[
  {
    "path": ".github/workflows/arduino_ci.yml",
    "content": "name: Arduino_CI\n\non:\n  push:\n    branches: [ master, develop ]\n  pull_request:\n    branches: [ master, develop ]\n\njobs:\n  arduino_ci:\n    runs-on: ubuntu-latest\n    strategy:\n      fail-fast: false\n    steps:\n      - uses: actions/checkout@v2\n      - name: install script\n        run: |\n          source <(curl -SLs https://raw.githubusercontent.com/ROBOTIS-GIT/OpenCR/master/install.sh) ${{github.ref}}\n          build_platform opencr"
  },
  {
    "path": ".gitignore",
    "content": "# Compiled Object files\n*.slo\n*.lo\n*.o\n\n# Precompiled Headers\n*.gch\n*.pch\n\n# Compiled Dynamic libraries\n*.so\n*.dylib\n*.dll\n\n# Fortran module files\n*.mod\n\n# Compiled Static libraries\n*.lai\n*.la\n*.a\n*.lib\n\n# Executables\n*.exe\n*.out\n*.app\n\n.vscode\n.metadata"
  },
  {
    "path": ".project",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<projectDescription>\n\t<name>OpenCR</name>\n\t<comment></comment>\n\t<projects>\n\t</projects>\n\t<buildSpec>\n\t</buildSpec>\n\t<natures>\n\t</natures>\n</projectDescription>\n"
  },
  {
    "path": "49-stlinkv2.rules",
    "content": "SUBSYSTEMS==\"usb\", ATTRS{idVendor}==\"0483\", ATTRS{idProduct}==\"3748\", MODE:=\"0666\", SYMLINK+=\"stlinkv2_%n\"\n"
  },
  {
    "path": "99-opencr-cdc.rules",
    "content": "#http://linux-tips.org/t/prevent-modem-manager-to-capture-usb-serial-devices/284/2.\n\n#cp rules /etc/udev/rules.d/\n#sudo udevadm control --reload-rules\n#sudo udevadm trigger\n\nATTRS{idVendor}==\"0483\" ATTRS{idProduct}==\"5740\", ENV{ID_MM_DEVICE_IGNORE}=\"1\", MODE:=\"0666\"\nATTRS{idVendor}==\"0483\" ATTRS{idProduct}==\"df11\", MODE:=\"0666\"\nATTRS{idVendor}==\"fff1\" ATTRS{idProduct}==\"ff48\", ENV{ID_MM_DEVICE_IGNORE}=\"1\", MODE:=\"0666\"\nATTRS{idVendor}==\"10c4\" ATTRS{idProduct}==\"ea60\", ENV{ID_MM_DEVICE_IGNORE}=\"1\", MODE:=\"0666\"\n"
  },
  {
    "path": "LICENSE",
    "content": "                                 Apache License\n                           Version 2.0, January 2004\n                        http://www.apache.org/licenses/\n\n   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION\n\n   1. Definitions.\n\n      \"License\" shall mean the terms and conditions for use, reproduction,\n      and distribution as defined by Sections 1 through 9 of this document.\n\n      \"Licensor\" shall mean the copyright owner or entity authorized by\n      the copyright owner that is granting the License.\n\n      \"Legal Entity\" shall mean the union of the acting entity and all\n      other entities that control, are controlled by, or are under common\n      control with that entity. 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The text should be enclosed in the appropriate\n      comment syntax for the file format. We also recommend that a\n      file or class name and description of purpose be included on the\n      same \"printed page\" as the copyright notice for easier\n      identification within third-party archives.\n\n   Copyright {yyyy} {name of copyright owner}\n\n   Licensed under the Apache License, Version 2.0 (the \"License\");\n   you may not use this file except in compliance with the License.\n   You may obtain a copy of the License at\n\n       http://www.apache.org/licenses/LICENSE-2.0\n\n   Unless required by applicable law or agreed to in writing, software\n   distributed under the License is distributed on an \"AS IS\" BASIS,\n   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n   See the License for the specific language governing permissions and\n   limitations under the License.\n"
  },
  {
    "path": "README.md",
    "content": "# OpenCR: Open Source Control Module for ROS [![Build Status](https://travis-ci.org/ROBOTIS-GIT/OpenCR.svg?branch=master)](https://travis-ci.org/ROBOTIS-GIT/OpenCR/)\n![](http://emanual.robotis.com/assets/images/parts/controller/opencr10/opencr_product.png)\n\n## ROBOTIS e-Manual for OpenCR\n- [ROBOTIS e-Manual for OpenCR](http://emanual.robotis.com/docs/en/parts/controller/opencr10/)\n\n## Open Source related to OpenCR\n- [Micro ROS Arduino](https://github.com/micro-ROS/micro_ros_arduino)\n- [OpenCR](https://github.com/ROBOTIS-GIT/OpenCR)\n- [OpenCR-Hardware](https://github.com/ROBOTIS-GIT/OpenCR-Hardware)\n- [OpenCM 9.04](https://github.com/ROBOTIS-GIT/OpenCM9.04)\n- [dynamixel_sdk](https://github.com/ROBOTIS-GIT/DynamixelSDK)\n- [turtlebot3](https://github.com/ROBOTIS-GIT/turtlebot3)\n- [open_manipulator](https://github.com/ROBOTIS-GIT/open_manipulator)\n- [robotis_op3](https://github.com/ROBOTIS-GIT/ROBOTIS-OP3)\n\n## Documents and Videos related to OpenCR\n- [ROBOTIS e-Manual for OpenCR](http://emanual.robotis.com/docs/en/parts/controller/opencr10/)\n- [ROBOTIS e-Manual for OpenCM 9.04](http://emanual.robotis.com/docs/en/parts/controller/opencm904/)\n- [ROBOTIS e-Manual for OpenCM 485 Expansion Board](http://emanual.robotis.com/docs/en/parts/controller/opencm485exp/)\n- [ROBOTIS e-Manual for Dynamixel SDK](http://emanual.robotis.com/docs/en/software/dynamixel/dynamixel_sdk/overview/)\n- [ROBOTIS e-Manual for TurtleBot3](http://turtlebot3.robotis.com/)\n- [ROBOTIS e-Manual for OpenManipulator](http://emanual.robotis.com/docs/en/platform/openmanipulator/)\n- [ROBOTIS e-Manual for ROBOTIS OP3](http://emanual.robotis.com/docs/en/platform/op3/introduction/)\n- [Videos for OpenCR](https://www.youtube.com/playlist?list=PLRG6WP3c31_VTd-u90LVXaT1B8NMjCSoj)\n\n## Repository folder structure description\n- arduino\n  - opencr_arduino\n    - libraries : A collection of some libraries that can be used with OpenCR.\n    - opencr : OpenCR package core to be installed in Arduino.\n    - tools : Tools for OpenCR firmware writing.\n  - opencr_develop\n    - opencr_bootloader : OpenCR bootloader source\n    - opencr_ld : OpenCR loader source (related bootloader)\n    - opencr_ld_shell : OpenCR loader script source for TB3\n  - opencr_release\n    - Folders(version name) : Compressed files for updating TB3 core binary with ld_shell for each TB3 core version.\n    - shell_update : Latest Compressed files for updating TB3 core binary with ld_shell.\n    - package_opencr_index.json : json file for Arduino OpenCR package.\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/.gitignore",
    "content": ".vscode\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/boards.txt",
    "content": "# OpenCR Boards\n#\nmenu.device_variant=Variant\nmenu.bootloader_version=Bootloader version\nmenu.upload_method=Upload method\n\nOpenCR.bootloader.tool = dfu_util\nOpenCR.bootloader.file = opencr_boot.bin\n\nOpenCR.name=OpenCR Board\nOpenCR.upload.maximum_size=786432\n\nOpenCR.upload.file_type=bin\nOpenCR.upload.ram.maximum_size=256788\nOpenCR.upload.flash.maximum_size=786432\nOpenCR.upload.params.quiet=no\n\nOpenCR.build.mcu=cortex-m7\nOpenCR.build.f_cpu=216000000L\nOpenCR.build.board=OpenCR\nOpenCR.build.core=arduino\nOpenCR.build.common_flags=-mthumb  -DSTM32F746xx -D__OPENCR__\n\nOpenCR.build.ldscript=bsp/opencr/ldscript/opencr_flash.ld\nOpenCR.build.variant=OpenCR\nOpenCR.build.variant_system_lib=lib_f746.a\nOpenCR.build.extra_flags=\n\n\nOpenCR.build.inc1=bsp/opencr\nOpenCR.build.inc2=bsp/opencr/include\nOpenCR.build.inc3=hw\nOpenCR.build.inc4=hw/driver\nOpenCR.build.inc5=hw/usb_cdc\nOpenCR.build.inc6=lib/STM32F7xx_HAL_Driver/Inc/\nOpenCR.build.inc7=\n\n#OpenCR.upload.tool=opencr_ld\n#OpenCR.menu.upload_method.upload.tool=opencr_ld\n\nOpenCR.menu.upload_method.UploadMethod=OpenCR Bootloader\nOpenCR.menu.upload_method.UploadMethod.upload.protocol=opencr_ld\nOpenCR.menu.upload_method.UploadMethod.upload.tool=opencr_ld\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/Arduino.h",
    "content": "/*\n  Arduino.h - Main include file for the Arduino SDK\n  Copyright (c) 2005-2013 Arduino Team.  All right reserved.\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n  Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n#ifndef Arduino_h\n#define Arduino_h\n\n#include <stdint.h>\n#include <stdlib.h>\n#include <string.h>\n#include <math.h>\n\n\n// some libraries and sketches depend on this\n// AVR stuff, assuming Arduino.h or WProgram.h\n// automatically includes it...\n#include <avr/pgmspace.h>\n#include <avr/interrupt.h>\n\n#include \"binary.h\"\n#include \"hw.h\"\n#include \"itoa.h\"\n\n#ifdef __cplusplus\nextern \"C\"{\n#endif // __cplusplus\n\n\n#include \"chip.h\"\n#include \"wiring_constants.h\"\n\n#define clockCyclesPerMicrosecond() ( SystemCoreClock / 1000000L )\n#define clockCyclesToMicroseconds(a) ( ((a) * 1000L) / (SystemCoreClock / 1000L) )\n#define microsecondsToClockCycles(a) ( (a) * (SystemCoreClock / 1000000L) )\n\nvoid yield(void);\n\n/* sketch */\nextern void setup( void ) ;\nextern void loop( void ) ;\n\n\n//#define NOT_A_PIN 0  // defined in pio.h/EPioType\n#define NOT_A_PORT           0\n\n#define NOT_AN_INTERRUPT -1\n\n\ntypedef void (*voidFuncPtr)( void ) ;\n\n/* Define attribute */\n#if defined   ( __CC_ARM   ) /* Keil uVision 4 */\n    #define WEAK (__attribute__ ((weak)))\n#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */\n    #define WEAK __weak\n#elif defined (  __GNUC__  ) /* GCC CS */\n    #define WEAK __attribute__ ((weak))\n#endif\n\n\n\n#ifdef __cplusplus\n} // extern \"C\"\n\n#include \"WCharacter.h\"\n#include \"WString.h\"\n#include \"Tone.h\"\n#include \"WMath.h\"\n#include \"HardwareSerial.h\"\n#include \"wiring_pulse.h\"\n\n#include \"variant.h\"\n\nvoid tone(uint8_t _pin, unsigned int frequency, unsigned long duration = 0);\nvoid noTone(uint8_t _pin);\n\n#endif // __cplusplus\n\n\n#include \"wiring.h\"\n#include \"wiring_digital.h\"\n#include \"wiring_analog.h\"\n#include \"wiring_shift.h\"\n#include \"WInterrupts.h\"\n#include \"digitalWriteFast.h\"\n#endif // Arduino_h\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/Client.h",
    "content": "/*\n  Client.h - Base class that provides Client\n  Copyright (c) 2011 Adrian McEwen.  All right reserved.\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n  Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n#ifndef client_h\n#define client_h\n#include \"Print.h\"\n#include \"Stream.h\"\n#include \"IPAddress.h\"\n\nclass Client : public Stream {\n\npublic:\n  virtual int connect(IPAddress ip, uint16_t port) =0;\n  virtual int connect(const char *host, uint16_t port) =0;\n  virtual size_t write(uint8_t) =0;\n  virtual size_t write(const uint8_t *buf, size_t size) =0;\n  virtual int available() = 0;\n  virtual int read() = 0;\n  virtual int read(uint8_t *buf, size_t size) = 0;\n  virtual int peek() = 0;\n  virtual void flush() = 0;\n  virtual void stop() = 0;\n  virtual uint8_t connected() = 0;\n  virtual operator bool() = 0;\nprotected:\n  uint8_t* rawIPAddress(IPAddress& addr) { return addr.raw_address(); };\n};\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/HardwareSerial.h",
    "content": "/*\n  Copyright (c) 2011 Arduino.  All right reserved.\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. \n  See the GNU Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n#ifndef HardwareSerial_h\n#define HardwareSerial_h\n\n#include <inttypes.h>\n\n#include \"Stream.h\"\n\nclass HardwareSerial : public Stream\n{\n  public:\n    virtual void begin(unsigned long) = 0;\n    virtual void end() = 0;\n    virtual int available(void) = 0;\n    virtual int peek(void) = 0;\n    virtual int read(void) = 0;\n    virtual void flush(void) = 0;\n    virtual size_t write(uint8_t) = 0;\n    using Print::write; // pull in write(str) and write(buf, size) from Print\n    virtual operator bool() = 0;\n};\n\nextern void serialEventRun(void) __attribute__((weak));\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/HardwareTimer.cpp",
    "content": "/******************************************************************************\n * The MIT License\n *\n * Copyright (c) 2010 Bryan Newbold.\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without\n * restriction, including without limitation the rights to use, copy,\n * modify, merge, publish, distribute, sublicense, and/or sell copies\n * of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n * SOFTWARE.\n *****************************************************************************/\n\n#include  <chip.h>\n\n#include <USBSerial.h>\n#include \"drv_timer.h\"\n#include \"variant.h\"\n#include \"HardwareTimer.h\"\n\n\n#define MAX_RELOAD ((1 << 16) - 1)\n\nHardwareTimer::HardwareTimer(uint8_t timerNum) {\n  if (timerNum > TIMER_CH_MAX) {\n    tim_num = 0;\n  }\n\n  tim_num = timerNum;\n}\n\nvoid HardwareTimer::pause(void) {\n  drv_timer_pause(tim_num);\n}\n\nvoid HardwareTimer::resume(void) {\n  drv_timer_resume(tim_num);\n}\n\nvoid HardwareTimer::stop(void) {\n  drv_timer_pause(tim_num);\n}\n\nvoid HardwareTimer::start(void) {\n  drv_timer_resume(tim_num);\n}\n\nuint16_t HardwareTimer::setPeriod(uint32_t microseconds) {\n\n  drv_timer_set_period(tim_num, microseconds);\n\n  return 0;\n}\n\nvoid HardwareTimer::attachInterrupt(voidFuncPtr handler) {\n  drv_timer_attachInterrupt(tim_num, handler);\n}\n\nvoid HardwareTimer::detachInterrupt(void) {\n    drv_timer_detachInterrupt(tim_num);\n}\n\nvoid HardwareTimer::refresh(void) {\n    drv_timer_refresh(tim_num);\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/HardwareTimer.h",
    "content": "/******************************************************************************\n * The MIT License\n *\n * Copyright (c) 2010 Bryan Newbold.\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without\n * restriction, including without limitation the rights to use, copy,\n * modify, merge, publish, distribute, sublicense, and/or sell copies\n * of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n * SOFTWARE.\n *****************************************************************************/\n\n\n#ifndef _HARDWARETIMER_H_\n#define _HARDWARETIMER_H_\n\n#include <inttypes.h>\n\n\n\n\n\nclass HardwareTimer {\nprivate:\n    uint8_t tim_num;\npublic:\n    HardwareTimer(uint8_t timerNum);\n\n    void pause(void);\n    void resume(void);\n    void stop(void);\n    void start(void);\n    uint16_t setPeriod(uint32_t microseconds);\n    void attachInterrupt(voidFuncPtr handler);\n    void detachInterrupt(void);\n    void refresh(void);\n};\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/IPAddress.cpp",
    "content": "/*\n  IPAddress.cpp - Base class that provides IPAddress\n  Copyright (c) 2011 Adrian McEwen.  All right reserved.\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n  Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n#include <Arduino.h>\n#include <IPAddress.h>\n\nIPAddress::IPAddress()\n{\n    _address.dword = 0;\n}\n\nIPAddress::IPAddress(uint8_t first_octet, uint8_t second_octet, uint8_t third_octet, uint8_t fourth_octet)\n{\n    _address.bytes[0] = first_octet;\n    _address.bytes[1] = second_octet;\n    _address.bytes[2] = third_octet;\n    _address.bytes[3] = fourth_octet;\n}\n\nIPAddress::IPAddress(uint32_t address)\n{\n    _address.dword = address;\n}\n\nIPAddress::IPAddress(const uint8_t *address)\n{\n    memcpy(_address.bytes, address, sizeof(_address.bytes));\n}\n\nbool IPAddress::fromString(const char *address)\n{\n    uint16_t acc = 0; // Accumulator\n    uint8_t dots = 0;\n\n    while (*address)\n    {\n        char c = *address++;\n        if (c >= '0' && c <= '9')\n        {\n            acc = acc * 10 + (c - '0');\n            if (acc > 255) {\n                // Value out of [0..255] range\n                return false;\n            }\n        }\n        else if (c == '.')\n        {\n            if (dots == 3) {\n                // Too much dots (there must be 3 dots)\n                return false;\n            }\n            _address.bytes[dots++] = acc;\n            acc = 0;\n        }\n        else\n        {\n            // Invalid char\n            return false;\n        }\n    }\n\n    if (dots != 3) {\n        // Too few dots (there must be 3 dots)\n        return false;\n    }\n    _address.bytes[3] = acc;\n    return true;\n}\n\nIPAddress& IPAddress::operator=(const uint8_t *address)\n{\n    memcpy(_address.bytes, address, sizeof(_address.bytes));\n    return *this;\n}\n\nIPAddress& IPAddress::operator=(uint32_t address)\n{\n    _address.dword = address;\n    return *this;\n}\n\nbool IPAddress::operator==(const uint8_t* addr) const\n{\n    return memcmp(addr, _address.bytes, sizeof(_address.bytes)) == 0;\n}\n\nsize_t IPAddress::printTo(Print& p) const\n{\n    size_t n = 0;\n    for (int i =0; i < 3; i++)\n    {\n        n += p.print(_address.bytes[i], DEC);\n        n += p.print('.');\n    }\n    n += p.print(_address.bytes[3], DEC);\n    return n;\n}\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/IPAddress.h",
    "content": "/*\n  IPAddress.h - Base class that provides IPAddress\n  Copyright (c) 2011 Adrian McEwen.  All right reserved.\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n  Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n#ifndef IPAddress_h\n#define IPAddress_h\n\n#include <stdint.h>\n#include \"Printable.h\"\n#include \"WString.h\"\n\n// A class to make it easier to handle and pass around IP addresses\n\nclass IPAddress : public Printable {\nprivate:\n    union {\n\tuint8_t bytes[4];  // IPv4 address\n\tuint32_t dword;\n    } _address;\n\n    // Access the raw byte array containing the address.  Because this returns a pointer\n    // to the internal structure rather than a copy of the address this function should only\n    // be used when you know that the usage of the returned uint8_t* will be transient and not\n    // stored.\n    uint8_t* raw_address() { return _address.bytes; };\n\npublic:\n    // Constructors\n    IPAddress();\n    IPAddress(uint8_t first_octet, uint8_t second_octet, uint8_t third_octet, uint8_t fourth_octet);\n    IPAddress(uint32_t address);\n    IPAddress(const uint8_t *address);\n\n    bool fromString(const char *address);\n    bool fromString(const String &address) { return fromString(address.c_str()); }\n\n    // Overloaded cast operator to allow IPAddress objects to be used where a pointer\n    // to a four-byte uint8_t array is expected\n    operator uint32_t() const { return _address.dword; };\n    bool operator==(const IPAddress& addr) const { return _address.dword == addr._address.dword; };\n    bool operator==(const uint8_t* addr) const;\n\n    // Overloaded index operator to allow getting and setting individual octets of the address\n    uint8_t operator[](int index) const { return _address.bytes[index]; };\n    uint8_t& operator[](int index) { return _address.bytes[index]; };\n\n    // Overloaded copy operators to allow initialisation of IPAddress objects from other types\n    IPAddress& operator=(const uint8_t *address);\n    IPAddress& operator=(uint32_t address);\n\n    virtual size_t printTo(Print& p) const;\n\n    friend class EthernetClass;\n    friend class UDP;\n    friend class Client;\n    friend class Server;\n    friend class DhcpClass;\n    friend class DNSClient;\n};\n\nconst IPAddress INADDR_NONE(0,0,0,0);\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/Print.cpp",
    "content": "/*\r\n Print.cpp - Base class that provides print() and println()\r\n Copyright (c) 2008 David A. Mellis.  All right reserved.\r\n\r\n This library is free software; you can redistribute it and/or\r\n modify it under the terms of the GNU Lesser General Public\r\n License as published by the Free Software Foundation; either\r\n version 2.1 of the License, or (at your option) any later version.\r\n\r\n This library is distributed in the hope that it will be useful,\r\n but WITHOUT ANY WARRANTY; without even the implied warranty of\r\n MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\r\n Lesser General Public License for more details.\r\n\r\n You should have received a copy of the GNU Lesser General Public\r\n License along with this library; if not, write to the Free Software\r\n Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\r\n\r\n Modified 23 November 2006 by David A. Mellis\r\n */\r\n\r\n#include <stdlib.h>\r\n#include <stdio.h>\r\n#include <string.h>\r\n#include <stdarg.h>\r\n#include <math.h>\r\n#include \"Arduino.h\"\r\n\r\n#include \"Print.h\"\r\n\r\n// Public Methods //////////////////////////////////////////////////////////////\r\n\r\n/* default implementation: may be overridden */\r\nsize_t Print::write(const uint8_t *buffer, size_t size)\r\n{\r\n  size_t n = 0;\r\n  while (size--) {\r\n    n += write(*buffer++);\r\n  }\r\n  return n;\r\n}\r\n\r\nsize_t Print::print(const __FlashStringHelper *ifsh)\r\n{\r\n  return print(reinterpret_cast<const char *>(ifsh));\r\n}\r\n\r\nsize_t Print::print(const String &s)\r\n{\r\n  return write(s.c_str(), s.length());\r\n}\r\n\r\nsize_t Print::print(const char str[])\r\n{\r\n  return write(str);\r\n}\r\n\r\nsize_t Print::print(char c)\r\n{\r\n  return write(c);\r\n}\r\n\r\nsize_t Print::print(unsigned char b, int base)\r\n{\r\n  return print((unsigned long) b, base);\r\n}\r\n\r\nsize_t Print::print(int n, int base)\r\n{\r\n  return print((long) n, base);\r\n}\r\n\r\nsize_t Print::print(unsigned int n, int base)\r\n{\r\n  return print((unsigned long) n, base);\r\n}\r\n\r\nsize_t Print::print(long n, int base)\r\n{\r\n  if (base == 0) {\r\n    return write(n);\r\n  } else if (base == 10) {\r\n    if (n < 0) {\r\n      int t = print('-');\r\n      n = -n;\r\n      return printNumber(n, 10) + t;\r\n    }\r\n    return printNumber(n, 10);\r\n  } else {\r\n    return printNumber(n, base);\r\n  }\r\n}\r\n\r\nsize_t Print::print(unsigned long n, int base)\r\n{\r\n  if (base == 0) return write(n);\r\n  else return printNumber(n, base);\r\n}\r\n\r\nsize_t Print::print(double n, int digits)\r\n{\r\n  return printFloat(n, digits);\r\n}\r\n\r\nsize_t Print::println(const __FlashStringHelper *ifsh)\r\n{\r\n  size_t n = print(ifsh);\r\n  n += println();\r\n  return n;\r\n}\r\n\r\nsize_t Print::print(const Printable& x)\r\n{\r\n  return x.printTo(*this);\r\n}\r\n\r\nsize_t Print::println(void)\r\n{\r\n  size_t n = print('\\r');\r\n  n += print('\\n');\r\n  return n;\r\n}\r\n\r\nsize_t Print::println(const String &s)\r\n{\r\n  size_t n = print(s);\r\n  n += println();\r\n  return n;\r\n}\r\n\r\nsize_t Print::println(const char c[])\r\n{\r\n  size_t n = print(c);\r\n  n += println();\r\n  return n;\r\n}\r\n\r\nsize_t Print::println(char c)\r\n{\r\n  size_t n = print(c);\r\n  n += println();\r\n  return n;\r\n}\r\n\r\nsize_t Print::println(unsigned char b, int base)\r\n{\r\n  size_t n = print(b, base);\r\n  n += println();\r\n  return n;\r\n}\r\n\r\nsize_t Print::println(int num, int base)\r\n{\r\n  size_t n = print(num, base);\r\n  n += println();\r\n  return n;\r\n}\r\n\r\nsize_t Print::println(unsigned int num, int base)\r\n{\r\n  size_t n = print(num, base);\r\n  n += println();\r\n  return n;\r\n}\r\n\r\nsize_t Print::println(long num, int base)\r\n{\r\n  size_t n = print(num, base);\r\n  n += println();\r\n  return n;\r\n}\r\n\r\nsize_t Print::println(unsigned long num, int base)\r\n{\r\n  size_t n = print(num, base);\r\n  n += println();\r\n  return n;\r\n}\r\n\r\nsize_t Print::println(double num, int digits)\r\n{\r\n  size_t n = print(num, digits);\r\n  n += println();\r\n  return n;\r\n}\r\n\r\nsize_t Print::println(const Printable& x)\r\n{\r\n  size_t n = print(x);\r\n  n += println();\r\n  return n;\r\n}\r\n\r\nsize_t Print::printf(const char *fmt, ... )\r\n{\r\n  char buf[256]; // resulting string limited to 128 chars\r\n  char buf_out[256];\r\n  va_list args;\r\n  size_t i;\r\n  int i_out;\r\n\r\n\r\n  va_start (args, fmt );\r\n  vsnprintf(buf, 256, fmt, args);\r\n  va_end (args);\r\n\r\n  i_out = 0;\r\n  for( i=0; i<strlen(buf); i++ )\r\n  {\r\n    if( buf[i] == '\\n' )\r\n    {\r\n      buf_out[i_out++] = '\\r';\r\n      buf_out[i_out++] = '\\n';\r\n    }\r\n    else\r\n    {\r\n      buf_out[i_out++] = buf[i];\r\n    }\r\n  }\r\n  buf_out[i_out] = 0;\r\n\r\n  return write(buf_out, i_out);\r\n}\r\n\r\n\r\n// Private Methods /////////////////////////////////////////////////////////////\r\n\r\nsize_t Print::printNumber(unsigned long n, uint8_t base) {\r\n  char buf[8 * sizeof(long) + 1]; // Assumes 8-bit chars plus zero byte.\r\n  char *str = &buf[sizeof(buf) - 1];\r\n\r\n  *str = '\\0';\r\n\r\n  // prevent crash if called with base == 1\r\n  if (base < 2) base = 10;\r\n\r\n  do {\r\n    unsigned long m = n;\r\n    n /= base;\r\n    char c = m - base * n;\r\n    *--str = c < 10 ? c + '0' : c + 'A' - 10;\r\n  } while(n);\r\n\r\n  return write(str);\r\n}\r\n\r\nsize_t Print::printFloat(double number, uint8_t digits)\r\n{\r\n  size_t n = 0;\r\n\r\n  if (isnan(number)) return print(\"nan\");\r\n  if (isinf(number)) return print(\"inf\");\r\n  if (number > 4294967040.0) return print (\"ovf\");  // constant determined empirically\r\n  if (number <-4294967040.0) return print (\"ovf\");  // constant determined empirically\r\n\r\n  // Handle negative numbers\r\n  if (number < 0.0)\r\n  {\r\n     n += print('-');\r\n     number = -number;\r\n  }\r\n\r\n  // Round correctly so that print(1.999, 2) prints as \"2.00\"\r\n  double rounding = 0.5;\r\n  for (uint8_t i=0; i<digits; ++i)\r\n    rounding /= 10.0;\r\n\r\n  number += rounding;\r\n\r\n  // Extract the integer part of the number and print it\r\n  unsigned long int_part = (unsigned long)number;\r\n  double remainder = number - (double)int_part;\r\n  n += print(int_part);\r\n\r\n  // Print the decimal point, but only if there are digits beyond\r\n  if (digits > 0) {\r\n    n += print(\".\");\r\n  }\r\n\r\n  // Extract digits from the remainder one at a time\r\n  while (digits-- > 0)\r\n  {\r\n    remainder *= 10.0;\r\n    int toPrint = int(remainder);\r\n    n += print(toPrint);\r\n    remainder -= toPrint;\r\n  }\r\n\r\n  return n;\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/Print.h",
    "content": "/*\n  Print.h - Base class that provides print() and println()\n  Copyright (c) 2008 David A. Mellis.  All right reserved.\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n  Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n#ifndef Print_h\n#define Print_h\n\n#include <inttypes.h>\n#include <stdio.h> // for size_t\n#include <stdarg.h>\n\n#include \"WString.h\"\n#include \"Printable.h\"\n\n#define DEC 10\n#define HEX 16\n#define OCT 8\n#define BIN 2\n\nclass Print\n{\n  private:\n    int write_error;\n    size_t printNumber(unsigned long, uint8_t);\n    size_t printFloat(double, uint8_t);\n  protected:\n    void setWriteError(int err = 1) { write_error = err; }\n  public:\n    Print() : write_error(0) {}\n\n    int getWriteError() { return write_error; }\n    void clearWriteError() { setWriteError(0); }\n\n    virtual size_t write(uint8_t) = 0;\n    size_t write(const char *str) {\n      if (str == NULL) return 0;\n      return write((const uint8_t *)str, strlen(str));\n    }\n    virtual size_t write(const uint8_t *buffer, size_t size);\n    size_t write(const char *buffer, size_t size) {\n      return write((const uint8_t *)buffer, size);\n    }\n\n    size_t print(const __FlashStringHelper *);\n    size_t print(const String &);\n    size_t print(const char[]);\n    size_t print(char);\n    size_t print(unsigned char, int = DEC);\n    size_t print(int, int = DEC);\n    size_t print(unsigned int, int = DEC);\n    size_t print(long, int = DEC);\n    size_t print(unsigned long, int = DEC);\n    size_t print(double, int = 2);\n    size_t print(const Printable&);\n\n    size_t println(const __FlashStringHelper *);\n    size_t println(const String &s);\n    size_t println(const char[]);\n    size_t println(char);\n    size_t println(unsigned char, int = DEC);\n    size_t println(int, int = DEC);\n    size_t println(unsigned int, int = DEC);\n    size_t println(long, int = DEC);\n    size_t println(unsigned long, int = DEC);\n    size_t println(double, int = 2);\n    size_t println(const Printable&);\n    size_t println(void);\n\n    size_t printf(const char *fmt, ... );\n\n};\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/Printable.h",
    "content": "/*\n  Printable.h - Interface class that allows printing of complex types\n  Copyright (c) 2011 Adrian McEwen.  All right reserved.\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n  Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n#ifndef Printable_h\n#define Printable_h\n\n#include <stdlib.h>\n\nclass Print;\n\n/** The Printable class provides a way for new classes to allow themselves to be printed.\n    By deriving from Printable and implementing the printTo method, it will then be possible\n    for users to print out instances of this class by passing them into the usual\n    Print::print and Print::println methods.\n*/\n\nclass Printable\n{\n  public:\n    virtual size_t printTo(Print& p) const = 0;\n};\n\n#endif\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/Reset.h",
    "content": "/*\n  Copyright (c) 2012 Arduino.  All right reserved.\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n  See the GNU Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n#ifndef RESET_H\n#define RESET_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\nvoid initiateReset(int ms);\nvoid tickReset();\nvoid cancelReset();\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/RingBuffer.cpp",
    "content": "/*\r\n  Copyright (c) 2011 Arduino.  All right reserved.\r\n\r\n  This library is free software; you can redistribute it and/or\r\n  modify it under the terms of the GNU Lesser General Public\r\n  License as published by the Free Software Foundation; either\r\n  version 2.1 of the License, or (at your option) any later version.\r\n\r\n  This library is distributed in the hope that it will be useful,\r\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\r\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. \r\n  See the GNU Lesser General Public License for more details.\r\n\r\n  You should have received a copy of the GNU Lesser General Public\r\n  License along with this library; if not, write to the Free Software\r\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\r\n*/\r\n\r\n#include \"RingBuffer.h\"\r\n#include <string.h>\r\n\r\nRingBuffer::RingBuffer( void )\r\n{\r\n    memset( (void *)_aucBuffer, 0, RING_BUFFER_SIZE ) ;\r\n    _iHead=0 ;\r\n    _iTail=0 ;\r\n}\r\n\r\nvoid RingBuffer::store_char( uint8_t c )\r\n{\r\n  int i = (uint32_t)(_iHead + 1) % RING_BUFFER_SIZE ;\r\n\r\n  // if we should be storing the received character into the location\r\n  // just before the tail (meaning that the head would advance to the\r\n  // current location of the tail), we're about to overflow the buffer\r\n  // and so we don't write the character or advance the head.\r\n  if ( i != _iTail )\r\n  {\r\n    _aucBuffer[_iHead] = c ;\r\n    _iHead = i ;\r\n  }\r\n}\r\n\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/RingBuffer.h",
    "content": "/*\r\n  Copyright (c) 2011 Arduino.  All right reserved.\r\n\r\n  This library is free software; you can redistribute it and/or\r\n  modify it under the terms of the GNU Lesser General Public\r\n  License as published by the Free Software Foundation; either\r\n  version 2.1 of the License, or (at your option) any later version.\r\n\r\n  This library is distributed in the hope that it will be useful,\r\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\r\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. \r\n  See the GNU Lesser General Public License for more details.\r\n\r\n  You should have received a copy of the GNU Lesser General Public\r\n  License along with this library; if not, write to the Free Software\r\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\r\n*/\r\n\r\n#ifndef _RING_BUFFER_\r\n#define _RING_BUFFER_\r\n\r\n#include <stdint.h>\r\n\r\n// Define constants and variables for buffering incoming serial data.  We're\r\n// using a ring buffer (I think), in which head is the index of the location\r\n// to which to write the next incoming character and tail is the index of the\r\n// location from which to read.\r\n#define RING_BUFFER_SIZE 128\r\n\r\nclass RingBuffer\r\n{\r\n  public:\r\n    volatile uint8_t _aucBuffer[RING_BUFFER_SIZE] ;\r\n    volatile int _iHead ;\r\n    volatile int _iTail ;\r\n\r\n  public:\r\n    RingBuffer( void ) ;\r\n    void store_char( uint8_t c ) ;\r\n} ;\r\n\r\n#endif /* _RING_BUFFER_ */\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/Server.h",
    "content": "/*\n  Server.h - Base class that provides Server\n  Copyright (c) 2011 Adrian McEwen.  All right reserved.\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n  Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n#ifndef server_h\n#define server_h\n\n#include \"Print.h\"\n\nclass Server : public Print {\npublic:\n  virtual void begin() =0;\n};\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/Stream.cpp",
    "content": "/*\r\n Stream.cpp - adds parsing methods to Stream class\r\n Copyright (c) 2008 David A. Mellis.  All right reserved.\r\n\r\n This library is free software; you can redistribute it and/or\r\n modify it under the terms of the GNU Lesser General Public\r\n License as published by the Free Software Foundation; either\r\n version 2.1 of the License, or (at your option) any later version.\r\n\r\n This library is distributed in the hope that it will be useful,\r\n but WITHOUT ANY WARRANTY; without even the implied warranty of\r\n MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\r\n Lesser General Public License for more details.\r\n\r\n You should have received a copy of the GNU Lesser General Public\r\n License along with this library; if not, write to the Free Software\r\n Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\r\n\r\n Created July 2011\r\n parsing functions based on TextFinder library by Michael Margolis\r\n\r\n findMulti/findUntil routines written by Jim Leonard/Xuth\r\n */\r\n\r\n#include \"Arduino.h\"\r\n#include \"Stream.h\"\r\n\r\n#define PARSE_TIMEOUT 1000  // default number of milli-seconds to wait\r\n#define NO_SKIP_CHAR  1  // a magic char not found in a valid ASCII numeric field\r\n\r\n// private method to read stream with timeout\r\nint Stream::timedRead()\r\n{\r\n  int c;\r\n  _startMillis = millis();\r\n  do {\r\n    c = read();\r\n    if (c >= 0) return c;\r\n  } while(millis() - _startMillis < _timeout);\r\n  return -1;     // -1 indicates timeout\r\n}\r\n\r\n// private method to peek stream with timeout\r\nint Stream::timedPeek()\r\n{\r\n  int c;\r\n  _startMillis = millis();\r\n  do {\r\n    c = peek();\r\n    if (c >= 0) return c;\r\n  } while(millis() - _startMillis < _timeout);\r\n  return -1;     // -1 indicates timeout\r\n}\r\n\r\n// returns peek of the next digit in the stream or -1 if timeout\r\n// discards non-numeric characters\r\nint Stream::peekNextDigit()\r\n{\r\n  int c;\r\n  while (1) {\r\n    c = timedPeek();\r\n    if (c < 0) return c;  // timeout\r\n    if (c == '-') return c;\r\n    if (c >= '0' && c <= '9') return c;\r\n    read();  // discard non-numeric\r\n  }\r\n}\r\n\r\n// Public Methods\r\n//////////////////////////////////////////////////////////////\r\n\r\nvoid Stream::setTimeout(unsigned long timeout)  // sets the maximum number of milliseconds to wait\r\n{\r\n  _timeout = timeout;\r\n}\r\n\r\n // find returns true if the target string is found\r\nbool  Stream::find(char *target)\r\n{\r\n  return findUntil(target, strlen(target), NULL, 0);\r\n}\r\n\r\n// reads data from the stream until the target string of given length is found\r\n// returns true if target string is found, false if timed out\r\nbool Stream::find(char *target, size_t length)\r\n{\r\n  return findUntil(target, length, NULL, 0);\r\n}\r\n\r\n// as find but search ends if the terminator string is found\r\nbool  Stream::findUntil(char *target, char *terminator)\r\n{\r\n  return findUntil(target, strlen(target), terminator, strlen(terminator));\r\n}\r\n\r\n// reads data from the stream until the target string of the given length is found\r\n// search terminated if the terminator string is found\r\n// returns true if target string is found, false if terminated or timed out\r\nbool Stream::findUntil(char *target, size_t targetLen, char *terminator, size_t termLen)\r\n{\r\n  if (terminator == NULL) {\r\n    MultiTarget t[1] = {{target, targetLen, 0}};\r\n    return findMulti(t, 1) == 0 ? true : false;\r\n  } else {\r\n    MultiTarget t[2] = {{target, targetLen, 0}, {terminator, termLen, 0}};\r\n    return findMulti(t, 2) == 0 ? true : false;\r\n  }\r\n}\r\n\r\n\r\n// returns the first valid (long) integer value from the current position.\r\n// initial characters that are not digits (or the minus sign) are skipped\r\n// function is terminated by the first character that is not a digit.\r\nlong Stream::parseInt()\r\n{\r\n  return parseInt(NO_SKIP_CHAR); // terminate on first non-digit character (or timeout)\r\n}\r\n\r\n// as above but a given skipChar is ignored\r\n// this allows format characters (typically commas) in values to be ignored\r\nlong Stream::parseInt(char skipChar)\r\n{\r\n  bool isNegative = false;\r\n  long value = 0;\r\n  int c;\r\n\r\n  c = peekNextDigit();\r\n  // ignore non numeric leading characters\r\n  if(c < 0)\r\n    return 0; // zero returned if timeout\r\n\r\n  do{\r\n    if(c == skipChar)\r\n      ; // ignore this charactor\r\n    else if(c == '-')\r\n      isNegative = true;\r\n    else if(c >= '0' && c <= '9')        // is c a digit?\r\n      value = value * 10 + c - '0';\r\n    read();  // consume the character we got with peek\r\n    c = timedPeek();\r\n  }\r\n  while( (c >= '0' && c <= '9') || c == skipChar );\r\n\r\n  if(isNegative)\r\n    value = -value;\r\n  return value;\r\n}\r\n\r\n\r\n// as parseInt but returns a floating point value\r\nfloat Stream::parseFloat()\r\n{\r\n  return parseFloat(NO_SKIP_CHAR);\r\n}\r\n\r\n// as above but the given skipChar is ignored\r\n// this allows format characters (typically commas) in values to be ignored\r\nfloat Stream::parseFloat(char skipChar){\r\n  bool isNegative = false;\r\n  bool isFraction = false;\r\n  long value = 0;\r\n  int c;//char c;\r\n  float fraction = 1.0;\r\n\r\n  c = peekNextDigit();\r\n    // ignore non numeric leading characters\r\n  if(c < 0)\r\n    return 0; // zero returned if timeout\r\n\r\n  do{\r\n    if(c == skipChar)\r\n      ; // ignore\r\n    else if(c == '-')\r\n      isNegative = true;\r\n    else if (c == '.')\r\n      isFraction = true;\r\n    else if(c >= '0' && c <= '9')  {      // is c a digit?\r\n      value = value * 10 + c - '0';\r\n      if(isFraction)\r\n         fraction *= 0.1;\r\n    }\r\n    read();  // consume the character we got with peek\r\n    c = timedPeek();\r\n  }\r\n  while( (c >= '0' && c <= '9')  || c == '.' || c == skipChar );\r\n\r\n  if(isNegative)\r\n    value = -value;\r\n  if(isFraction)\r\n    return value * fraction;\r\n  else\r\n    return value;\r\n}\r\n\r\n// read characters from stream into buffer\r\n// terminates if length characters have been read, or timeout (see setTimeout)\r\n// returns the number of characters placed in the buffer\r\n// the buffer is NOT null terminated.\r\n//\r\nsize_t Stream::readBytes(char *buffer, size_t length)\r\n{\r\n  size_t count = 0;\r\n  while (count < length) {\r\n    int c = timedRead();\r\n    if (c < 0) break;\r\n    *buffer++ = (char)c;\r\n    count++;\r\n  }\r\n  return count;\r\n}\r\n\r\n\r\n// as readBytes with terminator character\r\n// terminates if length characters have been read, timeout, or if the terminator character  detected\r\n// returns the number of characters placed in the buffer (0 means no valid data found)\r\n\r\nsize_t Stream::readBytesUntil(char terminator, char *buffer, size_t length)\r\n{\r\n  if (length < 1) return 0;\r\n  size_t index = 0;\r\n  while (index < length) {\r\n    int c = timedRead();\r\n    if (c < 0 || c == terminator) break;\r\n    *buffer++ = (char)c;\r\n    index++;\r\n  }\r\n  return index; // return number of characters, not including null terminator\r\n}\r\n\r\nString Stream::readString()\r\n{\r\n  String ret;\r\n  int c = timedRead();\r\n  while (c >= 0)\r\n  {\r\n    ret += (char)c;\r\n    c = timedRead();\r\n  }\r\n  return ret;\r\n}\r\n\r\nString Stream::readStringUntil(char terminator)\r\n{\r\n  String ret;\r\n  int c = timedRead();\r\n  while (c >= 0 && c != terminator)\r\n  {\r\n    ret += (char)c;\r\n    c = timedRead();\r\n  }\r\n  return ret;\r\n}\r\n\r\nint Stream::findMulti( struct Stream::MultiTarget *targets, int tCount) {\r\n  // any zero length target string automatically matches and would make\r\n  // a mess of the rest of the algorithm.\r\n  for (struct MultiTarget *t = targets; t < targets+tCount; ++t) {\r\n    if (t->len <= 0)\r\n      return t - targets;\r\n  }\r\n\r\n  while (1) {\r\n    int c = timedRead();\r\n    if (c < 0)\r\n      return -1;\r\n\r\n    for (struct MultiTarget *t = targets; t < targets+tCount; ++t) {\r\n      // the simple case is if we match, deal with that first.\r\n      if (c == t->str[t->index]) {\r\n        if (++t->index == t->len)\r\n          return t - targets;\r\n        else\r\n          continue;\r\n      }\r\n\r\n      // if not we need to walk back and see if we could have matched further\r\n      // down the stream (ie '1112' doesn't match the first position in '11112'\r\n      // but it will match the second position so we can't just reset the current\r\n      // index to 0 when we find a mismatch.\r\n      if (t->index == 0)\r\n        continue;\r\n\r\n      int origIndex = t->index;\r\n      do {\r\n        --t->index;\r\n        // first check if current char works against the new current index\r\n        if (c != t->str[t->index])\r\n          continue;\r\n\r\n        // if it's the only char then we're good, nothing more to check\r\n        if (t->index == 0) {\r\n          t->index++;\r\n          break;\r\n        }\r\n\r\n        // otherwise we need to check the rest of the found string\r\n        int diff = origIndex - t->index;\r\n        size_t i;\r\n        for (i = 0; i < t->index; ++i) {\r\n          if (t->str[i] != t->str[i + diff])\r\n            break;\r\n        }\r\n\r\n        // if we successfully got through the previous loop then our current\r\n        // index is good.\r\n        if (i == t->index) {\r\n          t->index++;\r\n          break;\r\n        }\r\n\r\n        // otherwise we just try the next index\r\n      } while (t->index);\r\n    }\r\n  }\r\n  // unreachable\r\n  return -1;\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/Stream.h",
    "content": "/*\n  Stream.h - base class for character-based streams.\n  Copyright (c) 2010 David A. Mellis.  All right reserved.\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n  Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n\n  parsing functions based on TextFinder library by Michael Margolis\n*/\n\n#ifndef Stream_h\n#define Stream_h\n\n#include <inttypes.h>\n#include \"Print.h\"\n\n// compatability macros for testing\n/*\n#define   getInt()            parseInt()\n#define   getInt(skipChar)    parseInt(skipchar)\n#define   getFloat()          parseFloat()\n#define   getFloat(skipChar)  parseFloat(skipChar)\n#define   getString( pre_string, post_string, buffer, length)\nreadBytesBetween( pre_string, terminator, buffer, length)\n*/\n\nclass Stream : public Print\n{\n  protected:\n    unsigned long _timeout;      // number of milliseconds to wait for the next char before aborting timed read\n    unsigned long _startMillis;  // used for timeout measurement\n    int timedRead();    // private method to read stream with timeout\n    int timedPeek();    // private method to peek stream with timeout\n    int peekNextDigit(); // returns the next numeric digit in the stream or -1 if timeout\n\n  public:\n    virtual int available() = 0;\n    virtual int read() = 0;\n    virtual int peek() = 0;\n    virtual void flush() = 0;\n\n    Stream() {_timeout=1000;}\n\n// parsing methods\n\n  void setTimeout(unsigned long timeout);  // sets maximum milliseconds to wait for stream data, default is 1 second\n\n  bool find(char *target);   // reads data from the stream until the target string is found\n  bool find(uint8_t *target) { return find ((char *)target); }\n  // returns true if target string is found, false if timed out (see setTimeout)\n\n  bool find(char *target, size_t length);   // reads data from the stream until the target string of given length is found\n  bool find(uint8_t *target, size_t length) { return find ((char *)target, length); }\n  // returns true if target string is found, false if timed out\n\n  bool findUntil(char *target, char *terminator);   // as find but search ends if the terminator string is found\n  bool findUntil(uint8_t *target, char *terminator) { return findUntil((char *)target, terminator); }\n\n  bool findUntil(char *target, size_t targetLen, char *terminate, size_t termLen);   // as above but search ends if the terminate string is found\n  bool findUntil(uint8_t *target, size_t targetLen, char *terminate, size_t termLen) {return findUntil((char *)target, targetLen, terminate, termLen); }\n\n\n  long parseInt(); // returns the first valid (long) integer value from the current position.\n  // initial characters that are not digits (or the minus sign) are skipped\n  // integer is terminated by the first character that is not a digit.\n\n  float parseFloat();               // float version of parseInt\n\n  size_t readBytes( char *buffer, size_t length); // read chars from stream into buffer\n  size_t readBytes( uint8_t *buffer, size_t length) { return readBytes((char *)buffer, length); }\n  // terminates if length characters have been read or timeout (see setTimeout)\n  // returns the number of characters placed in the buffer (0 means no valid data found)\n\n  size_t readBytesUntil( char terminator, char *buffer, size_t length); // as readBytes with terminator character\n  size_t readBytesUntil( char terminator, uint8_t *buffer, size_t length) { return readBytesUntil(terminator, (char *)buffer, length); }\n  // terminates if length characters have been read, timeout, or if the terminator character  detected\n  // returns the number of characters placed in the buffer (0 means no valid data found)\n\n  // Arduino String functions to be added here\n  String readString();\n  String readStringUntil(char terminator);\n\n  protected:\n  long parseInt(char skipChar); // as above but the given skipChar is ignored\n  // as above but the given skipChar is ignored\n  // this allows format characters (typically commas) in values to be ignored\n\n  float parseFloat(char skipChar);  // as above but the given skipChar is ignored\n\n  struct MultiTarget {\n    const char *str;  // string you're searching for\n    size_t len;       // length of string you're searching for\n    size_t index;     // index used by the search routine.\n  };\n\n  // This allows you to search for an arbitrary number of strings.\n  // Returns index of the target that is found first or -1 if timeout occurs.\n  int findMulti(struct MultiTarget *targets, int tCount);\n};\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/Tone.cpp",
    "content": "/* Tone.cpp\r\n\r\n  A Tone Generator Library\r\n\r\n  Written by Brett Hagman\r\n\r\n  This library is free software; you can redistribute it and/or\r\n  modify it under the terms of the GNU Lesser General Public\r\n  License as published by the Free Software Foundation; either\r\n  version 2.1 of the License, or (at your option) any later version.\r\n\r\n  This library is distributed in the hope that it will be useful,\r\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\r\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\r\n  Lesser General Public License for more details.\r\n\r\n  You should have received a copy of the GNU Lesser General Public\r\n  License along with this library; if not, write to the Free Software\r\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\r\n\r\nVersion Modified By Date     Comments\r\n------- ----------- -------- --------\r\n0001    B Hagman    09/08/02 Initial coding\r\n0002    B Hagman    09/08/18 Multiple pins\r\n0003    B Hagman    09/08/18 Moved initialization from constructor to begin()\r\n0004    B Hagman    09/09/26 Fixed problems with ATmega8\r\n0005    B Hagman    09/11/23 Scanned prescalars for best fit on 8 bit timers\r\n                    09/11/25 Changed pin toggle method to XOR\r\n                    09/11/25 Fixed timer0 from being excluded\r\n0006    D Mellis    09/12/29 Replaced objects with functions\r\n0007    M Sproul    10/08/29 Changed #ifdefs from cpu to register\r\n0008    S Kanemoto  12/06/22 Fixed for Leonardo by @maris_HY\r\n0009    J Reucker   15/04/10 Issue #292 Fixed problems with ATmega8 (thanks to Pete62)\r\n0010    jipp        15/04/13 added additional define check #2923\r\n0011    Baram       16/10/06 fixed for OpenCR\r\n*************************************************/\r\n\r\n#include  <chip.h>\r\n#include \"variant.h\"\r\n#include \"Tone.h\"\r\n\r\n\r\n// timerx_toggle_count:\r\n//  > 0 - duration specified\r\n//  = 0 - stopped\r\n//  < 0 - infinitely (until stop() method called, or new play() called)\r\n\r\nvolatile int32_t  tone_toggle_count;\r\nvolatile uint8_t  tone_timer = TIMER_TONE;\r\nvolatile uint8_t  tone_pin;\r\nvolatile uint8_t  tone_pin_out;\r\nvolatile bool     tone_enable = false;\r\n\r\n\r\nvoid tone_isr( void );\r\n\r\n\r\n\r\nstatic void toneBegin(uint8_t _pin)\r\n{\r\n  tone_pin = _pin;\r\n  tone_pin_out = 0;\r\n  tone_enable = true;\r\n}\r\n\r\n\r\nstatic void toneEnd(void)\r\n{\r\n  tone_enable = false;\r\n  tone_pin_out = 0;\r\n  drv_timer_pause(tone_timer);\r\n}\r\n\r\n\r\n// frequency (in hertz) and duration (in milliseconds).\r\n\r\nvoid tone(uint8_t _pin, unsigned int frequency, unsigned long duration)\r\n{\r\n  //uint8_t prescalarbits = 0b001;\r\n  long toggle_count = 0;\r\n  uint32_t ocr = 0;\r\n  //int8_t _timer;\r\n\r\n\r\n  // Set the pinMode as OUTPUT\r\n  pinMode(_pin, OUTPUT);\r\n  digitalWrite(_pin, 0);\r\n\r\n  ocr = (1000000 / frequency) / 2 ;\r\n\r\n  // Calculate the toggle count\r\n  if (duration > 0)\r\n  {\r\n    toggle_count = 2 * frequency * duration / 1000;\r\n  }\r\n  else\r\n  {\r\n    toggle_count = -1;\r\n  }\r\n\r\n  tone_toggle_count = toggle_count;\r\n\r\n  toneBegin(_pin);\r\n\r\n  drv_timer_set_period(tone_timer, ocr);\r\n  drv_timer_attachInterrupt(tone_timer, tone_isr);\r\n  drv_timer_resume(tone_timer);\r\n}\r\n\r\n\r\nvoid noTone(uint8_t _pin)\r\n{\r\n  toneEnd();\r\n  digitalWrite(_pin, 0);\r\n}\r\n\r\n\r\nvoid tone_isr( void )\r\n{\r\n  if (tone_toggle_count != 0)\r\n  {\r\n    // toggle the pin\r\n    tone_pin_out ^= 1;\r\n    digitalWrite(tone_pin, tone_pin_out);\r\n\r\n    if(tone_toggle_count > 0)\r\n    {\r\n      tone_toggle_count--;\r\n    }\r\n  }\r\n  else\r\n  {\r\n    toneEnd();\r\n  }\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/Tone.h",
    "content": "/*\n  Copyright (c) 2011 Arduino.  All right reserved.\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. \n  See the GNU Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n#ifndef _WIRING_TONE_\n#define _WIRING_TONE_\n\n\n#endif /* _WIRING_TONE_ */\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/UARTClass.cpp",
    "content": "/*\r\n  Copyright (c) 2011 Arduino.  All right reserved.\r\n\r\n  This library is free software; you can redistribute it and/or\r\n  modify it under the terms of the GNU Lesser General Public\r\n  License as published by the Free Software Foundation; either\r\n  version 2.1 of the License, or (at your option) any later version.\r\n\r\n  This library is distributed in the hope that it will be useful,\r\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\r\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\r\n  See the GNU Lesser General Public License for more details.\r\n\r\n  You should have received a copy of the GNU Lesser General Public\r\n  License along with this library; if not, write to the Free Software\r\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\r\n*/\r\n\r\n#include <stdlib.h>\r\n#include <stdio.h>\r\n#include <string.h>\r\n#include \"UARTClass.h\"\r\n#include \"wiring_digital.h\"\r\n#include \"wiring_constants.h\"\r\n#include \"variant.h\"\r\n#include \"digitalWriteFast.h\"\r\n// Constructors ////////////////////////////////////////////////////////////////\r\nUARTClass::UARTClass(void){\r\n\r\n}\r\n\r\nUARTClass::UARTClass(uint8_t uart_num, uint8_t uart_mode, uint8_t *txBuffer, uint16_t tx_buffer_size)\r\n{\r\n  _uart_num  = uart_num;\r\n  _uart_mode = uart_mode;\r\n  _uart_baudrate = 0;\r\n  rx_cnt = 0;\r\n  tx_cnt = 0;\r\n  tx_write_size = 0;\r\n  tx_buffer.buffer = txBuffer;\r\n  tx_buffer.buffer_size = tx_buffer_size;\r\n}\r\n\r\nvoid UARTClass::begin(const uint32_t dwBaudRate)\r\n{\r\n  begin(dwBaudRate, Mode_8N1);\r\n}\r\n\r\nvoid UARTClass::begin(const uint32_t dwBaudRate, const UARTModes config)\r\n{\r\n  UNUSED(config);\r\n\r\n#ifdef DRV_UART_RX_DMA_ONLY\r\n  rx_buffer.iHead = rx_buffer.iTail = 0;\r\n#endif\r\n  tx_buffer.iHead = 0;\r\n  tx_buffer.iTail = 0;\r\n\r\n  _uart_baudrate = dwBaudRate;\r\n\r\n  drv_uart_begin(_uart_num, _uart_mode, dwBaudRate);\r\n}\r\n\r\nvoid UARTClass::end( void )\r\n{\r\n  // Clear any received data\r\n#ifdef DRV_UART_RX_DMA_ONLY\r\n  rx_buffer.iHead = rx_buffer.iTail;\r\n#endif\r\n  // Wait for any outstanding data to be sent\r\n  flush();\r\n}\r\n\r\nint UARTClass::available( void )\r\n{\r\n#ifdef DRV_UART_RX_DMA_ONLY\r\n  if(drv_uart_get_mode(_uart_num) == DRV_UART_IRQ_MODE )\r\n  {\r\n    return (uint32_t)(SERIAL_BUFFER_SIZE + rx_buffer.iHead - rx_buffer.iTail) % SERIAL_BUFFER_SIZE;\r\n  }\r\n  else\r\n  {\r\n    return drv_uart_available(_uart_num);\r\n  }\r\n#else\r\n  return drv_uart_available(_uart_num);\r\n#endif  \r\n}\r\n\r\nint UARTClass::availableForWrite(void)\r\n{\r\n  int head = tx_buffer.iHead;\r\n  int tail = tx_buffer.iTail;\r\n  if (head >= tail) return SERIAL_BUFFER_SIZE - 1 - head + tail;\r\n  return tail - head - 1;\r\n}\r\n\r\nint UARTClass::peek( void )\r\n{\r\n#ifdef DRV_UART_RX_DMA_ONLY\r\n  if(drv_uart_get_mode(_uart_num) == DRV_UART_IRQ_MODE )\r\n  {\r\n    if ( rx_buffer.iHead == rx_buffer.iTail )\r\n      return -1;\r\n\r\n    return rx_buffer.buffer[rx_buffer.iTail];\r\n  }\r\n  else \r\n  {\r\n    return drv_uart_peek(_uart_num);\r\n  }\r\n#else\r\n  return drv_uart_peek(_uart_num);\r\n#endif  \r\n}\r\n\r\nint UARTClass::read( void )\r\n{\r\n#ifdef DRV_UART_RX_DMA_ONLY\r\n  if(drv_uart_get_mode(_uart_num) == DRV_UART_IRQ_MODE )\r\n  {\r\n    // if the head isn't ahead of the tail, we don't have any characters\r\n    if ( rx_buffer.iHead == rx_buffer.iTail )\r\n      return -1;\r\n\r\n    uint8_t uc = rx_buffer.buffer[rx_buffer.iTail];\r\n    rx_buffer.iTail = (unsigned int)(rx_buffer.iTail + 1) % SERIAL_BUFFER_SIZE;\r\n    rx_cnt++;\r\n    return uc;\r\n  }\r\n  else\r\n  {\r\n    int return_value = drv_uart_read(_uart_num);\r\n    if (return_value != -1) \r\n    {\r\n      rx_cnt++;\r\n    }\r\n    return return_value; \r\n  }\r\n#else\r\n  int return_value = drv_uart_read(_uart_num);\r\n  if (return_value != -1) \r\n  {\r\n    rx_cnt++;\r\n  }\r\n  return return_value; \r\n#endif  \r\n}\r\n\r\nvoid UARTClass::flush( void )\r\n{\r\n  while (tx_write_size); //wait for transmit data to be sent\r\n}\r\n\r\nvoid UARTClass::flushRx( uint32_t timeout_ms )\r\n{\r\n#ifdef DRV_UART_RX_DMA_ONLY\r\n  if(drv_uart_get_mode(_uart_num) == DRV_UART_IRQ_MODE )\r\n  {\r\n    // sort of hack, wait the time specified and then just clear it\r\n    if (timeout_ms) \r\n    {\r\n      uint32_t pre_time_ms = millis();\r\n      while((millis() - pre_time_ms) < timeout_ms)\r\n      {\r\n      }\r\n\r\n    }\r\n    rx_buffer.iTail = rx_buffer.iHead;  // clear out buffer\r\n  }\r\n  else \r\n  {\r\n    drv_uart_rx_flush(_uart_num, timeout_ms);\r\n  }\r\n#else\r\n  drv_uart_rx_flush(_uart_num, timeout_ms);\r\n#endif  \r\n}\r\n\r\nsize_t UARTClass::write( const uint8_t uc_data )\r\n{\r\n  return write(&uc_data, 1); // Lets call the buffer function to do the main work\r\n}\r\nvoid inline UARTClass::startNextTransmitDMAorIT()\r\n{\r\n  tx_write_size = (tx_buffer.iTail < tx_buffer.iHead)? tx_buffer.iHead-tx_buffer.iTail : tx_buffer.buffer_size - tx_buffer.iTail;\r\n  if (drv_uart_write_dma_it(_uart_num, &tx_buffer.buffer[tx_buffer.iTail], tx_write_size) != 0) \r\n  {\r\n    tx_write_size = 0;  // error so clear it out\r\n  }\r\n}\r\n\r\nsize_t UARTClass::write( const uint8_t *buffer, size_t size )\r\n{\r\n  tx_cnt += size;\r\n  size_t cbLeft = size; \r\n\r\n  // Lets try to put as much of this data into our TX buffer as possible. \r\n  while (cbLeft--) \r\n  {\r\n    uint16_t nextWrite = (tx_buffer.iHead + 1) % tx_buffer.buffer_size;\r\n    if (tx_buffer.iTail == nextWrite) \r\n    {\r\n      // See if we have an active TX or not\r\n      if (!tx_write_size)\r\n      {\r\n        startNextTransmitDMAorIT();\r\n      }\r\n      // right now this will wait for the entire previous write to complete before continue...\r\n      while (tx_buffer.iTail == nextWrite) \r\n      {\r\n\r\n      }\r\n    }\r\n    tx_buffer.buffer[tx_buffer.iHead] = *buffer++;\r\n    tx_buffer.iHead = nextWrite;\r\n\r\n  }\r\n  // we finished putting stuff on queue, so see if we need to start up write\r\n  // or if it is already going. \r\n  if (!tx_write_size)\r\n  {\r\n    startNextTransmitDMAorIT();\r\n  }\r\n  return size; \r\n}\r\n\r\n\r\nuint32_t UARTClass::getBaudRate( void )\r\n{\r\n  return _uart_baudrate;\r\n}\r\n\r\nuint32_t UARTClass::getRxCnt(void)\r\n{\r\n  return rx_cnt;\r\n}\r\n\r\nuint32_t UARTClass::getTxCnt(void)\r\n{\r\n  return tx_cnt;\r\n}\r\n\r\n\r\nvoid UARTClass::RxHandler (void)\r\n{\r\n#ifdef DRV_UART_RX_DMA_ONLY\r\n  if( _uart_mode == DRV_UART_IRQ_MODE )\r\n  {\r\n\r\n    if(available() < (SERIAL_BUFFER_SIZE - 1))\r\n    {\r\n      drv_uart_read_buf(_uart_num, &r_byte, 1);\r\n      rx_buffer.buffer[rx_buffer.iHead] = r_byte;\r\n  \t\trx_buffer.iHead = (uint16_t)(rx_buffer.iHead + 1) % SERIAL_BUFFER_SIZE;\r\n    }\r\n    drv_uart_start_rx(_uart_num);\r\n  }\r\n#endif\r\n}\r\n\r\nvoid UARTClass::TxHandler(void)\r\n{\r\n  // We completed previous write, so update our tail pointer by count\r\n  tx_buffer.iTail += tx_write_size; \r\n  if (tx_buffer.iTail >= tx_buffer.buffer_size) \r\n    tx_buffer.iTail = 0;  // Should only wrap to start by our other stuff...\r\n\r\n  if (tx_buffer.iHead != tx_buffer.iTail)\r\n  {\r\n    startNextTransmitDMAorIT();\r\n  }\r\n  else \r\n  {\r\n    // finished all outstanding writes so lets set count to 0\r\n    tx_write_size = 0;\r\n  }\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/UARTClass.h",
    "content": "/*\r\n  Copyright (c) 2011 Arduino.  All right reserved.\r\n\r\n  This library is free software; you can redistribute it and/or\r\n  modify it under the terms of the GNU Lesser General Public\r\n  License as published by the Free Software Foundation; either\r\n  version 2.1 of the License, or (at your option) any later version.\r\n\r\n  This library is distributed in the hope that it will be useful,\r\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\r\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\r\n  See the GNU Lesser General Public License for more details.\r\n\r\n  You should have received a copy of the GNU Lesser General Public\r\n  License along with this library; if not, write to the Free Software\r\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\r\n*/\r\n\r\n#ifndef _UART_CLASS_\r\n#define _UART_CLASS_\r\n\r\n#include \"HardwareSerial.h\"\r\n#include <chip.h>\r\n\r\n\r\n#define SERIAL_8N1 UARTClass::Mode_8N1\r\n#define SERIAL_8E1 UARTClass::Mode_8E1\r\n#define SERIAL_8O1 UARTClass::Mode_8O1\r\n#define SERIAL_8M1 UARTClass::Mode_8M1\r\n#define SERIAL_8S1 UARTClass::Mode_8S1\r\n\r\n#define SERIAL_BUFFER_SIZE 2048\r\n#define SERIAL_WRITES_NON_BLOCKING 1\r\nclass UARTClass : public HardwareSerial\r\n{\r\n  public:\r\n    enum UARTModes {\r\n      Mode_8N1 = 0, // = US_MR_CHRL_8_BIT | US_MR_NBSTOP_1_BIT | UART_MR_PAR_NO,\r\n      Mode_8E1,     // = US_MR_CHRL_8_BIT | US_MR_NBSTOP_1_BIT | UART_MR_PAR_EVEN,\r\n      Mode_8O1,     // = US_MR_CHRL_8_BIT | US_MR_NBSTOP_1_BIT | UART_MR_PAR_ODD,\r\n      Mode_8M1,     // = US_MR_CHRL_8_BIT | US_MR_NBSTOP_1_BIT | UART_MR_PAR_MARK,\r\n      Mode_8S1      // = US_MR_CHRL_8_BIT | US_MR_NBSTOP_1_BIT | UART_MR_PAR_SPACE,\r\n    };\r\n    UARTClass(uint8_t uart_num, uint8_t uart_mode, uint8_t *txBuffer, uint16_t tx_buffer_size);\r\n    UARTClass(void);\r\n    void begin(const uint32_t dwBaudRate);\r\n    void begin(const uint32_t dwBaudRate, const UARTModes config);\r\n    void end(void);\r\n    int available(void);\r\n    int availableForWrite(void);\r\n    int peek(void);\r\n    int read(void);\r\n    void flush(void);\r\n    void flushRx( uint32_t timeout_ms );\r\n    size_t write(const uint8_t c);\r\n    size_t write(const uint8_t *buffer, size_t size); \r\n    using Print::write; // pull in write(str) and write(buf, size) from Print\r\n\r\n\r\n    void RxHandler(void); /* Vassilis Serasidis */\r\n    void TxHandler(void); /* Vassilis Serasidis */\r\n    uint32_t getBaudRate(void);\r\n\r\n    uint32_t getRxCnt(void);\r\n    uint32_t getTxCnt(void);\r\n\r\n    operator bool() { return true; }; // UART always active\r\n\r\n\r\n  protected:\r\n    void inline startNextTransmitDMAorIT(void);\r\n#ifdef DRV_UART_RX_DMA_ONLY\r\n    struct ring_buffer\r\n    {\r\n      uint8_t buffer[SERIAL_BUFFER_SIZE];\r\n      volatile uint16_t iHead;\r\n      volatile uint16_t iTail;\r\n    };\r\n#endif    \r\n    struct tx_no_cache_buffer \r\n    {\r\n      uint8_t *buffer;\r\n      uint16_t buffer_size;\r\n      volatile uint16_t iHead;\r\n      volatile uint16_t iTail;\r\n    };\r\n\r\n    uint8_t  _uart_num;\r\n    uint8_t  _uart_mode;\r\n    uint32_t _uart_baudrate;\r\n\r\n    uint8_t r_byte;\r\n    volatile uint16_t    tx_write_size;\r\n    tx_no_cache_buffer tx_buffer;\r\n#ifdef DRV_UART_RX_DMA_ONLY\r\n    ring_buffer rx_buffer;\r\n#endif\r\n    uint32_t rx_cnt;\r\n    uint32_t tx_cnt;\r\n};\r\n\r\n#endif // _UART_CLASS_\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/USBSerial.cpp",
    "content": "/****************************************************************************\r\n *\r\n * USBSerial core library for Arduino STM32 + HAL + CubeMX (HALMX).\r\n *\r\n * Copyright (c) 2016 by Vassilis Serasidis <info@serasidis.gr>\r\n * Home: http://www.serasidis.gr\r\n * email: avrsite@yahoo.gr\r\n *\r\n * Arduino_STM32 forum: http://www.stm32duino.com\r\n *\r\n * Permission to use, copy, modify, and/or distribute this software for\r\n * any purpose with or without fee is hereby granted, provided that the\r\n * above copyright notice and this permission notice appear in all copies.\r\n *\r\n * Some functions follow the sam and samd arduino core libray files.\r\n *\r\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL\r\n * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED\r\n * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR\r\n * BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES\r\n * OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,\r\n * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,\r\n * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS\r\n *\r\n ****************************************************************************/\r\n/*\r\n *  Modified on: 2016. 7.12.\r\n *       Author: Baram, PBHP\r\n */\r\n\r\n#include  <chip.h>\r\n\r\n#include <USBSerial.h>\r\n#include \"variant.h\"\r\n\r\n\r\nextern uint32_t usb_cdc_bitrate;\r\nextern uint32_t usb_cdc_debug_cnt[];\r\n\r\n\r\nUSBSerial::USBSerial(){\r\n  baudrate = 0;\r\n  rx_cnt = 0;\r\n  tx_cnt = 0;\r\n  rx_err_cnt = 0;\r\n  tx_err_cnt = 0;\r\n}\r\n\r\nvoid USBSerial::begin(uint32_t baud_count){\r\n  UNUSED(baud_count);\r\n}\r\n\r\nvoid USBSerial::begin(uint32_t baud_count, uint8_t config){\r\n  UNUSED(baud_count);\r\n  UNUSED(config);\r\n}\r\n\r\nvoid USBSerial::end(void){\r\n}\r\n\r\n\r\nint USBSerial::available(void){\r\n  return vcp_is_available();\r\n}\r\n\r\nint USBSerial::peek(void)\r\n{\r\n  return vcp_peek();\r\n}\r\n\r\nint USBSerial::read(void)\r\n{\r\n  if ( vcp_is_available() == 0 )\r\n    return -1;\r\n\r\n  rx_cnt++;\r\n\r\n  return vcp_getch();\r\n}\r\n\r\nvoid USBSerial::flush(void){\r\n  while( vcp_is_transmitted() == FALSE );\r\n}\r\n\r\nsize_t USBSerial::write(const uint8_t *buffer, size_t size)\r\n{\r\n  uint32_t length;\r\n\r\n  length = vcp_write((uint8_t *)buffer, (uint32_t)size);\r\n\r\n  tx_cnt += length;\r\n  \r\n  return (size_t)length;\r\n}\r\n\r\n\r\nsize_t USBSerial::write(uint8_t c) {\r\n\treturn write(&c, 1);\r\n}\r\n\r\nuint32_t USBSerial::getBaudRate(void)\r\n{\r\n  return usb_cdc_bitrate;\r\n}\r\n\r\nuint32_t USBSerial::getRxCnt(void)\r\n{\r\n  return rx_cnt;\r\n}\r\n\r\nuint32_t USBSerial::getTxCnt(void)\r\n{\r\n  return tx_cnt;\r\n}\r\n\r\nuint32_t USBSerial::getRxErrCnt(void)\r\n{\r\n  return usb_cdc_debug_cnt[0];\r\n}\r\n\r\nuint32_t USBSerial::getTxErrCnt(void)\r\n{\r\n  return usb_cdc_debug_cnt[1];\r\n}\r\n\r\n\r\n// This operator is a convenient way for a sketch to check whether the\r\n// port has actually been configured and opened by the host (as opposed\r\n// to just being connected to the host).  It can be used, for example, in\r\n// setup() before printing to ensure that an application on the host is\r\n// actually ready to receive and display the data.\r\n// We add a short delay before returning to fix a bug observed by Federico\r\n// where the port is configured (lineState != 0) but not quite opened.\r\nUSBSerial::operator bool()\r\n{\r\n  if( vcp_is_connected() == TRUE ) return true;\r\n  else                             return false;\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/USBSerial.h",
    "content": "/****************************************************************************\n *\n * USBSerial core library for Arduino STM32 + HAL + CubeMX (HALMX).\n *\n * Copyright (c) 2016 by Vassilis Serasidis <info@serasidis.gr>\n * Home: http://www.serasidis.gr\n * email: avrsite@yahoo.gr\n *\n * Arduino_STM32 forum: http://www.stm32duino.com\n *\n * The USBSerial.h file follows the function prototypes of\n * the Arduino CDC.h file that was written by Peter Barrett\n *\n * Permission to use, copy, modify, and/or distribute this software for\n * any purpose with or without fee is hereby granted, provided that the\n * above copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL\n * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR\n * BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES\n * OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,\n * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,\n * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS\n *\n ****************************************************************************/\n /*\n *  Modified on: 2016. 7.12.\n *       Author: Baram, PBHP\n */\n\n#ifndef _SERIAL_USB_H_INCLUDED\n#define _SERIAL_USB_H_INCLUDED\n\n#include  <chip.h>\n\n#include \"RingBuffer.h\"\n#include \"Stream.h\"\n#include \"chip.h\"\n\nclass USBSerial : public Stream {\n\n  public:\n    USBSerial();\n    void begin(uint32_t baud_count);\n    void begin(uint32_t baud_count, uint8_t config);\n    void end(void);\n\n    virtual int available(void);\n    //virtual void accept(void);\n    virtual int peek(void);\n    virtual int read(void);\n    virtual void flush(void);\n    virtual size_t write(uint8_t c);\n    virtual size_t write(const uint8_t *buffer, size_t size);\n    using Print::write; // pull in write(str) from Print\n    operator bool();\n\n    uint32_t getBaudRate(void);\n    uint32_t getRxCnt(void);\n    uint32_t getTxCnt(void);\n    uint32_t getRxErrCnt(void);\n    uint32_t getTxErrCnt(void);\n\n  private:\n    uint32_t baudrate;\n    uint32_t rx_cnt;\n    uint32_t tx_cnt;\n    uint32_t rx_err_cnt;\n    uint32_t tx_err_cnt;\n\n};\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/Udp.h",
    "content": "/*\n *  Udp.cpp: Library to send/receive UDP packets.\n *\n * NOTE: UDP is fast, but has some important limitations (thanks to Warren Gray for mentioning these)\n * 1) UDP does not guarantee the order in which assembled UDP packets are received. This\n * might not happen often in practice, but in larger network topologies, a UDP\n * packet can be received out of sequence. \n * 2) UDP does not guard against lost packets - so packets *can* disappear without the sender being\n * aware of it. Again, this may not be a concern in practice on small local networks.\n * For more information, see http://www.cafeaulait.org/course/week12/35.html\n *\n * MIT License:\n * Copyright (c) 2008 Bjoern Hartmann\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n * \n * The above copyright notice and this permission notice shall be included in\n * all copies or substantial portions of the Software.\n * \n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n * THE SOFTWARE.\n *\n * bjoern@cs.stanford.edu 12/30/2008\n */\n\n#ifndef udp_h\n#define udp_h\n\n#include <Stream.h>\n#include <IPAddress.h>\n\nclass UDP : public Stream {\n\npublic:\n  virtual uint8_t begin(uint16_t) =0;\t// initialize, start listening on specified port. Returns 1 if successful, 0 if there are no sockets available to use\n  virtual void stop() =0;  // Finish with the UDP socket\n\n  // Sending UDP packets\n  \n  // Start building up a packet to send to the remote host specific in ip and port\n  // Returns 1 if successful, 0 if there was a problem with the supplied IP address or port\n  virtual int beginPacket(IPAddress ip, uint16_t port) =0;\n  // Start building up a packet to send to the remote host specific in host and port\n  // Returns 1 if successful, 0 if there was a problem resolving the hostname or port\n  virtual int beginPacket(const char *host, uint16_t port) =0;\n  // Finish off this packet and send it\n  // Returns 1 if the packet was sent successfully, 0 if there was an error\n  virtual int endPacket() =0;\n  // Write a single byte into the packet\n  virtual size_t write(uint8_t) =0;\n  // Write size bytes from buffer into the packet\n  virtual size_t write(const uint8_t *buffer, size_t size) =0;\n\n  // Start processing the next available incoming packet\n  // Returns the size of the packet in bytes, or 0 if no packets are available\n  virtual int parsePacket() =0;\n  // Number of bytes remaining in the current packet\n  virtual int available() =0;\n  // Read a single byte from the current packet\n  virtual int read() =0;\n  // Read up to len bytes from the current packet and place them into buffer\n  // Returns the number of bytes read, or 0 if none are available\n  virtual int read(unsigned char* buffer, size_t len) =0;\n  // Read up to len characters from the current packet and place them into buffer\n  // Returns the number of characters read, or 0 if none are available\n  virtual int read(char* buffer, size_t len) =0;\n  // Return the next byte from the current packet without moving on to the next byte\n  virtual int peek() =0;\n  virtual void flush() =0;\t// Finish reading the current packet\n\n  // Return the IP address of the host who sent the current incoming packet\n  virtual IPAddress remoteIP() =0;\n  // Return the port of the host who sent the current incoming packet\n  virtual uint16_t remotePort() =0;\nprotected:\n  uint8_t* rawIPAddress(IPAddress& addr) { return addr.raw_address(); };\n};\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/WCharacter.h",
    "content": "/*\n WCharacter.h - Character utility functions for Wiring & Arduino\n Copyright (c) 2010 Hernando Barragan.  All right reserved.\n\n This library is free software; you can redistribute it and/or\n modify it under the terms of the GNU Lesser General Public\n License as published by the Free Software Foundation; either\n version 2.1 of the License, or (at your option) any later version.\n\n This library is distributed in the hope that it will be useful,\n but WITHOUT ANY WARRANTY; without even the implied warranty of\n MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n Lesser General Public License for more details.\n\n You should have received a copy of the GNU Lesser General Public\n License along with this library; if not, write to the Free Software\n Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n */\n\n#ifndef Character_h\n#define Character_h\n\n#include <ctype.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n// WCharacter.h prototypes\n#if defined (  __GNUC__  )\ninline boolean isAlphaNumeric(int c) __attribute__((always_inline));\ninline boolean isAlpha(int c) __attribute__((always_inline));\ninline boolean isAscii(int c) __attribute__((always_inline));\ninline boolean isWhitespace(int c) __attribute__((always_inline));\ninline boolean isControl(int c) __attribute__((always_inline));\ninline boolean isDigit(int c) __attribute__((always_inline));\ninline boolean isGraph(int c) __attribute__((always_inline));\ninline boolean isLowerCase(int c) __attribute__((always_inline));\ninline boolean isPrintable(int c) __attribute__((always_inline));\ninline boolean isPunct(int c) __attribute__((always_inline));\ninline boolean isSpace(int c) __attribute__((always_inline));\ninline boolean isUpperCase(int c) __attribute__((always_inline));\ninline boolean isHexadecimalDigit(int c) __attribute__((always_inline));\ninline int toAscii(int c) __attribute__((always_inline));\ninline int toLowerCase(int c) __attribute__((always_inline));\ninline int toUpperCase(int c)__attribute__((always_inline));\n#elif defined ( __ICCARM__ )\n#endif\n\n// Checks for an alphanumeric character.\n// It is equivalent to (isalpha(c) || isdigit(c)).\ninline boolean isAlphaNumeric(int c)\n{\n  return ( isalnum(c) == 0 ? false : true);\n}\n\n\n// Checks for an alphabetic character.\n// It is equivalent to (isupper(c) || islower(c)).\ninline boolean isAlpha(int c)\n{\n  return ( isalpha(c) == 0 ? false : true);\n}\n\n\n// Checks whether c is a 7-bit unsigned char value\n// that fits into the ASCII character set.\ninline boolean isAscii(int c)\n{\n/*  return ( isascii(c) == 0 ? false : true); */\n  return ( (c & ~0x7f) != 0 ? false : true);\n}\n\n\n// Checks for a blank character, that is, a space or a tab.\ninline boolean isWhitespace(int c)\n{\n  return ( isblank (c) == 0 ? false : true);\n}\n\n\n// Checks for a control character.\ninline boolean isControl(int c)\n{\n  return ( iscntrl (c) == 0 ? false : true);\n}\n\n\n// Checks for a digit (0 through 9).\ninline boolean isDigit(int c)\n{\n  return ( isdigit (c) == 0 ? false : true);\n}\n\n\n// Checks for any printable character except space.\ninline boolean isGraph(int c)\n{\n  return ( isgraph (c) == 0 ? false : true);\n}\n\n\n// Checks for a lower-case character.\ninline boolean isLowerCase(int c)\n{\n  return (islower (c) == 0 ? false : true);\n}\n\n\n// Checks for any printable character including space.\ninline boolean isPrintable(int c)\n{\n  return ( isprint (c) == 0 ? false : true);\n}\n\n\n// Checks for any printable character which is not a space\n// or an alphanumeric character.\ninline boolean isPunct(int c)\n{\n  return ( ispunct (c) == 0 ? false : true);\n}\n\n\n// Checks for white-space characters. For the avr-libc library,\n// these are: space, formfeed ('\\f'), newline ('\\n'), carriage\n// return ('\\r'), horizontal tab ('\\t'), and vertical tab ('\\v').\ninline boolean isSpace(int c)\n{\n  return ( isspace (c) == 0 ? false : true);\n}\n\n\n// Checks for an uppercase letter.\ninline boolean isUpperCase(int c)\n{\n  return ( isupper (c) == 0 ? false : true);\n}\n\n\n// Checks for a hexadecimal digits, i.e. one of 0 1 2 3 4 5 6 7\n// 8 9 a b c d e f A B C D E F.\ninline boolean isHexadecimalDigit(int c)\n{\n  return ( isxdigit (c) == 0 ? false : true);\n}\n\n\n// Converts c to a 7-bit unsigned char value that fits into the\n// ASCII character set, by clearing the high-order bits.\ninline int toAscii(int c)\n{\n/*  return toascii (c); */\n  return (c & 0x7f);\n}\n\n\n// Warning:\n// Many people will be unhappy if you use this function.\n// This function will convert accented letters into random\n// characters.\n\n// Converts the letter c to lower case, if possible.\ninline int toLowerCase(int c)\n{\n  return tolower (c);\n}\n\n\n// Converts the letter c to upper case, if possible.\ninline int toUpperCase(int c)\n{\n  return toupper (c);\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/WInterrupts.c",
    "content": "/*\n  Copyright (c) 2014 Arduino.  All right reserved.\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n  See the GNU Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n#include \"WInterrupts.h\"\n#include \"variant.h\"\n#include \"wiring_digital.h\"\n\n#include <string.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n\n/*\n * \\brief Specifies a named Interrupt Service Routine (ISR) to call when an interrupt occurs.\n *        Replaces any previous function that was attached to the interrupt.\n */\n\nvoid attachInterrupt( uint32_t pin, voidFuncPtr callback, uint32_t ulMode )\n{\n  drv_exti_attach( pin, callback, ulMode );\n}\n\n/*\n * \\brief Turns off the given interrupt.\n */\nvoid detachInterrupt( uint32_t pin )\n{\n  drv_exti_detach( pin );\n}\n\n\n#ifdef __cplusplus\n}\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/WInterrupts.h",
    "content": "/*\n  Copyright (c) 2011-2012 Arduino.  All right reserved.\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. \n  See the GNU Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n#ifndef _WIRING_INTERRUPTS_\n#define _WIRING_INTERRUPTS_\n\n#include \"Arduino.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\nvoid attachInterrupt(uint32_t pin, void (*callback)(void), uint32_t mode);\n\nvoid detachInterrupt(uint32_t pin);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _WIRING_INTERRUPTS_ */\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/WMath.cpp",
    "content": "/*\n  Copyright (c) 2011 Arduino.  All right reserved.\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. \n  See the GNU Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\nextern \"C\" {\n  #include \"stdlib.h\"\n  #include \"stdint.h\"\n}\n#include \"WMath.h\"\n\nextern void randomSeed( uint32_t dwSeed )\n{\n  if ( dwSeed != 0 )\n  {\n    srand( dwSeed ) ;\n  }\n}\n\nextern long random( long howbig )\n{\n  if ( howbig == 0 )\n  {\n    return 0 ;\n  }\n\n  return rand() % howbig;\n}\n\nextern long random( long howsmall, long howbig )\n{\n  if (howsmall >= howbig)\n  {\n    return howsmall;\n  }\n\n  long diff = howbig - howsmall;\n\n  return random(diff) + howsmall;\n}\n\nextern long map(long x, long in_min, long in_max, long out_min, long out_max)\n{\n  return (x - in_min) * (out_max - out_min) / (in_max - in_min) + out_min;\n}\n\nextern uint16_t makeWord( uint16_t w )\n{\n  return w ;\n}\n\nextern uint16_t makeWord( uint8_t h, uint8_t l )\n{\n  return (h << 8) | l ;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/WMath.h",
    "content": "/*\n  Copyright (c) 2011 Arduino.  All right reserved.\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. \n  See the GNU Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n#ifndef _WIRING_MATH_\n#define _WIRING_MATH_\n\nextern long random( long ) ;\nextern long random( long, long ) ;\nextern void randomSeed( uint32_t dwSeed ) ;\nextern long map( long, long, long, long, long ) ;\n\nextern uint16_t makeWord( uint16_t w ) ;\nextern uint16_t makeWord( uint8_t h, uint8_t l ) ;\n\n#define word(...) makeWord(__VA_ARGS__)\n\n\n#endif /* _WIRING_MATH_ */\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/WString.cpp",
    "content": "/*\n  WString.cpp - String library for Wiring & Arduino\n  ...mostly rewritten by Paul Stoffregen...\n  Copyright (c) 2009-10 Hernando Barragan.  All rights reserved.\n  Copyright 2011, Paul Stoffregen, paul@pjrc.com\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n  Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n#include \"WString.h\"\n#include \"itoa.h\"\n#include \"avr/dtostrf.h\"\n\n/*********************************************/\n/*  Constructors                             */\n/*********************************************/\n\nString::String(const char *cstr)\n{\n\tinit();\n\tif (cstr) copy(cstr, strlen(cstr));\n}\n\nString::String(const String &value)\n{\n\tinit();\n\t*this = value;\n}\n\nString::String(const __FlashStringHelper *pstr)\n{\n\tinit();\n\t*this = pstr;\n}\n\n#ifdef __GXX_EXPERIMENTAL_CXX0X__\nString::String(String &&rval)\n{\n\tinit();\n\tmove(rval);\n}\nString::String(StringSumHelper &&rval)\n{\n\tinit();\n\tmove(rval);\n}\n#endif\n\nString::String(char c)\n{\n\tinit();\n\tchar buf[2];\n\tbuf[0] = c;\n\tbuf[1] = 0;\n\t*this = buf;\n}\n\nString::String(unsigned char value, unsigned char base)\n{\n\tinit();\n\tchar buf[1 + 8 * sizeof(unsigned char)];\n\tutoa(value, buf, base);\n\t*this = buf;\n}\n\nString::String(int value, unsigned char base)\n{\n\tinit();\n\tchar buf[2 + 8 * sizeof(int)];\n\titoa(value, buf, base);\n\t*this = buf;\n}\n\nString::String(unsigned int value, unsigned char base)\n{\n\tinit();\n\tchar buf[1 + 8 * sizeof(unsigned int)];\n\tutoa(value, buf, base);\n\t*this = buf;\n}\n\nString::String(long value, unsigned char base)\n{\n\tinit();\n\tchar buf[2 + 8 * sizeof(long)];\n\tltoa(value, buf, base);\n\t*this = buf;\n}\n\nString::String(unsigned long value, unsigned char base)\n{\n\tinit();\n\tchar buf[1 + 8 * sizeof(unsigned long)];\n\tultoa(value, buf, base);\n\t*this = buf;\n}\n\nString::String(float value, unsigned char decimalPlaces)\n{\n\tinit();\n\tchar buf[33];\n\t*this = dtostrf(value, (decimalPlaces + 2), decimalPlaces, buf);\n}\n\nString::String(double value, unsigned char decimalPlaces)\n{\n\tinit();\n\tchar buf[33];\n\t*this = dtostrf(value, (decimalPlaces + 2), decimalPlaces, buf);\n}\n\nString::~String()\n{\n\tfree(buffer);\n}\n\n/*********************************************/\n/*  Memory Management                        */\n/*********************************************/\n\ninline void String::init(void)\n{\n\tbuffer = NULL;\n\tcapacity = 0;\n\tlen = 0;\n}\n\nvoid String::invalidate(void)\n{\n\tif (buffer) free(buffer);\n\tbuffer = NULL;\n\tcapacity = len = 0;\n}\n\nunsigned char String::reserve(unsigned int size)\n{\n\tif (buffer && capacity >= size) return 1;\n\tif (changeBuffer(size)) {\n\t\tif (len == 0) buffer[0] = 0;\n\t\treturn 1;\n\t}\n\treturn 0;\n}\n\nunsigned char String::changeBuffer(unsigned int maxStrLen)\n{\n\tchar *newbuffer = (char *)realloc(buffer, maxStrLen + 1);\n\tif (newbuffer) {\n\t\tbuffer = newbuffer;\n\t\tcapacity = maxStrLen;\n\t\treturn 1;\n\t}\n\treturn 0;\n}\n\n/*********************************************/\n/*  Copy and Move                            */\n/*********************************************/\n\nString & String::copy(const char *cstr, unsigned int length)\n{\n\tif (!reserve(length)) {\n\t\tinvalidate();\n\t\treturn *this;\n\t}\n\tlen = length;\n\tstrcpy(buffer, cstr);\n\treturn *this;\n}\n\nString & String::copy(const __FlashStringHelper *pstr, unsigned int length)\n{\n\tif (!reserve(length)) {\n\t\tinvalidate();\n\t\treturn *this;\n\t}\n\tlen = length;\n\tstrcpy_P(buffer, (PGM_P)pstr);\n\treturn *this;\n}\n\n#ifdef __GXX_EXPERIMENTAL_CXX0X__\nvoid String::move(String &rhs)\n{\n\tif (buffer) {\n\t\tif (capacity >= rhs.len) {\n\t\t\tstrcpy(buffer, rhs.buffer);\n\t\t\tlen = rhs.len;\n\t\t\trhs.len = 0;\n\t\t\treturn;\n\t\t} else {\n\t\t\tfree(buffer);\n\t\t}\n\t}\n\tbuffer = rhs.buffer;\n\tcapacity = rhs.capacity;\n\tlen = rhs.len;\n\trhs.buffer = NULL;\n\trhs.capacity = 0;\n\trhs.len = 0;\n}\n#endif\n\nString & String::operator = (const String &rhs)\n{\n\tif (this == &rhs) return *this;\n\t\n\tif (rhs.buffer) copy(rhs.buffer, rhs.len);\n\telse invalidate();\n\t\n\treturn *this;\n}\n\n#ifdef __GXX_EXPERIMENTAL_CXX0X__\nString & String::operator = (String &&rval)\n{\n\tif (this != &rval) move(rval);\n\treturn *this;\n}\n\nString & String::operator = (StringSumHelper &&rval)\n{\n\tif (this != &rval) move(rval);\n\treturn *this;\n}\n#endif\n\nString & String::operator = (const char *cstr)\n{\n\tif (cstr) copy(cstr, strlen(cstr));\n\telse invalidate();\n\t\n\treturn *this;\n}\n\nString & String::operator = (const __FlashStringHelper *pstr)\n{\n\tif (pstr) copy(pstr, strlen_P((PGM_P)pstr));\n\telse invalidate();\n\n\treturn *this;\n}\n\n/*********************************************/\n/*  concat                                   */\n/*********************************************/\n\nunsigned char String::concat(const String &s)\n{\n\treturn concat(s.buffer, s.len);\n}\n#if 1\nunsigned char String::concat(const char *cstr, unsigned int length)\n{\n\tunsigned int newlen = len + length;\n\tif (!cstr) return 0;\n\tif (length == 0) return 1;\n\tif (!reserve(newlen)) return 0;\n\tstrcpy(buffer + len, cstr);\n\tlen = newlen;\n\treturn 1;\n}\n\nunsigned char String::concat(const char *cstr)\n{\n\tif (!cstr) return 0;\n\treturn concat(cstr, strlen(cstr));\n}\n\nunsigned char String::concat(char c)\n{\n\tchar buf[2];\n\tbuf[0] = c;\n\tbuf[1] = 0;\n\treturn concat(buf, 1);\n}\n\nunsigned char String::concat(unsigned char num)\n{\n\tchar buf[1 + 3 * sizeof(unsigned char)];\n\titoa(num, buf, 10);\n\treturn concat(buf, strlen(buf));\n}\n\nunsigned char String::concat(int num)\n{\n\tchar buf[2 + 3 * sizeof(int)];\n\titoa(num, buf, 10);\n\treturn concat(buf, strlen(buf));\n}\n\nunsigned char String::concat(unsigned int num)\n{\n\tchar buf[1 + 3 * sizeof(unsigned int)];\n\tutoa(num, buf, 10);\n\treturn concat(buf, strlen(buf));\n}\n\nunsigned char String::concat(long num)\n{\n\tchar buf[2 + 3 * sizeof(long)];\n\tltoa(num, buf, 10);\n\treturn concat(buf, strlen(buf));\n}\n\nunsigned char String::concat(unsigned long num)\n{\n\tchar buf[1 + 3 * sizeof(unsigned long)];\n\tultoa(num, buf, 10);\n\treturn concat(buf, strlen(buf));\n}\n\nunsigned char String::concat(float num)\n{\n\tchar buf[20];\n\tchar* string = dtostrf(num, 4, 2, buf);\n\treturn concat(string, strlen(string));\n}\n\nunsigned char String::concat(double num)\n{\n\tchar buf[20];\n\tchar* string = dtostrf(num, 4, 2, buf);\n\treturn concat(string, strlen(string));\n}\n\nunsigned char String::concat(const __FlashStringHelper * str)\n{\n\tif (!str) return 0;\n\tint length = strlen_P((const char *) str);\n\tif (length == 0) return 1;\n\tunsigned int newlen = len + length;\n\tif (!reserve(newlen)) return 0;\n\tstrcpy_P(buffer + len, (const char *) str);\n\tlen = newlen;\n\treturn 1;\n}\n\n/*********************************************/\n/*  Concatenate                              */\n/*********************************************/\n\nStringSumHelper & operator + (const StringSumHelper &lhs, const String &rhs)\n{\n\tStringSumHelper &a = const_cast<StringSumHelper&>(lhs);\n\tif (!a.concat(rhs.buffer, rhs.len)) a.invalidate();\n\treturn a;\n}\n\nStringSumHelper & operator + (const StringSumHelper &lhs, const char *cstr)\n{\n\tStringSumHelper &a = const_cast<StringSumHelper&>(lhs);\n\tif (!cstr || !a.concat(cstr, strlen(cstr))) a.invalidate();\n\treturn a;\n}\n\nStringSumHelper & operator + (const StringSumHelper &lhs, char c)\n{\n\tStringSumHelper &a = const_cast<StringSumHelper&>(lhs);\n\tif (!a.concat(c)) a.invalidate();\n\treturn a;\n}\n\nStringSumHelper & operator + (const StringSumHelper &lhs, unsigned char num)\n{\n\tStringSumHelper &a = const_cast<StringSumHelper&>(lhs);\n\tif (!a.concat(num)) a.invalidate();\n\treturn a;\n}\n\nStringSumHelper & operator + (const StringSumHelper &lhs, int num)\n{\n\tStringSumHelper &a = const_cast<StringSumHelper&>(lhs);\n\tif (!a.concat(num)) a.invalidate();\n\treturn a;\n}\n\nStringSumHelper & operator + (const StringSumHelper &lhs, unsigned int num)\n{\n\tStringSumHelper &a = const_cast<StringSumHelper&>(lhs);\n\tif (!a.concat(num)) a.invalidate();\n\treturn a;\n}\n\nStringSumHelper & operator + (const StringSumHelper &lhs, long num)\n{\n\tStringSumHelper &a = const_cast<StringSumHelper&>(lhs);\n\tif (!a.concat(num)) a.invalidate();\n\treturn a;\n}\n\nStringSumHelper & operator + (const StringSumHelper &lhs, unsigned long num)\n{\n\tStringSumHelper &a = const_cast<StringSumHelper&>(lhs);\n\tif (!a.concat(num)) a.invalidate();\n\treturn a;\n}\n\nStringSumHelper & operator + (const StringSumHelper &lhs, float num)\n{\n\tStringSumHelper &a = const_cast<StringSumHelper&>(lhs);\n\tif (!a.concat(num)) a.invalidate();\n\treturn a;\n}\n\nStringSumHelper & operator + (const StringSumHelper &lhs, double num)\n{\n\tStringSumHelper &a = const_cast<StringSumHelper&>(lhs);\n\tif (!a.concat(num)) a.invalidate();\n\treturn a;\n}\n\nStringSumHelper & operator + (const StringSumHelper &lhs, const __FlashStringHelper *rhs)\n{\n\tStringSumHelper &a = const_cast<StringSumHelper&>(lhs);\n\tif (!a.concat(rhs))\ta.invalidate();\n\treturn a;\n}\n#endif\n\n/*********************************************/\n/*  Comparison                               */\n/*********************************************/\n\nint String::compareTo(const String &s) const\n{\n\tif (!buffer || !s.buffer) {\n\t\tif (s.buffer && s.len > 0) return 0 - *(unsigned char *)s.buffer;\n\t\tif (buffer && len > 0) return *(unsigned char *)buffer;\n\t\treturn 0;\n\t}\n\treturn strcmp(buffer, s.buffer);\n}\n\nunsigned char String::equals(const String &s2) const\n{\n\treturn (len == s2.len && compareTo(s2) == 0);\n}\n\nunsigned char String::equals(const char *cstr) const\n{\n\tif (len == 0) return (cstr == NULL || *cstr == 0);\n\tif (cstr == NULL) return buffer[0] == 0;\n\treturn strcmp(buffer, cstr) == 0;\n}\n\nunsigned char String::operator<(const String &rhs) const\n{\n\treturn compareTo(rhs) < 0;\n}\n\nunsigned char String::operator>(const String &rhs) const\n{\n\treturn compareTo(rhs) > 0;\n}\n\nunsigned char String::operator<=(const String &rhs) const\n{\n\treturn compareTo(rhs) <= 0;\n}\n\nunsigned char String::operator>=(const String &rhs) const\n{\n\treturn compareTo(rhs) >= 0;\n}\n\nunsigned char String::equalsIgnoreCase( const String &s2 ) const\n{\n\tif (this == &s2) return 1;\n\tif (len != s2.len) return 0;\n\tif (len == 0) return 1;\n\tconst char *p1 = buffer;\n\tconst char *p2 = s2.buffer;\n\twhile (*p1) {\n\t\tif (tolower(*p1++) != tolower(*p2++)) return 0;\n\t} \n\treturn 1;\n}\n\nunsigned char String::startsWith( const String &s2 ) const\n{\n\tif (len < s2.len) return 0;\n\treturn startsWith(s2, 0);\n}\n\nunsigned char String::startsWith( const String &s2, unsigned int offset ) const\n{\n\tif (offset > len - s2.len || !buffer || !s2.buffer) return 0;\n\treturn strncmp( &buffer[offset], s2.buffer, s2.len ) == 0;\n}\n\nunsigned char String::endsWith( const String &s2 ) const\n{\n\tif ( len < s2.len || !buffer || !s2.buffer) return 0;\n\treturn strcmp(&buffer[len - s2.len], s2.buffer) == 0;\n}\n\n/*********************************************/\n/*  Character Access                         */\n/*********************************************/\n\nchar String::charAt(unsigned int loc) const\n{\n\treturn operator[](loc);\n}\n\nvoid String::setCharAt(unsigned int loc, char c) \n{\n\tif (loc < len) buffer[loc] = c;\n}\n\nchar & String::operator[](unsigned int index)\n{\n\tstatic char dummy_writable_char;\n\tif (index >= len || !buffer) {\n\t\tdummy_writable_char = 0;\n\t\treturn dummy_writable_char;\n\t}\n\treturn buffer[index];\n}\n\nchar String::operator[]( unsigned int index ) const\n{\n\tif (index >= len || !buffer) return 0;\n\treturn buffer[index];\n}\n\nvoid String::getBytes(unsigned char *buf, unsigned int bufsize, unsigned int index) const\n{\n\tif (!bufsize || !buf) return;\n\tif (index >= len) {\n\t\tbuf[0] = 0;\n\t\treturn;\n\t}\n\tunsigned int n = bufsize - 1;\n\tif (n > len - index) n = len - index;\n\tstrncpy((char *)buf, buffer + index, n);\n\tbuf[n] = 0;\n}\n\n/*********************************************/\n/*  Search                                   */\n/*********************************************/\n\nint String::indexOf(char c) const\n{\n\treturn indexOf(c, 0);\n}\n\nint String::indexOf( char ch, unsigned int fromIndex ) const\n{\n\tif (fromIndex >= len) return -1;\n\tconst char* temp = strchr(buffer + fromIndex, ch);\n\tif (temp == NULL) return -1;\n\treturn temp - buffer;\n}\n\nint String::indexOf(const String &s2) const\n{\n\treturn indexOf(s2, 0);\n}\n\nint String::indexOf(const String &s2, unsigned int fromIndex) const\n{\n\tif (fromIndex >= len) return -1;\n\tconst char *found = strstr(buffer + fromIndex, s2.buffer);\n\tif (found == NULL) return -1;\n\treturn found - buffer;\n}\n\nint String::lastIndexOf( char theChar ) const\n{\n\treturn lastIndexOf(theChar, len - 1);\n}\n\nint String::lastIndexOf(char ch, unsigned int fromIndex) const\n{\n\tif (fromIndex >= len) return -1;\n\tchar tempchar = buffer[fromIndex + 1];\n\tbuffer[fromIndex + 1] = '\\0';\n\tchar* temp = strrchr( buffer, ch );\n\tbuffer[fromIndex + 1] = tempchar;\n\tif (temp == NULL) return -1;\n\treturn temp - buffer;\n}\n\nint String::lastIndexOf(const String &s2) const\n{\n\treturn lastIndexOf(s2, len - s2.len);\n}\n\nint String::lastIndexOf(const String &s2, unsigned int fromIndex) const\n{\n  \tif (s2.len == 0 || len == 0 || s2.len > len) return -1;\n\tif (fromIndex >= len) fromIndex = len - 1;\n\tint found = -1;\n\tfor (char *p = buffer; p <= buffer + fromIndex; p++) {\n\t\tp = strstr(p, s2.buffer);\n\t\tif (!p) break;\n\t\tif ((unsigned int)(p - buffer) <= fromIndex) found = p - buffer;\n\t}\n\treturn found;\n}\n\nString String::substring(unsigned int left, unsigned int right) const\n{\n\tif (left > right) {\n\t\tunsigned int temp = right;\n\t\tright = left;\n\t\tleft = temp;\n\t}\n\tString out;\n\tif (left >= len) return out;\n\tif (right > len) right = len;\n\tchar temp = buffer[right];  // save the replaced character\n\tbuffer[right] = '\\0';\t\n\tout = buffer + left;  // pointer arithmetic\n\tbuffer[right] = temp;  //restore character\n\treturn out;\n}\n\n/*********************************************/\n/*  Modification                             */\n/*********************************************/\n\nvoid String::replace(char find, char replace)\n{\n\tif (!buffer) return;\n\tfor (char *p = buffer; *p; p++) {\n\t\tif (*p == find) *p = replace;\n\t}\n}\n\nvoid String::replace(const String& find, const String& replace)\n{\n\tif (len == 0 || find.len == 0) return;\n\tint diff = replace.len - find.len;\n\tchar *readFrom = buffer;\n\tchar *foundAt;\n\tif (diff == 0) {\n\t\twhile ((foundAt = strstr(readFrom, find.buffer)) != NULL) {\n\t\t\tmemcpy(foundAt, replace.buffer, replace.len);\n\t\t\treadFrom = foundAt + replace.len;\n\t\t}\n\t} else if (diff < 0) {\n\t\tchar *writeTo = buffer;\n\t\twhile ((foundAt = strstr(readFrom, find.buffer)) != NULL) {\n\t\t\tunsigned int n = foundAt - readFrom;\n\t\t\tmemcpy(writeTo, readFrom, n);\n\t\t\twriteTo += n;\n\t\t\tmemcpy(writeTo, replace.buffer, replace.len);\n\t\t\twriteTo += replace.len;\n\t\t\treadFrom = foundAt + find.len;\n\t\t\tlen += diff;\n\t\t}\n\t\tstrcpy(writeTo, readFrom);\n\t} else {\n\t\tunsigned int size = len; // compute size needed for result\n\t\twhile ((foundAt = strstr(readFrom, find.buffer)) != NULL) {\n\t\t\treadFrom = foundAt + find.len;\n\t\t\tsize += diff;\n\t\t}\n\t\tif (size == len) return;\n\t\tif (size > capacity && !changeBuffer(size)) return; // XXX: tell user!\n\t\tint index = len - 1;\n\t\twhile (index >= 0 && (index = lastIndexOf(find, index)) >= 0) {\n\t\t\treadFrom = buffer + index + find.len;\n\t\t\tmemmove(readFrom + diff, readFrom, len - (readFrom - buffer));\n\t\t\tlen += diff;\n\t\t\tbuffer[len] = 0;\n\t\t\tmemcpy(buffer + index, replace.buffer, replace.len);\n\t\t\tindex--;\n\t\t}\n\t}\n}\n\nvoid String::remove(unsigned int index){\n\t// Pass the biggest integer as the count. The remove method\n\t// below will take care of truncating it at the end of the\n\t// string.\n\tremove(index, (unsigned int)-1);\n}\n\nvoid String::remove(unsigned int index, unsigned int count){\n\tif (index >= len) { return; }\n\tif (count <= 0) { return; }\n\tif (count > len - index) { count = len - index; }\n\tchar *writeTo = buffer + index;\n\tlen = len - count;\n\tstrncpy(writeTo, buffer + index + count,len - index);\n\tbuffer[len] = 0;\n}\n\nvoid String::toLowerCase(void)\n{\n\tif (!buffer) return;\n\tfor (char *p = buffer; *p; p++) {\n\t\t*p = tolower(*p);\n\t}\n}\n\nvoid String::toUpperCase(void)\n{\n\tif (!buffer) return;\n\tfor (char *p = buffer; *p; p++) {\n\t\t*p = toupper(*p);\n\t}\n}\n\nvoid String::trim(void)\n{\n\tif (!buffer || len == 0) return;\n\tchar *begin = buffer;\n\twhile (isspace(*begin)) begin++;\n\tchar *end = buffer + len - 1;\n\twhile (isspace(*end) && end >= begin) end--;\n\tlen = end + 1 - begin;\n\tif (begin > buffer) memcpy(buffer, begin, len);\n\tbuffer[len] = 0;\n}\n\n/*********************************************/\n/*  Parsing / Conversion                     */\n/*********************************************/\n\nlong String::toInt(void) const\n{\n\tif (buffer) return atol(buffer);\n\treturn 0;\n}\n\nfloat String::toFloat(void) const\n{\n\tif (buffer) return float(atof(buffer));\n\treturn 0;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/WString.h",
    "content": "/*\n  WString.h - String library for Wiring & Arduino\n  ...mostly rewritten by Paul Stoffregen...\n  Copyright (c) 2009-10 Hernando Barragan.  All right reserved.\n  Copyright 2011, Paul Stoffregen, paul@pjrc.com\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n  Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n#ifndef String_class_h\n#define String_class_h\n#ifdef __cplusplus\n\n#include <stdlib.h>\n#include <string.h>\n#include <ctype.h>\n#include <avr/pgmspace.h>\n\n// When compiling programs with this class, the following gcc parameters\n// dramatically increase performance and memory (RAM) efficiency, typically\n// with little or no increase in code size.\n//     -felide-constructors\n//     -std=c++0x\n\nclass __FlashStringHelper;\n#define F(string_literal) (reinterpret_cast<const __FlashStringHelper *>(PSTR(string_literal)))\n\n// An inherited class for holding the result of a concatenation.  These\n// result objects are assumed to be writable by subsequent concatenations.\nclass StringSumHelper;\n\n// The string class\nclass String\n{\n\t// use a function pointer to allow for \"if (s)\" without the\n\t// complications of an operator bool(). for more information, see:\n\t// http://www.artima.com/cppsource/safebool.html\n\ttypedef void (String::*StringIfHelperType)() const;\n\tvoid StringIfHelper() const {}\n\npublic:\n\t// constructors\n\t// creates a copy of the initial value.\n\t// if the initial value is null or invalid, or if memory allocation\n\t// fails, the string will be marked as invalid (i.e. \"if (s)\" will\n\t// be false).\n\tString(const char *cstr = \"\");\n\tString(const String &str);\n\tString(const __FlashStringHelper *str);\n\t#ifdef __GXX_EXPERIMENTAL_CXX0X__\n\tString(String &&rval);\n\tString(StringSumHelper &&rval);\n\t#endif\n\texplicit String(char c);\n\texplicit String(unsigned char, unsigned char base=10);\n\texplicit String(int, unsigned char base=10);\n\texplicit String(unsigned int, unsigned char base=10);\n\texplicit String(long, unsigned char base=10);\n\texplicit String(unsigned long, unsigned char base=10);\n\texplicit String(float, unsigned char decimalPlaces=2);\n\texplicit String(double, unsigned char decimalPlaces=2);\n\t~String(void);\n\n\t// memory management\n\t// return true on success, false on failure (in which case, the string\n\t// is left unchanged).  reserve(0), if successful, will validate an\n\t// invalid string (i.e., \"if (s)\" will be true afterwards)\n\tunsigned char reserve(unsigned int size);\n\tinline unsigned int length(void) const {return len;}\n\n\t// creates a copy of the assigned value.  if the value is null or\n\t// invalid, or if the memory allocation fails, the string will be \n\t// marked as invalid (\"if (s)\" will be false).\n\tString & operator = (const String &rhs);\n\tString & operator = (const char *cstr);\n\tString & operator = (const __FlashStringHelper *str);\n\t#ifdef __GXX_EXPERIMENTAL_CXX0X__\n\tString & operator = (String &&rval);\n\tString & operator = (StringSumHelper &&rval);\n\t#endif\n\n\t// concatenate (works w/ built-in types)\n\t\n\t// returns true on success, false on failure (in which case, the string\n\t// is left unchanged).  if the argument is null or invalid, the \n\t// concatenation is considered unsucessful.  \n\tunsigned char concat(const String &str);\n\tunsigned char concat(const char *cstr);\n\tunsigned char concat(char c);\n\tunsigned char concat(unsigned char c);\n\tunsigned char concat(int num);\n\tunsigned char concat(unsigned int num);\n\tunsigned char concat(long num);\n\tunsigned char concat(unsigned long num);\n\tunsigned char concat(float num);\n\tunsigned char concat(double num);\n\tunsigned char concat(const __FlashStringHelper * str);\n\t\n\t// if there's not enough memory for the concatenated value, the string\n\t// will be left unchanged (but this isn't signalled in any way)\n\tString & operator += (const String &rhs)\t{concat(rhs); return (*this);}\n\tString & operator += (const char *cstr)\t\t{concat(cstr); return (*this);}\n\tString & operator += (char c)\t\t\t{concat(c); return (*this);}\n\tString & operator += (unsigned char num)\t\t{concat(num); return (*this);}\n\tString & operator += (int num)\t\t\t{concat(num); return (*this);}\n\tString & operator += (unsigned int num)\t\t{concat(num); return (*this);}\n\tString & operator += (long num)\t\t\t{concat(num); return (*this);}\n\tString & operator += (unsigned long num)\t{concat(num); return (*this);}\n\tString & operator += (float num)\t\t{concat(num); return (*this);}\n\tString & operator += (double num)\t\t{concat(num); return (*this);}\n\tString & operator += (const __FlashStringHelper *str){concat(str); return (*this);}\n\n\tfriend StringSumHelper & operator + (const StringSumHelper &lhs, const String &rhs);\n#if 1\n\tfriend StringSumHelper & operator + (const StringSumHelper &lhs, const char *cstr);\n\tfriend StringSumHelper & operator + (const StringSumHelper &lhs, char c);\n\tfriend StringSumHelper & operator + (const StringSumHelper &lhs, unsigned char num);\n\tfriend StringSumHelper & operator + (const StringSumHelper &lhs, int num);\n\tfriend StringSumHelper & operator + (const StringSumHelper &lhs, unsigned int num);\n\tfriend StringSumHelper & operator + (const StringSumHelper &lhs, long num);\n\tfriend StringSumHelper & operator + (const StringSumHelper &lhs, unsigned long num);\n\tfriend StringSumHelper & operator + (const StringSumHelper &lhs, float num);\n\tfriend StringSumHelper & operator + (const StringSumHelper &lhs, double num);\n\tfriend StringSumHelper & operator + (const StringSumHelper &lhs, const __FlashStringHelper *rhs);\n#endif\n\t// comparison (only works w/ Strings and \"strings\")\n\toperator StringIfHelperType() const { return buffer ? &String::StringIfHelper : 0; }\n\tint compareTo(const String &s) const;\n\tunsigned char equals(const String &s) const;\n\tunsigned char equals(const char *cstr) const;\n\tunsigned char operator == (const String &rhs) const {return equals(rhs);}\n\tunsigned char operator == (const char *cstr) const {return equals(cstr);}\n\tunsigned char operator != (const String &rhs) const {return !equals(rhs);}\n\tunsigned char operator != (const char *cstr) const {return !equals(cstr);}\n\tunsigned char operator <  (const String &rhs) const;\n\tunsigned char operator >  (const String &rhs) const;\n\tunsigned char operator <= (const String &rhs) const;\n\tunsigned char operator >= (const String &rhs) const;\n\tunsigned char equalsIgnoreCase(const String &s) const;\n\tunsigned char startsWith( const String &prefix) const;\n\tunsigned char startsWith(const String &prefix, unsigned int offset) const;\n\tunsigned char endsWith(const String &suffix) const;\n\n\t// character acccess\n\tchar charAt(unsigned int index) const;\n\tvoid setCharAt(unsigned int index, char c);\n\tchar operator [] (unsigned int index) const;\n\tchar& operator [] (unsigned int index);\n\tvoid getBytes(unsigned char *buf, unsigned int bufsize, unsigned int index=0) const;\n\tvoid toCharArray(char *buf, unsigned int bufsize, unsigned int index=0) const\n\t\t{getBytes((unsigned char *)buf, bufsize, index);}\n\tconst char * c_str() const { return buffer; }\n\n\t// search\n\tint indexOf( char ch ) const;\n\tint indexOf( char ch, unsigned int fromIndex ) const;\n\tint indexOf( const String &str ) const;\n\tint indexOf( const String &str, unsigned int fromIndex ) const;\n\tint lastIndexOf( char ch ) const;\n\tint lastIndexOf( char ch, unsigned int fromIndex ) const;\n\tint lastIndexOf( const String &str ) const;\n\tint lastIndexOf( const String &str, unsigned int fromIndex ) const;\n\tString substring( unsigned int beginIndex ) const { return substring(beginIndex, len); };\n\tString substring( unsigned int beginIndex, unsigned int endIndex ) const;\n\n\t// modification\n\tvoid replace(char find, char replace);\n\tvoid replace(const String& find, const String& replace);\n\tvoid remove(unsigned int index);\n\tvoid remove(unsigned int index, unsigned int count);\n\tvoid toLowerCase(void);\n\tvoid toUpperCase(void);\n\tvoid trim(void);\n\n\t// parsing/conversion\n\tlong toInt(void) const;\n\tfloat toFloat(void) const;\n\nprotected:\n\tchar *buffer;\t        // the actual char array\n\tunsigned int capacity;  // the array length minus one (for the '\\0')\n\tunsigned int len;       // the String length (not counting the '\\0')\nprotected:\n\tvoid init(void);\n\tvoid invalidate(void);\n\tunsigned char changeBuffer(unsigned int maxStrLen);\n\tunsigned char concat(const char *cstr, unsigned int length);\n\n\t// copy and move\n\tString & copy(const char *cstr, unsigned int length);\n\tString & copy(const __FlashStringHelper *pstr, unsigned int length);\n\t#ifdef __GXX_EXPERIMENTAL_CXX0X__\n\tvoid move(String &rhs);\n\t#endif\n};\n\nclass StringSumHelper : public String\n{\npublic:\n\tStringSumHelper(const String &s) : String(s) {}\n\tStringSumHelper(const char *p) : String(p) {}\n\tStringSumHelper(char c) : String(c) {}\n\tStringSumHelper(unsigned char num) : String(num) {}\n\tStringSumHelper(int num) : String(num) {}\n\tStringSumHelper(unsigned int num) : String(num) {}\n\tStringSumHelper(long num) : String(num) {}\n\tStringSumHelper(unsigned long num) : String(num) {}\n\tStringSumHelper(float num) : String(num) {}\n\tStringSumHelper(double num) : String(num) {}\n};\n\n#endif  // __cplusplus\n#endif  // String_class_h\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/avr/dtostrf.c",
    "content": "/*\n  dtostrf - Emulation for dtostrf function from avr-libc\n  Copyright (c) 2013 Arduino.  All rights reserved.\n  Written by Cristian Maglie <c.maglie@arduino.cc>\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n  Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <math.h>\n\nchar *dtostrf (double val, signed char width, unsigned char prec, char *sout) {\n  int val_int = (int)val;\n  int decimal_value = (int)(val * pow(10, prec)) - val_int * pow(10, prec);\n  sprintf(sout, \"%d.%d\", val_int, abs(decimal_value));\n  return sout;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/avr/dtostrf.h",
    "content": "/*\n  dtostrf - Emulation for dtostrf function from avr-libc\n  Copyright (c) 2013 Arduino.  All rights reserved.\n  Written by Cristian Maglie <c.maglie@arduino.cc>\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n  Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\nchar *dtostrf (double val, signed char width, unsigned char prec, char *sout);\n\n#ifdef __cplusplus\n}\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/avr/interrupt.h",
    "content": ""
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/avr/pgmspace.h",
    "content": "#ifndef __PGMSPACE_H_\n#define __PGMSPACE_H_ 1\n\n#include <inttypes.h>\n\n#define PROGMEM\n#define PGM_P  const char *\n#define PSTR(str) (str)\n\n#define _SFR_BYTE(n) (n)\n\ntypedef void prog_void;\ntypedef char prog_char;\ntypedef unsigned char prog_uchar;\ntypedef int8_t prog_int8_t;\ntypedef uint8_t prog_uint8_t;\ntypedef int16_t prog_int16_t;\ntypedef uint16_t prog_uint16_t;\ntypedef int32_t prog_int32_t;\ntypedef uint32_t prog_uint32_t;\n\n#define memcpy_P(dest, src, num) memcpy((dest), (src), (num))\n#define strcpy_P(dest, src) strcpy((dest), (src))\n#define strcat_P(dest, src) strcat((dest), (src))\n#define strcmp_P(a, b) strcmp((a), (b))\n#define strstr_P(a, b) strstr((a), (b))\n#define strlen_P(a) strlen((a))\n#define sprintf_P(s, f, ...) sprintf((s), (f), __VA_ARGS__)\n\n#define pgm_read_byte(addr) (*(const unsigned char *)(addr))\n#define pgm_read_word(addr) (*(const unsigned short *)(addr))\n#define pgm_read_dword(addr) (*(const unsigned long *)(addr))\n#define pgm_read_float(addr) (*(const float *)(addr))\n\n#define pgm_read_byte_near(addr) pgm_read_byte(addr)\n#define pgm_read_word_near(addr) pgm_read_word(addr)\n#define pgm_read_dword_near(addr) pgm_read_dword(addr)\n#define pgm_read_float_near(addr) pgm_read_float(addr)\n#define pgm_read_byte_far(addr) pgm_read_byte(addr)\n#define pgm_read_word_far(addr) pgm_read_word(addr)\n#define pgm_read_dword_far(addr) pgm_read_dword(addr)\n#define pgm_read_float_far(addr) pgm_read_float(addr)\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/binary.h",
    "content": "/*\n  binary.h - Definitions for binary constants\n  Copyright (c) 2006 David A. Mellis.  All right reserved.\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n  Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n#ifndef Binary_h\n#define Binary_h\n\n#define B0 0\n#define B00 0\n#define B000 0\n#define B0000 0\n#define B00000 0\n#define B000000 0\n#define B0000000 0\n#define B00000000 0\n#define B1 1\n#define B01 1\n#define B001 1\n#define B0001 1\n#define B00001 1\n#define B000001 1\n#define B0000001 1\n#define B00000001 1\n#define B10 2\n#define B010 2\n#define B0010 2\n#define B00010 2\n#define B000010 2\n#define B0000010 2\n#define B00000010 2\n#define B11 3\n#define B011 3\n#define B0011 3\n#define B00011 3\n#define B000011 3\n#define B0000011 3\n#define B00000011 3\n#define B100 4\n#define B0100 4\n#define B00100 4\n#define B000100 4\n#define B0000100 4\n#define B00000100 4\n#define B101 5\n#define B0101 5\n#define B00101 5\n#define B000101 5\n#define B0000101 5\n#define B00000101 5\n#define B110 6\n#define B0110 6\n#define B00110 6\n#define B000110 6\n#define B0000110 6\n#define B00000110 6\n#define B111 7\n#define B0111 7\n#define B00111 7\n#define B000111 7\n#define B0000111 7\n#define B00000111 7\n#define B1000 8\n#define B01000 8\n#define B001000 8\n#define B0001000 8\n#define B00001000 8\n#define B1001 9\n#define B01001 9\n#define B001001 9\n#define B0001001 9\n#define B00001001 9\n#define B1010 10\n#define B01010 10\n#define B001010 10\n#define B0001010 10\n#define B00001010 10\n#define B1011 11\n#define B01011 11\n#define B001011 11\n#define B0001011 11\n#define B00001011 11\n#define B1100 12\n#define B01100 12\n#define B001100 12\n#define B0001100 12\n#define B00001100 12\n#define B1101 13\n#define B01101 13\n#define B001101 13\n#define B0001101 13\n#define B00001101 13\n#define B1110 14\n#define B01110 14\n#define B001110 14\n#define B0001110 14\n#define B00001110 14\n#define B1111 15\n#define B01111 15\n#define B001111 15\n#define B0001111 15\n#define B00001111 15\n#define B10000 16\n#define B010000 16\n#define B0010000 16\n#define B00010000 16\n#define B10001 17\n#define B010001 17\n#define B0010001 17\n#define B00010001 17\n#define B10010 18\n#define B010010 18\n#define B0010010 18\n#define B00010010 18\n#define B10011 19\n#define B010011 19\n#define B0010011 19\n#define B00010011 19\n#define B10100 20\n#define B010100 20\n#define B0010100 20\n#define B00010100 20\n#define B10101 21\n#define B010101 21\n#define B0010101 21\n#define B00010101 21\n#define B10110 22\n#define B010110 22\n#define B0010110 22\n#define B00010110 22\n#define B10111 23\n#define B010111 23\n#define B0010111 23\n#define B00010111 23\n#define B11000 24\n#define B011000 24\n#define B0011000 24\n#define B00011000 24\n#define B11001 25\n#define B011001 25\n#define B0011001 25\n#define B00011001 25\n#define B11010 26\n#define B011010 26\n#define B0011010 26\n#define B00011010 26\n#define B11011 27\n#define B011011 27\n#define B0011011 27\n#define B00011011 27\n#define B11100 28\n#define B011100 28\n#define B0011100 28\n#define B00011100 28\n#define B11101 29\n#define B011101 29\n#define B0011101 29\n#define B00011101 29\n#define B11110 30\n#define B011110 30\n#define B0011110 30\n#define B00011110 30\n#define B11111 31\n#define B011111 31\n#define B0011111 31\n#define B00011111 31\n#define B100000 32\n#define B0100000 32\n#define B00100000 32\n#define B100001 33\n#define B0100001 33\n#define B00100001 33\n#define B100010 34\n#define B0100010 34\n#define B00100010 34\n#define B100011 35\n#define B0100011 35\n#define B00100011 35\n#define B100100 36\n#define B0100100 36\n#define B00100100 36\n#define B100101 37\n#define B0100101 37\n#define B00100101 37\n#define B100110 38\n#define B0100110 38\n#define B00100110 38\n#define B100111 39\n#define B0100111 39\n#define B00100111 39\n#define B101000 40\n#define B0101000 40\n#define B00101000 40\n#define B101001 41\n#define B0101001 41\n#define B00101001 41\n#define B101010 42\n#define B0101010 42\n#define B00101010 42\n#define B101011 43\n#define B0101011 43\n#define B00101011 43\n#define B101100 44\n#define B0101100 44\n#define B00101100 44\n#define B101101 45\n#define B0101101 45\n#define B00101101 45\n#define B101110 46\n#define B0101110 46\n#define B00101110 46\n#define B101111 47\n#define B0101111 47\n#define B00101111 47\n#define B110000 48\n#define B0110000 48\n#define B00110000 48\n#define B110001 49\n#define B0110001 49\n#define B00110001 49\n#define B110010 50\n#define B0110010 50\n#define B00110010 50\n#define B110011 51\n#define B0110011 51\n#define B00110011 51\n#define B110100 52\n#define B0110100 52\n#define B00110100 52\n#define B110101 53\n#define B0110101 53\n#define B00110101 53\n#define B110110 54\n#define B0110110 54\n#define B00110110 54\n#define B110111 55\n#define B0110111 55\n#define B00110111 55\n#define B111000 56\n#define B0111000 56\n#define B00111000 56\n#define B111001 57\n#define B0111001 57\n#define B00111001 57\n#define B111010 58\n#define B0111010 58\n#define B00111010 58\n#define B111011 59\n#define B0111011 59\n#define B00111011 59\n#define B111100 60\n#define B0111100 60\n#define B00111100 60\n#define B111101 61\n#define B0111101 61\n#define B00111101 61\n#define B111110 62\n#define B0111110 62\n#define B00111110 62\n#define B111111 63\n#define B0111111 63\n#define B00111111 63\n#define B1000000 64\n#define B01000000 64\n#define B1000001 65\n#define B01000001 65\n#define B1000010 66\n#define B01000010 66\n#define B1000011 67\n#define B01000011 67\n#define B1000100 68\n#define B01000100 68\n#define B1000101 69\n#define B01000101 69\n#define B1000110 70\n#define B01000110 70\n#define B1000111 71\n#define B01000111 71\n#define B1001000 72\n#define B01001000 72\n#define B1001001 73\n#define B01001001 73\n#define B1001010 74\n#define B01001010 74\n#define B1001011 75\n#define B01001011 75\n#define B1001100 76\n#define B01001100 76\n#define B1001101 77\n#define B01001101 77\n#define B1001110 78\n#define B01001110 78\n#define B1001111 79\n#define B01001111 79\n#define B1010000 80\n#define B01010000 80\n#define B1010001 81\n#define B01010001 81\n#define B1010010 82\n#define B01010010 82\n#define B1010011 83\n#define B01010011 83\n#define B1010100 84\n#define B01010100 84\n#define B1010101 85\n#define B01010101 85\n#define B1010110 86\n#define B01010110 86\n#define B1010111 87\n#define B01010111 87\n#define B1011000 88\n#define B01011000 88\n#define B1011001 89\n#define B01011001 89\n#define B1011010 90\n#define B01011010 90\n#define B1011011 91\n#define B01011011 91\n#define B1011100 92\n#define B01011100 92\n#define B1011101 93\n#define B01011101 93\n#define B1011110 94\n#define B01011110 94\n#define B1011111 95\n#define B01011111 95\n#define B1100000 96\n#define B01100000 96\n#define B1100001 97\n#define B01100001 97\n#define B1100010 98\n#define B01100010 98\n#define B1100011 99\n#define B01100011 99\n#define B1100100 100\n#define B01100100 100\n#define B1100101 101\n#define B01100101 101\n#define B1100110 102\n#define B01100110 102\n#define B1100111 103\n#define B01100111 103\n#define B1101000 104\n#define B01101000 104\n#define B1101001 105\n#define B01101001 105\n#define B1101010 106\n#define B01101010 106\n#define B1101011 107\n#define B01101011 107\n#define B1101100 108\n#define B01101100 108\n#define B1101101 109\n#define B01101101 109\n#define B1101110 110\n#define B01101110 110\n#define B1101111 111\n#define B01101111 111\n#define B1110000 112\n#define B01110000 112\n#define B1110001 113\n#define B01110001 113\n#define B1110010 114\n#define B01110010 114\n#define B1110011 115\n#define B01110011 115\n#define B1110100 116\n#define B01110100 116\n#define B1110101 117\n#define B01110101 117\n#define B1110110 118\n#define B01110110 118\n#define B1110111 119\n#define B01110111 119\n#define B1111000 120\n#define B01111000 120\n#define B1111001 121\n#define B01111001 121\n#define B1111010 122\n#define B01111010 122\n#define B1111011 123\n#define B01111011 123\n#define B1111100 124\n#define B01111100 124\n#define B1111101 125\n#define B01111101 125\n#define B1111110 126\n#define B01111110 126\n#define B1111111 127\n#define B01111111 127\n#define B10000000 128\n#define B10000001 129\n#define B10000010 130\n#define B10000011 131\n#define B10000100 132\n#define B10000101 133\n#define B10000110 134\n#define B10000111 135\n#define B10001000 136\n#define B10001001 137\n#define B10001010 138\n#define B10001011 139\n#define B10001100 140\n#define B10001101 141\n#define B10001110 142\n#define B10001111 143\n#define B10010000 144\n#define B10010001 145\n#define B10010010 146\n#define B10010011 147\n#define B10010100 148\n#define B10010101 149\n#define B10010110 150\n#define B10010111 151\n#define B10011000 152\n#define B10011001 153\n#define B10011010 154\n#define B10011011 155\n#define B10011100 156\n#define B10011101 157\n#define B10011110 158\n#define B10011111 159\n#define B10100000 160\n#define B10100001 161\n#define B10100010 162\n#define B10100011 163\n#define B10100100 164\n#define B10100101 165\n#define B10100110 166\n#define B10100111 167\n#define B10101000 168\n#define B10101001 169\n#define B10101010 170\n#define B10101011 171\n#define B10101100 172\n#define B10101101 173\n#define B10101110 174\n#define B10101111 175\n#define B10110000 176\n#define B10110001 177\n#define B10110010 178\n#define B10110011 179\n#define B10110100 180\n#define B10110101 181\n#define B10110110 182\n#define B10110111 183\n#define B10111000 184\n#define B10111001 185\n#define B10111010 186\n#define B10111011 187\n#define B10111100 188\n#define B10111101 189\n#define B10111110 190\n#define B10111111 191\n#define B11000000 192\n#define B11000001 193\n#define B11000010 194\n#define B11000011 195\n#define B11000100 196\n#define B11000101 197\n#define B11000110 198\n#define B11000111 199\n#define B11001000 200\n#define B11001001 201\n#define B11001010 202\n#define B11001011 203\n#define B11001100 204\n#define B11001101 205\n#define B11001110 206\n#define B11001111 207\n#define B11010000 208\n#define B11010001 209\n#define B11010010 210\n#define B11010011 211\n#define B11010100 212\n#define B11010101 213\n#define B11010110 214\n#define B11010111 215\n#define B11011000 216\n#define B11011001 217\n#define B11011010 218\n#define B11011011 219\n#define B11011100 220\n#define B11011101 221\n#define B11011110 222\n#define B11011111 223\n#define B11100000 224\n#define B11100001 225\n#define B11100010 226\n#define B11100011 227\n#define B11100100 228\n#define B11100101 229\n#define B11100110 230\n#define B11100111 231\n#define B11101000 232\n#define B11101001 233\n#define B11101010 234\n#define B11101011 235\n#define B11101100 236\n#define B11101101 237\n#define B11101110 238\n#define B11101111 239\n#define B11110000 240\n#define B11110001 241\n#define B11110010 242\n#define B11110011 243\n#define B11110100 244\n#define B11110101 245\n#define B11110110 246\n#define B11110111 247\n#define B11111000 248\n#define B11111001 249\n#define B11111010 250\n#define B11111011 251\n#define B11111100 252\n#define B11111101 253\n#define B11111110 254\n#define B11111111 255\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/digitalWriteFast.h",
    "content": "/*\n  digitalWriteFast.h - A faster digitalWrite and digitalRead\n  ...based partially on digitalWrite fast code by Paul Stoffregen,\n  as part of Teensyduino and partially based off of the earlier\n  arduino version http://code.google.com/p/digitalwritefast\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n  Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n/* Only want to process this if pin count has been defined which inplies that the full variant.h has been read */\n\n#ifdef PINS_COUNT \n#ifndef _DIGITAL_WRITE_FAST_\n#define _DIGITAL_WRITE_FAST_\n\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\nstatic inline void digitalWriteFast(uint8_t, uint8_t) __attribute__((always_inline, unused));\nstatic inline void digitalWriteFast(uint8_t pin, uint8_t val)\n{\n  if (__builtin_constant_p(pin)) {\n    if (val) {\n      if(pin < PINS_COUNT - 1) {\n        g_Pin2PortMapArray[pin].GPIOx_Port->BSRR = g_Pin2PortMapArray[pin].Pin_abstraction;\n      }\n    } else {\n      if (pin < PINS_COUNT - 1) {\n        g_Pin2PortMapArray[pin].GPIOx_Port->BSRR = (g_Pin2PortMapArray[pin].Pin_abstraction << 16);\n      }\n    }\n  } else {\n    digitalWrite(pin, val);\n  }\n}\n\n\nstatic inline int digitalReadFast(uint8_t) __attribute__((always_inline, unused));\nstatic inline int digitalReadFast(uint8_t pin)\n{\n  if (__builtin_constant_p(pin)) {\n    if (pin < PINS_COUNT - 1) {\n      return (g_Pin2PortMapArray[pin].GPIOx_Port->IDR & g_Pin2PortMapArray[pin].Pin_abstraction)? HIGH : LOW;\n    }\n  } \n  return digitalRead(pin);\n}\n\n\n#ifdef __cplusplus\n} // extern \"C\"\n#endif // __cplusplus\n\n\n#endif /* _DIGITAL_WRITE_FAST_ */\n#endif /* PINS_COUNT */"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/itoa.c",
    "content": "/*\n  Copyright (c) 2011 Arduino.  All right reserved.\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n  See the GNU Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n#include \"itoa.h\"\n#include <string.h>\n\n#ifdef __cplusplus\nextern \"C\"{\n#endif // __cplusplus\n\n\nextern char* itoa( int value, char *string, int radix )\n{\n  return ltoa( value, string, radix ) ;\n}\n\nextern char* ltoa( long value, char *string, int radix )\n{\n  char tmp[33];\n  char *tp = tmp;\n  long i;\n  unsigned long v;\n  int sign;\n  char *sp;\n\n  if ( string == NULL )\n  {\n    return 0 ;\n  }\n\n  if (radix > 36 || radix <= 1)\n  {\n    return 0 ;\n  }\n\n  sign = (radix == 10 && value < 0);\n  if (sign)\n  {\n    v = -value;\n  }\n  else\n  {\n    v = (unsigned long)value;\n  }\n\n  while (v || tp == tmp)\n  {\n    i = v % radix;\n    v = v / radix;\n    if (i < 10)\n      *tp++ = i+'0';\n    else\n      *tp++ = i + 'a' - 10;\n  }\n\n  sp = string;\n\n  if (sign)\n    *sp++ = '-';\n  while (tp > tmp)\n    *sp++ = *--tp;\n  *sp = 0;\n\n  return string;\n}\n\nextern char* utoa( unsigned long value, char *string, int radix )\n{\n  return ultoa( value, string, radix ) ;\n}\n\nextern char* ultoa( unsigned long value, char *string, int radix )\n{\n  char tmp[33];\n  char *tp = tmp;\n  long i;\n  unsigned long v = value;\n  char *sp;\n\n  if ( string == NULL )\n  {\n    return 0;\n  }\n\n  if (radix > 36 || radix <= 1)\n  {\n    return 0;\n  }\n\n  while (v || tp == tmp)\n  {\n    i = v % radix;\n    v = v / radix;\n    if (i < 10)\n      *tp++ = i+'0';\n    else\n      *tp++ = i + 'a' - 10;\n  }\n\n  sp = string;\n\n\n  while (tp > tmp)\n    *sp++ = *--tp;\n  *sp = 0;\n\n  return string;\n}\n\n\n#ifdef __cplusplus\n} // extern \"C\"\n#endif // __cplusplus\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/itoa.h",
    "content": "/*\n  Copyright (c) 2011 Arduino.  All right reserved.\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. \n  See the GNU Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n#ifndef _ITOA_\n#define _ITOA_\n\n#ifdef __cplusplus\nextern \"C\"{\n#endif // __cplusplus\n\n#if 0\n\nextern void itoa( int n, char s[] ) ;\n\n#else\n\nextern char* itoa( int value, char *string, int radix ) ;\nextern char* ltoa( long value, char *string, int radix ) ;\n//extern char* utoa( unsigned long value, char *string, int radix ) ;\nextern char* ultoa( unsigned long value, char *string, int radix ) ;\n#endif /* 0 */\n\n#ifdef __cplusplus\n} // extern \"C\"\n#endif // __cplusplus\n\n#endif // _ITOA_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/new.cpp",
    "content": "/*\n  Copyright (c) 2014 Arduino.  All right reserved.\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. \n  See the GNU Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n#include <stdlib.h>\n\nvoid *operator new(size_t size) {\n  return malloc(size);\n}\n\nvoid *operator new[](size_t size) {\n  return malloc(size);\n}\n\nvoid operator delete(void * ptr) {\n  free(ptr);\n}\n\nvoid operator delete[](void * ptr) {\n  free(ptr);\n}\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/syscalls.h",
    "content": "/*\n  Copyright (c) 2011 Arduino.  All right reserved.\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. \n  See the GNU Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n/**\n  * \\file syscalls.h\n  *\n  * Implementation of newlib syscall.\n  *\n  */\n\n/*----------------------------------------------------------------------------\n *        Headers\n *----------------------------------------------------------------------------*/\n#include <stdio.h>\n#include <stdarg.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n\n/*----------------------------------------------------------------------------\n *        Exported functions\n *----------------------------------------------------------------------------*/\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\nextern caddr_t _sbrk( int incr ) ;\n\nextern int link( char *cOld, char *cNew ) ;\n\nextern int _close( int file ) ;\n\nextern int _fstat( int file, struct stat *st ) ;\n\nextern int _isatty( int file ) ;\n\nextern int _lseek( int file, int ptr, int dir ) ;\n\nextern int _read(int file, char *ptr, int len) ;\n\nextern int _write( int file, char *ptr, int len ) ;\n\n#ifdef __cplusplus\n}\n#endif\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/wiring.c",
    "content": "/*\n  Copyright (c) 2011 Arduino.  All right reserved.\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n  See the GNU Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n#include \"Arduino.h\"\n#include \"drv_micros.h\"\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n\t/*\n\t\tThere is enough abstract similarity to Arduino that for some of these\n\t\twe can just do the function with a define in the chip.h header\n\n\t\t#define millis HAL_GetTick\n\t\t#define delay HAL_Delay\n\t*/\n\n\n/* \n\tNot sure how to do micros when the system clock ticks in milliseconds\n\t\n\t\n*/ \nuint32_t micros( void )\n{\n\treturn drv_micros();\n}\n\n#ifdef __cplusplus\n}\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/wiring.h",
    "content": "/*\n  Copyright (c) 2011 Arduino.  All right reserved.\n  Copyright (c) 2013 by Paul Stoffregen <paul@pjrc.com> (delayMicroseconds)\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. \n  See the GNU Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n#ifndef _WIRING_\n#define _WIRING_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n *\n */\nextern void initVariant( void ) ;\nextern void init( void ) ;\n\n/**\n * \\brief Returns the number of milliseconds since the Arduino board began running the current program.\n *\n * This number will overflow (go back to zero), after approximately 50 days.\n *\n * \\return Number of milliseconds since the program started (uint32_t)\n */\nextern uint32_t millis( void ) ;\n\n/**\n * \\brief Returns the number of microseconds since the Arduino board began running the current program.\n *\n * This number will overflow (go back to zero), after approximately 70 minutes. On 16 MHz Arduino boards\n * (e.g. Duemilanove and Nano), this function has a resolution of four microseconds (i.e. the value returned is\n * always a multiple of four). On 8 MHz Arduino boards (e.g. the LilyPad), this function has a resolution\n * of eight microseconds.\n *\n * \\note There are 1,000 microseconds in a millisecond and 1,000,000 microseconds in a second.\n */\nextern uint32_t micros( void ) ;\n\n/**\n * \\brief Pauses the program for the amount of time (in miliseconds) specified as parameter.\n * (There are 1000 milliseconds in a second.)\n *\n * \\param dwMs the number of milliseconds to pause (uint32_t)\n */\nextern void delay( uint32_t dwMs ) ;\n\n/**\n * \\brief Pauses the program for the amount of time (in microseconds) specified as parameter.\n *\n * \\param dwUs the number of microseconds to pause (uint32_t)\n */\n\nstatic inline void delayMicroseconds(uint32_t) __attribute__((always_inline, unused));\nstatic inline void delayMicroseconds(uint32_t usec){\n  uint32_t tTime;\n\n  tTime = micros();\n\n  while( (micros()-tTime) < usec );\n\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _WIRING_ */\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/wiring_analog.c",
    "content": "/*\n   Copyright (c) 2011 Arduino.  All right reserved.\n   This library is free software; you can redistribute it and/or\n   modify it under the terms of the GNU Lesser General Public\n   License as published by the Free Software Foundation; either\n   version 2.1 of the License, or (at your option) any later version.\n   This library is distributed in the hope that it will be useful,\n   but WITHOUT ANY WARRANTY; without even the implied warranty of\n   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n   See the GNU Lesser General Public License for more details.\n   You should have received a copy of the GNU Lesser General Public\n   License along with this library; if not, write to the Free Software\n   Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n */\n#include \"Arduino.h\"\n#include \"variant.h\"\n\nuint8_t analog_reference = DEFAULT;\n\n\nstatic int _readResolution = 10;\nstatic int _writeResolution = 8;\nint readResolBackup = -1;\nint writeResolBackup = -1;\n\n\n\nvoid analogReadResolution(int res) {\n\t_readResolution = res;\n}\n\n\nvoid analogWriteResolution(int res) {\n\t_writeResolution = res;\n}\n\nstatic inline uint32_t mapResolution(uint32_t value, uint32_t from, uint32_t to) {\n\tif (from == to)\n\t\treturn value;\n\tif (from > to)\n\t\treturn value >> (from-to);\n\telse\n\t\treturn value << (to-from);\n}\n\nvoid analogReference(uint8_t mode){\n\tanalog_reference = mode;\n}\n\nuint32_t analogRead( uint32_t ulPin ){ \n \n  ADC_ChannelConfTypeDef sConfig;\n  ADC_HandleTypeDef      *hADCx;\n\tuint32_t ulValue = 0;\n  uint32_t ulChannel;\n  uint32_t adc_pin;\n\n\n  adc_pin = analogPinToChannel(ulPin);\n\n  ulChannel = g_Pin2PortMapArray[adc_pin].adc_channel;\n  \n  if(ulChannel == NO_ADC)\n      return -1;\n\n  hADCx = g_Pin2PortMapArray[adc_pin].ADCx;\n\n  sConfig.Channel      = ulChannel;\n  sConfig.Rank         = 1;\n  sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;\n  sConfig.Offset       = 0;\n  HAL_ADC_ConfigChannel(hADCx, &sConfig);\n  \n  HAL_ADC_Start(hADCx);\n  HAL_ADC_PollForConversion(hADCx, 10);\n  ulValue = HAL_ADC_GetValue(hADCx);\n\n  ulValue = mapResolution(ulValue, 12, _readResolution);\n \n  return ulValue;\n}\n\n\nvoid analogWrite( uint32_t ulPin, uint32_t ulValue ){\n\n  if( drv_pwm_get_init(ulPin) == false )\n  {\n    drv_pwm_setup(ulPin);\n  }\n  \n  drv_pwm_set_duty(ulPin, _writeResolution, ulValue);\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/wiring_analog.h",
    "content": "/*\n  Copyright (c) 2011 Arduino.  All right reserved.\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. \n  See the GNU Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n#ifndef _WIRING_ANALOG_\n#define _WIRING_ANALOG_\n\n//#include \"stm32f1xx_hal.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n#define MAX_PWM_PIN 32\n\nextern ADC_HandleTypeDef hadc1;\nextern ADC_HandleTypeDef hadc2;\n\nextern TIM_HandleTypeDef htim1;\nextern TIM_HandleTypeDef htim2;\nextern TIM_HandleTypeDef htim3;\nextern TIM_HandleTypeDef htim4;\n\n/*\n * \\brief SAM3 products have only one reference for ADC\n */\ntypedef enum _eAnalogReference\n{\n  AR_DEFAULT,\n} eAnalogReference ;\n\n/*\n * \\brief Configures the reference voltage used for analog input (i.e. the value used as the top of the input range).\n * This function is kept only for compatibility with existing AVR based API.\n *\n * \\param ulMmode Should be set to AR_DEFAULT.\n */\nextern void analogReference( eAnalogReference ulMode ) ;\n\n/*\n * \\brief Writes an analog value (PWM wave) to a pin.\n *\n * \\param ulPin\n * \\param ulValue\n */\nextern void analogWrite( uint32_t ulPin, uint32_t ulValue ) ;\n\n/*\n * \\brief Reads the value from the specified analog pin.\n *\n * \\param ulPin\n *\n * \\return Read value from selected pin, if no error.\n */\nextern uint32_t analogRead( uint32_t ulPin ) ;\n\n/*\n * \\brief Set the resolution of analogRead return values. Default is 10 bits (range from 0 to 1023).\n *\n * \\param res\n */\nextern void analogReadResolution(int res);\n\n/*\n * \\brief Set the resolution of analogWrite parameters. Default is 8 bits (range from 0 to 255).\n *\n * \\param res\n */\nextern void analogWriteResolution(int res);\n\nextern void analogOutputInit( void ) ;\n\nextern void MX_TIMx_Init(uint32_t \tulPin);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _WIRING_ANALOG_ */\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/wiring_constants.h",
    "content": "/*\r\n  Copyright (c) 2011 Arduino.  All right reserved.\r\n\r\n  This library is free software; you can redistribute it and/or\r\n  modify it under the terms of the GNU Lesser General Public\r\n  License as published by the Free Software Foundation; either\r\n  version 2.1 of the License, or (at your option) any later version.\r\n\r\n  This library is distributed in the hope that it will be useful,\r\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\r\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\r\n  See the GNU Lesser General Public License for more details.\r\n\r\n  You should have received a copy of the GNU Lesser General Public\r\n  License along with this library; if not, write to the Free Software\r\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\r\n*/\r\n\r\n#ifndef _WIRING_CONSTANTS_\r\n#define _WIRING_CONSTANTS_\r\n\r\n#ifdef __cplusplus\r\nextern \"C\"{\r\n#endif // __cplusplus\r\n\r\n#define HIGH 0x1\r\n#define LOW  0x0\r\n\r\n#define INPUT           0x0\r\n#define OUTPUT          0x1\r\n#define INPUT_PULLUP    0x2\r\n#define INPUT_ANALOG    0x3\r\n#define INPUT_PULLDOWN  0x4\r\n#define OUTPUT_OPEN     0x5\r\n\r\n//#define true 0x1\r\n//#define false 0x0\r\n\r\n#define PI              3.1415926535897932384626433832795\r\n#define HALF_PI         1.5707963267948966192313216916398\r\n#define TWO_PI          6.283185307179586476925286766559\r\n#define DEG_TO_RAD      0.017453292519943295769236907684886\r\n#define RAD_TO_DEG      57.295779513082320876798154814105\r\n#define EULER           2.718281828459045235360287471352\r\n\r\n#define SERIAL  0x0\r\n#define DISPLAY 0x1\r\n\r\nenum BitOrder {\r\n\tLSBFIRST = 0,\r\n\tMSBFIRST = 1\r\n};\r\n\r\n//      LOW 0\r\n//      HIGH 1\r\n#define CHANGE 2\r\n#define FALLING 3\r\n#define RISING 4\r\n\r\n#define DEFAULT 1\r\n#define EXTERNAL 0\r\n\r\n// undefine stdlib's abs if encountered\r\n#ifdef abs\r\n#undef abs\r\n#endif // abs\r\n\r\n#ifndef min\r\n#define min(a,b) ((a)<(b)?(a):(b))\r\n#endif // min\r\n\r\n#ifndef max\r\n#define max(a,b) ((a)>(b)?(a):(b))\r\n#endif // max\r\n\r\n#define abs(x)                  ((x)>0?(x):-(x))\r\n#define constrain(amt,low,high) ((amt)<=(low)?(low):((amt)>=(high)?(high):(amt)))\r\n//#define round(x)                ((x)>=0?(long)((x)+0.5):(long)((x)-0.5))\r\n#define radians(deg)            ((deg)*DEG_TO_RAD)\r\n#define degrees(rad)            ((rad)*RAD_TO_DEG)\r\n#define sq(x)                   ((x)*(x))\r\n\r\n#define interrupts()            __enable_irq()\r\n#define noInterrupts()          __disable_irq()\r\n\r\n#define lowByte(w)              ((uint8_t) ((w) & 0xff))\r\n#define highByte(w)             ((uint8_t) ((w) >> 8))\r\n\r\n#define bitRead(value, bit)     (((value) >> (bit)) & 0x01)\r\n#define bitSet(value, bit)      ((value) |= (1UL << (bit)))\r\n#define bitClear(value, bit)    ((value) &= ~(1UL << (bit)))\r\n#define bitWrite(value, bit, bitvalue) (bitvalue ? bitSet(value, bit) : bitClear(value, bit))\r\n\r\ntypedef unsigned int word;\r\n\r\n#define bit(b) (1UL << (b))\r\n\r\ntypedef bool boolean ;\r\ntypedef uint8_t byte ;\r\n\r\n#ifdef __cplusplus\r\n} // extern \"C\"\r\n#endif // __cplusplus\r\n\r\n#endif /* _WIRING_CONSTANTS_ */\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/wiring_digital.c",
    "content": "/*\n  Copyright (c) 2011 Arduino.  All right reserved.\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n  See the GNU Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n#include \"Arduino.h\"\n#include \"variant.h\"\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n\t/*\n\n\t\tthe HAL drivers for STM32 do no access the registers directly\n\t\topaque structures are used to abstract the functions needed\n\n\t\texisting STM examples show this defined locally a static\n\t\t'static GPIO_InitTypeDef  GPIO_InitStruct;'\n\n\t\tvalue which we set here.  This is different than the\n\t\tway maple and sam set the pins as they use a global\n\t\tarray that contains device specific register setting values\n\n\n\t\tGPIO_InitTypeDef has the following members defined in stm32f4xx_hal_gpio.h:\n\n  uint32_t Pin\t\tSpecifies the GPIO pins to be configured.\n\t\t\t\t\ttypically a bitmapped mask that can be stored in a 16 bit value\n\n  uint32_t Mode\t\tSpecifies the operating mode for the selected pins.\n                    There are a number of modes that can be defined.\nGPIO_MODE_INPUT\t\t        \tInput Floating Mode\nGPIO_MODE_OUTPUT_PP        \t\tOutput Push Pull Mode\nGPIO_MODE_OUTPUT_OD        \t\tOutput Open Drain Mode\nGPIO_MODE_AF_PP            \t\tAlternate Function Push Pull Mode\nGPIO_MODE_AF_OD            \t\tAlternate Function Open Drain Mode\n\nGPIO_MODE_ANALOG           \t\tAnalog Mode\n\nGPIO_MODE_IT_RISING        \t\tExternal Interrupt Mode with Rising edge trigger detection\nGPIO_MODE_IT_FALLING       \t\tExternal Interrupt Mode with Falling edge trigger detection\nGPIO_MODE_IT_RISING_FALLING\t\tExternal Interrupt Mode with Rising/Falling edge trigger detection\n\nGPIO_MODE_EVT_RISING       \t\tExternal Event Mode with Rising edge trigger detection\nGPIO_MODE_EVT_FALLING      \t\tExternal Event Mode with Falling edge trigger detection\nGPIO_MODE_EVT_RISING_FALLING\tExternal Event Mode with Rising/Falling edge trigger detection\n\n\n  uint32_t Pull\t\tSpecifies the Pull-up or Pull-Down activation for the selected pins.\nGPIO_NOPULL\t\t\t\t\t\tNo Pull-up or Pull-down activation\nGPIO_PULLUP\t\t\t\t\t\tPull-up activation\nGPIO_PULLDOWN\t\t\t\t\tPull-down activation\n\n  uint32_t Speed\tSpecifies the speed for the selected pins.\nGPIO_SPEED_LOW\t\t\t\t\tLow speed\nGPIO_SPEED_MEDIUM\t\t\t\tMedium speed\nGPIO_SPEED_FAST\t\t\t\t\tFast speed\nGPIO_SPEED_HIGH\t\t\t\t\tHigh speed\n\n  uint32_t Alternate\tPeripheral to be connected to the selected pins.\n                        these are defined in stm32f4xx_hal_gpio_ex.h\n                        not all calls to HAL_GPIO_Init require this value to\n                        be set in the existing example code\n\n\n*/\n\n\n\n\nextern void pinMode( uint32_t ulPin, uint32_t ulMode )\n{\n\tGPIO_InitTypeDef  GPIO_InitStruct;\n\n\n\tGPIO_InitStruct.Pin = g_Pin2PortMapArray[ulPin].Pin_abstraction;\n\n\tdrv_pwm_release(ulPin);\n\n\n\tswitch ( ulMode )\n\t{\n\t  case INPUT:\n\t    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;\n\t    GPIO_InitStruct.Pull = GPIO_NOPULL;\n\t    break ;\n\n\t  case INPUT_PULLUP:\n\t\t\tGPIO_InitStruct.Mode = GPIO_MODE_INPUT;\n\t\t\tGPIO_InitStruct.Pull = GPIO_PULLUP;\n\t\t\tbreak ;\n\n\t  case INPUT_PULLDOWN:\n      GPIO_InitStruct.Mode = GPIO_MODE_INPUT;\n      GPIO_InitStruct.Pull = GPIO_PULLDOWN;\n\t    break;\n\n\t  case OUTPUT:\n \t\t\tGPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;\n \t\t\tGPIO_InitStruct.Pull = GPIO_NOPULL;\n \t\t\tbreak ;\n\n    case OUTPUT_OPEN:\n      GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;\n \t\t\tGPIO_InitStruct.Pull = GPIO_NOPULL;\n      break;\n\n\t  case INPUT_ANALOG:\n\t    drv_adc_pin_init(ulPin);\n\t    break;\n\n\t  default:\n\t    break ;\n\t}\n\n\tif( ulMode != INPUT_ANALOG )\n\t{\n\t  GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;\n\t  HAL_GPIO_Init(g_Pin2PortMapArray[ulPin].GPIOx_Port, &GPIO_InitStruct);\n\t}\n}\n\nextern void digitalWrite( uint32_t ulPin, uint32_t ulVal )\n{\n\n  switch(ulVal) {\n\n    case HIGH:\n\t\t\t/*\n\t\t\t\t\tAVR allows for the writing of inputs to set the pull up state\n\t\t\t\t\twe may want to do this here as well to maintain compatibility.\n\t\t\t*/\n      HAL_GPIO_WritePin(g_Pin2PortMapArray[ulPin].GPIOx_Port,g_Pin2PortMapArray[ulPin].Pin_abstraction,GPIO_PIN_SET);\n\t\t\tbreak;\n\n    case LOW:\n      /* simply reset the pin */\n      HAL_GPIO_WritePin(g_Pin2PortMapArray[ulPin].GPIOx_Port,g_Pin2PortMapArray[ulPin].Pin_abstraction,GPIO_PIN_RESET);\n\t\t\tbreak;\n\n    default:\n      /* should do an assert here to handle error conditions */\n\t\t\tbreak;\n  }\n}\n\nextern int digitalRead( uint32_t ulPin )\n{\n\tif(HAL_GPIO_ReadPin(g_Pin2PortMapArray[ulPin].GPIOx_Port,g_Pin2PortMapArray[ulPin].Pin_abstraction) == GPIO_PIN_RESET)\n\t{\n\t\treturn LOW; // Set from HIGH to LOW by Vassilis Serasidis\n\t}\n\n\treturn HIGH ; // Set from LOW to HIGH by Vassilis Serasidis\n}\n\n#ifdef __cplusplus\n}\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/wiring_digital.h",
    "content": "/*\n  Copyright (c) 2011 Arduino.  All right reserved.\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. \n  See the GNU Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n#ifndef _WIRING_DIGITAL_\n#define _WIRING_DIGITAL_\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n * \\brief Configures the specified pin to behave either as an input or an output. See the description of digital pins for details.\n *\n * \\param ulPin The number of the pin whose mode you wish to set\n * \\param ulMode Either INPUT or OUTPUT\n */\nextern void pinMode( uint32_t dwPin, uint32_t dwMode ) ;\n\n/**\n * \\brief Write a HIGH or a LOW value to a digital pin.\n *\n * If the pin has been configured as an OUTPUT with pinMode(), its voltage will be set to the\n * corresponding value: 5V (or 3.3V on 3.3V boards) for HIGH, 0V (ground) for LOW.\n *\n * If the pin is configured as an INPUT, writing a HIGH value with digitalWrite() will enable an internal\n * 20K pullup resistor (see the tutorial on digital pins). Writing LOW will disable the pullup. The pullup\n * resistor is enough to light an LED dimly, so if LEDs appear to work, but very dimly, this is a likely\n * cause. The remedy is to set the pin to an output with the pinMode() function.\n *\n * \\note Digital pin PIN_LED is harder to use as a digital input than the other digital pins because it has an LED\n * and resistor attached to it that's soldered to the board on most boards. If you enable its internal 20k pull-up\n * resistor, it will hang at around 1.7 V instead of the expected 5V because the onboard LED and series resistor\n * pull the voltage level down, meaning it always returns LOW. If you must use pin PIN_LED as a digital input, use an\n * external pull down resistor.\n *\n * \\param dwPin the pin number\n * \\param dwVal HIGH or LOW\n */\nextern void digitalWrite( uint32_t dwPin, uint32_t dwVal ) ;\n\n/**\n * \\brief Reads the value from a specified digital pin, either HIGH or LOW.\n *\n * \\param ulPin The number of the digital pin you want to read (int)\n *\n * \\return HIGH or LOW\n */\nextern int digitalRead( uint32_t ulPin ) ;\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _WIRING_DIGITAL_ */\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/wiring_private.h",
    "content": "/*\n  Copyright (c) 2011 Arduino.  All right reserved.\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. \n  See the GNU Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n#ifndef WiringPrivate_h\n#define WiringPrivate_h\n\n#include <stdint.h>\n#include <stdio.h>\n#include <stdarg.h>\n\n#ifdef __cplusplus\nextern \"C\"{\n#endif\n\n// Includes Atmel CMSIS\n#include <chip.h>\n\n#include \"wiring_constants.h\"\n\n#ifdef __cplusplus\n} // extern \"C\"\n\n#include \"HardwareSerial.h\"\n\n#endif\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/wiring_pulse.c",
    "content": "/*\n  Copyright (c) 2011 Arduino.  All right reserved.\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n  See the GNU Lesser General Public License for more details.\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n#include \"Arduino.h\"\n#include \"variant.h\"\n\n/* Measures the length (in microseconds) of a pulse on the pin; state is HIGH\n * or LOW, the type of pulse to measure.  Works on pulses from 2-3 microseconds\n * to 3 minutes in length, but must be called at least a few dozen microseconds\n * before the start of the pulse.\n *\n * ATTENTION:\n * this function relies on micros() so cannot be used in noInterrupt() context\n */\n\n //This function is from pulseInLong func\nuint32_t pulseIn( uint32_t ulPin, uint32_t state, uint32_t timeout )\n{\n    // cache the port and bit of the pin in order to speed up the\n   // pulse width measuring loop and achieve finer resolution.  calling\n   // digitalRead() instead yields much coarser resolution.\n   uint16_t bit = g_Pin2PortMapArray[ulPin].Pin_abstraction;\n   unsigned long stateMask = state ? bit : 0;\n\n   unsigned long startMicros = micros();\n\n   // wait for any previous pulse to end\n   while ((g_Pin2PortMapArray[ulPin].GPIOx_Port->IDR & bit) == stateMask)\n    if (micros() - startMicros > timeout)\n         return 0;\n\n   // wait for the pulse to start\n   while ((g_Pin2PortMapArray[ulPin].GPIOx_Port->IDR & bit) != stateMask)\n     if (micros() - startMicros > timeout)\n         return 0;\n\n   unsigned long start = micros();\n   // wait for the pulse to stop\n   while ((g_Pin2PortMapArray[ulPin].GPIOx_Port->IDR & bit) == stateMask){\n      if (micros() - startMicros > timeout)\n         return 0;\n   }\n\n   return micros() - start;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/wiring_pulse.h",
    "content": "/*\n  Copyright (c) 2011 Arduino.  All right reserved.\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. \n  See the GNU Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n#ifndef _WIRING_PULSE_\n#define _WIRING_PULSE_\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/*\n * \\brief Measures the length (in microseconds) of a pulse on the pin; state is HIGH\n * or LOW, the type of pulse to measure.  Works on pulses from 2-3 microseconds\n * to 3 minutes in length, but must be called at least a few dozen microseconds\n * before the start of the pulse.\n */\nextern uint32_t pulseIn( uint32_t ulPin, uint32_t ulState, uint32_t ulTimeout = 1000000L ) ;\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _WIRING_PULSE_ */\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/wiring_shift.c",
    "content": "/*\n  Copyright (c) 2011 Arduino.  All right reserved.\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. \n  See the GNU Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n#include \"Arduino.h\"\n\n#ifdef __cplusplus\nextern \"C\"{\n#endif\n\nuint32_t shiftIn( uint32_t ulDataPin, uint32_t ulClockPin, uint32_t ulBitOrder )\n{\n\tuint8_t value = 0 ;\n\tuint8_t i ;\n\n\tfor ( i=0 ; i < 8 ; ++i )\n    {\n\t\tdigitalWrite( ulClockPin, HIGH ) ;\n\n\t\tif ( ulBitOrder == LSBFIRST )\n        {\n\t\t\tvalue |= digitalRead( ulDataPin ) << i ;\n        }\n\t\telse\n        {\n\t\t\tvalue |= digitalRead( ulDataPin ) << (7 - i) ;\n        }\n\n\t\tdigitalWrite( ulClockPin, LOW ) ;\n\t}\n\n\treturn value ;\n}\n\nvoid shiftOut( uint32_t ulDataPin, uint32_t ulClockPin, uint32_t ulBitOrder, uint32_t ulVal )\n{\n\tuint8_t i ;\n\n\tfor ( i=0 ; i < 8 ; i++ )\n    {\n\t\tif ( ulBitOrder == LSBFIRST )\n        {\n\t\t\tdigitalWrite( ulDataPin, !!(ulVal & (1 << i)) ) ;\n        }\n\t\telse\t\n        {\n\t\t\tdigitalWrite( ulDataPin, !!(ulVal & (1 << (7 - i))) ) ;\n        }\n\n\t\tdigitalWrite( ulClockPin, HIGH ) ;\n\t\tdigitalWrite( ulClockPin, LOW ) ;\t\t\n\t}\n}\n\n#ifdef __cplusplus\n} // extern \"C\"\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/wiring_shift.h",
    "content": "/*\n  Copyright (c) 2011 Arduino.  All right reserved.\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. \n  See the GNU Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n#ifndef _WIRING_SHIFT_\n#define _WIRING_SHIFT_\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/*\n * \\brief\n */\nextern uint32_t shiftIn( uint32_t ulDataPin, uint32_t ulClockPin, uint32_t ulBitOrder ) ;\n\n\n/*\n * \\brief\n */\nextern void shiftOut( uint32_t ulDataPin, uint32_t ulClockPin, uint32_t ulBitOrder, uint32_t ulVal ) ;\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _WIRING_SHIFT_ */\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/cores/arduino/yield.cpp",
    "content": "#include <Arduino.h>\n\n\nvoid yield(void)\n{\n  //TODO : code implementations\n};"
  },
  {
    "path": "arduino/opencr_arduino/opencr/keywords.txt",
    "content": "# OpenCR specific functions\nSerial4\tKEYWORD1\nprintf\tKEYWORD2\nflushRx\tKEYWORD2\ngetBaudRate\tKEYWORD2\ngetRxCnt\tKEYWORD2\ngetTxCnt\tKEYWORD2\n\n# Arduino constants\n\n# advanced pin states\nOUTPUT_OPEN\tLITERAL1\nINPUT_PULLDOWN\tLITERAL1\nINPUT_ANALOG\tLITERAL1\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Adafruit_GFX.cpp",
    "content": "/*\nThis is the core graphics library for all our displays, providing a common\nset of graphics primitives (points, lines, circles, etc.).  It needs to be\npaired with a hardware-specific library for each display device we carry\n(to handle the lower-level functions).\n\nAdafruit invests time and resources providing this open source code, please\nsupport Adafruit & open-source hardware by purchasing products from Adafruit!\n\nCopyright (c) 2013 Adafruit Industries.  All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n- Redistributions of source code must retain the above copyright notice,\n  this list of conditions and the following disclaimer.\n- Redistributions in binary form must reproduce the above copyright notice,\n  this list of conditions and the following disclaimer in the documentation\n  and/or other materials provided with the distribution.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \"Adafruit_GFX.h\"\n#include \"glcdfont.c\"\n#ifdef __AVR__\n  #include <avr/pgmspace.h>\n#elif defined(ESP8266) || defined(ESP32)\n  #include <pgmspace.h>\n#endif\n\n// Many (but maybe not all) non-AVR board installs define macros\n// for compatibility with existing PROGMEM-reading AVR code.\n// Do our own checks and defines here for good measure...\n\n#ifndef pgm_read_byte\n #define pgm_read_byte(addr) (*(const unsigned char *)(addr))\n#endif\n#ifndef pgm_read_word\n #define pgm_read_word(addr) (*(const unsigned short *)(addr))\n#endif\n#ifndef pgm_read_dword\n #define pgm_read_dword(addr) (*(const unsigned long *)(addr))\n#endif\n\n// Pointers are a peculiar case...typically 16-bit on AVR boards,\n// 32 bits elsewhere.  Try to accommodate both...\n\n#if !defined(__INT_MAX__) || (__INT_MAX__ > 0xFFFF)\n #define pgm_read_pointer(addr) ((void *)pgm_read_dword(addr))\n#else\n #define pgm_read_pointer(addr) ((void *)pgm_read_word(addr))\n#endif\n\n#ifndef min\n#define min(a,b) (((a) < (b)) ? (a) : (b))\n#endif\n\n#ifndef _swap_int16_t\n#define _swap_int16_t(a, b) { int16_t t = a; a = b; b = t; }\n#endif\n\nAdafruit_GFX::Adafruit_GFX(int16_t w, int16_t h):\nWIDTH(w), HEIGHT(h)\n{\n    _width    = WIDTH;\n    _height   = HEIGHT;\n    rotation  = 0;\n    cursor_y  = cursor_x    = 0;\n    textsize  = 1;\n    textcolor = textbgcolor = 0xFFFF;\n    wrap      = true;\n    _cp437    = false;\n    gfxFont   = NULL;\n}\n\n// Bresenham's algorithm - thx wikpedia\nvoid Adafruit_GFX::writeLine(int16_t x0, int16_t y0, int16_t x1, int16_t y1,\n        uint16_t color) {\n    int16_t steep = abs(y1 - y0) > abs(x1 - x0);\n    if (steep) {\n        _swap_int16_t(x0, y0);\n        _swap_int16_t(x1, y1);\n    }\n\n    if (x0 > x1) {\n        _swap_int16_t(x0, x1);\n        _swap_int16_t(y0, y1);\n    }\n\n    int16_t dx, dy;\n    dx = x1 - x0;\n    dy = abs(y1 - y0);\n\n    int16_t err = dx / 2;\n    int16_t ystep;\n\n    if (y0 < y1) {\n        ystep = 1;\n    } else {\n        ystep = -1;\n    }\n\n    for (; x0<=x1; x0++) {\n        if (steep) {\n            writePixel(y0, x0, color);\n        } else {\n            writePixel(x0, y0, color);\n        }\n        err -= dy;\n        if (err < 0) {\n            y0 += ystep;\n            err += dx;\n        }\n    }\n}\n\nvoid Adafruit_GFX::startWrite(){\n    // Overwrite in subclasses if desired!\n}\n\nvoid Adafruit_GFX::writePixel(int16_t x, int16_t y, uint16_t color){\n    // Overwrite in subclasses if startWrite is defined!\n    drawPixel(x, y, color);\n}\n\n// (x,y) is topmost point; if unsure, calling function\n// should sort endpoints or call writeLine() instead\nvoid Adafruit_GFX::writeFastVLine(int16_t x, int16_t y,\n        int16_t h, uint16_t color) {\n    // Overwrite in subclasses if startWrite is defined!\n    // Can be just writeLine(x, y, x, y+h-1, color);\n    // or writeFillRect(x, y, 1, h, color);\n    drawFastVLine(x, y, h, color);\n}\n\n// (x,y) is leftmost point; if unsure, calling function\n// should sort endpoints or call writeLine() instead\nvoid Adafruit_GFX::writeFastHLine(int16_t x, int16_t y,\n        int16_t w, uint16_t color) {\n    // Overwrite in subclasses if startWrite is defined!\n    // Example: writeLine(x, y, x+w-1, y, color);\n    // or writeFillRect(x, y, w, 1, color);\n    drawFastHLine(x, y, w, color);\n}\n\nvoid Adafruit_GFX::writeFillRect(int16_t x, int16_t y, int16_t w, int16_t h,\n        uint16_t color) {\n    // Overwrite in subclasses if desired!\n    fillRect(x,y,w,h,color);\n}\n\nvoid Adafruit_GFX::endWrite(){\n    // Overwrite in subclasses if startWrite is defined!\n}\n\n// (x,y) is topmost point; if unsure, calling function\n// should sort endpoints or call drawLine() instead\nvoid Adafruit_GFX::drawFastVLine(int16_t x, int16_t y,\n        int16_t h, uint16_t color) {\n    // Update in subclasses if desired!\n    startWrite();\n    writeLine(x, y, x, y+h-1, color);\n    endWrite();\n}\n\n// (x,y) is leftmost point; if unsure, calling function\n// should sort endpoints or call drawLine() instead\nvoid Adafruit_GFX::drawFastHLine(int16_t x, int16_t y,\n        int16_t w, uint16_t color) {\n    // Update in subclasses if desired!\n    startWrite();\n    writeLine(x, y, x+w-1, y, color);\n    endWrite();\n}\n\nvoid Adafruit_GFX::fillRect(int16_t x, int16_t y, int16_t w, int16_t h,\n        uint16_t color) {\n    // Update in subclasses if desired!\n    startWrite();\n    for (int16_t i=x; i<x+w; i++) {\n        writeFastVLine(i, y, h, color);\n    }\n    endWrite();\n}\n\nvoid Adafruit_GFX::fillScreen(uint16_t color) {\n    // Update in subclasses if desired!\n    fillRect(0, 0, _width, _height, color);\n}\n\nvoid Adafruit_GFX::drawLine(int16_t x0, int16_t y0, int16_t x1, int16_t y1,\n        uint16_t color) {\n    // Update in subclasses if desired!\n    if(x0 == x1){\n        if(y0 > y1) _swap_int16_t(y0, y1);\n        drawFastVLine(x0, y0, y1 - y0 + 1, color);\n    } else if(y0 == y1){\n        if(x0 > x1) _swap_int16_t(x0, x1);\n        drawFastHLine(x0, y0, x1 - x0 + 1, color);\n    } else {\n        startWrite();\n        writeLine(x0, y0, x1, y1, color);\n        endWrite();\n    }\n}\n\n// Draw a circle outline\nvoid Adafruit_GFX::drawCircle(int16_t x0, int16_t y0, int16_t r,\n        uint16_t color) {\n    int16_t f = 1 - r;\n    int16_t ddF_x = 1;\n    int16_t ddF_y = -2 * r;\n    int16_t x = 0;\n    int16_t y = r;\n\n    startWrite();\n    writePixel(x0  , y0+r, color);\n    writePixel(x0  , y0-r, color);\n    writePixel(x0+r, y0  , color);\n    writePixel(x0-r, y0  , color);\n\n    while (x<y) {\n        if (f >= 0) {\n            y--;\n            ddF_y += 2;\n            f += ddF_y;\n        }\n        x++;\n        ddF_x += 2;\n        f += ddF_x;\n\n        writePixel(x0 + x, y0 + y, color);\n        writePixel(x0 - x, y0 + y, color);\n        writePixel(x0 + x, y0 - y, color);\n        writePixel(x0 - x, y0 - y, color);\n        writePixel(x0 + y, y0 + x, color);\n        writePixel(x0 - y, y0 + x, color);\n        writePixel(x0 + y, y0 - x, color);\n        writePixel(x0 - y, y0 - x, color);\n    }\n    endWrite();\n}\n\nvoid Adafruit_GFX::drawCircleHelper( int16_t x0, int16_t y0,\n        int16_t r, uint8_t cornername, uint16_t color) {\n    int16_t f     = 1 - r;\n    int16_t ddF_x = 1;\n    int16_t ddF_y = -2 * r;\n    int16_t x     = 0;\n    int16_t y     = r;\n\n    while (x<y) {\n        if (f >= 0) {\n            y--;\n            ddF_y += 2;\n            f     += ddF_y;\n        }\n        x++;\n        ddF_x += 2;\n        f     += ddF_x;\n        if (cornername & 0x4) {\n            writePixel(x0 + x, y0 + y, color);\n            writePixel(x0 + y, y0 + x, color);\n        }\n        if (cornername & 0x2) {\n            writePixel(x0 + x, y0 - y, color);\n            writePixel(x0 + y, y0 - x, color);\n        }\n        if (cornername & 0x8) {\n            writePixel(x0 - y, y0 + x, color);\n            writePixel(x0 - x, y0 + y, color);\n        }\n        if (cornername & 0x1) {\n            writePixel(x0 - y, y0 - x, color);\n            writePixel(x0 - x, y0 - y, color);\n        }\n    }\n}\n\nvoid Adafruit_GFX::fillCircle(int16_t x0, int16_t y0, int16_t r,\n        uint16_t color) {\n    startWrite();\n    writeFastVLine(x0, y0-r, 2*r+1, color);\n    fillCircleHelper(x0, y0, r, 3, 0, color);\n    endWrite();\n}\n\n// Used to do circles and roundrects\nvoid Adafruit_GFX::fillCircleHelper(int16_t x0, int16_t y0, int16_t r,\n        uint8_t cornername, int16_t delta, uint16_t color) {\n\n    int16_t f     = 1 - r;\n    int16_t ddF_x = 1;\n    int16_t ddF_y = -2 * r;\n    int16_t x     = 0;\n    int16_t y     = r;\n\n    while (x<y) {\n        if (f >= 0) {\n            y--;\n            ddF_y += 2;\n            f     += ddF_y;\n        }\n        x++;\n        ddF_x += 2;\n        f     += ddF_x;\n\n        if (cornername & 0x1) {\n            writeFastVLine(x0+x, y0-y, 2*y+1+delta, color);\n            writeFastVLine(x0+y, y0-x, 2*x+1+delta, color);\n        }\n        if (cornername & 0x2) {\n            writeFastVLine(x0-x, y0-y, 2*y+1+delta, color);\n            writeFastVLine(x0-y, y0-x, 2*x+1+delta, color);\n        }\n    }\n}\n\n// Draw a rectangle\nvoid Adafruit_GFX::drawRect(int16_t x, int16_t y, int16_t w, int16_t h,\n        uint16_t color) {\n    startWrite();\n    writeFastHLine(x, y, w, color);\n    writeFastHLine(x, y+h-1, w, color);\n    writeFastVLine(x, y, h, color);\n    writeFastVLine(x+w-1, y, h, color);\n    endWrite();\n}\n\n// Draw a rounded rectangle\nvoid Adafruit_GFX::drawRoundRect(int16_t x, int16_t y, int16_t w,\n        int16_t h, int16_t r, uint16_t color) {\n    // smarter version\n    startWrite();\n    writeFastHLine(x+r  , y    , w-2*r, color); // Top\n    writeFastHLine(x+r  , y+h-1, w-2*r, color); // Bottom\n    writeFastVLine(x    , y+r  , h-2*r, color); // Left\n    writeFastVLine(x+w-1, y+r  , h-2*r, color); // Right\n    // draw four corners\n    drawCircleHelper(x+r    , y+r    , r, 1, color);\n    drawCircleHelper(x+w-r-1, y+r    , r, 2, color);\n    drawCircleHelper(x+w-r-1, y+h-r-1, r, 4, color);\n    drawCircleHelper(x+r    , y+h-r-1, r, 8, color);\n    endWrite();\n}\n\n// Fill a rounded rectangle\nvoid Adafruit_GFX::fillRoundRect(int16_t x, int16_t y, int16_t w,\n        int16_t h, int16_t r, uint16_t color) {\n    // smarter version\n    startWrite();\n    writeFillRect(x+r, y, w-2*r, h, color);\n\n    // draw four corners\n    fillCircleHelper(x+w-r-1, y+r, r, 1, h-2*r-1, color);\n    fillCircleHelper(x+r    , y+r, r, 2, h-2*r-1, color);\n    endWrite();\n}\n\n// Draw a triangle\nvoid Adafruit_GFX::drawTriangle(int16_t x0, int16_t y0,\n        int16_t x1, int16_t y1, int16_t x2, int16_t y2, uint16_t color) {\n    drawLine(x0, y0, x1, y1, color);\n    drawLine(x1, y1, x2, y2, color);\n    drawLine(x2, y2, x0, y0, color);\n}\n\n// Fill a triangle\nvoid Adafruit_GFX::fillTriangle(int16_t x0, int16_t y0,\n        int16_t x1, int16_t y1, int16_t x2, int16_t y2, uint16_t color) {\n\n    int16_t a, b, y, last;\n\n    // Sort coordinates by Y order (y2 >= y1 >= y0)\n    if (y0 > y1) {\n        _swap_int16_t(y0, y1); _swap_int16_t(x0, x1);\n    }\n    if (y1 > y2) {\n        _swap_int16_t(y2, y1); _swap_int16_t(x2, x1);\n    }\n    if (y0 > y1) {\n        _swap_int16_t(y0, y1); _swap_int16_t(x0, x1);\n    }\n\n    startWrite();\n    if(y0 == y2) { // Handle awkward all-on-same-line case as its own thing\n        a = b = x0;\n        if(x1 < a)      a = x1;\n        else if(x1 > b) b = x1;\n        if(x2 < a)      a = x2;\n        else if(x2 > b) b = x2;\n        writeFastHLine(a, y0, b-a+1, color);\n        endWrite();\n        return;\n    }\n\n    int16_t\n    dx01 = x1 - x0,\n    dy01 = y1 - y0,\n    dx02 = x2 - x0,\n    dy02 = y2 - y0,\n    dx12 = x2 - x1,\n    dy12 = y2 - y1;\n    int32_t\n    sa   = 0,\n    sb   = 0;\n\n    // For upper part of triangle, find scanline crossings for segments\n    // 0-1 and 0-2.  If y1=y2 (flat-bottomed triangle), the scanline y1\n    // is included here (and second loop will be skipped, avoiding a /0\n    // error there), otherwise scanline y1 is skipped here and handled\n    // in the second loop...which also avoids a /0 error here if y0=y1\n    // (flat-topped triangle).\n    if(y1 == y2) last = y1;   // Include y1 scanline\n    else         last = y1-1; // Skip it\n\n    for(y=y0; y<=last; y++) {\n        a   = x0 + sa / dy01;\n        b   = x0 + sb / dy02;\n        sa += dx01;\n        sb += dx02;\n        /* longhand:\n        a = x0 + (x1 - x0) * (y - y0) / (y1 - y0);\n        b = x0 + (x2 - x0) * (y - y0) / (y2 - y0);\n        */\n        if(a > b) _swap_int16_t(a,b);\n        writeFastHLine(a, y, b-a+1, color);\n    }\n\n    // For lower part of triangle, find scanline crossings for segments\n    // 0-2 and 1-2.  This loop is skipped if y1=y2.\n    sa = dx12 * (y - y1);\n    sb = dx02 * (y - y0);\n    for(; y<=y2; y++) {\n        a   = x1 + sa / dy12;\n        b   = x0 + sb / dy02;\n        sa += dx12;\n        sb += dx02;\n        /* longhand:\n        a = x1 + (x2 - x1) * (y - y1) / (y2 - y1);\n        b = x0 + (x2 - x0) * (y - y0) / (y2 - y0);\n        */\n        if(a > b) _swap_int16_t(a,b);\n        writeFastHLine(a, y, b-a+1, color);\n    }\n    endWrite();\n}\n\n// BITMAP / XBITMAP / GRAYSCALE / RGB BITMAP FUNCTIONS ---------------------\n\n// Draw a PROGMEM-resident 1-bit image at the specified (x,y) position,\n// using the specified foreground color (unset bits are transparent).\nvoid Adafruit_GFX::drawBitmap(int16_t x, int16_t y,\n  const uint8_t bitmap[], int16_t w, int16_t h, uint16_t color) {\n\n    int16_t byteWidth = (w + 7) / 8; // Bitmap scanline pad = whole byte\n    uint8_t byte = 0;\n\n    startWrite();\n    for(int16_t j=0; j<h; j++, y++) {\n        for(int16_t i=0; i<w; i++) {\n            if(i & 7) byte <<= 1;\n            else      byte   = pgm_read_byte(&bitmap[j * byteWidth + i / 8]);\n            if(byte & 0x80) writePixel(x+i, y, color);\n        }\n    }\n    endWrite();\n}\n\n// Draw a PROGMEM-resident 1-bit image at the specified (x,y) position,\n// using the specified foreground (for set bits) and background (unset\n// bits) colors.\nvoid Adafruit_GFX::drawBitmap(int16_t x, int16_t y,\n  const uint8_t bitmap[], int16_t w, int16_t h,\n  uint16_t color, uint16_t bg) {\n\n    int16_t byteWidth = (w + 7) / 8; // Bitmap scanline pad = whole byte\n    uint8_t byte = 0;\n\n    startWrite();\n    for(int16_t j=0; j<h; j++, y++) {\n        for(int16_t i=0; i<w; i++ ) {\n            if(i & 7) byte <<= 1;\n            else      byte   = pgm_read_byte(&bitmap[j * byteWidth + i / 8]);\n            writePixel(x+i, y, (byte & 0x80) ? color : bg);\n        }\n    }\n    endWrite();\n}\n\n// Draw a RAM-resident 1-bit image at the specified (x,y) position,\n// using the specified foreground color (unset bits are transparent).\nvoid Adafruit_GFX::drawBitmap(int16_t x, int16_t y,\n  uint8_t *bitmap, int16_t w, int16_t h, uint16_t color) {\n\n    int16_t byteWidth = (w + 7) / 8; // Bitmap scanline pad = whole byte\n    uint8_t byte = 0;\n\n    startWrite();\n    for(int16_t j=0; j<h; j++, y++) {\n        for(int16_t i=0; i<w; i++ ) {\n            if(i & 7) byte <<= 1;\n            else      byte   = bitmap[j * byteWidth + i / 8];\n            if(byte & 0x80) writePixel(x+i, y, color);\n        }\n    }\n    endWrite();\n}\n\n// Draw a RAM-resident 1-bit image at the specified (x,y) position,\n// using the specified foreground (for set bits) and background (unset\n// bits) colors.\nvoid Adafruit_GFX::drawBitmap(int16_t x, int16_t y,\n  uint8_t *bitmap, int16_t w, int16_t h, uint16_t color, uint16_t bg) {\n\n    int16_t byteWidth = (w + 7) / 8; // Bitmap scanline pad = whole byte\n    uint8_t byte = 0;\n\n    startWrite();\n    for(int16_t j=0; j<h; j++, y++) {\n        for(int16_t i=0; i<w; i++ ) {\n            if(i & 7) byte <<= 1;\n            else      byte   = bitmap[j * byteWidth + i / 8];\n            writePixel(x+i, y, (byte & 0x80) ? color : bg);\n        }\n    }\n    endWrite();\n}\n\n// Draw PROGMEM-resident XBitMap Files (*.xbm), exported from GIMP,\n// Usage: Export from GIMP to *.xbm, rename *.xbm to *.c and open in editor.\n// C Array can be directly used with this function.\n// There is no RAM-resident version of this function; if generating bitmaps\n// in RAM, use the format defined by drawBitmap() and call that instead.\nvoid Adafruit_GFX::drawXBitmap(int16_t x, int16_t y,\n  const uint8_t bitmap[], int16_t w, int16_t h, uint16_t color) {\n\n    int16_t byteWidth = (w + 7) / 8; // Bitmap scanline pad = whole byte\n    uint8_t byte = 0;\n\n    startWrite();\n    for(int16_t j=0; j<h; j++, y++) {\n        for(int16_t i=0; i<w; i++ ) {\n            if(i & 7) byte >>= 1;\n            else      byte   = pgm_read_byte(&bitmap[j * byteWidth + i / 8]);\n            // Nearly identical to drawBitmap(), only the bit order\n            // is reversed here (left-to-right = LSB to MSB):\n            if(byte & 0x01) writePixel(x+i, y, color);\n        }\n    }\n    endWrite();\n}\n\n// Draw a PROGMEM-resident 8-bit image (grayscale) at the specified (x,y)\n// pos.  Specifically for 8-bit display devices such as IS31FL3731;\n// no color reduction/expansion is performed.\nvoid Adafruit_GFX::drawGrayscaleBitmap(int16_t x, int16_t y,\n  const uint8_t bitmap[], int16_t w, int16_t h) {\n    startWrite();\n    for(int16_t j=0; j<h; j++, y++) {\n        for(int16_t i=0; i<w; i++ ) {\n            writePixel(x+i, y, (uint8_t)pgm_read_byte(&bitmap[j * w + i]));\n        }\n    }\n    endWrite();\n}\n\n// Draw a RAM-resident 8-bit image (grayscale) at the specified (x,y)\n// pos.  Specifically for 8-bit display devices such as IS31FL3731;\n// no color reduction/expansion is performed.\nvoid Adafruit_GFX::drawGrayscaleBitmap(int16_t x, int16_t y,\n  uint8_t *bitmap, int16_t w, int16_t h) {\n    startWrite();\n    for(int16_t j=0; j<h; j++, y++) {\n        for(int16_t i=0; i<w; i++ ) {\n            writePixel(x+i, y, bitmap[j * w + i]);\n        }\n    }\n    endWrite();\n}\n\n// Draw a PROGMEM-resident 8-bit image (grayscale) with a 1-bit mask\n// (set bits = opaque, unset bits = clear) at the specified (x,y) position.\n// BOTH buffers (grayscale and mask) must be PROGMEM-resident.\n// Specifically for 8-bit display devices such as IS31FL3731;\n// no color reduction/expansion is performed.\nvoid Adafruit_GFX::drawGrayscaleBitmap(int16_t x, int16_t y,\n  const uint8_t bitmap[], const uint8_t mask[],\n  int16_t w, int16_t h) {\n    int16_t bw   = (w + 7) / 8; // Bitmask scanline pad = whole byte\n    uint8_t byte = 0;\n    startWrite();\n    for(int16_t j=0; j<h; j++, y++) {\n        for(int16_t i=0; i<w; i++ ) {\n            if(i & 7) byte <<= 1;\n            else      byte   = pgm_read_byte(&mask[j * bw + i / 8]);\n            if(byte & 0x80) {\n                writePixel(x+i, y, (uint8_t)pgm_read_byte(&bitmap[j * w + i]));\n            }\n        }\n    }\n    endWrite();\n}\n\n// Draw a RAM-resident 8-bit image (grayscale) with a 1-bit mask\n// (set bits = opaque, unset bits = clear) at the specified (x,y) pos.\n// BOTH buffers (grayscale and mask) must be RAM-resident, no mix-and-\n// match.  Specifically for 8-bit display devices such as IS31FL3731;\n// no color reduction/expansion is performed.\nvoid Adafruit_GFX::drawGrayscaleBitmap(int16_t x, int16_t y,\n  uint8_t *bitmap, uint8_t *mask, int16_t w, int16_t h) {\n    int16_t bw   = (w + 7) / 8; // Bitmask scanline pad = whole byte\n    uint8_t byte = 0;\n    startWrite();\n    for(int16_t j=0; j<h; j++, y++) {\n        for(int16_t i=0; i<w; i++ ) {\n            if(i & 7) byte <<= 1;\n            else      byte   = mask[j * bw + i / 8];\n            if(byte & 0x80) {\n                writePixel(x+i, y, bitmap[j * w + i]);\n            }\n        }\n    }\n    endWrite();\n}\n\n// Draw a PROGMEM-resident 16-bit image (RGB 5/6/5) at the specified (x,y)\n// position.  For 16-bit display devices; no color reduction performed.\nvoid Adafruit_GFX::drawRGBBitmap(int16_t x, int16_t y,\n  const uint16_t bitmap[], int16_t w, int16_t h) {\n    startWrite();\n    for(int16_t j=0; j<h; j++, y++) {\n        for(int16_t i=0; i<w; i++ ) {\n            writePixel(x+i, y, pgm_read_word(&bitmap[j * w + i]));\n        }\n    }\n    endWrite();\n}\n\n// Draw a RAM-resident 16-bit image (RGB 5/6/5) at the specified (x,y)\n// position.  For 16-bit display devices; no color reduction performed.\nvoid Adafruit_GFX::drawRGBBitmap(int16_t x, int16_t y,\n  uint16_t *bitmap, int16_t w, int16_t h) {\n    startWrite();\n    for(int16_t j=0; j<h; j++, y++) {\n        for(int16_t i=0; i<w; i++ ) {\n            writePixel(x+i, y, bitmap[j * w + i]);\n        }\n    }\n    endWrite();\n}\n\n// Draw a PROGMEM-resident 16-bit image (RGB 5/6/5) with a 1-bit mask\n// (set bits = opaque, unset bits = clear) at the specified (x,y) position.\n// BOTH buffers (color and mask) must be PROGMEM-resident.\n// For 16-bit display devices; no color reduction performed.\nvoid Adafruit_GFX::drawRGBBitmap(int16_t x, int16_t y,\n  const uint16_t bitmap[], const uint8_t mask[],\n  int16_t w, int16_t h) {\n    int16_t bw   = (w + 7) / 8; // Bitmask scanline pad = whole byte\n    uint8_t byte = 0;\n    startWrite();\n    for(int16_t j=0; j<h; j++, y++) {\n        for(int16_t i=0; i<w; i++ ) {\n            if(i & 7) byte <<= 1;\n            else      byte   = pgm_read_byte(&mask[j * bw + i / 8]);\n            if(byte & 0x80) {\n                writePixel(x+i, y, pgm_read_word(&bitmap[j * w + i]));\n            }\n        }\n    }\n    endWrite();\n}\n\n// Draw a RAM-resident 16-bit image (RGB 5/6/5) with a 1-bit mask\n// (set bits = opaque, unset bits = clear) at the specified (x,y) pos.\n// BOTH buffers (color and mask) must be RAM-resident, no mix-and-match.\n// For 16-bit display devices; no color reduction performed.\nvoid Adafruit_GFX::drawRGBBitmap(int16_t x, int16_t y,\n  uint16_t *bitmap, uint8_t *mask, int16_t w, int16_t h) {\n    int16_t bw   = (w + 7) / 8; // Bitmask scanline pad = whole byte\n    uint8_t byte = 0;\n    startWrite();\n    for(int16_t j=0; j<h; j++, y++) {\n        for(int16_t i=0; i<w; i++ ) {\n            if(i & 7) byte <<= 1;\n            else      byte   = mask[j * bw + i / 8];\n            if(byte & 0x80) {\n                writePixel(x+i, y, bitmap[j * w + i]);\n            }\n        }\n    }\n    endWrite();\n}\n\n// TEXT- AND CHARACTER-HANDLING FUNCTIONS ----------------------------------\n\n// Draw a character\nvoid Adafruit_GFX::drawChar(int16_t x, int16_t y, unsigned char c,\n  uint16_t color, uint16_t bg, uint8_t size) {\n\n    if(!gfxFont) { // 'Classic' built-in font\n\n        if((x >= _width)            || // Clip right\n           (y >= _height)           || // Clip bottom\n           ((x + 6 * size - 1) < 0) || // Clip left\n           ((y + 8 * size - 1) < 0))   // Clip top\n            return;\n\n        if(!_cp437 && (c >= 176)) c++; // Handle 'classic' charset behavior\n\n        startWrite();\n        for(int8_t i=0; i<5; i++ ) { // Char bitmap = 5 columns\n            uint8_t line = pgm_read_byte(&font[c * 5 + i]);\n            for(int8_t j=0; j<8; j++, line >>= 1) {\n                if(line & 1) {\n                    if(size == 1)\n                        writePixel(x+i, y+j, color);\n                    else\n                        writeFillRect(x+i*size, y+j*size, size, size, color);\n                } else if(bg != color) {\n                    if(size == 1)\n                        writePixel(x+i, y+j, bg);\n                    else\n                        writeFillRect(x+i*size, y+j*size, size, size, bg);\n                }\n            }\n        }\n        if(bg != color) { // If opaque, draw vertical line for last column\n            if(size == 1) writeFastVLine(x+5, y, 8, bg);\n            else          writeFillRect(x+5*size, y, size, 8*size, bg);\n        }\n        endWrite();\n\n    } else { // Custom font\n\n        // Character is assumed previously filtered by write() to eliminate\n        // newlines, returns, non-printable characters, etc.  Calling\n        // drawChar() directly with 'bad' characters of font may cause mayhem!\n\n        c -= (uint8_t)pgm_read_byte(&gfxFont->first);\n        GFXglyph *glyph  = &(((GFXglyph *)pgm_read_pointer(&gfxFont->glyph))[c]);\n        uint8_t  *bitmap = (uint8_t *)pgm_read_pointer(&gfxFont->bitmap);\n\n        uint16_t bo = pgm_read_word(&glyph->bitmapOffset);\n        uint8_t  w  = pgm_read_byte(&glyph->width),\n                 h  = pgm_read_byte(&glyph->height);\n        int8_t   xo = pgm_read_byte(&glyph->xOffset),\n                 yo = pgm_read_byte(&glyph->yOffset);\n        uint8_t  xx, yy, bits = 0, bit = 0;\n        int16_t  xo16 = 0, yo16 = 0;\n\n        if(size > 1) {\n            xo16 = xo;\n            yo16 = yo;\n        }\n\n        // Todo: Add character clipping here\n\n        // NOTE: THERE IS NO 'BACKGROUND' COLOR OPTION ON CUSTOM FONTS.\n        // THIS IS ON PURPOSE AND BY DESIGN.  The background color feature\n        // has typically been used with the 'classic' font to overwrite old\n        // screen contents with new data.  This ONLY works because the\n        // characters are a uniform size; it's not a sensible thing to do with\n        // proportionally-spaced fonts with glyphs of varying sizes (and that\n        // may overlap).  To replace previously-drawn text when using a custom\n        // font, use the getTextBounds() function to determine the smallest\n        // rectangle encompassing a string, erase the area with fillRect(),\n        // then draw new text.  This WILL infortunately 'blink' the text, but\n        // is unavoidable.  Drawing 'background' pixels will NOT fix this,\n        // only creates a new set of problems.  Have an idea to work around\n        // this (a canvas object type for MCUs that can afford the RAM and\n        // displays supporting setAddrWindow() and pushColors()), but haven't\n        // implemented this yet.\n\n        startWrite();\n        for(yy=0; yy<h; yy++) {\n            for(xx=0; xx<w; xx++) {\n                if(!(bit++ & 7)) {\n                    bits = pgm_read_byte(&bitmap[bo++]);\n                }\n                if(bits & 0x80) {\n                    if(size == 1) {\n                        writePixel(x+xo+xx, y+yo+yy, color);\n                    } else {\n                        writeFillRect(x+(xo16+xx)*size, y+(yo16+yy)*size,\n                          size, size, color);\n                    }\n                }\n                bits <<= 1;\n            }\n        }\n        endWrite();\n\n    } // End classic vs custom font\n}\n\n#if ARDUINO >= 100\nsize_t Adafruit_GFX::write(uint8_t c) {\n#else\nvoid Adafruit_GFX::write(uint8_t c) {\n#endif\n    if(!gfxFont) { // 'Classic' built-in font\n\n        if(c == '\\n') {                        // Newline?\n            cursor_x  = 0;                     // Reset x to zero,\n            cursor_y += textsize * 8;          // advance y one line\n        } else if(c != '\\r') {                 // Ignore carriage returns\n            if(wrap && ((cursor_x + textsize * 6) > _width)) { // Off right?\n                cursor_x  = 0;                 // Reset x to zero,\n                cursor_y += textsize * 8;      // advance y one line\n            }\n            drawChar(cursor_x, cursor_y, c, textcolor, textbgcolor, textsize);\n            cursor_x += textsize * 6;          // Advance x one char\n        }\n\n    } else { // Custom font\n\n        if(c == '\\n') {\n            cursor_x  = 0;\n            cursor_y += (int16_t)textsize *\n                        (uint8_t)pgm_read_byte(&gfxFont->yAdvance);\n        } else if(c != '\\r') {\n            uint8_t first = pgm_read_byte(&gfxFont->first);\n            if((c >= first) && (c <= (uint8_t)pgm_read_byte(&gfxFont->last))) {\n                GFXglyph *glyph = &(((GFXglyph *)pgm_read_pointer(\n                  &gfxFont->glyph))[c - first]);\n                uint8_t   w     = pgm_read_byte(&glyph->width),\n                          h     = pgm_read_byte(&glyph->height);\n                if((w > 0) && (h > 0)) { // Is there an associated bitmap?\n                    int16_t xo = (int8_t)pgm_read_byte(&glyph->xOffset); // sic\n                    if(wrap && ((cursor_x + textsize * (xo + w)) > _width)) {\n                        cursor_x  = 0;\n                        cursor_y += (int16_t)textsize *\n                          (uint8_t)pgm_read_byte(&gfxFont->yAdvance);\n                    }\n                    drawChar(cursor_x, cursor_y, c, textcolor, textbgcolor, textsize);\n                }\n                cursor_x += (uint8_t)pgm_read_byte(&glyph->xAdvance) * (int16_t)textsize;\n            }\n        }\n\n    }\n#if ARDUINO >= 100\n    return 1;\n#endif\n}\n\nvoid Adafruit_GFX::setCursor(int16_t x, int16_t y) {\n    cursor_x = x;\n    cursor_y = y;\n}\n\nint16_t Adafruit_GFX::getCursorX(void) const {\n    return cursor_x;\n}\n\nint16_t Adafruit_GFX::getCursorY(void) const {\n    return cursor_y;\n}\n\nvoid Adafruit_GFX::setTextSize(uint8_t s) {\n    textsize = (s > 0) ? s : 1;\n}\n\nvoid Adafruit_GFX::setTextColor(uint16_t c) {\n    // For 'transparent' background, we'll set the bg\n    // to the same as fg instead of using a flag\n    textcolor = textbgcolor = c;\n}\n\nvoid Adafruit_GFX::setTextColor(uint16_t c, uint16_t b) {\n    textcolor   = c;\n    textbgcolor = b;\n}\n\nvoid Adafruit_GFX::setTextWrap(boolean w) {\n    wrap = w;\n}\n\nuint8_t Adafruit_GFX::getRotation(void) const {\n    return rotation;\n}\n\nvoid Adafruit_GFX::setRotation(uint8_t x) {\n    rotation = (x & 3);\n    switch(rotation) {\n        case 0:\n        case 2:\n            _width  = WIDTH;\n            _height = HEIGHT;\n            break;\n        case 1:\n        case 3:\n            _width  = HEIGHT;\n            _height = WIDTH;\n            break;\n    }\n}\n\n// Enable (or disable) Code Page 437-compatible charset.\n// There was an error in glcdfont.c for the longest time -- one character\n// (#176, the 'light shade' block) was missing -- this threw off the index\n// of every character that followed it.  But a TON of code has been written\n// with the erroneous character indices.  By default, the library uses the\n// original 'wrong' behavior and old sketches will still work.  Pass 'true'\n// to this function to use correct CP437 character values in your code.\nvoid Adafruit_GFX::cp437(boolean x) {\n    _cp437 = x;\n}\n\nvoid Adafruit_GFX::setFont(const GFXfont *f) {\n    if(f) {            // Font struct pointer passed in?\n        if(!gfxFont) { // And no current font struct?\n            // Switching from classic to new font behavior.\n            // Move cursor pos down 6 pixels so it's on baseline.\n            cursor_y += 6;\n        }\n    } else if(gfxFont) { // NULL passed.  Current font struct defined?\n        // Switching from new to classic font behavior.\n        // Move cursor pos up 6 pixels so it's at top-left of char.\n        cursor_y -= 6;\n    }\n    gfxFont = (GFXfont *)f;\n}\n\n// Broke this out as it's used by both the PROGMEM- and RAM-resident\n// getTextBounds() functions.\nvoid Adafruit_GFX::charBounds(char c, int16_t *x, int16_t *y,\n  int16_t *minx, int16_t *miny, int16_t *maxx, int16_t *maxy) {\n\n    if(gfxFont) {\n\n        if(c == '\\n') { // Newline?\n            *x  = 0;    // Reset x to zero, advance y by one line\n            *y += textsize * (uint8_t)pgm_read_byte(&gfxFont->yAdvance);\n        } else if(c != '\\r') { // Not a carriage return; is normal char\n            uint8_t first = pgm_read_byte(&gfxFont->first),\n                    last  = pgm_read_byte(&gfxFont->last);\n            if((c >= first) && (c <= last)) { // Char present in this font?\n                GFXglyph *glyph = &(((GFXglyph *)pgm_read_pointer(\n                  &gfxFont->glyph))[c - first]);\n                uint8_t gw = pgm_read_byte(&glyph->width),\n                        gh = pgm_read_byte(&glyph->height),\n                        xa = pgm_read_byte(&glyph->xAdvance);\n                int8_t  xo = pgm_read_byte(&glyph->xOffset),\n                        yo = pgm_read_byte(&glyph->yOffset);\n                if(wrap && ((*x+(((int16_t)xo+gw)*textsize)) > _width)) {\n                    *x  = 0; // Reset x to zero, advance y by one line\n                    *y += textsize * (uint8_t)pgm_read_byte(&gfxFont->yAdvance);\n                }\n                int16_t ts = (int16_t)textsize,\n                        x1 = *x + xo * ts,\n                        y1 = *y + yo * ts,\n                        x2 = x1 + gw * ts - 1,\n                        y2 = y1 + gh * ts - 1;\n                if(x1 < *minx) *minx = x1;\n                if(y1 < *miny) *miny = y1;\n                if(x2 > *maxx) *maxx = x2;\n                if(y2 > *maxy) *maxy = y2;\n                *x += xa * ts;\n            }\n        }\n\n    } else { // Default font\n\n        if(c == '\\n') {                     // Newline?\n            *x  = 0;                        // Reset x to zero,\n            *y += textsize * 8;             // advance y one line\n            // min/max x/y unchaged -- that waits for next 'normal' character\n        } else if(c != '\\r') {  // Normal char; ignore carriage returns\n            if(wrap && ((*x + textsize * 6) > _width)) { // Off right?\n                *x  = 0;                    // Reset x to zero,\n                *y += textsize * 8;         // advance y one line\n            }\n            int x2 = *x + textsize * 6 - 1, // Lower-right pixel of char\n                y2 = *y + textsize * 8 - 1;\n            if(x2 > *maxx) *maxx = x2;      // Track max x, y\n            if(y2 > *maxy) *maxy = y2;\n            if(*x < *minx) *minx = *x;      // Track min x, y\n            if(*y < *miny) *miny = *y;\n            *x += textsize * 6;             // Advance x one char\n        }\n    }\n}\n\n// Pass string and a cursor position, returns UL corner and W,H.\nvoid Adafruit_GFX::getTextBounds(char *str, int16_t x, int16_t y,\n        int16_t *x1, int16_t *y1, uint16_t *w, uint16_t *h) {\n    uint8_t c; // Current character\n\n    *x1 = x;\n    *y1 = y;\n    *w  = *h = 0;\n\n    int16_t minx = _width, miny = _height, maxx = -1, maxy = -1;\n\n    while((c = *str++))\n        charBounds(c, &x, &y, &minx, &miny, &maxx, &maxy);\n\n    if(maxx >= minx) {\n        *x1 = minx;\n        *w  = maxx - minx + 1;\n    }\n    if(maxy >= miny) {\n        *y1 = miny;\n        *h  = maxy - miny + 1;\n    }\n}\n\n// Same as above, but for PROGMEM strings\nvoid Adafruit_GFX::getTextBounds(const __FlashStringHelper *str,\n        int16_t x, int16_t y, int16_t *x1, int16_t *y1, uint16_t *w, uint16_t *h) {\n    uint8_t *s = (uint8_t *)str, c;\n\n    *x1 = x;\n    *y1 = y;\n    *w  = *h = 0;\n\n    int16_t minx = _width, miny = _height, maxx = -1, maxy = -1;\n\n    while((c = pgm_read_byte(s++)))\n        charBounds(c, &x, &y, &minx, &miny, &maxx, &maxy);\n\n    if(maxx >= minx) {\n        *x1 = minx;\n        *w  = maxx - minx + 1;\n    }\n    if(maxy >= miny) {\n        *y1 = miny;\n        *h  = maxy - miny + 1;\n    }\n}\n\n// Return the size of the display (per current rotation)\nint16_t Adafruit_GFX::width(void) const {\n    return _width;\n}\n\nint16_t Adafruit_GFX::height(void) const {\n    return _height;\n}\n\nvoid Adafruit_GFX::invertDisplay(boolean i) {\n    // Do nothing, must be subclassed if supported by hardware\n}\n\n/***************************************************************************/\n// code for the GFX button UI element\n\nAdafruit_GFX_Button::Adafruit_GFX_Button(void) {\n  _gfx = 0;\n}\n\n// Classic initButton() function: pass center & size\nvoid Adafruit_GFX_Button::initButton(\n Adafruit_GFX *gfx, int16_t x, int16_t y, uint16_t w, uint16_t h,\n uint16_t outline, uint16_t fill, uint16_t textcolor,\n char *label, uint8_t textsize)\n{\n  // Tweak arguments and pass to the newer initButtonUL() function...\n  initButtonUL(gfx, x - (w / 2), y - (h / 2), w, h, outline, fill,\n    textcolor, label, textsize);\n}\n\n// Newer function instead accepts upper-left corner & size\nvoid Adafruit_GFX_Button::initButtonUL(\n Adafruit_GFX *gfx, int16_t x1, int16_t y1, uint16_t w, uint16_t h,\n uint16_t outline, uint16_t fill, uint16_t textcolor,\n char *label, uint8_t textsize)\n{\n  _x1           = x1;\n  _y1           = y1;\n  _w            = w;\n  _h            = h;\n  _outlinecolor = outline;\n  _fillcolor    = fill;\n  _textcolor    = textcolor;\n  _textsize     = textsize;\n  _gfx          = gfx;\n  strncpy(_label, label, 9);\n}\n\nvoid Adafruit_GFX_Button::drawButton(boolean inverted) {\n  uint16_t fill, outline, text;\n\n  if(!inverted) {\n    fill    = _fillcolor;\n    outline = _outlinecolor;\n    text    = _textcolor;\n  } else {\n    fill    = _textcolor;\n    outline = _outlinecolor;\n    text    = _fillcolor;\n  }\n\n  uint8_t r = min(_w, _h) / 4; // Corner radius\n  _gfx->fillRoundRect(_x1, _y1, _w, _h, r, fill);\n  _gfx->drawRoundRect(_x1, _y1, _w, _h, r, outline);\n\n  _gfx->setCursor(_x1 + (_w/2) - (strlen(_label) * 3 * _textsize),\n    _y1 + (_h/2) - (4 * _textsize));\n  _gfx->setTextColor(text);\n  _gfx->setTextSize(_textsize);\n  _gfx->print(_label);\n}\n\nboolean Adafruit_GFX_Button::contains(int16_t x, int16_t y) {\n  return ((x >= _x1) && (x < (_x1 + _w)) &&\n          (y >= _y1) && (y < (_y1 + _h)));\n}\n\nvoid Adafruit_GFX_Button::press(boolean p) {\n  laststate = currstate;\n  currstate = p;\n}\n\nboolean Adafruit_GFX_Button::isPressed() { return currstate; }\nboolean Adafruit_GFX_Button::justPressed() { return (currstate && !laststate); }\nboolean Adafruit_GFX_Button::justReleased() { return (!currstate && laststate); }\n\n// -------------------------------------------------------------------------\n\n// GFXcanvas1, GFXcanvas8 and GFXcanvas16 (currently a WIP, don't get too\n// comfy with the implementation) provide 1-, 8- and 16-bit offscreen\n// canvases, the address of which can be passed to drawBitmap() or\n// pushColors() (the latter appears only in a couple of GFX-subclassed TFT\n// libraries at this time).  This is here mostly to help with the recently-\n// added proportionally-spaced fonts; adds a way to refresh a section of the\n// screen without a massive flickering clear-and-redraw...but maybe you'll\n// find other uses too.  VERY RAM-intensive, since the buffer is in MCU\n// memory and not the display driver...GXFcanvas1 might be minimally useful\n// on an Uno-class board, but this and the others are much more likely to\n// require at least a Mega or various recent ARM-type boards (recommended,\n// as the text+bitmap draw can be pokey).  GFXcanvas1 requires 1 bit per\n// pixel (rounded up to nearest byte per scanline), GFXcanvas8 is 1 byte\n// per pixel (no scanline pad), and GFXcanvas16 uses 2 bytes per pixel (no\n// scanline pad).\n// NOT EXTENSIVELY TESTED YET.  MAY CONTAIN WORST BUGS KNOWN TO HUMANKIND.\n\nGFXcanvas1::GFXcanvas1(uint16_t w, uint16_t h) : Adafruit_GFX(w, h) {\n    uint16_t bytes = ((w + 7) / 8) * h;\n    if((buffer = (uint8_t *)malloc(bytes))) {\n        memset(buffer, 0, bytes);\n    }\n}\n\nGFXcanvas1::~GFXcanvas1(void) {\n    if(buffer) free(buffer);\n}\n\nuint8_t* GFXcanvas1::getBuffer(void) {\n    return buffer;\n}\n\nvoid GFXcanvas1::drawPixel(int16_t x, int16_t y, uint16_t color) {\n#ifdef __AVR__\n    // Bitmask tables of 0x80>>X and ~(0x80>>X), because X>>Y is slow on AVR\n    static const uint8_t PROGMEM\n        GFXsetBit[] = { 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01 },\n        GFXclrBit[] = { 0x7F, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD, 0xFE };\n#endif\n\n    if(buffer) {\n        if((x < 0) || (y < 0) || (x >= _width) || (y >= _height)) return;\n\n        int16_t t;\n        switch(rotation) {\n            case 1:\n                t = x;\n                x = WIDTH  - 1 - y;\n                y = t;\n                break;\n            case 2:\n                x = WIDTH  - 1 - x;\n                y = HEIGHT - 1 - y;\n                break;\n            case 3:\n                t = x;\n                x = y;\n                y = HEIGHT - 1 - t;\n                break;\n        }\n\n        uint8_t   *ptr  = &buffer[(x / 8) + y * ((WIDTH + 7) / 8)];\n#ifdef __AVR__\n        if(color) *ptr |= pgm_read_byte(&GFXsetBit[x & 7]);\n        else      *ptr &= pgm_read_byte(&GFXclrBit[x & 7]);\n#else\n        if(color) *ptr |=   0x80 >> (x & 7);\n        else      *ptr &= ~(0x80 >> (x & 7));\n#endif\n    }\n}\n\nvoid GFXcanvas1::fillScreen(uint16_t color) {\n    if(buffer) {\n        uint16_t bytes = ((WIDTH + 7) / 8) * HEIGHT;\n        memset(buffer, color ? 0xFF : 0x00, bytes);\n    }\n}\n\nGFXcanvas8::GFXcanvas8(uint16_t w, uint16_t h) : Adafruit_GFX(w, h) {\n    uint32_t bytes = w * h;\n    if((buffer = (uint8_t *)malloc(bytes))) {\n        memset(buffer, 0, bytes);\n    }\n}\n\nGFXcanvas8::~GFXcanvas8(void) {\n    if(buffer) free(buffer);\n}\n\nuint8_t* GFXcanvas8::getBuffer(void) {\n    return buffer;\n}\n\nvoid GFXcanvas8::drawPixel(int16_t x, int16_t y, uint16_t color) {\n    if(buffer) {\n        if((x < 0) || (y < 0) || (x >= _width) || (y >= _height)) return;\n\n        int16_t t;\n        switch(rotation) {\n            case 1:\n                t = x;\n                x = WIDTH  - 1 - y;\n                y = t;\n                break;\n            case 2:\n                x = WIDTH  - 1 - x;\n                y = HEIGHT - 1 - y;\n                break;\n            case 3:\n                t = x;\n                x = y;\n                y = HEIGHT - 1 - t;\n                break;\n        }\n\n        buffer[x + y * WIDTH] = color;\n    }\n}\n\nvoid GFXcanvas8::fillScreen(uint16_t color) {\n    if(buffer) {\n        memset(buffer, color, WIDTH * HEIGHT);\n    }\n}\n\nvoid GFXcanvas8::writeFastHLine(int16_t x, int16_t y,\n  int16_t w, uint16_t color) {\n\n    if((x >= _width) || (y < 0) || (y >= _height)) return;\n    int16_t x2 = x + w - 1;\n    if(x2 < 0) return;\n\n    // Clip left/right\n    if(x < 0) {\n        x = 0;\n        w = x2 + 1;\n    }\n    if(x2 >= _width) w = _width - x;\n\n    int16_t t;\n    switch(rotation) {\n        case 1:\n            t = x;\n            x = WIDTH  - 1 - y;\n            y = t;\n            break;\n        case 2:\n            x = WIDTH  - 1 - x;\n            y = HEIGHT - 1 - y;\n            break;\n        case 3:\n            t = x;\n            x = y;\n            y = HEIGHT - 1 - t;\n            break;\n    }\n\n    memset(buffer + y * WIDTH + x, color, w);\n}\n\nGFXcanvas16::GFXcanvas16(uint16_t w, uint16_t h) : Adafruit_GFX(w, h) {\n    uint32_t bytes = w * h * 2;\n    if((buffer = (uint16_t *)malloc(bytes))) {\n        memset(buffer, 0, bytes);\n    }\n}\n\nGFXcanvas16::~GFXcanvas16(void) {\n    if(buffer) free(buffer);\n}\n\nuint16_t* GFXcanvas16::getBuffer(void) {\n    return buffer;\n}\n\nvoid GFXcanvas16::drawPixel(int16_t x, int16_t y, uint16_t color) {\n    if(buffer) {\n        if((x < 0) || (y < 0) || (x >= _width) || (y >= _height)) return;\n\n        int16_t t;\n        switch(rotation) {\n            case 1:\n                t = x;\n                x = WIDTH  - 1 - y;\n                y = t;\n                break;\n            case 2:\n                x = WIDTH  - 1 - x;\n                y = HEIGHT - 1 - y;\n                break;\n            case 3:\n                t = x;\n                x = y;\n                y = HEIGHT - 1 - t;\n                break;\n        }\n\n        buffer[x + y * WIDTH] = color;\n    }\n}\n\nvoid GFXcanvas16::fillScreen(uint16_t color) {\n    if(buffer) {\n        uint8_t hi = color >> 8, lo = color & 0xFF;\n        if(hi == lo) {\n            memset(buffer, lo, WIDTH * HEIGHT * 2);\n        } else {\n            uint32_t i, pixels = WIDTH * HEIGHT;\n            for(i=0; i<pixels; i++) buffer[i] = color;\n        }\n    }\n}\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Adafruit_GFX.h",
    "content": "#ifndef _ADAFRUIT_GFX_H\n#define _ADAFRUIT_GFX_H\n\n#if ARDUINO >= 100\n #include \"Arduino.h\"\n #include \"Print.h\"\n#else\n #include \"WProgram.h\"\n#endif\n#include \"gfxfont.h\"\n\nclass Adafruit_GFX : public Print {\n\n public:\n\n  Adafruit_GFX(int16_t w, int16_t h); // Constructor\n\n  // This MUST be defined by the subclass:\n  virtual void drawPixel(int16_t x, int16_t y, uint16_t color) = 0;\n\n  // TRANSACTION API / CORE DRAW API\n  // These MAY be overridden by the subclass to provide device-specific\n  // optimized code.  Otherwise 'generic' versions are used.\n  virtual void startWrite(void);\n  virtual void writePixel(int16_t x, int16_t y, uint16_t color);\n  virtual void writeFillRect(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color);\n  virtual void writeFastVLine(int16_t x, int16_t y, int16_t h, uint16_t color);\n  virtual void writeFastHLine(int16_t x, int16_t y, int16_t w, uint16_t color);\n  virtual void writeLine(int16_t x0, int16_t y0, int16_t x1, int16_t y1, uint16_t color);\n  virtual void endWrite(void);\n\n  // CONTROL API\n  // These MAY be overridden by the subclass to provide device-specific\n  // optimized code.  Otherwise 'generic' versions are used.\n  virtual void setRotation(uint8_t r);\n  virtual void invertDisplay(boolean i);\n\n  // BASIC DRAW API\n  // These MAY be overridden by the subclass to provide device-specific\n  // optimized code.  Otherwise 'generic' versions are used.\n  virtual void\n    // It's good to implement those, even if using transaction API\n    drawFastVLine(int16_t x, int16_t y, int16_t h, uint16_t color),\n    drawFastHLine(int16_t x, int16_t y, int16_t w, uint16_t color),\n    fillRect(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color),\n    fillScreen(uint16_t color),\n    // Optional and probably not necessary to change\n    drawLine(int16_t x0, int16_t y0, int16_t x1, int16_t y1, uint16_t color),\n    drawRect(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color);\n\n  // These exist only with Adafruit_GFX (no subclass overrides)\n  void\n    drawCircle(int16_t x0, int16_t y0, int16_t r, uint16_t color),\n    drawCircleHelper(int16_t x0, int16_t y0, int16_t r, uint8_t cornername,\n      uint16_t color),\n    fillCircle(int16_t x0, int16_t y0, int16_t r, uint16_t color),\n    fillCircleHelper(int16_t x0, int16_t y0, int16_t r, uint8_t cornername,\n      int16_t delta, uint16_t color),\n    drawTriangle(int16_t x0, int16_t y0, int16_t x1, int16_t y1,\n      int16_t x2, int16_t y2, uint16_t color),\n    fillTriangle(int16_t x0, int16_t y0, int16_t x1, int16_t y1,\n      int16_t x2, int16_t y2, uint16_t color),\n    drawRoundRect(int16_t x0, int16_t y0, int16_t w, int16_t h,\n      int16_t radius, uint16_t color),\n    fillRoundRect(int16_t x0, int16_t y0, int16_t w, int16_t h,\n      int16_t radius, uint16_t color),\n    drawBitmap(int16_t x, int16_t y, const uint8_t bitmap[],\n      int16_t w, int16_t h, uint16_t color),\n    drawBitmap(int16_t x, int16_t y, const uint8_t bitmap[],\n      int16_t w, int16_t h, uint16_t color, uint16_t bg),\n    drawBitmap(int16_t x, int16_t y, uint8_t *bitmap,\n      int16_t w, int16_t h, uint16_t color),\n    drawBitmap(int16_t x, int16_t y, uint8_t *bitmap,\n      int16_t w, int16_t h, uint16_t color, uint16_t bg),\n    drawXBitmap(int16_t x, int16_t y, const uint8_t bitmap[],\n      int16_t w, int16_t h, uint16_t color),\n    drawGrayscaleBitmap(int16_t x, int16_t y, const uint8_t bitmap[],\n      int16_t w, int16_t h),\n    drawGrayscaleBitmap(int16_t x, int16_t y, uint8_t *bitmap,\n      int16_t w, int16_t h),\n    drawGrayscaleBitmap(int16_t x, int16_t y,\n      const uint8_t bitmap[], const uint8_t mask[],\n      int16_t w, int16_t h),\n    drawGrayscaleBitmap(int16_t x, int16_t y,\n      uint8_t *bitmap, uint8_t *mask, int16_t w, int16_t h),\n    drawRGBBitmap(int16_t x, int16_t y, const uint16_t bitmap[],\n      int16_t w, int16_t h),\n    drawRGBBitmap(int16_t x, int16_t y, uint16_t *bitmap,\n      int16_t w, int16_t h),\n    drawRGBBitmap(int16_t x, int16_t y,\n      const uint16_t bitmap[], const uint8_t mask[],\n      int16_t w, int16_t h),\n    drawRGBBitmap(int16_t x, int16_t y,\n      uint16_t *bitmap, uint8_t *mask, int16_t w, int16_t h),\n    drawChar(int16_t x, int16_t y, unsigned char c, uint16_t color,\n      uint16_t bg, uint8_t size),\n    setCursor(int16_t x, int16_t y),\n    setTextColor(uint16_t c),\n    setTextColor(uint16_t c, uint16_t bg),\n    setTextSize(uint8_t s),\n    setTextWrap(boolean w),\n    cp437(boolean x=true),\n    setFont(const GFXfont *f = NULL),\n    getTextBounds(char *string, int16_t x, int16_t y,\n      int16_t *x1, int16_t *y1, uint16_t *w, uint16_t *h),\n    getTextBounds(const __FlashStringHelper *s, int16_t x, int16_t y,\n      int16_t *x1, int16_t *y1, uint16_t *w, uint16_t *h);\n\n#if ARDUINO >= 100\n  virtual size_t write(uint8_t);\n#else\n  virtual void   write(uint8_t);\n#endif\n\n  int16_t height(void) const;\n  int16_t width(void) const;\n\n  uint8_t getRotation(void) const;\n\n  // get current cursor position (get rotation safe maximum values, using: width() for x, height() for y)\n  int16_t getCursorX(void) const;\n  int16_t getCursorY(void) const;\n\n protected:\n  void\n    charBounds(char c, int16_t *x, int16_t *y,\n      int16_t *minx, int16_t *miny, int16_t *maxx, int16_t *maxy);\n  const int16_t\n    WIDTH, HEIGHT;   // This is the 'raw' display w/h - never changes\n  int16_t\n    _width, _height, // Display w/h as modified by current rotation\n    cursor_x, cursor_y;\n  uint16_t\n    textcolor, textbgcolor;\n  uint8_t\n    textsize,\n    rotation;\n  boolean\n    wrap,   // If set, 'wrap' text at right edge of display\n    _cp437; // If set, use correct CP437 charset (default is off)\n  GFXfont\n    *gfxFont;\n};\n\nclass Adafruit_GFX_Button {\n\n public:\n  Adafruit_GFX_Button(void);\n  // \"Classic\" initButton() uses center & size\n  void initButton(Adafruit_GFX *gfx, int16_t x, int16_t y,\n   uint16_t w, uint16_t h, uint16_t outline, uint16_t fill,\n   uint16_t textcolor, char *label, uint8_t textsize);\n  // New/alt initButton() uses upper-left corner & size\n  void initButtonUL(Adafruit_GFX *gfx, int16_t x1, int16_t y1,\n   uint16_t w, uint16_t h, uint16_t outline, uint16_t fill,\n   uint16_t textcolor, char *label, uint8_t textsize);\n  void drawButton(boolean inverted = false);\n  boolean contains(int16_t x, int16_t y);\n\n  void press(boolean p);\n  boolean isPressed();\n  boolean justPressed();\n  boolean justReleased();\n\n private:\n  Adafruit_GFX *_gfx;\n  int16_t       _x1, _y1; // Coordinates of top-left corner\n  uint16_t      _w, _h;\n  uint8_t       _textsize;\n  uint16_t      _outlinecolor, _fillcolor, _textcolor;\n  char          _label[10];\n\n  boolean currstate, laststate;\n};\n\nclass GFXcanvas1 : public Adafruit_GFX {\n public:\n  GFXcanvas1(uint16_t w, uint16_t h);\n  ~GFXcanvas1(void);\n  void     drawPixel(int16_t x, int16_t y, uint16_t color),\n           fillScreen(uint16_t color);\n  uint8_t *getBuffer(void);\n private:\n  uint8_t *buffer;\n};\n\nclass GFXcanvas8 : public Adafruit_GFX {\n public:\n  GFXcanvas8(uint16_t w, uint16_t h);\n  ~GFXcanvas8(void);\n  void     drawPixel(int16_t x, int16_t y, uint16_t color),\n           fillScreen(uint16_t color),\n           writeFastHLine(int16_t x, int16_t y, int16_t w, uint16_t color);\n\n  uint8_t *getBuffer(void);\n private:\n  uint8_t *buffer;\n};\n\nclass GFXcanvas16 : public Adafruit_GFX {\n public:\n  GFXcanvas16(uint16_t w, uint16_t h);\n  ~GFXcanvas16(void);\n  void      drawPixel(int16_t x, int16_t y, uint16_t color),\n            fillScreen(uint16_t color);\n  uint16_t *getBuffer(void);\n private:\n  uint16_t *buffer;\n};\n\n#endif // _ADAFRUIT_GFX_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Adafruit_SPITFT.cpp",
    "content": "/***************************************************\n  This is our library for generic SPI TFT Displays with\n  address windows and 16 bit color (e.g. ILI9341, HX8357D, ST7735...)\n\n  Check out the links above for our tutorials and wiring diagrams\n  These displays use SPI to communicate, 4 or 5 pins are required to\n  interface (RST is optional)\n  Adafruit invests time and resources providing this open source code,\n  please support Adafruit and open-source hardware by purchasing\n  products from Adafruit!\n\n  Written by Limor Fried/Ladyada for Adafruit Industries.\n  MIT license, all text above must be included in any redistribution\n ****************************************************/\n\n#ifndef __AVR_ATtiny85__ // NOT A CHANCE of this stuff working on ATtiny!\n\n#include \"Adafruit_SPITFT.h\"\n#ifndef ARDUINO_STM32_FEATHER\n  #include \"pins_arduino.h\"\n#ifndef RASPI\n    #include \"wiring_private.h\"\n#endif\n#endif\n#include <limits.h>\n\n#include \"Adafruit_SPITFT_Macros.h\"\n\n\n\n// Pass 8-bit (each) R,G,B, get back 16-bit packed color\nuint16_t Adafruit_SPITFT::color565(uint8_t r, uint8_t g, uint8_t b) {\n    return ((r & 0xF8) << 8) | ((g & 0xFC) << 3) | ((b & 0xF8) >> 3);\n}\n\nAdafruit_SPITFT::Adafruit_SPITFT(uint16_t w, uint16_t h,\n\t\t\t\t int8_t cs, int8_t dc, int8_t mosi,\n\t\t\t\t int8_t sclk, int8_t rst, int8_t miso) \n  : Adafruit_GFX(w, h) {\n    _cs   = cs;\n    _dc   = dc;\n    _rst  = rst;\n    _sclk = sclk;\n    _mosi = mosi;\n    _miso = miso;\n    _freq = 0;\n#ifdef USE_FAST_PINIO\n    csport    = portOutputRegister(digitalPinToPort(_cs));\n    cspinmask = digitalPinToBitMask(_cs);\n    dcport    = portOutputRegister(digitalPinToPort(_dc));\n    dcpinmask = digitalPinToBitMask(_dc);\n    clkport     = portOutputRegister(digitalPinToPort(_sclk));\n    clkpinmask  = digitalPinToBitMask(_sclk);\n    mosiport    = portOutputRegister(digitalPinToPort(_mosi));\n    mosipinmask = digitalPinToBitMask(_mosi);\n    if(miso >= 0){\n        misoport    = portInputRegister(digitalPinToPort(_miso));\n        misopinmask = digitalPinToBitMask(_miso);\n    } else {\n        misoport    = 0;\n        misopinmask = 0;\n    }\n#endif\n}\n\nAdafruit_SPITFT::Adafruit_SPITFT(uint16_t w, uint16_t h,\n\t\t\t\t int8_t cs, int8_t dc, int8_t rst) \n  : Adafruit_GFX(w, h) {\n    _cs   = cs;\n    _dc   = dc;\n    _rst  = rst;\n    _sclk = -1;\n    _mosi = -1;\n    _miso = -1;\n    _freq = 0;\n#ifdef USE_FAST_PINIO\n    csport    = portOutputRegister(digitalPinToPort(_cs));\n    cspinmask = digitalPinToBitMask(_cs);\n    dcport    = portOutputRegister(digitalPinToPort(_dc));\n    dcpinmask = digitalPinToBitMask(_dc);\n    clkport     = 0;\n    clkpinmask  = 0;\n    mosiport    = 0;\n    mosipinmask = 0;\n    misoport    = 0;\n    misopinmask = 0;\n#endif\n}\n\n\nvoid Adafruit_SPITFT::initSPI(uint32_t freq)\n{\n    _freq = freq;\n\n    // Control Pins\n    pinMode(_dc, OUTPUT);\n    digitalWrite(_dc, LOW);\n    pinMode(_cs, OUTPUT);\n    digitalWrite(_cs, HIGH);\n\n    // Software SPI\n    if(_sclk >= 0){\n        pinMode(_mosi, OUTPUT);\n        digitalWrite(_mosi, LOW);\n        pinMode(_sclk, OUTPUT);\n        digitalWrite(_sclk, HIGH);\n        if(_miso >= 0){\n            pinMode(_miso, INPUT);\n        }\n    }\n\n    // Hardware SPI\n    SPI_BEGIN();\n\n    // toggle RST low to reset\n    if (_rst >= 0) {\n        pinMode(_rst, OUTPUT);\n        digitalWrite(_rst, HIGH);\n        delay(100);\n        digitalWrite(_rst, LOW);\n        delay(100);\n        digitalWrite(_rst, HIGH);\n        delay(200);\n    }\n}\n\nuint8_t Adafruit_SPITFT::spiRead() {\n    if(_sclk < 0){\n        return HSPI_READ();\n    }\n    if(_miso < 0){\n        return 0;\n    }\n    uint8_t r = 0;\n    for (uint8_t i=0; i<8; i++) {\n        SSPI_SCK_LOW();\n        SSPI_SCK_HIGH();\n        r <<= 1;\n        if (SSPI_MISO_READ()){\n            r |= 0x1;\n        }\n    }\n    return r;\n}\n\nvoid Adafruit_SPITFT::spiWrite(uint8_t b) {\n    if(_sclk < 0){\n        HSPI_WRITE(b);\n        return;\n    }\n    for(uint8_t bit = 0x80; bit; bit >>= 1){\n        if((b) & bit){\n            SSPI_MOSI_HIGH();\n        } else {\n            SSPI_MOSI_LOW();\n        }\n        SSPI_SCK_LOW();\n        SSPI_SCK_HIGH();\n    }\n}\n\n\n/*\n * Transaction API\n * */\n\nvoid Adafruit_SPITFT::startWrite(void){\n    SPI_BEGIN_TRANSACTION();\n    SPI_CS_LOW();\n}\n\nvoid Adafruit_SPITFT::endWrite(void){\n    SPI_CS_HIGH();\n    SPI_END_TRANSACTION();\n}\n\nvoid Adafruit_SPITFT::writeCommand(uint8_t cmd){\n    SPI_DC_LOW();\n    spiWrite(cmd);\n    SPI_DC_HIGH();\n}\n\nvoid Adafruit_SPITFT::pushColor(uint16_t color) {\n  startWrite();\n  SPI_WRITE16(color);\n  endWrite();\n}\n\n\nvoid Adafruit_SPITFT::writePixel(uint16_t color){\n    SPI_WRITE16(color);\n}\n\nvoid Adafruit_SPITFT::writePixels(uint16_t * colors, uint32_t len){\n    SPI_WRITE_PIXELS((uint8_t*)colors , len * 2);\n}\n\nvoid Adafruit_SPITFT::writeColor(uint16_t color, uint32_t len){\n#ifdef SPI_HAS_WRITE_PIXELS\n    if(_sclk >= 0){\n        for (uint32_t t=0; t<len; t++){\n            writePixel(color);\n        }\n        return;\n    }\n    static uint16_t temp[SPI_MAX_PIXELS_AT_ONCE];\n    size_t blen = (len > SPI_MAX_PIXELS_AT_ONCE)?SPI_MAX_PIXELS_AT_ONCE:len;\n    uint16_t tlen = 0;\n\n    for (uint32_t t=0; t<blen; t++){\n        temp[t] = color;\n    }\n\n    while(len){\n        tlen = (len>blen)?blen:len;\n        writePixels(temp, tlen);\n        len -= tlen;\n    }\n#else\n    uint8_t hi = color >> 8, lo = color;\n    if(_sclk < 0){ //AVR Optimization\n        for (uint32_t t=len; t; t--){\n            HSPI_WRITE(hi);\n            HSPI_WRITE(lo);\n        }\n        return;\n    }\n    for (uint32_t t=len; t; t--){\n        spiWrite(hi);\n        spiWrite(lo);\n    }\n#endif\n}\n\nvoid Adafruit_SPITFT::writePixel(int16_t x, int16_t y, uint16_t color) {\n    if((x < 0) ||(x >= _width) || (y < 0) || (y >= _height)) return;\n    setAddrWindow(x,y,1,1);\n    writePixel(color);\n}\n\nvoid Adafruit_SPITFT::writeFillRect(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color){\n    if((x >= _width) || (y >= _height)) return;\n    int16_t x2 = x + w - 1, y2 = y + h - 1;\n    if((x2 < 0) || (y2 < 0)) return;\n\n    // Clip left/top\n    if(x < 0) {\n        x = 0;\n        w = x2 + 1;\n    }\n    if(y < 0) {\n        y = 0;\n        h = y2 + 1;\n    }\n\n    // Clip right/bottom\n    if(x2 >= _width)  w = _width  - x;\n    if(y2 >= _height) h = _height - y;\n\n    int32_t len = (int32_t)w * h;\n    setAddrWindow(x, y, w, h);\n    writeColor(color, len);\n}\n\nvoid Adafruit_SPITFT::writeFastVLine(int16_t x, int16_t y, int16_t h, uint16_t color){\n    writeFillRect(x, y, 1, h, color);\n}\n\nvoid Adafruit_SPITFT::writeFastHLine(int16_t x, int16_t y, int16_t w, uint16_t color){\n    writeFillRect(x, y, w, 1, color);\n}\n\nvoid Adafruit_SPITFT::drawPixel(int16_t x, int16_t y, uint16_t color){\n    startWrite();\n    writePixel(x, y, color);\n    endWrite();\n}\n\nvoid Adafruit_SPITFT::drawFastVLine(int16_t x, int16_t y,\n        int16_t h, uint16_t color) {\n    startWrite();\n    writeFastVLine(x, y, h, color);\n    endWrite();\n}\n\nvoid Adafruit_SPITFT::drawFastHLine(int16_t x, int16_t y,\n        int16_t w, uint16_t color) {\n    startWrite();\n    writeFastHLine(x, y, w, color);\n    endWrite();\n}\n\nvoid Adafruit_SPITFT::fillRect(int16_t x, int16_t y, int16_t w, int16_t h,\n        uint16_t color) {\n    startWrite();\n    writeFillRect(x,y,w,h,color);\n    endWrite();\n}\n\n// Adapted from https://github.com/PaulStoffregen/ILI9341_t3\n// by Marc MERLIN. See examples/pictureEmbed to use this.\n// 5/6/2017: function name and arguments have changed for compatibility\n// with current GFX library and to avoid naming problems in prior\n// implementation.  Formerly drawBitmap() with arguments in different order.\nvoid Adafruit_SPITFT::drawRGBBitmap(int16_t x, int16_t y,\n  uint16_t *pcolors, int16_t w, int16_t h) {\n\n    int16_t x2, y2; // Lower-right coord\n    if(( x             >= _width ) ||      // Off-edge right\n       ( y             >= _height) ||      // \" top\n       ((x2 = (x+w-1)) <  0      ) ||      // \" left\n       ((y2 = (y+h-1)) <  0)     ) return; // \" bottom\n\n    int16_t bx1=0, by1=0, // Clipped top-left within bitmap\n            saveW=w;      // Save original bitmap width value\n    if(x < 0) { // Clip left\n        w  +=  x;\n        bx1 = -x;\n        x   =  0;\n    }\n    if(y < 0) { // Clip top\n        h  +=  y;\n        by1 = -y;\n        y   =  0;\n    }\n    if(x2 >= _width ) w = _width  - x; // Clip right\n    if(y2 >= _height) h = _height - y; // Clip bottom\n\n    pcolors += by1 * saveW + bx1; // Offset bitmap ptr to clipped top-left\n    startWrite();\n    setAddrWindow(x, y, w, h); // Clipped area\n    while(h--) { // For each (clipped) scanline...\n      writePixels(pcolors, w); // Push one (clipped) row\n      pcolors += saveW; // Advance pointer by one full (unclipped) line\n    }\n    endWrite();\n}\n\n#endif // !__AVR_ATtiny85__\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Adafruit_SPITFT.h",
    "content": "\n#ifndef _ADAFRUIT_SPITFT_\n#define _ADAFRUIT_SPITFT_\n\n\n#if ARDUINO >= 100\n #include \"Arduino.h\"\n #include \"Print.h\"\n#else\n #include \"WProgram.h\"\n#endif\n#include <SPI.h>\n#include \"Adafruit_GFX.h\"\n\n\n#if defined(ARDUINO_STM32_FEATHER)\ntypedef volatile uint32 RwReg;\n#endif\n#if defined(ARDUINO_FEATHER52)\ntypedef volatile uint32_t RwReg;\n#endif\n\nclass Adafruit_SPITFT : public Adafruit_GFX {\n    protected:\n\n    public:\n        Adafruit_SPITFT(uint16_t w, uint16_t h, int8_t _CS, int8_t _DC, int8_t _MOSI, int8_t _SCLK, int8_t _RST = -1, int8_t _MISO = -1);\n        Adafruit_SPITFT(uint16_t w, uint16_t h, int8_t _CS, int8_t _DC, int8_t _RST = -1);\n\n        virtual void begin(uint32_t freq) = 0;\n        void      initSPI(uint32_t freq);\n\n        // Required Non-Transaction\n        void      drawPixel(int16_t x, int16_t y, uint16_t color);\n\n        // Transaction API\n        void      startWrite(void);\n        void      endWrite(void);\n        void      writePixel(int16_t x, int16_t y, uint16_t color);\n        void      writeFillRect(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color);\n        void      writeFastVLine(int16_t x, int16_t y, int16_t h, uint16_t color);\n        void      writeFastHLine(int16_t x, int16_t y, int16_t w, uint16_t color);\n\n        // Transaction API not used by GFX\n\tvirtual   void setAddrWindow(uint16_t x, uint16_t y, uint16_t w, uint16_t h) = 0;\n        void      writePixel(uint16_t color);\n        void      writePixels(uint16_t * colors, uint32_t len);\n        void      writeColor(uint16_t color, uint32_t len);\n\tvoid      pushColor(uint16_t color);\n\n        // Recommended Non-Transaction\n        void      drawFastVLine(int16_t x, int16_t y, int16_t h, uint16_t color);\n        void      drawFastHLine(int16_t x, int16_t y, int16_t w, uint16_t color);\n        void      fillRect(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color);\n\n        using     Adafruit_GFX::drawRGBBitmap; // Check base class first\n        void      drawRGBBitmap(int16_t x, int16_t y,\n                    uint16_t *pcolors, int16_t w, int16_t h);\n\n        uint16_t  color565(uint8_t r, uint8_t g, uint8_t b);\n\n    protected:\n        uint32_t _freq;\n#if defined (__AVR__) || defined(TEENSYDUINO) || defined (ESP8266) || defined (ESP32)\n        int8_t  _cs, _dc, _rst, _sclk, _mosi, _miso;\n#else \n        int32_t  _cs, _dc, _rst, _sclk, _mosi, _miso;\n#endif\n\n#ifdef USE_FAST_PINIO\n        volatile RwReg *mosiport, *misoport, *clkport, *dcport, *csport;\n        RwReg  mosipinmask, misopinmask, clkpinmask, cspinmask, dcpinmask;\n#endif\n\n        void        writeCommand(uint8_t cmd);\n        void        spiWrite(uint8_t v);\n        uint8_t     spiRead(void);\n};\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Adafruit_SPITFT_Macros.h",
    "content": "\n/*\n * Control Pins\n * */\n\n#ifdef USE_FAST_PINIO\n#define SPI_DC_HIGH()           *dcport |=  dcpinmask\n#define SPI_DC_LOW()            *dcport &= ~dcpinmask\n#define SPI_CS_HIGH()           *csport |= cspinmask\n#define SPI_CS_LOW()            *csport &= ~cspinmask\n#else\n#define SPI_DC_HIGH()           digitalWrite(_dc, HIGH)\n#define SPI_DC_LOW()            digitalWrite(_dc, LOW)\n#define SPI_CS_HIGH()           digitalWrite(_cs, HIGH)\n#define SPI_CS_LOW()            digitalWrite(_cs, LOW)\n#endif\n\n/*\n * Software SPI Macros\n * */\n\n#ifdef USE_FAST_PINIO\n#define SSPI_MOSI_HIGH()        *mosiport |=  mosipinmask\n#define SSPI_MOSI_LOW()         *mosiport &= ~mosipinmask\n#define SSPI_SCK_HIGH()         *clkport |=  clkpinmask\n#define SSPI_SCK_LOW()          *clkport &= ~clkpinmask\n#define SSPI_MISO_READ()        ((*misoport & misopinmask) != 0)\n#else\n#define SSPI_MOSI_HIGH()        digitalWrite(_mosi, HIGH)\n#define SSPI_MOSI_LOW()         digitalWrite(_mosi, LOW)\n#define SSPI_SCK_HIGH()         digitalWrite(_sclk, HIGH)\n#define SSPI_SCK_LOW()          digitalWrite(_sclk, LOW)\n#define SSPI_MISO_READ()        digitalRead(_miso)\n#endif\n\n#define SSPI_BEGIN_TRANSACTION()\n#define SSPI_END_TRANSACTION()\n#define SSPI_WRITE(v)           spiWrite(v)\n#define SSPI_WRITE16(s)         SSPI_WRITE((s) >> 8); SSPI_WRITE(s)\n#define SSPI_WRITE32(l)         SSPI_WRITE((l) >> 24); SSPI_WRITE((l) >> 16); SSPI_WRITE((l) >> 8); SSPI_WRITE(l)\n#define SSPI_WRITE_PIXELS(c,l)  for(uint32_t i=0; i<(l); i+=2){ SSPI_WRITE(((uint8_t*)(c))[i+1]); SSPI_WRITE(((uint8_t*)(c))[i]); }\n\n/*\n * Hardware SPI Macros\n * */\n\n#define SPI_OBJECT  SPI\n\n#if defined (__AVR__) ||  defined(TEENSYDUINO) ||  defined(ARDUINO_ARCH_STM32F1)\n    #define HSPI_SET_CLOCK() SPI_OBJECT.setClockDivider(SPI_CLOCK_DIV2);\n#elif defined (__arm__)\n    #define HSPI_SET_CLOCK() SPI_OBJECT.setClockDivider(11);\n#elif defined(ESP8266) || defined(ESP32)\n    #define HSPI_SET_CLOCK() SPI_OBJECT.setFrequency(_freq);\n#elif defined(RASPI)\n    #define HSPI_SET_CLOCK() SPI_OBJECT.setClock(_freq);\n#elif defined(ARDUINO_ARCH_STM32F1)\n    #define HSPI_SET_CLOCK() SPI_OBJECT.setClock(_freq);\n#else\n    #define HSPI_SET_CLOCK()\n#endif\n\n#ifdef SPI_HAS_TRANSACTION\n    #define HSPI_BEGIN_TRANSACTION() SPI_OBJECT.beginTransaction(SPISettings(_freq, MSBFIRST, SPI_MODE0))\n    #define HSPI_END_TRANSACTION()   SPI_OBJECT.endTransaction()\n#else\n    #define HSPI_BEGIN_TRANSACTION() HSPI_SET_CLOCK(); SPI_OBJECT.setBitOrder(MSBFIRST); SPI_OBJECT.setDataMode(SPI_MODE0)\n    #define HSPI_END_TRANSACTION()\n#endif\n\n#ifdef ESP32\n    #define SPI_HAS_WRITE_PIXELS\n#endif\n#if defined(ESP8266) || defined(ESP32)\n    // Optimized SPI (ESP8266 and ESP32)\n    #define HSPI_READ()              SPI_OBJECT.transfer(0)\n    #define HSPI_WRITE(b)            SPI_OBJECT.write(b)\n    #define HSPI_WRITE16(s)          SPI_OBJECT.write16(s)\n    #define HSPI_WRITE32(l)          SPI_OBJECT.write32(l)\n    #ifdef SPI_HAS_WRITE_PIXELS\n        #define SPI_MAX_PIXELS_AT_ONCE  32\n        #define HSPI_WRITE_PIXELS(c,l)   SPI_OBJECT.writePixels(c,l)\n    #else\n        #define HSPI_WRITE_PIXELS(c,l)   for(uint32_t i=0; i<((l)/2); i++){ SPI_WRITE16(((uint16_t*)(c))[i]); }\n    #endif\n#else\n    // Standard Byte-by-Byte SPI\n\n    #if defined (__AVR__) || defined(TEENSYDUINO)\nstatic inline uint8_t _avr_spi_read(void) __attribute__((always_inline));\nstatic inline uint8_t _avr_spi_read(void) {\n    uint8_t r = 0;\n    SPDR = r;\n    while(!(SPSR & _BV(SPIF)));\n    r = SPDR;\n    return r;\n}\n        #define HSPI_WRITE(b)            {SPDR = (b); while(!(SPSR & _BV(SPIF)));}\n        #define HSPI_READ()              _avr_spi_read()\n    #else\n        #define HSPI_WRITE(b)            SPI_OBJECT.transfer((uint8_t)(b))\n        #define HSPI_READ()              HSPI_WRITE(0)\n    #endif\n    #define HSPI_WRITE16(s)          HSPI_WRITE((s) >> 8); HSPI_WRITE(s)\n    #define HSPI_WRITE32(l)          HSPI_WRITE((l) >> 24); HSPI_WRITE((l) >> 16); HSPI_WRITE((l) >> 8); HSPI_WRITE(l)\n    #define HSPI_WRITE_PIXELS(c,l)   for(uint32_t i=0; i<(l); i+=2){ HSPI_WRITE(((uint8_t*)(c))[i+1]); HSPI_WRITE(((uint8_t*)(c))[i]); }\n#endif\n\n#define SPI_BEGIN()             if(_sclk < 0){SPI_OBJECT.begin();}\n#define SPI_BEGIN_TRANSACTION() if(_sclk < 0){HSPI_BEGIN_TRANSACTION();}\n#define SPI_END_TRANSACTION()   if(_sclk < 0){HSPI_END_TRANSACTION();}\n#define SPI_WRITE16(s)          if(_sclk < 0){HSPI_WRITE16(s);}else{SSPI_WRITE16(s);}\n#define SPI_WRITE32(l)          if(_sclk < 0){HSPI_WRITE32(l);}else{SSPI_WRITE32(l);}\n#define SPI_WRITE_PIXELS(c,l)   if(_sclk < 0){HSPI_WRITE_PIXELS(c,l);}else{SSPI_WRITE_PIXELS(c,l);}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeMono12pt7b.h",
    "content": "const uint8_t FreeMono12pt7bBitmaps[] PROGMEM = {\n  0x49, 0x24, 0x92, 0x48, 0x01, 0xF8, 0xE7, 0xE7, 0x67, 0x42, 0x42, 0x42,\n  0x42, 0x09, 0x02, 0x41, 0x10, 0x44, 0x11, 0x1F, 0xF1, 0x10, 0x4C, 0x12,\n  0x3F, 0xE1, 0x20, 0x48, 0x12, 0x04, 0x81, 0x20, 0x48, 0x04, 0x07, 0xA2,\n  0x19, 0x02, 0x40, 0x10, 0x03, 0x00, 0x3C, 0x00, 0x80, 0x10, 0x06, 0x01,\n  0xE0, 0xA7, 0xC0, 0x40, 0x10, 0x04, 0x00, 0x3C, 0x19, 0x84, 0x21, 0x08,\n  0x66, 0x0F, 0x00, 0x0C, 0x1C, 0x78, 0x01, 0xE0, 0xCC, 0x21, 0x08, 0x43,\n  0x30, 0x78, 0x3E, 0x30, 0x10, 0x08, 0x02, 0x03, 0x03, 0x47, 0x14, 0x8A,\n  0x43, 0x11, 0x8F, 0x60, 0xFD, 0xA4, 0x90, 0x05, 0x25, 0x24, 0x92, 0x48,\n  0x92, 0x24, 0x11, 0x24, 0x89, 0x24, 0x92, 0x92, 0x90, 0x00, 0x04, 0x02,\n  0x11, 0x07, 0xF0, 0xC0, 0x50, 0x48, 0x42, 0x00, 0x08, 0x04, 0x02, 0x01,\n  0x00, 0x87, 0xFC, 0x20, 0x10, 0x08, 0x04, 0x02, 0x00, 0x3B, 0x9C, 0xCE,\n  0x62, 0x00, 0xFF, 0xE0, 0xFF, 0x80, 0x00, 0x80, 0xC0, 0x40, 0x20, 0x20,\n  0x10, 0x10, 0x08, 0x08, 0x04, 0x04, 0x02, 0x02, 0x01, 0x01, 0x00, 0x80,\n  0x80, 0x40, 0x00, 0x1C, 0x31, 0x90, 0x58, 0x38, 0x0C, 0x06, 0x03, 0x01,\n  0x80, 0xC0, 0x60, 0x30, 0x34, 0x13, 0x18, 0x70, 0x30, 0xE1, 0x44, 0x81,\n  0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x81, 0x1F, 0xC0, 0x1E, 0x10, 0x90,\n  0x68, 0x10, 0x08, 0x0C, 0x04, 0x04, 0x04, 0x06, 0x06, 0x06, 0x06, 0x0E,\n  0x07, 0xFE, 0x3E, 0x10, 0x40, 0x08, 0x02, 0x00, 0x80, 0x40, 0xE0, 0x04,\n  0x00, 0x80, 0x10, 0x04, 0x01, 0x00, 0xD8, 0x63, 0xE0, 0x06, 0x0A, 0x0A,\n  0x12, 0x22, 0x22, 0x42, 0x42, 0x82, 0x82, 0xFF, 0x02, 0x02, 0x02, 0x0F,\n  0x7F, 0x20, 0x10, 0x08, 0x04, 0x02, 0xF1, 0x8C, 0x03, 0x00, 0x80, 0x40,\n  0x20, 0x18, 0x16, 0x18, 0xF0, 0x0F, 0x8C, 0x08, 0x08, 0x04, 0x04, 0x02,\n  0x79, 0x46, 0xC1, 0xE0, 0x60, 0x28, 0x14, 0x19, 0x08, 0x78, 0xFF, 0x81,\n  0x81, 0x02, 0x02, 0x02, 0x02, 0x04, 0x04, 0x04, 0x04, 0x08, 0x08, 0x08,\n  0x08, 0x3E, 0x31, 0xB0, 0x70, 0x18, 0x0C, 0x05, 0x8C, 0x38, 0x63, 0x40,\n  0x60, 0x30, 0x18, 0x1B, 0x18, 0xF8, 0x3C, 0x31, 0x30, 0x50, 0x28, 0x0C,\n  0x0F, 0x06, 0x85, 0x3C, 0x80, 0x40, 0x40, 0x20, 0x20, 0x63, 0xE0, 0xFF,\n  0x80, 0x07, 0xFC, 0x39, 0xCE, 0x00, 0x00, 0x06, 0x33, 0x98, 0xC4, 0x00,\n  0x00, 0xC0, 0x60, 0x18, 0x0C, 0x06, 0x01, 0x80, 0x0C, 0x00, 0x60, 0x03,\n  0x00, 0x30, 0x01, 0x00, 0xFF, 0xF0, 0x00, 0x00, 0x0F, 0xFF, 0xC0, 0x06,\n  0x00, 0x30, 0x01, 0x80, 0x18, 0x01, 0x80, 0xC0, 0x30, 0x18, 0x0C, 0x02,\n  0x00, 0x00, 0x3E, 0x60, 0xA0, 0x20, 0x10, 0x08, 0x08, 0x18, 0x10, 0x08,\n  0x00, 0x00, 0x00, 0x01, 0xC0, 0xE0, 0x1C, 0x31, 0x10, 0x50, 0x28, 0x14,\n  0x3A, 0x25, 0x22, 0x91, 0x4C, 0xA3, 0xF0, 0x08, 0x02, 0x01, 0x80, 0x7C,\n  0x3F, 0x00, 0x0C, 0x00, 0x48, 0x01, 0x20, 0x04, 0x40, 0x21, 0x00, 0x84,\n  0x04, 0x08, 0x1F, 0xE0, 0x40, 0x82, 0x01, 0x08, 0x04, 0x20, 0x13, 0xE1,\n  0xF0, 0xFF, 0x08, 0x11, 0x01, 0x20, 0x24, 0x04, 0x81, 0x1F, 0xC2, 0x06,\n  0x40, 0x68, 0x05, 0x00, 0xA0, 0x14, 0x05, 0xFF, 0x00, 0x1E, 0x48, 0x74,\n  0x05, 0x01, 0x80, 0x20, 0x08, 0x02, 0x00, 0x80, 0x20, 0x04, 0x01, 0x01,\n  0x30, 0x87, 0xC0, 0xFE, 0x10, 0x44, 0x09, 0x02, 0x40, 0x50, 0x14, 0x05,\n  0x01, 0x40, 0x50, 0x14, 0x0D, 0x02, 0x41, 0x3F, 0x80, 0xFF, 0xC8, 0x09,\n  0x01, 0x20, 0x04, 0x00, 0x88, 0x1F, 0x02, 0x20, 0x40, 0x08, 0x01, 0x00,\n  0xA0, 0x14, 0x03, 0xFF, 0xC0, 0xFF, 0xE8, 0x05, 0x00, 0xA0, 0x04, 0x00,\n  0x88, 0x1F, 0x02, 0x20, 0x40, 0x08, 0x01, 0x00, 0x20, 0x04, 0x01, 0xF0,\n  0x00, 0x1F, 0x46, 0x19, 0x01, 0x60, 0x28, 0x01, 0x00, 0x20, 0x04, 0x00,\n  0x83, 0xF0, 0x0B, 0x01, 0x20, 0x23, 0x0C, 0x3E, 0x00, 0xE1, 0xD0, 0x24,\n  0x09, 0x02, 0x40, 0x90, 0x27, 0xF9, 0x02, 0x40, 0x90, 0x24, 0x09, 0x02,\n  0x40, 0xB8, 0x70, 0xFE, 0x20, 0x40, 0x81, 0x02, 0x04, 0x08, 0x10, 0x20,\n  0x40, 0x81, 0x1F, 0xC0, 0x0F, 0xE0, 0x10, 0x02, 0x00, 0x40, 0x08, 0x01,\n  0x00, 0x20, 0x04, 0x80, 0x90, 0x12, 0x02, 0x40, 0xC6, 0x30, 0x7C, 0x00,\n  0xF1, 0xE4, 0x0C, 0x41, 0x04, 0x20, 0x44, 0x04, 0x80, 0x5C, 0x06, 0x60,\n  0x43, 0x04, 0x10, 0x40, 0x84, 0x08, 0x40, 0xCF, 0x07, 0xF8, 0x04, 0x00,\n  0x80, 0x10, 0x02, 0x00, 0x40, 0x08, 0x01, 0x00, 0x20, 0x04, 0x04, 0x80,\n  0x90, 0x12, 0x03, 0xFF, 0xC0, 0xE0, 0x3B, 0x01, 0x94, 0x14, 0xA0, 0xA4,\n  0x89, 0x24, 0x49, 0x14, 0x48, 0xA2, 0x45, 0x12, 0x10, 0x90, 0x04, 0x80,\n  0x24, 0x01, 0x78, 0x3C, 0xE0, 0xF6, 0x02, 0x50, 0x25, 0x02, 0x48, 0x24,\n  0xC2, 0x44, 0x24, 0x22, 0x43, 0x24, 0x12, 0x40, 0xA4, 0x0A, 0x40, 0x6F,\n  0x06, 0x0F, 0x03, 0x0C, 0x60, 0x64, 0x02, 0x80, 0x18, 0x01, 0x80, 0x18,\n  0x01, 0x80, 0x18, 0x01, 0x40, 0x26, 0x06, 0x30, 0xC0, 0xF0, 0xFF, 0x10,\n  0x64, 0x05, 0x01, 0x40, 0x50, 0x34, 0x19, 0xFC, 0x40, 0x10, 0x04, 0x01,\n  0x00, 0x40, 0x3E, 0x00, 0x0F, 0x03, 0x0C, 0x60, 0x64, 0x02, 0x80, 0x18,\n  0x01, 0x80, 0x18, 0x01, 0x80, 0x18, 0x01, 0x40, 0x26, 0x06, 0x30, 0xC1,\n  0xF0, 0x0C, 0x01, 0xF1, 0x30, 0xE0, 0xFF, 0x04, 0x18, 0x40, 0xC4, 0x04,\n  0x40, 0x44, 0x0C, 0x41, 0x87, 0xE0, 0x43, 0x04, 0x10, 0x40, 0x84, 0x04,\n  0x40, 0x4F, 0x03, 0x1F, 0x48, 0x34, 0x05, 0x01, 0x40, 0x08, 0x01, 0xC0,\n  0x0E, 0x00, 0x40, 0x18, 0x06, 0x01, 0xE1, 0xA7, 0xC0, 0xFF, 0xF0, 0x86,\n  0x10, 0x82, 0x00, 0x40, 0x08, 0x01, 0x00, 0x20, 0x04, 0x00, 0x80, 0x10,\n  0x02, 0x00, 0x40, 0x7F, 0x00, 0xF0, 0xF4, 0x02, 0x40, 0x24, 0x02, 0x40,\n  0x24, 0x02, 0x40, 0x24, 0x02, 0x40, 0x24, 0x02, 0x40, 0x22, 0x04, 0x30,\n  0xC0, 0xF0, 0xF8, 0x7C, 0x80, 0x22, 0x01, 0x04, 0x04, 0x10, 0x20, 0x40,\n  0x80, 0x82, 0x02, 0x10, 0x08, 0x40, 0x11, 0x00, 0x48, 0x01, 0xA0, 0x03,\n  0x00, 0x0C, 0x00, 0xF8, 0x7C, 0x80, 0x22, 0x00, 0x88, 0xC2, 0x23, 0x10,\n  0x8E, 0x42, 0x29, 0x09, 0x24, 0x24, 0x90, 0x91, 0x41, 0x85, 0x06, 0x14,\n  0x18, 0x70, 0x60, 0x80, 0xF0, 0xF2, 0x06, 0x30, 0x41, 0x08, 0x09, 0x80,\n  0x50, 0x06, 0x00, 0x60, 0x0D, 0x00, 0x88, 0x10, 0xC2, 0x04, 0x60, 0x2F,\n  0x0F, 0xF0, 0xF2, 0x02, 0x10, 0x41, 0x04, 0x08, 0x80, 0x50, 0x05, 0x00,\n  0x20, 0x02, 0x00, 0x20, 0x02, 0x00, 0x20, 0x02, 0x01, 0xFC, 0xFF, 0x40,\n  0xA0, 0x90, 0x40, 0x40, 0x40, 0x20, 0x20, 0x20, 0x10, 0x50, 0x30, 0x18,\n  0x0F, 0xFC, 0xF2, 0x49, 0x24, 0x92, 0x49, 0x24, 0x9C, 0x80, 0x60, 0x10,\n  0x08, 0x02, 0x01, 0x00, 0x40, 0x20, 0x08, 0x04, 0x01, 0x00, 0x80, 0x20,\n  0x10, 0x04, 0x02, 0x00, 0x80, 0x40, 0xE4, 0x92, 0x49, 0x24, 0x92, 0x49,\n  0x3C, 0x08, 0x0C, 0x09, 0x0C, 0x4C, 0x14, 0x04, 0xFF, 0xFC, 0x84, 0x21,\n  0x3E, 0x00, 0x60, 0x08, 0x02, 0x3F, 0x98, 0x28, 0x0A, 0x02, 0xC3, 0x9F,\n  0x30, 0xE0, 0x01, 0x00, 0x08, 0x00, 0x40, 0x02, 0x00, 0x13, 0xE0, 0xA0,\n  0x86, 0x02, 0x20, 0x09, 0x00, 0x48, 0x02, 0x40, 0x13, 0x01, 0x14, 0x1B,\n  0x9F, 0x00, 0x1F, 0x4C, 0x19, 0x01, 0x40, 0x28, 0x01, 0x00, 0x20, 0x02,\n  0x00, 0x60, 0x43, 0xF0, 0x00, 0xC0, 0x08, 0x01, 0x00, 0x20, 0x04, 0x3C,\n  0x98, 0x52, 0x06, 0x80, 0x50, 0x0A, 0x01, 0x40, 0x24, 0x0C, 0xC2, 0x87,\n  0x98, 0x3F, 0x18, 0x68, 0x06, 0x01, 0xFF, 0xE0, 0x08, 0x03, 0x00, 0x60,\n  0xC7, 0xC0, 0x0F, 0x98, 0x08, 0x04, 0x02, 0x07, 0xF8, 0x80, 0x40, 0x20,\n  0x10, 0x08, 0x04, 0x02, 0x01, 0x03, 0xF8, 0x1E, 0x6C, 0x39, 0x03, 0x40,\n  0x28, 0x05, 0x00, 0xA0, 0x12, 0x06, 0x61, 0x43, 0xC8, 0x01, 0x00, 0x20,\n  0x08, 0x3E, 0x00, 0xC0, 0x10, 0x04, 0x01, 0x00, 0x40, 0x13, 0x87, 0x11,\n  0x82, 0x40, 0x90, 0x24, 0x09, 0x02, 0x40, 0x90, 0x2E, 0x1C, 0x08, 0x04,\n  0x02, 0x00, 0x00, 0x03, 0xC0, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01, 0x00,\n  0x80, 0x43, 0xFE, 0x04, 0x08, 0x10, 0x00, 0x1F, 0xC0, 0x81, 0x02, 0x04,\n  0x08, 0x10, 0x20, 0x40, 0x81, 0x02, 0x0B, 0xE0, 0xE0, 0x02, 0x00, 0x20,\n  0x02, 0x00, 0x20, 0x02, 0x3C, 0x21, 0x02, 0x60, 0x2C, 0x03, 0x80, 0x24,\n  0x02, 0x20, 0x21, 0x02, 0x08, 0xE1, 0xF0, 0x78, 0x04, 0x02, 0x01, 0x00,\n  0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01, 0x00, 0x80, 0x43, 0xFE,\n  0xDC, 0xE3, 0x19, 0x90, 0x84, 0x84, 0x24, 0x21, 0x21, 0x09, 0x08, 0x48,\n  0x42, 0x42, 0x17, 0x18, 0xC0, 0x67, 0x83, 0x84, 0x20, 0x22, 0x02, 0x20,\n  0x22, 0x02, 0x20, 0x22, 0x02, 0x20, 0x2F, 0x07, 0x1F, 0x04, 0x11, 0x01,\n  0x40, 0x18, 0x03, 0x00, 0x60, 0x0A, 0x02, 0x20, 0x83, 0xE0, 0xCF, 0x85,\n  0x06, 0x60, 0x24, 0x01, 0x40, 0x14, 0x01, 0x40, 0x16, 0x02, 0x50, 0x44,\n  0xF8, 0x40, 0x04, 0x00, 0x40, 0x0F, 0x00, 0x1E, 0x6C, 0x3B, 0x03, 0x40,\n  0x28, 0x05, 0x00, 0xA0, 0x12, 0x06, 0x61, 0x43, 0xC8, 0x01, 0x00, 0x20,\n  0x04, 0x03, 0xC0, 0xE3, 0x8B, 0x13, 0x80, 0x80, 0x20, 0x08, 0x02, 0x00,\n  0x80, 0x20, 0x3F, 0x80, 0x1F, 0x58, 0x34, 0x05, 0x80, 0x1E, 0x00, 0x60,\n  0x06, 0x01, 0xC0, 0xAF, 0xC0, 0x20, 0x04, 0x00, 0x80, 0x10, 0x0F, 0xF0,\n  0x40, 0x08, 0x01, 0x00, 0x20, 0x04, 0x00, 0x80, 0x10, 0x03, 0x04, 0x3F,\n  0x00, 0xC1, 0xC8, 0x09, 0x01, 0x20, 0x24, 0x04, 0x80, 0x90, 0x12, 0x02,\n  0x61, 0xC7, 0xCC, 0xF8, 0xF9, 0x01, 0x08, 0x10, 0x60, 0x81, 0x08, 0x08,\n  0x40, 0x22, 0x01, 0x20, 0x05, 0x00, 0x30, 0x00, 0xF0, 0x7A, 0x01, 0x10,\n  0x08, 0x8C, 0x42, 0x62, 0x12, 0x90, 0xA5, 0x05, 0x18, 0x28, 0xC0, 0x86,\n  0x00, 0x78, 0xF3, 0x04, 0x18, 0x80, 0xD0, 0x06, 0x00, 0x70, 0x09, 0x81,\n  0x0C, 0x20, 0x6F, 0x8F, 0xF0, 0xF2, 0x02, 0x20, 0x41, 0x04, 0x10, 0x80,\n  0x88, 0x09, 0x00, 0x50, 0x06, 0x00, 0x20, 0x04, 0x00, 0x40, 0x08, 0x0F,\n  0xE0, 0xFF, 0x41, 0x00, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x40, 0xBF,\n  0xC0, 0x19, 0x08, 0x42, 0x10, 0x84, 0x64, 0x18, 0x42, 0x10, 0x84, 0x20,\n  0xC0, 0xFF, 0xFF, 0xC0, 0xC1, 0x08, 0x42, 0x10, 0x84, 0x10, 0x4C, 0x42,\n  0x10, 0x84, 0x26, 0x00, 0x38, 0x13, 0x38, 0x38 };\n\nconst GFXglyph FreeMono12pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,  14,    0,    1 },   // 0x20 ' '\n  {     0,   3,  15,  14,    6,  -14 },   // 0x21 '!'\n  {     6,   8,   7,  14,    3,  -14 },   // 0x22 '\"'\n  {    13,  10,  16,  14,    2,  -14 },   // 0x23 '#'\n  {    33,  10,  17,  14,    2,  -14 },   // 0x24 '$'\n  {    55,  10,  15,  14,    2,  -14 },   // 0x25 '%'\n  {    74,   9,  12,  14,    3,  -11 },   // 0x26 '&'\n  {    88,   3,   7,  14,    5,  -14 },   // 0x27 '''\n  {    91,   3,  18,  14,    7,  -14 },   // 0x28 '('\n  {    98,   3,  18,  14,    4,  -14 },   // 0x29 ')'\n  {   105,   9,   9,  14,    3,  -14 },   // 0x2A '*'\n  {   116,   9,  11,  14,    3,  -11 },   // 0x2B '+'\n  {   129,   5,   7,  14,    3,   -3 },   // 0x2C ','\n  {   134,  11,   1,  14,    2,   -6 },   // 0x2D '-'\n  {   136,   3,   3,  14,    5,   -2 },   // 0x2E '.'\n  {   138,   9,  18,  14,    3,  -15 },   // 0x2F '/'\n  {   159,   9,  15,  14,    3,  -14 },   // 0x30 '0'\n  {   176,   7,  14,  14,    4,  -13 },   // 0x31 '1'\n  {   189,   9,  15,  14,    2,  -14 },   // 0x32 '2'\n  {   206,  10,  15,  14,    2,  -14 },   // 0x33 '3'\n  {   225,   8,  15,  14,    3,  -14 },   // 0x34 '4'\n  {   240,   9,  15,  14,    3,  -14 },   // 0x35 '5'\n  {   257,   9,  15,  14,    3,  -14 },   // 0x36 '6'\n  {   274,   8,  15,  14,    3,  -14 },   // 0x37 '7'\n  {   289,   9,  15,  14,    3,  -14 },   // 0x38 '8'\n  {   306,   9,  15,  14,    3,  -14 },   // 0x39 '9'\n  {   323,   3,  10,  14,    5,   -9 },   // 0x3A ':'\n  {   327,   5,  13,  14,    3,   -9 },   // 0x3B ';'\n  {   336,  11,  11,  14,    2,  -11 },   // 0x3C '<'\n  {   352,  12,   4,  14,    1,   -8 },   // 0x3D '='\n  {   358,  11,  11,  14,    2,  -11 },   // 0x3E '>'\n  {   374,   9,  14,  14,    3,  -13 },   // 0x3F '?'\n  {   390,   9,  16,  14,    3,  -14 },   // 0x40 '@'\n  {   408,  14,  14,  14,    0,  -13 },   // 0x41 'A'\n  {   433,  11,  14,  14,    2,  -13 },   // 0x42 'B'\n  {   453,  10,  14,  14,    2,  -13 },   // 0x43 'C'\n  {   471,  10,  14,  14,    2,  -13 },   // 0x44 'D'\n  {   489,  11,  14,  14,    2,  -13 },   // 0x45 'E'\n  {   509,  11,  14,  14,    2,  -13 },   // 0x46 'F'\n  {   529,  11,  14,  14,    2,  -13 },   // 0x47 'G'\n  {   549,  10,  14,  14,    2,  -13 },   // 0x48 'H'\n  {   567,   7,  14,  14,    4,  -13 },   // 0x49 'I'\n  {   580,  11,  14,  14,    2,  -13 },   // 0x4A 'J'\n  {   600,  12,  14,  14,    2,  -13 },   // 0x4B 'K'\n  {   621,  11,  14,  14,    2,  -13 },   // 0x4C 'L'\n  {   641,  13,  14,  14,    1,  -13 },   // 0x4D 'M'\n  {   664,  12,  14,  14,    1,  -13 },   // 0x4E 'N'\n  {   685,  12,  14,  14,    1,  -13 },   // 0x4F 'O'\n  {   706,  10,  14,  14,    2,  -13 },   // 0x50 'P'\n  {   724,  12,  17,  14,    1,  -13 },   // 0x51 'Q'\n  {   750,  12,  14,  14,    2,  -13 },   // 0x52 'R'\n  {   771,  10,  14,  14,    2,  -13 },   // 0x53 'S'\n  {   789,  11,  14,  14,    2,  -13 },   // 0x54 'T'\n  {   809,  12,  14,  14,    1,  -13 },   // 0x55 'U'\n  {   830,  14,  14,  14,    0,  -13 },   // 0x56 'V'\n  {   855,  14,  14,  14,    0,  -13 },   // 0x57 'W'\n  {   880,  12,  14,  14,    1,  -13 },   // 0x58 'X'\n  {   901,  12,  14,  14,    1,  -13 },   // 0x59 'Y'\n  {   922,   9,  14,  14,    3,  -13 },   // 0x5A 'Z'\n  {   938,   3,  18,  14,    7,  -14 },   // 0x5B '['\n  {   945,   9,  18,  14,    3,  -15 },   // 0x5C '\\'\n  {   966,   3,  18,  14,    5,  -14 },   // 0x5D ']'\n  {   973,   9,   6,  14,    3,  -14 },   // 0x5E '^'\n  {   980,  14,   1,  14,    0,    3 },   // 0x5F '_'\n  {   982,   4,   4,  14,    4,  -15 },   // 0x60 '`'\n  {   984,  10,  10,  14,    2,   -9 },   // 0x61 'a'\n  {   997,  13,  15,  14,    0,  -14 },   // 0x62 'b'\n  {  1022,  11,  10,  14,    2,   -9 },   // 0x63 'c'\n  {  1036,  11,  15,  14,    2,  -14 },   // 0x64 'd'\n  {  1057,  10,  10,  14,    2,   -9 },   // 0x65 'e'\n  {  1070,   9,  15,  14,    4,  -14 },   // 0x66 'f'\n  {  1087,  11,  14,  14,    2,   -9 },   // 0x67 'g'\n  {  1107,  10,  15,  14,    2,  -14 },   // 0x68 'h'\n  {  1126,   9,  15,  14,    3,  -14 },   // 0x69 'i'\n  {  1143,   7,  19,  14,    3,  -14 },   // 0x6A 'j'\n  {  1160,  12,  15,  14,    1,  -14 },   // 0x6B 'k'\n  {  1183,   9,  15,  14,    3,  -14 },   // 0x6C 'l'\n  {  1200,  13,  10,  14,    1,   -9 },   // 0x6D 'm'\n  {  1217,  12,  10,  14,    1,   -9 },   // 0x6E 'n'\n  {  1232,  11,  10,  14,    2,   -9 },   // 0x6F 'o'\n  {  1246,  12,  14,  14,    1,   -9 },   // 0x70 'p'\n  {  1267,  11,  14,  14,    2,   -9 },   // 0x71 'q'\n  {  1287,  10,  10,  14,    3,   -9 },   // 0x72 'r'\n  {  1300,  10,  10,  14,    2,   -9 },   // 0x73 's'\n  {  1313,  11,  14,  14,    1,  -13 },   // 0x74 't'\n  {  1333,  11,  10,  14,    2,   -9 },   // 0x75 'u'\n  {  1347,  13,  10,  14,    1,   -9 },   // 0x76 'v'\n  {  1364,  13,  10,  14,    1,   -9 },   // 0x77 'w'\n  {  1381,  12,  10,  14,    1,   -9 },   // 0x78 'x'\n  {  1396,  12,  14,  14,    1,   -9 },   // 0x79 'y'\n  {  1417,   9,  10,  14,    3,   -9 },   // 0x7A 'z'\n  {  1429,   5,  18,  14,    5,  -14 },   // 0x7B '{'\n  {  1441,   1,  18,  14,    7,  -14 },   // 0x7C '|'\n  {  1444,   5,  18,  14,    5,  -14 },   // 0x7D '}'\n  {  1456,  10,   3,  14,    2,   -7 } }; // 0x7E '~'\n\nconst GFXfont FreeMono12pt7b PROGMEM = {\n  (uint8_t  *)FreeMono12pt7bBitmaps,\n  (GFXglyph *)FreeMono12pt7bGlyphs,\n  0x20, 0x7E, 24 };\n\n// Approx. 2132 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeMono18pt7b.h",
    "content": "const uint8_t FreeMono18pt7bBitmaps[] PROGMEM = {\n  0x27, 0x77, 0x77, 0x77, 0x77, 0x22, 0x22, 0x20, 0x00, 0x6F, 0xF6, 0xF1,\n  0xFE, 0x3F, 0xC7, 0xF8, 0xFF, 0x1E, 0xC3, 0x98, 0x33, 0x06, 0x60, 0xCC,\n  0x18, 0x04, 0x20, 0x10, 0x80, 0x42, 0x01, 0x08, 0x04, 0x20, 0x10, 0x80,\n  0x42, 0x01, 0x10, 0x04, 0x41, 0xFF, 0xF0, 0x44, 0x02, 0x10, 0x08, 0x40,\n  0x21, 0x0F, 0xFF, 0xC2, 0x10, 0x08, 0x40, 0x21, 0x00, 0x84, 0x02, 0x10,\n  0x08, 0x40, 0x23, 0x00, 0x88, 0x02, 0x20, 0x02, 0x00, 0x10, 0x00, 0x80,\n  0x1F, 0xA3, 0x07, 0x10, 0x09, 0x00, 0x48, 0x00, 0x40, 0x03, 0x00, 0x0C,\n  0x00, 0x3C, 0x00, 0x1E, 0x00, 0x18, 0x00, 0x20, 0x01, 0x80, 0x0C, 0x00,\n  0x70, 0x05, 0xE0, 0xC9, 0xF8, 0x01, 0x00, 0x08, 0x00, 0x40, 0x02, 0x00,\n  0x10, 0x00, 0x1E, 0x00, 0x42, 0x01, 0x02, 0x02, 0x04, 0x04, 0x08, 0x08,\n  0x10, 0x08, 0x40, 0x0F, 0x00, 0x00, 0x1E, 0x01, 0xF0, 0x1F, 0x01, 0xE0,\n  0x0E, 0x00, 0x00, 0x3C, 0x00, 0x86, 0x02, 0x06, 0x04, 0x04, 0x08, 0x08,\n  0x10, 0x30, 0x10, 0xC0, 0x1E, 0x00, 0x0F, 0xC1, 0x00, 0x20, 0x02, 0x00,\n  0x20, 0x02, 0x00, 0x10, 0x01, 0x00, 0x08, 0x03, 0xC0, 0x6C, 0x3C, 0x62,\n  0x82, 0x68, 0x34, 0x81, 0xCC, 0x08, 0x61, 0xC3, 0xE7, 0xFF, 0xFF, 0xF6,\n  0x66, 0x66, 0x08, 0xC4, 0x62, 0x31, 0x8C, 0xC6, 0x31, 0x8C, 0x63, 0x18,\n  0xC3, 0x18, 0xC2, 0x18, 0xC3, 0x18, 0x86, 0x10, 0xC2, 0x18, 0xC6, 0x10,\n  0xC6, 0x31, 0x8C, 0x63, 0x18, 0x8C, 0x62, 0x31, 0x98, 0x80, 0x02, 0x00,\n  0x10, 0x00, 0x80, 0x04, 0x0C, 0x21, 0x9D, 0x70, 0x1C, 0x00, 0xA0, 0x0D,\n  0x80, 0xC6, 0x04, 0x10, 0x40, 0x80, 0x01, 0x00, 0x02, 0x00, 0x04, 0x00,\n  0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x40, 0x00, 0x80, 0xFF, 0xFE, 0x02,\n  0x00, 0x04, 0x00, 0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x40, 0x00, 0x80,\n  0x01, 0x00, 0x3E, 0x78, 0xF3, 0xC7, 0x8E, 0x18, 0x70, 0xC1, 0x80, 0xFF,\n  0xFE, 0x77, 0xFF, 0xF7, 0x00, 0x00, 0x08, 0x00, 0xC0, 0x04, 0x00, 0x60,\n  0x02, 0x00, 0x30, 0x01, 0x00, 0x18, 0x00, 0x80, 0x0C, 0x00, 0x40, 0x02,\n  0x00, 0x20, 0x01, 0x00, 0x10, 0x00, 0x80, 0x08, 0x00, 0x40, 0x04, 0x00,\n  0x20, 0x02, 0x00, 0x10, 0x01, 0x00, 0x08, 0x00, 0x80, 0x04, 0x00, 0x00,\n  0x0F, 0x81, 0x82, 0x08, 0x08, 0x80, 0x24, 0x01, 0x60, 0x0E, 0x00, 0x30,\n  0x01, 0x80, 0x0C, 0x00, 0x60, 0x03, 0x00, 0x18, 0x00, 0xC0, 0x06, 0x00,\n  0x30, 0x03, 0x40, 0x12, 0x00, 0x88, 0x08, 0x60, 0xC0, 0xF8, 0x00, 0x06,\n  0x00, 0x70, 0x06, 0x80, 0x64, 0x06, 0x20, 0x31, 0x00, 0x08, 0x00, 0x40,\n  0x02, 0x00, 0x10, 0x00, 0x80, 0x04, 0x00, 0x20, 0x01, 0x00, 0x08, 0x00,\n  0x40, 0x02, 0x00, 0x10, 0x00, 0x80, 0x04, 0x0F, 0xFF, 0x80, 0x0F, 0x80,\n  0xC3, 0x08, 0x04, 0x80, 0x24, 0x00, 0x80, 0x04, 0x00, 0x20, 0x02, 0x00,\n  0x10, 0x01, 0x00, 0x10, 0x01, 0x80, 0x18, 0x01, 0x80, 0x18, 0x01, 0x80,\n  0x18, 0x01, 0x80, 0x58, 0x03, 0x80, 0x1F, 0xFF, 0x80, 0x0F, 0xC0, 0xC0,\n  0x86, 0x01, 0x00, 0x02, 0x00, 0x08, 0x00, 0x20, 0x00, 0x80, 0x04, 0x00,\n  0x20, 0x0F, 0x00, 0x06, 0x00, 0x04, 0x00, 0x08, 0x00, 0x10, 0x00, 0x40,\n  0x01, 0x00, 0x04, 0x00, 0x2C, 0x01, 0x9C, 0x0C, 0x0F, 0xC0, 0x01, 0xC0,\n  0x14, 0x02, 0x40, 0x64, 0x04, 0x40, 0xC4, 0x08, 0x41, 0x84, 0x10, 0x42,\n  0x04, 0x20, 0x44, 0x04, 0x40, 0x48, 0x04, 0xFF, 0xF0, 0x04, 0x00, 0x40,\n  0x04, 0x00, 0x40, 0x04, 0x07, 0xF0, 0x3F, 0xF0, 0x80, 0x02, 0x00, 0x08,\n  0x00, 0x20, 0x00, 0x80, 0x02, 0x00, 0x0B, 0xF0, 0x30, 0x30, 0x00, 0x60,\n  0x00, 0x80, 0x01, 0x00, 0x04, 0x00, 0x10, 0x00, 0x40, 0x01, 0x00, 0x0E,\n  0x00, 0x2C, 0x01, 0x0C, 0x18, 0x0F, 0xC0, 0x01, 0xF0, 0x60, 0x18, 0x03,\n  0x00, 0x20, 0x04, 0x00, 0x40, 0x0C, 0x00, 0x80, 0x08, 0xF8, 0x98, 0x4A,\n  0x02, 0xE0, 0x3C, 0x01, 0x80, 0x14, 0x01, 0x40, 0x14, 0x03, 0x20, 0x21,\n  0x0C, 0x0F, 0x80, 0xFF, 0xF8, 0x01, 0x80, 0x18, 0x03, 0x00, 0x20, 0x02,\n  0x00, 0x20, 0x04, 0x00, 0x40, 0x04, 0x00, 0xC0, 0x08, 0x00, 0x80, 0x18,\n  0x01, 0x00, 0x10, 0x01, 0x00, 0x30, 0x02, 0x00, 0x20, 0x02, 0x00, 0x0F,\n  0x81, 0x83, 0x10, 0x05, 0x80, 0x38, 0x00, 0xC0, 0x06, 0x00, 0x30, 0x03,\n  0x40, 0x11, 0x83, 0x07, 0xF0, 0x60, 0xC4, 0x01, 0x60, 0x0E, 0x00, 0x30,\n  0x01, 0x80, 0x0E, 0x00, 0xD0, 0x04, 0x60, 0xC1, 0xFC, 0x00, 0x1F, 0x03,\n  0x08, 0x40, 0x4C, 0x02, 0x80, 0x28, 0x02, 0x80, 0x18, 0x03, 0xC0, 0x74,\n  0x05, 0x21, 0x91, 0xF1, 0x00, 0x10, 0x03, 0x00, 0x20, 0x02, 0x00, 0x40,\n  0x0C, 0x01, 0x80, 0x60, 0xF8, 0x00, 0x77, 0xFF, 0xF7, 0x00, 0x00, 0x00,\n  0x1D, 0xFF, 0xFD, 0xC0, 0x1C, 0x7C, 0xF9, 0xF1, 0xC0, 0x00, 0x00, 0x00,\n  0x00, 0xF1, 0xE3, 0x8F, 0x1C, 0x38, 0xE1, 0xC3, 0x06, 0x00, 0x00, 0x06,\n  0x00, 0x18, 0x00, 0xE0, 0x07, 0x00, 0x38, 0x01, 0xC0, 0x06, 0x00, 0x38,\n  0x00, 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x18, 0x00, 0x1C, 0x00, 0x0E,\n  0x00, 0x07, 0x00, 0x03, 0xFF, 0xFF, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x07, 0xFF, 0xFC, 0xC0, 0x00, 0xC0, 0x00, 0xE0, 0x00, 0x70,\n  0x00, 0x38, 0x00, 0x1C, 0x00, 0x0C, 0x00, 0x0E, 0x00, 0x0E, 0x00, 0x70,\n  0x03, 0x80, 0x0C, 0x00, 0x70, 0x03, 0x80, 0x1C, 0x00, 0x60, 0x00, 0x3F,\n  0x8E, 0x0C, 0x80, 0x28, 0x01, 0x80, 0x10, 0x01, 0x00, 0x10, 0x02, 0x00,\n  0xC0, 0x38, 0x06, 0x00, 0x40, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0E,\n  0x01, 0xF0, 0x1F, 0x00, 0xE0, 0x0F, 0x01, 0x86, 0x08, 0x08, 0x80, 0x24,\n  0x01, 0x40, 0x0A, 0x00, 0x50, 0x1E, 0x83, 0x14, 0x20, 0xA2, 0x05, 0x10,\n  0x28, 0x81, 0x46, 0x0A, 0x18, 0x50, 0x3F, 0x80, 0x04, 0x00, 0x10, 0x00,\n  0x80, 0x02, 0x00, 0x18, 0x18, 0x3F, 0x00, 0x1F, 0xF0, 0x00, 0x06, 0x80,\n  0x00, 0x34, 0x00, 0x01, 0x30, 0x00, 0x18, 0x80, 0x00, 0x86, 0x00, 0x04,\n  0x30, 0x00, 0x60, 0x80, 0x02, 0x06, 0x00, 0x10, 0x10, 0x01, 0x80, 0x80,\n  0x08, 0x06, 0x00, 0x7F, 0xF0, 0x06, 0x00, 0x80, 0x20, 0x06, 0x01, 0x00,\n  0x10, 0x18, 0x00, 0xC0, 0x80, 0x06, 0x04, 0x00, 0x11, 0xFC, 0x0F, 0xF0,\n  0xFF, 0xF8, 0x04, 0x01, 0x01, 0x00, 0x20, 0x40, 0x04, 0x10, 0x01, 0x04,\n  0x00, 0x41, 0x00, 0x10, 0x40, 0x08, 0x10, 0x0C, 0x07, 0xFF, 0x01, 0x00,\n  0x70, 0x40, 0x06, 0x10, 0x00, 0x84, 0x00, 0x11, 0x00, 0x04, 0x40, 0x01,\n  0x10, 0x00, 0x44, 0x00, 0x21, 0x00, 0x33, 0xFF, 0xF8, 0x03, 0xF1, 0x06,\n  0x0E, 0x8C, 0x01, 0xC4, 0x00, 0x64, 0x00, 0x12, 0x00, 0x0A, 0x00, 0x01,\n  0x00, 0x00, 0x80, 0x00, 0x40, 0x00, 0x20, 0x00, 0x10, 0x00, 0x08, 0x00,\n  0x04, 0x00, 0x01, 0x00, 0x00, 0x80, 0x00, 0x20, 0x01, 0x88, 0x01, 0x83,\n  0x03, 0x80, 0x7E, 0x00, 0xFF, 0xE0, 0x20, 0x18, 0x20, 0x0C, 0x20, 0x04,\n  0x20, 0x02, 0x20, 0x02, 0x20, 0x01, 0x20, 0x01, 0x20, 0x01, 0x20, 0x01,\n  0x20, 0x01, 0x20, 0x01, 0x20, 0x01, 0x20, 0x01, 0x20, 0x02, 0x20, 0x02,\n  0x20, 0x04, 0x20, 0x0C, 0x20, 0x18, 0xFF, 0xE0, 0xFF, 0xFF, 0x08, 0x00,\n  0x84, 0x00, 0x42, 0x00, 0x21, 0x00, 0x10, 0x80, 0x00, 0x40, 0x00, 0x20,\n  0x40, 0x10, 0x20, 0x0F, 0xF0, 0x04, 0x08, 0x02, 0x04, 0x01, 0x00, 0x00,\n  0x80, 0x00, 0x40, 0x02, 0x20, 0x01, 0x10, 0x00, 0x88, 0x00, 0x44, 0x00,\n  0x3F, 0xFF, 0xF0, 0xFF, 0xFF, 0x88, 0x00, 0x44, 0x00, 0x22, 0x00, 0x11,\n  0x00, 0x08, 0x80, 0x00, 0x40, 0x00, 0x20, 0x40, 0x10, 0x20, 0x0F, 0xF0,\n  0x04, 0x08, 0x02, 0x04, 0x01, 0x00, 0x00, 0x80, 0x00, 0x40, 0x00, 0x20,\n  0x00, 0x10, 0x00, 0x08, 0x00, 0x04, 0x00, 0x1F, 0xF8, 0x00, 0x03, 0xF9,\n  0x06, 0x07, 0x84, 0x00, 0xC4, 0x00, 0x24, 0x00, 0x12, 0x00, 0x02, 0x00,\n  0x01, 0x00, 0x00, 0x80, 0x00, 0x40, 0x00, 0x20, 0x00, 0x10, 0x0F, 0xF8,\n  0x00, 0x14, 0x00, 0x09, 0x00, 0x04, 0x80, 0x02, 0x20, 0x01, 0x18, 0x00,\n  0x83, 0x01, 0xC0, 0x7F, 0x00, 0xFC, 0x3F, 0x20, 0x04, 0x20, 0x04, 0x20,\n  0x04, 0x20, 0x04, 0x20, 0x04, 0x20, 0x04, 0x20, 0x04, 0x20, 0x04, 0x3F,\n  0xFC, 0x20, 0x04, 0x20, 0x04, 0x20, 0x04, 0x20, 0x04, 0x20, 0x04, 0x20,\n  0x04, 0x20, 0x04, 0x20, 0x04, 0x20, 0x04, 0xFC, 0x3F, 0xFF, 0xF8, 0x10,\n  0x00, 0x80, 0x04, 0x00, 0x20, 0x01, 0x00, 0x08, 0x00, 0x40, 0x02, 0x00,\n  0x10, 0x00, 0x80, 0x04, 0x00, 0x20, 0x01, 0x00, 0x08, 0x00, 0x40, 0x02,\n  0x00, 0x10, 0x00, 0x81, 0xFF, 0xF0, 0x03, 0xFF, 0x80, 0x04, 0x00, 0x02,\n  0x00, 0x01, 0x00, 0x00, 0x80, 0x00, 0x40, 0x00, 0x20, 0x00, 0x10, 0x00,\n  0x08, 0x00, 0x04, 0x00, 0x02, 0x10, 0x01, 0x08, 0x00, 0x84, 0x00, 0x42,\n  0x00, 0x21, 0x00, 0x10, 0x80, 0x10, 0x20, 0x18, 0x0C, 0x18, 0x01, 0xF0,\n  0x00, 0xFF, 0x1F, 0x84, 0x01, 0x81, 0x00, 0xC0, 0x40, 0x60, 0x10, 0x30,\n  0x04, 0x18, 0x01, 0x0C, 0x00, 0x46, 0x00, 0x13, 0x00, 0x05, 0xF0, 0x01,\n  0xC6, 0x00, 0x60, 0xC0, 0x10, 0x18, 0x04, 0x06, 0x01, 0x00, 0xC0, 0x40,\n  0x30, 0x10, 0x04, 0x04, 0x01, 0x81, 0x00, 0x23, 0xFC, 0x0F, 0xFF, 0x80,\n  0x10, 0x00, 0x20, 0x00, 0x40, 0x00, 0x80, 0x01, 0x00, 0x02, 0x00, 0x04,\n  0x00, 0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x40, 0x00, 0x80, 0x01, 0x00,\n  0x42, 0x00, 0x84, 0x01, 0x08, 0x02, 0x10, 0x04, 0x20, 0x0F, 0xFF, 0xF0,\n  0xF0, 0x01, 0xE7, 0x00, 0x70, 0xA0, 0x0A, 0x16, 0x03, 0x42, 0x40, 0x48,\n  0x4C, 0x19, 0x08, 0x82, 0x21, 0x10, 0x44, 0x23, 0x18, 0x84, 0x22, 0x10,\n  0x86, 0xC2, 0x10, 0x50, 0x42, 0x0E, 0x08, 0x41, 0xC1, 0x08, 0x00, 0x21,\n  0x00, 0x04, 0x20, 0x00, 0x84, 0x00, 0x10, 0x80, 0x02, 0x7F, 0x03, 0xF0,\n  0xF8, 0x1F, 0xC6, 0x00, 0x41, 0xC0, 0x10, 0x50, 0x04, 0x12, 0x01, 0x04,\n  0xC0, 0x41, 0x10, 0x10, 0x46, 0x04, 0x10, 0x81, 0x04, 0x10, 0x41, 0x04,\n  0x10, 0x40, 0x84, 0x10, 0x31, 0x04, 0x04, 0x41, 0x01, 0x90, 0x40, 0x24,\n  0x10, 0x05, 0x04, 0x01, 0xC1, 0x00, 0x31, 0xFC, 0x0C, 0x03, 0xE0, 0x06,\n  0x0C, 0x04, 0x01, 0x04, 0x00, 0x46, 0x00, 0x32, 0x00, 0x0B, 0x00, 0x05,\n  0x00, 0x01, 0x80, 0x00, 0xC0, 0x00, 0x60, 0x00, 0x30, 0x00, 0x18, 0x00,\n  0x0E, 0x00, 0x0D, 0x00, 0x04, 0xC0, 0x06, 0x20, 0x02, 0x08, 0x02, 0x03,\n  0x06, 0x00, 0x7C, 0x00, 0xFF, 0xF0, 0x10, 0x0C, 0x10, 0x02, 0x10, 0x03,\n  0x10, 0x01, 0x10, 0x01, 0x10, 0x01, 0x10, 0x03, 0x10, 0x06, 0x10, 0x0C,\n  0x1F, 0xF0, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00,\n  0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0xFF, 0xC0, 0x03, 0xE0, 0x06, 0x0C,\n  0x04, 0x01, 0x04, 0x00, 0x46, 0x00, 0x32, 0x00, 0x0B, 0x00, 0x07, 0x00,\n  0x01, 0x80, 0x00, 0xC0, 0x00, 0x60, 0x00, 0x30, 0x00, 0x18, 0x00, 0x0E,\n  0x00, 0x0D, 0x00, 0x04, 0xC0, 0x06, 0x20, 0x02, 0x08, 0x02, 0x03, 0x06,\n  0x00, 0xFC, 0x00, 0x30, 0x00, 0x30, 0x00, 0x7F, 0xC6, 0x38, 0x1E, 0xFF,\n  0xF0, 0x02, 0x01, 0x80, 0x40, 0x08, 0x08, 0x01, 0x81, 0x00, 0x10, 0x20,\n  0x02, 0x04, 0x00, 0x40, 0x80, 0x18, 0x10, 0x06, 0x02, 0x03, 0x80, 0x7F,\n  0xC0, 0x08, 0x18, 0x01, 0x01, 0x80, 0x20, 0x18, 0x04, 0x01, 0x80, 0x80,\n  0x10, 0x10, 0x03, 0x02, 0x00, 0x20, 0x40, 0x06, 0x7F, 0x80, 0x70, 0x0F,\n  0xC8, 0x61, 0xE2, 0x01, 0x90, 0x02, 0x40, 0x09, 0x00, 0x04, 0x00, 0x08,\n  0x00, 0x38, 0x00, 0x3E, 0x00, 0x0F, 0x00, 0x06, 0x00, 0x0C, 0x00, 0x18,\n  0x00, 0x60, 0x01, 0x80, 0x0F, 0x00, 0x2B, 0x03, 0x23, 0xF0, 0xFF, 0xFF,\n  0x02, 0x06, 0x04, 0x0C, 0x08, 0x18, 0x10, 0x20, 0x20, 0x00, 0x40, 0x00,\n  0x80, 0x01, 0x00, 0x02, 0x00, 0x04, 0x00, 0x08, 0x00, 0x10, 0x00, 0x20,\n  0x00, 0x40, 0x00, 0x80, 0x01, 0x00, 0x02, 0x00, 0x04, 0x01, 0xFF, 0xC0,\n  0xFC, 0x1F, 0x90, 0x01, 0x08, 0x00, 0x84, 0x00, 0x42, 0x00, 0x21, 0x00,\n  0x10, 0x80, 0x08, 0x40, 0x04, 0x20, 0x02, 0x10, 0x01, 0x08, 0x00, 0x84,\n  0x00, 0x42, 0x00, 0x21, 0x00, 0x10, 0x80, 0x08, 0x40, 0x04, 0x10, 0x04,\n  0x0C, 0x06, 0x03, 0x06, 0x00, 0x7C, 0x00, 0xFE, 0x03, 0xF8, 0x80, 0x02,\n  0x04, 0x00, 0x10, 0x30, 0x01, 0x80, 0x80, 0x08, 0x06, 0x00, 0xC0, 0x30,\n  0x06, 0x00, 0x80, 0x20, 0x06, 0x03, 0x00, 0x30, 0x10, 0x00, 0x80, 0x80,\n  0x06, 0x0C, 0x00, 0x10, 0x40, 0x00, 0x86, 0x00, 0x06, 0x20, 0x00, 0x11,\n  0x00, 0x00, 0xD8, 0x00, 0x06, 0x80, 0x00, 0x1C, 0x00, 0x00, 0xE0, 0x00,\n  0xFC, 0x0F, 0xE8, 0x00, 0x19, 0x00, 0x03, 0x10, 0x00, 0x62, 0x00, 0x08,\n  0x41, 0x81, 0x08, 0x28, 0x21, 0x05, 0x04, 0x21, 0xA0, 0x84, 0x36, 0x30,\n  0x84, 0x46, 0x08, 0x88, 0xC1, 0x31, 0x18, 0x24, 0x12, 0x04, 0x82, 0x40,\n  0xB0, 0x48, 0x14, 0x09, 0x02, 0x80, 0xA0, 0x30, 0x1C, 0x06, 0x03, 0x80,\n  0x7E, 0x0F, 0xC2, 0x00, 0x60, 0x60, 0x0C, 0x06, 0x03, 0x00, 0x60, 0xC0,\n  0x0C, 0x10, 0x00, 0xC6, 0x00, 0x0D, 0x80, 0x00, 0xA0, 0x00, 0x1C, 0x00,\n  0x03, 0x80, 0x00, 0xD8, 0x00, 0x11, 0x00, 0x06, 0x30, 0x01, 0x83, 0x00,\n  0x60, 0x30, 0x08, 0x06, 0x03, 0x00, 0x60, 0xC0, 0x06, 0x7F, 0x07, 0xF0,\n  0xFC, 0x1F, 0x98, 0x03, 0x04, 0x01, 0x03, 0x01, 0x80, 0xC1, 0x80, 0x20,\n  0x80, 0x18, 0xC0, 0x04, 0x40, 0x03, 0x60, 0x00, 0xE0, 0x00, 0x20, 0x00,\n  0x10, 0x00, 0x08, 0x00, 0x04, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x80,\n  0x00, 0x40, 0x00, 0x20, 0x03, 0xFF, 0x80, 0xFF, 0xF4, 0x00, 0xA0, 0x09,\n  0x00, 0x48, 0x04, 0x40, 0x40, 0x02, 0x00, 0x20, 0x02, 0x00, 0x10, 0x01,\n  0x00, 0x10, 0x00, 0x80, 0x08, 0x04, 0x80, 0x24, 0x01, 0x40, 0x0C, 0x00,\n  0x60, 0x03, 0xFF, 0xF0, 0xFC, 0x21, 0x08, 0x42, 0x10, 0x84, 0x21, 0x08,\n  0x42, 0x10, 0x84, 0x21, 0x08, 0x42, 0x10, 0xF8, 0x80, 0x02, 0x00, 0x10,\n  0x00, 0xC0, 0x02, 0x00, 0x18, 0x00, 0x40, 0x03, 0x00, 0x08, 0x00, 0x40,\n  0x01, 0x00, 0x08, 0x00, 0x20, 0x01, 0x00, 0x04, 0x00, 0x20, 0x00, 0x80,\n  0x04, 0x00, 0x10, 0x00, 0x80, 0x02, 0x00, 0x10, 0x00, 0x40, 0x02, 0x00,\n  0x08, 0x00, 0x40, 0xF8, 0x42, 0x10, 0x84, 0x21, 0x08, 0x42, 0x10, 0x84,\n  0x21, 0x08, 0x42, 0x10, 0x84, 0x21, 0xF8, 0x02, 0x00, 0x38, 0x03, 0x60,\n  0x11, 0x01, 0x8C, 0x18, 0x31, 0x80, 0xD8, 0x03, 0x80, 0x08, 0xFF, 0xFF,\n  0xF8, 0xC1, 0x83, 0x06, 0x0C, 0x0F, 0xC0, 0x70, 0x30, 0x00, 0x10, 0x00,\n  0x08, 0x00, 0x08, 0x00, 0x08, 0x0F, 0xF8, 0x30, 0x08, 0x40, 0x08, 0x80,\n  0x08, 0x80, 0x08, 0x80, 0x08, 0x80, 0x38, 0x60, 0xE8, 0x3F, 0x8F, 0xF0,\n  0x00, 0x04, 0x00, 0x01, 0x00, 0x00, 0x40, 0x00, 0x10, 0x00, 0x04, 0x00,\n  0x01, 0x0F, 0x80, 0x4C, 0x18, 0x14, 0x01, 0x06, 0x00, 0x21, 0x80, 0x08,\n  0x40, 0x01, 0x10, 0x00, 0x44, 0x00, 0x11, 0x00, 0x04, 0x40, 0x01, 0x18,\n  0x00, 0x86, 0x00, 0x21, 0xC0, 0x10, 0x5C, 0x18, 0xF1, 0xF8, 0x00, 0x07,\n  0xE4, 0x30, 0x78, 0x80, 0x32, 0x00, 0x24, 0x00, 0x50, 0x00, 0x20, 0x00,\n  0x40, 0x00, 0x80, 0x01, 0x00, 0x03, 0x00, 0x02, 0x00, 0x12, 0x00, 0xC3,\n  0x07, 0x01, 0xF8, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x80, 0x00, 0x20, 0x00,\n  0x08, 0x00, 0x02, 0x00, 0x00, 0x80, 0x7C, 0x20, 0x60, 0xC8, 0x20, 0x0A,\n  0x10, 0x01, 0x84, 0x00, 0x62, 0x00, 0x08, 0x80, 0x02, 0x20, 0x00, 0x88,\n  0x00, 0x22, 0x00, 0x08, 0xC0, 0x06, 0x10, 0x01, 0x82, 0x00, 0xE0, 0x60,\n  0xE8, 0x0F, 0xE3, 0xC0, 0x07, 0xE0, 0x1C, 0x18, 0x30, 0x0C, 0x60, 0x06,\n  0x40, 0x03, 0xC0, 0x03, 0xC0, 0x01, 0xFF, 0xFF, 0xC0, 0x00, 0xC0, 0x00,\n  0x40, 0x00, 0x60, 0x00, 0x30, 0x03, 0x0C, 0x0E, 0x03, 0xF0, 0x03, 0xFC,\n  0x18, 0x00, 0x80, 0x02, 0x00, 0x08, 0x00, 0x20, 0x0F, 0xFF, 0x82, 0x00,\n  0x08, 0x00, 0x20, 0x00, 0x80, 0x02, 0x00, 0x08, 0x00, 0x20, 0x00, 0x80,\n  0x02, 0x00, 0x08, 0x00, 0x20, 0x00, 0x80, 0x02, 0x00, 0xFF, 0xF0, 0x0F,\n  0xC7, 0x9C, 0x3A, 0x18, 0x07, 0x08, 0x01, 0x8C, 0x00, 0xC4, 0x00, 0x22,\n  0x00, 0x11, 0x00, 0x08, 0x80, 0x04, 0x40, 0x02, 0x10, 0x03, 0x08, 0x01,\n  0x82, 0x01, 0x40, 0xC3, 0x20, 0x3F, 0x10, 0x00, 0x08, 0x00, 0x04, 0x00,\n  0x02, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x7F, 0x00, 0xF0, 0x00,\n  0x08, 0x00, 0x04, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x80, 0x00, 0x47,\n  0xC0, 0x2C, 0x18, 0x1C, 0x04, 0x0C, 0x01, 0x04, 0x00, 0x82, 0x00, 0x41,\n  0x00, 0x20, 0x80, 0x10, 0x40, 0x08, 0x20, 0x04, 0x10, 0x02, 0x08, 0x01,\n  0x04, 0x00, 0x82, 0x00, 0x47, 0xC0, 0xF8, 0x06, 0x00, 0x18, 0x00, 0x60,\n  0x01, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x80, 0x02, 0x00, 0x08,\n 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0x08, 0x10, 0x81, 0x02, 0x10, 0x20, 0x42, 0x04,\n  0x08, 0x40, 0x81, 0x3E, 0x1C, 0x38, 0x71, 0xF0, 0x0B, 0x06, 0x07, 0x01,\n  0x03, 0x00, 0x41, 0x00, 0x20, 0x80, 0x10, 0x40, 0x08, 0x20, 0x04, 0x10,\n  0x02, 0x08, 0x01, 0x04, 0x00, 0x82, 0x00, 0x41, 0x00, 0x20, 0x80, 0x13,\n  0xF0, 0x3E, 0x07, 0xC0, 0x30, 0x60, 0x80, 0x22, 0x00, 0x24, 0x00, 0x50,\n  0x00, 0x60, 0x00, 0xC0, 0x01, 0x80, 0x03, 0x00, 0x05, 0x00, 0x12, 0x00,\n  0x22, 0x00, 0x83, 0x06, 0x01, 0xF0, 0x00, 0xF1, 0xFC, 0x05, 0xC1, 0x81,\n  0xC0, 0x10, 0x60, 0x02, 0x18, 0x00, 0xC4, 0x00, 0x11, 0x00, 0x04, 0x40,\n  0x01, 0x10, 0x00, 0x44, 0x00, 0x11, 0x80, 0x08, 0x60, 0x02, 0x14, 0x01,\n  0x04, 0xC1, 0x81, 0x0F, 0x80, 0x40, 0x00, 0x10, 0x00, 0x04, 0x00, 0x01,\n  0x00, 0x00, 0x40, 0x00, 0x10, 0x00, 0x3F, 0xC0, 0x00, 0x0F, 0xE3, 0xC6,\n  0x0E, 0x86, 0x00, 0xE1, 0x00, 0x18, 0xC0, 0x06, 0x20, 0x00, 0x88, 0x00,\n  0x22, 0x00, 0x08, 0x80, 0x02, 0x20, 0x00, 0x84, 0x00, 0x61, 0x00, 0x18,\n  0x20, 0x0A, 0x06, 0x0C, 0x80, 0x7C, 0x20, 0x00, 0x08, 0x00, 0x02, 0x00,\n  0x00, 0x80, 0x00, 0x20, 0x00, 0x08, 0x00, 0x02, 0x00, 0x0F, 0xF0, 0xF8,\n  0x7C, 0x11, 0x8C, 0x2C, 0x00, 0x70, 0x00, 0xC0, 0x01, 0x00, 0x02, 0x00,\n  0x04, 0x00, 0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x40, 0x00, 0x80, 0x01,\n  0x00, 0x3F, 0xFC, 0x00, 0x0F, 0xD1, 0x83, 0x98, 0x04, 0x80, 0x24, 0x00,\n  0x30, 0x00, 0xF0, 0x00, 0xFC, 0x00, 0x30, 0x00, 0xE0, 0x03, 0x00, 0x1C,\n  0x01, 0xF0, 0x1A, 0x7F, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08,\n  0x00, 0x08, 0x00, 0xFF, 0xFC, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08,\n  0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08,\n  0x00, 0x08, 0x00, 0x08, 0x01, 0x06, 0x0F, 0x03, 0xF8, 0xF0, 0x3E, 0x08,\n  0x01, 0x04, 0x00, 0x82, 0x00, 0x41, 0x00, 0x20, 0x80, 0x10, 0x40, 0x08,\n  0x20, 0x04, 0x10, 0x02, 0x08, 0x01, 0x04, 0x00, 0x82, 0x00, 0x41, 0x00,\n  0xE0, 0x41, 0xD0, 0x1F, 0x8E, 0xFE, 0x0F, 0xE2, 0x00, 0x20, 0x60, 0x0C,\n  0x0C, 0x01, 0x80, 0x80, 0x20, 0x18, 0x0C, 0x01, 0x01, 0x00, 0x30, 0x60,\n  0x02, 0x08, 0x00, 0x41, 0x00, 0x0C, 0x60, 0x00, 0x88, 0x00, 0x19, 0x00,\n  0x01, 0x40, 0x00, 0x38, 0x00, 0xFC, 0x07, 0xE4, 0x00, 0x10, 0x80, 0x02,\n  0x18, 0x20, 0xC3, 0x0E, 0x18, 0x21, 0x42, 0x04, 0x28, 0x40, 0x8D, 0x88,\n  0x19, 0x93, 0x03, 0x22, 0x60, 0x2C, 0x68, 0x05, 0x85, 0x00, 0xA0, 0xA0,\n  0x1C, 0x1C, 0x01, 0x81, 0x80, 0x7C, 0x1F, 0x18, 0x03, 0x06, 0x03, 0x01,\n  0x83, 0x00, 0x63, 0x00, 0x1B, 0x00, 0x07, 0x00, 0x03, 0x80, 0x03, 0x60,\n  0x03, 0x18, 0x03, 0x06, 0x03, 0x01, 0x83, 0x00, 0x61, 0x00, 0x33, 0xF0,\n  0x7E, 0xFC, 0x1F, 0x90, 0x01, 0x8C, 0x00, 0x86, 0x00, 0xC1, 0x80, 0x40,\n  0xC0, 0x60, 0x20, 0x20, 0x18, 0x30, 0x04, 0x10, 0x03, 0x08, 0x00, 0x8C,\n  0x00, 0x64, 0x00, 0x16, 0x00, 0x0E, 0x00, 0x07, 0x00, 0x01, 0x00, 0x01,\n  0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, 0x60, 0x00, 0x20, 0x07, 0xFE, 0x00,\n  0xFF, 0xF4, 0x01, 0x20, 0x09, 0x00, 0x80, 0x08, 0x00, 0x80, 0x08, 0x00,\n  0xC0, 0x04, 0x00, 0x40, 0x04, 0x00, 0x40, 0x14, 0x00, 0xA0, 0x07, 0xFF,\n  0xE0, 0x07, 0x0C, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,\n  0x30, 0xC0, 0x30, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,\n  0x0C, 0x07, 0xFF, 0xFF, 0xFF, 0x80, 0xE0, 0x30, 0x10, 0x10, 0x10, 0x10,\n  0x10, 0x10, 0x10, 0x10, 0x10, 0x08, 0x07, 0x0C, 0x10, 0x10, 0x10, 0x10,\n  0x10, 0x10, 0x10, 0x10, 0x10, 0x30, 0xE0, 0x1C, 0x00, 0x44, 0x0D, 0x84,\n  0x36, 0x04, 0x40, 0x07, 0x00 };\n\nconst GFXglyph FreeMono18pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,  21,    0,    1 },   // 0x20 ' '\n  {     0,   4,  22,  21,    8,  -21 },   // 0x21 '!'\n  {    11,  11,  10,  21,    5,  -20 },   // 0x22 '\"'\n  {    25,  14,  24,  21,    3,  -21 },   // 0x23 '#'\n  {    67,  13,  26,  21,    4,  -22 },   // 0x24 '$'\n  {   110,  15,  21,  21,    3,  -20 },   // 0x25 '%'\n  {   150,  12,  18,  21,    4,  -17 },   // 0x26 '&'\n  {   177,   4,  10,  21,    8,  -20 },   // 0x27 '''\n  {   182,   5,  25,  21,   10,  -20 },   // 0x28 '('\n  {   198,   5,  25,  21,    6,  -20 },   // 0x29 ')'\n  {   214,  13,  12,  21,    4,  -20 },   // 0x2A '*'\n  {   234,  15,  17,  21,    3,  -17 },   // 0x2B '+'\n  {   266,   7,  10,  21,    5,   -4 },   // 0x2C ','\n  {   275,  15,   1,  21,    3,   -9 },   // 0x2D '-'\n  {   277,   5,   5,  21,    8,   -4 },   // 0x2E '.'\n  {   281,  13,  26,  21,    4,  -22 },   // 0x2F '/'\n  {   324,  13,  21,  21,    4,  -20 },   // 0x30 '0'\n  {   359,  13,  21,  21,    4,  -20 },   // 0x31 '1'\n  {   394,  13,  21,  21,    3,  -20 },   // 0x32 '2'\n  {   429,  14,  21,  21,    3,  -20 },   // 0x33 '3'\n  {   466,  12,  21,  21,    4,  -20 },   // 0x34 '4'\n  {   498,  14,  21,  21,    3,  -20 },   // 0x35 '5'\n  {   535,  12,  21,  21,    5,  -20 },   // 0x36 '6'\n  {   567,  12,  21,  21,    4,  -20 },   // 0x37 '7'\n  {   599,  13,  21,  21,    4,  -20 },   // 0x38 '8'\n  {   634,  12,  21,  21,    5,  -20 },   // 0x39 '9'\n  {   666,   5,  15,  21,    8,  -14 },   // 0x3A ':'\n  {   676,   7,  20,  21,    5,  -14 },   // 0x3B ';'\n  {   694,  15,  16,  21,    3,  -17 },   // 0x3C '<'\n  {   724,  17,   6,  21,    2,  -12 },   // 0x3D '='\n  {   737,  15,  16,  21,    3,  -17 },   // 0x3E '>'\n  {   767,  12,  20,  21,    5,  -19 },   // 0x3F '?'\n  {   797,  13,  23,  21,    4,  -20 },   // 0x40 '@'\n  {   835,  21,  20,  21,    0,  -19 },   // 0x41 'A'\n  {   888,  18,  20,  21,    1,  -19 },   // 0x42 'B'\n  {   933,  17,  20,  21,    2,  -19 },   // 0x43 'C'\n  {   976,  16,  20,  21,    2,  -19 },   // 0x44 'D'\n  {  1016,  17,  20,  21,    1,  -19 },   // 0x45 'E'\n  {  1059,  17,  20,  21,    1,  -19 },   // 0x46 'F'\n  {  1102,  17,  20,  21,    2,  -19 },   // 0x47 'G'\n  {  1145,  16,  20,  21,    2,  -19 },   // 0x48 'H'\n  {  1185,  13,  20,  21,    4,  -19 },   // 0x49 'I'\n  {  1218,  17,  20,  21,    3,  -19 },   // 0x4A 'J'\n  {  1261,  18,  20,  21,    1,  -19 },   // 0x4B 'K'\n  {  1306,  15,  20,  21,    3,  -19 },   // 0x4C 'L'\n  {  1344,  19,  20,  21,    1,  -19 },   // 0x4D 'M'\n  {  1392,  18,  20,  21,    1,  -19 },   // 0x4E 'N'\n  {  1437,  17,  20,  21,    2,  -19 },   // 0x4F 'O'\n  {  1480,  16,  20,  21,    1,  -19 },   // 0x50 'P'\n  {  1520,  17,  24,  21,    2,  -19 },   // 0x51 'Q'\n  {  1571,  19,  20,  21,    1,  -19 },   // 0x52 'R'\n  {  1619,  14,  20,  21,    3,  -19 },   // 0x53 'S'\n  {  1654,  15,  20,  21,    3,  -19 },   // 0x54 'T'\n  {  1692,  17,  20,  21,    2,  -19 },   // 0x55 'U'\n  {  1735,  21,  20,  21,    0,  -19 },   // 0x56 'V'\n  {  1788,  19,  20,  21,    1,  -19 },   // 0x57 'W'\n  {  1836,  19,  20,  21,    1,  -19 },   // 0x58 'X'\n  {  1884,  17,  20,  21,    2,  -19 },   // 0x59 'Y'\n  {  1927,  13,  20,  21,    4,  -19 },   // 0x5A 'Z'\n  {  1960,   5,  25,  21,   10,  -20 },   // 0x5B '['\n  {  1976,  13,  26,  21,    4,  -22 },   // 0x5C '\\'\n  {  2019,   5,  25,  21,    6,  -20 },   // 0x5D ']'\n  {  2035,  13,   9,  21,    4,  -20 },   // 0x5E '^'\n  {  2050,  21,   1,  21,    0,    4 },   // 0x5F '_'\n  {  2053,   6,   5,  21,    5,  -21 },   // 0x60 '`'\n  {  2057,  16,  15,  21,    3,  -14 },   // 0x61 'a'\n  {  2087,  18,  21,  21,    1,  -20 },   // 0x62 'b'\n  {  2135,  15,  15,  21,    3,  -14 },   // 0x63 'c'\n  {  2164,  18,  21,  21,    2,  -20 },   // 0x64 'd'\n  {  2212,  16,  15,  21,    2,  -14 },   // 0x65 'e'\n  {  2242,  14,  21,  21,    4,  -20 },   // 0x66 'f'\n  {  2279,  17,  22,  21,    2,  -14 },   // 0x67 'g'\n  {  2326,  17,  21,  21,    1,  -20 },   // 0x68 'h'\n  {  2371,  14,  22,  21,    4,  -21 },   // 0x69 'i'\n  {  2410,  10,  29,  21,    5,  -21 },   // 0x6A 'j'\n  {  2447,  16,  21,  21,    2,  -20 },   // 0x6B 'k'\n  {  2489,  14,  21,  21,    4,  -20 },   // 0x6C 'l'\n  {  2526,  19,  15,  21,    1,  -14 },   // 0x6D 'm'\n  {  2562,  17,  15,  21,    1,  -14 },   // 0x6E 'n'\n  {  2594,  15,  15,  21,    3,  -14 },   // 0x6F 'o'\n  {  2623,  18,  22,  21,    1,  -14 },   // 0x70 'p'\n  {  2673,  18,  22,  21,    2,  -14 },   // 0x71 'q'\n  {  2723,  15,  15,  21,    3,  -14 },   // 0x72 'r'\n  {  2752,  13,  15,  21,    4,  -14 },   // 0x73 's'\n  {  2777,  16,  20,  21,    1,  -19 },   // 0x74 't'\n  {  2817,  17,  15,  21,    1,  -14 },   // 0x75 'u'\n  {  2849,  19,  15,  21,    1,  -14 },   // 0x76 'v'\n  {  2885,  19,  15,  21,    1,  -14 },   // 0x77 'w'\n  {  2921,  17,  15,  21,    2,  -14 },   // 0x78 'x'\n  {  2953,  17,  22,  21,    2,  -14 },   // 0x79 'y'\n  {  3000,  13,  15,  21,    4,  -14 },   // 0x7A 'z'\n  {  3025,   8,  25,  21,    6,  -20 },   // 0x7B '{'\n  {  3050,   1,  25,  21,   10,  -20 },   // 0x7C '|'\n  {  3054,   8,  25,  21,    7,  -20 },   // 0x7D '}'\n  {  3079,  15,   5,  21,    3,  -11 } }; // 0x7E '~'\n\nconst GFXfont FreeMono18pt7b PROGMEM = {\n  (uint8_t  *)FreeMono18pt7bBitmaps,\n  (GFXglyph *)FreeMono18pt7bGlyphs,\n  0x20, 0x7E, 35 };\n\n// Approx. 3761 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeMono24pt7b.h",
    "content": "const uint8_t FreeMono24pt7bBitmaps[] PROGMEM = {\n  0x73, 0x9C, 0xE7, 0x39, 0xCE, 0x73, 0x9C, 0xE7, 0x10, 0x84, 0x21, 0x08,\n  0x00, 0x00, 0x00, 0x03, 0xBF, 0xFF, 0xB8, 0xFE, 0x7F, 0x7C, 0x3E, 0x7C,\n  0x3E, 0x7C, 0x3E, 0x7C, 0x3E, 0x7C, 0x3E, 0x7C, 0x3E, 0x7C, 0x3E, 0x3C,\n  0x3E, 0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C, 0x01,\n  0x86, 0x00, 0x30, 0xC0, 0x06, 0x18, 0x00, 0xC3, 0x00, 0x18, 0x60, 0x03,\n  0x0C, 0x00, 0x61, 0x80, 0x0C, 0x70, 0x01, 0x8C, 0x00, 0x61, 0x80, 0x0C,\n  0x30, 0x3F, 0xFF, 0xF7, 0xFF, 0xFE, 0x06, 0x18, 0x00, 0xC3, 0x00, 0x18,\n  0x60, 0x03, 0x0C, 0x00, 0x61, 0x80, 0x0C, 0x30, 0x7F, 0xFF, 0xEF, 0xFF,\n  0xFC, 0x06, 0x18, 0x00, 0xC7, 0x00, 0x38, 0xC0, 0x06, 0x18, 0x00, 0xC3,\n  0x00, 0x18, 0x60, 0x03, 0x0C, 0x00, 0x61, 0x80, 0x0C, 0x30, 0x01, 0x86,\n  0x00, 0x30, 0xC0, 0x00, 0xC0, 0x00, 0x30, 0x00, 0x0C, 0x00, 0x0F, 0xC0,\n  0x0F, 0xFD, 0x87, 0x03, 0xE3, 0x80, 0x39, 0xC0, 0x06, 0x60, 0x01, 0x98,\n  0x00, 0x06, 0x00, 0x01, 0xC0, 0x00, 0x38, 0x00, 0x07, 0xC0, 0x00, 0x7F,\n  0x80, 0x03, 0xF8, 0x00, 0x0F, 0x80, 0x00, 0x60, 0x00, 0x1C, 0x00, 0x03,\n  0x80, 0x00, 0xF0, 0x00, 0x3C, 0x00, 0x1F, 0x80, 0x0E, 0xFC, 0x0F, 0x37,\n  0xFF, 0x80, 0x7F, 0x80, 0x03, 0x00, 0x00, 0xC0, 0x00, 0x30, 0x00, 0x0C,\n  0x00, 0x03, 0x00, 0x00, 0xC0, 0x00, 0x07, 0x80, 0x01, 0xFE, 0x00, 0x38,\n  0x70, 0x03, 0x03, 0x00, 0x60, 0x18, 0x06, 0x01, 0x80, 0x60, 0x18, 0x06,\n  0x01, 0x80, 0x30, 0x30, 0x03, 0x87, 0x00, 0x1F, 0xE0, 0x30, 0x78, 0x1F,\n  0x00, 0x1F, 0x80, 0x0F, 0xC0, 0x07, 0xE0, 0x03, 0xF0, 0x00, 0xF8, 0x00,\n  0x0C, 0x01, 0xE0, 0x00, 0x7F, 0x80, 0x0E, 0x1C, 0x00, 0xC0, 0xC0, 0x18,\n  0x06, 0x01, 0x80, 0x60, 0x18, 0x06, 0x01, 0x80, 0x60, 0x0C, 0x0E, 0x00,\n  0xE1, 0xC0, 0x07, 0xF8, 0x00, 0x1E, 0x00, 0x03, 0xEC, 0x01, 0xFF, 0x00,\n  0xE1, 0x00, 0x70, 0x00, 0x18, 0x00, 0x06, 0x00, 0x01, 0x80, 0x00, 0x30,\n  0x00, 0x0C, 0x00, 0x01, 0x80, 0x00, 0x60, 0x00, 0x7C, 0x00, 0x3B, 0x83,\n  0xD8, 0x60, 0xFE, 0x0C, 0x33, 0x03, 0x98, 0xC0, 0x66, 0x30, 0x0D, 0x8C,\n  0x03, 0xC3, 0x00, 0x70, 0x60, 0x1C, 0x1C, 0x0F, 0x03, 0x87, 0x7C, 0x7F,\n  0x9F, 0x07, 0x80, 0x00, 0xFE, 0xF9, 0xF3, 0xE7, 0xCF, 0x9F, 0x3E, 0x3C,\n  0x70, 0xE1, 0xC3, 0x87, 0x00, 0x06, 0x1C, 0x30, 0xE1, 0x87, 0x0E, 0x18,\n  0x70, 0xE1, 0xC3, 0x0E, 0x1C, 0x38, 0x70, 0xE1, 0xC3, 0x87, 0x0E, 0x0C,\n  0x1C, 0x38, 0x70, 0x60, 0xE1, 0xC1, 0x83, 0x83, 0x06, 0x06, 0x04, 0xC1,\n  0xC1, 0x83, 0x83, 0x07, 0x0E, 0x0C, 0x1C, 0x38, 0x70, 0xE0, 0xE1, 0xC3,\n  0x87, 0x0E, 0x1C, 0x38, 0x70, 0xE1, 0x87, 0x0E, 0x1C, 0x30, 0x61, 0xC3,\n  0x0E, 0x18, 0x70, 0xC1, 0x00, 0x00, 0xC0, 0x00, 0x30, 0x00, 0x0C, 0x00,\n  0x03, 0x00, 0x00, 0xC0, 0x10, 0x30, 0x3F, 0x8C, 0x7C, 0xFF, 0xFC, 0x07,\n  0xF8, 0x00, 0x78, 0x00, 0x1F, 0x00, 0x0C, 0xC0, 0x06, 0x18, 0x03, 0x87,\n  0x00, 0xC0, 0xC0, 0x60, 0x18, 0x00, 0x60, 0x00, 0x06, 0x00, 0x00, 0x60,\n  0x00, 0x06, 0x00, 0x00, 0x60, 0x00, 0x06, 0x00, 0x00, 0x60, 0x00, 0x06,\n  0x00, 0x00, 0x60, 0x00, 0x06, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,\n  0x60, 0x00, 0x06, 0x00, 0x00, 0x60, 0x00, 0x06, 0x00, 0x00, 0x60, 0x00,\n  0x06, 0x00, 0x00, 0x60, 0x00, 0x06, 0x00, 0x00, 0x60, 0x00, 0x06, 0x00,\n  0x1F, 0x8F, 0x87, 0xC7, 0xC3, 0xE1, 0xE1, 0xF0, 0xF0, 0x78, 0x38, 0x3C,\n  0x1C, 0x0E, 0x06, 0x00, 0x7F, 0xFF, 0xFD, 0xFF, 0xFF, 0xF0, 0x7D, 0xFF,\n  0xFF, 0xFF, 0xEF, 0x80, 0x00, 0x00, 0xC0, 0x00, 0x70, 0x00, 0x18, 0x00,\n  0x06, 0x00, 0x03, 0x00, 0x00, 0xC0, 0x00, 0x60, 0x00, 0x18, 0x00, 0x0C,\n  0x00, 0x03, 0x00, 0x01, 0x80, 0x00, 0x60, 0x00, 0x30, 0x00, 0x0C, 0x00,\n  0x06, 0x00, 0x01, 0x80, 0x00, 0xC0, 0x00, 0x30, 0x00, 0x18, 0x00, 0x06,\n  0x00, 0x03, 0x80, 0x00, 0xC0, 0x00, 0x70, 0x00, 0x18, 0x00, 0x0E, 0x00,\n  0x03, 0x00, 0x01, 0xC0, 0x00, 0x60, 0x00, 0x38, 0x00, 0x0C, 0x00, 0x07,\n  0x00, 0x01, 0x80, 0x00, 0x60, 0x00, 0x30, 0x00, 0x0C, 0x00, 0x00, 0x03,\n  0xF0, 0x03, 0xFF, 0x01, 0xE1, 0xE0, 0xE0, 0x18, 0x30, 0x03, 0x1C, 0x00,\n  0xE6, 0x00, 0x19, 0x80, 0x06, 0xE0, 0x01, 0xF0, 0x00, 0x3C, 0x00, 0x0F,\n  0x00, 0x03, 0xC0, 0x00, 0xF0, 0x00, 0x3C, 0x00, 0x0F, 0x00, 0x03, 0xC0,\n  0x00, 0xF0, 0x00, 0x3C, 0x00, 0x0F, 0x00, 0x03, 0xC0, 0x00, 0xF8, 0x00,\n  0x76, 0x00, 0x19, 0x80, 0x06, 0x70, 0x03, 0x8C, 0x00, 0xC3, 0x80, 0x60,\n  0x78, 0x78, 0x0F, 0xFC, 0x00, 0xFC, 0x00, 0x03, 0x80, 0x07, 0x80, 0x0F,\n  0x80, 0x1D, 0x80, 0x39, 0x80, 0x71, 0x80, 0xE1, 0x80, 0xC1, 0x80, 0x01,\n  0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01,\n  0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01,\n  0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01,\n  0x80, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0xF0, 0x03, 0xFF, 0x01, 0xC0, 0xE0,\n  0xC0, 0x1C, 0x60, 0x03, 0xB8, 0x00, 0x6C, 0x00, 0x0F, 0x00, 0x03, 0x00,\n  0x00, 0xC0, 0x00, 0x30, 0x00, 0x18, 0x00, 0x06, 0x00, 0x03, 0x00, 0x01,\n  0x80, 0x00, 0xC0, 0x00, 0x60, 0x00, 0x30, 0x00, 0x18, 0x00, 0x0C, 0x00,\n  0x06, 0x00, 0x03, 0x00, 0x01, 0x80, 0x00, 0xC0, 0x00, 0x60, 0x00, 0x30,\n  0x00, 0xD0, 0x00, 0x38, 0x00, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0x03,\n  0xF8, 0x01, 0xFF, 0xC0, 0x70, 0x3C, 0x18, 0x01, 0xC6, 0x00, 0x18, 0x00,\n  0x01, 0x80, 0x00, 0x30, 0x00, 0x06, 0x00, 0x00, 0xC0, 0x00, 0x18, 0x00,\n  0x06, 0x00, 0x01, 0xC0, 0x00, 0x70, 0x01, 0xFC, 0x00, 0x3F, 0x00, 0x00,\n  0x78, 0x00, 0x03, 0x80, 0x00, 0x38, 0x00, 0x03, 0x00, 0x00, 0x30, 0x00,\n  0x06, 0x00, 0x00, 0xC0, 0x00, 0x18, 0x00, 0x03, 0x00, 0x00, 0xD8, 0x00,\n  0x3B, 0x80, 0x0E, 0x3E, 0x07, 0x81, 0xFF, 0xE0, 0x07, 0xE0, 0x00, 0x00,\n  0x3C, 0x00, 0x7C, 0x00, 0x6C, 0x00, 0xCC, 0x00, 0x8C, 0x01, 0x8C, 0x03,\n  0x0C, 0x03, 0x0C, 0x06, 0x0C, 0x04, 0x0C, 0x0C, 0x0C, 0x08, 0x0C, 0x10,\n  0x0C, 0x30, 0x0C, 0x20, 0x0C, 0x60, 0x0C, 0x40, 0x0C, 0x80, 0x0C, 0xFF,\n  0xFF, 0xFF, 0xFF, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00,\n  0x0C, 0x00, 0x0C, 0x00, 0xFF, 0x00, 0xFF, 0x3F, 0xFF, 0x07, 0xFF, 0xE0,\n  0xC0, 0x00, 0x18, 0x00, 0x03, 0x00, 0x00, 0x60, 0x00, 0x0C, 0x00, 0x01,\n  0x80, 0x00, 0x30, 0x00, 0x06, 0x00, 0x00, 0xC7, 0xE0, 0x1F, 0xFF, 0x03,\n  0x80, 0x70, 0x00, 0x03, 0x00, 0x00, 0x30, 0x00, 0x06, 0x00, 0x00, 0x60,\n  0x00, 0x0C, 0x00, 0x01, 0x80, 0x00, 0x30, 0x00, 0x06, 0x00, 0x00, 0xC0,\n  0x00, 0x30, 0x00, 0x06, 0xC0, 0x01, 0xDC, 0x00, 0x71, 0xF0, 0x3C, 0x0F,\n  0xFF, 0x00, 0x3F, 0x00, 0x00, 0x3F, 0x80, 0x3F, 0xF0, 0x3E, 0x00, 0x1E,\n  0x00, 0x0E, 0x00, 0x07, 0x00, 0x03, 0x80, 0x00, 0xC0, 0x00, 0x70, 0x00,\n  0x18, 0x00, 0x06, 0x00, 0x03, 0x80, 0x00, 0xC1, 0xF8, 0x31, 0xFF, 0x0C,\n  0xF0, 0xF3, 0x70, 0x0C, 0xD8, 0x01, 0xBC, 0x00, 0x6E, 0x00, 0x0F, 0x80,\n  0x03, 0xC0, 0x00, 0xD8, 0x00, 0x36, 0x00, 0x0D, 0x80, 0x03, 0x30, 0x01,\n  0x8E, 0x00, 0x61, 0xC0, 0x30, 0x38, 0x38, 0x07, 0xFC, 0x00, 0x7C, 0x00,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0x00, 0x0F, 0x00, 0x03, 0xC0, 0x01, 0xC0,\n  0x00, 0x60, 0x00, 0x18, 0x00, 0x0E, 0x00, 0x03, 0x00, 0x00, 0xC0, 0x00,\n  0x30, 0x00, 0x18, 0x00, 0x06, 0x00, 0x01, 0x80, 0x00, 0xC0, 0x00, 0x30,\n  0x00, 0x0C, 0x00, 0x06, 0x00, 0x01, 0x80, 0x00, 0x60, 0x00, 0x30, 0x00,\n  0x0C, 0x00, 0x03, 0x00, 0x01, 0x80, 0x00, 0x60, 0x00, 0x18, 0x00, 0x0C,\n  0x00, 0x03, 0x00, 0x03, 0xF0, 0x03, 0xFF, 0x03, 0xC0, 0xF1, 0xC0, 0x0E,\n  0x60, 0x01, 0xB8, 0x00, 0x7C, 0x00, 0x0F, 0x00, 0x03, 0xC0, 0x00, 0xF0,\n  0x00, 0x36, 0x00, 0x18, 0xC0, 0x0C, 0x1C, 0x0E, 0x03, 0xFF, 0x00, 0xFF,\n  0xC0, 0x70, 0x38, 0x30, 0x03, 0x18, 0x00, 0x66, 0x00, 0x1B, 0x00, 0x03,\n  0xC0, 0x00, 0xF0, 0x00, 0x3C, 0x00, 0x0F, 0x00, 0x03, 0x60, 0x01, 0x98,\n  0x00, 0xE3, 0x00, 0x70, 0x70, 0x38, 0x0F, 0xFC, 0x00, 0xFC, 0x00, 0x07,\n  0xE0, 0x03, 0xFE, 0x01, 0xC1, 0xC0, 0xC0, 0x38, 0x60, 0x07, 0x18, 0x00,\n  0xCC, 0x00, 0x1B, 0x00, 0x06, 0xC0, 0x01, 0xB0, 0x00, 0x3C, 0x00, 0x1F,\n  0x00, 0x07, 0x60, 0x03, 0xD8, 0x01, 0xB3, 0x00, 0xCC, 0xF0, 0xF3, 0x0F,\n  0xF8, 0xC1, 0xF8, 0x30, 0x00, 0x1C, 0x00, 0x06, 0x00, 0x01, 0x80, 0x00,\n  0xE0, 0x00, 0x30, 0x00, 0x1C, 0x00, 0x0E, 0x00, 0x07, 0x00, 0x07, 0x80,\n  0x07, 0xC0, 0xFF, 0xC0, 0x1F, 0xC0, 0x00, 0x7D, 0xFF, 0xFF, 0xFF, 0xEF,\n  0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3E, 0xFF, 0xFF, 0xFF,\n  0xF7, 0xC0, 0x0F, 0x87, 0xF1, 0xFC, 0x7F, 0x1F, 0xC3, 0xE0, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0xF1, 0xF8, 0x7C, 0x3F, 0x0F,\n  0x83, 0xE0, 0xF0, 0x7C, 0x1E, 0x07, 0x81, 0xC0, 0xF0, 0x38, 0x04, 0x00,\n  0x00, 0x00, 0x18, 0x00, 0x01, 0xE0, 0x00, 0x1E, 0x00, 0x00, 0xE0, 0x00,\n  0x0F, 0x00, 0x00, 0xF0, 0x00, 0x0F, 0x00, 0x00, 0xF0, 0x00, 0x07, 0x00,\n  0x00, 0x78, 0x00, 0x07, 0x80, 0x00, 0x0F, 0x00, 0x00, 0x1E, 0x00, 0x00,\n  0x1E, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x1E, 0x00, 0x00,\n  0x3C, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x38, 0x00, 0x00,\n  0x20, 0x7F, 0xFF, 0xFF, 0x7F, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7F, 0xFF,\n  0xFF, 0x7F, 0xFF, 0xFF, 0xC0, 0x00, 0x07, 0x80, 0x00, 0x0F, 0x00, 0x00,\n  0x1E, 0x00, 0x00, 0x38, 0x00, 0x00, 0xF0, 0x00, 0x01, 0xE0, 0x00, 0x03,\n  0xC0, 0x00, 0x07, 0x80, 0x00, 0x0E, 0x00, 0x00, 0x3C, 0x00, 0x01, 0xE0,\n  0x00, 0x3C, 0x00, 0x07, 0x80, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x01, 0xE0,\n  0x00, 0x3C, 0x00, 0x07, 0x80, 0x00, 0xF0, 0x00, 0x0E, 0x00, 0x00, 0x60,\n  0x00, 0x00, 0x07, 0xF0, 0x1F, 0xFE, 0x3E, 0x07, 0x98, 0x00, 0xEC, 0x00,\n  0x36, 0x00, 0x0F, 0x00, 0x06, 0x00, 0x03, 0x00, 0x01, 0x80, 0x01, 0xC0,\n  0x00, 0xC0, 0x01, 0xC0, 0x03, 0xC0, 0x07, 0xC0, 0x07, 0x00, 0x03, 0x00,\n  0x01, 0x80, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x07, 0x80, 0x07, 0xE0, 0x03, 0xF0, 0x01, 0xF8, 0x00,\n  0x78, 0x00, 0x03, 0xF0, 0x03, 0xFF, 0x01, 0xE0, 0xE0, 0xE0, 0x1C, 0x30,\n  0x03, 0x1C, 0x00, 0x66, 0x00, 0x19, 0x80, 0x06, 0xC0, 0x01, 0xB0, 0x07,\n  0xEC, 0x07, 0xFB, 0x03, 0xC6, 0xC1, 0xC1, 0xB0, 0xE0, 0x6C, 0x30, 0x1B,\n  0x0C, 0x06, 0xC3, 0x01, 0xB0, 0xC0, 0x6C, 0x18, 0x1B, 0x07, 0x86, 0xC0,\n  0xFF, 0xF0, 0x0F, 0xFC, 0x00, 0x03, 0x00, 0x00, 0x60, 0x00, 0x18, 0x00,\n  0x07, 0x00, 0x00, 0xC0, 0x00, 0x38, 0x00, 0x07, 0x80, 0xC0, 0xFF, 0xF0,\n  0x0F, 0xE0, 0x07, 0xFF, 0x00, 0x00, 0x7F, 0xF0, 0x00, 0x00, 0x1B, 0x00,\n  0x00, 0x01, 0x98, 0x00, 0x00, 0x11, 0x80, 0x00, 0x03, 0x0C, 0x00, 0x00,\n  0x30, 0xC0, 0x00, 0x06, 0x0C, 0x00, 0x00, 0x60, 0x60, 0x00, 0x06, 0x06,\n  0x00, 0x00, 0xC0, 0x30, 0x00, 0x0C, 0x03, 0x00, 0x00, 0x80, 0x30, 0x00,\n  0x18, 0x01, 0x80, 0x01, 0x80, 0x18, 0x00, 0x3F, 0xFF, 0x80, 0x03, 0xFF,\n  0xFC, 0x00, 0x20, 0x00, 0xC0, 0x06, 0x00, 0x06, 0x00, 0x60, 0x00, 0x60,\n  0x0C, 0x00, 0x06, 0x00, 0xC0, 0x00, 0x30, 0x0C, 0x00, 0x03, 0x01, 0x80,\n  0x00, 0x18, 0x7F, 0xC0, 0x3F, 0xF7, 0xFC, 0x03, 0xFF, 0xFF, 0xFF, 0x03,\n  0xFF, 0xFF, 0x01, 0x80, 0x0E, 0x06, 0x00, 0x1C, 0x18, 0x00, 0x38, 0x60,\n  0x00, 0x61, 0x80, 0x01, 0x86, 0x00, 0x06, 0x18, 0x00, 0x38, 0x60, 0x01,\n  0xC1, 0x80, 0x1E, 0x07, 0xFF, 0xE0, 0x1F, 0xFF, 0xC0, 0x60, 0x03, 0xC1,\n  0x80, 0x03, 0x86, 0x00, 0x06, 0x18, 0x00, 0x1C, 0x60, 0x00, 0x31, 0x80,\n  0x00, 0xC6, 0x00, 0x03, 0x18, 0x00, 0x0C, 0x60, 0x00, 0x61, 0x80, 0x03,\n  0x86, 0x00, 0x1C, 0xFF, 0xFF, 0xE3, 0xFF, 0xFE, 0x00, 0x00, 0xFC, 0x00,\n  0x0F, 0xFE, 0x60, 0xF0, 0x3D, 0x87, 0x00, 0x3E, 0x38, 0x00, 0x38, 0xC0,\n  0x00, 0xE7, 0x00, 0x01, 0x98, 0x00, 0x06, 0x60, 0x00, 0x03, 0x00, 0x00,\n  0x0C, 0x00, 0x00, 0x30, 0x00, 0x00, 0xC0, 0x00, 0x03, 0x00, 0x00, 0x0C,\n  0x00, 0x00, 0x30, 0x00, 0x00, 0xC0, 0x00, 0x03, 0x00, 0x00, 0x0C, 0x00,\n  0x00, 0x18, 0x00, 0x00, 0x60, 0x00, 0x01, 0xC0, 0x00, 0x03, 0x80, 0x00,\n  0xC7, 0x00, 0x06, 0x0E, 0x00, 0x70, 0x1E, 0x07, 0x80, 0x3F, 0xFC, 0x00,\n  0x1F, 0x80, 0xFF, 0xFE, 0x03, 0xFF, 0xFE, 0x03, 0x00, 0x3C, 0x0C, 0x00,\n  0x38, 0x30, 0x00, 0x70, 0xC0, 0x00, 0xC3, 0x00, 0x03, 0x8C, 0x00, 0x06,\n  0x30, 0x00, 0x1C, 0xC0, 0x00, 0x33, 0x00, 0x00, 0xCC, 0x00, 0x03, 0x30,\n  0x00, 0x0C, 0xC0, 0x00, 0x33, 0x00, 0x00, 0xCC, 0x00, 0x03, 0x30, 0x00,\n  0x0C, 0xC0, 0x00, 0x33, 0x00, 0x01, 0x8C, 0x00, 0x06, 0x30, 0x00, 0x30,\n  0xC0, 0x01, 0xC3, 0x00, 0x0E, 0x0C, 0x00, 0xF0, 0xFF, 0xFF, 0x83, 0xFF,\n  0xF8, 0x00, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF, 0xE1, 0x80, 0x01, 0x86, 0x00,\n  0x06, 0x18, 0x00, 0x18, 0x60, 0x00, 0x61, 0x80, 0x01, 0x86, 0x00, 0x00,\n  0x18, 0x0C, 0x00, 0x60, 0x30, 0x01, 0x80, 0xC0, 0x07, 0xFF, 0x00, 0x1F,\n  0xFC, 0x00, 0x60, 0x30, 0x01, 0x80, 0xC0, 0x06, 0x03, 0x00, 0x18, 0x00,\n  0x00, 0x60, 0x00, 0x01, 0x80, 0x00, 0xC6, 0x00, 0x03, 0x18, 0x00, 0x0C,\n  0x60, 0x00, 0x31, 0x80, 0x00, 0xC6, 0x00, 0x03, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF1, 0x80, 0x00, 0xC6, 0x00,\n  0x03, 0x18, 0x00, 0x0C, 0x60, 0x00, 0x31, 0x80, 0x00, 0xC6, 0x00, 0x00,\n  0x18, 0x0C, 0x00, 0x60, 0x30, 0x01, 0x80, 0xC0, 0x07, 0xFF, 0x00, 0x1F,\n  0xFC, 0x00, 0x60, 0x30, 0x01, 0x80, 0xC0, 0x06, 0x03, 0x00, 0x18, 0x00,\n  0x00, 0x60, 0x00, 0x01, 0x80, 0x00, 0x06, 0x00, 0x00, 0x18, 0x00, 0x00,\n  0x60, 0x00, 0x01, 0x80, 0x00, 0x06, 0x00, 0x00, 0xFF, 0xF0, 0x03, 0xFF,\n  0xC0, 0x00, 0x00, 0xFF, 0x00, 0x07, 0xFF, 0x98, 0x1E, 0x03, 0xF0, 0x70,\n  0x01, 0xE1, 0x80, 0x01, 0xC6, 0x00, 0x01, 0x9C, 0x00, 0x03, 0x30, 0x00,\n  0x00, 0x60, 0x00, 0x01, 0xC0, 0x00, 0x03, 0x00, 0x00, 0x06, 0x00, 0x00,\n  0x0C, 0x00, 0x00, 0x18, 0x00, 0x00, 0x30, 0x00, 0x00, 0x60, 0x03, 0xFF,\n  0xC0, 0x07, 0xFF, 0x80, 0x00, 0x1B, 0x00, 0x00, 0x37, 0x00, 0x00, 0x66,\n  0x00, 0x00, 0xCC, 0x00, 0x01, 0x8C, 0x00, 0x03, 0x1C, 0x00, 0x06, 0x1E,\n  0x00, 0x0C, 0x0F, 0x00, 0xF8, 0x0F, 0xFF, 0xC0, 0x03, 0xFC, 0x00, 0x7F,\n  0x01, 0xFC, 0xFE, 0x03, 0xF8, 0x60, 0x00, 0xC0, 0xC0, 0x01, 0x81, 0x80,\n  0x03, 0x03, 0x00, 0x06, 0x06, 0x00, 0x0C, 0x0C, 0x00, 0x18, 0x18, 0x00,\n  0x30, 0x30, 0x00, 0x60, 0x60, 0x00, 0xC0, 0xFF, 0xFF, 0x81, 0xFF, 0xFF,\n  0x03, 0x00, 0x06, 0x06, 0x00, 0x0C, 0x0C, 0x00, 0x18, 0x18, 0x00, 0x30,\n  0x30, 0x00, 0x60, 0x60, 0x00, 0xC0, 0xC0, 0x01, 0x81, 0x80, 0x03, 0x03,\n  0x00, 0x06, 0x06, 0x00, 0x0C, 0x0C, 0x00, 0x18, 0xFF, 0x01, 0xFF, 0xFE,\n  0x03, 0xFC, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80,\n  0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80,\n  0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 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 0x18, 0x00, 0x60, 0x18, 0x00, 0x60, 0x18, 0x00, 0x70, 0x18, 0x00, 0x30,\n  0xFF, 0x80, 0x3F, 0xFF, 0x80, 0x1F, 0xFF, 0xF0, 0x07, 0xFF, 0x80, 0x01,\n  0x80, 0x00, 0x0C, 0x00, 0x00, 0x60, 0x00, 0x03, 0x00, 0x00, 0x18, 0x00,\n  0x00, 0xC0, 0x00, 0x06, 0x00, 0x00, 0x30, 0x00, 0x01, 0x80, 0x00, 0x0C,\n  0x00, 0x00, 0x60, 0x00, 0x03, 0x00, 0x00, 0x18, 0x00, 0x00, 0xC0, 0x00,\n  0x06, 0x00, 0x18, 0x30, 0x00, 0xC1, 0x80, 0x06, 0x0C, 0x00, 0x30, 0x60,\n  0x01, 0x83, 0x00, 0x0C, 0x18, 0x00, 0x60, 0xC0, 0x03, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xC0, 0xFC, 0x00, 0x0F, 0xFF, 0x00, 0x03, 0xF3, 0x60, 0x01,\n  0xB0, 0xD8, 0x00, 0x6C, 0x33, 0x00, 0x33, 0x0C, 0xC0, 0x0C, 0xC3, 0x38,\n  0x07, 0x30, 0xC6, 0x01, 0x8C, 0x31, 0xC0, 0xE3, 0x0C, 0x30, 0x30, 0xC3,\n  0x0C, 0x0C, 0x30, 0xC1, 0x86, 0x0C, 0x30, 0x61, 0x83, 0x0C, 0x0C, 0xC0,\n  0xC3, 0x03, 0x30, 0x30, 0xC0, 0x78, 0x0C, 0x30, 0x1E, 0x03, 0x0C, 0x03,\n  0x00, 0xC3, 0x00, 0x00, 0x30, 0xC0, 0x00, 0x0C, 0x30, 0x00, 0x03, 0x0C,\n  0x00, 0x00, 0xC3, 0x00, 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0xF7, 0xFC, 0x03, 0xFF,\n  0x18, 0x00, 0x01, 0x80, 0xC0, 0x00, 0x30, 0x0C, 0x00, 0x03, 0x00, 0x60,\n  0x00, 0x30, 0x06, 0x00, 0x06, 0x00, 0x60, 0x00, 0x60, 0x03, 0x00, 0x0C,\n  0x00, 0x30, 0x00, 0xC0, 0x03, 0x80, 0x0C, 0x00, 0x18, 0x01, 0x80, 0x01,\n  0x80, 0x18, 0x00, 0x0C, 0x03, 0x00, 0x00, 0xC0, 0x30, 0x00, 0x0E, 0x03,\n  0x00, 0x00, 0x60, 0x60, 0x00, 0x06, 0x06, 0x00, 0x00, 0x30, 0xC0, 0x00,\n  0x03, 0x0C, 0x00, 0x00, 0x30, 0x80, 0x00, 0x01, 0x98, 0x00, 0x00, 0x19,\n  0x80, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0xE0, 0x00,\n  0xFF, 0x80, 0x7F, 0xFF, 0xE0, 0x1F, 0xF3, 0x00, 0x00, 0x30, 0xC0, 0x00,\n  0x0C, 0x30, 0x00, 0x03, 0x0C, 0x03, 0x80, 0xC3, 0x01, 0xE0, 0x30, 0x60,\n  0x78, 0x0C, 0x18, 0x1F, 0x02, 0x06, 0x04, 0xC0, 0x81, 0x83, 0x30, 0x60,\n  0x60, 0xCC, 0x18, 0x18, 0x31, 0x86, 0x06, 0x18, 0x61, 0x81, 0x86, 0x18,\n  0x60, 0x71, 0x87, 0x18, 0x0C, 0x40, 0xC6, 0x03, 0x30, 0x31, 0x00, 0xCC,\n  0x0C, 0xC0, 0x33, 0x01, 0xB0, 0x0D, 0x80, 0x6C, 0x03, 0x60, 0x1B, 0x00,\n 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 0x00, 0x60, 0x60, 0x00, 0xC0, 0xC0, 0x01, 0x81, 0x80, 0x03, 0x03, 0x00,\n  0x06, 0x06, 0x00, 0x0C, 0x0C, 0x00, 0x18, 0x18, 0x00, 0x30, 0x30, 0x00,\n  0x63, 0xFC, 0x07, 0xFF, 0xF8, 0x0F, 0xF0, 0x01, 0xC0, 0x00, 0x70, 0x00,\n  0x1C, 0x00, 0x07, 0x00, 0x01, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x0F, 0xF0, 0x03, 0xFC, 0x00, 0x03, 0x00, 0x00, 0xC0,\n  0x00, 0x30, 0x00, 0x0C, 0x00, 0x03, 0x00, 0x00, 0xC0, 0x00, 0x30, 0x00,\n  0x0C, 0x00, 0x03, 0x00, 0x00, 0xC0, 0x00, 0x30, 0x00, 0x0C, 0x00, 0x03,\n  0x00, 0x00, 0xC0, 0x00, 0x30, 0x00, 0x0C, 0x03, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xC0, 0x00, 0x70, 0x01, 0xC0, 0x07, 0x00, 0x1C, 0x00, 0x70, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0x03, 0xFF, 0xFF, 0xFF, 0xC0, 0x03, 0x00, 0x0C,\n  0x00, 0x30, 0x00, 0xC0, 0x03, 0x00, 0x0C, 0x00, 0x30, 0x00, 0xC0, 0x03,\n  0x00, 0x0C, 0x00, 0x30, 0x00, 0xC0, 0x03, 0x00, 0x0C, 0x00, 0x30, 0x00,\n  0xC0, 0x03, 0x00, 0x0C, 0x00, 0x30, 0x00, 0xC0, 0x03, 0x00, 0x0C, 0x00,\n  0x70, 0x03, 0x80, 0x1C, 0xFF, 0xE3, 0xFF, 0x00, 0xF8, 0x00, 0x03, 0xE0,\n  0x00, 0x01, 0x80, 0x00, 0x06, 0x00, 0x00, 0x18, 0x00, 0x00, 0x60, 0x00,\n  0x01, 0x80, 0x00, 0x06, 0x00, 0x00, 0x18, 0x1F, 0xE0, 0x60, 0x7F, 0x81,\n  0x80, 0x60, 0x06, 0x07, 0x00, 0x18, 0x38, 0x00, 0x61, 0xC0, 0x01, 0x8E,\n  0x00, 0x06, 0x70, 0x00, 0x1B, 0x80, 0x00, 0x7F, 0x00, 0x01, 0xCE, 0x00,\n  0x06, 0x1C, 0x00, 0x18, 0x38, 0x00, 0x60, 0x70, 0x01, 0x80, 0xE0, 0x06,\n  0x01, 0xC0, 0x18, 0x03, 0x80, 0x60, 0x07, 0x0F, 0x80, 0x7F, 0xFE, 0x01,\n  0xFF, 0x3F, 0xC0, 0x0F, 0xF0, 0x00, 0x0C, 0x00, 0x03, 0x00, 0x00, 0xC0,\n  0x00, 0x30, 0x00, 0x0C, 0x00, 0x03, 0x00, 0x00, 0xC0, 0x00, 0x30, 0x00,\n  0x0C, 0x00, 0x03, 0x00, 0x00, 0xC0, 0x00, 0x30, 0x00, 0x0C, 0x00, 0x03,\n  0x00, 0x00, 0xC0, 0x00, 0x30, 0x00, 0x0C, 0x00, 0x03, 0x00, 0x00, 0xC0,\n  0x00, 0x30, 0x00, 0x0C, 0x00, 0x03, 0x00, 0x00, 0xC0, 0x00, 0x30, 0x0F,\n  0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0xF0, 0x3C, 0x0F, 0x9F, 0x87, 0xE0, 0xFB,\n  0x1C, 0xC7, 0x01, 0xE0, 0xD8, 0x38, 0x1C, 0x07, 0x01, 0x81, 0x80, 0x60,\n  0x18, 0x18, 0x06, 0x01, 0x81, 0x80, 0x60, 0x18, 0x18, 0x06, 0x01, 0x81,\n  0x80, 0x60, 0x18, 0x18, 0x06, 0x01, 0x81, 0x80, 0x60, 0x18, 0x18, 0x06,\n  0x01, 0x81, 0x80, 0x60, 0x18, 0x18, 0x06, 0x01, 0x81, 0x80, 0x60, 0x18,\n  0x18, 0x06, 0x01, 0x81, 0x80, 0x60, 0x18, 0x18, 0x06, 0x01, 0x8F, 0xE0,\n  0x7C, 0x1F, 0xFE, 0x07, 0xC1, 0xF0, 0x00, 0x1F, 0x00, 0xF8, 0xFF, 0x81,\n  0xF3, 0x83, 0x80, 0x6C, 0x03, 0x80, 0xF0, 0x03, 0x81, 0xC0, 0x03, 0x03,\n  0x00, 0x06, 0x06, 0x00, 0x0C, 0x0C, 0x00, 0x18, 0x18, 0x00, 0x30, 0x30,\n  0x00, 0x60, 0x60, 0x00, 0xC0, 0xC0, 0x01, 0x81, 0x80, 0x03, 0x03, 0x00,\n  0x06, 0x06, 0x00, 0x0C, 0x0C, 0x00, 0x18, 0x18, 0x00, 0x30, 0x30, 0x00,\n  0x67, 0xFC, 0x03, 0xFF, 0xF8, 0x07, 0xE0, 0x00, 0xFC, 0x00, 0x1F, 0xFE,\n  0x00, 0xF0, 0x3C, 0x07, 0x00, 0x38, 0x38, 0x00, 0x71, 0xC0, 0x00, 0xE6,\n  0x00, 0x01, 0x98, 0x00, 0x06, 0xC0, 0x00, 0x0F, 0x00, 0x00, 0x3C, 0x00,\n  0x00, 0xF0, 0x00, 0x03, 0xC0, 0x00, 0x0F, 0x00, 0x00, 0x36, 0x00, 0x01,\n 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0xD8, 0x0F, 0x07, 0x98, 0x07, 0xFF, 0x18, 0x01,\n  0xFC, 0x18, 0x00, 0x00, 0x18, 0x00, 0x00, 0x18, 0x00, 0x00, 0x18, 0x00,\n  0x00, 0x18, 0x00, 0x00, 0x18, 0x00, 0x00, 0x18, 0x00, 0x00, 0x18, 0x00,\n  0x03, 0xFF, 0x00, 0x03, 0xFF, 0x7E, 0x03, 0xC3, 0xF0, 0x7F, 0x81, 0x8F,\n  0x0E, 0x0C, 0xE0, 0x00, 0x7E, 0x00, 0x03, 0xC0, 0x00, 0x1C, 0x00, 0x00,\n  0xC0, 0x00, 0x06, 0x00, 0x00, 0x30, 0x00, 0x01, 0x80, 0x00, 0x0C, 0x00,\n  0x00, 0x60, 0x00, 0x03, 0x00, 0x00, 0x18, 0x00, 0x00, 0xC0, 0x00, 0x06,\n  0x00, 0x00, 0x30, 0x00, 0x3F, 0xFF, 0xC1, 0xFF, 0xFE, 0x00, 0x07, 0xF0,\n  0x07, 0xFF, 0x63, 0xC0, 0xF9, 0xC0, 0x0E, 0x60, 0x01, 0x98, 0x00, 0x66,\n  0x00, 0x19, 0xC0, 0x00, 0x38, 0x00, 0x07, 0xC0, 0x00, 0x7F, 0xC0, 0x00,\n  0x7C, 0x00, 0x03, 0x80, 0x00, 0x70, 0x00, 0x0F, 0x00, 0x03, 0xC0, 0x00,\n  0xF8, 0x00, 0x7F, 0x00, 0x3B, 0xF0, 0x3C, 0xDF, 0xFE, 0x00, 0xFE, 0x00,\n  0x0C, 0x00, 0x00, 0x60, 0x00, 0x03, 0x00, 0x00, 0x18, 0x00, 0x00, 0xC0,\n  0x00, 0x06, 0x00, 0x03, 0xFF, 0xFE, 0x1F, 0xFF, 0xF0, 0x0C, 0x00, 0x00,\n  0x60, 0x00, 0x03, 0x00, 0x00, 0x18, 0x00, 0x00, 0xC0, 0x00, 0x06, 0x00,\n  0x00, 0x30, 0x00, 0x01, 0x80, 0x00, 0x0C, 0x00, 0x00, 0x60, 0x00, 0x03,\n  0x00, 0x00, 0x18, 0x00, 0x00, 0xC0, 0x00, 0x06, 0x00, 0x00, 0x30, 0x00,\n  0x00, 0xC0, 0x07, 0x07, 0x01, 0xF0, 0x1F, 0xFF, 0x00, 0x3F, 0x80, 0xF8,\n  0x03, 0xF1, 0xF0, 0x07, 0xE0, 0x60, 0x00, 0xC0, 0xC0, 0x01, 0x81, 0x80,\n  0x03, 0x03, 0x00, 0x06, 0x06, 0x00, 0x0C, 0x0C, 0x00, 0x18, 0x18, 0x00,\n  0x30, 0x30, 0x00, 0x60, 0x60, 0x00, 0xC0, 0xC0, 0x01, 0x81, 0x80, 0x03,\n  0x03, 0x00, 0x06, 0x06, 0x00, 0x0C, 0x0C, 0x00, 0x38, 0x18, 0x00, 0xF0,\n  0x18, 0x03, 0x60, 0x38, 0x3C, 0xF8, 0x3F, 0xF1, 0xF0, 0x1F, 0x00, 0x00,\n  0x7F, 0xC0, 0xFF, 0xDF, 0xF0, 0x3F, 0xF0, 0xC0, 0x00, 0xC0, 0x30, 0x00,\n  0x30, 0x06, 0x00, 0x1C, 0x01, 0x80, 0x06, 0x00, 0x30, 0x01, 0x80, 0x0C,\n  0x00, 0xC0, 0x03, 0x80, 0x30, 0x00, 0x60, 0x18, 0x00, 0x18, 0x06, 0x00,\n  0x03, 0x03, 0x00, 0x00, 0xC0, 0xC0, 0x00, 0x18, 0x30, 0x00, 0x06, 0x18,\n  0x00, 0x00, 0xC6, 0x00, 0x00, 0x33, 0x00, 0x00, 0x0E, 0xC0, 0x00, 0x01,\n  0xE0, 0x00, 0x00, 0x78, 0x00, 0x7F, 0x00, 0x3F, 0xDF, 0xC0, 0x0F, 0xF1,\n  0x80, 0x00, 0x20, 0x60, 0x00, 0x18, 0x18, 0x00, 0x06, 0x06, 0x03, 0x01,\n  0x80, 0x81, 0xE0, 0x60, 0x30, 0x78, 0x10, 0x0C, 0x1E, 0x0C, 0x03, 0x0C,\n  0xC3, 0x00, 0xC3, 0x30, 0xC0, 0x10, 0xCC, 0x30, 0x06, 0x61, 0x98, 0x01,\n  0x98, 0x66, 0x00, 0x66, 0x19, 0x80, 0x0B, 0x03, 0x60, 0x03, 0xC0, 0xD0,\n  0x00, 0xF0, 0x1C, 0x00, 0x38, 0x07, 0x00, 0x0E, 0x01, 0xC0, 0x3F, 0x81,\n  0xFE, 0x3F, 0x81, 0xFE, 0x0C, 0x00, 0x38, 0x06, 0x00, 0x70, 0x03, 0x00,\n  0xE0, 0x01, 0x81, 0xC0, 0x00, 0xC3, 0x80, 0x00, 0x67, 0x00, 0x00, 0x3C,\n  0x00, 0x00, 0x18, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x67, 0x00, 0x00, 0xC3,\n  0x80, 0x01, 0x81, 0xC0, 0x03, 0x00, 0xE0, 0x06, 0x00, 0x70, 0x0C, 0x00,\n  0x38, 0x18, 0x00, 0x1C, 0x7F, 0x81, 0xFF, 0x7F, 0x81, 0xFF, 0x7F, 0x00,\n  0xFF, 0x7F, 0x00, 0xFF, 0x18, 0x00, 0x0C, 0x18, 0x00, 0x18, 0x0C, 0x00,\n  0x18, 0x0C, 0x00, 0x30, 0x06, 0x00, 0x30, 0x06, 0x00, 0x60, 0x03, 0x00,\n  0x60, 0x03, 0x00, 0xC0, 0x01, 0x80, 0xC0, 0x01, 0x81, 0x80, 0x00, 0xC1,\n  0x80, 0x00, 0xC3, 0x00, 0x00, 0x63, 0x00, 0x00, 0x66, 0x00, 0x00, 0x36,\n  0x00, 0x00, 0x34, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x18, 0x00, 0x00, 0x18,\n  0x00, 0x00, 0x18, 0x00, 0x00, 0x30, 0x00, 0x00, 0x30, 0x00, 0x00, 0x60,\n  0x00, 0x00, 0x60, 0x00, 0x00, 0xC0, 0x00, 0x7F, 0xFC, 0x00, 0x7F, 0xFC,\n  0x00, 0xFF, 0xFF, 0x7F, 0xFF, 0xB0, 0x01, 0x98, 0x01, 0xCC, 0x01, 0xC0,\n  0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xE0,\n  0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x03, 0x70,\n  0x01, 0xB0, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0x00, 0xE0, 0x7C, 0x0C,\n  0x03, 0x00, 0x60, 0x0C, 0x01, 0x80, 0x30, 0x06, 0x00, 0xC0, 0x18, 0x03,\n  0x00, 0x60, 0x0C, 0x03, 0x00, 0xE0, 0xF0, 0x1E, 0x00, 0x70, 0x06, 0x00,\n  0x60, 0x0C, 0x01, 0x80, 0x30, 0x06, 0x00, 0xC0, 0x18, 0x03, 0x00, 0x60,\n  0x0C, 0x01, 0x80, 0x18, 0x03, 0xE0, 0x1C, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xF0, 0xE0, 0x1F, 0x00, 0x60, 0x06, 0x00, 0xC0, 0x18,\n  0x03, 0x00, 0x60, 0x0C, 0x01, 0x80, 0x30, 0x06, 0x00, 0xC0, 0x18, 0x01,\n  0x80, 0x38, 0x01, 0xE0, 0x3C, 0x1C, 0x03, 0x00, 0xC0, 0x18, 0x03, 0x00,\n  0x60, 0x0C, 0x01, 0x80, 0x30, 0x06, 0x00, 0xC0, 0x18, 0x03, 0x00, 0xC0,\n  0xF8, 0x1C, 0x00, 0x0F, 0x00, 0x03, 0xFC, 0x03, 0x70, 0xE0, 0x76, 0x07,\n  0x8E, 0xC0, 0x1F, 0xC0, 0x00, 0xF0 };\n\nconst GFXglyph FreeMono24pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,  28,    0,    1 },   // 0x20 ' '\n  {     0,   5,  30,  28,   11,  -28 },   // 0x21 '!'\n  {    19,  16,  14,  28,    6,  -28 },   // 0x22 '\"'\n  {    47,  19,  32,  28,    4,  -29 },   // 0x23 '#'\n  {   123,  18,  33,  28,    5,  -29 },   // 0x24 '$'\n  {   198,  20,  29,  28,    4,  -27 },   // 0x25 '%'\n  {   271,  18,  25,  28,    5,  -23 },   // 0x26 '&'\n  {   328,   7,  14,  28,   11,  -28 },   // 0x27 '''\n  {   341,   7,  34,  28,   14,  -27 },   // 0x28 '('\n  {   371,   7,  34,  28,    8,  -27 },   // 0x29 ')'\n  {   401,  18,  16,  28,    5,  -27 },   // 0x2A '*'\n  {   437,  20,  22,  28,    4,  -23 },   // 0x2B '+'\n  {   492,   9,  14,  28,    6,   -6 },   // 0x2C ','\n  {   508,  22,   2,  28,    3,  -13 },   // 0x2D '-'\n  {   514,   7,   6,  28,   11,   -4 },   // 0x2E '.'\n  {   520,  18,  35,  28,    5,  -30 },   // 0x2F '/'\n  {   599,  18,  30,  28,    5,  -28 },   // 0x30 '0'\n  {   667,  16,  29,  28,    6,  -28 },   // 0x31 '1'\n  {   725,  18,  29,  28,    5,  -28 },   // 0x32 '2'\n  {   791,  19,  30,  28,    5,  -28 },   // 0x33 '3'\n  {   863,  16,  28,  28,    6,  -27 },   // 0x34 '4'\n  {   919,  19,  29,  28,    5,  -27 },   // 0x35 '5'\n  {   988,  18,  30,  28,    6,  -28 },   // 0x36 '6'\n  {  1056,  18,  28,  28,    5,  -27 },   // 0x37 '7'\n  {  1119,  18,  30,  28,    5,  -28 },   // 0x38 '8'\n  {  1187,  18,  30,  28,    6,  -28 },   // 0x39 '9'\n  {  1255,   7,  21,  28,   11,  -19 },   // 0x3A ':'\n  {  1274,  10,  27,  28,    7,  -19 },   // 0x3B ';'\n  {  1308,  22,  22,  28,    3,  -23 },   // 0x3C '<'\n  {  1369,  24,   9,  28,    2,  -17 },   // 0x3D '='\n  {  1396,  21,  22,  28,    4,  -23 },   // 0x3E '>'\n  {  1454,  17,  28,  28,    6,  -26 },   // 0x3F '?'\n  {  1514,  18,  32,  28,    5,  -28 },   // 0x40 '@'\n  {  1586,  28,  26,  28,    0,  -25 },   // 0x41 'A'\n  {  1677,  22,  26,  28,    3,  -25 },   // 0x42 'B'\n  {  1749,  22,  28,  28,    3,  -26 },   // 0x43 'C'\n  {  1826,  22,  26,  28,    3,  -25 },   // 0x44 'D'\n  {  1898,  22,  26,  28,    3,  -25 },   // 0x45 'E'\n  {  1970,  22,  26,  28,    3,  -25 },   // 0x46 'F'\n  {  2042,  23,  28,  28,    3,  -26 },   // 0x47 'G'\n  {  2123,  23,  26,  28,    3,  -25 },   // 0x48 'H'\n  {  2198,  16,  26,  28,    6,  -25 },   // 0x49 'I'\n  {  2250,  23,  27,  28,    4,  -25 },   // 0x4A 'J'\n  {  2328,  24,  26,  28,    3,  -25 },   // 0x4B 'K'\n  {  2406,  21,  26,  28,    4,  -25 },   // 0x4C 'L'\n  {  2475,  26,  26,  28,    1,  -25 },   // 0x4D 'M'\n  {  2560,  24,  26,  28,    2,  -25 },   // 0x4E 'N'\n  {  2638,  24,  28,  28,    2,  -26 },   // 0x4F 'O'\n  {  2722,  21,  26,  28,    3,  -25 },   // 0x50 'P'\n  {  2791,  24,  32,  28,    2,  -26 },   // 0x51 'Q'\n  {  2887,  24,  26,  28,    3,  -25 },   // 0x52 'R'\n  {  2965,  20,  28,  28,    4,  -26 },   // 0x53 'S'\n  {  3035,  22,  26,  28,    3,  -25 },   // 0x54 'T'\n  {  3107,  23,  27,  28,    3,  -25 },   // 0x55 'U'\n  {  3185,  28,  26,  28,    0,  -25 },   // 0x56 'V'\n  {  3276,  26,  26,  28,    1,  -25 },   // 0x57 'W'\n  {  3361,  24,  26,  28,    2,  -25 },   // 0x58 'X'\n  {  3439,  24,  26,  28,    2,  -25 },   // 0x59 'Y'\n  {  3517,  18,  26,  28,    5,  -25 },   // 0x5A 'Z'\n  {  3576,   7,  34,  28,   13,  -27 },   // 0x5B '['\n  {  3606,  18,  35,  28,    5,  -30 },   // 0x5C '\\'\n  {  3685,   7,  34,  28,    8,  -27 },   // 0x5D ']'\n  {  3715,  18,  12,  28,    5,  -28 },   // 0x5E '^'\n  {  3742,  28,   2,  28,    0,    5 },   // 0x5F '_'\n  {  3749,   8,   7,  28,    7,  -29 },   // 0x60 '`'\n  {  3756,  22,  22,  28,    3,  -20 },   // 0x61 'a'\n  {  3817,  23,  29,  28,    2,  -27 },   // 0x62 'b'\n  {  3901,  21,  22,  28,    4,  -20 },   // 0x63 'c'\n  {  3959,  24,  29,  28,    3,  -27 },   // 0x64 'd'\n  {  4046,  21,  22,  28,    3,  -20 },   // 0x65 'e'\n  {  4104,  19,  28,  28,    6,  -27 },   // 0x66 'f'\n  {  4171,  23,  30,  28,    3,  -20 },   // 0x67 'g'\n  {  4258,  23,  28,  28,    3,  -27 },   // 0x68 'h'\n  {  4339,  18,  29,  28,    5,  -28 },   // 0x69 'i'\n  {  4405,  14,  38,  28,    6,  -28 },   // 0x6A 'j'\n  {  4472,  22,  28,  28,    4,  -27 },   // 0x6B 'k'\n  {  4549,  18,  28,  28,    5,  -27 },   // 0x6C 'l'\n  {  4612,  28,  21,  28,    0,  -20 },   // 0x6D 'm'\n  {  4686,  23,  21,  28,    2,  -20 },   // 0x6E 'n'\n  {  4747,  22,  22,  28,    3,  -20 },   // 0x6F 'o'\n  {  4808,  23,  30,  28,    2,  -20 },   // 0x70 'p'\n  {  4895,  24,  30,  28,    3,  -20 },   // 0x71 'q'\n  {  4985,  21,  20,  28,    5,  -19 },   // 0x72 'r'\n  {  5038,  18,  22,  28,    5,  -20 },   // 0x73 's'\n  {  5088,  21,  27,  28,    3,  -25 },   // 0x74 't'\n  {  5159,  23,  21,  28,    3,  -19 },   // 0x75 'u'\n  {  5220,  26,  20,  28,    1,  -19 },   // 0x76 'v'\n  {  5285,  26,  20,  28,    1,  -19 },   // 0x77 'w'\n  {  5350,  24,  20,  28,    2,  -19 },   // 0x78 'x'\n  {  5410,  24,  29,  28,    2,  -19 },   // 0x79 'y'\n  {  5497,  17,  20,  28,    6,  -19 },   // 0x7A 'z'\n  {  5540,  11,  34,  28,    8,  -27 },   // 0x7B '{'\n  {  5587,   2,  34,  28,   13,  -27 },   // 0x7C '|'\n  {  5596,  11,  34,  28,    9,  -27 },   // 0x7D '}'\n  {  5643,  20,   6,  28,    4,  -15 } }; // 0x7E '~'\n\nconst GFXfont FreeMono24pt7b PROGMEM = {\n  (uint8_t  *)FreeMono24pt7bBitmaps,\n  (GFXglyph *)FreeMono24pt7bGlyphs,\n  0x20, 0x7E, 47 };\n\n// Approx. 6330 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeMono9pt7b.h",
    "content": "const uint8_t FreeMono9pt7bBitmaps[] PROGMEM = {\n  0xAA, 0xA8, 0x0C, 0xED, 0x24, 0x92, 0x48, 0x24, 0x48, 0x91, 0x2F, 0xE4,\n  0x89, 0x7F, 0x28, 0x51, 0x22, 0x40, 0x08, 0x3E, 0x62, 0x40, 0x30, 0x0E,\n  0x01, 0x81, 0xC3, 0xBE, 0x08, 0x08, 0x71, 0x12, 0x23, 0x80, 0x23, 0xB8,\n  0x0E, 0x22, 0x44, 0x70, 0x38, 0x81, 0x02, 0x06, 0x1A, 0x65, 0x46, 0xC8,\n  0xEC, 0xE9, 0x24, 0x5A, 0xAA, 0xA9, 0x40, 0xA9, 0x55, 0x5A, 0x80, 0x10,\n  0x22, 0x4B, 0xE3, 0x05, 0x11, 0x00, 0x10, 0x20, 0x47, 0xF1, 0x02, 0x04,\n  0x00, 0x6B, 0x48, 0xFF, 0x00, 0xF0, 0x02, 0x08, 0x10, 0x60, 0x81, 0x04,\n  0x08, 0x20, 0x41, 0x02, 0x08, 0x00, 0x38, 0x8A, 0x0C, 0x18, 0x30, 0x60,\n  0xC1, 0x82, 0x88, 0xE0, 0x27, 0x28, 0x42, 0x10, 0x84, 0x21, 0x3E, 0x38,\n  0x8A, 0x08, 0x10, 0x20, 0x82, 0x08, 0x61, 0x03, 0xF8, 0x7C, 0x06, 0x02,\n  0x02, 0x1C, 0x06, 0x01, 0x01, 0x01, 0x42, 0x3C, 0x18, 0xA2, 0x92, 0x8A,\n  0x28, 0xBF, 0x08, 0x21, 0xC0, 0x7C, 0x81, 0x03, 0xE4, 0x40, 0x40, 0x81,\n  0x03, 0x88, 0xE0, 0x1E, 0x41, 0x04, 0x0B, 0x98, 0xB0, 0xC1, 0xC2, 0x88,\n  0xE0, 0xFE, 0x04, 0x08, 0x20, 0x40, 0x82, 0x04, 0x08, 0x20, 0x40, 0x38,\n  0x8A, 0x0C, 0x14, 0x47, 0x11, 0x41, 0x83, 0x8C, 0xE0, 0x38, 0x8A, 0x1C,\n  0x18, 0x68, 0xCE, 0x81, 0x04, 0x13, 0xC0, 0xF0, 0x0F, 0x6C, 0x00, 0xD2,\n  0xD2, 0x00, 0x03, 0x04, 0x18, 0x60, 0x60, 0x18, 0x04, 0x03, 0xFF, 0x80,\n  0x00, 0x1F, 0xF0, 0x40, 0x18, 0x03, 0x00, 0x60, 0x20, 0x60, 0xC0, 0x80,\n  0x3D, 0x84, 0x08, 0x30, 0xC2, 0x00, 0x00, 0x00, 0x30, 0x3C, 0x46, 0x82,\n  0x8E, 0xB2, 0xA2, 0xA2, 0x9F, 0x80, 0x80, 0x40, 0x3C, 0x3C, 0x01, 0x40,\n  0x28, 0x09, 0x01, 0x10, 0x42, 0x0F, 0xC1, 0x04, 0x40, 0x9E, 0x3C, 0xFE,\n  0x21, 0x90, 0x48, 0x67, 0xE2, 0x09, 0x02, 0x81, 0x41, 0xFF, 0x80, 0x3E,\n  0xB0, 0xF0, 0x30, 0x08, 0x04, 0x02, 0x00, 0x80, 0x60, 0x8F, 0x80, 0xFE,\n  0x21, 0x90, 0x68, 0x14, 0x0A, 0x05, 0x02, 0x83, 0x43, 0x7F, 0x00, 0xFF,\n  0x20, 0x90, 0x08, 0x87, 0xC2, 0x21, 0x00, 0x81, 0x40, 0xFF, 0xC0, 0xFF,\n  0xA0, 0x50, 0x08, 0x87, 0xC2, 0x21, 0x00, 0x80, 0x40, 0x78, 0x00, 0x1E,\n  0x98, 0x6C, 0x0A, 0x00, 0x80, 0x20, 0xF8, 0x0B, 0x02, 0x60, 0x87, 0xC0,\n  0xE3, 0xA0, 0x90, 0x48, 0x27, 0xF2, 0x09, 0x04, 0x82, 0x41, 0x71, 0xC0,\n  0xF9, 0x08, 0x42, 0x10, 0x84, 0x27, 0xC0, 0x1F, 0x02, 0x02, 0x02, 0x02,\n  0x02, 0x82, 0x82, 0xC6, 0x78, 0xE3, 0xA1, 0x11, 0x09, 0x05, 0x83, 0x21,\n  0x08, 0x84, 0x41, 0x70, 0xC0, 0xE0, 0x40, 0x40, 0x40, 0x40, 0x40, 0x41,\n  0x41, 0x41, 0xFF, 0xE0, 0xEC, 0x19, 0x45, 0x28, 0xA4, 0xA4, 0x94, 0x91,\n  0x12, 0x02, 0x40, 0x5C, 0x1C, 0xC3, 0xB0, 0x94, 0x4A, 0x24, 0x92, 0x49,\n  0x14, 0x8A, 0x43, 0x70, 0x80, 0x1E, 0x31, 0x90, 0x50, 0x18, 0x0C, 0x06,\n  0x02, 0x82, 0x63, 0x0F, 0x00, 0xFE, 0x43, 0x41, 0x41, 0x42, 0x7C, 0x40,\n  0x40, 0x40, 0xF0, 0x1C, 0x31, 0x90, 0x50, 0x18, 0x0C, 0x06, 0x02, 0x82,\n  0x63, 0x1F, 0x04, 0x07, 0x92, 0x30, 0xFE, 0x21, 0x90, 0x48, 0x24, 0x23,\n  0xE1, 0x10, 0x84, 0x41, 0x70, 0xC0, 0x3A, 0xCD, 0x0A, 0x03, 0x01, 0x80,\n  0xC1, 0xC7, 0x78, 0xFF, 0xC4, 0x62, 0x21, 0x00, 0x80, 0x40, 0x20, 0x10,\n  0x08, 0x1F, 0x00, 0xE3, 0xA0, 0x90, 0x48, 0x24, 0x12, 0x09, 0x04, 0x82,\n  0x22, 0x0E, 0x00, 0xF1, 0xE8, 0x10, 0x82, 0x10, 0x42, 0x10, 0x22, 0x04,\n  0x80, 0x50, 0x0C, 0x00, 0x80, 0xF1, 0xE8, 0x09, 0x11, 0x25, 0x44, 0xA8,\n  0x55, 0x0C, 0xA1, 0x8C, 0x31, 0x84, 0x30, 0xE3, 0xA0, 0x88, 0x82, 0x80,\n  0x80, 0xC0, 0x90, 0x44, 0x41, 0x71, 0xC0, 0xE3, 0xA0, 0x88, 0x82, 0x81,\n  0x40, 0x40, 0x20, 0x10, 0x08, 0x1F, 0x00, 0xFD, 0x0A, 0x20, 0x81, 0x04,\n  0x10, 0x21, 0x83, 0xFC, 0xEA, 0xAA, 0xAA, 0xC0, 0x80, 0x81, 0x03, 0x02,\n  0x04, 0x04, 0x08, 0x08, 0x10, 0x10, 0x20, 0x20, 0xD5, 0x55, 0x55, 0xC0,\n  0x10, 0x51, 0x22, 0x28, 0x20, 0xFF, 0xE0, 0x88, 0x80, 0x7E, 0x00, 0x80,\n  0x47, 0xEC, 0x14, 0x0A, 0x0C, 0xFB, 0xC0, 0x20, 0x10, 0x0B, 0xC6, 0x12,\n  0x05, 0x02, 0x81, 0x40, 0xB0, 0xB7, 0x80, 0x3A, 0x8E, 0x0C, 0x08, 0x10,\n  0x10, 0x9E, 0x03, 0x00, 0x80, 0x47, 0xA4, 0x34, 0x0A, 0x05, 0x02, 0x81,\n  0x21, 0x8F, 0x60, 0x3C, 0x43, 0x81, 0xFF, 0x80, 0x80, 0x61, 0x3E, 0x3D,\n  0x04, 0x3E, 0x41, 0x04, 0x10, 0x41, 0x0F, 0x80, 0x3D, 0xA1, 0xA0, 0x50,\n  0x28, 0x14, 0x09, 0x0C, 0x7A, 0x01, 0x01, 0x87, 0x80, 0xC0, 0x20, 0x10,\n  0x0B, 0xC6, 0x32, 0x09, 0x04, 0x82, 0x41, 0x20, 0xB8, 0xE0, 0x10, 0x01,\n  0xC0, 0x81, 0x02, 0x04, 0x08, 0x11, 0xFC, 0x10, 0x3E, 0x10, 0x84, 0x21,\n  0x08, 0x42, 0x3F, 0x00, 0xC0, 0x40, 0x40, 0x4F, 0x44, 0x58, 0x70, 0x48,\n  0x44, 0x42, 0xC7, 0x70, 0x20, 0x40, 0x81, 0x02, 0x04, 0x08, 0x10, 0x23,\n  0xF8, 0xB7, 0x64, 0x62, 0x31, 0x18, 0x8C, 0x46, 0x23, 0x91, 0x5E, 0x31,\n  0x90, 0x48, 0x24, 0x12, 0x09, 0x05, 0xC7, 0x3E, 0x31, 0xA0, 0x30, 0x18,\n  0x0C, 0x05, 0x8C, 0x7C, 0xDE, 0x30, 0x90, 0x28, 0x14, 0x0A, 0x05, 0x84,\n  0xBC, 0x40, 0x20, 0x38, 0x00, 0x3D, 0xA1, 0xA0, 0x50, 0x28, 0x14, 0x09,\n  0x0C, 0x7A, 0x01, 0x00, 0x80, 0xE0, 0xCE, 0xA1, 0x82, 0x04, 0x08, 0x10,\n  0x7C, 0x3A, 0x8D, 0x0B, 0x80, 0xF0, 0x70, 0xDE, 0x40, 0x40, 0xFC, 0x40,\n  0x40, 0x40, 0x40, 0x40, 0x41, 0x3E, 0xC3, 0x41, 0x41, 0x41, 0x41, 0x41,\n  0x43, 0x3D, 0xE3, 0xA0, 0x90, 0x84, 0x42, 0x20, 0xA0, 0x50, 0x10, 0xE3,\n  0xC0, 0x92, 0x4B, 0x25, 0x92, 0xA9, 0x98, 0x44, 0xE3, 0x31, 0x05, 0x01,\n  0x01, 0x41, 0x11, 0x05, 0xC7, 0xE3, 0xA0, 0x90, 0x84, 0x42, 0x40, 0xA0,\n  0x60, 0x10, 0x10, 0x08, 0x3E, 0x00, 0xFD, 0x08, 0x20, 0x82, 0x08, 0x10,\n  0xBF, 0x29, 0x24, 0xA2, 0x49, 0x26, 0xFF, 0xF8, 0x89, 0x24, 0x8A, 0x49,\n  0x2C, 0x61, 0x24, 0x30 };\n\nconst GFXglyph FreeMono9pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,  11,    0,    1 },   // 0x20 ' '\n  {     0,   2,  11,  11,    4,  -10 },   // 0x21 '!'\n  {     3,   6,   5,  11,    2,  -10 },   // 0x22 '\"'\n  {     7,   7,  12,  11,    2,  -10 },   // 0x23 '#'\n  {    18,   8,  12,  11,    1,  -10 },   // 0x24 '$'\n  {    30,   7,  11,  11,    2,  -10 },   // 0x25 '%'\n  {    40,   7,  10,  11,    2,   -9 },   // 0x26 '&'\n  {    49,   3,   5,  11,    4,  -10 },   // 0x27 '''\n  {    51,   2,  13,  11,    5,  -10 },   // 0x28 '('\n  {    55,   2,  13,  11,    4,  -10 },   // 0x29 ')'\n  {    59,   7,   7,  11,    2,  -10 },   // 0x2A '*'\n  {    66,   7,   7,  11,    2,   -8 },   // 0x2B '+'\n  {    73,   3,   5,  11,    2,   -1 },   // 0x2C ','\n  {    75,   9,   1,  11,    1,   -5 },   // 0x2D '-'\n  {    77,   2,   2,  11,    4,   -1 },   // 0x2E '.'\n  {    78,   7,  13,  11,    2,  -11 },   // 0x2F '/'\n  {    90,   7,  11,  11,    2,  -10 },   // 0x30 '0'\n  {   100,   5,  11,  11,    3,  -10 },   // 0x31 '1'\n  {   107,   7,  11,  11,    2,  -10 },   // 0x32 '2'\n  {   117,   8,  11,  11,    1,  -10 },   // 0x33 '3'\n  {   128,   6,  11,  11,    3,  -10 },   // 0x34 '4'\n  {   137,   7,  11,  11,    2,  -10 },   // 0x35 '5'\n  {   147,   7,  11,  11,    2,  -10 },   // 0x36 '6'\n  {   157,   7,  11,  11,    2,  -10 },   // 0x37 '7'\n  {   167,   7,  11,  11,    2,  -10 },   // 0x38 '8'\n  {   177,   7,  11,  11,    2,  -10 },   // 0x39 '9'\n  {   187,   2,   8,  11,    4,   -7 },   // 0x3A ':'\n  {   189,   3,  11,  11,    3,   -7 },   // 0x3B ';'\n  {   194,   8,   8,  11,    1,   -8 },   // 0x3C '<'\n  {   202,   9,   4,  11,    1,   -6 },   // 0x3D '='\n  {   207,   9,   8,  11,    1,   -8 },   // 0x3E '>'\n  {   216,   7,  10,  11,    2,   -9 },   // 0x3F '?'\n  {   225,   8,  12,  11,    2,  -10 },   // 0x40 '@'\n  {   237,  11,  10,  11,    0,   -9 },   // 0x41 'A'\n  {   251,   9,  10,  11,    1,   -9 },   // 0x42 'B'\n  {   263,   9,  10,  11,    1,   -9 },   // 0x43 'C'\n  {   275,   9,  10,  11,    1,   -9 },   // 0x44 'D'\n  {   287,   9,  10,  11,    1,   -9 },   // 0x45 'E'\n  {   299,   9,  10,  11,    1,   -9 },   // 0x46 'F'\n  {   311,  10,  10,  11,    1,   -9 },   // 0x47 'G'\n  {   324,   9,  10,  11,    1,   -9 },   // 0x48 'H'\n  {   336,   5,  10,  11,    3,   -9 },   // 0x49 'I'\n  {   343,   8,  10,  11,    2,   -9 },   // 0x4A 'J'\n  {   353,   9,  10,  11,    1,   -9 },   // 0x4B 'K'\n  {   365,   8,  10,  11,    2,   -9 },   // 0x4C 'L'\n  {   375,  11,  10,  11,    0,   -9 },   // 0x4D 'M'\n  {   389,   9,  10,  11,    1,   -9 },   // 0x4E 'N'\n  {   401,   9,  10,  11,    1,   -9 },   // 0x4F 'O'\n  {   413,   8,  10,  11,    1,   -9 },   // 0x50 'P'\n  {   423,   9,  13,  11,    1,   -9 },   // 0x51 'Q'\n  {   438,   9,  10,  11,    1,   -9 },   // 0x52 'R'\n  {   450,   7,  10,  11,    2,   -9 },   // 0x53 'S'\n  {   459,   9,  10,  11,    1,   -9 },   // 0x54 'T'\n  {   471,   9,  10,  11,    1,   -9 },   // 0x55 'U'\n  {   483,  11,  10,  11,    0,   -9 },   // 0x56 'V'\n  {   497,  11,  10,  11,    0,   -9 },   // 0x57 'W'\n  {   511,   9,  10,  11,    1,   -9 },   // 0x58 'X'\n  {   523,   9,  10,  11,    1,   -9 },   // 0x59 'Y'\n  {   535,   7,  10,  11,    2,   -9 },   // 0x5A 'Z'\n  {   544,   2,  13,  11,    5,  -10 },   // 0x5B '['\n  {   548,   7,  13,  11,    2,  -11 },   // 0x5C '\\'\n  {   560,   2,  13,  11,    4,  -10 },   // 0x5D ']'\n  {   564,   7,   5,  11,    2,  -10 },   // 0x5E '^'\n  {   569,  11,   1,  11,    0,    2 },   // 0x5F '_'\n  {   571,   3,   3,  11,    3,  -11 },   // 0x60 '`'\n  {   573,   9,   8,  11,    1,   -7 },   // 0x61 'a'\n  {   582,   9,  11,  11,    1,  -10 },   // 0x62 'b'\n  {   595,   7,   8,  11,    2,   -7 },   // 0x63 'c'\n  {   602,   9,  11,  11,    1,  -10 },   // 0x64 'd'\n  {   615,   8,   8,  11,    1,   -7 },   // 0x65 'e'\n  {   623,   6,  11,  11,    3,  -10 },   // 0x66 'f'\n  {   632,   9,  11,  11,    1,   -7 },   // 0x67 'g'\n  {   645,   9,  11,  11,    1,  -10 },   // 0x68 'h'\n  {   658,   7,  10,  11,    2,   -9 },   // 0x69 'i'\n  {   667,   5,  13,  11,    3,   -9 },   // 0x6A 'j'\n  {   676,   8,  11,  11,    2,  -10 },   // 0x6B 'k'\n  {   687,   7,  11,  11,    2,  -10 },   // 0x6C 'l'\n  {   697,   9,   8,  11,    1,   -7 },   // 0x6D 'm'\n  {   706,   9,   8,  11,    1,   -7 },   // 0x6E 'n'\n  {   715,   9,   8,  11,    1,   -7 },   // 0x6F 'o'\n  {   724,   9,  11,  11,    1,   -7 },   // 0x70 'p'\n  {   737,   9,  11,  11,    1,   -7 },   // 0x71 'q'\n  {   750,   7,   8,  11,    3,   -7 },   // 0x72 'r'\n  {   757,   7,   8,  11,    2,   -7 },   // 0x73 's'\n  {   764,   8,  10,  11,    2,   -9 },   // 0x74 't'\n  {   774,   8,   8,  11,    1,   -7 },   // 0x75 'u'\n  {   782,   9,   8,  11,    1,   -7 },   // 0x76 'v'\n  {   791,   9,   8,  11,    1,   -7 },   // 0x77 'w'\n  {   800,   9,   8,  11,    1,   -7 },   // 0x78 'x'\n  {   809,   9,  11,  11,    1,   -7 },   // 0x79 'y'\n  {   822,   7,   8,  11,    2,   -7 },   // 0x7A 'z'\n  {   829,   3,  13,  11,    4,  -10 },   // 0x7B '{'\n  {   834,   1,  13,  11,    5,  -10 },   // 0x7C '|'\n  {   836,   3,  13,  11,    4,  -10 },   // 0x7D '}'\n  {   841,   7,   3,  11,    2,   -6 } }; // 0x7E '~'\n\nconst GFXfont FreeMono9pt7b PROGMEM = {\n  (uint8_t  *)FreeMono9pt7bBitmaps,\n  (GFXglyph *)FreeMono9pt7bGlyphs,\n  0x20, 0x7E, 18 };\n\n// Approx. 1516 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeMonoBold12pt7b.h",
    "content": "const uint8_t FreeMonoBold12pt7bBitmaps[] PROGMEM = {\n  0xFF, 0xFF, 0xFF, 0xF6, 0x66, 0x60, 0x6F, 0x60, 0xE7, 0xE7, 0x62, 0x42,\n  0x42, 0x42, 0x42, 0x11, 0x87, 0x30, 0xC6, 0x18, 0xC3, 0x31, 0xFF, 0xFF,\n  0xF9, 0x98, 0x33, 0x06, 0x60, 0xCC, 0x7F, 0xEF, 0xFC, 0x66, 0x0C, 0xC3,\n  0x98, 0x63, 0x04, 0x40, 0x0C, 0x03, 0x00, 0xC0, 0xFE, 0x7F, 0x9C, 0x66,\n  0x09, 0x80, 0x78, 0x0F, 0xE0, 0x7F, 0x03, 0xE0, 0xF8, 0x7F, 0xFB, 0xFC,\n  0x0C, 0x03, 0x00, 0xC0, 0x30, 0x38, 0x1F, 0x0C, 0x42, 0x10, 0xC4, 0x1F,\n  0x03, 0x9C, 0x3C, 0x7F, 0x33, 0xE0, 0x8C, 0x21, 0x08, 0xC3, 0xE0, 0x70,\n  0x3E, 0x1F, 0xC6, 0x61, 0x80, 0x70, 0x0C, 0x07, 0x83, 0xEE, 0xDF, 0xB3,\n  0xCC, 0x73, 0xFE, 0x7F, 0x80, 0xFD, 0x24, 0x90, 0x39, 0xDC, 0xE6, 0x73,\n  0x18, 0xC6, 0x31, 0x8C, 0x31, 0x8E, 0x31, 0xC4, 0xE7, 0x1C, 0xE3, 0x1C,\n  0x63, 0x18, 0xC6, 0x31, 0x98, 0xCE, 0x67, 0x10, 0x0C, 0x03, 0x00, 0xC3,\n  0xB7, 0xFF, 0xDF, 0xE1, 0xE0, 0xFC, 0x33, 0x0C, 0xC0, 0x06, 0x00, 0x60,\n  0x06, 0x00, 0x60, 0x06, 0x0F, 0xFF, 0xFF, 0xF0, 0x60, 0x06, 0x00, 0x60,\n  0x06, 0x00, 0x60, 0x06, 0x00, 0x3B, 0x9C, 0xCE, 0x62, 0x00, 0xFF, 0xFF,\n  0xFF, 0xFF, 0x80, 0x00, 0x40, 0x30, 0x1C, 0x07, 0x03, 0x80, 0xE0, 0x30,\n  0x1C, 0x06, 0x03, 0x80, 0xC0, 0x70, 0x18, 0x0E, 0x03, 0x01, 0xC0, 0x60,\n  0x38, 0x0E, 0x01, 0x00, 0x1E, 0x0F, 0xC6, 0x1B, 0x87, 0xC0, 0xF0, 0x3C,\n  0x0F, 0x03, 0xC0, 0xF0, 0x3C, 0x0F, 0x87, 0x61, 0x8F, 0xC1, 0xE0, 0x1C,\n  0x0F, 0x0F, 0xC3, 0xB0, 0x0C, 0x03, 0x00, 0xC0, 0x30, 0x0C, 0x03, 0x00,\n  0xC0, 0x30, 0x0C, 0x3F, 0xFF, 0xFC, 0x1F, 0x1F, 0xEE, 0x1F, 0x83, 0xC0,\n  0xC0, 0x70, 0x38, 0x1E, 0x0F, 0x07, 0x83, 0xC1, 0xE3, 0xF0, 0xFF, 0xFF,\n  0xFC, 0x3F, 0x0F, 0xF1, 0x87, 0x00, 0x60, 0x0C, 0x03, 0x83, 0xE0, 0x7C,\n  0x01, 0xC0, 0x0C, 0x01, 0x80, 0x3C, 0x0F, 0xFF, 0x9F, 0xC0, 0x07, 0x07,\n  0x83, 0xC3, 0xE1, 0xB1, 0xD8, 0xCC, 0xC6, 0xE3, 0x7F, 0xFF, 0xE0, 0x61,\n  0xF8, 0xFC, 0x7F, 0x9F, 0xE6, 0x01, 0x80, 0x60, 0x1F, 0x87, 0xF9, 0x86,\n  0x00, 0xC0, 0x30, 0x0C, 0x03, 0xC1, 0xBF, 0xE7, 0xE0, 0x07, 0xC7, 0xF3,\n  0xC1, 0xC0, 0x60, 0x38, 0x0E, 0xF3, 0xFE, 0xF1, 0xF8, 0x3E, 0x0F, 0x83,\n  0x71, 0xCF, 0xE1, 0xF0, 0xFF, 0xFF, 0xFC, 0x1F, 0x07, 0x01, 0x80, 0x60,\n  0x38, 0x0C, 0x03, 0x01, 0xC0, 0x60, 0x18, 0x0E, 0x03, 0x00, 0xC0, 0x1E,\n  0x1F, 0xEE, 0x1F, 0x03, 0xC0, 0xF0, 0x36, 0x19, 0xFE, 0x7F, 0xB8, 0x7C,\n  0x0F, 0x03, 0xE1, 0xDF, 0xE3, 0xF0, 0x3E, 0x1F, 0xCE, 0x3B, 0x07, 0xC1,\n  0xF0, 0x7E, 0x3D, 0xFF, 0x3D, 0xC0, 0x70, 0x18, 0x0E, 0x0F, 0x3F, 0x8F,\n  0x80, 0xFF, 0x80, 0x00, 0xFF, 0x80, 0x77, 0x70, 0x00, 0x00, 0x76, 0x6C,\n  0xC8, 0x80, 0x00, 0x30, 0x0F, 0x03, 0xE0, 0xF8, 0x3E, 0x0F, 0x80, 0x3E,\n  0x00, 0xF8, 0x03, 0xE0, 0x0F, 0x00, 0x20, 0xFF, 0xFF, 0xFF, 0x00, 0x00,\n  0x00, 0x00, 0x0F, 0xFF, 0xFF, 0xF0, 0x60, 0x0F, 0x80, 0x3E, 0x00, 0xF8,\n  0x03, 0xE0, 0x1F, 0x07, 0xC1, 0xF0, 0x7C, 0x0F, 0x00, 0x40, 0x00, 0x7C,\n  0x7F, 0xB0, 0xF8, 0x30, 0x18, 0x1C, 0x3C, 0x3C, 0x18, 0x08, 0x00, 0x07,\n  0x03, 0x81, 0xC0, 0x1E, 0x07, 0xF1, 0xC7, 0x30, 0x6C, 0x0D, 0x87, 0xB3,\n  0xF6, 0xE6, 0xD8, 0xDB, 0x1B, 0x73, 0x67, 0xFC, 0x7F, 0x80, 0x30, 0x03,\n  0x00, 0x71, 0xC7, 0xF8, 0x7C, 0x00, 0x3F, 0x80, 0x7F, 0x80, 0x1F, 0x00,\n  0x76, 0x00, 0xEE, 0x01, 0x8C, 0x07, 0x18, 0x0E, 0x38, 0x1F, 0xF0, 0x7F,\n  0xF0, 0xC0, 0x61, 0x80, 0xCF, 0xC7, 0xFF, 0x8F, 0xC0, 0xFF, 0xC7, 0xFF,\n  0x0C, 0x1C, 0x60, 0x63, 0x03, 0x18, 0x38, 0xFF, 0x87, 0xFE, 0x30, 0x39,\n  0x80, 0xCC, 0x06, 0x60, 0x7F, 0xFF, 0x7F, 0xF0, 0x0F, 0xF3, 0xFF, 0x70,\n  0x76, 0x03, 0xC0, 0x3C, 0x00, 0xC0, 0x0C, 0x00, 0xC0, 0x0C, 0x00, 0x60,\n  0x37, 0x07, 0x3F, 0xF0, 0xFC, 0xFF, 0x0F, 0xFC, 0x60, 0xE6, 0x06, 0x60,\n  0x36, 0x03, 0x60, 0x36, 0x03, 0x60, 0x36, 0x03, 0x60, 0x76, 0x0E, 0xFF,\n  0xCF, 0xF8, 0xFF, 0xF7, 0xFF, 0x8C, 0x0C, 0x60, 0x63, 0x1B, 0x18, 0xC0,\n  0xFE, 0x07, 0xF0, 0x31, 0x81, 0x8C, 0xCC, 0x06, 0x60, 0x3F, 0xFF, 0xFF,\n  0xFC, 0xFF, 0xFF, 0xFF, 0xCC, 0x06, 0x60, 0x33, 0x19, 0x98, 0xC0, 0xFE,\n  0x07, 0xF0, 0x31, 0x81, 0x8C, 0x0C, 0x00, 0x60, 0x0F, 0xF0, 0x7F, 0x80,\n  0x0F, 0xF1, 0xFF, 0x9C, 0x1C, 0xC0, 0x6C, 0x03, 0x60, 0x03, 0x00, 0x18,\n  0x7F, 0xC3, 0xFE, 0x01, 0xB8, 0x0C, 0xE0, 0xE3, 0xFF, 0x07, 0xE0, 0x7C,\n  0xF9, 0xF3, 0xE3, 0x03, 0x0C, 0x0C, 0x30, 0x30, 0xC0, 0xC3, 0xFF, 0x0F,\n  0xFC, 0x30, 0x30, 0xC0, 0xC3, 0x03, 0x0C, 0x0C, 0xFC, 0xFF, 0xF3, 0xF0,\n  0xFF, 0xFF, 0xF0, 0xC0, 0x30, 0x0C, 0x03, 0x00, 0xC0, 0x30, 0x0C, 0x03,\n  0x00, 0xC0, 0x30, 0xFF, 0xFF, 0xF0, 0x0F, 0xF8, 0x7F, 0xC0, 0x30, 0x01,\n  0x80, 0x0C, 0x00, 0x60, 0x03, 0x18, 0x18, 0xC0, 0xC6, 0x06, 0x30, 0x31,\n  0xC3, 0x0F, 0xF8, 0x1F, 0x00, 0xFC, 0xFB, 0xF3, 0xE3, 0x0E, 0x0C, 0x70,\n  0x33, 0x80, 0xFC, 0x03, 0xF0, 0x0F, 0xE0, 0x39, 0xC0, 0xC3, 0x03, 0x0E,\n  0x0C, 0x18, 0xFC, 0x7F, 0xF0, 0xF0, 0xFF, 0x0F, 0xF0, 0x18, 0x01, 0x80,\n  0x18, 0x01, 0x80, 0x18, 0x01, 0x80, 0x18, 0x31, 0x83, 0x18, 0x31, 0x83,\n  0xFF, 0xFF, 0xFF, 0xF0, 0x3F, 0xC0, 0xF7, 0x87, 0x9E, 0x1E, 0x7C, 0xF9,\n  0xB3, 0xE6, 0xFD, 0x99, 0xF6, 0x67, 0x99, 0x8E, 0x66, 0x31, 0x98, 0x06,\n  0xFC, 0xFF, 0xF3, 0xF0, 0xF1, 0xFF, 0xCF, 0xCF, 0x0C, 0x78, 0x63, 0xE3,\n  0x1B, 0x18, 0xDC, 0xC6, 0x76, 0x31, 0xB1, 0x8F, 0x8C, 0x3C, 0x61, 0xE7,\n  0xE7, 0x3F, 0x18, 0x0F, 0x03, 0xFC, 0x70, 0xE6, 0x06, 0xE0, 0x7C, 0x03,\n  0xC0, 0x3C, 0x03, 0xC0, 0x3E, 0x07, 0x60, 0x67, 0x0E, 0x3F, 0xC0, 0xF0,\n  0xFF, 0x8F, 0xFE, 0x30, 0x73, 0x03, 0x30, 0x33, 0x03, 0x30, 0x73, 0xFE,\n  0x3F, 0x83, 0x00, 0x30, 0x03, 0x00, 0xFF, 0x0F, 0xF0, 0x0F, 0x03, 0xFC,\n  0x70, 0xE6, 0x06, 0xE0, 0x7C, 0x03, 0xC0, 0x3C, 0x03, 0xC0, 0x3E, 0x07,\n  0x60, 0x67, 0x0E, 0x3F, 0xC1, 0xF0, 0x18, 0x33, 0xFF, 0x3F, 0xE0, 0xFF,\n  0x83, 0xFF, 0x83, 0x07, 0x0C, 0x0C, 0x30, 0x30, 0xC1, 0xC3, 0xFE, 0x0F,\n  0xF0, 0x31, 0xE0, 0xC3, 0x83, 0x07, 0x0C, 0x0C, 0xFE, 0x3F, 0xF8, 0x70,\n  0x3F, 0xDF, 0xFE, 0x1F, 0x03, 0xC0, 0xF8, 0x07, 0xE0, 0x7E, 0x01, 0xF0,\n  0x3C, 0x0F, 0x87, 0xFF, 0xBF, 0xC0, 0xFF, 0xFF, 0xFF, 0xC6, 0x3C, 0x63,\n  0xC6, 0x3C, 0x63, 0x06, 0x00, 0x60, 0x06, 0x00, 0x60, 0x06, 0x00, 0x60,\n  0x3F, 0xC3, 0xFC, 0xFF, 0xFF, 0xFF, 0x60, 0x66, 0x06, 0x60, 0x66, 0x06,\n  0x60, 0x66, 0x06, 0x60, 0x66, 0x06, 0x60, 0x63, 0x9C, 0x1F, 0xC0, 0xF0,\n  0xFC, 0x3F, 0xFC, 0x3F, 0x30, 0x0C, 0x38, 0x1C, 0x18, 0x18, 0x1C, 0x38,\n  0x1C, 0x38, 0x0E, 0x70, 0x0E, 0x70, 0x0F, 0x60, 0x07, 0xE0, 0x07, 0xE0,\n  0x03, 0xC0, 0x03, 0xC0, 0xFC, 0xFF, 0xF3, 0xF6, 0x01, 0xDC, 0xC6, 0x77,\n  0x99, 0xDE, 0x67, 0x79, 0x8D, 0xFE, 0x3F, 0xF8, 0xF3, 0xE3, 0xCF, 0x8F,\n  0x3C, 0x38, 0x70, 0xE1, 0xC0, 0xF8, 0xFB, 0xE3, 0xE3, 0x86, 0x0F, 0x38,\n  0x1F, 0xC0, 0x3E, 0x00, 0x70, 0x03, 0xE0, 0x0F, 0x80, 0x77, 0x03, 0x8E,\n  0x1E, 0x1C, 0xFC, 0xFF, 0xF3, 0xF0, 0xF9, 0xFF, 0x9F, 0x30, 0xC3, 0x9C,\n  0x19, 0x81, 0xF8, 0x0F, 0x00, 0x60, 0x06, 0x00, 0x60, 0x06, 0x00, 0x60,\n  0x3F, 0xC3, 0xFC, 0xFF, 0xBF, 0xEC, 0x3B, 0x0C, 0xC6, 0x33, 0x80, 0xC0,\n  0x60, 0x38, 0xCC, 0x36, 0x0F, 0x03, 0xFF, 0xFF, 0xF0, 0xFF, 0xF1, 0x8C,\n  0x63, 0x18, 0xC6, 0x31, 0x8C, 0x63, 0x18, 0xC7, 0xFE, 0x40, 0x30, 0x0E,\n  0x01, 0x80, 0x70, 0x0C, 0x03, 0x80, 0x60, 0x1C, 0x03, 0x00, 0xE0, 0x18,\n  0x07, 0x00, 0xC0, 0x38, 0x0E, 0x01, 0xC0, 0x70, 0x0C, 0x01, 0xFF, 0xC6,\n  0x31, 0x8C, 0x63, 0x18, 0xC6, 0x31, 0x8C, 0x63, 0x1F, 0xFE, 0x04, 0x03,\n  0x01, 0xE0, 0xFC, 0x7B, 0x9C, 0x7E, 0x1F, 0x03, 0xFF, 0xFF, 0xFF, 0xF0,\n  0xCE, 0x73, 0x3F, 0x07, 0xF8, 0x00, 0xC0, 0x0C, 0x1F, 0xC7, 0xFC, 0x60,\n  0xCC, 0x0C, 0xC1, 0xCF, 0xFF, 0x3F, 0xF0, 0xF0, 0x07, 0x80, 0x0C, 0x00,\n  0x60, 0x03, 0x7C, 0x1F, 0xF8, 0xF1, 0xC7, 0x07, 0x30, 0x19, 0x80, 0xCC,\n  0x06, 0x60, 0x73, 0xC7, 0x7F, 0xFB, 0xDF, 0x00, 0x1F, 0xB3, 0xFF, 0x70,\n  0xFE, 0x07, 0xC0, 0x3C, 0x00, 0xC0, 0x0C, 0x00, 0x70, 0x77, 0xFF, 0x1F,\n  0xC0, 0x01, 0xE0, 0x0F, 0x00, 0x18, 0x00, 0xC1, 0xF6, 0x3F, 0xF1, 0xC7,\n  0x9C, 0x1C, 0xC0, 0x66, 0x03, 0x30, 0x19, 0x81, 0xC7, 0x1E, 0x3F, 0xFC,\n  0x7D, 0xE0, 0x1F, 0x83, 0xFC, 0x70, 0xEE, 0x07, 0xFF, 0xFF, 0xFF, 0xE0,\n  0x0E, 0x00, 0x70, 0x73, 0xFF, 0x1F, 0xC0, 0x07, 0xC3, 0xFC, 0x60, 0x0C,\n  0x0F, 0xFD, 0xFF, 0x86, 0x00, 0xC0, 0x18, 0x03, 0x00, 0x60, 0x0C, 0x01,\n  0x81, 0xFF, 0xBF, 0xF0, 0x1F, 0x79, 0xFF, 0xDC, 0x79, 0x81, 0xCC, 0x06,\n  0x60, 0x33, 0x01, 0x9C, 0x1C, 0x71, 0xE1, 0xFF, 0x07, 0xD8, 0x00, 0xC0,\n  0x06, 0x00, 0x70, 0x7F, 0x03, 0xF0, 0xF0, 0x03, 0xC0, 0x03, 0x00, 0x0C,\n  0x00, 0x37, 0xC0, 0xFF, 0x83, 0xC7, 0x0C, 0x0C, 0x30, 0x30, 0xC0, 0xC3,\n  0x03, 0x0C, 0x0C, 0x30, 0x33, 0xF3, 0xFF, 0xCF, 0xC0, 0x06, 0x00, 0xC0,\n  0x00, 0x3F, 0x07, 0xE0, 0x0C, 0x01, 0x80, 0x30, 0x06, 0x00, 0xC0, 0x18,\n  0x03, 0x0F, 0xFF, 0xFF, 0xC0, 0x06, 0x06, 0x00, 0xFF, 0xFF, 0x03, 0x03,\n  0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x07, 0xFE, 0xFC,\n  0xF0, 0x07, 0x80, 0x0C, 0x00, 0x60, 0x03, 0x3F, 0x19, 0xF8, 0xDE, 0x07,\n  0xE0, 0x3E, 0x01, 0xF0, 0x0F, 0xC0, 0x6F, 0x03, 0x1C, 0x78, 0xFF, 0xC7,\n  0xE0, 0x7E, 0x0F, 0xC0, 0x18, 0x03, 0x00, 0x60, 0x0C, 0x01, 0x80, 0x30,\n  0x06, 0x00, 0xC0, 0x18, 0x03, 0x00, 0x61, 0xFF, 0xFF, 0xF8, 0xFE, 0xF1,\n  0xFF, 0xF1, 0xCE, 0x63, 0x18, 0xC6, 0x31, 0x8C, 0x63, 0x18, 0xC6, 0x31,\n  0x8C, 0x63, 0x19, 0xF7, 0xBF, 0xEF, 0x78, 0x77, 0xC1, 0xFF, 0x83, 0xC7,\n  0x0C, 0x0C, 0x30, 0x30, 0xC0, 0xC3, 0x03, 0x0C, 0x0C, 0x30, 0x33, 0xF1,\n  0xFF, 0xC7, 0xC0, 0x1F, 0x83, 0xFC, 0x70, 0xEE, 0x07, 0xC0, 0x3C, 0x03,\n  0xC0, 0x3E, 0x07, 0x70, 0xE3, 0xFC, 0x1F, 0x80, 0xF7, 0xE3, 0xFF, 0xC3,\n  0xC3, 0x8E, 0x07, 0x30, 0x0C, 0xC0, 0x33, 0x00, 0xCE, 0x07, 0x3C, 0x38,\n  0xFF, 0xC3, 0x7E, 0x0C, 0x00, 0x30, 0x00, 0xC0, 0x0F, 0xE0, 0x3F, 0x80,\n  0x1F, 0xBC, 0xFF, 0xF7, 0x0F, 0x38, 0x1C, 0xC0, 0x33, 0x00, 0xCC, 0x03,\n  0x38, 0x1C, 0x70, 0xF0, 0xFF, 0xC1, 0xFB, 0x00, 0x0C, 0x00, 0x30, 0x00,\n  0xC0, 0x1F, 0xC0, 0x7F, 0x79, 0xE7, 0xFF, 0x1F, 0x31, 0xC0, 0x18, 0x01,\n  0x80, 0x18, 0x01, 0x80, 0x18, 0x0F, 0xFC, 0xFF, 0xC0, 0x3F, 0x9F, 0xFE,\n  0x1F, 0x82, 0xFE, 0x1F, 0xE0, 0xFF, 0x03, 0xE0, 0xFF, 0xFF, 0xF0, 0x30,\n  0x06, 0x00, 0xC0, 0x7F, 0xEF, 0xFC, 0x60, 0x0C, 0x01, 0x80, 0x30, 0x06,\n  0x00, 0xC0, 0x18, 0x71, 0xFE, 0x1F, 0x00, 0xF1, 0xF7, 0x8F, 0x8C, 0x0C,\n  0x60, 0x63, 0x03, 0x18, 0x18, 0xC0, 0xC6, 0x06, 0x38, 0xF0, 0xFF, 0xC3,\n  0xEE, 0xFC, 0xFF, 0xF3, 0xF3, 0x87, 0x0E, 0x1C, 0x1C, 0x60, 0x73, 0x80,\n  0xEC, 0x03, 0xF0, 0x07, 0x80, 0x1E, 0x00, 0x78, 0x00, 0xF8, 0x7F, 0xE1,\n  0xF7, 0x39, 0x8C, 0xE6, 0x37, 0xB0, 0xFF, 0xC3, 0xFF, 0x07, 0xBC, 0x1C,\n  0xF0, 0x73, 0x81, 0x86, 0x00, 0x7C, 0xF9, 0xF3, 0xE3, 0xCF, 0x07, 0xF8,\n  0x0F, 0xC0, 0x1E, 0x00, 0xFC, 0x07, 0x38, 0x38, 0x73, 0xF3, 0xFF, 0xCF,\n  0xC0, 0xF9, 0xFF, 0x9F, 0x70, 0xE3, 0x0C, 0x39, 0xC1, 0x98, 0x19, 0x81,\n  0xF8, 0x0F, 0x00, 0xF0, 0x06, 0x00, 0x60, 0x0E, 0x00, 0xC0, 0xFF, 0x0F,\n  0xF0, 0x7F, 0xCF, 0xF9, 0x8E, 0x33, 0x80, 0x70, 0x1C, 0x07, 0x01, 0xC6,\n  0x70, 0xFF, 0xFF, 0xFF, 0x80, 0x0E, 0x3C, 0x60, 0xC1, 0x83, 0x06, 0x0C,\n  0x39, 0xE3, 0xC0, 0xC1, 0x83, 0x06, 0x0C, 0x18, 0x3C, 0x38, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xF0, 0xE1, 0xC0, 0xC1, 0x83, 0x06, 0x0C, 0x18, 0x30, 0x3C,\n  0x79, 0x83, 0x06, 0x0C, 0x18, 0x31, 0xE3, 0x80, 0x3C, 0x37, 0xE7, 0x67,\n  0xE6, 0x1C };\n\nconst GFXglyph FreeMonoBold12pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,  14,    0,    1 },   // 0x20 ' '\n  {     0,   4,  15,  14,    5,  -14 },   // 0x21 '!'\n  {     8,   8,   7,  14,    3,  -13 },   // 0x22 '\"'\n  {    15,  11,  18,  14,    2,  -15 },   // 0x23 '#'\n  {    40,  10,  20,  14,    2,  -16 },   // 0x24 '$'\n  {    65,  10,  15,  14,    2,  -14 },   // 0x25 '%'\n  {    84,  10,  13,  14,    2,  -12 },   // 0x26 '&'\n  {   101,   3,   7,  14,    5,  -13 },   // 0x27 '''\n  {   104,   5,  19,  14,    6,  -14 },   // 0x28 '('\n  {   116,   5,  19,  14,    3,  -14 },   // 0x29 ')'\n  {   128,  10,  10,  14,    2,  -14 },   // 0x2A '*'\n  {   141,  12,  13,  14,    1,  -12 },   // 0x2B '+'\n  {   161,   5,   7,  14,    4,   -2 },   // 0x2C ','\n  {   166,  12,   2,  14,    1,   -7 },   // 0x2D '-'\n  {   169,   3,   3,  14,    5,   -2 },   // 0x2E '.'\n  {   171,  10,  20,  14,    2,  -16 },   // 0x2F '/'\n  {   196,  10,  15,  14,    2,  -14 },   // 0x30 '0'\n  {   215,  10,  15,  14,    2,  -14 },   // 0x31 '1'\n  {   234,  10,  15,  14,    2,  -14 },   // 0x32 '2'\n  {   253,  11,  15,  14,    1,  -14 },   // 0x33 '3'\n  {   274,   9,  14,  14,    2,  -13 },   // 0x34 '4'\n  {   290,  10,  15,  14,    2,  -14 },   // 0x35 '5'\n  {   309,  10,  15,  14,    2,  -14 },   // 0x36 '6'\n  {   328,  10,  15,  14,    2,  -14 },   // 0x37 '7'\n  {   347,  10,  15,  14,    2,  -14 },   // 0x38 '8'\n  {   366,  10,  15,  14,    3,  -14 },   // 0x39 '9'\n  {   385,   3,  11,  14,    5,  -10 },   // 0x3A ':'\n  {   390,   4,  15,  14,    4,  -10 },   // 0x3B ';'\n  {   398,  12,  11,  14,    1,  -11 },   // 0x3C '<'\n  {   415,  12,   7,  14,    1,   -9 },   // 0x3D '='\n  {   426,  12,  11,  14,    1,  -11 },   // 0x3E '>'\n  {   443,   9,  14,  14,    3,  -13 },   // 0x3F '?'\n  {   459,  11,  19,  14,    2,  -14 },   // 0x40 '@'\n  {   486,  15,  14,  14,   -1,  -13 },   // 0x41 'A'\n  {   513,  13,  14,  14,    0,  -13 },   // 0x42 'B'\n  {   536,  12,  14,  14,    1,  -13 },   // 0x43 'C'\n  {   557,  12,  14,  14,    1,  -13 },   // 0x44 'D'\n  {   578,  13,  14,  14,    0,  -13 },   // 0x45 'E'\n  {   601,  13,  14,  14,    0,  -13 },   // 0x46 'F'\n  {   624,  13,  14,  14,    1,  -13 },   // 0x47 'G'\n  {   647,  14,  14,  14,    0,  -13 },   // 0x48 'H'\n  {   672,  10,  14,  14,    2,  -13 },   // 0x49 'I'\n  {   690,  13,  14,  14,    1,  -13 },   // 0x4A 'J'\n  {   713,  14,  14,  14,    0,  -13 },   // 0x4B 'K'\n  {   738,  12,  14,  14,    1,  -13 },   // 0x4C 'L'\n  {   759,  14,  14,  14,    0,  -13 },   // 0x4D 'M'\n  {   784,  13,  14,  14,    0,  -13 },   // 0x4E 'N'\n  {   807,  12,  14,  14,    1,  -13 },   // 0x4F 'O'\n  {   828,  12,  14,  14,    0,  -13 },   // 0x50 'P'\n  {   849,  12,  17,  14,    1,  -13 },   // 0x51 'Q'\n  {   875,  14,  14,  14,    0,  -13 },   // 0x52 'R'\n  {   900,  10,  14,  14,    2,  -13 },   // 0x53 'S'\n  {   918,  12,  14,  14,    1,  -13 },   // 0x54 'T'\n  {   939,  12,  14,  14,    1,  -13 },   // 0x55 'U'\n  {   960,  16,  14,  14,   -1,  -13 },   // 0x56 'V'\n  {   988,  14,  14,  14,    0,  -13 },   // 0x57 'W'\n  {  1013,  14,  14,  14,    0,  -13 },   // 0x58 'X'\n  {  1038,  12,  14,  14,    1,  -13 },   // 0x59 'Y'\n  {  1059,  10,  14,  14,    2,  -13 },   // 0x5A 'Z'\n  {  1077,   5,  19,  14,    6,  -14 },   // 0x5B '['\n  {  1089,  10,  20,  14,    2,  -16 },   // 0x5C '\\'\n  {  1114,   5,  19,  14,    3,  -14 },   // 0x5D ']'\n  {  1126,  10,   8,  14,    2,  -15 },   // 0x5E '^'\n  {  1136,  14,   2,  14,    0,    4 },   // 0x5F '_'\n  {  1140,   4,   4,  14,    4,  -15 },   // 0x60 '`'\n  {  1142,  12,  11,  14,    1,  -10 },   // 0x61 'a'\n  {  1159,  13,  15,  14,    0,  -14 },   // 0x62 'b'\n  {  1184,  12,  11,  14,    1,  -10 },   // 0x63 'c'\n  {  1201,  13,  15,  14,    1,  -14 },   // 0x64 'd'\n  {  1226,  12,  11,  14,    1,  -10 },   // 0x65 'e'\n  {  1243,  11,  15,  14,    2,  -14 },   // 0x66 'f'\n  {  1264,  13,  16,  14,    1,  -10 },   // 0x67 'g'\n  {  1290,  14,  15,  14,    0,  -14 },   // 0x68 'h'\n  {  1317,  11,  14,  14,    1,  -13 },   // 0x69 'i'\n  {  1337,   8,  19,  15,    3,  -13 },   // 0x6A 'j'\n  {  1356,  13,  15,  14,    1,  -14 },   // 0x6B 'k'\n  {  1381,  11,  15,  14,    1,  -14 },   // 0x6C 'l'\n  {  1402,  15,  11,  14,    0,  -10 },   // 0x6D 'm'\n  {  1423,  14,  11,  14,    0,  -10 },   // 0x6E 'n'\n  {  1443,  12,  11,  14,    1,  -10 },   // 0x6F 'o'\n  {  1460,  14,  16,  14,    0,  -10 },   // 0x70 'p'\n  {  1488,  14,  16,  14,    0,  -10 },   // 0x71 'q'\n  {  1516,  12,  11,  14,    1,  -10 },   // 0x72 'r'\n  {  1533,  10,  11,  14,    2,  -10 },   // 0x73 's'\n  {  1547,  11,  14,  14,    1,  -13 },   // 0x74 't'\n  {  1567,  13,  11,  14,    0,  -10 },   // 0x75 'u'\n  {  1585,  14,  11,  14,    0,  -10 },   // 0x76 'v'\n  {  1605,  14,  11,  14,    0,  -10 },   // 0x77 'w'\n  {  1625,  14,  11,  14,    0,  -10 },   // 0x78 'x'\n  {  1645,  12,  16,  14,    1,  -10 },   // 0x79 'y'\n  {  1669,  11,  11,  14,    1,  -10 },   // 0x7A 'z'\n  {  1685,   7,  19,  14,    3,  -14 },   // 0x7B '{'\n  {  1702,   2,  19,  14,    6,  -14 },   // 0x7C '|'\n  {  1707,   7,  19,  14,    4,  -14 },   // 0x7D '}'\n  {  1724,  12,   4,  14,    1,   -7 } }; // 0x7E '~'\n\nconst GFXfont FreeMonoBold12pt7b PROGMEM = {\n  (uint8_t  *)FreeMonoBold12pt7bBitmaps,\n  (GFXglyph *)FreeMonoBold12pt7bGlyphs,\n  0x20, 0x7E, 24 };\n\n// Approx. 2402 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeMonoBold18pt7b.h",
    "content": "const uint8_t FreeMonoBold18pt7bBitmaps[] PROGMEM = {\n  0x77, 0xFF, 0xFF, 0xFF, 0xFF, 0xFB, 0x9C, 0xE7, 0x39, 0xC4, 0x03, 0xBF,\n  0xFF, 0xB8, 0xF1, 0xFE, 0x3F, 0xC7, 0xF8, 0xFF, 0x1E, 0xC1, 0x98, 0x33,\n  0x06, 0x60, 0xCC, 0x18, 0x0E, 0x1C, 0x0F, 0x3C, 0x1F, 0x3C, 0x1E, 0x3C,\n  0x1E, 0x3C, 0x1E, 0x78, 0x1E, 0x78, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFE, 0x1E, 0x78, 0x1E, 0x78, 0x1E, 0x78, 0x7F, 0xFE, 0x7F, 0xFE,\n  0x7F, 0xFE, 0x7F, 0xFE, 0x3C, 0x78, 0x3C, 0x78, 0x3C, 0x78, 0x3C, 0xF0,\n  0x3C, 0xF0, 0x3C, 0xF0, 0x3C, 0xF0, 0x03, 0x00, 0x1E, 0x00, 0x78, 0x01,\n  0xE0, 0x1F, 0xF1, 0xFF, 0xE7, 0xFF, 0xBE, 0x1E, 0xF0, 0x3B, 0xC0, 0xCF,\n  0xE0, 0x3F, 0xF8, 0x7F, 0xF0, 0x7F, 0xE0, 0x1F, 0xF0, 0x0F, 0xE0, 0x3F,\n  0x80, 0xFF, 0x87, 0xFF, 0xFE, 0xFF, 0xF3, 0x7F, 0x80, 0x78, 0x01, 0xE0,\n  0x07, 0x80, 0x1E, 0x00, 0x78, 0x00, 0xC0, 0x1E, 0x00, 0xFF, 0x03, 0x86,\n  0x06, 0x06, 0x0C, 0x0C, 0x18, 0x18, 0x38, 0x70, 0x3F, 0xC2, 0x1E, 0x3E,\n  0x03, 0xF8, 0x3F, 0x83, 0xF8, 0x0F, 0x8F, 0x18, 0x7F, 0x01, 0xC7, 0x03,\n  0x06, 0x06, 0x0C, 0x0C, 0x18, 0x1C, 0x70, 0x1F, 0xC0, 0x0F, 0x00, 0x03,\n  0xD0, 0x1F, 0xF0, 0x7F, 0xE1, 0xFF, 0xC3, 0xE6, 0x07, 0x80, 0x0F, 0x00,\n  0x0F, 0x00, 0x1F, 0x00, 0x3E, 0x00, 0xFE, 0x03, 0xFE, 0xFF, 0xBD, 0xFE,\n  0x3F, 0xFC, 0x3F, 0x7C, 0x7C, 0xFF, 0xFE, 0xFF, 0xFC, 0xFF, 0xF8, 0x7E,\n  0xF0, 0xFF, 0xFF, 0xF6, 0x66, 0x66, 0x07, 0x0F, 0x1F, 0x1E, 0x3E, 0x3C,\n  0x78, 0x78, 0x78, 0x70, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0,\n  0x78, 0x78, 0x78, 0x3C, 0x3C, 0x1E, 0x1F, 0x0F, 0x07, 0xE0, 0xF0, 0xF8,\n  0x78, 0x7C, 0x3C, 0x3E, 0x1E, 0x1E, 0x1E, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F,\n  0x0F, 0x0F, 0x0E, 0x1E, 0x1E, 0x1E, 0x3C, 0x3C, 0x78, 0xF8, 0xF0, 0xE0,\n  0x01, 0x80, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0xFF, 0xFF,\n  0xFF, 0xFF, 0x7F, 0xFE, 0x1F, 0xF8, 0x07, 0xE0, 0x0F, 0xF0, 0x1F, 0xF8,\n  0x1E, 0x78, 0x1C, 0x38, 0x18, 0x18, 0x01, 0xC0, 0x03, 0xC0, 0x03, 0xC0,\n  0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0,\n  0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x01, 0x80, 0x3E, 0x78, 0xF3, 0xC7,\n  0x8E, 0x1C, 0x70, 0xE1, 0x80, 0x7F, 0xFF, 0xDF, 0xFF, 0xF9, 0xFF, 0xFF,\n  0x3F, 0xFF, 0xE0, 0x77, 0xFF, 0xF7, 0x00, 0x00, 0x0E, 0x00, 0x3C, 0x00,\n  0x78, 0x01, 0xE0, 0x03, 0xC0, 0x07, 0x00, 0x1E, 0x00, 0x38, 0x00, 0xF0,\n  0x01, 0xC0, 0x07, 0x80, 0x0F, 0x00, 0x3C, 0x00, 0x78, 0x01, 0xE0, 0x03,\n  0xC0, 0x0F, 0x00, 0x1E, 0x00, 0x78, 0x00, 0xF0, 0x03, 0xC0, 0x07, 0x80,\n  0x1E, 0x00, 0x3C, 0x00, 0x70, 0x01, 0xE0, 0x03, 0x80, 0x03, 0x00, 0x00,\n  0x07, 0xE0, 0x1F, 0xF8, 0x3F, 0xFC, 0x3F, 0xFC, 0x7C, 0x3E, 0x78, 0x1E,\n  0xF8, 0x1F, 0xF0, 0x0F, 0xF0, 0x0F, 0xF0, 0x0F, 0xF0, 0x0F, 0xF0, 0x0F,\n  0xF0, 0x0F, 0xF0, 0x0F, 0xF0, 0x0F, 0xF0, 0x0F, 0xF8, 0x1F, 0x78, 0x1E,\n  0x7C, 0x3E, 0x3F, 0xFC, 0x3F, 0xFC, 0x1F, 0xF8, 0x07, 0xE0, 0x07, 0xC0,\n  0x1F, 0x80, 0xFF, 0x03, 0xFE, 0x0F, 0xBC, 0x0C, 0x78, 0x00, 0xF0, 0x01,\n  0xE0, 0x03, 0xC0, 0x07, 0x80, 0x0F, 0x00, 0x1E, 0x00, 0x3C, 0x00, 0x78,\n  0x00, 0xF0, 0x01, 0xE0, 0x03, 0xC0, 0x07, 0x81, 0xFF, 0xFB, 0xFF, 0xF7,\n  0xFF, 0xE7, 0xFF, 0x80, 0x0F, 0xC0, 0x7F, 0xE1, 0xFF, 0xE3, 0xFF, 0xEF,\n  0x87, 0xDE, 0x07, 0xF8, 0x07, 0x80, 0x0F, 0x00, 0x1E, 0x00, 0x7C, 0x01,\n  0xF0, 0x07, 0xC0, 0x1F, 0x00, 0x7C, 0x01, 0xF0, 0x07, 0xC0, 0x1F, 0x00,\n  0x78, 0x03, 0xE0, 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x80,\n  0x0F, 0xC0, 0x7F, 0xF0, 0xFF, 0xF8, 0xFF, 0xFC, 0x70, 0x3E, 0x00, 0x1E,\n  0x00, 0x1E, 0x00, 0x1E, 0x00, 0x3C, 0x03, 0xFC, 0x03, 0xF0, 0x03, 0xF0,\n  0x03, 0xFC, 0x00, 0x3E, 0x00, 0x1F, 0x00, 0x0F, 0x00, 0x0F, 0x00, 0x0F,\n  0xE0, 0x3F, 0xFF, 0xFE, 0xFF, 0xFC, 0x7F, 0xF8, 0x1F, 0xE0, 0x00, 0xF8,\n  0x03, 0xF0, 0x07, 0xE0, 0x1F, 0xC0, 0x77, 0x80, 0xEF, 0x03, 0x9E, 0x0F,\n  0x3C, 0x1C, 0x78, 0x70, 0xF1, 0xE1, 0xE3, 0x83, 0xCF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFE, 0x00, 0x78, 0x07, 0xFC, 0x0F, 0xF8, 0x1F, 0xF0,\n  0x1F, 0xC0, 0x3F, 0xFC, 0x1F, 0xFE, 0x0F, 0xFF, 0x07, 0xFF, 0x83, 0xC0,\n  0x01, 0xE0, 0x00, 0xF0, 0x00, 0x7B, 0xE0, 0x3F, 0xFC, 0x1F, 0xFF, 0x0F,\n  0xFF, 0xC3, 0x83, 0xE0, 0x00, 0xF8, 0x00, 0x3C, 0x00, 0x1E, 0x00, 0x0F,\n  0x00, 0x0F, 0xB8, 0x0F, 0xBF, 0xFF, 0xCF, 0xFF, 0xC3, 0xFF, 0xC0, 0x7F,\n  0x80, 0x00, 0xFC, 0x07, 0xFC, 0x3F, 0xF8, 0xFF, 0xF1, 0xF8, 0x07, 0xC0,\n  0x1F, 0x00, 0x3C, 0x00, 0xF0, 0x01, 0xE7, 0xC3, 0xDF, 0xC7, 0x7F, 0xCF,\n  0xFF, 0xDF, 0x8F, 0xFC, 0x07, 0xF0, 0x0F, 0xF0, 0x1F, 0xE0, 0x3D, 0xE0,\n  0xFB, 0xFF, 0xE3, 0xFF, 0xC3, 0xFF, 0x01, 0xF8, 0x00, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0x01, 0xE0, 0x03, 0x80, 0x0F, 0x00, 0x1E,\n  0x00, 0x38, 0x00, 0xF0, 0x01, 0xE0, 0x07, 0x80, 0x0F, 0x00, 0x1E, 0x00,\n  0x78, 0x00, 0xF0, 0x01, 0xE0, 0x07, 0x80, 0x0F, 0x00, 0x1E, 0x00, 0x38,\n  0x00, 0x70, 0x00, 0x07, 0xC0, 0x3F, 0xE0, 0xFF, 0xE3, 0xFF, 0xEF, 0x83,\n  0xFE, 0x03, 0xFC, 0x07, 0xF8, 0x0F, 0xF0, 0x1E, 0xF0, 0x78, 0xFF, 0xE0,\n  0xFF, 0x81, 0xFF, 0x0F, 0xFF, 0x9E, 0x0F, 0x78, 0x0F, 0xF0, 0x1F, 0xE0,\n  0x3F, 0xE0, 0xFB, 0xFF, 0xE7, 0xFF, 0xC7, 0xFF, 0x03, 0xF8, 0x00, 0x0F,\n  0xC0, 0x3F, 0xE0, 0xFF, 0xE3, 0xFF, 0xEF, 0xC3, 0xDF, 0x03, 0xBC, 0x07,\n  0xF8, 0x0F, 0xF0, 0x1F, 0xF0, 0x3D, 0xF1, 0xFB, 0xFF, 0xF3, 0xFE, 0xE3,\n  0xFB, 0xC3, 0xE7, 0x80, 0x1E, 0x00, 0x7C, 0x01, 0xF0, 0x07, 0xE7, 0xFF,\n  0x8F, 0xFE, 0x1F, 0xF0, 0x1F, 0x80, 0x00, 0x77, 0xFF, 0xF7, 0x00, 0x00,\n  0x00, 0x00, 0xEF, 0xFF, 0xEE, 0x1C, 0x7C, 0xF9, 0xF1, 0xC0, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0xF3, 0xC7, 0x8E, 0x3C, 0x70, 0xE1, 0x87, 0x0C, 0x00,\n  0x00, 0x00, 0x00, 0x80, 0x00, 0xF0, 0x00, 0xFC, 0x00, 0xFE, 0x00, 0xFE,\n  0x00, 0xFE, 0x00, 0xFE, 0x00, 0xFE, 0x00, 0x7F, 0x00, 0x07, 0xF0, 0x00,\n  0x7F, 0x00, 0x07, 0xF0, 0x00, 0x7F, 0x00, 0x07, 0xF0, 0x00, 0x7C, 0x00,\n  0x07, 0x7F, 0xFF, 0xDF, 0xFF, 0xF9, 0xFF, 0xFF, 0x3F, 0xFF, 0xE0, 0x00,\n  0x00, 0x00, 0x00, 0x1F, 0xFF, 0xF7, 0xFF, 0xFE, 0x7F, 0xFF, 0xCF, 0xFF,\n  0xF8, 0x00, 0x00, 0x3C, 0x00, 0x0F, 0xC0, 0x01, 0xFC, 0x00, 0x1F, 0xC0,\n  0x01, 0xFC, 0x00, 0x1F, 0xC0, 0x01, 0xFC, 0x00, 0x3F, 0x80, 0x3F, 0x80,\n  0x3F, 0x80, 0x3F, 0x80, 0x3F, 0x80, 0x3F, 0x80, 0x0F, 0x80, 0x03, 0x80,\n  0x00, 0x1F, 0xC0, 0xFF, 0xE3, 0xFF, 0xF7, 0xFF, 0xEF, 0x07, 0xFE, 0x03,\n  0xDC, 0x07, 0x80, 0x0F, 0x00, 0x7C, 0x03, 0xF8, 0x1F, 0xC0, 0x1E, 0x00,\n  0x30, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x1F, 0x00, 0x3E,\n  0x00, 0x7C, 0x00, 0x70, 0x00, 0x07, 0xE0, 0x1F, 0xE0, 0x7F, 0xE1, 0xE1,\n  0xC7, 0x83, 0xCE, 0x03, 0xBC, 0x07, 0x70, 0x0E, 0xE0, 0x7D, 0xC3, 0xFB,\n  0x8F, 0xF7, 0x3C, 0xEE, 0x71, 0xDC, 0xE3, 0xB9, 0xC7, 0x73, 0xCE, 0xE3,\n  0xFF, 0xC3, 0xFF, 0x83, 0xFF, 0x00, 0x07, 0x00, 0x0E, 0x00, 0x1E, 0x02,\n  0x1E, 0x1E, 0x3F, 0xFC, 0x1F, 0xF0, 0x1F, 0x80, 0x0F, 0xF8, 0x00, 0x7F,\n  0xF0, 0x01, 0xFF, 0xC0, 0x03, 0xFF, 0x00, 0x01, 0xFE, 0x00, 0x07, 0xF8,\n  0x00, 0x1C, 0xF0, 0x00, 0xF3, 0xC0, 0x03, 0xCF, 0x00, 0x1E, 0x1E, 0x00,\n  0x78, 0x78, 0x03, 0xC0, 0xF0, 0x0F, 0xFF, 0xC0, 0x3F, 0xFF, 0x01, 0xFF,\n  0xFE, 0x07, 0xFF, 0xF8, 0x3C, 0x00, 0xF3, 0xFC, 0x1F, 0xEF, 0xF8, 0x7F,\n  0xFF, 0xE1, 0xFF, 0x7F, 0x03, 0xF8, 0x7F, 0xFC, 0x0F, 0xFF, 0xF0, 0xFF,\n  0xFF, 0x8F, 0xFF, 0xF8, 0x3C, 0x07, 0xC3, 0xC0, 0x3C, 0x3C, 0x03, 0xC3,\n  0xC0, 0x7C, 0x3F, 0xFF, 0x83, 0xFF, 0xF0, 0x3F, 0xFF, 0x83, 0xFF, 0xFE,\n  0x3C, 0x03, 0xE3, 0xC0, 0x1F, 0x3C, 0x00, 0xF3, 0xC0, 0x0F, 0x3C, 0x01,\n  0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xEF, 0xFF, 0xFC, 0x7F, 0xFF, 0x00, 0x01,\n  0xF8, 0xC1, 0xFF, 0xFC, 0x7F, 0xFF, 0x9F, 0xFF, 0xF7, 0xE0, 0x7E, 0xF8,\n  0x07, 0xFE, 0x00, 0x7F, 0x80, 0x0E, 0xF0, 0x00, 0x1E, 0x00, 0x03, 0xC0,\n  0x00, 0x78, 0x00, 0x0F, 0x00, 0x01, 0xE0, 0x00, 0x3E, 0x00, 0x03, 0xE0,\n  0x07, 0x7F, 0x03, 0xE7, 0xFF, 0xFC, 0x7F, 0xFF, 0x03, 0xFF, 0xC0, 0x1F,\n  0xE0, 0xFF, 0xF0, 0x3F, 0xFF, 0x0F, 0xFF, 0xE3, 0xFF, 0xFC, 0x78, 0x1F,\n  0x9E, 0x03, 0xE7, 0x80, 0x79, 0xE0, 0x0F, 0x78, 0x03, 0xDE, 0x00, 0xF7,\n  0x80, 0x3D, 0xE0, 0x0F, 0x78, 0x03, 0xDE, 0x00, 0xF7, 0x80, 0x7D, 0xE0,\n  0x1E, 0x78, 0x1F, 0xBF, 0xFF, 0xCF, 0xFF, 0xF3, 0xFF, 0xF0, 0x7F, 0xF0,\n  0x00, 0x7F, 0xFF, 0xDF, 0xFF, 0xFB, 0xFF, 0xFF, 0x7F, 0xFF, 0xE3, 0xC0,\n  0x3C, 0x78, 0x07, 0x8F, 0x1C, 0xF1, 0xE3, 0xCC, 0x3F, 0xF8, 0x07, 0xFF,\n  0x00, 0xFF, 0xE0, 0x1F, 0xFC, 0x03, 0xC7, 0x80, 0x78, 0xF1, 0x8F, 0x0C,\n  0x79, 0xE0, 0x0F, 0x3C, 0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xF7, 0xFF, 0xFE, 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xF3, 0xC0, 0x1E, 0x78, 0x63, 0xCF, 0x1E, 0x79, 0xE3, 0xC6, 0x3F, 0xF8,\n  0x07, 0xFF, 0x00, 0xFF, 0xE0, 0x1F, 0xFC, 0x03, 0xC7, 0x80, 0x78, 0xE0,\n  0x0F, 0x00, 0x01, 0xE0, 0x00, 0x3C, 0x00, 0x1F, 0xFC, 0x03, 0xFF, 0x80,\n  0x7F, 0xF0, 0x07, 0xFC, 0x00, 0x01, 0xFC, 0xE0, 0x7F, 0xFE, 0x1F, 0xFF,\n  0xE3, 0xFF, 0xFE, 0x7F, 0x03, 0xE7, 0xC0, 0x1E, 0xF8, 0x00, 0xEF, 0x00,\n  0x00, 0xF0, 0x00, 0x0F, 0x00, 0x00, 0xF0, 0x00, 0x0F, 0x03, 0xFE, 0xF0,\n  0x3F, 0xFF, 0x03, 0xFF, 0xF8, 0x3F, 0xF7, 0x80, 0x1E, 0x7E, 0x01, 0xE3,\n  0xFF, 0xFE, 0x1F, 0xFF, 0xE0, 0xFF, 0xF8, 0x01, 0xFE, 0x00, 0x7F, 0x0F,\n  0xE3, 0xFC, 0x7F, 0x9F, 0xE3, 0xFC, 0x7F, 0x1F, 0xC1, 0xE0, 0x3C, 0x0F,\n  0x01, 0xE0, 0x78, 0x0F, 0x03, 0xC0, 0x78, 0x1E, 0x03, 0xC0, 0xFF, 0xFE,\n  0x07, 0xFF, 0xF0, 0x3F, 0xFF, 0x81, 0xFF, 0xFC, 0x0F, 0x01, 0xE0, 0x78,\n  0x0F, 0x03, 0xC0, 0x78, 0x1E, 0x03, 0xC3, 0xFC, 0x7F, 0xBF, 0xE3, 0xFF,\n  0xFF, 0x1F, 0xF7, 0xF0, 0x7F, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0x07, 0x80, 0x1E, 0x00, 0x78, 0x01, 0xE0, 0x07, 0x80, 0x1E, 0x00,\n  0x78, 0x01, 0xE0, 0x07, 0x80, 0x1E, 0x00, 0x78, 0x01, 0xE0, 0x07, 0x83,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x7F, 0xF8, 0x01, 0xFF, 0xE0, 0x3F, 0xFC,\n  0x07, 0xFF, 0x80, 0xFF, 0xF0, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x03, 0xC0,\n  0x00, 0x78, 0x00, 0x0F, 0x00, 0x01, 0xE0, 0x00, 0x3C, 0x38, 0x07, 0x8F,\n  0x00, 0xF1, 0xE0, 0x1E, 0x3C, 0x03, 0xC7, 0x80, 0xF8, 0xF8, 0x3F, 0x1F,\n  0xFF, 0xC3, 0xFF, 0xF0, 0x1F, 0xFC, 0x00, 0x7E, 0x00, 0xFF, 0x0F, 0xCF,\n  0xF9, 0xFE, 0xFF, 0x9F, 0xEF, 0xF8, 0xFC, 0x3C, 0x1F, 0x03, 0xC3, 0xE0,\n  0x3C, 0x7C, 0x03, 0xCF, 0x80, 0x3D, 0xF0, 0x03, 0xFE, 0x00, 0x3F, 0xF8,\n  0x03, 0xFF, 0x80, 0x3E, 0x7C, 0x03, 0xC3, 0xE0, 0x3C, 0x1E, 0x03, 0xC0,\n  0xF0, 0x3C, 0x0F, 0x0F, 0xF8, 0x7E, 0xFF, 0x87, 0xFF, 0xF8, 0x7F, 0x7F,\n  0x03, 0xE0, 0xFF, 0xC0, 0x3F, 0xF0, 0x0F, 0xFC, 0x03, 0xFF, 0x00, 0x1E,\n  0x00, 0x07, 0x80, 0x01, 0xE0, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x07, 0x80,\n  0x01, 0xE0, 0x00, 0x78, 0x00, 0x1E, 0x01, 0x87, 0x80, 0xF1, 0xE0, 0x3C,\n  0x78, 0x0F, 0x1E, 0x03, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x7F,\n  0xFF, 0xC0, 0x3E, 0x00, 0xF8, 0xFC, 0x01, 0xF9, 0xFC, 0x07, 0xF3, 0xF8,\n  0x0F, 0xE3, 0xF8, 0x3F, 0x87, 0xF0, 0x7F, 0x0F, 0xF1, 0xFE, 0x1F, 0xE3,\n  0xFC, 0x3D, 0xE7, 0x78, 0x7B, 0xDE, 0xF0, 0xF7, 0xBD, 0xE1, 0xE7, 0xF3,\n  0xC3, 0xCF, 0xE7, 0x87, 0x8F, 0x8F, 0x0F, 0x1F, 0x1E, 0x1E, 0x1E, 0x3C,\n  0x3C, 0x00, 0x79, 0xFF, 0x07, 0xFF, 0xFE, 0x0F, 0xFF, 0xFC, 0x1F, 0xF7,\n  0xF0, 0x1F, 0xC0, 0xFC, 0x1F, 0xEF, 0xE1, 0xFF, 0xFE, 0x1F, 0xFF, 0xF1,\n  0xFF, 0x3F, 0x83, 0xC3, 0xF8, 0x3C, 0x3F, 0xC3, 0xC3, 0xFC, 0x3C, 0x3D,\n  0xE3, 0xC3, 0xDE, 0x3C, 0x3C, 0xF3, 0xC3, 0xC7, 0xBC, 0x3C, 0x7B, 0xC3,\n  0xC3, 0xFC, 0x3C, 0x3F, 0xC3, 0xC1, 0xFC, 0x3C, 0x1F, 0xCF, 0xF8, 0xFC,\n  0xFF, 0x87, 0xCF, 0xF8, 0x7C, 0x7F, 0x03, 0xC0, 0x01, 0xF8, 0x00, 0x7F,\n  0xE0, 0x0F, 0xFF, 0x81, 0xFF, 0xFC, 0x3F, 0x0F, 0xC7, 0xC0, 0x3E, 0x78,\n  0x01, 0xEF, 0x80, 0x1F, 0xF0, 0x00, 0xFF, 0x00, 0x0F, 0xF0, 0x00, 0xFF,\n  0x00, 0x0F, 0xF0, 0x00, 0xFF, 0x80, 0x1F, 0x78, 0x01, 0xE7, 0xC0, 0x3E,\n  0x3F, 0x0F, 0xC1, 0xFF, 0xF8, 0x1F, 0xFF, 0x00, 0x7F, 0xE0, 0x01, 0xF8,\n  0x00, 0x7F, 0xF8, 0x3F, 0xFF, 0x8F, 0xFF, 0xF3, 0xFF, 0xFE, 0x3C, 0x0F,\n  0xCF, 0x00, 0xF3, 0xC0, 0x3C, 0xF0, 0x0F, 0x3C, 0x03, 0xCF, 0x03, 0xF3,\n  0xFF, 0xF8, 0xFF, 0xFC, 0x3F, 0xFE, 0x0F, 0xFE, 0x03, 0xC0, 0x00, 0xF0,\n  0x00, 0x3C, 0x00, 0x3F, 0xF8, 0x0F, 0xFE, 0x03, 0xFF, 0x80, 0x7F, 0xC0,\n  0x00, 0x01, 0xF8, 0x00, 0x7F, 0xE0, 0x0F, 0xFF, 0x01, 0xFF, 0xF8, 0x3F,\n  0x0F, 0xC7, 0xC0, 0x3E, 0x78, 0x01, 0xEF, 0x80, 0x1F, 0xF0, 0x00, 0xFF,\n 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0xF7, 0x80, 0x0F, 0x3C,\n  0x38, 0x78, 0xE3, 0xE3, 0x87, 0x1F, 0x1C, 0x38, 0xF8, 0xE1, 0xEF, 0xE7,\n  0x0F, 0x7F, 0x78, 0x7B, 0xBB, 0xC3, 0xFD, 0xFE, 0x0F, 0xEF, 0xF0, 0x7E,\n  0x3F, 0x03, 0xF1, 0xF8, 0x1F, 0x8F, 0xC0, 0xFC, 0x3E, 0x07, 0xC1, 0xF0,\n  0x3E, 0x0F, 0x81, 0xF0, 0x7C, 0x00, 0x7E, 0x0F, 0xDF, 0xE3, 0xFF, 0xFC,\n  0x7F, 0xBF, 0x07, 0xE1, 0xE0, 0xF8, 0x3E, 0x3E, 0x03, 0xEF, 0x80, 0x3D,\n  0xE0, 0x03, 0xF8, 0x00, 0x3E, 0x00, 0x03, 0xC0, 0x00, 0xF8, 0x00, 0x3F,\n  0x80, 0x0F, 0x78, 0x03, 0xC7, 0x80, 0xF8, 0x78, 0x3E, 0x0F, 0x8F, 0xE3,\n  0xFF, 0xFC, 0x7F, 0xFF, 0x8F, 0xF7, 0xE0, 0xFC, 0x7E, 0x07, 0xEF, 0xF0,\n  0xFF, 0xFF, 0x0F, 0xF7, 0xE0, 0x7E, 0x1E, 0x07, 0x81, 0xF0, 0xF8, 0x0F,\n  0x0F, 0x00, 0x79, 0xE0, 0x07, 0xFE, 0x00, 0x3F, 0xC0, 0x01, 0xF8, 0x00,\n  0x0F, 0x00, 0x00, 0xF0, 0x00, 0x0F, 0x00, 0x00, 0xF0, 0x00, 0x0F, 0x00,\n  0x00, 0xF0, 0x00, 0xFF, 0xE0, 0x0F, 0xFF, 0x00, 0xFF, 0xF0, 0x07, 0xFE,\n  0x00, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xF0, 0x3C, 0xF0,\n  0x78, 0xF0, 0xF0, 0x70, 0xE0, 0x01, 0xE0, 0x03, 0xC0, 0x03, 0x80, 0x07,\n  0x00, 0x0F, 0x00, 0x1E, 0x0E, 0x1C, 0x0F, 0x38, 0x0F, 0x78, 0x0F, 0x7F,\n  0xFF, 0x7F, 0xFF, 0x7F, 0xFF, 0x7F, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0xF0,\n  0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0,\n  0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xFE, 0xFF, 0xFF, 0xFE, 0xE0, 0x01,\n  0xE0, 0x03, 0xC0, 0x03, 0xC0, 0x07, 0x80, 0x07, 0x00, 0x0F, 0x00, 0x0E,\n  0x00, 0x1E, 0x00, 0x1C, 0x00, 0x3C, 0x00, 0x78, 0x00, 0x78, 0x00, 0xF0,\n  0x00, 0xF0, 0x01, 0xE0, 0x01, 0xE0, 0x03, 0xC0, 0x03, 0xC0, 0x07, 0x80,\n  0x07, 0x80, 0x0F, 0x00, 0x0F, 0x00, 0x1E, 0x00, 0x1C, 0x00, 0x3C, 0x00,\n  0x38, 0x00, 0x70, 0x7F, 0xFF, 0xFF, 0xFF, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F,\n  0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F,\n  0x0F, 0x0F, 0x7F, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x07, 0x00, 0x1F, 0x00,\n  0x7F, 0x00, 0xFE, 0x03, 0xDE, 0x0F, 0x1E, 0x3E, 0x3E, 0xF8, 0x3F, 0xE0,\n  0x3F, 0x80, 0x38, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xF0, 0xC3, 0x87, 0x0E, 0x1C, 0x30, 0x01, 0xFC, 0x01, 0xFF, 0xC0,\n  0x3F, 0xFC, 0x07, 0xFF, 0xC0, 0x00, 0x78, 0x0F, 0xFF, 0x07, 0xFF, 0xE1,\n  0xFF, 0xFC, 0x7F, 0xFF, 0x9F, 0x80, 0xF3, 0xC0, 0x1E, 0x78, 0x0F, 0xCF,\n  0xFF, 0xFE, 0xFF, 0xFF, 0xCF, 0xFF, 0xF8, 0x7F, 0x3E, 0x7C, 0x00, 0x1F,\n  0x80, 0x03, 0xF0, 0x00, 0x7E, 0x00, 0x03, 0xC0, 0x00, 0x78, 0x00, 0x0F,\n  0x3F, 0x01, 0xFF, 0xF8, 0x3F, 0xFF, 0x87, 0xFF, 0xF0, 0xFC, 0x1F, 0x1F,\n  0x01, 0xF3, 0xC0, 0x1E, 0x78, 0x03, 0xCF, 0x00, 0x79, 0xE0, 0x0F, 0x3E,\n  0x03, 0xE7, 0xE0, 0xFB, 0xFF, 0xFF, 0x7F, 0xFF, 0xCF, 0xFF, 0xF0, 0xF9,\n  0xF8, 0x00, 0x03, 0xF3, 0x87, 0xFF, 0xCF, 0xFF, 0xEF, 0xFF, 0xF7, 0xE0,\n  0xFF, 0xC0, 0x3F, 0xC0, 0x0F, 0xE0, 0x00, 0xF0, 0x00, 0x78, 0x00, 0x3E,\n  0x00, 0x4F, 0x80, 0xF7, 0xFF, 0xF9, 0xFF, 0xF8, 0x7F, 0xF8, 0x0F, 0xF0,\n  0x00, 0x0F, 0xC0, 0x00, 0xFC, 0x00, 0x0F, 0xC0, 0x00, 0xFC, 0x00, 0x03,\n  0xC0, 0x00, 0x3C, 0x03, 0xF3, 0xC0, 0xFF, 0xBC, 0x1F, 0xFF, 0xC3, 0xFF,\n  0xFC, 0x7E, 0x0F, 0xC7, 0x80, 0x7C, 0xF0, 0x03, 0xCF, 0x00, 0x3C, 0xF0,\n  0x03, 0xCF, 0x00, 0x3C, 0xF8, 0x07, 0xC7, 0xE0, 0xFC, 0x7F, 0xFF, 0xF3,\n  0xFF, 0xFF, 0x0F, 0xFF, 0xF0, 0x3F, 0x3E, 0x03, 0xF0, 0x03, 0xFF, 0x01,\n  0xFF, 0xE0, 0xFF, 0xFC, 0x7E, 0x0F, 0x9E, 0x01, 0xEF, 0x00, 0x3F, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xE0, 0x00, 0x7F, 0xFF,\n  0xCF, 0xFF, 0xF1, 0xFF, 0xF8, 0x0F, 0xF0, 0x03, 0xFC, 0x07, 0xFF, 0x0F,\n  0xFF, 0x1F, 0xFF, 0x1E, 0x00, 0x1E, 0x00, 0xFF, 0xF8, 0xFF, 0xFC, 0xFF,\n  0xFC, 0xFF, 0xF8, 0x1E, 0x00, 0x1E, 0x00, 0x1E, 0x00, 0x1E, 0x00, 0x1E,\n  0x00, 0x1E, 0x00, 0x1E, 0x00, 0x1E, 0x00, 0xFF, 0xF8, 0xFF, 0xF8, 0xFF,\n  0xF8, 0xFF, 0xF8, 0x07, 0xE7, 0xC3, 0xFF, 0xFC, 0xFF, 0xFF, 0xBF, 0xFF,\n  0xF7, 0xC1, 0xF9, 0xF0, 0x1F, 0x3C, 0x01, 0xE7, 0x80, 0x3C, 0xF0, 0x07,\n  0x9E, 0x00, 0xF3, 0xE0, 0x3E, 0x3E, 0x0F, 0xC7, 0xFF, 0xF8, 0x7F, 0xFF,\n  0x07, 0xFD, 0xE0, 0x3F, 0x3C, 0x00, 0x07, 0x80, 0x00, 0xF0, 0x00, 0x3E,\n  0x03, 0xFF, 0x80, 0x7F, 0xF0, 0x0F, 0xFC, 0x00, 0xFE, 0x00, 0x3E, 0x00,\n  0x03, 0xF0, 0x00, 0x1F, 0x80, 0x00, 0xFC, 0x00, 0x01, 0xE0, 0x00, 0x0F,\n  0x00, 0x00, 0x78, 0xF8, 0x03, 0xDF, 0xE0, 0x1F, 0xFF, 0x80, 0xFF, 0xFE,\n  0x07, 0xE1, 0xF0, 0x3E, 0x07, 0x81, 0xE0, 0x3C, 0x0F, 0x01, 0xE0, 0x78,\n  0x0F, 0x03, 0xC0, 0x78, 0x1E, 0x03, 0xC0, 0xF0, 0x1E, 0x1F, 0xC1, 0xFD,\n  0xFE, 0x0F, 0xFF, 0xF0, 0x7F, 0xBF, 0x01, 0xF8, 0x03, 0xC0, 0x03, 0xC0,\n  0x03, 0xC0, 0x03, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x3F, 0xC0, 0x3F, 0xC0,\n  0x3F, 0xC0, 0x3F, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0,\n  0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0xFF, 0xFE, 0xFF, 0xFF,\n  0xFF, 0xFF, 0x7F, 0xFE, 0x03, 0xC0, 0x3C, 0x03, 0xC0, 0x3C, 0x00, 0x00,\n  0x00, 0x7F, 0xFF, 0xFF, 0xFF, 0xF7, 0xFF, 0x00, 0xF0, 0x0F, 0x00, 0xF0,\n  0x0F, 0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0x00, 0xF0,\n  0x0F, 0x00, 0xF0, 0x0F, 0x01, 0xFF, 0xFE, 0xFF, 0xEF, 0xFC, 0x7F, 0x00,\n  0x7C, 0x00, 0x3F, 0x00, 0x0F, 0xC0, 0x03, 0xF0, 0x00, 0x3C, 0x00, 0x0F,\n  0x00, 0x03, 0xC7, 0xF0, 0xF3, 0xFC, 0x3C, 0xFF, 0x0F, 0x3F, 0x83, 0xDF,\n  0x00, 0xFF, 0x80, 0x3F, 0xC0, 0x0F, 0xE0, 0x03, 0xFC, 0x00, 0xF7, 0x80,\n  0x3C, 0xF0, 0x0F, 0x1F, 0x0F, 0xC3, 0xFB, 0xF1, 0xFF, 0xFC, 0x7F, 0xDF,\n  0x0F, 0xE0, 0x3F, 0xC0, 0x3F, 0xC0, 0x3F, 0xC0, 0x3F, 0xC0, 0x03, 0xC0,\n  0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0,\n  0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0,\n  0x03, 0xC0, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0x7F, 0xFE, 0x3D, 0xE3,\n  0xC1, 0xFF, 0xFF, 0xC7, 0xFF, 0xFF, 0x1F, 0xFF, 0xFE, 0x3E, 0x3C, 0x78,\n  0xF0, 0xF1, 0xE3, 0xC3, 0xC7, 0x8F, 0x0F, 0x1E, 0x3C, 0x3C, 0x78, 0xF0,\n  0xF1, 0xE3, 0xC3, 0xC7, 0x8F, 0x0F, 0x1E, 0xFE, 0x3E, 0x7F, 0xF8, 0xF9,\n  0xFF, 0xE3, 0xE7, 0xDF, 0x0F, 0x1E, 0x1E, 0x7C, 0x03, 0xEF, 0xF0, 0x3F,\n  0xFF, 0x83, 0xFF, 0xFC, 0x1F, 0x87, 0xC1, 0xE0, 0x3C, 0x1E, 0x03, 0xC1,\n  0xE0, 0x3C, 0x1E, 0x03, 0xC1, 0xE0, 0x3C, 0x1E, 0x03, 0xC1, 0xE0, 0x3C,\n  0x7F, 0x0F, 0xFF, 0xF0, 0xFF, 0xFF, 0x0F, 0xF7, 0xE0, 0x7E, 0x03, 0xF8,\n  0x01, 0xFF, 0xC0, 0x7F, 0xFC, 0x1F, 0xFF, 0xC7, 0xE0, 0xFD, 0xF0, 0x07,\n  0xFC, 0x00, 0x7F, 0x80, 0x0F, 0xF0, 0x01, 0xFE, 0x00, 0x3F, 0xE0, 0x0F,\n  0xBF, 0x07, 0xE3, 0xFF, 0xF8, 0x3F, 0xFE, 0x03, 0xFF, 0x80, 0x1F, 0xC0,\n  0x3E, 0x7E, 0x03, 0xF7, 0xFC, 0x1F, 0xFF, 0xF0, 0xFF, 0xFF, 0xC1, 0xF8,\n  0x3F, 0x0F, 0x80, 0x7C, 0x78, 0x01, 0xE3, 0xC0, 0x0F, 0x1E, 0x00, 0x78,\n  0xF0, 0x03, 0xC7, 0xC0, 0x3E, 0x3F, 0x07, 0xE1, 0xFF, 0xFE, 0x0F, 0xFF,\n  0xE0, 0x7B, 0xFE, 0x03, 0xCF, 0xC0, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x07,\n  0x80, 0x00, 0xFF, 0x80, 0x0F, 0xFC, 0x00, 0x7F, 0xE0, 0x01, 0xFE, 0x00,\n  0x00, 0x03, 0xF3, 0xE0, 0x7F, 0xDF, 0x87, 0xFF, 0xFC, 0x7F, 0xFF, 0xE7,\n  0xE0, 0xFC, 0x7C, 0x03, 0xE3, 0xC0, 0x0F, 0x1E, 0x00, 0x78, 0xF0, 0x03,\n  0xC7, 0x80, 0x1E, 0x3E, 0x01, 0xF0, 0xFC, 0x1F, 0x83, 0xFF, 0xFC, 0x1F,\n  0xFF, 0xE0, 0x3F, 0xEF, 0x00, 0x7E, 0x78, 0x00, 0x03, 0xC0, 0x00, 0x1E,\n  0x00, 0x00, 0xF0, 0x00, 0x3F, 0xE0, 0x01, 0xFF, 0x80, 0x0F, 0xFC, 0x00,\n  0x3F, 0xC0, 0x7E, 0x1E, 0x7F, 0x3F, 0xFF, 0xBF, 0xFF, 0xFF, 0xF1, 0xFE,\n  0x00, 0xFC, 0x00, 0x7C, 0x00, 0x3C, 0x00, 0x1E, 0x00, 0x0F, 0x00, 0x07,\n  0x80, 0x03, 0xC0, 0x0F, 0xFF, 0x87, 0xFF, 0xC3, 0xFF, 0xE1, 0xFF, 0xE0,\n  0x07, 0xE6, 0x1F, 0xFE, 0x7F, 0xFE, 0x7F, 0xFE, 0x78, 0x1E, 0x78, 0x0E,\n  0x7F, 0xE0, 0x3F, 0xFC, 0x03, 0xFE, 0x60, 0x1F, 0xE0, 0x0F, 0xF8, 0x1F,\n  0xFF, 0xFF, 0xFF, 0xFE, 0x7F, 0xFC, 0x07, 0xE0, 0x0C, 0x00, 0x0F, 0x00,\n  0x07, 0x80, 0x03, 0xC0, 0x01, 0xE0, 0x07, 0xFF, 0xF3, 0xFF, 0xF9, 0xFF,\n  0xFC, 0xFF, 0xFC, 0x0F, 0x00, 0x07, 0x80, 0x03, 0xC0, 0x01, 0xE0, 0x00,\n  0xF0, 0x00, 0x78, 0x00, 0x3C, 0x00, 0x1E, 0x07, 0x8F, 0xFF, 0xC3, 0xFF,\n  0xC1, 0xFF, 0xC0, 0x3F, 0x80, 0xFC, 0x1F, 0xBF, 0x0F, 0xEF, 0xC3, 0xFB,\n  0xF0, 0xFE, 0x3C, 0x07, 0x8F, 0x01, 0xE3, 0xC0, 0x78, 0xF0, 0x1E, 0x3C,\n  0x07, 0x8F, 0x01, 0xE3, 0xC0, 0x78, 0xF8, 0x7E, 0x3F, 0xFF, 0xC7, 0xFF,\n  0xF0, 0xFF, 0x7C, 0x0F, 0x9E, 0x7F, 0x07, 0xF7, 0xFC, 0x7F, 0xFF, 0xE3,\n  0xFE, 0xFE, 0x0F, 0xE1, 0xE0, 0x3C, 0x0F, 0x01, 0xE0, 0x3C, 0x1E, 0x01,\n  0xE0, 0xF0, 0x07, 0x8F, 0x00, 0x3E, 0x78, 0x00, 0xF7, 0x80, 0x07, 0xFC,\n  0x00, 0x1F, 0xC0, 0x00, 0xFE, 0x00, 0x03, 0xE0, 0x00, 0x1F, 0x00, 0x7E,\n  0x03, 0xF7, 0xF8, 0x3F, 0xFF, 0xC1, 0xFE, 0xFC, 0x07, 0xF3, 0xC7, 0x0F,\n  0x1E, 0x7C, 0xF0, 0x73, 0xE7, 0x83, 0x9F, 0x7C, 0x1F, 0xFF, 0xC0, 0xFF,\n  0xFE, 0x03, 0xF7, 0xF0, 0x1F, 0xBF, 0x80, 0xFC, 0xF8, 0x07, 0xC7, 0xC0,\n  0x1E, 0x3E, 0x00, 0xE0, 0xE0, 0x7E, 0x0F, 0xDF, 0xE3, 0xFF, 0xFC, 0x7F,\n  0xBF, 0x07, 0xE1, 0xF1, 0xF0, 0x1F, 0xFC, 0x01, 0xFF, 0x00, 0x1F, 0xC0,\n  0x07, 0xF8, 0x01, 0xFF, 0xC0, 0x7E, 0xFC, 0x1F, 0x8F, 0xC7, 0xE0, 0xFD,\n  0xFE, 0x3F, 0xFF, 0xC7, 0xFF, 0xF0, 0x7F, 0x7E, 0x0F, 0xDF, 0xE3, 0xFF,\n  0xFC, 0x7F, 0xBF, 0x07, 0xE3, 0xC0, 0x78, 0x3C, 0x0E, 0x07, 0x83, 0xC0,\n  0x78, 0x70, 0x0F, 0x1E, 0x00, 0xE3, 0x80, 0x1E, 0xF0, 0x01, 0xDC, 0x00,\n  0x3F, 0x80, 0x03, 0xE0, 0x00, 0x7C, 0x00, 0x07, 0x00, 0x01, 0xE0, 0x00,\n  0x38, 0x00, 0x0F, 0x00, 0x3F, 0xF0, 0x0F, 0xFF, 0x01, 0xFF, 0xE0, 0x1F,\n  0xF8, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0xF9, 0xC7,\n  0xC0, 0x3E, 0x01, 0xF0, 0x0F, 0x80, 0x78, 0x03, 0xC0, 0x1E, 0x07, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0x81, 0xF0, 0xFC, 0x7E, 0x1F,\n  0x07, 0x81, 0xE0, 0x78, 0x1E, 0x07, 0x81, 0xE0, 0xF8, 0xFC, 0x3E, 0x0F,\n  0x83, 0xF0, 0x3E, 0x07, 0x81, 0xE0, 0x78, 0x1E, 0x07, 0x81, 0xF0, 0x7E,\n  0x0F, 0xC3, 0xF0, 0x38, 0x6F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0x70, 0x3E, 0x0F, 0xC1, 0xF8, 0x3E,\n  0x07, 0x81, 0xE0, 0x78, 0x1E, 0x07, 0x81, 0xE0, 0x7C, 0x0F, 0xC1, 0xF0,\n  0x7C, 0x3F, 0x1F, 0x07, 0x81, 0xE0, 0x78, 0x1E, 0x07, 0x83, 0xE1, 0xF8,\n  0xFC, 0x3F, 0x07, 0x00, 0x1E, 0x00, 0x1F, 0xC0, 0x1F, 0xF0, 0xDF, 0xFC,\n  0xFF, 0x3F, 0xFB, 0x0F, 0xF8, 0x03, 0xF8, 0x00, 0x78 };\n\nconst GFXglyph FreeMonoBold18pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,  21,    0,    1 },   // 0x20 ' '\n  {     0,   5,  22,  21,    8,  -21 },   // 0x21 '!'\n  {    14,  11,  10,  21,    5,  -20 },   // 0x22 '\"'\n  {    28,  16,  25,  21,    3,  -22 },   // 0x23 '#'\n  {    78,  14,  28,  21,    4,  -23 },   // 0x24 '$'\n  {   127,  15,  21,  21,    3,  -20 },   // 0x25 '%'\n  {   167,  15,  20,  21,    3,  -19 },   // 0x26 '&'\n  {   205,   4,  10,  21,    8,  -20 },   // 0x27 '''\n  {   210,   8,  27,  21,    9,  -21 },   // 0x28 '('\n  {   237,   8,  27,  21,    4,  -21 },   // 0x29 ')'\n  {   264,  16,  15,  21,    3,  -21 },   // 0x2A '*'\n  {   294,  16,  19,  21,    3,  -18 },   // 0x2B '+'\n  {   332,   7,  10,  21,    5,   -3 },   // 0x2C ','\n  {   341,  19,   4,  21,    1,  -11 },   // 0x2D '-'\n  {   351,   5,   5,  21,    8,   -4 },   // 0x2E '.'\n  {   355,  15,  28,  21,    3,  -23 },   // 0x2F '/'\n  {   408,  16,  23,  21,    3,  -22 },   // 0x30 '0'\n  {   454,  15,  22,  21,    3,  -21 },   // 0x31 '1'\n  {   496,  15,  23,  21,    3,  -22 },   // 0x32 '2'\n  {   540,  16,  23,  21,    3,  -22 },   // 0x33 '3'\n  {   586,  15,  21,  21,    3,  -20 },   // 0x34 '4'\n  {   626,  17,  22,  21,    2,  -21 },   // 0x35 '5'\n  {   673,  15,  23,  21,    4,  -22 },   // 0x36 '6'\n  {   717,  15,  22,  21,    3,  -21 },   // 0x37 '7'\n  {   759,  15,  23,  21,    3,  -22 },   // 0x38 '8'\n  {   803,  15,  23,  21,    4,  -22 },   // 0x39 '9'\n  {   847,   5,  16,  21,    8,  -15 },   // 0x3A ':'\n  {   857,   7,  22,  21,    5,  -15 },   // 0x3B ';'\n  {   877,  18,  16,  21,    1,  -17 },   // 0x3C '<'\n  {   913,  19,  10,  21,    1,  -14 },   // 0x3D '='\n  {   937,  18,  16,  21,    2,  -17 },   // 0x3E '>'\n  {   973,  15,  21,  21,    4,  -20 },   // 0x3F '?'\n  {  1013,  15,  27,  21,    3,  -21 },   // 0x40 '@'\n  {  1064,  22,  21,  21,   -1,  -20 },   // 0x41 'A'\n  {  1122,  20,  21,  21,    1,  -20 },   // 0x42 'B'\n  {  1175,  19,  21,  21,    1,  -20 },   // 0x43 'C'\n  {  1225,  18,  21,  21,    2,  -20 },   // 0x44 'D'\n  {  1273,  19,  21,  21,    1,  -20 },   // 0x45 'E'\n  {  1323,  19,  21,  21,    1,  -20 },   // 0x46 'F'\n  {  1373,  20,  21,  21,    1,  -20 },   // 0x47 'G'\n  {  1426,  21,  21,  21,    0,  -20 },   // 0x48 'H'\n  {  1482,  14,  21,  21,    4,  -20 },   // 0x49 'I'\n  {  1519,  19,  21,  21,    2,  -20 },   // 0x4A 'J'\n  {  1569,  20,  21,  21,    1,  -20 },   // 0x4B 'K'\n  {  1622,  18,  21,  21,    2,  -20 },   // 0x4C 'L'\n  {  1670,  23,  21,  21,   -1,  -20 },   // 0x4D 'M'\n  {  1731,  20,  21,  21,    1,  -20 },   // 0x4E 'N'\n  {  1784,  20,  21,  21,    1,  -20 },   // 0x4F 'O'\n  {  1837,  18,  21,  21,    1,  -20 },   // 0x50 'P'\n  {  1885,  20,  26,  21,    1,  -20 },   // 0x51 'Q'\n  {  1950,  21,  21,  21,    0,  -20 },   // 0x52 'R'\n  {  2006,  17,  21,  21,    2,  -20 },   // 0x53 'S'\n  {  2051,  19,  21,  21,    1,  -20 },   // 0x54 'T'\n  {  2101,  21,  21,  21,    0,  -20 },   // 0x55 'U'\n  {  2157,  23,  21,  21,   -1,  -20 },   // 0x56 'V'\n  {  2218,  21,  21,  21,    0,  -20 },   // 0x57 'W'\n  {  2274,  19,  21,  21,    1,  -20 },   // 0x58 'X'\n  {  2324,  20,  21,  21,    1,  -20 },   // 0x59 'Y'\n  {  2377,  16,  21,  21,    3,  -20 },   // 0x5A 'Z'\n  {  2419,   8,  27,  21,    9,  -21 },   // 0x5B '['\n  {  2446,  15,  28,  21,    3,  -23 },   // 0x5C '\\'\n  {  2499,   8,  27,  21,    4,  -21 },   // 0x5D ']'\n  {  2526,  15,  11,  21,    3,  -21 },   // 0x5E '^'\n  {  2547,  21,   4,  21,    0,    4 },   // 0x5F '_'\n  {  2558,   6,   6,  21,    6,  -22 },   // 0x60 '`'\n  {  2563,  19,  16,  21,    1,  -15 },   // 0x61 'a'\n  {  2601,  19,  22,  21,    1,  -21 },   // 0x62 'b'\n  {  2654,  17,  16,  21,    2,  -15 },   // 0x63 'c'\n  {  2688,  20,  22,  21,    1,  -21 },   // 0x64 'd'\n  {  2743,  18,  16,  21,    1,  -15 },   // 0x65 'e'\n  {  2779,  16,  22,  21,    4,  -21 },   // 0x66 'f'\n  {  2823,  19,  23,  21,    1,  -15 },   // 0x67 'g'\n  {  2878,  21,  22,  21,    0,  -21 },   // 0x68 'h'\n  {  2936,  16,  22,  21,    3,  -21 },   // 0x69 'i'\n  {  2980,  12,  29,  21,    5,  -21 },   // 0x6A 'j'\n  {  3024,  18,  22,  21,    2,  -21 },   // 0x6B 'k'\n  {  3074,  16,  22,  21,    3,  -21 },   // 0x6C 'l'\n  {  3118,  22,  16,  21,   -1,  -15 },   // 0x6D 'm'\n  {  3162,  20,  16,  21,    0,  -15 },   // 0x6E 'n'\n  {  3202,  19,  16,  21,    1,  -15 },   // 0x6F 'o'\n  {  3240,  21,  23,  21,    0,  -15 },   // 0x70 'p'\n  {  3301,  21,  23,  22,    1,  -15 },   // 0x71 'q'\n  {  3362,  17,  16,  21,    3,  -15 },   // 0x72 'r'\n  {  3396,  16,  16,  21,    3,  -15 },   // 0x73 's'\n  {  3428,  17,  21,  21,    1,  -20 },   // 0x74 't'\n  {  3473,  18,  16,  21,    1,  -15 },   // 0x75 'u'\n  {  3509,  21,  16,  21,    0,  -15 },   // 0x76 'v'\n  {  3551,  21,  16,  21,    0,  -15 },   // 0x77 'w'\n  {  3593,  19,  16,  21,    1,  -15 },   // 0x78 'x'\n  {  3631,  19,  23,  21,    1,  -15 },   // 0x79 'y'\n  {  3686,  14,  16,  21,    3,  -15 },   // 0x7A 'z'\n  {  3714,  10,  27,  21,    6,  -21 },   // 0x7B '{'\n  {  3748,   4,  27,  21,    9,  -21 },   // 0x7C '|'\n  {  3762,  10,  27,  21,    6,  -21 },   // 0x7D '}'\n  {  3796,  17,   8,  21,    2,  -13 } }; // 0x7E '~'\n\nconst GFXfont FreeMonoBold18pt7b PROGMEM = {\n  (uint8_t  *)FreeMonoBold18pt7bBitmaps,\n  (GFXglyph *)FreeMonoBold18pt7bGlyphs,\n  0x20, 0x7E, 35 };\n\n// Approx. 4485 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeMonoBold24pt7b.h",
    "content": "const uint8_t FreeMonoBold24pt7bBitmaps[] PROGMEM = {\n  0x38, 0xFB, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xF3, 0xE7, 0xCF,\n  0x9F, 0x3E, 0x7C, 0xF9, 0xF3, 0xE3, 0x82, 0x00, 0x00, 0x00, 0x71, 0xF7,\n  0xFF, 0xEF, 0x9E, 0x00, 0xFC, 0x7E, 0xF8, 0x7D, 0xF0, 0xFB, 0xE1, 0xF7,\n  0xC3, 0xEF, 0x87, 0xDF, 0x0F, 0xBE, 0x1F, 0x38, 0x1C, 0x70, 0x38, 0xE0,\n  0x71, 0xC0, 0xE3, 0x81, 0xC7, 0x03, 0x80, 0x01, 0xC1, 0xC0, 0x0F, 0x8F,\n  0x80, 0x3E, 0x3E, 0x00, 0xF8, 0xF8, 0x03, 0xE3, 0xE0, 0x0F, 0x8F, 0x80,\n  0x7E, 0x3E, 0x01, 0xF0, 0xF8, 0x07, 0xC7, 0xC0, 0x1F, 0x1F, 0x03, 0xFF,\n  0xFF, 0x9F, 0xFF, 0xFF, 0x7F, 0xFF, 0xFD, 0xFF, 0xFF, 0xF3, 0xFF, 0xFF,\n  0x81, 0xF1, 0xF0, 0x07, 0xC7, 0xC0, 0x1F, 0x1F, 0x00, 0x7C, 0x7C, 0x1F,\n  0xFF, 0xFC, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF, 0xEF, 0xFF, 0xFF, 0x9F, 0xFF,\n  0xFC, 0x0F, 0x8F, 0x80, 0x3E, 0x3E, 0x00, 0xF8, 0xF8, 0x03, 0xE3, 0xE0,\n  0x0F, 0x8F, 0x80, 0x3E, 0x3E, 0x00, 0xF8, 0xF8, 0x03, 0xE3, 0xE0, 0x0F,\n  0x8F, 0x80, 0x3C, 0x3C, 0x00, 0x00, 0xE0, 0x00, 0x3E, 0x00, 0x07, 0xC0,\n  0x00, 0xF8, 0x00, 0x1F, 0x00, 0x1F, 0xFF, 0x07, 0xFF, 0xF1, 0xFF, 0xFE,\n  0x7F, 0xFF, 0xDF, 0xC1, 0xFB, 0xF0, 0x1F, 0x7C, 0x01, 0xEF, 0x80, 0x39,\n  0xF8, 0x00, 0x3F, 0xF8, 0x03, 0xFF, 0xE0, 0x3F, 0xFF, 0x03, 0xFF, 0xF0,\n  0x0F, 0xFF, 0x00, 0x1F, 0xE0, 0x00, 0x7F, 0xC0, 0x07, 0xF8, 0x00, 0xFF,\n  0x80, 0x1F, 0xF8, 0x07, 0xFF, 0x81, 0xFB, 0xFF, 0xFF, 0x7F, 0xFF, 0xCF,\n  0xFF, 0xF1, 0xDF, 0xFC, 0x00, 0x7C, 0x00, 0x0F, 0x80, 0x01, 0xF0, 0x00,\n  0x3E, 0x00, 0x07, 0xC0, 0x00, 0xF8, 0x00, 0x1F, 0x00, 0x01, 0xC0, 0x00,\n  0x0F, 0x80, 0x00, 0xFF, 0x00, 0x1F, 0xFC, 0x00, 0xF0, 0xE0, 0x0F, 0x07,\n  0x80, 0x70, 0x1C, 0x03, 0x80, 0xE0, 0x1C, 0x07, 0x00, 0xF0, 0x78, 0x03,\n  0xC3, 0x80, 0x1F, 0xFC, 0x00, 0x7F, 0xC1, 0xF0, 0xF8, 0x7F, 0x00, 0x3F,\n  0xF0, 0x0F, 0xFC, 0x03, 0xFF, 0x00, 0xFF, 0xC0, 0x07, 0xE0, 0xF8, 0x38,\n  0x1F, 0xE0, 0x01, 0xFF, 0x80, 0x0F, 0x1E, 0x00, 0xF0, 0x78, 0x07, 0x01,\n  0xC0, 0x38, 0x0E, 0x01, 0xC0, 0x70, 0x0F, 0x07, 0x80, 0x38, 0x78, 0x01,\n  0xFF, 0xC0, 0x07, 0xF8, 0x00, 0x0F, 0x80, 0x00, 0xF8, 0x00, 0x1F, 0xFC,\n  0x01, 0xFF, 0xE0, 0x1F, 0xFF, 0x00, 0xFF, 0xF8, 0x0F, 0xC7, 0x00, 0x7C,\n  0x10, 0x03, 0xE0, 0x00, 0x1F, 0x00, 0x00, 0xFC, 0x00, 0x03, 0xF0, 0x00,\n  0x1F, 0x80, 0x00, 0xFE, 0x00, 0x0F, 0xF8, 0x00, 0xFF, 0xC7, 0xCF, 0xFF,\n  0x3F, 0x7E, 0xFF, 0xFF, 0xE7, 0xFF, 0xBE, 0x1F, 0xF9, 0xF0, 0x7F, 0x8F,\n  0x83, 0xFC, 0x7C, 0x0F, 0xE3, 0xF0, 0x7F, 0xCF, 0xFF, 0xFF, 0x7F, 0xFF,\n  0xF9, 0xFF, 0xFF, 0xC7, 0xFF, 0xFC, 0x0F, 0xE0, 0x00, 0xFD, 0xF7, 0xDF,\n  0x7D, 0xF7, 0xDF, 0x38, 0xE3, 0x8E, 0x38, 0xE0, 0x01, 0x80, 0xF0, 0x7C,\n  0x3F, 0x0F, 0xC7, 0xE1, 0xF8, 0xFC, 0x3E, 0x0F, 0x87, 0xC1, 0xF0, 0x7C,\n  0x1F, 0x0F, 0x83, 0xE0, 0xF8, 0x3E, 0x0F, 0x83, 0xE0, 0xF8, 0x3E, 0x0F,\n  0x81, 0xF0, 0x7C, 0x1F, 0x07, 0xC0, 0xF8, 0x3E, 0x0F, 0xC1, 0xF0, 0x7E,\n  0x0F, 0x83, 0xF0, 0x7C, 0x1F, 0x03, 0xC0, 0x60, 0x3C, 0x0F, 0x83, 0xF0,\n  0xFC, 0x1F, 0x83, 0xE0, 0xFC, 0x1F, 0x07, 0xC1, 0xF8, 0x3E, 0x0F, 0x83,\n  0xE0, 0x7C, 0x1F, 0x07, 0xC1, 0xF0, 0x7C, 0x1F, 0x07, 0xC1, 0xF0, 0x7C,\n  0x1E, 0x0F, 0x83, 0xE0, 0xF8, 0x7C, 0x1F, 0x0F, 0xC3, 0xE1, 0xF8, 0x7C,\n  0x3F, 0x0F, 0x83, 0xE0, 0xF0, 0x00, 0x00, 0x70, 0x00, 0x07, 0xC0, 0x00,\n  0x3E, 0x00, 0x01, 0xF0, 0x00, 0x0F, 0x80, 0x10, 0x7C, 0x11, 0xF3, 0xE7,\n  0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF, 0x87, 0xFF, 0xF0, 0x07,\n  0xFC, 0x00, 0x3F, 0xE0, 0x03, 0xFF, 0x80, 0x3F, 0x7E, 0x01, 0xFB, 0xF0,\n  0x1F, 0x8F, 0xC0, 0xF8, 0x3E, 0x03, 0x80, 0xE0, 0x00, 0x38, 0x00, 0x00,\n  0xF8, 0x00, 0x01, 0xF0, 0x00, 0x03, 0xE0, 0x00, 0x07, 0xC0, 0x00, 0x0F,\n  0x80, 0x00, 0x1F, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x7C, 0x00, 0x00, 0xF8,\n  0x01, 0xFF, 0xFF, 0xF7, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xDF, 0xFF, 0xFF, 0x00, 0x3E, 0x00, 0x00, 0x7C, 0x00, 0x00, 0xF8, 0x00,\n  0x01, 0xF0, 0x00, 0x03, 0xE0, 0x00, 0x07, 0xC0, 0x00, 0x0F, 0x80, 0x00,\n  0x1F, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x70, 0x00, 0x1F,\n  0x8F, 0x87, 0xC7, 0xC3, 0xE1, 0xE1, 0xF0, 0xF0, 0x78, 0x38, 0x3C, 0x1C,\n  0x0E, 0x06, 0x00, 0x7F, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0x7F, 0xFF, 0xFE, 0x7D, 0xFF, 0xFF, 0xFF, 0xEF, 0x80,\n  0x00, 0x00, 0x60, 0x00, 0x0F, 0x00, 0x01, 0xF0, 0x00, 0x1F, 0x00, 0x01,\n  0xF0, 0x00, 0x3E, 0x00, 0x03, 0xE0, 0x00, 0x7C, 0x00, 0x07, 0xC0, 0x00,\n  0xF8, 0x00, 0x0F, 0x80, 0x01, 0xF0, 0x00, 0x1F, 0x00, 0x03, 0xE0, 0x00,\n  0x3E, 0x00, 0x07, 0xC0, 0x00, 0x7C, 0x00, 0x0F, 0xC0, 0x00, 0xF8, 0x00,\n  0x1F, 0x80, 0x01, 0xF0, 0x00, 0x3F, 0x00, 0x03, 0xE0, 0x00, 0x3E, 0x00,\n  0x07, 0xC0, 0x00, 0x7C, 0x00, 0x0F, 0x80, 0x00, 0xF8, 0x00, 0x1F, 0x00,\n  0x01, 0xF0, 0x00, 0x3E, 0x00, 0x03, 0xE0, 0x00, 0x7C, 0x00, 0x07, 0xC0,\n  0x00, 0xFC, 0x00, 0x0F, 0x80, 0x00, 0xF8, 0x00, 0x0F, 0x00, 0x00, 0x01,\n  0xFC, 0x00, 0x3F, 0xF8, 0x03, 0xFF, 0xE0, 0x3F, 0xFF, 0x83, 0xFF, 0xFE,\n  0x1F, 0x83, 0xF1, 0xF8, 0x0F, 0xCF, 0x80, 0x3E, 0x7C, 0x01, 0xF7, 0xC0,\n  0x07, 0xFE, 0x00, 0x3F, 0xF0, 0x01, 0xFF, 0x80, 0x0F, 0xFC, 0x00, 0x7F,\n  0xE0, 0x03, 0xFF, 0x00, 0x1F, 0xF8, 0x00, 0xFF, 0xC0, 0x07, 0xFE, 0x00,\n  0x3F, 0xF0, 0x01, 0xFF, 0x80, 0x0F, 0xFC, 0x00, 0x7D, 0xF0, 0x07, 0xCF,\n  0x80, 0x3E, 0x7E, 0x03, 0xF1, 0xF8, 0x3F, 0x0F, 0xFF, 0xF8, 0x3F, 0xFF,\n  0x80, 0xFF, 0xF8, 0x03, 0xFF, 0x80, 0x07, 0xF0, 0x00, 0x01, 0xF8, 0x00,\n  0x3F, 0x80, 0x0F, 0xF8, 0x01, 0xFF, 0x80, 0x7F, 0xF8, 0x0F, 0xEF, 0x80,\n  0xFC, 0xF8, 0x07, 0x0F, 0x80, 0x00, 0xF8, 0x00, 0x0F, 0x80, 0x00, 0xF8,\n  0x00, 0x0F, 0x80, 0x00, 0xF8, 0x00, 0x0F, 0x80, 0x00, 0xF8, 0x00, 0x0F,\n  0x80, 0x00, 0xF8, 0x00, 0x0F, 0x80, 0x00, 0xF8, 0x00, 0x0F, 0x80, 0x00,\n  0xF8, 0x00, 0x0F, 0x80, 0x00, 0xF8, 0x00, 0x0F, 0x80, 0x3F, 0xFF, 0xE7,\n  0xFF, 0xFF, 0x7F, 0xFF, 0xF7, 0xFF, 0xFF, 0x3F, 0xFF, 0xE0, 0x01, 0xFC,\n  0x00, 0x3F, 0xF8, 0x07, 0xFF, 0xF0, 0x7F, 0xFF, 0xC7, 0xFF, 0xFF, 0x3F,\n  0x03, 0xFB, 0xF0, 0x07, 0xFF, 0x00, 0x1F, 0xF8, 0x00, 0xFB, 0x80, 0x07,\n  0xC0, 0x00, 0x3E, 0x00, 0x03, 0xF0, 0x00, 0x3F, 0x00, 0x03, 0xF8, 0x00,\n  0x3F, 0x80, 0x03, 0xF8, 0x00, 0x3F, 0x80, 0x03, 0xF8, 0x00, 0x3F, 0x00,\n  0x07, 0xF0, 0x00, 0x7F, 0x00, 0x07, 0xF0, 0x00, 0x7F, 0x00, 0x07, 0xE0,\n  0x0E, 0xFE, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0x03, 0xF8, 0x00, 0xFF, 0xF8, 0x0F, 0xFF,\n  0xE0, 0xFF, 0xFF, 0x8F, 0xFF, 0xFE, 0x7E, 0x03, 0xF1, 0xC0, 0x0F, 0xC0,\n  0x00, 0x3E, 0x00, 0x01, 0xF0, 0x00, 0x0F, 0x80, 0x00, 0xFC, 0x00, 0x0F,\n  0xC0, 0x0F, 0xFC, 0x00, 0xFF, 0xC0, 0x07, 0xFC, 0x00, 0x3F, 0xF0, 0x00,\n  0xFF, 0xC0, 0x00, 0x7F, 0x00, 0x00, 0xFC, 0x00, 0x03, 0xF0, 0x00, 0x0F,\n  0x80, 0x00, 0x7C, 0x00, 0x03, 0xE0, 0x00, 0x1F, 0x00, 0x01, 0xFF, 0xC0,\n  0x3F, 0xBF, 0xFF, 0xFD, 0xFF, 0xFF, 0xC7, 0xFF, 0xFC, 0x1F, 0xFF, 0xC0,\n  0x1F, 0xF0, 0x00, 0x00, 0x3F, 0x80, 0x03, 0xF8, 0x00, 0x7F, 0x80, 0x07,\n  0xF8, 0x00, 0xFF, 0x80, 0x1F, 0xF8, 0x01, 0xEF, 0x80, 0x3E, 0xF8, 0x03,\n  0xCF, 0x80, 0x7C, 0xF8, 0x0F, 0x8F, 0x80, 0xF0, 0xF8, 0x1F, 0x0F, 0x81,\n  0xE0, 0xF8, 0x3E, 0x0F, 0x87, 0xC0, 0xF8, 0x78, 0x0F, 0x8F, 0xFF, 0xFE,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0x00, 0x0F,\n  0x80, 0x07, 0xFE, 0x00, 0xFF, 0xF0, 0x0F, 0xFF, 0x00, 0xFF, 0xF0, 0x07,\n  0xFE, 0x3F, 0xFF, 0xC1, 0xFF, 0xFF, 0x0F, 0xFF, 0xF8, 0x7F, 0xFF, 0xC3,\n  0xFF, 0xFC, 0x1F, 0x00, 0x00, 0xF8, 0x00, 0x07, 0xC0, 0x00, 0x3E, 0x00,\n  0x01, 0xF0, 0x00, 0x0F, 0xBF, 0x00, 0x7F, 0xFF, 0x03, 0xFF, 0xFC, 0x1F,\n  0xFF, 0xF0, 0xFF, 0xFF, 0x83, 0xC0, 0xFE, 0x00, 0x01, 0xF0, 0x00, 0x0F,\n  0xC0, 0x00, 0x3E, 0x00, 0x01, 0xF0, 0x00, 0x0F, 0x80, 0x00, 0x7C, 0x00,\n  0x03, 0xE0, 0x00, 0x3F, 0xF0, 0x03, 0xF7, 0xE0, 0x3F, 0xBF, 0xFF, 0xF9,\n  0xFF, 0xFF, 0xC7, 0xFF, 0xFC, 0x1F, 0xFF, 0x80, 0x1F, 0xF0, 0x00, 0x00,\n  0x1F, 0xC0, 0x0F, 0xFF, 0x01, 0xFF, 0xF0, 0x7F, 0xFF, 0x0F, 0xFF, 0xE1,\n  0xFF, 0x00, 0x1F, 0xC0, 0x03, 0xF0, 0x00, 0x7E, 0x00, 0x07, 0xE0, 0x00,\n  0x7C, 0x00, 0x0F, 0x8F, 0xC0, 0xF9, 0xFF, 0x0F, 0xFF, 0xF8, 0xFF, 0xFF,\n  0xCF, 0xFF, 0xFC, 0xFF, 0x0F, 0xEF, 0xE0, 0x3E, 0xFC, 0x03, 0xFF, 0x80,\n  0x1F, 0xF8, 0x01, 0xFF, 0x80, 0x1F, 0xF8, 0x01, 0xF7, 0xC0, 0x3F, 0x7E,\n  0x03, 0xF3, 0xF0, 0x7E, 0x3F, 0xFF, 0xE1, 0xFF, 0xFC, 0x0F, 0xFF, 0x80,\n  0x7F, 0xF0, 0x01, 0xFC, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x1F, 0xF0, 0x03, 0xE0, 0x00,\n  0x3E, 0x00, 0x03, 0xE0, 0x00, 0x7C, 0x00, 0x07, 0xC0, 0x00, 0x7C, 0x00,\n  0x0F, 0x80, 0x00, 0xF8, 0x00, 0x0F, 0x80, 0x01, 0xF0, 0x00, 0x1F, 0x00,\n  0x01, 0xF0, 0x00, 0x3E, 0x00, 0x03, 0xE0, 0x00, 0x3E, 0x00, 0x07, 0xC0,\n  0x00, 0x7C, 0x00, 0x07, 0xC0, 0x00, 0xF8, 0x00, 0x0F, 0x80, 0x00, 0xF8,\n  0x00, 0x0F, 0x00, 0x00, 0xF0, 0x00, 0x06, 0x00, 0x01, 0xF8, 0x00, 0xFF,\n  0xF0, 0x1F, 0xFF, 0x83, 0xFF, 0xFC, 0x7F, 0xFF, 0xE7, 0xE0, 0x7E, 0xFC,\n  0x03, 0xFF, 0x80, 0x1F, 0xF8, 0x01, 0xFF, 0x80, 0x1F, 0xF8, 0x01, 0xF7,\n  0xC0, 0x3E, 0x7E, 0x07, 0xE3, 0xFF, 0xFC, 0x0F, 0xFF, 0x00, 0xFF, 0xF0,\n  0x1F, 0xFF, 0x83, 0xFF, 0xFC, 0x7F, 0x0F, 0xE7, 0xC0, 0x3E, 0xF8, 0x01,\n  0xFF, 0x80, 0x1F, 0xF8, 0x01, 0xFF, 0x80, 0x1F, 0xFC, 0x03, 0xF7, 0xE0,\n  0x7E, 0x7F, 0xFF, 0xE3, 0xFF, 0xFC, 0x1F, 0xFF, 0x80, 0xFF, 0xF0, 0x03,\n  0xFC, 0x00, 0x03, 0xF8, 0x00, 0xFF, 0xE0, 0x1F, 0xFF, 0x83, 0xFF, 0xF8,\n  0x7F, 0xFF, 0xC7, 0xE0, 0xFE, 0xFC, 0x03, 0xEF, 0x80, 0x3E, 0xF8, 0x01,\n  0xFF, 0x80, 0x1F, 0xF8, 0x01, 0xFF, 0x80, 0x3F, 0xFC, 0x07, 0xF7, 0xE0,\n  0xFF, 0x7F, 0xFF, 0xF3, 0xFF, 0xFF, 0x1F, 0xFF, 0xF0, 0xFF, 0x9F, 0x03,\n  0xF1, 0xF0, 0x00, 0x3F, 0x00, 0x03, 0xE0, 0x00, 0x7E, 0x00, 0x0F, 0xC0,\n  0x01, 0xFC, 0x00, 0x3F, 0x80, 0x0F, 0xF0, 0x7F, 0xFE, 0x0F, 0xFF, 0xC0,\n  0xFF, 0xF8, 0x0F, 0xFF, 0x00, 0x3F, 0x80, 0x00, 0x7D, 0xFF, 0xFF, 0xFF,\n  0xEF, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7D, 0xFF,\n  0xFF, 0xFF, 0xEF, 0x80, 0x0F, 0x87, 0xF1, 0xFC, 0x7F, 0x1F, 0xC3, 0xE0,\n  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,\n  0x1F, 0x87, 0xE1, 0xF0, 0xFC, 0x3E, 0x0F, 0x03, 0xC1, 0xE0, 0x78, 0x1C,\n  0x07, 0x01, 0x80, 0x00, 0x00, 0x04, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x7F,\n  0x00, 0x01, 0xFE, 0x00, 0x07, 0xFC, 0x00, 0x1F, 0xF0, 0x00, 0x7F, 0xC0,\n  0x01, 0xFF, 0x00, 0x07, 0xFE, 0x00, 0x1F, 0xF8, 0x00, 0x7F, 0xE0, 0x00,\n  0xFF, 0xE0, 0x00, 0x1F, 0xF8, 0x00, 0x07, 0xFE, 0x00, 0x01, 0xFF, 0x80,\n  0x00, 0x7F, 0xE0, 0x00, 0x1F, 0xF8, 0x00, 0x07, 0xFC, 0x00, 0x01, 0xFE,\n  0x00, 0x00, 0x7F, 0x00, 0x00, 0x1E, 0x7F, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x7F, 0xFF, 0xFE, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7F, 0xFF, 0xFE,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x7F, 0xFF, 0xFE,\n  0x00, 0x00, 0x01, 0xE0, 0x00, 0x03, 0xF0, 0x00, 0x07, 0xF8, 0x00, 0x07,\n  0xFC, 0x00, 0x03, 0xFE, 0x00, 0x01, 0xFF, 0x00, 0x00, 0xFF, 0x80, 0x00,\n  0x7F, 0xC0, 0x00, 0x7F, 0xE0, 0x00, 0x3F, 0xF0, 0x00, 0x3F, 0xF0, 0x01,\n  0xFF, 0x00, 0x0F, 0xF8, 0x00, 0x7F, 0xC0, 0x03, 0xFE, 0x00, 0x1F, 0xF0,\n  0x00, 0xFF, 0x80, 0x03, 0xFC, 0x00, 0x07, 0xE0, 0x00, 0x0F, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0x03, 0xF8, 0x01, 0xFF, 0xF0, 0xFF, 0xFF, 0x8F,\n  0xFF, 0xFC, 0xFF, 0xFF, 0xEF, 0xC0, 0x7E, 0xF8, 0x03, 0xFF, 0x80, 0x1F,\n  0x70, 0x01, 0xF0, 0x00, 0x1F, 0x00, 0x03, 0xF0, 0x00, 0x7E, 0x00, 0x3F,\n  0xE0, 0x0F, 0xFC, 0x01, 0xFF, 0x00, 0x0F, 0xC0, 0x00, 0xF0, 0x00, 0x0F,\n  0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x1F, 0x00, 0x03, 0xF8, 0x00, 0x3F, 0x80, 0x03, 0xF8, 0x00,\n  0x3F, 0x80, 0x01, 0xF0, 0x00, 0x01, 0xF0, 0x00, 0xFF, 0x80, 0x3F, 0xF8,\n  0x0F, 0xFF, 0x83, 0xE0, 0xF8, 0x78, 0x07, 0x1E, 0x00, 0xF3, 0x80, 0x0E,\n  0x70, 0x01, 0xDE, 0x00, 0x3B, 0x80, 0x3F, 0x70, 0x1F, 0xEE, 0x07, 0xFD,\n  0xC1, 0xFF, 0xB8, 0x7E, 0x77, 0x0F, 0x0E, 0xE3, 0xC1, 0xDC, 0x70, 0x3B,\n  0x8E, 0x07, 0x71, 0xC0, 0xEE, 0x3C, 0x1D, 0xC3, 0xC3, 0xB8, 0x7F, 0xF7,\n  0x07, 0xFF, 0xE0, 0x7F, 0xFC, 0x03, 0xFB, 0xC0, 0x00, 0x38, 0x00, 0x07,\n  0x00, 0x00, 0xF0, 0x00, 0x0F, 0x00, 0x61, 0xF0, 0x3E, 0x1F, 0xFF, 0xC3,\n  0xFF, 0xF0, 0x1F, 0xFC, 0x01, 0xFC, 0x00, 0x07, 0xFF, 0x80, 0x00, 0x7F,\n  0xFE, 0x00, 0x03, 0xFF, 0xF0, 0x00, 0x1F, 0xFF, 0xC0, 0x00, 0x7F, 0xFE,\n  0x00, 0x00, 0x1F, 0xF0, 0x00, 0x01, 0xF7, 0xC0, 0x00, 0x0F, 0xBE, 0x00,\n  0x00, 0x7D, 0xF8, 0x00, 0x07, 0xC7, 0xC0, 0x00, 0x3E, 0x3E, 0x00, 0x03,\n  0xE0, 0xF8, 0x00, 0x1F, 0x07, 0xC0, 0x00, 0xF0, 0x3F, 0x00, 0x0F, 0x80,\n  0xF8, 0x00, 0x7F, 0xFF, 0xC0, 0x07, 0xFF, 0xFF, 0x00, 0x3F, 0xFF, 0xF8,\n  0x03, 0xFF, 0xFF, 0xE0, 0x1F, 0xFF, 0xFF, 0x00, 0xF8, 0x00, 0xF8, 0x0F,\n  0x80, 0x03, 0xE1, 0xFF, 0x80, 0xFF, 0xDF, 0xFE, 0x0F, 0xFF, 0xFF, 0xF0,\n  0x7F, 0xFF, 0xFF, 0x83, 0xFF, 0xDF, 0xF8, 0x0F, 0xFC, 0x7F, 0xFF, 0xC0,\n  0x3F, 0xFF, 0xFC, 0x0F, 0xFF, 0xFF, 0xC3, 0xFF, 0xFF, 0xF8, 0x7F, 0xFF,\n  0xFE, 0x07, 0xC0, 0x1F, 0xC1, 0xF0, 0x01, 0xF0, 0x7C, 0x00, 0x7C, 0x1F,\n  0x00, 0x1F, 0x07, 0xC0, 0x0F, 0xC1, 0xF0, 0x07, 0xE0, 0x7F, 0xFF, 0xF0,\n  0x1F, 0xFF, 0xF8, 0x07, 0xFF, 0xFF, 0x01, 0xFF, 0xFF, 0xE0, 0x7F, 0xFF,\n  0xFC, 0x1F, 0x00, 0x3F, 0x87, 0xC0, 0x03, 0xF1, 0xF0, 0x00, 0x7C, 0x7C,\n  0x00, 0x1F, 0x1F, 0x00, 0x07, 0xC7, 0xC0, 0x03, 0xF7, 0xFF, 0xFF, 0xFB,\n  0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0x3F, 0xFF, 0xFF, 0x87, 0xFF, 0xFF,\n  0x00, 0x00, 0x7F, 0x00, 0x00, 0xFF, 0xE7, 0x01, 0xFF, 0xFF, 0xC1, 0xFF,\n  0xFF, 0xE1, 0xFF, 0xFF, 0xF1, 0xFE, 0x07, 0xF8, 0xFC, 0x01, 0xFC, 0xFC,\n  0x00, 0x7E, 0x7C, 0x00, 0x1F, 0x7E, 0x00, 0x0F, 0xBE, 0x00, 0x03, 0x9F,\n  0x00, 0x00, 0x0F, 0x80, 0x00, 0x07, 0xC0, 0x00, 0x03, 0xE0, 0x00, 0x01,\n  0xF0, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x3E, 0x00, 0x00,\n  0x1F, 0x80, 0x00, 0x07, 0xC0, 0x00, 0x03, 0xF0, 0x00, 0x39, 0xFC, 0x00,\n  0x7C, 0x7F, 0x80, 0xFF, 0x1F, 0xFF, 0xFF, 0x07, 0xFF, 0xFF, 0x81, 0xFF,\n  0xFF, 0x00, 0x3F, 0xFF, 0x00, 0x07, 0xFC, 0x00, 0x7F, 0xFF, 0x00, 0x7F,\n  0xFF, 0xF0, 0x3F, 0xFF, 0xFC, 0x1F, 0xFF, 0xFF, 0x07, 0xFF, 0xFF, 0xC1,\n  0xF0, 0x0F, 0xF0, 0xF8, 0x01, 0xF8, 0x7C, 0x00, 0x7E, 0x3E, 0x00, 0x1F,\n  0x1F, 0x00, 0x0F, 0xCF, 0x80, 0x03, 0xE7, 0xC0, 0x01, 0xF3, 0xE0, 0x00,\n  0xF9, 0xF0, 0x00, 0x7C, 0xF8, 0x00, 0x3E, 0x7C, 0x00, 0x1F, 0x3E, 0x00,\n  0x0F, 0x9F, 0x00, 0x07, 0xCF, 0x80, 0x07, 0xE7, 0xC0, 0x03, 0xE3, 0xE0,\n  0x03, 0xF1, 0xF0, 0x07, 0xF1, 0xFF, 0xFF, 0xF9, 0xFF, 0xFF, 0xF8, 0xFF,\n  0xFF, 0xF8, 0x7F, 0xFF, 0xF0, 0x1F, 0xFF, 0xE0, 0x00, 0x7F, 0xFF, 0xFF,\n  0x7F, 0xFF, 0xFF, 0xBF, 0xFF, 0xFF, 0xDF, 0xFF, 0xFF, 0xE7, 0xFF, 0xFF,\n  0xF0, 0xF8, 0x00, 0xF8, 0x7C, 0x00, 0x7C, 0x3E, 0x0E, 0x3E, 0x1F, 0x0F,\n  0x9F, 0x0F, 0x87, 0xC7, 0x07, 0xC3, 0xE0, 0x03, 0xFF, 0xF0, 0x01, 0xFF,\n  0xF8, 0x00, 0xFF, 0xFC, 0x00, 0x7F, 0xFE, 0x00, 0x3F, 0xFF, 0x00, 0x1F,\n  0x0F, 0x80, 0x0F, 0x87, 0xC3, 0x87, 0xC1, 0xC3, 0xE3, 0xE0, 0x01, 0xF1,\n  0xF0, 0x00, 0xF8, 0xF8, 0x00, 0x7D, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDF, 0xFF, 0xFF, 0xE0, 0x7F, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF7, 0xFF,\n  0xFF, 0xF8, 0xF8, 0x00, 0x7C, 0x7C, 0x00, 0x3E, 0x3E, 0x00, 0x1F, 0x1F,\n  0x07, 0x0F, 0x8F, 0x87, 0xC3, 0x87, 0xC3, 0xE0, 0x03, 0xFF, 0xF0, 0x01,\n  0xFF, 0xF8, 0x00, 0xFF, 0xFC, 0x00, 0x7F, 0xFE, 0x00, 0x3F, 0xFF, 0x00,\n  0x1F, 0x0F, 0x80, 0x0F, 0x87, 0xC0, 0x07, 0xC3, 0xE0, 0x03, 0xE0, 0xE0,\n  0x01, 0xF0, 0x00, 0x00, 0xF8, 0x00, 0x01, 0xFF, 0xF0, 0x01, 0xFF, 0xFC,\n  0x00, 0xFF, 0xFE, 0x00, 0x7F, 0xFF, 0x00, 0x1F, 0xFF, 0x00, 0x00, 0x00,\n  0x7F, 0x8E, 0x00, 0xFF, 0xF7, 0x81, 0xFF, 0xFF, 0xC1, 0xFF, 0xFF, 0xE1,\n  0xFF, 0xFF, 0xF1, 0xFE, 0x03, 0xF8, 0xFC, 0x00, 0xFC, 0xFC, 0x00, 0x3E,\n  0x7C, 0x00, 0x1F, 0x7E, 0x00, 0x07, 0x3E, 0x00, 0x00, 0x1F, 0x00, 0x00,\n  0x0F, 0x80, 0x00, 0x07, 0xC0, 0x00, 0x03, 0xE0, 0x00, 0x01, 0xF0, 0x0F,\n  0xFE, 0xF8, 0x0F, 0xFF, 0xFC, 0x07, 0xFF, 0xFE, 0x03, 0xFF, 0xFF, 0x00,\n  0xFF, 0xFF, 0xC0, 0x01, 0xF3, 0xF0, 0x00, 0xF9, 0xFC, 0x00, 0x7C, 0x7F,\n  0x80, 0xFE, 0x3F, 0xFF, 0xFF, 0x0F, 0xFF, 0xFF, 0x83, 0xFF, 0xFF, 0x80,\n  0x7F, 0xFF, 0x00, 0x07, 0xFC, 0x00, 0x3F, 0xE1, 0xFF, 0x1F, 0xFC, 0xFF,\n  0xE7, 0xFF, 0x3F, 0xF9, 0xFF, 0xCF, 0xFE, 0x3F, 0xE1, 0xFF, 0x07, 0xC0,\n  0x0F, 0x81, 0xF0, 0x03, 0xE0, 0x7C, 0x00, 0xF8, 0x1F, 0x00, 0x3E, 0x07,\n  0xC0, 0x0F, 0x81, 0xF0, 0x03, 0xE0, 0x7F, 0xFF, 0xF8, 0x1F, 0xFF, 0xFE,\n  0x07, 0xFF, 0xFF, 0x81, 0xFF, 0xFF, 0xE0, 0x7F, 0xFF, 0xF8, 0x1F, 0x00,\n  0x3E, 0x07, 0xC0, 0x0F, 0x81, 0xF0, 0x03, 0xE0, 0x7C, 0x00, 0xF8, 0x1F,\n  0x00, 0x3E, 0x07, 0xC0, 0x0F, 0x87, 0xFE, 0x1F, 0xFB, 0xFF, 0xCF, 0xFF,\n  0xFF, 0xF3, 0xFF, 0xFF, 0xFC, 0xFF, 0xF7, 0xFE, 0x1F, 0xF8, 0x7F, 0xFF,\n  0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF7, 0xFF, 0xFC, 0x03, 0xE0,\n  0x00, 0x7C, 0x00, 0x0F, 0x80, 0x01, 0xF0, 0x00, 0x3E, 0x00, 0x07, 0xC0,\n  0x00, 0xF8, 0x00, 0x1F, 0x00, 0x03, 0xE0, 0x00, 0x7C, 0x00, 0x0F, 0x80,\n  0x01, 0xF0, 0x00, 0x3E, 0x00, 0x07, 0xC0, 0x00, 0xF8, 0x00, 0x1F, 0x00,\n  0x03, 0xE0, 0x1F, 0xFF, 0xF7, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD,\n  0xFF, 0xFF, 0x00, 0x00, 0xFF, 0xFF, 0x00, 0xFF, 0xFF, 0xC0, 0x7F, 0xFF,\n  0xE0, 0x3F, 0xFF, 0xF0, 0x0F, 0xFF, 0xF0, 0x00, 0x0F, 0x80, 0x00, 0x07,\n  0xC0, 0x00, 0x03, 0xE0, 0x00, 0x01, 0xF0, 0x00, 0x00, 0xF8, 0x00, 0x00,\n  0x7C, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x0F, 0x80, 0x00,\n  0x07, 0xC0, 0xE0, 0x03, 0xE0, 0xF8, 0x01, 0xF0, 0x7C, 0x00, 0xF8, 0x3E,\n  0x00, 0x7C, 0x1F, 0x00, 0x3E, 0x0F, 0x80, 0x1F, 0x07, 0xC0, 0x1F, 0x83,\n  0xF8, 0x3F, 0x81, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xC0, 0x3F, 0xFF, 0xC0,\n  0x07, 0xFF, 0xC0, 0x00, 0x7F, 0x00, 0x00, 0x7F, 0xE0, 0xFF, 0x9F, 0xFE,\n  0x3F, 0xFB, 0xFF, 0xC7, 0xFF, 0x7F, 0xF8, 0xFF, 0xE7, 0xFE, 0x0F, 0xF8,\n  0x3E, 0x01, 0xF8, 0x07, 0xC0, 0xFE, 0x00, 0xF8, 0x3F, 0x80, 0x1F, 0x0F,\n  0xE0, 0x03, 0xE3, 0xF8, 0x00, 0x7D, 0xFC, 0x00, 0x0F, 0xFF, 0x00, 0x01,\n  0xFF, 0xF0, 0x00, 0x3F, 0xFF, 0x00, 0x07, 0xFF, 0xF0, 0x00, 0xFE, 0x7F,\n  0x00, 0x1F, 0x87, 0xF0, 0x03, 0xE0, 0x7E, 0x00, 0x7C, 0x07, 0xE0, 0x0F,\n  0x80, 0x7E, 0x01, 0xF0, 0x0F, 0xC0, 0x3E, 0x00, 0xF8, 0x1F, 0xF8, 0x1F,\n  0xF7, 0xFF, 0x81, 0xFF, 0xFF, 0xF0, 0x3F, 0xFF, 0xFE, 0x07, 0xFD, 0xFF,\n  0x80, 0x7F, 0x00, 0x7F, 0xFC, 0x00, 0x7F, 0xFF, 0x00, 0x3F, 0xFF, 0x80,\n  0x1F, 0xFF, 0xC0, 0x07, 0xFF, 0xC0, 0x00, 0x3E, 0x00, 0x00, 0x1F, 0x00,\n  0x00, 0x0F, 0x80, 0x00, 0x07, 0xC0, 0x00, 0x03, 0xE0, 0x00, 0x01, 0xF0,\n  0x00, 0x00, 0xF8, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x1F,\n  0x00, 0x00, 0x0F, 0x80, 0x0E, 0x07, 0xC0, 0x0F, 0x83, 0xE0, 0x07, 0xC1,\n  0xF0, 0x03, 0xE0, 0xF8, 0x01, 0xF0, 0x7C, 0x00, 0xF8, 0x3E, 0x00, 0x7D,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xDF, 0xFF, 0xFF, 0xE0, 0x3F, 0x80, 0x03, 0xF8, 0xFF, 0x80, 0x0F, 0xF9,\n  0xFF, 0x00, 0x1F, 0xF3, 0xFF, 0x00, 0x7F, 0xE3, 0xFE, 0x00, 0xFF, 0x83,\n  0xFE, 0x03, 0xFE, 0x07, 0xFC, 0x07, 0xFC, 0x0F, 0xFC, 0x1F, 0xF8, 0x1F,\n  0xF8, 0x3F, 0xF0, 0x3F, 0xF0, 0x7F, 0xE0, 0x7D, 0xF1, 0xF7, 0xC0, 0xFB,\n  0xE3, 0xEF, 0x81, 0xF7, 0xEF, 0xDF, 0x03, 0xE7, 0xDF, 0x3E, 0x07, 0xCF,\n  0xFE, 0x7C, 0x0F, 0x8F, 0xF8, 0xF8, 0x1F, 0x1F, 0xF1, 0xF0, 0x3E, 0x1F,\n  0xE3, 0xE0, 0x7C, 0x3F, 0x87, 0xC0, 0xF8, 0x3F, 0x0F, 0x81, 0xF0, 0x00,\n  0x1F, 0x03, 0xE0, 0x00, 0x3E, 0x1F, 0xF8, 0x03, 0xFF, 0x7F, 0xF8, 0x0F,\n  0xFF, 0xFF, 0xF0, 0x1F, 0xFF, 0xFF, 0xE0, 0x3F, 0xFD, 0xFF, 0x80, 0x3F,\n  0xF0, 0x7F, 0x00, 0x7F, 0xEF, 0xF8, 0x0F, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF,\n  0xFC, 0x0F, 0xFF, 0x7F, 0xE0, 0x7F, 0xE1, 0xFF, 0x00, 0xF8, 0x1F, 0xF0,\n  0x0F, 0x81, 0xFF, 0x80, 0xF8, 0x1F, 0xFC, 0x0F, 0x81, 0xFF, 0xC0, 0xF8,\n  0x1F, 0x7E, 0x0F, 0x81, 0xF3, 0xF0, 0xF8, 0x1F, 0x3F, 0x0F, 0x81, 0xF1,\n  0xF8, 0xF8, 0x1F, 0x0F, 0xCF, 0x81, 0xF0, 0xFC, 0xF8, 0x1F, 0x07, 0xEF,\n  0x81, 0xF0, 0x3F, 0xF8, 0x1F, 0x03, 0xFF, 0x81, 0xF0, 0x1F, 0xF8, 0x1F,\n  0x00, 0xFF, 0x81, 0xF0, 0x0F, 0xF8, 0x7F, 0xE0, 0x7F, 0x8F, 0xFF, 0x03,\n  0xF8, 0xFF, 0xF0, 0x3F, 0x8F, 0xFF, 0x01, 0xF8, 0x7F, 0xE0, 0x0F, 0x80,\n  0x00, 0x3F, 0x80, 0x00, 0x3F, 0xFC, 0x00, 0x0F, 0xFF, 0xE0, 0x03, 0xFF,\n  0xFE, 0x00, 0xFF, 0xFF, 0xE0, 0x3F, 0xC1, 0xFE, 0x0F, 0xE0, 0x0F, 0xE1,\n  0xF8, 0x00, 0xFC, 0x7E, 0x00, 0x0F, 0xCF, 0x80, 0x00, 0xFB, 0xF0, 0x00,\n  0x1F, 0xFC, 0x00, 0x01, 0xFF, 0x80, 0x00, 0x3F, 0xF0, 0x00, 0x07, 0xFE,\n  0x00, 0x00, 0xFF, 0xC0, 0x00, 0x1F, 0xF8, 0x00, 0x03, 0xFF, 0x00, 0x00,\n  0x7F, 0xF0, 0x00, 0x1F, 0xBE, 0x00, 0x03, 0xE7, 0xE0, 0x00, 0xFC, 0x7E,\n  0x00, 0x3F, 0x0F, 0xE0, 0x0F, 0xE0, 0xFF, 0x07, 0xF8, 0x0F, 0xFF, 0xFE,\n  0x00, 0xFF, 0xFF, 0x80, 0x0F, 0xFF, 0xE0, 0x00, 0xFF, 0xF8, 0x00, 0x03,\n  0xF8, 0x00, 0x7F, 0xFF, 0x80, 0xFF, 0xFF, 0xF0, 0xFF, 0xFF, 0xF8, 0xFF,\n  0xFF, 0xFC, 0x7F, 0xFF, 0xFE, 0x1F, 0x00, 0xFE, 0x1F, 0x00, 0x3F, 0x1F,\n  0x00, 0x1F, 0x1F, 0x00, 0x1F, 0x1F, 0x00, 0x1F, 0x1F, 0x00, 0x1F, 0x1F,\n  0x00, 0x3F, 0x1F, 0x00, 0x7E, 0x1F, 0xFF, 0xFE, 0x1F, 0xFF, 0xFC, 0x1F,\n  0xFF, 0xF8, 0x1F, 0xFF, 0xF0, 0x1F, 0xFF, 0x80, 0x1F, 0x00, 0x00, 0x1F,\n  0x00, 0x00, 0x1F, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x7F, 0xFC, 0x00, 0xFF,\n  0xFE, 0x00, 0xFF, 0xFE, 0x00, 0xFF, 0xFE, 0x00, 0x7F, 0xFC, 0x00, 0x00,\n  0x3F, 0x80, 0x00, 0x3F, 0xFC, 0x00, 0x0F, 0xFF, 0xE0, 0x03, 0xFF, 0xFE,\n  0x00, 0xFF, 0xFF, 0xE0, 0x3F, 0xC1, 0xFE, 0x0F, 0xE0, 0x0F, 0xE1, 0xF8,\n  0x00, 0xFC, 0x7E, 0x00, 0x0F, 0xCF, 0x80, 0x00, 0xFB, 0xF0, 0x00, 0x1F,\n  0xFC, 0x00, 0x01, 0xFF, 0x80, 0x00, 0x3F, 0xF0, 0x00, 0x07, 0xFE, 0x00,\n  0x00, 0xFF, 0xC0, 0x00, 0x1F, 0xF8, 0x00, 0x03, 0xFF, 0x80, 0x00, 0xFD,\n  0xF0, 0x00, 0x1F, 0x3F, 0x00, 0x07, 0xE7, 0xF0, 0x01, 0xF8, 0x7F, 0x00,\n  0x7F, 0x07, 0xF8, 0x3F, 0xC0, 0xFF, 0xFF, 0xF0, 0x07, 0xFF, 0xFC, 0x00,\n  0x7F, 0xFF, 0x00, 0x07, 0xFF, 0xC0, 0x00, 0x7F, 0xC0, 0x00, 0x0F, 0x00,\n  0x00, 0x03, 0xFF, 0x87, 0x80, 0xFF, 0xFF, 0xF8, 0x3F, 0xFF, 0xFF, 0x07,\n  0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xF0, 0x0F, 0x01, 0xF8, 0x00, 0x7F, 0xFF,\n  0x80, 0x0F, 0xFF, 0xFF, 0x00, 0xFF, 0xFF, 0xF8, 0x0F, 0xFF, 0xFF, 0xC0,\n  0x7F, 0xFF, 0xFE, 0x00, 0xF8, 0x07, 0xE0, 0x0F, 0x80, 0x3F, 0x00, 0xF8,\n  0x01, 0xF0, 0x0F, 0x80, 0x1F, 0x00, 0xF8, 0x01, 0xF0, 0x0F, 0x80, 0x3F,\n  0x00, 0xF8, 0x0F, 0xE0, 0x0F, 0xFF, 0xFE, 0x00, 0xFF, 0xFF, 0xC0, 0x0F,\n  0xFF, 0xF0, 0x00, 0xFF, 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0xE0, 0x00, 0x01, 0xF0,\n  0x00, 0x00, 0xF8, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x1F,\n  0x00, 0x00, 0x0F, 0x80, 0x00, 0x07, 0xC0, 0x00, 0x03, 0xE0, 0x00, 0x01,\n  0xF0, 0x00, 0x0F, 0xFF, 0x80, 0x0F, 0xFF, 0xE0, 0x07, 0xFF, 0xF0, 0x03,\n  0xFF, 0xF8, 0x00, 0xFF, 0xF8, 0x00, 0x7F, 0xE0, 0x7F, 0xEF, 0xFF, 0x0F,\n  0xFF, 0xFF, 0xF0, 0xFF, 0xFF, 0xFF, 0x0F, 0xFF, 0x7F, 0xE0, 0x7F, 0xE1,\n  0xF0, 0x00, 0xF8, 0x1F, 0x00, 0x0F, 0x81, 0xF0, 0x00, 0xF8, 0x1F, 0x00,\n  0x0F, 0x81, 0xF0, 0x00, 0xF8, 0x1F, 0x00, 0x0F, 0x81, 0xF0, 0x00, 0xF8,\n  0x1F, 0x00, 0x0F, 0x81, 0xF0, 0x00, 0xF8, 0x1F, 0x00, 0x0F, 0x81, 0xF0,\n  0x00, 0xF8, 0x1F, 0x00, 0x0F, 0x81, 0xF0, 0x00, 0xF8, 0x1F, 0x00, 0x0F,\n  0x81, 0xF0, 0x00, 0xF8, 0x1F, 0x80, 0x1F, 0x80, 0xF8, 0x01, 0xF0, 0x0F,\n  0xE0, 0x7F, 0x00, 0x7F, 0xFF, 0xE0, 0x03, 0xFF, 0xFE, 0x00, 0x1F, 0xFF,\n  0x80, 0x00, 0xFF, 0xF0, 0x00, 0x03, 0xFC, 0x00, 0x7F, 0xE0, 0x1F, 0xFB,\n  0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0x03, 0xFF, 0xFF, 0xFC, 0x0F, 0xFF, 0x7F,\n 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0x00, 0x00, 0x1F, 0x00,\n  0x00, 0x07, 0xC0, 0x00, 0x01, 0xF0, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x1F,\n  0x00, 0x00, 0x07, 0xC0, 0x00, 0x1F, 0xFF, 0x00, 0x0F, 0xFF, 0xE0, 0x03,\n  0xFF, 0xF8, 0x00, 0xFF, 0xFE, 0x00, 0x1F, 0xFF, 0x00, 0x7F, 0xFF, 0xF3,\n  0xFF, 0xFF, 0x9F, 0xFF, 0xFC, 0xFF, 0xFF, 0xE7, 0xFF, 0xFF, 0x3E, 0x03,\n  0xF1, 0xF0, 0x1F, 0x8F, 0x81, 0xF8, 0x7C, 0x1F, 0x83, 0xE1, 0xF8, 0x0E,\n  0x1F, 0x80, 0x01, 0xFC, 0x00, 0x0F, 0xC0, 0x00, 0xFC, 0x00, 0x0F, 0xC0,\n  0x00, 0xFC, 0x00, 0x0F, 0xE0, 0x70, 0x7E, 0x07, 0xC7, 0xE0, 0x3E, 0x7E,\n  0x01, 0xF7, 0xE0, 0x0F, 0xFF, 0x00, 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xBF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xBE, 0x0F, 0x83, 0xE0, 0xF8, 0x3E, 0x0F, 0x83, 0xE0, 0xF8,\n  0x3E, 0x0F, 0x83, 0xE0, 0xF8, 0x3E, 0x0F, 0x83, 0xE0, 0xF8, 0x3E, 0x0F,\n  0x83, 0xE0, 0xF8, 0x3E, 0x0F, 0x83, 0xE0, 0xF8, 0x3E, 0x0F, 0x83, 0xE0,\n  0xFF, 0xBF, 0xFF, 0xFF, 0xFF, 0xFF, 0x80, 0x60, 0x00, 0x0F, 0x00, 0x00,\n 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0xF0, 0xFC, 0x7E, 0x07, 0xEF, 0xC0, 0x3F, 0xF8,\n  0x01, 0xFF, 0x80, 0x0F, 0x70, 0x00, 0x60, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xF0, 0xE0, 0x78, 0x3E, 0x0F, 0xC3, 0xF0, 0x7C, 0x1E, 0x06, 0x01, 0xFF,\n  0x00, 0x0F, 0xFF, 0xC0, 0x1F, 0xFF, 0xE0, 0x1F, 0xFF, 0xF0, 0x0F, 0xFF,\n  0xF8, 0x00, 0x01, 0xF8, 0x00, 0x00, 0xF8, 0x00, 0x00, 0xF8, 0x01, 0xFF,\n  0xF8, 0x07, 0xFF, 0xF8, 0x1F, 0xFF, 0xF8, 0x3F, 0xFF, 0xF8, 0x7F, 0xFF,\n  0xF8, 0x7F, 0x00, 0xF8, 0xFC, 0x00, 0xF8, 0xF8, 0x00, 0xF8, 0xF8, 0x03,\n  0xF8, 0xFC, 0x0F, 0xFE, 0xFF, 0xFF, 0xFF, 0x7F, 0xFF, 0xFF, 0x3F, 0xFF,\n  0xFF, 0x1F, 0xFE, 0xFE, 0x07, 0xF0, 0x00, 0x7F, 0x00, 0x00, 0x1F, 0xE0,\n  0x00, 0x03, 0xFC, 0x00, 0x00, 0x7F, 0x80, 0x00, 0x07, 0xF0, 0x00, 0x00,\n  0x3E, 0x00, 0x00, 0x07, 0xC0, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x1F, 0x0F,\n  0xE0, 0x03, 0xEF, 0xFF, 0x00, 0x7F, 0xFF, 0xF8, 0x0F, 0xFF, 0xFF, 0x81,\n  0xFF, 0xFF, 0xF8, 0x3F, 0xE0, 0x7F, 0x07, 0xF0, 0x03, 0xF0, 0xFC, 0x00,\n  0x3E, 0x1F, 0x80, 0x07, 0xE3, 0xE0, 0x00, 0x7C, 0x7C, 0x00, 0x0F, 0x8F,\n  0x80, 0x01, 0xF1, 0xF0, 0x00, 0x3E, 0x3E, 0x00, 0x07, 0xC7, 0xE0, 0x01,\n  0xF8, 0xFC, 0x00, 0x3E, 0x1F, 0xC0, 0x0F, 0xCF, 0xFE, 0x07, 0xF3, 0xFF,\n  0xFF, 0xFE, 0x7F, 0xFF, 0xFF, 0x8F, 0xFF, 0xFF, 0xE0, 0xFE, 0x7F, 0xF0,\n  0x00, 0x03, 0xF8, 0x00, 0x00, 0xFF, 0x18, 0x03, 0xFF, 0xFC, 0x0F, 0xFF,\n  0xFC, 0x1F, 0xFF, 0xFC, 0x3F, 0xFF, 0xFC, 0x3F, 0x81, 0xFC, 0x7E, 0x00,\n  0x7C, 0x7C, 0x00, 0x7C, 0xFC, 0x00, 0x3C, 0xF8, 0x00, 0x38, 0xF8, 0x00,\n  0x00, 0xF8, 0x00, 0x00, 0xF8, 0x00, 0x00, 0xF8, 0x00, 0x00, 0xFC, 0x00,\n  0x00, 0x7C, 0x00, 0x06, 0x7E, 0x00, 0x1F, 0x7F, 0x80, 0x7F, 0x3F, 0xFF,\n  0xFF, 0x1F, 0xFF, 0xFE, 0x0F, 0xFF, 0xFC, 0x07, 0xFF, 0xF8, 0x00, 0xFF,\n  0xC0, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x7F, 0x80, 0x00, 0x1F, 0xE0, 0x00,\n  0x07, 0xF8, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x0F, 0x80, 0x00, 0x03, 0xE0,\n  0x00, 0x00, 0xF8, 0x00, 0xFE, 0x3E, 0x00, 0xFF, 0xEF, 0x80, 0xFF, 0xFF,\n  0xE0, 0x7F, 0xFF, 0xF8, 0x3F, 0xFF, 0xFE, 0x1F, 0xE0, 0xFF, 0x87, 0xE0,\n  0x0F, 0xE1, 0xF0, 0x01, 0xF8, 0xFC, 0x00, 0x7E, 0x3E, 0x00, 0x0F, 0x8F,\n  0x80, 0x03, 0xE3, 0xE0, 0x00, 0xF8, 0xF8, 0x00, 0x3E, 0x3E, 0x00, 0x0F,\n  0x8F, 0xC0, 0x07, 0xE1, 0xF0, 0x01, 0xF8, 0x7E, 0x00, 0xFE, 0x0F, 0xE0,\n  0x7F, 0xE3, 0xFF, 0xFF, 0xFC, 0x7F, 0xFF, 0xFF, 0x0F, 0xFF, 0xFF, 0xC0,\n  0xFF, 0xEF, 0xE0, 0x0F, 0xC0, 0x00, 0x00, 0xFE, 0x00, 0x03, 0xFF, 0xC0,\n  0x0F, 0xFF, 0xE0, 0x1F, 0xFF, 0xF0, 0x3F, 0xFF, 0xF8, 0x7F, 0x81, 0xFC,\n  0x7E, 0x00, 0x7E, 0xFC, 0x00, 0x3E, 0xF8, 0x00, 0x3E, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xF8, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x7F, 0x80, 0x7E,\n  0x3F, 0xFF, 0xFF, 0x1F, 0xFF, 0xFF, 0x0F, 0xFF, 0xFE, 0x07, 0xFF, 0xF8,\n  0x00, 0xFF, 0x80, 0x00, 0x3F, 0xE0, 0x03, 0xFF, 0xE0, 0x1F, 0xFF, 0xC0,\n  0xFF, 0xFF, 0x07, 0xFF, 0xF8, 0x1F, 0x80, 0x00, 0x7C, 0x00, 0x01, 0xF0,\n  0x00, 0x07, 0xC0, 0x01, 0xFF, 0xFF, 0x0F, 0xFF, 0xFE, 0x3F, 0xFF, 0xF8,\n  0xFF, 0xFF, 0xE1, 0xFF, 0xFF, 0x00, 0x7C, 0x00, 0x01, 0xF0, 0x00, 0x07,\n  0xC0, 0x00, 0x1F, 0x00, 0x00, 0x7C, 0x00, 0x01, 0xF0, 0x00, 0x07, 0xC0,\n  0x00, 0x1F, 0x00, 0x00, 0x7C, 0x00, 0x01, 0xF0, 0x00, 0x07, 0xC0, 0x01,\n  0xFF, 0xFF, 0x0F, 0xFF, 0xFE, 0x3F, 0xFF, 0xF8, 0xFF, 0xFF, 0xE1, 0xFF,\n  0xFF, 0x00, 0x00, 0xFC, 0x00, 0x03, 0xFF, 0xBF, 0x83, 0xFF, 0xFF, 0xE3,\n  0xFF, 0xFF, 0xF3, 0xFF, 0xFF, 0xFB, 0xFC, 0x3F, 0xF9, 0xF8, 0x07, 0xF0,\n  0xF8, 0x01, 0xF8, 0xFC, 0x00, 0xFC, 0x7C, 0x00, 0x3E, 0x3E, 0x00, 0x1F,\n  0x1F, 0x00, 0x0F, 0x8F, 0x80, 0x07, 0xC7, 0xC0, 0x03, 0xE3, 0xF0, 0x03,\n  0xF0, 0xF8, 0x01, 0xF8, 0x7E, 0x01, 0xFC, 0x3F, 0xC3, 0xFE, 0x0F, 0xFF,\n  0xFF, 0x03, 0xFF, 0xFF, 0x80, 0xFF, 0xFF, 0xC0, 0x3F, 0xFB, 0xE0, 0x07,\n  0xF1, 0xF0, 0x00, 0x00, 0xF8, 0x00, 0x00, 0xFC, 0x00, 0x00, 0xFE, 0x00,\n  0xFF, 0xFE, 0x00, 0xFF, 0xFF, 0x00, 0x7F, 0xFF, 0x00, 0x3F, 0xFE, 0x00,\n  0x0F, 0xFC, 0x00, 0x7F, 0x00, 0x00, 0x3F, 0xC0, 0x00, 0x0F, 0xF0, 0x00,\n  0x03, 0xFC, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x07, 0xC0, 0x00, 0x01, 0xF0,\n  0x00, 0x00, 0x7C, 0x00, 0x00, 0x1F, 0x0F, 0xC0, 0x07, 0xCF, 0xFC, 0x01,\n  0xF7, 0xFF, 0x80, 0x7F, 0xFF, 0xF0, 0x1F, 0xFF, 0xFC, 0x07, 0xFC, 0x1F,\n  0x81, 0xFC, 0x03, 0xE0, 0x7E, 0x00, 0xF8, 0x1F, 0x00, 0x3E, 0x07, 0xC0,\n  0x0F, 0x81, 0xF0, 0x03, 0xE0, 0x7C, 0x00, 0xF8, 0x1F, 0x00, 0x3E, 0x07,\n  0xC0, 0x0F, 0x81, 0xF0, 0x03, 0xE0, 0x7C, 0x00, 0xF8, 0x1F, 0x00, 0x3E,\n  0x1F, 0xF0, 0x3F, 0xEF, 0xFE, 0x1F, 0xFF, 0xFF, 0x87, 0xFF, 0xFF, 0xE1,\n  0xFF, 0xDF, 0xF0, 0x3F, 0xE0, 0x01, 0xF0, 0x00, 0x0F, 0x80, 0x00, 0x7C,\n  0x00, 0x03, 0xE0, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x1F, 0xF8, 0x01, 0xFF, 0xC0, 0x0F, 0xFE, 0x00, 0x7F, 0xF0,\n  0x01, 0xFF, 0x80, 0x00, 0x7C, 0x00, 0x03, 0xE0, 0x00, 0x1F, 0x00, 0x00,\n  0xF8, 0x00, 0x07, 0xC0, 0x00, 0x3E, 0x00, 0x01, 0xF0, 0x00, 0x0F, 0x80,\n  0x00, 0x7C, 0x00, 0x03, 0xE0, 0x00, 0x1F, 0x00, 0x7F, 0xFF, 0xF7, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF7, 0xFF, 0xFF, 0x00, 0x00, 0x7C,\n  0x00, 0x3E, 0x00, 0x1F, 0x00, 0x0F, 0x80, 0x07, 0xC0, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF7,\n  0xFF, 0xF8, 0x00, 0x7C, 0x00, 0x3E, 0x00, 0x1F, 0x00, 0x0F, 0x80, 0x07,\n  0xC0, 0x03, 0xE0, 0x01, 0xF0, 0x00, 0xF8, 0x00, 0x7C, 0x00, 0x3E, 0x00,\n  0x1F, 0x00, 0x0F, 0x80, 0x07, 0xC0, 0x03, 0xE0, 0x01, 0xF0, 0x00, 0xF8,\n  0x00, 0x7C, 0x00, 0x3E, 0x00, 0x3F, 0x00, 0x3F, 0xBF, 0xFF, 0xBF, 0xFF,\n  0x9F, 0xFF, 0xCF, 0xFF, 0x83, 0xFF, 0x00, 0x7F, 0x00, 0x00, 0x7F, 0x80,\n  0x00, 0x3F, 0xC0, 0x00, 0x1F, 0xE0, 0x00, 0x07, 0xF0, 0x00, 0x00, 0xF8,\n  0x00, 0x00, 0x7C, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x0F,\n  0x87, 0xFC, 0x07, 0xC7, 0xFF, 0x03, 0xE3, 0xFF, 0x81, 0xF1, 0xFF, 0xC0,\n  0xF8, 0x7F, 0xC0, 0x7C, 0xFE, 0x00, 0x3E, 0xFE, 0x00, 0x1F, 0xFE, 0x00,\n  0x0F, 0xFE, 0x00, 0x07, 0xFE, 0x00, 0x03, 0xFF, 0x80, 0x01, 0xFF, 0xE0,\n  0x00, 0xFF, 0xF8, 0x00, 0x7C, 0xFE, 0x00, 0x3E, 0x3F, 0x80, 0x1F, 0x0F,\n  0xE0, 0x3F, 0x81, 0xFF, 0xBF, 0xC1, 0xFF, 0xFF, 0xE0, 0xFF, 0xFF, 0xF0,\n  0x7F, 0xFB, 0xF8, 0x1F, 0xF8, 0x1F, 0xF8, 0x01, 0xFF, 0xC0, 0x0F, 0xFE,\n  0x00, 0x7F, 0xF0, 0x01, 0xFF, 0x80, 0x00, 0x7C, 0x00, 0x03, 0xE0, 0x00,\n  0x1F, 0x00, 0x00, 0xF8, 0x00, 0x07, 0xC0, 0x00, 0x3E, 0x00, 0x01, 0xF0,\n  0x00, 0x0F, 0x80, 0x00, 0x7C, 0x00, 0x03, 0xE0, 0x00, 0x1F, 0x00, 0x00,\n  0xF8, 0x00, 0x07, 0xC0, 0x00, 0x3E, 0x00, 0x01, 0xF0, 0x00, 0x0F, 0x80,\n  0x00, 0x7C, 0x00, 0x03, 0xE0, 0x00, 0x1F, 0x00, 0x00, 0xF8, 0x03, 0xFF,\n  0xFF, 0xBF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xBF, 0xFF, 0xF8,\n  0x00, 0x3C, 0x1F, 0x00, 0xFD, 0xFC, 0xFF, 0x07, 0xFF, 0xFF, 0xFE, 0x1F,\n  0xFF, 0xFF, 0xF8, 0x7F, 0xFF, 0xFF, 0xF0, 0xFF, 0x1F, 0x87, 0xC1, 0xF8,\n  0x7E, 0x1F, 0x07, 0xC1, 0xF0, 0x7C, 0x1F, 0x07, 0xC1, 0xF0, 0x7C, 0x1F,\n  0x07, 0xC1, 0xF0, 0x7C, 0x1F, 0x07, 0xC1, 0xF0, 0x7C, 0x1F, 0x07, 0xC1,\n  0xF0, 0x7C, 0x1F, 0x07, 0xC1, 0xF0, 0x7C, 0x1F, 0x07, 0xC1, 0xF0, 0x7C,\n  0x1F, 0x07, 0xC1, 0xF1, 0xFE, 0x1F, 0x87, 0xEF, 0xFC, 0x7F, 0x1F, 0xFF,\n  0xF1, 0xFC, 0x7F, 0xFF, 0xC7, 0xF1, 0xFD, 0xFE, 0x1F, 0x87, 0xE0, 0x00,\n  0x1F, 0x80, 0x1F, 0x9F, 0xF8, 0x1F, 0xDF, 0xFE, 0x0F, 0xFF, 0xFF, 0x87,\n  0xFF, 0xFF, 0xC1, 0xFF, 0x07, 0xF0, 0x7F, 0x01, 0xF8, 0x3F, 0x00, 0x7C,\n  0x1F, 0x00, 0x3E, 0x0F, 0x80, 0x1F, 0x07, 0xC0, 0x0F, 0x83, 0xE0, 0x07,\n  0xC1, 0xF0, 0x03, 0xE0, 0xF8, 0x01, 0xF0, 0x7C, 0x00, 0xF8, 0x3E, 0x00,\n  0x7C, 0x1F, 0x00, 0x3E, 0x3F, 0xE0, 0x7F, 0xBF, 0xF8, 0x7F, 0xFF, 0xFC,\n  0x3F, 0xFF, 0xFE, 0x1F, 0xFB, 0xFE, 0x07, 0xF8, 0x00, 0x7F, 0x00, 0x01,\n  0xFF, 0xF0, 0x01, 0xFF, 0xFC, 0x03, 0xFF, 0xFF, 0x83, 0xFF, 0xFF, 0xC1,\n  0xFE, 0x0F, 0xF1, 0xFC, 0x01, 0xFC, 0xFC, 0x00, 0x7E, 0xFC, 0x00, 0x1F,\n  0xFC, 0x00, 0x07, 0xFE, 0x00, 0x03, 0xFF, 0x00, 0x01, 0xFF, 0x80, 0x00,\n  0xFF, 0xC0, 0x00, 0x7F, 0xF0, 0x00, 0x7E, 0xF8, 0x00, 0x7E, 0x7F, 0x00,\n  0x7F, 0x1F, 0xC0, 0xFF, 0x07, 0xFF, 0xFF, 0x03, 0xFF, 0xFF, 0x80, 0x7F,\n  0xFF, 0x00, 0x1F, 0xFF, 0x00, 0x01, 0xFC, 0x00, 0x00, 0x07, 0xE0, 0x03,\n  0xF9, 0xFF, 0xC0, 0x7F, 0xBF, 0xFE, 0x07, 0xFF, 0xFF, 0xF8, 0x7F, 0xFF,\n  0xFF, 0xC3, 0xFF, 0x83, 0xFC, 0x0F, 0xE0, 0x0F, 0xE0, 0xFC, 0x00, 0x7E,\n  0x0F, 0xC0, 0x03, 0xF0, 0xF8, 0x00, 0x1F, 0x0F, 0x80, 0x01, 0xF0, 0xF8,\n  0x00, 0x1F, 0x0F, 0x80, 0x01, 0xF0, 0xF8, 0x00, 0x3F, 0x0F, 0xC0, 0x03,\n  0xF0, 0xFE, 0x00, 0x7E, 0x0F, 0xF8, 0x1F, 0xE0, 0xFF, 0xFF, 0xFC, 0x0F,\n  0xFF, 0xFF, 0x80, 0xFF, 0xFF, 0xF0, 0x0F, 0x9F, 0xFC, 0x00, 0xF8, 0x7F,\n  0x00, 0x0F, 0x80, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x0F, 0x80, 0x00, 0x00,\n  0xF8, 0x00, 0x00, 0x7F, 0xF8, 0x00, 0x0F, 0xFF, 0xC0, 0x00, 0xFF, 0xFC,\n  0x00, 0x0F, 0xFF, 0xC0, 0x00, 0x7F, 0xF8, 0x00, 0x00, 0x00, 0x7E, 0x00,\n  0x00, 0x3F, 0xF9, 0xFC, 0x0F, 0xFF, 0xDF, 0xE1, 0xFF, 0xFF, 0xFE, 0x3F,\n  0xFF, 0xFF, 0xE3, 0xF8, 0x1F, 0xFC, 0x7F, 0x00, 0x7F, 0x07, 0xC0, 0x03,\n  0xF0, 0xFC, 0x00, 0x3F, 0x0F, 0x80, 0x01, 0xF0, 0xF8, 0x00, 0x1F, 0x0F,\n  0x80, 0x01, 0xF0, 0xF8, 0x00, 0x1F, 0x0F, 0xC0, 0x01, 0xF0, 0xFC, 0x00,\n  0x3F, 0x07, 0xE0, 0x07, 0xF0, 0x7F, 0x81, 0xFF, 0x03, 0xFF, 0xFF, 0xF0,\n  0x1F, 0xFF, 0xFF, 0x00, 0xFF, 0xFF, 0xF0, 0x03, 0xFF, 0x9F, 0x00, 0x0F,\n  0xE1, 0xF0, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x01, 0xF0, 0x00, 0x00, 0x1F,\n  0x00, 0x00, 0x01, 0xF0, 0x00, 0x01, 0xFF, 0xE0, 0x00, 0x3F, 0xFF, 0x00,\n  0x03, 0xFF, 0xF0, 0x00, 0x3F, 0xFF, 0x00, 0x01, 0xFF, 0xE0, 0x00, 0x01,\n  0xF0, 0x3F, 0xC7, 0xFC, 0x7F, 0xCF, 0xFE, 0x7F, 0xDF, 0xFF, 0x7F, 0xFF,\n  0xFF, 0x3F, 0xFF, 0x0E, 0x07, 0xFC, 0x00, 0x07, 0xF8, 0x00, 0x07, 0xF0,\n  0x00, 0x07, 0xE0, 0x00, 0x07, 0xC0, 0x00, 0x07, 0xC0, 0x00, 0x07, 0xC0,\n  0x00, 0x07, 0xC0, 0x00, 0x07, 0xC0, 0x00, 0x07, 0xC0, 0x00, 0x07, 0xC0,\n  0x00, 0x7F, 0xFF, 0xC0, 0xFF, 0xFF, 0xE0, 0xFF, 0xFF, 0xE0, 0xFF, 0xFF,\n  0xE0, 0x7F, 0xFF, 0xC0, 0x03, 0xFC, 0x60, 0x7F, 0xFF, 0x87, 0xFF, 0xFC,\n  0x7F, 0xFF, 0xE7, 0xFF, 0xFF, 0x3F, 0x01, 0xF9, 0xF0, 0x07, 0xCF, 0xC0,\n  0x1C, 0x7F, 0xF0, 0x03, 0xFF, 0xF8, 0x0F, 0xFF, 0xF0, 0x3F, 0xFF, 0xC0,\n  0x3F, 0xFF, 0x00, 0x0F, 0xFD, 0xC0, 0x07, 0xFE, 0x00, 0x1F, 0xF8, 0x00,\n  0xFF, 0xF0, 0x1F, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xEF, 0xFF, 0xFE, 0x3F,\n  0xFF, 0xC0, 0x07, 0xF8, 0x00, 0x07, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x3E,\n  0x00, 0x00, 0x7C, 0x00, 0x00, 0xF8, 0x00, 0x01, 0xF0, 0x00, 0x1F, 0xFF,\n  0xF8, 0x7F, 0xFF, 0xF8, 0xFF, 0xFF, 0xF1, 0xFF, 0xFF, 0xE1, 0xFF, 0xFF,\n  0x80, 0x7C, 0x00, 0x00, 0xF8, 0x00, 0x01, 0xF0, 0x00, 0x03, 0xE0, 0x00,\n  0x07, 0xC0, 0x00, 0x0F, 0x80, 0x00, 0x1F, 0x00, 0x00, 0x3E, 0x00, 0x00,\n  0x7C, 0x00, 0x00, 0xF8, 0x00, 0x01, 0xF0, 0x03, 0x83, 0xF0, 0x1F, 0x87,\n  0xFF, 0xFF, 0x07, 0xFF, 0xFE, 0x0F, 0xFF, 0xF8, 0x07, 0xFF, 0xC0, 0x03,\n  0xFC, 0x00, 0x7F, 0x01, 0xFE, 0x7F, 0x81, 0xFF, 0x3F, 0xC0, 0xFF, 0x9F,\n  0xE0, 0x7F, 0xC7, 0xF0, 0x1F, 0xE0, 0xF8, 0x01, 0xF0, 0x7C, 0x00, 0xF8,\n  0x3E, 0x00, 0x7C, 0x1F, 0x00, 0x3E, 0x0F, 0x80, 0x1F, 0x07, 0xC0, 0x0F,\n  0x83, 0xE0, 0x07, 0xC1, 0xF0, 0x03, 0xE0, 0xF8, 0x01, 0xF0, 0x7C, 0x01,\n  0xF8, 0x3F, 0x01, 0xFC, 0x1F, 0xC1, 0xFF, 0x07, 0xFF, 0xFF, 0xC3, 0xFF,\n  0xFF, 0xE0, 0xFF, 0xF7, 0xF0, 0x3F, 0xF3, 0xF0, 0x03, 0xF0, 0x00, 0x7F,\n  0xE0, 0x7F, 0xEF, 0xFF, 0x0F, 0xFF, 0xFF, 0xF0, 0xFF, 0xFF, 0xFF, 0x0F,\n  0xFF, 0x7F, 0xE0, 0x7F, 0xE0, 0xF8, 0x01, 0xF0, 0x0F, 0xC0, 0x1F, 0x00,\n  0x7C, 0x03, 0xE0, 0x07, 0xE0, 0x3E, 0x00, 0x3E, 0x07, 0xC0, 0x03, 0xF0,\n  0x7C, 0x00, 0x1F, 0x0F, 0x80, 0x01, 0xF8, 0xF8, 0x00, 0x0F, 0x9F, 0x00,\n  0x00, 0xFD, 0xF0, 0x00, 0x07, 0xFE, 0x00, 0x00, 0x7F, 0xE0, 0x00, 0x03,\n  0xFC, 0x00, 0x00, 0x3F, 0xC0, 0x00, 0x01, 0xFC, 0x00, 0x00, 0x1F, 0x80,\n  0x00, 0x7F, 0x80, 0x1F, 0xEF, 0xFC, 0x03, 0xFF, 0xFF, 0xC0, 0x3F, 0xFF,\n  0xFC, 0x03, 0xFF, 0x7F, 0x80, 0x1F, 0xE1, 0xF0, 0xF8, 0x7C, 0x1F, 0x1F,\n  0x87, 0xC1, 0xF1, 0xF8, 0xFC, 0x1F, 0x1F, 0xCF, 0x80, 0xFB, 0xFC, 0xF8,\n  0x0F, 0xBF, 0xDF, 0x80, 0xFB, 0xFF, 0xF0, 0x0F, 0xFF, 0xFF, 0x00, 0x7F,\n  0xDF, 0xF0, 0x07, 0xF9, 0xFF, 0x00, 0x7F, 0x9F, 0xE0, 0x07, 0xF0, 0xFE,\n  0x00, 0x3F, 0x0F, 0xE0, 0x03, 0xF0, 0x7E, 0x00, 0x3E, 0x07, 0xC0, 0x03,\n  0xE0, 0x3C, 0x00, 0x3F, 0xC0, 0xFF, 0x1F, 0xF8, 0x7F, 0xE7, 0xFE, 0x1F,\n  0xF9, 0xFF, 0x87, 0xFE, 0x3F, 0xC0, 0xFF, 0x03, 0xF8, 0x7F, 0x00, 0x7F,\n  0x3F, 0x80, 0x0F, 0xFF, 0xC0, 0x01, 0xFF, 0xE0, 0x00, 0x3F, 0xE0, 0x00,\n  0x07, 0xF8, 0x00, 0x07, 0xFF, 0x00, 0x03, 0xFF, 0xE0, 0x01, 0xFF, 0xFE,\n  0x00, 0xFE, 0x1F, 0xC0, 0x7F, 0x03, 0xF8, 0x7F, 0xC0, 0xFF, 0xBF, 0xF8,\n  0x7F, 0xFF, 0xFE, 0x1F, 0xFF, 0xFF, 0x87, 0xFF, 0x7F, 0xC0, 0xFF, 0x80,\n  0x7F, 0x80, 0x7F, 0xBF, 0xF0, 0x3F, 0xFF, 0xFC, 0x0F, 0xFF, 0xFF, 0x03,\n  0xFF, 0x7F, 0x80, 0x7F, 0x8F, 0xC0, 0x07, 0x81, 0xF0, 0x03, 0xE0, 0x7E,\n  0x01, 0xF0, 0x0F, 0x80, 0x7C, 0x03, 0xF0, 0x3E, 0x00, 0x7C, 0x0F, 0x80,\n  0x0F, 0x87, 0xC0, 0x03, 0xE1, 0xF0, 0x00, 0x7C, 0xF8, 0x00, 0x1F, 0xFE,\n  0x00, 0x03, 0xFF, 0x00, 0x00, 0xFF, 0xC0, 0x00, 0x1F, 0xE0, 0x00, 0x07,\n  0xF0, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x1F, 0x80, 0x00,\n  0x07, 0xC0, 0x00, 0x03, 0xF0, 0x00, 0x00, 0xF8, 0x00, 0x1F, 0xFF, 0x80,\n  0x0F, 0xFF, 0xF0, 0x03, 0xFF, 0xFC, 0x00, 0xFF, 0xFF, 0x00, 0x1F, 0xFF,\n  0x80, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xF0, 0x3F, 0xBE, 0x0F, 0xC3, 0x83, 0xF0, 0x00, 0xFC, 0x00,\n  0x3F, 0x00, 0x0F, 0xC0, 0x03, 0xF0, 0x00, 0xFC, 0x00, 0x3F, 0x00, 0x0F,\n  0xC0, 0x3B, 0xF0, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFE, 0x00, 0x78, 0x03, 0xF0, 0x1F, 0xC0, 0xFF, 0x07,\n  0xF8, 0x1F, 0x80, 0x7C, 0x01, 0xF0, 0x07, 0xC0, 0x1F, 0x00, 0x7C, 0x01,\n  0xF0, 0x07, 0xC0, 0x1F, 0x00, 0x7C, 0x01, 0xF0, 0x0F, 0x81, 0xFE, 0x0F,\n  0xF0, 0x3F, 0x80, 0xFF, 0x01, 0xFE, 0x00, 0xFC, 0x01, 0xF0, 0x07, 0xC0,\n  0x1F, 0x00, 0x7C, 0x01, 0xF0, 0x07, 0xC0, 0x1F, 0x00, 0x7C, 0x01, 0xF8,\n  0x07, 0xF8, 0x0F, 0xF0, 0x3F, 0xC0, 0x7F, 0x00, 0x78, 0x77, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xE0, 0x78, 0x03, 0xF0, 0x0F,\n  0xE0, 0x3F, 0xC0, 0x7F, 0x00, 0x7E, 0x00, 0xF8, 0x03, 0xE0, 0x0F, 0x80,\n  0x3E, 0x00, 0xF8, 0x03, 0xE0, 0x0F, 0x80, 0x3E, 0x00, 0xF8, 0x03, 0xE0,\n  0x07, 0xC0, 0x1F, 0xE0, 0x3F, 0xC0, 0x7F, 0x03, 0xFC, 0x1F, 0xE0, 0xFC,\n  0x03, 0xE0, 0x0F, 0x80, 0x3E, 0x00, 0xF8, 0x03, 0xE0, 0x0F, 0x80, 0x3E,\n  0x00, 0xF8, 0x07, 0xE0, 0x7F, 0x83, 0xFC, 0x0F, 0xF0, 0x3F, 0x80, 0x78,\n  0x00, 0x07, 0x80, 0x00, 0x7F, 0x80, 0x03, 0xFF, 0x03, 0x9F, 0xFE, 0x1F,\n  0xFF, 0xFC, 0xFF, 0xF3, 0xFF, 0xFF, 0x87, 0xFF, 0x9C, 0x0F, 0xFC, 0x00,\n  0x0F, 0xE0, 0x00, 0x1F, 0x00 };\n\nconst GFXglyph FreeMonoBold24pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,  28,    0,    1 },   // 0x20 ' '\n  {     0,   7,  31,  28,   10,  -29 },   // 0x21 '!'\n  {    28,  15,  14,  28,    6,  -28 },   // 0x22 '\"'\n  {    55,  22,  34,  28,    3,  -30 },   // 0x23 '#'\n  {   149,  19,  38,  28,    5,  -31 },   // 0x24 '$'\n  {   240,  21,  30,  28,    4,  -28 },   // 0x25 '%'\n  {   319,  21,  28,  28,    4,  -26 },   // 0x26 '&'\n  {   393,   6,  14,  28,   11,  -28 },   // 0x27 '''\n  {   404,  10,  37,  28,   12,  -29 },   // 0x28 '('\n  {   451,  10,  37,  28,    6,  -29 },   // 0x29 ')'\n  {   498,  21,  19,  28,    4,  -28 },   // 0x2A '*'\n  {   548,  23,  26,  28,    3,  -25 },   // 0x2B '+'\n  {   623,   9,  14,  28,    7,   -6 },   // 0x2C ','\n  {   639,  24,   5,  28,    2,  -15 },   // 0x2D '-'\n  {   654,   7,   6,  28,   11,   -4 },   // 0x2E '.'\n  {   660,  20,  38,  28,    4,  -32 },   // 0x2F '/'\n  {   755,  21,  31,  28,    4,  -29 },   // 0x30 '0'\n  {   837,  20,  29,  28,    4,  -28 },   // 0x31 '1'\n  {   910,  21,  30,  28,    3,  -29 },   // 0x32 '2'\n  {   989,  21,  31,  28,    4,  -29 },   // 0x33 '3'\n  {  1071,  20,  28,  28,    4,  -27 },   // 0x34 '4'\n  {  1141,  21,  31,  28,    4,  -29 },   // 0x35 '5'\n  {  1223,  20,  31,  28,    5,  -29 },   // 0x36 '6'\n  {  1301,  20,  30,  28,    4,  -29 },   // 0x37 '7'\n  {  1376,  20,  31,  28,    4,  -29 },   // 0x38 '8'\n  {  1454,  20,  31,  28,    5,  -29 },   // 0x39 '9'\n  {  1532,   7,  22,  28,   11,  -20 },   // 0x3A ':'\n  {  1552,  10,  28,  28,    6,  -20 },   // 0x3B ';'\n  {  1587,  24,  21,  28,    2,  -23 },   // 0x3C '<'\n  {  1650,  24,  14,  28,    2,  -19 },   // 0x3D '='\n  {  1692,  23,  22,  28,    3,  -23 },   // 0x3E '>'\n  {  1756,  20,  29,  28,    5,  -27 },   // 0x3F '?'\n  {  1829,  19,  36,  28,    4,  -28 },   // 0x40 '@'\n  {  1915,  29,  27,  28,   -1,  -26 },   // 0x41 'A'\n  {  2013,  26,  27,  28,    1,  -26 },   // 0x42 'B'\n  {  2101,  25,  29,  28,    2,  -27 },   // 0x43 'C'\n  {  2192,  25,  27,  28,    1,  -26 },   // 0x44 'D'\n  {  2277,  25,  27,  28,    1,  -26 },   // 0x45 'E'\n  {  2362,  25,  27,  28,    1,  -26 },   // 0x46 'F'\n  {  2447,  25,  29,  28,    2,  -27 },   // 0x47 'G'\n  {  2538,  26,  27,  28,    1,  -26 },   // 0x48 'H'\n  {  2626,  19,  27,  28,    5,  -26 },   // 0x49 'I'\n  {  2691,  25,  28,  28,    3,  -26 },   // 0x4A 'J'\n  {  2779,  27,  27,  28,    1,  -26 },   // 0x4B 'K'\n  {  2871,  25,  27,  28,    2,  -26 },   // 0x4C 'L'\n  {  2956,  31,  27,  28,   -1,  -26 },   // 0x4D 'M'\n  {  3061,  28,  27,  28,    0,  -26 },   // 0x4E 'N'\n  {  3156,  27,  29,  28,    1,  -27 },   // 0x4F 'O'\n  {  3254,  24,  27,  28,    1,  -26 },   // 0x50 'P'\n  {  3335,  27,  35,  28,    1,  -27 },   // 0x51 'Q'\n  {  3454,  28,  27,  28,    0,  -26 },   // 0x52 'R'\n  {  3549,  22,  29,  28,    3,  -27 },   // 0x53 'S'\n  {  3629,  25,  27,  28,    2,  -26 },   // 0x54 'T'\n  {  3714,  28,  28,  28,    0,  -26 },   // 0x55 'U'\n  {  3812,  30,  27,  28,   -1,  -26 },   // 0x56 'V'\n  {  3914,  28,  27,  28,    0,  -26 },   // 0x57 'W'\n  {  4009,  26,  27,  28,    1,  -26 },   // 0x58 'X'\n  {  4097,  26,  27,  28,    1,  -26 },   // 0x59 'Y'\n  {  4185,  21,  27,  28,    4,  -26 },   // 0x5A 'Z'\n  {  4256,  10,  37,  28,   12,  -29 },   // 0x5B '['\n  {  4303,  20,  38,  28,    4,  -32 },   // 0x5C '\\'\n  {  4398,  10,  37,  28,    6,  -29 },   // 0x5D ']'\n  {  4445,  20,  15,  28,    4,  -29 },   // 0x5E '^'\n  {  4483,  28,   5,  28,    0,    5 },   // 0x5F '_'\n  {  4501,   9,   8,  28,    8,  -30 },   // 0x60 '`'\n  {  4510,  24,  23,  28,    2,  -21 },   // 0x61 'a'\n  {  4579,  27,  31,  28,    0,  -29 },   // 0x62 'b'\n  {  4684,  24,  23,  28,    3,  -21 },   // 0x63 'c'\n  {  4753,  26,  31,  28,    2,  -29 },   // 0x64 'd'\n  {  4854,  24,  23,  28,    2,  -21 },   // 0x65 'e'\n  {  4923,  22,  30,  28,    4,  -29 },   // 0x66 'f'\n  {  5006,  25,  31,  28,    2,  -21 },   // 0x67 'g'\n  {  5103,  26,  30,  28,    1,  -29 },   // 0x68 'h'\n  {  5201,  21,  29,  28,    4,  -28 },   // 0x69 'i'\n  {  5278,  17,  38,  28,    5,  -28 },   // 0x6A 'j'\n  {  5359,  25,  30,  28,    2,  -29 },   // 0x6B 'k'\n  {  5453,  21,  30,  28,    4,  -29 },   // 0x6C 'l'\n  {  5532,  30,  22,  28,   -1,  -21 },   // 0x6D 'm'\n  {  5615,  25,  22,  28,    1,  -21 },   // 0x6E 'n'\n  {  5684,  25,  23,  28,    2,  -21 },   // 0x6F 'o'\n  {  5756,  28,  31,  28,    0,  -21 },   // 0x70 'p'\n  {  5865,  28,  31,  28,    1,  -21 },   // 0x71 'q'\n  {  5974,  24,  22,  28,    3,  -21 },   // 0x72 'r'\n  {  6040,  21,  23,  28,    4,  -21 },   // 0x73 's'\n  {  6101,  23,  28,  28,    1,  -26 },   // 0x74 't'\n  {  6182,  25,  22,  28,    1,  -20 },   // 0x75 'u'\n  {  6251,  28,  21,  28,    0,  -20 },   // 0x76 'v'\n  {  6325,  28,  21,  28,    0,  -20 },   // 0x77 'w'\n  {  6399,  26,  21,  28,    1,  -20 },   // 0x78 'x'\n  {  6468,  26,  30,  28,    1,  -20 },   // 0x79 'y'\n  {  6566,  19,  21,  28,    5,  -20 },   // 0x7A 'z'\n  {  6616,  14,  37,  28,    7,  -29 },   // 0x7B '{'\n  {  6681,   5,  36,  28,   12,  -28 },   // 0x7C '|'\n  {  6704,  14,  37,  28,    8,  -29 },   // 0x7D '}'\n  {  6769,  22,  10,  28,    3,  -17 } }; // 0x7E '~'\n\nconst GFXfont FreeMonoBold24pt7b PROGMEM = {\n  (uint8_t  *)FreeMonoBold24pt7bBitmaps,\n  (GFXglyph *)FreeMonoBold24pt7bGlyphs,\n  0x20, 0x7E, 47 };\n\n// Approx. 7469 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeMonoBold9pt7b.h",
    "content": "const uint8_t FreeMonoBold9pt7bBitmaps[] PROGMEM = {\n  0xFF, 0xFF, 0xD2, 0x1F, 0x80, 0xEC, 0x89, 0x12, 0x24, 0x40, 0x36, 0x36,\n  0x36, 0x7F, 0x7F, 0x36, 0xFF, 0xFF, 0x3C, 0x3C, 0x3C, 0x00, 0x18, 0xFF,\n  0xFE, 0x3C, 0x1F, 0x1F, 0x83, 0x46, 0x8D, 0xF0, 0xC1, 0x83, 0x00, 0x61,\n  0x22, 0x44, 0x86, 0x67, 0x37, 0x11, 0x22, 0x4C, 0x70, 0x3C, 0x7E, 0x60,\n  0x60, 0x30, 0x7B, 0xDF, 0xCE, 0xFF, 0x7F, 0xC9, 0x24, 0x37, 0x66, 0xCC,\n  0xCC, 0xCC, 0x66, 0x31, 0xCE, 0x66, 0x33, 0x33, 0x33, 0x66, 0xC8, 0x18,\n  0x18, 0xFF, 0xFF, 0x3C, 0x3C, 0x66, 0x18, 0x18, 0x18, 0xFF, 0xFF, 0x18,\n  0x18, 0x18, 0x18, 0x6B, 0x48, 0xFF, 0xFF, 0xC0, 0xF0, 0x02, 0x0C, 0x18,\n  0x60, 0xC3, 0x06, 0x0C, 0x30, 0x61, 0x83, 0x0C, 0x18, 0x20, 0x00, 0x38,\n  0xFB, 0xBE, 0x3C, 0x78, 0xF1, 0xE3, 0xC7, 0xDD, 0xF1, 0xC0, 0x38, 0xF3,\n  0x60, 0xC1, 0x83, 0x06, 0x0C, 0x18, 0xFD, 0xF8, 0x3C, 0xFE, 0xC7, 0x03,\n  0x03, 0x06, 0x0C, 0x18, 0x70, 0xE3, 0xFF, 0xFF, 0x7C, 0xFE, 0x03, 0x03,\n  0x03, 0x1E, 0x1E, 0x07, 0x03, 0x03, 0xFE, 0x7C, 0x1C, 0x38, 0xB1, 0x64,\n  0xD9, 0xBF, 0xFF, 0x3E, 0x7C, 0x7E, 0x3F, 0x18, 0x0F, 0xC7, 0xF3, 0x1C,\n  0x06, 0x03, 0xC3, 0xFF, 0x9F, 0x80, 0x0F, 0x3F, 0x30, 0x60, 0x60, 0xDC,\n  0xFE, 0xE3, 0xC3, 0x63, 0x7E, 0x3C, 0xFF, 0xFF, 0xC3, 0x03, 0x06, 0x06,\n  0x06, 0x0C, 0x0C, 0x0C, 0x18, 0x38, 0xFB, 0x1E, 0x3C, 0x6F, 0x9F, 0x63,\n  0xC7, 0x8F, 0xF1, 0xC0, 0x3C, 0x7E, 0xE6, 0xC3, 0xC3, 0xE7, 0x7F, 0x3B,\n  0x06, 0x0E, 0xFC, 0xF0, 0xF0, 0x0F, 0x6C, 0x00, 0x1A, 0xD2, 0x00, 0x01,\n  0x83, 0x87, 0x0E, 0x0F, 0x80, 0xE0, 0x1C, 0x03, 0xFF, 0xFF, 0xC0, 0x00,\n  0x0F, 0xFF, 0xFC, 0xC0, 0x78, 0x0F, 0x01, 0xE0, 0xF9, 0xE3, 0xC1, 0x80,\n  0x7C, 0xFE, 0xC7, 0x03, 0x0E, 0x1C, 0x00, 0x00, 0x00, 0x30, 0x30, 0x1E,\n  0x1F, 0x1C, 0xDC, 0x6C, 0x76, 0x7B, 0x6D, 0xB6, 0xDB, 0x6F, 0xF3, 0xFC,\n  0x06, 0x33, 0xF8, 0x78, 0x3C, 0x07, 0xC0, 0x38, 0x05, 0x81, 0xB0, 0x36,\n  0x0F, 0xE1, 0xFC, 0x71, 0xDF, 0x7F, 0xEF, 0x80, 0xFF, 0x3F, 0xE6, 0x19,\n  0x86, 0x7F, 0x1F, 0xE6, 0x1D, 0x83, 0x60, 0xFF, 0xFF, 0xF0, 0x1F, 0xBF,\n  0xD8, 0xF8, 0x3C, 0x06, 0x03, 0x01, 0x80, 0x61, 0xBF, 0xC7, 0xC0, 0xFE,\n  0x3F, 0xE6, 0x19, 0x83, 0x60, 0xD8, 0x36, 0x0D, 0x83, 0x61, 0xBF, 0xEF,\n  0xE0, 0xFF, 0xFF, 0xD8, 0x6D, 0xB7, 0xC3, 0xE1, 0xB0, 0xC3, 0x61, 0xFF,\n  0xFF, 0xE0, 0xFF, 0xFF, 0xD8, 0x6D, 0xB7, 0xC3, 0xE1, 0xB0, 0xC0, 0x60,\n  0x7C, 0x3E, 0x00, 0x1F, 0x9F, 0xE6, 0x1B, 0x06, 0xC0, 0x30, 0x0C, 0x7F,\n  0x1F, 0xE1, 0x9F, 0xE3, 0xF0, 0xF7, 0xFB, 0xD8, 0xCC, 0x66, 0x33, 0xF9,\n  0xFC, 0xC6, 0x63, 0x7B, 0xFD, 0xE0, 0xFF, 0xF3, 0x0C, 0x30, 0xC3, 0x0C,\n  0x33, 0xFF, 0xC0, 0x1F, 0xC7, 0xF0, 0x30, 0x0C, 0x03, 0x00, 0xCC, 0x33,\n  0x0C, 0xC7, 0x3F, 0x87, 0xC0, 0xF7, 0xBD, 0xE6, 0x61, 0xB0, 0x78, 0x1F,\n  0x06, 0xE1, 0x98, 0x63, 0x3C, 0xFF, 0x3C, 0xFC, 0x7E, 0x0C, 0x06, 0x03,\n  0x01, 0x80, 0xC6, 0x63, 0x31, 0xFF, 0xFF, 0xE0, 0xE0, 0xFE, 0x3D, 0xC7,\n  0x3D, 0xE7, 0xBC, 0xD7, 0x9B, 0xB3, 0x76, 0x60, 0xDE, 0x3F, 0xC7, 0x80,\n  0xE1, 0xFE, 0x3D, 0xE3, 0x3C, 0x66, 0xCC, 0xDD, 0x99, 0xB3, 0x1E, 0x63,\n  0xDE, 0x3B, 0xC3, 0x00, 0x1F, 0x07, 0xF1, 0xC7, 0x70, 0x7C, 0x07, 0x80,\n  0xF0, 0x1F, 0x07, 0x71, 0xC7, 0xF0, 0x7C, 0x00, 0xFE, 0x7F, 0x98, 0x6C,\n  0x36, 0x1B, 0xF9, 0xF8, 0xC0, 0x60, 0x7C, 0x3E, 0x00, 0x1F, 0x07, 0xF1,\n  0xC7, 0x70, 0x7C, 0x07, 0x80, 0xF0, 0x1F, 0x07, 0x71, 0xC7, 0xF0, 0x7C,\n  0x0C, 0x33, 0xFE, 0x7F, 0x80, 0xFC, 0x7F, 0x18, 0xCC, 0x66, 0x73, 0xF1,\n  0xF0, 0xCC, 0x63, 0x7D, 0xFE, 0x60, 0x3F, 0xBF, 0xF0, 0x78, 0x0F, 0x03,\n  0xF8, 0x3F, 0x83, 0xC3, 0xFF, 0xBF, 0x80, 0xFF, 0xFF, 0xF6, 0x7B, 0x3D,\n  0x98, 0xC0, 0x60, 0x30, 0x18, 0x3F, 0x1F, 0x80, 0xF1, 0xFE, 0x3D, 0x83,\n  0x30, 0x66, 0x0C, 0xC1, 0x98, 0x33, 0x06, 0x60, 0xC7, 0xF0, 0x7C, 0x00,\n  0xFB, 0xFF, 0x7D, 0xC3, 0x18, 0xC3, 0x18, 0x36, 0x06, 0xC0, 0x50, 0x0E,\n  0x01, 0xC0, 0x10, 0x00, 0xFB, 0xFE, 0xF6, 0x0D, 0x93, 0x6E, 0xDB, 0xB7,\n  0xAD, 0xEE, 0x7B, 0x8E, 0xE3, 0x18, 0xF3, 0xFC, 0xF7, 0x38, 0xFC, 0x1E,\n  0x03, 0x01, 0xE0, 0xCC, 0x73, 0xBC, 0xFF, 0x3C, 0xF3, 0xFC, 0xF7, 0x38,\n  0xCC, 0x1E, 0x07, 0x80, 0xC0, 0x30, 0x0C, 0x0F, 0xC3, 0xF0, 0xFE, 0xFE,\n  0xC6, 0xCC, 0x18, 0x18, 0x30, 0x63, 0xC3, 0xFF, 0xFF, 0xFF, 0xCC, 0xCC,\n  0xCC, 0xCC, 0xCC, 0xFF, 0x01, 0x03, 0x06, 0x06, 0x0C, 0x0C, 0x18, 0x18,\n  0x30, 0x30, 0x60, 0x60, 0xC0, 0x80, 0xFF, 0x33, 0x33, 0x33, 0x33, 0x33,\n  0xFF, 0x10, 0x71, 0xE3, 0x6C, 0x70, 0x40, 0xFF, 0xFF, 0xFC, 0x88, 0x80,\n  0x7E, 0x3F, 0x8F, 0xCF, 0xEE, 0x36, 0x1B, 0xFE, 0xFF, 0xE0, 0x38, 0x06,\n  0x01, 0xBC, 0x7F, 0x9C, 0x76, 0x0D, 0x83, 0x71, 0xFF, 0xEE, 0xF0, 0x3F,\n  0xBF, 0xF8, 0x78, 0x3C, 0x07, 0x05, 0xFE, 0x7E, 0x03, 0x80, 0xE0, 0x18,\n  0xF6, 0x7F, 0xB8, 0xEC, 0x1B, 0x06, 0xE3, 0x9F, 0xF3, 0xFC, 0x3E, 0x3F,\n  0xB0, 0xFF, 0xFF, 0xFE, 0x01, 0xFE, 0x7E, 0x1F, 0x3F, 0x30, 0x7E, 0x7E,\n  0x30, 0x30, 0x30, 0x30, 0xFE, 0xFE, 0x3F, 0xBF, 0xF9, 0xD8, 0x6C, 0x37,\n  0x39, 0xFC, 0x76, 0x03, 0x01, 0x8F, 0xC7, 0xC0, 0xE0, 0x70, 0x18, 0x0D,\n  0xC7, 0xF3, 0x99, 0x8C, 0xC6, 0x63, 0x7B, 0xFD, 0xE0, 0x18, 0x18, 0x00,\n  0x78, 0x78, 0x18, 0x18, 0x18, 0x18, 0xFF, 0xFF, 0x18, 0x60, 0x3F, 0xFC,\n  0x30, 0xC3, 0x0C, 0x30, 0xC3, 0x0F, 0xFF, 0x80, 0xE0, 0x70, 0x18, 0x0D,\n  0xE6, 0xF3, 0xE1, 0xE0, 0xF8, 0x6E, 0x73, 0xF9, 0xE0, 0x78, 0x78, 0x18,\n  0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0xFF, 0xFF, 0xFD, 0x9F, 0xF9, 0x9B,\n  0x33, 0x66, 0x6C, 0xCD, 0xBD, 0xFF, 0xBF, 0xEE, 0x7F, 0x98, 0xCC, 0x66,\n  0x33, 0x1B, 0xDF, 0xEF, 0x3E, 0x3F, 0xB8, 0xF8, 0x3C, 0x1F, 0x1D, 0xFC,\n  0x7C, 0xEF, 0x1F, 0xF9, 0xC3, 0xB0, 0x36, 0x06, 0xE1, 0xDF, 0xF3, 0x78,\n  0x60, 0x0C, 0x03, 0xE0, 0x7C, 0x00, 0x1E, 0xEF, 0xFF, 0x87, 0x60, 0x6C,\n  0x0D, 0xC3, 0x9F, 0xF0, 0xF6, 0x00, 0xC0, 0x18, 0x0F, 0x81, 0xF0, 0x77,\n  0xBF, 0xCF, 0x06, 0x03, 0x01, 0x83, 0xF9, 0xFC, 0x3F, 0xFF, 0xC3, 0xFC,\n  0x3F, 0xC3, 0xFF, 0xFC, 0x60, 0x60, 0x60, 0xFE, 0xFE, 0x60, 0x60, 0x60,\n  0x61, 0x7F, 0x3E, 0xE7, 0x73, 0x98, 0xCC, 0x66, 0x33, 0x19, 0xFE, 0x7F,\n  0xFB, 0xFF, 0x7C, 0xC6, 0x18, 0xC1, 0xB0, 0x36, 0x03, 0x80, 0x70, 0xF1,\n  0xFE, 0x3D, 0xBB, 0x37, 0x63, 0xF8, 0x77, 0x0E, 0xE1, 0x8C, 0xF7, 0xFB,\n  0xCD, 0x83, 0x83, 0xC3, 0xBB, 0xDF, 0xEF, 0xF3, 0xFC, 0xF6, 0x18, 0xCC,\n  0x33, 0x07, 0x81, 0xE0, 0x30, 0x0C, 0x06, 0x0F, 0xC3, 0xF0, 0xFF, 0xFF,\n  0x30, 0xC3, 0x0C, 0x7F, 0xFF, 0x37, 0x66, 0x66, 0xCC, 0x66, 0x66, 0x73,\n  0xFF, 0xFF, 0xFF, 0xF0, 0xCE, 0x66, 0x66, 0x33, 0x66, 0x66, 0xEC, 0x70,\n  0x7C, 0xF3, 0xC0, 0xC0 };\n\nconst GFXglyph FreeMonoBold9pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,  11,    0,    1 },   // 0x20 ' '\n  {     0,   3,  11,  11,    4,  -10 },   // 0x21 '!'\n  {     5,   7,   5,  11,    2,  -10 },   // 0x22 '\"'\n  {    10,   8,  12,  11,    1,  -10 },   // 0x23 '#'\n  {    22,   7,  14,  11,    2,  -11 },   // 0x24 '$'\n  {    35,   7,  11,  11,    2,  -10 },   // 0x25 '%'\n  {    45,   8,  10,  11,    1,   -9 },   // 0x26 '&'\n  {    55,   3,   5,  11,    4,  -10 },   // 0x27 '''\n  {    57,   4,  14,  11,    5,  -10 },   // 0x28 '('\n  {    64,   4,  14,  11,    2,  -10 },   // 0x29 ')'\n  {    71,   8,   7,  11,    2,  -10 },   // 0x2A '*'\n  {    78,   8,   9,  11,    2,   -8 },   // 0x2B '+'\n  {    87,   3,   5,  11,    3,   -1 },   // 0x2C ','\n  {    89,   9,   2,  11,    1,   -5 },   // 0x2D '-'\n  {    92,   2,   2,  11,    4,   -1 },   // 0x2E '.'\n  {    93,   7,  15,  11,    2,  -12 },   // 0x2F '/'\n  {   107,   7,  12,  11,    2,  -11 },   // 0x30 '0'\n  {   118,   7,  11,  11,    2,  -10 },   // 0x31 '1'\n  {   128,   8,  12,  11,    1,  -11 },   // 0x32 '2'\n  {   140,   8,  12,  11,    2,  -11 },   // 0x33 '3'\n  {   152,   7,  10,  11,    2,   -9 },   // 0x34 '4'\n  {   161,   9,  11,  11,    1,  -10 },   // 0x35 '5'\n  {   174,   8,  12,  11,    2,  -11 },   // 0x36 '6'\n  {   186,   8,  11,  11,    1,  -10 },   // 0x37 '7'\n  {   197,   7,  12,  11,    2,  -11 },   // 0x38 '8'\n  {   208,   8,  12,  11,    2,  -11 },   // 0x39 '9'\n  {   220,   2,   8,  11,    4,   -7 },   // 0x3A ':'\n  {   222,   3,  11,  11,    3,   -7 },   // 0x3B ';'\n  {   227,   9,   8,  11,    1,   -8 },   // 0x3C '<'\n  {   236,   9,   6,  11,    1,   -7 },   // 0x3D '='\n  {   243,   9,   8,  11,    1,   -8 },   // 0x3E '>'\n  {   252,   8,  11,  11,    2,  -10 },   // 0x3F '?'\n  {   263,   9,  15,  11,    1,  -11 },   // 0x40 '@'\n  {   280,  11,  11,  11,    0,  -10 },   // 0x41 'A'\n  {   296,  10,  11,  11,    1,  -10 },   // 0x42 'B'\n  {   310,   9,  11,  11,    1,  -10 },   // 0x43 'C'\n  {   323,  10,  11,  11,    0,  -10 },   // 0x44 'D'\n  {   337,   9,  11,  11,    1,  -10 },   // 0x45 'E'\n  {   350,   9,  11,  11,    1,  -10 },   // 0x46 'F'\n  {   363,  10,  11,  11,    1,  -10 },   // 0x47 'G'\n  {   377,   9,  11,  11,    1,  -10 },   // 0x48 'H'\n  {   390,   6,  11,  11,    3,  -10 },   // 0x49 'I'\n  {   399,  10,  11,  11,    1,  -10 },   // 0x4A 'J'\n  {   413,  10,  11,  11,    1,  -10 },   // 0x4B 'K'\n  {   427,   9,  11,  11,    1,  -10 },   // 0x4C 'L'\n  {   440,  11,  11,  11,    0,  -10 },   // 0x4D 'M'\n  {   456,  11,  11,  11,    0,  -10 },   // 0x4E 'N'\n  {   472,  11,  11,  11,    0,  -10 },   // 0x4F 'O'\n  {   488,   9,  11,  11,    1,  -10 },   // 0x50 'P'\n  {   501,  11,  14,  11,    0,  -10 },   // 0x51 'Q'\n  {   521,   9,  11,  11,    1,  -10 },   // 0x52 'R'\n  {   534,   9,  11,  11,    1,  -10 },   // 0x53 'S'\n  {   547,   9,  11,  11,    1,  -10 },   // 0x54 'T'\n  {   560,  11,  11,  11,    0,  -10 },   // 0x55 'U'\n  {   576,  11,  11,  11,    0,  -10 },   // 0x56 'V'\n  {   592,  10,  11,  11,    0,  -10 },   // 0x57 'W'\n  {   606,  10,  11,  11,    0,  -10 },   // 0x58 'X'\n  {   620,  10,  11,  11,    0,  -10 },   // 0x59 'Y'\n  {   634,   8,  11,  11,    2,  -10 },   // 0x5A 'Z'\n  {   645,   4,  14,  11,    5,  -10 },   // 0x5B '['\n  {   652,   7,  15,  11,    2,  -12 },   // 0x5C '\\'\n  {   666,   4,  14,  11,    2,  -10 },   // 0x5D ']'\n  {   673,   7,   6,  11,    2,  -11 },   // 0x5E '^'\n  {   679,  11,   2,  11,    0,    3 },   // 0x5F '_'\n  {   682,   3,   3,  11,    3,  -11 },   // 0x60 '`'\n  {   684,   9,   8,  11,    1,   -7 },   // 0x61 'a'\n  {   693,  10,  11,  11,    0,  -10 },   // 0x62 'b'\n  {   707,   9,   8,  11,    1,   -7 },   // 0x63 'c'\n  {   716,  10,  11,  11,    1,  -10 },   // 0x64 'd'\n  {   730,   9,   8,  11,    1,   -7 },   // 0x65 'e'\n  {   739,   8,  11,  11,    2,  -10 },   // 0x66 'f'\n  {   750,   9,  12,  11,    1,   -7 },   // 0x67 'g'\n  {   764,   9,  11,  11,    1,  -10 },   // 0x68 'h'\n  {   777,   8,  11,  11,    2,  -10 },   // 0x69 'i'\n  {   788,   6,  15,  11,    2,  -10 },   // 0x6A 'j'\n  {   800,   9,  11,  11,    1,  -10 },   // 0x6B 'k'\n  {   813,   8,  11,  11,    2,  -10 },   // 0x6C 'l'\n  {   824,  11,   8,  11,    0,   -7 },   // 0x6D 'm'\n  {   835,   9,   8,  11,    1,   -7 },   // 0x6E 'n'\n  {   844,   9,   8,  11,    1,   -7 },   // 0x6F 'o'\n  {   853,  11,  12,  11,    0,   -7 },   // 0x70 'p'\n  {   870,  11,  12,  11,    0,   -7 },   // 0x71 'q'\n  {   887,   9,   8,  11,    1,   -7 },   // 0x72 'r'\n  {   896,   8,   8,  11,    2,   -7 },   // 0x73 's'\n  {   904,   8,  11,  11,    1,  -10 },   // 0x74 't'\n  {   915,   9,   8,  11,    1,   -7 },   // 0x75 'u'\n  {   924,  11,   8,  11,    0,   -7 },   // 0x76 'v'\n  {   935,  11,   8,  11,    0,   -7 },   // 0x77 'w'\n  {   946,   9,   8,  11,    1,   -7 },   // 0x78 'x'\n  {   955,  10,  12,  11,    0,   -7 },   // 0x79 'y'\n  {   970,   7,   8,  11,    2,   -7 },   // 0x7A 'z'\n  {   977,   4,  14,  11,    3,  -10 },   // 0x7B '{'\n  {   984,   2,  14,  11,    5,  -10 },   // 0x7C '|'\n  {   988,   4,  14,  11,    4,  -10 },   // 0x7D '}'\n  {   995,   9,   4,  11,    1,   -6 } }; // 0x7E '~'\n\nconst GFXfont FreeMonoBold9pt7b PROGMEM = {\n  (uint8_t  *)FreeMonoBold9pt7bBitmaps,\n  (GFXglyph *)FreeMonoBold9pt7bGlyphs,\n  0x20, 0x7E, 18 };\n\n// Approx. 1672 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeMonoBoldOblique12pt7b.h",
    "content": "const uint8_t FreeMonoBoldOblique12pt7bBitmaps[] PROGMEM = {\n  0x1C, 0xF3, 0xCE, 0x38, 0xE7, 0x1C, 0x61, 0x86, 0x00, 0x63, 0x8C, 0x00,\n  0xE7, 0xE7, 0xE6, 0xC6, 0xC6, 0xC4, 0x84, 0x03, 0x30, 0x19, 0x81, 0xDC,\n  0x0C, 0xE0, 0x66, 0x1F, 0xFC, 0xFF, 0xE1, 0x98, 0x0C, 0xC0, 0xEE, 0x06,\n  0x70, 0xFF, 0xCF, 0xFE, 0x1D, 0xC0, 0xCC, 0x06, 0x60, 0x77, 0x03, 0x30,\n  0x00, 0x01, 0x00, 0x70, 0x0C, 0x07, 0xF1, 0xFE, 0x71, 0xCC, 0x11, 0x80,\n  0x3F, 0x03, 0xF0, 0x0F, 0x20, 0x6E, 0x0D, 0xC3, 0x3F, 0xE7, 0xF8, 0x1C,\n  0x03, 0x00, 0x60, 0x0C, 0x00, 0x0E, 0x03, 0xE0, 0xC4, 0x10, 0x82, 0x30,\n  0x7C, 0x07, 0x78, 0x7C, 0x7F, 0x19, 0xF0, 0x62, 0x08, 0x41, 0x18, 0x3E,\n  0x03, 0x80, 0x07, 0xC1, 0xF8, 0x62, 0x0C, 0x01, 0x80, 0x38, 0x0F, 0x03,\n  0xF7, 0x6F, 0xD8, 0xF3, 0x1E, 0x7F, 0xE7, 0xF8, 0xFF, 0x6D, 0x20, 0x06,\n  0x1C, 0x70, 0xC3, 0x06, 0x18, 0x30, 0xC1, 0x83, 0x06, 0x0C, 0x18, 0x30,\n  0x70, 0x60, 0xC1, 0x00, 0x0C, 0x18, 0x38, 0x30, 0x60, 0xC1, 0x83, 0x06,\n  0x0C, 0x30, 0x61, 0xC3, 0x0E, 0x38, 0x61, 0xC2, 0x00, 0x06, 0x00, 0xC0,\n  0x18, 0x3F, 0x7F, 0xFE, 0xFF, 0x07, 0x81, 0xF8, 0x77, 0x0C, 0x60, 0x03,\n  0x00, 0x70, 0x07, 0x00, 0x60, 0x06, 0x0F, 0xFF, 0xFF, 0xF0, 0xE0, 0x0C,\n  0x00, 0xC0, 0x0C, 0x01, 0xC0, 0x18, 0x00, 0x1C, 0xE3, 0x1C, 0x63, 0x08,\n  0x00, 0x7F, 0xFF, 0xFF, 0xC0, 0x7F, 0x00, 0x00, 0x08, 0x00, 0x70, 0x01,\n  0x80, 0x0E, 0x00, 0x70, 0x03, 0x80, 0x0C, 0x00, 0x70, 0x03, 0x80, 0x0C,\n  0x00, 0x70, 0x03, 0x80, 0x0C, 0x00, 0x70, 0x03, 0x80, 0x0C, 0x00, 0x70,\n  0x03, 0x80, 0x0C, 0x00, 0x20, 0x00, 0x07, 0x83, 0xF8, 0xE3, 0x98, 0x37,\n  0x06, 0xC0, 0xD8, 0x1B, 0x03, 0xE0, 0xF8, 0x1B, 0x03, 0x60, 0xEE, 0x38,\n  0xFE, 0x0F, 0x00, 0x03, 0xC1, 0xF0, 0x7E, 0x0C, 0xC0, 0x38, 0x07, 0x00,\n  0xC0, 0x18, 0x07, 0x00, 0xE0, 0x18, 0x03, 0x00, 0x61, 0xFF, 0xFF, 0xF0,\n  0x03, 0xE0, 0x3F, 0x83, 0x8E, 0x38, 0x31, 0x81, 0x80, 0x18, 0x01, 0xC0,\n  0x1C, 0x01, 0xC0, 0x38, 0x03, 0x80, 0x38, 0x47, 0x87, 0x3F, 0xF3, 0xFF,\n  0x80, 0x07, 0xC1, 0xFF, 0x18, 0x70, 0x03, 0x00, 0x30, 0x06, 0x07, 0xC0,\n  0x7C, 0x00, 0xE0, 0x06, 0x00, 0x60, 0x06, 0xC1, 0xCF, 0xF8, 0x7E, 0x00,\n  0x01, 0xE0, 0x3C, 0x0F, 0x03, 0x60, 0xCC, 0x3B, 0x8E, 0x63, 0x8C, 0x61,\n  0x9F, 0xFB, 0xFF, 0x01, 0x81, 0xF8, 0x3F, 0x00, 0x0F, 0xF1, 0xFE, 0x18,\n  0x01, 0x80, 0x18, 0x03, 0xF8, 0x3F, 0xC3, 0x8E, 0x00, 0x60, 0x06, 0x00,\n  0x60, 0x0C, 0xC1, 0xCF, 0xF8, 0x7E, 0x00, 0x03, 0xE1, 0xFC, 0x70, 0x1C,\n  0x03, 0x00, 0xC0, 0x1B, 0xC7, 0xFC, 0xF3, 0x98, 0x33, 0x06, 0x60, 0xCE,\n  0x30, 0xFC, 0x0F, 0x00, 0xFF, 0xFF, 0xFB, 0x07, 0x60, 0xC0, 0x38, 0x06,\n  0x01, 0xC0, 0x30, 0x0E, 0x01, 0x80, 0x70, 0x1C, 0x03, 0x80, 0x60, 0x08,\n  0x00, 0x07, 0x83, 0xF8, 0xE3, 0xB0, 0x36, 0x06, 0xC0, 0xDC, 0x31, 0xFC,\n  0x3F, 0x8C, 0x3B, 0x03, 0x60, 0x6C, 0x39, 0xFE, 0x1F, 0x00, 0x07, 0x81,\n  0xF8, 0x63, 0x98, 0x33, 0x06, 0x60, 0xCE, 0x79, 0xFF, 0x1E, 0xC0, 0x18,\n  0x06, 0x01, 0xC0, 0x71, 0xFC, 0x3E, 0x00, 0x19, 0xCC, 0x00, 0x00, 0x00,\n  0x67, 0x30, 0x06, 0x1C, 0x30, 0x00, 0x00, 0x00, 0x00, 0x38, 0x71, 0xC3,\n  0x0E, 0x18, 0x20, 0x00, 0x00, 0x18, 0x03, 0xC0, 0x7C, 0x1F, 0x03, 0xE0,\n  0x3E, 0x00, 0x7C, 0x01, 0xF0, 0x03, 0xE0, 0x07, 0x80, 0x08, 0x7F, 0xFB,\n  0xFF, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x7F, 0xFB, 0xFF, 0xC0, 0x30, 0x01,\n  0xE0, 0x07, 0xC0, 0x0F, 0x00, 0x3E, 0x00, 0x7C, 0x1F, 0x03, 0xE0, 0x7C,\n  0x07, 0x80, 0x20, 0x00, 0x3E, 0x7F, 0xB0, 0xF8, 0x30, 0x18, 0x1C, 0x1C,\n  0x3C, 0x38, 0x18, 0x00, 0x06, 0x07, 0x03, 0x00, 0x03, 0xC0, 0x7E, 0x0C,\n  0x71, 0x83, 0x30, 0x33, 0x0F, 0x33, 0xE6, 0x76, 0x6C, 0x66, 0xC6, 0x6C,\n  0x6C, 0xFC, 0xC7, 0xEC, 0x00, 0xC0, 0x0C, 0x00, 0xE3, 0x07, 0xF0, 0x3C,\n  0x00, 0x07, 0xF0, 0x1F, 0xE0, 0x07, 0xC0, 0x1F, 0x80, 0x3B, 0x00, 0xE7,\n  0x01, 0x8E, 0x07, 0x1C, 0x1F, 0xF8, 0x3F, 0xF0, 0xE0, 0x71, 0x80, 0xEF,\n  0xC7, 0xFF, 0x8F, 0xC0, 0x3F, 0xF1, 0xFF, 0xC3, 0x06, 0x38, 0x31, 0xC1,\n  0x8C, 0x18, 0x7F, 0xC3, 0xFE, 0x38, 0x39, 0xC0, 0xCC, 0x06, 0x60, 0x6F,\n  0xFF, 0x7F, 0xE0, 0x03, 0xEC, 0x3F, 0xF1, 0xC3, 0x8C, 0x06, 0x60, 0x19,\n  0x80, 0x0C, 0x00, 0x30, 0x00, 0xC0, 0x03, 0x00, 0x0C, 0x03, 0x3C, 0x1C,\n  0x7F, 0xE0, 0x7E, 0x00, 0x3F, 0xE1, 0xFF, 0x87, 0x0C, 0x30, 0x31, 0x81,\n  0x8C, 0x0C, 0xE0, 0x67, 0x03, 0x30, 0x31, 0x81, 0x8C, 0x0C, 0xE1, 0xCF,\n  0xFC, 0x7F, 0x80, 0x1F, 0xFE, 0x3F, 0xFC, 0x38, 0x38, 0x70, 0x70, 0xCC,\n  0xC1, 0x98, 0x03, 0xF0, 0x0F, 0xE0, 0x1D, 0x80, 0x31, 0x18, 0x60, 0x70,\n  0xC0, 0xE7, 0xFF, 0x9F, 0xFF, 0x00, 0x1F, 0xFF, 0x1F, 0xFE, 0x0E, 0x06,\n  0x0C, 0x0E, 0x0C, 0xC4, 0x0C, 0xC0, 0x1F, 0xC0, 0x1F, 0xC0, 0x19, 0xC0,\n  0x19, 0x80, 0x18, 0x00, 0x38, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0x07, 0xEC,\n  0x7F, 0xF3, 0x83, 0x9C, 0x06, 0x60, 0x19, 0x80, 0x0C, 0x00, 0x30, 0xFE,\n  0xC3, 0xFB, 0x01, 0xCC, 0x07, 0x3C, 0x38, 0x7F, 0xE0, 0x7E, 0x00, 0x0F,\n  0xBF, 0x1F, 0xBE, 0x0E, 0x0C, 0x0C, 0x0C, 0x0C, 0x1C, 0x0C, 0x1C, 0x1F,\n  0xF8, 0x1F, 0xF8, 0x18, 0x18, 0x18, 0x38, 0x18, 0x38, 0x38, 0x30, 0x7C,\n  0xFC, 0xFC, 0xF8, 0x3F, 0xF3, 0xFF, 0x03, 0x00, 0x70, 0x07, 0x00, 0x60,\n  0x06, 0x00, 0x60, 0x0E, 0x00, 0xE0, 0x0E, 0x00, 0xC0, 0xFF, 0xCF, 0xFC,\n  0x03, 0xFF, 0x03, 0xFF, 0x00, 0x38, 0x00, 0x30, 0x00, 0x30, 0x00, 0x30,\n  0x00, 0x70, 0x20, 0x70, 0x60, 0x60, 0x60, 0x60, 0x60, 0xE0, 0xE1, 0xC0,\n  0xFF, 0x80, 0x3F, 0x00, 0x1F, 0x9F, 0x1F, 0x9E, 0x0E, 0x38, 0x0C, 0x70,\n  0x0C, 0xE0, 0x0F, 0xC0, 0x1F, 0xC0, 0x1F, 0xE0, 0x1C, 0xE0, 0x18, 0x60,\n  0x18, 0x70, 0x38, 0x70, 0xFE, 0x3C, 0xFC, 0x3C, 0x3F, 0xC1, 0xFE, 0x01,\n  0x80, 0x1C, 0x00, 0xE0, 0x06, 0x00, 0x30, 0x01, 0x80, 0x1C, 0x18, 0xE0,\n  0xC6, 0x06, 0x30, 0x7F, 0xFF, 0xFF, 0xF8, 0x1E, 0x07, 0x87, 0x81, 0xE0,\n  0xF0, 0xF0, 0x7C, 0x7C, 0x1F, 0x1F, 0x06, 0xCF, 0x81, 0xBF, 0x60, 0xEF,\n  0x98, 0x3B, 0xEE, 0x0C, 0x73, 0x83, 0x1C, 0xC0, 0xC0, 0x30, 0xFC, 0x7E,\n  0x3F, 0x1F, 0x80, 0x3C, 0x3F, 0x3E, 0x3F, 0x1E, 0x0C, 0x1F, 0x1C, 0x1F,\n  0x1C, 0x1B, 0x98, 0x3B, 0x98, 0x3B, 0x98, 0x31, 0xF8, 0x31, 0xF8, 0x30,\n  0xF0, 0x70, 0xF0, 0xFC, 0x70, 0xF8, 0x70, 0x03, 0xE0, 0x3F, 0xE1, 0xC3,\n  0x8C, 0x07, 0x60, 0x0D, 0x80, 0x3C, 0x00, 0xF0, 0x03, 0xC0, 0x1B, 0x00,\n  0x6E, 0x03, 0x1C, 0x38, 0x7F, 0xC0, 0x7C, 0x00, 0x3F, 0xE1, 0xFF, 0x83,\n  0x0E, 0x38, 0x31, 0xC1, 0x8C, 0x0C, 0x60, 0xC3, 0xFC, 0x3F, 0xC1, 0xC0,\n  0x0C, 0x00, 0x60, 0x0F, 0xF0, 0x7F, 0x80, 0x03, 0xE0, 0x3F, 0xE1, 0xC3,\n  0x8C, 0x07, 0x60, 0x0D, 0x80, 0x3C, 0x00, 0xF0, 0x03, 0xC0, 0x1B, 0x00,\n  0x6E, 0x03, 0x1C, 0x38, 0x7F, 0xC0, 0xFC, 0x03, 0x02, 0x1F, 0xFC, 0xFF,\n  0xE0, 0x1F, 0xF0, 0x3F, 0xF0, 0x38, 0x70, 0x60, 0x60, 0xC0, 0xC1, 0x87,\n  0x07, 0xFC, 0x0F, 0xF0, 0x18, 0xF0, 0x30, 0xE0, 0x60, 0xC1, 0xC1, 0xCF,\n  0xE1, 0xFF, 0xC3, 0xC0, 0x0F, 0xB1, 0xFF, 0x30, 0xE6, 0x06, 0x60, 0x67,\n  0x80, 0x7F, 0x01, 0xFC, 0x01, 0xC4, 0x0C, 0xC0, 0xCE, 0x18, 0xFF, 0x8B,\n  0xE0, 0x7F, 0xFB, 0xFF, 0xD9, 0xCF, 0xCE, 0x7C, 0x63, 0x63, 0x18, 0x18,\n  0x01, 0xC0, 0x0E, 0x00, 0x60, 0x03, 0x00, 0x18, 0x0F, 0xF8, 0x7F, 0xC0,\n  0x7E, 0xFF, 0xF3, 0xF3, 0x03, 0x1C, 0x0C, 0x60, 0x31, 0x81, 0xC6, 0x06,\n  0x38, 0x18, 0xE0, 0x63, 0x03, 0x8C, 0x0C, 0x30, 0x70, 0x7F, 0x80, 0xF8,\n  0x00, 0xFC, 0x7F, 0xF8, 0xFD, 0xC0, 0x61, 0x81, 0xC3, 0x87, 0x07, 0x0C,\n  0x0E, 0x38, 0x0C, 0x60, 0x19, 0xC0, 0x3F, 0x00, 0x7C, 0x00, 0xF8, 0x00,\n  0xE0, 0x01, 0x80, 0x00, 0x7E, 0x7E, 0xFC, 0xFD, 0xC0, 0x73, 0x9C, 0xE7,\n  0x79, 0x8E, 0xF7, 0x1B, 0xEE, 0x36, 0xD8, 0x7D, 0xF0, 0xF3, 0xE1, 0xE7,\n  0x83, 0x8F, 0x07, 0x1E, 0x1C, 0x38, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, 0x0E,\n  0x1C, 0x07, 0x38, 0x07, 0x70, 0x03, 0xE0, 0x03, 0xC0, 0x03, 0xC0, 0x07,\n  0xE0, 0x0E, 0xE0, 0x1C, 0x70, 0x38, 0x70, 0xFC, 0xFC, 0xFC, 0xFC, 0xF8,\n  0xFF, 0xC7, 0xCC, 0x38, 0x73, 0x83, 0x9C, 0x0F, 0xC0, 0x7C, 0x01, 0xC0,\n  0x0C, 0x00, 0x60, 0x03, 0x00, 0x38, 0x0F, 0xF8, 0x7F, 0x80, 0x0F, 0xF8,\n  0x7F, 0xE1, 0xC7, 0x86, 0x1C, 0x18, 0xE0, 0x07, 0x00, 0x38, 0x01, 0xC0,\n  0x0E, 0x00, 0x70, 0xC3, 0x83, 0x1C, 0x1C, 0x7F, 0xF3, 0xFF, 0x80, 0x0F,\n  0x87, 0xC3, 0x03, 0x81, 0xC0, 0xC0, 0x60, 0x30, 0x38, 0x1C, 0x0C, 0x06,\n  0x03, 0x03, 0x81, 0xC0, 0xC0, 0x60, 0x3E, 0x3F, 0x00, 0x41, 0xC3, 0x83,\n  0x07, 0x0E, 0x1C, 0x18, 0x38, 0x70, 0xE0, 0xC1, 0xC3, 0x83, 0x06, 0x0E,\n  0x1C, 0x18, 0x20, 0x1F, 0x0F, 0x80, 0xC0, 0xE0, 0x70, 0x30, 0x18, 0x0C,\n  0x0E, 0x07, 0x03, 0x01, 0x80, 0xC0, 0xE0, 0x70, 0x30, 0x18, 0x7C, 0x3E,\n  0x00, 0x02, 0x01, 0x80, 0xF0, 0x7E, 0x3B, 0x9C, 0x7E, 0x1F, 0x03, 0xFF,\n  0xFF, 0xFF, 0xFC, 0xCE, 0x73, 0x1F, 0xC3, 0xFE, 0x00, 0x60, 0x06, 0x0F,\n  0xE3, 0xFE, 0x70, 0xCC, 0x0C, 0xC3, 0xCF, 0xFF, 0x7F, 0xF0, 0x1E, 0x00,\n  0x3C, 0x00, 0x38, 0x00, 0x70, 0x00, 0xDF, 0x81, 0xFF, 0x83, 0xC3, 0x8F,\n  0x03, 0x1C, 0x06, 0x38, 0x0C, 0x70, 0x18, 0xE0, 0x63, 0xE1, 0x9F, 0xFE,\n  0x3D, 0xF8, 0x00, 0x0F, 0xF3, 0xFF, 0x30, 0x76, 0x07, 0xE0, 0x6C, 0x00,\n  0xC0, 0x0C, 0x00, 0xE0, 0x67, 0xFE, 0x3F, 0x80, 0x00, 0x3C, 0x00, 0xF0,\n  0x01, 0xC0, 0x06, 0x07, 0xD8, 0x7F, 0xE3, 0x0F, 0x98, 0x1E, 0x60, 0x73,\n  0x01, 0xCC, 0x07, 0x30, 0x3C, 0xE1, 0xF1, 0xFF, 0xE3, 0xF7, 0x80, 0x0F,\n  0xC1, 0xFE, 0x78, 0x76, 0x03, 0xFF, 0xFF, 0xFF, 0xC0, 0x0C, 0x00, 0xE0,\n  0xE7, 0xFE, 0x1F, 0x80, 0x00, 0xFC, 0x07, 0xF8, 0x0C, 0x00, 0x38, 0x01,\n  0xFF, 0x07, 0xFE, 0x01, 0x80, 0x07, 0x00, 0x0E, 0x00, 0x18, 0x00, 0x30,\n  0x00, 0x60, 0x01, 0xC0, 0x1F, 0xF8, 0x3F, 0xF0, 0x00, 0x0F, 0xBC, 0x7F,\n  0xF3, 0x0F, 0x18, 0x1C, 0xC0, 0x73, 0x01, 0x8C, 0x0E, 0x30, 0x38, 0xE3,\n  0xE1, 0xFF, 0x83, 0xEC, 0x00, 0x30, 0x01, 0xC0, 0x06, 0x07, 0xF0, 0x1F,\n  0x80, 0x1E, 0x01, 0xF0, 0x03, 0x00, 0x18, 0x00, 0xDE, 0x0F, 0xF8, 0x78,\n  0xC3, 0x86, 0x18, 0x30, 0xC1, 0x8E, 0x1C, 0x70, 0xE3, 0x06, 0x7E, 0xFF,\n  0xE7, 0xE0, 0x03, 0x80, 0x70, 0x00, 0x0F, 0xC1, 0xF0, 0x06, 0x00, 0xC0,\n  0x38, 0x07, 0x00, 0xC0, 0x18, 0x03, 0x0F, 0xFF, 0xFF, 0xC0, 0x00, 0x70,\n  0x07, 0x00, 0x00, 0xFF, 0x1F, 0xF0, 0x07, 0x00, 0x70, 0x06, 0x00, 0x60,\n  0x06, 0x00, 0xE0, 0x0E, 0x00, 0xC0, 0x0C, 0x00, 0xC0, 0x1C, 0x03, 0x87,\n  0xF0, 0xFE, 0x00, 0x1E, 0x00, 0x78, 0x00, 0xE0, 0x03, 0x80, 0x0C, 0xFC,\n  0x33, 0xE0, 0xDE, 0x07, 0xE0, 0x1F, 0x00, 0x7C, 0x01, 0xF8, 0x06, 0xF0,\n  0x39, 0xC3, 0xE7, 0xEF, 0x1F, 0x80, 0x0F, 0x81, 0xF0, 0x06, 0x01, 0xC0,\n  0x38, 0x06, 0x00, 0xC0, 0x18, 0x07, 0x00, 0xE0, 0x18, 0x03, 0x00, 0x61,\n  0xFF, 0xFF, 0xF8, 0x3F, 0xBC, 0x7F, 0xFC, 0xF3, 0x98, 0xC6, 0x33, 0x9C,\n  0xE7, 0x39, 0xCC, 0x63, 0x18, 0xC6, 0x31, 0x8D, 0xF7, 0xBF, 0xEF, 0x78,\n  0x3D, 0xE1, 0xFF, 0x8F, 0x8C, 0x38, 0x61, 0x83, 0x0C, 0x18, 0xE1, 0xC7,\n  0x0E, 0x30, 0x67, 0xEF, 0xFE, 0x7E, 0x07, 0xC1, 0xFE, 0x38, 0x76, 0x03,\n  0xC0, 0x3C, 0x03, 0xC0, 0x3C, 0x06, 0xE1, 0xC7, 0xF8, 0x3E, 0x00, 0x1E,\n  0xFC, 0x1F, 0xFE, 0x0F, 0x87, 0x0F, 0x03, 0x0E, 0x03, 0x0E, 0x03, 0x0E,\n  0x07, 0x0E, 0x06, 0x1F, 0x0C, 0x1F, 0xF8, 0x19, 0xF0, 0x18, 0x00, 0x18,\n  0x00, 0x38, 0x00, 0xFE, 0x00, 0xFE, 0x00, 0x0F, 0xDE, 0x3F, 0xFC, 0xC3,\n  0xE3, 0x03, 0x84, 0x07, 0x18, 0x0E, 0x30, 0x1C, 0x60, 0x78, 0xE1, 0xE0,\n  0xFF, 0xC0, 0xF9, 0x80, 0x03, 0x00, 0x0E, 0x00, 0x1C, 0x01, 0xFC, 0x03,\n  0xF8, 0x1E, 0x78, 0x7F, 0xF0, 0x7C, 0xC3, 0xC0, 0x0E, 0x00, 0x30, 0x00,\n  0xC0, 0x03, 0x00, 0x1C, 0x03, 0xFF, 0x0F, 0xFC, 0x00, 0x07, 0xF1, 0xFF,\n  0x30, 0x73, 0x86, 0x3F, 0x81, 0xFE, 0x03, 0xE6, 0x06, 0xE0, 0xEF, 0xFC,\n  0xFF, 0x00, 0x0C, 0x07, 0x01, 0x83, 0xFF, 0xFF, 0xCE, 0x03, 0x00, 0xC0,\n  0x30, 0x1C, 0x07, 0x01, 0x83, 0x7F, 0xCF, 0xC0, 0xF0, 0xFF, 0x1F, 0x60,\n  0x76, 0x07, 0x60, 0x76, 0x06, 0x60, 0x66, 0x0E, 0x61, 0xE7, 0xFF, 0x3E,\n  0xF0, 0x7E, 0x7E, 0xFC, 0xFC, 0xE0, 0xC0, 0xC3, 0x81, 0x86, 0x03, 0x98,\n  0x07, 0x70, 0x06, 0xC0, 0x0F, 0x80, 0x1E, 0x00, 0x38, 0x00, 0xF8, 0x7F,\n  0xE3, 0xE6, 0x63, 0x1B, 0xDC, 0x6F, 0x61, 0xFF, 0x87, 0xFC, 0x1E, 0xF0,\n  0x73, 0x81, 0xCE, 0x06, 0x38, 0x00, 0x3E, 0x7C, 0xF9, 0xF1, 0xE7, 0x03,\n  0xF8, 0x07, 0xC0, 0x1F, 0x01, 0xFC, 0x0F, 0x38, 0x78, 0xFB, 0xF7, 0xEF,\n  0x9F, 0x80, 0x1F, 0x1F, 0x3E, 0x1F, 0x1C, 0x1C, 0x0C, 0x18, 0x0E, 0x38,\n  0x0E, 0x70, 0x06, 0x60, 0x07, 0xE0, 0x07, 0xC0, 0x07, 0xC0, 0x03, 0x80,\n  0x07, 0x00, 0x07, 0x00, 0x0E, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0x1F, 0xF1,\n  0xFF, 0x38, 0xE3, 0x1C, 0x03, 0x80, 0x70, 0x0E, 0x01, 0xC6, 0x38, 0x67,\n  0xFE, 0x7F, 0xE0, 0x01, 0xC0, 0xF0, 0x70, 0x18, 0x06, 0x03, 0x80, 0xE0,\n  0x30, 0x1C, 0x3E, 0x0F, 0x00, 0x60, 0x18, 0x06, 0x03, 0x80, 0xC0, 0x30,\n  0x0F, 0x01, 0xC0, 0x0C, 0x71, 0xC7, 0x18, 0x63, 0x8E, 0x30, 0xC3, 0x1C,\n  0x71, 0x86, 0x38, 0xE3, 0x04, 0x00, 0x0E, 0x07, 0x80, 0xC0, 0x60, 0x70,\n  0x30, 0x18, 0x0C, 0x06, 0x01, 0xC1, 0xE1, 0xC0, 0xC0, 0xE0, 0x70, 0x30,\n  0x38, 0x78, 0x38, 0x00, 0x3C, 0x27, 0xE6, 0xEF, 0xCC, 0x38 };\n\nconst GFXglyph FreeMonoBoldOblique12pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,  14,    0,    1 },   // 0x20 ' '\n  {     0,   6,  15,  14,    6,  -14 },   // 0x21 '!'\n  {    12,   8,   7,  14,    6,  -13 },   // 0x22 '\"'\n  {    19,  13,  18,  14,    2,  -15 },   // 0x23 '#'\n  {    49,  11,  20,  14,    3,  -16 },   // 0x24 '$'\n  {    77,  11,  15,  14,    3,  -14 },   // 0x25 '%'\n  {    98,  11,  13,  14,    2,  -12 },   // 0x26 '&'\n  {   116,   3,   7,  14,    8,  -13 },   // 0x27 '''\n  {   119,   7,  19,  14,    7,  -14 },   // 0x28 '('\n  {   136,   7,  19,  14,    2,  -14 },   // 0x29 ')'\n  {   153,  11,  10,  14,    4,  -14 },   // 0x2A '*'\n  {   167,  12,  13,  14,    3,  -12 },   // 0x2B '+'\n  {   187,   6,   7,  14,    3,   -2 },   // 0x2C ','\n  {   193,  13,   2,  14,    2,   -7 },   // 0x2D '-'\n  {   197,   3,   3,  14,    6,   -2 },   // 0x2E '.'\n  {   199,  14,  20,  14,    2,  -16 },   // 0x2F '/'\n  {   234,  11,  15,  14,    3,  -14 },   // 0x30 '0'\n  {   255,  11,  15,  14,    2,  -14 },   // 0x31 '1'\n  {   276,  13,  15,  14,    1,  -14 },   // 0x32 '2'\n  {   301,  12,  15,  14,    2,  -14 },   // 0x33 '3'\n  {   324,  11,  14,  14,    3,  -13 },   // 0x34 '4'\n  {   344,  12,  15,  14,    2,  -14 },   // 0x35 '5'\n  {   367,  11,  15,  14,    4,  -14 },   // 0x36 '6'\n  {   388,  11,  15,  14,    4,  -14 },   // 0x37 '7'\n  {   409,  11,  15,  14,    3,  -14 },   // 0x38 '8'\n  {   430,  11,  15,  14,    3,  -14 },   // 0x39 '9'\n  {   451,   5,  11,  14,    5,  -10 },   // 0x3A ':'\n  {   458,   7,  15,  14,    3,  -10 },   // 0x3B ';'\n  {   472,  13,  11,  14,    2,  -11 },   // 0x3C '<'\n  {   490,  13,   7,  14,    2,   -9 },   // 0x3D '='\n  {   502,  13,  11,  14,    2,  -11 },   // 0x3E '>'\n  {   520,   9,  14,  14,    5,  -13 },   // 0x3F '?'\n  {   536,  12,  19,  14,    2,  -14 },   // 0x40 '@'\n  {   565,  15,  14,  14,    0,  -13 },   // 0x41 'A'\n  {   592,  13,  14,  14,    1,  -13 },   // 0x42 'B'\n  {   615,  14,  14,  14,    2,  -13 },   // 0x43 'C'\n  {   640,  13,  14,  14,    1,  -13 },   // 0x44 'D'\n  {   663,  15,  14,  14,    0,  -13 },   // 0x45 'E'\n  {   690,  16,  14,  14,    0,  -13 },   // 0x46 'F'\n  {   718,  14,  14,  14,    1,  -13 },   // 0x47 'G'\n  {   743,  16,  14,  14,    0,  -13 },   // 0x48 'H'\n  {   771,  12,  14,  14,    2,  -13 },   // 0x49 'I'\n  {   792,  16,  14,  14,    0,  -13 },   // 0x4A 'J'\n  {   820,  16,  14,  14,    0,  -13 },   // 0x4B 'K'\n  {   848,  13,  14,  14,    1,  -13 },   // 0x4C 'L'\n  {   871,  18,  14,  14,    0,  -13 },   // 0x4D 'M'\n  {   903,  16,  14,  14,    1,  -13 },   // 0x4E 'N'\n  {   931,  14,  14,  14,    1,  -13 },   // 0x4F 'O'\n  {   956,  13,  14,  14,    1,  -13 },   // 0x50 'P'\n  {   979,  14,  17,  14,    1,  -13 },   // 0x51 'Q'\n  {  1009,  15,  14,  14,    0,  -13 },   // 0x52 'R'\n  {  1036,  12,  14,  14,    3,  -13 },   // 0x53 'S'\n  {  1057,  13,  14,  14,    2,  -13 },   // 0x54 'T'\n  {  1080,  14,  14,  14,    2,  -13 },   // 0x55 'U'\n  {  1105,  15,  14,  14,    1,  -13 },   // 0x56 'V'\n  {  1132,  15,  14,  14,    1,  -13 },   // 0x57 'W'\n  {  1159,  16,  14,  14,    0,  -13 },   // 0x58 'X'\n  {  1187,  13,  14,  14,    2,  -13 },   // 0x59 'Y'\n  {  1210,  14,  14,  14,    1,  -13 },   // 0x5A 'Z'\n  {  1235,   9,  19,  14,    5,  -14 },   // 0x5B '['\n  {  1257,   7,  20,  14,    5,  -16 },   // 0x5C '\\'\n  {  1275,   9,  19,  14,    3,  -14 },   // 0x5D ']'\n  {  1297,  10,   8,  14,    4,  -15 },   // 0x5E '^'\n  {  1307,  15,   2,  14,   -1,    4 },   // 0x5F '_'\n  {  1311,   4,   4,  14,    7,  -15 },   // 0x60 '`'\n  {  1313,  12,  11,  14,    2,  -10 },   // 0x61 'a'\n  {  1330,  15,  15,  14,   -1,  -14 },   // 0x62 'b'\n  {  1359,  12,  11,  14,    2,  -10 },   // 0x63 'c'\n  {  1376,  14,  15,  14,    2,  -14 },   // 0x64 'd'\n  {  1403,  12,  11,  14,    2,  -10 },   // 0x65 'e'\n  {  1420,  15,  15,  14,    2,  -14 },   // 0x66 'f'\n  {  1449,  14,  16,  14,    2,  -10 },   // 0x67 'g'\n  {  1477,  13,  15,  14,    1,  -14 },   // 0x68 'h'\n  {  1502,  11,  14,  14,    2,  -13 },   // 0x69 'i'\n  {  1522,  12,  19,  14,    1,  -13 },   // 0x6A 'j'\n  {  1551,  14,  15,  14,    1,  -14 },   // 0x6B 'k'\n  {  1578,  11,  15,  14,    2,  -14 },   // 0x6C 'l'\n  {  1599,  15,  11,  14,    0,  -10 },   // 0x6D 'm'\n  {  1620,  13,  11,  14,    1,  -10 },   // 0x6E 'n'\n  {  1638,  12,  11,  14,    2,  -10 },   // 0x6F 'o'\n  {  1655,  16,  16,  14,   -1,  -10 },   // 0x70 'p'\n  {  1687,  15,  16,  14,    1,  -10 },   // 0x71 'q'\n  {  1717,  14,  11,  14,    1,  -10 },   // 0x72 'r'\n  {  1737,  12,  11,  14,    2,  -10 },   // 0x73 's'\n  {  1754,  10,  14,  14,    2,  -13 },   // 0x74 't'\n  {  1772,  12,  11,  14,    2,  -10 },   // 0x75 'u'\n  {  1789,  15,  11,  14,    1,  -10 },   // 0x76 'v'\n  {  1810,  14,  11,  14,    2,  -10 },   // 0x77 'w'\n  {  1830,  14,  11,  14,    1,  -10 },   // 0x78 'x'\n  {  1850,  16,  16,  14,    0,  -10 },   // 0x79 'y'\n  {  1882,  12,  11,  14,    2,  -10 },   // 0x7A 'z'\n  {  1899,  10,  19,  14,    4,  -14 },   // 0x7B '{'\n  {  1923,   6,  19,  14,    5,  -14 },   // 0x7C '|'\n  {  1938,   9,  19,  14,    3,  -14 },   // 0x7D '}'\n  {  1960,  12,   4,  14,    3,   -7 } }; // 0x7E '~'\n\nconst GFXfont FreeMonoBoldOblique12pt7b PROGMEM = {\n  (uint8_t  *)FreeMonoBoldOblique12pt7bBitmaps,\n  (GFXglyph *)FreeMonoBoldOblique12pt7bGlyphs,\n  0x20, 0x7E, 24 };\n\n// Approx. 2638 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeMonoBoldOblique18pt7b.h",
    "content": "const uint8_t FreeMonoBoldOblique18pt7bBitmaps[] PROGMEM = {\n  0x0F, 0x07, 0xC7, 0xE3, 0xF1, 0xF0, 0xF8, 0xFC, 0x7C, 0x3E, 0x1F, 0x0F,\n  0x07, 0x87, 0xC3, 0xC1, 0xE0, 0x60, 0x00, 0x38, 0x3E, 0x1F, 0x0F, 0x83,\n  0x80, 0xF8, 0xFF, 0x0E, 0xF1, 0xEF, 0x1E, 0xE1, 0xCE, 0x1C, 0xC1, 0xCC,\n  0x18, 0xC1, 0x88, 0x18, 0x00, 0xE3, 0x80, 0x79, 0xE0, 0x1C, 0x70, 0x07,\n  0x1C, 0x03, 0xCF, 0x00, 0xF3, 0xC0, 0x38, 0xE0, 0x7F, 0xFF, 0x3F, 0xFF,\n  0xCF, 0xFF, 0xF3, 0xFF, 0xF8, 0x3C, 0xF0, 0x0F, 0x3C, 0x03, 0x8E, 0x0F,\n  0xFF, 0xE3, 0xFF, 0xFC, 0xFF, 0xFF, 0x3F, 0xFF, 0x83, 0xCF, 0x00, 0xF3,\n  0xC0, 0x38, 0xE0, 0x1E, 0x78, 0x07, 0x9E, 0x01, 0xC7, 0x00, 0x71, 0xC0,\n  0x00, 0x00, 0x38, 0x00, 0x0E, 0x00, 0x07, 0x80, 0x03, 0xF0, 0x03, 0xFF,\n  0x81, 0xFF, 0xF0, 0xFF, 0xF8, 0x3C, 0x1E, 0x1E, 0x07, 0x87, 0x80, 0x01,\n  0xF0, 0x00, 0x7F, 0xC0, 0x0F, 0xFC, 0x01, 0xFF, 0x80, 0x07, 0xF0, 0x00,\n  0x3C, 0x70, 0x0F, 0x3C, 0x03, 0xCF, 0x83, 0xE3, 0xFF, 0xF8, 0xFF, 0xFC,\n  0x3F, 0xFE, 0x0C, 0xFE, 0x00, 0x1C, 0x00, 0x07, 0x00, 0x03, 0xC0, 0x00,\n  0xF0, 0x00, 0x18, 0x00, 0x03, 0xC0, 0x0F, 0xE0, 0x1C, 0x70, 0x30, 0x30,\n  0x30, 0x30, 0x30, 0x70, 0x38, 0xE0, 0x1F, 0xC3, 0x0F, 0x1F, 0x01, 0xFC,\n  0x0F, 0xE0, 0x7F, 0x00, 0xF8, 0xF0, 0x83, 0xF8, 0x07, 0x1C, 0x0E, 0x0C,\n  0x0C, 0x0C, 0x0C, 0x1C, 0x0E, 0x38, 0x07, 0xF0, 0x03, 0xC0, 0x00, 0x7A,\n  0x01, 0xFF, 0x03, 0xFF, 0x07, 0xFE, 0x0F, 0x9C, 0x0F, 0x00, 0x0F, 0x00,\n  0x0F, 0x00, 0x07, 0x80, 0x1F, 0x80, 0x3F, 0xC0, 0x7F, 0xCF, 0x79, 0xFF,\n  0xF1, 0xFE, 0xF1, 0xFC, 0xF0, 0xF8, 0xFF, 0xFE, 0xFF, 0xFE, 0x7F, 0xFE,\n  0x1F, 0xBC, 0x7B, 0xFD, 0xEF, 0x73, 0x9C, 0xC6, 0x00, 0x01, 0xC0, 0xF0,\n  0x3C, 0x1E, 0x0F, 0x03, 0xC1, 0xE0, 0x70, 0x3C, 0x0F, 0x07, 0x81, 0xE0,\n  0x78, 0x3C, 0x0F, 0x03, 0xC0, 0xF0, 0x3C, 0x0F, 0x03, 0xC0, 0xF0, 0x3E,\n  0x07, 0x81, 0xE0, 0x7C, 0x1F, 0x03, 0x80, 0x07, 0x03, 0xC0, 0xF8, 0x3E,\n  0x07, 0x81, 0xF0, 0x3C, 0x0F, 0x03, 0xC0, 0xF0, 0x3C, 0x0F, 0x03, 0xC0,\n  0xF0, 0x78, 0x1E, 0x07, 0x81, 0xC0, 0xF0, 0x3C, 0x1E, 0x07, 0x83, 0xC1,\n  0xE0, 0x78, 0x3C, 0x0E, 0x00, 0x00, 0xC0, 0x03, 0xC0, 0x07, 0x00, 0x0E,\n  0x02, 0x3C, 0x0F, 0xFF, 0xFF, 0xFF, 0xBF, 0xFE, 0x1F, 0xF0, 0x1F, 0x80,\n  0x7F, 0x81, 0xEF, 0x07, 0x8F, 0x0F, 0x1E, 0x08, 0x10, 0x00, 0x00, 0x70,\n  0x00, 0x3C, 0x00, 0x0F, 0x00, 0x03, 0xC0, 0x00, 0xE0, 0x00, 0x38, 0x00,\n  0x1E, 0x03, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF8, 0x0F,\n  0x00, 0x03, 0xC0, 0x00, 0xE0, 0x00, 0x38, 0x00, 0x0E, 0x00, 0x07, 0x80,\n  0x01, 0xC0, 0x00, 0x70, 0x00, 0x0F, 0x87, 0x87, 0x83, 0x83, 0xC1, 0xC1,\n  0xC0, 0xC0, 0xE0, 0x60, 0x00, 0xFF, 0xFF, 0xBF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFE, 0x77, 0xFF, 0xF7, 0x00, 0x00, 0x00, 0x38, 0x00, 0x03, 0xC0,\n  0x00, 0x1C, 0x00, 0x01, 0xE0, 0x00, 0x1E, 0x00, 0x01, 0xE0, 0x00, 0x0F,\n  0x00, 0x00, 0xF0, 0x00, 0x0F, 0x00, 0x00, 0x78, 0x00, 0x07, 0x80, 0x00,\n  0x78, 0x00, 0x03, 0xC0, 0x00, 0x3C, 0x00, 0x03, 0xC0, 0x00, 0x1C, 0x00,\n  0x01, 0xE0, 0x00, 0x1E, 0x00, 0x00, 0xE0, 0x00, 0x0F, 0x00, 0x00, 0xF0,\n  0x00, 0x0F, 0x00, 0x00, 0x78, 0x00, 0x07, 0x80, 0x00, 0x78, 0x00, 0x03,\n  0xC0, 0x00, 0x3C, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0xFC, 0x01, 0xFF,\n  0x01, 0xFF, 0xC1, 0xFF, 0xE1, 0xF1, 0xF9, 0xE0, 0x7C, 0xF0, 0x1E, 0xF0,\n  0x0F, 0x78, 0x07, 0xB8, 0x03, 0x9C, 0x03, 0xDE, 0x01, 0xCF, 0x00, 0xE7,\n  0x00, 0x73, 0xC0, 0x79, 0xE0, 0x3C, 0xF0, 0x1C, 0x78, 0x1E, 0x3E, 0x1E,\n  0x0F, 0xFF, 0x07, 0xFF, 0x01, 0xFF, 0x00, 0x7E, 0x00, 0x00, 0x7C, 0x03,\n  0xF8, 0x0F, 0xE0, 0x7F, 0xC0, 0xF7, 0x81, 0x8F, 0x00, 0x1C, 0x00, 0x38,\n  0x00, 0xF0, 0x01, 0xE0, 0x03, 0xC0, 0x07, 0x00, 0x0E, 0x00, 0x3C, 0x00,\n  0x78, 0x00, 0xF0, 0x01, 0xC0, 0x03, 0x81, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xEF, 0xFF, 0xC0, 0x00, 0x1F, 0x00, 0x07, 0xFC, 0x00, 0xFF, 0xE0, 0x1F,\n  0xFF, 0x03, 0xC1, 0xF0, 0x78, 0x0F, 0x07, 0x80, 0xF0, 0x70, 0x0F, 0x00,\n  0x01, 0xE0, 0x00, 0x3E, 0x00, 0x07, 0xC0, 0x00, 0xF8, 0x00, 0x3F, 0x00,\n  0x07, 0xE0, 0x01, 0xFC, 0x00, 0x3F, 0x80, 0x07, 0xE0, 0x01, 0xF8, 0x00,\n  0x3F, 0x03, 0x87, 0xFF, 0xF8, 0x7F, 0xFF, 0x87, 0xFF, 0xF8, 0xFF, 0xFF,\n  0x00, 0x00, 0xFE, 0x00, 0xFF, 0xC0, 0x7F, 0xF8, 0x3F, 0xFF, 0x0E, 0x07,\n  0xC0, 0x00, 0xF0, 0x00, 0x3C, 0x00, 0x1F, 0x00, 0x07, 0x80, 0x1F, 0xC0,\n  0x0F, 0xE0, 0x03, 0xF0, 0x00, 0xFF, 0x00, 0x03, 0xE0, 0x00, 0x78, 0x00,\n  0x1E, 0x00, 0x07, 0x80, 0x03, 0xC0, 0x03, 0xF1, 0xFF, 0xF8, 0xFF, 0xFC,\n  0x3F, 0xFE, 0x03, 0xFE, 0x00, 0x00, 0x1F, 0x00, 0x3F, 0x00, 0x7F, 0x00,\n  0xFE, 0x00, 0xFE, 0x01, 0xEE, 0x03, 0xDE, 0x07, 0x9E, 0x0F, 0x1C, 0x1E,\n  0x1C, 0x3C, 0x3C, 0x78, 0x3C, 0xFF, 0xFE, 0xFF, 0xFE, 0xFF, 0xFE, 0xFF,\n  0xFC, 0x00, 0x70, 0x03, 0xFC, 0x07, 0xFC, 0x07, 0xFC, 0x07, 0xF8, 0x07,\n  0xFF, 0xC1, 0xFF, 0xF0, 0x7F, 0xFC, 0x3F, 0xFE, 0x0F, 0x00, 0x03, 0xC0,\n  0x00, 0xE0, 0x00, 0x3B, 0xE0, 0x1F, 0xFE, 0x07, 0xFF, 0xC1, 0xFF, 0xF8,\n  0x78, 0x3E, 0x00, 0x07, 0x80, 0x01, 0xE0, 0x00, 0x78, 0x00, 0x1E, 0x00,\n  0x0F, 0x18, 0x0F, 0xCF, 0xFF, 0xE3, 0xFF, 0xF0, 0x7F, 0xF8, 0x07, 0xF0,\n  0x00, 0x00, 0x0F, 0xC0, 0x0F, 0xFC, 0x03, 0xFF, 0x81, 0xFF, 0xE0, 0x7F,\n  0x00, 0x1F, 0x80, 0x07, 0xC0, 0x01, 0xF0, 0x00, 0x3C, 0x00, 0x0F, 0x9F,\n  0x01, 0xEF, 0xF0, 0x3F, 0xFF, 0x0F, 0xFF, 0xF1, 0xFC, 0x3E, 0x3E, 0x03,\n  0xC7, 0x80, 0x78, 0xF0, 0x0F, 0x1E, 0x03, 0xC3, 0xE0, 0xF8, 0x7F, 0xFE,\n  0x07, 0xFF, 0x80, 0x7F, 0xE0, 0x07, 0xF0, 0x00, 0x7F, 0xFF, 0x7F, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0x0E, 0x00, 0x1E, 0x00, 0x1C, 0x00, 0x3C,\n  0x00, 0x78, 0x00, 0x70, 0x00, 0xF0, 0x00, 0xE0, 0x01, 0xE0, 0x01, 0xC0,\n  0x03, 0xC0, 0x07, 0x80, 0x07, 0x80, 0x0F, 0x00, 0x0E, 0x00, 0x1E, 0x00,\n  0x1C, 0x00, 0x1C, 0x00, 0x00, 0x7E, 0x00, 0x3F, 0xF0, 0x0F, 0xFF, 0x03,\n  0xFF, 0xF0, 0xF8, 0x3E, 0x3E, 0x03, 0xC7, 0x80, 0x78, 0xF0, 0x0F, 0x1E,\n  0x03, 0xC3, 0xE0, 0xF0, 0x3F, 0xFC, 0x03, 0xFF, 0x00, 0xFF, 0xE0, 0x7F,\n  0xFE, 0x1F, 0x83, 0xE3, 0xC0, 0x3C, 0xF0, 0x07, 0x9E, 0x01, 0xF3, 0xE0,\n  0x7C, 0x7F, 0xFF, 0x87, 0xFF, 0xE0, 0x7F, 0xF0, 0x03, 0xF8, 0x00, 0x00,\n  0x7E, 0x00, 0x7F, 0xC0, 0x3F, 0xF8, 0x1F, 0xFE, 0x0F, 0x87, 0xC3, 0xC0,\n  0xF1, 0xE0, 0x3C, 0x78, 0x0F, 0x1E, 0x03, 0xC7, 0x81, 0xF1, 0xF1, 0xFC,\n  0x7F, 0xFE, 0x0F, 0xFF, 0x81, 0xFD, 0xE0, 0x3E, 0xF0, 0x00, 0x7C, 0x00,\n  0x3E, 0x00, 0x1F, 0x00, 0x1F, 0x81, 0xFF, 0xC0, 0xFF, 0xE0, 0x3F, 0xE0,\n  0x07, 0xE0, 0x00, 0x1C, 0x7C, 0xF9, 0xF1, 0xC0, 0x00, 0x00, 0x00, 0x00,\n  0x03, 0x8F, 0x9F, 0x3E, 0x38, 0x01, 0xC0, 0x7C, 0x0F, 0x81, 0xF0, 0x3C,\n  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xC0, 0xF0, 0x1E,\n  0x07, 0x80, 0xE0, 0x38, 0x07, 0x01, 0xC0, 0x30, 0x0E, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0xFC, 0x00, 0xFE, 0x00, 0xFE, 0x00,\n  0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x00, 0xFE, 0x00, 0x0F, 0xE0, 0x00, 0xFE,\n  0x00, 0x1F, 0xC0, 0x01, 0xFC, 0x00, 0x1F, 0xC0, 0x01, 0xF0, 0x00, 0x38,\n  0x3F, 0xFF, 0xEF, 0xFF, 0xFD, 0xFF, 0xFF, 0x9F, 0xFF, 0xE0, 0x00, 0x00,\n  0x00, 0x00, 0x1F, 0xFF, 0xF7, 0xFF, 0xFE, 0xFF, 0xFF, 0xDF, 0xFF, 0xF0,\n  0x00, 0x00, 0x03, 0x80, 0x00, 0xFC, 0x00, 0x0F, 0xE0, 0x00, 0x7F, 0x00,\n  0x07, 0xF0, 0x00, 0x3F, 0x80, 0x01, 0xFC, 0x00, 0x1F, 0xC0, 0x0F, 0xE0,\n  0x07, 0xF0, 0x07, 0xF8, 0x03, 0xF8, 0x01, 0xFC, 0x00, 0x3E, 0x00, 0x07,\n  0x00, 0x00, 0x07, 0xE0, 0xFF, 0xC7, 0xFF, 0xBF, 0xFF, 0xF0, 0x7F, 0x80,\n  0xFE, 0x03, 0xC0, 0x0F, 0x00, 0x78, 0x0F, 0xE1, 0xFE, 0x0F, 0xF0, 0x7E,\n  0x01, 0xE0, 0x07, 0x00, 0x00, 0x00, 0x70, 0x03, 0xE0, 0x0F, 0x80, 0x3E,\n  0x00, 0x70, 0x00, 0x00, 0x3E, 0x00, 0x3F, 0xE0, 0x1F, 0xF8, 0x0F, 0x0F,\n  0x07, 0x01, 0xC3, 0x80, 0x71, 0xE0, 0x1C, 0x70, 0x0E, 0x18, 0x0F, 0x8E,\n  0x1F, 0xE3, 0x8F, 0xF0, 0xE7, 0x9C, 0x33, 0xC7, 0x1C, 0xE1, 0xC7, 0x38,\n  0x71, 0xCF, 0x18, 0x73, 0xFE, 0x38, 0x7F, 0xCE, 0x0F, 0xF3, 0x80, 0x00,\n  0xE0, 0x00, 0x38, 0x00, 0x0F, 0x00, 0x01, 0xE0, 0xC0, 0x7F, 0xF0, 0x0F,\n  0xF8, 0x01, 0xF8, 0x00, 0x01, 0xFF, 0x80, 0x07, 0xFE, 0x00, 0x1F, 0xF8,\n  0x00, 0x7F, 0xE0, 0x00, 0x3F, 0xC0, 0x00, 0xFF, 0x00, 0x07, 0xBC, 0x00,\n  0x1C, 0xF0, 0x00, 0xF3, 0xC0, 0x07, 0x87, 0x80, 0x1E, 0x1E, 0x00, 0xF0,\n  0x78, 0x07, 0xFF, 0xE0, 0x1F, 0xFF, 0x80, 0xFF, 0xFF, 0x07, 0xFF, 0xFC,\n  0x1E, 0x00, 0xF1, 0xFE, 0x1F, 0xFF, 0xF8, 0x7F, 0xFF, 0xE1, 0xFF, 0xFF,\n  0x07, 0xF8, 0x0F, 0xFF, 0xC0, 0x7F, 0xFF, 0x87, 0xFF, 0xFC, 0x1F, 0xFF,\n  0xF0, 0x38, 0x0F, 0x81, 0xC0, 0x3C, 0x1E, 0x01, 0xE0, 0xF0, 0x3E, 0x07,\n  0xFF, 0xE0, 0x3F, 0xFE, 0x03, 0xFF, 0xF8, 0x1F, 0xFF, 0xE0, 0xE0, 0x1F,\n  0x87, 0x00, 0x3C, 0x38, 0x01, 0xE3, 0xC0, 0x0F, 0x1E, 0x00, 0xF3, 0xFF,\n  0xFF, 0xBF, 0xFF, 0xF9, 0xFF, 0xFF, 0x8F, 0xFF, 0xF0, 0x00, 0x00, 0x7F,\n  0x30, 0x0F, 0xFF, 0xC1, 0xFF, 0xFE, 0x1F, 0xFF, 0xF1, 0xF8, 0x3F, 0x1F,\n  0x00, 0x78, 0xF0, 0x03, 0xCF, 0x80, 0x1C, 0x78, 0x00, 0x03, 0xC0, 0x00,\n  0x3C, 0x00, 0x01, 0xE0, 0x00, 0x0F, 0x00, 0x00, 0x78, 0x00, 0x03, 0xC0,\n  0x00, 0x1F, 0x00, 0x38, 0x7E, 0x07, 0xC3, 0xFF, 0xFC, 0x0F, 0xFF, 0xC0,\n  0x3F, 0xFC, 0x00, 0x7F, 0x80, 0x00, 0x0F, 0xFF, 0x80, 0x7F, 0xFE, 0x07,\n  0xFF, 0xF8, 0x1F, 0xFF, 0xE0, 0x78, 0x1F, 0x03, 0x80, 0x7C, 0x1C, 0x01,\n  0xE1, 0xE0, 0x0F, 0x0F, 0x00, 0x78, 0x70, 0x03, 0xC3, 0x80, 0x1E, 0x1C,\n  0x00, 0xF1, 0xE0, 0x0F, 0x0F, 0x00, 0x78, 0x70, 0x07, 0xC3, 0x80, 0x7C,\n  0x3C, 0x07, 0xC3, 0xFF, 0xFC, 0x3F, 0xFF, 0xC1, 0xFF, 0xFC, 0x0F, 0xFF,\n  0x80, 0x00, 0x07, 0xFF, 0xFC, 0x3F, 0xFF, 0xF0, 0xFF, 0xFF, 0xC3, 0xFF,\n  0xFF, 0x03, 0xC0, 0x3C, 0x0F, 0x00, 0xE0, 0x3C, 0x73, 0x80, 0xE3, 0xCC,\n  0x03, 0xFF, 0x00, 0x1F, 0xFC, 0x00, 0x7F, 0xE0, 0x01, 0xFF, 0x80, 0x07,\n  0x1E, 0x00, 0x3C, 0x70, 0x00, 0xF0, 0x07, 0x03, 0xC0, 0x1C, 0x0E, 0x00,\n  0xF1, 0xFF, 0xFF, 0xC7, 0xFF, 0xFE, 0x3F, 0xFF, 0xF8, 0x7F, 0xFF, 0xE0,\n  0x07, 0xFF, 0xFE, 0x1F, 0xFF, 0xFC, 0x3F, 0xFF, 0xF0, 0x7F, 0xFF, 0xE0,\n  0x3C, 0x01, 0xC0, 0x70, 0x07, 0x80, 0xE1, 0x8E, 0x03, 0xC7, 0x1C, 0x07,\n  0xFE, 0x00, 0x0F, 0xFC, 0x00, 0x1F, 0xF8, 0x00, 0x3F, 0xF0, 0x00, 0xF1,\n  0xC0, 0x01, 0xE3, 0x80, 0x03, 0x80, 0x00, 0x07, 0x00, 0x00, 0x1E, 0x00,\n  0x00, 0xFF, 0xE0, 0x03, 0xFF, 0xC0, 0x07, 0xFF, 0x80, 0x0F, 0xFE, 0x00,\n  0x00, 0x00, 0x3F, 0x18, 0x0F, 0xFF, 0xC0, 0xFF, 0xFE, 0x0F, 0xFF, 0xF0,\n  0xFC, 0x0F, 0x0F, 0x80, 0x38, 0xF8, 0x01, 0x87, 0x80, 0x00, 0x78, 0x00,\n  0x03, 0xC0, 0x00, 0x1E, 0x00, 0x00, 0xE0, 0x7F, 0xEF, 0x07, 0xFF, 0x78,\n  0x3F, 0xFB, 0xC0, 0xFF, 0x9E, 0x00, 0x38, 0xFC, 0x03, 0xC3, 0xFF, 0xFE,\n  0x1F, 0xFF, 0xE0, 0x3F, 0xFC, 0x00, 0x7F, 0x80, 0x00, 0x03, 0xF8, 0xFE,\n  0x0F, 0xF3, 0xFC, 0x1F, 0xE7, 0xF8, 0x3F, 0x8F, 0xE0, 0x3C, 0x07, 0x80,\n  0x70, 0x0E, 0x00, 0xE0, 0x1C, 0x03, 0xC0, 0x78, 0x07, 0x80, 0xF0, 0x0F,\n  0xFF, 0xC0, 0x1F, 0xFF, 0x80, 0x3F, 0xFF, 0x00, 0xFF, 0xFE, 0x01, 0xE0,\n  0x3C, 0x03, 0x80, 0x70, 0x07, 0x00, 0xE0, 0x1E, 0x03, 0xC0, 0xFF, 0x1F,\n  0xE1, 0xFE, 0x7F, 0xC7, 0xFC, 0xFF, 0x87, 0xF1, 0xFE, 0x00, 0x07, 0xFF,\n  0xE1, 0xFF, 0xFC, 0x3F, 0xFF, 0x87, 0xFF, 0xE0, 0x07, 0x80, 0x00, 0xE0,\n  0x00, 0x1C, 0x00, 0x03, 0x80, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x03, 0x80,\n  0x00, 0x70, 0x00, 0x1E, 0x00, 0x03, 0xC0, 0x00, 0x78, 0x00, 0x0E, 0x00,\n  0x01, 0xC0, 0x0F, 0xFF, 0xC3, 0xFF, 0xF8, 0x7F, 0xFF, 0x07, 0xFF, 0xE0,\n  0x00, 0x3F, 0xFE, 0x00, 0xFF, 0xFC, 0x01, 0xFF, 0xF8, 0x03, 0xFF, 0xE0,\n  0x00, 0x1C, 0x00, 0x00, 0x38, 0x00, 0x00, 0x70, 0x00, 0x01, 0xE0, 0x00,\n  0x03, 0xC0, 0x00, 0x07, 0x00, 0x00, 0x0E, 0x00, 0x80, 0x1C, 0x03, 0x80,\n  0x78, 0x0F, 0x00, 0xF0, 0x1E, 0x01, 0xC0, 0x38, 0x07, 0x80, 0x70, 0x1F,\n  0x01, 0xFF, 0xFC, 0x03, 0xFF, 0xF0, 0x03, 0xFF, 0xC0, 0x00, 0xFC, 0x00,\n  0x00, 0x07, 0xF8, 0xFC, 0x1F, 0xFB, 0xFC, 0x3F, 0xE7, 0xF0, 0x7F, 0xCF,\n  0xE0, 0x3C, 0x1E, 0x00, 0x70, 0xF8, 0x00, 0xE3, 0xE0, 0x03, 0xCF, 0x00,\n  0x07, 0xFC, 0x00, 0x0F, 0xF0, 0x00, 0x1F, 0xF0, 0x00, 0x3F, 0xF0, 0x00,\n  0xF9, 0xF0, 0x01, 0xE1, 0xE0, 0x03, 0x83, 0xE0, 0x07, 0x03, 0xC0, 0x1E,\n  0x07, 0x80, 0xFF, 0x8F, 0xE3, 0xFF, 0x0F, 0xC7, 0xFE, 0x1F, 0x8F, 0xF8,\n  0x3E, 0x00, 0x0F, 0xFE, 0x00, 0xFF, 0xF0, 0x1F, 0xFE, 0x00, 0xFF, 0xE0,\n  0x01, 0xE0, 0x00, 0x1E, 0x00, 0x01, 0xC0, 0x00, 0x1C, 0x00, 0x03, 0xC0,\n  0x00, 0x3C, 0x00, 0x03, 0x80, 0x00, 0x38, 0x00, 0x07, 0x80, 0x60, 0x78,\n  0x0F, 0x07, 0x80, 0xF0, 0x70, 0x0E, 0x07, 0x00, 0xE7, 0xFF, 0xFE, 0xFF,\n  0xFF, 0xEF, 0xFF, 0xFE, 0xFF, 0xFF, 0xC0, 0x0F, 0xC0, 0x1F, 0x87, 0xE0,\n  0x0F, 0xC7, 0xF8, 0x0F, 0xE1, 0xFC, 0x0F, 0xE0, 0x7E, 0x07, 0xE0, 0x3F,\n  0x07, 0xF0, 0x3F, 0xC7, 0xF8, 0x1F, 0xE3, 0xF8, 0x0E, 0xF3, 0xDC, 0x07,\n  0x7B, 0xDE, 0x03, 0x9F, 0xEF, 0x03, 0xCF, 0xE7, 0x81, 0xE7, 0xE3, 0x80,\n  0xE3, 0xF1, 0xC0, 0x70, 0xF1, 0xE0, 0x38, 0x70, 0xF0, 0x3C, 0x00, 0x70,\n  0x3F, 0xC1, 0xFE, 0x3F, 0xE1, 0xFF, 0x1F, 0xF0, 0xFF, 0x8F, 0xF0, 0x7F,\n  0x80, 0x0F, 0xC1, 0xFE, 0x1F, 0xC1, 0xFF, 0x1F, 0xC3, 0xFE, 0x1F, 0xE1,\n  0xFE, 0x07, 0xE0, 0x38, 0x07, 0xF0, 0x78, 0x07, 0xF0, 0x78, 0x0F, 0xF8,\n  0x70, 0x0F, 0x78, 0x70, 0x0E, 0x78, 0xF0, 0x0E, 0x7C, 0xF0, 0x1E, 0x3C,\n  0xF0, 0x1E, 0x3E, 0xE0, 0x1E, 0x1E, 0xE0, 0x1C, 0x1F, 0xE0, 0x1C, 0x0F,\n  0xE0, 0x3C, 0x0F, 0xE0, 0x7F, 0x87, 0xC0, 0xFF, 0x87, 0xC0, 0xFF, 0x87,\n  0xC0, 0xFF, 0x03, 0xC0, 0x00, 0x7E, 0x00, 0x1F, 0xF8, 0x07, 0xFF, 0xC0,\n  0xFF, 0xFE, 0x1F, 0x87, 0xE3, 0xE0, 0x1F, 0x3C, 0x01, 0xF7, 0xC0, 0x0F,\n  0x78, 0x00, 0xFF, 0x00, 0x0F, 0xF0, 0x00, 0xFF, 0x00, 0x0F, 0xF0, 0x01,\n  0xEF, 0x00, 0x3E, 0xF8, 0x03, 0xCF, 0x80, 0x7C, 0x7C, 0x1F, 0x87, 0xFF,\n  0xF0, 0x3F, 0xFE, 0x01, 0xFF, 0x80, 0x07, 0xE0, 0x00, 0x0F, 0xFF, 0x80,\n  0x7F, 0xFF, 0x07, 0xFF, 0xFC, 0x1F, 0xFF, 0xF0, 0x38, 0x0F, 0x81, 0xC0,\n  0x3C, 0x1E, 0x01, 0xE0, 0xF0, 0x0F, 0x07, 0x00, 0xF0, 0x38, 0x0F, 0x83,\n  0xFF, 0xF8, 0x1F, 0xFF, 0x80, 0xFF, 0xF8, 0x07, 0xFF, 0x00, 0x38, 0x00,\n  0x03, 0xC0, 0x00, 0x1E, 0x00, 0x03, 0xFF, 0x80, 0x3F, 0xFC, 0x01, 0xFF,\n  0xE0, 0x0F, 0xFE, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x1F, 0xF8, 0x07, 0xFF,\n  0xC0, 0xFF, 0xFE, 0x1F, 0x87, 0xE3, 0xE0, 0x1F, 0x3C, 0x01, 0xF7, 0xC0,\n  0x0F, 0x78, 0x00, 0xFF, 0x00, 0x0F, 0xF0, 0x00, 0xFF, 0x00, 0x0F, 0xF0,\n  0x01, 0xEF, 0x00, 0x3E, 0xF8, 0x03, 0xCF, 0x80, 0x7C, 0x7C, 0x1F, 0x87,\n  0xFF, 0xF0, 0x3F, 0xFE, 0x01, 0xFF, 0x80, 0x07, 0xE0, 0x01, 0xFE, 0x30,\n  0x3F, 0xFF, 0x87, 0xFF, 0xF0, 0x7F, 0xFF, 0x07, 0x83, 0xC0, 0x07, 0xFF,\n  0x80, 0x3F, 0xFF, 0x80, 0xFF, 0xFF, 0x03, 0xFF, 0xFE, 0x03, 0xC0, 0xF8,\n  0x0E, 0x01, 0xE0, 0x38, 0x07, 0x81, 0xE0, 0x3E, 0x07, 0x83, 0xF0, 0x1F,\n  0xFF, 0x80, 0x7F, 0xFC, 0x01, 0xFF, 0xC0, 0x0F, 0xFF, 0x80, 0x3C, 0x3E,\n  0x00, 0xE0, 0x7C, 0x03, 0x80, 0xF0, 0x1E, 0x03, 0xE1, 0xFF, 0x07, 0xFF,\n  0xFC, 0x1F, 0xFF, 0xF0, 0x3F, 0xFF, 0x80, 0xF8, 0x00, 0x7C, 0xE0, 0x7F,\n  0xFC, 0x1F, 0xFF, 0x87, 0xFF, 0xE0, 0xF8, 0x7C, 0x3C, 0x07, 0x87, 0x80,\n  0xE0, 0xF0, 0x00, 0x1F, 0x00, 0x03, 0xFE, 0x00, 0x3F, 0xF8, 0x03, 0xFF,\n  0x80, 0x07, 0xF8, 0x40, 0x1F, 0x3C, 0x01, 0xE7, 0x80, 0x3C, 0xFC, 0x1F,\n  0x1F, 0xFF, 0xE3, 0xFF, 0xF8, 0x7F, 0xFE, 0x00, 0x7E, 0x00, 0x7F, 0xFF,\n  0xEF, 0xFF, 0xFD, 0xFF, 0xFF, 0xBF, 0xFF, 0xFF, 0x0E, 0x1F, 0xE1, 0xC3,\n  0xBC, 0x78, 0x77, 0x0F, 0x1E, 0xE1, 0xC1, 0x80, 0x38, 0x00, 0x0F, 0x00,\n  0x01, 0xE0, 0x00, 0x3C, 0x00, 0x07, 0x00, 0x00, 0xE0, 0x00, 0x3C, 0x00,\n  0x07, 0x80, 0x0F, 0xFE, 0x03, 0xFF, 0xE0, 0x7F, 0xFC, 0x0F, 0xFF, 0x00,\n  0x7F, 0x8F, 0xF3, 0xFE, 0x7F, 0xDF, 0xF7, 0xFC, 0xFF, 0x1F, 0xE3, 0xC0,\n  0x3C, 0x1C, 0x01, 0xE0, 0xE0, 0x0F, 0x0F, 0x00, 0x70, 0x78, 0x03, 0x83,\n  0xC0, 0x3C, 0x1C, 0x01, 0xE0, 0xE0, 0x0E, 0x0F, 0x00, 0x70, 0x78, 0x03,\n  0x83, 0xC0, 0x3C, 0x1F, 0x01, 0xC0, 0xFC, 0x3E, 0x03, 0xFF, 0xE0, 0x1F,\n  0xFE, 0x00, 0x7F, 0xE0, 0x00, 0xFC, 0x00, 0x00, 0x7F, 0x81, 0xFE, 0xFF,\n  0x87, 0xFF, 0xFF, 0x0F, 0xFB, 0xFC, 0x1F, 0xE1, 0xC0, 0x0F, 0x03, 0xC0,\n  0x1C, 0x07, 0x80, 0x78, 0x0F, 0x01, 0xE0, 0x1E, 0x03, 0x80, 0x1E, 0x0F,\n  0x00, 0x3C, 0x3C, 0x00, 0x78, 0x70, 0x00, 0xF1, 0xE0, 0x01, 0xE7, 0x80,\n  0x01, 0xEF, 0x00, 0x03, 0xFC, 0x00, 0x07, 0xF0, 0x00, 0x0F, 0xE0, 0x00,\n  0x0F, 0x80, 0x00, 0x1E, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x7F, 0x87, 0xFF,\n  0xFF, 0x1F, 0xFF, 0xF8, 0x7F, 0xFF, 0xE1, 0xFE, 0x78, 0x00, 0xF1, 0xE3,\n  0xC3, 0x87, 0x8F, 0x0E, 0x1E, 0x7C, 0x78, 0x79, 0xF9, 0xC1, 0xEF, 0xEF,\n  0x07, 0xBF, 0xBC, 0x1D, 0xFE, 0xE0, 0x77, 0x7F, 0x81, 0xFD, 0xFE, 0x07,\n  0xE3, 0xF0, 0x3F, 0x8F, 0xC0, 0xFC, 0x3F, 0x03, 0xF0, 0xF8, 0x0F, 0x83,\n  0xE0, 0x3E, 0x0F, 0x80, 0xF0, 0x3C, 0x00, 0x07, 0xE0, 0x7E, 0x0F, 0xF0,\n  0xFF, 0x0F, 0xF0, 0xFE, 0x0F, 0xE0, 0xFE, 0x03, 0xC0, 0xF8, 0x01, 0xE1,\n  0xE0, 0x01, 0xF3, 0xC0, 0x00, 0xF7, 0x80, 0x00, 0x7F, 0x00, 0x00, 0x7E,\n  0x00, 0x00, 0x7C, 0x00, 0x00, 0xFE, 0x00, 0x01, 0xFF, 0x00, 0x03, 0xEF,\n  0x00, 0x07, 0xCF, 0x80, 0x0F, 0x87, 0xC0, 0x1F, 0x03, 0xC0, 0x7F, 0x07,\n  0xF0, 0xFF, 0x8F, 0xF0, 0xFF, 0x0F, 0xF0, 0xFF, 0x0F, 0xE0, 0x7E, 0x0F,\n  0xEF, 0xF0, 0xFF, 0xFF, 0x0F, 0xEF, 0xE0, 0xFE, 0x3C, 0x0F, 0x01, 0xE1,\n  0xE0, 0x1E, 0x3E, 0x00, 0xF7, 0xC0, 0x0F, 0xF8, 0x00, 0x7F, 0x00, 0x07,\n  0xE0, 0x00, 0x3C, 0x00, 0x03, 0x80, 0x00, 0x78, 0x00, 0x07, 0x80, 0x00,\n  0x78, 0x00, 0x07, 0x00, 0x07, 0xFF, 0x00, 0xFF, 0xF8, 0x0F, 0xFF, 0x00,\n  0xFF, 0xF0, 0x00, 0x07, 0xFF, 0xE0, 0xFF, 0xFC, 0x3F, 0xFF, 0x87, 0xFF,\n  0xF0, 0xF0, 0x7C, 0x1C, 0x1F, 0x03, 0x87, 0xC0, 0x61, 0xF0, 0x00, 0x7C,\n  0x00, 0x1F, 0x00, 0x07, 0xC0, 0x01, 0xF0, 0x00, 0x7C, 0x00, 0x1F, 0x07,\n  0x07, 0xC0, 0xE1, 0xF0, 0x3C, 0x7C, 0x07, 0x9F, 0xFF, 0xF3, 0xFF, 0xFC,\n  0x7F, 0xFF, 0x8F, 0xFF, 0xF0, 0x07, 0xF8, 0x3F, 0xC1, 0xFE, 0x0F, 0xE0,\n  0x70, 0x07, 0x80, 0x3C, 0x01, 0xC0, 0x0E, 0x00, 0xF0, 0x07, 0x80, 0x3C,\n  0x01, 0xC0, 0x0E, 0x00, 0xF0, 0x07, 0x80, 0x38, 0x01, 0xC0, 0x0E, 0x00,\n  0xF0, 0x07, 0x80, 0x38, 0x01, 0xC0, 0x1F, 0xE0, 0xFF, 0x07, 0xF8, 0x3F,\n  0x80, 0xE0, 0x38, 0x0F, 0x03, 0xC0, 0xF0, 0x1C, 0x07, 0x81, 0xE0, 0x78,\n  0x0E, 0x03, 0xC0, 0xF0, 0x3C, 0x07, 0x01, 0xE0, 0x78, 0x1E, 0x03, 0x80,\n  0xF0, 0x3C, 0x0F, 0x01, 0xE0, 0x78, 0x1E, 0x03, 0x80, 0xF0, 0x3C, 0x06,\n  0x07, 0xF8, 0x3F, 0xC1, 0xFC, 0x0F, 0xE0, 0x0F, 0x00, 0x78, 0x03, 0xC0,\n  0x1C, 0x00, 0xE0, 0x0F, 0x00, 0x78, 0x03, 0x80, 0x1C, 0x01, 0xE0, 0x0F,\n  0x00, 0x78, 0x03, 0x80, 0x1C, 0x01, 0xE0, 0x0F, 0x00, 0x70, 0x03, 0x80,\n  0x1C, 0x0F, 0xE0, 0xFF, 0x07, 0xF0, 0x3F, 0x80, 0x00, 0x40, 0x01, 0x80,\n  0x07, 0x80, 0x3F, 0x80, 0xFF, 0x03, 0xFF, 0x0F, 0x9F, 0x3E, 0x1E, 0xF8,\n  0x3F, 0xE0, 0x3F, 0x00, 0x30, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xF0, 0xC3, 0xC7, 0x0E, 0x3C, 0x30, 0x00, 0xFE, 0x00,\n  0x7F, 0xF0, 0x1F, 0xFF, 0x03, 0xFF, 0xE0, 0x00, 0x3C, 0x07, 0xFF, 0x83,\n  0xFF, 0xF0, 0xFF, 0xFC, 0x3F, 0xFF, 0x8F, 0x80, 0xF3, 0xE0, 0x1E, 0x78,\n  0x1F, 0x8F, 0xFF, 0xFF, 0xFF, 0xFF, 0xDF, 0xFF, 0xF8, 0xFE, 0x7E, 0x07,\n  0xE0, 0x00, 0x3F, 0x80, 0x00, 0xFC, 0x00, 0x03, 0xF0, 0x00, 0x01, 0xC0,\n  0x00, 0x0F, 0x00, 0x00, 0x3C, 0xFC, 0x00, 0xEF, 0xFC, 0x03, 0xFF, 0xF8,\n  0x1F, 0xFF, 0xE0, 0x7E, 0x0F, 0xC1, 0xE0, 0x1F, 0x07, 0x00, 0x3C, 0x1C,\n  0x00, 0xF0, 0xE0, 0x03, 0xC3, 0x80, 0x1E, 0x0F, 0x00, 0xF8, 0x3E, 0x07,\n  0xC7, 0xFF, 0xFF, 0x3F, 0xFF, 0xF8, 0xFF, 0xFF, 0x81, 0xF1, 0xF8, 0x00,\n  0x00, 0xFE, 0x60, 0xFF, 0xFC, 0x3F, 0xFF, 0x8F, 0xFF, 0xF3, 0xF0, 0x3C,\n  0xF8, 0x03, 0x9E, 0x00, 0x67, 0x80, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x03,\n  0xC0, 0x00, 0x7E, 0x01, 0xC7, 0xFF, 0xF8, 0xFF, 0xFE, 0x0F, 0xFF, 0x80,\n  0x7F, 0x80, 0x00, 0x01, 0xF8, 0x00, 0x1F, 0x80, 0x00, 0xFC, 0x00, 0x07,\n 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0x1E, 0x00, 0x70, 0xF0, 0x03, 0x87, 0x80, 0x3C,\n  0x3E, 0x03, 0xE1, 0xF8, 0x7E, 0x07, 0xFF, 0xF0, 0x3F, 0xFF, 0x80, 0xFF,\n  0xFC, 0x01, 0xF9, 0xE0, 0x00, 0x0E, 0x00, 0x00, 0xF0, 0x00, 0x0F, 0x80,\n  0x7F, 0xF8, 0x07, 0xFF, 0x80, 0x3F, 0xF8, 0x00, 0xFF, 0x00, 0x00, 0x0F,\n  0xC0, 0x00, 0xFC, 0x00, 0x0F, 0xC0, 0x00, 0xFC, 0x00, 0x03, 0xC0, 0x00,\n  0x38, 0x00, 0x03, 0x9F, 0x00, 0x7F, 0xFC, 0x07, 0xFF, 0xC0, 0x7F, 0xFE,\n  0x07, 0xC3, 0xE0, 0x70, 0x1E, 0x0F, 0x01, 0xC0, 0xF0, 0x1C, 0x0E, 0x03,\n  0xC0, 0xE0, 0x3C, 0x1E, 0x03, 0x81, 0xE0, 0x38, 0x7F, 0x0F, 0xFF, 0xF8,\n  0xFF, 0xFF, 0x8F, 0xF7, 0xF0, 0xFE, 0x00, 0x78, 0x00, 0x78, 0x00, 0x78,\n  0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x0F, 0xF0, 0x0F, 0xF0, 0x1F, 0xF0,\n  0x0F, 0xF0, 0x00, 0xF0, 0x00, 0xE0, 0x00, 0xE0, 0x01, 0xE0, 0x01, 0xE0,\n  0x01, 0xE0, 0x01, 0xC0, 0x01, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFE, 0x00, 0x07, 0x80, 0x01, 0xE0, 0x00, 0xF8, 0x00, 0x3C, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0x7F, 0xFC, 0x3F, 0xFE, 0x0F, 0xFF, 0x81, 0xFF,\n  0xE0, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x07, 0x00, 0x01, 0xC0, 0x00, 0xF0,\n  0x00, 0x3C, 0x00, 0x0E, 0x00, 0x03, 0x80, 0x00, 0xE0, 0x00, 0x78, 0x00,\n  0x1E, 0x00, 0x07, 0x00, 0x01, 0xC0, 0x00, 0xF0, 0x00, 0x7C, 0x1F, 0xFE,\n  0x0F, 0xFF, 0x03, 0xFF, 0x80, 0x7F, 0x80, 0x00, 0x07, 0xE0, 0x00, 0xFE,\n  0x00, 0x0F, 0xE0, 0x00, 0x7C, 0x00, 0x01, 0xC0, 0x00, 0x3C, 0x00, 0x03,\n  0xCF, 0xF0, 0x3C, 0xFF, 0x03, 0x9F, 0xF0, 0x38, 0xFE, 0x07, 0xBF, 0x00,\n  0x7F, 0xC0, 0x07, 0xF8, 0x00, 0x7F, 0x00, 0x07, 0xF8, 0x00, 0xFF, 0xC0,\n  0x0F, 0x7E, 0x00, 0xE3, 0xF0, 0x7E, 0x1F, 0xE7, 0xE1, 0xFE, 0xFE, 0x3F,\n  0xE7, 0xE1, 0xFC, 0x03, 0xFC, 0x07, 0xFC, 0x07, 0xF8, 0x07, 0xF8, 0x00,\n  0x78, 0x00, 0x78, 0x00, 0x78, 0x00, 0x70, 0x00, 0x70, 0x00, 0xF0, 0x00,\n  0xF0, 0x00, 0xE0, 0x00, 0xE0, 0x01, 0xE0, 0x01, 0xE0, 0x01, 0xE0, 0x01,\n  0xC0, 0x01, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0x1F,\n  0x7C, 0x78, 0x7F, 0xFF, 0xF8, 0xFF, 0xFF, 0xF9, 0xFF, 0xFF, 0xF0, 0xF1,\n  0xF1, 0xE1, 0xC3, 0x83, 0xC7, 0x87, 0x07, 0x8F, 0x0E, 0x0E, 0x1C, 0x3C,\n  0x1C, 0x38, 0x78, 0x78, 0x70, 0xE0, 0xF1, 0xE1, 0xC1, 0xC7, 0xE3, 0xC3,\n  0xFF, 0xCF, 0xC7, 0xFF, 0x9F, 0x9F, 0xFF, 0x3E, 0x3E, 0x0F, 0x8F, 0x80,\n  0xFD, 0xFF, 0x07, 0xFF, 0xF8, 0x3F, 0xFF, 0xE0, 0x7E, 0x1F, 0x07, 0xC0,\n  0x78, 0x3C, 0x03, 0x81, 0xE0, 0x1C, 0x0E, 0x01, 0xE0, 0x70, 0x0F, 0x07,\n  0x80, 0x70, 0x3C, 0x03, 0x87, 0xF0, 0x3F, 0x7F, 0xC3, 0xFF, 0xFE, 0x1F,\n  0xEF, 0xE0, 0xFE, 0x01, 0xFC, 0x01, 0xFF, 0x80, 0xFF, 0xF8, 0x7F, 0xFE,\n  0x3E, 0x0F, 0xDF, 0x01, 0xF7, 0x80, 0x3F, 0xC0, 0x0F, 0xF0, 0x03, 0xFC,\n  0x01, 0xEF, 0x80, 0xFB, 0xF0, 0x7C, 0x7F, 0xFF, 0x1F, 0xFF, 0x03, 0xFF,\n  0x80, 0x3F, 0x80, 0x07, 0xC7, 0xE0, 0x1F, 0xBF, 0xF0, 0x3F, 0xFF, 0xF0,\n  0x7F, 0xFF, 0xE0, 0x3F, 0x07, 0xE0, 0x78, 0x03, 0xC0, 0xE0, 0x07, 0x81,\n  0xC0, 0x0F, 0x07, 0x00, 0x1E, 0x0F, 0x00, 0x78, 0x1E, 0x01, 0xF0, 0x3E,\n  0x07, 0xC0, 0xFF, 0xFF, 0x81, 0xFF, 0xFE, 0x03, 0xDF, 0xF0, 0x07, 0x1F,\n  0x80, 0x0E, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x78, 0x00, 0x03, 0xFE, 0x00,\n  0x0F, 0xFE, 0x00, 0x1F, 0xF8, 0x00, 0x3F, 0xF0, 0x00, 0x00, 0x01, 0xF8,\n  0xF8, 0x1F, 0xFF, 0xF1, 0xFF, 0xFF, 0xCF, 0xFF, 0xFE, 0x3E, 0x07, 0xC1,\n  0xF0, 0x0F, 0x07, 0x80, 0x1C, 0x3C, 0x00, 0x70, 0xF0, 0x03, 0x83, 0xC0,\n  0x0E, 0x0F, 0x80, 0x78, 0x3F, 0x07, 0xE0, 0x7F, 0xFF, 0x81, 0xFF, 0xFC,\n  0x03, 0xFF, 0x70, 0x03, 0xF3, 0xC0, 0x00, 0x0F, 0x00, 0x00, 0x3C, 0x00,\n  0x00, 0xE0, 0x00, 0x3F, 0xE0, 0x01, 0xFF, 0xC0, 0x07, 0xFF, 0x00, 0x1F,\n  0xF8, 0x00, 0x0F, 0xC3, 0xC1, 0xFC, 0xFF, 0x1F, 0xFF, 0xF1, 0xFF, 0xFE,\n  0x03, 0xFC, 0x00, 0x3F, 0x00, 0x03, 0xC0, 0x00, 0x78, 0x00, 0x07, 0x80,\n  0x00, 0x70, 0x00, 0x07, 0x00, 0x00, 0xF0, 0x00, 0xFF, 0xFC, 0x0F, 0xFF,\n  0xE0, 0xFF, 0xFC, 0x0F, 0xFF, 0xC0, 0x03, 0xF3, 0x0F, 0xFF, 0x3F, 0xFF,\n  0x3F, 0xFF, 0x7C, 0x0E, 0x78, 0x00, 0x7F, 0xE0, 0x3F, 0xFC, 0x1F, 0xFF,\n  0x00, 0x3F, 0x70, 0x0F, 0xF8, 0x1F, 0xFF, 0xFE, 0xFF, 0xFC, 0xFF, 0xF8,\n  0x0F, 0xE0, 0x06, 0x00, 0x0F, 0x00, 0x0F, 0x00, 0x0E, 0x00, 0x0E, 0x00,\n  0x7F, 0xFE, 0xFF, 0xFE, 0xFF, 0xFE, 0xFF, 0xFC, 0x1C, 0x00, 0x3C, 0x00,\n  0x3C, 0x00, 0x38, 0x00, 0x38, 0x00, 0x38, 0x00, 0x78, 0x00, 0x7C, 0x0E,\n  0x7F, 0xFF, 0x7F, 0xFE, 0x3F, 0xFC, 0x0F, 0xE0, 0x7C, 0x0F, 0xFF, 0x07,\n  0xFF, 0x81, 0xFF, 0xE0, 0x7E, 0x78, 0x03, 0x9E, 0x00, 0xE7, 0x80, 0x79,\n  0xE0, 0x1E, 0x78, 0x07, 0x1E, 0x01, 0xC7, 0x80, 0xF1, 0xE0, 0xFC, 0x7F,\n  0xFF, 0x9F, 0xFF, 0xE3, 0xFF, 0xF8, 0x3E, 0x7C, 0x7F, 0x87, 0xFF, 0xFC,\n  0x7F, 0xFF, 0xE3, 0xFF, 0xFF, 0x1F, 0xE1, 0xE0, 0x3C, 0x0F, 0x03, 0xC0,\n  0x78, 0x3C, 0x01, 0xE1, 0xC0, 0x0F, 0x1E, 0x00, 0x79, 0xE0, 0x03, 0xCE,\n  0x00, 0x0F, 0xF0, 0x00, 0x7F, 0x00, 0x03, 0xF0, 0x00, 0x0F, 0x80, 0x00,\n  0x78, 0x00, 0x7E, 0x03, 0xF7, 0xF0, 0x3F, 0xFF, 0x81, 0xFD, 0xF8, 0x0F,\n  0xE7, 0x8E, 0x1C, 0x3C, 0xF9, 0xE1, 0xE7, 0xCE, 0x0F, 0x7E, 0xF0, 0x7B,\n  0xF7, 0x03, 0xFF, 0xF8, 0x1F, 0xDF, 0x80, 0xFC, 0xFC, 0x07, 0xE7, 0xE0,\n  0x3E, 0x3E, 0x01, 0xF1, 0xF0, 0x0F, 0x07, 0x00, 0x0F, 0xE3, 0xF8, 0xFF,\n  0x1F, 0xC7, 0xF9, 0xFE, 0x1F, 0x87, 0xF0, 0x7E, 0x7C, 0x01, 0xFF, 0xC0,\n  0x07, 0xFC, 0x00, 0x1F, 0x80, 0x00, 0xFC, 0x00, 0x1F, 0xF0, 0x01, 0xF7,\n  0xC0, 0x1F, 0x1F, 0x03, 0xF0, 0x7C, 0x7F, 0xCF, 0xFB, 0xFE, 0x7F, 0xDF,\n  0xE3, 0xFC, 0x07, 0xF0, 0x7F, 0x0F, 0xF0, 0xFF, 0x0F, 0xF0, 0xFF, 0x07,\n  0xE0, 0xFE, 0x03, 0xC0, 0x78, 0x03, 0xC0, 0x78, 0x03, 0xC0, 0xF0, 0x01,\n  0xE1, 0xE0, 0x01, 0xE1, 0xC0, 0x01, 0xE3, 0xC0, 0x00, 0xF7, 0x80, 0x00,\n  0xFF, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x7C, 0x00, 0x00,\n  0x78, 0x00, 0x00, 0x70, 0x00, 0x00, 0xE0, 0x00, 0x01, 0xE0, 0x00, 0x7F,\n  0xF0, 0x00, 0xFF, 0xF8, 0x00, 0xFF, 0xF0, 0x00, 0x7F, 0xF0, 0x00, 0x1F,\n  0xFF, 0xC7, 0xFF, 0xF1, 0xFF, 0xF8, 0xFF, 0xFE, 0x3C, 0x1F, 0x0E, 0x1F,\n  0x00, 0x0F, 0x80, 0x07, 0xC0, 0x07, 0xC0, 0x03, 0xE0, 0x01, 0xF0, 0x00,\n  0xF8, 0x3C, 0xFF, 0xFF, 0x3F, 0xFF, 0xCF, 0xFF, 0xE3, 0xFF, 0xF8, 0x00,\n  0xF0, 0x1F, 0x03, 0xF0, 0x7E, 0x07, 0x80, 0x70, 0x0F, 0x00, 0xF0, 0x0E,\n  0x00, 0xE0, 0x1E, 0x01, 0xC0, 0xFC, 0x0F, 0x80, 0xF8, 0x0F, 0xC0, 0x3C,\n  0x03, 0xC0, 0x38, 0x03, 0x80, 0x78, 0x07, 0x80, 0x78, 0x07, 0xE0, 0x7E,\n  0x03, 0xE0, 0x1C, 0x00, 0x02, 0x07, 0x07, 0x0F, 0x0F, 0x0E, 0x0E, 0x0E,\n  0x1E, 0x1E, 0x1C, 0x1C, 0x1C, 0x3C, 0x3C, 0x38, 0x38, 0x38, 0x78, 0x78,\n  0x70, 0x70, 0x70, 0xF0, 0xF0, 0xE0, 0xE0, 0x01, 0xC0, 0x1F, 0x00, 0xFC,\n  0x07, 0xE0, 0x0F, 0x00, 0x78, 0x03, 0xC0, 0x1C, 0x00, 0xE0, 0x0F, 0x00,\n  0x78, 0x03, 0xC0, 0x1F, 0x80, 0x7C, 0x03, 0xE0, 0x3F, 0x03, 0xC0, 0x1C,\n  0x00, 0xE0, 0x0F, 0x00, 0x78, 0x03, 0x80, 0x3C, 0x0F, 0xE0, 0x7E, 0x07,\n  0xE0, 0x1E, 0x00, 0x0F, 0x00, 0x1F, 0xC0, 0x1F, 0xF0, 0xFF, 0xFC, 0xFF,\n  0x3F, 0xFF, 0x0F, 0xF8, 0x03, 0xF8, 0x00, 0xF0 };\n\nconst GFXglyph FreeMonoBoldOblique18pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,  21,    0,    1 },   // 0x20 ' '\n  {     0,   9,  22,  21,    9,  -21 },   // 0x21 '!'\n  {    25,  12,  10,  21,    9,  -20 },   // 0x22 '\"'\n  {    40,  18,  25,  21,    4,  -22 },   // 0x23 '#'\n  {    97,  18,  28,  21,    4,  -23 },   // 0x24 '$'\n  {   160,  16,  21,  21,    5,  -20 },   // 0x25 '%'\n  {   202,  16,  20,  21,    4,  -19 },   // 0x26 '&'\n  {   242,   5,  10,  21,   12,  -20 },   // 0x27 '''\n  {   249,  10,  27,  21,   11,  -21 },   // 0x28 '('\n  {   283,  10,  27,  21,    4,  -21 },   // 0x29 ')'\n  {   317,  15,  15,  21,    6,  -21 },   // 0x2A '*'\n  {   346,  18,  19,  21,    4,  -18 },   // 0x2B '+'\n  {   389,   9,  10,  21,    4,   -3 },   // 0x2C ','\n  {   401,  18,   4,  21,    4,  -11 },   // 0x2D '-'\n  {   410,   5,   5,  21,    8,   -4 },   // 0x2E '.'\n  {   414,  21,  28,  21,    2,  -23 },   // 0x2F '/'\n  {   488,  17,  23,  21,    5,  -22 },   // 0x30 '0'\n  {   537,  15,  22,  21,    3,  -21 },   // 0x31 '1'\n  {   579,  20,  23,  21,    2,  -22 },   // 0x32 '2'\n  {   637,  18,  23,  21,    3,  -22 },   // 0x33 '3'\n  {   689,  16,  21,  21,    4,  -20 },   // 0x34 '4'\n  {   731,  18,  22,  21,    4,  -21 },   // 0x35 '5'\n  {   781,  19,  23,  21,    5,  -22 },   // 0x36 '6'\n  {   836,  16,  22,  21,    6,  -21 },   // 0x37 '7'\n  {   880,  19,  23,  21,    3,  -22 },   // 0x38 '8'\n  {   935,  18,  23,  21,    4,  -22 },   // 0x39 '9'\n  {   987,   7,  16,  21,    9,  -15 },   // 0x3A ':'\n  {  1001,  11,  22,  21,    4,  -15 },   // 0x3B ';'\n  {  1032,  18,  16,  21,    4,  -17 },   // 0x3C '<'\n  {  1068,  19,  10,  21,    3,  -14 },   // 0x3D '='\n  {  1092,  19,  16,  21,    3,  -17 },   // 0x3E '>'\n  {  1130,  14,  21,  21,    8,  -20 },   // 0x3F '?'\n  {  1167,  18,  27,  21,    3,  -21 },   // 0x40 '@'\n  {  1228,  22,  21,  21,    0,  -20 },   // 0x41 'A'\n  {  1286,  21,  21,  21,    1,  -20 },   // 0x42 'B'\n  {  1342,  21,  21,  21,    2,  -20 },   // 0x43 'C'\n  {  1398,  21,  21,  21,    1,  -20 },   // 0x44 'D'\n  {  1454,  22,  21,  21,    0,  -20 },   // 0x45 'E'\n  {  1512,  23,  21,  21,    0,  -20 },   // 0x46 'F'\n  {  1573,  21,  21,  21,    2,  -20 },   // 0x47 'G'\n  {  1629,  23,  21,  21,    0,  -20 },   // 0x48 'H'\n  {  1690,  19,  21,  21,    2,  -20 },   // 0x49 'I'\n  {  1740,  23,  21,  21,    0,  -20 },   // 0x4A 'J'\n  {  1801,  23,  21,  21,    0,  -20 },   // 0x4B 'K'\n  {  1862,  20,  21,  21,    1,  -20 },   // 0x4C 'L'\n  {  1915,  25,  21,  21,    0,  -20 },   // 0x4D 'M'\n  {  1981,  24,  21,  21,    1,  -20 },   // 0x4E 'N'\n  {  2044,  20,  21,  21,    2,  -20 },   // 0x4F 'O'\n  {  2097,  21,  21,  21,    1,  -20 },   // 0x50 'P'\n  {  2153,  20,  26,  21,    2,  -20 },   // 0x51 'Q'\n  {  2218,  22,  21,  21,    0,  -20 },   // 0x52 'R'\n  {  2276,  19,  21,  21,    3,  -20 },   // 0x53 'S'\n  {  2326,  19,  21,  21,    3,  -20 },   // 0x54 'T'\n  {  2376,  21,  21,  21,    3,  -20 },   // 0x55 'U'\n  {  2432,  23,  21,  21,    1,  -20 },   // 0x56 'V'\n  {  2493,  22,  21,  21,    2,  -20 },   // 0x57 'W'\n  {  2551,  24,  21,  21,    0,  -20 },   // 0x58 'X'\n  {  2614,  20,  21,  21,    3,  -20 },   // 0x59 'Y'\n  {  2667,  19,  21,  21,    2,  -20 },   // 0x5A 'Z'\n  {  2717,  13,  27,  21,    8,  -21 },   // 0x5B '['\n  {  2761,  10,  28,  21,    8,  -23 },   // 0x5C '\\'\n  {  2796,  13,  27,  21,    4,  -21 },   // 0x5D ']'\n  {  2840,  15,  11,  21,    6,  -21 },   // 0x5E '^'\n  {  2861,  21,   4,  21,   -1,    4 },   // 0x5F '_'\n  {  2872,   6,   6,  21,   10,  -22 },   // 0x60 '`'\n  {  2877,  19,  16,  21,    2,  -15 },   // 0x61 'a'\n  {  2915,  22,  22,  21,    0,  -21 },   // 0x62 'b'\n  {  2976,  19,  16,  21,    3,  -15 },   // 0x63 'c'\n  {  3014,  21,  22,  21,    3,  -21 },   // 0x64 'd'\n  {  3072,  18,  16,  21,    3,  -15 },   // 0x65 'e'\n  {  3108,  21,  22,  21,    3,  -21 },   // 0x66 'f'\n  {  3166,  21,  23,  21,    2,  -15 },   // 0x67 'g'\n  {  3227,  20,  22,  21,    1,  -21 },   // 0x68 'h'\n  {  3282,  16,  22,  21,    3,  -21 },   // 0x69 'i'\n  {  3326,  18,  29,  21,    2,  -21 },   // 0x6A 'j'\n  {  3392,  20,  22,  21,    1,  -21 },   // 0x6B 'k'\n  {  3447,  16,  22,  21,    3,  -21 },   // 0x6C 'l'\n  {  3491,  23,  16,  21,    0,  -15 },   // 0x6D 'm'\n  {  3537,  21,  16,  21,    1,  -15 },   // 0x6E 'n'\n  {  3579,  18,  16,  21,    3,  -15 },   // 0x6F 'o'\n  {  3615,  23,  23,  21,   -1,  -15 },   // 0x70 'p'\n  {  3682,  22,  23,  21,    2,  -15 },   // 0x71 'q'\n  {  3746,  20,  16,  21,    2,  -15 },   // 0x72 'r'\n  {  3786,  16,  16,  21,    4,  -15 },   // 0x73 's'\n  {  3818,  16,  21,  21,    4,  -20 },   // 0x74 't'\n  {  3860,  18,  16,  21,    3,  -15 },   // 0x75 'u'\n  {  3896,  21,  16,  21,    2,  -15 },   // 0x76 'v'\n  {  3938,  21,  16,  21,    3,  -15 },   // 0x77 'w'\n  {  3980,  21,  16,  21,    1,  -15 },   // 0x78 'x'\n  {  4022,  24,  23,  21,   -1,  -15 },   // 0x79 'y'\n  {  4091,  18,  16,  21,    3,  -15 },   // 0x7A 'z'\n  {  4127,  12,  27,  21,    8,  -21 },   // 0x7B '{'\n  {  4168,   8,  27,  21,    8,  -21 },   // 0x7C '|'\n  {  4195,  13,  27,  21,    4,  -21 },   // 0x7D '}'\n  {  4239,  17,   8,  21,    4,  -13 } }; // 0x7E '~'\n\nconst GFXfont FreeMonoBoldOblique18pt7b PROGMEM = {\n  (uint8_t  *)FreeMonoBoldOblique18pt7bBitmaps,\n  (GFXglyph *)FreeMonoBoldOblique18pt7bGlyphs,\n  0x20, 0x7E, 35 };\n\n// Approx. 4928 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeMonoBoldOblique24pt7b.h",
    "content": "const uint8_t FreeMonoBoldOblique24pt7bBitmaps[] PROGMEM = {\n  0x01, 0xE0, 0x3F, 0x07, 0xF0, 0xFF, 0x0F, 0xF0, 0xFF, 0x0F, 0xE0, 0xFE,\n  0x0F, 0xE0, 0xFE, 0x0F, 0xC0, 0xFC, 0x1F, 0xC1, 0xF8, 0x1F, 0x81, 0xF8,\n  0x1F, 0x81, 0xF0, 0x1F, 0x01, 0xF0, 0x1E, 0x00, 0x80, 0x00, 0x00, 0x00,\n  0x00, 0x03, 0xC0, 0x7E, 0x0F, 0xE0, 0xFE, 0x0F, 0xC0, 0x78, 0x00, 0x7E,\n  0x1F, 0xBF, 0x0F, 0xDF, 0x87, 0xCF, 0x83, 0xE7, 0xC1, 0xF3, 0xE0, 0xF1,\n  0xE0, 0xF8, 0xF0, 0x7C, 0x78, 0x3C, 0x38, 0x1E, 0x1C, 0x0F, 0x0E, 0x07,\n  0x0E, 0x03, 0x83, 0x01, 0x80, 0x00, 0x1C, 0x1C, 0x00, 0x3E, 0x3E, 0x00,\n  0x3E, 0x3E, 0x00, 0x3C, 0x3C, 0x00, 0x7C, 0x7C, 0x00, 0x7C, 0x7C, 0x00,\n  0x7C, 0x7C, 0x00, 0xF8, 0xF8, 0x00, 0xF8, 0xF8, 0x00, 0xF8, 0xF8, 0x0F,\n  0xFF, 0xFF, 0x1F, 0xFF, 0xFF, 0x1F, 0xFF, 0xFF, 0x1F, 0xFF, 0xFF, 0x1F,\n  0xFF, 0xFE, 0x03, 0xE3, 0xE0, 0x03, 0xE3, 0xE0, 0x03, 0xC3, 0xC0, 0x07,\n  0xC7, 0xC0, 0x7F, 0xFF, 0xF8, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF, 0xFC, 0xFF,\n  0xFF, 0xF8, 0xFF, 0xFF, 0xF0, 0x0F, 0x0F, 0x00, 0x1F, 0x1F, 0x00, 0x1F,\n  0x1F, 0x00, 0x1F, 0x1F, 0x00, 0x3E, 0x1E, 0x00, 0x3E, 0x3E, 0x00, 0x3E,\n  0x3E, 0x00, 0x3C, 0x3C, 0x00, 0x7C, 0x7C, 0x00, 0x38, 0x38, 0x00, 0x00,\n  0x00, 0xE0, 0x00, 0x00, 0xF0, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x7C, 0x00,\n  0x00, 0xFF, 0x00, 0x01, 0xFF, 0xFC, 0x03, 0xFF, 0xFE, 0x03, 0xFF, 0xFF,\n  0x01, 0xFF, 0xFF, 0x81, 0xFC, 0x1F, 0xC1, 0xF8, 0x03, 0xC0, 0xF8, 0x01,\n  0xE0, 0x7C, 0x00, 0x40, 0x3F, 0x00, 0x00, 0x1F, 0xF0, 0x00, 0x0F, 0xFF,\n  0x80, 0x03, 0xFF, 0xF8, 0x00, 0xFF, 0xFE, 0x00, 0x0F, 0xFF, 0x00, 0x00,\n  0x7F, 0xC0, 0x00, 0x07, 0xE0, 0xE0, 0x01, 0xF0, 0xF0, 0x00, 0xF8, 0xF8,\n  0x00, 0xFC, 0x7E, 0x00, 0xFC, 0x3F, 0x81, 0xFE, 0x1F, 0xFF, 0xFE, 0x0F,\n  0xFF, 0xFE, 0x0F, 0xFF, 0xFE, 0x03, 0xFF, 0xFC, 0x00, 0x07, 0xF0, 0x00,\n  0x01, 0xF0, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x78, 0x00, 0x00, 0x7C, 0x00,\n  0x00, 0x3E, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0xF8,\n  0x00, 0x0F, 0xF8, 0x00, 0x7F, 0xE0, 0x03, 0xC3, 0xC0, 0x0E, 0x07, 0x00,\n  0x70, 0x1C, 0x01, 0xC0, 0x70, 0x07, 0x01, 0xC0, 0x1C, 0x0E, 0x00, 0x78,\n  0x78, 0x00, 0xFF, 0xC0, 0x03, 0xFE, 0x1F, 0x03, 0xE3, 0xFC, 0x00, 0x7F,\n  0xC0, 0x0F, 0xF8, 0x03, 0xFF, 0x00, 0x7F, 0xC0, 0x03, 0xF8, 0x7C, 0x0F,\n  0x07, 0xFC, 0x00, 0x3F, 0xF0, 0x01, 0xE1, 0xE0, 0x07, 0x03, 0x80, 0x38,\n  0x0E, 0x00, 0xE0, 0x38, 0x03, 0x80, 0xE0, 0x0E, 0x07, 0x00, 0x3C, 0x3C,\n  0x00, 0x7F, 0xE0, 0x01, 0xFF, 0x00, 0x01, 0xF0, 0x00, 0x00, 0x1F, 0x00,\n  0x01, 0xFF, 0x80, 0x3F, 0xFC, 0x03, 0xFF, 0xE0, 0x1F, 0xFE, 0x01, 0xF1,\n  0xE0, 0x1F, 0x04, 0x00, 0xF8, 0x00, 0x07, 0xC0, 0x00, 0x3E, 0x00, 0x01,\n  0xF8, 0x00, 0x0F, 0xC0, 0x00, 0x3F, 0x00, 0x07, 0xF8, 0x00, 0x7F, 0xE3,\n  0xE7, 0xFF, 0x3F, 0x7E, 0xFF, 0xFB, 0xE7, 0xFF, 0x9E, 0x1F, 0xF1, 0xF0,\n  0xFF, 0x8F, 0x83, 0xF8, 0x7C, 0x1F, 0xC3, 0xF0, 0xFF, 0x9F, 0xFF, 0xFC,\n  0x7F, 0xFF, 0xE3, 0xFF, 0xFF, 0x0F, 0xFD, 0xF0, 0x1F, 0x80, 0x00, 0x7E,\n  0xFD, 0xF3, 0xE7, 0xCF, 0x3E, 0x7C, 0xF1, 0xE3, 0xC7, 0x0E, 0x18, 0x00,\n  0x00, 0x18, 0x00, 0xF0, 0x07, 0xC0, 0x3F, 0x01, 0xF8, 0x07, 0xC0, 0x3E,\n  0x01, 0xF8, 0x07, 0xC0, 0x3E, 0x00, 0xF8, 0x07, 0xC0, 0x1F, 0x00, 0xF8,\n  0x03, 0xE0, 0x1F, 0x00, 0x7C, 0x01, 0xF0, 0x07, 0xC0, 0x3E, 0x00, 0xF8,\n  0x03, 0xE0, 0x0F, 0x80, 0x3E, 0x00, 0xF8, 0x03, 0xE0, 0x0F, 0x80, 0x3E,\n  0x00, 0xFC, 0x01, 0xF0, 0x07, 0xC0, 0x1F, 0x80, 0x7E, 0x00, 0xFC, 0x03,\n  0xF0, 0x07, 0xC0, 0x1E, 0x00, 0x00, 0xC0, 0x07, 0x80, 0x3F, 0x00, 0xFC,\n  0x03, 0xF0, 0x07, 0xE0, 0x1F, 0x80, 0x3E, 0x00, 0xF8, 0x03, 0xF0, 0x07,\n  0xC0, 0x1F, 0x00, 0x7C, 0x01, 0xF0, 0x07, 0xC0, 0x1F, 0x00, 0x7C, 0x01,\n  0xF0, 0x07, 0xC0, 0x3E, 0x00, 0xF8, 0x03, 0xE0, 0x1F, 0x00, 0x7C, 0x01,\n  0xF0, 0x0F, 0x80, 0x3E, 0x01, 0xF0, 0x0F, 0xC0, 0x3E, 0x01, 0xF0, 0x0F,\n  0xC0, 0x3E, 0x01, 0xF0, 0x0F, 0x80, 0x3E, 0x00, 0xF0, 0x00, 0x00, 0x3C,\n  0x00, 0x01, 0xE0, 0x00, 0x1F, 0x00, 0x00, 0xF8, 0x00, 0x07, 0xC0, 0x08,\n  0x3C, 0x09, 0xF9, 0xE7, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF,\n  0x87, 0xFF, 0xE0, 0x07, 0xF8, 0x00, 0x7F, 0xC0, 0x07, 0xFF, 0x00, 0x7F,\n  0xF8, 0x07, 0xE7, 0xE0, 0x3E, 0x3F, 0x01, 0xE0, 0xF8, 0x0E, 0x07, 0x80,\n  0x00, 0x07, 0x00, 0x00, 0x0F, 0x80, 0x00, 0x0F, 0x00, 0x00, 0x0F, 0x00,\n  0x00, 0x1F, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x1E, 0x00,\n  0x00, 0x3E, 0x00, 0x00, 0x3E, 0x00, 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0x00, 0x7C, 0x00,\n  0x00, 0x78, 0x00, 0x00, 0x78, 0x00, 0x00, 0xF8, 0x00, 0x00, 0xF8, 0x00,\n  0x00, 0xF8, 0x00, 0x00, 0xF0, 0x00, 0x00, 0xF0, 0x00, 0x01, 0xF0, 0x00,\n  0x01, 0xF0, 0x00, 0x00, 0xE0, 0x00, 0x03, 0xF0, 0x7E, 0x07, 0xC0, 0xFC,\n  0x0F, 0x81, 0xF0, 0x1E, 0x03, 0xE0, 0x3C, 0x07, 0x80, 0x78, 0x0F, 0x00,\n  0xE0, 0x0C, 0x00, 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0x3C, 0xFF, 0xFF, 0xFF, 0xCF, 0x00,\n  0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x01, 0xF0, 0x00,\n  0x00, 0x3E, 0x00, 0x00, 0x03, 0xE0, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x0F,\n  0x80, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x03, 0xE0, 0x00,\n  0x00, 0x3E, 0x00, 0x00, 0x07, 0xC0, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x1F,\n  0x80, 0x00, 0x01, 0xF0, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x07, 0xE0, 0x00,\n  0x00, 0x7C, 0x00, 0x00, 0x0F, 0x80, 0x00, 0x01, 0xF8, 0x00, 0x00, 0x1F,\n  0x00, 0x00, 0x03, 0xE0, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x07, 0xC0, 0x00,\n  0x00, 0xF8, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x01, 0xF0, 0x00, 0x00, 0x3E,\n  0x00, 0x00, 0x07, 0xC0, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x0F, 0x80, 0x00,\n  0x01, 0xF0, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x03, 0xE0, 0x00, 0x00, 0x7C,\n  0x00, 0x00, 0x07, 0xC0, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x07, 0x00, 0x00,\n  0x00, 0x00, 0x0F, 0xC0, 0x00, 0xFF, 0xE0, 0x03, 0xFF, 0xE0, 0x1F, 0xFF,\n  0xE0, 0x7F, 0xFF, 0xC0, 0xFC, 0x1F, 0x83, 0xF0, 0x1F, 0x8F, 0xC0, 0x1F,\n  0x1F, 0x00, 0x3E, 0x7C, 0x00, 0x7C, 0xF8, 0x00, 0xF9, 0xF0, 0x01, 0xF3,\n  0xC0, 0x07, 0xCF, 0x80, 0x0F, 0x9F, 0x00, 0x1E, 0x3E, 0x00, 0x3C, 0x78,\n  0x00, 0xF8, 0xF0, 0x01, 0xF3, 0xE0, 0x03, 0xE7, 0xC0, 0x07, 0x8F, 0x80,\n  0x1F, 0x1F, 0x00, 0x3E, 0x3E, 0x00, 0xF8, 0x7C, 0x01, 0xF0, 0xFC, 0x07,\n  0xC1, 0xFC, 0x3F, 0x81, 0xFF, 0xFE, 0x03, 0xFF, 0xF8, 0x03, 0xFF, 0xE0,\n  0x03, 0xFF, 0x00, 0x01, 0xF8, 0x00, 0x00, 0x00, 0x07, 0xE0, 0x00, 0x7E,\n  0x00, 0x0F, 0xF0, 0x01, 0xFF, 0x80, 0x1F, 0xFC, 0x03, 0xFB, 0xE0, 0x1F,\n  0x9E, 0x00, 0xF1, 0xF0, 0x00, 0x0F, 0x80, 0x00, 0x7C, 0x00, 0x03, 0xE0,\n  0x00, 0x1E, 0x00, 0x01, 0xF0, 0x00, 0x0F, 0x80, 0x00, 0x7C, 0x00, 0x03,\n  0xC0, 0x00, 0x1E, 0x00, 0x01, 0xF0, 0x00, 0x0F, 0x80, 0x00, 0x7C, 0x00,\n  0x03, 0xC0, 0x00, 0x3E, 0x00, 0x01, 0xF0, 0x00, 0x0F, 0x80, 0x00, 0x7C,\n  0x01, 0xFF, 0xFF, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x3F,\n  0xFF, 0xF0, 0x00, 0x03, 0xF8, 0x00, 0x03, 0xFF, 0x80, 0x03, 0xFF, 0xF0,\n  0x01, 0xFF, 0xFE, 0x00, 0xFF, 0xFF, 0x80, 0x7F, 0x07, 0xF0, 0x1F, 0x00,\n  0xFC, 0x0F, 0x80, 0x1F, 0x03, 0xE0, 0x07, 0xC0, 0xF0, 0x01, 0xF0, 0x00,\n  0x00, 0xF8, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x1F, 0xC0,\n  0x00, 0x0F, 0xE0, 0x00, 0x07, 0xF0, 0x00, 0x07, 0xF8, 0x00, 0x03, 0xF8,\n  0x00, 0x03, 0xFC, 0x00, 0x01, 0xFE, 0x00, 0x01, 0xFE, 0x00, 0x00, 0xFF,\n  0x00, 0x00, 0xFF, 0x00, 0x00, 0x7F, 0x80, 0x70, 0x3F, 0x80, 0x3E, 0x1F,\n  0xFF, 0xFF, 0x07, 0xFF, 0xFF, 0xC1, 0xFF, 0xFF, 0xF0, 0xFF, 0xFF, 0xFC,\n  0x3F, 0xFF, 0xFF, 0x00, 0x00, 0x07, 0xF8, 0x00, 0x0F, 0xFE, 0x00, 0x1F,\n  0xFF, 0x80, 0x1F, 0xFF, 0xE0, 0x1F, 0xFF, 0xF8, 0x0F, 0x81, 0xFC, 0x07,\n  0x00, 0x3E, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x0F, 0x80, 0x00, 0x0F, 0xC0,\n  0x00, 0x07, 0xC0, 0x00, 0x0F, 0xC0, 0x01, 0xFF, 0xC0, 0x01, 0xFF, 0xC0,\n  0x00, 0xFF, 0x80, 0x00, 0x7F, 0xE0, 0x00, 0x1F, 0xF8, 0x00, 0x00, 0xFE,\n  0x00, 0x00, 0x1F, 0x80, 0x00, 0x07, 0xC0, 0x00, 0x03, 0xE0, 0x00, 0x01,\n  0xF0, 0x00, 0x00, 0xF8, 0x00, 0x00, 0xF8, 0x00, 0x00, 0xFC, 0x3C, 0x01,\n  0xFC, 0x3F, 0xFF, 0xFC, 0x1F, 0xFF, 0xFC, 0x0F, 0xFF, 0xFC, 0x03, 0xFF,\n  0xFC, 0x00, 0x3F, 0xF0, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x07, 0xF0, 0x00,\n  0x3F, 0xC0, 0x01, 0xFE, 0x00, 0x0F, 0xF8, 0x00, 0x7F, 0xE0, 0x03, 0xFF,\n  0x80, 0x1F, 0xBE, 0x00, 0x7C, 0xF0, 0x03, 0xE7, 0xC0, 0x1F, 0x1F, 0x00,\n  0xF8, 0x7C, 0x07, 0xE1, 0xE0, 0x3F, 0x07, 0x81, 0xF8, 0x3E, 0x07, 0xC0,\n  0xF8, 0x3E, 0x03, 0xC1, 0xFF, 0xFF, 0xCF, 0xFF, 0xFF, 0xBF, 0xFF, 0xFE,\n  0xFF, 0xFF, 0xF3, 0xFF, 0xFF, 0x80, 0x00, 0xF8, 0x00, 0x3F, 0xF8, 0x01,\n  0xFF, 0xE0, 0x07, 0xFF, 0x80, 0x1F, 0xFE, 0x00, 0x7F, 0xF0, 0x01, 0xFF,\n  0xFF, 0x00, 0xFF, 0xFF, 0x80, 0x7F, 0xFF, 0xC0, 0x3F, 0xFF, 0xE0, 0x3F,\n  0xFF, 0xE0, 0x1F, 0x00, 0x00, 0x0F, 0x80, 0x00, 0x07, 0xC0, 0x00, 0x03,\n  0xC0, 0x00, 0x03, 0xE0, 0x00, 0x01, 0xF7, 0xF0, 0x00, 0xFF, 0xFE, 0x00,\n  0x7F, 0xFF, 0x80, 0x3F, 0xFF, 0xE0, 0x1F, 0xFF, 0xF0, 0x0F, 0x01, 0xFC,\n  0x00, 0x00, 0x7E, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x0F, 0x80, 0x00, 0x07,\n  0xC0, 0x00, 0x03, 0xE0, 0x00, 0x01, 0xF0, 0x00, 0x01, 0xF0, 0x00, 0x00,\n  0xF8, 0x00, 0x00, 0xF8, 0x3C, 0x03, 0xFC, 0x3F, 0xFF, 0xFC, 0x1F, 0xFF,\n  0xFC, 0x0F, 0xFF, 0xFC, 0x03, 0xFF, 0xF8, 0x00, 0x3F, 0xE0, 0x00, 0x00,\n  0x01, 0xFC, 0x00, 0x07, 0xFE, 0x00, 0x1F, 0xFF, 0x00, 0x7F, 0xFF, 0x00,\n  0xFF, 0xFE, 0x01, 0xFE, 0x1C, 0x03, 0xF8, 0x00, 0x07, 0xE0, 0x00, 0x0F,\n  0xC0, 0x00, 0x1F, 0x80, 0x00, 0x1F, 0x00, 0x00, 0x3E, 0x3E, 0x00, 0x3E,\n  0xFF, 0x80, 0x7D, 0xFF, 0xC0, 0x7F, 0xFF, 0xE0, 0x7F, 0xFF, 0xE0, 0x7F,\n  0x87, 0xF0, 0xFF, 0x03, 0xF0, 0xFC, 0x01, 0xF0, 0xF8, 0x01, 0xF0, 0xF8,\n  0x01, 0xF0, 0xF8, 0x01, 0xF0, 0xF8, 0x03, 0xE0, 0xF8, 0x03, 0xE0, 0xFC,\n  0x07, 0xC0, 0xFE, 0x0F, 0xC0, 0x7F, 0xFF, 0x80, 0x7F, 0xFF, 0x00, 0x3F,\n  0xFE, 0x00, 0x1F, 0xFC, 0x00, 0x07, 0xF0, 0x00, 0x7F, 0xFF, 0xFD, 0xFF,\n  0xFF, 0xE7, 0xFF, 0xFF, 0xBF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFB, 0xE0, 0x07,\n  0xCF, 0x00, 0x1F, 0x00, 0x00, 0xF8, 0x00, 0x03, 0xE0, 0x00, 0x1F, 0x00,\n  0x00, 0x7C, 0x00, 0x03, 0xE0, 0x00, 0x0F, 0x80, 0x00, 0x7C, 0x00, 0x01,\n  0xE0, 0x00, 0x0F, 0x80, 0x00, 0x7C, 0x00, 0x01, 0xF0, 0x00, 0x0F, 0x80,\n  0x00, 0x3E, 0x00, 0x01, 0xF0, 0x00, 0x07, 0xC0, 0x00, 0x3E, 0x00, 0x00,\n  0xF8, 0x00, 0x07, 0xC0, 0x00, 0x1F, 0x00, 0x00, 0xF8, 0x00, 0x03, 0xE0,\n  0x00, 0x1F, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x1F, 0xC0, 0x00, 0xFF,\n  0xE0, 0x07, 0xFF, 0xE0, 0x1F, 0xFF, 0xE0, 0x7F, 0xFF, 0xC0, 0xFC, 0x1F,\n  0xC3, 0xF0, 0x1F, 0x8F, 0xC0, 0x1F, 0x1F, 0x00, 0x3E, 0x3E, 0x00, 0x7C,\n  0x7C, 0x01, 0xF0, 0xFC, 0x07, 0xE0, 0xFC, 0x1F, 0x81, 0xFF, 0xFE, 0x01,\n  0xFF, 0xF0, 0x01, 0xFF, 0xE0, 0x0F, 0xFF, 0xE0, 0x3F, 0xFF, 0xE0, 0xFE,\n  0x0F, 0xC3, 0xF0, 0x0F, 0xC7, 0xC0, 0x0F, 0x9F, 0x00, 0x1F, 0x3E, 0x00,\n  0x3E, 0x7C, 0x00, 0xFC, 0xFC, 0x03, 0xF1, 0xFC, 0x1F, 0xE3, 0xFF, 0xFF,\n  0x83, 0xFF, 0xFE, 0x03, 0xFF, 0xF8, 0x03, 0xFF, 0xC0, 0x01, 0xFC, 0x00,\n  0x00, 0x00, 0x0F, 0xE0, 0x00, 0x3F, 0xF8, 0x00, 0xFF, 0xFC, 0x01, 0xFF,\n  0xFE, 0x03, 0xFF, 0xFE, 0x03, 0xF0, 0x7F, 0x07, 0xE0, 0x3F, 0x07, 0xC0,\n  0x1F, 0x0F, 0xC0, 0x1F, 0x0F, 0x80, 0x1F, 0x0F, 0x80, 0x1F, 0x0F, 0x80,\n  0x3F, 0x0F, 0xC0, 0x7F, 0x0F, 0xE1, 0xFF, 0x07, 0xFF, 0xFE, 0x07, 0xFF,\n  0xFE, 0x03, 0xFF, 0xBE, 0x01, 0xFF, 0x7C, 0x00, 0xFC, 0x7C, 0x00, 0x00,\n  0xFC, 0x00, 0x01, 0xF8, 0x00, 0x01, 0xF8, 0x00, 0x03, 0xF0, 0x00, 0x0F,\n  0xE0, 0x00, 0x1F, 0xC0, 0x38, 0x7F, 0x80, 0x7F, 0xFF, 0x00, 0xFF, 0xFE,\n  0x00, 0xFF, 0xF8, 0x00, 0x7F, 0xE0, 0x00, 0x3F, 0x80, 0x00, 0x07, 0x83,\n  0xF1, 0xFC, 0x7F, 0x1F, 0x83, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x1F, 0x8F, 0xE3, 0xF8, 0xFC,\n  0x1E, 0x00, 0x00, 0x3C, 0x00, 0xFC, 0x03, 0xF8, 0x07, 0xF0, 0x0F, 0xC0,\n  0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xF8, 0x03, 0xE0, 0x0F, 0xC0,\n  0x1F, 0x00, 0x7C, 0x00, 0xF0, 0x03, 0xE0, 0x07, 0x80, 0x1E, 0x00, 0x38,\n  0x00, 0xF0, 0x01, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,\n  0x03, 0xC0, 0x00, 0x0F, 0xE0, 0x00, 0x1F, 0xF0, 0x00, 0x3F, 0xE0, 0x00,\n  0x7F, 0xC0, 0x00, 0xFF, 0x80, 0x03, 0xFF, 0x00, 0x07, 0xFE, 0x00, 0x0F,\n  0xFC, 0x00, 0x1F, 0xF0, 0x00, 0x1F, 0xFC, 0x00, 0x01, 0xFF, 0x00, 0x00,\n  0x3F, 0xE0, 0x00, 0x0F, 0xFC, 0x00, 0x01, 0xFF, 0x00, 0x00, 0x3F, 0xE0,\n  0x00, 0x07, 0xFC, 0x00, 0x01, 0xFF, 0x00, 0x00, 0x3F, 0x80, 0x00, 0x07,\n  0x80, 0x1F, 0xFF, 0xFF, 0xCF, 0xFF, 0xFF, 0xF3, 0xFF, 0xFF, 0xFC, 0xFF,\n  0xFF, 0xFF, 0x3F, 0xFF, 0xFF, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0xFF, 0xFF, 0xCF, 0xFF, 0xFF,\n  0xF3, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF, 0xFF, 0x3F, 0xFF, 0xFF, 0x80, 0x00,\n  0x00, 0x00, 0x07, 0x80, 0x00, 0x07, 0xF0, 0x00, 0x03, 0xFC, 0x00, 0x00,\n  0xFF, 0x80, 0x00, 0x1F, 0xF0, 0x00, 0x07, 0xFE, 0x00, 0x00, 0xFF, 0xC0,\n  0x00, 0x1F, 0xF0, 0x00, 0x07, 0xFE, 0x00, 0x00, 0xFF, 0xC0, 0x00, 0x7F,\n  0xE0, 0x00, 0xFF, 0xC0, 0x01, 0xFF, 0x80, 0x03, 0xFE, 0x00, 0x07, 0xFC,\n  0x00, 0x1F, 0xF8, 0x00, 0x3F, 0xF0, 0x00, 0x3F, 0xC0, 0x00, 0x1F, 0x80,\n  0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xFC, 0x01, 0xFF,\n  0xE1, 0xFF, 0xFE, 0x3F, 0xFF, 0xE7, 0xFF, 0xFF, 0xF8, 0x1F, 0xFE, 0x00,\n  0xFF, 0x80, 0x1F, 0xF0, 0x03, 0xE0, 0x00, 0x7C, 0x00, 0x1F, 0x00, 0x0F,\n  0xE0, 0x07, 0xF8, 0x07, 0xFE, 0x01, 0xFF, 0x80, 0x7F, 0xC0, 0x0F, 0xE0,\n  0x01, 0xF0, 0x00, 0x3C, 0x00, 0x03, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0xF0, 0x00, 0x3F, 0x00, 0x0F, 0xE0, 0x01, 0xFC, 0x00,\n  0x3F, 0x00, 0x03, 0xC0, 0x00, 0x00, 0x0F, 0xE0, 0x00, 0x7F, 0xF0, 0x01,\n  0xFF, 0xF0, 0x0F, 0xFF, 0xE0, 0x3F, 0x07, 0xE0, 0x7C, 0x07, 0xC1, 0xE0,\n  0x07, 0x87, 0xC0, 0x0F, 0x0F, 0x00, 0x1C, 0x3C, 0x00, 0x78, 0x78, 0x07,\n  0xF1, 0xE0, 0x3F, 0xE3, 0xC1, 0xFF, 0x87, 0x87, 0xFF, 0x0E, 0x1F, 0x9E,\n  0x3C, 0x7C, 0x3C, 0x78, 0xF0, 0x78, 0xF3, 0xC0, 0xE1, 0xC7, 0x83, 0xC3,\n  0x8F, 0x07, 0x8F, 0x1E, 0x0F, 0x1E, 0x3E, 0x1C, 0x3C, 0x7F, 0xFC, 0x78,\n  0x7F, 0xFC, 0xF0, 0x7F, 0xF1, 0xE0, 0x3F, 0xE3, 0xC0, 0x00, 0x07, 0x80,\n  0x00, 0x0F, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x3F, 0x01,\n  0xC0, 0x7F, 0xFF, 0x80, 0x7F, 0xFE, 0x00, 0x7F, 0xF8, 0x00, 0x3F, 0x80,\n  0x00, 0x00, 0x3F, 0xFE, 0x00, 0x01, 0xFF, 0xF8, 0x00, 0x07, 0xFF, 0xE0,\n  0x00, 0x1F, 0xFF, 0x80, 0x00, 0x7F, 0xFE, 0x00, 0x00, 0x0F, 0xFC, 0x00,\n  0x00, 0x7F, 0xF0, 0x00, 0x01, 0xE7, 0xC0, 0x00, 0x0F, 0x9F, 0x00, 0x00,\n  0x7C, 0x7C, 0x00, 0x01, 0xE1, 0xF8, 0x00, 0x0F, 0x87, 0xE0, 0x00, 0x7C,\n  0x0F, 0x80, 0x01, 0xF0, 0x3E, 0x00, 0x0F, 0x80, 0xF8, 0x00, 0x3F, 0xFF,\n  0xF0, 0x01, 0xFF, 0xFF, 0xC0, 0x0F, 0xFF, 0xFF, 0x00, 0x3F, 0xFF, 0xFC,\n  0x01, 0xFF, 0xFF, 0xF8, 0x0F, 0xC0, 0x07, 0xE0, 0x3E, 0x00, 0x0F, 0x87,\n  0xFF, 0x03, 0xFF, 0xBF, 0xFC, 0x1F, 0xFF, 0xFF, 0xF0, 0x7F, 0xFF, 0xFF,\n  0xC1, 0xFF, 0xEF, 0xFE, 0x07, 0xFF, 0x00, 0x03, 0xFF, 0xFF, 0x80, 0x3F,\n  0xFF, 0xFF, 0x01, 0xFF, 0xFF, 0xFC, 0x0F, 0xFF, 0xFF, 0xE0, 0x7F, 0xFF,\n  0xFF, 0x80, 0x7C, 0x00, 0xFC, 0x03, 0xE0, 0x03, 0xE0, 0x1E, 0x00, 0x1F,\n  0x01, 0xF0, 0x00, 0xF8, 0x0F, 0x80, 0x0F, 0x80, 0x7C, 0x01, 0xF8, 0x03,\n  0xFF, 0xFF, 0x80, 0x1F, 0xFF, 0xF8, 0x01, 0xFF, 0xFF, 0xC0, 0x0F, 0xFF,\n  0xFF, 0x80, 0x7F, 0xFF, 0xFC, 0x03, 0xC0, 0x0F, 0xF0, 0x3E, 0x00, 0x1F,\n  0x81, 0xF0, 0x00, 0x7C, 0x0F, 0x80, 0x03, 0xE0, 0x78, 0x00, 0x1F, 0x03,\n  0xC0, 0x03, 0xF1, 0xFF, 0xFF, 0xFF, 0x9F, 0xFF, 0xFF, 0xF8, 0xFF, 0xFF,\n  0xFF, 0x87, 0xFF, 0xFF, 0xF0, 0x1F, 0xFF, 0xFE, 0x00, 0x00, 0x07, 0xF0,\n  0x00, 0x03, 0xFF, 0xE6, 0x00, 0x7F, 0xFF, 0xF0, 0x1F, 0xFF, 0xFF, 0x03,\n  0xFF, 0xFF, 0xF0, 0x7F, 0x81, 0xFF, 0x0F, 0xE0, 0x07, 0xE1, 0xF8, 0x00,\n  0x3E, 0x1F, 0x00, 0x03, 0xE3, 0xF0, 0x00, 0x3C, 0x3E, 0x00, 0x03, 0xC7,\n  0xE0, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x07, 0xC0, 0x00, 0x00, 0x7C, 0x00,\n  0x00, 0x0F, 0x80, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x0F, 0x80, 0x00, 0x00,\n  0xF8, 0x00, 0x00, 0x0F, 0x80, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x0F, 0xC0,\n  0x00, 0x70, 0x7E, 0x00, 0x1F, 0x07, 0xF8, 0x07, 0xF0, 0x3F, 0xFF, 0xFF,\n  0x03, 0xFF, 0xFF, 0xE0, 0x1F, 0xFF, 0xF8, 0x00, 0x7F, 0xFE, 0x00, 0x00,\n  0xFF, 0x00, 0x00, 0x03, 0xFF, 0xFC, 0x00, 0x7F, 0xFF, 0xF0, 0x07, 0xFF,\n  0xFF, 0x80, 0x7F, 0xFF, 0xFC, 0x03, 0xFF, 0xFF, 0xE0, 0x1F, 0x00, 0xFE,\n  0x01, 0xF0, 0x07, 0xE0, 0x1E, 0x00, 0x3F, 0x01, 0xE0, 0x01, 0xF0, 0x3E,\n  0x00, 0x1F, 0x03, 0xE0, 0x01, 0xF0, 0x3E, 0x00, 0x1F, 0x03, 0xC0, 0x01,\n  0xF0, 0x7C, 0x00, 0x1F, 0x07, 0xC0, 0x03, 0xF0, 0x7C, 0x00, 0x3E, 0x07,\n  0x80, 0x03, 0xE0, 0x78, 0x00, 0x7E, 0x0F, 0x80, 0x07, 0xC0, 0xF8, 0x00,\n  0xFC, 0x0F, 0x80, 0x1F, 0x80, 0xF0, 0x07, 0xF0, 0x7F, 0xFF, 0xFE, 0x07,\n  0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xF8, 0x0F, 0xFF, 0xFE, 0x00, 0x7F, 0xFF,\n  0x00, 0x00, 0x03, 0xFF, 0xFF, 0xF8, 0x3F, 0xFF, 0xFF, 0xC3, 0xFF, 0xFF,\n  0xFE, 0x1F, 0xFF, 0xFF, 0xE0, 0x7F, 0xFF, 0xFF, 0x00, 0x78, 0x00, 0xF8,\n  0x07, 0xC0, 0x07, 0xC0, 0x3E, 0x00, 0x3E, 0x01, 0xF0, 0xF1, 0xE0, 0x0F,\n  0x0F, 0x8E, 0x00, 0x78, 0x7C, 0x00, 0x07, 0xFF, 0xE0, 0x00, 0x3F, 0xFE,\n  0x00, 0x01, 0xFF, 0xF0, 0x00, 0x0F, 0xFF, 0x80, 0x00, 0xFF, 0xFC, 0x00,\n  0x07, 0xC3, 0xC0, 0x00, 0x3E, 0x1E, 0x1E, 0x01, 0xE0, 0xE0, 0xF0, 0x0F,\n  0x00, 0x0F, 0x80, 0xF8, 0x00, 0x7C, 0x07, 0xC0, 0x03, 0xE1, 0xFF, 0xFF,\n  0xFE, 0x1F, 0xFF, 0xFF, 0xF0, 0xFF, 0xFF, 0xFF, 0x87, 0xFF, 0xFF, 0xFC,\n  0x3F, 0xFF, 0xFF, 0xC0, 0x03, 0xFF, 0xFF, 0xFE, 0x0F, 0xFF, 0xFF, 0xF8,\n  0x1F, 0xFF, 0xFF, 0xF0, 0x3F, 0xFF, 0xFF, 0xE0, 0x3F, 0xFF, 0xFF, 0xC0,\n  0x1F, 0x00, 0x0F, 0x80, 0x3E, 0x00, 0x1E, 0x00, 0x78, 0x00, 0x7C, 0x00,\n  0xF0, 0x70, 0xF8, 0x03, 0xE1, 0xF0, 0xE0, 0x07, 0xC3, 0xC0, 0x00, 0x0F,\n  0xFF, 0x80, 0x00, 0x1F, 0xFF, 0x00, 0x00, 0x7F, 0xFE, 0x00, 0x00, 0xFF,\n  0xFC, 0x00, 0x01, 0xFF, 0xF0, 0x00, 0x03, 0xC3, 0xE0, 0x00, 0x07, 0x87,\n  0xC0, 0x00, 0x1F, 0x07, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x7C, 0x00,\n  0x00, 0x00, 0xF0, 0x00, 0x00, 0x0F, 0xFF, 0xC0, 0x00, 0x3F, 0xFF, 0x80,\n  0x00, 0xFF, 0xFF, 0x00, 0x01, 0xFF, 0xFE, 0x00, 0x01, 0xFF, 0xF8, 0x00,\n  0x00, 0x00, 0x07, 0xF8, 0x60, 0x03, 0xFF, 0xFF, 0x00, 0x7F, 0xFF, 0xF0,\n  0x1F, 0xFF, 0xFF, 0x03, 0xFF, 0xFF, 0xE0, 0x7F, 0x80, 0xFE, 0x0F, 0xE0,\n  0x03, 0xE0, 0xF8, 0x00, 0x3C, 0x1F, 0x00, 0x03, 0xC3, 0xF0, 0x00, 0x00,\n  0x3E, 0x00, 0x00, 0x03, 0xE0, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x07, 0xC0,\n  0x00, 0x00, 0x7C, 0x00, 0x00, 0x07, 0xC0, 0x7F, 0xFC, 0xF8, 0x0F, 0xFF,\n  0xEF, 0x80, 0xFF, 0xFE, 0xF8, 0x0F, 0xFF, 0xCF, 0x80, 0x7F, 0xF8, 0xF8,\n  0x00, 0x1F, 0x0F, 0xC0, 0x01, 0xF0, 0xFE, 0x00, 0x1F, 0x07, 0xF8, 0x07,\n  0xE0, 0x7F, 0xFF, 0xFE, 0x03, 0xFF, 0xFF, 0xE0, 0x1F, 0xFF, 0xFC, 0x00,\n  0x7F, 0xFE, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x01, 0xFF, 0x0F, 0xF8, 0x0F,\n  0xFC, 0x7F, 0xF0, 0x7F, 0xF1, 0xFF, 0xC1, 0xFF, 0xC7, 0xFE, 0x03, 0xFE,\n  0x1F, 0xF0, 0x07, 0xC0, 0x0F, 0x80, 0x1F, 0x00, 0x3C, 0x00, 0x78, 0x00,\n  0xF0, 0x01, 0xE0, 0x07, 0xC0, 0x0F, 0x80, 0x1F, 0x00, 0x3E, 0x00, 0x7C,\n  0x00, 0xFF, 0xFF, 0xE0, 0x03, 0xFF, 0xFF, 0x80, 0x1F, 0xFF, 0xFE, 0x00,\n  0x7F, 0xFF, 0xF8, 0x01, 0xFF, 0xFF, 0xC0, 0x07, 0x80, 0x1F, 0x00, 0x1E,\n  0x00, 0x7C, 0x00, 0xF8, 0x01, 0xF0, 0x03, 0xE0, 0x07, 0xC0, 0x0F, 0x80,\n  0x1E, 0x00, 0x3C, 0x00, 0xF8, 0x07, 0xFE, 0x1F, 0xF8, 0x3F, 0xF8, 0xFF,\n  0xF0, 0xFF, 0xE3, 0xFF, 0xC3, 0xFF, 0x8F, 0xFE, 0x0F, 0xFC, 0x3F, 0xF8,\n  0x00, 0x03, 0xFF, 0xFF, 0x83, 0xFF, 0xFF, 0xC1, 0xFF, 0xFF, 0xE0, 0xFF,\n  0xFF, 0xF0, 0x7F, 0xFF, 0xF0, 0x00, 0x7C, 0x00, 0x00, 0x3E, 0x00, 0x00,\n  0x1E, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x0F, 0x80, 0x00, 0x07, 0xC0, 0x00,\n  0x03, 0xC0, 0x00, 0x03, 0xE0, 0x00, 0x01, 0xF0, 0x00, 0x00, 0xF8, 0x00,\n  0x00, 0x7C, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x1F, 0x00,\n  0x00, 0x0F, 0x80, 0x00, 0x07, 0x80, 0x00, 0x07, 0xC0, 0x01, 0xFF, 0xFF,\n  0xC1, 0xFF, 0xFF, 0xE0, 0xFF, 0xFF, 0xF0, 0x7F, 0xFF, 0xF8, 0x1F, 0xFF,\n  0xF8, 0x00, 0x00, 0x07, 0xFF, 0xFE, 0x00, 0x1F, 0xFF, 0xFC, 0x00, 0x3F,\n  0xFF, 0xF8, 0x00, 0x7F, 0xFF, 0xF0, 0x00, 0x7F, 0xFF, 0xC0, 0x00, 0x01,\n  0xF0, 0x00, 0x00, 0x03, 0xE0, 0x00, 0x00, 0x07, 0x80, 0x00, 0x00, 0x0F,\n  0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0xF8,\n  0x00, 0x00, 0x01, 0xE0, 0x00, 0x00, 0x07, 0xC0, 0x07, 0x00, 0x0F, 0x80,\n  0x1F, 0x00, 0x1F, 0x00, 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 0x00, 0xF0, 0x7E, 0x1F, 0x00, 0x7C, 0x1F, 0x07, 0xC0, 0x1F, 0x00, 0x01,\n  0xF0, 0x07, 0xC0, 0x00, 0x78, 0x07, 0xFE, 0x01, 0xFF, 0x83, 0xFF, 0xC0,\n  0xFF, 0xF0, 0xFF, 0xF0, 0x7F, 0xFC, 0x3F, 0xF8, 0x1F, 0xFE, 0x0F, 0xFC,\n  0x03, 0xFF, 0x00, 0x07, 0xF8, 0x07, 0xFF, 0x0F, 0xFC, 0x0F, 0xFF, 0x0F,\n  0xFC, 0x0F, 0xFF, 0x0F, 0xFC, 0x0F, 0xFF, 0x0F, 0xFE, 0x0F, 0xFE, 0x01,\n  0xFE, 0x00, 0xF8, 0x01, 0xFF, 0x00, 0xF0, 0x01, 0xFF, 0x01, 0xF0, 0x03,\n  0xFF, 0x81, 0xF0, 0x03, 0xFF, 0x81, 0xF0, 0x03, 0xEF, 0xC1, 0xF0, 0x03,\n  0xCF, 0xC1, 0xE0, 0x07, 0xC7, 0xE3, 0xE0, 0x07, 0xC7, 0xE3, 0xE0, 0x07,\n  0xC3, 0xF3, 0xE0, 0x07, 0xC3, 0xF3, 0xC0, 0x07, 0x81, 0xF7, 0xC0, 0x0F,\n  0x81, 0xFF, 0xC0, 0x0F, 0x80, 0xFF, 0xC0, 0x0F, 0x80, 0xFF, 0xC0, 0x0F,\n  0x00, 0xFF, 0x80, 0x0F, 0x00, 0x7F, 0x80, 0x7F, 0xF0, 0x7F, 0x80, 0xFF,\n  0xF0, 0x3F, 0x80, 0xFF, 0xF0, 0x3F, 0x00, 0xFF, 0xF0, 0x1F, 0x00, 0x7F,\n  0xE0, 0x1F, 0x00, 0x00, 0x07, 0xF0, 0x00, 0x03, 0xFF, 0x80, 0x01, 0xFF,\n  0xF8, 0x00, 0xFF, 0xFF, 0x80, 0x3F, 0xFF, 0xF8, 0x0F, 0xF0, 0x7F, 0x83,\n  0xF8, 0x03, 0xF0, 0xFC, 0x00, 0x7E, 0x1F, 0x00, 0x07, 0xE7, 0xE0, 0x00,\n  0x7C, 0xF8, 0x00, 0x0F, 0xBE, 0x00, 0x01, 0xF7, 0xC0, 0x00, 0x3E, 0xF0,\n  0x00, 0x07, 0xFE, 0x00, 0x00, 0xFF, 0xC0, 0x00, 0x3E, 0xF8, 0x00, 0x07,\n  0xDF, 0x00, 0x00, 0xFB, 0xE0, 0x00, 0x3E, 0x7C, 0x00, 0x0F, 0xCF, 0xC0,\n  0x01, 0xF0, 0xF8, 0x00, 0x7E, 0x1F, 0x80, 0x3F, 0x83, 0xFC, 0x1F, 0xE0,\n  0x3F, 0xFF, 0xF8, 0x03, 0xFF, 0xFE, 0x00, 0x3F, 0xFF, 0x00, 0x03, 0xFF,\n  0x80, 0x00, 0x1F, 0xC0, 0x00, 0x03, 0xFF, 0xFE, 0x00, 0x7F, 0xFF, 0xF8,\n  0x07, 0xFF, 0xFF, 0xC0, 0x7F, 0xFF, 0xFE, 0x07, 0xFF, 0xFF, 0xF0, 0x0F,\n  0x80, 0x7F, 0x00, 0xF8, 0x01, 0xF0, 0x0F, 0x00, 0x1F, 0x01, 0xF0, 0x01,\n  0xF0, 0x1F, 0x00, 0x1F, 0x01, 0xF0, 0x03, 0xE0, 0x1E, 0x00, 0x7E, 0x01,\n  0xE0, 0x0F, 0xC0, 0x3F, 0xFF, 0xFC, 0x03, 0xFF, 0xFF, 0x80, 0x3F, 0xFF,\n  0xE0, 0x03, 0xFF, 0xFC, 0x00, 0x7F, 0xFE, 0x00, 0x07, 0xC0, 0x00, 0x00,\n  0x7C, 0x00, 0x00, 0x07, 0x80, 0x00, 0x00, 0x78, 0x00, 0x00, 0x7F, 0xFF,\n  0x00, 0x0F, 0xFF, 0xF0, 0x00, 0xFF, 0xFF, 0x00, 0x0F, 0xFF, 0xF0, 0x00,\n  0x7F, 0xFE, 0x00, 0x00, 0x00, 0x07, 0xF0, 0x00, 0x07, 0xFF, 0x80, 0x03,\n  0xFF, 0xF8, 0x00, 0xFF, 0xFF, 0x80, 0x3F, 0xFF, 0xF8, 0x0F, 0xF0, 0x7F,\n  0x83, 0xF8, 0x03, 0xF0, 0xFC, 0x00, 0x3F, 0x1F, 0x00, 0x07, 0xE7, 0xC0,\n  0x00, 0x7D, 0xF8, 0x00, 0x0F, 0xBE, 0x00, 0x01, 0xF7, 0xC0, 0x00, 0x3F,\n  0xF0, 0x00, 0x07, 0xFE, 0x00, 0x00, 0xFF, 0xC0, 0x00, 0x3E, 0xF8, 0x00,\n  0x07, 0xDF, 0x00, 0x01, 0xFB, 0xE0, 0x00, 0x3E, 0x7E, 0x00, 0x0F, 0x8F,\n  0xC0, 0x03, 0xF0, 0xFC, 0x01, 0xFC, 0x1F, 0xE0, 0xFF, 0x01, 0xFF, 0xFF,\n  0xC0, 0x1F, 0xFF, 0xF0, 0x01, 0xFF, 0xFC, 0x00, 0x1F, 0xFE, 0x00, 0x01,\n  0xFE, 0x00, 0x00, 0x78, 0x00, 0x00, 0x1F, 0xF8, 0x38, 0x0F, 0xFF, 0xFF,\n  0x81, 0xFF, 0xFF, 0xF0, 0x7F, 0xFF, 0xFC, 0x0F, 0xFF, 0xFF, 0x00, 0xF0,\n  0x1F, 0x80, 0x00, 0x03, 0xFF, 0xFE, 0x00, 0x3F, 0xFF, 0xFC, 0x01, 0xFF,\n  0xFF, 0xF0, 0x0F, 0xFF, 0xFF, 0xC0, 0x3F, 0xFF, 0xFF, 0x00, 0x7C, 0x03,\n  0xF8, 0x03, 0xE0, 0x07, 0xC0, 0x1E, 0x00, 0x3E, 0x00, 0xF0, 0x01, 0xF0,\n  0x0F, 0x80, 0x1F, 0x80, 0x7C, 0x01, 0xF8, 0x03, 0xE0, 0x3F, 0x80, 0x1F,\n  0xFF, 0xFC, 0x01, 0xFF, 0xFF, 0x80, 0x0F, 0xFF, 0xF8, 0x00, 0x7F, 0xFF,\n  0x00, 0x03, 0xFF, 0xFC, 0x00, 0x1E, 0x07, 0xF0, 0x01, 0xF0, 0x1F, 0xC0,\n  0x0F, 0x80, 0x7E, 0x00, 0x7C, 0x03, 0xF8, 0x03, 0xC0, 0x0F, 0xC0, 0xFF,\n  0xE0, 0x7F, 0xCF, 0xFF, 0x01, 0xFF, 0xFF, 0xF8, 0x0F, 0xFF, 0xFF, 0xC0,\n  0x3F, 0xDF, 0xFC, 0x01, 0xFC, 0x00, 0x0F, 0xE1, 0x80, 0x0F, 0xFF, 0xF0,\n  0x0F, 0xFF, 0xFC, 0x07, 0xFF, 0xFF, 0x03, 0xFF, 0xFF, 0xC1, 0xFC, 0x0F,\n  0xE0, 0x7C, 0x01, 0xF8, 0x3E, 0x00, 0x3E, 0x0F, 0x80, 0x0F, 0x03, 0xE0,\n  0x03, 0xC0, 0xFC, 0x00, 0x00, 0x3F, 0xE0, 0x00, 0x07, 0xFF, 0x80, 0x01,\n  0xFF, 0xFC, 0x00, 0x3F, 0xFF, 0x80, 0x03, 0xFF, 0xF0, 0x00, 0x07, 0xFE,\n  0x00, 0x00, 0x3F, 0x80, 0x00, 0x03, 0xE1, 0xE0, 0x00, 0xF8, 0xF8, 0x00,\n  0x3E, 0x3E, 0x00, 0x1F, 0x8F, 0xC0, 0x0F, 0xC3, 0xFC, 0x0F, 0xF0, 0xFF,\n  0xFF, 0xF8, 0x3F, 0xFF, 0xFC, 0x0F, 0xFF, 0xFE, 0x03, 0x9F, 0xFE, 0x00,\n  0x01, 0xFE, 0x00, 0x00, 0x3F, 0xFF, 0xFF, 0xCF, 0xFF, 0xFF, 0xF7, 0xFF,\n  0xFF, 0xFD, 0xFF, 0xFF, 0xFE, 0x7F, 0xFF, 0xFF, 0x9F, 0x07, 0x83, 0xE7,\n  0x83, 0xE0, 0xFB, 0xE0, 0xF8, 0x3E, 0xF8, 0x3E, 0x0F, 0x3E, 0x0F, 0x07,\n  0xCF, 0x07, 0xC1, 0xF3, 0x81, 0xF0, 0x38, 0x00, 0x7C, 0x00, 0x00, 0x1E,\n  0x00, 0x00, 0x07, 0x80, 0x00, 0x03, 0xE0, 0x00, 0x00, 0xF8, 0x00, 0x00,\n  0x3E, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x07, 0xC0, 0x00, 0x01, 0xF0, 0x00,\n  0x00, 0x7C, 0x00, 0x07, 0xFF, 0xF8, 0x01, 0xFF, 0xFE, 0x00, 0xFF, 0xFF,\n  0x80, 0x3F, 0xFF, 0xE0, 0x07, 0xFF, 0xF0, 0x00, 0x3F, 0xF0, 0x7F, 0xE7,\n  0xFF, 0x8F, 0xFF, 0x7F, 0xF9, 0xFF, 0xF7, 0xFF, 0x1F, 0xFE, 0x7F, 0xF0,\n  0xFF, 0xC1, 0xE0, 0x01, 0xF0, 0x1E, 0x00, 0x1F, 0x03, 0xE0, 0x01, 0xF0,\n  0x3E, 0x00, 0x1F, 0x03, 0xE0, 0x01, 0xE0, 0x3C, 0x00, 0x3E, 0x07, 0xC0,\n  0x03, 0xE0, 0x7C, 0x00, 0x3E, 0x07, 0xC0, 0x03, 0xC0, 0x7C, 0x00, 0x3C,\n  0x07, 0x80, 0x07, 0xC0, 0xF8, 0x00, 0x7C, 0x0F, 0x80, 0x07, 0xC0, 0xF8,\n  0x00, 0x78, 0x0F, 0x80, 0x0F, 0x80, 0xFC, 0x01, 0xF8, 0x0F, 0xC0, 0x3F,\n  0x00, 0xFF, 0x07, 0xE0, 0x07, 0xFF, 0xFE, 0x00, 0x7F, 0xFF, 0xC0, 0x03,\n  0xFF, 0xF0, 0x00, 0x0F, 0xFE, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x7F, 0xF0,\n  0x1F, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0x03, 0xFF, 0xFF, 0xFC, 0x0F,\n  0xFF, 0x7F, 0xE0, 0x3F, 0xF8, 0x7C, 0x00, 0x1F, 0x01, 0xF0, 0x00, 0xF8,\n  0x07, 0xC0, 0x03, 0xE0, 0x1F, 0x80, 0x1F, 0x00, 0x3E, 0x00, 0xF8, 0x00,\n  0xF8, 0x03, 0xE0, 0x03, 0xE0, 0x1F, 0x00, 0x0F, 0xC0, 0xFC, 0x00, 0x1F,\n  0x03, 0xE0, 0x00, 0x7C, 0x1F, 0x00, 0x01, 0xF0, 0xFC, 0x00, 0x07, 0xC3,\n  0xE0, 0x00, 0x1F, 0x9F, 0x00, 0x00, 0x3E, 0xFC, 0x00, 0x00, 0xFB, 0xE0,\n  0x00, 0x03, 0xFF, 0x00, 0x00, 0x0F, 0xFC, 0x00, 0x00, 0x3F, 0xE0, 0x00,\n  0x00, 0x7F, 0x00, 0x00, 0x01, 0xFC, 0x00, 0x00, 0x07, 0xE0, 0x00, 0x00,\n  0x1F, 0x00, 0x00, 0x00, 0x7F, 0xF0, 0x3F, 0xFF, 0xFF, 0x83, 0xFF, 0xFF,\n  0xFC, 0x1F, 0xFF, 0xFF, 0xE0, 0xFF, 0xFF, 0xFE, 0x07, 0xFF, 0x1E, 0x00,\n  0x01, 0xE0, 0xF0, 0x7C, 0x1F, 0x0F, 0x87, 0xE0, 0xF0, 0x7C, 0x3F, 0x0F,\n  0x83, 0xE3, 0xF8, 0x7C, 0x1F, 0x1F, 0xE3, 0xC0, 0xF9, 0xFF, 0x3E, 0x07,\n  0xCF, 0xF9, 0xF0, 0x3E, 0xFF, 0xCF, 0x01, 0xF7, 0xBE, 0xF8, 0x0F, 0xFD,\n  0xF7, 0xC0, 0x7B, 0xCF, 0xFC, 0x03, 0xFE, 0x7F, 0xE0, 0x3F, 0xE3, 0xFF,\n  0x01, 0xFF, 0x0F, 0xF0, 0x0F, 0xF0, 0x7F, 0x80, 0x7F, 0x83, 0xFC, 0x03,\n  0xF8, 0x1F, 0xC0, 0x1F, 0xC0, 0xFE, 0x00, 0xFC, 0x07, 0xF0, 0x07, 0xE0,\n  0x3F, 0x00, 0x3E, 0x01, 0xF8, 0x00, 0x01, 0xFE, 0x03, 0xFE, 0x03, 0xFF,\n  0x07, 0xFF, 0x07, 0xFF, 0x07, 0xFF, 0x07, 0xFE, 0x07, 0xFE, 0x03, 0xFC,\n  0x03, 0xFC, 0x00, 0xFC, 0x03, 0xF0, 0x00, 0xFE, 0x07, 0xE0, 0x00, 0x7E,\n  0x1F, 0xC0, 0x00, 0x3F, 0x3F, 0x00, 0x00, 0x1F, 0xFE, 0x00, 0x00, 0x1F,\n  0xFC, 0x00, 0x00, 0x0F, 0xF8, 0x00, 0x00, 0x07, 0xF0, 0x00, 0x00, 0x07,\n  0xE0, 0x00, 0x00, 0x0F, 0xF0, 0x00, 0x00, 0x1F, 0xF8, 0x00, 0x00, 0x7F,\n  0xF8, 0x00, 0x00, 0xFC, 0xFC, 0x00, 0x01, 0xF8, 0x7E, 0x00, 0x03, 0xF0,\n  0x7E, 0x00, 0x07, 0xE0, 0x3F, 0x00, 0x0F, 0xC0, 0x1F, 0x80, 0x7F, 0xE0,\n  0x7F, 0xE0, 0xFF, 0xE0, 0xFF, 0xE0, 0xFF, 0xE0, 0xFF, 0xE0, 0xFF, 0xE0,\n  0xFF, 0xE0, 0x7F, 0xC0, 0xFF, 0xC0, 0x7F, 0xC0, 0x7F, 0xFF, 0xF0, 0x3F,\n  0xFF, 0xFC, 0x0F, 0xFF, 0xFF, 0x03, 0xFF, 0x7F, 0x80, 0xFF, 0x87, 0xC0,\n  0x1F, 0x01, 0xF8, 0x0F, 0x80, 0x3E, 0x07, 0xC0, 0x0F, 0xC3, 0xE0, 0x01,\n  0xF1, 0xF0, 0x00, 0x7E, 0xF8, 0x00, 0x0F, 0xFC, 0x00, 0x03, 0xFE, 0x00,\n  0x00, 0x7F, 0x80, 0x00, 0x1F, 0xC0, 0x00, 0x03, 0xE0, 0x00, 0x00, 0xF0,\n  0x00, 0x00, 0x7C, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x07, 0xC0, 0x00, 0x01,\n  0xE0, 0x00, 0x00, 0x78, 0x00, 0x07, 0xFF, 0xF0, 0x03, 0xFF, 0xFE, 0x00,\n  0xFF, 0xFF, 0x80, 0x3F, 0xFF, 0xC0, 0x0F, 0xFF, 0xE0, 0x00, 0x01, 0xFF,\n  0xFF, 0xC0, 0x3F, 0xFF, 0xF8, 0x07, 0xFF, 0xFF, 0x00, 0xFF, 0xFF, 0xE0,\n  0x3F, 0xFF, 0xFC, 0x07, 0xC0, 0x3F, 0x00, 0xF8, 0x0F, 0xC0, 0x1F, 0x03,\n  0xF0, 0x03, 0xC0, 0xFC, 0x00, 0xF8, 0x3F, 0x00, 0x0E, 0x0F, 0xC0, 0x00,\n  0x03, 0xF0, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x1F, 0x80,\n  0x00, 0x07, 0xE0, 0x00, 0x01, 0xF8, 0x0E, 0x00, 0x7E, 0x03, 0xE0, 0x1F,\n  0x80, 0x7C, 0x07, 0xE0, 0x0F, 0x01, 0xF8, 0x03, 0xE0, 0x7E, 0x00, 0x7C,\n  0x1F, 0xFF, 0xFF, 0x83, 0xFF, 0xFF, 0xF0, 0x7F, 0xFF, 0xFC, 0x0F, 0xFF,\n  0xFF, 0x81, 0xFF, 0xFF, 0xF0, 0x00, 0x00, 0xFF, 0xC0, 0x3F, 0xF0, 0x0F,\n  0xFC, 0x07, 0xFF, 0x01, 0xFF, 0x80, 0x7C, 0x00, 0x1E, 0x00, 0x07, 0x80,\n  0x03, 0xE0, 0x00, 0xF8, 0x00, 0x3E, 0x00, 0x0F, 0x00, 0x07, 0xC0, 0x01,\n  0xF0, 0x00, 0x7C, 0x00, 0x1F, 0x00, 0x07, 0x80, 0x03, 0xE0, 0x00, 0xF8,\n  0x00, 0x3E, 0x00, 0x0F, 0x00, 0x03, 0xC0, 0x01, 0xF0, 0x00, 0x7C, 0x00,\n  0x1F, 0x00, 0x07, 0x80, 0x01, 0xE0, 0x00, 0xF8, 0x00, 0x3E, 0x00, 0x0F,\n  0x80, 0x03, 0xC0, 0x01, 0xF0, 0x00, 0x7F, 0xE0, 0x1F, 0xF8, 0x07, 0xFE,\n  0x01, 0xFF, 0x80, 0xFF, 0xC0, 0x00, 0x20, 0x03, 0xC0, 0x3E, 0x01, 0xF0,\n  0x07, 0xC0, 0x3E, 0x01, 0xF0, 0x0F, 0x80, 0x3E, 0x01, 0xF0, 0x0F, 0x80,\n  0x7C, 0x01, 0xF0, 0x0F, 0x80, 0x7C, 0x03, 0xE0, 0x0F, 0x80, 0x7C, 0x03,\n  0xE0, 0x1F, 0x80, 0x7C, 0x03, 0xE0, 0x1F, 0x00, 0x7C, 0x03, 0xE0, 0x1F,\n  0x00, 0xF8, 0x03, 0xE0, 0x1F, 0x00, 0xF8, 0x07, 0xC0, 0x1F, 0x00, 0xF8,\n  0x07, 0xC0, 0x3E, 0x00, 0xF0, 0x07, 0x80, 0x38, 0x00, 0xFF, 0xC0, 0x7F,\n  0xE0, 0x1F, 0xF8, 0x07, 0xFE, 0x01, 0xFF, 0x80, 0x03, 0xE0, 0x00, 0xF0,\n  0x00, 0x7C, 0x00, 0x1F, 0x00, 0x07, 0xC0, 0x01, 0xE0, 0x00, 0x78, 0x00,\n  0x3E, 0x00, 0x0F, 0x80, 0x03, 0xE0, 0x00, 0xF0, 0x00, 0x3C, 0x00, 0x1F,\n  0x00, 0x07, 0xC0, 0x01, 0xF0, 0x00, 0x78, 0x00, 0x3E, 0x00, 0x0F, 0x80,\n  0x03, 0xE0, 0x00, 0xF8, 0x00, 0x3C, 0x00, 0x1F, 0x00, 0x07, 0xC0, 0x01,\n  0xF0, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x0F, 0x80, 0x7F, 0xE0, 0x3F, 0xF8,\n  0x0F, 0xFC, 0x03, 0xFF, 0x00, 0xFF, 0xC0, 0x00, 0x00, 0x08, 0x00, 0x01,\n  0xC0, 0x00, 0x3C, 0x00, 0x07, 0xE0, 0x00, 0xFE, 0x00, 0x1F, 0xF0, 0x03,\n  0xFF, 0x80, 0xFF, 0xF8, 0x1F, 0xCF, 0xC3, 0xF8, 0xFE, 0x7E, 0x07, 0xEF,\n  0xC0, 0x3F, 0xF8, 0x03, 0xFF, 0x00, 0x1F, 0xE0, 0x00, 0xE0, 0x7F, 0xFF,\n  0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xEF, 0xFF, 0xFF, 0xFF, 0x00, 0x60, 0xF0, 0xF8, 0x7C, 0x3E, 0x1F, 0x0F,\n  0x06, 0x00, 0x3F, 0xE0, 0x03, 0xFF, 0xF8, 0x07, 0xFF, 0xFC, 0x07, 0xFF,\n  0xFE, 0x07, 0xFF, 0xFE, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x3E, 0x00, 0x00,\n  0x3E, 0x00, 0x7F, 0xFE, 0x03, 0xFF, 0xFC, 0x0F, 0xFF, 0xFC, 0x1F, 0xFF,\n  0xFC, 0x3F, 0xFF, 0xFC, 0x7F, 0x00, 0x78, 0x7C, 0x00, 0x78, 0xF8, 0x00,\n  0xF8, 0xF8, 0x03, 0xF8, 0xFC, 0x0F, 0xFE, 0xFF, 0xFF, 0xFF, 0x7F, 0xFF,\n  0xFF, 0x7F, 0xFF, 0xFF, 0x3F, 0xFD, 0xFE, 0x0F, 0xE0, 0x00, 0x03, 0xFC,\n  0x00, 0x00, 0x3F, 0xE0, 0x00, 0x01, 0xFF, 0x00, 0x00, 0x0F, 0xF0, 0x00,\n  0x00, 0x3F, 0x80, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x03, 0xE0, 0x00, 0x00,\n  0x1F, 0x00, 0x00, 0x00, 0xF0, 0xFE, 0x00, 0x0F, 0xBF, 0xFC, 0x00, 0x7F,\n  0xFF, 0xF8, 0x03, 0xFF, 0xFF, 0xC0, 0x1F, 0xFF, 0xFF, 0x00, 0xFF, 0x03,\n  0xF8, 0x0F, 0xE0, 0x07, 0xE0, 0x7E, 0x00, 0x3F, 0x03, 0xE0, 0x00, 0xF8,\n  0x1F, 0x00, 0x07, 0xC0, 0xF0, 0x00, 0x3E, 0x0F, 0x80, 0x01, 0xF0, 0x7C,\n  0x00, 0x1F, 0x03, 0xE0, 0x00, 0xF8, 0x1F, 0x00, 0x0F, 0xC0, 0xFC, 0x00,\n  0x7C, 0x0F, 0xE0, 0x07, 0xE3, 0xFF, 0xC0, 0xFE, 0x3F, 0xFF, 0xFF, 0xE1,\n  0xFF, 0xFF, 0xFE, 0x0F, 0xFF, 0xFF, 0xE0, 0x7F, 0x9F, 0xFC, 0x00, 0x00,\n  0x3F, 0x80, 0x00, 0x00, 0x1F, 0xE3, 0x80, 0x7F, 0xFF, 0xC0, 0x7F, 0xFF,\n  0xE0, 0xFF, 0xFF, 0xF0, 0xFF, 0xFF, 0xF8, 0xFF, 0x01, 0xFC, 0x7E, 0x00,\n  0x7C, 0x7E, 0x00, 0x3E, 0x3E, 0x00, 0x0E, 0x3E, 0x00, 0x00, 0x1F, 0x00,\n  0x00, 0x1F, 0x00, 0x00, 0x0F, 0x80, 0x00, 0x07, 0xC0, 0x00, 0x03, 0xE0,\n  0x00, 0x01, 0xF0, 0x00, 0x00, 0xFC, 0x00, 0x0C, 0x7F, 0x80, 0x3F, 0x1F,\n  0xFF, 0xFF, 0x8F, 0xFF, 0xFF, 0x83, 0xFF, 0xFF, 0x80, 0x7F, 0xFF, 0x00,\n  0x0F, 0xFC, 0x00, 0x00, 0x00, 0x0F, 0xF0, 0x00, 0x01, 0xFE, 0x00, 0x00,\n  0x1F, 0xE0, 0x00, 0x01, 0xFE, 0x00, 0x00, 0x1F, 0xE0, 0x00, 0x00, 0x3E,\n  0x00, 0x00, 0x03, 0xC0, 0x00, 0x00, 0x7C, 0x00, 0x3F, 0x87, 0xC0, 0x0F,\n  0xFF, 0x7C, 0x03, 0xFF, 0xFF, 0xC0, 0x7F, 0xFF, 0xF8, 0x0F, 0xFF, 0xFF,\n  0x81, 0xFC, 0x0F, 0xF8, 0x3F, 0x00, 0x3F, 0x83, 0xE0, 0x01, 0xF0, 0x7C,\n  0x00, 0x1F, 0x07, 0xC0, 0x01, 0xF0, 0xF8, 0x00, 0x1F, 0x0F, 0x80, 0x01,\n  0xF0, 0xF8, 0x00, 0x1E, 0x0F, 0x80, 0x03, 0xE0, 0xF8, 0x00, 0x3E, 0x0F,\n  0xC0, 0x07, 0xE0, 0xFC, 0x00, 0xFE, 0x07, 0xF0, 0x3F, 0xF8, 0x7F, 0xFF,\n  0xFF, 0xC3, 0xFF, 0xFF, 0xFC, 0x3F, 0xFF, 0xFF, 0xC0, 0xFF, 0xE7, 0xF8,\n  0x03, 0xF8, 0x00, 0x00, 0x00, 0x1F, 0xC0, 0x00, 0xFF, 0xF0, 0x03, 0xFF,\n  0xF8, 0x07, 0xFF, 0xFC, 0x0F, 0xFF, 0xFE, 0x1F, 0xE0, 0x7E, 0x3F, 0x80,\n  0x1F, 0x3F, 0x00, 0x0F, 0x7E, 0x00, 0x0F, 0x7F, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF8, 0x00,\n  0x00, 0xFC, 0x00, 0x00, 0xFC, 0x00, 0x1C, 0x7F, 0x01, 0xFE, 0x7F, 0xFF,\n  0xFE, 0x3F, 0xFF, 0xFE, 0x1F, 0xFF, 0xFC, 0x0F, 0xFF, 0xF0, 0x03, 0xFF,\n  0x00, 0x00, 0x00, 0x7F, 0xC0, 0x00, 0x3F, 0xFF, 0x00, 0x07, 0xFF, 0xF0,\n  0x00, 0xFF, 0xFF, 0x00, 0x1F, 0xFF, 0xE0, 0x01, 0xF0, 0x00, 0x00, 0x3E,\n  0x00, 0x00, 0x03, 0xE0, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x7F, 0xFF, 0xF0,\n  0x0F, 0xFF, 0xFF, 0x00, 0xFF, 0xFF, 0xF0, 0x0F, 0xFF, 0xFF, 0x00, 0xFF,\n  0xFF, 0xE0, 0x00, 0x78, 0x00, 0x00, 0x0F, 0x80, 0x00, 0x00, 0xF8, 0x00,\n  0x00, 0x0F, 0x80, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x01,\n  0xF0, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x01, 0xF0, 0x00, 0x00, 0x1E, 0x00,\n  0x00, 0x03, 0xE0, 0x00, 0x07, 0xFF, 0xFF, 0x00, 0xFF, 0xFF, 0xF0, 0x0F,\n  0xFF, 0xFF, 0x00, 0xFF, 0xFF, 0xF0, 0x07, 0xFF, 0xFE, 0x00, 0x00, 0x3F,\n  0x80, 0x00, 0x0F, 0xFE, 0xFF, 0x03, 0xFF, 0xFF, 0xF0, 0x7F, 0xFF, 0xFF,\n  0x0F, 0xFF, 0xFF, 0xF1, 0xFC, 0x1F, 0xFE, 0x3F, 0x80, 0x7F, 0x03, 0xE0,\n  0x03, 0xF0, 0x7E, 0x00, 0x3E, 0x07, 0xC0, 0x03, 0xE0, 0xF8, 0x00, 0x3E,\n  0x0F, 0x80, 0x03, 0xE0, 0xF8, 0x00, 0x3E, 0x0F, 0x80, 0x03, 0xC0, 0xF8,\n  0x00, 0x7C, 0x0F, 0xC0, 0x0F, 0xC0, 0xFC, 0x01, 0xFC, 0x07, 0xF0, 0x7F,\n  0x80, 0x7F, 0xFF, 0xF8, 0x03, 0xFF, 0xFF, 0x80, 0x3F, 0xFF, 0xF8, 0x00,\n  0xFF, 0xEF, 0x80, 0x03, 0xF0, 0xF0, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x01,\n  0xF0, 0x00, 0x00, 0x7E, 0x00, 0x1F, 0xFF, 0xE0, 0x03, 0xFF, 0xFC, 0x00,\n  0x3F, 0xFF, 0x80, 0x03, 0xFF, 0xE0, 0x00, 0x3F, 0xF8, 0x00, 0x00, 0x03,\n  0xF8, 0x00, 0x01, 0xFE, 0x00, 0x00, 0xFF, 0x80, 0x00, 0x3F, 0xE0, 0x00,\n  0x07, 0xF0, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x07, 0xC0,\n  0x00, 0x01, 0xF1, 0xF8, 0x00, 0x79, 0xFF, 0x80, 0x1E, 0xFF, 0xF0, 0x0F,\n  0xFF, 0xFC, 0x03, 0xFF, 0xFF, 0x80, 0xFF, 0x07, 0xE0, 0x3F, 0x00, 0xF8,\n  0x1F, 0x80, 0x3E, 0x07, 0xC0, 0x0F, 0x81, 0xF0, 0x03, 0xC0, 0x7C, 0x00,\n  0xF0, 0x1E, 0x00, 0x7C, 0x0F, 0x80, 0x1F, 0x03, 0xE0, 0x07, 0xC0, 0xF8,\n  0x01, 0xE0, 0x3C, 0x00, 0xF8, 0x0F, 0x00, 0x3E, 0x1F, 0xF8, 0x3F, 0xEF,\n  0xFE, 0x1F, 0xFF, 0xFF, 0x87, 0xFF, 0xFF, 0xE1, 0xFF, 0xFF, 0xF0, 0x3F,\n  0xE0, 0x00, 0x07, 0xE0, 0x00, 0x0F, 0xC0, 0x00, 0x1F, 0x80, 0x00, 0x3E,\n  0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n  0x01, 0xFF, 0xC0, 0x07, 0xFF, 0x80, 0x0F, 0xFE, 0x00, 0x1F, 0xFC, 0x00,\n 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0x00, 0x0F, 0x80, 0x00,\n  0x1F, 0x00, 0x00, 0x3E, 0x00, 0x7F, 0xFF, 0xF9, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xCF, 0xFF, 0xFF, 0x00, 0x00, 0x07, 0x81, 0xE0,\n  0x3F, 0xBF, 0x9F, 0xE1, 0xFF, 0xFE, 0xFF, 0x87, 0xFF, 0xFF, 0xFF, 0x1F,\n  0xFF, 0xFF, 0xFC, 0x7F, 0xC7, 0xF1, 0xF0, 0x7E, 0x1F, 0x87, 0xC1, 0xF0,\n  0x7C, 0x1F, 0x07, 0x81, 0xE0, 0x7C, 0x1E, 0x0F, 0x81, 0xE0, 0xF8, 0x3E,\n  0x0F, 0x83, 0xE0, 0xF8, 0x3E, 0x0F, 0x83, 0xE0, 0xF8, 0x3C, 0x0F, 0x03,\n  0xC1, 0xF0, 0x7C, 0x0F, 0x07, 0xC1, 0xF0, 0x7C, 0x1F, 0x07, 0xC1, 0xF1,\n  0xFE, 0x1F, 0x87, 0xEF, 0xFC, 0x7F, 0x1F, 0xFF, 0xF3, 0xFC, 0x7F, 0xFF,\n  0xCF, 0xF3, 0xFF, 0xFE, 0x3F, 0x8F, 0xE0, 0x00, 0x01, 0xF8, 0x01, 0xF9,\n  0xFF, 0x80, 0xFE, 0xFF, 0xF0, 0x7F, 0xFF, 0xFC, 0x1F, 0xFF, 0xFF, 0x83,\n  0xFF, 0x07, 0xE0, 0x3F, 0x00, 0xF8, 0x1F, 0x80, 0x3E, 0x07, 0xC0, 0x0F,\n  0x81, 0xF0, 0x03, 0xC0, 0x7C, 0x00, 0xF0, 0x1E, 0x00, 0x7C, 0x0F, 0x80,\n  0x1F, 0x03, 0xE0, 0x07, 0xC0, 0xF8, 0x01, 0xE0, 0x3C, 0x00, 0xF8, 0x0F,\n  0x00, 0x3E, 0x1F, 0xF8, 0x3F, 0xEF, 0xFE, 0x1F, 0xFF, 0xFF, 0x87, 0xFF,\n  0xFF, 0xE1, 0xFF, 0xFF, 0xF0, 0x3F, 0xE0, 0x00, 0x1F, 0xC0, 0x00, 0x7F,\n  0xFC, 0x00, 0x7F, 0xFF, 0x00, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xF0, 0xFF,\n  0x03, 0xF8, 0xFE, 0x00, 0xFE, 0x7C, 0x00, 0x3F, 0x7C, 0x00, 0x0F, 0xBE,\n  0x00, 0x07, 0xFE, 0x00, 0x03, 0xFF, 0x00, 0x01, 0xFF, 0x80, 0x00, 0xFF,\n  0xC0, 0x00, 0xFB, 0xE0, 0x00, 0xFD, 0xF8, 0x00, 0x7C, 0xFE, 0x00, 0xFE,\n  0x3F, 0x81, 0xFE, 0x1F, 0xFF, 0xFE, 0x07, 0xFF, 0xFE, 0x01, 0xFF, 0xFC,\n  0x00, 0x7F, 0xFC, 0x00, 0x07, 0xF0, 0x00, 0x00, 0x00, 0x3F, 0x80, 0x07,\n  0xF9, 0xFF, 0xC0, 0x1F, 0xF7, 0xFF, 0xC0, 0x3F, 0xFF, 0xFF, 0xC0, 0x7F,\n  0xFF, 0xFF, 0xC0, 0x7F, 0xF0, 0x3F, 0x80, 0x3F, 0x80, 0x1F, 0x80, 0x7E,\n  0x00, 0x3F, 0x00, 0xF8, 0x00, 0x3E, 0x01, 0xF0, 0x00, 0x7C, 0x03, 0xC0,\n  0x00, 0xF8, 0x0F, 0x80, 0x01, 0xF0, 0x1F, 0x00, 0x07, 0xE0, 0x3E, 0x00,\n  0x0F, 0x80, 0x7C, 0x00, 0x3F, 0x01, 0xFC, 0x00, 0xFC, 0x03, 0xFE, 0x07,\n  0xF8, 0x07, 0xFF, 0xFF, 0xE0, 0x0F, 0xFF, 0xFF, 0x80, 0x1E, 0xFF, 0xFC,\n  0x00, 0x7C, 0xFF, 0xF0, 0x00, 0xF8, 0x7F, 0x00, 0x01, 0xF0, 0x00, 0x00,\n  0x03, 0xE0, 0x00, 0x00, 0x07, 0x80, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x01,\n  0xFF, 0xF0, 0x00, 0x07, 0xFF, 0xE0, 0x00, 0x0F, 0xFF, 0xC0, 0x00, 0x1F,\n  0xFF, 0x80, 0x00, 0x3F, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x3F, 0x80, 0x00,\n  0x07, 0xFF, 0x3F, 0xC0, 0xFF, 0xFD, 0xFE, 0x0F, 0xFF, 0xFF, 0xF0, 0xFF,\n  0xFF, 0xFF, 0x8F, 0xE0, 0x7F, 0xF8, 0xFC, 0x00, 0xFE, 0x07, 0xC0, 0x03,\n  0xE0, 0x7C, 0x00, 0x1F, 0x03, 0xE0, 0x00, 0xF8, 0x1E, 0x00, 0x07, 0xC1,\n  0xF0, 0x00, 0x3E, 0x0F, 0x80, 0x01, 0xE0, 0x7C, 0x00, 0x1F, 0x03, 0xF0,\n  0x01, 0xF8, 0x1F, 0x80, 0x1F, 0xC0, 0xFF, 0x03, 0xFC, 0x03, 0xFF, 0xFF,\n  0xE0, 0x1F, 0xFF, 0xFF, 0x00, 0x7F, 0xFF, 0xF8, 0x00, 0xFF, 0xE7, 0xC0,\n  0x01, 0xFC, 0x3C, 0x00, 0x00, 0x01, 0xE0, 0x00, 0x00, 0x1F, 0x00, 0x00,\n  0x00, 0xF8, 0x00, 0x00, 0x07, 0xC0, 0x00, 0x07, 0xFF, 0x80, 0x00, 0x7F,\n  0xFE, 0x00, 0x07, 0xFF, 0xF0, 0x00, 0x3F, 0xFF, 0x00, 0x00, 0xFF, 0xF0,\n  0x00, 0x00, 0x00, 0x0F, 0x80, 0x3F, 0xC3, 0xFE, 0x07, 0xFC, 0xFF, 0xE0,\n  0x7F, 0xDF, 0xFF, 0x07, 0xFF, 0xFF, 0xE0, 0x7F, 0xFF, 0x1C, 0x00, 0x7F,\n  0xC0, 0x00, 0x07, 0xF0, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x0F, 0xC0, 0x00,\n  0x00, 0xF8, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x01, 0xF0, 0x00, 0x00, 0x1F,\n  0x00, 0x00, 0x01, 0xF0, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x01, 0xE0, 0x00,\n  0x07, 0xFF, 0xFF, 0x00, 0xFF, 0xFF, 0xF0, 0x0F, 0xFF, 0xFF, 0x00, 0xFF,\n  0xFF, 0xF0, 0x07, 0xFF, 0xFE, 0x00, 0x00, 0x3F, 0xCE, 0x03, 0xFF, 0xFC,\n  0x0F, 0xFF, 0xF8, 0x3F, 0xFF, 0xF0, 0xFF, 0xFF, 0xC3, 0xF8, 0x0F, 0x87,\n  0xC0, 0x0E, 0x0F, 0x80, 0x00, 0x1F, 0xF0, 0x00, 0x3F, 0xFF, 0x80, 0x3F,\n  0xFF, 0xC0, 0x3F, 0xFF, 0xC0, 0x1F, 0xFF, 0xC0, 0x01, 0xFF, 0x80, 0x00,\n  0x3F, 0x1C, 0x00, 0x3E, 0x7C, 0x00, 0x7C, 0xFC, 0x03, 0xF3, 0xFF, 0xFF,\n  0xE7, 0xFF, 0xFF, 0x8F, 0xFF, 0xFE, 0x1F, 0xFF, 0xF0, 0x00, 0xFF, 0x00,\n  0x00, 0x03, 0xC0, 0x00, 0x7C, 0x00, 0x07, 0xC0, 0x00, 0x7C, 0x00, 0x07,\n  0x80, 0x00, 0x78, 0x00, 0x7F, 0xFF, 0xEF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xE1, 0xF0, 0x00, 0x1F, 0x00, 0x01, 0xE0, 0x00,\n  0x1E, 0x00, 0x03, 0xE0, 0x00, 0x3E, 0x00, 0x03, 0xE0, 0x00, 0x3C, 0x00,\n  0x07, 0xC0, 0x00, 0x7C, 0x00, 0x07, 0xC0, 0x00, 0x7E, 0x00, 0xF7, 0xFF,\n  0xFF, 0x7F, 0xFF, 0xF3, 0xFF, 0xFE, 0x1F, 0xFF, 0x80, 0x7F, 0x80, 0x7F,\n  0x01, 0xFF, 0xFE, 0x07, 0xFF, 0xF8, 0x1F, 0xFF, 0xF0, 0x3F, 0xFF, 0xE0,\n  0x3F, 0xC7, 0xC0, 0x07, 0x8F, 0x80, 0x1F, 0x3E, 0x00, 0x3E, 0x7C, 0x00,\n  0x7C, 0xF8, 0x00, 0xF1, 0xF0, 0x03, 0xE3, 0xE0, 0x07, 0xC7, 0xC0, 0x0F,\n  0x8F, 0x80, 0x1F, 0x1F, 0x00, 0x7C, 0x3E, 0x01, 0xF8, 0x7E, 0x0F, 0xFC,\n  0xFF, 0xFF, 0xF8, 0xFF, 0xFF, 0xF1, 0xFF, 0xEF, 0xE1, 0xFF, 0xBF, 0x80,\n  0xFC, 0x00, 0x00, 0x7F, 0xF0, 0x7F, 0xFF, 0xFF, 0x0F, 0xFF, 0xFF, 0xF0,\n  0xFF, 0xFF, 0xFF, 0x0F, 0xFF, 0xFF, 0xE0, 0xFF, 0xE1, 0xF8, 0x03, 0xE0,\n  0x0F, 0x80, 0x3E, 0x00, 0xF8, 0x07, 0xC0, 0x0F, 0x80, 0xF8, 0x00, 0xFC,\n  0x1F, 0x80, 0x07, 0xC1, 0xF0, 0x00, 0x7C, 0x3E, 0x00, 0x07, 0xE7, 0xE0,\n  0x00, 0x3E, 0x7C, 0x00, 0x03, 0xEF, 0x80, 0x00, 0x3F, 0xF0, 0x00, 0x03,\n  0xFF, 0x00, 0x00, 0x1F, 0xE0, 0x00, 0x01, 0xFC, 0x00, 0x00, 0x1F, 0xC0,\n  0x00, 0x00, 0xF8, 0x00, 0x00, 0x7F, 0xC0, 0x1F, 0xEF, 0xFC, 0x03, 0xFF,\n  0xFF, 0xC0, 0x7F, 0xFF, 0xFC, 0x07, 0xFE, 0x7F, 0x80, 0x3F, 0xC3, 0xE1,\n  0xF0, 0xF8, 0x3E, 0x3F, 0x0F, 0x03, 0xE3, 0xF1, 0xF0, 0x3E, 0x7F, 0x1E,\n  0x03, 0xE7, 0xF3, 0xE0, 0x3E, 0xFF, 0xBC, 0x03, 0xFF, 0xFF, 0xC0, 0x3F,\n  0xFF, 0xFC, 0x03, 0xFE, 0xFF, 0x80, 0x3F, 0xEF, 0xF8, 0x03, 0xFC, 0xFF,\n  0x00, 0x3F, 0x8F, 0xF0, 0x03, 0xF8, 0x7E, 0x00, 0x3F, 0x07, 0xE0, 0x01,\n  0xF0, 0x7C, 0x00, 0x1E, 0x07, 0xC0, 0x00, 0x03, 0xFE, 0x0F, 0xF8, 0x3F,\n  0xF0, 0xFF, 0xC1, 0xFF, 0x8F, 0xFE, 0x0F, 0xFC, 0x7F, 0xF0, 0x7F, 0xC1,\n  0xFF, 0x00, 0xFE, 0x1F, 0xC0, 0x03, 0xF9, 0xFC, 0x00, 0x0F, 0xFF, 0xC0,\n  0x00, 0x3F, 0xF8, 0x00, 0x00, 0xFF, 0x80, 0x00, 0x07, 0xF8, 0x00, 0x00,\n  0x7F, 0xE0, 0x00, 0x0F, 0xFF, 0x80, 0x00, 0xFE, 0xFE, 0x00, 0x0F, 0xE3,\n  0xF8, 0x00, 0xFE, 0x0F, 0xE0, 0x3F, 0xE0, 0x7F, 0xC3, 0xFF, 0x87, 0xFF,\n  0x3F, 0xFC, 0x7F, 0xF9, 0xFF, 0xE3, 0xFF, 0x87, 0xFE, 0x0F, 0xF8, 0x00,\n  0x01, 0xFE, 0x03, 0xFE, 0x03, 0xFF, 0x07, 0xFF, 0x07, 0xFF, 0x07, 0xFF,\n  0x07, 0xFF, 0x07, 0xFE, 0x03, 0xFC, 0x03, 0xFC, 0x01, 0xF8, 0x01, 0xF0,\n  0x00, 0xF8, 0x03, 0xF0, 0x00, 0xF8, 0x03, 0xE0, 0x00, 0xFC, 0x07, 0xC0,\n  0x00, 0x7C, 0x0F, 0x80, 0x00, 0x7C, 0x0F, 0x80, 0x00, 0x7E, 0x1F, 0x00,\n  0x00, 0x7E, 0x3E, 0x00, 0x00, 0x3E, 0x7C, 0x00, 0x00, 0x3E, 0x7C, 0x00,\n  0x00, 0x3F, 0xF8, 0x00, 0x00, 0x1F, 0xF0, 0x00, 0x00, 0x1F, 0xE0, 0x00,\n  0x00, 0x1F, 0xC0, 0x00, 0x00, 0x0F, 0xC0, 0x00, 0x00, 0x0F, 0x80, 0x00,\n  0x00, 0x1F, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00,\n  0x00, 0x7C, 0x00, 0x00, 0x7F, 0xFF, 0x00, 0x00, 0xFF, 0xFF, 0x00, 0x00,\n  0xFF, 0xFF, 0x00, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x7F, 0xFE, 0x00, 0x00,\n  0x07, 0xFF, 0xFF, 0x83, 0xFF, 0xFF, 0x81, 0xFF, 0xFF, 0xC1, 0xFF, 0xFF,\n  0xE0, 0xFF, 0xFF, 0xE0, 0x7C, 0x0F, 0xE0, 0x3C, 0x0F, 0xE0, 0x1E, 0x0F,\n  0xC0, 0x00, 0x1F, 0xC0, 0x00, 0x1F, 0xC0, 0x00, 0x1F, 0xC0, 0x00, 0x1F,\n  0x80, 0x00, 0x3F, 0x80, 0x00, 0x3F, 0x80, 0x00, 0x3F, 0x80, 0xF0, 0x3F,\n  0x00, 0xF8, 0x3F, 0xFF, 0xFC, 0x3F, 0xFF, 0xFE, 0x1F, 0xFF, 0xFE, 0x0F,\n  0xFF, 0xFF, 0x0F, 0xFF, 0xFF, 0x80, 0x00, 0x0F, 0x00, 0x1F, 0xC0, 0x1F,\n  0xE0, 0x1F, 0xF0, 0x0F, 0xE0, 0x0F, 0xC0, 0x07, 0xC0, 0x07, 0xC0, 0x03,\n  0xE0, 0x01, 0xF0, 0x00, 0xF8, 0x00, 0x78, 0x00, 0x7C, 0x00, 0x3E, 0x00,\n  0x1F, 0x00, 0x1F, 0x00, 0x0F, 0x80, 0x3F, 0x80, 0x3F, 0xC0, 0x1F, 0xC0,\n  0x0F, 0xE0, 0x07, 0xF8, 0x00, 0xFC, 0x00, 0x3E, 0x00, 0x1F, 0x00, 0x0F,\n  0x80, 0x07, 0x80, 0x07, 0xC0, 0x03, 0xE0, 0x01, 0xF0, 0x00, 0xF8, 0x00,\n  0x7E, 0x00, 0x3F, 0x80, 0x1F, 0xE0, 0x07, 0xF0, 0x03, 0xF8, 0x00, 0x78,\n  0x00, 0x01, 0xE0, 0x3C, 0x0F, 0x81, 0xF0, 0x3E, 0x07, 0x80, 0xF0, 0x3E,\n  0x07, 0xC0, 0xF0, 0x1E, 0x03, 0xC0, 0xF8, 0x1F, 0x03, 0xC0, 0x78, 0x0F,\n  0x03, 0xE0, 0x7C, 0x0F, 0x01, 0xE0, 0x3C, 0x0F, 0x81, 0xF0, 0x3C, 0x07,\n  0x80, 0xF0, 0x3E, 0x07, 0xC0, 0xF0, 0x1E, 0x07, 0xC0, 0xF8, 0x1F, 0x03,\n  0xC0, 0x70, 0x00, 0x00, 0xF0, 0x00, 0xFC, 0x00, 0x7F, 0x00, 0x3F, 0xC0,\n  0x0F, 0xE0, 0x03, 0xF0, 0x00, 0xF8, 0x00, 0x7C, 0x00, 0x3E, 0x00, 0x1F,\n  0x00, 0x0F, 0x80, 0x07, 0x80, 0x03, 0xC0, 0x03, 0xE0, 0x01, 0xF0, 0x00,\n  0xF8, 0x00, 0x7E, 0x00, 0x3F, 0xC0, 0x0F, 0xE0, 0x07, 0xF0, 0x07, 0xF8,\n  0x07, 0xF8, 0x03, 0xE0, 0x03, 0xE0, 0x01, 0xF0, 0x00, 0xF0, 0x00, 0x78,\n  0x00, 0x7C, 0x00, 0x3E, 0x00, 0x1F, 0x00, 0x0F, 0x00, 0x1F, 0x80, 0x7F,\n  0xC0, 0x7F, 0xC0, 0x3F, 0xC0, 0x1F, 0xC0, 0x07, 0x80, 0x00, 0x03, 0xE0,\n  0x00, 0x1F, 0xE0, 0x00, 0x7F, 0xE0, 0x39, 0xFF, 0xE0, 0xF7, 0xFF, 0xE7,\n  0xFF, 0xCF, 0xFF, 0xFE, 0x0F, 0xFF, 0x38, 0x0F, 0xFC, 0x00, 0x0F, 0xE0,\n  0x00, 0x0F, 0x80 };\n\nconst GFXglyph FreeMonoBoldOblique24pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,  28,    0,    1 },   // 0x20 ' '\n  {     0,  12,  31,  28,   12,  -29 },   // 0x21 '!'\n  {    47,  17,  14,  28,   11,  -28 },   // 0x22 '\"'\n  {    77,  24,  34,  28,    5,  -30 },   // 0x23 '#'\n  {   179,  25,  38,  28,    4,  -31 },   // 0x24 '$'\n  {   298,  22,  30,  28,    6,  -28 },   // 0x25 '%'\n  {   381,  21,  28,  28,    5,  -26 },   // 0x26 '&'\n  {   455,   7,  14,  28,   16,  -28 },   // 0x27 '''\n  {   468,  14,  37,  28,   14,  -29 },   // 0x28 '('\n  {   533,  14,  37,  28,    5,  -29 },   // 0x29 ')'\n  {   598,  21,  19,  28,    8,  -28 },   // 0x2A '*'\n  {   648,  24,  26,  28,    5,  -25 },   // 0x2B '+'\n  {   726,  12,  14,  28,    6,   -6 },   // 0x2C ','\n  {   747,  24,   5,  28,    5,  -15 },   // 0x2D '-'\n  {   762,   7,   6,  28,   11,   -4 },   // 0x2E '.'\n  {   768,  28,  38,  28,    3,  -32 },   // 0x2F '/'\n  {   901,  23,  31,  28,    6,  -29 },   // 0x30 '0'\n  {   991,  21,  30,  28,    4,  -29 },   // 0x31 '1'\n  {  1070,  26,  30,  28,    3,  -29 },   // 0x32 '2'\n  {  1168,  25,  31,  28,    4,  -29 },   // 0x33 '3'\n  {  1265,  22,  28,  28,    5,  -27 },   // 0x34 '4'\n  {  1342,  25,  31,  28,    4,  -29 },   // 0x35 '5'\n  {  1439,  24,  31,  28,    7,  -29 },   // 0x36 '6'\n  {  1532,  22,  30,  28,    9,  -29 },   // 0x37 '7'\n  {  1615,  23,  31,  28,    6,  -29 },   // 0x38 '8'\n  {  1705,  24,  31,  28,    5,  -29 },   // 0x39 '9'\n  {  1798,  10,  22,  28,   11,  -20 },   // 0x3A ':'\n  {  1826,  15,  28,  28,    5,  -20 },   // 0x3B ';'\n  {  1879,  25,  21,  28,    5,  -23 },   // 0x3C '<'\n  {  1945,  26,  14,  28,    4,  -19 },   // 0x3D '='\n  {  1991,  25,  22,  28,    4,  -23 },   // 0x3E '>'\n  {  2060,  19,  29,  28,   10,  -27 },   // 0x3F '?'\n  {  2129,  23,  36,  28,    5,  -28 },   // 0x40 '@'\n  {  2233,  30,  27,  28,    0,  -26 },   // 0x41 'A'\n  {  2335,  29,  27,  28,    1,  -26 },   // 0x42 'B'\n  {  2433,  28,  29,  28,    3,  -27 },   // 0x43 'C'\n  {  2535,  28,  27,  28,    1,  -26 },   // 0x44 'D'\n  {  2630,  29,  27,  28,    1,  -26 },   // 0x45 'E'\n  {  2728,  31,  27,  28,    0,  -26 },   // 0x46 'F'\n  {  2833,  28,  29,  28,    3,  -27 },   // 0x47 'G'\n  {  2935,  30,  27,  28,    1,  -26 },   // 0x48 'H'\n  {  3037,  25,  27,  28,    3,  -26 },   // 0x49 'I'\n  {  3122,  31,  28,  28,    0,  -26 },   // 0x4A 'J'\n  {  3231,  31,  27,  28,    0,  -26 },   // 0x4B 'K'\n  {  3336,  27,  27,  28,    1,  -26 },   // 0x4C 'L'\n  {  3428,  34,  27,  28,    0,  -26 },   // 0x4D 'M'\n  {  3543,  32,  27,  28,    1,  -26 },   // 0x4E 'N'\n  {  3651,  27,  29,  28,    3,  -27 },   // 0x4F 'O'\n  {  3749,  28,  27,  28,    1,  -26 },   // 0x50 'P'\n  {  3844,  27,  35,  28,    3,  -27 },   // 0x51 'Q'\n  {  3963,  29,  27,  28,    0,  -26 },   // 0x52 'R'\n  {  4061,  26,  29,  28,    3,  -27 },   // 0x53 'S'\n  {  4156,  26,  27,  28,    4,  -26 },   // 0x54 'T'\n  {  4244,  28,  28,  28,    4,  -26 },   // 0x55 'U'\n  {  4342,  30,  27,  28,    2,  -26 },   // 0x56 'V'\n  {  4444,  29,  27,  28,    3,  -26 },   // 0x57 'W'\n  {  4542,  32,  27,  28,    0,  -26 },   // 0x58 'X'\n  {  4650,  26,  27,  28,    4,  -26 },   // 0x59 'Y'\n  {  4738,  27,  27,  28,    2,  -26 },   // 0x5A 'Z'\n  {  4830,  18,  37,  28,   10,  -29 },   // 0x5B '['\n  {  4914,  13,  38,  28,   10,  -32 },   // 0x5C '\\'\n  {  4976,  18,  37,  28,    5,  -29 },   // 0x5D ']'\n  {  5060,  20,  15,  28,    8,  -29 },   // 0x5E '^'\n  {  5098,  29,   5,  28,   -2,    5 },   // 0x5F '_'\n  {  5117,   8,   8,  28,   13,  -30 },   // 0x60 '`'\n  {  5125,  24,  23,  28,    3,  -21 },   // 0x61 'a'\n  {  5194,  29,  31,  28,    0,  -29 },   // 0x62 'b'\n  {  5307,  25,  23,  28,    3,  -21 },   // 0x63 'c'\n  {  5379,  28,  31,  28,    3,  -29 },   // 0x64 'd'\n  {  5488,  24,  23,  28,    3,  -21 },   // 0x65 'e'\n  {  5557,  28,  30,  28,    4,  -29 },   // 0x66 'f'\n  {  5662,  28,  31,  28,    3,  -21 },   // 0x67 'g'\n  {  5771,  26,  30,  28,    2,  -29 },   // 0x68 'h'\n  {  5869,  23,  29,  28,    3,  -28 },   // 0x69 'i'\n  {  5953,  23,  38,  28,    3,  -28 },   // 0x6A 'j'\n  {  6063,  26,  30,  28,    2,  -29 },   // 0x6B 'k'\n  {  6161,  23,  30,  28,    3,  -29 },   // 0x6C 'l'\n  {  6248,  30,  22,  28,    0,  -21 },   // 0x6D 'm'\n  {  6331,  26,  22,  28,    2,  -21 },   // 0x6E 'n'\n  {  6403,  25,  23,  28,    3,  -21 },   // 0x6F 'o'\n  {  6475,  31,  31,  28,   -1,  -21 },   // 0x70 'p'\n  {  6596,  29,  31,  28,    2,  -21 },   // 0x71 'q'\n  {  6709,  28,  22,  28,    2,  -21 },   // 0x72 'r'\n  {  6786,  23,  23,  28,    4,  -21 },   // 0x73 's'\n  {  6853,  20,  28,  28,    5,  -26 },   // 0x74 't'\n  {  6923,  23,  22,  28,    5,  -20 },   // 0x75 'u'\n  {  6987,  28,  21,  28,    3,  -20 },   // 0x76 'v'\n  {  7061,  28,  21,  28,    3,  -20 },   // 0x77 'w'\n  {  7135,  29,  21,  28,    1,  -20 },   // 0x78 'x'\n  {  7212,  32,  30,  28,   -1,  -20 },   // 0x79 'y'\n  {  7332,  25,  21,  28,    4,  -20 },   // 0x7A 'z'\n  {  7398,  17,  37,  28,   10,  -29 },   // 0x7B '{'\n  {  7477,  11,  36,  28,   11,  -28 },   // 0x7C '|'\n  {  7527,  17,  37,  28,    6,  -29 },   // 0x7D '}'\n  {  7606,  23,  10,  28,    5,  -17 } }; // 0x7E '~'\n\nconst GFXfont FreeMonoBoldOblique24pt7b PROGMEM = {\n  (uint8_t  *)FreeMonoBoldOblique24pt7bBitmaps,\n  (GFXglyph *)FreeMonoBoldOblique24pt7bGlyphs,\n  0x20, 0x7E, 47 };\n\n// Approx. 8307 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeMonoBoldOblique9pt7b.h",
    "content": "const uint8_t FreeMonoBoldOblique9pt7bBitmaps[] PROGMEM = {\n  0x39, 0xCC, 0x67, 0x31, 0x8C, 0x07, 0x38, 0x6C, 0xD9, 0x36, 0x48, 0x80,\n  0x09, 0x0D, 0x86, 0xCF, 0xF7, 0xF9, 0xB3, 0xFD, 0xFE, 0x6C, 0x36, 0x1B,\n  0x00, 0x00, 0x06, 0x07, 0x07, 0xE6, 0x33, 0x01, 0xE0, 0x7C, 0x06, 0x43,\n  0x33, 0xBF, 0x83, 0x03, 0x00, 0x80, 0x1C, 0x11, 0x10, 0x88, 0x83, 0xB8,\n  0xF3, 0xB8, 0x22, 0x21, 0x11, 0x07, 0x00, 0x0F, 0x1F, 0x30, 0x30, 0x38,\n  0x7B, 0xDF, 0xCE, 0xFF, 0x7E, 0xFA, 0x80, 0x19, 0x8C, 0xC6, 0x63, 0x18,\n  0xC6, 0x31, 0xC6, 0x30, 0x31, 0xC6, 0x31, 0x8C, 0x63, 0x31, 0x98, 0xCC,\n  0x40, 0x08, 0x08, 0xFF, 0xFF, 0x38, 0x6C, 0x6C, 0x0C, 0x06, 0x03, 0x1F,\n  0xFF, 0xF8, 0xC0, 0x60, 0x30, 0x10, 0x00, 0x36, 0x4C, 0x80, 0xFF, 0xFF,\n  0xC0, 0xFC, 0x00, 0x00, 0x0C, 0x03, 0x00, 0xC0, 0x18, 0x06, 0x01, 0x80,\n  0x30, 0x0C, 0x03, 0x00, 0x60, 0x18, 0x06, 0x00, 0xC0, 0x30, 0x00, 0x0F,\n  0x0F, 0xCC, 0x6C, 0x36, 0x1B, 0x0D, 0x05, 0x86, 0xC3, 0x63, 0x3F, 0x8F,\n  0x00, 0x06, 0x1C, 0x3C, 0x6C, 0x0C, 0x0C, 0x08, 0x18, 0x18, 0x18, 0xFE,\n  0xFE, 0x07, 0x83, 0xF1, 0x8C, 0x43, 0x00, 0xC0, 0xE0, 0x70, 0x38, 0x38,\n  0x1C, 0x6F, 0xF3, 0xFC, 0x1F, 0x1F, 0xC0, 0x60, 0x30, 0x30, 0x70, 0x38,\n  0x06, 0x03, 0x03, 0xBF, 0x9F, 0x80, 0x03, 0x07, 0x0B, 0x1B, 0x32, 0x66,\n  0xFF, 0xFF, 0x1E, 0x1E, 0x3F, 0x9F, 0x98, 0x0F, 0xC7, 0xF3, 0x18, 0x0C,\n  0x06, 0x06, 0x7F, 0x1E, 0x00, 0x07, 0x87, 0xCE, 0x06, 0x06, 0x03, 0xF3,\n  0xFD, 0xC6, 0xC3, 0x63, 0xBF, 0x8F, 0x80, 0xFF, 0xFF, 0xC3, 0x06, 0x06,\n  0x0C, 0x18, 0x18, 0x30, 0x30, 0x60, 0x1F, 0x1F, 0xDC, 0x6C, 0x36, 0x31,\n  0xF1, 0xF8, 0xC6, 0xC3, 0x63, 0xBF, 0x8F, 0x80, 0x1E, 0x3F, 0x33, 0x63,\n  0x63, 0x67, 0x7F, 0x3E, 0x06, 0x1C, 0xF8, 0xF0, 0x77, 0x00, 0x00, 0xEE,\n  0x1C, 0x70, 0x00, 0x00, 0x03, 0x0C, 0x61, 0x08, 0x00, 0x00, 0xC1, 0xE1,\n  0xE1, 0xE0, 0xF0, 0x07, 0x00, 0xF0, 0x0C, 0x7F, 0xDF, 0xF0, 0x00, 0x00,\n  0x7F, 0xFF, 0xF0, 0x30, 0x0F, 0x00, 0xE0, 0x1E, 0x07, 0xC7, 0x87, 0x83,\n  0x00, 0x7D, 0xFF, 0x18, 0x30, 0xE3, 0x9C, 0x30, 0x01, 0xC3, 0x80, 0x0F,\n  0x0F, 0xCC, 0x6C, 0x36, 0x72, 0x79, 0x7D, 0xB6, 0xDA, 0x6F, 0xB3, 0xD8,\n  0x0C, 0x07, 0xE1, 0xE0, 0x0F, 0x83, 0xF0, 0x1E, 0x03, 0xC0, 0xD8, 0x31,\n  0x87, 0xF1, 0xFE, 0x30, 0xDF, 0x3F, 0xC7, 0x80, 0x3F, 0xC7, 0xFC, 0x61,\n  0x8C, 0x31, 0xFC, 0x3F, 0x84, 0x19, 0x83, 0x30, 0x6F, 0xFB, 0xFE, 0x00,\n  0x0F, 0xF1, 0xFF, 0x30, 0x66, 0x06, 0x60, 0x0C, 0x00, 0xC0, 0x0C, 0x00,\n  0xE0, 0xC7, 0xF8, 0x3F, 0x00, 0x3F, 0x87, 0xF8, 0x63, 0x8C, 0x31, 0x06,\n  0x60, 0xCC, 0x19, 0x86, 0x31, 0xCF, 0xF3, 0xF8, 0x00, 0x3F, 0xE3, 0xFE,\n  0x18, 0x61, 0xB6, 0x1F, 0x01, 0xF0, 0x32, 0x03, 0x00, 0x30, 0x4F, 0xFC,\n  0xFF, 0xC0, 0x3F, 0xF3, 0xFE, 0x18, 0x61, 0xB6, 0x1F, 0x03, 0xF0, 0x32,\n  0x03, 0x00, 0x30, 0x0F, 0xC0, 0xFC, 0x00, 0x0F, 0xE3, 0xFC, 0xC1, 0x30,\n  0x06, 0x01, 0x80, 0x31, 0xF6, 0x3E, 0xE1, 0x9F, 0xF0, 0xF8, 0x00, 0x1E,\n  0xF3, 0xCF, 0x18, 0x61, 0x84, 0x10, 0xC3, 0xFC, 0x3F, 0xC3, 0x08, 0x31,\n  0x8F, 0xBC, 0xFB, 0xC0, 0x3F, 0xCF, 0xF0, 0x60, 0x10, 0x0C, 0x03, 0x00,\n  0xC0, 0x20, 0x18, 0x3F, 0xCF, 0xF0, 0x07, 0xF0, 0x7F, 0x00, 0x80, 0x18,\n  0x01, 0x80, 0x18, 0x61, 0x84, 0x10, 0xC3, 0x0F, 0xE0, 0x7C, 0x00, 0x3E,\n  0xE7, 0xFC, 0x66, 0x0D, 0x81, 0x60, 0x7C, 0x0E, 0xC1, 0x98, 0x31, 0x1F,\n  0x3B, 0xE7, 0x00, 0x3F, 0x07, 0xE0, 0x30, 0x06, 0x00, 0xC0, 0x10, 0x06,\n  0x00, 0xC3, 0x18, 0x6F, 0xFB, 0xFF, 0x00, 0x38, 0x39, 0xC3, 0xC7, 0x3C,\n  0x79, 0xE3, 0xDA, 0x1F, 0xF0, 0x9D, 0x8C, 0xCC, 0x60, 0x67, 0xCF, 0x3C,\n  0x78, 0x3C, 0xF9, 0xE7, 0x87, 0x18, 0x3C, 0xC1, 0x66, 0x1B, 0xB0, 0xCD,\n  0x06, 0x78, 0x31, 0xC3, 0xCE, 0x3E, 0x30, 0x0F, 0x0F, 0xE7, 0x1D, 0x83,\n  0xC0, 0xF0, 0x3C, 0x0F, 0x06, 0xE3, 0x9F, 0xC3, 0xC0, 0x3F, 0xC7, 0xFC,\n  0x61, 0x8C, 0x31, 0x8E, 0x3F, 0x87, 0xE1, 0x80, 0x30, 0x0F, 0xC3, 0xF0,\n  0x00, 0x0F, 0x0F, 0xE7, 0x1D, 0x83, 0xC0, 0xF0, 0x3C, 0x0F, 0x06, 0xE3,\n  0x1F, 0xC3, 0xC0, 0x80, 0x7F, 0x3F, 0xC0, 0x3F, 0xC3, 0xFE, 0x18, 0x61,\n  0x86, 0x10, 0xE3, 0xFC, 0x3F, 0x83, 0x18, 0x31, 0xCF, 0x8F, 0xF8, 0x70,\n  0x1E, 0xCF, 0xF7, 0x19, 0x80, 0x70, 0x1F, 0x81, 0xF3, 0x0C, 0xC3, 0x3F,\n  0x8B, 0xC0, 0x7F, 0xCF, 0xF9, 0x93, 0x66, 0x60, 0xC0, 0x18, 0x02, 0x00,\n  0xC0, 0x18, 0x0F, 0xC1, 0xF8, 0x00, 0xF9, 0xFF, 0x7D, 0x83, 0x30, 0x64,\n  0x09, 0x83, 0x30, 0x66, 0x0C, 0xE3, 0x0F, 0xC0, 0xF0, 0x00, 0xF9, 0xFE,\n  0x3D, 0x83, 0x30, 0xC6, 0x30, 0xE6, 0x0D, 0x81, 0xB0, 0x3C, 0x07, 0x00,\n  0x60, 0x00, 0xF9, 0xFF, 0x3D, 0x83, 0x36, 0x64, 0xC8, 0xBF, 0x35, 0xE7,\n  0xB8, 0xE7, 0x1C, 0xE3, 0x18, 0x00, 0x3C, 0xF3, 0xCF, 0x1C, 0xC0, 0xD8,\n  0x0F, 0x00, 0x60, 0x0F, 0x01, 0xB8, 0x31, 0x8F, 0x3C, 0xF3, 0xC0, 0x79,\n  0xEE, 0x38, 0xC6, 0x19, 0x81, 0xE0, 0x38, 0x06, 0x00, 0xC0, 0x18, 0x0F,\n  0xC3, 0xF8, 0x00, 0x3F, 0xCF, 0xF3, 0x18, 0xCC, 0x06, 0x03, 0x01, 0x80,\n  0xC6, 0x61, 0xBF, 0xCF, 0xF0, 0x1E, 0x3C, 0xC1, 0x83, 0x06, 0x08, 0x30,\n  0x60, 0xC1, 0x06, 0x0F, 0x1E, 0x00, 0x06, 0x31, 0x86, 0x31, 0x8C, 0x31,\n  0x8C, 0x61, 0x8C, 0x60, 0x1E, 0x78, 0x30, 0x60, 0xC1, 0x86, 0x0C, 0x18,\n  0x30, 0x41, 0x8F, 0x1E, 0x00, 0x08, 0x1C, 0x3C, 0x76, 0xE7, 0xC3, 0x7F,\n  0xFF, 0xFC, 0x88, 0x80, 0x0F, 0x07, 0xE1, 0xF9, 0xFE, 0xE3, 0x30, 0xCF,\n  0xFD, 0xFF, 0x38, 0x07, 0x00, 0x60, 0x0F, 0xC1, 0xFC, 0x71, 0xCC, 0x19,\n  0x83, 0x30, 0xDF, 0xFB, 0xBC, 0x00, 0x1F, 0xCF, 0xF6, 0x1B, 0x00, 0xC0,\n  0x30, 0x0F, 0xF1, 0xF8, 0x01, 0xE0, 0x38, 0x03, 0x0F, 0x63, 0xFC, 0xC3,\n  0x30, 0x66, 0x0C, 0xC3, 0x9F, 0xF9, 0xF7, 0x00, 0x1F, 0x1F, 0xD8, 0x3F,\n  0xFF, 0xFE, 0x1B, 0xFC, 0xF8, 0x07, 0xC3, 0xF1, 0x81, 0xFE, 0x7F, 0x84,\n  0x03, 0x00, 0xC0, 0x30, 0x3F, 0x8F, 0xE0, 0x1E, 0xE7, 0xFD, 0x86, 0x60,\n  0xCC, 0x19, 0xC6, 0x3F, 0xC1, 0xD8, 0x03, 0x00, 0xE1, 0xF8, 0x3E, 0x00,\n  0x38, 0x1E, 0x01, 0x00, 0xDC, 0x3F, 0x8C, 0x62, 0x19, 0x84, 0x63, 0x3D,\n  0xFF, 0x7C, 0x06, 0x03, 0x00, 0x03, 0xC3, 0xE0, 0x20, 0x30, 0x18, 0x0C,\n  0x3F, 0xFF, 0xE0, 0x01, 0x81, 0x80, 0x07, 0xF3, 0xF8, 0x0C, 0x04, 0x06,\n  0x03, 0x01, 0x80, 0xC0, 0x40, 0x67, 0xE3, 0xE0, 0x38, 0x0E, 0x01, 0x80,\n  0x4F, 0x37, 0xCF, 0x83, 0xC0, 0xF0, 0x26, 0x39, 0xEE, 0x78, 0x1F, 0x0F,\n  0x01, 0x80, 0xC0, 0x60, 0x20, 0x30, 0x18, 0x0C, 0x3F, 0xFF, 0xE0, 0x7E,\n  0xE7, 0xFF, 0x33, 0x32, 0x63, 0x66, 0x36, 0x62, 0xF7, 0x7F, 0x67, 0x77,\n  0x8F, 0xF8, 0xC3, 0x10, 0x66, 0x08, 0xC3, 0x3C, 0x7F, 0x8F, 0x1F, 0x0F,\n  0xE6, 0x1F, 0x03, 0xC0, 0xF8, 0x67, 0xF0, 0xF8, 0x3F, 0xE3, 0xFF, 0x1C,\n  0x31, 0x83, 0x18, 0x31, 0x86, 0x3F, 0xE3, 0x78, 0x30, 0x03, 0x00, 0xFC,\n  0x0F, 0x80, 0x1E, 0xEF, 0xFD, 0x86, 0x60, 0xCC, 0x19, 0xC7, 0x3F, 0xE1,\n  0xE8, 0x03, 0x00, 0x60, 0x3E, 0x07, 0xC0, 0x39, 0xDF, 0xF1, 0xC0, 0x60,\n  0x10, 0x0C, 0x0F, 0xF3, 0xF8, 0x1F, 0x7F, 0x63, 0x7E, 0x1F, 0xC3, 0xFE,\n  0xFC, 0x10, 0x08, 0x0C, 0x1F, 0xEF, 0xF1, 0x80, 0x80, 0xC0, 0x60, 0x3F,\n  0x8F, 0x80, 0xF3, 0xFC, 0xF6, 0x09, 0x86, 0x61, 0x98, 0xE7, 0xF8, 0xFE,\n  0xFB, 0xFF, 0x7C, 0xC6, 0x19, 0x83, 0x60, 0x6C, 0x07, 0x00, 0xC0, 0xF1,\n  0xFE, 0x3D, 0xB3, 0x37, 0xC7, 0xF8, 0xEE, 0x1D, 0xC3, 0x30, 0x79, 0xEF,\n  0x38, 0xEE, 0x0F, 0x01, 0xE0, 0x6E, 0x3C, 0xE7, 0xBC, 0x3C, 0xF3, 0x8F,\n  0x18, 0xC1, 0x9C, 0x19, 0x81, 0xF0, 0x0E, 0x00, 0xE0, 0x0C, 0x01, 0x80,\n  0xFC, 0x0F, 0xC0, 0x7F, 0xBF, 0xD9, 0xC1, 0x83, 0x83, 0x1B, 0xFD, 0xFE,\n  0x06, 0x1C, 0x60, 0xC1, 0x86, 0x3C, 0x70, 0x30, 0x41, 0x83, 0x07, 0x06,\n  0x00, 0x33, 0x32, 0x26, 0x66, 0x44, 0xCC, 0xC8, 0x0C, 0x0E, 0x04, 0x0C,\n  0x0C, 0x0C, 0x0F, 0x0F, 0x18, 0x18, 0x10, 0x30, 0xF0, 0xE0, 0x38, 0x7C,\n  0xF7, 0xC1, 0xC0 };\n\nconst GFXglyph FreeMonoBoldOblique9pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,  11,    0,    1 },   // 0x20 ' '\n  {     0,   5,  11,  11,    4,  -10 },   // 0x21 '!'\n  {     7,   7,   5,  11,    4,  -10 },   // 0x22 '\"'\n  {    12,   9,  12,  11,    2,  -10 },   // 0x23 '#'\n  {    26,   9,  14,  11,    2,  -11 },   // 0x24 '$'\n  {    42,   9,  11,  11,    2,  -10 },   // 0x25 '%'\n  {    55,   8,  10,  11,    2,   -9 },   // 0x26 '&'\n  {    65,   2,   5,  11,    6,  -10 },   // 0x27 '''\n  {    67,   5,  14,  11,    5,  -10 },   // 0x28 '('\n  {    76,   5,  14,  11,    2,  -10 },   // 0x29 ')'\n  {    85,   8,   7,  11,    3,  -10 },   // 0x2A '*'\n  {    92,   9,   9,  11,    2,   -8 },   // 0x2B '+'\n  {   103,   4,   5,  11,    2,   -1 },   // 0x2C ','\n  {   106,   9,   2,  11,    2,   -5 },   // 0x2D '-'\n  {   109,   3,   2,  11,    4,   -1 },   // 0x2E '.'\n  {   110,  11,  15,  11,    1,  -12 },   // 0x2F '/'\n  {   131,   9,  12,  11,    2,  -11 },   // 0x30 '0'\n  {   145,   8,  12,  11,    2,  -11 },   // 0x31 '1'\n  {   157,  10,  12,  11,    1,  -11 },   // 0x32 '2'\n  {   172,   9,  12,  11,    2,  -11 },   // 0x33 '3'\n  {   186,   8,  10,  11,    2,   -9 },   // 0x34 '4'\n  {   196,   9,  11,  11,    3,  -10 },   // 0x35 '5'\n  {   209,   9,  12,  11,    3,  -11 },   // 0x36 '6'\n  {   223,   8,  11,  11,    3,  -10 },   // 0x37 '7'\n  {   234,   9,  12,  11,    2,  -11 },   // 0x38 '8'\n  {   248,   8,  12,  11,    3,  -11 },   // 0x39 '9'\n  {   260,   4,   8,  11,    4,   -7 },   // 0x3A ':'\n  {   264,   6,  11,  11,    2,   -7 },   // 0x3B ';'\n  {   273,  10,   8,  11,    2,   -8 },   // 0x3C '<'\n  {   283,  10,   6,  11,    1,   -7 },   // 0x3D '='\n  {   291,  10,   8,  11,    1,   -8 },   // 0x3E '>'\n  {   301,   7,  11,  11,    4,  -10 },   // 0x3F '?'\n  {   311,   9,  15,  11,    2,  -11 },   // 0x40 '@'\n  {   328,  11,  11,  11,    0,  -10 },   // 0x41 'A'\n  {   344,  11,  11,  11,    0,  -10 },   // 0x42 'B'\n  {   360,  12,  11,  11,    1,  -10 },   // 0x43 'C'\n  {   377,  11,  11,  11,    0,  -10 },   // 0x44 'D'\n  {   393,  12,  11,  11,    0,  -10 },   // 0x45 'E'\n  {   410,  12,  11,  11,    0,  -10 },   // 0x46 'F'\n  {   427,  11,  11,  11,    1,  -10 },   // 0x47 'G'\n  {   443,  12,  11,  11,    0,  -10 },   // 0x48 'H'\n  {   460,  10,  11,  11,    1,  -10 },   // 0x49 'I'\n  {   474,  12,  11,  11,    0,  -10 },   // 0x4A 'J'\n  {   491,  11,  11,  11,    0,  -10 },   // 0x4B 'K'\n  {   507,  11,  11,  11,    0,  -10 },   // 0x4C 'L'\n  {   523,  13,  11,  11,    0,  -10 },   // 0x4D 'M'\n  {   541,  13,  11,  11,    0,  -10 },   // 0x4E 'N'\n  {   559,  10,  11,  11,    1,  -10 },   // 0x4F 'O'\n  {   573,  11,  11,  11,    0,  -10 },   // 0x50 'P'\n  {   589,  10,  14,  11,    1,  -10 },   // 0x51 'Q'\n  {   607,  12,  11,  11,    0,  -10 },   // 0x52 'R'\n  {   624,  10,  11,  11,    2,  -10 },   // 0x53 'S'\n  {   638,  11,  11,  11,    1,  -10 },   // 0x54 'T'\n  {   654,  11,  11,  11,    1,  -10 },   // 0x55 'U'\n  {   670,  11,  11,  11,    1,  -10 },   // 0x56 'V'\n  {   686,  11,  11,  11,    1,  -10 },   // 0x57 'W'\n  {   702,  12,  11,  11,    0,  -10 },   // 0x58 'X'\n  {   719,  11,  11,  11,    1,  -10 },   // 0x59 'Y'\n  {   735,  10,  11,  11,    1,  -10 },   // 0x5A 'Z'\n  {   749,   7,  14,  11,    4,  -10 },   // 0x5B '['\n  {   762,   5,  15,  11,    4,  -12 },   // 0x5C '\\'\n  {   772,   7,  14,  11,    2,  -10 },   // 0x5D ']'\n  {   785,   8,   6,  11,    3,  -11 },   // 0x5E '^'\n  {   791,  11,   2,  11,   -1,    3 },   // 0x5F '_'\n  {   794,   3,   3,  11,    5,  -11 },   // 0x60 '`'\n  {   796,  10,   8,  11,    1,   -7 },   // 0x61 'a'\n  {   806,  11,  11,  11,    0,  -10 },   // 0x62 'b'\n  {   822,  10,   8,  11,    1,   -7 },   // 0x63 'c'\n  {   832,  11,  11,  11,    1,  -10 },   // 0x64 'd'\n  {   848,   9,   8,  11,    1,   -7 },   // 0x65 'e'\n  {   857,  10,  11,  11,    2,  -10 },   // 0x66 'f'\n  {   871,  11,  12,  11,    1,   -7 },   // 0x67 'g'\n  {   888,  10,  11,  11,    1,  -10 },   // 0x68 'h'\n  {   902,   9,  11,  11,    1,  -10 },   // 0x69 'i'\n  {   915,   9,  15,  11,    1,  -10 },   // 0x6A 'j'\n  {   932,  10,  11,  11,    1,  -10 },   // 0x6B 'k'\n  {   946,   9,  11,  11,    1,  -10 },   // 0x6C 'l'\n  {   959,  12,   8,  11,    0,   -7 },   // 0x6D 'm'\n  {   971,  11,   8,  11,    1,   -7 },   // 0x6E 'n'\n  {   982,  10,   8,  11,    1,   -7 },   // 0x6F 'o'\n  {   992,  12,  12,  11,   -1,   -7 },   // 0x70 'p'\n  {  1010,  11,  12,  11,    1,   -7 },   // 0x71 'q'\n  {  1027,  10,   8,  11,    1,   -7 },   // 0x72 'r'\n  {  1037,   8,   8,  11,    2,   -7 },   // 0x73 's'\n  {  1045,   9,  11,  11,    1,  -10 },   // 0x74 't'\n  {  1058,  10,   8,  11,    1,   -7 },   // 0x75 'u'\n  {  1068,  11,   8,  11,    1,   -7 },   // 0x76 'v'\n  {  1079,  11,   8,  11,    1,   -7 },   // 0x77 'w'\n  {  1090,  11,   8,  11,    1,   -7 },   // 0x78 'x'\n  {  1101,  12,  12,  11,    0,   -7 },   // 0x79 'y'\n  {  1119,   9,   8,  11,    2,   -7 },   // 0x7A 'z'\n  {  1128,   7,  14,  11,    3,  -10 },   // 0x7B '{'\n  {  1141,   4,  14,  11,    4,  -10 },   // 0x7C '|'\n  {  1148,   8,  14,  11,    2,  -10 },   // 0x7D '}'\n  {  1162,   9,   4,  11,    2,   -6 } }; // 0x7E '~'\n\nconst GFXfont FreeMonoBoldOblique9pt7b PROGMEM = {\n  (uint8_t  *)FreeMonoBoldOblique9pt7bBitmaps,\n  (GFXglyph *)FreeMonoBoldOblique9pt7bGlyphs,\n  0x20, 0x7E, 18 };\n\n// Approx. 1839 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeMonoOblique12pt7b.h",
    "content": "const uint8_t FreeMonoOblique12pt7bBitmaps[] PROGMEM = {\n  0x11, 0x11, 0x12, 0x22, 0x22, 0x00, 0x0E, 0xE0, 0xE7, 0xE7, 0xC6, 0xC6,\n  0xC6, 0x84, 0x84, 0x02, 0x40, 0x88, 0x12, 0x02, 0x40, 0x48, 0x7F, 0xC2,\n  0x40, 0x48, 0x11, 0x1F, 0xF8, 0x48, 0x09, 0x02, 0x40, 0x48, 0x09, 0x02,\n  0x20, 0x02, 0x01, 0x00, 0xF4, 0xC3, 0x60, 0x50, 0x04, 0x00, 0xC0, 0x0F,\n  0x00, 0x60, 0x0A, 0x02, 0x81, 0x30, 0xC7, 0xC0, 0x80, 0x20, 0x08, 0x00,\n  0x0E, 0x02, 0x20, 0x84, 0x10, 0x82, 0x20, 0x38, 0x00, 0x38, 0x38, 0x38,\n  0x08, 0xE0, 0x22, 0x08, 0x41, 0x08, 0x22, 0x03, 0x80, 0x07, 0x84, 0x04,\n  0x02, 0x01, 0x00, 0xC1, 0xA2, 0x8A, 0x85, 0x43, 0x31, 0x8F, 0x60, 0xFF,\n  0x6D, 0x20, 0x00, 0x44, 0x42, 0x21, 0x08, 0x84, 0x21, 0x08, 0x42, 0x10,\n  0x42, 0x00, 0x00, 0x84, 0x10, 0x84, 0x21, 0x08, 0x46, 0x21, 0x10, 0x88,\n  0x44, 0x00, 0x04, 0x02, 0x02, 0x1D, 0x13, 0xF0, 0x40, 0x50, 0x48, 0x44,\n  0x00, 0x02, 0x00, 0x40, 0x08, 0x02, 0x00, 0x41, 0xFF, 0xC1, 0x00, 0x20,\n  0x08, 0x01, 0x00, 0x20, 0x00, 0x1C, 0xE3, 0x18, 0x63, 0x08, 0x00, 0xFF,\n  0xE0, 0x7F, 0x00, 0x00, 0x08, 0x00, 0x80, 0x04, 0x00, 0x40, 0x04, 0x00,\n  0x60, 0x02, 0x00, 0x20, 0x03, 0x00, 0x10, 0x01, 0x00, 0x18, 0x00, 0x80,\n  0x08, 0x00, 0x80, 0x04, 0x00, 0x40, 0x04, 0x00, 0x00, 0x07, 0x06, 0x23,\n  0x04, 0x81, 0x40, 0x50, 0x14, 0x06, 0x02, 0x80, 0xA0, 0x28, 0x0A, 0x04,\n  0x83, 0x11, 0x83, 0x80, 0x03, 0x03, 0x83, 0x83, 0x43, 0x20, 0x10, 0x08,\n  0x08, 0x04, 0x02, 0x01, 0x01, 0x00, 0x80, 0x43, 0xFE, 0x01, 0xC0, 0x62,\n  0x0C, 0x10, 0x81, 0x00, 0x10, 0x02, 0x00, 0x60, 0x0C, 0x01, 0x00, 0x20,\n  0x0C, 0x01, 0x80, 0x20, 0x04, 0x04, 0xFF, 0xC0, 0x07, 0xC3, 0x0C, 0x00,\n  0x80, 0x10, 0x06, 0x01, 0x81, 0xC0, 0x0C, 0x00, 0x40, 0x08, 0x01, 0x00,\n  0x20, 0x09, 0x86, 0x0F, 0x00, 0x00, 0xC0, 0x50, 0x24, 0x12, 0x04, 0x82,\n  0x21, 0x08, 0x82, 0x21, 0x10, 0x4F, 0xF8, 0x04, 0x01, 0x00, 0x80, 0xF8,\n  0x0F, 0xE2, 0x00, 0x40, 0x08, 0x01, 0x00, 0x4E, 0x0E, 0x20, 0x02, 0x00,\n  0x40, 0x08, 0x01, 0x00, 0x40, 0x19, 0x06, 0x1F, 0x00, 0x01, 0xE0, 0xC0,\n  0x60, 0x18, 0x02, 0x00, 0x80, 0x13, 0xC5, 0x88, 0xE0, 0x98, 0x12, 0x02,\n  0x40, 0x48, 0x10, 0x84, 0x0F, 0x00, 0xFF, 0xA0, 0x20, 0x08, 0x04, 0x01,\n  0x00, 0x80, 0x20, 0x10, 0x04, 0x02, 0x00, 0x80, 0x40, 0x10, 0x08, 0x02,\n  0x00, 0x07, 0x81, 0x08, 0x40, 0x90, 0x12, 0x02, 0x40, 0x84, 0x20, 0x78,\n  0x30, 0x88, 0x0A, 0x01, 0x40, 0x28, 0x08, 0x82, 0x0F, 0x80, 0x07, 0x81,\n  0x08, 0x40, 0x90, 0x12, 0x02, 0x40, 0xC8, 0x39, 0x8D, 0x1E, 0x40, 0x08,\n  0x02, 0x00, 0xC0, 0x30, 0x18, 0x3E, 0x00, 0x19, 0xCC, 0x00, 0x00, 0x0C,\n  0xE6, 0x00, 0x06, 0x1C, 0x30, 0x00, 0x00, 0x00, 0x1C, 0x30, 0xE1, 0x86,\n  0x08, 0x00, 0x00, 0x30, 0x0C, 0x03, 0x00, 0xC0, 0x30, 0x06, 0x00, 0x30,\n  0x00, 0xC0, 0x06, 0x00, 0x18, 0x00, 0xC0, 0x7F, 0xF8, 0x00, 0x00, 0x01,\n  0xFF, 0xE0, 0x18, 0x00, 0xC0, 0x03, 0x00, 0x18, 0x00, 0x60, 0x03, 0x00,\n  0xC0, 0x30, 0x0C, 0x03, 0x00, 0xC0, 0x00, 0x3E, 0xC3, 0x81, 0x01, 0x03,\n  0x06, 0x18, 0x20, 0x20, 0x00, 0x00, 0x00, 0xE0, 0xE0, 0x07, 0x82, 0x31,\n  0x04, 0x81, 0x20, 0x48, 0x74, 0x65, 0x21, 0x48, 0x92, 0x28, 0x7A, 0x00,\n  0x80, 0x20, 0x04, 0x00, 0xF8, 0x07, 0xE0, 0x02, 0x80, 0x0A, 0x00, 0x48,\n  0x01, 0x20, 0x08, 0x40, 0x41, 0x01, 0x04, 0x0F, 0xF0, 0x20, 0x41, 0x01,\n  0x04, 0x02, 0x20, 0x0B, 0xE1, 0xF0, 0x1F, 0xF0, 0x40, 0xC2, 0x02, 0x10,\n  0x10, 0x81, 0x84, 0x18, 0x7F, 0x82, 0x02, 0x10, 0x08, 0x80, 0x44, 0x02,\n  0x60, 0x22, 0x03, 0x7F, 0xE0, 0x07, 0x91, 0x87, 0x20, 0x34, 0x02, 0x40,\n  0x08, 0x00, 0x80, 0x08, 0x00, 0x80, 0x08, 0x00, 0x80, 0x04, 0x04, 0x61,\n  0x81, 0xE0, 0x1F, 0xE0, 0x41, 0x82, 0x06, 0x10, 0x11, 0x00, 0x88, 0x04,\n  0x40, 0x22, 0x01, 0x10, 0x11, 0x00, 0x88, 0x08, 0x40, 0xC2, 0x0C, 0x7F,\n  0x80, 0x1F, 0xFC, 0x20, 0x10, 0x80, 0x82, 0x00, 0x08, 0x00, 0x22, 0x01,\n  0xF8, 0x04, 0x20, 0x10, 0x00, 0x40, 0x01, 0x01, 0x0C, 0x04, 0x20, 0x13,\n  0xFF, 0xC0, 0x1F, 0xFC, 0x20, 0x10, 0x80, 0x42, 0x01, 0x08, 0x00, 0x22,\n  0x01, 0xF8, 0x04, 0x20, 0x10, 0x00, 0x40, 0x01, 0x00, 0x0C, 0x00, 0x20,\n  0x03, 0xF8, 0x00, 0x07, 0xD0, 0x83, 0x30, 0x12, 0x00, 0x40, 0x04, 0x00,\n  0x80, 0x08, 0x00, 0x83, 0xE8, 0x04, 0x80, 0x4C, 0x04, 0x60, 0x41, 0xF8,\n  0x0F, 0x3C, 0x08, 0x10, 0x20, 0x20, 0x40, 0x40, 0x81, 0x01, 0x02, 0x03,\n  0xFC, 0x08, 0x08, 0x10, 0x10, 0x20, 0x40, 0x40, 0x80, 0x81, 0x02, 0x02,\n  0x1F, 0x1E, 0x00, 0x3F, 0xE0, 0x40, 0x08, 0x01, 0x00, 0x20, 0x08, 0x01,\n  0x00, 0x20, 0x04, 0x00, 0x80, 0x20, 0x04, 0x00, 0x81, 0xFF, 0x00, 0x03,\n  0xFE, 0x00, 0x20, 0x00, 0x80, 0x01, 0x00, 0x02, 0x00, 0x04, 0x00, 0x08,\n  0x00, 0x20, 0x40, 0x40, 0x80, 0x81, 0x01, 0x02, 0x04, 0x06, 0x10, 0x07,\n  0xC0, 0x00, 0x1F, 0x1E, 0x10, 0x10, 0x20, 0xC0, 0x43, 0x00, 0x88, 0x01,\n  0x20, 0x07, 0xC0, 0x0C, 0x40, 0x10, 0x40, 0x20, 0x80, 0x41, 0x01, 0x81,\n  0x02, 0x02, 0x1F, 0x87, 0x00, 0x3F, 0x80, 0x40, 0x04, 0x00, 0x40, 0x08,\n  0x00, 0x80, 0x08, 0x00, 0x80, 0x08, 0x01, 0x01, 0x10, 0x11, 0x02, 0x10,\n  0x2F, 0xFE, 0x1C, 0x03, 0x85, 0x03, 0x02, 0x82, 0x81, 0x41, 0x40, 0xA1,\n  0x20, 0x89, 0x30, 0x44, 0x90, 0x22, 0x88, 0x11, 0x44, 0x08, 0x42, 0x08,\n  0x03, 0x04, 0x01, 0x02, 0x00, 0x87, 0xC3, 0xE0, 0x3C, 0x3E, 0x18, 0x08,\n  0x38, 0x20, 0x50, 0x41, 0x20, 0x82, 0x61, 0x04, 0x42, 0x08, 0x88, 0x10,\n  0x90, 0x41, 0x20, 0x83, 0x41, 0x02, 0x82, 0x06, 0x1F, 0x04, 0x00, 0x03,\n  0xC0, 0x61, 0x84, 0x04, 0x40, 0x14, 0x00, 0xA0, 0x06, 0x00, 0x30, 0x01,\n  0x80, 0x14, 0x00, 0xA0, 0x08, 0x80, 0x86, 0x18, 0x0F, 0x00, 0x1F, 0xE0,\n  0x40, 0x82, 0x02, 0x10, 0x10, 0x80, 0x84, 0x08, 0x40, 0x83, 0xF8, 0x10,\n  0x00, 0x80, 0x04, 0x00, 0x60, 0x02, 0x00, 0x7F, 0x00, 0x03, 0xC0, 0x61,\n  0x84, 0x04, 0x40, 0x14, 0x00, 0xA0, 0x06, 0x00, 0x30, 0x01, 0x80, 0x14,\n  0x00, 0xA0, 0x08, 0x80, 0x86, 0x18, 0x1F, 0x00, 0x40, 0x0F, 0xC4, 0x41,\n  0xC0, 0x1F, 0xE0, 0x40, 0x82, 0x02, 0x10, 0x10, 0x80, 0x84, 0x08, 0x60,\n  0x83, 0xF8, 0x10, 0xC0, 0x82, 0x04, 0x08, 0x40, 0x42, 0x03, 0x7E, 0x0C,\n  0x07, 0xA3, 0x0C, 0x40, 0x90, 0x12, 0x00, 0x40, 0x06, 0x00, 0x3C, 0x00,\n  0x40, 0x0A, 0x01, 0x40, 0x4C, 0x11, 0x7C, 0x00, 0xFF, 0xE8, 0x42, 0x84,\n  0x20, 0x40, 0x04, 0x00, 0x80, 0x08, 0x00, 0x80, 0x08, 0x00, 0x80, 0x10,\n  0x01, 0x00, 0x10, 0x0F, 0xE0, 0xF8, 0xF9, 0x00, 0x88, 0x08, 0x80, 0x44,\n  0x02, 0x20, 0x11, 0x01, 0x08, 0x08, 0x80, 0x44, 0x02, 0x20, 0x31, 0x01,\n  0x04, 0x30, 0x1E, 0x00, 0xF8, 0x7D, 0x00, 0x42, 0x01, 0x08, 0x08, 0x20,\n  0x40, 0x81, 0x02, 0x08, 0x08, 0x20, 0x11, 0x00, 0x48, 0x01, 0x20, 0x05,\n  0x00, 0x14, 0x00, 0x60, 0x00, 0xF8, 0x7D, 0x00, 0x44, 0x01, 0x11, 0x84,\n  0x46, 0x21, 0x18, 0x84, 0xA2, 0x12, 0x90, 0x91, 0x42, 0x45, 0x0A, 0x14,\n  0x28, 0x60, 0xC1, 0x83, 0x06, 0x00, 0x1E, 0x1E, 0x10, 0x10, 0x10, 0x40,\n  0x21, 0x00, 0x24, 0x00, 0x78, 0x00, 0x60, 0x01, 0xC0, 0x06, 0x80, 0x09,\n  0x80, 0x21, 0x00, 0x81, 0x02, 0x02, 0x1E, 0x1F, 0x00, 0xF0, 0xF4, 0x04,\n  0x20, 0x82, 0x18, 0x11, 0x01, 0x20, 0x1C, 0x00, 0x80, 0x08, 0x00, 0x80,\n  0x10, 0x01, 0x00, 0x10, 0x0F, 0xE0, 0x0F, 0xF1, 0x01, 0x10, 0x21, 0x04,\n  0x00, 0x80, 0x10, 0x02, 0x00, 0x40, 0x0C, 0x01, 0x82, 0x10, 0x22, 0x04,\n  0x40, 0x47, 0xFC, 0x0E, 0x20, 0x40, 0x81, 0x02, 0x08, 0x10, 0x20, 0x40,\n  0x82, 0x04, 0x08, 0x10, 0x20, 0x81, 0xE0, 0x84, 0x20, 0x84, 0x20, 0x84,\n  0x21, 0x04, 0x21, 0x08, 0x21, 0x08, 0x40, 0x1E, 0x04, 0x08, 0x20, 0x40,\n  0x81, 0x02, 0x04, 0x10, 0x20, 0x40, 0x81, 0x02, 0x08, 0x11, 0xE0, 0x04,\n  0x06, 0x04, 0x84, 0x44, 0x14, 0x0C, 0xFF, 0xFE, 0x99, 0x90, 0x1F, 0xC0,\n  0x06, 0x00, 0x20, 0x02, 0x1F, 0xE6, 0x04, 0xC0, 0x48, 0x04, 0x81, 0xC7,\n  0xEF, 0x18, 0x00, 0x40, 0x02, 0x00, 0x10, 0x00, 0x80, 0x09, 0xF0, 0x50,\n  0xC3, 0x03, 0x10, 0x08, 0x80, 0x48, 0x02, 0x40, 0x23, 0x03, 0x1C, 0x33,\n  0xBE, 0x00, 0x0F, 0xD3, 0x07, 0x60, 0x24, 0x02, 0x80, 0x08, 0x00, 0x80,\n  0x08, 0x06, 0x41, 0xC3, 0xF0, 0x00, 0x38, 0x00, 0x40, 0x02, 0x00, 0x20,\n  0x01, 0x07, 0xC8, 0x43, 0x44, 0x0E, 0x40, 0x24, 0x01, 0x20, 0x09, 0x00,\n  0xC8, 0x0E, 0x20, 0xE0, 0xF9, 0xC0, 0x0F, 0x86, 0x09, 0x00, 0xA0, 0x1F,\n  0xFF, 0x00, 0x20, 0x06, 0x00, 0x60, 0xC7, 0xE0, 0x01, 0xF8, 0x10, 0x01,\n  0x00, 0x08, 0x00, 0x40, 0x1F, 0xF0, 0x20, 0x01, 0x00, 0x08, 0x00, 0x40,\n  0x04, 0x00, 0x20, 0x01, 0x00, 0x08, 0x03, 0xFE, 0x00, 0x0F, 0x31, 0x86,\n  0x10, 0x10, 0x80, 0x88, 0x04, 0x40, 0x22, 0x02, 0x10, 0x10, 0x43, 0x81,\n  0xE4, 0x00, 0x40, 0x02, 0x00, 0x20, 0x3E, 0x00, 0x1C, 0x00, 0x20, 0x03,\n  0x00, 0x10, 0x00, 0x80, 0x05, 0xF0, 0x30, 0xC3, 0x02, 0x10, 0x10, 0x80,\n  0x84, 0x0C, 0x20, 0x63, 0x02, 0x10, 0x13, 0xE3, 0xE0, 0x01, 0x80, 0x40,\n  0x10, 0x00, 0x00, 0x07, 0xC0, 0x20, 0x08, 0x02, 0x00, 0x80, 0x20, 0x10,\n  0x04, 0x01, 0x0F, 0xFC, 0x00, 0x40, 0x10, 0x0C, 0x00, 0x00, 0x07, 0xF0,\n  0x04, 0x01, 0x00, 0x40, 0x20, 0x08, 0x02, 0x00, 0x80, 0x20, 0x10, 0x04,\n  0x01, 0x00, 0x8F, 0xC0, 0x18, 0x00, 0x80, 0x08, 0x00, 0x80, 0x08, 0x01,\n  0x1F, 0x10, 0x81, 0x30, 0x14, 0x01, 0xC0, 0x26, 0x02, 0x20, 0x21, 0x02,\n  0x08, 0xE1, 0xE0, 0x0F, 0x80, 0x40, 0x10, 0x04, 0x01, 0x00, 0x40, 0x20,\n  0x08, 0x02, 0x00, 0x80, 0x20, 0x10, 0x04, 0x01, 0x0F, 0xFC, 0x3B, 0xB8,\n  0x33, 0x91, 0x08, 0x44, 0x21, 0x10, 0x84, 0x42, 0x12, 0x10, 0x48, 0x42,\n  0x21, 0x0B, 0xC6, 0x30, 0x19, 0xE0, 0xE3, 0x08, 0x11, 0x01, 0x10, 0x11,\n  0x02, 0x10, 0x21, 0x02, 0x20, 0x2F, 0x87, 0x0F, 0x86, 0x19, 0x80, 0xA0,\n  0x18, 0x03, 0x00, 0x60, 0x14, 0x06, 0x61, 0x87, 0xC0, 0x19, 0xF0, 0x28,\n  0x20, 0xC0, 0x42, 0x01, 0x10, 0x04, 0x40, 0x11, 0x00, 0x86, 0x06, 0x14,\n  0x30, 0xCF, 0x02, 0x00, 0x08, 0x00, 0x20, 0x03, 0xF0, 0x00, 0x0F, 0x39,\n  0x85, 0x18, 0x18, 0x80, 0x88, 0x04, 0x40, 0x22, 0x01, 0x18, 0x18, 0x63,\n  0x81, 0xE4, 0x00, 0x20, 0x01, 0x00, 0x10, 0x07, 0xE0, 0x1C, 0x78, 0x2C,\n  0x01, 0x80, 0x18, 0x00, 0x80, 0x04, 0x00, 0x20, 0x02, 0x00, 0x10, 0x07,\n  0xFC, 0x00, 0x0F, 0x44, 0x32, 0x04, 0x80, 0x1E, 0x00, 0x60, 0x0A, 0x02,\n  0xC1, 0x2F, 0x80, 0x10, 0x08, 0x04, 0x02, 0x0F, 0xF9, 0x00, 0x80, 0x40,\n  0x20, 0x20, 0x10, 0x08, 0x04, 0x19, 0xF0, 0xE0, 0xF2, 0x02, 0x40, 0x24,\n  0x02, 0x40, 0x24, 0x06, 0x40, 0x44, 0x04, 0x41, 0xC3, 0xE6, 0xF8, 0xFA,\n  0x01, 0x08, 0x10, 0x41, 0x02, 0x08, 0x10, 0x80, 0x48, 0x02, 0x40, 0x14,\n  0x00, 0xC0, 0x00, 0xE0, 0x7A, 0x01, 0x10, 0x08, 0x8C, 0x84, 0xA4, 0x25,\n  0x21, 0x4A, 0x0A, 0x50, 0x63, 0x02, 0x18, 0x00, 0x1E, 0x3C, 0x20, 0x40,\n  0x46, 0x00, 0xB0, 0x03, 0x00, 0x0E, 0x00, 0xC8, 0x06, 0x10, 0x20, 0x23,\n  0xE3, 0xC0, 0x3C, 0x3C, 0x40, 0x20, 0x81, 0x02, 0x08, 0x08, 0x20, 0x31,\n  0x00, 0x48, 0x01, 0x40, 0x05, 0x00, 0x08, 0x00, 0x40, 0x02, 0x00, 0x08,\n  0x03, 0xF0, 0x00, 0x3F, 0xC4, 0x18, 0x06, 0x01, 0x80, 0x60, 0x10, 0x04,\n  0x01, 0x00, 0x40, 0x9F, 0xF0, 0x06, 0x10, 0x20, 0x41, 0x02, 0x04, 0x08,\n  0x21, 0x80, 0x81, 0x02, 0x08, 0x10, 0x20, 0x40, 0xC0, 0x01, 0x11, 0x12,\n  0x22, 0x24, 0x44, 0x44, 0x88, 0x80, 0x0C, 0x08, 0x10, 0x20, 0x40, 0x82,\n  0x04, 0x08, 0x0C, 0x20, 0x81, 0x02, 0x04, 0x08, 0x21, 0x80, 0x38, 0x28,\n  0x88, 0x0E, 0x00 };\n\nconst GFXglyph FreeMonoOblique12pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,  14,    0,    1 },   // 0x20 ' '\n  {     0,   4,  15,  14,    6,  -14 },   // 0x21 '!'\n  {     8,   8,   7,  14,    5,  -14 },   // 0x22 '\"'\n  {    15,  11,  16,  14,    3,  -14 },   // 0x23 '#'\n  {    37,  10,  18,  14,    4,  -15 },   // 0x24 '$'\n  {    60,  11,  15,  14,    3,  -14 },   // 0x25 '%'\n  {    81,   9,  12,  14,    3,  -11 },   // 0x26 '&'\n  {    95,   3,   7,  14,    8,  -14 },   // 0x27 '''\n  {    98,   5,  18,  14,    8,  -14 },   // 0x28 '('\n  {   110,   5,  18,  14,    4,  -14 },   // 0x29 ')'\n  {   122,   9,   9,  14,    5,  -14 },   // 0x2A '*'\n  {   133,  11,  11,  14,    3,  -11 },   // 0x2B '+'\n  {   149,   6,   7,  14,    3,   -3 },   // 0x2C ','\n  {   155,  11,   1,  14,    3,   -6 },   // 0x2D '-'\n  {   157,   3,   3,  14,    6,   -2 },   // 0x2E '.'\n  {   159,  13,  18,  14,    2,  -15 },   // 0x2F '/'\n  {   189,  10,  15,  14,    4,  -14 },   // 0x30 '0'\n  {   208,   9,  15,  14,    3,  -14 },   // 0x31 '1'\n  {   225,  12,  15,  14,    2,  -14 },   // 0x32 '2'\n  {   248,  11,  15,  14,    3,  -14 },   // 0x33 '3'\n  {   269,  10,  15,  14,    3,  -14 },   // 0x34 '4'\n  {   288,  11,  15,  14,    3,  -14 },   // 0x35 '5'\n  {   309,  11,  15,  14,    4,  -14 },   // 0x36 '6'\n  {   330,  10,  15,  14,    5,  -14 },   // 0x37 '7'\n  {   349,  11,  15,  14,    3,  -14 },   // 0x38 '8'\n  {   370,  11,  15,  14,    3,  -14 },   // 0x39 '9'\n  {   391,   5,  10,  14,    5,   -9 },   // 0x3A ':'\n  {   398,   7,  13,  14,    3,   -9 },   // 0x3B ';'\n  {   410,  12,  11,  14,    3,  -11 },   // 0x3C '<'\n  {   427,  13,   4,  14,    2,   -8 },   // 0x3D '='\n  {   434,  12,  11,  14,    2,  -11 },   // 0x3E '>'\n  {   451,   8,  14,  14,    6,  -13 },   // 0x3F '?'\n  {   465,  10,  16,  14,    3,  -14 },   // 0x40 '@'\n  {   485,  14,  14,  14,    0,  -13 },   // 0x41 'A'\n  {   510,  13,  14,  14,    1,  -13 },   // 0x42 'B'\n  {   533,  12,  14,  14,    3,  -13 },   // 0x43 'C'\n  {   554,  13,  14,  14,    1,  -13 },   // 0x44 'D'\n  {   577,  14,  14,  14,    1,  -13 },   // 0x45 'E'\n  {   602,  14,  14,  14,    1,  -13 },   // 0x46 'F'\n  {   627,  12,  14,  14,    3,  -13 },   // 0x47 'G'\n  {   648,  15,  14,  14,    1,  -13 },   // 0x48 'H'\n  {   675,  11,  14,  14,    3,  -13 },   // 0x49 'I'\n  {   695,  15,  14,  14,    2,  -13 },   // 0x4A 'J'\n  {   722,  15,  14,  14,    1,  -13 },   // 0x4B 'K'\n  {   749,  12,  14,  14,    2,  -13 },   // 0x4C 'L'\n  {   770,  17,  14,  14,    0,  -13 },   // 0x4D 'M'\n  {   800,  15,  14,  14,    1,  -13 },   // 0x4E 'N'\n  {   827,  13,  14,  14,    2,  -13 },   // 0x4F 'O'\n  {   850,  13,  14,  14,    1,  -13 },   // 0x50 'P'\n  {   873,  13,  17,  14,    2,  -13 },   // 0x51 'Q'\n  {   901,  13,  14,  14,    1,  -13 },   // 0x52 'R'\n  {   924,  11,  14,  14,    3,  -13 },   // 0x53 'S'\n  {   944,  12,  14,  14,    4,  -13 },   // 0x54 'T'\n  {   965,  13,  14,  14,    3,  -13 },   // 0x55 'U'\n  {   988,  14,  14,  14,    3,  -13 },   // 0x56 'V'\n  {  1013,  14,  14,  14,    3,  -13 },   // 0x57 'W'\n  {  1038,  15,  14,  14,    1,  -13 },   // 0x58 'X'\n  {  1065,  12,  14,  14,    4,  -13 },   // 0x59 'Y'\n  {  1086,  12,  14,  14,    2,  -13 },   // 0x5A 'Z'\n  {  1107,   7,  18,  14,    6,  -14 },   // 0x5B '['\n  {  1123,   5,  18,  14,    6,  -15 },   // 0x5C '\\'\n  {  1135,   7,  18,  14,    3,  -14 },   // 0x5D ']'\n  {  1151,   9,   6,  14,    5,  -14 },   // 0x5E '^'\n  {  1158,  15,   1,  14,   -1,    3 },   // 0x5F '_'\n  {  1160,   3,   4,  14,    6,  -15 },   // 0x60 '`'\n  {  1162,  12,  10,  14,    2,   -9 },   // 0x61 'a'\n  {  1177,  13,  15,  14,    1,  -14 },   // 0x62 'b'\n  {  1202,  12,  10,  14,    3,   -9 },   // 0x63 'c'\n  {  1217,  13,  15,  14,    2,  -14 },   // 0x64 'd'\n  {  1242,  11,  10,  14,    3,   -9 },   // 0x65 'e'\n  {  1256,  13,  15,  14,    3,  -14 },   // 0x66 'f'\n  {  1281,  13,  14,  14,    3,   -9 },   // 0x67 'g'\n  {  1304,  13,  15,  14,    1,  -14 },   // 0x68 'h'\n  {  1329,  10,  15,  14,    2,  -14 },   // 0x69 'i'\n  {  1348,  10,  19,  14,    2,  -14 },   // 0x6A 'j'\n  {  1372,  12,  15,  14,    2,  -14 },   // 0x6B 'k'\n  {  1395,  10,  15,  14,    2,  -14 },   // 0x6C 'l'\n  {  1414,  14,  10,  14,    0,   -9 },   // 0x6D 'm'\n  {  1432,  12,  10,  14,    1,   -9 },   // 0x6E 'n'\n  {  1447,  11,  10,  14,    3,   -9 },   // 0x6F 'o'\n  {  1461,  14,  14,  14,    0,   -9 },   // 0x70 'p'\n  {  1486,  13,  14,  14,    3,   -9 },   // 0x71 'q'\n  {  1509,  13,  10,  14,    2,   -9 },   // 0x72 'r'\n  {  1526,  10,  10,  14,    3,   -9 },   // 0x73 's'\n  {  1539,   9,  14,  14,    3,  -13 },   // 0x74 't'\n  {  1555,  12,  10,  14,    2,   -9 },   // 0x75 'u'\n  {  1570,  13,  10,  14,    3,   -9 },   // 0x76 'v'\n  {  1587,  13,  10,  14,    3,   -9 },   // 0x77 'w'\n  {  1604,  14,  10,  14,    1,   -9 },   // 0x78 'x'\n  {  1622,  14,  14,  14,    1,   -9 },   // 0x79 'y'\n  {  1647,  11,  10,  14,    3,   -9 },   // 0x7A 'z'\n  {  1661,   7,  18,  14,    5,  -14 },   // 0x7B '{'\n  {  1677,   4,  17,  14,    6,  -13 },   // 0x7C '|'\n  {  1686,   7,  18,  14,    4,  -14 },   // 0x7D '}'\n  {  1702,  11,   3,  14,    3,   -7 } }; // 0x7E '~'\n\nconst GFXfont FreeMonoOblique12pt7b PROGMEM = {\n  (uint8_t  *)FreeMonoOblique12pt7bBitmaps,\n  (GFXglyph *)FreeMonoOblique12pt7bGlyphs,\n  0x20, 0x7E, 24 };\n\n// Approx. 2379 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeMonoOblique18pt7b.h",
    "content": "const uint8_t FreeMonoOblique18pt7bBitmaps[] PROGMEM = {\n  0x00, 0x1C, 0x38, 0x70, 0xC1, 0x83, 0x06, 0x18, 0x30, 0x60, 0xC1, 0x02,\n  0x04, 0x00, 0x00, 0x01, 0xC7, 0x8F, 0x1C, 0x00, 0x78, 0x7B, 0xC3, 0xFC,\n  0x3D, 0xE1, 0xEF, 0x0F, 0x70, 0x73, 0x83, 0x98, 0x18, 0xC0, 0xC6, 0x06,\n  0x00, 0x00, 0x8C, 0x01, 0x18, 0x06, 0x20, 0x08, 0x40, 0x11, 0x80, 0x62,\n  0x00, 0xC4, 0x01, 0x18, 0x02, 0x30, 0x7F, 0xFC, 0x10, 0x80, 0x23, 0x00,\n  0xC4, 0x01, 0x88, 0x3F, 0xFF, 0x04, 0x60, 0x18, 0x80, 0x21, 0x00, 0x46,\n  0x01, 0x88, 0x03, 0x10, 0x04, 0x60, 0x08, 0xC0, 0x31, 0x00, 0x00, 0x30,\n  0x00, 0x20, 0x00, 0x20, 0x00, 0xF9, 0x03, 0x0F, 0x06, 0x03, 0x04, 0x03,\n  0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x04, 0x00, 0x03, 0xC0, 0x00, 0x78,\n  0x00, 0x0C, 0x00, 0x04, 0x00, 0x04, 0x40, 0x04, 0x40, 0x08, 0x40, 0x18,\n  0xF0, 0x60, 0x9F, 0x80, 0x02, 0x00, 0x06, 0x00, 0x04, 0x00, 0x04, 0x00,\n  0x04, 0x00, 0x03, 0xC0, 0x0C, 0x60, 0x08, 0x20, 0x10, 0x20, 0x10, 0x20,\n  0x10, 0x40, 0x18, 0x80, 0x0F, 0x00, 0x00, 0x0F, 0x00, 0x78, 0x07, 0xC0,\n  0x3C, 0x00, 0xE0, 0x00, 0x01, 0xE0, 0x02, 0x18, 0x04, 0x08, 0x08, 0x08,\n  0x08, 0x08, 0x08, 0x10, 0x0C, 0x20, 0x07, 0xC0, 0x01, 0xF0, 0x11, 0x81,\n  0x00, 0x10, 0x00, 0x80, 0x04, 0x00, 0x20, 0x01, 0x80, 0x04, 0x00, 0xF0,\n  0x09, 0x86, 0x84, 0x48, 0x32, 0x40, 0xA2, 0x07, 0x10, 0x30, 0x43, 0x81,\n  0xE7, 0x80, 0x7B, 0xFD, 0xEF, 0x73, 0x98, 0xC6, 0x00, 0x01, 0x02, 0x06,\n  0x0C, 0x0C, 0x18, 0x10, 0x30, 0x30, 0x60, 0x60, 0x60, 0xC0, 0xC0, 0xC0,\n  0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0x40, 0x60, 0x60, 0x20, 0x04, 0x06,\n  0x06, 0x02, 0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x06,\n  0x06, 0x06, 0x0C, 0x0C, 0x0C, 0x18, 0x10, 0x30, 0x60, 0x40, 0xC0, 0x01,\n  0x00, 0x04, 0x00, 0x10, 0x00, 0xC6, 0xE3, 0xF8, 0x7E, 0x00, 0x70, 0x03,\n  0x40, 0x19, 0x80, 0xC2, 0x06, 0x0C, 0x00, 0x00, 0xC0, 0x01, 0x00, 0x02,\n  0x00, 0x04, 0x00, 0x08, 0x00, 0x20, 0x00, 0x40, 0x00, 0x80, 0xFF, 0xFE,\n  0x02, 0x00, 0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x40, 0x00, 0x80, 0x02,\n  0x00, 0x04, 0x00, 0x0F, 0x87, 0x87, 0x83, 0x83, 0xC1, 0xC1, 0xC0, 0xC0,\n  0xE0, 0x60, 0x00, 0xFF, 0xFF, 0x77, 0xFF, 0xF7, 0x00, 0x00, 0x00, 0x60,\n  0x00, 0x08, 0x00, 0x02, 0x00, 0x00, 0xC0, 0x00, 0x30, 0x00, 0x04, 0x00,\n  0x01, 0x80, 0x00, 0x60, 0x00, 0x08, 0x00, 0x03, 0x00, 0x00, 0xC0, 0x00,\n  0x10, 0x00, 0x06, 0x00, 0x01, 0x80, 0x00, 0x20, 0x00, 0x0C, 0x00, 0x03,\n  0x00, 0x00, 0x40, 0x00, 0x18, 0x00, 0x06, 0x00, 0x00, 0x80, 0x00, 0x20,\n  0x00, 0x0C, 0x00, 0x03, 0x00, 0x00, 0x40, 0x00, 0x08, 0x00, 0x00, 0x01,\n  0xF0, 0x18, 0x60, 0x80, 0x86, 0x01, 0x10, 0x04, 0x80, 0x12, 0x00, 0x50,\n  0x01, 0x40, 0x0D, 0x00, 0x24, 0x00, 0xA0, 0x02, 0x80, 0x1A, 0x00, 0x48,\n  0x01, 0x20, 0x0C, 0x80, 0x22, 0x01, 0x84, 0x0C, 0x18, 0x60, 0x3E, 0x00,\n  0x00, 0x60, 0x07, 0x00, 0x68, 0x06, 0x40, 0xE4, 0x04, 0x20, 0x01, 0x00,\n  0x08, 0x00, 0x40, 0x04, 0x00, 0x20, 0x01, 0x00, 0x08, 0x00, 0x80, 0x04,\n  0x00, 0x20, 0x01, 0x00, 0x08, 0x00, 0x80, 0x04, 0x0F, 0xFF, 0x80, 0x00,\n  0x3C, 0x00, 0x61, 0x80, 0x40, 0x40, 0x40, 0x10, 0x60, 0x08, 0x00, 0x04,\n  0x00, 0x02, 0x00, 0x02, 0x00, 0x03, 0x00, 0x03, 0x00, 0x07, 0x00, 0x07,\n  0x00, 0x06, 0x00, 0x06, 0x00, 0x0E, 0x00, 0x0E, 0x00, 0x0C, 0x00, 0x0C,\n  0x00, 0x1C, 0x01, 0x1C, 0x00, 0x8F, 0xFF, 0xC0, 0x00, 0xFC, 0x03, 0x06,\n  0x06, 0x03, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x02, 0x00, 0x02,\n  0x00, 0x0C, 0x00, 0xF0, 0x00, 0x18, 0x00, 0x04, 0x00, 0x02, 0x00, 0x02,\n  0x00, 0x02, 0x00, 0x02, 0x00, 0x04, 0x00, 0x04, 0x40, 0x18, 0x70, 0x30,\n  0x0F, 0xC0, 0x00, 0x1C, 0x00, 0xD0, 0x06, 0x80, 0x32, 0x00, 0x88, 0x04,\n  0x20, 0x30, 0x81, 0x84, 0x04, 0x10, 0x20, 0x41, 0x81, 0x0C, 0x08, 0x60,\n  0x21, 0x00, 0x8F, 0xFF, 0x80, 0x18, 0x00, 0x40, 0x01, 0x00, 0x04, 0x00,\n  0x10, 0x07, 0xE0, 0x03, 0xFF, 0x03, 0x00, 0x01, 0x80, 0x00, 0x80, 0x00,\n  0x40, 0x00, 0x20, 0x00, 0x30, 0x00, 0x1B, 0xE0, 0x0E, 0x0C, 0x00, 0x02,\n  0x00, 0x00, 0x80, 0x00, 0x40, 0x00, 0x20, 0x00, 0x10, 0x00, 0x08, 0x00,\n  0x08, 0x00, 0x04, 0x60, 0x04, 0x18, 0x04, 0x06, 0x0C, 0x00, 0xF8, 0x00,\n  0x00, 0x3F, 0x00, 0xC0, 0x03, 0x00, 0x04, 0x00, 0x08, 0x00, 0x10, 0x00,\n  0x30, 0x00, 0x20, 0x00, 0x40, 0x00, 0x43, 0xE0, 0x4C, 0x30, 0xB0, 0x18,\n  0xE0, 0x08, 0xC0, 0x08, 0x80, 0x08, 0x80, 0x08, 0x80, 0x10, 0xC0, 0x10,\n  0x40, 0x20, 0x20, 0xC0, 0x1F, 0x00, 0xFF, 0xFC, 0x00, 0xE0, 0x04, 0x00,\n  0x60, 0x02, 0x00, 0x30, 0x01, 0x00, 0x18, 0x00, 0x80, 0x0C, 0x00, 0x40,\n  0x06, 0x00, 0x20, 0x03, 0x00, 0x10, 0x01, 0x80, 0x08, 0x00, 0xC0, 0x04,\n  0x00, 0x60, 0x02, 0x00, 0x00, 0x00, 0xF0, 0x06, 0x18, 0x10, 0x18, 0x40,\n  0x11, 0x00, 0x22, 0x00, 0x44, 0x00, 0x88, 0x02, 0x18, 0x08, 0x18, 0x60,\n  0x1F, 0x80, 0xC1, 0x82, 0x01, 0x88, 0x01, 0x20, 0x02, 0x40, 0x04, 0x80,\n  0x09, 0x00, 0x23, 0x00, 0x83, 0x06, 0x01, 0xF0, 0x00, 0x00, 0xF0, 0x06,\n  0x18, 0x10, 0x10, 0x40, 0x30, 0x80, 0x22, 0x00, 0x44, 0x00, 0x88, 0x03,\n  0x10, 0x0E, 0x30, 0x34, 0x30, 0xD0, 0x3E, 0x20, 0x00, 0x40, 0x01, 0x00,\n  0x02, 0x00, 0x08, 0x00, 0x20, 0x00, 0xC0, 0x02, 0x00, 0x18, 0x0F, 0xC0,\n  0x00, 0x1C, 0x7C, 0xF9, 0xF1, 0xC0, 0x00, 0x00, 0x00, 0x01, 0xC7, 0xCF,\n  0x9F, 0x1C, 0x00, 0x01, 0xC0, 0x7C, 0x0F, 0x81, 0xF0, 0x1C, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x07, 0x81, 0xE0, 0x3C, 0x0F, 0x01,\n  0xC0, 0x70, 0x0E, 0x03, 0x80, 0x60, 0x00, 0x00, 0x01, 0x80, 0x03, 0x80,\n  0x07, 0x00, 0x0E, 0x00, 0x1C, 0x00, 0x38, 0x00, 0x70, 0x00, 0xE0, 0x00,\n  0xE0, 0x00, 0x1C, 0x00, 0x07, 0x00, 0x00, 0xE0, 0x00, 0x38, 0x00, 0x07,\n  0x00, 0x00, 0xE0, 0x00, 0x38, 0x7F, 0xFF, 0xE0, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0x01, 0xFF, 0xFF, 0x80, 0x18, 0x00, 0x03, 0x80,\n  0x00, 0x38, 0x00, 0x07, 0x00, 0x00, 0x70, 0x00, 0x0E, 0x00, 0x00, 0xE0,\n  0x00, 0x0E, 0x00, 0x03, 0x80, 0x03, 0x80, 0x03, 0x80, 0x03, 0x80, 0x03,\n  0x80, 0x03, 0x80, 0x03, 0x80, 0x03, 0x80, 0x00, 0x1F, 0xCE, 0x06, 0x80,\n  0x38, 0x01, 0x80, 0x10, 0x01, 0x00, 0x20, 0x04, 0x01, 0x80, 0xF0, 0x18,\n  0x01, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x0F, 0x80, 0xF8,\n  0x07, 0x00, 0x01, 0xF0, 0x0C, 0x30, 0x30, 0x30, 0x40, 0x21, 0x00, 0x44,\n  0x00, 0x88, 0x01, 0x10, 0x1E, 0x40, 0xC4, 0x86, 0x11, 0x08, 0x22, 0x20,\n  0x48, 0x40, 0x90, 0x82, 0x21, 0x84, 0x40, 0xFC, 0x80, 0x01, 0x00, 0x02,\n  0x00, 0x04, 0x00, 0x04, 0x00, 0x0C, 0x18, 0x07, 0xC0, 0x00, 0x01, 0xFE,\n  0x00, 0x00, 0x68, 0x00, 0x06, 0x40, 0x00, 0x32, 0x00, 0x03, 0x10, 0x00,\n  0x10, 0x80, 0x01, 0x84, 0x00, 0x18, 0x10, 0x00, 0xC0, 0x80, 0x0C, 0x04,\n  0x00, 0x60, 0x20, 0x06, 0x01, 0x00, 0x3F, 0xFC, 0x02, 0x00, 0x20, 0x10,\n  0x01, 0x01, 0x00, 0x08, 0x08, 0x00, 0x40, 0x80, 0x02, 0x0C, 0x00, 0x09,\n  0xFC, 0x07, 0xF0, 0x0F, 0xFF, 0x00, 0x40, 0x60, 0x20, 0x0C, 0x08, 0x01,\n  0x02, 0x00, 0x40, 0x80, 0x10, 0x40, 0x08, 0x10, 0x06, 0x04, 0x03, 0x01,\n  0xFF, 0x80, 0x40, 0x38, 0x20, 0x02, 0x08, 0x00, 0x42, 0x00, 0x10, 0x80,\n  0x04, 0x40, 0x01, 0x10, 0x00, 0x84, 0x00, 0x41, 0x00, 0x23, 0xFF, 0xF0,\n  0x00, 0xFC, 0x40, 0xC1, 0xF0, 0xC0, 0x1C, 0x60, 0x06, 0x10, 0x00, 0x88,\n  0x00, 0x24, 0x00, 0x01, 0x00, 0x00, 0x40, 0x00, 0x30, 0x00, 0x08, 0x00,\n  0x02, 0x00, 0x00, 0x80, 0x00, 0x20, 0x00, 0x08, 0x00, 0x03, 0x00, 0x00,\n  0x40, 0x06, 0x08, 0x03, 0x01, 0x83, 0x80, 0x3F, 0x00, 0x0F, 0xFE, 0x00,\n  0x80, 0xC0, 0x20, 0x18, 0x10, 0x02, 0x04, 0x00, 0x41, 0x00, 0x10, 0x40,\n  0x04, 0x20, 0x01, 0x08, 0x00, 0x42, 0x00, 0x10, 0x80, 0x08, 0x20, 0x02,\n  0x10, 0x00, 0x84, 0x00, 0x21, 0x00, 0x10, 0x40, 0x08, 0x20, 0x06, 0x08,\n  0x03, 0x02, 0x01, 0x83, 0xFF, 0x80, 0x0F, 0xFF, 0xE0, 0x10, 0x02, 0x02,\n  0x00, 0x60, 0x20, 0x06, 0x02, 0x00, 0x60, 0x20, 0x00, 0x04, 0x00, 0x00,\n  0x40, 0x80, 0x04, 0x10, 0x00, 0x7F, 0x00, 0x04, 0x10, 0x00, 0x81, 0x00,\n  0x08, 0x00, 0x00, 0x80, 0x00, 0x08, 0x00, 0x81, 0x00, 0x08, 0x10, 0x00,\n  0x81, 0x00, 0x18, 0x10, 0x01, 0x8F, 0xFF, 0xF0, 0x0F, 0xFF, 0xF0, 0x10,\n  0x03, 0x02, 0x00, 0x30, 0x20, 0x03, 0x02, 0x00, 0x20, 0x20, 0x00, 0x04,\n  0x00, 0x00, 0x40, 0x80, 0x04, 0x10, 0x00, 0x7F, 0x00, 0x04, 0x10, 0x00,\n  0x81, 0x00, 0x08, 0x00, 0x00, 0x80, 0x00, 0x08, 0x00, 0x01, 0x00, 0x00,\n  0x10, 0x00, 0x01, 0x00, 0x00, 0x10, 0x00, 0x0F, 0xF8, 0x00, 0x00, 0xFE,\n  0x40, 0xC0, 0xF0, 0x40, 0x1C, 0x20, 0x03, 0x10, 0x00, 0x88, 0x00, 0x02,\n  0x00, 0x01, 0x00, 0x00, 0x40, 0x00, 0x10, 0x00, 0x08, 0x00, 0x02, 0x01,\n  0xFE, 0x80, 0x02, 0x20, 0x00, 0x88, 0x00, 0x22, 0x00, 0x08, 0x40, 0x04,\n  0x18, 0x01, 0x03, 0x81, 0xC0, 0x3F, 0x80, 0x07, 0xE1, 0xF8, 0x08, 0x02,\n  0x00, 0x80, 0x10, 0x04, 0x00, 0x80, 0x20, 0x04, 0x01, 0x00, 0x20, 0x18,\n  0x02, 0x00, 0x80, 0x10, 0x04, 0x00, 0x80, 0x3F, 0xFC, 0x01, 0x00, 0x60,\n  0x10, 0x02, 0x00, 0x80, 0x10, 0x04, 0x00, 0x80, 0x20, 0x04, 0x02, 0x00,\n  0x40, 0x10, 0x02, 0x00, 0x80, 0x10, 0x04, 0x00, 0x81, 0xF8, 0x3F, 0x00,\n  0x0F, 0xFF, 0x80, 0x10, 0x00, 0x08, 0x00, 0x08, 0x00, 0x04, 0x00, 0x02,\n  0x00, 0x01, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, 0x40, 0x00, 0x20, 0x00,\n  0x10, 0x00, 0x08, 0x00, 0x08, 0x00, 0x04, 0x00, 0x02, 0x00, 0x01, 0x00,\n  0x01, 0x00, 0x00, 0x80, 0x1F, 0xFF, 0x00, 0x00, 0xFF, 0xF0, 0x00, 0x20,\n  0x00, 0x02, 0x00, 0x00, 0x20, 0x00, 0x02, 0x00, 0x00, 0x20, 0x00, 0x04,\n  0x00, 0x00, 0x40, 0x00, 0x04, 0x00, 0x00, 0x40, 0x00, 0x0C, 0x04, 0x00,\n  0x80, 0x40, 0x08, 0x08, 0x00, 0x80, 0x80, 0x08, 0x08, 0x01, 0x00, 0x80,\n  0x10, 0x0C, 0x02, 0x00, 0x60, 0xC0, 0x01, 0xF0, 0x00, 0x0F, 0xE1, 0xF8,\n  0x08, 0x03, 0x00, 0x80, 0x60, 0x04, 0x06, 0x00, 0x20, 0x60, 0x01, 0x06,\n  0x00, 0x10, 0xC0, 0x00, 0x8C, 0x00, 0x04, 0xC0, 0x00, 0x2F, 0x80, 0x01,\n  0x8E, 0x00, 0x18, 0x30, 0x00, 0x80, 0xC0, 0x04, 0x06, 0x00, 0x20, 0x10,\n  0x02, 0x00, 0xC0, 0x10, 0x06, 0x00, 0x80, 0x30, 0x04, 0x00, 0x81, 0xFC,\n  0x07, 0x80, 0x07, 0xFC, 0x00, 0x10, 0x00, 0x08, 0x00, 0x02, 0x00, 0x00,\n  0x80, 0x00, 0x20, 0x00, 0x08, 0x00, 0x04, 0x00, 0x01, 0x00, 0x00, 0x40,\n  0x00, 0x10, 0x00, 0x08, 0x00, 0x02, 0x00, 0x00, 0x80, 0x10, 0x20, 0x04,\n  0x08, 0x01, 0x04, 0x00, 0x81, 0x00, 0x20, 0x40, 0x0B, 0xFF, 0xFE, 0x0F,\n  0x00, 0x1E, 0x03, 0x00, 0x38, 0x05, 0x00, 0x68, 0x04, 0x80, 0x68, 0x04,\n  0x80, 0xC8, 0x04, 0x80, 0x90, 0x04, 0x81, 0x90, 0x08, 0x43, 0x10, 0x08,\n  0x42, 0x10, 0x08, 0x46, 0x10, 0x08, 0x4C, 0x20, 0x10, 0x2C, 0x20, 0x10,\n  0x38, 0x20, 0x10, 0x30, 0x20, 0x10, 0x00, 0x40, 0x10, 0x00, 0x40, 0x20,\n  0x00, 0x40, 0x20, 0x00, 0x40, 0x20, 0x00, 0x40, 0xFC, 0x07, 0xE0, 0x1F,\n  0x01, 0xFC, 0x0C, 0x00, 0x80, 0x78, 0x02, 0x01, 0xE0, 0x18, 0x04, 0x80,\n  0x60, 0x13, 0x01, 0x00, 0x4C, 0x04, 0x03, 0x18, 0x10, 0x0C, 0x60, 0xC0,\n  0x20, 0x83, 0x00, 0x83, 0x08, 0x06, 0x0C, 0x20, 0x18, 0x18, 0x80, 0x40,\n  0x66, 0x01, 0x00, 0x98, 0x04, 0x03, 0x40, 0x30, 0x0D, 0x00, 0xC0, 0x14,\n  0x02, 0x00, 0x70, 0x3F, 0x80, 0xC0, 0x00, 0xF8, 0x01, 0x83, 0x01, 0x00,\n  0xC1, 0x00, 0x21, 0x00, 0x19, 0x00, 0x04, 0x80, 0x02, 0x80, 0x01, 0x40,\n  0x00, 0xC0, 0x00, 0x60, 0x00, 0x30, 0x00, 0x28, 0x00, 0x14, 0x00, 0x12,\n  0x00, 0x09, 0x80, 0x08, 0x40, 0x08, 0x30, 0x08, 0x0C, 0x18, 0x01, 0xF0,\n  0x00, 0x0F, 0xFE, 0x00, 0x40, 0x60, 0x20, 0x0C, 0x08, 0x01, 0x02, 0x00,\n  0x40, 0x80, 0x10, 0x40, 0x04, 0x10, 0x02, 0x04, 0x01, 0x01, 0x01, 0x80,\n  0x7F, 0x80, 0x20, 0x00, 0x08, 0x00, 0x02, 0x00, 0x00, 0x80, 0x00, 0x40,\n  0x00, 0x10, 0x00, 0x04, 0x00, 0x01, 0x00, 0x03, 0xFE, 0x00, 0x00, 0xF8,\n  0x01, 0x83, 0x01, 0x00, 0xC1, 0x00, 0x21, 0x00, 0x19, 0x00, 0x05, 0x00,\n  0x02, 0x80, 0x01, 0x40, 0x00, 0xC0, 0x00, 0x60, 0x00, 0x30, 0x00, 0x28,\n  0x00, 0x14, 0x00, 0x12, 0x00, 0x09, 0x80, 0x08, 0x40, 0x08, 0x30, 0x08,\n  0x0C, 0x18, 0x03, 0xF0, 0x00, 0xC0, 0x01, 0xC0, 0x01, 0xFE, 0x18, 0xC0,\n  0xF0, 0x0F, 0xFE, 0x00, 0x40, 0x60, 0x20, 0x0C, 0x08, 0x01, 0x02, 0x00,\n  0x40, 0x80, 0x10, 0x40, 0x04, 0x10, 0x02, 0x04, 0x01, 0x01, 0x01, 0x80,\n  0x7F, 0x80, 0x20, 0x60, 0x08, 0x0C, 0x02, 0x03, 0x80, 0x80, 0x60, 0x40,\n  0x18, 0x10, 0x03, 0x04, 0x00, 0xC1, 0x00, 0x1B, 0xF8, 0x07, 0x00, 0x7E,\n  0x40, 0x60, 0xF0, 0x20, 0x1C, 0x10, 0x02, 0x08, 0x00, 0x82, 0x00, 0x00,\n  0x80, 0x00, 0x30, 0x00, 0x06, 0x00, 0x00, 0xF8, 0x00, 0x03, 0xC0, 0x00,\n  0x18, 0x00, 0x01, 0x00, 0x00, 0x44, 0x00, 0x11, 0x00, 0x04, 0x40, 0x02,\n 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 0x80, 0x08, 0x80, 0x38, 0xC0, 0xE8, 0x3F, 0x0F, 0x0F, 0x00, 0x00, 0x20,\n  0x00, 0x04, 0x00, 0x01, 0x80, 0x00, 0x30, 0x00, 0x04, 0x00, 0x00, 0x87,\n  0xC0, 0x13, 0x0C, 0x06, 0x80, 0x40, 0xE0, 0x0C, 0x18, 0x00, 0x82, 0x00,\n  0x10, 0xC0, 0x02, 0x10, 0x00, 0x42, 0x00, 0x08, 0x40, 0x02, 0x08, 0x00,\n  0x43, 0x80, 0x10, 0x70, 0x04, 0x09, 0x83, 0x0F, 0x1F, 0x80, 0x01, 0xFC,\n  0x83, 0x03, 0xC6, 0x00, 0xE4, 0x00, 0x22, 0x00, 0x12, 0x00, 0x01, 0x00,\n  0x01, 0x00, 0x00, 0x80, 0x00, 0x40, 0x00, 0x20, 0x00, 0x18, 0x00, 0x64,\n  0x00, 0x61, 0x81, 0xC0, 0x7F, 0x00, 0x00, 0x03, 0xC0, 0x00, 0x30, 0x00,\n  0x0C, 0x00, 0x02, 0x00, 0x00, 0x80, 0x00, 0x60, 0x3F, 0x18, 0x10, 0x64,\n  0x18, 0x0D, 0x08, 0x01, 0xC2, 0x00, 0x71, 0x00, 0x0C, 0x80, 0x02, 0x20,\n  0x00, 0x88, 0x00, 0x62, 0x00, 0x18, 0x80, 0x0E, 0x20, 0x03, 0x04, 0x03,\n  0x40, 0xC1, 0xB0, 0x1F, 0x8F, 0x00, 0x01, 0xF0, 0x0E, 0x0C, 0x18, 0x06,\n  0x30, 0x02, 0x60, 0x01, 0x40, 0x01, 0xC0, 0x01, 0xFF, 0xFF, 0x80, 0x00,\n  0x80, 0x00, 0x80, 0x00, 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0x00, 0x08, 0x00, 0x40,\n  0x02, 0x00, 0xD8, 0x1C, 0x3F, 0x00, 0xF0, 0x1E, 0x20, 0x04, 0x80, 0x09,\n  0x00, 0x12, 0x00, 0x24, 0x00, 0xC8, 0x01, 0x20, 0x02, 0x40, 0x04, 0x80,\n  0x09, 0x00, 0x12, 0x00, 0x64, 0x03, 0x8C, 0x1D, 0x0F, 0xC3, 0x80, 0xFE,\n  0x0F, 0xE6, 0x00, 0x20, 0x40, 0x08, 0x08, 0x03, 0x01, 0x80, 0x40, 0x30,\n  0x18, 0x06, 0x02, 0x00, 0x40, 0x80, 0x08, 0x30, 0x01, 0x84, 0x00, 0x31,\n  0x80, 0x02, 0x20, 0x00, 0x48, 0x00, 0x09, 0x00, 0x01, 0xC0, 0x00, 0xF8,\n  0x0F, 0xA0, 0x01, 0x90, 0x00, 0x88, 0x40, 0xC4, 0x30, 0x42, 0x18, 0x61,\n  0x1A, 0x20, 0x8D, 0x10, 0x4C, 0x98, 0x26, 0x48, 0x16, 0x2C, 0x0B, 0x14,\n  0x07, 0x0A, 0x03, 0x07, 0x01, 0x81, 0x00, 0x0F, 0x83, 0xE0, 0xC0, 0x18,\n  0x0C, 0x0C, 0x01, 0x83, 0x00, 0x18, 0xC0, 0x01, 0xB0, 0x00, 0x1C, 0x00,\n  0x03, 0x00, 0x00, 0xF0, 0x00, 0x63, 0x00, 0x18, 0x30, 0x06, 0x06, 0x01,\n  0x80, 0x60, 0x60, 0x06, 0x3F, 0x07, 0xE0, 0x0F, 0xC0, 0xF8, 0x30, 0x01,\n  0x00, 0x80, 0x18, 0x04, 0x00, 0x80, 0x30, 0x0C, 0x01, 0x80, 0xC0, 0x04,\n  0x04, 0x00, 0x30, 0x60, 0x01, 0x86, 0x00, 0x04, 0x20, 0x00, 0x23, 0x00,\n  0x01, 0xB0, 0x00, 0x0D, 0x00, 0x00, 0x38, 0x00, 0x01, 0x80, 0x00, 0x08,\n  0x00, 0x00, 0xC0, 0x00, 0x04, 0x00, 0x00, 0x60, 0x00, 0x06, 0x00, 0x00,\n  0x20, 0x00, 0x7F, 0xE0, 0x00, 0x1F, 0xFF, 0x10, 0x06, 0x10, 0x0C, 0x10,\n  0x18, 0x00, 0x30, 0x00, 0x60, 0x00, 0xC0, 0x01, 0x80, 0x03, 0x00, 0x06,\n  0x00, 0x0C, 0x00, 0x18, 0x04, 0x30, 0x0C, 0x60, 0x0C, 0xFF, 0xF8, 0x00,\n  0xE0, 0x20, 0x08, 0x01, 0x00, 0x20, 0x04, 0x01, 0x00, 0x20, 0x04, 0x00,\n  0x80, 0x20, 0x08, 0x0E, 0x00, 0x60, 0x04, 0x00, 0x80, 0x10, 0x02, 0x00,\n  0x40, 0x08, 0x02, 0x00, 0x40, 0x08, 0x01, 0x00, 0x18, 0x00, 0x00, 0x10,\n  0xC3, 0x08, 0x20, 0x86, 0x18, 0x41, 0x04, 0x30, 0xC2, 0x08, 0x21, 0x86,\n  0x10, 0x43, 0x0C, 0x20, 0x06, 0x00, 0x40, 0x10, 0x04, 0x01, 0x00, 0x40,\n  0x10, 0x04, 0x02, 0x00, 0x80, 0x20, 0x0C, 0x01, 0xC0, 0xC0, 0x40, 0x10,\n  0x04, 0x03, 0x00, 0x80, 0x20, 0x08, 0x02, 0x01, 0x00, 0xC0, 0xE0, 0x00,\n  0x1E, 0x02, 0x66, 0x0D, 0x86, 0x16, 0x06, 0x48, 0x07, 0x00 };\n\nconst GFXglyph FreeMonoOblique18pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,  21,    0,    1 },   // 0x20 ' '\n  {     0,   7,  22,  21,    9,  -21 },   // 0x21 '!'\n  {    20,  13,  10,  21,    7,  -20 },   // 0x22 '\"'\n  {    37,  15,  24,  21,    5,  -21 },   // 0x23 '#'\n  {    82,  16,  26,  21,    4,  -22 },   // 0x24 '$'\n  {   134,  16,  21,  21,    5,  -20 },   // 0x25 '%'\n  {   176,  13,  18,  21,    5,  -17 },   // 0x26 '&'\n  {   206,   5,  10,  21,   12,  -20 },   // 0x27 '''\n  {   213,   8,  25,  21,   12,  -20 },   // 0x28 '('\n  {   238,   8,  25,  21,    5,  -20 },   // 0x29 ')'\n  {   263,  14,  11,  21,    7,  -19 },   // 0x2A '*'\n  {   283,  15,  17,  21,    5,  -17 },   // 0x2B '+'\n  {   315,   9,  10,  21,    4,   -4 },   // 0x2C ','\n  {   327,  16,   1,  21,    5,   -9 },   // 0x2D '-'\n  {   329,   5,   5,  21,    8,   -4 },   // 0x2E '.'\n  {   333,  19,  26,  21,    3,  -22 },   // 0x2F '/'\n  {   395,  14,  21,  21,    5,  -20 },   // 0x30 '0'\n  {   432,  13,  21,  21,    4,  -20 },   // 0x31 '1'\n  {   467,  17,  21,  21,    3,  -20 },   // 0x32 '2'\n  {   512,  16,  21,  21,    3,  -20 },   // 0x33 '3'\n  {   554,  14,  21,  21,    5,  -20 },   // 0x34 '4'\n  {   591,  17,  21,  21,    4,  -20 },   // 0x35 '5'\n  {   636,  16,  21,  21,    6,  -20 },   // 0x36 '6'\n  {   678,  13,  21,  21,    8,  -20 },   // 0x37 '7'\n  {   713,  15,  21,  21,    5,  -20 },   // 0x38 '8'\n  {   753,  15,  21,  21,    5,  -20 },   // 0x39 '9'\n  {   793,   7,  15,  21,    8,  -14 },   // 0x3A ':'\n  {   807,  11,  20,  21,    4,  -14 },   // 0x3B ';'\n  {   835,  17,  16,  21,    5,  -17 },   // 0x3C '<'\n  {   869,  19,   6,  21,    3,  -12 },   // 0x3D '='\n  {   884,  18,  16,  21,    3,  -17 },   // 0x3E '>'\n  {   920,  12,  20,  21,    8,  -19 },   // 0x3F '?'\n  {   950,  15,  23,  21,    5,  -20 },   // 0x40 '@'\n  {   994,  21,  20,  21,    0,  -19 },   // 0x41 'A'\n  {  1047,  18,  20,  21,    2,  -19 },   // 0x42 'B'\n  {  1092,  18,  20,  21,    4,  -19 },   // 0x43 'C'\n  {  1137,  18,  20,  21,    2,  -19 },   // 0x44 'D'\n  {  1182,  20,  20,  21,    2,  -19 },   // 0x45 'E'\n  {  1232,  20,  20,  21,    2,  -19 },   // 0x46 'F'\n  {  1282,  18,  20,  21,    4,  -19 },   // 0x47 'G'\n  {  1327,  21,  20,  21,    2,  -19 },   // 0x48 'H'\n  {  1380,  17,  20,  21,    4,  -19 },   // 0x49 'I'\n  {  1423,  20,  20,  21,    4,  -19 },   // 0x4A 'J'\n  {  1473,  21,  20,  21,    2,  -19 },   // 0x4B 'K'\n  {  1526,  18,  20,  21,    2,  -19 },   // 0x4C 'L'\n  {  1571,  24,  20,  21,    1,  -19 },   // 0x4D 'M'\n  {  1631,  22,  20,  21,    2,  -19 },   // 0x4E 'N'\n  {  1686,  17,  20,  21,    4,  -19 },   // 0x4F 'O'\n  {  1729,  18,  20,  21,    2,  -19 },   // 0x50 'P'\n  {  1774,  17,  24,  21,    4,  -19 },   // 0x51 'Q'\n  {  1825,  18,  20,  21,    2,  -19 },   // 0x52 'R'\n  {  1870,  18,  20,  21,    3,  -19 },   // 0x53 'S'\n  {  1915,  17,  20,  21,    5,  -19 },   // 0x54 'T'\n  {  1958,  18,  20,  21,    5,  -19 },   // 0x55 'U'\n  {  2003,  21,  20,  21,    4,  -19 },   // 0x56 'V'\n  {  2056,  20,  20,  21,    4,  -19 },   // 0x57 'W'\n  {  2106,  21,  20,  21,    2,  -19 },   // 0x58 'X'\n  {  2159,  18,  20,  21,    5,  -19 },   // 0x59 'Y'\n  {  2204,  17,  20,  21,    4,  -19 },   // 0x5A 'Z'\n  {  2247,  11,  25,  21,    9,  -20 },   // 0x5B '['\n  {  2282,   8,  27,  21,    9,  -22 },   // 0x5C '\\'\n  {  2309,  11,  25,  21,    5,  -20 },   // 0x5D ']'\n  {  2344,  13,   9,  21,    7,  -20 },   // 0x5E '^'\n  {  2359,  21,   1,  21,   -1,    4 },   // 0x5F '_'\n  {  2362,   5,   5,  21,    9,  -21 },   // 0x60 '`'\n  {  2366,  16,  15,  21,    3,  -14 },   // 0x61 'a'\n  {  2396,  19,  21,  21,    1,  -20 },   // 0x62 'b'\n  {  2446,  17,  15,  21,    4,  -14 },   // 0x63 'c'\n  {  2478,  18,  21,  21,    4,  -20 },   // 0x64 'd'\n  {  2526,  16,  15,  21,    4,  -14 },   // 0x65 'e'\n  {  2556,  19,  21,  21,    4,  -20 },   // 0x66 'f'\n  {  2606,  19,  22,  21,    4,  -14 },   // 0x67 'g'\n  {  2659,  18,  21,  21,    2,  -20 },   // 0x68 'h'\n  {  2707,  15,  22,  21,    3,  -21 },   // 0x69 'i'\n  {  2749,  15,  29,  21,    3,  -21 },   // 0x6A 'j'\n  {  2804,  18,  21,  21,    2,  -20 },   // 0x6B 'k'\n  {  2852,  15,  21,  21,    3,  -20 },   // 0x6C 'l'\n  {  2892,  20,  15,  21,    1,  -14 },   // 0x6D 'm'\n  {  2930,  17,  15,  21,    2,  -14 },   // 0x6E 'n'\n  {  2962,  16,  15,  21,    4,  -14 },   // 0x6F 'o'\n  {  2992,  20,  22,  21,    0,  -14 },   // 0x70 'p'\n  {  3047,  19,  22,  21,    4,  -14 },   // 0x71 'q'\n  {  3100,  19,  15,  21,    3,  -14 },   // 0x72 'r'\n  {  3136,  15,  15,  21,    4,  -14 },   // 0x73 's'\n  {  3165,  13,  20,  21,    5,  -19 },   // 0x74 't'\n  {  3198,  15,  15,  21,    4,  -14 },   // 0x75 'u'\n  {  3227,  19,  15,  21,    4,  -14 },   // 0x76 'v'\n  {  3263,  17,  15,  21,    5,  -14 },   // 0x77 'w'\n  {  3295,  19,  15,  21,    2,  -14 },   // 0x78 'x'\n  {  3331,  21,  22,  21,    1,  -14 },   // 0x79 'y'\n  {  3389,  16,  15,  21,    4,  -14 },   // 0x7A 'z'\n  {  3419,  11,  25,  21,    8,  -20 },   // 0x7B '{'\n  {  3454,   6,  24,  21,    9,  -19 },   // 0x7C '|'\n  {  3472,  10,  25,  21,    6,  -20 },   // 0x7D '}'\n  {  3504,  15,   5,  21,    5,  -11 } }; // 0x7E '~'\n\nconst GFXfont FreeMonoOblique18pt7b PROGMEM = {\n  (uint8_t  *)FreeMonoOblique18pt7bBitmaps,\n  (GFXglyph *)FreeMonoOblique18pt7bGlyphs,\n  0x20, 0x7E, 35 };\n\n// Approx. 4186 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeMonoOblique24pt7b.h",
    "content": "const uint8_t FreeMonoOblique24pt7bBitmaps[] PROGMEM = {\n  0x01, 0xC0, 0xF0, 0x3C, 0x0E, 0x03, 0x81, 0xE0, 0x78, 0x1C, 0x07, 0x01,\n  0xC0, 0xE0, 0x38, 0x0E, 0x03, 0x00, 0xC0, 0x70, 0x1C, 0x06, 0x01, 0x80,\n  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x0F, 0x83, 0xE0, 0xF8,\n  0x1C, 0x00, 0x7E, 0x3F, 0x7E, 0x3F, 0x7C, 0x3E, 0x7C, 0x3E, 0x7C, 0x3E,\n  0x78, 0x3C, 0xF8, 0x7C, 0xF0, 0x78, 0xF0, 0x78, 0xF0, 0x78, 0xE0, 0x70,\n  0xE0, 0x70, 0xE0, 0x70, 0xC0, 0x60, 0x00, 0x18, 0x30, 0x00, 0x61, 0x80,\n  0x01, 0x86, 0x00, 0x04, 0x18, 0x00, 0x30, 0xC0, 0x00, 0xC3, 0x00, 0x03,\n  0x0C, 0x00, 0x18, 0x30, 0x00, 0x61, 0x80, 0x01, 0x86, 0x00, 0x06, 0x18,\n  0x07, 0xFF, 0xFF, 0x1F, 0xFF, 0xFC, 0x03, 0x0C, 0x00, 0x18, 0x30, 0x00,\n  0x61, 0x80, 0x01, 0x86, 0x00, 0x06, 0x18, 0x00, 0x30, 0xC0, 0x1F, 0xFF,\n  0xF8, 0x7F, 0xFF, 0xE0, 0x18, 0x30, 0x00, 0x61, 0x80, 0x01, 0x86, 0x00,\n  0x06, 0x18, 0x00, 0x30, 0x40, 0x00, 0xC3, 0x00, 0x03, 0x0C, 0x00, 0x18,\n  0x30, 0x00, 0x61, 0x80, 0x01, 0x86, 0x00, 0x06, 0x18, 0x00, 0x00, 0x03,\n  0x00, 0x00, 0x18, 0x00, 0x00, 0x80, 0x00, 0x3F, 0x00, 0x07, 0xFD, 0x80,\n  0x70, 0x7C, 0x06, 0x00, 0xE0, 0x60, 0x02, 0x07, 0x00, 0x10, 0x30, 0x00,\n  0x01, 0x80, 0x00, 0x0C, 0x00, 0x00, 0x70, 0x00, 0x01, 0xF0, 0x00, 0x07,\n  0xF8, 0x00, 0x07, 0xF0, 0x00, 0x03, 0xC0, 0x00, 0x07, 0x00, 0x00, 0x18,\n  0x00, 0x00, 0xC2, 0x00, 0x06, 0x30, 0x00, 0x61, 0x80, 0x03, 0x1E, 0x00,\n  0x30, 0xFC, 0x07, 0x06, 0x7F, 0xF0, 0x00, 0xFE, 0x00, 0x01, 0x80, 0x00,\n  0x0C, 0x00, 0x00, 0x60, 0x00, 0x06, 0x00, 0x00, 0x30, 0x00, 0x01, 0x80,\n  0x00, 0x00, 0x78, 0x00, 0x07, 0xF8, 0x00, 0x38, 0x60, 0x01, 0xC0, 0xC0,\n  0x06, 0x03, 0x00, 0x30, 0x0C, 0x00, 0xC0, 0x30, 0x03, 0x01, 0x80, 0x0C,\n  0x0E, 0x00, 0x38, 0x70, 0x00, 0x7F, 0x81, 0xC0, 0xF8, 0x3F, 0x00, 0x07,\n  0xC0, 0x01, 0xF8, 0x00, 0x3F, 0x00, 0x07, 0xC0, 0x00, 0x78, 0x00, 0x01,\n  0x00, 0x78, 0x00, 0x07, 0xF8, 0x00, 0x38, 0x60, 0x01, 0x80, 0xC0, 0x06,\n  0x03, 0x00, 0x30, 0x0C, 0x00, 0xC0, 0x30, 0x03, 0x01, 0x80, 0x0C, 0x0E,\n  0x00, 0x18, 0x70, 0x00, 0x7F, 0x80, 0x00, 0x78, 0x00, 0x00, 0x1E, 0x00,\n  0x0F, 0xF8, 0x03, 0x8E, 0x00, 0xC0, 0x00, 0x38, 0x00, 0x06, 0x00, 0x00,\n  0xC0, 0x00, 0x18, 0x00, 0x01, 0x00, 0x00, 0x30, 0x00, 0x06, 0x00, 0x03,\n  0xE0, 0x01, 0xCC, 0x0E, 0x60, 0xC3, 0xD8, 0x18, 0x63, 0x03, 0x18, 0xC0,\n  0x33, 0x18, 0x06, 0xC3, 0x00, 0x70, 0x60, 0x0E, 0x0C, 0x01, 0xC0, 0xC0,\n  0x78, 0x1C, 0x3B, 0xE1, 0xFE, 0x3C, 0x1F, 0x00, 0x00, 0x7E, 0xFD, 0xF3,\n  0xE7, 0xCF, 0x3E, 0x78, 0xF1, 0xE3, 0x87, 0x0E, 0x18, 0x00, 0x00, 0x60,\n  0x18, 0x07, 0x00, 0xC0, 0x30, 0x0E, 0x01, 0x80, 0x70, 0x0C, 0x03, 0x80,\n  0x60, 0x1C, 0x03, 0x80, 0xE0, 0x1C, 0x03, 0x80, 0xF0, 0x1C, 0x03, 0x80,\n  0x70, 0x0E, 0x01, 0xC0, 0x38, 0x07, 0x00, 0xE0, 0x1C, 0x03, 0x80, 0x30,\n  0x06, 0x00, 0xC0, 0x1C, 0x01, 0x80, 0x30, 0x02, 0x00, 0x01, 0x80, 0x30,\n  0x06, 0x00, 0xE0, 0x0C, 0x01, 0x80, 0x30, 0x07, 0x00, 0xE0, 0x1C, 0x03,\n  0x80, 0x70, 0x0E, 0x01, 0xC0, 0x38, 0x07, 0x00, 0xE0, 0x38, 0x07, 0x00,\n  0xE0, 0x3C, 0x07, 0x00, 0xE0, 0x38, 0x07, 0x01, 0xC0, 0x38, 0x0E, 0x01,\n  0x80, 0x70, 0x0C, 0x03, 0x00, 0xC0, 0x10, 0x00, 0x00, 0x20, 0x00, 0x18,\n  0x00, 0x06, 0x00, 0x01, 0x80, 0x00, 0xC0, 0x00, 0x30, 0x0E, 0x0C, 0x0B,\n  0xF3, 0x3E, 0x3F, 0xFE, 0x01, 0xFC, 0x00, 0x3C, 0x00, 0x1F, 0x00, 0x0E,\n  0x60, 0x07, 0x18, 0x01, 0x83, 0x00, 0xC0, 0xC0, 0x60, 0x30, 0x00, 0x00,\n  0x0C, 0x00, 0x00, 0x30, 0x00, 0x00, 0xC0, 0x00, 0x07, 0x00, 0x00, 0x18,\n  0x00, 0x00, 0x60, 0x00, 0x01, 0x80, 0x00, 0x06, 0x00, 0x00, 0x30, 0x00,\n  0x00, 0xC0, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0x00, 0x30, 0x00, 0x01,\n  0x80, 0x00, 0x06, 0x00, 0x00, 0x18, 0x00, 0x00, 0x60, 0x00, 0x01, 0x80,\n  0x00, 0x0C, 0x00, 0x00, 0x30, 0x00, 0x00, 0xC0, 0x00, 0x03, 0x00, 0x00,\n  0x03, 0xF0, 0x7E, 0x07, 0xC0, 0xF8, 0x0F, 0x81, 0xF0, 0x1E, 0x03, 0xE0,\n  0x3C, 0x07, 0x80, 0x70, 0x0F, 0x00, 0xE0, 0x0C, 0x00, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xE0, 0x3C, 0xFF, 0xFF, 0xFF, 0xCF, 0x00, 0x00, 0x00, 0x03,\n  0x00, 0x00, 0x03, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x0C,\n  0x00, 0x00, 0x18, 0x00, 0x00, 0x30, 0x00, 0x00, 0x30, 0x00, 0x00, 0x60,\n  0x00, 0x00, 0xC0, 0x00, 0x00, 0xC0, 0x00, 0x01, 0x80, 0x00, 0x03, 0x00,\n  0x00, 0x07, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x1C, 0x00,\n  0x00, 0x18, 0x00, 0x00, 0x30, 0x00, 0x00, 0x70, 0x00, 0x00, 0x60, 0x00,\n  0x00, 0xC0, 0x00, 0x01, 0x80, 0x00, 0x01, 0x80, 0x00, 0x03, 0x00, 0x00,\n  0x06, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x18, 0x00, 0x00,\n  0x18, 0x00, 0x00, 0x30, 0x00, 0x00, 0x60, 0x00, 0x00, 0xE0, 0x00, 0x00,\n  0xC0, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x0F, 0xF8, 0x01,\n  0xC1, 0xC0, 0x38, 0x0E, 0x07, 0x00, 0x60, 0xE0, 0x03, 0x0C, 0x00, 0x31,\n  0x80, 0x03, 0x18, 0x00, 0x33, 0x00, 0x03, 0x30, 0x00, 0x33, 0x00, 0x03,\n  0x20, 0x00, 0x26, 0x00, 0x06, 0x60, 0x00, 0x66, 0x00, 0x06, 0x40, 0x00,\n  0x4C, 0x00, 0x0C, 0xC0, 0x00, 0xCC, 0x00, 0x0C, 0xC0, 0x01, 0x8C, 0x00,\n  0x18, 0xC0, 0x01, 0x8C, 0x00, 0x30, 0xC0, 0x07, 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 0x6E, 0x00, 0x1F, 0x00, 0x02, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xC3, 0x86, 0x0C, 0x18, 0x70, 0xC0, 0x00, 0x3F, 0x80, 0x0F, 0xFF, 0x80,\n  0x78, 0x07, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x18, 0x00, 0x00, 0x60, 0x00,\n  0x01, 0x80, 0x00, 0x06, 0x00, 0x00, 0x38, 0x03, 0xFC, 0xC0, 0x7F, 0xFF,\n  0x07, 0xC0, 0x0C, 0x38, 0x00, 0x31, 0xC0, 0x01, 0xCE, 0x00, 0x06, 0x30,\n  0x00, 0x18, 0xC0, 0x00, 0xE3, 0x00, 0x07, 0x8E, 0x00, 0x7C, 0x1C, 0x0F,\n  0x3F, 0x3F, 0xF0, 0xFC, 0x7F, 0x00, 0x00, 0x03, 0xF0, 0x00, 0x00, 0x7C,\n  0x00, 0x00, 0x01, 0x80, 0x00, 0x00, 0x30, 0x00, 0x00, 0x06, 0x00, 0x00,\n  0x00, 0xC0, 0x00, 0x00, 0x10, 0x00, 0x00, 0x06, 0x07, 0xE0, 0x00, 0xC3,\n  0xFF, 0x00, 0x19, 0xC0, 0xF0, 0x03, 0x60, 0x07, 0x00, 0xD8, 0x00, 0x60,\n  0x1E, 0x00, 0x0E, 0x03, 0x80, 0x00, 0xC0, 0x60, 0x00, 0x18, 0x0C, 0x00,\n  0x03, 0x03, 0x00, 0x00, 0x60, 0x60, 0x00, 0x0C, 0x0C, 0x00, 0x01, 0x81,\n  0x80, 0x00, 0x60, 0x70, 0x00, 0x0C, 0x0E, 0x00, 0x03, 0x01, 0xC0, 0x00,\n  0x60, 0x3C, 0x00, 0x18, 0x05, 0x80, 0x06, 0x01, 0xB8, 0x01, 0x83, 0xF3,\n  0xC1, 0xE0, 0x7E, 0x3F, 0xF8, 0x00, 0x01, 0xF8, 0x00, 0x00, 0x3F, 0x00,\n  0x07, 0xFF, 0x30, 0x38, 0x0F, 0xC1, 0x80, 0x1F, 0x0C, 0x00, 0x18, 0x60,\n  0x00, 0x63, 0x00, 0x01, 0x9C, 0x00, 0x06, 0x60, 0x00, 0x01, 0x80, 0x00,\n  0x0C, 0x00, 0x00, 0x30, 0x00, 0x00, 0xC0, 0x00, 0x03, 0x00, 0x00, 0x0C,\n  0x00, 0x00, 0x30, 0x00, 0x00, 0xE0, 0x00, 0x01, 0x80, 0x00, 0xC7, 0x00,\n  0x0E, 0x0F, 0x01, 0xF0, 0x1F, 0xFF, 0x00, 0x1F, 0xE0, 0x00, 0x00, 0x00,\n  0x1F, 0x80, 0x00, 0x0F, 0x80, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x60, 0x00,\n  0x00, 0x30, 0x00, 0x00, 0x10, 0x00, 0x00, 0x18, 0x00, 0xFC, 0x0C, 0x01,\n  0xFF, 0x86, 0x01, 0xC0, 0xE3, 0x03, 0x80, 0x1B, 0x03, 0x80, 0x05, 0x81,\n  0x80, 0x03, 0xC1, 0x80, 0x00, 0xE1, 0x80, 0x00, 0x60, 0xC0, 0x00, 0x30,\n  0x60, 0x00, 0x18, 0x60, 0x00, 0x0C, 0x30, 0x00, 0x06, 0x18, 0x00, 0x02,\n  0x0C, 0x00, 0x03, 0x06, 0x00, 0x01, 0x83, 0x00, 0x01, 0xC1, 0xC0, 0x01,\n  0xE0, 0x60, 0x01, 0xE0, 0x38, 0x01, 0xB0, 0x0F, 0x03, 0x9F, 0x03, 0xFF,\n  0x0F, 0x80, 0x7E, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x07, 0xFF, 0x80, 0x78,\n  0x0F, 0x03, 0x80, 0x0E, 0x1C, 0x00, 0x18, 0xE0, 0x00, 0x73, 0x00, 0x00,\n  0xD8, 0x00, 0x03, 0x60, 0x00, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0,\n  0x00, 0x00, 0xC0, 0x00, 0x03, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x38, 0x00,\n  0x00, 0x60, 0x00, 0x01, 0xC0, 0x00, 0x03, 0x80, 0x03, 0x07, 0x80, 0xF8,\n  0x0F, 0xFF, 0x80, 0x0F, 0xF0, 0x00, 0x00, 0x00, 0xFF, 0x80, 0x00, 0xFF,\n  0xF0, 0x00, 0xF0, 0x00, 0x00, 0x70, 0x00, 0x00, 0x18, 0x00, 0x00, 0x06,\n  0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x07, 0xFF, 0xFC, 0x03,\n  0xFF, 0xFF, 0x00, 0x03, 0x00, 0x00, 0x01, 0x80, 0x00, 0x00, 0x60, 0x00,\n  0x00, 0x18, 0x00, 0x00, 0x06, 0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0xC0,\n  0x00, 0x00, 0x30, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x03, 0x00, 0x00, 0x01,\n  0x80, 0x00, 0x00, 0x60, 0x00, 0x00, 0x18, 0x00, 0x00, 0x06, 0x00, 0x00,\n  0x01, 0x80, 0x00, 0x00, 0xC0, 0x00, 0x0F, 0xFF, 0xFC, 0x03, 0xFF, 0xFE,\n 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 0x18, 0x00, 0x03, 0x00, 0x00, 0x60, 0x00, 0x0C, 0x03, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xF0, 0x00, 0x1E, 0x07, 0x81, 0xE7, 0xE1, 0xF8, 0x3D, 0x8E, 0xE3,\n  0x81, 0xE0, 0xF8, 0x30, 0x38, 0x1E, 0x06, 0x06, 0x03, 0x80, 0xC1, 0x80,\n  0x60, 0x18, 0x30, 0x0C, 0x03, 0x06, 0x01, 0x80, 0x60, 0xC0, 0x30, 0x08,\n  0x18, 0x0C, 0x03, 0x06, 0x01, 0x80, 0x60, 0xC0, 0x30, 0x0C, 0x18, 0x06,\n  0x01, 0x83, 0x00, 0x80, 0x60, 0x40, 0x30, 0x0C, 0x18, 0x06, 0x01, 0x83,\n  0x00, 0xC0, 0x30, 0x60, 0x18, 0x06, 0x7F, 0x03, 0xC1, 0xFF, 0xE0, 0xF8,\n  0x3E, 0x00, 0x03, 0xE0, 0x1F, 0x1F, 0xF0, 0x3E, 0x60, 0x70, 0x0F, 0x80,\n  0x70, 0x3C, 0x00, 0x60, 0x70, 0x00, 0xC0, 0xC0, 0x01, 0x81, 0x80, 0x03,\n  0x07, 0x00, 0x06, 0x0C, 0x00, 0x1C, 0x18, 0x00, 0x30, 0x30, 0x00, 0x60,\n  0x60, 0x00, 0xC1, 0xC0, 0x01, 0x83, 0x00, 0x06, 0x06, 0x00, 0x0C, 0x0C,\n  0x00, 0x18, 0x18, 0x00, 0x30, 0x70, 0x00, 0x67, 0xFC, 0x07, 0xFF, 0xF0,\n  0x0F, 0xE0, 0x00, 0x3F, 0x00, 0x07, 0xFF, 0x00, 0x3C, 0x0F, 0x01, 0xC0,\n  0x1C, 0x0C, 0x00, 0x38, 0x60, 0x00, 0x63, 0x00, 0x00, 0xDC, 0x00, 0x03,\n  0x60, 0x00, 0x0D, 0x80, 0x00, 0x3C, 0x00, 0x00, 0xF0, 0x00, 0x03, 0xC0,\n  0x00, 0x1B, 0x00, 0x00, 0x6C, 0x00, 0x03, 0xB0, 0x00, 0x0C, 0x60, 0x00,\n  0x61, 0xC0, 0x03, 0x03, 0x80, 0x38, 0x0F, 0x03, 0xC0, 0x0F, 0xFE, 0x00,\n  0x0F, 0xC0, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x1F, 0x8F, 0xFE, 0x00, 0xFC,\n  0xE0, 0x78, 0x00, 0xCC, 0x00, 0xE0, 0x06, 0xC0, 0x03, 0x00, 0x3C, 0x00,\n  0x1C, 0x01, 0xC0, 0x00, 0x60, 0x0C, 0x00, 0x03, 0x00, 0xE0, 0x00, 0x18,\n  0x06, 0x00, 0x00, 0xC0, 0x30, 0x00, 0x06, 0x01, 0x80, 0x00, 0x30, 0x0C,\n  0x00, 0x03, 0x00, 0xE0, 0x00, 0x18, 0x07, 0x00, 0x01, 0x80, 0x3C, 0x00,\n  0x1C, 0x01, 0xE0, 0x01, 0xC0, 0x0D, 0x80, 0x1C, 0x00, 0xCF, 0x03, 0xC0,\n  0x06, 0x3F, 0xF8, 0x00, 0x30, 0x7F, 0x00, 0x01, 0x80, 0x00, 0x00, 0x0C,\n  0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x30, 0x00,\n  0x00, 0x01, 0x80, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x07, 0xFF, 0x00, 0x00,\n  0x7F, 0xF8, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x7F, 0xE1, 0xF0, 0x78,\n  0x1C, 0xFC, 0x38, 0x01, 0xB0, 0x1C, 0x00, 0x2C, 0x0E, 0x00, 0x0F, 0x03,\n  0x00, 0x01, 0xC1, 0x80, 0x00, 0x60, 0x60, 0x00, 0x18, 0x30, 0x00, 0x06,\n  0x0C, 0x00, 0x01, 0x83, 0x00, 0x00, 0x60, 0xC0, 0x00, 0x30, 0x30, 0x00,\n  0x0C, 0x0C, 0x00, 0x07, 0x03, 0x80, 0x03, 0xC0, 0x60, 0x01, 0xB0, 0x1C,\n  0x00, 0xD8, 0x03, 0xC0, 0xE6, 0x00, 0x7F, 0xF1, 0x80, 0x07, 0xE0, 0x60,\n  0x00, 0x00, 0x18, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,\n  0xC0, 0x00, 0x00, 0x30, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x06, 0x00, 0x00,\n  0x7F, 0xF8, 0x00, 0x1F, 0xFE, 0x00, 0x07, 0xF0, 0x3E, 0x03, 0xF8, 0x7F,\n  0xC0, 0x18, 0xF0, 0x60, 0x0C, 0xE0, 0x00, 0x07, 0xE0, 0x00, 0x03, 0xC0,\n  0x00, 0x03, 0xC0, 0x00, 0x01, 0x80, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x60,\n  0x00, 0x00, 0x30, 0x00, 0x00, 0x38, 0x00, 0x00, 0x18, 0x00, 0x00, 0x0C,\n  0x00, 0x00, 0x06, 0x00, 0x00, 0x03, 0x00, 0x00, 0x03, 0x80, 0x00, 0x01,\n  0x80, 0x00, 0x3F, 0xFF, 0xF0, 0x1F, 0xFF, 0xF0, 0x00, 0x00, 0x3F, 0x00,\n  0x0F, 0xFE, 0xC0, 0xF0, 0x3E, 0x0E, 0x00, 0x70, 0xE0, 0x01, 0x06, 0x00,\n  0x08, 0x30, 0x00, 0x41, 0xC0, 0x00, 0x07, 0x00, 0x00, 0x3F, 0xF0, 0x00,\n  0x3F, 0xE0, 0x00, 0x07, 0xC0, 0x00, 0x07, 0x00, 0x00, 0x18, 0x00, 0x00,\n  0xCC, 0x00, 0x06, 0x60, 0x00, 0x33, 0x00, 0x03, 0x3C, 0x00, 0x71, 0xF8,\n  0x0F, 0x0D, 0xFF, 0xF0, 0x01, 0xFC, 0x00, 0x03, 0x00, 0x03, 0x00, 0x01,\n  0x80, 0x00, 0xC0, 0x00, 0x60, 0x00, 0x70, 0x03, 0xFF, 0xFF, 0xFF, 0xFF,\n  0x0C, 0x00, 0x06, 0x00, 0x06, 0x00, 0x03, 0x00, 0x01, 0x80, 0x00, 0xC0,\n  0x00, 0xE0, 0x00, 0x60, 0x00, 0x30, 0x00, 0x18, 0x00, 0x0C, 0x00, 0x0E,\n  0x00, 0x06, 0x00, 0x03, 0x00, 0x01, 0x80, 0x00, 0xC0, 0x03, 0x38, 0x0F,\n  0x9F, 0xFF, 0x03, 0xF8, 0x00, 0xFC, 0x03, 0xFF, 0xE0, 0x1F, 0xC6, 0x00,\n  0x0C, 0x30, 0x00, 0x61, 0x80, 0x03, 0x0C, 0x00, 0x18, 0x60, 0x01, 0x86,\n  0x00, 0x0C, 0x30, 0x00, 0x61, 0x80, 0x03, 0x0C, 0x00, 0x18, 0x60, 0x01,\n  0x86, 0x00, 0x0C, 0x30, 0x00, 0x61, 0x80, 0x03, 0x0C, 0x00, 0x38, 0x60,\n  0x07, 0x83, 0x80, 0x6C, 0x1E, 0x1E, 0x7C, 0x7F, 0xE3, 0xE0, 0xF8, 0x00,\n  0x00, 0x7F, 0xC0, 0xFF, 0xFF, 0xF0, 0x3F, 0xF1, 0xC0, 0x00, 0xC0, 0x30,\n  0x00, 0x60, 0x0C, 0x00, 0x18, 0x03, 0x00, 0x0C, 0x00, 0xE0, 0x06, 0x00,\n  0x18, 0x01, 0x80, 0x06, 0x00, 0xC0, 0x01, 0x80, 0x30, 0x00, 0x60, 0x18,\n  0x00, 0x0C, 0x0C, 0x00, 0x03, 0x03, 0x00, 0x00, 0xC1, 0x80, 0x00, 0x30,\n  0xC0, 0x00, 0x06, 0x30, 0x00, 0x01, 0x98, 0x00, 0x00, 0x6C, 0x00, 0x00,\n  0x1F, 0x00, 0x00, 0x07, 0x80, 0x00, 0xFE, 0x00, 0x7F, 0xFF, 0x00, 0x3F,\n  0xCC, 0x00, 0x03, 0x06, 0x00, 0x01, 0x83, 0x00, 0x01, 0x81, 0x81, 0x80,\n  0xC0, 0xC1, 0xE0, 0x60, 0x60, 0xF0, 0x60, 0x30, 0xD8, 0x30, 0x18, 0x6C,\n  0x30, 0x0C, 0x66, 0x18, 0x06, 0x33, 0x18, 0x03, 0x31, 0x8C, 0x01, 0x98,\n  0x66, 0x00, 0xD8, 0x36, 0x00, 0x6C, 0x1B, 0x00, 0x3C, 0x0F, 0x00, 0x1E,\n  0x07, 0x80, 0x0E, 0x03, 0x80, 0x07, 0x01, 0xC0, 0x00, 0x07, 0xF0, 0x3F,\n  0xC3, 0xFC, 0x0F, 0xF0, 0x38, 0x00, 0x60, 0x07, 0x00, 0x70, 0x00, 0xE0,\n  0x38, 0x00, 0x18, 0x1C, 0x00, 0x03, 0x0C, 0x00, 0x00, 0xEE, 0x00, 0x00,\n  0x1F, 0x00, 0x00, 0x03, 0x80, 0x00, 0x01, 0xE0, 0x00, 0x01, 0xDC, 0x00,\n  0x00, 0xE3, 0x80, 0x00, 0x70, 0x70, 0x00, 0x38, 0x0E, 0x00, 0x18, 0x01,\n  0x80, 0x1C, 0x00, 0x30, 0x0E, 0x00, 0x0E, 0x0F, 0xF0, 0x3F, 0xE3, 0xFC,\n  0x0F, 0xF8, 0x03, 0xF8, 0x07, 0xF8, 0x3F, 0xC0, 0x3F, 0xC0, 0x60, 0x00,\n  0x30, 0x01, 0x80, 0x01, 0x80, 0x0C, 0x00, 0x18, 0x00, 0x60, 0x01, 0x80,\n  0x03, 0x80, 0x0C, 0x00, 0x0C, 0x00, 0xC0, 0x00, 0x60, 0x0C, 0x00, 0x03,\n  0x00, 0x60, 0x00, 0x0C, 0x06, 0x00, 0x00, 0x60, 0x60, 0x00, 0x03, 0x06,\n  0x00, 0x00, 0x1C, 0x30, 0x00, 0x00, 0x63, 0x00, 0x00, 0x03, 0x30, 0x00,\n  0x00, 0x19, 0x80, 0x00, 0x00, 0x78, 0x00, 0x00, 0x03, 0x80, 0x00, 0x00,\n  0x1C, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x60,\n  0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x03, 0x00, 0x00,\n  0x00, 0x30, 0x00, 0x01, 0xFF, 0xF8, 0x00, 0x0F, 0xFF, 0x80, 0x00, 0x00,\n  0x07, 0xFF, 0xF8, 0x3F, 0xFF, 0xC3, 0x00, 0x0C, 0x18, 0x00, 0xC0, 0xC0,\n  0x0C, 0x00, 0x00, 0xC0, 0x00, 0x1C, 0x00, 0x01, 0xC0, 0x00, 0x1C, 0x00,\n  0x01, 0xC0, 0x00, 0x1C, 0x00, 0x01, 0xC0, 0x00, 0x18, 0x00, 0x01, 0x80,\n  0x00, 0x18, 0x00, 0x01, 0x80, 0x0C, 0x18, 0x00, 0x61, 0x80, 0x02, 0x1F,\n  0xFF, 0xF0, 0xFF, 0xFF, 0x80, 0x00, 0x0E, 0x00, 0x7C, 0x01, 0xC0, 0x03,\n  0x00, 0x0C, 0x00, 0x18, 0x00, 0x30, 0x00, 0x60, 0x01, 0xC0, 0x03, 0x00,\n  0x06, 0x00, 0x0C, 0x00, 0x18, 0x00, 0x60, 0x01, 0xC0, 0x0F, 0x00, 0xF8,\n  0x01, 0xF0, 0x00, 0x30, 0x00, 0x30, 0x00, 0x60, 0x00, 0xC0, 0x03, 0x80,\n  0x06, 0x00, 0x0C, 0x00, 0x18, 0x00, 0x30, 0x00, 0xE0, 0x01, 0x80, 0x03,\n  0x00, 0x06, 0x00, 0x0E, 0x00, 0x0F, 0x00, 0x0E, 0x00, 0x01, 0x80, 0xC0,\n  0x60, 0x60, 0x30, 0x18, 0x0C, 0x06, 0x06, 0x03, 0x01, 0x80, 0xC0, 0x40,\n  0x60, 0x30, 0x18, 0x0C, 0x0C, 0x06, 0x03, 0x01, 0x80, 0xC0, 0xC0, 0x60,\n  0x30, 0x18, 0x08, 0x0C, 0x06, 0x03, 0x01, 0x80, 0x80, 0xC0, 0x60, 0x30,\n  0x00, 0x01, 0xC0, 0x03, 0xC0, 0x01, 0xC0, 0x01, 0x80, 0x03, 0x00, 0x06,\n  0x00, 0x0C, 0x00, 0x30, 0x00, 0x60, 0x00, 0xC0, 0x01, 0x80, 0x03, 0x00,\n  0x0C, 0x00, 0x18, 0x00, 0x38, 0x00, 0x38, 0x00, 0x3E, 0x00, 0x7C, 0x03,\n  0xC0, 0x0E, 0x00, 0x18, 0x00, 0x70, 0x00, 0xC0, 0x01, 0x80, 0x03, 0x00,\n  0x06, 0x00, 0x18, 0x00, 0x30, 0x00, 0x60, 0x00, 0xC0, 0x03, 0x00, 0x0E,\n  0x00, 0xF8, 0x01, 0xC0, 0x00, 0x0F, 0x00, 0x01, 0xFC, 0x03, 0x70, 0xE0,\n  0x7E, 0x07, 0x1E, 0xC0, 0x3F, 0x80, 0x01, 0xE0 };\n\nconst GFXglyph FreeMonoOblique24pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,  28,    0,    1 },   // 0x20 ' '\n  {     0,  10,  30,  28,   12,  -28 },   // 0x21 '!'\n  {    38,  16,  14,  28,   10,  -28 },   // 0x22 '\"'\n  {    66,  22,  32,  28,    6,  -29 },   // 0x23 '#'\n  {   154,  21,  33,  28,    6,  -29 },   // 0x24 '$'\n  {   241,  22,  29,  28,    6,  -27 },   // 0x25 '%'\n  {   321,  19,  25,  28,    6,  -23 },   // 0x26 '&'\n  {   381,   7,  14,  28,   16,  -28 },   // 0x27 '''\n  {   394,  11,  34,  28,   16,  -27 },   // 0x28 '('\n  {   441,  11,  34,  28,    7,  -27 },   // 0x29 ')'\n  {   488,  18,  17,  28,   10,  -28 },   // 0x2A '*'\n  {   527,  22,  22,  28,    6,  -23 },   // 0x2B '+'\n  {   588,  12,  14,  28,    5,   -6 },   // 0x2C ','\n  {   609,  22,   2,  28,    6,  -13 },   // 0x2D '-'\n  {   615,   7,   6,  28,   11,   -4 },   // 0x2E '.'\n  {   621,  24,  35,  28,    5,  -30 },   // 0x2F '/'\n  {   726,  20,  30,  28,    7,  -28 },   // 0x30 '0'\n  {   801,  17,  29,  28,    6,  -28 },   // 0x31 '1'\n  {   863,  23,  29,  28,    4,  -28 },   // 0x32 '2'\n  {   947,  22,  30,  28,    5,  -28 },   // 0x33 '3'\n  {  1030,  19,  28,  28,    7,  -27 },   // 0x34 '4'\n  {  1097,  21,  29,  28,    6,  -27 },   // 0x35 '5'\n  {  1174,  21,  30,  28,    9,  -28 },   // 0x36 '6'\n  {  1253,  18,  28,  28,   10,  -27 },   // 0x37 '7'\n  {  1316,  20,  30,  28,    7,  -28 },   // 0x38 '8'\n  {  1391,  22,  30,  28,    6,  -28 },   // 0x39 '9'\n  {  1474,  10,  21,  28,   11,  -19 },   // 0x3A ':'\n  {  1501,  15,  27,  28,    5,  -19 },   // 0x3B ';'\n  {  1552,  23,  22,  28,    6,  -23 },   // 0x3C '<'\n  {  1616,  25,   9,  28,    4,  -17 },   // 0x3D '='\n  {  1645,  24,  22,  28,    4,  -23 },   // 0x3E '>'\n  {  1711,  16,  28,  28,   11,  -26 },   // 0x3F '?'\n  {  1767,  19,  32,  28,    7,  -28 },   // 0x40 '@'\n  {  1843,  27,  26,  28,    1,  -25 },   // 0x41 'A'\n  {  1931,  26,  26,  28,    2,  -25 },   // 0x42 'B'\n  {  2016,  25,  28,  28,    5,  -26 },   // 0x43 'C'\n  {  2104,  26,  26,  28,    2,  -25 },   // 0x44 'D'\n  {  2189,  27,  26,  28,    2,  -25 },   // 0x45 'E'\n  {  2277,  28,  26,  28,    2,  -25 },   // 0x46 'F'\n  {  2368,  25,  28,  28,    5,  -26 },   // 0x47 'G'\n  {  2456,  27,  26,  28,    3,  -25 },   // 0x48 'H'\n  {  2544,  22,  26,  28,    6,  -25 },   // 0x49 'I'\n  {  2616,  28,  27,  28,    5,  -25 },   // 0x4A 'J'\n  {  2711,  29,  26,  28,    2,  -25 },   // 0x4B 'K'\n  {  2806,  25,  26,  28,    3,  -25 },   // 0x4C 'L'\n  {  2888,  32,  26,  28,    1,  -25 },   // 0x4D 'M'\n  {  2992,  30,  26,  28,    2,  -25 },   // 0x4E 'N'\n  {  3090,  24,  28,  28,    5,  -26 },   // 0x4F 'O'\n  {  3174,  26,  26,  28,    2,  -25 },   // 0x50 'P'\n  {  3259,  24,  32,  28,    5,  -26 },   // 0x51 'Q'\n  {  3355,  26,  26,  28,    2,  -25 },   // 0x52 'R'\n  {  3440,  24,  28,  28,    5,  -26 },   // 0x53 'S'\n  {  3524,  24,  26,  28,    7,  -25 },   // 0x54 'T'\n  {  3602,  26,  27,  28,    6,  -25 },   // 0x55 'U'\n  {  3690,  27,  26,  28,    6,  -25 },   // 0x56 'V'\n  {  3778,  27,  26,  28,    6,  -25 },   // 0x57 'W'\n  {  3866,  29,  26,  28,    2,  -25 },   // 0x58 'X'\n  {  3961,  24,  26,  28,    7,  -25 },   // 0x59 'Y'\n  {  4039,  23,  26,  28,    5,  -25 },   // 0x5A 'Z'\n  {  4114,  15,  34,  28,   12,  -27 },   // 0x5B '['\n  {  4178,  10,  35,  28,   12,  -30 },   // 0x5C '\\'\n  {  4222,  15,  34,  28,    6,  -27 },   // 0x5D ']'\n  {  4286,  18,  12,  28,    9,  -28 },   // 0x5E '^'\n  {  4313,  28,   2,  28,   -1,    5 },   // 0x5F '_'\n  {  4320,   6,   7,  28,   13,  -29 },   // 0x60 '`'\n  {  4326,  22,  22,  28,    4,  -20 },   // 0x61 'a'\n  {  4387,  27,  29,  28,    1,  -27 },   // 0x62 'b'\n  {  4485,  22,  22,  28,    6,  -20 },   // 0x63 'c'\n  {  4546,  25,  29,  28,    5,  -27 },   // 0x64 'd'\n  {  4637,  22,  22,  28,    5,  -20 },   // 0x65 'e'\n  {  4698,  26,  28,  28,    5,  -27 },   // 0x66 'f'\n  {  4789,  25,  30,  28,    5,  -20 },   // 0x67 'g'\n  {  4883,  24,  28,  28,    3,  -27 },   // 0x68 'h'\n  {  4967,  19,  29,  28,    5,  -28 },   // 0x69 'i'\n  {  5036,  20,  38,  28,    4,  -28 },   // 0x6A 'j'\n  {  5131,  24,  28,  28,    3,  -27 },   // 0x6B 'k'\n  {  5215,  19,  28,  28,    5,  -27 },   // 0x6C 'l'\n  {  5282,  27,  21,  28,    1,  -20 },   // 0x6D 'm'\n  {  5353,  23,  21,  28,    3,  -20 },   // 0x6E 'n'\n  {  5414,  22,  22,  28,    5,  -20 },   // 0x6F 'o'\n  {  5475,  29,  30,  28,   -1,  -20 },   // 0x70 'p'\n  {  5584,  26,  30,  28,    5,  -20 },   // 0x71 'q'\n  {  5682,  25,  20,  28,    4,  -19 },   // 0x72 'r'\n  {  5745,  21,  22,  28,    5,  -20 },   // 0x73 's'\n  {  5803,  17,  27,  28,    7,  -25 },   // 0x74 't'\n  {  5861,  21,  21,  28,    6,  -19 },   // 0x75 'u'\n  {  5917,  26,  20,  28,    5,  -19 },   // 0x76 'v'\n  {  5982,  25,  20,  28,    6,  -19 },   // 0x77 'w'\n  {  6045,  26,  20,  28,    3,  -19 },   // 0x78 'x'\n  {  6110,  29,  29,  28,    1,  -19 },   // 0x79 'y'\n  {  6216,  21,  20,  28,    5,  -19 },   // 0x7A 'z'\n  {  6269,  15,  34,  28,   10,  -27 },   // 0x7B '{'\n  {  6333,   9,  35,  28,   12,  -28 },   // 0x7C '|'\n  {  6373,  15,  34,  28,    8,  -27 },   // 0x7D '}'\n  {  6437,  20,   6,  28,    7,  -15 } }; // 0x7E '~'\n\nconst GFXfont FreeMonoOblique24pt7b PROGMEM = {\n  (uint8_t  *)FreeMonoOblique24pt7bBitmaps,\n  (GFXglyph *)FreeMonoOblique24pt7bGlyphs,\n  0x20, 0x7E, 47 };\n\n// Approx. 7124 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeMonoOblique9pt7b.h",
    "content": "const uint8_t FreeMonoOblique9pt7bBitmaps[] PROGMEM = {\n  0x11, 0x22, 0x24, 0x40, 0x00, 0xC0, 0xDE, 0xE5, 0x29, 0x00, 0x09, 0x05,\n  0x02, 0x82, 0x47, 0xF8, 0xA0, 0x51, 0xFE, 0x28, 0x14, 0x0A, 0x09, 0x00,\n  0x08, 0x1D, 0x23, 0x40, 0x70, 0x1C, 0x02, 0x82, 0x84, 0x78, 0x20, 0x20,\n  0x1C, 0x11, 0x08, 0x83, 0x80, 0x18, 0x71, 0xC0, 0x1C, 0x11, 0x08, 0x83,\n  0x80, 0x1E, 0x60, 0x81, 0x03, 0x0A, 0x65, 0x46, 0x88, 0xE8, 0xFA, 0x80,\n  0x12, 0x24, 0x48, 0x88, 0x88, 0x88, 0x80, 0x01, 0x11, 0x11, 0x11, 0x22,\n  0x44, 0x80, 0x10, 0x22, 0x5B, 0xC3, 0x0A, 0x22, 0x00, 0x04, 0x02, 0x02,\n  0x1F, 0xF0, 0x80, 0x40, 0x20, 0x00, 0x36, 0x4C, 0x80, 0xFF, 0x80, 0xF0,\n  0x00, 0x80, 0x80, 0x40, 0x40, 0x40, 0x20, 0x20, 0x20, 0x10, 0x10, 0x10,\n  0x08, 0x08, 0x00, 0x1C, 0x45, 0x0A, 0x18, 0x30, 0x61, 0x42, 0x85, 0x11,\n  0xC0, 0x04, 0x38, 0x90, 0x20, 0x81, 0x02, 0x04, 0x08, 0x23, 0xF8, 0x07,\n  0x04, 0xC4, 0x20, 0x10, 0x10, 0x30, 0x20, 0x20, 0x60, 0x40, 0x3F, 0x80,\n  0x0F, 0x00, 0x40, 0x20, 0x20, 0x60, 0x18, 0x04, 0x02, 0x01, 0x43, 0x1E,\n  0x00, 0x03, 0x05, 0x0A, 0x12, 0x22, 0x22, 0x42, 0x7F, 0x04, 0x04, 0x1E,\n  0x1F, 0x88, 0x08, 0x05, 0xC3, 0x30, 0x08, 0x04, 0x02, 0x02, 0x42, 0x1E,\n  0x00, 0x07, 0x18, 0x20, 0x40, 0x5C, 0xA6, 0xC2, 0x82, 0x82, 0xC4, 0x78,\n  0xFF, 0x04, 0x10, 0x20, 0x82, 0x04, 0x10, 0x20, 0x81, 0x00, 0x1E, 0x23,\n  0x41, 0x41, 0x62, 0x1C, 0x66, 0x82, 0x82, 0x84, 0x78, 0x1E, 0x23, 0x41,\n  0x41, 0x43, 0x65, 0x3A, 0x02, 0x04, 0x18, 0xE0, 0x6C, 0x00, 0x36, 0x18,\n  0xC0, 0x00, 0x19, 0x8C, 0xC4, 0x00, 0x01, 0x83, 0x06, 0x0C, 0x06, 0x00,\n  0x80, 0x30, 0x04, 0xFF, 0x80, 0x00, 0x1F, 0xF0, 0x20, 0x0C, 0x01, 0x00,\n  0x60, 0x20, 0x60, 0xC1, 0x80, 0x3D, 0x8E, 0x08, 0x10, 0xC6, 0x08, 0x00,\n  0x01, 0x80, 0x1C, 0x45, 0x0A, 0x79, 0x34, 0x69, 0x4E, 0x81, 0x03, 0x03,\n  0xC0, 0x0F, 0x00, 0x60, 0x12, 0x02, 0x40, 0x88, 0x21, 0x07, 0xE1, 0x04,\n  0x20, 0x5E, 0x3C, 0x3F, 0x84, 0x11, 0x04, 0x82, 0x3F, 0x88, 0x32, 0x04,\n  0x81, 0x60, 0xBF, 0xC0, 0x1E, 0x98, 0xD0, 0x28, 0x08, 0x04, 0x02, 0x01,\n  0x00, 0x41, 0x1F, 0x00, 0x3F, 0x0C, 0x22, 0x04, 0x81, 0x20, 0x48, 0x12,\n  0x09, 0x02, 0x43, 0x3F, 0x00, 0x3F, 0xC4, 0x11, 0x00, 0x88, 0x3E, 0x08,\n  0x82, 0x00, 0x82, 0x60, 0xBF, 0xE0, 0x3F, 0xE2, 0x08, 0x40, 0x11, 0x03,\n  0xE0, 0x44, 0x08, 0x01, 0x00, 0x60, 0x1F, 0x00, 0x1E, 0x98, 0xD0, 0x08,\n  0x08, 0x04, 0x7A, 0x05, 0x02, 0x41, 0x1F, 0x00, 0x3D, 0xE2, 0x18, 0x42,\n  0x08, 0x43, 0xF8, 0x41, 0x08, 0x21, 0x08, 0x21, 0x1E, 0xF0, 0x3F, 0x82,\n  0x02, 0x01, 0x00, 0x80, 0x40, 0x20, 0x20, 0x10, 0x7F, 0x00, 0x0F, 0xE0,\n  0x20, 0x04, 0x00, 0x80, 0x10, 0x02, 0x20, 0x84, 0x10, 0x84, 0x0F, 0x00,\n  0x3C, 0xE2, 0x10, 0x44, 0x11, 0x02, 0xC0, 0x64, 0x08, 0x81, 0x08, 0x61,\n  0x1E, 0x38, 0x3E, 0x02, 0x00, 0x80, 0x20, 0x10, 0x04, 0x01, 0x04, 0x42,\n  0x10, 0xBF, 0xE0, 0x38, 0x38, 0xC3, 0x05, 0x28, 0x29, 0x42, 0x52, 0x13,\n  0x10, 0x99, 0x84, 0x08, 0x20, 0x47, 0x8F, 0x00, 0x70, 0xE6, 0x08, 0xA1,\n  0x14, 0x22, 0x48, 0x49, 0x11, 0x22, 0x14, 0x43, 0x1E, 0x20, 0x1E, 0x18,\n  0x90, 0x28, 0x18, 0x0C, 0x06, 0x05, 0x02, 0x46, 0x1E, 0x00, 0x3F, 0x84,\n  0x31, 0x04, 0x81, 0x20, 0x8F, 0xC2, 0x00, 0x80, 0x60, 0x3E, 0x00, 0x1E,\n  0x18, 0x90, 0x28, 0x18, 0x0C, 0x06, 0x05, 0x02, 0x46, 0x1E, 0x08, 0x0F,\n  0x44, 0x60, 0x3F, 0x84, 0x31, 0x04, 0x81, 0x20, 0x8F, 0xC2, 0x10, 0x84,\n  0x60, 0xBC, 0x10, 0x0F, 0x88, 0xC8, 0x24, 0x01, 0x80, 0x38, 0x05, 0x02,\n  0xC2, 0x5E, 0x00, 0xFF, 0xC4, 0x44, 0x02, 0x01, 0x00, 0x80, 0x40, 0x60,\n  0x20, 0x7E, 0x00, 0xF1, 0xD0, 0x24, 0x09, 0x02, 0x41, 0xA0, 0x48, 0x12,\n  0x04, 0xC6, 0x1F, 0x00, 0xF1, 0xE8, 0x11, 0x02, 0x20, 0x82, 0x20, 0x44,\n  0x09, 0x01, 0x40, 0x28, 0x02, 0x00, 0xF1, 0xE8, 0x09, 0x12, 0x26, 0x45,\n  0x48, 0xAA, 0x29, 0x45, 0x28, 0xC6, 0x18, 0xC0, 0x38, 0xE2, 0x08, 0x26,\n  0x05, 0x00, 0x40, 0x18, 0x04, 0x81, 0x08, 0x41, 0x1C, 0x70, 0xE3, 0xA0,\n  0x90, 0x84, 0x81, 0x80, 0x80, 0x40, 0x20, 0x20, 0x7E, 0x00, 0x3F, 0x90,\n  0x88, 0x80, 0x80, 0x80, 0x80, 0x80, 0x82, 0x82, 0x7F, 0x00, 0x39, 0x08,\n  0x44, 0x21, 0x08, 0x42, 0x21, 0x0E, 0x00, 0x88, 0x44, 0x44, 0x22, 0x22,\n  0x11, 0x11, 0x38, 0x42, 0x11, 0x08, 0x42, 0x10, 0x84, 0x2E, 0x00, 0x08,\n  0x28, 0x92, 0x18, 0x20, 0xFF, 0xC0, 0xA4, 0x3E, 0x00, 0x80, 0x47, 0xA4,\n  0x34, 0x12, 0x18, 0xF7, 0x38, 0x01, 0x00, 0x40, 0x09, 0xE1, 0xC6, 0x20,\n  0x44, 0x09, 0x01, 0x30, 0x46, 0x13, 0xBC, 0x00, 0x1F, 0x48, 0x74, 0x0A,\n  0x00, 0x80, 0x20, 0x0C, 0x18, 0xF8, 0x01, 0x80, 0x40, 0x23, 0x96, 0x32,\n  0x0A, 0x05, 0x02, 0x81, 0x61, 0x1F, 0xE0, 0x1F, 0x30, 0xD0, 0x3F, 0xF8,\n  0x04, 0x01, 0x00, 0x7C, 0x07, 0xC3, 0x00, 0x80, 0xFE, 0x10, 0x04, 0x01,\n  0x00, 0x40, 0x10, 0x08, 0x0F, 0xE0, 0x1D, 0xD8, 0xC4, 0x12, 0x04, 0x82,\n  0x20, 0x8C, 0x61, 0xE8, 0x02, 0x01, 0x07, 0x80, 0x30, 0x04, 0x01, 0x00,\n  0x5C, 0x38, 0x88, 0x22, 0x08, 0x82, 0x21, 0x18, 0x4F, 0x3C, 0x04, 0x04,\n  0x00, 0x38, 0x08, 0x08, 0x08, 0x08, 0x10, 0x10, 0xFF, 0x01, 0x00, 0x80,\n  0x03, 0xF0, 0x10, 0x08, 0x04, 0x02, 0x02, 0x01, 0x00, 0x80, 0x40, 0x47,\n  0xC0, 0x38, 0x08, 0x04, 0x02, 0x71, 0x20, 0xA0, 0xA0, 0x68, 0x24, 0x11,\n  0x38, 0xE0, 0x3C, 0x04, 0x04, 0x08, 0x08, 0x08, 0x08, 0x08, 0x10, 0x10,\n  0xFF, 0x3E, 0xE2, 0x64, 0x88, 0x91, 0x12, 0x24, 0x48, 0x91, 0x17, 0x33,\n  0x37, 0x14, 0x4C, 0x24, 0x12, 0x09, 0x08, 0x85, 0xE3, 0x1E, 0x10, 0x90,\n  0x30, 0x18, 0x0C, 0x0B, 0x08, 0x78, 0x33, 0xC3, 0x8C, 0x40, 0x88, 0x12,\n  0x02, 0x60, 0x8C, 0x31, 0x78, 0x20, 0x08, 0x03, 0xE0, 0x00, 0x1C, 0xD8,\n  0xC4, 0x12, 0x04, 0x81, 0x20, 0x4C, 0x21, 0xF8, 0x02, 0x00, 0x81, 0xF0,\n  0x73, 0x8E, 0x04, 0x04, 0x02, 0x01, 0x00, 0x81, 0xFC, 0x1F, 0x61, 0x40,\n  0x3C, 0x03, 0x81, 0x82, 0xFC, 0x10, 0x63, 0xF9, 0x02, 0x04, 0x10, 0x20,\n  0x40, 0x7C, 0xE3, 0x10, 0x90, 0x48, 0x24, 0x22, 0x11, 0x18, 0xF6, 0xF3,\n  0xD0, 0x44, 0x10, 0x88, 0x24, 0x09, 0x02, 0x80, 0x40, 0xE1, 0xD0, 0x24,\n  0x91, 0x24, 0x55, 0x19, 0x86, 0x61, 0x10, 0x39, 0xC4, 0x20, 0xB0, 0x30,\n  0x0C, 0x04, 0x86, 0x13, 0x8E, 0x3C, 0x71, 0x04, 0x10, 0x40, 0x88, 0x09,\n  0x00, 0xA0, 0x06, 0x00, 0x40, 0x08, 0x01, 0x00, 0xFC, 0x00, 0x7F, 0x42,\n  0x04, 0x08, 0x10, 0x20, 0x42, 0xFE, 0x0C, 0x41, 0x04, 0x30, 0x8C, 0x08,\n  0x21, 0x04, 0x10, 0x60, 0x24, 0x94, 0x92, 0x52, 0x40, 0x18, 0x20, 0x82,\n  0x10, 0x40, 0xC4, 0x10, 0x82, 0x08, 0xC0, 0x61, 0x24, 0x30 };\n\nconst GFXglyph FreeMonoOblique9pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,  11,    0,    1 },   // 0x20 ' '\n  {     0,   4,  11,  11,    4,  -10 },   // 0x21 '!'\n  {     6,   5,   5,  11,    4,  -10 },   // 0x22 '\"'\n  {    10,   9,  12,  11,    2,  -10 },   // 0x23 '#'\n  {    24,   8,  12,  11,    3,  -10 },   // 0x24 '$'\n  {    36,   9,  11,  11,    2,  -10 },   // 0x25 '%'\n  {    49,   7,  10,  11,    2,   -9 },   // 0x26 '&'\n  {    58,   2,   5,  11,    6,  -10 },   // 0x27 '''\n  {    60,   4,  13,  11,    6,  -10 },   // 0x28 '('\n  {    67,   4,  13,  11,    3,  -10 },   // 0x29 ')'\n  {    74,   7,   7,  11,    4,  -10 },   // 0x2A '*'\n  {    81,   9,   8,  11,    2,   -8 },   // 0x2B '+'\n  {    90,   4,   5,  11,    2,   -1 },   // 0x2C ','\n  {    93,   9,   1,  11,    2,   -5 },   // 0x2D '-'\n  {    95,   2,   2,  11,    4,   -1 },   // 0x2E '.'\n  {    96,   9,  13,  11,    2,  -11 },   // 0x2F '/'\n  {   111,   7,  11,  11,    3,  -10 },   // 0x30 '0'\n  {   121,   7,  11,  11,    2,  -10 },   // 0x31 '1'\n  {   131,   9,  11,  11,    2,  -10 },   // 0x32 '2'\n  {   144,   9,  11,  11,    2,  -10 },   // 0x33 '3'\n  {   157,   8,  11,  11,    2,  -10 },   // 0x34 '4'\n  {   168,   9,  11,  11,    2,  -10 },   // 0x35 '5'\n  {   181,   8,  11,  11,    3,  -10 },   // 0x36 '6'\n  {   192,   7,  11,  11,    4,  -10 },   // 0x37 '7'\n  {   202,   8,  11,  11,    3,  -10 },   // 0x38 '8'\n  {   213,   8,  11,  11,    3,  -10 },   // 0x39 '9'\n  {   224,   3,   8,  11,    4,   -7 },   // 0x3A ':'\n  {   227,   5,  11,  11,    2,   -7 },   // 0x3B ';'\n  {   234,   9,   8,  11,    2,   -8 },   // 0x3C '<'\n  {   243,   9,   4,  11,    2,   -6 },   // 0x3D '='\n  {   248,   9,   8,  11,    2,   -8 },   // 0x3E '>'\n  {   257,   7,  10,  11,    4,   -9 },   // 0x3F '?'\n  {   266,   7,  12,  11,    3,  -10 },   // 0x40 '@'\n  {   277,  11,  10,  11,    0,   -9 },   // 0x41 'A'\n  {   291,  10,  10,  11,    1,   -9 },   // 0x42 'B'\n  {   304,   9,  10,  11,    2,   -9 },   // 0x43 'C'\n  {   316,  10,  10,  11,    1,   -9 },   // 0x44 'D'\n  {   329,  10,  10,  11,    1,   -9 },   // 0x45 'E'\n  {   342,  11,  10,  11,    1,   -9 },   // 0x46 'F'\n  {   356,   9,  10,  11,    2,   -9 },   // 0x47 'G'\n  {   368,  11,  10,  11,    1,   -9 },   // 0x48 'H'\n  {   382,   9,  10,  11,    2,   -9 },   // 0x49 'I'\n  {   394,  11,  10,  11,    2,   -9 },   // 0x4A 'J'\n  {   408,  11,  10,  11,    1,   -9 },   // 0x4B 'K'\n  {   422,  10,  10,  11,    1,   -9 },   // 0x4C 'L'\n  {   435,  13,  10,  11,    0,   -9 },   // 0x4D 'M'\n  {   452,  11,  10,  11,    1,   -9 },   // 0x4E 'N'\n  {   466,   9,  10,  11,    2,   -9 },   // 0x4F 'O'\n  {   478,  10,  10,  11,    1,   -9 },   // 0x50 'P'\n  {   491,   9,  13,  11,    2,   -9 },   // 0x51 'Q'\n  {   506,  10,  10,  11,    1,   -9 },   // 0x52 'R'\n  {   519,   9,  10,  11,    2,   -9 },   // 0x53 'S'\n  {   531,   9,  10,  11,    3,   -9 },   // 0x54 'T'\n  {   543,  10,  10,  11,    2,   -9 },   // 0x55 'U'\n  {   556,  11,  10,  11,    2,   -9 },   // 0x56 'V'\n  {   570,  11,  10,  11,    2,   -9 },   // 0x57 'W'\n  {   584,  11,  10,  11,    1,   -9 },   // 0x58 'X'\n  {   598,   9,  10,  11,    3,   -9 },   // 0x59 'Y'\n  {   610,   9,  10,  11,    2,   -9 },   // 0x5A 'Z'\n  {   622,   5,  13,  11,    5,  -10 },   // 0x5B '['\n  {   631,   4,  14,  11,    4,  -11 },   // 0x5C '\\'\n  {   638,   5,  13,  11,    2,  -10 },   // 0x5D ']'\n  {   647,   7,   5,  11,    3,  -10 },   // 0x5E '^'\n  {   652,  11,   1,  11,    0,    2 },   // 0x5F '_'\n  {   654,   2,   3,  11,    5,  -11 },   // 0x60 '`'\n  {   655,   9,   8,  11,    2,   -7 },   // 0x61 'a'\n  {   664,  11,  11,  11,    0,  -10 },   // 0x62 'b'\n  {   680,  10,   8,  11,    2,   -7 },   // 0x63 'c'\n  {   690,   9,  11,  11,    2,  -10 },   // 0x64 'd'\n  {   703,   9,   8,  11,    2,   -7 },   // 0x65 'e'\n  {   712,  10,  11,  11,    2,  -10 },   // 0x66 'f'\n  {   726,  10,  11,  11,    2,   -7 },   // 0x67 'g'\n  {   740,  10,  11,  11,    1,  -10 },   // 0x68 'h'\n  {   754,   8,  11,  11,    2,  -10 },   // 0x69 'i'\n  {   765,   9,  14,  11,    1,  -10 },   // 0x6A 'j'\n  {   781,   9,  11,  11,    1,  -10 },   // 0x6B 'k'\n  {   794,   8,  11,  11,    2,  -10 },   // 0x6C 'l'\n  {   805,  11,   8,  11,    0,   -7 },   // 0x6D 'm'\n  {   816,   9,   8,  11,    1,   -7 },   // 0x6E 'n'\n  {   825,   9,   8,  11,    2,   -7 },   // 0x6F 'o'\n  {   834,  11,  11,  11,    0,   -7 },   // 0x70 'p'\n  {   850,  10,  11,  11,    2,   -7 },   // 0x71 'q'\n  {   864,   9,   8,  11,    2,   -7 },   // 0x72 'r'\n  {   873,   8,   8,  11,    2,   -7 },   // 0x73 's'\n  {   881,   7,  10,  11,    2,   -9 },   // 0x74 't'\n  {   890,   9,   8,  11,    2,   -7 },   // 0x75 'u'\n  {   899,  10,   8,  11,    2,   -7 },   // 0x76 'v'\n  {   909,  10,   8,  11,    2,   -7 },   // 0x77 'w'\n  {   919,  10,   8,  11,    1,   -7 },   // 0x78 'x'\n  {   929,  12,  11,  11,    0,   -7 },   // 0x79 'y'\n  {   946,   8,   8,  11,    2,   -7 },   // 0x7A 'z'\n  {   954,   6,  13,  11,    4,  -10 },   // 0x7B '{'\n  {   964,   3,  12,  11,    5,   -9 },   // 0x7C '|'\n  {   969,   6,  13,  11,    3,  -10 },   // 0x7D '}'\n  {   979,   7,   3,  11,    3,   -6 } }; // 0x7E '~'\n\nconst GFXfont FreeMonoOblique9pt7b PROGMEM = {\n  (uint8_t  *)FreeMonoOblique9pt7bBitmaps,\n  (GFXglyph *)FreeMonoOblique9pt7bGlyphs,\n  0x20, 0x7E, 18 };\n\n// Approx. 1654 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeSans12pt7b.h",
    "content": "const uint8_t FreeSans12pt7bBitmaps[] PROGMEM = {\n  0xFF, 0xFF, 0xFF, 0xF0, 0xF0, 0xCF, 0x3C, 0xF3, 0x8A, 0x20, 0x06, 0x30,\n  0x31, 0x03, 0x18, 0x18, 0xC7, 0xFF, 0xBF, 0xFC, 0x31, 0x03, 0x18, 0x18,\n  0xC7, 0xFF, 0xBF, 0xFC, 0x31, 0x01, 0x18, 0x18, 0xC0, 0xC6, 0x06, 0x30,\n  0x04, 0x03, 0xE1, 0xFF, 0x72, 0x6C, 0x47, 0x88, 0xF1, 0x07, 0x20, 0x7E,\n  0x03, 0xF0, 0x17, 0x02, 0x3C, 0x47, 0x88, 0xF1, 0x1B, 0x26, 0x7F, 0xC3,\n  0xE0, 0x10, 0x02, 0x00, 0x00, 0x06, 0x03, 0xC0, 0x40, 0x7E, 0x0C, 0x0E,\n  0x70, 0x80, 0xC3, 0x18, 0x0C, 0x31, 0x00, 0xE7, 0x30, 0x07, 0xE6, 0x00,\n  0x3C, 0x40, 0x00, 0x0C, 0x7C, 0x00, 0x8F, 0xE0, 0x19, 0xC7, 0x01, 0x18,\n  0x30, 0x31, 0x83, 0x02, 0x1C, 0x70, 0x40, 0xFE, 0x04, 0x07, 0xC0, 0x0F,\n  0x00, 0x7E, 0x03, 0x9C, 0x0C, 0x30, 0x30, 0xC0, 0xE7, 0x01, 0xF8, 0x03,\n  0x80, 0x3E, 0x01, 0xCC, 0x6E, 0x19, 0xB0, 0x7C, 0xC0, 0xF3, 0x03, 0xCE,\n  0x1F, 0x9F, 0xE6, 0x1E, 0x1C, 0xFF, 0xA0, 0x08, 0x8C, 0x66, 0x31, 0x98,\n  0xC6, 0x31, 0x8C, 0x63, 0x08, 0x63, 0x08, 0x61, 0x0C, 0x20, 0x82, 0x18,\n  0xC3, 0x18, 0xC3, 0x18, 0xC6, 0x31, 0x8C, 0x62, 0x31, 0x88, 0xC4, 0x62,\n  0x00, 0x10, 0x23, 0x5B, 0xE3, 0x8D, 0x91, 0x00, 0x0C, 0x03, 0x00, 0xC0,\n  0x30, 0xFF, 0xFF, 0xF0, 0xC0, 0x30, 0x0C, 0x03, 0x00, 0xC0, 0xF5, 0x60,\n  0xFF, 0xF0, 0xF0, 0x02, 0x0C, 0x10, 0x20, 0xC1, 0x02, 0x0C, 0x10, 0x20,\n  0xC1, 0x02, 0x0C, 0x10, 0x20, 0xC1, 0x00, 0x1F, 0x07, 0xF1, 0xC7, 0x30,\n  0x6E, 0x0F, 0x80, 0xF0, 0x1E, 0x03, 0xC0, 0x78, 0x0F, 0x01, 0xE0, 0x3C,\n  0x0E, 0xC1, 0x9C, 0x71, 0xFC, 0x1F, 0x00, 0x08, 0xCF, 0xFF, 0x8C, 0x63,\n  0x18, 0xC6, 0x31, 0x8C, 0x63, 0x18, 0x1F, 0x0F, 0xF9, 0x87, 0x60, 0x7C,\n  0x06, 0x00, 0xC0, 0x18, 0x07, 0x01, 0xC0, 0xF0, 0x78, 0x1C, 0x06, 0x00,\n  0x80, 0x30, 0x07, 0xFF, 0xFF, 0xE0, 0x3F, 0x0F, 0xF3, 0x87, 0x60, 0x6C,\n  0x0C, 0x01, 0x80, 0x70, 0x7C, 0x0F, 0x80, 0x18, 0x01, 0x80, 0x3C, 0x07,\n  0x80, 0xD8, 0x73, 0xFC, 0x1F, 0x00, 0x01, 0x80, 0x70, 0x0E, 0x03, 0xC0,\n  0xD8, 0x1B, 0x06, 0x61, 0x8C, 0x21, 0x8C, 0x33, 0x06, 0x7F, 0xFF, 0xFE,\n  0x03, 0x00, 0x60, 0x0C, 0x01, 0x80, 0x3F, 0xCF, 0xF9, 0x80, 0x30, 0x06,\n  0x00, 0xDE, 0x1F, 0xE7, 0x0E, 0x00, 0xE0, 0x0C, 0x01, 0x80, 0x30, 0x07,\n  0x81, 0xF8, 0x73, 0xFC, 0x1F, 0x00, 0x0F, 0x07, 0xF9, 0xC3, 0x30, 0x74,\n  0x01, 0x80, 0x33, 0xC7, 0xFE, 0xF0, 0xDC, 0x1F, 0x01, 0xE0, 0x3C, 0x06,\n  0xC1, 0xDC, 0x71, 0xFC, 0x1F, 0x00, 0xFF, 0xFF, 0xFC, 0x01, 0x00, 0x60,\n  0x18, 0x02, 0x00, 0xC0, 0x30, 0x06, 0x01, 0x80, 0x30, 0x04, 0x01, 0x80,\n  0x30, 0x06, 0x01, 0x80, 0x30, 0x00, 0x1F, 0x07, 0xF1, 0xC7, 0x30, 0x66,\n  0x0C, 0xC1, 0x8C, 0x61, 0xFC, 0x3F, 0x8E, 0x3B, 0x01, 0xE0, 0x3C, 0x07,\n  0x80, 0xD8, 0x31, 0xFC, 0x1F, 0x00, 0x1F, 0x07, 0xF1, 0xC7, 0x70, 0x6C,\n  0x07, 0x80, 0xF0, 0x1E, 0x07, 0x61, 0xEF, 0xFC, 0x79, 0x80, 0x30, 0x05,\n  0x81, 0x98, 0x73, 0xFC, 0x1E, 0x00, 0xF0, 0x00, 0x03, 0xC0, 0xF0, 0x00,\n  0x0F, 0x56, 0x00, 0x00, 0x07, 0x01, 0xE0, 0xF8, 0x3C, 0x0F, 0x00, 0xE0,\n  0x07, 0xC0, 0x0F, 0x00, 0x3C, 0x00, 0xF0, 0x01, 0xFF, 0xFF, 0xFF, 0x00,\n  0x00, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0x0E, 0x00, 0x78, 0x01, 0xF0, 0x07,\n  0xC0, 0x0F, 0x00, 0x70, 0x1E, 0x0F, 0x03, 0xC0, 0xF0, 0x08, 0x00, 0x1F,\n  0x1F, 0xEE, 0x1B, 0x03, 0xC0, 0xC0, 0x30, 0x0C, 0x06, 0x03, 0x81, 0xC0,\n  0xE0, 0x30, 0x0C, 0x03, 0x00, 0x00, 0x00, 0x0C, 0x03, 0x00, 0x00, 0xFE,\n  0x00, 0x0F, 0xFE, 0x00, 0xF0, 0x3E, 0x07, 0x00, 0x3C, 0x38, 0x00, 0x30,\n  0xC1, 0xE0, 0x66, 0x0F, 0xD9, 0xD8, 0x61, 0xC3, 0xC3, 0x07, 0x0F, 0x1C,\n  0x1C, 0x3C, 0x60, 0x60, 0xF1, 0x81, 0x83, 0xC6, 0x06, 0x1B, 0x18, 0x38,\n  0xEE, 0x71, 0xE7, 0x18, 0xFD, 0xF8, 0x71, 0xE7, 0xC0, 0xE0, 0x00, 0x01,\n  0xE0, 0x00, 0x01, 0xFF, 0xC0, 0x01, 0xFC, 0x00, 0x03, 0xC0, 0x03, 0xC0,\n  0x03, 0xC0, 0x07, 0xE0, 0x06, 0x60, 0x06, 0x60, 0x0E, 0x70, 0x0C, 0x30,\n  0x0C, 0x30, 0x1C, 0x38, 0x18, 0x18, 0x1F, 0xF8, 0x3F, 0xFC, 0x30, 0x1C,\n  0x30, 0x0C, 0x70, 0x0E, 0x60, 0x06, 0x60, 0x06, 0xFF, 0xC7, 0xFF, 0x30,\n  0x19, 0x80, 0x6C, 0x03, 0x60, 0x1B, 0x00, 0xD8, 0x0C, 0xFF, 0xC7, 0xFF,\n  0x30, 0x0D, 0x80, 0x3C, 0x01, 0xE0, 0x0F, 0x00, 0x78, 0x06, 0xFF, 0xF7,\n  0xFE, 0x00, 0x07, 0xE0, 0x3F, 0xF0, 0xE0, 0x73, 0x80, 0x66, 0x00, 0x6C,\n  0x00, 0x30, 0x00, 0x60, 0x00, 0xC0, 0x01, 0x80, 0x03, 0x00, 0x06, 0x00,\n  0x06, 0x00, 0x6C, 0x00, 0xDC, 0x03, 0x1E, 0x0E, 0x1F, 0xF8, 0x0F, 0xC0,\n  0xFF, 0x83, 0xFF, 0x8C, 0x07, 0x30, 0x0E, 0xC0, 0x1B, 0x00, 0x7C, 0x00,\n  0xF0, 0x03, 0xC0, 0x0F, 0x00, 0x3C, 0x00, 0xF0, 0x03, 0xC0, 0x1F, 0x00,\n  0x6C, 0x03, 0xB0, 0x1C, 0xFF, 0xE3, 0xFF, 0x00, 0xFF, 0xFF, 0xFF, 0xC0,\n  0x0C, 0x00, 0xC0, 0x0C, 0x00, 0xC0, 0x0C, 0x00, 0xFF, 0xEF, 0xFE, 0xC0,\n  0x0C, 0x00, 0xC0, 0x0C, 0x00, 0xC0, 0x0C, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0x00, 0x60, 0x0C, 0x01, 0x80, 0x30, 0x06, 0x00, 0xFF, 0xDF,\n  0xFB, 0x00, 0x60, 0x0C, 0x01, 0x80, 0x30, 0x06, 0x00, 0xC0, 0x18, 0x00,\n  0x07, 0xF0, 0x1F, 0xFC, 0x3C, 0x1E, 0x70, 0x06, 0x60, 0x03, 0xE0, 0x00,\n  0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x7F, 0xC0, 0x7F, 0xC0, 0x03, 0xC0, 0x03,\n  0x60, 0x03, 0x60, 0x07, 0x30, 0x0F, 0x3C, 0x1F, 0x1F, 0xFB, 0x07, 0xE1,\n  0xC0, 0x1E, 0x00, 0xF0, 0x07, 0x80, 0x3C, 0x01, 0xE0, 0x0F, 0x00, 0x78,\n  0x03, 0xFF, 0xFF, 0xFF, 0xF0, 0x07, 0x80, 0x3C, 0x01, 0xE0, 0x0F, 0x00,\n  0x78, 0x03, 0xC0, 0x1E, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0x01,\n  0x80, 0xC0, 0x60, 0x30, 0x18, 0x0C, 0x06, 0x03, 0x01, 0x80, 0xC0, 0x60,\n  0x3C, 0x1E, 0x0F, 0x07, 0xC7, 0x7F, 0x1F, 0x00, 0xC0, 0x3B, 0x01, 0xCC,\n  0x0E, 0x30, 0x70, 0xC3, 0x83, 0x1C, 0x0C, 0xE0, 0x33, 0x80, 0xDE, 0x03,\n  0xDC, 0x0E, 0x38, 0x30, 0x60, 0xC1, 0xC3, 0x03, 0x8C, 0x06, 0x30, 0x1C,\n  0xC0, 0x3B, 0x00, 0x60, 0xC0, 0x30, 0x0C, 0x03, 0x00, 0xC0, 0x30, 0x0C,\n  0x03, 0x00, 0xC0, 0x30, 0x0C, 0x03, 0x00, 0xC0, 0x30, 0x0C, 0x03, 0x00,\n  0xFF, 0xFF, 0xF0, 0xE0, 0x07, 0xE0, 0x07, 0xF0, 0x0F, 0xF0, 0x0F, 0xD0,\n  0x0F, 0xD8, 0x1B, 0xD8, 0x1B, 0xD8, 0x1B, 0xCC, 0x33, 0xCC, 0x33, 0xCC,\n  0x33, 0xC6, 0x63, 0xC6, 0x63, 0xC6, 0x63, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3,\n  0xC3, 0xC1, 0x83, 0xE0, 0x1F, 0x00, 0xFC, 0x07, 0xE0, 0x3D, 0x81, 0xEE,\n  0x0F, 0x30, 0x79, 0xC3, 0xC6, 0x1E, 0x18, 0xF0, 0xE7, 0x83, 0x3C, 0x1D,\n  0xE0, 0x6F, 0x01, 0xF8, 0x0F, 0xC0, 0x3E, 0x01, 0xC0, 0x03, 0xE0, 0x0F,\n  0xFC, 0x0F, 0x07, 0x86, 0x00, 0xC6, 0x00, 0x33, 0x00, 0x1B, 0x00, 0x07,\n  0x80, 0x03, 0xC0, 0x01, 0xE0, 0x00, 0xF0, 0x00, 0x78, 0x00, 0x36, 0x00,\n  0x33, 0x00, 0x18, 0xC0, 0x18, 0x78, 0x3C, 0x1F, 0xFC, 0x03, 0xF8, 0x00,\n  0xFF, 0x8F, 0xFE, 0xC0, 0x6C, 0x03, 0xC0, 0x3C, 0x03, 0xC0, 0x3C, 0x07,\n  0xFF, 0xEF, 0xFC, 0xC0, 0x0C, 0x00, 0xC0, 0x0C, 0x00, 0xC0, 0x0C, 0x00,\n  0xC0, 0x0C, 0x00, 0x03, 0xE0, 0x0F, 0xFC, 0x0F, 0x07, 0x86, 0x00, 0xC6,\n  0x00, 0x33, 0x00, 0x1B, 0x00, 0x07, 0x80, 0x03, 0xC0, 0x01, 0xE0, 0x00,\n  0xF0, 0x00, 0x78, 0x00, 0x36, 0x00, 0x33, 0x01, 0x98, 0xC0, 0xFC, 0x78,\n  0x3C, 0x1F, 0xFF, 0x03, 0xF9, 0x80, 0x00, 0x40, 0xFF, 0xC3, 0xFF, 0xCC,\n  0x03, 0xB0, 0x06, 0xC0, 0x1B, 0x00, 0x6C, 0x01, 0xB0, 0x0C, 0xFF, 0xE3,\n  0xFF, 0xCC, 0x03, 0xB0, 0x06, 0xC0, 0x1B, 0x00, 0x6C, 0x01, 0xB0, 0x06,\n  0xC0, 0x1B, 0x00, 0x70, 0x0F, 0xE0, 0x7F, 0xC3, 0x83, 0x9C, 0x07, 0x60,\n  0x0D, 0x80, 0x06, 0x00, 0x1E, 0x00, 0x3F, 0x80, 0x3F, 0xC0, 0x0F, 0x80,\n  0x07, 0xC0, 0x0F, 0x00, 0x3E, 0x00, 0xDE, 0x0E, 0x3F, 0xF0, 0x3F, 0x80,\n  0xFF, 0xFF, 0xFF, 0x06, 0x00, 0x60, 0x06, 0x00, 0x60, 0x06, 0x00, 0x60,\n  0x06, 0x00, 0x60, 0x06, 0x00, 0x60, 0x06, 0x00, 0x60, 0x06, 0x00, 0x60,\n  0x06, 0x00, 0x60, 0xC0, 0x1E, 0x00, 0xF0, 0x07, 0x80, 0x3C, 0x01, 0xE0,\n  0x0F, 0x00, 0x78, 0x03, 0xC0, 0x1E, 0x00, 0xF0, 0x07, 0x80, 0x3C, 0x01,\n  0xE0, 0x0F, 0x80, 0xEE, 0x0E, 0x3F, 0xE0, 0x7C, 0x00, 0x60, 0x06, 0xC0,\n  0x1D, 0xC0, 0x31, 0x80, 0x63, 0x01, 0xC7, 0x03, 0x06, 0x06, 0x0C, 0x1C,\n  0x1C, 0x30, 0x18, 0x60, 0x31, 0xC0, 0x73, 0x00, 0x66, 0x00, 0xDC, 0x01,\n  0xF0, 0x01, 0xE0, 0x03, 0xC0, 0x07, 0x00, 0xE0, 0x30, 0x1D, 0x80, 0xE0,\n  0x76, 0x07, 0x81, 0xD8, 0x1E, 0x06, 0x70, 0x7C, 0x18, 0xC1, 0xB0, 0xE3,\n  0x0C, 0xC3, 0x8C, 0x33, 0x0C, 0x38, 0xC6, 0x30, 0x67, 0x18, 0xC1, 0x98,\n  0x67, 0x06, 0x61, 0xD8, 0x1D, 0x83, 0x60, 0x3C, 0x0D, 0x80, 0xF0, 0x3E,\n  0x03, 0xC0, 0x70, 0x0F, 0x01, 0xC0, 0x18, 0x07, 0x00, 0x70, 0x0E, 0x60,\n  0x38, 0xE0, 0x60, 0xE1, 0xC0, 0xC3, 0x01, 0xCC, 0x01, 0xF8, 0x01, 0xE0,\n  0x03, 0x80, 0x07, 0x80, 0x1F, 0x00, 0x33, 0x00, 0xE7, 0x03, 0x86, 0x06,\n  0x0E, 0x1C, 0x0E, 0x70, 0x0C, 0xC0, 0x1C, 0x60, 0x06, 0x70, 0x0E, 0x30,\n  0x1C, 0x38, 0x18, 0x1C, 0x38, 0x0C, 0x30, 0x0E, 0x70, 0x06, 0x60, 0x03,\n  0xC0, 0x03, 0xC0, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01,\n  0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0xFF, 0xFF, 0xFF, 0xC0, 0x0E,\n  0x00, 0xE0, 0x0E, 0x00, 0x60, 0x07, 0x00, 0x70, 0x07, 0x00, 0x30, 0x03,\n  0x80, 0x38, 0x03, 0x80, 0x18, 0x01, 0xC0, 0x1C, 0x00, 0xFF, 0xFF, 0xFF,\n  0xC0, 0xFF, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCF,\n  0xF0, 0x81, 0x81, 0x02, 0x06, 0x04, 0x08, 0x18, 0x10, 0x20, 0x60, 0x40,\n  0x81, 0x81, 0x02, 0x06, 0x04, 0xFF, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33,\n  0x33, 0x33, 0x33, 0x3F, 0xF0, 0x0C, 0x0E, 0x05, 0x86, 0xC3, 0x21, 0x19,\n  0x8C, 0x83, 0xC1, 0x80, 0xFF, 0xFE, 0xE3, 0x8C, 0x30, 0x3F, 0x07, 0xF8,\n  0xE1, 0xCC, 0x0C, 0x00, 0xC0, 0x1C, 0x3F, 0xCF, 0x8C, 0xC0, 0xCC, 0x0C,\n  0xE3, 0xC7, 0xEF, 0x3C, 0x70, 0xC0, 0x0C, 0x00, 0xC0, 0x0C, 0x00, 0xC0,\n  0x0C, 0xF8, 0xDF, 0xCF, 0x0E, 0xE0, 0x7C, 0x03, 0xC0, 0x3C, 0x03, 0xC0,\n  0x3C, 0x03, 0xE0, 0x6F, 0x0E, 0xDF, 0xCC, 0xF8, 0x1F, 0x0F, 0xE7, 0x1B,\n  0x83, 0xC0, 0x30, 0x0C, 0x03, 0x00, 0xC0, 0x38, 0x37, 0x1C, 0xFE, 0x1F,\n  0x00, 0x00, 0x60, 0x0C, 0x01, 0x80, 0x30, 0x06, 0x3C, 0xCF, 0xFB, 0x8F,\n  0xE0, 0xF8, 0x0F, 0x01, 0xE0, 0x3C, 0x07, 0x80, 0xF8, 0x3B, 0x8F, 0x3F,\n  0x63, 0xCC, 0x1F, 0x07, 0xF1, 0xC7, 0x70, 0x3C, 0x07, 0xFF, 0xFF, 0xFE,\n  0x00, 0xC0, 0x1C, 0x0D, 0xC3, 0x1F, 0xE1, 0xF0, 0x3B, 0xD8, 0xC6, 0x7F,\n  0xEC, 0x63, 0x18, 0xC6, 0x31, 0x8C, 0x63, 0x00, 0x1E, 0x67, 0xFD, 0xC7,\n  0xF0, 0x7C, 0x07, 0x80, 0xF0, 0x1E, 0x03, 0xC0, 0x7C, 0x1D, 0xC7, 0x9F,\n  0xB1, 0xE6, 0x00, 0xC0, 0x3E, 0x0E, 0x7F, 0xC7, 0xE0, 0xC0, 0x30, 0x0C,\n  0x03, 0x00, 0xC0, 0x33, 0xCD, 0xFB, 0xC7, 0xE0, 0xF0, 0x3C, 0x0F, 0x03,\n  0xC0, 0xF0, 0x3C, 0x0F, 0x03, 0xC0, 0xF0, 0x30, 0xF0, 0x3F, 0xFF, 0xFF,\n  0xF0, 0x33, 0x00, 0x03, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x3F,\n  0xE0, 0xC0, 0x18, 0x03, 0x00, 0x60, 0x0C, 0x01, 0x83, 0x30, 0xC6, 0x30,\n  0xCC, 0x1B, 0x83, 0xF0, 0x77, 0x0C, 0x61, 0x8E, 0x30, 0xE6, 0x0C, 0xC1,\n  0xD8, 0x18, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0xCF, 0x1F, 0x6F, 0xDF, 0xFC,\n  0x78, 0xFC, 0x18, 0x3C, 0x0C, 0x1E, 0x06, 0x0F, 0x03, 0x07, 0x81, 0x83,\n  0xC0, 0xC1, 0xE0, 0x60, 0xF0, 0x30, 0x78, 0x18, 0x3C, 0x0C, 0x18, 0xCF,\n  0x37, 0xEF, 0x1F, 0x83, 0xC0, 0xF0, 0x3C, 0x0F, 0x03, 0xC0, 0xF0, 0x3C,\n  0x0F, 0x03, 0xC0, 0xC0, 0x1F, 0x07, 0xF1, 0xC7, 0x70, 0x7C, 0x07, 0x80,\n  0xF0, 0x1E, 0x03, 0xC0, 0x7C, 0x1D, 0xC7, 0x1F, 0xC1, 0xF0, 0xCF, 0x8D,\n  0xFC, 0xF0, 0xEE, 0x06, 0xC0, 0x3C, 0x03, 0xC0, 0x3C, 0x03, 0xC0, 0x3E,\n  0x07, 0xF0, 0xEF, 0xFC, 0xCF, 0x8C, 0x00, 0xC0, 0x0C, 0x00, 0xC0, 0x00,\n  0x1E, 0x67, 0xFD, 0xC7, 0xF0, 0x7C, 0x07, 0x80, 0xF0, 0x1E, 0x03, 0xC0,\n  0x7C, 0x1D, 0xC7, 0x9F, 0xF1, 0xE6, 0x00, 0xC0, 0x18, 0x03, 0x00, 0x60,\n  0xCF, 0x7F, 0x38, 0xC3, 0x0C, 0x30, 0xC3, 0x0C, 0x30, 0xC0, 0x3E, 0x1F,\n  0xEE, 0x1B, 0x00, 0xC0, 0x3C, 0x07, 0xF0, 0x3E, 0x01, 0xF0, 0x3E, 0x1D,\n  0xFE, 0x3E, 0x00, 0x63, 0x19, 0xFF, 0xB1, 0x8C, 0x63, 0x18, 0xC6, 0x31,\n  0xE7, 0xC0, 0xF0, 0x3C, 0x0F, 0x03, 0xC0, 0xF0, 0x3C, 0x0F, 0x03, 0xC0,\n  0xF0, 0x7E, 0x3D, 0xFB, 0x3C, 0xC0, 0xE0, 0x66, 0x06, 0x60, 0x67, 0x0C,\n  0x30, 0xC3, 0x0C, 0x39, 0x81, 0x98, 0x19, 0x81, 0xF0, 0x0F, 0x00, 0xE0,\n  0x0E, 0x00, 0xC1, 0xC1, 0xB0, 0xE1, 0xD8, 0x70, 0xCC, 0x2C, 0x66, 0x36,\n  0x31, 0x9B, 0x18, 0xCD, 0x98, 0x64, 0x6C, 0x16, 0x36, 0x0F, 0x1A, 0x07,\n  0x8F, 0x03, 0x83, 0x80, 0xC1, 0xC0, 0x60, 0xEE, 0x18, 0xC6, 0x0C, 0xC1,\n  0xF0, 0x1C, 0x01, 0x80, 0x78, 0x1B, 0x03, 0x30, 0xC7, 0x30, 0x66, 0x06,\n  0xE0, 0x6C, 0x0D, 0x83, 0x38, 0x63, 0x0C, 0x63, 0x0E, 0x60, 0xCC, 0x1B,\n  0x03, 0x60, 0x3C, 0x07, 0x00, 0xE0, 0x18, 0x03, 0x00, 0xE0, 0x78, 0x0E,\n  0x00, 0xFF, 0xFF, 0xF0, 0x18, 0x0C, 0x07, 0x03, 0x81, 0xC0, 0x60, 0x30,\n  0x18, 0x0E, 0x03, 0xFF, 0xFF, 0xC0, 0x19, 0xCC, 0x63, 0x18, 0xC6, 0x31,\n  0x99, 0x86, 0x18, 0xC6, 0x31, 0x8C, 0x63, 0x1C, 0x60, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFC, 0xC7, 0x18, 0xC6, 0x31, 0x8C, 0x63, 0x0C, 0x33, 0x31,\n  0x8C, 0x63, 0x18, 0xC6, 0x73, 0x00, 0x70, 0x3E, 0x09, 0xE4, 0x1F, 0x03,\n  0x80 };\n\nconst GFXglyph FreeSans12pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,   6,    0,    1 },   // 0x20 ' '\n  {     0,   2,  18,   8,    3,  -17 },   // 0x21 '!'\n  {     5,   6,   6,   8,    1,  -16 },   // 0x22 '\"'\n  {    10,  13,  16,  13,    0,  -15 },   // 0x23 '#'\n  {    36,  11,  20,  13,    1,  -17 },   // 0x24 '$'\n  {    64,  20,  17,  21,    1,  -16 },   // 0x25 '%'\n  {   107,  14,  17,  16,    1,  -16 },   // 0x26 '&'\n  {   137,   2,   6,   5,    1,  -16 },   // 0x27 '''\n  {   139,   5,  23,   8,    2,  -17 },   // 0x28 '('\n  {   154,   5,  23,   8,    1,  -17 },   // 0x29 ')'\n  {   169,   7,   7,   9,    1,  -17 },   // 0x2A '*'\n  {   176,  10,  11,  14,    2,  -10 },   // 0x2B '+'\n  {   190,   2,   6,   7,    2,   -1 },   // 0x2C ','\n  {   192,   6,   2,   8,    1,   -7 },   // 0x2D '-'\n  {   194,   2,   2,   6,    2,   -1 },   // 0x2E '.'\n  {   195,   7,  18,   7,    0,  -17 },   // 0x2F '/'\n  {   211,  11,  17,  13,    1,  -16 },   // 0x30 '0'\n  {   235,   5,  17,  13,    3,  -16 },   // 0x31 '1'\n  {   246,  11,  17,  13,    1,  -16 },   // 0x32 '2'\n  {   270,  11,  17,  13,    1,  -16 },   // 0x33 '3'\n  {   294,  11,  17,  13,    1,  -16 },   // 0x34 '4'\n  {   318,  11,  17,  13,    1,  -16 },   // 0x35 '5'\n  {   342,  11,  17,  13,    1,  -16 },   // 0x36 '6'\n  {   366,  11,  17,  13,    1,  -16 },   // 0x37 '7'\n  {   390,  11,  17,  13,    1,  -16 },   // 0x38 '8'\n  {   414,  11,  17,  13,    1,  -16 },   // 0x39 '9'\n  {   438,   2,  13,   6,    2,  -12 },   // 0x3A ':'\n  {   442,   2,  16,   6,    2,  -11 },   // 0x3B ';'\n  {   446,  12,  12,  14,    1,  -11 },   // 0x3C '<'\n  {   464,  12,   6,  14,    1,   -8 },   // 0x3D '='\n  {   473,  12,  12,  14,    1,  -11 },   // 0x3E '>'\n  {   491,  10,  18,  13,    2,  -17 },   // 0x3F '?'\n  {   514,  22,  21,  24,    1,  -17 },   // 0x40 '@'\n  {   572,  16,  18,  16,    0,  -17 },   // 0x41 'A'\n  {   608,  13,  18,  16,    2,  -17 },   // 0x42 'B'\n  {   638,  15,  18,  17,    1,  -17 },   // 0x43 'C'\n  {   672,  14,  18,  17,    2,  -17 },   // 0x44 'D'\n  {   704,  12,  18,  15,    2,  -17 },   // 0x45 'E'\n  {   731,  11,  18,  14,    2,  -17 },   // 0x46 'F'\n  {   756,  16,  18,  18,    1,  -17 },   // 0x47 'G'\n  {   792,  13,  18,  17,    2,  -17 },   // 0x48 'H'\n  {   822,   2,  18,   7,    2,  -17 },   // 0x49 'I'\n  {   827,   9,  18,  13,    1,  -17 },   // 0x4A 'J'\n  {   848,  14,  18,  16,    2,  -17 },   // 0x4B 'K'\n  {   880,  10,  18,  14,    2,  -17 },   // 0x4C 'L'\n  {   903,  16,  18,  20,    2,  -17 },   // 0x4D 'M'\n  {   939,  13,  18,  18,    2,  -17 },   // 0x4E 'N'\n  {   969,  17,  18,  19,    1,  -17 },   // 0x4F 'O'\n  {  1008,  12,  18,  16,    2,  -17 },   // 0x50 'P'\n  {  1035,  17,  19,  19,    1,  -17 },   // 0x51 'Q'\n  {  1076,  14,  18,  17,    2,  -17 },   // 0x52 'R'\n  {  1108,  14,  18,  16,    1,  -17 },   // 0x53 'S'\n  {  1140,  12,  18,  15,    1,  -17 },   // 0x54 'T'\n  {  1167,  13,  18,  17,    2,  -17 },   // 0x55 'U'\n  {  1197,  15,  18,  15,    0,  -17 },   // 0x56 'V'\n  {  1231,  22,  18,  22,    0,  -17 },   // 0x57 'W'\n  {  1281,  15,  18,  16,    0,  -17 },   // 0x58 'X'\n  {  1315,  16,  18,  16,    0,  -17 },   // 0x59 'Y'\n  {  1351,  13,  18,  15,    1,  -17 },   // 0x5A 'Z'\n  {  1381,   4,  23,   7,    2,  -17 },   // 0x5B '['\n  {  1393,   7,  18,   7,    0,  -17 },   // 0x5C '\\'\n  {  1409,   4,  23,   7,    1,  -17 },   // 0x5D ']'\n  {  1421,   9,   9,  11,    1,  -16 },   // 0x5E '^'\n  {  1432,  15,   1,  13,   -1,    4 },   // 0x5F '_'\n  {  1434,   5,   4,   6,    1,  -17 },   // 0x60 '`'\n  {  1437,  12,  13,  13,    1,  -12 },   // 0x61 'a'\n  {  1457,  12,  18,  13,    1,  -17 },   // 0x62 'b'\n  {  1484,  10,  13,  12,    1,  -12 },   // 0x63 'c'\n  {  1501,  11,  18,  13,    1,  -17 },   // 0x64 'd'\n  {  1526,  11,  13,  13,    1,  -12 },   // 0x65 'e'\n  {  1544,   5,  18,   7,    1,  -17 },   // 0x66 'f'\n  {  1556,  11,  18,  13,    1,  -12 },   // 0x67 'g'\n  {  1581,  10,  18,  13,    1,  -17 },   // 0x68 'h'\n  {  1604,   2,  18,   5,    2,  -17 },   // 0x69 'i'\n  {  1609,   4,  23,   6,    0,  -17 },   // 0x6A 'j'\n  {  1621,  11,  18,  12,    1,  -17 },   // 0x6B 'k'\n  {  1646,   2,  18,   5,    1,  -17 },   // 0x6C 'l'\n  {  1651,  17,  13,  19,    1,  -12 },   // 0x6D 'm'\n  {  1679,  10,  13,  13,    1,  -12 },   // 0x6E 'n'\n  {  1696,  11,  13,  13,    1,  -12 },   // 0x6F 'o'\n  {  1714,  12,  17,  13,    1,  -12 },   // 0x70 'p'\n  {  1740,  11,  17,  13,    1,  -12 },   // 0x71 'q'\n  {  1764,   6,  13,   8,    1,  -12 },   // 0x72 'r'\n  {  1774,  10,  13,  12,    1,  -12 },   // 0x73 's'\n  {  1791,   5,  16,   7,    1,  -15 },   // 0x74 't'\n  {  1801,  10,  13,  13,    1,  -12 },   // 0x75 'u'\n  {  1818,  12,  13,  12,    0,  -12 },   // 0x76 'v'\n  {  1838,  17,  13,  17,    0,  -12 },   // 0x77 'w'\n  {  1866,  11,  13,  11,    0,  -12 },   // 0x78 'x'\n  {  1884,  11,  18,  11,    0,  -12 },   // 0x79 'y'\n  {  1909,  10,  13,  12,    1,  -12 },   // 0x7A 'z'\n  {  1926,   5,  23,   8,    1,  -17 },   // 0x7B '{'\n  {  1941,   2,  23,   6,    2,  -17 },   // 0x7C '|'\n  {  1947,   5,  23,   8,    2,  -17 },   // 0x7D '}'\n  {  1962,  10,   5,  12,    1,  -10 } }; // 0x7E '~'\n\nconst GFXfont FreeSans12pt7b PROGMEM = {\n  (uint8_t  *)FreeSans12pt7bBitmaps,\n  (GFXglyph *)FreeSans12pt7bGlyphs,\n  0x20, 0x7E, 29 };\n\n// Approx. 2641 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeSans18pt7b.h",
    "content": "const uint8_t FreeSans18pt7bBitmaps[] PROGMEM = {\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xE9, 0x20, 0x3F, 0xFC, 0xE3, 0xF1,\n  0xF8, 0xFC, 0x7E, 0x3F, 0x1F, 0x8E, 0x82, 0x41, 0x00, 0x01, 0xC3, 0x80,\n  0x38, 0x70, 0x06, 0x0E, 0x00, 0xC1, 0x80, 0x38, 0x70, 0x07, 0x0E, 0x0F,\n  0xFF, 0xF9, 0xFF, 0xFF, 0x3F, 0xFF, 0xE0, 0xE1, 0xC0, 0x1C, 0x38, 0x03,\n  0x87, 0x00, 0x70, 0xE0, 0x0C, 0x18, 0x3F, 0xFF, 0xF7, 0xFF, 0xFE, 0xFF,\n  0xFF, 0xC1, 0xC3, 0x80, 0x30, 0x60, 0x06, 0x0C, 0x01, 0xC3, 0x80, 0x38,\n  0x70, 0x07, 0x0E, 0x00, 0xC1, 0x80, 0x03, 0x00, 0x0F, 0xC0, 0x3F, 0xF0,\n  0x3F, 0xF8, 0x7B, 0x3C, 0xF3, 0x1C, 0xE3, 0x0E, 0xE3, 0x0E, 0xE3, 0x0E,\n  0xE3, 0x00, 0xE3, 0x00, 0xF3, 0x00, 0x7B, 0x00, 0x7F, 0x80, 0x1F, 0xF0,\n  0x07, 0xFC, 0x03, 0x7E, 0x03, 0x0F, 0x03, 0x07, 0xE3, 0x07, 0xE3, 0x07,\n  0xE3, 0x07, 0xE3, 0x0F, 0x73, 0x3E, 0x7F, 0xFC, 0x3F, 0xF8, 0x0F, 0xE0,\n  0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x78, 0x00,\n  0xE0, 0x0F, 0xF0, 0x06, 0x00, 0xFF, 0xC0, 0x70, 0x07, 0x0E, 0x07, 0x00,\n  0x70, 0x38, 0x38, 0x03, 0x00, 0xC3, 0x80, 0x18, 0x06, 0x1C, 0x00, 0xE0,\n  0x71, 0xC0, 0x03, 0x87, 0x8C, 0x00, 0x1F, 0xF8, 0xE0, 0x00, 0x7F, 0x86,\n  0x00, 0x01, 0xF8, 0x70, 0x00, 0x00, 0x03, 0x03, 0xC0, 0x00, 0x38, 0x7F,\n  0x80, 0x01, 0x87, 0xFE, 0x00, 0x1C, 0x38, 0x70, 0x00, 0xC3, 0x81, 0xC0,\n  0x0E, 0x18, 0x06, 0x00, 0xE0, 0xC0, 0x30, 0x07, 0x07, 0x03, 0x80, 0x70,\n  0x1C, 0x38, 0x03, 0x80, 0xFF, 0xC0, 0x38, 0x03, 0xFC, 0x01, 0x80, 0x07,\n  0x80, 0x01, 0xF0, 0x00, 0x7F, 0x80, 0x0F, 0xFC, 0x01, 0xE1, 0xE0, 0x1C,\n  0x0E, 0x01, 0xC0, 0xE0, 0x1C, 0x0E, 0x01, 0xE1, 0xE0, 0x0E, 0x3C, 0x00,\n  0x77, 0x80, 0x07, 0xF0, 0x00, 0x7C, 0x00, 0x0F, 0xE0, 0x03, 0xCF, 0x1C,\n  0x78, 0x79, 0xC7, 0x03, 0xDC, 0xE0, 0x1F, 0x8E, 0x00, 0xF8, 0xE0, 0x0F,\n  0x0E, 0x00, 0x70, 0xF0, 0x0F, 0x87, 0xC3, 0xFC, 0x7F, 0xFD, 0xC3, 0xFF,\n  0x0E, 0x0F, 0xC0, 0xF0, 0xFF, 0xFF, 0xFA, 0x40, 0x06, 0x06, 0x0C, 0x0C,\n  0x18, 0x18, 0x38, 0x30, 0x70, 0x70, 0x70, 0x60, 0xE0, 0xE0, 0xE0, 0xE0,\n  0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0x60, 0x70, 0x70, 0x70, 0x30, 0x38, 0x18,\n  0x18, 0x0C, 0x0C, 0x06, 0x03, 0xC0, 0x60, 0x30, 0x30, 0x38, 0x18, 0x1C,\n  0x0C, 0x0E, 0x0E, 0x0E, 0x06, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,\n  0x07, 0x07, 0x06, 0x0E, 0x0E, 0x0E, 0x0C, 0x1C, 0x18, 0x38, 0x30, 0x30,\n  0x60, 0xC0, 0x0C, 0x03, 0x00, 0xC3, 0xB7, 0xFF, 0xC7, 0x81, 0xE0, 0xEC,\n  0x73, 0x88, 0x40, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01,\n  0x80, 0x01, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x80, 0x01,\n  0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0xFF,\n  0xF6, 0xDA, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0x00, 0xC0, 0x30, 0x18,\n  0x06, 0x01, 0x80, 0xC0, 0x30, 0x0C, 0x06, 0x01, 0x80, 0x60, 0x30, 0x0C,\n  0x03, 0x00, 0xC0, 0x60, 0x18, 0x06, 0x03, 0x00, 0xC0, 0x30, 0x18, 0x06,\n  0x01, 0x80, 0xC0, 0x30, 0x00, 0x07, 0xE0, 0x0F, 0xF8, 0x1F, 0xFC, 0x3C,\n  0x3C, 0x78, 0x1E, 0x70, 0x0E, 0x70, 0x0E, 0xE0, 0x07, 0xE0, 0x07, 0xE0,\n  0x07, 0xE0, 0x07, 0xE0, 0x07, 0xE0, 0x07, 0xE0, 0x07, 0xE0, 0x07, 0xE0,\n  0x07, 0xE0, 0x07, 0xE0, 0x0F, 0x70, 0x0E, 0x70, 0x0E, 0x78, 0x1E, 0x3C,\n  0x3C, 0x1F, 0xF8, 0x1F, 0xF0, 0x07, 0xE0, 0x03, 0x03, 0x07, 0x0F, 0x3F,\n  0xFF, 0xFF, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,\n  0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0xE0, 0x1F, 0xF8,\n  0x3F, 0xFC, 0x7C, 0x3E, 0x70, 0x0F, 0xF0, 0x0F, 0xE0, 0x07, 0xE0, 0x07,\n  0x00, 0x07, 0x00, 0x07, 0x00, 0x0F, 0x00, 0x1E, 0x00, 0x3C, 0x00, 0xF8,\n  0x03, 0xF0, 0x07, 0xC0, 0x1F, 0x00, 0x3C, 0x00, 0x38, 0x00, 0x70, 0x00,\n  0x60, 0x00, 0xE0, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x07, 0xF0,\n  0x07, 0xFE, 0x07, 0xFF, 0x87, 0x83, 0xC3, 0x80, 0xF3, 0x80, 0x39, 0xC0,\n  0x1C, 0xE0, 0x0E, 0x00, 0x07, 0x00, 0x0F, 0x00, 0x7F, 0x00, 0x3F, 0x00,\n  0x1F, 0xE0, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x07, 0x00, 0x03, 0xF0, 0x01,\n  0xF8, 0x00, 0xFE, 0x00, 0x77, 0x00, 0x73, 0xE0, 0xF8, 0xFF, 0xF8, 0x3F,\n  0xF8, 0x07, 0xF0, 0x00, 0x00, 0x38, 0x00, 0x38, 0x00, 0x78, 0x00, 0xF8,\n  0x00, 0xF8, 0x01, 0xF8, 0x03, 0xB8, 0x03, 0x38, 0x07, 0x38, 0x0E, 0x38,\n  0x1C, 0x38, 0x18, 0x38, 0x38, 0x38, 0x70, 0x38, 0x60, 0x38, 0xE0, 0x38,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x38, 0x00, 0x38, 0x00, 0x38,\n  0x00, 0x38, 0x00, 0x38, 0x00, 0x38, 0x1F, 0xFF, 0x0F, 0xFF, 0x8F, 0xFF,\n  0xC7, 0x00, 0x03, 0x80, 0x01, 0xC0, 0x00, 0xE0, 0x00, 0x70, 0x00, 0x39,\n  0xF0, 0x3F, 0xFE, 0x1F, 0xFF, 0x8F, 0x83, 0xE7, 0x00, 0xF0, 0x00, 0x3C,\n  0x00, 0x0E, 0x00, 0x07, 0x00, 0x03, 0x80, 0x01, 0xC0, 0x00, 0xFC, 0x00,\n  0xEF, 0x00, 0x73, 0xC0, 0xF0, 0xFF, 0xF8, 0x3F, 0xF8, 0x07, 0xE0, 0x00,\n  0x03, 0xE0, 0x0F, 0xF8, 0x1F, 0xFC, 0x3C, 0x1E, 0x38, 0x0E, 0x70, 0x0E,\n  0x70, 0x00, 0x60, 0x00, 0xE0, 0x00, 0xE3, 0xE0, 0xEF, 0xF8, 0xFF, 0xFC,\n  0xFC, 0x3E, 0xF0, 0x0E, 0xF0, 0x0F, 0xE0, 0x07, 0xE0, 0x07, 0xE0, 0x07,\n  0x60, 0x07, 0x70, 0x0F, 0x70, 0x0E, 0x3C, 0x3E, 0x3F, 0xFC, 0x1F, 0xF8,\n  0x07, 0xE0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x06, 0x00, 0x0E,\n  0x00, 0x1C, 0x00, 0x18, 0x00, 0x38, 0x00, 0x70, 0x00, 0x60, 0x00, 0xE0,\n  0x00, 0xC0, 0x01, 0xC0, 0x01, 0x80, 0x03, 0x80, 0x03, 0x80, 0x07, 0x00,\n  0x07, 0x00, 0x07, 0x00, 0x0E, 0x00, 0x0E, 0x00, 0x0E, 0x00, 0x0C, 0x00,\n  0x1C, 0x00, 0x1C, 0x00, 0x07, 0xF0, 0x0F, 0xFE, 0x0F, 0xFF, 0x87, 0x83,\n  0xC7, 0x80, 0xF3, 0x80, 0x39, 0xC0, 0x1C, 0xE0, 0x0E, 0x78, 0x0F, 0x1E,\n  0x0F, 0x07, 0xFF, 0x01, 0xFF, 0x03, 0xFF, 0xE3, 0xE0, 0xF9, 0xC0, 0x1D,\n  0xC0, 0x0F, 0xE0, 0x03, 0xF0, 0x01, 0xF8, 0x00, 0xFC, 0x00, 0xF7, 0x00,\n  0x73, 0xE0, 0xF8, 0xFF, 0xF8, 0x3F, 0xF8, 0x07, 0xF0, 0x00, 0x07, 0xE0,\n  0x1F, 0xF8, 0x3F, 0xFC, 0x7C, 0x3C, 0x70, 0x0E, 0xF0, 0x0E, 0xE0, 0x06,\n  0xE0, 0x07, 0xE0, 0x07, 0xE0, 0x07, 0xE0, 0x0F, 0x70, 0x0F, 0x78, 0x3F,\n  0x3F, 0xFF, 0x1F, 0xF7, 0x07, 0xC7, 0x00, 0x07, 0x00, 0x06, 0x00, 0x0E,\n  0x70, 0x0E, 0x70, 0x1C, 0x78, 0x3C, 0x3F, 0xF8, 0x1F, 0xF0, 0x07, 0xC0,\n  0xFF, 0xF0, 0x00, 0x00, 0x00, 0x07, 0xFF, 0x80, 0xFF, 0xF0, 0x00, 0x00,\n  0x00, 0x07, 0xFF, 0xB6, 0xD6, 0x00, 0x00, 0x80, 0x03, 0xC0, 0x07, 0xE0,\n  0x0F, 0xC0, 0x3F, 0x80, 0x7E, 0x00, 0xFC, 0x01, 0xF0, 0x00, 0xE0, 0x00,\n  0x7C, 0x00, 0x1F, 0xC0, 0x01, 0xF8, 0x00, 0x3F, 0x80, 0x07, 0xF0, 0x00,\n  0x7E, 0x00, 0x0F, 0x00, 0x01, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0x80, 0x80, 0x00, 0x70, 0x00, 0x3E, 0x00, 0x0F, 0xE0, 0x00, 0xFC,\n  0x00, 0x1F, 0xC0, 0x03, 0xF8, 0x00, 0x3F, 0x00, 0x07, 0x80, 0x0F, 0xC0,\n  0x1F, 0x80, 0x7F, 0x00, 0xFC, 0x01, 0xF8, 0x03, 0xF0, 0x01, 0xC0, 0x00,\n  0x80, 0x00, 0x00, 0x0F, 0xC0, 0x7F, 0xE1, 0xFF, 0xE3, 0xC3, 0xEF, 0x01,\n  0xFC, 0x01, 0xF8, 0x03, 0xF0, 0x07, 0x00, 0x0E, 0x00, 0x38, 0x00, 0xF0,\n  0x07, 0xC0, 0x1F, 0x00, 0x7C, 0x00, 0xE0, 0x03, 0xC0, 0x07, 0x00, 0x0E,\n  0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xC0, 0x03, 0x80,\n  0x07, 0x00, 0x0E, 0x00, 0x00, 0x07, 0xF8, 0x00, 0x00, 0x3F, 0xFF, 0x00,\n  0x00, 0xFF, 0xFF, 0xC0, 0x01, 0xF8, 0x0F, 0xE0, 0x03, 0xE0, 0x01, 0xF0,\n  0x07, 0x80, 0x00, 0xF8, 0x0F, 0x00, 0x00, 0x3C, 0x1E, 0x00, 0x00, 0x1E,\n  0x3C, 0x03, 0xE0, 0x1E, 0x38, 0x0F, 0xF3, 0x8E, 0x78, 0x1E, 0x3F, 0x0F,\n  0x70, 0x38, 0x1F, 0x07, 0x70, 0x78, 0x0F, 0x07, 0xE0, 0x70, 0x0E, 0x07,\n  0xE0, 0x70, 0x0E, 0x07, 0xE0, 0xE0, 0x0E, 0x07, 0xE0, 0xE0, 0x1C, 0x07,\n  0xE0, 0xE0, 0x1C, 0x0E, 0xE0, 0xE0, 0x1C, 0x0E, 0xE0, 0xE0, 0x38, 0x1C,\n  0xF0, 0x70, 0x78, 0x3C, 0x70, 0x78, 0xFC, 0x78, 0x78, 0x3F, 0xDF, 0xF0,\n  0x38, 0x1F, 0x0F, 0xC0, 0x3C, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00,\n  0x0F, 0x80, 0x00, 0x00, 0x07, 0xF0, 0x0E, 0x00, 0x01, 0xFF, 0xFE, 0x00,\n  0x00, 0x7F, 0xFE, 0x00, 0x00, 0x1F, 0xF0, 0x00, 0x00, 0xF8, 0x00, 0x03,\n  0xE0, 0x00, 0x0F, 0xC0, 0x00, 0x7F, 0x00, 0x01, 0xDC, 0x00, 0x07, 0x78,\n  0x00, 0x3C, 0xE0, 0x00, 0xE3, 0x80, 0x03, 0x8F, 0x00, 0x1E, 0x1C, 0x00,\n  0x70, 0x70, 0x01, 0xC1, 0xE0, 0x0E, 0x03, 0x80, 0x38, 0x0E, 0x00, 0xE0,\n  0x3C, 0x07, 0xFF, 0xF0, 0x1F, 0xFF, 0xE0, 0xFF, 0xFF, 0x83, 0xC0, 0x0E,\n  0x0E, 0x00, 0x3C, 0x78, 0x00, 0xF1, 0xE0, 0x01, 0xC7, 0x00, 0x07, 0xBC,\n  0x00, 0x1E, 0xF0, 0x00, 0x3B, 0x80, 0x00, 0xF0, 0xFF, 0xFC, 0x1F, 0xFF,\n  0xE3, 0xFF, 0xFE, 0x70, 0x03, 0xCE, 0x00, 0x3D, 0xC0, 0x03, 0xB8, 0x00,\n  0x77, 0x00, 0x0E, 0xE0, 0x01, 0xDC, 0x00, 0x73, 0x80, 0x1E, 0x7F, 0xFF,\n  0x8F, 0xFF, 0xF1, 0xFF, 0xFF, 0x38, 0x00, 0xF7, 0x00, 0x0E, 0xE0, 0x00,\n  0xFC, 0x00, 0x1F, 0x80, 0x03, 0xF0, 0x00, 0x7E, 0x00, 0x0F, 0xC0, 0x03,\n  0xF8, 0x00, 0xF7, 0xFF, 0xFC, 0xFF, 0xFF, 0x1F, 0xFF, 0x80, 0x00, 0xFF,\n  0x00, 0x0F, 0xFF, 0x00, 0xFF, 0xFE, 0x07, 0xE0, 0x7C, 0x3E, 0x00, 0x78,\n  0xF0, 0x00, 0xE7, 0x80, 0x03, 0xDC, 0x00, 0x07, 0x70, 0x00, 0x03, 0x80,\n  0x00, 0x0E, 0x00, 0x00, 0x38, 0x00, 0x00, 0xE0, 0x00, 0x03, 0x80, 0x00,\n  0x0E, 0x00, 0x00, 0x38, 0x00, 0x00, 0xE0, 0x00, 0x1D, 0xC0, 0x00, 0x77,\n  0x00, 0x03, 0xDE, 0x00, 0x0E, 0x3C, 0x00, 0x78, 0xF8, 0x03, 0xC1, 0xF8,\n  0x1F, 0x03, 0xFF, 0xF8, 0x03, 0xFF, 0xC0, 0x03, 0xF8, 0x00, 0xFF, 0xF8,\n  0x0F, 0xFF, 0xE0, 0xFF, 0xFF, 0x0E, 0x00, 0xF8, 0xE0, 0x03, 0xCE, 0x00,\n  0x1C, 0xE0, 0x00, 0xEE, 0x00, 0x0E, 0xE0, 0x00, 0xFE, 0x00, 0x07, 0xE0,\n  0x00, 0x7E, 0x00, 0x07, 0xE0, 0x00, 0x7E, 0x00, 0x07, 0xE0, 0x00, 0x7E,\n  0x00, 0x07, 0xE0, 0x00, 0x7E, 0x00, 0x0F, 0xE0, 0x00, 0xEE, 0x00, 0x0E,\n  0xE0, 0x01, 0xEE, 0x00, 0x3C, 0xE0, 0x0F, 0x8F, 0xFF, 0xF0, 0xFF, 0xFE,\n  0x0F, 0xFF, 0x80, 0xFF, 0xFF, 0xBF, 0xFF, 0xEF, 0xFF, 0xFB, 0x80, 0x00,\n  0xE0, 0x00, 0x38, 0x00, 0x0E, 0x00, 0x03, 0x80, 0x00, 0xE0, 0x00, 0x38,\n  0x00, 0x0E, 0x00, 0x03, 0xFF, 0xFE, 0xFF, 0xFF, 0xBF, 0xFF, 0xEE, 0x00,\n  0x03, 0x80, 0x00, 0xE0, 0x00, 0x38, 0x00, 0x0E, 0x00, 0x03, 0x80, 0x00,\n  0xE0, 0x00, 0x38, 0x00, 0x0E, 0x00, 0x03, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0x00, 0x0E, 0x00,\n  0x07, 0x00, 0x03, 0x80, 0x01, 0xC0, 0x00, 0xE0, 0x00, 0x70, 0x00, 0x38,\n  0x00, 0x1F, 0xFF, 0xCF, 0xFF, 0xE7, 0xFF, 0xF3, 0x80, 0x01, 0xC0, 0x00,\n  0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C, 0x00, 0x0E, 0x00, 0x07, 0x00,\n  0x03, 0x80, 0x01, 0xC0, 0x00, 0xE0, 0x00, 0x70, 0x00, 0x00, 0x00, 0x7F,\n  0x80, 0x03, 0xFF, 0xE0, 0x07, 0xFF, 0xF8, 0x0F, 0x80, 0xFC, 0x1E, 0x00,\n  0x3E, 0x3C, 0x00, 0x0E, 0x78, 0x00, 0x0F, 0x70, 0x00, 0x07, 0x70, 0x00,\n  0x00, 0xE0, 0x00, 0x00, 0xE0, 0x00, 0x00, 0xE0, 0x00, 0x00, 0xE0, 0x03,\n  0xFF, 0xE0, 0x03, 0xFF, 0xE0, 0x03, 0xFF, 0xE0, 0x00, 0x07, 0xF0, 0x00,\n  0x07, 0x70, 0x00, 0x07, 0x70, 0x00, 0x0F, 0x78, 0x00, 0x0F, 0x3C, 0x00,\n  0x1F, 0x1E, 0x00, 0x3F, 0x0F, 0xC0, 0xF7, 0x07, 0xFF, 0xE7, 0x03, 0xFF,\n  0xC3, 0x00, 0xFF, 0x03, 0xE0, 0x00, 0xFC, 0x00, 0x1F, 0x80, 0x03, 0xF0,\n  0x00, 0x7E, 0x00, 0x0F, 0xC0, 0x01, 0xF8, 0x00, 0x3F, 0x00, 0x07, 0xE0,\n  0x00, 0xFC, 0x00, 0x1F, 0x80, 0x03, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xF8, 0x00, 0x3F, 0x00, 0x07, 0xE0, 0x00, 0xFC, 0x00, 0x1F, 0x80,\n  0x03, 0xF0, 0x00, 0x7E, 0x00, 0x0F, 0xC0, 0x01, 0xF8, 0x00, 0x3F, 0x00,\n  0x07, 0xE0, 0x00, 0xFC, 0x00, 0x1C, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFC, 0x00, 0x1C, 0x00, 0x70, 0x01, 0xC0, 0x07, 0x00,\n  0x1C, 0x00, 0x70, 0x01, 0xC0, 0x07, 0x00, 0x1C, 0x00, 0x70, 0x01, 0xC0,\n  0x07, 0x00, 0x1C, 0x00, 0x70, 0x01, 0xC0, 0x07, 0x00, 0x1F, 0x80, 0x7E,\n  0x01, 0xF8, 0x07, 0xE0, 0x1F, 0xC0, 0xF7, 0x87, 0x9F, 0xFE, 0x3F, 0xF0,\n  0x3F, 0x00, 0xE0, 0x01, 0xEE, 0x00, 0x3C, 0xE0, 0x07, 0x8E, 0x00, 0xF0,\n  0xE0, 0x1E, 0x0E, 0x03, 0xE0, 0xE0, 0x7C, 0x0E, 0x0F, 0x80, 0xE1, 0xF0,\n  0x0E, 0x1E, 0x00, 0xE3, 0xC0, 0x0E, 0x7C, 0x00, 0xEF, 0xE0, 0x0F, 0xCE,\n  0x00, 0xF8, 0xF0, 0x0F, 0x07, 0x80, 0xE0, 0x3C, 0x0E, 0x03, 0xC0, 0xE0,\n  0x1E, 0x0E, 0x00, 0xF0, 0xE0, 0x0F, 0x0E, 0x00, 0x78, 0xE0, 0x03, 0xCE,\n  0x00, 0x3C, 0xE0, 0x01, 0xEE, 0x00, 0x0F, 0xE0, 0x01, 0xC0, 0x03, 0x80,\n  0x07, 0x00, 0x0E, 0x00, 0x1C, 0x00, 0x38, 0x00, 0x70, 0x00, 0xE0, 0x01,\n  0xC0, 0x03, 0x80, 0x07, 0x00, 0x0E, 0x00, 0x1C, 0x00, 0x38, 0x00, 0x70,\n  0x00, 0xE0, 0x01, 0xC0, 0x03, 0x80, 0x07, 0x00, 0x0E, 0x00, 0x1C, 0x00,\n  0x38, 0x00, 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xF8, 0x00, 0x1F, 0xF8,\n  0x00, 0x1F, 0xF8, 0x00, 0x1F, 0xFC, 0x00, 0x3F, 0xFC, 0x00, 0x3F, 0xFC,\n  0x00, 0x3F, 0xEE, 0x00, 0x77, 0xEE, 0x00, 0x77, 0xEE, 0x00, 0x77, 0xE7,\n  0x00, 0xE7, 0xE7, 0x00, 0xE7, 0xE7, 0x00, 0xE7, 0xE3, 0x81, 0xC7, 0xE3,\n  0x81, 0xC7, 0xE3, 0x81, 0xC7, 0xE1, 0xC3, 0x87, 0xE1, 0xC3, 0x87, 0xE1,\n  0xC3, 0x87, 0xE0, 0xE7, 0x07, 0xE0, 0xE7, 0x07, 0xE0, 0xE7, 0x07, 0xE0,\n  0x7E, 0x07, 0xE0, 0x7E, 0x07, 0xE0, 0x7E, 0x07, 0xE0, 0x3C, 0x07, 0xE0,\n  0x3C, 0x07, 0xF0, 0x00, 0x7F, 0x00, 0x07, 0xF8, 0x00, 0x7F, 0xC0, 0x07,\n  0xFC, 0x00, 0x7F, 0xE0, 0x07, 0xEF, 0x00, 0x7E, 0x70, 0x07, 0xE7, 0x80,\n  0x7E, 0x3C, 0x07, 0xE1, 0xC0, 0x7E, 0x1E, 0x07, 0xE0, 0xE0, 0x7E, 0x0F,\n  0x07, 0xE0, 0x78, 0x7E, 0x03, 0x87, 0xE0, 0x3C, 0x7E, 0x01, 0xE7, 0xE0,\n  0x0E, 0x7E, 0x00, 0xF7, 0xE0, 0x07, 0xFE, 0x00, 0x3F, 0xE0, 0x03, 0xFE,\n  0x00, 0x1F, 0xE0, 0x01, 0xFE, 0x00, 0x0F, 0x00, 0x7F, 0x00, 0x01, 0xFF,\n  0xF0, 0x01, 0xFF, 0xFC, 0x01, 0xF0, 0x1F, 0x01, 0xE0, 0x03, 0xC1, 0xE0,\n  0x00, 0xF1, 0xE0, 0x00, 0x3C, 0xE0, 0x00, 0x0E, 0x70, 0x00, 0x07, 0x70,\n  0x00, 0x03, 0xF8, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x3F,\n  0x00, 0x00, 0x1F, 0x80, 0x00, 0x0F, 0xC0, 0x00, 0x07, 0xE0, 0x00, 0x03,\n  0xB8, 0x00, 0x03, 0x9C, 0x00, 0x01, 0xCF, 0x00, 0x01, 0xE3, 0xC0, 0x01,\n  0xE0, 0xF0, 0x01, 0xE0, 0x3E, 0x03, 0xE0, 0x0F, 0xFF, 0xE0, 0x03, 0xFF,\n  0xE0, 0x00, 0x3F, 0x80, 0x00, 0xFF, 0xFC, 0x3F, 0xFF, 0x8F, 0xFF, 0xF3,\n  0x80, 0x3E, 0xE0, 0x03, 0xF8, 0x00, 0x7E, 0x00, 0x1F, 0x80, 0x07, 0xE0,\n  0x01, 0xF8, 0x00, 0x7E, 0x00, 0x3F, 0x80, 0x1E, 0xFF, 0xFF, 0x3F, 0xFF,\n  0x8F, 0xFF, 0xC3, 0x80, 0x00, 0xE0, 0x00, 0x38, 0x00, 0x0E, 0x00, 0x03,\n  0x80, 0x00, 0xE0, 0x00, 0x38, 0x00, 0x0E, 0x00, 0x03, 0x80, 0x00, 0xE0,\n  0x00, 0x38, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x01, 0xFF, 0xF0, 0x01, 0xFF,\n  0xFC, 0x01, 0xF0, 0x1F, 0x01, 0xE0, 0x03, 0xC1, 0xE0, 0x00, 0xF1, 0xE0,\n  0x00, 0x3C, 0xE0, 0x00, 0x0E, 0x70, 0x00, 0x07, 0x70, 0x00, 0x01, 0xF8,\n  0x00, 0x00, 0xFC, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x1F,\n  0x80, 0x00, 0x0F, 0xC0, 0x00, 0x07, 0xE0, 0x00, 0x07, 0xB8, 0x00, 0x03,\n  0x9C, 0x00, 0x01, 0xCF, 0x00, 0x39, 0xE3, 0xC0, 0x1F, 0xE0, 0xF0, 0x07,\n  0xE0, 0x3E, 0x03, 0xF0, 0x0F, 0xFF, 0xFC, 0x03, 0xFF, 0xEE, 0x00, 0x3F,\n  0x83, 0x80, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x20, 0xFF, 0xFE, 0x0F, 0xFF,\n  0xF8, 0xFF, 0xFF, 0xCE, 0x00, 0x3C, 0xE0, 0x01, 0xEE, 0x00, 0x0E, 0xE0,\n  0x00, 0xEE, 0x00, 0x0E, 0xE0, 0x00, 0xEE, 0x00, 0x0E, 0xE0, 0x01, 0xCE,\n  0x00, 0x3C, 0xFF, 0xFF, 0x8F, 0xFF, 0xF0, 0xFF, 0xFF, 0x8E, 0x00, 0x3C,\n  0xE0, 0x01, 0xEE, 0x00, 0x0E, 0xE0, 0x00, 0xEE, 0x00, 0x0E, 0xE0, 0x00,\n  0xEE, 0x00, 0x0E, 0xE0, 0x00, 0xEE, 0x00, 0x0E, 0xE0, 0x00, 0xFE, 0x00,\n  0x0F, 0x03, 0xFC, 0x00, 0xFF, 0xF0, 0x1F, 0xFF, 0x83, 0xE0, 0x7C, 0x38,\n  0x01, 0xE7, 0x00, 0x0E, 0x70, 0x00, 0xE7, 0x00, 0x00, 0x70, 0x00, 0x07,\n  0x80, 0x00, 0x3E, 0x00, 0x01, 0xFE, 0x00, 0x0F, 0xFE, 0x00, 0x3F, 0xF8,\n  0x00, 0x3F, 0xE0, 0x00, 0x3E, 0x00, 0x00, 0xF0, 0x00, 0x07, 0xE0, 0x00,\n  0x7E, 0x00, 0x07, 0xF0, 0x00, 0x77, 0x80, 0x0E, 0x7C, 0x03, 0xE3, 0xFF,\n  0xFC, 0x1F, 0xFF, 0x80, 0x3F, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0x80, 0x70, 0x00, 0x0E, 0x00, 0x01, 0xC0, 0x00, 0x38, 0x00, 0x07,\n  0x00, 0x00, 0xE0, 0x00, 0x1C, 0x00, 0x03, 0x80, 0x00, 0x70, 0x00, 0x0E,\n  0x00, 0x01, 0xC0, 0x00, 0x38, 0x00, 0x07, 0x00, 0x00, 0xE0, 0x00, 0x1C,\n  0x00, 0x03, 0x80, 0x00, 0x70, 0x00, 0x0E, 0x00, 0x01, 0xC0, 0x00, 0x38,\n  0x00, 0x07, 0x00, 0x00, 0xE0, 0x00, 0x1C, 0x00, 0xE0, 0x00, 0xFC, 0x00,\n  0x1F, 0x80, 0x03, 0xF0, 0x00, 0x7E, 0x00, 0x0F, 0xC0, 0x01, 0xF8, 0x00,\n  0x3F, 0x00, 0x07, 0xE0, 0x00, 0xFC, 0x00, 0x1F, 0x80, 0x03, 0xF0, 0x00,\n  0x7E, 0x00, 0x0F, 0xC0, 0x01, 0xF8, 0x00, 0x3F, 0x00, 0x07, 0xE0, 0x00,\n  0xFC, 0x00, 0x1F, 0x80, 0x03, 0xF0, 0x00, 0x7F, 0x00, 0x1E, 0xF0, 0x07,\n  0x9F, 0x01, 0xF1, 0xFF, 0xFC, 0x1F, 0xFE, 0x00, 0x7F, 0x00, 0xE0, 0x00,\n  0x7F, 0x80, 0x03, 0xFC, 0x00, 0x1C, 0xE0, 0x01, 0xE7, 0x80, 0x0F, 0x3C,\n  0x00, 0x70, 0xE0, 0x07, 0x87, 0x80, 0x3C, 0x1C, 0x01, 0xC0, 0xE0, 0x0E,\n  0x07, 0x80, 0xE0, 0x1C, 0x07, 0x00, 0xE0, 0x38, 0x07, 0x83, 0x80, 0x1C,\n  0x1C, 0x00, 0xE0, 0xE0, 0x07, 0x8E, 0x00, 0x1C, 0x70, 0x00, 0xE3, 0x80,\n  0x07, 0xB8, 0x00, 0x1D, 0xC0, 0x00, 0xEE, 0x00, 0x07, 0xE0, 0x00, 0x1F,\n  0x00, 0x00, 0xF8, 0x00, 0x03, 0x80, 0x00, 0x70, 0x03, 0xC0, 0x0F, 0x70,\n  0x03, 0xC0, 0x0F, 0x78, 0x03, 0xE0, 0x0F, 0x78, 0x03, 0xE0, 0x0E, 0x38,\n  0x07, 0xE0, 0x0E, 0x38, 0x07, 0xF0, 0x1E, 0x3C, 0x07, 0x70, 0x1E, 0x3C,\n  0x07, 0x70, 0x1C, 0x1C, 0x0E, 0x70, 0x1C, 0x1C, 0x0E, 0x38, 0x3C, 0x1C,\n  0x0E, 0x38, 0x3C, 0x1E, 0x1E, 0x38, 0x38, 0x0E, 0x1C, 0x38, 0x38, 0x0E,\n  0x1C, 0x1C, 0x38, 0x0E, 0x1C, 0x1C, 0x78, 0x0F, 0x3C, 0x1C, 0x70, 0x07,\n  0x38, 0x0E, 0x70, 0x07, 0x38, 0x0E, 0x70, 0x07, 0x38, 0x0E, 0x70, 0x07,\n  0x70, 0x0E, 0xE0, 0x03, 0xF0, 0x07, 0xE0, 0x03, 0xF0, 0x07, 0xE0, 0x03,\n  0xF0, 0x07, 0xE0, 0x03, 0xE0, 0x03, 0xC0, 0x01, 0xE0, 0x03, 0xC0, 0x01,\n  0xE0, 0x03, 0xC0, 0xF0, 0x00, 0x7B, 0xC0, 0x07, 0x8F, 0x00, 0x38, 0x78,\n  0x03, 0xC1, 0xE0, 0x3C, 0x07, 0x81, 0xC0, 0x3C, 0x1E, 0x00, 0xF1, 0xE0,\n  0x03, 0x8E, 0x00, 0x1E, 0xF0, 0x00, 0x7F, 0x00, 0x01, 0xF0, 0x00, 0x0F,\n  0x80, 0x00, 0x7C, 0x00, 0x07, 0xF0, 0x00, 0x3B, 0x80, 0x03, 0xDE, 0x00,\n  0x3C, 0x78, 0x01, 0xC1, 0xC0, 0x1E, 0x0F, 0x01, 0xE0, 0x3C, 0x0E, 0x00,\n  0xE0, 0xF0, 0x07, 0x8F, 0x00, 0x1E, 0x70, 0x00, 0xF7, 0x80, 0x03, 0xC0,\n  0xF0, 0x00, 0x3C, 0xF0, 0x00, 0x78, 0xF0, 0x01, 0xE1, 0xE0, 0x03, 0x81,\n  0xE0, 0x0F, 0x01, 0xC0, 0x1C, 0x03, 0xC0, 0x78, 0x03, 0xC1, 0xE0, 0x07,\n  0x83, 0x80, 0x07, 0x8F, 0x00, 0x07, 0x1C, 0x00, 0x0F, 0x78, 0x00, 0x0E,\n  0xE0, 0x00, 0x0F, 0x80, 0x00, 0x1F, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x38,\n  0x00, 0x00, 0x70, 0x00, 0x00, 0xE0, 0x00, 0x01, 0xC0, 0x00, 0x03, 0x80,\n  0x00, 0x07, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x38, 0x00,\n  0x00, 0x70, 0x00, 0x7F, 0xFF, 0xEF, 0xFF, 0xFD, 0xFF, 0xFF, 0x80, 0x00,\n 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0xFF, 0xFF, 0xFF, 0xC0, 0xF0, 0xF0, 0xE0, 0xE0,\n  0xE0, 0x07, 0xF0, 0x0F, 0xFC, 0x0F, 0xFF, 0x0F, 0x03, 0xC7, 0x00, 0xE0,\n  0x00, 0x70, 0x00, 0x38, 0x00, 0x1C, 0x00, 0xFE, 0x0F, 0xFF, 0x1F, 0xF3,\n  0x9F, 0x01, 0xCF, 0x00, 0xE7, 0x00, 0x73, 0x80, 0x79, 0xE0, 0xFC, 0x7F,\n  0xEF, 0x9F, 0xE3, 0xC7, 0xE1, 0xE0, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00,\n  0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE3, 0xE0, 0xEF, 0xF8,\n  0xFF, 0xFC, 0xFC, 0x3E, 0xF8, 0x1E, 0xF0, 0x0E, 0xE0, 0x0F, 0xE0, 0x07,\n  0xE0, 0x07, 0xE0, 0x07, 0xE0, 0x07, 0xE0, 0x07, 0xE0, 0x07, 0xF0, 0x0E,\n  0xF8, 0x1E, 0xFC, 0x3C, 0xEF, 0xFC, 0xEF, 0xF8, 0xE3, 0xE0, 0x07, 0xF0,\n  0x1F, 0xF8, 0x3F, 0xFC, 0x3C, 0x1E, 0x78, 0x0E, 0x70, 0x07, 0xE0, 0x00,\n  0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x07,\n  0x70, 0x07, 0x78, 0x0E, 0x7C, 0x1E, 0x3F, 0xFC, 0x1F, 0xF8, 0x07, 0xE0,\n  0x00, 0x03, 0x80, 0x01, 0xC0, 0x00, 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00,\n  0x1C, 0x00, 0x0E, 0x0F, 0xC7, 0x1F, 0xFB, 0x9F, 0xFF, 0xDF, 0x07, 0xEF,\n  0x01, 0xF7, 0x00, 0x7F, 0x80, 0x3F, 0x80, 0x0F, 0xC0, 0x07, 0xE0, 0x03,\n  0xF0, 0x01, 0xF8, 0x00, 0xFC, 0x00, 0x77, 0x00, 0x7B, 0xC0, 0x7D, 0xF0,\n  0x7E, 0x7F, 0xFB, 0x1F, 0xF9, 0x83, 0xF0, 0xC0, 0x07, 0xE0, 0x1F, 0xF8,\n  0x3F, 0xFC, 0x7C, 0x1E, 0x70, 0x0E, 0x60, 0x06, 0xE0, 0x07, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0x70, 0x07,\n  0x78, 0x0E, 0x3C, 0x1E, 0x3F, 0xFC, 0x1F, 0xF8, 0x07, 0xE0, 0x0E, 0x3C,\n  0xF9, 0xC3, 0x87, 0x0E, 0x7F, 0xFF, 0xFC, 0xE1, 0xC3, 0x87, 0x0E, 0x1C,\n  0x38, 0x70, 0xE1, 0xC3, 0x87, 0x0E, 0x1C, 0x38, 0x70, 0x07, 0xC7, 0x1F,\n  0xF7, 0x3F, 0xFF, 0x3C, 0x3F, 0x78, 0x0F, 0x70, 0x0F, 0xE0, 0x07, 0xE0,\n  0x07, 0xE0, 0x07, 0xE0, 0x07, 0xE0, 0x07, 0xE0, 0x07, 0xE0, 0x07, 0x70,\n  0x0F, 0x78, 0x0F, 0x7C, 0x3F, 0x3F, 0xF7, 0x1F, 0xE7, 0x07, 0xC7, 0x00,\n  0x07, 0x00, 0x07, 0x00, 0x0E, 0x70, 0x0E, 0x78, 0x1E, 0x3F, 0xFC, 0x1F,\n  0xF8, 0x07, 0xE0, 0xE0, 0x01, 0xC0, 0x03, 0x80, 0x07, 0x00, 0x0E, 0x00,\n  0x1C, 0x00, 0x38, 0x00, 0x71, 0xF8, 0xE7, 0xFD, 0xDF, 0xFB, 0xF0, 0xFF,\n  0xC0, 0xFF, 0x00, 0xFC, 0x01, 0xF8, 0x03, 0xF0, 0x07, 0xE0, 0x0F, 0xC0,\n  0x1F, 0x80, 0x3F, 0x00, 0x7E, 0x00, 0xFC, 0x01, 0xF8, 0x03, 0xF0, 0x07,\n  0xE0, 0x0F, 0xC0, 0x1C, 0xFF, 0xF0, 0x07, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFC, 0x1C, 0x71, 0xC7, 0x00, 0x00, 0x07, 0x1C, 0x71, 0xC7, 0x1C,\n  0x71, 0xC7, 0x1C, 0x71, 0xC7, 0x1C, 0x71, 0xC7, 0x1C, 0x71, 0xC7, 0x1C,\n  0x73, 0xFF, 0xFB, 0xC0, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00,\n  0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x3C, 0xE0, 0x78, 0xE0, 0xF0,\n  0xE1, 0xE0, 0xE3, 0xC0, 0xE7, 0x80, 0xEF, 0x00, 0xEF, 0x80, 0xFF, 0x80,\n  0xFB, 0xC0, 0xF1, 0xE0, 0xE0, 0xE0, 0xE0, 0xF0, 0xE0, 0x70, 0xE0, 0x78,\n  0xE0, 0x3C, 0xE0, 0x1C, 0xE0, 0x1E, 0xE0, 0x0E, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xE3, 0xE0, 0xF8, 0xE7, 0xF1, 0xFE,\n  0xEF, 0xFB, 0xFE, 0xF8, 0x7F, 0x0F, 0xF0, 0x3E, 0x07, 0xF0, 0x1C, 0x07,\n  0xE0, 0x1C, 0x07, 0xE0, 0x1C, 0x07, 0xE0, 0x1C, 0x07, 0xE0, 0x1C, 0x07,\n  0xE0, 0x1C, 0x07, 0xE0, 0x1C, 0x07, 0xE0, 0x1C, 0x07, 0xE0, 0x1C, 0x07,\n  0xE0, 0x1C, 0x07, 0xE0, 0x1C, 0x07, 0xE0, 0x1C, 0x07, 0xE0, 0x1C, 0x07,\n  0xE0, 0x1C, 0x07, 0xE3, 0xF1, 0xCF, 0xFB, 0xBF, 0xF7, 0xE1, 0xFF, 0x81,\n  0xFE, 0x01, 0xF8, 0x03, 0xF0, 0x07, 0xE0, 0x0F, 0xC0, 0x1F, 0x80, 0x3F,\n  0x00, 0x7E, 0x00, 0xFC, 0x01, 0xF8, 0x03, 0xF0, 0x07, 0xE0, 0x0F, 0xC0,\n  0x1F, 0x80, 0x38, 0x07, 0xF0, 0x0F, 0xFE, 0x0F, 0xFF, 0x87, 0x83, 0xC7,\n  0x80, 0xF3, 0x80, 0x3B, 0x80, 0x1F, 0xC0, 0x07, 0xE0, 0x03, 0xF0, 0x01,\n  0xF8, 0x00, 0xFC, 0x00, 0x7E, 0x00, 0x3B, 0x80, 0x39, 0xE0, 0x3C, 0x78,\n  0x3C, 0x3F, 0xFE, 0x0F, 0xFE, 0x01, 0xFC, 0x00, 0xE3, 0xE0, 0xE7, 0xF8,\n  0xEF, 0xFC, 0xFC, 0x3E, 0xF8, 0x1E, 0xF0, 0x0E, 0xE0, 0x0F, 0xE0, 0x07,\n  0xE0, 0x07, 0xE0, 0x07, 0xE0, 0x07, 0xE0, 0x07, 0xE0, 0x07, 0xF0, 0x0E,\n  0xF8, 0x1E, 0xFC, 0x3E, 0xFF, 0xFC, 0xEF, 0xF8, 0xE3, 0xE0, 0xE0, 0x00,\n  0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0x07, 0xE1,\n  0x8F, 0xFC, 0xCF, 0xFF, 0x67, 0x83, 0xF7, 0x80, 0xFB, 0x80, 0x3F, 0xC0,\n  0x1F, 0xC0, 0x07, 0xE0, 0x03, 0xF0, 0x01, 0xF8, 0x00, 0xFC, 0x00, 0x7E,\n  0x00, 0x3B, 0x80, 0x3D, 0xE0, 0x3E, 0xF8, 0x3F, 0x3F, 0xFF, 0x8F, 0xFD,\n  0xC1, 0xF8, 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C, 0x00, 0x0E, 0x00,\n  0x07, 0x00, 0x03, 0x80, 0xE3, 0xF7, 0xFB, 0xFF, 0x8F, 0x07, 0x83, 0x81,\n  0xC0, 0xE0, 0x70, 0x38, 0x1C, 0x0E, 0x07, 0x03, 0x81, 0xC0, 0xE0, 0x70,\n  0x38, 0x00, 0x0F, 0xC0, 0xFF, 0x87, 0xFF, 0x3C, 0x1E, 0xE0, 0x3B, 0x80,\n  0x0E, 0x00, 0x3C, 0x00, 0x7F, 0x00, 0xFF, 0x80, 0xFF, 0x80, 0x7F, 0x00,\n  0x3F, 0x80, 0x7E, 0x01, 0xFC, 0x1F, 0x7F, 0xF8, 0xFF, 0xC1, 0xFC, 0x00,\n  0x38, 0x70, 0xE1, 0xCF, 0xFF, 0xFF, 0x9C, 0x38, 0x70, 0xE1, 0xC3, 0x87,\n  0x0E, 0x1C, 0x38, 0x70, 0xE1, 0xC3, 0xE7, 0xC7, 0x80, 0xE0, 0x0F, 0xC0,\n  0x1F, 0x80, 0x3F, 0x00, 0x7E, 0x00, 0xFC, 0x01, 0xF8, 0x03, 0xF0, 0x07,\n  0xE0, 0x0F, 0xC0, 0x1F, 0x80, 0x3F, 0x00, 0x7E, 0x00, 0xFC, 0x03, 0xFC,\n  0x0F, 0xFC, 0x3F, 0x7F, 0xEE, 0xFF, 0x9C, 0x7E, 0x38, 0x70, 0x03, 0xB8,\n  0x03, 0x9C, 0x01, 0xC7, 0x00, 0xE3, 0x80, 0xE1, 0xC0, 0x70, 0x70, 0x38,\n  0x38, 0x38, 0x1C, 0x1C, 0x07, 0x0E, 0x03, 0x8E, 0x01, 0xC7, 0x00, 0x77,\n  0x00, 0x3B, 0x80, 0x1D, 0xC0, 0x07, 0xC0, 0x03, 0xE0, 0x01, 0xF0, 0x00,\n  0x70, 0x00, 0xF0, 0x1C, 0x03, 0xB8, 0x1F, 0x03, 0xDC, 0x0F, 0x81, 0xCE,\n  0x07, 0xC0, 0xE7, 0x83, 0xE0, 0x71, 0xC3, 0xB8, 0x70, 0xE1, 0xDC, 0x38,\n  0x70, 0xEE, 0x1C, 0x1C, 0x63, 0x0E, 0x0E, 0x71, 0xCE, 0x07, 0x38, 0xE7,\n  0x03, 0x9C, 0x73, 0x80, 0xEC, 0x19, 0x80, 0x7E, 0x0F, 0xC0, 0x3F, 0x07,\n  0xE0, 0x0F, 0x83, 0xF0, 0x07, 0x80, 0xF0, 0x03, 0xC0, 0x78, 0x01, 0xE0,\n  0x3C, 0x00, 0x70, 0x07, 0x38, 0x0E, 0x3C, 0x1C, 0x1C, 0x1C, 0x0E, 0x38,\n  0x0F, 0x70, 0x07, 0x70, 0x03, 0xE0, 0x03, 0xC0, 0x01, 0xC0, 0x03, 0xE0,\n  0x07, 0xE0, 0x07, 0x70, 0x0E, 0x78, 0x1E, 0x38, 0x1C, 0x1C, 0x38, 0x1E,\n  0x78, 0x0E, 0x70, 0x07, 0x70, 0x07, 0x38, 0x03, 0x9C, 0x01, 0xC7, 0x01,\n  0xC3, 0x80, 0xE1, 0xC0, 0x70, 0x70, 0x70, 0x38, 0x38, 0x1C, 0x3C, 0x07,\n  0x1C, 0x03, 0x8E, 0x01, 0xCE, 0x00, 0x77, 0x00, 0x3B, 0x80, 0x1F, 0x80,\n  0x07, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x38,\n  0x00, 0x1C, 0x00, 0x1E, 0x00, 0x0E, 0x00, 0x3F, 0x00, 0x1F, 0x00, 0x0F,\n  0x00, 0x00, 0x7F, 0xFC, 0xFF, 0xF9, 0xFF, 0xF0, 0x00, 0xE0, 0x03, 0x80,\n  0x0E, 0x00, 0x3C, 0x00, 0xF0, 0x03, 0xC0, 0x0F, 0x00, 0x1C, 0x00, 0x70,\n  0x01, 0xE0, 0x07, 0x80, 0x1E, 0x00, 0x78, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xF8, 0x07, 0x0F, 0x1F, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n  0x1C, 0x1C, 0x1C, 0x1C, 0x38, 0xF8, 0xE0, 0xF8, 0x38, 0x1C, 0x1C, 0x1C,\n  0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1F, 0x0F, 0x07, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xE0, 0xF0, 0xF8, 0x38,\n  0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x1C, 0x1F,\n  0x07, 0x1F, 0x1C, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38, 0x38,\n  0x38, 0x38, 0xF8, 0xF0, 0xE0, 0x38, 0x00, 0xFC, 0x03, 0xFC, 0x1F, 0x3E,\n  0x3C, 0x1F, 0xE0, 0x1F, 0x80, 0x1E, 0x00 };\n\nconst GFXglyph FreeSans18pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,   9,    0,    1 },   // 0x20 ' '\n  {     0,   3,  26,  12,    4,  -25 },   // 0x21 '!'\n  {    10,   9,   9,  12,    1,  -24 },   // 0x22 '\"'\n  {    21,  19,  24,  19,    0,  -23 },   // 0x23 '#'\n  {    78,  16,  30,  19,    2,  -26 },   // 0x24 '$'\n  {   138,  29,  25,  31,    1,  -24 },   // 0x25 '%'\n  {   229,  20,  25,  23,    2,  -24 },   // 0x26 '&'\n  {   292,   3,   9,   7,    2,  -24 },   // 0x27 '''\n  {   296,   8,  33,  12,    3,  -25 },   // 0x28 '('\n  {   329,   8,  33,  12,    1,  -25 },   // 0x29 ')'\n  {   362,  10,  10,  14,    2,  -25 },   // 0x2A '*'\n  {   375,  16,  16,  20,    2,  -15 },   // 0x2B '+'\n  {   407,   3,   9,  10,    3,   -3 },   // 0x2C ','\n  {   411,   8,   3,  12,    2,  -10 },   // 0x2D '-'\n  {   414,   3,   4,   9,    3,   -3 },   // 0x2E '.'\n  {   416,  10,  26,  10,    0,  -25 },   // 0x2F '/'\n  {   449,  16,  25,  19,    2,  -24 },   // 0x30 '0'\n  {   499,   8,  25,  19,    4,  -24 },   // 0x31 '1'\n  {   524,  16,  25,  19,    2,  -24 },   // 0x32 '2'\n  {   574,  17,  25,  19,    1,  -24 },   // 0x33 '3'\n  {   628,  16,  25,  19,    1,  -24 },   // 0x34 '4'\n  {   678,  17,  25,  19,    1,  -24 },   // 0x35 '5'\n  {   732,  16,  25,  19,    2,  -24 },   // 0x36 '6'\n  {   782,  16,  25,  19,    2,  -24 },   // 0x37 '7'\n  {   832,  17,  25,  19,    1,  -24 },   // 0x38 '8'\n  {   886,  16,  25,  19,    1,  -24 },   // 0x39 '9'\n  {   936,   3,  19,   9,    3,  -18 },   // 0x3A ':'\n  {   944,   3,  24,   9,    3,  -18 },   // 0x3B ';'\n  {   953,  17,  17,  20,    2,  -16 },   // 0x3C '<'\n  {   990,  17,   9,  20,    2,  -12 },   // 0x3D '='\n  {  1010,  17,  17,  20,    2,  -16 },   // 0x3E '>'\n  {  1047,  15,  26,  19,    3,  -25 },   // 0x3F '?'\n  {  1096,  32,  31,  36,    1,  -25 },   // 0x40 '@'\n  {  1220,  22,  26,  23,    1,  -25 },   // 0x41 'A'\n  {  1292,  19,  26,  23,    3,  -25 },   // 0x42 'B'\n  {  1354,  22,  26,  25,    1,  -25 },   // 0x43 'C'\n  {  1426,  20,  26,  24,    3,  -25 },   // 0x44 'D'\n  {  1491,  18,  26,  22,    3,  -25 },   // 0x45 'E'\n  {  1550,  17,  26,  21,    3,  -25 },   // 0x46 'F'\n  {  1606,  24,  26,  27,    1,  -25 },   // 0x47 'G'\n  {  1684,  19,  26,  25,    3,  -25 },   // 0x48 'H'\n  {  1746,   3,  26,  10,    4,  -25 },   // 0x49 'I'\n  {  1756,  14,  26,  18,    1,  -25 },   // 0x4A 'J'\n  {  1802,  20,  26,  24,    3,  -25 },   // 0x4B 'K'\n  {  1867,  15,  26,  20,    3,  -25 },   // 0x4C 'L'\n  {  1916,  24,  26,  30,    3,  -25 },   // 0x4D 'M'\n  {  1994,  20,  26,  26,    3,  -25 },   // 0x4E 'N'\n  {  2059,  25,  26,  27,    1,  -25 },   // 0x4F 'O'\n  {  2141,  18,  26,  23,    3,  -25 },   // 0x50 'P'\n  {  2200,  25,  28,  27,    1,  -25 },   // 0x51 'Q'\n  {  2288,  20,  26,  25,    3,  -25 },   // 0x52 'R'\n  {  2353,  20,  26,  23,    1,  -25 },   // 0x53 'S'\n  {  2418,  19,  26,  22,    1,  -25 },   // 0x54 'T'\n  {  2480,  19,  26,  25,    3,  -25 },   // 0x55 'U'\n  {  2542,  21,  26,  23,    1,  -25 },   // 0x56 'V'\n  {  2611,  32,  26,  33,    0,  -25 },   // 0x57 'W'\n  {  2715,  21,  26,  23,    1,  -25 },   // 0x58 'X'\n  {  2784,  23,  26,  24,    0,  -25 },   // 0x59 'Y'\n  {  2859,  19,  26,  22,    1,  -25 },   // 0x5A 'Z'\n  {  2921,   6,  33,  10,    2,  -25 },   // 0x5B '['\n  {  2946,  10,  26,  10,    0,  -25 },   // 0x5C '\\'\n  {  2979,   6,  33,  10,    1,  -25 },   // 0x5D ']'\n  {  3004,  13,  13,  16,    2,  -24 },   // 0x5E '^'\n  {  3026,  21,   2,  19,   -1,    5 },   // 0x5F '_'\n  {  3032,   7,   5,   9,    1,  -25 },   // 0x60 '`'\n  {  3037,  17,  19,  19,    1,  -18 },   // 0x61 'a'\n  {  3078,  16,  26,  20,    2,  -25 },   // 0x62 'b'\n  {  3130,  16,  19,  18,    1,  -18 },   // 0x63 'c'\n  {  3168,  17,  26,  20,    1,  -25 },   // 0x64 'd'\n  {  3224,  16,  19,  19,    1,  -18 },   // 0x65 'e'\n  {  3262,   7,  26,  10,    1,  -25 },   // 0x66 'f'\n  {  3285,  16,  27,  19,    1,  -18 },   // 0x67 'g'\n  {  3339,  15,  26,  19,    2,  -25 },   // 0x68 'h'\n  {  3388,   3,  26,   8,    2,  -25 },   // 0x69 'i'\n  {  3398,   6,  34,   9,    0,  -25 },   // 0x6A 'j'\n  {  3424,  16,  26,  18,    2,  -25 },   // 0x6B 'k'\n  {  3476,   3,  26,   7,    2,  -25 },   // 0x6C 'l'\n  {  3486,  24,  19,  28,    2,  -18 },   // 0x6D 'm'\n  {  3543,  15,  19,  19,    2,  -18 },   // 0x6E 'n'\n  {  3579,  17,  19,  19,    1,  -18 },   // 0x6F 'o'\n  {  3620,  16,  25,  20,    2,  -18 },   // 0x70 'p'\n  {  3670,  17,  25,  20,    1,  -18 },   // 0x71 'q'\n  {  3724,   9,  19,  12,    2,  -18 },   // 0x72 'r'\n  {  3746,  14,  19,  17,    2,  -18 },   // 0x73 's'\n  {  3780,   7,  23,  10,    1,  -22 },   // 0x74 't'\n  {  3801,  15,  19,  19,    2,  -18 },   // 0x75 'u'\n  {  3837,  17,  19,  17,    0,  -18 },   // 0x76 'v'\n  {  3878,  25,  19,  25,    0,  -18 },   // 0x77 'w'\n  {  3938,  16,  19,  17,    0,  -18 },   // 0x78 'x'\n  {  3976,  17,  27,  17,    0,  -18 },   // 0x79 'y'\n  {  4034,  15,  19,  17,    1,  -18 },   // 0x7A 'z'\n  {  4070,   8,  33,  12,    1,  -25 },   // 0x7B '{'\n  {  4103,   2,  33,   9,    3,  -25 },   // 0x7C '|'\n  {  4112,   8,  33,  12,    3,  -25 },   // 0x7D '}'\n  {  4145,  15,   7,  18,    1,  -15 } }; // 0x7E '~'\n\nconst GFXfont FreeSans18pt7b PROGMEM = {\n  (uint8_t  *)FreeSans18pt7bBitmaps,\n  (GFXglyph *)FreeSans18pt7bGlyphs,\n  0x20, 0x7E, 42 };\n\n// Approx. 4831 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeSans24pt7b.h",
    "content": "const uint8_t FreeSans24pt7bBitmaps[] PROGMEM = {\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x76, 0x66,\n  0x66, 0x00, 0x0F, 0xFF, 0xFF, 0xF1, 0xFE, 0x3F, 0xC7, 0xF8, 0xFF, 0x1F,\n  0xE3, 0xFC, 0x7F, 0x8F, 0xF1, 0xEC, 0x19, 0x83, 0x30, 0x60, 0x00, 0x70,\n  0x3C, 0x00, 0x70, 0x3C, 0x00, 0xF0, 0x38, 0x00, 0xF0, 0x38, 0x00, 0xF0,\n  0x78, 0x00, 0xE0, 0x78, 0x00, 0xE0, 0x78, 0x01, 0xE0, 0x70, 0x01, 0xE0,\n  0x70, 0x7F, 0xFF, 0xFF, 0x7F, 0xFF, 0xFF, 0x7F, 0xFF, 0xFF, 0x03, 0xC0,\n  0xE0, 0x03, 0xC0, 0xE0, 0x03, 0xC0, 0xE0, 0x03, 0x81, 0xE0, 0x03, 0x81,\n  0xE0, 0x03, 0x81, 0xE0, 0x07, 0x81, 0xC0, 0x07, 0x81, 0xC0, 0xFF, 0xFF,\n  0xFE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0x0F, 0x03, 0x80, 0x0F, 0x03,\n  0x80, 0x0F, 0x07, 0x80, 0x0E, 0x07, 0x80, 0x0E, 0x07, 0x80, 0x1E, 0x07,\n  0x00, 0x1E, 0x07, 0x00, 0x1E, 0x07, 0x00, 0x1C, 0x0F, 0x00, 0x1C, 0x0F,\n  0x00, 0x00, 0x38, 0x00, 0x01, 0xFC, 0x00, 0x1F, 0xFE, 0x00, 0x7F, 0xFE,\n  0x01, 0xFF, 0xFE, 0x07, 0xE7, 0x3E, 0x0F, 0x8E, 0x3C, 0x3E, 0x1C, 0x3C,\n  0x78, 0x38, 0x38, 0xF0, 0x70, 0x71, 0xE0, 0xE0, 0xE3, 0xC1, 0xC0, 0x07,\n  0x83, 0x80, 0x0F, 0x87, 0x00, 0x0F, 0x8E, 0x00, 0x1F, 0xDC, 0x00, 0x1F,\n  0xF8, 0x00, 0x1F, 0xFF, 0x00, 0x0F, 0xFF, 0x80, 0x07, 0xFF, 0x80, 0x03,\n  0xFF, 0x80, 0x07, 0x1F, 0x80, 0x0E, 0x1F, 0x00, 0x1C, 0x1F, 0x00, 0x38,\n  0x1F, 0xC0, 0x70, 0x3F, 0x80, 0xE0, 0x7F, 0x81, 0xC0, 0xFF, 0x03, 0x81,\n  0xEF, 0x07, 0x07, 0x9F, 0x0E, 0x0F, 0x3E, 0x1C, 0x3E, 0x3F, 0x39, 0xF8,\n  0x3F, 0xFF, 0xE0, 0x3F, 0xFF, 0x00, 0x0F, 0xF8, 0x00, 0x03, 0x80, 0x00,\n  0x07, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x38, 0x00, 0x00,\n  0x00, 0x00, 0x1C, 0x00, 0x0F, 0xC0, 0x00, 0x78, 0x00, 0x3F, 0xE0, 0x00,\n  0xE0, 0x01, 0xFF, 0xE0, 0x03, 0x80, 0x03, 0xFF, 0xE0, 0x07, 0x00, 0x0F,\n  0x87, 0xC0, 0x1C, 0x00, 0x3C, 0x03, 0xC0, 0x38, 0x00, 0x70, 0x03, 0x80,\n  0xE0, 0x00, 0xE0, 0x07, 0x03, 0xC0, 0x01, 0xC0, 0x0E, 0x07, 0x00, 0x03,\n  0x80, 0x1C, 0x1E, 0x00, 0x07, 0x80, 0x78, 0x38, 0x00, 0x07, 0xC3, 0xE0,\n  0xF0, 0x00, 0x07, 0xFF, 0xC1, 0xC0, 0x00, 0x0F, 0xFF, 0x07, 0x80, 0x00,\n  0x0F, 0xFC, 0x0E, 0x00, 0x00, 0x07, 0xE0, 0x38, 0x00, 0x00, 0x00, 0x00,\n  0x70, 0x00, 0x00, 0x00, 0x01, 0xC0, 0x3F, 0x00, 0x00, 0x03, 0x80, 0xFF,\n  0x80, 0x00, 0x0E, 0x07, 0xFF, 0x80, 0x00, 0x3C, 0x0F, 0xFF, 0x80, 0x00,\n  0x70, 0x3E, 0x1F, 0x00, 0x01, 0xE0, 0xF0, 0x0F, 0x00, 0x03, 0x81, 0xC0,\n  0x0E, 0x00, 0x0F, 0x03, 0x80, 0x1C, 0x00, 0x1C, 0x07, 0x00, 0x38, 0x00,\n  0x78, 0x0E, 0x00, 0x70, 0x00, 0xE0, 0x1E, 0x01, 0xE0, 0x03, 0x80, 0x1F,\n  0x0F, 0x80, 0x07, 0x00, 0x1F, 0xFF, 0x00, 0x1C, 0x00, 0x3F, 0xFC, 0x00,\n  0x38, 0x00, 0x1F, 0xF0, 0x00, 0xE0, 0x00, 0x1F, 0x80, 0x00, 0x7E, 0x00,\n  0x00, 0x1F, 0xF0, 0x00, 0x03, 0xFF, 0x80, 0x00, 0x7F, 0xFC, 0x00, 0x07,\n  0xC3, 0xC0, 0x00, 0xF8, 0x1E, 0x00, 0x0F, 0x00, 0xE0, 0x00, 0xF0, 0x0E,\n  0x00, 0x0F, 0x00, 0xE0, 0x00, 0xF0, 0x0E, 0x00, 0x07, 0x81, 0xE0, 0x00,\n  0x7C, 0x3C, 0x00, 0x03, 0xEF, 0x80, 0x00, 0x1F, 0xF0, 0x00, 0x01, 0xFE,\n  0x00, 0x00, 0x1F, 0x80, 0x00, 0x03, 0xFC, 0x00, 0x00, 0xFF, 0xE0, 0x00,\n  0x1F, 0x1E, 0x07, 0x83, 0xE0, 0xF0, 0x78, 0x7C, 0x0F, 0x8F, 0x87, 0x80,\n  0x7C, 0xF0, 0xF0, 0x03, 0xFF, 0x0F, 0x00, 0x1F, 0xE0, 0xF0, 0x00, 0xFE,\n  0x0F, 0x00, 0x0F, 0xC0, 0xF0, 0x00, 0x7E, 0x0F, 0x80, 0x0F, 0xF0, 0x7C,\n  0x01, 0xFF, 0x07, 0xF0, 0x7D, 0xF8, 0x3F, 0xFF, 0x8F, 0xC1, 0xFF, 0xF0,\n  0x7E, 0x0F, 0xFE, 0x03, 0xE0, 0x3F, 0x80, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xF6, 0x66, 0x01, 0xC0, 0x70, 0x38, 0x1C, 0x07, 0x03, 0xC0, 0xE0, 0x78,\n  0x1C, 0x07, 0x03, 0xC0, 0xE0, 0x78, 0x1E, 0x07, 0x81, 0xE0, 0x70, 0x3C,\n  0x0F, 0x03, 0xC0, 0xF0, 0x3C, 0x0F, 0x03, 0xC0, 0xF0, 0x3C, 0x0F, 0x03,\n  0xC0, 0x70, 0x1E, 0x07, 0x81, 0xE0, 0x38, 0x0F, 0x03, 0xC0, 0x70, 0x1E,\n  0x03, 0x80, 0xE0, 0x1C, 0x07, 0x00, 0xE0, 0x18, 0x07, 0xE0, 0x38, 0x07,\n  0x01, 0xC0, 0x38, 0x0F, 0x01, 0xC0, 0x78, 0x0E, 0x03, 0x80, 0xF0, 0x1C,\n  0x07, 0x01, 0xE0, 0x78, 0x1E, 0x03, 0x80, 0xF0, 0x3C, 0x0F, 0x03, 0xC0,\n  0xF0, 0x3C, 0x0F, 0x03, 0xC0, 0xF0, 0x3C, 0x0F, 0x07, 0x81, 0xE0, 0x78,\n  0x1E, 0x07, 0x03, 0xC0, 0xF0, 0x38, 0x1E, 0x07, 0x01, 0xC0, 0xE0, 0x38,\n  0x1C, 0x06, 0x03, 0x80, 0x03, 0x00, 0x0C, 0x00, 0x30, 0x00, 0xC0, 0x63,\n  0x1B, 0xFF, 0xFF, 0xFF, 0xC3, 0xF0, 0x07, 0x80, 0x3F, 0x01, 0xCE, 0x07,\n  0x3C, 0x38, 0x70, 0x21, 0x00, 0x00, 0x38, 0x00, 0x00, 0x70, 0x00, 0x00,\n  0xE0, 0x00, 0x01, 0xC0, 0x00, 0x03, 0x80, 0x00, 0x07, 0x00, 0x00, 0x0E,\n  0x00, 0x00, 0x1C, 0x00, 0x00, 0x38, 0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xE0, 0x07, 0x00, 0x00, 0x0E, 0x00,\n  0x00, 0x1C, 0x00, 0x00, 0x38, 0x00, 0x00, 0x70, 0x00, 0x00, 0xE0, 0x00,\n  0x01, 0xC0, 0x00, 0x03, 0x80, 0x00, 0x07, 0x00, 0x00, 0xFF, 0xFF, 0xF3,\n  0x33, 0x36, 0xEC, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0xFF, 0xFF, 0xF0,\n  0x00, 0x38, 0x01, 0xC0, 0x0C, 0x00, 0xE0, 0x07, 0x00, 0x30, 0x03, 0x80,\n  0x1C, 0x00, 0xC0, 0x06, 0x00, 0x70, 0x03, 0x80, 0x18, 0x01, 0xC0, 0x0E,\n  0x00, 0x60, 0x03, 0x00, 0x38, 0x01, 0x80, 0x0C, 0x00, 0xE0, 0x07, 0x00,\n  0x30, 0x03, 0x80, 0x1C, 0x00, 0xC0, 0x06, 0x00, 0x70, 0x03, 0x80, 0x18,\n  0x01, 0xC0, 0x0E, 0x00, 0x60, 0x07, 0x00, 0x38, 0x00, 0x00, 0xFC, 0x00,\n  0x0F, 0xFC, 0x00, 0xFF, 0xFC, 0x07, 0xFF, 0xF8, 0x1F, 0x87, 0xE0, 0xF8,\n  0x07, 0xC3, 0xC0, 0x0F, 0x1F, 0x00, 0x3E, 0x78, 0x00, 0x79, 0xE0, 0x01,\n  0xE7, 0x80, 0x07, 0xBC, 0x00, 0x0F, 0xF0, 0x00, 0x3F, 0xC0, 0x00, 0xFF,\n  0x00, 0x03, 0xFC, 0x00, 0x0F, 0xF0, 0x00, 0x3F, 0xC0, 0x00, 0xFF, 0x00,\n  0x03, 0xFC, 0x00, 0x0F, 0xF0, 0x00, 0x3F, 0xC0, 0x00, 0xFF, 0x00, 0x03,\n  0xDE, 0x00, 0x1E, 0x78, 0x00, 0x79, 0xE0, 0x01, 0xE7, 0xC0, 0x0F, 0x8F,\n  0x00, 0x3C, 0x3E, 0x01, 0xF0, 0x7C, 0x1F, 0x81, 0xFF, 0xFE, 0x03, 0xFF,\n  0xF0, 0x03, 0xFF, 0x00, 0x03, 0xF0, 0x00, 0x00, 0x60, 0x1C, 0x03, 0x80,\n  0xF0, 0x3E, 0x3F, 0xFF, 0xFF, 0xFF, 0xFF, 0xE0, 0x3C, 0x07, 0x80, 0xF0,\n  0x1E, 0x03, 0xC0, 0x78, 0x0F, 0x01, 0xE0, 0x3C, 0x07, 0x80, 0xF0, 0x1E,\n  0x03, 0xC0, 0x78, 0x0F, 0x01, 0xE0, 0x3C, 0x07, 0x80, 0xF0, 0x1E, 0x03,\n  0xC0, 0x78, 0x0F, 0x01, 0xE0, 0x01, 0xFE, 0x00, 0x1F, 0xFE, 0x01, 0xFF,\n  0xFE, 0x0F, 0xFF, 0xFC, 0x3F, 0x03, 0xF9, 0xF0, 0x03, 0xE7, 0x80, 0x07,\n  0xFE, 0x00, 0x1F, 0xF0, 0x00, 0x3F, 0xC0, 0x00, 0xFF, 0x00, 0x03, 0xC0,\n  0x00, 0x0F, 0x00, 0x00, 0x7C, 0x00, 0x01, 0xF0, 0x00, 0x0F, 0x80, 0x00,\n  0x7C, 0x00, 0x07, 0xF0, 0x00, 0x7F, 0x80, 0x07, 0xF8, 0x00, 0x3F, 0xC0,\n  0x03, 0xFC, 0x00, 0x1F, 0xC0, 0x00, 0xFC, 0x00, 0x07, 0xC0, 0x00, 0x3E,\n  0x00, 0x00, 0xE0, 0x00, 0x07, 0x80, 0x00, 0x1C, 0x00, 0x00, 0x70, 0x00,\n  0x03, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC,\n  0x00, 0xFE, 0x00, 0x0F, 0xFF, 0x80, 0x3F, 0xFF, 0x80, 0xFF, 0xFF, 0x83,\n  0xF0, 0x1F, 0x87, 0xC0, 0x1F, 0x1F, 0x00, 0x1F, 0x3C, 0x00, 0x1E, 0x78,\n  0x00, 0x3C, 0xF0, 0x00, 0x78, 0x00, 0x00, 0xF0, 0x00, 0x01, 0xE0, 0x00,\n  0x07, 0x80, 0x00, 0x7F, 0x00, 0x1F, 0xFC, 0x00, 0x3F, 0xE0, 0x00, 0x7F,\n  0xE0, 0x00, 0xFF, 0xF0, 0x00, 0x07, 0xF0, 0x00, 0x03, 0xE0, 0x00, 0x03,\n  0xE0, 0x00, 0x03, 0xC0, 0x00, 0x07, 0x80, 0x00, 0x0F, 0xF0, 0x00, 0x1F,\n  0xE0, 0x00, 0x3F, 0xE0, 0x00, 0xFB, 0xC0, 0x01, 0xE7, 0xC0, 0x07, 0xC7,\n  0xE0, 0x3F, 0x0F, 0xFF, 0xFE, 0x0F, 0xFF, 0xF8, 0x07, 0xFF, 0xC0, 0x03,\n  0xFC, 0x00, 0x00, 0x01, 0xC0, 0x00, 0x07, 0x80, 0x00, 0x1F, 0x00, 0x00,\n  0x7E, 0x00, 0x00, 0xFC, 0x00, 0x03, 0xF8, 0x00, 0x0F, 0xF0, 0x00, 0x3F,\n  0xE0, 0x00, 0x7B, 0xC0, 0x01, 0xE7, 0x80, 0x07, 0x8F, 0x00, 0x0F, 0x1E,\n  0x00, 0x3C, 0x3C, 0x00, 0xF0, 0x78, 0x03, 0xC0, 0xF0, 0x07, 0x81, 0xE0,\n  0x1E, 0x03, 0xC0, 0x78, 0x07, 0x81, 0xE0, 0x0F, 0x03, 0xC0, 0x1E, 0x0F,\n  0x00, 0x3C, 0x1F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFE, 0x00, 0x07, 0x80, 0x00, 0x0F, 0x00, 0x00, 0x1E, 0x00, 0x00,\n  0x3C, 0x00, 0x00, 0x78, 0x00, 0x00, 0xF0, 0x00, 0x01, 0xE0, 0x00, 0x03,\n  0xC0, 0x1F, 0xFF, 0xF0, 0x7F, 0xFF, 0xC1, 0xFF, 0xFF, 0x07, 0xFF, 0xFC,\n  0x3C, 0x00, 0x00, 0xF0, 0x00, 0x03, 0xC0, 0x00, 0x0F, 0x00, 0x00, 0x3C,\n  0x00, 0x00, 0xF0, 0x00, 0x03, 0xC0, 0x00, 0x1F, 0x3F, 0x80, 0x7B, 0xFF,\n  0x81, 0xFF, 0xFF, 0x07, 0xFF, 0xFE, 0x1F, 0x80, 0xFC, 0x78, 0x01, 0xF8,\n  0x00, 0x03, 0xE0, 0x00, 0x07, 0xC0, 0x00, 0x0F, 0x00, 0x00, 0x3C, 0x00,\n  0x00, 0xF0, 0x00, 0x03, 0xC0, 0x00, 0x0F, 0x00, 0x00, 0x3F, 0xC0, 0x00,\n  0xFF, 0x80, 0x07, 0x9E, 0x00, 0x1E, 0x7C, 0x00, 0xF1, 0xFC, 0x0F, 0xC3,\n  0xFF, 0xFE, 0x07, 0xFF, 0xF0, 0x0F, 0xFF, 0x80, 0x07, 0xF0, 0x00, 0x00,\n  0xFE, 0x00, 0x0F, 0xFE, 0x00, 0x7F, 0xFC, 0x03, 0xFF, 0xF8, 0x1F, 0x83,\n  0xF0, 0xF8, 0x07, 0xC3, 0xC0, 0x0F, 0x8F, 0x00, 0x1E, 0x78, 0x00, 0x79,\n  0xE0, 0x00, 0x07, 0x00, 0x00, 0x3C, 0x00, 0x00, 0xF0, 0xFE, 0x03, 0xCF,\n  0xFE, 0x0F, 0x7F, 0xFE, 0x3F, 0xFF, 0xFC, 0xFF, 0x03, 0xF3, 0xF0, 0x03,\n  0xEF, 0x80, 0x07, 0xBE, 0x00, 0x1F, 0xF0, 0x00, 0x3F, 0xC0, 0x00, 0xFF,\n  0x00, 0x03, 0xFC, 0x00, 0x0F, 0x70, 0x00, 0x3D, 0xC0, 0x00, 0xF7, 0x80,\n  0x07, 0x9F, 0x00, 0x3E, 0x3E, 0x00, 0xF8, 0xFC, 0x0F, 0xC1, 0xFF, 0xFE,\n  0x03, 0xFF, 0xF0, 0x07, 0xFF, 0x80, 0x07, 0xF8, 0x00, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0x00, 0x07, 0x00, 0x00,\n  0x78, 0x00, 0x07, 0x80, 0x00, 0x38, 0x00, 0x03, 0xC0, 0x00, 0x3C, 0x00,\n  0x01, 0xC0, 0x00, 0x1E, 0x00, 0x00, 0xE0, 0x00, 0x0F, 0x00, 0x00, 0x70,\n  0x00, 0x07, 0x80, 0x00, 0x38, 0x00, 0x03, 0xC0, 0x00, 0x1C, 0x00, 0x01,\n  0xE0, 0x00, 0x0E, 0x00, 0x00, 0xF0, 0x00, 0x07, 0x80, 0x00, 0x38, 0x00,\n  0x03, 0xC0, 0x00, 0x1E, 0x00, 0x00, 0xE0, 0x00, 0x0F, 0x00, 0x00, 0x78,\n  0x00, 0x03, 0xC0, 0x00, 0x1C, 0x00, 0x01, 0xE0, 0x00, 0x0F, 0x00, 0x00,\n  0x01, 0xFE, 0x00, 0x1F, 0xFE, 0x00, 0xFF, 0xFC, 0x07, 0xFF, 0xF8, 0x3F,\n  0x03, 0xF1, 0xF0, 0x03, 0xC7, 0xC0, 0x0F, 0x9E, 0x00, 0x1E, 0x78, 0x00,\n  0x79, 0xE0, 0x01, 0xE7, 0x80, 0x0F, 0x8F, 0x00, 0x3C, 0x3F, 0x03, 0xF0,\n  0x7F, 0xFF, 0x80, 0x7F, 0xF8, 0x03, 0xFF, 0xF0, 0x1F, 0xFF, 0xE0, 0xFC,\n  0x0F, 0xC7, 0xC0, 0x0F, 0x9E, 0x00, 0x1E, 0xF8, 0x00, 0x7F, 0xC0, 0x00,\n  0xFF, 0x00, 0x03, 0xFC, 0x00, 0x0F, 0xF0, 0x00, 0x3F, 0xC0, 0x00, 0xFF,\n  0x80, 0x07, 0xDE, 0x00, 0x1E, 0x7C, 0x00, 0xF8, 0xFC, 0x0F, 0xC3, 0xFF,\n  0xFF, 0x07, 0xFF, 0xF8, 0x07, 0xFF, 0x80, 0x07, 0xF8, 0x00, 0x01, 0xFC,\n  0x00, 0x3F, 0xF8, 0x03, 0xFF, 0xE0, 0x3F, 0xFF, 0x83, 0xF0, 0x7E, 0x3E,\n  0x00, 0xF1, 0xE0, 0x07, 0xCF, 0x00, 0x1E, 0xF0, 0x00, 0x77, 0x80, 0x03,\n  0xBC, 0x00, 0x1F, 0xE0, 0x00, 0xFF, 0x00, 0x07, 0xF8, 0x00, 0x3F, 0xE0,\n  0x03, 0xEF, 0x00, 0x1F, 0x7C, 0x01, 0xF9, 0xF8, 0x3F, 0xCF, 0xFF, 0xFE,\n  0x3F, 0xFE, 0xF0, 0xFF, 0xE7, 0x80, 0xFC, 0x3C, 0x00, 0x01, 0xE0, 0x00,\n  0x0E, 0x00, 0x00, 0xF0, 0x00, 0x07, 0x9E, 0x00, 0x3C, 0xF0, 0x03, 0xC7,\n  0xC0, 0x3E, 0x1F, 0x03, 0xE0, 0xFF, 0xFE, 0x03, 0xFF, 0xE0, 0x0F, 0xFE,\n  0x00, 0x1F, 0xC0, 0x00, 0xFF, 0xFF, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0xFF, 0xFF, 0xF0, 0xFF, 0xFF, 0xF0, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0xFF, 0xFF, 0xF3, 0x33, 0x36, 0xEC, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x1C, 0x00, 0x00, 0xF8, 0x00, 0x07, 0xF0, 0x00, 0x7F, 0xC0,\n  0x03, 0xFC, 0x00, 0x3F, 0xE0, 0x01, 0xFF, 0x00, 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 0xFF, 0xE0, 0x07, 0x00, 0x18, 0x00, 0xE0, 0x07, 0x00, 0x18, 0x00, 0xE0,\n  0x07, 0x00, 0x18, 0x00, 0xC0, 0x07, 0x00, 0x38, 0x00, 0xC0, 0x07, 0x00,\n  0x38, 0x00, 0xC0, 0x06, 0x00, 0x38, 0x00, 0xC0, 0x06, 0x00, 0x38, 0x01,\n  0xC0, 0x06, 0x00, 0x38, 0x01, 0xC0, 0x06, 0x00, 0x30, 0x01, 0xC0, 0x0E,\n  0x00, 0x30, 0x01, 0xC0, 0x0E, 0x00, 0x30, 0x01, 0xC0, 0x0E, 0xFF, 0xFF,\n  0xFF, 0xFF, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F,\n  0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F,\n  0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F,\n  0x0F, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0xE0, 0x00, 0x78, 0x00, 0x3F,\n  0x00, 0x0F, 0xC0, 0x07, 0xF8, 0x01, 0xCE, 0x00, 0x73, 0x80, 0x3C, 0x70,\n  0x0E, 0x1C, 0x07, 0x87, 0x81, 0xC0, 0xE0, 0x70, 0x38, 0x38, 0x07, 0x0E,\n  0x01, 0xC7, 0x80, 0x79, 0xC0, 0x0E, 0x70, 0x03, 0xB8, 0x00, 0x70, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0x0F, 0x01, 0xE0, 0x3C, 0x07,\n  0x00, 0xE0, 0x1C, 0x01, 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0xFC, 0xF8, 0x07, 0xF7, 0xC0, 0x0F, 0xDE, 0x00,\n  0x1F, 0x78, 0x00, 0x7F, 0xE0, 0x00, 0xFF, 0x00, 0x03, 0xFC, 0x00, 0x0F,\n  0xF0, 0x00, 0x3F, 0xC0, 0x00, 0xFF, 0x00, 0x03, 0xFC, 0x00, 0x0F, 0xF0,\n  0x00, 0x3F, 0xC0, 0x00, 0xF7, 0x80, 0x07, 0xDE, 0x00, 0x1F, 0x7C, 0x00,\n  0xFC, 0xF8, 0x07, 0xF3, 0xF8, 0x3F, 0xC7, 0xFF, 0xEF, 0x0F, 0xFF, 0x3C,\n  0x1F, 0xF8, 0xF0, 0x1F, 0x83, 0xC0, 0x00, 0x0F, 0x00, 0x00, 0x79, 0xE0,\n  0x01, 0xE7, 0xC0, 0x0F, 0x8F, 0x80, 0xFC, 0x3F, 0xFF, 0xF0, 0x7F, 0xFF,\n  0x80, 0xFF, 0xFC, 0x00, 0x7F, 0x80, 0xF0, 0x00, 0x1E, 0x00, 0x03, 0xC0,\n  0x00, 0x78, 0x00, 0x0F, 0x00, 0x01, 0xE0, 0x00, 0x3C, 0x00, 0x07, 0x80,\n  0x00, 0xF0, 0xFE, 0x1E, 0x3F, 0xE3, 0xCF, 0xFF, 0x7B, 0xFF, 0xEF, 0xF0,\n  0xFF, 0xF8, 0x07, 0xFF, 0x00, 0x7F, 0xC0, 0x0F, 0xF8, 0x01, 0xFE, 0x00,\n  0x3F, 0xC0, 0x07, 0xF8, 0x00, 0xFF, 0x00, 0x1F, 0xE0, 0x03, 0xFC, 0x00,\n  0x7F, 0x80, 0x0F, 0xF0, 0x01, 0xFE, 0x00, 0x3F, 0xC0, 0x07, 0xF8, 0x00,\n  0xFF, 0x00, 0x1F, 0xE0, 0x03, 0xFC, 0x00, 0x7F, 0x80, 0x0F, 0xF0, 0x01,\n  0xFE, 0x00, 0x3C, 0xFF, 0xFF, 0xF0, 0x00, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x0F, 0x0F, 0x0F, 0x0F,\n  0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F,\n  0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F,\n  0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x1F,\n  0xFF, 0xFE, 0xFE, 0xF8, 0xF0, 0x00, 0x07, 0x80, 0x00, 0x3C, 0x00, 0x01,\n  0xE0, 0x00, 0x0F, 0x00, 0x00, 0x78, 0x00, 0x03, 0xC0, 0x00, 0x1E, 0x00,\n  0x00, 0xF0, 0x00, 0x07, 0x80, 0x1F, 0x3C, 0x01, 0xF1, 0xE0, 0x1F, 0x0F,\n  0x01, 0xF0, 0x78, 0x1F, 0x03, 0xC1, 0xF0, 0x1E, 0x1F, 0x00, 0xF1, 0xF0,\n  0x07, 0x9F, 0x00, 0x3D, 0xF8, 0x01, 0xFF, 0xE0, 0x0F, 0xFF, 0x80, 0x7F,\n  0x7C, 0x03, 0xF1, 0xF0, 0x1F, 0x07, 0xC0, 0xF0, 0x3E, 0x07, 0x80, 0xF8,\n  0x3C, 0x03, 0xC1, 0xE0, 0x1F, 0x0F, 0x00, 0x7C, 0x78, 0x03, 0xE3, 0xC0,\n  0x0F, 0x9E, 0x00, 0x3C, 0xF0, 0x01, 0xF7, 0x80, 0x07, 0xC0, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0x00, 0xFC, 0x03, 0xF0, 0xE3, 0xFE, 0x0F, 0xFC, 0xE7,\n  0xFF, 0x1F, 0xFE, 0xEF, 0xFF, 0xBF, 0xFE, 0xFE, 0x0F, 0xF8, 0x3F, 0xFC,\n  0x07, 0xF0, 0x1F, 0xF8, 0x03, 0xE0, 0x0F, 0xF8, 0x03, 0xE0, 0x0F, 0xF0,\n  0x03, 0xC0, 0x0F, 0xF0, 0x03, 0xC0, 0x0F, 0xF0, 0x03, 0xC0, 0x0F, 0xF0,\n  0x03, 0xC0, 0x0F, 0xF0, 0x03, 0xC0, 0x0F, 0xF0, 0x03, 0xC0, 0x0F, 0xF0,\n  0x03, 0xC0, 0x0F, 0xF0, 0x03, 0xC0, 0x0F, 0xF0, 0x03, 0xC0, 0x0F, 0xF0,\n  0x03, 0xC0, 0x0F, 0xF0, 0x03, 0xC0, 0x0F, 0xF0, 0x03, 0xC0, 0x0F, 0xF0,\n  0x03, 0xC0, 0x0F, 0xF0, 0x03, 0xC0, 0x0F, 0xF0, 0x03, 0xC0, 0x0F, 0xF0,\n  0x03, 0xC0, 0x0F, 0xF0, 0x03, 0xC0, 0x0F, 0xF0, 0x03, 0xC0, 0x0F, 0x00,\n  0x7E, 0x0E, 0x1F, 0xF8, 0xE7, 0xFF, 0xCE, 0xFF, 0xFE, 0xEF, 0x07, 0xFF,\n  0xE0, 0x1F, 0xFC, 0x01, 0xFF, 0x80, 0x0F, 0xF8, 0x00, 0xFF, 0x00, 0x0F,\n  0xF0, 0x00, 0xFF, 0x00, 0x0F, 0xF0, 0x00, 0xFF, 0x00, 0x0F, 0xF0, 0x00,\n  0xFF, 0x00, 0x0F, 0xF0, 0x00, 0xFF, 0x00, 0x0F, 0xF0, 0x00, 0xFF, 0x00,\n  0x0F, 0xF0, 0x00, 0xFF, 0x00, 0x0F, 0xF0, 0x00, 0xFF, 0x00, 0x0F, 0xF0,\n  0x00, 0xFF, 0x00, 0x0F, 0x00, 0xFE, 0x00, 0x07, 0xFF, 0x00, 0x3F, 0xFF,\n  0x80, 0xFF, 0xFF, 0x83, 0xF8, 0x3F, 0x87, 0xC0, 0x1F, 0x1F, 0x00, 0x1F,\n  0x3C, 0x00, 0x1E, 0x78, 0x00, 0x3D, 0xF0, 0x00, 0x7F, 0xC0, 0x00, 0x7F,\n  0x80, 0x00, 0xFF, 0x00, 0x01, 0xFE, 0x00, 0x03, 0xFC, 0x00, 0x07, 0xF8,\n  0x00, 0x0F, 0xF0, 0x00, 0x1F, 0xF0, 0x00, 0x7D, 0xE0, 0x00, 0xF3, 0xC0,\n  0x01, 0xE7, 0xC0, 0x07, 0xC7, 0xC0, 0x1F, 0x0F, 0xE0, 0xFE, 0x0F, 0xFF,\n  0xF8, 0x0F, 0xFF, 0xE0, 0x0F, 0xFF, 0x80, 0x03, 0xF8, 0x00, 0x00, 0xFE,\n  0x03, 0x8F, 0xFE, 0x0E, 0x7F, 0xFC, 0x3B, 0xFF, 0xF8, 0xFF, 0x87, 0xF3,\n  0xF8, 0x07, 0xCF, 0xC0, 0x0F, 0xBE, 0x00, 0x1E, 0xF8, 0x00, 0x7B, 0xE0,\n  0x01, 0xFF, 0x00, 0x03, 0xFC, 0x00, 0x0F, 0xF0, 0x00, 0x3F, 0xC0, 0x00,\n  0xFF, 0x00, 0x03, 0xFC, 0x00, 0x0F, 0xF0, 0x00, 0x3F, 0xC0, 0x01, 0xFF,\n  0x80, 0x07, 0xBE, 0x00, 0x1E, 0xFC, 0x00, 0xFB, 0xF8, 0x07, 0xCF, 0xF0,\n  0x7F, 0x3F, 0xFF, 0xF8, 0xF7, 0xFF, 0xC3, 0xC7, 0xFE, 0x0F, 0x07, 0xE0,\n  0x3C, 0x00, 0x00, 0xF0, 0x00, 0x03, 0xC0, 0x00, 0x0F, 0x00, 0x00, 0x3C,\n  0x00, 0x00, 0xF0, 0x00, 0x03, 0xC0, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00,\n  0xFE, 0x00, 0x07, 0xFF, 0x1C, 0x3F, 0xFF, 0x38, 0xFF, 0xFF, 0x73, 0xF8,\n  0x3F, 0xE7, 0xC0, 0x1F, 0xDF, 0x00, 0x1F, 0xBE, 0x00, 0x1F, 0x78, 0x00,\n  0x3F, 0xF0, 0x00, 0x7F, 0xC0, 0x00, 0x7F, 0x80, 0x00, 0xFF, 0x00, 0x01,\n  0xFE, 0x00, 0x03, 0xFC, 0x00, 0x07, 0xF8, 0x00, 0x0F, 0xF0, 0x00, 0x1F,\n  0xF0, 0x00, 0x7D, 0xE0, 0x00, 0xFB, 0xC0, 0x01, 0xF7, 0xC0, 0x07, 0xE7,\n  0xC0, 0x1F, 0xCF, 0xE0, 0xFF, 0x8F, 0xFF, 0xEF, 0x0F, 0xFF, 0xDE, 0x0F,\n  0xFE, 0x3C, 0x07, 0xF0, 0x78, 0x00, 0x00, 0xF0, 0x00, 0x01, 0xE0, 0x00,\n  0x03, 0xC0, 0x00, 0x07, 0x80, 0x00, 0x0F, 0x00, 0x00, 0x1E, 0x00, 0x00,\n  0x3C, 0x00, 0x00, 0x78, 0x00, 0xFE, 0x1F, 0xE7, 0xFE, 0xFF, 0xFF, 0x8F,\n  0xC0, 0xF8, 0x0F, 0x80, 0xF8, 0x0F, 0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x0F,\n  0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x0F,\n  0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0x00, 0x01, 0xFC, 0x00, 0xFF, 0xF0,\n  0x1F, 0xFF, 0x83, 0xFF, 0xFC, 0x3E, 0x07, 0xE7, 0xC0, 0x3E, 0x78, 0x01,\n  0xE7, 0x80, 0x00, 0x78, 0x00, 0x07, 0xC0, 0x00, 0x7E, 0x00, 0x03, 0xFC,\n  0x00, 0x1F, 0xFC, 0x00, 0xFF, 0xF8, 0x03, 0xFF, 0xC0, 0x03, 0xFE, 0x00,\n  0x03, 0xF0, 0x00, 0x1F, 0x00, 0x00, 0xFF, 0x00, 0x0F, 0xF0, 0x00, 0xFF,\n  0x80, 0x1F, 0x7E, 0x07, 0xE7, 0xFF, 0xFE, 0x3F, 0xFF, 0xC1, 0xFF, 0xF0,\n  0x03, 0xFC, 0x00, 0x1E, 0x07, 0x81, 0xE0, 0x78, 0x1E, 0x07, 0x8F, 0xFF,\n  0xFF, 0xFF, 0xC7, 0x81, 0xE0, 0x78, 0x1E, 0x07, 0x81, 0xE0, 0x78, 0x1E,\n  0x07, 0x81, 0xE0, 0x78, 0x1E, 0x07, 0x81, 0xE0, 0x78, 0x1E, 0x07, 0x81,\n  0xE0, 0x78, 0x1F, 0xC7, 0xF0, 0xFC, 0x1F, 0xF0, 0x00, 0xFF, 0x00, 0x0F,\n  0xF0, 0x00, 0xFF, 0x00, 0x0F, 0xF0, 0x00, 0xFF, 0x00, 0x0F, 0xF0, 0x00,\n  0xFF, 0x00, 0x0F, 0xF0, 0x00, 0xFF, 0x00, 0x0F, 0xF0, 0x00, 0xFF, 0x00,\n  0x0F, 0xF0, 0x00, 0xFF, 0x00, 0x0F, 0xF0, 0x00, 0xFF, 0x00, 0x0F, 0xF0,\n  0x00, 0xFF, 0x00, 0x1F, 0xF0, 0x01, 0xFF, 0x00, 0x3F, 0xF8, 0x07, 0xFF,\n  0xE0, 0xFF, 0x7F, 0xFF, 0x77, 0xFF, 0xE7, 0x1F, 0xFC, 0x70, 0x7E, 0x00,\n  0x78, 0x00, 0x3E, 0xF0, 0x00, 0x79, 0xF0, 0x00, 0xF1, 0xE0, 0x03, 0xE3,\n  0xC0, 0x07, 0x87, 0xC0, 0x0F, 0x07, 0x80, 0x3C, 0x0F, 0x00, 0x78, 0x1F,\n  0x01, 0xF0, 0x1E, 0x03, 0xC0, 0x3C, 0x07, 0x80, 0x7C, 0x1F, 0x00, 0x78,\n  0x3C, 0x00, 0xF0, 0x78, 0x01, 0xF1, 0xE0, 0x01, 0xE3, 0xC0, 0x03, 0xC7,\n  0x80, 0x03, 0xDE, 0x00, 0x07, 0xBC, 0x00, 0x0F, 0x70, 0x00, 0x0F, 0xE0,\n  0x00, 0x1F, 0xC0, 0x00, 0x3F, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x7C, 0x00,\n  0xF8, 0x03, 0xE0, 0x07, 0x9E, 0x00, 0xFC, 0x01, 0xE7, 0x80, 0x3F, 0x00,\n  0x79, 0xF0, 0x0F, 0xC0, 0x3E, 0x3C, 0x07, 0xF0, 0x0F, 0x0F, 0x01, 0xFE,\n  0x03, 0xC3, 0xC0, 0x7F, 0x80, 0xF0, 0x78, 0x1D, 0xE0, 0x78, 0x1E, 0x0F,\n  0x38, 0x1E, 0x07, 0x83, 0xCF, 0x07, 0x81, 0xE0, 0xF3, 0xC1, 0xE0, 0x3C,\n  0x38, 0xF0, 0xF0, 0x0F, 0x1E, 0x1C, 0x3C, 0x03, 0xC7, 0x87, 0x8F, 0x00,\n  0x71, 0xE1, 0xE3, 0x80, 0x1E, 0x70, 0x79, 0xE0, 0x07, 0xBC, 0x0E, 0x78,\n  0x01, 0xEF, 0x03, 0xDE, 0x00, 0x3B, 0xC0, 0xF7, 0x00, 0x0F, 0xE0, 0x3F,\n  0xC0, 0x03, 0xF8, 0x07, 0xF0, 0x00, 0x7E, 0x01, 0xF8, 0x00, 0x1F, 0x80,\n  0x7E, 0x00, 0x07, 0xC0, 0x1F, 0x80, 0x01, 0xF0, 0x03, 0xC0, 0x00, 0x7C,\n  0x00, 0x78, 0xF0, 0x03, 0xE1, 0xE0, 0x0F, 0x07, 0xC0, 0x78, 0x0F, 0x03,\n  0xE0, 0x1E, 0x0F, 0x00, 0x7C, 0x78, 0x00, 0xF3, 0xE0, 0x01, 0xEF, 0x00,\n  0x07, 0xF8, 0x00, 0x0F, 0xC0, 0x00, 0x1F, 0x00, 0x00, 0x7C, 0x00, 0x03,\n  0xF0, 0x00, 0x0F, 0xE0, 0x00, 0x7F, 0xC0, 0x03, 0xCF, 0x00, 0x0F, 0x1E,\n  0x00, 0x78, 0x7C, 0x03, 0xE0, 0xF0, 0x0F, 0x03, 0xE0, 0x78, 0x07, 0xC3,\n  0xE0, 0x0F, 0x1F, 0x00, 0x3E, 0x78, 0x00, 0x7C, 0x78, 0x00, 0x3D, 0xE0,\n  0x01, 0xF7, 0x80, 0x07, 0x8F, 0x00, 0x1E, 0x3C, 0x00, 0xF0, 0xF0, 0x03,\n  0xC1, 0xE0, 0x0F, 0x07, 0x80, 0x78, 0x1E, 0x01, 0xE0, 0x3C, 0x07, 0x80,\n  0xF0, 0x3C, 0x03, 0xC0, 0xF0, 0x07, 0x87, 0xC0, 0x1E, 0x1E, 0x00, 0x78,\n  0x78, 0x00, 0xF3, 0xC0, 0x03, 0xCF, 0x00, 0x0F, 0x3C, 0x00, 0x1F, 0xE0,\n  0x00, 0x7F, 0x80, 0x01, 0xFE, 0x00, 0x03, 0xF0, 0x00, 0x0F, 0xC0, 0x00,\n  0x3E, 0x00, 0x00, 0x78, 0x00, 0x01, 0xE0, 0x00, 0x0F, 0x00, 0x00, 0x3C,\n  0x00, 0x01, 0xF0, 0x00, 0x07, 0x80, 0x00, 0x3E, 0x00, 0x0F, 0xF0, 0x00,\n  0x3F, 0xC0, 0x00, 0xFE, 0x00, 0x01, 0xE0, 0x00, 0x00, 0x7F, 0xFF, 0xF7,\n  0xFF, 0xFF, 0x7F, 0xFF, 0xF7, 0xFF, 0xFF, 0x00, 0x01, 0xE0, 0x00, 0x3E,\n  0x00, 0x07, 0xC0, 0x00, 0xF8, 0x00, 0x1F, 0x00, 0x03, 0xE0, 0x00, 0x7C,\n  0x00, 0x07, 0x80, 0x00, 0xF8, 0x00, 0x1F, 0x00, 0x03, 0xE0, 0x00, 0x7C,\n  0x00, 0x0F, 0x80, 0x01, 0xF0, 0x00, 0x3E, 0x00, 0x03, 0xC0, 0x00, 0x7C,\n  0x00, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0,\n  0x01, 0xE0, 0xFC, 0x1F, 0x87, 0x80, 0xE0, 0x1C, 0x03, 0x80, 0x70, 0x0E,\n  0x01, 0xC0, 0x38, 0x07, 0x00, 0xE0, 0x1C, 0x03, 0x80, 0x70, 0x0E, 0x01,\n  0xC0, 0x78, 0x1E, 0x0F, 0x81, 0xE0, 0x3C, 0x07, 0xC0, 0x3C, 0x03, 0x80,\n  0x38, 0x07, 0x00, 0xE0, 0x1C, 0x03, 0x80, 0x70, 0x0E, 0x01, 0xC0, 0x38,\n  0x07, 0x00, 0xE0, 0x1C, 0x03, 0x80, 0x70, 0x0F, 0x00, 0xFC, 0x1F, 0x80,\n  0xF0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0xF0, 0x1F, 0x83, 0xF0, 0x0F, 0x00,\n  0xE0, 0x1C, 0x03, 0x80, 0x70, 0x0E, 0x01, 0xC0, 0x38, 0x07, 0x00, 0xE0,\n  0x1C, 0x03, 0x80, 0x70, 0x0E, 0x01, 0xC0, 0x1C, 0x03, 0xC0, 0x3E, 0x03,\n  0xC0, 0x78, 0x1F, 0x07, 0x80, 0xE0, 0x38, 0x07, 0x00, 0xE0, 0x1C, 0x03,\n  0x80, 0x70, 0x0E, 0x01, 0xC0, 0x38, 0x07, 0x00, 0xE0, 0x1C, 0x03, 0x80,\n  0x70, 0x1E, 0x1F, 0x83, 0xF0, 0x78, 0x00, 0x3E, 0x00, 0x0F, 0xF0, 0x0D,\n  0xFF, 0x01, 0xF0, 0xF8, 0x7C, 0x0F, 0xFD, 0x80, 0x7F, 0x80, 0x03, 0xE0 };\n\nconst GFXglyph FreeSans24pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,  12,    0,    1 },   // 0x20 ' '\n  {     0,   4,  34,  16,    6,  -33 },   // 0x21 '!'\n  {    17,  11,  12,  16,    2,  -32 },   // 0x22 '\"'\n  {    34,  24,  33,  26,    1,  -31 },   // 0x23 '#'\n  {   133,  23,  41,  26,    1,  -34 },   // 0x24 '$'\n  {   251,  39,  34,  42,    1,  -32 },   // 0x25 '%'\n  {   417,  28,  34,  31,    2,  -32 },   // 0x26 '&'\n  {   536,   4,  12,   9,    2,  -32 },   // 0x27 '''\n  {   542,  10,  44,  16,    3,  -33 },   // 0x28 '('\n  {   597,  10,  44,  16,    2,  -33 },   // 0x29 ')'\n  {   652,  14,  14,  18,    2,  -33 },   // 0x2A '*'\n  {   677,  23,  22,  27,    2,  -21 },   // 0x2B '+'\n  {   741,   4,  12,  13,    4,   -4 },   // 0x2C ','\n  {   747,  11,   4,  16,    2,  -14 },   // 0x2D '-'\n  {   753,   4,   5,  12,    4,   -4 },   // 0x2E '.'\n  {   756,  13,  35,  13,    0,  -33 },   // 0x2F '/'\n  {   813,  22,  34,  26,    2,  -32 },   // 0x30 '0'\n  {   907,  11,  33,  26,    5,  -32 },   // 0x31 '1'\n  {   953,  22,  33,  26,    2,  -32 },   // 0x32 '2'\n  {  1044,  23,  34,  26,    1,  -32 },   // 0x33 '3'\n  {  1142,  23,  33,  26,    1,  -32 },   // 0x34 '4'\n  {  1237,  22,  34,  26,    2,  -32 },   // 0x35 '5'\n  {  1331,  22,  34,  26,    2,  -32 },   // 0x36 '6'\n  {  1425,  21,  33,  26,    2,  -32 },   // 0x37 '7'\n  {  1512,  22,  34,  26,    2,  -32 },   // 0x38 '8'\n  {  1606,  21,  34,  26,    2,  -32 },   // 0x39 '9'\n  {  1696,   4,  25,  12,    4,  -24 },   // 0x3A ':'\n  {  1709,   4,  32,  12,    4,  -24 },   // 0x3B ';'\n  {  1725,  23,  23,  27,    2,  -22 },   // 0x3C '<'\n  {  1792,  23,  12,  27,    2,  -16 },   // 0x3D '='\n  {  1827,  23,  23,  27,    2,  -22 },   // 0x3E '>'\n  {  1894,  20,  35,  26,    4,  -34 },   // 0x3F '?'\n  {  1982,  43,  42,  48,    2,  -34 },   // 0x40 '@'\n  {  2208,  30,  34,  31,    1,  -33 },   // 0x41 'A'\n  {  2336,  25,  34,  31,    4,  -33 },   // 0x42 'B'\n  {  2443,  29,  36,  33,    2,  -34 },   // 0x43 'C'\n  {  2574,  27,  34,  33,    4,  -33 },   // 0x44 'D'\n  {  2689,  24,  34,  30,    4,  -33 },   // 0x45 'E'\n  {  2791,  22,  34,  28,    4,  -33 },   // 0x46 'F'\n  {  2885,  31,  36,  36,    2,  -34 },   // 0x47 'G'\n  {  3025,  26,  34,  34,    4,  -33 },   // 0x48 'H'\n  {  3136,   4,  34,  13,    5,  -33 },   // 0x49 'I'\n  {  3153,  19,  35,  25,    2,  -33 },   // 0x4A 'J'\n  {  3237,  27,  34,  32,    4,  -33 },   // 0x4B 'K'\n  {  3352,  21,  34,  26,    4,  -33 },   // 0x4C 'L'\n  {  3442,  32,  34,  40,    4,  -33 },   // 0x4D 'M'\n  {  3578,  26,  34,  34,    4,  -33 },   // 0x4E 'N'\n  {  3689,  33,  36,  37,    2,  -34 },   // 0x4F 'O'\n  {  3838,  24,  34,  31,    4,  -33 },   // 0x50 'P'\n  {  3940,  33,  38,  37,    2,  -34 },   // 0x51 'Q'\n  {  4097,  26,  34,  33,    4,  -33 },   // 0x52 'R'\n  {  4208,  27,  36,  31,    2,  -34 },   // 0x53 'S'\n  {  4330,  26,  34,  30,    2,  -33 },   // 0x54 'T'\n  {  4441,  26,  35,  34,    4,  -33 },   // 0x55 'U'\n  {  4555,  29,  34,  30,    1,  -33 },   // 0x56 'V'\n  {  4679,  42,  34,  44,    1,  -33 },   // 0x57 'W'\n  {  4858,  29,  34,  31,    1,  -33 },   // 0x58 'X'\n  {  4982,  30,  34,  32,    1,  -33 },   // 0x59 'Y'\n  {  5110,  27,  34,  29,    1,  -33 },   // 0x5A 'Z'\n  {  5225,   8,  44,  13,    3,  -33 },   // 0x5B '['\n  {  5269,  13,  35,  13,    0,  -33 },   // 0x5C '\\'\n  {  5326,   8,  44,  13,    1,  -33 },   // 0x5D ']'\n  {  5370,  18,  18,  22,    2,  -32 },   // 0x5E '^'\n  {  5411,  28,   2,  26,   -1,    7 },   // 0x5F '_'\n  {  5418,  10,   7,  12,    1,  -34 },   // 0x60 '`'\n  {  5427,  24,  27,  26,    1,  -25 },   // 0x61 'a'\n  {  5508,  22,  35,  26,    3,  -33 },   // 0x62 'b'\n  {  5605,  21,  27,  24,    1,  -25 },   // 0x63 'c'\n  {  5676,  23,  35,  26,    1,  -33 },   // 0x64 'd'\n  {  5777,  22,  27,  25,    1,  -25 },   // 0x65 'e'\n  {  5852,  10,  34,  13,    1,  -33 },   // 0x66 'f'\n  {  5895,  22,  36,  26,    1,  -25 },   // 0x67 'g'\n  {  5994,  19,  34,  25,    3,  -33 },   // 0x68 'h'\n  {  6075,   4,  34,  10,    3,  -33 },   // 0x69 'i'\n  {  6092,   8,  44,  11,    0,  -33 },   // 0x6A 'j'\n  {  6136,  21,  34,  24,    3,  -33 },   // 0x6B 'k'\n  {  6226,   4,  34,  10,    3,  -33 },   // 0x6C 'l'\n  {  6243,  32,  26,  38,    3,  -25 },   // 0x6D 'm'\n  {  6347,  20,  26,  25,    3,  -25 },   // 0x6E 'n'\n  {  6412,  23,  27,  25,    1,  -25 },   // 0x6F 'o'\n  {  6490,  22,  35,  26,    3,  -25 },   // 0x70 'p'\n  {  6587,  23,  35,  26,    1,  -25 },   // 0x71 'q'\n  {  6688,  12,  26,  16,    3,  -25 },   // 0x72 'r'\n  {  6727,  20,  27,  23,    1,  -25 },   // 0x73 's'\n  {  6795,  10,  32,  13,    1,  -30 },   // 0x74 't'\n  {  6835,  20,  26,  25,    3,  -24 },   // 0x75 'u'\n  {  6900,  23,  25,  23,    0,  -24 },   // 0x76 'v'\n  {  6972,  34,  25,  34,    0,  -24 },   // 0x77 'w'\n  {  7079,  22,  25,  22,    0,  -24 },   // 0x78 'x'\n  {  7148,  22,  35,  22,    0,  -24 },   // 0x79 'y'\n  {  7245,  20,  25,  23,    1,  -24 },   // 0x7A 'z'\n  {  7308,  11,  44,  16,    2,  -33 },   // 0x7B '{'\n  {  7369,   3,  44,  12,    4,  -33 },   // 0x7C '|'\n  {  7386,  11,  44,  16,    2,  -33 },   // 0x7D '}'\n  {  7447,  19,   7,  24,    2,  -19 } }; // 0x7E '~'\n\nconst GFXfont FreeSans24pt7b PROGMEM = {\n  (uint8_t  *)FreeSans24pt7bBitmaps,\n  (GFXglyph *)FreeSans24pt7bGlyphs,\n  0x20, 0x7E, 56 };\n\n// Approx. 8136 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeSans9pt7b.h",
    "content": "const uint8_t FreeSans9pt7bBitmaps[] PROGMEM = {\n  0xFF, 0xFF, 0xF8, 0xC0, 0xDE, 0xF7, 0x20, 0x09, 0x86, 0x41, 0x91, 0xFF,\n  0x13, 0x04, 0xC3, 0x20, 0xC8, 0xFF, 0x89, 0x82, 0x61, 0x90, 0x10, 0x1F,\n  0x14, 0xDA, 0x3D, 0x1E, 0x83, 0x40, 0x78, 0x17, 0x08, 0xF4, 0x7A, 0x35,\n  0x33, 0xF0, 0x40, 0x20, 0x38, 0x10, 0xEC, 0x20, 0xC6, 0x20, 0xC6, 0x40,\n  0xC6, 0x40, 0x6C, 0x80, 0x39, 0x00, 0x01, 0x3C, 0x02, 0x77, 0x02, 0x63,\n  0x04, 0x63, 0x04, 0x77, 0x08, 0x3C, 0x0E, 0x06, 0x60, 0xCC, 0x19, 0x81,\n  0xE0, 0x18, 0x0F, 0x03, 0x36, 0xC2, 0xD8, 0x73, 0x06, 0x31, 0xE3, 0xC4,\n  0xFE, 0x13, 0x26, 0x6C, 0xCC, 0xCC, 0xC4, 0x66, 0x23, 0x10, 0x8C, 0x46,\n  0x63, 0x33, 0x33, 0x32, 0x66, 0x4C, 0x80, 0x25, 0x7E, 0xA5, 0x00, 0x30,\n  0xC3, 0x3F, 0x30, 0xC3, 0x0C, 0xD6, 0xF0, 0xC0, 0x08, 0x44, 0x21, 0x10,\n  0x84, 0x42, 0x11, 0x08, 0x00, 0x3C, 0x66, 0x42, 0xC3, 0xC3, 0xC3, 0xC3,\n  0xC3, 0xC3, 0xC3, 0x42, 0x66, 0x3C, 0x11, 0x3F, 0x33, 0x33, 0x33, 0x33,\n  0x30, 0x3E, 0x31, 0xB0, 0x78, 0x30, 0x18, 0x1C, 0x1C, 0x1C, 0x18, 0x18,\n  0x10, 0x08, 0x07, 0xF8, 0x3C, 0x66, 0xC3, 0xC3, 0x03, 0x06, 0x1C, 0x07,\n  0x03, 0xC3, 0xC3, 0x66, 0x3C, 0x0C, 0x18, 0x71, 0x62, 0xC9, 0xA3, 0x46,\n  0xFE, 0x18, 0x30, 0x60, 0xC0, 0x7F, 0x20, 0x10, 0x08, 0x08, 0x07, 0xF3,\n  0x8C, 0x03, 0x01, 0x80, 0xF0, 0x6C, 0x63, 0xE0, 0x1E, 0x31, 0x98, 0x78,\n  0x0C, 0x06, 0xF3, 0x8D, 0x83, 0xC1, 0xE0, 0xD0, 0x6C, 0x63, 0xE0, 0xFF,\n  0x03, 0x02, 0x06, 0x04, 0x0C, 0x08, 0x18, 0x18, 0x18, 0x10, 0x30, 0x30,\n  0x3E, 0x31, 0xB0, 0x78, 0x3C, 0x1B, 0x18, 0xF8, 0xC6, 0xC1, 0xE0, 0xF0,\n  0x6C, 0x63, 0xE0, 0x3C, 0x66, 0xC2, 0xC3, 0xC3, 0xC3, 0x67, 0x3B, 0x03,\n  0x03, 0xC2, 0x66, 0x3C, 0xC0, 0x00, 0x30, 0xC0, 0x00, 0x00, 0x64, 0xA0,\n  0x00, 0x81, 0xC7, 0x8E, 0x0C, 0x07, 0x80, 0x70, 0x0E, 0x01, 0x80, 0xFF,\n  0x80, 0x00, 0x1F, 0xF0, 0x00, 0x70, 0x0E, 0x01, 0xC0, 0x18, 0x38, 0x71,\n  0xC0, 0x80, 0x00, 0x3E, 0x31, 0xB0, 0x78, 0x30, 0x18, 0x18, 0x38, 0x18,\n  0x18, 0x0C, 0x00, 0x00, 0x01, 0x80, 0x03, 0xF0, 0x06, 0x0E, 0x06, 0x01,\n  0x86, 0x00, 0x66, 0x1D, 0xBB, 0x31, 0xCF, 0x18, 0xC7, 0x98, 0x63, 0xCC,\n  0x31, 0xE6, 0x11, 0xB3, 0x99, 0xCC, 0xF7, 0x86, 0x00, 0x01, 0x80, 0x00,\n  0x70, 0x40, 0x0F, 0xE0, 0x06, 0x00, 0xF0, 0x0F, 0x00, 0x90, 0x19, 0x81,\n  0x98, 0x10, 0x83, 0x0C, 0x3F, 0xC2, 0x04, 0x60, 0x66, 0x06, 0xC0, 0x30,\n  0xFF, 0x18, 0x33, 0x03, 0x60, 0x6C, 0x0D, 0x83, 0x3F, 0xC6, 0x06, 0xC0,\n  0x78, 0x0F, 0x01, 0xE0, 0x6F, 0xF8, 0x1F, 0x86, 0x19, 0x81, 0xA0, 0x3C,\n  0x01, 0x80, 0x30, 0x06, 0x00, 0xC0, 0x68, 0x0D, 0x83, 0x18, 0x61, 0xF0,\n  0xFF, 0x18, 0x33, 0x03, 0x60, 0x3C, 0x07, 0x80, 0xF0, 0x1E, 0x03, 0xC0,\n  0x78, 0x0F, 0x03, 0x60, 0xCF, 0xF0, 0xFF, 0xE0, 0x30, 0x18, 0x0C, 0x06,\n  0x03, 0xFD, 0x80, 0xC0, 0x60, 0x30, 0x18, 0x0F, 0xF8, 0xFF, 0xC0, 0xC0,\n  0xC0, 0xC0, 0xC0, 0xFE, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0x0F, 0x83,\n  0x0E, 0x60, 0x66, 0x03, 0xC0, 0x0C, 0x00, 0xC1, 0xFC, 0x03, 0xC0, 0x36,\n  0x03, 0x60, 0x73, 0x0F, 0x0F, 0x10, 0xC0, 0x78, 0x0F, 0x01, 0xE0, 0x3C,\n  0x07, 0x80, 0xFF, 0xFE, 0x03, 0xC0, 0x78, 0x0F, 0x01, 0xE0, 0x3C, 0x06,\n  0xFF, 0xFF, 0xFF, 0xC0, 0x06, 0x0C, 0x18, 0x30, 0x60, 0xC1, 0x83, 0x07,\n  0x8F, 0x1E, 0x27, 0x80, 0xC0, 0xD8, 0x33, 0x0C, 0x63, 0x0C, 0xC1, 0xB8,\n  0x3F, 0x07, 0x30, 0xC3, 0x18, 0x63, 0x06, 0x60, 0x6C, 0x0C, 0xC0, 0xC0,\n  0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xFF, 0xE0,\n  0x3F, 0x01, 0xFC, 0x1F, 0xE0, 0xFD, 0x05, 0xEC, 0x6F, 0x63, 0x79, 0x13,\n  0xCD, 0x9E, 0x6C, 0xF1, 0x47, 0x8E, 0x3C, 0x71, 0x80, 0xE0, 0x7C, 0x0F,\n  0xC1, 0xE8, 0x3D, 0x87, 0x98, 0xF1, 0x1E, 0x33, 0xC3, 0x78, 0x6F, 0x07,\n  0xE0, 0x7C, 0x0E, 0x0F, 0x81, 0x83, 0x18, 0x0C, 0xC0, 0x6C, 0x01, 0xE0,\n  0x0F, 0x00, 0x78, 0x03, 0xC0, 0x1B, 0x01, 0x98, 0x0C, 0x60, 0xC0, 0xF8,\n  0x00, 0xFF, 0x30, 0x6C, 0x0F, 0x03, 0xC0, 0xF0, 0x6F, 0xF3, 0x00, 0xC0,\n  0x30, 0x0C, 0x03, 0x00, 0xC0, 0x00, 0x0F, 0x81, 0x83, 0x18, 0x0C, 0xC0,\n  0x6C, 0x01, 0xE0, 0x0F, 0x00, 0x78, 0x03, 0xC0, 0x1B, 0x01, 0x98, 0x6C,\n  0x60, 0xC0, 0xFB, 0x00, 0x08, 0xFF, 0x8C, 0x0E, 0xC0, 0x6C, 0x06, 0xC0,\n  0x6C, 0x0C, 0xFF, 0x8C, 0x0E, 0xC0, 0x6C, 0x06, 0xC0, 0x6C, 0x06, 0xC0,\n  0x70, 0x3F, 0x18, 0x6C, 0x0F, 0x03, 0xC0, 0x1E, 0x01, 0xF0, 0x0E, 0x00,\n  0xF0, 0x3C, 0x0D, 0x86, 0x3F, 0x00, 0xFF, 0x86, 0x03, 0x01, 0x80, 0xC0,\n  0x60, 0x30, 0x18, 0x0C, 0x06, 0x03, 0x01, 0x80, 0xC0, 0xC0, 0x78, 0x0F,\n  0x01, 0xE0, 0x3C, 0x07, 0x80, 0xF0, 0x1E, 0x03, 0xC0, 0x78, 0x0F, 0x01,\n  0xB0, 0x61, 0xF0, 0xC0, 0x6C, 0x0D, 0x81, 0x10, 0x63, 0x0C, 0x61, 0x04,\n  0x60, 0xCC, 0x19, 0x01, 0x60, 0x3C, 0x07, 0x00, 0x60, 0xC1, 0x81, 0x30,\n  0xE1, 0x98, 0x70, 0xCC, 0x28, 0x66, 0x26, 0x21, 0x13, 0x30, 0xC8, 0x98,\n  0x6C, 0x4C, 0x14, 0x34, 0x0A, 0x1A, 0x07, 0x07, 0x03, 0x03, 0x80, 0x81,\n  0x80, 0x60, 0x63, 0x0C, 0x30, 0xC1, 0x98, 0x0F, 0x00, 0xE0, 0x06, 0x00,\n  0xF0, 0x19, 0x01, 0x98, 0x30, 0xC6, 0x0E, 0x60, 0x60, 0xC0, 0x36, 0x06,\n  0x30, 0xC3, 0x0C, 0x19, 0x81, 0xD8, 0x0F, 0x00, 0x60, 0x06, 0x00, 0x60,\n  0x06, 0x00, 0x60, 0x06, 0x00, 0xFF, 0xC0, 0x60, 0x30, 0x0C, 0x06, 0x03,\n  0x01, 0xC0, 0x60, 0x30, 0x18, 0x06, 0x03, 0x00, 0xFF, 0xC0, 0xFB, 0x6D,\n  0xB6, 0xDB, 0x6D, 0xB6, 0xE0, 0x84, 0x10, 0x84, 0x10, 0x84, 0x10, 0x84,\n  0x10, 0x80, 0xED, 0xB6, 0xDB, 0x6D, 0xB6, 0xDB, 0xE0, 0x30, 0x60, 0xA2,\n  0x44, 0xD8, 0xA1, 0x80, 0xFF, 0xC0, 0xC6, 0x30, 0x7E, 0x71, 0xB0, 0xC0,\n  0x60, 0xF3, 0xDB, 0x0D, 0x86, 0xC7, 0x3D, 0xC0, 0xC0, 0x60, 0x30, 0x1B,\n  0xCE, 0x36, 0x0F, 0x07, 0x83, 0xC1, 0xE0, 0xF0, 0x7C, 0x6D, 0xE0, 0x3C,\n  0x66, 0xC3, 0xC0, 0xC0, 0xC0, 0xC0, 0xC3, 0x66, 0x3C, 0x03, 0x03, 0x03,\n  0x3B, 0x67, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0x67, 0x3B, 0x3C, 0x66,\n  0xC3, 0xC3, 0xFF, 0xC0, 0xC0, 0xC3, 0x66, 0x3C, 0x36, 0x6F, 0x66, 0x66,\n  0x66, 0x66, 0x60, 0x3B, 0x67, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0x67,\n  0x3B, 0x03, 0x03, 0xC6, 0x7C, 0xC0, 0xC0, 0xC0, 0xDE, 0xE3, 0xC3, 0xC3,\n  0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xFF, 0xFF, 0xC0, 0x30, 0x03,\n  0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0xE0, 0xC0, 0x60, 0x30, 0x18, 0x4C,\n  0x46, 0x63, 0x61, 0xF0, 0xEC, 0x62, 0x31, 0x98, 0x6C, 0x30, 0xFF, 0xFF,\n  0xFF, 0xC0, 0xDE, 0xF7, 0x1C, 0xF0, 0xC7, 0x86, 0x3C, 0x31, 0xE1, 0x8F,\n  0x0C, 0x78, 0x63, 0xC3, 0x1E, 0x18, 0xC0, 0xDE, 0xE3, 0xC3, 0xC3, 0xC3,\n  0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0x3C, 0x66, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3,\n  0xC3, 0x66, 0x3C, 0xDE, 0x71, 0xB0, 0x78, 0x3C, 0x1E, 0x0F, 0x07, 0x83,\n  0xE3, 0x6F, 0x30, 0x18, 0x0C, 0x00, 0x3B, 0x67, 0xC3, 0xC3, 0xC3, 0xC3,\n  0xC3, 0xC3, 0x67, 0x3B, 0x03, 0x03, 0x03, 0xDF, 0x31, 0x8C, 0x63, 0x18,\n  0xC6, 0x00, 0x3E, 0xE3, 0xC0, 0xC0, 0xE0, 0x3C, 0x07, 0xC3, 0xE3, 0x7E,\n  0x66, 0xF6, 0x66, 0x66, 0x66, 0x67, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3,\n  0xC3, 0xC3, 0xC7, 0x7B, 0xC1, 0xA0, 0x98, 0xCC, 0x42, 0x21, 0xB0, 0xD0,\n  0x28, 0x1C, 0x0C, 0x00, 0xC6, 0x1E, 0x38, 0x91, 0xC4, 0xCA, 0x66, 0xD3,\n  0x16, 0xD0, 0xA6, 0x87, 0x1C, 0x38, 0xC0, 0xC6, 0x00, 0x43, 0x62, 0x36,\n  0x1C, 0x18, 0x1C, 0x3C, 0x26, 0x62, 0x43, 0xC1, 0x21, 0x98, 0xCC, 0x42,\n  0x61, 0xB0, 0xD0, 0x38, 0x1C, 0x0C, 0x06, 0x03, 0x01, 0x03, 0x00, 0xFE,\n  0x0C, 0x30, 0xC1, 0x86, 0x18, 0x20, 0xC1, 0xFC, 0x36, 0x66, 0x66, 0x6E,\n  0xCE, 0x66, 0x66, 0x66, 0x30, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xC6, 0x66,\n  0x66, 0x67, 0x37, 0x66, 0x66, 0x66, 0xC0, 0x61, 0x24, 0x38 };\n\nconst GFXglyph FreeSans9pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,   5,    0,    1 },   // 0x20 ' '\n  {     0,   2,  13,   6,    2,  -12 },   // 0x21 '!'\n  {     4,   5,   4,   6,    1,  -12 },   // 0x22 '\"'\n  {     7,  10,  12,  10,    0,  -11 },   // 0x23 '#'\n  {    22,   9,  16,  10,    1,  -13 },   // 0x24 '$'\n  {    40,  16,  13,  16,    1,  -12 },   // 0x25 '%'\n  {    66,  11,  13,  12,    1,  -12 },   // 0x26 '&'\n  {    84,   2,   4,   4,    1,  -12 },   // 0x27 '''\n  {    85,   4,  17,   6,    1,  -12 },   // 0x28 '('\n  {    94,   4,  17,   6,    1,  -12 },   // 0x29 ')'\n  {   103,   5,   5,   7,    1,  -12 },   // 0x2A '*'\n  {   107,   6,   8,  11,    3,   -7 },   // 0x2B '+'\n  {   113,   2,   4,   5,    2,    0 },   // 0x2C ','\n  {   114,   4,   1,   6,    1,   -4 },   // 0x2D '-'\n  {   115,   2,   1,   5,    1,    0 },   // 0x2E '.'\n  {   116,   5,  13,   5,    0,  -12 },   // 0x2F '/'\n  {   125,   8,  13,  10,    1,  -12 },   // 0x30 '0'\n  {   138,   4,  13,  10,    3,  -12 },   // 0x31 '1'\n  {   145,   9,  13,  10,    1,  -12 },   // 0x32 '2'\n  {   160,   8,  13,  10,    1,  -12 },   // 0x33 '3'\n  {   173,   7,  13,  10,    2,  -12 },   // 0x34 '4'\n  {   185,   9,  13,  10,    1,  -12 },   // 0x35 '5'\n  {   200,   9,  13,  10,    1,  -12 },   // 0x36 '6'\n  {   215,   8,  13,  10,    0,  -12 },   // 0x37 '7'\n  {   228,   9,  13,  10,    1,  -12 },   // 0x38 '8'\n  {   243,   8,  13,  10,    1,  -12 },   // 0x39 '9'\n  {   256,   2,  10,   5,    1,   -9 },   // 0x3A ':'\n  {   259,   3,  12,   5,    1,   -8 },   // 0x3B ';'\n  {   264,   9,   9,  11,    1,   -8 },   // 0x3C '<'\n  {   275,   9,   4,  11,    1,   -5 },   // 0x3D '='\n  {   280,   9,   9,  11,    1,   -8 },   // 0x3E '>'\n  {   291,   9,  13,  10,    1,  -12 },   // 0x3F '?'\n  {   306,  17,  16,  18,    1,  -12 },   // 0x40 '@'\n  {   340,  12,  13,  12,    0,  -12 },   // 0x41 'A'\n  {   360,  11,  13,  12,    1,  -12 },   // 0x42 'B'\n  {   378,  11,  13,  13,    1,  -12 },   // 0x43 'C'\n  {   396,  11,  13,  13,    1,  -12 },   // 0x44 'D'\n  {   414,   9,  13,  11,    1,  -12 },   // 0x45 'E'\n  {   429,   8,  13,  11,    1,  -12 },   // 0x46 'F'\n  {   442,  12,  13,  14,    1,  -12 },   // 0x47 'G'\n  {   462,  11,  13,  13,    1,  -12 },   // 0x48 'H'\n  {   480,   2,  13,   5,    2,  -12 },   // 0x49 'I'\n  {   484,   7,  13,  10,    1,  -12 },   // 0x4A 'J'\n  {   496,  11,  13,  12,    1,  -12 },   // 0x4B 'K'\n  {   514,   8,  13,  10,    1,  -12 },   // 0x4C 'L'\n  {   527,  13,  13,  15,    1,  -12 },   // 0x4D 'M'\n  {   549,  11,  13,  13,    1,  -12 },   // 0x4E 'N'\n  {   567,  13,  13,  14,    1,  -12 },   // 0x4F 'O'\n  {   589,  10,  13,  12,    1,  -12 },   // 0x50 'P'\n  {   606,  13,  14,  14,    1,  -12 },   // 0x51 'Q'\n  {   629,  12,  13,  13,    1,  -12 },   // 0x52 'R'\n  {   649,  10,  13,  12,    1,  -12 },   // 0x53 'S'\n  {   666,   9,  13,  11,    1,  -12 },   // 0x54 'T'\n  {   681,  11,  13,  13,    1,  -12 },   // 0x55 'U'\n  {   699,  11,  13,  12,    0,  -12 },   // 0x56 'V'\n  {   717,  17,  13,  17,    0,  -12 },   // 0x57 'W'\n  {   745,  12,  13,  12,    0,  -12 },   // 0x58 'X'\n  {   765,  12,  13,  12,    0,  -12 },   // 0x59 'Y'\n  {   785,  10,  13,  11,    1,  -12 },   // 0x5A 'Z'\n  {   802,   3,  17,   5,    1,  -12 },   // 0x5B '['\n  {   809,   5,  13,   5,    0,  -12 },   // 0x5C '\\'\n  {   818,   3,  17,   5,    0,  -12 },   // 0x5D ']'\n  {   825,   7,   7,   8,    1,  -12 },   // 0x5E '^'\n  {   832,  10,   1,  10,    0,    3 },   // 0x5F '_'\n  {   834,   4,   3,   5,    0,  -12 },   // 0x60 '`'\n  {   836,   9,  10,  10,    1,   -9 },   // 0x61 'a'\n  {   848,   9,  13,  10,    1,  -12 },   // 0x62 'b'\n  {   863,   8,  10,   9,    1,   -9 },   // 0x63 'c'\n  {   873,   8,  13,  10,    1,  -12 },   // 0x64 'd'\n  {   886,   8,  10,  10,    1,   -9 },   // 0x65 'e'\n  {   896,   4,  13,   5,    1,  -12 },   // 0x66 'f'\n  {   903,   8,  14,  10,    1,   -9 },   // 0x67 'g'\n  {   917,   8,  13,  10,    1,  -12 },   // 0x68 'h'\n  {   930,   2,  13,   4,    1,  -12 },   // 0x69 'i'\n  {   934,   4,  17,   4,    0,  -12 },   // 0x6A 'j'\n  {   943,   9,  13,   9,    1,  -12 },   // 0x6B 'k'\n  {   958,   2,  13,   4,    1,  -12 },   // 0x6C 'l'\n  {   962,  13,  10,  15,    1,   -9 },   // 0x6D 'm'\n  {   979,   8,  10,  10,    1,   -9 },   // 0x6E 'n'\n  {   989,   8,  10,  10,    1,   -9 },   // 0x6F 'o'\n  {   999,   9,  13,  10,    1,   -9 },   // 0x70 'p'\n  {  1014,   8,  13,  10,    1,   -9 },   // 0x71 'q'\n  {  1027,   5,  10,   6,    1,   -9 },   // 0x72 'r'\n  {  1034,   8,  10,   9,    1,   -9 },   // 0x73 's'\n  {  1044,   4,  12,   5,    1,  -11 },   // 0x74 't'\n  {  1050,   8,  10,  10,    1,   -9 },   // 0x75 'u'\n  {  1060,   9,  10,   9,    0,   -9 },   // 0x76 'v'\n  {  1072,  13,  10,  13,    0,   -9 },   // 0x77 'w'\n  {  1089,   8,  10,   9,    0,   -9 },   // 0x78 'x'\n  {  1099,   9,  14,   9,    0,   -9 },   // 0x79 'y'\n  {  1115,   7,  10,   9,    1,   -9 },   // 0x7A 'z'\n  {  1124,   4,  17,   6,    1,  -12 },   // 0x7B '{'\n  {  1133,   2,  17,   4,    2,  -12 },   // 0x7C '|'\n  {  1138,   4,  17,   6,    1,  -12 },   // 0x7D '}'\n  {  1147,   7,   3,   9,    1,   -7 } }; // 0x7E '~'\n\nconst GFXfont FreeSans9pt7b PROGMEM = {\n  (uint8_t  *)FreeSans9pt7bBitmaps,\n  (GFXglyph *)FreeSans9pt7bGlyphs,\n  0x20, 0x7E, 22 };\n\n// Approx. 1822 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeSansBold12pt7b.h",
    "content": "const uint8_t FreeSansBold12pt7bBitmaps[] PROGMEM = {\n  0xFF, 0xFF, 0xFF, 0xFF, 0x76, 0x66, 0x60, 0xFF, 0xF0, 0xF3, 0xFC, 0xFF,\n  0x3F, 0xCF, 0x61, 0x98, 0x60, 0x0E, 0x70, 0x73, 0x83, 0x18, 0xFF, 0xF7,\n  0xFF, 0xBF, 0xFC, 0x73, 0x83, 0x18, 0x18, 0xC7, 0xFF, 0xBF, 0xFD, 0xFF,\n  0xE3, 0x18, 0x39, 0xC1, 0xCE, 0x0E, 0x70, 0x02, 0x00, 0x7E, 0x0F, 0xF8,\n  0x7F, 0xE7, 0xAF, 0xB9, 0x3D, 0xC8, 0x0F, 0x40, 0x3F, 0x00, 0xFF, 0x00,\n  0xFC, 0x05, 0xFF, 0x27, 0xF9, 0x3F, 0xEB, 0xEF, 0xFE, 0x3F, 0xE0, 0x7C,\n  0x00, 0x80, 0x04, 0x00, 0x3C, 0x06, 0x0F, 0xC1, 0x81, 0xFC, 0x30, 0x73,\n  0x8C, 0x0C, 0x31, 0x81, 0xCE, 0x60, 0x1F, 0xCC, 0x03, 0xF3, 0x00, 0x3C,\n  0x67, 0x80, 0x19, 0xF8, 0x02, 0x7F, 0x80, 0xCE, 0x70, 0x11, 0x86, 0x06,\n  0x39, 0xC1, 0x87, 0xF8, 0x30, 0x7E, 0x0C, 0x07, 0x80, 0x07, 0x80, 0x1F,\n  0xC0, 0x3F, 0xE0, 0x3C, 0xE0, 0x3C, 0xE0, 0x3E, 0xE0, 0x0F, 0xC0, 0x07,\n  0x00, 0x3F, 0x8C, 0x7F, 0xCC, 0xF1, 0xFC, 0xF0, 0xF8, 0xF0, 0x78, 0xF8,\n  0xF8, 0x7F, 0xFC, 0x3F, 0xDE, 0x1F, 0x8E, 0xFF, 0xFF, 0x66, 0x0C, 0x73,\n  0x8E, 0x71, 0xC7, 0x38, 0xE3, 0x8E, 0x38, 0xE3, 0x8E, 0x1C, 0x71, 0xC3,\n  0x8E, 0x18, 0x70, 0xC3, 0x87, 0x1C, 0x38, 0xE3, 0x87, 0x1C, 0x71, 0xC7,\n  0x1C, 0x71, 0xCE, 0x38, 0xE7, 0x1C, 0x63, 0x80, 0x10, 0x23, 0x5F, 0xF3,\n  0x87, 0x1B, 0x14, 0x0E, 0x01, 0xC0, 0x38, 0x07, 0x0F, 0xFF, 0xFF, 0xFF,\n  0xF8, 0x70, 0x0E, 0x01, 0xC0, 0x38, 0x00, 0xFF, 0xF3, 0x36, 0xC0, 0xFF,\n  0xFF, 0xC0, 0xFF, 0xF0, 0x0C, 0x30, 0x86, 0x18, 0x61, 0x0C, 0x30, 0xC2,\n  0x18, 0x61, 0x84, 0x30, 0xC0, 0x1F, 0x83, 0xFC, 0x7F, 0xE7, 0x9E, 0xF0,\n  0xFF, 0x0F, 0xF0, 0xFF, 0x0F, 0xF0, 0xFF, 0x0F, 0xF0, 0xFF, 0x0F, 0xF0,\n  0xF7, 0x9E, 0x7F, 0xE3, 0xFC, 0x0F, 0x00, 0x06, 0x1C, 0x7F, 0xFF, 0xE3,\n  0xC7, 0x8F, 0x1E, 0x3C, 0x78, 0xF1, 0xE3, 0xC7, 0x8F, 0x1E, 0x1F, 0x83,\n  0xFC, 0x7F, 0xEF, 0x9F, 0xF0, 0xFF, 0x0F, 0x00, 0xF0, 0x0F, 0x01, 0xE0,\n  0x3C, 0x0F, 0x81, 0xE0, 0x3C, 0x03, 0x80, 0x7F, 0xF7, 0xFF, 0x7F, 0xF0,\n  0x1F, 0x07, 0xFC, 0xFF, 0xEF, 0x1E, 0xF1, 0xE0, 0x1E, 0x03, 0xC0, 0x78,\n  0x07, 0xC0, 0x1E, 0x00, 0xF0, 0x0F, 0xF0, 0xFF, 0x1F, 0x7F, 0xE7, 0xFC,\n  0x1F, 0x80, 0x03, 0xC0, 0xF8, 0x1F, 0x07, 0xE1, 0xBC, 0x27, 0x8C, 0xF3,\n  0x1E, 0x63, 0xD8, 0x7B, 0xFF, 0xFF, 0xFF, 0xFE, 0x07, 0x80, 0xF0, 0x1E,\n  0x03, 0xC0, 0x3F, 0xE7, 0xFE, 0x7F, 0xE7, 0x00, 0x60, 0x06, 0xF8, 0x7F,\n  0xCF, 0xFE, 0xF1, 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0x00, 0xFE, 0x1E, 0xFF,\n  0xE7, 0xFC, 0x3F, 0x00, 0x0F, 0x83, 0xFC, 0x7F, 0xE7, 0x9F, 0xF0, 0x0F,\n  0x78, 0xFF, 0xCF, 0xFE, 0xF9, 0xFF, 0x0F, 0xF0, 0xFF, 0x0F, 0xF0, 0xF7,\n  0x9F, 0x7F, 0xE3, 0xFC, 0x0F, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, 0x80, 0xE0,\n  0x1C, 0x07, 0x01, 0xE0, 0x38, 0x0F, 0x01, 0xC0, 0x78, 0x0F, 0x01, 0xE0,\n  0x38, 0x0F, 0x01, 0xE0, 0x3C, 0x00, 0x0F, 0x03, 0xFC, 0x7F, 0xC7, 0x9E,\n  0x70, 0xE7, 0x0E, 0x39, 0xC1, 0xF8, 0x3F, 0xC7, 0x9E, 0xF0, 0xFF, 0x0F,\n  0xF0, 0xFF, 0x9F, 0x7F, 0xE3, 0xFC, 0x1F, 0x80, 0x1F, 0x03, 0xFC, 0x7F,\n  0xEF, 0x9E, 0xF0, 0xEF, 0x0F, 0xF0, 0xFF, 0x0F, 0xF9, 0xF7, 0xFF, 0x3F,\n  0xF1, 0xEF, 0x00, 0xEF, 0x1E, 0x7F, 0xE7, 0xFC, 0x1F, 0x00, 0xFF, 0xF0,\n  0x00, 0x00, 0x0F, 0xFF, 0xFF, 0xF0, 0x00, 0x00, 0x0F, 0xFF, 0x11, 0x6C,\n  0x00, 0x10, 0x07, 0x03, 0xF1, 0xFC, 0x7E, 0x0F, 0x80, 0xE0, 0x0F, 0xC0,\n  0x3F, 0x80, 0x7F, 0x00, 0xF0, 0x03, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0x00,\n  0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0x00, 0x0E, 0x00, 0xFC,\n  0x07, 0xF0, 0x0F, 0xE0, 0x1F, 0x00, 0xF0, 0x7F, 0x1F, 0x8F, 0xE0, 0xF0,\n  0x08, 0x00, 0x1F, 0x07, 0xFC, 0x7F, 0xEF, 0x9F, 0xF0, 0xFF, 0x0F, 0x00,\n  0xF0, 0x0F, 0x01, 0xE0, 0x3C, 0x07, 0x80, 0xF0, 0x0E, 0x00, 0xE0, 0x00,\n  0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x00, 0xFE, 0x00, 0x1F, 0xFC, 0x03, 0xC0,\n  0xF0, 0x38, 0x01, 0xC3, 0x80, 0x07, 0x18, 0x3D, 0x99, 0x87, 0xEC, 0x6C,\n  0x71, 0xC3, 0xC3, 0x06, 0x1E, 0x18, 0x30, 0xF1, 0x81, 0x87, 0x8C, 0x18,\n  0x7C, 0x60, 0xC3, 0x63, 0x8E, 0x3B, 0x8F, 0xDF, 0x8C, 0x3C, 0xF0, 0x70,\n  0x00, 0x01, 0xC0, 0x00, 0x07, 0x80, 0x80, 0x1F, 0xFE, 0x00, 0x1F, 0xC0,\n  0x00, 0x03, 0xE0, 0x03, 0xE0, 0x03, 0xE0, 0x07, 0xF0, 0x07, 0xF0, 0x07,\n  0x70, 0x0F, 0x78, 0x0E, 0x78, 0x0E, 0x38, 0x1E, 0x3C, 0x1C, 0x3C, 0x3F,\n  0xFC, 0x3F, 0xFE, 0x3F, 0xFE, 0x78, 0x0E, 0x78, 0x0F, 0x70, 0x0F, 0xF0,\n  0x07, 0xFF, 0xC3, 0xFF, 0xCF, 0xFF, 0x3C, 0x3E, 0xF0, 0x7B, 0xC1, 0xEF,\n  0x0F, 0xBF, 0xFC, 0xFF, 0xE3, 0xFF, 0xCF, 0x07, 0xBC, 0x0F, 0xF0, 0x3F,\n  0xC0, 0xFF, 0x07, 0xFF, 0xFE, 0xFF, 0xFB, 0xFF, 0x80, 0x07, 0xE0, 0x1F,\n  0xF8, 0x3F, 0xFC, 0x7C, 0x3E, 0x78, 0x1F, 0xF8, 0x0F, 0xF0, 0x00, 0xF0,\n  0x00, 0xF0, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0xF8, 0x0F, 0x78,\n  0x1F, 0x7C, 0x3E, 0x3F, 0xFE, 0x1F, 0xFC, 0x07, 0xF0, 0xFF, 0xE1, 0xFF,\n  0xE3, 0xFF, 0xE7, 0x83, 0xEF, 0x03, 0xDE, 0x07, 0xFC, 0x07, 0xF8, 0x0F,\n  0xF0, 0x1F, 0xE0, 0x3F, 0xC0, 0x7F, 0x80, 0xFF, 0x03, 0xFE, 0x07, 0xBC,\n  0x1F, 0x7F, 0xFC, 0xFF, 0xF1, 0xFF, 0x80, 0xFF, 0xF7, 0xFF, 0xBF, 0xFD,\n  0xE0, 0x0F, 0x00, 0x78, 0x03, 0xC0, 0x1F, 0xFC, 0xFF, 0xE7, 0xFF, 0x3C,\n  0x01, 0xE0, 0x0F, 0x00, 0x78, 0x03, 0xC0, 0x1F, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x0F,\n  0xFE, 0xFF, 0xEF, 0xFE, 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x0F,\n  0x00, 0xF0, 0x0F, 0x00, 0x03, 0xF0, 0x0F, 0xFC, 0x3F, 0xFE, 0x3E, 0x1F,\n  0x78, 0x07, 0x78, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0xF0, 0x7F, 0xF0, 0x7F,\n  0xF0, 0x7F, 0xF0, 0x07, 0x78, 0x07, 0x7C, 0x0F, 0x3E, 0x1F, 0x3F, 0xFB,\n  0x0F, 0xFB, 0x03, 0xE3, 0xF0, 0x3F, 0xC0, 0xFF, 0x03, 0xFC, 0x0F, 0xF0,\n  0x3F, 0xC0, 0xFF, 0x03, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0xFC,\n  0x0F, 0xF0, 0x3F, 0xC0, 0xFF, 0x03, 0xFC, 0x0F, 0xF0, 0x3F, 0xC0, 0xF0,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0xE0, 0x3C,\n  0x07, 0x80, 0xF0, 0x1E, 0x03, 0xC0, 0x78, 0x0F, 0x01, 0xE0, 0x3C, 0x07,\n  0xF8, 0xFF, 0x1F, 0xE3, 0xFC, 0x7B, 0xFE, 0x7F, 0xC3, 0xE0, 0xF0, 0x3E,\n  0xF0, 0x3C, 0xF0, 0x78, 0xF0, 0xF0, 0xF1, 0xE0, 0xF3, 0xC0, 0xF7, 0x80,\n  0xFF, 0x00, 0xFF, 0x80, 0xFF, 0x80, 0xFB, 0xC0, 0xF1, 0xE0, 0xF0, 0xF0,\n  0xF0, 0xF0, 0xF0, 0x78, 0xF0, 0x3C, 0xF0, 0x3E, 0xF0, 0x1E, 0xF0, 0x1E,\n  0x03, 0xC0, 0x78, 0x0F, 0x01, 0xE0, 0x3C, 0x07, 0x80, 0xF0, 0x1E, 0x03,\n  0xC0, 0x78, 0x0F, 0x01, 0xE0, 0x3C, 0x07, 0xFF, 0xFF, 0xFF, 0xFC, 0xF8,\n  0x1F, 0xFE, 0x0F, 0xFF, 0x0F, 0xFF, 0x87, 0xFF, 0xC3, 0xFF, 0xE1, 0xFF,\n  0xF9, 0xFF, 0xFC, 0xEF, 0xFE, 0x77, 0xFB, 0x3B, 0xFD, 0xDD, 0xFE, 0xFC,\n  0xFF, 0x7E, 0x7F, 0x9F, 0x3F, 0xCF, 0x9F, 0xE7, 0x8F, 0xF3, 0xC7, 0xF8,\n  0xE3, 0xC0, 0xF0, 0x1F, 0xF0, 0x3F, 0xF0, 0x7F, 0xE0, 0xFF, 0xE1, 0xFF,\n  0xC3, 0xFD, 0xC7, 0xFB, 0x8F, 0xF3, 0x9F, 0xE7, 0x3F, 0xC7, 0x7F, 0x8F,\n  0xFF, 0x0F, 0xFE, 0x1F, 0xFC, 0x1F, 0xF8, 0x1F, 0xF0, 0x3F, 0xE0, 0x3C,\n  0x03, 0xE0, 0x0F, 0xFC, 0x0F, 0xFF, 0x87, 0xC7, 0xC7, 0x80, 0xF3, 0xC0,\n  0x7B, 0xC0, 0x1F, 0xE0, 0x0F, 0xF0, 0x07, 0xF8, 0x03, 0xFC, 0x01, 0xFE,\n  0x00, 0xF7, 0x80, 0xF3, 0xC0, 0x78, 0xF0, 0xF8, 0x7F, 0xFC, 0x1F, 0xFC,\n  0x03, 0xF8, 0x00, 0xFF, 0xE3, 0xFF, 0xEF, 0xFF, 0xBC, 0x1F, 0xF0, 0x3F,\n  0xC0, 0xFF, 0x03, 0xFC, 0x1F, 0xFF, 0xFB, 0xFF, 0xCF, 0xFE, 0x3C, 0x00,\n  0xF0, 0x03, 0xC0, 0x0F, 0x00, 0x3C, 0x00, 0xF0, 0x03, 0xC0, 0x00, 0x03,\n  0xE0, 0x0F, 0xFC, 0x0F, 0xFF, 0x87, 0xC7, 0xC7, 0x80, 0xF3, 0xC0, 0x7B,\n  0xC0, 0x1F, 0xE0, 0x0F, 0xF0, 0x07, 0xF8, 0x03, 0xFC, 0x01, 0xFE, 0x04,\n  0xF7, 0x87, 0xF3, 0xC3, 0xF8, 0xF0, 0xF8, 0x7F, 0xFC, 0x1F, 0xFF, 0x83,\n  0xF1, 0x80, 0x00, 0x00, 0xFF, 0xF8, 0xFF, 0xFC, 0xFF, 0xFC, 0xF0, 0x3E,\n  0xF0, 0x1E, 0xF0, 0x1E, 0xF0, 0x1E, 0xF0, 0x3C, 0xFF, 0xF8, 0xFF, 0xF0,\n  0xFF, 0xF8, 0xF0, 0x3C, 0xF0, 0x3C, 0xF0, 0x3C, 0xF0, 0x3C, 0xF0, 0x3C,\n  0xF0, 0x3C, 0xF0, 0x1F, 0x0F, 0xC0, 0x7F, 0xE1, 0xFF, 0xE7, 0xC3, 0xEF,\n  0x03, 0xDE, 0x00, 0x3C, 0x00, 0x7F, 0x00, 0x7F, 0xF0, 0x3F, 0xF8, 0x0F,\n  0xF8, 0x01, 0xF0, 0x01, 0xFE, 0x03, 0xDE, 0x0F, 0xBF, 0xFE, 0x3F, 0xF8,\n  0x1F, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0xF0, 0x0F, 0x00, 0xF0, 0x0F,\n  0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x0F,\n  0x00, 0xF0, 0x0F, 0x00, 0xF0, 0xF0, 0x3F, 0xC0, 0xFF, 0x03, 0xFC, 0x0F,\n  0xF0, 0x3F, 0xC0, 0xFF, 0x03, 0xFC, 0x0F, 0xF0, 0x3F, 0xC0, 0xFF, 0x03,\n  0xFC, 0x0F, 0xF0, 0x3F, 0xC0, 0xF7, 0x87, 0x9F, 0xFE, 0x3F, 0xF0, 0x3F,\n  0x00, 0x70, 0x0E, 0xF0, 0x3D, 0xE0, 0x79, 0xC0, 0xE3, 0x81, 0xC7, 0x87,\n  0x87, 0x0E, 0x0E, 0x1C, 0x1E, 0x78, 0x1C, 0xE0, 0x39, 0xC0, 0x73, 0x80,\n  0x7E, 0x00, 0xFC, 0x01, 0xF8, 0x01, 0xE0, 0x03, 0xC0, 0x07, 0x80, 0x70,\n  0x38, 0x1C, 0xE0, 0xF0, 0x79, 0xE1, 0xF0, 0xF3, 0xC3, 0xE1, 0xE3, 0x87,\n  0xC3, 0x87, 0x0F, 0x87, 0x0E, 0x3B, 0x9E, 0x1E, 0x77, 0x38, 0x1C, 0xEE,\n  0x70, 0x39, 0xCC, 0xE0, 0x73, 0x99, 0xC0, 0x6E, 0x3F, 0x00, 0xFC, 0x7E,\n  0x01, 0xF8, 0xFC, 0x03, 0xF0, 0xF8, 0x03, 0xE1, 0xE0, 0x07, 0x83, 0xC0,\n  0x0F, 0x07, 0x80, 0xF0, 0x3C, 0xF0, 0xF9, 0xE1, 0xE1, 0xE7, 0x83, 0xCF,\n  0x03, 0xFC, 0x03, 0xF0, 0x07, 0xE0, 0x07, 0x80, 0x0F, 0x00, 0x3F, 0x00,\n  0xFF, 0x01, 0xFE, 0x07, 0x9E, 0x0F, 0x1E, 0x3C, 0x3C, 0xF8, 0x3D, 0xE0,\n  0x78, 0xF0, 0x1E, 0x78, 0x1E, 0x78, 0x3C, 0x3C, 0x3C, 0x3C, 0x78, 0x1E,\n  0x78, 0x0E, 0x70, 0x0F, 0xF0, 0x07, 0xE0, 0x07, 0xE0, 0x03, 0xC0, 0x03,\n  0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03,\n  0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0x01, 0xF0, 0x0F, 0x00, 0xF0, 0x0F,\n  0x00, 0xF8, 0x07, 0x80, 0x78, 0x07, 0x80, 0x7C, 0x03, 0xC0, 0x3C, 0x03,\n  0xC0, 0x1F, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFC, 0xF3, 0xCF,\n  0x3C, 0xF3, 0xCF, 0x3C, 0xF3, 0xCF, 0x3C, 0xF3, 0xCF, 0x3C, 0xFF, 0xFF,\n  0xC0, 0xC1, 0x81, 0x03, 0x06, 0x04, 0x0C, 0x18, 0x10, 0x30, 0x60, 0x40,\n  0xC1, 0x81, 0x03, 0x06, 0xFF, 0xFF, 0xCF, 0x3C, 0xF3, 0xCF, 0x3C, 0xF3,\n  0xCF, 0x3C, 0xF3, 0xCF, 0x3C, 0xF3, 0xCF, 0xFF, 0xFF, 0xC0, 0x0F, 0x00,\n  0xF0, 0x0F, 0x01, 0xF8, 0x1B, 0x83, 0x9C, 0x39, 0xC3, 0x0C, 0x70, 0xE7,\n  0x0E, 0xE0, 0x70, 0xFF, 0xFF, 0xFF, 0xFC, 0xE6, 0x30, 0x1F, 0x83, 0xFF,\n  0x1F, 0xFD, 0xE1, 0xE0, 0x0F, 0x03, 0xF9, 0xFF, 0xDF, 0x1E, 0xF0, 0xF7,\n  0x8F, 0xBF, 0xFC, 0xFF, 0xE3, 0xCF, 0x80, 0xF0, 0x07, 0x80, 0x3C, 0x01,\n  0xE0, 0x0F, 0x00, 0x7B, 0xC3, 0xFF, 0x9F, 0xFE, 0xF8, 0xF7, 0x83, 0xFC,\n  0x1F, 0xE0, 0xFF, 0x07, 0xF8, 0x3F, 0xE3, 0xDF, 0xFE, 0xFF, 0xE7, 0xBE,\n  0x00, 0x0F, 0x83, 0xFE, 0x7F, 0xF7, 0x8F, 0xF0, 0x7F, 0x00, 0xF0, 0x0F,\n  0x00, 0xF0, 0x77, 0x8F, 0x7F, 0xF3, 0xFE, 0x0F, 0x80, 0x00, 0x78, 0x03,\n  0xC0, 0x1E, 0x00, 0xF0, 0x07, 0x8F, 0xBC, 0xFF, 0xEF, 0xFF, 0x78, 0xFF,\n  0x83, 0xFC, 0x1F, 0xE0, 0xFF, 0x07, 0xF8, 0x3D, 0xE3, 0xEF, 0xFF, 0x3F,\n  0xF8, 0xFB, 0xC0, 0x1F, 0x81, 0xFE, 0x1F, 0xF9, 0xF1, 0xCF, 0x07, 0x7F,\n  0xFB, 0xFF, 0xDE, 0x00, 0xF0, 0x03, 0xC3, 0x9F, 0xFC, 0x7F, 0xC0, 0xF8,\n  0x00, 0x3E, 0xFD, 0xFB, 0xC7, 0x9F, 0xBF, 0x3C, 0x78, 0xF1, 0xE3, 0xC7,\n  0x8F, 0x1E, 0x3C, 0x78, 0xF0, 0x1E, 0x79, 0xFB, 0xDF, 0xFE, 0xF1, 0xFF,\n  0x07, 0xF8, 0x3F, 0xC1, 0xFE, 0x0F, 0xF0, 0x7F, 0xC7, 0xDF, 0xFE, 0x7F,\n  0xF1, 0xF7, 0x80, 0x3C, 0x01, 0xFF, 0x1E, 0x7F, 0xF0, 0xFE, 0x00, 0xF0,\n  0x0F, 0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0x7C, 0xFF, 0xEF, 0xFF, 0xF9,\n  0xFF, 0x0F, 0xF0, 0xFF, 0x0F, 0xF0, 0xFF, 0x0F, 0xF0, 0xFF, 0x0F, 0xF0,\n  0xFF, 0x0F, 0xFF, 0xF0, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x3C,\n  0xF3, 0xC0, 0x00, 0xF3, 0xCF, 0x3C, 0xF3, 0xCF, 0x3C, 0xF3, 0xCF, 0x3C,\n  0xF3, 0xCF, 0xFF, 0xFF, 0x80, 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0x00, 0xF0,\n  0x0F, 0x0F, 0xF1, 0xEF, 0x3C, 0xF7, 0x8F, 0xF0, 0xFF, 0x0F, 0xF8, 0xFF,\n  0x8F, 0x3C, 0xF1, 0xCF, 0x1E, 0xF0, 0xEF, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF7, 0x8F, 0x9F, 0xFB, 0xFB, 0xFF, 0xFF,\n  0xFC, 0xF8, 0xFF, 0x1E, 0x1F, 0xE3, 0xC3, 0xFC, 0x78, 0x7F, 0x8F, 0x0F,\n  0xF1, 0xE1, 0xFE, 0x3C, 0x3F, 0xC7, 0x87, 0xF8, 0xF0, 0xFF, 0x1E, 0x1E,\n  0xF7, 0xCF, 0xFE, 0xFF, 0xFF, 0x9F, 0xF0, 0xFF, 0x0F, 0xF0, 0xFF, 0x0F,\n  0xF0, 0xFF, 0x0F, 0xF0, 0xFF, 0x0F, 0xF0, 0xF0, 0x0F, 0x81, 0xFF, 0x1F,\n  0xFC, 0xF1, 0xEF, 0x07, 0xF8, 0x3F, 0xC1, 0xFE, 0x0F, 0xF0, 0x7B, 0xC7,\n  0x9F, 0xFC, 0x7F, 0xC0, 0xF8, 0x00, 0xF7, 0xC7, 0xFF, 0x3F, 0xFD, 0xF1,\n  0xEF, 0x07, 0xF8, 0x3F, 0xC1, 0xFE, 0x0F, 0xF0, 0x7F, 0xC7, 0xBF, 0xFD,\n  0xFF, 0xCF, 0x78, 0x78, 0x03, 0xC0, 0x1E, 0x00, 0xF0, 0x07, 0x80, 0x00,\n  0x0F, 0x79, 0xFF, 0xDF, 0xFE, 0xF1, 0xFF, 0x07, 0xF8, 0x3F, 0xC1, 0xFE,\n  0x0F, 0xF0, 0x7B, 0xC7, 0xDF, 0xFE, 0x7F, 0xF1, 0xF7, 0x80, 0x3C, 0x01,\n  0xE0, 0x0F, 0x00, 0x78, 0x03, 0xC0, 0xF3, 0xF7, 0xFF, 0xF8, 0xF0, 0xF0,\n  0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0x1F, 0x87, 0xFC, 0xFF, 0xEF,\n  0x0F, 0xF8, 0x0F, 0xF0, 0x7F, 0xE0, 0xFF, 0x01, 0xFF, 0x0F, 0xFF, 0xE7,\n  0xFE, 0x1F, 0x80, 0x79, 0xE7, 0xBF, 0xFD, 0xE7, 0x9E, 0x79, 0xE7, 0x9E,\n  0x7D, 0xF3, 0xC0, 0xF0, 0xFF, 0x0F, 0xF0, 0xFF, 0x0F, 0xF0, 0xFF, 0x0F,\n  0xF0, 0xFF, 0x0F, 0xF0, 0xFF, 0x1F, 0xFF, 0xF7, 0xFF, 0x3E, 0xF0, 0xF0,\n  0x7B, 0x83, 0x9E, 0x1C, 0xF1, 0xE3, 0x8E, 0x1C, 0x70, 0x77, 0x83, 0xB8,\n  0x1D, 0xC0, 0x7E, 0x03, 0xE0, 0x1F, 0x00, 0x70, 0x00, 0xF0, 0xE1, 0xDC,\n  0x78, 0x77, 0x1F, 0x3D, 0xE7, 0xCF, 0x79, 0xB3, 0x8E, 0x6C, 0xE3, 0xBB,\n  0x38, 0xEE, 0xFC, 0x1F, 0x3F, 0x07, 0xC7, 0xC1, 0xF1, 0xF0, 0x7C, 0x78,\n  0x0E, 0x1E, 0x00, 0x78, 0xF3, 0xC7, 0x8F, 0x78, 0x3B, 0x81, 0xFC, 0x07,\n  0xC0, 0x1E, 0x01, 0xF0, 0x1F, 0xC0, 0xEF, 0x0F, 0x78, 0xF1, 0xE7, 0x87,\n  0x00, 0xF0, 0x7B, 0x83, 0x9E, 0x1C, 0x71, 0xE3, 0x8E, 0x1E, 0x70, 0x73,\n  0x83, 0xB8, 0x1F, 0xC0, 0x7E, 0x03, 0xE0, 0x0F, 0x00, 0x70, 0x03, 0x80,\n  0x3C, 0x07, 0xC0, 0x3E, 0x01, 0xE0, 0x00, 0xFF, 0xFF, 0xFF, 0xFC, 0x0F,\n  0x07, 0x83, 0xC1, 0xE0, 0xF0, 0x78, 0x3C, 0x0F, 0xFF, 0xFF, 0xFF, 0xC0,\n  0x1C, 0xF3, 0xCE, 0x38, 0xE3, 0x8E, 0x38, 0xE3, 0xBC, 0xF0, 0xE3, 0x8E,\n  0x38, 0xE3, 0x8E, 0x3C, 0xF1, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0,\n  0xE3, 0x8F, 0x1C, 0x71, 0xC7, 0x1C, 0x71, 0xC7, 0x0F, 0x3D, 0xC7, 0x1C,\n  0x71, 0xC7, 0x1C, 0xF3, 0xCE, 0x00, 0x78, 0x0F, 0xE0, 0xCF, 0x30, 0x7F,\n  0x01, 0xE0 };\n\nconst GFXglyph FreeSansBold12pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,   7,    0,    1 },   // 0x20 ' '\n  {     0,   4,  17,   8,    3,  -16 },   // 0x21 '!'\n  {     9,  10,   6,  11,    1,  -17 },   // 0x22 '\"'\n  {    17,  13,  16,  13,    0,  -15 },   // 0x23 '#'\n  {    43,  13,  20,  13,    0,  -17 },   // 0x24 '$'\n  {    76,  19,  17,  21,    1,  -16 },   // 0x25 '%'\n  {   117,  16,  17,  17,    1,  -16 },   // 0x26 '&'\n  {   151,   4,   6,   6,    1,  -17 },   // 0x27 '''\n  {   154,   6,  22,   8,    1,  -17 },   // 0x28 '('\n  {   171,   6,  22,   8,    1,  -17 },   // 0x29 ')'\n  {   188,   7,   8,   9,    1,  -17 },   // 0x2A '*'\n  {   195,  11,  11,  14,    2,  -10 },   // 0x2B '+'\n  {   211,   4,   7,   6,    1,   -2 },   // 0x2C ','\n  {   215,   6,   3,   8,    1,   -7 },   // 0x2D '-'\n  {   218,   4,   3,   6,    1,   -2 },   // 0x2E '.'\n  {   220,   6,  17,   7,    0,  -16 },   // 0x2F '/'\n  {   233,  12,  17,  13,    1,  -16 },   // 0x30 '0'\n  {   259,   7,  17,  14,    3,  -16 },   // 0x31 '1'\n  {   274,  12,  17,  13,    1,  -16 },   // 0x32 '2'\n  {   300,  12,  17,  13,    1,  -16 },   // 0x33 '3'\n  {   326,  11,  17,  13,    1,  -16 },   // 0x34 '4'\n  {   350,  12,  17,  13,    1,  -16 },   // 0x35 '5'\n  {   376,  12,  17,  13,    1,  -16 },   // 0x36 '6'\n  {   402,  11,  17,  13,    1,  -16 },   // 0x37 '7'\n  {   426,  12,  17,  13,    1,  -16 },   // 0x38 '8'\n  {   452,  12,  17,  13,    1,  -16 },   // 0x39 '9'\n  {   478,   4,  12,   6,    1,  -11 },   // 0x3A ':'\n  {   484,   4,  16,   6,    1,  -11 },   // 0x3B ';'\n  {   492,  12,  12,  14,    1,  -11 },   // 0x3C '<'\n  {   510,  12,   9,  14,    1,   -9 },   // 0x3D '='\n  {   524,  12,  12,  14,    1,  -11 },   // 0x3E '>'\n  {   542,  12,  18,  15,    2,  -17 },   // 0x3F '?'\n  {   569,  21,  21,  23,    1,  -17 },   // 0x40 '@'\n  {   625,  16,  18,  17,    0,  -17 },   // 0x41 'A'\n  {   661,  14,  18,  17,    2,  -17 },   // 0x42 'B'\n  {   693,  16,  18,  17,    1,  -17 },   // 0x43 'C'\n  {   729,  15,  18,  17,    2,  -17 },   // 0x44 'D'\n  {   763,  13,  18,  16,    2,  -17 },   // 0x45 'E'\n  {   793,  12,  18,  15,    2,  -17 },   // 0x46 'F'\n  {   820,  16,  18,  18,    1,  -17 },   // 0x47 'G'\n  {   856,  14,  18,  18,    2,  -17 },   // 0x48 'H'\n  {   888,   4,  18,   7,    2,  -17 },   // 0x49 'I'\n  {   897,  11,  18,  14,    1,  -17 },   // 0x4A 'J'\n  {   922,  16,  18,  17,    2,  -17 },   // 0x4B 'K'\n  {   958,  11,  18,  15,    2,  -17 },   // 0x4C 'L'\n  {   983,  17,  18,  21,    2,  -17 },   // 0x4D 'M'\n  {  1022,  15,  18,  18,    2,  -17 },   // 0x4E 'N'\n  {  1056,  17,  18,  19,    1,  -17 },   // 0x4F 'O'\n  {  1095,  14,  18,  16,    2,  -17 },   // 0x50 'P'\n  {  1127,  17,  19,  19,    1,  -17 },   // 0x51 'Q'\n  {  1168,  16,  18,  17,    2,  -17 },   // 0x52 'R'\n  {  1204,  15,  18,  16,    1,  -17 },   // 0x53 'S'\n  {  1238,  12,  18,  15,    2,  -17 },   // 0x54 'T'\n  {  1265,  14,  18,  18,    2,  -17 },   // 0x55 'U'\n  {  1297,  15,  18,  16,    0,  -17 },   // 0x56 'V'\n  {  1331,  23,  18,  23,    0,  -17 },   // 0x57 'W'\n  {  1383,  15,  18,  16,    1,  -17 },   // 0x58 'X'\n  {  1417,  16,  18,  15,    0,  -17 },   // 0x59 'Y'\n  {  1453,  13,  18,  15,    1,  -17 },   // 0x5A 'Z'\n  {  1483,   6,  23,   8,    2,  -17 },   // 0x5B '['\n  {  1501,   7,  17,   7,    0,  -16 },   // 0x5C '\\'\n  {  1516,   6,  23,   8,    0,  -17 },   // 0x5D ']'\n  {  1534,  12,  11,  14,    1,  -16 },   // 0x5E '^'\n  {  1551,  15,   2,  13,   -1,    4 },   // 0x5F '_'\n  {  1555,   4,   3,   6,    0,  -17 },   // 0x60 '`'\n  {  1557,  13,  13,  14,    1,  -12 },   // 0x61 'a'\n  {  1579,  13,  18,  15,    2,  -17 },   // 0x62 'b'\n  {  1609,  12,  13,  13,    1,  -12 },   // 0x63 'c'\n  {  1629,  13,  18,  15,    1,  -17 },   // 0x64 'd'\n  {  1659,  13,  13,  14,    1,  -12 },   // 0x65 'e'\n  {  1681,   7,  18,   8,    1,  -17 },   // 0x66 'f'\n  {  1697,  13,  18,  15,    1,  -12 },   // 0x67 'g'\n  {  1727,  12,  18,  14,    2,  -17 },   // 0x68 'h'\n  {  1754,   4,  18,   7,    2,  -17 },   // 0x69 'i'\n  {  1763,   6,  23,   7,    0,  -17 },   // 0x6A 'j'\n  {  1781,  12,  18,  14,    2,  -17 },   // 0x6B 'k'\n  {  1808,   4,  18,   6,    2,  -17 },   // 0x6C 'l'\n  {  1817,  19,  13,  21,    2,  -12 },   // 0x6D 'm'\n  {  1848,  12,  13,  15,    2,  -12 },   // 0x6E 'n'\n  {  1868,  13,  13,  15,    1,  -12 },   // 0x6F 'o'\n  {  1890,  13,  18,  15,    2,  -12 },   // 0x70 'p'\n  {  1920,  13,  18,  15,    1,  -12 },   // 0x71 'q'\n  {  1950,   8,  13,   9,    2,  -12 },   // 0x72 'r'\n  {  1963,  12,  13,  13,    1,  -12 },   // 0x73 's'\n  {  1983,   6,  15,   8,    1,  -14 },   // 0x74 't'\n  {  1995,  12,  13,  15,    2,  -12 },   // 0x75 'u'\n  {  2015,  13,  13,  13,    0,  -12 },   // 0x76 'v'\n  {  2037,  18,  13,  19,    0,  -12 },   // 0x77 'w'\n  {  2067,  13,  13,  13,    0,  -12 },   // 0x78 'x'\n  {  2089,  13,  18,  13,    0,  -12 },   // 0x79 'y'\n  {  2119,  10,  13,  12,    1,  -12 },   // 0x7A 'z'\n  {  2136,   6,  23,   9,    1,  -17 },   // 0x7B '{'\n  {  2154,   2,  22,   7,    2,  -17 },   // 0x7C '|'\n  {  2160,   6,  23,   9,    3,  -17 },   // 0x7D '}'\n  {  2178,  12,   5,  12,    0,   -7 } }; // 0x7E '~'\n\nconst GFXfont FreeSansBold12pt7b PROGMEM = {\n  (uint8_t  *)FreeSansBold12pt7bBitmaps,\n  (GFXglyph *)FreeSansBold12pt7bGlyphs,\n  0x20, 0x7E, 29 };\n\n// Approx. 2858 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeSansBold18pt7b.h",
    "content": "const uint8_t FreeSansBold18pt7bBitmaps[] PROGMEM = {\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xE7, 0x39, 0xCE, 0x73, 0x80,\n  0x0F, 0xFF, 0xFF, 0xF8, 0xF8, 0xFF, 0xC7, 0xFE, 0x3F, 0xF1, 0xFF, 0x8F,\n  0xFC, 0x7D, 0xC1, 0xCE, 0x0E, 0x70, 0x70, 0x03, 0xC3, 0x80, 0x3C, 0x78,\n  0x03, 0xC7, 0x80, 0x38, 0x78, 0x07, 0x87, 0x07, 0xFF, 0xFF, 0x7F, 0xFF,\n  0xF7, 0xFF, 0xFF, 0x7F, 0xFF, 0xF0, 0xF0, 0xE0, 0x0F, 0x0E, 0x00, 0xF1,\n  0xE0, 0x0F, 0x1E, 0x00, 0xE1, 0xE0, 0xFF, 0xFF, 0xCF, 0xFF, 0xFC, 0xFF,\n  0xFF, 0xCF, 0xFF, 0xFC, 0x1C, 0x3C, 0x03, 0xC3, 0x80, 0x3C, 0x78, 0x03,\n  0xC7, 0x80, 0x38, 0x78, 0x03, 0x87, 0x80, 0x00, 0x60, 0x00, 0x7F, 0x80,\n  0x3F, 0xFC, 0x0F, 0xFF, 0xC3, 0xFF, 0xFC, 0xFC, 0xDF, 0x9F, 0x19, 0xFB,\n  0xC3, 0x1F, 0x78, 0x63, 0xEF, 0x8C, 0x01, 0xFD, 0x80, 0x1F, 0xF0, 0x01,\n  0xFF, 0xC0, 0x1F, 0xFE, 0x00, 0x7F, 0xE0, 0x03, 0xFE, 0x00, 0x67, 0xE0,\n  0x0C, 0x7F, 0xE1, 0x8F, 0xFC, 0x31, 0xFF, 0xC6, 0x3E, 0xFC, 0xDF, 0x9F,\n  0xFF, 0xF1, 0xFF, 0xFC, 0x0F, 0xFF, 0x00, 0x7F, 0x80, 0x01, 0x80, 0x00,\n  0x30, 0x00, 0x06, 0x00, 0x0F, 0x00, 0x1C, 0x01, 0xFE, 0x00, 0xE0, 0x1F,\n  0xF8, 0x0E, 0x00, 0xFF, 0xC0, 0x70, 0x0F, 0x0F, 0x07, 0x00, 0x70, 0x38,\n  0x38, 0x03, 0x81, 0xC3, 0x80, 0x1C, 0x0E, 0x3C, 0x00, 0xF0, 0xF1, 0xC0,\n  0x03, 0xFF, 0x1C, 0x00, 0x1F, 0xF8, 0xE0, 0x00, 0x7F, 0x8E, 0x00, 0x00,\n  0xF0, 0x70, 0xF8, 0x00, 0x07, 0x1F, 0xF0, 0x00, 0x39, 0xFF, 0xC0, 0x03,\n  0x8F, 0xFE, 0x00, 0x1C, 0xF0, 0x78, 0x01, 0xC7, 0x01, 0xC0, 0x0C, 0x38,\n  0x0E, 0x00, 0xE1, 0xC0, 0x70, 0x06, 0x0F, 0x07, 0x80, 0x70, 0x3F, 0xF8,\n  0x07, 0x01, 0xFF, 0xC0, 0x38, 0x07, 0xFC, 0x03, 0x80, 0x0F, 0x80, 0x01,\n  0xF0, 0x00, 0x1F, 0xE0, 0x00, 0xFF, 0xC0, 0x03, 0xFF, 0x80, 0x1F, 0x1E,\n  0x00, 0x7C, 0x78, 0x01, 0xF1, 0xE0, 0x07, 0xE7, 0x80, 0x0F, 0xBC, 0x00,\n  0x1F, 0xE0, 0x00, 0x3F, 0x00, 0x01, 0xF8, 0x00, 0x1F, 0xF0, 0xF0, 0xFF,\n  0xE3, 0xC7, 0xE7, 0xCF, 0x3F, 0x0F, 0xF8, 0xF8, 0x3F, 0xE3, 0xE0, 0x7F,\n  0x8F, 0x80, 0xFC, 0x3F, 0x03, 0xF0, 0x7E, 0x3F, 0xE1, 0xFF, 0xFF, 0x83,\n  0xFF, 0xFF, 0x07, 0xFE, 0x7E, 0x07, 0xF0, 0xFC, 0xFF, 0xFF, 0xFF, 0xFD,\n  0xCE, 0x70, 0x07, 0x87, 0x83, 0xC3, 0xC1, 0xE1, 0xE0, 0xF0, 0x78, 0x78,\n  0x3C, 0x1E, 0x1E, 0x0F, 0x07, 0x83, 0xC1, 0xE0, 0xF0, 0x78, 0x3C, 0x1E,\n  0x0F, 0x03, 0x81, 0xE0, 0xF0, 0x78, 0x1E, 0x0F, 0x03, 0x81, 0xE0, 0x70,\n  0x3C, 0x0E, 0x07, 0x80, 0xF0, 0x38, 0x1E, 0x07, 0x83, 0xC0, 0xF0, 0x78,\n  0x3C, 0x0F, 0x07, 0x83, 0xC0, 0xF0, 0x78, 0x3C, 0x1E, 0x0F, 0x07, 0x83,\n  0xC1, 0xE0, 0xF0, 0x78, 0x78, 0x3C, 0x1E, 0x0F, 0x0F, 0x07, 0x87, 0x83,\n  0xC1, 0xC1, 0xE0, 0xE0, 0xF0, 0x00, 0x06, 0x00, 0x60, 0x06, 0x07, 0x6E,\n  0x7F, 0xE3, 0xFC, 0x0F, 0x01, 0xF8, 0x1F, 0x83, 0x9C, 0x10, 0x80, 0x03,\n  0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0xC0, 0x03, 0xC0, 0x03,\n  0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0xFF, 0xFF, 0xFF, 0x8C, 0x63,\n  0x37, 0xB0, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0xFF, 0xFF, 0xFF, 0x80, 0x01,\n  0x81, 0xC0, 0xC0, 0x60, 0x70, 0x38, 0x18, 0x0C, 0x0E, 0x06, 0x03, 0x01,\n  0x81, 0xC0, 0xC0, 0x60, 0x30, 0x38, 0x18, 0x0C, 0x0E, 0x07, 0x03, 0x01,\n  0x81, 0xC0, 0xC0, 0x00, 0x07, 0xF0, 0x0F, 0xFE, 0x0F, 0xFF, 0x87, 0xFF,\n  0xC7, 0xE3, 0xF3, 0xE0, 0xF9, 0xF0, 0x7D, 0xF0, 0x1F, 0xF8, 0x0F, 0xFC,\n  0x07, 0xFE, 0x03, 0xFF, 0x01, 0xFF, 0x80, 0xFF, 0xC0, 0x7F, 0xE0, 0x3F,\n  0xF0, 0x1F, 0xF8, 0x0F, 0xFC, 0x07, 0xDF, 0x07, 0xCF, 0x83, 0xE7, 0xE3,\n  0xF1, 0xFF, 0xF0, 0xFF, 0xF8, 0x3F, 0xF8, 0x07, 0xF0, 0x00, 0x01, 0xC0,\n  0xF0, 0x3C, 0x1F, 0x1F, 0xFF, 0xFF, 0xFF, 0xFF, 0x07, 0xC1, 0xF0, 0x7C,\n  0x1F, 0x07, 0xC1, 0xF0, 0x7C, 0x1F, 0x07, 0xC1, 0xF0, 0x7C, 0x1F, 0x07,\n  0xC1, 0xF0, 0x7C, 0x1F, 0x07, 0xC0, 0x07, 0xF0, 0x0F, 0xFE, 0x0F, 0xFF,\n  0x8F, 0xFF, 0xE7, 0xE3, 0xF7, 0xE0, 0xFF, 0xE0, 0x3F, 0xF0, 0x1F, 0xF8,\n  0x0F, 0x80, 0x07, 0xC0, 0x07, 0xE0, 0x03, 0xE0, 0x03, 0xF0, 0x03, 0xF0,\n  0x07, 0xF0, 0x07, 0xF0, 0x07, 0xE0, 0x07, 0xE0, 0x07, 0xC0, 0x07, 0xC0,\n  0x03, 0xE0, 0x03, 0xFF, 0xFD, 0xFF, 0xFE, 0xFF, 0xFF, 0x7F, 0xFF, 0x80,\n  0x07, 0xE0, 0x0F, 0xFC, 0x0F, 0xFF, 0x0F, 0xFF, 0xCF, 0xC3, 0xF7, 0xC0,\n  0xFB, 0xE0, 0x7D, 0xF0, 0x3E, 0x00, 0x1F, 0x00, 0x1F, 0x00, 0x0F, 0x80,\n  0x3F, 0x80, 0x1F, 0xC0, 0x0F, 0xF0, 0x00, 0xFC, 0x00, 0x3F, 0x00, 0x0F,\n  0xFC, 0x07, 0xFE, 0x03, 0xFF, 0x83, 0xF7, 0xC3, 0xF3, 0xFF, 0xF8, 0xFF,\n  0xF8, 0x3F, 0xF8, 0x07, 0xF0, 0x00, 0x00, 0xFC, 0x00, 0xFC, 0x01, 0xFC,\n  0x01, 0xFC, 0x03, 0xFC, 0x07, 0x7C, 0x07, 0x7C, 0x0E, 0x7C, 0x0E, 0x7C,\n  0x1C, 0x7C, 0x18, 0x7C, 0x38, 0x7C, 0x70, 0x7C, 0x60, 0x7C, 0xE0, 0x7C,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x7C, 0x00, 0x7C,\n  0x00, 0x7C, 0x00, 0x7C, 0x00, 0x7C, 0x00, 0x7C, 0x1F, 0xFF, 0x0F, 0xFF,\n  0x8F, 0xFF, 0xC7, 0xFF, 0xE3, 0xC0, 0x01, 0xE0, 0x00, 0xE0, 0x00, 0x70,\n  0x00, 0x79, 0xF0, 0x3F, 0xFE, 0x1F, 0xFF, 0x8F, 0xFF, 0xE7, 0xC3, 0xF0,\n  0x00, 0xFC, 0x00, 0x3E, 0x00, 0x1F, 0x00, 0x0F, 0x80, 0x07, 0xFE, 0x03,\n  0xFF, 0x03, 0xFF, 0xC3, 0xF3, 0xFF, 0xF1, 0xFF, 0xF8, 0x3F, 0xF0, 0x07,\n  0xE0, 0x00, 0x03, 0xF8, 0x03, 0xFF, 0x81, 0xFF, 0xF0, 0xFF, 0xFE, 0x3E,\n  0x1F, 0x9F, 0x03, 0xE7, 0xC0, 0x03, 0xE0, 0x00, 0xF8, 0xF8, 0x3E, 0xFF,\n  0x8F, 0xFF, 0xF3, 0xFF, 0xFE, 0xFE, 0x1F, 0xBF, 0x03, 0xFF, 0x80, 0x7F,\n  0xE0, 0x1F, 0xF8, 0x07, 0xFE, 0x01, 0xF7, 0x80, 0x7D, 0xF0, 0x3E, 0x7E,\n  0x1F, 0x8F, 0xFF, 0xC1, 0xFF, 0xF0, 0x3F, 0xF0, 0x03, 0xF0, 0x00, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0x00, 0xF0, 0x00, 0xF8,\n  0x00, 0xF8, 0x00, 0x78, 0x00, 0x7C, 0x00, 0x3C, 0x00, 0x3E, 0x00, 0x1E,\n  0x00, 0x1F, 0x00, 0x0F, 0x00, 0x0F, 0x80, 0x07, 0xC0, 0x03, 0xC0, 0x03,\n  0xE0, 0x01, 0xF0, 0x00, 0xF8, 0x00, 0x78, 0x00, 0x7C, 0x00, 0x3E, 0x00,\n  0x1F, 0x00, 0x0F, 0x80, 0x00, 0x07, 0xE0, 0x07, 0xFC, 0x0F, 0xFF, 0x07,\n  0xFF, 0xC7, 0xC3, 0xF3, 0xC0, 0xF9, 0xE0, 0x3C, 0xF0, 0x1E, 0x78, 0x1F,\n  0x1E, 0x1F, 0x07, 0xFF, 0x01, 0xFF, 0x03, 0xFF, 0xE3, 0xF1, 0xF9, 0xF0,\n  0x7D, 0xF0, 0x1F, 0xF8, 0x0F, 0xFC, 0x07, 0xFE, 0x03, 0xFF, 0x83, 0xF7,\n  0xC3, 0xF3, 0xFF, 0xF8, 0xFF, 0xF8, 0x3F, 0xF8, 0x07, 0xF0, 0x00, 0x07,\n  0xE0, 0x0F, 0xFC, 0x0F, 0xFF, 0x0F, 0xFF, 0xC7, 0xE3, 0xF7, 0xE0, 0xFB,\n  0xE0, 0x3D, 0xF0, 0x1F, 0xF8, 0x0F, 0xFC, 0x07, 0xFE, 0x03, 0xFF, 0x83,\n  0xF7, 0xE3, 0xFB, 0xFF, 0xFC, 0xFF, 0xFE, 0x3F, 0xDF, 0x07, 0xCF, 0x80,\n  0x07, 0x80, 0x03, 0xDF, 0x03, 0xE7, 0xC3, 0xE3, 0xFF, 0xF0, 0xFF, 0xF0,\n  0x3F, 0xF0, 0x07, 0xE0, 0x00, 0xFF, 0xFF, 0xFF, 0x80, 0x00, 0x00, 0x00,\n  0x00, 0x7F, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0x80, 0x00, 0x00, 0x00,\n  0x00, 0x7F, 0xFF, 0xFF, 0xC6, 0x33, 0x9B, 0xD8, 0x00, 0x00, 0xC0, 0x00,\n  0xF0, 0x01, 0xFC, 0x03, 0xFF, 0x03, 0xFF, 0x07, 0xFE, 0x0F, 0xFC, 0x03,\n  0xF8, 0x00, 0xF0, 0x00, 0x3F, 0x80, 0x0F, 0xFC, 0x00, 0x7F, 0xE0, 0x07,\n  0xFF, 0x00, 0x3F, 0xF0, 0x01, 0xFC, 0x00, 0x1F, 0x00, 0x00, 0xC0, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xF0, 0xC0, 0x00, 0x3C, 0x00, 0x0F, 0xE0, 0x03, 0xFF, 0x00, 0x3F, 0xF0,\n  0x01, 0xFF, 0x80, 0x0F, 0xFC, 0x00, 0x7F, 0x00, 0x03, 0xC0, 0x07, 0xF0,\n  0x0F, 0xFC, 0x1F, 0xF8, 0x3F, 0xF8, 0x3F, 0xF0, 0x0F, 0xE0, 0x03, 0xC0,\n  0x00, 0xC0, 0x00, 0x00, 0x07, 0xF0, 0x07, 0xFF, 0x03, 0xFF, 0xF1, 0xFF,\n  0xFC, 0x7E, 0x3F, 0xBF, 0x03, 0xFF, 0x80, 0x7F, 0xE0, 0x1F, 0xF8, 0x07,\n  0xC0, 0x03, 0xF0, 0x01, 0xFC, 0x00, 0xFE, 0x00, 0x7F, 0x00, 0x3F, 0x80,\n  0x1F, 0xC0, 0x07, 0xC0, 0x03, 0xE0, 0x00, 0xF0, 0x00, 0x3C, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x3E, 0x00, 0x0F, 0x80, 0x03, 0xE0,\n  0x00, 0xF8, 0x00, 0x00, 0x07, 0xFC, 0x00, 0x00, 0x3F, 0xFF, 0x00, 0x00,\n  0xFF, 0xFF, 0xC0, 0x01, 0xF8, 0x07, 0xF0, 0x03, 0xE0, 0x01, 0xF8, 0x07,\n  0x80, 0x00, 0x7C, 0x0F, 0x00, 0x00, 0x3C, 0x1E, 0x03, 0xE3, 0x9E, 0x3C,\n  0x0F, 0xF7, 0x8E, 0x38, 0x1F, 0xFF, 0x0E, 0x78, 0x3E, 0x1F, 0x07, 0x70,\n  0x38, 0x0F, 0x07, 0x70, 0x78, 0x0F, 0x07, 0xE0, 0x70, 0x0E, 0x07, 0xE0,\n  0x70, 0x0E, 0x07, 0xE0, 0xE0, 0x0E, 0x07, 0xE0, 0xE0, 0x1E, 0x0F, 0xE0,\n  0xE0, 0x1C, 0x0E, 0xE0, 0xE0, 0x3C, 0x1E, 0xE0, 0xF0, 0x3C, 0x3C, 0xF0,\n  0xF0, 0xFC, 0x7C, 0x70, 0x7F, 0xFF, 0xF8, 0x78, 0x3F, 0xCF, 0xF0, 0x3C,\n  0x1F, 0x07, 0xC0, 0x3E, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x0F,\n  0xC0, 0x01, 0x00, 0x07, 0xF0, 0x0F, 0x00, 0x03, 0xFF, 0xFF, 0x00, 0x00,\n  0xFF, 0xFF, 0x00, 0x00, 0x1F, 0xF8, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x7F,\n  0x00, 0x00, 0x7F, 0x00, 0x00, 0xFF, 0x00, 0x00, 0xFF, 0x80, 0x01, 0xFF,\n  0x80, 0x01, 0xFF, 0x80, 0x01, 0xF7, 0xC0, 0x03, 0xE7, 0xC0, 0x03, 0xE7,\n  0xC0, 0x03, 0xE3, 0xE0, 0x07, 0xC3, 0xE0, 0x07, 0xC3, 0xE0, 0x07, 0xC1,\n  0xF0, 0x0F, 0x81, 0xF0, 0x0F, 0x81, 0xF0, 0x0F, 0xFF, 0xF8, 0x1F, 0xFF,\n  0xF8, 0x1F, 0xFF, 0xFC, 0x1F, 0xFF, 0xFC, 0x3E, 0x00, 0x7C, 0x3E, 0x00,\n  0x7E, 0x3E, 0x00, 0x3E, 0x7C, 0x00, 0x3E, 0x7C, 0x00, 0x3F, 0x7C, 0x00,\n  0x1F, 0xFF, 0xFC, 0x0F, 0xFF, 0xF0, 0xFF, 0xFF, 0x8F, 0xFF, 0xFC, 0xF8,\n  0x07, 0xEF, 0x80, 0x3E, 0xF8, 0x03, 0xEF, 0x80, 0x3E, 0xF8, 0x03, 0xEF,\n  0x80, 0x3E, 0xF8, 0x07, 0xCF, 0xFF, 0xF8, 0xFF, 0xFF, 0x0F, 0xFF, 0xF8,\n  0xFF, 0xFF, 0xCF, 0x80, 0x7E, 0xF8, 0x01, 0xEF, 0x80, 0x1F, 0xF8, 0x01,\n  0xFF, 0x80, 0x1F, 0xF8, 0x01, 0xFF, 0x80, 0x3E, 0xFF, 0xFF, 0xEF, 0xFF,\n  0xFC, 0xFF, 0xFF, 0x8F, 0xFF, 0xE0, 0x00, 0xFF, 0x00, 0x07, 0xFF, 0x80,\n  0x3F, 0xFF, 0xC0, 0xFF, 0xFF, 0xC3, 0xF8, 0x1F, 0x87, 0xE0, 0x1F, 0x9F,\n  0x80, 0x1F, 0x3E, 0x00, 0x1F, 0x7C, 0x00, 0x3F, 0xF0, 0x00, 0x03, 0xE0,\n  0x00, 0x07, 0xC0, 0x00, 0x0F, 0x80, 0x00, 0x1F, 0x00, 0x00, 0x3E, 0x00,\n  0x00, 0x7C, 0x00, 0x00, 0xF8, 0x00, 0x00, 0xF8, 0x00, 0x7D, 0xF0, 0x00,\n  0xFB, 0xF0, 0x03, 0xF3, 0xF0, 0x0F, 0xC7, 0xF0, 0x3F, 0x87, 0xFF, 0xFE,\n  0x07, 0xFF, 0xF8, 0x03, 0xFF, 0xC0, 0x01, 0xFE, 0x00, 0xFF, 0xFC, 0x07,\n  0xFF, 0xF8, 0x3F, 0xFF, 0xE1, 0xFF, 0xFF, 0x8F, 0x80, 0xFE, 0x7C, 0x01,\n  0xF3, 0xE0, 0x07, 0xDF, 0x00, 0x3E, 0xF8, 0x01, 0xF7, 0xC0, 0x07, 0xFE,\n  0x00, 0x3F, 0xF0, 0x01, 0xFF, 0x80, 0x0F, 0xFC, 0x00, 0x7F, 0xE0, 0x03,\n  0xFF, 0x00, 0x1F, 0xF8, 0x00, 0xFF, 0xC0, 0x0F, 0xFE, 0x00, 0x7D, 0xF0,\n  0x03, 0xEF, 0x80, 0x3E, 0x7C, 0x07, 0xF3, 0xFF, 0xFF, 0x1F, 0xFF, 0xF0,\n  0xFF, 0xFF, 0x07, 0xFF, 0xE0, 0x00, 0xFF, 0xFF, 0xDF, 0xFF, 0xFB, 0xFF,\n  0xFF, 0x7F, 0xFF, 0xEF, 0x80, 0x01, 0xF0, 0x00, 0x3E, 0x00, 0x07, 0xC0,\n  0x00, 0xF8, 0x00, 0x1F, 0x00, 0x03, 0xE0, 0x00, 0x7F, 0xFF, 0xCF, 0xFF,\n  0xF9, 0xFF, 0xFF, 0x3F, 0xFF, 0xE7, 0xC0, 0x00, 0xF8, 0x00, 0x1F, 0x00,\n  0x03, 0xE0, 0x00, 0x7C, 0x00, 0x0F, 0x80, 0x01, 0xF0, 0x00, 0x3F, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x80, 0x07, 0xC0, 0x03, 0xE0, 0x01, 0xF0,\n  0x00, 0xF8, 0x00, 0x7C, 0x00, 0x3E, 0x00, 0x1F, 0xFF, 0xEF, 0xFF, 0xF7,\n  0xFF, 0xFB, 0xFF, 0xFD, 0xF0, 0x00, 0xF8, 0x00, 0x7C, 0x00, 0x3E, 0x00,\n  0x1F, 0x00, 0x0F, 0x80, 0x07, 0xC0, 0x03, 0xE0, 0x01, 0xF0, 0x00, 0xF8,\n  0x00, 0x7C, 0x00, 0x00, 0x00, 0x7F, 0x80, 0x03, 0xFF, 0xE0, 0x07, 0xFF,\n  0xF8, 0x0F, 0xFF, 0xFC, 0x1F, 0xC0, 0xFE, 0x3F, 0x00, 0x7E, 0x7E, 0x00,\n  0x3F, 0x7C, 0x00, 0x1F, 0x7C, 0x00, 0x00, 0xF8, 0x00, 0x00, 0xF8, 0x00,\n  0x00, 0xF8, 0x00, 0x00, 0xF8, 0x03, 0xFF, 0xF8, 0x03, 0xFF, 0xF8, 0x03,\n  0xFF, 0xF8, 0x03, 0xFF, 0xFC, 0x00, 0x0F, 0x7C, 0x00, 0x1F, 0x7C, 0x00,\n  0x1F, 0x7E, 0x00, 0x3F, 0x3F, 0x00, 0x7F, 0x1F, 0xC1, 0xFF, 0x0F, 0xFF,\n  0xFF, 0x07, 0xFF, 0xE7, 0x03, 0xFF, 0xC7, 0x00, 0xFF, 0x07, 0xF8, 0x01,\n  0xFF, 0x80, 0x1F, 0xF8, 0x01, 0xFF, 0x80, 0x1F, 0xF8, 0x01, 0xFF, 0x80,\n  0x1F, 0xF8, 0x01, 0xFF, 0x80, 0x1F, 0xF8, 0x01, 0xFF, 0x80, 0x1F, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF8, 0x01, 0xFF,\n  0x80, 0x1F, 0xF8, 0x01, 0xFF, 0x80, 0x1F, 0xF8, 0x01, 0xFF, 0x80, 0x1F,\n  0xF8, 0x01, 0xFF, 0x80, 0x1F, 0xF8, 0x01, 0xFF, 0x80, 0x1F, 0xF8, 0x01,\n  0xFF, 0x80, 0x1F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0x00, 0x1F, 0x00, 0x1F,\n  0x00, 0x1F, 0x00, 0x1F, 0x00, 0x1F, 0x00, 0x1F, 0x00, 0x1F, 0x00, 0x1F,\n  0x00, 0x1F, 0x00, 0x1F, 0x00, 0x1F, 0x00, 0x1F, 0x00, 0x1F, 0x00, 0x1F,\n  0x00, 0x1F, 0x00, 0x1F, 0xF8, 0x1F, 0xF8, 0x1F, 0xF8, 0x1F, 0xF8, 0x1F,\n  0xF8, 0x1F, 0xFC, 0x3F, 0x7F, 0xFE, 0x3F, 0xFC, 0x1F, 0xF8, 0x07, 0xE0,\n  0xF8, 0x01, 0xFB, 0xE0, 0x0F, 0xCF, 0x80, 0x7E, 0x3E, 0x03, 0xF0, 0xF8,\n  0x1F, 0x83, 0xE0, 0xFC, 0x0F, 0x87, 0xE0, 0x3E, 0x3F, 0x00, 0xF8, 0xF8,\n  0x03, 0xE7, 0xE0, 0x0F, 0xBF, 0x00, 0x3F, 0xF8, 0x00, 0xFF, 0xF0, 0x03,\n  0xFF, 0xE0, 0x0F, 0xFF, 0x80, 0x3F, 0xBF, 0x00, 0xFC, 0x7E, 0x03, 0xE0,\n  0xFC, 0x0F, 0x81, 0xF8, 0x3E, 0x07, 0xE0, 0xF8, 0x0F, 0xC3, 0xE0, 0x1F,\n  0x8F, 0x80, 0x7F, 0x3E, 0x00, 0xFC, 0xF8, 0x01, 0xFB, 0xE0, 0x03, 0xF0,\n  0xF8, 0x00, 0x7C, 0x00, 0x3E, 0x00, 0x1F, 0x00, 0x0F, 0x80, 0x07, 0xC0,\n  0x03, 0xE0, 0x01, 0xF0, 0x00, 0xF8, 0x00, 0x7C, 0x00, 0x3E, 0x00, 0x1F,\n  0x00, 0x0F, 0x80, 0x07, 0xC0, 0x03, 0xE0, 0x01, 0xF0, 0x00, 0xF8, 0x00,\n  0x7C, 0x00, 0x3E, 0x00, 0x1F, 0x00, 0x0F, 0x80, 0x07, 0xC0, 0x03, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0x00, 0xFF, 0xFF,\n  0x00, 0xFF, 0xFF, 0x00, 0xFF, 0xFF, 0x01, 0xFF, 0xFF, 0x81, 0xFF, 0xFF,\n  0x81, 0xFF, 0xFF, 0x81, 0xFF, 0xFF, 0x81, 0xFF, 0xFB, 0xC3, 0xDF, 0xFB,\n  0xC3, 0xDF, 0xFB, 0xC3, 0xDF, 0xFB, 0xC3, 0xDF, 0xF9, 0xC7, 0xDF, 0xF9,\n  0xE7, 0x9F, 0xF9, 0xE7, 0x9F, 0xF9, 0xE7, 0x9F, 0xF9, 0xE7, 0x9F, 0xF8,\n  0xFF, 0x1F, 0xF8, 0xFF, 0x1F, 0xF8, 0xFF, 0x1F, 0xF8, 0xFF, 0x1F, 0xF8,\n  0x7F, 0x1F, 0xF8, 0x7E, 0x1F, 0xF8, 0x7E, 0x1F, 0xF8, 0x7E, 0x1F, 0xF8,\n  0x3E, 0x1F, 0xF8, 0x01, 0xFF, 0xC0, 0x1F, 0xFE, 0x01, 0xFF, 0xE0, 0x1F,\n  0xFF, 0x01, 0xFF, 0xF0, 0x1F, 0xFF, 0x81, 0xFF, 0xF8, 0x1F, 0xFF, 0xC1,\n  0xFF, 0xBC, 0x1F, 0xFB, 0xE1, 0xFF, 0x9F, 0x1F, 0xF9, 0xF1, 0xFF, 0x8F,\n  0x9F, 0xF8, 0x79, 0xFF, 0x87, 0xDF, 0xF8, 0x3D, 0xFF, 0x83, 0xFF, 0xF8,\n  0x1F, 0xFF, 0x81, 0xFF, 0xF8, 0x0F, 0xFF, 0x80, 0xFF, 0xF8, 0x07, 0xFF,\n  0x80, 0x3F, 0xF8, 0x03, 0xFF, 0x80, 0x1F, 0x00, 0x7F, 0x00, 0x01, 0xFF,\n  0xF0, 0x01, 0xFF, 0xFC, 0x03, 0xFF, 0xFF, 0x01, 0xFC, 0x1F, 0xC1, 0xF8,\n  0x03, 0xF1, 0xF8, 0x00, 0xFC, 0xF8, 0x00, 0x3E, 0x7C, 0x00, 0x1F, 0x7C,\n  0x00, 0x07, 0xFE, 0x00, 0x03, 0xFF, 0x00, 0x01, 0xFF, 0x80, 0x00, 0xFF,\n  0xC0, 0x00, 0x7F, 0xE0, 0x00, 0x3F, 0xF0, 0x00, 0x1F, 0xF8, 0x00, 0x0F,\n  0xBE, 0x00, 0x0F, 0x9F, 0x00, 0x07, 0xCF, 0xC0, 0x07, 0xE3, 0xF0, 0x07,\n  0xE0, 0xFE, 0x0F, 0xE0, 0x7F, 0xFF, 0xE0, 0x0F, 0xFF, 0xE0, 0x03, 0xFF,\n  0xE0, 0x00, 0x3F, 0x80, 0x00, 0xFF, 0xFC, 0x1F, 0xFF, 0xE3, 0xFF, 0xFE,\n  0x7F, 0xFF, 0xEF, 0x80, 0xFF, 0xF0, 0x0F, 0xFE, 0x00, 0xFF, 0xC0, 0x1F,\n  0xF8, 0x03, 0xFF, 0x00, 0x7F, 0xE0, 0x1F, 0xFC, 0x07, 0xEF, 0xFF, 0xFD,\n  0xFF, 0xFF, 0x3F, 0xFF, 0xC7, 0xFF, 0xE0, 0xF8, 0x00, 0x1F, 0x00, 0x03,\n  0xE0, 0x00, 0x7C, 0x00, 0x0F, 0x80, 0x01, 0xF0, 0x00, 0x3E, 0x00, 0x07,\n  0xC0, 0x00, 0xF8, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x01, 0xFF,\n  0xF0, 0x01, 0xFF, 0xFC, 0x03, 0xFF, 0xFF, 0x01, 0xFC, 0x1F, 0xC1, 0xF8,\n  0x03, 0xF1, 0xF8, 0x00, 0xFC, 0xF8, 0x00, 0x3E, 0x7C, 0x00, 0x1F, 0x7C,\n  0x00, 0x07, 0xFE, 0x00, 0x03, 0xFF, 0x00, 0x01, 0xFF, 0x80, 0x00, 0xFF,\n  0xC0, 0x00, 0x7F, 0xE0, 0x00, 0x3F, 0xF0, 0x00, 0x1F, 0xF8, 0x01, 0x0F,\n  0xBE, 0x01, 0xCF, 0x9F, 0x01, 0xFF, 0xCF, 0xC0, 0x7F, 0xE3, 0xF0, 0x1F,\n  0xE0, 0xFE, 0x0F, 0xF0, 0x7F, 0xFF, 0xF8, 0x0F, 0xFF, 0xFE, 0x03, 0xFF,\n  0xEF, 0x80, 0x3F, 0xC3, 0x80, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0x07, 0xFF,\n  0xFE, 0x3F, 0xFF, 0xF9, 0xFF, 0xFF, 0xCF, 0x80, 0x3F, 0x7C, 0x00, 0xFB,\n  0xE0, 0x07, 0xDF, 0x00, 0x3E, 0xF8, 0x01, 0xF7, 0xC0, 0x0F, 0x3E, 0x00,\n  0xF9, 0xFF, 0xFF, 0x8F, 0xFF, 0xF8, 0x7F, 0xFF, 0xC3, 0xFF, 0xFF, 0x1F,\n  0x00, 0xFC, 0xF8, 0x03, 0xE7, 0xC0, 0x1F, 0x3E, 0x00, 0xF9, 0xF0, 0x07,\n  0xCF, 0x80, 0x3E, 0x7C, 0x01, 0xF3, 0xE0, 0x0F, 0x9F, 0x00, 0x7C, 0xF8,\n  0x03, 0xF7, 0xC0, 0x0F, 0xC0, 0x07, 0xF8, 0x01, 0xFF, 0xF0, 0x3F, 0xFF,\n  0x87, 0xFF, 0xFC, 0x7E, 0x0F, 0xCF, 0xC0, 0x7E, 0xF8, 0x03, 0xEF, 0x80,\n  0x3E, 0xF8, 0x00, 0x0F, 0xC0, 0x00, 0xFF, 0x00, 0x07, 0xFF, 0xC0, 0x3F,\n  0xFF, 0x81, 0xFF, 0xFC, 0x03, 0xFF, 0xE0, 0x01, 0xFF, 0x00, 0x03, 0xF0,\n  0x00, 0x1F, 0xF8, 0x01, 0xFF, 0x80, 0x1F, 0xFC, 0x03, 0xFF, 0xE0, 0x7E,\n  0x7F, 0xFF, 0xE3, 0xFF, 0xFC, 0x1F, 0xFF, 0x00, 0x3F, 0xC0, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0x1F, 0x00, 0x03, 0xE0,\n  0x00, 0x7C, 0x00, 0x0F, 0x80, 0x01, 0xF0, 0x00, 0x3E, 0x00, 0x07, 0xC0,\n  0x00, 0xF8, 0x00, 0x1F, 0x00, 0x03, 0xE0, 0x00, 0x7C, 0x00, 0x0F, 0x80,\n  0x01, 0xF0, 0x00, 0x3E, 0x00, 0x07, 0xC0, 0x00, 0xF8, 0x00, 0x1F, 0x00,\n  0x03, 0xE0, 0x00, 0x7C, 0x00, 0x0F, 0x80, 0x01, 0xF0, 0x00, 0x3E, 0x00,\n  0xF8, 0x01, 0xFF, 0x80, 0x1F, 0xF8, 0x01, 0xFF, 0x80, 0x1F, 0xF8, 0x01,\n  0xFF, 0x80, 0x1F, 0xF8, 0x01, 0xFF, 0x80, 0x1F, 0xF8, 0x01, 0xFF, 0x80,\n  0x1F, 0xF8, 0x01, 0xFF, 0x80, 0x1F, 0xF8, 0x01, 0xFF, 0x80, 0x1F, 0xF8,\n  0x01, 0xFF, 0x80, 0x1F, 0xF8, 0x01, 0xFF, 0x80, 0x1F, 0xF8, 0x01, 0xFF,\n  0x80, 0x1F, 0x7C, 0x03, 0xE7, 0xE0, 0x7E, 0x3F, 0xFF, 0xC3, 0xFF, 0xFC,\n  0x0F, 0xFF, 0x00, 0x3F, 0xC0, 0xF8, 0x00, 0xFB, 0xE0, 0x03, 0xE7, 0xC0,\n  0x1F, 0x9F, 0x00, 0x7C, 0x7C, 0x01, 0xF0, 0xF8, 0x07, 0xC3, 0xE0, 0x3E,\n  0x0F, 0x80, 0xF8, 0x1E, 0x03, 0xE0, 0x7C, 0x1F, 0x01, 0xF0, 0x7C, 0x03,\n  0xC1, 0xF0, 0x0F, 0x87, 0x80, 0x3E, 0x3E, 0x00, 0xF8, 0xF8, 0x01, 0xE3,\n  0xC0, 0x07, 0xCF, 0x00, 0x1F, 0x7C, 0x00, 0x3D, 0xE0, 0x00, 0xFF, 0x80,\n  0x03, 0xFE, 0x00, 0x07, 0xF0, 0x00, 0x1F, 0xC0, 0x00, 0x7F, 0x00, 0x00,\n  0xF8, 0x00, 0x03, 0xE0, 0x00, 0xF8, 0x07, 0xC0, 0x3F, 0xF8, 0x07, 0xE0,\n  0x3E, 0xFC, 0x07, 0xE0, 0x3E, 0x7C, 0x0F, 0xE0, 0x3E, 0x7C, 0x0F, 0xE0,\n  0x7E, 0x7C, 0x0F, 0xE0, 0x7C, 0x7C, 0x0F, 0xF0, 0x7C, 0x3E, 0x0F, 0xF0,\n  0x7C, 0x3E, 0x1E, 0xF0, 0x78, 0x3E, 0x1E, 0x70, 0xF8, 0x1E, 0x1E, 0x70,\n  0xF8, 0x1E, 0x1E, 0x78, 0xF8, 0x1F, 0x1E, 0x78, 0xF0, 0x1F, 0x3C, 0x78,\n  0xF0, 0x0F, 0x3C, 0x39, 0xF0, 0x0F, 0x3C, 0x3D, 0xF0, 0x0F, 0x3C, 0x3D,\n  0xE0, 0x0F, 0xBC, 0x3D, 0xE0, 0x07, 0xF8, 0x3D, 0xE0, 0x07, 0xF8, 0x1F,\n  0xE0, 0x07, 0xF8, 0x1F, 0xC0, 0x03, 0xF8, 0x1F, 0xC0, 0x03, 0xF8, 0x1F,\n  0xC0, 0x03, 0xF0, 0x0F, 0x80, 0x03, 0xF0, 0x0F, 0x80, 0x01, 0xF0, 0x0F,\n  0x80, 0xFE, 0x01, 0xF9, 0xF8, 0x07, 0xE3, 0xF0, 0x3F, 0x0F, 0xC0, 0xF8,\n  0x1F, 0x87, 0xE0, 0x7E, 0x3F, 0x00, 0xFC, 0xFC, 0x01, 0xF7, 0xE0, 0x07,\n  0xFF, 0x00, 0x0F, 0xFC, 0x00, 0x3F, 0xE0, 0x00, 0x7F, 0x00, 0x00, 0xFC,\n  0x00, 0x07, 0xF0, 0x00, 0x1F, 0xE0, 0x00, 0xFF, 0x80, 0x03, 0xFF, 0x00,\n  0x1F, 0x7E, 0x00, 0xFC, 0xF8, 0x03, 0xE3, 0xF0, 0x1F, 0x87, 0xC0, 0x7C,\n  0x1F, 0x83, 0xF0, 0x3F, 0x1F, 0x80, 0xFC, 0x7E, 0x01, 0xFB, 0xF0, 0x07,\n  0xF0, 0xFC, 0x01, 0xFF, 0xE0, 0x0F, 0x9F, 0x00, 0xFC, 0xFC, 0x07, 0xC3,\n  0xE0, 0x7E, 0x1F, 0x83, 0xE0, 0x7C, 0x1F, 0x03, 0xF1, 0xF0, 0x0F, 0x8F,\n  0x80, 0x7E, 0xF8, 0x01, 0xF7, 0xC0, 0x0F, 0xFC, 0x00, 0x3F, 0xE0, 0x00,\n  0xFE, 0x00, 0x07, 0xF0, 0x00, 0x1F, 0x00, 0x00, 0xF8, 0x00, 0x07, 0xC0,\n  0x00, 0x3E, 0x00, 0x01, 0xF0, 0x00, 0x0F, 0x80, 0x00, 0x7C, 0x00, 0x03,\n  0xE0, 0x00, 0x1F, 0x00, 0x00, 0xF8, 0x00, 0x07, 0xC0, 0x00, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0x00, 0x7E, 0x00, 0x1F,\n  0x80, 0x07, 0xE0, 0x00, 0xFC, 0x00, 0x3F, 0x00, 0x0F, 0xC0, 0x03, 0xF8,\n  0x00, 0x7E, 0x00, 0x1F, 0x80, 0x07, 0xE0, 0x01, 0xFC, 0x00, 0x3F, 0x00,\n  0x0F, 0xC0, 0x03, 0xF0, 0x00, 0x7E, 0x00, 0x1F, 0x80, 0x07, 0xE0, 0x01,\n  0xFC, 0x00, 0x3F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8,\n  0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8,\n  0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF, 0xE0, 0x38, 0x06,\n  0x01, 0x80, 0x70, 0x0C, 0x03, 0x00, 0xE0, 0x18, 0x06, 0x01, 0xC0, 0x30,\n  0x0C, 0x03, 0x00, 0xE0, 0x18, 0x06, 0x01, 0xC0, 0x30, 0x0C, 0x03, 0x80,\n  0x60, 0x18, 0x07, 0x01, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x1F, 0x1F, 0x1F,\n  0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,\n  0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0xFF, 0xFF,\n  0xFF, 0xFF, 0x03, 0xE0, 0x07, 0xE0, 0x07, 0xE0, 0x0F, 0xF0, 0x0F, 0xF0,\n  0x0F, 0x78, 0x1E, 0x78, 0x1E, 0x78, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x1E,\n  0x78, 0x1E, 0x78, 0x1E, 0x70, 0x0F, 0xF0, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFE, 0xF8, 0xF0, 0xF0, 0xE0, 0xE0, 0x07, 0xF8, 0x07,\n  0xFF, 0x83, 0xFF, 0xF1, 0xFF, 0xFE, 0x7C, 0x1F, 0xBE, 0x03, 0xE0, 0x00,\n  0xF8, 0x01, 0xFE, 0x0F, 0xFF, 0x8F, 0xFF, 0xE7, 0xF8, 0xFB, 0xF0, 0x3E,\n  0xF8, 0x0F, 0xBE, 0x07, 0xEF, 0xC3, 0xFB, 0xFF, 0xFE, 0x7F, 0xFF, 0x8F,\n  0xFB, 0xF1, 0xF8, 0xFC, 0xF8, 0x00, 0x3E, 0x00, 0x0F, 0x80, 0x03, 0xE0,\n  0x00, 0xF8, 0x00, 0x3E, 0x00, 0x0F, 0x80, 0x03, 0xE7, 0xE0, 0xFB, 0xFC,\n  0x3F, 0xFF, 0xCF, 0xFF, 0xF3, 0xF8, 0x7E, 0xFC, 0x0F, 0xBF, 0x03, 0xFF,\n  0x80, 0x7F, 0xE0, 0x1F, 0xF8, 0x07, 0xFE, 0x01, 0xFF, 0x80, 0x7F, 0xF0,\n  0x3F, 0xFC, 0x0F, 0xBF, 0x87, 0xEF, 0xFF, 0xF3, 0xFF, 0xFC, 0xFB, 0xFC,\n  0x3E, 0x7E, 0x00, 0x03, 0xF0, 0x07, 0xFE, 0x0F, 0xFF, 0x87, 0xFF, 0xE7,\n  0xE1, 0xFB, 0xE0, 0x7F, 0xE0, 0x3F, 0xF0, 0x00, 0xF8, 0x00, 0x7C, 0x00,\n  0x3E, 0x00, 0x1F, 0x00, 0x0F, 0x80, 0xFB, 0xE0, 0x7D, 0xF8, 0x7E, 0x7F,\n  0xFE, 0x3F, 0xFE, 0x0F, 0xFE, 0x00, 0xFC, 0x00, 0x00, 0x03, 0xE0, 0x00,\n  0x7C, 0x00, 0x0F, 0x80, 0x01, 0xF0, 0x00, 0x3E, 0x00, 0x07, 0xC0, 0x00,\n  0xF8, 0x1F, 0x1F, 0x0F, 0xFB, 0xE3, 0xFF, 0xFC, 0xFF, 0xFF, 0xBF, 0x8F,\n  0xF7, 0xC0, 0x7F, 0xF8, 0x0F, 0xFE, 0x00, 0xFF, 0xC0, 0x1F, 0xF8, 0x03,\n  0xFF, 0x00, 0x7F, 0xE0, 0x0F, 0xFE, 0x03, 0xF7, 0xC0, 0x7E, 0xFC, 0x3F,\n  0xCF, 0xFF, 0xF8, 0xFF, 0xFF, 0x0F, 0xFB, 0xE0, 0xFC, 0x7C, 0x07, 0xE0,\n  0x07, 0xFE, 0x03, 0xFF, 0xE0, 0xFF, 0xF8, 0x7E, 0x1F, 0x1F, 0x03, 0xCF,\n  0x80, 0xFB, 0xE0, 0x1E, 0xFF, 0xFF, 0xBF, 0xFF, 0xEF, 0xFF, 0xFB, 0xE0,\n  0x00, 0xF8, 0x00, 0x3F, 0x03, 0xE7, 0xE1, 0xF9, 0xFF, 0xFC, 0x3F, 0xFE,\n  0x07, 0xFF, 0x00, 0x7F, 0x00, 0x0F, 0xC7, 0xF3, 0xFC, 0xFF, 0x3E, 0x0F,\n  0x83, 0xE3, 0xFE, 0xFF, 0xBF, 0xE3, 0xE0, 0xF8, 0x3E, 0x0F, 0x83, 0xE0,\n  0xF8, 0x3E, 0x0F, 0x83, 0xE0, 0xF8, 0x3E, 0x0F, 0x83, 0xE0, 0xF8, 0x3E,\n  0x0F, 0x80, 0x07, 0xC7, 0xC3, 0xFD, 0xF3, 0xFF, 0xFC, 0xFF, 0xFF, 0x7E,\n  0x1F, 0xDF, 0x03, 0xFF, 0xC0, 0xFF, 0xE0, 0x1F, 0xF8, 0x07, 0xFE, 0x01,\n  0xFF, 0x80, 0x7F, 0xE0, 0x1F, 0xFC, 0x0F, 0xDF, 0x03, 0xF7, 0xE1, 0xFD,\n  0xFF, 0xFF, 0x3F, 0xFF, 0xC7, 0xFD, 0xF0, 0x7C, 0x7C, 0x00, 0x1F, 0x00,\n  0x07, 0xFF, 0x03, 0xF7, 0xE1, 0xF9, 0xFF, 0xFC, 0x3F, 0xFE, 0x01, 0xFE,\n  0x00, 0xF8, 0x00, 0x7C, 0x00, 0x3E, 0x00, 0x1F, 0x00, 0x0F, 0x80, 0x07,\n  0xC0, 0x03, 0xE0, 0x01, 0xF1, 0xF0, 0xFB, 0xFE, 0x7F, 0xFF, 0xBF, 0xFF,\n  0xDF, 0xC3, 0xFF, 0xC0, 0xFF, 0xC0, 0x7F, 0xE0, 0x3F, 0xF0, 0x1F, 0xF8,\n  0x0F, 0xFC, 0x07, 0xFE, 0x03, 0xFF, 0x01, 0xFF, 0x80, 0xFF, 0xC0, 0x7F,\n  0xE0, 0x3F, 0xF0, 0x1F, 0xF8, 0x0F, 0xFC, 0x07, 0xC0, 0xFF, 0xFF, 0xF0,\n  0x00, 0x1F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xC0, 0x3E, 0x7C, 0xF9, 0xF0, 0x00, 0x00, 0x1F, 0x3E, 0x7C, 0xF9,\n  0xF3, 0xE7, 0xCF, 0x9F, 0x3E, 0x7C, 0xF9, 0xF3, 0xE7, 0xCF, 0x9F, 0x3E,\n  0x7C, 0xF9, 0xF3, 0xFF, 0xFF, 0xFE, 0xF8, 0xF8, 0x00, 0x7C, 0x00, 0x3E,\n  0x00, 0x1F, 0x00, 0x0F, 0x80, 0x07, 0xC0, 0x03, 0xE0, 0x01, 0xF0, 0x3E,\n  0xF8, 0x3E, 0x7C, 0x3F, 0x3E, 0x3F, 0x1F, 0x3F, 0x0F, 0x9F, 0x07, 0xDF,\n  0x03, 0xFF, 0x81, 0xFF, 0xC0, 0xFF, 0xF0, 0x7F, 0xF8, 0x3F, 0x7E, 0x1F,\n  0x1F, 0x0F, 0x87, 0xC7, 0xC3, 0xF3, 0xE0, 0xF9, 0xF0, 0x7E, 0xF8, 0x1F,\n  0x7C, 0x0F, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xF8, 0xF8, 0x3F, 0x1F,\n  0x7F, 0x9F, 0xF3, 0xFF, 0xFF, 0xFF, 0x7F, 0xFF, 0xFF, 0xFF, 0xC3, 0xF8,\n  0x7F, 0xF8, 0x3F, 0x07, 0xFE, 0x07, 0xC0, 0xFF, 0xC0, 0xF8, 0x1F, 0xF8,\n  0x1F, 0x03, 0xFF, 0x03, 0xE0, 0x7F, 0xE0, 0x7C, 0x0F, 0xFC, 0x0F, 0x81,\n  0xFF, 0x81, 0xF0, 0x3F, 0xF0, 0x3E, 0x07, 0xFE, 0x07, 0xC0, 0xFF, 0xC0,\n  0xF8, 0x1F, 0xF8, 0x1F, 0x03, 0xFF, 0x03, 0xE0, 0x7F, 0xE0, 0x7C, 0x0F,\n  0x80, 0xF8, 0xF8, 0x7D, 0xFF, 0x3F, 0xFF, 0xDF, 0xFF, 0xEF, 0xE1, 0xFF,\n  0xE0, 0x7F, 0xE0, 0x3F, 0xF0, 0x1F, 0xF8, 0x0F, 0xFC, 0x07, 0xFE, 0x03,\n  0xFF, 0x01, 0xFF, 0x80, 0xFF, 0xC0, 0x7F, 0xE0, 0x3F, 0xF0, 0x1F, 0xF8,\n  0x0F, 0xFC, 0x07, 0xFE, 0x03, 0xE0, 0x03, 0xF8, 0x01, 0xFF, 0xC0, 0x7F,\n  0xFC, 0x1F, 0xFF, 0xC7, 0xF0, 0xFC, 0xF8, 0x0F, 0xBF, 0x01, 0xFF, 0xC0,\n  0x1F, 0xF8, 0x03, 0xFF, 0x00, 0x7F, 0xE0, 0x0F, 0xFC, 0x01, 0xFF, 0xC0,\n  0x7E, 0xF8, 0x0F, 0x9F, 0x87, 0xF1, 0xFF, 0xFC, 0x1F, 0xFF, 0x01, 0xFF,\n  0xC0, 0x0F, 0xE0, 0x00, 0xF8, 0xF8, 0x3E, 0xFF, 0x8F, 0xFF, 0xF3, 0xFF,\n  0xFC, 0xFE, 0x1F, 0xBF, 0x03, 0xEF, 0xC0, 0xFF, 0xE0, 0x1F, 0xF8, 0x07,\n  0xFE, 0x01, 0xFF, 0x80, 0x7F, 0xE0, 0x1F, 0xFC, 0x0F, 0xFF, 0x03, 0xEF,\n  0xE1, 0xFB, 0xFF, 0xFC, 0xFF, 0xFF, 0x3E, 0xFF, 0x0F, 0x8F, 0x83, 0xE0,\n  0x00, 0xF8, 0x00, 0x3E, 0x00, 0x0F, 0x80, 0x03, 0xE0, 0x00, 0xF8, 0x00,\n  0x3E, 0x00, 0x00, 0x07, 0xE3, 0xE1, 0xFF, 0x7C, 0x7F, 0xFF, 0x9F, 0xFF,\n  0xF7, 0xF1, 0xFE, 0xF8, 0x0F, 0xFF, 0x01, 0xFF, 0xC0, 0x1F, 0xF8, 0x03,\n  0xFF, 0x00, 0x7F, 0xE0, 0x0F, 0xFC, 0x01, 0xFF, 0xC0, 0x7E, 0xF8, 0x0F,\n  0xDF, 0x83, 0xF9, 0xFF, 0xFF, 0x3F, 0xFF, 0xE1, 0xFF, 0x7C, 0x1F, 0x8F,\n  0x80, 0x01, 0xF0, 0x00, 0x3E, 0x00, 0x07, 0xC0, 0x00, 0xF8, 0x00, 0x1F,\n  0x00, 0x03, 0xE0, 0x00, 0x7C, 0xF8, 0xFF, 0x7F, 0xFF, 0xFF, 0xFF, 0xE1,\n  0xF8, 0x3E, 0x07, 0xC0, 0xF8, 0x1F, 0x03, 0xE0, 0x7C, 0x0F, 0x81, 0xF0,\n  0x3E, 0x07, 0xC0, 0xF8, 0x1F, 0x03, 0xE0, 0x00, 0x07, 0xF0, 0x0F, 0xFE,\n  0x0F, 0xFF, 0x87, 0xFF, 0xE7, 0xE1, 0xF3, 0xE0, 0x79, 0xF8, 0x00, 0xFF,\n  0x80, 0x3F, 0xFC, 0x1F, 0xFF, 0x83, 0xFF, 0xC0, 0x3F, 0xF0, 0x01, 0xFF,\n  0xC0, 0x7D, 0xF0, 0x7E, 0xFF, 0xFE, 0x3F, 0xFF, 0x0F, 0xFF, 0x01, 0xFE,\n  0x00, 0x3E, 0x1F, 0x0F, 0x87, 0xC3, 0xE7, 0xFF, 0xFF, 0xFF, 0x3E, 0x1F,\n  0x0F, 0x87, 0xC3, 0xE1, 0xF0, 0xF8, 0x7C, 0x3E, 0x1F, 0x0F, 0x87, 0xF3,\n  0xF8, 0xFC, 0x3E, 0xF8, 0x0F, 0xFC, 0x07, 0xFE, 0x03, 0xFF, 0x01, 0xFF,\n  0x80, 0xFF, 0xC0, 0x7F, 0xE0, 0x3F, 0xF0, 0x1F, 0xF8, 0x0F, 0xFC, 0x07,\n  0xFE, 0x03, 0xFF, 0x01, 0xFF, 0x80, 0xFF, 0xC0, 0xFF, 0xF0, 0xFF, 0xFF,\n  0xFF, 0x7F, 0xFF, 0x9F, 0xF7, 0xC7, 0xE3, 0xE0, 0x7C, 0x07, 0xCF, 0x80,\n  0xF9, 0xF0, 0x1F, 0x1F, 0x07, 0xC3, 0xE0, 0xF8, 0x7C, 0x1F, 0x07, 0x83,\n  0xC0, 0xF8, 0xF8, 0x1F, 0x1F, 0x01, 0xE3, 0xC0, 0x3E, 0x78, 0x07, 0xDF,\n  0x00, 0x7B, 0xC0, 0x0F, 0xF8, 0x01, 0xFF, 0x00, 0x1F, 0xC0, 0x03, 0xF8,\n  0x00, 0x7F, 0x00, 0x07, 0xC0, 0x00, 0xFC, 0x1F, 0x03, 0xEF, 0x83, 0xE0,\n  0x7D, 0xF0, 0x7E, 0x1F, 0x3E, 0x0F, 0xC3, 0xE3, 0xC3, 0xF8, 0x7C, 0x7C,\n  0x7F, 0x0F, 0x0F, 0x8F, 0xF3, 0xE1, 0xF1, 0xDE, 0x7C, 0x1E, 0x7B, 0xCF,\n  0x83, 0xEF, 0x39, 0xE0, 0x7D, 0xE7, 0x3C, 0x07, 0xB8, 0xFF, 0x80, 0xF7,\n  0x1F, 0xE0, 0x1F, 0xE3, 0xFC, 0x03, 0xFC, 0x3F, 0x80, 0x3F, 0x07, 0xF0,\n  0x07, 0xE0, 0xFC, 0x00, 0xFC, 0x1F, 0x80, 0x0F, 0x83, 0xF0, 0x00, 0xFC,\n  0x1F, 0x9F, 0x07, 0xE7, 0xE3, 0xF0, 0xF8, 0xF8, 0x1F, 0x7E, 0x07, 0xDF,\n  0x00, 0xFF, 0x80, 0x1F, 0xE0, 0x07, 0xF0, 0x00, 0xF8, 0x00, 0x7F, 0x00,\n  0x3F, 0xE0, 0x0F, 0xF8, 0x07, 0xDF, 0x03, 0xF7, 0xE0, 0xF8, 0xF8, 0x7E,\n  0x3F, 0x1F, 0x07, 0xEF, 0xC0, 0xF8, 0x7C, 0x03, 0xEF, 0x80, 0xF9, 0xF8,\n  0x1F, 0x1F, 0x03, 0xE3, 0xE0, 0xF8, 0x7C, 0x1F, 0x07, 0xC3, 0xE0, 0xF8,\n  0x78, 0x0F, 0x1F, 0x01, 0xF3, 0xC0, 0x3E, 0x78, 0x03, 0xDF, 0x00, 0x7F,\n  0xC0, 0x0F, 0xF8, 0x00, 0xFF, 0x00, 0x1F, 0xC0, 0x01, 0xF8, 0x00, 0x3F,\n  0x00, 0x07, 0xC0, 0x00, 0xF8, 0x00, 0x1E, 0x00, 0x07, 0xC0, 0x07, 0xF8,\n  0x00, 0xFE, 0x00, 0x1F, 0x80, 0x03, 0xE0, 0x00, 0x7F, 0xFE, 0x7F, 0xFE,\n  0x7F, 0xFE, 0x7F, 0xFE, 0x00, 0x7E, 0x00, 0xFC, 0x01, 0xF8, 0x03, 0xF0,\n  0x03, 0xF0, 0x07, 0xE0, 0x0F, 0xC0, 0x1F, 0x80, 0x3F, 0x00, 0x7E, 0x00,\n  0xFE, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x07, 0x87,\n  0xC7, 0xE3, 0xF1, 0xE0, 0xF0, 0x78, 0x3C, 0x1E, 0x0F, 0x07, 0x83, 0xC1,\n  0xE0, 0xF0, 0xF9, 0xF8, 0xF0, 0x7E, 0x0F, 0x83, 0xC1, 0xE0, 0xF0, 0x78,\n  0x3C, 0x1E, 0x0F, 0x07, 0x83, 0xC1, 0xE0, 0xFC, 0x7E, 0x1F, 0x07, 0x80,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xE0, 0xF0, 0x7C, 0x3E, 0x1F, 0x83, 0xC1, 0xE0, 0xF0, 0x78, 0x3C, 0x1E,\n  0x0F, 0x07, 0x83, 0xC1, 0xE0, 0xF0, 0x7C, 0x1F, 0x83, 0xC7, 0xE7, 0xC3,\n  0xC1, 0xE0, 0xF0, 0x78, 0x3C, 0x1E, 0x0F, 0x07, 0x83, 0xC7, 0xE3, 0xE1,\n  0xF0, 0xF0, 0x00, 0x3C, 0x00, 0xFE, 0x0F, 0xFE, 0x1E, 0x1F, 0xFC, 0x0F,\n  0xC0, 0x0F, 0x00 };\n\nconst GFXglyph FreeSansBold18pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,  10,    0,    1 },   // 0x20 ' '\n  {     0,   5,  25,  12,    4,  -24 },   // 0x21 '!'\n  {    16,  13,   9,  17,    2,  -25 },   // 0x22 '\"'\n  {    31,  20,  24,  19,    0,  -23 },   // 0x23 '#'\n  {    91,  19,  29,  19,    0,  -25 },   // 0x24 '$'\n  {   160,  29,  25,  31,    1,  -24 },   // 0x25 '%'\n  {   251,  22,  25,  25,    2,  -24 },   // 0x26 '&'\n  {   320,   5,   9,   9,    2,  -25 },   // 0x27 '''\n  {   326,   9,  33,  12,    1,  -25 },   // 0x28 '('\n  {   364,   9,  33,  12,    1,  -25 },   // 0x29 ')'\n  {   402,  12,  11,  14,    0,  -25 },   // 0x2A '*'\n  {   419,  16,  16,  20,    2,  -15 },   // 0x2B '+'\n  {   451,   5,  11,   9,    2,   -4 },   // 0x2C ','\n  {   458,   9,   4,  12,    1,  -10 },   // 0x2D '-'\n  {   463,   5,   5,   9,    2,   -4 },   // 0x2E '.'\n  {   467,   9,  25,  10,    0,  -24 },   // 0x2F '/'\n  {   496,  17,  25,  19,    1,  -24 },   // 0x30 '0'\n  {   550,  10,  25,  19,    3,  -24 },   // 0x31 '1'\n  {   582,  17,  25,  19,    1,  -24 },   // 0x32 '2'\n  {   636,  17,  25,  19,    1,  -24 },   // 0x33 '3'\n  {   690,  16,  25,  19,    2,  -24 },   // 0x34 '4'\n  {   740,  17,  25,  19,    1,  -24 },   // 0x35 '5'\n  {   794,  18,  25,  19,    1,  -24 },   // 0x36 '6'\n  {   851,  17,  25,  19,    1,  -24 },   // 0x37 '7'\n  {   905,  17,  25,  19,    1,  -24 },   // 0x38 '8'\n  {   959,  17,  25,  19,    1,  -24 },   // 0x39 '9'\n  {  1013,   5,  18,   9,    2,  -17 },   // 0x3A ':'\n  {  1025,   5,  24,   9,    2,  -17 },   // 0x3B ';'\n  {  1040,  18,  17,  20,    1,  -16 },   // 0x3C '<'\n  {  1079,  17,  12,  20,    2,  -13 },   // 0x3D '='\n  {  1105,  18,  17,  20,    1,  -16 },   // 0x3E '>'\n  {  1144,  18,  26,  21,    2,  -25 },   // 0x3F '?'\n  {  1203,  32,  31,  34,    1,  -25 },   // 0x40 '@'\n  {  1327,  24,  26,  24,    0,  -25 },   // 0x41 'A'\n  {  1405,  20,  26,  25,    3,  -25 },   // 0x42 'B'\n  {  1470,  23,  26,  25,    1,  -25 },   // 0x43 'C'\n  {  1545,  21,  26,  25,    3,  -25 },   // 0x44 'D'\n  {  1614,  19,  26,  23,    3,  -25 },   // 0x45 'E'\n  {  1676,  17,  26,  22,    3,  -25 },   // 0x46 'F'\n  {  1732,  24,  26,  27,    1,  -25 },   // 0x47 'G'\n  {  1810,  20,  26,  26,    3,  -25 },   // 0x48 'H'\n  {  1875,   5,  26,  11,    3,  -25 },   // 0x49 'I'\n  {  1892,  16,  26,  20,    1,  -25 },   // 0x4A 'J'\n  {  1944,  22,  26,  25,    3,  -25 },   // 0x4B 'K'\n  {  2016,  17,  26,  22,    3,  -25 },   // 0x4C 'L'\n  {  2072,  24,  26,  30,    3,  -25 },   // 0x4D 'M'\n  {  2150,  20,  26,  26,    3,  -25 },   // 0x4E 'N'\n  {  2215,  25,  26,  27,    1,  -25 },   // 0x4F 'O'\n  {  2297,  19,  26,  24,    3,  -25 },   // 0x50 'P'\n  {  2359,  25,  27,  27,    1,  -25 },   // 0x51 'Q'\n  {  2444,  21,  26,  25,    3,  -25 },   // 0x52 'R'\n  {  2513,  20,  26,  24,    2,  -25 },   // 0x53 'S'\n  {  2578,  19,  26,  23,    2,  -25 },   // 0x54 'T'\n  {  2640,  20,  26,  26,    3,  -25 },   // 0x55 'U'\n  {  2705,  22,  26,  23,    1,  -25 },   // 0x56 'V'\n  {  2777,  32,  26,  34,    1,  -25 },   // 0x57 'W'\n  {  2881,  22,  26,  24,    1,  -25 },   // 0x58 'X'\n  {  2953,  21,  26,  22,    1,  -25 },   // 0x59 'Y'\n  {  3022,  19,  26,  21,    1,  -25 },   // 0x5A 'Z'\n  {  3084,   8,  33,  12,    2,  -25 },   // 0x5B '['\n  {  3117,  10,  25,  10,    0,  -24 },   // 0x5C '\\'\n  {  3149,   8,  33,  12,    1,  -25 },   // 0x5D ']'\n  {  3182,  16,  15,  20,    2,  -23 },   // 0x5E '^'\n  {  3212,  21,   3,  19,   -1,    5 },   // 0x5F '_'\n  {  3220,   7,   5,   9,    1,  -25 },   // 0x60 '`'\n  {  3225,  18,  19,  20,    1,  -18 },   // 0x61 'a'\n  {  3268,  18,  26,  22,    2,  -25 },   // 0x62 'b'\n  {  3327,  17,  19,  20,    1,  -18 },   // 0x63 'c'\n  {  3368,  19,  26,  22,    1,  -25 },   // 0x64 'd'\n  {  3430,  18,  19,  20,    1,  -18 },   // 0x65 'e'\n  {  3473,  10,  26,  12,    1,  -25 },   // 0x66 'f'\n  {  3506,  18,  26,  21,    1,  -18 },   // 0x67 'g'\n  {  3565,  17,  26,  21,    2,  -25 },   // 0x68 'h'\n  {  3621,   5,  26,  10,    2,  -25 },   // 0x69 'i'\n  {  3638,   7,  33,  10,    0,  -25 },   // 0x6A 'j'\n  {  3667,  17,  26,  20,    2,  -25 },   // 0x6B 'k'\n  {  3723,   5,  26,   9,    2,  -25 },   // 0x6C 'l'\n  {  3740,  27,  19,  31,    2,  -18 },   // 0x6D 'm'\n  {  3805,  17,  19,  21,    2,  -18 },   // 0x6E 'n'\n  {  3846,  19,  19,  21,    1,  -18 },   // 0x6F 'o'\n  {  3892,  18,  26,  22,    2,  -18 },   // 0x70 'p'\n  {  3951,  19,  26,  22,    1,  -18 },   // 0x71 'q'\n  {  4013,  11,  19,  14,    2,  -18 },   // 0x72 'r'\n  {  4040,  17,  19,  19,    1,  -18 },   // 0x73 's'\n  {  4081,   9,  23,  12,    1,  -22 },   // 0x74 't'\n  {  4107,  17,  19,  21,    2,  -18 },   // 0x75 'u'\n  {  4148,  19,  19,  19,    0,  -18 },   // 0x76 'v'\n  {  4194,  27,  19,  27,    0,  -18 },   // 0x77 'w'\n  {  4259,  18,  19,  19,    1,  -18 },   // 0x78 'x'\n  {  4302,  19,  26,  19,    0,  -18 },   // 0x79 'y'\n  {  4364,  16,  19,  18,    1,  -18 },   // 0x7A 'z'\n  {  4402,   9,  33,  14,    1,  -25 },   // 0x7B '{'\n  {  4440,   3,  33,  10,    4,  -25 },   // 0x7C '|'\n  {  4453,   9,  33,  14,    3,  -25 },   // 0x7D '}'\n  {  4491,  15,   6,  18,    1,  -10 } }; // 0x7E '~'\n\nconst GFXfont FreeSansBold18pt7b PROGMEM = {\n  (uint8_t  *)FreeSansBold18pt7bBitmaps,\n  (GFXglyph *)FreeSansBold18pt7bGlyphs,\n  0x20, 0x7E, 42 };\n\n// Approx. 5175 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeSansBold24pt7b.h",
    "content": "const uint8_t FreeSansBold24pt7bBitmaps[] PROGMEM = {\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xDF, 0x3E, 0x7C, 0xF9, 0xF3, 0xE7, 0xC7, 0x0E, 0x1C, 0x00, 0x00, 0x07,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFE, 0x1F, 0xFF, 0x87, 0xFF, 0xE1,\n  0xFF, 0xF8, 0x7F, 0xFE, 0x1F, 0xFF, 0x87, 0xFF, 0xE1, 0xFD, 0xF0, 0x3E,\n  0x7C, 0x0F, 0x9F, 0x03, 0xE3, 0x80, 0x70, 0xE0, 0x1C, 0x00, 0xF8, 0x3E,\n  0x00, 0x3E, 0x0F, 0x80, 0x0F, 0x83, 0xE0, 0x03, 0xE0, 0xF8, 0x00, 0xF8,\n  0x7C, 0x00, 0x7C, 0x1F, 0x00, 0x1F, 0x07, 0xC1, 0xFF, 0xFF, 0xFF, 0x7F,\n  0xFF, 0xFF, 0xDF, 0xFF, 0xFF, 0xF7, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF,\n  0x03, 0xE0, 0xF8, 0x00, 0xF8, 0x3E, 0x00, 0x3E, 0x1F, 0x00, 0x1F, 0x07,\n  0xC0, 0x07, 0xC1, 0xF0, 0x01, 0xF0, 0x7C, 0x00, 0x7C, 0x1F, 0x03, 0xFF,\n  0xFF, 0xFC, 0xFF, 0xFF, 0xFF, 0x3F, 0xFF, 0xFF, 0xCF, 0xFF, 0xFF, 0xF3,\n  0xFF, 0xFF, 0xFC, 0x0F, 0x87, 0xC0, 0x07, 0xC1, 0xF0, 0x01, 0xF0, 0x7C,\n  0x00, 0x7C, 0x1F, 0x00, 0x1F, 0x07, 0xC0, 0x07, 0xC3, 0xE0, 0x03, 0xE0,\n  0xF8, 0x00, 0xF8, 0x3E, 0x00, 0x3E, 0x0F, 0x80, 0x00, 0x00, 0x38, 0x00,\n  0x00, 0x1C, 0x00, 0x00, 0x7F, 0xE0, 0x00, 0xFF, 0xFC, 0x00, 0xFF, 0xFF,\n  0x80, 0xFF, 0xFF, 0xE0, 0xFF, 0xFF, 0xF8, 0x7F, 0x73, 0xFE, 0x7F, 0x38,\n  0xFF, 0x3F, 0x1C, 0x3F, 0xDF, 0x8E, 0x0F, 0xEF, 0xC7, 0x07, 0xF7, 0xE3,\n  0x80, 0x03, 0xF9, 0xC0, 0x01, 0xFE, 0xE0, 0x00, 0x7F, 0xF0, 0x00, 0x3F,\n  0xFC, 0x00, 0x0F, 0xFF, 0xC0, 0x03, 0xFF, 0xFC, 0x00, 0x7F, 0xFF, 0x80,\n  0x0F, 0xFF, 0xE0, 0x01, 0xFF, 0xF8, 0x00, 0xE7, 0xFC, 0x00, 0x71, 0xFF,\n  0x00, 0x38, 0x7F, 0xFF, 0x1C, 0x1F, 0xFF, 0x8E, 0x0F, 0xFF, 0xC7, 0x07,\n  0xFF, 0xE3, 0x87, 0xFB, 0xF9, 0xC3, 0xF9, 0xFE, 0xE7, 0xFC, 0x7F, 0xFF,\n  0xFC, 0x3F, 0xFF, 0xFC, 0x0F, 0xFF, 0xFC, 0x01, 0xFF, 0xF8, 0x00, 0x3F,\n  0xE0, 0x00, 0x03, 0x80, 0x00, 0x01, 0xC0, 0x00, 0x00, 0xE0, 0x00, 0x00,\n  0x70, 0x00, 0x03, 0xE0, 0x00, 0x3C, 0x00, 0x1F, 0xF0, 0x00, 0x78, 0x00,\n  0x7F, 0xF8, 0x01, 0xE0, 0x01, 0xFF, 0xF0, 0x03, 0xC0, 0x07, 0xFF, 0xF0,\n  0x0F, 0x00, 0x0F, 0x83, 0xE0, 0x1E, 0x00, 0x3E, 0x03, 0xE0, 0x78, 0x00,\n  0x78, 0x03, 0xC0, 0xF0, 0x00, 0xF0, 0x07, 0x83, 0xC0, 0x01, 0xE0, 0x0F,\n  0x07, 0x80, 0x03, 0xE0, 0x3E, 0x1E, 0x00, 0x03, 0xE0, 0xF8, 0x3C, 0x00,\n  0x07, 0xFF, 0xF0, 0xF0, 0x00, 0x07, 0xFF, 0xC1, 0xE0, 0x00, 0x07, 0xFF,\n  0x07, 0x80, 0x00, 0x07, 0xFC, 0x1F, 0x00, 0x00, 0x03, 0xE0, 0x3C, 0x00,\n  0x00, 0x00, 0x00, 0xF0, 0x1F, 0x00, 0x00, 0x01, 0xE0, 0xFF, 0x80, 0x00,\n  0x07, 0x87, 0xFF, 0xC0, 0x00, 0x0F, 0x0F, 0xFF, 0x80, 0x00, 0x3C, 0x3F,\n  0xFF, 0x80, 0x00, 0x78, 0xFC, 0x1F, 0x00, 0x01, 0xE1, 0xF0, 0x1F, 0x00,\n  0x03, 0xC3, 0xC0, 0x1E, 0x00, 0x0F, 0x07, 0x80, 0x3C, 0x00, 0x1E, 0x0F,\n  0x00, 0x78, 0x00, 0x78, 0x1F, 0x01, 0xF0, 0x00, 0xF0, 0x1F, 0x07, 0xC0,\n  0x03, 0xC0, 0x3F, 0xFF, 0x80, 0x07, 0x80, 0x3F, 0xFE, 0x00, 0x1E, 0x00,\n  0x7F, 0xF8, 0x00, 0x7C, 0x00, 0x3F, 0xE0, 0x00, 0xF0, 0x00, 0x1F, 0x00,\n  0x00, 0x3F, 0x00, 0x00, 0x03, 0xFE, 0x00, 0x00, 0x1F, 0xFC, 0x00, 0x00,\n  0xFF, 0xF8, 0x00, 0x07, 0xFF, 0xF0, 0x00, 0x3F, 0xCF, 0xC0, 0x00, 0xFE,\n  0x1F, 0x00, 0x03, 0xF8, 0x7C, 0x00, 0x0F, 0xE1, 0xF0, 0x00, 0x3F, 0xC7,\n  0xC0, 0x00, 0x7F, 0x3E, 0x00, 0x01, 0xFF, 0xF8, 0x00, 0x03, 0xFF, 0xC0,\n  0x00, 0x07, 0xFE, 0x00, 0x00, 0x0F, 0xF0, 0x00, 0x00, 0x7F, 0x80, 0x00,\n  0x07, 0xFF, 0x03, 0xE0, 0x3F, 0xFE, 0x0F, 0x83, 0xFF, 0xF8, 0x3E, 0x1F,\n  0xF3, 0xF1, 0xF8, 0x7F, 0x07, 0xE7, 0xE3, 0xFC, 0x1F, 0xFF, 0x0F, 0xE0,\n  0x3F, 0xFC, 0x3F, 0x80, 0x7F, 0xF0, 0xFE, 0x01, 0xFF, 0x83, 0xF8, 0x03,\n  0xFE, 0x0F, 0xF0, 0x0F, 0xF0, 0x3F, 0xE0, 0x7F, 0xE0, 0x7F, 0xC3, 0xFF,\n  0xC1, 0xFF, 0xFF, 0xFF, 0x03, 0xFF, 0xFF, 0xFE, 0x07, 0xFF, 0xFB, 0xFC,\n  0x0F, 0xFF, 0xC7, 0xF8, 0x1F, 0xFE, 0x0F, 0xE0, 0x0F, 0xE0, 0x00, 0x00,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xBE, 0x7C, 0xF8, 0xE1, 0xC0, 0x00,\n  0xF0, 0x0F, 0x80, 0xF8, 0x07, 0xC0, 0x7C, 0x07, 0xE0, 0x3E, 0x03, 0xF0,\n  0x1F, 0x80, 0xF8, 0x0F, 0xC0, 0x7E, 0x07, 0xE0, 0x3F, 0x01, 0xF8, 0x0F,\n  0xC0, 0xFC, 0x07, 0xE0, 0x3F, 0x01, 0xF8, 0x0F, 0xC0, 0x7E, 0x03, 0xF0,\n  0x1F, 0x80, 0xFC, 0x07, 0xE0, 0x3F, 0x00, 0xF8, 0x07, 0xE0, 0x3F, 0x01,\n  0xF8, 0x07, 0xC0, 0x3F, 0x01, 0xF8, 0x07, 0xC0, 0x3F, 0x00, 0xF8, 0x07,\n  0xE0, 0x1F, 0x00, 0xF8, 0x03, 0xE0, 0x1F, 0x00, 0x7C, 0x01, 0xE0, 0x78,\n  0x03, 0xE0, 0x0F, 0x80, 0x7C, 0x01, 0xF0, 0x0F, 0x80, 0x3E, 0x01, 0xF0,\n  0x0F, 0xC0, 0x3E, 0x01, 0xF8, 0x0F, 0xC0, 0x3F, 0x01, 0xF8, 0x0F, 0xC0,\n  0x7E, 0x01, 0xF8, 0x0F, 0xC0, 0x7E, 0x03, 0xF0, 0x1F, 0x80, 0xFC, 0x07,\n  0xE0, 0x3F, 0x01, 0xF8, 0x0F, 0xC0, 0x7E, 0x03, 0xE0, 0x3F, 0x01, 0xF8,\n  0x0F, 0xC0, 0x7C, 0x07, 0xE0, 0x3F, 0x01, 0xF0, 0x1F, 0x80, 0xF8, 0x0F,\n  0xC0, 0x7C, 0x07, 0xE0, 0x3E, 0x03, 0xF0, 0x1F, 0x01, 0xF0, 0x00, 0x03,\n  0x80, 0x07, 0x00, 0x0E, 0x00, 0x1C, 0x06, 0x38, 0xDF, 0xFF, 0xFF, 0xFF,\n  0x9F, 0xFE, 0x07, 0xC0, 0x1F, 0xC0, 0x3F, 0x80, 0xF7, 0x83, 0xC7, 0x87,\n  0x8F, 0x02, 0x08, 0x00, 0x00, 0x7C, 0x00, 0x00, 0xF8, 0x00, 0x01, 0xF0,\n  0x00, 0x03, 0xE0, 0x00, 0x07, 0xC0, 0x00, 0x0F, 0x80, 0x00, 0x1F, 0x00,\n  0x00, 0x3E, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0x1F, 0x00, 0x00,\n  0x3E, 0x00, 0x00, 0x7C, 0x00, 0x00, 0xF8, 0x00, 0x01, 0xF0, 0x00, 0x03,\n  0xE0, 0x00, 0x07, 0xC0, 0x00, 0x0F, 0x80, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0x87, 0x0E, 0x1C, 0x78, 0xEF, 0xDF, 0x38, 0x00, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0x80, 0x00, 0x38, 0x03, 0xC0, 0x1C, 0x00, 0xE0, 0x07, 0x00,\n  0x70, 0x03, 0x80, 0x1C, 0x01, 0xE0, 0x0E, 0x00, 0x70, 0x03, 0x80, 0x38,\n  0x01, 0xC0, 0x0E, 0x00, 0xF0, 0x07, 0x00, 0x38, 0x03, 0xC0, 0x1C, 0x00,\n  0xE0, 0x07, 0x00, 0x70, 0x03, 0x80, 0x1C, 0x01, 0xE0, 0x0E, 0x00, 0x70,\n  0x03, 0x80, 0x38, 0x01, 0xC0, 0x0E, 0x00, 0xF0, 0x07, 0x00, 0x00, 0x00,\n  0xFF, 0x00, 0x03, 0xFF, 0xC0, 0x0F, 0xFF, 0xF0, 0x1F, 0xFF, 0xF8, 0x1F,\n  0xFF, 0xF8, 0x3F, 0xFF, 0xFC, 0x3F, 0xC3, 0xFC, 0x7F, 0x81, 0xFE, 0x7F,\n  0x00, 0xFE, 0x7F, 0x00, 0xFE, 0x7F, 0x00, 0xFE, 0xFE, 0x00, 0x7F, 0xFE,\n  0x00, 0x7F, 0xFE, 0x00, 0x7F, 0xFE, 0x00, 0x7F, 0xFE, 0x00, 0x7F, 0xFE,\n  0x00, 0x7F, 0xFE, 0x00, 0x7F, 0xFE, 0x00, 0x7F, 0xFE, 0x00, 0x7F, 0xFE,\n  0x00, 0x7F, 0xFE, 0x00, 0x7F, 0xFE, 0x00, 0x7F, 0xFE, 0x00, 0x7F, 0x7F,\n  0x00, 0xFE, 0x7F, 0x00, 0xFE, 0x7F, 0x00, 0xFE, 0x7F, 0x81, 0xFE, 0x3F,\n  0xC3, 0xFC, 0x3F, 0xFF, 0xFC, 0x1F, 0xFF, 0xF8, 0x1F, 0xFF, 0xF8, 0x0F,\n  0xFF, 0xF0, 0x03, 0xFF, 0xC0, 0x00, 0xFF, 0x00, 0x00, 0x3C, 0x01, 0xF0,\n  0x07, 0xC0, 0x3F, 0x01, 0xFC, 0x3F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xF0, 0x1F, 0xC0, 0x7F, 0x01, 0xFC, 0x07, 0xF0, 0x1F, 0xC0, 0x7F,\n  0x01, 0xFC, 0x07, 0xF0, 0x1F, 0xC0, 0x7F, 0x01, 0xFC, 0x07, 0xF0, 0x1F,\n  0xC0, 0x7F, 0x01, 0xFC, 0x07, 0xF0, 0x1F, 0xC0, 0x7F, 0x01, 0xFC, 0x07,\n  0xF0, 0x1F, 0xC0, 0x7F, 0x01, 0xFC, 0x01, 0xFE, 0x00, 0x0F, 0xFF, 0x80,\n  0x3F, 0xFF, 0x80, 0xFF, 0xFF, 0x83, 0xFF, 0xFF, 0x8F, 0xFF, 0xFF, 0x9F,\n  0xE0, 0xFF, 0x7F, 0x80, 0xFF, 0xFE, 0x01, 0xFF, 0xFC, 0x01, 0xFF, 0xF8,\n  0x03, 0xFF, 0xF0, 0x07, 0xF0, 0x00, 0x0F, 0xE0, 0x00, 0x1F, 0xC0, 0x00,\n  0x7F, 0x80, 0x00, 0xFE, 0x00, 0x03, 0xFC, 0x00, 0x0F, 0xF0, 0x00, 0x7F,\n  0xC0, 0x01, 0xFF, 0x00, 0x07, 0xF8, 0x00, 0x3F, 0xE0, 0x00, 0xFF, 0x00,\n  0x03, 0xFC, 0x00, 0x0F, 0xF0, 0x00, 0x3F, 0xC0, 0x00, 0x7F, 0x00, 0x01,\n  0xFC, 0x00, 0x03, 0xFF, 0xFF, 0xE7, 0xFF, 0xFF, 0xDF, 0xFF, 0xFF, 0xBF,\n  0xFF, 0xFF, 0x7F, 0xFF, 0xFE, 0xFF, 0xFF, 0xFC, 0x01, 0xFE, 0x00, 0x0F,\n  0xFF, 0x80, 0x7F, 0xFF, 0x81, 0xFF, 0xFF, 0x87, 0xFF, 0xFF, 0x8F, 0xFF,\n  0xFF, 0x1F, 0xE1, 0xFF, 0x7F, 0x81, 0xFE, 0xFE, 0x01, 0xFD, 0xFC, 0x03,\n  0xFB, 0xF8, 0x07, 0xF0, 0x00, 0x0F, 0xE0, 0x00, 0x1F, 0x80, 0x00, 0x7F,\n  0x00, 0x01, 0xFC, 0x00, 0x1F, 0xF0, 0x00, 0x3F, 0xC0, 0x00, 0x7F, 0xC0,\n  0x00, 0xFF, 0xE0, 0x00, 0x3F, 0xE0, 0x00, 0x1F, 0xC0, 0x00, 0x3F, 0xC0,\n  0x00, 0x3F, 0x80, 0x00, 0x7F, 0x00, 0x00, 0xFF, 0xFC, 0x01, 0xFF, 0xF8,\n  0x07, 0xFF, 0xF8, 0x0F, 0xF7, 0xF8, 0x3F, 0xCF, 0xFF, 0xFF, 0x9F, 0xFF,\n  0xFE, 0x1F, 0xFF, 0xF8, 0x1F, 0xFF, 0xE0, 0x0F, 0xFF, 0x80, 0x07, 0xF8,\n  0x00, 0x00, 0x1F, 0xE0, 0x00, 0x7F, 0x80, 0x03, 0xFE, 0x00, 0x0F, 0xF8,\n  0x00, 0x7F, 0xE0, 0x03, 0xFF, 0x80, 0x0F, 0xFE, 0x00, 0x7B, 0xF8, 0x01,\n  0xEF, 0xE0, 0x0F, 0x3F, 0x80, 0x78, 0xFE, 0x01, 0xE3, 0xF8, 0x0F, 0x0F,\n  0xE0, 0x38, 0x3F, 0x81, 0xE0, 0xFE, 0x07, 0x03, 0xF8, 0x3C, 0x0F, 0xE1,\n  0xE0, 0x3F, 0x87, 0x00, 0xFE, 0x3C, 0x03, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xF0, 0x00, 0xFE, 0x00, 0x03, 0xF8, 0x00, 0x0F, 0xE0, 0x00, 0x3F, 0x80,\n  0x00, 0xFE, 0x00, 0x03, 0xF8, 0x00, 0x0F, 0xE0, 0x1F, 0xFF, 0xFC, 0x3F,\n  0xFF, 0xF8, 0x7F, 0xFF, 0xF0, 0xFF, 0xFF, 0xE3, 0xFF, 0xFF, 0xC7, 0xFF,\n  0xFF, 0x8F, 0x80, 0x00, 0x1F, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x78, 0x00,\n  0x01, 0xF1, 0xF8, 0x03, 0xEF, 0xFE, 0x07, 0xFF, 0xFE, 0x0F, 0xFF, 0xFE,\n  0x1F, 0xFF, 0xFE, 0x7F, 0xFF, 0xFC, 0xFE, 0x07, 0xFC, 0x00, 0x07, 0xF8,\n  0x00, 0x07, 0xF8, 0x00, 0x07, 0xF0, 0x00, 0x0F, 0xE0, 0x00, 0x1F, 0xC0,\n  0x00, 0x3F, 0x80, 0x00, 0x7F, 0x00, 0x00, 0xFF, 0xF8, 0x03, 0xFF, 0xF8,\n  0x0F, 0xF7, 0xF8, 0x3F, 0xEF, 0xFF, 0xFF, 0x8F, 0xFF, 0xFF, 0x0F, 0xFF,\n  0xFC, 0x0F, 0xFF, 0xE0, 0x0F, 0xFF, 0x80, 0x03, 0xF8, 0x00, 0x00, 0xFF,\n  0x00, 0x07, 0xFF, 0x80, 0x1F, 0xFF, 0xC0, 0x7F, 0xFF, 0x81, 0xFF, 0xFF,\n  0x87, 0xFF, 0xFF, 0x8F, 0xF0, 0xFF, 0x3F, 0xC0, 0xFE, 0x7F, 0x00, 0x00,\n  0xFE, 0x00, 0x01, 0xFC, 0x00, 0x07, 0xF0, 0x00, 0x0F, 0xE3, 0xF0, 0x1F,\n  0xDF, 0xF8, 0x3F, 0xFF, 0xFC, 0x7F, 0xFF, 0xFC, 0xFF, 0xFF, 0xF9, 0xFF,\n  0x87, 0xFB, 0xFC, 0x07, 0xF7, 0xF8, 0x0F, 0xFF, 0xE0, 0x0F, 0xFF, 0xC0,\n  0x1F, 0xFF, 0x80, 0x3F, 0xFF, 0x00, 0x7F, 0x7E, 0x00, 0xFE, 0xFC, 0x01,\n  0xFD, 0xFC, 0x07, 0xFB, 0xF8, 0x0F, 0xE3, 0xFC, 0x7F, 0xC7, 0xFF, 0xFF,\n  0x07, 0xFF, 0xFE, 0x0F, 0xFF, 0xF8, 0x0F, 0xFF, 0xE0, 0x07, 0xFF, 0x80,\n  0x03, 0xF8, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0x00, 0x3F, 0x00,\n  0x00, 0xFC, 0x00, 0x03, 0xF8, 0x00, 0x07, 0xE0, 0x00, 0x1F, 0x80, 0x00,\n  0x7F, 0x00, 0x00, 0xFC, 0x00, 0x03, 0xF8, 0x00, 0x07, 0xE0, 0x00, 0x1F,\n  0x80, 0x00, 0x7F, 0x00, 0x00, 0xFE, 0x00, 0x01, 0xF8, 0x00, 0x07, 0xF0,\n  0x00, 0x0F, 0xC0, 0x00, 0x3F, 0x80, 0x00, 0x7F, 0x00, 0x00, 0xFC, 0x00,\n  0x01, 0xF8, 0x00, 0x07, 0xF0, 0x00, 0x0F, 0xE0, 0x00, 0x1F, 0xC0, 0x00,\n  0x3F, 0x00, 0x00, 0xFE, 0x00, 0x01, 0xFC, 0x00, 0x03, 0xF8, 0x00, 0x07,\n  0xF0, 0x00, 0x00, 0xFE, 0x00, 0x03, 0xFF, 0xC0, 0x0F, 0xFF, 0xE0, 0x1F,\n  0xFF, 0xF0, 0x3F, 0xFF, 0xF8, 0x3F, 0xFF, 0xF8, 0x7F, 0x83, 0xFC, 0x7F,\n  0x00, 0xFC, 0x7E, 0x00, 0xFC, 0x7E, 0x00, 0x7C, 0x7E, 0x00, 0x7C, 0x7E,\n  0x00, 0xFC, 0x3F, 0x00, 0xF8, 0x3F, 0x83, 0xF8, 0x0F, 0xFF, 0xF0, 0x07,\n  0xFF, 0xC0, 0x0F, 0xFF, 0xF0, 0x1F, 0xFF, 0xF8, 0x3F, 0xC3, 0xFC, 0x7F,\n  0x00, 0xFE, 0x7F, 0x00, 0xFE, 0xFE, 0x00, 0x7F, 0xFE, 0x00, 0x7F, 0xFE,\n  0x00, 0x7F, 0xFE, 0x00, 0x7F, 0xFE, 0x00, 0x7F, 0xFF, 0x00, 0xFF, 0xFF,\n  0x00, 0xFE, 0x7F, 0x83, 0xFE, 0x7F, 0xFF, 0xFE, 0x3F, 0xFF, 0xFC, 0x1F,\n  0xFF, 0xF8, 0x0F, 0xFF, 0xF0, 0x07, 0xFF, 0xC0, 0x00, 0xFF, 0x00, 0x00,\n  0xFF, 0x00, 0x03, 0xFF, 0xC0, 0x0F, 0xFF, 0xE0, 0x1F, 0xFF, 0xF0, 0x3F,\n  0xFF, 0xF8, 0x3F, 0xFF, 0xFC, 0x7F, 0xC3, 0xFC, 0x7F, 0x01, 0xFE, 0xFF,\n  0x00, 0xFE, 0xFE, 0x00, 0x7E, 0xFE, 0x00, 0x7E, 0xFE, 0x00, 0x7F, 0xFE,\n  0x00, 0x7F, 0xFE, 0x00, 0x7F, 0xFE, 0x00, 0x7F, 0xFF, 0x00, 0xFF, 0x7F,\n  0x01, 0xFF, 0x7F, 0xC3, 0xFF, 0x7F, 0xFF, 0xFF, 0x3F, 0xFF, 0xFF, 0x1F,\n  0xFF, 0xFF, 0x0F, 0xFF, 0x7F, 0x07, 0xFE, 0x7F, 0x01, 0xFC, 0x7E, 0x00,\n  0x00, 0x7E, 0x00, 0x00, 0xFE, 0x00, 0x00, 0xFE, 0x7F, 0x01, 0xFC, 0x7F,\n  0x83, 0xFC, 0x7F, 0xFF, 0xF8, 0x3F, 0xFF, 0xF8, 0x3F, 0xFF, 0xF0, 0x1F,\n  0xFF, 0xE0, 0x07, 0xFF, 0x80, 0x01, 0xFE, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n 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 0x01, 0xFC, 0x1F, 0xF8, 0xFF, 0x80, 0x1F, 0xC0, 0xFC, 0x07, 0xC0, 0x01,\n  0xFC, 0x00, 0x00, 0x00, 0x00, 0x1F, 0xC0, 0x00, 0x00, 0x00, 0x01, 0xFE,\n  0x00, 0x00, 0x00, 0x00, 0x1F, 0xF8, 0x00, 0x60, 0x00, 0x01, 0xFF, 0xFF,\n  0xFE, 0x00, 0x00, 0x0F, 0xFF, 0xFF, 0xC0, 0x00, 0x00, 0x7F, 0xFF, 0xF0,\n  0x00, 0x00, 0x00, 0xFF, 0xE0, 0x00, 0x00, 0x00, 0x0F, 0xF8, 0x00, 0x00,\n  0x0F, 0xF8, 0x00, 0x00, 0x0F, 0xF8, 0x00, 0x00, 0x1F, 0xFC, 0x00, 0x00,\n  0x1F, 0xFC, 0x00, 0x00, 0x1F, 0xFC, 0x00, 0x00, 0x3F, 0xFE, 0x00, 0x00,\n  0x3F, 0xFE, 0x00, 0x00, 0x3F, 0x7E, 0x00, 0x00, 0x7F, 0x7F, 0x00, 0x00,\n  0x7F, 0x7F, 0x00, 0x00, 0x7E, 0x3F, 0x00, 0x00, 0xFE, 0x3F, 0x80, 0x00,\n  0xFE, 0x3F, 0x80, 0x01, 0xFC, 0x1F, 0x80, 0x01, 0xFC, 0x1F, 0xC0, 0x01,\n  0xF8, 0x1F, 0xC0, 0x03, 0xF8, 0x0F, 0xE0, 0x03, 0xF8, 0x0F, 0xE0, 0x03,\n  0xF0, 0x0F, 0xE0, 0x07, 0xF0, 0x07, 0xF0, 0x07, 0xFF, 0xFF, 0xF0, 0x07,\n  0xFF, 0xFF, 0xF0, 0x0F, 0xFF, 0xFF, 0xF8, 0x0F, 0xFF, 0xFF, 0xF8, 0x1F,\n  0xFF, 0xFF, 0xF8, 0x1F, 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0xF0, 0x0F, 0xFF, 0xFF,\n  0xE0, 0x3F, 0xFF, 0xFF, 0xC1, 0xFF, 0x81, 0xFF, 0x0F, 0xF8, 0x01, 0xFE,\n  0x3F, 0xC0, 0x07, 0xF9, 0xFE, 0x00, 0x0F, 0xE7, 0xF8, 0x00, 0x1F, 0xDF,\n  0xC0, 0x00, 0x7F, 0x7F, 0x00, 0x00, 0x03, 0xF8, 0x00, 0x00, 0x0F, 0xE0,\n  0x00, 0x00, 0x3F, 0x80, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x03, 0xF8, 0x00,\n  0x00, 0x0F, 0xE0, 0x00, 0x00, 0x3F, 0x80, 0x00, 0x00, 0xFE, 0x00, 0x00,\n  0x03, 0xF8, 0x00, 0x00, 0x0F, 0xE0, 0x00, 0x00, 0x1F, 0xC0, 0x00, 0x00,\n  0x7F, 0x00, 0x01, 0xFD, 0xFC, 0x00, 0x07, 0xF7, 0xF8, 0x00, 0x3F, 0xCF,\n  0xF0, 0x00, 0xFE, 0x3F, 0xE0, 0x07, 0xF8, 0x7F, 0xE0, 0x7F, 0xC0, 0xFF,\n  0xFF, 0xFF, 0x03, 0xFF, 0xFF, 0xF8, 0x07, 0xFF, 0xFF, 0xC0, 0x07, 0xFF,\n  0xFE, 0x00, 0x0F, 0xFF, 0xE0, 0x00, 0x07, 0xFC, 0x00, 0xFF, 0xFF, 0xC0,\n  0x0F, 0xFF, 0xFF, 0x80, 0xFF, 0xFF, 0xFC, 0x0F, 0xFF, 0xFF, 0xE0, 0xFF,\n  0xFF, 0xFF, 0x0F, 0xFF, 0xFF, 0xF8, 0xFE, 0x00, 0xFF, 0xCF, 0xE0, 0x03,\n  0xFC, 0xFE, 0x00, 0x1F, 0xEF, 0xE0, 0x01, 0xFE, 0xFE, 0x00, 0x0F, 0xEF,\n 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0x3F, 0xC0, 0x01, 0xFC,\n  0x7F, 0x00, 0x01, 0xFD, 0xFE, 0x00, 0x03, 0xFB, 0xF8, 0x00, 0x00, 0x07,\n  0xF0, 0x00, 0x00, 0x1F, 0xC0, 0x00, 0x00, 0x3F, 0x80, 0x00, 0x00, 0x7F,\n  0x00, 0x00, 0x00, 0xFE, 0x00, 0x3F, 0xFF, 0xFC, 0x00, 0x7F, 0xFF, 0xF8,\n  0x00, 0xFF, 0xFF, 0xF0, 0x01, 0xFF, 0xFF, 0xE0, 0x03, 0xFF, 0xFF, 0xC0,\n  0x07, 0xFF, 0xFF, 0xC0, 0x00, 0x1F, 0xBF, 0x80, 0x00, 0x3F, 0x7F, 0x00,\n  0x00, 0x7E, 0xFF, 0x00, 0x01, 0xFC, 0xFF, 0x00, 0x03, 0xF9, 0xFF, 0x00,\n  0x0F, 0xF1, 0xFF, 0x00, 0x3F, 0xE3, 0xFF, 0x83, 0xFF, 0xC3, 0xFF, 0xFF,\n  0xFF, 0x83, 0xFF, 0xFF, 0xDF, 0x03, 0xFF, 0xFF, 0x9E, 0x03, 0xFF, 0xFE,\n  0x3C, 0x01, 0xFF, 0xF0, 0x78, 0x00, 0x7F, 0x80, 0x00, 0xFE, 0x00, 0x0F,\n  0xFF, 0xC0, 0x01, 0xFF, 0xF8, 0x00, 0x3F, 0xFF, 0x00, 0x07, 0xFF, 0xE0,\n  0x00, 0xFF, 0xFC, 0x00, 0x1F, 0xFF, 0x80, 0x03, 0xFF, 0xF0, 0x00, 0x7F,\n  0xFE, 0x00, 0x0F, 0xFF, 0xC0, 0x01, 0xFF, 0xF8, 0x00, 0x3F, 0xFF, 0x00,\n  0x07, 0xFF, 0xE0, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n 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0xFE, 0x01, 0xFF, 0xF8, 0x07, 0xFF, 0xE0, 0x1F,\n  0xFF, 0xC0, 0xFF, 0xFF, 0x87, 0xFD, 0xFF, 0xFF, 0xE7, 0xFF, 0xFF, 0x8F,\n  0xFF, 0xFC, 0x1F, 0xFF, 0xE0, 0x3F, 0xFF, 0x00, 0x1F, 0xE0, 0x00, 0xFE,\n  0x00, 0x0F, 0xF3, 0xF8, 0x00, 0x7F, 0x8F, 0xE0, 0x03, 0xFC, 0x3F, 0x80,\n  0x1F, 0xE0, 0xFE, 0x00, 0xFF, 0x83, 0xF8, 0x07, 0xFC, 0x0F, 0xE0, 0x1F,\n  0xE0, 0x3F, 0x80, 0xFF, 0x00, 0xFE, 0x07, 0xF8, 0x03, 0xF8, 0x3F, 0xC0,\n  0x0F, 0xE1, 0xFE, 0x00, 0x3F, 0x8F, 0xF0, 0x00, 0xFE, 0x7F, 0x80, 0x03,\n  0xFB, 0xFC, 0x00, 0x0F, 0xFF, 0xE0, 0x00, 0x3F, 0xFF, 0xC0, 0x00, 0xFF,\n  0xFF, 0x00, 0x03, 0xFF, 0xFE, 0x00, 0x0F, 0xFF, 0xFC, 0x00, 0x3F, 0xF7,\n  0xF8, 0x00, 0xFF, 0x8F, 0xF0, 0x03, 0xFC, 0x3F, 0xC0, 0x0F, 0xE0, 0x7F,\n  0x80, 0x3F, 0x80, 0xFF, 0x00, 0xFE, 0x01, 0xFE, 0x03, 0xF8, 0x07, 0xFC,\n  0x0F, 0xE0, 0x0F, 0xF0, 0x3F, 0x80, 0x1F, 0xE0, 0xFE, 0x00, 0x3F, 0xC3,\n  0xF8, 0x00, 0xFF, 0x8F, 0xE0, 0x01, 0xFE, 0x3F, 0x80, 0x03, 0xFC, 0xFE,\n  0x00, 0x07, 0xFB, 0xF8, 0x00, 0x1F, 0xF0, 0xFE, 0x00, 0x01, 0xFC, 0x00,\n  0x03, 0xF8, 0x00, 0x07, 0xF0, 0x00, 0x0F, 0xE0, 0x00, 0x1F, 0xC0, 0x00,\n  0x3F, 0x80, 0x00, 0x7F, 0x00, 0x00, 0xFE, 0x00, 0x01, 0xFC, 0x00, 0x03,\n  0xF8, 0x00, 0x07, 0xF0, 0x00, 0x0F, 0xE0, 0x00, 0x1F, 0xC0, 0x00, 0x3F,\n  0x80, 0x00, 0x7F, 0x00, 0x00, 0xFE, 0x00, 0x01, 0xFC, 0x00, 0x03, 0xF8,\n  0x00, 0x07, 0xF0, 0x00, 0x0F, 0xE0, 0x00, 0x1F, 0xC0, 0x00, 0x3F, 0x80,\n  0x00, 0x7F, 0x00, 0x00, 0xFE, 0x00, 0x01, 0xFC, 0x00, 0x03, 0xF8, 0x00,\n  0x07, 0xF0, 0x00, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xE0, 0x03,\n  0xFF, 0xFF, 0xF0, 0x01, 0xFF, 0xFF, 0xF8, 0x00, 0xFF, 0xFF, 0xFC, 0x00,\n  0x7F, 0xFF, 0xFE, 0x00, 0x7F, 0xFF, 0xFF, 0x80, 0x3F, 0xFF, 0xFF, 0xC0,\n  0x1F, 0xFF, 0xFF, 0xE0, 0x0F, 0xFF, 0xFF, 0xF0, 0x07, 0xFF, 0xFF, 0xFC,\n  0x07, 0xFF, 0xFF, 0xBE, 0x03, 0xEF, 0xFF, 0xDF, 0x01, 0xF7, 0xFF, 0xEF,\n  0x80, 0xFB, 0xFF, 0xF7, 0xC0, 0xFD, 0xFF, 0xFB, 0xF0, 0x7C, 0xFF, 0xFC,\n  0xF8, 0x3E, 0x7F, 0xFE, 0x7C, 0x1F, 0x3F, 0xFF, 0x3E, 0x0F, 0x9F, 0xFF,\n  0x9F, 0x8F, 0x8F, 0xFF, 0xC7, 0xC7, 0xC7, 0xFF, 0xE3, 0xE3, 0xE3, 0xFF,\n  0xF1, 0xF1, 0xF1, 0xFF, 0xF8, 0xFC, 0xF8, 0xFF, 0xFC, 0x3E, 0xF8, 0x7F,\n  0xFE, 0x1F, 0x7C, 0x3F, 0xFF, 0x0F, 0xBE, 0x1F, 0xFF, 0x87, 0xDF, 0x0F,\n  0xFF, 0xC3, 0xFF, 0x07, 0xFF, 0xE0, 0xFF, 0x83, 0xFF, 0xF0, 0x7F, 0xC1,\n  0xFF, 0xF8, 0x3F, 0xE0, 0xFF, 0xFC, 0x1F, 0xF0, 0x7F, 0xFE, 0x07, 0xF0,\n  0x3F, 0xFF, 0x03, 0xF8, 0x1F, 0xC0, 0xFE, 0x00, 0x07, 0xFF, 0xF0, 0x00,\n  0x7F, 0xFF, 0x80, 0x07, 0xFF, 0xF8, 0x00, 0x7F, 0xFF, 0xC0, 0x07, 0xFF,\n  0xFC, 0x00, 0x7F, 0xFF, 0xE0, 0x07, 0xFF, 0xFF, 0x00, 0x7F, 0xFF, 0xF0,\n  0x07, 0xFF, 0xFF, 0x80, 0x7F, 0xFF, 0xF8, 0x07, 0xFF, 0xEF, 0xC0, 0x7F,\n  0xFE, 0xFE, 0x07, 0xFF, 0xE7, 0xE0, 0x7F, 0xFE, 0x7F, 0x07, 0xFF, 0xE3,\n  0xF0, 0x7F, 0xFE, 0x1F, 0x87, 0xFF, 0xE1, 0xFC, 0x7F, 0xFE, 0x0F, 0xC7,\n  0xFF, 0xE0, 0xFE, 0x7F, 0xFE, 0x07, 0xE7, 0xFF, 0xE0, 0x3F, 0x7F, 0xFE,\n  0x03, 0xFF, 0xFF, 0xE0, 0x1F, 0xFF, 0xFE, 0x01, 0xFF, 0xFF, 0xE0, 0x0F,\n  0xFF, 0xFE, 0x00, 0x7F, 0xFF, 0xE0, 0x07, 0xFF, 0xFE, 0x00, 0x3F, 0xFF,\n  0xE0, 0x03, 0xFF, 0xFE, 0x00, 0x1F, 0xFF, 0xE0, 0x00, 0xFF, 0xFE, 0x00,\n  0x0F, 0xFF, 0xE0, 0x00, 0x7F, 0x00, 0x0F, 0xF8, 0x00, 0x00, 0x3F, 0xFF,\n  0x80, 0x00, 0x7F, 0xFF, 0xE0, 0x00, 0x7F, 0xFF, 0xFC, 0x00, 0x7F, 0xFF,\n  0xFF, 0x00, 0x7F, 0xFF, 0xFF, 0xC0, 0x7F, 0xE0, 0x3F, 0xF0, 0x3F, 0xC0,\n  0x0F, 0xF8, 0x3F, 0xC0, 0x01, 0xFE, 0x1F, 0xC0, 0x00, 0x7F, 0x1F, 0xE0,\n  0x00, 0x3F, 0xCF, 0xE0, 0x00, 0x0F, 0xE7, 0xF0, 0x00, 0x07, 0xF7, 0xF8,\n  0x00, 0x03, 0xFF, 0xF8, 0x00, 0x00, 0xFF, 0xFC, 0x00, 0x00, 0x7F, 0xFE,\n  0x00, 0x00, 0x3F, 0xFF, 0x00, 0x00, 0x1F, 0xFF, 0x80, 0x00, 0x0F, 0xFF,\n  0xC0, 0x00, 0x07, 0xFF, 0xE0, 0x00, 0x03, 0xFF, 0xF0, 0x00, 0x01, 0xFF,\n  0xFC, 0x00, 0x01, 0xFE, 0xFE, 0x00, 0x00, 0xFE, 0x7F, 0x00, 0x00, 0x7F,\n  0x3F, 0xC0, 0x00, 0x7F, 0x8F, 0xE0, 0x00, 0x3F, 0x87, 0xF8, 0x00, 0x3F,\n  0xC1, 0xFE, 0x00, 0x3F, 0xC0, 0xFF, 0xC0, 0x7F, 0xE0, 0x3F, 0xFF, 0xFF,\n  0xE0, 0x0F, 0xFF, 0xFF, 0xE0, 0x03, 0xFF, 0xFF, 0xE0, 0x00, 0xFF, 0xFF,\n  0xE0, 0x00, 0x1F, 0xFF, 0xC0, 0x00, 0x01, 0xFF, 0x00, 0x00, 0xFF, 0xFF,\n  0xE0, 0x3F, 0xFF, 0xFF, 0x0F, 0xFF, 0xFF, 0xE3, 0xFF, 0xFF, 0xFC, 0xFF,\n  0xFF, 0xFF, 0xBF, 0xFF, 0xFF, 0xEF, 0xE0, 0x0F, 0xFB, 0xF8, 0x00, 0xFF,\n  0xFE, 0x00, 0x1F, 0xFF, 0x80, 0x07, 0xFF, 0xE0, 0x01, 0xFF, 0xF8, 0x00,\n  0x7F, 0xFE, 0x00, 0x1F, 0xFF, 0x80, 0x07, 0xFF, 0xE0, 0x03, 0xFF, 0xF8,\n  0x03, 0xFE, 0xFF, 0xFF, 0xFF, 0xBF, 0xFF, 0xFF, 0xCF, 0xFF, 0xFF, 0xF3,\n  0xFF, 0xFF, 0xF8, 0xFF, 0xFF, 0xF8, 0x3F, 0xFF, 0xF8, 0x0F, 0xE0, 0x00,\n  0x03, 0xF8, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x3F, 0x80, 0x00, 0x0F, 0xE0,\n  0x00, 0x03, 0xF8, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x3F, 0x80, 0x00, 0x0F,\n  0xE0, 0x00, 0x03, 0xF8, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x3F, 0x80, 0x00,\n  0x00, 0x00, 0x0F, 0xF8, 0x00, 0x00, 0x3F, 0xFF, 0x80, 0x00, 0x7F, 0xFF,\n  0xE0, 0x00, 0x7F, 0xFF, 0xFC, 0x00, 0x7F, 0xFF, 0xFF, 0x00, 0x7F, 0xFF,\n  0xFF, 0xC0, 0x7F, 0xE0, 0x3F, 0xF0, 0x3F, 0xC0, 0x07, 0xF8, 0x3F, 0xC0,\n  0x01, 0xFE, 0x1F, 0xC0, 0x00, 0x7F, 0x1F, 0xE0, 0x00, 0x3F, 0xCF, 0xE0,\n  0x00, 0x0F, 0xE7, 0xF0, 0x00, 0x07, 0xF7, 0xF8, 0x00, 0x03, 0xFF, 0xF8,\n  0x00, 0x00, 0xFF, 0xFC, 0x00, 0x00, 0x7F, 0xFE, 0x00, 0x00, 0x3F, 0xFF,\n  0x00, 0x00, 0x1F, 0xFF, 0x80, 0x00, 0x0F, 0xFF, 0xC0, 0x00, 0x07, 0xFF,\n  0xE0, 0x00, 0x03, 0xFF, 0xF0, 0x00, 0x01, 0xFF, 0xFC, 0x00, 0x21, 0xFE,\n  0xFE, 0x00, 0x38, 0xFE, 0x7F, 0x00, 0x3E, 0x7F, 0x3F, 0xC0, 0x3F, 0xFF,\n  0x8F, 0xE0, 0x0F, 0xFF, 0x87, 0xF8, 0x03, 0xFF, 0xC1, 0xFE, 0x00, 0xFF,\n  0xC0, 0xFF, 0xC0, 0x7F, 0xE0, 0x3F, 0xFF, 0xFF, 0xF0, 0x0F, 0xFF, 0xFF,\n  0xFC, 0x03, 0xFF, 0xFF, 0xFF, 0x00, 0xFF, 0xFF, 0xFF, 0xC0, 0x1F, 0xFF,\n  0xCF, 0xC0, 0x01, 0xFF, 0x03, 0xC0, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF,\n  0xF8, 0x0F, 0xFF, 0xFF, 0xE0, 0xFF, 0xFF, 0xFF, 0x8F, 0xFF, 0xFF, 0xF8,\n  0xFF, 0xFF, 0xFF, 0xCF, 0xFF, 0xFF, 0xFC, 0xFE, 0x00, 0x3F, 0xEF, 0xE0,\n  0x01, 0xFE, 0xFE, 0x00, 0x0F, 0xEF, 0xE0, 0x00, 0xFE, 0xFE, 0x00, 0x0F,\n  0xEF, 0xE0, 0x00, 0xFE, 0xFE, 0x00, 0x0F, 0xEF, 0xE0, 0x01, 0xFC, 0xFE,\n  0x00, 0x3F, 0xCF, 0xFF, 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0x0F, 0xFF, 0xFF,\n  0xC0, 0xFF, 0xFF, 0xFE, 0x0F, 0xFF, 0xFF, 0xF0, 0xFF, 0xFF, 0xFF, 0x8F,\n  0xE0, 0x07, 0xF8, 0xFE, 0x00, 0x1F, 0xCF, 0xE0, 0x01, 0xFC, 0xFE, 0x00,\n  0x1F, 0xCF, 0xE0, 0x01, 0xFC, 0xFE, 0x00, 0x1F, 0xCF, 0xE0, 0x01, 0xFC,\n  0xFE, 0x00, 0x1F, 0xCF, 0xE0, 0x01, 0xFC, 0xFE, 0x00, 0x1F, 0xCF, 0xE0,\n  0x01, 0xFC, 0xFE, 0x00, 0x1F, 0xEF, 0xE0, 0x00, 0xFF, 0x00, 0xFF, 0xC0,\n  0x00, 0x3F, 0xFF, 0x80, 0x0F, 0xFF, 0xFE, 0x01, 0xFF, 0xFF, 0xF0, 0x3F,\n  0xFF, 0xFF, 0x87, 0xFF, 0xFF, 0xFC, 0x7F, 0xC0, 0xFF, 0xCF, 0xF0, 0x03,\n  0xFE, 0xFE, 0x00, 0x1F, 0xEF, 0xE0, 0x00, 0xFE, 0xFE, 0x00, 0x0F, 0xEF,\n  0xE0, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x0F, 0xFC, 0x00, 0x00, 0x7F, 0xFC,\n  0x00, 0x07, 0xFF, 0xFE, 0x00, 0x3F, 0xFF, 0xFC, 0x01, 0xFF, 0xFF, 0xF0,\n  0x07, 0xFF, 0xFF, 0xC0, 0x0F, 0xFF, 0xFE, 0x00, 0x07, 0xFF, 0xE0, 0x00,\n  0x03, 0xFF, 0x00, 0x00, 0x0F, 0xF0, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x07,\n  0xFF, 0xE0, 0x00, 0x7F, 0xFE, 0x00, 0x07, 0xFF, 0xE0, 0x00, 0xFF, 0xFF,\n  0x00, 0x0F, 0xE7, 0xFC, 0x03, 0xFE, 0x7F, 0xFF, 0xFF, 0xE3, 0xFF, 0xFF,\n  0xFC, 0x1F, 0xFF, 0xFF, 0x80, 0xFF, 0xFF, 0xF0, 0x03, 0xFF, 0xFC, 0x00,\n  0x07, 0xFE, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0,\n  0x0F, 0xE0, 0x00, 0x01, 0xFC, 0x00, 0x00, 0x3F, 0x80, 0x00, 0x07, 0xF0,\n  0x00, 0x00, 0xFE, 0x00, 0x00, 0x1F, 0xC0, 0x00, 0x03, 0xF8, 0x00, 0x00,\n  0x7F, 0x00, 0x00, 0x0F, 0xE0, 0x00, 0x01, 0xFC, 0x00, 0x00, 0x3F, 0x80,\n  0x00, 0x07, 0xF0, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x1F, 0xC0, 0x00, 0x03,\n  0xF8, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x0F, 0xE0, 0x00, 0x01, 0xFC, 0x00,\n  0x00, 0x3F, 0x80, 0x00, 0x07, 0xF0, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x1F,\n  0xC0, 0x00, 0x03, 0xF8, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x0F, 0xE0, 0x00,\n  0x01, 0xFC, 0x00, 0x00, 0x3F, 0x80, 0x00, 0x07, 0xF0, 0x00, 0xFE, 0x00,\n  0x0F, 0xFF, 0xC0, 0x01, 0xFF, 0xF8, 0x00, 0x3F, 0xFF, 0x00, 0x07, 0xFF,\n  0xE0, 0x00, 0xFF, 0xFC, 0x00, 0x1F, 0xFF, 0x80, 0x03, 0xFF, 0xF0, 0x00,\n  0x7F, 0xFE, 0x00, 0x0F, 0xFF, 0xC0, 0x01, 0xFF, 0xF8, 0x00, 0x3F, 0xFF,\n  0x00, 0x07, 0xFF, 0xE0, 0x00, 0xFF, 0xFC, 0x00, 0x1F, 0xFF, 0x80, 0x03,\n  0xFF, 0xF0, 0x00, 0x7F, 0xFE, 0x00, 0x0F, 0xFF, 0xC0, 0x01, 0xFF, 0xF8,\n  0x00, 0x3F, 0xFF, 0x00, 0x07, 0xFF, 0xE0, 0x00, 0xFF, 0xFC, 0x00, 0x1F,\n  0xFF, 0x80, 0x03, 0xFF, 0xF0, 0x00, 0x7F, 0xFE, 0x00, 0x0F, 0xFF, 0xC0,\n  0x01, 0xFF, 0xFC, 0x00, 0x7F, 0xBF, 0xC0, 0x1F, 0xE7, 0xFC, 0x07, 0xFC,\n  0x7F, 0xFF, 0xFF, 0x0F, 0xFF, 0xFF, 0xE0, 0xFF, 0xFF, 0xF8, 0x0F, 0xFF,\n  0xFE, 0x00, 0x7F, 0xFF, 0x00, 0x01, 0xFF, 0x00, 0x00, 0xFE, 0x00, 0x03,\n  0xFF, 0xF0, 0x00, 0x1F, 0xDF, 0xC0, 0x01, 0xFC, 0xFE, 0x00, 0x0F, 0xE7,\n  0xF0, 0x00, 0x7F, 0x1F, 0xC0, 0x03, 0xF0, 0xFE, 0x00, 0x3F, 0x87, 0xF0,\n  0x01, 0xFC, 0x1F, 0xC0, 0x0F, 0xC0, 0xFE, 0x00, 0xFE, 0x03, 0xF0, 0x07,\n  0xF0, 0x1F, 0x80, 0x3F, 0x00, 0xFE, 0x03, 0xF8, 0x03, 0xF0, 0x1F, 0xC0,\n  0x1F, 0x80, 0xFC, 0x00, 0xFE, 0x07, 0xE0, 0x03, 0xF0, 0x7F, 0x00, 0x1F,\n  0x83, 0xF0, 0x00, 0xFE, 0x1F, 0x80, 0x03, 0xF1, 0xF8, 0x00, 0x1F, 0x8F,\n  0xC0, 0x00, 0xFC, 0x7E, 0x00, 0x03, 0xF3, 0xE0, 0x00, 0x1F, 0xBF, 0x00,\n  0x00, 0xFD, 0xF8, 0x00, 0x03, 0xFF, 0x80, 0x00, 0x1F, 0xFC, 0x00, 0x00,\n  0xFF, 0xE0, 0x00, 0x03, 0xFE, 0x00, 0x00, 0x1F, 0xF0, 0x00, 0x00, 0xFF,\n  0x80, 0x00, 0x03, 0xF8, 0x00, 0x00, 0x1F, 0xC0, 0x00, 0x00, 0xFE, 0x00,\n  0x00, 0xFF, 0x00, 0x3F, 0x80, 0x1F, 0xFF, 0xE0, 0x07, 0xF0, 0x03, 0xFD,\n  0xFC, 0x01, 0xFE, 0x00, 0x7F, 0x3F, 0x80, 0x3F, 0xE0, 0x0F, 0xE7, 0xF0,\n  0x07, 0xFC, 0x01, 0xFC, 0x7F, 0x00, 0xFF, 0x80, 0x7F, 0x8F, 0xE0, 0x1F,\n  0xF0, 0x0F, 0xE1, 0xFC, 0x07, 0xFF, 0x01, 0xFC, 0x3F, 0x80, 0xFB, 0xE0,\n  0x3F, 0x83, 0xF0, 0x1F, 0x7C, 0x07, 0xE0, 0x7F, 0x03, 0xEF, 0x81, 0xFC,\n  0x0F, 0xE0, 0x7D, 0xF0, 0x3F, 0x80, 0xFC, 0x1F, 0x9F, 0x07, 0xF0, 0x1F,\n  0x83, 0xE3, 0xE0, 0xFC, 0x03, 0xF0, 0x7C, 0x7C, 0x1F, 0x80, 0x7F, 0x0F,\n  0x8F, 0x87, 0xF0, 0x07, 0xE1, 0xF0, 0xF8, 0xFC, 0x00, 0xFC, 0x7E, 0x1F,\n  0x1F, 0x80, 0x1F, 0x8F, 0x83, 0xE3, 0xF0, 0x01, 0xF9, 0xF0, 0x7C, 0x7E,\n  0x00, 0x3F, 0x3E, 0x0F, 0x9F, 0x80, 0x07, 0xE7, 0xC0, 0xFB, 0xF0, 0x00,\n  0xFD, 0xF0, 0x1F, 0x7E, 0x00, 0x0F, 0xBE, 0x03, 0xEF, 0xC0, 0x01, 0xFF,\n  0xC0, 0x7D, 0xF0, 0x00, 0x3F, 0xF8, 0x0F, 0xFE, 0x00, 0x03, 0xFF, 0x00,\n  0xFF, 0xC0, 0x00, 0x7F, 0xC0, 0x1F, 0xF0, 0x00, 0x0F, 0xF8, 0x03, 0xFE,\n  0x00, 0x01, 0xFF, 0x00, 0x7F, 0xC0, 0x00, 0x1F, 0xE0, 0x07, 0xF8, 0x00,\n  0x03, 0xFC, 0x00, 0xFE, 0x00, 0x00, 0x7F, 0x00, 0x1F, 0xC0, 0x00, 0x07,\n  0xE0, 0x03, 0xF8, 0x00, 0x7F, 0x80, 0x07, 0xF9, 0xFF, 0x00, 0x3F, 0xC3,\n  0xFC, 0x00, 0xFF, 0x07, 0xF8, 0x07, 0xF8, 0x1F, 0xE0, 0x1F, 0xC0, 0x3F,\n  0xC0, 0xFF, 0x00, 0xFF, 0x07, 0xF8, 0x01, 0xFE, 0x1F, 0xE0, 0x03, 0xF8,\n  0xFF, 0x00, 0x0F, 0xF3, 0xF8, 0x00, 0x1F, 0xDF, 0xE0, 0x00, 0x3F, 0xFF,\n  0x00, 0x00, 0xFF, 0xF8, 0x00, 0x01, 0xFF, 0xE0, 0x00, 0x07, 0xFF, 0x00,\n  0x00, 0x0F, 0xF8, 0x00, 0x00, 0x1F, 0xE0, 0x00, 0x00, 0xFF, 0x80, 0x00,\n  0x03, 0xFF, 0x00, 0x00, 0x1F, 0xFC, 0x00, 0x00, 0x7F, 0xF8, 0x00, 0x03,\n  0xFF, 0xF0, 0x00, 0x1F, 0xFF, 0xC0, 0x00, 0x7F, 0x7F, 0x80, 0x03, 0xF8,\n  0xFF, 0x00, 0x1F, 0xE1, 0xFC, 0x00, 0x7F, 0x07, 0xF8, 0x03, 0xFC, 0x0F,\n  0xF0, 0x1F, 0xE0, 0x3F, 0xC0, 0x7F, 0x80, 0x7F, 0x83, 0xFC, 0x01, 0xFE,\n  0x0F, 0xF0, 0x03, 0xFC, 0x7F, 0x80, 0x0F, 0xFB, 0xFE, 0x00, 0x1F, 0xE0,\n  0xFF, 0x00, 0x07, 0xFF, 0xF8, 0x00, 0x7F, 0x9F, 0xE0, 0x03, 0xFC, 0xFF,\n  0x00, 0x3F, 0xC3, 0xFC, 0x01, 0xFE, 0x0F, 0xE0, 0x0F, 0xE0, 0x7F, 0x00,\n  0xFF, 0x01, 0xFC, 0x07, 0xF0, 0x0F, 0xE0, 0x7F, 0x80, 0x3F, 0x83, 0xF8,\n  0x01, 0xFC, 0x3F, 0xC0, 0x07, 0xF1, 0xFC, 0x00, 0x3F, 0x8F, 0xE0, 0x00,\n  0xFE, 0xFE, 0x00, 0x07, 0xF7, 0xF0, 0x00, 0x1F, 0xFF, 0x00, 0x00, 0xFF,\n  0xF8, 0x00, 0x03, 0xFF, 0x80, 0x00, 0x1F, 0xF8, 0x00, 0x00, 0x7F, 0xC0,\n  0x00, 0x01, 0xFC, 0x00, 0x00, 0x0F, 0xE0, 0x00, 0x00, 0x7F, 0x00, 0x00,\n  0x03, 0xF8, 0x00, 0x00, 0x1F, 0xC0, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x07,\n  0xF0, 0x00, 0x00, 0x3F, 0x80, 0x00, 0x01, 0xFC, 0x00, 0x00, 0x0F, 0xE0,\n  0x00, 0x00, 0x7F, 0x00, 0x00, 0x03, 0xF8, 0x00, 0x00, 0x1F, 0xC0, 0x00,\n  0x00, 0xFE, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0,\n  0x00, 0x03, 0xFC, 0x00, 0x01, 0xFE, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x7F,\n  0x80, 0x00, 0x3F, 0xE0, 0x00, 0x0F, 0xF0, 0x00, 0x07, 0xF8, 0x00, 0x03,\n  0xFC, 0x00, 0x01, 0xFE, 0x00, 0x00, 0xFF, 0x80, 0x00, 0x3F, 0xC0, 0x00,\n  0x1F, 0xE0, 0x00, 0x0F, 0xF0, 0x00, 0x07, 0xF8, 0x00, 0x03, 0xFE, 0x00,\n  0x00, 0xFF, 0x00, 0x00, 0x7F, 0x80, 0x00, 0x3F, 0xC0, 0x00, 0x1F, 0xE0,\n  0x00, 0x0F, 0xF8, 0x00, 0x03, 0xFC, 0x00, 0x01, 0xFE, 0x00, 0x00, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFC, 0x3F, 0x87, 0xF0, 0xFE, 0x1F, 0xC3, 0xF8, 0x7F, 0x0F,\n  0xE1, 0xFC, 0x3F, 0x87, 0xF0, 0xFE, 0x1F, 0xC3, 0xF8, 0x7F, 0x0F, 0xE1,\n  0xFC, 0x3F, 0x87, 0xF0, 0xFE, 0x1F, 0xC3, 0xF8, 0x7F, 0x0F, 0xE1, 0xFC,\n  0x3F, 0x87, 0xF0, 0xFE, 0x1F, 0xC3, 0xF8, 0x7F, 0x0F, 0xE1, 0xFC, 0x3F,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x80, 0xE0, 0x03, 0xC0, 0x07, 0x00,\n  0x1C, 0x00, 0x78, 0x00, 0xE0, 0x03, 0x80, 0x0F, 0x00, 0x1C, 0x00, 0x70,\n  0x01, 0xE0, 0x03, 0x80, 0x0E, 0x00, 0x38, 0x00, 0x70, 0x01, 0xC0, 0x07,\n  0x00, 0x0E, 0x00, 0x38, 0x00, 0xE0, 0x01, 0xC0, 0x07, 0x00, 0x1C, 0x00,\n  0x78, 0x00, 0xE0, 0x03, 0x80, 0x0F, 0x00, 0x1C, 0x00, 0x70, 0x01, 0xE0,\n  0x03, 0x80, 0x0E, 0x00, 0x3C, 0x00, 0x70, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFE, 0x1F, 0xC3, 0xF8, 0x7F, 0x0F, 0xE1, 0xFC, 0x3F, 0x87, 0xF0,\n  0xFE, 0x1F, 0xC3, 0xF8, 0x7F, 0x0F, 0xE1, 0xFC, 0x3F, 0x87, 0xF0, 0xFE,\n  0x1F, 0xC3, 0xF8, 0x7F, 0x0F, 0xE1, 0xFC, 0x3F, 0x87, 0xF0, 0xFE, 0x1F,\n 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0xFF, 0xFC, 0x7F, 0xFF, 0xFC, 0x3F, 0xFD, 0xFE,\n  0x1F, 0xF0, 0xFF, 0x07, 0xE0, 0x00, 0xFE, 0x00, 0x00, 0x7F, 0x00, 0x00,\n  0x3F, 0x80, 0x00, 0x1F, 0xC0, 0x00, 0x0F, 0xE0, 0x00, 0x07, 0xF0, 0x00,\n  0x03, 0xF8, 0x00, 0x01, 0xFC, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x7F, 0x0F,\n  0xC0, 0x3F, 0x9F, 0xF8, 0x1F, 0xDF, 0xFF, 0x0F, 0xFF, 0xFF, 0xC7, 0xFF,\n  0xFF, 0xE3, 0xFF, 0xFF, 0xF9, 0xFF, 0x83, 0xFE, 0xFF, 0x80, 0xFF, 0x7F,\n  0x80, 0x3F, 0xBF, 0xC0, 0x1F, 0xFF, 0xC0, 0x07, 0xFF, 0xE0, 0x03, 0xFF,\n  0xF0, 0x01, 0xFF, 0xF8, 0x00, 0xFF, 0xFC, 0x00, 0x7F, 0xFE, 0x00, 0x3F,\n  0xFF, 0x80, 0x3F, 0xFF, 0xC0, 0x1F, 0xDF, 0xF0, 0x1F, 0xEF, 0xFC, 0x1F,\n  0xF7, 0xFF, 0xFF, 0xF3, 0xFF, 0xFF, 0xF1, 0xFF, 0xFF, 0xF8, 0xFE, 0xFF,\n  0xF8, 0x7F, 0x3F, 0xF0, 0x00, 0x07, 0xE0, 0x00, 0x00, 0xFF, 0x00, 0x07,\n  0xFF, 0xC0, 0x3F, 0xFF, 0xC0, 0xFF, 0xFF, 0xC3, 0xFF, 0xFF, 0xC7, 0xFF,\n  0xFF, 0x9F, 0xF0, 0x7F, 0xBF, 0xC0, 0x7F, 0x7F, 0x00, 0x7F, 0xFC, 0x00,\n  0x03, 0xF8, 0x00, 0x07, 0xF0, 0x00, 0x0F, 0xE0, 0x00, 0x1F, 0xC0, 0x00,\n  0x3F, 0x80, 0x00, 0x7F, 0x00, 0x00, 0xFE, 0x00, 0x00, 0xFE, 0x00, 0xFD,\n  0xFE, 0x03, 0xFB, 0xFE, 0x0F, 0xF3, 0xFF, 0xFF, 0xC7, 0xFF, 0xFF, 0x87,\n  0xFF, 0xFE, 0x07, 0xFF, 0xF8, 0x03, 0xFF, 0xE0, 0x01, 0xFE, 0x00, 0x00,\n  0x00, 0x3F, 0x80, 0x00, 0x1F, 0xC0, 0x00, 0x0F, 0xE0, 0x00, 0x07, 0xF0,\n  0x00, 0x03, 0xF8, 0x00, 0x01, 0xFC, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x7F,\n  0x00, 0x00, 0x3F, 0x80, 0x7E, 0x1F, 0xC0, 0xFF, 0xCF, 0xE1, 0xFF, 0xF7,\n  0xF1, 0xFF, 0xFF, 0xF8, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF, 0xFE, 0xFF, 0x83,\n  0xFF, 0x7F, 0x80, 0xFF, 0xBF, 0x80, 0x3F, 0xFF, 0xC0, 0x1F, 0xFF, 0xC0,\n  0x07, 0xFF, 0xE0, 0x03, 0xFF, 0xF0, 0x01, 0xFF, 0xF8, 0x00, 0xFF, 0xFC,\n  0x00, 0x7F, 0xFE, 0x00, 0x3F, 0xFF, 0x80, 0x3F, 0xDF, 0xC0, 0x1F, 0xEF,\n  0xF0, 0x1F, 0xF7, 0xFC, 0x1F, 0xF9, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF, 0xFE,\n  0x3F, 0xFF, 0xFF, 0x0F, 0xFF, 0xBF, 0x81, 0xFF, 0x9F, 0xC0, 0x3F, 0x00,\n  0x00, 0x00, 0xFE, 0x00, 0x03, 0xFF, 0x80, 0x0F, 0xFF, 0xE0, 0x1F, 0xFF,\n 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0xFE, 0x00, 0x7F, 0xFE, 0x00, 0x7F, 0xFE, 0x00,\n  0x7F, 0xFE, 0x00, 0x7F, 0xFE, 0x00, 0x7F, 0xFE, 0x00, 0xFF, 0xFF, 0x00,\n  0xFF, 0x7F, 0x81, 0xFF, 0x7F, 0xC3, 0xFF, 0x3F, 0xFF, 0xFF, 0x3F, 0xFF,\n  0xFF, 0x1F, 0xFF, 0xFF, 0x0F, 0xFF, 0x7F, 0x07, 0xFE, 0x7F, 0x01, 0xF8,\n  0x7F, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x7F, 0x7F, 0x00,\n  0xFF, 0x7F, 0x01, 0xFE, 0x7F, 0xC3, 0xFE, 0x3F, 0xFF, 0xFC, 0x1F, 0xFF,\n  0xF8, 0x0F, 0xFF, 0xE0, 0x01, 0xFF, 0x00, 0xFE, 0x00, 0x01, 0xFC, 0x00,\n  0x03, 0xF8, 0x00, 0x07, 0xF0, 0x00, 0x0F, 0xE0, 0x00, 0x1F, 0xC0, 0x00,\n  0x3F, 0x80, 0x00, 0x7F, 0x00, 0x00, 0xFE, 0x00, 0x01, 0xFC, 0x3F, 0x83,\n  0xF8, 0xFF, 0xC7, 0xF7, 0xFF, 0xCF, 0xEF, 0xFF, 0xDF, 0xFF, 0xFF, 0xBF,\n  0xFF, 0xFF, 0xFF, 0xE1, 0xFF, 0xFF, 0x01, 0xFF, 0xFE, 0x01, 0xFF, 0xF8,\n  0x03, 0xFF, 0xF0, 0x07, 0xFF, 0xE0, 0x0F, 0xFF, 0xC0, 0x1F, 0xFF, 0x80,\n  0x3F, 0xFF, 0x00, 0x7F, 0xFE, 0x00, 0xFF, 0xFC, 0x01, 0xFF, 0xF8, 0x03,\n  0xFF, 0xF0, 0x07, 0xFF, 0xE0, 0x0F, 0xFF, 0xC0, 0x1F, 0xFF, 0x80, 0x3F,\n  0xFF, 0x00, 0x7F, 0xFE, 0x00, 0xFF, 0xFC, 0x01, 0xFC, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xC0, 0x00, 0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFC, 0x1F, 0xC7, 0xF1, 0xFC, 0x7F, 0x1F, 0xC7, 0xF0, 0x00,\n  0x00, 0x00, 0x07, 0xF1, 0xFC, 0x7F, 0x1F, 0xC7, 0xF1, 0xFC, 0x7F, 0x1F,\n  0xC7, 0xF1, 0xFC, 0x7F, 0x1F, 0xC7, 0xF1, 0xFC, 0x7F, 0x1F, 0xC7, 0xF1,\n  0xFC, 0x7F, 0x1F, 0xC7, 0xF1, 0xFC, 0x7F, 0x1F, 0xC7, 0xF1, 0xFC, 0x7F,\n  0x1F, 0xC7, 0xF1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFB, 0xFE, 0xFE, 0x00,\n  0xFE, 0x00, 0x01, 0xFC, 0x00, 0x03, 0xF8, 0x00, 0x07, 0xF0, 0x00, 0x0F,\n  0xE0, 0x00, 0x1F, 0xC0, 0x00, 0x3F, 0x80, 0x00, 0x7F, 0x00, 0x00, 0xFE,\n  0x00, 0x01, 0xFC, 0x03, 0xFB, 0xF8, 0x0F, 0xE7, 0xF0, 0x3F, 0xCF, 0xE0,\n  0xFF, 0x1F, 0xC3, 0xFC, 0x3F, 0x87, 0xF0, 0x7F, 0x1F, 0xC0, 0xFE, 0x7F,\n  0x01, 0xFD, 0xFC, 0x03, 0xFF, 0xF0, 0x07, 0xFF, 0xF0, 0x0F, 0xFF, 0xE0,\n  0x1F, 0xFF, 0xE0, 0x3F, 0xFF, 0xE0, 0x7F, 0xDF, 0xC0, 0xFF, 0x3F, 0xC1,\n  0xFC, 0x3F, 0x83, 0xF8, 0x3F, 0x87, 0xF0, 0x7F, 0x8F, 0xE0, 0x7F, 0x1F,\n  0xC0, 0xFF, 0x3F, 0x80, 0xFE, 0x7F, 0x01, 0xFE, 0xFE, 0x01, 0xFD, 0xFC,\n  0x03, 0xFC, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFE, 0x1F, 0x80, 0x7E,\n  0x0F, 0xE7, 0xFE, 0x1F, 0xF8, 0xFE, 0xFF, 0xF3, 0xFF, 0xCF, 0xFF, 0xFF,\n  0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xEF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0x83, 0xFF, 0x0F, 0xFF, 0xF0, 0x1F, 0xE0, 0x7F, 0xFE, 0x01, 0xFC, 0x07,\n  0xFF, 0xE0, 0x1F, 0xC0, 0x7F, 0xFE, 0x01, 0xFC, 0x07, 0xFF, 0xE0, 0x1F,\n  0xC0, 0x7F, 0xFE, 0x01, 0xFC, 0x07, 0xFF, 0xE0, 0x1F, 0xC0, 0x7F, 0xFE,\n  0x01, 0xFC, 0x07, 0xFF, 0xE0, 0x1F, 0xC0, 0x7F, 0xFE, 0x01, 0xFC, 0x07,\n  0xFF, 0xE0, 0x1F, 0xC0, 0x7F, 0xFE, 0x01, 0xFC, 0x07, 0xFF, 0xE0, 0x1F,\n  0xC0, 0x7F, 0xFE, 0x01, 0xFC, 0x07, 0xFF, 0xE0, 0x1F, 0xC0, 0x7F, 0xFE,\n  0x01, 0xFC, 0x07, 0xFF, 0xE0, 0x1F, 0xC0, 0x7F, 0xFE, 0x01, 0xFC, 0x07,\n  0xF0, 0xFE, 0x1F, 0xC1, 0xFC, 0xFF, 0xE3, 0xFB, 0xFF, 0xE7, 0xFF, 0xFF,\n  0xEF, 0xFF, 0xFF, 0xDF, 0xFF, 0xFF, 0xFF, 0xF0, 0xFF, 0xFF, 0x80, 0xFF,\n  0xFE, 0x00, 0xFF, 0xFC, 0x01, 0xFF, 0xF8, 0x03, 0xFF, 0xF0, 0x07, 0xFF,\n  0xE0, 0x0F, 0xFF, 0xC0, 0x1F, 0xFF, 0x80, 0x3F, 0xFF, 0x00, 0x7F, 0xFE,\n  0x00, 0xFF, 0xFC, 0x01, 0xFF, 0xF8, 0x03, 0xFF, 0xF0, 0x07, 0xFF, 0xE0,\n  0x0F, 0xFF, 0xC0, 0x1F, 0xFF, 0x80, 0x3F, 0xFF, 0x00, 0x7F, 0xFE, 0x00,\n  0xFE, 0x00, 0x7F, 0x80, 0x01, 0xFF, 0xF0, 0x01, 0xFF, 0xFE, 0x01, 0xFF,\n  0xFF, 0x81, 0xFF, 0xFF, 0xE1, 0xFF, 0xFF, 0xF1, 0xFF, 0x07, 0xFC, 0xFF,\n  0x01, 0xFE, 0x7F, 0x00, 0x7F, 0x7F, 0x80, 0x3F, 0xFF, 0x80, 0x0F, 0xFF,\n  0xC0, 0x07, 0xFF, 0xE0, 0x03, 0xFF, 0xF0, 0x01, 0xFF, 0xF8, 0x00, 0xFF,\n  0xFC, 0x00, 0x7F, 0xFF, 0x00, 0x7F, 0xBF, 0x80, 0x3F, 0x9F, 0xE0, 0x3F,\n  0xCF, 0xF8, 0x3F, 0xE3, 0xFF, 0xFF, 0xE0, 0xFF, 0xFF, 0xF0, 0x3F, 0xFF,\n  0xF0, 0x0F, 0xFF, 0xF0, 0x03, 0xFF, 0xE0, 0x00, 0x3F, 0xC0, 0x00, 0xFE,\n  0x1F, 0x80, 0x7F, 0x3F, 0xF0, 0x3F, 0xBF, 0xFE, 0x1F, 0xDF, 0xFF, 0x8F,\n  0xFF, 0xFF, 0xC7, 0xFF, 0xFF, 0xF3, 0xFF, 0x07, 0xFD, 0xFF, 0x01, 0xFE,\n  0xFF, 0x00, 0x7F, 0x7F, 0x80, 0x3F, 0xFF, 0x80, 0x0F, 0xFF, 0xC0, 0x07,\n  0xFF, 0xE0, 0x03, 0xFF, 0xF0, 0x01, 0xFF, 0xF8, 0x00, 0xFF, 0xFC, 0x00,\n  0x7F, 0xFF, 0x00, 0x7F, 0xFF, 0x80, 0x3F, 0xBF, 0xE0, 0x3F, 0xDF, 0xF8,\n  0x3F, 0xCF, 0xFF, 0xFF, 0xE7, 0xFF, 0xFF, 0xE3, 0xFB, 0xFF, 0xE1, 0xFD,\n  0xFF, 0xF0, 0xFE, 0x7F, 0xE0, 0x7F, 0x0F, 0xC0, 0x3F, 0x80, 0x00, 0x1F,\n  0xC0, 0x00, 0x0F, 0xE0, 0x00, 0x07, 0xF0, 0x00, 0x03, 0xF8, 0x00, 0x01,\n  0xFC, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x3F, 0x80, 0x00,\n  0x1F, 0xC0, 0x00, 0x00, 0x00, 0xFC, 0x3F, 0x81, 0xFF, 0x9F, 0xC3, 0xFF,\n  0xEF, 0xE1, 0xFF, 0xF7, 0xF1, 0xFF, 0xFF, 0xF9, 0xFF, 0xFF, 0xFD, 0xFF,\n  0x07, 0xFE, 0xFF, 0x01, 0xFF, 0x7F, 0x00, 0x7F, 0xFF, 0x80, 0x3F, 0xFF,\n  0x80, 0x0F, 0xFF, 0xC0, 0x07, 0xFF, 0xE0, 0x03, 0xFF, 0xF0, 0x01, 0xFF,\n  0xF8, 0x00, 0xFF, 0xFC, 0x00, 0x7F, 0xFF, 0x00, 0x7F, 0xBF, 0x80, 0x3F,\n  0xDF, 0xE0, 0x3F, 0xEF, 0xF8, 0x3F, 0xF3, 0xFF, 0xFF, 0xF8, 0xFF, 0xFF,\n  0xFC, 0x7F, 0xFE, 0xFE, 0x1F, 0xFF, 0x7F, 0x03, 0xFF, 0x3F, 0x80, 0x7E,\n  0x1F, 0xC0, 0x00, 0x0F, 0xE0, 0x00, 0x07, 0xF0, 0x00, 0x03, 0xF8, 0x00,\n  0x01, 0xFC, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x3F, 0x80,\n  0x00, 0x1F, 0xC0, 0x00, 0x0F, 0xE0, 0x00, 0x07, 0xF0, 0xFE, 0x1F, 0xFC,\n  0x7F, 0xFB, 0xFF, 0xF7, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0x7F, 0x80,\n  0xFF, 0x01, 0xFC, 0x03, 0xF8, 0x07, 0xF0, 0x0F, 0xE0, 0x1F, 0xC0, 0x3F,\n  0x80, 0x7F, 0x00, 0xFE, 0x01, 0xFC, 0x03, 0xF8, 0x07, 0xF0, 0x0F, 0xE0,\n  0x1F, 0xC0, 0x3F, 0x80, 0x7F, 0x00, 0xFE, 0x00, 0x00, 0xFF, 0x00, 0x07,\n  0xFF, 0xE0, 0x0F, 0xFF, 0xF8, 0x1F, 0xFF, 0xFC, 0x3F, 0xFF, 0xFC, 0x7F,\n  0x81, 0xFE, 0x7F, 0x00, 0xFE, 0x7F, 0x00, 0xFE, 0x7F, 0xC0, 0x00, 0x7F,\n  0xFC, 0x00, 0x7F, 0xFF, 0x80, 0x3F, 0xFF, 0xF0, 0x1F, 0xFF, 0xFC, 0x07,\n  0xFF, 0xFE, 0x00, 0x7F, 0xFE, 0x00, 0x0F, 0xFF, 0x00, 0x01, 0xFF, 0x00,\n  0x00, 0x7F, 0xFE, 0x00, 0x7F, 0x7F, 0x00, 0x7F, 0x7F, 0x81, 0xFE, 0x7F,\n  0xFF, 0xFE, 0x3F, 0xFF, 0xFC, 0x1F, 0xFF, 0xF8, 0x0F, 0xFF, 0xF0, 0x01,\n  0xFF, 0x80, 0x3F, 0x83, 0xF8, 0x3F, 0x83, 0xF8, 0x3F, 0x83, 0xF8, 0x3F,\n  0x8F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF3, 0xF8, 0x3F, 0x83, 0xF8, 0x3F,\n  0x83, 0xF8, 0x3F, 0x83, 0xF8, 0x3F, 0x83, 0xF8, 0x3F, 0x83, 0xF8, 0x3F,\n  0x83, 0xF8, 0x3F, 0x83, 0xF8, 0x3F, 0x83, 0xFF, 0x3F, 0xF1, 0xFF, 0x0F,\n  0xF0, 0x7F, 0xFE, 0x00, 0xFF, 0xFC, 0x01, 0xFF, 0xF8, 0x03, 0xFF, 0xF0,\n  0x07, 0xFF, 0xE0, 0x0F, 0xFF, 0xC0, 0x1F, 0xFF, 0x80, 0x3F, 0xFF, 0x00,\n  0x7F, 0xFE, 0x00, 0xFF, 0xFC, 0x01, 0xFF, 0xF8, 0x03, 0xFF, 0xF0, 0x07,\n  0xFF, 0xE0, 0x0F, 0xFF, 0xC0, 0x1F, 0xFF, 0x80, 0x3F, 0xFF, 0x00, 0x7F,\n  0xFE, 0x00, 0xFF, 0xFC, 0x03, 0xFF, 0xFC, 0x07, 0xFF, 0xFC, 0x3F, 0xFF,\n  0xFF, 0xFF, 0xEF, 0xFF, 0xFF, 0xDF, 0xFF, 0xBF, 0x9F, 0xFF, 0x7F, 0x1F,\n  0xFC, 0xFE, 0x0F, 0xE0, 0x00, 0x7F, 0x00, 0x3F, 0xBF, 0x80, 0x1F, 0x9F,\n  0xC0, 0x1F, 0xC7, 0xE0, 0x0F, 0xE3, 0xF8, 0x07, 0xE1, 0xFC, 0x07, 0xF0,\n  0x7E, 0x03, 0xF8, 0x3F, 0x81, 0xF8, 0x1F, 0xC0, 0xFC, 0x07, 0xE0, 0xFE,\n  0x03, 0xF8, 0x7E, 0x00, 0xFC, 0x3F, 0x00, 0x7E, 0x1F, 0x80, 0x3F, 0x1F,\n  0x80, 0x0F, 0xCF, 0xC0, 0x07, 0xE7, 0xE0, 0x03, 0xF7, 0xE0, 0x00, 0xFF,\n  0xF0, 0x00, 0x7F, 0xF8, 0x00, 0x3F, 0xF8, 0x00, 0x0F, 0xFC, 0x00, 0x07,\n  0xFE, 0x00, 0x03, 0xFE, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x7F, 0x00, 0x00,\n  0xFC, 0x03, 0xF8, 0x0F, 0xFF, 0xC0, 0x7F, 0x01, 0xFF, 0xF8, 0x0F, 0xE0,\n  0x3F, 0x3F, 0x03, 0xFE, 0x07, 0xE7, 0xE0, 0x7F, 0xC1, 0xFC, 0xFE, 0x0F,\n  0xF8, 0x3F, 0x9F, 0xC1, 0xFF, 0x07, 0xE1, 0xF8, 0x3D, 0xE0, 0xFC, 0x3F,\n  0x0F, 0xBE, 0x3F, 0x87, 0xF1, 0xF7, 0xC7, 0xE0, 0x7E, 0x3E, 0xF8, 0xFC,\n  0x0F, 0xC7, 0xDF, 0x1F, 0x81, 0xF9, 0xF1, 0xE3, 0xF0, 0x3F, 0x3E, 0x3E,\n  0xFC, 0x03, 0xF7, 0xC7, 0xDF, 0x80, 0x7E, 0xF8, 0xFB, 0xF0, 0x0F, 0xDE,\n  0x1F, 0x7C, 0x00, 0xFF, 0xC1, 0xFF, 0x80, 0x1F, 0xF8, 0x3F, 0xF0, 0x03,\n  0xFF, 0x07, 0xFE, 0x00, 0x7F, 0xC0, 0xFF, 0x80, 0x07, 0xF8, 0x1F, 0xF0,\n  0x00, 0xFF, 0x01, 0xFE, 0x00, 0x1F, 0xE0, 0x3F, 0x80, 0x01, 0xFC, 0x07,\n  0xF0, 0x00, 0xFF, 0x00, 0xFF, 0x7F, 0x81, 0xFE, 0x3F, 0x81, 0xFC, 0x3F,\n  0xC3, 0xFC, 0x1F, 0xC3, 0xF8, 0x0F, 0xE7, 0xF0, 0x0F, 0xEF, 0xF0, 0x07,\n  0xFF, 0xE0, 0x03, 0xFF, 0xC0, 0x03, 0xFF, 0xC0, 0x01, 0xFF, 0x80, 0x00,\n  0xFF, 0x00, 0x00, 0xFF, 0x00, 0x01, 0xFF, 0x00, 0x01, 0xFF, 0x80, 0x03,\n  0xFF, 0xC0, 0x07, 0xFF, 0xC0, 0x07, 0xFF, 0xE0, 0x0F, 0xE7, 0xF0, 0x1F,\n  0xE7, 0xF0, 0x1F, 0xC3, 0xF8, 0x3F, 0xC3, 0xFC, 0x7F, 0x81, 0xFC, 0x7F,\n  0x01, 0xFE, 0xFF, 0x00, 0xFF, 0x7F, 0x00, 0x3F, 0xBF, 0x80, 0x1F, 0xDF,\n  0xC0, 0x0F, 0xC7, 0xF0, 0x07, 0xE3, 0xF8, 0x07, 0xF1, 0xFC, 0x03, 0xF0,\n  0x7F, 0x01, 0xF8, 0x3F, 0x81, 0xFC, 0x0F, 0xC0, 0xFC, 0x07, 0xF0, 0x7E,\n  0x03, 0xF8, 0x3F, 0x00, 0xFC, 0x3F, 0x00, 0x7E, 0x1F, 0x80, 0x3F, 0x8F,\n  0xC0, 0x0F, 0xCF, 0xC0, 0x07, 0xE7, 0xE0, 0x03, 0xFB, 0xF0, 0x00, 0xFD,\n  0xF0, 0x00, 0x7F, 0xF8, 0x00, 0x3F, 0xFC, 0x00, 0x0F, 0xFC, 0x00, 0x07,\n  0xFE, 0x00, 0x03, 0xFF, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x7F, 0x80, 0x00,\n  0x1F, 0xC0, 0x00, 0x0F, 0xC0, 0x00, 0x07, 0xE0, 0x00, 0x03, 0xF0, 0x00,\n  0x03, 0xF0, 0x00, 0x03, 0xF8, 0x00, 0x1F, 0xF8, 0x00, 0x0F, 0xFC, 0x00,\n  0x07, 0xFC, 0x00, 0x03, 0xFC, 0x00, 0x01, 0xF8, 0x00, 0x00, 0x7F, 0xFF,\n  0xFB, 0xFF, 0xFF, 0xDF, 0xFF, 0xFE, 0xFF, 0xFF, 0xF7, 0xFF, 0xFF, 0xBF,\n  0xFF, 0xFC, 0x00, 0x3F, 0xE0, 0x03, 0xFE, 0x00, 0x1F, 0xE0, 0x01, 0xFE,\n  0x00, 0x1F, 0xE0, 0x01, 0xFE, 0x00, 0x1F, 0xE0, 0x01, 0xFE, 0x00, 0x1F,\n  0xE0, 0x01, 0xFE, 0x00, 0x1F, 0xE0, 0x01, 0xFE, 0x00, 0x1F, 0xE0, 0x01,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xF8, 0x01, 0xF8, 0x1F, 0xC1, 0xFE, 0x0F, 0xF0, 0xFF,\n  0x87, 0xE0, 0x3E, 0x01, 0xF0, 0x0F, 0x80, 0x7C, 0x03, 0xE0, 0x1F, 0x00,\n  0xF8, 0x07, 0xC0, 0x3E, 0x01, 0xF0, 0x0F, 0x80, 0x7C, 0x03, 0xE0, 0x3F,\n  0x0F, 0xF0, 0x7F, 0x03, 0xF8, 0x1F, 0xE0, 0x1F, 0x80, 0x7C, 0x03, 0xE0,\n  0x1F, 0x00, 0xF8, 0x07, 0xC0, 0x3E, 0x01, 0xF0, 0x0F, 0x80, 0x7C, 0x03,\n  0xE0, 0x1F, 0x00, 0xF8, 0x07, 0xE0, 0x3F, 0xE0, 0xFF, 0x07, 0xF8, 0x1F,\n  0xC0, 0x7E, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFC, 0x07, 0xF0, 0x3F, 0xC1, 0xFE, 0x0F, 0xF8, 0x0F, 0xC0, 0x3E, 0x01,\n  0xF0, 0x0F, 0x80, 0x7C, 0x03, 0xE0, 0x1F, 0x00, 0xF8, 0x07, 0xC0, 0x3E,\n  0x01, 0xF0, 0x0F, 0x80, 0x7C, 0x03, 0xE0, 0x1F, 0x80, 0x7F, 0x81, 0xFC,\n  0x0F, 0xE0, 0xFF, 0x0F, 0xC0, 0x7C, 0x03, 0xE0, 0x1F, 0x00, 0xF8, 0x07,\n  0xC0, 0x3E, 0x01, 0xF0, 0x0F, 0x80, 0x7C, 0x03, 0xE0, 0x1F, 0x00, 0xF8,\n  0x0F, 0xC3, 0xFE, 0x1F, 0xE0, 0xFF, 0x07, 0xF0, 0x3F, 0x00, 0x1F, 0x00,\n  0x03, 0xFE, 0x00, 0x1F, 0xF8, 0x0F, 0xFF, 0xF0, 0xFF, 0x0F, 0xFF, 0xF0,\n  0x1F, 0xF8, 0x00, 0x7F, 0x80, 0x00, 0xF8 };\n\nconst GFXglyph FreeSansBold24pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,  13,    0,    1 },   // 0x20 ' '\n  {     0,   7,  34,  16,    5,  -33 },   // 0x21 '!'\n  {    30,  18,  12,  22,    2,  -33 },   // 0x22 '\"'\n  {    57,  26,  33,  26,    0,  -31 },   // 0x23 '#'\n  {   165,  25,  40,  26,    1,  -34 },   // 0x24 '$'\n  {   290,  39,  34,  42,    1,  -32 },   // 0x25 '%'\n  {   456,  30,  35,  34,    3,  -33 },   // 0x26 '&'\n  {   588,   7,  12,  12,    3,  -33 },   // 0x27 '''\n  {   599,  13,  44,  16,    2,  -33 },   // 0x28 '('\n  {   671,  13,  44,  16,    1,  -33 },   // 0x29 ')'\n  {   743,  15,  15,  18,    1,  -33 },   // 0x2A '*'\n  {   772,  23,  22,  27,    2,  -21 },   // 0x2B '+'\n  {   836,   7,  15,  12,    2,   -6 },   // 0x2C ','\n  {   850,  13,   6,  16,    1,  -15 },   // 0x2D '-'\n  {   860,   7,   7,  12,    2,   -6 },   // 0x2E '.'\n  {   867,  13,  34,  13,    0,  -32 },   // 0x2F '/'\n  {   923,  24,  35,  26,    1,  -33 },   // 0x30 '0'\n  {  1028,  14,  33,  26,    4,  -32 },   // 0x31 '1'\n  {  1086,  23,  34,  26,    2,  -33 },   // 0x32 '2'\n  {  1184,  23,  35,  26,    2,  -33 },   // 0x33 '3'\n  {  1285,  22,  33,  26,    2,  -32 },   // 0x34 '4'\n  {  1376,  23,  34,  26,    2,  -32 },   // 0x35 '5'\n  {  1474,  23,  35,  26,    2,  -33 },   // 0x36 '6'\n  {  1575,  23,  33,  26,    1,  -32 },   // 0x37 '7'\n  {  1670,  24,  35,  26,    1,  -33 },   // 0x38 '8'\n  {  1775,  24,  35,  26,    1,  -33 },   // 0x39 '9'\n  {  1880,   7,  25,  12,    2,  -24 },   // 0x3A ':'\n  {  1902,   7,  33,  12,    2,  -24 },   // 0x3B ';'\n  {  1931,  23,  23,  27,    2,  -22 },   // 0x3C '<'\n  {  1998,  23,  18,  27,    2,  -19 },   // 0x3D '='\n  {  2050,  23,  23,  27,    2,  -22 },   // 0x3E '>'\n  {  2117,  24,  35,  29,    3,  -34 },   // 0x3F '?'\n  {  2222,  43,  41,  46,    1,  -34 },   // 0x40 '@'\n  {  2443,  32,  34,  33,    0,  -33 },   // 0x41 'A'\n  {  2579,  27,  34,  33,    4,  -33 },   // 0x42 'B'\n  {  2694,  30,  36,  34,    2,  -34 },   // 0x43 'C'\n  {  2829,  28,  34,  34,    4,  -33 },   // 0x44 'D'\n  {  2948,  25,  34,  31,    4,  -33 },   // 0x45 'E'\n  {  3055,  24,  34,  30,    4,  -33 },   // 0x46 'F'\n  {  3157,  31,  36,  36,    2,  -34 },   // 0x47 'G'\n  {  3297,  27,  34,  35,    4,  -33 },   // 0x48 'H'\n  {  3412,   7,  34,  15,    4,  -33 },   // 0x49 'I'\n  {  3442,  22,  35,  27,    1,  -33 },   // 0x4A 'J'\n  {  3539,  30,  34,  34,    4,  -33 },   // 0x4B 'K'\n  {  3667,  23,  34,  29,    4,  -33 },   // 0x4C 'L'\n  {  3765,  33,  34,  41,    4,  -33 },   // 0x4D 'M'\n  {  3906,  28,  34,  35,    4,  -33 },   // 0x4E 'N'\n  {  4025,  33,  36,  37,    2,  -34 },   // 0x4F 'O'\n  {  4174,  26,  34,  32,    4,  -33 },   // 0x50 'P'\n  {  4285,  33,  37,  37,    2,  -34 },   // 0x51 'Q'\n  {  4438,  28,  34,  34,    4,  -33 },   // 0x52 'R'\n  {  4557,  28,  36,  32,    2,  -34 },   // 0x53 'S'\n  {  4683,  27,  34,  30,    2,  -33 },   // 0x54 'T'\n  {  4798,  27,  35,  35,    4,  -33 },   // 0x55 'U'\n  {  4917,  29,  34,  31,    1,  -33 },   // 0x56 'V'\n  {  5041,  43,  34,  45,    1,  -33 },   // 0x57 'W'\n  {  5224,  30,  34,  32,    1,  -33 },   // 0x58 'X'\n  {  5352,  29,  34,  30,    1,  -33 },   // 0x59 'Y'\n  {  5476,  26,  34,  29,    1,  -33 },   // 0x5A 'Z'\n  {  5587,  11,  43,  16,    3,  -33 },   // 0x5B '['\n  {  5647,  14,  34,  13,   -1,  -32 },   // 0x5C '\\'\n  {  5707,  11,  43,  16,    1,  -33 },   // 0x5D ']'\n  {  5767,  22,  20,  27,    3,  -32 },   // 0x5E '^'\n  {  5822,  28,   4,  26,   -1,    6 },   // 0x5F '_'\n  {  5836,   9,   7,  12,    1,  -35 },   // 0x60 '`'\n  {  5844,  24,  26,  27,    2,  -24 },   // 0x61 'a'\n  {  5922,  25,  35,  29,    3,  -33 },   // 0x62 'b'\n  {  6032,  23,  26,  26,    2,  -24 },   // 0x63 'c'\n  {  6107,  25,  35,  29,    2,  -33 },   // 0x64 'd'\n  {  6217,  24,  26,  27,    2,  -24 },   // 0x65 'e'\n  {  6295,  14,  34,  16,    1,  -33 },   // 0x66 'f'\n  {  6355,  24,  36,  29,    2,  -24 },   // 0x67 'g'\n  {  6463,  23,  34,  28,    3,  -33 },   // 0x68 'h'\n  {  6561,   7,  34,  13,    3,  -33 },   // 0x69 'i'\n  {  6591,  10,  45,  13,    0,  -33 },   // 0x6A 'j'\n  {  6648,  23,  34,  27,    3,  -33 },   // 0x6B 'k'\n  {  6746,   7,  34,  13,    3,  -33 },   // 0x6C 'l'\n  {  6776,  36,  25,  42,    3,  -24 },   // 0x6D 'm'\n  {  6889,  23,  25,  29,    3,  -24 },   // 0x6E 'n'\n  {  6961,  25,  26,  29,    2,  -24 },   // 0x6F 'o'\n  {  7043,  25,  36,  29,    3,  -24 },   // 0x70 'p'\n  {  7156,  25,  36,  29,    2,  -24 },   // 0x71 'q'\n  {  7269,  15,  25,  18,    3,  -24 },   // 0x72 'r'\n  {  7316,  24,  26,  26,    1,  -24 },   // 0x73 's'\n  {  7394,  12,  32,  16,    2,  -30 },   // 0x74 't'\n  {  7442,  23,  26,  29,    3,  -24 },   // 0x75 'u'\n  {  7517,  25,  25,  25,    0,  -24 },   // 0x76 'v'\n  {  7596,  35,  25,  37,    1,  -24 },   // 0x77 'w'\n  {  7706,  24,  25,  26,    1,  -24 },   // 0x78 'x'\n  {  7781,  25,  36,  26,    0,  -24 },   // 0x79 'y'\n  {  7894,  21,  25,  24,    1,  -24 },   // 0x7A 'z'\n  {  7960,  13,  43,  18,    2,  -33 },   // 0x7B '{'\n  {  8030,   4,  44,  13,    5,  -33 },   // 0x7C '|'\n  {  8052,  13,  43,  18,    3,  -33 },   // 0x7D '}'\n  {  8122,  21,   8,  23,    1,  -14 } }; // 0x7E '~'\n\nconst GFXfont FreeSansBold24pt7b PROGMEM = {\n  (uint8_t  *)FreeSansBold24pt7bBitmaps,\n  (GFXglyph *)FreeSansBold24pt7bGlyphs,\n  0x20, 0x7E, 56 };\n\n// Approx. 8815 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeSansBold9pt7b.h",
    "content": "const uint8_t FreeSansBold9pt7bBitmaps[] PROGMEM = {\n  0xFF, 0xFF, 0xFE, 0x48, 0x7E, 0xEF, 0xDF, 0xBF, 0x74, 0x40, 0x19, 0x86,\n  0x67, 0xFD, 0xFF, 0x33, 0x0C, 0xC3, 0x33, 0xFE, 0xFF, 0x99, 0x86, 0x61,\n  0x90, 0x10, 0x1F, 0x1F, 0xDE, 0xFF, 0x3F, 0x83, 0xC0, 0xFC, 0x1F, 0x09,\n  0xFC, 0xFE, 0xF7, 0xF1, 0xE0, 0x40, 0x38, 0x10, 0x7C, 0x30, 0xC6, 0x20,\n  0xC6, 0x40, 0xC6, 0x40, 0x7C, 0x80, 0x39, 0x9C, 0x01, 0x3E, 0x03, 0x63,\n  0x02, 0x63, 0x04, 0x63, 0x0C, 0x3E, 0x08, 0x1C, 0x0E, 0x01, 0xF8, 0x3B,\n  0x83, 0xB8, 0x3F, 0x01, 0xE0, 0x3E, 0x67, 0x76, 0xE3, 0xEE, 0x1C, 0xF3,\n  0xC7, 0xFE, 0x3F, 0x70, 0xFF, 0xF4, 0x18, 0x63, 0x1C, 0x73, 0x8E, 0x38,\n  0xE3, 0x8E, 0x18, 0x70, 0xC3, 0x06, 0x08, 0x61, 0x83, 0x0E, 0x38, 0x71,\n  0xC7, 0x1C, 0x71, 0xC6, 0x38, 0xE3, 0x18, 0x40, 0x21, 0x3E, 0x45, 0x28,\n  0x38, 0x70, 0xE7, 0xFF, 0xE7, 0x0E, 0x1C, 0xFC, 0x9C, 0xFF, 0xC0, 0xFC,\n  0x08, 0xC4, 0x23, 0x10, 0x84, 0x62, 0x11, 0x88, 0x00, 0x3E, 0x3F, 0x9D,\n  0xDC, 0x7E, 0x3F, 0x1F, 0x8F, 0xC7, 0xE3, 0xF1, 0xDD, 0xCF, 0xE3, 0xE0,\n  0x08, 0xFF, 0xF3, 0x9C, 0xE7, 0x39, 0xCE, 0x73, 0x80, 0x3E, 0x3F, 0xB8,\n  0xFC, 0x70, 0x38, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x0F, 0xF7, 0xF8,\n  0x3C, 0x7F, 0xE7, 0xE7, 0x07, 0x0C, 0x0E, 0x07, 0x07, 0xE7, 0xE7, 0x7E,\n  0x3C, 0x0E, 0x1E, 0x1E, 0x2E, 0x2E, 0x4E, 0x4E, 0x8E, 0xFF, 0xFF, 0x0E,\n  0x0E, 0x0E, 0x7F, 0x3F, 0x90, 0x18, 0x0D, 0xE7, 0xFB, 0x9E, 0x07, 0x03,\n  0x81, 0xF1, 0xFF, 0xE7, 0xC0, 0x3E, 0x3F, 0x9C, 0xFC, 0x0E, 0xE7, 0xFB,\n  0xDF, 0xC7, 0xE3, 0xF1, 0xDD, 0xEF, 0xE3, 0xE0, 0xFF, 0xFF, 0xC0, 0xE0,\n  0xE0, 0x60, 0x70, 0x30, 0x38, 0x1C, 0x0C, 0x0E, 0x07, 0x03, 0x80, 0x3F,\n  0x1F, 0xEE, 0x3F, 0x87, 0xE3, 0xCF, 0xC7, 0xFB, 0xCF, 0xE1, 0xF8, 0x7F,\n  0x3D, 0xFE, 0x3F, 0x00, 0x3E, 0x3F, 0xBD, 0xDC, 0x7E, 0x3F, 0x1F, 0xDE,\n  0xFF, 0x3B, 0x81, 0xF9, 0xCF, 0xE3, 0xC0, 0xFC, 0x00, 0x07, 0xE0, 0xFC,\n  0x00, 0x07, 0xE5, 0xE0, 0x00, 0x83, 0xC7, 0xDF, 0x0C, 0x07, 0x80, 0xF8,\n  0x1F, 0x01, 0x80, 0xFF, 0xFF, 0xC0, 0x00, 0x0F, 0xFF, 0xFC, 0x00, 0x70,\n  0x3F, 0x03, 0xE0, 0x38, 0x7D, 0xF1, 0xE0, 0x80, 0x00, 0x3E, 0x3F, 0xB8,\n  0xFC, 0x70, 0x38, 0x1C, 0x1C, 0x1C, 0x1C, 0x0E, 0x00, 0x03, 0x81, 0xC0,\n  0x03, 0xF0, 0x0F, 0xFC, 0x1E, 0x0E, 0x38, 0x02, 0x70, 0xE9, 0x63, 0x19,\n  0xC2, 0x19, 0xC6, 0x11, 0xC6, 0x33, 0xC6, 0x32, 0x63, 0xFE, 0x73, 0xDC,\n  0x3C, 0x00, 0x1F, 0xF8, 0x07, 0xF0, 0x07, 0x00, 0xF0, 0x0F, 0x80, 0xF8,\n  0x1D, 0x81, 0x9C, 0x19, 0xC3, 0x8C, 0x3F, 0xE7, 0xFE, 0x70, 0x66, 0x07,\n  0xE0, 0x70, 0xFF, 0x9F, 0xFB, 0x83, 0xF0, 0x7E, 0x0F, 0xFF, 0x3F, 0xF7,\n  0x06, 0xE0, 0xFC, 0x1F, 0x83, 0xFF, 0xEF, 0xF8, 0x1F, 0x83, 0xFE, 0x78,\n  0xE7, 0x07, 0xE0, 0x0E, 0x00, 0xE0, 0x0E, 0x00, 0xE0, 0x07, 0x07, 0x78,\n  0xF3, 0xFE, 0x1F, 0x80, 0xFF, 0x8F, 0xFC, 0xE0, 0xEE, 0x0E, 0xE0, 0x7E,\n  0x07, 0xE0, 0x7E, 0x07, 0xE0, 0x7E, 0x0E, 0xE0, 0xEF, 0xFC, 0xFF, 0x80,\n  0xFF, 0xFF, 0xF8, 0x1C, 0x0E, 0x07, 0xFB, 0xFD, 0xC0, 0xE0, 0x70, 0x38,\n  0x1F, 0xFF, 0xF8, 0xFF, 0xFF, 0xF8, 0x1C, 0x0E, 0x07, 0xFB, 0xFD, 0xC0,\n  0xE0, 0x70, 0x38, 0x1C, 0x0E, 0x00, 0x0F, 0x87, 0xF9, 0xE3, 0xB8, 0x3E,\n  0x01, 0xC0, 0x38, 0xFF, 0x1F, 0xE0, 0x6E, 0x0D, 0xE3, 0x9F, 0xD0, 0xF2,\n  0xE0, 0xFC, 0x1F, 0x83, 0xF0, 0x7E, 0x0F, 0xFF, 0xFF, 0xFF, 0x07, 0xE0,\n  0xFC, 0x1F, 0x83, 0xF0, 0x7E, 0x0E, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0x07,\n  0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0xE7, 0xE7, 0xE7, 0x7E, 0x3C,\n  0xE0, 0xEE, 0x1C, 0xE3, 0x8E, 0x70, 0xEE, 0x0F, 0xC0, 0xFE, 0x0F, 0x70,\n  0xE7, 0x0E, 0x38, 0xE1, 0xCE, 0x0E, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0,\n  0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xFF, 0xFF, 0xF8, 0x7F, 0xE1,\n  0xFF, 0x87, 0xFE, 0x1F, 0xEC, 0x7F, 0xB3, 0x7E, 0xCD, 0xFB, 0x37, 0xEC,\n  0xDF, 0x9E, 0x7E, 0x79, 0xF9, 0xE7, 0xE7, 0x9C, 0xE0, 0xFE, 0x1F, 0xC3,\n  0xFC, 0x7F, 0xCF, 0xD9, 0xFB, 0xBF, 0x37, 0xE7, 0xFC, 0x7F, 0x87, 0xF0,\n  0xFE, 0x0E, 0x0F, 0x81, 0xFF, 0x1E, 0x3C, 0xE0, 0xEE, 0x03, 0xF0, 0x1F,\n  0x80, 0xFC, 0x07, 0xE0, 0x3B, 0x83, 0x9E, 0x3C, 0x7F, 0xC0, 0xF8, 0x00,\n  0xFF, 0x9F, 0xFB, 0x87, 0xF0, 0x7E, 0x0F, 0xC3, 0xFF, 0xF7, 0xFC, 0xE0,\n  0x1C, 0x03, 0x80, 0x70, 0x0E, 0x00, 0x0F, 0x81, 0xFF, 0x1E, 0x3C, 0xE0,\n  0xEE, 0x03, 0xF0, 0x1F, 0x80, 0xFC, 0x07, 0xE1, 0xBB, 0x8F, 0x9E, 0x3C,\n  0x7F, 0xE0, 0xFB, 0x80, 0x08, 0xFF, 0x8F, 0xFC, 0xE0, 0xEE, 0x0E, 0xE0,\n  0xEE, 0x0E, 0xFF, 0xCF, 0xFC, 0xE0, 0xEE, 0x0E, 0xE0, 0xEE, 0x0E, 0xE0,\n  0xF0, 0x3F, 0x0F, 0xFB, 0xC7, 0xF0, 0x7E, 0x01, 0xFC, 0x1F, 0xF0, 0x3F,\n  0x00, 0xFC, 0x1D, 0xC7, 0xBF, 0xE1, 0xF8, 0xFF, 0xFF, 0xC7, 0x03, 0x81,\n  0xC0, 0xE0, 0x70, 0x38, 0x1C, 0x0E, 0x07, 0x03, 0x81, 0xC0, 0xE0, 0xFC,\n  0x1F, 0x83, 0xF0, 0x7E, 0x0F, 0xC1, 0xF8, 0x3F, 0x07, 0xE0, 0xFC, 0x1F,\n  0xC7, 0xBF, 0xE1, 0xF0, 0x60, 0x67, 0x0E, 0x70, 0xE3, 0x0C, 0x30, 0xC3,\n  0x9C, 0x19, 0x81, 0x98, 0x1F, 0x80, 0xF0, 0x0F, 0x00, 0xF0, 0x06, 0x00,\n  0x61, 0xC3, 0xB8, 0xE1, 0x9C, 0x70, 0xCE, 0x3C, 0xE3, 0x36, 0x71, 0x9B,\n  0x30, 0xED, 0x98, 0x36, 0x7C, 0x1B, 0x3C, 0x0F, 0x1E, 0x07, 0x8F, 0x01,\n  0xC3, 0x80, 0xE1, 0x80, 0x70, 0xE7, 0x8E, 0x39, 0xC1, 0xF8, 0x1F, 0x80,\n  0xF0, 0x07, 0x00, 0xF0, 0x1F, 0x81, 0x9C, 0x39, 0xC7, 0x0E, 0x70, 0xE0,\n  0xE0, 0xFC, 0x39, 0xC7, 0x18, 0xC3, 0xB8, 0x36, 0x07, 0xC0, 0x70, 0x0E,\n  0x01, 0xC0, 0x38, 0x07, 0x00, 0xE0, 0xFF, 0xFF, 0xC0, 0xE0, 0xE0, 0xF0,\n  0x70, 0x70, 0x70, 0x78, 0x38, 0x38, 0x1F, 0xFF, 0xF8, 0xFF, 0xEE, 0xEE,\n  0xEE, 0xEE, 0xEE, 0xEE, 0xEF, 0xF0, 0x86, 0x10, 0x86, 0x10, 0x84, 0x30,\n  0x84, 0x30, 0x80, 0xFF, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x7F, 0xF0,\n  0x18, 0x1C, 0x3C, 0x3E, 0x36, 0x66, 0x63, 0xC3, 0xFF, 0xC0, 0xCC, 0x3F,\n  0x1F, 0xEE, 0x38, 0x0E, 0x3F, 0x9E, 0xEE, 0x3B, 0x9E, 0xFF, 0x9E, 0xE0,\n  0xE0, 0x38, 0x0E, 0x03, 0xBC, 0xFF, 0xBC, 0xEE, 0x1F, 0x87, 0xE1, 0xF8,\n  0x7F, 0x3B, 0xFE, 0xEF, 0x00, 0x1F, 0x3F, 0xDC, 0x7C, 0x0E, 0x07, 0x03,\n  0x80, 0xE3, 0x7F, 0x8F, 0x00, 0x03, 0x81, 0xC0, 0xE7, 0x77, 0xFB, 0xBF,\n  0x8F, 0xC7, 0xE3, 0xF1, 0xFD, 0xEF, 0xF3, 0xB8, 0x3E, 0x3F, 0x9C, 0xDC,\n  0x3F, 0xFF, 0xFF, 0x81, 0xC3, 0x7F, 0x8F, 0x00, 0x3B, 0xDD, 0xFF, 0xB9,\n  0xCE, 0x73, 0x9C, 0xE7, 0x00, 0x3B, 0xBF, 0xDD, 0xFC, 0x7E, 0x3F, 0x1F,\n  0x8F, 0xEF, 0x7F, 0x9D, 0xC0, 0xFC, 0x77, 0xF1, 0xF0, 0xE0, 0x70, 0x38,\n  0x1D, 0xEF, 0xFF, 0x9F, 0x8F, 0xC7, 0xE3, 0xF1, 0xF8, 0xFC, 0x7E, 0x38,\n  0xFC, 0x7F, 0xFF, 0xFF, 0xFE, 0x77, 0x07, 0x77, 0x77, 0x77, 0x77, 0x77,\n  0x7F, 0xE0, 0xE0, 0x70, 0x38, 0x1C, 0x7E, 0x77, 0x73, 0xF1, 0xF8, 0xFE,\n  0x77, 0x39, 0xDC, 0x6E, 0x38, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xEF, 0x7B,\n  0xFF, 0xFE, 0x39, 0xF8, 0xE7, 0xE3, 0x9F, 0x8E, 0x7E, 0x39, 0xF8, 0xE7,\n  0xE3, 0x9F, 0x8E, 0x70, 0xEF, 0x7F, 0xF8, 0xFC, 0x7E, 0x3F, 0x1F, 0x8F,\n  0xC7, 0xE3, 0xF1, 0xC0, 0x1E, 0x1F, 0xE7, 0x3B, 0x87, 0xE1, 0xF8, 0x7E,\n  0x1D, 0xCE, 0x7F, 0x87, 0x80, 0xEF, 0x3F, 0xEF, 0x3B, 0x87, 0xE1, 0xF8,\n  0x7E, 0x1F, 0xCE, 0xFF, 0xBB, 0xCE, 0x03, 0x80, 0xE0, 0x38, 0x00, 0x3B,\n  0xBF, 0xFD, 0xFC, 0x7E, 0x3F, 0x1F, 0x8F, 0xEF, 0x7F, 0x9D, 0xC0, 0xE0,\n  0x70, 0x38, 0x1C, 0xEF, 0xFF, 0x38, 0xE3, 0x8E, 0x38, 0xE3, 0x80, 0x3E,\n  0x3F, 0xB8, 0xFC, 0x0F, 0xC3, 0xFC, 0x3F, 0xC7, 0xFF, 0x1F, 0x00, 0x73,\n  0xBF, 0xF7, 0x39, 0xCE, 0x73, 0x9E, 0x70, 0xE3, 0xF1, 0xF8, 0xFC, 0x7E,\n  0x3F, 0x1F, 0x8F, 0xC7, 0xFF, 0xBD, 0xC0, 0xE1, 0x98, 0x67, 0x39, 0xCC,\n  0x33, 0x0D, 0xC3, 0xE0, 0x78, 0x1E, 0x07, 0x00, 0xE3, 0x1D, 0x9E, 0x66,\n  0x79, 0x99, 0xE6, 0x77, 0xB8, 0xD2, 0xC3, 0xCF, 0x0F, 0x3C, 0x3C, 0xF0,\n  0x73, 0x80, 0x73, 0x9C, 0xE3, 0xF0, 0x78, 0x1E, 0x07, 0x81, 0xE0, 0xFC,\n  0x73, 0x9C, 0xE0, 0xE1, 0xD8, 0x67, 0x39, 0xCE, 0x33, 0x0E, 0xC3, 0xE0,\n  0x78, 0x1E, 0x03, 0x00, 0xC0, 0x70, 0x38, 0x0E, 0x00, 0xFE, 0xFE, 0x0E,\n  0x1C, 0x38, 0x38, 0x70, 0xE0, 0xFF, 0xFF, 0x37, 0x66, 0x66, 0x6E, 0xE6,\n  0x66, 0x66, 0x67, 0x30, 0xFF, 0xFF, 0x80, 0xCE, 0x66, 0x66, 0x67, 0x76,\n  0x66, 0x66, 0x6E, 0xC0, 0x71, 0x8E };\n\nconst GFXglyph FreeSansBold9pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,   5,    0,    1 },   // 0x20 ' '\n  {     0,   3,  13,   6,    2,  -12 },   // 0x21 '!'\n  {     5,   7,   5,   9,    1,  -12 },   // 0x22 '\"'\n  {    10,  10,  12,  10,    0,  -11 },   // 0x23 '#'\n  {    25,   9,  15,  10,    1,  -13 },   // 0x24 '$'\n  {    42,  16,  13,  16,    0,  -12 },   // 0x25 '%'\n  {    68,  12,  13,  13,    1,  -12 },   // 0x26 '&'\n  {    88,   3,   5,   5,    1,  -12 },   // 0x27 '''\n  {    90,   6,  17,   6,    1,  -12 },   // 0x28 '('\n  {   103,   6,  17,   6,    0,  -12 },   // 0x29 ')'\n  {   116,   5,   6,   7,    1,  -12 },   // 0x2A '*'\n  {   120,   7,   8,  11,    2,   -7 },   // 0x2B '+'\n  {   127,   3,   5,   4,    1,   -1 },   // 0x2C ','\n  {   129,   5,   2,   6,    0,   -5 },   // 0x2D '-'\n  {   131,   3,   2,   4,    1,   -1 },   // 0x2E '.'\n  {   132,   5,  13,   5,    0,  -12 },   // 0x2F '/'\n  {   141,   9,  13,  10,    1,  -12 },   // 0x30 '0'\n  {   156,   5,  13,  10,    2,  -12 },   // 0x31 '1'\n  {   165,   9,  13,  10,    1,  -12 },   // 0x32 '2'\n  {   180,   8,  13,  10,    1,  -12 },   // 0x33 '3'\n  {   193,   8,  13,  10,    2,  -12 },   // 0x34 '4'\n  {   206,   9,  13,  10,    1,  -12 },   // 0x35 '5'\n  {   221,   9,  13,  10,    1,  -12 },   // 0x36 '6'\n  {   236,   9,  13,  10,    0,  -12 },   // 0x37 '7'\n  {   251,  10,  13,  10,    0,  -12 },   // 0x38 '8'\n  {   268,   9,  13,  10,    1,  -12 },   // 0x39 '9'\n  {   283,   3,   9,   4,    1,   -8 },   // 0x3A ':'\n  {   287,   3,  12,   4,    1,   -8 },   // 0x3B ';'\n  {   292,   9,   9,  11,    1,   -8 },   // 0x3C '<'\n  {   303,   9,   6,  11,    1,   -6 },   // 0x3D '='\n  {   310,   9,   9,  11,    1,   -8 },   // 0x3E '>'\n  {   321,   9,  13,  11,    1,  -12 },   // 0x3F '?'\n  {   336,  16,  15,  18,    0,  -12 },   // 0x40 '@'\n  {   366,  12,  13,  13,    0,  -12 },   // 0x41 'A'\n  {   386,  11,  13,  13,    1,  -12 },   // 0x42 'B'\n  {   404,  12,  13,  13,    1,  -12 },   // 0x43 'C'\n  {   424,  12,  13,  13,    1,  -12 },   // 0x44 'D'\n  {   444,   9,  13,  12,    1,  -12 },   // 0x45 'E'\n  {   459,   9,  13,  11,    1,  -12 },   // 0x46 'F'\n  {   474,  11,  13,  14,    1,  -12 },   // 0x47 'G'\n  {   492,  11,  13,  13,    1,  -12 },   // 0x48 'H'\n  {   510,   3,  13,   6,    1,  -12 },   // 0x49 'I'\n  {   515,   8,  13,  10,    1,  -12 },   // 0x4A 'J'\n  {   528,  12,  13,  13,    1,  -12 },   // 0x4B 'K'\n  {   548,   8,  13,  11,    1,  -12 },   // 0x4C 'L'\n  {   561,  14,  13,  16,    1,  -12 },   // 0x4D 'M'\n  {   584,  11,  13,  14,    1,  -12 },   // 0x4E 'N'\n  {   602,  13,  13,  14,    1,  -12 },   // 0x4F 'O'\n  {   624,  11,  13,  12,    1,  -12 },   // 0x50 'P'\n  {   642,  13,  14,  14,    1,  -12 },   // 0x51 'Q'\n  {   665,  12,  13,  13,    1,  -12 },   // 0x52 'R'\n  {   685,  11,  13,  12,    1,  -12 },   // 0x53 'S'\n  {   703,   9,  13,  12,    2,  -12 },   // 0x54 'T'\n  {   718,  11,  13,  13,    1,  -12 },   // 0x55 'U'\n  {   736,  12,  13,  12,    0,  -12 },   // 0x56 'V'\n  {   756,  17,  13,  17,    0,  -12 },   // 0x57 'W'\n  {   784,  12,  13,  12,    0,  -12 },   // 0x58 'X'\n  {   804,  11,  13,  12,    1,  -12 },   // 0x59 'Y'\n  {   822,   9,  13,  11,    1,  -12 },   // 0x5A 'Z'\n  {   837,   4,  17,   6,    1,  -12 },   // 0x5B '['\n  {   846,   5,  13,   5,    0,  -12 },   // 0x5C '\\'\n  {   855,   4,  17,   6,    0,  -12 },   // 0x5D ']'\n  {   864,   8,   8,  11,    1,  -12 },   // 0x5E '^'\n  {   872,  10,   1,  10,    0,    4 },   // 0x5F '_'\n  {   874,   3,   2,   5,    0,  -12 },   // 0x60 '`'\n  {   875,  10,  10,  10,    1,   -9 },   // 0x61 'a'\n  {   888,  10,  13,  11,    1,  -12 },   // 0x62 'b'\n  {   905,   9,  10,  10,    1,   -9 },   // 0x63 'c'\n  {   917,   9,  13,  11,    1,  -12 },   // 0x64 'd'\n  {   932,   9,  10,  10,    1,   -9 },   // 0x65 'e'\n  {   944,   5,  13,   6,    1,  -12 },   // 0x66 'f'\n  {   953,   9,  14,  11,    1,   -9 },   // 0x67 'g'\n  {   969,   9,  13,  11,    1,  -12 },   // 0x68 'h'\n  {   984,   3,  13,   5,    1,  -12 },   // 0x69 'i'\n  {   989,   4,  17,   5,    0,  -12 },   // 0x6A 'j'\n  {   998,   9,  13,  10,    1,  -12 },   // 0x6B 'k'\n  {  1013,   3,  13,   5,    1,  -12 },   // 0x6C 'l'\n  {  1018,  14,  10,  16,    1,   -9 },   // 0x6D 'm'\n  {  1036,   9,  10,  11,    1,   -9 },   // 0x6E 'n'\n  {  1048,  10,  10,  11,    1,   -9 },   // 0x6F 'o'\n  {  1061,  10,  14,  11,    1,   -9 },   // 0x70 'p'\n  {  1079,   9,  14,  11,    1,   -9 },   // 0x71 'q'\n  {  1095,   6,  10,   7,    1,   -9 },   // 0x72 'r'\n  {  1103,   9,  10,  10,    1,   -9 },   // 0x73 's'\n  {  1115,   5,  12,   6,    1,  -11 },   // 0x74 't'\n  {  1123,   9,  10,  11,    1,   -9 },   // 0x75 'u'\n  {  1135,  10,  10,  10,    0,   -9 },   // 0x76 'v'\n  {  1148,  14,  10,  14,    0,   -9 },   // 0x77 'w'\n  {  1166,  10,  10,  10,    0,   -9 },   // 0x78 'x'\n  {  1179,  10,  14,  10,    0,   -9 },   // 0x79 'y'\n  {  1197,   8,  10,   9,    1,   -9 },   // 0x7A 'z'\n  {  1207,   4,  17,   7,    1,  -12 },   // 0x7B '{'\n  {  1216,   1,  17,   5,    2,  -12 },   // 0x7C '|'\n  {  1219,   4,  17,   7,    2,  -12 },   // 0x7D '}'\n  {  1228,   8,   2,   9,    0,   -4 } }; // 0x7E '~'\n\nconst GFXfont FreeSansBold9pt7b PROGMEM = {\n  (uint8_t  *)FreeSansBold9pt7bBitmaps,\n  (GFXglyph *)FreeSansBold9pt7bGlyphs,\n  0x20, 0x7E, 22 };\n\n// Approx. 1902 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeSansBoldOblique12pt7b.h",
    "content": "const uint8_t FreeSansBoldOblique12pt7bBitmaps[] PROGMEM = {\n  0x1C, 0x3C, 0x78, 0xE1, 0xC3, 0x8F, 0x1C, 0x38, 0x70, 0xC1, 0x83, 0x00,\n  0x1C, 0x78, 0xF0, 0x71, 0xFC, 0xFE, 0x3B, 0x8E, 0xC3, 0x30, 0xC0, 0x01,\n  0x8C, 0x07, 0x38, 0x0C, 0x61, 0xFF, 0xF3, 0xFF, 0xE7, 0xFF, 0x83, 0x9C,\n  0x0E, 0x70, 0x1C, 0xE1, 0xFF, 0xF3, 0xFF, 0xC7, 0xFF, 0x83, 0x18, 0x0E,\n  0x70, 0x18, 0xC0, 0x73, 0x80, 0x00, 0x40, 0x07, 0xF0, 0x3F, 0xF0, 0xFF,\n  0xF3, 0xC9, 0xE7, 0xB3, 0xCF, 0x60, 0x1F, 0xC0, 0x3F, 0xC0, 0x3F, 0xE0,\n  0x1F, 0xE0, 0x1B, 0xE0, 0x33, 0xDE, 0x47, 0xBC, 0x8F, 0x7F, 0x7C, 0x7F,\n  0xF0, 0x7F, 0x80, 0x18, 0x00, 0x20, 0x00, 0xC0, 0x00, 0x00, 0x01, 0x87,\n  0x80, 0xC3, 0xF0, 0x61, 0xFE, 0x10, 0xE1, 0x8C, 0x30, 0x66, 0x0C, 0x3B,\n  0x03, 0xFC, 0x80, 0x7E, 0x60, 0x0F, 0x30, 0x00, 0x18, 0x70, 0x0C, 0x7E,\n  0x03, 0x1F, 0xC1, 0x8E, 0x30, 0xC3, 0x1C, 0x60, 0xFE, 0x18, 0x1F, 0x8C,\n  0x07, 0x80, 0x01, 0xE0, 0x07, 0xF0, 0x1F, 0xE0, 0x79, 0xC0, 0xF3, 0x81,\n  0xEE, 0x01, 0xF8, 0x01, 0xE0, 0x1F, 0xC6, 0x7B, 0xDD, 0xE3, 0xF7, 0x87,\n  0xEF, 0x07, 0x9F, 0x1F, 0x3F, 0xFF, 0x3F, 0xDE, 0x3F, 0x1C, 0x7F, 0xEE,\n  0xCC, 0x03, 0x83, 0x81, 0x81, 0xC1, 0xC0, 0xE0, 0xE0, 0x70, 0x70, 0x38,\n  0x3C, 0x1C, 0x0E, 0x07, 0x03, 0x81, 0xC0, 0xE0, 0x70, 0x18, 0x0E, 0x07,\n  0x01, 0x80, 0x06, 0x03, 0x81, 0xC0, 0x60, 0x38, 0x1C, 0x0E, 0x07, 0x03,\n  0x81, 0xC0, 0xE0, 0xE0, 0x70, 0x38, 0x38, 0x1C, 0x1C, 0x0E, 0x0E, 0x06,\n  0x07, 0x07, 0x00, 0x0C, 0x0C, 0x4F, 0xFF, 0x1C, 0x3C, 0x6C, 0x44, 0x03,\n  0x80, 0x38, 0x07, 0x00, 0x70, 0x7F, 0xFF, 0xFF, 0xFF, 0xF0, 0xE0, 0x0E,\n  0x00, 0xE0, 0x0C, 0x00, 0x7B, 0xDC, 0x23, 0x33, 0x00, 0x7F, 0xFF, 0xF0,\n  0x7F, 0xE0, 0x00, 0xC0, 0x30, 0x18, 0x04, 0x03, 0x00, 0x80, 0x60, 0x10,\n  0x0C, 0x02, 0x01, 0x80, 0x40, 0x30, 0x08, 0x06, 0x01, 0x00, 0xC0, 0x00,\n  0x03, 0xC0, 0x7F, 0x87, 0xFC, 0x78, 0xF3, 0xC7, 0xBC, 0x3D, 0xE1, 0xEF,\n  0x0F, 0xF0, 0x7F, 0x87, 0xBC, 0x3D, 0xE1, 0xEF, 0x1E, 0x78, 0xF3, 0xFF,\n  0x0F, 0xF0, 0x3E, 0x00, 0x03, 0x83, 0x83, 0xCF, 0xEF, 0xF0, 0x78, 0x38,\n  0x1C, 0x0E, 0x0F, 0x07, 0x03, 0x81, 0xC1, 0xE0, 0xF0, 0x70, 0x38, 0x00,\n  0x03, 0xF0, 0x0F, 0xF8, 0x7F, 0xF8, 0xF1, 0xF3, 0xC1, 0xE7, 0x83, 0xC0,\n  0x07, 0x80, 0x1E, 0x00, 0x78, 0x03, 0xE0, 0x0F, 0x00, 0x7C, 0x01, 0xE0,\n  0x07, 0x00, 0x1F, 0xFC, 0x3F, 0xF8, 0xFF, 0xF0, 0x07, 0xE0, 0xFF, 0x8F,\n  0xFE, 0xF8, 0xF7, 0x87, 0x80, 0x78, 0x0F, 0x80, 0xFC, 0x07, 0xE0, 0x0F,\n  0x80, 0x3C, 0x01, 0xEF, 0x0F, 0x78, 0xF3, 0xFF, 0x8F, 0xF8, 0x3F, 0x00,\n  0x00, 0x78, 0x07, 0xC0, 0x7E, 0x03, 0xF0, 0x37, 0x03, 0x38, 0x31, 0xC3,\n  0x9E, 0x38, 0xF1, 0x87, 0x1F, 0xFE, 0xFF, 0xF7, 0xFF, 0x80, 0xF0, 0x07,\n  0x00, 0x38, 0x03, 0xC0, 0x07, 0xFC, 0x1F, 0xF0, 0xFF, 0xC3, 0x00, 0x1C,\n  0x00, 0x7F, 0x81, 0xFF, 0x0F, 0xFE, 0x38, 0xF8, 0x01, 0xE0, 0x07, 0x80,\n  0x1E, 0xF0, 0xF3, 0xC7, 0xCF, 0xFE, 0x1F, 0xF0, 0x3F, 0x00, 0x03, 0xE0,\n  0x7F, 0x87, 0xFE, 0x78, 0xF3, 0xC0, 0x3D, 0xE1, 0xFF, 0x8F, 0xFE, 0xF8,\n  0xF7, 0xC7, 0xBC, 0x3D, 0xE1, 0xEF, 0x1E, 0x7C, 0xF3, 0xFF, 0x0F, 0xF0,\n  0x1F, 0x00, 0x7F, 0xFB, 0xFF, 0xDF, 0xFE, 0x00, 0xE0, 0x0E, 0x00, 0xE0,\n  0x0E, 0x00, 0xE0, 0x0F, 0x00, 0x70, 0x07, 0x00, 0x78, 0x03, 0x80, 0x3C,\n  0x01, 0xC0, 0x0E, 0x00, 0xF0, 0x00, 0x03, 0xF0, 0x1F, 0xE0, 0xFF, 0xC7,\n  0x8F, 0x1C, 0x3C, 0x71, 0xE0, 0xFF, 0x03, 0xF8, 0x3F, 0xF1, 0xF1, 0xE7,\n  0x87, 0xBC, 0x1E, 0xF0, 0x7B, 0xE3, 0xCF, 0xFF, 0x1F, 0xF8, 0x1F, 0x80,\n  0x03, 0xE0, 0x3F, 0xE1, 0xFF, 0x8F, 0x9F, 0x3C, 0x3D, 0xE0, 0xF7, 0x83,\n  0xDE, 0x1F, 0x78, 0xFD, 0xFF, 0xE3, 0xFF, 0x87, 0xDE, 0x00, 0xF3, 0xC7,\n  0x8F, 0xFE, 0x1F, 0xF0, 0x3F, 0x00, 0x1C, 0xF3, 0x80, 0x00, 0x00, 0x00,\n  0x01, 0xCF, 0x38, 0x0E, 0x3C, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF1,\n  0xE3, 0x81, 0x06, 0x18, 0x60, 0x00, 0x00, 0x01, 0xC0, 0x7E, 0x1F, 0xE7,\n  0xF8, 0x7E, 0x03, 0xE0, 0x1F, 0xE0, 0x3F, 0xC0, 0x7F, 0x00, 0x78, 0x00,\n  0xC0, 0x3F, 0xFC, 0xFF, 0xF3, 0xFF, 0x80, 0x00, 0x00, 0x00, 0x00, 0x07,\n  0xFF, 0x9F, 0xFC, 0x7F, 0xF0, 0x30, 0x01, 0xE0, 0x0F, 0xE0, 0x3F, 0xC0,\n  0x7F, 0x80, 0x7C, 0x07, 0xE1, 0xFE, 0x7F, 0x87, 0xE0, 0x38, 0x00, 0x00,\n  0x00, 0x0F, 0xC1, 0xFF, 0x8F, 0xFC, 0xF1, 0xFF, 0x07, 0xF0, 0x3C, 0x01,\n  0xE0, 0x1E, 0x01, 0xE0, 0x3E, 0x03, 0xE0, 0x1C, 0x01, 0xC0, 0x0E, 0x00,\n  0x00, 0x07, 0x80, 0x3C, 0x01, 0xC0, 0x00, 0x00, 0x3F, 0x80, 0x03, 0xFF,\n  0x80, 0x3C, 0x0F, 0x01, 0xC0, 0x0E, 0x0E, 0x00, 0x1C, 0x70, 0xF7, 0x73,\n  0x87, 0xF8, 0xCC, 0x31, 0xE3, 0x61, 0x87, 0x0D, 0x8C, 0x1C, 0x3C, 0x30,\n  0x61, 0xB1, 0x81, 0x86, 0xC6, 0x0C, 0x3B, 0x18, 0x71, 0xCC, 0x63, 0xCE,\n  0x31, 0xFB, 0xF0, 0xE3, 0xCF, 0x01, 0xC0, 0x00, 0x03, 0xC0, 0xC0, 0x07,\n  0xFF, 0x00, 0x07, 0xF0, 0x00, 0x00, 0x3E, 0x00, 0x3F, 0x00, 0x1F, 0x80,\n  0x1F, 0xC0, 0x0F, 0xE0, 0x0F, 0xF0, 0x07, 0x7C, 0x07, 0x1E, 0x03, 0x8F,\n  0x03, 0x87, 0x83, 0xC3, 0xC1, 0xFF, 0xE1, 0xFF, 0xF0, 0xFF, 0xFC, 0xF0,\n  0x1E, 0x70, 0x0F, 0x78, 0x07, 0xB8, 0x03, 0xC0, 0x0F, 0xFE, 0x0F, 0xFF,\n  0x87, 0xFF, 0xE3, 0xC0, 0xF1, 0xC0, 0x78, 0xE0, 0x3C, 0xF0, 0x3C, 0x7F,\n  0xFC, 0x3F, 0xFC, 0x1F, 0xFF, 0x0E, 0x07, 0xCF, 0x01, 0xE7, 0x80, 0xF3,\n  0x80, 0x79, 0xC0, 0x79, 0xFF, 0xF8, 0xFF, 0xFC, 0x7F, 0xF8, 0x00, 0x01,\n  0xF8, 0x03, 0xFF, 0x03, 0xFF, 0xC3, 0xE1, 0xF3, 0xC0, 0x79, 0xE0, 0x3D,\n  0xE0, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0x78, 0x00, 0x3C, 0x00, 0x1E, 0x00,\n  0x0F, 0x00, 0xE7, 0x80, 0xF3, 0xE0, 0xF0, 0xFF, 0xF8, 0x3F, 0xF0, 0x07,\n  0xE0, 0x00, 0x1F, 0xFC, 0x0F, 0xFF, 0x87, 0xFF, 0xC3, 0x81, 0xF1, 0xC0,\n  0x79, 0xE0, 0x3C, 0xF0, 0x1E, 0x78, 0x0F, 0x38, 0x07, 0x9C, 0x03, 0xDE,\n  0x03, 0xCF, 0x01, 0xE7, 0x81, 0xF3, 0x80, 0xF1, 0xC1, 0xF1, 0xFF, 0xF0,\n  0xFF, 0xF0, 0x7F, 0xE0, 0x00, 0x0F, 0xFF, 0x1F, 0xFF, 0x1F, 0xFF, 0x1C,\n  0x00, 0x1C, 0x00, 0x3C, 0x00, 0x3C, 0x00, 0x3F, 0xFC, 0x3F, 0xFC, 0x3F,\n  0xFC, 0x78, 0x00, 0x78, 0x00, 0x78, 0x00, 0x70, 0x00, 0x70, 0x00, 0xFF,\n  0xF8, 0xFF, 0xF8, 0xFF, 0xF8, 0x1F, 0xFF, 0x1F, 0xFE, 0x1F, 0xFE, 0x1C,\n  0x00, 0x1C, 0x00, 0x3C, 0x00, 0x3C, 0x00, 0x3F, 0xF8, 0x3F, 0xF8, 0x3F,\n  0xF8, 0x78, 0x00, 0x78, 0x00, 0x78, 0x00, 0x70, 0x00, 0xF0, 0x00, 0xF0,\n  0x00, 0xF0, 0x00, 0xE0, 0x00, 0x01, 0xFC, 0x03, 0xFF, 0x03, 0xFF, 0xC3,\n  0xE0, 0xF3, 0xC0, 0x39, 0xC0, 0x01, 0xE0, 0x00, 0xF0, 0x00, 0xF0, 0x7F,\n  0x78, 0x3F, 0xBC, 0x1F, 0xDE, 0x01, 0xCF, 0x00, 0xE7, 0xC0, 0xF1, 0xF0,\n  0xF8, 0xFF, 0xFC, 0x3F, 0xEC, 0x07, 0xE6, 0x00, 0x1E, 0x03, 0x8F, 0x01,\n  0xC7, 0x01, 0xE3, 0x80, 0xF3, 0xC0, 0x79, 0xE0, 0x38, 0xF0, 0x1C, 0x7F,\n  0xFE, 0x3F, 0xFF, 0x3F, 0xFF, 0x9E, 0x03, 0x8F, 0x01, 0xC7, 0x01, 0xE3,\n  0x80, 0xF3, 0xC0, 0x71, 0xE0, 0x38, 0xF0, 0x3C, 0x70, 0x1E, 0x00, 0x1E,\n  0x3C, 0x78, 0xE1, 0xC7, 0x8F, 0x1E, 0x38, 0x71, 0xE3, 0xC7, 0x8E, 0x1C,\n  0x78, 0xF1, 0xE0, 0x00, 0x1C, 0x00, 0xF0, 0x03, 0xC0, 0x0F, 0x00, 0x38,\n  0x00, 0xE0, 0x07, 0x80, 0x1E, 0x00, 0x78, 0x01, 0xC0, 0x07, 0x3C, 0x3C,\n  0xF0, 0xF3, 0xC3, 0x8F, 0x1E, 0x3F, 0xF8, 0x7F, 0xC0, 0xFC, 0x00, 0x1E,\n  0x07, 0xC7, 0x83, 0xE1, 0xE1, 0xE0, 0x70, 0xF0, 0x1C, 0x78, 0x0F, 0x3C,\n  0x03, 0xDE, 0x00, 0xFF, 0x00, 0x3F, 0xC0, 0x0F, 0xF0, 0x07, 0xDE, 0x01,\n  0xE7, 0xC0, 0x78, 0xF0, 0x1C, 0x3E, 0x0F, 0x07, 0x83, 0xC0, 0xF0, 0xF0,\n  0x3C, 0x38, 0x07, 0x80, 0x0E, 0x00, 0xF0, 0x07, 0x80, 0x3C, 0x01, 0xC0,\n  0x0E, 0x00, 0xF0, 0x07, 0x80, 0x38, 0x01, 0xC0, 0x1E, 0x00, 0xF0, 0x07,\n  0x80, 0x38, 0x01, 0xC0, 0x1F, 0xFE, 0xFF, 0xF7, 0xFF, 0x80, 0x1F, 0x03,\n  0xF1, 0xF0, 0x3F, 0x1F, 0x07, 0xF1, 0xF0, 0x7F, 0x3F, 0x0F, 0xE3, 0xF0,\n  0xEE, 0x3B, 0x1E, 0xE3, 0xB1, 0xDE, 0x3B, 0x1D, 0xE7, 0xB3, 0x9C, 0x7B,\n  0x39, 0xC7, 0x37, 0x9C, 0x73, 0x73, 0xCF, 0x3F, 0x3C, 0xF3, 0xE3, 0x8F,\n  0x3E, 0x38, 0xE3, 0xC3, 0x8E, 0x3C, 0x78, 0x1E, 0x03, 0x87, 0xC0, 0xE1,\n  0xF0, 0x38, 0x7C, 0x1E, 0x1F, 0x87, 0x8F, 0xE1, 0xC3, 0xB8, 0x70, 0xEF,\n  0x1C, 0x39, 0xCF, 0x1E, 0x73, 0xC7, 0x8E, 0xE1, 0xC3, 0xB8, 0x70, 0xEE,\n  0x1C, 0x1F, 0x8F, 0x07, 0xE3, 0xC1, 0xF0, 0xE0, 0x3C, 0x38, 0x0F, 0x00,\n  0x01, 0xF8, 0x03, 0xFF, 0x03, 0xFF, 0xC3, 0xE3, 0xE3, 0xC0, 0xF9, 0xE0,\n  0x3D, 0xE0, 0x1E, 0xF0, 0x0F, 0xF0, 0x07, 0xF8, 0x03, 0xFC, 0x03, 0xDE,\n  0x01, 0xEF, 0x00, 0xF7, 0xC0, 0xF1, 0xF0, 0xF0, 0xFF, 0xF0, 0x3F, 0xF0,\n  0x07, 0xE0, 0x00, 0x1F, 0xFC, 0x1F, 0xFE, 0x1F, 0xFF, 0x1C, 0x1F, 0x1C,\n  0x0F, 0x3C, 0x0F, 0x3C, 0x0F, 0x3C, 0x1E, 0x3F, 0xFC, 0x3F, 0xFC, 0x7F,\n  0xF0, 0x78, 0x00, 0x78, 0x00, 0x70, 0x00, 0x70, 0x00, 0xF0, 0x00, 0xF0,\n  0x00, 0xF0, 0x00, 0x01, 0xF8, 0x03, 0xFF, 0x03, 0xFF, 0xC3, 0xE3, 0xE3,\n  0xC0, 0xF9, 0xC0, 0x3D, 0xE0, 0x1E, 0xF0, 0x0F, 0xF0, 0x07, 0xF8, 0x03,\n  0xFC, 0x03, 0xDE, 0x09, 0xEF, 0x0E, 0xE7, 0xC7, 0xF1, 0xF1, 0xF0, 0xFF,\n  0xF8, 0x3F, 0xFE, 0x07, 0xE6, 0x00, 0x02, 0x00, 0x0F, 0xFE, 0x0F, 0xFF,\n  0x87, 0xFF, 0xE3, 0x81, 0xF1, 0xC0, 0x78, 0xE0, 0x3C, 0xF0, 0x1C, 0x78,\n  0x1E, 0x3F, 0xFC, 0x1F, 0xFC, 0x1F, 0xFF, 0x8F, 0x03, 0xC7, 0x81, 0xE3,\n  0x80, 0xF1, 0xC0, 0xF1, 0xE0, 0x78, 0xF0, 0x3C, 0x78, 0x1F, 0x00, 0x03,\n  0xF8, 0x0F, 0xFE, 0x1F, 0xFF, 0x1E, 0x1F, 0x3C, 0x0F, 0x3C, 0x0F, 0x3C,\n  0x00, 0x3F, 0x00, 0x1F, 0xF0, 0x0F, 0xFC, 0x01, 0xFE, 0x00, 0x3E, 0xF0,\n  0x1E, 0xF0, 0x1E, 0xF8, 0x3C, 0x7F, 0xF8, 0x7F, 0xF0, 0x1F, 0xC0, 0x7F,\n  0xFE, 0xFF, 0xFD, 0xFF, 0xF8, 0x1C, 0x00, 0x78, 0x00, 0xF0, 0x01, 0xE0,\n  0x03, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x3C, 0x00, 0x78, 0x00, 0xE0, 0x01,\n  0xC0, 0x07, 0x80, 0x0F, 0x00, 0x1E, 0x00, 0x38, 0x00, 0x1E, 0x07, 0x1C,\n  0x0F, 0x3C, 0x0F, 0x3C, 0x0F, 0x3C, 0x0E, 0x38, 0x0E, 0x78, 0x1E, 0x78,\n  0x1E, 0x78, 0x1E, 0x78, 0x1C, 0x70, 0x1C, 0xF0, 0x3C, 0xF0, 0x3C, 0xF0,\n  0x38, 0xF8, 0x78, 0xFF, 0xF0, 0x7F, 0xE0, 0x1F, 0x80, 0xF0, 0x1F, 0xE0,\n  0x39, 0xC0, 0xF3, 0x81, 0xC7, 0x07, 0x8E, 0x0E, 0x1C, 0x3C, 0x3C, 0x70,\n  0x79, 0xE0, 0xF3, 0x80, 0xEF, 0x01, 0xDC, 0x03, 0xB8, 0x07, 0xE0, 0x0F,\n  0x80, 0x1F, 0x00, 0x3C, 0x00, 0x78, 0x00, 0xF0, 0x70, 0x7F, 0x87, 0x83,\n  0xFC, 0x3C, 0x3D, 0xE1, 0xE1, 0xEF, 0x1F, 0x0E, 0x78, 0xD8, 0xF3, 0xC6,\n  0xC7, 0x0E, 0x76, 0x78, 0x73, 0x33, 0x83, 0xB9, 0x9C, 0x1D, 0xCD, 0xC0,\n  0xEC, 0x6E, 0x07, 0xE3, 0xE0, 0x3E, 0x1F, 0x01, 0xF0, 0xF0, 0x0F, 0x87,\n  0x80, 0x78, 0x38, 0x03, 0xC1, 0xC0, 0x00, 0x0F, 0x03, 0xC3, 0xC1, 0xE0,\n  0xF8, 0xF0, 0x1E, 0x78, 0x07, 0x9E, 0x00, 0xFF, 0x00, 0x3F, 0x80, 0x0F,\n  0xC0, 0x01, 0xE0, 0x00, 0xF8, 0x00, 0x3F, 0x00, 0x1F, 0xC0, 0x0F, 0xF0,\n  0x07, 0x9E, 0x03, 0xC7, 0x80, 0xF0, 0xF0, 0x78, 0x3C, 0x3C, 0x0F, 0x80,\n  0x78, 0x1E, 0xF0, 0x79, 0xE0, 0xF3, 0xC3, 0xC3, 0xCF, 0x07, 0x9E, 0x0F,\n  0x78, 0x0F, 0xE0, 0x1F, 0x80, 0x3F, 0x00, 0x3C, 0x00, 0x70, 0x00, 0xE0,\n  0x03, 0xC0, 0x07, 0x80, 0x0F, 0x00, 0x1C, 0x00, 0x38, 0x00, 0x1F, 0xFF,\n  0x0F, 0xFF, 0x87, 0xFF, 0xC0, 0x03, 0xC0, 0x03, 0xE0, 0x03, 0xE0, 0x03,\n  0xE0, 0x03, 0xE0, 0x01, 0xE0, 0x01, 0xE0, 0x01, 0xE0, 0x01, 0xE0, 0x01,\n  0xE0, 0x01, 0xE0, 0x01, 0xE0, 0x01, 0xFF, 0xF0, 0xFF, 0xF8, 0x7F, 0xFC,\n  0x00, 0x0F, 0xC3, 0xF0, 0xFC, 0x38, 0x1E, 0x07, 0x01, 0xC0, 0x70, 0x1C,\n  0x0F, 0x03, 0x80, 0xE0, 0x38, 0x0E, 0x07, 0x01, 0xC0, 0x70, 0x1C, 0x0F,\n  0x03, 0x80, 0xFC, 0x3F, 0x0F, 0xC0, 0x08, 0x88, 0xC4, 0x44, 0x66, 0x66,\n  0x66, 0x62, 0x22, 0x33, 0x33, 0x30, 0x0F, 0xC3, 0xF0, 0xFC, 0x07, 0x03,\n  0xC0, 0xE0, 0x38, 0x0E, 0x03, 0x81, 0xC0, 0x70, 0x1C, 0x07, 0x03, 0xC0,\n  0xE0, 0x38, 0x0E, 0x03, 0x81, 0xE0, 0x70, 0xFC, 0x3F, 0x0F, 0xC0, 0x03,\n  0x80, 0xF0, 0x1E, 0x07, 0xE1, 0xDC, 0x3B, 0x8E, 0x71, 0x86, 0x70, 0xFC,\n  0x1F, 0x83, 0x80, 0x7F, 0xFE, 0xFF, 0xFC, 0xE6, 0x30, 0x07, 0xE0, 0xFF,\n  0x8F, 0xFE, 0x70, 0xE0, 0x07, 0x03, 0xF8, 0xFF, 0xCF, 0x9E, 0xF0, 0xF7,\n  0x8F, 0x3F, 0xF8, 0xFF, 0xC3, 0xDF, 0x00, 0x0E, 0x00, 0x1C, 0x00, 0x38,\n  0x00, 0xF0, 0x01, 0xE0, 0x03, 0x9F, 0x07, 0xFF, 0x0F, 0xFF, 0x3E, 0x3E,\n  0x78, 0x3C, 0xF0, 0x79, 0xC0, 0xF3, 0x81, 0xEF, 0x07, 0x9F, 0x1F, 0x3F,\n  0xFC, 0x7F, 0xF0, 0xEF, 0x80, 0x07, 0xC0, 0xFF, 0x8F, 0xFE, 0xF8, 0xF7,\n  0x87, 0xB8, 0x03, 0xC0, 0x1E, 0x00, 0xF0, 0xF7, 0x8F, 0x1F, 0xF8, 0xFF,\n  0x81, 0xF0, 0x00, 0x00, 0x1E, 0x00, 0x38, 0x00, 0x70, 0x00, 0xE0, 0x03,\n  0xC0, 0xF7, 0x87, 0xFE, 0x1F, 0xFC, 0x7C, 0x78, 0xF0, 0x73, 0xC0, 0xE7,\n  0x81, 0x8F, 0x07, 0x1E, 0x0E, 0x3E, 0x3C, 0x7F, 0xF8, 0x7F, 0xE0, 0x7D,\n  0xC0, 0x07, 0xC0, 0xFF, 0x8F, 0xFE, 0xF0, 0xF7, 0x87, 0xFF, 0xFF, 0xFF,\n  0xFE, 0x00, 0xF0, 0x07, 0xC7, 0x9F, 0xF8, 0xFF, 0x81, 0xF0, 0x00, 0x07,\n  0x87, 0xC7, 0xE3, 0xC1, 0xC3, 0xF9, 0xFC, 0x78, 0x3C, 0x1C, 0x0E, 0x07,\n  0x07, 0x83, 0x81, 0xC0, 0xE0, 0xF0, 0x78, 0x00, 0x03, 0xDE, 0x1F, 0xF8,\n  0x7F, 0xF1, 0xF1, 0xE3, 0xC1, 0xCF, 0x03, 0x9E, 0x06, 0x3C, 0x0C, 0x78,\n  0x38, 0xF8, 0xF1, 0xFF, 0xC1, 0xFF, 0x81, 0xF7, 0x00, 0x0E, 0x3C, 0x3C,\n  0x78, 0xF0, 0x7F, 0xC0, 0x7E, 0x00, 0x1E, 0x00, 0x70, 0x01, 0xC0, 0x07,\n  0x00, 0x3C, 0x00, 0xF7, 0xC3, 0xBF, 0x8F, 0xFF, 0x3C, 0x3D, 0xE0, 0xE7,\n  0x83, 0x9C, 0x0E, 0x70, 0x79, 0xC1, 0xEF, 0x07, 0x3C, 0x1C, 0xE0, 0x73,\n  0x83, 0xC0, 0x0E, 0x3C, 0x70, 0x00, 0x03, 0x8F, 0x1E, 0x38, 0x71, 0xE3,\n  0xC7, 0x0E, 0x1C, 0x78, 0xF1, 0xC0, 0x03, 0xC0, 0xE0, 0x38, 0x00, 0x00,\n  0x01, 0xE0, 0x70, 0x1C, 0x07, 0x03, 0xC0, 0xF0, 0x38, 0x0E, 0x03, 0x81,\n  0xE0, 0x70, 0x1C, 0x07, 0x03, 0xC0, 0xF0, 0xF8, 0x3E, 0x0F, 0x00, 0x0E,\n  0x00, 0x1C, 0x00, 0x38, 0x00, 0xF0, 0x01, 0xE0, 0x03, 0x87, 0x87, 0x1E,\n  0x0E, 0x78, 0x3D, 0xE0, 0x7F, 0x80, 0xFE, 0x01, 0xFE, 0x03, 0xFC, 0x0F,\n  0x38, 0x1E, 0x78, 0x38, 0xF0, 0x70, 0xF0, 0xE1, 0xE0, 0x0E, 0x3C, 0x78,\n  0xE1, 0xC3, 0x8F, 0x1E, 0x38, 0x71, 0xE3, 0xC7, 0x0E, 0x1C, 0x78, 0xF1,\n  0xC0, 0x1C, 0xF1, 0xE0, 0xEF, 0xDF, 0x87, 0xFF, 0xFE, 0x7C, 0x78, 0xF3,\n  0xC3, 0x87, 0x9C, 0x1C, 0x38, 0xE1, 0xE1, 0xC7, 0x0E, 0x0E, 0x78, 0x70,\n  0xF3, 0xC3, 0x87, 0x9C, 0x3C, 0x38, 0xE1, 0xE1, 0xC7, 0x0E, 0x0E, 0x00,\n  0x3D, 0xF0, 0xEF, 0xE3, 0xFF, 0xCF, 0x0F, 0x78, 0x39, 0xC0, 0xE7, 0x03,\n  0x9C, 0x1E, 0xF0, 0x7B, 0xC1, 0xCE, 0x07, 0x38, 0x1C, 0xE0, 0xF0, 0x07,\n  0xE0, 0x7F, 0xE3, 0xFF, 0x9F, 0x1F, 0x78, 0x3F, 0xC0, 0xFF, 0x03, 0xFC,\n  0x1F, 0xF0, 0x7B, 0xE3, 0xE7, 0xFF, 0x1F, 0xF8, 0x1F, 0x80, 0x0E, 0x7C,\n  0x0F, 0xFE, 0x0F, 0xFF, 0x1F, 0x1F, 0x1E, 0x0F, 0x1E, 0x0F, 0x1C, 0x0F,\n  0x1C, 0x0F, 0x3C, 0x1E, 0x3E, 0x3E, 0x3F, 0xFC, 0x3F, 0xF8, 0x7B, 0xE0,\n  0x78, 0x00, 0x70, 0x00, 0x70, 0x00, 0x70, 0x00, 0xF0, 0x00, 0x07, 0xBC,\n  0x7F, 0xF3, 0xFF, 0x9F, 0x1E, 0x78, 0x3B, 0xC0, 0xEF, 0x03, 0x3C, 0x0C,\n  0xF0, 0x73, 0xE3, 0xCF, 0xFF, 0x1F, 0xF8, 0x3C, 0xE0, 0x03, 0x80, 0x1E,\n  0x00, 0x78, 0x01, 0xC0, 0x07, 0x00, 0x3D, 0xCE, 0xE3, 0xF8, 0xF0, 0x78,\n  0x1E, 0x07, 0x01, 0xC0, 0xF0, 0x3C, 0x0E, 0x03, 0x80, 0xE0, 0x00, 0x1F,\n  0xC3, 0xFE, 0x7F, 0xFF, 0x0F, 0xF0, 0x0F, 0xE0, 0x7F, 0xC1, 0xFE, 0x03,\n  0xEE, 0x1E, 0xFF, 0xC7, 0xFC, 0x3F, 0x00, 0x1E, 0x1E, 0x1C, 0x7F, 0xFF,\n  0x3C, 0x38, 0x38, 0x38, 0x78, 0x78, 0x70, 0x7C, 0xF8, 0x78, 0x38, 0x3C,\n  0xE0, 0xE3, 0x83, 0x9E, 0x0E, 0x70, 0x79, 0xC1, 0xE7, 0x07, 0x3C, 0x1C,\n  0xF0, 0xF3, 0xE7, 0xCF, 0xFF, 0x1F, 0xF8, 0x3C, 0xE0, 0xF0, 0x77, 0x87,\n  0xBC, 0x38, 0xE3, 0xC7, 0x1C, 0x39, 0xE1, 0xCE, 0x0E, 0xE0, 0x77, 0x03,\n  0xF0, 0x0F, 0x80, 0x78, 0x03, 0xC0, 0x00, 0xF1, 0xC3, 0xF8, 0xE3, 0xFC,\n  0xF1, 0xDE, 0x79, 0xEF, 0x3C, 0xE7, 0xB6, 0x73, 0xDB, 0x70, 0xED, 0xB8,\n  0x7C, 0xF8, 0x3E, 0x7C, 0x1F, 0x3C, 0x0F, 0x1E, 0x07, 0x8E, 0x00, 0x0F,\n  0x1E, 0x0F, 0x3C, 0x0F, 0x38, 0x07, 0x70, 0x07, 0xF0, 0x03, 0xE0, 0x03,\n  0xC0, 0x07, 0xC0, 0x0F, 0xE0, 0x1E, 0xE0, 0x3C, 0xF0, 0x3C, 0xF0, 0x78,\n  0x78, 0x3C, 0x1C, 0x78, 0x78, 0xF0, 0xE1, 0xE3, 0xC1, 0xC7, 0x03, 0x9E,\n  0x07, 0x38, 0x0E, 0xE0, 0x1D, 0xC0, 0x3F, 0x00, 0x7E, 0x00, 0x78, 0x00,\n  0xF0, 0x01, 0xC0, 0x07, 0x00, 0x7E, 0x00, 0xF8, 0x01, 0xE0, 0x00, 0x1F,\n  0xF9, 0xFF, 0xCF, 0xFC, 0x01, 0xE0, 0x3E, 0x03, 0xC0, 0x3C, 0x03, 0xC0,\n  0x3C, 0x03, 0xC0, 0x3F, 0xF9, 0xFF, 0xCF, 0xFC, 0x00, 0x07, 0x87, 0xC3,\n  0xE3, 0xC1, 0xC0, 0xE0, 0x70, 0x38, 0x3C, 0x1C, 0x0E, 0x1E, 0x0F, 0x03,\n  0x81, 0xC0, 0xE0, 0x70, 0x78, 0x38, 0x1C, 0x0F, 0x87, 0xC1, 0xC0, 0x0C,\n  0x30, 0x86, 0x18, 0x61, 0x8C, 0x30, 0xC3, 0x0C, 0x61, 0x86, 0x18, 0x63,\n  0x0C, 0x30, 0xC2, 0x00, 0x00, 0x07, 0x07, 0xC3, 0xE0, 0x70, 0x38, 0x3C,\n  0x1C, 0x0E, 0x07, 0x03, 0x81, 0xE0, 0xF0, 0xE0, 0x70, 0x78, 0x38, 0x1C,\n  0x0E, 0x07, 0x07, 0x8F, 0x87, 0xC3, 0xC0, 0x3C, 0x07, 0xE0, 0xC7, 0x30,\n  0x7E, 0x01, 0xC0 };\n\nconst GFXglyph FreeSansBoldOblique12pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,   7,    0,    1 },   // 0x20 ' '\n  {     0,   7,  17,   8,    3,  -16 },   // 0x21 '!'\n  {    15,  10,   6,  11,    4,  -17 },   // 0x22 '\"'\n  {    23,  15,  16,  13,    1,  -15 },   // 0x23 '#'\n  {    53,  15,  21,  13,    1,  -17 },   // 0x24 '$'\n  {    93,  18,  18,  21,    3,  -17 },   // 0x25 '%'\n  {   134,  15,  17,  17,    2,  -16 },   // 0x26 '&'\n  {   166,   4,   6,   6,    4,  -17 },   // 0x27 '''\n  {   169,   9,  22,   8,    2,  -17 },   // 0x28 '('\n  {   194,   9,  22,   8,   -1,  -16 },   // 0x29 ')'\n  {   219,   8,   8,   9,    3,  -17 },   // 0x2A '*'\n  {   227,  12,  11,  14,    2,  -10 },   // 0x2B '+'\n  {   244,   5,   7,   7,    1,   -2 },   // 0x2C ','\n  {   249,   7,   3,   8,    2,   -7 },   // 0x2D '-'\n  {   252,   4,   3,   7,    2,   -2 },   // 0x2E '.'\n  {   254,  10,  17,   7,    0,  -16 },   // 0x2F '/'\n  {   276,  13,  17,  13,    2,  -16 },   // 0x30 '0'\n  {   304,   9,  17,  13,    4,  -16 },   // 0x31 '1'\n  {   324,  15,  17,  13,    1,  -16 },   // 0x32 '2'\n  {   356,  13,  17,  13,    2,  -16 },   // 0x33 '3'\n  {   384,  13,  17,  13,    1,  -16 },   // 0x34 '4'\n  {   412,  14,  17,  13,    1,  -16 },   // 0x35 '5'\n  {   442,  13,  17,  13,    2,  -16 },   // 0x36 '6'\n  {   470,  13,  17,  13,    3,  -16 },   // 0x37 '7'\n  {   498,  14,  17,  13,    1,  -16 },   // 0x38 '8'\n  {   528,  14,  17,  13,    2,  -16 },   // 0x39 '9'\n  {   558,   6,  12,   8,    3,  -11 },   // 0x3A ':'\n  {   567,   7,  16,   8,    2,  -11 },   // 0x3B ';'\n  {   581,  13,  12,  14,    2,  -11 },   // 0x3C '<'\n  {   601,  14,   9,  14,    1,   -9 },   // 0x3D '='\n  {   617,  13,  12,  14,    1,  -10 },   // 0x3E '>'\n  {   637,  13,  18,  15,    4,  -17 },   // 0x3F '?'\n  {   667,  22,  21,  23,    2,  -17 },   // 0x40 '@'\n  {   725,  17,  18,  17,    0,  -17 },   // 0x41 'A'\n  {   764,  17,  18,  17,    2,  -17 },   // 0x42 'B'\n  {   803,  17,  18,  17,    3,  -17 },   // 0x43 'C'\n  {   842,  17,  18,  17,    2,  -17 },   // 0x44 'D'\n  {   881,  16,  18,  16,    2,  -17 },   // 0x45 'E'\n  {   917,  16,  18,  15,    2,  -17 },   // 0x46 'F'\n  {   953,  17,  18,  19,    3,  -17 },   // 0x47 'G'\n  {   992,  17,  18,  17,    2,  -17 },   // 0x48 'H'\n  {  1031,   7,  18,   7,    2,  -17 },   // 0x49 'I'\n  {  1047,  14,  18,  13,    1,  -17 },   // 0x4A 'J'\n  {  1079,  18,  18,  17,    2,  -17 },   // 0x4B 'K'\n  {  1120,  13,  18,  15,    2,  -17 },   // 0x4C 'L'\n  {  1150,  20,  18,  20,    2,  -17 },   // 0x4D 'M'\n  {  1195,  18,  18,  17,    2,  -17 },   // 0x4E 'N'\n  {  1236,  17,  18,  19,    3,  -17 },   // 0x4F 'O'\n  {  1275,  16,  18,  16,    2,  -17 },   // 0x50 'P'\n  {  1311,  17,  19,  19,    3,  -17 },   // 0x51 'Q'\n  {  1352,  17,  18,  17,    2,  -17 },   // 0x52 'R'\n  {  1391,  16,  18,  16,    2,  -17 },   // 0x53 'S'\n  {  1427,  15,  18,  15,    3,  -17 },   // 0x54 'T'\n  {  1461,  16,  18,  17,    3,  -17 },   // 0x55 'U'\n  {  1497,  15,  18,  16,    4,  -17 },   // 0x56 'V'\n  {  1531,  21,  18,  23,    4,  -17 },   // 0x57 'W'\n  {  1579,  18,  18,  16,    1,  -17 },   // 0x58 'X'\n  {  1620,  15,  18,  16,    4,  -17 },   // 0x59 'Y'\n  {  1654,  17,  18,  15,    1,  -17 },   // 0x5A 'Z'\n  {  1693,  10,  23,   8,    1,  -17 },   // 0x5B '['\n  {  1722,   4,  23,   7,    3,  -22 },   // 0x5C '\\'\n  {  1734,  10,  23,   8,    0,  -17 },   // 0x5D ']'\n  {  1763,  11,  11,  14,    3,  -16 },   // 0x5E '^'\n  {  1779,  15,   2,  13,   -2,    4 },   // 0x5F '_'\n  {  1783,   4,   3,   8,    4,  -17 },   // 0x60 '`'\n  {  1785,  13,  13,  13,    1,  -12 },   // 0x61 'a'\n  {  1807,  15,  18,  15,    1,  -17 },   // 0x62 'b'\n  {  1841,  13,  13,  13,    2,  -12 },   // 0x63 'c'\n  {  1863,  15,  18,  15,    2,  -17 },   // 0x64 'd'\n  {  1897,  13,  13,  13,    2,  -12 },   // 0x65 'e'\n  {  1919,   9,  18,   8,    2,  -17 },   // 0x66 'f'\n  {  1940,  15,  18,  15,    1,  -12 },   // 0x67 'g'\n  {  1974,  14,  18,  15,    2,  -17 },   // 0x68 'h'\n  {  2006,   7,  18,   7,    2,  -17 },   // 0x69 'i'\n  {  2022,  10,  23,   7,   -1,  -17 },   // 0x6A 'j'\n  {  2051,  15,  18,  13,    1,  -17 },   // 0x6B 'k'\n  {  2085,   7,  18,   7,    2,  -17 },   // 0x6C 'l'\n  {  2101,  21,  13,  21,    1,  -12 },   // 0x6D 'm'\n  {  2136,  14,  13,  15,    2,  -12 },   // 0x6E 'n'\n  {  2159,  14,  13,  15,    2,  -12 },   // 0x6F 'o'\n  {  2182,  16,  18,  15,    0,  -12 },   // 0x70 'p'\n  {  2218,  14,  18,  15,    2,  -12 },   // 0x71 'q'\n  {  2250,  10,  13,   9,    2,  -12 },   // 0x72 'r'\n  {  2267,  12,  13,  13,    3,  -12 },   // 0x73 's'\n  {  2287,   8,  15,   8,    2,  -14 },   // 0x74 't'\n  {  2302,  14,  13,  15,    2,  -12 },   // 0x75 'u'\n  {  2325,  13,  13,  13,    3,  -12 },   // 0x76 'v'\n  {  2347,  17,  13,  19,    3,  -12 },   // 0x77 'w'\n  {  2375,  16,  13,  13,    0,  -12 },   // 0x78 'x'\n  {  2401,  15,  18,  13,    1,  -12 },   // 0x79 'y'\n  {  2435,  13,  13,  12,    1,  -12 },   // 0x7A 'z'\n  {  2457,   9,  23,   9,    3,  -17 },   // 0x7B '{'\n  {  2483,   6,  23,   7,    1,  -17 },   // 0x7C '|'\n  {  2501,   9,  23,   9,    0,  -17 },   // 0x7D '}'\n  {  2527,  12,   5,  14,    2,   -7 } }; // 0x7E '~'\n\nconst GFXfont FreeSansBoldOblique12pt7b PROGMEM = {\n  (uint8_t  *)FreeSansBoldOblique12pt7bBitmaps,\n  (GFXglyph *)FreeSansBoldOblique12pt7bGlyphs,\n  0x20, 0x7E, 29 };\n\n// Approx. 3207 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeSansBoldOblique18pt7b.h",
    "content": "const uint8_t FreeSansBoldOblique18pt7bBitmaps[] PROGMEM = {\n  0x06, 0x01, 0xC0, 0x7C, 0x1F, 0x0F, 0xC3, 0xE0, 0xF8, 0x3E, 0x0F, 0x83,\n  0xC0, 0xF0, 0x7C, 0x1E, 0x07, 0x81, 0xE0, 0x78, 0x1C, 0x07, 0x01, 0xC0,\n  0x60, 0x7C, 0x1F, 0x07, 0xC3, 0xF0, 0xF8, 0x00, 0x78, 0x7B, 0xC3, 0xFE,\n  0x3F, 0xE1, 0xEF, 0x0F, 0x78, 0x7B, 0x83, 0x9C, 0x1C, 0xC0, 0xC0, 0x00,\n  0x3C, 0x38, 0x00, 0xF1, 0xE0, 0x07, 0x87, 0x00, 0x1E, 0x3C, 0x00, 0xF0,\n  0xE0, 0x3F, 0xFF, 0xF0, 0xFF, 0xFF, 0xC7, 0xFF, 0xFF, 0x1F, 0xFF, 0xF8,\n  0x0F, 0x0E, 0x00, 0x3C, 0x78, 0x00, 0xE1, 0xE0, 0x07, 0x8F, 0x00, 0x1C,\n  0x3C, 0x07, 0xFF, 0xFE, 0x1F, 0xFF, 0xF8, 0x7F, 0xFF, 0xE3, 0xFF, 0xFF,\n  0x01, 0xE3, 0xC0, 0x0F, 0x0E, 0x00, 0x3C, 0x78, 0x01, 0xE1, 0xC0, 0x07,\n  0x8F, 0x00, 0x3C, 0x38, 0x00, 0x00, 0x0C, 0x00, 0x01, 0x80, 0x00, 0xFC,\n  0x00, 0xFF, 0xC0, 0x3F, 0xFC, 0x0F, 0xFF, 0xC3, 0xE6, 0x78, 0x78, 0xCF,\n  0x1E, 0x39, 0xE3, 0xC7, 0x3C, 0x78, 0xC0, 0x0F, 0x98, 0x01, 0xFF, 0x00,\n  0x1F, 0xF8, 0x01, 0xFF, 0x80, 0x1F, 0xF8, 0x00, 0x7F, 0x80, 0x0F, 0xF0,\n  0x03, 0xBE, 0x00, 0x67, 0xCF, 0x8C, 0xF9, 0xF1, 0x9F, 0x3E, 0x77, 0xC7,\n  0xEF, 0xF8, 0x7F, 0xFE, 0x0F, 0xFF, 0x80, 0xFF, 0xE0, 0x03, 0xE0, 0x00,\n  0x38, 0x00, 0x06, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x07, 0x01, 0xE0,\n  0x03, 0x81, 0xFE, 0x00, 0xC0, 0xFF, 0x80, 0x70, 0x7F, 0xF0, 0x38, 0x1E,\n  0x3C, 0x1C, 0x0F, 0x07, 0x06, 0x03, 0x81, 0xC3, 0x80, 0xE0, 0xF1, 0xC0,\n  0x3C, 0x78, 0xE0, 0x0F, 0xFE, 0x30, 0x01, 0xFF, 0x1C, 0x00, 0x7F, 0x8E,\n  0x00, 0x07, 0x83, 0x00, 0x00, 0x01, 0x83, 0xE0, 0x00, 0xE3, 0xFE, 0x00,\n  0x71, 0xFF, 0x80, 0x18, 0xFF, 0xF0, 0x0C, 0x3C, 0x3C, 0x07, 0x1C, 0x07,\n  0x03, 0x87, 0x01, 0xC0, 0xC1, 0xE1, 0xE0, 0x60, 0x7F, 0xF8, 0x38, 0x0F,\n  0xFC, 0x1C, 0x03, 0xFE, 0x06, 0x00, 0x3E, 0x00, 0x00, 0x1F, 0x00, 0x03,\n  0xFC, 0x00, 0x3F, 0xF0, 0x03, 0xFF, 0x80, 0x3F, 0x3C, 0x01, 0xF1, 0xE0,\n  0x0F, 0x8F, 0x00, 0x7C, 0xF0, 0x03, 0xFF, 0x80, 0x0F, 0xF8, 0x00, 0x3F,\n  0x00, 0x03, 0xF0, 0x00, 0x7F, 0xC7, 0x8F, 0xFE, 0x3C, 0xFC, 0xFB, 0xCF,\n  0x83, 0xFE, 0xF8, 0x1F, 0xE7, 0xC0, 0x7E, 0x3E, 0x03, 0xE1, 0xF0, 0x1F,\n  0x0F, 0xE3, 0xFC, 0x7F, 0xFF, 0xE1, 0xFF, 0xFF, 0x87, 0xFE, 0x7C, 0x0F,\n  0xE1, 0xF0, 0x7B, 0xFF, 0xEF, 0x7B, 0x9C, 0xC0, 0x00, 0x78, 0x07, 0x80,\n  0x78, 0x03, 0x80, 0x3C, 0x03, 0xC0, 0x1E, 0x01, 0xE0, 0x1E, 0x00, 0xF0,\n  0x0F, 0x00, 0x78, 0x03, 0xC0, 0x3C, 0x01, 0xE0, 0x0F, 0x00, 0xF0, 0x07,\n  0x80, 0x3C, 0x01, 0xE0, 0x0F, 0x00, 0x78, 0x03, 0xC0, 0x1E, 0x00, 0xF0,\n  0x07, 0x80, 0x1C, 0x00, 0xF0, 0x07, 0x80, 0x3C, 0x00, 0xE0, 0x07, 0x80,\n  0x1C, 0x00, 0x01, 0xC0, 0x0F, 0x00, 0x38, 0x01, 0xE0, 0x0F, 0x00, 0x78,\n  0x01, 0xC0, 0x0F, 0x00, 0x78, 0x03, 0xC0, 0x1E, 0x00, 0xF0, 0x07, 0x80,\n  0x3C, 0x01, 0xE0, 0x0F, 0x00, 0xF8, 0x07, 0x80, 0x3C, 0x01, 0xE0, 0x1E,\n  0x00, 0xF0, 0x07, 0x80, 0x78, 0x03, 0xC0, 0x3C, 0x03, 0xC0, 0x1E, 0x01,\n  0xE0, 0x1E, 0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x00, 0x03, 0x00, 0x70, 0x07,\n  0x04, 0x63, 0xFF, 0xF7, 0xFF, 0x1F, 0x83, 0xF0, 0x3B, 0x87, 0x38, 0x21,\n  0x00, 0x00, 0x78, 0x00, 0x3C, 0x00, 0x0F, 0x00, 0x03, 0xC0, 0x00, 0xF0,\n  0x00, 0x7C, 0x07, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, 0xBF, 0xFF, 0xE0,\n  0x3C, 0x00, 0x0F, 0x00, 0x03, 0xC0, 0x00, 0xF0, 0x00, 0x7C, 0x00, 0x1E,\n  0x00, 0x3E, 0x7C, 0xF3, 0xE7, 0xC1, 0x87, 0x0C, 0x39, 0xE3, 0x00, 0x7F,\n  0xDF, 0xFF, 0xFB, 0xFE, 0x7D, 0xF7, 0xBE, 0xF8, 0x00, 0x0E, 0x00, 0x18,\n  0x00, 0x70, 0x00, 0xC0, 0x03, 0x80, 0x06, 0x00, 0x1C, 0x00, 0x30, 0x00,\n  0xE0, 0x01, 0x80, 0x07, 0x00, 0x0C, 0x00, 0x38, 0x00, 0x60, 0x01, 0xC0,\n  0x03, 0x00, 0x0E, 0x00, 0x18, 0x00, 0x70, 0x00, 0xC0, 0x03, 0x80, 0x06,\n  0x00, 0x1C, 0x00, 0x30, 0x00, 0xE0, 0x00, 0x00, 0xFC, 0x00, 0x7F, 0xC0,\n  0x7F, 0xF8, 0x3F, 0xFE, 0x0F, 0x8F, 0xC7, 0xC1, 0xF1, 0xE0, 0x7C, 0xF8,\n  0x1F, 0x3E, 0x07, 0xDF, 0x01, 0xF7, 0xC0, 0x7D, 0xF0, 0x3F, 0x7C, 0x0F,\n  0xBF, 0x03, 0xEF, 0x80, 0xFB, 0xE0, 0x3E, 0xF8, 0x1F, 0x3E, 0x07, 0xCF,\n  0x81, 0xE3, 0xE0, 0xF8, 0xFC, 0x7C, 0x1F, 0xFF, 0x07, 0xFF, 0x80, 0xFF,\n  0xC0, 0x0F, 0x80, 0x00, 0x00, 0x70, 0x03, 0x80, 0x3C, 0x03, 0xE0, 0xFF,\n  0x3F, 0xF3, 0xFF, 0x9F, 0xFC, 0x03, 0xE0, 0x1F, 0x01, 0xF0, 0x0F, 0x80,\n  0x7C, 0x03, 0xE0, 0x1E, 0x01, 0xF0, 0x0F, 0x80, 0x7C, 0x03, 0xE0, 0x3E,\n  0x01, 0xF0, 0x0F, 0x80, 0x7C, 0x03, 0xE0, 0x3E, 0x00, 0x00, 0x1F, 0x80,\n  0x07, 0xFF, 0x00, 0x7F, 0xFC, 0x07, 0xFF, 0xE0, 0x7E, 0x1F, 0x83, 0xE0,\n  0x7C, 0x1F, 0x03, 0xE1, 0xF0, 0x1F, 0x0F, 0x80, 0xF8, 0x00, 0x0F, 0x80,\n  0x00, 0x7C, 0x00, 0x07, 0xC0, 0x00, 0x7C, 0x00, 0x07, 0xE0, 0x00, 0xFC,\n  0x00, 0x0F, 0xC0, 0x01, 0xF8, 0x00, 0x3F, 0x80, 0x03, 0xF8, 0x00, 0x3F,\n  0x00, 0x03, 0xF0, 0x00, 0x1F, 0xFF, 0xE1, 0xFF, 0xFF, 0x0F, 0xFF, 0xF0,\n  0x7F, 0xFF, 0x80, 0x00, 0x7F, 0x00, 0x1F, 0xFC, 0x03, 0xFF, 0xE0, 0x7F,\n  0xFF, 0x0F, 0x83, 0xF0, 0xF0, 0x1F, 0x1F, 0x01, 0xF1, 0xE0, 0x1F, 0x00,\n  0x03, 0xE0, 0x00, 0xFC, 0x00, 0xFF, 0x80, 0x0F, 0xF0, 0x00, 0xFF, 0x80,\n  0x0F, 0xFC, 0x00, 0x0F, 0xC0, 0x00, 0x7C, 0x00, 0x07, 0xCF, 0x80, 0x7C,\n  0xF8, 0x07, 0xCF, 0x80, 0xF8, 0xFC, 0x3F, 0x8F, 0xFF, 0xF0, 0x7F, 0xFE,\n  0x03, 0xFF, 0xC0, 0x0F, 0xE0, 0x00, 0x00, 0x07, 0xE0, 0x01, 0xFC, 0x00,\n  0x7F, 0x00, 0x1F, 0xE0, 0x03, 0xFC, 0x00, 0xEF, 0x80, 0x3D, 0xF0, 0x0F,\n  0x7C, 0x03, 0xCF, 0x80, 0xF1, 0xF0, 0x1C, 0x3E, 0x07, 0x07, 0xC1, 0xE1,\n  0xF0, 0x78, 0x3E, 0x1E, 0x07, 0xC3, 0xFF, 0xFE, 0x7F, 0xFF, 0xDF, 0xFF,\n  0xFB, 0xFF, 0xFF, 0x00, 0x1F, 0x00, 0x03, 0xE0, 0x00, 0x78, 0x00, 0x1F,\n  0x00, 0x03, 0xE0, 0x00, 0x7C, 0x00, 0x01, 0xFF, 0xF0, 0x3F, 0xFF, 0x03,\n  0xFF, 0xF0, 0x3F, 0xFF, 0x07, 0x80, 0x00, 0x78, 0x00, 0x0F, 0x00, 0x00,\n  0xF7, 0xE0, 0x0F, 0xFF, 0x01, 0xFF, 0xF8, 0x1F, 0xFF, 0x83, 0xF0, 0xFC,\n  0x3E, 0x07, 0xC0, 0x00, 0x7C, 0x00, 0x07, 0xC0, 0x00, 0x7C, 0x00, 0x07,\n  0x8F, 0x80, 0xF8, 0xF8, 0x1F, 0x8F, 0xC3, 0xF0, 0xFF, 0xFE, 0x07, 0xFF,\n  0xC0, 0x3F, 0xF8, 0x00, 0xFE, 0x00, 0x00, 0x7E, 0x00, 0x3F, 0xF0, 0x0F,\n  0xFF, 0x03, 0xFF, 0xE0, 0xF8, 0x7E, 0x3E, 0x07, 0xC7, 0x80, 0x01, 0xF0,\n  0x00, 0x3C, 0xFC, 0x07, 0xFF, 0xC1, 0xFF, 0xFC, 0x3F, 0xFF, 0xC7, 0xE1,\n  0xF8, 0xF8, 0x1F, 0x3E, 0x03, 0xE7, 0x80, 0x7C, 0xF0, 0x0F, 0x9E, 0x01,\n  0xE3, 0xC0, 0x7C, 0x78, 0x1F, 0x0F, 0x87, 0xE0, 0xFF, 0xF8, 0x1F, 0xFE,\n  0x01, 0xFF, 0x80, 0x0F, 0xC0, 0x00, 0x7F, 0xFF, 0xEF, 0xFF, 0xF9, 0xFF,\n  0xFF, 0x7F, 0xFF, 0xE0, 0x00, 0xF8, 0x00, 0x3E, 0x00, 0x0F, 0x80, 0x03,\n  0xE0, 0x00, 0xF8, 0x00, 0x3E, 0x00, 0x07, 0x80, 0x01, 0xF0, 0x00, 0x7C,\n  0x00, 0x1F, 0x00, 0x03, 0xE0, 0x00, 0xF8, 0x00, 0x1F, 0x00, 0x07, 0xC0,\n  0x00, 0xF8, 0x00, 0x3E, 0x00, 0x07, 0xC0, 0x01, 0xF0, 0x00, 0x3E, 0x00,\n  0x07, 0xC0, 0x00, 0x00, 0x7F, 0x00, 0x1F, 0xFC, 0x07, 0xFF, 0xE0, 0xFF,\n  0xFF, 0x0F, 0x81, 0xF1, 0xF0, 0x0F, 0x1E, 0x00, 0xF1, 0xE0, 0x1E, 0x1F,\n  0x07, 0xE0, 0xFF, 0xFC, 0x07, 0xFF, 0x00, 0xFF, 0xF8, 0x1F, 0xFF, 0x83,\n  0xF0, 0xFC, 0x7C, 0x07, 0xC7, 0xC0, 0x7C, 0xF8, 0x07, 0xCF, 0x80, 0x7C,\n  0xF8, 0x0F, 0x8F, 0x80, 0xF8, 0xFC, 0x3F, 0x0F, 0xFF, 0xF0, 0x7F, 0xFE,\n  0x03, 0xFF, 0x80, 0x0F, 0xE0, 0x00, 0x00, 0x7E, 0x00, 0x3F, 0xF0, 0x0F,\n  0xFF, 0x03, 0xFF, 0xE0, 0xFC, 0x3E, 0x3F, 0x03, 0xC7, 0xC0, 0x79, 0xF0,\n  0x0F, 0x3E, 0x01, 0xE7, 0xC0, 0x3C, 0xF8, 0x0F, 0x9F, 0x03, 0xE3, 0xF0,\n  0xFC, 0x7F, 0xFF, 0x87, 0xFF, 0xF0, 0x7F, 0xFE, 0x07, 0xE7, 0x80, 0x01,\n  0xF0, 0x00, 0x3C, 0x7C, 0x0F, 0x8F, 0xC3, 0xE1, 0xFF, 0xF8, 0x1F, 0xFE,\n  0x01, 0xFF, 0x80, 0x0F, 0xC0, 0x00, 0x0F, 0x87, 0xC3, 0xC3, 0xE1, 0xF0,\n  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xE1, 0xF0, 0xF0,\n  0xF8, 0x7C, 0x00, 0x07, 0xC1, 0xF0, 0x78, 0x3E, 0x0F, 0x80, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x83, 0xE0, 0xF0, 0x7C,\n  0x1F, 0x00, 0xC0, 0x70, 0x18, 0x0E, 0x0F, 0x03, 0x00, 0x00, 0x00, 0x20,\n  0x00, 0x3C, 0x00, 0x3F, 0x80, 0x3F, 0xE0, 0x3F, 0xFC, 0x3F, 0xFC, 0x1F,\n  0xFC, 0x07, 0xFC, 0x00, 0xFC, 0x00, 0x1F, 0xF0, 0x03, 0xFF, 0x80, 0x1F,\n  0xFE, 0x00, 0xFF, 0xF0, 0x03, 0xFE, 0x00, 0x1F, 0xC0, 0x00, 0x78, 0x00,\n  0x03, 0x00, 0x1F, 0xFF, 0xF3, 0xFF, 0xFE, 0x3F, 0xFF, 0xE3, 0xFF, 0xFE,\n  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7F, 0xFF,\n  0xC7, 0xFF, 0xFC, 0xFF, 0xFF, 0x8F, 0xFF, 0xF8, 0x18, 0x00, 0x03, 0xC0,\n  0x00, 0x7F, 0x00, 0x0F, 0xF8, 0x01, 0xFF, 0xE0, 0x0F, 0xFF, 0x00, 0x3F,\n  0xF8, 0x01, 0xFF, 0x00, 0x07, 0xE0, 0x07, 0xFC, 0x07, 0xFF, 0x07, 0xFF,\n  0x87, 0xFF, 0x80, 0xFF, 0x80, 0x3F, 0x80, 0x07, 0x80, 0x00, 0x80, 0x00,\n  0x00, 0x03, 0xF8, 0x03, 0xFF, 0xC1, 0xFF, 0xF8, 0xFF, 0xFE, 0x7E, 0x1F,\n  0xDF, 0x03, 0xFF, 0x80, 0x7F, 0xE0, 0x1F, 0xF8, 0x07, 0xC0, 0x03, 0xE0,\n  0x01, 0xF8, 0x00, 0xFC, 0x00, 0xFE, 0x00, 0x7F, 0x00, 0x3F, 0x80, 0x1F,\n  0x80, 0x07, 0x80, 0x03, 0xE0, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00,\n  0x07, 0xC0, 0x01, 0xF0, 0x00, 0xFC, 0x00, 0x3E, 0x00, 0x0F, 0x80, 0x00,\n  0x00, 0x00, 0x7F, 0x80, 0x00, 0x01, 0xFF, 0xF8, 0x00, 0x03, 0xFF, 0xFE,\n  0x00, 0x07, 0xF0, 0x1F, 0xC0, 0x0F, 0xC0, 0x03, 0xE0, 0x0F, 0x80, 0x00,\n  0xF8, 0x0F, 0x00, 0x00, 0x3C, 0x0F, 0x01, 0xF1, 0xCF, 0x0F, 0x03, 0xFD,\n  0xC7, 0x8F, 0x03, 0xFF, 0xE1, 0xC7, 0x03, 0xE3, 0xE0, 0xE7, 0x03, 0xC0,\n  0xF0, 0x73, 0x83, 0xC0, 0x78, 0x3B, 0x81, 0xE0, 0x38, 0x1D, 0xC1, 0xE0,\n  0x1C, 0x1C, 0xC0, 0xF0, 0x1C, 0x0E, 0xE0, 0x70, 0x0E, 0x0F, 0x70, 0x78,\n  0x0E, 0x07, 0x38, 0x3C, 0x0F, 0x07, 0x1C, 0x1E, 0x0F, 0x87, 0x8E, 0x0F,\n  0x8F, 0xCF, 0x87, 0x07, 0xFF, 0xFF, 0x83, 0xC1, 0xFE, 0x7F, 0x00, 0xE0,\n  0x3C, 0x1F, 0x00, 0x78, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x0F,\n  0xC0, 0x01, 0x00, 0x03, 0xF8, 0x07, 0x80, 0x00, 0xFF, 0xFF, 0xC0, 0x00,\n  0x1F, 0xFF, 0xE0, 0x00, 0x01, 0xFF, 0x00, 0x00, 0x00, 0x03, 0xF0, 0x00,\n  0x0F, 0xE0, 0x00, 0x1F, 0xE0, 0x00, 0x7F, 0xC0, 0x00, 0xFF, 0x80, 0x03,\n  0xFF, 0x00, 0x07, 0xFE, 0x00, 0x1F, 0x7C, 0x00, 0x7E, 0xF8, 0x00, 0xF9,\n  0xF0, 0x03, 0xF3, 0xE0, 0x07, 0xC3, 0xE0, 0x1F, 0x87, 0xC0, 0x3E, 0x0F,\n  0x80, 0xF8, 0x1F, 0x01, 0xF0, 0x3E, 0x07, 0xFF, 0xFC, 0x1F, 0xFF, 0xF8,\n  0x3F, 0xFF, 0xF0, 0xFF, 0xFF, 0xF1, 0xF0, 0x03, 0xE7, 0xC0, 0x07, 0xCF,\n  0x80, 0x0F, 0xBE, 0x00, 0x1F, 0x7C, 0x00, 0x3F, 0xF0, 0x00, 0x7C, 0x07,\n  0xFF, 0xF0, 0x07, 0xFF, 0xFC, 0x07, 0xFF, 0xFE, 0x0F, 0xFF, 0xFF, 0x0F,\n  0xC0, 0x3F, 0x0F, 0x80, 0x1F, 0x0F, 0x80, 0x1F, 0x0F, 0x80, 0x1F, 0x1F,\n  0x80, 0x1E, 0x1F, 0x80, 0x3E, 0x1F, 0x00, 0x7C, 0x1F, 0xFF, 0xF8, 0x1F,\n  0xFF, 0xF0, 0x3F, 0xFF, 0xF8, 0x3F, 0xFF, 0xF8, 0x3E, 0x00, 0xFC, 0x3E,\n  0x00, 0x7C, 0x3E, 0x00, 0x7C, 0x7E, 0x00, 0x7C, 0x7C, 0x00, 0x7C, 0x7C,\n  0x00, 0xF8, 0x7C, 0x01, 0xF8, 0x7F, 0xFF, 0xF0, 0xFF, 0xFF, 0xE0, 0xFF,\n  0xFF, 0xC0, 0xFF, 0xFE, 0x00, 0x00, 0x1F, 0xE0, 0x00, 0x7F, 0xF8, 0x01,\n  0xFF, 0xFC, 0x03, 0xFF, 0xFE, 0x07, 0xE0, 0x7F, 0x0F, 0xC0, 0x3F, 0x1F,\n  0x80, 0x1F, 0x3F, 0x00, 0x1F, 0x3E, 0x00, 0x1F, 0x7E, 0x00, 0x00, 0x7C,\n  0x00, 0x00, 0x7C, 0x00, 0x00, 0x7C, 0x00, 0x00, 0xF8, 0x00, 0x00, 0xF8,\n  0x00, 0x00, 0xF8, 0x00, 0x00, 0xF8, 0x00, 0x00, 0xF8, 0x00, 0x7C, 0xF8,\n  0x00, 0x7C, 0xFC, 0x00, 0xF8, 0xFC, 0x01, 0xF8, 0x7F, 0x07, 0xF0, 0x7F,\n  0xFF, 0xE0, 0x3F, 0xFF, 0xC0, 0x0F, 0xFF, 0x00, 0x03, 0xFC, 0x00, 0x07,\n  0xFF, 0xE0, 0x07, 0xFF, 0xF8, 0x07, 0xFF, 0xFC, 0x0F, 0xFF, 0xFE, 0x0F,\n  0x80, 0x7E, 0x0F, 0x80, 0x3F, 0x0F, 0x80, 0x1F, 0x1F, 0x80, 0x1F, 0x1F,\n  0x80, 0x1F, 0x1F, 0x00, 0x1F, 0x1F, 0x00, 0x1F, 0x1F, 0x00, 0x1F, 0x3F,\n  0x00, 0x1F, 0x3E, 0x00, 0x3E, 0x3E, 0x00, 0x3E, 0x3E, 0x00, 0x3E, 0x3E,\n  0x00, 0x3E, 0x7E, 0x00, 0x7C, 0x7C, 0x00, 0x7C, 0x7C, 0x00, 0xF8, 0x7C,\n  0x01, 0xF8, 0x7C, 0x07, 0xF0, 0xFF, 0xFF, 0xE0, 0xFF, 0xFF, 0xC0, 0xFF,\n  0xFF, 0x00, 0xFF, 0xF8, 0x00, 0x07, 0xFF, 0xFF, 0x07, 0xFF, 0xFE, 0x07,\n  0xFF, 0xFE, 0x0F, 0xFF, 0xFE, 0x0F, 0x80, 0x00, 0x0F, 0x80, 0x00, 0x0F,\n  0x80, 0x00, 0x0F, 0x80, 0x00, 0x1F, 0x80, 0x00, 0x1F, 0x00, 0x00, 0x1F,\n  0x00, 0x00, 0x1F, 0xFF, 0xF0, 0x1F, 0xFF, 0xF0, 0x3F, 0xFF, 0xF0, 0x3F,\n  0xFF, 0xF0, 0x3E, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x7E,\n  0x00, 0x00, 0x7C, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x7C, 0x00, 0x00, 0xFF,\n  0xFF, 0xF0, 0xFF, 0xFF, 0xE0, 0xFF, 0xFF, 0xE0, 0xFF, 0xFF, 0xE0, 0x07,\n  0xFF, 0xFE, 0x0F, 0xFF, 0xFC, 0x3F, 0xFF, 0xF0, 0x7F, 0xFF, 0xE0, 0xF8,\n  0x00, 0x01, 0xF0, 0x00, 0x03, 0xE0, 0x00, 0x0F, 0xC0, 0x00, 0x1F, 0x00,\n  0x00, 0x3E, 0x00, 0x00, 0x7C, 0x00, 0x00, 0xFF, 0xFF, 0x03, 0xFF, 0xFE,\n  0x07, 0xFF, 0xFC, 0x0F, 0xFF, 0xF0, 0x1F, 0x00, 0x00, 0x3E, 0x00, 0x00,\n  0xFC, 0x00, 0x01, 0xF0, 0x00, 0x03, 0xE0, 0x00, 0x07, 0xC0, 0x00, 0x0F,\n  0x80, 0x00, 0x3F, 0x00, 0x00, 0x7C, 0x00, 0x00, 0xF8, 0x00, 0x01, 0xF0,\n  0x00, 0x00, 0x00, 0x1F, 0xE0, 0x00, 0x7F, 0xF8, 0x01, 0xFF, 0xFC, 0x03,\n  0xFF, 0xFE, 0x07, 0xE0, 0x7E, 0x0F, 0x80, 0x3F, 0x1F, 0x00, 0x1F, 0x3E,\n  0x00, 0x1F, 0x3E, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x7C,\n  0x00, 0x00, 0xF8, 0x03, 0xFF, 0xF8, 0x07, 0xFF, 0xF8, 0x07, 0xFE, 0xF8,\n  0x07, 0xFE, 0xF8, 0x00, 0x3E, 0xF8, 0x00, 0x3E, 0xFC, 0x00, 0x7E, 0xFC,\n  0x00, 0x7C, 0x7E, 0x00, 0xFC, 0x7F, 0x83, 0xFC, 0x3F, 0xFF, 0xFC, 0x1F,\n  0xFF, 0xBC, 0x0F, 0xFF, 0x38, 0x03, 0xFC, 0x38, 0x03, 0xE0, 0x07, 0xC0,\n  0xF8, 0x01, 0xF0, 0x7E, 0x00, 0x7C, 0x1F, 0x00, 0x3F, 0x07, 0xC0, 0x0F,\n  0x81, 0xF0, 0x03, 0xE0, 0xFC, 0x00, 0xF8, 0x3E, 0x00, 0x3E, 0x0F, 0x80,\n  0x1F, 0x83, 0xE0, 0x07, 0xC0, 0xFF, 0xFF, 0xF0, 0x7F, 0xFF, 0xFC, 0x1F,\n  0xFF, 0xFF, 0x07, 0xFF, 0xFF, 0xC1, 0xF0, 0x03, 0xE0, 0x7C, 0x00, 0xF8,\n  0x3F, 0x00, 0x3E, 0x0F, 0x80, 0x0F, 0x83, 0xE0, 0x07, 0xE0, 0xF8, 0x01,\n  0xF0, 0x3E, 0x00, 0x7C, 0x1F, 0x80, 0x1F, 0x07, 0xC0, 0x0F, 0xC1, 0xF0,\n  0x03, 0xF0, 0x7C, 0x00, 0xF8, 0x3F, 0x00, 0x3E, 0x00, 0x07, 0xC3, 0xF0,\n  0xFC, 0x3E, 0x0F, 0x83, 0xE0, 0xF8, 0x7E, 0x1F, 0x07, 0xC1, 0xF0, 0x7C,\n  0x3F, 0x0F, 0xC3, 0xE0, 0xF8, 0x3E, 0x0F, 0x87, 0xE1, 0xF0, 0x7C, 0x1F,\n  0x07, 0xC3, 0xF0, 0xFC, 0x3E, 0x00, 0x00, 0x01, 0xF0, 0x00, 0x1F, 0x00,\n  0x01, 0xF0, 0x00, 0x3F, 0x00, 0x03, 0xE0, 0x00, 0x3E, 0x00, 0x03, 0xE0,\n  0x00, 0x3E, 0x00, 0x07, 0xE0, 0x00, 0x7C, 0x00, 0x07, 0xC0, 0x00, 0x7C,\n  0x00, 0x0F, 0xC0, 0x00, 0xFC, 0x00, 0x0F, 0x80, 0x00, 0xF8, 0x7C, 0x0F,\n  0x8F, 0x81, 0xF8, 0xF8, 0x1F, 0x0F, 0x81, 0xF0, 0xF8, 0x1F, 0x0F, 0xC3,\n  0xF0, 0xFF, 0xFE, 0x07, 0xFF, 0xC0, 0x3F, 0xF8, 0x01, 0xFC, 0x00, 0x07,\n  0xC0, 0x0F, 0xC1, 0xF0, 0x07, 0xE0, 0x7C, 0x03, 0xF0, 0x3F, 0x03, 0xF8,\n  0x0F, 0x81, 0xF8, 0x03, 0xE0, 0xFC, 0x00, 0xF8, 0x7E, 0x00, 0x7E, 0x3F,\n  0x00, 0x1F, 0x1F, 0x80, 0x07, 0xCF, 0xC0, 0x01, 0xF7, 0xE0, 0x00, 0x7F,\n  0xF0, 0x00, 0x3F, 0xFC, 0x00, 0x0F, 0xFF, 0x80, 0x03, 0xFF, 0xF0, 0x00,\n  0xFE, 0xFC, 0x00, 0x3F, 0x1F, 0x80, 0x1F, 0x87, 0xE0, 0x07, 0xC0, 0xFC,\n  0x01, 0xF0, 0x3F, 0x00, 0x7C, 0x07, 0xE0, 0x1F, 0x01, 0xFC, 0x0F, 0xC0,\n  0x3F, 0x03, 0xE0, 0x0F, 0xE0, 0xF8, 0x01, 0xF8, 0x3E, 0x00, 0x3F, 0x00,\n  0x07, 0xC0, 0x01, 0xF0, 0x00, 0x7C, 0x00, 0x1F, 0x00, 0x0F, 0xC0, 0x03,\n  0xE0, 0x00, 0xF8, 0x00, 0x3E, 0x00, 0x1F, 0x80, 0x07, 0xC0, 0x01, 0xF0,\n  0x00, 0x7C, 0x00, 0x1F, 0x00, 0x0F, 0xC0, 0x03, 0xE0, 0x00, 0xF8, 0x00,\n  0x3E, 0x00, 0x0F, 0x80, 0x07, 0xE0, 0x01, 0xF0, 0x00, 0x7C, 0x00, 0x1F,\n  0x00, 0x07, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xBF, 0xFF, 0xE0, 0x03,\n  0xF8, 0x01, 0xFC, 0x07, 0xF0, 0x07, 0xF8, 0x1F, 0xE0, 0x0F, 0xF0, 0x3F,\n  0xC0, 0x3F, 0xE0, 0x7F, 0x80, 0x7F, 0xC0, 0xFF, 0x01, 0xFF, 0x01, 0xFE,\n  0x03, 0xFE, 0x07, 0xDC, 0x07, 0x7C, 0x0F, 0xB8, 0x1E, 0xF8, 0x1F, 0x70,\n  0x3D, 0xF0, 0x3E, 0xF0, 0xF7, 0xC0, 0xF9, 0xE1, 0xEF, 0x81, 0xF3, 0xC7,\n  0x9F, 0x03, 0xE7, 0x8F, 0x3E, 0x07, 0xCF, 0x3C, 0x7C, 0x0F, 0x9E, 0x79,\n  0xF0, 0x3E, 0x3C, 0xE3, 0xE0, 0x7C, 0x7B, 0xC7, 0xC0, 0xF8, 0xF7, 0x8F,\n  0x81, 0xF1, 0xFE, 0x1E, 0x07, 0xE3, 0xFC, 0x7C, 0x0F, 0x87, 0xF0, 0xF8,\n  0x1F, 0x0F, 0xE1, 0xF0, 0x3E, 0x1F, 0x83, 0xE0, 0x7C, 0x3F, 0x0F, 0x81,\n  0xF0, 0x7E, 0x1F, 0x00, 0x03, 0xE0, 0x07, 0xC0, 0x7E, 0x00, 0xF8, 0x1F,\n  0xC0, 0x1F, 0x03, 0xF8, 0x03, 0xE0, 0x7F, 0x80, 0x7C, 0x0F, 0xF0, 0x1F,\n  0x01, 0xFF, 0x03, 0xE0, 0x7F, 0xE0, 0x7C, 0x0F, 0xBC, 0x0F, 0x81, 0xF7,\n  0xC1, 0xF0, 0x3E, 0xF8, 0x7C, 0x0F, 0x8F, 0x0F, 0x81, 0xF1, 0xF1, 0xF0,\n  0x3E, 0x3E, 0x3E, 0x07, 0xC3, 0xC7, 0xC0, 0xF8, 0x7D, 0xF0, 0x3E, 0x0F,\n  0xBE, 0x07, 0xC0, 0xF7, 0xC0, 0xF8, 0x1F, 0xF8, 0x1F, 0x01, 0xFE, 0x03,\n  0xC0, 0x3F, 0xC0, 0xF8, 0x07, 0xF8, 0x1F, 0x00, 0x7F, 0x03, 0xE0, 0x0F,\n  0xE0, 0x7C, 0x01, 0xF8, 0x1F, 0x00, 0x1F, 0x00, 0x00, 0x1F, 0xE0, 0x00,\n  0x3F, 0xFC, 0x00, 0x7F, 0xFF, 0x00, 0x7F, 0xFF, 0xC0, 0x7E, 0x07, 0xF0,\n  0x7E, 0x01, 0xF8, 0x7C, 0x00, 0x7E, 0x3E, 0x00, 0x1F, 0x3E, 0x00, 0x0F,\n  0x9E, 0x00, 0x07, 0xDF, 0x00, 0x03, 0xEF, 0x80, 0x01, 0xFF, 0x80, 0x00,\n  0xFF, 0xC0, 0x00, 0x7F, 0xE0, 0x00, 0x7D, 0xF0, 0x00, 0x3E, 0xF8, 0x00,\n  0x1F, 0x7C, 0x00, 0x1F, 0x3E, 0x00, 0x1F, 0x9F, 0x80, 0x0F, 0x87, 0xE0,\n  0x0F, 0x83, 0xF8, 0x1F, 0x80, 0xFF, 0xFF, 0x80, 0x3F, 0xFF, 0x80, 0x0F,\n  0xFF, 0x00, 0x01, 0xFE, 0x00, 0x00, 0x07, 0xFF, 0xE0, 0x0F, 0xFF, 0xF0,\n  0x3F, 0xFF, 0xF0, 0x7F, 0xFF, 0xF0, 0xF8, 0x07, 0xE1, 0xF0, 0x07, 0xC3,\n  0xE0, 0x0F, 0x8F, 0xC0, 0x1F, 0x1F, 0x00, 0x3E, 0x3E, 0x00, 0xF8, 0x7C,\n  0x01, 0xF0, 0xF8, 0x07, 0xC3, 0xFF, 0xFF, 0x87, 0xFF, 0xFE, 0x0F, 0xFF,\n  0xF8, 0x1F, 0xFF, 0x80, 0x3E, 0x00, 0x00, 0xFC, 0x00, 0x01, 0xF0, 0x00,\n  0x03, 0xE0, 0x00, 0x07, 0xC0, 0x00, 0x0F, 0x80, 0x00, 0x3F, 0x00, 0x00,\n  0x7C, 0x00, 0x00, 0xF8, 0x00, 0x01, 0xF0, 0x00, 0x00, 0x00, 0x1F, 0xC0,\n  0x00, 0x3F, 0xFC, 0x00, 0x7F, 0xFF, 0x00, 0x7F, 0xFF, 0xC0, 0x7F, 0x07,\n  0xF0, 0x7E, 0x01, 0xF8, 0x7E, 0x00, 0x7E, 0x3E, 0x00, 0x1F, 0x3E, 0x00,\n  0x0F, 0x9E, 0x00, 0x07, 0xDF, 0x00, 0x03, 0xEF, 0x80, 0x01, 0xF7, 0x80,\n  0x00, 0xFF, 0xC0, 0x00, 0x7F, 0xE0, 0x00, 0x7D, 0xF0, 0x00, 0x3E, 0xF8,\n  0x02, 0x1F, 0x7C, 0x03, 0x9F, 0x3E, 0x03, 0xFF, 0x9F, 0x81, 0xFF, 0x87,\n  0xE0, 0x7F, 0x83, 0xF8, 0x3F, 0xC0, 0xFF, 0xFF, 0xE0, 0x3F, 0xFF, 0xF0,\n  0x0F, 0xFF, 0xFC, 0x01, 0xFE, 0x1C, 0x00, 0x00, 0x0C, 0x00, 0x07, 0xFF,\n  0xF8, 0x07, 0xFF, 0xFE, 0x07, 0xFF, 0xFE, 0x0F, 0xFF, 0xFF, 0x0F, 0x80,\n  0x3F, 0x0F, 0x80, 0x1F, 0x0F, 0x80, 0x1F, 0x0F, 0x80, 0x1F, 0x1F, 0x80,\n  0x1E, 0x1F, 0x00, 0x3E, 0x1F, 0x00, 0x7C, 0x1F, 0xFF, 0xF8, 0x1F, 0xFF,\n  0xE0, 0x3F, 0xFF, 0xF0, 0x3F, 0xFF, 0xF8, 0x3E, 0x01, 0xF8, 0x3E, 0x00,\n  0xF8, 0x3E, 0x00, 0xF8, 0x7E, 0x00, 0xF8, 0x7C, 0x00, 0xF8, 0x7C, 0x01,\n  0xF0, 0x7C, 0x01, 0xF0, 0x7C, 0x01, 0xF0, 0xFC, 0x01, 0xF0, 0xF8, 0x01,\n  0xF0, 0xF8, 0x01, 0xF0, 0x00, 0x3F, 0xC0, 0x07, 0xFF, 0xC0, 0x3F, 0xFF,\n  0x81, 0xFF, 0xFF, 0x0F, 0xC0, 0xFC, 0x3E, 0x01, 0xF1, 0xF0, 0x07, 0xC7,\n  0xC0, 0x1F, 0x1F, 0x00, 0x00, 0x7E, 0x00, 0x01, 0xFC, 0x00, 0x07, 0xFF,\n  0x80, 0x0F, 0xFF, 0xC0, 0x1F, 0xFF, 0xC0, 0x1F, 0xFF, 0x80, 0x03, 0xFE,\n  0x00, 0x01, 0xF8, 0x00, 0x03, 0xEF, 0x80, 0x0F, 0xBE, 0x00, 0x3C, 0xFC,\n  0x01, 0xF3, 0xF8, 0x1F, 0x87, 0xFF, 0xFE, 0x0F, 0xFF, 0xF0, 0x1F, 0xFF,\n  0x00, 0x1F, 0xF0, 0x00, 0x7F, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xF0, 0x0F, 0x80, 0x00, 0xFC, 0x00, 0x07, 0xC0, 0x00, 0x3E,\n  0x00, 0x01, 0xF0, 0x00, 0x0F, 0x80, 0x00, 0xFC, 0x00, 0x07, 0xC0, 0x00,\n  0x3E, 0x00, 0x01, 0xF0, 0x00, 0x0F, 0x80, 0x00, 0xFC, 0x00, 0x07, 0xC0,\n  0x00, 0x3E, 0x00, 0x01, 0xF0, 0x00, 0x0F, 0x80, 0x00, 0xFC, 0x00, 0x07,\n  0xC0, 0x00, 0x3E, 0x00, 0x01, 0xF0, 0x00, 0x0F, 0x80, 0x00, 0xFC, 0x00,\n  0x00, 0x0F, 0x80, 0x1F, 0x1F, 0x80, 0x1F, 0x1F, 0x00, 0x1F, 0x1F, 0x00,\n  0x3F, 0x1F, 0x00, 0x3E, 0x1F, 0x00, 0x3E, 0x3E, 0x00, 0x3E, 0x3E, 0x00,\n  0x7E, 0x3E, 0x00, 0x7C, 0x3E, 0x00, 0x7C, 0x3E, 0x00, 0x7C, 0x7C, 0x00,\n  0x7C, 0x7C, 0x00, 0xFC, 0x7C, 0x00, 0xF8, 0x7C, 0x00, 0xF8, 0x7C, 0x00,\n  0xF8, 0xF8, 0x00, 0xF8, 0xF8, 0x01, 0xF8, 0xF8, 0x01, 0xF0, 0xF8, 0x01,\n  0xF0, 0xF8, 0x03, 0xE0, 0xFE, 0x0F, 0xE0, 0x7F, 0xFF, 0xC0, 0x7F, 0xFF,\n  0x80, 0x1F, 0xFE, 0x00, 0x07, 0xF8, 0x00, 0xFC, 0x00, 0x7F, 0xF0, 0x03,\n  0xE7, 0xC0, 0x0F, 0x9F, 0x00, 0x7C, 0x7C, 0x01, 0xF1, 0xF0, 0x0F, 0x87,\n  0xC0, 0x3E, 0x1F, 0x01, 0xF0, 0x7C, 0x07, 0x81, 0xF0, 0x3E, 0x03, 0xC0,\n  0xF0, 0x0F, 0x07, 0xC0, 0x3E, 0x1E, 0x00, 0xF8, 0xF8, 0x03, 0xE3, 0xC0,\n  0x0F, 0x9F, 0x00, 0x3E, 0x78, 0x00, 0xFB, 0xE0, 0x01, 0xEF, 0x00, 0x07,\n  0xFC, 0x00, 0x1F, 0xE0, 0x00, 0x7F, 0x00, 0x01, 0xFC, 0x00, 0x07, 0xE0,\n  0x00, 0x1F, 0x80, 0x00, 0x7C, 0x00, 0x00, 0xF8, 0x07, 0xE0, 0x1F, 0xF8,\n  0x07, 0xE0, 0x3F, 0xF8, 0x0F, 0xE0, 0x3E, 0xF8, 0x0F, 0xE0, 0x7E, 0xF8,\n  0x1F, 0xE0, 0x7C, 0xF8, 0x1F, 0xE0, 0x7C, 0xF8, 0x3F, 0xE0, 0xF8, 0xF8,\n  0x3D, 0xE0, 0xF8, 0x78, 0x3D, 0xE1, 0xF0, 0x78, 0x79, 0xE1, 0xF0, 0x78,\n  0x79, 0xE1, 0xE0, 0x78, 0xF9, 0xE3, 0xE0, 0x78, 0xF1, 0xE3, 0xC0, 0x79,\n  0xF1, 0xE7, 0xC0, 0x79, 0xE1, 0xE7, 0x80, 0x79, 0xE1, 0xE7, 0x80, 0x7B,\n  0xC1, 0xEF, 0x80, 0x7B, 0xC1, 0xEF, 0x00, 0x7F, 0x81, 0xFF, 0x00, 0x7F,\n  0x81, 0xFE, 0x00, 0x7F, 0x01, 0xFE, 0x00, 0x7F, 0x01, 0xFC, 0x00, 0x7F,\n  0x01, 0xFC, 0x00, 0x7E, 0x01, 0xF8, 0x00, 0x3E, 0x01, 0xF8, 0x00, 0x3C,\n  0x01, 0xF0, 0x00, 0x03, 0xF0, 0x07, 0xE0, 0x7E, 0x01, 0xF8, 0x07, 0xE0,\n  0x7E, 0x00, 0xFC, 0x1F, 0x80, 0x1F, 0x83, 0xE0, 0x01, 0xF8, 0xF8, 0x00,\n  0x3F, 0x3F, 0x00, 0x03, 0xEF, 0xC0, 0x00, 0x7F, 0xF0, 0x00, 0x0F, 0xFC,\n  0x00, 0x00, 0xFF, 0x00, 0x00, 0x1F, 0xE0, 0x00, 0x03, 0xF8, 0x00, 0x00,\n  0x7F, 0x00, 0x00, 0x1F, 0xE0, 0x00, 0x07, 0xFE, 0x00, 0x00, 0xFF, 0xC0,\n  0x00, 0x3E, 0xF8, 0x00, 0x0F, 0xDF, 0x80, 0x03, 0xF3, 0xF0, 0x00, 0xFC,\n  0x3F, 0x00, 0x3F, 0x07, 0xE0, 0x07, 0xE0, 0xFC, 0x01, 0xF8, 0x0F, 0xC0,\n  0x7E, 0x01, 0xF8, 0x1F, 0x80, 0x3F, 0x80, 0x7C, 0x00, 0xFD, 0xF8, 0x07,\n  0xE7, 0xE0, 0x1F, 0x1F, 0x80, 0xFC, 0x3E, 0x07, 0xE0, 0xFC, 0x1F, 0x03,\n  0xF0, 0xFC, 0x07, 0xC7, 0xE0, 0x1F, 0x1F, 0x00, 0x7E, 0xFC, 0x00, 0xFB,\n  0xE0, 0x03, 0xFF, 0x00, 0x0F, 0xF8, 0x00, 0x1F, 0xE0, 0x00, 0x7F, 0x00,\n  0x01, 0xF8, 0x00, 0x07, 0xE0, 0x00, 0x1F, 0x00, 0x00, 0x7C, 0x00, 0x01,\n  0xF0, 0x00, 0x07, 0xC0, 0x00, 0x3F, 0x00, 0x00, 0xF8, 0x00, 0x03, 0xE0,\n  0x00, 0x0F, 0x80, 0x00, 0x3E, 0x00, 0x00, 0x07, 0xFF, 0xFF, 0x83, 0xFF,\n  0xFF, 0x81, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xE0, 0x00, 0x07, 0xE0, 0x00,\n  0x07, 0xE0, 0x00, 0x07, 0xE0, 0x00, 0x07, 0xF0, 0x00, 0x07, 0xF0, 0x00,\n  0x07, 0xF0, 0x00, 0x03, 0xF0, 0x00, 0x03, 0xF0, 0x00, 0x03, 0xF0, 0x00,\n  0x03, 0xF0, 0x00, 0x03, 0xF0, 0x00, 0x03, 0xF0, 0x00, 0x03, 0xF0, 0x00,\n  0x03, 0xF0, 0x00, 0x03, 0xF0, 0x00, 0x03, 0xF0, 0x00, 0x03, 0xF8, 0x00,\n  0x03, 0xF8, 0x00, 0x01, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xE0, 0xFF, 0xFF,\n  0xF0, 0x7F, 0xFF, 0xF0, 0x00, 0x01, 0xFE, 0x03, 0xFC, 0x07, 0xF8, 0x1F,\n  0xF0, 0x3C, 0x00, 0x78, 0x00, 0xF0, 0x01, 0xE0, 0x07, 0x80, 0x0F, 0x00,\n  0x1E, 0x00, 0x3C, 0x00, 0xF8, 0x01, 0xE0, 0x03, 0xC0, 0x07, 0x80, 0x0F,\n  0x00, 0x3C, 0x00, 0x78, 0x00, 0xF0, 0x01, 0xE0, 0x07, 0x80, 0x0F, 0x00,\n  0x1E, 0x00, 0x3C, 0x00, 0xF8, 0x01, 0xE0, 0x03, 0xC0, 0x07, 0x80, 0x0F,\n  0xF0, 0x3F, 0xC0, 0x7F, 0x80, 0xFF, 0x00, 0xE7, 0x39, 0xCE, 0x31, 0x8C,\n  0x63, 0x1C, 0xE7, 0x39, 0xCE, 0x31, 0x8C, 0x63, 0x9C, 0xE7, 0x38, 0x01,\n  0xFE, 0x03, 0xFC, 0x07, 0xF8, 0x1F, 0xE0, 0x03, 0xC0, 0x07, 0x80, 0x0F,\n  0x00, 0x3E, 0x00, 0x78, 0x00, 0xF0, 0x01, 0xE0, 0x03, 0xC0, 0x0F, 0x00,\n  0x1E, 0x00, 0x3C, 0x00, 0x78, 0x01, 0xE0, 0x03, 0xC0, 0x07, 0x80, 0x0F,\n  0x00, 0x3E, 0x00, 0x78, 0x00, 0xF0, 0x01, 0xE0, 0x03, 0xC0, 0x0F, 0x00,\n  0x1E, 0x00, 0x3C, 0x00, 0x78, 0x1F, 0xF0, 0x3F, 0xC0, 0x7F, 0x80, 0xFF,\n  0x00, 0x00, 0x7C, 0x00, 0xFC, 0x01, 0xFC, 0x01, 0xFC, 0x03, 0xFC, 0x03,\n  0x9E, 0x07, 0x9E, 0x0F, 0x1E, 0x0F, 0x1E, 0x1E, 0x1E, 0x1C, 0x0F, 0x3C,\n  0x0F, 0x78, 0x0F, 0x78, 0x0F, 0xF0, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFE, 0xF3, 0x8C, 0x71, 0x80, 0x01, 0xFE, 0x01, 0xFF, 0xE0,\n  0xFF, 0xF8, 0x7F, 0xFF, 0x1F, 0x0F, 0xC7, 0x81, 0xF0, 0x00, 0x7C, 0x00,\n  0xFE, 0x07, 0xFF, 0x87, 0xFF, 0xE3, 0xFE, 0xF9, 0xF0, 0x7C, 0xF8, 0x1F,\n  0x3E, 0x0F, 0xCF, 0x87, 0xF3, 0xFF, 0xF8, 0xFF, 0xFE, 0x1F, 0xEF, 0x81,\n  0xE3, 0xF0, 0x07, 0xC0, 0x00, 0x7C, 0x00, 0x07, 0xC0, 0x00, 0x7C, 0x00,\n  0x07, 0x80, 0x00, 0xF8, 0x00, 0x0F, 0x80, 0x00, 0xF9, 0xF8, 0x0F, 0xFF,\n  0xC1, 0xFF, 0xFE, 0x1F, 0xFF, 0xE1, 0xFC, 0x3F, 0x1F, 0x83, 0xF1, 0xF0,\n  0x1F, 0x3E, 0x01, 0xF3, 0xE0, 0x1F, 0x3C, 0x01, 0xF3, 0xC0, 0x1F, 0x3C,\n  0x03, 0xE7, 0xC0, 0x3E, 0x7E, 0x07, 0xC7, 0xF1, 0xFC, 0x7F, 0xFF, 0x87,\n  0xFF, 0xF0, 0xFB, 0xFE, 0x0F, 0x9F, 0x80, 0x00, 0xFC, 0x01, 0xFF, 0xC0,\n  0xFF, 0xF8, 0x7F, 0xFF, 0x3F, 0x0F, 0xCF, 0x81, 0xF7, 0xC0, 0x7D, 0xF0,\n  0x00, 0x7C, 0x00, 0x3E, 0x00, 0x0F, 0x80, 0x03, 0xE0, 0x00, 0xF8, 0x0F,\n  0xBE, 0x07, 0xCF, 0xC3, 0xF1, 0xFF, 0xF8, 0x7F, 0xFC, 0x0F, 0xFE, 0x00,\n  0xFE, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x03, 0xE0, 0x00, 0x0F, 0x80, 0x00,\n  0x3E, 0x00, 0x00, 0xF8, 0x00, 0x07, 0xC0, 0x00, 0x1F, 0x00, 0x7E, 0x7C,\n  0x07, 0xFD, 0xF0, 0x3F, 0xFF, 0xC1, 0xFF, 0xFE, 0x0F, 0xE3, 0xF8, 0x3E,\n  0x07, 0xE1, 0xF0, 0x1F, 0x87, 0xC0, 0x3C, 0x3E, 0x00, 0xF0, 0xF8, 0x07,\n  0xC3, 0xE0, 0x1F, 0x0F, 0x80, 0x7C, 0x3E, 0x03, 0xE0, 0xF8, 0x1F, 0x83,\n  0xF0, 0xFE, 0x07, 0xFF, 0xF8, 0x1F, 0xFF, 0xE0, 0x3F, 0xFF, 0x00, 0x7E,\n  0x7C, 0x00, 0x00, 0xFE, 0x00, 0x7F, 0xE0, 0x3F, 0xFE, 0x0F, 0xFF, 0xE3,\n  0xF0, 0x7E, 0x7C, 0x07, 0xDF, 0x00, 0xFB, 0xE0, 0x1F, 0x7F, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0x00, 0x0F, 0x80, 0x01, 0xF0, 0x1F, 0x3F,\n  0x07, 0xE3, 0xFF, 0xF8, 0x7F, 0xFE, 0x03, 0xFF, 0x00, 0x3F, 0x80, 0x00,\n  0x00, 0xF8, 0x1F, 0xC1, 0xFE, 0x0F, 0xF0, 0x7C, 0x07, 0xC0, 0x3E, 0x0F,\n  0xFE, 0x7F, 0xF3, 0xFF, 0x07, 0xC0, 0x3E, 0x01, 0xF0, 0x0F, 0x80, 0x7C,\n  0x07, 0xC0, 0x3E, 0x01, 0xF0, 0x0F, 0x80, 0x78, 0x07, 0xC0, 0x3E, 0x01,\n  0xF0, 0x0F, 0x80, 0xF8, 0x07, 0xC0, 0x00, 0x00, 0x7C, 0x7C, 0x07, 0xFD,\n  0xF0, 0x3F, 0xF7, 0x81, 0xFF, 0xFE, 0x0F, 0xE3, 0xF8, 0x3E, 0x07, 0xE1,\n  0xF8, 0x0F, 0x87, 0xC0, 0x3C, 0x1E, 0x00, 0xF0, 0xF8, 0x03, 0xC3, 0xE0,\n  0x1F, 0x0F, 0x80, 0x78, 0x3E, 0x03, 0xE0, 0xF8, 0x1F, 0x83, 0xF0, 0xFE,\n  0x07, 0xFF, 0xF8, 0x1F, 0xFF, 0xC0, 0x3F, 0xEF, 0x00, 0x3E, 0x7C, 0x00,\n  0x01, 0xF0, 0x00, 0x07, 0xC3, 0xE0, 0x3E, 0x0F, 0x80, 0xF8, 0x3F, 0x0F,\n  0xC0, 0x7F, 0xFE, 0x00, 0xFF, 0xF0, 0x00, 0xFE, 0x00, 0x00, 0x03, 0xE0,\n  0x00, 0x7C, 0x00, 0x07, 0xC0, 0x00, 0x7C, 0x00, 0x07, 0xC0, 0x00, 0x7C,\n  0x00, 0x0F, 0x80, 0x00, 0xF8, 0xF8, 0x0F, 0xBF, 0xE0, 0xFF, 0xFF, 0x0F,\n  0xFF, 0xF1, 0xFC, 0x3F, 0x1F, 0x81, 0xF1, 0xF0, 0x1F, 0x1F, 0x01, 0xF1,\n  0xE0, 0x1F, 0x3E, 0x03, 0xE3, 0xE0, 0x3E, 0x3E, 0x03, 0xE3, 0xE0, 0x3E,\n  0x7C, 0x03, 0xE7, 0xC0, 0x7C, 0x7C, 0x07, 0xC7, 0xC0, 0x7C, 0x7C, 0x07,\n  0xCF, 0x80, 0x78, 0x07, 0xC1, 0xF0, 0x7C, 0x3E, 0x00, 0x00, 0x00, 0x00,\n  0x3E, 0x1F, 0x07, 0xC1, 0xF0, 0x7C, 0x1F, 0x0F, 0x83, 0xE0, 0xF8, 0x3E,\n  0x0F, 0x87, 0xC1, 0xF0, 0x7C, 0x1F, 0x07, 0xC3, 0xE0, 0xF8, 0x3E, 0x00,\n  0x00, 0x3E, 0x00, 0x78, 0x01, 0xF0, 0x03, 0xE0, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x7C, 0x00, 0xF8, 0x01, 0xF0, 0x03, 0xE0, 0x0F, 0x80, 0x1F,\n  0x00, 0x3E, 0x00, 0x7C, 0x00, 0xF8, 0x03, 0xE0, 0x07, 0xC0, 0x0F, 0x80,\n  0x1F, 0x00, 0x3C, 0x00, 0xF8, 0x01, 0xF0, 0x03, 0xE0, 0x07, 0xC0, 0x1F,\n  0x00, 0x3E, 0x00, 0x7C, 0x00, 0xF8, 0x03, 0xF0, 0x1F, 0xC0, 0x3F, 0x80,\n  0x7E, 0x01, 0xF0, 0x00, 0x07, 0xC0, 0x00, 0x3E, 0x00, 0x01, 0xF0, 0x00,\n  0x0F, 0x80, 0x00, 0x78, 0x00, 0x07, 0xC0, 0x00, 0x3E, 0x00, 0x01, 0xF0,\n  0x3E, 0x0F, 0x83, 0xE0, 0xF8, 0x3E, 0x07, 0xC7, 0xE0, 0x3E, 0x7E, 0x01,\n  0xF7, 0xE0, 0x0F, 0xFE, 0x00, 0xFF, 0xE0, 0x07, 0xFF, 0x00, 0x3F, 0xFC,\n  0x01, 0xFF, 0xE0, 0x0F, 0xDF, 0x00, 0xFC, 0xFC, 0x07, 0xC3, 0xE0, 0x3E,\n  0x1F, 0x01, 0xF0, 0xFC, 0x0F, 0x83, 0xE0, 0xF8, 0x1F, 0x87, 0xC0, 0xFC,\n  0x00, 0x07, 0xC1, 0xF0, 0x7C, 0x3E, 0x0F, 0x83, 0xE0, 0xF8, 0x3E, 0x1F,\n  0x07, 0xC1, 0xF0, 0x7C, 0x1F, 0x0F, 0x83, 0xE0, 0xF8, 0x3E, 0x0F, 0x87,\n  0xC1, 0xF0, 0x7C, 0x1F, 0x07, 0xC3, 0xE0, 0xF8, 0x3E, 0x00, 0x0F, 0x8F,\n  0x83, 0xF0, 0x3E, 0xFF, 0x3F, 0xE0, 0xF7, 0xFF, 0xFF, 0xC7, 0xFF, 0xFF,\n  0xFF, 0x1F, 0xC7, 0xF8, 0x7C, 0x7C, 0x0F, 0x81, 0xF1, 0xF0, 0x3E, 0x07,\n  0xCF, 0x81, 0xF0, 0x3E, 0x3E, 0x07, 0xC0, 0xF8, 0xF8, 0x1F, 0x03, 0xE3,\n  0xE0, 0x7C, 0x0F, 0x8F, 0x81, 0xF0, 0x3E, 0x7C, 0x0F, 0x81, 0xF1, 0xF0,\n  0x3E, 0x07, 0xC7, 0xC0, 0xF8, 0x1F, 0x1F, 0x03, 0xE0, 0x7C, 0x7C, 0x0F,\n  0x81, 0xE3, 0xE0, 0x7C, 0x0F, 0x8F, 0x81, 0xF0, 0x3E, 0x00, 0x0F, 0x8F,\n  0x80, 0xFB, 0xFE, 0x0F, 0xFF, 0xF1, 0xFF, 0xFF, 0x1F, 0xC3, 0xF1, 0xF8,\n  0x1F, 0x1F, 0x01, 0xF1, 0xF0, 0x1F, 0x3E, 0x01, 0xF3, 0xE0, 0x3E, 0x3E,\n  0x03, 0xE3, 0xE0, 0x3E, 0x3C, 0x03, 0xE7, 0xC0, 0x3E, 0x7C, 0x07, 0xC7,\n  0xC0, 0x7C, 0x7C, 0x07, 0xC7, 0x80, 0x7C, 0xF8, 0x07, 0x80, 0x00, 0xFE,\n  0x00, 0x7F, 0xF0, 0x3F, 0xFF, 0x0F, 0xFF, 0xE3, 0xF8, 0xFE, 0x7C, 0x0F,\n  0xDF, 0x00, 0xFB, 0xE0, 0x1F, 0xF8, 0x03, 0xFF, 0x00, 0x7F, 0xE0, 0x1F,\n  0xFC, 0x03, 0xEF, 0x80, 0x7D, 0xF8, 0x1F, 0x3F, 0x07, 0xE3, 0xFF, 0xF8,\n  0x7F, 0xFE, 0x07, 0xFF, 0x00, 0x3F, 0x80, 0x00, 0x03, 0xE7, 0xE0, 0x0F,\n  0xBF, 0xC0, 0x7D, 0xFF, 0x81, 0xFF, 0xFE, 0x07, 0xF0, 0xFC, 0x1F, 0x81,\n  0xF0, 0x7C, 0x07, 0xC3, 0xE0, 0x1F, 0x0F, 0x80, 0x7C, 0x3E, 0x01, 0xF0,\n  0xF0, 0x07, 0xC3, 0xC0, 0x3E, 0x1F, 0x00, 0xF8, 0x7E, 0x07, 0xC1, 0xFC,\n  0x7F, 0x07, 0xFF, 0xF8, 0x1F, 0xFF, 0xC0, 0xFB, 0xFE, 0x03, 0xE7, 0xE0,\n  0x0F, 0x80, 0x00, 0x3E, 0x00, 0x00, 0xF0, 0x00, 0x07, 0xC0, 0x00, 0x1F,\n  0x00, 0x00, 0x7C, 0x00, 0x01, 0xF0, 0x00, 0x0F, 0x80, 0x00, 0x00, 0x01,\n  0xF1, 0xF0, 0x7F, 0xDF, 0x0F, 0xFD, 0xF1, 0xFF, 0xFE, 0x3F, 0x8F, 0xE3,\n  0xE0, 0x7E, 0x7C, 0x03, 0xE7, 0xC0, 0x3E, 0xF8, 0x03, 0xCF, 0x80, 0x3C,\n  0xF8, 0x07, 0xCF, 0x80, 0x7C, 0xF8, 0x0F, 0x8F, 0x81, 0xF8, 0xFC, 0x3F,\n  0x87, 0xFF, 0xF8, 0x7F, 0xFF, 0x83, 0xFF, 0xF0, 0x1F, 0x9F, 0x00, 0x01,\n  0xF0, 0x00, 0x1F, 0x00, 0x01, 0xF0, 0x00, 0x3E, 0x00, 0x03, 0xE0, 0x00,\n  0x3E, 0x00, 0x03, 0xE0, 0x00, 0x3E, 0x00, 0x0F, 0x8E, 0x1F, 0x7C, 0x3F,\n  0xF0, 0xFF, 0xE1, 0xFC, 0x03, 0xF0, 0x07, 0xC0, 0x0F, 0x80, 0x3E, 0x00,\n  0x7C, 0x00, 0xF8, 0x01, 0xF0, 0x03, 0xE0, 0x0F, 0x80, 0x1F, 0x00, 0x3E,\n  0x00, 0x7C, 0x00, 0xF0, 0x03, 0xE0, 0x00, 0x01, 0xFC, 0x01, 0xFF, 0xC0,\n  0xFF, 0xF8, 0x7F, 0xFF, 0x3F, 0x0F, 0xCF, 0x81, 0xF3, 0xF0, 0x00, 0xFF,\n  0x80, 0x3F, 0xFC, 0x07, 0xFF, 0xC0, 0x7F, 0xF8, 0x03, 0xFE, 0x00, 0x1F,\n  0xBE, 0x03, 0xEF, 0xC1, 0xFB, 0xFF, 0xFC, 0x7F, 0xFE, 0x0F, 0xFF, 0x00,\n  0xFE, 0x00, 0x0F, 0x81, 0xF0, 0x7C, 0x0F, 0x81, 0xF0, 0xFF, 0xBF, 0xF7,\n  0xFE, 0x3E, 0x07, 0xC0, 0xF8, 0x3E, 0x07, 0xC0, 0xF8, 0x1F, 0x03, 0xE0,\n  0xF8, 0x1F, 0x03, 0xE0, 0x7F, 0x0F, 0xE1, 0xFC, 0x1F, 0x80, 0x1F, 0x01,\n  0xF1, 0xF0, 0x1F, 0x3E, 0x03, 0xE3, 0xE0, 0x3E, 0x3E, 0x03, 0xE3, 0xE0,\n  0x3E, 0x3E, 0x03, 0xE7, 0xC0, 0x7C, 0x7C, 0x07, 0xC7, 0xC0, 0x7C, 0x7C,\n  0x07, 0xC7, 0xC0, 0x7C, 0xF8, 0x0F, 0x8F, 0x81, 0xF8, 0xF8, 0x3F, 0x8F,\n  0xFF, 0xF8, 0xFF, 0xFF, 0x07, 0xFD, 0xF0, 0x3F, 0x1F, 0x00, 0xF8, 0x0F,\n  0xFE, 0x03, 0xEF, 0x81, 0xF3, 0xE0, 0x7C, 0xF8, 0x3E, 0x3E, 0x0F, 0x8F,\n  0x87, 0xC1, 0xE1, 0xF0, 0x78, 0xF8, 0x1E, 0x3E, 0x07, 0x9F, 0x01, 0xF7,\n  0x80, 0x7F, 0xE0, 0x1F, 0xF0, 0x03, 0xFC, 0x00, 0xFE, 0x00, 0x3F, 0x80,\n  0x0F, 0xC0, 0x03, 0xF0, 0x00, 0xF8, 0x1F, 0x07, 0xFF, 0x03, 0xE0, 0xFB,\n  0xE0, 0xFC, 0x1F, 0x7C, 0x1F, 0x87, 0xCF, 0x87, 0xF0, 0xF9, 0xF0, 0xFE,\n  0x3E, 0x3E, 0x3D, 0xC7, 0xC3, 0xC7, 0xB9, 0xF0, 0x79, 0xE7, 0x3E, 0x0F,\n  0x3C, 0xE7, 0x81, 0xEF, 0x1D, 0xF0, 0x3D, 0xE3, 0xBC, 0x07, 0xBC, 0x7F,\n  0x80, 0xFF, 0x0F, 0xE0, 0x1F, 0xE1, 0xFC, 0x03, 0xF8, 0x3F, 0x00, 0x7F,\n  0x07, 0xE0, 0x0F, 0xC0, 0xF8, 0x01, 0xF8, 0x1F, 0x00, 0x00, 0x0F, 0xC1,\n  0xF8, 0x3F, 0x07, 0xC0, 0x7C, 0x3E, 0x01, 0xF9, 0xF8, 0x03, 0xEF, 0xC0,\n  0x0F, 0xBE, 0x00, 0x1F, 0xF0, 0x00, 0x7F, 0x80, 0x01, 0xFC, 0x00, 0x03,\n  0xE0, 0x00, 0x1F, 0xC0, 0x00, 0xFF, 0x00, 0x07, 0xFE, 0x00, 0x3E, 0xF8,\n  0x01, 0xFB, 0xF0, 0x07, 0xC7, 0xC0, 0x3E, 0x1F, 0x81, 0xF8, 0x7E, 0x0F,\n  0xC0, 0xF8, 0x00, 0x1F, 0x80, 0x7C, 0x3E, 0x03, 0xE0, 0xF8, 0x0F, 0x03,\n  0xE0, 0x7C, 0x0F, 0x81, 0xE0, 0x3E, 0x0F, 0x80, 0xF8, 0x3C, 0x03, 0xE1,\n  0xF0, 0x07, 0x87, 0x80, 0x1F, 0x3E, 0x00, 0x7C, 0xF0, 0x01, 0xF7, 0xC0,\n  0x07, 0xDE, 0x00, 0x1F, 0xF0, 0x00, 0x7F, 0xC0, 0x01, 0xFE, 0x00, 0x03,\n  0xF8, 0x00, 0x0F, 0xC0, 0x00, 0x3F, 0x00, 0x00, 0xF8, 0x00, 0x03, 0xE0,\n  0x00, 0x1F, 0x00, 0x00, 0xF8, 0x00, 0x1F, 0xE0, 0x00, 0x7F, 0x00, 0x01,\n  0xF8, 0x00, 0x0F, 0x80, 0x00, 0x00, 0x0F, 0xFF, 0xE1, 0xFF, 0xFC, 0x3F,\n  0xFF, 0x87, 0xFF, 0xE0, 0x00, 0xFC, 0x00, 0x3F, 0x00, 0x0F, 0xC0, 0x03,\n  0xF0, 0x01, 0xFC, 0x00, 0x7E, 0x00, 0x1F, 0x80, 0x07, 0xE0, 0x01, 0xF8,\n  0x00, 0x7E, 0x00, 0x1F, 0x80, 0x07, 0xFF, 0xF8, 0xFF, 0xFF, 0x1F, 0xFF,\n  0xE3, 0xFF, 0xFC, 0x00, 0x00, 0x7C, 0x03, 0xF0, 0x1F, 0xC0, 0xFE, 0x03,\n  0xE0, 0x0F, 0x00, 0x3C, 0x00, 0xF0, 0x07, 0x80, 0x1E, 0x00, 0x78, 0x01,\n  0xE0, 0x0F, 0x80, 0x3C, 0x01, 0xF0, 0x1F, 0x80, 0x70, 0x01, 0xF8, 0x01,\n  0xE0, 0x07, 0x80, 0x1E, 0x00, 0x78, 0x03, 0xC0, 0x0F, 0x00, 0x3C, 0x00,\n  0xF0, 0x07, 0x80, 0x1E, 0x00, 0x78, 0x01, 0xFC, 0x07, 0xE0, 0x0F, 0x80,\n  0x1E, 0x00, 0x03, 0x81, 0xC0, 0xC0, 0xE0, 0x70, 0x38, 0x1C, 0x0C, 0x0E,\n  0x07, 0x03, 0x81, 0xC0, 0xC0, 0xE0, 0x70, 0x38, 0x18, 0x1C, 0x0E, 0x07,\n  0x03, 0x81, 0x81, 0xC0, 0xE0, 0x70, 0x38, 0x18, 0x1C, 0x0E, 0x07, 0x01,\n  0x80, 0x80, 0x00, 0x00, 0x01, 0xE0, 0x07, 0xC0, 0x1F, 0x80, 0xFE, 0x00,\n  0x78, 0x01, 0xE0, 0x07, 0x80, 0x3C, 0x00, 0xF0, 0x03, 0xC0, 0x0F, 0x00,\n  0x78, 0x01, 0xE0, 0x07, 0x80, 0x1E, 0x00, 0x7E, 0x00, 0x38, 0x07, 0xE0,\n  0x3E, 0x00, 0xF0, 0x07, 0xC0, 0x1E, 0x00, 0x78, 0x01, 0xE0, 0x07, 0x80,\n  0x3C, 0x00, 0xF0, 0x03, 0xC0, 0x1F, 0x01, 0xF8, 0x0F, 0xE0, 0x3F, 0x00,\n  0xF8, 0x00, 0x0F, 0x00, 0x1F, 0xC1, 0xDF, 0xF0, 0xEE, 0x3F, 0xE6, 0x07,\n  0xF0, 0x01, 0xE0 };\n\nconst GFXglyph FreeSansBoldOblique18pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,  10,    0,    1 },   // 0x20 ' '\n  {     0,  10,  25,  12,    4,  -24 },   // 0x21 '!'\n  {    32,  13,   9,  17,    6,  -25 },   // 0x22 '\"'\n  {    47,  22,  24,  19,    1,  -23 },   // 0x23 '#'\n  {   113,  19,  31,  19,    2,  -26 },   // 0x24 '$'\n  {   187,  26,  26,  31,    5,  -25 },   // 0x25 '%'\n  {   272,  21,  25,  25,    3,  -24 },   // 0x26 '&'\n  {   338,   5,   9,   8,    6,  -25 },   // 0x27 '''\n  {   344,  13,  33,  12,    3,  -25 },   // 0x28 '('\n  {   398,  13,  33,  12,   -1,  -25 },   // 0x29 ')'\n  {   452,  12,  11,  14,    5,  -25 },   // 0x2A '*'\n  {   469,  18,  16,  20,    3,  -15 },   // 0x2B '+'\n  {   505,   7,  11,  10,    1,   -4 },   // 0x2C ','\n  {   515,  10,   4,  12,    2,  -10 },   // 0x2D '-'\n  {   520,   6,   5,  10,    2,   -4 },   // 0x2E '.'\n  {   524,  15,  25,  10,    0,  -24 },   // 0x2F '/'\n  {   571,  18,  25,  19,    3,  -24 },   // 0x30 '0'\n  {   628,  13,  25,  19,    6,  -24 },   // 0x31 '1'\n  {   669,  21,  25,  19,    1,  -24 },   // 0x32 '2'\n  {   735,  20,  25,  19,    2,  -24 },   // 0x33 '3'\n  {   798,  19,  25,  19,    2,  -24 },   // 0x34 '4'\n  {   858,  20,  24,  19,    2,  -23 },   // 0x35 '5'\n  {   918,  19,  25,  19,    3,  -24 },   // 0x36 '6'\n  {   978,  19,  24,  19,    5,  -23 },   // 0x37 '7'\n  {  1035,  20,  25,  19,    2,  -24 },   // 0x38 '8'\n  {  1098,  19,  25,  19,    2,  -24 },   // 0x39 '9'\n  {  1158,   9,  18,  12,    4,  -17 },   // 0x3A ':'\n  {  1179,  10,  24,  12,    3,  -17 },   // 0x3B ';'\n  {  1209,  19,  17,  20,    3,  -16 },   // 0x3C '<'\n  {  1250,  20,  12,  20,    2,  -13 },   // 0x3D '='\n  {  1280,  19,  17,  20,    1,  -15 },   // 0x3E '>'\n  {  1321,  18,  26,  21,    6,  -25 },   // 0x3F '?'\n  {  1380,  33,  31,  34,    3,  -25 },   // 0x40 '@'\n  {  1508,  23,  26,  25,    1,  -25 },   // 0x41 'A'\n  {  1583,  24,  26,  25,    3,  -25 },   // 0x42 'B'\n  {  1661,  24,  26,  25,    4,  -25 },   // 0x43 'C'\n  {  1739,  24,  26,  25,    3,  -25 },   // 0x44 'D'\n  {  1817,  24,  26,  23,    3,  -25 },   // 0x45 'E'\n  {  1895,  23,  26,  21,    3,  -25 },   // 0x46 'F'\n  {  1970,  24,  26,  27,    4,  -25 },   // 0x47 'G'\n  {  2048,  26,  26,  25,    2,  -25 },   // 0x48 'H'\n  {  2133,  10,  26,  10,    2,  -25 },   // 0x49 'I'\n  {  2166,  20,  26,  19,    2,  -25 },   // 0x4A 'J'\n  {  2231,  26,  26,  25,    3,  -25 },   // 0x4B 'K'\n  {  2316,  18,  26,  21,    3,  -25 },   // 0x4C 'L'\n  {  2375,  31,  26,  29,    2,  -25 },   // 0x4D 'M'\n  {  2476,  27,  26,  25,    2,  -25 },   // 0x4E 'N'\n  {  2564,  25,  26,  27,    4,  -25 },   // 0x4F 'O'\n  {  2646,  23,  26,  23,    3,  -25 },   // 0x50 'P'\n  {  2721,  25,  27,  27,    4,  -25 },   // 0x51 'Q'\n  {  2806,  24,  26,  25,    3,  -25 },   // 0x52 'R'\n  {  2884,  22,  26,  23,    3,  -25 },   // 0x53 'S'\n  {  2956,  21,  26,  21,    5,  -25 },   // 0x54 'T'\n  {  3025,  24,  26,  25,    4,  -25 },   // 0x55 'U'\n  {  3103,  22,  26,  23,    6,  -25 },   // 0x56 'V'\n  {  3175,  32,  26,  33,    6,  -25 },   // 0x57 'W'\n  {  3279,  27,  26,  23,    1,  -25 },   // 0x58 'X'\n  {  3367,  22,  26,  23,    6,  -25 },   // 0x59 'Y'\n  {  3439,  25,  26,  21,    1,  -25 },   // 0x5A 'Z'\n  {  3521,  15,  33,  12,    1,  -25 },   // 0x5B '['\n  {  3583,   5,  25,  10,    5,  -24 },   // 0x5C '\\'\n  {  3599,  15,  33,  12,   -1,  -25 },   // 0x5D ']'\n  {  3661,  16,  15,  20,    4,  -23 },   // 0x5E '^'\n  {  3691,  21,   3,  19,   -2,    5 },   // 0x5F '_'\n  {  3699,   5,   5,  12,    6,  -25 },   // 0x60 '`'\n  {  3703,  18,  19,  19,    2,  -18 },   // 0x61 'a'\n  {  3746,  20,  26,  21,    2,  -25 },   // 0x62 'b'\n  {  3811,  18,  19,  19,    3,  -18 },   // 0x63 'c'\n  {  3854,  22,  26,  21,    3,  -25 },   // 0x64 'd'\n  {  3926,  19,  19,  19,    2,  -18 },   // 0x65 'e'\n  {  3972,  13,  26,  12,    3,  -25 },   // 0x66 'f'\n  {  4015,  22,  27,  21,    1,  -18 },   // 0x67 'g'\n  {  4090,  20,  26,  21,    2,  -25 },   // 0x68 'h'\n  {  4155,  10,  26,  10,    2,  -25 },   // 0x69 'i'\n  {  4188,  15,  34,  10,   -2,  -25 },   // 0x6A 'j'\n  {  4252,  21,  26,  19,    2,  -25 },   // 0x6B 'k'\n  {  4321,  10,  26,  10,    2,  -25 },   // 0x6C 'l'\n  {  4354,  30,  19,  31,    2,  -18 },   // 0x6D 'm'\n  {  4426,  20,  19,  21,    2,  -18 },   // 0x6E 'n'\n  {  4474,  19,  19,  21,    3,  -18 },   // 0x6F 'o'\n  {  4520,  22,  27,  21,    0,  -18 },   // 0x70 'p'\n  {  4595,  20,  27,  21,    3,  -18 },   // 0x71 'q'\n  {  4663,  15,  19,  14,    2,  -18 },   // 0x72 'r'\n  {  4699,  18,  19,  19,    2,  -18 },   // 0x73 's'\n  {  4742,  11,  23,  12,    4,  -22 },   // 0x74 't'\n  {  4774,  20,  19,  21,    3,  -18 },   // 0x75 'u'\n  {  4822,  18,  19,  19,    5,  -18 },   // 0x76 'v'\n  {  4865,  27,  19,  27,    4,  -18 },   // 0x77 'w'\n  {  4930,  22,  19,  19,    1,  -18 },   // 0x78 'x'\n  {  4983,  22,  27,  19,    1,  -18 },   // 0x79 'y'\n  {  5058,  19,  19,  17,    1,  -18 },   // 0x7A 'z'\n  {  5104,  14,  33,  14,    2,  -25 },   // 0x7B '{'\n  {  5162,   9,  33,  10,    2,  -25 },   // 0x7C '|'\n  {  5200,  14,  33,  14,    2,  -25 },   // 0x7D '}'\n  {  5258,  17,   6,  20,    3,  -10 } }; // 0x7E '~'\n\nconst GFXfont FreeSansBoldOblique18pt7b PROGMEM = {\n  (uint8_t  *)FreeSansBoldOblique18pt7bBitmaps,\n  (GFXglyph *)FreeSansBoldOblique18pt7bGlyphs,\n  0x20, 0x7E, 42 };\n\n// Approx. 5943 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeSansBoldOblique24pt7b.h",
    "content": "const uint8_t FreeSansBoldOblique24pt7bBitmaps[] PROGMEM = {\n  0x01, 0xE0, 0x07, 0xF0, 0x1F, 0xC0, 0xFF, 0x03, 0xF8, 0x0F, 0xE0, 0x3F,\n  0x80, 0xFE, 0x07, 0xF0, 0x1F, 0xC0, 0x7F, 0x01, 0xFC, 0x07, 0xE0, 0x1F,\n  0x80, 0x7E, 0x01, 0xF0, 0x07, 0xC0, 0x1F, 0x00, 0xF8, 0x03, 0xE0, 0x0F,\n  0x80, 0x3C, 0x00, 0xF0, 0x03, 0xC0, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x1F,\n  0xC0, 0x7F, 0x01, 0xFC, 0x07, 0xF0, 0x1F, 0xC0, 0xFE, 0x03, 0xF8, 0x00,\n  0x7E, 0x0F, 0xDF, 0x83, 0xF7, 0xE0, 0xFF, 0xF0, 0x7E, 0xFC, 0x1F, 0xBF,\n  0x07, 0xEF, 0xC1, 0xFB, 0xE0, 0x7C, 0xF8, 0x1F, 0x3C, 0x07, 0x8F, 0x01,\n  0xE3, 0x80, 0x70, 0x00, 0x07, 0xC1, 0xF0, 0x00, 0x3E, 0x0F, 0x80, 0x03,\n  0xE0, 0xF8, 0x00, 0x1F, 0x07, 0xC0, 0x01, 0xF0, 0x7C, 0x00, 0x0F, 0x83,\n  0xE0, 0x00, 0xF8, 0x3E, 0x00, 0xFF, 0xFF, 0xFF, 0x0F, 0xFF, 0xFF, 0xF8,\n  0x7F, 0xFF, 0xFF, 0xC3, 0xFF, 0xFF, 0xFC, 0x1F, 0xFF, 0xFF, 0xE0, 0x0F,\n  0x83, 0xE0, 0x00, 0x7C, 0x3E, 0x00, 0x07, 0xC1, 0xF0, 0x00, 0x3E, 0x0F,\n  0x80, 0x03, 0xE0, 0xF8, 0x00, 0x1F, 0x07, 0xC0, 0x00, 0xF8, 0x7C, 0x00,\n  0xFF, 0xFF, 0xFF, 0x0F, 0xFF, 0xFF, 0xF8, 0x7F, 0xFF, 0xFF, 0x83, 0xFF,\n  0xFF, 0xFC, 0x1F, 0xFF, 0xFF, 0xE0, 0x1F, 0x07, 0xC0, 0x00, 0xF8, 0x3E,\n  0x00, 0x0F, 0x83, 0xE0, 0x00, 0x7C, 0x1F, 0x00, 0x07, 0xC1, 0xF0, 0x00,\n  0x3E, 0x0F, 0x80, 0x01, 0xF0, 0xF8, 0x00, 0x1F, 0x07, 0xC0, 0x00, 0xF8,\n  0x3C, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x38, 0x00, 0x00, 0x0E,\n  0x00, 0x00, 0x3F, 0xF0, 0x00, 0x7F, 0xFF, 0x00, 0x3F, 0xFF, 0xE0, 0x1F,\n  0xFF, 0xF8, 0x0F, 0xFF, 0xFF, 0x07, 0xF3, 0x9F, 0xC1, 0xF8, 0xE3, 0xF0,\n  0x7C, 0x38, 0xFC, 0x3F, 0x0E, 0x3F, 0x0F, 0xC7, 0x8F, 0xC3, 0xF1, 0xC0,\n  0x00, 0xFE, 0x70, 0x00, 0x3F, 0xDC, 0x00, 0x0F, 0xFF, 0x00, 0x01, 0xFF,\n  0xE0, 0x00, 0x3F, 0xFE, 0x00, 0x0F, 0xFF, 0xE0, 0x00, 0xFF, 0xFC, 0x00,\n  0x0F, 0xFF, 0x00, 0x01, 0xFF, 0xE0, 0x00, 0x77, 0xF8, 0x00, 0x1C, 0xFE,\n  0x00, 0x07, 0x3F, 0x8F, 0xE3, 0xCF, 0xE3, 0xF8, 0xE3, 0xF8, 0xFE, 0x38,\n  0xFC, 0x3F, 0x8E, 0x7F, 0x0F, 0xF3, 0x9F, 0xC3, 0xFD, 0xFF, 0xE0, 0x7F,\n  0xFF, 0xF0, 0x1F, 0xFF, 0xFC, 0x03, 0xFF, 0xFC, 0x00, 0x7F, 0xFE, 0x00,\n  0x03, 0xFC, 0x00, 0x00, 0x38, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x03, 0x80,\n  0x00, 0x01, 0xE0, 0x00, 0x00, 0x70, 0x00, 0x00, 0x01, 0xF8, 0x00, 0x07,\n  0x80, 0x7F, 0xE0, 0x00, 0xF0, 0x0F, 0xFF, 0x00, 0x1E, 0x01, 0xFF, 0xF0,\n  0x01, 0xC0, 0x3F, 0xFF, 0x80, 0x3C, 0x07, 0xE1, 0xF8, 0x07, 0x80, 0x78,\n  0x07, 0x80, 0xF0, 0x0F, 0x80, 0x78, 0x0E, 0x00, 0xF0, 0x07, 0x81, 0xC0,\n  0x0F, 0x00, 0xF8, 0x3C, 0x00, 0xF0, 0x0F, 0x07, 0x80, 0x0F, 0xC3, 0xF0,\n  0xF0, 0x00, 0xFF, 0xFE, 0x0E, 0x00, 0x07, 0xFF, 0xC1, 0xE0, 0x00, 0x7F,\n  0xF8, 0x3C, 0x00, 0x03, 0xFF, 0x07, 0x80, 0x00, 0x0F, 0xC0, 0x70, 0x00,\n  0x00, 0x00, 0x0E, 0x03, 0xF0, 0x00, 0x01, 0xE0, 0xFF, 0xC0, 0x00, 0x3C,\n  0x1F, 0xFE, 0x00, 0x03, 0x83, 0xFF, 0xE0, 0x00, 0x70, 0x7F, 0xFF, 0x00,\n  0x0F, 0x0F, 0xC3, 0xF0, 0x01, 0xE0, 0xF0, 0x0F, 0x00, 0x3C, 0x1F, 0x00,\n  0xF0, 0x03, 0x81, 0xE0, 0x0F, 0x00, 0x78, 0x1E, 0x01, 0xF0, 0x0F, 0x01,\n  0xE0, 0x1E, 0x01, 0xE0, 0x1F, 0x87, 0xE0, 0x1C, 0x01, 0xFF, 0xFC, 0x03,\n  0x80, 0x0F, 0xFF, 0x80, 0x78, 0x00, 0xFF, 0xF0, 0x0F, 0x00, 0x07, 0xFE,\n  0x01, 0xE0, 0x00, 0x1F, 0x80, 0x00, 0x01, 0xF8, 0x00, 0x00, 0x3F, 0xF0,\n  0x00, 0x07, 0xFF, 0xC0, 0x00, 0x7F, 0xFF, 0x00, 0x03, 0xFF, 0xF8, 0x00,\n  0x3F, 0x9F, 0xC0, 0x03, 0xF8, 0x7E, 0x00, 0x1F, 0xC3, 0xF0, 0x00, 0xFE,\n  0x1F, 0x00, 0x07, 0xF1, 0xF8, 0x00, 0x3F, 0xCF, 0xC0, 0x01, 0xFE, 0xFC,\n  0x00, 0x07, 0xFF, 0xC0, 0x00, 0x3F, 0xFC, 0x00, 0x00, 0xFF, 0xC0, 0x00,\n  0x07, 0xF8, 0x00, 0x00, 0xFF, 0xC0, 0x00, 0x1F, 0xFF, 0x07, 0xC1, 0xFF,\n  0xF8, 0x3E, 0x3F, 0xFF, 0xE3, 0xE3, 0xFE, 0x3F, 0x1F, 0x1F, 0xC1, 0xFD,\n  0xF1, 0xFC, 0x07, 0xFF, 0x8F, 0xC0, 0x3F, 0xF8, 0xFE, 0x00, 0xFF, 0xC7,\n  0xF0, 0x07, 0xFC, 0x3F, 0x80, 0x1F, 0xC1, 0xFC, 0x00, 0xFE, 0x0F, 0xF0,\n  0x1F, 0xF8, 0x7F, 0xC1, 0xFF, 0xC1, 0xFF, 0xFF, 0xFF, 0x0F, 0xFF, 0xFF,\n  0xFC, 0x3F, 0xFF, 0xCF, 0xE0, 0x7F, 0xF8, 0x7F, 0x80, 0xFF, 0x00, 0x00,\n  0x7E, 0xFD, 0xFF, 0xEF, 0xDF, 0xBF, 0x7C, 0xF9, 0xE3, 0xC7, 0x00, 0x00,\n  0x0F, 0x80, 0x0F, 0x80, 0x0F, 0x80, 0x0F, 0xC0, 0x07, 0xC0, 0x07, 0xC0,\n  0x07, 0xE0, 0x03, 0xE0, 0x03, 0xE0, 0x03, 0xF0, 0x01, 0xF0, 0x01, 0xF8,\n  0x00, 0xF8, 0x00, 0xFC, 0x00, 0x7C, 0x00, 0x7E, 0x00, 0x3E, 0x00, 0x1F,\n  0x00, 0x1F, 0x80, 0x0F, 0x80, 0x07, 0xC0, 0x03, 0xE0, 0x03, 0xF0, 0x01,\n  0xF0, 0x00, 0xF8, 0x00, 0x7C, 0x00, 0x3E, 0x00, 0x1F, 0x00, 0x0F, 0x80,\n  0x07, 0xC0, 0x03, 0xE0, 0x01, 0xF0, 0x00, 0xF8, 0x00, 0x7C, 0x00, 0x1E,\n  0x00, 0x0F, 0x80, 0x07, 0xC0, 0x03, 0xE0, 0x01, 0xF0, 0x00, 0x7C, 0x00,\n  0x3E, 0x00, 0x1F, 0x00, 0x07, 0x80, 0x03, 0xE0, 0x00, 0x00, 0x7C, 0x00,\n  0x1E, 0x00, 0x0F, 0x80, 0x07, 0xC0, 0x03, 0xE0, 0x00, 0xF0, 0x00, 0x7C,\n  0x00, 0x3E, 0x00, 0x1F, 0x00, 0x07, 0x80, 0x03, 0xE0, 0x01, 0xF0, 0x00,\n  0xF8, 0x00, 0x7C, 0x00, 0x3E, 0x00, 0x1F, 0x00, 0x0F, 0x80, 0x07, 0xC0,\n  0x03, 0xE0, 0x01, 0xF0, 0x00, 0xF8, 0x00, 0xF8, 0x00, 0x7C, 0x00, 0x3E,\n  0x00, 0x1F, 0x00, 0x1F, 0x80, 0x0F, 0x80, 0x07, 0xC0, 0x07, 0xE0, 0x03,\n  0xE0, 0x03, 0xF0, 0x01, 0xF0, 0x01, 0xF8, 0x00, 0xF8, 0x00, 0xFC, 0x00,\n  0x7C, 0x00, 0x7C, 0x00, 0x7E, 0x00, 0x3E, 0x00, 0x3E, 0x00, 0x3F, 0x00,\n  0x1F, 0x00, 0x1F, 0x00, 0x1F, 0x00, 0x00, 0x01, 0xE0, 0x03, 0x80, 0x07,\n  0x00, 0x0E, 0x07, 0x3C, 0x6F, 0xFF, 0xFF, 0xFF, 0xBF, 0xFE, 0x0F, 0xE0,\n  0x1F, 0xC0, 0x7F, 0x81, 0xEF, 0x87, 0x8F, 0x0E, 0x1E, 0x08, 0x10, 0x00,\n  0x00, 0x0F, 0x80, 0x00, 0x1F, 0x80, 0x00, 0x1F, 0x80, 0x00, 0x1F, 0x00,\n  0x00, 0x1F, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x3F, 0x00,\n  0x7F, 0xFF, 0xFF, 0x7F, 0xFF, 0xFF, 0x7F, 0xFF, 0xFF, 0x7F, 0xFF, 0xFE,\n  0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFE, 0x00, 0xFC, 0x00, 0x00, 0xFC, 0x00,\n  0x00, 0xFC, 0x00, 0x00, 0xF8, 0x00, 0x00, 0xF8, 0x00, 0x01, 0xF8, 0x00,\n  0x01, 0xF8, 0x00, 0x01, 0xF8, 0x00, 0x1F, 0xC7, 0xF1, 0xF8, 0xFE, 0x3F,\n  0x8F, 0xE0, 0x38, 0x1C, 0x07, 0x03, 0xC0, 0xE0, 0xF0, 0xFC, 0x3C, 0x0C,\n  0x00, 0x7F, 0xFD, 0xFF, 0xF7, 0xFF, 0x9F, 0xFE, 0xFF, 0xFB, 0xFF, 0xE0,\n  0x7F, 0x7F, 0x7F, 0x7E, 0xFE, 0xFE, 0xFE, 0x00, 0x00, 0x70, 0x00, 0x0E,\n  0x00, 0x00, 0xE0, 0x00, 0x1C, 0x00, 0x01, 0xC0, 0x00, 0x38, 0x00, 0x03,\n  0x80, 0x00, 0x70, 0x00, 0x07, 0x00, 0x00, 0xE0, 0x00, 0x0E, 0x00, 0x01,\n  0xC0, 0x00, 0x1C, 0x00, 0x03, 0x80, 0x00, 0x38, 0x00, 0x07, 0x00, 0x00,\n  0x70, 0x00, 0x0E, 0x00, 0x00, 0xE0, 0x00, 0x1C, 0x00, 0x01, 0xC0, 0x00,\n  0x38, 0x00, 0x03, 0x80, 0x00, 0x70, 0x00, 0x07, 0x00, 0x00, 0xE0, 0x00,\n  0x0E, 0x00, 0x01, 0xC0, 0x00, 0x1C, 0x00, 0x03, 0x80, 0x00, 0x38, 0x00,\n  0x07, 0x00, 0x00, 0x70, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x0F, 0xE0, 0x00,\n  0x1F, 0xFC, 0x00, 0x3F, 0xFF, 0x80, 0x3F, 0xFF, 0xC0, 0x3F, 0xFF, 0xF0,\n  0x1F, 0xC7, 0xF8, 0x1F, 0xC1, 0xFE, 0x1F, 0xC0, 0x7F, 0x0F, 0xC0, 0x3F,\n  0x8F, 0xE0, 0x1F, 0xC7, 0xF0, 0x0F, 0xE3, 0xF0, 0x07, 0xF3, 0xF8, 0x03,\n  0xF9, 0xFC, 0x01, 0xFC, 0xFC, 0x01, 0xFE, 0xFE, 0x00, 0xFE, 0x7F, 0x00,\n  0x7F, 0x3F, 0x80, 0x3F, 0x9F, 0xC0, 0x1F, 0xCF, 0xE0, 0x1F, 0xEF, 0xE0,\n  0x0F, 0xE7, 0xF0, 0x07, 0xF3, 0xF8, 0x03, 0xF9, 0xFC, 0x03, 0xF8, 0xFE,\n  0x01, 0xFC, 0x7F, 0x00, 0xFE, 0x3F, 0x80, 0xFE, 0x1F, 0xE0, 0x7F, 0x0F,\n  0xF8, 0xFF, 0x03, 0xFF, 0xFF, 0x01, 0xFF, 0xFF, 0x80, 0x7F, 0xFF, 0x80,\n  0x1F, 0xFF, 0x00, 0x07, 0xFF, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x0F,\n  0x80, 0x0F, 0x80, 0x07, 0xC0, 0x07, 0xE0, 0x0F, 0xF0, 0x3F, 0xF9, 0xFF,\n  0xF8, 0xFF, 0xFC, 0xFF, 0xFE, 0x7F, 0xFF, 0x00, 0x3F, 0x80, 0x1F, 0x80,\n  0x0F, 0xC0, 0x0F, 0xE0, 0x07, 0xF0, 0x03, 0xF8, 0x01, 0xF8, 0x01, 0xFC,\n  0x00, 0xFE, 0x00, 0x7F, 0x00, 0x3F, 0x00, 0x1F, 0x80, 0x1F, 0xC0, 0x0F,\n  0xE0, 0x07, 0xF0, 0x03, 0xF0, 0x01, 0xF8, 0x01, 0xFC, 0x00, 0xFE, 0x00,\n  0x7F, 0x00, 0x3F, 0x00, 0x3F, 0x80, 0x1F, 0xC0, 0x00, 0x00, 0x01, 0xFE,\n  0x00, 0x00, 0x7F, 0xFC, 0x00, 0x0F, 0xFF, 0xF8, 0x00, 0xFF, 0xFF, 0xE0,\n  0x0F, 0xFF, 0xFF, 0x00, 0xFF, 0x07, 0xFC, 0x07, 0xF0, 0x1F, 0xE0, 0x7F,\n  0x00, 0x7F, 0x03, 0xF0, 0x03, 0xF8, 0x1F, 0x80, 0x1F, 0xC1, 0xF8, 0x00,\n  0xFE, 0x0F, 0xC0, 0x0F, 0xE0, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x07, 0xF0,\n  0x00, 0x00, 0x3F, 0x80, 0x00, 0x07, 0xF8, 0x00, 0x00, 0x7F, 0x80, 0x00,\n  0x07, 0xF8, 0x00, 0x00, 0xFF, 0x80, 0x00, 0x1F, 0xF8, 0x00, 0x01, 0xFF,\n  0x00, 0x00, 0x3F, 0xE0, 0x00, 0x07, 0xFE, 0x00, 0x00, 0x7F, 0xC0, 0x00,\n  0x07, 0xFC, 0x00, 0x00, 0x7F, 0x80, 0x00, 0x07, 0xF8, 0x00, 0x00, 0x7F,\n  0x80, 0x00, 0x03, 0xFF, 0xFF, 0xF0, 0x3F, 0xFF, 0xFF, 0x81, 0xFF, 0xFF,\n  0xFC, 0x1F, 0xFF, 0xFF, 0xE0, 0xFF, 0xFF, 0xFF, 0x07, 0xFF, 0xFF, 0xF0,\n  0x00, 0x00, 0x0F, 0xF8, 0x00, 0x0F, 0xFF, 0x80, 0x0F, 0xFF, 0xF0, 0x07,\n  0xFF, 0xFE, 0x03, 0xFF, 0xFF, 0xC0, 0xFE, 0x1F, 0xF0, 0x7F, 0x01, 0xFC,\n  0x1F, 0x80, 0x7F, 0x07, 0xE0, 0x1F, 0xC3, 0xF0, 0x07, 0xF0, 0xFC, 0x01,\n  0xF8, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x7F, 0x80, 0x01,\n  0xFF, 0xC0, 0x00, 0x7F, 0xE0, 0x00, 0x1F, 0xFC, 0x00, 0x07, 0xFF, 0x80,\n  0x01, 0xFF, 0xE0, 0x00, 0x07, 0xFC, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x1F,\n  0xC0, 0x00, 0x07, 0xF0, 0x00, 0x01, 0xFC, 0x00, 0x00, 0x7F, 0x3F, 0x80,\n  0x3F, 0xCF, 0xE0, 0x0F, 0xE3, 0xF8, 0x07, 0xF8, 0xFF, 0x83, 0xFC, 0x3F,\n  0xFF, 0xFF, 0x07, 0xFF, 0xFF, 0x81, 0xFF, 0xFF, 0xC0, 0x3F, 0xFF, 0xE0,\n  0x03, 0xFF, 0xE0, 0x00, 0x3F, 0xC0, 0x00, 0x00, 0x00, 0x7F, 0x80, 0x00,\n  0x7F, 0xC0, 0x00, 0x7F, 0xE0, 0x00, 0x7F, 0xE0, 0x00, 0x3F, 0xF0, 0x00,\n  0x3F, 0xF8, 0x00, 0x3D, 0xFC, 0x00, 0x3C, 0xFE, 0x00, 0x3E, 0x7E, 0x00,\n  0x3E, 0x7F, 0x00, 0x1E, 0x3F, 0x80, 0x1E, 0x1F, 0xC0, 0x1E, 0x0F, 0xC0,\n  0x1F, 0x07, 0xE0, 0x1F, 0x07, 0xF0, 0x1F, 0x03, 0xF8, 0x1F, 0x01, 0xFC,\n  0x0F, 0x80, 0xFC, 0x0F, 0x80, 0xFE, 0x0F, 0x80, 0x7F, 0x07, 0xFF, 0xFF,\n  0xF7, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF,\n  0xFE, 0x00, 0x03, 0xF8, 0x00, 0x01, 0xF8, 0x00, 0x01, 0xFC, 0x00, 0x00,\n  0xFE, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x1F, 0x80, 0x00,\n  0x7F, 0xFF, 0xE0, 0x0F, 0xFF, 0xFC, 0x01, 0xFF, 0xFF, 0x80, 0x7F, 0xFF,\n  0xF0, 0x0F, 0xFF, 0xFC, 0x03, 0xFF, 0xFF, 0x80, 0x7C, 0x00, 0x00, 0x0F,\n  0x80, 0x00, 0x03, 0xE0, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x0F, 0x80, 0x00,\n  0x03, 0xE3, 0xF0, 0x00, 0x7F, 0xFF, 0x80, 0x1F, 0xFF, 0xF8, 0x03, 0xFF,\n  0xFF, 0x80, 0x7F, 0xFF, 0xF0, 0x1F, 0xE1, 0xFF, 0x03, 0xF0, 0x1F, 0xE0,\n  0x00, 0x01, 0xFC, 0x00, 0x00, 0x3F, 0x80, 0x00, 0x07, 0xF0, 0x00, 0x00,\n  0xFE, 0x00, 0x00, 0x1F, 0xC0, 0x00, 0x07, 0xF0, 0xFE, 0x00, 0xFE, 0x1F,\n  0xC0, 0x3F, 0x83, 0xF8, 0x07, 0xF0, 0x7F, 0x83, 0xFC, 0x0F, 0xFF, 0xFF,\n  0x80, 0xFF, 0xFF, 0xE0, 0x1F, 0xFF, 0xF8, 0x01, 0xFF, 0xFE, 0x00, 0x0F,\n  0xFF, 0x00, 0x00, 0x7F, 0x80, 0x00, 0x00, 0x07, 0xF0, 0x00, 0x1F, 0xFE,\n  0x00, 0x1F, 0xFF, 0x80, 0x1F, 0xFF, 0xE0, 0x1F, 0xFF, 0xF8, 0x1F, 0xC3,\n  0xFC, 0x1F, 0x80, 0xFE, 0x0F, 0xC0, 0x3F, 0x0F, 0xC0, 0x00, 0x07, 0xE0,\n  0x00, 0x07, 0xE0, 0x00, 0x03, 0xF0, 0x00, 0x03, 0xF8, 0xFC, 0x01, 0xF9,\n  0xFF, 0x80, 0xFF, 0xFF, 0xE0, 0xFF, 0xFF, 0xF8, 0x7F, 0xFF, 0xFC, 0x3F,\n  0xE1, 0xFF, 0x1F, 0xE0, 0x7F, 0x8F, 0xE0, 0x1F, 0xCF, 0xE0, 0x0F, 0xE7,\n  0xF0, 0x07, 0xF3, 0xF0, 0x03, 0xF9, 0xF8, 0x01, 0xF8, 0xFC, 0x01, 0xFC,\n  0x7E, 0x00, 0xFE, 0x3F, 0x00, 0xFE, 0x1F, 0xC0, 0xFF, 0x0F, 0xF0, 0xFF,\n  0x03, 0xFF, 0xFF, 0x81, 0xFF, 0xFF, 0x80, 0x7F, 0xFF, 0x80, 0x1F, 0xFF,\n  0x80, 0x07, 0xFF, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x3F, 0xFF, 0xFF, 0xCF,\n  0xFF, 0xFF, 0xF3, 0xFF, 0xFF, 0xF8, 0xFF, 0xFF, 0xFE, 0x7F, 0xFF, 0xFF,\n  0x9F, 0xFF, 0xFF, 0xE0, 0x00, 0x07, 0xF0, 0x00, 0x03, 0xF8, 0x00, 0x01,\n  0xFC, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x3F, 0x80, 0x00,\n  0x1F, 0xC0, 0x00, 0x07, 0xE0, 0x00, 0x03, 0xF0, 0x00, 0x01, 0xF8, 0x00,\n  0x00, 0xFE, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x1F, 0x80, 0x00, 0x0F, 0xE0,\n  0x00, 0x03, 0xF0, 0x00, 0x01, 0xFC, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x3F,\n  0x80, 0x00, 0x0F, 0xC0, 0x00, 0x07, 0xF0, 0x00, 0x01, 0xF8, 0x00, 0x00,\n  0xFE, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x1F, 0xC0, 0x00, 0x07, 0xF0, 0x00,\n  0x01, 0xF8, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x07, 0xF0, 0x00,\n  0x0F, 0xFF, 0x80, 0x07, 0xFF, 0xF0, 0x03, 0xFF, 0xFE, 0x01, 0xFF, 0xFF,\n  0xC0, 0xFE, 0x0F, 0xF0, 0x3E, 0x01, 0xFC, 0x1F, 0x80, 0x3F, 0x07, 0xC0,\n  0x0F, 0xC1, 0xF0, 0x03, 0xF0, 0x7C, 0x01, 0xF8, 0x1F, 0x00, 0xFC, 0x03,\n  0xF0, 0x7F, 0x00, 0xFF, 0xFF, 0x00, 0x1F, 0xFF, 0x80, 0x07, 0xFF, 0xE0,\n  0x07, 0xFF, 0xFC, 0x03, 0xFF, 0xFF, 0x81, 0xFE, 0x1F, 0xE0, 0xFE, 0x03,\n  0xFC, 0x3F, 0x00, 0x7F, 0x1F, 0xC0, 0x1F, 0xC7, 0xE0, 0x07, 0xF3, 0xF8,\n  0x01, 0xFC, 0xFE, 0x00, 0x7F, 0x3F, 0x80, 0x3F, 0x8F, 0xE0, 0x0F, 0xE3,\n  0xFC, 0x07, 0xF0, 0xFF, 0x87, 0xFC, 0x3F, 0xFF, 0xFE, 0x07, 0xFF, 0xFF,\n  0x00, 0xFF, 0xFF, 0xC0, 0x3F, 0xFF, 0xC0, 0x03, 0xFF, 0xE0, 0x00, 0x3F,\n  0xC0, 0x00, 0x00, 0x0F, 0xE0, 0x00, 0x1F, 0xFC, 0x00, 0x3F, 0xFF, 0x00,\n  0x3F, 0xFF, 0xC0, 0x3F, 0xFF, 0xF0, 0x3F, 0xC3, 0xF8, 0x3F, 0xC0, 0xFE,\n  0x1F, 0xC0, 0x3F, 0x1F, 0xC0, 0x1F, 0x8F, 0xE0, 0x0F, 0xC7, 0xE0, 0x07,\n  0xE7, 0xF0, 0x03, 0xF3, 0xF8, 0x01, 0xF9, 0xFC, 0x01, 0xFC, 0xFE, 0x00,\n  0xFE, 0x7F, 0x00, 0xFE, 0x3F, 0xC0, 0xFF, 0x1F, 0xF0, 0xFF, 0x87, 0xFF,\n  0xFF, 0xC3, 0xFF, 0xFF, 0xE0, 0xFF, 0xFF, 0xE0, 0x3F, 0xF3, 0xF0, 0x07,\n  0xE3, 0xF8, 0x00, 0x01, 0xF8, 0x00, 0x00, 0xFC, 0x00, 0x00, 0xFC, 0x00,\n  0x00, 0x7E, 0x1F, 0xC0, 0x7E, 0x0F, 0xF0, 0xFF, 0x07, 0xFF, 0xFF, 0x01,\n  0xFF, 0xFF, 0x00, 0xFF, 0xFF, 0x00, 0x3F, 0xFF, 0x00, 0x0F, 0xFF, 0x00,\n  0x01, 0xFC, 0x00, 0x00, 0x07, 0xF0, 0x7F, 0x07, 0xF0, 0x7E, 0x0F, 0xE0,\n  0xFE, 0x0F, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x07, 0xF0, 0x7F, 0x07,\n  0xE0, 0xFE, 0x0F, 0xE0, 0xFE, 0x00, 0x01, 0xFC, 0x07, 0xF0, 0x1F, 0xC0,\n  0x7E, 0x03, 0xF8, 0x0F, 0xE0, 0x3F, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0x01, 0xFC, 0x07, 0xF0, 0x1F, 0x80, 0xFE, 0x03, 0xF8, 0x0F, 0xE0,\n  0x03, 0x80, 0x1C, 0x00, 0x70, 0x03, 0xC0, 0x0E, 0x00, 0xF0, 0x0F, 0xC0,\n  0x3C, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0xE0, 0x00,\n  0x01, 0xF8, 0x00, 0x03, 0xFE, 0x00, 0x07, 0xFF, 0x80, 0x0F, 0xFF, 0xE0,\n  0x1F, 0xFF, 0xF0, 0x1F, 0xFF, 0xE0, 0x3F, 0xFF, 0xC0, 0x1F, 0xFF, 0x80,\n  0x0F, 0xFF, 0x00, 0x03, 0xFE, 0x00, 0x00, 0xFF, 0xE0, 0x00, 0x3F, 0xFE,\n  0x00, 0x0F, 0xFF, 0xF0, 0x00, 0xFF, 0xFF, 0x80, 0x07, 0xFF, 0xF8, 0x00,\n  0x7F, 0xFF, 0x00, 0x03, 0xFF, 0xC0, 0x00, 0x3F, 0xF0, 0x00, 0x01, 0xF8,\n  0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x80, 0x1F, 0xFF, 0xFF, 0xC7, 0xFF,\n  0xFF, 0xF1, 0xFF, 0xFF, 0xFC, 0x7F, 0xFF, 0xFF, 0x1F, 0xFF, 0xFF, 0x8F,\n  0xFF, 0xFF, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7F, 0xFF,\n  0xFF, 0x1F, 0xFF, 0xFF, 0xC7, 0xFF, 0xFF, 0xE3, 0xFF, 0xFF, 0xF8, 0xFF,\n  0xFF, 0xFE, 0x3F, 0xFF, 0xFF, 0x80, 0x04, 0x00, 0x00, 0x01, 0xE0, 0x00,\n  0x00, 0x7E, 0x00, 0x00, 0x3F, 0xF0, 0x00, 0x0F, 0xFF, 0x00, 0x03, 0xFF,\n  0xF8, 0x00, 0x7F, 0xFF, 0x80, 0x07, 0xFF, 0xFC, 0x00, 0x3F, 0xFF, 0xC0,\n  0x01, 0xFF, 0xF0, 0x00, 0x1F, 0xFC, 0x00, 0x01, 0xFF, 0x00, 0x03, 0xFF,\n  0xC0, 0x07, 0xFF, 0xE0, 0x0F, 0xFF, 0xF0, 0x1F, 0xFF, 0xE0, 0x3F, 0xFF,\n  0xE0, 0x1F, 0xFF, 0xC0, 0x07, 0xFF, 0x80, 0x01, 0xFF, 0x00, 0x00, 0x7E,\n  0x00, 0x00, 0x1C, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x3F, 0x80,\n  0x01, 0xFF, 0xF0, 0x07, 0xFF, 0xF8, 0x0F, 0xFF, 0xFC, 0x1F, 0xFF, 0xFE,\n  0x1F, 0xFF, 0xFE, 0x3F, 0xC1, 0xFF, 0x3F, 0x80, 0xFF, 0x7F, 0x00, 0x7F,\n  0x7E, 0x00, 0x7F, 0xFE, 0x00, 0x7F, 0xFE, 0x00, 0x7F, 0x00, 0x00, 0xFE,\n  0x00, 0x00, 0xFE, 0x00, 0x01, 0xFC, 0x00, 0x07, 0xFC, 0x00, 0x0F, 0xF8,\n  0x00, 0x1F, 0xF0, 0x00, 0x3F, 0xC0, 0x00, 0x7F, 0x80, 0x00, 0xFE, 0x00,\n  0x01, 0xF8, 0x00, 0x01, 0xF0, 0x00, 0x03, 0xF0, 0x00, 0x03, 0xE0, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0xE0, 0x00,\n  0x0F, 0xE0, 0x00, 0x0F, 0xE0, 0x00, 0x0F, 0xE0, 0x00, 0x1F, 0xC0, 0x00,\n  0x1F, 0xC0, 0x00, 0x1F, 0xC0, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xC0, 0x00,\n  0x00, 0x00, 0x7F, 0xFF, 0xC0, 0x00, 0x00, 0x0F, 0xFF, 0xFF, 0x80, 0x00,\n  0x01, 0xFF, 0xFF, 0xFE, 0x00, 0x00, 0x3F, 0xE0, 0x1F, 0xF8, 0x00, 0x07,\n  0xF8, 0x00, 0x1F, 0xE0, 0x00, 0x7F, 0x00, 0x00, 0x3F, 0x80, 0x07, 0xE0,\n  0x00, 0x00, 0xFE, 0x00, 0xFE, 0x00, 0x00, 0x03, 0xF0, 0x0F, 0xC0, 0x00,\n  0x00, 0x0F, 0x80, 0xFC, 0x00, 0x00, 0x00, 0x3E, 0x07, 0xC0, 0x03, 0xF1,\n  0xF1, 0xF0, 0x7C, 0x00, 0xFF, 0xCF, 0x07, 0x87, 0xE0, 0x1F, 0xFF, 0xF8,\n  0x3C, 0x7E, 0x01, 0xF8, 0x7F, 0x81, 0xE3, 0xE0, 0x1F, 0x01, 0xF8, 0x0F,\n  0x3E, 0x01, 0xF0, 0x0F, 0xC0, 0x79, 0xF0, 0x1F, 0x00, 0x7C, 0x03, 0xDF,\n  0x00, 0xF0, 0x03, 0xE0, 0x1C, 0xF8, 0x0F, 0x80, 0x1E, 0x01, 0xE7, 0xC0,\n  0x78, 0x00, 0xF0, 0x0F, 0x3C, 0x07, 0xC0, 0x0F, 0x00, 0xF3, 0xE0, 0x3C,\n  0x00, 0x78, 0x07, 0x9F, 0x03, 0xE0, 0x07, 0x80, 0x78, 0xF8, 0x1F, 0x00,\n  0x7C, 0x07, 0xC7, 0xC0, 0xF8, 0x07, 0xC0, 0x7C, 0x3E, 0x07, 0xC0, 0x7E,\n  0x07, 0xC1, 0xF0, 0x3F, 0x07, 0xF8, 0xFC, 0x0F, 0x81, 0xFF, 0xFF, 0xFF,\n  0xC0, 0x7E, 0x07, 0xFF, 0xBF, 0xFC, 0x01, 0xF0, 0x1F, 0xF8, 0xFF, 0x80,\n  0x0F, 0xC0, 0x7E, 0x03, 0xF0, 0x00, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x01,\n  0xFC, 0x00, 0x00, 0x00, 0x00, 0x07, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x3F,\n  0xE0, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xE0, 0x03, 0x80, 0x00, 0x01, 0xFF,\n  0xFF, 0xFE, 0x00, 0x00, 0x07, 0xFF, 0xFF, 0xF0, 0x00, 0x00, 0x0F, 0xFF,\n  0xFE, 0x00, 0x00, 0x00, 0x07, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F,\n  0xF0, 0x00, 0x00, 0x3F, 0xF0, 0x00, 0x00, 0x3F, 0xF0, 0x00, 0x00, 0x7F,\n  0xF0, 0x00, 0x00, 0x7F, 0xF0, 0x00, 0x00, 0xFF, 0xF0, 0x00, 0x00, 0xFF,\n  0xF0, 0x00, 0x01, 0xFF, 0xF0, 0x00, 0x03, 0xFF, 0xF8, 0x00, 0x03, 0xFB,\n  0xF8, 0x00, 0x07, 0xF3, 0xF8, 0x00, 0x07, 0xE3, 0xF8, 0x00, 0x0F, 0xE3,\n  0xF8, 0x00, 0x0F, 0xC3, 0xF8, 0x00, 0x1F, 0xC3, 0xF8, 0x00, 0x1F, 0x83,\n  0xF8, 0x00, 0x3F, 0x81, 0xFC, 0x00, 0x7F, 0x01, 0xFC, 0x00, 0x7F, 0x01,\n  0xFC, 0x00, 0xFE, 0x01, 0xFC, 0x00, 0xFC, 0x01, 0xFC, 0x01, 0xFF, 0xFF,\n  0xFC, 0x01, 0xFF, 0xFF, 0xFC, 0x03, 0xFF, 0xFF, 0xFE, 0x07, 0xFF, 0xFF,\n  0xFE, 0x07, 0xFF, 0xFF, 0xFE, 0x0F, 0xFF, 0xFF, 0xFE, 0x0F, 0xE0, 0x00,\n  0xFE, 0x1F, 0xC0, 0x00, 0xFE, 0x1F, 0xC0, 0x00, 0xFE, 0x3F, 0x80, 0x00,\n  0xFE, 0x3F, 0x80, 0x00, 0x7F, 0x7F, 0x00, 0x00, 0x7F, 0xFF, 0x00, 0x00,\n  0x7F, 0x01, 0xFF, 0xFF, 0xC0, 0x01, 0xFF, 0xFF, 0xF8, 0x01, 0xFF, 0xFF,\n  0xFC, 0x03, 0xFF, 0xFF, 0xFE, 0x03, 0xFF, 0xFF, 0xFE, 0x03, 0xFF, 0xFF,\n  0xFF, 0x03, 0xF8, 0x00, 0xFF, 0x03, 0xF8, 0x00, 0x7F, 0x07, 0xF0, 0x00,\n  0x7F, 0x07, 0xF0, 0x00, 0x7F, 0x07, 0xF0, 0x00, 0x7E, 0x07, 0xF0, 0x00,\n  0xFE, 0x0F, 0xF0, 0x03, 0xFC, 0x0F, 0xFF, 0xFF, 0xF8, 0x0F, 0xFF, 0xFF,\n  0xF0, 0x0F, 0xFF, 0xFF, 0xE0, 0x0F, 0xFF, 0xFF, 0xF0, 0x1F, 0xFF, 0xFF,\n  0xF8, 0x1F, 0xFF, 0xFF, 0xF8, 0x1F, 0xC0, 0x07, 0xFC, 0x1F, 0xC0, 0x01,\n  0xFC, 0x1F, 0xC0, 0x01, 0xFC, 0x3F, 0x80, 0x01, 0xFC, 0x3F, 0x80, 0x01,\n  0xFC, 0x3F, 0x80, 0x01, 0xFC, 0x3F, 0x80, 0x03, 0xF8, 0x7F, 0x00, 0x07,\n  0xF8, 0x7F, 0x00, 0x0F, 0xF0, 0x7F, 0xFF, 0xFF, 0xF0, 0x7F, 0xFF, 0xFF,\n  0xE0, 0x7F, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0x80, 0xFF, 0xFF, 0xFE,\n  0x00, 0xFF, 0xFF, 0xF0, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x07, 0xFF,\n  0xE0, 0x00, 0x1F, 0xFF, 0xF0, 0x00, 0x7F, 0xFF, 0xF8, 0x00, 0xFF, 0xFF,\n  0xFC, 0x01, 0xFF, 0xFF, 0xFE, 0x03, 0xFF, 0x03, 0xFE, 0x07, 0xFC, 0x01,\n  0xFF, 0x0F, 0xF0, 0x00, 0xFF, 0x0F, 0xE0, 0x00, 0x7F, 0x1F, 0xE0, 0x00,\n  0x7F, 0x1F, 0xC0, 0x00, 0x7F, 0x3F, 0x80, 0x00, 0x00, 0x3F, 0x80, 0x00,\n  0x00, 0x7F, 0x80, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x00,\n  0x00, 0x7F, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00,\n  0x00, 0xFE, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00,\n  0x00, 0xFE, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x01, 0xF8, 0xFE, 0x00, 0x03,\n  0xF8, 0xFF, 0x00, 0x07, 0xF8, 0xFF, 0x00, 0x07, 0xF0, 0x7F, 0x80, 0x1F,\n  0xF0, 0x7F, 0xE0, 0x7F, 0xE0, 0x3F, 0xFF, 0xFF, 0xC0, 0x3F, 0xFF, 0xFF,\n  0x80, 0x1F, 0xFF, 0xFF, 0x00, 0x0F, 0xFF, 0xFE, 0x00, 0x03, 0xFF, 0xF8,\n  0x00, 0x00, 0x7F, 0xC0, 0x00, 0x01, 0xFF, 0xFF, 0x80, 0x01, 0xFF, 0xFF,\n  0xE0, 0x03, 0xFF, 0xFF, 0xF8, 0x03, 0xFF, 0xFF, 0xFC, 0x03, 0xFF, 0xFF,\n  0xFC, 0x03, 0xFF, 0xFF, 0xFE, 0x03, 0xF8, 0x03, 0xFE, 0x07, 0xF0, 0x01,\n  0xFF, 0x07, 0xF0, 0x00, 0xFF, 0x07, 0xF0, 0x00, 0x7F, 0x07, 0xF0, 0x00,\n  0x7F, 0x0F, 0xF0, 0x00, 0x7F, 0x0F, 0xE0, 0x00, 0x7F, 0x0F, 0xE0, 0x00,\n  0x7F, 0x0F, 0xE0, 0x00, 0x7F, 0x0F, 0xE0, 0x00, 0x7F, 0x1F, 0xC0, 0x00,\n  0x7F, 0x1F, 0xC0, 0x00, 0xFE, 0x1F, 0xC0, 0x00, 0xFE, 0x1F, 0xC0, 0x00,\n  0xFE, 0x1F, 0xC0, 0x01, 0xFE, 0x3F, 0x80, 0x01, 0xFC, 0x3F, 0x80, 0x01,\n  0xFC, 0x3F, 0x80, 0x03, 0xF8, 0x3F, 0x80, 0x07, 0xF8, 0x7F, 0x00, 0x0F,\n  0xF0, 0x7F, 0x00, 0x1F, 0xF0, 0x7F, 0x00, 0x7F, 0xE0, 0x7F, 0xFF, 0xFF,\n  0xC0, 0x7F, 0xFF, 0xFF, 0x80, 0xFF, 0xFF, 0xFF, 0x00, 0xFF, 0xFF, 0xFE,\n  0x00, 0xFF, 0xFF, 0xF8, 0x00, 0xFF, 0xFF, 0x80, 0x00, 0x01, 0xFF, 0xFF,\n  0xFF, 0x01, 0xFF, 0xFF, 0xFF, 0x03, 0xFF, 0xFF, 0xFE, 0x03, 0xFF, 0xFF,\n  0xFE, 0x03, 0xFF, 0xFF, 0xFE, 0x03, 0xFF, 0xFF, 0xFE, 0x03, 0xF8, 0x00,\n  0x00, 0x07, 0xF0, 0x00, 0x00, 0x07, 0xF0, 0x00, 0x00, 0x07, 0xF0, 0x00,\n  0x00, 0x07, 0xF0, 0x00, 0x00, 0x07, 0xF0, 0x00, 0x00, 0x0F, 0xE0, 0x00,\n  0x00, 0x0F, 0xFF, 0xFF, 0xF0, 0x0F, 0xFF, 0xFF, 0xE0, 0x0F, 0xFF, 0xFF,\n  0xE0, 0x1F, 0xFF, 0xFF, 0xE0, 0x1F, 0xFF, 0xFF, 0xE0, 0x1F, 0xFF, 0xFF,\n  0xE0, 0x1F, 0xC0, 0x00, 0x00, 0x1F, 0xC0, 0x00, 0x00, 0x3F, 0x80, 0x00,\n  0x00, 0x3F, 0x80, 0x00, 0x00, 0x3F, 0x80, 0x00, 0x00, 0x3F, 0x80, 0x00,\n  0x00, 0x3F, 0x80, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x00,\n  0x00, 0x7F, 0xFF, 0xFF, 0xC0, 0x7F, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF,\n  0xC0, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF,\n  0x80, 0x00, 0xFF, 0xFF, 0xFF, 0x01, 0xFF, 0xFF, 0xFF, 0x01, 0xFF, 0xFF,\n  0xFE, 0x01, 0xFF, 0xFF, 0xFE, 0x01, 0xFF, 0xFF, 0xFE, 0x01, 0xFF, 0xFF,\n  0xFE, 0x03, 0xF8, 0x00, 0x00, 0x03, 0xF8, 0x00, 0x00, 0x03, 0xF8, 0x00,\n  0x00, 0x03, 0xF8, 0x00, 0x00, 0x03, 0xF8, 0x00, 0x00, 0x07, 0xF0, 0x00,\n  0x00, 0x07, 0xF0, 0x00, 0x00, 0x07, 0xFF, 0xFF, 0xE0, 0x07, 0xFF, 0xFF,\n  0xE0, 0x0F, 0xFF, 0xFF, 0xE0, 0x0F, 0xFF, 0xFF, 0xC0, 0x0F, 0xFF, 0xFF,\n  0xC0, 0x0F, 0xFF, 0xFF, 0xC0, 0x0F, 0xE0, 0x00, 0x00, 0x1F, 0xC0, 0x00,\n  0x00, 0x1F, 0xC0, 0x00, 0x00, 0x1F, 0xC0, 0x00, 0x00, 0x1F, 0xC0, 0x00,\n  0x00, 0x1F, 0xC0, 0x00, 0x00, 0x3F, 0x80, 0x00, 0x00, 0x3F, 0x80, 0x00,\n  0x00, 0x3F, 0x80, 0x00, 0x00, 0x3F, 0x80, 0x00, 0x00, 0x7F, 0x00, 0x00,\n  0x00, 0x7F, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x00,\n  0x00, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x80, 0x00, 0x03, 0xFF,\n  0xF8, 0x00, 0x07, 0xFF, 0xFE, 0x00, 0x0F, 0xFF, 0xFF, 0x80, 0x0F, 0xFF,\n  0xFF, 0xE0, 0x0F, 0xFF, 0xFF, 0xF8, 0x0F, 0xFC, 0x07, 0xFC, 0x0F, 0xF8,\n  0x00, 0xFF, 0x0F, 0xF0, 0x00, 0x3F, 0x87, 0xF0, 0x00, 0x1F, 0xC7, 0xF0,\n  0x00, 0x0F, 0xE3, 0xF8, 0x00, 0x00, 0x03, 0xF8, 0x00, 0x00, 0x01, 0xFC,\n  0x00, 0x00, 0x01, 0xFC, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x7F,\n  0x00, 0x3F, 0xFF, 0x3F, 0x00, 0x1F, 0xFF, 0xBF, 0x80, 0x0F, 0xFF, 0x9F,\n  0xC0, 0x07, 0xFF, 0xCF, 0xE0, 0x03, 0xFF, 0xE7, 0xF0, 0x03, 0xFF, 0xF3,\n  0xF8, 0x00, 0x01, 0xF9, 0xFC, 0x00, 0x01, 0xF8, 0xFF, 0x00, 0x00, 0xFC,\n  0x7F, 0x80, 0x00, 0xFE, 0x3F, 0xC0, 0x00, 0xFF, 0x0F, 0xF0, 0x00, 0xFF,\n  0x87, 0xFC, 0x00, 0xFF, 0x81, 0xFF, 0x81, 0xFF, 0xC0, 0xFF, 0xFF, 0xFF,\n  0xE0, 0x3F, 0xFF, 0xFF, 0xF0, 0x0F, 0xFF, 0xFE, 0xF8, 0x03, 0xFF, 0xFC,\n  0x78, 0x00, 0x7F, 0xFC, 0x3C, 0x00, 0x0F, 0xF0, 0x00, 0x00, 0x01, 0xFC,\n  0x00, 0x0F, 0xE0, 0x3F, 0x80, 0x01, 0xFC, 0x07, 0xF0, 0x00, 0x3F, 0x80,\n  0xFE, 0x00, 0x0F, 0xE0, 0x1F, 0xC0, 0x01, 0xFC, 0x07, 0xF0, 0x00, 0x3F,\n  0x80, 0xFE, 0x00, 0x07, 0xF0, 0x1F, 0xC0, 0x00, 0xFE, 0x03, 0xF8, 0x00,\n  0x3F, 0x80, 0xFF, 0x00, 0x07, 0xF0, 0x1F, 0xC0, 0x00, 0xFE, 0x03, 0xF8,\n  0x00, 0x1F, 0xC0, 0x7F, 0x00, 0x07, 0xF0, 0x0F, 0xFF, 0xFF, 0xFE, 0x03,\n  0xFF, 0xFF, 0xFF, 0xC0, 0x7F, 0xFF, 0xFF, 0xF8, 0x0F, 0xFF, 0xFF, 0xFF,\n  0x01, 0xFF, 0xFF, 0xFF, 0xC0, 0x3F, 0xFF, 0xFF, 0xF8, 0x0F, 0xE0, 0x00,\n  0x7F, 0x01, 0xFC, 0x00, 0x0F, 0xE0, 0x3F, 0x80, 0x01, 0xFC, 0x07, 0xF0,\n  0x00, 0x7F, 0x01, 0xFC, 0x00, 0x0F, 0xE0, 0x3F, 0x80, 0x01, 0xFC, 0x07,\n  0xF0, 0x00, 0x3F, 0x80, 0xFE, 0x00, 0x0F, 0xE0, 0x1F, 0xC0, 0x01, 0xFC,\n  0x07, 0xF0, 0x00, 0x3F, 0x80, 0xFE, 0x00, 0x07, 0xF0, 0x1F, 0xC0, 0x00,\n  0xFE, 0x03, 0xF8, 0x00, 0x3F, 0x80, 0x7F, 0x00, 0x07, 0xF0, 0x1F, 0xC0,\n  0x00, 0xFE, 0x00, 0x01, 0xFC, 0x07, 0xF0, 0x3F, 0x80, 0xFE, 0x03, 0xF8,\n  0x0F, 0xE0, 0x3F, 0x81, 0xFC, 0x07, 0xF0, 0x1F, 0xC0, 0x7F, 0x01, 0xFC,\n  0x0F, 0xE0, 0x3F, 0x80, 0xFE, 0x03, 0xF8, 0x0F, 0xE0, 0x7F, 0x01, 0xFC,\n  0x07, 0xF0, 0x1F, 0xC0, 0x7F, 0x03, 0xF8, 0x0F, 0xE0, 0x3F, 0x80, 0xFE,\n  0x03, 0xF8, 0x1F, 0xC0, 0x7F, 0x01, 0xFC, 0x07, 0xF0, 0x1F, 0xC0, 0xFE,\n  0x03, 0xF8, 0x00, 0x00, 0x00, 0x0F, 0xE0, 0x00, 0x01, 0xFC, 0x00, 0x00,\n  0x3F, 0x80, 0x00, 0x0F, 0xE0, 0x00, 0x01, 0xFC, 0x00, 0x00, 0x3F, 0x80,\n  0x00, 0x07, 0xF0, 0x00, 0x01, 0xFE, 0x00, 0x00, 0x3F, 0x80, 0x00, 0x07,\n  0xF0, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x1F, 0xC0, 0x00, 0x07, 0xF0, 0x00,\n  0x00, 0xFE, 0x00, 0x00, 0x1F, 0xC0, 0x00, 0x03, 0xF8, 0x00, 0x00, 0x7F,\n  0x00, 0x00, 0x1F, 0xC0, 0x00, 0x03, 0xF8, 0x00, 0x00, 0x7F, 0x00, 0x00,\n  0x0F, 0xE0, 0xFE, 0x03, 0xFC, 0x1F, 0xC0, 0x7F, 0x03, 0xF8, 0x0F, 0xE0,\n  0xFE, 0x01, 0xFC, 0x1F, 0xC0, 0x3F, 0x83, 0xF8, 0x0F, 0xE0, 0x7F, 0x01,\n  0xFC, 0x0F, 0xF0, 0xFF, 0x81, 0xFF, 0xFF, 0xE0, 0x3F, 0xFF, 0xF8, 0x03,\n  0xFF, 0xFF, 0x00, 0x3F, 0xFF, 0x80, 0x03, 0xFF, 0xE0, 0x00, 0x1F, 0xE0,\n  0x00, 0x00, 0x00, 0xFE, 0x00, 0x0F, 0xF0, 0x0F, 0xF0, 0x00, 0xFF, 0x00,\n  0x7F, 0x00, 0x1F, 0xF0, 0x03, 0xF8, 0x01, 0xFF, 0x00, 0x1F, 0xC0, 0x1F,\n  0xE0, 0x00, 0xFE, 0x01, 0xFE, 0x00, 0x0F, 0xE0, 0x1F, 0xE0, 0x00, 0x7F,\n  0x01, 0xFE, 0x00, 0x03, 0xF8, 0x1F, 0xE0, 0x00, 0x1F, 0xC1, 0xFE, 0x00,\n  0x00, 0xFE, 0x1F, 0xE0, 0x00, 0x0F, 0xE3, 0xFE, 0x00, 0x00, 0x7F, 0x3F,\n  0xC0, 0x00, 0x03, 0xFB, 0xFC, 0x00, 0x00, 0x1F, 0xFF, 0xC0, 0x00, 0x01,\n  0xFF, 0xFE, 0x00, 0x00, 0x0F, 0xFF, 0xF8, 0x00, 0x00, 0x7F, 0xFF, 0xC0,\n  0x00, 0x03, 0xFF, 0xFF, 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0xFF, 0xFF, 0x7F, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0x01, 0xFF,\n  0x80, 0x03, 0xFF, 0x80, 0xFF, 0xC0, 0x01, 0xFF, 0x80, 0x7F, 0xE0, 0x01,\n  0xFF, 0xC0, 0x3F, 0xF0, 0x00, 0xFF, 0xE0, 0x3F, 0xF8, 0x00, 0xFF, 0xF0,\n  0x1F, 0xFC, 0x00, 0x7F, 0xF8, 0x0F, 0xFE, 0x00, 0x7D, 0xF8, 0x07, 0xEF,\n  0x00, 0x3E, 0xFC, 0x03, 0xF7, 0x80, 0x3F, 0xFE, 0x03, 0xFB, 0xC0, 0x1F,\n  0x7F, 0x01, 0xFD, 0xE0, 0x1F, 0xBF, 0x00, 0xFE, 0xF0, 0x0F, 0x9F, 0x80,\n  0x7E, 0x78, 0x0F, 0xDF, 0xC0, 0x7F, 0x3E, 0x07, 0xCF, 0xE0, 0x3F, 0x9F,\n  0x07, 0xE7, 0xF0, 0x1F, 0xCF, 0x83, 0xE3, 0xF0, 0x0F, 0xE7, 0xC3, 0xF1,\n  0xF8, 0x07, 0xE3, 0xE1, 0xF9, 0xFC, 0x07, 0xF1, 0xF0, 0xF8, 0xFE, 0x03,\n  0xF8, 0xF8, 0xFC, 0x7F, 0x01, 0xFC, 0x7C, 0x7C, 0x3F, 0x00, 0xFC, 0x3E,\n  0x7E, 0x1F, 0x80, 0x7E, 0x1F, 0x3E, 0x1F, 0xC0, 0x7F, 0x0F, 0xBF, 0x0F,\n  0xE0, 0x3F, 0x87, 0xDF, 0x07, 0xE0, 0x1F, 0xC3, 0xFF, 0x83, 0xF0, 0x0F,\n  0xC1, 0xFF, 0xC3, 0xF8, 0x0F, 0xE0, 0xFF, 0xC1, 0xFC, 0x07, 0xF0, 0x7F,\n  0xE0, 0xFE, 0x03, 0xF8, 0x3F, 0xE0, 0x7E, 0x01, 0xFC, 0x1F, 0xF0, 0x3F,\n  0x00, 0xFC, 0x0F, 0xF0, 0x3F, 0x80, 0xFE, 0x07, 0xF8, 0x1F, 0xC0, 0x7F,\n  0x03, 0xF8, 0x0F, 0xC0, 0x00, 0x01, 0xFE, 0x00, 0x07, 0xE0, 0x3F, 0xC0,\n  0x01, 0xFC, 0x07, 0xFC, 0x00, 0x3F, 0x80, 0xFF, 0x80, 0x07, 0xF0, 0x1F,\n  0xF0, 0x00, 0xFC, 0x07, 0xFF, 0x00, 0x3F, 0x80, 0xFF, 0xE0, 0x07, 0xF0,\n  0x1F, 0xFC, 0x00, 0xFE, 0x03, 0xFF, 0xC0, 0x1F, 0x80, 0xFF, 0xF8, 0x03,\n  0xF0, 0x1F, 0xFF, 0x80, 0xFE, 0x03, 0xFB, 0xF0, 0x1F, 0xC0, 0x7E, 0x7E,\n  0x03, 0xF8, 0x0F, 0xC7, 0xE0, 0x7E, 0x03, 0xF8, 0xFC, 0x0F, 0xC0, 0x7F,\n  0x1F, 0x83, 0xF8, 0x0F, 0xE1, 0xF8, 0x7F, 0x01, 0xF8, 0x3F, 0x0F, 0xE0,\n  0x3F, 0x07, 0xF1, 0xF8, 0x0F, 0xE0, 0x7E, 0x3F, 0x01, 0xFC, 0x0F, 0xCF,\n  0xE0, 0x3F, 0x00, 0xFD, 0xFC, 0x07, 0xE0, 0x1F, 0xBF, 0x81, 0xFC, 0x03,\n  0xF7, 0xE0, 0x3F, 0x80, 0x3F, 0xFC, 0x07, 0xF0, 0x07, 0xFF, 0x80, 0xFC,\n  0x00, 0xFF, 0xF0, 0x1F, 0x80, 0x0F, 0xFC, 0x07, 0xF0, 0x01, 0xFF, 0x80,\n  0xFE, 0x00, 0x3F, 0xF0, 0x1F, 0xC0, 0x03, 0xFE, 0x03, 0xF0, 0x00, 0x7F,\n  0xC0, 0x7E, 0x00, 0x07, 0xF0, 0x1F, 0xC0, 0x00, 0xFE, 0x00, 0x00, 0x00,\n  0xFF, 0x80, 0x00, 0x01, 0xFF, 0xF8, 0x00, 0x01, 0xFF, 0xFF, 0x80, 0x01,\n  0xFF, 0xFF, 0xF0, 0x00, 0xFF, 0xFF, 0xFE, 0x00, 0x7F, 0xFF, 0xFF, 0xC0,\n  0x3F, 0xF0, 0x3F, 0xF8, 0x1F, 0xF0, 0x03, 0xFE, 0x07, 0xF0, 0x00, 0x7F,\n  0x83, 0xF8, 0x00, 0x0F, 0xF1, 0xFE, 0x00, 0x03, 0xFC, 0x7F, 0x00, 0x00,\n  0x7F, 0x3F, 0x80, 0x00, 0x1F, 0xCF, 0xE0, 0x00, 0x07, 0xF7, 0xF0, 0x00,\n  0x01, 0xFD, 0xFC, 0x00, 0x00, 0x7F, 0x7F, 0x00, 0x00, 0x1F, 0xDF, 0xC0,\n  0x00, 0x07, 0xFF, 0xE0, 0x00, 0x03, 0xFB, 0xF8, 0x00, 0x00, 0xFE, 0xFE,\n  0x00, 0x00, 0x3F, 0xBF, 0x80, 0x00, 0x0F, 0xEF, 0xE0, 0x00, 0x07, 0xF3,\n  0xF8, 0x00, 0x01, 0xFC, 0xFE, 0x00, 0x00, 0xFE, 0x3F, 0xC0, 0x00, 0x7F,\n  0x8F, 0xF0, 0x00, 0x1F, 0xC1, 0xFE, 0x00, 0x0F, 0xE0, 0x7F, 0xC0, 0x0F,\n  0xF8, 0x1F, 0xFC, 0x0F, 0xFC, 0x03, 0xFF, 0xFF, 0xFE, 0x00, 0x7F, 0xFF,\n  0xFF, 0x00, 0x0F, 0xFF, 0xFF, 0x80, 0x01, 0xFF, 0xFF, 0x80, 0x00, 0x1F,\n  0xFF, 0x80, 0x00, 0x01, 0xFF, 0x00, 0x00, 0x01, 0xFF, 0xFF, 0x80, 0x03,\n  0xFF, 0xFF, 0xE0, 0x0F, 0xFF, 0xFF, 0xE0, 0x1F, 0xFF, 0xFF, 0xE0, 0x3F,\n  0xFF, 0xFF, 0xC0, 0x7F, 0xFF, 0xFF, 0xC1, 0xFE, 0x00, 0xFF, 0x83, 0xF8,\n  0x00, 0xFF, 0x07, 0xF0, 0x00, 0xFE, 0x0F, 0xE0, 0x01, 0xFC, 0x1F, 0xC0,\n  0x03, 0xF8, 0x7F, 0x00, 0x07, 0xF0, 0xFE, 0x00, 0x1F, 0xC1, 0xFC, 0x00,\n  0x3F, 0x83, 0xF8, 0x00, 0xFE, 0x07, 0xF0, 0x07, 0xFC, 0x1F, 0xFF, 0xFF,\n  0xF0, 0x3F, 0xFF, 0xFF, 0xE0, 0x7F, 0xFF, 0xFF, 0x80, 0xFF, 0xFF, 0xFE,\n  0x03, 0xFF, 0xFF, 0xF0, 0x07, 0xFF, 0xFF, 0x80, 0x0F, 0xE0, 0x00, 0x00,\n  0x1F, 0xC0, 0x00, 0x00, 0x3F, 0x80, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x01,\n  0xFC, 0x00, 0x00, 0x03, 0xF8, 0x00, 0x00, 0x07, 0xF0, 0x00, 0x00, 0x0F,\n  0xE0, 0x00, 0x00, 0x3F, 0x80, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x00, 0xFE,\n  0x00, 0x00, 0x01, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x80, 0x00,\n  0x01, 0xFF, 0xF8, 0x00, 0x01, 0xFF, 0xFF, 0x80, 0x01, 0xFF, 0xFF, 0xF0,\n  0x00, 0xFF, 0xFF, 0xFE, 0x00, 0x7F, 0xFF, 0xFF, 0xC0, 0x3F, 0xF0, 0x3F,\n  0xF0, 0x1F, 0xF0, 0x03, 0xFE, 0x07, 0xF8, 0x00, 0x7F, 0x83, 0xFC, 0x00,\n  0x0F, 0xF1, 0xFE, 0x00, 0x03, 0xFC, 0x7F, 0x00, 0x00, 0x7F, 0x3F, 0x80,\n  0x00, 0x1F, 0xCF, 0xE0, 0x00, 0x07, 0xF3, 0xF0, 0x00, 0x01, 0xFD, 0xFC,\n  0x00, 0x00, 0x7F, 0x7F, 0x00, 0x00, 0x1F, 0xDF, 0x80, 0x00, 0x07, 0xFF,\n  0xE0, 0x00, 0x03, 0xFB, 0xF8, 0x00, 0x00, 0xFE, 0xFE, 0x00, 0x00, 0x3F,\n  0xBF, 0x80, 0x00, 0x0F, 0xEF, 0xE0, 0x01, 0x87, 0xF3, 0xF8, 0x00, 0xF1,\n  0xFC, 0xFE, 0x00, 0x7C, 0xFE, 0x3F, 0xC0, 0x3F, 0xFF, 0x8F, 0xF0, 0x07,\n  0xFF, 0xC1, 0xFE, 0x01, 0xFF, 0xE0, 0x7F, 0xC0, 0x3F, 0xF8, 0x1F, 0xFC,\n  0x0F, 0xFC, 0x03, 0xFF, 0xFF, 0xFF, 0x00, 0x7F, 0xFF, 0xFF, 0xC0, 0x0F,\n  0xFF, 0xFF, 0xF8, 0x01, 0xFF, 0xFF, 0xFF, 0x00, 0x1F, 0xFF, 0x9F, 0x80,\n  0x01, 0xFF, 0x03, 0xC0, 0x00, 0x00, 0x00, 0x60, 0x00, 0x01, 0xFF, 0xFF,\n  0xF0, 0x00, 0xFF, 0xFF, 0xFE, 0x00, 0x7F, 0xFF, 0xFF, 0x80, 0x7F, 0xFF,\n  0xFF, 0xE0, 0x3F, 0xFF, 0xFF, 0xF0, 0x1F, 0xFF, 0xFF, 0xFC, 0x0F, 0xE0,\n  0x03, 0xFE, 0x0F, 0xF0, 0x00, 0xFF, 0x07, 0xF0, 0x00, 0x3F, 0x83, 0xF8,\n  0x00, 0x1F, 0xC1, 0xFC, 0x00, 0x0F, 0xC0, 0xFE, 0x00, 0x07, 0xE0, 0xFE,\n  0x00, 0x07, 0xF0, 0x7F, 0x00, 0x07, 0xF0, 0x3F, 0x80, 0x0F, 0xF0, 0x1F,\n  0xFF, 0xFF, 0xF0, 0x0F, 0xFF, 0xFF, 0xF0, 0x0F, 0xFF, 0xFF, 0xE0, 0x07,\n  0xFF, 0xFF, 0xF0, 0x03, 0xFF, 0xFF, 0xFC, 0x01, 0xFF, 0xFF, 0xFF, 0x01,\n  0xFC, 0x00, 0x7F, 0x80, 0xFE, 0x00, 0x1F, 0xC0, 0x7F, 0x00, 0x0F, 0xE0,\n  0x3F, 0x80, 0x07, 0xF0, 0x1F, 0xC0, 0x03, 0xF8, 0x1F, 0xC0, 0x01, 0xFC,\n  0x0F, 0xE0, 0x01, 0xFC, 0x07, 0xF0, 0x00, 0xFE, 0x03, 0xF8, 0x00, 0x7F,\n  0x01, 0xFC, 0x00, 0x3F, 0x81, 0xFC, 0x00, 0x1F, 0xC0, 0xFE, 0x00, 0x0F,\n  0xE0, 0x7F, 0x00, 0x07, 0xF0, 0x00, 0x00, 0x03, 0xFE, 0x00, 0x00, 0x7F,\n  0xFF, 0x00, 0x07, 0xFF, 0xFE, 0x00, 0x3F, 0xFF, 0xFC, 0x01, 0xFF, 0xFF,\n  0xF8, 0x0F, 0xFF, 0xFF, 0xF0, 0x3F, 0xC0, 0x7F, 0xC1, 0xFE, 0x00, 0xFF,\n  0x07, 0xF0, 0x01, 0xFC, 0x3F, 0x80, 0x07, 0xF0, 0xFE, 0x00, 0x1F, 0xC3,\n  0xF8, 0x00, 0x00, 0x0F, 0xE0, 0x00, 0x00, 0x3F, 0xC0, 0x00, 0x00, 0xFF,\n  0xE0, 0x00, 0x03, 0xFF, 0xFC, 0x00, 0x07, 0xFF, 0xFF, 0x00, 0x0F, 0xFF,\n  0xFE, 0x00, 0x1F, 0xFF, 0xFE, 0x00, 0x0F, 0xFF, 0xF8, 0x00, 0x03, 0xFF,\n  0xF0, 0x00, 0x00, 0xFF, 0xC0, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x01, 0xFC,\n  0x00, 0x00, 0x07, 0xF3, 0xF8, 0x00, 0x1F, 0xCF, 0xE0, 0x00, 0x7E, 0x3F,\n  0x80, 0x03, 0xF8, 0xFF, 0x00, 0x1F, 0xE3, 0xFF, 0x01, 0xFF, 0x07, 0xFF,\n  0xFF, 0xF8, 0x1F, 0xFF, 0xFF, 0xE0, 0x3F, 0xFF, 0xFF, 0x00, 0x7F, 0xFF,\n  0xF0, 0x00, 0x7F, 0xFF, 0x80, 0x00, 0x3F, 0xF0, 0x00, 0x7F, 0xFF, 0xFF,\n  0xF7, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xEF, 0xFF, 0xFF, 0xFE, 0x00, 0x3F, 0x80, 0x00, 0x03, 0xF8,\n  0x00, 0x00, 0x3F, 0x80, 0x00, 0x07, 0xF0, 0x00, 0x00, 0x7F, 0x00, 0x00,\n  0x07, 0xF0, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x0F, 0xF0, 0x00, 0x00, 0xFE,\n  0x00, 0x00, 0x0F, 0xE0, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x0F, 0xE0, 0x00,\n  0x01, 0xFC, 0x00, 0x00, 0x1F, 0xC0, 0x00, 0x01, 0xFC, 0x00, 0x00, 0x1F,\n  0xC0, 0x00, 0x01, 0xFC, 0x00, 0x00, 0x3F, 0x80, 0x00, 0x03, 0xF8, 0x00,\n  0x00, 0x3F, 0x80, 0x00, 0x03, 0xF8, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x07,\n  0xF0, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x07, 0xF0, 0x00, 0x00, 0x7F, 0x00,\n  0x00, 0x0F, 0xE0, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x07, 0xF0, 0x00, 0x7F,\n  0x07, 0xF0, 0x00, 0x7F, 0x07, 0xF0, 0x00, 0xFE, 0x0F, 0xE0, 0x00, 0xFE,\n  0x0F, 0xE0, 0x00, 0xFE, 0x0F, 0xE0, 0x00, 0xFE, 0x0F, 0xE0, 0x00, 0xFE,\n  0x0F, 0xE0, 0x01, 0xFC, 0x1F, 0xC0, 0x01, 0xFC, 0x1F, 0xC0, 0x01, 0xFC,\n  0x1F, 0xC0, 0x01, 0xFC, 0x1F, 0xC0, 0x01, 0xFC, 0x3F, 0x80, 0x03, 0xF8,\n  0x3F, 0x80, 0x03, 0xF8, 0x3F, 0x80, 0x03, 0xF8, 0x3F, 0x80, 0x03, 0xF8,\n  0x3F, 0x80, 0x07, 0xF0, 0x7F, 0x00, 0x07, 0xF0, 0x7F, 0x00, 0x07, 0xF0,\n  0x7F, 0x00, 0x07, 0xF0, 0x7F, 0x00, 0x07, 0xF0, 0x7F, 0x00, 0x0F, 0xE0,\n  0xFE, 0x00, 0x0F, 0xE0, 0xFE, 0x00, 0x0F, 0xE0, 0xFE, 0x00, 0x0F, 0xE0,\n  0xFE, 0x00, 0x1F, 0xC0, 0xFE, 0x00, 0x1F, 0xC0, 0xFF, 0x00, 0x3F, 0x80,\n  0xFF, 0xC0, 0xFF, 0x80, 0x7F, 0xFF, 0xFF, 0x00, 0x7F, 0xFF, 0xFE, 0x00,\n  0x3F, 0xFF, 0xFC, 0x00, 0x1F, 0xFF, 0xF8, 0x00, 0x0F, 0xFF, 0xE0, 0x00,\n  0x01, 0xFF, 0x00, 0x00, 0xFF, 0x00, 0x03, 0xF9, 0xFC, 0x00, 0x0F, 0xE7,\n  0xF0, 0x00, 0x7F, 0x1F, 0xC0, 0x01, 0xFC, 0x7F, 0x00, 0x0F, 0xE1, 0xFC,\n  0x00, 0x3F, 0x87, 0xF0, 0x01, 0xFC, 0x1F, 0xC0, 0x07, 0xF0, 0x3F, 0x00,\n  0x3F, 0x80, 0xFC, 0x00, 0xFC, 0x03, 0xF0, 0x07, 0xF0, 0x0F, 0xC0, 0x1F,\n  0x80, 0x3F, 0x80, 0xFE, 0x00, 0xFE, 0x03, 0xF0, 0x03, 0xF8, 0x1F, 0xC0,\n  0x0F, 0xE0, 0x7E, 0x00, 0x1F, 0x83, 0xF8, 0x00, 0x7E, 0x0F, 0xC0, 0x01,\n  0xF8, 0x7E, 0x00, 0x07, 0xE1, 0xF8, 0x00, 0x1F, 0x8F, 0xC0, 0x00, 0x7E,\n  0x3F, 0x00, 0x01, 0xF9, 0xF8, 0x00, 0x07, 0xE7, 0xE0, 0x00, 0x0F, 0xFF,\n  0x00, 0x00, 0x3F, 0xFC, 0x00, 0x00, 0xFF, 0xE0, 0x00, 0x03, 0xFF, 0x00,\n  0x00, 0x0F, 0xFC, 0x00, 0x00, 0x3F, 0xE0, 0x00, 0x00, 0xFF, 0x80, 0x00,\n  0x01, 0xFC, 0x00, 0x00, 0x07, 0xF0, 0x00, 0x00, 0x1F, 0x80, 0x00, 0x00,\n  0xFE, 0x00, 0x7F, 0x80, 0x1F, 0xFF, 0xC0, 0x0F, 0xF0, 0x03, 0xFB, 0xF8,\n  0x01, 0xFE, 0x00, 0x7F, 0x7F, 0x00, 0x7F, 0xC0, 0x1F, 0xCF, 0xE0, 0x0F,\n  0xF8, 0x03, 0xF9, 0xFC, 0x03, 0xFF, 0x00, 0xFE, 0x3F, 0x80, 0x7F, 0xE0,\n  0x1F, 0xC7, 0xF0, 0x1F, 0xFC, 0x07, 0xF0, 0x7E, 0x03, 0xFF, 0x80, 0xFE,\n  0x0F, 0xC0, 0x7D, 0xF0, 0x1F, 0x81, 0xF8, 0x1F, 0xBE, 0x07, 0xF0, 0x3F,\n  0x03, 0xE7, 0xC0, 0xFC, 0x07, 0xE0, 0xFC, 0xF8, 0x3F, 0x80, 0xFC, 0x1F,\n  0x1F, 0x07, 0xE0, 0x1F, 0x83, 0xE3, 0xE0, 0xFC, 0x03, 0xF0, 0xFC, 0x7C,\n  0x3F, 0x00, 0x7E, 0x1F, 0x0F, 0x87, 0xE0, 0x0F, 0xC7, 0xE1, 0xF1, 0xF8,\n  0x01, 0xF8, 0xF8, 0x3E, 0x3F, 0x00, 0x3F, 0x3F, 0x07, 0xCF, 0xC0, 0x07,\n  0xE7, 0xC0, 0xF9, 0xF8, 0x00, 0xFC, 0xF8, 0x1F, 0x3E, 0x00, 0x1F, 0xBE,\n  0x03, 0xEF, 0xC0, 0x01, 0xF7, 0xC0, 0x7D, 0xF0, 0x00, 0x3F, 0xF8, 0x0F,\n  0xFE, 0x00, 0x07, 0xFE, 0x01, 0xFF, 0x80, 0x00, 0xFF, 0xC0, 0x3F, 0xF0,\n  0x00, 0x1F, 0xF0, 0x07, 0xFC, 0x00, 0x03, 0xFE, 0x00, 0xFF, 0x80, 0x00,\n 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0xFF, 0xE0, 0x3F, 0xFF,\n  0xFF, 0xF0, 0x1F, 0xFF, 0xFF, 0xF8, 0x0F, 0xFF, 0xFF, 0xF8, 0x00, 0x00,\n  0x07, 0xFC, 0x00, 0x00, 0x07, 0xFC, 0x00, 0x00, 0x07, 0xFC, 0x00, 0x00,\n  0x07, 0xFC, 0x00, 0x00, 0x07, 0xFC, 0x00, 0x00, 0x07, 0xFC, 0x00, 0x00,\n  0x07, 0xFC, 0x00, 0x00, 0x07, 0xFC, 0x00, 0x00, 0x07, 0xFC, 0x00, 0x00,\n  0x07, 0xFC, 0x00, 0x00, 0x07, 0xFC, 0x00, 0x00, 0x07, 0xFC, 0x00, 0x00,\n  0x07, 0xFC, 0x00, 0x00, 0x07, 0xFC, 0x00, 0x00, 0x07, 0xFC, 0x00, 0x00,\n  0x07, 0xFC, 0x00, 0x00, 0x07, 0xF8, 0x00, 0x00, 0x07, 0xF8, 0x00, 0x00,\n  0x07, 0xF8, 0x00, 0x00, 0x07, 0xF8, 0x00, 0x00, 0x07, 0xF8, 0x00, 0x00,\n  0x07, 0xF8, 0x00, 0x00, 0x03, 0xFF, 0xFF, 0xFE, 0x03, 0xFF, 0xFF, 0xFF,\n  0x01, 0xFF, 0xFF, 0xFF, 0x80, 0xFF, 0xFF, 0xFF, 0xC0, 0x7F, 0xFF, 0xFF,\n  0xC0, 0x3F, 0xFF, 0xFF, 0xE0, 0x00, 0x00, 0x7F, 0xF8, 0x03, 0xFF, 0x80,\n  0x1F, 0xFC, 0x00, 0xFF, 0xE0, 0x0F, 0xFF, 0x00, 0x7E, 0x00, 0x03, 0xF0,\n  0x00, 0x1F, 0x80, 0x01, 0xFC, 0x00, 0x0F, 0xC0, 0x00, 0x7E, 0x00, 0x03,\n  0xF0, 0x00, 0x1F, 0x80, 0x01, 0xFC, 0x00, 0x0F, 0xC0, 0x00, 0x7E, 0x00,\n  0x03, 0xF0, 0x00, 0x1F, 0x80, 0x01, 0xFC, 0x00, 0x0F, 0xC0, 0x00, 0x7E,\n  0x00, 0x03, 0xF0, 0x00, 0x3F, 0x80, 0x01, 0xF8, 0x00, 0x0F, 0xC0, 0x00,\n  0x7E, 0x00, 0x03, 0xF0, 0x00, 0x3F, 0x80, 0x01, 0xF8, 0x00, 0x0F, 0xC0,\n  0x00, 0x7E, 0x00, 0x03, 0xF0, 0x00, 0x3F, 0x00, 0x01, 0xF8, 0x00, 0x0F,\n  0xC0, 0x00, 0x7E, 0x00, 0x07, 0xF0, 0x00, 0x3F, 0x00, 0x01, 0xFF, 0xC0,\n  0x0F, 0xFE, 0x00, 0x7F, 0xF0, 0x07, 0xFF, 0x80, 0x3F, 0xFC, 0x00, 0x81,\n  0xC3, 0xC7, 0x8F, 0x0E, 0x1C, 0x38, 0x70, 0xE1, 0xC3, 0xC7, 0x8F, 0x1E,\n  0x1C, 0x38, 0x70, 0xE1, 0xC3, 0x87, 0x8F, 0x1E, 0x3C, 0x38, 0x70, 0xE1,\n  0xC3, 0x87, 0x0F, 0x1E, 0x3C, 0x78, 0xF0, 0x00, 0x7F, 0xF8, 0x03, 0xFF,\n  0xC0, 0x1F, 0xFC, 0x00, 0xFF, 0xE0, 0x07, 0xFF, 0x00, 0x01, 0xF8, 0x00,\n  0x1F, 0xC0, 0x00, 0xFC, 0x00, 0x07, 0xE0, 0x00, 0x3F, 0x00, 0x01, 0xF8,\n  0x00, 0x1F, 0x80, 0x00, 0xFC, 0x00, 0x07, 0xE0, 0x00, 0x3F, 0x00, 0x03,\n  0xF8, 0x00, 0x1F, 0x80, 0x00, 0xFC, 0x00, 0x07, 0xE0, 0x00, 0x3F, 0x00,\n  0x03, 0xF8, 0x00, 0x1F, 0x80, 0x00, 0xFC, 0x00, 0x07, 0xE0, 0x00, 0x7F,\n  0x00, 0x03, 0xF0, 0x00, 0x1F, 0x80, 0x00, 0xFC, 0x00, 0x07, 0xE0, 0x00,\n  0x7F, 0x00, 0x03, 0xF0, 0x00, 0x1F, 0x80, 0x00, 0xFC, 0x00, 0x07, 0xE0,\n  0x00, 0x7F, 0x00, 0x03, 0xF0, 0x00, 0x1F, 0x80, 0x00, 0xFC, 0x01, 0xFF,\n  0xE0, 0x0F, 0xFE, 0x00, 0x7F, 0xF0, 0x03, 0xFF, 0x80, 0x3F, 0xFC, 0x00,\n  0x00, 0x1F, 0x80, 0x00, 0xFE, 0x00, 0x0F, 0xF0, 0x00, 0x7F, 0x80, 0x07,\n  0xFC, 0x00, 0x7F, 0xE0, 0x03, 0xFF, 0x80, 0x3E, 0xFC, 0x01, 0xF3, 0xE0,\n  0x1F, 0x1F, 0x01, 0xF8, 0xF8, 0x0F, 0x87, 0xE0, 0xFC, 0x3F, 0x07, 0xC0,\n  0xF8, 0x7C, 0x07, 0xC7, 0xE0, 0x3E, 0x3E, 0x01, 0xFB, 0xF0, 0x0F, 0xDF,\n  0x00, 0x3F, 0xF0, 0x01, 0xF0, 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xE0, 0xF8, 0xF0, 0xF1, 0xE1,\n  0xC3, 0xC3, 0x80, 0x00, 0x1F, 0xF0, 0x00, 0x7F, 0xFF, 0x00, 0xFF, 0xFF,\n  0xC0, 0xFF, 0xFF, 0xF0, 0x7F, 0xFF, 0xF8, 0x7F, 0x03, 0xFC, 0x3F, 0x00,\n  0xFE, 0x1F, 0x80, 0x7E, 0x00, 0x00, 0x7F, 0x00, 0x00, 0xFF, 0x80, 0x1F,\n  0xFF, 0xC0, 0x7F, 0xFF, 0xC0, 0xFF, 0xFF, 0xE0, 0xFF, 0xF7, 0xF0, 0xFF,\n  0x83, 0xF8, 0xFF, 0x01, 0xF8, 0x7F, 0x00, 0xFC, 0x7F, 0x00, 0xFE, 0x3F,\n  0x80, 0x7F, 0x1F, 0xC0, 0x7F, 0x8F, 0xF0, 0xFF, 0x87, 0xFF, 0xFF, 0xC3,\n  0xFF, 0xFF, 0xE0, 0xFF, 0xF7, 0xF8, 0x3F, 0xF3, 0xFC, 0x07, 0xE0, 0x00,\n  0x00, 0x01, 0xFC, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x07, 0xE0, 0x00, 0x01,\n  0xFC, 0x00, 0x00, 0x3F, 0x80, 0x00, 0x07, 0xE0, 0x00, 0x00, 0xFC, 0x00,\n  0x00, 0x3F, 0x80, 0x00, 0x07, 0xF0, 0x00, 0x00, 0xFE, 0x3F, 0x80, 0x1F,\n  0x9F, 0xFC, 0x03, 0xF7, 0xFF, 0xC0, 0xFF, 0xFF, 0xF8, 0x1F, 0xFF, 0xFF,\n  0x83, 0xFF, 0x0F, 0xF0, 0x7F, 0x80, 0xFF, 0x0F, 0xE0, 0x1F, 0xE3, 0xF8,\n  0x01, 0xFC, 0x7F, 0x00, 0x3F, 0x8F, 0xC0, 0x07, 0xF1, 0xF8, 0x00, 0xFE,\n  0x7F, 0x00, 0x1F, 0xCF, 0xC0, 0x03, 0xF9, 0xF8, 0x00, 0xFE, 0x3F, 0x00,\n  0x1F, 0xC7, 0xE0, 0x03, 0xF9, 0xFC, 0x00, 0xFE, 0x3F, 0xC0, 0x3F, 0xC7,\n  0xF8, 0x0F, 0xF0, 0xFF, 0x83, 0xFC, 0x1F, 0xFF, 0xFF, 0x07, 0xFF, 0xFF,\n  0xC0, 0xFF, 0xFF, 0xF0, 0x1F, 0x9F, 0xFC, 0x00, 0x00, 0xFC, 0x00, 0x00,\n  0x00, 0x1F, 0xE0, 0x00, 0x3F, 0xFC, 0x00, 0x7F, 0xFF, 0x80, 0x7F, 0xFF,\n  0xE0, 0x7F, 0xFF, 0xF0, 0x7F, 0x83, 0xFC, 0x7F, 0x00, 0xFE, 0x3F, 0x00,\n  0x7F, 0x3F, 0x80, 0x3F, 0x9F, 0x80, 0x00, 0x1F, 0xC0, 0x00, 0x0F, 0xE0,\n  0x00, 0x07, 0xE0, 0x00, 0x07, 0xF0, 0x00, 0x03, 0xF8, 0x00, 0x01, 0xFC,\n  0x00, 0x00, 0xFE, 0x00, 0x00, 0x7F, 0x00, 0x7F, 0x3F, 0x80, 0x3F, 0x9F,\n  0xE0, 0x3F, 0x87, 0xF8, 0x3F, 0x83, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xC0,\n  0x3F, 0xFF, 0xC0, 0x0F, 0xFF, 0x80, 0x01, 0xFE, 0x00, 0x00, 0x00, 0x00,\n  0x03, 0xF8, 0x00, 0x00, 0x1F, 0xC0, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x07,\n  0xE0, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x03, 0xF8, 0x00, 0x00, 0x1F, 0xC0,\n  0x00, 0x00, 0xFC, 0x00, 0x00, 0x0F, 0xE0, 0x01, 0xFC, 0x7F, 0x00, 0x3F,\n  0xF3, 0xF8, 0x03, 0xFF, 0xDF, 0x80, 0x7F, 0xFF, 0xFC, 0x07, 0xFF, 0xFF,\n  0xE0, 0x3F, 0xC3, 0xFF, 0x03, 0xFC, 0x0F, 0xF8, 0x3F, 0xC0, 0x3F, 0x81,\n  0xFC, 0x01, 0xFC, 0x1F, 0xC0, 0x07, 0xE0, 0xFE, 0x00, 0x3F, 0x07, 0xF0,\n  0x03, 0xF8, 0x7F, 0x00, 0x1F, 0x83, 0xF8, 0x00, 0xFC, 0x1F, 0xC0, 0x07,\n  0xE0, 0xFE, 0x00, 0x3F, 0x07, 0xF0, 0x03, 0xF0, 0x3F, 0x80, 0x3F, 0x81,\n  0xFC, 0x01, 0xFC, 0x0F, 0xF0, 0x1F, 0xE0, 0x3F, 0xC3, 0xFF, 0x01, 0xFF,\n  0xFF, 0xF0, 0x0F, 0xFF, 0xFF, 0x80, 0x3F, 0xFF, 0xFC, 0x00, 0xFF, 0xCF,\n  0xE0, 0x01, 0xF8, 0x00, 0x00, 0x00, 0x1F, 0xC0, 0x00, 0x7F, 0xFC, 0x00,\n  0x7F, 0xFF, 0x00, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xF0, 0x7F, 0x87, 0xF8,\n  0x7F, 0x01, 0xFE, 0x7F, 0x00, 0x7F, 0x3F, 0x80, 0x3F, 0xBF, 0x80, 0x1F,\n  0xDF, 0xC0, 0x0F, 0xEF, 0xFF, 0xFF, 0xF7, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFD, 0xFC, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x7F, 0x00,\n  0x00, 0x3F, 0x80, 0x3F, 0x9F, 0xE0, 0x3F, 0x87, 0xF8, 0x3F, 0xC3, 0xFF,\n  0xFF, 0xC0, 0xFF, 0xFF, 0xC0, 0x3F, 0xFF, 0x80, 0x0F, 0xFF, 0x80, 0x00,\n  0xFE, 0x00, 0x00, 0x00, 0x1F, 0xC0, 0x1F, 0xF0, 0x0F, 0xF8, 0x07, 0xFE,\n  0x01, 0xFF, 0x80, 0xFE, 0x00, 0x3F, 0x80, 0x0F, 0xC0, 0x03, 0xF0, 0x01,\n  0xFC, 0x03, 0xFF, 0xF1, 0xFF, 0xF8, 0x7F, 0xFE, 0x1F, 0xFF, 0x80, 0xFE,\n  0x00, 0x3F, 0x80, 0x0F, 0xE0, 0x03, 0xF0, 0x00, 0xFC, 0x00, 0x7F, 0x00,\n  0x1F, 0xC0, 0x07, 0xE0, 0x01, 0xF8, 0x00, 0xFE, 0x00, 0x3F, 0x80, 0x0F,\n  0xE0, 0x03, 0xF0, 0x00, 0xFC, 0x00, 0x7F, 0x00, 0x1F, 0xC0, 0x07, 0xF0,\n  0x01, 0xF8, 0x00, 0x7E, 0x00, 0x3F, 0x80, 0x00, 0x00, 0x07, 0xC3, 0xF8,\n  0x01, 0xFF, 0x9F, 0x80, 0x1F, 0xFE, 0xFC, 0x01, 0xFF, 0xFF, 0xE0, 0x1F,\n  0xFF, 0xFF, 0x01, 0xFE, 0x1F, 0xF8, 0x1F, 0xE0, 0x3F, 0x80, 0xFE, 0x01,\n  0xFC, 0x0F, 0xE0, 0x0F, 0xE0, 0x7F, 0x00, 0x3F, 0x07, 0xF0, 0x01, 0xF8,\n  0x3F, 0x80, 0x0F, 0x81, 0xF8, 0x00, 0x7C, 0x1F, 0xC0, 0x07, 0xE0, 0xFE,\n  0x00, 0x3F, 0x07, 0xF0, 0x01, 0xF0, 0x3F, 0x80, 0x1F, 0x81, 0xFC, 0x00,\n  0xFC, 0x0F, 0xE0, 0x0F, 0xE0, 0x7F, 0x80, 0xFF, 0x03, 0xFE, 0x1F, 0xF0,\n  0x0F, 0xFF, 0xFF, 0x80, 0x7F, 0xFF, 0xFC, 0x01, 0xFF, 0xF7, 0xE0, 0x07,\n  0xFE, 0x7F, 0x00, 0x0F, 0xC3, 0xF0, 0x00, 0x00, 0x1F, 0x80, 0x00, 0x01,\n  0xFC, 0x0F, 0xE0, 0x0F, 0xC0, 0x7F, 0x00, 0xFE, 0x03, 0xFC, 0x1F, 0xE0,\n  0x1F, 0xFF, 0xFE, 0x00, 0x7F, 0xFF, 0xE0, 0x01, 0xFF, 0xFC, 0x00, 0x01,\n  0xFF, 0x00, 0x00, 0x01, 0xFC, 0x00, 0x00, 0x3F, 0x80, 0x00, 0x07, 0xE0,\n  0x00, 0x00, 0xFC, 0x00, 0x00, 0x3F, 0x80, 0x00, 0x07, 0xF0, 0x00, 0x00,\n  0xFE, 0x00, 0x00, 0x1F, 0x80, 0x00, 0x03, 0xF0, 0x00, 0x00, 0xFE, 0x0F,\n  0xC0, 0x1F, 0xCF, 0xFE, 0x03, 0xFB, 0xFF, 0xE0, 0x7F, 0xFF, 0xFE, 0x0F,\n  0xFF, 0xFF, 0xC3, 0xFF, 0x07, 0xF8, 0x7F, 0x80, 0x7F, 0x0F, 0xE0, 0x0F,\n  0xE1, 0xFC, 0x01, 0xFC, 0x7F, 0x00, 0x3F, 0x0F, 0xE0, 0x07, 0xE1, 0xFC,\n  0x01, 0xFC, 0x3F, 0x00, 0x3F, 0x87, 0xE0, 0x07, 0xF1, 0xFC, 0x00, 0xFC,\n  0x3F, 0x80, 0x1F, 0x87, 0xF0, 0x07, 0xF0, 0xFC, 0x00, 0xFE, 0x1F, 0x80,\n  0x1F, 0xC7, 0xF0, 0x03, 0xF0, 0xFE, 0x00, 0x7E, 0x1F, 0xC0, 0x1F, 0xC3,\n  0xF0, 0x03, 0xF8, 0xFE, 0x00, 0x7F, 0x1F, 0xC0, 0x0F, 0xC0, 0x01, 0xFC,\n  0x07, 0xF0, 0x1F, 0x80, 0x7E, 0x03, 0xF8, 0x0F, 0xE0, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x1F, 0xC0, 0x7F, 0x01, 0xFC, 0x07, 0xE0, 0x3F, 0x80, 0xFE,\n  0x03, 0xF8, 0x0F, 0xC0, 0x3F, 0x01, 0xFC, 0x07, 0xF0, 0x1F, 0xC0, 0x7E,\n  0x03, 0xF8, 0x0F, 0xE0, 0x3F, 0x80, 0xFC, 0x03, 0xF0, 0x1F, 0xC0, 0x7F,\n  0x01, 0xFC, 0x07, 0xE0, 0x1F, 0x80, 0xFE, 0x03, 0xF8, 0x00, 0x00, 0x0F,\n  0xE0, 0x01, 0xFC, 0x00, 0x3F, 0x80, 0x07, 0xE0, 0x00, 0xFC, 0x00, 0x3F,\n  0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xF0, 0x00, 0xFE,\n  0x00, 0x1F, 0xC0, 0x03, 0xF8, 0x00, 0x7E, 0x00, 0x1F, 0xC0, 0x03, 0xF8,\n  0x00, 0x7F, 0x00, 0x0F, 0xC0, 0x01, 0xF8, 0x00, 0x7F, 0x00, 0x0F, 0xE0,\n  0x01, 0xFC, 0x00, 0x3F, 0x00, 0x07, 0xE0, 0x01, 0xFC, 0x00, 0x3F, 0x80,\n  0x07, 0xF0, 0x00, 0xFC, 0x00, 0x1F, 0x80, 0x07, 0xF0, 0x00, 0xFE, 0x00,\n  0x1F, 0x80, 0x03, 0xF0, 0x00, 0xFE, 0x00, 0x1F, 0xC0, 0x03, 0xF8, 0x00,\n  0x7E, 0x00, 0x0F, 0xC0, 0x03, 0xF8, 0x03, 0xFF, 0x00, 0x7F, 0xC0, 0x0F,\n  0xF8, 0x03, 0xFE, 0x00, 0x7E, 0x00, 0x00, 0x01, 0xFC, 0x00, 0x00, 0x1F,\n  0x80, 0x00, 0x01, 0xF8, 0x00, 0x00, 0x3F, 0x80, 0x00, 0x03, 0xF8, 0x00,\n  0x00, 0x3F, 0x00, 0x00, 0x03, 0xF0, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x07,\n  0xF0, 0x00, 0x00, 0x7F, 0x00, 0xFE, 0x07, 0xE0, 0x3F, 0xC0, 0x7E, 0x07,\n  0xF8, 0x0F, 0xE0, 0xFF, 0x00, 0xFE, 0x1F, 0xC0, 0x0F, 0xE3, 0xF8, 0x00,\n  0xFC, 0x7F, 0x00, 0x0F, 0xCF, 0xE0, 0x01, 0xFD, 0xFC, 0x00, 0x1F, 0xFF,\n  0x80, 0x01, 0xFF, 0xF8, 0x00, 0x1F, 0xFF, 0x80, 0x03, 0xFF, 0xFC, 0x00,\n  0x3F, 0xFF, 0xC0, 0x03, 0xFE, 0xFE, 0x00, 0x3F, 0xCF, 0xE0, 0x03, 0xF0,\n  0xFE, 0x00, 0x7F, 0x07, 0xF0, 0x07, 0xF0, 0x7F, 0x00, 0x7F, 0x07, 0xF8,\n  0x07, 0xE0, 0x3F, 0x80, 0x7E, 0x03, 0xF8, 0x0F, 0xE0, 0x3F, 0xC0, 0xFE,\n  0x01, 0xFC, 0x0F, 0xC0, 0x1F, 0xE0, 0x01, 0xFC, 0x07, 0xF0, 0x1F, 0x80,\n  0x7E, 0x03, 0xF8, 0x0F, 0xE0, 0x3F, 0x80, 0xFC, 0x03, 0xF0, 0x1F, 0xC0,\n  0x7F, 0x01, 0xFC, 0x07, 0xE0, 0x3F, 0x80, 0xFE, 0x03, 0xF8, 0x0F, 0xC0,\n  0x3F, 0x01, 0xFC, 0x07, 0xF0, 0x1F, 0xC0, 0x7E, 0x03, 0xF8, 0x0F, 0xE0,\n  0x3F, 0x80, 0xFC, 0x03, 0xF0, 0x1F, 0xC0, 0x7F, 0x01, 0xFC, 0x07, 0xE0,\n  0x1F, 0x80, 0xFE, 0x03, 0xF8, 0x00, 0x07, 0xF0, 0xFC, 0x03, 0xF0, 0x07,\n  0xE3, 0xFF, 0x0F, 0xFC, 0x07, 0xEF, 0xFF, 0x3F, 0xFE, 0x0F, 0xFF, 0xFF,\n  0xFF, 0xFF, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF, 0x0F, 0xF8, 0x7F, 0xF0, 0xFF,\n  0x0F, 0xE0, 0x3F, 0xC0, 0x7F, 0x0F, 0xE0, 0x3F, 0x80, 0x7F, 0x1F, 0xC0,\n  0x3F, 0x80, 0x7E, 0x1F, 0xC0, 0x3F, 0x00, 0x7E, 0x1F, 0xC0, 0x3F, 0x00,\n  0xFE, 0x1F, 0x80, 0x7F, 0x00, 0xFE, 0x3F, 0x80, 0x7F, 0x00, 0xFC, 0x3F,\n  0x80, 0x7F, 0x00, 0xFC, 0x3F, 0x80, 0x7E, 0x01, 0xFC, 0x3F, 0x00, 0x7E,\n  0x01, 0xFC, 0x3F, 0x00, 0xFE, 0x01, 0xFC, 0x7F, 0x00, 0xFE, 0x01, 0xF8,\n  0x7F, 0x00, 0xFE, 0x01, 0xF8, 0x7F, 0x00, 0xFC, 0x03, 0xF8, 0x7E, 0x01,\n  0xFC, 0x03, 0xF8, 0x7E, 0x01, 0xFC, 0x03, 0xF8, 0xFE, 0x01, 0xFC, 0x03,\n  0xF0, 0xFE, 0x01, 0xF8, 0x03, 0xF0, 0xFE, 0x01, 0xF8, 0x07, 0xF0, 0x07,\n  0xF0, 0xFE, 0x00, 0xFE, 0x7F, 0xF0, 0x1F, 0x9F, 0xFF, 0x03, 0xFF, 0xFF,\n  0xF0, 0xFF, 0xFF, 0xFE, 0x1F, 0xF8, 0x3F, 0xC3, 0xFC, 0x03, 0xF8, 0x7F,\n  0x00, 0x7F, 0x0F, 0xE0, 0x0F, 0xE3, 0xF8, 0x01, 0xF8, 0x7F, 0x00, 0x3F,\n  0x0F, 0xC0, 0x0F, 0xE1, 0xF8, 0x01, 0xFC, 0x7F, 0x00, 0x3F, 0x8F, 0xE0,\n  0x07, 0xE1, 0xFC, 0x00, 0xFC, 0x3F, 0x00, 0x3F, 0x87, 0xE0, 0x07, 0xF1,\n  0xFC, 0x00, 0xFE, 0x3F, 0x80, 0x1F, 0x87, 0xF0, 0x03, 0xF0, 0xFC, 0x00,\n  0xFE, 0x3F, 0x80, 0x1F, 0xC7, 0xF0, 0x03, 0xF8, 0xFE, 0x00, 0x7E, 0x00,\n  0x00, 0x1F, 0xE0, 0x00, 0x1F, 0xFF, 0x00, 0x1F, 0xFF, 0xE0, 0x0F, 0xFF,\n  0xFC, 0x07, 0xFF, 0xFF, 0x83, 0xFC, 0x1F, 0xE1, 0xFE, 0x03, 0xFC, 0xFF,\n  0x00, 0xFF, 0x3F, 0x80, 0x1F, 0xDF, 0xC0, 0x07, 0xF7, 0xF0, 0x01, 0xFD,\n  0xFC, 0x00, 0x7F, 0xFE, 0x00, 0x1F, 0xFF, 0x80, 0x07, 0xFF, 0xE0, 0x03,\n  0xFB, 0xF8, 0x00, 0xFE, 0xFE, 0x00, 0x3F, 0xBF, 0x80, 0x1F, 0xCF, 0xF0,\n  0x0F, 0xF3, 0xFC, 0x07, 0xF8, 0x7F, 0x83, 0xFC, 0x1F, 0xFF, 0xFE, 0x03,\n  0xFF, 0xFF, 0x00, 0x7F, 0xFF, 0x80, 0x0F, 0xFF, 0x80, 0x00, 0x7F, 0x00,\n  0x00, 0x01, 0xFC, 0x3F, 0x00, 0x0F, 0xCF, 0xFE, 0x00, 0x7E, 0xFF, 0xF8,\n  0x07, 0xFF, 0xFF, 0xC0, 0x3F, 0xFF, 0xFF, 0x01, 0xFF, 0x87, 0xF8, 0x0F,\n  0xF0, 0x1F, 0xE0, 0xFF, 0x00, 0xFF, 0x07, 0xF0, 0x03, 0xF8, 0x3F, 0x80,\n  0x1F, 0xC1, 0xF8, 0x00, 0xFE, 0x0F, 0xC0, 0x07, 0xF0, 0xFE, 0x00, 0x3F,\n  0x87, 0xF0, 0x01, 0xFC, 0x3F, 0x00, 0x1F, 0xC1, 0xF8, 0x00, 0xFE, 0x1F,\n  0xC0, 0x07, 0xF0, 0xFE, 0x00, 0x7F, 0x07, 0xF8, 0x07, 0xF8, 0x3F, 0xC0,\n  0x7F, 0x81, 0xFF, 0x87, 0xF8, 0x1F, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xFC,\n  0x07, 0xF7, 0xFF, 0xC0, 0x3F, 0x1F, 0xF8, 0x01, 0xF8, 0x7F, 0x00, 0x1F,\n  0xC0, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x07, 0xF0, 0x00, 0x00, 0x3F, 0x00,\n  0x00, 0x03, 0xF8, 0x00, 0x00, 0x1F, 0xC0, 0x00, 0x00, 0xFE, 0x00, 0x00,\n  0x07, 0xE0, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x87, 0xF0,\n  0x0F, 0xFE, 0x7F, 0x01, 0xFF, 0xF7, 0xE0, 0x3F, 0xFF, 0x7E, 0x07, 0xFF,\n  0xFF, 0xE0, 0xFF, 0x07, 0xFE, 0x1F, 0xE0, 0x3F, 0xE3, 0xFC, 0x03, 0xFC,\n  0x3F, 0x80, 0x1F, 0xC7, 0xF0, 0x01, 0xFC, 0x7F, 0x00, 0x1F, 0xC7, 0xF0,\n  0x01, 0xF8, 0xFE, 0x00, 0x1F, 0x8F, 0xE0, 0x03, 0xF8, 0xFE, 0x00, 0x3F,\n  0x8F, 0xE0, 0x03, 0xF8, 0xFE, 0x00, 0x7F, 0x0F, 0xE0, 0x07, 0xF0, 0xFE,\n  0x00, 0xFF, 0x0F, 0xF0, 0x1F, 0xF0, 0x7F, 0x87, 0xFF, 0x07, 0xFF, 0xFF,\n  0xE0, 0x3F, 0xFF, 0x7E, 0x03, 0xFF, 0xEF, 0xE0, 0x1F, 0xFC, 0xFE, 0x00,\n  0x7F, 0x0F, 0xC0, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x1F, 0xC0, 0x00, 0x01,\n  0xFC, 0x00, 0x00, 0x1F, 0xC0, 0x00, 0x01, 0xF8, 0x00, 0x00, 0x1F, 0x80,\n  0x00, 0x03, 0xF8, 0x00, 0x00, 0x3F, 0x80, 0x00, 0x03, 0xF8, 0x00, 0x07,\n  0xF0, 0xF0, 0x7F, 0x3F, 0x07, 0xE7, 0xE0, 0x7E, 0xFE, 0x0F, 0xFF, 0xE0,\n  0xFF, 0xFE, 0x0F, 0xFC, 0x00, 0xFF, 0x00, 0x0F, 0xE0, 0x01, 0xFC, 0x00,\n  0x1F, 0xC0, 0x01, 0xF8, 0x00, 0x1F, 0x80, 0x03, 0xF8, 0x00, 0x3F, 0x80,\n  0x03, 0xF8, 0x00, 0x3F, 0x00, 0x03, 0xF0, 0x00, 0x7F, 0x00, 0x07, 0xF0,\n  0x00, 0x7F, 0x00, 0x07, 0xE0, 0x00, 0xFE, 0x00, 0x0F, 0xE0, 0x00, 0xFE,\n  0x00, 0x00, 0x00, 0x1F, 0xE0, 0x00, 0xFF, 0xF8, 0x03, 0xFF, 0xFC, 0x07,\n  0xFF, 0xFE, 0x0F, 0xFF, 0xFF, 0x0F, 0xE0, 0xFF, 0x1F, 0xC0, 0x7F, 0x1F,\n  0xC0, 0x7F, 0x1F, 0xE0, 0x00, 0x1F, 0xFC, 0x00, 0x1F, 0xFF, 0xC0, 0x0F,\n  0xFF, 0xF0, 0x07, 0xFF, 0xF8, 0x03, 0xFF, 0xFC, 0x00, 0x7F, 0xFE, 0x00,\n  0x0F, 0xFE, 0x00, 0x03, 0xFE, 0x00, 0x00, 0xFE, 0xFC, 0x00, 0xFE, 0xFE,\n  0x00, 0xFE, 0xFF, 0x03, 0xFC, 0x7F, 0xFF, 0xF8, 0x7F, 0xFF, 0xF8, 0x3F,\n  0xFF, 0xE0, 0x1F, 0xFF, 0xC0, 0x03, 0xFE, 0x00, 0x03, 0xF0, 0x1F, 0xC0,\n  0x7F, 0x01, 0xFC, 0x07, 0xE0, 0x3F, 0x80, 0xFE, 0x1F, 0xFF, 0x7F, 0xFD,\n  0xFF, 0xFF, 0xFF, 0xC7, 0xF0, 0x1F, 0xC0, 0x7E, 0x01, 0xF8, 0x0F, 0xE0,\n  0x3F, 0x80, 0xFE, 0x03, 0xF0, 0x0F, 0xC0, 0x7F, 0x01, 0xFC, 0x07, 0xE0,\n  0x1F, 0x80, 0xFE, 0x03, 0xF8, 0x0F, 0xE0, 0x3F, 0xF0, 0xFF, 0xC3, 0xFF,\n  0x07, 0xFC, 0x0F, 0xE0, 0x0F, 0xC0, 0x0F, 0xE1, 0xF8, 0x01, 0xFC, 0x7F,\n  0x00, 0x3F, 0x0F, 0xE0, 0x0F, 0xE1, 0xFC, 0x01, 0xFC, 0x3F, 0x00, 0x3F,\n  0x87, 0xE0, 0x07, 0xE1, 0xFC, 0x00, 0xFC, 0x3F, 0x80, 0x3F, 0x87, 0xF0,\n  0x07, 0xF0, 0xFC, 0x00, 0xFE, 0x1F, 0x80, 0x1F, 0x87, 0xF0, 0x03, 0xF0,\n  0xFE, 0x00, 0xFE, 0x1F, 0x80, 0x1F, 0xC3, 0xF0, 0x03, 0xF0, 0xFE, 0x00,\n  0x7E, 0x1F, 0xC0, 0x1F, 0xC3, 0xF8, 0x07, 0xF8, 0x7F, 0x01, 0xFF, 0x0F,\n  0xF0, 0x7F, 0xC1, 0xFF, 0xFF, 0xF8, 0x3F, 0xFF, 0xFF, 0x03, 0xFF, 0xEF,\n  0xE0, 0x3F, 0xF9, 0xFC, 0x01, 0xF8, 0x00, 0x00, 0xFE, 0x00, 0x7F, 0x7F,\n  0x00, 0x3F, 0xBF, 0x80, 0x3F, 0x8F, 0xC0, 0x1F, 0xC7, 0xE0, 0x1F, 0xC3,\n  0xF0, 0x0F, 0xC1, 0xFC, 0x0F, 0xE0, 0xFE, 0x07, 0xE0, 0x7F, 0x07, 0xF0,\n  0x3F, 0x83, 0xF0, 0x0F, 0xC3, 0xF8, 0x07, 0xE1, 0xF8, 0x03, 0xF1, 0xFC,\n  0x01, 0xF8, 0xFC, 0x00, 0xFC, 0xFC, 0x00, 0x7E, 0x7E, 0x00, 0x3F, 0x7E,\n  0x00, 0x0F, 0xBF, 0x00, 0x07, 0xFF, 0x00, 0x03, 0xFF, 0x80, 0x01, 0xFF,\n  0x80, 0x00, 0xFF, 0x80, 0x00, 0x7F, 0xC0, 0x00, 0x3F, 0xC0, 0x00, 0x1F,\n  0xE0, 0x00, 0x00, 0xFE, 0x03, 0xF8, 0x0F, 0xFF, 0xC0, 0x7F, 0x01, 0xFF,\n  0xF8, 0x1F, 0xE0, 0x3F, 0x7F, 0x03, 0xFC, 0x0F, 0xEF, 0xE0, 0xFF, 0x81,\n  0xF9, 0xFC, 0x1F, 0xF0, 0x7F, 0x3F, 0x83, 0xFE, 0x0F, 0xC3, 0xF0, 0xFF,\n  0xC3, 0xF8, 0x7E, 0x1E, 0xF8, 0x7E, 0x0F, 0xC7, 0xDF, 0x1F, 0xC1, 0xF8,\n  0xFB, 0xE3, 0xF0, 0x3F, 0x1E, 0x7C, 0x7E, 0x07, 0xE7, 0xCF, 0x9F, 0x80,\n  0xFC, 0xF1, 0xF3, 0xF0, 0x1F, 0xBE, 0x3E, 0xFC, 0x03, 0xF7, 0x87, 0xDF,\n  0x80, 0x7E, 0xF0, 0xFF, 0xE0, 0x0F, 0xFE, 0x1F, 0xFC, 0x01, 0xFF, 0x83,\n  0xFF, 0x00, 0x3F, 0xF0, 0x7F, 0xE0, 0x07, 0xFC, 0x0F, 0xF8, 0x00, 0x7F,\n  0x81, 0xFF, 0x00, 0x0F, 0xF0, 0x3F, 0xC0, 0x01, 0xFC, 0x07, 0xF8, 0x00,\n  0x3F, 0x80, 0xFE, 0x00, 0x00, 0x03, 0xFC, 0x07, 0xF8, 0x1F, 0xE0, 0x7F,\n  0x80, 0x7F, 0x03, 0xF8, 0x03, 0xF8, 0x3F, 0x80, 0x1F, 0xE3, 0xF8, 0x00,\n  0x7F, 0x3F, 0x80, 0x03, 0xF9, 0xFC, 0x00, 0x0F, 0xFF, 0xC0, 0x00, 0x7F,\n  0xFC, 0x00, 0x01, 0xFF, 0xC0, 0x00, 0x0F, 0xFC, 0x00, 0x00, 0x7F, 0xC0,\n  0x00, 0x01, 0xFC, 0x00, 0x00, 0x1F, 0xF0, 0x00, 0x01, 0xFF, 0x80, 0x00,\n  0x1F, 0xFE, 0x00, 0x01, 0xFF, 0xF0, 0x00, 0x1F, 0xDF, 0xC0, 0x01, 0xFC,\n  0xFE, 0x00, 0x1F, 0xE7, 0xF8, 0x00, 0xFE, 0x1F, 0xC0, 0x0F, 0xE0, 0xFE,\n  0x00, 0xFF, 0x07, 0xF8, 0x0F, 0xF0, 0x1F, 0xC0, 0xFF, 0x00, 0xFF, 0x00,\n  0x0F, 0xE0, 0x03, 0xF0, 0x7F, 0x00, 0x3F, 0x83, 0xF8, 0x01, 0xF8, 0x1F,\n  0xC0, 0x1F, 0xC0, 0xFE, 0x00, 0xFC, 0x03, 0xF8, 0x0F, 0xE0, 0x1F, 0xC0,\n  0x7E, 0x00, 0xFE, 0x07, 0xE0, 0x07, 0xF0, 0x3F, 0x00, 0x3F, 0x83, 0xF0,\n  0x01, 0xFC, 0x1F, 0x80, 0x0F, 0xE1, 0xF8, 0x00, 0x3F, 0x0F, 0xC0, 0x01,\n  0xF8, 0xFC, 0x00, 0x0F, 0xC7, 0xC0, 0x00, 0x7F, 0x7E, 0x00, 0x03, 0xFB,\n  0xE0, 0x00, 0x1F, 0xFF, 0x00, 0x00, 0xFF, 0xF0, 0x00, 0x03, 0xFF, 0x80,\n  0x00, 0x1F, 0xF8, 0x00, 0x00, 0xFF, 0x80, 0x00, 0x07, 0xFC, 0x00, 0x00,\n  0x3F, 0xC0, 0x00, 0x01, 0xFE, 0x00, 0x00, 0x0F, 0xE0, 0x00, 0x00, 0x7F,\n  0x00, 0x00, 0x03, 0xF0, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x03, 0xF8, 0x00,\n  0x01, 0xFF, 0x80, 0x00, 0x1F, 0xFC, 0x00, 0x00, 0xFF, 0xC0, 0x00, 0x07,\n  0xF8, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x03, 0xFF, 0xFF, 0xC0, 0xFF,\n  0xFF, 0xF0, 0x3F, 0xFF, 0xF8, 0x1F, 0xFF, 0xFE, 0x07, 0xFF, 0xFF, 0x80,\n  0x00, 0x3F, 0xC0, 0x00, 0x1F, 0xE0, 0x00, 0x0F, 0xF0, 0x00, 0x07, 0xF8,\n  0x00, 0x03, 0xFC, 0x00, 0x01, 0xFE, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x7F,\n  0x80, 0x00, 0x3F, 0xC0, 0x00, 0x1F, 0xE0, 0x00, 0x0F, 0xF0, 0x00, 0x07,\n  0xF8, 0x00, 0x03, 0xFC, 0x00, 0x01, 0xFE, 0x00, 0x00, 0xFF, 0x00, 0x00,\n  0x7F, 0xFF, 0xFC, 0x1F, 0xFF, 0xFF, 0x07, 0xFF, 0xFF, 0xC3, 0xFF, 0xFF,\n  0xE0, 0xFF, 0xFF, 0xF8, 0x00, 0x00, 0x0F, 0xC0, 0x0F, 0xF0, 0x07, 0xFC,\n  0x01, 0xFE, 0x00, 0xFF, 0x80, 0x3E, 0x00, 0x0F, 0x80, 0x07, 0xE0, 0x01,\n  0xF0, 0x00, 0x7C, 0x00, 0x1F, 0x00, 0x07, 0xC0, 0x03, 0xE0, 0x00, 0xF8,\n  0x00, 0x3E, 0x00, 0x0F, 0x80, 0x07, 0xE0, 0x01, 0xF0, 0x00, 0x7C, 0x00,\n  0x3F, 0x00, 0x7F, 0x80, 0x1F, 0x80, 0x07, 0xE0, 0x03, 0xFC, 0x00, 0x3F,\n  0x00, 0x07, 0xC0, 0x01, 0xF0, 0x00, 0x7C, 0x00, 0x1F, 0x00, 0x07, 0xC0,\n  0x01, 0xF0, 0x00, 0xF8, 0x00, 0x3E, 0x00, 0x0F, 0x80, 0x03, 0xE0, 0x01,\n  0xF0, 0x00, 0x7C, 0x00, 0x1F, 0x00, 0x07, 0xF8, 0x01, 0xFE, 0x00, 0x7F,\n  0x80, 0x0F, 0xE0, 0x01, 0xF8, 0x00, 0x00, 0x78, 0x03, 0xC0, 0x1C, 0x01,\n  0xE0, 0x0F, 0x00, 0x78, 0x03, 0xC0, 0x1C, 0x01, 0xE0, 0x0F, 0x00, 0x78,\n  0x03, 0xC0, 0x1C, 0x01, 0xE0, 0x0F, 0x00, 0x78, 0x03, 0xC0, 0x3C, 0x01,\n  0xE0, 0x0F, 0x00, 0x78, 0x03, 0x80, 0x3C, 0x01, 0xE0, 0x0F, 0x00, 0x78,\n  0x03, 0x80, 0x3C, 0x01, 0xE0, 0x0F, 0x00, 0x78, 0x03, 0x80, 0x3C, 0x01,\n  0xE0, 0x0F, 0x00, 0x70, 0x07, 0x80, 0x3C, 0x01, 0xE0, 0x0F, 0x00, 0x70,\n  0x07, 0x80, 0x3C, 0x00, 0x00, 0x7E, 0x00, 0x1F, 0xC0, 0x07, 0xF0, 0x01,\n  0xFE, 0x00, 0x7F, 0x80, 0x03, 0xE0, 0x00, 0xF8, 0x00, 0x3E, 0x00, 0x1F,\n  0x00, 0x07, 0xC0, 0x01, 0xF0, 0x00, 0x7C, 0x00, 0x3E, 0x00, 0x0F, 0x80,\n  0x03, 0xE0, 0x00, 0xF8, 0x00, 0x3E, 0x00, 0x0F, 0x80, 0x03, 0xF0, 0x00,\n  0xFF, 0x00, 0x1F, 0x80, 0x07, 0xE0, 0x07, 0xF8, 0x03, 0xF0, 0x00, 0xF8,\n  0x00, 0x3E, 0x00, 0x1F, 0x00, 0x07, 0xC0, 0x01, 0xF0, 0x00, 0x7C, 0x00,\n  0x1F, 0x00, 0x0F, 0x80, 0x03, 0xE0, 0x00, 0xF8, 0x00, 0x3E, 0x00, 0x1F,\n  0x80, 0x07, 0xC0, 0x01, 0xF0, 0x07, 0xFC, 0x01, 0xFE, 0x00, 0xFF, 0x80,\n  0x3F, 0xC0, 0x0F, 0xC0, 0x00, 0x0F, 0x80, 0x00, 0xFF, 0x80, 0x07, 0xFF,\n  0x03, 0xDF, 0xFE, 0x0F, 0xF0, 0x7F, 0xFB, 0x80, 0xFF, 0xE0, 0x01, 0xFF,\n  0x00, 0x03, 0xF0 };\n\nconst GFXglyph FreeSansBoldOblique24pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,  13,    0,    1 },   // 0x20 ' '\n  {     0,  14,  34,  16,    5,  -33 },   // 0x21 '!'\n  {    60,  18,  12,  22,    8,  -33 },   // 0x22 '\"'\n  {    87,  29,  33,  26,    2,  -31 },   // 0x23 '#'\n  {   207,  26,  42,  26,    3,  -35 },   // 0x24 '$'\n  {   344,  36,  34,  42,    6,  -32 },   // 0x25 '%'\n  {   497,  29,  35,  34,    4,  -33 },   // 0x26 '&'\n  {   624,   7,  12,  11,    8,  -33 },   // 0x27 '''\n  {   635,  17,  44,  16,    4,  -33 },   // 0x28 '('\n  {   729,  17,  44,  16,    0,  -34 },   // 0x29 ')'\n  {   823,  15,  15,  18,    7,  -33 },   // 0x2A '*'\n  {   852,  24,  22,  27,    4,  -21 },   // 0x2B '+'\n  {   918,  10,  15,  13,    1,   -6 },   // 0x2C ','\n  {   937,  14,   6,  16,    3,  -15 },   // 0x2D '-'\n  {   948,   8,   7,  13,    3,   -6 },   // 0x2E '.'\n  {   955,  20,  34,  13,    0,  -32 },   // 0x2F '/'\n  {  1040,  25,  35,  26,    4,  -33 },   // 0x30 '0'\n  {  1150,  17,  33,  26,    8,  -32 },   // 0x31 '1'\n  {  1221,  29,  34,  26,    1,  -33 },   // 0x32 '2'\n  {  1345,  26,  35,  26,    3,  -33 },   // 0x33 '3'\n  {  1459,  25,  32,  26,    3,  -31 },   // 0x34 '4'\n  {  1559,  27,  34,  26,    3,  -32 },   // 0x35 '5'\n  {  1674,  25,  35,  26,    4,  -33 },   // 0x36 '6'\n  {  1784,  26,  33,  26,    6,  -32 },   // 0x37 '7'\n  {  1892,  26,  35,  26,    3,  -33 },   // 0x38 '8'\n  {  2006,  25,  35,  26,    4,  -33 },   // 0x39 '9'\n  {  2116,  12,  25,  16,    5,  -24 },   // 0x3A ':'\n  {  2154,  14,  33,  16,    3,  -24 },   // 0x3B ';'\n  {  2212,  26,  23,  27,    4,  -22 },   // 0x3C '<'\n  {  2287,  26,  18,  27,    3,  -19 },   // 0x3D '='\n  {  2346,  26,  23,  27,    1,  -21 },   // 0x3E '>'\n  {  2421,  24,  35,  29,    8,  -34 },   // 0x3F '?'\n  {  2526,  45,  41,  46,    3,  -34 },   // 0x40 '@'\n  {  2757,  32,  34,  34,    1,  -33 },   // 0x41 'A'\n  {  2893,  32,  34,  34,    4,  -33 },   // 0x42 'B'\n  {  3029,  32,  36,  34,    5,  -34 },   // 0x43 'C'\n  {  3173,  32,  34,  34,    4,  -33 },   // 0x44 'D'\n  {  3309,  32,  34,  31,    4,  -33 },   // 0x45 'E'\n  {  3445,  32,  34,  29,    3,  -33 },   // 0x46 'F'\n  {  3581,  33,  36,  37,    5,  -34 },   // 0x47 'G'\n  {  3730,  35,  34,  34,    3,  -33 },   // 0x48 'H'\n  {  3879,  14,  34,  13,    3,  -33 },   // 0x49 'I'\n  {  3939,  27,  35,  26,    3,  -33 },   // 0x4A 'J'\n  {  4058,  37,  34,  34,    3,  -33 },   // 0x4B 'K'\n  {  4216,  24,  34,  29,    4,  -33 },   // 0x4C 'L'\n  {  4318,  41,  34,  39,    3,  -33 },   // 0x4D 'M'\n  {  4493,  35,  34,  34,    3,  -33 },   // 0x4E 'N'\n  {  4642,  34,  36,  37,    5,  -34 },   // 0x4F 'O'\n  {  4795,  31,  34,  31,    4,  -33 },   // 0x50 'P'\n  {  4927,  34,  37,  37,    5,  -34 },   // 0x51 'Q'\n  {  5085,  33,  34,  34,    4,  -33 },   // 0x52 'R'\n  {  5226,  30,  36,  31,    4,  -34 },   // 0x53 'S'\n  {  5361,  28,  34,  29,    7,  -33 },   // 0x54 'T'\n  {  5480,  32,  35,  34,    6,  -33 },   // 0x55 'U'\n  {  5620,  30,  34,  31,    8,  -33 },   // 0x56 'V'\n  {  5748,  43,  34,  44,    8,  -33 },   // 0x57 'W'\n  {  5931,  37,  34,  31,    1,  -33 },   // 0x58 'X'\n  {  6089,  29,  34,  31,    9,  -33 },   // 0x59 'Y'\n  {  6213,  33,  34,  29,    1,  -33 },   // 0x5A 'Z'\n  {  6354,  21,  43,  16,    1,  -33 },   // 0x5B '['\n  {  6467,   7,  36,  13,    6,  -34 },   // 0x5C '\\'\n  {  6499,  21,  43,  16,   -1,  -33 },   // 0x5D ']'\n  {  6612,  21,  20,  27,    6,  -32 },   // 0x5E '^'\n  {  6665,  29,   4,  26,   -3,    6 },   // 0x5F '_'\n  {  6680,   7,   7,  16,    8,  -35 },   // 0x60 '`'\n  {  6687,  25,  26,  26,    2,  -24 },   // 0x61 'a'\n  {  6769,  27,  35,  29,    3,  -33 },   // 0x62 'b'\n  {  6888,  25,  26,  26,    4,  -24 },   // 0x63 'c'\n  {  6970,  29,  35,  29,    4,  -33 },   // 0x64 'd'\n  {  7097,  25,  26,  26,    3,  -24 },   // 0x65 'e'\n  {  7179,  18,  34,  16,    4,  -33 },   // 0x66 'f'\n  {  7256,  29,  35,  29,    2,  -24 },   // 0x67 'g'\n  {  7383,  27,  34,  29,    3,  -33 },   // 0x68 'h'\n  {  7498,  14,  34,  13,    3,  -33 },   // 0x69 'i'\n  {  7558,  19,  44,  13,   -2,  -33 },   // 0x6A 'j'\n  {  7663,  28,  34,  26,    3,  -33 },   // 0x6B 'k'\n  {  7782,  14,  34,  13,    3,  -33 },   // 0x6C 'l'\n  {  7842,  40,  25,  42,    3,  -24 },   // 0x6D 'm'\n  {  7967,  27,  25,  29,    3,  -24 },   // 0x6E 'n'\n  {  8052,  26,  26,  29,    4,  -24 },   // 0x6F 'o'\n  {  8137,  29,  35,  29,    1,  -24 },   // 0x70 'p'\n  {  8264,  28,  35,  29,    3,  -24 },   // 0x71 'q'\n  {  8387,  20,  25,  18,    3,  -24 },   // 0x72 'r'\n  {  8450,  24,  26,  26,    3,  -24 },   // 0x73 's'\n  {  8528,  14,  32,  16,    5,  -30 },   // 0x74 't'\n  {  8584,  27,  26,  29,    4,  -24 },   // 0x75 'u'\n  {  8672,  25,  25,  26,    6,  -24 },   // 0x76 'v'\n  {  8751,  35,  25,  37,    6,  -24 },   // 0x77 'w'\n  {  8861,  29,  25,  26,    1,  -24 },   // 0x78 'x'\n  {  8952,  29,  35,  26,    2,  -24 },   // 0x79 'y'\n  {  9079,  26,  25,  23,    1,  -24 },   // 0x7A 'z'\n  {  9161,  18,  43,  18,    4,  -33 },   // 0x7B '{'\n  {  9258,  13,  43,  13,    3,  -33 },   // 0x7C '|'\n  {  9328,  18,  43,  18,    2,  -33 },   // 0x7D '}'\n  {  9425,  22,   8,  27,    5,  -14 } }; // 0x7E '~'\n\nconst GFXfont FreeSansBoldOblique24pt7b PROGMEM = {\n  (uint8_t  *)FreeSansBoldOblique24pt7bBitmaps,\n  (GFXglyph *)FreeSansBoldOblique24pt7bGlyphs,\n  0x20, 0x7E, 56 };\n\n// Approx. 10119 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeSansBoldOblique9pt7b.h",
    "content": "const uint8_t FreeSansBoldOblique9pt7bBitmaps[] PROGMEM = {\n  0x21, 0x8E, 0x73, 0x18, 0xC6, 0x21, 0x19, 0xCE, 0x00, 0xEF, 0xDF, 0xBE,\n  0x68, 0x80, 0x06, 0xC1, 0x99, 0xFF, 0xBF, 0xF1, 0xB0, 0x66, 0x0C, 0xC7,\n  0xFC, 0xFF, 0x8C, 0x83, 0x30, 0x64, 0x00, 0x02, 0x00, 0xF0, 0x7F, 0x1D,\n  0x73, 0xEE, 0x78, 0x0F, 0x00, 0xF8, 0x0F, 0xC1, 0xBB, 0xA7, 0x74, 0xEF,\n  0xF8, 0xFE, 0x04, 0x00, 0x80, 0x3C, 0x11, 0xF8, 0x8E, 0x66, 0x31, 0x90,\n  0xCE, 0x83, 0xF4, 0x07, 0xB0, 0x00, 0x9E, 0x04, 0xFC, 0x26, 0x31, 0x98,\n  0xC4, 0x7E, 0x20, 0xF0, 0x07, 0x80, 0xFC, 0x1D, 0xC1, 0xDC, 0x1F, 0x80,\n  0xE0, 0x3E, 0x37, 0x77, 0xE3, 0xEE, 0x3C, 0xE3, 0xCF, 0xFE, 0x3C, 0xE0,\n  0xFF, 0xE8, 0x06, 0x06, 0x0C, 0x18, 0x38, 0x30, 0x70, 0x60, 0xE0, 0xE0,\n  0xE0, 0xE0, 0xE0, 0xE0, 0x60, 0x70, 0x30, 0x0C, 0x0E, 0x06, 0x07, 0x07,\n  0x07, 0x07, 0x07, 0x07, 0x06, 0x0E, 0x0C, 0x1C, 0x18, 0x30, 0x60, 0x60,\n  0x32, 0xBF, 0x9C, 0xD2, 0x40, 0x0C, 0x06, 0x07, 0x1F, 0xFF, 0xF0, 0xC0,\n  0xE0, 0x60, 0x77, 0x72, 0x6C, 0xFF, 0xC0, 0xFC, 0x02, 0x02, 0x04, 0x04,\n  0x08, 0x08, 0x10, 0x10, 0x20, 0x20, 0x40, 0x40, 0x80, 0x0F, 0x07, 0xE3,\n  0x9D, 0xC7, 0x71, 0xDC, 0x7E, 0x1F, 0x8E, 0xE3, 0xB8, 0xEE, 0x73, 0xF8,\n  0x3C, 0x00, 0x04, 0x3B, 0xF7, 0xE1, 0xC3, 0x06, 0x1C, 0x38, 0x70, 0xC1,\n  0x87, 0x00, 0x0F, 0x87, 0xFC, 0xE3, 0xB8, 0x70, 0x0E, 0x03, 0x80, 0xF0,\n  0x38, 0x1E, 0x07, 0x01, 0xC0, 0x7F, 0xCF, 0xF8, 0x0F, 0xC7, 0xFC, 0xE3,\n  0xB8, 0x70, 0x1C, 0x0F, 0x03, 0xF0, 0x0E, 0x01, 0xDC, 0x3B, 0x8E, 0x7F,\n  0x83, 0xE0, 0x03, 0xC0, 0xE0, 0x58, 0x2E, 0x13, 0x8C, 0xE6, 0x33, 0xFE,\n  0xFF, 0x81, 0xC0, 0x60, 0x18, 0x0F, 0xE3, 0xFC, 0x60, 0x0C, 0x03, 0x78,\n  0x7F, 0x9C, 0x70, 0x0E, 0x01, 0xDC, 0x33, 0x8E, 0x7F, 0x83, 0xE0, 0x0F,\n  0x07, 0xE3, 0x9D, 0xC0, 0x7F, 0x1F, 0xEF, 0x3B, 0x8E, 0xE3, 0xB8, 0xCE,\n  0x71, 0xF8, 0x3C, 0x00, 0x7F, 0xDF, 0xF0, 0x18, 0x0C, 0x06, 0x03, 0x81,\n  0xC0, 0x60, 0x38, 0x0C, 0x07, 0x01, 0x80, 0x60, 0x00, 0x0F, 0x83, 0xFC,\n  0xE3, 0x9C, 0x73, 0x9C, 0x3F, 0x0F, 0xE3, 0x8E, 0xE1, 0xDC, 0x3B, 0x8E,\n  0x7F, 0xC3, 0xE0, 0x0F, 0x83, 0xF8, 0xE3, 0xB8, 0x77, 0x0E, 0xE1, 0xDC,\n  0x7B, 0xFE, 0x3D, 0xC0, 0x33, 0x8E, 0x7F, 0x87, 0xC0, 0x77, 0x00, 0x00,\n  0x0E, 0xE0, 0x39, 0xC0, 0x00, 0x01, 0xCE, 0x71, 0x19, 0x80, 0x00, 0x00,\n  0x70, 0xFD, 0xF8, 0x70, 0x3F, 0x03, 0xF8, 0x1E, 0x01, 0x80, 0x7F, 0xDF,\n  0xF0, 0x00, 0x00, 0xFF, 0xBF, 0xE0, 0x60, 0x1E, 0x07, 0xF0, 0x3F, 0x03,\n  0x87, 0xEF, 0xC3, 0x80, 0x00, 0x00, 0x1F, 0x1F, 0xFE, 0x1F, 0x87, 0x01,\n  0xC0, 0xE0, 0x70, 0x78, 0x3C, 0x0E, 0x00, 0x00, 0xE0, 0x38, 0x00, 0x00,\n  0xFC, 0x00, 0xFF, 0xC0, 0xF0, 0x78, 0x70, 0x07, 0x38, 0x01, 0xCC, 0x3F,\n  0x36, 0x31, 0x8D, 0x98, 0x63, 0xC4, 0x11, 0xF3, 0x0C, 0x6C, 0xC6, 0x73,\n  0x3E, 0xF8, 0xE7, 0x3C, 0x1E, 0x00, 0x03, 0xFE, 0x00, 0x3F, 0x00, 0x01,\n  0xE0, 0x0F, 0x00, 0xF8, 0x07, 0xC0, 0x6F, 0x03, 0x38, 0x31, 0xC3, 0x8E,\n  0x1F, 0xF1, 0xFF, 0x8C, 0x1E, 0xE0, 0x76, 0x03, 0x80, 0x1F, 0xF0, 0xFF,\n  0xC6, 0x0E, 0x70, 0x73, 0x87, 0x1F, 0xF0, 0xFF, 0x86, 0x0E, 0x70, 0x73,\n  0x83, 0x9C, 0x38, 0xFF, 0xC7, 0xF8, 0x00, 0x07, 0xE0, 0xFF, 0x8F, 0x1E,\n  0x70, 0x77, 0x00, 0x30, 0x03, 0x80, 0x1C, 0x00, 0xE0, 0x07, 0x03, 0xBC,\n  0x38, 0xFF, 0x83, 0xF0, 0x00, 0x1F, 0xE0, 0xFF, 0x86, 0x1E, 0x70, 0x73,\n  0x83, 0x9C, 0x1C, 0xC0, 0xE6, 0x07, 0x70, 0x73, 0x83, 0x9C, 0x38, 0xFF,\n  0x8F, 0xF0, 0x00, 0x1F, 0xF8, 0xFF, 0x86, 0x00, 0x70, 0x03, 0x80, 0x1F,\n  0xF0, 0xFF, 0x86, 0x00, 0x70, 0x03, 0x80, 0x1C, 0x00, 0xFF, 0xC7, 0xFC,\n  0x00, 0x1F, 0xF1, 0xFF, 0x18, 0x03, 0x80, 0x38, 0x03, 0xFC, 0x3F, 0xC7,\n  0x00, 0x70, 0x07, 0x00, 0x70, 0x06, 0x00, 0xE0, 0x00, 0x07, 0xC1, 0xFE,\n  0x38, 0x77, 0x03, 0x70, 0x0E, 0x00, 0xE1, 0xEE, 0x1E, 0xE0, 0x6E, 0x0E,\n  0x70, 0xE7, 0xFC, 0x1F, 0x40, 0x1C, 0x1C, 0x60, 0x63, 0x83, 0x8E, 0x0E,\n  0x38, 0x38, 0xFF, 0xC3, 0xFF, 0x1C, 0x1C, 0x70, 0x71, 0xC1, 0xC6, 0x06,\n  0x18, 0x38, 0xE0, 0xE0, 0x39, 0xCE, 0x63, 0x39, 0xCE, 0x63, 0x39, 0xCE,\n  0x00, 0x00, 0xC0, 0x18, 0x07, 0x00, 0xE0, 0x1C, 0x03, 0x00, 0xE0, 0x1C,\n  0xE3, 0x9C, 0x73, 0x9C, 0x7F, 0x87, 0xC0, 0x1C, 0x3C, 0x71, 0xC1, 0x8E,\n  0x0E, 0x70, 0x3B, 0x80, 0xFC, 0x03, 0xF0, 0x0E, 0xE0, 0x73, 0x81, 0xC7,\n  0x07, 0x1C, 0x18, 0x38, 0xE0, 0xF0, 0x1C, 0x07, 0x01, 0x80, 0xE0, 0x38,\n  0x0E, 0x03, 0x80, 0xC0, 0x70, 0x1C, 0x07, 0x01, 0xFF, 0x7F, 0x80, 0x1E,\n  0x1F, 0x1E, 0x1E, 0x3E, 0x1E, 0x3E, 0x3E, 0x36, 0x3E, 0x36, 0x6E, 0x36,\n  0x6C, 0x76, 0xCC, 0x76, 0xDC, 0x67, 0x9C, 0x67, 0x98, 0xE7, 0x18, 0xE7,\n  0x18, 0x1C, 0x1C, 0x70, 0x63, 0xE1, 0x8F, 0x8E, 0x3E, 0x38, 0xDC, 0xC3,\n  0x33, 0x1C, 0xEC, 0x71, 0xF1, 0xC7, 0xC6, 0x1E, 0x18, 0x38, 0xE0, 0xE0,\n  0x07, 0xC0, 0xFF, 0x8E, 0x1E, 0xE0, 0x77, 0x03, 0xF0, 0x1F, 0x80, 0xFC,\n  0x07, 0xE0, 0x77, 0x03, 0xBC, 0x38, 0xFF, 0x81, 0xF0, 0x00, 0x1F, 0xF0,\n  0xFF, 0xC6, 0x0E, 0x70, 0x73, 0x83, 0x9C, 0x38, 0xFF, 0x87, 0xF8, 0x70,\n  0x03, 0x80, 0x1C, 0x00, 0xC0, 0x0E, 0x00, 0x00, 0x07, 0xC0, 0xFF, 0x8F,\n  0x1C, 0xE0, 0x77, 0x03, 0xB0, 0x1F, 0x80, 0xFC, 0x06, 0xE1, 0x77, 0x1F,\n  0x3C, 0x78, 0xFF, 0xC1, 0xF6, 0x00, 0x20, 0x1F, 0xF0, 0xFF, 0xC6, 0x0E,\n  0x70, 0x73, 0x83, 0x9C, 0x38, 0xFF, 0x87, 0xFC, 0x70, 0x73, 0x83, 0x9C,\n  0x38, 0xC1, 0xC6, 0x0F, 0x00, 0x07, 0xE0, 0xFF, 0xC7, 0x0E, 0x70, 0x73,\n  0x80, 0x1F, 0x80, 0x7F, 0x80, 0x7E, 0x00, 0x77, 0x03, 0xBC, 0x38, 0xFF,\n  0xC3, 0xF8, 0x00, 0xFF, 0xDF, 0xF8, 0x70, 0x0E, 0x01, 0xC0, 0x38, 0x06,\n  0x01, 0xC0, 0x38, 0x07, 0x00, 0xC0, 0x18, 0x07, 0x00, 0x38, 0x31, 0xC1,\n  0x8C, 0x1C, 0xE0, 0xE7, 0x07, 0x38, 0x31, 0xC3, 0x9C, 0x1C, 0xE0, 0xE7,\n  0x06, 0x38, 0x70, 0xFF, 0x03, 0xE0, 0x00, 0xE0, 0xFC, 0x1D, 0x87, 0x30,\n  0xC6, 0x38, 0xC6, 0x19, 0xC3, 0xB0, 0x7E, 0x0F, 0x80, 0xF0, 0x1C, 0x03,\n  0x00, 0xE1, 0xC3, 0xF1, 0xE3, 0xB8, 0xF1, 0xDC, 0x78, 0xCE, 0x6C, 0xE7,\n  0x36, 0x63, 0xB3, 0x70, 0xD9, 0xB0, 0x7C, 0xD8, 0x3C, 0x78, 0x1E, 0x3C,\n  0x0E, 0x1C, 0x07, 0x0E, 0x00, 0x0E, 0x1C, 0x38, 0xE0, 0xE7, 0x01, 0xD8,\n  0x07, 0xE0, 0x0F, 0x00, 0x38, 0x01, 0xE0, 0x0F, 0xC0, 0x77, 0x01, 0x8E,\n  0x0E, 0x38, 0x70, 0xF0, 0xE0, 0xEE, 0x39, 0xC7, 0x39, 0xC3, 0x70, 0x7C,\n  0x0F, 0x80, 0xE0, 0x1C, 0x03, 0x00, 0xE0, 0x1C, 0x03, 0x80, 0x3F, 0xF3,\n  0xFF, 0x00, 0xE0, 0x1C, 0x03, 0x80, 0x70, 0x0E, 0x01, 0xC0, 0x3C, 0x07,\n  0x80, 0x70, 0x0F, 0xFC, 0xFF, 0xC0, 0x0F, 0x0F, 0x0C, 0x1C, 0x18, 0x18,\n  0x18, 0x18, 0x30, 0x30, 0x30, 0x30, 0x60, 0x60, 0x60, 0x78, 0x78, 0x12,\n  0x4C, 0x92, 0x49, 0x26, 0xD9, 0x20, 0x1E, 0x1E, 0x06, 0x06, 0x06, 0x0C,\n  0x0C, 0x0C, 0x0C, 0x18, 0x18, 0x18, 0x18, 0x38, 0x30, 0xF0, 0xF0, 0x06,\n  0x0E, 0x0E, 0x1B, 0x33, 0x33, 0x63, 0x63, 0xFF, 0xE0, 0xCC, 0x1F, 0x8F,\n  0xF3, 0x1C, 0x06, 0x1F, 0x9F, 0xEE, 0x3B, 0x9C, 0xFF, 0x1D, 0xC0, 0x18,\n  0x03, 0x00, 0xE0, 0x1D, 0xC3, 0xFC, 0x71, 0xDC, 0x3B, 0x87, 0x70, 0xEE,\n  0x39, 0xCF, 0x7F, 0xCF, 0xE0, 0x0F, 0x0F, 0xF7, 0x1D, 0xC0, 0xE0, 0x38,\n  0x0E, 0x03, 0x8E, 0x7F, 0x0F, 0x80, 0x00, 0x60, 0x06, 0x00, 0x61, 0xEE,\n  0x3F, 0xE7, 0x9C, 0x71, 0xCE, 0x1C, 0xE1, 0xCE, 0x1C, 0xE3, 0x87, 0xF8,\n  0x7F, 0x80, 0x1F, 0x0F, 0xE7, 0x1D, 0xC7, 0xFF, 0xFF, 0xFE, 0x03, 0x8E,\n  0x7F, 0x0F, 0x80, 0x1C, 0xF3, 0x3F, 0xFD, 0xC7, 0x18, 0x63, 0x8E, 0x30,\n  0xC0, 0x0F, 0x71, 0xFE, 0x3C, 0xE3, 0x8E, 0x70, 0xE7, 0x0E, 0x70, 0xC7,\n  0x1C, 0x3F, 0xC3, 0xFC, 0x01, 0xCE, 0x38, 0x7F, 0x03, 0xE0, 0x18, 0x03,\n  0x00, 0xE0, 0x1D, 0xE3, 0xFE, 0x71, 0xCC, 0x3B, 0x86, 0x70, 0xCC, 0x39,\n  0x87, 0x30, 0xEE, 0x18, 0x39, 0xC0, 0x63, 0x39, 0xCE, 0x63, 0x39, 0xCE,\n  0x00, 0x06, 0x06, 0x00, 0x0E, 0x0E, 0x0C, 0x0C, 0x1C, 0x1C, 0x1C, 0x18,\n  0x18, 0x38, 0x38, 0x30, 0x70, 0xE0, 0x18, 0x03, 0x00, 0xE0, 0x1C, 0xE3,\n  0x38, 0x6E, 0x1F, 0x83, 0xF0, 0x7E, 0x0E, 0xE1, 0x9C, 0x73, 0x8E, 0x38,\n  0x39, 0xCE, 0x63, 0x39, 0xCE, 0x63, 0x39, 0xCE, 0x00, 0x3B, 0x9E, 0x3F,\n  0xFF, 0x39, 0xC7, 0x71, 0xC6, 0x71, 0x86, 0x71, 0x8E, 0x63, 0x8E, 0x63,\n  0x8C, 0xE3, 0x8C, 0xE3, 0x1C, 0x3B, 0xC7, 0xFC, 0xE3, 0xB8, 0x77, 0x0C,\n  0xE1, 0x98, 0x73, 0x0E, 0xE1, 0xDC, 0x30, 0x0F, 0x87, 0xF9, 0xE7, 0xB8,\n  0x7E, 0x0F, 0xC1, 0xF8, 0x77, 0x9E, 0x7F, 0x87, 0xC0, 0x1D, 0xE1, 0xFE,\n  0x1C, 0x73, 0x87, 0x38, 0x73, 0x87, 0x38, 0xE3, 0x8E, 0x7F, 0xC7, 0xF8,\n  0x60, 0x06, 0x00, 0x60, 0x0E, 0x00, 0x1E, 0xE7, 0xFD, 0xE7, 0x38, 0xEE,\n  0x1D, 0xC3, 0xB8, 0x77, 0x1C, 0x7F, 0x8F, 0xF0, 0x0E, 0x01, 0x80, 0x30,\n  0x06, 0x00, 0x3B, 0x36, 0x38, 0x70, 0x70, 0x70, 0x60, 0x60, 0xE0, 0xE0,\n  0x3E, 0x3F, 0xF8, 0xFC, 0x0F, 0xC3, 0xF8, 0x3D, 0x8E, 0xFE, 0x3E, 0x00,\n  0x38, 0xCF, 0xFE, 0x71, 0x86, 0x38, 0xE3, 0x8F, 0x3C, 0x31, 0xDC, 0x77,\n  0x19, 0x86, 0x63, 0xB8, 0xEE, 0x33, 0x9C, 0xFF, 0x1F, 0xC0, 0xE1, 0x98,\n  0xE6, 0x31, 0x9C, 0x66, 0x1B, 0x86, 0xC1, 0xF0, 0x78, 0x0E, 0x00, 0xE7,\n  0x1B, 0x9C, 0xEE, 0x73, 0x3B, 0xDC, 0xEB, 0x63, 0xAD, 0x8F, 0xBC, 0x1C,\n  0xF0, 0x73, 0xC1, 0xCE, 0x00, 0x1C, 0xE1, 0xCC, 0x0D, 0x80, 0xF8, 0x0F,\n  0x00, 0xF0, 0x1F, 0x03, 0xB8, 0x33, 0x87, 0x38, 0x70, 0xCE, 0x38, 0xC6,\n  0x19, 0xC3, 0x30, 0x66, 0x0F, 0x81, 0xF0, 0x3C, 0x03, 0x80, 0x60, 0x18,\n  0x0F, 0x01, 0xC0, 0x00, 0x1F, 0xCF, 0xF0, 0x38, 0x1C, 0x0E, 0x07, 0x03,\n  0x81, 0xC0, 0x7F, 0xBF, 0xE0, 0x0E, 0x38, 0x61, 0x83, 0x06, 0x0C, 0x78,\n  0xF0, 0xC1, 0x83, 0x0E, 0x1C, 0x38, 0x78, 0x70, 0x18, 0xC4, 0x21, 0x18,\n  0xC4, 0x21, 0x18, 0xC4, 0x23, 0x18, 0x80, 0x1C, 0x3C, 0x38, 0x70, 0xE1,\n  0x83, 0x06, 0x1E, 0x5C, 0x60, 0xC1, 0x83, 0x0C, 0x38, 0xE0, 0x71, 0x8E };\n\nconst GFXglyph FreeSansBoldOblique9pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,   5,    0,    1 },   // 0x20 ' '\n  {     0,   5,  13,   6,    2,  -12 },   // 0x21 '!'\n  {     9,   7,   5,   9,    3,  -12 },   // 0x22 '\"'\n  {    14,  11,  12,  10,    1,  -11 },   // 0x23 '#'\n  {    31,  11,  16,  10,    1,  -13 },   // 0x24 '$'\n  {    53,  14,  13,  16,    2,  -12 },   // 0x25 '%'\n  {    76,  12,  13,  13,    2,  -12 },   // 0x26 '&'\n  {    96,   3,   5,   4,    3,  -12 },   // 0x27 '''\n  {    98,   8,  17,   6,    2,  -12 },   // 0x28 '('\n  {   115,   8,  17,   6,   -2,  -13 },   // 0x29 ')'\n  {   132,   6,   6,   7,    3,  -12 },   // 0x2A '*'\n  {   137,   9,   8,  11,    2,   -7 },   // 0x2B '+'\n  {   146,   4,   6,   5,    0,   -2 },   // 0x2C ','\n  {   149,   5,   2,   6,    1,   -5 },   // 0x2D '-'\n  {   151,   3,   2,   5,    1,   -1 },   // 0x2E '.'\n  {   152,   8,  13,   5,    0,  -12 },   // 0x2F '/'\n  {   165,  10,  13,  10,    1,  -12 },   // 0x30 '0'\n  {   182,   7,  13,  10,    3,  -12 },   // 0x31 '1'\n  {   194,  11,  13,  10,    1,  -12 },   // 0x32 '2'\n  {   212,  11,  13,  10,    1,  -12 },   // 0x33 '3'\n  {   230,  10,  12,  10,    1,  -11 },   // 0x34 '4'\n  {   245,  11,  13,  10,    1,  -12 },   // 0x35 '5'\n  {   263,  10,  13,  10,    2,  -12 },   // 0x36 '6'\n  {   280,  10,  13,  10,    2,  -12 },   // 0x37 '7'\n  {   297,  11,  13,  10,    1,  -12 },   // 0x38 '8'\n  {   315,  11,  13,  10,    1,  -12 },   // 0x39 '9'\n  {   333,   4,   9,   6,    2,   -8 },   // 0x3A ':'\n  {   338,   5,  12,   6,    1,   -8 },   // 0x3B ';'\n  {   346,  10,   9,  11,    1,   -8 },   // 0x3C '<'\n  {   358,  10,   6,  11,    1,   -6 },   // 0x3D '='\n  {   366,  10,   9,  11,    1,   -7 },   // 0x3E '>'\n  {   378,  10,  13,  11,    3,  -12 },   // 0x3F '?'\n  {   395,  18,  16,  18,    1,  -13 },   // 0x40 '@'\n  {   431,  13,  13,  13,    0,  -12 },   // 0x41 'A'\n  {   453,  13,  13,  13,    1,  -12 },   // 0x42 'B'\n  {   475,  13,  13,  13,    2,  -12 },   // 0x43 'C'\n  {   497,  13,  13,  13,    1,  -12 },   // 0x44 'D'\n  {   519,  13,  13,  12,    1,  -12 },   // 0x45 'E'\n  {   541,  12,  13,  11,    1,  -12 },   // 0x46 'F'\n  {   561,  12,  13,  14,    2,  -12 },   // 0x47 'G'\n  {   581,  14,  13,  13,    1,  -12 },   // 0x48 'H'\n  {   604,   5,  13,   5,    1,  -12 },   // 0x49 'I'\n  {   613,  11,  13,  10,    1,  -12 },   // 0x4A 'J'\n  {   631,  14,  13,  13,    1,  -12 },   // 0x4B 'K'\n  {   654,  10,  13,  11,    1,  -12 },   // 0x4C 'L'\n  {   671,  16,  13,  15,    1,  -12 },   // 0x4D 'M'\n  {   697,  14,  13,  13,    1,  -12 },   // 0x4E 'N'\n  {   720,  13,  13,  14,    2,  -12 },   // 0x4F 'O'\n  {   742,  13,  13,  12,    1,  -12 },   // 0x50 'P'\n  {   764,  13,  14,  14,    2,  -12 },   // 0x51 'Q'\n  {   787,  13,  13,  13,    1,  -12 },   // 0x52 'R'\n  {   809,  13,  13,  12,    1,  -12 },   // 0x53 'S'\n  {   831,  11,  13,  11,    3,  -12 },   // 0x54 'T'\n  {   849,  13,  13,  13,    2,  -12 },   // 0x55 'U'\n  {   871,  11,  13,  12,    3,  -12 },   // 0x56 'V'\n  {   889,  17,  13,  17,    3,  -12 },   // 0x57 'W'\n  {   917,  14,  13,  12,    0,  -12 },   // 0x58 'X'\n  {   940,  11,  13,  12,    3,  -12 },   // 0x59 'Y'\n  {   958,  12,  13,  11,    1,  -12 },   // 0x5A 'Z'\n  {   978,   8,  17,   6,    0,  -12 },   // 0x5B '['\n  {   995,   3,  17,   5,    2,  -16 },   // 0x5C '\\'\n  {  1002,   8,  17,   6,    0,  -13 },   // 0x5D ']'\n  {  1019,   8,   8,  11,    2,  -12 },   // 0x5E '^'\n  {  1027,  11,   1,  10,   -1,    4 },   // 0x5F '_'\n  {  1029,   3,   2,   6,    3,  -12 },   // 0x60 '`'\n  {  1030,  10,  10,  10,    1,   -9 },   // 0x61 'a'\n  {  1043,  11,  13,  11,    1,  -12 },   // 0x62 'b'\n  {  1061,  10,  10,  10,    1,   -9 },   // 0x63 'c'\n  {  1074,  12,  13,  11,    1,  -12 },   // 0x64 'd'\n  {  1094,  10,  10,  10,    1,   -9 },   // 0x65 'e'\n  {  1107,   6,  13,   6,    2,  -12 },   // 0x66 'f'\n  {  1117,  12,  14,  11,    0,   -9 },   // 0x67 'g'\n  {  1138,  11,  13,  11,    1,  -12 },   // 0x68 'h'\n  {  1156,   5,  13,   5,    1,  -12 },   // 0x69 'i'\n  {  1165,   8,  17,   5,   -1,  -12 },   // 0x6A 'j'\n  {  1182,  11,  13,  10,    1,  -12 },   // 0x6B 'k'\n  {  1200,   5,  13,   5,    1,  -12 },   // 0x6C 'l'\n  {  1209,  16,  10,  16,    1,   -9 },   // 0x6D 'm'\n  {  1229,  11,  10,  11,    1,   -9 },   // 0x6E 'n'\n  {  1243,  11,  10,  11,    1,   -9 },   // 0x6F 'o'\n  {  1257,  12,  14,  11,    0,   -9 },   // 0x70 'p'\n  {  1278,  11,  14,  11,    1,   -9 },   // 0x71 'q'\n  {  1298,   8,  10,   7,    1,   -9 },   // 0x72 'r'\n  {  1308,   9,  10,  10,    2,   -9 },   // 0x73 's'\n  {  1320,   6,  12,   6,    2,  -11 },   // 0x74 't'\n  {  1329,  10,  10,  11,    2,   -9 },   // 0x75 'u'\n  {  1342,  10,  10,  10,    2,   -9 },   // 0x76 'v'\n  {  1355,  14,  10,  14,    2,   -9 },   // 0x77 'w'\n  {  1373,  12,  10,  10,    0,   -9 },   // 0x78 'x'\n  {  1388,  11,  14,  10,    1,   -9 },   // 0x79 'y'\n  {  1408,  10,  10,   9,    0,   -9 },   // 0x7A 'z'\n  {  1421,   7,  17,   7,    2,  -12 },   // 0x7B '{'\n  {  1436,   5,  17,   5,    1,  -12 },   // 0x7C '|'\n  {  1447,   7,  17,   7,    0,  -13 },   // 0x7D '}'\n  {  1462,   8,   2,  11,    2,   -4 } }; // 0x7E '~'\n\nconst GFXfont FreeSansBoldOblique9pt7b PROGMEM = {\n  (uint8_t  *)FreeSansBoldOblique9pt7bBitmaps,\n  (GFXglyph *)FreeSansBoldOblique9pt7bGlyphs,\n  0x20, 0x7E, 22 };\n\n// Approx. 2136 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeSansOblique12pt7b.h",
    "content": "const uint8_t FreeSansOblique12pt7bBitmaps[] PROGMEM = {\n  0x0C, 0x61, 0x86, 0x18, 0x63, 0x0C, 0x30, 0xC2, 0x18, 0x61, 0x00, 0x00,\n  0xC3, 0x00, 0xCF, 0x3C, 0xE2, 0x8A, 0x20, 0x01, 0x8C, 0x03, 0x18, 0x06,\n  0x60, 0x18, 0xC0, 0x31, 0x83, 0xFF, 0x87, 0xFF, 0x03, 0x18, 0x0C, 0x60,\n  0x18, 0xC0, 0x23, 0x03, 0xFF, 0x8F, 0xFF, 0x02, 0x30, 0x0C, 0x60, 0x18,\n  0x80, 0x63, 0x00, 0xC6, 0x00, 0x00, 0x80, 0x3F, 0x03, 0xFC, 0x32, 0x73,\n  0x91, 0x99, 0x8C, 0xCC, 0x06, 0x60, 0x3E, 0x00, 0x7E, 0x01, 0xFC, 0x0C,\n  0xEC, 0x43, 0x62, 0x1B, 0x11, 0x9D, 0x9C, 0x7F, 0xC1, 0xF8, 0x02, 0x00,\n  0x10, 0x01, 0x80, 0x00, 0x00, 0x01, 0x83, 0xC0, 0x60, 0xFC, 0x18, 0x30,\n  0xC2, 0x0C, 0x18, 0xC1, 0x83, 0x30, 0x38, 0xCC, 0x03, 0xF1, 0x00, 0x3C,\n  0x40, 0x00, 0x18, 0xF0, 0x06, 0x3F, 0x01, 0x8C, 0x30, 0x23, 0x06, 0x0C,\n  0x60, 0xC3, 0x0E, 0x30, 0xC0, 0xFC, 0x10, 0x0F, 0x00, 0x01, 0xE0, 0x3F,\n  0x81, 0x8C, 0x18, 0x60, 0xC3, 0x06, 0x30, 0x1F, 0x00, 0xE0, 0x1F, 0x01,\n  0xDC, 0xD8, 0x6D, 0x81, 0xEC, 0x0E, 0x60, 0x73, 0x87, 0xCF, 0xE6, 0x3E,\n  0x38, 0xFE, 0xA0, 0x03, 0x06, 0x04, 0x0C, 0x18, 0x18, 0x30, 0x30, 0x60,\n  0x60, 0x60, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0x40, 0x60,\n  0x60, 0x20, 0x04, 0x06, 0x06, 0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,\n  0x03, 0x03, 0x06, 0x06, 0x06, 0x0C, 0x0C, 0x18, 0x18, 0x30, 0x20, 0x60,\n  0xC0, 0x0C, 0x0C, 0x49, 0x7F, 0x3C, 0x3C, 0x6C, 0x00, 0x03, 0x00, 0x30,\n  0x03, 0x00, 0x30, 0xFF, 0xFF, 0xFF, 0x06, 0x00, 0x60, 0x06, 0x00, 0xC0,\n  0x0C, 0x00, 0x77, 0x22, 0x6C, 0xFF, 0xF0, 0xFC, 0x00, 0x40, 0x30, 0x08,\n  0x06, 0x01, 0x00, 0xC0, 0x20, 0x18, 0x04, 0x02, 0x00, 0x80, 0x40, 0x10,\n  0x08, 0x02, 0x01, 0x00, 0xC0, 0x20, 0x00, 0x07, 0xC0, 0xFE, 0x1C, 0x73,\n  0x83, 0x30, 0x36, 0x03, 0x60, 0x36, 0x03, 0xC0, 0x7C, 0x07, 0xC0, 0x6C,\n  0x06, 0xC0, 0xEC, 0x0C, 0xE3, 0x87, 0xF0, 0x3E, 0x00, 0x02, 0x0C, 0x77,\n  0xEF, 0xC1, 0x83, 0x0C, 0x18, 0x30, 0x61, 0xC3, 0x06, 0x0C, 0x18, 0x60,\n  0x03, 0xF0, 0x1F, 0xE0, 0xE1, 0xC7, 0x03, 0x18, 0x0C, 0x00, 0x30, 0x01,\n  0x80, 0x0E, 0x00, 0x70, 0x07, 0x80, 0x78, 0x07, 0x80, 0x38, 0x01, 0xC0,\n  0x06, 0x00, 0x1F, 0xFC, 0xFF, 0xE0, 0x07, 0xC0, 0xFE, 0x1C, 0x73, 0x03,\n  0x30, 0x30, 0x03, 0x00, 0xE0, 0x7C, 0x07, 0xC0, 0x0E, 0x00, 0x60, 0x06,\n  0xC0, 0x6C, 0x0C, 0xE1, 0xC7, 0xF8, 0x3E, 0x00, 0x00, 0x60, 0x06, 0x00,\n  0xE0, 0x1E, 0x03, 0xE0, 0x6C, 0x0C, 0xC1, 0x8C, 0x30, 0xC6, 0x1C, 0xC1,\n  0x8F, 0xFF, 0xFF, 0xE0, 0x18, 0x03, 0x00, 0x30, 0x03, 0x00, 0x0F, 0xF8,\n  0x7F, 0xC6, 0x00, 0x30, 0x01, 0x00, 0x1B, 0xC0, 0xFF, 0x06, 0x1C, 0x60,\n  0x60, 0x03, 0x00, 0x18, 0x00, 0xC0, 0x0C, 0x60, 0x63, 0x86, 0x0F, 0xE0,\n  0x3E, 0x00, 0x03, 0xC0, 0xFE, 0x1C, 0x73, 0x83, 0x30, 0x06, 0x00, 0x67,\n  0x87, 0xFC, 0xF0, 0xEE, 0x06, 0xC0, 0x6C, 0x06, 0xC0, 0x4C, 0x0C, 0xE1,\n  0x87, 0xF8, 0x3E, 0x00, 0x3F, 0xFB, 0xFF, 0xC0, 0x0C, 0x00, 0xC0, 0x0C,\n  0x00, 0xC0, 0x06, 0x00, 0x60, 0x06, 0x00, 0x70, 0x03, 0x00, 0x30, 0x03,\n  0x80, 0x18, 0x01, 0xC0, 0x0C, 0x00, 0xE0, 0x00, 0x07, 0xC0, 0xFE, 0x1C,\n  0x73, 0x03, 0x30, 0x33, 0x03, 0x38, 0x61, 0xFC, 0x3F, 0xC7, 0x0E, 0x60,\n  0x6C, 0x06, 0xC0, 0x6C, 0x0C, 0xE1, 0xC7, 0xF8, 0x3E, 0x00, 0x07, 0xC1,\n  0xFE, 0x38, 0x73, 0x03, 0x60, 0x36, 0x03, 0x60, 0x36, 0x07, 0x70, 0xF3,\n  0xFE, 0x1E, 0x60, 0x0E, 0x00, 0xCC, 0x1C, 0xE3, 0x87, 0xF0, 0x3C, 0x00,\n  0x39, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x39, 0xC0, 0x1C, 0x70, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x07, 0x1C, 0x20, 0x86, 0x30, 0x00, 0x00, 0x01, 0xC0,\n  0x3C, 0x0F, 0x81, 0xE0, 0x7C, 0x03, 0x80, 0x0F, 0x00, 0x1F, 0x00, 0x3E,\n  0x00, 0x38, 0x00, 0x40, 0x7F, 0xFB, 0xFF, 0x80, 0x00, 0x00, 0x0F, 0xFF,\n  0x7F, 0xF0, 0x20, 0x01, 0xC0, 0x07, 0xC0, 0x0F, 0x80, 0x0F, 0x00, 0x1C,\n  0x03, 0xE0, 0x78, 0x1F, 0x03, 0xC0, 0x38, 0x00, 0x00, 0x00, 0x0F, 0x87,\n  0xF9, 0xC3, 0xB0, 0x3C, 0x06, 0x00, 0xC0, 0x30, 0x0C, 0x03, 0x01, 0xC0,\n  0x30, 0x0C, 0x01, 0x80, 0x00, 0x00, 0x00, 0x00, 0x30, 0x06, 0x00, 0x00,\n  0x3F, 0x80, 0x01, 0xFF, 0xE0, 0x0F, 0x01, 0xE0, 0x38, 0x00, 0xE0, 0xE0,\n  0x00, 0xC3, 0x87, 0x81, 0xCE, 0x1F, 0xB1, 0x98, 0x71, 0xC3, 0x61, 0x83,\n  0x86, 0xC6, 0x06, 0x0F, 0x0C, 0x0C, 0x3E, 0x30, 0x30, 0x6C, 0x60, 0x61,\n  0xD8, 0xC1, 0x87, 0x31, 0xC7, 0x1C, 0x61, 0xF7, 0xF0, 0x63, 0xCF, 0x80,\n  0xE0, 0x00, 0x00, 0xF0, 0x00, 0x00, 0xFF, 0xE0, 0x00, 0x7F, 0x00, 0x00,\n  0x00, 0x38, 0x00, 0x78, 0x00, 0x7C, 0x00, 0xFC, 0x00, 0xDC, 0x01, 0xCC,\n  0x01, 0x8C, 0x03, 0x8C, 0x03, 0x0C, 0x06, 0x0C, 0x0E, 0x0E, 0x0F, 0xFE,\n  0x1F, 0xFE, 0x18, 0x06, 0x38, 0x06, 0x30, 0x06, 0x70, 0x06, 0x60, 0x07,\n  0x0F, 0xF8, 0x1F, 0xF8, 0x60, 0x38, 0xC0, 0x31, 0x80, 0x63, 0x00, 0xCE,\n  0x03, 0x18, 0x0C, 0x3F, 0xF0, 0x7F, 0xF0, 0xC0, 0x73, 0x00, 0x66, 0x00,\n  0xCC, 0x01, 0x98, 0x06, 0x70, 0x1C, 0xFF, 0xF1, 0xFF, 0x80, 0x01, 0xF8,\n  0x07, 0xFE, 0x0E, 0x0E, 0x1C, 0x03, 0x38, 0x03, 0x30, 0x00, 0x60, 0x00,\n  0x60, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x06,\n  0xC0, 0x0C, 0xE0, 0x1C, 0x70, 0x78, 0x3F, 0xF0, 0x1F, 0x80, 0x0F, 0xF8,\n  0x1F, 0xFC, 0x18, 0x0E, 0x18, 0x07, 0x18, 0x03, 0x18, 0x03, 0x38, 0x03,\n  0x30, 0x03, 0x30, 0x03, 0x30, 0x03, 0x70, 0x06, 0x70, 0x06, 0x60, 0x0C,\n  0x60, 0x0C, 0x60, 0x18, 0xE0, 0x78, 0xFF, 0xE0, 0xFF, 0x80, 0x0F, 0xFF,\n  0x1F, 0xFE, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0x38, 0x00,\n  0x30, 0x00, 0x3F, 0xFC, 0x3F, 0xF8, 0x70, 0x00, 0x70, 0x00, 0x60, 0x00,\n  0x60, 0x00, 0x60, 0x00, 0xE0, 0x00, 0xFF, 0xF8, 0xFF, 0xF8, 0x0F, 0xFE,\n  0x3F, 0xFC, 0x60, 0x00, 0xC0, 0x01, 0x80, 0x03, 0x00, 0x0E, 0x00, 0x18,\n  0x00, 0x3F, 0xF0, 0x7F, 0xE1, 0xC0, 0x03, 0x80, 0x06, 0x00, 0x0C, 0x00,\n  0x18, 0x00, 0x70, 0x00, 0xC0, 0x01, 0x80, 0x00, 0x01, 0xF8, 0x07, 0xFE,\n  0x0E, 0x0F, 0x18, 0x03, 0x30, 0x03, 0x70, 0x00, 0x60, 0x00, 0x60, 0x00,\n  0xC0, 0x7F, 0xC0, 0x7E, 0xC0, 0x02, 0xC0, 0x06, 0xC0, 0x06, 0xE0, 0x0E,\n  0x60, 0x1E, 0x78, 0x3C, 0x3F, 0xE4, 0x0F, 0x84, 0x0C, 0x01, 0x8E, 0x00,\n  0xC6, 0x00, 0xE3, 0x00, 0x61, 0x80, 0x30, 0xC0, 0x18, 0xE0, 0x0C, 0x60,\n  0x0E, 0x3F, 0xFE, 0x1F, 0xFF, 0x1C, 0x01, 0x8E, 0x01, 0xC6, 0x00, 0xE3,\n  0x00, 0x61, 0x80, 0x31, 0xC0, 0x18, 0xC0, 0x1C, 0x60, 0x0C, 0x00, 0x0C,\n  0x71, 0x86, 0x18, 0x63, 0x8C, 0x30, 0xC3, 0x1C, 0x61, 0x86, 0x18, 0xE3,\n  0x00, 0x00, 0x18, 0x01, 0x80, 0x0C, 0x00, 0x60, 0x03, 0x00, 0x38, 0x01,\n  0x80, 0x0C, 0x00, 0x60, 0x03, 0x00, 0x38, 0x01, 0x8C, 0x0C, 0x60, 0x63,\n  0x07, 0x1C, 0x70, 0x7F, 0x01, 0xF0, 0x00, 0x0C, 0x03, 0x87, 0x01, 0xC1,\n  0x80, 0xE0, 0x60, 0x60, 0x18, 0x70, 0x06, 0x38, 0x03, 0x9C, 0x00, 0xCE,\n  0x00, 0x37, 0x80, 0x0F, 0x70, 0x07, 0x8C, 0x01, 0xC3, 0x80, 0x60, 0x60,\n  0x18, 0x1C, 0x06, 0x03, 0x03, 0x80, 0xE0, 0xC0, 0x18, 0x30, 0x07, 0x00,\n  0x0C, 0x03, 0x80, 0x60, 0x0C, 0x01, 0x80, 0x30, 0x0E, 0x01, 0x80, 0x30,\n  0x06, 0x01, 0xC0, 0x38, 0x06, 0x00, 0xC0, 0x18, 0x07, 0x00, 0xFF, 0xFF,\n  0xFC, 0x0E, 0x00, 0x71, 0xE0, 0x0F, 0x1E, 0x00, 0xF1, 0xE0, 0x1E, 0x1E,\n  0x01, 0xE1, 0xE0, 0x36, 0x3B, 0x03, 0x63, 0x30, 0x6E, 0x33, 0x0E, 0xC3,\n  0x30, 0xCC, 0x33, 0x18, 0xC6, 0x31, 0x8C, 0x63, 0x31, 0xC6, 0x33, 0x18,\n  0x61, 0xE1, 0x8E, 0x1E, 0x18, 0xC1, 0xC1, 0x8C, 0x1C, 0x38, 0x0C, 0x01,\n  0x8F, 0x00, 0xC7, 0x80, 0x63, 0xE0, 0x71, 0xF0, 0x30, 0xD8, 0x18, 0xEE,\n  0x0C, 0x63, 0x06, 0x31, 0xC7, 0x18, 0xE3, 0x0C, 0x31, 0x8C, 0x1C, 0xC6,\n  0x06, 0x63, 0x03, 0xF1, 0x80, 0xF1, 0xC0, 0x78, 0xC0, 0x3C, 0x60, 0x0E,\n  0x00, 0x01, 0xF8, 0x03, 0xFF, 0x03, 0x83, 0xC3, 0x80, 0x63, 0x00, 0x3B,\n  0x80, 0x0D, 0x80, 0x06, 0xC0, 0x03, 0xC0, 0x01, 0xE0, 0x00, 0xF0, 0x00,\n  0xF8, 0x00, 0x6C, 0x00, 0x36, 0x00, 0x31, 0x80, 0x30, 0xF0, 0x78, 0x3F,\n  0xF0, 0x07, 0xE0, 0x00, 0x0F, 0xF8, 0x3F, 0xF8, 0x60, 0x38, 0xC0, 0x31,\n  0x80, 0x63, 0x00, 0xCE, 0x03, 0x18, 0x0E, 0x3F, 0xF8, 0x7F, 0xE1, 0xC0,\n  0x03, 0x80, 0x06, 0x00, 0x0C, 0x00, 0x18, 0x00, 0x70, 0x00, 0xC0, 0x01,\n  0x80, 0x00, 0x00, 0xFC, 0x01, 0xFF, 0xC0, 0xF0, 0x78, 0x70, 0x06, 0x38,\n  0x01, 0xCC, 0x00, 0x36, 0x00, 0x0D, 0x80, 0x03, 0xC0, 0x00, 0xF0, 0x00,\n  0x3C, 0x00, 0x1B, 0x00, 0x06, 0xC0, 0x03, 0x38, 0x1D, 0xC6, 0x03, 0xE1,\n  0xE0, 0xF0, 0x3F, 0xFE, 0x03, 0xF1, 0xC0, 0x00, 0x20, 0x0F, 0xFC, 0x1F,\n  0xFE, 0x18, 0x07, 0x18, 0x03, 0x18, 0x03, 0x18, 0x03, 0x38, 0x06, 0x30,\n  0x0C, 0x3F, 0xF8, 0x3F, 0xF8, 0x70, 0x1C, 0x70, 0x0C, 0x60, 0x0C, 0x60,\n  0x0C, 0x60, 0x18, 0xE0, 0x18, 0xC0, 0x18, 0xC0, 0x1C, 0x03, 0xF8, 0x1F,\n  0xF8, 0x70, 0x38, 0xC0, 0x33, 0x00, 0x66, 0x00, 0x0C, 0x00, 0x1E, 0x00,\n  0x1F, 0xC0, 0x0F, 0xF0, 0x01, 0xF0, 0x00, 0xEC, 0x00, 0xD8, 0x01, 0xB0,\n  0x06, 0x70, 0x38, 0x7F, 0xE0, 0x3F, 0x00, 0xFF, 0xFF, 0xFF, 0xF0, 0x70,\n  0x01, 0xC0, 0x06, 0x00, 0x18, 0x00, 0x60, 0x03, 0x80, 0x0C, 0x00, 0x30,\n  0x00, 0xC0, 0x03, 0x00, 0x1C, 0x00, 0x60, 0x01, 0x80, 0x06, 0x00, 0x18,\n  0x00, 0xE0, 0x00, 0x18, 0x03, 0x38, 0x03, 0x30, 0x07, 0x30, 0x06, 0x30,\n  0x06, 0x70, 0x06, 0x70, 0x0E, 0x60, 0x0C, 0x60, 0x0C, 0x60, 0x0C, 0xE0,\n  0x0C, 0xC0, 0x1C, 0xC0, 0x18, 0xC0, 0x18, 0xC0, 0x38, 0xE0, 0x70, 0x7F,\n  0xE0, 0x1F, 0x80, 0xC0, 0x0F, 0xC0, 0x1B, 0x80, 0x73, 0x00, 0xC6, 0x03,\n  0x0C, 0x06, 0x18, 0x18, 0x30, 0x70, 0x60, 0xC0, 0xE3, 0x81, 0xC6, 0x01,\n  0x9C, 0x03, 0x30, 0x06, 0xE0, 0x0D, 0x80, 0x1E, 0x00, 0x3C, 0x00, 0x70,\n  0x00, 0xC0, 0x70, 0x1F, 0x01, 0xC0, 0x6C, 0x0F, 0x03, 0xB0, 0x3C, 0x0C,\n  0xC1, 0xF0, 0x73, 0x06, 0xC1, 0x8C, 0x3B, 0x06, 0x30, 0xC6, 0x30, 0xC7,\n  0x18, 0xC3, 0x18, 0x67, 0x0C, 0xE1, 0x98, 0x33, 0x06, 0xE0, 0xDC, 0x1B,\n  0x03, 0x60, 0x6C, 0x07, 0x81, 0xE0, 0x1C, 0x07, 0x80, 0x70, 0x1C, 0x01,\n  0x80, 0x70, 0x00, 0x07, 0x00, 0xE0, 0xE0, 0x38, 0x0C, 0x0E, 0x01, 0xC3,\n  0x80, 0x18, 0xE0, 0x03, 0x98, 0x00, 0x36, 0x00, 0x07, 0x80, 0x00, 0xF0,\n  0x00, 0x1E, 0x00, 0x07, 0xC0, 0x01, 0xDC, 0x00, 0x73, 0x80, 0x1C, 0x30,\n  0x03, 0x07, 0x00, 0xC0, 0x60, 0x38, 0x0E, 0x0E, 0x00, 0xC0, 0xE0, 0x06,\n  0x60, 0x0C, 0x70, 0x1C, 0x70, 0x38, 0x30, 0x70, 0x38, 0x60, 0x18, 0xC0,\n  0x1D, 0xC0, 0x1F, 0x80, 0x0F, 0x00, 0x0E, 0x00, 0x0E, 0x00, 0x0E, 0x00,\n  0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x1C, 0x00, 0x18, 0x00, 0x0F, 0xFF,\n  0x87, 0xFF, 0x80, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01,\n  0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x01,\n  0xC0, 0x01, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xFF, 0xF8, 0x7F, 0xFC,\n  0x00, 0x07, 0xC1, 0xE0, 0x60, 0x18, 0x0C, 0x03, 0x00, 0xC0, 0x30, 0x1C,\n  0x06, 0x01, 0x80, 0x60, 0x18, 0x0E, 0x03, 0x00, 0xC0, 0x30, 0x0C, 0x06,\n  0x01, 0x80, 0x60, 0x1E, 0x07, 0x80, 0x93, 0x6C, 0x92, 0x49, 0x24, 0xDB,\n  0x24, 0x07, 0x81, 0xE0, 0x18, 0x06, 0x01, 0x80, 0xC0, 0x30, 0x0C, 0x03,\n  0x01, 0xC0, 0x60, 0x18, 0x06, 0x01, 0x80, 0xE0, 0x30, 0x0C, 0x03, 0x00,\n  0xC0, 0x60, 0x18, 0x1E, 0x0F, 0x80, 0x03, 0x01, 0xC0, 0xD8, 0x36, 0x19,\n  0x84, 0x63, 0x19, 0x83, 0x60, 0xC0, 0xFF, 0xFC, 0xE6, 0x23, 0x07, 0xC3,\n  0xFC, 0xE3, 0x98, 0x30, 0x06, 0x01, 0x87, 0xF3, 0xC6, 0xC0, 0xD8, 0x3B,\n  0x0E, 0x7F, 0x77, 0xCC, 0x0C, 0x00, 0x60, 0x03, 0x00, 0x30, 0x01, 0x80,\n  0x0C, 0xF0, 0x7F, 0xC3, 0x87, 0x38, 0x19, 0x80, 0xCC, 0x06, 0x60, 0x32,\n  0x03, 0xB0, 0x19, 0xC1, 0xCE, 0x1C, 0x7F, 0xC3, 0x7C, 0x00, 0x0F, 0x83,\n  0xF8, 0xE3, 0xB8, 0x36, 0x07, 0xC0, 0x30, 0x06, 0x00, 0xC0, 0x18, 0x1B,\n  0x86, 0x3F, 0xC3, 0xE0, 0x00, 0x0C, 0x00, 0x60, 0x01, 0x80, 0x06, 0x00,\n  0x18, 0x3E, 0x61, 0xFF, 0x0E, 0x3C, 0x70, 0x71, 0x80, 0xCE, 0x07, 0x30,\n  0x18, 0xC0, 0x63, 0x01, 0x8C, 0x0E, 0x38, 0x78, 0x7F, 0xC0, 0xFB, 0x00,\n  0x07, 0xC1, 0xFE, 0x38, 0x77, 0x03, 0x60, 0x37, 0xFF, 0xFF, 0xFC, 0x00,\n  0xC0, 0x0C, 0x06, 0xE1, 0xC7, 0xF8, 0x3E, 0x00, 0x07, 0x0F, 0x1C, 0x18,\n  0x18, 0x7E, 0x7E, 0x30, 0x30, 0x30, 0x30, 0x60, 0x60, 0x60, 0x60, 0x60,\n  0xC0, 0xC0, 0x03, 0xCC, 0x3F, 0xA1, 0xC7, 0x8E, 0x0E, 0x30, 0x38, 0xC0,\n  0xC6, 0x03, 0x18, 0x0C, 0x60, 0x71, 0x81, 0xC7, 0x0E, 0x0F, 0xF8, 0x1E,\n  0x60, 0x03, 0x80, 0x0C, 0x30, 0x70, 0x7F, 0x80, 0xF8, 0x00, 0x0C, 0x00,\n  0xC0, 0x0C, 0x01, 0x80, 0x18, 0x01, 0x9E, 0x1F, 0xF1, 0xC7, 0x38, 0x33,\n  0x03, 0x30, 0x33, 0x07, 0x30, 0x66, 0x06, 0x60, 0x66, 0x06, 0x60, 0xC6,\n  0x0C, 0x18, 0xC0, 0x00, 0x18, 0xC6, 0x33, 0x18, 0xC6, 0x31, 0x98, 0xC6,\n  0x00, 0x01, 0x80, 0xC0, 0x00, 0x00, 0x00, 0x18, 0x1C, 0x0C, 0x06, 0x03,\n  0x01, 0x81, 0x80, 0xC0, 0x60, 0x30, 0x18, 0x18, 0x0C, 0x06, 0x03, 0x03,\n  0x87, 0x83, 0x80, 0x0C, 0x00, 0x60, 0x03, 0x00, 0x30, 0x01, 0x80, 0x0C,\n  0x18, 0x61, 0x83, 0x38, 0x33, 0x81, 0xB8, 0x0F, 0xC0, 0x77, 0x03, 0x18,\n  0x30, 0xC1, 0x87, 0x0C, 0x18, 0x60, 0xE3, 0x03, 0x00, 0x18, 0xC6, 0x63,\n  0x18, 0xC6, 0x33, 0x18, 0xC6, 0x31, 0x98, 0xC6, 0x00, 0x1B, 0xE3, 0xC3,\n  0xFD, 0xFC, 0xF1, 0xE1, 0x9C, 0x18, 0x33, 0x03, 0x06, 0x60, 0xC0, 0xCC,\n  0x18, 0x3B, 0x83, 0x06, 0x60, 0x60, 0xCC, 0x0C, 0x19, 0x83, 0x03, 0x30,\n  0x60, 0xE6, 0x0C, 0x18, 0x1B, 0xE1, 0xFF, 0x3C, 0x73, 0x83, 0x30, 0x33,\n  0x03, 0x30, 0x77, 0x06, 0x60, 0x66, 0x06, 0x60, 0x66, 0x0C, 0x60, 0xC0,\n  0x07, 0xC1, 0xFE, 0x38, 0x77, 0x03, 0x60, 0x3E, 0x03, 0xC0, 0x3C, 0x06,\n  0xC0, 0x6C, 0x0E, 0xE1, 0xC7, 0xF8, 0x3E, 0x00, 0x0C, 0xF0, 0x3F, 0xE0,\n  0xE1, 0xC7, 0x03, 0x1C, 0x0C, 0x60, 0x31, 0x80, 0xCE, 0x07, 0x38, 0x18,\n  0xE0, 0xE3, 0xC7, 0x0F, 0xF8, 0x77, 0xC1, 0x80, 0x06, 0x00, 0x18, 0x00,\n  0x60, 0x03, 0x80, 0x00, 0x0F, 0x98, 0xFF, 0xCE, 0x3C, 0xE0, 0xE6, 0x03,\n  0x70, 0x1B, 0x01, 0x98, 0x0C, 0xC0, 0x66, 0x07, 0x38, 0x78, 0xFF, 0x83,\n  0xCC, 0x00, 0x60, 0x07, 0x00, 0x38, 0x01, 0x80, 0x0C, 0x00, 0x1B, 0x8F,\n  0xCF, 0x07, 0x03, 0x01, 0x80, 0xC0, 0xE0, 0x60, 0x30, 0x18, 0x0C, 0x06,\n  0x00, 0x0F, 0xC1, 0xFF, 0x30, 0x76, 0x03, 0x60, 0x07, 0x80, 0x3F, 0x80,\n  0x7E, 0x00, 0x6C, 0x06, 0xE0, 0xCF, 0xF8, 0x3E, 0x00, 0x18, 0x30, 0x67,\n  0xEF, 0xC6, 0x0C, 0x30, 0x60, 0xC1, 0x83, 0x0C, 0x18, 0x3C, 0x38, 0x30,\n  0x33, 0x03, 0x30, 0x37, 0x06, 0x60, 0x66, 0x06, 0x60, 0x66, 0x06, 0xC0,\n  0xEC, 0x0C, 0xC3, 0xCF, 0xFC, 0x7C, 0xC0, 0xC0, 0x78, 0x1B, 0x03, 0x60,\n  0xC6, 0x18, 0xC6, 0x19, 0xC3, 0x30, 0x6C, 0x0D, 0x81, 0xE0, 0x3C, 0x03,\n  0x00, 0xC1, 0xC3, 0xE1, 0xE1, 0xB0, 0xF0, 0xD8, 0x78, 0xCC, 0x6C, 0x66,\n  0x36, 0x63, 0x33, 0x30, 0x99, 0xB0, 0x58, 0xD8, 0x2C, 0x78, 0x1C, 0x3C,\n  0x0E, 0x1C, 0x06, 0x0E, 0x00, 0x0C, 0x1C, 0x30, 0xE0, 0xE3, 0x01, 0x98,\n  0x07, 0xC0, 0x0E, 0x00, 0x30, 0x01, 0xE0, 0x0F, 0x80, 0x73, 0x01, 0x8C,\n  0x0C, 0x38, 0x60, 0x60, 0x18, 0x0C, 0x60, 0x61, 0x83, 0x86, 0x0C, 0x1C,\n  0x60, 0x31, 0x80, 0xCC, 0x03, 0x30, 0x0D, 0x80, 0x36, 0x00, 0xF0, 0x03,\n  0x80, 0x06, 0x00, 0x30, 0x00, 0xC0, 0x06, 0x00, 0xF0, 0x03, 0x80, 0x00,\n  0x1F, 0xF1, 0xFF, 0x00, 0x70, 0x0C, 0x01, 0x80, 0x30, 0x06, 0x00, 0xC0,\n  0x18, 0x03, 0x00, 0x60, 0x0F, 0xFC, 0xFF, 0xC0, 0x07, 0x0E, 0x18, 0x18,\n  0x18, 0x18, 0x30, 0x30, 0x30, 0x30, 0x60, 0xE0, 0xE0, 0x60, 0x60, 0x60,\n  0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xF0, 0x60, 0x0C, 0x30, 0x82, 0x08, 0x61,\n  0x84, 0x10, 0x43, 0x0C, 0x20, 0x86, 0x18, 0x41, 0x04, 0x30, 0xC2, 0x00,\n  0x00, 0x06, 0x07, 0x80, 0xC0, 0x60, 0x30, 0x18, 0x0C, 0x0C, 0x06, 0x03,\n  0x01, 0xC0, 0xE0, 0x60, 0x60, 0x30, 0x18, 0x0C, 0x0C, 0x06, 0x03, 0x01,\n  0x83, 0x83, 0x80, 0x38, 0x0F, 0x82, 0x38, 0x83, 0xE0, 0x38 };\n\nconst GFXglyph FreeSansOblique12pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,   7,    0,    1 },   // 0x20 ' '\n  {     0,   6,  18,   7,    3,  -17 },   // 0x21 '!'\n  {    14,   6,   6,   9,    4,  -16 },   // 0x22 '\"'\n  {    19,  15,  18,  13,    1,  -17 },   // 0x23 '#'\n  {    53,  13,  21,  13,    2,  -17 },   // 0x24 '$'\n  {    88,  19,  17,  21,    3,  -16 },   // 0x25 '%'\n  {   129,  13,  17,  16,    2,  -16 },   // 0x26 '&'\n  {   157,   2,   6,   5,    4,  -16 },   // 0x27 '''\n  {   159,   8,  23,   8,    3,  -17 },   // 0x28 '('\n  {   182,   8,  23,   8,    0,  -16 },   // 0x29 ')'\n  {   205,   8,   8,   9,    4,  -17 },   // 0x2A '*'\n  {   213,  12,  11,  14,    2,  -10 },   // 0x2B '+'\n  {   230,   4,   6,   7,    1,   -1 },   // 0x2C ','\n  {   233,   6,   2,   8,    2,   -7 },   // 0x2D '-'\n  {   235,   3,   2,   7,    2,   -1 },   // 0x2E '.'\n  {   236,  10,  18,   7,    0,  -17 },   // 0x2F '/'\n  {   259,  12,  17,  13,    2,  -16 },   // 0x30 '0'\n  {   285,   7,  17,  13,    5,  -16 },   // 0x31 '1'\n  {   300,  14,  17,  13,    1,  -16 },   // 0x32 '2'\n  {   330,  12,  17,  13,    2,  -16 },   // 0x33 '3'\n  {   356,  12,  17,  13,    2,  -16 },   // 0x34 '4'\n  {   382,  13,  17,  13,    2,  -16 },   // 0x35 '5'\n  {   410,  12,  17,  13,    2,  -16 },   // 0x36 '6'\n  {   436,  13,  17,  13,    3,  -16 },   // 0x37 '7'\n  {   464,  12,  17,  13,    2,  -16 },   // 0x38 '8'\n  {   490,  12,  17,  13,    2,  -16 },   // 0x39 '9'\n  {   516,   5,  12,   7,    3,  -11 },   // 0x3A ':'\n  {   524,   6,  16,   7,    2,  -11 },   // 0x3B ';'\n  {   536,  13,  12,  14,    2,  -11 },   // 0x3C '<'\n  {   556,  13,   6,  14,    2,   -8 },   // 0x3D '='\n  {   566,  13,  12,  14,    1,  -10 },   // 0x3E '>'\n  {   586,  11,  18,  13,    4,  -17 },   // 0x3F '?'\n  {   611,  23,  21,  24,    2,  -17 },   // 0x40 '@'\n  {   672,  16,  18,  16,    0,  -17 },   // 0x41 'A'\n  {   708,  15,  18,  16,    2,  -17 },   // 0x42 'B'\n  {   742,  16,  18,  17,    2,  -17 },   // 0x43 'C'\n  {   778,  16,  18,  17,    2,  -17 },   // 0x44 'D'\n  {   814,  16,  18,  16,    2,  -17 },   // 0x45 'E'\n  {   850,  15,  18,  14,    2,  -17 },   // 0x46 'F'\n  {   884,  16,  18,  19,    3,  -17 },   // 0x47 'G'\n  {   920,  17,  18,  17,    2,  -17 },   // 0x48 'H'\n  {   959,   6,  18,   7,    2,  -17 },   // 0x49 'I'\n  {   973,  13,  18,  12,    1,  -17 },   // 0x4A 'J'\n  {  1003,  18,  18,  16,    2,  -17 },   // 0x4B 'K'\n  {  1044,  11,  18,  13,    2,  -17 },   // 0x4C 'L'\n  {  1069,  20,  18,  20,    2,  -17 },   // 0x4D 'M'\n  {  1114,  17,  18,  18,    2,  -17 },   // 0x4E 'N'\n  {  1153,  17,  18,  18,    2,  -17 },   // 0x4F 'O'\n  {  1192,  15,  18,  15,    2,  -17 },   // 0x50 'P'\n  {  1226,  18,  19,  19,    2,  -17 },   // 0x51 'Q'\n  {  1269,  16,  18,  17,    2,  -17 },   // 0x52 'R'\n  {  1305,  15,  18,  16,    2,  -17 },   // 0x53 'S'\n  {  1339,  14,  18,  15,    4,  -17 },   // 0x54 'T'\n  {  1371,  16,  18,  17,    3,  -17 },   // 0x55 'U'\n  {  1407,  15,  18,  15,    4,  -17 },   // 0x56 'V'\n  {  1441,  22,  18,  22,    4,  -17 },   // 0x57 'W'\n  {  1491,  19,  18,  16,    0,  -17 },   // 0x58 'X'\n  {  1534,  16,  18,  16,    4,  -17 },   // 0x59 'Y'\n  {  1570,  17,  18,  15,    1,  -17 },   // 0x5A 'Z'\n  {  1609,  10,  23,   7,    0,  -17 },   // 0x5B '['\n  {  1638,   3,  18,   7,    4,  -17 },   // 0x5C '\\'\n  {  1645,  10,  23,   7,   -1,  -16 },   // 0x5D ']'\n  {  1674,  10,   9,  11,    2,  -16 },   // 0x5E '^'\n  {  1686,  14,   1,  13,   -1,    4 },   // 0x5F '_'\n  {  1688,   4,   4,   8,    4,  -17 },   // 0x60 '`'\n  {  1690,  11,  13,  13,    2,  -12 },   // 0x61 'a'\n  {  1708,  13,  18,  13,    1,  -17 },   // 0x62 'b'\n  {  1738,  11,  13,  12,    2,  -12 },   // 0x63 'c'\n  {  1756,  14,  18,  13,    2,  -17 },   // 0x64 'd'\n  {  1788,  12,  13,  13,    2,  -12 },   // 0x65 'e'\n  {  1808,   8,  18,   6,    2,  -17 },   // 0x66 'f'\n  {  1826,  14,  18,  13,    1,  -12 },   // 0x67 'g'\n  {  1858,  12,  18,  13,    1,  -17 },   // 0x68 'h'\n  {  1885,   5,  18,   5,    2,  -17 },   // 0x69 'i'\n  {  1897,   9,  23,   6,   -1,  -17 },   // 0x6A 'j'\n  {  1923,  13,  18,  12,    1,  -17 },   // 0x6B 'k'\n  {  1953,   5,  18,   5,    2,  -17 },   // 0x6C 'l'\n  {  1965,  19,  13,  20,    1,  -12 },   // 0x6D 'm'\n  {  1996,  12,  13,  13,    1,  -12 },   // 0x6E 'n'\n  {  2016,  12,  13,  13,    2,  -12 },   // 0x6F 'o'\n  {  2036,  14,  18,  14,    0,  -12 },   // 0x70 'p'\n  {  2068,  13,  18,  13,    2,  -12 },   // 0x71 'q'\n  {  2098,   9,  13,   8,    1,  -12 },   // 0x72 'r'\n  {  2113,  12,  13,  12,    1,  -12 },   // 0x73 's'\n  {  2133,   7,  16,   6,    2,  -15 },   // 0x74 't'\n  {  2147,  12,  13,  13,    2,  -12 },   // 0x75 'u'\n  {  2167,  11,  13,  12,    3,  -12 },   // 0x76 'v'\n  {  2185,  17,  13,  17,    3,  -12 },   // 0x77 'w'\n  {  2213,  14,  13,  12,    0,  -12 },   // 0x78 'x'\n  {  2236,  14,  18,  11,    0,  -12 },   // 0x79 'y'\n  {  2268,  12,  13,  12,    1,  -12 },   // 0x7A 'z'\n  {  2288,   8,  23,   8,    3,  -17 },   // 0x7B '{'\n  {  2311,   6,  23,   6,    1,  -17 },   // 0x7C '|'\n  {  2329,   9,  23,   8,   -1,  -16 },   // 0x7D '}'\n  {  2355,  11,   5,  14,    3,  -10 } }; // 0x7E '~'\n\nconst GFXfont FreeSansOblique12pt7b PROGMEM = {\n  (uint8_t  *)FreeSansOblique12pt7bBitmaps,\n  (GFXglyph *)FreeSansOblique12pt7bGlyphs,\n  0x20, 0x7E, 29 };\n\n// Approx. 3034 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeSansOblique18pt7b.h",
    "content": "const uint8_t FreeSansOblique18pt7bBitmaps[] PROGMEM = {\n  0x03, 0x83, 0x81, 0xC0, 0xE0, 0x70, 0x78, 0x38, 0x1C, 0x0E, 0x07, 0x07,\n  0x83, 0x81, 0xC0, 0xE0, 0x60, 0x30, 0x30, 0x18, 0x0C, 0x04, 0x00, 0x00,\n  0x01, 0xC0, 0xE0, 0x70, 0x78, 0x00, 0x71, 0xDC, 0x7F, 0x3F, 0x8E, 0xE3,\n  0xB8, 0xEC, 0x33, 0x0C, 0xC3, 0x00, 0x00, 0x38, 0x70, 0x01, 0xC3, 0x80,\n  0x0C, 0x18, 0x00, 0xE1, 0xC0, 0x06, 0x0C, 0x00, 0x70, 0xE0, 0x03, 0x87,\n  0x03, 0xFF, 0xFF, 0x1F, 0xFF, 0xF0, 0xFF, 0xFF, 0x80, 0x60, 0xC0, 0x07,\n  0x0E, 0x00, 0x30, 0x60, 0x03, 0x87, 0x00, 0x18, 0x30, 0x1F, 0xFF, 0xF8,\n  0xFF, 0xFF, 0xC7, 0xFF, 0xFC, 0x07, 0x0E, 0x00, 0x30, 0x70, 0x03, 0x87,\n  0x00, 0x1C, 0x38, 0x00, 0xC1, 0x80, 0x0E, 0x1C, 0x00, 0x60, 0xC0, 0x00,\n  0x00, 0x0C, 0x00, 0x07, 0xF8, 0x01, 0xFF, 0xC0, 0x3F, 0xFE, 0x07, 0x99,\n  0xF0, 0xF1, 0x87, 0x0E, 0x18, 0x71, 0xC1, 0x87, 0x1C, 0x38, 0x01, 0xC3,\n  0x00, 0x1C, 0x30, 0x01, 0xE3, 0x00, 0x0F, 0xB0, 0x00, 0xFF, 0x80, 0x03,\n  0xFF, 0x00, 0x0F, 0xF8, 0x00, 0x6F, 0xC0, 0x06, 0x3C, 0x00, 0xC1, 0xCE,\n  0x0C, 0x1C, 0xE0, 0xC1, 0xCE, 0x0C, 0x38, 0xF1, 0xC3, 0x8F, 0x98, 0xF0,\n  0x7F, 0xFE, 0x03, 0xFF, 0xC0, 0x0F, 0xF0, 0x00, 0x30, 0x00, 0x03, 0x00,\n  0x00, 0x30, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x07, 0x03, 0xE0, 0x03,\n  0x81, 0xFC, 0x00, 0xC0, 0xFF, 0x00, 0x60, 0x70, 0xE0, 0x38, 0x38, 0x18,\n  0x1C, 0x0C, 0x06, 0x0E, 0x03, 0x01, 0x83, 0x00, 0xC0, 0xE1, 0x80, 0x38,\n  0x70, 0xE0, 0x0F, 0xF8, 0x70, 0x01, 0xFC, 0x18, 0x00, 0x3E, 0x0C, 0x00,\n  0x00, 0x06, 0x07, 0x80, 0x03, 0x87, 0xF8, 0x00, 0xC3, 0xFE, 0x00, 0x61,\n  0xE1, 0xC0, 0x30, 0x60, 0x30, 0x1C, 0x30, 0x0C, 0x0E, 0x0C, 0x03, 0x03,\n  0x03, 0x01, 0x81, 0x80, 0xE1, 0xE0, 0xC0, 0x1F, 0xF0, 0x70, 0x07, 0xF8,\n  0x18, 0x00, 0xF8, 0x00, 0x00, 0x1F, 0x00, 0x07, 0xF8, 0x00, 0xFF, 0xC0,\n  0x1E, 0x3C, 0x03, 0xC1, 0xC0, 0x38, 0x1C, 0x03, 0x81, 0xC0, 0x38, 0x38,\n  0x03, 0xC7, 0x00, 0x1D, 0xE0, 0x01, 0xFC, 0x00, 0x1F, 0x00, 0x07, 0xF0,\n  0x01, 0xF7, 0x87, 0x3C, 0x3C, 0xE7, 0x81, 0xCE, 0x70, 0x1F, 0xCE, 0x00,\n  0xFC, 0xE0, 0x07, 0x8E, 0x00, 0x78, 0xF0, 0x1F, 0x8F, 0x87, 0xFC, 0x7F,\n  0xF9, 0xC3, 0xFE, 0x1E, 0x1F, 0x80, 0xE0, 0x77, 0xFE, 0xEE, 0xCC, 0xC0,\n  0x00, 0x30, 0x06, 0x00, 0xC0, 0x18, 0x03, 0x80, 0x30, 0x06, 0x00, 0xE0,\n  0x0C, 0x01, 0xC0, 0x18, 0x03, 0x80, 0x38, 0x07, 0x00, 0x70, 0x07, 0x00,\n  0x70, 0x0E, 0x00, 0xE0, 0x0E, 0x00, 0xE0, 0x0E, 0x00, 0xE0, 0x0E, 0x00,\n  0xE0, 0x0E, 0x00, 0xE0, 0x06, 0x00, 0x70, 0x07, 0x00, 0x30, 0x03, 0x00,\n  0x18, 0x00, 0x01, 0x80, 0x0C, 0x00, 0xC0, 0x0E, 0x00, 0xE0, 0x06, 0x00,\n  0x70, 0x07, 0x00, 0x70, 0x07, 0x00, 0x70, 0x07, 0x00, 0x70, 0x07, 0x00,\n  0x70, 0x07, 0x00, 0xE0, 0x0E, 0x00, 0xE0, 0x0E, 0x01, 0xC0, 0x1C, 0x03,\n  0x80, 0x38, 0x03, 0x00, 0x70, 0x06, 0x00, 0xC0, 0x1C, 0x01, 0x80, 0x30,\n  0x06, 0x00, 0xC0, 0x00, 0x06, 0x01, 0x84, 0x47, 0xF7, 0xFF, 0xCF, 0xC1,\n  0xE0, 0xD8, 0x67, 0x18, 0xC0, 0x00, 0x70, 0x00, 0x1C, 0x00, 0x0F, 0x00,\n  0x03, 0x80, 0x00, 0xE0, 0x00, 0x38, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xC0, 0x70, 0x00, 0x1C, 0x00, 0x07, 0x00, 0x01, 0xC0, 0x00, 0xE0,\n  0x00, 0x38, 0x00, 0x0E, 0x00, 0x3B, 0xDC, 0x21, 0x18, 0x98, 0xFF, 0xFF,\n  0xFF, 0xE0, 0x7F, 0xFE, 0x00, 0x06, 0x00, 0x18, 0x00, 0x30, 0x00, 0xC0,\n  0x01, 0x80, 0x06, 0x00, 0x0C, 0x00, 0x30, 0x00, 0x60, 0x01, 0x80, 0x03,\n  0x00, 0x0C, 0x00, 0x18, 0x00, 0x60, 0x00, 0xC0, 0x03, 0x00, 0x06, 0x00,\n  0x18, 0x00, 0x20, 0x00, 0xC0, 0x03, 0x00, 0x06, 0x00, 0x18, 0x00, 0x30,\n  0x00, 0xC0, 0x01, 0x80, 0x00, 0x00, 0x7C, 0x00, 0x7F, 0xC0, 0x7F, 0xF8,\n  0x3E, 0x1E, 0x0F, 0x03, 0xC7, 0x80, 0x71, 0xC0, 0x1C, 0xE0, 0x07, 0x38,\n  0x01, 0xDE, 0x00, 0x77, 0x00, 0x1D, 0xC0, 0x0F, 0x70, 0x03, 0xFC, 0x00,\n  0xEE, 0x00, 0x3B, 0x80, 0x0E, 0xE0, 0x07, 0xB8, 0x01, 0xCE, 0x00, 0xF3,\n  0x80, 0x38, 0xF0, 0x1E, 0x1E, 0x1F, 0x07, 0xFF, 0x80, 0xFF, 0xC0, 0x0F,\n  0x80, 0x00, 0x00, 0xC0, 0x70, 0x3C, 0x3E, 0xFF, 0xBF, 0xEF, 0xF8, 0x1E,\n  0x07, 0x01, 0xC0, 0x70, 0x1C, 0x0F, 0x03, 0x80, 0xE0, 0x38, 0x0E, 0x07,\n  0x81, 0xC0, 0x70, 0x1C, 0x07, 0x01, 0xC0, 0xE0, 0x38, 0x00, 0x00, 0x3F,\n  0x00, 0x0F, 0xFC, 0x03, 0xFF, 0xE0, 0x7C, 0x1E, 0x07, 0x80, 0xF0, 0xF0,\n  0x07, 0x0E, 0x00, 0x70, 0xE0, 0x07, 0x00, 0x00, 0x70, 0x00, 0x0E, 0x00,\n  0x01, 0xE0, 0x00, 0x3C, 0x00, 0x0F, 0x80, 0x03, 0xF0, 0x00, 0xFC, 0x00,\n  0x1F, 0x00, 0x07, 0xC0, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x03, 0x80, 0x00,\n  0x70, 0x00, 0x07, 0x00, 0x00, 0xFF, 0xFF, 0x8F, 0xFF, 0xF0, 0xFF, 0xFF,\n  0x00, 0x00, 0x7E, 0x00, 0x3F, 0xF0, 0x0F, 0xFF, 0x03, 0xC1, 0xF0, 0x70,\n  0x0E, 0x1C, 0x01, 0xC3, 0x80, 0x38, 0xE0, 0x07, 0x00, 0x01, 0xC0, 0x00,\n  0xF0, 0x03, 0xFC, 0x00, 0x7F, 0x00, 0x0F, 0xF0, 0x00, 0x1F, 0x00, 0x00,\n  0xE0, 0x00, 0x1C, 0x00, 0x03, 0x9C, 0x00, 0x73, 0x80, 0x1E, 0x70, 0x03,\n  0x8F, 0x00, 0xF1, 0xF0, 0x7C, 0x1F, 0xFF, 0x01, 0xFF, 0xC0, 0x0F, 0xC0,\n  0x00, 0x00, 0x01, 0xC0, 0x00, 0xE0, 0x00, 0x78, 0x00, 0x3E, 0x00, 0x1F,\n  0x80, 0x0F, 0xE0, 0x07, 0xF0, 0x03, 0xDC, 0x01, 0xE7, 0x00, 0x71, 0xC0,\n  0x38, 0xF0, 0x1C, 0x38, 0x0E, 0x0E, 0x07, 0x03, 0x83, 0x80, 0xE1, 0xC0,\n  0x70, 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0x00, 0x70, 0x00, 0x38,\n  0x00, 0x0E, 0x00, 0x03, 0x80, 0x00, 0xE0, 0x00, 0x38, 0x00, 0x01, 0xFF,\n  0xF0, 0x3F, 0xFF, 0x03, 0xFF, 0xE0, 0x78, 0x00, 0x07, 0x00, 0x00, 0x70,\n  0x00, 0x0E, 0x00, 0x00, 0xE0, 0x00, 0x0E, 0xFC, 0x01, 0xFF, 0xF0, 0x1F,\n  0xFF, 0x83, 0xE0, 0x78, 0x3C, 0x03, 0xC0, 0x00, 0x1C, 0x00, 0x01, 0xC0,\n  0x00, 0x1C, 0x00, 0x01, 0xC0, 0x00, 0x18, 0x00, 0x03, 0x8E, 0x00, 0x78,\n  0xE0, 0x0F, 0x0F, 0x81, 0xE0, 0x7F, 0xFC, 0x03, 0xFF, 0x80, 0x0F, 0xE0,\n  0x00, 0x00, 0x7E, 0x00, 0x3F, 0xF0, 0x0F, 0xFF, 0x03, 0xE1, 0xF0, 0xF0,\n  0x0E, 0x1C, 0x01, 0xC7, 0x00, 0x01, 0xE0, 0x00, 0x38, 0x00, 0x07, 0x1F,\n  0x01, 0xCF, 0xF8, 0x3B, 0xFF, 0x87, 0xE0, 0xF8, 0xF0, 0x0F, 0x3C, 0x00,\n  0xE7, 0x80, 0x1C, 0xE0, 0x03, 0x9C, 0x00, 0x73, 0x80, 0x1C, 0x70, 0x03,\n  0x8F, 0x00, 0xE0, 0xF0, 0x78, 0x1F, 0xFF, 0x01, 0xFF, 0x80, 0x0F, 0xC0,\n  0x00, 0x3F, 0xFF, 0xCF, 0xFF, 0xF7, 0xFF, 0xFC, 0x00, 0x0E, 0x00, 0x07,\n  0x00, 0x03, 0x80, 0x00, 0xC0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C, 0x00,\n  0x0E, 0x00, 0x03, 0x80, 0x01, 0xC0, 0x00, 0xE0, 0x00, 0x78, 0x00, 0x1C,\n  0x00, 0x0E, 0x00, 0x03, 0x80, 0x01, 0xC0, 0x00, 0xF0, 0x00, 0x38, 0x00,\n  0x1E, 0x00, 0x07, 0x00, 0x03, 0xC0, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x7E,\n  0x00, 0x3F, 0xF0, 0x1F, 0xFF, 0x07, 0xC1, 0xF0, 0xE0, 0x0E, 0x38, 0x01,\n  0xC7, 0x00, 0x38, 0xE0, 0x0E, 0x1C, 0x01, 0xC3, 0xC0, 0xF0, 0x3F, 0xFC,\n  0x03, 0xFE, 0x01, 0xFF, 0xF0, 0x7C, 0x1E, 0x1E, 0x01, 0xE3, 0x80, 0x1C,\n  0xE0, 0x03, 0x9C, 0x00, 0x73, 0x80, 0x0E, 0x70, 0x03, 0x8F, 0x00, 0xF1,\n  0xF0, 0x7C, 0x1F, 0xFF, 0x01, 0xFF, 0xC0, 0x0F, 0xC0, 0x00, 0x00, 0x7E,\n  0x00, 0x3F, 0xF0, 0x1F, 0xFF, 0x07, 0xC1, 0xE0, 0xE0, 0x1E, 0x38, 0x01,\n  0xC7, 0x00, 0x39, 0xC0, 0x07, 0x38, 0x00, 0xE7, 0x00, 0x3C, 0xE0, 0x07,\n  0x9E, 0x01, 0xE3, 0xE0, 0xFC, 0x3F, 0xFB, 0x83, 0xFE, 0xF0, 0x3F, 0x1C,\n  0x00, 0x03, 0x80, 0x00, 0xF0, 0x00, 0x1C, 0x70, 0x07, 0x8E, 0x01, 0xE1,\n  0xE0, 0xF8, 0x1F, 0xFE, 0x01, 0xFF, 0x80, 0x0F, 0xC0, 0x00, 0x0E, 0x3C,\n  0x78, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,\n  0xF1, 0xE3, 0x80, 0x07, 0x0F, 0x0F, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x78, 0x70, 0x10, 0x10,\n  0x30, 0x20, 0xC0, 0x00, 0x00, 0x20, 0x00, 0x1C, 0x00, 0x1F, 0x80, 0x1F,\n  0xC0, 0x0F, 0xC0, 0x0F, 0xE0, 0x07, 0xE0, 0x03, 0xF0, 0x00, 0xF0, 0x00,\n  0x1F, 0x80, 0x00, 0xFC, 0x00, 0x07, 0xE0, 0x00, 0x3F, 0x00, 0x01, 0xF8,\n  0x00, 0x0F, 0xC0, 0x00, 0x78, 0x00, 0x01, 0x00, 0x7F, 0xFF, 0xDF, 0xFF,\n  0xF7, 0xFF, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0xFF, 0xFB,\n  0xFF, 0xFE, 0xFF, 0xFF, 0x80, 0x10, 0x00, 0x03, 0xC0, 0x00, 0x7E, 0x00,\n  0x03, 0xF0, 0x00, 0x1F, 0x80, 0x00, 0xFC, 0x00, 0x07, 0xE0, 0x00, 0x3F,\n  0x00, 0x01, 0xE0, 0x01, 0xF8, 0x00, 0xFC, 0x00, 0xFE, 0x00, 0x7E, 0x00,\n  0x7F, 0x00, 0x3F, 0x00, 0x07, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, 0xF8,\n  0x0F, 0xFC, 0x1F, 0xFE, 0x3C, 0x1F, 0x78, 0x07, 0x70, 0x07, 0xE0, 0x07,\n  0xE0, 0x07, 0x00, 0x0E, 0x00, 0x1E, 0x00, 0x3C, 0x00, 0x78, 0x00, 0xF0,\n  0x01, 0xC0, 0x03, 0x80, 0x07, 0x00, 0x0F, 0x00, 0x0E, 0x00, 0x0E, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x1C, 0x00, 0x1C, 0x00,\n  0x3C, 0x00, 0x00, 0x00, 0xFF, 0x80, 0x00, 0x03, 0xFF, 0xF0, 0x00, 0x07,\n  0xFF, 0xFE, 0x00, 0x0F, 0xE0, 0x3F, 0x80, 0x0F, 0x80, 0x03, 0xE0, 0x0F,\n  0x00, 0x00, 0xF8, 0x0F, 0x00, 0x00, 0x3C, 0x0F, 0x01, 0xF0, 0x0F, 0x0F,\n  0x03, 0xFD, 0xC7, 0x8F, 0x03, 0xFE, 0xE1, 0xC7, 0x03, 0xC3, 0x60, 0xE7,\n  0x03, 0xC0, 0xF0, 0x77, 0x83, 0xC0, 0x70, 0x3B, 0x83, 0xC0, 0x78, 0x1D,\n  0xC1, 0xC0, 0x38, 0x1F, 0xC1, 0xE0, 0x1C, 0x0E, 0xE0, 0xE0, 0x1C, 0x0F,\n  0x70, 0x70, 0x0E, 0x07, 0x38, 0x38, 0x0E, 0x07, 0x9C, 0x1C, 0x0F, 0x07,\n  0x8E, 0x0F, 0x0F, 0x8F, 0x87, 0x03, 0xFD, 0xFF, 0x83, 0xC1, 0xFC, 0xFF,\n  0x80, 0xE0, 0x7C, 0x3F, 0x00, 0x78, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00,\n  0x00, 0x07, 0x80, 0x00, 0x00, 0x01, 0xF8, 0x07, 0x00, 0x00, 0x7F, 0xFF,\n  0x80, 0x00, 0x1F, 0xFF, 0xC0, 0x00, 0x01, 0xFE, 0x00, 0x00, 0x00, 0x01,\n  0xE0, 0x00, 0x07, 0xC0, 0x00, 0x0F, 0xC0, 0x00, 0x3F, 0x80, 0x00, 0xFF,\n  0x00, 0x01, 0xDE, 0x00, 0x07, 0x9C, 0x00, 0x0E, 0x38, 0x00, 0x3C, 0x70,\n  0x00, 0x70, 0xF0, 0x01, 0xC1, 0xE0, 0x07, 0x83, 0xC0, 0x0E, 0x07, 0x80,\n  0x38, 0x07, 0x00, 0x70, 0x0E, 0x01, 0xFF, 0xFC, 0x03, 0xFF, 0xFC, 0x0F,\n  0xFF, 0xF8, 0x1C, 0x00, 0xF0, 0x70, 0x01, 0xE1, 0xE0, 0x01, 0xC3, 0x80,\n  0x03, 0x8F, 0x00, 0x07, 0x1C, 0x00, 0x0E, 0x78, 0x00, 0x1E, 0xE0, 0x00,\n  0x3C, 0x07, 0xFF, 0xC0, 0x3F, 0xFF, 0x81, 0xFF, 0xFC, 0x0E, 0x00, 0xF0,\n  0xF0, 0x03, 0x87, 0x00, 0x1C, 0x38, 0x00, 0xE1, 0xC0, 0x07, 0x0E, 0x00,\n  0x70, 0xF0, 0x03, 0x87, 0x00, 0x78, 0x3F, 0xFF, 0x81, 0xFF, 0xF8, 0x0F,\n  0xFF, 0xF0, 0xE0, 0x03, 0xC7, 0x00, 0x0E, 0x38, 0x00, 0x71, 0xC0, 0x03,\n  0x9E, 0x00, 0x1C, 0xE0, 0x00, 0xE7, 0x00, 0x0E, 0x38, 0x00, 0xF1, 0xC0,\n  0x0F, 0x1F, 0xFF, 0xF0, 0xFF, 0xFF, 0x07, 0xFF, 0xE0, 0x00, 0x00, 0x1F,\n  0x80, 0x03, 0xFF, 0x80, 0x1F, 0xFF, 0x01, 0xF8, 0x3E, 0x07, 0x80, 0x38,\n  0x38, 0x00, 0xF1, 0xC0, 0x01, 0xCF, 0x00, 0x07, 0x38, 0x00, 0x01, 0xE0,\n  0x00, 0x07, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x70, 0x00, 0x03, 0x80, 0x00,\n  0x0E, 0x00, 0x00, 0x38, 0x00, 0x00, 0xE0, 0x00, 0x7B, 0x80, 0x01, 0xCE,\n  0x00, 0x0F, 0x3C, 0x00, 0x38, 0x70, 0x01, 0xE1, 0xE0, 0x0F, 0x07, 0xC0,\n  0xF8, 0x0F, 0xFF, 0xC0, 0x1F, 0xFC, 0x00, 0x1F, 0xC0, 0x00, 0x07, 0xFF,\n  0xC0, 0x0F, 0xFF, 0xE0, 0x1F, 0xFF, 0xE0, 0x38, 0x03, 0xE0, 0xF0, 0x03,\n  0xC1, 0xC0, 0x03, 0x83, 0x80, 0x03, 0x87, 0x00, 0x07, 0x1E, 0x00, 0x0E,\n  0x3C, 0x00, 0x1C, 0x70, 0x00, 0x38, 0xE0, 0x00, 0x71, 0xC0, 0x00, 0xE7,\n  0x80, 0x03, 0x8F, 0x00, 0x07, 0x1C, 0x00, 0x0E, 0x38, 0x00, 0x3C, 0x70,\n  0x00, 0x71, 0xE0, 0x01, 0xE3, 0x80, 0x03, 0x87, 0x00, 0x0E, 0x0E, 0x00,\n  0x3C, 0x1C, 0x01, 0xF0, 0x7F, 0xFF, 0xC0, 0xFF, 0xFE, 0x01, 0xFF, 0xF0,\n  0x00, 0x07, 0xFF, 0xFE, 0x0F, 0xFF, 0xFC, 0x1F, 0xFF, 0xF0, 0x38, 0x00,\n  0x00, 0xF0, 0x00, 0x01, 0xC0, 0x00, 0x03, 0x80, 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 0x3F, 0xFF, 0x81, 0xDF, 0xF8, 0x0E, 0x3F, 0x00, 0x70, 0x00, 0x03, 0x80,\n  0x00, 0x3C, 0x00, 0x01, 0xC0, 0x00, 0x0E, 0x00, 0x00, 0x70, 0x00, 0x03,\n  0x80, 0x00, 0x00, 0x00, 0xF8, 0xF0, 0x7F, 0xEE, 0x0F, 0xFF, 0xE1, 0xF0,\n  0xFE, 0x3C, 0x07, 0xE3, 0x80, 0x3E, 0x70, 0x03, 0xC7, 0x00, 0x3C, 0x70,\n  0x03, 0xCE, 0x00, 0x3C, 0xE0, 0x07, 0x8E, 0x00, 0x78, 0xE0, 0x07, 0x8E,\n  0x00, 0xF8, 0xF0, 0x1F, 0x87, 0x87, 0xF0, 0x7F, 0xF7, 0x03, 0xFE, 0x70,\n  0x0F, 0x8F, 0x00, 0x00, 0xF0, 0x00, 0x0E, 0x00, 0x00, 0xE0, 0x00, 0x0E,\n  0x00, 0x01, 0xE0, 0x00, 0x1C, 0x00, 0x01, 0xC0, 0x00, 0x04, 0x00, 0x1E,\n  0x78, 0xE7, 0xC7, 0x7C, 0x3F, 0x01, 0xF0, 0x0F, 0x00, 0xF0, 0x07, 0x00,\n  0x38, 0x01, 0xC0, 0x0E, 0x00, 0xF0, 0x07, 0x00, 0x38, 0x01, 0xC0, 0x0E,\n  0x00, 0x70, 0x07, 0x00, 0x38, 0x00, 0x01, 0xF8, 0x07, 0xFE, 0x0F, 0xFF,\n  0x1E, 0x0F, 0x3C, 0x07, 0x38, 0x07, 0x38, 0x00, 0x3C, 0x00, 0x3F, 0x80,\n  0x1F, 0xF8, 0x07, 0xFC, 0x00, 0x7E, 0x00, 0x0E, 0xE0, 0x0E, 0xE0, 0x1E,\n  0xF0, 0x3C, 0x7F, 0xF8, 0x7F, 0xF0, 0x1F, 0xC0, 0x0E, 0x03, 0x80, 0xE0,\n  0x38, 0x7F, 0xDF, 0xEF, 0xF8, 0x70, 0x1C, 0x0E, 0x03, 0x80, 0xE0, 0x38,\n  0x1E, 0x07, 0x01, 0xC0, 0x70, 0x1C, 0x0F, 0x03, 0x80, 0xFC, 0x3F, 0x07,\n  0x80, 0x1C, 0x03, 0xC7, 0x00, 0xE1, 0xC0, 0x38, 0xF0, 0x0E, 0x38, 0x03,\n  0x8E, 0x00, 0xE3, 0x80, 0x70, 0xE0, 0x1C, 0x78, 0x07, 0x1C, 0x01, 0xC7,\n  0x00, 0x71, 0xC0, 0x3C, 0x70, 0x0E, 0x38, 0x07, 0x8E, 0x03, 0xE3, 0x81,\n  0xF8, 0xFF, 0xFE, 0x1F, 0xFF, 0x03, 0xF1, 0xC0, 0xE0, 0x07, 0xE0, 0x0F,\n  0xE0, 0x0E, 0xE0, 0x1C, 0x70, 0x1C, 0x70, 0x38, 0x70, 0x38, 0x70, 0x70,\n  0x70, 0xF0, 0x70, 0xE0, 0x71, 0xC0, 0x71, 0xC0, 0x33, 0x80, 0x3B, 0x80,\n  0x3F, 0x00, 0x3F, 0x00, 0x3E, 0x00, 0x3C, 0x00, 0x3C, 0x00, 0xE0, 0x1C,\n  0x07, 0xE0, 0x3C, 0x0E, 0xE0, 0x3C, 0x0E, 0xE0, 0x7C, 0x1C, 0xE0, 0x7C,\n  0x1C, 0xE0, 0xEC, 0x38, 0xE0, 0xEC, 0x38, 0x61, 0xCC, 0x70, 0x61, 0xCC,\n  0x70, 0x63, 0x8C, 0xE0, 0x73, 0x8C, 0xE0, 0x77, 0x0C, 0xC0, 0x77, 0x0D,\n  0xC0, 0x7E, 0x0D, 0x80, 0x7E, 0x0F, 0x80, 0x7C, 0x0F, 0x80, 0x7C, 0x0F,\n  0x00, 0x78, 0x0F, 0x00, 0x78, 0x0E, 0x00, 0x0E, 0x00, 0xE1, 0xE0, 0x38,\n  0x1C, 0x0E, 0x03, 0xC3, 0x80, 0x38, 0xE0, 0x07, 0xBC, 0x00, 0x77, 0x00,\n  0x0F, 0xC0, 0x00, 0xF0, 0x00, 0x1C, 0x00, 0x07, 0xC0, 0x01, 0xF8, 0x00,\n  0x77, 0x80, 0x1E, 0x70, 0x07, 0x8F, 0x00, 0xE0, 0xE0, 0x38, 0x1C, 0x0E,\n  0x01, 0xC3, 0x80, 0x38, 0x00, 0x0E, 0x00, 0x70, 0xF0, 0x0F, 0x07, 0x00,\n  0xE0, 0x70, 0x1C, 0x07, 0x01, 0xC0, 0x70, 0x38, 0x07, 0x03, 0x80, 0x70,\n  0x70, 0x07, 0x07, 0x00, 0x70, 0xE0, 0x03, 0x9E, 0x00, 0x39, 0xC0, 0x03,\n  0xB8, 0x00, 0x3B, 0x80, 0x03, 0xF0, 0x00, 0x3F, 0x00, 0x03, 0xE0, 0x00,\n  0x1E, 0x00, 0x01, 0xC0, 0x00, 0x38, 0x00, 0x03, 0x80, 0x00, 0x70, 0x00,\n  0x07, 0x00, 0x00, 0xE0, 0x00, 0xFE, 0x00, 0x0F, 0xC0, 0x00, 0xF0, 0x00,\n  0x00, 0x07, 0xFF, 0xC0, 0xFF, 0xF8, 0x3F, 0xFF, 0x00, 0x01, 0xC0, 0x00,\n  0x70, 0x00, 0x1C, 0x00, 0x07, 0x00, 0x01, 0xC0, 0x00, 0x70, 0x00, 0x1C,\n  0x00, 0x07, 0x00, 0x03, 0xC0, 0x00, 0xF0, 0x00, 0x3C, 0x00, 0x0F, 0x00,\n  0x03, 0xC0, 0x00, 0x7F, 0xFE, 0x1F, 0xFF, 0xC3, 0xFF, 0xF8, 0x00, 0x00,\n  0x70, 0x1F, 0x01, 0xF0, 0x3C, 0x03, 0x80, 0x38, 0x07, 0x00, 0x70, 0x07,\n  0x00, 0x70, 0x07, 0x00, 0xE0, 0x0E, 0x01, 0xE0, 0x3C, 0x0F, 0x80, 0xE0,\n  0x0F, 0x00, 0x78, 0x03, 0x80, 0x38, 0x03, 0x80, 0x38, 0x03, 0x80, 0x38,\n  0x07, 0x00, 0x70, 0x07, 0x00, 0x70, 0x0E, 0x00, 0xF8, 0x0F, 0x80, 0x78,\n  0x00, 0x01, 0x80, 0xC0, 0xC0, 0x60, 0x30, 0x18, 0x0C, 0x0C, 0x06, 0x03,\n  0x01, 0x81, 0xC0, 0xC0, 0x60, 0x30, 0x18, 0x18, 0x0C, 0x06, 0x03, 0x01,\n  0x81, 0x80, 0xC0, 0x60, 0x30, 0x38, 0x18, 0x0C, 0x06, 0x03, 0x03, 0x01,\n  0x80, 0xC0, 0x00, 0x01, 0xE0, 0x1F, 0x01, 0xF0, 0x07, 0x00, 0xE0, 0x0E,\n  0x00, 0xE0, 0x0E, 0x01, 0xC0, 0x1C, 0x01, 0xC0, 0x1C, 0x01, 0xC0, 0x1C,\n  0x01, 0xE0, 0x0F, 0x00, 0x70, 0x1F, 0x03, 0xC0, 0x78, 0x07, 0x00, 0x70,\n  0x0E, 0x00, 0xE0, 0x0E, 0x00, 0xE0, 0x0E, 0x01, 0xC0, 0x1C, 0x03, 0xC0,\n  0xF8, 0x0F, 0x80, 0xE0, 0x00, 0x1C, 0x00, 0x3F, 0x00, 0x7F, 0x83, 0x63,\n  0xC7, 0xC1, 0xFE, 0x00, 0xFC, 0x00, 0x78 };\n\nconst GFXglyph FreeSansOblique18pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,  10,    0,    1 },   // 0x20 ' '\n  {     0,   9,  26,  10,    4,  -25 },   // 0x21 '!'\n  {    30,  10,   9,  12,    6,  -24 },   // 0x22 '\"'\n  {    42,  21,  25,  19,    2,  -24 },   // 0x23 '#'\n  {   108,  20,  31,  19,    2,  -26 },   // 0x24 '$'\n  {   186,  26,  25,  31,    5,  -24 },   // 0x25 '%'\n  {   268,  20,  25,  23,    3,  -24 },   // 0x26 '&'\n  {   331,   4,   9,   7,    6,  -24 },   // 0x27 '''\n  {   336,  12,  33,  12,    4,  -25 },   // 0x28 '('\n  {   386,  12,  33,  12,   -1,  -24 },   // 0x29 ')'\n  {   436,  10,  10,  14,    6,  -25 },   // 0x2A '*'\n  {   449,  18,  16,  20,    3,  -15 },   // 0x2B '+'\n  {   485,   5,   8,  10,    2,   -2 },   // 0x2C ','\n  {   490,   9,   3,  12,    3,  -10 },   // 0x2D '-'\n  {   494,   4,   4,  10,    3,   -3 },   // 0x2E '.'\n  {   496,  15,  26,  10,    0,  -25 },   // 0x2F '/'\n  {   545,  18,  25,  19,    3,  -24 },   // 0x30 '0'\n  {   602,  10,  25,  19,    7,  -24 },   // 0x31 '1'\n  {   634,  20,  25,  19,    2,  -24 },   // 0x32 '2'\n  {   697,  19,  25,  19,    2,  -24 },   // 0x33 '3'\n  {   757,  18,  25,  19,    2,  -24 },   // 0x34 '4'\n  {   814,  20,  25,  19,    2,  -24 },   // 0x35 '5'\n  {   877,  19,  25,  19,    3,  -24 },   // 0x36 '6'\n  {   937,  18,  25,  19,    5,  -24 },   // 0x37 '7'\n  {   994,  19,  25,  19,    3,  -24 },   // 0x38 '8'\n  {  1054,  19,  25,  19,    2,  -24 },   // 0x39 '9'\n  {  1114,   7,  19,  10,    4,  -18 },   // 0x3A ':'\n  {  1131,   8,  24,  10,    3,  -18 },   // 0x3B ';'\n  {  1155,  19,  17,  20,    3,  -16 },   // 0x3C '<'\n  {  1196,  18,   9,  20,    3,  -12 },   // 0x3D '='\n  {  1217,  19,  17,  20,    2,  -15 },   // 0x3E '>'\n  {  1258,  16,  26,  19,    6,  -25 },   // 0x3F '?'\n  {  1310,  33,  31,  36,    3,  -25 },   // 0x40 '@'\n  {  1438,  23,  26,  23,    0,  -25 },   // 0x41 'A'\n  {  1513,  21,  26,  23,    3,  -25 },   // 0x42 'B'\n  {  1582,  22,  26,  25,    4,  -25 },   // 0x43 'C'\n  {  1654,  23,  26,  25,    3,  -25 },   // 0x44 'D'\n  {  1729,  23,  26,  23,    3,  -25 },   // 0x45 'E'\n  {  1804,  22,  26,  21,    3,  -25 },   // 0x46 'F'\n  {  1876,  24,  26,  27,    4,  -25 },   // 0x47 'G'\n  {  1954,  25,  26,  25,    3,  -25 },   // 0x48 'H'\n  {  2036,   8,  26,  10,    4,  -25 },   // 0x49 'I'\n  {  2062,  18,  26,  18,    2,  -25 },   // 0x4A 'J'\n  {  2121,  25,  26,  23,    3,  -25 },   // 0x4B 'K'\n  {  2203,  16,  26,  19,    3,  -25 },   // 0x4C 'L'\n  {  2255,  29,  26,  30,    3,  -25 },   // 0x4D 'M'\n  {  2350,  25,  26,  26,    3,  -25 },   // 0x4E 'N'\n  {  2432,  24,  26,  27,    4,  -25 },   // 0x4F 'O'\n  {  2510,  22,  26,  23,    3,  -25 },   // 0x50 'P'\n  {  2582,  25,  28,  27,    4,  -25 },   // 0x51 'Q'\n  {  2670,  23,  26,  25,    3,  -25 },   // 0x52 'R'\n  {  2745,  22,  26,  23,    3,  -25 },   // 0x53 'S'\n  {  2817,  20,  26,  21,    6,  -25 },   // 0x54 'T'\n  {  2882,  24,  26,  25,    4,  -25 },   // 0x55 'U'\n  {  2960,  21,  26,  23,    6,  -25 },   // 0x56 'V'\n  {  3029,  32,  26,  33,    6,  -25 },   // 0x57 'W'\n  {  3133,  27,  26,  23,    1,  -25 },   // 0x58 'X'\n  {  3221,  23,  26,  24,    6,  -25 },   // 0x59 'Y'\n  {  3296,  25,  26,  21,    1,  -25 },   // 0x5A 'Z'\n  {  3378,  13,  33,  10,    1,  -25 },   // 0x5B '['\n  {  3432,   4,  26,  10,    5,  -25 },   // 0x5C '\\'\n  {  3445,  13,  33,  10,   -1,  -24 },   // 0x5D ']'\n  {  3499,  14,  14,  16,    3,  -24 },   // 0x5E '^'\n  {  3524,  21,   2,  19,   -2,    5 },   // 0x5F '_'\n  {  3530,   6,   5,  12,    6,  -25 },   // 0x60 '`'\n  {  3534,  18,  19,  19,    2,  -18 },   // 0x61 'a'\n  {  3577,  19,  26,  20,    2,  -25 },   // 0x62 'b'\n  {  3639,  16,  19,  18,    3,  -18 },   // 0x63 'c'\n  {  3677,  20,  26,  20,    3,  -25 },   // 0x64 'd'\n  {  3742,  17,  19,  19,    3,  -18 },   // 0x65 'e'\n  {  3783,  11,  26,   9,    2,  -25 },   // 0x66 'f'\n  {  3819,  19,  27,  19,    2,  -18 },   // 0x67 'g'\n  {  3884,  18,  26,  19,    2,  -25 },   // 0x68 'h'\n  {  3943,   8,  26,   8,    2,  -25 },   // 0x69 'i'\n  {  3969,  14,  34,   8,   -2,  -25 },   // 0x6A 'j'\n  {  4029,  19,  26,  18,    2,  -25 },   // 0x6B 'k'\n  {  4091,   8,  26,   8,    2,  -25 },   // 0x6C 'l'\n  {  4117,  27,  19,  29,    2,  -18 },   // 0x6D 'm'\n  {  4182,  18,  19,  19,    2,  -18 },   // 0x6E 'n'\n  {  4225,  17,  19,  19,    3,  -18 },   // 0x6F 'o'\n  {  4266,  21,  26,  20,    0,  -18 },   // 0x70 'p'\n  {  4335,  20,  27,  19,    2,  -18 },   // 0x71 'q'\n  {  4403,  13,  19,  11,    2,  -18 },   // 0x72 'r'\n  {  4434,  16,  19,  18,    2,  -18 },   // 0x73 's'\n  {  4472,  10,  23,   9,    3,  -22 },   // 0x74 't'\n  {  4501,  18,  19,  19,    3,  -18 },   // 0x75 'u'\n  {  4544,  16,  19,  17,    4,  -18 },   // 0x76 'v'\n  {  4582,  24,  19,  25,    4,  -18 },   // 0x77 'w'\n  {  4639,  19,  19,  17,    1,  -18 },   // 0x78 'x'\n  {  4685,  20,  27,  17,    0,  -18 },   // 0x79 'y'\n  {  4753,  19,  19,  17,    1,  -18 },   // 0x7A 'z'\n  {  4799,  12,  33,  12,    3,  -25 },   // 0x7B '{'\n  {  4849,   9,  33,   9,    2,  -25 },   // 0x7C '|'\n  {  4887,  12,  33,  12,    0,  -24 },   // 0x7D '}'\n  {  4937,  16,   7,  20,    5,  -15 } }; // 0x7E '~'\n\nconst GFXfont FreeSansOblique18pt7b PROGMEM = {\n  (uint8_t  *)FreeSansOblique18pt7bBitmaps,\n  (GFXglyph *)FreeSansOblique18pt7bGlyphs,\n  0x20, 0x7E, 42 };\n\n// Approx. 5623 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeSansOblique24pt7b.h",
    "content": "const uint8_t FreeSansOblique24pt7bBitmaps[] PROGMEM = {\n  0x01, 0xE0, 0x3C, 0x0F, 0x81, 0xE0, 0x3C, 0x07, 0x80, 0xF0, 0x3C, 0x07,\n  0x80, 0xF0, 0x1E, 0x03, 0xC0, 0xF0, 0x1E, 0x03, 0xC0, 0x78, 0x0F, 0x03,\n  0xC0, 0x78, 0x0F, 0x01, 0xE0, 0x38, 0x07, 0x00, 0xE0, 0x18, 0x03, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0xF0, 0x1E, 0x07, 0x80, 0xF0, 0x1E, 0x00, 0x78,\n  0x7B, 0xC3, 0xDE, 0x1F, 0xE1, 0xEF, 0x0F, 0x78, 0x7B, 0xC3, 0xDC, 0x1C,\n  0xE0, 0xE7, 0x07, 0x30, 0x31, 0x81, 0x80, 0x00, 0x07, 0x81, 0xC0, 0x00,\n  0x78, 0x3C, 0x00, 0x07, 0x03, 0xC0, 0x00, 0xF0, 0x38, 0x00, 0x0E, 0x07,\n  0x80, 0x01, 0xE0, 0x70, 0x00, 0x1E, 0x0F, 0x00, 0x01, 0xC0, 0xF0, 0x00,\n  0x3C, 0x0E, 0x00, 0xFF, 0xFF, 0xFE, 0x0F, 0xFF, 0xFF, 0xE0, 0xFF, 0xFF,\n  0xFE, 0x00, 0x70, 0x3C, 0x00, 0x0F, 0x03, 0x80, 0x00, 0xF0, 0x78, 0x00,\n  0x0E, 0x07, 0x80, 0x01, 0xE0, 0x70, 0x00, 0x1C, 0x0F, 0x00, 0x03, 0xC0,\n  0xE0, 0x00, 0x3C, 0x1E, 0x00, 0x03, 0x81, 0xE0, 0x0F, 0xFF, 0xFF, 0xE0,\n  0xFF, 0xFF, 0xFE, 0x0F, 0xFF, 0xFF, 0xE0, 0x0F, 0x03, 0x80, 0x00, 0xE0,\n  0x78, 0x00, 0x1E, 0x07, 0x00, 0x01, 0xC0, 0xF0, 0x00, 0x1C, 0x0F, 0x00,\n  0x03, 0xC0, 0xE0, 0x00, 0x38, 0x1E, 0x00, 0x07, 0x81, 0xC0, 0x00, 0x78,\n  0x3C, 0x00, 0x07, 0x03, 0xC0, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x30,\n  0x00, 0x00, 0x7F, 0x80, 0x00, 0xFF, 0xF8, 0x00, 0x7F, 0xFF, 0x00, 0x7F,\n  0xFF, 0xE0, 0x1F, 0x18, 0xF8, 0x0F, 0x8E, 0x1F, 0x07, 0xC3, 0x83, 0xC1,\n  0xE0, 0xE0, 0xF0, 0x70, 0x38, 0x3C, 0x3C, 0x0C, 0x0F, 0x0F, 0x07, 0x00,\n  0x03, 0xC1, 0xC0, 0x00, 0xF0, 0x70, 0x00, 0x3E, 0x1C, 0x00, 0x0F, 0xE6,\n  0x00, 0x01, 0xFF, 0xC0, 0x00, 0x3F, 0xFE, 0x00, 0x03, 0xFF, 0xE0, 0x00,\n  0x3F, 0xFC, 0x00, 0x03, 0xFF, 0x80, 0x01, 0xC7, 0xF0, 0x00, 0x70, 0x7C,\n  0x00, 0x1C, 0x0F, 0x00, 0x06, 0x03, 0xCF, 0x03, 0x80, 0xF3, 0xC0, 0xE0,\n  0x3C, 0xF0, 0x38, 0x0E, 0x3C, 0x0E, 0x07, 0x8F, 0x03, 0x01, 0xE3, 0xE1,\n  0xC0, 0xF0, 0xF8, 0x70, 0x78, 0x1F, 0x9C, 0xFC, 0x03, 0xFF, 0xFE, 0x00,\n  0x7F, 0xFF, 0x00, 0x03, 0xFE, 0x00, 0x00, 0x38, 0x00, 0x00, 0x0E, 0x00,\n  0x00, 0x03, 0x00, 0x00, 0x01, 0xC0, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x07, 0x80, 0x1F, 0x00, 0x00, 0x70, 0x07, 0xFC, 0x00, 0x0E,\n  0x00, 0xFF, 0xE0, 0x01, 0xC0, 0x1E, 0x1E, 0x00, 0x3C, 0x03, 0x80, 0xF0,\n  0x03, 0x80, 0x70, 0x07, 0x00, 0x70, 0x07, 0x00, 0x70, 0x0E, 0x00, 0xE0,\n  0x07, 0x01, 0xC0, 0x0E, 0x00, 0x70, 0x3C, 0x00, 0xE0, 0x0E, 0x03, 0x80,\n  0x0E, 0x00, 0xE0, 0x70, 0x00, 0xF0, 0x1C, 0x0E, 0x00, 0x07, 0x87, 0xC1,\n  0xE0, 0x00, 0x7F, 0xF8, 0x1C, 0x00, 0x03, 0xFE, 0x03, 0x80, 0x00, 0x0F,\n  0x80, 0x70, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x01, 0xE0, 0x1F,\n  0x00, 0x00, 0x1C, 0x07, 0xFC, 0x00, 0x03, 0x80, 0xFF, 0xE0, 0x00, 0x70,\n  0x1E, 0x1E, 0x00, 0x0F, 0x03, 0x80, 0xF0, 0x00, 0xE0, 0x70, 0x07, 0x00,\n  0x1C, 0x07, 0x00, 0x70, 0x03, 0x80, 0xE0, 0x07, 0x00, 0x70, 0x0E, 0x00,\n  0x70, 0x0F, 0x00, 0xE0, 0x0E, 0x00, 0xE0, 0x0E, 0x00, 0xE0, 0x1C, 0x00,\n  0xF0, 0x1C, 0x03, 0x80, 0x07, 0x87, 0xC0, 0x70, 0x00, 0x7F, 0xF8, 0x07,\n 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0xFF, 0x0F, 0xF0, 0xFF, 0xC3, 0xF0, 0xFC, 0x07,\n  0xF8, 0x1F, 0x1F, 0x80, 0x3F, 0x00, 0xF1, 0xF0, 0x03, 0xE0, 0x0F, 0x1E,\n  0x00, 0x3C, 0x00, 0xF1, 0xE0, 0x03, 0xC0, 0x0F, 0x1E, 0x00, 0x3C, 0x00,\n  0xF1, 0xE0, 0x07, 0x80, 0x0F, 0x3C, 0x00, 0x78, 0x01, 0xF3, 0xC0, 0x07,\n  0x80, 0x1E, 0x3C, 0x00, 0x78, 0x01, 0xE3, 0xC0, 0x0F, 0x80, 0x1E, 0x3C,\n  0x00, 0xF0, 0x01, 0xE7, 0xC0, 0x0F, 0x00, 0x3C, 0x78, 0x00, 0xF0, 0x03,\n  0xC7, 0x80, 0x0F, 0x00, 0x3C, 0x78, 0x01, 0xE0, 0x03, 0xC7, 0x80, 0x1E,\n  0x00, 0x3C, 0xF8, 0x01, 0xE0, 0x07, 0x8F, 0x00, 0x1E, 0x00, 0x78, 0xF0,\n  0x01, 0xE0, 0x07, 0x8F, 0x00, 0x3C, 0x00, 0x78, 0x00, 0x07, 0xE0, 0x1F,\n  0x3F, 0xF0, 0x3C, 0xFF, 0xF0, 0x7B, 0xFF, 0xE0, 0xFF, 0x07, 0xE1, 0xF8,\n  0x07, 0xC7, 0xE0, 0x07, 0x8F, 0x80, 0x0F, 0x1F, 0x00, 0x1E, 0x3C, 0x00,\n  0x3C, 0x78, 0x00, 0x78, 0xF0, 0x01, 0xE3, 0xC0, 0x03, 0xC7, 0x80, 0x07,\n  0x8F, 0x00, 0x0F, 0x1E, 0x00, 0x3E, 0x3C, 0x00, 0x78, 0xF0, 0x00, 0xF1,\n  0xE0, 0x01, 0xE3, 0xC0, 0x03, 0xC7, 0x80, 0x0F, 0x8F, 0x00, 0x1E, 0x3E,\n  0x00, 0x3C, 0x78, 0x00, 0x78, 0xF0, 0x00, 0xF1, 0xE0, 0x03, 0xC0, 0x00,\n  0x1F, 0x80, 0x01, 0xFF, 0xC0, 0x0F, 0xFF, 0xE0, 0x3F, 0xFF, 0xC0, 0xFE,\n  0x0F, 0xC1, 0xF0, 0x0F, 0x87, 0xC0, 0x0F, 0x8F, 0x00, 0x0F, 0x3C, 0x00,\n  0x1E, 0x78, 0x00, 0x3D, 0xE0, 0x00, 0x7B, 0xC0, 0x00, 0xF7, 0x80, 0x01,\n  0xFE, 0x00, 0x03, 0xFC, 0x00, 0x0F, 0x78, 0x00, 0x1E, 0xF0, 0x00, 0x3D,\n  0xE0, 0x00, 0xF3, 0xC0, 0x01, 0xE7, 0x80, 0x07, 0x8F, 0x80, 0x1F, 0x0F,\n  0x80, 0x7C, 0x1F, 0x83, 0xF8, 0x1F, 0xFF, 0xE0, 0x3F, 0xFF, 0x00, 0x1F,\n  0xFC, 0x00, 0x0F, 0xC0, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x3C, 0x7F, 0xE0,\n  0x07, 0xBF, 0xFE, 0x01, 0xFF, 0xFF, 0xC0, 0x3D, 0xE0, 0xFC, 0x07, 0xF0,\n  0x0F, 0x80, 0xFC, 0x00, 0xF8, 0x1F, 0x00, 0x0F, 0x07, 0xC0, 0x01, 0xE0,\n  0xF8, 0x00, 0x3C, 0x1F, 0x00, 0x07, 0x83, 0xC0, 0x00, 0xF0, 0x78, 0x00,\n  0x1E, 0x1F, 0x00, 0x03, 0xC3, 0xC0, 0x00, 0xF0, 0x78, 0x00, 0x1E, 0x0F,\n  0x00, 0x03, 0xC3, 0xE0, 0x00, 0xF8, 0x7C, 0x00, 0x1E, 0x0F, 0x80, 0x07,\n  0xC1, 0xF8, 0x01, 0xF0, 0x3F, 0x80, 0x7C, 0x0F, 0xF8, 0x3F, 0x81, 0xEF,\n  0xFF, 0xE0, 0x3C, 0xFF, 0xF8, 0x07, 0x8F, 0xFC, 0x00, 0xF0, 0xFE, 0x00,\n  0x3E, 0x00, 0x00, 0x07, 0x80, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x1E, 0x00,\n  0x00, 0x03, 0xC0, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x03,\n  0xC0, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x80, 0x00, 0x3F,\n  0xF8, 0xF0, 0x1F, 0xFF, 0x3C, 0x0F, 0xFF, 0xDF, 0x07, 0xE0, 0xFF, 0x83,\n  0xE0, 0x1F, 0xE1, 0xF0, 0x03, 0xF8, 0x78, 0x00, 0xFE, 0x3C, 0x00, 0x1F,\n  0x8F, 0x00, 0x07, 0xC7, 0x80, 0x01, 0xF1, 0xE0, 0x00, 0x7C, 0x78, 0x00,\n  0x1F, 0x3C, 0x00, 0x0F, 0x8F, 0x00, 0x03, 0xE3, 0xC0, 0x00, 0xF8, 0xF0,\n  0x00, 0x3E, 0x3C, 0x00, 0x1F, 0x8F, 0x00, 0x0F, 0xC3, 0xC0, 0x03, 0xF0,\n  0xF8, 0x01, 0xFC, 0x1F, 0x00, 0xFF, 0x07, 0xE0, 0xFF, 0xC0, 0xFF, 0xFD,\n  0xE0, 0x1F, 0xFE, 0x78, 0x03, 0xFF, 0x3E, 0x00, 0x3F, 0x0F, 0x80, 0x00,\n  0x03, 0xC0, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x1F, 0x00,\n  0x00, 0x07, 0xC0, 0x00, 0x01, 0xE0, 0x00, 0x00, 0x78, 0x00, 0x00, 0x3E,\n  0x00, 0x00, 0x0F, 0x80, 0x00, 0x07, 0x87, 0xCF, 0xC3, 0xCF, 0xE1, 0xEF,\n  0xE0, 0xFF, 0x80, 0x7F, 0x00, 0x7E, 0x00, 0x3F, 0x00, 0x1F, 0x00, 0x0F,\n  0x00, 0x07, 0x80, 0x03, 0xC0, 0x03, 0xC0, 0x01, 0xE0, 0x00, 0xF0, 0x00,\n  0x78, 0x00, 0x3C, 0x00, 0x3E, 0x00, 0x1E, 0x00, 0x0F, 0x00, 0x07, 0x80,\n  0x03, 0xC0, 0x03, 0xE0, 0x01, 0xE0, 0x00, 0xF0, 0x00, 0x78, 0x00, 0x00,\n  0x00, 0x3F, 0x80, 0x07, 0xFF, 0x00, 0xFF, 0xFC, 0x0F, 0xFF, 0xE0, 0xFC,\n  0x1F, 0x87, 0x80, 0x3C, 0x7C, 0x01, 0xE3, 0xC0, 0x0F, 0x1E, 0x00, 0x00,\n  0xF0, 0x00, 0x07, 0xC0, 0x00, 0x3F, 0xC0, 0x00, 0xFF, 0xE0, 0x03, 0xFF,\n  0xC0, 0x07, 0xFF, 0x80, 0x07, 0xFE, 0x00, 0x03, 0xF0, 0x00, 0x07, 0xBC,\n  0x00, 0x3D, 0xE0, 0x01, 0xEF, 0x00, 0x1F, 0x7C, 0x01, 0xF3, 0xF0, 0x1F,\n  0x8F, 0xFF, 0xF8, 0x7F, 0xFF, 0x80, 0xFF, 0xF0, 0x01, 0xFE, 0x00, 0x03,\n  0xC0, 0x1E, 0x01, 0xE0, 0x0F, 0x00, 0x78, 0x03, 0xC1, 0xFF, 0xEF, 0xFF,\n  0x7F, 0xF0, 0x78, 0x03, 0xC0, 0x3C, 0x01, 0xE0, 0x0F, 0x00, 0x78, 0x03,\n  0xC0, 0x3C, 0x01, 0xE0, 0x0F, 0x00, 0x78, 0x03, 0xC0, 0x3C, 0x01, 0xE0,\n  0x0F, 0x00, 0x78, 0x07, 0xC0, 0x3C, 0x01, 0xE0, 0x0F, 0xF0, 0x7F, 0x81,\n  0xF8, 0x07, 0xC0, 0x0F, 0x00, 0x0F, 0x0F, 0x00, 0x1E, 0x0F, 0x00, 0x1E,\n  0x1F, 0x00, 0x1E, 0x1E, 0x00, 0x1E, 0x1E, 0x00, 0x1E, 0x1E, 0x00, 0x3C,\n  0x1E, 0x00, 0x3C, 0x3E, 0x00, 0x3C, 0x3C, 0x00, 0x3C, 0x3C, 0x00, 0x3C,\n  0x3C, 0x00, 0x7C, 0x3C, 0x00, 0x78, 0x78, 0x00, 0x78, 0x78, 0x00, 0x78,\n  0x78, 0x00, 0x78, 0x78, 0x00, 0xF8, 0x78, 0x00, 0xF0, 0xF0, 0x01, 0xF0,\n  0xF0, 0x03, 0xF0, 0xF0, 0x07, 0xF0, 0xF8, 0x1F, 0xF0, 0xFF, 0xFF, 0xE0,\n  0x7F, 0xFD, 0xE0, 0x3F, 0xF1, 0xE0, 0x1F, 0xC0, 0x00, 0xF0, 0x00, 0x7F,\n  0xC0, 0x01, 0xEF, 0x00, 0x0F, 0xBC, 0x00, 0x3C, 0x78, 0x01, 0xE1, 0xE0,\n  0x07, 0x87, 0x80, 0x3C, 0x1E, 0x01, 0xF0, 0x78, 0x07, 0x81, 0xE0, 0x3E,\n  0x07, 0x80, 0xF0, 0x1E, 0x07, 0x80, 0x38, 0x1E, 0x00, 0xF0, 0xF0, 0x03,\n  0xC7, 0xC0, 0x0F, 0x1E, 0x00, 0x3C, 0xF0, 0x00, 0xF3, 0xC0, 0x03, 0xDE,\n  0x00, 0x07, 0x78, 0x00, 0x1F, 0xC0, 0x00, 0x7E, 0x00, 0x01, 0xF8, 0x00,\n  0x07, 0xC0, 0x00, 0x1F, 0x00, 0x00, 0xF0, 0x07, 0xC0, 0x0F, 0x78, 0x03,\n  0xE0, 0x0F, 0xBC, 0x03, 0xF0, 0x07, 0x9E, 0x01, 0xF8, 0x03, 0xCF, 0x00,\n  0xFC, 0x03, 0xC7, 0x80, 0xFE, 0x01, 0xE3, 0xC0, 0x77, 0x01, 0xE0, 0xE0,\n  0x7B, 0x80, 0xF0, 0x70, 0x39, 0xC0, 0xF0, 0x38, 0x3C, 0xE0, 0x78, 0x1C,\n  0x1E, 0x78, 0x78, 0x0F, 0x1E, 0x3C, 0x3C, 0x07, 0x8F, 0x1E, 0x3C, 0x03,\n  0xC7, 0x0F, 0x1E, 0x01, 0xE7, 0x87, 0x9E, 0x00, 0xF3, 0x81, 0xCF, 0x00,\n  0x7B, 0xC0, 0xEF, 0x00, 0x3D, 0xC0, 0x77, 0x80, 0x1F, 0xE0, 0x3F, 0x80,\n  0x0F, 0xF0, 0x1F, 0xC0, 0x07, 0xF0, 0x0F, 0xC0, 0x01, 0xF8, 0x07, 0xE0,\n  0x00, 0xF8, 0x03, 0xE0, 0x00, 0x7C, 0x01, 0xF0, 0x00, 0x3C, 0x00, 0xF0,\n  0x00, 0x00, 0x03, 0xC0, 0x07, 0xC0, 0xF8, 0x01, 0xE0, 0x1E, 0x00, 0xF0,\n  0x07, 0x80, 0x78, 0x00, 0xF0, 0x3C, 0x00, 0x3C, 0x1F, 0x00, 0x0F, 0x8F,\n  0x80, 0x01, 0xE7, 0xC0, 0x00, 0x7D, 0xE0, 0x00, 0x0F, 0xF0, 0x00, 0x03,\n  0xF8, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x0F, 0xC0, 0x00,\n  0x07, 0xF0, 0x00, 0x03, 0xFE, 0x00, 0x01, 0xF7, 0x80, 0x00, 0xF9, 0xF0,\n  0x00, 0x3C, 0x3C, 0x00, 0x1E, 0x0F, 0x80, 0x0F, 0x01, 0xE0, 0x07, 0x80,\n  0x7C, 0x03, 0xE0, 0x0F, 0x01, 0xF0, 0x03, 0xE0, 0xF8, 0x00, 0x78, 0x00,\n  0x03, 0xC0, 0x01, 0xE0, 0x78, 0x00, 0x78, 0x0F, 0x00, 0x0F, 0x01, 0xE0,\n  0x03, 0xC0, 0x3C, 0x00, 0x78, 0x07, 0xC0, 0x1E, 0x00, 0x78, 0x07, 0xC0,\n  0x0F, 0x00, 0xF0, 0x01, 0xE0, 0x3C, 0x00, 0x3C, 0x07, 0x80, 0x07, 0x81,\n  0xE0, 0x00, 0xF0, 0x3C, 0x00, 0x1E, 0x0F, 0x00, 0x03, 0xC1, 0xC0, 0x00,\n  0x3C, 0x78, 0x00, 0x07, 0x9E, 0x00, 0x00, 0xF3, 0xC0, 0x00, 0x1E, 0xF0,\n  0x00, 0x03, 0xDE, 0x00, 0x00, 0x7F, 0x80, 0x00, 0x0F, 0xE0, 0x00, 0x01,\n  0xFC, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x03, 0xE0, 0x00, 0x00, 0x78, 0x00,\n  0x00, 0x0F, 0x00, 0x00, 0x03, 0xC0, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x1E,\n  0x00, 0x00, 0x07, 0x80, 0x00, 0x01, 0xF0, 0x00, 0x03, 0xFC, 0x00, 0x00,\n  0xFF, 0x00, 0x00, 0x1F, 0xC0, 0x00, 0x03, 0xE0, 0x00, 0x00, 0x00, 0x01,\n  0xFF, 0xFF, 0x81, 0xFF, 0xFF, 0xC0, 0xFF, 0xFF, 0xE0, 0x7F, 0xFF, 0xE0,\n  0x00, 0x01, 0xF0, 0x00, 0x01, 0xF0, 0x00, 0x01, 0xF0, 0x00, 0x01, 0xF0,\n  0x00, 0x01, 0xF0, 0x00, 0x01, 0xE0, 0x00, 0x01, 0xE0, 0x00, 0x01, 0xE0,\n  0x00, 0x01, 0xE0, 0x00, 0x03, 0xE0, 0x00, 0x03, 0xE0, 0x00, 0x03, 0xE0,\n  0x00, 0x03, 0xE0, 0x00, 0x03, 0xE0, 0x00, 0x03, 0xE0, 0x00, 0x03, 0xE0,\n  0x00, 0x03, 0xC0, 0x00, 0x03, 0xFF, 0xFF, 0xC1, 0xFF, 0xFF, 0xE0, 0xFF,\n  0xFF, 0xF0, 0x7F, 0xFF, 0xF8, 0x00, 0x00, 0x1F, 0x00, 0x7E, 0x00, 0xFE,\n  0x00, 0xF0, 0x01, 0xE0, 0x01, 0xE0, 0x01, 0xE0, 0x03, 0xC0, 0x03, 0xC0,\n  0x03, 0xC0, 0x03, 0xC0, 0x07, 0xC0, 0x07, 0x80, 0x07, 0x80, 0x07, 0x80,\n  0x07, 0x80, 0x0F, 0x00, 0x0F, 0x00, 0x1E, 0x00, 0x3C, 0x00, 0xF8, 0x00,\n  0xE0, 0x00, 0xF0, 0x00, 0x78, 0x00, 0x38, 0x00, 0x38, 0x00, 0x38, 0x00,\n  0x38, 0x00, 0x38, 0x00, 0x3C, 0x00, 0x7C, 0x00, 0x78, 0x00, 0x78, 0x00,\n  0x78, 0x00, 0x78, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0xE0, 0x00,\n  0xE0, 0x00, 0xF0, 0x00, 0xFC, 0x00, 0xFC, 0x00, 0x7C, 0x00, 0x00, 0x70,\n  0x07, 0x00, 0x60, 0x06, 0x00, 0xE0, 0x0E, 0x00, 0xE0, 0x0C, 0x01, 0xC0,\n  0x1C, 0x01, 0xC0, 0x1C, 0x01, 0x80, 0x38, 0x03, 0x80, 0x38, 0x03, 0x00,\n  0x30, 0x07, 0x00, 0x70, 0x07, 0x00, 0x60, 0x0E, 0x00, 0xE0, 0x0E, 0x00,\n  0xE0, 0x0C, 0x01, 0xC0, 0x1C, 0x01, 0xC0, 0x1C, 0x01, 0x80, 0x38, 0x03,\n  0x80, 0x38, 0x03, 0x00, 0x70, 0x07, 0x00, 0x70, 0x07, 0x00, 0x60, 0x0E,\n  0x00, 0xE0, 0x06, 0x00, 0x00, 0x3E, 0x00, 0x3E, 0x00, 0x3F, 0x00, 0x0F,\n  0x00, 0x07, 0x00, 0x07, 0x00, 0x0F, 0x00, 0x0F, 0x00, 0x0F, 0x00, 0x1E,\n  0x00, 0x1E, 0x00, 0x1E, 0x00, 0x1E, 0x00, 0x3E, 0x00, 0x3C, 0x00, 0x1C,\n  0x00, 0x1C, 0x00, 0x1C, 0x00, 0x1C, 0x00, 0x1C, 0x00, 0x1E, 0x00, 0x0F,\n  0x00, 0x07, 0x00, 0x1F, 0x00, 0x3C, 0x00, 0x78, 0x00, 0xF0, 0x00, 0xF0,\n  0x01, 0xE0, 0x01, 0xE0, 0x01, 0xE0, 0x01, 0xE0, 0x03, 0xE0, 0x03, 0xC0,\n  0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x07, 0x80, 0x07, 0x80, 0x07, 0x80,\n  0x0F, 0x00, 0x7F, 0x00, 0x7E, 0x00, 0xF8, 0x00, 0x0F, 0x00, 0x01, 0xFE,\n  0x00, 0xCF, 0xFC, 0x0E, 0xE3, 0xF0, 0xE6, 0x07, 0xFF, 0x60, 0x0F, 0xF0,\n  0x00, 0x1E, 0x00 };\n\nconst GFXglyph FreeSansOblique24pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,  13,    0,    1 },   // 0x20 ' '\n  {     0,  11,  34,  13,    6,  -33 },   // 0x21 '!'\n  {    47,  13,  12,  17,    8,  -32 },   // 0x22 '\"'\n  {    67,  28,  34,  26,    3,  -32 },   // 0x23 '#'\n  {   186,  26,  42,  26,    3,  -35 },   // 0x24 '$'\n  {   323,  36,  34,  42,    6,  -32 },   // 0x25 '%'\n  {   476,  26,  34,  31,    4,  -32 },   // 0x26 '&'\n  {   587,   5,  12,   9,    8,  -32 },   // 0x27 '''\n  {   595,  15,  44,  16,    5,  -33 },   // 0x28 '('\n  {   678,  15,  44,  16,    1,  -33 },   // 0x29 ')'\n  {   761,  14,  13,  18,    8,  -33 },   // 0x2A '*'\n  {   784,  23,  22,  27,    5,  -20 },   // 0x2B '+'\n  {   848,   7,  12,  13,    3,   -4 },   // 0x2C ','\n  {   859,  12,   4,  16,    5,  -14 },   // 0x2D '-'\n  {   865,   6,   5,  13,    4,   -4 },   // 0x2E '.'\n  {   869,  21,  35,  13,   -1,  -33 },   // 0x2F '/'\n  {   961,  23,  34,  26,    5,  -32 },   // 0x30 '0'\n  {  1059,  13,  33,  26,   10,  -32 },   // 0x31 '1'\n  {  1113,  27,  33,  26,    2,  -32 },   // 0x32 '2'\n  {  1225,  25,  34,  26,    3,  -32 },   // 0x33 '3'\n  {  1332,  24,  33,  26,    3,  -32 },   // 0x34 '4'\n  {  1431,  27,  34,  26,    3,  -32 },   // 0x35 '5'\n  {  1546,  24,  34,  26,    4,  -32 },   // 0x36 '6'\n  {  1648,  26,  33,  26,    6,  -32 },   // 0x37 '7'\n  {  1756,  25,  34,  26,    3,  -32 },   // 0x38 '8'\n  {  1863,  24,  34,  26,    4,  -32 },   // 0x39 '9'\n  {  1965,  10,  25,  13,    5,  -24 },   // 0x3A ':'\n  {  1997,  11,  32,  13,    4,  -24 },   // 0x3B ';'\n  {  2041,  26,  23,  27,    4,  -22 },   // 0x3C '<'\n  {  2116,  26,  12,  27,    3,  -16 },   // 0x3D '='\n  {  2155,  26,  23,  27,    2,  -21 },   // 0x3E '>'\n  {  2230,  20,  35,  26,    9,  -34 },   // 0x3F '?'\n  {  2318,  45,  42,  48,    4,  -34 },   // 0x40 '@'\n  {  2555,  30,  34,  31,    1,  -33 },   // 0x41 'A'\n  {  2683,  29,  34,  31,    4,  -33 },   // 0x42 'B'\n  {  2807,  30,  36,  33,    5,  -34 },   // 0x43 'C'\n  {  2942,  31,  34,  33,    4,  -33 },   // 0x44 'D'\n  {  3074,  31,  34,  31,    4,  -33 },   // 0x45 'E'\n  {  3206,  30,  34,  28,    4,  -33 },   // 0x46 'F'\n  {  3334,  33,  36,  37,    5,  -34 },   // 0x47 'G'\n  {  3483,  33,  34,  34,    4,  -33 },   // 0x48 'H'\n  {  3624,  11,  34,  13,    5,  -33 },   // 0x49 'I'\n  {  3671,  25,  35,  24,    2,  -33 },   // 0x4A 'J'\n  {  3781,  34,  34,  31,    4,  -33 },   // 0x4B 'K'\n  {  3926,  22,  34,  26,    4,  -33 },   // 0x4C 'L'\n  {  4020,  39,  34,  40,    4,  -33 },   // 0x4D 'M'\n  {  4186,  34,  34,  34,    4,  -33 },   // 0x4E 'N'\n  {  4331,  33,  36,  36,    5,  -34 },   // 0x4F 'O'\n  {  4480,  29,  34,  30,    4,  -33 },   // 0x50 'P'\n  {  4604,  33,  38,  36,    5,  -34 },   // 0x51 'Q'\n  {  4761,  30,  34,  33,    4,  -33 },   // 0x52 'R'\n  {  4889,  29,  36,  31,    4,  -34 },   // 0x53 'S'\n  {  5020,  28,  34,  29,    7,  -33 },   // 0x54 'T'\n  {  5139,  31,  35,  34,    6,  -33 },   // 0x55 'U'\n  {  5275,  29,  34,  30,    8,  -33 },   // 0x56 'V'\n  {  5399,  43,  34,  44,    8,  -33 },   // 0x57 'W'\n  {  5582,  36,  34,  31,    1,  -33 },   // 0x58 'X'\n  {  5735,  30,  34,  32,    8,  -33 },   // 0x59 'Y'\n  {  5863,  34,  34,  29,    1,  -33 },   // 0x5A 'Z'\n  {  6008,  18,  44,  13,    1,  -33 },   // 0x5B '['\n  {  6107,   6,  35,  13,    7,  -33 },   // 0x5C '\\'\n  {  6134,  18,  44,  13,   -1,  -33 },   // 0x5D ']'\n  {  6233,  17,  18,  22,    6,  -32 },   // 0x5E '^'\n  {  6272,  29,   2,  26,   -3,    7 },   // 0x5F '_'\n  {  6280,   8,   7,  16,    8,  -34 },   // 0x60 '`'\n  {  6287,  23,  27,  26,    3,  -25 },   // 0x61 'a'\n  {  6365,  25,  35,  26,    3,  -33 },   // 0x62 'b'\n  {  6475,  22,  27,  24,    4,  -25 },   // 0x63 'c'\n  {  6550,  27,  35,  26,    4,  -33 },   // 0x64 'd'\n  {  6669,  23,  27,  26,    4,  -25 },   // 0x65 'e'\n  {  6747,  15,  34,  12,    3,  -33 },   // 0x66 'f'\n  {  6811,  27,  36,  26,    2,  -25 },   // 0x67 'g'\n  {  6933,  23,  34,  25,    3,  -33 },   // 0x68 'h'\n  {  7031,  11,  34,  10,    3,  -33 },   // 0x69 'i'\n  {  7078,  18,  44,  11,   -2,  -33 },   // 0x6A 'j'\n  {  7177,  25,  34,  24,    3,  -33 },   // 0x6B 'k'\n  {  7284,  11,  34,  10,    3,  -33 },   // 0x6C 'l'\n  {  7331,  36,  26,  38,    3,  -25 },   // 0x6D 'm'\n  {  7448,  23,  26,  25,    3,  -25 },   // 0x6E 'n'\n  {  7523,  23,  27,  26,    4,  -25 },   // 0x6F 'o'\n  {  7601,  27,  36,  26,    1,  -25 },   // 0x70 'p'\n  {  7723,  26,  36,  26,    3,  -25 },   // 0x71 'q'\n  {  7840,  17,  26,  15,    3,  -25 },   // 0x72 'r'\n  {  7896,  21,  27,  24,    3,  -25 },   // 0x73 's'\n  {  7967,  13,  32,  12,    4,  -30 },   // 0x74 't'\n  {  8019,  24,  26,  25,    4,  -24 },   // 0x75 'u'\n  {  8097,  22,  25,  23,    6,  -24 },   // 0x76 'v'\n  {  8166,  33,  25,  34,    6,  -24 },   // 0x77 'w'\n  {  8270,  26,  25,  23,    1,  -24 },   // 0x78 'x'\n  {  8352,  27,  35,  23,    0,  -24 },   // 0x79 'y'\n  {  8471,  25,  25,  23,    1,  -24 },   // 0x7A 'z'\n  {  8550,  16,  44,  16,    5,  -33 },   // 0x7B '{'\n  {  8638,  12,  44,  12,    3,  -33 },   // 0x7C '|'\n  {  8704,  16,  44,  16,   -1,  -33 },   // 0x7D '}'\n  {  8792,  21,   7,  27,    6,  -19 } }; // 0x7E '~'\n\nconst GFXfont FreeSansOblique24pt7b PROGMEM = {\n  (uint8_t  *)FreeSansOblique24pt7bBitmaps,\n  (GFXglyph *)FreeSansOblique24pt7bGlyphs,\n  0x20, 0x7E, 56 };\n\n// Approx. 9483 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeSansOblique9pt7b.h",
    "content": "const uint8_t FreeSansOblique9pt7bBitmaps[] PROGMEM = {\n  0x10, 0x84, 0x22, 0x10, 0x84, 0x42, 0x10, 0x08, 0x00, 0xDE, 0xE5, 0x20,\n  0x06, 0x40, 0x88, 0x13, 0x06, 0x43, 0xFE, 0x32, 0x04, 0x40, 0x98, 0x32,\n  0x1F, 0xF0, 0x98, 0x22, 0x04, 0xC0, 0x02, 0x01, 0xF8, 0x6B, 0x99, 0x33,\n  0x40, 0x68, 0x0F, 0x00, 0xF8, 0x07, 0xC1, 0x1B, 0x23, 0x64, 0x4E, 0x98,\n  0xFC, 0x04, 0x00, 0x80, 0x3C, 0x08, 0xCC, 0x23, 0x18, 0x86, 0x32, 0x0C,\n  0x64, 0x19, 0x90, 0x1E, 0x40, 0x01, 0x1E, 0x02, 0x66, 0x09, 0x8C, 0x23,\n  0x18, 0x86, 0x62, 0x07, 0x80, 0x0F, 0x06, 0x63, 0x18, 0xC6, 0x3F, 0x07,\n  0x03, 0xC1, 0xB3, 0xC7, 0xB0, 0xCC, 0x33, 0x3E, 0x79, 0x80, 0xFA, 0x04,\n  0x10, 0x60, 0x83, 0x04, 0x18, 0x30, 0xC1, 0x83, 0x06, 0x0C, 0x18, 0x10,\n  0x30, 0x20, 0x08, 0x18, 0x10, 0x30, 0x60, 0xC1, 0x83, 0x06, 0x18, 0x30,\n  0x41, 0x82, 0x0C, 0x10, 0x40, 0x19, 0x73, 0x16, 0x48, 0x04, 0x04, 0x02,\n  0x1F, 0xF0, 0x80, 0x80, 0x40, 0x20, 0x6D, 0x28, 0xF0, 0xC0, 0x01, 0x02,\n  0x04, 0x04, 0x08, 0x08, 0x10, 0x10, 0x20, 0x20, 0x40, 0x40, 0x80, 0x0F,\n  0x19, 0xC8, 0x6C, 0x36, 0x1A, 0x0F, 0x05, 0x86, 0xC3, 0x61, 0xB1, 0x9C,\n  0x87, 0x80, 0x08, 0xCD, 0xE3, 0x18, 0xC4, 0x23, 0x18, 0xC4, 0x00, 0x07,\n  0x83, 0x1C, 0x41, 0x98, 0x30, 0x06, 0x01, 0x80, 0x60, 0x38, 0x1C, 0x06,\n  0x01, 0x80, 0x20, 0x0F, 0xF8, 0x0F, 0x86, 0x73, 0x0C, 0x83, 0x00, 0xC0,\n  0x60, 0xE0, 0x06, 0x01, 0xB0, 0x6C, 0x13, 0x8C, 0x7C, 0x00, 0x00, 0x80,\n  0xC0, 0xE0, 0xA0, 0x90, 0x98, 0x8C, 0x86, 0xFF, 0x81, 0x01, 0x80, 0xC0,\n  0x60, 0x0F, 0xC3, 0x00, 0x40, 0x08, 0x03, 0x00, 0x7F, 0x1C, 0x70, 0x06,\n  0x00, 0xC0, 0x1B, 0x06, 0x71, 0x87, 0xE0, 0x0F, 0x86, 0x73, 0x0D, 0x80,\n  0x60, 0x1F, 0xCF, 0x3B, 0x86, 0xC1, 0xB0, 0x6C, 0x33, 0x98, 0x3C, 0x00,\n  0x7F, 0xC0, 0x20, 0x10, 0x0C, 0x06, 0x01, 0x00, 0x80, 0x60, 0x10, 0x0C,\n  0x02, 0x01, 0x80, 0x40, 0x00, 0x0F, 0x86, 0x73, 0x0C, 0xC3, 0x30, 0xCC,\n  0x61, 0xE1, 0x86, 0x41, 0xB0, 0x6C, 0x13, 0x8C, 0x3E, 0x00, 0x0F, 0x06,\n  0x73, 0x0D, 0x83, 0x60, 0xD8, 0x77, 0x3C, 0xFE, 0x01, 0x80, 0x6C, 0x33,\n  0x98, 0x7C, 0x00, 0x30, 0x00, 0x00, 0x00, 0xC0, 0x18, 0x00, 0x00, 0x00,\n  0x0C, 0x62, 0x11, 0x00, 0x00, 0x01, 0xC3, 0x8F, 0x0C, 0x07, 0x00, 0xE0,\n  0x1E, 0x01, 0x00, 0x7F, 0xC0, 0x00, 0x03, 0xFE, 0x40, 0x3C, 0x03, 0x80,\n  0x70, 0x18, 0x78, 0xE1, 0xC0, 0x00, 0x00, 0x1F, 0x30, 0xD0, 0x78, 0x30,\n  0x30, 0x30, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0xFE,\n  0x00, 0xC0, 0xE0, 0xC0, 0x18, 0x61, 0xD3, 0x31, 0x9C, 0xD8, 0xC2, 0x36,\n  0x31, 0x8F, 0x18, 0x67, 0xC6, 0x11, 0xB1, 0x8C, 0xCC, 0x67, 0x63, 0x0E,\n  0xF0, 0x60, 0x00, 0x1C, 0x00, 0x01, 0x81, 0x00, 0x1F, 0xC0, 0x01, 0xC0,\n  0x1C, 0x03, 0xC0, 0x24, 0x06, 0x60, 0x46, 0x0C, 0x61, 0x86, 0x1F, 0xE3,\n  0x06, 0x20, 0x26, 0x03, 0x40, 0x30, 0x1F, 0xE1, 0x87, 0x30, 0x33, 0x03,\n  0x30, 0x23, 0x06, 0x3F, 0xC6, 0x06, 0x60, 0x66, 0x06, 0x60, 0x66, 0x0C,\n  0x7F, 0x80, 0x07, 0xC1, 0x86, 0x30, 0x32, 0x03, 0x60, 0x04, 0x00, 0xC0,\n  0x0C, 0x00, 0xC0, 0x6C, 0x06, 0xC0, 0xC6, 0x18, 0x3E, 0x00, 0x1F, 0xE0,\n  0xC1, 0x84, 0x06, 0x60, 0x33, 0x01, 0x98, 0x0C, 0x80, 0x64, 0x02, 0x60,\n  0x33, 0x01, 0x98, 0x18, 0x81, 0x87, 0xF0, 0x00, 0x1F, 0xF1, 0x80, 0x10,\n  0x03, 0x00, 0x30, 0x03, 0x00, 0x3F, 0xE2, 0x00, 0x60, 0x06, 0x00, 0x60,\n  0x04, 0x00, 0x7F, 0xC0, 0x1F, 0xF1, 0x80, 0x10, 0x03, 0x00, 0x30, 0x03,\n  0x00, 0x3F, 0xC2, 0x00, 0x60, 0x06, 0x00, 0x60, 0x04, 0x00, 0x40, 0x00,\n  0x07, 0xE0, 0xE1, 0x8C, 0x06, 0xC0, 0x36, 0x00, 0x60, 0x03, 0x07, 0xF8,\n  0x02, 0xC0, 0x36, 0x01, 0x98, 0x1C, 0xE1, 0xC1, 0xF2, 0x00, 0x18, 0x08,\n  0xC0, 0xC4, 0x06, 0x60, 0x33, 0x01, 0x18, 0x18, 0xFF, 0xC4, 0x06, 0x60,\n  0x23, 0x01, 0x18, 0x18, 0x80, 0xC4, 0x06, 0x00, 0x33, 0x32, 0x26, 0x66,\n  0x44, 0xCC, 0xC0, 0x00, 0xC0, 0x60, 0x18, 0x06, 0x01, 0x80, 0x60, 0x30,\n  0x0C, 0x03, 0x30, 0xCC, 0x63, 0x18, 0x7C, 0x00, 0x18, 0x18, 0x60, 0xC1,\n  0x0E, 0x0C, 0x60, 0x33, 0x00, 0xD8, 0x03, 0xF0, 0x0C, 0xC0, 0x61, 0x81,\n  0x86, 0x06, 0x0C, 0x10, 0x30, 0x40, 0x60, 0x18, 0x0C, 0x04, 0x06, 0x03,\n  0x01, 0x80, 0xC0, 0x40, 0x60, 0x30, 0x18, 0x08, 0x07, 0xF8, 0x18, 0x06,\n  0x18, 0x0E, 0x18, 0x0E, 0x34, 0x1E, 0x34, 0x36, 0x34, 0x34, 0x24, 0x64,\n  0x24, 0x6C, 0x64, 0xCC, 0x64, 0x8C, 0x65, 0x88, 0x43, 0x08, 0x43, 0x18,\n  0x18, 0x08, 0xE0, 0x47, 0x06, 0x6C, 0x33, 0x61, 0x99, 0x08, 0x8C, 0xC4,\n  0x66, 0x61, 0xB3, 0x0D, 0x18, 0x38, 0x81, 0xC4, 0x06, 0x00, 0x07, 0xC0,\n  0xC3, 0x8C, 0x0E, 0xC0, 0x36, 0x01, 0xE0, 0x0F, 0x00, 0x78, 0x03, 0xC0,\n  0x36, 0x01, 0xB8, 0x18, 0xE1, 0x81, 0xF0, 0x00, 0x1F, 0xE1, 0x83, 0x10,\n  0x33, 0x03, 0x30, 0x33, 0x06, 0x3F, 0xC2, 0x00, 0x60, 0x06, 0x00, 0x60,\n  0x04, 0x00, 0x40, 0x00, 0x07, 0xC0, 0xC3, 0x8C, 0x0E, 0xC0, 0x36, 0x01,\n  0xE0, 0x0F, 0x00, 0x78, 0x03, 0xC0, 0x36, 0x09, 0xB8, 0x78, 0xE3, 0x81,\n  0xF6, 0x00, 0x10, 0x1F, 0xF0, 0xC0, 0xC4, 0x06, 0x60, 0x33, 0x01, 0x18,\n  0x18, 0xFF, 0x04, 0x0C, 0x60, 0x63, 0x03, 0x18, 0x18, 0x80, 0xC4, 0x06,\n  0x00, 0x07, 0xC1, 0x87, 0x30, 0x33, 0x03, 0x30, 0x03, 0xC0, 0x0F, 0xC0,\n  0x1E, 0x00, 0x6C, 0x06, 0xC0, 0x46, 0x0C, 0x3F, 0x00, 0xFF, 0xC3, 0x00,\n  0xC0, 0x20, 0x18, 0x06, 0x01, 0x80, 0x60, 0x10, 0x0C, 0x03, 0x00, 0xC0,\n  0x20, 0x00, 0x30, 0x13, 0x03, 0x20, 0x36, 0x03, 0x60, 0x26, 0x06, 0x60,\n  0x64, 0x06, 0xC0, 0x6C, 0x04, 0xC0, 0xCE, 0x18, 0x3E, 0x00, 0xC0, 0x78,\n  0x0B, 0x03, 0x20, 0xC4, 0x18, 0xC6, 0x18, 0x83, 0x30, 0x64, 0x0D, 0x80,\n  0xA0, 0x1C, 0x03, 0x00, 0xC1, 0x83, 0xC1, 0x83, 0xC3, 0x86, 0xC2, 0x86,\n  0xC6, 0x84, 0xC4, 0x8C, 0xCC, 0xC8, 0xC8, 0xD8, 0xD8, 0xD0, 0xD0, 0xF0,\n  0x70, 0xE0, 0x60, 0xE0, 0x60, 0xE0, 0x0C, 0x0C, 0x30, 0x60, 0x63, 0x01,\n  0x98, 0x02, 0xC0, 0x0E, 0x00, 0x38, 0x01, 0xE0, 0x0C, 0x80, 0x33, 0x01,\n  0x8C, 0x0C, 0x18, 0x60, 0x60, 0xC0, 0x66, 0x0C, 0x60, 0xC2, 0x18, 0x33,\n  0x03, 0x60, 0x1C, 0x01, 0x80, 0x18, 0x01, 0x80, 0x18, 0x01, 0x00, 0x30,\n  0x00, 0x1F, 0xF0, 0x07, 0x00, 0xE0, 0x0C, 0x01, 0x80, 0x30, 0x06, 0x00,\n  0xC0, 0x18, 0x03, 0x00, 0x60, 0x0C, 0x00, 0xFF, 0xC0, 0x0E, 0x10, 0x20,\n  0x41, 0x02, 0x04, 0x08, 0x20, 0x40, 0x81, 0x04, 0x08, 0x10, 0x20, 0xE0,\n  0xAA, 0xA9, 0x55, 0x40, 0x0E, 0x08, 0x10, 0x20, 0x41, 0x02, 0x04, 0x08,\n  0x20, 0x40, 0x81, 0x04, 0x08, 0x10, 0xE0, 0x0C, 0x18, 0x51, 0xA2, 0x4C,\n  0x50, 0x80, 0xFF, 0xE0, 0xC8, 0x80, 0x0F, 0x86, 0x33, 0x0C, 0x03, 0x03,\n  0xDF, 0xEE, 0x0B, 0x02, 0xC1, 0x9F, 0xE0, 0x10, 0x04, 0x01, 0x00, 0xDC,\n  0x39, 0x88, 0x32, 0x0D, 0x83, 0x40, 0xD0, 0x64, 0x1B, 0x8C, 0xBC, 0x00,\n  0x1F, 0x18, 0xD8, 0x6C, 0x0C, 0x06, 0x03, 0x01, 0x86, 0x66, 0x3E, 0x00,\n  0x00, 0x20, 0x08, 0x01, 0x0F, 0x23, 0x14, 0xC1, 0x18, 0x26, 0x04, 0xC0,\n  0x98, 0x23, 0x04, 0x71, 0x87, 0xD0, 0x0F, 0x0C, 0x76, 0x0D, 0x83, 0xFF,\n  0xF0, 0x0C, 0x03, 0x06, 0x63, 0x0F, 0x80, 0x1C, 0xC2, 0x1E, 0x20, 0x84,\n  0x10, 0x41, 0x04, 0x20, 0x80, 0x0F, 0x46, 0x33, 0x0C, 0xC1, 0x60, 0xD8,\n  0x26, 0x09, 0x86, 0x71, 0x8F, 0xE0, 0x10, 0x04, 0xC2, 0x1F, 0x00, 0x10,\n  0x04, 0x01, 0x00, 0x9F, 0x39, 0x88, 0x22, 0x09, 0x02, 0x40, 0x90, 0x44,\n  0x12, 0x04, 0x81, 0x00, 0x10, 0x02, 0x22, 0x64, 0x44, 0x48, 0x80, 0x04,\n  0x00, 0x01, 0x08, 0x20, 0x82, 0x08, 0x41, 0x04, 0x10, 0x42, 0x08, 0xE0,\n  0x10, 0x08, 0x04, 0x04, 0x32, 0x31, 0x20, 0xA0, 0xB8, 0x6C, 0x22, 0x11,\n  0x90, 0xC8, 0x30, 0x11, 0x22, 0x22, 0x64, 0x44, 0x48, 0x80, 0x2F, 0x3C,\n  0x63, 0x8C, 0x86, 0x19, 0x08, 0x44, 0x10, 0x88, 0x21, 0x10, 0x82, 0x21,\n  0x04, 0x82, 0x11, 0x04, 0x20, 0x00, 0x0B, 0xF3, 0x18, 0x82, 0x20, 0x90,\n  0x24, 0x09, 0x04, 0x41, 0x20, 0x48, 0x10, 0x0F, 0x0C, 0x76, 0x0D, 0x83,\n  0xC0, 0xF0, 0x3C, 0x1B, 0x06, 0xE3, 0x0F, 0x00, 0x17, 0xC3, 0x1C, 0x41,\n  0x98, 0x32, 0x06, 0x40, 0xC8, 0x33, 0x06, 0x71, 0x8B, 0xC1, 0x00, 0x20,\n  0x08, 0x01, 0x00, 0x00, 0x1E, 0xCC, 0x66, 0x09, 0x82, 0xC0, 0xB0, 0x4C,\n  0x13, 0x04, 0x63, 0x0F, 0xC0, 0x20, 0x08, 0x02, 0x00, 0x80, 0x2C, 0x60,\n  0x81, 0x04, 0x08, 0x10, 0x20, 0x81, 0x00, 0x1E, 0x33, 0x63, 0x60, 0x70,\n  0x1E, 0x03, 0xC3, 0xC6, 0x7C, 0x22, 0xF2, 0x44, 0x44, 0xCC, 0xCE, 0x21,\n  0x20, 0x90, 0x48, 0x24, 0x12, 0x13, 0x09, 0x84, 0xE6, 0x3E, 0x00, 0xC1,\n  0xE1, 0xB0, 0xC8, 0xC4, 0x43, 0x61, 0xA0, 0xF0, 0x70, 0x18, 0x00, 0xC7,\n  0x1E, 0x38, 0xB3, 0xCD, 0x96, 0x4C, 0xB6, 0x6D, 0xB1, 0x4D, 0x0E, 0x78,\n  0x63, 0x83, 0x1C, 0x00, 0x10, 0xC3, 0x10, 0x24, 0x07, 0x80, 0xE0, 0x1C,\n  0x07, 0x81, 0x90, 0x23, 0x08, 0x20, 0x30, 0x46, 0x18, 0x42, 0x08, 0xC1,\n  0x10, 0x24, 0x07, 0x80, 0xE0, 0x1C, 0x03, 0x00, 0x60, 0x08, 0x03, 0x01,\n  0xC0, 0x00, 0x3F, 0x80, 0x80, 0x80, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0,\n  0x7F, 0x00, 0x18, 0x88, 0x42, 0x10, 0x88, 0xC3, 0x18, 0x88, 0x42, 0x18,\n  0xE0, 0x11, 0x22, 0x22, 0x24, 0x44, 0x4C, 0x88, 0x88, 0x00, 0x38, 0xC2,\n  0x10, 0x88, 0xC6, 0x18, 0x88, 0x42, 0x10, 0x88, 0xC0, 0x70, 0x4E, 0x41,\n  0xC0 };\n\nconst GFXglyph FreeSansOblique9pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,   5,    0,    1 },   // 0x20 ' '\n  {     0,   5,  13,   5,    2,  -12 },   // 0x21 '!'\n  {     9,   5,   4,   6,    3,  -12 },   // 0x22 '\"'\n  {    12,  11,  13,  10,    1,  -12 },   // 0x23 '#'\n  {    30,  11,  16,  10,    1,  -13 },   // 0x24 '$'\n  {    52,  15,  13,  16,    2,  -12 },   // 0x25 '%'\n  {    77,  10,  13,  12,    2,  -12 },   // 0x26 '&'\n  {    94,   2,   4,   3,    3,  -12 },   // 0x27 '''\n  {    95,   7,  17,   6,    2,  -12 },   // 0x28 '('\n  {   110,   7,  17,   6,   -1,  -12 },   // 0x29 ')'\n  {   125,   6,   5,   7,    3,  -12 },   // 0x2A '*'\n  {   129,   9,   8,  11,    2,   -7 },   // 0x2B '+'\n  {   138,   3,   5,   5,    1,   -1 },   // 0x2C ','\n  {   140,   4,   1,   6,    2,   -4 },   // 0x2D '-'\n  {   141,   2,   1,   5,    2,    0 },   // 0x2E '.'\n  {   142,   8,  13,   5,    0,  -12 },   // 0x2F '/'\n  {   155,   9,  13,  10,    2,  -12 },   // 0x30 '0'\n  {   170,   5,  13,  10,    4,  -12 },   // 0x31 '1'\n  {   179,  11,  13,  10,    1,  -12 },   // 0x32 '2'\n  {   197,  10,  13,  10,    1,  -12 },   // 0x33 '3'\n  {   214,   9,  13,  10,    1,  -12 },   // 0x34 '4'\n  {   229,  11,  13,  10,    1,  -12 },   // 0x35 '5'\n  {   247,  10,  13,  10,    2,  -12 },   // 0x36 '6'\n  {   264,  10,  13,  10,    2,  -12 },   // 0x37 '7'\n  {   281,  10,  13,  10,    1,  -12 },   // 0x38 '8'\n  {   298,  10,  13,  10,    1,  -12 },   // 0x39 '9'\n  {   315,   4,   9,   5,    2,   -8 },   // 0x3A ':'\n  {   320,   5,  12,   5,    1,   -8 },   // 0x3B ';'\n  {   328,   9,   9,  11,    2,   -8 },   // 0x3C '<'\n  {   339,  10,   4,  11,    1,   -5 },   // 0x3D '='\n  {   344,   9,   9,  11,    1,   -7 },   // 0x3E '>'\n  {   355,   9,  13,  10,    3,  -12 },   // 0x3F '?'\n  {   370,  18,  16,  18,    1,  -12 },   // 0x40 '@'\n  {   406,  12,  13,  12,    0,  -12 },   // 0x41 'A'\n  {   426,  12,  13,  12,    1,  -12 },   // 0x42 'B'\n  {   446,  12,  13,  13,    2,  -12 },   // 0x43 'C'\n  {   466,  13,  13,  13,    1,  -12 },   // 0x44 'D'\n  {   488,  12,  13,  12,    1,  -12 },   // 0x45 'E'\n  {   508,  12,  13,  11,    1,  -12 },   // 0x46 'F'\n  {   528,  13,  13,  14,    2,  -12 },   // 0x47 'G'\n  {   550,  13,  13,  13,    1,  -12 },   // 0x48 'H'\n  {   572,   4,  13,   5,    2,  -12 },   // 0x49 'I'\n  {   579,  10,  13,   9,    1,  -12 },   // 0x4A 'J'\n  {   596,  14,  13,  12,    1,  -12 },   // 0x4B 'K'\n  {   619,   9,  13,  10,    1,  -12 },   // 0x4C 'L'\n  {   634,  16,  13,  15,    1,  -12 },   // 0x4D 'M'\n  {   660,  13,  13,  13,    1,  -12 },   // 0x4E 'N'\n  {   682,  13,  13,  14,    2,  -12 },   // 0x4F 'O'\n  {   704,  12,  13,  12,    1,  -12 },   // 0x50 'P'\n  {   724,  13,  14,  14,    2,  -12 },   // 0x51 'Q'\n  {   747,  13,  13,  13,    1,  -12 },   // 0x52 'R'\n  {   769,  12,  13,  12,    1,  -12 },   // 0x53 'S'\n  {   789,  10,  13,  11,    3,  -12 },   // 0x54 'T'\n  {   806,  12,  13,  13,    2,  -12 },   // 0x55 'U'\n  {   826,  11,  13,  12,    3,  -12 },   // 0x56 'V'\n  {   844,  16,  13,  17,    3,  -12 },   // 0x57 'W'\n  {   870,  14,  13,  12,    0,  -12 },   // 0x58 'X'\n  {   893,  12,  13,  12,    3,  -12 },   // 0x59 'Y'\n  {   913,  12,  13,  11,    1,  -12 },   // 0x5A 'Z'\n  {   933,   7,  17,   5,    0,  -12 },   // 0x5B '['\n  {   948,   2,  13,   5,    3,  -12 },   // 0x5C '\\'\n  {   952,   7,  17,   5,    0,  -12 },   // 0x5D ']'\n  {   967,   7,   7,   8,    2,  -12 },   // 0x5E '^'\n  {   974,  11,   1,  10,   -1,    3 },   // 0x5F '_'\n  {   976,   3,   3,   6,    3,  -12 },   // 0x60 '`'\n  {   978,  10,  10,  10,    1,   -9 },   // 0x61 'a'\n  {   991,  10,  13,  10,    1,  -12 },   // 0x62 'b'\n  {  1008,   9,  10,   9,    1,   -9 },   // 0x63 'c'\n  {  1020,  11,  13,  10,    1,  -12 },   // 0x64 'd'\n  {  1038,  10,  10,  10,    1,   -9 },   // 0x65 'e'\n  {  1051,   6,  13,   5,    1,  -12 },   // 0x66 'f'\n  {  1061,  10,  14,  10,    0,   -9 },   // 0x67 'g'\n  {  1079,  10,  13,  10,    1,  -12 },   // 0x68 'h'\n  {  1096,   4,  13,   4,    1,  -12 },   // 0x69 'i'\n  {  1103,   6,  17,   4,   -1,  -12 },   // 0x6A 'j'\n  {  1116,   9,  13,   9,    1,  -12 },   // 0x6B 'k'\n  {  1131,   4,  13,   4,    1,  -12 },   // 0x6C 'l'\n  {  1138,  15,  10,  15,    1,   -9 },   // 0x6D 'm'\n  {  1157,  10,  11,  10,    1,  -10 },   // 0x6E 'n'\n  {  1171,  10,  10,  10,    1,   -9 },   // 0x6F 'o'\n  {  1184,  11,  14,  10,    0,   -9 },   // 0x70 'p'\n  {  1204,  10,  14,  10,    1,   -9 },   // 0x71 'q'\n  {  1222,   7,  10,   6,    1,   -9 },   // 0x72 'r'\n  {  1231,   8,  10,   9,    1,   -9 },   // 0x73 's'\n  {  1241,   4,  12,   5,    2,  -11 },   // 0x74 't'\n  {  1247,   9,  10,  10,    2,   -9 },   // 0x75 'u'\n  {  1259,   9,  10,   9,    2,   -9 },   // 0x76 'v'\n  {  1271,  13,  10,  13,    2,   -9 },   // 0x77 'w'\n  {  1288,  11,  10,   9,    0,   -9 },   // 0x78 'x'\n  {  1302,  11,  14,   9,    0,   -9 },   // 0x79 'y'\n  {  1322,   9,  10,   9,    1,   -9 },   // 0x7A 'z'\n  {  1334,   5,  17,   6,    2,  -12 },   // 0x7B '{'\n  {  1345,   4,  17,   5,    1,  -12 },   // 0x7C '|'\n  {  1354,   5,  17,   6,    0,  -12 },   // 0x7D '}'\n  {  1365,   9,   3,  11,    2,   -7 } }; // 0x7E '~'\n\nconst GFXfont FreeSansOblique9pt7b PROGMEM = {\n  (uint8_t  *)FreeSansOblique9pt7bBitmaps,\n  (GFXglyph *)FreeSansOblique9pt7bGlyphs,\n  0x20, 0x7E, 22 };\n\n// Approx. 2041 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeSerif12pt7b.h",
    "content": "const uint8_t FreeSerif12pt7bBitmaps[] PROGMEM = {\n  0xFF, 0xFE, 0xA8, 0x3F, 0xCF, 0x3C, 0xF3, 0x8A, 0x20, 0x0C, 0x40, 0xC4,\n  0x08, 0x40, 0x8C, 0x08, 0xC7, 0xFF, 0x18, 0x81, 0x88, 0x10, 0x81, 0x08,\n  0xFF, 0xE1, 0x18, 0x31, 0x03, 0x10, 0x31, 0x02, 0x10, 0x04, 0x07, 0xC6,\n  0x5B, 0x12, 0xC4, 0xB1, 0x0F, 0x41, 0xF0, 0x1E, 0x01, 0xE0, 0x58, 0x13,\n  0x84, 0xE1, 0x3C, 0x4F, 0x96, 0x3F, 0x01, 0x00, 0x00, 0x04, 0x03, 0x83,\n  0x03, 0x9F, 0x81, 0xC2, 0x20, 0x60, 0x90, 0x38, 0x24, 0x0C, 0x12, 0x03,\n  0x0D, 0x00, 0xC6, 0x47, 0x9E, 0x23, 0x10, 0x09, 0x84, 0x04, 0xE1, 0x03,\n  0x30, 0x40, 0x8C, 0x20, 0x43, 0x08, 0x10, 0xC4, 0x08, 0x1E, 0x00, 0x03,\n  0xC0, 0x02, 0x30, 0x03, 0x08, 0x01, 0x84, 0x00, 0xC4, 0x00, 0x7C, 0xF8,\n  0x1C, 0x38, 0x1E, 0x08, 0x33, 0x0C, 0x31, 0xC4, 0x10, 0x74, 0x18, 0x3A,\n  0x0C, 0x0E, 0x07, 0x03, 0x83, 0xC3, 0xE2, 0x7E, 0x3E, 0xFF, 0xA0, 0x04,\n  0x21, 0x08, 0x61, 0x0C, 0x30, 0xC3, 0x0C, 0x30, 0xC1, 0x04, 0x18, 0x20,\n  0x40, 0x81, 0x81, 0x02, 0x04, 0x18, 0x20, 0x83, 0x0C, 0x30, 0xC3, 0x0C,\n  0x30, 0x86, 0x10, 0x84, 0x20, 0x30, 0xB3, 0xD7, 0x54, 0x38, 0x7C, 0xD3,\n  0x30, 0x30, 0x10, 0x04, 0x00, 0x80, 0x10, 0x02, 0x00, 0x41, 0xFF, 0xC1,\n  0x00, 0x20, 0x04, 0x00, 0x80, 0x10, 0x00, 0xDF, 0x95, 0x00, 0xFC, 0xFC,\n  0x06, 0x0C, 0x10, 0x60, 0xC1, 0x06, 0x0C, 0x10, 0x60, 0xC1, 0x06, 0x0C,\n  0x10, 0x60, 0xC0, 0x1E, 0x0C, 0xC6, 0x19, 0x86, 0xC0, 0xB0, 0x3C, 0x0F,\n  0x03, 0xC0, 0xF0, 0x3C, 0x0F, 0x03, 0xC0, 0xD8, 0x66, 0x18, 0xCC, 0x1E,\n  0x00, 0x11, 0xC3, 0x0C, 0x30, 0xC3, 0x0C, 0x30, 0xC3, 0x0C, 0x30, 0xC3,\n  0x0C, 0xFC, 0x1E, 0x18, 0xC4, 0x1A, 0x06, 0x01, 0x80, 0x60, 0x10, 0x0C,\n  0x02, 0x01, 0x00, 0xC0, 0x60, 0x30, 0x18, 0x1F, 0xF8, 0x1E, 0x18, 0xE8,\n  0x18, 0x06, 0x01, 0x00, 0x80, 0xF0, 0x7E, 0x03, 0xC0, 0x70, 0x0C, 0x03,\n  0x00, 0xC0, 0x6E, 0x11, 0xF8, 0x01, 0x00, 0xC0, 0x70, 0x2C, 0x0B, 0x04,\n  0xC2, 0x30, 0x8C, 0x43, 0x20, 0xC8, 0x33, 0xFF, 0x03, 0x00, 0xC0, 0x30,\n  0x0C, 0x00, 0x03, 0xF1, 0x00, 0x40, 0x18, 0x0F, 0x80, 0xF8, 0x0E, 0x01,\n  0xC0, 0x30, 0x0C, 0x03, 0x00, 0xC0, 0x20, 0x1B, 0x8C, 0x7C, 0x00, 0x01,\n  0xC3, 0xC1, 0xC0, 0xC0, 0x70, 0x18, 0x0E, 0xF3, 0xCE, 0xC1, 0xF0, 0x3C,\n  0x0F, 0x03, 0xC0, 0xD8, 0x36, 0x08, 0xC6, 0x1E, 0x00, 0x3F, 0xD0, 0x38,\n  0x08, 0x06, 0x01, 0x80, 0x40, 0x10, 0x0C, 0x02, 0x00, 0x80, 0x20, 0x10,\n  0x04, 0x01, 0x00, 0x80, 0x20, 0x1F, 0x18, 0x6C, 0x0F, 0x03, 0xC0, 0xF8,\n  0x67, 0x30, 0xF0, 0x1E, 0x09, 0xE6, 0x3B, 0x07, 0xC0, 0xF0, 0x3C, 0x0D,\n  0x86, 0x1F, 0x00, 0x1E, 0x08, 0xC6, 0x1B, 0x02, 0xC0, 0xF0, 0x3C, 0x0F,\n  0x03, 0xE0, 0xDC, 0x73, 0xEC, 0x06, 0x01, 0x80, 0xC0, 0x70, 0x38, 0x38,\n  0x18, 0x00, 0xFC, 0x00, 0x3F, 0xCC, 0xC0, 0x00, 0x00, 0x06, 0x77, 0x12,\n  0x40, 0x00, 0x00, 0x07, 0x01, 0xE0, 0x78, 0x1E, 0x07, 0x00, 0xC0, 0x0F,\n  0x00, 0x3C, 0x00, 0xF0, 0x03, 0xC0, 0x07, 0x00, 0x10, 0xFF, 0xF0, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0x0F, 0xFF, 0x80, 0x0E, 0x00, 0x3C, 0x00, 0xF0,\n  0x03, 0xC0, 0x0F, 0x00, 0x30, 0x0E, 0x07, 0x81, 0xE0, 0x78, 0x0E, 0x00,\n  0x00, 0x00, 0x7C, 0x86, 0x83, 0xC3, 0x03, 0x03, 0x06, 0x0C, 0x08, 0x08,\n  0x10, 0x10, 0x00, 0x00, 0x30, 0x30, 0x30, 0x03, 0xF0, 0x06, 0x06, 0x06,\n  0x00, 0x86, 0x00, 0x26, 0x0E, 0xD3, 0x0C, 0xC7, 0x0C, 0x63, 0x84, 0x31,\n  0xC6, 0x18, 0xE3, 0x08, 0x71, 0x8C, 0x4C, 0xC6, 0x46, 0x3D, 0xC1, 0x80,\n  0x00, 0x30, 0x10, 0x07, 0xF0, 0x00, 0x80, 0x00, 0x60, 0x00, 0x70, 0x00,\n  0x38, 0x00, 0x2E, 0x00, 0x13, 0x00, 0x19, 0xC0, 0x08, 0x60, 0x04, 0x38,\n  0x04, 0x0C, 0x03, 0xFF, 0x03, 0x03, 0x81, 0x00, 0xE1, 0x80, 0x70, 0xC0,\n  0x3D, 0xF0, 0x3F, 0xFF, 0x83, 0x0C, 0x30, 0x63, 0x06, 0x30, 0x63, 0x06,\n  0x30, 0xC3, 0xF0, 0x30, 0xE3, 0x06, 0x30, 0x33, 0x03, 0x30, 0x33, 0x07,\n  0x30, 0xEF, 0xFC, 0x07, 0xE2, 0x38, 0x3C, 0xC0, 0x3B, 0x00, 0x36, 0x00,\n  0x38, 0x00, 0x30, 0x00, 0x60, 0x00, 0xC0, 0x01, 0x80, 0x03, 0x00, 0x03,\n  0x00, 0x06, 0x00, 0x06, 0x00, 0x47, 0x03, 0x03, 0xF8, 0xFF, 0xC0, 0x30,\n  0x78, 0x30, 0x1C, 0x30, 0x0E, 0x30, 0x06, 0x30, 0x03, 0x30, 0x03, 0x30,\n  0x03, 0x30, 0x03, 0x30, 0x03, 0x30, 0x03, 0x30, 0x06, 0x30, 0x06, 0x30,\n  0x0C, 0x30, 0x78, 0xFF, 0xC0, 0xFF, 0xFC, 0xC0, 0x33, 0x00, 0x4C, 0x00,\n  0x30, 0x00, 0xC0, 0x43, 0x03, 0x0F, 0xFC, 0x30, 0x30, 0xC0, 0x43, 0x00,\n  0x0C, 0x00, 0x30, 0x08, 0xC0, 0x23, 0x03, 0xBF, 0xFE, 0xFF, 0xFC, 0xC0,\n  0x33, 0x00, 0x4C, 0x00, 0x30, 0x00, 0xC0, 0x43, 0x03, 0x0F, 0xFC, 0x30,\n  0x30, 0xC0, 0x43, 0x00, 0x0C, 0x00, 0x30, 0x00, 0xC0, 0x03, 0x00, 0x3F,\n  0x00, 0x07, 0xE4, 0x1C, 0x3C, 0x30, 0x0C, 0x60, 0x0C, 0x60, 0x04, 0xC0,\n  0x00, 0xC0, 0x00, 0xC0, 0x3F, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0x60,\n  0x0C, 0x60, 0x0C, 0x30, 0x0C, 0x1C, 0x1C, 0x07, 0xE0, 0xFC, 0x3F, 0x30,\n  0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x3F,\n  0xFC, 0x30, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x30,\n  0x0C, 0x30, 0x0C, 0xFC, 0x3F, 0xFC, 0xC3, 0x0C, 0x30, 0xC3, 0x0C, 0x30,\n  0xC3, 0x0C, 0x30, 0xC3, 0x3F, 0x3F, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C,\n  0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0xC8, 0xF0, 0xFC, 0xFE, 0x30,\n  0x38, 0x30, 0x20, 0x30, 0x40, 0x30, 0x80, 0x33, 0x00, 0x36, 0x00, 0x3E,\n  0x00, 0x37, 0x00, 0x33, 0x80, 0x31, 0xC0, 0x30, 0xE0, 0x30, 0x70, 0x30,\n  0x38, 0x30, 0x3C, 0xFC, 0x7F, 0xFC, 0x00, 0x60, 0x00, 0xC0, 0x01, 0x80,\n  0x03, 0x00, 0x06, 0x00, 0x0C, 0x00, 0x18, 0x00, 0x30, 0x00, 0x60, 0x00,\n  0xC0, 0x01, 0x80, 0x03, 0x00, 0x26, 0x00, 0x8C, 0x07, 0x7F, 0xFE, 0xF8,\n  0x01, 0xE7, 0x00, 0x70, 0xE0, 0x0E, 0x1E, 0x03, 0xC2, 0xC0, 0x58, 0x5C,\n  0x1B, 0x09, 0x82, 0x61, 0x38, 0x4C, 0x27, 0x11, 0x84, 0x72, 0x30, 0x8E,\n  0xC6, 0x10, 0xD0, 0xC2, 0x1E, 0x18, 0x41, 0x83, 0x1C, 0x30, 0x67, 0xC4,\n  0x3F, 0xF0, 0x1F, 0x78, 0x0E, 0x3C, 0x04, 0x3E, 0x04, 0x2E, 0x04, 0x27,\n  0x04, 0x23, 0x84, 0x23, 0xC4, 0x21, 0xE4, 0x20, 0xE4, 0x20, 0x74, 0x20,\n  0x3C, 0x20, 0x1C, 0x20, 0x0C, 0x70, 0x0C, 0xF8, 0x04, 0x07, 0xC0, 0x30,\n  0x60, 0xC0, 0x63, 0x00, 0x66, 0x00, 0xD8, 0x00, 0xF0, 0x01, 0xE0, 0x03,\n  0xC0, 0x07, 0x80, 0x0F, 0x00, 0x1B, 0x00, 0x66, 0x00, 0xC6, 0x03, 0x06,\n  0x0C, 0x03, 0xE0, 0xFF, 0x83, 0x0E, 0x30, 0x73, 0x03, 0x30, 0x33, 0x03,\n  0x30, 0x63, 0x0E, 0x3F, 0x83, 0x00, 0x30, 0x03, 0x00, 0x30, 0x03, 0x00,\n  0x30, 0x0F, 0xC0, 0x0F, 0xE0, 0x18, 0x30, 0x30, 0x18, 0x60, 0x0C, 0x60,\n  0x0C, 0xC0, 0x06, 0xC0, 0x06, 0xC0, 0x06, 0xC0, 0x06, 0xC0, 0x06, 0xC0,\n  0x06, 0x60, 0x0C, 0x60, 0x0C, 0x30, 0x18, 0x18, 0x30, 0x07, 0xC0, 0x03,\n  0xC0, 0x01, 0xE0, 0x00, 0x78, 0x00, 0x1F, 0xFF, 0x80, 0x61, 0xC0, 0xC1,\n  0xC1, 0x81, 0x83, 0x03, 0x06, 0x06, 0x0C, 0x1C, 0x18, 0x70, 0x3F, 0x80,\n  0x67, 0x00, 0xC7, 0x01, 0x8F, 0x03, 0x0F, 0x06, 0x0E, 0x0C, 0x0E, 0x7E,\n  0x0F, 0x1F, 0x46, 0x19, 0x81, 0x30, 0x27, 0x02, 0xF0, 0x0F, 0x00, 0xF8,\n  0x07, 0xC0, 0x38, 0x03, 0xC0, 0x34, 0x06, 0x80, 0xDC, 0x32, 0x7C, 0xFF,\n  0xFF, 0x86, 0x0E, 0x0C, 0x1C, 0x18, 0x10, 0x30, 0x00, 0x60, 0x00, 0xC0,\n  0x01, 0x80, 0x03, 0x00, 0x06, 0x00, 0x0C, 0x00, 0x18, 0x00, 0x30, 0x00,\n  0x60, 0x00, 0xC0, 0x07, 0xE0, 0xFC, 0x1F, 0x30, 0x0E, 0x30, 0x04, 0x30,\n  0x04, 0x30, 0x04, 0x30, 0x04, 0x30, 0x04, 0x30, 0x04, 0x30, 0x04, 0x30,\n  0x04, 0x30, 0x04, 0x30, 0x04, 0x30, 0x04, 0x18, 0x08, 0x1C, 0x18, 0x07,\n  0xE0, 0xFE, 0x0F, 0x9C, 0x03, 0x0E, 0x01, 0x83, 0x00, 0x81, 0xC0, 0x40,\n  0x60, 0x40, 0x38, 0x20, 0x0C, 0x30, 0x07, 0x10, 0x01, 0x98, 0x00, 0xE8,\n  0x00, 0x34, 0x00, 0x1E, 0x00, 0x06, 0x00, 0x03, 0x00, 0x01, 0x00, 0xFC,\n  0xFC, 0x3D, 0xE1, 0xC0, 0x63, 0x83, 0x01, 0x86, 0x0E, 0x04, 0x1C, 0x18,\n  0x10, 0x70, 0x70, 0x80, 0xC3, 0xC2, 0x03, 0x8B, 0x08, 0x06, 0x6E, 0x40,\n  0x1D, 0x19, 0x00, 0x74, 0x78, 0x00, 0xE1, 0xE0, 0x03, 0x83, 0x80, 0x0E,\n  0x0C, 0x00, 0x10, 0x10, 0x00, 0x40, 0x40, 0x7F, 0x1F, 0x9E, 0x03, 0x07,\n  0x03, 0x01, 0xC3, 0x00, 0x71, 0x00, 0x19, 0x00, 0x0F, 0x00, 0x03, 0x80,\n  0x01, 0xE0, 0x01, 0xB0, 0x01, 0x9C, 0x00, 0x87, 0x00, 0x81, 0xC0, 0x80,\n  0xE0, 0xC0, 0x79, 0xF8, 0x7F, 0xFE, 0x1F, 0x78, 0x0C, 0x38, 0x08, 0x1C,\n  0x18, 0x0E, 0x10, 0x06, 0x20, 0x07, 0x60, 0x03, 0xC0, 0x01, 0x80, 0x01,\n  0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x07,\n  0xE0, 0x7F, 0xFB, 0x00, 0xC8, 0x07, 0x20, 0x38, 0x01, 0xC0, 0x07, 0x00,\n  0x38, 0x01, 0xC0, 0x07, 0x00, 0x38, 0x01, 0xC0, 0x0E, 0x00, 0x38, 0x05,\n  0xC0, 0x3E, 0x01, 0xBF, 0xFE, 0xFE, 0x31, 0x8C, 0x63, 0x18, 0xC6, 0x31,\n  0x8C, 0x63, 0x18, 0xC6, 0x31, 0xF0, 0xC1, 0x81, 0x03, 0x06, 0x04, 0x0C,\n  0x18, 0x10, 0x30, 0x60, 0x40, 0xC1, 0x81, 0x03, 0x06, 0xF8, 0xC6, 0x31,\n  0x8C, 0x63, 0x18, 0xC6, 0x31, 0x8C, 0x63, 0x18, 0xC7, 0xF0, 0x0C, 0x07,\n  0x01, 0x60, 0xD8, 0x23, 0x18, 0xC4, 0x1B, 0x06, 0x80, 0xC0, 0xFF, 0xF0,\n  0xC7, 0x0C, 0x30, 0x3E, 0x31, 0x8C, 0x30, 0x0C, 0x03, 0x07, 0xC6, 0x33,\n  0x0C, 0xC3, 0x31, 0xC7, 0xB8, 0x20, 0x38, 0x06, 0x01, 0x80, 0x60, 0x18,\n  0x06, 0xF1, 0xC6, 0x61, 0xD8, 0x36, 0x0D, 0x83, 0x60, 0xD8, 0x26, 0x19,\n  0x84, 0x3E, 0x00, 0x1E, 0x23, 0x63, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xE1,\n  0x72, 0x3C, 0x00, 0x80, 0xE0, 0x18, 0x06, 0x01, 0x80, 0x61, 0xD8, 0x8E,\n  0x61, 0xB0, 0x6C, 0x1B, 0x06, 0xC1, 0xB0, 0x6E, 0x19, 0xCE, 0x3D, 0xC0,\n  0x1E, 0x08, 0xE4, 0x1B, 0xFE, 0xC0, 0x30, 0x0C, 0x03, 0x81, 0x60, 0x9C,\n  0x41, 0xE0, 0x0F, 0x08, 0xC4, 0x06, 0x03, 0x01, 0x81, 0xF0, 0x60, 0x30,\n  0x18, 0x0C, 0x06, 0x03, 0x01, 0x80, 0xC0, 0x60, 0xFC, 0x00, 0x1F, 0x03,\n  0x1F, 0x60, 0xC6, 0x0C, 0x60, 0xC3, 0x18, 0x1F, 0x02, 0x00, 0x40, 0x07,\n  0xFC, 0x40, 0x24, 0x02, 0xC0, 0x2C, 0x04, 0xE0, 0x83, 0xF0, 0x30, 0x1E,\n  0x00, 0xC0, 0x18, 0x03, 0x00, 0x60, 0x0D, 0xE1, 0xCE, 0x30, 0xC6, 0x18,\n  0xC3, 0x18, 0x63, 0x0C, 0x61, 0x8C, 0x31, 0x86, 0x79, 0xE0, 0x31, 0x80,\n  0x00, 0x09, 0xC6, 0x31, 0x8C, 0x63, 0x18, 0xDF, 0x0C, 0x30, 0x00, 0x00,\n  0x31, 0xC3, 0x0C, 0x30, 0xC3, 0x0C, 0x30, 0xC3, 0x0C, 0x30, 0xF2, 0xF0,\n  0x20, 0x1C, 0x01, 0x80, 0x30, 0x06, 0x00, 0xC0, 0x18, 0xFB, 0x08, 0x62,\n  0x0C, 0x81, 0xE0, 0x3E, 0x06, 0xE0, 0xCE, 0x18, 0xC3, 0x0E, 0xF3, 0xE0,\n  0x13, 0x8C, 0x63, 0x18, 0xC6, 0x31, 0x8C, 0x63, 0x18, 0xC6, 0xF8, 0xF7,\n  0x8F, 0x0E, 0x3C, 0xE3, 0x0C, 0x18, 0xC3, 0x06, 0x30, 0xC1, 0x8C, 0x30,\n  0x63, 0x0C, 0x18, 0xC3, 0x06, 0x30, 0xC1, 0x8C, 0x30, 0x67, 0x9E, 0x3C,\n  0xF7, 0x87, 0x18, 0xC3, 0x18, 0x63, 0x0C, 0x61, 0x8C, 0x31, 0x86, 0x30,\n  0xC6, 0x19, 0xE7, 0x80, 0x1E, 0x18, 0xE4, 0x1B, 0x03, 0xC0, 0xF0, 0x3C,\n  0x0F, 0x03, 0x60, 0x9C, 0x41, 0xE0, 0x77, 0x87, 0x18, 0xC3, 0x98, 0x33,\n  0x06, 0x60, 0xCC, 0x19, 0x83, 0x30, 0xC7, 0x10, 0xDC, 0x18, 0x03, 0x00,\n  0x60, 0x0C, 0x07, 0xE0, 0x1E, 0x8C, 0xE6, 0x1B, 0x06, 0xC1, 0xB0, 0x6C,\n  0x1B, 0x06, 0xE1, 0x98, 0xE3, 0xD8, 0x06, 0x01, 0x80, 0x60, 0x18, 0x1F,\n  0x37, 0x7B, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x7C, 0x7B,\n  0x0E, 0x1C, 0x1E, 0x0F, 0x07, 0xC3, 0x87, 0x8A, 0xE0, 0x21, 0x8F, 0x98,\n  0x61, 0x86, 0x18, 0x61, 0x86, 0x19, 0x38, 0xE3, 0x98, 0x66, 0x19, 0x86,\n  0x61, 0x98, 0x66, 0x19, 0x86, 0x61, 0x9C, 0xE3, 0xDC, 0xF8, 0xEE, 0x08,\n  0xC1, 0x18, 0x41, 0x88, 0x32, 0x03, 0x40, 0x68, 0x06, 0x00, 0xC0, 0x10,\n  0x00, 0xF3, 0xE7, 0x61, 0x83, 0x70, 0xC2, 0x30, 0xC2, 0x30, 0xC4, 0x19,\n  0x64, 0x19, 0x68, 0x0E, 0x38, 0x0E, 0x38, 0x0C, 0x30, 0x04, 0x10, 0xFB,\n  0xC6, 0x30, 0x64, 0x0F, 0x00, 0xC0, 0x0C, 0x03, 0xC0, 0x98, 0x21, 0x8C,\n  0x3B, 0xCF, 0x80, 0xF8, 0xEE, 0x08, 0xC1, 0x18, 0x41, 0x88, 0x31, 0x03,\n  0x40, 0x68, 0x06, 0x00, 0xC0, 0x08, 0x02, 0x00, 0x40, 0x10, 0x1E, 0x03,\n  0x80, 0x7F, 0x90, 0xE0, 0x30, 0x18, 0x0E, 0x03, 0x01, 0xC0, 0xE0, 0x30,\n  0x5C, 0x3F, 0xF8, 0x19, 0x8C, 0x63, 0x18, 0xC6, 0x31, 0xB0, 0x63, 0x18,\n  0xC6, 0x31, 0x8C, 0x61, 0x80, 0xFF, 0xFF, 0x80, 0xC3, 0x18, 0xC6, 0x31,\n  0x8C, 0x63, 0x06, 0xC6, 0x31, 0x8C, 0x63, 0x18, 0xCC, 0x00, 0x38, 0x06,\n  0x62, 0x41, 0xC0 };\n\nconst GFXglyph FreeSerif12pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,   6,    0,    1 },   // 0x20 ' '\n  {     0,   2,  16,   8,    3,  -15 },   // 0x21 '!'\n  {     4,   6,   6,  10,    1,  -15 },   // 0x22 '\"'\n  {     9,  12,  16,  12,    0,  -15 },   // 0x23 '#'\n  {    33,  10,  18,  12,    1,  -16 },   // 0x24 '$'\n  {    56,  18,  17,  20,    1,  -16 },   // 0x25 '%'\n  {    95,  17,  16,  19,    1,  -15 },   // 0x26 '&'\n  {   129,   2,   6,   5,    1,  -15 },   // 0x27 '''\n  {   131,   6,  20,   8,    1,  -15 },   // 0x28 '('\n  {   146,   6,  20,   8,    1,  -15 },   // 0x29 ')'\n  {   161,   8,  10,  12,    3,  -14 },   // 0x2A '*'\n  {   171,  11,  11,  14,    1,  -10 },   // 0x2B '+'\n  {   187,   3,   6,   6,    2,   -2 },   // 0x2C ','\n  {   190,   6,   1,   8,    1,   -5 },   // 0x2D '-'\n  {   191,   2,   3,   6,    2,   -2 },   // 0x2E '.'\n  {   192,   7,  17,   7,    0,  -16 },   // 0x2F '/'\n  {   207,  10,  17,  12,    1,  -16 },   // 0x30 '0'\n  {   229,   6,  17,  12,    3,  -16 },   // 0x31 '1'\n  {   242,  10,  15,  12,    1,  -14 },   // 0x32 '2'\n  {   261,  10,  16,  12,    1,  -15 },   // 0x33 '3'\n  {   281,  10,  16,  12,    1,  -15 },   // 0x34 '4'\n  {   301,  10,  17,  12,    1,  -16 },   // 0x35 '5'\n  {   323,  10,  17,  12,    1,  -16 },   // 0x36 '6'\n  {   345,  10,  16,  12,    0,  -15 },   // 0x37 '7'\n  {   365,  10,  17,  12,    1,  -16 },   // 0x38 '8'\n  {   387,  10,  18,  12,    1,  -16 },   // 0x39 '9'\n  {   410,   2,  12,   6,    2,  -11 },   // 0x3A ':'\n  {   413,   4,  15,   6,    2,  -11 },   // 0x3B ';'\n  {   421,  12,  13,  14,    1,  -12 },   // 0x3C '<'\n  {   441,  12,   6,  14,    1,   -8 },   // 0x3D '='\n  {   450,  12,  13,  14,    1,  -11 },   // 0x3E '>'\n  {   470,   8,  17,  11,    2,  -16 },   // 0x3F '?'\n  {   487,  17,  16,  21,    2,  -15 },   // 0x40 '@'\n  {   521,  17,  16,  17,    0,  -15 },   // 0x41 'A'\n  {   555,  12,  16,  15,    1,  -15 },   // 0x42 'B'\n  {   579,  15,  16,  16,    1,  -15 },   // 0x43 'C'\n  {   609,  16,  16,  17,    0,  -15 },   // 0x44 'D'\n  {   641,  14,  16,  15,    0,  -15 },   // 0x45 'E'\n  {   669,  14,  16,  14,    0,  -15 },   // 0x46 'F'\n  {   697,  16,  16,  17,    1,  -15 },   // 0x47 'G'\n  {   729,  16,  16,  17,    0,  -15 },   // 0x48 'H'\n  {   761,   6,  16,   8,    1,  -15 },   // 0x49 'I'\n  {   773,   8,  16,   9,    0,  -15 },   // 0x4A 'J'\n  {   789,  16,  16,  17,    1,  -15 },   // 0x4B 'K'\n  {   821,  15,  16,  15,    0,  -15 },   // 0x4C 'L'\n  {   851,  19,  16,  21,    1,  -15 },   // 0x4D 'M'\n  {   889,  16,  16,  17,    1,  -15 },   // 0x4E 'N'\n  {   921,  15,  16,  17,    1,  -15 },   // 0x4F 'O'\n  {   951,  12,  16,  14,    0,  -15 },   // 0x50 'P'\n  {   975,  16,  20,  17,    1,  -15 },   // 0x51 'Q'\n  {  1015,  15,  16,  16,    0,  -15 },   // 0x52 'R'\n  {  1045,  11,  16,  13,    0,  -15 },   // 0x53 'S'\n  {  1067,  15,  16,  15,    0,  -15 },   // 0x54 'T'\n  {  1097,  16,  16,  17,    1,  -15 },   // 0x55 'U'\n  {  1129,  17,  16,  17,    0,  -15 },   // 0x56 'V'\n  {  1163,  22,  16,  23,    0,  -15 },   // 0x57 'W'\n  {  1207,  17,  16,  17,    0,  -15 },   // 0x58 'X'\n  {  1241,  16,  16,  17,    0,  -15 },   // 0x59 'Y'\n  {  1273,  14,  16,  15,    1,  -15 },   // 0x5A 'Z'\n  {  1301,   5,  20,   8,    2,  -15 },   // 0x5B '['\n  {  1314,   7,  17,   7,    0,  -16 },   // 0x5C '\\'\n  {  1329,   5,  20,   8,    1,  -15 },   // 0x5D ']'\n  {  1342,  10,   9,  11,    1,  -15 },   // 0x5E '^'\n  {  1354,  12,   1,  12,    0,    3 },   // 0x5F '_'\n  {  1356,   5,   4,   6,    0,  -15 },   // 0x60 '`'\n  {  1359,  10,  11,  10,    1,  -10 },   // 0x61 'a'\n  {  1373,  10,  17,  12,    1,  -16 },   // 0x62 'b'\n  {  1395,   8,  11,  11,    1,  -10 },   // 0x63 'c'\n  {  1406,  10,  17,  12,    1,  -16 },   // 0x64 'd'\n  {  1428,  10,  11,  11,    1,  -10 },   // 0x65 'e'\n  {  1442,   9,  17,   9,    0,  -16 },   // 0x66 'f'\n  {  1462,  12,  16,  11,    0,  -10 },   // 0x67 'g'\n  {  1486,  11,  17,  12,    0,  -16 },   // 0x68 'h'\n  {  1510,   5,  16,   7,    0,  -15 },   // 0x69 'i'\n  {  1520,   6,  21,   8,    0,  -15 },   // 0x6A 'j'\n  {  1536,  11,  17,  12,    1,  -16 },   // 0x6B 'k'\n  {  1560,   5,  17,   6,    0,  -16 },   // 0x6C 'l'\n  {  1571,  18,  11,  19,    0,  -10 },   // 0x6D 'm'\n  {  1596,  11,  11,  12,    0,  -10 },   // 0x6E 'n'\n  {  1612,  10,  11,  12,    1,  -10 },   // 0x6F 'o'\n  {  1626,  11,  16,  12,    0,  -10 },   // 0x70 'p'\n  {  1648,  10,  16,  12,    1,  -10 },   // 0x71 'q'\n  {  1668,   8,  11,   8,    0,  -10 },   // 0x72 'r'\n  {  1679,   7,  11,   9,    1,  -10 },   // 0x73 's'\n  {  1689,   6,  13,   7,    1,  -12 },   // 0x74 't'\n  {  1699,  10,  11,  12,    1,  -10 },   // 0x75 'u'\n  {  1713,  11,  11,  11,    0,  -10 },   // 0x76 'v'\n  {  1729,  16,  11,  16,    0,  -10 },   // 0x77 'w'\n  {  1751,  11,  11,  12,    0,  -10 },   // 0x78 'x'\n  {  1767,  11,  16,  11,    0,  -10 },   // 0x79 'y'\n  {  1789,  10,  11,  10,    0,  -10 },   // 0x7A 'z'\n  {  1803,   5,  21,  12,    2,  -16 },   // 0x7B '{'\n  {  1817,   1,  17,   5,    2,  -16 },   // 0x7C '|'\n  {  1820,   5,  21,  12,    5,  -15 },   // 0x7D '}'\n  {  1834,  12,   3,  12,    0,   -6 } }; // 0x7E '~'\n\nconst GFXfont FreeSerif12pt7b PROGMEM = {\n  (uint8_t  *)FreeSerif12pt7bBitmaps,\n  (GFXglyph *)FreeSerif12pt7bGlyphs,\n  0x20, 0x7E, 29 };\n\n// Approx. 2511 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeSerif18pt7b.h",
    "content": "const uint8_t FreeSerif18pt7bBitmaps[] PROGMEM = {\n  0x6F, 0xFF, 0xFF, 0xFE, 0x66, 0x66, 0x66, 0x64, 0x40, 0x00, 0x6F, 0xF6,\n  0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0x46, 0x42, 0x42, 0x42, 0x03, 0x06, 0x01,\n  0x83, 0x00, 0xC1, 0x80, 0x61, 0xC0, 0x30, 0xC0, 0x38, 0x60, 0x18, 0x30,\n  0xFF, 0xFF, 0x7F, 0xFF, 0x83, 0x06, 0x01, 0x86, 0x00, 0xC3, 0x00, 0xC1,\n  0x87, 0xFF, 0xFF, 0xFF, 0xFE, 0x18, 0x30, 0x0C, 0x18, 0x06, 0x18, 0x06,\n  0x0C, 0x03, 0x06, 0x01, 0x83, 0x00, 0xC1, 0x80, 0x60, 0xC0, 0x02, 0x00,\n  0x10, 0x03, 0xE0, 0x64, 0xE6, 0x23, 0x61, 0x1B, 0x08, 0x58, 0x42, 0xE2,\n  0x03, 0x90, 0x1F, 0x80, 0x7E, 0x00, 0xFC, 0x01, 0xF0, 0x0F, 0xC0, 0x4E,\n  0x02, 0x38, 0x10, 0xE0, 0x87, 0x04, 0x3C, 0x21, 0xE1, 0x1B, 0xC9, 0xCF,\n  0xFC, 0x1F, 0x80, 0x10, 0x00, 0x80, 0x07, 0x80, 0x20, 0x0F, 0xF0, 0x70,\n  0x0F, 0x07, 0xD0, 0x0F, 0x02, 0x18, 0x07, 0x01, 0x18, 0x07, 0x00, 0x8C,\n  0x03, 0x80, 0x4C, 0x01, 0x80, 0x44, 0x00, 0xC0, 0x26, 0x00, 0x60, 0x22,\n  0x0F, 0x30, 0x33, 0x1F, 0xCC, 0x73, 0x1E, 0x37, 0xF1, 0x8E, 0x19, 0xE1,\n  0x8E, 0x04, 0x00, 0x86, 0x02, 0x00, 0xC7, 0x01, 0x00, 0xC3, 0x80, 0x80,\n  0x61, 0x80, 0x80, 0x60, 0xC0, 0x40, 0x30, 0x60, 0x40, 0x30, 0x38, 0xE0,\n  0x30, 0x0F, 0xE0, 0x18, 0x03, 0xC0, 0x00, 0x78, 0x00, 0x00, 0x7E, 0x00,\n  0x00, 0x61, 0x80, 0x00, 0x60, 0x60, 0x00, 0x30, 0x30, 0x00, 0x18, 0x18,\n  0x00, 0x0C, 0x0C, 0x00, 0x06, 0x0C, 0x00, 0x03, 0x8E, 0x00, 0x01, 0xCE,\n  0x00, 0x00, 0x7C, 0x3F, 0xC0, 0x38, 0x07, 0x80, 0x3E, 0x03, 0x80, 0x77,\n  0x01, 0x80, 0x73, 0xC0, 0x80, 0xF0, 0xF0, 0xC0, 0x70, 0x7C, 0xC0, 0x78,\n  0x1E, 0x40, 0x3C, 0x07, 0xC0, 0x1E, 0x01, 0xE0, 0x0F, 0x00, 0x78, 0x0F,\n  0xC0, 0xFF, 0x0D, 0xF0, 0xC7, 0xFC, 0x7F, 0xC1, 0xFC, 0x1F, 0x80, 0x3C,\n  0x00, 0xFF, 0xFE, 0x92, 0x40, 0x00, 0x80, 0x80, 0x80, 0x80, 0x80, 0xC0,\n  0xC0, 0x60, 0x70, 0x30, 0x18, 0x1C, 0x0E, 0x07, 0x03, 0x81, 0xC0, 0xE0,\n  0x70, 0x38, 0x0C, 0x06, 0x03, 0x80, 0xC0, 0x60, 0x18, 0x0C, 0x03, 0x00,\n  0xC0, 0x30, 0x0C, 0x80, 0x30, 0x0C, 0x03, 0x00, 0xC0, 0x60, 0x18, 0x0C,\n  0x07, 0x01, 0x80, 0xC0, 0x70, 0x38, 0x1C, 0x0E, 0x07, 0x03, 0x81, 0xC0,\n  0xE0, 0x60, 0x30, 0x38, 0x18, 0x0C, 0x0C, 0x04, 0x04, 0x04, 0x04, 0x04,\n  0x00, 0x0C, 0x00, 0xC0, 0x0C, 0x0C, 0x46, 0xE4, 0xF7, 0x5E, 0x1F, 0x00,\n  0xC0, 0x17, 0x8E, 0x4E, 0xE4, 0xFC, 0xC6, 0x0C, 0x00, 0xC0, 0x01, 0x80,\n  0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80,\n  0x01, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80,\n  0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x6F, 0xFF,\n  0x11, 0x24, 0x80, 0xFF, 0xFF, 0x6F, 0xF6, 0x00, 0xC0, 0x60, 0x18, 0x06,\n  0x03, 0x80, 0xC0, 0x30, 0x1C, 0x06, 0x01, 0x80, 0xE0, 0x30, 0x0C, 0x07,\n  0x01, 0x80, 0x60, 0x38, 0x0C, 0x03, 0x01, 0xC0, 0x60, 0x18, 0x0E, 0x03,\n  0x00, 0x03, 0xE0, 0x0E, 0x70, 0x1C, 0x38, 0x38, 0x1C, 0x38, 0x1C, 0x78,\n  0x1E, 0x70, 0x0E, 0xF0, 0x0F, 0xF0, 0x0F, 0xF0, 0x0F, 0xF0, 0x0F, 0xF0,\n  0x0F, 0xF0, 0x0F, 0xF0, 0x0F, 0xF0, 0x0F, 0xF0, 0x0F, 0x70, 0x0E, 0x70,\n  0x0E, 0x78, 0x1E, 0x38, 0x1C, 0x38, 0x1C, 0x1C, 0x38, 0x0C, 0x30, 0x03,\n  0xC0, 0x06, 0x03, 0x83, 0xE3, 0x38, 0x0E, 0x03, 0x80, 0xE0, 0x38, 0x0E,\n  0x03, 0x80, 0xE0, 0x38, 0x0E, 0x03, 0x80, 0xE0, 0x38, 0x0E, 0x03, 0x80,\n  0xE0, 0x38, 0x0E, 0x03, 0x81, 0xE1, 0xFF, 0x07, 0xC0, 0x1F, 0xF0, 0x3F,\n  0xF8, 0x70, 0xF8, 0x60, 0x3C, 0xC0, 0x3C, 0x80, 0x1C, 0x00, 0x1C, 0x00,\n  0x1C, 0x00, 0x18, 0x00, 0x18, 0x00, 0x30, 0x00, 0x30, 0x00, 0x60, 0x00,\n  0xC0, 0x00, 0x80, 0x01, 0x00, 0x02, 0x00, 0x04, 0x00, 0x08, 0x01, 0x10,\n  0x02, 0x3F, 0xFE, 0x7F, 0xFC, 0xFF, 0xFC, 0x0F, 0xC0, 0xFF, 0x0C, 0x3C,\n  0x80, 0xE4, 0x03, 0x00, 0x18, 0x00, 0xC0, 0x04, 0x00, 0x40, 0x04, 0x00,\n  0xF8, 0x1F, 0xE0, 0x0F, 0x00, 0x1C, 0x00, 0xE0, 0x03, 0x00, 0x18, 0x00,\n  0xC0, 0x06, 0x00, 0x60, 0x03, 0x78, 0x73, 0xFF, 0x0F, 0xC0, 0x00, 0x30,\n  0x00, 0x30, 0x00, 0x70, 0x00, 0xF0, 0x00, 0xB0, 0x01, 0x30, 0x03, 0x30,\n  0x06, 0x30, 0x04, 0x30, 0x08, 0x30, 0x18, 0x30, 0x10, 0x30, 0x20, 0x30,\n  0x60, 0x30, 0xC0, 0x30, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x30, 0x00, 0x30,\n  0x00, 0x30, 0x00, 0x30, 0x00, 0x30, 0x00, 0x30, 0x00, 0x00, 0x7F, 0xC3,\n  0xFE, 0x1F, 0xE1, 0x80, 0x08, 0x00, 0xC0, 0x07, 0xC0, 0x7F, 0x81, 0xFF,\n  0x00, 0xFC, 0x01, 0xE0, 0x07, 0x80, 0x1C, 0x00, 0x60, 0x03, 0x00, 0x18,\n  0x00, 0xC0, 0x06, 0x00, 0x60, 0x07, 0x78, 0x73, 0xFF, 0x0F, 0xC0, 0x00,\n  0x0E, 0x00, 0xF8, 0x03, 0xC0, 0x07, 0x80, 0x0F, 0x00, 0x1E, 0x00, 0x3C,\n  0x00, 0x7C, 0x00, 0x79, 0xF0, 0x7F, 0xFC, 0xF8, 0x3C, 0xF0, 0x1E, 0xF0,\n  0x1F, 0xF0, 0x0F, 0xF0, 0x0F, 0xF0, 0x0F, 0xF0, 0x0F, 0x70, 0x0F, 0x78,\n  0x0F, 0x78, 0x0E, 0x3C, 0x1E, 0x1E, 0x3C, 0x0F, 0xF8, 0x07, 0xE0, 0x3F,\n  0xFD, 0xFF, 0xF7, 0xFF, 0xF0, 0x06, 0x80, 0x18, 0x00, 0x60, 0x03, 0x00,\n  0x0C, 0x00, 0x30, 0x01, 0x80, 0x06, 0x00, 0x18, 0x00, 0xE0, 0x03, 0x00,\n  0x0C, 0x00, 0x70, 0x01, 0x80, 0x06, 0x00, 0x38, 0x00, 0xC0, 0x03, 0x00,\n  0x1C, 0x00, 0x60, 0x00, 0x0F, 0x83, 0xFC, 0x70, 0xE6, 0x07, 0xC0, 0x3C,\n  0x03, 0xC0, 0x3E, 0x03, 0x70, 0x67, 0x8C, 0x3D, 0x81, 0xF0, 0x0F, 0x81,\n  0x7C, 0x21, 0xE6, 0x0E, 0xC0, 0x7C, 0x03, 0xC0, 0x3C, 0x03, 0xC0, 0x36,\n  0x06, 0x70, 0xE3, 0xFC, 0x0F, 0x80, 0x07, 0xC0, 0x1F, 0xF0, 0x3C, 0x78,\n  0x38, 0x3C, 0x78, 0x1E, 0x70, 0x1E, 0xF0, 0x0E, 0xF0, 0x0F, 0xF0, 0x0F,\n  0xF0, 0x0F, 0xF0, 0x0F, 0xF0, 0x0F, 0xF8, 0x0F, 0x78, 0x0F, 0x3C, 0x3F,\n  0x1F, 0xEE, 0x0F, 0x9E, 0x00, 0x1E, 0x00, 0x3C, 0x00, 0x38, 0x00, 0x78,\n  0x00, 0xF0, 0x01, 0xE0, 0x07, 0x80, 0x1E, 0x00, 0x70, 0x00, 0x6F, 0xF6,\n  0x00, 0x00, 0x00, 0x00, 0x06, 0xFF, 0x60, 0x67, 0xBC, 0xC0, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x19, 0xEF, 0x78, 0x42, 0x22, 0x20, 0x00, 0x00, 0xC0,\n  0x00, 0xF0, 0x01, 0xF8, 0x01, 0xF8, 0x01, 0xF8, 0x01, 0xF0, 0x03, 0xF0,\n  0x03, 0xF0, 0x00, 0xF0, 0x00, 0x3E, 0x00, 0x07, 0xE0, 0x00, 0x7E, 0x00,\n  0x03, 0xE0, 0x00, 0x3E, 0x00, 0x03, 0xF0, 0x00, 0x3F, 0x00, 0x03, 0xC0,\n  0x00, 0x10, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0x80,\n  0x00, 0x3C, 0x00, 0x0F, 0xC0, 0x00, 0xFC, 0x00, 0x07, 0xC0, 0x00, 0x7C,\n  0x00, 0x07, 0xE0, 0x00, 0x7E, 0x00, 0x07, 0xC0, 0x00, 0xF0, 0x00, 0xFC,\n  0x00, 0xFC, 0x00, 0xF8, 0x01, 0xF8, 0x01, 0xF8, 0x01, 0xF8, 0x00, 0xF0,\n  0x00, 0x30, 0x00, 0x00, 0x1F, 0x81, 0xFF, 0x18, 0x7D, 0x81, 0xEC, 0x07,\n  0xF0, 0x3F, 0x81, 0xE0, 0x0F, 0x00, 0x70, 0x03, 0x80, 0x38, 0x01, 0x80,\n  0x08, 0x00, 0xC0, 0x04, 0x00, 0x20, 0x02, 0x00, 0x10, 0x00, 0x80, 0x00,\n  0x00, 0x00, 0x03, 0x00, 0x3C, 0x01, 0xE0, 0x07, 0x00, 0x00, 0x7F, 0x00,\n  0x01, 0xFF, 0xC0, 0x07, 0x80, 0xF0, 0x0F, 0x00, 0x38, 0x1C, 0x00, 0x1C,\n  0x38, 0x00, 0x0C, 0x38, 0x00, 0x06, 0x70, 0x1E, 0x02, 0x70, 0x3F, 0xE3,\n  0xF0, 0x71, 0xE1, 0xE0, 0xE0, 0xC1, 0xE0, 0xC0, 0xC1, 0xE0, 0xC1, 0xC1,\n  0xE1, 0x81, 0xC1, 0xE1, 0x81, 0x83, 0xE1, 0x83, 0x82, 0xE1, 0x83, 0x86,\n  0x71, 0xC7, 0x8C, 0x70, 0xF9, 0xF8, 0x38, 0xF0, 0xF0, 0x3C, 0x00, 0x00,\n  0x1E, 0x00, 0x00, 0x07, 0x80, 0x70, 0x03, 0xFF, 0xE0, 0x00, 0x7F, 0x00,\n  0x00, 0x10, 0x00, 0x00, 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0xC0, 0x0F, 0xE0, 0x03,\n  0xF8, 0x00, 0xFC, 0x00, 0x3E, 0x00, 0x1F, 0x80, 0x0F, 0x80, 0x0F, 0xC0,\n  0x0F, 0xE0, 0x0F, 0x70, 0x1E, 0x78, 0x3C, 0x4F, 0xF8, 0x43, 0xF0, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xE0, 0xF0, 0x7C, 0x0F, 0x03, 0x80, 0xF0, 0x10,\n  0x0F, 0x00, 0x00, 0xF0, 0x00, 0x0F, 0x00, 0x00, 0xF0, 0x00, 0x0F, 0x00,\n  0x00, 0xF0, 0x00, 0x0F, 0x00, 0x00, 0xF0, 0x00, 0x0F, 0x00, 0x00, 0xF0,\n  0x00, 0x0F, 0x00, 0x00, 0xF0, 0x00, 0x0F, 0x00, 0x00, 0xF0, 0x00, 0x0F,\n  0x00, 0x00, 0xF0, 0x00, 0x1F, 0x80, 0x03, 0xFC, 0x00, 0xFF, 0x01, 0xFD,\n  0xF8, 0x01, 0xC3, 0xC0, 0x02, 0x0F, 0x00, 0x08, 0x3C, 0x00, 0x20, 0xF0,\n  0x00, 0x83, 0xC0, 0x02, 0x0F, 0x00, 0x08, 0x3C, 0x00, 0x20, 0xF0, 0x00,\n  0x83, 0xC0, 0x02, 0x0F, 0x00, 0x08, 0x3C, 0x00, 0x20, 0xF0, 0x00, 0x83,\n  0xC0, 0x02, 0x0F, 0x00, 0x08, 0x3C, 0x00, 0x20, 0xF0, 0x00, 0x81, 0xE0,\n  0x04, 0x07, 0x80, 0x30, 0x0F, 0x81, 0x80, 0x1F, 0xFC, 0x00, 0x1F, 0xC0,\n  0x00, 0xFF, 0xC0, 0x7F, 0x3E, 0x00, 0x1E, 0x1E, 0x00, 0x0C, 0x0E, 0x00,\n  0x18, 0x0F, 0x00, 0x18, 0x07, 0x00, 0x10, 0x07, 0x80, 0x30, 0x07, 0x80,\n  0x30, 0x03, 0xC0, 0x60, 0x03, 0xC0, 0x60, 0x01, 0xE0, 0x40, 0x01, 0xE0,\n  0xC0, 0x00, 0xF0, 0xC0, 0x00, 0xF1, 0x80, 0x00, 0x71, 0x80, 0x00, 0x7B,\n  0x00, 0x00, 0x3B, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x1E,\n  0x00, 0x00, 0x0C, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x08, 0x00, 0xFF, 0x9F,\n  0xF0, 0x3F, 0x9F, 0x03, 0xE0, 0x07, 0x07, 0x80, 0xF0, 0x03, 0x03, 0xC0,\n  0x78, 0x01, 0x80, 0xE0, 0x1E, 0x00, 0x80, 0x78, 0x0F, 0x00, 0xC0, 0x1C,\n  0x03, 0x80, 0x60, 0x0F, 0x01, 0xE0, 0x20, 0x07, 0x81, 0xF0, 0x30, 0x01,\n  0xC0, 0xBC, 0x18, 0x00, 0xF0, 0xDE, 0x08, 0x00, 0x78, 0x67, 0x0C, 0x00,\n  0x1E, 0x23, 0xC4, 0x00, 0x0F, 0x31, 0xE6, 0x00, 0x03, 0x90, 0x7B, 0x00,\n  0x01, 0xF8, 0x3D, 0x00, 0x00, 0xFC, 0x0F, 0x80, 0x00, 0x3C, 0x07, 0xC0,\n  0x00, 0x1E, 0x03, 0xC0, 0x00, 0x0F, 0x00, 0xE0, 0x00, 0x03, 0x00, 0x70,\n  0x00, 0x01, 0x80, 0x10, 0x00, 0x00, 0x80, 0x08, 0x00, 0x7F, 0xE0, 0xFF,\n  0x0F, 0xC0, 0x1E, 0x03, 0xE0, 0x0E, 0x00, 0xF0, 0x06, 0x00, 0x3C, 0x06,\n  0x00, 0x0F, 0x06, 0x00, 0x07, 0x86, 0x00, 0x01, 0xE6, 0x00, 0x00, 0x7B,\n  0x00, 0x00, 0x3F, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x03, 0xC0, 0x00, 0x03,\n  0xF0, 0x00, 0x03, 0x78, 0x00, 0x01, 0x9E, 0x00, 0x01, 0x87, 0x80, 0x01,\n  0x83, 0xE0, 0x01, 0x80, 0xF0, 0x01, 0x80, 0x3C, 0x01, 0x80, 0x1F, 0x01,\n  0xC0, 0x07, 0xC1, 0xE0, 0x03, 0xF3, 0xFE, 0x0F, 0xFE, 0xFF, 0xC0, 0xFF,\n  0x7E, 0x00, 0x1C, 0x1E, 0x00, 0x18, 0x1F, 0x00, 0x30, 0x0F, 0x00, 0x60,\n  0x07, 0x80, 0x60, 0x03, 0xC0, 0xC0, 0x03, 0xE1, 0x80, 0x01, 0xE1, 0x80,\n  0x00, 0xF3, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x3C, 0x00,\n  0x00, 0x3C, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x3C, 0x00,\n  0x00, 0x3C, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x3C, 0x00,\n  0x00, 0x7E, 0x00, 0x01, 0xFF, 0x80, 0x3F, 0xFF, 0xF1, 0xFF, 0xFF, 0x9C,\n  0x00, 0x78, 0xC0, 0x07, 0x84, 0x00, 0x38, 0x00, 0x03, 0xC0, 0x00, 0x3C,\n  0x00, 0x03, 0xC0, 0x00, 0x1C, 0x00, 0x01, 0xE0, 0x00, 0x1E, 0x00, 0x01,\n  0xE0, 0x00, 0x0E, 0x00, 0x00, 0xF0, 0x00, 0x0F, 0x00, 0x00, 0xF0, 0x00,\n  0x07, 0x00, 0x00, 0x78, 0x00, 0x47, 0x80, 0x06, 0x78, 0x00, 0x33, 0x80,\n  0x07, 0x3F, 0xFF, 0xFB, 0xFF, 0xFF, 0xC0, 0xFF, 0x83, 0x06, 0x0C, 0x18,\n  0x30, 0x60, 0xC1, 0x83, 0x06, 0x0C, 0x18, 0x30, 0x60, 0xC1, 0x83, 0x06,\n  0x0C, 0x18, 0x30, 0x60, 0xC1, 0x83, 0x07, 0xF0, 0xC0, 0x18, 0x06, 0x01,\n  0x80, 0x70, 0x0C, 0x03, 0x00, 0xE0, 0x18, 0x06, 0x01, 0xC0, 0x30, 0x0C,\n  0x03, 0x80, 0x60, 0x18, 0x07, 0x00, 0xC0, 0x30, 0x0E, 0x01, 0x80, 0x60,\n  0x1C, 0x03, 0xFE, 0x0C, 0x18, 0x30, 0x60, 0xC1, 0x83, 0x06, 0x0C, 0x18,\n  0x30, 0x60, 0xC1, 0x83, 0x06, 0x0C, 0x18, 0x30, 0x60, 0xC1, 0x83, 0x06,\n  0x0C, 0x1F, 0xF0, 0x03, 0x80, 0x0F, 0x00, 0x1F, 0x00, 0x76, 0x00, 0xCE,\n  0x03, 0x8C, 0x06, 0x1C, 0x1C, 0x18, 0x30, 0x30, 0xE0, 0x31, 0x80, 0x67,\n  0x00, 0x6C, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0xC0, 0xE0, 0x70,\n  0x18, 0x0C, 0x03, 0x1F, 0x03, 0x8C, 0x38, 0x31, 0xC1, 0x8E, 0x0C, 0x00,\n  0x60, 0x0F, 0x01, 0x98, 0x30, 0xC3, 0x86, 0x38, 0x31, 0xC1, 0x8E, 0x0C,\n  0x78, 0xE5, 0xFB, 0xCF, 0x0C, 0x00, 0x00, 0x38, 0x00, 0xF8, 0x00, 0x38,\n  0x00, 0x38, 0x00, 0x38, 0x00, 0x38, 0x00, 0x38, 0x00, 0x38, 0x00, 0x39,\n  0xF0, 0x3B, 0xFC, 0x3C, 0x3E, 0x38, 0x0E, 0x38, 0x0F, 0x38, 0x07, 0x38,\n  0x07, 0x38, 0x07, 0x38, 0x07, 0x38, 0x07, 0x38, 0x06, 0x38, 0x0E, 0x38,\n  0x0C, 0x3C, 0x1C, 0x1F, 0xF0, 0x07, 0xE0, 0x07, 0xE0, 0x7F, 0xE3, 0x87,\n  0xD8, 0x0F, 0x60, 0x1B, 0x00, 0x0C, 0x00, 0x30, 0x00, 0xC0, 0x03, 0x00,\n  0x0E, 0x00, 0x3C, 0x01, 0x78, 0x19, 0xFF, 0xC3, 0xFE, 0x03, 0xE0, 0x00,\n  0x00, 0x00, 0x1C, 0x00, 0x7C, 0x00, 0x1C, 0x00, 0x1C, 0x00, 0x1C, 0x00,\n  0x1C, 0x00, 0x1C, 0x00, 0x1C, 0x07, 0x9C, 0x1F, 0xDC, 0x38, 0x7C, 0x70,\n  0x3C, 0x70, 0x1C, 0x60, 0x1C, 0xE0, 0x1C, 0xE0, 0x1C, 0xE0, 0x1C, 0xE0,\n  0x1C, 0xE0, 0x1C, 0xF0, 0x1C, 0x70, 0x1C, 0x7C, 0x3E, 0x3F, 0xDF, 0x0F,\n  0x90, 0x0F, 0x81, 0xFF, 0x08, 0x3C, 0x80, 0xE7, 0xFF, 0x7F, 0xFF, 0x00,\n  0x18, 0x00, 0xC0, 0x07, 0x00, 0x38, 0x03, 0xE0, 0x37, 0x83, 0x3F, 0xF0,\n  0xFF, 0x03, 0xF0, 0x01, 0xF0, 0x3F, 0xC3, 0x8E, 0x18, 0x00, 0xC0, 0x0E,\n  0x00, 0x70, 0x03, 0x80, 0x1C, 0x03, 0xFE, 0x1F, 0xF0, 0x38, 0x01, 0xC0,\n  0x0E, 0x00, 0x70, 0x03, 0x80, 0x1C, 0x00, 0xE0, 0x07, 0x00, 0x38, 0x01,\n  0xC0, 0x0E, 0x00, 0x70, 0x07, 0xC0, 0xFF, 0x80, 0x0F, 0xC0, 0x1F, 0xFF,\n  0x38, 0xFF, 0x70, 0x70, 0x70, 0x70, 0x70, 0x30, 0x70, 0x30, 0x70, 0x30,\n  0x38, 0x20, 0x1C, 0x60, 0x0F, 0x80, 0x10, 0x00, 0x20, 0x00, 0x60, 0x00,\n  0x7F, 0xE0, 0x3F, 0xFC, 0x1F, 0xFE, 0x20, 0x06, 0x40, 0x02, 0xC0, 0x02,\n  0xC0, 0x04, 0xF0, 0x18, 0x7F, 0xF0, 0x1F, 0x80, 0x00, 0x00, 0x38, 0x00,\n  0xF8, 0x00, 0x38, 0x00, 0x38, 0x00, 0x38, 0x00, 0x38, 0x00, 0x38, 0x00,\n  0x38, 0x00, 0x38, 0xF0, 0x3B, 0xF8, 0x3E, 0x3C, 0x3C, 0x1C, 0x38, 0x1C,\n  0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C,\n  0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C, 0x7C, 0x3E, 0xFE, 0x7F, 0x18, 0x3C,\n  0x3C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x04, 0x3C, 0x7C, 0x1C, 0x1C, 0x1C,\n  0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x3C, 0xFF, 0x03, 0x03,\n  0xC1, 0xE0, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0xC3, 0xE0, 0x70,\n  0x38, 0x1C, 0x0E, 0x07, 0x03, 0x81, 0xC0, 0xE0, 0x70, 0x38, 0x1C, 0x0E,\n  0x07, 0x03, 0x81, 0xC0, 0xE0, 0x70, 0x37, 0x3B, 0xF8, 0xF8, 0x00, 0x00,\n  0x1C, 0x00, 0x3E, 0x00, 0x07, 0x00, 0x03, 0x80, 0x01, 0xC0, 0x00, 0xE0,\n  0x00, 0x70, 0x00, 0x38, 0x00, 0x1C, 0x3F, 0x8E, 0x0F, 0x07, 0x06, 0x03,\n  0x86, 0x01, 0xC4, 0x00, 0xE4, 0x00, 0x7E, 0x00, 0x3F, 0x80, 0x1D, 0xC0,\n  0x0E, 0x70, 0x07, 0x1C, 0x03, 0x8F, 0x01, 0xC3, 0xC0, 0xE0, 0xF0, 0xF8,\n  0x3C, 0xFE, 0x7F, 0x80, 0x00, 0x1C, 0x7C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n  0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n  0x1C, 0x1C, 0x1C, 0x3C, 0xFF, 0x38, 0xF0, 0x7C, 0x3E, 0xFE, 0x7F, 0x83,\n  0xE3, 0xF0, 0xE0, 0xE0, 0x70, 0x1C, 0x38, 0x1C, 0x07, 0x0E, 0x07, 0x01,\n  0xC3, 0x81, 0xC0, 0x70, 0xE0, 0x70, 0x1C, 0x38, 0x1C, 0x07, 0x0E, 0x07,\n  0x01, 0xC3, 0x81, 0xC0, 0x70, 0xE0, 0x70, 0x1C, 0x38, 0x1C, 0x07, 0x0E,\n  0x07, 0x01, 0xC3, 0x81, 0xE0, 0x73, 0xF9, 0xFC, 0x7F, 0x38, 0xF0, 0xFB,\n  0xF8, 0x3E, 0x3C, 0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C, 0x38,\n  0x1C, 0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C, 0x38,\n  0x1C, 0x78, 0x3C, 0xFE, 0x7F, 0x07, 0xE0, 0x1F, 0xF8, 0x3C, 0x7C, 0x78,\n  0x3E, 0x70, 0x1E, 0xF0, 0x0F, 0xF0, 0x0F, 0xF0, 0x0F, 0xF0, 0x0F, 0xF0,\n  0x0F, 0xF8, 0x0F, 0x78, 0x0E, 0x7C, 0x1C, 0x3E, 0x3C, 0x0F, 0xF0, 0x07,\n  0xC0, 0x18, 0xF0, 0xFB, 0xFC, 0x3E, 0x1E, 0x38, 0x0E, 0x38, 0x0F, 0x38,\n  0x07, 0x38, 0x07, 0x38, 0x07, 0x38, 0x07, 0x38, 0x07, 0x38, 0x06, 0x38,\n  0x0E, 0x38, 0x0C, 0x3E, 0x1C, 0x3B, 0xF8, 0x39, 0xE0, 0x38, 0x00, 0x38,\n  0x00, 0x38, 0x00, 0x38, 0x00, 0x38, 0x00, 0x38, 0x00, 0x7C, 0x00, 0xFF,\n  0x00, 0x07, 0xC4, 0x1F, 0xEC, 0x3C, 0x3C, 0x70, 0x1C, 0x70, 0x1C, 0x60,\n  0x1C, 0xE0, 0x1C, 0xE0, 0x1C, 0xE0, 0x1C, 0xE0, 0x1C, 0xE0, 0x1C, 0xF0,\n  0x1C, 0x70, 0x1C, 0x78, 0x3C, 0x3F, 0xDC, 0x1F, 0x1C, 0x00, 0x1C, 0x00,\n  0x1C, 0x00, 0x1C, 0x00, 0x1C, 0x00, 0x1C, 0x00, 0x1C, 0x00, 0x3E, 0x00,\n  0xFF, 0x19, 0xFF, 0x7C, 0xF3, 0x9C, 0x03, 0x80, 0x70, 0x0E, 0x01, 0xC0,\n  0x38, 0x07, 0x00, 0xE0, 0x1C, 0x03, 0x80, 0x70, 0x1F, 0x07, 0xF0, 0x3E,\n  0x58, 0x7C, 0x0F, 0x03, 0xC0, 0x7C, 0x07, 0x80, 0xF8, 0x1F, 0x81, 0xF8,\n  0x1E, 0x03, 0xC0, 0xF0, 0x3E, 0x1A, 0x7C, 0x10, 0x30, 0x70, 0xFE, 0xFE,\n  0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x79,\n  0x7E, 0x3C, 0xF8, 0x7C, 0x38, 0x3C, 0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C,\n  0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C, 0x38, 0x1C,\n  0x38, 0x1C, 0x38, 0x1C, 0x3C, 0x7C, 0x1F, 0xDF, 0x0F, 0x18, 0xFE, 0x1F,\n  0x7C, 0x06, 0x38, 0x04, 0x1C, 0x04, 0x1C, 0x0C, 0x0E, 0x08, 0x0E, 0x18,\n  0x07, 0x10, 0x07, 0x10, 0x07, 0x20, 0x03, 0xA0, 0x03, 0xE0, 0x01, 0xC0,\n  0x01, 0xC0, 0x00, 0x80, 0x00, 0x80, 0xFC, 0x7F, 0x1F, 0x78, 0x3C, 0x06,\n  0x38, 0x1C, 0x04, 0x38, 0x1C, 0x04, 0x1C, 0x1C, 0x0C, 0x1C, 0x0E, 0x08,\n  0x1C, 0x1E, 0x18, 0x0E, 0x17, 0x10, 0x0E, 0x37, 0x10, 0x07, 0x23, 0x30,\n  0x07, 0x63, 0xA0, 0x07, 0x43, 0xE0, 0x03, 0xC1, 0xC0, 0x03, 0x81, 0xC0,\n  0x01, 0x80, 0x80, 0x01, 0x00, 0x80, 0x7F, 0x7E, 0x1E, 0x0C, 0x07, 0x8C,\n  0x01, 0xC4, 0x00, 0x76, 0x00, 0x3E, 0x00, 0x0E, 0x00, 0x03, 0x80, 0x03,\n  0xE0, 0x01, 0x70, 0x01, 0x1C, 0x01, 0x8F, 0x01, 0x83, 0x80, 0x80, 0xE0,\n  0xC0, 0x79, 0xF0, 0xFF, 0xFE, 0x0F, 0x7C, 0x06, 0x38, 0x06, 0x1C, 0x04,\n  0x1C, 0x0C, 0x0E, 0x0C, 0x0E, 0x08, 0x0F, 0x18, 0x07, 0x10, 0x07, 0x90,\n  0x03, 0xB0, 0x03, 0xA0, 0x01, 0xE0, 0x01, 0xE0, 0x00, 0xC0, 0x00, 0xC0,\n  0x00, 0x80, 0x00, 0x80, 0x01, 0x80, 0x01, 0x00, 0x03, 0x00, 0x7E, 0x00,\n  0x7C, 0x00, 0x78, 0x00, 0x7F, 0xF9, 0xFF, 0xE6, 0x07, 0x10, 0x38, 0x00,\n  0xE0, 0x07, 0x00, 0x38, 0x01, 0xE0, 0x07, 0x00, 0x38, 0x01, 0xE0, 0x07,\n  0x01, 0x38, 0x0D, 0xC0, 0x3F, 0xFF, 0xBF, 0xFE, 0x07, 0x0E, 0x1C, 0x18,\n  0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x30, 0x60, 0x60,\n  0x10, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x1C,\n  0x0E, 0x07, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xE0, 0x70, 0x38, 0x18,\n  0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x08, 0x06, 0x06,\n  0x08, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x38,\n  0x70, 0xE0, 0x3E, 0x00, 0x7F, 0x87, 0xE3, 0xFE, 0x00, 0x7C };\n\nconst GFXglyph FreeSerif18pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,   9,    0,    1 },   // 0x20 ' '\n  {     0,   4,  24,  12,    5,  -23 },   // 0x21 '!'\n  {    12,   8,   9,  14,    3,  -23 },   // 0x22 '\"'\n  {    21,  17,  23,  17,    0,  -22 },   // 0x23 '#'\n  {    70,  13,  27,  17,    2,  -24 },   // 0x24 '$'\n  {   114,  25,  23,  29,    2,  -22 },   // 0x25 '%'\n  {   186,  25,  25,  27,    1,  -24 },   // 0x26 '&'\n  {   265,   3,   9,   7,    2,  -23 },   // 0x27 '''\n  {   269,   9,  30,  12,    2,  -23 },   // 0x28 '('\n  {   303,   9,  30,  12,    1,  -22 },   // 0x29 ')'\n  {   337,  12,  14,  18,    3,  -23 },   // 0x2A '*'\n  {   358,  16,  18,  20,    2,  -17 },   // 0x2B '+'\n  {   394,   4,   9,   9,    2,   -3 },   // 0x2C ','\n  {   399,   8,   2,  12,    1,   -8 },   // 0x2D '-'\n  {   401,   4,   4,   9,    2,   -3 },   // 0x2E '.'\n  {   403,  10,  24,  10,    0,  -23 },   // 0x2F '/'\n  {   433,  16,  24,  18,    1,  -23 },   // 0x30 '0'\n  {   481,  10,  24,  18,    3,  -23 },   // 0x31 '1'\n  {   511,  16,  24,  17,    1,  -23 },   // 0x32 '2'\n  {   559,  13,  24,  17,    2,  -23 },   // 0x33 '3'\n  {   598,  16,  23,  18,    0,  -22 },   // 0x34 '4'\n  {   644,  13,  24,  17,    2,  -23 },   // 0x35 '5'\n  {   683,  16,  24,  18,    1,  -23 },   // 0x36 '6'\n  {   731,  14,  23,  18,    1,  -22 },   // 0x37 '7'\n  {   772,  12,  25,  18,    2,  -24 },   // 0x38 '8'\n  {   810,  16,  26,  17,    1,  -24 },   // 0x39 '9'\n  {   862,   4,  17,   9,    2,  -16 },   // 0x3A ':'\n  {   871,   5,  22,   9,    2,  -16 },   // 0x3B ';'\n  {   885,  18,  18,  20,    1,  -17 },   // 0x3C '<'\n  {   926,  18,   9,  20,    1,  -12 },   // 0x3D '='\n  {   947,  18,  18,  20,    1,  -17 },   // 0x3E '>'\n  {   988,  13,  25,  16,    2,  -24 },   // 0x3F '?'\n  {  1029,  24,  25,  30,    3,  -24 },   // 0x40 '@'\n  {  1104,  24,  23,  25,    1,  -22 },   // 0x41 'A'\n  {  1173,  20,  23,  22,    1,  -22 },   // 0x42 'B'\n  {  1231,  22,  24,  23,    1,  -23 },   // 0x43 'C'\n  {  1297,  23,  23,  25,    1,  -22 },   // 0x44 'D'\n  {  1364,  20,  23,  21,    2,  -22 },   // 0x45 'E'\n  {  1422,  17,  23,  20,    2,  -22 },   // 0x46 'F'\n  {  1471,  23,  24,  25,    1,  -23 },   // 0x47 'G'\n  {  1540,  22,  23,  25,    2,  -22 },   // 0x48 'H'\n  {  1604,   9,  23,  11,    2,  -22 },   // 0x49 'I'\n  {  1630,  12,  23,  13,    0,  -22 },   // 0x4A 'J'\n  {  1665,  23,  23,  25,    2,  -22 },   // 0x4B 'K'\n  {  1732,  19,  23,  21,    2,  -22 },   // 0x4C 'L'\n  {  1787,  29,  23,  31,    1,  -22 },   // 0x4D 'M'\n  {  1871,  23,  23,  25,    1,  -22 },   // 0x4E 'N'\n  {  1938,  23,  24,  25,    1,  -23 },   // 0x4F 'O'\n  {  2007,  18,  23,  20,    1,  -22 },   // 0x50 'P'\n  {  2059,  23,  30,  25,    1,  -23 },   // 0x51 'Q'\n  {  2146,  21,  23,  23,    2,  -22 },   // 0x52 'R'\n  {  2207,  16,  24,  19,    1,  -23 },   // 0x53 'S'\n  {  2255,  20,  23,  21,    1,  -22 },   // 0x54 'T'\n  {  2313,  22,  23,  25,    2,  -22 },   // 0x55 'U'\n  {  2377,  24,  23,  25,    0,  -22 },   // 0x56 'V'\n  {  2446,  33,  23,  33,    0,  -22 },   // 0x57 'W'\n  {  2541,  25,  23,  25,    0,  -22 },   // 0x58 'X'\n  {  2613,  24,  23,  25,    1,  -22 },   // 0x59 'Y'\n  {  2682,  21,  23,  21,    0,  -22 },   // 0x5A 'Z'\n  {  2743,   7,  28,  12,    3,  -22 },   // 0x5B '['\n  {  2768,  10,  24,  10,    0,  -23 },   // 0x5C '\\'\n  {  2798,   7,  28,  12,    2,  -22 },   // 0x5D ']'\n  {  2823,  15,  13,  16,    1,  -22 },   // 0x5E '^'\n  {  2848,  18,   2,  17,    0,    3 },   // 0x5F '_'\n  {  2853,   8,   6,   9,    1,  -23 },   // 0x60 '`'\n  {  2859,  13,  16,  15,    2,  -15 },   // 0x61 'a'\n  {  2885,  16,  25,  17,    1,  -24 },   // 0x62 'b'\n  {  2935,  14,  16,  16,    1,  -15 },   // 0x63 'c'\n  {  2963,  16,  25,  17,    1,  -24 },   // 0x64 'd'\n  {  3013,  13,  16,  16,    1,  -15 },   // 0x65 'e'\n  {  3039,  13,  25,  13,    0,  -24 },   // 0x66 'f'\n  {  3080,  16,  24,  16,    1,  -15 },   // 0x67 'g'\n  {  3128,  16,  25,  17,    1,  -24 },   // 0x68 'h'\n  {  3178,   8,  24,  10,    0,  -23 },   // 0x69 'i'\n  {  3202,   9,  32,  12,    0,  -23 },   // 0x6A 'j'\n  {  3238,  17,  25,  18,    1,  -24 },   // 0x6B 'k'\n  {  3292,   8,  25,   9,    0,  -24 },   // 0x6C 'l'\n  {  3317,  26,  16,  27,    1,  -15 },   // 0x6D 'm'\n  {  3369,  16,  16,  17,    1,  -15 },   // 0x6E 'n'\n  {  3401,  16,  16,  17,    1,  -15 },   // 0x6F 'o'\n  {  3433,  16,  24,  17,    1,  -15 },   // 0x70 'p'\n  {  3481,  16,  24,  17,    1,  -15 },   // 0x71 'q'\n  {  3529,  11,  16,  12,    1,  -15 },   // 0x72 'r'\n  {  3551,  10,  16,  13,    1,  -15 },   // 0x73 's'\n  {  3571,   8,  19,  10,    2,  -18 },   // 0x74 't'\n  {  3590,  16,  16,  17,    1,  -15 },   // 0x75 'u'\n  {  3622,  16,  16,  16,    0,  -15 },   // 0x76 'v'\n  {  3654,  24,  16,  24,    0,  -15 },   // 0x77 'w'\n  {  3702,  17,  16,  17,    0,  -15 },   // 0x78 'x'\n  {  3736,  16,  24,  16,    0,  -15 },   // 0x79 'y'\n  {  3784,  14,  16,  15,    0,  -15 },   // 0x7A 'z'\n  {  3812,   8,  30,  17,    3,  -23 },   // 0x7B '{'\n  {  3842,   2,  24,   7,    2,  -23 },   // 0x7C '|'\n  {  3848,   8,  30,  17,    6,  -22 },   // 0x7D '}'\n  {  3878,  16,   4,  17,    1,  -10 } }; // 0x7E '~'\n\nconst GFXfont FreeSerif18pt7b PROGMEM = {\n  (uint8_t  *)FreeSerif18pt7bBitmaps,\n  (GFXglyph *)FreeSerif18pt7bGlyphs,\n  0x20, 0x7E, 42 };\n\n// Approx. 4558 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeSerif24pt7b.h",
    "content": "const uint8_t FreeSerif24pt7bBitmaps[] PROGMEM = {\n  0x77, 0xBF, 0xFF, 0xFF, 0xFF, 0xFB, 0x9C, 0xE7, 0x39, 0xCE, 0x61, 0x08,\n  0x42, 0x10, 0x84, 0x00, 0x00, 0xEF, 0xFF, 0xEE, 0x60, 0x6F, 0x0F, 0xF0,\n  0xFF, 0x0F, 0xF0, 0xFF, 0x0F, 0x60, 0x66, 0x06, 0x60, 0x66, 0x06, 0x60,\n  0x66, 0x06, 0x00, 0xE0, 0x70, 0x01, 0xC0, 0xE0, 0x03, 0x81, 0xC0, 0x07,\n  0x03, 0x80, 0x0E, 0x06, 0x00, 0x18, 0x0C, 0x00, 0x30, 0x38, 0x00, 0xE0,\n  0x70, 0x01, 0xC0, 0xE0, 0x03, 0x81, 0xC1, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF,\n  0xF0, 0x18, 0x0C, 0x00, 0x70, 0x38, 0x00, 0xE0, 0x70, 0x01, 0xC0, 0xE0,\n  0x03, 0x81, 0xC0, 0x07, 0x03, 0x80, 0x0C, 0x06, 0x07, 0xFF, 0xFF, 0xEF,\n  0xFF, 0xFF, 0xC0, 0xE0, 0x70, 0x01, 0xC0, 0xE0, 0x03, 0x81, 0xC0, 0x06,\n  0x03, 0x80, 0x0C, 0x06, 0x00, 0x38, 0x1C, 0x00, 0x70, 0x38, 0x00, 0xE0,\n  0x70, 0x01, 0xC0, 0xE0, 0x03, 0x81, 0xC0, 0x00, 0x00, 0x40, 0x00, 0x08,\n  0x00, 0x01, 0x00, 0x01, 0xFC, 0x01, 0xE4, 0xF8, 0x70, 0x87, 0x9C, 0x10,\n  0x77, 0x02, 0x06, 0xE0, 0x40, 0xDC, 0x08, 0x0B, 0x81, 0x00, 0x78, 0x20,\n  0x07, 0x84, 0x00, 0xFC, 0x80, 0x0F, 0xF0, 0x00, 0xFE, 0x00, 0x07, 0xF0,\n  0x00, 0x7F, 0x80, 0x03, 0xFC, 0x00, 0x3F, 0xC0, 0x05, 0xFC, 0x00, 0x8F,\n  0x80, 0x10, 0xF8, 0x02, 0x0F, 0x00, 0x40, 0xF0, 0x08, 0x1E, 0x01, 0x03,\n  0xE0, 0x20, 0x7C, 0x04, 0x0F, 0xC0, 0x83, 0xBC, 0x10, 0xE3, 0xE2, 0x78,\n  0x3F, 0xFE, 0x00, 0xFE, 0x00, 0x01, 0x00, 0x00, 0x20, 0x00, 0x04, 0x00,\n  0x01, 0xF0, 0x00, 0xC0, 0x03, 0xFC, 0x01, 0xE0, 0x03, 0xC7, 0x81, 0xE0,\n  0x03, 0xC0, 0x7F, 0x60, 0x03, 0xC0, 0x20, 0x70, 0x01, 0xE0, 0x10, 0x30,\n  0x01, 0xE0, 0x08, 0x38, 0x00, 0xE0, 0x04, 0x18, 0x00, 0xF0, 0x02, 0x1C,\n  0x00, 0x78, 0x02, 0x0C, 0x00, 0x38, 0x01, 0x0E, 0x00, 0x1C, 0x01, 0x86,\n  0x00, 0x0E, 0x00, 0x86, 0x00, 0x07, 0x00, 0x87, 0x03, 0xE1, 0x80, 0xC3,\n  0x07, 0xFC, 0xE1, 0xC3, 0x87, 0xC6, 0x3F, 0xC1, 0x87, 0x81, 0x8F, 0x81,\n  0xC7, 0x80, 0x40, 0x00, 0xC3, 0xC0, 0x20, 0x00, 0xE3, 0xC0, 0x10, 0x00,\n  0x61, 0xC0, 0x08, 0x00, 0x61, 0xE0, 0x04, 0x00, 0x70, 0xF0, 0x06, 0x00,\n  0x30, 0x70, 0x02, 0x00, 0x38, 0x38, 0x03, 0x00, 0x18, 0x1C, 0x01, 0x00,\n  0x1C, 0x0E, 0x01, 0x80, 0x0C, 0x07, 0x01, 0x80, 0x0E, 0x01, 0xC3, 0x80,\n  0x06, 0x00, 0x7F, 0x80, 0x06, 0x00, 0x1F, 0x00, 0x07, 0x00, 0x00, 0x00,\n  0x00, 0x1F, 0x00, 0x00, 0x00, 0x3F, 0xC0, 0x00, 0x00, 0x70, 0xE0, 0x00,\n  0x00, 0xE0, 0x60, 0x00, 0x00, 0xC0, 0x30, 0x00, 0x01, 0xC0, 0x30, 0x00,\n  0x01, 0xC0, 0x30, 0x00, 0x01, 0xC0, 0x30, 0x00, 0x01, 0xC0, 0x70, 0x00,\n  0x01, 0xE0, 0xE0, 0x00, 0x01, 0xE1, 0xC0, 0x00, 0x00, 0xF3, 0x80, 0x00,\n  0x00, 0xFF, 0x0F, 0xFC, 0x00, 0xFC, 0x03, 0xF0, 0x00, 0xF8, 0x01, 0xE0,\n  0x01, 0xFC, 0x01, 0xC0, 0x07, 0x7C, 0x01, 0xC0, 0x0F, 0x3E, 0x01, 0x80,\n  0x1E, 0x3E, 0x03, 0x00, 0x3C, 0x1F, 0x03, 0x00, 0x7C, 0x1F, 0x06, 0x00,\n  0x78, 0x0F, 0x86, 0x00, 0x78, 0x07, 0xCC, 0x00, 0xF8, 0x07, 0xE8, 0x00,\n  0xF8, 0x03, 0xF8, 0x00, 0xF8, 0x01, 0xF0, 0x00, 0xF8, 0x01, 0xF8, 0x00,\n  0xFC, 0x00, 0xFC, 0x01, 0xFC, 0x01, 0xFE, 0x01, 0x7E, 0x03, 0xBF, 0x86,\n  0x7F, 0x0F, 0x1F, 0xFE, 0x3F, 0xFC, 0x0F, 0xF8, 0x0F, 0xE0, 0x03, 0xF0,\n  0x6F, 0xFF, 0xFF, 0x66, 0x66, 0x66, 0x00, 0x10, 0x02, 0x00, 0xC0, 0x18,\n  0x03, 0x00, 0x60, 0x0E, 0x00, 0xC0, 0x1C, 0x03, 0x80, 0x38, 0x03, 0x80,\n  0x78, 0x07, 0x00, 0x70, 0x0F, 0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0x00,\n  0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x07, 0x00, 0x70, 0x07, 0x80,\n  0x38, 0x03, 0x80, 0x38, 0x01, 0xC0, 0x0C, 0x00, 0xC0, 0x06, 0x00, 0x30,\n  0x01, 0x80, 0x0C, 0x00, 0x60, 0x03, 0xC0, 0x06, 0x00, 0x30, 0x01, 0x80,\n  0x0C, 0x00, 0x60, 0x07, 0x00, 0x30, 0x03, 0x80, 0x1C, 0x01, 0xC0, 0x1C,\n  0x01, 0xE0, 0x0E, 0x00, 0xE0, 0x0F, 0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x0F,\n  0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x0E, 0x00, 0xE0, 0x1E,\n  0x01, 0xC0, 0x1C, 0x01, 0xC0, 0x38, 0x03, 0x00, 0x70, 0x0E, 0x00, 0xC0,\n  0x18, 0x03, 0x00, 0x40, 0x08, 0x00, 0x03, 0x80, 0x03, 0x80, 0x03, 0x80,\n  0x43, 0x86, 0xE1, 0x0F, 0xF1, 0x1F, 0xF9, 0x3E, 0x3D, 0x78, 0x07, 0xC0,\n  0x01, 0x00, 0x07, 0xC0, 0x19, 0x30, 0xF9, 0x1E, 0xF1, 0x0F, 0xE1, 0x07,\n  0x03, 0x80, 0x03, 0x80, 0x03, 0x80, 0x03, 0x80, 0x00, 0x38, 0x00, 0x00,\n  0x70, 0x00, 0x00, 0xE0, 0x00, 0x01, 0xC0, 0x00, 0x03, 0x80, 0x00, 0x07,\n  0x00, 0x00, 0x0E, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x38, 0x00, 0x00, 0x70,\n  0x00, 0x00, 0xE0, 0x07, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xE0, 0x07, 0x00,\n  0x00, 0x0E, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x38, 0x00, 0x00, 0x70, 0x00,\n  0x00, 0xE0, 0x00, 0x01, 0xC0, 0x00, 0x03, 0x80, 0x00, 0x07, 0x00, 0x00,\n  0x0E, 0x00, 0x00, 0x73, 0xEF, 0xFF, 0x7C, 0x10, 0x42, 0x08, 0xC6, 0x00,\n  0xFF, 0xFF, 0xFC, 0x77, 0xFF, 0xF7, 0x00, 0x00, 0x1C, 0x00, 0xE0, 0x03,\n  0x80, 0x0E, 0x00, 0x70, 0x01, 0xC0, 0x07, 0x00, 0x38, 0x00, 0xE0, 0x03,\n  0x80, 0x1C, 0x00, 0x70, 0x01, 0xC0, 0x0E, 0x00, 0x38, 0x01, 0xE0, 0x07,\n  0x00, 0x1C, 0x00, 0xF0, 0x03, 0x80, 0x0E, 0x00, 0x78, 0x01, 0xC0, 0x07,\n  0x00, 0x3C, 0x00, 0xE0, 0x03, 0x80, 0x1E, 0x00, 0x70, 0x01, 0xC0, 0x0F,\n  0x00, 0x38, 0x00, 0x00, 0xFC, 0x00, 0x0E, 0x1C, 0x00, 0x70, 0x38, 0x03,\n  0x80, 0x70, 0x1E, 0x01, 0xE0, 0xF0, 0x03, 0x83, 0xC0, 0x0F, 0x0F, 0x00,\n  0x3C, 0x7C, 0x00, 0xF9, 0xE0, 0x01, 0xE7, 0x80, 0x07, 0xBE, 0x00, 0x1F,\n  0xF8, 0x00, 0x7F, 0xE0, 0x01, 0xFF, 0x80, 0x07, 0xFE, 0x00, 0x1F, 0xF8,\n  0x00, 0x7F, 0xE0, 0x01, 0xFF, 0x80, 0x07, 0xFE, 0x00, 0x1F, 0xF8, 0x00,\n  0x7F, 0xE0, 0x01, 0xF7, 0x80, 0x07, 0x9E, 0x00, 0x1E, 0x7C, 0x00, 0xF8,\n  0xF0, 0x03, 0xC3, 0xC0, 0x0F, 0x07, 0x00, 0x38, 0x1E, 0x01, 0xE0, 0x38,\n  0x07, 0x00, 0x70, 0x38, 0x00, 0xE1, 0xC0, 0x00, 0xFC, 0x00, 0x00, 0x80,\n  0x1C, 0x03, 0xE0, 0x7F, 0x0C, 0x78, 0x03, 0xC0, 0x1E, 0x00, 0xF0, 0x07,\n  0x80, 0x3C, 0x01, 0xE0, 0x0F, 0x00, 0x78, 0x03, 0xC0, 0x1E, 0x00, 0xF0,\n  0x07, 0x80, 0x3C, 0x01, 0xE0, 0x0F, 0x00, 0x78, 0x03, 0xC0, 0x1E, 0x00,\n  0xF0, 0x07, 0x80, 0x3C, 0x01, 0xE0, 0x0F, 0x00, 0x78, 0x03, 0xC0, 0x3F,\n  0x0F, 0xFF, 0x01, 0xF8, 0x00, 0x3F, 0xF0, 0x07, 0xFF, 0xE0, 0x70, 0x3F,\n  0x83, 0x00, 0x7C, 0x30, 0x01, 0xF1, 0x00, 0x0F, 0x98, 0x00, 0x3C, 0x80,\n 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 0x07, 0xC0, 0x00, 0xF8, 0x1F, 0x00, 0x03, 0xE0, 0x7C, 0x00, 0x0F, 0x81,\n  0xF0, 0x00, 0x3E, 0x07, 0xC0, 0x00, 0xF8, 0x1F, 0x00, 0x03, 0xE0, 0xFE,\n  0x00, 0x1F, 0xCF, 0xFE, 0x01, 0xFF, 0xC0, 0xFF, 0xF8, 0xFE, 0x03, 0xE0,\n  0x1F, 0x00, 0xF8, 0x07, 0xC0, 0x3E, 0x01, 0xF0, 0x0F, 0x80, 0x7C, 0x03,\n  0xE0, 0x1F, 0x00, 0xF8, 0x07, 0xC0, 0x3E, 0x01, 0xF0, 0x0F, 0x80, 0x7C,\n  0x03, 0xE0, 0x1F, 0x00, 0xF8, 0x07, 0xC0, 0x3E, 0x01, 0xF0, 0x0F, 0x80,\n  0x7C, 0x03, 0xE0, 0x1F, 0x00, 0xF8, 0x0F, 0xE3, 0xFF, 0xE0, 0x0F, 0xFF,\n  0x80, 0xFE, 0x00, 0x3E, 0x00, 0x1F, 0x00, 0x0F, 0x80, 0x07, 0xC0, 0x03,\n  0xE0, 0x01, 0xF0, 0x00, 0xF8, 0x00, 0x7C, 0x00, 0x3E, 0x00, 0x1F, 0x00,\n  0x0F, 0x80, 0x07, 0xC0, 0x03, 0xE0, 0x01, 0xF0, 0x00, 0xF8, 0x00, 0x7C,\n  0x00, 0x3E, 0x00, 0x1F, 0x00, 0x0F, 0x80, 0x07, 0xC0, 0x03, 0xE0, 0x01,\n  0xF0, 0x00, 0xF8, 0x00, 0x7C, 0x00, 0x3C, 0x0E, 0x1E, 0x0F, 0x8F, 0x07,\n  0xCF, 0x01, 0xFF, 0x00, 0x7E, 0x00, 0xFF, 0xF8, 0x3F, 0xFC, 0x3F, 0xC0,\n  0x07, 0xE0, 0x0F, 0x80, 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0x00, 0x3C, 0x00, 0x78, 0x01, 0xF8, 0x0F, 0xFC,\n  0x00, 0x1F, 0x91, 0x87, 0x98, 0x1D, 0xC0, 0x6E, 0x03, 0x70, 0x0B, 0xC0,\n  0x5F, 0x80, 0x7E, 0x01, 0xFC, 0x07, 0xF0, 0x0F, 0xE0, 0x3F, 0x00, 0x7E,\n  0x01, 0xF0, 0x07, 0xC0, 0x3E, 0x01, 0xF8, 0x0D, 0xE0, 0xC8, 0xF8, 0x00,\n  0x04, 0x00, 0xC0, 0x0C, 0x01, 0xC0, 0x3C, 0x07, 0xFC, 0xFF, 0xC3, 0xC0,\n  0x3C, 0x03, 0xC0, 0x3C, 0x03, 0xC0, 0x3C, 0x03, 0xC0, 0x3C, 0x03, 0xC0,\n  0x3C, 0x03, 0xC0, 0x3C, 0x03, 0xC0, 0x3C, 0x03, 0xC0, 0x3C, 0x03, 0xE2,\n  0x1F, 0xC0, 0xF8, 0xFC, 0x0F, 0xE1, 0xF0, 0x0F, 0x83, 0xC0, 0x1E, 0x0F,\n  0x00, 0x78, 0x3C, 0x01, 0xE0, 0xF0, 0x07, 0x83, 0xC0, 0x1E, 0x0F, 0x00,\n  0x78, 0x3C, 0x01, 0xE0, 0xF0, 0x07, 0x83, 0xC0, 0x1E, 0x0F, 0x00, 0x78,\n  0x3C, 0x01, 0xE0, 0xF0, 0x07, 0x83, 0xC0, 0x1E, 0x0F, 0x00, 0x78, 0x3C,\n  0x01, 0xE0, 0xF8, 0x0F, 0x81, 0xF0, 0xFF, 0x03, 0xFE, 0x7F, 0x07, 0xE1,\n  0xC0, 0xFF, 0x81, 0xFC, 0xFC, 0x01, 0xC1, 0xE0, 0x07, 0x07, 0x80, 0x18,\n  0x0F, 0x00, 0x60, 0x3C, 0x01, 0x00, 0x78, 0x0C, 0x01, 0xE0, 0x30, 0x07,\n  0x81, 0x80, 0x0F, 0x06, 0x00, 0x3C, 0x10, 0x00, 0x78, 0xC0, 0x01, 0xE3,\n  0x00, 0x03, 0x98, 0x00, 0x0F, 0x60, 0x00, 0x3D, 0x00, 0x00, 0x7C, 0x00,\n  0x01, 0xF0, 0x00, 0x03, 0x80, 0x00, 0x0E, 0x00, 0x00, 0x30, 0x00, 0x00,\n  0x40, 0x00, 0xFF, 0x8F, 0xF8, 0x3F, 0x7E, 0x07, 0xE0, 0x0E, 0x3E, 0x03,\n  0xC0, 0x0C, 0x1E, 0x03, 0xE0, 0x0C, 0x1E, 0x01, 0xE0, 0x0C, 0x1E, 0x01,\n  0xE0, 0x18, 0x0F, 0x00, 0xF0, 0x18, 0x0F, 0x01, 0xF0, 0x10, 0x07, 0x81,\n  0xF0, 0x30, 0x07, 0x81, 0x78, 0x30, 0x07, 0x83, 0x78, 0x60, 0x03, 0xC3,\n  0x38, 0x60, 0x03, 0xC6, 0x3C, 0x40, 0x01, 0xC6, 0x3C, 0xC0, 0x01, 0xEC,\n  0x1E, 0xC0, 0x01, 0xEC, 0x1F, 0x80, 0x00, 0xF8, 0x0F, 0x80, 0x00, 0xF8,\n  0x0F, 0x00, 0x00, 0x70, 0x0F, 0x00, 0x00, 0x70, 0x07, 0x00, 0x00, 0x60,\n  0x06, 0x00, 0x00, 0x20, 0x02, 0x00, 0x7F, 0xE7, 0xF0, 0x7E, 0x0F, 0x00,\n  0xF8, 0x38, 0x01, 0xE0, 0xC0, 0x07, 0xC6, 0x00, 0x0F, 0x30, 0x00, 0x1E,\n  0xC0, 0x00, 0x7E, 0x00, 0x00, 0xF0, 0x00, 0x01, 0xE0, 0x00, 0x07, 0xC0,\n  0x00, 0x3F, 0x00, 0x00, 0xDE, 0x00, 0x06, 0x7C, 0x00, 0x30, 0xF0, 0x01,\n  0xC1, 0xE0, 0x06, 0x07, 0xC0, 0x30, 0x0F, 0x01, 0xC0, 0x1E, 0x0F, 0x00,\n  0xFC, 0xFE, 0x07, 0xFC, 0xFF, 0xC0, 0xFC, 0xFC, 0x01, 0xE1, 0xE0, 0x03,\n  0x07, 0x80, 0x18, 0x0F, 0x00, 0x60, 0x3C, 0x01, 0x80, 0x78, 0x0C, 0x01,\n  0xE0, 0x30, 0x03, 0xC0, 0xC0, 0x0F, 0x06, 0x00, 0x3E, 0x18, 0x00, 0x78,\n  0x40, 0x01, 0xF3, 0x00, 0x03, 0xCC, 0x00, 0x0F, 0xE0, 0x00, 0x1F, 0x80,\n  0x00, 0x7C, 0x00, 0x00, 0xF0, 0x00, 0x03, 0xC0, 0x00, 0x06, 0x00, 0x00,\n  0x18, 0x00, 0x00, 0x40, 0x00, 0x03, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x60,\n  0x00, 0x01, 0x80, 0x00, 0x0C, 0x00, 0x0F, 0xF0, 0x00, 0x7F, 0x80, 0x01,\n  0xFC, 0x00, 0x03, 0xE0, 0x00, 0x00, 0x7F, 0xFF, 0x9F, 0xFF, 0xE6, 0x00,\n  0xF1, 0x00, 0x78, 0x40, 0x3E, 0x00, 0x0F, 0x00, 0x07, 0x80, 0x03, 0xE0,\n  0x00, 0xF0, 0x00, 0x78, 0x00, 0x3E, 0x00, 0x0F, 0x00, 0x07, 0x80, 0x03,\n  0xE0, 0x01, 0xF0, 0x04, 0x78, 0x01, 0x3E, 0x00, 0xDF, 0x00, 0x37, 0x80,\n  0x1F, 0xFF, 0xFE, 0xFF, 0xFF, 0x80, 0x01, 0xE0, 0x78, 0x1C, 0x07, 0x80,\n  0xE0, 0x1C, 0x03, 0x80, 0x70, 0x0E, 0x01, 0xC0, 0x38, 0x07, 0x00, 0xE0,\n  0x1C, 0x03, 0x80, 0x70, 0x0E, 0x01, 0xC0, 0x70, 0x1C, 0x0E, 0x00, 0x70,\n  0x07, 0x00, 0x70, 0x0E, 0x01, 0xC0, 0x38, 0x07, 0x00, 0xE0, 0x1C, 0x03,\n  0x80, 0x70, 0x0E, 0x01, 0xC0, 0x38, 0x07, 0x00, 0xE0, 0x1C, 0x01, 0xC0,\n  0x1E, 0x00, 0xE0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xE0, 0x0F, 0x00, 0x70, 0x0F, 0x00, 0xE0, 0x1C, 0x03,\n  0x80, 0x70, 0x0E, 0x01, 0xC0, 0x38, 0x07, 0x00, 0xE0, 0x1C, 0x03, 0x80,\n  0x70, 0x0E, 0x01, 0xC0, 0x1C, 0x01, 0xC0, 0x0E, 0x07, 0x01, 0xC0, 0x70,\n  0x0E, 0x01, 0xC0, 0x38, 0x07, 0x00, 0xE0, 0x1C, 0x03, 0x80, 0x70, 0x0E,\n  0x01, 0xC0, 0x38, 0x07, 0x00, 0xE0, 0x3C, 0x07, 0x03, 0xC0, 0xF0, 0x00,\n  0x1F, 0x80, 0x00, 0xFF, 0x80, 0xC7, 0x0F, 0x87, 0xB8, 0x0F, 0xFC, 0x00,\n  0x07, 0xC0 };\n\nconst GFXglyph FreeSerif24pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,  12,    0,    1 },   // 0x20 ' '\n  {     0,   5,  32,  16,    6,  -31 },   // 0x21 '!'\n  {    20,  12,  12,  19,    4,  -31 },   // 0x22 '\"'\n  {    38,  23,  31,  23,    0,  -30 },   // 0x23 '#'\n  {   128,  19,  37,  24,    2,  -33 },   // 0x24 '$'\n  {   216,  33,  32,  39,    3,  -30 },   // 0x25 '%'\n  {   348,  32,  33,  37,    2,  -31 },   // 0x26 '&'\n  {   480,   4,  12,   9,    3,  -31 },   // 0x27 '''\n  {   486,  12,  40,  16,    2,  -31 },   // 0x28 '('\n  {   546,  12,  40,  16,    2,  -30 },   // 0x29 ')'\n  {   606,  16,  19,  24,    4,  -30 },   // 0x2A '*'\n  {   644,  23,  23,  27,    2,  -22 },   // 0x2B '+'\n  {   711,   6,  11,  12,    2,   -4 },   // 0x2C ','\n  {   720,  11,   2,  16,    2,  -10 },   // 0x2D '-'\n  {   723,   5,   5,  12,    3,   -3 },   // 0x2E '.'\n  {   727,  14,  32,  14,    0,  -30 },   // 0x2F '/'\n  {   783,  22,  33,  23,    1,  -31 },   // 0x30 '0'\n  {   874,  13,  32,  24,    5,  -31 },   // 0x31 '1'\n  {   926,  21,  31,  23,    1,  -30 },   // 0x32 '2'\n  {  1008,  18,  32,  23,    2,  -30 },   // 0x33 '3'\n  {  1080,  21,  31,  24,    1,  -30 },   // 0x34 '4'\n  {  1162,  19,  33,  24,    2,  -31 },   // 0x35 '5'\n  {  1241,  21,  33,  23,    2,  -31 },   // 0x36 '6'\n  {  1328,  20,  31,  24,    1,  -30 },   // 0x37 '7'\n  {  1406,  18,  33,  23,    3,  -31 },   // 0x38 '8'\n  {  1481,  21,  33,  24,    1,  -31 },   // 0x39 '9'\n  {  1568,   5,  22,  12,    4,  -20 },   // 0x3A ':'\n  {  1582,   6,  27,  12,    3,  -20 },   // 0x3B ';'\n  {  1603,  24,  25,  27,    1,  -24 },   // 0x3C '<'\n  {  1678,  24,  11,  27,    1,  -16 },   // 0x3D '='\n  {  1711,  24,  25,  27,    2,  -23 },   // 0x3E '>'\n  {  1786,  17,  32,  21,    3,  -31 },   // 0x3F '?'\n  {  1854,  32,  33,  41,    4,  -31 },   // 0x40 '@'\n  {  1986,  32,  32,  34,    1,  -31 },   // 0x41 'A'\n  {  2114,  27,  31,  30,    0,  -30 },   // 0x42 'B'\n  {  2219,  28,  33,  31,    2,  -31 },   // 0x43 'C'\n  {  2335,  31,  31,  34,    1,  -30 },   // 0x44 'D'\n  {  2456,  27,  31,  29,    2,  -30 },   // 0x45 'E'\n  {  2561,  24,  31,  27,    2,  -30 },   // 0x46 'F'\n  {  2654,  31,  33,  35,    2,  -31 },   // 0x47 'G'\n  {  2782,  30,  31,  34,    2,  -30 },   // 0x48 'H'\n  {  2899,  13,  31,  15,    1,  -30 },   // 0x49 'I'\n  {  2950,  17,  32,  18,    0,  -30 },   // 0x4A 'J'\n  {  3018,  32,  31,  33,    1,  -30 },   // 0x4B 'K'\n  {  3142,  26,  31,  29,    2,  -30 },   // 0x4C 'L'\n  {  3243,  39,  31,  41,    1,  -30 },   // 0x4D 'M'\n  {  3395,  32,  32,  34,    1,  -30 },   // 0x4E 'N'\n  {  3523,  30,  33,  34,    2,  -31 },   // 0x4F 'O'\n  {  3647,  23,  31,  27,    2,  -30 },   // 0x50 'P'\n  {  3737,  31,  40,  34,    2,  -31 },   // 0x51 'Q'\n  {  3892,  28,  31,  31,    2,  -30 },   // 0x52 'R'\n  {  4001,  21,  33,  25,    2,  -31 },   // 0x53 'S'\n  {  4088,  27,  31,  28,    1,  -30 },   // 0x54 'T'\n  {  4193,  32,  32,  34,    1,  -30 },   // 0x55 'U'\n  {  4321,  32,  32,  33,    0,  -30 },   // 0x56 'V'\n  {  4449,  44,  32,  45,    0,  -30 },   // 0x57 'W'\n  {  4625,  33,  31,  34,    0,  -30 },   // 0x58 'X'\n  {  4753,  32,  31,  33,    0,  -30 },   // 0x59 'Y'\n  {  4877,  27,  31,  29,    1,  -30 },   // 0x5A 'Z'\n  {  4982,   9,  38,  16,    4,  -30 },   // 0x5B '['\n  {  5025,  14,  32,  14,    0,  -30 },   // 0x5C '\\'\n  {  5081,   9,  38,  16,    3,  -30 },   // 0x5D ']'\n  {  5124,  20,  17,  22,    1,  -30 },   // 0x5E '^'\n  {  5167,  24,   2,  23,    0,    5 },   // 0x5F '_'\n  {  5173,  10,   8,  12,    1,  -31 },   // 0x60 '`'\n  {  5183,  18,  21,  20,    1,  -20 },   // 0x61 'a'\n  {  5231,  21,  32,  24,    1,  -31 },   // 0x62 'b'\n  {  5315,  19,  21,  21,    1,  -20 },   // 0x63 'c'\n  {  5365,  22,  32,  23,    1,  -31 },   // 0x64 'd'\n  {  5453,  18,  21,  21,    1,  -20 },   // 0x65 'e'\n  {  5501,  17,  33,  18,    0,  -32 },   // 0x66 'f'\n  {  5572,  21,  31,  22,    1,  -20 },   // 0x67 'g'\n  {  5654,  22,  32,  23,    0,  -31 },   // 0x68 'h'\n  {  5742,  11,  32,  13,    0,  -31 },   // 0x69 'i'\n  {  5786,  12,  42,  16,    0,  -31 },   // 0x6A 'j'\n  {  5849,  23,  32,  24,    1,  -31 },   // 0x6B 'k'\n  {  5941,  11,  32,  12,    0,  -31 },   // 0x6C 'l'\n  {  5985,  35,  21,  37,    1,  -20 },   // 0x6D 'm'\n  {  6077,  22,  21,  23,    0,  -20 },   // 0x6E 'n'\n  {  6135,  22,  21,  23,    1,  -20 },   // 0x6F 'o'\n  {  6193,  21,  31,  24,    1,  -20 },   // 0x70 'p'\n  {  6275,  21,  31,  23,    1,  -20 },   // 0x71 'q'\n  {  6357,  15,  21,  16,    1,  -20 },   // 0x72 'r'\n  {  6397,  13,  21,  17,    2,  -20 },   // 0x73 's'\n  {  6432,  12,  26,  13,    1,  -25 },   // 0x74 't'\n  {  6471,  22,  21,  23,    1,  -20 },   // 0x75 'u'\n  {  6529,  22,  22,  22,    0,  -20 },   // 0x76 'v'\n  {  6590,  32,  22,  32,    0,  -20 },   // 0x77 'w'\n  {  6678,  22,  21,  23,    0,  -20 },   // 0x78 'x'\n  {  6736,  22,  31,  22,    0,  -20 },   // 0x79 'y'\n  {  6822,  18,  21,  20,    1,  -20 },   // 0x7A 'z'\n  {  6870,  11,  41,  23,    5,  -31 },   // 0x7B '{'\n  {  6927,   3,  32,   9,    3,  -30 },   // 0x7C '|'\n  {  6939,  11,  41,  23,    7,  -31 },   // 0x7D '}'\n  {  6996,  22,   5,  23,    1,  -13 } }; // 0x7E '~'\n\nconst GFXfont FreeSerif24pt7b PROGMEM = {\n  (uint8_t  *)FreeSerif24pt7bBitmaps,\n  (GFXglyph *)FreeSerif24pt7bGlyphs,\n  0x20, 0x7E, 56 };\n\n// Approx. 7682 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeSerif9pt7b.h",
    "content": "const uint8_t FreeSerif9pt7bBitmaps[] PROGMEM = {\n  0xFF, 0xEA, 0x03, 0xDE, 0xF7, 0x20, 0x11, 0x09, 0x04, 0x82, 0x4F, 0xF9,\n  0x10, 0x89, 0xFF, 0x24, 0x12, 0x09, 0x0C, 0x80, 0x10, 0x7C, 0xD6, 0xD2,\n  0xD0, 0xF0, 0x38, 0x1E, 0x17, 0x93, 0x93, 0xD6, 0x7C, 0x10, 0x38, 0x43,\n  0x3C, 0x39, 0x21, 0x8A, 0x0C, 0x50, 0x65, 0x39, 0xCB, 0x20, 0xB9, 0x05,\n  0x88, 0x4C, 0x44, 0x64, 0x21, 0xC0, 0x0E, 0x00, 0xC8, 0x06, 0x40, 0x32,\n  0x01, 0xA0, 0x07, 0x78, 0x31, 0x87, 0x88, 0x46, 0x86, 0x34, 0x30, 0xC1,\n  0xC7, 0x17, 0xCF, 0x00, 0xFE, 0x08, 0x88, 0x84, 0x63, 0x18, 0xC6, 0x10,\n  0x82, 0x08, 0x20, 0x82, 0x08, 0x21, 0x0C, 0x63, 0x18, 0xC4, 0x22, 0x22,\n  0x00, 0x63, 0x9A, 0xDC, 0x72, 0xB6, 0x08, 0x08, 0x04, 0x02, 0x01, 0x0F,\n  0xF8, 0x40, 0x20, 0x10, 0x08, 0x00, 0xD8, 0xF0, 0xF0, 0x08, 0x84, 0x22,\n  0x10, 0x8C, 0x42, 0x31, 0x00, 0x1C, 0x31, 0x98, 0xD8, 0x3C, 0x1E, 0x0F,\n  0x07, 0x83, 0xC1, 0xE0, 0xD8, 0xC4, 0x61, 0xC0, 0x13, 0x8C, 0x63, 0x18,\n  0xC6, 0x31, 0x8C, 0x67, 0x80, 0x3C, 0x4E, 0x86, 0x06, 0x06, 0x04, 0x0C,\n  0x08, 0x10, 0x20, 0x41, 0xFE, 0x3C, 0xC6, 0x06, 0x04, 0x1C, 0x3E, 0x07,\n  0x03, 0x03, 0x03, 0x06, 0xF8, 0x04, 0x18, 0x71, 0x64, 0xC9, 0xA3, 0x46,\n  0xFE, 0x18, 0x30, 0x60, 0x0F, 0x10, 0x20, 0x3C, 0x0E, 0x07, 0x03, 0x03,\n  0x03, 0x02, 0x04, 0xF8, 0x07, 0x1C, 0x30, 0x60, 0x60, 0xDC, 0xE6, 0xC3,\n  0xC3, 0xC3, 0x43, 0x66, 0x3C, 0x7F, 0x82, 0x02, 0x02, 0x04, 0x04, 0x04,\n  0x08, 0x08, 0x08, 0x10, 0x10, 0x3C, 0x8F, 0x1E, 0x3E, 0x4F, 0x06, 0x36,\n  0xC7, 0x8F, 0x1B, 0x33, 0xC0, 0x3C, 0x66, 0xC2, 0xC3, 0xC3, 0xC3, 0xC3,\n  0x63, 0x3F, 0x06, 0x06, 0x0C, 0x38, 0x60, 0xF0, 0x0F, 0xD8, 0x00, 0x03,\n  0x28, 0x01, 0x87, 0x0E, 0x1C, 0x0C, 0x03, 0x80, 0x70, 0x0E, 0x00, 0x80,\n  0xFF, 0x80, 0x00, 0x00, 0x0F, 0xF8, 0x80, 0x1C, 0x01, 0xC0, 0x1C, 0x01,\n  0xC0, 0xE0, 0xE0, 0xE0, 0xC0, 0x00, 0x79, 0x1A, 0x18, 0x30, 0x60, 0x83,\n  0x04, 0x10, 0x20, 0x40, 0x03, 0x00, 0x0F, 0x83, 0x8C, 0x60, 0x26, 0x02,\n  0xC7, 0x9C, 0xC9, 0xD8, 0x9D, 0x99, 0xD9, 0x26, 0xEC, 0x60, 0x03, 0x04,\n  0x0F, 0x80, 0x02, 0x00, 0x10, 0x01, 0xC0, 0x16, 0x00, 0x98, 0x04, 0xC0,\n  0x43, 0x03, 0xF8, 0x20, 0x61, 0x03, 0x18, 0x1D, 0xE1, 0xF0, 0xFF, 0x86,\n  0x1C, 0xC1, 0x98, 0x33, 0x0C, 0x7E, 0x0C, 0x31, 0x83, 0x30, 0x66, 0x0C,\n  0xC3, 0x7F, 0xC0, 0x1F, 0x26, 0x1D, 0x81, 0xE0, 0x1C, 0x01, 0x80, 0x30,\n  0x06, 0x00, 0xC0, 0x0C, 0x00, 0xC1, 0x8F, 0xC0, 0xFF, 0x03, 0x1C, 0x30,\n  0x63, 0x07, 0x30, 0x33, 0x03, 0x30, 0x33, 0x03, 0x30, 0x33, 0x06, 0x30,\n  0xCF, 0xF0, 0xFF, 0x98, 0x26, 0x01, 0x80, 0x61, 0x1F, 0xC6, 0x11, 0x80,\n  0x60, 0x18, 0x16, 0x0F, 0xFE, 0xFF, 0xB0, 0x58, 0x0C, 0x06, 0x13, 0xF9,\n  0x84, 0xC0, 0x60, 0x30, 0x18, 0x1E, 0x00, 0x1F, 0x23, 0x0E, 0x60, 0x26,\n  0x00, 0xC0, 0x0C, 0x0F, 0xC0, 0x6C, 0x06, 0xC0, 0x66, 0x06, 0x30, 0x60,\n  0xF8, 0xF1, 0xEC, 0x19, 0x83, 0x30, 0x66, 0x0C, 0xFF, 0x98, 0x33, 0x06,\n  0x60, 0xCC, 0x19, 0x83, 0x78, 0xF0, 0xF6, 0x66, 0x66, 0x66, 0x66, 0x6F,\n  0x3C, 0x61, 0x86, 0x18, 0x61, 0x86, 0x18, 0x6D, 0xBC, 0xF3, 0xE6, 0x08,\n  0x61, 0x06, 0x20, 0x64, 0x07, 0x80, 0x6C, 0x06, 0x60, 0x63, 0x06, 0x18,\n  0x60, 0xCF, 0x3F, 0xF0, 0x18, 0x06, 0x01, 0x80, 0x60, 0x18, 0x06, 0x01,\n  0x80, 0x60, 0x18, 0x16, 0x0B, 0xFE, 0xF0, 0x0E, 0x70, 0x38, 0xE0, 0x71,\n  0xE1, 0x62, 0xC2, 0xC5, 0xC9, 0x89, 0x93, 0x13, 0x26, 0x23, 0x8C, 0x47,\n  0x18, 0x84, 0x33, 0x88, 0xF0, 0xE0, 0xEE, 0x09, 0xC1, 0x2C, 0x25, 0xC4,\n  0x9C, 0x91, 0x92, 0x1A, 0x41, 0xC8, 0x19, 0x03, 0x70, 0x20, 0x1F, 0x06,\n  0x31, 0x83, 0x20, 0x2C, 0x07, 0x80, 0xF0, 0x1E, 0x03, 0xC0, 0x68, 0x09,\n  0x83, 0x18, 0xC1, 0xF0, 0xFE, 0x31, 0x98, 0x6C, 0x36, 0x1B, 0x19, 0xF8,\n  0xC0, 0x60, 0x30, 0x18, 0x1E, 0x00, 0x1F, 0x06, 0x31, 0x83, 0x20, 0x2C,\n  0x07, 0x80, 0xF0, 0x1E, 0x03, 0xC0, 0x68, 0x19, 0x83, 0x18, 0xC0, 0xE0,\n  0x0E, 0x00, 0xE0, 0x07, 0xFE, 0x0C, 0x61, 0x86, 0x30, 0xC6, 0x18, 0xC6,\n  0x1F, 0x83, 0x70, 0x67, 0x0C, 0x71, 0x87, 0x78, 0x70, 0x1D, 0x31, 0x98,\n  0x4C, 0x07, 0x80, 0xE0, 0x1C, 0x07, 0x01, 0xA0, 0xD8, 0xCB, 0xC0, 0xFF,\n  0xF8, 0xCE, 0x18, 0x83, 0x00, 0x60, 0x0C, 0x01, 0x80, 0x30, 0x06, 0x00,\n  0xC0, 0x18, 0x07, 0x80, 0xF0, 0xEC, 0x09, 0x81, 0x30, 0x26, 0x04, 0xC0,\n  0x98, 0x13, 0x02, 0x60, 0x4C, 0x08, 0xC2, 0x0F, 0x80, 0xF8, 0x77, 0x02,\n  0x30, 0x23, 0x04, 0x18, 0x41, 0x84, 0x0C, 0x80, 0xC8, 0x07, 0x00, 0x70,\n  0x02, 0x00, 0x20, 0xFB, 0xE7, 0xB0, 0xC0, 0x8C, 0x20, 0x86, 0x18, 0x41,\n  0x8C, 0x40, 0xCB, 0x20, 0x65, 0x90, 0x1A, 0x70, 0x0E, 0x38, 0x03, 0x1C,\n  0x01, 0x04, 0x00, 0x82, 0x00, 0xFC, 0xF9, 0x83, 0x06, 0x10, 0x19, 0x00,\n  0xD0, 0x03, 0x00, 0x1C, 0x01, 0x30, 0x11, 0xC1, 0x86, 0x08, 0x19, 0xE3,\n  0xF0, 0xF8, 0xF6, 0x06, 0x30, 0x41, 0x88, 0x1D, 0x00, 0xD0, 0x06, 0x00,\n  0x60, 0x06, 0x00, 0x60, 0x06, 0x00, 0xF0, 0x3F, 0xCC, 0x11, 0x06, 0x01,\n  0x80, 0x70, 0x0C, 0x03, 0x00, 0xE0, 0x38, 0x06, 0x05, 0xC1, 0x7F, 0xE0,\n  0xFB, 0x6D, 0xB6, 0xDB, 0x6D, 0xB8, 0x82, 0x10, 0x82, 0x10, 0x86, 0x10,\n  0x86, 0x10, 0xED, 0xB6, 0xDB, 0x6D, 0xB6, 0xF8, 0x18, 0x1C, 0x34, 0x26,\n  0x62, 0x42, 0xC1, 0xFF, 0x80, 0x84, 0x20, 0x79, 0x98, 0x30, 0xE6, 0xD9,\n  0xB3, 0x3F, 0x20, 0x70, 0x18, 0x0C, 0x06, 0x03, 0x71, 0xCC, 0xC3, 0x61,\n  0xB0, 0xD8, 0x6C, 0x63, 0xE0, 0x3C, 0xCF, 0x06, 0x0C, 0x18, 0x18, 0x9E,\n  0x01, 0x03, 0x80, 0xC0, 0x60, 0x31, 0xD9, 0x9D, 0x86, 0xC3, 0x61, 0xB0,\n  0xCC, 0x63, 0xF0, 0x3C, 0x46, 0xFE, 0xC0, 0xC0, 0xE1, 0x62, 0x3C, 0x1E,\n  0x41, 0x83, 0x06, 0x1E, 0x18, 0x30, 0x60, 0xC1, 0x83, 0x0F, 0x00, 0x3C,\n  0x19, 0xF6, 0x31, 0x8C, 0x1E, 0x08, 0x04, 0x01, 0xFC, 0x40, 0xB0, 0x2E,\n  0x11, 0xF8, 0x20, 0x70, 0x18, 0x0C, 0x06, 0x03, 0x71, 0xCC, 0xC6, 0x63,\n  0x31, 0x98, 0xCC, 0x6F, 0x78, 0x60, 0x02, 0xE6, 0x66, 0x66, 0xF0, 0x18,\n  0x00, 0x33, 0x8C, 0x63, 0x18, 0xC6, 0x31, 0x8B, 0x80, 0x20, 0x70, 0x18,\n  0x0C, 0x06, 0x03, 0x3D, 0x88, 0xD8, 0x78, 0x36, 0x19, 0x8C, 0x6F, 0x78,\n  0x2E, 0x66, 0x66, 0x66, 0x66, 0x66, 0xF0, 0xEE, 0x71, 0xCE, 0x66, 0x31,\n  0x98, 0xC6, 0x63, 0x19, 0x8C, 0x66, 0x31, 0xBD, 0xEF, 0xEE, 0x39, 0x98,\n  0xCC, 0x66, 0x33, 0x19, 0x8D, 0xEF, 0x3E, 0x31, 0xB0, 0x78, 0x3C, 0x1E,\n  0x0D, 0x8C, 0x7C, 0xEE, 0x39, 0x98, 0x6C, 0x36, 0x1B, 0x0D, 0x8C, 0xFC,\n  0x60, 0x30, 0x18, 0x1E, 0x00, 0x3D, 0x31, 0xB0, 0xD8, 0x6C, 0x36, 0x1B,\n  0x8C, 0xFE, 0x03, 0x01, 0x80, 0xC0, 0xF0, 0x6D, 0xC6, 0x18, 0x61, 0x86,\n  0x3C, 0x76, 0x38, 0x58, 0x3E, 0x38, 0xFE, 0x27, 0x98, 0xC6, 0x31, 0x8C,\n  0x38, 0xE7, 0x31, 0x98, 0xCC, 0x66, 0x33, 0x19, 0x8C, 0x7F, 0xF3, 0x61,\n  0x22, 0x32, 0x14, 0x1C, 0x08, 0x08, 0xEF, 0x36, 0x61, 0x62, 0x22, 0x32,\n  0x35, 0x41, 0x9C, 0x18, 0x81, 0x08, 0xF7, 0x12, 0x0E, 0x03, 0x01, 0xC1,\n  0x21, 0x09, 0xCF, 0xF3, 0x61, 0x62, 0x32, 0x34, 0x14, 0x1C, 0x08, 0x08,\n  0x08, 0x10, 0xE0, 0xFD, 0x18, 0x60, 0x83, 0x0C, 0x70, 0xFE, 0x19, 0x8C,\n  0x63, 0x18, 0xC4, 0x61, 0x8C, 0x63, 0x18, 0xC3, 0xFF, 0xF0, 0xC3, 0x18,\n  0xC6, 0x31, 0x84, 0x33, 0x18, 0xC6, 0x31, 0x98, 0x70, 0x24, 0xC1, 0xC0 };\n\nconst GFXglyph FreeSerif9pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,   5,    0,    1 },   // 0x20 ' '\n  {     0,   2,  12,   6,    2,  -11 },   // 0x21 '!'\n  {     3,   5,   4,   7,    1,  -11 },   // 0x22 '\"'\n  {     6,   9,  12,   9,    0,  -11 },   // 0x23 '#'\n  {    20,   8,  14,   9,    1,  -12 },   // 0x24 '$'\n  {    34,  13,  12,  15,    1,  -11 },   // 0x25 '%'\n  {    54,  13,  13,  14,    1,  -12 },   // 0x26 '&'\n  {    76,   2,   4,   4,    1,  -11 },   // 0x27 '''\n  {    77,   5,  15,   6,    1,  -11 },   // 0x28 '('\n  {    87,   5,  15,   6,    0,  -11 },   // 0x29 ')'\n  {    97,   6,   8,   9,    3,  -11 },   // 0x2A '*'\n  {   103,   9,   9,  10,    0,   -8 },   // 0x2B '+'\n  {   114,   2,   3,   4,    2,    0 },   // 0x2C ','\n  {   115,   4,   1,   6,    1,   -3 },   // 0x2D '-'\n  {   116,   2,   2,   5,    1,   -1 },   // 0x2E '.'\n  {   117,   5,  12,   5,    0,  -11 },   // 0x2F '/'\n  {   125,   9,  13,   9,    0,  -12 },   // 0x30 '0'\n  {   140,   5,  13,   9,    2,  -12 },   // 0x31 '1'\n  {   149,   8,  12,   9,    1,  -11 },   // 0x32 '2'\n  {   161,   8,  12,   9,    0,  -11 },   // 0x33 '3'\n  {   173,   7,  12,   9,    1,  -11 },   // 0x34 '4'\n  {   184,   8,  12,   9,    0,  -11 },   // 0x35 '5'\n  {   196,   8,  13,   9,    1,  -12 },   // 0x36 '6'\n  {   209,   8,  12,   9,    0,  -11 },   // 0x37 '7'\n  {   221,   7,  13,   9,    1,  -12 },   // 0x38 '8'\n  {   233,   8,  14,   9,    1,  -12 },   // 0x39 '9'\n  {   247,   2,   8,   5,    1,   -7 },   // 0x3A ':'\n  {   249,   3,  10,   5,    1,   -7 },   // 0x3B ';'\n  {   253,   9,   9,  10,    1,   -8 },   // 0x3C '<'\n  {   264,   9,   5,  10,    1,   -6 },   // 0x3D '='\n  {   270,  10,   9,  10,    0,   -8 },   // 0x3E '>'\n  {   282,   7,  13,   8,    1,  -12 },   // 0x3F '?'\n  {   294,  12,  13,  16,    2,  -12 },   // 0x40 '@'\n  {   314,  13,  12,  13,    0,  -11 },   // 0x41 'A'\n  {   334,  11,  12,  11,    0,  -11 },   // 0x42 'B'\n  {   351,  11,  12,  12,    1,  -11 },   // 0x43 'C'\n  {   368,  12,  12,  13,    0,  -11 },   // 0x44 'D'\n  {   386,  10,  12,  11,    1,  -11 },   // 0x45 'E'\n  {   401,   9,  12,  10,    1,  -11 },   // 0x46 'F'\n  {   415,  12,  12,  13,    1,  -11 },   // 0x47 'G'\n  {   433,  11,  12,  13,    1,  -11 },   // 0x48 'H'\n  {   450,   4,  12,   6,    1,  -11 },   // 0x49 'I'\n  {   456,   6,  12,   7,    0,  -11 },   // 0x4A 'J'\n  {   465,  12,  12,  13,    1,  -11 },   // 0x4B 'K'\n  {   483,  10,  12,  11,    1,  -11 },   // 0x4C 'L'\n  {   498,  15,  12,  16,    0,  -11 },   // 0x4D 'M'\n  {   521,  11,  12,  13,    1,  -11 },   // 0x4E 'N'\n  {   538,  11,  13,  13,    1,  -12 },   // 0x4F 'O'\n  {   556,   9,  12,  10,    1,  -11 },   // 0x50 'P'\n  {   570,  11,  16,  13,    1,  -12 },   // 0x51 'Q'\n  {   592,  11,  12,  12,    1,  -11 },   // 0x52 'R'\n  {   609,   9,  12,  10,    0,  -11 },   // 0x53 'S'\n  {   623,  11,  12,  11,    0,  -11 },   // 0x54 'T'\n  {   640,  11,  12,  13,    1,  -11 },   // 0x55 'U'\n  {   657,  12,  12,  13,    0,  -11 },   // 0x56 'V'\n  {   675,  17,  12,  17,    0,  -11 },   // 0x57 'W'\n  {   701,  13,  12,  13,    0,  -11 },   // 0x58 'X'\n  {   721,  12,  12,  13,    0,  -11 },   // 0x59 'Y'\n  {   739,  11,  12,  11,    0,  -11 },   // 0x5A 'Z'\n  {   756,   3,  15,   6,    2,  -11 },   // 0x5B '['\n  {   762,   5,  12,   5,    0,  -11 },   // 0x5C '\\'\n  {   770,   3,  15,   6,    1,  -11 },   // 0x5D ']'\n  {   776,   8,   7,   8,    0,  -11 },   // 0x5E '^'\n  {   783,   9,   1,   9,    0,    2 },   // 0x5F '_'\n  {   785,   4,   3,   5,    0,  -11 },   // 0x60 '`'\n  {   787,   7,   8,   8,    1,   -7 },   // 0x61 'a'\n  {   794,   9,  13,   9,    0,  -12 },   // 0x62 'b'\n  {   809,   7,   8,   8,    0,   -7 },   // 0x63 'c'\n  {   816,   9,  13,   9,    0,  -12 },   // 0x64 'd'\n  {   831,   8,   8,   8,    0,   -7 },   // 0x65 'e'\n  {   839,   7,  13,   7,    1,  -12 },   // 0x66 'f'\n  {   851,  10,  12,   8,    0,   -7 },   // 0x67 'g'\n  {   866,   9,  13,   9,    0,  -12 },   // 0x68 'h'\n  {   881,   4,  11,   5,    1,  -10 },   // 0x69 'i'\n  {   887,   5,  15,   6,    0,  -10 },   // 0x6A 'j'\n  {   897,   9,  13,   9,    1,  -12 },   // 0x6B 'k'\n  {   912,   4,  13,   5,    1,  -12 },   // 0x6C 'l'\n  {   919,  14,   8,  14,    0,   -7 },   // 0x6D 'm'\n  {   933,   9,   8,   9,    0,   -7 },   // 0x6E 'n'\n  {   942,   9,   8,   9,    0,   -7 },   // 0x6F 'o'\n  {   951,   9,  12,   9,    0,   -7 },   // 0x70 'p'\n  {   965,   9,  12,   9,    0,   -7 },   // 0x71 'q'\n  {   979,   6,   8,   6,    0,   -7 },   // 0x72 'r'\n  {   985,   6,   8,   7,    1,   -7 },   // 0x73 's'\n  {   991,   5,   9,   5,    0,   -8 },   // 0x74 't'\n  {   997,   9,   8,   9,    0,   -7 },   // 0x75 'u'\n  {  1006,   8,   8,   8,    0,   -7 },   // 0x76 'v'\n  {  1014,  12,   8,  12,    0,   -7 },   // 0x77 'w'\n  {  1026,   9,   8,   9,    0,   -7 },   // 0x78 'x'\n  {  1035,   8,  12,   8,    0,   -7 },   // 0x79 'y'\n  {  1047,   7,   8,   7,    1,   -7 },   // 0x7A 'z'\n  {  1054,   5,  16,   9,    1,  -12 },   // 0x7B '{'\n  {  1064,   1,  12,   4,    1,  -11 },   // 0x7C '|'\n  {  1066,   5,  16,   9,    3,  -11 },   // 0x7D '}'\n  {  1076,   9,   3,   9,    0,   -5 } }; // 0x7E '~'\n\nconst GFXfont FreeSerif9pt7b PROGMEM = {\n  (uint8_t  *)FreeSerif9pt7bBitmaps,\n  (GFXglyph *)FreeSerif9pt7bGlyphs,\n  0x20, 0x7E, 22 };\n\n// Approx. 1752 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeSerifBold12pt7b.h",
    "content": "const uint8_t FreeSerifBold12pt7bBitmaps[] PROGMEM = {\n  0x7F, 0xFF, 0x77, 0x66, 0x22, 0x00, 0x6F, 0xF7, 0xE3, 0xF1, 0xF8, 0xFC,\n  0x7E, 0x3A, 0x09, 0x04, 0x0C, 0x40, 0xCC, 0x0C, 0xC0, 0x8C, 0x18, 0xC7,\n  0xFF, 0x18, 0xC1, 0x88, 0x19, 0x81, 0x98, 0xFF, 0xE3, 0x18, 0x31, 0x83,\n  0x18, 0x33, 0x03, 0x30, 0x08, 0x01, 0x00, 0xFC, 0x24, 0xEC, 0x8D, 0x90,\n  0xBA, 0x07, 0xC0, 0x7E, 0x07, 0xF0, 0x7F, 0x07, 0xF0, 0x9F, 0x11, 0xE2,\n  0x3E, 0x46, 0xE9, 0xC7, 0xC0, 0x20, 0x04, 0x00, 0x1E, 0x0C, 0x0E, 0x7F,\n  0x07, 0x10, 0x83, 0xC4, 0x40, 0xE1, 0x30, 0x38, 0x88, 0x0E, 0x26, 0x03,\n  0x91, 0x1E, 0x78, 0x8E, 0x40, 0x27, 0x10, 0x11, 0xC4, 0x0C, 0xE1, 0x02,\n  0x38, 0x81, 0x0E, 0x20, 0x43, 0x90, 0x20, 0x78, 0x03, 0xE0, 0x01, 0x9E,\n  0x00, 0xE3, 0x80, 0x38, 0xE0, 0x0F, 0x30, 0x03, 0xF0, 0x00, 0x78, 0x7C,\n  0x1F, 0x06, 0x1B, 0xE1, 0x1C, 0x7C, 0x8F, 0x1F, 0x23, 0xC3, 0xF0, 0xF8,\n  0x7C, 0x3E, 0x0F, 0x97, 0xC7, 0xFC, 0xFE, 0x3E, 0xFF, 0xFE, 0x90, 0x00,\n  0x31, 0x0C, 0x31, 0x86, 0x38, 0xE3, 0x8E, 0x38, 0xE3, 0x86, 0x18, 0x60,\n  0xC1, 0x02, 0x04, 0x03, 0x06, 0x0C, 0x30, 0x61, 0x87, 0x1C, 0x71, 0xC7,\n  0x1C, 0x71, 0x86, 0x38, 0xC2, 0x10, 0x80, 0x1C, 0x6E, 0xFA, 0xEF, 0xF1,\n  0xC7, 0xFF, 0xAF, 0xBB, 0x1C, 0x04, 0x00, 0x06, 0x00, 0x60, 0x06, 0x00,\n  0x60, 0x06, 0x0F, 0xFF, 0xFF, 0xF0, 0x60, 0x06, 0x00, 0x60, 0x06, 0x00,\n  0x60, 0x6F, 0xF7, 0x11, 0x24, 0xFF, 0xFF, 0xC0, 0x6F, 0xF6, 0x03, 0x07,\n  0x06, 0x06, 0x0C, 0x0C, 0x0C, 0x18, 0x18, 0x18, 0x30, 0x30, 0x30, 0x60,\n  0x60, 0x60, 0xC0, 0x0E, 0x07, 0x71, 0xC7, 0x38, 0xEF, 0x1D, 0xE3, 0xFC,\n  0x7F, 0x8F, 0xF1, 0xFE, 0x3F, 0xC7, 0xF8, 0xF7, 0x1C, 0xE3, 0x8E, 0xE0,\n  0xF8, 0x06, 0x0F, 0x1F, 0x83, 0xC1, 0xE0, 0xF0, 0x78, 0x3C, 0x1E, 0x0F,\n  0x07, 0x83, 0xC1, 0xE0, 0xF0, 0xF9, 0xFF, 0x0F, 0x03, 0xFC, 0x7F, 0xC4,\n  0x3E, 0x01, 0xE0, 0x1E, 0x01, 0xE0, 0x1C, 0x03, 0x80, 0x30, 0x06, 0x00,\n  0xC1, 0x18, 0x13, 0xFE, 0x7F, 0xEF, 0xFE, 0x1F, 0x0C, 0xFA, 0x0F, 0x01,\n  0xE0, 0x38, 0x0E, 0x03, 0xE0, 0x3E, 0x03, 0xE0, 0x3C, 0x03, 0x80, 0x70,\n  0x0D, 0xC1, 0xBC, 0x43, 0xF0, 0x03, 0x80, 0xE0, 0x78, 0x3E, 0x17, 0x89,\n  0xE2, 0x79, 0x1E, 0x87, 0xA1, 0xEF, 0xFF, 0xFF, 0xFF, 0xC1, 0xE0, 0x78,\n  0x1E, 0x3F, 0xE7, 0xF8, 0xFF, 0x10, 0x04, 0x00, 0xF8, 0x1F, 0xC7, 0xFC,\n  0x1F, 0xC0, 0x78, 0x07, 0x00, 0x60, 0x0D, 0xC1, 0x3C, 0x43, 0xF0, 0x00,\n  0xE0, 0xF0, 0x38, 0x1E, 0x07, 0x80, 0xF0, 0x3F, 0xE7, 0x9E, 0xF1, 0xFE,\n  0x3F, 0xC7, 0xF8, 0xF7, 0x1E, 0xE3, 0x8E, 0x60, 0xF8, 0x7F, 0xEF, 0xFD,\n  0xFF, 0xA0, 0x68, 0x0C, 0x03, 0x80, 0x60, 0x0C, 0x03, 0x00, 0x60, 0x0C,\n  0x03, 0x00, 0x60, 0x1C, 0x03, 0x00, 0x60, 0x1F, 0x0E, 0x73, 0x87, 0x70,\n  0xEF, 0x1D, 0xF3, 0x1F, 0x81, 0xF8, 0x1F, 0xCC, 0xFB, 0x8F, 0xF0, 0xFE,\n  0x1F, 0xC3, 0x9C, 0xF1, 0xF8, 0x1F, 0x06, 0x71, 0xC7, 0x78, 0xEF, 0x1F,\n  0xE3, 0xFC, 0x7F, 0x8F, 0x79, 0xE7, 0xFC, 0x0F, 0x01, 0xC0, 0x78, 0x1C,\n  0x0F, 0x07, 0x00, 0x6F, 0xF6, 0x00, 0x06, 0xFF, 0x60, 0x6F, 0xF6, 0x00,\n  0x06, 0xFF, 0x71, 0x22, 0xC0, 0x00, 0x04, 0x00, 0x70, 0x07, 0xC0, 0xFC,\n  0x0F, 0x80, 0xF8, 0x0F, 0x80, 0x1F, 0x00, 0x1F, 0x00, 0x1F, 0x00, 0x1F,\n  0x00, 0x1F, 0x00, 0x1C, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xF0, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0x0F, 0xFF, 0xFF, 0xFF, 0x00, 0x03, 0x80, 0x0F,\n  0x80, 0x0F, 0x80, 0x0F, 0x80, 0x0F, 0x80, 0x0F, 0x80, 0x1F, 0x01, 0xF0,\n  0x1F, 0x03, 0xF0, 0x3E, 0x00, 0xE0, 0x02, 0x00, 0x00, 0x3E, 0x11, 0xEC,\n  0x3F, 0x8F, 0xE3, 0xC0, 0xF0, 0x78, 0x18, 0x08, 0x02, 0x00, 0x00, 0x00,\n  0x1C, 0x07, 0x81, 0xE0, 0x30, 0x03, 0xF0, 0x0E, 0x18, 0x18, 0x04, 0x30,\n  0x66, 0x70, 0xDB, 0x61, 0x99, 0xE3, 0x19, 0xE3, 0x31, 0xE6, 0x31, 0xE6,\n  0x31, 0xE6, 0xF2, 0x66, 0xB2, 0x73, 0x3C, 0x38, 0x00, 0x1E, 0x04, 0x03,\n  0xF8, 0x00, 0x80, 0x00, 0xC0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x3E, 0x00,\n  0x1F, 0x00, 0x1B, 0xC0, 0x09, 0xE0, 0x0C, 0xF8, 0x04, 0x3C, 0x02, 0x1F,\n  0x03, 0xFF, 0x81, 0x03, 0xC1, 0x80, 0xF0, 0x80, 0x7D, 0xF0, 0xFF, 0xFF,\n  0xC0, 0xF3, 0xC3, 0xC7, 0x8F, 0x1E, 0x3C, 0x78, 0xF1, 0xE3, 0xCE, 0x0F,\n  0xF0, 0x3C, 0x70, 0xF0, 0xE3, 0xC3, 0xCF, 0x0F, 0x3C, 0x3C, 0xF0, 0xE3,\n  0xC7, 0xBF, 0xF8, 0x07, 0xE2, 0x38, 0x7C, 0xE0, 0x3B, 0xC0, 0x37, 0x00,\n  0x7E, 0x00, 0x7C, 0x00, 0x78, 0x00, 0xF0, 0x01, 0xE0, 0x03, 0xC0, 0x03,\n  0x80, 0x07, 0x80, 0x27, 0x00, 0xC7, 0x86, 0x03, 0xF0, 0xFF, 0xE0, 0x1E,\n  0x1E, 0x0F, 0x07, 0x87, 0x81, 0xE3, 0xC0, 0xF1, 0xE0, 0x3C, 0xF0, 0x1E,\n  0x78, 0x0F, 0x3C, 0x07, 0x9E, 0x03, 0xCF, 0x01, 0xE7, 0x80, 0xE3, 0xC0,\n  0xF1, 0xE0, 0xF0, 0xF0, 0xE1, 0xFF, 0xC0, 0xFF, 0xFC, 0x78, 0x38, 0xF0,\n  0x31, 0xE0, 0x23, 0xC4, 0x07, 0x88, 0x0F, 0x30, 0x1F, 0xE0, 0x3C, 0xC0,\n  0x78, 0x80, 0xF1, 0x01, 0xE0, 0x23, 0xC0, 0x47, 0x81, 0x8F, 0x07, 0x7F,\n  0xFE, 0xFF, 0xFC, 0xF0, 0x73, 0xC0, 0xCF, 0x01, 0x3C, 0x40, 0xF1, 0x03,\n  0xCC, 0x0F, 0xF0, 0x3C, 0xC0, 0xF1, 0x03, 0xC4, 0x0F, 0x00, 0x3C, 0x00,\n  0xF0, 0x03, 0xC0, 0x3F, 0xC0, 0x07, 0xE2, 0x1C, 0x3E, 0x38, 0x0E, 0x78,\n  0x06, 0x70, 0x06, 0xF0, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0xF0,\n  0x7F, 0xF0, 0x1E, 0x70, 0x1E, 0x78, 0x1E, 0x38, 0x1E, 0x1E, 0x1E, 0x07,\n  0xF0, 0xFE, 0xFF, 0x78, 0x3C, 0x78, 0x3C, 0x78, 0x3C, 0x78, 0x3C, 0x78,\n  0x3C, 0x78, 0x3C, 0x7F, 0xFC, 0x78, 0x3C, 0x78, 0x3C, 0x78, 0x3C, 0x78,\n  0x3C, 0x78, 0x3C, 0x78, 0x3C, 0x78, 0x3C, 0xFE, 0xFF, 0xFF, 0x3C, 0x3C,\n  0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C,\n  0xFF, 0x0F, 0xF0, 0x3C, 0x03, 0xC0, 0x3C, 0x03, 0xC0, 0x3C, 0x03, 0xC0,\n  0x3C, 0x03, 0xC0, 0x3C, 0x03, 0xC0, 0x3C, 0x03, 0xC0, 0x3C, 0xE3, 0xCE,\n  0x38, 0xE3, 0x83, 0xE0, 0xFE, 0x7F, 0x3C, 0x0E, 0x1E, 0x04, 0x0F, 0x04,\n  0x07, 0x84, 0x03, 0xCC, 0x01, 0xEE, 0x00, 0xFF, 0x00, 0x7F, 0xC0, 0x3C,\n  0xF0, 0x1E, 0x7C, 0x0F, 0x1F, 0x07, 0x87, 0xC3, 0xC1, 0xF1, 0xE0, 0x7D,\n  0xFC, 0xFF, 0xFE, 0x01, 0xE0, 0x07, 0x80, 0x1E, 0x00, 0x78, 0x01, 0xE0,\n  0x07, 0x80, 0x1E, 0x00, 0x78, 0x01, 0xE0, 0x07, 0x80, 0x1E, 0x01, 0x78,\n  0x0D, 0xE0, 0x67, 0x83, 0xBF, 0xFE, 0xFC, 0x01, 0xF3, 0xC0, 0x3E, 0x3E,\n  0x03, 0xE2, 0xE0, 0x5E, 0x2F, 0x05, 0xE2, 0xF0, 0x5E, 0x27, 0x09, 0xE2,\n  0x78, 0x9E, 0x23, 0x91, 0xE2, 0x3D, 0x1E, 0x23, 0xF1, 0xE2, 0x1E, 0x1E,\n  0x21, 0xE1, 0xE2, 0x0C, 0x1E, 0x20, 0xC1, 0xEF, 0x88, 0x3F, 0xF8, 0x1E,\n  0xF8, 0x18, 0xF8, 0x11, 0xF8, 0x22, 0xF8, 0x45, 0xF0, 0x89, 0xF1, 0x11,\n  0xF2, 0x21, 0xF4, 0x41, 0xF8, 0x81, 0xF1, 0x01, 0xE2, 0x03, 0xC4, 0x03,\n  0x8C, 0x03, 0x7C, 0x02, 0x07, 0xF0, 0x0F, 0x1E, 0x0E, 0x03, 0x8F, 0x01,\n  0xE7, 0x00, 0x77, 0x80, 0x3F, 0xC0, 0x1F, 0xE0, 0x0F, 0xF0, 0x07, 0xF8,\n  0x03, 0xFC, 0x01, 0xEE, 0x00, 0xE7, 0x80, 0xF1, 0xC0, 0x70, 0x70, 0x70,\n  0x0F, 0xE0, 0xFF, 0x87, 0x9E, 0x78, 0xF7, 0x8F, 0x78, 0xF7, 0x8F, 0x78,\n  0xF7, 0x9E, 0x7F, 0x87, 0x80, 0x78, 0x07, 0x80, 0x78, 0x07, 0x80, 0x78,\n  0x0F, 0xE0, 0x07, 0xF0, 0x0F, 0x1E, 0x0E, 0x07, 0x8F, 0x01, 0xE7, 0x00,\n  0xF7, 0x80, 0x3F, 0xC0, 0x1F, 0xE0, 0x0F, 0xF0, 0x07, 0xF8, 0x03, 0xFC,\n  0x01, 0xEE, 0x00, 0xE7, 0x00, 0xF1, 0xC0, 0x70, 0x70, 0x70, 0x1C, 0xF0,\n  0x03, 0xE0, 0x01, 0xF8, 0x00, 0x3E, 0x00, 0x07, 0xE0, 0xFF, 0xE0, 0x3C,\n  0x78, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x38, 0x3C,\n  0x70, 0x3F, 0xC0, 0x3D, 0xE0, 0x3C, 0xF0, 0x3C, 0xF8, 0x3C, 0x78, 0x3C,\n  0x3C, 0x3C, 0x3E, 0xFF, 0x1F, 0x1F, 0x27, 0x0E, 0x60, 0x6E, 0x06, 0xF0,\n  0x2F, 0x80, 0x7F, 0x07, 0xFC, 0x1F, 0xE0, 0x7E, 0x01, 0xF8, 0x07, 0xC0,\n  0x7C, 0x06, 0xF0, 0xC9, 0xF8, 0xFF, 0xFF, 0xC7, 0x9F, 0x0F, 0x1C, 0x1E,\n  0x10, 0x3C, 0x00, 0x78, 0x00, 0xF0, 0x01, 0xE0, 0x03, 0xC0, 0x07, 0x80,\n  0x0F, 0x00, 0x1E, 0x00, 0x3C, 0x00, 0x78, 0x00, 0xF0, 0x07, 0xF8, 0xFE,\n  0x1E, 0xF0, 0x09, 0xE0, 0x13, 0xC0, 0x27, 0x80, 0x4F, 0x00, 0x9E, 0x01,\n  0x3C, 0x02, 0x78, 0x04, 0xF0, 0x09, 0xE0, 0x13, 0xC0, 0x27, 0x80, 0x47,\n  0x81, 0x07, 0x84, 0x07, 0xF0, 0xFF, 0x0F, 0x9E, 0x03, 0x0F, 0x00, 0x83,\n  0xC0, 0x81, 0xE0, 0x40, 0xF8, 0x60, 0x3C, 0x20, 0x1E, 0x10, 0x07, 0x90,\n  0x03, 0xC8, 0x00, 0xF4, 0x00, 0x7C, 0x00, 0x3E, 0x00, 0x0E, 0x00, 0x07,\n  0x00, 0x01, 0x80, 0x00, 0x80, 0x00, 0xFE, 0x7F, 0x9E, 0xF8, 0x3C, 0x08,\n  0xF0, 0x78, 0x31, 0xE0, 0xF0, 0x41, 0xE0, 0xF0, 0x83, 0xC3, 0xE3, 0x07,\n  0x85, 0xC4, 0x07, 0x93, 0xC8, 0x0F, 0x27, 0xB0, 0x0E, 0x47, 0x40, 0x1F,\n  0x0F, 0x80, 0x3E, 0x1F, 0x00, 0x38, 0x1C, 0x00, 0x70, 0x38, 0x00, 0xE0,\n  0x30, 0x00, 0x80, 0x40, 0xFF, 0x9F, 0x9F, 0x07, 0x07, 0x83, 0x03, 0xE3,\n  0x00, 0xF9, 0x00, 0x3D, 0x00, 0x1F, 0x00, 0x07, 0xC0, 0x01, 0xE0, 0x00,\n  0xF8, 0x00, 0xBE, 0x00, 0x8F, 0x00, 0x83, 0xC0, 0xC1, 0xF0, 0xE0, 0xFD,\n  0xF8, 0xFF, 0xFF, 0x1F, 0x7C, 0x06, 0x3C, 0x04, 0x3E, 0x0C, 0x1E, 0x08,\n  0x0F, 0x10, 0x0F, 0x30, 0x07, 0xA0, 0x07, 0xC0, 0x03, 0xC0, 0x03, 0xC0,\n  0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x0F, 0xF0, 0x7F, 0xFC,\n  0xE0, 0xF1, 0x83, 0xE2, 0x07, 0x84, 0x1E, 0x00, 0x7C, 0x00, 0xF0, 0x03,\n  0xC0, 0x0F, 0x80, 0x1E, 0x00, 0x7C, 0x08, 0xF0, 0x13, 0xC0, 0x6F, 0x81,\n  0x9E, 0x07, 0x7F, 0xFE, 0xFF, 0x39, 0xCE, 0x73, 0x9C, 0xE7, 0x39, 0xCE,\n  0x73, 0x9C, 0xE7, 0x39, 0xF0, 0xC0, 0x60, 0x60, 0x60, 0x30, 0x30, 0x30,\n  0x18, 0x18, 0x18, 0x0C, 0x0C, 0x0C, 0x06, 0x06, 0x06, 0x03, 0xF9, 0xCE,\n  0x73, 0x9C, 0xE7, 0x39, 0xCE, 0x73, 0x9C, 0xE7, 0x39, 0xCF, 0xF0, 0x0C,\n  0x07, 0x81, 0xE0, 0xCC, 0x33, 0x18, 0x66, 0x1B, 0x87, 0xC0, 0xC0, 0xFF,\n  0xF0, 0xC7, 0x1C, 0x30, 0x1F, 0x0E, 0x71, 0xCF, 0x39, 0xE0, 0x3C, 0x1F,\n  0x8E, 0xF3, 0x9E, 0xF3, 0xDE, 0x79, 0xFF, 0x80, 0xF8, 0x07, 0x80, 0x78,\n  0x07, 0x80, 0x78, 0x07, 0xB8, 0x7D, 0xE7, 0x8E, 0x78, 0xF7, 0x8F, 0x78,\n  0xF7, 0x8F, 0x78, 0xF7, 0x8E, 0x79, 0xC4, 0x78, 0x1F, 0x1D, 0xDC, 0xFE,\n  0x7F, 0x07, 0x83, 0xC1, 0xE0, 0x78, 0x3C, 0x47, 0xC0, 0x03, 0xE0, 0x1E,\n  0x01, 0xE0, 0x1E, 0x01, 0xE1, 0xDE, 0x7B, 0xE7, 0x1E, 0xF1, 0xEF, 0x1E,\n  0xF1, 0xEF, 0x1E, 0xF1, 0xE7, 0x1E, 0x7B, 0xE1, 0xDF, 0x1F, 0x0C, 0x67,\n  0x1B, 0xC7, 0xFF, 0xFC, 0x0F, 0x03, 0xC0, 0x78, 0x4E, 0x21, 0xF0, 0x1E,\n  0x3B, 0x7B, 0x78, 0x78, 0xFC, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,\n  0x78, 0x78, 0xFC, 0x3E, 0x0E, 0x7F, 0xCE, 0x79, 0xEF, 0x3C, 0xE7, 0x0F,\n  0xC1, 0x00, 0x60, 0x1C, 0x03, 0xFE, 0x7F, 0xE3, 0xFF, 0x80, 0xF0, 0x33,\n  0xFC, 0xF8, 0x07, 0x80, 0x78, 0x07, 0x80, 0x78, 0x07, 0xB8, 0x7D, 0xE7,\n  0x9E, 0x79, 0xE7, 0x9E, 0x79, 0xE7, 0x9E, 0x79, 0xE7, 0x9E, 0x79, 0xEF,\n  0xFF, 0x31, 0xE7, 0x8C, 0x03, 0xE7, 0x9E, 0x79, 0xE7, 0x9E, 0x79, 0xE7,\n  0xBF, 0x06, 0x0F, 0x0F, 0x06, 0x00, 0x1F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F,\n  0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0xCF, 0xCE, 0x7C, 0xF8, 0x03,\n  0xC0, 0x1E, 0x00, 0xF0, 0x07, 0x80, 0x3C, 0xF9, 0xE1, 0x8F, 0x10, 0x79,\n  0x03, 0xD8, 0x1F, 0xE0, 0xF7, 0x87, 0x9E, 0x3C, 0x71, 0xE3, 0xDF, 0xBF,\n  0xF9, 0xE7, 0x9E, 0x79, 0xE7, 0x9E, 0x79, 0xE7, 0x9E, 0x79, 0xE7, 0xBF,\n  0xFB, 0xCF, 0x0F, 0xBE, 0x79, 0xE7, 0x8F, 0x3C, 0xF1, 0xE7, 0x9E, 0x3C,\n  0xF3, 0xC7, 0x9E, 0x78, 0xF3, 0xCF, 0x1E, 0x79, 0xE3, 0xCF, 0x3C, 0x7B,\n  0xFF, 0xDF, 0x80, 0xFB, 0x87, 0xDE, 0x79, 0xE7, 0x9E, 0x79, 0xE7, 0x9E,\n  0x79, 0xE7, 0x9E, 0x79, 0xE7, 0x9E, 0xFF, 0xF0, 0x1F, 0x07, 0x71, 0xC7,\n  0x78, 0xFF, 0x1F, 0xE3, 0xFC, 0x7F, 0x8F, 0x71, 0xC7, 0x70, 0x7C, 0x00,\n  0xFB, 0x87, 0xDE, 0x78, 0xE7, 0x8F, 0x78, 0xF7, 0x8F, 0x78, 0xF7, 0x8F,\n  0x78, 0xE7, 0x9E, 0x7F, 0x87, 0x80, 0x78, 0x07, 0x80, 0x78, 0x0F, 0xC0,\n  0x1E, 0x23, 0x9E, 0x71, 0xEF, 0x1E, 0xF1, 0xEF, 0x1E, 0xF1, 0xEF, 0x1E,\n  0x71, 0xE7, 0x9E, 0x1F, 0xE0, 0x1E, 0x01, 0xE0, 0x1E, 0x01, 0xE0, 0x3F,\n  0xF9, 0xDF, 0xF7, 0xDD, 0xE0, 0x78, 0x1E, 0x07, 0x81, 0xE0, 0x78, 0x1E,\n  0x0F, 0xC0, 0x3D, 0x43, 0xC3, 0xE0, 0xFC, 0x7E, 0x1F, 0x87, 0x83, 0xC2,\n  0xBC, 0x08, 0x18, 0x38, 0x78, 0xFC, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,\n  0x78, 0x78, 0x79, 0x3E, 0xFB, 0xE7, 0x9E, 0x79, 0xE7, 0x9E, 0x79, 0xE7,\n  0x9E, 0x79, 0xE7, 0x9E, 0x79, 0xE7, 0x9E, 0x3F, 0xF0, 0xFC, 0xEF, 0x08,\n  0xE1, 0x1E, 0x41, 0xC8, 0x3D, 0x03, 0xC0, 0x78, 0x0E, 0x00, 0xC0, 0x10,\n  0x00, 0xFD, 0xF7, 0xBC, 0x71, 0x9E, 0x38, 0x87, 0x1E, 0x43, 0xCF, 0x40,\n  0xEB, 0xA0, 0x7C, 0xF0, 0x1C, 0x70, 0x0E, 0x38, 0x06, 0x08, 0x01, 0x04,\n  0x00, 0xFC, 0xF7, 0x84, 0x3C, 0x81, 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0x80,\n  0xBC, 0x13, 0xC2, 0x1E, 0xFB, 0xF0, 0xFC, 0xEF, 0x08, 0xE1, 0x1E, 0x43,\n  0xC8, 0x3A, 0x07, 0xC0, 0x78, 0x0E, 0x01, 0xC0, 0x18, 0x02, 0x00, 0x41,\n  0xC8, 0x3A, 0x03, 0x80, 0xFF, 0xB1, 0xE8, 0x70, 0x3C, 0x1E, 0x07, 0x83,\n  0xC1, 0xE0, 0x78, 0xBC, 0x2F, 0xF8, 0x07, 0x0E, 0x1C, 0x1C, 0x1C, 0x1C,\n  0x1C, 0x1C, 0x1C, 0x1C, 0xE0, 0x18, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C,\n  0x1C, 0x1E, 0x07, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0, 0xE0, 0x70, 0x38, 0x38,\n  0x38, 0x38, 0x38, 0x38, 0x38, 0x18, 0x07, 0x38, 0x38, 0x38, 0x38, 0x38,\n  0x38, 0x38, 0x38, 0x70, 0xE0, 0x70, 0x1F, 0x8B, 0x3F, 0x01, 0xC0 };\n\nconst GFXglyph FreeSerifBold12pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,   6,    0,    1 },   // 0x20 ' '\n  {     0,   4,  16,   8,    2,  -15 },   // 0x21 '!'\n  {     8,   9,   7,  13,    2,  -15 },   // 0x22 '\"'\n  {    16,  12,  16,  12,    0,  -15 },   // 0x23 '#'\n  {    40,  11,  20,  12,    1,  -17 },   // 0x24 '$'\n  {    68,  18,  16,  24,    3,  -15 },   // 0x25 '%'\n  {   104,  18,  16,  20,    1,  -15 },   // 0x26 '&'\n  {   140,   3,   7,   7,    2,  -15 },   // 0x27 '''\n  {   143,   6,  21,   8,    1,  -16 },   // 0x28 '('\n  {   159,   6,  21,   8,    1,  -16 },   // 0x29 ')'\n  {   175,   9,  10,  12,    2,  -15 },   // 0x2A '*'\n  {   187,  12,  12,  16,    2,  -11 },   // 0x2B '+'\n  {   205,   4,   8,   6,    1,   -3 },   // 0x2C ','\n  {   209,   6,   3,   8,    1,   -6 },   // 0x2D '-'\n  {   212,   4,   4,   6,    1,   -3 },   // 0x2E '.'\n  {   214,   8,  17,   7,   -1,  -15 },   // 0x2F '/'\n  {   231,  11,  16,  12,    1,  -15 },   // 0x30 '0'\n  {   253,   9,  16,  12,    1,  -15 },   // 0x31 '1'\n  {   271,  12,  16,  12,    0,  -15 },   // 0x32 '2'\n  {   295,  11,  16,  12,    1,  -15 },   // 0x33 '3'\n  {   317,  10,  16,  12,    1,  -15 },   // 0x34 '4'\n  {   337,  11,  16,  12,    1,  -15 },   // 0x35 '5'\n  {   359,  11,  16,  12,    1,  -15 },   // 0x36 '6'\n  {   381,  11,  16,  12,    0,  -15 },   // 0x37 '7'\n  {   403,  11,  16,  12,    1,  -15 },   // 0x38 '8'\n  {   425,  11,  16,  12,    1,  -15 },   // 0x39 '9'\n  {   447,   4,  11,   8,    2,  -10 },   // 0x3A ':'\n  {   453,   4,  15,   8,    2,  -10 },   // 0x3B ';'\n  {   461,  14,  14,  16,    1,  -12 },   // 0x3C '<'\n  {   486,  14,   8,  16,    1,   -9 },   // 0x3D '='\n  {   500,  14,  14,  16,    1,  -12 },   // 0x3E '>'\n  {   525,  10,  16,  12,    1,  -15 },   // 0x3F '?'\n  {   545,  16,  16,  22,    3,  -15 },   // 0x40 '@'\n  {   577,  17,  16,  17,    0,  -15 },   // 0x41 'A'\n  {   611,  14,  16,  16,    1,  -15 },   // 0x42 'B'\n  {   639,  15,  16,  17,    1,  -15 },   // 0x43 'C'\n  {   669,  17,  16,  18,    0,  -15 },   // 0x44 'D'\n  {   703,  15,  16,  16,    1,  -15 },   // 0x45 'E'\n  {   733,  14,  16,  15,    1,  -15 },   // 0x46 'F'\n  {   761,  16,  16,  19,    1,  -15 },   // 0x47 'G'\n  {   793,  16,  16,  19,    2,  -15 },   // 0x48 'H'\n  {   825,   8,  16,   9,    1,  -15 },   // 0x49 'I'\n  {   841,  12,  18,  12,    0,  -15 },   // 0x4A 'J'\n  {   868,  17,  16,  19,    2,  -15 },   // 0x4B 'K'\n  {   902,  14,  16,  16,    2,  -15 },   // 0x4C 'L'\n  {   930,  20,  16,  23,    1,  -15 },   // 0x4D 'M'\n  {   970,  15,  16,  17,    1,  -15 },   // 0x4E 'N'\n  {  1000,  17,  16,  19,    1,  -15 },   // 0x4F 'O'\n  {  1034,  12,  16,  15,    2,  -15 },   // 0x50 'P'\n  {  1058,  17,  20,  19,    1,  -15 },   // 0x51 'Q'\n  {  1101,  16,  16,  17,    1,  -15 },   // 0x52 'R'\n  {  1133,  12,  16,  14,    1,  -15 },   // 0x53 'S'\n  {  1157,  15,  16,  15,    0,  -15 },   // 0x54 'T'\n  {  1187,  15,  16,  17,    1,  -15 },   // 0x55 'U'\n  {  1217,  17,  17,  17,    0,  -15 },   // 0x56 'V'\n  {  1254,  23,  16,  24,    0,  -15 },   // 0x57 'W'\n  {  1300,  17,  16,  17,    0,  -15 },   // 0x58 'X'\n  {  1334,  16,  16,  17,    1,  -15 },   // 0x59 'Y'\n  {  1366,  15,  16,  16,    0,  -15 },   // 0x5A 'Z'\n  {  1396,   5,  20,   8,    2,  -15 },   // 0x5B '['\n  {  1409,   8,  17,   7,   -1,  -15 },   // 0x5C '\\'\n  {  1426,   5,  20,   8,    2,  -15 },   // 0x5D ']'\n  {  1439,  10,   9,  14,    2,  -15 },   // 0x5E '^'\n  {  1451,  12,   1,  12,    0,    4 },   // 0x5F '_'\n  {  1453,   5,   4,   8,    0,  -16 },   // 0x60 '`'\n  {  1456,  11,  11,  12,    1,  -10 },   // 0x61 'a'\n  {  1472,  12,  16,  13,    1,  -15 },   // 0x62 'b'\n  {  1496,   9,  11,  10,    1,  -10 },   // 0x63 'c'\n  {  1509,  12,  16,  13,    1,  -15 },   // 0x64 'd'\n  {  1533,  10,  11,  11,    1,  -10 },   // 0x65 'e'\n  {  1547,   8,  16,   9,    1,  -15 },   // 0x66 'f'\n  {  1563,  11,  16,  12,    1,  -10 },   // 0x67 'g'\n  {  1585,  12,  16,  13,    1,  -15 },   // 0x68 'h'\n  {  1609,   6,  16,   7,    1,  -15 },   // 0x69 'i'\n  {  1621,   8,  21,  10,    0,  -15 },   // 0x6A 'j'\n  {  1642,  13,  16,  13,    1,  -15 },   // 0x6B 'k'\n  {  1668,   6,  16,   7,    1,  -15 },   // 0x6C 'l'\n  {  1680,  19,  11,  20,    1,  -10 },   // 0x6D 'm'\n  {  1707,  12,  11,  13,    1,  -10 },   // 0x6E 'n'\n  {  1724,  11,  11,  12,    1,  -10 },   // 0x6F 'o'\n  {  1740,  12,  16,  13,    1,  -10 },   // 0x70 'p'\n  {  1764,  12,  16,  13,    1,  -10 },   // 0x71 'q'\n  {  1788,  10,  11,  10,    1,  -10 },   // 0x72 'r'\n  {  1802,   8,  11,  10,    1,  -10 },   // 0x73 's'\n  {  1813,   8,  15,   8,    1,  -14 },   // 0x74 't'\n  {  1828,  12,  11,  14,    1,  -10 },   // 0x75 'u'\n  {  1845,  11,  11,  12,    0,  -10 },   // 0x76 'v'\n  {  1861,  17,  11,  17,    0,  -10 },   // 0x77 'w'\n  {  1885,  12,  11,  12,    0,  -10 },   // 0x78 'x'\n  {  1902,  11,  16,  12,    0,  -10 },   // 0x79 'y'\n  {  1924,  10,  11,  11,    1,  -10 },   // 0x7A 'z'\n  {  1938,   8,  21,   9,    0,  -16 },   // 0x7B '{'\n  {  1959,   2,  17,   5,    2,  -15 },   // 0x7C '|'\n  {  1964,   8,  21,   9,    2,  -16 },   // 0x7D '}'\n  {  1985,  11,   4,  12,    1,   -7 } }; // 0x7E '~'\n\nconst GFXfont FreeSerifBold12pt7b PROGMEM = {\n  (uint8_t  *)FreeSerifBold12pt7bBitmaps,\n  (GFXglyph *)FreeSerifBold12pt7bGlyphs,\n  0x20, 0x7E, 29 };\n\n// Approx. 2663 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeSerifBold18pt7b.h",
    "content": "const uint8_t FreeSerifBold18pt7bBitmaps[] PROGMEM = {\n  0x7B, 0xEF, 0xFF, 0xFF, 0xF7, 0x9E, 0x71, 0xC7, 0x0C, 0x20, 0x82, 0x00,\n  0x00, 0x07, 0x3E, 0xFF, 0xFF, 0xDC, 0x60, 0x37, 0x83, 0xFC, 0x1F, 0xE0,\n  0xFF, 0x07, 0xB8, 0x3D, 0xC0, 0xCC, 0x06, 0x20, 0x31, 0x01, 0x80, 0x03,\n  0x8E, 0x00, 0xC3, 0x80, 0x30, 0xE0, 0x1C, 0x38, 0x07, 0x0E, 0x01, 0xC3,\n  0x87, 0xFF, 0xFD, 0xFF, 0xFF, 0x7F, 0xFF, 0xC1, 0x87, 0x00, 0xE1, 0xC0,\n  0x38, 0x70, 0x0E, 0x1C, 0x03, 0x86, 0x0F, 0xFF, 0xF3, 0xFF, 0xFC, 0xFF,\n  0xFF, 0x07, 0x0E, 0x01, 0xC3, 0x80, 0x70, 0xE0, 0x1C, 0x30, 0x07, 0x0C,\n  0x01, 0x87, 0x00, 0x61, 0xC0, 0x02, 0x00, 0x04, 0x00, 0x08, 0x00, 0xFF,\n  0x03, 0x27, 0x8C, 0x47, 0x38, 0x86, 0x71, 0x0C, 0xF2, 0x09, 0xF4, 0x03,\n  0xF8, 0x03, 0xF8, 0x07, 0xFC, 0x03, 0xFC, 0x03, 0xFE, 0x01, 0xFE, 0x03,\n  0xFC, 0x04, 0xFC, 0x08, 0xFA, 0x10, 0xF4, 0x21, 0xEC, 0x43, 0xD8, 0x8F,\n  0x3D, 0x3C, 0x3F, 0xF0, 0x1F, 0x00, 0x08, 0x00, 0x10, 0x00, 0x03, 0xC0,\n  0x18, 0x01, 0xFE, 0x0F, 0x00, 0x7C, 0xFF, 0xC0, 0x1F, 0x0F, 0x90, 0x07,\n  0xC1, 0x06, 0x00, 0xF0, 0x21, 0x80, 0x3E, 0x04, 0x30, 0x07, 0x81, 0x8C,\n  0x00, 0xF0, 0x21, 0x80, 0x1E, 0x0C, 0x60, 0x03, 0xC1, 0x18, 0x1E, 0x3C,\n  0xE3, 0x0F, 0xE7, 0xF8, 0xC3, 0xE6, 0x3C, 0x18, 0xF8, 0x40, 0x06, 0x3E,\n  0x08, 0x01, 0x87, 0x81, 0x00, 0x31, 0xF0, 0x20, 0x0C, 0x3E, 0x04, 0x01,\n  0x87, 0x81, 0x00, 0x60, 0xF0, 0x60, 0x18, 0x1E, 0x08, 0x03, 0x03, 0xC7,\n  0x00, 0xC0, 0x3F, 0xC0, 0x18, 0x03, 0xE0, 0x00, 0x7E, 0x00, 0x00, 0x7F,\n  0xE0, 0x00, 0x38, 0xF8, 0x00, 0x1E, 0x1F, 0x00, 0x07, 0x83, 0xC0, 0x01,\n  0xF0, 0xF0, 0x00, 0x7C, 0x38, 0x00, 0x1F, 0x9C, 0x00, 0x03, 0xFC, 0x00,\n  0x00, 0xFE, 0x0F, 0xF0, 0x3F, 0x80, 0xF0, 0x1F, 0xF0, 0x18, 0x1C, 0xFE,\n  0x0C, 0x0E, 0x1F, 0xC3, 0x07, 0x87, 0xF1, 0x81, 0xE0, 0xFE, 0x40, 0xF8,\n  0x1F, 0xF0, 0x3F, 0x07, 0xF8, 0x0F, 0xC0, 0xFE, 0x03, 0xF8, 0x1F, 0xC0,\n  0xFE, 0x07, 0xF8, 0x9F, 0xE3, 0xFF, 0xE7, 0xFF, 0x9F, 0xF0, 0xFF, 0xC3,\n  0xF8, 0x0F, 0x80, 0x3C, 0x00, 0x6F, 0xFF, 0xFF, 0x66, 0x66, 0x00, 0x81,\n  0x81, 0x81, 0x81, 0x80, 0xC0, 0xE0, 0x70, 0x70, 0x38, 0x3C, 0x1E, 0x0F,\n  0x07, 0x83, 0xC1, 0xE0, 0xF0, 0x78, 0x3C, 0x0E, 0x07, 0x03, 0x80, 0xE0,\n  0x70, 0x18, 0x06, 0x01, 0x00, 0x40, 0x10, 0x04, 0x80, 0x30, 0x0C, 0x03,\n  0x00, 0xC0, 0x60, 0x38, 0x1C, 0x07, 0x03, 0x81, 0xC0, 0xF0, 0x78, 0x3C,\n  0x1E, 0x0F, 0x07, 0x83, 0xC1, 0xE0, 0xE0, 0x70, 0x38, 0x38, 0x1C, 0x0C,\n  0x0C, 0x06, 0x04, 0x04, 0x04, 0x00, 0x03, 0x00, 0x1E, 0x00, 0x78, 0x1D,\n  0xE6, 0xFB, 0x3D, 0xED, 0xF3, 0xFF, 0x01, 0xC0, 0x7F, 0xF3, 0xED, 0xFF,\n  0x33, 0xD9, 0xE6, 0x07, 0x80, 0x1E, 0x00, 0x30, 0x00, 0x00, 0xE0, 0x00,\n  0x1C, 0x00, 0x03, 0x80, 0x00, 0x70, 0x00, 0x0E, 0x00, 0x01, 0xC0, 0x00,\n  0x38, 0x00, 0x07, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x80,\n  0x70, 0x00, 0x0E, 0x00, 0x01, 0xC0, 0x00, 0x38, 0x00, 0x07, 0x00, 0x00,\n  0xE0, 0x00, 0x1C, 0x00, 0x03, 0x80, 0x00, 0x73, 0xEF, 0xFF, 0xFD, 0xF0,\n  0xC2, 0x18, 0xC6, 0x30, 0xFF, 0xFF, 0xFF, 0xFF, 0x7B, 0xFF, 0xFF, 0xFD,\n  0xE0, 0x00, 0xE0, 0x3C, 0x07, 0x00, 0xE0, 0x1C, 0x07, 0x00, 0xE0, 0x1C,\n  0x07, 0x00, 0xE0, 0x1C, 0x07, 0x00, 0xE0, 0x1C, 0x07, 0x00, 0xE0, 0x1C,\n  0x07, 0x00, 0xE0, 0x1C, 0x07, 0x00, 0xE0, 0x1C, 0x07, 0x00, 0xE0, 0x00,\n  0x03, 0xC0, 0x0E, 0x70, 0x1E, 0x78, 0x3C, 0x3C, 0x3C, 0x3C, 0x7C, 0x3E,\n  0x7C, 0x3E, 0x7C, 0x3E, 0xFC, 0x3F, 0xFC, 0x3F, 0xFC, 0x3F, 0xFC, 0x3F,\n  0xFC, 0x3F, 0xFC, 0x3F, 0xFC, 0x3F, 0xFC, 0x3F, 0xFC, 0x3E, 0x7C, 0x3E,\n  0x7C, 0x3E, 0x3C, 0x3C, 0x3C, 0x3C, 0x1E, 0x78, 0x0E, 0x70, 0x03, 0xC0,\n  0x00, 0xC0, 0x3C, 0x0F, 0xC3, 0xFC, 0x4F, 0xC0, 0xFC, 0x0F, 0xC0, 0xFC,\n  0x0F, 0xC0, 0xFC, 0x0F, 0xC0, 0xFC, 0x0F, 0xC0, 0xFC, 0x0F, 0xC0, 0xFC,\n  0x0F, 0xC0, 0xFC, 0x0F, 0xC0, 0xFC, 0x0F, 0xC0, 0xFC, 0x1F, 0xEF, 0xFF,\n  0x03, 0xE0, 0x0F, 0xF8, 0x1F, 0xFC, 0x3F, 0xFC, 0x30, 0xFE, 0x60, 0x7E,\n  0x40, 0x3E, 0x00, 0x3E, 0x00, 0x3E, 0x00, 0x3C, 0x00, 0x3C, 0x00, 0x78,\n  0x00, 0x70, 0x00, 0xE0, 0x00, 0xC0, 0x01, 0x80, 0x03, 0x00, 0x06, 0x01,\n  0x0C, 0x03, 0x1F, 0xFF, 0x1F, 0xFF, 0x3F, 0xFE, 0x7F, 0xFE, 0xFF, 0xFE,\n  0x03, 0xF0, 0x0F, 0xF8, 0x3F, 0xFC, 0x21, 0xFE, 0x40, 0xFE, 0x00, 0x7E,\n  0x00, 0x7E, 0x00, 0x7C, 0x00, 0x78, 0x00, 0xF0, 0x01, 0xFC, 0x03, 0xFE,\n  0x00, 0x7E, 0x00, 0x3F, 0x00, 0x1F, 0x00, 0x0F, 0x00, 0x0F, 0x00, 0x0F,\n  0x00, 0x0E, 0x70, 0x0E, 0xFC, 0x1C, 0xFE, 0x38, 0x7F, 0xE0, 0x3F, 0x80,\n  0x00, 0x38, 0x00, 0xF0, 0x03, 0xE0, 0x07, 0xC0, 0x1F, 0x80, 0x5F, 0x00,\n  0xBE, 0x02, 0x7C, 0x08, 0xF8, 0x31, 0xF0, 0x43, 0xE1, 0x07, 0xC4, 0x0F,\n  0x88, 0x1F, 0x20, 0x3E, 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF8,\n  0x07, 0xC0, 0x0F, 0x80, 0x1F, 0x00, 0x3E, 0x00, 0x7C, 0x0F, 0xFE, 0x1F,\n  0xF8, 0x7F, 0xF0, 0xFF, 0xE1, 0x80, 0x03, 0x00, 0x0C, 0x00, 0x18, 0x00,\n  0x3F, 0x80, 0xFF, 0xC1, 0xFF, 0xC3, 0xFF, 0xC3, 0xFF, 0x80, 0x3F, 0x80,\n  0x0F, 0x00, 0x0E, 0x00, 0x1C, 0x00, 0x18, 0x00, 0x37, 0x80, 0x4F, 0x81,\n  0x9F, 0xC6, 0x3F, 0xF8, 0x1F, 0x80, 0x00, 0x07, 0x00, 0x7C, 0x01, 0xF0,\n  0x03, 0xC0, 0x0F, 0x80, 0x1F, 0x00, 0x1F, 0x00, 0x3E, 0x00, 0x7E, 0x00,\n  0x7F, 0xF0, 0x7F, 0xFC, 0xFC, 0x7E, 0xFC, 0x7E, 0xFC, 0x3F, 0xFC, 0x3F,\n  0xFC, 0x3F, 0xFC, 0x3F, 0xFC, 0x3F, 0x7C, 0x3F, 0x7C, 0x3E, 0x3C, 0x3E,\n  0x3E, 0x3C, 0x1E, 0x78, 0x07, 0xE0, 0x7F, 0xFF, 0x7F, 0xFE, 0x7F, 0xFE,\n  0xFF, 0xFE, 0xFF, 0xFC, 0xC0, 0x1C, 0x80, 0x18, 0x80, 0x38, 0x00, 0x38,\n  0x00, 0x70, 0x00, 0x70, 0x00, 0x70, 0x00, 0xE0, 0x00, 0xE0, 0x00, 0xE0,\n  0x01, 0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x03, 0x80, 0x03, 0x80, 0x07, 0x80,\n  0x07, 0x00, 0x07, 0x00, 0x0F, 0x00, 0x0F, 0xE0, 0x38, 0x78, 0x70, 0x3C,\n  0xF0, 0x1E, 0xF0, 0x1E, 0xF8, 0x1E, 0xF8, 0x1E, 0xFE, 0x3C, 0x7F, 0xB0,\n  0x7F, 0xE0, 0x3F, 0xF0, 0x0F, 0xF8, 0x1F, 0xFC, 0x39, 0xFE, 0x70, 0xFF,\n  0xF0, 0x3F, 0xF0, 0x3F, 0xF0, 0x1F, 0xF0, 0x1F, 0xF0, 0x1E, 0x78, 0x3E,\n  0x7C, 0x7C, 0x3F, 0xF8, 0x0F, 0xE0, 0x07, 0xE0, 0x1E, 0x78, 0x3C, 0x7C,\n  0x7C, 0x3C, 0x7C, 0x3E, 0xFC, 0x3E, 0xFC, 0x3F, 0xFC, 0x3F, 0xFC, 0x3F,\n  0xFC, 0x3F, 0xFC, 0x3F, 0x7E, 0x3F, 0x7E, 0x3F, 0x3F, 0xFE, 0x0F, 0xFE,\n  0x00, 0x7E, 0x00, 0x7C, 0x00, 0xF8, 0x00, 0xF8, 0x01, 0xF0, 0x03, 0xC0,\n  0x0F, 0x80, 0x3E, 0x00, 0xE0, 0x00, 0x7B, 0xFF, 0xFF, 0xFD, 0xE0, 0x00,\n  0x00, 0x07, 0xBF, 0xFF, 0xFF, 0xDE, 0x39, 0xFB, 0xF7, 0xEF, 0xC7, 0x00,\n  0x00, 0x00, 0x01, 0xE7, 0xEF, 0xFF, 0xFF, 0xBF, 0x06, 0x08, 0x30, 0xC2,\n  0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x0F, 0x80, 0x07, 0xF0,\n  0x03, 0xFC, 0x01, 0xFE, 0x00, 0xFE, 0x00, 0x7F, 0x00, 0x3F, 0x80, 0x1F,\n  0xC0, 0x03, 0xF8, 0x00, 0x1F, 0xC0, 0x00, 0xFE, 0x00, 0x07, 0xF0, 0x00,\n  0x3F, 0x80, 0x01, 0xFE, 0x00, 0x0F, 0xE0, 0x00, 0x7C, 0x00, 0x01, 0x80,\n  0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x80, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0x00, 0x00, 0x18, 0x00, 0x03,\n  0xE0, 0x00, 0x7F, 0x00, 0x07, 0xF8, 0x00, 0x1F, 0xC0, 0x00, 0xFE, 0x00,\n  0x07, 0xF0, 0x00, 0x3F, 0x80, 0x01, 0xFC, 0x00, 0x3F, 0x80, 0x1F, 0xC0,\n  0x0F, 0xE0, 0x07, 0xF0, 0x07, 0xF8, 0x03, 0xFC, 0x00, 0xFE, 0x00, 0x1F,\n  0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0xC0, 0xFF, 0xC7, 0x1F,\n  0xB8, 0x3E, 0xF0, 0xFF, 0xC3, 0xFF, 0x0F, 0xD8, 0x3F, 0x00, 0xF8, 0x07,\n  0xC0, 0x1E, 0x00, 0x60, 0x03, 0x00, 0x08, 0x00, 0x20, 0x00, 0x80, 0x00,\n  0x00, 0x00, 0x00, 0x70, 0x03, 0xE0, 0x1F, 0x80, 0x7E, 0x01, 0xF8, 0x01,\n  0xC0, 0x00, 0x7F, 0x00, 0x01, 0xFF, 0xE0, 0x07, 0xC0, 0xF0, 0x0F, 0x00,\n  0x38, 0x1E, 0x00, 0x0C, 0x3C, 0x07, 0x06, 0x38, 0x1F, 0x72, 0x78, 0x3C,\n  0xF3, 0x78, 0x78, 0xE1, 0xF0, 0x70, 0xE1, 0xF0, 0xF0, 0xE1, 0xF0, 0xE0,\n  0xC1, 0xF1, 0xE1, 0xC1, 0xF1, 0xC1, 0xC1, 0xF1, 0xC3, 0x82, 0xF1, 0xC3,\n  0x86, 0x71, 0xC7, 0x8C, 0x79, 0xFB, 0xF8, 0x78, 0xF1, 0xF0, 0x3C, 0x00,\n  0x00, 0x1E, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x07, 0xC0, 0x78, 0x03, 0xFF,\n  0xE0, 0x00, 0x7F, 0x80, 0x00, 0x10, 0x00, 0x00, 0x38, 0x00, 0x00, 0x38,\n  0x00, 0x00, 0x78, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x7C, 0x00, 0x00, 0xFE,\n  0x00, 0x00, 0xFE, 0x00, 0x01, 0xBF, 0x00, 0x01, 0xBF, 0x00, 0x01, 0x1F,\n  0x00, 0x03, 0x1F, 0x80, 0x02, 0x1F, 0x80, 0x06, 0x0F, 0xC0, 0x06, 0x0F,\n  0xC0, 0x04, 0x07, 0xE0, 0x0F, 0xFF, 0xE0, 0x0F, 0xFF, 0xE0, 0x18, 0x03,\n  0xF0, 0x18, 0x03, 0xF0, 0x30, 0x01, 0xF8, 0x30, 0x01, 0xF8, 0x70, 0x01,\n  0xFC, 0xFE, 0x0F, 0xFF, 0xFF, 0xFE, 0x07, 0xFF, 0xFE, 0x0F, 0xE1, 0xF8,\n  0x3F, 0x07, 0xC1, 0xF8, 0x3F, 0x0F, 0xC1, 0xF8, 0x7E, 0x0F, 0xC3, 0xF0,\n  0x7E, 0x1F, 0x87, 0xE0, 0xFC, 0x7C, 0x07, 0xFF, 0x00, 0x3F, 0xFF, 0x01,\n  0xF8, 0xFE, 0x0F, 0xC1, 0xF8, 0x7E, 0x0F, 0xC3, 0xF0, 0x3F, 0x1F, 0x81,\n  0xF8, 0xFC, 0x0F, 0xC7, 0xE0, 0x7E, 0x3F, 0x03, 0xF1, 0xF8, 0x3F, 0x0F,\n  0xC3, 0xF0, 0xFF, 0xFF, 0x1F, 0xFF, 0xC0, 0x00, 0x7E, 0x04, 0x07, 0xFF,\n  0x18, 0x1F, 0x07, 0xF0, 0x7C, 0x03, 0xE1, 0xF0, 0x03, 0xC7, 0xC0, 0x03,\n  0x9F, 0x80, 0x03, 0x3F, 0x00, 0x06, 0x7C, 0x00, 0x05, 0xF8, 0x00, 0x03,\n  0xF0, 0x00, 0x07, 0xE0, 0x00, 0x0F, 0xC0, 0x00, 0x1F, 0x80, 0x00, 0x3F,\n  0x00, 0x00, 0x7E, 0x00, 0x00, 0xFC, 0x00, 0x00, 0xFC, 0x00, 0x01, 0xF8,\n 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0x7E, 0x00, 0x77, 0xF0, 0x07, 0x3F, 0x00, 0xFB,\n  0xFF, 0xFF, 0xDF, 0xFF, 0xFE, 0xFF, 0xFF, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0,\n  0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0,\n  0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xFF, 0xFF, 0xE0, 0x1E,\n  0x01, 0xC0, 0x38, 0x07, 0x80, 0x70, 0x0E, 0x01, 0xC0, 0x1C, 0x03, 0x80,\n  0x70, 0x07, 0x00, 0xE0, 0x1C, 0x01, 0xC0, 0x38, 0x07, 0x00, 0x70, 0x0E,\n  0x01, 0xC0, 0x1C, 0x03, 0x80, 0x70, 0x0F, 0x00, 0xE0, 0xFF, 0xFF, 0x0F,\n  0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F,\n  0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F,\n  0xFF, 0xFF, 0x03, 0x80, 0x0F, 0x00, 0x1F, 0x00, 0x7E, 0x00, 0xEE, 0x03,\n  0x9C, 0x07, 0x1C, 0x1C, 0x38, 0x38, 0x38, 0xE0, 0x71, 0xC0, 0x77, 0x00,\n  0xEE, 0x00, 0xE0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xE0, 0xF0,\n  0x78, 0x3C, 0x0E, 0x07, 0x0F, 0xE0, 0x3F, 0xF0, 0x78, 0xF8, 0x78, 0x7C,\n  0x78, 0x7C, 0x38, 0x7C, 0x00, 0x7C, 0x03, 0xFC, 0x1E, 0x7C, 0x7C, 0x7C,\n  0xFC, 0x7C, 0xFC, 0x7C, 0xFC, 0xFC, 0xFF, 0xFD, 0x7F, 0x7F, 0x3C, 0x3C,\n  0xFC, 0x00, 0x1F, 0x00, 0x07, 0xC0, 0x01, 0xF0, 0x00, 0x7C, 0x00, 0x1F,\n  0x00, 0x07, 0xC0, 0x01, 0xF0, 0x00, 0x7C, 0xF8, 0x1F, 0x7F, 0x87, 0xE3,\n  0xF1, 0xF0, 0x7E, 0x7C, 0x0F, 0x9F, 0x03, 0xF7, 0xC0, 0xFD, 0xF0, 0x3F,\n  0x7C, 0x0F, 0xDF, 0x03, 0xF7, 0xC0, 0xFD, 0xF0, 0x3E, 0x7C, 0x1F, 0x1F,\n  0x8F, 0xC6, 0x7F, 0xC1, 0x07, 0xC0, 0x07, 0xC0, 0x7F, 0xC3, 0xC7, 0x9F,\n  0x1E, 0x78, 0x7B, 0xE1, 0xCF, 0x80, 0x3E, 0x00, 0xF8, 0x03, 0xE0, 0x0F,\n  0x80, 0x3F, 0x00, 0x7C, 0x00, 0xFC, 0x61, 0xFF, 0x03, 0xF0, 0x00, 0x7F,\n  0x00, 0x07, 0xC0, 0x01, 0xF0, 0x00, 0x7C, 0x00, 0x1F, 0x00, 0x07, 0xC0,\n  0x01, 0xF0, 0x00, 0x7C, 0x07, 0x9F, 0x07, 0xF7, 0xC3, 0xE3, 0xF1, 0xF8,\n  0x7C, 0x7C, 0x1F, 0x3F, 0x07, 0xCF, 0xC1, 0xF3, 0xF0, 0x7C, 0xFC, 0x1F,\n  0x3F, 0x07, 0xCF, 0xC1, 0xF1, 0xF0, 0x7C, 0x7E, 0x1F, 0x0F, 0x8F, 0xC1,\n  0xFD, 0xFC, 0x3E, 0x70, 0x0F, 0xC0, 0x7F, 0xC3, 0xC7, 0x1E, 0x1E, 0xF8,\n  0x7B, 0xFF, 0xFF, 0xFF, 0xFE, 0x00, 0xF8, 0x03, 0xE0, 0x0F, 0xC0, 0x1F,\n  0x03, 0x7E, 0x18, 0xFF, 0xC1, 0xFE, 0x03, 0xF0, 0x0F, 0x83, 0xF8, 0xF3,\n  0xBE, 0xF7, 0xDC, 0xF8, 0x1F, 0x03, 0xE0, 0xFF, 0x1F, 0xE1, 0xF0, 0x3E,\n  0x07, 0xC0, 0xF8, 0x1F, 0x03, 0xE0, 0x7C, 0x0F, 0x81, 0xF0, 0x3E, 0x07,\n  0xC0, 0xF8, 0x1F, 0x07, 0xF8, 0x0F, 0xC0, 0x1F, 0xFF, 0xDF, 0x1F, 0xFF,\n  0x07, 0x8F, 0x83, 0xE7, 0xC1, 0xF3, 0xE0, 0xF9, 0xF0, 0x7C, 0x78, 0x3C,\n  0x1E, 0x3E, 0x03, 0xFC, 0x03, 0x00, 0x07, 0x00, 0x07, 0x80, 0x03, 0xFF,\n  0xF1, 0xFF, 0xFE, 0x7F, 0xFF, 0x8F, 0xFF, 0xF8, 0x01, 0xFC, 0x00, 0x7F,\n  0x00, 0x73, 0xFF, 0xF0, 0x7F, 0xC0, 0xFC, 0x00, 0x3E, 0x00, 0x1F, 0x00,\n  0x0F, 0x80, 0x07, 0xC0, 0x03, 0xE0, 0x01, 0xF0, 0x00, 0xF8, 0x00, 0x7C,\n  0x7C, 0x3E, 0xFF, 0x1F, 0xCF, 0xCF, 0x83, 0xE7, 0xC1, 0xF3, 0xE0, 0xF9,\n  0xF0, 0x7C, 0xF8, 0x3E, 0x7C, 0x1F, 0x3E, 0x0F, 0x9F, 0x07, 0xCF, 0x83,\n  0xE7, 0xC1, 0xF3, 0xE0, 0xF9, 0xF0, 0x7D, 0xFC, 0x7F, 0x39, 0xFB, 0xF7,\n  0xE7, 0x80, 0x00, 0x00, 0xFC, 0xF9, 0xF3, 0xE7, 0xCF, 0x9F, 0x3E, 0x7C,\n  0xF9, 0xF3, 0xE7, 0xCF, 0x9F, 0x7F, 0x03, 0xC0, 0xFC, 0x1F, 0x83, 0xF0,\n  0x3C, 0x00, 0x00, 0x00, 0x00, 0x0F, 0xE0, 0x7C, 0x0F, 0x81, 0xF0, 0x3E,\n  0x07, 0xC0, 0xF8, 0x1F, 0x03, 0xE0, 0x7C, 0x0F, 0x81, 0xF0, 0x3E, 0x07,\n  0xC0, 0xF8, 0x1F, 0x03, 0xE0, 0x7D, 0xCF, 0xF9, 0xEE, 0x7C, 0xFF, 0x0F,\n  0x80, 0xFC, 0x00, 0x1F, 0x00, 0x07, 0xC0, 0x01, 0xF0, 0x00, 0x7C, 0x00,\n  0x1F, 0x00, 0x07, 0xC0, 0x01, 0xF0, 0x00, 0x7C, 0x7F, 0x9F, 0x07, 0x87,\n  0xC1, 0x81, 0xF0, 0xC0, 0x7C, 0x60, 0x1F, 0x30, 0x07, 0xDE, 0x01, 0xFF,\n  0xC0, 0x7F, 0xF0, 0x1F, 0x3E, 0x07, 0xCF, 0xC1, 0xF1, 0xF8, 0x7C, 0x3E,\n  0x1F, 0x07, 0xC7, 0xC1, 0xFB, 0xF9, 0xFF, 0xFC, 0xF9, 0xF3, 0xE7, 0xCF,\n  0x9F, 0x3E, 0x7C, 0xF9, 0xF3, 0xE7, 0xCF, 0x9F, 0x3E, 0x7C, 0xF9, 0xF3,\n  0xE7, 0xCF, 0x9F, 0x7F, 0xFC, 0x7C, 0x1F, 0x0F, 0xBF, 0xCF, 0xF1, 0xF8,\n  0xFF, 0x3F, 0x3E, 0x0F, 0x83, 0xE7, 0xC1, 0xF0, 0x7C, 0xF8, 0x3E, 0x0F,\n  0x9F, 0x07, 0xC1, 0xF3, 0xE0, 0xF8, 0x3E, 0x7C, 0x1F, 0x07, 0xCF, 0x83,\n  0xE0, 0xF9, 0xF0, 0x7C, 0x1F, 0x3E, 0x0F, 0x83, 0xE7, 0xC1, 0xF0, 0x7C,\n  0xF8, 0x3E, 0x0F, 0x9F, 0x07, 0xC1, 0xF7, 0xF1, 0xFC, 0x7F, 0xFC, 0x7C,\n  0x3E, 0xFF, 0x1F, 0xCF, 0xCF, 0x83, 0xE7, 0xC1, 0xF3, 0xE0, 0xF9, 0xF0,\n  0x7C, 0xF8, 0x3E, 0x7C, 0x1F, 0x3E, 0x0F, 0x9F, 0x07, 0xCF, 0x83, 0xE7,\n  0xC1, 0xF3, 0xE0, 0xF9, 0xF0, 0x7D, 0xFC, 0x7F, 0x07, 0xF0, 0x0F, 0xFE,\n  0x0F, 0x8F, 0x8F, 0x87, 0xE7, 0xC1, 0xF7, 0xE0, 0xFF, 0xF0, 0x7F, 0xF8,\n  0x3F, 0xFC, 0x1F, 0xFE, 0x0F, 0xFF, 0x07, 0xEF, 0x83, 0xE7, 0xC1, 0xF1,\n  0xF1, 0xF0, 0x7F, 0xF0, 0x0F, 0xE0, 0xFE, 0x7C, 0x07, 0xDF, 0xE0, 0xFE,\n  0x3E, 0x1F, 0x07, 0xE3, 0xE0, 0x7C, 0x7C, 0x0F, 0xCF, 0x81, 0xF9, 0xF0,\n  0x3F, 0x3E, 0x07, 0xE7, 0xC0, 0xFC, 0xF8, 0x1F, 0x9F, 0x03, 0xE3, 0xE0,\n  0xFC, 0x7E, 0x3F, 0x0F, 0xBF, 0xC1, 0xF3, 0xE0, 0x3E, 0x00, 0x07, 0xC0,\n  0x00, 0xF8, 0x00, 0x1F, 0x00, 0x03, 0xE0, 0x00, 0x7E, 0x00, 0x1F, 0xE0,\n  0x00, 0x07, 0xC1, 0x0F, 0xF9, 0x8F, 0xCD, 0xCF, 0xC3, 0xE7, 0xC1, 0xF7,\n  0xE0, 0xFB, 0xF0, 0x7D, 0xF8, 0x3E, 0xFC, 0x1F, 0x7E, 0x0F, 0xBF, 0x07,\n  0xDF, 0x83, 0xE7, 0xE1, 0xF1, 0xF1, 0xF8, 0x7F, 0x7C, 0x1F, 0x3E, 0x00,\n  0x1F, 0x00, 0x0F, 0x80, 0x07, 0xC0, 0x03, 0xE0, 0x01, 0xF0, 0x01, 0xF8,\n  0x01, 0xFE, 0xFC, 0x73, 0xEF, 0xDF, 0xFE, 0xFC, 0xF7, 0xC3, 0xBE, 0x01,\n  0xF0, 0x0F, 0x80, 0x7C, 0x03, 0xE0, 0x1F, 0x00, 0xF8, 0x07, 0xC0, 0x3E,\n  0x01, 0xF0, 0x1F, 0xE0, 0x1E, 0x23, 0xFE, 0x70, 0xEE, 0x06, 0xE0, 0x2F,\n  0x80, 0xFF, 0x07, 0xFC, 0x3F, 0xE0, 0xFF, 0x81, 0xF8, 0x07, 0xC0, 0x7E,\n  0x0E, 0xBF, 0xC8, 0xF8, 0x04, 0x03, 0x01, 0xC0, 0xF0, 0x7C, 0x3F, 0xEF,\n  0xF9, 0xF0, 0x7C, 0x1F, 0x07, 0xC1, 0xF0, 0x7C, 0x1F, 0x07, 0xC1, 0xF0,\n  0x7C, 0x5F, 0x37, 0xF8, 0xFE, 0x1E, 0x00, 0xFC, 0x7F, 0x1F, 0x07, 0xC7,\n  0xC1, 0xF1, 0xF0, 0x7C, 0x7C, 0x1F, 0x1F, 0x07, 0xC7, 0xC1, 0xF1, 0xF0,\n  0x7C, 0x7C, 0x1F, 0x1F, 0x07, 0xC7, 0xC1, 0xF1, 0xF0, 0x7C, 0x7C, 0x1F,\n  0x1F, 0x8F, 0xC3, 0xFD, 0xFC, 0x7C, 0x60, 0xFF, 0x9F, 0xBF, 0x83, 0x0F,\n  0x81, 0x87, 0xE0, 0x81, 0xF0, 0x40, 0xF8, 0x40, 0x3E, 0x20, 0x1F, 0x30,\n  0x07, 0xD0, 0x03, 0xF8, 0x00, 0xF8, 0x00, 0x7C, 0x00, 0x3C, 0x00, 0x0E,\n  0x00, 0x07, 0x00, 0x01, 0x00, 0xFF, 0x3F, 0xCF, 0x7E, 0x1F, 0x06, 0x3E,\n  0x0F, 0x06, 0x3E, 0x0F, 0x84, 0x1F, 0x0F, 0x8C, 0x1F, 0x1F, 0x88, 0x0F,\n  0x17, 0xC8, 0x0F, 0x97, 0xD8, 0x0F, 0xB3, 0xD0, 0x07, 0xE3, 0xF0, 0x07,\n  0xE3, 0xE0, 0x03, 0xC1, 0xE0, 0x03, 0xC1, 0xE0, 0x03, 0x81, 0xC0, 0x01,\n  0x80, 0xC0, 0x01, 0x80, 0x80, 0xFF, 0x3F, 0x7E, 0x0C, 0x3E, 0x08, 0x3F,\n  0x18, 0x1F, 0x30, 0x0F, 0xE0, 0x0F, 0xC0, 0x07, 0xE0, 0x03, 0xE0, 0x03,\n  0xF0, 0x05, 0xF8, 0x0C, 0xF8, 0x18, 0xFC, 0x30, 0x7E, 0x70, 0x7E, 0xFC,\n  0xFF, 0xFF, 0x3F, 0x7E, 0x0C, 0x7C, 0x0C, 0x3E, 0x08, 0x3E, 0x08, 0x1E,\n  0x18, 0x1F, 0x10, 0x0F, 0x30, 0x0F, 0xA0, 0x0F, 0xA0, 0x07, 0xE0, 0x07,\n  0xC0, 0x03, 0xC0, 0x03, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x00, 0x01,\n  0x00, 0x61, 0x00, 0xF2, 0x00, 0xF6, 0x00, 0xFC, 0x00, 0x78, 0x00, 0x7F,\n  0xFD, 0xFF, 0xF7, 0x0F, 0xD0, 0x3E, 0x01, 0xF0, 0x0F, 0xC0, 0x3E, 0x01,\n  0xF0, 0x0F, 0xC0, 0x3E, 0x01, 0xF8, 0x0F, 0xC1, 0x3E, 0x05, 0xF8, 0x7F,\n  0xFF, 0xFF, 0xFF, 0x01, 0xE0, 0xF8, 0x3E, 0x07, 0x80, 0xF0, 0x1E, 0x03,\n  0xC0, 0x78, 0x0F, 0x01, 0xE0, 0x3C, 0x07, 0x80, 0xF0, 0x1E, 0x07, 0x87,\n  0x80, 0x1E, 0x01, 0xE0, 0x3C, 0x07, 0x80, 0xF0, 0x1E, 0x03, 0xC0, 0x78,\n  0x0F, 0x01, 0xE0, 0x3C, 0x07, 0x80, 0xF8, 0x0F, 0x80, 0x78, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xE0, 0xF0, 0x0F, 0x80, 0xF0,\n  0x0F, 0x01, 0xE0, 0x3C, 0x07, 0x80, 0xF0, 0x1E, 0x03, 0xC0, 0x78, 0x0F,\n  0x01, 0xE0, 0x3C, 0x03, 0xC0, 0x0F, 0x0F, 0x03, 0xC0, 0x78, 0x0F, 0x01,\n  0xE0, 0x3C, 0x07, 0x80, 0xF0, 0x1E, 0x03, 0xC0, 0x78, 0x0F, 0x03, 0xE0,\n  0xF8, 0x3C, 0x00, 0x3E, 0x00, 0x7F, 0xC6, 0xFF, 0xFF, 0x61, 0xFE, 0x00,\n  0x7C };\n\nconst GFXglyph FreeSerifBold18pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,   9,    0,    1 },   // 0x20 ' '\n  {     0,   6,  24,  12,    3,  -23 },   // 0x21 '!'\n  {    18,  13,  10,  19,    3,  -23 },   // 0x22 '\"'\n  {    35,  18,  24,  17,    0,  -23 },   // 0x23 '#'\n  {    89,  15,  28,  17,    1,  -25 },   // 0x24 '$'\n  {   142,  27,  24,  35,    4,  -23 },   // 0x25 '%'\n  {   223,  26,  25,  29,    2,  -23 },   // 0x26 '&'\n  {   305,   4,  10,  10,    3,  -23 },   // 0x27 '''\n  {   310,   9,  30,  12,    2,  -23 },   // 0x28 '('\n  {   344,   9,  30,  12,    1,  -23 },   // 0x29 ')'\n  {   378,  14,  15,  18,    2,  -23 },   // 0x2A '*'\n  {   405,  19,  19,  24,    2,  -17 },   // 0x2B '+'\n  {   451,   6,  12,   9,    1,   -5 },   // 0x2C ','\n  {   460,   8,   4,  12,    2,   -9 },   // 0x2D '-'\n  {   464,   6,   6,   9,    1,   -5 },   // 0x2E '.'\n  {   469,  11,  25,  10,   -1,  -23 },   // 0x2F '/'\n  {   504,  16,  24,  18,    1,  -23 },   // 0x30 '0'\n  {   552,  12,  24,  18,    3,  -23 },   // 0x31 '1'\n  {   588,  16,  24,  17,    1,  -23 },   // 0x32 '2'\n  {   636,  16,  24,  18,    0,  -23 },   // 0x33 '3'\n  {   684,  15,  24,  18,    1,  -23 },   // 0x34 '4'\n  {   729,  15,  24,  18,    1,  -23 },   // 0x35 '5'\n  {   774,  16,  24,  18,    1,  -23 },   // 0x36 '6'\n  {   822,  16,  24,  17,    1,  -23 },   // 0x37 '7'\n  {   870,  16,  24,  17,    1,  -23 },   // 0x38 '8'\n  {   918,  16,  24,  18,    1,  -23 },   // 0x39 '9'\n  {   966,   6,  16,  12,    3,  -15 },   // 0x3A ':'\n  {   978,   7,  22,  12,    2,  -15 },   // 0x3B ';'\n  {   998,  19,  20,  24,    2,  -18 },   // 0x3C '<'\n  {  1046,  19,  12,  24,    2,  -14 },   // 0x3D '='\n  {  1075,  19,  20,  24,    3,  -18 },   // 0x3E '>'\n  {  1123,  14,  24,  18,    2,  -23 },   // 0x3F '?'\n  {  1165,  24,  25,  33,    4,  -23 },   // 0x40 '@'\n  {  1240,  24,  24,  25,    1,  -23 },   // 0x41 'A'\n  {  1312,  21,  24,  23,    1,  -23 },   // 0x42 'B'\n  {  1375,  23,  25,  25,    1,  -23 },   // 0x43 'C'\n  {  1447,  23,  24,  26,    1,  -23 },   // 0x44 'D'\n  {  1516,  21,  24,  23,    2,  -23 },   // 0x45 'E'\n  {  1579,  19,  24,  22,    2,  -23 },   // 0x46 'F'\n  {  1636,  25,  25,  27,    1,  -23 },   // 0x47 'G'\n  {  1715,  24,  24,  27,    2,  -23 },   // 0x48 'H'\n  {  1787,  11,  24,  14,    2,  -23 },   // 0x49 'I'\n  {  1820,  16,  27,  18,    0,  -23 },   // 0x4A 'J'\n  {  1874,  25,  24,  27,    2,  -23 },   // 0x4B 'K'\n  {  1949,  21,  24,  23,    2,  -23 },   // 0x4C 'L'\n  {  2012,  31,  24,  33,    1,  -23 },   // 0x4D 'M'\n  {  2105,  23,  24,  25,    1,  -23 },   // 0x4E 'N'\n  {  2174,  25,  25,  27,    1,  -23 },   // 0x4F 'O'\n  {  2253,  19,  24,  22,    2,  -23 },   // 0x50 'P'\n  {  2310,  25,  30,  27,    1,  -23 },   // 0x51 'Q'\n  {  2404,  23,  24,  25,    2,  -23 },   // 0x52 'R'\n  {  2473,  16,  25,  20,    2,  -23 },   // 0x53 'S'\n  {  2523,  21,  24,  23,    1,  -23 },   // 0x54 'T'\n  {  2586,  22,  25,  25,    2,  -23 },   // 0x55 'U'\n  {  2655,  24,  24,  25,    0,  -23 },   // 0x56 'V'\n  {  2727,  34,  25,  34,    0,  -23 },   // 0x57 'W'\n  {  2834,  24,  24,  25,    1,  -23 },   // 0x58 'X'\n  {  2906,  24,  24,  25,    1,  -23 },   // 0x59 'Y'\n  {  2978,  21,  24,  23,    1,  -23 },   // 0x5A 'Z'\n  {  3041,   8,  29,  12,    2,  -23 },   // 0x5B '['\n  {  3070,  11,  25,  10,   -1,  -23 },   // 0x5C '\\'\n  {  3105,   8,  29,  12,    2,  -23 },   // 0x5D ']'\n  {  3134,  15,  13,  20,    3,  -23 },   // 0x5E '^'\n  {  3159,  18,   3,  17,    0,    3 },   // 0x5F '_'\n  {  3166,   8,   6,  12,    0,  -23 },   // 0x60 '`'\n  {  3172,  16,  16,  18,    1,  -15 },   // 0x61 'a'\n  {  3204,  18,  24,  19,    1,  -23 },   // 0x62 'b'\n  {  3258,  14,  16,  15,    1,  -15 },   // 0x63 'c'\n  {  3286,  18,  24,  19,    1,  -23 },   // 0x64 'd'\n  {  3340,  14,  16,  16,    1,  -15 },   // 0x65 'e'\n  {  3368,  11,  24,  14,    2,  -23 },   // 0x66 'f'\n  {  3401,  17,  23,  17,    1,  -15 },   // 0x67 'g'\n  {  3450,  17,  24,  19,    1,  -23 },   // 0x68 'h'\n  {  3501,   7,  24,  10,    2,  -23 },   // 0x69 'i'\n  {  3522,  11,  31,  14,    0,  -23 },   // 0x6A 'j'\n  {  3565,  18,  24,  19,    1,  -23 },   // 0x6B 'k'\n  {  3619,   7,  24,  10,    1,  -23 },   // 0x6C 'l'\n  {  3640,  27,  16,  29,    1,  -15 },   // 0x6D 'm'\n  {  3694,  17,  16,  19,    1,  -15 },   // 0x6E 'n'\n  {  3728,  17,  16,  18,    1,  -15 },   // 0x6F 'o'\n  {  3762,  19,  23,  19,    0,  -15 },   // 0x70 'p'\n  {  3817,  17,  23,  19,    1,  -15 },   // 0x71 'q'\n  {  3866,  13,  16,  15,    1,  -15 },   // 0x72 'r'\n  {  3892,  12,  16,  14,    1,  -15 },   // 0x73 's'\n  {  3916,  10,  21,  12,    1,  -20 },   // 0x74 't'\n  {  3943,  18,  16,  20,    1,  -15 },   // 0x75 'u'\n  {  3979,  17,  16,  17,    0,  -15 },   // 0x76 'v'\n  {  4013,  24,  16,  25,    0,  -15 },   // 0x77 'w'\n  {  4061,  16,  16,  18,    1,  -15 },   // 0x78 'x'\n  {  4093,  16,  23,  17,    0,  -15 },   // 0x79 'y'\n  {  4139,  14,  16,  16,    0,  -15 },   // 0x7A 'z'\n  {  4167,  11,  31,  14,    1,  -24 },   // 0x7B '{'\n  {  4210,   3,  25,   8,    2,  -23 },   // 0x7C '|'\n  {  4220,  11,  31,  14,    3,  -24 },   // 0x7D '}'\n  {  4263,  16,   5,  18,    1,  -11 } }; // 0x7E '~'\n\nconst GFXfont FreeSerifBold18pt7b PROGMEM = {\n  (uint8_t  *)FreeSerifBold18pt7bBitmaps,\n  (GFXglyph *)FreeSerifBold18pt7bGlyphs,\n  0x20, 0x7E, 42 };\n\n// Approx. 4945 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeSerifBold24pt7b.h",
    "content": "const uint8_t FreeSerifBold24pt7bBitmaps[] PROGMEM = {\n  0x3C, 0x7E, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x7E, 0x7E, 0x7C, 0x7C,\n  0x3C, 0x3C, 0x38, 0x38, 0x38, 0x38, 0x18, 0x10, 0x10, 0x10, 0x00, 0x00,\n  0x00, 0x00, 0x3C, 0x7E, 0xFF, 0xFF, 0xFF, 0xFF, 0x7E, 0x3C, 0x70, 0x07,\n  0x7C, 0x07, 0xFE, 0x03, 0xFF, 0x01, 0xFF, 0x80, 0xFF, 0xC0, 0x7F, 0xC0,\n  0x3E, 0xE0, 0x0E, 0x70, 0x07, 0x38, 0x03, 0x9C, 0x01, 0xC4, 0x00, 0xE2,\n  0x00, 0x20, 0x00, 0xF0, 0x70, 0x01, 0xC0, 0xE0, 0x03, 0x81, 0xC0, 0x0F,\n  0x07, 0x80, 0x1E, 0x0F, 0x00, 0x3C, 0x1E, 0x00, 0x78, 0x3C, 0x00, 0xF0,\n  0x78, 0x01, 0xC0, 0xE0, 0x03, 0x81, 0xC0, 0xFF, 0xFF, 0xF9, 0xFF, 0xFF,\n  0xF3, 0xFF, 0xFF, 0xE0, 0x78, 0x3C, 0x00, 0xF0, 0x78, 0x01, 0xC0, 0xE0,\n  0x03, 0x81, 0xC0, 0x0F, 0x07, 0x80, 0x1E, 0x0F, 0x00, 0x3C, 0x1E, 0x0F,\n  0xFF, 0xFF, 0xDF, 0xFF, 0xFF, 0xBF, 0xFF, 0xFF, 0x03, 0x81, 0xC0, 0x0F,\n  0x07, 0x80, 0x1E, 0x0F, 0x00, 0x3C, 0x1E, 0x00, 0x78, 0x3C, 0x00, 0xF0,\n  0x78, 0x01, 0xE0, 0xE0, 0x03, 0x81, 0xC0, 0x07, 0x07, 0x80, 0x1E, 0x0F,\n  0x00, 0x00, 0x60, 0x00, 0x03, 0x00, 0x00, 0x18, 0x00, 0x00, 0xC0, 0x00,\n  0x7F, 0xF0, 0x0F, 0x37, 0xE0, 0xE1, 0x8F, 0x8E, 0x0C, 0x3C, 0x70, 0x60,\n  0xE7, 0x83, 0x03, 0x3C, 0x18, 0x19, 0xF0, 0xC0, 0x4F, 0xC6, 0x02, 0x7F,\n  0xF0, 0x03, 0xFF, 0x80, 0x0F, 0xFE, 0x00, 0x3F, 0xFC, 0x00, 0xFF, 0xF0,\n  0x03, 0xFF, 0xE0, 0x0F, 0xFF, 0x80, 0x1F, 0xFE, 0x00, 0x3F, 0xF8, 0x01,\n  0xFF, 0xC0, 0x0C, 0xFF, 0x00, 0x63, 0xFA, 0x03, 0x0F, 0xD0, 0x18, 0x3E,\n  0x80, 0xC1, 0xF6, 0x06, 0x0F, 0xB8, 0x30, 0x79, 0xC1, 0x87, 0xCF, 0x0C,\n  0x3C, 0x7E, 0x67, 0xC0, 0xFF, 0xF8, 0x00, 0xFE, 0x00, 0x00, 0xC0, 0x00,\n  0x06, 0x00, 0x00, 0x30, 0x00, 0x01, 0x80, 0x00, 0x00, 0x00, 0x00, 0x30,\n  0x00, 0x3E, 0x00, 0x0C, 0x00, 0x0F, 0xF0, 0x03, 0x80, 0x07, 0xE7, 0x03,\n  0xE0, 0x01, 0xF8, 0x7F, 0xFC, 0x00, 0x3E, 0x07, 0xF7, 0x00, 0x0F, 0xC0,\n  0x80, 0xE0, 0x03, 0xF0, 0x10, 0x38, 0x00, 0x7E, 0x02, 0x07, 0x00, 0x0F,\n  0x80, 0x41, 0xC0, 0x03, 0xF0, 0x10, 0x30, 0x00, 0x7E, 0x02, 0x0E, 0x00,\n  0x0F, 0x80, 0xC1, 0x80, 0x01, 0xF0, 0x10, 0x70, 0x00, 0x3E, 0x06, 0x1C,\n  0x00, 0x07, 0xC1, 0x83, 0x80, 0x00, 0x7C, 0x60, 0xE0, 0x1F, 0x07, 0xF8,\n  0x18, 0x0F, 0xF8, 0x7C, 0x07, 0x07, 0xF1, 0x00, 0x00, 0xC1, 0xF8, 0x10,\n  0x00, 0x38, 0x3F, 0x02, 0x00, 0x06, 0x0F, 0xC0, 0x40, 0x01, 0xC3, 0xF0,\n  0x08, 0x00, 0x30, 0x7E, 0x01, 0x00, 0x0E, 0x1F, 0x80, 0x40, 0x03, 0x83,\n  0xF0, 0x08, 0x00, 0x60, 0x7E, 0x01, 0x00, 0x1C, 0x0F, 0x80, 0x40, 0x03,\n  0x01, 0xF0, 0x18, 0x00, 0xE0, 0x3E, 0x02, 0x00, 0x18, 0x03, 0xC0, 0xC0,\n  0x07, 0x00, 0x7C, 0x70, 0x00, 0xC0, 0x07, 0xFC, 0x00, 0x38, 0x00, 0x7E,\n  0x00, 0x00, 0x0F, 0xE0, 0x00, 0x00, 0x0F, 0xFE, 0x00, 0x00, 0x07, 0x8F,\n  0xE0, 0x00, 0x03, 0xC1, 0xF8, 0x00, 0x00, 0xF0, 0x3F, 0x00, 0x00, 0x7C,\n  0x07, 0xC0, 0x00, 0x1F, 0x01, 0xF0, 0x00, 0x07, 0xE0, 0x7C, 0x00, 0x01,\n  0xF8, 0x1E, 0x00, 0x00, 0x7F, 0x07, 0x80, 0x00, 0x1F, 0xE3, 0x80, 0x00,\n  0x03, 0xFF, 0xC0, 0x00, 0x00, 0xFF, 0x80, 0x00, 0x00, 0x1F, 0xE0, 0x3F,\n  0xF0, 0x07, 0xFC, 0x01, 0xF0, 0x07, 0xFF, 0x00, 0x78, 0x07, 0xBF, 0xE0,\n  0x1C, 0x03, 0x87, 0xFC, 0x07, 0x01, 0xE0, 0xFF, 0x81, 0x80, 0xF0, 0x3F,\n  0xE0, 0xC0, 0x7C, 0x07, 0xFC, 0x30, 0x1F, 0x00, 0xFF, 0x98, 0x0F, 0xC0,\n  0x3F, 0xFC, 0x03, 0xF0, 0x07, 0xFF, 0x00, 0xFE, 0x00, 0xFF, 0x80, 0x3F,\n  0x80, 0x3F, 0xF0, 0x0F, 0xF0, 0x07, 0xFE, 0x03, 0xFC, 0x00, 0xFF, 0x81,\n  0x7F, 0x80, 0x3F, 0xF8, 0xDF, 0xF0, 0x1F, 0xFF, 0xE3, 0xFF, 0x0E, 0xFF,\n  0xF8, 0xFF, 0xFE, 0x1F, 0xFC, 0x0F, 0xFE, 0x03, 0xFE, 0x00, 0xFE, 0x00,\n  0x3E, 0x00, 0x77, 0xFF, 0xFF, 0xFF, 0xEE, 0x73, 0x9C, 0xE2, 0x00, 0x00,\n  0x00, 0x03, 0x00, 0x60, 0x1C, 0x03, 0x80, 0x70, 0x06, 0x00, 0xE0, 0x1C,\n  0x01, 0xC0, 0x3C, 0x03, 0xC0, 0x78, 0x07, 0x80, 0x78, 0x07, 0x80, 0xF8,\n  0x0F, 0x80, 0xF8, 0x0F, 0x80, 0xF8, 0x0F, 0x80, 0xF8, 0x0F, 0x80, 0xF8,\n  0x0F, 0x80, 0x78, 0x07, 0x80, 0x78, 0x03, 0xC0, 0x3C, 0x01, 0xC0, 0x1C,\n  0x00, 0xE0, 0x0E, 0x00, 0x70, 0x03, 0x00, 0x18, 0x00, 0xC0, 0x03, 0x00,\n  0x10, 0x00, 0x0C, 0x00, 0x60, 0x03, 0x00, 0x18, 0x00, 0xC0, 0x06, 0x00,\n  0x70, 0x03, 0x80, 0x38, 0x03, 0xC0, 0x3C, 0x03, 0xE0, 0x1E, 0x01, 0xE0,\n  0x1E, 0x01, 0xF0, 0x1F, 0x01, 0xF0, 0x1F, 0x01, 0xF0, 0x1F, 0x01, 0xF0,\n  0x1F, 0x01, 0xF0, 0x1F, 0x01, 0xE0, 0x1E, 0x01, 0xE0, 0x3C, 0x03, 0xC0,\n  0x38, 0x03, 0x80, 0x70, 0x07, 0x00, 0xE0, 0x0C, 0x01, 0x80, 0x30, 0x0C,\n  0x00, 0x80, 0x00, 0x01, 0xC0, 0x00, 0xF8, 0x00, 0x3E, 0x00, 0x0F, 0x80,\n  0x03, 0xE0, 0x3C, 0x78, 0xEF, 0x9C, 0x7B, 0xF7, 0x3F, 0xFE, 0xDF, 0x8F,\n  0xFF, 0xC0, 0x7F, 0x00, 0x3F, 0xC0, 0x7E, 0xBF, 0x3F, 0x77, 0xEF, 0x9C,\n  0xFF, 0xC7, 0x1E, 0x63, 0xE3, 0x80, 0xF8, 0x00, 0x3E, 0x00, 0x0F, 0x80,\n  0x01, 0xC0, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x07, 0x80, 0x00, 0x01, 0xE0,\n  0x00, 0x00, 0x78, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x07, 0x80, 0x00, 0x01,\n  0xE0, 0x00, 0x00, 0x78, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x07, 0x80, 0x0F,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFC, 0x00, 0x78, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x07,\n  0x80, 0x00, 0x01, 0xE0, 0x00, 0x00, 0x78, 0x00, 0x00, 0x1E, 0x00, 0x00,\n  0x07, 0x80, 0x00, 0x01, 0xE0, 0x00, 0x00, 0x78, 0x00, 0x00, 0x1E, 0x00,\n  0x00, 0x3C, 0x7E, 0xFE, 0xFF, 0xFF, 0xFF, 0x7F, 0x07, 0x06, 0x06, 0x0C,\n  0x18, 0x30, 0x60, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0x3C,\n  0x7E, 0xFF, 0xFF, 0xFF, 0xFF, 0x7E, 0x3C, 0x00, 0x1E, 0x00, 0x7C, 0x00,\n  0xF0, 0x01, 0xE0, 0x07, 0xC0, 0x0F, 0x00, 0x1E, 0x00, 0x7C, 0x00, 0xF0,\n  0x01, 0xE0, 0x07, 0xC0, 0x0F, 0x00, 0x1E, 0x00, 0x7C, 0x00, 0xF0, 0x01,\n  0xE0, 0x07, 0xC0, 0x0F, 0x00, 0x1E, 0x00, 0x7C, 0x00, 0xF0, 0x01, 0xE0,\n  0x03, 0xC0, 0x0F, 0x00, 0x1E, 0x00, 0x3C, 0x00, 0xF0, 0x01, 0xE0, 0x03,\n  0xC0, 0x0F, 0x00, 0x1E, 0x00, 0x3C, 0x00, 0xF0, 0x00, 0x00, 0xFC, 0x00,\n  0x0F, 0x3C, 0x00, 0x78, 0x78, 0x03, 0xE1, 0xF0, 0x1F, 0x03, 0xE0, 0x7C,\n  0x0F, 0x83, 0xF0, 0x3F, 0x0F, 0xC0, 0xFC, 0x7F, 0x03, 0xF9, 0xFC, 0x0F,\n  0xE7, 0xF0, 0x3F, 0xBF, 0xC0, 0xFE, 0xFF, 0x03, 0xFF, 0xFC, 0x0F, 0xFF,\n  0xF0, 0x3F, 0xFF, 0xC0, 0xFF, 0xFF, 0x03, 0xFF, 0xFC, 0x0F, 0xFF, 0xF0,\n  0x3F, 0xFF, 0xC0, 0xFF, 0xFF, 0x03, 0xFF, 0xFC, 0x0F, 0xFF, 0xF0, 0x3F,\n  0x9F, 0xC0, 0xFE, 0x7F, 0x03, 0xF9, 0xFC, 0x0F, 0xE3, 0xF0, 0x3F, 0x0F,\n  0xC0, 0xFC, 0x1F, 0x03, 0xE0, 0x7C, 0x0F, 0x80, 0xF8, 0x7C, 0x01, 0xE1,\n  0xE0, 0x03, 0xCF, 0x00, 0x03, 0xF0, 0x00, 0x00, 0x18, 0x00, 0x1E, 0x00,\n  0x1F, 0x80, 0x1F, 0xE0, 0x1F, 0xF8, 0x1D, 0xFE, 0x00, 0x3F, 0x80, 0x0F,\n  0xE0, 0x03, 0xF8, 0x00, 0xFE, 0x00, 0x3F, 0x80, 0x0F, 0xE0, 0x03, 0xF8,\n  0x00, 0xFE, 0x00, 0x3F, 0x80, 0x0F, 0xE0, 0x03, 0xF8, 0x00, 0xFE, 0x00,\n  0x3F, 0x80, 0x0F, 0xE0, 0x03, 0xF8, 0x00, 0xFE, 0x00, 0x3F, 0x80, 0x0F,\n  0xE0, 0x03, 0xF8, 0x00, 0xFE, 0x00, 0x3F, 0x80, 0x0F, 0xE0, 0x03, 0xF8,\n  0x00, 0xFE, 0x00, 0x7F, 0x80, 0x3F, 0xF8, 0xFF, 0xFF, 0xC0, 0x00, 0xFC,\n  0x00, 0x1F, 0xF8, 0x03, 0xFF, 0xE0, 0x3F, 0xFF, 0x81, 0xFF, 0xFC, 0x1C,\n  0x1F, 0xF1, 0xC0, 0x7F, 0x8C, 0x01, 0xFC, 0x40, 0x0F, 0xE0, 0x00, 0x3F,\n  0x00, 0x01, 0xF8, 0x00, 0x0F, 0xC0, 0x00, 0x7C, 0x00, 0x03, 0xE0, 0x00,\n  0x3E, 0x00, 0x01, 0xF0, 0x00, 0x0F, 0x00, 0x00, 0xF0, 0x00, 0x07, 0x00,\n  0x00, 0x70, 0x00, 0x07, 0x80, 0x00, 0x38, 0x00, 0x03, 0x80, 0x00, 0x38,\n  0x01, 0x03, 0x80, 0x18, 0x38, 0x00, 0x81, 0x80, 0x1C, 0x1F, 0xFF, 0xE1,\n  0xFF, 0xFF, 0x1F, 0xFF, 0xF9, 0xFF, 0xFF, 0x9F, 0xFF, 0xFC, 0xFF, 0xFF,\n  0xE0, 0x00, 0xFE, 0x00, 0x3F, 0xFC, 0x03, 0xFF, 0xF0, 0x30, 0xFF, 0xC2,\n  0x01, 0xFE, 0x30, 0x0F, 0xF1, 0x00, 0x3F, 0x80, 0x01, 0xFC, 0x00, 0x0F,\n  0xE0, 0x00, 0x7E, 0x00, 0x03, 0xF0, 0x00, 0x3F, 0x00, 0x01, 0xF0, 0x00,\n  0x1F, 0xC0, 0x03, 0xFF, 0x00, 0x3F, 0xFC, 0x00, 0x7F, 0xF0, 0x00, 0xFF,\n  0x80, 0x03, 0xFE, 0x00, 0x0F, 0xF0, 0x00, 0x3F, 0x80, 0x00, 0xFC, 0x00,\n  0x07, 0xE0, 0x00, 0x1F, 0x00, 0x00, 0xF8, 0x00, 0x07, 0x80, 0x00, 0x3C,\n  0x00, 0x01, 0xC7, 0x80, 0x0E, 0x7F, 0x00, 0xE3, 0xFC, 0x06, 0x1F, 0xF8,\n  0xE0, 0x7F, 0xFC, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x03, 0xC0, 0x00, 0x1E,\n  0x00, 0x01, 0xF0, 0x00, 0x1F, 0x80, 0x01, 0xFC, 0x00, 0x0F, 0xE0, 0x00,\n  0xFF, 0x00, 0x0D, 0xF8, 0x00, 0xEF, 0xC0, 0x06, 0x7E, 0x00, 0x63, 0xF0,\n  0x07, 0x1F, 0x80, 0x30, 0xFC, 0x03, 0x07, 0xE0, 0x38, 0x3F, 0x03, 0x81,\n  0xF8, 0x18, 0x0F, 0xC1, 0xC0, 0x7E, 0x1C, 0x03, 0xF0, 0xC0, 0x1F, 0x8E,\n  0x00, 0xFC, 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xC0, 0x03, 0xF0, 0x00, 0x1F, 0x80, 0x00, 0xFC, 0x00,\n  0x07, 0xE0, 0x00, 0x3F, 0x00, 0x01, 0xF8, 0x00, 0x0F, 0xC0, 0x07, 0xFF,\n  0xF0, 0x7F, 0xFF, 0x0F, 0xFF, 0xE0, 0xFF, 0xFE, 0x0F, 0xFF, 0xE1, 0xFF,\n  0xFC, 0x18, 0x00, 0x01, 0x80, 0x00, 0x18, 0x00, 0x03, 0x00, 0x00, 0x3F,\n  0x80, 0x03, 0xFF, 0x80, 0x7F, 0xFE, 0x07, 0xFF, 0xF0, 0x7F, 0xFF, 0x87,\n  0xFF, 0xFC, 0x7F, 0xFF, 0xC0, 0x07, 0xFC, 0x00, 0x1F, 0xE0, 0x00, 0x7E,\n  0x00, 0x03, 0xE0, 0x00, 0x1E, 0x00, 0x00, 0xE0, 0x00, 0x0E, 0x00, 0x00,\n  0xC0, 0x00, 0x0C, 0x78, 0x00, 0x8F, 0xE0, 0x18, 0xFF, 0x87, 0x0F, 0xFF,\n  0xE0, 0x7F, 0xF8, 0x01, 0xFE, 0x00, 0x00, 0x00, 0x38, 0x00, 0x1F, 0x00,\n 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0xFF, 0x00, 0x03, 0xF8,\n  0x00, 0x1F, 0xE0, 0x00, 0x7F, 0x00, 0x03, 0xF8, 0x00, 0x0F, 0xC0, 0x00,\n  0x7E, 0x00, 0x03, 0xF0, 0x00, 0x3F, 0x00, 0x01, 0xF0, 0x00, 0x3F, 0x00,\n  0x03, 0x80, 0x00, 0x00, 0x3C, 0x7E, 0xFF, 0xFF, 0xFF, 0xFF, 0x7E, 0x3C,\n  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x7E, 0xFF, 0xFF,\n  0xFF, 0xFF, 0x7E, 0x3C, 0x3C, 0x3F, 0x3F, 0xDF, 0xEF, 0xF7, 0xF9, 0xF8,\n  0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x7F, 0x7F,\n  0xBF, 0xFF, 0xFF, 0xFB, 0xFC, 0xFE, 0x07, 0x03, 0x01, 0x81, 0x81, 0x81,\n  0x83, 0x81, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0xF0, 0x00, 0x00,\n  0xFC, 0x00, 0x00, 0xFF, 0x00, 0x00, 0xFF, 0xC0, 0x01, 0xFF, 0x80, 0x01,\n  0xFF, 0x80, 0x01, 0xFF, 0x80, 0x01, 0xFF, 0x80, 0x01, 0xFF, 0x80, 0x01,\n  0xFF, 0x80, 0x01, 0xFF, 0x80, 0x00, 0xFF, 0x80, 0x00, 0x3F, 0xE0, 0x00,\n  0x07, 0xFE, 0x00, 0x00, 0x7F, 0xE0, 0x00, 0x07, 0xFE, 0x00, 0x00, 0x7F,\n  0xE0, 0x00, 0x07, 0xFF, 0x00, 0x00, 0x3F, 0xF0, 0x00, 0x03, 0xFF, 0x00,\n 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0xF0, 0x00, 0xFF, 0x0F,\n  0xF0, 0x00, 0xFF, 0x0F, 0xF0, 0x00, 0xFF, 0x0F, 0xF0, 0x00, 0xFF, 0x0F,\n  0xF0, 0x00, 0xFF, 0x0F, 0xF0, 0x00, 0xFF, 0x0F, 0xF0, 0x00, 0xFF, 0x0F,\n  0xF0, 0x00, 0xFE, 0x0F, 0xF0, 0x00, 0xFE, 0x0F, 0xF0, 0x01, 0xFE, 0x0F,\n  0xF0, 0x01, 0xFC, 0x0F, 0xF0, 0x01, 0xFC, 0x0F, 0xF0, 0x03, 0xF8, 0x0F,\n  0xF0, 0x03, 0xF0, 0x0F, 0xF0, 0x07, 0xE0, 0x0F, 0xF0, 0x0F, 0xC0, 0x0F,\n  0xF8, 0x3F, 0x80, 0x1F, 0xFF, 0xFE, 0x00, 0xFF, 0xFF, 0xF0, 0x00, 0xFF,\n  0xFF, 0xFF, 0xC3, 0xFF, 0xFF, 0xFC, 0x1F, 0xE0, 0x1F, 0xC1, 0xFE, 0x00,\n  0x3C, 0x1F, 0xE0, 0x01, 0xC1, 0xFE, 0x00, 0x0C, 0x1F, 0xE0, 0x00, 0xC1,\n  0xFE, 0x00, 0x04, 0x1F, 0xE0, 0x20, 0x41, 0xFE, 0x02, 0x00, 0x1F, 0xE0,\n  0x60, 0x01, 0xFE, 0x06, 0x00, 0x1F, 0xE0, 0xE0, 0x01, 0xFE, 0x1E, 0x00,\n  0x1F, 0xFF, 0xE0, 0x01, 0xFF, 0xFE, 0x00, 0x1F, 0xE3, 0xE0, 0x01, 0xFE,\n  0x0E, 0x00, 0x1F, 0xE0, 0x60, 0x01, 0xFE, 0x06, 0x00, 0x1F, 0xE0, 0x20,\n  0x01, 0xFE, 0x02, 0x00, 0x1F, 0xE0, 0x00, 0x11, 0xFE, 0x00, 0x03, 0x1F,\n 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0x3F, 0x80, 0x00, 0x38, 0x1F, 0xC0, 0x00, 0x0C,\n  0x1F, 0xE0, 0x00, 0x06, 0x0F, 0xE0, 0x00, 0x01, 0x07, 0xF0, 0x00, 0x00,\n  0x07, 0xF8, 0x00, 0x00, 0x03, 0xFC, 0x00, 0x00, 0x01, 0xFE, 0x00, 0x00,\n  0x00, 0xFF, 0x00, 0x00, 0x00, 0x7F, 0x80, 0x00, 0x00, 0x3F, 0xC0, 0x00,\n  0x00, 0x1F, 0xE0, 0x00, 0x00, 0x0F, 0xF0, 0x03, 0xFF, 0xFF, 0xF8, 0x00,\n  0x3F, 0xF1, 0xFC, 0x00, 0x0F, 0xF0, 0xFF, 0x00, 0x07, 0xF8, 0x7F, 0x80,\n  0x03, 0xFC, 0x1F, 0xC0, 0x01, 0xFE, 0x0F, 0xE0, 0x00, 0xFF, 0x03, 0xF8,\n  0x00, 0x7F, 0x80, 0xFC, 0x00, 0x3F, 0xC0, 0x3F, 0x00, 0x1F, 0xE0, 0x0F,\n  0xC0, 0x0F, 0xF0, 0x03, 0xF8, 0x1F, 0xF0, 0x00, 0x7F, 0xFF, 0xC0, 0x00,\n  0x07, 0xFE, 0x00, 0x00, 0xFF, 0xFC, 0x1F, 0xFF, 0x9F, 0xF8, 0x03, 0xFF,\n  0x07, 0xF8, 0x00, 0xFF, 0x03, 0xFC, 0x00, 0x7F, 0x81, 0xFE, 0x00, 0x3F,\n  0xC0, 0xFF, 0x00, 0x1F, 0xE0, 0x7F, 0x80, 0x0F, 0xF0, 0x3F, 0xC0, 0x07,\n  0xF8, 0x1F, 0xE0, 0x03, 0xFC, 0x0F, 0xF0, 0x01, 0xFE, 0x07, 0xF8, 0x00,\n  0xFF, 0x03, 0xFC, 0x00, 0x7F, 0x81, 0xFE, 0x00, 0x3F, 0xC0, 0xFF, 0x00,\n  0x1F, 0xE0, 0x7F, 0x80, 0x0F, 0xF0, 0x3F, 0xFF, 0xFF, 0xF8, 0x1F, 0xFF,\n  0xFF, 0xFC, 0x0F, 0xF0, 0x01, 0xFE, 0x07, 0xF8, 0x00, 0xFF, 0x03, 0xFC,\n  0x00, 0x7F, 0x81, 0xFE, 0x00, 0x3F, 0xC0, 0xFF, 0x00, 0x1F, 0xE0, 0x7F,\n  0x80, 0x0F, 0xF0, 0x3F, 0xC0, 0x07, 0xF8, 0x1F, 0xE0, 0x03, 0xFC, 0x0F,\n  0xF0, 0x01, 0xFE, 0x07, 0xF8, 0x00, 0xFF, 0x03, 0xFC, 0x00, 0x7F, 0x81,\n  0xFE, 0x00, 0x3F, 0xC0, 0xFF, 0x00, 0x1F, 0xE0, 0xFF, 0xC0, 0x1F, 0xF9,\n  0xFF, 0xF8, 0x3F, 0xFF, 0xFF, 0xFE, 0x7F, 0xE0, 0x7F, 0x80, 0xFF, 0x01,\n  0xFE, 0x03, 0xFC, 0x07, 0xF8, 0x0F, 0xF0, 0x1F, 0xE0, 0x3F, 0xC0, 0x7F,\n  0x80, 0xFF, 0x01, 0xFE, 0x03, 0xFC, 0x07, 0xF8, 0x0F, 0xF0, 0x1F, 0xE0,\n  0x3F, 0xC0, 0x7F, 0x80, 0xFF, 0x01, 0xFE, 0x03, 0xFC, 0x07, 0xF8, 0x0F,\n  0xF0, 0x1F, 0xE0, 0x3F, 0xC0, 0x7F, 0x80, 0xFF, 0x01, 0xFE, 0x03, 0xFC,\n  0x0F, 0xFC, 0x7F, 0xFF, 0x01, 0xFF, 0xFC, 0x00, 0xFF, 0xC0, 0x01, 0xFE,\n  0x00, 0x07, 0xF8, 0x00, 0x1F, 0xE0, 0x00, 0x7F, 0x80, 0x01, 0xFE, 0x00,\n  0x07, 0xF8, 0x00, 0x1F, 0xE0, 0x00, 0x7F, 0x80, 0x01, 0xFE, 0x00, 0x07,\n  0xF8, 0x00, 0x1F, 0xE0, 0x00, 0x7F, 0x80, 0x01, 0xFE, 0x00, 0x07, 0xF8,\n  0x00, 0x1F, 0xE0, 0x00, 0x7F, 0x80, 0x01, 0xFE, 0x00, 0x07, 0xF8, 0x00,\n  0x1F, 0xE0, 0x00, 0x7F, 0x80, 0x01, 0xFE, 0x00, 0x07, 0xF8, 0x00, 0x1F,\n  0xE0, 0x00, 0x7F, 0x80, 0x01, 0xFE, 0x00, 0x07, 0xF8, 0x78, 0x1F, 0xE3,\n  0xF0, 0x7F, 0x8F, 0xC1, 0xFC, 0x3F, 0x07, 0xF0, 0xFC, 0x1F, 0xC1, 0xE0,\n  0xFE, 0x07, 0xC3, 0xF0, 0x0F, 0xFF, 0x80, 0x07, 0xF0, 0x00, 0xFF, 0xFC,\n  0x1F, 0xFF, 0x0F, 0xFC, 0x00, 0xFF, 0x01, 0xFE, 0x00, 0x1E, 0x00, 0x7F,\n  0x80, 0x07, 0x00, 0x1F, 0xE0, 0x03, 0x80, 0x07, 0xF8, 0x01, 0xC0, 0x01,\n  0xFE, 0x00, 0xE0, 0x00, 0x7F, 0x80, 0x70, 0x00, 0x1F, 0xE0, 0x38, 0x00,\n  0x07, 0xF8, 0x1C, 0x00, 0x01, 0xFE, 0x0E, 0x00, 0x00, 0x7F, 0x87, 0x00,\n  0x00, 0x1F, 0xE3, 0xC0, 0x00, 0x07, 0xF9, 0xF8, 0x00, 0x01, 0xFE, 0xFE,\n  0x00, 0x00, 0x7F, 0xFF, 0xC0, 0x00, 0x1F, 0xFF, 0xF8, 0x00, 0x07, 0xFD,\n  0xFF, 0x00, 0x01, 0xFE, 0x7F, 0xE0, 0x00, 0x7F, 0x8F, 0xF8, 0x00, 0x1F,\n  0xE1, 0xFF, 0x00, 0x07, 0xF8, 0x3F, 0xE0, 0x01, 0xFE, 0x07, 0xFC, 0x00,\n  0x7F, 0x81, 0xFF, 0x80, 0x1F, 0xE0, 0x3F, 0xE0, 0x07, 0xF8, 0x07, 0xFC,\n  0x01, 0xFE, 0x00, 0xFF, 0x80, 0x7F, 0x80, 0x1F, 0xF0, 0x1F, 0xE0, 0x07,\n  0xFE, 0x07, 0xF8, 0x00, 0xFF, 0x83, 0xFF, 0x00, 0x3F, 0xF3, 0xFF, 0xF0,\n  0xFF, 0xFF, 0xFF, 0xFE, 0x00, 0x03, 0xFF, 0x00, 0x00, 0x1F, 0xE0, 0x00,\n  0x01, 0xFE, 0x00, 0x00, 0x1F, 0xE0, 0x00, 0x01, 0xFE, 0x00, 0x00, 0x1F,\n  0xE0, 0x00, 0x01, 0xFE, 0x00, 0x00, 0x1F, 0xE0, 0x00, 0x01, 0xFE, 0x00,\n  0x00, 0x1F, 0xE0, 0x00, 0x01, 0xFE, 0x00, 0x00, 0x1F, 0xE0, 0x00, 0x01,\n  0xFE, 0x00, 0x00, 0x1F, 0xE0, 0x00, 0x01, 0xFE, 0x00, 0x00, 0x1F, 0xE0,\n  0x00, 0x01, 0xFE, 0x00, 0x00, 0x1F, 0xE0, 0x00, 0x01, 0xFE, 0x00, 0x00,\n  0x1F, 0xE0, 0x00, 0x01, 0xFE, 0x00, 0x01, 0x1F, 0xE0, 0x00, 0x31, 0xFE,\n  0x00, 0x03, 0x1F, 0xE0, 0x00, 0x71, 0xFE, 0x00, 0x07, 0x1F, 0xE0, 0x00,\n  0xE1, 0xFE, 0x00, 0x1E, 0x1F, 0xE0, 0x07, 0xE3, 0xFF, 0x01, 0xFE, 0xFF,\n  0xFF, 0xFF, 0xEF, 0xFF, 0xFF, 0xFE, 0x7F, 0xF0, 0x00, 0x01, 0xFF, 0xE1,\n  0xFF, 0x00, 0x00, 0x3F, 0xF0, 0x1F, 0xE0, 0x00, 0x0F, 0xFC, 0x03, 0xFC,\n  0x00, 0x01, 0xFF, 0x80, 0x7F, 0xC0, 0x00, 0x2F, 0xF0, 0x0B, 0xF8, 0x00,\n  0x0D, 0xFE, 0x01, 0x7F, 0x80, 0x01, 0xBF, 0xC0, 0x27, 0xF0, 0x00, 0x67,\n  0xF8, 0x04, 0xFF, 0x00, 0x0C, 0xFF, 0x00, 0x8F, 0xE0, 0x03, 0x1F, 0xE0,\n  0x11, 0xFE, 0x00, 0x63, 0xFC, 0x02, 0x3F, 0xC0, 0x08, 0x7F, 0x80, 0x43,\n  0xF8, 0x03, 0x0F, 0xF0, 0x08, 0x7F, 0x80, 0x61, 0xFE, 0x01, 0x07, 0xF0,\n  0x18, 0x3F, 0xC0, 0x20, 0xFF, 0x03, 0x07, 0xF8, 0x04, 0x0F, 0xE0, 0xC0,\n  0xFF, 0x00, 0x81, 0xFE, 0x18, 0x1F, 0xE0, 0x10, 0x3F, 0xC6, 0x03, 0xFC,\n  0x02, 0x03, 0xF8, 0xC0, 0x7F, 0x80, 0x40, 0x7F, 0x98, 0x0F, 0xF0, 0x08,\n  0x07, 0xF6, 0x01, 0xFE, 0x01, 0x00, 0xFF, 0xC0, 0x3F, 0xC0, 0x20, 0x0F,\n  0xF0, 0x07, 0xF8, 0x04, 0x01, 0xFE, 0x00, 0xFF, 0x00, 0x80, 0x1F, 0x80,\n  0x1F, 0xE0, 0x10, 0x03, 0xF0, 0x03, 0xFC, 0x02, 0x00, 0x7E, 0x00, 0x7F,\n  0x80, 0x40, 0x07, 0x80, 0x0F, 0xF0, 0x0C, 0x00, 0xF0, 0x01, 0xFE, 0x07,\n  0xC0, 0x0C, 0x00, 0x7F, 0xE7, 0xFF, 0x01, 0x80, 0x3F, 0xFF, 0xFF, 0xC0,\n  0x03, 0xFE, 0xFF, 0xC0, 0x01, 0xF0, 0xFF, 0xC0, 0x01, 0xC0, 0xFF, 0xC0,\n  0x01, 0x80, 0xFF, 0x80, 0x03, 0x01, 0xFF, 0x80, 0x06, 0x03, 0xFF, 0x80,\n  0x0C, 0x07, 0xFF, 0x80, 0x18, 0x0D, 0xFF, 0x80, 0x30, 0x19, 0xFF, 0x00,\n  0x60, 0x31, 0xFF, 0x00, 0xC0, 0x61, 0xFF, 0x01, 0x80, 0xC1, 0xFF, 0x03,\n  0x01, 0x83, 0xFF, 0x06, 0x03, 0x03, 0xFE, 0x0C, 0x06, 0x03, 0xFE, 0x18,\n  0x0C, 0x03, 0xFE, 0x30, 0x18, 0x03, 0xFE, 0x60, 0x30, 0x03, 0xFE, 0xC0,\n  0x60, 0x07, 0xFD, 0x80, 0xC0, 0x07, 0xFF, 0x01, 0x80, 0x07, 0xFE, 0x03,\n  0x00, 0x07, 0xFC, 0x06, 0x00, 0x07, 0xF8, 0x0C, 0x00, 0x07, 0xF0, 0x18,\n  0x00, 0x0F, 0xE0, 0x30, 0x00, 0x0F, 0xC0, 0x60, 0x00, 0x0F, 0x80, 0xC0,\n  0x00, 0x0F, 0x01, 0xC0, 0x00, 0x0E, 0x0F, 0xC0, 0x00, 0x1C, 0x7F, 0xE0,\n  0x00, 0x18, 0x00, 0x0F, 0xF8, 0x00, 0x00, 0x3F, 0xFF, 0x80, 0x00, 0x3F,\n  0x07, 0xF0, 0x00, 0x7E, 0x00, 0xFC, 0x00, 0x7E, 0x00, 0x3F, 0x00, 0x7E,\n  0x00, 0x1F, 0xC0, 0x7F, 0x00, 0x07, 0xF0, 0x3F, 0x00, 0x03, 0xF8, 0x3F,\n  0x80, 0x00, 0xFE, 0x3F, 0xC0, 0x00, 0x7F, 0x1F, 0xE0, 0x00, 0x3F, 0xCF,\n  0xE0, 0x00, 0x0F, 0xEF, 0xF0, 0x00, 0x07, 0xF7, 0xF8, 0x00, 0x03, 0xFF,\n  0xFC, 0x00, 0x01, 0xFF, 0xFE, 0x00, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x7F,\n  0xFF, 0x80, 0x00, 0x3F, 0xFF, 0xC0, 0x00, 0x1F, 0xFF, 0xE0, 0x00, 0x0F,\n  0xFF, 0xF0, 0x00, 0x07, 0xFF, 0xF8, 0x00, 0x03, 0xFD, 0xFC, 0x00, 0x01,\n  0xFC, 0xFE, 0x00, 0x01, 0xFE, 0x7F, 0x80, 0x00, 0xFF, 0x1F, 0xC0, 0x00,\n  0x7F, 0x0F, 0xE0, 0x00, 0x3F, 0x83, 0xF8, 0x00, 0x3F, 0x80, 0xFC, 0x00,\n  0x1F, 0x80, 0x3F, 0x00, 0x1F, 0x80, 0x0F, 0xC0, 0x1F, 0x80, 0x03, 0xF8,\n  0x3F, 0x80, 0x00, 0x7F, 0xFF, 0x00, 0x00, 0x07, 0xFC, 0x00, 0x00, 0xFF,\n  0xFF, 0xE0, 0x1F, 0xFF, 0xFF, 0x01, 0xFE, 0x1F, 0xE0, 0x7F, 0x81, 0xFC,\n  0x1F, 0xE0, 0x7F, 0x87, 0xF8, 0x0F, 0xE1, 0xFE, 0x03, 0xFC, 0x7F, 0x80,\n  0xFF, 0x1F, 0xE0, 0x3F, 0xC7, 0xF8, 0x0F, 0xF1, 0xFE, 0x03, 0xFC, 0x7F,\n  0x80, 0xFF, 0x1F, 0xE0, 0x3F, 0x87, 0xF8, 0x1F, 0xE1, 0xFE, 0x07, 0xF0,\n  0x7F, 0x87, 0xF8, 0x1F, 0xFF, 0xF8, 0x07, 0xFF, 0xF8, 0x01, 0xFE, 0x00,\n  0x00, 0x7F, 0x80, 0x00, 0x1F, 0xE0, 0x00, 0x07, 0xF8, 0x00, 0x01, 0xFE,\n  0x00, 0x00, 0x7F, 0x80, 0x00, 0x1F, 0xE0, 0x00, 0x07, 0xF8, 0x00, 0x01,\n  0xFE, 0x00, 0x00, 0x7F, 0x80, 0x00, 0x1F, 0xE0, 0x00, 0x07, 0xF8, 0x00,\n  0x03, 0xFF, 0x00, 0x03, 0xFF, 0xF0, 0x00, 0x00, 0x0F, 0xF8, 0x00, 0x00,\n  0x3F, 0xFF, 0x80, 0x00, 0x3F, 0x07, 0xE0, 0x00, 0x7E, 0x00, 0xFC, 0x00,\n  0x7E, 0x00, 0x3F, 0x00, 0x7E, 0x00, 0x1F, 0xC0, 0x7F, 0x00, 0x07, 0xF0,\n  0x3F, 0x00, 0x03, 0xF8, 0x3F, 0x80, 0x00, 0xFE, 0x1F, 0xC0, 0x00, 0x7F,\n  0x1F, 0xE0, 0x00, 0x3F, 0xCF, 0xE0, 0x00, 0x0F, 0xE7, 0xF0, 0x00, 0x07,\n  0xF7, 0xF8, 0x00, 0x03, 0xFF, 0xFC, 0x00, 0x01, 0xFF, 0xFE, 0x00, 0x00,\n  0xFF, 0xFF, 0x00, 0x00, 0x7F, 0xFF, 0x80, 0x00, 0x3F, 0xFF, 0xC0, 0x00,\n  0x1F, 0xFF, 0xE0, 0x00, 0x0F, 0xFF, 0xF0, 0x00, 0x07, 0xFF, 0xF8, 0x00,\n  0x03, 0xFD, 0xFC, 0x00, 0x01, 0xFC, 0xFE, 0x00, 0x01, 0xFE, 0x7F, 0x80,\n  0x00, 0xFF, 0x1F, 0xC0, 0x00, 0x7F, 0x0F, 0xE0, 0x00, 0x3F, 0x83, 0xF8,\n  0x00, 0x3F, 0x80, 0xFC, 0x00, 0x1F, 0x80, 0x3F, 0x00, 0x1F, 0x80, 0x0F,\n  0xC0, 0x1F, 0x80, 0x03, 0xF0, 0x1F, 0x00, 0x00, 0x3F, 0xFE, 0x00, 0x00,\n  0x0F, 0xFC, 0x00, 0x00, 0x03, 0xFF, 0x00, 0x00, 0x01, 0xFF, 0xC0, 0x00,\n  0x00, 0x7F, 0xF0, 0x00, 0x00, 0x1F, 0xFC, 0x00, 0x00, 0x07, 0xFF, 0x80,\n  0x00, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x0F, 0xF8, 0x00, 0xFF, 0xFF, 0xE0,\n  0x00, 0xFF, 0xFF, 0xF8, 0x00, 0x7F, 0xC3, 0xFC, 0x00, 0xFF, 0x01, 0xFC,\n  0x01, 0xFE, 0x03, 0xFC, 0x03, 0xFC, 0x03, 0xF8, 0x07, 0xF8, 0x07, 0xF8,\n  0x0F, 0xF0, 0x0F, 0xF0, 0x1F, 0xE0, 0x1F, 0xE0, 0x3F, 0xC0, 0x3F, 0xC0,\n  0x7F, 0x80, 0x7F, 0x80, 0xFF, 0x00, 0xFF, 0x01, 0xFE, 0x01, 0xFC, 0x03,\n  0xFC, 0x07, 0xF8, 0x07, 0xF8, 0x1F, 0xE0, 0x0F, 0xF0, 0xFF, 0x00, 0x1F,\n  0xFF, 0xF8, 0x00, 0x3F, 0xFF, 0xE0, 0x00, 0x7F, 0x9F, 0xE0, 0x00, 0xFF,\n  0x3F, 0xC0, 0x01, 0xFE, 0x3F, 0xC0, 0x03, 0xFC, 0x7F, 0xC0, 0x07, 0xF8,\n  0x7F, 0xC0, 0x0F, 0xF0, 0x7F, 0x80, 0x1F, 0xE0, 0xFF, 0x80, 0x3F, 0xC0,\n  0xFF, 0x80, 0x7F, 0x80, 0xFF, 0x00, 0xFF, 0x01, 0xFF, 0x01, 0xFE, 0x01,\n  0xFF, 0x03, 0xFC, 0x01, 0xFF, 0x0F, 0xFC, 0x03, 0xFE, 0x7F, 0xFE, 0x03,\n  0xFF, 0x03, 0xF8, 0x10, 0x7F, 0xF9, 0x87, 0xC1, 0xFC, 0x78, 0x03, 0xE7,\n  0x80, 0x0F, 0x3C, 0x00, 0x3B, 0xE0, 0x01, 0xDF, 0x00, 0x06, 0xF8, 0x00,\n  0x37, 0xE0, 0x00, 0xBF, 0x80, 0x01, 0xFF, 0x00, 0x0F, 0xFE, 0x00, 0x3F,\n  0xFC, 0x01, 0xFF, 0xF8, 0x07, 0xFF, 0xF0, 0x1F, 0xFF, 0xC0, 0x7F, 0xFF,\n  0x00, 0xFF, 0xFC, 0x01, 0xFF, 0xE0, 0x03, 0xFF, 0x80, 0x07, 0xFC, 0x00,\n  0x1F, 0xF0, 0x00, 0x3F, 0x80, 0x01, 0xFE, 0x00, 0x07, 0xF0, 0x00, 0x3F,\n  0xC0, 0x01, 0xEE, 0x00, 0x0F, 0x78, 0x00, 0xF3, 0xE0, 0x0F, 0x9F, 0xC0,\n  0xF8, 0x8F, 0xFF, 0x04, 0x0F, 0xE0, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFC, 0x3F, 0xC3, 0xFF, 0x03, 0xFC, 0x0F, 0xE0, 0x3F, 0xC0,\n  0x7C, 0x03, 0xFC, 0x03, 0xC0, 0x3F, 0xC0, 0x38, 0x03, 0xFC, 0x01, 0x80,\n  0x3F, 0xC0, 0x10, 0x03, 0xFC, 0x00, 0x00, 0x3F, 0xC0, 0x00, 0x03, 0xFC,\n  0x00, 0x00, 0x3F, 0xC0, 0x00, 0x03, 0xFC, 0x00, 0x00, 0x3F, 0xC0, 0x00,\n  0x03, 0xFC, 0x00, 0x00, 0x3F, 0xC0, 0x00, 0x03, 0xFC, 0x00, 0x00, 0x3F,\n  0xC0, 0x00, 0x03, 0xFC, 0x00, 0x00, 0x3F, 0xC0, 0x00, 0x03, 0xFC, 0x00,\n  0x00, 0x3F, 0xC0, 0x00, 0x03, 0xFC, 0x00, 0x00, 0x3F, 0xC0, 0x00, 0x03,\n  0xFC, 0x00, 0x00, 0x3F, 0xC0, 0x00, 0x03, 0xFC, 0x00, 0x00, 0x3F, 0xC0,\n  0x00, 0x03, 0xFC, 0x00, 0x00, 0x7F, 0xE0, 0x00, 0x3F, 0xFF, 0xC0, 0xFF,\n  0xFE, 0x07, 0xFC, 0xFF, 0xC0, 0x07, 0xC1, 0xFE, 0x00, 0x0E, 0x07, 0xF8,\n  0x00, 0x18, 0x1F, 0xE0, 0x00, 0x60, 0x7F, 0x80, 0x01, 0x81, 0xFE, 0x00,\n  0x06, 0x07, 0xF8, 0x00, 0x18, 0x1F, 0xE0, 0x00, 0x60, 0x7F, 0x80, 0x01,\n  0x81, 0xFE, 0x00, 0x06, 0x07, 0xF8, 0x00, 0x18, 0x1F, 0xE0, 0x00, 0x60,\n  0x7F, 0x80, 0x01, 0x81, 0xFE, 0x00, 0x06, 0x07, 0xF8, 0x00, 0x18, 0x1F,\n  0xE0, 0x00, 0x60, 0x7F, 0x80, 0x01, 0x81, 0xFE, 0x00, 0x06, 0x07, 0xF8,\n  0x00, 0x18, 0x1F, 0xE0, 0x00, 0x60, 0x7F, 0x80, 0x01, 0x81, 0xFE, 0x00,\n  0x06, 0x07, 0xF8, 0x00, 0x18, 0x1F, 0xE0, 0x00, 0x60, 0x7F, 0x80, 0x03,\n  0x00, 0xFF, 0x00, 0x0C, 0x03, 0xFC, 0x00, 0x30, 0x07, 0xF0, 0x01, 0x80,\n  0x0F, 0xE0, 0x0E, 0x00, 0x1F, 0xE0, 0xF0, 0x00, 0x1F, 0xFF, 0x00, 0x00,\n  0x1F, 0xF0, 0x00, 0xFF, 0xFF, 0x01, 0xFF, 0x9F, 0xFC, 0x00, 0x1F, 0x07,\n  0xFC, 0x00, 0x07, 0x01, 0xFE, 0x00, 0x03, 0x00, 0x7F, 0x80, 0x03, 0x80,\n  0x3F, 0xC0, 0x01, 0x80, 0x1F, 0xE0, 0x00, 0xC0, 0x07, 0xF8, 0x00, 0xC0,\n  0x03, 0xFC, 0x00, 0x60, 0x00, 0xFF, 0x00, 0x30, 0x00, 0x7F, 0x80, 0x30,\n  0x00, 0x1F, 0xE0, 0x18, 0x00, 0x0F, 0xF0, 0x18, 0x00, 0x07, 0xF8, 0x0C,\n  0x00, 0x01, 0xFE, 0x06, 0x00, 0x00, 0xFF, 0x06, 0x00, 0x00, 0x3F, 0xC3,\n  0x00, 0x00, 0x1F, 0xE3, 0x80, 0x00, 0x0F, 0xF1, 0x80, 0x00, 0x03, 0xFC,\n  0xC0, 0x00, 0x01, 0xFE, 0xC0, 0x00, 0x00, 0x7F, 0xE0, 0x00, 0x00, 0x3F,\n  0xF0, 0x00, 0x00, 0x0F, 0xF0, 0x00, 0x00, 0x07, 0xF8, 0x00, 0x00, 0x03,\n  0xF8, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00,\n  0x1E, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,\n  0x01, 0x80, 0x00, 0xFF, 0xF8, 0x7F, 0xFF, 0x0F, 0xFB, 0xFF, 0x00, 0xFF,\n  0xC0, 0x1F, 0x0F, 0xF0, 0x03, 0xFC, 0x00, 0x70, 0x3F, 0x80, 0x0F, 0xE0,\n  0x03, 0x81, 0xFE, 0x00, 0x7F, 0x80, 0x1C, 0x0F, 0xF0, 0x03, 0xFC, 0x00,\n  0xC0, 0x3F, 0x80, 0x0F, 0xE0, 0x06, 0x01, 0xFE, 0x00, 0x7F, 0x00, 0x70,\n  0x0F, 0xF0, 0x07, 0xFC, 0x03, 0x00, 0x3F, 0x80, 0x3F, 0xE0, 0x18, 0x01,\n  0xFE, 0x01, 0xFF, 0x01, 0xC0, 0x0F, 0xF0, 0x1B, 0xFC, 0x0C, 0x00, 0x3F,\n  0x80, 0xCF, 0xE0, 0x60, 0x01, 0xFE, 0x06, 0x7F, 0x07, 0x00, 0x0F, 0xF0,\n  0x63, 0xFC, 0x30, 0x00, 0x3F, 0x83, 0x0F, 0xE1, 0x80, 0x01, 0xFE, 0x30,\n  0x7F, 0x1C, 0x00, 0x07, 0xF1, 0x81, 0xFC, 0xC0, 0x00, 0x3F, 0x8C, 0x0F,\n  0xE6, 0x00, 0x01, 0xFE, 0xC0, 0x7F, 0x70, 0x00, 0x07, 0xF6, 0x01, 0xFB,\n  0x00, 0x00, 0x3F, 0xE0, 0x0F, 0xF8, 0x00, 0x01, 0xFF, 0x00, 0x7F, 0xC0,\n  0x00, 0x07, 0xF8, 0x01, 0xFC, 0x00, 0x00, 0x3F, 0x80, 0x0F, 0xE0, 0x00,\n  0x01, 0xFC, 0x00, 0x7F, 0x00, 0x00, 0x07, 0xE0, 0x01, 0xF0, 0x00, 0x00,\n  0x3E, 0x00, 0x0F, 0x80, 0x00, 0x01, 0xF0, 0x00, 0x7C, 0x00, 0x00, 0x07,\n  0x00, 0x01, 0xC0, 0x00, 0x00, 0x38, 0x00, 0x0E, 0x00, 0x00, 0x01, 0xC0,\n  0x00, 0x70, 0x00, 0x00, 0x04, 0x00, 0x01, 0x00, 0x00, 0xFF, 0xFF, 0x0F,\n  0xFF, 0x3F, 0xF8, 0x01, 0xF8, 0x1F, 0xF8, 0x01, 0xE0, 0x0F, 0xF8, 0x01,\n  0xC0, 0x0F, 0xF8, 0x01, 0x80, 0x07, 0xFC, 0x03, 0x80, 0x03, 0xFE, 0x07,\n  0x00, 0x03, 0xFE, 0x06, 0x00, 0x01, 0xFF, 0x0C, 0x00, 0x00, 0xFF, 0x9C,\n  0x00, 0x00, 0xFF, 0x98, 0x00, 0x00, 0x7F, 0xF0, 0x00, 0x00, 0x3F, 0xF0,\n  0x00, 0x00, 0x3F, 0xE0, 0x00, 0x00, 0x1F, 0xF0, 0x00, 0x00, 0x0F, 0xF0,\n  0x00, 0x00, 0x0F, 0xF8, 0x00, 0x00, 0x07, 0xFC, 0x00, 0x00, 0x0F, 0xFC,\n  0x00, 0x00, 0x0F, 0xFE, 0x00, 0x00, 0x19, 0xFE, 0x00, 0x00, 0x31, 0xFF,\n  0x00, 0x00, 0x70, 0xFF, 0x80, 0x00, 0x60, 0x7F, 0x80, 0x00, 0xC0, 0x7F,\n  0xC0, 0x01, 0xC0, 0x3F, 0xE0, 0x03, 0x80, 0x1F, 0xE0, 0x07, 0x00, 0x1F,\n  0xF0, 0x07, 0x00, 0x0F, 0xF8, 0x0F, 0x00, 0x0F, 0xF8, 0x3F, 0x80, 0x1F,\n  0xFC, 0xFF, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0xFF, 0x7F, 0xF0, 0x00,\n  0x7E, 0x1F, 0xF0, 0x00, 0x38, 0x1F, 0xF0, 0x00, 0x38, 0x0F, 0xF0, 0x00,\n  0x70, 0x0F, 0xF8, 0x00, 0x60, 0x07, 0xF8, 0x00, 0x60, 0x07, 0xFC, 0x00,\n  0xC0, 0x03, 0xFC, 0x01, 0xC0, 0x01, 0xFE, 0x01, 0x80, 0x01, 0xFE, 0x03,\n  0x00, 0x00, 0xFF, 0x03, 0x00, 0x00, 0xFF, 0x86, 0x00, 0x00, 0x7F, 0x8E,\n  0x00, 0x00, 0x7F, 0xCC, 0x00, 0x00, 0x3F, 0xD8, 0x00, 0x00, 0x3F, 0xF8,\n  0x00, 0x00, 0x1F, 0xF0, 0x00, 0x00, 0x1F, 0xF0, 0x00, 0x00, 0x0F, 0xF0,\n  0x00, 0x00, 0x0F, 0xF0, 0x00, 0x00, 0x0F, 0xF0, 0x00, 0x00, 0x0F, 0xF0,\n  0x00, 0x00, 0x0F, 0xF0, 0x00, 0x00, 0x0F, 0xF0, 0x00, 0x00, 0x0F, 0xF0,\n  0x00, 0x00, 0x0F, 0xF0, 0x00, 0x00, 0x0F, 0xF0, 0x00, 0x00, 0x0F, 0xF0,\n  0x00, 0x00, 0x0F, 0xF0, 0x00, 0x00, 0x1F, 0xF8, 0x00, 0x00, 0x7F, 0xFE,\n  0x00, 0x3F, 0xFF, 0xFF, 0xE3, 0xFF, 0xFF, 0xFC, 0x3F, 0x80, 0x7F, 0xC3,\n  0xE0, 0x07, 0xF8, 0x38, 0x00, 0xFF, 0x83, 0x80, 0x0F, 0xF0, 0x30, 0x01,\n  0xFE, 0x07, 0x00, 0x3F, 0xE0, 0x60, 0x03, 0xFC, 0x06, 0x00, 0x7F, 0xC0,\n  0x00, 0x0F, 0xF8, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x1F, 0xF0, 0x00, 0x01,\n  0xFE, 0x00, 0x00, 0x3F, 0xE0, 0x00, 0x07, 0xFC, 0x00, 0x00, 0x7F, 0x80,\n  0x00, 0x0F, 0xF8, 0x00, 0x01, 0xFF, 0x00, 0x00, 0x1F, 0xE0, 0x00, 0x03,\n  0xFE, 0x00, 0x00, 0x3F, 0xC0, 0x01, 0x07, 0xFC, 0x00, 0x30, 0xFF, 0x80,\n  0x03, 0x0F, 0xF0, 0x00, 0x31, 0xFF, 0x00, 0x07, 0x1F, 0xE0, 0x00, 0xF3,\n  0xFE, 0x00, 0x1E, 0x7F, 0xC0, 0x03, 0xE7, 0xF8, 0x01, 0xFE, 0xFF, 0xFF,\n  0xFF, 0xEF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xF0, 0x7C, 0x0F, 0x81,\n  0xF0, 0x3E, 0x07, 0xC0, 0xF8, 0x1F, 0x03, 0xE0, 0x7C, 0x0F, 0x81, 0xF0,\n  0x3E, 0x07, 0xC0, 0xF8, 0x1F, 0x03, 0xE0, 0x7C, 0x0F, 0x81, 0xF0, 0x3E,\n  0x07, 0xC0, 0xF8, 0x1F, 0x03, 0xE0, 0x7C, 0x0F, 0x81, 0xF0, 0x3E, 0x07,\n  0xC0, 0xF8, 0x1F, 0x03, 0xE0, 0x7C, 0x0F, 0x81, 0xFF, 0xFF, 0xF8, 0xF0,\n  0x01, 0xF0, 0x01, 0xE0, 0x03, 0xC0, 0x07, 0xC0, 0x07, 0x80, 0x0F, 0x00,\n  0x1F, 0x00, 0x1E, 0x00, 0x3C, 0x00, 0x7C, 0x00, 0x78, 0x00, 0xF0, 0x01,\n  0xF0, 0x01, 0xE0, 0x03, 0xC0, 0x07, 0xC0, 0x07, 0x80, 0x0F, 0x00, 0x1F,\n  0x00, 0x1E, 0x00, 0x3C, 0x00, 0x78, 0x00, 0x78, 0x00, 0xF0, 0x01, 0xE0,\n  0x01, 0xE0, 0x03, 0xC0, 0x07, 0x80, 0x07, 0x80, 0x0F, 0x00, 0x1E, 0x00,\n  0x1E, 0xFF, 0xFF, 0xFC, 0x1F, 0x81, 0xF0, 0x3E, 0x07, 0xC0, 0xF8, 0x1F,\n  0x03, 0xE0, 0x7C, 0x0F, 0x81, 0xF0, 0x3E, 0x07, 0xC0, 0xF8, 0x1F, 0x03,\n  0xE0, 0x7C, 0x0F, 0x81, 0xF0, 0x3E, 0x07, 0xC0, 0xF8, 0x1F, 0x03, 0xE0,\n  0x7C, 0x0F, 0x81, 0xF0, 0x3E, 0x07, 0xC0, 0xF8, 0x1F, 0x03, 0xE0, 0x7C,\n  0x0F, 0x81, 0xF0, 0x3F, 0xFF, 0xFF, 0xF8, 0x00, 0x78, 0x00, 0x07, 0xC0,\n  0x00, 0x3F, 0x00, 0x03, 0xF8, 0x00, 0x1F, 0xE0, 0x01, 0xEF, 0x00, 0x0F,\n  0x3C, 0x00, 0xF1, 0xE0, 0x07, 0x87, 0x80, 0x78, 0x3C, 0x03, 0xC0, 0xF0,\n  0x3C, 0x07, 0x81, 0xE0, 0x1E, 0x1E, 0x00, 0xF0, 0xF0, 0x07, 0xCF, 0x00,\n  0x1E, 0x78, 0x00, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0x70, 0x1F, 0x03, 0xF0, 0x7E, 0x03, 0xE0, 0x3E, 0x01, 0xE0, 0x1E,\n  0x00, 0xE0, 0x03, 0xFC, 0x00, 0x3F, 0xFC, 0x03, 0xE1, 0xF8, 0x0F, 0x03,\n  0xF0, 0x7C, 0x07, 0xC1, 0xF8, 0x1F, 0x87, 0xE0, 0x7E, 0x1F, 0x81, 0xF8,\n  0x3C, 0x07, 0xE0, 0x00, 0x1F, 0x80, 0x01, 0xFE, 0x00, 0x3F, 0xF8, 0x03,\n  0xE7, 0xE0, 0x3E, 0x1F, 0x83, 0xF0, 0x7E, 0x1F, 0x81, 0xF8, 0x7E, 0x07,\n  0xE3, 0xF8, 0x1F, 0x8F, 0xE0, 0x7E, 0x3F, 0x83, 0xF8, 0xFF, 0x1F, 0xE1,\n  0xFF, 0xDF, 0xF7, 0xFE, 0x3F, 0x07, 0xE0, 0xF8, 0xFF, 0x80, 0x00, 0x1F,\n  0xC0, 0x00, 0x07, 0xE0, 0x00, 0x03, 0xF0, 0x00, 0x01, 0xF8, 0x00, 0x00,\n  0xFC, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x1F, 0x80, 0x00,\n  0x0F, 0xC7, 0xF0, 0x07, 0xEF, 0xFE, 0x03, 0xFC, 0x3F, 0x81, 0xFC, 0x0F,\n  0xE0, 0xFC, 0x03, 0xF0, 0x7E, 0x01, 0xFC, 0x3F, 0x00, 0xFE, 0x1F, 0x80,\n  0x3F, 0x8F, 0xC0, 0x1F, 0xC7, 0xE0, 0x0F, 0xE3, 0xF0, 0x07, 0xF1, 0xF8,\n  0x03, 0xF8, 0xFC, 0x01, 0xFC, 0x7E, 0x00, 0xFE, 0x3F, 0x00, 0x7F, 0x1F,\n  0x80, 0x3F, 0x0F, 0xC0, 0x1F, 0x87, 0xE0, 0x1F, 0xC3, 0xF0, 0x0F, 0xC1,\n  0xF8, 0x07, 0xE0, 0xFE, 0x07, 0xE0, 0x73, 0x87, 0xE0, 0x30, 0xFF, 0xC0,\n  0x10, 0x1F, 0x80, 0x00, 0x00, 0xFC, 0x00, 0x7F, 0xE0, 0x3E, 0x3E, 0x0F,\n  0x83, 0xE3, 0xE0, 0x7C, 0x7C, 0x0F, 0x9F, 0x01, 0xF3, 0xE0, 0x1C, 0x7C,\n  0x00, 0x1F, 0x80, 0x03, 0xF0, 0x00, 0x7E, 0x00, 0x0F, 0xC0, 0x01, 0xF8,\n  0x00, 0x3F, 0x00, 0x07, 0xF0, 0x00, 0xFE, 0x00, 0x0F, 0xE0, 0x01, 0xFC,\n  0x00, 0x1F, 0xC0, 0x21, 0xFE, 0x0C, 0x3F, 0xFF, 0x01, 0xFF, 0x80, 0x0F,\n  0xC0, 0x00, 0x1F, 0xF8, 0x00, 0x03, 0xF8, 0x00, 0x01, 0xF8, 0x00, 0x01,\n  0xF8, 0x00, 0x01, 0xF8, 0x00, 0x01, 0xF8, 0x00, 0x01, 0xF8, 0x00, 0x01,\n  0xF8, 0x00, 0x01, 0xF8, 0x03, 0xF1, 0xF8, 0x07, 0xFD, 0xF8, 0x1F, 0xC7,\n  0xF8, 0x1F, 0x83, 0xF8, 0x3F, 0x01, 0xF8, 0x7F, 0x01, 0xF8, 0x7E, 0x01,\n  0xF8, 0x7E, 0x01, 0xF8, 0xFE, 0x01, 0xF8, 0xFE, 0x01, 0xF8, 0xFE, 0x01,\n  0xF8, 0xFE, 0x01, 0xF8, 0xFE, 0x01, 0xF8, 0xFE, 0x01, 0xF8, 0xFE, 0x01,\n  0xF8, 0xFE, 0x01, 0xF8, 0xFE, 0x01, 0xF8, 0x7E, 0x01, 0xF8, 0x7F, 0x01,\n  0xF8, 0x3F, 0x03, 0xF8, 0x3F, 0x03, 0xF8, 0x1F, 0x87, 0xFC, 0x0F, 0xFD,\n  0xFF, 0x03, 0xF1, 0xC0, 0x03, 0xF0, 0x03, 0xFF, 0x01, 0xE1, 0xE0, 0xF8,\n  0x7C, 0x3C, 0x0F, 0x1F, 0x03, 0xE7, 0xC0, 0xFB, 0xF0, 0x3E, 0xFC, 0x0F,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0x00, 0xFC, 0x00, 0x3F, 0x00, 0x0F,\n  0xC0, 0x03, 0xF8, 0x00, 0xFE, 0x00, 0x1F, 0x80, 0x07, 0xF0, 0x0C, 0xFC,\n  0x06, 0x3F, 0xC3, 0x07, 0xFF, 0x80, 0xFF, 0xC0, 0x0F, 0xC0, 0x00, 0xFC,\n  0x01, 0xFF, 0x81, 0xF1, 0xC1, 0xF0, 0xF0, 0xF8, 0xF8, 0xFC, 0x7C, 0x7E,\n  0x1C, 0x3F, 0x00, 0x1F, 0x80, 0x0F, 0xC0, 0x07, 0xE0, 0x1F, 0xFF, 0x0F,\n  0xFF, 0x80, 0xFC, 0x00, 0x7E, 0x00, 0x3F, 0x00, 0x1F, 0x80, 0x0F, 0xC0,\n  0x07, 0xE0, 0x03, 0xF0, 0x01, 0xF8, 0x00, 0xFC, 0x00, 0x7E, 0x00, 0x3F,\n  0x00, 0x1F, 0x80, 0x0F, 0xC0, 0x07, 0xE0, 0x03, 0xF0, 0x01, 0xF8, 0x00,\n  0xFC, 0x00, 0x7E, 0x00, 0x7F, 0x80, 0xFF, 0xF8, 0x00, 0x07, 0xF0, 0x03,\n  0xFF, 0xFC, 0xF8, 0x7F, 0xBE, 0x07, 0x87, 0xC0, 0xF9, 0xF8, 0x1F, 0xBF,\n  0x03, 0xF7, 0xE0, 0x7E, 0xFC, 0x0F, 0xDF, 0x81, 0xF9, 0xF0, 0x3F, 0x3E,\n  0x07, 0xC3, 0xE1, 0xF8, 0x3C, 0x7E, 0x01, 0xFF, 0x00, 0x60, 0x00, 0x38,\n  0x00, 0x0F, 0x00, 0x01, 0xF0, 0x00, 0x7F, 0xFF, 0x0F, 0xFF, 0xF9, 0xFF,\n  0xFF, 0x9F, 0xFF, 0xF9, 0xFF, 0xFF, 0x0F, 0xFF, 0xEF, 0x00, 0x3F, 0xC0,\n  0x03, 0xF8, 0x00, 0x7F, 0x00, 0x1C, 0xF8, 0x07, 0x0F, 0xFF, 0xC0, 0x7F,\n  0xC0, 0xFF, 0x80, 0x00, 0x3F, 0x80, 0x00, 0x1F, 0x80, 0x00, 0x1F, 0x80,\n  0x00, 0x1F, 0x80, 0x00, 0x1F, 0x80, 0x00, 0x1F, 0x80, 0x00, 0x1F, 0x80,\n  0x00, 0x1F, 0x80, 0x00, 0x1F, 0x87, 0xE0, 0x1F, 0x9F, 0xF0, 0x1F, 0xBF,\n  0xF8, 0x1F, 0xF1, 0xF8, 0x1F, 0xC0, 0xFC, 0x1F, 0x80, 0xFC, 0x1F, 0x80,\n  0xFC, 0x1F, 0x80, 0xFC, 0x1F, 0x80, 0xFC, 0x1F, 0x80, 0xFC, 0x1F, 0x80,\n  0xFC, 0x1F, 0x80, 0xFC, 0x1F, 0x80, 0xFC, 0x1F, 0x80, 0xFC, 0x1F, 0x80,\n  0xFC, 0x1F, 0x80, 0xFC, 0x1F, 0x80, 0xFC, 0x1F, 0x80, 0xFC, 0x1F, 0x80,\n  0xFC, 0x1F, 0x80, 0xFC, 0x1F, 0x80, 0xFC, 0x3F, 0xC1, 0xFE, 0xFF, 0xE3,\n  0xFF, 0x0F, 0x07, 0xE1, 0xFE, 0x3F, 0xC7, 0xF8, 0x7F, 0x03, 0xC0, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0x7F, 0xC3, 0xF8, 0x3F, 0x07, 0xE0, 0xFC, 0x1F,\n  0x83, 0xF0, 0x7E, 0x0F, 0xC1, 0xF8, 0x3F, 0x07, 0xE0, 0xFC, 0x1F, 0x83,\n  0xF0, 0x7E, 0x0F, 0xC1, 0xF8, 0x3F, 0x07, 0xE1, 0xFE, 0xFF, 0xE0, 0x00,\n  0x70, 0x07, 0xF0, 0x3F, 0xC0, 0xFF, 0x03, 0xFC, 0x07, 0xF0, 0x0F, 0x80,\n  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xFF, 0x01, 0xFC, 0x03, 0xF0,\n  0x0F, 0xC0, 0x3F, 0x00, 0xFC, 0x03, 0xF0, 0x0F, 0xC0, 0x3F, 0x00, 0xFC,\n  0x03, 0xF0, 0x0F, 0xC0, 0x3F, 0x00, 0xFC, 0x03, 0xF0, 0x0F, 0xC0, 0x3F,\n  0x00, 0xFC, 0x03, 0xF0, 0x0F, 0xC0, 0x3F, 0x00, 0xFC, 0x03, 0xF0, 0x0F,\n  0xDC, 0x3F, 0xF8, 0xFB, 0xE3, 0xEF, 0x0F, 0xBC, 0x7C, 0x7F, 0xE0, 0x7E,\n  0x00, 0xFF, 0x80, 0x00, 0x1F, 0xC0, 0x00, 0x07, 0xE0, 0x00, 0x03, 0xF0,\n  0x00, 0x01, 0xF8, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x3F,\n  0x00, 0x00, 0x1F, 0x80, 0x00, 0x0F, 0xC0, 0x00, 0x07, 0xE1, 0xFF, 0x83,\n  0xF0, 0x3F, 0x01, 0xF8, 0x0E, 0x00, 0xFC, 0x06, 0x00, 0x7E, 0x06, 0x00,\n  0x3F, 0x06, 0x00, 0x1F, 0x86, 0x00, 0x0F, 0xC7, 0x00, 0x07, 0xE7, 0x80,\n  0x03, 0xF7, 0xE0, 0x01, 0xFF, 0xF8, 0x00, 0xFF, 0xFC, 0x00, 0x7E, 0x7F,\n  0x00, 0x3F, 0x1F, 0xC0, 0x1F, 0x8F, 0xE0, 0x0F, 0xC3, 0xF8, 0x07, 0xE0,\n  0xFE, 0x03, 0xF0, 0x7F, 0x81, 0xF8, 0x1F, 0xC0, 0xFC, 0x0F, 0xF0, 0xFF,\n  0x07, 0xFD, 0xFF, 0xC7, 0xFF, 0xFF, 0x87, 0xF0, 0x7E, 0x0F, 0xC1, 0xF8,\n  0x3F, 0x07, 0xE0, 0xFC, 0x1F, 0x83, 0xF0, 0x7E, 0x0F, 0xC1, 0xF8, 0x3F,\n  0x07, 0xE0, 0xFC, 0x1F, 0x83, 0xF0, 0x7E, 0x0F, 0xC1, 0xF8, 0x3F, 0x07,\n  0xE0, 0xFC, 0x1F, 0x83, 0xF0, 0x7E, 0x0F, 0xC1, 0xF8, 0x3F, 0x0F, 0xF7,\n  0xFF, 0x00, 0x07, 0xE0, 0x3F, 0x07, 0xFC, 0xFF, 0x87, 0xFC, 0x0F, 0xEF,\n  0xFE, 0x7F, 0xF0, 0x3F, 0xC3, 0xFF, 0x1F, 0x81, 0xFC, 0x0F, 0xE0, 0x7E,\n  0x0F, 0xC0, 0x7E, 0x03, 0xF0, 0x7E, 0x03, 0xF0, 0x1F, 0x83, 0xF0, 0x1F,\n  0x80, 0xFC, 0x1F, 0x80, 0xFC, 0x07, 0xE0, 0xFC, 0x07, 0xE0, 0x3F, 0x07,\n  0xE0, 0x3F, 0x01, 0xF8, 0x3F, 0x01, 0xF8, 0x0F, 0xC1, 0xF8, 0x0F, 0xC0,\n  0x7E, 0x0F, 0xC0, 0x7E, 0x03, 0xF0, 0x7E, 0x03, 0xF0, 0x1F, 0x83, 0xF0,\n  0x1F, 0x80, 0xFC, 0x1F, 0x80, 0xFC, 0x07, 0xE0, 0xFC, 0x07, 0xE0, 0x3F,\n  0x07, 0xE0, 0x3F, 0x01, 0xF8, 0x3F, 0x01, 0xF8, 0x0F, 0xC1, 0xF8, 0x0F,\n  0xC0, 0x7E, 0x1F, 0xE0, 0xFF, 0x07, 0xFB, 0xFF, 0x8F, 0xFC, 0x7F, 0xE0,\n  0x00, 0x07, 0xE0, 0xFF, 0x9F, 0xF0, 0x3F, 0xBF, 0xF8, 0x1F, 0xF1, 0xF8,\n  0x1F, 0xC0, 0xFC, 0x1F, 0x80, 0xFC, 0x1F, 0x80, 0xFC, 0x1F, 0x80, 0xFC,\n  0x1F, 0x80, 0xFC, 0x1F, 0x80, 0xFC, 0x1F, 0x80, 0xFC, 0x1F, 0x80, 0xFC,\n  0x1F, 0x80, 0xFC, 0x1F, 0x80, 0xFC, 0x1F, 0x80, 0xFC, 0x1F, 0x80, 0xFC,\n  0x1F, 0x80, 0xFC, 0x1F, 0x80, 0xFC, 0x1F, 0x80, 0xFC, 0x1F, 0x80, 0xFC,\n  0x1F, 0x80, 0xFC, 0x3F, 0xC1, 0xFE, 0xFF, 0xE3, 0xFF, 0x01, 0xFC, 0x00,\n  0x3F, 0xF8, 0x03, 0xE3, 0xE0, 0x3E, 0x0F, 0x83, 0xF0, 0x7E, 0x1F, 0x01,\n  0xF1, 0xF8, 0x0F, 0xCF, 0xC0, 0x7E, 0xFE, 0x03, 0xFF, 0xF0, 0x1F, 0xFF,\n  0x80, 0xFF, 0xFC, 0x07, 0xFF, 0xE0, 0x3F, 0xFF, 0x01, 0xFF, 0xF8, 0x0F,\n  0xFF, 0xC0, 0x7F, 0x7E, 0x03, 0xF3, 0xF0, 0x1F, 0x8F, 0x80, 0xF8, 0x7E,\n  0x0F, 0xC1, 0xF0, 0x7C, 0x07, 0xC7, 0xC0, 0x1F, 0xFC, 0x00, 0x3F, 0x80,\n  0x00, 0x0F, 0xC0, 0xFF, 0xBF, 0xF0, 0x3F, 0xF1, 0xF8, 0x1F, 0xC0, 0xFC,\n  0x1F, 0xC0, 0xFC, 0x1F, 0x80, 0xFE, 0x1F, 0x80, 0x7E, 0x1F, 0x80, 0x7F,\n  0x1F, 0x80, 0x7F, 0x1F, 0x80, 0x7F, 0x1F, 0x80, 0x7F, 0x1F, 0x80, 0x7F,\n  0x1F, 0x80, 0x7F, 0x1F, 0x80, 0x7F, 0x1F, 0x80, 0x7F, 0x1F, 0x80, 0x7F,\n  0x1F, 0x80, 0x7E, 0x1F, 0x80, 0x7E, 0x1F, 0x80, 0xFE, 0x1F, 0x80, 0xFC,\n  0x1F, 0xC1, 0xF8, 0x1F, 0xE3, 0xF8, 0x1F, 0xBF, 0xE0, 0x1F, 0x8F, 0xC0,\n  0x1F, 0x80, 0x00, 0x1F, 0x80, 0x00, 0x1F, 0x80, 0x00, 0x1F, 0x80, 0x00,\n  0x1F, 0x80, 0x00, 0x1F, 0x80, 0x00, 0x3F, 0xC0, 0x00, 0xFF, 0xF8, 0x00,\n  0x00, 0xF8, 0x08, 0x07, 0xFE, 0x18, 0x0F, 0xC7, 0x38, 0x1F, 0x83, 0xF8,\n  0x3F, 0x01, 0xF8, 0x3F, 0x01, 0xF8, 0x7F, 0x01, 0xF8, 0x7E, 0x01, 0xF8,\n  0x7E, 0x01, 0xF8, 0xFE, 0x01, 0xF8, 0xFE, 0x01, 0xF8, 0xFE, 0x01, 0xF8,\n  0xFE, 0x01, 0xF8, 0xFE, 0x01, 0xF8, 0xFE, 0x01, 0xF8, 0xFE, 0x01, 0xF8,\n  0xFE, 0x01, 0xF8, 0x7E, 0x01, 0xF8, 0x7F, 0x01, 0xF8, 0x7F, 0x01, 0xF8,\n  0x3F, 0x83, 0xF8, 0x1F, 0xC7, 0xF8, 0x0F, 0xFD, 0xF8, 0x03, 0xF1, 0xF8,\n  0x00, 0x01, 0xF8, 0x00, 0x01, 0xF8, 0x00, 0x01, 0xF8, 0x00, 0x01, 0xF8,\n  0x00, 0x01, 0xF8, 0x00, 0x01, 0xF8, 0x00, 0x03, 0xFC, 0x00, 0x0F, 0xFF,\n  0x00, 0x07, 0x9F, 0xF3, 0xF8, 0xFE, 0xFF, 0x8F, 0xFF, 0xF1, 0xFE, 0x7E,\n  0x3F, 0x87, 0x87, 0xE0, 0x00, 0xFC, 0x00, 0x1F, 0x80, 0x03, 0xF0, 0x00,\n  0x7E, 0x00, 0x0F, 0xC0, 0x01, 0xF8, 0x00, 0x3F, 0x00, 0x07, 0xE0, 0x00,\n  0xFC, 0x00, 0x1F, 0x80, 0x03, 0xF0, 0x00, 0x7E, 0x00, 0x0F, 0xC0, 0x01,\n  0xF8, 0x00, 0x7F, 0x80, 0x3F, 0xFC, 0x00, 0x0F, 0x84, 0x3F, 0xF8, 0xE1,\n  0xF3, 0x80, 0xEF, 0x00, 0xDE, 0x01, 0xBE, 0x01, 0x7E, 0x00, 0xFF, 0x01,\n  0xFF, 0x81, 0xFF, 0xC3, 0xFF, 0xC3, 0xFF, 0xC1, 0xFF, 0x80, 0xFF, 0x80,\n  0x7F, 0x80, 0x7F, 0x80, 0x7F, 0x00, 0x7E, 0x00, 0xFE, 0x01, 0xDF, 0x0F,\n  0x37, 0xFC, 0x43, 0xF0, 0x01, 0x00, 0x0C, 0x00, 0x70, 0x01, 0xC0, 0x0F,\n  0x00, 0x7C, 0x03, 0xF0, 0x1F, 0xC0, 0xFF, 0xF3, 0xFF, 0xC3, 0xF0, 0x0F,\n  0xC0, 0x3F, 0x00, 0xFC, 0x03, 0xF0, 0x0F, 0xC0, 0x3F, 0x00, 0xFC, 0x03,\n  0xF0, 0x0F, 0xC0, 0x3F, 0x00, 0xFC, 0x03, 0xF0, 0x0F, 0xC0, 0x3F, 0x00,\n  0xFC, 0x23, 0xF0, 0x8F, 0xE6, 0x1F, 0xF0, 0x7F, 0x80, 0xF8, 0x00, 0xFF,\n  0x87, 0xFC, 0x1F, 0xC0, 0xFE, 0x07, 0xE0, 0x3F, 0x03, 0xF0, 0x1F, 0x81,\n  0xF8, 0x0F, 0xC0, 0xFC, 0x07, 0xE0, 0x7E, 0x03, 0xF0, 0x3F, 0x01, 0xF8,\n  0x1F, 0x80, 0xFC, 0x0F, 0xC0, 0x7E, 0x07, 0xE0, 0x3F, 0x03, 0xF0, 0x1F,\n  0x81, 0xF8, 0x0F, 0xC0, 0xFC, 0x07, 0xE0, 0x7E, 0x03, 0xF0, 0x3F, 0x01,\n  0xF8, 0x1F, 0x80, 0xFC, 0x0F, 0xC0, 0x7E, 0x07, 0xE0, 0x7F, 0x03, 0xF8,\n  0x7F, 0xC0, 0xFF, 0xEF, 0xF8, 0x3F, 0xE7, 0xC0, 0x0F, 0xC2, 0x00, 0xFF,\n  0xF1, 0xFC, 0xFF, 0x01, 0xE3, 0xFC, 0x03, 0x07, 0xF0, 0x0C, 0x1F, 0xC0,\n  0x60, 0x3F, 0x81, 0x80, 0xFE, 0x04, 0x01, 0xF8, 0x30, 0x07, 0xF0, 0xC0,\n  0x1F, 0xC6, 0x00, 0x3F, 0x98, 0x00, 0xFE, 0x40, 0x01, 0xFB, 0x00, 0x07,\n  0xFC, 0x00, 0x1F, 0xE0, 0x00, 0x3F, 0x80, 0x00, 0xFE, 0x00, 0x01, 0xF0,\n  0x00, 0x07, 0xC0, 0x00, 0x1E, 0x00, 0x00, 0x38, 0x00, 0x00, 0xE0, 0x00,\n  0x01, 0x00, 0x00, 0xFF, 0xE7, 0xFF, 0x3F, 0xBF, 0xE0, 0xFE, 0x07, 0x0F,\n  0xE0, 0x7F, 0x03, 0x83, 0xF0, 0x1F, 0x81, 0x81, 0xFC, 0x0F, 0xC0, 0xC0,\n  0xFE, 0x07, 0xF0, 0x40, 0x3F, 0x03, 0xF8, 0x60, 0x1F, 0xC3, 0xFC, 0x30,\n  0x07, 0xE1, 0xFE, 0x10, 0x03, 0xF0, 0x9F, 0x98, 0x01, 0xFC, 0xCF, 0xCC,\n  0x00, 0x7E, 0x67, 0xEC, 0x00, 0x3F, 0xE1, 0xFE, 0x00, 0x1F, 0xF0, 0xFE,\n  0x00, 0x07, 0xF0, 0x7F, 0x00, 0x03, 0xF8, 0x3F, 0x80, 0x00, 0xFC, 0x0F,\n  0x80, 0x00, 0x7C, 0x07, 0xC0, 0x00, 0x3E, 0x03, 0xE0, 0x00, 0x0F, 0x00,\n  0xE0, 0x00, 0x07, 0x00, 0x70, 0x00, 0x03, 0x80, 0x38, 0x00, 0x00, 0x80,\n  0x08, 0x00, 0xFF, 0xF3, 0xFD, 0xFF, 0x03, 0xC3, 0xFC, 0x0E, 0x07, 0xF0,\n  0x30, 0x1F, 0xE1, 0x80, 0x3F, 0x8C, 0x00, 0x7F, 0x70, 0x01, 0xFF, 0x80,\n  0x03, 0xFC, 0x00, 0x0F, 0xF0, 0x00, 0x1F, 0xE0, 0x00, 0x3F, 0x80, 0x00,\n  0xFF, 0x00, 0x07, 0xFE, 0x00, 0x1B, 0xF8, 0x00, 0xCF, 0xF0, 0x06, 0x1F,\n  0xC0, 0x38, 0x3F, 0x80, 0xC0, 0xFF, 0x07, 0x01, 0xFC, 0x3C, 0x07, 0xFB,\n  0xFC, 0x7F, 0xF0, 0xFF, 0xE3, 0xFB, 0xFC, 0x07, 0x8F, 0xE0, 0x18, 0x7F,\n  0x01, 0x81, 0xF8, 0x0C, 0x0F, 0xE0, 0x60, 0x7F, 0x06, 0x01, 0xF8, 0x30,\n  0x0F, 0xE1, 0x80, 0x7F, 0x18, 0x01, 0xF8, 0xC0, 0x0F, 0xE6, 0x00, 0x3F,\n  0x60, 0x01, 0xFF, 0x00, 0x0F, 0xF0, 0x00, 0x3F, 0x80, 0x01, 0xFC, 0x00,\n  0x07, 0xC0, 0x00, 0x3E, 0x00, 0x01, 0xF0, 0x00, 0x07, 0x00, 0x00, 0x38,\n  0x00, 0x00, 0x80, 0x00, 0x0C, 0x00, 0x00, 0x60, 0x03, 0x82, 0x00, 0x3E,\n  0x30, 0x01, 0xF1, 0x00, 0x0F, 0x98, 0x00, 0x3F, 0x80, 0x00, 0xF0, 0x00,\n  0x00, 0x7F, 0xFF, 0xEF, 0xFF, 0xFD, 0xE0, 0x7F, 0x30, 0x1F, 0xC6, 0x07,\n  0xF8, 0x80, 0xFE, 0x00, 0x3F, 0xC0, 0x07, 0xF0, 0x01, 0xFC, 0x00, 0x3F,\n  0x80, 0x0F, 0xE0, 0x03, 0xFC, 0x00, 0x7F, 0x00, 0x1F, 0xE0, 0x03, 0xF8,\n  0x00, 0xFE, 0x03, 0x3F, 0xC0, 0x67, 0xF0, 0x19, 0xFE, 0x07, 0x3F, 0x83,\n  0xEF, 0xFF, 0xFD, 0xFF, 0xFF, 0x80, 0x00, 0x7C, 0x07, 0xE0, 0x3E, 0x00,\n  0xF8, 0x07, 0xC0, 0x1F, 0x00, 0x7C, 0x01, 0xF0, 0x07, 0xC0, 0x1F, 0x00,\n  0x7C, 0x01, 0xF0, 0x07, 0xC0, 0x1F, 0x00, 0x7C, 0x01, 0xF0, 0x07, 0xC0,\n  0x1F, 0x00, 0xF8, 0x03, 0xC0, 0x3C, 0x01, 0xF0, 0x00, 0xF0, 0x03, 0xE0,\n  0x07, 0xC0, 0x1F, 0x00, 0x7C, 0x01, 0xF0, 0x07, 0xC0, 0x1F, 0x00, 0x7C,\n  0x01, 0xF0, 0x07, 0xC0, 0x1F, 0x00, 0x7C, 0x01, 0xF0, 0x07, 0xC0, 0x1F,\n  0x00, 0x3E, 0x00, 0xF8, 0x01, 0xF8, 0x01, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xF0, 0xF8, 0x01, 0xF8, 0x01, 0xF0, 0x07, 0xC0, 0x0F, 0x80, 0x3E, 0x00,\n  0xF8, 0x03, 0xE0, 0x0F, 0x80, 0x3E, 0x00, 0xF8, 0x03, 0xE0, 0x0F, 0x80,\n  0x3E, 0x00, 0xF8, 0x03, 0xE0, 0x0F, 0x80, 0x3E, 0x00, 0x7C, 0x00, 0xF0,\n  0x00, 0xF0, 0x03, 0xE0, 0x3C, 0x01, 0xF0, 0x0F, 0x80, 0x3E, 0x00, 0xF8,\n  0x03, 0xE0, 0x0F, 0x80, 0x3E, 0x00, 0xF8, 0x03, 0xE0, 0x0F, 0x80, 0x3E,\n  0x00, 0xF8, 0x03, 0xE0, 0x0F, 0x80, 0x3E, 0x01, 0xF0, 0x07, 0xC0, 0x7E,\n  0x03, 0xE0, 0x00, 0x0F, 0x80, 0x00, 0xFF, 0xC0, 0x47, 0xFF, 0xC3, 0x9F,\n  0xFF, 0xFF, 0x70, 0x7F, 0xF8, 0x80, 0x7F, 0xC0, 0x00, 0x3E, 0x00 };\n\nconst GFXglyph FreeSerifBold24pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,  12,    0,    1 },   // 0x20 ' '\n  {     0,   8,  34,  16,    4,  -32 },   // 0x21 '!'\n  {    34,  17,  13,  26,    4,  -32 },   // 0x22 '\"'\n  {    62,  23,  33,  23,    0,  -32 },   // 0x23 '#'\n  {   157,  21,  39,  24,    1,  -34 },   // 0x24 '$'\n  {   260,  35,  34,  47,    6,  -32 },   // 0x25 '%'\n  {   409,  34,  34,  39,    3,  -32 },   // 0x26 '&'\n  {   554,   5,  13,  13,    4,  -32 },   // 0x27 '''\n  {   563,  12,  41,  16,    2,  -32 },   // 0x28 '('\n  {   625,  12,  41,  16,    1,  -32 },   // 0x29 ')'\n  {   687,  18,  21,  24,    3,  -32 },   // 0x2A '*'\n  {   735,  26,  25,  32,    3,  -24 },   // 0x2B '+'\n  {   817,   8,  15,  12,    2,   -6 },   // 0x2C ','\n  {   832,  11,   5,  16,    2,  -12 },   // 0x2D '-'\n  {   839,   8,   8,  12,    2,   -6 },   // 0x2E '.'\n  {   847,  15,  33,  13,   -1,  -32 },   // 0x2F '/'\n  {   909,  22,  34,  23,    1,  -32 },   // 0x30 '0'\n  {  1003,  18,  33,  23,    3,  -32 },   // 0x31 '1'\n  {  1078,  21,  33,  24,    1,  -32 },   // 0x32 '2'\n  {  1165,  21,  34,  24,    1,  -32 },   // 0x33 '3'\n  {  1255,  21,  33,  24,    1,  -32 },   // 0x34 '4'\n  {  1342,  20,  32,  23,    2,  -31 },   // 0x35 '5'\n  {  1422,  21,  34,  24,    1,  -32 },   // 0x36 '6'\n  {  1512,  21,  32,  23,    1,  -31 },   // 0x37 '7'\n  {  1596,  21,  34,  23,    1,  -32 },   // 0x38 '8'\n  {  1686,  22,  34,  23,    1,  -32 },   // 0x39 '9'\n  {  1780,   8,  24,  16,    4,  -22 },   // 0x3A ':'\n  {  1804,   9,  31,  16,    3,  -22 },   // 0x3B ';'\n  {  1839,  26,  26,  32,    3,  -24 },   // 0x3C '<'\n  {  1924,  26,  17,  32,    3,  -20 },   // 0x3D '='\n  {  1980,  26,  26,  32,    3,  -24 },   // 0x3E '>'\n  {  2065,  18,  34,  24,    3,  -32 },   // 0x3F '?'\n  {  2142,  33,  34,  44,    5,  -32 },   // 0x40 '@'\n  {  2283,  32,  33,  34,    1,  -32 },   // 0x41 'A'\n  {  2415,  28,  32,  31,    1,  -31 },   // 0x42 'B'\n  {  2527,  30,  34,  33,    2,  -32 },   // 0x43 'C'\n  {  2655,  32,  32,  34,    1,  -31 },   // 0x44 'D'\n  {  2783,  28,  32,  32,    2,  -31 },   // 0x45 'E'\n  {  2895,  25,  32,  29,    2,  -31 },   // 0x46 'F'\n  {  2995,  33,  34,  36,    2,  -32 },   // 0x47 'G'\n  {  3136,  33,  32,  37,    2,  -31 },   // 0x48 'H'\n  {  3268,  15,  32,  18,    2,  -31 },   // 0x49 'I'\n  {  3328,  22,  37,  24,    0,  -31 },   // 0x4A 'J'\n  {  3430,  34,  32,  36,    2,  -31 },   // 0x4B 'K'\n  {  3566,  28,  32,  31,    2,  -31 },   // 0x4C 'L'\n  {  3678,  43,  32,  45,    0,  -31 },   // 0x4D 'M'\n  {  3850,  31,  32,  34,    1,  -31 },   // 0x4E 'N'\n  {  3974,  33,  34,  37,    2,  -32 },   // 0x4F 'O'\n  {  4115,  26,  32,  30,    2,  -31 },   // 0x50 'P'\n  {  4219,  33,  41,  37,    2,  -32 },   // 0x51 'Q'\n  {  4389,  31,  32,  34,    2,  -31 },   // 0x52 'R'\n  {  4513,  21,  34,  27,    3,  -32 },   // 0x53 'S'\n  {  4603,  28,  32,  30,    1,  -31 },   // 0x54 'T'\n  {  4715,  30,  33,  34,    2,  -31 },   // 0x55 'U'\n  {  4839,  33,  32,  33,    0,  -31 },   // 0x56 'V'\n  {  4971,  45,  33,  46,    1,  -31 },   // 0x57 'W'\n  {  5157,  32,  32,  34,    1,  -31 },   // 0x58 'X'\n  {  5285,  32,  32,  33,    1,  -31 },   // 0x59 'Y'\n  {  5413,  28,  32,  30,    1,  -31 },   // 0x5A 'Z'\n  {  5525,  11,  39,  16,    3,  -31 },   // 0x5B '['\n  {  5579,  15,  33,  13,   -1,  -32 },   // 0x5C '\\'\n  {  5641,  11,  39,  16,    2,  -31 },   // 0x5D ']'\n  {  5695,  21,  17,  27,    3,  -31 },   // 0x5E '^'\n  {  5740,  24,   3,  23,    0,    5 },   // 0x5F '_'\n  {  5749,  11,   9,  16,    0,  -33 },   // 0x60 '`'\n  {  5762,  22,  24,  23,    1,  -22 },   // 0x61 'a'\n  {  5828,  25,  33,  26,    0,  -31 },   // 0x62 'b'\n  {  5932,  19,  24,  20,    1,  -22 },   // 0x63 'c'\n  {  5989,  24,  33,  26,    1,  -31 },   // 0x64 'd'\n  {  6088,  18,  24,  21,    1,  -22 },   // 0x65 'e'\n  {  6142,  17,  33,  18,    1,  -32 },   // 0x66 'f'\n  {  6213,  19,  32,  24,    2,  -22 },   // 0x67 'g'\n  {  6289,  24,  32,  26,    0,  -31 },   // 0x68 'h'\n  {  6385,  11,  33,  14,    1,  -32 },   // 0x69 'i'\n  {  6431,  14,  42,  18,    0,  -32 },   // 0x6A 'j'\n  {  6505,  25,  32,  26,    0,  -31 },   // 0x6B 'k'\n  {  6605,  11,  32,  13,    0,  -31 },   // 0x6C 'l'\n  {  6649,  37,  23,  39,    0,  -22 },   // 0x6D 'm'\n  {  6756,  24,  23,  26,    0,  -22 },   // 0x6E 'n'\n  {  6825,  21,  24,  24,    1,  -22 },   // 0x6F 'o'\n  {  6888,  24,  32,  26,    0,  -22 },   // 0x70 'p'\n  {  6984,  24,  32,  26,    1,  -22 },   // 0x71 'q'\n  {  7080,  19,  23,  20,    0,  -22 },   // 0x72 'r'\n  {  7135,  15,  24,  19,    2,  -22 },   // 0x73 's'\n  {  7180,  14,  31,  16,    1,  -29 },   // 0x74 't'\n  {  7235,  25,  23,  27,    0,  -21 },   // 0x75 'u'\n  {  7307,  22,  23,  23,    0,  -21 },   // 0x76 'v'\n  {  7371,  33,  23,  33,    0,  -21 },   // 0x77 'w'\n  {  7466,  22,  22,  24,    1,  -21 },   // 0x78 'x'\n  {  7527,  21,  31,  23,    0,  -21 },   // 0x79 'y'\n  {  7609,  19,  22,  21,    1,  -21 },   // 0x7A 'z'\n  {  7662,  14,  42,  19,    1,  -33 },   // 0x7B '{'\n  {  7736,   4,  33,  10,    3,  -32 },   // 0x7C '|'\n  {  7753,  14,  42,  19,    4,  -33 },   // 0x7D '}'\n  {  7827,  22,   7,  24,    1,  -14 } }; // 0x7E '~'\n\nconst GFXfont FreeSerifBold24pt7b PROGMEM = {\n  (uint8_t  *)FreeSerifBold24pt7bBitmaps,\n  (GFXglyph *)FreeSerifBold24pt7bGlyphs,\n  0x20, 0x7E, 56 };\n\n// Approx. 8519 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeSerifBold9pt7b.h",
    "content": "const uint8_t FreeSerifBold9pt7bBitmaps[] PROGMEM = {\n  0xFF, 0xF4, 0x92, 0x1F, 0xF0, 0xCF, 0x3C, 0xE3, 0x88, 0x13, 0x09, 0x84,\n  0xC2, 0x47, 0xF9, 0x90, 0xC8, 0x4C, 0xFF, 0x13, 0x09, 0x0C, 0x86, 0x40,\n  0x10, 0x38, 0xD6, 0x92, 0xD2, 0xF0, 0x7C, 0x3E, 0x17, 0x93, 0x93, 0xD6,\n  0x7C, 0x10, 0x3C, 0x21, 0xCF, 0x0E, 0x24, 0x30, 0xA0, 0xC5, 0x03, 0x34,\n  0xE7, 0x26, 0x40, 0xB9, 0x04, 0xC4, 0x23, 0x30, 0x8C, 0x84, 0x1C, 0x0F,\n  0x00, 0xCC, 0x06, 0x60, 0x3E, 0x00, 0xE7, 0x8F, 0x18, 0x9C, 0x8C, 0xE4,\n  0xE3, 0xC7, 0x9E, 0x3C, 0x72, 0xFD, 0xE0, 0xFF, 0x80, 0x32, 0x44, 0xCC,\n  0xCC, 0xCC, 0xC4, 0x62, 0x10, 0x84, 0x22, 0x33, 0x33, 0x33, 0x32, 0x64,\n  0x80, 0x31, 0x6B, 0xB1, 0x8E, 0xD6, 0x8C, 0x00, 0x08, 0x04, 0x02, 0x01,\n  0x0F, 0xF8, 0x40, 0x20, 0x10, 0x08, 0x00, 0xDF, 0x95, 0x00, 0xFF, 0xFF,\n  0x80, 0x0C, 0x21, 0x86, 0x10, 0xC3, 0x08, 0x61, 0x84, 0x30, 0xC0, 0x1C,\n  0x33, 0x98, 0xDC, 0x7E, 0x3F, 0x1F, 0x8F, 0xC7, 0xE3, 0xB1, 0x98, 0xC3,\n  0x80, 0x08, 0xE3, 0x8E, 0x38, 0xE3, 0x8E, 0x38, 0xE3, 0xBF, 0x3C, 0x3F,\n  0x23, 0xC0, 0xE0, 0x70, 0x30, 0x38, 0x18, 0x18, 0x18, 0x5F, 0xDF, 0xE0,\n  0x7C, 0x8E, 0x0E, 0x0E, 0x0C, 0x1E, 0x07, 0x03, 0x03, 0x02, 0xE6, 0xF8,\n  0x06, 0x0E, 0x0E, 0x3E, 0x2E, 0x4E, 0x8E, 0x8E, 0xFF, 0xFF, 0x0E, 0x0E,\n  0x3F, 0x7E, 0x40, 0x40, 0xF8, 0xFC, 0x1E, 0x06, 0x02, 0x02, 0xE4, 0xF8,\n  0x07, 0x1C, 0x30, 0x70, 0xFC, 0xE6, 0xE7, 0xE7, 0xE7, 0x67, 0x66, 0x3C,\n  0x7F, 0x3F, 0xA0, 0xD0, 0x40, 0x60, 0x30, 0x10, 0x18, 0x0C, 0x04, 0x06,\n  0x03, 0x00, 0x3C, 0xC6, 0xC6, 0xC6, 0xFC, 0x7C, 0x3E, 0xCF, 0xC7, 0xC7,\n  0xC6, 0x7C, 0x3E, 0x33, 0xB8, 0xDC, 0x7E, 0x3F, 0x1D, 0xCE, 0x7F, 0x07,\n  0x07, 0x0F, 0x1C, 0x00, 0xFF, 0x80, 0x3F, 0xE0, 0xFF, 0x80, 0x37, 0xE5,\n  0x40, 0x00, 0x00, 0x70, 0x78, 0x78, 0x78, 0x38, 0x03, 0x80, 0x3C, 0x03,\n  0xC0, 0x30, 0xFF, 0xC0, 0x00, 0x00, 0x00, 0xFF, 0xC0, 0xC0, 0x3C, 0x03,\n  0xC0, 0x1C, 0x01, 0xC1, 0xE1, 0xE1, 0xE0, 0xE0, 0x00, 0x00, 0x3D, 0x9F,\n  0x3E, 0x70, 0xE1, 0x04, 0x08, 0x00, 0x70, 0xE1, 0xC0, 0x0F, 0x81, 0x83,\n  0x18, 0xC4, 0x89, 0x9C, 0x4C, 0xE4, 0x67, 0x22, 0x39, 0x22, 0x4F, 0xE3,\n  0x00, 0x0C, 0x10, 0x1F, 0x00, 0x02, 0x00, 0x30, 0x01, 0xC0, 0x0E, 0x00,\n  0xB8, 0x05, 0xC0, 0x4F, 0x02, 0x38, 0x3F, 0xE1, 0x07, 0x18, 0x3D, 0xE3,\n  0xF0, 0xFF, 0x87, 0x1C, 0xE3, 0x9C, 0x73, 0x9C, 0x7F, 0x0E, 0x71, 0xC7,\n  0x38, 0xE7, 0x1C, 0xE7, 0x7F, 0xC0, 0x1F, 0x26, 0x1D, 0xC1, 0xB0, 0x1E,\n  0x01, 0xC0, 0x38, 0x07, 0x00, 0xE0, 0x0E, 0x04, 0xE1, 0x0F, 0xC0, 0xFF,\n  0x0E, 0x71, 0xC7, 0x38, 0x77, 0x0E, 0xE1, 0xDC, 0x3B, 0x87, 0x70, 0xCE,\n  0x39, 0xC6, 0x7F, 0x80, 0xFF, 0xCE, 0x19, 0xC1, 0x38, 0x87, 0x30, 0xFE,\n  0x1C, 0xC3, 0x88, 0x70, 0x2E, 0x0D, 0xC3, 0x7F, 0xE0, 0xFF, 0xDC, 0x37,\n  0x05, 0xC4, 0x73, 0x1F, 0xC7, 0x31, 0xC4, 0x70, 0x1C, 0x07, 0x03, 0xE0,\n  0x1F, 0x23, 0x0E, 0x70, 0x6E, 0x02, 0xE0, 0x0E, 0x00, 0xE1, 0xFE, 0x0E,\n  0x60, 0xE7, 0x0E, 0x38, 0xE0, 0xF8, 0xF9, 0xF7, 0x0E, 0x70, 0xE7, 0x0E,\n  0x70, 0xE7, 0xFE, 0x70, 0xE7, 0x0E, 0x70, 0xE7, 0x0E, 0x70, 0xEF, 0x9F,\n  0xFB, 0x9C, 0xE7, 0x39, 0xCE, 0x73, 0x9D, 0xF0, 0x1F, 0x0E, 0x0E, 0x0E,\n  0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E, 0xCE, 0xCC, 0x78, 0xF9, 0xF3,\n  0x82, 0x1C, 0x20, 0xE2, 0x07, 0x20, 0x3F, 0x01, 0xDC, 0x0E, 0x70, 0x73,\n  0xC3, 0x8F, 0x1C, 0x3D, 0xF3, 0xF0, 0xF8, 0x0E, 0x01, 0xC0, 0x38, 0x07,\n  0x00, 0xE0, 0x1C, 0x03, 0x80, 0x70, 0x2E, 0x09, 0xC3, 0x7F, 0xE0, 0xF8,\n  0x0F, 0x3C, 0x1E, 0x3C, 0x1E, 0x2E, 0x2E, 0x2E, 0x2E, 0x26, 0x4E, 0x27,\n  0x4E, 0x27, 0x4E, 0x23, 0x8E, 0x23, 0x8E, 0x21, 0x0E, 0x71, 0x1F, 0xF0,\n  0xEE, 0x09, 0xE1, 0x3E, 0x25, 0xE4, 0x9E, 0x91, 0xD2, 0x1E, 0x43, 0xC8,\n  0x39, 0x03, 0x70, 0x20, 0x1F, 0x83, 0x0C, 0x70, 0xEE, 0x07, 0xE0, 0x7E,\n  0x07, 0xE0, 0x7E, 0x07, 0xE0, 0x77, 0x0E, 0x30, 0xC1, 0xF8, 0xFF, 0x1C,\n  0xE7, 0x1D, 0xC7, 0x71, 0xDC, 0xE7, 0xF1, 0xC0, 0x70, 0x1C, 0x07, 0x03,\n  0xE0, 0x0F, 0x83, 0x9C, 0x70, 0xE6, 0x06, 0xE0, 0x7E, 0x07, 0xE0, 0x7E,\n  0x07, 0xE0, 0x76, 0x06, 0x30, 0xC1, 0x98, 0x0F, 0x00, 0x78, 0x03, 0xE0,\n  0xFF, 0x07, 0x38, 0x71, 0xC7, 0x1C, 0x71, 0xC7, 0x38, 0x7E, 0x07, 0x70,\n  0x77, 0x87, 0x3C, 0x71, 0xEF, 0x8F, 0x39, 0x47, 0xC1, 0xC0, 0xF0, 0x7C,\n  0x3E, 0x0F, 0x83, 0xC3, 0xC6, 0xBC, 0xFF, 0xFC, 0xE3, 0x8E, 0x10, 0xE0,\n  0x0E, 0x00, 0xE0, 0x0E, 0x00, 0xE0, 0x0E, 0x00, 0xE0, 0x0E, 0x01, 0xF0,\n  0xF8, 0xEE, 0x09, 0xC1, 0x38, 0x27, 0x04, 0xE0, 0x9C, 0x13, 0x82, 0x70,\n  0x4E, 0x08, 0xE2, 0x0F, 0x80, 0xFC, 0x7B, 0xC1, 0x0E, 0x08, 0x70, 0x81,\n  0xC4, 0x0E, 0x20, 0x7A, 0x01, 0xD0, 0x0E, 0x80, 0x38, 0x01, 0xC0, 0x04,\n  0x00, 0x20, 0x00, 0xFD, 0xFB, 0xDC, 0x38, 0x43, 0x87, 0x10, 0xE1, 0xC4,\n  0x38, 0xF2, 0x07, 0x2E, 0x81, 0xD3, 0xA0, 0x34, 0x70, 0x0E, 0x1C, 0x03,\n  0x87, 0x00, 0x60, 0x80, 0x10, 0x20, 0xFE, 0xF3, 0xC3, 0x0F, 0x10, 0x39,\n  0x00, 0xF0, 0x03, 0x80, 0x1E, 0x01, 0x70, 0x09, 0xC0, 0x8F, 0x08, 0x3D,\n  0xF3, 0xF0, 0xFC, 0x7B, 0xC1, 0x8E, 0x08, 0x38, 0x81, 0xE8, 0x07, 0x40,\n  0x1C, 0x00, 0xE0, 0x07, 0x00, 0x38, 0x01, 0xC0, 0x1F, 0x00, 0xFF, 0xD8,\n  0x72, 0x1E, 0x43, 0x80, 0xE0, 0x1C, 0x07, 0x01, 0xC0, 0x38, 0x2E, 0x0F,\n  0x83, 0x7F, 0xE0, 0xFC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xF0, 0xC1,\n  0x06, 0x18, 0x20, 0xC3, 0x04, 0x18, 0x60, 0x83, 0x0C, 0xF3, 0x33, 0x33,\n  0x33, 0x33, 0x33, 0x33, 0xF0, 0x18, 0x1C, 0x34, 0x26, 0x62, 0x43, 0xC1,\n  0xFF, 0x80, 0xC6, 0x30, 0x7C, 0x63, 0xB1, 0xC0, 0xE1, 0xF3, 0x3B, 0x9D,\n  0xCE, 0xFF, 0x80, 0xF0, 0x1C, 0x07, 0x01, 0xDC, 0x7B, 0x9C, 0x77, 0x1D,\n  0xC7, 0x71, 0xDC, 0x77, 0x39, 0x3C, 0x3C, 0xED, 0x9F, 0x0E, 0x1C, 0x38,\n  0x39, 0x3C, 0x07, 0x80, 0xE0, 0x38, 0xEE, 0x77, 0xB8, 0xEE, 0x3B, 0x8E,\n  0xE3, 0xB8, 0xE7, 0x78, 0xEF, 0x3C, 0x66, 0xE6, 0xFE, 0xE0, 0xE0, 0xE0,\n  0x72, 0x3C, 0x3E, 0xED, 0xC7, 0xC7, 0x0E, 0x1C, 0x38, 0x70, 0xE1, 0xC7,\n  0xC0, 0x31, 0xDF, 0xBF, 0x7E, 0xE7, 0x90, 0x60, 0xFC, 0xFE, 0x0C, 0x17,\n  0xC0, 0xF0, 0x1C, 0x07, 0x01, 0xDC, 0x7B, 0x9C, 0xE7, 0x39, 0xCE, 0x73,\n  0x9C, 0xE7, 0x3B, 0xFF, 0x73, 0x9D, 0xE7, 0x39, 0xCE, 0x73, 0x9D, 0xF0,\n  0x1C, 0x71, 0xCF, 0x1C, 0x71, 0xC7, 0x1C, 0x71, 0xC7, 0x1C, 0x7D, 0xBE,\n  0xF0, 0x1C, 0x07, 0x01, 0xCE, 0x71, 0x1C, 0x87, 0x41, 0xF8, 0x77, 0x1C,\n  0xE7, 0x1B, 0xEF, 0xF3, 0x9C, 0xE7, 0x39, 0xCE, 0x73, 0x9D, 0xF0, 0xF7,\n  0x38, 0xF7, 0xB9, 0xCE, 0x73, 0x9C, 0xE7, 0x39, 0xCE, 0x73, 0x9C, 0xE7,\n  0x39, 0xCE, 0xFF, 0xFE, 0xF7, 0x1E, 0xE7, 0x39, 0xCE, 0x73, 0x9C, 0xE7,\n  0x39, 0xCE, 0xFF, 0xC0, 0x3E, 0x31, 0xB8, 0xFC, 0x7E, 0x3F, 0x1F, 0x8E,\n  0xC6, 0x3E, 0x00, 0xF7, 0x1E, 0xE7, 0x1D, 0xC7, 0x71, 0xDC, 0x77, 0x1D,\n  0xCE, 0x7F, 0x1C, 0x07, 0x01, 0xC0, 0xF8, 0x00, 0x3C, 0x9C, 0xEE, 0x3B,\n  0x8E, 0xE3, 0xB8, 0xEE, 0x39, 0xCE, 0x3F, 0x80, 0xE0, 0x38, 0x0E, 0x07,\n  0xC0, 0xF7, 0x7B, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0xF8, 0x7E, 0x73,\n  0xC7, 0x8E, 0x39, 0xB0, 0x10, 0xCF, 0x9C, 0x71, 0xC7, 0x1C, 0x71, 0xD3,\n  0x80, 0xF7, 0x9C, 0xE7, 0x39, 0xCE, 0x73, 0x9C, 0xE7, 0x39, 0xCE, 0x3F,\n  0xC0, 0xFB, 0xB8, 0x8C, 0x87, 0x43, 0xC0, 0xE0, 0x70, 0x10, 0x08, 0x00,\n  0xF7, 0xB6, 0x31, 0x73, 0xA3, 0x3A, 0x3D, 0xA3, 0xDC, 0x18, 0xC1, 0x88,\n  0x10, 0x80, 0xFB, 0xB8, 0x8E, 0x83, 0x81, 0xC0, 0xF0, 0x98, 0xCE, 0xEF,\n  0x80, 0xF7, 0x62, 0x72, 0x34, 0x34, 0x3C, 0x18, 0x18, 0x10, 0x10, 0x10,\n  0xE0, 0xE0, 0xFF, 0x1C, 0x70, 0xE3, 0x87, 0x1C, 0x71, 0xFE, 0x19, 0x8C,\n  0x63, 0x18, 0xCC, 0x61, 0x8C, 0x63, 0x18, 0xC3, 0xFF, 0xF8, 0xC3, 0x18,\n  0xC6, 0x31, 0x86, 0x33, 0x18, 0xC6, 0x31, 0x98, 0xF0, 0x8E };\n\nconst GFXglyph FreeSerifBold9pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,   5,    0,    1 },   // 0x20 ' '\n  {     0,   3,  12,   6,    1,  -11 },   // 0x21 '!'\n  {     5,   6,   5,  10,    2,  -11 },   // 0x22 '\"'\n  {     9,   9,  13,   9,    0,  -12 },   // 0x23 '#'\n  {    24,   8,  14,   9,    1,  -12 },   // 0x24 '$'\n  {    38,  14,  12,  18,    2,  -11 },   // 0x25 '%'\n  {    59,  13,  12,  15,    1,  -11 },   // 0x26 '&'\n  {    79,   2,   5,   5,    1,  -11 },   // 0x27 '''\n  {    81,   4,  15,   6,    1,  -11 },   // 0x28 '('\n  {    89,   4,  15,   6,    1,  -11 },   // 0x29 ')'\n  {    97,   7,   7,   9,    2,  -11 },   // 0x2A '*'\n  {   104,   9,   9,  12,    1,   -8 },   // 0x2B '+'\n  {   115,   3,   6,   4,    1,   -2 },   // 0x2C ','\n  {   118,   4,   2,   6,    1,   -4 },   // 0x2D '-'\n  {   119,   3,   3,   4,    1,   -2 },   // 0x2E '.'\n  {   121,   6,  13,   5,    0,  -11 },   // 0x2F '/'\n  {   131,   9,  12,   9,    0,  -11 },   // 0x30 '0'\n  {   145,   6,  12,   9,    1,  -11 },   // 0x31 '1'\n  {   154,   9,  12,   9,    0,  -11 },   // 0x32 '2'\n  {   168,   8,  12,   9,    0,  -11 },   // 0x33 '3'\n  {   180,   8,  12,   9,    1,  -11 },   // 0x34 '4'\n  {   192,   8,  12,   9,    1,  -11 },   // 0x35 '5'\n  {   204,   8,  12,   9,    1,  -11 },   // 0x36 '6'\n  {   216,   9,  12,   9,    0,  -11 },   // 0x37 '7'\n  {   230,   8,  12,   9,    1,  -11 },   // 0x38 '8'\n  {   242,   9,  12,   9,    0,  -11 },   // 0x39 '9'\n  {   256,   3,   9,   6,    1,   -8 },   // 0x3A ':'\n  {   260,   3,  12,   6,    2,   -8 },   // 0x3B ';'\n  {   265,  10,  10,  12,    1,   -9 },   // 0x3C '<'\n  {   278,  10,   5,  12,    1,   -6 },   // 0x3D '='\n  {   285,  10,  10,  12,    1,   -8 },   // 0x3E '>'\n  {   298,   7,  12,   9,    1,  -11 },   // 0x3F '?'\n  {   309,  13,  12,  17,    2,  -11 },   // 0x40 '@'\n  {   329,  13,  12,  13,    0,  -11 },   // 0x41 'A'\n  {   349,  11,  12,  12,    0,  -11 },   // 0x42 'B'\n  {   366,  11,  12,  13,    1,  -11 },   // 0x43 'C'\n  {   383,  11,  12,  13,    1,  -11 },   // 0x44 'D'\n  {   400,  11,  12,  12,    1,  -11 },   // 0x45 'E'\n  {   417,  10,  12,  11,    1,  -11 },   // 0x46 'F'\n  {   432,  12,  12,  14,    1,  -11 },   // 0x47 'G'\n  {   450,  12,  12,  14,    1,  -11 },   // 0x48 'H'\n  {   468,   5,  12,   7,    1,  -11 },   // 0x49 'I'\n  {   476,   8,  14,   9,    0,  -11 },   // 0x4A 'J'\n  {   490,  13,  12,  14,    1,  -11 },   // 0x4B 'K'\n  {   510,  11,  12,  12,    1,  -11 },   // 0x4C 'L'\n  {   527,  16,  12,  17,    0,  -11 },   // 0x4D 'M'\n  {   551,  11,  12,  13,    1,  -11 },   // 0x4E 'N'\n  {   568,  12,  12,  14,    1,  -11 },   // 0x4F 'O'\n  {   586,  10,  12,  11,    1,  -11 },   // 0x50 'P'\n  {   601,  12,  15,  14,    1,  -11 },   // 0x51 'Q'\n  {   624,  12,  12,  13,    1,  -11 },   // 0x52 'R'\n  {   642,   8,  12,  10,    1,  -11 },   // 0x53 'S'\n  {   654,  12,  12,  12,    0,  -11 },   // 0x54 'T'\n  {   672,  11,  12,  13,    1,  -11 },   // 0x55 'U'\n  {   689,  13,  13,  13,    0,  -11 },   // 0x56 'V'\n  {   711,  18,  12,  18,    0,  -11 },   // 0x57 'W'\n  {   738,  13,  12,  13,    0,  -11 },   // 0x58 'X'\n  {   758,  13,  12,  13,    0,  -11 },   // 0x59 'Y'\n  {   778,  11,  12,  12,    1,  -11 },   // 0x5A 'Z'\n  {   795,   4,  15,   6,    1,  -11 },   // 0x5B '['\n  {   803,   6,  13,   5,    0,  -11 },   // 0x5C '\\'\n  {   813,   4,  15,   6,    1,  -11 },   // 0x5D ']'\n  {   821,   8,   7,  10,    1,  -11 },   // 0x5E '^'\n  {   828,   9,   1,   9,    0,    3 },   // 0x5F '_'\n  {   830,   4,   3,   6,    0,  -12 },   // 0x60 '`'\n  {   832,   9,   9,   9,    0,   -8 },   // 0x61 'a'\n  {   843,  10,  12,  10,    0,  -11 },   // 0x62 'b'\n  {   858,   7,   9,   8,    0,   -8 },   // 0x63 'c'\n  {   866,  10,  12,  10,    0,  -11 },   // 0x64 'd'\n  {   881,   8,   9,   8,    0,   -8 },   // 0x65 'e'\n  {   890,   7,  12,   7,    0,  -11 },   // 0x66 'f'\n  {   901,   7,  13,   9,    1,   -8 },   // 0x67 'g'\n  {   913,  10,  12,  10,    0,  -11 },   // 0x68 'h'\n  {   928,   5,  12,   5,    0,  -11 },   // 0x69 'i'\n  {   936,   6,  16,   7,    0,  -11 },   // 0x6A 'j'\n  {   948,  10,  12,  10,    0,  -11 },   // 0x6B 'k'\n  {   963,   5,  12,   5,    0,  -11 },   // 0x6C 'l'\n  {   971,  15,   9,  15,    0,   -8 },   // 0x6D 'm'\n  {   988,  10,   9,  10,    0,   -8 },   // 0x6E 'n'\n  {  1000,   9,   9,   9,    0,   -8 },   // 0x6F 'o'\n  {  1011,  10,  13,  10,    0,   -8 },   // 0x70 'p'\n  {  1028,  10,  13,  10,    0,   -8 },   // 0x71 'q'\n  {  1045,   8,   9,   8,    0,   -8 },   // 0x72 'r'\n  {  1054,   5,   9,   7,    1,   -8 },   // 0x73 's'\n  {  1060,   6,  11,   6,    0,  -10 },   // 0x74 't'\n  {  1069,  10,   9,  10,    0,   -8 },   // 0x75 'u'\n  {  1081,   9,   9,   9,    0,   -8 },   // 0x76 'v'\n  {  1092,  12,   9,  13,    0,   -8 },   // 0x77 'w'\n  {  1106,   9,   9,   9,    0,   -8 },   // 0x78 'x'\n  {  1117,   8,  13,   9,    0,   -8 },   // 0x79 'y'\n  {  1130,   7,   9,   8,    1,   -8 },   // 0x7A 'z'\n  {  1138,   5,  16,   7,    0,  -12 },   // 0x7B '{'\n  {  1148,   1,  13,   4,    1,  -11 },   // 0x7C '|'\n  {  1150,   5,  16,   7,    2,  -12 },   // 0x7D '}'\n  {  1160,   8,   2,   9,    1,   -4 } }; // 0x7E '~'\n\nconst GFXfont FreeSerifBold9pt7b PROGMEM = {\n  (uint8_t  *)FreeSerifBold9pt7bBitmaps,\n  (GFXglyph *)FreeSerifBold9pt7bGlyphs,\n  0x20, 0x7E, 22 };\n\n// Approx. 1834 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeSerifBoldItalic12pt7b.h",
    "content": "const uint8_t FreeSerifBoldItalic12pt7bBitmaps[] PROGMEM = {\n  0x07, 0x07, 0x07, 0x0F, 0x0E, 0x0E, 0x0C, 0x0C, 0x08, 0x18, 0x10, 0x00,\n  0x00, 0x60, 0xF0, 0xF0, 0x60, 0x61, 0xF1, 0xF8, 0xF8, 0x6C, 0x34, 0x12,\n  0x08, 0x01, 0x8C, 0x06, 0x60, 0x31, 0x80, 0xCC, 0x06, 0x30, 0xFF, 0xF0,\n  0xC6, 0x03, 0x18, 0x0C, 0xC0, 0x63, 0x0F, 0xFF, 0x0C, 0x60, 0x33, 0x01,\n  0x8C, 0x06, 0x30, 0x19, 0x80, 0x00, 0x80, 0x08, 0x07, 0xC1, 0x96, 0x31,\n  0x33, 0x13, 0x3A, 0x23, 0xE0, 0x1E, 0x01, 0xF0, 0x07, 0x80, 0x7C, 0x05,\n  0xC4, 0xCC, 0x48, 0xCC, 0x8C, 0xF8, 0x83, 0x30, 0x1E, 0x01, 0x00, 0x00,\n  0x02, 0x07, 0x83, 0x03, 0x9F, 0x81, 0xC4, 0x20, 0x71, 0x10, 0x3C, 0x44,\n  0x0E, 0x22, 0x03, 0x88, 0x80, 0xE4, 0x40, 0x1E, 0x31, 0xE0, 0x08, 0xE4,\n  0x06, 0x71, 0x01, 0x3C, 0x40, 0x8E, 0x10, 0x23, 0x88, 0x10, 0xE2, 0x04,\n  0x39, 0x02, 0x07, 0x80, 0x00, 0xF0, 0x01, 0x98, 0x03, 0x98, 0x03, 0x98,\n  0x03, 0xB0, 0x03, 0xE0, 0x03, 0x80, 0x0F, 0x9F, 0x19, 0xCE, 0x31, 0xCC,\n  0x61, 0xC8, 0xE1, 0xC8, 0xE0, 0xF0, 0xE0, 0xE0, 0xF0, 0x70, 0x78, 0x79,\n  0x3F, 0xBE, 0x7F, 0xED, 0x20, 0x02, 0x08, 0x20, 0xC3, 0x0E, 0x18, 0x30,\n  0xE1, 0x83, 0x06, 0x0C, 0x18, 0x30, 0x20, 0x40, 0x80, 0x81, 0x01, 0x00,\n  0x10, 0x10, 0x20, 0x20, 0x40, 0xC1, 0x83, 0x06, 0x0C, 0x18, 0x70, 0xE1,\n  0x83, 0x0C, 0x18, 0x61, 0x86, 0x00, 0x00, 0x0C, 0x33, 0x6C, 0x9B, 0xAE,\n  0x1C, 0x3F, 0xEC, 0x9B, 0x36, 0x0C, 0x02, 0x00, 0x06, 0x00, 0x60, 0x06,\n  0x00, 0x60, 0x06, 0x0F, 0xFF, 0xFF, 0xF0, 0x60, 0x06, 0x00, 0x60, 0x06,\n  0x00, 0x60, 0x31, 0xCE, 0x31, 0x08, 0x98, 0xFF, 0xFF, 0xC0, 0x6F, 0xF6,\n  0x01, 0x80, 0x60, 0x30, 0x0C, 0x07, 0x01, 0x80, 0xE0, 0x30, 0x1C, 0x06,\n  0x01, 0x80, 0xC0, 0x30, 0x18, 0x06, 0x03, 0x00, 0x03, 0x81, 0xC8, 0x71,\n  0x1C, 0x33, 0x86, 0xE1, 0xDC, 0x3B, 0x87, 0xE0, 0xFC, 0x3B, 0x87, 0x70,\n  0xEC, 0x39, 0x87, 0x31, 0xC2, 0x30, 0x3C, 0x00, 0x01, 0xC3, 0xF0, 0x38,\n  0x0E, 0x03, 0x81, 0xE0, 0x70, 0x1C, 0x0F, 0x03, 0x80, 0xE0, 0x38, 0x1E,\n  0x07, 0x01, 0xC0, 0xF0, 0xFF, 0x80, 0x07, 0x81, 0xF8, 0x47, 0x90, 0x70,\n  0x0E, 0x01, 0xC0, 0x30, 0x0E, 0x01, 0x80, 0x60, 0x18, 0x06, 0x01, 0x80,\n  0x40, 0x8F, 0xF3, 0xFC, 0xFF, 0x80, 0x07, 0xC3, 0x3C, 0x03, 0x80, 0x70,\n  0x0C, 0x03, 0x81, 0xC0, 0xFC, 0x07, 0xC0, 0x78, 0x07, 0x00, 0xE0, 0x1C,\n  0x03, 0x30, 0xE7, 0x10, 0x7C, 0x00, 0x00, 0x10, 0x01, 0x80, 0x3C, 0x03,\n  0xE0, 0x2E, 0x02, 0x70, 0x23, 0x82, 0x38, 0x21, 0xC2, 0x0E, 0x1F, 0xF9,\n  0xFF, 0xC0, 0x38, 0x01, 0xC0, 0x1C, 0x00, 0xE0, 0x07, 0xF0, 0x7E, 0x0F,\n  0xE0, 0x80, 0x08, 0x01, 0xE0, 0x1F, 0x83, 0xF8, 0x03, 0xC0, 0x1C, 0x00,\n  0xC0, 0x0C, 0x00, 0xC0, 0x08, 0x61, 0x8F, 0x30, 0x7C, 0x00, 0x00, 0x60,\n  0x78, 0x1C, 0x0F, 0x01, 0xC0, 0x70, 0x1F, 0xC3, 0x8C, 0xE1, 0xDC, 0x3B,\n  0x87, 0x61, 0xEC, 0x3D, 0x87, 0x31, 0xE2, 0x38, 0x3C, 0x00, 0x3F, 0xEF,\n  0xF9, 0xFF, 0x60, 0xC8, 0x18, 0x06, 0x00, 0x80, 0x30, 0x0C, 0x01, 0x80,\n  0x60, 0x1C, 0x03, 0x00, 0xC0, 0x18, 0x06, 0x00, 0x03, 0x81, 0x88, 0x61,\n  0x8C, 0x31, 0x86, 0x38, 0xC7, 0xB0, 0x78, 0x0F, 0x86, 0x71, 0x87, 0x60,\n  0x6C, 0x0D, 0x81, 0xB0, 0x63, 0x18, 0x3E, 0x00, 0x07, 0x81, 0xC8, 0x71,\n  0x8E, 0x33, 0xC6, 0x70, 0xCE, 0x39, 0xC7, 0x38, 0xE3, 0x38, 0x3F, 0x01,\n  0xC0, 0x38, 0x0E, 0x03, 0x81, 0xC0, 0xE0, 0x00, 0x0C, 0x3C, 0x78, 0x60,\n  0x00, 0x00, 0x00, 0x61, 0xE3, 0xC3, 0x00, 0x0E, 0x0F, 0x0F, 0x0E, 0x00,\n  0x00, 0x00, 0x00, 0x38, 0x38, 0x38, 0x18, 0x10, 0x20, 0x40, 0x00, 0x10,\n  0x07, 0x01, 0xF0, 0x7C, 0x3F, 0x0F, 0x80, 0xE0, 0x0F, 0x80, 0x3E, 0x00,\n  0xF8, 0x03, 0xE0, 0x07, 0x00, 0x10, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00,\n  0xFF, 0xFF, 0xFF, 0x80, 0x07, 0x00, 0x3F, 0x00, 0x3E, 0x00, 0x7C, 0x00,\n  0xF8, 0x01, 0xE0, 0x1F, 0x07, 0xE0, 0xF8, 0x1F, 0x01, 0xE0, 0x0C, 0x00,\n  0x00, 0x1E, 0x19, 0x8C, 0xE6, 0x70, 0x38, 0x38, 0x1C, 0x18, 0x18, 0x08,\n  0x08, 0x00, 0x00, 0x03, 0x03, 0xC1, 0xE0, 0x60, 0x00, 0x03, 0xF0, 0x07,\n  0x06, 0x06, 0x00, 0x86, 0x0E, 0x66, 0x0D, 0xDB, 0x0C, 0xE7, 0x06, 0x33,\n  0x83, 0x31, 0xC3, 0x18, 0xE1, 0x8C, 0x70, 0xCC, 0x4C, 0x66, 0x46, 0x1F,\n  0xC1, 0x80, 0x00, 0x30, 0x10, 0x07, 0xF0, 0x00, 0x10, 0x00, 0x30, 0x00,\n  0x70, 0x00, 0x70, 0x00, 0xF0, 0x01, 0xF0, 0x01, 0x78, 0x03, 0x78, 0x02,\n  0x38, 0x04, 0x38, 0x0C, 0x38, 0x0F, 0xF8, 0x18, 0x3C, 0x30, 0x3C, 0x20,\n  0x3C, 0x60, 0x3C, 0xF8, 0x7F, 0x1F, 0xFC, 0x07, 0x9E, 0x07, 0x0F, 0x07,\n  0x0F, 0x0F, 0x0F, 0x0F, 0x1E, 0x0E, 0x3C, 0x0F, 0xE0, 0x1E, 0x3C, 0x1E,\n  0x1E, 0x1C, 0x1E, 0x3C, 0x1E, 0x3C, 0x1E, 0x3C, 0x3E, 0x38, 0x3C, 0x7C,\n  0x78, 0xFF, 0xE0, 0x01, 0xF2, 0x0E, 0x1C, 0x38, 0x18, 0xE0, 0x33, 0xC0,\n  0x4F, 0x00, 0x9E, 0x00, 0x7C, 0x00, 0xF0, 0x01, 0xE0, 0x03, 0xC0, 0x07,\n  0x80, 0x0F, 0x00, 0x1E, 0x00, 0x1E, 0x04, 0x1E, 0x30, 0x0F, 0x80, 0x1F,\n  0xFC, 0x01, 0xE3, 0xC0, 0x70, 0x78, 0x1C, 0x0E, 0x0F, 0x03, 0xC3, 0xC0,\n  0xF0, 0xE0, 0x3C, 0x38, 0x0F, 0x1E, 0x03, 0xC7, 0x81, 0xF1, 0xC0, 0x78,\n  0xF0, 0x1E, 0x3C, 0x0F, 0x0F, 0x03, 0xC3, 0x81, 0xC1, 0xE1, 0xE0, 0xFF,\n  0xE0, 0x00, 0x1F, 0xFF, 0x83, 0xC1, 0xC1, 0xC0, 0x40, 0xE0, 0x20, 0xF0,\n  0x00, 0x78, 0xC0, 0x38, 0x40, 0x1F, 0xE0, 0x1E, 0x70, 0x0F, 0x18, 0x07,\n  0x08, 0x03, 0x84, 0x03, 0xC0, 0x61, 0xE0, 0x20, 0xE0, 0x30, 0xF8, 0x78,\n  0xFF, 0xFC, 0x00, 0x1F, 0xFF, 0x07, 0x87, 0x07, 0x02, 0x07, 0x02, 0x0F,\n  0x00, 0x0F, 0x18, 0x0E, 0x10, 0x0F, 0xF0, 0x1E, 0x70, 0x1E, 0x30, 0x1C,\n  0x20, 0x1C, 0x00, 0x3C, 0x00, 0x3C, 0x00, 0x38, 0x00, 0x7C, 0x00, 0xFE,\n  0x00, 0x01, 0xF9, 0x03, 0xC3, 0x83, 0x81, 0xC3, 0x80, 0x43, 0xC0, 0x23,\n  0xC0, 0x01, 0xE0, 0x01, 0xF0, 0x00, 0xF0, 0x3F, 0xF8, 0x0F, 0x3C, 0x07,\n  0x9E, 0x03, 0xCF, 0x01, 0xC3, 0x80, 0xE1, 0xE0, 0xF0, 0x78, 0x70, 0x0F,\n  0xE0, 0x00, 0x1F, 0xE7, 0xF0, 0x78, 0x3C, 0x07, 0x83, 0xC0, 0x70, 0x3C,\n  0x0F, 0x03, 0x80, 0xF0, 0x78, 0x0E, 0x07, 0x80, 0xE0, 0x70, 0x1F, 0xFF,\n  0x01, 0xE0, 0xF0, 0x1C, 0x0F, 0x03, 0xC0, 0xE0, 0x3C, 0x1E, 0x03, 0xC1,\n  0xE0, 0x38, 0x1E, 0x07, 0xC3, 0xE0, 0xFE, 0x7F, 0x00, 0x1F, 0xC1, 0xE0,\n  0x70, 0x1C, 0x0F, 0x03, 0xC0, 0xE0, 0x38, 0x1E, 0x07, 0x81, 0xC0, 0x70,\n  0x3C, 0x0F, 0x03, 0x81, 0xF0, 0xFE, 0x00, 0x01, 0xFC, 0x03, 0xC0, 0x0F,\n  0x00, 0x38, 0x00, 0xE0, 0x07, 0x80, 0x1E, 0x00, 0x70, 0x01, 0xC0, 0x0F,\n  0x00, 0x3C, 0x00, 0xE0, 0x07, 0x80, 0x1E, 0x0E, 0x70, 0x3B, 0xC0, 0xCE,\n  0x01, 0xF0, 0x00, 0x1F, 0xEF, 0x83, 0xC1, 0x81, 0xC1, 0x80, 0xE1, 0x80,\n  0xF1, 0x80, 0x79, 0x00, 0x39, 0x00, 0x1F, 0x80, 0x1F, 0xE0, 0x0F, 0x70,\n  0x07, 0x3C, 0x07, 0x8E, 0x03, 0xC7, 0x01, 0xE3, 0xC0, 0xE0, 0xE0, 0xF8,\n  0x78, 0xFE, 0xFE, 0x00, 0x1F, 0xE0, 0x0F, 0x00, 0x1C, 0x00, 0x38, 0x00,\n  0xF0, 0x01, 0xE0, 0x03, 0x80, 0x07, 0x00, 0x1E, 0x00, 0x3C, 0x00, 0x70,\n  0x00, 0xE0, 0x03, 0xC0, 0x27, 0x00, 0xCE, 0x03, 0x3C, 0x1E, 0xFF, 0xFC,\n  0x0F, 0x80, 0x7E, 0x0F, 0x00, 0xF0, 0x1E, 0x03, 0xE0, 0x3C, 0x0F, 0x80,\n  0xB8, 0x17, 0x01, 0x70, 0x5E, 0x02, 0xF1, 0xBC, 0x05, 0xE2, 0x70, 0x11,\n  0xC8, 0xE0, 0x23, 0xB3, 0xC0, 0x47, 0x47, 0x81, 0x0F, 0x8E, 0x02, 0x1E,\n  0x1C, 0x04, 0x38, 0x78, 0x08, 0x70, 0xF0, 0x30, 0xC3, 0xE0, 0xF9, 0x8F,\n  0xE0, 0x1F, 0x03, 0xE0, 0xF0, 0x38, 0x1E, 0x02, 0x03, 0xE0, 0xC0, 0xBC,\n  0x10, 0x13, 0xC2, 0x02, 0x78, 0x40, 0x47, 0x90, 0x10, 0xF2, 0x02, 0x0F,\n  0x40, 0x41, 0xE8, 0x18, 0x1E, 0x02, 0x03, 0xC0, 0x40, 0x38, 0x08, 0x06,\n  0x03, 0x00, 0x40, 0x10, 0x08, 0x00, 0x01, 0xF8, 0x07, 0x1C, 0x0E, 0x0E,\n  0x1E, 0x0F, 0x3C, 0x0F, 0x3C, 0x0F, 0x78, 0x0F, 0x78, 0x0F, 0xF8, 0x1F,\n  0xF0, 0x1E, 0xF0, 0x1E, 0xF0, 0x3C, 0xF0, 0x3C, 0xF0, 0x78, 0x70, 0x70,\n  0x38, 0xE0, 0x1F, 0x80, 0x1F, 0xFC, 0x07, 0x9E, 0x07, 0x0F, 0x07, 0x0F,\n  0x0F, 0x0F, 0x0F, 0x0F, 0x0E, 0x1E, 0x0E, 0x3C, 0x1F, 0xF0, 0x1E, 0x00,\n  0x1C, 0x00, 0x1C, 0x00, 0x3C, 0x00, 0x38, 0x00, 0x38, 0x00, 0x7C, 0x00,\n  0xFE, 0x00, 0x01, 0xF8, 0x07, 0x1C, 0x0E, 0x0E, 0x1E, 0x0F, 0x3C, 0x0F,\n  0x3C, 0x0F, 0x78, 0x0F, 0x78, 0x1F, 0xF8, 0x1F, 0xF0, 0x1E, 0xF0, 0x1E,\n  0xF0, 0x3C, 0xF0, 0x3C, 0xF0, 0x78, 0x70, 0x70, 0x39, 0xC0, 0x0E, 0x00,\n  0x08, 0x02, 0x3F, 0x04, 0x7F, 0xF8, 0x83, 0xF0, 0x1F, 0xF8, 0x07, 0x9E,\n  0x07, 0x8F, 0x07, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x1E, 0x0E, 0x3C,\n  0x1F, 0xF0, 0x1E, 0xF0, 0x1C, 0xF0, 0x3C, 0xF0, 0x3C, 0x78, 0x3C, 0x78,\n  0x3C, 0x78, 0x7C, 0x3C, 0xFE, 0x3E, 0x07, 0x91, 0xC7, 0x18, 0x73, 0x82,\n  0x38, 0x23, 0xC0, 0x3E, 0x01, 0xF0, 0x0F, 0x80, 0x7C, 0x01, 0xE0, 0x1E,\n  0x40, 0xE4, 0x0E, 0x60, 0xCE, 0x1C, 0x9F, 0x00, 0x7F, 0xFE, 0xE7, 0x9D,\n  0x0E, 0x16, 0x3C, 0x20, 0x78, 0x40, 0xE0, 0x01, 0xC0, 0x07, 0x80, 0x0F,\n  0x00, 0x1C, 0x00, 0x38, 0x00, 0xF0, 0x01, 0xE0, 0x03, 0x80, 0x0F, 0x00,\n  0x1E, 0x00, 0xFF, 0x00, 0x7F, 0x1F, 0x3C, 0x0E, 0x38, 0x04, 0x38, 0x0C,\n  0x78, 0x08, 0x78, 0x08, 0x70, 0x08, 0x70, 0x10, 0xF0, 0x10, 0xF0, 0x10,\n  0xF0, 0x10, 0xF0, 0x20, 0xF0, 0x20, 0xF0, 0x20, 0xF0, 0x40, 0x78, 0xC0,\n  0x3F, 0x00, 0xFF, 0x1F, 0x3C, 0x06, 0x3C, 0x04, 0x3C, 0x08, 0x3C, 0x08,\n  0x3C, 0x10, 0x1C, 0x20, 0x1C, 0x20, 0x1E, 0x40, 0x1E, 0x80, 0x1E, 0x80,\n  0x1F, 0x00, 0x0E, 0x00, 0x0E, 0x00, 0x0C, 0x00, 0x08, 0x00, 0xFE, 0x7C,\n  0x79, 0xE1, 0xC1, 0x8F, 0x0E, 0x08, 0x78, 0x70, 0x43, 0xC7, 0x84, 0x1E,\n  0x3E, 0x20, 0x72, 0xF2, 0x03, 0x97, 0x90, 0x1D, 0x1D, 0x00, 0xE8, 0xE8,\n  0x07, 0x87, 0x80, 0x3C, 0x3C, 0x01, 0xC1, 0xC0, 0x0E, 0x0E, 0x00, 0x20,\n  0x60, 0x01, 0x02, 0x00, 0x1F, 0xCF, 0x83, 0xC1, 0x81, 0xE1, 0x80, 0x71,\n  0x80, 0x39, 0x80, 0x1F, 0x80, 0x07, 0x80, 0x03, 0x80, 0x01, 0xE0, 0x01,\n  0xF0, 0x00, 0xB8, 0x00, 0x9C, 0x00, 0x8F, 0x00, 0x83, 0x80, 0xC1, 0xC0,\n  0xE0, 0xF0, 0xF9, 0xFE, 0x00, 0xFE, 0x7C, 0xE0, 0x63, 0x81, 0x0F, 0x08,\n  0x1C, 0x40, 0x71, 0x01, 0xE8, 0x03, 0xC0, 0x0E, 0x00, 0x38, 0x01, 0xE0,\n  0x07, 0x80, 0x1C, 0x00, 0x70, 0x03, 0xC0, 0x0F, 0x00, 0xFF, 0x00, 0x1F,\n  0xFE, 0x38, 0x78, 0x60, 0xF1, 0x83, 0xC2, 0x0F, 0x00, 0x1E, 0x00, 0x78,\n  0x01, 0xE0, 0x07, 0xC0, 0x0F, 0x00, 0x3C, 0x00, 0xF8, 0x01, 0xE0, 0x47,\n  0x81, 0x1F, 0x06, 0x3C, 0x3C, 0xFF, 0xF0, 0x07, 0xC1, 0x80, 0xE0, 0x30,\n  0x0C, 0x03, 0x01, 0xC0, 0x60, 0x18, 0x06, 0x03, 0x80, 0xC0, 0x30, 0x0C,\n  0x07, 0x01, 0xC0, 0x60, 0x18, 0x0E, 0x03, 0xE0, 0xC3, 0x06, 0x18, 0x61,\n  0x83, 0x0C, 0x30, 0xC1, 0x86, 0x18, 0x60, 0xC3, 0x0F, 0x81, 0xC0, 0xE0,\n  0x60, 0x30, 0x18, 0x1C, 0x0C, 0x06, 0x03, 0x03, 0x81, 0x80, 0xC0, 0x60,\n  0x70, 0x38, 0x18, 0x0C, 0x0E, 0x1F, 0x00, 0x0C, 0x07, 0x81, 0xE0, 0xDC,\n  0x33, 0x18, 0xC6, 0x1B, 0x06, 0xC0, 0xC0, 0xFF, 0xF0, 0xC7, 0x0C, 0x30,\n  0x07, 0x70, 0xCE, 0x1C, 0xE3, 0x8E, 0x70, 0xC7, 0x0C, 0x71, 0xCE, 0x1C,\n  0xE1, 0x8E, 0x79, 0xE9, 0xA7, 0x1C, 0x02, 0x07, 0xC0, 0x38, 0x06, 0x01,\n  0xC0, 0x38, 0x06, 0x71, 0xF7, 0x38, 0xE7, 0x1C, 0xC3, 0xB8, 0x77, 0x1C,\n  0xE3, 0xB8, 0xE7, 0x18, 0xE6, 0x0F, 0x80, 0x07, 0x0C, 0xCE, 0x66, 0x07,\n  0x03, 0x83, 0x81, 0xC0, 0xE0, 0x70, 0xBC, 0x87, 0x80, 0x00, 0x08, 0x03,\n  0xE0, 0x03, 0x80, 0x0E, 0x00, 0x70, 0x01, 0xC0, 0x77, 0x03, 0x3C, 0x18,\n  0xE0, 0xE3, 0x87, 0x0E, 0x1C, 0x70, 0x71, 0xC3, 0x87, 0x0E, 0x3C, 0x38,\n  0xE8, 0xE5, 0xA1, 0xE7, 0x00, 0x07, 0x0C, 0xCE, 0x66, 0x37, 0x33, 0xBB,\n  0xB1, 0xE0, 0xE0, 0x70, 0xB8, 0x87, 0x80, 0x00, 0x38, 0x01, 0xB0, 0x0C,\n  0xC0, 0x30, 0x01, 0xC0, 0x07, 0x00, 0x7E, 0x00, 0xE0, 0x03, 0x80, 0x0E,\n  0x00, 0x30, 0x01, 0xC0, 0x07, 0x00, 0x1C, 0x00, 0x70, 0x03, 0x80, 0x0E,\n  0x00, 0x38, 0x00, 0xC0, 0x33, 0x00, 0xD8, 0x01, 0xC0, 0x00, 0x03, 0x80,\n  0x73, 0xC7, 0x1C, 0x38, 0xE1, 0xCF, 0x06, 0x70, 0x1E, 0x01, 0x00, 0x1C,\n  0x00, 0xF8, 0x07, 0xF0, 0xC7, 0x8C, 0x0C, 0x60, 0x63, 0x86, 0x07, 0xE0,\n  0x01, 0x00, 0xF8, 0x01, 0x80, 0x1C, 0x00, 0xE0, 0x07, 0x00, 0x31, 0xC3,\n  0xBE, 0x1E, 0x70, 0xE3, 0x8F, 0x38, 0x71, 0xC3, 0x8E, 0x1C, 0xE1, 0xC7,\n  0x0E, 0x3A, 0x71, 0xD3, 0x0F, 0x00, 0x1C, 0x71, 0xC0, 0x00, 0x6F, 0x8E,\n  0x31, 0xC7, 0x18, 0x63, 0x8E, 0xBC, 0xE0, 0x00, 0xE0, 0x1C, 0x03, 0x80,\n  0x00, 0x00, 0x0F, 0x80, 0x70, 0x0E, 0x01, 0xC0, 0x70, 0x0E, 0x01, 0xC0,\n  0x38, 0x0E, 0x01, 0xC0, 0x38, 0x06, 0x01, 0xC3, 0x38, 0x6E, 0x07, 0x80,\n  0x01, 0x00, 0xF8, 0x01, 0xC0, 0x1C, 0x00, 0xE0, 0x07, 0x00, 0x33, 0xE3,\n  0x8C, 0x1C, 0xC0, 0xE4, 0x06, 0x40, 0x7E, 0x03, 0xF0, 0x1D, 0x81, 0xCE,\n  0x0E, 0x72, 0x71, 0xA3, 0x8E, 0x00, 0x06, 0x7C, 0x70, 0xE1, 0xC3, 0x0E,\n  0x1C, 0x38, 0x61, 0xC3, 0x87, 0x0C, 0x38, 0x72, 0xE9, 0xE0, 0x3C, 0x73,\n  0xC7, 0x7D, 0x71, 0xE7, 0x9C, 0xF1, 0xCE, 0x3C, 0xF3, 0x8E, 0x39, 0xC3,\n  0x8E, 0x71, 0xC3, 0x1C, 0x71, 0xC7, 0x1C, 0x71, 0xD7, 0x1C, 0x7B, 0x8E,\n  0x1C, 0x3C, 0xF1, 0xD7, 0x1E, 0x73, 0xCE, 0x3C, 0xE3, 0x8E, 0x39, 0xC7,\n  0x9C, 0x71, 0xC7, 0x1D, 0x71, 0xEE, 0x1C, 0x0F, 0x06, 0x63, 0x9D, 0xC7,\n  0x71, 0xF8, 0x7E, 0x3F, 0x8E, 0xE3, 0xB9, 0xC6, 0x60, 0xF0, 0x0F, 0x38,\n  0x1F, 0x70, 0x71, 0xC1, 0xC7, 0x0E, 0x1C, 0x38, 0xF0, 0xE3, 0x83, 0x8E,\n  0x1C, 0x70, 0x71, 0xC1, 0xCE, 0x07, 0xE0, 0x38, 0x00, 0xE0, 0x03, 0x80,\n  0x3F, 0x00, 0x07, 0x70, 0xCE, 0x18, 0xE3, 0x8E, 0x70, 0xE7, 0x1C, 0xF1,\n  0xCE, 0x1C, 0xE3, 0x8E, 0x38, 0xE7, 0x87, 0xB0, 0x07, 0x00, 0x70, 0x0F,\n  0x03, 0xF8, 0x0D, 0xDF, 0x71, 0xAC, 0xF0, 0x38, 0x0E, 0x03, 0x81, 0xC0,\n  0x70, 0x1C, 0x0E, 0x00, 0x1D, 0x99, 0x8C, 0x46, 0x23, 0x80, 0xE0, 0x70,\n  0x1C, 0x06, 0x23, 0x19, 0x17, 0x00, 0x0C, 0x10, 0xE3, 0xF3, 0x86, 0x1C,\n  0x38, 0x71, 0xC3, 0x87, 0x0E, 0x9E, 0x38, 0x00, 0xF8, 0xE3, 0x8E, 0x38,\n  0xC3, 0x9C, 0x71, 0xC7, 0x18, 0x71, 0x87, 0x38, 0xE3, 0x8E, 0xFA, 0xF3,\n  0xAE, 0x3C, 0xF0, 0xDC, 0x33, 0x0C, 0xC2, 0x31, 0x8C, 0xC3, 0x60, 0xF0,\n  0x38, 0x0C, 0x02, 0x00, 0xE0, 0x86, 0xE3, 0x0C, 0xC6, 0x19, 0x9C, 0x23,\n  0x78, 0xC7, 0xF9, 0x0E, 0x74, 0x1C, 0xF0, 0x31, 0xC0, 0x43, 0x00, 0x84,\n  0x00, 0x0E, 0x31, 0xF3, 0x83, 0xA0, 0x0E, 0x00, 0x70, 0x03, 0x80, 0x1C,\n  0x00, 0xE0, 0x0B, 0x02, 0x5D, 0x3C, 0xF1, 0xC3, 0x00, 0x04, 0x67, 0x8C,\n  0x79, 0x87, 0x10, 0xE2, 0x1C, 0x81, 0x90, 0x3A, 0x07, 0x80, 0xF0, 0x1C,\n  0x03, 0x00, 0x40, 0x08, 0x32, 0x07, 0x80, 0x3F, 0xCF, 0xE6, 0x30, 0x08,\n  0x04, 0x02, 0x01, 0x00, 0xC0, 0x30, 0x1E, 0x0F, 0x98, 0x76, 0x07, 0x00,\n  0x01, 0xE0, 0x70, 0x1C, 0x03, 0x80, 0x60, 0x1C, 0x03, 0x80, 0x60, 0x0C,\n  0x03, 0x80, 0xF0, 0x3C, 0x07, 0x00, 0x40, 0x0C, 0x01, 0x80, 0x70, 0x0E,\n  0x01, 0xC0, 0x30, 0x03, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, 0x07, 0x00, 0xE0,\n  0x18, 0x06, 0x01, 0x80, 0xE0, 0x38, 0x0C, 0x03, 0x00, 0xC0, 0x10, 0x1F,\n  0x07, 0x03, 0x80, 0xE0, 0x30, 0x0C, 0x07, 0x01, 0x80, 0xE0, 0xE0, 0x00,\n  0x38, 0x0F, 0xCD, 0x1F, 0x80, 0xE0 };\n\nconst GFXglyph FreeSerifBoldItalic12pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,   6,    0,    1 },   // 0x20 ' '\n  {     0,   8,  17,   9,    2,  -15 },   // 0x21 '!'\n  {    17,   9,   7,  13,    4,  -15 },   // 0x22 '\"'\n  {    25,  14,  16,  12,   -1,  -15 },   // 0x23 '#'\n  {    53,  12,  20,  12,    0,  -17 },   // 0x24 '$'\n  {    83,  18,  18,  20,    1,  -16 },   // 0x25 '%'\n  {   124,  16,  17,  19,    0,  -15 },   // 0x26 '&'\n  {   158,   3,   7,   7,    3,  -15 },   // 0x27 '''\n  {   161,   7,  21,   8,    1,  -15 },   // 0x28 '('\n  {   180,   7,  21,   8,   -1,  -15 },   // 0x29 ')'\n  {   199,  10,  10,  12,    1,  -15 },   // 0x2A '*'\n  {   212,  12,  12,  14,    1,  -11 },   // 0x2B '+'\n  {   230,   5,   8,   6,   -2,   -3 },   // 0x2C ','\n  {   235,   6,   3,   8,    0,   -6 },   // 0x2D '-'\n  {   238,   4,   4,   6,    0,   -2 },   // 0x2E '.'\n  {   240,  10,  16,   8,    0,  -15 },   // 0x2F '/'\n  {   260,  11,  17,  12,    0,  -15 },   // 0x30 '0'\n  {   284,  10,  17,  12,    0,  -15 },   // 0x31 '1'\n  {   306,  11,  17,  12,    0,  -15 },   // 0x32 '2'\n  {   330,  11,  17,  12,    0,  -15 },   // 0x33 '3'\n  {   354,  13,  16,  12,    0,  -15 },   // 0x34 '4'\n  {   380,  12,  17,  12,    0,  -15 },   // 0x35 '5'\n  {   406,  11,  17,  12,    1,  -15 },   // 0x36 '6'\n  {   430,  11,  16,  12,    2,  -15 },   // 0x37 '7'\n  {   452,  11,  17,  12,    0,  -15 },   // 0x38 '8'\n  {   476,  11,  17,  12,    0,  -15 },   // 0x39 '9'\n  {   500,   7,  12,   6,    0,  -10 },   // 0x3A ':'\n  {   511,   8,  15,   6,   -1,  -10 },   // 0x3B ';'\n  {   526,  12,  13,  14,    1,  -12 },   // 0x3C '<'\n  {   546,  12,   6,  14,    2,   -8 },   // 0x3D '='\n  {   555,  13,  13,  14,    1,  -12 },   // 0x3E '>'\n  {   577,   9,  17,  12,    2,  -15 },   // 0x3F '?'\n  {   597,  17,  16,  20,    1,  -15 },   // 0x40 '@'\n  {   631,  16,  17,  17,    0,  -15 },   // 0x41 'A'\n  {   665,  16,  17,  15,    0,  -15 },   // 0x42 'B'\n  {   699,  15,  17,  15,    1,  -15 },   // 0x43 'C'\n  {   731,  18,  17,  17,    0,  -15 },   // 0x44 'D'\n  {   770,  17,  17,  15,    0,  -15 },   // 0x45 'E'\n  {   807,  16,  17,  15,    0,  -15 },   // 0x46 'F'\n  {   841,  17,  17,  17,    1,  -15 },   // 0x47 'G'\n  {   878,  20,  17,  18,    0,  -15 },   // 0x48 'H'\n  {   921,  10,  17,   9,    0,  -15 },   // 0x49 'I'\n  {   943,  14,  18,  12,    0,  -15 },   // 0x4A 'J'\n  {   975,  17,  17,  16,    0,  -15 },   // 0x4B 'K'\n  {  1012,  15,  17,  15,    0,  -15 },   // 0x4C 'L'\n  {  1044,  23,  17,  21,    0,  -15 },   // 0x4D 'M'\n  {  1093,  19,  17,  17,    0,  -15 },   // 0x4E 'N'\n  {  1134,  16,  17,  16,    1,  -15 },   // 0x4F 'O'\n  {  1168,  16,  17,  14,    0,  -15 },   // 0x50 'P'\n  {  1202,  16,  21,  16,    1,  -15 },   // 0x51 'Q'\n  {  1244,  16,  17,  16,    0,  -15 },   // 0x52 'R'\n  {  1278,  12,  17,  12,    0,  -15 },   // 0x53 'S'\n  {  1304,  15,  17,  14,    2,  -15 },   // 0x54 'T'\n  {  1336,  16,  17,  17,    3,  -15 },   // 0x55 'U'\n  {  1370,  16,  16,  17,    3,  -15 },   // 0x56 'V'\n  {  1402,  21,  16,  22,    3,  -15 },   // 0x57 'W'\n  {  1444,  17,  17,  17,    0,  -15 },   // 0x58 'X'\n  {  1481,  14,  17,  15,    3,  -15 },   // 0x59 'Y'\n  {  1511,  15,  17,  13,    0,  -15 },   // 0x5A 'Z'\n  {  1543,  10,  20,   8,   -1,  -15 },   // 0x5B '['\n  {  1568,   6,  16,  10,    3,  -15 },   // 0x5C '\\'\n  {  1580,   9,  20,   8,   -1,  -15 },   // 0x5D ']'\n  {  1603,  10,   9,  14,    2,  -15 },   // 0x5E '^'\n  {  1615,  12,   1,  12,    0,    4 },   // 0x5F '_'\n  {  1617,   5,   4,   8,    2,  -15 },   // 0x60 '`'\n  {  1620,  12,  12,  12,    0,  -10 },   // 0x61 'a'\n  {  1638,  11,  18,  12,    1,  -16 },   // 0x62 'b'\n  {  1663,   9,  12,  10,    1,  -10 },   // 0x63 'c'\n  {  1677,  14,  18,  12,    0,  -16 },   // 0x64 'd'\n  {  1709,   9,  12,  10,    1,  -10 },   // 0x65 'e'\n  {  1723,  14,  22,  12,   -2,  -16 },   // 0x66 'f'\n  {  1762,  13,  16,  12,   -1,  -10 },   // 0x67 'g'\n  {  1788,  13,  18,  13,    0,  -16 },   // 0x68 'h'\n  {  1818,   6,  17,   7,    1,  -15 },   // 0x69 'i'\n  {  1831,  11,  21,   8,   -2,  -15 },   // 0x6A 'j'\n  {  1860,  13,  18,  12,    0,  -16 },   // 0x6B 'k'\n  {  1890,   7,  18,   7,    1,  -16 },   // 0x6C 'l'\n  {  1906,  18,  12,  18,    0,  -10 },   // 0x6D 'm'\n  {  1933,  12,  12,  13,    0,  -10 },   // 0x6E 'n'\n  {  1951,  10,  12,  11,    1,  -10 },   // 0x6F 'o'\n  {  1966,  14,  16,  12,   -2,  -10 },   // 0x70 'p'\n  {  1994,  12,  16,  12,    0,  -10 },   // 0x71 'q'\n  {  2018,  10,  11,  10,    0,  -10 },   // 0x72 'r'\n  {  2032,   9,  12,   9,    0,  -10 },   // 0x73 's'\n  {  2046,   7,  15,   7,    1,  -13 },   // 0x74 't'\n  {  2060,  12,  12,  13,    1,  -10 },   // 0x75 'u'\n  {  2078,  10,  11,  11,    1,  -10 },   // 0x76 'v'\n  {  2092,  15,  11,  16,    1,  -10 },   // 0x77 'w'\n  {  2113,  13,  12,  11,   -1,  -10 },   // 0x78 'x'\n  {  2133,  11,  16,  10,   -1,  -10 },   // 0x79 'y'\n  {  2155,  10,  13,  10,    0,  -10 },   // 0x7A 'z'\n  {  2172,  11,  21,   8,    0,  -16 },   // 0x7B '{'\n  {  2201,   2,  16,   6,    3,  -15 },   // 0x7C '|'\n  {  2205,  10,  21,   8,   -3,  -16 },   // 0x7D '}'\n  {  2232,  11,   4,  14,    1,   -7 } }; // 0x7E '~'\n\nconst GFXfont FreeSerifBoldItalic12pt7b PROGMEM = {\n  (uint8_t  *)FreeSerifBoldItalic12pt7bBitmaps,\n  (GFXglyph *)FreeSerifBoldItalic12pt7bGlyphs,\n  0x20, 0x7E, 29 };\n\n// Approx. 2910 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeSerifBoldItalic18pt7b.h",
    "content": "const uint8_t FreeSerifBoldItalic18pt7bBitmaps[] PROGMEM = {\n  0x01, 0xC0, 0x7C, 0x0F, 0x81, 0xF0, 0x3E, 0x07, 0x80, 0xF0, 0x3C, 0x07,\n  0x80, 0xE0, 0x1C, 0x03, 0x00, 0x60, 0x0C, 0x03, 0x00, 0x60, 0x08, 0x00,\n  0x00, 0x00, 0x00, 0x07, 0x81, 0xF8, 0x3F, 0x07, 0xE0, 0x78, 0x00, 0x38,\n  0x1D, 0xE0, 0xF7, 0x83, 0xDC, 0x0E, 0x70, 0x39, 0xC0, 0xE6, 0x03, 0x18,\n  0x0C, 0x40, 0x23, 0x01, 0x80, 0x00, 0x38, 0x60, 0x07, 0x0E, 0x00, 0x70,\n  0xC0, 0x06, 0x1C, 0x00, 0xE1, 0xC0, 0x0E, 0x38, 0x01, 0xC3, 0x81, 0xFF,\n  0xFF, 0x1F, 0xFF, 0xE1, 0xFF, 0xFE, 0x03, 0x86, 0x00, 0x30, 0xE0, 0x07,\n  0x0E, 0x00, 0x71, 0xC0, 0x0E, 0x1C, 0x0F, 0xFF, 0xF8, 0xFF, 0xFF, 0x0F,\n  0xFF, 0xF0, 0x1C, 0x30, 0x01, 0x87, 0x00, 0x38, 0x70, 0x03, 0x0E, 0x00,\n  0x70, 0xE0, 0x07, 0x0C, 0x00, 0xE1, 0xC0, 0x00, 0x00, 0x08, 0x00, 0x0C,\n  0x00, 0x7E, 0x00, 0xFF, 0xC0, 0xF3, 0x70, 0x71, 0x9C, 0x70, 0xC6, 0x38,\n  0x43, 0x1C, 0x61, 0x0F, 0x30, 0x87, 0xD8, 0x03, 0xF8, 0x00, 0xFE, 0x00,\n  0x3F, 0x80, 0x0F, 0xE0, 0x03, 0xF8, 0x01, 0xFC, 0x00, 0xDF, 0x10, 0x47,\n  0x88, 0x63, 0xCC, 0x31, 0xE6, 0x10, 0xF3, 0x98, 0x71, 0xCC, 0x78, 0x7E,\n  0x78, 0x07, 0xF8, 0x03, 0xF0, 0x01, 0x80, 0x00, 0xC0, 0x00, 0x03, 0xC0,\n  0x18, 0x01, 0xFE, 0x0F, 0x00, 0x7C, 0xFF, 0xC0, 0x1F, 0x0F, 0x98, 0x07,\n  0xC1, 0x06, 0x00, 0xF8, 0x21, 0x80, 0x3E, 0x04, 0x30, 0x07, 0xC1, 0x8C,\n  0x00, 0xF0, 0x21, 0x80, 0x1E, 0x0C, 0x60, 0x03, 0xC1, 0x0C, 0x00, 0x78,\n  0xC3, 0x03, 0xC7, 0xF8, 0x61, 0xFC, 0x7C, 0x18, 0x7C, 0xC0, 0x06, 0x1F,\n  0x08, 0x00, 0xC7, 0xC1, 0x00, 0x30, 0xF0, 0x20, 0x06, 0x3E, 0x04, 0x01,\n  0x87, 0xC1, 0x00, 0x30, 0xF0, 0x20, 0x0C, 0x1E, 0x0C, 0x03, 0x03, 0xC1,\n  0x00, 0x60, 0x3C, 0xC0, 0x18, 0x07, 0xF8, 0x03, 0x00, 0x7C, 0x00, 0x00,\n  0x0F, 0x80, 0x00, 0x1F, 0xF0, 0x00, 0x1E, 0x38, 0x00, 0x0E, 0x0E, 0x00,\n  0x0F, 0x07, 0x00, 0x07, 0x83, 0x80, 0x03, 0xC3, 0x80, 0x01, 0xE3, 0x80,\n  0x00, 0xF7, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x7F, 0x0F,\n  0xF0, 0xE7, 0x81, 0xE0, 0xE3, 0xE0, 0xE0, 0xE1, 0xF0, 0x60, 0xE0, 0x7C,\n  0x60, 0xF0, 0x3E, 0x20, 0x78, 0x1F, 0xB0, 0x3C, 0x07, 0xF0, 0x1F, 0x03,\n  0xF0, 0x0F, 0x80, 0xFC, 0x03, 0xF0, 0x7F, 0x8D, 0xFF, 0xEF, 0xFC, 0x7F,\n  0xE3, 0xFC, 0x0F, 0xC0, 0x78, 0x00, 0x3B, 0xDE, 0xE7, 0x39, 0x8C, 0x46,\n  0x00, 0x00, 0x60, 0x18, 0x06, 0x01, 0x80, 0x60, 0x1C, 0x07, 0x01, 0xE0,\n  0x38, 0x0F, 0x01, 0xC0, 0x38, 0x0F, 0x01, 0xE0, 0x38, 0x07, 0x00, 0xE0,\n  0x1C, 0x03, 0x80, 0x70, 0x0E, 0x00, 0xC0, 0x18, 0x03, 0x00, 0x60, 0x06,\n  0x00, 0xC0, 0x08, 0x00, 0x80, 0x10, 0x00, 0x06, 0x00, 0x40, 0x04, 0x00,\n  0x80, 0x18, 0x01, 0x00, 0x30, 0x06, 0x00, 0xC0, 0x1C, 0x03, 0x80, 0x70,\n  0x0E, 0x01, 0xC0, 0x38, 0x07, 0x01, 0xE0, 0x3C, 0x07, 0x00, 0xE0, 0x3C,\n  0x07, 0x00, 0xE0, 0x38, 0x06, 0x01, 0xC0, 0x70, 0x18, 0x06, 0x01, 0x80,\n  0x00, 0x07, 0x00, 0x38, 0x01, 0xC1, 0x8E, 0x3E, 0x23, 0xF9, 0x3F, 0xEB,\n  0xE0, 0xE0, 0xFF, 0xF7, 0x93, 0xF8, 0x9F, 0x8E, 0x60, 0x70, 0x03, 0x80,\n  0x08, 0x00, 0x01, 0xC0, 0x00, 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C,\n  0x00, 0x0E, 0x00, 0x07, 0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0,\n  0x70, 0x00, 0x38, 0x00, 0x1C, 0x00, 0x0E, 0x00, 0x07, 0x00, 0x03, 0x80,\n  0x01, 0xC0, 0x00, 0x1C, 0x7C, 0xF9, 0xF1, 0xE1, 0xC3, 0x0C, 0x30, 0xC2,\n  0x00, 0x7F, 0xFF, 0xFF, 0xFF, 0xE0, 0x7B, 0xFF, 0xFF, 0x78, 0x00, 0x1C,\n  0x00, 0xE0, 0x03, 0x80, 0x1E, 0x00, 0x70, 0x01, 0xC0, 0x0E, 0x00, 0x38,\n  0x01, 0xC0, 0x07, 0x00, 0x38, 0x00, 0xE0, 0x07, 0x80, 0x1C, 0x00, 0x70,\n  0x03, 0x80, 0x0E, 0x00, 0x70, 0x01, 0xC0, 0x0E, 0x00, 0x38, 0x01, 0xC0,\n  0x07, 0x00, 0x1C, 0x00, 0xE0, 0x00, 0x00, 0xF0, 0x07, 0x30, 0x1C, 0x30,\n  0x78, 0x60, 0xE0, 0xE3, 0xC1, 0xCF, 0x83, 0x9E, 0x0F, 0x3C, 0x1E, 0xF8,\n  0x3D, 0xE0, 0x7B, 0xC1, 0xFF, 0x83, 0xFF, 0x07, 0xBC, 0x0F, 0x78, 0x3E,\n  0xF0, 0x7D, 0xE0, 0xF3, 0x81, 0xE7, 0x07, 0x8E, 0x0F, 0x0C, 0x3C, 0x18,\n  0x70, 0x19, 0xC0, 0x1E, 0x00, 0x00, 0x06, 0x01, 0xF8, 0x1F, 0xF0, 0x03,\n  0xE0, 0x07, 0x80, 0x1F, 0x00, 0x3E, 0x00, 0x7C, 0x00, 0xF0, 0x03, 0xE0,\n  0x07, 0xC0, 0x0F, 0x80, 0x1E, 0x00, 0x7C, 0x00, 0xF8, 0x01, 0xE0, 0x07,\n  0xC0, 0x0F, 0x80, 0x1F, 0x00, 0x3C, 0x00, 0xF8, 0x01, 0xF0, 0x03, 0xE0,\n  0x0F, 0xC0, 0xFF, 0xF0, 0x00, 0xF8, 0x01, 0xFC, 0x03, 0xFE, 0x06, 0x3F,\n  0x08, 0x1F, 0x18, 0x0F, 0x00, 0x0F, 0x00, 0x0F, 0x00, 0x0F, 0x00, 0x0E,\n  0x00, 0x1E, 0x00, 0x1C, 0x00, 0x38, 0x00, 0x30, 0x00, 0x70, 0x00, 0xC0,\n  0x01, 0x80, 0x03, 0x00, 0x06, 0x02, 0x0C, 0x06, 0x08, 0x0C, 0x1F, 0xFC,\n  0x3F, 0xFC, 0x7F, 0xF8, 0xFF, 0xF8, 0x00, 0xF0, 0x07, 0xF8, 0x1F, 0xF0,\n  0x61, 0xF0, 0x81, 0xE0, 0x03, 0xC0, 0x07, 0x80, 0x0E, 0x00, 0x3C, 0x00,\n  0xE0, 0x07, 0xC0, 0x3F, 0xC0, 0x1F, 0x80, 0x0F, 0x80, 0x1F, 0x00, 0x1E,\n  0x00, 0x3C, 0x00, 0x78, 0x00, 0xF0, 0x01, 0xC0, 0x07, 0x9C, 0x0E, 0x3C,\n  0x38, 0x7F, 0xE0, 0x7E, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x70, 0x00, 0x3C,\n  0x00, 0x1E, 0x00, 0x0F, 0x80, 0x07, 0xE0, 0x02, 0xF8, 0x01, 0x3C, 0x00,\n  0x9F, 0x00, 0x47, 0xC0, 0x31, 0xE0, 0x18, 0x78, 0x0C, 0x3E, 0x06, 0x0F,\n  0x83, 0x03, 0xC1, 0x80, 0xF0, 0x7F, 0xFF, 0x1F, 0xFF, 0xCF, 0xFF, 0xF0,\n  0x03, 0xE0, 0x00, 0xF8, 0x00, 0x3C, 0x00, 0x0F, 0x00, 0x07, 0xC0, 0x01,\n  0xFF, 0x00, 0xFF, 0x80, 0xFF, 0xC0, 0x7F, 0xE0, 0x60, 0x00, 0x30, 0x00,\n  0x10, 0x00, 0x1F, 0x00, 0x0F, 0xE0, 0x0F, 0xF8, 0x07, 0xFE, 0x00, 0x3F,\n  0x00, 0x07, 0xC0, 0x01, 0xE0, 0x00, 0xF0, 0x00, 0x38, 0x00, 0x1C, 0x00,\n  0x0E, 0x00, 0x06, 0x00, 0x03, 0x00, 0x03, 0x87, 0x83, 0x83, 0xE3, 0x81,\n  0xFF, 0x80, 0x3F, 0x00, 0x00, 0x00, 0x03, 0x80, 0x0F, 0x80, 0x1F, 0x00,\n  0x3E, 0x00, 0x3E, 0x00, 0x3E, 0x00, 0x3E, 0x00, 0x3E, 0x00, 0x1F, 0x00,\n  0x1F, 0xF0, 0x1F, 0xFE, 0x0F, 0xCF, 0x07, 0xC3, 0xC7, 0xE1, 0xE3, 0xE0,\n  0xF1, 0xF0, 0x78, 0xF8, 0x3C, 0x78, 0x3E, 0x3C, 0x1F, 0x1E, 0x0F, 0x0F,\n  0x0F, 0x83, 0x87, 0x81, 0xE7, 0x80, 0x7F, 0x80, 0x0F, 0x80, 0x00, 0x3F,\n  0xFF, 0x3F, 0xFE, 0x3F, 0xFE, 0x7F, 0xFC, 0x60, 0x1C, 0x80, 0x38, 0x80,\n  0x30, 0x00, 0x70, 0x00, 0x60, 0x00, 0xE0, 0x01, 0xC0, 0x01, 0xC0, 0x03,\n  0x80, 0x03, 0x80, 0x07, 0x00, 0x0E, 0x00, 0x0E, 0x00, 0x1C, 0x00, 0x1C,\n  0x00, 0x38, 0x00, 0x38, 0x00, 0x70, 0x00, 0xF0, 0x00, 0xE0, 0x00, 0x00,\n  0xF8, 0x00, 0xFF, 0x00, 0xE1, 0xC0, 0xE0, 0xF0, 0xF0, 0x38, 0x78, 0x1C,\n  0x3C, 0x0E, 0x1F, 0x07, 0x0F, 0x87, 0x07, 0xE7, 0x01, 0xFF, 0x00, 0x7E,\n  0x00, 0x1F, 0x80, 0x3F, 0xE0, 0x73, 0xF0, 0x70, 0xFC, 0x70, 0x3E, 0x70,\n  0x0F, 0x38, 0x07, 0x9C, 0x03, 0xCE, 0x01, 0xE7, 0x00, 0xE1, 0xC0, 0xE0,\n  0x70, 0xE0, 0x0F, 0xC0, 0x00, 0x00, 0xF8, 0x01, 0xFF, 0x01, 0xF3, 0xC1,\n  0xF0, 0xE1, 0xF0, 0x70, 0xF0, 0x3C, 0xF8, 0x1E, 0x7C, 0x0F, 0x3C, 0x0F,\n  0x9E, 0x07, 0xCF, 0x03, 0xE7, 0x83, 0xF3, 0xC1, 0xF0, 0xF1, 0xF8, 0x3F,\n  0xF8, 0x0F, 0xFC, 0x00, 0x7C, 0x00, 0x7C, 0x00, 0x7E, 0x00, 0x3E, 0x00,\n  0x3C, 0x00, 0x7C, 0x00, 0x7C, 0x00, 0xF0, 0x00, 0xC0, 0x00, 0x00, 0x07,\n  0x83, 0xF0, 0xFC, 0x3F, 0x07, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x78, 0x3F, 0x0F, 0xC3, 0xF0, 0x78, 0x00, 0x03, 0xC0, 0xFC,\n  0x1F, 0x83, 0xF0, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n  0x0C, 0x03, 0xC0, 0x7C, 0x0F, 0x80, 0xF0, 0x0E, 0x01, 0x80, 0x30, 0x0C,\n  0x03, 0x01, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x7C, 0x00,\n  0x7F, 0x00, 0x7F, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0xFE, 0x00, 0xFE, 0x00,\n  0x3E, 0x00, 0x0F, 0xC0, 0x01, 0xFC, 0x00, 0x1F, 0xE0, 0x01, 0xFE, 0x00,\n  0x0F, 0xE0, 0x00, 0xFF, 0x00, 0x0F, 0xC0, 0x00, 0xF0, 0x00, 0x04, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x03, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0x00, 0x00,\n  0x38, 0x00, 0x0F, 0x80, 0x03, 0xF8, 0x00, 0x3F, 0x80, 0x03, 0xFC, 0x00,\n  0x3F, 0xC0, 0x01, 0xFC, 0x00, 0x1F, 0xC0, 0x01, 0xF0, 0x00, 0xFC, 0x00,\n  0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFC, 0x03, 0xFC, 0x00, 0xFC, 0x00,\n  0x3C, 0x00, 0x08, 0x00, 0x00, 0x07, 0xC0, 0xFF, 0x0E, 0x3C, 0x70, 0xF3,\n  0xC7, 0x8C, 0x3C, 0x01, 0xE0, 0x1F, 0x00, 0xF0, 0x07, 0x80, 0x78, 0x07,\n  0x80, 0x30, 0x03, 0x00, 0x10, 0x01, 0x80, 0x08, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0x07, 0x80, 0x7E, 0x03, 0xF0, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x3F,\n  0x80, 0x00, 0xFF, 0xF8, 0x01, 0xF0, 0x1E, 0x01, 0xE0, 0x03, 0x81, 0xC0,\n  0x00, 0xE1, 0xC0, 0x18, 0x38, 0xE0, 0x3F, 0xCC, 0xE0, 0x3C, 0xE7, 0x70,\n  0x3C, 0x71, 0xF0, 0x1C, 0x30, 0xF8, 0x1E, 0x38, 0x7C, 0x0E, 0x1C, 0x3E,\n  0x0F, 0x0E, 0x1F, 0x07, 0x0E, 0x0F, 0x83, 0x87, 0x0D, 0xC1, 0xC7, 0x86,\n  0x70, 0xE5, 0xC6, 0x38, 0x7C, 0xFE, 0x1C, 0x1C, 0x3E, 0x07, 0x00, 0x00,\n  0x01, 0xC0, 0x00, 0x00, 0x78, 0x00, 0x40, 0x1F, 0x00, 0xE0, 0x03, 0xFF,\n  0xE0, 0x00, 0x3F, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x03, 0x00, 0x00,\n  0x0E, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x7C, 0x00, 0x00, 0xF8, 0x00, 0x03,\n  0xF0, 0x00, 0x0F, 0xE0, 0x00, 0x17, 0xC0, 0x00, 0x67, 0x80, 0x00, 0x8F,\n  0x00, 0x03, 0x1F, 0x00, 0x0C, 0x3E, 0x00, 0x10, 0x7C, 0x00, 0x60, 0xF8,\n  0x00, 0x81, 0xF0, 0x03, 0xFF, 0xE0, 0x0F, 0xFF, 0xE0, 0x18, 0x07, 0xC0,\n  0x60, 0x0F, 0x81, 0xC0, 0x1F, 0x03, 0x00, 0x3E, 0x0E, 0x00, 0x7C, 0x3C,\n  0x00, 0xFC, 0xFE, 0x0F, 0xFE, 0x07, 0xFF, 0xE0, 0x01, 0xFF, 0xFC, 0x01,\n  0xF8, 0x7E, 0x01, 0xF8, 0x3F, 0x01, 0xF0, 0x3F, 0x01, 0xF0, 0x3F, 0x01,\n  0xF0, 0x3F, 0x03, 0xE0, 0x3F, 0x03, 0xE0, 0x7E, 0x03, 0xE0, 0xFC, 0x03,\n  0xE3, 0xF0, 0x07, 0xFF, 0x80, 0x07, 0xC3, 0xE0, 0x07, 0xC1, 0xF8, 0x0F,\n  0xC0, 0xF8, 0x0F, 0x80, 0xFC, 0x0F, 0x80, 0xFC, 0x0F, 0x80, 0xFC, 0x1F,\n  0x80, 0xFC, 0x1F, 0x01, 0xFC, 0x1F, 0x01, 0xF8, 0x1F, 0x03, 0xF0, 0x3F,\n  0x0F, 0xE0, 0x7F, 0xFF, 0xC0, 0xFF, 0xFE, 0x00, 0x00, 0x1F, 0x82, 0x01,\n  0xFF, 0xE8, 0x07, 0xE0, 0xF0, 0x3F, 0x80, 0xE0, 0xFE, 0x00, 0xC1, 0xF8,\n  0x01, 0x87, 0xE0, 0x02, 0x1F, 0x80, 0x04, 0x3F, 0x00, 0x00, 0xFC, 0x00,\n  0x01, 0xF8, 0x00, 0x07, 0xF0, 0x00, 0x0F, 0xE0, 0x00, 0x1F, 0x80, 0x00,\n  0x3F, 0x00, 0x00, 0x7E, 0x00, 0x00, 0xFC, 0x00, 0x01, 0xF8, 0x00, 0x03,\n  0xF0, 0x00, 0x03, 0xE0, 0x01, 0x07, 0xE0, 0x06, 0x07, 0xE0, 0x18, 0x07,\n  0xE0, 0xE0, 0x07, 0xFF, 0x00, 0x01, 0xF8, 0x00, 0x07, 0xFF, 0xE0, 0x01,\n  0xFF, 0xFE, 0x00, 0x1F, 0x87, 0xE0, 0x07, 0xE0, 0x7C, 0x01, 0xF0, 0x1F,\n  0x80, 0x7C, 0x03, 0xE0, 0x1F, 0x00, 0xF8, 0x0F, 0x80, 0x3F, 0x03, 0xE0,\n  0x0F, 0xC0, 0xF8, 0x03, 0xF0, 0x3E, 0x00, 0xFC, 0x1F, 0x00, 0x3F, 0x07,\n  0xC0, 0x0F, 0xC1, 0xF0, 0x07, 0xF0, 0xFC, 0x01, 0xF8, 0x3E, 0x00, 0x7E,\n  0x0F, 0x80, 0x3F, 0x83, 0xE0, 0x0F, 0xC1, 0xF8, 0x07, 0xF0, 0x7C, 0x01,\n  0xF8, 0x1F, 0x00, 0xFC, 0x07, 0xC0, 0x7E, 0x03, 0xF0, 0x7E, 0x01, 0xFF,\n  0xFF, 0x00, 0xFF, 0xFE, 0x00, 0x00, 0x07, 0xFF, 0xFE, 0x03, 0xFF, 0xFC,\n  0x07, 0xE0, 0x78, 0x0F, 0xC0, 0x60, 0x1F, 0x00, 0x40, 0x3E, 0x00, 0x80,\n  0x7C, 0x01, 0x01, 0xF8, 0x10, 0x03, 0xE0, 0x60, 0x07, 0xC3, 0x80, 0x0F,\n  0xFF, 0x00, 0x3F, 0xFE, 0x00, 0x7C, 0x38, 0x00, 0xF8, 0x30, 0x03, 0xF0,\n  0x60, 0x07, 0xC0, 0x80, 0x0F, 0x81, 0x00, 0x1F, 0x00, 0x10, 0x7E, 0x00,\n  0x60, 0xF8, 0x01, 0xC1, 0xF0, 0x07, 0x03, 0xE0, 0x1E, 0x0F, 0xC0, 0xFC,\n  0x3F, 0xFF, 0xF8, 0xFF, 0xFF, 0xE0, 0x07, 0xFF, 0xFE, 0x03, 0xFF, 0xFC,\n  0x07, 0xE0, 0x78, 0x0F, 0xC0, 0x60, 0x1F, 0x00, 0x40, 0x3E, 0x00, 0x80,\n  0x7C, 0x01, 0x01, 0xF8, 0x20, 0x03, 0xE0, 0xC0, 0x07, 0xC3, 0x80, 0x0F,\n  0xFE, 0x00, 0x3F, 0xFC, 0x00, 0x7C, 0x38, 0x00, 0xF8, 0x30, 0x03, 0xF0,\n  0x60, 0x07, 0xC0, 0x80, 0x0F, 0x81, 0x00, 0x1F, 0x00, 0x00, 0x7E, 0x00,\n  0x00, 0xF8, 0x00, 0x01, 0xF0, 0x00, 0x03, 0xE0, 0x00, 0x0F, 0xC0, 0x00,\n  0x3F, 0x80, 0x00, 0xFF, 0xC0, 0x00, 0x00, 0x1F, 0xC2, 0x00, 0xFF, 0xF6,\n  0x01, 0xF8, 0x3C, 0x03, 0xE0, 0x1C, 0x0F, 0xC0, 0x0C, 0x0F, 0xC0, 0x08,\n  0x1F, 0x80, 0x08, 0x3F, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x7E, 0x00, 0x00,\n  0x7E, 0x00, 0x00, 0x7E, 0x00, 0x00, 0xFE, 0x00, 0x00, 0xFC, 0x03, 0xFF,\n  0xFC, 0x00, 0xFC, 0xFC, 0x00, 0xF8, 0xFC, 0x00, 0xF8, 0xFC, 0x00, 0xF8,\n  0xFC, 0x00, 0xF0, 0x7C, 0x01, 0xF0, 0x7E, 0x01, 0xF0, 0x3E, 0x01, 0xF0,\n  0x1F, 0x83, 0xE0, 0x0F, 0xFF, 0x80, 0x01, 0xFC, 0x00, 0x07, 0xFF, 0x3F,\n  0xF8, 0x0F, 0xE0, 0x7F, 0x00, 0x7E, 0x01, 0xF8, 0x03, 0xF0, 0x0F, 0x80,\n  0x1F, 0x00, 0x7C, 0x00, 0xF8, 0x07, 0xE0, 0x07, 0xC0, 0x3E, 0x00, 0x7E,\n  0x01, 0xF0, 0x03, 0xE0, 0x0F, 0x80, 0x1F, 0x00, 0xF8, 0x00, 0xF8, 0x07,\n  0xC0, 0x0F, 0xFF, 0xFE, 0x00, 0x7F, 0xFF, 0xF0, 0x03, 0xE0, 0x1F, 0x00,\n  0x3F, 0x00, 0xF8, 0x01, 0xF0, 0x07, 0xC0, 0x0F, 0x80, 0x7E, 0x00, 0x7C,\n  0x03, 0xE0, 0x07, 0xE0, 0x1F, 0x00, 0x3E, 0x00, 0xF8, 0x01, 0xF0, 0x0F,\n  0xC0, 0x0F, 0x80, 0x7C, 0x00, 0xFC, 0x03, 0xE0, 0x0F, 0xE0, 0x3F, 0x80,\n  0xFF, 0xC7, 0xFF, 0x00, 0x07, 0xFE, 0x03, 0xF8, 0x07, 0xE0, 0x0F, 0xC0,\n  0x1F, 0x00, 0x3E, 0x00, 0x7C, 0x01, 0xF0, 0x03, 0xE0, 0x07, 0xC0, 0x0F,\n  0x80, 0x3E, 0x00, 0x7C, 0x00, 0xF8, 0x03, 0xF0, 0x07, 0xC0, 0x0F, 0x80,\n  0x1F, 0x00, 0x7C, 0x00, 0xF8, 0x01, 0xF0, 0x03, 0xE0, 0x0F, 0xC0, 0x3F,\n  0x80, 0xFF, 0xC0, 0x00, 0x3F, 0xF0, 0x01, 0xFE, 0x00, 0x0F, 0xC0, 0x00,\n  0xF8, 0x00, 0x0F, 0x80, 0x00, 0xF8, 0x00, 0x1F, 0x80, 0x01, 0xF0, 0x00,\n  0x1F, 0x00, 0x01, 0xF0, 0x00, 0x3E, 0x00, 0x03, 0xE0, 0x00, 0x3E, 0x00,\n  0x07, 0xE0, 0x00, 0x7C, 0x00, 0x07, 0xC0, 0x00, 0x7C, 0x00, 0x0F, 0xC0,\n  0x00, 0xF8, 0x00, 0x0F, 0x80, 0x00, 0xF8, 0x00, 0x1F, 0x00, 0x61, 0xF0,\n  0x0F, 0x3F, 0x00, 0xE7, 0xE0, 0x07, 0xFC, 0x00, 0x3F, 0x00, 0x00, 0x07,\n  0xFF, 0x3F, 0x80, 0xFE, 0x07, 0x80, 0x7E, 0x03, 0x00, 0x3F, 0x03, 0x00,\n  0x1F, 0x03, 0x00, 0x0F, 0x83, 0x00, 0x07, 0xC3, 0x00, 0x07, 0xE3, 0x00,\n  0x03, 0xE3, 0x00, 0x01, 0xF3, 0x00, 0x00, 0xFB, 0x80, 0x00, 0xFB, 0xC0,\n  0x00, 0x7F, 0xE0, 0x00, 0x3E, 0xF8, 0x00, 0x3F, 0x7C, 0x00, 0x1F, 0x1F,\n  0x00, 0x0F, 0x8F, 0x80, 0x07, 0xC7, 0xE0, 0x07, 0xE1, 0xF0, 0x03, 0xE0,\n  0xFC, 0x01, 0xF0, 0x3E, 0x00, 0xF8, 0x1F, 0x00, 0xFC, 0x07, 0xC0, 0xFE,\n  0x07, 0xF0, 0xFF, 0xCF, 0xFC, 0x00, 0x07, 0xFF, 0x00, 0x07, 0xF0, 0x00,\n  0x1F, 0x80, 0x00, 0x7E, 0x00, 0x01, 0xF0, 0x00, 0x07, 0xC0, 0x00, 0x1F,\n  0x00, 0x00, 0xF8, 0x00, 0x03, 0xE0, 0x00, 0x0F, 0x80, 0x00, 0x3E, 0x00,\n  0x01, 0xF0, 0x00, 0x07, 0xC0, 0x00, 0x1F, 0x00, 0x00, 0xFC, 0x00, 0x03,\n  0xE0, 0x00, 0x0F, 0x80, 0x00, 0x3E, 0x00, 0x11, 0xF0, 0x00, 0xC7, 0xC0,\n  0x06, 0x1F, 0x00, 0x38, 0x7C, 0x01, 0xE3, 0xF0, 0x3F, 0x9F, 0xFF, 0xFC,\n  0xFF, 0xFF, 0xF0, 0x07, 0xF8, 0x00, 0x7F, 0x80, 0xFC, 0x00, 0x3F, 0x80,\n  0x3E, 0x00, 0x3F, 0x80, 0x1F, 0x00, 0x3F, 0x80, 0x1F, 0x80, 0x1F, 0xC0,\n  0x0F, 0xE0, 0x1B, 0xE0, 0x07, 0xF0, 0x0D, 0xF0, 0x02, 0xF8, 0x0D, 0xF0,\n  0x03, 0x7C, 0x0C, 0xF8, 0x01, 0xBE, 0x06, 0x7C, 0x00, 0xDF, 0x06, 0x7C,\n  0x00, 0xCF, 0x83, 0x3E, 0x00, 0x67, 0xC3, 0x1F, 0x00, 0x31, 0xE3, 0x0F,\n  0x80, 0x38, 0xF9, 0x8F, 0x80, 0x18, 0x7D, 0x87, 0xC0, 0x0C, 0x3F, 0x83,\n  0xE0, 0x06, 0x1F, 0xC1, 0xF0, 0x06, 0x0F, 0xC1, 0xF0, 0x03, 0x07, 0xC0,\n  0xF8, 0x01, 0x83, 0xE0, 0x7C, 0x01, 0xC0, 0xE0, 0x7E, 0x00, 0xE0, 0x70,\n  0x3F, 0x00, 0xF8, 0x30, 0x3F, 0x80, 0xFF, 0x10, 0x7F, 0xF0, 0x00, 0x07,\n  0xF0, 0x0F, 0xE0, 0x3E, 0x00, 0x78, 0x07, 0xE0, 0x06, 0x00, 0x7C, 0x00,\n  0xC0, 0x1F, 0xC0, 0x10, 0x03, 0xF8, 0x06, 0x00, 0x6F, 0x80, 0xC0, 0x19,\n  0xF0, 0x10, 0x03, 0x3F, 0x02, 0x00, 0x63, 0xE0, 0xC0, 0x0C, 0x7C, 0x18,\n  0x03, 0x07, 0xC2, 0x00, 0x60, 0xF8, 0x40, 0x0C, 0x0F, 0x98, 0x03, 0x81,\n  0xF3, 0x00, 0x60, 0x3F, 0x40, 0x0C, 0x03, 0xF8, 0x01, 0x80, 0x7F, 0x00,\n  0x60, 0x07, 0xC0, 0x0C, 0x00, 0xF8, 0x01, 0x80, 0x0F, 0x00, 0x70, 0x01,\n  0xE0, 0x0E, 0x00, 0x18, 0x03, 0xE0, 0x03, 0x00, 0x02, 0x00, 0x60, 0x00,\n  0x00, 0x1F, 0xC0, 0x00, 0xFF, 0xC0, 0x07, 0xC3, 0xE0, 0x1F, 0x03, 0xC0,\n  0x7C, 0x03, 0xC1, 0xF0, 0x07, 0x87, 0xE0, 0x0F, 0x8F, 0x80, 0x1F, 0x3F,\n  0x00, 0x3E, 0x7C, 0x00, 0x7D, 0xF8, 0x01, 0xFB, 0xE0, 0x03, 0xF7, 0xC0,\n  0x07, 0xDF, 0x80, 0x1F, 0xBF, 0x00, 0x3F, 0x7C, 0x00, 0x7C, 0xF8, 0x01,\n  0xF9, 0xF0, 0x03, 0xE3, 0xE0, 0x0F, 0xC7, 0xC0, 0x1F, 0x07, 0x80, 0x7C,\n  0x0F, 0x81, 0xF0, 0x0F, 0x87, 0xC0, 0x0F, 0xFE, 0x00, 0x07, 0xF0, 0x00,\n  0x07, 0xFF, 0xE0, 0x03, 0xFF, 0xF0, 0x07, 0xE3, 0xF0, 0x0F, 0x83, 0xE0,\n  0x1F, 0x07, 0xE0, 0x3E, 0x0F, 0xC0, 0x7C, 0x1F, 0x81, 0xF0, 0x3F, 0x03,\n  0xE0, 0xFE, 0x07, 0xC1, 0xF8, 0x0F, 0x87, 0xF0, 0x3E, 0x1F, 0xC0, 0x7F,\n  0xFE, 0x00, 0xFF, 0xF0, 0x03, 0xE0, 0x00, 0x07, 0xC0, 0x00, 0x0F, 0x80,\n  0x00, 0x1F, 0x00, 0x00, 0x7C, 0x00, 0x00, 0xF8, 0x00, 0x01, 0xF0, 0x00,\n  0x03, 0xE0, 0x00, 0x0F, 0xC0, 0x00, 0x3F, 0x80, 0x00, 0xFF, 0xC0, 0x00,\n  0x00, 0x1F, 0xC0, 0x00, 0xFF, 0xC0, 0x07, 0xC3, 0xE0, 0x1F, 0x03, 0xC0,\n  0x7C, 0x03, 0xC1, 0xF0, 0x07, 0x87, 0xE0, 0x0F, 0x8F, 0x80, 0x1F, 0x3F,\n  0x00, 0x3E, 0x7C, 0x00, 0x7D, 0xF8, 0x01, 0xFB, 0xF0, 0x03, 0xF7, 0xC0,\n  0x07, 0xDF, 0x80, 0x0F, 0xBF, 0x00, 0x3F, 0x7C, 0x00, 0x7C, 0xF8, 0x01,\n  0xF9, 0xF0, 0x03, 0xE3, 0xE0, 0x07, 0xC7, 0xC0, 0x1F, 0x07, 0x80, 0x7C,\n  0x0F, 0x01, 0xF0, 0x0F, 0x07, 0x80, 0x07, 0xFE, 0x00, 0x03, 0x80, 0x00,\n  0x0C, 0x00, 0x00, 0x3C, 0x00, 0x20, 0xFF, 0xC1, 0x87, 0xFF, 0xFE, 0x1E,\n  0xFF, 0xF8, 0x00, 0x1F, 0xC0, 0x00, 0x07, 0xFF, 0xE0, 0x01, 0xFF, 0xFC,\n  0x01, 0xF8, 0x7E, 0x01, 0xF8, 0x3F, 0x01, 0xF8, 0x3F, 0x01, 0xF0, 0x3F,\n  0x01, 0xF0, 0x3F, 0x03, 0xF0, 0x3F, 0x03, 0xE0, 0x7E, 0x03, 0xE0, 0xFE,\n  0x03, 0xE1, 0xF8, 0x07, 0xFF, 0xF0, 0x07, 0xFF, 0x80, 0x07, 0xDF, 0xC0,\n  0x0F, 0xCF, 0xC0, 0x0F, 0xCF, 0xC0, 0x0F, 0x8F, 0xE0, 0x0F, 0x87, 0xE0,\n  0x1F, 0x87, 0xE0, 0x1F, 0x03, 0xF0, 0x1F, 0x03, 0xF0, 0x1F, 0x03, 0xF0,\n  0x3F, 0x01, 0xF8, 0x7F, 0x01, 0xF8, 0xFF, 0xE1, 0xFE, 0x00, 0xF8, 0x40,\n  0xFF, 0xB0, 0x38, 0x3C, 0x1C, 0x07, 0x0F, 0x01, 0xC3, 0xC0, 0x20, 0xF0,\n  0x08, 0x3E, 0x02, 0x0F, 0xC0, 0x03, 0xF8, 0x00, 0x7F, 0x00, 0x0F, 0xE0,\n  0x01, 0xFC, 0x00, 0x3F, 0x80, 0x07, 0xE0, 0x00, 0xFC, 0x00, 0x1F, 0x00,\n  0x03, 0xC4, 0x00, 0xF1, 0x00, 0x3C, 0x60, 0x0F, 0x38, 0x07, 0x8F, 0x83,\n  0xC2, 0x3F, 0xE0, 0x83, 0xF0, 0x00, 0x3F, 0xFF, 0xF9, 0xFF, 0xFF, 0xCF,\n  0x1F, 0x1E, 0x70, 0xF8, 0x77, 0x0F, 0x83, 0x30, 0x7C, 0x09, 0x03, 0xE0,\n  0x40, 0x3F, 0x02, 0x01, 0xF0, 0x00, 0x0F, 0x80, 0x00, 0x7C, 0x00, 0x07,\n  0xC0, 0x00, 0x3E, 0x00, 0x01, 0xF0, 0x00, 0x0F, 0x80, 0x00, 0xF8, 0x00,\n  0x07, 0xC0, 0x00, 0x3E, 0x00, 0x03, 0xF0, 0x00, 0x1F, 0x00, 0x00, 0xF8,\n  0x00, 0x07, 0xC0, 0x00, 0x7E, 0x00, 0x07, 0xF0, 0x00, 0xFF, 0xF0, 0x00,\n  0x7F, 0xF0, 0xFF, 0x1F, 0xC0, 0x3E, 0x1F, 0x80, 0x1C, 0x1F, 0x80, 0x18,\n  0x1F, 0x00, 0x18, 0x1F, 0x00, 0x18, 0x1F, 0x00, 0x30, 0x3F, 0x00, 0x30,\n  0x3E, 0x00, 0x30, 0x3E, 0x00, 0x30, 0x7E, 0x00, 0x60, 0x7C, 0x00, 0x60,\n  0x7C, 0x00, 0x60, 0x7C, 0x00, 0xC0, 0x7C, 0x00, 0xC0, 0xF8, 0x00, 0xC0,\n  0xF8, 0x00, 0xC0, 0xF8, 0x01, 0x80, 0xF8, 0x01, 0x80, 0xF8, 0x03, 0x80,\n  0xF8, 0x03, 0x00, 0x7C, 0x06, 0x00, 0x7E, 0x1E, 0x00, 0x3F, 0xF8, 0x00,\n  0x0F, 0xE0, 0x00, 0xFF, 0xE0, 0x7F, 0x3F, 0x80, 0x1C, 0x1F, 0x80, 0x18,\n  0x1F, 0x80, 0x18, 0x1F, 0x80, 0x30, 0x1F, 0x80, 0x30, 0x0F, 0x80, 0x60,\n  0x0F, 0x80, 0x40, 0x0F, 0x80, 0xC0, 0x0F, 0x81, 0x80, 0x0F, 0x81, 0x00,\n  0x0F, 0xC3, 0x00, 0x0F, 0xC6, 0x00, 0x07, 0xC6, 0x00, 0x07, 0xCC, 0x00,\n  0x07, 0xC8, 0x00, 0x07, 0xD8, 0x00, 0x07, 0xF0, 0x00, 0x07, 0xF0, 0x00,\n  0x07, 0xE0, 0x00, 0x03, 0xC0, 0x00, 0x03, 0xC0, 0x00, 0x03, 0x80, 0x00,\n  0x03, 0x00, 0x00, 0x03, 0x00, 0x00, 0xFF, 0xCF, 0xF8, 0x7E, 0x7F, 0x07,\n  0xE0, 0x38, 0x7C, 0x07, 0x80, 0x60, 0xF8, 0x0F, 0x00, 0x81, 0xF0, 0x1E,\n  0x03, 0x03, 0xE0, 0x3E, 0x04, 0x07, 0xE0, 0xFC, 0x18, 0x07, 0xC1, 0xF8,\n  0x20, 0x0F, 0x87, 0xF0, 0xC0, 0x1F, 0x0B, 0xE1, 0x00, 0x3E, 0x37, 0xC6,\n  0x00, 0x7C, 0x47, 0x88, 0x00, 0xF9, 0x8F, 0x30, 0x01, 0xF2, 0x1F, 0x40,\n  0x03, 0xEC, 0x3E, 0x80, 0x03, 0xF0, 0x7F, 0x00, 0x07, 0xE0, 0xFC, 0x00,\n  0x0F, 0x81, 0xF8, 0x00, 0x1F, 0x03, 0xE0, 0x00, 0x3C, 0x07, 0xC0, 0x00,\n  0x78, 0x07, 0x00, 0x00, 0xF0, 0x0E, 0x00, 0x00, 0xC0, 0x18, 0x00, 0x01,\n  0x80, 0x30, 0x00, 0x02, 0x00, 0x40, 0x00, 0x0F, 0xFE, 0x3F, 0x81, 0xFC,\n  0x07, 0x80, 0x7C, 0x03, 0x00, 0x3F, 0x03, 0x00, 0x0F, 0x83, 0x80, 0x07,\n  0xC1, 0x80, 0x03, 0xE1, 0x80, 0x00, 0xF9, 0x80, 0x00, 0x7D, 0x80, 0x00,\n  0x3F, 0x80, 0x00, 0x0F, 0x80, 0x00, 0x07, 0xC0, 0x00, 0x03, 0xE0, 0x00,\n  0x01, 0xF8, 0x00, 0x01, 0xFC, 0x00, 0x00, 0xBE, 0x00, 0x00, 0xCF, 0x00,\n  0x00, 0xC7, 0xC0, 0x00, 0xC3, 0xE0, 0x00, 0xC1, 0xF0, 0x00, 0xC0, 0x7C,\n  0x00, 0xE0, 0x3E, 0x00, 0xE0, 0x1F, 0x00, 0xF8, 0x1F, 0xE0, 0xFF, 0x1F,\n  0xF8, 0x00, 0xFF, 0xC3, 0xF9, 0xF8, 0x07, 0x87, 0xC0, 0x38, 0x3E, 0x01,\n  0x81, 0xF0, 0x18, 0x07, 0xC0, 0x80, 0x3E, 0x0C, 0x01, 0xF0, 0xC0, 0x07,\n  0xC4, 0x00, 0x3E, 0x60, 0x01, 0xF6, 0x00, 0x07, 0xA0, 0x00, 0x3F, 0x00,\n  0x01, 0xF0, 0x00, 0x0F, 0x80, 0x00, 0xFC, 0x00, 0x07, 0xC0, 0x00, 0x3E,\n  0x00, 0x01, 0xF0, 0x00, 0x1F, 0x00, 0x00, 0xF8, 0x00, 0x07, 0xC0, 0x00,\n  0x7E, 0x00, 0x07, 0xF0, 0x00, 0xFF, 0xF0, 0x00, 0x07, 0xFF, 0xF8, 0x3F,\n  0xFF, 0xC3, 0xE0, 0x7E, 0x1C, 0x07, 0xE0, 0xC0, 0x3E, 0x0C, 0x03, 0xF0,\n  0x40, 0x3F, 0x00, 0x03, 0xF0, 0x00, 0x1F, 0x80, 0x01, 0xF8, 0x00, 0x1F,\n  0x80, 0x00, 0xF8, 0x00, 0x0F, 0xC0, 0x00, 0xFC, 0x00, 0x0F, 0xC0, 0x00,\n  0x7E, 0x00, 0x07, 0xE0, 0x00, 0x7E, 0x00, 0x83, 0xE0, 0x0C, 0x3F, 0x00,\n  0xC3, 0xF0, 0x0E, 0x1F, 0x00, 0xF1, 0xF8, 0x1F, 0x9F, 0xFF, 0xF8, 0xFF,\n  0xFF, 0xC0, 0x01, 0xFC, 0x0F, 0xE0, 0x3C, 0x00, 0xE0, 0x03, 0x80, 0x1E,\n  0x00, 0x78, 0x01, 0xC0, 0x07, 0x00, 0x3C, 0x00, 0xF0, 0x03, 0x80, 0x0E,\n  0x00, 0x38, 0x01, 0xE0, 0x07, 0x00, 0x1C, 0x00, 0x70, 0x03, 0xC0, 0x0F,\n  0x00, 0x38, 0x00, 0xE0, 0x07, 0x80, 0x1E, 0x00, 0x70, 0x01, 0xC0, 0x0F,\n  0x00, 0x3C, 0x00, 0xFF, 0x03, 0xF8, 0x00, 0xE0, 0x38, 0x07, 0x01, 0xC0,\n  0x70, 0x0C, 0x03, 0x80, 0xE0, 0x38, 0x07, 0x01, 0xC0, 0x70, 0x0C, 0x03,\n  0x80, 0xE0, 0x38, 0x07, 0x01, 0xC0, 0x70, 0x0C, 0x03, 0x80, 0xE0, 0x38,\n  0x07, 0x01, 0xC0, 0x03, 0xFC, 0x0F, 0xF0, 0x03, 0x80, 0x0E, 0x00, 0x38,\n  0x01, 0xE0, 0x07, 0x80, 0x1C, 0x00, 0x70, 0x03, 0xC0, 0x0F, 0x00, 0x38,\n  0x00, 0xE0, 0x07, 0x80, 0x1E, 0x00, 0x70, 0x01, 0xC0, 0x0F, 0x00, 0x3C,\n  0x00, 0xE0, 0x03, 0x80, 0x0E, 0x00, 0x78, 0x01, 0xE0, 0x07, 0x00, 0x1C,\n  0x00, 0xF0, 0x03, 0xC0, 0xFE, 0x03, 0xF8, 0x00, 0x03, 0xC0, 0x03, 0xC0,\n  0x07, 0xE0, 0x07, 0xE0, 0x0E, 0x70, 0x0E, 0x70, 0x1C, 0x78, 0x1C, 0x38,\n  0x3C, 0x3C, 0x38, 0x1C, 0x78, 0x1E, 0x70, 0x0E, 0xF0, 0x0E, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xE1, 0xE3, 0xC1, 0xC1, 0xC0, 0xC0, 0x00,\n  0xF7, 0x80, 0xFD, 0xE0, 0x7C, 0xF0, 0x3C, 0x3C, 0x1E, 0x0F, 0x0F, 0x83,\n  0x83, 0xC1, 0xE1, 0xE0, 0x78, 0x78, 0x1C, 0x3E, 0x0F, 0x0F, 0x03, 0xC3,\n  0xC1, 0xF0, 0xF0, 0xFC, 0xFE, 0x6F, 0x6F, 0xF3, 0xF1, 0xF8, 0xF8, 0x3C,\n  0x1C, 0x00, 0x01, 0xE0, 0x1F, 0xC0, 0x07, 0xC0, 0x07, 0xC0, 0x07, 0x80,\n  0x07, 0x80, 0x0F, 0x80, 0x0F, 0x00, 0x0F, 0x00, 0x0F, 0x3C, 0x1E, 0xFE,\n  0x1F, 0x9F, 0x1F, 0x0F, 0x1E, 0x0F, 0x3E, 0x0F, 0x3C, 0x0F, 0x3C, 0x1F,\n  0x78, 0x1E, 0x78, 0x1E, 0x78, 0x3C, 0x78, 0x3C, 0xF0, 0x78, 0xF0, 0xF0,\n  0xF1, 0xE0, 0x7F, 0xC0, 0x3F, 0x00, 0x01, 0xF0, 0x3F, 0xC3, 0xCE, 0x3C,\n  0xF3, 0xC7, 0x1E, 0x01, 0xE0, 0x0F, 0x00, 0xF8, 0x07, 0x80, 0x3C, 0x01,\n  0xE0, 0x0F, 0x03, 0x78, 0x31, 0xE3, 0x0F, 0xF0, 0x1E, 0x00, 0x00, 0x1F,\n  0xC0, 0x00, 0xF8, 0x00, 0x1F, 0x00, 0x03, 0xE0, 0x00, 0x78, 0x00, 0x0F,\n  0x00, 0x03, 0xE0, 0x00, 0x7C, 0x01, 0xEF, 0x00, 0x7F, 0xE0, 0x3E, 0x7C,\n  0x07, 0x8F, 0x01, 0xE1, 0xE0, 0x78, 0x3C, 0x0F, 0x0F, 0x83, 0xC1, 0xE0,\n  0x78, 0x3C, 0x1E, 0x0F, 0x83, 0xC1, 0xF0, 0x78, 0x7C, 0x0F, 0x0F, 0x91,\n  0xE3, 0xF6, 0x3F, 0xDF, 0x83, 0xF3, 0xE0, 0x3C, 0x38, 0x00, 0x01, 0xE0,\n  0x3F, 0x83, 0xCE, 0x3C, 0x73, 0xC3, 0x9E, 0x1D, 0xE1, 0xCF, 0x1C, 0xFB,\n  0xC7, 0xF8, 0x3C, 0x01, 0xE0, 0x0F, 0x02, 0x78, 0x31, 0xE3, 0x0F, 0xF0,\n  0x1E, 0x00, 0x00, 0x01, 0xF0, 0x00, 0x1D, 0xC0, 0x01, 0xCE, 0x00, 0x1C,\n  0x70, 0x01, 0xE0, 0x00, 0x0F, 0x00, 0x00, 0x78, 0x00, 0x07, 0x80, 0x00,\n  0x3C, 0x00, 0x0F, 0xFC, 0x00, 0x7F, 0xE0, 0x00, 0xF0, 0x00, 0x07, 0x80,\n  0x00, 0x3C, 0x00, 0x03, 0xE0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00, 0x07,\n  0x80, 0x00, 0x7C, 0x00, 0x03, 0xC0, 0x00, 0x1E, 0x00, 0x00, 0xF0, 0x00,\n  0x07, 0x80, 0x00, 0x78, 0x00, 0x03, 0xC0, 0x00, 0x1E, 0x00, 0x00, 0xE0,\n  0x00, 0x0F, 0x00, 0x0E, 0x70, 0x00, 0x77, 0x80, 0x03, 0xF8, 0x00, 0x0F,\n  0x80, 0x00, 0x00, 0xFE, 0x00, 0x7F, 0xFC, 0x1F, 0x1F, 0x87, 0xC3, 0xC1,\n  0xF0, 0x78, 0x3C, 0x1F, 0x07, 0x83, 0xE0, 0xF0, 0xF8, 0x0E, 0x3E, 0x01,\n  0xFF, 0x80, 0x3F, 0xC0, 0x0C, 0x00, 0x03, 0xC0, 0x00, 0x7F, 0x80, 0x0F,\n  0xFE, 0x00, 0x7F, 0xF0, 0x70, 0xFF, 0x1C, 0x03, 0xE3, 0x80, 0x3C, 0x70,\n  0x07, 0x0F, 0x03, 0xE0, 0xFF, 0xF0, 0x07, 0xF0, 0x00, 0x1F, 0xC0, 0x03,\n  0xE0, 0x00, 0xF0, 0x00, 0xF8, 0x00, 0x78, 0x00, 0x3C, 0x00, 0x1E, 0x00,\n  0x1F, 0x00, 0x0F, 0x0E, 0x07, 0x9F, 0x83, 0xDF, 0xC3, 0xE9, 0xE1, 0xE8,\n  0xF0, 0xF8, 0xF8, 0x7C, 0x78, 0x7C, 0x3C, 0x3E, 0x3E, 0x1E, 0x1E, 0x1F,\n  0x0F, 0x0F, 0x0F, 0x87, 0x87, 0xCB, 0xC3, 0xCB, 0xE1, 0xE9, 0xE0, 0xFC,\n  0xF0, 0x38, 0x00, 0x03, 0x03, 0xC1, 0xE0, 0xF0, 0x30, 0x00, 0x00, 0x00,\n  0x07, 0x3F, 0x87, 0x83, 0xC1, 0xE0, 0xF0, 0xF0, 0x78, 0x3C, 0x1E, 0x1E,\n  0x0F, 0x27, 0x17, 0x93, 0xF1, 0xF8, 0x70, 0x00, 0x00, 0x06, 0x00, 0x0F,\n  0x00, 0x0F, 0x00, 0x0F, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0x06, 0x00, 0xFE, 0x00, 0x3E, 0x00, 0x3C, 0x00, 0x3C, 0x00, 0x3C,\n  0x00, 0x7C, 0x00, 0x78, 0x00, 0x78, 0x00, 0x78, 0x00, 0xF8, 0x00, 0xF0,\n  0x00, 0xF0, 0x00, 0xF0, 0x01, 0xF0, 0x01, 0xE0, 0x01, 0xE0, 0x01, 0xE0,\n  0x03, 0xC0, 0xE3, 0xC0, 0xE7, 0x80, 0xFF, 0x00, 0x7C, 0x00, 0x1F, 0xC0,\n  0x03, 0xE0, 0x00, 0xF0, 0x00, 0x78, 0x00, 0x78, 0x00, 0x3C, 0x00, 0x1E,\n  0x00, 0x1F, 0x00, 0x0F, 0x3F, 0x87, 0x87, 0x83, 0xC3, 0x03, 0xE3, 0x01,\n  0xE3, 0x00, 0xF3, 0x00, 0x7B, 0x80, 0x7B, 0xC0, 0x3F, 0xE0, 0x1E, 0xF0,\n  0x1F, 0x78, 0x0F, 0x1E, 0x07, 0x8F, 0x13, 0xC7, 0x93, 0xE1, 0xF9, 0xE0,\n  0xF8, 0xF0, 0x38, 0x00, 0x1F, 0xC0, 0xF8, 0x1F, 0x03, 0xC0, 0x78, 0x1F,\n  0x03, 0xE0, 0x78, 0x0F, 0x01, 0xE0, 0x78, 0x0F, 0x01, 0xE0, 0x3C, 0x0F,\n  0x01, 0xE0, 0x3C, 0x0F, 0x81, 0xE0, 0x3C, 0x8F, 0x31, 0xEC, 0x3F, 0x07,\n  0xC0, 0x70, 0x00, 0x01, 0x87, 0x07, 0x0F, 0xE7, 0xE7, 0xE0, 0xF3, 0xF9,\n  0xF8, 0x3D, 0x9E, 0x9E, 0x0F, 0x47, 0xC7, 0x83, 0xE1, 0xD1, 0xE1, 0xF8,\n  0xF8, 0xF0, 0x7C, 0x3C, 0x3C, 0x1F, 0x0F, 0x1F, 0x0F, 0x87, 0xC7, 0x83,\n  0xE1, 0xE1, 0xE0, 0xF0, 0x78, 0x78, 0x3C, 0x1E, 0x3C, 0x1F, 0x0F, 0x0F,\n  0x27, 0x83, 0xC3, 0xD1, 0xE0, 0xF0, 0xFC, 0xF8, 0x78, 0x1C, 0x00, 0x01,\n  0x8F, 0x0F, 0xE7, 0xE0, 0xF3, 0xF8, 0x3C, 0x9E, 0x0F, 0x47, 0x87, 0xA3,\n  0xC1, 0xE8, 0xF0, 0x7C, 0x3C, 0x1E, 0x1E, 0x0F, 0x87, 0x83, 0xE1, 0xE0,\n  0xF0, 0xF8, 0x3C, 0x3C, 0x1F, 0x0F, 0x27, 0x83, 0xD1, 0xE0, 0xFC, 0x78,\n  0x1C, 0x00, 0x01, 0xF0, 0x0E, 0x30, 0x38, 0x70, 0xF0, 0xF3, 0xC1, 0xE7,\n  0x83, 0xDE, 0x07, 0xBC, 0x1F, 0xF8, 0x3F, 0xE0, 0x7B, 0xC0, 0xF7, 0x83,\n  0xCF, 0x07, 0x9E, 0x1E, 0x1C, 0x38, 0x1C, 0xE0, 0x1F, 0x00, 0x00, 0xE3,\n  0x80, 0xFD, 0xF8, 0x0F, 0xFF, 0x81, 0xE8, 0xF0, 0x3E, 0x1E, 0x07, 0x83,\n  0xC0, 0xF0, 0x78, 0x3E, 0x1F, 0x07, 0x83, 0xC0, 0xF0, 0x78, 0x1E, 0x1F,\n  0x07, 0x83, 0xC0, 0xF0, 0xF8, 0x1E, 0x1E, 0x03, 0xC7, 0x80, 0xFF, 0xE0,\n  0x1E, 0xF0, 0x03, 0xC0, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x03, 0xC0, 0x00,\n  0xF8, 0x00, 0x3F, 0xC0, 0x00, 0x01, 0xEF, 0x07, 0xFF, 0x0F, 0x1E, 0x1E,\n  0x1E, 0x1E, 0x1E, 0x3C, 0x1E, 0x7C, 0x3C, 0x78, 0x3C, 0x78, 0x3C, 0xF0,\n  0x7C, 0xF0, 0x78, 0xF0, 0xF8, 0xF0, 0xF8, 0xF1, 0xF0, 0xFE, 0xF0, 0x7E,\n  0xF0, 0x39, 0xE0, 0x01, 0xE0, 0x01, 0xE0, 0x01, 0xE0, 0x03, 0xC0, 0x03,\n  0xC0, 0x1F, 0xF8, 0x03, 0x9C, 0x7F, 0x7C, 0x3D, 0xF8, 0x7A, 0xE0, 0xF8,\n  0x03, 0xE0, 0x07, 0xC0, 0x0F, 0x00, 0x3E, 0x00, 0x7C, 0x00, 0xF0, 0x01,\n  0xE0, 0x07, 0xC0, 0x0F, 0x00, 0x1E, 0x00, 0x7C, 0x00, 0x07, 0x18, 0xFF,\n  0xC7, 0x1C, 0x70, 0x63, 0x81, 0x1E, 0x08, 0xF8, 0x07, 0xE0, 0x1F, 0x00,\n  0x7C, 0x01, 0xF0, 0x07, 0x84, 0x3C, 0x20, 0xE1, 0x87, 0x1C, 0x70, 0x9E,\n  0x00, 0x00, 0x80, 0x60, 0x30, 0x1C, 0x1F, 0x1F, 0xF7, 0xFC, 0x78, 0x1E,\n  0x07, 0x83, 0xC0, 0xF0, 0x3C, 0x1F, 0x07, 0x81, 0xE0, 0x79, 0x3C, 0x4F,\n  0x23, 0xF0, 0xFC, 0x1C, 0x00, 0x0F, 0x0F, 0x3F, 0x87, 0x8F, 0x83, 0xC7,\n  0xC1, 0xE3, 0xE1, 0xE1, 0xE0, 0xF0, 0xF0, 0x78, 0xF8, 0x78, 0x78, 0x3C,\n  0x3C, 0x3E, 0x1E, 0x1F, 0x1E, 0x1F, 0x0F, 0x17, 0x97, 0x9B, 0xCB, 0xF9,\n  0xF9, 0xF8, 0xF8, 0x78, 0x38, 0x00, 0x18, 0x37, 0xC3, 0xDE, 0x1E, 0x78,\n  0x73, 0xC1, 0x9E, 0x08, 0xF0, 0xC7, 0x84, 0x3C, 0x41, 0xE4, 0x0F, 0x40,\n  0x7C, 0x03, 0xC0, 0x1C, 0x00, 0xC0, 0x04, 0x00, 0x38, 0x10, 0xDF, 0x06,\n  0x3D, 0xE0, 0xC7, 0xBC, 0x38, 0x73, 0xC7, 0x06, 0x79, 0xF0, 0x8F, 0x3E,\n  0x11, 0xEB, 0xC4, 0x3F, 0x79, 0x07, 0xCF, 0x60, 0xF9, 0xE8, 0x1E, 0x3E,\n  0x03, 0x87, 0x80, 0x70, 0xF0, 0x0C, 0x0C, 0x01, 0x01, 0x00, 0x03, 0x83,\n  0x87, 0xF1, 0xF0, 0x3C, 0xF8, 0x0F, 0x60, 0x03, 0xD0, 0x00, 0xF8, 0x00,\n  0x1E, 0x00, 0x07, 0x80, 0x01, 0xE0, 0x00, 0x78, 0x00, 0x1F, 0x00, 0x0F,\n  0xC0, 0x02, 0xF1, 0x39, 0x3C, 0xCF, 0xCF, 0xE3, 0xE1, 0xF0, 0x70, 0x38,\n  0x00, 0x01, 0x83, 0x07, 0xE3, 0xC1, 0xF1, 0xE0, 0x78, 0xF0, 0x3E, 0x18,\n  0x1F, 0x08, 0x07, 0x84, 0x03, 0xC6, 0x01, 0xE2, 0x00, 0xFB, 0x00, 0x3D,\n  0x00, 0x1F, 0x80, 0x0F, 0x80, 0x07, 0xC0, 0x03, 0xC0, 0x01, 0xE0, 0x00,\n  0xE0, 0x00, 0x60, 0x00, 0x60, 0x0E, 0x60, 0x0F, 0xE0, 0x07, 0xE0, 0x01,\n  0xC0, 0x00, 0x1F, 0xFC, 0x3F, 0xF8, 0x7F, 0xE1, 0x81, 0x82, 0x06, 0x00,\n  0x08, 0x00, 0x20, 0x00, 0xC0, 0x03, 0x00, 0x0C, 0x00, 0x10, 0x00, 0x40,\n  0x01, 0x80, 0x07, 0xC0, 0x1F, 0x86, 0x3F, 0x8E, 0xCF, 0x9C, 0x07, 0x30,\n  0x03, 0xC0, 0x00, 0x1E, 0x00, 0xF8, 0x03, 0xC0, 0x0F, 0x00, 0x1E, 0x00,\n  0x38, 0x00, 0xF0, 0x01, 0xE0, 0x03, 0xC0, 0x07, 0x00, 0x1E, 0x00, 0x3C,\n  0x00, 0x78, 0x01, 0xE0, 0x03, 0xC0, 0x1F, 0x00, 0x7E, 0x00, 0x30, 0x00,\n  0x60, 0x00, 0xE0, 0x01, 0xC0, 0x07, 0x80, 0x0F, 0x00, 0x1E, 0x00, 0x38,\n  0x00, 0xF0, 0x01, 0xE0, 0x03, 0xC0, 0x07, 0x00, 0x0E, 0x00, 0x0C, 0x00,\n  0x0F, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xE0,\n  0x00, 0xF0, 0x00, 0x70, 0x00, 0x70, 0x00, 0xE0, 0x01, 0xC0, 0x03, 0x80,\n  0x07, 0x00, 0x1E, 0x00, 0x3C, 0x00, 0x78, 0x00, 0xE0, 0x03, 0xC0, 0x07,\n  0x80, 0x0F, 0x00, 0x1C, 0x00, 0x18, 0x00, 0x10, 0x00, 0xF0, 0x03, 0xF0,\n  0x0F, 0x00, 0x1E, 0x00, 0x38, 0x00, 0xF0, 0x01, 0xE0, 0x03, 0xC0, 0x07,\n  0x00, 0x1E, 0x00, 0x3C, 0x00, 0x70, 0x01, 0xE0, 0x0F, 0x80, 0x7C, 0x00,\n  0x3E, 0x00, 0x7F, 0xC6, 0xFF, 0xFF, 0x61, 0xFE, 0x00, 0x7C };\n\nconst GFXglyph FreeSerifBoldItalic18pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,   9,    0,    1 },   // 0x20 ' '\n  {     0,  11,  25,  14,    2,  -23 },   // 0x21 '!'\n  {    35,  14,  10,  19,    4,  -23 },   // 0x22 '\"'\n  {    53,  20,  25,  17,   -1,  -24 },   // 0x23 '#'\n  {   116,  17,  29,  18,    0,  -25 },   // 0x24 '$'\n  {   178,  27,  25,  29,    1,  -23 },   // 0x25 '%'\n  {   263,  25,  25,  27,    0,  -23 },   // 0x26 '&'\n  {   342,   5,  10,  10,    4,  -23 },   // 0x27 '''\n  {   349,  11,  30,  12,    1,  -23 },   // 0x28 '('\n  {   391,  11,  30,  12,   -2,  -23 },   // 0x29 ')'\n  {   433,  13,  15,  18,    2,  -23 },   // 0x2A '*'\n  {   458,  17,  17,  20,    1,  -16 },   // 0x2B '+'\n  {   495,   7,  11,   9,   -2,   -4 },   // 0x2C ','\n  {   505,   9,   4,  12,    0,   -9 },   // 0x2D '-'\n  {   510,   6,   5,   9,    0,   -3 },   // 0x2E '.'\n  {   514,  14,  25,  12,    0,  -23 },   // 0x2F '/'\n  {   558,  15,  25,  18,    1,  -23 },   // 0x30 '0'\n  {   605,  15,  25,  17,    0,  -23 },   // 0x31 '1'\n  {   652,  16,  25,  18,    0,  -23 },   // 0x32 '2'\n  {   702,  15,  25,  17,    1,  -23 },   // 0x33 '3'\n  {   749,  18,  24,  17,    0,  -23 },   // 0x34 '4'\n  {   803,  17,  25,  18,    0,  -23 },   // 0x35 '5'\n  {   857,  17,  25,  18,    1,  -23 },   // 0x36 '6'\n  {   911,  16,  24,  17,    3,  -23 },   // 0x37 '7'\n  {   959,  17,  25,  18,    0,  -23 },   // 0x38 '8'\n  {  1013,  17,  25,  18,    0,  -23 },   // 0x39 '9'\n  {  1067,  10,  17,   9,    0,  -15 },   // 0x3A ':'\n  {  1089,  11,  22,   9,   -1,  -15 },   // 0x3B ';'\n  {  1120,  18,  19,  20,    1,  -18 },   // 0x3C '<'\n  {  1163,  18,  10,  20,    2,  -13 },   // 0x3D '='\n  {  1186,  18,  19,  20,    2,  -18 },   // 0x3E '>'\n  {  1229,  13,  25,  17,    3,  -23 },   // 0x3F '?'\n  {  1270,  25,  25,  29,    2,  -23 },   // 0x40 '@'\n  {  1349,  23,  25,  24,    0,  -23 },   // 0x41 'A'\n  {  1421,  24,  25,  22,    0,  -23 },   // 0x42 'B'\n  {  1496,  23,  25,  22,    1,  -23 },   // 0x43 'C'\n  {  1568,  26,  25,  25,    0,  -23 },   // 0x44 'D'\n  {  1650,  23,  25,  22,    0,  -23 },   // 0x45 'E'\n  {  1722,  23,  25,  21,    0,  -23 },   // 0x46 'F'\n  {  1794,  24,  25,  25,    2,  -23 },   // 0x47 'G'\n  {  1869,  29,  25,  26,    0,  -23 },   // 0x48 'H'\n  {  1960,  15,  25,  13,    0,  -23 },   // 0x49 'I'\n  {  2007,  20,  27,  17,    0,  -23 },   // 0x4A 'J'\n  {  2075,  25,  25,  23,    0,  -23 },   // 0x4B 'K'\n  {  2154,  22,  25,  21,    0,  -23 },   // 0x4C 'L'\n  {  2223,  33,  25,  31,    0,  -23 },   // 0x4D 'M'\n  {  2327,  27,  25,  25,    0,  -23 },   // 0x4E 'N'\n  {  2412,  23,  25,  24,    1,  -23 },   // 0x4F 'O'\n  {  2484,  23,  25,  21,    0,  -23 },   // 0x50 'P'\n  {  2556,  23,  31,  24,    1,  -23 },   // 0x51 'Q'\n  {  2646,  24,  25,  23,    0,  -23 },   // 0x52 'R'\n  {  2721,  18,  25,  18,    0,  -23 },   // 0x53 'S'\n  {  2778,  21,  25,  21,    3,  -23 },   // 0x54 'T'\n  {  2844,  24,  25,  25,    4,  -23 },   // 0x55 'U'\n  {  2919,  24,  25,  25,    4,  -23 },   // 0x56 'V'\n  {  2994,  31,  25,  32,    4,  -23 },   // 0x57 'W'\n  {  3091,  25,  25,  24,    0,  -23 },   // 0x58 'X'\n  {  3170,  21,  25,  22,    4,  -23 },   // 0x59 'Y'\n  {  3236,  21,  25,  20,    0,  -23 },   // 0x5A 'Z'\n  {  3302,  14,  30,  12,   -1,  -23 },   // 0x5B '['\n  {  3355,  10,  25,  14,    4,  -23 },   // 0x5C '\\'\n  {  3387,  14,  30,  12,   -2,  -23 },   // 0x5D ']'\n  {  3440,  16,  13,  20,    2,  -23 },   // 0x5E '^'\n  {  3466,  18,   3,  17,    0,    3 },   // 0x5F '_'\n  {  3473,   7,   6,  12,    3,  -23 },   // 0x60 '`'\n  {  3479,  18,  17,  18,    0,  -15 },   // 0x61 'a'\n  {  3518,  16,  26,  17,    1,  -24 },   // 0x62 'b'\n  {  3570,  13,  17,  15,    1,  -15 },   // 0x63 'c'\n  {  3598,  19,  25,  18,    1,  -23 },   // 0x64 'd'\n  {  3658,  13,  17,  15,    1,  -15 },   // 0x65 'e'\n  {  3686,  21,  32,  17,   -3,  -24 },   // 0x66 'f'\n  {  3770,  19,  23,  17,   -1,  -15 },   // 0x67 'g'\n  {  3825,  17,  25,  19,    1,  -23 },   // 0x68 'h'\n  {  3879,   9,  25,  10,    1,  -23 },   // 0x69 'i'\n  {  3908,  16,  31,  12,   -3,  -23 },   // 0x6A 'j'\n  {  3970,  17,  25,  18,    1,  -23 },   // 0x6B 'k'\n  {  4024,  11,  25,  10,    1,  -23 },   // 0x6C 'l'\n  {  4059,  26,  17,  27,    0,  -15 },   // 0x6D 'm'\n  {  4115,  18,  17,  18,    0,  -15 },   // 0x6E 'n'\n  {  4154,  15,  17,  17,    1,  -15 },   // 0x6F 'o'\n  {  4186,  19,  23,  17,   -2,  -15 },   // 0x70 'p'\n  {  4241,  16,  23,  17,    1,  -15 },   // 0x71 'q'\n  {  4287,  15,  16,  14,    0,  -15 },   // 0x72 'r'\n  {  4317,  13,  17,  12,    0,  -15 },   // 0x73 's'\n  {  4345,  10,  22,  10,    1,  -20 },   // 0x74 't'\n  {  4373,  17,  17,  19,    1,  -15 },   // 0x75 'u'\n  {  4410,  13,  16,  15,    2,  -15 },   // 0x76 'v'\n  {  4436,  19,  16,  23,    3,  -15 },   // 0x77 'w'\n  {  4474,  18,  17,  17,   -1,  -15 },   // 0x78 'x'\n  {  4513,  17,  23,  15,   -2,  -15 },   // 0x79 'y'\n  {  4562,  15,  19,  14,    0,  -15 },   // 0x7A 'z'\n  {  4598,  15,  32,  12,    0,  -24 },   // 0x7B '{'\n  {  4658,   3,  25,   9,    4,  -23 },   // 0x7C '|'\n  {  4668,  15,  32,  12,   -5,  -24 },   // 0x7D '}'\n  {  4728,  16,   5,  20,    2,  -11 } }; // 0x7E '~'\n\nconst GFXfont FreeSerifBoldItalic18pt7b PROGMEM = {\n  (uint8_t  *)FreeSerifBoldItalic18pt7bBitmaps,\n  (GFXglyph *)FreeSerifBoldItalic18pt7bGlyphs,\n  0x20, 0x7E, 42 };\n\n// Approx. 5410 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeSerifBoldItalic24pt7b.h",
    "content": "const uint8_t FreeSerifBoldItalic24pt7bBitmaps[] PROGMEM = {\n  0x00, 0x3C, 0x00, 0xFC, 0x01, 0xF8, 0x07, 0xF0, 0x0F, 0xE0, 0x1F, 0xC0,\n  0x3F, 0x00, 0x7E, 0x00, 0xF8, 0x01, 0xF0, 0x07, 0xC0, 0x0F, 0x80, 0x1E,\n  0x00, 0x3C, 0x00, 0x70, 0x00, 0xE0, 0x01, 0xC0, 0x03, 0x00, 0x0E, 0x00,\n  0x18, 0x00, 0x30, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0xF0, 0x03, 0xF0, 0x0F, 0xF0, 0x1F, 0xE0, 0x3F, 0xC0, 0x3F, 0x00,\n  0x3C, 0x00, 0x1C, 0x01, 0xC7, 0xC0, 0x7D, 0xF8, 0x1F, 0xBF, 0x03, 0xF7,\n  0xC0, 0x7C, 0xF8, 0x0F, 0x9E, 0x01, 0xE3, 0xC0, 0x3C, 0x70, 0x07, 0x1E,\n  0x00, 0xE3, 0x80, 0x38, 0x70, 0x07, 0x0C, 0x00, 0xC0, 0x00, 0x03, 0xC1,\n  0xE0, 0x00, 0x70, 0x38, 0x00, 0x1E, 0x0F, 0x00, 0x03, 0xC1, 0xE0, 0x00,\n  0x70, 0x38, 0x00, 0x1E, 0x0F, 0x00, 0x03, 0x81, 0xC0, 0x00, 0xF0, 0x78,\n  0x00, 0x1E, 0x0F, 0x00, 0x07, 0x83, 0xC0, 0x1F, 0xFF, 0xFF, 0x83, 0xFF,\n  0xFF, 0xF0, 0x7F, 0xFF, 0xFC, 0x00, 0xE0, 0x70, 0x00, 0x3C, 0x1E, 0x00,\n  0x07, 0x83, 0xC0, 0x00, 0xE0, 0x70, 0x00, 0x3C, 0x1E, 0x00, 0x07, 0x83,\n  0xC0, 0x00, 0xE0, 0x70, 0x07, 0xFF, 0xFF, 0xE0, 0xFF, 0xFF, 0xFC, 0x1F,\n  0xFF, 0xFF, 0x00, 0x38, 0x1C, 0x00, 0x0F, 0x07, 0x80, 0x01, 0xE0, 0xF0,\n  0x00, 0x38, 0x1C, 0x00, 0x0F, 0x07, 0x80, 0x01, 0xC0, 0xE0, 0x00, 0x78,\n  0x3C, 0x00, 0x0F, 0x07, 0x80, 0x01, 0xC0, 0xE0, 0x00, 0x78, 0x3C, 0x00,\n  0x00, 0x00, 0x00, 0xE0, 0x00, 0x00, 0xC0, 0x00, 0x00, 0xC0, 0x00, 0x1F,\n  0xE0, 0x00, 0x7F, 0xF8, 0x01, 0xF1, 0x9E, 0x01, 0xC1, 0x8F, 0x03, 0x83,\n  0x8F, 0x03, 0x83, 0x06, 0x07, 0x83, 0x06, 0x07, 0x87, 0x06, 0x07, 0xC7,\n  0x04, 0x07, 0xE6, 0x04, 0x07, 0xFE, 0x00, 0x03, 0xFE, 0x00, 0x03, 0xFF,\n  0x00, 0x01, 0xFF, 0x80, 0x00, 0xFF, 0xC0, 0x00, 0x7F, 0xE0, 0x00, 0x1F,\n  0xE0, 0x00, 0x1F, 0xF0, 0x00, 0x3F, 0xF0, 0x00, 0x3B, 0xF8, 0x20, 0x31,\n  0xF8, 0x20, 0x30, 0xF8, 0x60, 0x70, 0xF8, 0x60, 0x60, 0xF8, 0x60, 0x60,\n  0xF8, 0xF0, 0xE0, 0xF0, 0xF0, 0xE1, 0xE0, 0x78, 0xC3, 0xE0, 0x3C, 0xC7,\n  0xC0, 0x0F, 0xFF, 0x00, 0x03, 0xFC, 0x00, 0x01, 0x80, 0x00, 0x03, 0x80,\n  0x00, 0x03, 0x80, 0x00, 0x03, 0x00, 0x00, 0x03, 0x00, 0x00, 0x01, 0xF0,\n  0x00, 0x70, 0x00, 0xFF, 0x80, 0x1C, 0x00, 0x3F, 0x38, 0x1F, 0x00, 0x0F,\n  0xC7, 0xFF, 0xE0, 0x03, 0xF0, 0x3F, 0xB8, 0x00, 0x7E, 0x04, 0x07, 0x00,\n  0x1F, 0x80, 0x81, 0xC0, 0x03, 0xF0, 0x10, 0x38, 0x00, 0xFC, 0x02, 0x0E,\n  0x00, 0x1F, 0x80, 0x81, 0x80, 0x03, 0xF0, 0x10, 0x70, 0x00, 0x7C, 0x06,\n  0x1C, 0x00, 0x0F, 0x80, 0x83, 0x80, 0x01, 0xF0, 0x30, 0xE0, 0x00, 0x1E,\n  0x0C, 0x1C, 0x07, 0xC3, 0xE3, 0x07, 0x03, 0xFC, 0x3F, 0xC0, 0xC0, 0xFC,\n  0x43, 0xE0, 0x38, 0x3E, 0x0C, 0x00, 0x0E, 0x0F, 0xC0, 0x80, 0x01, 0xC3,\n  0xF0, 0x10, 0x00, 0x70, 0xFC, 0x02, 0x00, 0x0C, 0x1F, 0x80, 0x40, 0x03,\n  0x83, 0xE0, 0x08, 0x00, 0x60, 0xFC, 0x02, 0x00, 0x1C, 0x1F, 0x80, 0x40,\n  0x07, 0x03, 0xE0, 0x10, 0x00, 0xE0, 0x7C, 0x02, 0x00, 0x38, 0x0F, 0x80,\n  0xC0, 0x06, 0x01, 0xF0, 0x30, 0x01, 0xC0, 0x1F, 0x0C, 0x00, 0x30, 0x01,\n  0xFF, 0x00, 0x0E, 0x00, 0x1F, 0x80, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00,\n  0xFF, 0x80, 0x00, 0x01, 0xF1, 0xE0, 0x00, 0x00, 0xF0, 0x78, 0x00, 0x00,\n  0xF0, 0x3C, 0x00, 0x00, 0x78, 0x1E, 0x00, 0x00, 0x7C, 0x0F, 0x00, 0x00,\n  0x3E, 0x0F, 0x80, 0x00, 0x1F, 0x07, 0x80, 0x00, 0x0F, 0x87, 0x80, 0x00,\n  0x07, 0xC7, 0x80, 0x00, 0x03, 0xFF, 0x00, 0x00, 0x01, 0xFE, 0x00, 0x00,\n  0x00, 0xFC, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x01, 0xFF, 0x07, 0xFE,\n  0x03, 0xCF, 0xC0, 0xFE, 0x03, 0xC7, 0xE0, 0x3C, 0x07, 0xC3, 0xF0, 0x1C,\n  0x07, 0xC0, 0xFC, 0x0C, 0x03, 0xC0, 0x7E, 0x0E, 0x03, 0xE0, 0x3F, 0x0E,\n  0x01, 0xF0, 0x1F, 0xC6, 0x01, 0xF8, 0x07, 0xF6, 0x00, 0xFC, 0x03, 0xFF,\n  0x00, 0x7E, 0x00, 0xFF, 0x00, 0x3F, 0x80, 0x7F, 0x80, 0x1F, 0xC0, 0x1F,\n  0xC0, 0x07, 0xF0, 0x0F, 0xF0, 0x13, 0xFE, 0x0F, 0xFE, 0x18, 0xFF, 0xFE,\n  0xFF, 0xF8, 0x3F, 0xFE, 0x3F, 0xF8, 0x07, 0xF8, 0x03, 0xF0, 0x00, 0x1C,\n  0x7D, 0xFB, 0xF7, 0xCF, 0x9E, 0x3C, 0x71, 0xE3, 0x87, 0x0C, 0x00, 0x00,\n  0x04, 0x00, 0x70, 0x03, 0x80, 0x1C, 0x00, 0xE0, 0x07, 0x00, 0x3C, 0x01,\n  0xE0, 0x0F, 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0xF8, 0x8F, 0xFE, 0x38, 0xFB, 0x87,\n  0x0E, 0x01, 0xF0, 0x00, 0x3E, 0x00, 0x07, 0xC0, 0x00, 0x70, 0x00, 0x00,\n  0x78, 0x00, 0x01, 0xE0, 0x00, 0x07, 0x80, 0x00, 0x1E, 0x00, 0x00, 0x78,\n  0x00, 0x01, 0xE0, 0x00, 0x07, 0x80, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x03,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0x01,\n  0xE0, 0x00, 0x07, 0x80, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x01, 0xE0,\n  0x00, 0x07, 0x80, 0x00, 0x1E, 0x00, 0x00, 0x78, 0x00, 0x01, 0xE0, 0x00,\n  0x07, 0x80, 0x00, 0x0F, 0x07, 0xE1, 0xFC, 0x7F, 0x1F, 0xC3, 0xF0, 0x7C,\n  0x0E, 0x03, 0x80, 0xC0, 0x60, 0x30, 0x18, 0x1C, 0x04, 0x00, 0x7F, 0xF7,\n  0xFF, 0x7F, 0xEF, 0xFE, 0xFF, 0xE0, 0x3C, 0x7E, 0xFF, 0xFF, 0xFF, 0x7E,\n  0x3C, 0x00, 0x01, 0xE0, 0x00, 0x78, 0x00, 0x0F, 0x00, 0x03, 0xC0, 0x00,\n  0x78, 0x00, 0x1E, 0x00, 0x03, 0xC0, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x07,\n  0xC0, 0x00, 0xF0, 0x00, 0x1E, 0x00, 0x07, 0x80, 0x00, 0xF0, 0x00, 0x3C,\n  0x00, 0x07, 0x80, 0x01, 0xE0, 0x00, 0x3C, 0x00, 0x0F, 0x00, 0x01, 0xE0,\n  0x00, 0x7C, 0x00, 0x0F, 0x00, 0x01, 0xE0, 0x00, 0x78, 0x00, 0x0F, 0x00,\n  0x03, 0xC0, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x03, 0xC0, 0x00, 0xF8, 0x00,\n  0x1E, 0x00, 0x07, 0xC0, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x0F, 0x80, 0x00,\n  0xE3, 0x80, 0x0F, 0x07, 0x00, 0x7C, 0x1C, 0x03, 0xE0, 0x78, 0x0F, 0x81,\n  0xE0, 0x7C, 0x07, 0x83, 0xF0, 0x1F, 0x0F, 0xC0, 0xFC, 0x7E, 0x03, 0xF1,\n  0xF8, 0x0F, 0xCF, 0xE0, 0x3F, 0x3F, 0x00, 0xFD, 0xFC, 0x07, 0xF7, 0xF0,\n  0x1F, 0xDF, 0xC0, 0x7F, 0x7E, 0x01, 0xFB, 0xF8, 0x0F, 0xEF, 0xE0, 0x3F,\n  0xBF, 0x80, 0xFE, 0xFC, 0x03, 0xF3, 0xF0, 0x1F, 0xCF, 0xC0, 0x7F, 0x3F,\n  0x01, 0xF8, 0xFC, 0x07, 0xE3, 0xE0, 0x3F, 0x0F, 0x80, 0xFC, 0x1E, 0x07,\n  0xE0, 0x78, 0x1F, 0x00, 0xE0, 0x78, 0x03, 0x83, 0xC0, 0x07, 0x1E, 0x00,\n  0x07, 0xE0, 0x00, 0x00, 0x00, 0x70, 0x01, 0xFE, 0x01, 0xFF, 0xE0, 0x00,\n  0xFE, 0x00, 0x0F, 0xC0, 0x00, 0xFC, 0x00, 0x0F, 0xC0, 0x01, 0xFC, 0x00,\n  0x1F, 0x80, 0x01, 0xF8, 0x00, 0x3F, 0x80, 0x03, 0xF8, 0x00, 0x3F, 0x00,\n  0x03, 0xF0, 0x00, 0x7F, 0x00, 0x07, 0xE0, 0x00, 0x7E, 0x00, 0x07, 0xE0,\n  0x00, 0xFE, 0x00, 0x0F, 0xC0, 0x00, 0xFC, 0x00, 0x1F, 0xC0, 0x01, 0xFC,\n  0x00, 0x1F, 0x80, 0x01, 0xF8, 0x00, 0x3F, 0x80, 0x03, 0xF0, 0x00, 0x3F,\n  0x00, 0x07, 0xF0, 0x00, 0x7F, 0x00, 0x1F, 0xF8, 0x0F, 0xFF, 0xF0, 0x00,\n  0x0F, 0x80, 0x01, 0xFF, 0x80, 0x0F, 0xFF, 0x00, 0x7F, 0xFE, 0x03, 0x83,\n  0xF8, 0x0C, 0x07, 0xF0, 0x60, 0x1F, 0xC3, 0x00, 0x3F, 0x00, 0x00, 0xFC,\n  0x00, 0x03, 0xF0, 0x00, 0x0F, 0xC0, 0x00, 0x3E, 0x00, 0x01, 0xF8, 0x00,\n  0x07, 0xC0, 0x00, 0x3F, 0x00, 0x00, 0xF8, 0x00, 0x07, 0xC0, 0x00, 0x1E,\n  0x00, 0x00, 0xF0, 0x00, 0x07, 0x80, 0x00, 0x3C, 0x00, 0x01, 0xE0, 0x00,\n  0x0E, 0x00, 0x00, 0x70, 0x06, 0x03, 0x80, 0x10, 0x1C, 0x00, 0xC0, 0xE0,\n  0x06, 0x07, 0xFF, 0xF8, 0x3F, 0xFF, 0xE1, 0xFF, 0xFF, 0x0F, 0xFF, 0xFC,\n  0x3F, 0xFF, 0xE0, 0x00, 0x0F, 0xC0, 0x00, 0xFF, 0xC0, 0x0F, 0xFF, 0x80,\n  0x60, 0xFE, 0x03, 0x01, 0xFC, 0x08, 0x03, 0xF0, 0x00, 0x0F, 0xC0, 0x00,\n  0x3F, 0x00, 0x00, 0xFC, 0x00, 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0xFC, 0x00, 0x00,\n  0x7E, 0x00, 0x00, 0x3F, 0xFE, 0x00, 0x7F, 0xFE, 0x00, 0x7F, 0xFE, 0x00,\n  0x7F, 0xFC, 0x00, 0xFF, 0xFC, 0x00, 0xC0, 0x00, 0x01, 0x80, 0x00, 0x01,\n  0x80, 0x00, 0x03, 0x00, 0x00, 0x03, 0xF0, 0x00, 0x07, 0xFE, 0x00, 0x07,\n  0xFF, 0x00, 0x07, 0xFF, 0x80, 0x0F, 0xFF, 0xC0, 0x00, 0xFF, 0xE0, 0x00,\n  0x1F, 0xE0, 0x00, 0x0F, 0xF0, 0x00, 0x07, 0xF0, 0x00, 0x03, 0xF0, 0x00,\n  0x03, 0xF0, 0x00, 0x01, 0xF0, 0x00, 0x01, 0xF0, 0x00, 0x01, 0xF0, 0x00,\n  0x01, 0xE0, 0x00, 0x01, 0xE0, 0x00, 0x03, 0xC0, 0x78, 0x03, 0xC0, 0xFC,\n  0x07, 0x80, 0xFC, 0x0F, 0x00, 0xFE, 0x1E, 0x00, 0x7F, 0xF8, 0x00, 0x1F,\n  0xC0, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x01, 0xF8, 0x00, 0x0F, 0x80, 0x00,\n  0x7E, 0x00, 0x03, 0xF0, 0x00, 0x0F, 0xC0, 0x00, 0x3F, 0x00, 0x01, 0xFC,\n  0x00, 0x03, 0xF0, 0x00, 0x0F, 0xE0, 0x00, 0x3F, 0x80, 0x00, 0xFE, 0x00,\n  0x01, 0xFF, 0xF0, 0x07, 0xFF, 0xF0, 0x0F, 0xE1, 0xF0, 0x3F, 0x81, 0xF0,\n  0x7F, 0x03, 0xF0, 0xFC, 0x07, 0xE3, 0xF8, 0x0F, 0xC7, 0xF0, 0x1F, 0x8F,\n  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 0x06, 0x00, 0x01, 0xF0, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x03, 0xE0, 0x00,\n  0x00, 0x3E, 0x00, 0x00, 0x07, 0xE0, 0x00, 0x03, 0xFF, 0xC0, 0x00, 0x3F,\n  0xFC, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x0F, 0xC0, 0x00, 0x00, 0xF8, 0x00,\n  0x00, 0x0F, 0x80, 0x00, 0x01, 0xF8, 0x00, 0x00, 0x1F, 0x80, 0x00, 0x01,\n  0xF8, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x03, 0xF0, 0x00, 0x00, 0x3F, 0x00,\n  0x00, 0x03, 0xF0, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x03, 0xE0, 0x00, 0x00,\n  0x7E, 0x00, 0x00, 0x07, 0xE0, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x07, 0xC0,\n  0x00, 0x00, 0xFC, 0x00, 0x00, 0x0F, 0x80, 0x00, 0x00, 0xF8, 0x00, 0x00,\n  0x0F, 0x80, 0x00, 0x01, 0xF0, 0x00, 0x06, 0x1F, 0x00, 0x00, 0xF1, 0xE0,\n  0x00, 0x0F, 0x3E, 0x00, 0x00, 0xF3, 0xC0, 0x00, 0x07, 0xF8, 0x00, 0x00,\n  0x3E, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x80, 0x00, 0x7F, 0xF0, 0x00, 0x7E,\n  0x3F, 0xE0, 0x7C, 0x0F, 0xF0, 0x7E, 0x07, 0xC0, 0x7E, 0x03, 0xE0, 0x3F,\n  0x01, 0xF0, 0x1F, 0x01, 0xF8, 0x0F, 0x80, 0xFC, 0x07, 0xC0, 0xFC, 0x01,\n  0xE0, 0xFC, 0x00, 0x78, 0xFC, 0x00, 0x1F, 0xFC, 0x00, 0x0F, 0xF0, 0x00,\n  0x1C, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x1F, 0x80, 0x00, 0x0F, 0xF8, 0x00,\n  0x07, 0xFF, 0x80, 0x01, 0xFF, 0xF8, 0x00, 0x7F, 0xFE, 0x00, 0x77, 0xFF,\n  0x80, 0xF0, 0x7F, 0xC0, 0xF0, 0x07, 0xE0, 0xF0, 0x01, 0xF0, 0x78, 0x00,\n  0xF8, 0x3C, 0x00, 0x78, 0x1F, 0x00, 0x7C, 0x07, 0xC0, 0x78, 0x01, 0xFF,\n  0xF8, 0x00, 0x1F, 0xE0, 0x00, 0x00, 0x04, 0x00, 0x01, 0xF8, 0x00, 0x1F,\n  0xF0, 0x00, 0x07, 0xE0, 0x00, 0x0F, 0x80, 0x00, 0x1F, 0x00, 0x00, 0x7E,\n  0x00, 0x00, 0xFC, 0x00, 0x01, 0xF0, 0x00, 0x03, 0xE0, 0x00, 0x0F, 0xC0,\n  0x00, 0x1F, 0x87, 0xC0, 0x3E, 0x1F, 0xC0, 0xFC, 0x7F, 0x81, 0xF9, 0x9F,\n  0x03, 0xE6, 0x3E, 0x07, 0xD8, 0x7C, 0x1F, 0xA0, 0xF8, 0x3F, 0x83, 0xF0,\n  0x7F, 0x07, 0xE0, 0xFC, 0x0F, 0xC3, 0xF8, 0x3F, 0x07, 0xE0, 0x7E, 0x0F,\n  0xC0, 0xFC, 0x3F, 0x03, 0xF0, 0x7E, 0x07, 0xE0, 0xFC, 0x0F, 0xC1, 0xF0,\n  0x3F, 0x17, 0xE0, 0x7E, 0x6F, 0xC0, 0xF9, 0x9F, 0x01, 0xF6, 0x3E, 0x03,\n  0xF8, 0xFC, 0x07, 0xF1, 0xC0, 0x07, 0x80, 0x01, 0xE0, 0x3F, 0x03, 0xF0,\n  0x3F, 0x03, 0xF0, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xC7,\n  0xFC, 0x1F, 0xC0, 0xF8, 0x0F, 0x81, 0xF8, 0x1F, 0x81, 0xF0, 0x1F, 0x03,\n  0xF0, 0x3E, 0x03, 0xE0, 0x3E, 0x07, 0xE0, 0x7C, 0x07, 0xC0, 0xFC, 0x2F,\n  0x84, 0xF8, 0xCF, 0x98, 0xFF, 0x0F, 0xE0, 0x78, 0x00, 0x00, 0x00, 0x78,\n  0x00, 0x03, 0xF0, 0x00, 0x0F, 0xC0, 0x00, 0x3F, 0x00, 0x00, 0xFC, 0x00,\n  0x01, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x01, 0x00, 0x00, 0xFC, 0x00, 0x1F, 0xF0, 0x00, 0x1F, 0xC0,\n  0x00, 0x3E, 0x00, 0x01, 0xF8, 0x00, 0x07, 0xE0, 0x00, 0x1F, 0x80, 0x00,\n  0x7C, 0x00, 0x03, 0xF0, 0x00, 0x0F, 0xC0, 0x00, 0x3F, 0x00, 0x00, 0xF8,\n  0x00, 0x07, 0xE0, 0x00, 0x1F, 0x80, 0x00, 0x7E, 0x00, 0x01, 0xF0, 0x00,\n  0x0F, 0xC0, 0x00, 0x3F, 0x00, 0x00, 0xFC, 0x00, 0x03, 0xE0, 0x00, 0x1F,\n  0x80, 0x00, 0x7E, 0x00, 0x01, 0xF0, 0x00, 0x07, 0xC0, 0x00, 0x3F, 0x00,\n  0x60, 0xF8, 0x03, 0xC3, 0xC0, 0x0F, 0x1F, 0x00, 0x3C, 0xF8, 0x00, 0x7F,\n  0xC0, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0xFC, 0x00, 0x07,\n  0xFC, 0x00, 0x00, 0xFC, 0x00, 0x00, 0xF8, 0x00, 0x00, 0xF8, 0x00, 0x01,\n  0xF8, 0x00, 0x01, 0xF8, 0x00, 0x01, 0xF0, 0x00, 0x01, 0xF0, 0x00, 0x03,\n  0xF0, 0x00, 0x03, 0xF0, 0x00, 0x03, 0xE3, 0xFF, 0x03, 0xE0, 0xFC, 0x07,\n  0xE0, 0xF0, 0x07, 0xE0, 0xE0, 0x07, 0xC1, 0xC0, 0x0F, 0xC3, 0x80, 0x0F,\n  0xC7, 0x00, 0x0F, 0x8E, 0x00, 0x0F, 0xBE, 0x00, 0x1F, 0xFE, 0x00, 0x1F,\n  0xFE, 0x00, 0x1F, 0xFE, 0x00, 0x1F, 0x3E, 0x00, 0x3F, 0x3F, 0x00, 0x3F,\n  0x1F, 0x00, 0x3E, 0x1F, 0x00, 0x7E, 0x1F, 0x04, 0x7E, 0x1F, 0x8C, 0x7E,\n  0x0F, 0x98, 0x7C, 0x0F, 0xF0, 0xFC, 0x07, 0xE0, 0xE0, 0x03, 0xC0, 0x00,\n  0x08, 0x0F, 0xC7, 0xFE, 0x07, 0xF0, 0x3F, 0x01, 0xF8, 0x0F, 0xC0, 0x7C,\n  0x07, 0xE0, 0x3F, 0x01, 0xF8, 0x0F, 0x80, 0x7C, 0x07, 0xE0, 0x3E, 0x01,\n  0xF0, 0x1F, 0x80, 0xFC, 0x07, 0xC0, 0x3E, 0x03, 0xF0, 0x1F, 0x80, 0xF8,\n  0x0F, 0xC0, 0x7E, 0x03, 0xE0, 0x1F, 0x00, 0xF8, 0x8F, 0x8C, 0x7C, 0x43,\n  0xE4, 0x1F, 0xE0, 0xFE, 0x03, 0xC0, 0x00, 0x00, 0x70, 0x78, 0x0F, 0x83,\n  0xFE, 0x3F, 0x87, 0xF8, 0x1F, 0xCF, 0xF1, 0xFF, 0x03, 0xF1, 0x3E, 0x73,\n  0xE0, 0x7E, 0x47, 0xD8, 0x7C, 0x0F, 0xD0, 0xFB, 0x1F, 0x81, 0xF4, 0x3E,\n  0xC3, 0xF0, 0x3E, 0x87, 0xF0, 0x7C, 0x0F, 0xE0, 0xFE, 0x1F, 0x81, 0xF4,\n  0x1F, 0x83, 0xF0, 0x3F, 0x07, 0xE0, 0x7C, 0x07, 0xE0, 0xFC, 0x1F, 0x81,\n  0xF8, 0x1F, 0x83, 0xF0, 0x3F, 0x07, 0xE0, 0x7C, 0x07, 0xE0, 0xFC, 0x0F,\n  0x80, 0xF8, 0x1F, 0x03, 0xF0, 0x3F, 0x07, 0xE0, 0x7E, 0x07, 0xE0, 0xFC,\n  0x0F, 0x88, 0xF8, 0x1F, 0x81, 0xF3, 0x3F, 0x03, 0xE0, 0x3E, 0x47, 0xE0,\n  0xFC, 0x07, 0xF0, 0xFC, 0x1F, 0x80, 0xFE, 0x18, 0x00, 0x00, 0x0F, 0x00,\n  0x00, 0x70, 0xF8, 0x7F, 0xC3, 0xF8, 0x1F, 0x8F, 0xF0, 0x3F, 0x33, 0xE0,\n  0x7C, 0x87, 0xC1, 0xF9, 0x0F, 0x83, 0xF4, 0x1F, 0x07, 0xD0, 0x3E, 0x0F,\n  0xE0, 0xFC, 0x3F, 0x81, 0xF8, 0x7F, 0x03, 0xE0, 0xFC, 0x0F, 0xC1, 0xF8,\n  0x1F, 0x87, 0xE0, 0x3E, 0x0F, 0xC0, 0xFC, 0x1F, 0x81, 0xF0, 0x3E, 0x03,\n  0xE0, 0xFC, 0x0F, 0xC9, 0xF8, 0x1F, 0x33, 0xE0, 0x3E, 0x47, 0xC0, 0x7F,\n  0x1F, 0x80, 0xFE, 0x38, 0x00, 0xF0, 0x00, 0x00, 0x3F, 0x00, 0x0E, 0x38,\n  0x03, 0xC1, 0xC0, 0x78, 0x1E, 0x0F, 0x81, 0xF0, 0xF0, 0x1F, 0x1F, 0x01,\n  0xF3, 0xE0, 0x1F, 0x3E, 0x03, 0xF7, 0xC0, 0x3F, 0x7C, 0x03, 0xF7, 0xC0,\n  0x3E, 0xFC, 0x03, 0xEF, 0xC0, 0x7E, 0xF8, 0x07, 0xCF, 0x80, 0x7C, 0xF8,\n  0x0F, 0x8F, 0x80, 0xF8, 0xF8, 0x1F, 0x07, 0x81, 0xE0, 0x78, 0x3C, 0x03,\n  0xC7, 0x00, 0x0F, 0xC0, 0x00, 0x00, 0x0F, 0x1F, 0x00, 0x3F, 0xE7, 0xF8,\n  0x01, 0xF9, 0xFF, 0x00, 0x1F, 0x47, 0xF0, 0x07, 0xF0, 0x7E, 0x00, 0xFE,\n  0x0F, 0xC0, 0x1F, 0x81, 0xF8, 0x03, 0xF0, 0x3F, 0x00, 0xFC, 0x07, 0xE0,\n  0x1F, 0x81, 0xFC, 0x03, 0xE0, 0x3F, 0x00, 0x7C, 0x07, 0xE0, 0x1F, 0x81,\n  0xFC, 0x03, 0xF0, 0x3F, 0x00, 0x7C, 0x07, 0xE0, 0x0F, 0x81, 0xF8, 0x03,\n  0xF0, 0x3E, 0x00, 0x7E, 0x0F, 0xC0, 0x0F, 0x81, 0xF0, 0x01, 0xF0, 0x7C,\n  0x00, 0x7F, 0x1F, 0x00, 0x0F, 0xFF, 0xC0, 0x01, 0xF3, 0xE0, 0x00, 0x3E,\n  0x00, 0x00, 0x0F, 0xC0, 0x00, 0x01, 0xF8, 0x00, 0x00, 0x3E, 0x00, 0x00,\n  0x0F, 0xC0, 0x00, 0x01, 0xF8, 0x00, 0x00, 0x7F, 0x00, 0x00, 0x3F, 0xFC,\n  0x00, 0x00, 0x00, 0x3E, 0x00, 0x03, 0xF9, 0xF0, 0x1F, 0x1F, 0xC0, 0xF8,\n  0x7E, 0x07, 0xC1, 0xF8, 0x3F, 0x07, 0xE0, 0xF8, 0x1F, 0x87, 0xE0, 0x7C,\n  0x3F, 0x01, 0xF0, 0xFC, 0x0F, 0xC7, 0xE0, 0x3E, 0x1F, 0x80, 0xF8, 0x7E,\n  0x07, 0xE3, 0xF0, 0x1F, 0x8F, 0xC0, 0x7C, 0x3F, 0x03, 0xF0, 0xFC, 0x0F,\n  0xC3, 0xF0, 0x7E, 0x0F, 0xC3, 0xF8, 0x3F, 0x9B, 0xE0, 0x7F, 0xDF, 0x01,\n  0xFE, 0x7C, 0x01, 0xF1, 0xF0, 0x00, 0x0F, 0xC0, 0x00, 0x3E, 0x00, 0x00,\n  0xF8, 0x00, 0x07, 0xE0, 0x00, 0x1F, 0x80, 0x00, 0x7C, 0x00, 0x03, 0xF8,\n  0x00, 0x7F, 0xF8, 0x00, 0x00, 0x71, 0xE1, 0xFF, 0x3E, 0x07, 0xE7, 0xF0,\n  0x7E, 0xFF, 0x07, 0xE9, 0xE0, 0x7D, 0x0E, 0x07, 0xD0, 0x00, 0xFE, 0x00,\n  0x0F, 0xE0, 0x00, 0xFC, 0x00, 0x0F, 0xC0, 0x01, 0xFC, 0x00, 0x1F, 0x80,\n  0x01, 0xF8, 0x00, 0x1F, 0x00, 0x03, 0xF0, 0x00, 0x3F, 0x00, 0x03, 0xF0,\n  0x00, 0x7E, 0x00, 0x07, 0xE0, 0x00, 0x7E, 0x00, 0x07, 0xC0, 0x00, 0x01,\n  0xF1, 0x07, 0xFF, 0x0F, 0x0F, 0x0E, 0x07, 0x1E, 0x06, 0x1E, 0x06, 0x1F,\n  0x02, 0x1F, 0x02, 0x1F, 0x80, 0x0F, 0xC0, 0x0F, 0xE0, 0x0F, 0xF0, 0x07,\n  0xF8, 0x03, 0xF8, 0x01, 0xFC, 0x00, 0xFC, 0x40, 0x7C, 0x40, 0x7C, 0x60,\n  0x3C, 0xE0, 0x38, 0xF0, 0x38, 0xF8, 0xF0, 0xDF, 0xC0, 0x00, 0x20, 0x03,\n  0x00, 0x38, 0x03, 0x80, 0x3C, 0x03, 0xE0, 0x7F, 0x07, 0xFF, 0x3F, 0xF8,\n  0x7C, 0x07, 0xE0, 0x3F, 0x01, 0xF0, 0x0F, 0x80, 0xFC, 0x07, 0xC0, 0x3E,\n  0x03, 0xF0, 0x1F, 0x80, 0xF8, 0x07, 0xC0, 0x7E, 0x03, 0xF1, 0x1F, 0x08,\n  0xF8, 0x87, 0xC8, 0x3F, 0xC1, 0xFC, 0x07, 0x80, 0x00, 0x00, 0x40, 0x00,\n  0x1F, 0x03, 0xF7, 0xF8, 0x0F, 0x87, 0xE0, 0x3E, 0x1F, 0x81, 0xF8, 0x7E,\n  0x07, 0xC1, 0xF0, 0x1F, 0x07, 0xC0, 0xFC, 0x3F, 0x03, 0xE0, 0xF8, 0x0F,\n  0x83, 0xE0, 0x7E, 0x0F, 0x81, 0xF8, 0x7E, 0x0F, 0xC1, 0xF0, 0x3F, 0x07,\n  0xC1, 0xFC, 0x1F, 0x07, 0xE0, 0xF8, 0x2F, 0x83, 0xE1, 0x3C, 0x6F, 0x8D,\n  0xF1, 0x3E, 0x67, 0xC8, 0xFF, 0x1F, 0xE3, 0xF8, 0x7F, 0x07, 0xC0, 0xF0,\n  0x00, 0x06, 0x07, 0x1F, 0x07, 0xBF, 0x83, 0xE7, 0xC1, 0xF3, 0xE0, 0xF9,\n  0xF8, 0x3C, 0x7C, 0x0C, 0x3E, 0x06, 0x1F, 0x03, 0x0F, 0x83, 0x07, 0xC1,\n  0x83, 0xE1, 0x81, 0xF1, 0x80, 0xF9, 0x80, 0x7C, 0xC0, 0x3E, 0xC0, 0x1F,\n  0xC0, 0x0F, 0xC0, 0x07, 0xC0, 0x03, 0xC0, 0x01, 0xC0, 0x00, 0xC0, 0x00,\n  0x40, 0x00, 0x06, 0x01, 0x81, 0xC7, 0xC0, 0x30, 0x7F, 0xF8, 0x0E, 0x0F,\n  0x9F, 0x01, 0xC1, 0xF3, 0xE0, 0x78, 0x3E, 0x7C, 0x1F, 0x03, 0xCF, 0xC3,\n  0xE0, 0x30, 0xF8, 0xFC, 0x06, 0x1F, 0x1F, 0xC0, 0x83, 0xE7, 0xF8, 0x30,\n  0x7C, 0xFF, 0x04, 0x0F, 0xB7, 0xE1, 0x81, 0xF6, 0xFC, 0x60, 0x3F, 0x8F,\n  0x98, 0x07, 0xE1, 0xF3, 0x00, 0xFC, 0x3E, 0xC0, 0x1F, 0x07, 0xF0, 0x03,\n  0xE0, 0xFC, 0x00, 0x78, 0x1F, 0x80, 0x0F, 0x03, 0xE0, 0x01, 0xC0, 0x78,\n  0x00, 0x30, 0x0E, 0x00, 0x06, 0x01, 0x80, 0x00, 0x00, 0xF0, 0x1E, 0x0F,\n  0xF0, 0x3E, 0x01, 0xF8, 0x7F, 0x01, 0xF8, 0xFF, 0x00, 0xF9, 0x8E, 0x00,\n  0xFB, 0x00, 0x00, 0xFF, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x7C, 0x00, 0x00,\n  0x7C, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x7E, 0x00, 0x00,\n  0x7E, 0x00, 0x00, 0x7E, 0x00, 0x00, 0xFE, 0x00, 0x01, 0xBF, 0x00, 0x01,\n  0xBF, 0x08, 0x73, 0x1F, 0x18, 0xFF, 0x1F, 0x30, 0xFE, 0x1F, 0xE0, 0xFC,\n  0x0F, 0xC0, 0x78, 0x07, 0x80, 0x00, 0x30, 0x1C, 0x0F, 0xF0, 0x7C, 0x07,\n  0xE0, 0xF8, 0x0F, 0xC1, 0xF0, 0x0F, 0xC1, 0xE0, 0x1F, 0x81, 0xC0, 0x3F,\n  0x03, 0x00, 0x3E, 0x06, 0x00, 0x7E, 0x08, 0x00, 0xFC, 0x30, 0x01, 0xF8,\n  0x60, 0x01, 0xF1, 0x80, 0x03, 0xE3, 0x00, 0x07, 0xCC, 0x00, 0x0F, 0xD8,\n  0x00, 0x1F, 0xE0, 0x00, 0x1F, 0xC0, 0x00, 0x3F, 0x00, 0x00, 0x7E, 0x00,\n  0x00, 0xF8, 0x00, 0x01, 0xE0, 0x00, 0x03, 0xC0, 0x00, 0x07, 0x00, 0x00,\n  0x0C, 0x00, 0x00, 0x18, 0x00, 0x00, 0x60, 0x01, 0xC1, 0x80, 0x07, 0xE6,\n  0x00, 0x0F, 0xF8, 0x00, 0x1F, 0xC0, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x07,\n  0xFF, 0xE1, 0xFF, 0xF8, 0x3F, 0xFF, 0x07, 0xFF, 0xC0, 0x80, 0x70, 0x30,\n  0x1C, 0x04, 0x07, 0x00, 0x00, 0xC0, 0x00, 0x38, 0x00, 0x0E, 0x00, 0x03,\n  0x80, 0x00, 0x60, 0x00, 0x18, 0x00, 0x06, 0x00, 0x01, 0xC0, 0x00, 0x30,\n  0x00, 0x0C, 0x00, 0x03, 0xE0, 0x00, 0xFE, 0x00, 0x1F, 0xE0, 0xC7, 0xFC,\n  0x3D, 0xCF, 0xC7, 0x90, 0xF8, 0xF0, 0x07, 0x9C, 0x00, 0x3E, 0x00, 0x00,\n  0x01, 0xF0, 0x00, 0xFC, 0x00, 0x1F, 0x00, 0x03, 0xE0, 0x00, 0x7C, 0x00,\n  0x07, 0xC0, 0x00, 0x78, 0x00, 0x0F, 0x80, 0x00, 0xF8, 0x00, 0x0F, 0x80,\n  0x01, 0xF0, 0x00, 0x1F, 0x00, 0x01, 0xF0, 0x00, 0x1F, 0x00, 0x03, 0xE0,\n  0x00, 0x3E, 0x00, 0x03, 0xC0, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x0F, 0xC0,\n  0x00, 0x1F, 0x00, 0x00, 0xF8, 0x00, 0x0F, 0x80, 0x00, 0xF8, 0x00, 0x0F,\n  0x80, 0x01, 0xF0, 0x00, 0x1F, 0x00, 0x01, 0xF0, 0x00, 0x1F, 0x00, 0x03,\n  0xE0, 0x00, 0x3E, 0x00, 0x03, 0xE0, 0x00, 0x3E, 0x00, 0x07, 0xC0, 0x00,\n  0x7C, 0x00, 0x07, 0xC0, 0x00, 0x7C, 0x00, 0x07, 0xC0, 0x00, 0x7E, 0x00,\n  0x03, 0xF0, 0x00, 0x07, 0xC0, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0x00,\n  0x3E, 0x00, 0x00, 0xFC, 0x00, 0x03, 0xE0, 0x00, 0x3E, 0x00, 0x03, 0xE0,\n  0x00, 0x3E, 0x00, 0x03, 0xE0, 0x00, 0x7C, 0x00, 0x07, 0xC0, 0x00, 0x7C,\n  0x00, 0x07, 0xC0, 0x00, 0xF8, 0x00, 0x0F, 0x80, 0x00, 0xF8, 0x00, 0x0F,\n  0x80, 0x01, 0xF0, 0x00, 0x1F, 0x00, 0x01, 0xF0, 0x00, 0x1F, 0x00, 0x00,\n  0xF8, 0x00, 0x03, 0xE0, 0x00, 0x78, 0x00, 0x1E, 0x00, 0x03, 0xE0, 0x00,\n  0x7C, 0x00, 0x07, 0xC0, 0x00, 0xF8, 0x00, 0x0F, 0x80, 0x00, 0xF8, 0x00,\n  0x0F, 0x80, 0x01, 0xF0, 0x00, 0x1F, 0x00, 0x01, 0xF0, 0x00, 0x1F, 0x00,\n  0x03, 0xE0, 0x00, 0x3E, 0x00, 0x07, 0xC0, 0x00, 0x7C, 0x00, 0x0F, 0x80,\n  0x03, 0xF0, 0x00, 0xF8, 0x00, 0x00, 0x1F, 0x00, 0x03, 0xFF, 0x01, 0x3F,\n  0xFE, 0x1D, 0xFF, 0xFF, 0xFE, 0x0F, 0xFF, 0x00, 0x1F, 0xF0, 0x00, 0x1F,\n  0x00 };\n\nconst GFXglyph FreeSerifBoldItalic24pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,  12,    0,    1 },   // 0x20 ' '\n  {     0,  15,  33,  18,    3,  -31 },   // 0x21 '!'\n  {    62,  19,  13,  26,    6,  -31 },   // 0x22 '\"'\n  {    93,  27,  33,  23,   -2,  -32 },   // 0x23 '#'\n  {   205,  24,  39,  24,   -1,  -33 },   // 0x24 '$'\n  {   322,  35,  32,  39,    2,  -30 },   // 0x25 '%'\n  {   462,  33,  33,  37,    0,  -31 },   // 0x26 '&'\n  {   599,   7,  13,  13,    6,  -31 },   // 0x27 '''\n  {   611,  14,  41,  16,    1,  -31 },   // 0x28 '('\n  {   683,  14,  41,  16,   -2,  -31 },   // 0x29 ')'\n  {   755,  19,  20,  23,    3,  -31 },   // 0x2A '*'\n  {   803,  22,  23,  27,    2,  -22 },   // 0x2B '+'\n  {   867,  10,  15,  12,   -3,   -5 },   // 0x2C ','\n  {   886,  12,   5,  16,    0,  -12 },   // 0x2D '-'\n  {   894,   8,   7,  12,    0,   -5 },   // 0x2E '.'\n  {   901,  19,  33,  16,    0,  -31 },   // 0x2F '/'\n  {   980,  22,  33,  23,    1,  -31 },   // 0x30 '0'\n  {  1071,  20,  32,  23,    0,  -31 },   // 0x31 '1'\n  {  1151,  22,  32,  23,    1,  -31 },   // 0x32 '2'\n  {  1239,  22,  33,  24,    0,  -31 },   // 0x33 '3'\n  {  1330,  25,  32,  23,    0,  -31 },   // 0x34 '4'\n  {  1430,  24,  32,  24,    0,  -30 },   // 0x35 '5'\n  {  1526,  23,  32,  24,    1,  -30 },   // 0x36 '6'\n  {  1618,  23,  31,  23,    3,  -30 },   // 0x37 '7'\n  {  1708,  21,  33,  23,    1,  -31 },   // 0x38 '8'\n  {  1795,  23,  33,  23,    0,  -31 },   // 0x39 '9'\n  {  1890,  13,  22,  12,    0,  -20 },   // 0x3A ':'\n  {  1926,  15,  30,  12,   -2,  -20 },   // 0x3B ';'\n  {  1983,  24,  25,  27,    1,  -23 },   // 0x3C '<'\n  {  2058,  24,  14,  27,    3,  -18 },   // 0x3D '='\n  {  2100,  24,  25,  27,    3,  -23 },   // 0x3E '>'\n  {  2175,  18,  33,  24,    4,  -31 },   // 0x3F '?'\n  {  2250,  33,  33,  39,    3,  -31 },   // 0x40 '@'\n  {  2387,  31,  32,  33,    0,  -31 },   // 0x41 'A'\n  {  2511,  31,  31,  30,    0,  -30 },   // 0x42 'B'\n  {  2632,  29,  33,  29,    2,  -31 },   // 0x43 'C'\n  {  2752,  35,  31,  34,    0,  -30 },   // 0x44 'D'\n  {  2888,  32,  31,  30,    0,  -30 },   // 0x45 'E'\n  {  3012,  31,  31,  29,    0,  -30 },   // 0x46 'F'\n  {  3133,  32,  33,  33,    2,  -31 },   // 0x47 'G'\n  {  3265,  39,  31,  35,    0,  -30 },   // 0x48 'H'\n  {  3417,  21,  31,  18,    0,  -30 },   // 0x49 'I'\n  {  3499,  27,  36,  23,    0,  -30 },   // 0x4A 'J'\n  {  3621,  34,  31,  31,    0,  -30 },   // 0x4B 'K'\n  {  3753,  29,  31,  29,    0,  -30 },   // 0x4C 'L'\n  {  3866,  44,  32,  41,    0,  -30 },   // 0x4D 'M'\n  {  4042,  37,  32,  33,    0,  -30 },   // 0x4E 'N'\n  {  4190,  31,  33,  32,    2,  -31 },   // 0x4F 'O'\n  {  4318,  31,  31,  28,    0,  -30 },   // 0x50 'P'\n  {  4439,  31,  42,  32,    2,  -31 },   // 0x51 'Q'\n  {  4602,  32,  31,  31,    0,  -30 },   // 0x52 'R'\n  {  4726,  24,  33,  24,    0,  -31 },   // 0x53 'S'\n  {  4825,  27,  31,  28,    4,  -30 },   // 0x54 'T'\n  {  4930,  32,  32,  34,    5,  -30 },   // 0x55 'U'\n  {  5058,  31,  32,  33,    6,  -30 },   // 0x56 'V'\n  {  5182,  41,  32,  44,    6,  -30 },   // 0x57 'W'\n  {  5346,  34,  31,  33,    0,  -30 },   // 0x58 'X'\n  {  5478,  28,  31,  30,    6,  -30 },   // 0x59 'Y'\n  {  5587,  28,  31,  26,    0,  -30 },   // 0x5A 'Z'\n  {  5696,  19,  38,  16,   -2,  -30 },   // 0x5B '['\n  {  5787,  13,  33,  19,    6,  -31 },   // 0x5C '\\'\n  {  5841,  19,  38,  16,   -3,  -30 },   // 0x5D ']'\n  {  5932,  21,  17,  27,    3,  -30 },   // 0x5E '^'\n  {  5977,  24,   3,  23,    0,    5 },   // 0x5F '_'\n  {  5986,  10,   9,  16,    4,  -32 },   // 0x60 '`'\n  {  5998,  22,  23,  24,    1,  -21 },   // 0x61 'a'\n  {  6062,  22,  33,  23,    1,  -31 },   // 0x62 'b'\n  {  6153,  18,  23,  20,    1,  -21 },   // 0x63 'c'\n  {  6205,  25,  34,  24,    1,  -32 },   // 0x64 'd'\n  {  6312,  18,  23,  20,    1,  -21 },   // 0x65 'e'\n  {  6364,  28,  41,  23,   -4,  -31 },   // 0x66 'f'\n  {  6508,  25,  31,  23,   -1,  -21 },   // 0x67 'g'\n  {  6605,  23,  34,  26,    1,  -32 },   // 0x68 'h'\n  {  6703,  12,  33,  14,    2,  -31 },   // 0x69 'i'\n  {  6753,  22,  42,  16,   -4,  -31 },   // 0x6A 'j'\n  {  6869,  24,  34,  24,    1,  -32 },   // 0x6B 'k'\n  {  6971,  13,  34,  14,    2,  -32 },   // 0x6C 'l'\n  {  7027,  35,  23,  36,    0,  -21 },   // 0x6D 'm'\n  {  7128,  23,  23,  25,    0,  -21 },   // 0x6E 'n'\n  {  7195,  20,  23,  22,    1,  -21 },   // 0x6F 'o'\n  {  7253,  27,  31,  23,   -4,  -21 },   // 0x70 'p'\n  {  7358,  22,  31,  23,    1,  -21 },   // 0x71 'q'\n  {  7444,  20,  22,  19,    0,  -21 },   // 0x72 'r'\n  {  7499,  16,  23,  17,    0,  -21 },   // 0x73 's'\n  {  7545,  13,  29,  13,    2,  -27 },   // 0x74 't'\n  {  7593,  22,  23,  25,    2,  -21 },   // 0x75 'u'\n  {  7657,  17,  23,  21,    3,  -21 },   // 0x76 'v'\n  {  7706,  27,  23,  31,    3,  -21 },   // 0x77 'w'\n  {  7784,  24,  23,  22,   -1,  -21 },   // 0x78 'x'\n  {  7853,  23,  31,  20,   -3,  -21 },   // 0x79 'y'\n  {  7943,  19,  25,  19,    0,  -20 },   // 0x7A 'z'\n  {  8003,  20,  41,  16,    0,  -31 },   // 0x7B '{'\n  {  8106,   4,  33,  13,    5,  -31 },   // 0x7C '|'\n  {  8123,  20,  41,  16,   -6,  -31 },   // 0x7D '}'\n  {  8226,  21,   7,  27,    3,  -14 } }; // 0x7E '~'\n\nconst GFXfont FreeSerifBoldItalic24pt7b PROGMEM = {\n  (uint8_t  *)FreeSerifBoldItalic24pt7bBitmaps,\n  (GFXglyph *)FreeSerifBoldItalic24pt7bGlyphs,\n  0x20, 0x7E, 56 };\n\n// Approx. 8917 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeSerifBoldItalic9pt7b.h",
    "content": "const uint8_t FreeSerifBoldItalic9pt7bBitmaps[] PROGMEM = {\n  0x0C, 0x31, 0xC6, 0x18, 0x41, 0x08, 0x20, 0x0E, 0x38, 0xE0, 0xCF, 0x38,\n  0xA2, 0x88, 0x02, 0x40, 0xC8, 0x13, 0x06, 0x43, 0xFC, 0x32, 0x06, 0x40,\n  0x98, 0x7F, 0x84, 0xC0, 0x90, 0x32, 0x04, 0xC0, 0x01, 0x01, 0xF0, 0x4B,\n  0x99, 0x33, 0x24, 0x78, 0x07, 0x80, 0x38, 0x0B, 0x89, 0x31, 0x26, 0x64,\n  0xC7, 0x30, 0x3C, 0x04, 0x00, 0x38, 0x41, 0x9F, 0x06, 0x48, 0x31, 0x60,\n  0xCD, 0x03, 0x2C, 0x07, 0x27, 0x81, 0x39, 0x05, 0xC4, 0x26, 0x10, 0x98,\n  0x84, 0x66, 0x10, 0xE0, 0x03, 0x80, 0x22, 0x03, 0x10, 0x19, 0x00, 0xF0,\n  0x0F, 0x3C, 0xF8, 0xCC, 0xC4, 0xE7, 0x47, 0x3E, 0x38, 0xE1, 0xE7, 0x97,\n  0xCF, 0x00, 0xFA, 0x80, 0x08, 0x88, 0x84, 0x62, 0x10, 0x84, 0x21, 0x08,\n  0x41, 0x00, 0x20, 0x84, 0x10, 0x84, 0x21, 0x08, 0xC6, 0x23, 0x11, 0x00,\n  0x18, 0x18, 0xD6, 0x38, 0x18, 0xF7, 0x18, 0x18, 0x08, 0x04, 0x02, 0x01,\n  0x0F, 0xF8, 0x40, 0x20, 0x10, 0x08, 0x00, 0x6D, 0x95, 0x00, 0xFF, 0xC0,\n  0xFF, 0x80, 0x06, 0x0C, 0x30, 0x60, 0x83, 0x04, 0x18, 0x20, 0xC1, 0x06,\n  0x00, 0x0F, 0x0C, 0x8C, 0x6E, 0x37, 0x1B, 0x1F, 0x8F, 0xC7, 0xC7, 0x63,\n  0xB1, 0x89, 0x83, 0x80, 0x06, 0x1E, 0x0E, 0x0E, 0x0C, 0x0C, 0x1C, 0x18,\n  0x18, 0x18, 0x38, 0x38, 0xFC, 0x1F, 0x13, 0xD0, 0xE0, 0x70, 0x38, 0x38,\n  0x18, 0x18, 0x18, 0x08, 0x08, 0x4F, 0xCF, 0xE0, 0x1F, 0x11, 0xC0, 0xE0,\n  0x60, 0xC1, 0xF0, 0x38, 0x0C, 0x06, 0x03, 0x01, 0x19, 0x8F, 0x00, 0x00,\n  0x80, 0xC0, 0xE1, 0xE0, 0xB0, 0x98, 0x9C, 0x8C, 0xFF, 0x07, 0x03, 0x01,\n  0x80, 0x0F, 0x88, 0x08, 0x07, 0x83, 0xE0, 0x78, 0x1C, 0x06, 0x03, 0x01,\n  0x80, 0x9C, 0x87, 0x80, 0x03, 0x87, 0x07, 0x07, 0x07, 0x03, 0xE3, 0x99,\n  0xCC, 0xC6, 0x63, 0x33, 0x89, 0x87, 0x80, 0x3F, 0xBF, 0x90, 0x80, 0xC0,\n  0x40, 0x60, 0x20, 0x30, 0x30, 0x10, 0x18, 0x08, 0x00, 0x1E, 0x13, 0x31,\n  0x31, 0x3A, 0x1C, 0x1C, 0x6E, 0xC6, 0xC6, 0xC6, 0x44, 0x38, 0x0E, 0x1C,\n  0x8C, 0x6C, 0x36, 0x3B, 0x1D, 0x8E, 0x7E, 0x0E, 0x07, 0x07, 0x0E, 0x0C,\n  0x00, 0x39, 0xCE, 0x00, 0x03, 0x9C, 0xE0, 0x39, 0xCE, 0x00, 0x01, 0x8C,\n  0x22, 0x20, 0x00, 0x01, 0xC3, 0xC7, 0x8E, 0x06, 0x01, 0xE0, 0x3C, 0x07,\n  0x80, 0x40, 0xFF, 0x80, 0x00, 0x00, 0x0F, 0xF8, 0x00, 0x60, 0x1E, 0x03,\n  0xC0, 0x78, 0x1C, 0x3C, 0x78, 0xF0, 0x40, 0x00, 0x1C, 0x27, 0x37, 0x07,\n  0x0E, 0x1C, 0x30, 0x60, 0x40, 0x00, 0xE0, 0xE0, 0xE0, 0x0F, 0x80, 0xC3,\n  0x08, 0x04, 0xC3, 0x3C, 0x24, 0xE2, 0x27, 0x33, 0x39, 0x11, 0xC9, 0x93,\n  0x77, 0x18, 0x00, 0x70, 0x40, 0xFC, 0x00, 0x00, 0x80, 0x18, 0x01, 0x80,\n  0x38, 0x05, 0x80, 0x5C, 0x09, 0xC1, 0x1C, 0x1F, 0xC2, 0x0C, 0x20, 0xC4,\n  0x0E, 0xF3, 0xF0, 0x3F, 0xE0, 0xC7, 0x0C, 0x71, 0xC7, 0x1C, 0xE1, 0xF0,\n  0x39, 0xC3, 0x8E, 0x38, 0xE3, 0x0E, 0x71, 0xE7, 0x1C, 0xFF, 0x00, 0x07,\n  0xD1, 0xC7, 0x38, 0x27, 0x02, 0x70, 0x0F, 0x00, 0xE0, 0x0E, 0x00, 0xE0,\n  0x0E, 0x00, 0x60, 0x87, 0x18, 0x1E, 0x00, 0x3F, 0xE0, 0x30, 0xE0, 0xC1,\n  0x87, 0x07, 0x1C, 0x1C, 0x60, 0x73, 0x81, 0xCE, 0x07, 0x38, 0x38, 0xC0,\n  0xE7, 0x07, 0x1C, 0x78, 0xFF, 0x80, 0x1F, 0xF8, 0x61, 0xC3, 0x04, 0x38,\n  0x81, 0xCC, 0x0F, 0xE0, 0xE2, 0x07, 0x10, 0x38, 0x81, 0x81, 0x1C, 0x18,\n  0xE3, 0x8F, 0xFC, 0x00, 0x3F, 0xF8, 0x61, 0xC3, 0x04, 0x38, 0x81, 0xCC,\n  0x0F, 0xE0, 0xE2, 0x07, 0x10, 0x38, 0x81, 0x80, 0x1C, 0x00, 0xE0, 0x0F,\n  0x80, 0x00, 0x07, 0x91, 0xC7, 0x38, 0x27, 0x00, 0x70, 0x0F, 0x00, 0xE1,\n  0xFE, 0x0E, 0xE0, 0xCE, 0x0C, 0x60, 0xC7, 0x1C, 0x1F, 0x00, 0x1F, 0x7E,\n  0x1C, 0x38, 0x30, 0x60, 0xE1, 0xC1, 0xC3, 0x83, 0x06, 0x0F, 0xFC, 0x1C,\n  0x38, 0x38, 0x70, 0x60, 0xC1, 0xC3, 0x83, 0x87, 0x0F, 0x9F, 0x00, 0x3F,\n  0x0C, 0x0C, 0x1C, 0x1C, 0x18, 0x38, 0x38, 0x38, 0x30, 0x70, 0x70, 0xF8,\n  0x07, 0xC0, 0xE0, 0x38, 0x0C, 0x07, 0x01, 0xC0, 0x70, 0x18, 0x0E, 0x03,\n  0x80, 0xC3, 0x30, 0xDC, 0x1E, 0x00, 0x1F, 0x78, 0x71, 0x83, 0x18, 0x39,\n  0x81, 0xD0, 0x0D, 0x00, 0xFC, 0x07, 0x60, 0x3B, 0x81, 0x8C, 0x1C, 0x70,\n  0xE1, 0x8F, 0xBE, 0x00, 0x1F, 0x00, 0xC0, 0x0C, 0x01, 0xC0, 0x1C, 0x01,\n  0x80, 0x38, 0x03, 0x80, 0x38, 0x03, 0x01, 0x70, 0x37, 0x0E, 0xFF, 0xE0,\n  0x1E, 0x07, 0x87, 0x07, 0x83, 0x83, 0x82, 0xC3, 0xC1, 0x62, 0xE0, 0xB1,\n  0x70, 0x99, 0x30, 0x4D, 0xB8, 0x27, 0x9C, 0x13, 0x8C, 0x11, 0xC6, 0x0C,\n  0xC7, 0x0F, 0x47, 0xC0, 0x3C, 0x3C, 0x38, 0x20, 0xE0, 0x85, 0xC4, 0x13,\n  0x10, 0x4E, 0x42, 0x3A, 0x08, 0x78, 0x21, 0xE0, 0x83, 0x84, 0x0C, 0x18,\n  0x10, 0x00, 0x40, 0x07, 0xC1, 0xCE, 0x38, 0x73, 0x87, 0x70, 0x77, 0x07,\n  0xF0, 0xFE, 0x0E, 0xE0, 0xEE, 0x1C, 0xE1, 0xC6, 0x38, 0x3E, 0x00, 0x3F,\n  0xC0, 0xC7, 0x0C, 0x71, 0xC7, 0x1C, 0x71, 0x8E, 0x3F, 0xC3, 0x80, 0x30,\n  0x03, 0x00, 0x70, 0x07, 0x00, 0xF8, 0x00, 0x07, 0xC0, 0xCE, 0x38, 0x73,\n  0x87, 0x70, 0x77, 0x07, 0xF0, 0x7E, 0x0E, 0xE0, 0xEE, 0x0C, 0xE1, 0xC6,\n  0x38, 0x36, 0x01, 0x80, 0x3C, 0x2D, 0xFC, 0x3F, 0xC0, 0xE7, 0x0C, 0x71,\n  0xC7, 0x1C, 0x71, 0x8E, 0x3F, 0x83, 0xB8, 0x3B, 0x83, 0x3C, 0x71, 0xC7,\n  0x1C, 0xF9, 0xF0, 0x0C, 0x89, 0x8C, 0x46, 0x23, 0x80, 0xE0, 0x78, 0x0E,\n  0x03, 0x21, 0x90, 0xCC, 0xC9, 0xC0, 0x7F, 0xE9, 0xDF, 0x31, 0x4E, 0x21,\n  0xC0, 0x38, 0x06, 0x01, 0xC0, 0x38, 0x06, 0x00, 0xC0, 0x38, 0x0F, 0xC0,\n  0x7C, 0xF3, 0x82, 0x30, 0x27, 0x04, 0x70, 0x46, 0x04, 0xE0, 0x4E, 0x08,\n  0xE0, 0x8E, 0x08, 0xE1, 0x0F, 0x30, 0x3C, 0x00, 0xFC, 0x73, 0x82, 0x38,\n  0x23, 0x84, 0x38, 0x83, 0x90, 0x39, 0x01, 0xA0, 0x1C, 0x01, 0xC0, 0x18,\n  0x01, 0x00, 0xF9, 0xF7, 0x30, 0xE2, 0x30, 0xC2, 0x38, 0xC4, 0x3B, 0xC4,\n  0x3A, 0xE8, 0x3C, 0xE8, 0x3C, 0xF0, 0x18, 0xF0, 0x18, 0x60, 0x10, 0x60,\n  0x10, 0x40, 0x3F, 0x78, 0x61, 0x83, 0x98, 0x1D, 0x00, 0x70, 0x03, 0x80,\n  0x1C, 0x01, 0x60, 0x0B, 0x80, 0x9C, 0x08, 0x60, 0xC3, 0x8F, 0x7E, 0x00,\n  0xF9, 0xE6, 0x18, 0xC2, 0x1C, 0x81, 0xA0, 0x34, 0x07, 0x00, 0xC0, 0x18,\n  0x07, 0x00, 0xE0, 0x1C, 0x0F, 0xC0, 0x3F, 0xE6, 0x19, 0x87, 0x21, 0xC0,\n  0x30, 0x0E, 0x03, 0x80, 0x60, 0x1C, 0x07, 0x05, 0xC1, 0x38, 0xEF, 0xFC,\n  0x0E, 0x08, 0x18, 0x18, 0x18, 0x10, 0x30, 0x30, 0x30, 0x20, 0x60, 0x60,\n  0x60, 0x40, 0xF0, 0xC6, 0x10, 0xC6, 0x10, 0x86, 0x30, 0x86, 0x30, 0x1E,\n  0x0C, 0x18, 0x20, 0xC1, 0x83, 0x04, 0x18, 0x30, 0x60, 0x83, 0x06, 0x3C,\n  0x00, 0x18, 0x1C, 0x34, 0x26, 0x66, 0x43, 0xC3, 0xFF, 0x80, 0xC6, 0x30,\n  0x0D, 0x9D, 0x8C, 0xCC, 0x6E, 0x26, 0x33, 0x19, 0xBE, 0x66, 0x00, 0x00,\n  0x78, 0x18, 0x30, 0x30, 0x3E, 0x73, 0x63, 0x63, 0x63, 0xC6, 0xC6, 0xCC,\n  0x70, 0x0F, 0x3B, 0x70, 0x70, 0xE0, 0xE0, 0xE2, 0xE4, 0x78, 0x00, 0x00,\n  0xF0, 0x1C, 0x06, 0x01, 0x83, 0xE3, 0x30, 0xCC, 0x63, 0x19, 0xCC, 0x63,\n  0x38, 0xCF, 0x1D, 0x80, 0x0E, 0x75, 0xCB, 0xBE, 0xDE, 0x38, 0x72, 0x78,\n  0x00, 0xE0, 0x34, 0x0C, 0x01, 0x80, 0x30, 0x1F, 0x01, 0x80, 0x30, 0x06,\n  0x01, 0xC0, 0x30, 0x06, 0x00, 0xC0, 0x30, 0x06, 0x04, 0x80, 0xE0, 0x00,\n  0x1C, 0x19, 0xD8, 0xCC, 0x66, 0x60, 0xE1, 0x80, 0xF0, 0x7E, 0x43, 0x21,\n  0x8F, 0x00, 0x00, 0x1E, 0x07, 0x03, 0x01, 0x80, 0xD8, 0xFC, 0x76, 0x33,\n  0x19, 0x99, 0xCC, 0xD6, 0x77, 0x30, 0x39, 0xC0, 0x0F, 0x31, 0x8C, 0xC6,\n  0x31, 0xAE, 0x00, 0x03, 0x81, 0xC0, 0x00, 0x00, 0xE0, 0x30, 0x18, 0x18,\n  0x0C, 0x06, 0x03, 0x03, 0x01, 0x80, 0xC2, 0xC1, 0xC0, 0x00, 0x0F, 0x00,\n  0xC0, 0x60, 0x18, 0x06, 0xF3, 0x90, 0xC8, 0x34, 0x0F, 0x06, 0xC1, 0x98,\n  0x66, 0xB9, 0xC0, 0x03, 0xCC, 0x63, 0x39, 0x8C, 0x66, 0x31, 0x8E, 0x70,\n  0x7B, 0x99, 0xAF, 0xCE, 0x66, 0x63, 0x67, 0x33, 0x31, 0x99, 0x8C, 0xCC,\n  0xE7, 0xC6, 0x30, 0x73, 0x7F, 0x73, 0x73, 0x63, 0x67, 0xE6, 0xC7, 0xC6,\n  0x1E, 0x33, 0x63, 0x63, 0xC3, 0xC6, 0xC6, 0xCC, 0x78, 0x1D, 0xC3, 0xB1,\n  0xCC, 0x63, 0x19, 0xCE, 0x63, 0x18, 0xCC, 0x3E, 0x1C, 0x06, 0x03, 0xE0,\n  0x0D, 0x99, 0x8C, 0xCC, 0x6E, 0x76, 0x33, 0x19, 0x9C, 0x7C, 0x06, 0x07,\n  0x07, 0xC0, 0x76, 0x3A, 0x30, 0x70, 0x60, 0x60, 0x60, 0xE0, 0x3D, 0x14,\n  0x58, 0x38, 0x60, 0xA2, 0xF0, 0x08, 0xCC, 0xF6, 0x31, 0x98, 0xC6, 0x35,\n  0xC0, 0xE3, 0x63, 0x66, 0x66, 0x66, 0xCC, 0xCC, 0xFE, 0xEC, 0xE6, 0xCD,\n  0x8B, 0x26, 0x8E, 0x18, 0x20, 0xE4, 0xD9, 0x36, 0xE5, 0xDA, 0x77, 0x19,\n  0xC6, 0x61, 0x10, 0x39, 0xC7, 0xB0, 0xC0, 0x30, 0x0C, 0x03, 0x00, 0xE1,\n  0x5A, 0x67, 0x00, 0x39, 0x8C, 0xC3, 0x21, 0xA0, 0xD0, 0x68, 0x38, 0x0C,\n  0x04, 0x04, 0x14, 0x0C, 0x00, 0x3E, 0x46, 0x0C, 0x08, 0x10, 0x20, 0x70,\n  0x1A, 0x0E, 0x03, 0x0E, 0x0C, 0x0C, 0x08, 0x18, 0x18, 0x10, 0x60, 0x30,\n  0x30, 0x30, 0x60, 0x60, 0x60, 0x30, 0xFF, 0xF0, 0x0C, 0x06, 0x06, 0x06,\n  0x04, 0x0C, 0x0C, 0x0C, 0x06, 0x18, 0x18, 0x18, 0x30, 0x30, 0x30, 0xE0,\n  0x71, 0x8F };\n\nconst GFXglyph FreeSerifBoldItalic9pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,   5,    0,    1 },   // 0x20 ' '\n  {     0,   6,  13,   7,    1,  -11 },   // 0x21 '!'\n  {    10,   6,   5,  10,    3,  -11 },   // 0x22 '\"'\n  {    14,  11,  13,   9,   -1,  -12 },   // 0x23 '#'\n  {    32,  11,  15,   9,   -1,  -12 },   // 0x24 '$'\n  {    53,  14,  13,  15,    1,  -11 },   // 0x25 '%'\n  {    76,  13,  13,  14,    0,  -11 },   // 0x26 '&'\n  {    98,   2,   5,   5,    3,  -11 },   // 0x27 '''\n  {   100,   5,  16,   6,    1,  -11 },   // 0x28 '('\n  {   110,   5,  16,   6,   -1,  -11 },   // 0x29 ')'\n  {   120,   8,   8,   9,    1,  -11 },   // 0x2A '*'\n  {   128,   9,   9,  10,    0,   -8 },   // 0x2B '+'\n  {   139,   3,   6,   5,   -1,   -2 },   // 0x2C ','\n  {   142,   5,   2,   6,    0,   -4 },   // 0x2D '-'\n  {   144,   3,   3,   4,    0,   -1 },   // 0x2E '.'\n  {   146,   7,  12,   6,    0,  -11 },   // 0x2F '/'\n  {   157,   9,  13,   9,    0,  -11 },   // 0x30 '0'\n  {   172,   8,  13,   9,    0,  -11 },   // 0x31 '1'\n  {   185,   9,  13,   9,    0,  -11 },   // 0x32 '2'\n  {   200,   9,  13,   9,    0,  -11 },   // 0x33 '3'\n  {   215,   9,  12,   9,    0,  -11 },   // 0x34 '4'\n  {   229,   9,  13,   9,    0,  -11 },   // 0x35 '5'\n  {   244,   9,  13,   9,    1,  -11 },   // 0x36 '6'\n  {   259,   9,  12,   9,    1,  -11 },   // 0x37 '7'\n  {   273,   8,  13,   9,    0,  -11 },   // 0x38 '8'\n  {   286,   9,  13,   9,    0,  -11 },   // 0x39 '9'\n  {   301,   5,   9,   5,    0,   -7 },   // 0x3A ':'\n  {   307,   5,  11,   5,    0,   -7 },   // 0x3B ';'\n  {   314,   9,  10,  10,    1,   -9 },   // 0x3C '<'\n  {   326,   9,   5,  10,    1,   -6 },   // 0x3D '='\n  {   332,   9,  10,  10,    1,   -9 },   // 0x3E '>'\n  {   344,   8,  13,   9,    1,  -11 },   // 0x3F '?'\n  {   357,  13,  13,  15,    1,  -12 },   // 0x40 '@'\n  {   379,  12,  13,  13,    0,  -11 },   // 0x41 'A'\n  {   399,  12,  13,  12,    0,  -11 },   // 0x42 'B'\n  {   419,  12,  13,  11,    1,  -11 },   // 0x43 'C'\n  {   439,  14,  13,  13,    0,  -11 },   // 0x44 'D'\n  {   462,  13,  13,  11,    0,  -11 },   // 0x45 'E'\n  {   484,  13,  13,  11,    0,  -11 },   // 0x46 'F'\n  {   506,  12,  13,  13,    1,  -11 },   // 0x47 'G'\n  {   526,  15,  13,  14,    0,  -11 },   // 0x48 'H'\n  {   551,   8,  13,   7,    0,  -11 },   // 0x49 'I'\n  {   564,  10,  14,   9,    0,  -11 },   // 0x4A 'J'\n  {   582,  13,  13,  12,    0,  -11 },   // 0x4B 'K'\n  {   604,  12,  13,  11,    0,  -11 },   // 0x4C 'L'\n  {   624,  17,  13,  16,    0,  -11 },   // 0x4D 'M'\n  {   652,  14,  13,  13,    0,  -11 },   // 0x4E 'N'\n  {   675,  12,  13,  12,    1,  -11 },   // 0x4F 'O'\n  {   695,  12,  13,  11,    0,  -11 },   // 0x50 'P'\n  {   715,  12,  16,  12,    1,  -11 },   // 0x51 'Q'\n  {   739,  12,  13,  12,    0,  -11 },   // 0x52 'R'\n  {   759,   9,  13,   9,    0,  -11 },   // 0x53 'S'\n  {   774,  11,  13,  11,    2,  -11 },   // 0x54 'T'\n  {   792,  12,  13,  13,    2,  -11 },   // 0x55 'U'\n  {   812,  12,  12,  13,    2,  -11 },   // 0x56 'V'\n  {   830,  16,  12,  17,    2,  -11 },   // 0x57 'W'\n  {   854,  13,  13,  13,    0,  -11 },   // 0x58 'X'\n  {   876,  11,  13,  11,    2,  -11 },   // 0x59 'Y'\n  {   894,  11,  13,  10,    0,  -11 },   // 0x5A 'Z'\n  {   912,   8,  15,   6,   -1,  -11 },   // 0x5B '['\n  {   927,   5,  12,   7,    2,  -11 },   // 0x5C '\\'\n  {   935,   7,  15,   6,   -1,  -11 },   // 0x5D ']'\n  {   949,   8,   7,  10,    1,  -11 },   // 0x5E '^'\n  {   956,   9,   1,   9,    0,    3 },   // 0x5F '_'\n  {   958,   4,   3,   6,    2,  -11 },   // 0x60 '`'\n  {   960,   9,   9,   9,    0,   -7 },   // 0x61 'a'\n  {   971,   8,  14,   9,    0,  -12 },   // 0x62 'b'\n  {   985,   8,   9,   8,    0,   -7 },   // 0x63 'c'\n  {   994,  10,  14,   9,    0,  -12 },   // 0x64 'd'\n  {  1012,   7,   9,   7,    0,   -7 },   // 0x65 'e'\n  {  1020,  11,  17,   9,   -2,  -12 },   // 0x66 'f'\n  {  1044,   9,  12,   9,    0,   -7 },   // 0x67 'g'\n  {  1058,   9,  14,  10,    0,  -12 },   // 0x68 'h'\n  {  1074,   5,  13,   5,    1,  -11 },   // 0x69 'i'\n  {  1083,   9,  16,   6,   -1,  -11 },   // 0x6A 'j'\n  {  1101,  10,  14,   9,    0,  -12 },   // 0x6B 'k'\n  {  1119,   5,  14,   5,    1,  -12 },   // 0x6C 'l'\n  {  1128,  13,   9,  14,    0,   -7 },   // 0x6D 'm'\n  {  1143,   8,   9,   9,    0,   -7 },   // 0x6E 'n'\n  {  1152,   8,   9,   9,    0,   -7 },   // 0x6F 'o'\n  {  1161,  10,  12,   9,   -2,   -7 },   // 0x70 'p'\n  {  1176,   9,  12,   9,    0,   -7 },   // 0x71 'q'\n  {  1190,   8,   8,   7,    0,   -7 },   // 0x72 'r'\n  {  1198,   6,   9,   6,    0,   -7 },   // 0x73 's'\n  {  1205,   5,  12,   5,    1,  -10 },   // 0x74 't'\n  {  1213,   8,   9,  10,    1,   -7 },   // 0x75 'u'\n  {  1222,   7,   8,   8,    1,   -7 },   // 0x76 'v'\n  {  1229,  10,   8,  12,    1,   -7 },   // 0x77 'w'\n  {  1239,  10,   9,   9,   -1,   -7 },   // 0x78 'x'\n  {  1251,   9,  12,   8,   -1,   -7 },   // 0x79 'y'\n  {  1265,   8,   9,   7,    0,   -7 },   // 0x7A 'z'\n  {  1274,   8,  16,   6,    0,  -12 },   // 0x7B '{'\n  {  1290,   1,  12,   5,    2,  -11 },   // 0x7C '|'\n  {  1292,   8,  16,   6,   -2,  -12 },   // 0x7D '}'\n  {  1308,   8,   2,  10,    1,   -4 } }; // 0x7E '~'\n\nconst GFXfont FreeSerifBoldItalic9pt7b PROGMEM = {\n  (uint8_t  *)FreeSerifBoldItalic9pt7bBitmaps,\n  (GFXglyph *)FreeSerifBoldItalic9pt7bGlyphs,\n  0x20, 0x7E, 22 };\n\n// Approx. 1982 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeSerifItalic12pt7b.h",
    "content": "const uint8_t FreeSerifItalic12pt7bBitmaps[] PROGMEM = {\n  0x0C, 0x31, 0xC6, 0x18, 0x43, 0x0C, 0x20, 0x84, 0x10, 0x03, 0x0C, 0x30,\n  0x66, 0xCD, 0x12, 0x24, 0x51, 0x00, 0x03, 0x10, 0x11, 0x80, 0x8C, 0x0C,\n  0x40, 0x46, 0x1F, 0xFC, 0x21, 0x01, 0x18, 0x18, 0x80, 0x84, 0x3F, 0xF8,\n  0x62, 0x02, 0x30, 0x31, 0x01, 0x08, 0x08, 0xC0, 0x00, 0x40, 0x08, 0x07,\n  0xC0, 0xCA, 0x18, 0xA1, 0x92, 0x19, 0x01, 0xD0, 0x0F, 0x00, 0x78, 0x03,\n  0xC0, 0x2E, 0x02, 0x64, 0x46, 0x44, 0x64, 0x46, 0x64, 0xC1, 0xF0, 0x08,\n  0x00, 0x80, 0x00, 0x08, 0x0F, 0x0C, 0x0C, 0x7C, 0x0C, 0x22, 0x06, 0x12,\n  0x06, 0x09, 0x03, 0x09, 0x01, 0x84, 0x80, 0xC4, 0x8F, 0x3C, 0x4C, 0x40,\n  0x4C, 0x20, 0x4E, 0x10, 0x26, 0x08, 0x23, 0x08, 0x11, 0x84, 0x10, 0xC4,\n  0x08, 0x3C, 0x00, 0x00, 0xE0, 0x02, 0x60, 0x0C, 0xC0, 0x19, 0x80, 0x36,\n  0x00, 0x70, 0x00, 0xC0, 0x07, 0x9F, 0x33, 0x08, 0xC3, 0x13, 0x06, 0x46,\n  0x0D, 0x0C, 0x0C, 0x18, 0x1C, 0x1C, 0x5C, 0x9F, 0x1E, 0xFA, 0xA0, 0x02,\n  0x08, 0x20, 0xC3, 0x06, 0x18, 0x30, 0xE1, 0x83, 0x06, 0x0C, 0x18, 0x30,\n  0x60, 0x40, 0x80, 0x81, 0x00, 0x08, 0x10, 0x10, 0x20, 0x40, 0xC1, 0x83,\n  0x06, 0x0C, 0x18, 0x70, 0xC1, 0x83, 0x0C, 0x10, 0x41, 0x04, 0x00, 0x18,\n  0x18, 0x18, 0x93, 0x74, 0x38, 0xD7, 0x93, 0x18, 0x18, 0x04, 0x00, 0x80,\n  0x10, 0x02, 0x00, 0x41, 0xFF, 0xC1, 0x00, 0x20, 0x04, 0x00, 0x80, 0x10,\n  0x00, 0x6C, 0x95, 0x00, 0xF8, 0xFC, 0x00, 0x40, 0x18, 0x02, 0x00, 0xC0,\n  0x30, 0x06, 0x01, 0x80, 0x20, 0x0C, 0x01, 0x00, 0x60, 0x18, 0x03, 0x00,\n  0xC0, 0x10, 0x06, 0x00, 0x07, 0x81, 0x98, 0x61, 0x18, 0x33, 0x06, 0xC0,\n  0xD8, 0x1B, 0x03, 0xE0, 0xF8, 0x1F, 0x03, 0x60, 0x6C, 0x19, 0x83, 0x10,\n  0xC3, 0x30, 0x3C, 0x00, 0x01, 0x87, 0xC0, 0xC0, 0x60, 0x30, 0x18, 0x18,\n  0x0C, 0x06, 0x07, 0x03, 0x01, 0x80, 0xC0, 0xC0, 0x60, 0x30, 0xFE, 0x00,\n  0x0F, 0x0C, 0x64, 0x0C, 0x03, 0x00, 0xC0, 0x20, 0x18, 0x0C, 0x02, 0x01,\n  0x00, 0x80, 0x40, 0x20, 0x10, 0x2F, 0xF0, 0x07, 0x86, 0x30, 0x0C, 0x03,\n  0x01, 0x81, 0x81, 0xF0, 0x1E, 0x03, 0x80, 0x60, 0x18, 0x06, 0x01, 0x00,\n  0xCC, 0x63, 0xE0, 0x00, 0x20, 0x0C, 0x03, 0x80, 0xA0, 0x2C, 0x09, 0x82,\n  0x30, 0x84, 0x31, 0x8C, 0x33, 0x06, 0x7F, 0xE0, 0x30, 0x06, 0x00, 0x80,\n  0x30, 0x03, 0xE1, 0x80, 0x20, 0x06, 0x00, 0xF0, 0x0F, 0x00, 0x60, 0x06,\n  0x00, 0xC0, 0x18, 0x03, 0x00, 0x40, 0x18, 0x02, 0x30, 0x87, 0xE0, 0x00,\n  0x70, 0x3C, 0x07, 0x00, 0xE0, 0x1C, 0x03, 0x80, 0x7F, 0x07, 0x18, 0x60,\n  0xCE, 0x0C, 0xC0, 0xCC, 0x0C, 0xC0, 0xCC, 0x18, 0x41, 0x86, 0x30, 0x3E,\n  0x00, 0x7F, 0xF0, 0x18, 0x03, 0x00, 0xC0, 0x10, 0x06, 0x01, 0x80, 0x30,\n  0x0C, 0x01, 0x00, 0x60, 0x08, 0x03, 0x00, 0xC0, 0x10, 0x06, 0x00, 0x0F,\n  0x83, 0x18, 0xC1, 0x98, 0x33, 0x06, 0x71, 0x87, 0x60, 0x70, 0x17, 0x0C,\n  0x71, 0x07, 0x60, 0x6C, 0x0D, 0x81, 0xB0, 0x63, 0x1C, 0x3E, 0x00, 0x07,\n  0x83, 0x18, 0xC1, 0x18, 0x36, 0x06, 0xC0, 0xD8, 0x1B, 0x07, 0x60, 0xE6,\n  0x38, 0x7F, 0x00, 0xC0, 0x30, 0x0C, 0x07, 0x03, 0xC0, 0xC0, 0x00, 0x33,\n  0x30, 0x00, 0x00, 0xCC, 0xC0, 0x18, 0xC6, 0x00, 0x00, 0x00, 0x03, 0x18,\n  0x44, 0x40, 0x00, 0x00, 0x03, 0x00, 0xF0, 0x38, 0x1E, 0x07, 0x80, 0xE0,\n  0x0F, 0x00, 0x1C, 0x00, 0x78, 0x01, 0xE0, 0x07, 0x00, 0x10, 0xFF, 0xF0,\n  0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0xFF, 0x00, 0x0C, 0x00, 0xF0, 0x01,\n  0xC0, 0x07, 0x80, 0x1E, 0x00, 0x70, 0x0F, 0x03, 0xC1, 0xE0, 0x78, 0x0E,\n  0x00, 0x80, 0x00, 0x3E, 0x21, 0x90, 0x60, 0x30, 0x38, 0x38, 0x30, 0x30,\n  0x20, 0x20, 0x10, 0x00, 0x00, 0x06, 0x03, 0x01, 0x80, 0x07, 0xE0, 0x1C,\n  0x18, 0x30, 0x04, 0x60, 0x02, 0x61, 0xDA, 0xC3, 0x31, 0xC6, 0x31, 0xC4,\n  0x31, 0xCC, 0x31, 0xCC, 0x21, 0xCC, 0x62, 0x6C, 0xE4, 0x67, 0x38, 0x30,\n  0x00, 0x1C, 0x08, 0x07, 0xF0, 0x00, 0x20, 0x00, 0xC0, 0x03, 0x80, 0x0B,\n  0x00, 0x16, 0x00, 0x4E, 0x00, 0x9C, 0x02, 0x18, 0x08, 0x30, 0x1F, 0xE0,\n  0x40, 0xC1, 0x81, 0xC2, 0x03, 0x8C, 0x07, 0x3C, 0x1F, 0x80, 0x1F, 0xF0,\n  0x1C, 0x60, 0x60, 0xC1, 0x83, 0x06, 0x0C, 0x38, 0x60, 0xC3, 0x03, 0xF0,\n  0x1C, 0x30, 0x60, 0x61, 0x81, 0x86, 0x06, 0x38, 0x18, 0xC0, 0xC3, 0x06,\n  0x3F, 0xF0, 0x01, 0xF9, 0x06, 0x0F, 0x1C, 0x06, 0x38, 0x02, 0x30, 0x02,\n  0x60, 0x00, 0x60, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00,\n  0xC0, 0x00, 0xC0, 0x08, 0x60, 0x10, 0x30, 0x60, 0x1F, 0x80, 0x1F, 0xF0,\n  0x07, 0x0C, 0x06, 0x06, 0x06, 0x06, 0x06, 0x03, 0x0E, 0x03, 0x0C, 0x03,\n  0x0C, 0x03, 0x1C, 0x03, 0x1C, 0x07, 0x18, 0x06, 0x18, 0x06, 0x38, 0x0C,\n  0x30, 0x18, 0x30, 0x70, 0xFF, 0x80, 0x1F, 0xFF, 0x07, 0x07, 0x06, 0x02,\n  0x06, 0x02, 0x06, 0x00, 0x0E, 0x10, 0x0C, 0x30, 0x0F, 0xF0, 0x1C, 0x20,\n  0x18, 0x20, 0x18, 0x00, 0x18, 0x00, 0x38, 0x04, 0x30, 0x08, 0x30, 0x38,\n  0xFF, 0xF8, 0x1F, 0xFF, 0x07, 0x07, 0x07, 0x02, 0x06, 0x02, 0x06, 0x00,\n  0x0E, 0x10, 0x0C, 0x30, 0x0F, 0xF0, 0x1C, 0x20, 0x1C, 0x20, 0x18, 0x00,\n  0x18, 0x00, 0x38, 0x00, 0x30, 0x00, 0x30, 0x00, 0xFC, 0x00, 0x01, 0xF1,\n  0x06, 0x0F, 0x18, 0x07, 0x38, 0x02, 0x30, 0x02, 0x60, 0x00, 0x60, 0x00,\n  0xE0, 0x00, 0xC0, 0x7F, 0xC0, 0x1C, 0xC0, 0x1C, 0xC0, 0x18, 0xC0, 0x18,\n  0x60, 0x18, 0x30, 0x38, 0x0F, 0xC0, 0x1F, 0xC7, 0xE0, 0xE0, 0x70, 0x18,\n  0x0E, 0x03, 0x01, 0x80, 0x60, 0x30, 0x1C, 0x0E, 0x03, 0x01, 0x80, 0x7F,\n  0xF0, 0x1C, 0x06, 0x03, 0x01, 0xC0, 0x60, 0x30, 0x0C, 0x06, 0x03, 0x81,\n  0xC0, 0x60, 0x38, 0x0C, 0x06, 0x07, 0xE3, 0xF0, 0x1F, 0x83, 0x81, 0x80,\n  0xC0, 0x60, 0x70, 0x30, 0x18, 0x1C, 0x0C, 0x06, 0x03, 0x03, 0x81, 0x80,\n  0xC1, 0xF8, 0x03, 0xF0, 0x0C, 0x00, 0xC0, 0x1C, 0x01, 0x80, 0x18, 0x03,\n  0x80, 0x30, 0x03, 0x00, 0x30, 0x07, 0x00, 0x60, 0x06, 0x0C, 0xE0, 0xCC,\n  0x07, 0x80, 0x1F, 0xCF, 0x83, 0x83, 0x81, 0x81, 0x00, 0xC3, 0x00, 0x62,\n  0x00, 0x72, 0x00, 0x36, 0x00, 0x1E, 0x00, 0x1D, 0x80, 0x0C, 0xE0, 0x06,\n  0x30, 0x03, 0x1C, 0x03, 0x87, 0x01, 0x81, 0x80, 0xC0, 0xE1, 0xF9, 0xFC,\n  0x1F, 0xC0, 0x1C, 0x00, 0x60, 0x01, 0x80, 0x06, 0x00, 0x38, 0x00, 0xC0,\n  0x03, 0x00, 0x1C, 0x00, 0x60, 0x01, 0x80, 0x06, 0x00, 0x38, 0x0C, 0xC0,\n  0x23, 0x03, 0xBF, 0xFE, 0x0F, 0x00, 0x78, 0x38, 0x07, 0x81, 0xC0, 0x38,\n  0x0E, 0x02, 0xC0, 0x70, 0x3E, 0x05, 0xC1, 0x70, 0x2E, 0x13, 0x01, 0x31,\n  0x98, 0x11, 0x89, 0xC0, 0x8C, 0x8C, 0x04, 0x6C, 0x60, 0x23, 0x43, 0x02,\n  0x1C, 0x38, 0x10, 0xE1, 0x81, 0x86, 0x1C, 0x1F, 0x23, 0xF8, 0x1E, 0x07,\n  0xC1, 0xC0, 0x60, 0x70, 0x10, 0x1C, 0x0C, 0x05, 0x82, 0x02, 0x60, 0x80,\n  0x9C, 0x60, 0x23, 0x10, 0x10, 0xC4, 0x04, 0x19, 0x01, 0x06, 0xC0, 0x40,\n  0xE0, 0x20, 0x38, 0x08, 0x0E, 0x06, 0x01, 0x03, 0xE0, 0x40, 0x01, 0xF0,\n  0x0C, 0x10, 0x30, 0x10, 0xC0, 0x33, 0x00, 0x6E, 0x00, 0xD8, 0x01, 0xF0,\n  0x03, 0xC0, 0x0D, 0x80, 0x1B, 0x00, 0x76, 0x00, 0xCC, 0x03, 0x08, 0x0C,\n  0x18, 0x70, 0x0F, 0x80, 0x1F, 0xF0, 0x1C, 0x60, 0x60, 0xC1, 0x83, 0x06,\n  0x0C, 0x38, 0x30, 0xC1, 0x83, 0x0E, 0x1F, 0xE0, 0x60, 0x01, 0x80, 0x06,\n  0x00, 0x38, 0x00, 0xC0, 0x03, 0x00, 0x3F, 0x00, 0x01, 0xF0, 0x06, 0x10,\n  0x30, 0x30, 0xC0, 0x33, 0x00, 0x66, 0x00, 0xD8, 0x01, 0xB0, 0x03, 0xE0,\n  0x0F, 0x80, 0x1B, 0x00, 0x36, 0x00, 0xCC, 0x03, 0x98, 0x06, 0x18, 0x18,\n  0x18, 0xC0, 0x0E, 0x00, 0x20, 0x01, 0xF8, 0x36, 0x7F, 0x80, 0x1F, 0xF0,\n  0x1C, 0x60, 0x60, 0xC1, 0x83, 0x06, 0x0C, 0x38, 0x70, 0xC3, 0x83, 0xF8,\n  0x1D, 0xC0, 0x63, 0x01, 0x8C, 0x06, 0x18, 0x38, 0x60, 0xC1, 0xC3, 0x03,\n  0x3F, 0x0F, 0x07, 0x90, 0xC7, 0x18, 0x21, 0x82, 0x18, 0x01, 0xC0, 0x0E,\n  0x00, 0x70, 0x03, 0x80, 0x1C, 0x00, 0xC4, 0x0C, 0x40, 0xC6, 0x08, 0xE1,\n  0x89, 0xE0, 0x7F, 0xFE, 0xC7, 0x1D, 0x0C, 0x14, 0x18, 0x20, 0x70, 0x00,\n  0xE0, 0x01, 0x80, 0x03, 0x00, 0x0E, 0x00, 0x18, 0x00, 0x30, 0x00, 0x60,\n  0x01, 0xC0, 0x03, 0x00, 0x0E, 0x00, 0x7F, 0x80, 0x7E, 0x1F, 0x38, 0x0C,\n  0x38, 0x0C, 0x30, 0x08, 0x30, 0x08, 0x70, 0x08, 0x70, 0x10, 0x60, 0x10,\n  0x60, 0x10, 0xE0, 0x10, 0xC0, 0x20, 0xC0, 0x20, 0xC0, 0x60, 0xC0, 0x40,\n  0x61, 0x80, 0x3F, 0x00, 0xFC, 0x3E, 0xE0, 0x18, 0xC0, 0x21, 0x80, 0xC3,\n  0x81, 0x07, 0x04, 0x0E, 0x08, 0x0C, 0x20, 0x18, 0x80, 0x31, 0x00, 0x64,\n  0x00, 0xF0, 0x01, 0xE0, 0x01, 0x80, 0x02, 0x00, 0x04, 0x00, 0xFD, 0xF8,\n  0xF7, 0x07, 0x06, 0x30, 0x60, 0x63, 0x07, 0x04, 0x30, 0x70, 0x83, 0x8F,\n  0x08, 0x38, 0xB1, 0x03, 0x93, 0x10, 0x19, 0x32, 0x01, 0xA3, 0x20, 0x1A,\n  0x34, 0x01, 0xC3, 0x40, 0x1C, 0x38, 0x01, 0x83, 0x00, 0x18, 0x30, 0x01,\n  0x02, 0x00, 0x1F, 0x9F, 0x0E, 0x06, 0x06, 0x04, 0x07, 0x08, 0x03, 0x10,\n  0x03, 0x20, 0x03, 0xC0, 0x01, 0x80, 0x01, 0xC0, 0x03, 0xC0, 0x06, 0xE0,\n  0x0C, 0x60, 0x18, 0x60, 0x30, 0x70, 0x70, 0x78, 0xF8, 0xFC, 0xFC, 0xFB,\n  0x81, 0x8C, 0x08, 0x60, 0x83, 0x8C, 0x0C, 0xC0, 0x64, 0x03, 0xC0, 0x0C,\n  0x00, 0xE0, 0x07, 0x00, 0x30, 0x01, 0x80, 0x1C, 0x00, 0xC0, 0x1F, 0xC0,\n  0x1F, 0xFE, 0x30, 0x38, 0xC0, 0xF1, 0x01, 0xC0, 0x07, 0x00, 0x1C, 0x00,\n  0x70, 0x01, 0xE0, 0x03, 0x80, 0x0E, 0x00, 0x38, 0x00, 0xE0, 0x01, 0xC0,\n  0x47, 0x01, 0x1C, 0x06, 0x7F, 0xF8, 0x07, 0x04, 0x08, 0x08, 0x08, 0x18,\n  0x10, 0x10, 0x10, 0x20, 0x20, 0x20, 0x20, 0x40, 0x40, 0x40, 0x80, 0x80,\n  0x80, 0xE0, 0xC0, 0xC0, 0x40, 0x60, 0x20, 0x30, 0x30, 0x18, 0x18, 0x08,\n  0x0C, 0x04, 0x06, 0x06, 0x03, 0x03, 0x0E, 0x04, 0x08, 0x10, 0x60, 0x81,\n  0x02, 0x04, 0x18, 0x20, 0x40, 0x81, 0x02, 0x08, 0x10, 0x20, 0x47, 0x80,\n  0x0C, 0x03, 0x81, 0xE0, 0x4C, 0x33, 0x08, 0x66, 0x19, 0x03, 0xC0, 0xC0,\n  0xFF, 0xF0, 0xCE, 0x63, 0x07, 0xA0, 0xCE, 0x18, 0x63, 0x04, 0x60, 0xC6,\n  0x0C, 0xC0, 0xCC, 0x18, 0xC3, 0x8C, 0x5A, 0x79, 0xC0, 0x38, 0x06, 0x01,\n  0x80, 0x40, 0x30, 0x0C, 0xE3, 0xCC, 0xC3, 0x70, 0xD8, 0x36, 0x19, 0x06,\n  0xC3, 0x30, 0x8C, 0xC3, 0xE0, 0x0F, 0x0C, 0xCC, 0x6C, 0x06, 0x06, 0x03,\n  0x01, 0x80, 0xC0, 0x73, 0x1E, 0x00, 0x00, 0x70, 0x01, 0x80, 0x0C, 0x00,\n  0x60, 0x02, 0x03, 0xF0, 0x31, 0x83, 0x08, 0x30, 0xC3, 0x06, 0x18, 0x31,\n  0x81, 0x8C, 0x18, 0x61, 0xCB, 0x16, 0x8F, 0x38, 0x07, 0x19, 0x31, 0x63,\n  0x62, 0xEC, 0xD0, 0xC0, 0xC0, 0xE6, 0x78, 0x00, 0x38, 0x01, 0x30, 0x0C,\n  0x00, 0x20, 0x01, 0x80, 0x06, 0x00, 0xFE, 0x00, 0x40, 0x03, 0x00, 0x0C,\n  0x00, 0x30, 0x00, 0x80, 0x06, 0x00, 0x18, 0x00, 0x60, 0x01, 0x80, 0x04,\n  0x00, 0x30, 0x00, 0xC0, 0x02, 0x00, 0x90, 0x03, 0x80, 0x00, 0x07, 0xC0,\n  0xC7, 0x18, 0x61, 0x86, 0x18, 0xE1, 0x8C, 0x07, 0x80, 0x80, 0x1C, 0x00,\n  0xF0, 0x33, 0x84, 0x18, 0x80, 0x88, 0x08, 0x61, 0x03, 0xE0, 0x1C, 0x00,\n  0xC0, 0x0C, 0x00, 0xC0, 0x18, 0x01, 0x8E, 0x1B, 0x61, 0xC6, 0x38, 0x63,\n  0x8C, 0x30, 0xC3, 0x0C, 0x60, 0xC6, 0x1A, 0x61, 0xA4, 0x1C, 0x18, 0xC6,\n  0x00, 0x0B, 0xC6, 0x23, 0x18, 0x8C, 0x63, 0x5C, 0x01, 0x80, 0xC0, 0x60,\n  0x00, 0x00, 0x0C, 0x1E, 0x02, 0x03, 0x01, 0x80, 0xC0, 0x40, 0x60, 0x30,\n  0x18, 0x08, 0x0C, 0x06, 0x02, 0x1B, 0x0F, 0x00, 0x1C, 0x01, 0x80, 0x30,\n  0x06, 0x01, 0x80, 0x33, 0xC6, 0x30, 0x88, 0x32, 0x06, 0x80, 0xF0, 0x1B,\n  0x06, 0x60, 0xC4, 0x18, 0xD2, 0x0C, 0x3C, 0x61, 0x86, 0x18, 0xC3, 0x0C,\n  0x21, 0x86, 0x18, 0x43, 0x2D, 0x38, 0x78, 0xE7, 0x0D, 0xB5, 0x8D, 0x1C,\n  0xC7, 0x0C, 0x63, 0x8E, 0x31, 0x86, 0x30, 0xC3, 0x18, 0xC1, 0x0C, 0x61,\n  0x84, 0xB0, 0xC6, 0xB0, 0x63, 0x80, 0x78, 0xE1, 0xB6, 0x14, 0x63, 0x84,\n  0x38, 0xC3, 0x0C, 0x70, 0x86, 0x18, 0x61, 0x96, 0x1A, 0xC1, 0xC0, 0x0F,\n  0x06, 0x63, 0x0D, 0x83, 0x60, 0xF0, 0x3C, 0x1B, 0x06, 0xC3, 0x39, 0x87,\n  0x80, 0x1E, 0xF0, 0x39, 0xC1, 0x86, 0x0C, 0x30, 0xC1, 0x86, 0x0C, 0x30,\n  0xC3, 0x06, 0x18, 0x60, 0xC6, 0x07, 0xC0, 0x60, 0x03, 0x00, 0x18, 0x00,\n  0xC0, 0x1F, 0x00, 0x07, 0x81, 0x9C, 0x63, 0x98, 0x76, 0x0C, 0xC1, 0xB0,\n  0x76, 0x0E, 0xC3, 0x98, 0xB1, 0xE6, 0x00, 0x80, 0x30, 0x06, 0x00, 0xC0,\n  0xFC, 0x79, 0x8F, 0xC5, 0x07, 0x03, 0x01, 0x80, 0xC0, 0xC0, 0x60, 0x30,\n  0x10, 0x00, 0x1E, 0x98, 0xCC, 0x27, 0x11, 0x80, 0xE0, 0x39, 0x0C, 0x86,\n  0x62, 0x2E, 0x00, 0x08, 0x67, 0xCC, 0x30, 0xC6, 0x18, 0x61, 0x8C, 0x34,\n  0xE0, 0xF0, 0xCC, 0x19, 0x83, 0x30, 0xC6, 0x18, 0x87, 0x31, 0x66, 0x3C,\n  0xCB, 0x1A, 0x6B, 0x8E, 0x00, 0x70, 0xCC, 0x33, 0x04, 0xC2, 0x18, 0x86,\n  0x41, 0x90, 0x68, 0x1C, 0x06, 0x01, 0x00, 0x61, 0x0F, 0x84, 0x36, 0x30,\n  0xDC, 0xC1, 0x35, 0x08, 0xD4, 0x23, 0x91, 0x0E, 0x48, 0x30, 0xE0, 0xC3,\n  0x02, 0x08, 0x00, 0x0C, 0x63, 0x4A, 0x07, 0x00, 0x70, 0x06, 0x00, 0x20,\n  0x07, 0x00, 0xB0, 0x0B, 0x21, 0x14, 0xE1, 0x80, 0x38, 0x63, 0x0C, 0x30,\n  0x86, 0x10, 0xC4, 0x0C, 0x81, 0xA0, 0x34, 0x07, 0x00, 0x60, 0x08, 0x02,\n  0x00, 0x40, 0x10, 0x04, 0x07, 0x00, 0x1F, 0x90, 0x80, 0x80, 0xC0, 0xC0,\n  0x40, 0x60, 0x60, 0x60, 0x38, 0x3E, 0x03, 0xA0, 0x60, 0x00, 0x83, 0x81,\n  0x01, 0x80, 0xC0, 0x40, 0x60, 0x30, 0x10, 0x10, 0x1C, 0x06, 0x03, 0x03,\n  0x01, 0x80, 0xC0, 0x40, 0x60, 0x30, 0x18, 0x07, 0x00, 0xFF, 0xFF, 0x07,\n  0x00, 0xC0, 0x60, 0x30, 0x10, 0x18, 0x0C, 0x06, 0x06, 0x03, 0x01, 0x80,\n  0x60, 0x40, 0x60, 0x30, 0x10, 0x18, 0x0C, 0x06, 0x06, 0x06, 0x00, 0x78,\n  0x18, 0x8C, 0x0F, 0x00 };\n\nconst GFXglyph FreeSerifItalic12pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,   6,    0,    1 },   // 0x20 ' '\n  {     0,   6,  16,   8,    1,  -15 },   // 0x21 '!'\n  {    12,   7,   6,   8,    3,  -15 },   // 0x22 '\"'\n  {    18,  13,  16,  12,    0,  -15 },   // 0x23 '#'\n  {    44,  12,  20,  12,    0,  -17 },   // 0x24 '$'\n  {    74,  17,  17,  20,    2,  -16 },   // 0x25 '%'\n  {   111,  15,  16,  19,    2,  -15 },   // 0x26 '&'\n  {   141,   2,   6,   5,    4,  -15 },   // 0x27 '''\n  {   143,   7,  20,   8,    1,  -15 },   // 0x28 '('\n  {   161,   7,  20,   8,    0,  -15 },   // 0x29 ')'\n  {   179,   8,  10,  12,    4,  -15 },   // 0x2A '*'\n  {   189,  11,  11,  16,    2,  -10 },   // 0x2B '+'\n  {   205,   3,   6,   6,    0,   -2 },   // 0x2C ','\n  {   208,   5,   1,   8,    1,   -5 },   // 0x2D '-'\n  {   209,   2,   3,   6,    1,   -2 },   // 0x2E '.'\n  {   210,  11,  16,   7,    0,  -15 },   // 0x2F '/'\n  {   232,  11,  17,  12,    1,  -16 },   // 0x30 '0'\n  {   256,   9,  17,  12,    1,  -16 },   // 0x31 '1'\n  {   276,  10,  15,  12,    1,  -14 },   // 0x32 '2'\n  {   295,  10,  16,  12,    1,  -15 },   // 0x33 '3'\n  {   315,  11,  16,  12,    0,  -15 },   // 0x34 '4'\n  {   337,  11,  16,  12,    0,  -15 },   // 0x35 '5'\n  {   359,  12,  17,  12,    1,  -16 },   // 0x36 '6'\n  {   385,  11,  16,  12,    2,  -15 },   // 0x37 '7'\n  {   407,  11,  17,  12,    1,  -16 },   // 0x38 '8'\n  {   431,  11,  17,  12,    1,  -16 },   // 0x39 '9'\n  {   455,   4,  11,   6,    1,  -10 },   // 0x3A ':'\n  {   461,   5,  14,   6,    0,  -10 },   // 0x3B ';'\n  {   470,  12,  13,  14,    1,  -12 },   // 0x3C '<'\n  {   490,  12,   6,  16,    2,   -8 },   // 0x3D '='\n  {   499,  12,  13,  14,    2,  -12 },   // 0x3E '>'\n  {   519,   9,  16,  11,    3,  -15 },   // 0x3F '?'\n  {   537,  16,  16,  19,    2,  -15 },   // 0x40 '@'\n  {   569,  15,  15,  16,    0,  -14 },   // 0x41 'A'\n  {   598,  14,  16,  14,    0,  -15 },   // 0x42 'B'\n  {   626,  16,  16,  15,    1,  -15 },   // 0x43 'C'\n  {   658,  16,  16,  17,    0,  -15 },   // 0x44 'D'\n  {   690,  16,  16,  14,    0,  -15 },   // 0x45 'E'\n  {   722,  16,  16,  14,    0,  -15 },   // 0x46 'F'\n  {   754,  16,  16,  17,    1,  -15 },   // 0x47 'G'\n  {   786,  19,  16,  17,    0,  -15 },   // 0x48 'H'\n  {   824,   9,  16,   8,    0,  -15 },   // 0x49 'I'\n  {   842,  12,  16,  10,    0,  -15 },   // 0x4A 'J'\n  {   866,  17,  16,  15,    0,  -15 },   // 0x4B 'K'\n  {   900,  14,  16,  14,    0,  -15 },   // 0x4C 'L'\n  {   928,  21,  16,  20,    0,  -15 },   // 0x4D 'M'\n  {   970,  18,  16,  16,    0,  -15 },   // 0x4E 'N'\n  {  1006,  15,  16,  16,    1,  -15 },   // 0x4F 'O'\n  {  1036,  14,  16,  14,    0,  -15 },   // 0x50 'P'\n  {  1064,  15,  20,  16,    1,  -15 },   // 0x51 'Q'\n  {  1102,  14,  16,  15,    0,  -15 },   // 0x52 'R'\n  {  1130,  12,  16,  11,    0,  -15 },   // 0x53 'S'\n  {  1154,  15,  16,  14,    2,  -15 },   // 0x54 'T'\n  {  1184,  16,  16,  17,    3,  -15 },   // 0x55 'U'\n  {  1216,  15,  16,  16,    3,  -15 },   // 0x56 'V'\n  {  1246,  20,  16,  21,    3,  -15 },   // 0x57 'W'\n  {  1286,  16,  16,  16,    0,  -15 },   // 0x58 'X'\n  {  1318,  13,  16,  14,    3,  -15 },   // 0x59 'Y'\n  {  1344,  15,  16,  14,    0,  -15 },   // 0x5A 'Z'\n  {  1374,   8,  20,   9,    1,  -15 },   // 0x5B '['\n  {  1394,   8,  16,  12,    3,  -15 },   // 0x5C '\\'\n  {  1410,   7,  20,   9,    1,  -15 },   // 0x5D ']'\n  {  1428,  10,   9,  10,    0,  -15 },   // 0x5E '^'\n  {  1440,  12,   1,  12,    0,    3 },   // 0x5F '_'\n  {  1442,   4,   4,   6,    3,  -15 },   // 0x60 '`'\n  {  1444,  12,  11,  12,    0,  -10 },   // 0x61 'a'\n  {  1461,  10,  16,  11,    1,  -15 },   // 0x62 'b'\n  {  1481,   9,  11,  10,    1,  -10 },   // 0x63 'c'\n  {  1494,  13,  16,  12,    0,  -15 },   // 0x64 'd'\n  {  1520,   8,  11,  10,    1,  -10 },   // 0x65 'e'\n  {  1531,  14,  22,  10,   -2,  -16 },   // 0x66 'f'\n  {  1570,  12,  16,  11,   -1,  -10 },   // 0x67 'g'\n  {  1594,  12,  16,  12,    0,  -15 },   // 0x68 'h'\n  {  1618,   5,  16,   6,    1,  -15 },   // 0x69 'i'\n  {  1628,   9,  21,   7,   -2,  -15 },   // 0x6A 'j'\n  {  1652,  11,  16,  11,    0,  -15 },   // 0x6B 'k'\n  {  1674,   6,  16,   6,    1,  -15 },   // 0x6C 'l'\n  {  1686,  17,  11,  17,    0,  -10 },   // 0x6D 'm'\n  {  1710,  12,  11,  12,    0,  -10 },   // 0x6E 'n'\n  {  1727,  10,  11,  11,    1,  -10 },   // 0x6F 'o'\n  {  1741,  13,  16,  11,   -2,  -10 },   // 0x70 'p'\n  {  1767,  11,  16,  12,    0,  -10 },   // 0x71 'q'\n  {  1789,   9,  11,   9,    0,  -10 },   // 0x72 'r'\n  {  1802,   9,  11,   8,    0,  -10 },   // 0x73 's'\n  {  1815,   6,  13,   6,    1,  -12 },   // 0x74 't'\n  {  1825,  11,  11,  12,    1,  -10 },   // 0x75 'u'\n  {  1841,  10,  11,  11,    1,  -10 },   // 0x76 'v'\n  {  1855,  14,  11,  16,    2,  -10 },   // 0x77 'w'\n  {  1875,  12,  11,  10,   -1,  -10 },   // 0x78 'x'\n  {  1892,  11,  16,  11,    0,  -10 },   // 0x79 'y'\n  {  1914,   9,  13,   9,    0,  -10 },   // 0x7A 'z'\n  {  1929,   9,  21,  10,    1,  -16 },   // 0x7B '{'\n  {  1953,   1,  16,   7,    3,  -15 },   // 0x7C '|'\n  {  1955,   9,  21,  10,    0,  -16 },   // 0x7D '}'\n  {  1979,  11,   3,  13,    1,   -6 } }; // 0x7E '~'\n\nconst GFXfont FreeSerifItalic12pt7b PROGMEM = {\n  (uint8_t  *)FreeSerifItalic12pt7bBitmaps,\n  (GFXglyph *)FreeSerifItalic12pt7bGlyphs,\n  0x20, 0x7E, 29 };\n\n// Approx. 2656 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeSerifItalic18pt7b.h",
    "content": "const uint8_t FreeSerifItalic18pt7bBitmaps[] PROGMEM = {\n  0x01, 0xC0, 0xF0, 0x3C, 0x0F, 0x03, 0x81, 0xE0, 0x70, 0x1C, 0x06, 0x01,\n  0x80, 0xC0, 0x30, 0x0C, 0x02, 0x01, 0x80, 0x40, 0x10, 0x00, 0x00, 0x01,\n  0x80, 0xF0, 0x3C, 0x06, 0x00, 0x38, 0x77, 0x8F, 0x78, 0xF7, 0x0E, 0x60,\n  0xE6, 0x0C, 0xC1, 0x8C, 0x18, 0x81, 0x00, 0x00, 0x60, 0xC0, 0x0C, 0x38,\n  0x03, 0x86, 0x00, 0x60, 0xC0, 0x0C, 0x38, 0x03, 0x06, 0x00, 0x60, 0xC0,\n  0xFF, 0xFF, 0x1F, 0xFF, 0xE0, 0x61, 0xC0, 0x1C, 0x30, 0x03, 0x06, 0x00,\n  0x61, 0xC0, 0x18, 0x30, 0x3F, 0xFF, 0xC7, 0xFF, 0xF8, 0x18, 0x30, 0x03,\n  0x0E, 0x00, 0xE1, 0x80, 0x18, 0x30, 0x03, 0x0C, 0x00, 0xC1, 0x80, 0x18,\n  0x70, 0x00, 0x00, 0x08, 0x00, 0x30, 0x00, 0x40, 0x0F, 0xC0, 0x61, 0xE1,\n  0x86, 0xC6, 0x0D, 0x8C, 0x1A, 0x18, 0x24, 0x38, 0xC0, 0x39, 0x80, 0x7F,\n  0x00, 0x7E, 0x00, 0x3E, 0x00, 0x3E, 0x00, 0x7C, 0x00, 0xDC, 0x03, 0x38,\n  0x06, 0x32, 0x0C, 0x64, 0x18, 0xDC, 0x71, 0xB8, 0xC6, 0x39, 0x8C, 0x3F,\n  0x30, 0x1F, 0x80, 0x18, 0x00, 0x30, 0x00, 0x60, 0x00, 0x07, 0x80, 0x60,\n  0x0F, 0xE0, 0xE0, 0x0F, 0x0F, 0xB0, 0x0E, 0x04, 0x30, 0x07, 0x02, 0x18,\n  0x07, 0x01, 0x18, 0x03, 0x00, 0x8C, 0x01, 0x80, 0x8C, 0x00, 0xC0, 0x4C,\n  0x00, 0x60, 0x66, 0x1F, 0x30, 0x66, 0x1F, 0xCC, 0x63, 0x1C, 0x67, 0xE3,\n  0x1C, 0x19, 0xE1, 0x1C, 0x04, 0x01, 0x8C, 0x02, 0x00, 0x8E, 0x01, 0x00,\n  0xC7, 0x00, 0x80, 0xC3, 0x00, 0x80, 0x61, 0x80, 0xC0, 0x60, 0xC0, 0xC0,\n  0x20, 0x70, 0xE0, 0x30, 0x1F, 0xC0, 0x10, 0x07, 0xC0, 0x00, 0x1E, 0x00,\n  0x00, 0xFC, 0x00, 0x07, 0x18, 0x00, 0x18, 0x60, 0x00, 0xE1, 0x80, 0x03,\n  0x8C, 0x00, 0x0E, 0x60, 0x00, 0x3B, 0x00, 0x00, 0xF0, 0x00, 0x07, 0x80,\n  0x00, 0x7F, 0x1F, 0xC3, 0x3C, 0x1C, 0x38, 0x70, 0x61, 0xE1, 0xE3, 0x87,\n  0x07, 0x8C, 0x3C, 0x0F, 0x60, 0xF0, 0x3D, 0x03, 0xC0, 0x78, 0x0F, 0x01,\n  0xE0, 0x3E, 0x07, 0xC0, 0x7C, 0x77, 0x84, 0xFF, 0x8F, 0xE1, 0xF8, 0x0F,\n  0x00, 0x3B, 0xDE, 0xE7, 0x33, 0x18, 0x80, 0x00, 0x80, 0x80, 0x80, 0x80,\n  0xC0, 0xC0, 0xE0, 0x60, 0x70, 0x38, 0x18, 0x0C, 0x0E, 0x07, 0x03, 0x01,\n  0x80, 0xC0, 0x60, 0x30, 0x18, 0x0C, 0x06, 0x01, 0x00, 0x80, 0x40, 0x30,\n  0x08, 0x04, 0x02, 0x00, 0x04, 0x01, 0x00, 0x80, 0x60, 0x10, 0x08, 0x04,\n  0x03, 0x01, 0x80, 0xC0, 0x60, 0x30, 0x18, 0x0C, 0x0E, 0x07, 0x03, 0x81,\n  0x80, 0xC0, 0xE0, 0x60, 0x30, 0x30, 0x18, 0x18, 0x08, 0x08, 0x08, 0x08,\n  0x00, 0x06, 0x00, 0x60, 0x06, 0x0C, 0x43, 0xE4, 0xF1, 0x58, 0x0E, 0x00,\n  0xF0, 0x74, 0xEE, 0x47, 0xC4, 0x30, 0x60, 0x06, 0x00, 0x60, 0x01, 0x80,\n  0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80,\n  0x01, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80,\n  0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x31, 0xCE,\n  0x31, 0x08, 0x98, 0xFF, 0xFF, 0x6F, 0xF6, 0x00, 0x06, 0x00, 0x0E, 0x00,\n  0x0C, 0x00, 0x1C, 0x00, 0x38, 0x00, 0x30, 0x00, 0x70, 0x00, 0x60, 0x00,\n  0xE0, 0x00, 0xC0, 0x01, 0xC0, 0x03, 0x80, 0x03, 0x00, 0x07, 0x00, 0x06,\n  0x00, 0x0E, 0x00, 0x0C, 0x00, 0x1C, 0x00, 0x38, 0x00, 0x30, 0x00, 0x70,\n  0x00, 0x60, 0x00, 0xE0, 0x00, 0x00, 0x78, 0x00, 0xC3, 0x00, 0xC1, 0xC0,\n  0xC0, 0x60, 0xE0, 0x30, 0xE0, 0x1C, 0x70, 0x0E, 0x70, 0x07, 0x38, 0x03,\n  0xBC, 0x01, 0xDC, 0x01, 0xEE, 0x00, 0xFF, 0x00, 0x7F, 0x80, 0x3B, 0x80,\n  0x1D, 0xC0, 0x1E, 0xE0, 0x0E, 0x70, 0x0F, 0x38, 0x07, 0x1C, 0x07, 0x06,\n  0x03, 0x83, 0x83, 0x80, 0xC3, 0x00, 0x1F, 0x00, 0x00, 0xF0, 0x7F, 0x00,\n  0x70, 0x07, 0x00, 0xE0, 0x0E, 0x00, 0xE0, 0x0E, 0x01, 0xC0, 0x1C, 0x01,\n  0xC0, 0x38, 0x03, 0x80, 0x38, 0x03, 0x80, 0x70, 0x07, 0x00, 0x70, 0x0E,\n  0x00, 0xE0, 0x0E, 0x00, 0xE0, 0x1E, 0x0F, 0xF8, 0x01, 0xF0, 0x07, 0xFC,\n  0x0C, 0x3E, 0x10, 0x1F, 0x20, 0x0F, 0x00, 0x0F, 0x00, 0x0F, 0x00, 0x0F,\n  0x00, 0x1E, 0x00, 0x1C, 0x00, 0x38, 0x00, 0x30, 0x00, 0x70, 0x00, 0xE0,\n  0x01, 0xC0, 0x03, 0x80, 0x07, 0x00, 0x0E, 0x00, 0x1C, 0x00, 0x38, 0x04,\n  0x30, 0x0C, 0x7F, 0xF8, 0xFF, 0xF0, 0x00, 0x7C, 0x00, 0xFF, 0x00, 0xC3,\n  0xC0, 0x80, 0xF0, 0x00, 0x78, 0x00, 0x3C, 0x00, 0x1C, 0x00, 0x1C, 0x00,\n  0x38, 0x00, 0xF0, 0x03, 0xFC, 0x00, 0x1F, 0x00, 0x03, 0xC0, 0x01, 0xE0,\n  0x00, 0x70, 0x00, 0x38, 0x00, 0x1C, 0x00, 0x0E, 0x00, 0x06, 0x00, 0x07,\n  0x00, 0x03, 0x07, 0x87, 0x03, 0xFF, 0x00, 0xFC, 0x00, 0x00, 0x01, 0x80,\n  0x01, 0x80, 0x01, 0xC0, 0x01, 0xE0, 0x01, 0xF0, 0x01, 0xB0, 0x01, 0xB8,\n  0x01, 0x9C, 0x01, 0x8C, 0x00, 0x86, 0x00, 0x87, 0x00, 0x83, 0x80, 0x81,\n  0x80, 0x81, 0xC0, 0xC0, 0xE0, 0xC0, 0x70, 0xFF, 0xFF, 0x7F, 0xFF, 0x00,\n  0x1C, 0x00, 0x0C, 0x00, 0x0E, 0x00, 0x07, 0x00, 0x03, 0x80, 0x01, 0x80,\n  0x01, 0xFF, 0x01, 0xFF, 0x02, 0x00, 0x02, 0x00, 0x06, 0x00, 0x07, 0x00,\n  0x0F, 0xC0, 0x0F, 0xF0, 0x00, 0xF8, 0x00, 0x38, 0x00, 0x1C, 0x00, 0x1C,\n  0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x08, 0x00, 0x18,\n  0x00, 0x30, 0x00, 0x30, 0x70, 0xE0, 0xFF, 0x80, 0x7E, 0x00, 0x00, 0x03,\n  0x80, 0x1F, 0x00, 0x3C, 0x00, 0x3C, 0x00, 0x38, 0x00, 0x38, 0x00, 0x38,\n  0x00, 0x3C, 0x00, 0x3D, 0xF0, 0x1F, 0xFE, 0x1F, 0x0F, 0x8E, 0x03, 0xC7,\n  0x00, 0xF7, 0x00, 0x7B, 0x80, 0x3D, 0x80, 0x1E, 0xC0, 0x0F, 0x60, 0x0F,\n  0xB0, 0x07, 0x98, 0x03, 0xC4, 0x03, 0xC3, 0x03, 0xC0, 0xC3, 0x80, 0x1F,\n  0x00, 0x3F, 0xFF, 0x7F, 0xFE, 0x40, 0x0E, 0x80, 0x0C, 0x00, 0x18, 0x00,\n  0x18, 0x00, 0x30, 0x00, 0x70, 0x00, 0x60, 0x00, 0xC0, 0x01, 0xC0, 0x01,\n  0x80, 0x03, 0x80, 0x03, 0x00, 0x06, 0x00, 0x0E, 0x00, 0x0C, 0x00, 0x1C,\n  0x00, 0x18, 0x00, 0x30, 0x00, 0x70, 0x00, 0x60, 0x00, 0xE0, 0x00, 0x00,\n  0xF8, 0x03, 0x0E, 0x06, 0x06, 0x0C, 0x03, 0x0C, 0x03, 0x0C, 0x03, 0x0C,\n  0x03, 0x0E, 0x06, 0x07, 0x8E, 0x07, 0xD8, 0x03, 0xE0, 0x07, 0xF0, 0x1C,\n  0xF8, 0x30, 0x3C, 0x60, 0x1C, 0x60, 0x0E, 0xC0, 0x06, 0xC0, 0x06, 0xC0,\n  0x06, 0xC0, 0x06, 0xE0, 0x0C, 0x60, 0x18, 0x38, 0x30, 0x0F, 0xC0, 0x01,\n  0xF8, 0x07, 0x8C, 0x0E, 0x06, 0x1E, 0x02, 0x3C, 0x03, 0x3C, 0x03, 0x78,\n  0x03, 0x78, 0x03, 0x78, 0x03, 0x78, 0x07, 0x78, 0x07, 0x78, 0x07, 0x3C,\n  0x0E, 0x3E, 0x1E, 0x1F, 0xEE, 0x07, 0x9C, 0x00, 0x38, 0x00, 0x78, 0x00,\n  0x70, 0x01, 0xE0, 0x03, 0xC0, 0x0F, 0x00, 0x3C, 0x00, 0xE0, 0x00, 0x0C,\n  0x3C, 0x78, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0F, 0x1E, 0x18,\n  0x00, 0x07, 0x03, 0xC1, 0xE0, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0x02, 0x03, 0x81, 0xC0, 0xE0, 0x30, 0x10, 0x10, 0x10, 0x00, 0x00,\n  0x00, 0x00, 0xC0, 0x01, 0xF0, 0x01, 0xF8, 0x01, 0xF8, 0x01, 0xF0, 0x01,\n  0xF0, 0x03, 0xF0, 0x03, 0xF0, 0x00, 0xF0, 0x00, 0x3E, 0x00, 0x07, 0xE0,\n  0x00, 0x7E, 0x00, 0x03, 0xE0, 0x00, 0x3E, 0x00, 0x03, 0xF0, 0x00, 0x3F,\n  0x00, 0x03, 0xC0, 0x00, 0x10, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xC0, 0xC0, 0x00, 0x3C, 0x00, 0x07, 0xE0, 0x00, 0x7E, 0x00, 0x07,\n  0xE0, 0x00, 0x3E, 0x00, 0x03, 0xE0, 0x00, 0x3F, 0x00, 0x03, 0xC0, 0x01,\n  0xF0, 0x01, 0xF8, 0x01, 0xF8, 0x01, 0xF0, 0x01, 0xF0, 0x03, 0xF0, 0x03,\n  0xF0, 0x00, 0xF0, 0x00, 0x20, 0x00, 0x00, 0x0F, 0x81, 0x86, 0x30, 0x33,\n  0x03, 0x30, 0x30, 0x03, 0x00, 0x60, 0x0E, 0x01, 0xC0, 0x38, 0x06, 0x00,\n  0xC0, 0x08, 0x01, 0x00, 0x10, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06,\n  0x00, 0xF0, 0x0F, 0x00, 0x60, 0x00, 0x00, 0x7F, 0x00, 0x03, 0xFF, 0xE0,\n  0x07, 0x80, 0xF0, 0x0E, 0x00, 0x38, 0x1C, 0x00, 0x0C, 0x38, 0x0E, 0x06,\n  0x70, 0x3F, 0xE2, 0x70, 0x71, 0xE3, 0xF0, 0x60, 0xE1, 0xE0, 0xC0, 0xC1,\n  0xE0, 0xC0, 0xC1, 0xE1, 0x81, 0xC1, 0xE1, 0x81, 0xC1, 0xE1, 0x81, 0x82,\n  0xE1, 0x83, 0x82, 0x71, 0x83, 0x86, 0x71, 0xC7, 0x8C, 0x38, 0xF9, 0xF8,\n  0x3C, 0xF0, 0xF0, 0x1E, 0x00, 0x00, 0x0F, 0x80, 0x30, 0x03, 0xFF, 0xE0,\n  0x00, 0x7F, 0x00, 0x00, 0x03, 0x00, 0x00, 0x18, 0x00, 0x01, 0xC0, 0x00,\n  0x1E, 0x00, 0x00, 0xF0, 0x00, 0x0F, 0x80, 0x00, 0x5E, 0x00, 0x04, 0xF0,\n  0x00, 0x63, 0x80, 0x02, 0x1C, 0x00, 0x20, 0xE0, 0x01, 0x07, 0x00, 0x10,\n  0x3C, 0x01, 0xFF, 0xE0, 0x0F, 0xFF, 0x00, 0xC0, 0x38, 0x04, 0x01, 0xC0,\n  0x60, 0x0E, 0x06, 0x00, 0x78, 0x30, 0x03, 0xC3, 0x00, 0x1E, 0x38, 0x00,\n  0xFB, 0xF0, 0x1F, 0xE0, 0x07, 0xFF, 0x80, 0x0F, 0xFF, 0x00, 0x78, 0x3C,\n  0x03, 0xC0, 0xF0, 0x1E, 0x07, 0x80, 0xE0, 0x3C, 0x07, 0x01, 0xE0, 0x78,\n  0x1E, 0x03, 0x83, 0xE0, 0x1F, 0xF8, 0x01, 0xFF, 0xC0, 0x0F, 0x0F, 0x00,\n  0x70, 0x3C, 0x03, 0x80, 0xF0, 0x3C, 0x07, 0x81, 0xC0, 0x3C, 0x0E, 0x01,\n  0xE0, 0xF0, 0x0F, 0x07, 0x80, 0xF0, 0x38, 0x0F, 0x81, 0xC1, 0xF8, 0x1F,\n  0xFF, 0x83, 0xFF, 0xE0, 0x00, 0x00, 0x3F, 0x08, 0x07, 0xFF, 0xC0, 0xF8,\n  0x3E, 0x0F, 0x00, 0x70, 0xF0, 0x03, 0x8F, 0x00, 0x08, 0xF0, 0x00, 0x47,\n  0x80, 0x00, 0x78, 0x00, 0x03, 0xC0, 0x00, 0x1E, 0x00, 0x01, 0xE0, 0x00,\n  0x0F, 0x00, 0x00, 0x78, 0x00, 0x03, 0xC0, 0x00, 0x1E, 0x00, 0x00, 0xF0,\n  0x00, 0x03, 0x80, 0x02, 0x1E, 0x00, 0x20, 0x78, 0x02, 0x03, 0xE0, 0x60,\n  0x07, 0xFE, 0x00, 0x0F, 0xC0, 0x00, 0x07, 0xFF, 0xC0, 0x00, 0xFF, 0xFC,\n  0x00, 0x78, 0x1F, 0x00, 0x3C, 0x03, 0xC0, 0x1E, 0x00, 0xF0, 0x0E, 0x00,\n  0x78, 0x07, 0x00, 0x1E, 0x07, 0x80, 0x0F, 0x03, 0x80, 0x07, 0x81, 0xC0,\n  0x03, 0xC1, 0xE0, 0x01, 0xE0, 0xF0, 0x00, 0xF0, 0x70, 0x00, 0x78, 0x38,\n  0x00, 0x78, 0x3C, 0x00, 0x3C, 0x1E, 0x00, 0x3E, 0x0E, 0x00, 0x1E, 0x0F,\n  0x00, 0x1E, 0x07, 0x80, 0x1E, 0x03, 0x80, 0x3E, 0x01, 0xC0, 0x7E, 0x01,\n  0xFF, 0xFC, 0x03, 0xFF, 0xF0, 0x00, 0x07, 0xFF, 0xFC, 0x07, 0xFF, 0xF0,\n  0x1E, 0x01, 0xC0, 0x78, 0x02, 0x01, 0xE0, 0x08, 0x07, 0x00, 0x00, 0x1C,\n  0x08, 0x00, 0xF0, 0x60, 0x03, 0x83, 0x80, 0x0F, 0xFC, 0x00, 0x7F, 0xF0,\n  0x01, 0xE0, 0xC0, 0x07, 0x03, 0x00, 0x1C, 0x08, 0x00, 0xF0, 0x20, 0x03,\n  0x80, 0x00, 0x0E, 0x00, 0x00, 0x78, 0x00, 0x81, 0xE0, 0x06, 0x07, 0x00,\n  0x38, 0x1C, 0x03, 0xC0, 0xFF, 0xFF, 0x0F, 0xFF, 0xFC, 0x00, 0x07, 0xFF,\n  0xFC, 0x07, 0xFF, 0xF0, 0x1E, 0x01, 0xC0, 0x78, 0x02, 0x01, 0xE0, 0x08,\n  0x07, 0x00, 0x20, 0x1C, 0x00, 0x00, 0xF0, 0x20, 0x03, 0x81, 0x80, 0x0E,\n  0x0C, 0x00, 0x7F, 0xF0, 0x01, 0xFF, 0xC0, 0x07, 0x03, 0x00, 0x1C, 0x0C,\n  0x00, 0xF0, 0x20, 0x03, 0xC0, 0x00, 0x0E, 0x00, 0x00, 0x78, 0x00, 0x01,\n  0xE0, 0x00, 0x07, 0x00, 0x00, 0x1C, 0x00, 0x00, 0xF8, 0x00, 0x0F, 0xF8,\n  0x00, 0x00, 0x00, 0x3F, 0x02, 0x01, 0xFF, 0x88, 0x0F, 0x81, 0xF0, 0x3C,\n  0x01, 0xE0, 0xF0, 0x01, 0xC3, 0xC0, 0x01, 0x0F, 0x80, 0x02, 0x1E, 0x00,\n  0x00, 0x7C, 0x00, 0x00, 0xF0, 0x00, 0x01, 0xE0, 0x00, 0x07, 0xC0, 0x00,\n  0x0F, 0x00, 0x3F, 0xFE, 0x00, 0x1E, 0x3C, 0x00, 0x38, 0x78, 0x00, 0x70,\n  0xF0, 0x00, 0xE0, 0xE0, 0x01, 0xC1, 0xE0, 0x07, 0x01, 0xE0, 0x0E, 0x01,\n  0xF0, 0x3C, 0x01, 0xFF, 0xF0, 0x00, 0xFF, 0x00, 0x00, 0x07, 0xFC, 0x3F,\n  0xE0, 0x3E, 0x00, 0xF0, 0x07, 0x80, 0x1C, 0x00, 0xF0, 0x03, 0x80, 0x1C,\n  0x00, 0xF0, 0x03, 0x80, 0x1E, 0x00, 0x70, 0x03, 0x80, 0x1E, 0x00, 0x70,\n  0x03, 0x80, 0x1E, 0x00, 0x70, 0x03, 0x80, 0x1F, 0xFF, 0xF0, 0x03, 0xFF,\n  0xFE, 0x00, 0x70, 0x03, 0xC0, 0x0E, 0x00, 0x70, 0x03, 0xC0, 0x0E, 0x00,\n  0x70, 0x03, 0xC0, 0x0E, 0x00, 0x78, 0x03, 0xC0, 0x0E, 0x00, 0x78, 0x01,\n  0xC0, 0x0E, 0x00, 0x78, 0x01, 0xC0, 0x0E, 0x00, 0x78, 0x03, 0xE0, 0x3F,\n  0xE1, 0xFF, 0x00, 0x07, 0xFC, 0x07, 0xC0, 0x1E, 0x00, 0x78, 0x01, 0xC0,\n  0x07, 0x00, 0x1C, 0x00, 0xF0, 0x03, 0x80, 0x0E, 0x00, 0x78, 0x01, 0xE0,\n  0x07, 0x00, 0x1C, 0x00, 0xF0, 0x03, 0x80, 0x0E, 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 0x80, 0x00, 0x3C, 0x00, 0xC1, 0xE0, 0x02, 0x0F, 0x00, 0x18, 0x38, 0x01,\n  0xE1, 0xFF, 0xFF, 0x0F, 0xFF, 0xFC, 0x00, 0x01, 0xF8, 0x0C, 0x00, 0xC0,\n  0x06, 0x00, 0x30, 0x01, 0x80, 0x18, 0x00, 0xC0, 0x06, 0x00, 0x30, 0x03,\n  0x00, 0x18, 0x00, 0xC0, 0x06, 0x00, 0x60, 0x03, 0x00, 0x18, 0x01, 0xC0,\n  0x0C, 0x00, 0x60, 0x03, 0x00, 0x30, 0x01, 0x80, 0x0C, 0x00, 0x60, 0x06,\n  0x00, 0x30, 0x01, 0xF8, 0x00, 0xE0, 0x0E, 0x00, 0x60, 0x07, 0x00, 0x30,\n  0x03, 0x80, 0x18, 0x01, 0xC0, 0x0C, 0x00, 0xC0, 0x0E, 0x00, 0x60, 0x07,\n  0x00, 0x30, 0x03, 0x80, 0x18, 0x01, 0xC0, 0x0C, 0x00, 0xC0, 0x0E, 0x00,\n  0x60, 0x07, 0x00, 0x30, 0x03, 0xF0, 0x06, 0x00, 0x60, 0x06, 0x00, 0x60,\n  0x0E, 0x00, 0xC0, 0x0C, 0x00, 0xC0, 0x0C, 0x01, 0x80, 0x18, 0x01, 0x80,\n  0x18, 0x03, 0x00, 0x30, 0x03, 0x00, 0x30, 0x03, 0x00, 0x60, 0x06, 0x00,\n  0x60, 0x06, 0x00, 0xC0, 0x0C, 0x00, 0xC0, 0x0C, 0x0F, 0xC0, 0x03, 0x80,\n  0x07, 0x00, 0x1F, 0x00, 0x36, 0x00, 0xCE, 0x01, 0x8C, 0x06, 0x1C, 0x0C,\n  0x18, 0x38, 0x38, 0x60, 0x31, 0xC0, 0x73, 0x00, 0x6E, 0x00, 0xE0, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xF0, 0xE3, 0x8F, 0x0E, 0x18, 0x30, 0x01, 0xEC, 0x0E,\n  0x58, 0x30, 0x70, 0xE0, 0xC3, 0x81, 0x86, 0x07, 0x1C, 0x0C, 0x38, 0x18,\n  0xE0, 0x71, 0xC0, 0xE3, 0x83, 0x87, 0x0B, 0x2F, 0x36, 0xCF, 0xCF, 0x1F,\n  0x1C, 0x00, 0x03, 0x00, 0x1F, 0x00, 0x07, 0x00, 0x07, 0x00, 0x06, 0x00,\n  0x0E, 0x00, 0x0E, 0x00, 0x0E, 0x00, 0x0C, 0x00, 0x1C, 0x7C, 0x1C, 0xFE,\n  0x19, 0x8F, 0x1A, 0x07, 0x3C, 0x07, 0x38, 0x07, 0x38, 0x07, 0x70, 0x0E,\n  0x70, 0x0E, 0x70, 0x1C, 0x60, 0x18, 0xE0, 0x30, 0xE0, 0x60, 0xE1, 0xC0,\n  0x3F, 0x00, 0x01, 0xF0, 0x38, 0xC3, 0x8E, 0x78, 0x73, 0x80, 0x3C, 0x01,\n  0xC0, 0x1E, 0x00, 0xF0, 0x07, 0x80, 0x3C, 0x01, 0xE0, 0x47, 0x84, 0x3F,\n  0xC0, 0x7C, 0x00, 0x00, 0x01, 0x80, 0x07, 0xC0, 0x00, 0xE0, 0x00, 0x60,\n  0x00, 0x30, 0x00, 0x38, 0x00, 0x1C, 0x00, 0x0C, 0x00, 0x06, 0x00, 0xF7,\n  0x01, 0xC7, 0x81, 0xC3, 0x81, 0xC1, 0xC1, 0xE0, 0xE0, 0xE0, 0x60, 0xF0,\n  0x30, 0x78, 0x38, 0x78, 0x18, 0x3C, 0x0C, 0x1E, 0x0C, 0x0F, 0x0E, 0x27,\n  0xCB, 0x21, 0xF9, 0xE0, 0x78, 0xE0, 0x00, 0xF0, 0x1C, 0xC3, 0x86, 0x38,\n  0x33, 0xC3, 0x1C, 0x31, 0xE3, 0x1F, 0xE0, 0xF0, 0x07, 0x80, 0x3C, 0x01,\n  0xE0, 0x47, 0x84, 0x3F, 0xC0, 0x7C, 0x00, 0x00, 0x01, 0xE0, 0x00, 0x33,\n  0x00, 0x06, 0x30, 0x00, 0xC0, 0x00, 0x0C, 0x00, 0x01, 0xC0, 0x00, 0x18,\n  0x00, 0x01, 0x80, 0x00, 0x38, 0x00, 0x3F, 0xF8, 0x03, 0xFF, 0x80, 0x03,\n  0x00, 0x00, 0x70, 0x00, 0x07, 0x00, 0x00, 0x70, 0x00, 0x06, 0x00, 0x00,\n  0x60, 0x00, 0x0E, 0x00, 0x00, 0xE0, 0x00, 0x0C, 0x00, 0x00, 0xC0, 0x00,\n  0x1C, 0x00, 0x01, 0xC0, 0x00, 0x18, 0x00, 0x01, 0x80, 0x00, 0x18, 0x00,\n  0x03, 0x00, 0x00, 0x30, 0x00, 0xC6, 0x00, 0x0C, 0xC0, 0x00, 0x78, 0x00,\n  0x00, 0x01, 0xF8, 0x07, 0x1F, 0x0E, 0x0F, 0x0C, 0x0E, 0x18, 0x0E, 0x18,\n  0x0E, 0x18, 0x1E, 0x18, 0x3C, 0x0C, 0x78, 0x07, 0xE0, 0x08, 0x00, 0x18,\n  0x00, 0x1E, 0x00, 0x0F, 0xE0, 0x13, 0xF0, 0x60, 0x78, 0xC0, 0x38, 0xC0,\n  0x18, 0xC0, 0x18, 0xC0, 0x30, 0x60, 0x60, 0x3F, 0x80, 0x03, 0x00, 0x1F,\n  0x00, 0x07, 0x00, 0x07, 0x00, 0x06, 0x00, 0x06, 0x00, 0x0E, 0x00, 0x0E,\n  0x00, 0x0C, 0x00, 0x1C, 0x38, 0x1C, 0x7C, 0x1C, 0xCC, 0x19, 0x0C, 0x3A,\n  0x0C, 0x3C, 0x1C, 0x3C, 0x18, 0x38, 0x18, 0x70, 0x38, 0x70, 0x38, 0x70,\n  0x30, 0x60, 0x72, 0xE0, 0x76, 0xE0, 0x7C, 0xC0, 0x70, 0x03, 0x03, 0xC1,\n  0xE0, 0x60, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x7E, 0x0F, 0x03, 0x81, 0x81,\n  0xC0, 0xE0, 0x70, 0x30, 0x38, 0x1C, 0x1C, 0x4C, 0x47, 0xC3, 0xC0, 0x00,\n  0x0C, 0x00, 0x3C, 0x00, 0x78, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x18, 0x03, 0xF0, 0x00, 0xE0, 0x01, 0x80, 0x03, 0x00,\n  0x0E, 0x00, 0x1C, 0x00, 0x30, 0x00, 0x60, 0x01, 0xC0, 0x03, 0x80, 0x06,\n  0x00, 0x0C, 0x00, 0x38, 0x00, 0x70, 0x00, 0xC0, 0x03, 0x80, 0x06, 0x00,\n  0x0C, 0x06, 0x30, 0x0C, 0xC0, 0x0F, 0x00, 0x00, 0x03, 0x00, 0x3E, 0x00,\n  0x1C, 0x00, 0x38, 0x00, 0x60, 0x01, 0xC0, 0x03, 0x80, 0x07, 0x00, 0x0C,\n  0x00, 0x38, 0xFC, 0x70, 0x60, 0xE1, 0x81, 0x86, 0x07, 0x10, 0x0E, 0x40,\n  0x1B, 0x80, 0x3F, 0x00, 0xE7, 0x01, 0xCE, 0x03, 0x0C, 0x06, 0x1C, 0x5C,\n  0x1D, 0x38, 0x3E, 0x60, 0x38, 0x03, 0x1F, 0x07, 0x07, 0x06, 0x0E, 0x0E,\n  0x0E, 0x0C, 0x1C, 0x1C, 0x18, 0x38, 0x38, 0x38, 0x30, 0x70, 0x70, 0x70,\n  0x64, 0xE4, 0xE8, 0xF0, 0xE0, 0x00, 0x06, 0x18, 0x1E, 0x3E, 0x3C, 0x3F,\n  0x0E, 0x4C, 0x47, 0x0C, 0x8C, 0x8E, 0x1D, 0x0D, 0x0E, 0x1E, 0x1A, 0x0E,\n  0x1C, 0x1E, 0x0C, 0x3C, 0x1C, 0x1C, 0x38, 0x38, 0x1C, 0x38, 0x38, 0x1C,\n  0x30, 0x38, 0x18, 0x70, 0x30, 0x39, 0x70, 0x70, 0x32, 0x60, 0x70, 0x3C,\n  0x60, 0x60, 0x38, 0x06, 0x0E, 0x1F, 0x1F, 0x83, 0x99, 0xC1, 0x98, 0xC1,\n  0xD8, 0xE0, 0xE8, 0x70, 0x78, 0x30, 0x38, 0x38, 0x3C, 0x1C, 0x1C, 0x0E,\n  0x0E, 0x06, 0x0E, 0x03, 0x17, 0x01, 0xB3, 0x80, 0xF1, 0x80, 0x70, 0x01,\n  0xF0, 0x0E, 0x38, 0x38, 0x30, 0xE0, 0x73, 0x80, 0xEE, 0x01, 0xDC, 0x03,\n  0xF8, 0x0F, 0xE0, 0x1D, 0xC0, 0x3B, 0x80, 0xE7, 0x03, 0x8E, 0x06, 0x0E,\n  0x38, 0x07, 0xC0, 0x00, 0x00, 0xE7, 0xC0, 0x7C, 0xFE, 0x01, 0xD1, 0xF0,\n  0x1E, 0x0F, 0x01, 0xC0, 0xF0, 0x38, 0x0F, 0x03, 0x80, 0xF0, 0x38, 0x0E,\n  0x03, 0x01, 0xE0, 0x70, 0x1C, 0x07, 0x03, 0xC0, 0x60, 0x78, 0x06, 0x0F,\n  0x00, 0xE1, 0xC0, 0x0F, 0xF0, 0x00, 0xC0, 0x00, 0x1C, 0x00, 0x01, 0xC0,\n  0x00, 0x1C, 0x00, 0x01, 0x80, 0x00, 0x38, 0x00, 0x0F, 0xF0, 0x00, 0x00,\n  0xF7, 0x03, 0xCE, 0x0F, 0x06, 0x1E, 0x06, 0x1C, 0x04, 0x3C, 0x04, 0x78,\n  0x04, 0x78, 0x0C, 0xF0, 0x08, 0xF0, 0x18, 0xF0, 0x38, 0xF0, 0xF0, 0xF9,\n  0x70, 0x7E, 0x70, 0x3C, 0x70, 0x00, 0x60, 0x00, 0xE0, 0x00, 0xE0, 0x00,\n  0xC0, 0x01, 0xC0, 0x01, 0xC0, 0x0F, 0xF0, 0x7C, 0x70, 0xE7, 0xC7, 0x4C,\n  0x34, 0x01, 0xA0, 0x1E, 0x00, 0xF0, 0x07, 0x00, 0x78, 0x03, 0x80, 0x1C,\n  0x00, 0xC0, 0x0E, 0x00, 0x70, 0x03, 0x80, 0x00, 0x07, 0x88, 0x63, 0x86,\n  0x0C, 0x30, 0x21, 0xC1, 0x0E, 0x00, 0x38, 0x00, 0xE0, 0x03, 0x80, 0x1C,\n  0x10, 0x60, 0x83, 0x06, 0x18, 0x71, 0x82, 0x78, 0x00, 0x02, 0x03, 0x03,\n  0x07, 0xF7, 0xF8, 0xE0, 0x60, 0x70, 0x38, 0x1C, 0x0C, 0x0E, 0x07, 0x03,\n  0x01, 0x91, 0xC8, 0xF8, 0x78, 0x00, 0x1C, 0x0D, 0xF8, 0x38, 0x60, 0x70,\n  0xC1, 0xC3, 0x83, 0x87, 0x07, 0x0C, 0x1E, 0x38, 0x78, 0x70, 0xB0, 0xE2,\n  0x61, 0x8D, 0xC7, 0x33, 0x2C, 0xC6, 0x5F, 0x0F, 0x38, 0x1C, 0x00, 0x18,\n  0x1B, 0xE0, 0x73, 0x81, 0xC6, 0x03, 0x18, 0x0C, 0x70, 0x21, 0xC1, 0x83,\n  0x0C, 0x0C, 0x20, 0x31, 0x00, 0xC8, 0x03, 0x40, 0x0E, 0x00, 0x30, 0x00,\n  0x80, 0x00, 0x18, 0x04, 0x1B, 0xE0, 0x30, 0x71, 0x80, 0xC1, 0xC6, 0x07,\n  0x01, 0x1C, 0x2C, 0x08, 0x70, 0xB0, 0x20, 0xC4, 0xC1, 0x03, 0x21, 0x84,\n  0x0D, 0x86, 0x20, 0x34, 0x19, 0x00, 0xE0, 0x68, 0x03, 0x81, 0xA0, 0x0C,\n  0x07, 0x00, 0x30, 0x18, 0x00, 0x80, 0x40, 0x00, 0x03, 0x07, 0x0F, 0x8F,\n  0x13, 0x93, 0x01, 0xB0, 0x01, 0xE0, 0x01, 0xC0, 0x00, 0xC0, 0x00, 0xC0,\n  0x01, 0xC0, 0x03, 0xE0, 0x02, 0x60, 0x04, 0x62, 0x08, 0x64, 0xF0, 0x7C,\n  0xE0, 0x30, 0x06, 0x06, 0x3F, 0x07, 0x07, 0x07, 0x07, 0x03, 0x03, 0x81,\n  0x03, 0x82, 0x01, 0x82, 0x01, 0xC4, 0x01, 0xC4, 0x01, 0xC8, 0x00, 0xC8,\n  0x00, 0xD0, 0x00, 0xF0, 0x00, 0xE0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0x80,\n  0x01, 0x00, 0x02, 0x00, 0x04, 0x00, 0x78, 0x00, 0x70, 0x00, 0x1F, 0xFC,\n  0x7F, 0xE1, 0x01, 0x08, 0x08, 0x00, 0x40, 0x02, 0x00, 0x10, 0x00, 0x80,\n  0x06, 0x00, 0x10, 0x00, 0x80, 0x04, 0x00, 0x38, 0x01, 0xF0, 0x0B, 0xE0,\n  0x01, 0xC6, 0x03, 0x98, 0x03, 0x80, 0x00, 0x70, 0x0C, 0x01, 0x80, 0x38,\n  0x03, 0x80, 0x30, 0x07, 0x00, 0x70, 0x07, 0x00, 0x60, 0x0E, 0x00, 0xE0,\n  0x0C, 0x01, 0xC0, 0x1C, 0x07, 0x80, 0x30, 0x04, 0x00, 0x20, 0x03, 0x00,\n  0x30, 0x07, 0x00, 0x70, 0x06, 0x00, 0x60, 0x0E, 0x00, 0xE0, 0x0C, 0x00,\n  0xC0, 0x07, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0x00, 0xC0, 0x06,\n  0x00, 0x30, 0x03, 0x00, 0x30, 0x03, 0x00, 0x70, 0x07, 0x00, 0x70, 0x06,\n  0x00, 0xE0, 0x0E, 0x00, 0xE0, 0x0C, 0x00, 0x40, 0x04, 0x00, 0xC0, 0x1E,\n  0x03, 0x80, 0x38, 0x03, 0x00, 0x70, 0x07, 0x00, 0x70, 0x06, 0x00, 0xE0,\n  0x0E, 0x00, 0xC0, 0x1C, 0x01, 0x80, 0x70, 0x00, 0x1E, 0x00, 0x3F, 0xE1,\n  0xF8, 0x7F, 0xC0, 0x07, 0x80 };\n\nconst GFXglyph FreeSerifItalic18pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,   9,    0,    1 },   // 0x20 ' '\n  {     0,  10,  23,  12,    1,  -22 },   // 0x21 '!'\n  {    29,  12,   9,  12,    4,  -22 },   // 0x22 '\"'\n  {    43,  19,  23,  17,    0,  -22 },   // 0x23 '#'\n  {    98,  15,  29,  17,    1,  -25 },   // 0x24 '$'\n  {   153,  25,  23,  29,    3,  -22 },   // 0x25 '%'\n  {   225,  22,  23,  27,    3,  -22 },   // 0x26 '&'\n  {   289,   5,   9,   7,    4,  -22 },   // 0x27 '''\n  {   295,   9,  29,  12,    1,  -22 },   // 0x28 '('\n  {   328,   9,  29,  12,    1,  -22 },   // 0x29 ')'\n  {   361,  12,  14,  18,    5,  -22 },   // 0x2A '*'\n  {   382,  16,  18,  24,    4,  -17 },   // 0x2B '+'\n  {   418,   5,   8,   9,   -1,   -2 },   // 0x2C ','\n  {   423,   8,   2,  12,    2,   -8 },   // 0x2D '-'\n  {   425,   4,   4,   9,    1,   -3 },   // 0x2E '.'\n  {   427,  16,  23,  10,    0,  -22 },   // 0x2F '/'\n  {   473,  17,  24,  17,    1,  -23 },   // 0x30 '0'\n  {   524,  12,  24,  17,    2,  -23 },   // 0x31 '1'\n  {   560,  16,  23,  17,    1,  -22 },   // 0x32 '2'\n  {   606,  17,  24,  18,    0,  -23 },   // 0x33 '3'\n  {   657,  17,  24,  17,    0,  -23 },   // 0x34 '4'\n  {   708,  16,  23,  18,    0,  -22 },   // 0x35 '5'\n  {   754,  17,  24,  18,    1,  -23 },   // 0x36 '6'\n  {   805,  16,  23,  17,    3,  -22 },   // 0x37 '7'\n  {   851,  16,  24,  18,    1,  -23 },   // 0x38 '8'\n  {   899,  16,  24,  17,    1,  -23 },   // 0x39 '9'\n  {   947,   7,  15,   9,    2,  -14 },   // 0x3A ':'\n  {   961,   9,  20,   9,    1,  -14 },   // 0x3B ';'\n  {   984,  18,  18,  20,    2,  -17 },   // 0x3C '<'\n  {  1025,  18,   9,  23,    3,  -12 },   // 0x3D '='\n  {  1046,  18,  18,  20,    2,  -17 },   // 0x3E '>'\n  {  1087,  12,  23,  16,    4,  -22 },   // 0x3F '?'\n  {  1122,  24,  23,  27,    2,  -22 },   // 0x40 '@'\n  {  1191,  21,  23,  23,    0,  -22 },   // 0x41 'A'\n  {  1252,  21,  23,  21,    0,  -22 },   // 0x42 'B'\n  {  1313,  21,  23,  21,    2,  -22 },   // 0x43 'C'\n  {  1374,  25,  23,  25,    0,  -22 },   // 0x44 'D'\n  {  1446,  22,  23,  20,    0,  -22 },   // 0x45 'E'\n  {  1510,  22,  23,  20,    0,  -22 },   // 0x46 'F'\n  {  1574,  23,  23,  24,    2,  -22 },   // 0x47 'G'\n  {  1641,  27,  23,  25,    0,  -22 },   // 0x48 'H'\n  {  1719,  14,  23,  11,    0,  -22 },   // 0x49 'I'\n  {  1760,  17,  23,  15,    0,  -22 },   // 0x4A 'J'\n  {  1809,  25,  23,  22,    0,  -22 },   // 0x4B 'K'\n  {  1881,  20,  23,  20,    0,  -22 },   // 0x4C 'L'\n  {  1939,  31,  23,  29,    0,  -22 },   // 0x4D 'M'\n  {  2029,  26,  23,  24,    0,  -22 },   // 0x4E 'N'\n  {  2104,  23,  23,  23,    1,  -22 },   // 0x4F 'O'\n  {  2171,  22,  23,  20,    0,  -22 },   // 0x50 'P'\n  {  2235,  23,  29,  23,    1,  -22 },   // 0x51 'Q'\n  {  2319,  21,  23,  22,    0,  -22 },   // 0x52 'R'\n  {  2380,  17,  23,  16,    0,  -22 },   // 0x53 'S'\n  {  2429,  20,  23,  21,    3,  -22 },   // 0x54 'T'\n  {  2487,  23,  23,  25,    4,  -22 },   // 0x55 'U'\n  {  2554,  21,  23,  23,    5,  -22 },   // 0x56 'V'\n  {  2615,  29,  23,  31,    5,  -22 },   // 0x57 'W'\n  {  2699,  24,  23,  23,    0,  -22 },   // 0x58 'X'\n  {  2768,  19,  23,  21,    4,  -22 },   // 0x59 'Y'\n  {  2823,  22,  23,  20,    0,  -22 },   // 0x5A 'Z'\n  {  2887,  13,  28,  14,    1,  -22 },   // 0x5B '['\n  {  2933,  12,  23,  17,    4,  -22 },   // 0x5C '\\'\n  {  2968,  12,  28,  14,    1,  -22 },   // 0x5D ']'\n  {  3010,  15,  13,  15,    0,  -22 },   // 0x5E '^'\n  {  3035,  18,   2,  17,    0,    3 },   // 0x5F '_'\n  {  3040,   6,   6,   9,    5,  -22 },   // 0x60 '`'\n  {  3045,  15,  15,  17,    1,  -14 },   // 0x61 'a'\n  {  3074,  16,  24,  17,    1,  -23 },   // 0x62 'b'\n  {  3122,  13,  15,  14,    1,  -14 },   // 0x63 'c'\n  {  3147,  17,  24,  18,    1,  -23 },   // 0x64 'd'\n  {  3198,  13,  15,  14,    1,  -14 },   // 0x65 'e'\n  {  3223,  20,  31,  15,   -3,  -23 },   // 0x66 'f'\n  {  3301,  16,  22,  15,   -1,  -14 },   // 0x67 'g'\n  {  3345,  16,  24,  17,    1,  -23 },   // 0x68 'h'\n  {  3393,   9,  23,   9,    1,  -22 },   // 0x69 'i'\n  {  3419,  15,  30,  10,   -3,  -22 },   // 0x6A 'j'\n  {  3476,  15,  24,  16,    1,  -23 },   // 0x6B 'k'\n  {  3521,   8,  25,   9,    1,  -23 },   // 0x6C 'l'\n  {  3546,  24,  15,  25,    0,  -14 },   // 0x6D 'm'\n  {  3591,  17,  15,  17,    0,  -14 },   // 0x6E 'n'\n  {  3623,  15,  15,  17,    1,  -14 },   // 0x6F 'o'\n  {  3652,  20,  22,  16,   -3,  -14 },   // 0x70 'p'\n  {  3707,  16,  22,  17,    1,  -14 },   // 0x71 'q'\n  {  3751,  13,  15,  13,    1,  -14 },   // 0x72 'r'\n  {  3776,  13,  15,  12,    0,  -14 },   // 0x73 's'\n  {  3801,   9,  18,   8,    1,  -17 },   // 0x74 't'\n  {  3822,  15,  15,  17,    1,  -14 },   // 0x75 'u'\n  {  3851,  14,  15,  16,    2,  -14 },   // 0x76 'v'\n  {  3878,  22,  15,  24,    1,  -14 },   // 0x77 'w'\n  {  3920,  16,  15,  15,   -1,  -14 },   // 0x78 'x'\n  {  3950,  16,  22,  16,    0,  -14 },   // 0x79 'y'\n  {  3994,  14,  18,  14,    0,  -14 },   // 0x7A 'z'\n  {  4026,  12,  30,  14,    2,  -23 },   // 0x7B '{'\n  {  4071,   2,  23,  10,    4,  -22 },   // 0x7C '|'\n  {  4077,  12,  31,  14,    0,  -24 },   // 0x7D '}'\n  {  4124,  17,   4,  19,    1,  -10 } }; // 0x7E '~'\n\nconst GFXfont FreeSerifItalic18pt7b PROGMEM = {\n  (uint8_t  *)FreeSerifItalic18pt7bBitmaps,\n  (GFXglyph *)FreeSerifItalic18pt7bGlyphs,\n  0x20, 0x7E, 42 };\n\n// Approx. 4805 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeSerifItalic24pt7b.h",
    "content": "const uint8_t FreeSerifItalic24pt7bBitmaps[] PROGMEM = {\n  0x00, 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0x01, 0xF0, 0x1E, 0x01, 0xE0, 0x1C,\n  0x01, 0xC0, 0x3C, 0x03, 0x80, 0x38, 0x03, 0x80, 0x30, 0x07, 0x00, 0x60,\n  0x06, 0x00, 0x60, 0x04, 0x00, 0x40, 0x0C, 0x00, 0x80, 0x08, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0xF8, 0x0F, 0x80, 0xF8, 0x07, 0x00,\n  0x38, 0x1D, 0xE0, 0x77, 0x83, 0xDC, 0x0E, 0x70, 0x39, 0xC1, 0xEE, 0x07,\n  0x38, 0x1C, 0xC0, 0x63, 0x01, 0x8C, 0x06, 0x20, 0x10, 0x00, 0x06, 0x03,\n  0x00, 0x07, 0x03, 0x80, 0x03, 0x81, 0xC0, 0x03, 0x81, 0xC0, 0x01, 0xC0,\n  0xE0, 0x00, 0xE0, 0x70, 0x00, 0xE0, 0x70, 0x00, 0x70, 0x38, 0x00, 0x30,\n  0x18, 0x00, 0x38, 0x1C, 0x03, 0xFF, 0xFF, 0xE1, 0xFF, 0xFF, 0xF0, 0x0E,\n  0x07, 0x00, 0x06, 0x03, 0x00, 0x07, 0x03, 0x80, 0x03, 0x81, 0xC0, 0x03,\n  0x81, 0xC0, 0x01, 0xC0, 0xE0, 0x00, 0xE0, 0x70, 0x1F, 0xFF, 0xFF, 0x8F,\n  0xFF, 0xFF, 0x80, 0x70, 0x38, 0x00, 0x38, 0x1C, 0x00, 0x1C, 0x0C, 0x00,\n  0x1C, 0x0E, 0x00, 0x0E, 0x07, 0x00, 0x0E, 0x07, 0x00, 0x07, 0x03, 0x80,\n  0x03, 0x81, 0xC0, 0x03, 0x81, 0xC0, 0x01, 0xC0, 0xE0, 0x00, 0x00, 0x01,\n  0x00, 0x00, 0x18, 0x00, 0x00, 0xC0, 0x00, 0xFF, 0x80, 0x1C, 0x2F, 0x01,\n  0x83, 0x3C, 0x1C, 0x18, 0xE1, 0xC0, 0xC3, 0x0E, 0x06, 0x18, 0x70, 0x60,\n  0x83, 0x83, 0x04, 0x1E, 0x18, 0x00, 0xF8, 0xC0, 0x03, 0xEC, 0x00, 0x0F,\n  0xE0, 0x00, 0x3F, 0x00, 0x00, 0xFC, 0x00, 0x03, 0xF0, 0x00, 0x0F, 0xC0,\n  0x00, 0x7F, 0x00, 0x03, 0x7C, 0x00, 0x19, 0xE0, 0x01, 0x87, 0x80, 0x0C,\n  0x3C, 0x00, 0x60, 0xE2, 0x03, 0x07, 0x10, 0x30, 0x39, 0x81, 0x81, 0xCE,\n  0x0C, 0x0C, 0x70, 0x60, 0xE3, 0xC6, 0x06, 0x0F, 0x30, 0x60, 0x1F, 0x9E,\n  0x00, 0x3F, 0x80, 0x00, 0xC0, 0x00, 0x06, 0x00, 0x00, 0x30, 0x00, 0x01,\n  0x80, 0x00, 0x01, 0xF0, 0x00, 0xC0, 0x03, 0xFE, 0x01, 0xE0, 0x03, 0xC7,\n  0x83, 0xE0, 0x03, 0xC0, 0x7F, 0x60, 0x03, 0xC0, 0x20, 0x70, 0x01, 0xC0,\n  0x10, 0x30, 0x01, 0xE0, 0x08, 0x38, 0x00, 0xE0, 0x04, 0x18, 0x00, 0xF0,\n  0x02, 0x1C, 0x00, 0x70, 0x02, 0x0C, 0x00, 0x38, 0x01, 0x0E, 0x00, 0x1C,\n  0x01, 0x8E, 0x00, 0x0E, 0x00, 0x86, 0x00, 0x07, 0x00, 0x87, 0x03, 0xE1,\n  0x80, 0xC3, 0x07, 0xFC, 0xE1, 0xC3, 0x87, 0xC6, 0x3F, 0x81, 0x87, 0x81,\n  0x8F, 0x81, 0xC7, 0x80, 0x40, 0x00, 0xC3, 0xC0, 0x20, 0x00, 0xE3, 0xC0,\n  0x10, 0x00, 0x61, 0xC0, 0x08, 0x00, 0x61, 0xE0, 0x04, 0x00, 0x70, 0xF0,\n  0x06, 0x00, 0x30, 0x70, 0x02, 0x00, 0x38, 0x38, 0x03, 0x00, 0x18, 0x1C,\n  0x01, 0x00, 0x1C, 0x0E, 0x01, 0x80, 0x0C, 0x07, 0x01, 0x80, 0x0E, 0x01,\n  0xC3, 0x80, 0x06, 0x00, 0x7F, 0x80, 0x06, 0x00, 0x1F, 0x00, 0x07, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x0F, 0xF0, 0x00, 0x00, 0x71,\n  0xC0, 0x00, 0x01, 0xC3, 0x80, 0x00, 0x0E, 0x0E, 0x00, 0x00, 0x38, 0x38,\n  0x00, 0x01, 0xE0, 0xE0, 0x00, 0x07, 0x87, 0x00, 0x00, 0x1E, 0x18, 0x00,\n  0x00, 0x78, 0xC0, 0x00, 0x01, 0xE6, 0x00, 0x00, 0x07, 0xF0, 0x00, 0x00,\n  0x1F, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x07, 0xE0, 0x00, 0x00, 0x7F,\n  0xC1, 0xFE, 0x03, 0x9F, 0x03, 0xE0, 0x3C, 0x3C, 0x07, 0x01, 0xE0, 0xF8,\n  0x1C, 0x0F, 0x03, 0xE0, 0xE0, 0x7C, 0x07, 0x83, 0x01, 0xE0, 0x1F, 0x1C,\n  0x07, 0x80, 0x7C, 0x60, 0x3E, 0x00, 0xFB, 0x00, 0xF8, 0x03, 0xFC, 0x03,\n  0xE0, 0x07, 0xE0, 0x0F, 0x80, 0x1F, 0x00, 0x3F, 0x00, 0x3E, 0x00, 0x7C,\n  0x00, 0xFC, 0x01, 0xF8, 0x0F, 0xF0, 0x03, 0xF0, 0xF3, 0xF0, 0x87, 0xFF,\n  0x07, 0xFC, 0x07, 0xF0, 0x07, 0xC0, 0x39, 0xDE, 0xE7, 0x3B, 0x9C, 0xC6,\n  0x31, 0x00, 0x00, 0x10, 0x01, 0x00, 0x18, 0x01, 0x80, 0x18, 0x01, 0x80,\n  0x1C, 0x00, 0xC0, 0x0E, 0x00, 0xE0, 0x07, 0x00, 0x78, 0x03, 0x80, 0x3C,\n  0x01, 0xE0, 0x0E, 0x00, 0x70, 0x07, 0x80, 0x3C, 0x01, 0xE0, 0x0E, 0x00,\n  0x70, 0x03, 0x80, 0x1C, 0x00, 0xE0, 0x07, 0x00, 0x38, 0x01, 0xC0, 0x0E,\n  0x00, 0x30, 0x01, 0x80, 0x0C, 0x00, 0x60, 0x01, 0x80, 0x0C, 0x00, 0x60,\n  0x01, 0x00, 0x0C, 0x00, 0x20, 0x00, 0x00, 0x80, 0x06, 0x00, 0x10, 0x00,\n  0x80, 0x06, 0x00, 0x30, 0x00, 0xC0, 0x06, 0x00, 0x30, 0x01, 0x80, 0x0C,\n  0x00, 0x70, 0x03, 0x80, 0x1C, 0x00, 0xE0, 0x07, 0x00, 0x38, 0x01, 0xC0,\n  0x1E, 0x00, 0xF0, 0x07, 0x80, 0x3C, 0x01, 0xC0, 0x1E, 0x00, 0xF0, 0x07,\n  0x80, 0x38, 0x03, 0xC0, 0x1C, 0x00, 0xE0, 0x0E, 0x00, 0x60, 0x07, 0x00,\n  0x30, 0x03, 0x00, 0x30, 0x03, 0x00, 0x10, 0x01, 0x00, 0x00, 0x01, 0x00,\n  0x03, 0x80, 0x03, 0x80, 0x03, 0x80, 0x03, 0x80, 0xE1, 0x07, 0xE1, 0x0F,\n  0xF1, 0x1F, 0x19, 0x30, 0x07, 0xC0, 0x03, 0x80, 0x0D, 0x60, 0x79, 0x3C,\n  0xF1, 0x1F, 0xE1, 0x0F, 0xE1, 0x07, 0x03, 0x80, 0x03, 0x80, 0x03, 0x80,\n  0x03, 0x00, 0x00, 0x38, 0x00, 0x00, 0x70, 0x00, 0x00, 0xE0, 0x00, 0x01,\n  0xC0, 0x00, 0x03, 0x80, 0x00, 0x07, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x1C,\n  0x00, 0x00, 0x38, 0x00, 0x00, 0x70, 0x03, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xE0, 0x07, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x1C, 0x00,\n  0x00, 0x38, 0x00, 0x00, 0x70, 0x00, 0x00, 0xE0, 0x00, 0x01, 0xC0, 0x00,\n  0x03, 0x80, 0x00, 0x07, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x1C, 0x7C, 0xF9,\n  0xF1, 0xE1, 0xC3, 0x0C, 0x10, 0xC1, 0x00, 0x7F, 0xFF, 0xFF, 0xFF, 0x00,\n  0x77, 0xFF, 0xF7, 0x00, 0x00, 0x00, 0x78, 0x00, 0x03, 0x80, 0x00, 0x3C,\n  0x00, 0x01, 0xC0, 0x00, 0x1E, 0x00, 0x00, 0xE0, 0x00, 0x0E, 0x00, 0x00,\n  0xF0, 0x00, 0x07, 0x00, 0x00, 0x78, 0x00, 0x03, 0x80, 0x00, 0x3C, 0x00,\n  0x01, 0xC0, 0x00, 0x1E, 0x00, 0x00, 0xE0, 0x00, 0x0F, 0x00, 0x00, 0x70,\n  0x00, 0x07, 0x80, 0x00, 0x38, 0x00, 0x03, 0x80, 0x00, 0x3C, 0x00, 0x01,\n  0xC0, 0x00, 0x1E, 0x00, 0x00, 0xE0, 0x00, 0x0F, 0x00, 0x00, 0x70, 0x00,\n  0x07, 0x80, 0x00, 0x38, 0x00, 0x03, 0xC0, 0x00, 0x1C, 0x00, 0x01, 0xE0,\n  0x00, 0x0E, 0x00, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x1F, 0x80, 0x03, 0x86,\n  0x00, 0x30, 0x18, 0x03, 0x00, 0xC0, 0x38, 0x03, 0x03, 0x80, 0x18, 0x38,\n  0x00, 0xC1, 0xC0, 0x07, 0x1C, 0x00, 0x38, 0xE0, 0x01, 0xCF, 0x00, 0x0E,\n  0x70, 0x00, 0x77, 0x80, 0x07, 0xBC, 0x00, 0x3D, 0xE0, 0x01, 0xEE, 0x00,\n  0x0F, 0xF0, 0x00, 0x77, 0x80, 0x07, 0xBC, 0x00, 0x3D, 0xC0, 0x01, 0xCE,\n  0x00, 0x1E, 0x70, 0x00, 0xF3, 0x80, 0x07, 0x1C, 0x00, 0x78, 0xE0, 0x03,\n  0x83, 0x00, 0x38, 0x18, 0x03, 0x80, 0xE0, 0x18, 0x03, 0x01, 0x80, 0x0C,\n  0x38, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1F, 0xC0, 0x3F, 0xE0,\n  0x01, 0xF0, 0x00, 0xF0, 0x00, 0x78, 0x00, 0x3C, 0x00, 0x1C, 0x00, 0x1E,\n  0x00, 0x0F, 0x00, 0x07, 0x80, 0x07, 0x80, 0x03, 0xC0, 0x01, 0xE0, 0x00,\n  0xF0, 0x00, 0xF0, 0x00, 0x78, 0x00, 0x3C, 0x00, 0x3C, 0x00, 0x1E, 0x00,\n  0x0F, 0x00, 0x07, 0x80, 0x07, 0x80, 0x03, 0xC0, 0x01, 0xE0, 0x01, 0xE0,\n  0x00, 0xF0, 0x00, 0x78, 0x00, 0x3C, 0x00, 0x3C, 0x00, 0x3F, 0x01, 0xFF,\n  0xF0, 0x00, 0x3F, 0x00, 0x07, 0xFE, 0x00, 0x7F, 0xF8, 0x07, 0x07, 0xE0,\n  0x60, 0x1F, 0x06, 0x00, 0x7C, 0x20, 0x01, 0xE0, 0x00, 0x0F, 0x00, 0x00,\n  0x78, 0x00, 0x03, 0xC0, 0x00, 0x1C, 0x00, 0x01, 0xE0, 0x00, 0x0E, 0x00,\n  0x00, 0xF0, 0x00, 0x07, 0x00, 0x00, 0x70, 0x00, 0x07, 0x00, 0x00, 0x70,\n  0x00, 0x03, 0x00, 0x00, 0x30, 0x00, 0x03, 0x00, 0x00, 0x30, 0x00, 0x03,\n  0x00, 0x00, 0x30, 0x00, 0x03, 0x00, 0x00, 0x30, 0x01, 0x03, 0x00, 0x08,\n  0x30, 0x00, 0xC3, 0xFF, 0xFC, 0x3F, 0xFF, 0xE3, 0xFF, 0xFE, 0x00, 0x00,\n  0x0F, 0xC0, 0x00, 0xFF, 0xC0, 0x06, 0x0F, 0x80, 0x30, 0x1E, 0x01, 0x80,\n  0x3C, 0x00, 0x00, 0xF0, 0x00, 0x03, 0xC0, 0x00, 0x0F, 0x00, 0x00, 0x78,\n  0x00, 0x01, 0xE0, 0x00, 0x0E, 0x00, 0x00, 0xF0, 0x00, 0x0E, 0x00, 0x01,\n  0xF8, 0x00, 0x3F, 0xF8, 0x00, 0x0F, 0xF0, 0x00, 0x07, 0xC0, 0x00, 0x0F,\n  0x80, 0x00, 0x3E, 0x00, 0x00, 0x78, 0x00, 0x01, 0xE0, 0x00, 0x07, 0x80,\n  0x00, 0x1E, 0x00, 0x00, 0x70, 0x00, 0x01, 0xC0, 0x00, 0x07, 0x00, 0x00,\n  0x38, 0x00, 0x00, 0xC0, 0x70, 0x06, 0x03, 0xF8, 0x70, 0x07, 0xFF, 0x00,\n  0x0F, 0xF0, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x70, 0x00, 0x03, 0xC0,\n  0x00, 0x1F, 0x00, 0x00, 0xF8, 0x00, 0x07, 0xE0, 0x00, 0x37, 0x80, 0x00,\n  0xDC, 0x00, 0x06, 0x70, 0x00, 0x33, 0xC0, 0x01, 0x8F, 0x00, 0x0C, 0x38,\n  0x00, 0x60, 0xE0, 0x03, 0x07, 0x80, 0x18, 0x1E, 0x00, 0xC0, 0x70, 0x06,\n  0x03, 0xC0, 0x30, 0x0F, 0x01, 0x80, 0x38, 0x0C, 0x00, 0xE0, 0x70, 0x07,\n  0x81, 0xFF, 0xFF, 0xEF, 0xFF, 0xFF, 0xBF, 0xFF, 0xFE, 0x00, 0x0F, 0x00,\n  0x00, 0x38, 0x00, 0x00, 0xE0, 0x00, 0x07, 0x80, 0x00, 0x1E, 0x00, 0x00,\n  0x70, 0x00, 0x03, 0xC0, 0x00, 0x0F, 0x00, 0x00, 0x3F, 0xFC, 0x00, 0xFF,\n  0xF0, 0x07, 0xFF, 0x80, 0x10, 0x00, 0x00, 0x40, 0x00, 0x02, 0x00, 0x00,\n  0x08, 0x00, 0x00, 0x70, 0x00, 0x01, 0xF8, 0x00, 0x0F, 0xF0, 0x00, 0x3F,\n  0xF0, 0x00, 0x1F, 0xE0, 0x00, 0x1F, 0x80, 0x00, 0x1F, 0x00, 0x00, 0x3C,\n  0x00, 0x00, 0x78, 0x00, 0x01, 0xE0, 0x00, 0x03, 0x80, 0x00, 0x0E, 0x00,\n  0x00, 0x38, 0x00, 0x00, 0xE0, 0x00, 0x03, 0x80, 0x00, 0x0C, 0x00, 0x00,\n  0x70, 0x00, 0x01, 0xC0, 0x00, 0x06, 0x00, 0x00, 0x30, 0x00, 0x01, 0x80,\n  0x70, 0x0E, 0x03, 0xF0, 0xE0, 0x07, 0xFF, 0x00, 0x0F, 0xE0, 0x00, 0x00,\n  0x00, 0x0E, 0x00, 0x01, 0xF0, 0x00, 0x1F, 0x00, 0x00, 0xF8, 0x00, 0x03,\n  0xE0, 0x00, 0x0F, 0x00, 0x00, 0x7C, 0x00, 0x01, 0xF0, 0x00, 0x03, 0xC0,\n  0x00, 0x0F, 0x80, 0x00, 0x3E, 0x00, 0x00, 0xF9, 0xF8, 0x01, 0xFF, 0xFC,\n  0x07, 0xE0, 0x7C, 0x0F, 0x80, 0x7C, 0x3E, 0x00, 0x78, 0x78, 0x00, 0x78,\n  0xF0, 0x00, 0xF3, 0xC0, 0x01, 0xE7, 0x80, 0x03, 0xCF, 0x00, 0x07, 0x9C,\n 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0x00, 0x07, 0x87, 0x3F, 0x87, 0xC3, 0xC7, 0xE1,\n  0xE6, 0xF0, 0xF6, 0x00, 0x72, 0x00, 0x3A, 0x00, 0x1D, 0x00, 0x1F, 0x00,\n  0x0E, 0x80, 0x07, 0x80, 0x03, 0xC0, 0x03, 0xC0, 0x01, 0xE0, 0x00, 0xF0,\n  0x00, 0xF0, 0x00, 0x78, 0x00, 0x3C, 0x00, 0x1C, 0x00, 0x1E, 0x00, 0x0F,\n  0x00, 0x00, 0x01, 0xF8, 0x81, 0x87, 0xC1, 0x80, 0xE1, 0xC0, 0x60, 0xE0,\n  0x10, 0x70, 0x08, 0x3C, 0x04, 0x1F, 0x00, 0x07, 0xC0, 0x03, 0xE0, 0x00,\n  0xF8, 0x00, 0x3E, 0x00, 0x0F, 0x00, 0x03, 0xC1, 0x01, 0xE0, 0x80, 0x70,\n  0x40, 0x38, 0x30, 0x1C, 0x38, 0x0C, 0x1C, 0x0E, 0x0F, 0x0E, 0x04, 0x7C,\n  0x00, 0x00, 0xC0, 0x18, 0x03, 0x80, 0x78, 0x1F, 0x03, 0xFF, 0x7F, 0xF0,\n  0xF0, 0x0E, 0x00, 0xE0, 0x1E, 0x01, 0xE0, 0x1C, 0x01, 0xC0, 0x3C, 0x03,\n  0xC0, 0x38, 0x03, 0x80, 0x78, 0x07, 0x80, 0x70, 0x8F, 0x10, 0xF1, 0x0F,\n  0x20, 0xFC, 0x07, 0x80, 0x00, 0x00, 0x00, 0xF0, 0x0E, 0x7F, 0x00, 0xE0,\n  0xF0, 0x1E, 0x0E, 0x01, 0xE1, 0xE0, 0x3C, 0x1E, 0x03, 0xC1, 0xE0, 0x3C,\n  0x1C, 0x07, 0xC3, 0xC0, 0x78, 0x3C, 0x0F, 0x83, 0xC0, 0xB8, 0x38, 0x1F,\n  0x87, 0x83, 0x70, 0x78, 0x27, 0x07, 0x86, 0x70, 0x70, 0xC7, 0x1F, 0x08,\n  0xE1, 0xE1, 0x0E, 0x2E, 0x60, 0xE4, 0xFC, 0x0F, 0x87, 0x00, 0x70, 0x1C,\n  0x03, 0xBF, 0x00, 0xF1, 0xE0, 0x3C, 0x78, 0x07, 0x1E, 0x00, 0xC3, 0x80,\n  0x30, 0xE0, 0x08, 0x38, 0x06, 0x0E, 0x01, 0x03, 0x80, 0xC0, 0xF0, 0x20,\n  0x3C, 0x10, 0x07, 0x04, 0x01, 0xC2, 0x00, 0x71, 0x00, 0x1C, 0xC0, 0x07,\n  0x60, 0x01, 0xF0, 0x00, 0x78, 0x00, 0x1C, 0x00, 0x06, 0x00, 0x01, 0x00,\n  0x00, 0x0C, 0x00, 0x40, 0x3B, 0xF8, 0x01, 0x00, 0xF1, 0xE0, 0x0C, 0x03,\n  0xC3, 0x80, 0x78, 0x07, 0x0E, 0x01, 0xE0, 0x0C, 0x38, 0x0F, 0x80, 0x20,\n  0xE0, 0x6E, 0x00, 0x83, 0x81, 0x38, 0x04, 0x0F, 0x0C, 0xE0, 0x10, 0x1C,\n  0x23, 0x80, 0x80, 0x71, 0x8E, 0x06, 0x01, 0xCC, 0x38, 0x10, 0x07, 0x20,\n  0xE0, 0x80, 0x1D, 0x83, 0x86, 0x00, 0x7C, 0x07, 0x30, 0x01, 0xF0, 0x1C,\n  0x80, 0x07, 0x80, 0x74, 0x00, 0x1E, 0x01, 0xF0, 0x00, 0x70, 0x07, 0x80,\n  0x01, 0xC0, 0x1C, 0x00, 0x06, 0x00, 0x60, 0x00, 0x10, 0x01, 0x00, 0x00,\n  0x00, 0xE0, 0x38, 0x1F, 0x81, 0xF0, 0x8F, 0x09, 0x80, 0x3C, 0x40, 0x00,\n  0x72, 0x00, 0x01, 0xD0, 0x00, 0x07, 0xC0, 0x00, 0x1E, 0x00, 0x00, 0x38,\n  0x00, 0x00, 0xE0, 0x00, 0x03, 0x80, 0x00, 0x0F, 0x00, 0x00, 0x7C, 0x00,\n  0x01, 0x70, 0x00, 0x09, 0xC0, 0x00, 0x67, 0x00, 0x01, 0x1E, 0x10, 0x08,\n  0x38, 0x40, 0x40, 0xE2, 0x39, 0x03, 0xD0, 0xF8, 0x0F, 0x83, 0xC0, 0x1C,\n  0x00, 0x07, 0x80, 0x33, 0xFC, 0x03, 0xC1, 0xE0, 0x1E, 0x07, 0x80, 0x70,\n  0x3C, 0x01, 0x80, 0xE0, 0x0C, 0x07, 0x80, 0x40, 0x3C, 0x02, 0x00, 0xE0,\n  0x20, 0x07, 0x81, 0x00, 0x3C, 0x18, 0x01, 0xE0, 0x80, 0x07, 0x0C, 0x00,\n  0x38, 0x40, 0x01, 0xE4, 0x00, 0x0F, 0x60, 0x00, 0x3A, 0x00, 0x01, 0xF0,\n  0x00, 0x0F, 0x00, 0x00, 0x70, 0x00, 0x03, 0x80, 0x00, 0x18, 0x00, 0x00,\n  0x80, 0x00, 0x0C, 0x00, 0x00, 0x40, 0x00, 0x04, 0x00, 0x00, 0x40, 0x00,\n  0x04, 0x00, 0x0E, 0x40, 0x00, 0x7C, 0x00, 0x03, 0xC0, 0x00, 0x00, 0x0F,\n  0xFF, 0x87, 0xFF, 0x82, 0x00, 0x83, 0x00, 0xC1, 0x00, 0xC0, 0x00, 0xC0,\n  0x00, 0xC0, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x20,\n  0x00, 0x30, 0x00, 0x30, 0x00, 0x30, 0x00, 0x30, 0x00, 0x18, 0x00, 0x1E,\n  0x00, 0x1F, 0xC0, 0x1F, 0xF0, 0xE8, 0xFC, 0x70, 0x1E, 0x38, 0x03, 0x88,\n  0x00, 0x78, 0x00, 0x0F, 0x00, 0x1E, 0x00, 0x1E, 0x00, 0x0E, 0x00, 0x0F,\n  0x00, 0x07, 0x80, 0x03, 0x80, 0x01, 0xC0, 0x01, 0xE0, 0x00, 0xF0, 0x00,\n  0x70, 0x00, 0x78, 0x00, 0x3C, 0x00, 0x1C, 0x00, 0x0E, 0x00, 0x0F, 0x00,\n  0x07, 0x80, 0x07, 0x80, 0x03, 0xC0, 0x07, 0xC0, 0x07, 0xC0, 0x00, 0x80,\n  0x00, 0x60, 0x00, 0x38, 0x00, 0x1C, 0x00, 0x0E, 0x00, 0x0F, 0x00, 0x07,\n  0x80, 0x03, 0x80, 0x01, 0xC0, 0x01, 0xE0, 0x00, 0xF0, 0x00, 0x70, 0x00,\n  0x38, 0x00, 0x3C, 0x00, 0x1E, 0x00, 0x0E, 0x00, 0x07, 0x00, 0x01, 0x80,\n  0x00, 0x70, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n  0xFF, 0xFF, 0xFF, 0xE0, 0x00, 0x18, 0x00, 0x0E, 0x00, 0x06, 0x00, 0x07,\n  0x00, 0x07, 0x00, 0x07, 0x00, 0x07, 0x00, 0x0F, 0x00, 0x0F, 0x00, 0x0E,\n  0x00, 0x0E, 0x00, 0x1E, 0x00, 0x1E, 0x00, 0x1C, 0x00, 0x1C, 0x00, 0x3C,\n  0x00, 0x3C, 0x00, 0x38, 0x00, 0x38, 0x00, 0x18, 0x00, 0x08, 0x00, 0x1C,\n  0x00, 0x7E, 0x00, 0x78, 0x00, 0xF0, 0x00, 0xE0, 0x01, 0xE0, 0x01, 0xE0,\n  0x01, 0xC0, 0x01, 0xC0, 0x03, 0xC0, 0x03, 0x80, 0x03, 0x80, 0x07, 0x80,\n  0x07, 0x80, 0x07, 0x00, 0x07, 0x00, 0x0F, 0x00, 0x0E, 0x00, 0x1C, 0x00,\n  0xF8, 0x00, 0x1F, 0x80, 0x00, 0xFF, 0x80, 0xC7, 0xFF, 0x87, 0xBC, 0x3F,\n  0xFE, 0x60, 0x3F, 0xF0, 0x00, 0x1F, 0x00 };\n\nconst GFXglyph FreeSerifItalic24pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,  12,    0,    1 },   // 0x20 ' '\n  {     0,  12,  32,  16,    2,  -30 },   // 0x21 '!'\n  {    48,  14,  12,  16,    6,  -31 },   // 0x22 '\"'\n  {    69,  25,  31,  23,    0,  -30 },   // 0x23 '#'\n  {   166,  21,  38,  24,    2,  -33 },   // 0x24 '$'\n  {   266,  33,  32,  39,    4,  -30 },   // 0x25 '%'\n  {   398,  30,  33,  37,    4,  -31 },   // 0x26 '&'\n  {   522,   5,  12,   9,    6,  -31 },   // 0x27 '''\n  {   530,  13,  39,  16,    2,  -30 },   // 0x28 '('\n  {   594,  13,  39,  16,    0,  -30 },   // 0x29 ')'\n  {   658,  16,  20,  23,    7,  -31 },   // 0x2A '*'\n  {   698,  23,  23,  32,    4,  -22 },   // 0x2B '+'\n  {   765,   7,  11,  12,   -1,   -4 },   // 0x2C ','\n  {   775,  11,   3,  16,    2,  -11 },   // 0x2D '-'\n  {   780,   5,   5,  12,    1,   -3 },   // 0x2E '.'\n  {   784,  21,  33,  14,    0,  -31 },   // 0x2F '/'\n  {   871,  21,  31,  23,    2,  -30 },   // 0x30 '0'\n  {   953,  17,  32,  23,    2,  -31 },   // 0x31 '1'\n  {  1021,  21,  31,  24,    0,  -30 },   // 0x32 '2'\n  {  1103,  22,  32,  23,    0,  -31 },   // 0x33 '3'\n  {  1191,  22,  32,  23,    0,  -31 },   // 0x34 '4'\n  {  1279,  22,  32,  24,    0,  -31 },   // 0x35 '5'\n  {  1367,  23,  32,  23,    1,  -31 },   // 0x36 '6'\n  {  1459,  21,  32,  23,    4,  -31 },   // 0x37 '7'\n  {  1543,  22,  32,  23,    1,  -31 },   // 0x38 '8'\n  {  1631,  22,  33,  23,    1,  -31 },   // 0x39 '9'\n  {  1722,   9,  22,  12,    2,  -20 },   // 0x3A ':'\n  {  1747,  11,  27,  12,    1,  -20 },   // 0x3B ';'\n  {  1785,  23,  25,  27,    3,  -24 },   // 0x3C '<'\n  {  1857,  24,  12,  31,    4,  -17 },   // 0x3D '='\n  {  1893,  24,  25,  27,    3,  -24 },   // 0x3E '>'\n  {  1968,  16,  33,  21,    6,  -31 },   // 0x3F '?'\n  {  2034,  33,  33,  37,    3,  -31 },   // 0x40 '@'\n  {  2171,  29,  31,  31,    0,  -30 },   // 0x41 'A'\n  {  2284,  28,  31,  28,    0,  -30 },   // 0x42 'B'\n  {  2393,  30,  33,  29,    2,  -31 },   // 0x43 'C'\n  {  2517,  33,  31,  33,    0,  -30 },   // 0x44 'D'\n  {  2645,  29,  31,  27,    0,  -30 },   // 0x45 'E'\n  {  2758,  29,  31,  27,    0,  -30 },   // 0x46 'F'\n  {  2871,  31,  33,  32,    2,  -31 },   // 0x47 'G'\n  {  2999,  36,  31,  33,    0,  -30 },   // 0x48 'H'\n  {  3139,  18,  31,  15,    0,  -30 },   // 0x49 'I'\n  {  3209,  23,  32,  20,    0,  -30 },   // 0x4A 'J'\n  {  3301,  33,  31,  30,    0,  -30 },   // 0x4B 'K'\n  {  3429,  27,  31,  27,    0,  -30 },   // 0x4C 'L'\n  {  3534,  42,  31,  39,    0,  -30 },   // 0x4D 'M'\n  {  3697,  35,  32,  32,    0,  -30 },   // 0x4E 'N'\n  {  3837,  30,  33,  31,    2,  -31 },   // 0x4F 'O'\n  {  3961,  29,  31,  27,    0,  -30 },   // 0x50 'P'\n  {  4074,  30,  41,  31,    2,  -31 },   // 0x51 'Q'\n  {  4228,  28,  31,  29,    0,  -30 },   // 0x52 'R'\n  {  4337,  23,  33,  21,    0,  -31 },   // 0x53 'S'\n  {  4432,  27,  31,  28,    4,  -30 },   // 0x54 'T'\n  {  4537,  31,  32,  33,    5,  -30 },   // 0x55 'U'\n  {  4661,  29,  32,  31,    6,  -30 },   // 0x56 'V'\n  {  4777,  39,  32,  42,    6,  -30 },   // 0x57 'W'\n  {  4933,  32,  31,  31,    0,  -30 },   // 0x58 'X'\n  {  5057,  26,  31,  28,    5,  -30 },   // 0x59 'Y'\n  {  5158,  29,  31,  26,    0,  -30 },   // 0x5A 'Z'\n  {  5271,  17,  39,  18,    1,  -31 },   // 0x5B '['\n  {  5354,  17,  33,  23,    5,  -31 },   // 0x5C '\\'\n  {  5425,  17,  39,  18,    1,  -31 },   // 0x5D ']'\n  {  5508,  20,  17,  20,    0,  -31 },   // 0x5E '^'\n  {  5551,  24,   2,  23,    0,    5 },   // 0x5F '_'\n  {  5557,   8,   8,  12,    6,  -31 },   // 0x60 '`'\n  {  5565,  21,  21,  23,    1,  -20 },   // 0x61 'a'\n  {  5621,  21,  33,  22,    1,  -31 },   // 0x62 'b'\n  {  5708,  18,  22,  19,    1,  -20 },   // 0x63 'c'\n  {  5758,  24,  33,  23,    1,  -31 },   // 0x64 'd'\n  {  5857,  18,  22,  19,    1,  -20 },   // 0x65 'e'\n  {  5907,  27,  42,  20,   -4,  -31 },   // 0x66 'f'\n  {  6049,  21,  31,  21,   -1,  -20 },   // 0x67 'g'\n  {  6131,  21,  32,  23,    1,  -31 },   // 0x68 'h'\n  {  6215,  10,  32,  12,    2,  -30 },   // 0x69 'i'\n  {  6255,  19,  41,  13,   -3,  -30 },   // 0x6A 'j'\n  {  6353,  21,  33,  21,    1,  -31 },   // 0x6B 'k'\n  {  6440,  11,  33,  12,    2,  -31 },   // 0x6C 'l'\n  {  6486,  31,  21,  34,    1,  -20 },   // 0x6D 'm'\n  {  6568,  21,  21,  23,    1,  -20 },   // 0x6E 'n'\n  {  6624,  21,  22,  22,    1,  -20 },   // 0x6F 'o'\n  {  6682,  27,  31,  22,   -4,  -20 },   // 0x70 'p'\n  {  6787,  21,  31,  23,    1,  -20 },   // 0x71 'q'\n  {  6869,  17,  21,  17,    1,  -20 },   // 0x72 'r'\n  {  6914,  17,  22,  16,    0,  -20 },   // 0x73 's'\n  {  6961,  12,  26,  11,    1,  -24 },   // 0x74 't'\n  {  7000,  20,  22,  23,    1,  -20 },   // 0x75 'u'\n  {  7055,  18,  22,  21,    3,  -20 },   // 0x76 'v'\n  {  7105,  30,  22,  32,    2,  -20 },   // 0x77 'w'\n  {  7188,  22,  22,  20,   -1,  -20 },   // 0x78 'x'\n  {  7249,  21,  31,  22,    1,  -20 },   // 0x79 'y'\n  {  7331,  17,  24,  18,    0,  -19 },   // 0x7A 'z'\n  {  7382,  17,  40,  19,    2,  -31 },   // 0x7B '{'\n  {  7467,   3,  33,  13,    5,  -31 },   // 0x7C '|'\n  {  7480,  16,  41,  19,    0,  -32 },   // 0x7D '}'\n  {  7562,  22,   6,  25,    2,  -14 } }; // 0x7E '~'\n\nconst GFXfont FreeSerifItalic24pt7b PROGMEM = {\n  (uint8_t  *)FreeSerifItalic24pt7bBitmaps,\n  (GFXglyph *)FreeSerifItalic24pt7bGlyphs,\n  0x20, 0x7E, 56 };\n\n// Approx. 8251 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/FreeSerifItalic9pt7b.h",
    "content": "const uint8_t FreeSerifItalic9pt7bBitmaps[] PROGMEM = {\n  0x11, 0x12, 0x22, 0x24, 0x40, 0x0C, 0xDE, 0xE5, 0x40, 0x04, 0x82, 0x20,\n  0x98, 0x24, 0x7F, 0xC4, 0x82, 0x23, 0xFC, 0x24, 0x11, 0x04, 0x83, 0x20,\n  0x1C, 0x1B, 0x99, 0x4D, 0x26, 0x81, 0xC0, 0x70, 0x1C, 0x13, 0x49, 0xA4,\n  0xDA, 0xC7, 0xC1, 0x00, 0x80, 0x1C, 0x61, 0xCF, 0x0E, 0x28, 0x30, 0xA0,\n  0xC5, 0x03, 0x34, 0xE7, 0xAE, 0x40, 0xB1, 0x05, 0x84, 0x26, 0x20, 0x99,\n  0x84, 0x3C, 0x03, 0x80, 0x6C, 0x06, 0xC0, 0x78, 0x06, 0x01, 0xEF, 0x66,\n  0x24, 0x24, 0xC3, 0x8C, 0x10, 0xE3, 0x87, 0xCE, 0xFA, 0x08, 0x21, 0x08,\n  0x61, 0x8C, 0x30, 0xC3, 0x0C, 0x30, 0x41, 0x02, 0x00, 0x10, 0x40, 0x82,\n  0x0C, 0x30, 0xC3, 0x0C, 0x61, 0x84, 0x21, 0x08, 0x00, 0x30, 0xCA, 0x5E,\n  0x6A, 0x93, 0x08, 0x08, 0x04, 0x02, 0x01, 0x0F, 0xF8, 0x40, 0x20, 0x10,\n  0x08, 0x00, 0x56, 0xF0, 0xF0, 0x03, 0x02, 0x06, 0x04, 0x08, 0x08, 0x10,\n  0x30, 0x20, 0x60, 0x40, 0xC0, 0x0E, 0x0C, 0x8C, 0x6C, 0x36, 0x1F, 0x0F,\n  0x07, 0x87, 0xC3, 0x61, 0xB1, 0x88, 0x83, 0x80, 0x04, 0x70, 0xC3, 0x08,\n  0x21, 0x86, 0x10, 0x43, 0x08, 0xF8, 0x1C, 0x67, 0x83, 0x03, 0x02, 0x06,\n  0x0C, 0x08, 0x10, 0x20, 0x42, 0xFC, 0x0F, 0x08, 0xC0, 0x60, 0xC1, 0xE0,\n  0x38, 0x0C, 0x06, 0x03, 0x01, 0x01, 0x1F, 0x00, 0x01, 0x01, 0x81, 0x41,\n  0x61, 0x21, 0x11, 0x18, 0x88, 0xFF, 0x02, 0x03, 0x01, 0x00, 0x0F, 0x84,\n  0x04, 0x03, 0x80, 0x60, 0x18, 0x0C, 0x06, 0x03, 0x03, 0x03, 0x1E, 0x00,\n  0x01, 0x83, 0x87, 0x07, 0x03, 0x03, 0x73, 0xCD, 0x86, 0xC3, 0x61, 0xB1,\n  0x88, 0xC3, 0xC0, 0x7F, 0x40, 0x80, 0x80, 0x40, 0x40, 0x60, 0x20, 0x20,\n  0x10, 0x10, 0x18, 0x08, 0x00, 0x1E, 0x19, 0xCC, 0x66, 0x33, 0xB0, 0xE0,\n  0x50, 0xCC, 0xC3, 0x61, 0xB0, 0xCC, 0xC3, 0xC0, 0x0E, 0x19, 0x8C, 0x6C,\n  0x36, 0x1B, 0x0D, 0x86, 0xE6, 0x3F, 0x03, 0x03, 0x06, 0x0C, 0x00, 0x33,\n  0x00, 0x00, 0xCC, 0x33, 0x00, 0x00, 0x44, 0x48, 0x01, 0x83, 0x86, 0x1C,\n  0x0C, 0x03, 0x80, 0x30, 0x07, 0x00, 0x80, 0xFF, 0x80, 0x00, 0x00, 0x0F,\n  0xF8, 0xC0, 0x1C, 0x03, 0x80, 0x70, 0x18, 0x38, 0x70, 0xC0, 0x80, 0x00,\n  0x3C, 0x8C, 0x18, 0x30, 0xC3, 0x0C, 0x20, 0x40, 0x80, 0x06, 0x00, 0x0F,\n  0xC0, 0xC3, 0x0C, 0x04, 0xC7, 0xBC, 0x64, 0xE2, 0x27, 0x31, 0x39, 0x91,\n  0xCC, 0x93, 0x3B, 0x0E, 0x00, 0x1F, 0x80, 0x01, 0x00, 0x60, 0x14, 0x04,\n  0xC0, 0x98, 0x23, 0x07, 0xE1, 0x04, 0x20, 0x88, 0x1B, 0x8F, 0x80, 0x3F,\n  0xC1, 0x8C, 0x21, 0x8C, 0x31, 0x8C, 0x3E, 0x04, 0x61, 0x86, 0x30, 0xC4,\n  0x19, 0x86, 0x7F, 0x80, 0x07, 0x91, 0x86, 0x30, 0x26, 0x02, 0x60, 0x0C,\n  0x00, 0xC0, 0x0C, 0x00, 0xC0, 0x0C, 0x00, 0x61, 0x83, 0xE0, 0x3F, 0xC0,\n  0x63, 0x82, 0x0C, 0x30, 0x31, 0x81, 0x8C, 0x0C, 0x40, 0x66, 0x07, 0x30,\n  0x31, 0x03, 0x18, 0x71, 0xFE, 0x00, 0x3F, 0xF0, 0xC2, 0x08, 0x21, 0x80,\n  0x19, 0x81, 0xF8, 0x11, 0x03, 0x10, 0x30, 0x02, 0x04, 0x60, 0x8F, 0xF8,\n  0x3F, 0xF0, 0xC2, 0x08, 0x21, 0x80, 0x19, 0x81, 0xF8, 0x11, 0x03, 0x10,\n  0x30, 0x02, 0x00, 0x60, 0x0F, 0x80, 0x07, 0x91, 0x87, 0x30, 0x26, 0x02,\n  0x60, 0x0C, 0x00, 0xC1, 0xFC, 0x0C, 0xC0, 0xCC, 0x0C, 0x60, 0x83, 0xF0,\n  0x3E, 0x3C, 0x30, 0x60, 0x81, 0x06, 0x0C, 0x18, 0x30, 0x7F, 0x81, 0x06,\n  0x0C, 0x18, 0x30, 0x60, 0x81, 0x06, 0x0C, 0x3C, 0x78, 0x1E, 0x18, 0x20,\n  0xC1, 0x83, 0x04, 0x18, 0x30, 0x41, 0x87, 0x80, 0x0F, 0x81, 0x80, 0x80,\n  0xC0, 0x60, 0x20, 0x30, 0x18, 0x0C, 0x04, 0x36, 0x1E, 0x00, 0x3E, 0x78,\n  0x61, 0x82, 0x10, 0x31, 0x01, 0xB0, 0x0E, 0x00, 0x58, 0x06, 0x60, 0x33,\n  0x01, 0x0C, 0x18, 0x61, 0xE7, 0xC0, 0x3E, 0x01, 0x80, 0x20, 0x0C, 0x01,\n  0x80, 0x30, 0x04, 0x01, 0x80, 0x30, 0x04, 0x0D, 0x83, 0x7F, 0xE0, 0x1C,\n  0x07, 0x0C, 0x0E, 0x0C, 0x14, 0x14, 0x1C, 0x14, 0x2C, 0x16, 0x4C, 0x26,\n  0x48, 0x26, 0x98, 0x27, 0x18, 0x27, 0x10, 0x42, 0x30, 0xF4, 0x7C, 0x38,\n  0x78, 0x60, 0x83, 0x04, 0x2C, 0x41, 0x22, 0x09, 0x10, 0x4D, 0x84, 0x28,\n  0x21, 0x41, 0x06, 0x10, 0x21, 0xE1, 0x00, 0x07, 0x83, 0x18, 0xC1, 0xB0,\n  0x36, 0x07, 0xC0, 0xF0, 0x3E, 0x06, 0xC0, 0xD8, 0x31, 0x8C, 0x1E, 0x00,\n  0x3F, 0xC1, 0x9C, 0x21, 0x8C, 0x31, 0x86, 0x31, 0x87, 0xE1, 0x80, 0x30,\n  0x04, 0x01, 0x80, 0x78, 0x00, 0x07, 0x83, 0x18, 0xC1, 0x98, 0x36, 0x07,\n  0xC0, 0xF0, 0x1E, 0x06, 0xC0, 0xD8, 0x31, 0x04, 0x13, 0x01, 0x80, 0x70,\n  0xB7, 0xE0, 0x3F, 0xC1, 0x8C, 0x21, 0x8C, 0x31, 0x8C, 0x3F, 0x04, 0xC1,\n  0x98, 0x31, 0x84, 0x31, 0x86, 0x78, 0x70, 0x1E, 0x4C, 0x63, 0x08, 0xC0,\n  0x38, 0x07, 0x00, 0x60, 0x0C, 0x43, 0x10, 0xC6, 0x62, 0x70, 0x7F, 0xE9,\n  0x8E, 0x31, 0x04, 0x01, 0x80, 0x30, 0x06, 0x00, 0x80, 0x30, 0x06, 0x00,\n  0x80, 0x7E, 0x00, 0x7C, 0xF3, 0x02, 0x30, 0x46, 0x04, 0x60, 0x46, 0x04,\n  0x40, 0x8C, 0x08, 0xC0, 0x8C, 0x10, 0xE3, 0x03, 0xC0, 0xF8, 0xEC, 0x0C,\n  0x81, 0x18, 0x43, 0x08, 0x62, 0x0C, 0x81, 0x90, 0x14, 0x03, 0x00, 0x60,\n  0x08, 0x00, 0xFB, 0xCE, 0x43, 0x0C, 0x86, 0x11, 0x8C, 0x43, 0x38, 0x86,\n  0xB2, 0x0D, 0x24, 0x1C, 0x50, 0x38, 0xA0, 0x21, 0x80, 0x42, 0x01, 0x04,\n  0x00, 0x3E, 0x71, 0x82, 0x0C, 0x40, 0xC8, 0x07, 0x00, 0x60, 0x06, 0x00,\n  0xB0, 0x13, 0x02, 0x18, 0x61, 0x8F, 0x3E, 0xF9, 0xC8, 0x23, 0x10, 0xC8,\n  0x34, 0x05, 0x01, 0x80, 0x40, 0x30, 0x0C, 0x03, 0x03, 0xE0, 0x3F, 0xE4,\n  0x19, 0x03, 0x00, 0xC0, 0x30, 0x0C, 0x03, 0x00, 0x40, 0x18, 0x06, 0x05,\n  0x81, 0x7F, 0xE0, 0x0E, 0x10, 0x20, 0x81, 0x02, 0x04, 0x10, 0x20, 0x40,\n  0x82, 0x04, 0x08, 0x1C, 0x00, 0x81, 0x04, 0x18, 0x20, 0xC1, 0x04, 0x08,\n  0x20, 0x41, 0x38, 0x20, 0x82, 0x08, 0x41, 0x04, 0x10, 0xC2, 0x08, 0x20,\n  0x8C, 0x00, 0x18, 0x18, 0x2C, 0x24, 0x46, 0x42, 0x83, 0xFF, 0x80, 0xD8,\n  0x80, 0x1F, 0x98, 0x98, 0x4C, 0x2C, 0x36, 0x33, 0x3A, 0xEE, 0x38, 0x08,\n  0x04, 0x02, 0x03, 0x71, 0xCC, 0xC6, 0xC3, 0x63, 0x21, 0x93, 0x8F, 0x00,\n  0x1F, 0x33, 0x60, 0xC0, 0xC0, 0xC0, 0xC4, 0x78, 0x01, 0x80, 0x40, 0x60,\n  0x20, 0xF1, 0x89, 0x8C, 0xC4, 0xC2, 0x63, 0x33, 0xAE, 0xE0, 0x0E, 0x65,\n  0x8B, 0x2F, 0x98, 0x31, 0x3C, 0x01, 0xE0, 0x40, 0x08, 0x02, 0x00, 0x40,\n  0x3E, 0x03, 0x00, 0x40, 0x08, 0x01, 0x00, 0x60, 0x0C, 0x01, 0x00, 0x20,\n  0x04, 0x01, 0x00, 0xC0, 0x00, 0x1E, 0x19, 0xD8, 0xCC, 0xE1, 0xC3, 0x01,\n  0xE0, 0xBC, 0x82, 0x41, 0x31, 0x0F, 0x00, 0x38, 0x08, 0x04, 0x02, 0x03,\n  0x39, 0x6C, 0xC6, 0x46, 0x63, 0x21, 0x11, 0xB8, 0xE0, 0x30, 0x00, 0xE2,\n  0x44, 0xC8, 0xCE, 0x06, 0x00, 0x00, 0x00, 0xC0, 0x83, 0x04, 0x08, 0x10,\n  0x60, 0x81, 0x02, 0x04, 0x70, 0x38, 0x10, 0x10, 0x10, 0x37, 0x22, 0x24,\n  0x38, 0x78, 0x48, 0x4D, 0xC6, 0x73, 0x32, 0x26, 0x64, 0x4C, 0xDE, 0x77,\n  0x39, 0x5E, 0xCC, 0xCC, 0xCE, 0x66, 0x62, 0x22, 0x11, 0x11, 0xB9, 0x8E,\n  0x77, 0x3B, 0x33, 0x62, 0x62, 0x42, 0x4D, 0xCE, 0x0F, 0x18, 0xD8, 0x7C,\n  0x3C, 0x3E, 0x1B, 0x18, 0xF0, 0x3B, 0x87, 0x31, 0x8C, 0x43, 0x31, 0x88,\n  0x62, 0x30, 0xF0, 0x60, 0x10, 0x04, 0x03, 0x80, 0x0F, 0x18, 0x98, 0x4C,\n  0x2C, 0x26, 0x33, 0x38, 0xEC, 0x04, 0x02, 0x03, 0x03, 0xC0, 0x76, 0x50,\n  0xC1, 0x06, 0x08, 0x10, 0x60, 0x1A, 0x6C, 0xC8, 0xC0, 0xD1, 0xB3, 0x5C,\n  0x23, 0xC8, 0xC4, 0x21, 0x18, 0xE0, 0xC3, 0x42, 0x42, 0xC6, 0x86, 0x8C,\n  0x9D, 0xEE, 0x62, 0xC4, 0x89, 0xA3, 0x47, 0x0C, 0x10, 0xE2, 0x2C, 0x44,\n  0xD8, 0x9D, 0x23, 0xA4, 0x65, 0x0C, 0xC1, 0x10, 0x19, 0x95, 0x43, 0x01,\n  0x80, 0xC0, 0xA0, 0x91, 0x8E, 0x70, 0x88, 0x46, 0x23, 0x20, 0x90, 0x50,\n  0x28, 0x18, 0x08, 0x08, 0x08, 0x18, 0x00, 0x3F, 0x42, 0x04, 0x08, 0x10,\n  0x20, 0x40, 0x72, 0x0E, 0x08, 0x61, 0x04, 0x30, 0x86, 0x08, 0x61, 0x04,\n  0x30, 0xC3, 0x8F, 0x00, 0xFF, 0xF0, 0x1E, 0x0C, 0x10, 0x20, 0xC1, 0x82,\n  0x04, 0x1C, 0x30, 0x40, 0x83, 0x04, 0x08, 0x20, 0x60, 0x99, 0x8E };\n\nconst GFXglyph FreeSerifItalic9pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,   5,    0,    1 },   // 0x20 ' '\n  {     0,   4,  12,   6,    1,  -11 },   // 0x21 '!'\n  {     6,   5,   4,   6,    3,  -11 },   // 0x22 '\"'\n  {     9,  10,  12,   9,    0,  -11 },   // 0x23 '#'\n  {    24,   9,  15,   9,    1,  -12 },   // 0x24 '$'\n  {    41,  14,  12,  15,    1,  -11 },   // 0x25 '%'\n  {    62,  12,  12,  14,    1,  -11 },   // 0x26 '&'\n  {    80,   2,   4,   4,    3,  -11 },   // 0x27 '''\n  {    81,   6,  15,   6,    1,  -11 },   // 0x28 '('\n  {    93,   6,  15,   6,    0,  -11 },   // 0x29 ')'\n  {   105,   6,   8,   9,    3,  -11 },   // 0x2A '*'\n  {   111,   9,   9,  12,    1,   -8 },   // 0x2B '+'\n  {   122,   2,   4,   5,    0,   -1 },   // 0x2C ','\n  {   123,   4,   1,   6,    1,   -3 },   // 0x2D '-'\n  {   124,   2,   2,   5,    0,   -1 },   // 0x2E '.'\n  {   125,   8,  12,   5,    0,  -11 },   // 0x2F '/'\n  {   137,   9,  13,   9,    1,  -12 },   // 0x30 '0'\n  {   152,   6,  13,   9,    1,  -12 },   // 0x31 '1'\n  {   162,   8,  12,   9,    1,  -11 },   // 0x32 '2'\n  {   174,   9,  12,   9,    0,  -11 },   // 0x33 '3'\n  {   188,   9,  12,   9,    0,  -11 },   // 0x34 '4'\n  {   202,   9,  12,   9,    0,  -11 },   // 0x35 '5'\n  {   216,   9,  13,   9,    1,  -12 },   // 0x36 '6'\n  {   231,   9,  12,   9,    1,  -11 },   // 0x37 '7'\n  {   245,   9,  13,   9,    1,  -12 },   // 0x38 '8'\n  {   260,   9,  13,   9,    0,  -12 },   // 0x39 '9'\n  {   275,   4,   8,   4,    1,   -7 },   // 0x3A ':'\n  {   279,   4,  10,   4,    1,   -7 },   // 0x3B ';'\n  {   284,   9,   9,  10,    1,   -8 },   // 0x3C '<'\n  {   295,   9,   5,  12,    2,   -6 },   // 0x3D '='\n  {   301,   9,   9,  10,    1,   -8 },   // 0x3E '>'\n  {   312,   7,  12,   8,    2,  -11 },   // 0x3F '?'\n  {   323,  13,  12,  14,    1,  -11 },   // 0x40 '@'\n  {   343,  11,  11,  12,    0,  -10 },   // 0x41 'A'\n  {   359,  11,  12,  11,    0,  -11 },   // 0x42 'B'\n  {   376,  12,  12,  11,    1,  -11 },   // 0x43 'C'\n  {   394,  13,  12,  13,    0,  -11 },   // 0x44 'D'\n  {   414,  12,  12,  10,    0,  -11 },   // 0x45 'E'\n  {   432,  12,  12,  10,    0,  -11 },   // 0x46 'F'\n  {   450,  12,  12,  12,    1,  -11 },   // 0x47 'G'\n  {   468,  14,  12,  13,    0,  -11 },   // 0x48 'H'\n  {   489,   7,  12,   6,    0,  -11 },   // 0x49 'I'\n  {   500,   9,  12,   8,    0,  -11 },   // 0x4A 'J'\n  {   514,  13,  12,  12,    0,  -11 },   // 0x4B 'K'\n  {   534,  11,  12,  10,    0,  -11 },   // 0x4C 'L'\n  {   551,  16,  12,  15,    0,  -11 },   // 0x4D 'M'\n  {   575,  13,  12,  12,    0,  -11 },   // 0x4E 'N'\n  {   595,  11,  12,  12,    1,  -11 },   // 0x4F 'O'\n  {   612,  11,  12,  10,    0,  -11 },   // 0x50 'P'\n  {   629,  11,  15,  12,    1,  -11 },   // 0x51 'Q'\n  {   650,  11,  12,  11,    0,  -11 },   // 0x52 'R'\n  {   667,  10,  12,   8,    0,  -11 },   // 0x53 'S'\n  {   682,  11,  12,  11,    2,  -11 },   // 0x54 'T'\n  {   699,  12,  12,  13,    2,  -11 },   // 0x55 'U'\n  {   717,  11,  12,  12,    2,  -11 },   // 0x56 'V'\n  {   734,  15,  12,  16,    2,  -11 },   // 0x57 'W'\n  {   757,  12,  12,  12,    0,  -11 },   // 0x58 'X'\n  {   775,  10,  12,  11,    2,  -11 },   // 0x59 'Y'\n  {   790,  11,  12,  10,    0,  -11 },   // 0x5A 'Z'\n  {   807,   7,  15,   7,    0,  -11 },   // 0x5B '['\n  {   821,   6,  12,   9,    2,  -11 },   // 0x5C '\\'\n  {   830,   6,  15,   7,    1,  -11 },   // 0x5D ']'\n  {   842,   8,   7,   8,    0,  -11 },   // 0x5E '^'\n  {   849,   9,   1,   9,    0,    2 },   // 0x5F '_'\n  {   851,   3,   3,   5,    2,  -11 },   // 0x60 '`'\n  {   853,   9,   8,   9,    0,   -7 },   // 0x61 'a'\n  {   862,   9,  12,   9,    0,  -11 },   // 0x62 'b'\n  {   876,   8,   8,   7,    0,   -7 },   // 0x63 'c'\n  {   884,   9,  12,   9,    0,  -11 },   // 0x64 'd'\n  {   898,   7,   8,   7,    0,   -7 },   // 0x65 'e'\n  {   905,  11,  17,   8,   -1,  -12 },   // 0x66 'f'\n  {   929,   9,  12,   8,    0,   -7 },   // 0x67 'g'\n  {   943,   9,  12,   9,    0,  -11 },   // 0x68 'h'\n  {   957,   4,  12,   4,    1,  -11 },   // 0x69 'i'\n  {   963,   7,  16,   5,   -1,  -11 },   // 0x6A 'j'\n  {   977,   8,  12,   8,    0,  -11 },   // 0x6B 'k'\n  {   989,   4,  12,   5,    1,  -11 },   // 0x6C 'l'\n  {   995,  13,   8,  13,    0,   -7 },   // 0x6D 'm'\n  {  1008,   8,   8,   9,    0,   -7 },   // 0x6E 'n'\n  {  1016,   9,   8,   9,    0,   -7 },   // 0x6F 'o'\n  {  1025,  10,  12,   8,   -1,   -7 },   // 0x70 'p'\n  {  1040,   9,  12,   9,    0,   -7 },   // 0x71 'q'\n  {  1054,   7,   8,   7,    0,   -7 },   // 0x72 'r'\n  {  1061,   7,   8,   6,    0,   -7 },   // 0x73 's'\n  {  1068,   5,   9,   4,    0,   -8 },   // 0x74 't'\n  {  1074,   8,   8,   9,    1,   -7 },   // 0x75 'u'\n  {  1082,   7,   8,   8,    1,   -7 },   // 0x76 'v'\n  {  1089,  11,   8,  12,    1,   -7 },   // 0x77 'w'\n  {  1100,   9,   8,   8,   -1,   -7 },   // 0x78 'x'\n  {  1109,   9,  12,   9,    0,   -7 },   // 0x79 'y'\n  {  1123,   8,   9,   7,    0,   -7 },   // 0x7A 'z'\n  {  1132,   6,  15,   7,    1,  -11 },   // 0x7B '{'\n  {  1144,   1,  12,   5,    2,  -11 },   // 0x7C '|'\n  {  1146,   7,  16,   7,    0,  -12 },   // 0x7D '}'\n  {  1160,   8,   3,  10,    1,   -5 } }; // 0x7E '~'\n\nconst GFXfont FreeSerifItalic9pt7b PROGMEM = {\n  (uint8_t  *)FreeSerifItalic9pt7bBitmaps,\n  (GFXglyph *)FreeSerifItalic9pt7bGlyphs,\n  0x20, 0x7E, 22 };\n\n// Approx. 1835 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/Org_01.h",
    "content": "// Org_v01 by Orgdot (www.orgdot.com/aliasfonts).  A tiny,\n// stylized font with all characters within a 6 pixel height.\n\nconst uint8_t Org_01Bitmaps[] PROGMEM = {\n  0xE8, 0xA0, 0x57, 0xD5, 0xF5, 0x00, 0xFD, 0x3E, 0x5F, 0x80, 0x88, 0x88,\n  0x88, 0x80, 0xF4, 0xBF, 0x2E, 0x80, 0x80, 0x6A, 0x40, 0x95, 0x80, 0xAA,\n  0x80, 0x5D, 0x00, 0xC0, 0xF0, 0x80, 0x08, 0x88, 0x88, 0x00, 0xFC, 0x63,\n  0x1F, 0x80, 0xF8, 0xF8, 0x7F, 0x0F, 0x80, 0xF8, 0x7E, 0x1F, 0x80, 0x8C,\n  0x7E, 0x10, 0x80, 0xFC, 0x3E, 0x1F, 0x80, 0xFC, 0x3F, 0x1F, 0x80, 0xF8,\n  0x42, 0x10, 0x80, 0xFC, 0x7F, 0x1F, 0x80, 0xFC, 0x7E, 0x1F, 0x80, 0x90,\n  0xB0, 0x2A, 0x22, 0xF0, 0xF0, 0x88, 0xA8, 0xF8, 0x4E, 0x02, 0x00, 0xFD,\n  0x6F, 0x0F, 0x80, 0xFC, 0x7F, 0x18, 0x80, 0xF4, 0x7D, 0x1F, 0x00, 0xFC,\n  0x21, 0x0F, 0x80, 0xF4, 0x63, 0x1F, 0x00, 0xFC, 0x3F, 0x0F, 0x80, 0xFC,\n  0x3F, 0x08, 0x00, 0xFC, 0x2F, 0x1F, 0x80, 0x8C, 0x7F, 0x18, 0x80, 0xF9,\n  0x08, 0x4F, 0x80, 0x78, 0x85, 0x2F, 0x80, 0x8D, 0xB1, 0x68, 0x80, 0x84,\n  0x21, 0x0F, 0x80, 0xFD, 0x6B, 0x5A, 0x80, 0xFC, 0x63, 0x18, 0x80, 0xFC,\n  0x63, 0x1F, 0x80, 0xFC, 0x7F, 0x08, 0x00, 0xFC, 0x63, 0x3F, 0x80, 0xFC,\n  0x7F, 0x29, 0x00, 0xFC, 0x3E, 0x1F, 0x80, 0xF9, 0x08, 0x42, 0x00, 0x8C,\n  0x63, 0x1F, 0x80, 0x8C, 0x62, 0xA2, 0x00, 0xAD, 0x6B, 0x5F, 0x80, 0x8A,\n  0x88, 0xA8, 0x80, 0x8C, 0x54, 0x42, 0x00, 0xF8, 0x7F, 0x0F, 0x80, 0xEA,\n  0xC0, 0x82, 0x08, 0x20, 0x80, 0xD5, 0xC0, 0x54, 0xF8, 0x80, 0xF1, 0xFF,\n  0x8F, 0x99, 0xF0, 0xF8, 0x8F, 0x1F, 0x99, 0xF0, 0xFF, 0x8F, 0x6B, 0xA4,\n  0xF9, 0x9F, 0x10, 0x8F, 0x99, 0x90, 0xF0, 0x55, 0xC0, 0x8A, 0xF9, 0x90,\n  0xF8, 0xFD, 0x63, 0x10, 0xF9, 0x99, 0xF9, 0x9F, 0xF9, 0x9F, 0x80, 0xF9,\n  0x9F, 0x20, 0xF8, 0x88, 0x47, 0x1F, 0x27, 0xC8, 0x42, 0x00, 0x99, 0x9F,\n  0x99, 0x97, 0x8C, 0x6B, 0xF0, 0x96, 0x69, 0x99, 0x9F, 0x10, 0x2E, 0x8F,\n  0x2B, 0x22, 0xF8, 0x89, 0xA8, 0x0F, 0xE0 };\n\nconst GFXglyph Org_01Glyphs[] PROGMEM = {\n  {     0,   0,   0,   6,    0,    1 },   // 0x20 ' '\n  {     0,   1,   5,   2,    0,   -4 },   // 0x21 '!'\n  {     1,   3,   1,   4,    0,   -4 },   // 0x22 '\"'\n  {     2,   5,   5,   6,    0,   -4 },   // 0x23 '#'\n  {     6,   5,   5,   6,    0,   -4 },   // 0x24 '$'\n  {    10,   5,   5,   6,    0,   -4 },   // 0x25 '%'\n  {    14,   5,   5,   6,    0,   -4 },   // 0x26 '&'\n  {    18,   1,   1,   2,    0,   -4 },   // 0x27 '''\n  {    19,   2,   5,   3,    0,   -4 },   // 0x28 '('\n  {    21,   2,   5,   3,    0,   -4 },   // 0x29 ')'\n  {    23,   3,   3,   4,    0,   -3 },   // 0x2A '*'\n  {    25,   3,   3,   4,    0,   -3 },   // 0x2B '+'\n  {    27,   1,   2,   2,    0,    0 },   // 0x2C ','\n  {    28,   4,   1,   5,    0,   -2 },   // 0x2D '-'\n  {    29,   1,   1,   2,    0,    0 },   // 0x2E '.'\n  {    30,   5,   5,   6,    0,   -4 },   // 0x2F '/'\n  {    34,   5,   5,   6,    0,   -4 },   // 0x30 '0'\n  {    38,   1,   5,   2,    0,   -4 },   // 0x31 '1'\n  {    39,   5,   5,   6,    0,   -4 },   // 0x32 '2'\n  {    43,   5,   5,   6,    0,   -4 },   // 0x33 '3'\n  {    47,   5,   5,   6,    0,   -4 },   // 0x34 '4'\n  {    51,   5,   5,   6,    0,   -4 },   // 0x35 '5'\n  {    55,   5,   5,   6,    0,   -4 },   // 0x36 '6'\n  {    59,   5,   5,   6,    0,   -4 },   // 0x37 '7'\n  {    63,   5,   5,   6,    0,   -4 },   // 0x38 '8'\n  {    67,   5,   5,   6,    0,   -4 },   // 0x39 '9'\n  {    71,   1,   4,   2,    0,   -3 },   // 0x3A ':'\n  {    72,   1,   4,   2,    0,   -3 },   // 0x3B ';'\n  {    73,   3,   5,   4,    0,   -4 },   // 0x3C '<'\n  {    75,   4,   3,   5,    0,   -3 },   // 0x3D '='\n  {    77,   3,   5,   4,    0,   -4 },   // 0x3E '>'\n  {    79,   5,   5,   6,    0,   -4 },   // 0x3F '?'\n  {    83,   5,   5,   6,    0,   -4 },   // 0x40 '@'\n  {    87,   5,   5,   6,    0,   -4 },   // 0x41 'A'\n  {    91,   5,   5,   6,    0,   -4 },   // 0x42 'B'\n  {    95,   5,   5,   6,    0,   -4 },   // 0x43 'C'\n  {    99,   5,   5,   6,    0,   -4 },   // 0x44 'D'\n  {   103,   5,   5,   6,    0,   -4 },   // 0x45 'E'\n  {   107,   5,   5,   6,    0,   -4 },   // 0x46 'F'\n  {   111,   5,   5,   6,    0,   -4 },   // 0x47 'G'\n  {   115,   5,   5,   6,    0,   -4 },   // 0x48 'H'\n  {   119,   5,   5,   6,    0,   -4 },   // 0x49 'I'\n  {   123,   5,   5,   6,    0,   -4 },   // 0x4A 'J'\n  {   127,   5,   5,   6,    0,   -4 },   // 0x4B 'K'\n  {   131,   5,   5,   6,    0,   -4 },   // 0x4C 'L'\n  {   135,   5,   5,   6,    0,   -4 },   // 0x4D 'M'\n  {   139,   5,   5,   6,    0,   -4 },   // 0x4E 'N'\n  {   143,   5,   5,   6,    0,   -4 },   // 0x4F 'O'\n  {   147,   5,   5,   6,    0,   -4 },   // 0x50 'P'\n  {   151,   5,   5,   6,    0,   -4 },   // 0x51 'Q'\n  {   155,   5,   5,   6,    0,   -4 },   // 0x52 'R'\n  {   159,   5,   5,   6,    0,   -4 },   // 0x53 'S'\n  {   163,   5,   5,   6,    0,   -4 },   // 0x54 'T'\n  {   167,   5,   5,   6,    0,   -4 },   // 0x55 'U'\n  {   171,   5,   5,   6,    0,   -4 },   // 0x56 'V'\n  {   175,   5,   5,   6,    0,   -4 },   // 0x57 'W'\n  {   179,   5,   5,   6,    0,   -4 },   // 0x58 'X'\n  {   183,   5,   5,   6,    0,   -4 },   // 0x59 'Y'\n  {   187,   5,   5,   6,    0,   -4 },   // 0x5A 'Z'\n  {   191,   2,   5,   3,    0,   -4 },   // 0x5B '['\n  {   193,   5,   5,   6,    0,   -4 },   // 0x5C '\\'\n  {   197,   2,   5,   3,    0,   -4 },   // 0x5D ']'\n  {   199,   3,   2,   4,    0,   -4 },   // 0x5E '^'\n  {   200,   5,   1,   6,    0,    1 },   // 0x5F '_'\n  {   201,   1,   1,   2,    0,   -4 },   // 0x60 '`'\n  {   202,   4,   4,   5,    0,   -3 },   // 0x61 'a'\n  {   204,   4,   5,   5,    0,   -4 },   // 0x62 'b'\n  {   207,   4,   4,   5,    0,   -3 },   // 0x63 'c'\n  {   209,   4,   5,   5,    0,   -4 },   // 0x64 'd'\n  {   212,   4,   4,   5,    0,   -3 },   // 0x65 'e'\n  {   214,   3,   5,   4,    0,   -4 },   // 0x66 'f'\n  {   216,   4,   5,   5,    0,   -3 },   // 0x67 'g'\n  {   219,   4,   5,   5,    0,   -4 },   // 0x68 'h'\n  {   222,   1,   4,   2,    0,   -3 },   // 0x69 'i'\n  {   223,   2,   5,   3,    0,   -3 },   // 0x6A 'j'\n  {   225,   4,   5,   5,    0,   -4 },   // 0x6B 'k'\n  {   228,   1,   5,   2,    0,   -4 },   // 0x6C 'l'\n  {   229,   5,   4,   6,    0,   -3 },   // 0x6D 'm'\n  {   232,   4,   4,   5,    0,   -3 },   // 0x6E 'n'\n  {   234,   4,   4,   5,    0,   -3 },   // 0x6F 'o'\n  {   236,   4,   5,   5,    0,   -3 },   // 0x70 'p'\n  {   239,   4,   5,   5,    0,   -3 },   // 0x71 'q'\n  {   242,   4,   4,   5,    0,   -3 },   // 0x72 'r'\n  {   244,   4,   4,   5,    0,   -3 },   // 0x73 's'\n  {   246,   5,   5,   6,    0,   -4 },   // 0x74 't'\n  {   250,   4,   4,   5,    0,   -3 },   // 0x75 'u'\n  {   252,   4,   4,   5,    0,   -3 },   // 0x76 'v'\n  {   254,   5,   4,   6,    0,   -3 },   // 0x77 'w'\n  {   257,   4,   4,   5,    0,   -3 },   // 0x78 'x'\n  {   259,   4,   5,   5,    0,   -3 },   // 0x79 'y'\n  {   262,   4,   4,   5,    0,   -3 },   // 0x7A 'z'\n  {   264,   3,   5,   4,    0,   -4 },   // 0x7B '{'\n  {   266,   1,   5,   2,    0,   -4 },   // 0x7C '|'\n  {   267,   3,   5,   4,    0,   -4 },   // 0x7D '}'\n  {   269,   5,   3,   6,    0,   -3 } }; // 0x7E '~'\n\nconst GFXfont Org_01 PROGMEM = {\n  (uint8_t  *)Org_01Bitmaps,\n  (GFXglyph *)Org_01Glyphs,\n  0x20, 0x7E, 7 };\n\n// Approx. 943 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/Picopixel.h",
    "content": "// Picopixel by Sebastian Weber.  A tiny font\n// with all characters within a 6 pixel height.\n\nconst uint8_t PicopixelBitmaps[] PROGMEM = {\n  0xE8, 0xB4, 0x57, 0xD5, 0xF5, 0x00, 0x4E, 0x3E, 0x80, 0xA5, 0x4A, 0x4A,\n  0x5A, 0x50, 0xC0, 0x6A, 0x40, 0x95, 0x80, 0xAA, 0x80, 0x5D, 0x00, 0x60,\n  0xE0, 0x80, 0x25, 0x48, 0x56, 0xD4, 0x75, 0x40, 0xC5, 0x4E, 0xC5, 0x1C,\n  0x97, 0x92, 0xF3, 0x1C, 0x53, 0x54, 0xE5, 0x48, 0x55, 0x54, 0x55, 0x94,\n  0xA0, 0x46, 0x64, 0xE3, 0x80, 0x98, 0xC5, 0x04, 0x56, 0xC6, 0x57, 0xDA,\n  0xD7, 0x5C, 0x72, 0x46, 0xD6, 0xDC, 0xF3, 0xCE, 0xF3, 0x48, 0x72, 0xD4,\n  0xB7, 0xDA, 0xF8, 0x24, 0xD4, 0xBB, 0x5A, 0x92, 0x4E, 0x8E, 0xEB, 0x58,\n  0x80, 0x9D, 0xB9, 0x90, 0x56, 0xD4, 0xD7, 0x48, 0x56, 0xD4, 0x40, 0xD7,\n  0x5A, 0x71, 0x1C, 0xE9, 0x24, 0xB6, 0xD4, 0xB6, 0xA4, 0x8C, 0x6B, 0x55,\n  0x00, 0xB5, 0x5A, 0xB5, 0x24, 0xE5, 0x4E, 0xEA, 0xC0, 0x91, 0x12, 0xD5,\n  0xC0, 0x54, 0xF0, 0x90, 0xC7, 0xF0, 0x93, 0x5E, 0x71, 0x80, 0x25, 0xDE,\n  0x5E, 0x30, 0x6E, 0x80, 0x77, 0x9C, 0x93, 0x5A, 0xB8, 0x45, 0x60, 0x92,\n  0xEA, 0xAA, 0x40, 0xD5, 0x6A, 0xD6, 0x80, 0x55, 0x00, 0xD7, 0x40, 0x75,\n  0x90, 0xE8, 0x71, 0xE0, 0xBA, 0x40, 0xB5, 0x80, 0xB5, 0x00, 0x8D, 0x54,\n  0xAA, 0x80, 0xAC, 0xE0, 0xE5, 0x70, 0x6A, 0x26, 0xFC, 0xC8, 0xAC, 0x5A };\n\nconst GFXglyph PicopixelGlyphs[] PROGMEM = {\n  {     0,   0,   0,   2,    0,    1 },   // 0x20 ' '\n  {     0,   1,   5,   2,    0,   -4 },   // 0x21 '!'\n  {     1,   3,   2,   4,    0,   -4 },   // 0x22 '\"'\n  {     2,   5,   5,   6,    0,   -4 },   // 0x23 '#'\n  {     6,   3,   6,   4,    0,   -4 },   // 0x24 '$'\n  {     9,   3,   5,   4,    0,   -4 },   // 0x25 '%'\n  {    11,   4,   5,   5,    0,   -4 },   // 0x26 '&'\n  {    14,   1,   2,   2,    0,   -4 },   // 0x27 '''\n  {    15,   2,   5,   3,    0,   -4 },   // 0x28 '('\n  {    17,   2,   5,   3,    0,   -4 },   // 0x29 ')'\n  {    19,   3,   3,   4,    0,   -3 },   // 0x2A '*'\n  {    21,   3,   3,   4,    0,   -3 },   // 0x2B '+'\n  {    23,   2,   2,   3,    0,    0 },   // 0x2C ','\n  {    24,   3,   1,   4,    0,   -2 },   // 0x2D '-'\n  {    25,   1,   1,   2,    0,    0 },   // 0x2E '.'\n  {    26,   3,   5,   4,    0,   -4 },   // 0x2F '/'\n  {    28,   3,   5,   4,    0,   -4 },   // 0x30 '0'\n  {    30,   2,   5,   3,    0,   -4 },   // 0x31 '1'\n  {    32,   3,   5,   4,    0,   -4 },   // 0x32 '2'\n  {    34,   3,   5,   4,    0,   -4 },   // 0x33 '3'\n  {    36,   3,   5,   4,    0,   -4 },   // 0x34 '4'\n  {    38,   3,   5,   4,    0,   -4 },   // 0x35 '5'\n  {    40,   3,   5,   4,    0,   -4 },   // 0x36 '6'\n  {    42,   3,   5,   4,    0,   -4 },   // 0x37 '7'\n  {    44,   3,   5,   4,    0,   -4 },   // 0x38 '8'\n  {    46,   3,   5,   4,    0,   -4 },   // 0x39 '9'\n  {    48,   1,   3,   2,    0,   -3 },   // 0x3A ':'\n  {    49,   2,   4,   3,    0,   -3 },   // 0x3B ';'\n  {    50,   2,   3,   3,    0,   -3 },   // 0x3C '<'\n  {    51,   3,   3,   4,    0,   -3 },   // 0x3D '='\n  {    53,   2,   3,   3,    0,   -3 },   // 0x3E '>'\n  {    54,   3,   5,   4,    0,   -4 },   // 0x3F '?'\n  {    56,   3,   5,   4,    0,   -4 },   // 0x40 '@'\n  {    58,   3,   5,   4,    0,   -4 },   // 0x41 'A'\n  {    60,   3,   5,   4,    0,   -4 },   // 0x42 'B'\n  {    62,   3,   5,   4,    0,   -4 },   // 0x43 'C'\n  {    64,   3,   5,   4,    0,   -4 },   // 0x44 'D'\n  {    66,   3,   5,   4,    0,   -4 },   // 0x45 'E'\n  {    68,   3,   5,   4,    0,   -4 },   // 0x46 'F'\n  {    70,   3,   5,   4,    0,   -4 },   // 0x47 'G'\n  {    72,   3,   5,   4,    0,   -4 },   // 0x48 'H'\n  {    74,   1,   5,   2,    0,   -4 },   // 0x49 'I'\n  {    75,   3,   5,   4,    0,   -4 },   // 0x4A 'J'\n  {    77,   3,   5,   4,    0,   -4 },   // 0x4B 'K'\n  {    79,   3,   5,   4,    0,   -4 },   // 0x4C 'L'\n  {    81,   5,   5,   6,    0,   -4 },   // 0x4D 'M'\n  {    85,   4,   5,   5,    0,   -4 },   // 0x4E 'N'\n  {    88,   3,   5,   4,    0,   -4 },   // 0x4F 'O'\n  {    90,   3,   5,   4,    0,   -4 },   // 0x50 'P'\n  {    92,   3,   6,   4,    0,   -4 },   // 0x51 'Q'\n  {    95,   3,   5,   4,    0,   -4 },   // 0x52 'R'\n  {    97,   3,   5,   4,    0,   -4 },   // 0x53 'S'\n  {    99,   3,   5,   4,    0,   -4 },   // 0x54 'T'\n  {   101,   3,   5,   4,    0,   -4 },   // 0x55 'U'\n  {   103,   3,   5,   4,    0,   -4 },   // 0x56 'V'\n  {   105,   5,   5,   6,    0,   -4 },   // 0x57 'W'\n  {   109,   3,   5,   4,    0,   -4 },   // 0x58 'X'\n  {   111,   3,   5,   4,    0,   -4 },   // 0x59 'Y'\n  {   113,   3,   5,   4,    0,   -4 },   // 0x5A 'Z'\n  {   115,   2,   5,   3,    0,   -4 },   // 0x5B '['\n  {   117,   3,   5,   4,    0,   -4 },   // 0x5C '\\'\n  {   119,   2,   5,   3,    0,   -4 },   // 0x5D ']'\n  {   121,   3,   2,   4,    0,   -4 },   // 0x5E '^'\n  {   122,   4,   1,   4,    0,    1 },   // 0x5F '_'\n  {   123,   2,   2,   3,    0,   -4 },   // 0x60 '`'\n  {   124,   3,   4,   4,    0,   -3 },   // 0x61 'a'\n  {   126,   3,   5,   4,    0,   -4 },   // 0x62 'b'\n  {   128,   3,   3,   4,    0,   -2 },   // 0x63 'c'\n  {   130,   3,   5,   4,    0,   -4 },   // 0x64 'd'\n  {   132,   3,   4,   4,    0,   -3 },   // 0x65 'e'\n  {   134,   2,   5,   3,    0,   -4 },   // 0x66 'f'\n  {   136,   3,   5,   4,    0,   -3 },   // 0x67 'g'\n  {   138,   3,   5,   4,    0,   -4 },   // 0x68 'h'\n  {   140,   1,   5,   2,    0,   -4 },   // 0x69 'i'\n  {   141,   2,   6,   3,    0,   -4 },   // 0x6A 'j'\n  {   143,   3,   5,   4,    0,   -4 },   // 0x6B 'k'\n  {   145,   2,   5,   3,    0,   -4 },   // 0x6C 'l'\n  {   147,   5,   3,   6,    0,   -2 },   // 0x6D 'm'\n  {   149,   3,   3,   4,    0,   -2 },   // 0x6E 'n'\n  {   151,   3,   3,   4,    0,   -2 },   // 0x6F 'o'\n  {   153,   3,   4,   4,    0,   -2 },   // 0x70 'p'\n  {   155,   3,   4,   4,    0,   -2 },   // 0x71 'q'\n  {   157,   2,   3,   3,    0,   -2 },   // 0x72 'r'\n  {   158,   3,   4,   4,    0,   -3 },   // 0x73 's'\n  {   160,   2,   5,   3,    0,   -4 },   // 0x74 't'\n  {   162,   3,   3,   4,    0,   -2 },   // 0x75 'u'\n  {   164,   3,   3,   4,    0,   -2 },   // 0x76 'v'\n  {   166,   5,   3,   6,    0,   -2 },   // 0x77 'w'\n  {   168,   3,   3,   4,    0,   -2 },   // 0x78 'x'\n  {   170,   3,   4,   4,    0,   -2 },   // 0x79 'y'\n  {   172,   3,   4,   4,    0,   -3 },   // 0x7A 'z'\n  {   174,   3,   5,   4,    0,   -4 },   // 0x7B '{'\n  {   176,   1,   6,   2,    0,   -4 },   // 0x7C '|'\n  {   177,   3,   5,   4,    0,   -4 },   // 0x7D '}'\n  {   179,   4,   2,   5,    0,   -3 } }; // 0x7E '~'\n\nconst GFXfont Picopixel PROGMEM = {\n  (uint8_t  *)PicopixelBitmaps,\n  (GFXglyph *)PicopixelGlyphs,\n  0x20, 0x7E, 7 };\n\n// Approx. 852 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/Tiny3x3a2pt7b",
    "content": "/**\n** The FontStruction “Tiny3x3a”\n** (https://fontstruct.com/fontstructions/show/670512) by “Michaelangel007” is\n** licensed under a Creative Commons Attribution Non-commercial Share Alike license\n** (http://creativecommons.org/licenses/by-nc-sa/3.0/).\n** “Tiny3x3a” was originally cloned (copied) from the FontStruction\n** “CHECKER” (https://fontstruct.com/fontstructions/show/2391) by Wolf grant\n** Grant, which is licensed under a Creative Commons Attribution Non-commercial\n** Share Alike license (http://creativecommons.org/licenses/by-nc-sa/3.0/).\n* \n* Converted by eadmaster with fontconvert\n**/\n\nconst uint8_t Tiny3x3a2pt7bBitmaps[] PROGMEM = {\n  0xC0, 0xB4, 0xBF, 0x80, 0x6B, 0x00, 0xDD, 0x80, 0x59, 0x80, 0x80, 0x64,\n  0x98, 0xF0, 0x5D, 0x00, 0xC0, 0xE0, 0x80, 0x2A, 0x00, 0x55, 0x00, 0x94,\n  0xC9, 0x80, 0xEF, 0x80, 0xBC, 0x80, 0x6B, 0x00, 0x9F, 0x80, 0xE4, 0x80,\n  0x7F, 0x00, 0xFC, 0x80, 0xA0, 0x58, 0x64, 0xE3, 0x80, 0x98, 0xD8, 0xD8,\n  0x80, 0x5E, 0x80, 0xDF, 0x80, 0x71, 0x80, 0xD7, 0x00, 0xFB, 0x80, 0xFA,\n  0x00, 0xD7, 0x80, 0xBE, 0x80, 0xE0, 0x27, 0x00, 0xBA, 0x80, 0x93, 0x80,\n  0xFE, 0x80, 0xF6, 0x80, 0xF7, 0x80, 0xFE, 0x00, 0xF7, 0x00, 0xDE, 0x80,\n  0x6B, 0x00, 0xE9, 0x00, 0xB7, 0x80, 0xB5, 0x00, 0xBF, 0x80, 0xAA, 0x80,\n  0xA9, 0x00, 0xEB, 0x80, 0xEC, 0x88, 0x80, 0xDC, 0x54, 0xE0, 0x90, 0x70,\n  0xBC, 0xF0, 0x7C, 0xB0, 0x68, 0xFC, 0xBC, 0xC0, 0x58, 0x9A, 0x80, 0xA4,\n  0xDC, 0xD4, 0xF0, 0xF8, 0xF4, 0xE0, 0x60, 0x59, 0x80, 0xBC, 0xA8, 0xEC,\n  0xF0, 0xAC, 0x80, 0x90, 0x79, 0x80, 0xF0, 0xCF, 0x00, 0x78 };\n\nconst GFXglyph Tiny3x3a2pt7bGlyphs[] PROGMEM = {\n  {     0,   0,   0,   4,    0,    1 },   // 0x20 ' '\n  {     0,   1,   2,   3,    1,   -2 },   // 0x21 '!'\n  {     1,   3,   2,   4,    0,   -2 },   // 0x22 '\"'\n  {     2,   3,   3,   4,    0,   -2 },   // 0x23 '#'\n  {     4,   3,   3,   4,    0,   -2 },   // 0x24 '$'\n  {     6,   3,   3,   4,    0,   -2 },   // 0x25 '%'\n  {     8,   3,   3,   4,    0,   -2 },   // 0x26 '&'\n  {    10,   1,   1,   3,    1,   -2 },   // 0x27 '''\n  {    11,   2,   3,   3,    0,   -2 },   // 0x28 '('\n  {    12,   2,   3,   4,    1,   -2 },   // 0x29 ')'\n  {    13,   2,   2,   4,    1,   -2 },   // 0x2A '*'\n  {    14,   3,   3,   4,    0,   -2 },   // 0x2B '+'\n  {    16,   1,   2,   2,    0,    0 },   // 0x2C ','\n  {    17,   3,   1,   4,    0,   -1 },   // 0x2D '-'\n  {    18,   1,   1,   2,    0,    0 },   // 0x2E '.'\n  {    19,   3,   3,   4,    0,   -2 },   // 0x2F '/'\n  {    21,   3,   3,   4,    0,   -2 },   // 0x30 '0'\n  {    23,   2,   3,   3,    0,   -2 },   // 0x31 '1'\n  {    24,   3,   3,   4,    0,   -2 },   // 0x32 '2'\n  {    26,   3,   3,   4,    0,   -2 },   // 0x33 '3'\n  {    28,   3,   3,   4,    0,   -2 },   // 0x34 '4'\n  {    30,   3,   3,   4,    0,   -2 },   // 0x35 '5'\n  {    32,   3,   3,   4,    0,   -2 },   // 0x36 '6'\n  {    34,   3,   3,   4,    0,   -2 },   // 0x37 '7'\n  {    36,   3,   3,   4,    0,   -2 },   // 0x38 '8'\n  {    38,   3,   3,   4,    0,   -2 },   // 0x39 '9'\n  {    40,   1,   3,   3,    1,   -2 },   // 0x3A ':'\n  {    41,   2,   3,   3,    0,   -1 },   // 0x3B ';'\n  {    42,   2,   3,   3,    0,   -2 },   // 0x3C '<'\n  {    43,   3,   3,   4,    0,   -2 },   // 0x3D '='\n  {    45,   2,   3,   4,    1,   -2 },   // 0x3E '>'\n  {    46,   2,   3,   4,    1,   -2 },   // 0x3F '?'\n  {    47,   3,   3,   4,    0,   -2 },   // 0x40 '@'\n  {    49,   3,   3,   4,    0,   -2 },   // 0x41 'A'\n  {    51,   3,   3,   4,    0,   -2 },   // 0x42 'B'\n  {    53,   3,   3,   4,    0,   -2 },   // 0x43 'C'\n  {    55,   3,   3,   4,    0,   -2 },   // 0x44 'D'\n  {    57,   3,   3,   4,    0,   -2 },   // 0x45 'E'\n  {    59,   3,   3,   4,    0,   -2 },   // 0x46 'F'\n  {    61,   3,   3,   4,    0,   -2 },   // 0x47 'G'\n  {    63,   3,   3,   4,    0,   -2 },   // 0x48 'H'\n  {    65,   1,   3,   3,    1,   -2 },   // 0x49 'I'\n  {    66,   3,   3,   4,    0,   -2 },   // 0x4A 'J'\n  {    68,   3,   3,   4,    0,   -2 },   // 0x4B 'K'\n  {    70,   3,   3,   4,    0,   -2 },   // 0x4C 'L'\n  {    72,   3,   3,   4,    0,   -2 },   // 0x4D 'M'\n  {    74,   3,   3,   4,    0,   -2 },   // 0x4E 'N'\n  {    76,   3,   3,   4,    0,   -2 },   // 0x4F 'O'\n  {    78,   3,   3,   4,    0,   -2 },   // 0x50 'P'\n  {    80,   3,   3,   4,    0,   -2 },   // 0x51 'Q'\n  {    82,   3,   3,   4,    0,   -2 },   // 0x52 'R'\n  {    84,   3,   3,   4,    0,   -2 },   // 0x53 'S'\n  {    86,   3,   3,   4,    0,   -2 },   // 0x54 'T'\n  {    88,   3,   3,   4,    0,   -2 },   // 0x55 'U'\n  {    90,   3,   3,   4,    0,   -2 },   // 0x56 'V'\n  {    92,   3,   3,   4,    0,   -2 },   // 0x57 'W'\n  {    94,   3,   3,   4,    0,   -2 },   // 0x58 'X'\n  {    96,   3,   3,   4,    0,   -2 },   // 0x59 'Y'\n  {    98,   3,   3,   4,    0,   -2 },   // 0x5A 'Z'\n  {   100,   2,   3,   3,    0,   -2 },   // 0x5B '['\n  {   101,   3,   3,   4,    0,   -2 },   // 0x5C '\\'\n  {   103,   2,   3,   4,    1,   -2 },   // 0x5D ']'\n  {   104,   3,   2,   4,    0,   -2 },   // 0x5E '^'\n  {   105,   3,   1,   4,    0,    0 },   // 0x5F '_'\n  {   106,   2,   2,   3,    0,   -2 },   // 0x60 '`'\n  {   107,   2,   2,   3,    0,   -1 },   // 0x61 'a'\n  {   108,   2,   3,   3,    0,   -2 },   // 0x62 'b'\n  {   109,   2,   2,   3,    0,   -1 },   // 0x63 'c'\n  {   110,   2,   3,   3,    0,   -2 },   // 0x64 'd'\n  {   111,   2,   2,   3,    0,   -1 },   // 0x65 'e'\n  {   112,   2,   3,   3,    0,   -2 },   // 0x66 'f'\n  {   113,   2,   3,   3,    0,   -1 },   // 0x67 'g'\n  {   114,   2,   3,   3,    0,   -2 },   // 0x68 'h'\n  {   115,   1,   2,   2,    0,   -1 },   // 0x69 'i'\n  {   116,   2,   3,   3,    0,   -1 },   // 0x6A 'j'\n  {   117,   3,   3,   4,    0,   -2 },   // 0x6B 'k'\n  {   119,   2,   3,   3,    0,   -2 },   // 0x6C 'l'\n  {   120,   3,   2,   4,    0,   -1 },   // 0x6D 'm'\n  {   121,   3,   2,   4,    0,   -1 },   // 0x6E 'n'\n  {   122,   2,   2,   3,    0,   -1 },   // 0x6F 'o'\n  {   123,   2,   3,   3,    0,   -1 },   // 0x70 'p'\n  {   124,   2,   3,   3,    0,   -1 },   // 0x71 'q'\n  {   125,   2,   2,   3,    0,   -1 },   // 0x72 'r'\n  {   126,   2,   2,   3,    0,   -1 },   // 0x73 's'\n  {   127,   3,   3,   4,    0,   -2 },   // 0x74 't'\n  {   129,   3,   2,   4,    0,   -1 },   // 0x75 'u'\n  {   130,   3,   2,   4,    0,   -1 },   // 0x76 'v'\n  {   131,   3,   2,   4,    0,   -1 },   // 0x77 'w'\n  {   132,   2,   2,   3,    0,   -1 },   // 0x78 'x'\n  {   133,   3,   3,   4,    0,   -1 },   // 0x79 'y'\n  {   135,   2,   2,   3,    0,   -1 },   // 0x7A 'z'\n  {   136,   3,   3,   4,    0,   -2 },   // 0x7B '{'\n  {   138,   1,   4,   3,    1,   -2 },   // 0x7C '|'\n  {   139,   3,   3,   4,    0,   -2 },   // 0x7D '}'\n  {   141,   3,   2,   4,    0,   -2 } }; // 0x7E '~'\n\nconst GFXfont Tiny3x3a2pt7b PROGMEM = {\n  (uint8_t  *)Tiny3x3a2pt7bBitmaps,\n  (GFXglyph *)Tiny3x3a2pt7bGlyphs,\n  0x20, 0x7E, 4 };\n\n// Approx. 814 bytes\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/Fonts/TomThumb.h",
    "content": "/**\n** The original 3x5 font is licensed under the 3-clause BSD license:\n**\n** Copyright 1999 Brian J. Swetland\n** Copyright 1999 Vassilii Khachaturov\n** Portions (of vt100.c/vt100.h) copyright Dan Marks\n** \n** All rights reserved.\n**\n** Redistribution and use in source and binary forms, with or without\n** modification, are permitted provided that the following conditions\n** are met:\n** 1. Redistributions of source code must retain the above copyright\n**    notice, this list of conditions, and the following disclaimer.\n** 2. Redistributions in binary form must reproduce the above copyright\n**    notice, this list of conditions, and the following disclaimer in the\n**    documentation and/or other materials provided with the distribution.\n** 3. The name of the authors may not be used to endorse or promote products\n**    derived from this software without specific prior written permission.\n**\n** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR\n** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES\n** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.\n** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,\n** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT\n** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\n** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n** \n** Modifications to Tom Thumb for improved readability are from Robey Pointer, \n** see:\n** http://robey.lag.net/2010/01/23/tiny-monospace-font.html\n** \n** The original author does not have any objection to relicensing of Robey \n** Pointer's modifications (in this file) in a more permissive license.  See \n** the discussion at the above blog, and also here:\n** http://opengameart.org/forumtopic/how-to-submit-art-using-the-3-clause-bsd-license\n**\n** Feb 21, 2016: Conversion from Linux BDF --> Adafruit GFX font,\n** with the help of this Python script:\n** https://gist.github.com/skelliam/322d421f028545f16f6d\n** William Skellenger (williamj@skellenger.net)\n** Twitter: @skelliam\n** \n*/\n\n#define TOMTHUMB_USE_EXTENDED 0\n\nconst uint8_t TomThumbBitmaps[] PROGMEM = {\n   0x00,                                /* 0x20 space */\n   0x80, 0x80, 0x80, 0x00, 0x80,        /* 0x21 exclam */\n   0xA0, 0xA0,                          /* 0x22 quotedbl */\n   0xA0, 0xE0, 0xA0, 0xE0, 0xA0,        /* 0x23 numbersign */\n   0x60, 0xC0, 0x60, 0xC0, 0x40,        /* 0x24 dollar */\n   0x80, 0x20, 0x40, 0x80, 0x20,        /* 0x25 percent */\n   0xC0, 0xC0, 0xE0, 0xA0, 0x60,        /* 0x26 ampersand */\n   0x80, 0x80,                          /* 0x27 quotesingle */\n   0x40, 0x80, 0x80, 0x80, 0x40,        /* 0x28 parenleft */\n   0x80, 0x40, 0x40, 0x40, 0x80,        /* 0x29 parenright */\n   0xA0, 0x40, 0xA0,                    /* 0x2A asterisk */\n   0x40, 0xE0, 0x40,                    /* 0x2B plus */\n   0x40, 0x80,                          /* 0x2C comma */\n   0xE0,                                /* 0x2D hyphen */\n   0x80,                                /* 0x2E period */\n   0x20, 0x20, 0x40, 0x80, 0x80,        /* 0x2F slash */\n   0x60, 0xA0, 0xA0, 0xA0, 0xC0,        /* 0x30 zero */\n   0x40, 0xC0, 0x40, 0x40, 0x40,        /* 0x31 one */\n   0xC0, 0x20, 0x40, 0x80, 0xE0,        /* 0x32 two */\n   0xC0, 0x20, 0x40, 0x20, 0xC0,        /* 0x33 three */\n   0xA0, 0xA0, 0xE0, 0x20, 0x20,        /* 0x34 four */\n   0xE0, 0x80, 0xC0, 0x20, 0xC0,        /* 0x35 five */\n   0x60, 0x80, 0xE0, 0xA0, 0xE0,        /* 0x36 six */\n   0xE0, 0x20, 0x40, 0x80, 0x80,        /* 0x37 seven */\n   0xE0, 0xA0, 0xE0, 0xA0, 0xE0,        /* 0x38 eight */\n   0xE0, 0xA0, 0xE0, 0x20, 0xC0,        /* 0x39 nine */\n   0x80, 0x00, 0x80,                    /* 0x3A colon */\n   0x40, 0x00, 0x40, 0x80,              /* 0x3B semicolon */\n   0x20, 0x40, 0x80, 0x40, 0x20,        /* 0x3C less */\n   0xE0, 0x00, 0xE0,                    /* 0x3D equal */\n   0x80, 0x40, 0x20, 0x40, 0x80,        /* 0x3E greater */\n   0xE0, 0x20, 0x40, 0x00, 0x40,        /* 0x3F question */\n   0x40, 0xA0, 0xE0, 0x80, 0x60,        /* 0x40 at */\n   0x40, 0xA0, 0xE0, 0xA0, 0xA0,        /* 0x41 A */\n   0xC0, 0xA0, 0xC0, 0xA0, 0xC0,        /* 0x42 B */\n   0x60, 0x80, 0x80, 0x80, 0x60,        /* 0x43 C */\n   0xC0, 0xA0, 0xA0, 0xA0, 0xC0,        /* 0x44 D */\n   0xE0, 0x80, 0xE0, 0x80, 0xE0,        /* 0x45 E */\n   0xE0, 0x80, 0xE0, 0x80, 0x80,        /* 0x46 F */\n   0x60, 0x80, 0xE0, 0xA0, 0x60,        /* 0x47 G */\n   0xA0, 0xA0, 0xE0, 0xA0, 0xA0,        /* 0x48 H */\n   0xE0, 0x40, 0x40, 0x40, 0xE0,        /* 0x49 I */\n   0x20, 0x20, 0x20, 0xA0, 0x40,        /* 0x4A J */\n   0xA0, 0xA0, 0xC0, 0xA0, 0xA0,        /* 0x4B K */\n   0x80, 0x80, 0x80, 0x80, 0xE0,        /* 0x4C L */\n   0xA0, 0xE0, 0xE0, 0xA0, 0xA0,        /* 0x4D M */\n   0xA0, 0xE0, 0xE0, 0xE0, 0xA0,        /* 0x4E N */\n   0x40, 0xA0, 0xA0, 0xA0, 0x40,        /* 0x4F O */\n   0xC0, 0xA0, 0xC0, 0x80, 0x80,        /* 0x50 P */\n   0x40, 0xA0, 0xA0, 0xE0, 0x60,        /* 0x51 Q */\n   0xC0, 0xA0, 0xE0, 0xC0, 0xA0,        /* 0x52 R */\n   0x60, 0x80, 0x40, 0x20, 0xC0,        /* 0x53 S */\n   0xE0, 0x40, 0x40, 0x40, 0x40,        /* 0x54 T */\n   0xA0, 0xA0, 0xA0, 0xA0, 0x60,        /* 0x55 U */\n   0xA0, 0xA0, 0xA0, 0x40, 0x40,        /* 0x56 V */\n   0xA0, 0xA0, 0xE0, 0xE0, 0xA0,        /* 0x57 W */\n   0xA0, 0xA0, 0x40, 0xA0, 0xA0,        /* 0x58 X */\n   0xA0, 0xA0, 0x40, 0x40, 0x40,        /* 0x59 Y */\n   0xE0, 0x20, 0x40, 0x80, 0xE0,        /* 0x5A Z */\n   0xE0, 0x80, 0x80, 0x80, 0xE0,        /* 0x5B bracketleft */\n   0x80, 0x40, 0x20,                    /* 0x5C backslash */\n   0xE0, 0x20, 0x20, 0x20, 0xE0,        /* 0x5D bracketright */\n   0x40, 0xA0,                          /* 0x5E asciicircum */\n   0xE0,                                /* 0x5F underscore */\n   0x80, 0x40,                          /* 0x60 grave */\n   0xC0, 0x60, 0xA0, 0xE0,              /* 0x61 a */\n   0x80, 0xC0, 0xA0, 0xA0, 0xC0,        /* 0x62 b */\n   0x60, 0x80, 0x80, 0x60,              /* 0x63 c */\n   0x20, 0x60, 0xA0, 0xA0, 0x60,        /* 0x64 d */\n   0x60, 0xA0, 0xC0, 0x60,              /* 0x65 e */\n   0x20, 0x40, 0xE0, 0x40, 0x40,        /* 0x66 f */\n   0x60, 0xA0, 0xE0, 0x20, 0x40,        /* 0x67 g */\n   0x80, 0xC0, 0xA0, 0xA0, 0xA0,        /* 0x68 h */\n   0x80, 0x00, 0x80, 0x80, 0x80,        /* 0x69 i */\n   0x20, 0x00, 0x20, 0x20, 0xA0, 0x40,  /* 0x6A j */\n   0x80, 0xA0, 0xC0, 0xC0, 0xA0,        /* 0x6B k */\n   0xC0, 0x40, 0x40, 0x40, 0xE0,        /* 0x6C l */\n   0xE0, 0xE0, 0xE0, 0xA0,              /* 0x6D m */\n   0xC0, 0xA0, 0xA0, 0xA0,              /* 0x6E n */\n   0x40, 0xA0, 0xA0, 0x40,              /* 0x6F o */\n   0xC0, 0xA0, 0xA0, 0xC0, 0x80,        /* 0x70 p */\n   0x60, 0xA0, 0xA0, 0x60, 0x20,        /* 0x71 q */\n   0x60, 0x80, 0x80, 0x80,              /* 0x72 r */\n   0x60, 0xC0, 0x60, 0xC0,              /* 0x73 s */\n   0x40, 0xE0, 0x40, 0x40, 0x60,        /* 0x74 t */\n   0xA0, 0xA0, 0xA0, 0x60,              /* 0x75 u */\n   0xA0, 0xA0, 0xE0, 0x40,              /* 0x76 v */\n   0xA0, 0xE0, 0xE0, 0xE0,              /* 0x77 w */\n   0xA0, 0x40, 0x40, 0xA0,              /* 0x78 x */\n   0xA0, 0xA0, 0x60, 0x20, 0x40,        /* 0x79 y */\n   0xE0, 0x60, 0xC0, 0xE0,              /* 0x7A z */\n   0x60, 0x40, 0x80, 0x40, 0x60,        /* 0x7B braceleft */\n   0x80, 0x80, 0x00, 0x80, 0x80,        /* 0x7C bar */\n   0xC0, 0x40, 0x20, 0x40, 0xC0,        /* 0x7D braceright */\n   0x60, 0xC0,                          /* 0x7E asciitilde */\n#if (TOMTHUMB_USE_EXTENDED)\n   0x80, 0x00, 0x80, 0x80, 0x80,        /* 0xA1 exclamdown */\n   0x40, 0xE0, 0x80, 0xE0, 0x40,        /* 0xA2 cent */\n   0x60, 0x40, 0xE0, 0x40, 0xE0,        /* 0xA3 sterling */\n   0xA0, 0x40, 0xE0, 0x40, 0xA0,        /* 0xA4 currency */\n   0xA0, 0xA0, 0x40, 0xE0, 0x40,        /* 0xA5 yen */\n   0x80, 0x80, 0x00, 0x80, 0x80,        /* 0xA6 brokenbar */\n   0x60, 0x40, 0xA0, 0x40, 0xC0,        /* 0xA7 section */\n   0xA0,                                /* 0xA8 dieresis */\n   0x60, 0x80, 0x60,                    /* 0xA9 copyright */\n   0x60, 0xA0, 0xE0, 0x00, 0xE0,        /* 0xAA ordfeminine */\n   0x40, 0x80, 0x40,                    /* 0xAB guillemotleft */\n   0xE0, 0x20,                          /* 0xAC logicalnot */\n   0xC0,                                /* 0xAD softhyphen */\n   0xC0, 0xC0, 0xA0,                    /* 0xAE registered */\n   0xE0,                                /* 0xAF macron */\n   0x40, 0xA0, 0x40,                    /* 0xB0 degree */\n   0x40, 0xE0, 0x40, 0x00, 0xE0,        /* 0xB1 plusminus */\n   0xC0, 0x40, 0x60,                    /* 0xB2 twosuperior */\n   0xE0, 0x60, 0xE0,                    /* 0xB3 threesuperior */\n   0x40, 0x80,                          /* 0xB4 acute */\n   0xA0, 0xA0, 0xA0, 0xC0, 0x80,        /* 0xB5 mu */\n   0x60, 0xA0, 0x60, 0x60, 0x60,        /* 0xB6 paragraph */\n   0xE0, 0xE0, 0xE0,                    /* 0xB7 periodcentered */\n   0x40, 0x20, 0xC0,                    /* 0xB8 cedilla */\n   0x80, 0x80, 0x80,                    /* 0xB9 onesuperior */\n   0x40, 0xA0, 0x40, 0x00, 0xE0,        /* 0xBA ordmasculine */\n   0x80, 0x40, 0x80,                    /* 0xBB guillemotright */\n   0x80, 0x80, 0x00, 0x60, 0x20,        /* 0xBC onequarter */\n   0x80, 0x80, 0x00, 0xC0, 0x60,        /* 0xBD onehalf */\n   0xC0, 0xC0, 0x00, 0x60, 0x20,        /* 0xBE threequarters */\n   0x40, 0x00, 0x40, 0x80, 0xE0,        /* 0xBF questiondown */\n   0x40, 0x20, 0x40, 0xE0, 0xA0,        /* 0xC0 Agrave */\n   0x40, 0x80, 0x40, 0xE0, 0xA0,        /* 0xC1 Aacute */\n   0xE0, 0x00, 0x40, 0xE0, 0xA0,        /* 0xC2 Acircumflex */\n   0x60, 0xC0, 0x40, 0xE0, 0xA0,        /* 0xC3 Atilde */\n   0xA0, 0x40, 0xA0, 0xE0, 0xA0,        /* 0xC4 Adieresis */\n   0xC0, 0xC0, 0xA0, 0xE0, 0xA0,        /* 0xC5 Aring */\n   0x60, 0xC0, 0xE0, 0xC0, 0xE0,        /* 0xC6 AE */\n   0x60, 0x80, 0x80, 0x60, 0x20, 0x40,  /* 0xC7 Ccedilla */\n   0x40, 0x20, 0xE0, 0xC0, 0xE0,        /* 0xC8 Egrave */\n   0x40, 0x80, 0xE0, 0xC0, 0xE0,        /* 0xC9 Eacute */\n   0xE0, 0x00, 0xE0, 0xC0, 0xE0,        /* 0xCA Ecircumflex */\n   0xA0, 0x00, 0xE0, 0xC0, 0xE0,        /* 0xCB Edieresis */\n   0x40, 0x20, 0xE0, 0x40, 0xE0,        /* 0xCC Igrave */\n   0x40, 0x80, 0xE0, 0x40, 0xE0,        /* 0xCD Iacute */\n   0xE0, 0x00, 0xE0, 0x40, 0xE0,        /* 0xCE Icircumflex */\n   0xA0, 0x00, 0xE0, 0x40, 0xE0,        /* 0xCF Idieresis */\n   0xC0, 0xA0, 0xE0, 0xA0, 0xC0,        /* 0xD0 Eth */\n   0xC0, 0x60, 0xA0, 0xE0, 0xA0,        /* 0xD1 Ntilde */\n   0x40, 0x20, 0xE0, 0xA0, 0xE0,        /* 0xD2 Ograve */\n   0x40, 0x80, 0xE0, 0xA0, 0xE0,        /* 0xD3 Oacute */\n   0xE0, 0x00, 0xE0, 0xA0, 0xE0,        /* 0xD4 Ocircumflex */\n   0xC0, 0x60, 0xE0, 0xA0, 0xE0,        /* 0xD5 Otilde */\n   0xA0, 0x00, 0xE0, 0xA0, 0xE0,        /* 0xD6 Odieresis */\n   0xA0, 0x40, 0xA0,                    /* 0xD7 multiply */\n   0x60, 0xA0, 0xE0, 0xA0, 0xC0,        /* 0xD8 Oslash */\n   0x80, 0x40, 0xA0, 0xA0, 0xE0,        /* 0xD9 Ugrave */\n   0x20, 0x40, 0xA0, 0xA0, 0xE0,        /* 0xDA Uacute */\n   0xE0, 0x00, 0xA0, 0xA0, 0xE0,        /* 0xDB Ucircumflex */\n   0xA0, 0x00, 0xA0, 0xA0, 0xE0,        /* 0xDC Udieresis */\n   0x20, 0x40, 0xA0, 0xE0, 0x40,        /* 0xDD Yacute */\n   0x80, 0xE0, 0xA0, 0xE0, 0x80,        /* 0xDE Thorn */\n   0x60, 0xA0, 0xC0, 0xA0, 0xC0, 0x80,  /* 0xDF germandbls */\n   0x40, 0x20, 0x60, 0xA0, 0xE0,        /* 0xE0 agrave */\n   0x40, 0x80, 0x60, 0xA0, 0xE0,        /* 0xE1 aacute */\n   0xE0, 0x00, 0x60, 0xA0, 0xE0,        /* 0xE2 acircumflex */\n   0x60, 0xC0, 0x60, 0xA0, 0xE0,        /* 0xE3 atilde */\n   0xA0, 0x00, 0x60, 0xA0, 0xE0,        /* 0xE4 adieresis */\n   0x60, 0x60, 0x60, 0xA0, 0xE0,        /* 0xE5 aring */\n   0x60, 0xE0, 0xE0, 0xC0,              /* 0xE6 ae */\n   0x60, 0x80, 0x60, 0x20, 0x40,        /* 0xE7 ccedilla */\n   0x40, 0x20, 0x60, 0xE0, 0x60,        /* 0xE8 egrave */\n   0x40, 0x80, 0x60, 0xE0, 0x60,        /* 0xE9 eacute */\n   0xE0, 0x00, 0x60, 0xE0, 0x60,        /* 0xEA ecircumflex */\n   0xA0, 0x00, 0x60, 0xE0, 0x60,        /* 0xEB edieresis */\n   0x80, 0x40, 0x80, 0x80, 0x80,        /* 0xEC igrave */\n   0x40, 0x80, 0x40, 0x40, 0x40,        /* 0xED iacute */\n   0xE0, 0x00, 0x40, 0x40, 0x40,        /* 0xEE icircumflex */\n   0xA0, 0x00, 0x40, 0x40, 0x40,        /* 0xEF idieresis */\n   0x60, 0xC0, 0x60, 0xA0, 0x60,        /* 0xF0 eth */\n   0xC0, 0x60, 0xC0, 0xA0, 0xA0,        /* 0xF1 ntilde */\n   0x40, 0x20, 0x40, 0xA0, 0x40,        /* 0xF2 ograve */\n   0x40, 0x80, 0x40, 0xA0, 0x40,        /* 0xF3 oacute */\n   0xE0, 0x00, 0x40, 0xA0, 0x40,        /* 0xF4 ocircumflex */\n   0xC0, 0x60, 0x40, 0xA0, 0x40,        /* 0xF5 otilde */\n   0xA0, 0x00, 0x40, 0xA0, 0x40,        /* 0xF6 odieresis */\n   0x40, 0x00, 0xE0, 0x00, 0x40,        /* 0xF7 divide */\n   0x60, 0xE0, 0xA0, 0xC0,              /* 0xF8 oslash */\n   0x80, 0x40, 0xA0, 0xA0, 0x60,        /* 0xF9 ugrave */\n   0x20, 0x40, 0xA0, 0xA0, 0x60,        /* 0xFA uacute */\n   0xE0, 0x00, 0xA0, 0xA0, 0x60,        /* 0xFB ucircumflex */\n   0xA0, 0x00, 0xA0, 0xA0, 0x60,        /* 0xFC udieresis */\n   0x20, 0x40, 0xA0, 0x60, 0x20, 0x40,  /* 0xFD yacute */\n   0x80, 0xC0, 0xA0, 0xC0, 0x80,        /* 0xFE thorn */\n   0xA0, 0x00, 0xA0, 0x60, 0x20, 0x40,  /* 0xFF ydieresis */\n   0x00,                                /* 0x11D gcircumflex */\n   0x60, 0xC0, 0xE0, 0xC0, 0x60,        /* 0x152 OE */\n   0x60, 0xE0, 0xC0, 0xE0,              /* 0x153 oe */\n   0xA0, 0x60, 0xC0, 0x60, 0xC0,        /* 0x160 Scaron */\n   0xA0, 0x60, 0xC0, 0x60, 0xC0,        /* 0x161 scaron */\n   0xA0, 0x00, 0xA0, 0x40, 0x40,        /* 0x178 Ydieresis */\n   0xA0, 0xE0, 0x60, 0xC0, 0xE0,        /* 0x17D Zcaron */\n   0xA0, 0xE0, 0x60, 0xC0, 0xE0,        /* 0x17E zcaron */\n   0x00,                                /* 0xEA4 uni0EA4 */\n   0x00,                                /* 0x13A0 uni13A0 */\n   0x80,                                /* 0x2022 bullet */\n   0xA0,                                /* 0x2026 ellipsis */\n   0x60, 0xE0, 0xE0, 0xC0, 0x60,        /* 0x20AC Euro */\n   0xE0, 0xA0, 0xA0, 0xA0, 0xE0,        /* 0xFFFD uniFFFD */\n#endif /* (TOMTHUMB_USE_EXTENDED)  */\n  };\n\n\n/* {offset, width, height, advance cursor, x offset, y offset} */\nconst GFXglyph TomThumbGlyphs[] PROGMEM = {\n   { 0, 8, 1, 2, 0, -5 },    /* 0x20 space */\n   { 1, 8, 5, 2, 0, -5 },    /* 0x21 exclam */\n   { 6, 8, 2, 4, 0, -5 },    /* 0x22 quotedbl */\n   { 8, 8, 5, 4, 0, -5 },    /* 0x23 numbersign */\n   { 13, 8, 5, 4, 0, -5 },   /* 0x24 dollar */\n   { 18, 8, 5, 4, 0, -5 },   /* 0x25 percent */\n   { 23, 8, 5, 4, 0, -5 },   /* 0x26 ampersand */\n   { 28, 8, 2, 2, 0, -5 },   /* 0x27 quotesingle */\n   { 30, 8, 5, 3, 0, -5 },   /* 0x28 parenleft */\n   { 35, 8, 5, 3, 0, -5 },   /* 0x29 parenright */\n   { 40, 8, 3, 4, 0, -5 },   /* 0x2A asterisk */\n   { 43, 8, 3, 4, 0, -4 },   /* 0x2B plus */\n   { 46, 8, 2, 3, 0, -2 },   /* 0x2C comma */\n   { 48, 8, 1, 4, 0, -3 },   /* 0x2D hyphen */\n   { 49, 8, 1, 2, 0, -1 },   /* 0x2E period */\n   { 50, 8, 5, 4, 0, -5 },   /* 0x2F slash */\n   { 55, 8, 5, 4, 0, -5 },   /* 0x30 zero */\n   { 60, 8, 5, 3, 0, -5 },   /* 0x31 one */\n   { 65, 8, 5, 4, 0, -5 },   /* 0x32 two */\n   { 70, 8, 5, 4, 0, -5 },   /* 0x33 three */\n   { 75, 8, 5, 4, 0, -5 },   /* 0x34 four */\n   { 80, 8, 5, 4, 0, -5 },   /* 0x35 five */\n   { 85, 8, 5, 4, 0, -5 },   /* 0x36 six */\n   { 90, 8, 5, 4, 0, -5 },   /* 0x37 seven */\n   { 95, 8, 5, 4, 0, -5 },   /* 0x38 eight */\n   { 100, 8, 5, 4, 0, -5 },  /* 0x39 nine */\n   { 105, 8, 3, 2, 0, -4 },  /* 0x3A colon */\n   { 108, 8, 4, 3, 0, -4 },  /* 0x3B semicolon */\n   { 112, 8, 5, 4, 0, -5 },  /* 0x3C less */\n   { 117, 8, 3, 4, 0, -4 },  /* 0x3D equal */\n   { 120, 8, 5, 4, 0, -5 },  /* 0x3E greater */\n   { 125, 8, 5, 4, 0, -5 },  /* 0x3F question */\n   { 130, 8, 5, 4, 0, -5 },  /* 0x40 at */\n   { 135, 8, 5, 4, 0, -5 },  /* 0x41 A */\n   { 140, 8, 5, 4, 0, -5 },  /* 0x42 B */\n   { 145, 8, 5, 4, 0, -5 },  /* 0x43 C */\n   { 150, 8, 5, 4, 0, -5 },  /* 0x44 D */\n   { 155, 8, 5, 4, 0, -5 },  /* 0x45 E */\n   { 160, 8, 5, 4, 0, -5 },  /* 0x46 F */\n   { 165, 8, 5, 4, 0, -5 },  /* 0x47 G */\n   { 170, 8, 5, 4, 0, -5 },  /* 0x48 H */\n   { 175, 8, 5, 4, 0, -5 },  /* 0x49 I */\n   { 180, 8, 5, 4, 0, -5 },  /* 0x4A J */\n   { 185, 8, 5, 4, 0, -5 },  /* 0x4B K */\n   { 190, 8, 5, 4, 0, -5 },  /* 0x4C L */\n   { 195, 8, 5, 4, 0, -5 },  /* 0x4D M */\n   { 200, 8, 5, 4, 0, -5 },  /* 0x4E N */\n   { 205, 8, 5, 4, 0, -5 },  /* 0x4F O */\n   { 210, 8, 5, 4, 0, -5 },  /* 0x50 P */\n   { 215, 8, 5, 4, 0, -5 },  /* 0x51 Q */\n   { 220, 8, 5, 4, 0, -5 },  /* 0x52 R */\n   { 225, 8, 5, 4, 0, -5 },  /* 0x53 S */\n   { 230, 8, 5, 4, 0, -5 },  /* 0x54 T */\n   { 235, 8, 5, 4, 0, -5 },  /* 0x55 U */\n   { 240, 8, 5, 4, 0, -5 },  /* 0x56 V */\n   { 245, 8, 5, 4, 0, -5 },  /* 0x57 W */\n   { 250, 8, 5, 4, 0, -5 },  /* 0x58 X */\n   { 255, 8, 5, 4, 0, -5 },  /* 0x59 Y */\n   { 260, 8, 5, 4, 0, -5 },  /* 0x5A Z */\n   { 265, 8, 5, 4, 0, -5 },  /* 0x5B bracketleft */\n   { 270, 8, 3, 4, 0, -4 },  /* 0x5C backslash */\n   { 273, 8, 5, 4, 0, -5 },  /* 0x5D bracketright */\n   { 278, 8, 2, 4, 0, -5 },  /* 0x5E asciicircum */\n   { 280, 8, 1, 4, 0, -1 },  /* 0x5F underscore */\n   { 281, 8, 2, 3, 0, -5 },  /* 0x60 grave */\n   { 283, 8, 4, 4, 0, -4 },  /* 0x61 a */\n   { 287, 8, 5, 4, 0, -5 },  /* 0x62 b */\n   { 292, 8, 4, 4, 0, -4 },  /* 0x63 c */\n   { 296, 8, 5, 4, 0, -5 },  /* 0x64 d */\n   { 301, 8, 4, 4, 0, -4 },  /* 0x65 e */\n   { 305, 8, 5, 4, 0, -5 },  /* 0x66 f */\n   { 310, 8, 5, 4, 0, -4 },  /* 0x67 g */\n   { 315, 8, 5, 4, 0, -5 },  /* 0x68 h */\n   { 320, 8, 5, 2, 0, -5 },  /* 0x69 i */\n   { 325, 8, 6, 4, 0, -5 },  /* 0x6A j */\n   { 331, 8, 5, 4, 0, -5 },  /* 0x6B k */\n   { 336, 8, 5, 4, 0, -5 },  /* 0x6C l */\n   { 341, 8, 4, 4, 0, -4 },  /* 0x6D m */\n   { 345, 8, 4, 4, 0, -4 },  /* 0x6E n */\n   { 349, 8, 4, 4, 0, -4 },  /* 0x6F o */\n   { 353, 8, 5, 4, 0, -4 },  /* 0x70 p */\n   { 358, 8, 5, 4, 0, -4 },  /* 0x71 q */\n   { 363, 8, 4, 4, 0, -4 },  /* 0x72 r */\n   { 367, 8, 4, 4, 0, -4 },  /* 0x73 s */\n   { 371, 8, 5, 4, 0, -5 },  /* 0x74 t */\n   { 376, 8, 4, 4, 0, -4 },  /* 0x75 u */\n   { 380, 8, 4, 4, 0, -4 },  /* 0x76 v */\n   { 384, 8, 4, 4, 0, -4 },  /* 0x77 w */\n   { 388, 8, 4, 4, 0, -4 },  /* 0x78 x */\n   { 392, 8, 5, 4, 0, -4 },  /* 0x79 y */\n   { 397, 8, 4, 4, 0, -4 },  /* 0x7A z */\n   { 401, 8, 5, 4, 0, -5 },  /* 0x7B braceleft */\n   { 406, 8, 5, 2, 0, -5 },  /* 0x7C bar */\n   { 411, 8, 5, 4, 0, -5 },  /* 0x7D braceright */\n   { 416, 8, 2, 4, 0, -5 },  /* 0x7E asciitilde */\n#if (TOMTHUMB_USE_EXTENDED)\n   { 418, 8, 5, 2, 0, -5 },  /* 0xA1 exclamdown */\n   { 423, 8, 5, 4, 0, -5 },  /* 0xA2 cent */\n   { 428, 8, 5, 4, 0, -5 },  /* 0xA3 sterling */\n   { 433, 8, 5, 4, 0, -5 },  /* 0xA4 currency */\n   { 438, 8, 5, 4, 0, -5 },  /* 0xA5 yen */\n   { 443, 8, 5, 2, 0, -5 },  /* 0xA6 brokenbar */\n   { 448, 8, 5, 4, 0, -5 },  /* 0xA7 section */\n   { 453, 8, 1, 4, 0, -5 },  /* 0xA8 dieresis */\n   { 454, 8, 3, 4, 0, -5 },  /* 0xA9 copyright */\n   { 457, 8, 5, 4, 0, -5 },  /* 0xAA ordfeminine */\n   { 462, 8, 3, 3, 0, -5 },  /* 0xAB guillemotleft */\n   { 465, 8, 2, 4, 0, -4 },  /* 0xAC logicalnot */\n   { 467, 8, 1, 3, 0, -3 },  /* 0xAD softhyphen */\n   { 468, 8, 3, 4, 0, -5 },  /* 0xAE registered */\n   { 471, 8, 1, 4, 0, -5 },  /* 0xAF macron */\n   { 472, 8, 3, 4, 0, -5 },  /* 0xB0 degree */\n   { 475, 8, 5, 4, 0, -5 },  /* 0xB1 plusminus */\n   { 480, 8, 3, 4, 0, -5 },  /* 0xB2 twosuperior */\n   { 483, 8, 3, 4, 0, -5 },  /* 0xB3 threesuperior */\n   { 486, 8, 2, 3, 0, -5 },  /* 0xB4 acute */\n   { 488, 8, 5, 4, 0, -5 },  /* 0xB5 mu */\n   { 493, 8, 5, 4, 0, -5 },  /* 0xB6 paragraph */\n   { 498, 8, 3, 4, 0, -4 },  /* 0xB7 periodcentered */\n   { 501, 8, 3, 4, 0, -3 },  /* 0xB8 cedilla */\n   { 504, 8, 3, 2, 0, -5 },  /* 0xB9 onesuperior */\n   { 507, 8, 5, 4, 0, -5 },  /* 0xBA ordmasculine */\n   { 512, 8, 3, 3, 0, -5 },  /* 0xBB guillemotright */\n   { 515, 8, 5, 4, 0, -5 },  /* 0xBC onequarter */\n   { 520, 8, 5, 4, 0, -5 },  /* 0xBD onehalf */\n   { 525, 8, 5, 4, 0, -5 },  /* 0xBE threequarters */\n   { 530, 8, 5, 4, 0, -5 },  /* 0xBF questiondown */\n   { 535, 8, 5, 4, 0, -5 },  /* 0xC0 Agrave */\n   { 540, 8, 5, 4, 0, -5 },  /* 0xC1 Aacute */\n   { 545, 8, 5, 4, 0, -5 },  /* 0xC2 Acircumflex */\n   { 550, 8, 5, 4, 0, -5 },  /* 0xC3 Atilde */\n   { 555, 8, 5, 4, 0, -5 },  /* 0xC4 Adieresis */\n   { 560, 8, 5, 4, 0, -5 },  /* 0xC5 Aring */\n   { 565, 8, 5, 4, 0, -5 },  /* 0xC6 AE */\n   { 570, 8, 6, 4, 0, -5 },  /* 0xC7 Ccedilla */\n   { 576, 8, 5, 4, 0, -5 },  /* 0xC8 Egrave */\n   { 581, 8, 5, 4, 0, -5 },  /* 0xC9 Eacute */\n   { 586, 8, 5, 4, 0, -5 },  /* 0xCA Ecircumflex */\n   { 591, 8, 5, 4, 0, -5 },  /* 0xCB Edieresis */\n   { 596, 8, 5, 4, 0, -5 },  /* 0xCC Igrave */\n   { 601, 8, 5, 4, 0, -5 },  /* 0xCD Iacute */\n   { 606, 8, 5, 4, 0, -5 },  /* 0xCE Icircumflex */\n   { 611, 8, 5, 4, 0, -5 },  /* 0xCF Idieresis */\n   { 616, 8, 5, 4, 0, -5 },  /* 0xD0 Eth */\n   { 621, 8, 5, 4, 0, -5 },  /* 0xD1 Ntilde */\n   { 626, 8, 5, 4, 0, -5 },  /* 0xD2 Ograve */\n   { 631, 8, 5, 4, 0, -5 },  /* 0xD3 Oacute */\n   { 636, 8, 5, 4, 0, -5 },  /* 0xD4 Ocircumflex */\n   { 641, 8, 5, 4, 0, -5 },  /* 0xD5 Otilde */\n   { 646, 8, 5, 4, 0, -5 },  /* 0xD6 Odieresis */\n   { 651, 8, 3, 4, 0, -4 },  /* 0xD7 multiply */\n   { 654, 8, 5, 4, 0, -5 },  /* 0xD8 Oslash */\n   { 659, 8, 5, 4, 0, -5 },  /* 0xD9 Ugrave */\n   { 664, 8, 5, 4, 0, -5 },  /* 0xDA Uacute */\n   { 669, 8, 5, 4, 0, -5 },  /* 0xDB Ucircumflex */\n   { 674, 8, 5, 4, 0, -5 },  /* 0xDC Udieresis */\n   { 679, 8, 5, 4, 0, -5 },  /* 0xDD Yacute */\n   { 684, 8, 5, 4, 0, -5 },  /* 0xDE Thorn */\n   { 689, 8, 6, 4, 0, -5 },  /* 0xDF germandbls */\n   { 695, 8, 5, 4, 0, -5 },  /* 0xE0 agrave */\n   { 700, 8, 5, 4, 0, -5 },  /* 0xE1 aacute */\n   { 705, 8, 5, 4, 0, -5 },  /* 0xE2 acircumflex */\n   { 710, 8, 5, 4, 0, -5 },  /* 0xE3 atilde */\n   { 715, 8, 5, 4, 0, -5 },  /* 0xE4 adieresis */\n   { 720, 8, 5, 4, 0, -5 },  /* 0xE5 aring */\n   { 725, 8, 4, 4, 0, -4 },  /* 0xE6 ae */\n   { 729, 8, 5, 4, 0, -4 },  /* 0xE7 ccedilla */\n   { 734, 8, 5, 4, 0, -5 },  /* 0xE8 egrave */\n   { 739, 8, 5, 4, 0, -5 },  /* 0xE9 eacute */\n   { 744, 8, 5, 4, 0, -5 },  /* 0xEA ecircumflex */\n   { 749, 8, 5, 4, 0, -5 },  /* 0xEB edieresis */\n   { 754, 8, 5, 3, 0, -5 },  /* 0xEC igrave */\n   { 759, 8, 5, 3, 0, -5 },  /* 0xED iacute */\n   { 764, 8, 5, 4, 0, -5 },  /* 0xEE icircumflex */\n   { 769, 8, 5, 4, 0, -5 },  /* 0xEF idieresis */\n   { 774, 8, 5, 4, 0, -5 },  /* 0xF0 eth */\n   { 779, 8, 5, 4, 0, -5 },  /* 0xF1 ntilde */\n   { 784, 8, 5, 4, 0, -5 },  /* 0xF2 ograve */\n   { 789, 8, 5, 4, 0, -5 },  /* 0xF3 oacute */\n   { 794, 8, 5, 4, 0, -5 },  /* 0xF4 ocircumflex */\n   { 799, 8, 5, 4, 0, -5 },  /* 0xF5 otilde */\n   { 804, 8, 5, 4, 0, -5 },  /* 0xF6 odieresis */\n   { 809, 8, 5, 4, 0, -5 },  /* 0xF7 divide */\n   { 814, 8, 4, 4, 0, -4 },  /* 0xF8 oslash */\n   { 818, 8, 5, 4, 0, -5 },  /* 0xF9 ugrave */\n   { 823, 8, 5, 4, 0, -5 },  /* 0xFA uacute */\n   { 828, 8, 5, 4, 0, -5 },  /* 0xFB ucircumflex */\n   { 833, 8, 5, 4, 0, -5 },  /* 0xFC udieresis */\n   { 838, 8, 6, 4, 0, -5 },  /* 0xFD yacute */\n   { 844, 8, 5, 4, 0, -4 },  /* 0xFE thorn */\n   { 849, 8, 6, 4, 0, -5 },  /* 0xFF ydieresis */\n   { 855, 8, 1, 2, 0, -1 },  /* 0x11D gcircumflex */\n   { 856, 8, 5, 4, 0, -5 },  /* 0x152 OE */\n   { 861, 8, 4, 4, 0, -4 },  /* 0x153 oe */\n   { 865, 8, 5, 4, 0, -5 },  /* 0x160 Scaron */\n   { 870, 8, 5, 4, 0, -5 },  /* 0x161 scaron */\n   { 875, 8, 5, 4, 0, -5 },  /* 0x178 Ydieresis */\n   { 880, 8, 5, 4, 0, -5 },  /* 0x17D Zcaron */\n   { 885, 8, 5, 4, 0, -5 },  /* 0x17E zcaron */\n   { 890, 8, 1, 2, 0, -1 },  /* 0xEA4 uni0EA4 */\n   { 891, 8, 1, 2, 0, -1 },  /* 0x13A0 uni13A0 */\n   { 892, 8, 1, 2, 0, -3 },  /* 0x2022 bullet */\n   { 893, 8, 1, 4, 0, -1 },  /* 0x2026 ellipsis */\n   { 894, 8, 5, 4, 0, -5 },  /* 0x20AC Euro */\n   { 899, 8, 5, 4, 0, -5 },  /* 0xFFFD uniFFFD */\n#endif /* (TOMTHUMB_USE_EXTENDED) */\n};\n\nconst GFXfont TomThumb PROGMEM = {\n  (uint8_t  *)TomThumbBitmaps,\n  (GFXglyph *)TomThumbGlyphs,\n  0x20, 0x7E, 6 };\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/README.md",
    "content": "# Adafruit GFX Library\n\nThis is the core graphics library for all our displays, providing a common set of graphics primitives (points, lines, circles, etc.). It needs to be paired with a hardware-specific library for each display device we carry (to handle the lower-level functions).\n\nAdafruit invests time and resources providing this open source code, please support Adafruit and open-source hardware by purchasing products from Adafruit!\n\nWritten by Limor Fried/Ladyada for Adafruit Industries.\nBSD license, check license.txt for more information.\nAll text above must be included in any redistribution.\n\nRecent Arduino IDE releases include the Library Manager for easy installation. Otherwise, to download, click the DOWNLOAD ZIP button, uncompress and rename the uncompressed folder Adafruit_GFX. Confirm that the Adafruit_GFX folder contains Adafruit_GFX.cpp and Adafruit_GFX.h. Place the Adafruit_GFX library folder your <arduinosketchfolder>/Libraries/ folder. You may need to create the Libraries subfolder if its your first library. Restart the IDE.\n\n# Useful Resources\n\n- Image2Code: This is a handy Java GUI utility to convert a BMP file into the array code necessary to display the image with the drawBitmap function. Check out the code at ehubin's GitHub repository: https://github.com/ehubin/Adafruit-GFX-Library/tree/master/Img2Code\n\n- drawXBitmap function: You can use the GIMP photo editor to save a .xbm file and use the array saved in the file to draw a bitmap with the drawXBitmap function. See the pull request here for more details: https://github.com/adafruit/Adafruit-GFX-Library/pull/31\n\n- 'Fonts' folder contains bitmap fonts for use with recent (1.1 and later) Adafruit_GFX. To use a font in your Arduino sketch, #include the corresponding .h file and pass address of GFXfont struct to setFont(). Pass NULL to revert to 'classic' fixed-space bitmap font.\n\n- 'fontconvert' folder contains a command-line tool for converting TTF fonts to Adafruit_GFX .h format.\n\n---\n\n### Roadmap\n\nThe PRIME DIRECTIVE is to maintain backward compatibility with existing Arduino sketches -- many are hosted elsewhere and don't track changes here, some are in print and can never be changed! This \"little\" library has grown organically over time and sometimes we paint ourselves into a design corner and just have to live with it or add ungainly workarounds.\n\nHighly unlikely to merge any changes for additional or incompatible font formats (see Prime Directive above). There are already two formats and the code is quite bloaty there as it is (this also creates liabilities for tools and documentation). If you *must* have a more sophisticated font format, consider creating a fork with the features required for your project. For similar reasons, also unlikely to add any more bitmap formats, it's getting messy.\n\nPlease don't reformat code for the sake of reformatting code. The resulting large \"visual diff\" makes it impossible to untangle actual bug fixes from merely rearranged lines.\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/fontconvert/Makefile",
    "content": "all: fontconvert\n\nCC     = gcc\nCFLAGS = -Wall -I/usr/local/include/freetype2 -I/usr/include/freetype2 -I/usr/include\nLIBS   = -lfreetype\n\nfontconvert: fontconvert.c\n\t$(CC) $(CFLAGS) $< $(LIBS) -o $@\n\tstrip $@\n\nclean:\n\trm -f fontconvert\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/fontconvert/fontconvert.c",
    "content": "/*\nTrueType to Adafruit_GFX font converter.  Derived from Peter Jakobs'\nAdafruit_ftGFX fork & makefont tool, and Paul Kourany's Adafruit_mfGFX.\n\nNOT AN ARDUINO SKETCH.  This is a command-line tool for preprocessing\nfonts to be used with the Adafruit_GFX Arduino library.\n\nFor UNIX-like systems.  Outputs to stdout; redirect to header file, e.g.:\n  ./fontconvert ~/Library/Fonts/FreeSans.ttf 18 > FreeSans18pt7b.h\n\nREQUIRES FREETYPE LIBRARY.  www.freetype.org\n\nCurrently this only extracts the printable 7-bit ASCII chars of a font.\nWill eventually extend with some int'l chars a la ftGFX, not there yet.\nKeep 7-bit fonts around as an option in that case, more compact.\n\nSee notes at end for glyph nomenclature & other tidbits.\n*/\n\n#include <stdio.h>\n#include <ctype.h>\n#include <stdint.h>\n#include <ft2build.h>\n#include FT_GLYPH_H\n#include \"../gfxfont.h\" // Adafruit_GFX font structures\n\n#define DPI 141 // Approximate res. of Adafruit 2.8\" TFT\n\n// Accumulate bits for output, with periodic hexadecimal byte write\nvoid enbit(uint8_t value) {\n\tstatic uint8_t row = 0, sum = 0, bit = 0x80, firstCall = 1;\n\tif(value) sum |= bit;    // Set bit if needed\n\tif(!(bit >>= 1)) {       // Advance to next bit, end of byte reached?\n\t\tif(!firstCall) { // Format output table nicely\n\t\t\tif(++row >= 12) {        // Last entry on line?\n\t\t\t\tprintf(\",\\n  \"); //   Newline format output\n\t\t\t\trow = 0;         //   Reset row counter\n\t\t\t} else {                 // Not end of line\n\t\t\t\tprintf(\", \");    //   Simple comma delim\n\t\t\t}\n\t\t}\n\t\tprintf(\"0x%02X\", sum); // Write byte value\n\t\tsum       = 0;         // Clear for next byte\n\t\tbit       = 0x80;      // Reset bit counter\n\t\tfirstCall = 0;         // Formatting flag\n\t}\n}\n\nint main(int argc, char *argv[]) {\n\tint                i, j, err, size, first=' ', last='~',\n\t                   bitmapOffset = 0, x, y, byte;\n\tchar              *fontName, c, *ptr;\n\tFT_Library         library;\n\tFT_Face            face;\n\tFT_Glyph           glyph;\n\tFT_Bitmap         *bitmap;\n\tFT_BitmapGlyphRec *g;\n\tGFXglyph          *table;\n\tuint8_t            bit;\n\n\t// Parse command line.  Valid syntaxes are:\n\t//   fontconvert [filename] [size]\n\t//   fontconvert [filename] [size] [last char]\n\t//   fontconvert [filename] [size] [first char] [last char]\n\t// Unless overridden, default first and last chars are\n\t// ' ' (space) and '~', respectively\n\n\tif(argc < 3) {\n\t\tfprintf(stderr, \"Usage: %s fontfile size [first] [last]\\n\",\n\t\t  argv[0]);\n\t\treturn 1;\n\t}\n\n\tsize = atoi(argv[2]);\n\n\tif(argc == 4) {\n\t\tlast  = atoi(argv[3]);\n\t} else if(argc == 5) {\n\t\tfirst = atoi(argv[3]);\n\t\tlast  = atoi(argv[4]);\n\t}\n\n\tif(last < first) {\n\t\ti     = first;\n\t\tfirst = last;\n\t\tlast  = i;\n\t}\n\n\tptr = strrchr(argv[1], '/'); // Find last slash in filename\n\tif(ptr) ptr++;         // First character of filename (path stripped)\n\telse    ptr = argv[1]; // No path; font in local dir.\n\n\t// Allocate space for font name and glyph table\n\tif((!(fontName = malloc(strlen(ptr) + 20))) ||\n\t   (!(table = (GFXglyph *)malloc((last - first + 1) *\n\t    sizeof(GFXglyph))))) {\n\t\tfprintf(stderr, \"Malloc error\\n\");\n\t\treturn 1;\n\t}\n\n\t// Derive font table names from filename.  Period (filename\n\t// extension) is truncated and replaced with the font size & bits.\n\tstrcpy(fontName, ptr);\n\tptr = strrchr(fontName, '.'); // Find last period (file ext)\n\tif(!ptr) ptr = &fontName[strlen(fontName)]; // If none, append\n\t// Insert font size and 7/8 bit.  fontName was alloc'd w/extra\n\t// space to allow this, we're not sprintfing into Forbidden Zone.\n\tsprintf(ptr, \"%dpt%db\", size, (last > 127) ? 8 : 7);\n\t// Space and punctuation chars in name replaced w/ underscores.  \n\tfor(i=0; (c=fontName[i]); i++) {\n\t\tif(isspace(c) || ispunct(c)) fontName[i] = '_';\n\t}\n\n\t// Init FreeType lib, load font\n\tif((err = FT_Init_FreeType(&library))) {\n\t\tfprintf(stderr, \"FreeType init error: %d\", err);\n\t\treturn err;\n\t}\n\tif((err = FT_New_Face(library, argv[1], 0, &face))) {\n\t\tfprintf(stderr, \"Font load error: %d\", err);\n\t\tFT_Done_FreeType(library);\n\t\treturn err;\n\t}\n\n\t// << 6 because '26dot6' fixed-point format\n\tFT_Set_Char_Size(face, size << 6, 0, DPI, 0);\n\n\t// Currently all symbols from 'first' to 'last' are processed.\n\t// Fonts may contain WAY more glyphs than that, but this code\n\t// will need to handle encoding stuff to deal with extracting\n\t// the right symbols, and that's not done yet.\n\t// fprintf(stderr, \"%ld glyphs\\n\", face->num_glyphs);\n\n\tprintf(\"const uint8_t %sBitmaps[] PROGMEM = {\\n  \", fontName);\n\n\t// Process glyphs and output huge bitmap data array\n\tfor(i=first, j=0; i<=last; i++, j++) {\n\t\t// MONO renderer provides clean image with perfect crop\n\t\t// (no wasted pixels) via bitmap struct.\n\t\tif((err = FT_Load_Char(face, i, FT_LOAD_TARGET_MONO))) {\n\t\t\tfprintf(stderr, \"Error %d loading char '%c'\\n\",\n\t\t\t  err, i);\n\t\t\tcontinue;\n\t\t}\n\n\t\tif((err = FT_Render_Glyph(face->glyph,\n\t\t  FT_RENDER_MODE_MONO))) {\n\t\t\tfprintf(stderr, \"Error %d rendering char '%c'\\n\",\n\t\t\t  err, i);\n\t\t\tcontinue;\n\t\t}\n\n\t\tif((err = FT_Get_Glyph(face->glyph, &glyph))) {\n\t\t\tfprintf(stderr, \"Error %d getting glyph '%c'\\n\",\n\t\t\t  err, i);\n\t\t\tcontinue;\n\t\t}\n\n\t\tbitmap = &face->glyph->bitmap;\n\t\tg      = (FT_BitmapGlyphRec *)glyph;\n\n\t\t// Minimal font and per-glyph information is stored to\n\t\t// reduce flash space requirements.  Glyph bitmaps are\n\t\t// fully bit-packed; no per-scanline pad, though end of\n\t\t// each character may be padded to next byte boundary\n\t\t// when needed.  16-bit offset means 64K max for bitmaps,\n\t\t// code currently doesn't check for overflow.  (Doesn't\n\t\t// check that size & offsets are within bounds either for\n\t\t// that matter...please convert fonts responsibly.)\n\t\ttable[j].bitmapOffset = bitmapOffset;\n\t\ttable[j].width        = bitmap->width;\n\t\ttable[j].height       = bitmap->rows;\n\t\ttable[j].xAdvance     = face->glyph->advance.x >> 6;\n\t\ttable[j].xOffset      = g->left;\n\t\ttable[j].yOffset      = 1 - g->top;\n\n\t\tfor(y=0; y < bitmap->rows; y++) {\n\t\t\tfor(x=0;x < bitmap->width; x++) {\n\t\t\t\tbyte = x / 8;\n\t\t\t\tbit  = 0x80 >> (x & 7);\n\t\t\t\tenbit(bitmap->buffer[\n\t\t\t\t  y * bitmap->pitch + byte] & bit);\n\t\t\t}\n\t\t}\n\n\t\t// Pad end of char bitmap to next byte boundary if needed\n\t\tint n = (bitmap->width * bitmap->rows) & 7;\n\t\tif(n) { // Pixel count not an even multiple of 8?\n\t\t\tn = 8 - n; // # bits to next multiple\n\t\t\twhile(n--) enbit(0);\n\t\t}\n\t\tbitmapOffset += (bitmap->width * bitmap->rows + 7) / 8;\n\n\t\tFT_Done_Glyph(glyph);\n\t}\n\n\tprintf(\" };\\n\\n\"); // End bitmap array\n\n\t// Output glyph attributes table (one per character)\n\tprintf(\"const GFXglyph %sGlyphs[] PROGMEM = {\\n\", fontName);\n\tfor(i=first, j=0; i<=last; i++, j++) {\n\t\tprintf(\"  { %5d, %3d, %3d, %3d, %4d, %4d }\",\n\t\t  table[j].bitmapOffset,\n\t\t  table[j].width,\n\t\t  table[j].height,\n\t\t  table[j].xAdvance,\n\t\t  table[j].xOffset,\n\t\t  table[j].yOffset);\n\t\tif(i < last) {\n\t\t\tprintf(\",   // 0x%02X\", i);\n\t\t\tif((i >= ' ') && (i <= '~')) {\n\t\t\t\tprintf(\" '%c'\", i);\n\t\t\t}\n\t\t\tputchar('\\n');\n\t\t}\n\t}\n\tprintf(\" }; // 0x%02X\", last);\n\tif((last >= ' ') && (last <= '~')) printf(\" '%c'\", last);\n\tprintf(\"\\n\\n\");\n\n\t// Output font structure\n\tprintf(\"const GFXfont %s PROGMEM = {\\n\", fontName);\n\tprintf(\"  (uint8_t  *)%sBitmaps,\\n\", fontName);\n\tprintf(\"  (GFXglyph *)%sGlyphs,\\n\", fontName);\n\tif (face->size->metrics.height == 0) {\n      // No face height info, assume fixed width and get from a glyph.\n\t\tprintf(\"  0x%02X, 0x%02X, %d };\\n\\n\",\n\t\t\tfirst, last, table[0].height);\n\t} else {\n\t\tprintf(\"  0x%02X, 0x%02X, %ld };\\n\\n\",\n\t\t\tfirst, last, face->size->metrics.height >> 6);\n\t}\n\tprintf(\"// Approx. %d bytes\\n\",\n\t  bitmapOffset + (last - first + 1) * 7 + 7);\n\t// Size estimate is based on AVR struct and pointer sizes;\n\t// actual size may vary.\n\n\tFT_Done_FreeType(library);\n\n\treturn 0;\n}\n\n/* -------------------------------------------------------------------------\n\nCharacter metrics are slightly different from classic GFX & ftGFX.\nIn classic GFX: cursor position is the upper-left pixel of each 5x7\ncharacter; lower extent of most glyphs (except those w/descenders)\nis +6 pixels in Y direction.\nW/new GFX fonts: cursor position is on baseline, where baseline is\n'inclusive' (containing the bottom-most row of pixels in most symbols,\nexcept those with descenders; ftGFX is one pixel lower).\n\nCursor Y will be moved automatically when switching between classic\nand new fonts.  If you switch fonts, any print() calls will continue\nalong the same baseline.\n\n                    ...........#####.. -- yOffset\n                    ..........######..\n                    ..........######..\n                    .........#######..\n                    ........#########.\n   * = Cursor pos.  ........#########.\n                    .......##########.\n                    ......#####..####.\n                    ......#####..####.\n       *.#..        .....#####...####.\n       .#.#.        ....##############\n       #...#        ...###############\n       #...#        ...###############\n       #####        ..#####......#####\n       #...#        .#####.......#####\n====== #...# ====== #*###.........#### ======= Baseline\n                    || xOffset\n\nglyph->xOffset and yOffset are pixel offsets, in GFX coordinate space\n(+Y is down), from the cursor position to the top-left pixel of the\nglyph bitmap.  i.e. yOffset is typically negative, xOffset is typically\nzero but a few glyphs will have other values (even negative xOffsets\nsometimes, totally normal).  glyph->xAdvance is the distance to move\nthe cursor on the X axis after drawing the corresponding symbol.\n\nThere's also some changes with regard to 'background' color and new GFX\nfonts (classic fonts unchanged).  See Adafruit_GFX.cpp for explanation.\n*/\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/fontconvert/fontconvert_win.md",
    "content": "### A short guide to use fontconvert.c to create your own fonts using MinGW.\r\n\r\n#### STEP 1: INSTALL MinGW\r\n\r\nInstall MinGW (Minimalist GNU for Windows) from [MinGW.org](http://www.mingw.org/).\r\nPlease read carefully the instructions found on [Getting started page](http://www.mingw.org/wiki/Getting_Started).\r\nI suggest installing with the \"Graphical User Interface Installer\".\r\nTo complete your initial installation you should further install some \"packages\".\r\nFor our purpose you should only install the \"Basic Setup\" packages.\r\nTo do that:\r\n\r\n1. Open the MinGW Installation Manager\r\n2. From the left panel click \"Basic Setup\".\r\n3. On the right panel choose \"mingw32-base\", \"mingw-gcc-g++\", \"mingw-gcc-objc\" and \"msys-base\"\r\nand click \"Mark for installation\"\r\n4. From the Menu click \"Installation\" and then \"Apply changes\". In the pop-up window select \"Apply\".\r\n\r\n\r\n#### STEP 2: INSTALL Freetype Library\r\n\r\nTo read about the freetype project visit [freetype.org](https://www.freetype.org/).\r\nTo Download the latest version of freetype go to [download page](http://download.savannah.gnu.org/releases/freetype/)\r\nand choose \"freetype-2.7.tar.gz\" file (or a newer version if available).\r\nTo avoid long cd commands later in the command prompt, I suggest you unzip the file in the C:\\ directory.\r\n(I also renamed the folder to \"ft27\")\r\nBefore you build the library it's good to read these articles:\r\n* [Using MSYS with MinGW](http://www.mingw.org/wiki/MSYS)\r\n* [Installation and Use of Supplementary Libraries with MinGW](http://www.mingw.org/wiki/LibraryPathHOWTO)\r\n* [Include Path](http://www.mingw.org/wiki/IncludePathHOWTO)\r\n\r\nInside the unzipped folder there is another folder named \"docs\". Open it and read the INSTALL.UNIX (using notepad).\r\nPay attention to paragraph 3 (Build and Install the Library). So, let's begin the installation.\r\nTo give the appropriate commands we will use the MSYS command prompt (not cmd.exe of windows) which is UNIX like.\r\nFollow the path C:\\MinGW\\msys\\1.0 and double click \"msys.bat\". The command prompt environment appears.\r\nEnter \"ft27\" directory using the cd commands:\r\n```\r\ncd /c\r\ncd ft27\r\n```\r\n\r\nand then type one by one the commands:\r\n```\r\n./configure --prefix=/mingw\r\nmake\r\nmake install\r\n```\r\nOnce you're finished, go inside \"C:\\MinGW\\include\" and there should be a new folder named \"freetype2\".\r\nThat, hopefully, means that you have installed the library correctly !!\r\n\r\n#### STEP 3: Build fontconvert.c\r\n\r\nBefore proceeding I suggest you make a copy of Adafruit_GFX_library folder in C:\\ directory.\r\nThen, inside \"fontconvert\" folder open the \"makefile\" with an editor ( I used notepad++).\r\nChange the commands so in the end the program looks like :\r\n```\r\nall: fontconvert\r\n\r\nCC     = gcc\r\nCFLAGS = -Wall -I c:/mingw/include/freetype2\r\nLIBS   = -lfreetype\r\n\r\nfontconvert: fontconvert.c\r\n\t$(CC) $(CFLAGS) $< $(LIBS) -o $@\r\n\r\nclean:\r\n\trm -f fontconvert\r\n```\r\nGo back in the command prompt and with a cd command enter the fontconvert directory.\r\n```\r\ncd /c/adafruit_gfx_library\\fontconvert\r\n```\r\nGive the command:\r\n```\r\nmake\r\n```\r\nThis command will, eventually, create a \"fontconvert.exe\" file inside fontconvert directory.\r\n\r\n#### STEP 4: Create your own font header files\r\n\r\nNow that you have an executable file, you can use it to create your own fonts to work with Adafruit GFX lib.\r\nSo, if we suppose that you already have a .ttf file with your favorite fonts, jump to the command prompt and type:\r\n```\r\n./fontconvert yourfonts.ttf 9 > yourfonts9pt7b.h\r\n```\r\nYou can read more details at: [learn.adafruit](https://learn.adafruit.com/adafruit-gfx-graphics-library/using-fonts).\r\n\r\nTaraaaaaammm !! you've just created your new font header file. Put it inside the \"Fonts\" folder, grab a cup of coffee\r\nand start playing with your Arduino (or whatever else ....)+ display module project.\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/fontconvert/makefonts.sh",
    "content": "#!/bin/bash\n\n# Ugly little Bash script, generates a set of .h files for GFX using\n# GNU FreeFont sources.  There are three fonts: 'Mono' (Courier-like),\n# 'Sans' (Helvetica-like) and 'Serif' (Times-like); four styles: regular,\n# bold, oblique or italic, and bold+oblique or bold+italic; and four\n# sizes: 9, 12, 18 and 24 point.  No real error checking or anything,\n# this just powers through all the combinations, calling the fontconvert\n# utility and redirecting the output to a .h file for each combo.\n\n# Adafruit_GFX repository does not include the source outline fonts\n# (huge zipfile, different license) but they're easily acquired:\n# http://savannah.gnu.org/projects/freefont/\n\nconvert=./fontconvert\ninpath=~/Desktop/freefont/\noutpath=../Fonts/\nfonts=(FreeMono FreeSans FreeSerif)\nstyles=(\"\" Bold Italic BoldItalic Oblique BoldOblique)\nsizes=(9 12 18 24)\n\nfor f in ${fonts[*]}\ndo\n\tfor index in ${!styles[*]}\n\tdo\n\t\tst=${styles[$index]}\n\t\tfor si in ${sizes[*]}\n\t\tdo\n\t\t\tinfile=$inpath$f$st\".ttf\"\n\t\t\tif [ -f $infile ] # Does source combination exist?\n\t\t\t  then\n\t\t\t\toutfile=$outpath$f$st$si\"pt7b.h\"\n#\t\t\t\tprintf \"%s %s %s > %s\\n\" $convert $infile $si $outfile\n\t\t\t\t$convert $infile $si > $outfile\n\t\t\tfi\n\t\tdone\n\tdone\ndone\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/gfxfont.h",
    "content": "// Font structures for newer Adafruit_GFX (1.1 and later).\n// Example fonts are included in 'Fonts' directory.\n// To use a font in your Arduino sketch, #include the corresponding .h\n// file and pass address of GFXfont struct to setFont().  Pass NULL to\n// revert to 'classic' fixed-space bitmap font.\n\n#ifndef _GFXFONT_H_\n#define _GFXFONT_H_\n\ntypedef struct { // Data stored PER GLYPH\n\tuint16_t bitmapOffset;     // Pointer into GFXfont->bitmap\n\tuint8_t  width, height;    // Bitmap dimensions in pixels\n\tuint8_t  xAdvance;         // Distance to advance cursor (x axis)\n\tint8_t   xOffset, yOffset; // Dist from cursor pos to UL corner\n} GFXglyph;\n\ntypedef struct { // Data stored for FONT AS A WHOLE:\n\tuint8_t  *bitmap;      // Glyph bitmaps, concatenated\n\tGFXglyph *glyph;       // Glyph array\n\tuint8_t   first, last; // ASCII extents\n\tuint8_t   yAdvance;    // Newline distance (y axis)\n} GFXfont;\n\n#endif // _GFXFONT_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/glcdfont.c",
    "content": "// This is the 'classic' fixed-space bitmap font for Adafruit_GFX since 1.0.\n// See gfxfont.h for newer custom bitmap font info.\n\n#ifndef FONT5X7_H\n#define FONT5X7_H\n\n#ifdef __AVR__\n #include <avr/io.h>\n #include <avr/pgmspace.h>\n#elif defined(ESP8266)\n #include <pgmspace.h>\n#else\n #define PROGMEM\n#endif\n\n// Standard ASCII 5x7 font\n\nstatic const unsigned char font[] PROGMEM = {\n\t0x00, 0x00, 0x00, 0x00, 0x00,\n\t0x3E, 0x5B, 0x4F, 0x5B, 0x3E,\n\t0x3E, 0x6B, 0x4F, 0x6B, 0x3E,\n\t0x1C, 0x3E, 0x7C, 0x3E, 0x1C,\n\t0x18, 0x3C, 0x7E, 0x3C, 0x18,\n\t0x1C, 0x57, 0x7D, 0x57, 0x1C,\n\t0x1C, 0x5E, 0x7F, 0x5E, 0x1C,\n\t0x00, 0x18, 0x3C, 0x18, 0x00,\n\t0xFF, 0xE7, 0xC3, 0xE7, 0xFF,\n\t0x00, 0x18, 0x24, 0x18, 0x00,\n\t0xFF, 0xE7, 0xDB, 0xE7, 0xFF,\n\t0x30, 0x48, 0x3A, 0x06, 0x0E,\n\t0x26, 0x29, 0x79, 0x29, 0x26,\n\t0x40, 0x7F, 0x05, 0x05, 0x07,\n\t0x40, 0x7F, 0x05, 0x25, 0x3F,\n\t0x5A, 0x3C, 0xE7, 0x3C, 0x5A,\n\t0x7F, 0x3E, 0x1C, 0x1C, 0x08,\n\t0x08, 0x1C, 0x1C, 0x3E, 0x7F,\n\t0x14, 0x22, 0x7F, 0x22, 0x14,\n\t0x5F, 0x5F, 0x00, 0x5F, 0x5F,\n\t0x06, 0x09, 0x7F, 0x01, 0x7F,\n\t0x00, 0x66, 0x89, 0x95, 0x6A,\n\t0x60, 0x60, 0x60, 0x60, 0x60,\n\t0x94, 0xA2, 0xFF, 0xA2, 0x94,\n\t0x08, 0x04, 0x7E, 0x04, 0x08,\n\t0x10, 0x20, 0x7E, 0x20, 0x10,\n\t0x08, 0x08, 0x2A, 0x1C, 0x08,\n\t0x08, 0x1C, 0x2A, 0x08, 0x08,\n\t0x1E, 0x10, 0x10, 0x10, 0x10,\n\t0x0C, 0x1E, 0x0C, 0x1E, 0x0C,\n\t0x30, 0x38, 0x3E, 0x38, 0x30,\n\t0x06, 0x0E, 0x3E, 0x0E, 0x06,\n\t0x00, 0x00, 0x00, 0x00, 0x00,\n\t0x00, 0x00, 0x5F, 0x00, 0x00,\n\t0x00, 0x07, 0x00, 0x07, 0x00,\n\t0x14, 0x7F, 0x14, 0x7F, 0x14,\n\t0x24, 0x2A, 0x7F, 0x2A, 0x12,\n\t0x23, 0x13, 0x08, 0x64, 0x62,\n\t0x36, 0x49, 0x56, 0x20, 0x50,\n\t0x00, 0x08, 0x07, 0x03, 0x00,\n\t0x00, 0x1C, 0x22, 0x41, 0x00,\n\t0x00, 0x41, 0x22, 0x1C, 0x00,\n\t0x2A, 0x1C, 0x7F, 0x1C, 0x2A,\n\t0x08, 0x08, 0x3E, 0x08, 0x08,\n\t0x00, 0x80, 0x70, 0x30, 0x00,\n\t0x08, 0x08, 0x08, 0x08, 0x08,\n\t0x00, 0x00, 0x60, 0x60, 0x00,\n\t0x20, 0x10, 0x08, 0x04, 0x02,\n\t0x3E, 0x51, 0x49, 0x45, 0x3E,\n\t0x00, 0x42, 0x7F, 0x40, 0x00,\n\t0x72, 0x49, 0x49, 0x49, 0x46,\n\t0x21, 0x41, 0x49, 0x4D, 0x33,\n\t0x18, 0x14, 0x12, 0x7F, 0x10,\n\t0x27, 0x45, 0x45, 0x45, 0x39,\n\t0x3C, 0x4A, 0x49, 0x49, 0x31,\n\t0x41, 0x21, 0x11, 0x09, 0x07,\n\t0x36, 0x49, 0x49, 0x49, 0x36,\n\t0x46, 0x49, 0x49, 0x29, 0x1E,\n\t0x00, 0x00, 0x14, 0x00, 0x00,\n\t0x00, 0x40, 0x34, 0x00, 0x00,\n\t0x00, 0x08, 0x14, 0x22, 0x41,\n\t0x14, 0x14, 0x14, 0x14, 0x14,\n\t0x00, 0x41, 0x22, 0x14, 0x08,\n\t0x02, 0x01, 0x59, 0x09, 0x06,\n\t0x3E, 0x41, 0x5D, 0x59, 0x4E,\n\t0x7C, 0x12, 0x11, 0x12, 0x7C,\n\t0x7F, 0x49, 0x49, 0x49, 0x36,\n\t0x3E, 0x41, 0x41, 0x41, 0x22,\n\t0x7F, 0x41, 0x41, 0x41, 0x3E,\n\t0x7F, 0x49, 0x49, 0x49, 0x41,\n\t0x7F, 0x09, 0x09, 0x09, 0x01,\n\t0x3E, 0x41, 0x41, 0x51, 0x73,\n\t0x7F, 0x08, 0x08, 0x08, 0x7F,\n\t0x00, 0x41, 0x7F, 0x41, 0x00,\n\t0x20, 0x40, 0x41, 0x3F, 0x01,\n\t0x7F, 0x08, 0x14, 0x22, 0x41,\n\t0x7F, 0x40, 0x40, 0x40, 0x40,\n\t0x7F, 0x02, 0x1C, 0x02, 0x7F,\n\t0x7F, 0x04, 0x08, 0x10, 0x7F,\n\t0x3E, 0x41, 0x41, 0x41, 0x3E,\n\t0x7F, 0x09, 0x09, 0x09, 0x06,\n\t0x3E, 0x41, 0x51, 0x21, 0x5E,\n\t0x7F, 0x09, 0x19, 0x29, 0x46,\n\t0x26, 0x49, 0x49, 0x49, 0x32,\n\t0x03, 0x01, 0x7F, 0x01, 0x03,\n\t0x3F, 0x40, 0x40, 0x40, 0x3F,\n\t0x1F, 0x20, 0x40, 0x20, 0x1F,\n\t0x3F, 0x40, 0x38, 0x40, 0x3F,\n\t0x63, 0x14, 0x08, 0x14, 0x63,\n\t0x03, 0x04, 0x78, 0x04, 0x03,\n\t0x61, 0x59, 0x49, 0x4D, 0x43,\n\t0x00, 0x7F, 0x41, 0x41, 0x41,\n\t0x02, 0x04, 0x08, 0x10, 0x20,\n\t0x00, 0x41, 0x41, 0x41, 0x7F,\n\t0x04, 0x02, 0x01, 0x02, 0x04,\n\t0x40, 0x40, 0x40, 0x40, 0x40,\n\t0x00, 0x03, 0x07, 0x08, 0x00,\n\t0x20, 0x54, 0x54, 0x78, 0x40,\n\t0x7F, 0x28, 0x44, 0x44, 0x38,\n\t0x38, 0x44, 0x44, 0x44, 0x28,\n\t0x38, 0x44, 0x44, 0x28, 0x7F,\n\t0x38, 0x54, 0x54, 0x54, 0x18,\n\t0x00, 0x08, 0x7E, 0x09, 0x02,\n\t0x18, 0xA4, 0xA4, 0x9C, 0x78,\n\t0x7F, 0x08, 0x04, 0x04, 0x78,\n\t0x00, 0x44, 0x7D, 0x40, 0x00,\n\t0x20, 0x40, 0x40, 0x3D, 0x00,\n\t0x7F, 0x10, 0x28, 0x44, 0x00,\n\t0x00, 0x41, 0x7F, 0x40, 0x00,\n\t0x7C, 0x04, 0x78, 0x04, 0x78,\n\t0x7C, 0x08, 0x04, 0x04, 0x78,\n\t0x38, 0x44, 0x44, 0x44, 0x38,\n\t0xFC, 0x18, 0x24, 0x24, 0x18,\n\t0x18, 0x24, 0x24, 0x18, 0xFC,\n\t0x7C, 0x08, 0x04, 0x04, 0x08,\n\t0x48, 0x54, 0x54, 0x54, 0x24,\n\t0x04, 0x04, 0x3F, 0x44, 0x24,\n\t0x3C, 0x40, 0x40, 0x20, 0x7C,\n\t0x1C, 0x20, 0x40, 0x20, 0x1C,\n\t0x3C, 0x40, 0x30, 0x40, 0x3C,\n\t0x44, 0x28, 0x10, 0x28, 0x44,\n\t0x4C, 0x90, 0x90, 0x90, 0x7C,\n\t0x44, 0x64, 0x54, 0x4C, 0x44,\n\t0x00, 0x08, 0x36, 0x41, 0x00,\n\t0x00, 0x00, 0x77, 0x00, 0x00,\n\t0x00, 0x41, 0x36, 0x08, 0x00,\n\t0x02, 0x01, 0x02, 0x04, 0x02,\n\t0x3C, 0x26, 0x23, 0x26, 0x3C,\n\t0x1E, 0xA1, 0xA1, 0x61, 0x12,\n\t0x3A, 0x40, 0x40, 0x20, 0x7A,\n\t0x38, 0x54, 0x54, 0x55, 0x59,\n\t0x21, 0x55, 0x55, 0x79, 0x41,\n\t0x22, 0x54, 0x54, 0x78, 0x42, // a-umlaut\n\t0x21, 0x55, 0x54, 0x78, 0x40,\n\t0x20, 0x54, 0x55, 0x79, 0x40,\n\t0x0C, 0x1E, 0x52, 0x72, 0x12,\n\t0x39, 0x55, 0x55, 0x55, 0x59,\n\t0x39, 0x54, 0x54, 0x54, 0x59,\n\t0x39, 0x55, 0x54, 0x54, 0x58,\n\t0x00, 0x00, 0x45, 0x7C, 0x41,\n\t0x00, 0x02, 0x45, 0x7D, 0x42,\n\t0x00, 0x01, 0x45, 0x7C, 0x40,\n\t0x7D, 0x12, 0x11, 0x12, 0x7D, // A-umlaut\n\t0xF0, 0x28, 0x25, 0x28, 0xF0,\n\t0x7C, 0x54, 0x55, 0x45, 0x00,\n\t0x20, 0x54, 0x54, 0x7C, 0x54,\n\t0x7C, 0x0A, 0x09, 0x7F, 0x49,\n\t0x32, 0x49, 0x49, 0x49, 0x32,\n\t0x3A, 0x44, 0x44, 0x44, 0x3A, // o-umlaut\n\t0x32, 0x4A, 0x48, 0x48, 0x30,\n\t0x3A, 0x41, 0x41, 0x21, 0x7A,\n\t0x3A, 0x42, 0x40, 0x20, 0x78,\n\t0x00, 0x9D, 0xA0, 0xA0, 0x7D,\n\t0x3D, 0x42, 0x42, 0x42, 0x3D, // O-umlaut\n\t0x3D, 0x40, 0x40, 0x40, 0x3D,\n\t0x3C, 0x24, 0xFF, 0x24, 0x24,\n\t0x48, 0x7E, 0x49, 0x43, 0x66,\n\t0x2B, 0x2F, 0xFC, 0x2F, 0x2B,\n\t0xFF, 0x09, 0x29, 0xF6, 0x20,\n\t0xC0, 0x88, 0x7E, 0x09, 0x03,\n\t0x20, 0x54, 0x54, 0x79, 0x41,\n\t0x00, 0x00, 0x44, 0x7D, 0x41,\n\t0x30, 0x48, 0x48, 0x4A, 0x32,\n\t0x38, 0x40, 0x40, 0x22, 0x7A,\n\t0x00, 0x7A, 0x0A, 0x0A, 0x72,\n\t0x7D, 0x0D, 0x19, 0x31, 0x7D,\n\t0x26, 0x29, 0x29, 0x2F, 0x28,\n\t0x26, 0x29, 0x29, 0x29, 0x26,\n\t0x30, 0x48, 0x4D, 0x40, 0x20,\n\t0x38, 0x08, 0x08, 0x08, 0x08,\n\t0x08, 0x08, 0x08, 0x08, 0x38,\n\t0x2F, 0x10, 0xC8, 0xAC, 0xBA,\n\t0x2F, 0x10, 0x28, 0x34, 0xFA,\n\t0x00, 0x00, 0x7B, 0x00, 0x00,\n\t0x08, 0x14, 0x2A, 0x14, 0x22,\n\t0x22, 0x14, 0x2A, 0x14, 0x08,\n\t0x55, 0x00, 0x55, 0x00, 0x55, // #176 (25% block) missing in old code\n\t0xAA, 0x55, 0xAA, 0x55, 0xAA, // 50% block\n\t0xFF, 0x55, 0xFF, 0x55, 0xFF, // 75% block\n\t0x00, 0x00, 0x00, 0xFF, 0x00,\n\t0x10, 0x10, 0x10, 0xFF, 0x00,\n\t0x14, 0x14, 0x14, 0xFF, 0x00,\n\t0x10, 0x10, 0xFF, 0x00, 0xFF,\n\t0x10, 0x10, 0xF0, 0x10, 0xF0,\n\t0x14, 0x14, 0x14, 0xFC, 0x00,\n\t0x14, 0x14, 0xF7, 0x00, 0xFF,\n\t0x00, 0x00, 0xFF, 0x00, 0xFF,\n\t0x14, 0x14, 0xF4, 0x04, 0xFC,\n\t0x14, 0x14, 0x17, 0x10, 0x1F,\n\t0x10, 0x10, 0x1F, 0x10, 0x1F,\n\t0x14, 0x14, 0x14, 0x1F, 0x00,\n\t0x10, 0x10, 0x10, 0xF0, 0x00,\n\t0x00, 0x00, 0x00, 0x1F, 0x10,\n\t0x10, 0x10, 0x10, 0x1F, 0x10,\n\t0x10, 0x10, 0x10, 0xF0, 0x10,\n\t0x00, 0x00, 0x00, 0xFF, 0x10,\n\t0x10, 0x10, 0x10, 0x10, 0x10,\n\t0x10, 0x10, 0x10, 0xFF, 0x10,\n\t0x00, 0x00, 0x00, 0xFF, 0x14,\n\t0x00, 0x00, 0xFF, 0x00, 0xFF,\n\t0x00, 0x00, 0x1F, 0x10, 0x17,\n\t0x00, 0x00, 0xFC, 0x04, 0xF4,\n\t0x14, 0x14, 0x17, 0x10, 0x17,\n\t0x14, 0x14, 0xF4, 0x04, 0xF4,\n\t0x00, 0x00, 0xFF, 0x00, 0xF7,\n\t0x14, 0x14, 0x14, 0x14, 0x14,\n\t0x14, 0x14, 0xF7, 0x00, 0xF7,\n\t0x14, 0x14, 0x14, 0x17, 0x14,\n\t0x10, 0x10, 0x1F, 0x10, 0x1F,\n\t0x14, 0x14, 0x14, 0xF4, 0x14,\n\t0x10, 0x10, 0xF0, 0x10, 0xF0,\n\t0x00, 0x00, 0x1F, 0x10, 0x1F,\n\t0x00, 0x00, 0x00, 0x1F, 0x14,\n\t0x00, 0x00, 0x00, 0xFC, 0x14,\n\t0x00, 0x00, 0xF0, 0x10, 0xF0,\n\t0x10, 0x10, 0xFF, 0x10, 0xFF,\n\t0x14, 0x14, 0x14, 0xFF, 0x14,\n\t0x10, 0x10, 0x10, 0x1F, 0x00,\n\t0x00, 0x00, 0x00, 0xF0, 0x10,\n\t0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n\t0xF0, 0xF0, 0xF0, 0xF0, 0xF0,\n\t0xFF, 0xFF, 0xFF, 0x00, 0x00,\n\t0x00, 0x00, 0x00, 0xFF, 0xFF,\n\t0x0F, 0x0F, 0x0F, 0x0F, 0x0F,\n\t0x38, 0x44, 0x44, 0x38, 0x44,\n\t0xFC, 0x4A, 0x4A, 0x4A, 0x34, // sharp-s or beta\n\t0x7E, 0x02, 0x02, 0x06, 0x06,\n\t0x02, 0x7E, 0x02, 0x7E, 0x02,\n\t0x63, 0x55, 0x49, 0x41, 0x63,\n\t0x38, 0x44, 0x44, 0x3C, 0x04,\n\t0x40, 0x7E, 0x20, 0x1E, 0x20,\n\t0x06, 0x02, 0x7E, 0x02, 0x02,\n\t0x99, 0xA5, 0xE7, 0xA5, 0x99,\n\t0x1C, 0x2A, 0x49, 0x2A, 0x1C,\n\t0x4C, 0x72, 0x01, 0x72, 0x4C,\n\t0x30, 0x4A, 0x4D, 0x4D, 0x30,\n\t0x30, 0x48, 0x78, 0x48, 0x30,\n\t0xBC, 0x62, 0x5A, 0x46, 0x3D,\n\t0x3E, 0x49, 0x49, 0x49, 0x00,\n\t0x7E, 0x01, 0x01, 0x01, 0x7E,\n\t0x2A, 0x2A, 0x2A, 0x2A, 0x2A,\n\t0x44, 0x44, 0x5F, 0x44, 0x44,\n\t0x40, 0x51, 0x4A, 0x44, 0x40,\n\t0x40, 0x44, 0x4A, 0x51, 0x40,\n\t0x00, 0x00, 0xFF, 0x01, 0x03,\n\t0xE0, 0x80, 0xFF, 0x00, 0x00,\n\t0x08, 0x08, 0x6B, 0x6B, 0x08,\n\t0x36, 0x12, 0x36, 0x24, 0x36,\n\t0x06, 0x0F, 0x09, 0x0F, 0x06,\n\t0x00, 0x00, 0x18, 0x18, 0x00,\n\t0x00, 0x00, 0x10, 0x10, 0x00,\n\t0x30, 0x40, 0xFF, 0x01, 0x01,\n\t0x00, 0x1F, 0x01, 0x01, 0x1E,\n\t0x00, 0x19, 0x1D, 0x17, 0x12,\n\t0x00, 0x3C, 0x3C, 0x3C, 0x3C,\n\t0x00, 0x00, 0x00, 0x00, 0x00  // #255 NBSP\n};\n#endif // FONT5X7_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/library.properties",
    "content": "name=Adafruit GFX Library\nversion=1.2.3\nauthor=Adafruit\nmaintainer=Adafruit <info@adafruit.com>\nsentence=Adafruit GFX graphics core library, this is the 'core' class that all our other graphics libraries derive from.\nparagraph=Install this library in addition to the display library for your hardware.\ncategory=Display\nurl=https://github.com/adafruit/Adafruit-GFX-Library\narchitectures=*\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Adafruit_GFX_Library/license.txt",
    "content": "Software License Agreement (BSD License)\n\nCopyright (c) 2012 Adafruit Industries.  All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n- Redistributions of source code must retain the above copyright notice,\n  this list of conditions and the following disclaimer.\n- Redistributions in binary form must reproduce the above copyright notice,\n  this list of conditions and the following disclaimer in the documentation\n  and/or other materials provided with the distribution.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/CAN/CAN.cpp",
    "content": "#include \"CAN.h\"\n#include \"drv_can.h\"\n\nCANClass CanBus;\n\n#define OPENCR_CAN_CHANNEL 0 //CAN2\n\nCANClass::CANClass()\n{\n    format_ = CAN_STD_FORMAT;\n}\n\nbool CANClass::begin()\n{\n    return drvCanOpen(OPENCR_CAN_CHANNEL, CAN_BAUD_125K, format_);\n}\n\nbool CANClass::begin(uint32_t baudrate)\n{\n    return drvCanOpen(OPENCR_CAN_CHANNEL, baudrate, format_);\n}\n\nbool CANClass::begin(uint32_t baudrate, uint8_t format)\n{\n    return drvCanOpen(OPENCR_CAN_CHANNEL, baudrate, format);\n}\n\nvoid CANClass::end(void)\n{\n    drvCanClose(OPENCR_CAN_CHANNEL);\n}\n\n bool CANClass::configFilter(uint32_t id, uint32_t mask)\n {\n    return drvCanConfigFilter(0, id, mask, format_);\n }\n\n bool CANClass::configFilter(uint32_t id, uint32_t mask, uint8_t format)\n {\n    return drvCanConfigFilter(0, id, mask, format);\n }\n\nuint32_t CANClass::write(uint32_t id, uint8_t *p_data, uint32_t length)\n{\n    return drvCanWrite(OPENCR_CAN_CHANNEL, id, p_data, length, format_);\n}\n\nuint32_t CANClass::write(uint32_t id, uint8_t *p_data, uint32_t length, uint8_t format)\n{\n    return drvCanWrite(OPENCR_CAN_CHANNEL, id, p_data, length, format);\n}\n\nuint8_t CANClass::read(void)  //read one byte\n{\n    return drvCanRead(OPENCR_CAN_CHANNEL);\n}\n\nuint32_t  CANClass::available(void)\n{\n    return drvCanAvailable(OPENCR_CAN_CHANNEL); \n}\n\nuint32_t CANClass::writeMessage(can_message_t *p_msg)\n{\n    drv_can_msg_t msg;\n    msg.id = p_msg->id;\n    msg.format = p_msg->format;\n    msg.length = p_msg->length;\n    memcpy(msg.data, p_msg->data, 8);\n\n    return drvCanWriteMsg(OPENCR_CAN_CHANNEL, &msg);\n}\n\nbool CANClass::readMessage(can_message_t *p_msg)\n{\n    bool ret = false;\n    drv_can_msg_t *rx_msg;\n\n    rx_msg = drvCanReadMsg(OPENCR_CAN_CHANNEL);\n\n    if(rx_msg != NULL)\n    {\n        p_msg->id = rx_msg->id;\n        p_msg->format = rx_msg->format;\n        p_msg->length = rx_msg->length;\n\n        memcpy(p_msg->data, rx_msg->data, p_msg->length);\n\n        ret = true;\n    }\n\n    return ret;\n}\n\nuint32_t CANClass::availableMessage(void)\n{\n     return drvCanAvailableMsg(OPENCR_CAN_CHANNEL);\n}\n\nuint8_t CANClass::getErrCount(void)\n{\n    return drvCanGetErrCount(OPENCR_CAN_CHANNEL);\n}\nuint32_t CANClass::getError(void)\n{\n    return drvCanGetError(OPENCR_CAN_CHANNEL);\n}\n\nuint32_t CANClass::getState(void)\n{\n     return drvCanGetState(OPENCR_CAN_CHANNEL);\n}\n\nvoid CANClass::attachRxInterrupt(void (*handler)(can_message_t *arg))\n{\n    drvCanAttachRxInterrupt(OPENCR_CAN_CHANNEL, (void(*)(void *arg)) handler);\n}\n\nvoid CANClass::detachRxInterrupt(void)\n{\n    drvCanDetachRxInterrupt(OPENCR_CAN_CHANNEL);\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/CAN/CAN.h",
    "content": "#ifndef _BSP_CAN_H_\n#define _BSP_CAN_H_\n\n#include <chip.h>\n#include \"variant.h\"\n#include \"drv_can.h\"\n#include \"def.h\"\n\n#define CAN_STD_FORMAT            _DEF_CAN_STD\n#define CAN_EXT_FORMAT            _DEF_CAN_EXT\n\n#define CAN_BAUD_125K       _DEF_CAN_BAUD_125K\n#define CAN_BAUD_250K       _DEF_CAN_BAUD_250K\n#define CAN_BAUD_500K       _DEF_CAN_BAUD_500K\n#define CAN_BAUD_1000K      _DEF_CAN_BAUD_1000K\n\ntypedef struct can_message\n{\n    uint32_t id;\n    uint32_t length;\n    uint8_t  data[8];\n    uint8_t  format;\n}can_message_t;\n\nclass CANClass\n{\npublic:\n    CANClass();\n    bool begin();\n    bool begin(uint32_t baudrate);\n    bool begin(uint32_t baudrate, uint8_t format);\n    void end(void);\n    bool configFilter(uint32_t id, uint32_t mask);\n    bool configFilter(uint32_t id, uint32_t mask, uint8_t format);\n    uint32_t write(uint32_t id, uint8_t *p_data, uint32_t length);  //write data\n    uint32_t write(uint32_t id, uint8_t *p_data, uint32_t length, uint8_t format);\n    uint8_t read(void); //read one byte\n    uint32_t  available(void);\n    uint32_t writeMessage(can_message_t *p_msg);\n    bool readMessage(can_message_t *p_msg);\n    uint32_t availableMessage(void);\n\n    uint8_t getErrCount(void);\n    uint32_t getError(void);\n    uint32_t getState(void);\n\n    void attachRxInterrupt(void (*handler)(can_message_t *arg));\n    void detachRxInterrupt(void);\n\nprivate:\n    uint8_t format_;    \n};\n\nextern CANClass CanBus;\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelSDK/README.md",
    "content": ""
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelSDK/include/dynamixel_sdk/dynamixel_sdk.h",
    "content": "/*******************************************************************************\n* Copyright 2017 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n////////////////////////////////////////////////////////////////////////////////\n/// @file The file that includes whole Dynamixel SDK libraries\n/// @author Zerom, Leon (RyuWoon Jung)\n////////////////////////////////////////////////////////////////////////////////\n\n#ifndef DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_DYNAMIXELSDK_H_\n#define DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_DYNAMIXELSDK_H_\n\n\n#include \"group_bulk_read.h\"\n#include \"group_bulk_write.h\"\n#include \"group_sync_read.h\"\n#include \"group_sync_write.h\"\n#include \"packet_handler.h\"\n#include \"port_handler.h\"\n\n\n#endif /* DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_DYNAMIXELSDK_H_ */\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelSDK/include/dynamixel_sdk/group_bulk_read.h",
    "content": "/*******************************************************************************\n* Copyright 2017 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n////////////////////////////////////////////////////////////////////////////////\n/// @file The file for Dynamixel Bulk Read\n/// @author Zerom, Leon (RyuWoon Jung)\n////////////////////////////////////////////////////////////////////////////////\n\n#ifndef DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_GROUPBULKREAD_H_\n#define DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_GROUPBULKREAD_H_\n\n\n#include <map>\n#include <vector>\n#include \"port_handler.h\"\n#include \"packet_handler.h\"\n\nnamespace dynamixel\n{\n\n////////////////////////////////////////////////////////////////////////////////\n/// @brief The class for reading multiple Dynamixel data from different addresses with different lengths at once\n////////////////////////////////////////////////////////////////////////////////\nclass WINDECLSPEC GroupBulkRead\n{\n private:\n  PortHandler    *port_;\n  PacketHandler  *ph_;\n\n  std::vector<uint8_t>            id_list_;\n  std::map<uint8_t, uint16_t>     address_list_;  // <id, start_address>\n  std::map<uint8_t, uint16_t>     length_list_;   // <id, data_length>\n  std::map<uint8_t, uint8_t *>    data_list_;     // <id, data>\n  std::map<uint8_t, uint8_t *>    error_list_;    // <id, error>\n\n  bool            last_result_;\n  bool            is_param_changed_;\n\n  uint8_t        *param_;\n\n  void    makeParam();\n\n public:\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that Initializes instance for Bulk Read\n  /// @param port PortHandler instance\n  /// @param ph PacketHandler instance\n  ////////////////////////////////////////////////////////////////////////////////\n  GroupBulkRead(PortHandler *port, PacketHandler *ph);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls clearParam function to clear the parameter list for Bulk Read\n  ////////////////////////////////////////////////////////////////////////////////\n  ~GroupBulkRead() { clearParam(); }\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that returns PortHandler instance\n  /// @return PortHandler instance\n  ////////////////////////////////////////////////////////////////////////////////\n  PortHandler     *getPortHandler()   { return port_; }\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that returns PacketHandler instance\n  /// @return PacketHandler instance\n  ////////////////////////////////////////////////////////////////////////////////\n  PacketHandler   *getPacketHandler() { return ph_; }\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that adds id, start_address, data_length to the Bulk Read list\n  /// @param id Dynamixel ID\n  /// @param start_address Address of the data for read\n  /// @data_length Length of the data for read\n  /// @return false\n  /// @return   when the ID exists already in the list\n  /// @return or true\n  ////////////////////////////////////////////////////////////////////////////////\n  bool    addParam    (uint8_t id, uint16_t start_address, uint16_t data_length);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that removes id from the Bulk Read list\n  /// @param id Dynamixel ID\n  ////////////////////////////////////////////////////////////////////////////////\n  void    removeParam (uint8_t id);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that clears the Bulk Read list\n  ////////////////////////////////////////////////////////////////////////////////\n  void    clearParam  ();\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits the Bulk Read instruction packet which might be constructed by GroupBulkRead::addParam function\n  /// @return COMM_NOT_AVAILABLE\n  /// @return   when the list for Bulk Read is empty\n  /// @return or the other communication results which come from PacketHandler::bulkReadTx\n  ////////////////////////////////////////////////////////////////////////////////\n  int     txPacket();\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that receives the packet which might be come from the Dynamixel\n  /// @return COMM_NOT_AVAILABLE\n  /// @return   when the list for Bulk Read is empty\n  /// @return COMM_RX_FAIL\n  /// @return   when there is no packet recieved\n  /// @return COMM_SUCCESS\n  /// @return   when there is packet recieved\n  /// @return or the other communication results\n  ////////////////////////////////////////////////////////////////////////////////\n  int     rxPacket();\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits and receives the packet which might be come from the Dynamixel\n  /// @return COMM_RX_FAIL\n  /// @return   when there is no packet recieved\n  /// @return COMM_SUCCESS\n  /// @return   when there is packet recieved\n  /// @return or the other communication results which come from GroupBulkRead::txPacket or GroupBulkRead::rxPacket\n  ////////////////////////////////////////////////////////////////////////////////\n  int     txRxPacket();\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that checks whether there are available data which might be received by GroupBulkRead::rxPacket or GroupBulkRead::txRxPacket\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for read\n  /// @param data_length Length of the data for read\n  /// @return false\n  /// @return  when there are no data available\n  /// @return or true\n  ////////////////////////////////////////////////////////////////////////////////\n  bool        isAvailable (uint8_t id, uint16_t address, uint16_t data_length);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that gets the data which might be received by GroupBulkRead::rxPacket or GroupBulkRead::txRxPacket\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for read\n  /// @data_length Length of the data for read\n  /// @return data value\n  ////////////////////////////////////////////////////////////////////////////////\n  uint32_t    getData     (uint8_t id, uint16_t address, uint16_t data_length);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that gets the error which might be received by GroupBulkRead::rxPacket or GroupBulkRead::txRxPacket\n  /// @param id Dynamixel ID\n  /// @error error of Dynamixel\n  /// @return true\n  /// @return   when Dynamixel returned specific error byte\n  /// @return or false \n  ////////////////////////////////////////////////////////////////////////////////\n  bool        getError    (uint8_t id, uint8_t* error);\n};\n\n}\n\n\n#endif /* DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_GROUPBULKREAD_H_ */\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelSDK/include/dynamixel_sdk/group_bulk_write.h",
    "content": "/*******************************************************************************\n* Copyright 2017 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n////////////////////////////////////////////////////////////////////////////////\n/// @file The file for Dynamixel Bulk Write\n/// @author Zerom, Leon (RyuWoon Jung)\n////////////////////////////////////////////////////////////////////////////////\n\n#ifndef DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_GROUPBULKWRITE_H_\n#define DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_GROUPBULKWRITE_H_\n\n\n#include <map>\n#include <vector>\n#include \"port_handler.h\"\n#include \"packet_handler.h\"\n\nnamespace dynamixel\n{\n\n////////////////////////////////////////////////////////////////////////////////\n/// @brief The class for writing multiple Dynamixel data from different addresses with different lengths at once\n////////////////////////////////////////////////////////////////////////////////\nclass WINDECLSPEC GroupBulkWrite\n{\n private:\n  PortHandler    *port_;\n  PacketHandler  *ph_;\n\n  std::vector<uint8_t>            id_list_;\n  std::map<uint8_t, uint16_t>     address_list_;  // <id, start_address>\n  std::map<uint8_t, uint16_t>     length_list_;   // <id, data_length>\n  std::map<uint8_t, uint8_t *>    data_list_;     // <id, data>\n\n  bool            is_param_changed_;\n\n  uint8_t        *param_;\n  uint16_t        param_length_;\n\n  void    makeParam();\n\n public:\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that Initializes instance for Bulk Write\n  /// @param port PortHandler instance\n  /// @param ph PacketHandler instance\n  ////////////////////////////////////////////////////////////////////////////////\n  GroupBulkWrite(PortHandler *port, PacketHandler *ph);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls clearParam function to clear the parameter list for Bulk Write\n  ////////////////////////////////////////////////////////////////////////////////\n  ~GroupBulkWrite() { clearParam(); }\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that returns PortHandler instance\n  /// @return PortHandler instance\n  ////////////////////////////////////////////////////////////////////////////////\n  PortHandler     *getPortHandler()   { return port_; }\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that returns PacketHandler instance\n  /// @return PacketHandler instance\n  ////////////////////////////////////////////////////////////////////////////////\n  PacketHandler   *getPacketHandler() { return ph_; }\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that adds id, start_address, data_length to the Bulk Write list\n  /// @param id Dynamixel ID\n  /// @param start_address Address of the data for write\n  /// @param data_length Length of the data for write\n  /// @return false\n  /// @return   when the ID exists already in the list\n  /// @return or true\n  ////////////////////////////////////////////////////////////////////////////////\n  bool    addParam    (uint8_t id, uint16_t start_address, uint16_t data_length, uint8_t *data);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that removes id from the Bulk Write list\n  /// @param id Dynamixel ID\n  ////////////////////////////////////////////////////////////////////////////////\n  void    removeParam (uint8_t id);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that changes the data for write in id -> start_address -> data_length to the Bulk Write list\n  /// @param id Dynamixel ID\n  /// @param start_address Address of the data for write\n  /// @param data_length Length of the data for write\n  /// @param data for replacement\n  /// @return false\n  /// @return   when the ID doesn't exist in the list\n  /// @return or true\n  ////////////////////////////////////////////////////////////////////////////////\n  bool    changeParam (uint8_t id, uint16_t start_address, uint16_t data_length, uint8_t *data);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that clears the Bulk Write list\n  ////////////////////////////////////////////////////////////////////////////////\n  void    clearParam  ();\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits the Bulk Write instruction packet which might be constructed by GroupBulkWrite::addParam function\n  /// @return COMM_NOT_AVAILABLE\n  /// @return   when the list for Bulk Write is empty\n  /// @return   when Protocol1.0 has been used\n  /// @return or the other communication results which come from PacketHandler::bulkWriteTxOnly\n  ////////////////////////////////////////////////////////////////////////////////\n  int     txPacket();\n};\n\n}\n\n\n#endif /* DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_GROUPBULKWRITE_H_ */\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelSDK/include/dynamixel_sdk/group_sync_read.h",
    "content": "/*******************************************************************************\n* Copyright 2017 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n////////////////////////////////////////////////////////////////////////////////\n/// @file The file for Dynamixel Sync Read\n/// @author Zerom, Leon (RyuWoon Jung)\n////////////////////////////////////////////////////////////////////////////////\n\n#ifndef DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_GROUPSYNCREAD_H_\n#define DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_GROUPSYNCREAD_H_\n\n\n#include <map>\n#include <vector>\n#include \"port_handler.h\"\n#include \"packet_handler.h\"\n\nnamespace dynamixel\n{\n\n////////////////////////////////////////////////////////////////////////////////\n/// @brief The class for reading multiple Dynamixel data from same address with same length at once\n////////////////////////////////////////////////////////////////////////////////\nclass WINDECLSPEC GroupSyncRead\n{\n private:\n  PortHandler    *port_;\n  PacketHandler  *ph_;\n\n  std::vector<uint8_t>            id_list_;\n  std::map<uint8_t, uint8_t *>    data_list_;  // <id, data>\n  std::map<uint8_t, uint8_t *>    error_list_; // <id, error>\n\n  bool            last_result_;\n  bool            is_param_changed_;\n\n  uint8_t        *param_;\n  uint16_t        start_address_;\n  uint16_t        data_length_;\n\n  void    makeParam();\n\n public:\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that Initializes instance for Sync Read\n  /// @param port PortHandler instance\n  /// @param ph PacketHandler instance\n  /// @param start_address Address of the data for read\n  /// @param data_length Length of the data for read\n  ////////////////////////////////////////////////////////////////////////////////\n  GroupSyncRead(PortHandler *port, PacketHandler *ph, uint16_t start_address, uint16_t data_length);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls clearParam function to clear the parameter list for Sync Read\n  ////////////////////////////////////////////////////////////////////////////////\n  ~GroupSyncRead() { clearParam(); }\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that returns PortHandler instance\n  /// @return PortHandler instance\n  ////////////////////////////////////////////////////////////////////////////////\n  PortHandler     *getPortHandler()   { return port_; }\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that returns PacketHandler instance\n  /// @return PacketHandler instance\n  ////////////////////////////////////////////////////////////////////////////////\n  PacketHandler   *getPacketHandler() { return ph_; }\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that adds id, start_address, data_length to the Sync Read list\n  /// @param id Dynamixel ID\n  /// @return false\n  /// @return   when the ID exists already in the list\n  /// @return   when the protocol1.0 has been used\n  /// @return or true\n  ////////////////////////////////////////////////////////////////////////////////\n  bool    addParam    (uint8_t id);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that removes id from the Sync Read list\n  /// @param id Dynamixel ID\n  ////////////////////////////////////////////////////////////////////////////////\n  void    removeParam (uint8_t id);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that clears the Sync Read list\n  ////////////////////////////////////////////////////////////////////////////////\n  void    clearParam  ();\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits the Sync Read instruction packet which might be constructed by GroupSyncRead::addParam function\n  /// @return COMM_NOT_AVAILABLE\n  /// @return   when the list for Sync Read is empty\n  /// @return   when the protocol1.0 has been used\n  /// @return or the other communication results which come from PacketHandler::syncReadTx\n  ////////////////////////////////////////////////////////////////////////////////\n  int     txPacket();\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that receives the packet which might be come from the Dynamixel\n  /// @return COMM_NOT_AVAILABLE\n  /// @return   when the list for Sync Read is empty\n  /// @return   when the protocol1.0 has been used\n  /// @return COMM_SUCCESS\n  /// @return   when there is packet recieved\n  /// @return or the other communication results\n  ////////////////////////////////////////////////////////////////////////////////\n  int     rxPacket();\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits and receives the packet which might be come from the Dynamixel\n  /// @return COMM_NOT_AVAILABLE\n  /// @return   when the protocol1.0 has been used\n  /// @return COMM_RX_FAIL\n  /// @return   when there is no packet recieved\n  /// @return COMM_SUCCESS\n  /// @return   when there is packet recieved\n  /// @return or the other communication results which come from GroupBulkRead::txPacket or GroupBulkRead::rxPacket\n  ////////////////////////////////////////////////////////////////////////////////\n  int     txRxPacket();\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that checks whether there are available data which might be received by GroupSyncRead::rxPacket or GroupSyncRead::txRxPacket\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for read\n  /// @param data_length Length of the data for read\n  /// @return false\n  /// @return   when there are no data available\n  /// @return   when the protocol1.0 has been used\n  /// @return or true\n  ////////////////////////////////////////////////////////////////////////////////\n  bool        isAvailable (uint8_t id, uint16_t address, uint16_t data_length);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that gets the data which might be received by GroupSyncRead::rxPacket or GroupSyncRead::txRxPacket\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for read\n  /// @data_length Length of the data for read\n  /// @return data value\n  ////////////////////////////////////////////////////////////////////////////////\n  uint32_t    getData     (uint8_t id, uint16_t address, uint16_t data_length);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that gets the error which might be received by GroupSyncRead::rxPacket or GroupSyncRead::txRxPacket\n  /// @param id Dynamixel ID\n  /// @error error of Dynamixel\n  /// @return true\n  /// @return   when Dynamixel returned specific error byte\n  /// @return or false \n  ////////////////////////////////////////////////////////////////////////////////\n  bool        getError    (uint8_t id, uint8_t* error);\n};\n\n}\n\n\n#endif /* DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_GROUPSYNCREAD_H_ */\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelSDK/include/dynamixel_sdk/group_sync_write.h",
    "content": "/*******************************************************************************\n* Copyright 2017 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n////////////////////////////////////////////////////////////////////////////////\n/// @file The file for Dynamixel Sync Write\n/// @author Zerom, Leon (RyuWoon Jung)\n////////////////////////////////////////////////////////////////////////////////\n\n#ifndef DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_GROUPSYNCWRITE_H_\n#define DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_GROUPSYNCWRITE_H_\n\n\n#include <map>\n#include <vector>\n#include \"port_handler.h\"\n#include \"packet_handler.h\"\n\nnamespace dynamixel\n{\n\n////////////////////////////////////////////////////////////////////////////////\n/// @brief The class for writing multiple Dynamixel data from same address with same length at once\n////////////////////////////////////////////////////////////////////////////////\nclass WINDECLSPEC GroupSyncWrite\n{\n private:\n  PortHandler    *port_;\n  PacketHandler  *ph_;\n\n  std::vector<uint8_t>            id_list_;\n  std::map<uint8_t, uint8_t* >    data_list_; // <id, data>\n\n  bool            is_param_changed_;\n\n  uint8_t        *param_;\n  uint16_t        start_address_;\n  uint16_t        data_length_;\n\n  void    makeParam();\n\n public:\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that Initializes instance for Sync Write\n  /// @param port PortHandler instance\n  /// @param ph PacketHandler instance\n  /// @param start_address Address of the data for write\n  /// @param data_length Length of the data for write\n  ////////////////////////////////////////////////////////////////////////////////\n  GroupSyncWrite(PortHandler *port, PacketHandler *ph, uint16_t start_address, uint16_t data_length);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls clearParam function to clear the parameter list for Sync Write\n  ////////////////////////////////////////////////////////////////////////////////\n  ~GroupSyncWrite() { clearParam(); }\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that returns PortHandler instance\n  /// @return PortHandler instance\n  ////////////////////////////////////////////////////////////////////////////////\n  PortHandler     *getPortHandler()   { return port_; }\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that returns PacketHandler instance\n  /// @return PacketHandler instance\n  ////////////////////////////////////////////////////////////////////////////////\n  PacketHandler   *getPacketHandler() { return ph_; }\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that adds id, start_address, data_length to the Sync Write list\n  /// @param id Dynamixel ID\n  /// @param data Data for write\n  /// @return false\n  /// @return   when the ID exists already in the list\n  /// @return or true\n  ////////////////////////////////////////////////////////////////////////////////\n  bool    addParam    (uint8_t id, uint8_t *data);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that removes id from the Sync Write list\n  /// @param id Dynamixel ID\n  ////////////////////////////////////////////////////////////////////////////////\n  void    removeParam (uint8_t id);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that changes the data for write in id -> start_address -> data_length to the Sync Write list\n  /// @param id Dynamixel ID\n  /// @param data for replacement\n  /// @return false\n  /// @return   when the ID doesn't exist in the list\n  /// @return or true\n  ////////////////////////////////////////////////////////////////////////////////\n  bool    changeParam (uint8_t id, uint8_t *data);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that clears the Sync Write list\n  ////////////////////////////////////////////////////////////////////////////////\n  void    clearParam  ();\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits the Sync Write instruction packet which might be constructed by GroupSyncWrite::addParam function\n  /// @return COMM_NOT_AVAILABLE\n  /// @return   when the list for Sync Write is empty\n  /// @return or the other communication results which come from PacketHandler::syncWriteTxOnly\n  ////////////////////////////////////////////////////////////////////////////////\n  int     txPacket();\n};\n\n}\n\n\n#endif /* DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_GROUPSYNCWRITE_H_ */\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelSDK/include/dynamixel_sdk/packet_handler.h",
    "content": "/*******************************************************************************\n* Copyright 2017 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n////////////////////////////////////////////////////////////////////////////////\n/// @file The file for Dynamixel packet control\n/// @author Zerom, Leon (RyuWoon Jung)\n////////////////////////////////////////////////////////////////////////////////\n\n#ifndef DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_PACKETHANDLER_H_\n#define DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_PACKETHANDLER_H_\n\n#if defined(ARDUINO) || defined(__OPENCR__) || defined(__OPENCM904__)\n#include <Arduino.h>\n\n#define ERROR_PRINT  SerialBT2.print\t\n#else\t\n#define ERROR_PRINT  printf\n\n#endif\n\n#include <stdio.h>\n#include <vector>\n#include \"port_handler.h\"\n\n#define BROADCAST_ID        0xFE    // 254\n#define MAX_ID              0xFC    // 252\n\n/* Macro for Control Table Value */\n#define DXL_MAKEWORD(a, b)  ((uint16_t)(((uint8_t)(((uint64_t)(a)) & 0xff)) | ((uint16_t)((uint8_t)(((uint64_t)(b)) & 0xff))) << 8))\n#define DXL_MAKEDWORD(a, b) ((uint32_t)(((uint16_t)(((uint64_t)(a)) & 0xffff)) | ((uint32_t)((uint16_t)(((uint64_t)(b)) & 0xffff))) << 16))\n#define DXL_LOWORD(l)       ((uint16_t)(((uint64_t)(l)) & 0xffff))\n#define DXL_HIWORD(l)       ((uint16_t)((((uint64_t)(l)) >> 16) & 0xffff))\n#define DXL_LOBYTE(w)       ((uint8_t)(((uint64_t)(w)) & 0xff))\n#define DXL_HIBYTE(w)       ((uint8_t)((((uint64_t)(w)) >> 8) & 0xff))\n\n/* Instruction for DXL Protocol */\n#define INST_PING               1\n#define INST_READ               2\n#define INST_WRITE              3\n#define INST_REG_WRITE          4\n#define INST_ACTION             5\n#define INST_FACTORY_RESET      6\n#define INST_SYNC_WRITE         131     // 0x83\n#define INST_BULK_READ          146     // 0x92\n// --- Only for 2.0 --- //\n#define INST_REBOOT             8\n#define INST_CLEAR              16      // 0x10\n#define INST_STATUS             85      // 0x55\n#define INST_SYNC_READ          130     // 0x82\n#define INST_BULK_WRITE         147     // 0x93\n\n// Communication Result\n#define COMM_SUCCESS        0       // tx or rx packet communication success\n#define COMM_PORT_BUSY      -1000   // Port is busy (in use)\n#define COMM_TX_FAIL        -1001   // Failed transmit instruction packet\n#define COMM_RX_FAIL        -1002   // Failed get status packet\n#define COMM_TX_ERROR       -2000   // Incorrect instruction packet\n#define COMM_RX_WAITING     -3000   // Now recieving status packet\n#define COMM_RX_TIMEOUT     -3001   // There is no status packet\n#define COMM_RX_CORRUPT     -3002   // Incorrect status packet\n#define COMM_NOT_AVAILABLE  -9000   //\n\nnamespace dynamixel\n{\n\n////////////////////////////////////////////////////////////////////////////////\n/// @brief The class that inherits Protocol1PacketHandler class or Protocol2PacketHandler class\n////////////////////////////////////////////////////////////////////////////////\nclass WINDECLSPEC PacketHandler\n{\n protected:\n  PacketHandler() { }\n\n public:\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that returns PacketHandler instance\n  /// @return PacketHandler instance\n  ////////////////////////////////////////////////////////////////////////////////\n  static PacketHandler *getPacketHandler(float protocol_version = 2.0);\n\n  virtual ~PacketHandler() { }\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that returns Protocol version\n  /// @return protocol version\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual float   getProtocolVersion() = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that gets description of communication result\n  /// @param result Communication result which might be gotten by the tx rx functions\n  /// @return description of communication result in const char* (string)\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual const char *getTxRxResult     (int result) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that gets description of hardware error\n  /// @param error Dynamixel hardware error which might be gotten by the tx rx functions\n  /// @return description of hardware error in const char* (string)\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual const char *getRxPacketError  (uint8_t error) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits the instruction packet txpacket via PortHandler port.\n  /// @description The function clears the port buffer by PortHandler::clearPort() function,\n  /// @description   then transmits txpacket by PortHandler::writePort() function.\n  /// @description The function activates only when the port is not busy and when the packet is already written on the port buffer\n  /// @param port PortHandler instance\n  /// @param txpacket packet for transmission\n  /// @return COMM_PORT_BUSY\n  /// @return   when the port is already in use\n  /// @return COMM_TX_ERROR\n  /// @return   when txpacket is out of range described by TXPACKET_MAX_LEN\n  /// @return COMM_TX_FAIL\n  /// @return   when written packet is shorter than expected\n  /// @return or COMM_SUCCESS\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int txPacket        (PortHandler *port, uint8_t *txpacket) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that receives packet (rxpacket) during designated time via PortHandler port\n  /// @description The function repeatedly tries to receive rxpacket by PortHandler::readPort() function.\n  /// @description It breaks out\n  /// @description when PortHandler::isPacketTimeout() shows the timeout,\n  /// @description when rxpacket seemed as corrupted, or\n  /// @description when nothing received\n  /// @param port PortHandler instance\n  /// @param rxpacket received packet\n  /// @return COMM_RX_CORRUPT\n  /// @return   when it received the packet but it couldn't find header in the packet\n  /// @return   when it found header in the packet but the id, length or error value is out of range\n  /// @return   when it received the packet but it is shorted than expected\n  /// @return COMM_RX_TIMEOUT\n  /// @return   when there is no rxpacket received until PortHandler::isPacketTimeout() shows the timeout\n  /// @return COMM_SUCCESS\n  /// @return   when rxpacket passes checksum test\n  /// @return or COMM_RX_FAIL\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int rxPacket        (PortHandler *port, uint8_t *rxpacket) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits packet (txpacket) and receives packet (rxpacket) during designated time via PortHandler port\n  /// @description The function calls PacketHandler::txPacket(),\n  /// @description and calls PacketHandler::rxPacket() if it succeeds PacketHandler::txPacket().\n  /// @description It breaks out\n  /// @description when it fails PacketHandler::txPacket(),\n  /// @description when txpacket is called by PacketHandler::broadcastPing() / PacketHandler::syncWriteTxOnly() / PacketHandler::regWriteTxOnly / PacketHandler::action\n  /// @param port PortHandler instance\n  /// @param txpacket packet for transmission\n  /// @param rxpacket received packet\n  /// @return COMM_SUCCESS\n  /// @return   when it succeeds PacketHandler::txPacket() and PacketHandler::rxPacket()\n  /// @return or the other communication results which come from PacketHandler::txPacket() and PacketHandler::rxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int txRxPacket      (PortHandler *port, uint8_t *txpacket, uint8_t *rxpacket, uint8_t *error = 0) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that pings Dynamixel but doesn't take its model number\n  /// @description The function calls PacketHandler::ping() which gets Dynamixel model number,\n  /// @description but doesn't carry the model number\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from PacketHandler::ping()\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int ping            (PortHandler *port, uint8_t id, uint8_t *error = 0) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that pings Dynamixel and takes its model number\n  /// @description The function makes an instruction packet with INST_PING,\n  /// @description transmits the packet with PacketHandler::txRxPacket(),\n  /// @description and call PacketHandler::readTxRx to read model_number in the rx buffer.\n  /// @description It breaks out\n  /// @description when it tries to transmit to BROADCAST_ID\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param error Dynamixel hardware error\n  /// @return COMM_NOT_AVAILABLE\n  /// @return   when it tries to transmit to BROADCAST_ID\n  /// @return COMM_SUCCESS\n  /// @return   when it succeeds to ping Dynamixel and get model_number from it\n  /// @return or the other communication results which come from PacketHandler::txRxPacket() and PacketHandler::readTxRx()\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int ping            (PortHandler *port, uint8_t id, uint16_t *model_number, uint8_t *error = 0) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief (Available only in Protocol 2.0) The function that pings all connected Dynamixel\n  /// @param port PortHandler instance\n  /// @param id_list ID list of Dynamixels which are found by broadcast ping\n  /// @return COMM_NOT_AVAILABLE\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int broadcastPing   (PortHandler *port, std::vector<uint8_t> &id_list) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that makes Dynamixels run as written in the Dynamixel register\n  /// @description The function makes an instruction packet with INST_ACTION,\n  /// @description transmits the packet with PacketHandler::txRxPacket().\n  /// @description To use this function, Dynamixel register should be set by PacketHandler::regWriteTxOnly() or PacketHandler::regWriteTxRx()\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @return communication results which come from PacketHandler::txRxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int action          (PortHandler *port, uint8_t id) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that makes Dynamixel reboot\n  /// @description The function makes an instruction packet with INST_REBOOT,\n  /// @description transmits the packet with PacketHandler::txRxPacket(),\n  /// @description then Dynamixel reboots.\n  /// @description During reboot, its LED will blink.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param error Dynamixel hardware error\n  /// @return COMM_NOT_AVAILABLE\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int reboot          (PortHandler *port, uint8_t id, uint8_t *error = 0) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that reset multi-turn revolution information of Dynamixel\n  /// @description The function makes an instruction packet with INST_CLEAR,\n  /// @description transmits the packet with PacketHandler::txRxPacket().\n  /// @description Applied Products : MX with Protocol 2.0 (Firmware v42 or above),\n  /// @description Dynamixel X-series (Firmware v42 or above).\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from PacketHandler::txRxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int clearMultiTurn  (PortHandler *port, uint8_t id, uint8_t *error = 0) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that makes Dynamixel reset as it was produced in the factory\n  /// @description The function makes an instruction packet with INST_FACTORY_RESET,\n  /// @description transmits the packet with PacketHandler::txRxPacket().\n  /// @description Be careful of the use.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param option Reset option\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from PacketHandler::txRxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int factoryReset    (PortHandler *port, uint8_t id, uint8_t option = 0, uint8_t *error = 0) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits INST_READ instruction packet\n  /// @description The function makes an instruction packet with INST_READ,\n  /// @description transmits the packet with PacketHandler::txPacket().\n  /// @description It breaks out\n  /// @description when it tries to transmit to BROADCAST_ID\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for read\n  /// @param length Length of the data for read\n  /// @return COMM_NOT_AVAILABLE\n  /// @return   when it tries to transmit to BROADCAST_ID\n  /// @return or the other communication results which come from PacketHandler::txPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int readTx          (PortHandler *port, uint8_t id, uint16_t address, uint16_t length) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that receives the packet and reads the data in the packet\n  /// @description The function receives the packet which might be come by previous INST_READ instruction packet transmission,\n  /// @description gets the data from the packet.\n  /// @param port PortHandler instance\n  /// @param length Length of the data for read\n  /// @param data Data extracted from the packet\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from PacketHandler::rxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int readRx          (PortHandler *port, uint8_t id, uint16_t length, uint8_t *data, uint8_t *error = 0) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits INST_READ instruction packet, and read data from received packet\n  /// @description The function makes an instruction packet with INST_READ,\n  /// @description transmits and receives the packet with PacketHandler::txRxPacket(),\n  /// @description gets the data from the packet.\n  /// @description It breaks out\n  /// @description when it tries to transmit to BROADCAST_ID\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for read\n  /// @param length Length of the data for read\n  /// @param data Data extracted from the packet\n  /// @param error Dynamixel hardware error\n  /// @return COMM_NOT_AVAILABLE\n  /// @return   when it tries to transmit to BROADCAST_ID\n  /// @return or the other communication results which come from PacketHandler::txRxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int readTxRx        (PortHandler *port, uint8_t id, uint16_t address, uint16_t length, uint8_t *data, uint8_t *error = 0) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls PacketHandler::readTx() function for reading 1 byte data\n  /// @description The function calls PacketHandler::readTx() function for reading 1 byte data\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for read\n  /// @return communication results which come from PacketHandler::readTx()\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int read1ByteTx     (PortHandler *port, uint8_t id, uint16_t address) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls PacketHandler::readRx() function and reads 1 byte data on the packet\n  /// @description The function calls PacketHandler::readRx() function,\n  /// @description gets 1 byte data from the packet.\n  /// @param port PortHandler instance\n  /// @param data Data extracted from the packet\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from PacketHandler::readRx()\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int read1ByteRx     (PortHandler *port, uint8_t id, uint8_t *data, uint8_t *error = 0) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls PacketHandler::readTxRx() function for reading 1 byte data\n  /// @description The function calls PacketHandler::readTxRx(),\n  /// @description gets 1 byte data from the packet.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for read\n  /// @param length Length of the data for read\n  /// @param data Data extracted from the packet\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from PacketHandler::txRxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int read1ByteTxRx   (PortHandler *port, uint8_t id, uint16_t address, uint8_t *data, uint8_t *error = 0) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls PacketHandler::readTx() function for reading 2 byte data\n  /// @description The function calls PacketHandler::readTx() function for reading 2 byte data\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for read\n  /// @return communication results which come from PacketHandler::readTx()\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int read2ByteTx     (PortHandler *port, uint8_t id, uint16_t address) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls PacketHandler::readRx() function and reads 2 byte data on the packet\n  /// @description The function calls PacketHandler::readRx() function,\n  /// @description gets 2 byte data from the packet.\n  /// @param port PortHandler instance\n  /// @param data Data extracted from the packet\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from PacketHandler::readRx()\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int read2ByteRx     (PortHandler *port, uint8_t id, uint16_t *data, uint8_t *error = 0) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls PacketHandler::readTxRx() function for reading 2 byte data\n  /// @description The function calls PacketHandler::readTxRx(),\n  /// @description gets 2 byte data from the packet.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for read\n  /// @param length Length of the data for read\n  /// @param data Data extracted from the packet\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from PacketHandler::txRxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int read2ByteTxRx   (PortHandler *port, uint8_t id, uint16_t address, uint16_t *data, uint8_t *error = 0) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls PacketHandler::readTx() function for reading 4 byte data\n  /// @description The function calls PacketHandler::readTx() function for reading 4 byte data\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for read\n  /// @return communication results which come from PacketHandler::readTx()\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int read4ByteTx     (PortHandler *port, uint8_t id, uint16_t address) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls PacketHandler::readRx() function and reads 4 byte data on the packet\n  /// @description The function calls PacketHandler::readRx() function,\n  /// @description gets 4 byte data from the packet.\n  /// @param port PortHandler instance\n  /// @param data Data extracted from the packet\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from PacketHandler::readRx()\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int read4ByteRx     (PortHandler *port, uint8_t id, uint32_t *data, uint8_t *error = 0) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls PacketHandler::readTxRx() function for reading 4 byte data\n  /// @description The function calls PacketHandler::readTxRx(),\n  /// @description gets 4 byte data from the packet.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for read\n  /// @param length Length of the data for read\n  /// @param data Data extracted from the packet\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from PacketHandler::txRxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int read4ByteTxRx   (PortHandler *port, uint8_t id, uint16_t address, uint32_t *data, uint8_t *error = 0) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits INST_WRITE instruction packet with the data for write\n  /// @description The function makes an instruction packet with INST_WRITE and the data for write,\n  /// @description transmits the packet with PacketHandler::txPacket().\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for write\n  /// @param length Length of the data for write\n  /// @param data Data for write\n  /// @return communication results which come from PacketHandler::txPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int writeTxOnly     (PortHandler *port, uint8_t id, uint16_t address, uint16_t length, uint8_t *data) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits INST_WRITE instruction packet with the data for write, and receives the packet\n  /// @description The function makes an instruction packet with INST_WRITE and the data for write,\n  /// @description transmits and receives the packet with PacketHandler::txRxPacket(),\n  /// @description gets the error from the packet.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for write\n  /// @param length Length of the data for write\n  /// @param data Data for write\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from PacketHandler::txRxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int writeTxRx       (PortHandler *port, uint8_t id, uint16_t address, uint16_t length, uint8_t *data, uint8_t *error = 0) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls PacketHandler::writeTxOnly() for writing 1 byte data\n  /// @description The function calls PacketHandler::writeTxOnly() for writing 1 byte data.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for write\n  /// @param data Data for write\n  /// @return communication results which come from PacketHandler::writeTxOnly()\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int write1ByteTxOnly(PortHandler *port, uint8_t id, uint16_t address, uint8_t data) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls PacketHandler::writeTxRx() for writing 1 byte data and receives the packet\n  /// @description The function calls PacketHandler::writeTxRx() for writing 1 byte data and receves the packet,\n  /// @description gets the error from the packet.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for write\n  /// @param data Data for write\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from PacketHandler::writeTxRx()\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int write1ByteTxRx  (PortHandler *port, uint8_t id, uint16_t address, uint8_t data, uint8_t *error = 0) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls PacketHandler::writeTxOnly() for writing 2 byte data\n  /// @description The function calls PacketHandler::writeTxOnly() for writing 2 byte data.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for write\n  /// @param data Data for write\n  /// @return communication results which come from PacketHandler::writeTxOnly()\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int write2ByteTxOnly(PortHandler *port, uint8_t id, uint16_t address, uint16_t data) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls PacketHandler::writeTxRx() for writing 2 byte data and receives the packet\n  /// @description The function calls PacketHandler::writeTxRx() for writing 2 byte data and receves the packet,\n  /// @description gets the error from the packet.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for write\n  /// @param data Data for write\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from PacketHandler::writeTxRx()\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int write2ByteTxRx  (PortHandler *port, uint8_t id, uint16_t address, uint16_t data, uint8_t *error = 0) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls PacketHandler::writeTxOnly() for writing 4 byte data\n  /// @description The function calls PacketHandler::writeTxOnly() for writing 4 byte data.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for write\n  /// @param data Data for write\n  /// @return communication results which come from PacketHandler::writeTxOnly()\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int write4ByteTxOnly(PortHandler *port, uint8_t id, uint16_t address, uint32_t data) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls PacketHandler::writeTxRx() for writing 4 byte data and receives the packet\n  /// @description The function calls PacketHandler::writeTxRx() for writing 4 byte data and receves the packet,\n  /// @description gets the error from the packet.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for write\n  /// @param data Data for write\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from PacketHandler::writeTxRx()\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int write4ByteTxRx  (PortHandler *port, uint8_t id, uint16_t address, uint32_t data, uint8_t *error = 0) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits INST_REG_WRITE instruction packet with the data for writing on the Dynamixel register\n  /// @description The function makes an instruction packet with INST_REG_WRITE and the data for writing on the Dynamixel register,\n  /// @description transmits the packet with PacketHandler::txPacket().\n  /// @description The data written in the register will act when INST_ACTION instruction packet is transmitted to the Dynamxel.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for write\n  /// @param length Length of the data for write\n  /// @param data Data for write\n  /// @return communication results which come from PacketHandler::txPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int regWriteTxOnly  (PortHandler *port, uint8_t id, uint16_t address, uint16_t length, uint8_t *data) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits INST_REG_WRITE instruction packet with the data for writing on the Dynamixel register, and receives the packet\n  /// @description The function makes an instruction packet with INST_REG_WRITE and the data for writing on the Dynamixel register,\n  /// @description transmits and receives the packet with PacketHandler::txRxPacket(),\n  /// @description gets the error from the packet.\n  /// @description The data written in the register will act when INST_ACTION instruction packet is transmitted to the Dynamxel.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for write\n  /// @param length Length of the data for write\n  /// @param data Data for write\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from PacketHandler::txRxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int regWriteTxRx    (PortHandler *port, uint8_t id, uint16_t address, uint16_t length, uint8_t *data, uint8_t *error = 0) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits INST_SYNC_READ instruction packet\n  /// @description The function makes an instruction packet with INST_SYNC_READ,\n  /// @description transmits the packet with PacketHandler::txPacket().\n  /// @param port PortHandler instance\n  /// @param start_address Address of the data for Sync Read\n  /// @param data_length Length of the data for Sync Read\n  /// @param param Parameter for Sync Read\n  /// @param param_length Length of the data for Sync Read\n  /// @return communication results which come from PacketHandler::txPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int syncReadTx      (PortHandler *port, uint16_t start_address, uint16_t data_length, uint8_t *param, uint16_t param_length) = 0;\n  // SyncReadRx   -> GroupSyncRead class\n  // SyncReadTxRx -> GroupSyncRead class\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits INST_SYNC_WRITE instruction packet\n  /// @description The function makes an instruction packet with INST_SYNC_WRITE,\n  /// @description transmits the packet with PacketHandler::txRxPacket().\n  /// @param port PortHandler instance\n  /// @param start_address Address of the data for Sync Write\n  /// @param data_length Length of the data for Sync Write\n  /// @param param Parameter for Sync Write\n  /// @param param_length Length of the data for Sync Write\n  /// @return communication results which come from PacketHandler::txRxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int syncWriteTxOnly (PortHandler *port, uint16_t start_address, uint16_t data_length, uint8_t *param, uint16_t param_length) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits INST_BULK_READ instruction packet\n  /// @description The function makes an instruction packet with INST_BULK_READ,\n  /// @description transmits the packet with PacketHandler::txPacket().\n  /// @param port PortHandler instance\n  /// @param param Parameter for Bulk Read\n  /// @param param_length Length of the data for Bulk Read\n  /// @return communication results which come from PacketHandler::txPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int bulkReadTx      (PortHandler *port, uint8_t *param, uint16_t param_length) = 0;\n  // BulkReadRx   -> GroupBulkRead class\n  // BulkReadTxRx -> GroupBulkRead class\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits INST_BULK_WRITE instruction packet\n  /// @description The function makes an instruction packet with INST_BULK_WRITE,\n  /// @description transmits the packet with PacketHandler::txRxPacket().\n  /// @param port PortHandler instance\n  /// @param param Parameter for Bulk Write\n  /// @param param_length Length of the data for Bulk Write\n  /// @return communication results which come from PacketHandler::txRxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int bulkWriteTxOnly (PortHandler *port, uint8_t *param, uint16_t param_length) = 0;\n};\n\n}\n\n\n#endif /* DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_PACKETHANDLER_H_ */\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelSDK/include/dynamixel_sdk/port_handler.h",
    "content": "/*******************************************************************************\n* Copyright 2017 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n////////////////////////////////////////////////////////////////////////////////\n/// @file The file for port control\n/// @author Zerom, Leon (RyuWoon Jung)\n////////////////////////////////////////////////////////////////////////////////\n\n#ifndef DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_PORTHANDLER_H_\n#define DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_PORTHANDLER_H_\n\n#if defined(__linux__)\n#define WINDECLSPEC\n#elif defined(__APPLE__)\n#define WINDECLSPEC\n#elif defined(_WIN32) || defined(_WIN64)\n  #ifdef WINDLLEXPORT\n  #define WINDECLSPEC __declspec(dllexport)\n  #else\n  #define WINDECLSPEC __declspec(dllimport)\n  #endif\n#elif defined(ARDUINO) || defined(__OPENCR__) || defined(__OPENCM904__)\n#define WINDECLSPEC\n#endif\n\n#ifdef __GNUC__\n#define DEPRECATED __attribute__((deprecated))\n#elif defined(_MSC_VER)\n#define DEPRECATED __declspec(deprecated)\n#else\n#pragma message(\"WARNING: You need to implement DEPRECATED for this compiler\")\n#define DEPRECATED\n#endif\n\n#include <stdint.h>\n\nnamespace dynamixel\n{\n\n////////////////////////////////////////////////////////////////////////////////\n/// @brief The class for port control that inherits PortHandlerLinux, PortHandlerWindows, PortHandlerMac, or PortHandlerArduino\n////////////////////////////////////////////////////////////////////////////////\nclass WINDECLSPEC PortHandler\n{\n public:\n  static const int DEFAULT_BAUDRATE_ = 57600; ///< Default Baudrate\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that gets PortHandler class inheritance\n  /// @description The function gets class inheritance (PortHandlerLinux / PortHandlerWindows / PortHandlerMac / PortHandlerArduino.\n  ////////////////////////////////////////////////////////////////////////////////\n  static PortHandler *getPortHandler(const char *port_name);\n\n  bool   is_using_; ///< shows whether the port is in use\n\n  virtual ~PortHandler() { }\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that opens the port\n  /// @description The function calls PortHandlerLinux::setBaudRate() to open the port.\n  /// @return communication results which come from PortHandlerLinux::setBaudRate()\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual bool    openPort() = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that closes the port\n  /// @description The function closes the port.\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual void    closePort() = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that clears the port\n  /// @description The function clears the port.\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual void    clearPort() = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that sets port name into the port handler\n  /// @description The function sets port name into the port handler.\n  /// @param port_name Port name\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual void    setPortName(const char* port_name) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that returns port name set into the port handler\n  /// @description The function returns current port name set into the port handler.\n  /// @return Port name\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual char   *getPortName() = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that sets baudrate into the port handler\n  /// @description The function sets baudrate into the port handler.\n  /// @param baudrate Baudrate\n  /// @return false\n  /// @return   when error was occurred during port opening\n  /// @return or true\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual bool    setBaudRate(const int baudrate) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that returns current baudrate set into the port handler\n  /// @description The function returns current baudrate set into the port handler.\n  /// @return Baudrate\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int     getBaudRate() = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that checks how much bytes are able to be read from the port buffer\n  /// @description The function checks how much bytes are able to be read from the port buffer\n  /// @description and returns the number.\n  /// @return Length of read-able bytes in the port buffer\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int     getBytesAvailable() = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that reads bytes from the port buffer\n  /// @description The function gets bytes from the port buffer,\n  /// @description and returns a number of bytes read.\n  /// @param packet Buffer for the packet received\n  /// @param length Length of the buffer for read\n  /// @return -1\n  /// @return   when error was occurred\n  /// @return or Length of bytes read\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int     readPort(uint8_t *packet, int length) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that writes bytes on the port buffer\n  /// @description The function writes bytes on the port buffer,\n  /// @description and returns a number of bytes which are successfully written.\n  /// @param packet Buffer which would be written on the port buffer\n  /// @param length Length of the buffer for write\n  /// @return -1\n  /// @return   when error was occurred\n  /// @return or Length of bytes written\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual int     writePort(uint8_t *packet, int length) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that sets and starts stopwatch for watching packet timeout\n  /// @description The function sets the stopwatch by getting current time and the time of packet timeout with packet_length.\n  /// @param packet_length Length of the packet expected to be received\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual void    setPacketTimeout(uint16_t packet_length) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that sets and starts stopwatch for watching packet timeout\n  /// @description The function sets the stopwatch by getting current time and the time of packet timeout with msec.\n  /// @param packet_length Length of the packet expected to be received\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual void    setPacketTimeout(double msec) = 0;\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that checks whether packet timeout is occurred\n  /// @description The function checks whether current time is passed by the time of packet timeout from the time set by PortHandlerLinux::setPacketTimeout().\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual bool    isPacketTimeout() = 0;\n};\n\n}\n\n\n#endif /* DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_PORTHANDLER_H_ */\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelSDK/include/dynamixel_sdk/port_handler_arduino.h",
    "content": "/*******************************************************************************\n* Copyright 2017 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n////////////////////////////////////////////////////////////////////////////////\n/// @file The file for port control in Arduino\n/// @author Cho (Hancheol Cho), Leon (RyuWoon Jung)\n////////////////////////////////////////////////////////////////////////////////\n\n#ifndef DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_ARDUINO_PORTHANDLERARDUINO_H_\n#define DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_ARDUINO_PORTHANDLERARDUINO_H_\n\n#if defined(ARDUINO) || defined(__OPENCR__) || defined (__OPENCM904__)\n#include <Arduino.h>\n#endif\n\n#include \"port_handler.h\"\n\nnamespace dynamixel\n{\n\n////////////////////////////////////////////////////////////////////////////////\n/// @brief The class for control port in Arduino\n////////////////////////////////////////////////////////////////////////////////\nclass PortHandlerArduino : public PortHandler\n{\n private:\n  int     socket_fd_;\n  int     baudrate_;\n  char    port_name_[100];\n\n  double  packet_start_time_;\n  double  packet_timeout_;\n  double  tx_time_per_byte;\n\n#if defined(__OPENCM904__)\n  UARTClass *p_dxl_serial;\n#endif\n\n  bool    setupPort(const int cflag_baud);\n\n  double  getCurrentTime();\n  double  getTimeSinceStart();\n\n  int     checkBaudrateAvailable(int baudrate);\n\n  void    setPowerOn();\n  void    setPowerOff();\n  void    setTxEnable();\n  void    setTxDisable();\n\n public:\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that initializes instance of PortHandler and gets port_name\n  /// @description The function initializes instance of PortHandler and gets port_name.\n  ////////////////////////////////////////////////////////////////////////////////\n  PortHandlerArduino(const char *port_name);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that closes the port\n  /// @description The function calls PortHandlerArduino::closePort() to close the port.\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual ~PortHandlerArduino() { closePort(); }\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that opens the port\n  /// @description The function calls PortHandlerArduino::setBaudRate() to open the port.\n  /// @return communication results which come from PortHandlerArduino::setBaudRate()\n  ////////////////////////////////////////////////////////////////////////////////\n  bool    openPort();\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that closes the port\n  /// @description The function closes the port.\n  ////////////////////////////////////////////////////////////////////////////////\n  void    closePort();\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that clears the port\n  /// @description The function clears the port.\n  ////////////////////////////////////////////////////////////////////////////////\n  void    clearPort();\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that sets port name into the port handler\n  /// @description The function sets port name into the port handler.\n  /// @param port_name Port name\n  ////////////////////////////////////////////////////////////////////////////////\n  void    setPortName(const char *port_name);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that returns port name set into the port handler\n  /// @description The function returns current port name set into the port handler.\n  /// @return Port name\n  ////////////////////////////////////////////////////////////////////////////////\n  char   *getPortName();\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that sets baudrate into the port handler\n  /// @description The function sets baudrate into the port handler.\n  /// @param baudrate Baudrate\n  /// @return false\n  /// @return   when error was occurred during port opening\n  /// @return or true\n  ////////////////////////////////////////////////////////////////////////////////\n  bool    setBaudRate(const int baudrate);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that returns current baudrate set into the port handler\n  /// @description The function returns current baudrate set into the port handler.\n  /// @return Baudrate\n  ////////////////////////////////////////////////////////////////////////////////\n  int     getBaudRate();\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that checks how much bytes are able to be read from the port buffer\n  /// @description The function checks how much bytes are able to be read from the port buffer\n  /// @description and returns the number.\n  /// @return Length of read-able bytes in the port buffer\n  ////////////////////////////////////////////////////////////////////////////////\n  int     getBytesAvailable();\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that reads bytes from the port buffer\n  /// @description The function gets bytes from the port buffer,\n  /// @description and returns a number of bytes read.\n  /// @param packet Buffer for the packet received\n  /// @param length Length of the buffer for read\n  /// @return -1\n  /// @return   when error was occurred\n  /// @return or Length of bytes read\n  ////////////////////////////////////////////////////////////////////////////////\n  int     readPort(uint8_t *packet, int length);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that writes bytes on the port buffer\n  /// @description The function writes bytes on the port buffer,\n  /// @description and returns a number of bytes which are successfully written.\n  /// @param packet Buffer which would be written on the port buffer\n  /// @param length Length of the buffer for write\n  /// @return -1\n  /// @return   when error was occurred\n  /// @return or Length of bytes written\n  ////////////////////////////////////////////////////////////////////////////////\n  int     writePort(uint8_t *packet, int length);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that sets and starts stopwatch for watching packet timeout\n  /// @description The function sets the stopwatch by getting current time and the time of packet timeout with packet_length.\n  /// @param packet_length Length of the packet expected to be received\n  ////////////////////////////////////////////////////////////////////////////////\n  void    setPacketTimeout(uint16_t packet_length);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that sets and starts stopwatch for watching packet timeout\n  /// @description The function sets the stopwatch by getting current time and the time of packet timeout with msec.\n  /// @param packet_length Length of the packet expected to be received\n  ////////////////////////////////////////////////////////////////////////////////\n  void    setPacketTimeout(double msec);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that checks whether packet timeout is occurred\n  /// @description The function checks whether current time is passed by the time of packet timeout from the time set by PortHandlerArduino::setPacketTimeout().\n  ////////////////////////////////////////////////////////////////////////////////\n  bool    isPacketTimeout();\n};\n\n}\n\n\n#endif /* DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_ARDUINO_PORTHANDLERARDUINO_H_ */\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelSDK/include/dynamixel_sdk/port_handler_linux.h",
    "content": "/*******************************************************************************\n* Copyright 2017 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n////////////////////////////////////////////////////////////////////////////////\n/// @file The file for port control in Linux\n/// @author Zerom, Leon (RyuWoon Jung)\n////////////////////////////////////////////////////////////////////////////////\n\n#ifndef DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_LINUX_PORTHANDLERLINUX_H_\n#define DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_LINUX_PORTHANDLERLINUX_H_\n\n\n#include \"port_handler.h\"\n\nnamespace dynamixel\n{\n\n////////////////////////////////////////////////////////////////////////////////\n/// @brief The class for control port in Linux\n////////////////////////////////////////////////////////////////////////////////\nclass PortHandlerLinux : public PortHandler\n{\n private:\n  int     socket_fd_;\n  int     baudrate_;\n  char    port_name_[100];\n\n  double  packet_start_time_;\n  double  packet_timeout_;\n  double  tx_time_per_byte;\n\n  bool    setupPort(const int cflag_baud);\n  bool    setCustomBaudrate(int speed);\n  int     getCFlagBaud(const int baudrate);\n\n  double  getCurrentTime();\n  double  getTimeSinceStart();\n\n public:\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that initializes instance of PortHandler and gets port_name\n  /// @description The function initializes instance of PortHandler and gets port_name.\n  ////////////////////////////////////////////////////////////////////////////////\n  PortHandlerLinux(const char *port_name);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that closes the port\n  /// @description The function calls PortHandlerLinux::closePort() to close the port.\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual ~PortHandlerLinux() { closePort(); }\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that opens the port\n  /// @description The function calls PortHandlerLinux::setBaudRate() to open the port.\n  /// @return communication results which come from PortHandlerLinux::setBaudRate()\n  ////////////////////////////////////////////////////////////////////////////////\n  bool    openPort();\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that closes the port\n  /// @description The function closes the port.\n  ////////////////////////////////////////////////////////////////////////////////\n  void    closePort();\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that clears the port\n  /// @description The function clears the port.\n  ////////////////////////////////////////////////////////////////////////////////\n  void    clearPort();\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that sets port name into the port handler\n  /// @description The function sets port name into the port handler.\n  /// @param port_name Port name\n  ////////////////////////////////////////////////////////////////////////////////\n  void    setPortName(const char *port_name);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that returns port name set into the port handler\n  /// @description The function returns current port name set into the port handler.\n  /// @return Port name\n  ////////////////////////////////////////////////////////////////////////////////\n  char   *getPortName();\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that sets baudrate into the port handler\n  /// @description The function sets baudrate into the port handler.\n  /// @param baudrate Baudrate\n  /// @return false\n  /// @return   when error was occurred during port opening\n  /// @return or true\n  ////////////////////////////////////////////////////////////////////////////////\n  bool    setBaudRate(const int baudrate);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that returns current baudrate set into the port handler\n  /// @description The function returns current baudrate set into the port handler.\n  /// @return Baudrate\n  ////////////////////////////////////////////////////////////////////////////////\n  int     getBaudRate();\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that checks how much bytes are able to be read from the port buffer\n  /// @description The function checks how much bytes are able to be read from the port buffer\n  /// @description and returns the number.\n  /// @return Length of read-able bytes in the port buffer\n  ////////////////////////////////////////////////////////////////////////////////\n  int     getBytesAvailable();\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that reads bytes from the port buffer\n  /// @description The function gets bytes from the port buffer,\n  /// @description and returns a number of bytes read.\n  /// @param packet Buffer for the packet received\n  /// @param length Length of the buffer for read\n  /// @return -1\n  /// @return   when error was occurred\n  /// @return or Length of bytes read\n  ////////////////////////////////////////////////////////////////////////////////\n  int     readPort(uint8_t *packet, int length);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that writes bytes on the port buffer\n  /// @description The function writes bytes on the port buffer,\n  /// @description and returns a number of bytes which are successfully written.\n  /// @param packet Buffer which would be written on the port buffer\n  /// @param length Length of the buffer for write\n  /// @return -1\n  /// @return   when error was occurred\n  /// @return or Length of bytes written\n  ////////////////////////////////////////////////////////////////////////////////\n  int     writePort(uint8_t *packet, int length);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that sets and starts stopwatch for watching packet timeout\n  /// @description The function sets the stopwatch by getting current time and the time of packet timeout with packet_length.\n  /// @param packet_length Length of the packet expected to be received\n  ////////////////////////////////////////////////////////////////////////////////\n  void    setPacketTimeout(uint16_t packet_length);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that sets and starts stopwatch for watching packet timeout\n  /// @description The function sets the stopwatch by getting current time and the time of packet timeout with msec.\n  /// @param packet_length Length of the packet expected to be received\n  ////////////////////////////////////////////////////////////////////////////////\n  void    setPacketTimeout(double msec);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that checks whether packet timeout is occurred\n  /// @description The function checks whether current time is passed by the time of packet timeout from the time set by PortHandlerLinux::setPacketTimeout().\n  ////////////////////////////////////////////////////////////////////////////////\n  bool    isPacketTimeout();\n};\n\n}\n\n\n#endif /* DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_LINUX_PORTHANDLERLINUX_H_ */\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelSDK/include/dynamixel_sdk/port_handler_mac.h",
    "content": "/*******************************************************************************\n* Copyright 2017 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n////////////////////////////////////////////////////////////////////////////////\n/// @file The file for port control in Mac OS\n/// @author Leon (RyuWoon Jung)\n////////////////////////////////////////////////////////////////////////////////\n\n#ifndef DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_MAC_PORTHANDLERMAC_H_\n#define DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_MAC_PORTHANDLERMAC_H_\n\n\n#include \"port_handler.h\"\n\nnamespace dynamixel\n{\n\n////////////////////////////////////////////////////////////////////////////////\n/// @brief The class for control port in Mac OS\n////////////////////////////////////////////////////////////////////////////////\nclass PortHandlerMac : public PortHandler\n{\n private:\n  int     socket_fd_;\n  int     baudrate_;\n  char    port_name_[100];\n\n  double  packet_start_time_;\n  double  packet_timeout_;\n  double  tx_time_per_byte;\n\n  bool    setupPort(const int cflag_baud);\n  bool    setCustomBaudrate(int speed);\n  int     getCFlagBaud(const int baudrate);\n\n  double  getCurrentTime();\n  double  getTimeSinceStart();\n\n public:\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that initializes instance of PortHandler and gets port_name\n  /// @description The function initializes instance of PortHandler and gets port_name.\n  ////////////////////////////////////////////////////////////////////////////////\n  PortHandlerMac(const char *port_name);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that closes the port\n  /// @description The function calls PortHandlerMac::closePort() to close the port.\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual ~PortHandlerMac() { closePort(); }\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that opens the port\n  /// @description The function calls PortHandlerMac::setBaudRate() to open the port.\n  /// @return communication results which come from PortHandlerMac::setBaudRate()\n  ////////////////////////////////////////////////////////////////////////////////\n  bool    openPort();\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that closes the port\n  /// @description The function closes the port.\n  ////////////////////////////////////////////////////////////////////////////////\n  void    closePort();\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that clears the port\n  /// @description The function clears the port.\n  ////////////////////////////////////////////////////////////////////////////////\n  void    clearPort();\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that sets port name into the port handler\n  /// @description The function sets port name into the port handler.\n  /// @param port_name Port name\n  ////////////////////////////////////////////////////////////////////////////////\n  void    setPortName(const char *port_name);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that returns port name set into the port handler\n  /// @description The function returns current port name set into the port handler.\n  /// @return Port name\n  ////////////////////////////////////////////////////////////////////////////////\n  char   *getPortName();\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that sets baudrate into the port handler\n  /// @description The function sets baudrate into the port handler.\n  /// @param baudrate Baudrate\n  /// @return false\n  /// @return   when error was occurred during port opening\n  /// @return or true\n  ////////////////////////////////////////////////////////////////////////////////\n  bool    setBaudRate(const int baudrate);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that returns current baudrate set into the port handler\n  /// @description The function returns current baudrate set into the port handler.\n  /// @warning Mac OS doesn't support over 230400 bps\n  /// @return Baudrate\n  ////////////////////////////////////////////////////////////////////////////////\n  int     getBaudRate();\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that checks how much bytes are able to be read from the port buffer\n  /// @description The function checks how much bytes are able to be read from the port buffer\n  /// @description and returns the number.\n  /// @return Length of read-able bytes in the port buffer\n  ////////////////////////////////////////////////////////////////////////////////\n  int     getBytesAvailable();\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that reads bytes from the port buffer\n  /// @description The function gets bytes from the port buffer,\n  /// @description and returns a number of bytes read.\n  /// @param packet Buffer for the packet received\n  /// @param length Length of the buffer for read\n  /// @return -1\n  /// @return   when error was occurred\n  /// @return or Length of bytes read\n  ////////////////////////////////////////////////////////////////////////////////\n  int     readPort(uint8_t *packet, int length);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that writes bytes on the port buffer\n  /// @description The function writes bytes on the port buffer,\n  /// @description and returns a number of bytes which are successfully written.\n  /// @param packet Buffer which would be written on the port buffer\n  /// @param length Length of the buffer for write\n  /// @return -1\n  /// @return   when error was occurred\n  /// @return or Length of bytes written\n  ////////////////////////////////////////////////////////////////////////////////\n  int     writePort(uint8_t *packet, int length);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that sets and starts stopwatch for watching packet timeout\n  /// @description The function sets the stopwatch by getting current time and the time of packet timeout with packet_length.\n  /// @param packet_length Length of the packet expected to be received\n  ////////////////////////////////////////////////////////////////////////////////\n  void    setPacketTimeout(uint16_t packet_length);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that sets and starts stopwatch for watching packet timeout\n  /// @description The function sets the stopwatch by getting current time and the time of packet timeout with msec.\n  /// @param packet_length Length of the packet expected to be received\n  ////////////////////////////////////////////////////////////////////////////////\n  void    setPacketTimeout(double msec);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that checks whether packet timeout is occurred\n  /// @description The function checks whether current time is passed by the time of packet timeout from the time set by PortHandlerMac::setPacketTimeout().\n  ////////////////////////////////////////////////////////////////////////////////\n  bool    isPacketTimeout();\n};\n\n}\n\n\n#endif /* DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_MAC_PORTHANDLERMAC_H_ */\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelSDK/include/dynamixel_sdk/port_handler_windows.h",
    "content": "/*******************************************************************************\n* Copyright 2017 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n////////////////////////////////////////////////////////////////////////////////\n/// @file The file for port control in Windows\n/// @author Leon (RyuWoon Jung)\n////////////////////////////////////////////////////////////////////////////////\n\n#ifndef DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_WINDOWS_PORTHANDLERWINDOWS_H_\n#define DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_WINDOWS_PORTHANDLERWINDOWS_H_\n\n#include <Windows.h>\n\n#include \"port_handler.h\"\n\nnamespace dynamixel\n{\n\n////////////////////////////////////////////////////////////////////////////////\n/// @brief The class for control port in Windows\n////////////////////////////////////////////////////////////////////////////////\nclass WINDECLSPEC PortHandlerWindows : public PortHandler\n{\n private:\n  HANDLE  serial_handle_;\n  LARGE_INTEGER freq_, counter_;\n\n  int     baudrate_;\n  char    port_name_[100];\n\n  double  packet_start_time_;\n  double  packet_timeout_;\n  double  tx_time_per_byte_;\n\n  bool    setupPort(const int baudrate);\n\n  double  getCurrentTime();\n  double  getTimeSinceStart();\n\n public:\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that initializes instance of PortHandler and gets port_name\n  /// @description The function initializes instance of PortHandler and gets port_name.\n  ////////////////////////////////////////////////////////////////////////////////\n  PortHandlerWindows(const char *port_name);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that closes the port\n  /// @description The function calls PortHandlerWindows::closePort() to close the port.\n  ////////////////////////////////////////////////////////////////////////////////\n  virtual ~PortHandlerWindows() { closePort(); }\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that opens the port\n  /// @description The function calls PortHandlerWindows::setBaudRate() to open the port.\n  /// @return communication results which come from PortHandlerWindows::setBaudRate()\n  ////////////////////////////////////////////////////////////////////////////////\n  bool    openPort();\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that closes the port\n  /// @description The function closes the port.\n  ////////////////////////////////////////////////////////////////////////////////\n  void    closePort();\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that clears the port\n  /// @description The function clears the port.\n  ////////////////////////////////////////////////////////////////////////////////\n  void    clearPort();\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that sets port name into the port handler\n  /// @description The function sets port name into the port handler.\n  /// @param port_name Port name\n  ////////////////////////////////////////////////////////////////////////////////\n  void    setPortName(const char *port_name);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that returns port name set into the port handler\n  /// @description The function returns current port name set into the port handler.\n  /// @return Port name\n  ////////////////////////////////////////////////////////////////////////////////\n  char   *getPortName();\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that sets baudrate into the port handler\n  /// @description The function sets baudrate into the port handler.\n  /// @param baudrate Baudrate\n  /// @return false\n  /// @return   when error was occurred during port opening\n  /// @return or true\n  ////////////////////////////////////////////////////////////////////////////////\n  bool    setBaudRate(const int baudrate);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that returns current baudrate set into the port handler\n  /// @description The function returns current baudrate set into the port handler.\n  /// @return Baudrate\n  ////////////////////////////////////////////////////////////////////////////////\n  int     getBaudRate();\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that checks how much bytes are able to be read from the port buffer\n  /// @description The function checks how much bytes are able to be read from the port buffer\n  /// @description and returns the number.\n  /// @return Length of read-able bytes in the port buffer\n  ////////////////////////////////////////////////////////////////////////////////\n  int     getBytesAvailable();\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that reads bytes from the port buffer\n  /// @description The function gets bytes from the port buffer,\n  /// @description and returns a number of bytes read.\n  /// @param packet Buffer for the packet received\n  /// @param length Length of the buffer for read\n  /// @return -1\n  /// @return   when error was occurred\n  /// @return or Length of bytes read\n  ////////////////////////////////////////////////////////////////////////////////\n  int     readPort(uint8_t *packet, int length);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that writes bytes on the port buffer\n  /// @description The function writes bytes on the port buffer,\n  /// @description and returns a number of bytes which are successfully written.\n  /// @param packet Buffer which would be written on the port buffer\n  /// @param length Length of the buffer for write\n  /// @return -1\n  /// @return   when error was occurred\n  /// @return or Length of bytes written\n  ////////////////////////////////////////////////////////////////////////////////\n  int     writePort(uint8_t *packet, int length);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that sets and starts stopwatch for watching packet timeout\n  /// @description The function sets the stopwatch by getting current time and the time of packet timeout with packet_length.\n  /// @param packet_length Length of the packet expected to be received\n  ////////////////////////////////////////////////////////////////////////////////\n  void    setPacketTimeout(uint16_t packet_length);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that sets and starts stopwatch for watching packet timeout\n  /// @description The function sets the stopwatch by getting current time and the time of packet timeout with msec.\n  /// @param packet_length Length of the packet expected to be received\n  ////////////////////////////////////////////////////////////////////////////////\n  void    setPacketTimeout(double msec);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that checks whether packet timeout is occurred\n  /// @description The function checks whether current time is passed by the time of packet timeout from the time set by PortHandlerWindows::setPacketTimeout().\n  ////////////////////////////////////////////////////////////////////////////////\n  bool    isPacketTimeout();\n};\n\n}\n\n\n#endif /* DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_WINDOWS_PORTHANDLERWINDOWS_H_ */\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelSDK/include/dynamixel_sdk/protocol1_packet_handler.h",
    "content": "/*******************************************************************************\n* Copyright 2017 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n////////////////////////////////////////////////////////////////////////////////\n/// @file The file for Protocol 1.0 Dynamixel packet control\n/// @author Zerom, Leon (RyuWoon Jung)\n////////////////////////////////////////////////////////////////////////////////\n\n#ifndef DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_PROTOCOL1PACKETHANDLER_H_\n#define DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_PROTOCOL1PACKETHANDLER_H_\n\n\n#include \"packet_handler.h\"\n\nnamespace dynamixel\n{\n\n////////////////////////////////////////////////////////////////////////////////\n/// @brief The class for control Dynamixel by using Protocol1.0\n////////////////////////////////////////////////////////////////////////////////\nclass WINDECLSPEC Protocol1PacketHandler : public PacketHandler\n{\n private:\n  static Protocol1PacketHandler *unique_instance_;\n\n  Protocol1PacketHandler();\n\n public:\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that returns Protocol1PacketHandler instance\n  /// @return Protocol1PacketHandler instance\n  ////////////////////////////////////////////////////////////////////////////////\n  static Protocol1PacketHandler *getInstance() { return unique_instance_; }\n\n  virtual ~Protocol1PacketHandler() { }\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that returns Protocol version used in Protocol1PacketHandler (1.0)\n  /// @return 1.0\n  ////////////////////////////////////////////////////////////////////////////////\n  float   getProtocolVersion() { return 1.0; }\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that gets description of communication result\n  /// @param result Communication result which might be gotten by the tx rx functions\n  /// @return description of communication result in const char* (string)\n  ////////////////////////////////////////////////////////////////////////////////\n  const char *getTxRxResult     (int result);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that gets description of hardware error\n  /// @param error Dynamixel hardware error which might be gotten by the tx rx functions\n  /// @return description of hardware error in const char* (string)\n  ////////////////////////////////////////////////////////////////////////////////\n  const char *getRxPacketError  (uint8_t error);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits the instruction packet txpacket via PortHandler port.\n  /// @description The function clears the port buffer by PortHandler::clearPort() function,\n  /// @description   then transmits txpacket by PortHandler::writePort() function.\n  /// @description The function activates only when the port is not busy and when the packet is already written on the port buffer\n  /// @param port PortHandler instance\n  /// @param txpacket packet for transmission\n  /// @return COMM_PORT_BUSY\n  /// @return   when the port is already in use\n  /// @return COMM_TX_ERROR\n  /// @return   when txpacket is out of range described by TXPACKET_MAX_LEN\n  /// @return COMM_TX_FAIL\n  /// @return   when written packet is shorter than expected\n  /// @return or COMM_SUCCESS\n  ////////////////////////////////////////////////////////////////////////////////\n  int txPacket        (PortHandler *port, uint8_t *txpacket);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that receives packet (rxpacket) during designated time via PortHandler port\n  /// @description The function repeatedly tries to receive rxpacket by PortHandler::readPort() function.\n  /// @description It breaks out\n  /// @description when PortHandler::isPacketTimeout() shows the timeout,\n  /// @description when rxpacket seemed as corrupted, or\n  /// @description when nothing received\n  /// @param port PortHandler instance\n  /// @param rxpacket received packet\n  /// @return COMM_RX_CORRUPT\n  /// @return   when it received the packet but it couldn't find header in the packet\n  /// @return   when it found header in the packet but the id, length or error value is out of range\n  /// @return   when it received the packet but it is shorted than expected\n  /// @return COMM_RX_TIMEOUT\n  /// @return   when there is no rxpacket received until PortHandler::isPacketTimeout() shows the timeout\n  /// @return COMM_SUCCESS\n  /// @return   when rxpacket passes checksum test\n  /// @return or COMM_RX_FAIL\n  ////////////////////////////////////////////////////////////////////////////////\n  int rxPacket        (PortHandler *port, uint8_t *rxpacket);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits packet (txpacket) and receives packet (rxpacket) during designated time via PortHandler port\n  /// @description The function calls Protocol1PacketHandler::txPacket(),\n  /// @description and calls Protocol1PacketHandler::rxPacket() if it succeeds Protocol1PacketHandler::txPacket().\n  /// @description It breaks out\n  /// @description when it fails Protocol1PacketHandler::txPacket(),\n  /// @description when txpacket is called by Protocol1PacketHandler::broadcastPing() / Protocol1PacketHandler::syncWriteTxOnly() / Protocol1PacketHandler::regWriteTxOnly / Protocol1PacketHandler::action\n  /// @param port PortHandler instance\n  /// @param txpacket packet for transmission\n  /// @param rxpacket received packet\n  /// @return COMM_SUCCESS\n  /// @return   when it succeeds Protocol1PacketHandler::txPacket() and Protocol1PacketHandler::rxPacket()\n  /// @return or the other communication results which come from Protocol1PacketHandler::txPacket() and Protocol1PacketHandler::rxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  int txRxPacket      (PortHandler *port, uint8_t *txpacket, uint8_t *rxpacket, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that pings Dynamixel but doesn't take its model number\n  /// @description The function calls Protocol1PacketHandler::ping() which gets Dynamixel model number,\n  /// @description but doesn't carry the model number\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from Protocol1PacketHandler::ping()\n  ////////////////////////////////////////////////////////////////////////////////\n  int ping            (PortHandler *port, uint8_t id, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that pings Dynamixel and takes its model number\n  /// @description The function makes an instruction packet with INST_PING,\n  /// @description transmits the packet with Protocol1PacketHandler::txRxPacket(),\n  /// @description and call Protocol1PacketHandler::readTxRx to read model_number in the rx buffer.\n  /// @description It breaks out\n  /// @description when it tries to transmit to BROADCAST_ID\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param error Dynamixel hardware error\n  /// @return COMM_NOT_AVAILABLE\n  /// @return   when it tries to transmit to BROADCAST_ID\n  /// @return COMM_SUCCESS\n  /// @return   when it succeeds to ping Dynamixel and get model_number from it\n  /// @return or the other communication results which come from Protocol1PacketHandler::txRxPacket() and Protocol1PacketHandler::readTxRx()\n  ////////////////////////////////////////////////////////////////////////////////\n  int ping            (PortHandler *port, uint8_t id, uint16_t *model_number, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief (Available only in Protocol 2.0) The function that pings all connected Dynamixel\n  /// @param port PortHandler instance\n  /// @param id_list ID list of Dynamixels which are found by broadcast ping\n  /// @return COMM_NOT_AVAILABLE\n  ////////////////////////////////////////////////////////////////////////////////\n  int broadcastPing   (PortHandler *port, std::vector<uint8_t> &id_list);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that makes Dynamixels run as written in the Dynamixel register\n  /// @description The function makes an instruction packet with INST_ACTION,\n  /// @description transmits the packet with Protocol1PacketHandler::txRxPacket().\n  /// @description To use this function, Dynamixel register should be set by Protocol1PacketHandler::regWriteTxOnly() or Protocol1PacketHandler::regWriteTxRx()\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @return communication results which come from Protocol1PacketHandler::txRxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  int action          (PortHandler *port, uint8_t id);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief (Available only in Protocol 2.0) The function that makes Dynamixel reboot\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param error Dynamixel hardware error\n  /// @return COMM_NOT_AVAILABLE\n  ////////////////////////////////////////////////////////////////////////////////\n  int reboot          (PortHandler *port, uint8_t id, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief (Available only in Protocol 2.0) The function that reset multi-turn revolution information of Dynamixel\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param error Dynamixel hardware error\n  /// @return COMM_NOT_AVAILABLE\n  ////////////////////////////////////////////////////////////////////////////////\n  int clearMultiTurn  (PortHandler *port, uint8_t id, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that makes Dynamixel reset as it was produced in the factory\n  /// @description The function makes an instruction packet with INST_FACTORY_RESET,\n  /// @description transmits the packet with Protocol1PacketHandler::txRxPacket().\n  /// @description Be careful of the use.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param option (Not available in Protocol 1.0) Reset option\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from Protocol1PacketHandler::txRxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  int factoryReset    (PortHandler *port, uint8_t id, uint8_t option, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits INST_READ instruction packet\n  /// @description The function makes an instruction packet with INST_READ,\n  /// @description transmits the packet with Protocol1PacketHandler::txPacket().\n  /// @description It breaks out\n  /// @description when it tries to transmit to BROADCAST_ID\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for read\n  /// @param length Length of the data for read\n  /// @return COMM_NOT_AVAILABLE\n  /// @return   when it tries to transmit to BROADCAST_ID\n  /// @return or the other communication results which come from Protocol1PacketHandler::txPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  int readTx          (PortHandler *port, uint8_t id, uint16_t address, uint16_t length);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that receives the packet and reads the data in the packet\n  /// @description The function receives the packet which might be come by previous INST_READ instruction packet transmission,\n  /// @description gets the data from the packet.\n  /// @param port PortHandler instance\n  /// @param length Length of the data for read\n  /// @param data Data extracted from the packet\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from Protocol1PacketHandler::rxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  int readRx          (PortHandler *port, uint8_t id, uint16_t length, uint8_t *data, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits INST_READ instruction packet, and read data from received packet\n  /// @description The function makes an instruction packet with INST_READ,\n  /// @description transmits and receives the packet with Protocol1PacketHandler::txRxPacket(),\n  /// @description gets the data from the packet.\n  /// @description It breaks out\n  /// @description when it tries to transmit to BROADCAST_ID\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for read\n  /// @param length Length of the data for read\n  /// @param data Data extracted from the packet\n  /// @param error Dynamixel hardware error\n  /// @return COMM_NOT_AVAILABLE\n  /// @return   when it tries to transmit to BROADCAST_ID\n  /// @return or the other communication results which come from Protocol1PacketHandler::txRxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  int readTxRx        (PortHandler *port, uint8_t id, uint16_t address, uint16_t length, uint8_t *data, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls Protocol1PacketHandler::readTx() function for reading 1 byte data\n  /// @description The function calls Protocol1PacketHandler::readTx() function for reading 1 byte data\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for read\n  /// @return communication results which come from Protocol1PacketHandler::readTx()\n  ////////////////////////////////////////////////////////////////////////////////\n  int read1ByteTx     (PortHandler *port, uint8_t id, uint16_t address);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls Protocol1PacketHandler::readRx() function and reads 1 byte data on the packet\n  /// @description The function calls Protocol1PacketHandler::readRx() function,\n  /// @description gets 1 byte data from the packet.\n  /// @param port PortHandler instance\n  /// @param data Data extracted from the packet\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from Protocol1PacketHandler::readRx()\n  ////////////////////////////////////////////////////////////////////////////////\n  int read1ByteRx     (PortHandler *port, uint8_t id, uint8_t *data, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls Protocol1PacketHandler::readTxRx() function for reading 1 byte data\n  /// @description The function calls Protocol1PacketHandler::readTxRx(),\n  /// @description gets 1 byte data from the packet.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for read\n  /// @param length Length of the data for read\n  /// @param data Data extracted from the packet\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from Protocol1PacketHandler::txRxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  int read1ByteTxRx       (PortHandler *port, uint8_t id, uint16_t address, uint8_t *data, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls Protocol1PacketHandler::readTx() function for reading 2 byte data\n  /// @description The function calls Protocol1PacketHandler::readTx() function for reading 2 byte data\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for read\n  /// @return communication results which come from Protocol1PacketHandler::readTx()\n  ////////////////////////////////////////////////////////////////////////////////\n  int read2ByteTx     (PortHandler *port, uint8_t id, uint16_t address);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls Protocol1PacketHandler::readRx() function and reads 2 byte data on the packet\n  /// @description The function calls Protocol1PacketHandler::readRx() function,\n  /// @description gets 2 byte data from the packet.\n  /// @param port PortHandler instance\n  /// @param data Data extracted from the packet\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from Protocol1PacketHandler::readRx()\n  ////////////////////////////////////////////////////////////////////////////////\n  int read2ByteRx     (PortHandler *port, uint8_t id, uint16_t *data, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls Protocol1PacketHandler::readTxRx() function for reading 2 byte data\n  /// @description The function calls Protocol1PacketHandler::readTxRx(),\n  /// @description gets 2 byte data from the packet.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for read\n  /// @param length Length of the data for read\n  /// @param data Data extracted from the packet\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from Protocol1PacketHandler::txRxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  int read2ByteTxRx       (PortHandler *port, uint8_t id, uint16_t address, uint16_t *data, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls Protocol1PacketHandler::readTx() function for reading 4 byte data\n  /// @description The function calls Protocol1PacketHandler::readTx() function for reading 4 byte data\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for read\n  /// @return communication results which come from Protocol1PacketHandler::readTx()\n  ////////////////////////////////////////////////////////////////////////////////\n  int read4ByteTx     (PortHandler *port, uint8_t id, uint16_t address);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls Protocol1PacketHandler::readRx() function and reads 4 byte data on the packet\n  /// @description The function calls Protocol1PacketHandler::readRx() function,\n  /// @description gets 4 byte data from the packet.\n  /// @param port PortHandler instance\n  /// @param data Data extracted from the packet\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from Protocol1PacketHandler::readRx()\n  ////////////////////////////////////////////////////////////////////////////////\n  int read4ByteRx     (PortHandler *port, uint8_t id, uint32_t *data, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls Protocol1PacketHandler::readTxRx() function for reading 4 byte data\n  /// @description The function calls Protocol1PacketHandler::readTxRx(),\n  /// @description gets 4 byte data from the packet.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for read\n  /// @param length Length of the data for read\n  /// @param data Data extracted from the packet\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from Protocol1PacketHandler::txRxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  int read4ByteTxRx       (PortHandler *port, uint8_t id, uint16_t address, uint32_t *data, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits INST_WRITE instruction packet with the data for write\n  /// @description The function makes an instruction packet with INST_WRITE and the data for write,\n  /// @description transmits the packet with Protocol1PacketHandler::txPacket().\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for write\n  /// @param length Length of the data for write\n  /// @param data Data for write\n  /// @return communication results which come from Protocol1PacketHandler::txPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  int writeTxOnly     (PortHandler *port, uint8_t id, uint16_t address, uint16_t length, uint8_t *data);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits INST_WRITE instruction packet with the data for write, and receives the packet\n  /// @description The function makes an instruction packet with INST_WRITE and the data for write,\n  /// @description transmits and receives the packet with Protocol1PacketHandler::txRxPacket(),\n  /// @description gets the error from the packet.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for write\n  /// @param length Length of the data for write\n  /// @param data Data for write\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from Protocol1PacketHandler::txRxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  int writeTxRx           (PortHandler *port, uint8_t id, uint16_t address, uint16_t length, uint8_t *data, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls Protocol1PacketHandler::writeTxOnly() for writing 1 byte data\n  /// @description The function calls Protocol1PacketHandler::writeTxOnly() for writing 1 byte data.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for write\n  /// @param data Data for write\n  /// @return communication results which come from Protocol1PacketHandler::writeTxOnly()\n  ////////////////////////////////////////////////////////////////////////////////\n  int write1ByteTxOnly(PortHandler *port, uint8_t id, uint16_t address, uint8_t data);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls Protocol1PacketHandler::writeTxRx() for writing 1 byte data and receives the packet\n  /// @description The function calls Protocol1PacketHandler::writeTxRx() for writing 1 byte data and receves the packet,\n  /// @description gets the error from the packet.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for write\n  /// @param data Data for write\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from Protocol1PacketHandler::writeTxRx()\n  ////////////////////////////////////////////////////////////////////////////////\n  int write1ByteTxRx      (PortHandler *port, uint8_t id, uint16_t address, uint8_t data, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls Protocol1PacketHandler::writeTxOnly() for writing 2 byte data\n  /// @description The function calls Protocol1PacketHandler::writeTxOnly() for writing 2 byte data.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for write\n  /// @param data Data for write\n  /// @return communication results which come from Protocol1PacketHandler::writeTxOnly()\n  ////////////////////////////////////////////////////////////////////////////////\n  int write2ByteTxOnly(PortHandler *port, uint8_t id, uint16_t address, uint16_t data);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls Protocol1PacketHandler::writeTxRx() for writing 2 byte data and receives the packet\n  /// @description The function calls Protocol1PacketHandler::writeTxRx() for writing 2 byte data and receves the packet,\n  /// @description gets the error from the packet.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for write\n  /// @param data Data for write\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from Protocol1PacketHandler::writeTxRx()\n  ////////////////////////////////////////////////////////////////////////////////\n  int write2ByteTxRx      (PortHandler *port, uint8_t id, uint16_t address, uint16_t data, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls Protocol1PacketHandler::writeTxOnly() for writing 4 byte data\n  /// @description The function calls Protocol1PacketHandler::writeTxOnly() for writing 4 byte data.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for write\n  /// @param data Data for write\n  /// @return communication results which come from Protocol1PacketHandler::writeTxOnly()\n  ////////////////////////////////////////////////////////////////////////////////\n  int write4ByteTxOnly(PortHandler *port, uint8_t id, uint16_t address, uint32_t data);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls Protocol1PacketHandler::writeTxRx() for writing 4 byte data and receives the packet\n  /// @description The function calls Protocol1PacketHandler::writeTxRx() for writing 4 byte data and receves the packet,\n  /// @description gets the error from the packet.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for write\n  /// @param data Data for write\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from Protocol1PacketHandler::writeTxRx()\n  ////////////////////////////////////////////////////////////////////////////////\n  int write4ByteTxRx      (PortHandler *port, uint8_t id, uint16_t address, uint32_t data, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits INST_REG_WRITE instruction packet with the data for writing on the Dynamixel register\n  /// @description The function makes an instruction packet with INST_REG_WRITE and the data for writing on the Dynamixel register,\n  /// @description transmits the packet with Protocol1PacketHandler::txPacket().\n  /// @description The data written in the register will act when INST_ACTION instruction packet is transmitted to the Dynamxel.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for write\n  /// @param length Length of the data for write\n  /// @param data Data for write\n  /// @return communication results which come from Protocol1PacketHandler::txPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  int regWriteTxOnly  (PortHandler *port, uint8_t id, uint16_t address, uint16_t length, uint8_t *data);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits INST_REG_WRITE instruction packet with the data for writing on the Dynamixel register, and receives the packet\n  /// @description The function makes an instruction packet with INST_REG_WRITE and the data for writing on the Dynamixel register,\n  /// @description transmits and receives the packet with Protocol1PacketHandler::txRxPacket(),\n  /// @description gets the error from the packet.\n  /// @description The data written in the register will act when INST_ACTION instruction packet is transmitted to the Dynamxel.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for write\n  /// @param length Length of the data for write\n  /// @param data Data for write\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from Protocol1PacketHandler::txRxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  int regWriteTxRx        (PortHandler *port, uint8_t id, uint16_t address, uint16_t length, uint8_t *data, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief (Available only in Protocol 2.0) The function that transmits Sync Read instruction packet\n  /// @param port PortHandler instance\n  /// @param start_address Address of the data for Sync Read\n  /// @param data_length Length of the data for Sync Read\n  /// @param param Parameter for Sync Read\n  /// @param param_length Length of the data for Sync Read\n  /// @return COMM_NOT_AVAILABLE\n  ////////////////////////////////////////////////////////////////////////////////\n  int syncReadTx      (PortHandler *port, uint16_t start_address, uint16_t data_length, uint8_t *param, uint16_t param_length);\n  // SyncReadRx   -> GroupSyncRead class\n  // SyncReadTxRx -> GroupSyncRead class\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits Sync Write instruction packet\n  /// @description The function makes an instruction packet with INST_SYNC_WRITE,\n  /// @description transmits the packet with Protocol1PacketHandler::txRxPacket().\n  /// @param port PortHandler instance\n  /// @param start_address Address of the data for Sync Write\n  /// @param data_length Length of the data for Sync Write\n  /// @param param Parameter for Sync Write {ID1, DATA0, DATA1, ..., DATAn, ID2, DATA0, DATA1, ..., DATAn, ID3, DATA0, DATA1, ..., DATAn}\n  /// @param param_length Length of the data for Sync Write\n  /// @return communication results which come from Protocol1PacketHandler::txRxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  int syncWriteTxOnly (PortHandler *port, uint16_t start_address, uint16_t data_length, uint8_t *param, uint16_t param_length);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief (Available only on Dynamixel MX / X series) The function that transmits Bulk Read instruction packet\n  /// @description The function makes an instruction packet with INST_BULK_READ,\n  /// @description transmits the packet with Protocol1PacketHandler::txPacket().\n  /// @param port PortHandler instance\n  /// @param param Parameter for Bulk Read {LEN1, ID1, ADDR1, LEN2, ID2, ADDR2, ...}\n  /// @param param_length Length of the data for Bulk Read\n  /// @return communication results which come from Protocol1PacketHandler::txPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  int bulkReadTx      (PortHandler *port, uint8_t *param, uint16_t param_length);\n  // BulkReadRx   -> GroupBulkRead class\n  // BulkReadTxRx -> GroupBulkRead class\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief (Available only in Protocol 2.0) The function that transmits Bulk Write instruction packet\n  /// @param port PortHandler instance\n  /// @param param Parameter for Bulk Write\n  /// @param param_length Length of the data for Bulk Write\n  /// @return COMM_NOT_AVAILABLE\n  ////////////////////////////////////////////////////////////////////////////////\n  int bulkWriteTxOnly (PortHandler *port, uint8_t *param, uint16_t param_length);\n};\n\n}\n\n\n#endif /* DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_PROTOCOL1PACKETHANDLER_H_ */\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelSDK/include/dynamixel_sdk/protocol2_packet_handler.h",
    "content": "/*******************************************************************************\n* Copyright 2017 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n////////////////////////////////////////////////////////////////////////////////\n/// @file The file for Protocol 2.0 Dynamixel packet control\n/// @author Zerom, Leon (RyuWoon Jung)\n////////////////////////////////////////////////////////////////////////////////\n\n#ifndef DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_PROTOCOL2PACKETHANDLER_H_\n#define DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_PROTOCOL2PACKETHANDLER_H_\n\n\n#include \"packet_handler.h\"\n\nnamespace dynamixel\n{\n\n////////////////////////////////////////////////////////////////////////////////\n/// @brief The class for control Dynamixel by using Protocol2.0\n////////////////////////////////////////////////////////////////////////////////\nclass WINDECLSPEC Protocol2PacketHandler : public PacketHandler\n{\n private:\n  static Protocol2PacketHandler *unique_instance_;\n\n  Protocol2PacketHandler();\n\n  uint16_t    updateCRC(uint16_t crc_accum, uint8_t *data_blk_ptr, uint16_t data_blk_size);\n  void        addStuffing(uint8_t *packet);\n  void        removeStuffing(uint8_t *packet);\n\n public:\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that returns Protocol2PacketHandler instance\n  /// @return Protocol2PacketHandler instance\n  ////////////////////////////////////////////////////////////////////////////////\n  static Protocol2PacketHandler *getInstance() { return unique_instance_; }\n\n  virtual ~Protocol2PacketHandler() { }\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that returns Protocol version used in Protocol2PacketHandler (2.0)\n  /// @return 2.0\n  ////////////////////////////////////////////////////////////////////////////////\n  float   getProtocolVersion() { return 2.0; }\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that gets description of communication result\n  /// @param result Communication result which might be gotten by the tx rx functions\n  /// @return description of communication result in const char* (string)\n  ////////////////////////////////////////////////////////////////////////////////\n  const char *getTxRxResult     (int result);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that gets description of hardware error\n  /// @param error Dynamixel hardware error which might be gotten by the tx rx functions\n  /// @return description of hardware error in const char* (string)\n  ////////////////////////////////////////////////////////////////////////////////\n  const char *getRxPacketError  (uint8_t error);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits the instruction packet txpacket via PortHandler port.\n  /// @description The function clears the port buffer by PortHandler::clearPort() function,\n  /// @description   then transmits txpacket by PortHandler::writePort() function.\n  /// @description The function activates only when the port is not busy and when the packet is already written on the port buffer\n  /// @param port PortHandler instance\n  /// @param txpacket packet for transmission\n  /// @return COMM_PORT_BUSY\n  /// @return   when the port is already in use\n  /// @return COMM_TX_ERROR\n  /// @return   when txpacket is out of range described by TXPACKET_MAX_LEN\n  /// @return COMM_TX_FAIL\n  /// @return   when written packet is shorter than expected\n  /// @return or COMM_SUCCESS\n  ////////////////////////////////////////////////////////////////////////////////\n  int txPacket        (PortHandler *port, uint8_t *txpacket);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that receives packet (rxpacket) during designated time via PortHandler port\n  /// @description The function repeatedly tries to receive rxpacket by PortHandler::readPort() function.\n  /// @description It breaks out\n  /// @description when PortHandler::isPacketTimeout() shows the timeout,\n  /// @description when rxpacket seemed as corrupted, or\n  /// @description when nothing received\n  /// @param port PortHandler instance\n  /// @param rxpacket received packet\n  /// @return COMM_RX_CORRUPT\n  /// @return   when it received the packet but it couldn't find header in the packet\n  /// @return   when it found header in the packet but the id, length or error value is out of range\n  /// @return   when it received the packet but it is shorted than expected\n  /// @return COMM_RX_TIMEOUT\n  /// @return   when there is no rxpacket received until PortHandler::isPacketTimeout() shows the timeout\n  /// @return COMM_SUCCESS\n  /// @return   when rxpacket passes checksum test\n  /// @return or COMM_RX_FAIL\n  ////////////////////////////////////////////////////////////////////////////////\n  int rxPacket        (PortHandler *port, uint8_t *rxpacket);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits packet (txpacket) and receives packet (rxpacket) during designated time via PortHandler port\n  /// @description The function calls Protocol2PacketHandler::txPacket(),\n  /// @description and calls Protocol2PacketHandler::rxPacket() if it succeeds Protocol2PacketHandler::txPacket().\n  /// @description It breaks out\n  /// @description when it fails Protocol2PacketHandler::txPacket(),\n  /// @description when txpacket is called by Protocol2PacketHandler::broadcastPing() / Protocol2PacketHandler::syncWriteTxOnly() / Protocol2PacketHandler::regWriteTxOnly / Protocol2PacketHandler::action\n  /// @param port PortHandler instance\n  /// @param txpacket packet for transmission\n  /// @param rxpacket received packet\n  /// @return COMM_SUCCESS\n  /// @return   when it succeeds Protocol2PacketHandler::txPacket() and Protocol2PacketHandler::rxPacket()\n  /// @return or the other communication results which come from Protocol2PacketHandler::txPacket() and Protocol2PacketHandler::rxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  int txRxPacket      (PortHandler *port, uint8_t *txpacket, uint8_t *rxpacket, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that pings Dynamixel but doesn't take its model number\n  /// @description The function calls Protocol2PacketHandler::ping() which gets Dynamixel model number,\n  /// @description but doesn't carry the model number\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from Protocol2PacketHandler::ping()\n  ////////////////////////////////////////////////////////////////////////////////\n  int ping            (PortHandler *port, uint8_t id, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that pings Dynamixel and takes its model number\n  /// @description The function makes an instruction packet with INST_PING,\n  /// @description transmits the packet with Protocol2PacketHandler::txRxPacket(),\n  /// @description and call Protocol2PacketHandler::readTxRx to read model_number in the rx buffer.\n  /// @description It breaks out\n  /// @description when it tries to transmit to BROADCAST_ID\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param error Dynamixel hardware error\n  /// @return COMM_NOT_AVAILABLE\n  /// @return   when it tries to transmit to BROADCAST_ID\n  /// @return COMM_SUCCESS\n  /// @return   when it succeeds to ping Dynamixel and get model_number from it\n  /// @return or the other communication results which come from Protocol2PacketHandler::txRxPacket() and Protocol2PacketHandler::readTxRx()\n  ////////////////////////////////////////////////////////////////////////////////\n  int ping            (PortHandler *port, uint8_t id, uint16_t *model_number, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief (Available only in Protocol 2.0) The function that pings all connected Dynamixel\n  /// @param port PortHandler instance\n  /// @param id_list ID list of Dynamixels which are found by broadcast ping\n  /// @return COMM_NOT_AVAILABLE\n  ////////////////////////////////////////////////////////////////////////////////\n  int broadcastPing   (PortHandler *port, std::vector<uint8_t> &id_list);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that makes Dynamixels run as written in the Dynamixel register\n  /// @description The function makes an instruction packet with INST_ACTION,\n  /// @description transmits the packet with Protocol2PacketHandler::txRxPacket().\n  /// @description To use this function, Dynamixel register should be set by Protocol2PacketHandler::regWriteTxOnly() or Protocol2PacketHandler::regWriteTxRx()\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @return communication results which come from Protocol2PacketHandler::txRxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  int action          (PortHandler *port, uint8_t id);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that makes Dynamixel reboot\n  /// @description The function makes an instruction packet with INST_REBOOT,\n  /// @description transmits the packet with Protocol2PacketHandler::txRxPacket(),\n  /// @description then Dynamixel reboots.\n  /// @description During reboot, its LED will blink.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param error Dynamixel hardware error\n  /// @return COMM_NOT_AVAILABLE\n  ////////////////////////////////////////////////////////////////////////////////\n  int reboot          (PortHandler *port, uint8_t id, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that reset multi-turn revolution information of Dynamixel\n  /// @description The function makes an instruction packet with INST_CLEAR,\n  /// @description transmits the packet with Protocol2PacketHandler::txRxPacket().\n  /// @description Applied Products : MX with Protocol 2.0 (Firmware v42 or above),\n  /// @description Dynamixel X-series (Firmware v42 or above).\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from Protocol2PacketHandler::txRxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  int clearMultiTurn  (PortHandler *port, uint8_t id, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that makes Dynamixel reset as it was produced in the factory\n  /// @description The function makes an instruction packet with INST_FACTORY_RESET,\n  /// @description transmits the packet with Protocol2PacketHandler::txRxPacket().\n  /// @description Be careful of the use.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param option Reset option (0xFF for reset all values / 0x01 for reset all values except ID / 0x02 for reset all values except ID and Baudrate)\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from Protocol2PacketHandler::txRxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  int factoryReset    (PortHandler *port, uint8_t id, uint8_t option, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits INST_READ instruction packet\n  /// @description The function makes an instruction packet with INST_READ,\n  /// @description transmits the packet with Protocol2PacketHandler::txPacket().\n  /// @description It breaks out\n  /// @description when it tries to transmit to BROADCAST_ID\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for read\n  /// @param length Length of the data for read\n  /// @return COMM_NOT_AVAILABLE\n  /// @return   when it tries to transmit to BROADCAST_ID\n  /// @return or the other communication results which come from Protocol2PacketHandler::txPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  int readTx          (PortHandler *port, uint8_t id, uint16_t address, uint16_t length);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that receives the packet and reads the data in the packet\n  /// @description The function receives the packet which might be come by previous INST_READ instruction packet transmission,\n  /// @description gets the data from the packet.\n  /// @param port PortHandler instance\n  /// @param length Length of the data for read\n  /// @param data Data extracted from the packet\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from Protocol2PacketHandler::rxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  int readRx          (PortHandler *port, uint8_t id, uint16_t length, uint8_t *data, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits INST_READ instruction packet, and read data from received packet\n  /// @description The function makes an instruction packet with INST_READ,\n  /// @description transmits and receives the packet with Protocol2PacketHandler::txRxPacket(),\n  /// @description gets the data from the packet.\n  /// @description It breaks out\n  /// @description when it tries to transmit to BROADCAST_ID\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for read\n  /// @param length Length of the data for read\n  /// @param data Data extracted from the packet\n  /// @param error Dynamixel hardware error\n  /// @return COMM_NOT_AVAILABLE\n  /// @return   when it tries to transmit to BROADCAST_ID\n  /// @return or the other communication results which come from Protocol2PacketHandler::txRxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  int readTxRx        (PortHandler *port, uint8_t id, uint16_t address, uint16_t length, uint8_t *data, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls Protocol2PacketHandler::readTx() function for reading 1 byte data\n  /// @description The function calls Protocol2PacketHandler::readTx() function for reading 1 byte data\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for read\n  /// @return communication results which come from Protocol2PacketHandler::readTx()\n  ////////////////////////////////////////////////////////////////////////////////\n  int read1ByteTx     (PortHandler *port, uint8_t id, uint16_t address);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls Protocol2PacketHandler::readRx() function and reads 1 byte data on the packet\n  /// @description The function calls Protocol2PacketHandler::readRx() function,\n  /// @description gets 1 byte data from the packet.\n  /// @param port PortHandler instance\n  /// @param data Data extracted from the packet\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from Protocol2PacketHandler::readRx()\n  ////////////////////////////////////////////////////////////////////////////////\n  int read1ByteRx     (PortHandler *port, uint8_t id, uint8_t *data, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls Protocol2PacketHandler::readTxRx() function for reading 1 byte data\n  /// @description The function calls Protocol2PacketHandler::readTxRx(),\n  /// @description gets 1 byte data from the packet.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for read\n  /// @param length Length of the data for read\n  /// @param data Data extracted from the packet\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from Protocol2PacketHandler::txRxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  int read1ByteTxRx       (PortHandler *port, uint8_t id, uint16_t address, uint8_t *data, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls Protocol2PacketHandler::readTx() function for reading 2 byte data\n  /// @description The function calls Protocol2PacketHandler::readTx() function for reading 2 byte data\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for read\n  /// @return communication results which come from Protocol2PacketHandler::readTx()\n  ////////////////////////////////////////////////////////////////////////////////\n  int read2ByteTx     (PortHandler *port, uint8_t id, uint16_t address);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls Protocol2PacketHandler::readRx() function and reads 2 byte data on the packet\n  /// @description The function calls Protocol2PacketHandler::readRx() function,\n  /// @description gets 2 byte data from the packet.\n  /// @param port PortHandler instance\n  /// @param data Data extracted from the packet\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from Protocol2PacketHandler::readRx()\n  ////////////////////////////////////////////////////////////////////////////////\n  int read2ByteRx     (PortHandler *port, uint8_t id, uint16_t *data, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls Protocol2PacketHandler::readTxRx() function for reading 2 byte data\n  /// @description The function calls Protocol2PacketHandler::readTxRx(),\n  /// @description gets 2 byte data from the packet.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for read\n  /// @param length Length of the data for read\n  /// @param data Data extracted from the packet\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from Protocol2PacketHandler::txRxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  int read2ByteTxRx       (PortHandler *port, uint8_t id, uint16_t address, uint16_t *data, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls Protocol2PacketHandler::readTx() function for reading 4 byte data\n  /// @description The function calls Protocol2PacketHandler::readTx() function for reading 4 byte data\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for read\n  /// @return communication results which come from Protocol2PacketHandler::readTx()\n  ////////////////////////////////////////////////////////////////////////////////\n  int read4ByteTx     (PortHandler *port, uint8_t id, uint16_t address);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls Protocol2PacketHandler::readRx() function and reads 4 byte data on the packet\n  /// @description The function calls Protocol2PacketHandler::readRx() function,\n  /// @description gets 4 byte data from the packet.\n  /// @param port PortHandler instance\n  /// @param data Data extracted from the packet\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from Protocol2PacketHandler::readRx()\n  ////////////////////////////////////////////////////////////////////////////////\n  int read4ByteRx     (PortHandler *port, uint8_t id, uint32_t *data, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls Protocol2PacketHandler::readTxRx() function for reading 4 byte data\n  /// @description The function calls Protocol2PacketHandler::readTxRx(),\n  /// @description gets 4 byte data from the packet.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for read\n  /// @param length Length of the data for read\n  /// @param data Data extracted from the packet\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from Protocol2PacketHandler::txRxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  int read4ByteTxRx       (PortHandler *port, uint8_t id, uint16_t address, uint32_t *data, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits INST_WRITE instruction packet with the data for write\n  /// @description The function makes an instruction packet with INST_WRITE and the data for write,\n  /// @description transmits the packet with Protocol2PacketHandler::txPacket().\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for write\n  /// @param length Length of the data for write\n  /// @param data Data for write\n  /// @return communication results which come from Protocol2PacketHandler::txPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  int writeTxOnly     (PortHandler *port, uint8_t id, uint16_t address, uint16_t length, uint8_t *data);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits INST_WRITE instruction packet with the data for write, and receives the packet\n  /// @description The function makes an instruction packet with INST_WRITE and the data for write,\n  /// @description transmits and receives the packet with Protocol2PacketHandler::txRxPacket(),\n  /// @description gets the error from the packet.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for write\n  /// @param length Length of the data for write\n  /// @param data Data for write\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from Protocol2PacketHandler::txRxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  int writeTxRx           (PortHandler *port, uint8_t id, uint16_t address, uint16_t length, uint8_t *data, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls Protocol2PacketHandler::writeTxOnly() for writing 1 byte data\n  /// @description The function calls Protocol2PacketHandler::writeTxOnly() for writing 1 byte data.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for write\n  /// @param data Data for write\n  /// @return communication results which come from Protocol2PacketHandler::writeTxOnly()\n  ////////////////////////////////////////////////////////////////////////////////\n  int write1ByteTxOnly(PortHandler *port, uint8_t id, uint16_t address, uint8_t data);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls Protocol2PacketHandler::writeTxRx() for writing 1 byte data and receives the packet\n  /// @description The function calls Protocol2PacketHandler::writeTxRx() for writing 1 byte data and receves the packet,\n  /// @description gets the error from the packet.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for write\n  /// @param data Data for write\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from Protocol2PacketHandler::writeTxRx()\n  ////////////////////////////////////////////////////////////////////////////////\n  int write1ByteTxRx      (PortHandler *port, uint8_t id, uint16_t address, uint8_t data, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls Protocol2PacketHandler::writeTxOnly() for writing 2 byte data\n  /// @description The function calls Protocol2PacketHandler::writeTxOnly() for writing 2 byte data.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for write\n  /// @param data Data for write\n  /// @return communication results which come from Protocol2PacketHandler::writeTxOnly()\n  ////////////////////////////////////////////////////////////////////////////////\n  int write2ByteTxOnly(PortHandler *port, uint8_t id, uint16_t address, uint16_t data);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls Protocol2PacketHandler::writeTxRx() for writing 2 byte data and receives the packet\n  /// @description The function calls Protocol2PacketHandler::writeTxRx() for writing 2 byte data and receves the packet,\n  /// @description gets the error from the packet.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for write\n  /// @param data Data for write\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from Protocol2PacketHandler::writeTxRx()\n  ////////////////////////////////////////////////////////////////////////////////\n  int write2ByteTxRx      (PortHandler *port, uint8_t id, uint16_t address, uint16_t data, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls Protocol2PacketHandler::writeTxOnly() for writing 4 byte data\n  /// @description The function calls Protocol2PacketHandler::writeTxOnly() for writing 4 byte data.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for write\n  /// @param data Data for write\n  /// @return communication results which come from Protocol2PacketHandler::writeTxOnly()\n  ////////////////////////////////////////////////////////////////////////////////\n  int write4ByteTxOnly(PortHandler *port, uint8_t id, uint16_t address, uint32_t data);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that calls Protocol2PacketHandler::writeTxRx() for writing 4 byte data and receives the packet\n  /// @description The function calls Protocol2PacketHandler::writeTxRx() for writing 4 byte data and receves the packet,\n  /// @description gets the error from the packet.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for write\n  /// @param data Data for write\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from Protocol2PacketHandler::writeTxRx()\n  ////////////////////////////////////////////////////////////////////////////////\n  int write4ByteTxRx      (PortHandler *port, uint8_t id, uint16_t address, uint32_t data, uint8_t *error = 0);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits INST_REG_WRITE instruction packet with the data for writing on the Dynamixel register\n  /// @description The function makes an instruction packet with INST_REG_WRITE and the data for writing on the Dynamixel register,\n  /// @description transmits the packet with Protocol2PacketHandler::txPacket().\n  /// @description The data written in the register will act when INST_ACTION instruction packet is transmitted to the Dynamxel.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for write\n  /// @param length Length of the data for write\n  /// @param data Data for write\n  /// @return communication results which come from Protocol2PacketHandler::txPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  int regWriteTxOnly  (PortHandler *port, uint8_t id, uint16_t address, uint16_t length, uint8_t *data);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits INST_REG_WRITE instruction packet with the data for writing on the Dynamixel register, and receives the packet\n  /// @description The function makes an instruction packet with INST_REG_WRITE and the data for writing on the Dynamixel register,\n  /// @description transmits and receives the packet with Protocol2PacketHandler::txRxPacket(),\n  /// @description gets the error from the packet.\n  /// @description The data written in the register will act when INST_ACTION instruction packet is transmitted to the Dynamxel.\n  /// @param port PortHandler instance\n  /// @param id Dynamixel ID\n  /// @param address Address of the data for write\n  /// @param length Length of the data for write\n  /// @param data Data for write\n  /// @param error Dynamixel hardware error\n  /// @return communication results which come from Protocol2PacketHandler::txRxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  int regWriteTxRx        (PortHandler *port, uint8_t id, uint16_t address, uint16_t length, uint8_t *data, uint8_t *error = 0);\n\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits INST_SYNC_READ instruction packet\n  /// @description The function makes an instruction packet with INST_SYNC_READ,\n  /// @description transmits the packet with Protocol2PacketHandler::txPacket().\n  /// @param port PortHandler instance\n  /// @param start_address Address of the data for Sync Read\n  /// @param data_length Length of the data for Sync Read\n  /// @param param Parameter for Sync Read\n  /// @param param_length Length of the data for Sync Read\n  /// @return communication results which come from Protocol2PacketHandler::txPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  int syncReadTx      (PortHandler *port, uint16_t start_address, uint16_t data_length, uint8_t *param, uint16_t param_length);\n  // SyncReadRx   -> GroupSyncRead class\n  // SyncReadTxRx -> GroupSyncRead class\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits INST_SYNC_WRITE instruction packet\n  /// @description The function makes an instruction packet with INST_SYNC_WRITE,\n  /// @description transmits the packet with Protocol2PacketHandler::txRxPacket().\n  /// @param port PortHandler instance\n  /// @param start_address Address of the data for Sync Write\n  /// @param data_length Length of the data for Sync Write\n  /// @param param Parameter for Sync Write {ID1, DATA0, DATA1, ..., DATAn, ID2, DATA0, DATA1, ..., DATAn, ID3, DATA0, DATA1, ..., DATAn}\n  /// @param param_length Length of the data for Sync Write\n  /// @return communication results which come from Protocol2PacketHandler::txRxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  int syncWriteTxOnly (PortHandler *port, uint16_t start_address, uint16_t data_length, uint8_t *param, uint16_t param_length);\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits INST_BULK_READ instruction packet\n  /// @description The function makes an instruction packet with INST_BULK_READ,\n  /// @description transmits the packet with Protocol2PacketHandler::txPacket().\n  /// @param port PortHandler instance\n  /// @param param Parameter for Bulk Read {ID1, ADDR_L1, ADDR_H1, LEN_L1, LEN_H1, ID2, ADDR_L2, ADDR_H2, LEN_L2, LEN_H2, ...}\n  /// @param param_length Length of the data for Bulk Read\n  /// @return communication results which come from Protocol2PacketHandler::txPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  int bulkReadTx      (PortHandler *port, uint8_t *param, uint16_t param_length);\n  // BulkReadRx   -> GroupBulkRead class\n  // BulkReadTxRx -> GroupBulkRead class\n\n  ////////////////////////////////////////////////////////////////////////////////\n  /// @brief The function that transmits INST_BULK_WRITE instruction packet\n  /// @description The function makes an instruction packet with INST_BULK_WRITE,\n  /// @description transmits the packet with Protocol2PacketHandler::txRxPacket().\n  /// @param port PortHandler instance\n  /// @param param Parameter for Bulk Write {ID1, START_ADDR_L, START_ADDR_H, DATA_LEN_L, DATA_LEN_H, DATA0, DATA1, ..., DATAn, ID2, START_ADDR_L, START_ADDR_H, DATA_LEN_L, DATA_LEN_H, DATA0, DATA1, ..., DATAn}\n  /// @param param_length Length of the data for Bulk Write\n  /// @return communication results which come from Protocol2PacketHandler::txRxPacket()\n  ////////////////////////////////////////////////////////////////////////////////\n  int bulkWriteTxOnly (PortHandler *port, uint8_t *param, uint16_t param_length);\n};\n\n}\n\n\n#endif /* DYNAMIXEL_SDK_INCLUDE_DYNAMIXEL_SDK_PROTOCOL2PACKETHANDLER_H_ */\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelSDK/keywords.txt",
    "content": "#######################################\n# Syntax Coloring Map LatchClcd\n#######################################\n\n#######################################\n# Datatypes (KEYWORD1)\n#######################################\n\nDynamixelSDK\tKEYWORD1\n\n#######################################\n# Methods and Functions (KEYWORD2)\n#######################################\n#port handler\ngetPortHandler\tKEYWORD2\nopenPort\tKEYWORD2\nclosePort\tKEYWORD2\nclearPort\tKEYWORD2\nsetPortName\tKEYWORD2\ngetPortName\tKEYWORD2\nsetBaudRate\tKEYWORD2\ngetBaudRate\tKEYWORD2\ngetBytesAvailable\tKEYWORD2\nreadPort\tKEYWORD2\nwritePort\tKEYWORD2\nsetPacketTimeout\tKEYWORD2\nsetPacketTimeout\tKEYWORD2\nisPacketTimeout\tKEYWORD2\n#PORTHANDLER\ngetPacketHandler\tKEYWORD2\ngetProtocolVersion\tKEYWORD2\ngetTxRxResult\tKEYWORD2\ngetRxPacketError\tKEYWORD2\ntxPacket\tKEYWORD2\nrxPacket\tKEYWORD2\ntxRxPacket\tKEYWORD2\nping\tKEYWORD2\nbroadcastPing\tKEYWORD2\naction\tKEYWORD2\nreboot\tKEYWORD2\nfactoryReset\tKEYWORD2\nreadTx\tKEYWORD2\nreadRx\tKEYWORD2\nreadTxRx\tKEYWORD2read1ByteTx\tKEYWORD2\nread1ByteRx\tKEYWORD2\nread1ByteTxRx\tKEYWORD2\nread2ByteTx\tKEYWORD2\nread2ByteRx\tKEYWORD2\nread2ByteTxRx\tKEYWORD2\nread4ByteTx\tKEYWORD2\nread4ByteRx\tKEYWORD2\nread4ByteTxRx\tKEYWORD2\nwriteTxOnly\tKEYWORD2\nwriteTxRx\tKEYWORD2write1ByteTxOnly\tKEYWORD2\nwrite1ByteTxRx\tKEYWORD2\nwrite2ByteTxOnly\tKEYWORD2\nwrite2ByteTxRx\tKEYWORD2\nwrite4ByteTxOnly\tKEYWORD2\nwrite4ByteTxRx\tKEYWORD2\nregWriteTxOnly\tKEYWORD2\nregWriteTxRx\tKEYWORD2\nsyncReadTx\tKEYWORD2\nsyncWriteTxOnly\tKEYWORD2\nbulkReadTx\tKEYWORD2\nbulkWriteTxOnly\tKEYWORD2\n\n#######################################\n# Constants (LITERAL1)\n#######################################\nINST_PING\tLITERAL1\nINST_READ\tLITERAL1\nINST_WRITE\tLITERAL1\nINST_REG_WRITE\tLITERAL1\nINST_ACTION\tLITERAL1\nINST_FACTORY_RESET\tLITERAL1\nINST_SYNC_WRITE\tLITERAL1\nINST_BULK_READ\tLITERAL1\nINST_REBOOT\tLITERAL1\nINST_STATUS\tLITERAL1\nINST_SYNC_READ\tLITERAL1\nINST_BULK_WRITE\tLITERAL1\nCOMM_SUCCESS\tLITERAL1\nCOMM_PORT_BUSY\tLITERAL1\nCOMM_TX_FAIL\tLITERAL1\nCOMM_RX_FAIL\tLITERAL1\nCOMM_TX_ERROR\tLITERAL1\nCOMM_RX_WAITING\tLITERAL1\nCOMM_RX_TIMEOUT\tLITERAL1\nCOMM_RX_CORRUPT\tLITERAL1\nCOMM_NOT_AVAILABLE\tLITERAL1\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelSDK/library.properties",
    "content": "name=DynamixelSDK\nversion=0.0.1\nauthor=ROBOTIS\nmaintainer=RoBOTIS\nsentence=DynamixelSDK for OpenCR\nparagraph=https://github.com/ROBOTIS-GIT/DynamixelSDK\ncategory=Device Control\nurl=https://github.com/ROBOTIS-GIT/DynamixelSDK\narchitectures=OpenCR\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelSDK/src/DynamixelSDK.h",
    "content": "#include \"../include/dynamixel_sdk/dynamixel_sdk.h\"\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelSDK/src/dynamixel_sdk/group_bulk_read.cpp",
    "content": "/*******************************************************************************\n* Copyright 2017 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Author: zerom, Ryu Woon Jung (Leon) */\n\n#include <stdio.h>\n#include <algorithm>\n\n#if defined(__linux__)\n#include \"group_bulk_read.h\"\n#elif defined(__APPLE__)\n#include \"group_bulk_read.h\"\n#elif defined(_WIN32) || defined(_WIN64)\n#define WINDLLEXPORT\n#include \"group_bulk_read.h\"\n#elif defined(ARDUINO) || defined(__OPENCR__) || defined(__OPENCM904__)\n#include \"../../include/dynamixel_sdk/group_bulk_read.h\"\n#endif\n\nusing namespace dynamixel;\n\nGroupBulkRead::GroupBulkRead(PortHandler *port, PacketHandler *ph)\n  : port_(port),\n    ph_(ph),\n    last_result_(false),\n    is_param_changed_(false),\n    param_(0)\n{\n  clearParam();\n}\n\nvoid GroupBulkRead::makeParam()\n{\n  if (id_list_.size() == 0)\n    return;\n\n  if (param_ != 0)\n    delete[] param_;\n  param_ = 0;\n\n  if (ph_->getProtocolVersion() == 1.0)\n  {\n    param_ = new uint8_t[id_list_.size() * 3];  // ID(1) + ADDR(1) + LENGTH(1)\n  }\n  else    // 2.0\n  {\n    param_ = new uint8_t[id_list_.size() * 5];  // ID(1) + ADDR(2) + LENGTH(2)\n  }\n\n  int idx = 0;\n  for (unsigned int i = 0; i < id_list_.size(); i++)\n  {\n    uint8_t id = id_list_[i];\n    if (ph_->getProtocolVersion() == 1.0)\n    {\n      param_[idx++] = (uint8_t)length_list_[id];    // LEN\n      param_[idx++] = id;                           // ID\n      param_[idx++] = (uint8_t)address_list_[id];   // ADDR\n    }\n    else    // 2.0\n    {\n      param_[idx++] = id;                               // ID\n      param_[idx++] = DXL_LOBYTE(address_list_[id]);    // ADDR_L\n      param_[idx++] = DXL_HIBYTE(address_list_[id]);    // ADDR_H\n      param_[idx++] = DXL_LOBYTE(length_list_[id]);     // LEN_L\n      param_[idx++] = DXL_HIBYTE(length_list_[id]);     // LEN_H\n    }\n  }\n}\n\nbool GroupBulkRead::addParam(uint8_t id, uint16_t start_address, uint16_t data_length)\n{\n  if (std::find(id_list_.begin(), id_list_.end(), id) != id_list_.end())   // id already exist\n    return false;\n\n  id_list_.push_back(id);\n  length_list_[id]    = data_length;\n  address_list_[id]   = start_address;\n  data_list_[id]      = new uint8_t[data_length];\n  error_list_[id]     = new uint8_t[1];\n\n  is_param_changed_   = true;\n  return true;\n}\n\nvoid GroupBulkRead::removeParam(uint8_t id)\n{\n  std::vector<uint8_t>::iterator it = std::find(id_list_.begin(), id_list_.end(), id);\n  if (it == id_list_.end())    // NOT exist\n    return;\n\n  id_list_.erase(it);\n  address_list_.erase(id);\n  length_list_.erase(id);\n  delete[] data_list_[id];\n  delete[] error_list_[id];\n  data_list_.erase(id);\n  error_list_.erase(id);\n\n  is_param_changed_   = true;\n}\n\nvoid GroupBulkRead::clearParam()\n{\n  if (id_list_.size() == 0)\n    return;\n\n  for (unsigned int i = 0; i < id_list_.size(); i++)\n  {\n    delete[] data_list_[id_list_[i]];\n    delete[] error_list_[id_list_[i]];\n  }\n\n  id_list_.clear();\n  address_list_.clear();\n  length_list_.clear();\n  data_list_.clear();\n  error_list_.clear();\n  if (param_ != 0)\n    delete[] param_;\n  param_ = 0;\n}\n\nint GroupBulkRead::txPacket()\n{\n  if (id_list_.size() == 0)\n    return COMM_NOT_AVAILABLE;\n\n  if (is_param_changed_ == true || param_ == 0)\n    makeParam();\n\n  if (ph_->getProtocolVersion() == 1.0)\n  {\n    return ph_->bulkReadTx(port_, param_, id_list_.size() * 3);\n  }\n  else    // 2.0\n  {\n    return ph_->bulkReadTx(port_, param_, id_list_.size() * 5);\n  }\n}\n\nint GroupBulkRead::rxPacket()\n{\n  int cnt            = id_list_.size();\n  int result          = COMM_RX_FAIL;\n\n  last_result_ = false;\n\n  if (cnt == 0)\n    return COMM_NOT_AVAILABLE;\n\n  for (int i = 0; i < cnt; i++)\n  {\n    uint8_t id = id_list_[i];\n\n    result = ph_->readRx(port_, id, length_list_[id], data_list_[id], error_list_[id]);\n    if (result != COMM_SUCCESS)\n      return result;\n  }\n\n  if (result == COMM_SUCCESS)\n    last_result_ = true;\n\n  return result;\n}\n\nint GroupBulkRead::txRxPacket()\n{\n  int result         = COMM_TX_FAIL;\n\n  result = txPacket();\n  if (result != COMM_SUCCESS)\n    return result;\n\n  return rxPacket();\n}\n\nbool GroupBulkRead::isAvailable(uint8_t id, uint16_t address, uint16_t data_length)\n{\n  uint16_t start_addr;\n\n  if (last_result_ == false || data_list_.find(id) == data_list_.end())\n    return false;\n\n  start_addr = address_list_[id];\n\n  if (address < start_addr || start_addr + length_list_[id] - data_length < address)\n    return false;\n\n  return true;\n}\n\nuint32_t GroupBulkRead::getData(uint8_t id, uint16_t address, uint16_t data_length)\n{\n  if (isAvailable(id, address, data_length) == false)\n    return 0;\n\n  uint16_t start_addr = address_list_[id];\n\n  switch(data_length)\n  {\n    case 1:\n      return data_list_[id][address - start_addr];\n\n    case 2:\n      return DXL_MAKEWORD(data_list_[id][address - start_addr], data_list_[id][address - start_addr + 1]);\n\n    case 4:\n      return DXL_MAKEDWORD(DXL_MAKEWORD(data_list_[id][address - start_addr + 0], data_list_[id][address - start_addr + 1]),\n                           DXL_MAKEWORD(data_list_[id][address - start_addr + 2], data_list_[id][address - start_addr + 3]));\n\n    default:\n      return 0;\n  }\n}\n\nbool GroupBulkRead::getError(uint8_t id, uint8_t* error)\n{\n  // TODO : check protocol version, last_result_, data_list\n  // if (last_result_ == false || error_list_.find(id) == error_list_.end())\n\n  error[0] = error_list_[id][0];\n\n  if (error[0] != 0)\n  {\n    return true;\n  }\n  else\n  {\n    return false;\n  }\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelSDK/src/dynamixel_sdk/group_bulk_write.cpp",
    "content": "/*******************************************************************************\n* Copyright 2017 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Author: zerom, Ryu Woon Jung (Leon) */\n\n#include <algorithm>\n\n#if defined(__linux__)\n#include \"group_bulk_write.h\"\n#elif defined(__APPLE__)\n#include \"group_bulk_write.h\"\n#elif defined(_WIN32) || defined(_WIN64)\n#define WINDLLEXPORT\n#include \"group_bulk_write.h\"\n#elif defined(ARDUINO) || defined(__OPENCR__) || defined(__OPENCM904__)\n#include \"../../include/dynamixel_sdk/group_bulk_write.h\"\n#endif\n\nusing namespace dynamixel;\n\nGroupBulkWrite::GroupBulkWrite(PortHandler *port, PacketHandler *ph)\n  : port_(port),\n    ph_(ph),\n    is_param_changed_(false),\n    param_(0),\n    param_length_(0)\n{\n  clearParam();\n}\n\nvoid GroupBulkWrite::makeParam()\n{\n  if (ph_->getProtocolVersion() == 1.0 || id_list_.size() == 0)\n    return;\n\n  if (param_ != 0)\n    delete[] param_;\n  param_ = 0;\n\n  param_length_ = 0;\n  for (unsigned int i = 0; i < id_list_.size(); i++)\n    param_length_ += 1 + 2 + 2 + length_list_[id_list_[i]];\n\n  param_ = new uint8_t[param_length_];\n\n  int idx = 0;\n  for (unsigned int i = 0; i < id_list_.size(); i++)\n  {\n    uint8_t id = id_list_[i];\n    if (data_list_[id] == 0)\n      return;\n\n    param_[idx++] = id;\n    param_[idx++] = DXL_LOBYTE(address_list_[id]);\n    param_[idx++] = DXL_HIBYTE(address_list_[id]);\n    param_[idx++] = DXL_LOBYTE(length_list_[id]);\n    param_[idx++] = DXL_HIBYTE(length_list_[id]);\n    for (int c = 0; c < length_list_[id]; c++)\n      param_[idx++] = (data_list_[id])[c];\n  }\n}\n\nbool GroupBulkWrite::addParam(uint8_t id, uint16_t start_address, uint16_t data_length, uint8_t *data)\n{\n  if (ph_->getProtocolVersion() == 1.0)\n    return false;\n\n  if (std::find(id_list_.begin(), id_list_.end(), id) != id_list_.end())   // id already exist\n    return false;\n\n  id_list_.push_back(id);\n  address_list_[id]   = start_address;\n  length_list_[id]    = data_length;\n  data_list_[id]      = new uint8_t[data_length];\n  for (int c = 0; c < data_length; c++)\n    data_list_[id][c] = data[c];\n\n  is_param_changed_   = true;\n  return true;\n}\nvoid GroupBulkWrite::removeParam(uint8_t id)\n{\n  if (ph_->getProtocolVersion() == 1.0)\n    return;\n\n  std::vector<uint8_t>::iterator it = std::find(id_list_.begin(), id_list_.end(), id);\n  if (it == id_list_.end())    // NOT exist\n    return;\n\n  id_list_.erase(it);\n  address_list_.erase(id);\n  length_list_.erase(id);\n  delete[] data_list_[id];\n  data_list_.erase(id);\n\n  is_param_changed_   = true;\n}\nbool GroupBulkWrite::changeParam(uint8_t id, uint16_t start_address, uint16_t data_length, uint8_t *data)\n{\n  if (ph_->getProtocolVersion() == 1.0)\n    return false;\n\n  std::vector<uint8_t>::iterator it = std::find(id_list_.begin(), id_list_.end(), id);\n  if (it == id_list_.end())    // NOT exist\n    return false;\n\n  address_list_[id]   = start_address;\n  length_list_[id]    = data_length;\n  delete[] data_list_[id];\n  data_list_[id]      = new uint8_t[data_length];\n  for (int c = 0; c < data_length; c++)\n    data_list_[id][c] = data[c];\n\n  is_param_changed_   = true;\n  return true;\n}\nvoid GroupBulkWrite::clearParam()\n{\n  if (ph_->getProtocolVersion() == 1.0 || id_list_.size() == 0)\n    return;\n\n  for (unsigned int i = 0; i < id_list_.size(); i++)\n    delete[] data_list_[id_list_[i]];\n\n  id_list_.clear();\n  address_list_.clear();\n  length_list_.clear();\n  data_list_.clear();\n  if (param_ != 0)\n    delete[] param_;\n  param_ = 0;\n}\nint GroupBulkWrite::txPacket()\n{\n  if (ph_->getProtocolVersion() == 1.0 || id_list_.size() == 0)\n    return COMM_NOT_AVAILABLE;\n\n  if (is_param_changed_ == true || param_ == 0)\n    makeParam();\n\n  return ph_->bulkWriteTxOnly(port_, param_, param_length_);\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelSDK/src/dynamixel_sdk/group_sync_read.cpp",
    "content": "/*******************************************************************************\n* Copyright 2017 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Author: zerom, Ryu Woon Jung (Leon) */\n\n#include <algorithm>\n\n#if defined(__linux__)\n#include \"group_sync_read.h\"\n#elif defined(__APPLE__)\n#include \"group_sync_read.h\"\n#elif defined(_WIN32) || defined(_WIN64)\n#define WINDLLEXPORT\n#include \"group_sync_read.h\"\n#elif defined(ARDUINO) || defined(__OPENCR__) || defined(__OPENCM904__)\n#include \"../../include/dynamixel_sdk/group_sync_read.h\"\n#endif\n\nusing namespace dynamixel;\n\nGroupSyncRead::GroupSyncRead(PortHandler *port, PacketHandler *ph, uint16_t start_address, uint16_t data_length)\n  : port_(port),\n    ph_(ph),\n    last_result_(false),\n    is_param_changed_(false),\n    param_(0),\n    start_address_(start_address),\n    data_length_(data_length)\n{\n  clearParam();\n}\n\nvoid GroupSyncRead::makeParam()\n{\n  if (ph_->getProtocolVersion() == 1.0 || id_list_.size() == 0)\n    return;\n\n  if (param_ != 0)\n    delete[] param_;\n  param_ = 0;\n\n  param_ = new uint8_t[id_list_.size() * 1];  // ID(1)\n\n  int idx = 0;\n  for (unsigned int i = 0; i < id_list_.size(); i++)\n    param_[idx++] = id_list_[i];\n}\n\nbool GroupSyncRead::addParam(uint8_t id)\n{\n  if (ph_->getProtocolVersion() == 1.0)\n    return false;\n\n  if (std::find(id_list_.begin(), id_list_.end(), id) != id_list_.end())   // id already exist\n    return false;\n\n  id_list_.push_back(id);\n  data_list_[id] = new uint8_t[data_length_];\n  error_list_[id] = new uint8_t[1];\n\n  is_param_changed_   = true;\n  return true;\n}\nvoid GroupSyncRead::removeParam(uint8_t id)\n{\n  if (ph_->getProtocolVersion() == 1.0)\n    return;\n\n  std::vector<uint8_t>::iterator it = std::find(id_list_.begin(), id_list_.end(), id);\n  if (it == id_list_.end())    // NOT exist\n    return;\n\n  id_list_.erase(it);\n  delete[] data_list_[id];\n  delete[] error_list_[id];\n  data_list_.erase(id);\n  error_list_.erase(id);\n\n  is_param_changed_   = true;\n}\nvoid GroupSyncRead::clearParam()\n{\n  if (ph_->getProtocolVersion() == 1.0 || id_list_.size() == 0)\n    return;\n\n  for (unsigned int i = 0; i < id_list_.size(); i++)\n  {\n    delete[] data_list_[id_list_[i]];\n    delete[] error_list_[id_list_[i]];\n  }\n\n  id_list_.clear();\n  data_list_.clear();\n  error_list_.clear();\n  if (param_ != 0)\n    delete[] param_;\n  param_ = 0;\n}\n\nint GroupSyncRead::txPacket()\n{\n  if (ph_->getProtocolVersion() == 1.0 || id_list_.size() == 0)\n    return COMM_NOT_AVAILABLE;\n\n  if (is_param_changed_ == true || param_ == 0)\n    makeParam();\n\n  return ph_->syncReadTx(port_, start_address_, data_length_, param_, (uint16_t)id_list_.size() * 1);\n}\n\nint GroupSyncRead::rxPacket()\n{\n  last_result_ = false;\n\n  if (ph_->getProtocolVersion() == 1.0)\n    return COMM_NOT_AVAILABLE;\n\n  int cnt            = id_list_.size();\n  int result         = COMM_RX_FAIL;\n\n  if (cnt == 0)\n    return COMM_NOT_AVAILABLE;\n\n  for (int i = 0; i < cnt; i++)\n  {\n    uint8_t id = id_list_[i];\n\n    result = ph_->readRx(port_, id, data_length_, data_list_[id], error_list_[id]);\n    if (result != COMM_SUCCESS)\n      return result;\n  }\n\n  if (result == COMM_SUCCESS)\n    last_result_ = true;\n\n  return result;\n}\n\nint GroupSyncRead::txRxPacket()\n{\n  if (ph_->getProtocolVersion() == 1.0)\n    return COMM_NOT_AVAILABLE;\n\n  int result         = COMM_TX_FAIL;\n\n  result = txPacket();\n  if (result != COMM_SUCCESS)\n    return result;\n\n  return rxPacket();\n}\n\nbool GroupSyncRead::isAvailable(uint8_t id, uint16_t address, uint16_t data_length)\n{\n  if (ph_->getProtocolVersion() == 1.0 || last_result_ == false || data_list_.find(id) == data_list_.end())\n    return false;\n\n  if (address < start_address_ || start_address_ + data_length_ - data_length < address)\n    return false;\n\n  return true;\n}\n\nuint32_t GroupSyncRead::getData(uint8_t id, uint16_t address, uint16_t data_length)\n{\n  if (isAvailable(id, address, data_length) == false)\n    return 0;\n\n  switch(data_length)\n  {\n    case 1:\n      return data_list_[id][address - start_address_];\n\n    case 2:\n      return DXL_MAKEWORD(data_list_[id][address - start_address_], data_list_[id][address - start_address_ + 1]);\n\n    case 4:\n      return DXL_MAKEDWORD(DXL_MAKEWORD(data_list_[id][address - start_address_ + 0], data_list_[id][address - start_address_ + 1]),\n                 DXL_MAKEWORD(data_list_[id][address - start_address_ + 2], data_list_[id][address - start_address_ + 3]));\n\n    default:\n      return 0;\n  }\n}\n\nbool GroupSyncRead::getError(uint8_t id, uint8_t* error)\n{\n  // TODO : check protocol version, last_result_, data_list\n  // if (ph_->getProtocolVersion() == 1.0 || last_result_ == false || error_list_.find(id) == error_list_.end())\n\n  error[0] = error_list_[id][0];\n\n  if (error[0] != 0)\n  {\n    return true;\n  }\n  else\n  {\n    return false;\n  }\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelSDK/src/dynamixel_sdk/group_sync_write.cpp",
    "content": "/*******************************************************************************\n* Copyright 2017 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Author: zerom, Ryu Woon Jung (Leon) */\n\n#include <algorithm>\n\n#if defined(__linux__)\n#include \"group_sync_write.h\"\n#elif defined(__APPLE__)\n#include \"group_sync_write.h\"\n#elif defined(_WIN32) || defined(_WIN64)\n#define WINDLLEXPORT\n#include \"group_sync_write.h\"\n#elif defined(ARDUINO) || defined(__OPENCR__) || defined(__OPENCM904__)\n#include \"../../include/dynamixel_sdk/group_sync_write.h\"\n#endif\n\nusing namespace dynamixel;\n\nGroupSyncWrite::GroupSyncWrite(PortHandler *port, PacketHandler *ph, uint16_t start_address, uint16_t data_length)\n  : port_(port),\n    ph_(ph),\n    is_param_changed_(false),\n    param_(0),\n    start_address_(start_address),\n    data_length_(data_length)\n{\n  clearParam();\n}\n\nvoid GroupSyncWrite::makeParam()\n{\n  if (id_list_.size() == 0) return;\n\n  if (param_ != 0)\n    delete[] param_;\n  param_ = 0;\n\n  param_ = new uint8_t[id_list_.size() * (1 + data_length_)]; // ID(1) + DATA(data_length)\n\n  int idx = 0;\n  for (unsigned int i = 0; i < id_list_.size(); i++)\n  {\n    uint8_t id = id_list_[i];\n    if (data_list_[id] == 0)\n      return;\n\n    param_[idx++] = id;\n    for (int c = 0; c < data_length_; c++)\n      param_[idx++] = (data_list_[id])[c];\n  }\n}\n\nbool GroupSyncWrite::addParam(uint8_t id, uint8_t *data)\n{\n  if (std::find(id_list_.begin(), id_list_.end(), id) != id_list_.end())   // id already exist\n    return false;\n\n  id_list_.push_back(id);\n  data_list_[id]    = new uint8_t[data_length_];\n  for (int c = 0; c < data_length_; c++)\n    data_list_[id][c] = data[c];\n\n  is_param_changed_   = true;\n  return true;\n}\n\nvoid GroupSyncWrite::removeParam(uint8_t id)\n{\n  std::vector<uint8_t>::iterator it = std::find(id_list_.begin(), id_list_.end(), id);\n  if (it == id_list_.end())    // NOT exist\n    return;\n\n  id_list_.erase(it);\n  delete[] data_list_[id];\n  data_list_.erase(id);\n\n  is_param_changed_   = true;\n}\n\nbool GroupSyncWrite::changeParam(uint8_t id, uint8_t *data)\n{\n  std::vector<uint8_t>::iterator it = std::find(id_list_.begin(), id_list_.end(), id);\n  if (it == id_list_.end())    // NOT exist\n    return false;\n\n  delete[] data_list_[id];\n  data_list_[id]    = new uint8_t[data_length_];\n  for (int c = 0; c < data_length_; c++)\n    data_list_[id][c] = data[c];\n\n  is_param_changed_   = true;\n  return true;\n}\n\nvoid GroupSyncWrite::clearParam()\n{\n  if (id_list_.size() == 0)\n    return;\n\n  for (unsigned int i = 0; i < id_list_.size(); i++)\n    delete[] data_list_[id_list_[i]];\n\n  id_list_.clear();\n  data_list_.clear();\n  if (param_ != 0)\n    delete[] param_;\n  param_ = 0;\n}\n\nint GroupSyncWrite::txPacket()\n{\n  if (id_list_.size() == 0)\n    return COMM_NOT_AVAILABLE;\n\n  if (is_param_changed_ == true || param_ == 0)\n    makeParam();\n\n  return ph_->syncWriteTxOnly(port_, start_address_, data_length_, param_, id_list_.size() * (1 + data_length_));\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelSDK/src/dynamixel_sdk/packet_handler.cpp",
    "content": "/*******************************************************************************\n* Copyright 2017 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Author: zerom, Ryu Woon Jung (Leon) */\n\n#if defined(__linux__)\n#include \"packet_handler.h\"\n#include \"protocol1_packet_handler.h\"\n#include \"protocol2_packet_handler.h\"\n#elif defined(__APPLE__)\n#include \"packet_handler.h\"\n#include \"protocol1_packet_handler.h\"\n#include \"protocol2_packet_handler.h\"\n#elif defined(_WIN32) || defined(_WIN64)\n#define WINDLLEXPORT\n#include \"packet_handler.h\"\n#include \"protocol1_packet_handler.h\"\n#include \"protocol2_packet_handler.h\"\n#elif defined(ARDUINO) || defined(__OPENCR__) || defined(__OPENCM904__)\n#include \"../../include/dynamixel_sdk/packet_handler.h\"\n#include \"../../include/dynamixel_sdk/protocol1_packet_handler.h\"\n#include \"../../include/dynamixel_sdk/protocol2_packet_handler.h\"\n#endif\n\nusing namespace dynamixel;\n\nPacketHandler *PacketHandler::getPacketHandler(float protocol_version)\n{\n  if (protocol_version == 1.0)\n  {\n    return (PacketHandler *)(Protocol1PacketHandler::getInstance());\n  }\n  else if (protocol_version == 2.0)\n  {\n    return (PacketHandler *)(Protocol2PacketHandler::getInstance());\n  }\n\n  return (PacketHandler *)(Protocol2PacketHandler::getInstance());\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelSDK/src/dynamixel_sdk/port_handler.cpp",
    "content": "/*******************************************************************************\n* Copyright 2017 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Author: zerom, Ryu Woon Jung (Leon) */\n\n#if defined(__linux__)\n#include \"port_handler.h\"\n#include \"port_handler_linux.h\"\n#elif defined(__APPLE__)\n#include \"port_handler.h\"\n#include \"port_handler_mac.h\"\n#elif defined(_WIN32) || defined(_WIN64)\n#define WINDLLEXPORT\n#include \"port_handler.h\"\n#include \"port_handler_windows.h\"\n#elif defined(ARDUINO) || defined(__OPENCR__) || defined(__OPENCM904__)\n#include \"../../include/dynamixel_sdk/port_handler.h\"\n#include \"../../include/dynamixel_sdk/port_handler_arduino.h\"\n#endif\n\nusing namespace dynamixel;\n\nPortHandler *PortHandler::getPortHandler(const char *port_name)\n{\n#if defined(__linux__)\n  return (PortHandler *)(new PortHandlerLinux(port_name));\n#elif defined(__APPLE__)\n  return (PortHandler *)(new PortHandlerMac(port_name));\n#elif defined(_WIN32) || defined(_WIN64)\n  return (PortHandler *)(new PortHandlerWindows(port_name));\n#elif defined(ARDUINO) || defined(__OPENCR__) || defined(__OPENCM904__)\n  return (PortHandler *)(new PortHandlerArduino(port_name));\n#endif\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelSDK/src/dynamixel_sdk/port_handler_arduino.cpp",
    "content": "/*******************************************************************************\n* Copyright 2017 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Author: Ryu Woon Jung (Leon) */\n\n#if defined(ARDUINO) || defined(__OPENCR__) || defined(__OPENCM904__)\n\n#include <Arduino.h>\n\n\n#include \"../../include/dynamixel_sdk/port_handler_arduino.h\"\n\n#if defined (__OPENCR__)\n#define DYNAMIXEL_SERIAL  Serial3\n#endif\n\n#define LATENCY_TIMER     4  // msec (USB latency timer)\n\nusing namespace dynamixel;\n\nPortHandlerArduino::PortHandlerArduino(const char *port_name)\n  : baudrate_(DEFAULT_BAUDRATE_),\n    packet_start_time_(0.0),\n    packet_timeout_(0.0),\n    tx_time_per_byte(0.0)\n{\n  is_using_ = false;\n  setPortName(port_name);\n\n#if defined(__OPENCR__)\n  pinMode(BDPIN_DXL_PWR_EN, OUTPUT);\n\n  setPowerOff();\n#elif defined(__OPENCM904__)\n  if (port_name[0] == '1')\n  {\n    socket_fd_ = 0;\n    p_dxl_serial = &Serial1;\n  }\n  else if (port_name[0] == '2')\n  {\n    socket_fd_ = 1;\n    p_dxl_serial = &Serial2;\n  }\n  else if (port_name[0] == '3')\n  {\n    socket_fd_ = 2;\n    p_dxl_serial = &Serial3;\n  }\n  else\n  {\n    socket_fd_ = 0;\n    p_dxl_serial = &Serial1;\n  }\n\n  drv_dxl_begin(socket_fd_);\n#endif\n\n  setTxDisable();\n}\n\nbool PortHandlerArduino::openPort()\n{\n#if defined(__OPENCR__)\n  pinMode(BDPIN_DXL_PWR_EN, OUTPUT);\n\n  setPowerOn();\n  delay(1000);\n#endif\n\n  return setBaudRate(baudrate_);\n}\n\nvoid PortHandlerArduino::closePort()\n{\n  setPowerOff();\n}\n\nvoid PortHandlerArduino::clearPort()\n{\n#if defined(__OPENCR__)\n  DYNAMIXEL_SERIAL.flush();\n  // Clear out all data from the input queue. \n  while (DYNAMIXEL_SERIAL.available())\n  {\n    DYNAMIXEL_SERIAL.read();\n  }\n#elif defined(__OPENCM904__)\n  p_dxl_serial->flush();\n  while (p_dxl_serial->available())\n  {\n    p_dxl_serial->read();\n  }\n#endif\n}\n\nvoid PortHandlerArduino::setPortName(const char *port_name)\n{\n  strcpy(port_name_, port_name);\n}\n\nchar *PortHandlerArduino::getPortName()\n{\n  return port_name_;\n}\n\nbool PortHandlerArduino::setBaudRate(const int baudrate)\n{\n  baudrate_ = checkBaudrateAvailable(baudrate);\n\n  if (baudrate_ == -1)\n    return false;\n\n  setupPort(baudrate_);\n\n  return true;\n}\n\nint PortHandlerArduino::getBaudRate()\n{\n  return baudrate_;\n}\n\nint PortHandlerArduino::getBytesAvailable()\n{\n  int bytes_available;\n\n#if defined(__OPENCR__)\n  bytes_available = DYNAMIXEL_SERIAL.available();\n#elif defined(__OPENCM904__)\n  bytes_available = p_dxl_serial->available();\n#endif\n\n  return bytes_available;\n}\n\nint PortHandlerArduino::readPort(uint8_t *packet, int length)\n{\n  int rx_length;\n\n#if defined(__OPENCR__)\n  rx_length = DYNAMIXEL_SERIAL.available();\n#elif defined(__OPENCM904__)\n  rx_length = p_dxl_serial->available();\n#endif\n\n  if (rx_length > length)\n    rx_length = length;\n\n  for (int i = 0; i < rx_length; i++)\n  {\n#if defined(__OPENCR__)\n    packet[i] = DYNAMIXEL_SERIAL.read();\n#elif defined(__OPENCM904__)\n    packet[i] = p_dxl_serial->read();\n#endif\n  }\n\n  return rx_length;\n}\n\nint PortHandlerArduino::writePort(uint8_t *packet, int length)\n{\n  int length_written;\n\n  setTxEnable();\n\n#if defined(__OPENCR__)\n  length_written = DYNAMIXEL_SERIAL.write(packet, length);\n#elif defined(__OPENCM904__)\n  length_written = p_dxl_serial->write(packet, length);\n#endif\n\n  setTxDisable();\n\n  return length_written;\n}\n\nvoid PortHandlerArduino::setPacketTimeout(uint16_t packet_length)\n{\n  packet_start_time_  = getCurrentTime();\n  packet_timeout_     = (tx_time_per_byte * (double)packet_length) + (LATENCY_TIMER * 2.0) + 2.0;\n}\n\nvoid PortHandlerArduino::setPacketTimeout(double msec)\n{\n  packet_start_time_  = getCurrentTime();\n  packet_timeout_     = msec;\n}\n\nbool PortHandlerArduino::isPacketTimeout()\n{\n  if (getTimeSinceStart() > packet_timeout_)\n  {\n    packet_timeout_ = 0;\n    return true;\n  }\n\n  return false;\n}\n\ndouble PortHandlerArduino::getCurrentTime()\n{\n  return (double)millis();\n}\n\ndouble PortHandlerArduino::getTimeSinceStart()\n{\n  double elapsed_time;\n\n  elapsed_time = getCurrentTime() - packet_start_time_;\n  if (elapsed_time < 0.0)\n    packet_start_time_ = getCurrentTime();\n\n  return elapsed_time;\n}\n\nbool PortHandlerArduino::setupPort(int baudrate)\n{\n#if defined(__OPENCR__)\n  DYNAMIXEL_SERIAL.begin(baudrate);\n#elif defined(__OPENCM904__)\n  p_dxl_serial->setDxlMode(true);\n  p_dxl_serial->begin(baudrate);\n#endif\n\n  delay(100);\n\n  tx_time_per_byte = (1000.0 / (double)baudrate) * 10.0;\n  return true;\n}\n\nint PortHandlerArduino::checkBaudrateAvailable(int baudrate)\n{\n  switch(baudrate)\n  {\n    case 9600:\n      return 9600;\n    case 57600:\n      return 57600;\n    case 115200:\n      return 115200;\n    case 1000000:\n      return 1000000;\n    case 2000000:\n      return 2000000;\n    case 3000000:\n      return 3000000;\n    case 4000000:\n      return 4000000;\n    case 4500000:\n      return 4500000;\n    default:\n      return -1;\n  }\n}\n\nvoid PortHandlerArduino::setPowerOn()\n{\n#if defined(__OPENCR__)\n  digitalWrite(BDPIN_DXL_PWR_EN, HIGH);\n#endif\n}\n\nvoid PortHandlerArduino::setPowerOff()\n{\n#if defined(__OPENCR__)\n  digitalWrite(BDPIN_DXL_PWR_EN, LOW);\n#endif\n}\n\nvoid PortHandlerArduino::setTxEnable()\n{\n#if defined(__OPENCR__)\n  drv_dxl_tx_enable(TRUE);\n#elif defined(__OPENCM904__)\n  drv_dxl_tx_enable(socket_fd_, TRUE);\n#endif\n}\n\nvoid PortHandlerArduino::setTxDisable()\n{\n#if defined(__OPENCR__)\n#ifdef SERIAL_WRITES_NON_BLOCKING\n  DYNAMIXEL_SERIAL.flush(); // make sure it completes before we disable... \n#endif\n  drv_dxl_tx_enable(FALSE);\n\n#elif defined(__OPENCM904__)\n#ifdef SERIAL_WRITES_NON_BLOCKING\n  p_dxl_serial->flush();\n#endif\n  drv_dxl_tx_enable(socket_fd_, FALSE);\n#endif\n}\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelSDK/src/dynamixel_sdk/port_handler_linux.cpp",
    "content": "/*******************************************************************************\n* Copyright 2017 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Author: zerom, Ryu Woon Jung (Leon) */\n\n#if defined(__linux__)\n\n#include <stdio.h>\n#include <fcntl.h>\n#include <string.h>\n#include <unistd.h>\n#include <termios.h>\n#include <time.h>\n#include <sys/time.h>\n#include <sys/ioctl.h>\n#include <linux/serial.h>\n\n#include \"port_handler_linux.h\"\n\n#define LATENCY_TIMER  16  // msec (USB latency timer)\n                           // You should adjust the latency timer value. From the version Ubuntu 16.04.2, the default latency timer of the usb serial is '16 msec'.\n                           // When you are going to use sync / bulk read, the latency timer should be loosen.\n                           // the lower latency timer value, the faster communication speed.\n\n                           // Note:\n                           // You can check its value by:\n                           // $ cat /sys/bus/usb-serial/devices/ttyUSB0/latency_timer\n                           //\n                           // If you think that the communication is too slow, type following after plugging the usb in to change the latency timer\n                           //\n                           // Method 1. Type following (you should do this everytime when the usb once was plugged out or the connection was dropped)\n                           // $ echo 1 | sudo tee /sys/bus/usb-serial/devices/ttyUSB0/latency_timer\n                           // $ cat /sys/bus/usb-serial/devices/ttyUSB0/latency_timer\n                           //\n                           // Method 2. If you want to set it as be done automatically, and don't want to do above everytime, make rules file in /etc/udev/rules.d/. For example,\n                           // $ echo ACTION==\\\"add\\\", SUBSYSTEM==\\\"usb-serial\\\", DRIVER==\\\"ftdi_sio\\\", ATTR{latency_timer}=\\\"1\\\" > 99-dynamixelsdk-usb.rules\n                           // $ sudo cp ./99-dynamixelsdk-usb.rules /etc/udev/rules.d/\n                           // $ sudo udevadm control --reload-rules\n                           // $ sudo udevadm trigger --action=add\n                           // $ cat /sys/bus/usb-serial/devices/ttyUSB0/latency_timer\n                           //\n                           // or if you have another good idea that can be an alternatives,\n                           // please give us advice via github issue https://github.com/ROBOTIS-GIT/DynamixelSDK/issues\n\nusing namespace dynamixel;\n\nPortHandlerLinux::PortHandlerLinux(const char *port_name)\n  : socket_fd_(-1),\n    baudrate_(DEFAULT_BAUDRATE_),\n    packet_start_time_(0.0),\n    packet_timeout_(0.0),\n    tx_time_per_byte(0.0)\n{\n  is_using_ = false;\n  setPortName(port_name);\n}\n\nbool PortHandlerLinux::openPort()\n{\n  return setBaudRate(baudrate_);\n}\n\nvoid PortHandlerLinux::closePort()\n{\n  if(socket_fd_ != -1)\n    close(socket_fd_);\n  socket_fd_ = -1;\n}\n\nvoid PortHandlerLinux::clearPort()\n{\n  tcflush(socket_fd_, TCIFLUSH);\n}\n\nvoid PortHandlerLinux::setPortName(const char *port_name)\n{\n  strcpy(port_name_, port_name);\n}\n\nchar *PortHandlerLinux::getPortName()\n{\n  return port_name_;\n}\n\n// TODO: baud number ??\nbool PortHandlerLinux::setBaudRate(const int baudrate)\n{\n  int baud = getCFlagBaud(baudrate);\n\n  closePort();\n\n  if(baud <= 0)   // custom baudrate\n  {\n    setupPort(B38400);\n    baudrate_ = baudrate;\n    return setCustomBaudrate(baudrate);\n  }\n  else\n  {\n    baudrate_ = baudrate;\n    return setupPort(baud);\n  }\n}\n\nint PortHandlerLinux::getBaudRate()\n{\n  return baudrate_;\n}\n\nint PortHandlerLinux::getBytesAvailable()\n{\n  int bytes_available;\n  ioctl(socket_fd_, FIONREAD, &bytes_available);\n  return bytes_available;\n}\n\nint PortHandlerLinux::readPort(uint8_t *packet, int length)\n{\n  return read(socket_fd_, packet, length);\n}\n\nint PortHandlerLinux::writePort(uint8_t *packet, int length)\n{\n  return write(socket_fd_, packet, length);\n}\n\nvoid PortHandlerLinux::setPacketTimeout(uint16_t packet_length)\n{\n  packet_start_time_  = getCurrentTime();\n  packet_timeout_     = (tx_time_per_byte * (double)packet_length) + (LATENCY_TIMER * 2.0) + 2.0;\n}\n\nvoid PortHandlerLinux::setPacketTimeout(double msec)\n{\n  packet_start_time_  = getCurrentTime();\n  packet_timeout_     = msec;\n}\n\nbool PortHandlerLinux::isPacketTimeout()\n{\n  if(getTimeSinceStart() > packet_timeout_)\n  {\n    packet_timeout_ = 0;\n    return true;\n  }\n  return false;\n}\n\ndouble PortHandlerLinux::getCurrentTime()\n{\n\tstruct timespec tv;\n\tclock_gettime(CLOCK_REALTIME, &tv);\n\treturn ((double)tv.tv_sec * 1000.0 + (double)tv.tv_nsec * 0.001 * 0.001);\n}\n\ndouble PortHandlerLinux::getTimeSinceStart()\n{\n  double time;\n\n  time = getCurrentTime() - packet_start_time_;\n  if(time < 0.0)\n    packet_start_time_ = getCurrentTime();\n\n  return time;\n}\n\nbool PortHandlerLinux::setupPort(int cflag_baud)\n{\n  struct termios newtio;\n\n  socket_fd_ = open(port_name_, O_RDWR|O_NOCTTY|O_NONBLOCK);\n  if(socket_fd_ < 0)\n  {\n    printf(\"[PortHandlerLinux::SetupPort] Error opening serial port!\\n\");\n    return false;\n  }\n\n  bzero(&newtio, sizeof(newtio)); // clear struct for new port settings\n\n  newtio.c_cflag = cflag_baud | CS8 | CLOCAL | CREAD;\n  newtio.c_iflag = IGNPAR;\n  newtio.c_oflag      = 0;\n  newtio.c_lflag      = 0;\n  newtio.c_cc[VTIME]  = 0;\n  newtio.c_cc[VMIN]   = 0;\n\n  // clean the buffer and activate the settings for the port\n  tcflush(socket_fd_, TCIFLUSH);\n  tcsetattr(socket_fd_, TCSANOW, &newtio);\n\n  tx_time_per_byte = (1000.0 / (double)baudrate_) * 10.0;\n  return true;\n}\n\nbool PortHandlerLinux::setCustomBaudrate(int speed)\n{\n  // try to set a custom divisor\n  struct serial_struct ss;\n  if(ioctl(socket_fd_, TIOCGSERIAL, &ss) != 0)\n  {\n    printf(\"[PortHandlerLinux::SetCustomBaudrate] TIOCGSERIAL failed!\\n\");\n    return false;\n  }\n\n  ss.flags = (ss.flags & ~ASYNC_SPD_MASK) | ASYNC_SPD_CUST;\n  ss.custom_divisor = (ss.baud_base + (speed / 2)) / speed;\n  int closest_speed = ss.baud_base / ss.custom_divisor;\n\n  if(closest_speed < speed * 98 / 100 || closest_speed > speed * 102 / 100)\n  {\n    printf(\"[PortHandlerLinux::SetCustomBaudrate] Cannot set speed to %d, closest is %d \\n\", speed, closest_speed);\n    return false;\n  }\n\n  if(ioctl(socket_fd_, TIOCSSERIAL, &ss) < 0)\n  {\n    printf(\"[PortHandlerLinux::SetCustomBaudrate] TIOCSSERIAL failed!\\n\");\n    return false;\n  }\n\n  tx_time_per_byte = (1000.0 / (double)speed) * 10.0;\n  return true;\n}\n\nint PortHandlerLinux::getCFlagBaud(int baudrate)\n{\n  switch(baudrate)\n  {\n    case 9600:\n      return B9600;\n    case 19200:\n      return B19200;\n    case 38400:\n      return B38400;\n    case 57600:\n      return B57600;\n    case 115200:\n      return B115200;\n    case 230400:\n      return B230400;\n    case 460800:\n      return B460800;\n    case 500000:\n      return B500000;\n    case 576000:\n      return B576000;\n    case 921600:\n      return B921600;\n    case 1000000:\n      return B1000000;\n    case 1152000:\n      return B1152000;\n    case 1500000:\n      return B1500000;\n    case 2000000:\n      return B2000000;\n    case 2500000:\n      return B2500000;\n    case 3000000:\n      return B3000000;\n    case 3500000:\n      return B3500000;\n    case 4000000:\n      return B4000000;\n    default:\n      return -1;\n  }\n}\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelSDK/src/dynamixel_sdk/port_handler_mac.cpp",
    "content": "/*******************************************************************************\n* Copyright 2017 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Author: Ryu Woon Jung (Leon) */\n\n#if defined(__APPLE__)\n\n#include <stdio.h>\n#include <fcntl.h>\n#include <string.h>\n#include <unistd.h>\n#include <termios.h>\n#include <time.h>\n#include <sys/time.h>\n#include <sys/ioctl.h>\n\n#ifdef __MACH__\n#include <mach/clock.h>\n#include <mach/mach.h>\n#endif\n\n#include \"port_handler_mac.h\"\n\n#define LATENCY_TIMER   16  // msec (USB latency timer)\n                            // You should adjust the latency timer value.\n                            // When you are going to use sync / bulk read, the latency timer should be loosen.\n                            // the lower latency timer value, the faster communication speed.\n\n                            // Note:\n                            // You can either change its value by following:\n                            // http://www.ftdichip.com/Support/Documents/TechnicalNotes/TN_105%20Adding%20Support%20for%20New%20FTDI%20Devices%20to%20Mac%20Driver.pdf\n\nusing namespace dynamixel;\n\nPortHandlerMac::PortHandlerMac(const char *port_name)\n  : socket_fd_(-1),\n    baudrate_(DEFAULT_BAUDRATE_),\n    packet_start_time_(0.0),\n    packet_timeout_(0.0),\n    tx_time_per_byte(0.0)\n{\n  is_using_ = false;\n  setPortName(port_name);\n}\n\nbool PortHandlerMac::openPort()\n{\n  return setBaudRate(baudrate_);\n}\n\nvoid PortHandlerMac::closePort()\n{\n  if(socket_fd_ != -1)\n    close(socket_fd_);\n  socket_fd_ = -1;\n}\n\nvoid PortHandlerMac::clearPort()\n{\n  tcflush(socket_fd_, TCIFLUSH);\n}\n\nvoid PortHandlerMac::setPortName(const char *port_name)\n{\n  strcpy(port_name_, port_name);\n}\n\nchar *PortHandlerMac::getPortName()\n{\n  return port_name_;\n}\n\n// TODO: baud number ??\nbool PortHandlerMac::setBaudRate(const int baudrate)\n{\n  int baud = getCFlagBaud(baudrate);\n\n  closePort();\n\n  if(baud <= 0)   // custom baudrate\n  {\n    setupPort(B38400);\n    baudrate_ = baudrate;\n    return setCustomBaudrate(baudrate);\n  }\n  else\n  {\n    baudrate_ = baudrate;\n    return setupPort(baud);\n  }\n}\n\nint PortHandlerMac::getBaudRate()\n{\n  return baudrate_;\n}\n\nint PortHandlerMac::getBytesAvailable()\n{\n  int bytes_available;\n  ioctl(socket_fd_, FIONREAD, &bytes_available);\n  return bytes_available;\n}\n\nint PortHandlerMac::readPort(uint8_t *packet, int length)\n{\n  return read(socket_fd_, packet, length);\n}\n\nint PortHandlerMac::writePort(uint8_t *packet, int length)\n{\n  return write(socket_fd_, packet, length);\n}\n\nvoid PortHandlerMac::setPacketTimeout(uint16_t packet_length)\n{\n  packet_start_time_  = getCurrentTime();\n  packet_timeout_     = (tx_time_per_byte * (double)packet_length) + (LATENCY_TIMER * 2.0) + 2.0;\n}\n\nvoid PortHandlerMac::setPacketTimeout(double msec)\n{\n  packet_start_time_  = getCurrentTime();\n  packet_timeout_     = msec;\n}\n\nbool PortHandlerMac::isPacketTimeout()\n{\n  if(getTimeSinceStart() > packet_timeout_)\n  {\n    packet_timeout_ = 0;\n    return true;\n  }\n  return false;\n}\n\ndouble PortHandlerMac::getCurrentTime()\n{\n  struct timespec tv;\n#ifdef __MACH__ // OS X does not have clock_gettime, so here uses clock_get_time\n  clock_serv_t cclock;\n  mach_timespec_t mts;\n  host_get_clock_service(mach_host_self(), CALENDAR_CLOCK, &cclock);\n  clock_get_time(cclock, &mts);\n  mach_port_deallocate(mach_task_self(), cclock);\n  tv.tv_sec = mts.tv_sec;\n  tv.tv_nsec = mts.tv_nsec;\n#else\n  clock_gettime(CLOCK_REALTIME, &tv);\n#endif\n  return ((double)tv.tv_sec * 1000.0 + (double)tv.tv_nsec * 0.001 * 0.001);\n}\n\ndouble PortHandlerMac::getTimeSinceStart()\n{\n  double time;\n\n  time = getCurrentTime() - packet_start_time_;\n  if(time < 0.0)\n    packet_start_time_ = getCurrentTime();\n\n  return time;\n}\n\nbool PortHandlerMac::setupPort(int cflag_baud)\n{\n  struct termios newtio;\n\n  socket_fd_ = open(port_name_, O_RDWR|O_NOCTTY|O_NONBLOCK);\n  if(socket_fd_ < 0)\n  {\n    printf(\"[PortHandlerMac::SetupPort] Error opening serial port!\\n\");\n    return false;\n  }\n\n  bzero(&newtio, sizeof(newtio)); // clear struct for new port settings\n\n  newtio.c_cflag = CS8 | CLOCAL | CREAD;\n  newtio.c_iflag = IGNPAR;\n  newtio.c_oflag      = 0;\n  newtio.c_lflag      = 0;\n  newtio.c_cc[VTIME]  = 0;\n  newtio.c_cc[VMIN]   = 0;\n  cfsetispeed(&newtio, cflag_baud);\n  cfsetospeed(&newtio, cflag_baud);\n\n  // clean the buffer and activate the settings for the port\n  tcflush(socket_fd_, TCIFLUSH);\n  tcsetattr(socket_fd_, TCSANOW, &newtio);\n\n  tx_time_per_byte = (1000.0 / (double)baudrate_) * 10.0;\n  return true;\n}\n\nbool PortHandlerMac::setCustomBaudrate(int speed)\n{\n  printf(\"[PortHandlerMac::SetCustomBaudrate] Not supported on Mac!\\n\");\n  return false;\n}\n\nint PortHandlerMac::getCFlagBaud(int baudrate)\n{\n  switch(baudrate)\n  {\n    case 9600:\n      return B9600;\n    case 19200:\n      return B19200;\n    case 38400:\n      return B38400;\n    case 57600:\n      return B57600;\n    case 115200:\n      return B115200;\n    case 230400:\n      return B230400;\n    // Mac OS doesn't support over B230400\n    // case 460800:\n    //   return B460800;\n    // case 500000:\n    //   return B500000;\n    // case 576000:\n    //   return B576000;\n    // case 921600:\n    //   return B921600;\n    // case 1000000:\n    //   return B1000000;\n    // case 1152000:\n    //   return B1152000;\n    // case 1500000:\n    //   return B1500000;\n    // case 2000000:\n    //   return B2000000;\n    // case 2500000:\n    //   return B2500000;\n    // case 3000000:\n    //   return B3000000;\n    // case 3500000:\n    //   return B3500000;\n    // case 4000000:\n    //   return B4000000;\n    default:\n      return -1;\n  }\n}\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelSDK/src/dynamixel_sdk/port_handler_windows.cpp",
    "content": "/*******************************************************************************\n* Copyright 2017 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Author: Ryu Woon Jung (Leon) */\n\n#if defined(_WIN32) || defined(_WIN64)\n#define WINDLLEXPORT\n\n#include \"port_handler_windows.h\"\n\n#include <stdio.h>\n#include <string.h>\n#include <time.h>\n\n#define LATENCY_TIMER  16 // msec (USB latency timer)\n                          // You should adjust the latency timer value. In Windows, the default latency timer of the usb serial is '16 msec'.\n                          // When you are going to use sync / bulk read, the latency timer should be loosen.\n                          // the lower latency timer value, the faster communication speed.\n\n                          // Note:\n                          // You can either checking or changing its value by:\n                          // [Device Manager] -> [Port (COM & LPT)] -> the port you use but starts with COMx-> mouse right click -> properties\n                          // -> [port settings] -> [details] -> change response time from 16 to the value you need\n\nusing namespace dynamixel;\n\nPortHandlerWindows::PortHandlerWindows(const char *port_name)\n  : serial_handle_(INVALID_HANDLE_VALUE),\n  baudrate_(DEFAULT_BAUDRATE_),\n  packet_start_time_(0.0),\n  packet_timeout_(0.0),\n  tx_time_per_byte_(0.0)\n{\n  is_using_ = false;\n\n  char buffer[15];\n  sprintf_s(buffer, sizeof(buffer), \"\\\\\\\\.\\\\%s\", port_name);\n  setPortName(buffer);\n}\n\nbool PortHandlerWindows::openPort()\n{\n  return setBaudRate(baudrate_);\n}\n\nvoid PortHandlerWindows::closePort()\n{\n  if (serial_handle_ != INVALID_HANDLE_VALUE)\n  {\n    CloseHandle(serial_handle_);\n    serial_handle_ = INVALID_HANDLE_VALUE;\n  }\n}\n\nvoid PortHandlerWindows::clearPort()\n{\n  PurgeComm(serial_handle_, PURGE_RXABORT | PURGE_RXCLEAR);\n}\n\nvoid PortHandlerWindows::setPortName(const char *port_name)\n{\n  strcpy_s(port_name_, sizeof(port_name_), port_name);\n}\n\nchar *PortHandlerWindows::getPortName()\n{\n  return port_name_;\n}\n\nbool PortHandlerWindows::setBaudRate(const int baudrate)\n{\n  closePort();\n\n  baudrate_ = baudrate;\n  return setupPort(baudrate);\n}\n\nint PortHandlerWindows::getBaudRate()\n{\n  return baudrate_;\n}\n\nint PortHandlerWindows::getBytesAvailable()\n{\n  DWORD retbyte = 2;\n  BOOL res = DeviceIoControl(serial_handle_, GENERIC_READ | GENERIC_WRITE, NULL, 0, 0, 0, &retbyte, (LPOVERLAPPED)NULL);\n\n  printf(\"%d\", (int)res);\n  return (int)retbyte;\n}\n\nint PortHandlerWindows::readPort(uint8_t *packet, int length)\n{\n  DWORD dwRead = 0;\n\n  if (ReadFile(serial_handle_, packet, (DWORD)length, &dwRead, NULL) == FALSE)\n    return -1;\n\n  return (int)dwRead;\n}\n\nint PortHandlerWindows::writePort(uint8_t *packet, int length)\n{\n  DWORD dwWrite = 0;\n\n  if (WriteFile(serial_handle_, packet, (DWORD)length, &dwWrite, NULL) == FALSE)\n    return -1;\n\n  return (int)dwWrite;\n}\n\nvoid PortHandlerWindows::setPacketTimeout(uint16_t packet_length)\n{\n  packet_start_time_ = getCurrentTime();\n  packet_timeout_ = (tx_time_per_byte_ * (double)packet_length) + (LATENCY_TIMER * 2.0) + 2.0;\n}\n\nvoid PortHandlerWindows::setPacketTimeout(double msec)\n{\n  packet_start_time_ = getCurrentTime();\n  packet_timeout_ = msec;\n}\n\nbool PortHandlerWindows::isPacketTimeout()\n{\n  if (getTimeSinceStart() > packet_timeout_)\n  {\n    packet_timeout_ = 0;\n    return true;\n  }\n  return false;\n}\n\ndouble PortHandlerWindows::getCurrentTime()\n{\n  QueryPerformanceCounter(&counter_);\n  QueryPerformanceFrequency(&freq_);\n  return (double)counter_.QuadPart / (double)freq_.QuadPart * 1000.0;\n}\n\ndouble PortHandlerWindows::getTimeSinceStart()\n{\n  double time;\n\n  time = getCurrentTime() - packet_start_time_;\n  if (time < 0.0) packet_start_time_ = getCurrentTime();\n\n  return time;\n}\n\nbool PortHandlerWindows::setupPort(int baudrate)\n{\n  DCB dcb;\n  COMMTIMEOUTS timeouts;\n  DWORD dwError;\n\n  closePort();\n\n  serial_handle_ = CreateFileA(port_name_, GENERIC_READ | GENERIC_WRITE, 0, NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL, NULL);\n  if (serial_handle_ == INVALID_HANDLE_VALUE)\n  {\n    printf(\"[PortHandlerWindows::SetupPort] Error opening serial port!\\n\");\n    return false;\n  }\n\n  dcb.DCBlength = sizeof(DCB);\n  if (GetCommState(serial_handle_, &dcb) == FALSE)\n    goto DXL_HAL_OPEN_ERROR;\n\n  // Set baudrate\n  dcb.BaudRate = (DWORD)baudrate;\n  dcb.ByteSize = 8;                    // Data bit = 8bit\n  dcb.Parity = NOPARITY;             // No parity\n  dcb.StopBits = ONESTOPBIT;           // Stop bit = 1\n  dcb.fParity = NOPARITY;             // No Parity check\n  dcb.fBinary = 1;                    // Binary mode\n  dcb.fNull = 0;                    // Get Null byte\n  dcb.fAbortOnError = 0;\n  dcb.fErrorChar = 0;\n  // Not using XOn/XOff\n  dcb.fOutX = 0;\n  dcb.fInX = 0;\n  // Not using H/W flow control\n  dcb.fDtrControl = DTR_CONTROL_DISABLE;\n  dcb.fRtsControl = RTS_CONTROL_DISABLE;\n  dcb.fDsrSensitivity = 0;\n  dcb.fOutxDsrFlow = 0;\n  dcb.fOutxCtsFlow = 0;\n\n  if (SetCommState(serial_handle_, &dcb) == FALSE)\n    goto DXL_HAL_OPEN_ERROR;\n\n  if (SetCommMask(serial_handle_, 0) == FALSE) // Not using Comm event\n    goto DXL_HAL_OPEN_ERROR;\n  if (SetupComm(serial_handle_, 4096, 4096) == FALSE) // Buffer size (Rx,Tx)\n    goto DXL_HAL_OPEN_ERROR;\n  if (PurgeComm(serial_handle_, PURGE_TXABORT | PURGE_TXCLEAR | PURGE_RXABORT | PURGE_RXCLEAR) == FALSE) // Clear buffer\n    goto DXL_HAL_OPEN_ERROR;\n  if (ClearCommError(serial_handle_, &dwError, NULL) == FALSE)\n    goto DXL_HAL_OPEN_ERROR;\n\n  if (GetCommTimeouts(serial_handle_, &timeouts) == FALSE)\n    goto DXL_HAL_OPEN_ERROR;\n  // Timeout (Not using timeout)\n  // Immediatly return\n  timeouts.ReadIntervalTimeout = 0;\n  timeouts.ReadTotalTimeoutMultiplier = 0;\n  timeouts.ReadTotalTimeoutConstant = 1; // must not be zero.\n  timeouts.WriteTotalTimeoutMultiplier = 0;\n  timeouts.WriteTotalTimeoutConstant = 0;\n  if (SetCommTimeouts(serial_handle_, &timeouts) == FALSE)\n    goto DXL_HAL_OPEN_ERROR;\n\n  tx_time_per_byte_ = (1000.0 / (double)baudrate_) * 10.0;\n  return true;\n\nDXL_HAL_OPEN_ERROR:\n  closePort();\n  return false;\n}\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelSDK/src/dynamixel_sdk/protocol1_packet_handler.cpp",
    "content": "/*******************************************************************************\n* Copyright 2017 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Author: zerom, Ryu Woon Jung (Leon) */\n\n#if defined(__linux__)\n#include \"protocol1_packet_handler.h\"\n#elif defined(__APPLE__)\n#include \"protocol1_packet_handler.h\"\n#elif defined(_WIN32) || defined(_WIN64)\n#define WINDLLEXPORT\n#include \"protocol1_packet_handler.h\"\n#elif defined(ARDUINO) || defined(__OPENCR__) || defined(__OPENCM904__)\n#include \"../../include/dynamixel_sdk/protocol1_packet_handler.h\"\n#endif\n\n#include <string.h>\n#include <stdlib.h>\n\n#define TXPACKET_MAX_LEN    (250)\n#define RXPACKET_MAX_LEN    (250)\n\n///////////////// for Protocol 1.0 Packet /////////////////\n#define PKT_HEADER0             0\n#define PKT_HEADER1             1\n#define PKT_ID                  2\n#define PKT_LENGTH              3\n#define PKT_INSTRUCTION         4\n#define PKT_ERROR               4\n#define PKT_PARAMETER0          5\n\n///////////////// Protocol 1.0 Error bit /////////////////\n#define ERRBIT_VOLTAGE          1       // Supplied voltage is out of the range (operating volatage set in the control table)\n#define ERRBIT_ANGLE            2       // Goal position is written out of the range (from CW angle limit to CCW angle limit)\n#define ERRBIT_OVERHEAT         4       // Temperature is out of the range (operating temperature set in the control table)\n#define ERRBIT_RANGE            8       // Command(setting value) is out of the range for use.\n#define ERRBIT_CHECKSUM         16      // Instruction packet checksum is incorrect.\n#define ERRBIT_OVERLOAD         32      // The current load cannot be controlled by the set torque.\n#define ERRBIT_INSTRUCTION      64      // Undefined instruction or delivering the action command without the reg_write command.\n\nusing namespace dynamixel;\n\nProtocol1PacketHandler *Protocol1PacketHandler::unique_instance_ = new Protocol1PacketHandler();\n\nProtocol1PacketHandler::Protocol1PacketHandler() { }\n\nconst char *Protocol1PacketHandler::getTxRxResult(int result)\n{\n  switch(result)\n  {\n    case COMM_SUCCESS:\n      return \"[TxRxResult] Communication success.\";\n\n    case COMM_PORT_BUSY:\n      return \"[TxRxResult] Port is in use!\";\n\n    case COMM_TX_FAIL:\n      return \"[TxRxResult] Failed transmit instruction packet!\";\n\n    case COMM_RX_FAIL:\n      return \"[TxRxResult] Failed get status packet from device!\";\n\n    case COMM_TX_ERROR:\n      return \"[TxRxResult] Incorrect instruction packet!\";\n\n    case COMM_RX_WAITING:\n      return \"[TxRxResult] Now recieving status packet!\";\n\n    case COMM_RX_TIMEOUT:\n      return \"[TxRxResult] There is no status packet!\";\n\n    case COMM_RX_CORRUPT:\n      return \"[TxRxResult] Incorrect status packet!\";\n\n    case COMM_NOT_AVAILABLE:\n      return \"[TxRxResult] Protocol does not support This function!\";\n\n    default:\n      return \"\";\n  }\n}\n\nconst char *Protocol1PacketHandler::getRxPacketError(uint8_t error)\n{\n  if (error & ERRBIT_VOLTAGE)\n    return \"[RxPacketError] Input voltage error!\";\n\n  if (error & ERRBIT_ANGLE)\n    return \"[RxPacketError] Angle limit error!\";\n\n  if (error & ERRBIT_OVERHEAT)\n    return \"[RxPacketError] Overheat error!\";\n\n  if (error & ERRBIT_RANGE)\n    return \"[RxPacketError] Out of range error!\";\n\n  if (error & ERRBIT_CHECKSUM)\n    return \"[RxPacketError] Checksum error!\";\n\n  if (error & ERRBIT_OVERLOAD)\n    return \"[RxPacketError] Overload error!\";\n\n  if (error & ERRBIT_INSTRUCTION)\n    return \"[RxPacketError] Instruction code error!\";\n\n  return \"\";\n}\n\nint Protocol1PacketHandler::txPacket(PortHandler *port, uint8_t *txpacket)\n{\n  uint8_t checksum               = 0;\n  uint8_t total_packet_length    = txpacket[PKT_LENGTH] + 4; // 4: HEADER0 HEADER1 ID LENGTH\n  uint8_t written_packet_length  = 0;\n\n  if (port->is_using_)\n    return COMM_PORT_BUSY;\n  port->is_using_ = true;\n\n  // check max packet length\n  if (total_packet_length > TXPACKET_MAX_LEN)\n  {\n    port->is_using_ = false;\n    return COMM_TX_ERROR;\n  }\n\n  // make packet header\n  txpacket[PKT_HEADER0]   = 0xFF;\n  txpacket[PKT_HEADER1]   = 0xFF;\n\n  // add a checksum to the packet\n  for (uint16_t idx = 2; idx < total_packet_length - 1; idx++)   // except header, checksum\n    checksum += txpacket[idx];\n  txpacket[total_packet_length - 1] = ~checksum;\n\n  // tx packet\n  port->clearPort();\n  written_packet_length = port->writePort(txpacket, total_packet_length);\n  if (total_packet_length != written_packet_length)\n  {\n    port->is_using_ = false;\n    return COMM_TX_FAIL;\n  }\n\n  return COMM_SUCCESS;\n}\n\nint Protocol1PacketHandler::rxPacket(PortHandler *port, uint8_t *rxpacket)\n{\n  int     result         = COMM_TX_FAIL;\n\n  uint8_t checksum       = 0;\n  uint8_t rx_length      = 0;\n  uint8_t wait_length    = 6;    // minimum length (HEADER0 HEADER1 ID LENGTH ERROR CHKSUM)\n\n  while(true)\n  {\n    rx_length += port->readPort(&rxpacket[rx_length], wait_length - rx_length);\n    if (rx_length >= wait_length)\n    {\n      uint8_t idx = 0;\n\n      // find packet header\n      for (idx = 0; idx < (rx_length - 1); idx++)\n      {\n        if (rxpacket[idx] == 0xFF && rxpacket[idx+1] == 0xFF)\n          break;\n      }\n\n      if (idx == 0)   // found at the beginning of the packet\n      {\n        if (rxpacket[PKT_ID] > 0xFD ||                  // unavailable ID\n            rxpacket[PKT_LENGTH] > RXPACKET_MAX_LEN ||  // unavailable Length\n            rxpacket[PKT_ERROR] > 0x7F)                 // unavailable Error\n        {\n            // remove the first byte in the packet\n            for (uint16_t s = 0; s < rx_length - 1; s++)\n              rxpacket[s] = rxpacket[1 + s];\n            //memcpy(&rxpacket[0], &rxpacket[idx], rx_length - idx);\n            rx_length -= 1;\n            continue;\n        }\n\n        // re-calculate the exact length of the rx packet\n        if (wait_length != rxpacket[PKT_LENGTH] + PKT_LENGTH + 1)\n        {\n          wait_length = rxpacket[PKT_LENGTH] + PKT_LENGTH + 1;\n          continue;\n        }\n\n        if (rx_length < wait_length)\n        {\n          // check timeout\n          if (port->isPacketTimeout() == true)\n          {\n            if (rx_length == 0)\n            {\n              result = COMM_RX_TIMEOUT;\n            }\n            else\n            {\n              result = COMM_RX_CORRUPT;\n            }\n            break;\n          }\n          else\n          {\n            continue;\n          }\n        }\n\n        // calculate checksum\n        for (uint16_t i = 2; i < wait_length - 1; i++)   // except header, checksum\n          checksum += rxpacket[i];\n        checksum = ~checksum;\n\n        // verify checksum\n        if (rxpacket[wait_length - 1] == checksum)\n        {\n          result = COMM_SUCCESS;\n        }\n        else\n        {\n          result = COMM_RX_CORRUPT;\n        }\n        break;\n      }\n      else\n      {\n        // remove unnecessary packets\n        for (uint16_t s = 0; s < rx_length - idx; s++)\n          rxpacket[s] = rxpacket[idx + s];\n        //memcpy(&rxpacket[0], &rxpacket[idx], rx_length - idx);\n        rx_length -= idx;\n      }\n    }\n    else\n    {\n      // check timeout\n      if (port->isPacketTimeout() == true)\n      {\n        if (rx_length == 0)\n        {\n          result = COMM_RX_TIMEOUT;\n        }\n        else\n        {\n          result = COMM_RX_CORRUPT;\n        }\n        break;\n      }\n    }\n  }\n  port->is_using_ = false;\n\n  return result;\n}\n\n// NOT for BulkRead instruction\nint Protocol1PacketHandler::txRxPacket(PortHandler *port, uint8_t *txpacket, uint8_t *rxpacket, uint8_t *error)\n{\n  int result = COMM_TX_FAIL;\n\n  // tx packet\n  result = txPacket(port, txpacket);\n  if (result != COMM_SUCCESS)\n    return result;\n\n  // (Instruction == BulkRead) == this function is not available.\n  if(txpacket[PKT_INSTRUCTION] == INST_BULK_READ)\n    result = COMM_NOT_AVAILABLE;\n\n  // (ID == Broadcast ID) == no need to wait for status packet or not available\n  // (Instruction == action) == no need to wait for status packet\n  if (txpacket[PKT_ID] == BROADCAST_ID || txpacket[PKT_INSTRUCTION] == INST_ACTION)\n  {\n    port->is_using_ = false;\n    return result;\n  }\n\n  // set packet timeout\n  if (txpacket[PKT_INSTRUCTION] == INST_READ)\n  {\n    port->setPacketTimeout((uint16_t)(txpacket[PKT_PARAMETER0+1] + 6));\n  }\n  else\n  {\n    port->setPacketTimeout((uint16_t)6); // HEADER0 HEADER1 ID LENGTH ERROR CHECKSUM\n  }\n\n  // rx packet\n  do {\n    result = rxPacket(port, rxpacket);\n  } while (result == COMM_SUCCESS && txpacket[PKT_ID] != rxpacket[PKT_ID]);\n\n  if (result == COMM_SUCCESS && txpacket[PKT_ID] == rxpacket[PKT_ID])\n  {\n    if (error != 0)\n      *error = (uint8_t)rxpacket[PKT_ERROR];\n  }\n\n  return result;\n}\n\nint Protocol1PacketHandler::ping(PortHandler *port, uint8_t id, uint8_t *error)\n{\n  return ping(port, id, 0, error);\n}\n\nint Protocol1PacketHandler::ping(PortHandler *port, uint8_t id, uint16_t *model_number, uint8_t *error)\n{\n  int result                 = COMM_TX_FAIL;\n\n  uint8_t txpacket[6]         = {0};\n  uint8_t rxpacket[6]         = {0};\n\n  if (id >= BROADCAST_ID)\n    return COMM_NOT_AVAILABLE;\n\n  txpacket[PKT_ID]            = id;\n  txpacket[PKT_LENGTH]        = 2;\n  txpacket[PKT_INSTRUCTION]   = INST_PING;\n\n  result = txRxPacket(port, txpacket, rxpacket, error);\n  if (result == COMM_SUCCESS && model_number != 0)\n  {\n    uint8_t data_read[2] = {0};\n    result = readTxRx(port, id, 0, 2, data_read);  // Address 0 : Model Number\n    if (result == COMM_SUCCESS) *model_number = DXL_MAKEWORD(data_read[0], data_read[1]);\n  }\n\n  return result;\n}\n\nint Protocol1PacketHandler::broadcastPing(PortHandler *port, std::vector<uint8_t> &id_list)\n{\n  return COMM_NOT_AVAILABLE;\n}\n\nint Protocol1PacketHandler::action(PortHandler *port, uint8_t id)\n{\n  uint8_t txpacket[6]         = {0};\n\n  txpacket[PKT_ID]            = id;\n  txpacket[PKT_LENGTH]        = 2;\n  txpacket[PKT_INSTRUCTION]   = INST_ACTION;\n\n  return txRxPacket(port, txpacket, 0);\n}\n\nint Protocol1PacketHandler::reboot(PortHandler *port, uint8_t id, uint8_t *error)\n{\n  return COMM_NOT_AVAILABLE;\n}\n\nint Protocol1PacketHandler::clearMultiTurn(PortHandler *port, uint8_t id, uint8_t *error)\n{\n  return COMM_NOT_AVAILABLE;\n}\n\nint Protocol1PacketHandler::factoryReset(PortHandler *port, uint8_t id, uint8_t option, uint8_t *error)\n{\n  uint8_t txpacket[6]         = {0};\n  uint8_t rxpacket[6]         = {0};\n\n  txpacket[PKT_ID]            = id;\n  txpacket[PKT_LENGTH]        = 2;\n  txpacket[PKT_INSTRUCTION]   = INST_FACTORY_RESET;\n\n  return txRxPacket(port, txpacket, rxpacket, error);\n}\n\nint Protocol1PacketHandler::readTx(PortHandler *port, uint8_t id, uint16_t address, uint16_t length)\n{\n  int result                 = COMM_TX_FAIL;\n\n  uint8_t txpacket[8]         = {0};\n\n  if (id >= BROADCAST_ID)\n    return COMM_NOT_AVAILABLE;\n\n  txpacket[PKT_ID]            = id;\n  txpacket[PKT_LENGTH]        = 4;\n  txpacket[PKT_INSTRUCTION]   = INST_READ;\n  txpacket[PKT_PARAMETER0+0]  = (uint8_t)address;\n  txpacket[PKT_PARAMETER0+1]  = (uint8_t)length;\n\n  result = txPacket(port, txpacket);\n\n  // set packet timeout\n  if (result == COMM_SUCCESS)\n    port->setPacketTimeout((uint16_t)(length+6));\n\n  return result;\n}\n\nint Protocol1PacketHandler::readRx(PortHandler *port, uint8_t id, uint16_t length, uint8_t *data, uint8_t *error)\n{\n  int result                  = COMM_TX_FAIL;\n  uint8_t *rxpacket           = (uint8_t *)malloc(RXPACKET_MAX_LEN); //(length+6);\n  //uint8_t *rxpacket         = new uint8_t[length+6];\n\n  do {\n    result = rxPacket(port, rxpacket);\n  } while (result == COMM_SUCCESS && rxpacket[PKT_ID] != id);\n\n  if (result == COMM_SUCCESS && rxpacket[PKT_ID] == id)\n  {\n    if (error != 0)\n    {\n      *error = (uint8_t)rxpacket[PKT_ERROR];\n    }\n    for (uint16_t s = 0; s < length; s++)\n    {\n      data[s] = rxpacket[PKT_PARAMETER0 + s];\n    }\n    //memcpy(data, &rxpacket[PKT_PARAMETER0], length);\n  }\n\n  free(rxpacket);\n  //delete[] rxpacket;\n  return result;\n}\n\nint Protocol1PacketHandler::readTxRx(PortHandler *port, uint8_t id, uint16_t address, uint16_t length, uint8_t *data, uint8_t *error)\n{\n  int result = COMM_TX_FAIL;\n\n  uint8_t txpacket[8]         = {0};\n  uint8_t *rxpacket           = (uint8_t *)malloc(RXPACKET_MAX_LEN);//(length+6);\n\n  if (id >= BROADCAST_ID)\n    return COMM_NOT_AVAILABLE;\n\n  txpacket[PKT_ID]            = id;\n  txpacket[PKT_LENGTH]        = 4;\n  txpacket[PKT_INSTRUCTION]   = INST_READ;\n  txpacket[PKT_PARAMETER0+0]  = (uint8_t)address;\n  txpacket[PKT_PARAMETER0+1]  = (uint8_t)length;\n\n  result = txRxPacket(port, txpacket, rxpacket, error);\n  if (result == COMM_SUCCESS)\n  {\n    if (error != 0)\n    {\n      *error = (uint8_t)rxpacket[PKT_ERROR];\n    }\n    for (uint16_t s = 0; s < length; s++)\n    {\n      data[s] = rxpacket[PKT_PARAMETER0 + s];\n    }\n    //memcpy(data, &rxpacket[PKT_PARAMETER0], length);\n  }\n\n  free(rxpacket);\n  //delete[] rxpacket;\n  return result;\n}\n\nint Protocol1PacketHandler::read1ByteTx(PortHandler *port, uint8_t id, uint16_t address)\n{\n  return readTx(port, id, address, 1);\n}\nint Protocol1PacketHandler::read1ByteRx(PortHandler *port, uint8_t id, uint8_t *data, uint8_t *error)\n{\n  uint8_t data_read[1] = {0};\n  int result = readRx(port, id, 1, data_read, error);\n  if (result == COMM_SUCCESS)\n    *data = data_read[0];\n  return result;\n}\nint Protocol1PacketHandler::read1ByteTxRx(PortHandler *port, uint8_t id, uint16_t address, uint8_t *data, uint8_t *error)\n{\n  uint8_t data_read[1] = {0};\n  int result = readTxRx(port, id, address, 1, data_read, error);\n  if (result == COMM_SUCCESS)\n    *data = data_read[0];\n  return result;\n}\n\nint Protocol1PacketHandler::read2ByteTx(PortHandler *port, uint8_t id, uint16_t address)\n{\n  return readTx(port, id, address, 2);\n}\nint Protocol1PacketHandler::read2ByteRx(PortHandler *port, uint8_t id, uint16_t *data, uint8_t *error)\n{\n  uint8_t data_read[2] = {0};\n  int result = readRx(port, id, 2, data_read, error);\n  if (result == COMM_SUCCESS)\n    *data = DXL_MAKEWORD(data_read[0], data_read[1]);\n  return result;\n}\nint Protocol1PacketHandler::read2ByteTxRx(PortHandler *port, uint8_t id, uint16_t address, uint16_t *data, uint8_t *error)\n{\n  uint8_t data_read[2] = {0};\n  int result = readTxRx(port, id, address, 2, data_read, error);\n  if (result == COMM_SUCCESS)\n    *data = DXL_MAKEWORD(data_read[0], data_read[1]);\n  return result;\n}\n\nint Protocol1PacketHandler::read4ByteTx(PortHandler *port, uint8_t id, uint16_t address)\n{\n  return readTx(port, id, address, 4);\n}\nint Protocol1PacketHandler::read4ByteRx(PortHandler *port, uint8_t id, uint32_t *data, uint8_t *error)\n{\n  uint8_t data_read[4] = {0};\n  int result = readRx(port, id, 4, data_read, error);\n  if (result == COMM_SUCCESS)\n    *data = DXL_MAKEDWORD(DXL_MAKEWORD(data_read[0], data_read[1]), DXL_MAKEWORD(data_read[2], data_read[3]));\n  return result;\n}\nint Protocol1PacketHandler::read4ByteTxRx(PortHandler *port, uint8_t id, uint16_t address, uint32_t *data, uint8_t *error)\n{\n  uint8_t data_read[4] = {0};\n  int result = readTxRx(port, id, address, 4, data_read, error);\n  if (result == COMM_SUCCESS)\n    *data = DXL_MAKEDWORD(DXL_MAKEWORD(data_read[0], data_read[1]), DXL_MAKEWORD(data_read[2], data_read[3]));\n  return result;\n}\n\nint Protocol1PacketHandler::writeTxOnly(PortHandler *port, uint8_t id, uint16_t address, uint16_t length, uint8_t *data)\n{\n  int result                 = COMM_TX_FAIL;\n\n  uint8_t *txpacket           = (uint8_t *)malloc(length+7);\n  //uint8_t *txpacket           = new uint8_t[length+7];\n\n  txpacket[PKT_ID]            = id;\n  txpacket[PKT_LENGTH]        = length+3;\n  txpacket[PKT_INSTRUCTION]   = INST_WRITE;\n  txpacket[PKT_PARAMETER0]    = (uint8_t)address;\n\n  for (uint16_t s = 0; s < length; s++)\n    txpacket[PKT_PARAMETER0+1+s] = data[s];\n  //memcpy(&txpacket[PKT_PARAMETER0+1], data, length);\n\n  result = txPacket(port, txpacket);\n  port->is_using_ = false;\n\n  free(txpacket);\n  //delete[] txpacket;\n  return result;\n}\n\nint Protocol1PacketHandler::writeTxRx(PortHandler *port, uint8_t id, uint16_t address, uint16_t length, uint8_t *data, uint8_t *error)\n{\n  int result                 = COMM_TX_FAIL;\n\n  uint8_t *txpacket           = (uint8_t *)malloc(length+7); //#6->7\n  //uint8_t *txpacket           = new uint8_t[length+7];\n  uint8_t rxpacket[6]         = {0};\n\n  txpacket[PKT_ID]            = id;\n  txpacket[PKT_LENGTH]        = length+3;\n  txpacket[PKT_INSTRUCTION]   = INST_WRITE;\n  txpacket[PKT_PARAMETER0]    = (uint8_t)address;\n\n  for (uint16_t s = 0; s < length; s++)\n    txpacket[PKT_PARAMETER0+1+s] = data[s];\n  //memcpy(&txpacket[PKT_PARAMETER0+1], data, length);\n\n  result = txRxPacket(port, txpacket, rxpacket, error);\n\n  free(txpacket);\n  //delete[] txpacket;\n  return result;\n}\n\nint Protocol1PacketHandler::write1ByteTxOnly(PortHandler *port, uint8_t id, uint16_t address, uint8_t data)\n{\n  uint8_t data_write[1] = { data };\n  return writeTxOnly(port, id, address, 1, data_write);\n}\nint Protocol1PacketHandler::write1ByteTxRx(PortHandler *port, uint8_t id, uint16_t address, uint8_t data, uint8_t *error)\n{\n  uint8_t data_write[1] = { data };\n  return writeTxRx(port, id, address, 1, data_write, error);\n}\n\nint Protocol1PacketHandler::write2ByteTxOnly(PortHandler *port, uint8_t id, uint16_t address, uint16_t data)\n{\n  uint8_t data_write[2] = { DXL_LOBYTE(data), DXL_HIBYTE(data) };\n  return writeTxOnly(port, id, address, 2, data_write);\n}\nint Protocol1PacketHandler::write2ByteTxRx(PortHandler *port, uint8_t id, uint16_t address, uint16_t data, uint8_t *error)\n{\n  uint8_t data_write[2] = { DXL_LOBYTE(data), DXL_HIBYTE(data) };\n  return writeTxRx(port, id, address, 2, data_write, error);\n}\n\nint Protocol1PacketHandler::write4ByteTxOnly(PortHandler *port, uint8_t id, uint16_t address, uint32_t data)\n{\n  uint8_t data_write[4] = { DXL_LOBYTE(DXL_LOWORD(data)), DXL_HIBYTE(DXL_LOWORD(data)), DXL_LOBYTE(DXL_HIWORD(data)), DXL_HIBYTE(DXL_HIWORD(data)) };\n  return writeTxOnly(port, id, address, 4, data_write);\n}\nint Protocol1PacketHandler::write4ByteTxRx(PortHandler *port, uint8_t id, uint16_t address, uint32_t data, uint8_t *error)\n{\n  uint8_t data_write[4] = { DXL_LOBYTE(DXL_LOWORD(data)), DXL_HIBYTE(DXL_LOWORD(data)), DXL_LOBYTE(DXL_HIWORD(data)), DXL_HIBYTE(DXL_HIWORD(data)) };\n  return writeTxRx(port, id, address, 4, data_write, error);\n}\n\nint Protocol1PacketHandler::regWriteTxOnly(PortHandler *port, uint8_t id, uint16_t address, uint16_t length, uint8_t *data)\n{\n  int result                 = COMM_TX_FAIL;\n\n  uint8_t *txpacket           = (uint8_t *)malloc(length+6);\n  //uint8_t *txpacket           = new uint8_t[length+6];\n\n  txpacket[PKT_ID]            = id;\n  txpacket[PKT_LENGTH]        = length+3;\n  txpacket[PKT_INSTRUCTION]   = INST_REG_WRITE;\n  txpacket[PKT_PARAMETER0]    = (uint8_t)address;\n\n  for (uint16_t s = 0; s < length; s++)\n    txpacket[PKT_PARAMETER0+1+s] = data[s];\n  //memcpy(&txpacket[PKT_PARAMETER0+1], data, length);\n\n  result = txPacket(port, txpacket);\n  port->is_using_ = false;\n\n  free(txpacket);\n  //delete[] txpacket;\n  return result;\n}\n\nint Protocol1PacketHandler::regWriteTxRx(PortHandler *port, uint8_t id, uint16_t address, uint16_t length, uint8_t *data, uint8_t *error)\n{\n  int result                 = COMM_TX_FAIL;\n\n  uint8_t *txpacket           = (uint8_t *)malloc(length+6);\n  //uint8_t *txpacket           = new uint8_t[length+6];\n  uint8_t rxpacket[6]         = {0};\n\n  txpacket[PKT_ID]            = id;\n  txpacket[PKT_LENGTH]        = length+3;\n  txpacket[PKT_INSTRUCTION]   = INST_REG_WRITE;\n  txpacket[PKT_PARAMETER0]    = (uint8_t)address;\n\n  for (uint16_t s = 0; s < length; s++)\n    txpacket[PKT_PARAMETER0+1+s] = data[s];\n  //memcpy(&txpacket[PKT_PARAMETER0+1], data, length);\n\n  result = txRxPacket(port, txpacket, rxpacket, error);\n\n  free(txpacket);\n  //delete[] txpacket;\n  return result;\n}\n\nint Protocol1PacketHandler::syncReadTx(PortHandler *port, uint16_t start_address, uint16_t data_length, uint8_t *param, uint16_t param_length)\n{\n  return COMM_NOT_AVAILABLE;\n}\n\nint Protocol1PacketHandler::syncWriteTxOnly(PortHandler *port, uint16_t start_address, uint16_t data_length, uint8_t *param, uint16_t param_length)\n{\n  int result                 = COMM_TX_FAIL;\n\n  uint8_t *txpacket           = (uint8_t *)malloc(param_length+8);\n  // 8: HEADER0 HEADER1 ID LEN INST START_ADDR DATA_LEN ... CHKSUM\n  //uint8_t *txpacket           = new uint8_t[param_length + 8];\n\n  txpacket[PKT_ID]            = BROADCAST_ID;\n  txpacket[PKT_LENGTH]        = param_length + 4; // 4: INST START_ADDR DATA_LEN ... CHKSUM\n  txpacket[PKT_INSTRUCTION]   = INST_SYNC_WRITE;\n  txpacket[PKT_PARAMETER0+0]  = start_address;\n  txpacket[PKT_PARAMETER0+1]  = data_length;\n\n  for (uint16_t s = 0; s < param_length; s++)\n    txpacket[PKT_PARAMETER0+2+s] = param[s];\n  //memcpy(&txpacket[PKT_PARAMETER0+2], param, param_length);\n\n  result = txRxPacket(port, txpacket, 0, 0);\n\n  free(txpacket);\n  //delete[] txpacket;\n  return result;\n}\n\nint Protocol1PacketHandler::bulkReadTx(PortHandler *port, uint8_t *param, uint16_t param_length)\n{\n  int result                 = COMM_TX_FAIL;\n\n  uint8_t *txpacket           = (uint8_t *)malloc(param_length+7);\n  // 7: HEADER0 HEADER1 ID LEN INST 0x00 ... CHKSUM\n  //uint8_t *txpacket           = new uint8_t[param_length + 7];\n\n  txpacket[PKT_ID]            = BROADCAST_ID;\n  txpacket[PKT_LENGTH]        = param_length + 3; // 3: INST 0x00 ... CHKSUM\n  txpacket[PKT_INSTRUCTION]   = INST_BULK_READ;\n  txpacket[PKT_PARAMETER0+0]  = 0x00;\n\n  for (uint16_t s = 0; s < param_length; s++)\n    txpacket[PKT_PARAMETER0+1+s] = param[s];\n  //memcpy(&txpacket[PKT_PARAMETER0+1], param, param_length);\n\n  result = txPacket(port, txpacket);\n  if (result == COMM_SUCCESS)\n  {\n    int wait_length = 0;\n    for (uint16_t i = 0; i < param_length; i += 3)\n      wait_length += param[i] + 7;\n    port->setPacketTimeout((uint16_t)wait_length);\n  }\n\n  free(txpacket);\n  //delete[] txpacket;\n  return result;\n}\n\nint Protocol1PacketHandler::bulkWriteTxOnly(PortHandler *port, uint8_t *param, uint16_t param_length)\n{\n  return COMM_NOT_AVAILABLE;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelSDK/src/dynamixel_sdk/protocol2_packet_handler.cpp",
    "content": "/*******************************************************************************\n* Copyright 2017 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Author: zerom, Ryu Woon Jung (Leon) */\n\n#if defined(__linux__)\n#include <unistd.h>\n#include \"protocol2_packet_handler.h\"\n#elif defined(__APPLE__)\n#include <unistd.h>\n#include \"protocol2_packet_handler.h\"\n#elif defined(_WIN32) || defined(_WIN64)\n#define WINDLLEXPORT\n#include <Windows.h>\n#include \"protocol2_packet_handler.h\"\n#elif defined(ARDUINO) || defined(__OPENCR__) || defined(__OPENCM904__)\n#include \"../../include/dynamixel_sdk/protocol2_packet_handler.h\"\n#endif\n\n#include <stdio.h>\n#include <string.h>\n#include <stdlib.h>\n\n#define TXPACKET_MAX_LEN    (1*1024)\n#define RXPACKET_MAX_LEN    (1*1024)\n\n///////////////// for Protocol 2.0 Packet /////////////////\n#define PKT_HEADER0             0\n#define PKT_HEADER1             1\n#define PKT_HEADER2             2\n#define PKT_RESERVED            3\n#define PKT_ID                  4\n#define PKT_LENGTH_L            5\n#define PKT_LENGTH_H            6\n#define PKT_INSTRUCTION         7\n#define PKT_ERROR               8\n#define PKT_PARAMETER0          8\n\n///////////////// Protocol 2.0 Error bit /////////////////\n#define ERRNUM_RESULT_FAIL      1       // Failed to process the instruction packet.\n#define ERRNUM_INSTRUCTION      2       // Instruction error\n#define ERRNUM_CRC              3       // CRC check error\n#define ERRNUM_DATA_RANGE       4       // Data range error\n#define ERRNUM_DATA_LENGTH      5       // Data length error\n#define ERRNUM_DATA_LIMIT       6       // Data limit error\n#define ERRNUM_ACCESS           7       // Access error\n\n#define ERRBIT_ALERT            128     //When the device has a problem, this bit is set to 1. Check \"Device Status Check\" value.\n\nusing namespace dynamixel;\n\nProtocol2PacketHandler *Protocol2PacketHandler::unique_instance_ = new Protocol2PacketHandler();\n\nProtocol2PacketHandler::Protocol2PacketHandler() { }\n\nconst char *Protocol2PacketHandler::getTxRxResult(int result)\n{\n  switch(result)\n  {\n    case COMM_SUCCESS:\n      return \"[TxRxResult] Communication success.\";\n\n    case COMM_PORT_BUSY:\n      return \"[TxRxResult] Port is in use!\";\n\n    case COMM_TX_FAIL:\n      return \"[TxRxResult] Failed transmit instruction packet!\";\n\n    case COMM_RX_FAIL:\n      return \"[TxRxResult] Failed get status packet from device!\";\n\n    case COMM_TX_ERROR:\n      return \"[TxRxResult] Incorrect instruction packet!\";\n\n    case COMM_RX_WAITING:\n      return \"[TxRxResult] Now recieving status packet!\";\n\n    case COMM_RX_TIMEOUT:\n      return \"[TxRxResult] There is no status packet!\";\n\n    case COMM_RX_CORRUPT:\n      return \"[TxRxResult] Incorrect status packet!\";\n\n    case COMM_NOT_AVAILABLE:\n      return \"[TxRxResult] Protocol does not support This function!\";\n\n    default:\n      return \"\";\n  }\n}\n\nconst char *Protocol2PacketHandler::getRxPacketError(uint8_t error)\n{\n  if (error & ERRBIT_ALERT)\n    return \"[RxPacketError] Hardware error occurred. Check the error at Control Table (Hardware Error Status)!\";\n\n  int not_alert_error = error & ~ERRBIT_ALERT;\n\n  switch(not_alert_error)\n  {\n    case 0:\n      return \"\";\n\n    case ERRNUM_RESULT_FAIL:\n      return \"[RxPacketError] Failed to process the instruction packet!\";\n\n    case ERRNUM_INSTRUCTION:\n      return \"[RxPacketError] Undefined instruction or incorrect instruction!\";\n\n    case ERRNUM_CRC:\n      return \"[RxPacketError] CRC doesn't match!\";\n\n    case ERRNUM_DATA_RANGE:\n      return \"[RxPacketError] The data value is out of range!\";\n\n    case ERRNUM_DATA_LENGTH:\n      return \"[RxPacketError] The data length does not match as expected!\";\n\n    case ERRNUM_DATA_LIMIT:\n      return \"[RxPacketError] The data value exceeds the limit value!\";\n\n    case ERRNUM_ACCESS:\n      return \"[RxPacketError] Writing or Reading is not available to target address!\";\n\n    default:\n      return \"[RxPacketError] Unknown error code!\";\n  }\n}\n\nunsigned short Protocol2PacketHandler::updateCRC(uint16_t crc_accum, uint8_t *data_blk_ptr, uint16_t data_blk_size)\n{\n  uint16_t i;\n  static const uint16_t crc_table[256] = {0x0000,\n  0x8005, 0x800F, 0x000A, 0x801B, 0x001E, 0x0014, 0x8011,\n  0x8033, 0x0036, 0x003C, 0x8039, 0x0028, 0x802D, 0x8027,\n  0x0022, 0x8063, 0x0066, 0x006C, 0x8069, 0x0078, 0x807D,\n  0x8077, 0x0072, 0x0050, 0x8055, 0x805F, 0x005A, 0x804B,\n  0x004E, 0x0044, 0x8041, 0x80C3, 0x00C6, 0x00CC, 0x80C9,\n  0x00D8, 0x80DD, 0x80D7, 0x00D2, 0x00F0, 0x80F5, 0x80FF,\n  0x00FA, 0x80EB, 0x00EE, 0x00E4, 0x80E1, 0x00A0, 0x80A5,\n  0x80AF, 0x00AA, 0x80BB, 0x00BE, 0x00B4, 0x80B1, 0x8093,\n  0x0096, 0x009C, 0x8099, 0x0088, 0x808D, 0x8087, 0x0082,\n  0x8183, 0x0186, 0x018C, 0x8189, 0x0198, 0x819D, 0x8197,\n  0x0192, 0x01B0, 0x81B5, 0x81BF, 0x01BA, 0x81AB, 0x01AE,\n  0x01A4, 0x81A1, 0x01E0, 0x81E5, 0x81EF, 0x01EA, 0x81FB,\n  0x01FE, 0x01F4, 0x81F1, 0x81D3, 0x01D6, 0x01DC, 0x81D9,\n  0x01C8, 0x81CD, 0x81C7, 0x01C2, 0x0140, 0x8145, 0x814F,\n  0x014A, 0x815B, 0x015E, 0x0154, 0x8151, 0x8173, 0x0176,\n  0x017C, 0x8179, 0x0168, 0x816D, 0x8167, 0x0162, 0x8123,\n  0x0126, 0x012C, 0x8129, 0x0138, 0x813D, 0x8137, 0x0132,\n  0x0110, 0x8115, 0x811F, 0x011A, 0x810B, 0x010E, 0x0104,\n  0x8101, 0x8303, 0x0306, 0x030C, 0x8309, 0x0318, 0x831D,\n  0x8317, 0x0312, 0x0330, 0x8335, 0x833F, 0x033A, 0x832B,\n  0x032E, 0x0324, 0x8321, 0x0360, 0x8365, 0x836F, 0x036A,\n  0x837B, 0x037E, 0x0374, 0x8371, 0x8353, 0x0356, 0x035C,\n  0x8359, 0x0348, 0x834D, 0x8347, 0x0342, 0x03C0, 0x83C5,\n  0x83CF, 0x03CA, 0x83DB, 0x03DE, 0x03D4, 0x83D1, 0x83F3,\n  0x03F6, 0x03FC, 0x83F9, 0x03E8, 0x83ED, 0x83E7, 0x03E2,\n  0x83A3, 0x03A6, 0x03AC, 0x83A9, 0x03B8, 0x83BD, 0x83B7,\n  0x03B2, 0x0390, 0x8395, 0x839F, 0x039A, 0x838B, 0x038E,\n  0x0384, 0x8381, 0x0280, 0x8285, 0x828F, 0x028A, 0x829B,\n  0x029E, 0x0294, 0x8291, 0x82B3, 0x02B6, 0x02BC, 0x82B9,\n  0x02A8, 0x82AD, 0x82A7, 0x02A2, 0x82E3, 0x02E6, 0x02EC,\n  0x82E9, 0x02F8, 0x82FD, 0x82F7, 0x02F2, 0x02D0, 0x82D5,\n  0x82DF, 0x02DA, 0x82CB, 0x02CE, 0x02C4, 0x82C1, 0x8243,\n  0x0246, 0x024C, 0x8249, 0x0258, 0x825D, 0x8257, 0x0252,\n  0x0270, 0x8275, 0x827F, 0x027A, 0x826B, 0x026E, 0x0264,\n  0x8261, 0x0220, 0x8225, 0x822F, 0x022A, 0x823B, 0x023E,\n  0x0234, 0x8231, 0x8213, 0x0216, 0x021C, 0x8219, 0x0208,\n  0x820D, 0x8207, 0x0202 };\n\n  for (uint16_t j = 0; j < data_blk_size; j++)\n  {\n    i = ((uint16_t)(crc_accum >> 8) ^ *data_blk_ptr++) & 0xFF;\n    crc_accum = (crc_accum << 8) ^ crc_table[i];\n  }\n\n  return crc_accum;\n}\n\nvoid Protocol2PacketHandler::addStuffing(uint8_t *packet)\n{\n  int packet_length_in = DXL_MAKEWORD(packet[PKT_LENGTH_L], packet[PKT_LENGTH_H]);\n  int packet_length_out = packet_length_in;\n  \n  if (packet_length_in < 8) // INSTRUCTION, ADDR_L, ADDR_H, CRC16_L, CRC16_H + FF FF FD\n    return;\n\n  uint8_t *packet_ptr;\n  uint16_t packet_length_before_crc = packet_length_in - 2;\n  for (uint16_t i = 3; i < packet_length_before_crc; i++)\n  {\n    packet_ptr = &packet[i+PKT_INSTRUCTION-2];\n    if (packet_ptr[0] == 0xFF && packet_ptr[1] == 0xFF && packet_ptr[2] == 0xFD)\n      packet_length_out++;\n  }\n  \n  if (packet_length_in == packet_length_out)  // no stuffing required\n    return;\n  \n  uint16_t out_index  = packet_length_out + 6 - 2;  // last index before crc\n  uint16_t in_index   = packet_length_in + 6 - 2;   // last index before crc\n  while (out_index != in_index)\n  {\n    if (packet[in_index] == 0xFD && packet[in_index-1] == 0xFF && packet[in_index-2] == 0xFF)\n    {\n      packet[out_index--] = 0xFD; // byte stuffing\n      if (out_index != in_index)\n      {\n        packet[out_index--] = packet[in_index--]; // FD\n        packet[out_index--] = packet[in_index--]; // FF\n        packet[out_index--] = packet[in_index--]; // FF\n      }\n    }\n    else\n    {\n      packet[out_index--] = packet[in_index--];\n    }\n  }\n\n  packet[PKT_LENGTH_L] = DXL_LOBYTE(packet_length_out);\n  packet[PKT_LENGTH_H] = DXL_HIBYTE(packet_length_out);\n\n  return;\n}\n\nvoid Protocol2PacketHandler::removeStuffing(uint8_t *packet)\n{\n  int i = 0, index = 0;\n  int packet_length_in = DXL_MAKEWORD(packet[PKT_LENGTH_L], packet[PKT_LENGTH_H]);\n  int packet_length_out = packet_length_in;\n\n  index = PKT_INSTRUCTION;\n  for (i = 0; i < packet_length_in - 2; i++)  // except CRC\n  {\n    if (packet[i+PKT_INSTRUCTION] == 0xFD && packet[i+PKT_INSTRUCTION+1] == 0xFD && packet[i+PKT_INSTRUCTION-1] == 0xFF && packet[i+PKT_INSTRUCTION-2] == 0xFF)\n    {   // FF FF FD FD\n      packet_length_out--;\n      i++;\n    }\n    packet[index++] = packet[i+PKT_INSTRUCTION];\n  }\n  packet[index++] = packet[PKT_INSTRUCTION+packet_length_in-2];\n  packet[index++] = packet[PKT_INSTRUCTION+packet_length_in-1];\n\n  packet[PKT_LENGTH_L] = DXL_LOBYTE(packet_length_out);\n  packet[PKT_LENGTH_H] = DXL_HIBYTE(packet_length_out);\n}\n\nint Protocol2PacketHandler::txPacket(PortHandler *port, uint8_t *txpacket)\n{\n  uint16_t total_packet_length   = 0;\n  uint16_t written_packet_length = 0;\n\n  if (port->is_using_)\n    return COMM_PORT_BUSY;\n  port->is_using_ = true;\n\n  // byte stuffing for header\n  addStuffing(txpacket);\n\n  // check max packet length\n  total_packet_length = DXL_MAKEWORD(txpacket[PKT_LENGTH_L], txpacket[PKT_LENGTH_H]) + 7;\n  // 7: HEADER0 HEADER1 HEADER2 RESERVED ID LENGTH_L LENGTH_H\n  if (total_packet_length > TXPACKET_MAX_LEN)\n  {\n    port->is_using_ = false;\n    return COMM_TX_ERROR;\n  }\n\n  // make packet header\n  txpacket[PKT_HEADER0]   = 0xFF;\n  txpacket[PKT_HEADER1]   = 0xFF;\n  txpacket[PKT_HEADER2]   = 0xFD;\n  txpacket[PKT_RESERVED]  = 0x00;\n\n  // add CRC16\n  uint16_t crc = updateCRC(0, txpacket, total_packet_length - 2);    // 2: CRC16\n  txpacket[total_packet_length - 2] = DXL_LOBYTE(crc);\n  txpacket[total_packet_length - 1] = DXL_HIBYTE(crc);\n\n  // tx packet\n  port->clearPort();\n  written_packet_length = port->writePort(txpacket, total_packet_length);\n  if (total_packet_length != written_packet_length)\n  {\n    port->is_using_ = false;\n    return COMM_TX_FAIL;\n  }\n\n  return COMM_SUCCESS;\n}\n\nint Protocol2PacketHandler::rxPacket(PortHandler *port, uint8_t *rxpacket)\n{\n  int     result         = COMM_TX_FAIL;\n\n  uint16_t rx_length     = 0;\n  uint16_t wait_length   = 11; // minimum length (HEADER0 HEADER1 HEADER2 RESERVED ID LENGTH_L LENGTH_H INST ERROR CRC16_L CRC16_H)\n\n  while(true)\n  {\n    rx_length += port->readPort(&rxpacket[rx_length], wait_length - rx_length);\n    if (rx_length >= wait_length)\n    {\n      uint16_t idx = 0;\n\n      // find packet header\n      for (idx = 0; idx < (rx_length - 3); idx++)\n      {\n        if ((rxpacket[idx] == 0xFF) && (rxpacket[idx+1] == 0xFF) && (rxpacket[idx+2] == 0xFD) && (rxpacket[idx+3] != 0xFD))\n          break;\n      }\n\n      if (idx == 0)   // found at the beginning of the packet\n      {\n        if (rxpacket[PKT_RESERVED] != 0x00 ||\n           rxpacket[PKT_ID] > 0xFC ||\n           DXL_MAKEWORD(rxpacket[PKT_LENGTH_L], rxpacket[PKT_LENGTH_H]) > RXPACKET_MAX_LEN ||\n           rxpacket[PKT_INSTRUCTION] != 0x55)\n        {\n          // remove the first byte in the packet\n          for (uint16_t s = 0; s < rx_length - 1; s++)\n            rxpacket[s] = rxpacket[1 + s];\n          //memcpy(&rxpacket[0], &rxpacket[idx], rx_length - idx);\n          rx_length -= 1;\n          continue;\n        }\n\n        // re-calculate the exact length of the rx packet\n        if (wait_length != DXL_MAKEWORD(rxpacket[PKT_LENGTH_L], rxpacket[PKT_LENGTH_H]) + PKT_LENGTH_H + 1)\n        {\n          wait_length = DXL_MAKEWORD(rxpacket[PKT_LENGTH_L], rxpacket[PKT_LENGTH_H]) + PKT_LENGTH_H + 1;\n          continue;\n        }\n\n        if (rx_length < wait_length)\n        {\n          // check timeout\n          if (port->isPacketTimeout() == true)\n          {\n            if (rx_length == 0)\n            {\n              result = COMM_RX_TIMEOUT;\n            }\n            else\n            {\n              result = COMM_RX_CORRUPT;\n            }\n            break;\n          }\n          else\n          {\n            continue;\n          }\n        }\n\n        // verify CRC16\n        uint16_t crc = DXL_MAKEWORD(rxpacket[wait_length-2], rxpacket[wait_length-1]);\n        if (updateCRC(0, rxpacket, wait_length - 2) == crc)\n        {\n          result = COMM_SUCCESS;\n        }\n        else\n        {\n          result = COMM_RX_CORRUPT;\n        }\n        break;\n      }\n      else\n      {\n        // remove unnecessary packets\n        for (uint16_t s = 0; s < rx_length - idx; s++)\n          rxpacket[s] = rxpacket[idx + s];\n        //memcpy(&rxpacket[0], &rxpacket[idx], rx_length - idx);\n        rx_length -= idx;\n      }\n    }\n    else\n    {\n      // check timeout\n      if (port->isPacketTimeout() == true)\n      {\n        if (rx_length == 0)\n        {\n          result = COMM_RX_TIMEOUT;\n        }\n        else\n        {\n          result = COMM_RX_CORRUPT;\n        }\n        break;\n      }\n    }\n#if defined(__linux__) || defined(__APPLE__)\n    usleep(0);\n#elif defined(_WIN32) || defined(_WIN64)\n    Sleep(0);\n#endif\n  }\n  port->is_using_ = false;\n\n  if (result == COMM_SUCCESS)\n    removeStuffing(rxpacket);\n\n  return result;\n}\n\n// NOT for BulkRead / SyncRead instruction\nint Protocol2PacketHandler::txRxPacket(PortHandler *port, uint8_t *txpacket, uint8_t *rxpacket, uint8_t *error)\n{\n  int result = COMM_TX_FAIL;\n\n  // tx packet\n  result = txPacket(port, txpacket);\n  if (result != COMM_SUCCESS)\n    return result;\n\n  // (Instruction == BulkRead or SyncRead) == this function is not available.\n  if (txpacket[PKT_INSTRUCTION] == INST_BULK_READ || txpacket[PKT_INSTRUCTION] == INST_SYNC_READ)\n    result = COMM_NOT_AVAILABLE;\n\n  // (ID == Broadcast ID) == no need to wait for status packet or not available.\n  // (Instruction == action) == no need to wait for status packet\n  if (txpacket[PKT_ID] == BROADCAST_ID || txpacket[PKT_INSTRUCTION] == INST_ACTION)\n  {\n    port->is_using_ = false;\n    return result;\n  }\n\n  // set packet timeout\n  if (txpacket[PKT_INSTRUCTION] == INST_READ)\n  {\n    port->setPacketTimeout((uint16_t)(DXL_MAKEWORD(txpacket[PKT_PARAMETER0+2], txpacket[PKT_PARAMETER0+3]) + 11));\n  }\n  else\n  {\n    port->setPacketTimeout((uint16_t)11);\n    // HEADER0 HEADER1 HEADER2 RESERVED ID LENGTH_L LENGTH_H INST ERROR CRC16_L CRC16_H\n  }\n\n  // rx packet\n  do {\n    result = rxPacket(port, rxpacket);\n  } while (result == COMM_SUCCESS && txpacket[PKT_ID] != rxpacket[PKT_ID]);\n\n  if (result == COMM_SUCCESS && txpacket[PKT_ID] == rxpacket[PKT_ID])\n  {\n    if (error != 0)\n      *error = (uint8_t)rxpacket[PKT_ERROR];\n  }\n\n  return result;\n}\n\nint Protocol2PacketHandler::ping(PortHandler *port, uint8_t id, uint8_t *error)\n{\n  return ping(port, id, 0, error);\n}\n\nint Protocol2PacketHandler::ping(PortHandler *port, uint8_t id, uint16_t *model_number, uint8_t *error)\n{\n  int result                 = COMM_TX_FAIL;\n\n  uint8_t txpacket[10]        = {0};\n  uint8_t rxpacket[14]        = {0};\n\n  if (id >= BROADCAST_ID)\n    return COMM_NOT_AVAILABLE;\n\n  txpacket[PKT_ID]            = id;\n  txpacket[PKT_LENGTH_L]      = 3;\n  txpacket[PKT_LENGTH_H]      = 0;\n  txpacket[PKT_INSTRUCTION]   = INST_PING;\n\n  result = txRxPacket(port, txpacket, rxpacket, error);\n  if (result == COMM_SUCCESS && model_number != 0)\n    *model_number = DXL_MAKEWORD(rxpacket[PKT_PARAMETER0+1], rxpacket[PKT_PARAMETER0+2]);\n\n  return result;\n}\n\nint Protocol2PacketHandler::broadcastPing(PortHandler *port, std::vector<uint8_t> &id_list)\n{\n  const int STATUS_LENGTH     = 14;\n  int result                  = COMM_TX_FAIL;\n\n  id_list.clear();\n\n  uint16_t rx_length          = 0;\n  uint16_t wait_length        = STATUS_LENGTH * MAX_ID;\n\n  uint8_t txpacket[10]        = {0};\n  uint8_t rxpacket[STATUS_LENGTH * MAX_ID] = {0};\n\n  txpacket[PKT_ID]            = BROADCAST_ID;\n  txpacket[PKT_LENGTH_L]      = 3;\n  txpacket[PKT_LENGTH_H]      = 0;\n  txpacket[PKT_INSTRUCTION]   = INST_PING;\n\n  result = txPacket(port, txpacket);\n  if (result != COMM_SUCCESS)\n  {\n    port->is_using_ = false;\n    return result;\n  }\n\n  // set rx timeout\n  port->setPacketTimeout((uint16_t)(wait_length * 30));\n\n  while(1)\n  {\n    rx_length += port->readPort(&rxpacket[rx_length], wait_length - rx_length);\n    if (port->isPacketTimeout() == true)// || rx_length >= wait_length)\n      break;\n  }\n\n  port->is_using_ = false;\n\n  if (rx_length == 0)\n    return COMM_RX_TIMEOUT;\n\n  while(1)\n  {\n    if (rx_length < STATUS_LENGTH)\n      return COMM_RX_CORRUPT;\n\n    uint16_t idx = 0;\n\n    // find packet header\n    for (idx = 0; idx < (rx_length - 2); idx++)\n    {\n      if (rxpacket[idx] == 0xFF && rxpacket[idx+1] == 0xFF && rxpacket[idx+2] == 0xFD)\n        break;\n    }\n\n    if (idx == 0)   // found at the beginning of the packet\n    {\n      // verify CRC16\n      uint16_t crc = DXL_MAKEWORD(rxpacket[STATUS_LENGTH-2], rxpacket[STATUS_LENGTH-1]);\n\n      if (updateCRC(0, rxpacket, STATUS_LENGTH - 2) == crc)\n      {\n        result = COMM_SUCCESS;\n\n        id_list.push_back(rxpacket[PKT_ID]);\n\n        for (uint16_t s = 0; s < rx_length - STATUS_LENGTH; s++)\n          rxpacket[s] = rxpacket[STATUS_LENGTH + s];\n        rx_length -= STATUS_LENGTH;\n\n        if (rx_length == 0)\n          return result;\n      }\n      else\n      {\n        result = COMM_RX_CORRUPT;\n\n        // remove header (0xFF 0xFF 0xFD)\n        for (uint16_t s = 0; s < rx_length - 3; s++)\n          rxpacket[s] = rxpacket[3 + s];\n        rx_length -= 3;\n      }\n    }\n    else\n    {\n      // remove unnecessary packets\n      for (uint16_t s = 0; s < rx_length - idx; s++)\n        rxpacket[s] = rxpacket[idx + s];\n      rx_length -= idx;\n    }\n  }\n\n  return result;\n}\n\nint Protocol2PacketHandler::action(PortHandler *port, uint8_t id)\n{\n  uint8_t txpacket[10]        = {0};\n\n  txpacket[PKT_ID]            = id;\n  txpacket[PKT_LENGTH_L]      = 3;\n  txpacket[PKT_LENGTH_H]      = 0;\n  txpacket[PKT_INSTRUCTION]   = INST_ACTION;\n\n  return txRxPacket(port, txpacket, 0);\n}\n\nint Protocol2PacketHandler::reboot(PortHandler *port, uint8_t id, uint8_t *error)\n{\n  uint8_t txpacket[10]        = {0};\n  uint8_t rxpacket[11]        = {0};\n\n  txpacket[PKT_ID]            = id;\n  txpacket[PKT_LENGTH_L]      = 3;\n  txpacket[PKT_LENGTH_H]      = 0;\n  txpacket[PKT_INSTRUCTION]   = INST_REBOOT;\n\n  return txRxPacket(port, txpacket, rxpacket, error);\n}\n\nint Protocol2PacketHandler::clearMultiTurn(PortHandler *port, uint8_t id, uint8_t *error)\n{\n  uint8_t txpacket[15]        = {0};\n  uint8_t rxpacket[11]        = {0};\n\n  txpacket[PKT_ID]            = id;\n  txpacket[PKT_LENGTH_L]      = 8;\n  txpacket[PKT_LENGTH_H]      = 0;\n  txpacket[PKT_INSTRUCTION]   = INST_CLEAR;\n  txpacket[PKT_PARAMETER0]    = 0x01;\n  txpacket[PKT_PARAMETER0+1]  = 0x44;\n  txpacket[PKT_PARAMETER0+2]  = 0x58;\n  txpacket[PKT_PARAMETER0+3]  = 0x4C;\n  txpacket[PKT_PARAMETER0+4]  = 0x22;\n\n  return txRxPacket(port, txpacket, rxpacket, error);\n}\n\nint Protocol2PacketHandler::factoryReset(PortHandler *port, uint8_t id, uint8_t option, uint8_t *error)\n{\n  uint8_t txpacket[11]        = {0};\n  uint8_t rxpacket[11]        = {0};\n\n  txpacket[PKT_ID]            = id;\n  txpacket[PKT_LENGTH_L]      = 4;\n  txpacket[PKT_LENGTH_H]      = 0;\n  txpacket[PKT_INSTRUCTION]   = INST_FACTORY_RESET;\n  txpacket[PKT_PARAMETER0]    = option;\n\n  return txRxPacket(port, txpacket, rxpacket, error);\n}\n\nint Protocol2PacketHandler::readTx(PortHandler *port, uint8_t id, uint16_t address, uint16_t length)\n{\n  int result                 = COMM_TX_FAIL;\n\n  uint8_t txpacket[14]        = {0};\n\n  if (id >= BROADCAST_ID)\n    return COMM_NOT_AVAILABLE;\n\n  txpacket[PKT_ID]            = id;\n  txpacket[PKT_LENGTH_L]      = 7;\n  txpacket[PKT_LENGTH_H]      = 0;\n  txpacket[PKT_INSTRUCTION]   = INST_READ;\n  txpacket[PKT_PARAMETER0+0]  = (uint8_t)DXL_LOBYTE(address);\n  txpacket[PKT_PARAMETER0+1]  = (uint8_t)DXL_HIBYTE(address);\n  txpacket[PKT_PARAMETER0+2]  = (uint8_t)DXL_LOBYTE(length);\n  txpacket[PKT_PARAMETER0+3]  = (uint8_t)DXL_HIBYTE(length);\n\n  result = txPacket(port, txpacket);\n\n  // set packet timeout\n  if (result == COMM_SUCCESS)\n    port->setPacketTimeout((uint16_t)(length + 11));\n\n  return result;\n}\n\nint Protocol2PacketHandler::readRx(PortHandler *port, uint8_t id, uint16_t length, uint8_t *data, uint8_t *error)\n{\n  int result                  = COMM_TX_FAIL;\n  uint8_t *rxpacket           = (uint8_t *)malloc(length + 11 + (length / 3));\n  //(length + 11 + (length/3));  // (length/3): consider stuffing\n  \n  if (rxpacket == NULL)\n    return result;\n  \n  do {\n    result = rxPacket(port, rxpacket);\n  } while (result == COMM_SUCCESS && rxpacket[PKT_ID] != id);\n\n  if (result == COMM_SUCCESS && rxpacket[PKT_ID] == id)\n  {\n    if (error != 0)\n      *error = (uint8_t)rxpacket[PKT_ERROR];\n\n    for (uint16_t s = 0; s < length; s++)\n    {\n      data[s] = rxpacket[PKT_PARAMETER0 + 1 + s];\n    }\n    //memcpy(data, &rxpacket[PKT_PARAMETER0+1], length);\n  }\n\n  free(rxpacket);\n  //delete[] rxpacket;\n  return result;\n}\n\nint Protocol2PacketHandler::readTxRx(PortHandler *port, uint8_t id, uint16_t address, uint16_t length, uint8_t *data, uint8_t *error)\n{\n  int result                  = COMM_TX_FAIL;\n\n  uint8_t txpacket[14]        = {0};\n  uint8_t *rxpacket           = (uint8_t *)malloc(length + 11 + (length / 3));\n  //(length + 11 + (length/3));  // (length/3): consider stuffing\n\n  if (rxpacket == NULL)\n    return result;\n  \n  if (id >= BROADCAST_ID)\n    return COMM_NOT_AVAILABLE;\n\n  txpacket[PKT_ID]            = id;\n  txpacket[PKT_LENGTH_L]      = 7;\n  txpacket[PKT_LENGTH_H]      = 0;\n  txpacket[PKT_INSTRUCTION]   = INST_READ;\n  txpacket[PKT_PARAMETER0+0]  = (uint8_t)DXL_LOBYTE(address);\n  txpacket[PKT_PARAMETER0+1]  = (uint8_t)DXL_HIBYTE(address);\n  txpacket[PKT_PARAMETER0+2]  = (uint8_t)DXL_LOBYTE(length);\n  txpacket[PKT_PARAMETER0+3]  = (uint8_t)DXL_HIBYTE(length);\n\n  result = txRxPacket(port, txpacket, rxpacket, error);\n  if (result == COMM_SUCCESS)\n  {\n    if (error != 0)\n      *error = (uint8_t)rxpacket[PKT_ERROR];\n\n    for (uint16_t s = 0; s < length; s++)\n    {\n      data[s] = rxpacket[PKT_PARAMETER0 + 1 + s];\n    }\n    //memcpy(data, &rxpacket[PKT_PARAMETER0+1], length);\n  }\n\n  free(rxpacket);\n  //delete[] rxpacket;\n  return result;\n}\n\nint Protocol2PacketHandler::read1ByteTx(PortHandler *port, uint8_t id, uint16_t address)\n{\n  return readTx(port, id, address, 1);\n}\nint Protocol2PacketHandler::read1ByteRx(PortHandler *port, uint8_t id, uint8_t *data, uint8_t *error)\n{\n  uint8_t data_read[1] = {0};\n  int result = readRx(port, id, 1, data_read, error);\n  if (result == COMM_SUCCESS)\n    *data = data_read[0];\n  return result;\n}\nint Protocol2PacketHandler::read1ByteTxRx(PortHandler *port, uint8_t id, uint16_t address, uint8_t *data, uint8_t *error)\n{\n  uint8_t data_read[1] = {0};\n  int result = readTxRx(port, id, address, 1, data_read, error);\n  if (result == COMM_SUCCESS)\n    *data = data_read[0];\n  return result;\n}\n\nint Protocol2PacketHandler::read2ByteTx(PortHandler *port, uint8_t id, uint16_t address)\n{\n  return readTx(port, id, address, 2);\n}\nint Protocol2PacketHandler::read2ByteRx(PortHandler *port, uint8_t id, uint16_t *data, uint8_t *error)\n{\n  uint8_t data_read[2] = {0};\n  int result = readRx(port, id, 2, data_read, error);\n  if (result == COMM_SUCCESS)\n    *data = DXL_MAKEWORD(data_read[0], data_read[1]);\n  return result;\n}\nint Protocol2PacketHandler::read2ByteTxRx(PortHandler *port, uint8_t id, uint16_t address, uint16_t *data, uint8_t *error)\n{\n  uint8_t data_read[2] = {0};\n  int result = readTxRx(port, id, address, 2, data_read, error);\n  if (result == COMM_SUCCESS)\n    *data = DXL_MAKEWORD(data_read[0], data_read[1]);\n  return result;\n}\n\nint Protocol2PacketHandler::read4ByteTx(PortHandler *port, uint8_t id, uint16_t address)\n{\n  return readTx(port, id, address, 4);\n}\nint Protocol2PacketHandler::read4ByteRx(PortHandler *port, uint8_t id, uint32_t *data, uint8_t *error)\n{\n  uint8_t data_read[4] = {0};\n  int result = readRx(port, id, 4, data_read, error);\n  if (result == COMM_SUCCESS)\n    *data = DXL_MAKEDWORD(DXL_MAKEWORD(data_read[0], data_read[1]), DXL_MAKEWORD(data_read[2], data_read[3]));\n  return result;\n}\nint Protocol2PacketHandler::read4ByteTxRx(PortHandler *port, uint8_t id, uint16_t address, uint32_t *data, uint8_t *error)\n{\n  uint8_t data_read[4] = {0};\n  int result = readTxRx(port, id, address, 4, data_read, error);\n  if (result == COMM_SUCCESS)\n    *data = DXL_MAKEDWORD(DXL_MAKEWORD(data_read[0], data_read[1]), DXL_MAKEWORD(data_read[2], data_read[3]));\n  return result;\n}\n\n\nint Protocol2PacketHandler::writeTxOnly(PortHandler *port, uint8_t id, uint16_t address, uint16_t length, uint8_t *data)\n{\n  int result                  = COMM_TX_FAIL;\n\n  uint8_t *txpacket           = (uint8_t *)malloc(length + 12 + (length / 3));\n  \n  if (txpacket == NULL)\n    return result;\n\n  txpacket[PKT_ID]            = id;\n  txpacket[PKT_LENGTH_L]      = DXL_LOBYTE(length+5);\n  txpacket[PKT_LENGTH_H]      = DXL_HIBYTE(length+5);\n  txpacket[PKT_INSTRUCTION]   = INST_WRITE;\n  txpacket[PKT_PARAMETER0+0]  = (uint8_t)DXL_LOBYTE(address);\n  txpacket[PKT_PARAMETER0+1]  = (uint8_t)DXL_HIBYTE(address);\n\n  for (uint16_t s = 0; s < length; s++)\n    txpacket[PKT_PARAMETER0+2+s] = data[s];\n  //memcpy(&txpacket[PKT_PARAMETER0+2], data, length);\n\n  result = txPacket(port, txpacket);\n  port->is_using_ = false;\n\n  free(txpacket);\n  //delete[] txpacket;\n  return result;\n}\n\nint Protocol2PacketHandler::writeTxRx(PortHandler *port, uint8_t id, uint16_t address, uint16_t length, uint8_t *data, uint8_t *error)\n{\n  int result                  = COMM_TX_FAIL;\n\n  uint8_t *txpacket           = (uint8_t *)malloc(length + 12 + (length / 3));\n  uint8_t rxpacket[11]        = {0};\n\n  if (txpacket == NULL)\n    return result;\n  \n  txpacket[PKT_ID]            = id;\n  txpacket[PKT_LENGTH_L]      = DXL_LOBYTE(length+5);\n  txpacket[PKT_LENGTH_H]      = DXL_HIBYTE(length+5);\n  txpacket[PKT_INSTRUCTION]   = INST_WRITE;\n  txpacket[PKT_PARAMETER0+0]  = (uint8_t)DXL_LOBYTE(address);\n  txpacket[PKT_PARAMETER0+1]  = (uint8_t)DXL_HIBYTE(address);\n\n  for (uint16_t s = 0; s < length; s++)\n    txpacket[PKT_PARAMETER0+2+s] = data[s];\n  //memcpy(&txpacket[PKT_PARAMETER0+2], data, length);\n\n  result = txRxPacket(port, txpacket, rxpacket, error);\n\n  free(txpacket);\n  //delete[] txpacket;\n  return result;\n}\n\nint Protocol2PacketHandler::write1ByteTxOnly(PortHandler *port, uint8_t id, uint16_t address, uint8_t data)\n{\n  uint8_t data_write[1] = { data };\n  return writeTxOnly(port, id, address, 1, data_write);\n}\nint Protocol2PacketHandler::write1ByteTxRx(PortHandler *port, uint8_t id, uint16_t address, uint8_t data, uint8_t *error)\n{\n  uint8_t data_write[1] = { data };\n  return writeTxRx(port, id, address, 1, data_write, error);\n}\n\nint Protocol2PacketHandler::write2ByteTxOnly(PortHandler *port, uint8_t id, uint16_t address, uint16_t data)\n{\n  uint8_t data_write[2] = { DXL_LOBYTE(data), DXL_HIBYTE(data) };\n  return writeTxOnly(port, id, address, 2, data_write);\n}\nint Protocol2PacketHandler::write2ByteTxRx(PortHandler *port, uint8_t id, uint16_t address, uint16_t data, uint8_t *error)\n{\n  uint8_t data_write[2] = { DXL_LOBYTE(data), DXL_HIBYTE(data) };\n  return writeTxRx(port, id, address, 2, data_write, error);\n}\n\nint Protocol2PacketHandler::write4ByteTxOnly(PortHandler *port, uint8_t id, uint16_t address, uint32_t data)\n{\n  uint8_t data_write[4] = { DXL_LOBYTE(DXL_LOWORD(data)), DXL_HIBYTE(DXL_LOWORD(data)), DXL_LOBYTE(DXL_HIWORD(data)), DXL_HIBYTE(DXL_HIWORD(data)) };\n  return writeTxOnly(port, id, address, 4, data_write);\n}\nint Protocol2PacketHandler::write4ByteTxRx(PortHandler *port, uint8_t id, uint16_t address, uint32_t data, uint8_t *error)\n{\n  uint8_t data_write[4] = { DXL_LOBYTE(DXL_LOWORD(data)), DXL_HIBYTE(DXL_LOWORD(data)), DXL_LOBYTE(DXL_HIWORD(data)), DXL_HIBYTE(DXL_HIWORD(data)) };\n  return writeTxRx(port, id, address, 4, data_write, error);\n}\n\nint Protocol2PacketHandler::regWriteTxOnly(PortHandler *port, uint8_t id, uint16_t address, uint16_t length, uint8_t *data)\n{\n  int result                  = COMM_TX_FAIL;\n\n  uint8_t *txpacket           = (uint8_t *)malloc(length + 12 + (length / 3));\n\n  if (txpacket == NULL)\n    return result;\n  \n  txpacket[PKT_ID]            = id;\n  txpacket[PKT_LENGTH_L]      = DXL_LOBYTE(length+5);\n  txpacket[PKT_LENGTH_H]      = DXL_HIBYTE(length+5);\n  txpacket[PKT_INSTRUCTION]   = INST_REG_WRITE;\n  txpacket[PKT_PARAMETER0+0]  = (uint8_t)DXL_LOBYTE(address);\n  txpacket[PKT_PARAMETER0+1]  = (uint8_t)DXL_HIBYTE(address);\n\n  for (uint16_t s = 0; s < length; s++)\n    txpacket[PKT_PARAMETER0+2+s] = data[s];\n  //memcpy(&txpacket[PKT_PARAMETER0+2], data, length);\n\n  result = txPacket(port, txpacket);\n  port->is_using_ = false;\n\n  free(txpacket);\n  //delete[] txpacket;\n  return result;\n}\n\nint Protocol2PacketHandler::regWriteTxRx(PortHandler *port, uint8_t id, uint16_t address, uint16_t length, uint8_t *data, uint8_t *error)\n{\n  int result                  = COMM_TX_FAIL;\n\n  uint8_t *txpacket           = (uint8_t *)malloc(length + 12 + (length / 3));\n  uint8_t rxpacket[11]        = {0};\n\n  if (txpacket == NULL)\n    return result;\n  \n  txpacket[PKT_ID]            = id;\n  txpacket[PKT_LENGTH_L]      = DXL_LOBYTE(length+5);\n  txpacket[PKT_LENGTH_H]      = DXL_HIBYTE(length+5);\n  txpacket[PKT_INSTRUCTION]   = INST_REG_WRITE;\n  txpacket[PKT_PARAMETER0+0]  = (uint8_t)DXL_LOBYTE(address);\n  txpacket[PKT_PARAMETER0+1]  = (uint8_t)DXL_HIBYTE(address);\n\n  for (uint16_t s = 0; s < length; s++)\n    txpacket[PKT_PARAMETER0+2+s] = data[s];\n  //memcpy(&txpacket[PKT_PARAMETER0+2], data, length);\n\n  result = txRxPacket(port, txpacket, rxpacket, error);\n\n  free(txpacket);\n  //delete[] txpacket;\n  return result;\n}\n\nint Protocol2PacketHandler::syncReadTx(PortHandler *port, uint16_t start_address, uint16_t data_length, uint8_t *param, uint16_t param_length)\n{\n  int result                  = COMM_TX_FAIL;\n\n  uint8_t *txpacket           = (uint8_t *)malloc(param_length + 14 + (param_length / 3));\n  // 14: HEADER0 HEADER1 HEADER2 RESERVED ID LEN_L LEN_H INST START_ADDR_L START_ADDR_H DATA_LEN_L DATA_LEN_H CRC16_L CRC16_H\n\n  if (txpacket == NULL)\n    return result;\n  \n  txpacket[PKT_ID]            = BROADCAST_ID;\n  txpacket[PKT_LENGTH_L]      = DXL_LOBYTE(param_length + 7); // 7: INST START_ADDR_L START_ADDR_H DATA_LEN_L DATA_LEN_H CRC16_L CRC16_H\n  txpacket[PKT_LENGTH_H]      = DXL_HIBYTE(param_length + 7); // 7: INST START_ADDR_L START_ADDR_H DATA_LEN_L DATA_LEN_H CRC16_L CRC16_H\n  txpacket[PKT_INSTRUCTION]   = INST_SYNC_READ;\n  txpacket[PKT_PARAMETER0+0]  = DXL_LOBYTE(start_address);\n  txpacket[PKT_PARAMETER0+1]  = DXL_HIBYTE(start_address);\n  txpacket[PKT_PARAMETER0+2]  = DXL_LOBYTE(data_length);\n  txpacket[PKT_PARAMETER0+3]  = DXL_HIBYTE(data_length);\n\n  for (uint16_t s = 0; s < param_length; s++)\n    txpacket[PKT_PARAMETER0+4+s] = param[s];\n  //memcpy(&txpacket[PKT_PARAMETER0+4], param, param_length);\n\n  result = txPacket(port, txpacket);\n  if (result == COMM_SUCCESS)\n    port->setPacketTimeout((uint16_t)((11 + data_length) * param_length));\n\n  free(txpacket);\n  return result;\n}\n\nint Protocol2PacketHandler::syncWriteTxOnly(PortHandler *port, uint16_t start_address, uint16_t data_length, uint8_t *param, uint16_t param_length)\n{\n  int result                  = COMM_TX_FAIL;\n\n  uint8_t *txpacket           = (uint8_t *)malloc(param_length + 14 + (param_length / 3));\n  // 14: HEADER0 HEADER1 HEADER2 RESERVED ID LEN_L LEN_H INST START_ADDR_L START_ADDR_H DATA_LEN_L DATA_LEN_H CRC16_L CRC16_H\n\n  if (txpacket == NULL)\n    return result;\n  \n  txpacket[PKT_ID]            = BROADCAST_ID;\n  txpacket[PKT_LENGTH_L]      = DXL_LOBYTE(param_length + 7); // 7: INST START_ADDR_L START_ADDR_H DATA_LEN_L DATA_LEN_H CRC16_L CRC16_H\n  txpacket[PKT_LENGTH_H]      = DXL_HIBYTE(param_length + 7); // 7: INST START_ADDR_L START_ADDR_H DATA_LEN_L DATA_LEN_H CRC16_L CRC16_H\n  txpacket[PKT_INSTRUCTION]   = INST_SYNC_WRITE;\n  txpacket[PKT_PARAMETER0+0]  = DXL_LOBYTE(start_address);\n  txpacket[PKT_PARAMETER0+1]  = DXL_HIBYTE(start_address);\n  txpacket[PKT_PARAMETER0+2]  = DXL_LOBYTE(data_length);\n  txpacket[PKT_PARAMETER0+3]  = DXL_HIBYTE(data_length);\n\n  for (uint16_t s = 0; s < param_length; s++)\n    txpacket[PKT_PARAMETER0+4+s] = param[s];\n  //memcpy(&txpacket[PKT_PARAMETER0+4], param, param_length);\n\n  result = txRxPacket(port, txpacket, 0, 0);\n\n  free(txpacket);\n  //delete[] txpacket;\n  return result;\n}\n\nint Protocol2PacketHandler::bulkReadTx(PortHandler *port, uint8_t *param, uint16_t param_length)\n{\n  int result                  = COMM_TX_FAIL;\n\n  uint8_t *txpacket           = (uint8_t *)malloc(param_length + 10 + (param_length / 3));\n  // 10: HEADER0 HEADER1 HEADER2 RESERVED ID LEN_L LEN_H INST CRC16_L CRC16_H\n\n  if (txpacket == NULL)\n    return result;\n  \n  txpacket[PKT_ID]            = BROADCAST_ID;\n  txpacket[PKT_LENGTH_L]      = DXL_LOBYTE(param_length + 3); // 3: INST CRC16_L CRC16_H\n  txpacket[PKT_LENGTH_H]      = DXL_HIBYTE(param_length + 3); // 3: INST CRC16_L CRC16_H\n  txpacket[PKT_INSTRUCTION]   = INST_BULK_READ;\n\n  for (uint16_t s = 0; s < param_length; s++)\n    txpacket[PKT_PARAMETER0+s] = param[s];\n  //memcpy(&txpacket[PKT_PARAMETER0], param, param_length);\n\n  result = txPacket(port, txpacket);\n  if (result == COMM_SUCCESS)\n  {\n    int wait_length = 0;\n    for (uint16_t i = 0; i < param_length; i += 5)\n      wait_length += DXL_MAKEWORD(param[i+3], param[i+4]) + 10;\n    port->setPacketTimeout((uint16_t)wait_length);\n  }\n\n  free(txpacket);\n  //delete[] txpacket;\n  return result;\n}\n\nint Protocol2PacketHandler::bulkWriteTxOnly(PortHandler *port, uint8_t *param, uint16_t param_length)\n{\n  int result                  = COMM_TX_FAIL;\n\n  uint8_t *txpacket           = (uint8_t *)malloc(param_length + 10 + (param_length / 3));\n  // 10: HEADER0 HEADER1 HEADER2 RESERVED ID LEN_L LEN_H INST CRC16_L CRC16_H\n\n  if (txpacket == NULL)\n    return result;\n  \n  txpacket[PKT_ID]            = BROADCAST_ID;\n  txpacket[PKT_LENGTH_L]      = DXL_LOBYTE(param_length + 3); // 3: INST CRC16_L CRC16_H\n  txpacket[PKT_LENGTH_H]      = DXL_HIBYTE(param_length + 3); // 3: INST CRC16_L CRC16_H\n  txpacket[PKT_INSTRUCTION]   = INST_BULK_WRITE;\n\n  for (uint16_t s = 0; s < param_length; s++)\n    txpacket[PKT_PARAMETER0+s] = param[s];\n  //memcpy(&txpacket[PKT_PARAMETER0], param, param_length);\n\n  result = txRxPacket(port, txpacket, 0, 0);\n\n  free(txpacket);\n  //delete[] txpacket;\n  return result;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelWorkbench/include/dynamixel_workbench_toolbox/dynamixel_driver.h",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Taehun Lim (Darby) */\n\n#ifndef DYNAMIXEL_DRIVER_H\n#define DYNAMIXEL_DRIVER_H\n\n#include \"dynamixel_tool.h\"\n\n#if defined(__OPENCR__) || defined(__OPENCM904__)\n  #include <Arduino.h>\n  #include <DynamixelSDK.h>\n#elif defined(__linux__) || defined(__APPLE__)\n  #include \"unistd.h\"\n  #include \"dynamixel_sdk/dynamixel_sdk.h\"\n#endif\n\n#define MAX_DXL_SERIES_NUM  5\n#define MAX_HANDLER_NUM     5\n#define MAX_BULK_PARAMETER  21\n\ntypedef struct \n{\n  const ControlItem *control_item; \n  dynamixel::GroupSyncWrite *groupSyncWrite;    \n} SyncWriteHandler;\n\ntypedef struct \n{\n  const ControlItem *control_item;\n  dynamixel::GroupSyncRead  *groupSyncRead;     \n} SyncReadHandler;\n\ntypedef struct\n{\n  uint8_t  id;\n  uint16_t address;\n  uint16_t data_length;\n} BulkParameter;\n\ntypedef struct\n{\n  int dxl_comm_result;\n  bool dxl_addparam_result;\n  bool dxl_getdata_result;\n  uint8_t dxl_error;\n} ErrorFromSDK;\n\nclass DynamixelDriver\n{\n private:\n  dynamixel::PortHandler   *portHandler_;\n  dynamixel::PacketHandler *packetHandler_;\n\n  SyncWriteHandler syncWriteHandler_[MAX_HANDLER_NUM];\n  SyncReadHandler  syncReadHandler_[MAX_HANDLER_NUM];\n\n  dynamixel::GroupBulkRead  *groupBulkRead_;  \n  dynamixel::GroupBulkWrite *groupBulkWrite_;\n  BulkParameter bulk_read_param_[MAX_BULK_PARAMETER];\n \n  DynamixelTool tools_[MAX_DXL_SERIES_NUM];\n\n  uint8_t tools_cnt_;\n  uint8_t sync_write_handler_cnt_;\n  uint8_t sync_read_handler_cnt_;\n  uint8_t bulk_read_parameter_cnt_;\n\n public:\n  DynamixelDriver();\n  ~DynamixelDriver();\n\n  bool init(const char* device_name = \"/dev/ttyUSB0\", \n            uint32_t baud_rate = 57600, \n            const char **log = NULL);\n\n  bool begin(const char* device_name = \"/dev/ttyUSB0\", \n            uint32_t baud_rate = 57600, \n            const char **log = NULL);\n\n  bool setPortHandler(const char *device_name, const char **log = NULL);\n  bool setBaudrate(uint32_t baud_rate, const char **log = NULL);\n  bool setPacketHandler(float protocol_version, const char **log = NULL);\n\n  float getProtocolVersion(void);\n  uint32_t getBaudrate(void);\n\n  const char * getModelName(uint8_t id, const char **log = NULL);\n  uint16_t getModelNumber(uint8_t id, const char **log = NULL);\n  const ControlItem *getControlTable(uint8_t id, const char **log = NULL);\n  const ControlItem *getItemInfo(uint8_t id, const char *item_name, const char **log = NULL);\n  uint8_t getTheNumberOfControlItem(uint8_t id, const char **log = NULL);\n  const ModelInfo* getModelInfo(uint8_t id, const char **log = NULL);\n\n  uint8_t getTheNumberOfSyncWriteHandler(void);\n  uint8_t getTheNumberOfSyncReadHandler(void);\n  uint8_t getTheNumberOfBulkReadParam(void);\n\n  bool scan(uint8_t *get_id,\n            uint8_t *get_the_number_of_id, \n            uint8_t range = 253,\n            const char **log = NULL);\n\n  bool scan(uint8_t *get_id,\n            uint8_t *get_the_number_of_id, \n            uint8_t start_number,\n            uint8_t end_number,\n            const char **log = NULL);\n\n  bool ping(uint8_t id, \n            uint16_t *get_model_number,\n            const char **log = NULL);\n\n  bool ping(uint8_t id,\n            const char **log = NULL);\n\n  bool clearMultiTurn(uint8_t id, const char **log = NULL);\n\n  bool reboot(uint8_t id, const char **log = NULL);\n  bool reset(uint8_t id, const char **log = NULL);\n\n  bool writeRegister(uint8_t id, uint16_t address, uint16_t length, uint8_t* data, const char **log = NULL);\n  bool writeRegister(uint8_t id, const char *item_name, int32_t data, const char **log = NULL);\n\n  bool writeOnlyRegister(uint8_t id, uint16_t address, uint16_t length, uint8_t *data, const char **log = NULL);\n  bool writeOnlyRegister(uint8_t id, const char *item_name, int32_t data, const char **log = NULL);\n\n  bool readRegister(uint8_t id, uint16_t address, uint16_t length, uint32_t *data, const char **log = NULL);\n  bool readRegister(uint8_t id, const char *item_name, int32_t *data, const char **log = NULL);\n\n  void getParam(int32_t data, uint8_t *param);\n\n  bool addSyncWriteHandler(uint16_t address, uint16_t length, const char **log = NULL);\n  bool addSyncWriteHandler(uint8_t id, const char *item_name, const char **log = NULL);\n\n  bool syncWrite(uint8_t index, int32_t *data, const char **log = NULL);\n  bool syncWrite(uint8_t index, uint8_t *id, uint8_t id_num, int32_t *data, uint8_t data_num_for_each_id, const char **log = NULL);\n\n  bool addSyncReadHandler(uint16_t address, uint16_t length, const char **log = NULL);\n  bool addSyncReadHandler(uint8_t id, const char *item_name, const char **log = NULL);\n\n  bool syncRead(uint8_t index, const char **log = NULL);\n  bool syncRead(uint8_t index, uint8_t *id, uint8_t id_num, const char **log = NULL);\n\n  bool getSyncReadData(uint8_t index, int32_t *data, const char **log = NULL);\n  bool getSyncReadData(uint8_t index, uint8_t *id, uint8_t id_num, int32_t *data, const char **log = NULL);\n  bool getSyncReadData(uint8_t index, uint8_t *id, uint8_t id_num, uint16_t address, uint16_t length, int32_t *data, const char **log = NULL);\n\n  bool initBulkWrite(const char **log = NULL);\n\n  bool addBulkWriteParam(uint8_t id, uint16_t address, uint16_t length, int32_t data, const char **log = NULL);\n  bool addBulkWriteParam(uint8_t id, const char *item_name, int32_t data, const char **log = NULL);\n\n  bool bulkWrite(const char **log = NULL);\n\n  bool initBulkRead(const char **log = NULL);\n\n  bool addBulkReadParam(uint8_t id, uint16_t address, uint16_t length, const char **log = NULL);\n  bool addBulkReadParam(uint8_t id, const char *item_name, const char **log = NULL);\n\n  bool bulkRead(const char **log = NULL);\n\n  bool getBulkReadData(int32_t *data, const char **log = NULL);\n  bool getBulkReadData(uint8_t *id, uint8_t id_num, uint16_t *address, uint16_t *length, int32_t *data, const char **log = NULL);\n\n  bool clearBulkReadParam(void);\n\n private:\n  void initTools(void);\n  bool setTool(uint16_t model_number, uint8_t id, const char **log = NULL);\n  uint8_t getTool(uint8_t id, const char **log = NULL);\n};\n\n#endif //DYNAMIXEL_DRIVER_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelWorkbench/include/dynamixel_workbench_toolbox/dynamixel_item.h",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Taehun Lim (Darby), Ryan Shim */\n\n#ifndef DYNAMIXEL_ITEM_H\n#define DYNAMIXEL_ITEM_H\n\n#include <stdint.h>\n#include <stddef.h>\n\n#define AX_12A     12\n#define AX_12W     300\n#define AX_18A     18\n\n#define RX_10      10\n#define RX_24F     24\n#define RX_28      28\n#define RX_64      64\n\n#define EX_106     107\n\n#define MX_12W     360\n#define MX_28      29\n#define MX_28_2    30\n#define MX_64      310\n#define MX_64_2    311\n#define MX_106     320\n#define MX_106_2   321\n\n#define XL_320     350\n#define XL330_M077 1190\n#define XL330_M288 1200\n#define XL430_W250 1060\n\n#define XL430_W250_2 1090 // 2XL\n#define XC430_W250_2 1160 // 2XC\n\n#define XC430_W150 1070\n#define XC430_W240 1080\n\n#define XM430_W210 1030\n#define XM430_W350 1020\n\n#define XM540_W150 1130\n#define XM540_W270 1120\n\n#define XH430_W210 1010\n#define XH430_W350 1000\n#define XH430_V210 1050\n#define XH430_V350 1040\n\n#define XH540_W150 1110\n#define XH540_W270 1100\n#define XH540_V150 1150\n#define XH540_V270 1140\n\n#define XW540_T140 1180\n#define XW540_T260 1170\n\n#define PRO_L42_10_S300_R  35072\n#define PRO_L54_30_S400_R  37928\n#define PRO_L54_30_S500_R  37896\n#define PRO_L54_50_S290_R  38176\n#define PRO_L54_50_S500_R  38152\n\n#define PRO_M42_10_S260_R  43288\n#define PRO_M54_40_S250_R  46096\n#define PRO_M54_60_S250_R  46352\n\n#define PRO_H42_20_S300_R  51200\n#define PRO_H54_100_S500_R 53768\n#define PRO_H54_200_S500_R 54024\n\n#define PRO_M42_10_S260_R_A  43289\n#define PRO_M54_40_S250_R_A  46097\n#define PRO_M54_60_S250_R_A  46353\n\n#define PRO_H42_20_S300_R_A  51201\n#define PRO_H54_100_S500_R_A 53769\n#define PRO_H54_200_S500_R_A 54025\n\n#define PRO_PLUS_M42P_010_S260_R  2100\n#define PRO_PLUS_M54P_040_S250_R  2110\n#define PRO_PLUS_M54P_060_S250_R  2120\n\n#define PRO_PLUS_H42P_020_S300_R  2000\n#define PRO_PLUS_H54P_100_S500_R  2010\n#define PRO_PLUS_H54P_200_S500_R  2020\n\n#define RH_P12_RN   35073\n#define RH_P12_RN_A 35074\n\n#define BYTE  1\n#define WORD  2\n#define DWORD 4\n\ntypedef struct \n{\n  const char *item_name;\n  uint16_t    address;\n  uint8_t\t    item_name_length;\n  uint16_t    data_length;\n} ControlItem;\n\ntypedef struct\n{\n  float rpm;\n\n  int64_t value_of_min_radian_position;\n  int64_t value_of_zero_radian_position;\n  int64_t value_of_max_radian_position;\n\n  float  min_radian;\n  float  max_radian;\n} ModelInfo;\n\n// Public Functions\nnamespace DynamixelItem\n{\nconst ControlItem *getControlTable(uint16_t model_number);\nconst ModelInfo *getModelInfo(uint16_t model_number);\n\nuint8_t getTheNumberOfControlItem();\n}\n\n#endif //DYNAMIXEL_ITEM_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelWorkbench/include/dynamixel_workbench_toolbox/dynamixel_tool.h",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Taehun Lim (Darby) */\n\n#ifndef DYNAMIXEL_TOOL_H\n#define DYNAMIXEL_TOOL_H\n\n#include <string.h>\n#include <stdio.h>\n\n#include \"dynamixel_item.h\"\n\nclass DynamixelTool\n{\n private:\n  enum {DYNAMIXEL_BUFFER = 30};\n  uint8_t dxl_id_[DYNAMIXEL_BUFFER];\n  uint8_t dxl_cnt_;\n\n  const char *model_name_;\n  uint16_t model_number_;\n\n  const ControlItem *control_table_;\n  const ModelInfo *model_info_;\n\n  uint16_t the_number_of_control_item_;\n\n public:\n  DynamixelTool();\n  ~DynamixelTool();\n\n  void initTool(void);\n\n  bool addTool(const char *model_name, uint8_t id, const char **log = NULL);\n  bool addTool(uint16_t model_number, uint8_t id, const char **log = NULL);\n\n  void addDXL(uint8_t id);\n\n  const char *getModelName(void);\n  uint16_t getModelNumber(void);\n\n  const uint8_t* getID(void);\n  uint8_t getDynamixelBuffer(void);\n  uint8_t getDynamixelCount(void);\n\n  float getRPM(void);\n\n  int64_t getValueOfMinRadianPosition(void);\n  int64_t getValueOfMaxRadianPosition(void);\n  int64_t getValueOfZeroRadianPosition(void);\n\n  float getMinRadian(void);\n  float getMaxRadian(void);\n\n  uint8_t getTheNumberOfControlItem(void);\n  \n  const ControlItem *getControlItem(const char *item_name, const char **log = NULL);\n  const ControlItem *getControlTable(void);\n  const ModelInfo *getModelInfo(void);\n\n private:\n  bool setControlTable(const char *model_name, const char **log = NULL);\n  bool setControlTable(uint16_t model_number, const char **log = NULL);\n\n  bool setModelName(uint16_t model_number, const char **log = NULL);\n  bool setModelNumber(const char *model_name, const char **log = NULL);\n};\n#endif //DYNAMIXEL_TOOL_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelWorkbench/include/dynamixel_workbench_toolbox/dynamixel_workbench.h",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Taehun Lim (Darby) */\n\n#ifndef DYNAMIXEL_WORKBENCH_H_\n#define DYNAMIXEL_WORKBENCH_H_\n\n#include \"dynamixel_driver.h\"\n\nclass DynamixelWorkbench : public DynamixelDriver\n{\n public:\n  DynamixelWorkbench();\n  ~DynamixelWorkbench();\n\n  bool torque(uint8_t id, int32_t onoff, const char **log = NULL);\n  bool torqueOn(uint8_t id, const char **log = NULL);\n  bool torqueOff(uint8_t id, const char **log = NULL);\n\n  bool changeID(uint8_t id, uint8_t new_id, const char **log = NULL);\n  bool changeBaudrate(uint8_t id, uint32_t new_baudrate, const char **log = NULL);\n  bool changeProtocolVersion(uint8_t id, uint8_t version, const char **log = NULL);\n\n  bool itemWrite(uint8_t id, const char *item_name, int32_t data, const char **log = NULL);\n  bool itemRead(uint8_t id, const char *item_name, int32_t *data, const char **log = NULL);\n\n  bool led(uint8_t id, int32_t onoff, const char **log = NULL);\n  bool ledOn(uint8_t id, const char **log = NULL);\n  bool ledOff(uint8_t id, const char **log = NULL);\n\n  bool setNormalDirection(uint8_t id, const char **log = NULL);\n  bool setReverseDirection(uint8_t id, const char **log = NULL);\n  \n  bool setVelocityBasedProfile(uint8_t id, const char **log = NULL);\n  bool setTimeBasedProfile(uint8_t id, const char **log = NULL);\n\n  bool setSecondaryID(uint8_t id, uint8_t secondary_id, const char **log = NULL);\n\n  bool setCurrentControlMode(uint8_t id, const char **log = NULL);\n  bool setTorqueControlMode(uint8_t id, const char **log = NULL);\n  bool setVelocityControlMode(uint8_t id, const char **log = NULL);  \n  bool setPositionControlMode(uint8_t id, const char **log = NULL);  \n  bool setExtendedPositionControlMode(uint8_t id, const char **log = NULL);\n  bool setMultiTurnControlMode(uint8_t id, const char **log = NULL);\n  bool setCurrentBasedPositionControlMode(uint8_t id, const char **log = NULL);\n  bool setPWMControlMode(uint8_t id, const char **log = NULL);\n\n  bool setOperatingMode(uint8_t id, uint8_t index, const char **log = NULL);\n\n  bool jointMode(uint8_t id, int32_t velocity = 0, int32_t acceleration = 0, const char **log = NULL);\n  bool wheelMode(uint8_t id, int32_t acceleration = 0, const char **log = NULL);\n  bool currentBasedPositionMode(uint8_t id, int32_t current = 0, const char **log = NULL);\n\n  bool goalPosition(uint8_t id, int value, const char **log = NULL);    //keep compatibility with older codes\n  bool goalPosition(uint8_t id, int32_t value, const char **log = NULL);\n  bool goalPosition(uint8_t id, float radian, const char **log = NULL);\n\n  bool goalSpeed(uint8_t id, int value, const char **log = NULL);       //keep compatibility with older codes\n  bool goalVelocity(uint8_t id, int value, const char **log = NULL);    //keep compatibility with older codes  \n  bool goalVelocity(uint8_t id, int32_t value, const char **log = NULL);\n  bool goalVelocity(uint8_t id, float velocity, const char **log = NULL);\n\n  bool getPresentPositionData(uint8_t id, int32_t* data, const char **log = NULL);\n  bool getRadian(uint8_t id, float* radian, const char **log = NULL);\n\n  bool getPresentVelocityData(uint8_t id, int32_t* data, const char **log = NULL);\n  bool getVelocity(uint8_t id, float* velocity, const char **log = NULL);\n\n  int32_t convertRadian2Value(uint8_t id, float radian);\n  float convertValue2Radian(uint8_t id, int32_t value);\n\n  int32_t convertRadian2Value(float radian, int32_t max_position, int32_t min_position, float max_radian, float min_radian);\n  float convertValue2Radian(int32_t value, int32_t max_position, int32_t min_position, float max_radian, float min_radian);\n\n  int32_t convertVelocity2Value(uint8_t id, float velocity);\n  float convertValue2Velocity(uint8_t id, int32_t value);\n\n  int16_t convertCurrent2Value(uint8_t id, float current);\n  int16_t convertCurrent2Value(float current);\n  float convertValue2Current(uint8_t id, int16_t value);\n  float convertValue2Current(int16_t value);\n\n  float convertValue2Load(int16_t value);\n};\n\n#endif /*DYNAMIXEL_WORKBENCH_H_*/\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelWorkbench/keywords.txt",
    "content": "#######################################\n# Syntax Coloring Map DynamixelWorkbench\n#######################################\n\n#######################################\n# Datatypes (KEYWORD1)\n#######################################\nDynamixelWorkbench\t\t\tKEYWORD1\n\n#######################################\n# Methods and Functions (KEYWORD2)\n#######################################\nbegin\t\t\t            KEYWORD2\nscan\t\t\t            KEYWORD2\nping\t\t\t            KEYWORD2\nreboot\t              KEYWORD2\nreset                 KEYWORD2\nsetID\t\t\t            KEYWORD2\nsetBaud \t            KEYWORD2\nsetPacketHandler\t\t  KEYWORD2\ngetModelName          KEYWORD2\nledOn                 KEYWORD2\nledOff                KEYWORD2\njointMode             KEYWORD2\nwheelMode             KEYWORD2\ncurrentMode           KEYWORD2\ngoalPosition          KEYWORD2\ngoalSpeed             KEYWORD2\nitemWrite             KEYWORD2\nsyncWrite             KEYWORD2\nbulkWrite             KEYWORD2\nitemRead              KEYWORD2\nsyncRead              KEYWORD2\nbulkRead              KEYWORD2\naddSyncWrite          KEYWORD2\naddSyncRead           KEYWORD2\ninitBulkWrite         KEYWORD2\ninitBulkRead          KEYWORD2\naddBulkWriteParam     KEYWORD2\naddBulkReadParam      KEYWORD2\nsetBulkRead           KEYWORD2\nconvertRadian2Value   KEYWORD2\nconvertValue2Radian   KEYWORD2\nconvertVelocity2Value KEYWORD2\nconvertValue2Velocity KEYWORD2\nconvertTorque2Value   KEYWORD2\nconvertValue2Torque   KEYWORD2\n\n#######################################\n# Constants (LITERAL1)\n#######################################\nX_SERIES_CURRENT_CONTROL_MODE                 LITERAL1\nX_SERIES_VELOCITY_CONTROL_MODE\t\t            LITERAL1\nX_SERIES_POSITION_CONTROL_MODE\t\t            LITERAL1\nX_SERIES_EXTENDED_POSITION_CONTROL_MODE\t\t    LITERAL1\nX_SERIES_CURRENT_BASED_POSITION_CONTROL_MODE\tLITERAL1\nX_SERIES_VOLTAGE_CONTROL_MODE\t                LITERAL1\nPRO_SERIES_TORQUE_CONTROL_MODE                LITERAL1\nPRO_SERIES_VELOCITY_CONTROL_MODE              LITERAL1\nPRO_SERIES_POSITION_CONTROL_MODE              LITERAL1\nPRO_SERIES_EXTENDED_POSITION_CONTROL_MODE     LITERAL1"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelWorkbench/library.properties",
    "content": "name=DynamixelWorkbench\nversion=0.1.0\nauthor=Darby Lim (thlim@robotis.com)\nmaintainer=Pyo(pyo@robotis.com)\nsentence=DynamixelWorkbench using DynamixelSDK\nparagraph=\ncategory=Other\nurl=https://github.com/ROBOTIS-GIT/dynamixel-workbench\narchitectures=OpenCR\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelWorkbench/src/DynamixelWorkbench.h",
    "content": "#include \"../include/dynamixel_workbench_toolbox/dynamixel_workbench.h\"\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelWorkbench/src/dynamixel_workbench_toolbox/dynamixel_driver.cpp",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Taehun Lim (Darby) */\n\n#include \"../../include/dynamixel_workbench_toolbox/dynamixel_driver.h\"\n\nDynamixelDriver::DynamixelDriver() : tools_cnt_(0), \n                                    sync_write_handler_cnt_(0), \n                                    sync_read_handler_cnt_(0),\n                                    bulk_read_parameter_cnt_(0)\n{\n\n}\n\nDynamixelDriver::~DynamixelDriver()\n{ \n  for (int i = 0; i < tools_cnt_; i++)\n  {\n    for (int j = 0; j < tools_[i].getDynamixelCount(); j++)\n    {\n      writeRegister(tools_[i].getID()[j], \"Torque_Enable\", (uint8_t)0);\n    }\n  }\n\n  portHandler_->closePort();\n}\n\nvoid DynamixelDriver::initTools(void)\n{\n  for (uint8_t num = 0; num < MAX_DXL_SERIES_NUM; num++)\n    tools_[num].initTool();\n\n  tools_cnt_ = 0;\n}\n\nbool DynamixelDriver::setTool(uint16_t model_number, uint8_t id, const char **log)\n{\n  bool result = false;\n\n  // See if we have a matching tool? \n  for (uint8_t num = 0; num < tools_cnt_; num++)\n  {\n    if (tools_[num].getModelNumber() == model_number)\n    {\n      if (tools_[num].getDynamixelCount() < tools_[num].getDynamixelBuffer())\n      {\n        // Found one with the right model number and it is not full\n        tools_[num].addDXL(id);\n        return true;\n      }\n      else\n      {\n        if (log != NULL) *log = \"[DynamixelDriver] Too many Dynamixels are connected (default buffer size is 16, the same series of Dynamixels)\";\n        return false;\n      }\n    }\n  }\n  // We did not find one so lets allocate a new one\n  if (tools_cnt_ < MAX_DXL_SERIES_NUM) \n  {\n    // only do it if we still have some room...\n    result = tools_[tools_cnt_++].addTool(model_number, id, log);\n    return result;\n  }\n  else\n  {\n    if (log != NULL) *log = \"[DynamixelDriver] Too many series are connected (MAX = 5 different series)\";\n    return false;\n  }\n\n  if (log != NULL) *log = \"[DynamixelDriver] Failed to set the Tool\";\n  return false;\n}\n\nuint8_t DynamixelDriver::getTool(uint8_t id, const char **log)\n{\n  for (int i = 0; i < tools_cnt_; i++)\n  {\n    for (int j = 0; j < tools_[i].getDynamixelCount(); j++)\n    {\n      if (tools_[i].getID()[j] == id)\n      {\n        return i;\n      }\n    }\n  }\n\n  if (log != NULL) *log = \"[DynamixelDriver] Failed to get the Tool\";\n  return 0xff;\n}\n\nbool DynamixelDriver::init(const char *device_name, uint32_t baud_rate, const char **log)\n{\n  bool result = false;\n\n  result = setPortHandler(device_name, log);\n  if (result == false) return false;\n\n  result = setBaudrate(baud_rate, log);\n  if (result == false) return false;\n\n  result = setPacketHandler(2.0f, log);\n  if (result == false) return false;\n\n  return result;\n}\n\nbool DynamixelDriver::begin(const char *device_name, uint32_t baud_rate, const char **log)\n{\n  return init(device_name, baud_rate, log);\n}\n\nbool DynamixelDriver::setPortHandler(const char *device_name, const char **log)\n{\n  portHandler_ = dynamixel::PortHandler::getPortHandler(device_name);\n\n  if (portHandler_->openPort())\n  {\n    if (log != NULL) *log = \"[DynamixelDriver] Succeeded to open the port!\";\n    return true;\n  }\n\n  if (log != NULL) *log = \"[DynamixelDriver] Failed to open the port!\";\n  return false;\n}\n\nbool DynamixelDriver::setBaudrate(uint32_t baud_rate, const char **log)\n{\n  if (portHandler_->setBaudRate((int)baud_rate))\n  {\n    if (log != NULL) *log = \"[DynamixelDriver] Succeeded to change the baudrate!\";\n    return true;\n  }\n\n  if (log != NULL) *log = \"[DynamixelDriver] Failed to change the baudrate!\";\n  return false;\n}\n\nbool DynamixelDriver::setPacketHandler(float protocol_version, const char **log)\n{\n  packetHandler_ = dynamixel::PacketHandler::getPacketHandler(protocol_version);\n\n  if (packetHandler_->getProtocolVersion() == protocol_version)\n  {\n    if (log != NULL) *log = \"[DynamixelDriver] Succeeded to set the protocol!\";\n    return true;\n  }\n\n  if (log != NULL) *log = \"[DynamixelDriver] Failed to set the protocol!\";\n  return false;\n}\n\nfloat DynamixelDriver::getProtocolVersion(void)\n{\n  return packetHandler_->getProtocolVersion();\n}\n\nuint32_t DynamixelDriver::getBaudrate(void)\n{\n  return portHandler_->getBaudRate();\n}\n\nconst char* DynamixelDriver::getModelName(uint8_t id, const char **log)\n{\n  uint8_t factor = getTool(id, log);\n  if (factor == 0xff) \n    return NULL;\n  else\n    return tools_[factor].getModelName();\n\n  return NULL;\n}\n\nuint16_t DynamixelDriver::getModelNumber(uint8_t id, const char **log)\n{\n  uint8_t factor = getTool(id, log);\n  if (factor == 0xff) return false;\n\n  for (int i = 0; i < tools_[factor].getDynamixelCount(); i++)\n  {\n    if (tools_[factor].getID()[i] == id)\n      return tools_[factor].getModelNumber();\n  }\n\n  return false;\n}\n\nconst ControlItem* DynamixelDriver::getControlTable(uint8_t id, const char **log)\n{\n  uint8_t factor = getTool(id, log);\n  if (factor == 0xff) return NULL;\n\n  return tools_[factor].getControlTable();\n}\n\nconst ControlItem* DynamixelDriver::getItemInfo(uint8_t id, const char *item_name, const char **log)\n{\n  const ControlItem *control_item;\n\n  uint8_t factor = getTool(id, log);\n  if (factor == 0xff) return NULL; \n\n  control_item = tools_[factor].getControlItem(item_name, log);\n  if (control_item == NULL) return NULL;\n  else return control_item;\n\n  return NULL;\n}\n\nuint8_t DynamixelDriver::getTheNumberOfControlItem(uint8_t id, const char **log)\n{\n  uint8_t factor = getTool(id, log);\n  if (factor == 0xff) return false;\n\n  return tools_[factor].getTheNumberOfControlItem();\n}\n\nconst ModelInfo* DynamixelDriver::getModelInfo(uint8_t id, const char **log)\n{\n  uint8_t factor = getTool(id, log);\n  if (factor == 0xff) return NULL;\n\n  return tools_[factor].getModelInfo();\n}\n\nuint8_t DynamixelDriver::getTheNumberOfSyncWriteHandler(void)\n{\n  return sync_write_handler_cnt_;\n}\n\nuint8_t DynamixelDriver::getTheNumberOfSyncReadHandler(void)\n{\n  return sync_read_handler_cnt_;\n}\n\nuint8_t DynamixelDriver::getTheNumberOfBulkReadParam(void)\n{\n  return bulk_read_parameter_cnt_;\n}\n\nbool DynamixelDriver::scan(uint8_t *get_id, uint8_t *get_the_number_of_id, uint8_t start_num, uint8_t end_num, const char **log)\n{\n  ErrorFromSDK sdk_error = {0, false, false, 0};\n  bool result = false;\n\n  uint8_t id = 0;\n  uint8_t id_cnt = 0;\n\n  uint16_t model_number = 0;\n\n  uint8_t get_end_num = end_num;\n\n  if (get_end_num > 253) get_end_num = 253;\n\n  initTools();\n\n  result = setPacketHandler(1.0f, log);\n  if (result == false) return false;\n\n  for (id = start_num; id <= get_end_num; id++)\n  { \n    sdk_error.dxl_comm_result = packetHandler_->ping(portHandler_, id, &model_number, &sdk_error.dxl_error);\n    if (sdk_error.dxl_comm_result != COMM_SUCCESS)\n    {\n      if (log != NULL) *log = packetHandler_->getTxRxResult(sdk_error.dxl_comm_result);\n    }\n    else if (sdk_error.dxl_error != 0)\n    {\n      if (log != NULL) *log = packetHandler_->getRxPacketError(sdk_error.dxl_error);\n    }\n    else\n    {\n      get_id[id_cnt++] = id;\n      setTool(model_number, id);\n    }    \n  }\n\n  if (id_cnt > 0)\n  {\n    *get_the_number_of_id = id_cnt;\n    return result;\n  }\n\n  result = setPacketHandler(2.0f, log);\n  if (result == false) return false;\n\n  for (id = start_num; id <= get_end_num; id++)\n  {\n    sdk_error.dxl_comm_result = packetHandler_->ping(portHandler_, id, &model_number, &sdk_error.dxl_error);\n    \n    if (sdk_error.dxl_comm_result != COMM_SUCCESS)\n    {\n      if (log != NULL) *log = packetHandler_->getTxRxResult(sdk_error.dxl_comm_result);\n    }\n    else if (sdk_error.dxl_error != 0)\n    {\n      if (log != NULL) *log = packetHandler_->getRxPacketError(sdk_error.dxl_error);\n    }\n    else\n    {\n      get_id[id_cnt++] = id;\n      setTool(model_number, id);\n    }   \n  }\n\n  if (id_cnt > 0)\n  {\n    *get_the_number_of_id = id_cnt;\n    return result;\n  }\n\n  return result;\n}\n\nbool DynamixelDriver::scan(uint8_t *get_id, uint8_t *get_the_number_of_id, uint8_t range, const char **log)\n{\n  return scan(get_id, get_the_number_of_id, 0, range, log);\n}\n\nbool DynamixelDriver::ping(uint8_t id, uint16_t *get_model_number, const char **log)\n{\n  ErrorFromSDK sdk_error = {0, false, false, 0};\n  bool result = false;\n\n  uint16_t model_number = 0;\n\n  result = setPacketHandler(1.0f, log);\n  if (result == false) return false;\n\n  sdk_error.dxl_comm_result = packetHandler_->ping(portHandler_, id, &model_number, &sdk_error.dxl_error);  \n  if (sdk_error.dxl_comm_result != COMM_SUCCESS)\n  {\n    if (log != NULL)  *log = packetHandler_->getTxRxResult(sdk_error.dxl_comm_result);\n  }\n  else if (sdk_error.dxl_error != 0)\n  {\n    if (log != NULL)  *log = packetHandler_->getRxPacketError(sdk_error.dxl_error);\n  }\n  else\n  {\n    setTool(model_number, id);\n    if (get_model_number != NULL) *get_model_number = model_number;\n    return true;\n  }\n\n  result = setPacketHandler(2.0f, log);\n  if (result == false) return false;\n\n  sdk_error.dxl_comm_result = packetHandler_->ping(portHandler_, id, &model_number, &sdk_error.dxl_error);  \n  if (sdk_error.dxl_comm_result != COMM_SUCCESS)\n  {\n    if (log != NULL)  *log = packetHandler_->getTxRxResult(sdk_error.dxl_comm_result);\n  }\n  else if (sdk_error.dxl_error != 0)\n  {\n    if (log != NULL)  *log = packetHandler_->getRxPacketError(sdk_error.dxl_error);\n  }\n  else\n  {\n    setTool(model_number, id);\n    if (get_model_number != NULL) *get_model_number = model_number;\n    return true;\n  }  \n\n  return false;\n}\n\nbool DynamixelDriver::ping(uint8_t id, const char **log)\n{\n  return ping(id, NULL, log);\n}\n\nbool DynamixelDriver::clearMultiTurn(uint8_t id, const char **log)\n{\n  ErrorFromSDK sdk_error = {0, false, false, 0};\n\n  sdk_error.dxl_comm_result = packetHandler_->clearMultiTurn(portHandler_, id, &sdk_error.dxl_error);\n  if (sdk_error.dxl_comm_result != COMM_SUCCESS)\n  {\n    if (log != NULL) *log = packetHandler_->getTxRxResult(sdk_error.dxl_comm_result);\n    return false;\n  }\n  else if (sdk_error.dxl_error != 0)\n  {\n    if (log != NULL) *log = packetHandler_->getRxPacketError(sdk_error.dxl_error);\n    return false;\n  }\n  else\n  {\n    if (log != NULL) *log = \"[DynamixelDriver] Succeeded to clear!\";\n    return true;\n  }\n\n  return false;\n}\n\nbool DynamixelDriver::reboot(uint8_t id, const char **log)\n{\n  ErrorFromSDK sdk_error = {0, false, false, 0};\n\n  if (getProtocolVersion() == 1.0)\n  {\n    if (log != NULL) *log = \"[DynamixelDriver] reboot functions is not available with the Dynamixel Protocol 1.0.\";\n    return false;\n  }\n  else\n  {\n    sdk_error.dxl_comm_result = packetHandler_->reboot(portHandler_, id, &sdk_error.dxl_error);\n#if defined(__OPENCR__) || defined(__OPENCM904__)\n    delay(1000);\n#else\n    usleep(1000*1000);\n#endif\n\n    if (sdk_error.dxl_comm_result != COMM_SUCCESS)\n    {\n      if (log != NULL) *log = packetHandler_->getTxRxResult(sdk_error.dxl_comm_result);\n      return false;\n    }\n    else if (sdk_error.dxl_error != 0)\n    {\n      if (log != NULL) *log = packetHandler_->getRxPacketError(sdk_error.dxl_error);\n      return false;\n    }\n    else\n    {\n      if (log != NULL) *log = \"[DynamixelDriver] Succeeded to reboot!\";\n      return true;\n    }\n  }\n\n  return false;\n}\n\nbool DynamixelDriver::reset(uint8_t id, const char **log)\n{\n  ErrorFromSDK sdk_error = {0, false, false, 0};\n  bool result = false;\n\n  uint32_t new_baud_rate = 0;\n  uint8_t new_id = 1;\n\n  const char* model_name = getModelName(id, log);\n  if (model_name == NULL) return false;\n\n  uint16_t model_number = getModelNumber(id, log);\n  if (model_number == 0) return false;\n\n  if (getProtocolVersion() == 1.0)\n  {\n    sdk_error.dxl_comm_result = packetHandler_->factoryReset(portHandler_, id, 0x00, &sdk_error.dxl_error);\n#if defined(__OPENCR__) || defined(__OPENCM904__)\n    delay(2000);\n#else\n    usleep(1000*2000);\n#endif\n\n    if (sdk_error.dxl_comm_result != COMM_SUCCESS)\n    {\n      if (log != NULL) *log = packetHandler_->getTxRxResult(sdk_error.dxl_comm_result);\n      return false;\n    }\n    else if (sdk_error.dxl_error != 0)\n    {\n      if (log != NULL) *log = packetHandler_->getRxPacketError(sdk_error.dxl_error);\n      return false;\n    }\n    else\n    {\n      if (!strncmp(model_name, \"AX\", strlen(\"AX\")) ||\n          !strncmp(model_name, \"MX-12W\", strlen(\"MX-12W\")))\n        new_baud_rate = 1000000;\n      else\n        new_baud_rate = 57600;\n\n      result = setBaudrate(new_baud_rate, log);\n      if (result == false) \n        return false;\n      else\n      {\n        if (!strncmp(model_name, \"MX-28-2\", strlen(\"MX-28-2\"))   ||\n            !strncmp(model_name, \"MX-64-2\", strlen(\"MX-64-2\"))   ||\n            !strncmp(model_name, \"MX-106-2\", strlen(\"MX-106-2\")) ||\n            !strncmp(model_name, \"XL\", strlen(\"XL\"))  ||\n            !strncmp(model_name, \"XM\", strlen(\"XM\"))  ||\n            !strncmp(model_name, \"XH\", strlen(\"XH\"))  ||\n            !strncmp(model_name, \"PRO\", strlen(\"PRO\"))||\n            !strncmp(model_name, \"RH\", strlen(\"RH\")))\n        {\n          result = setPacketHandler(2.0f, log);\n          if (result == false) return false;\n        }          \n        else\n        {\n          result = setPacketHandler(1.0f, log);\n          if (result == false) return false; \n        }\n      }\n    }\n\n    initTools();\n    result = setTool(model_number, new_id, log);\n    if (result == false) return false; \n    \n    if (log != NULL) *log = \"[DynamixelDriver] Succeeded to reset!\";\n    return true;\n  }\n  else if (getProtocolVersion() == 2.0)\n  {\n    sdk_error.dxl_comm_result = packetHandler_->factoryReset(portHandler_, id, 0xff, &sdk_error.dxl_error);\n#if defined(__OPENCR__) || defined(__OPENCM904__)\n    delay(2000);\n#else\n    usleep(1000*2000);\n#endif\n\n    if (sdk_error.dxl_comm_result != COMM_SUCCESS)\n    {\n      if (log != NULL) *log = packetHandler_->getTxRxResult(sdk_error.dxl_comm_result);\n      return false;\n    }\n    else if (sdk_error.dxl_error != 0)\n    {\n      if (log != NULL) *log = packetHandler_->getRxPacketError(sdk_error.dxl_error);\n      return false;\n    }\n    else\n    {\n      if (!strncmp(model_name, \"XL-320\", strlen(\"XL-320\"))) \n        new_baud_rate = 1000000;\n      else \n        new_baud_rate = 57600;\n\n      result = setBaudrate(new_baud_rate, log);\n      if (result == false) \n        return false;\n      else\n      {\n        result = setPacketHandler(2.0f, log);\n        if (result == false)  return false;\n      }\n    }\n\n    initTools();\n    result = setTool(model_number, new_id, log);\n    if (result == false) return false; \n    \n    if (log != NULL) *log = \"[DynamixelDriver] Succeeded to reset!\";\n    return true;\n  }\n\n  return result;\n}\n\nbool DynamixelDriver::writeRegister(uint8_t id, uint16_t address, uint16_t length, uint8_t* data, const char **log)\n{\n  ErrorFromSDK sdk_error = {0, false, false, 0};\n\n#if defined(__OPENCR__) || defined(__OPENCM904__)\n    delay(10);\n#else\n    usleep(1000*10);\n#endif\n\n  sdk_error.dxl_comm_result = packetHandler_->writeTxRx(portHandler_, \n                                                        id, \n                                                        address, \n                                                        length, \n                                                        data,\n                                                        &sdk_error.dxl_error);\n  if (sdk_error.dxl_comm_result != COMM_SUCCESS)\n  {\n    if (log != NULL) *log = packetHandler_->getTxRxResult(sdk_error.dxl_comm_result);\n    return false;\n  }\n  else if (sdk_error.dxl_error != 0)\n  {\n    if (log != NULL) *log = packetHandler_->getRxPacketError(sdk_error.dxl_error);\n    return false;\n  }\n  else\n  {\n    if (log != NULL) *log = \"[DynamixelDriver] Succeeded to write!\";\n    return true;\n  }\n\n  return false;\n}\n\nbool DynamixelDriver::writeRegister(uint8_t id, const char *item_name, int32_t data, const char **log)\n{\n  ErrorFromSDK sdk_error = {0, false, false, 0};\n\n  const ControlItem *control_item;\n\n  uint8_t factor = getTool(id, log);\n  if (factor == 0xff) return false;\n\n  control_item = tools_[factor].getControlItem(item_name, log);\n  if (control_item == NULL) return false;\n\n  uint8_t data_1_byte = (uint8_t)data;\n  uint16_t data_2_byte = (uint16_t)data;\n  uint32_t data_4_byte = (uint32_t)data;\n\n#if defined(__OPENCR__) || defined(__OPENCM904__)\n    delay(10);\n#else\n    usleep(1000*10);\n#endif\n\n  switch (control_item->data_length)\n  {\n    case BYTE:\n      sdk_error.dxl_comm_result = packetHandler_->write1ByteTxRx(portHandler_,\n                                                            id,\n                                                            control_item->address,\n                                                            data_1_byte,\n                                                            &sdk_error.dxl_error);\n     break;\n\n    case WORD:\n      sdk_error.dxl_comm_result = packetHandler_->write2ByteTxRx(portHandler_,\n                                                            id,\n                                                            control_item->address,\n                                                            data_2_byte,\n                                                            &sdk_error.dxl_error);\n     break;\n\n    case DWORD:\n      sdk_error.dxl_comm_result = packetHandler_->write4ByteTxRx(portHandler_,\n                                                            id,\n                                                            control_item->address,\n                                                            data_4_byte,\n                                                            &sdk_error.dxl_error);\n     break;\n\n    default:\n      sdk_error.dxl_comm_result = packetHandler_->write1ByteTxRx(portHandler_,\n                                                            id,\n                                                            control_item->address,\n                                                            data_1_byte,\n                                                            &sdk_error.dxl_error);\n     break;\n  }\n\n  if (sdk_error.dxl_comm_result != COMM_SUCCESS)\n  {\n    if (log != NULL) *log = packetHandler_->getTxRxResult(sdk_error.dxl_comm_result);\n    return false;\n  }\n  else if (sdk_error.dxl_error != 0)\n  {\n    if (log != NULL) *log = packetHandler_->getRxPacketError(sdk_error.dxl_error);\n    return false;\n  }\n  else\n  {\n    if (log != NULL) *log = \"[DynamixelDriver] Succeeded to write!\";\n    return true;\n  }\n\n  return false;\n}\n\nbool DynamixelDriver::writeOnlyRegister(uint8_t id, uint16_t address, uint16_t length, uint8_t *data, const char **log)\n{\n  ErrorFromSDK sdk_error = {0, false, false, 0};\n\n#if defined(__OPENCR__) || defined(__OPENCM904__)\n    delay(10);\n#else\n    usleep(1000*10);\n#endif\n\n  sdk_error.dxl_comm_result = packetHandler_->writeTxOnly(portHandler_, \n                                                          id, \n                                                          address, \n                                                          length, \n                                                          data);\n  if (sdk_error.dxl_comm_result != COMM_SUCCESS)\n  {\n    if (log != NULL) *log = packetHandler_->getTxRxResult(sdk_error.dxl_comm_result);\n    return false;\n  }\n  else\n  {\n    if (log != NULL) *log = \"[DynamixelDriver] Succeeded to write!\";\n    return true;\n  }\n\n  return false;\n}\n\nbool DynamixelDriver::writeOnlyRegister(uint8_t id, const char *item_name, int32_t data, const char **log)\n{\n  ErrorFromSDK sdk_error = {0, false, false, 0};\n\n  const ControlItem *control_item;\n\n  uint8_t factor = getTool(id, log);\n  if (factor == 0xff) return false;\n\n  control_item = tools_[factor].getControlItem(item_name, log);\n  if (control_item == NULL) return false;\n\n#if defined(__OPENCR__) || defined(__OPENCM904__)\n    delay(10);\n#else\n    usleep(1000*10);\n#endif\n\n  switch (control_item->data_length)\n  {\n    case BYTE:\n      sdk_error.dxl_comm_result = packetHandler_->write1ByteTxOnly(portHandler_,\n                                                            id,\n                                                            control_item->address,\n                                                            (uint8_t)data);\n     break;\n\n    case WORD:\n      sdk_error.dxl_comm_result = packetHandler_->write2ByteTxOnly(portHandler_,\n                                                            id,\n                                                            control_item->address,\n                                                            (uint16_t)data);\n     break;\n\n    case DWORD:\n      sdk_error.dxl_comm_result = packetHandler_->write4ByteTxOnly(portHandler_,\n                                                            id,\n                                                            control_item->address,\n                                                            (uint32_t)data);\n     break;\n\n    default:\n      sdk_error.dxl_comm_result = packetHandler_->write1ByteTxOnly(portHandler_,\n                                                            id,\n                                                            control_item->address,\n                                                            (uint8_t)data);\n     break;\n  }\n\n  if (sdk_error.dxl_comm_result != COMM_SUCCESS)\n  {\n    if (log != NULL) *log = packetHandler_->getTxRxResult(sdk_error.dxl_comm_result);\n    return false;\n  }\n  else\n  {\n    if (log != NULL) *log = \"[DynamixelDriver] Succeeded to write!\";\n    return true;\n  }\n\n  return false;\n}\n\nbool DynamixelDriver::readRegister(uint8_t id, uint16_t address, uint16_t length, uint32_t *data, const char **log)\n{\n  ErrorFromSDK sdk_error = {0, false, false, 0};\n  \n  uint8_t data_read[length];\n\n  sdk_error.dxl_comm_result = packetHandler_->readTxRx(portHandler_, \n                                                      id, \n                                                      address,\n                                                      length, \n                                                      (uint8_t *)&data_read, \n                                                      &sdk_error.dxl_error);\n  if (sdk_error.dxl_comm_result != COMM_SUCCESS)\n  {\n    if (log != NULL) *log = packetHandler_->getTxRxResult(sdk_error.dxl_comm_result);\n    return false;\n  }\n  else if (sdk_error.dxl_error != 0)\n  {\n    if (log != NULL) *log = packetHandler_->getRxPacketError(sdk_error.dxl_error);\n    return false;\n  }\n  else\n  {\n    switch (length)\n    {\n      case BYTE:\n        *data = data_read[0];\n       break;\n\n      case WORD:\n        *data = DXL_MAKEWORD(data_read[0], data_read[1]);\n       break;\n\n      case DWORD:\n        *data = DXL_MAKEDWORD(DXL_MAKEWORD(data_read[0], data_read[1]), DXL_MAKEWORD(data_read[2], data_read[3]));\n       break;\n\n      default:\n        for (uint16_t index = 0; index < length; index++)\n        {\n          data[index] = (uint32_t)data_read[index];\n        }\n       break;\n    }\n    if (log != NULL) *log = \"[DynamixelDriver] Succeeded to read!\";\n    return true;\n  }\n\n  return false;\n}\n\nbool DynamixelDriver::readRegister(uint8_t id, const char *item_name, int32_t *data, const char **log)\n{\n  ErrorFromSDK sdk_error = {0, false, false, 0};\n\n  const ControlItem *control_item;\n\n  uint8_t factor = getTool(id, log);\n  if (factor == 0xff) return false;\n\n  control_item = tools_[factor].getControlItem(item_name, log);\n  if (control_item == NULL) return false;\n\n  uint8_t data_1_byte  = 0;\n  uint16_t data_2_byte = 0;\n  uint32_t data_4_byte = 0;\n\n  switch (control_item->data_length)\n  {\n    case BYTE:\n      sdk_error.dxl_comm_result = packetHandler_->read1ByteTxRx(portHandler_,\n                                                            id,\n                                                            control_item->address,\n                                                            &data_1_byte,\n                                                            &sdk_error.dxl_error);\n     break;\n\n    case WORD:\n      sdk_error.dxl_comm_result = packetHandler_->read2ByteTxRx(portHandler_,\n                                                            id,\n                                                            control_item->address,\n                                                            &data_2_byte,\n                                                            &sdk_error.dxl_error);\n     break;\n\n    case DWORD:\n      sdk_error.dxl_comm_result = packetHandler_->read4ByteTxRx(portHandler_,\n                                                            id,\n                                                            control_item->address,\n                                                            &data_4_byte,\n                                                            &sdk_error.dxl_error);\n     break;\n\n    default:\n      sdk_error.dxl_comm_result = packetHandler_->read1ByteTxRx(portHandler_,\n                                                            id,\n                                                            control_item->address,\n                                                            &data_1_byte,\n                                                            &sdk_error.dxl_error);\n     break;\n  }\n\n  if (sdk_error.dxl_comm_result != COMM_SUCCESS)\n  {\n    if (log != NULL) *log = packetHandler_->getTxRxResult(sdk_error.dxl_comm_result);\n    return false;\n  }\n  else if (sdk_error.dxl_error != 0)\n  {\n    if (log != NULL) *log = packetHandler_->getRxPacketError(sdk_error.dxl_error);\n    return false;\n  }\n  else\n  {\n    switch (control_item->data_length)\n    {\n      case BYTE:\n        *data = data_1_byte;\n      break;\n\n      case WORD:\n        *data = data_2_byte;\n      break;\n\n      case DWORD:\n        *data = data_4_byte;\n      break;\n\n      default:\n        *data = data_1_byte;\n      break;\n    }\n\n    if (log != NULL) *log = \"[DynamixelDriver] Succeeded to read!\";\n    return true;\n  }\n\n  return false;\n}\n\nvoid DynamixelDriver::getParam(int32_t data, uint8_t *param)\n{\n  param[0] = DXL_LOBYTE(DXL_LOWORD(data));\n  param[1] = DXL_HIBYTE(DXL_LOWORD(data));\n  param[2] = DXL_LOBYTE(DXL_HIWORD(data));\n  param[3] = DXL_HIBYTE(DXL_HIWORD(data));\n}\n\nbool DynamixelDriver::addSyncWriteHandler(uint16_t address, uint16_t length, const char **log)\n{\n  if (sync_write_handler_cnt_ > (MAX_HANDLER_NUM-1))\n  {\n    if (log != NULL) *log = \"[DynamixelDriver] Too many sync write handler are added (MAX = 5)\";\n    return false;\n  }\n\n  syncWriteHandler_[sync_write_handler_cnt_].control_item = NULL;\n\n  syncWriteHandler_[sync_write_handler_cnt_].groupSyncWrite = new dynamixel::GroupSyncWrite(portHandler_,\n                                                                                            packetHandler_,\n                                                                                            address,\n                                                                                            length);\n\n  sync_write_handler_cnt_++;\n\n  if (log != NULL) *log = \"[DynamixelDriver] Succeeded to add sync write handler\";\n  return true;    \n}\n\nbool DynamixelDriver::addSyncWriteHandler(uint8_t id, const char *item_name, const char **log)\n{\n  const ControlItem *control_item;\n\n  uint8_t factor = getTool(id, log);\n  if (factor == 0xff) return false; \n\n  control_item = tools_[factor].getControlItem(item_name, log);\n  if (control_item == NULL) return false;\n\n  if (sync_write_handler_cnt_ > (MAX_HANDLER_NUM-1))\n  {\n    if (log != NULL) *log = \"[DynamixelDriver] Too many sync write handler are added (MAX = 5)\";\n    return false;\n  }\n\n  syncWriteHandler_[sync_write_handler_cnt_].control_item = control_item;\n\n  syncWriteHandler_[sync_write_handler_cnt_].groupSyncWrite = new dynamixel::GroupSyncWrite(portHandler_,\n                                                                                            packetHandler_,\n                                                                                            control_item->address,\n                                                                                            control_item->data_length);\n\n  sync_write_handler_cnt_++;\n\n  if (log != NULL) *log = \"[DynamixelDriver] Succeeded to add sync write handler\";\n  return true;                                                            \n}\n\nbool DynamixelDriver::syncWrite(uint8_t index, int32_t *data, const char **log)\n{\n  ErrorFromSDK sdk_error = {0, false, false, 0};\n\n  uint8_t dxl_cnt = 0;\n  uint8_t parameter[4] = {0, 0, 0, 0};\n\n  for (int i = 0; i < tools_cnt_; i++)\n  {\n    for (int j = 0; j < tools_[i].getDynamixelCount(); j++)\n    {\n      getParam(data[dxl_cnt], parameter);\n      sdk_error.dxl_addparam_result = syncWriteHandler_[index].groupSyncWrite->addParam(tools_[i].getID()[j], (uint8_t *)&parameter);\n      if (sdk_error.dxl_addparam_result != true)\n      {\n        if (log != NULL) *log = \"groupSyncWrite addparam failed\";\n        return false;\n      }\n      else\n        dxl_cnt++;\n    }\n  }\n\n  sdk_error.dxl_comm_result = syncWriteHandler_[index].groupSyncWrite->txPacket();\n  if (sdk_error.dxl_comm_result != COMM_SUCCESS)\n  {\n    if (log != NULL) *log = packetHandler_->getTxRxResult(sdk_error.dxl_comm_result);\n    return false;\n  }\n\n  syncWriteHandler_[index].groupSyncWrite->clearParam();\n\n  if (log != NULL) *log = \"[DynamixelDriver] Succeeded to sync write!\";\n  return true;\n}\n\nbool DynamixelDriver::syncWrite(uint8_t index, uint8_t *id, uint8_t id_num, int32_t *data, uint8_t data_num_for_each_id, const char **log)\n{\n  ErrorFromSDK sdk_error = {0, false, false, 0};\n\n  uint8_t parameter[4] = {0, 0, 0, 0};\n  uint8_t multi_parameter[4*data_num_for_each_id];\n  uint8_t cnt = 0;\n\n  for (int i = 0; i < id_num; i++)\n  {\n    for (int j = 0; j < data_num_for_each_id; j++)\n    {\n      getParam(data[cnt++], parameter);\n      for (int k = 0; k < 4; k++)\n      {\n        multi_parameter[4*j+k] = parameter[k];\n      }\n    }\n\n    sdk_error.dxl_addparam_result = syncWriteHandler_[index].groupSyncWrite->addParam(id[i], (uint8_t *)&multi_parameter);\n    if (sdk_error.dxl_addparam_result != true)\n    {\n      if (log != NULL) *log = \"groupSyncWrite addparam failed\";\n      return false;\n    }\n  }\n\n  sdk_error.dxl_comm_result = syncWriteHandler_[index].groupSyncWrite->txPacket();\n  if (sdk_error.dxl_comm_result != COMM_SUCCESS)\n  {\n    if (log != NULL) *log = packetHandler_->getTxRxResult(sdk_error.dxl_comm_result);\n    return false;\n  }\n\n  syncWriteHandler_[index].groupSyncWrite->clearParam();\n\n  if (log != NULL) *log = \"[DynamixelDriver] Succeeded to sync write!\";\n  return true;\n}\n\nbool DynamixelDriver::addSyncReadHandler(uint16_t address, uint16_t length, const char **log)\n{\n  if (sync_read_handler_cnt_ > (MAX_HANDLER_NUM-1))\n  {\n    if (log != NULL) *log = \"[DynamixelDriver] Too many sync read handler are added (MAX = 5)\";\n    return false;\n  }\n\n  syncReadHandler_[sync_read_handler_cnt_].control_item = NULL;\n\n  syncReadHandler_[sync_read_handler_cnt_].groupSyncRead = new dynamixel::GroupSyncRead(portHandler_,\n                                                                                          packetHandler_,\n                                                                                          address,\n                                                                                          length);\n\n  sync_read_handler_cnt_++;\n\n  if (log != NULL) *log = \"[DynamixelDriver] Succeeded to add sync read handler\";\n  return true;\n}\n\nbool DynamixelDriver::addSyncReadHandler(uint8_t id, const char *item_name, const char **log)\n{\n  const ControlItem *control_item;\n\n  uint8_t factor = getTool(id, log);\n  if (factor == 0xff) return false; \n\n  control_item = tools_[factor].getControlItem(item_name, log);\n  if (control_item == NULL) return false;\n\n  if (sync_read_handler_cnt_ > (MAX_HANDLER_NUM-1))\n  {\n    if (log != NULL) *log = \"[DynamixelDriver] Too many sync read handler are added (MAX = 5)\";\n    return false;\n  }\n\n  syncReadHandler_[sync_read_handler_cnt_].control_item = control_item;\n\n  syncReadHandler_[sync_read_handler_cnt_].groupSyncRead = new dynamixel::GroupSyncRead(portHandler_,\n                                                                                          packetHandler_,\n                                                                                          control_item->address,\n                                                                                          control_item->data_length);\n\n  sync_read_handler_cnt_++;\n\n  if (log != NULL) *log = \"[DynamixelDriver] Succeeded to add sync read handler\";\n  return true;       \n}\n\nbool DynamixelDriver::syncRead(uint8_t index, const char **log)\n{\n  ErrorFromSDK sdk_error = {0, false, false, 0};\n\n  syncReadHandler_[index].groupSyncRead->clearParam();\n  for (int i = 0; i < tools_cnt_; i++)\n  {\n    for (int j = 0; j < tools_[i].getDynamixelCount(); j++)\n    {\n      sdk_error.dxl_addparam_result = syncReadHandler_[index].groupSyncRead->addParam(tools_[i].getID()[j]);\n      if (sdk_error.dxl_addparam_result != true)\n      {\n        if (log != NULL) *log = \"groupSyncWrite addparam failed\";\n        return false;\n      }\n    }\n  }\n\n  sdk_error.dxl_comm_result = syncReadHandler_[index].groupSyncRead->txRxPacket();\n  if (sdk_error.dxl_comm_result != COMM_SUCCESS)\n  {\n    if (log != NULL) *log = packetHandler_->getTxRxResult(sdk_error.dxl_comm_result);\n    return false;\n  }\n\n  if (log != NULL) *log = \"[DynamixelDriver] Succeeded to sync read!\";\n  return true;\n}\n\nbool DynamixelDriver::syncRead(uint8_t index, uint8_t *id, uint8_t id_num, const char **log)\n{\n  ErrorFromSDK sdk_error = {0, false, false, 0};\n\n  syncReadHandler_[index].groupSyncRead->clearParam();\n  for (int i = 0; i < id_num; i++)\n  {\n    sdk_error.dxl_addparam_result = syncReadHandler_[index].groupSyncRead->addParam(id[i]);\n    if (sdk_error.dxl_addparam_result != true)\n    {\n      if (log != NULL) *log = \"groupSyncWrite addparam failed\";\n      return false;\n    }\n  }\n\n  sdk_error.dxl_comm_result = syncReadHandler_[index].groupSyncRead->txRxPacket();\n  if (sdk_error.dxl_comm_result != COMM_SUCCESS)\n  {\n    if (log != NULL) *log = packetHandler_->getTxRxResult(sdk_error.dxl_comm_result);\n    return false;\n  }\n\n  if (log != NULL) *log = \"[DynamixelDriver] Succeeded to sync read!\";\n  return true;\n}\n\nbool DynamixelDriver::getSyncReadData(uint8_t index, int32_t *data, const char **log)\n{\n  ErrorFromSDK sdk_error = {0, false, false, 0};\n\n  for (int i = 0; i < tools_cnt_; i++)\n  {\n    for (int j = 0; j < tools_[i].getDynamixelCount(); j++)\n    {\n      sdk_error.dxl_getdata_result = syncReadHandler_[index].groupSyncRead->isAvailable(tools_[i].getID()[j], \n                                                                                        syncReadHandler_[index].control_item->address, \n                                                                                        syncReadHandler_[index].control_item->data_length);\n      if (sdk_error.dxl_getdata_result != true)\n      {\n        if (log != NULL) *log = \"groupSyncRead getdata failed\";\n        return false;\n      }\n      else\n      {\n        data[i+j] = syncReadHandler_[index].groupSyncRead->getData(tools_[i].getID()[j], \n                                                                    syncReadHandler_[index].control_item->address, \n                                                                    syncReadHandler_[index].control_item->data_length);\n      }\n    }\n  }\n\n  if (log != NULL) *log = \"[DynamixelDriver] Succeeded to get sync read data!\";\n  return true;\n}\n\nbool DynamixelDriver::getSyncReadData(uint8_t index, uint8_t *id, uint8_t id_num, int32_t *data, const char **log)\n{\n  ErrorFromSDK sdk_error = {0, false, false, 0};\n\n  for (int i = 0; i < id_num; i++)\n  {\n    sdk_error.dxl_getdata_result = syncReadHandler_[index].groupSyncRead->isAvailable(id[i], \n                                                                                      syncReadHandler_[index].control_item->address, \n                                                                                      syncReadHandler_[index].control_item->data_length);\n    if (sdk_error.dxl_getdata_result != true)\n    {\n      if (log != NULL) *log = \"groupSyncRead getdata failed\";\n      return false;\n    }\n    else\n    {\n      data[i] = syncReadHandler_[index].groupSyncRead->getData(id[i], \n                                                                syncReadHandler_[index].control_item->address, \n                                                                syncReadHandler_[index].control_item->data_length);\n    }\n  }\n\n  if (log != NULL) *log = \"[DynamixelDriver] Succeeded to get sync read data!\";\n  return true;\n}\n\nbool DynamixelDriver::getSyncReadData(uint8_t index, uint8_t *id, uint8_t id_num, uint16_t address, uint16_t length, int32_t *data, const char **log)\n{\n  ErrorFromSDK sdk_error = {0, false, false, 0};\n  \n  for (int i = 0; i < id_num; i++)\n  {\n    sdk_error.dxl_getdata_result = syncReadHandler_[index].groupSyncRead->isAvailable(id[i], \n                                                                                      address, \n                                                                                      length);\n    if (sdk_error.dxl_getdata_result != true)\n    {\n      if (log != NULL) *log = \"groupSyncRead getdata failed\";\n      return false;\n    }\n    else\n    {\n      data[i] = syncReadHandler_[index].groupSyncRead->getData(id[i], \n                                                              address, \n                                                              length);\n    }\n  }\n\n  if (log != NULL) *log = \"[DynamixelDriver] Succeeded to get sync read data!\";\n  return true;\n}\n\nbool DynamixelDriver::initBulkWrite(const char **log)\n{\n  if (portHandler_ == NULL)\n  {\n    if (log != NULL) *log = \"[DynamixelDriver] Failed to load portHandler!\";\n  }\n  else if (packetHandler_ == NULL)\n  {\n    if (log != NULL) *log = \"[DynamixelDriver] Failed to load packetHandler!\";\n  }\n  else\n  {\n    groupBulkWrite_ = new dynamixel::GroupBulkWrite(portHandler_, packetHandler_);\n\n    if (log != NULL) *log = \"[DynamixelDriver] Succeeded to init groupBulkWrite!\";\n    return true;\n  }\n\n  return false;\n}\n\nbool DynamixelDriver::addBulkWriteParam(uint8_t id, uint16_t address, uint16_t length, int32_t data, const char **log)\n{\n  ErrorFromSDK sdk_error = {0, false, false, 0};\n\n  uint8_t parameter[4] = {0, 0, 0, 0};\n\n  getParam(data, parameter);\n  sdk_error.dxl_addparam_result = groupBulkWrite_->addParam(id, \n                                                            address, \n                                                            length, \n                                                            parameter);\n  if (sdk_error.dxl_addparam_result != true)\n  {\n    if (log != NULL) *log = \"groupBulkWrite addparam failed\";\n    return false;\n  }\n\n  if (log != NULL) *log = \"[DynamixelDriver] Succeeded to add param for bulk write!\";\n  return true;\n}\n\nbool DynamixelDriver::addBulkWriteParam(uint8_t id, const char *item_name, int32_t data, const char **log)\n{\n  ErrorFromSDK sdk_error = {0, false, false, 0};\n\n  uint8_t parameter[4] = {0, 0, 0, 0};\n\n  const ControlItem *control_item;\n\n  uint8_t factor = getTool(id, log);\n  if (factor == 0xff) return false; \n\n  control_item = tools_[factor].getControlItem(item_name, log);\n  if (control_item == NULL) return false;\n\n  getParam(data, parameter);\n  sdk_error.dxl_addparam_result = groupBulkWrite_->addParam(id, \n                                                            control_item->address, \n                                                            control_item->data_length, \n                                                            parameter);\n  if (sdk_error.dxl_addparam_result != true)\n  {\n    if (log != NULL) *log = \"groupBulkWrite addparam failed\";\n    return false;\n  }\n\n  if (log != NULL) *log = \"[DynamixelDriver] Succeeded to add param for bulk write!\";\n  return true;\n}\n\nbool DynamixelDriver::bulkWrite(const char **log)\n{\n  ErrorFromSDK sdk_error = {0, false, false, 0};\n\n  sdk_error.dxl_comm_result = groupBulkWrite_->txPacket();\n  if (sdk_error.dxl_comm_result != COMM_SUCCESS)\n  {\n    if (log != NULL) *log = packetHandler_->getTxRxResult(sdk_error.dxl_comm_result);\n    return false;\n  }\n\n  groupBulkWrite_->clearParam();\n  if (log != NULL) *log = \"[DynamixelDriver] Succeeded to bulk write!\";\n\n  return true;\n}\n\nbool DynamixelDriver::initBulkRead(const char **log)\n{\n  if (portHandler_ == NULL)\n  {\n    if (log != NULL) *log = \"[DynamixelDriver] Failed to load portHandler!\";\n  }\n  else if (packetHandler_ == NULL)\n  {\n    if (log != NULL) *log = \"[DynamixelDriver] Failed to load packetHandler!\";\n  }\n  else\n  {\n    groupBulkRead_ = new dynamixel::GroupBulkRead(portHandler_, packetHandler_);\n\n    if (log != NULL) *log = \"[DynamixelDriver] Succeeded to init groupBulkRead!\";\n\n    return true;\n  }\n\n  return false;\n}\n\nbool DynamixelDriver::addBulkReadParam(uint8_t id, uint16_t address, uint16_t length, const char **log)\n{\n  ErrorFromSDK sdk_error = {0, false, false, 0};\n\n  sdk_error.dxl_addparam_result = groupBulkRead_->addParam(id, \n                                                           address, \n                                                           length);\n  if (sdk_error.dxl_addparam_result != true)\n  {\n    if (log != NULL) *log = \"grouBulkRead addparam failed\";\n    return false;\n  }\n\n  if (bulk_read_parameter_cnt_ < (MAX_BULK_PARAMETER-1))\n  {\n    bulk_read_param_[bulk_read_parameter_cnt_].id = id;\n    bulk_read_param_[bulk_read_parameter_cnt_].address = address;\n    bulk_read_param_[bulk_read_parameter_cnt_].data_length = length;\n    bulk_read_parameter_cnt_++;\n  }\n  else\n  {\n    if (log != NULL) *log = \"[DynamixelDriver] Too many bulk parameter are added (default buffer size is 21)\";\n    return false;\n  }\n\n  if (log != NULL) *log = \"[DynamixelDriver] Succeeded to add param for bulk read!\";\n  return true;\n}\n\nbool DynamixelDriver::addBulkReadParam(uint8_t id, const char *item_name, const char **log)\n{\n  ErrorFromSDK sdk_error = {0, false, false, 0};\n\n  const ControlItem *control_item;\n\n  uint8_t factor = getTool(id, log);\n  if (factor == 0xff) return false; \n\n  control_item = tools_[factor].getControlItem(item_name, log);\n  if (control_item == NULL) return false;\n\n  sdk_error.dxl_addparam_result = groupBulkRead_->addParam(id, \n                                                          control_item->address, \n                                                          control_item->data_length);\n  if (sdk_error.dxl_addparam_result != true)\n  {\n    if (log != NULL) *log = \"grouBulkRead addparam failed\";\n    return false;\n  }\n\n  if (bulk_read_parameter_cnt_ < (MAX_BULK_PARAMETER-1))\n  {\n    bulk_read_param_[bulk_read_parameter_cnt_].id = id;\n    bulk_read_param_[bulk_read_parameter_cnt_].address = control_item->address;\n    bulk_read_param_[bulk_read_parameter_cnt_].data_length = control_item->data_length;\n    bulk_read_parameter_cnt_++;\n  }\n  else\n  {\n    if (log != NULL) *log = \"[DynamixelDriver] Too many bulk parameter are added (default buffer size is 21)\";\n    return false;\n  }\n\n  if (log != NULL) *log = \"[DynamixelDriver] Succeeded to add param for bulk read!\";\n  return true;\n}\n\nbool DynamixelDriver::bulkRead(const char **log)\n{\n  ErrorFromSDK sdk_error = {0, false, false, 0};\n  \n  sdk_error.dxl_comm_result = groupBulkRead_->txRxPacket();\n  if (sdk_error.dxl_comm_result != COMM_SUCCESS) \n  {\n    if (log != NULL) *log = packetHandler_->getTxRxResult(sdk_error.dxl_comm_result);\n    return false;\n  }\n\n  if (log != NULL) *log = \"[DynamixelDriver] Succeeded to bulk read!\";\n  return true;\n}\n\nbool DynamixelDriver::getBulkReadData(int32_t *data, const char **log)\n{\n  ErrorFromSDK sdk_error = {0, false, false, 0};\n\n  for (int i = 0; i < bulk_read_parameter_cnt_; i++)\n  {\n    sdk_error.dxl_getdata_result = groupBulkRead_->isAvailable(bulk_read_param_[i].id, \n                                                              bulk_read_param_[i].address, \n                                                              bulk_read_param_[i].data_length);\n    if (sdk_error.dxl_getdata_result != true)\n    {\n      if (log != NULL) *log = \"groupBulkRead getdata failed\";\n      return false;\n    }\n    else\n    {\n      data[i] = groupBulkRead_->getData(bulk_read_param_[i].id, \n                                        bulk_read_param_[i].address, \n                                        bulk_read_param_[i].data_length);\n    }\n  }\n\n  if (log != NULL) *log = \"[DynamixelDriver] Succeeded to get bulk read data!\";\n  return true;\n}\n\nbool DynamixelDriver::getBulkReadData(uint8_t *id, uint8_t id_num, uint16_t *address, uint16_t *length, int32_t *data, const char **log)\n{\n  ErrorFromSDK sdk_error = {0, false, false, 0};\n\n  for (int i = 0; i < id_num; i++)\n  {\n    sdk_error.dxl_getdata_result = groupBulkRead_->isAvailable(id[i], \n                                                              address[i], \n                                                              length[i]);\n    if (sdk_error.dxl_getdata_result != true)\n    {\n      if (log != NULL) *log = \"groupBulkRead getdata failed\";\n      return false;\n    }\n    else\n    {\n      data[i] = groupBulkRead_->getData(id[i], \n                                        address[i], \n                                        length[i]);\n    }\n  }\n\n  if (log != NULL) *log = \"[DynamixelDriver] Succeeded to get bulk read data!\";\n  return true;\n}\n\nbool DynamixelDriver::clearBulkReadParam(void)\n{\n  groupBulkRead_->clearParam();\n  bulk_read_parameter_cnt_ = 0;\n\n  return true;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelWorkbench/src/dynamixel_workbench_toolbox/dynamixel_item.cpp",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Taehun Lim (Darby), Ryan Shim */\n\n#include \"../../include/dynamixel_workbench_toolbox/dynamixel_item.h\"\n\n//=========================================================\n// Servo register definitions\n//=========================================================\n\n//_________________________________________________________\n\nstatic const char s_Acceleration_Limit[] = \"Acceleration_Limit\";\nstatic const char s_Alarm_LED[] = \"Alarm_LED\";\nstatic const char s_Baud_Rate[] = \"Baud_Rate\";\nstatic const char s_Bus_Watchdog[] = \"Bus_Watchdog\";\nstatic const char s_CCW_Angle_Limit[] = \"CCW_Angle_Limit\";\nstatic const char s_CCW_Compliance_Margin[] = \"CCW_Compliance_Margin\";\nstatic const char s_CCW_Compliance_Slope[] = \"CCW_Compliance_Slope\";\nstatic const char s_Control_Mode[] = \"Control_Mode\";\nstatic const char s_Current[] = \"Current\";\nstatic const char s_Current_Limit[] = \"Current_Limit\";\nstatic const char s_CW_Angle_Limit[] = \"CW_Angle_Limit\";\nstatic const char s_CW_Compliance_Margin[] = \"CW_Compliance_Margin\";\nstatic const char s_CW_Compliance_Slope[] = \"CW_Compliance_Slope\";\nstatic const char s_D_gain[] = \"D_gain\";\nstatic const char s_Drive_Mode[] = \"Drive_Mode\";\nstatic const char s_External_Port_Mode_1[] = \"External_Port_Mode_1\";\nstatic const char s_External_Port_Mode_2[] = \"External_Port_Mode_2\";\nstatic const char s_External_Port_Mode_3[] = \"External_Port_Mode_3\";\nstatic const char s_External_Port_Mode_4[] = \"External_Port_Mode_4\";\nstatic const char s_Feedforward_1st_Gain[] = \"Feedforward_1st_Gain\";\nstatic const char s_Feedforward_2nd_Gain[] = \"Feedforward_2nd_Gain\";\nstatic const char s_Firmware_Version[] = \"Firmware_Version\";\nstatic const char s_Goal_Acceleration[] = \"Goal_Acceleration\";\nstatic const char s_Goal_Current[] = \"Goal_Current\";\nstatic const char s_Goal_Position[] = \"Goal_Position\";\nstatic const char s_Goal_PWM[] = \"Goal_PWM\";\nstatic const char s_Goal_Torque[] = \"Goal_Torque\";\nstatic const char s_Goal_Velocity[] = \"Goal_Velocity\";\nstatic const char s_Hardware_Error_Status[] = \"Hardware_Error_Status\";\nstatic const char s_Homing_Offset[] = \"Homing_Offset\";\nstatic const char s_I_gain[] = \"I_gain\";\nstatic const char s_ID[] = \"ID\";\nstatic const char s_LED[] = \"LED\";\nstatic const char s_LED_BLUE[] = \"LED_BLUE\";\nstatic const char s_LED_GREEN[] = \"LED_GREEN\";\nstatic const char s_LED_RED[] = \"LED_RED\";\nstatic const char s_Lock[] = \"Lock\";\nstatic const char s_Max_Position_Limit[] = \"Max_Position_Limit\";\nstatic const char s_Max_Torque[] = \"Max_Torque\";\nstatic const char s_Max_Voltage_Limit[] = \"Max_Voltage_Limit\";\nstatic const char s_Min_Position_Limit[] = \"Min_Position_Limit\";\nstatic const char s_Min_Voltage_Limit[] = \"Min_Voltage_Limit\";\nstatic const char s_Model_Number[] = \"Model_Number\";\nstatic const char s_Moving[] = \"Moving\";\nstatic const char s_Moving_Speed[] = \"Moving_Speed\";\nstatic const char s_Moving_Status[] = \"Moving_Status\";\nstatic const char s_Moving_Threshold[] = \"Moving_Threshold\";\nstatic const char s_Multi_Turn_Offset[] = \"Multi_Turn_Offset\";\nstatic const char s_Operating_Mode[] = \"Operating_Mode\";\nstatic const char s_P_gain[] = \"P_gain\";\nstatic const char s_Position_D_Gain[] = \"Position_D_Gain\";\nstatic const char s_Position_I_Gain[] = \"Position_I_Gain\";\nstatic const char s_Position_P_Gain[] = \"Position_P_Gain\";\nstatic const char s_Position_Trajectory[] = \"Position_Trajectory\";\nstatic const char s_Present_Current[] = \"Present_Current\";\nstatic const char s_Present_Input[] = \"Present_Input\";\nstatic const char s_Present_Input_Voltage[] = \"Present_Input_Voltage\";\nstatic const char s_Present_Load[] = \"Present_Load\";\nstatic const char s_Present_Position[] = \"Present_Position\";\nstatic const char s_Present_PWM[] = \"Present_PWM\";\nstatic const char s_Present_Speed[] = \"Present_Speed\";\nstatic const char s_Present_Temperature[] = \"Present_Temperature\";\nstatic const char s_Present_Velocity[] = \"Present_Velocity\";\nstatic const char s_Present_Voltage[] = \"Present_Voltage\";\nstatic const char s_Profile_Acceleration[] = \"Profile_Acceleration\";\nstatic const char s_Profile_Velocity[] = \"Profile_Velocity\";\nstatic const char s_Protocol_Version[] = \"Protocol_Version\";\nstatic const char s_Punch[] = \"Punch\";\nstatic const char s_PWM_Limit[] = \"PWM_Limit\";\nstatic const char s_Realtime_Tick[] = \"Realtime_Tick\";\nstatic const char s_Registered[] = \"Registered\";\nstatic const char s_Registered_Instruction[] = \"Registered_Instruction\";\nstatic const char s_Resolution_Divider[] = \"Resolution_Divider\";\nstatic const char s_Return_Delay_Time[] = \"Return_Delay_Time\";\nstatic const char s_Secondary_ID[] = \"Secondary_ID\";\nstatic const char s_Sensored_Current[] = \"Sensored_Current\";\nstatic const char s_Shutdown[] = \"Shutdown\";\nstatic const char s_Status_Return_Level[] = \"Status_Return_Level\";\nstatic const char s_Temperature_Limit[] = \"Temperature_Limit\";\nstatic const char s_Torque_Control_Mode_Enable[] = \"Torque_Control_Mode_Enable\";\nstatic const char s_Torque_Enable[] = \"Torque_Enable\";\nstatic const char s_Torque_Limit[] = \"Torque_Limit\";\nstatic const char s_Velocity_I_Gain[] = \"Velocity_I_Gain\";\nstatic const char s_Velocity_Limit[] = \"Velocity_Limit\";\nstatic const char s_Velocity_P_Gain[] = \"Velocity_P_Gain\";\nstatic const char s_Velocity_Trajectory[] = \"Velocity_Trajectory\";\n\n//_________________________________________________________\n\n//---------------------------------------------------------\n// AX servos - (num == AX_12A || num == AX_12W || num == AX_18A)\n//---------------------------------------------------------\nstatic const ControlItem items_AX[]{\n    {s_Model_Number, 0, sizeof(s_Model_Number) - 1, 2},\n    {s_Firmware_Version, 2, sizeof(s_Firmware_Version) - 1, 1},\n    {s_ID, 3, sizeof(s_ID) - 1, 1},\n    {s_Baud_Rate, 4, sizeof(s_Baud_Rate) - 1, 1},\n    {s_Return_Delay_Time, 5, sizeof(s_Return_Delay_Time) - 1, 1},\n    {s_CW_Angle_Limit, 6, sizeof(s_CW_Angle_Limit) - 1, 2},\n    {s_CCW_Angle_Limit, 8, sizeof(s_CCW_Angle_Limit) - 1, 2},\n    {s_Temperature_Limit, 11, sizeof(s_Temperature_Limit) - 1, 1},\n    {s_Min_Voltage_Limit, 12, sizeof(s_Min_Voltage_Limit) - 1, 1},\n    {s_Max_Voltage_Limit, 13, sizeof(s_Max_Voltage_Limit) - 1, 1},\n    {s_Max_Torque, 14, sizeof(s_Max_Torque) - 1, 2},\n    {s_Status_Return_Level, 16, sizeof(s_Status_Return_Level) - 1, 1},\n    {s_Alarm_LED, 17, sizeof(s_Alarm_LED) - 1, 1},\n    {s_Shutdown, 18, sizeof(s_Shutdown) - 1, 1},\n\n    {s_Torque_Enable, 24, sizeof(s_Torque_Enable) - 1, 1},\n    {s_LED, 25, sizeof(s_LED) - 1, 1},\n    {s_CW_Compliance_Margin, 26, sizeof(s_CW_Compliance_Margin) - 1, 1},\n    {s_CCW_Compliance_Margin, 27, sizeof(s_CCW_Compliance_Margin) - 1, 1},\n    {s_CW_Compliance_Slope, 28, sizeof(s_CW_Compliance_Slope) - 1, 1},\n    {s_CCW_Compliance_Slope, 29, sizeof(s_CCW_Compliance_Slope) - 1, 1},\n    {s_Goal_Position, 30, sizeof(s_Goal_Position) - 1, 2},\n    {s_Moving_Speed, 32, sizeof(s_Moving_Speed) - 1, 2},\n    {s_Torque_Limit, 34, sizeof(s_Torque_Limit) - 1, 2},\n    {s_Present_Position, 36, sizeof(s_Present_Position) - 1, 2},\n    {s_Present_Speed, 38, sizeof(s_Present_Speed) - 1, 2},\n    {s_Present_Load, 40, sizeof(s_Present_Load) - 1, 2},\n    {s_Present_Voltage, 42, sizeof(s_Present_Voltage) - 1, 1},\n    {s_Present_Temperature, 43, sizeof(s_Present_Temperature) - 1, 1},\n    {s_Registered, 44, sizeof(s_Registered) - 1, 1},\n    {s_Moving, 46, sizeof(s_Moving) - 1, 1},\n    {s_Lock, 47, sizeof(s_Lock) - 1, 1},\n    {s_Punch, 48, sizeof(s_Punch) - 1, 2}};\n#define COUNT_AX_ITEMS (sizeof(items_AX) / sizeof(items_AX[0]))\n\nstatic const ModelInfo info_AX = {0.11,\n                                  0,\n                                  512,\n                                  1024,\n                                  -2.61799, \n                                  2.61799};\n\n//---------------------------------------------------------\n// RX servos - (num == RX_10 || num == RX_24F || num == RX_28 || num == RX_64)\n//---------------------------------------------------------\nstatic const ControlItem items_RX[]{\n    {s_Model_Number, 0, sizeof(s_Model_Number) - 1, 2},\n    {s_Firmware_Version, 2, sizeof(s_Firmware_Version) - 1, 1},\n    {s_ID, 3, sizeof(s_ID) - 1, 1},\n    {s_Baud_Rate, 4, sizeof(s_Baud_Rate) - 1, 1},\n    {s_Return_Delay_Time, 5, sizeof(s_Return_Delay_Time) - 1, 1},\n    {s_CW_Angle_Limit, 6, sizeof(s_CW_Angle_Limit) - 1, 2},\n    {s_CCW_Angle_Limit, 8, sizeof(s_CCW_Angle_Limit) - 1, 2},\n    {s_Temperature_Limit, 11, sizeof(s_Temperature_Limit) - 1, 1},\n    {s_Min_Voltage_Limit, 12, sizeof(s_Min_Voltage_Limit) - 1, 1},\n    {s_Max_Voltage_Limit, 13, sizeof(s_Max_Voltage_Limit) - 1, 1},\n    {s_Max_Torque, 14, sizeof(s_Max_Torque) - 1, 2},\n    {s_Status_Return_Level, 16, sizeof(s_Status_Return_Level) - 1, 1},\n    {s_Alarm_LED, 17, sizeof(s_Alarm_LED) - 1, 1},\n    {s_Shutdown, 18, sizeof(s_Shutdown) - 1, 1},\n\n    {s_Torque_Enable, 24, sizeof(s_Torque_Enable) - 1, 1},\n    {s_LED, 25, sizeof(s_LED) - 1, 1},\n    {s_CW_Compliance_Margin, 26, sizeof(s_CW_Compliance_Margin) - 1, 1},\n    {s_CCW_Compliance_Margin, 27, sizeof(s_CCW_Compliance_Margin) - 1, 1},\n    {s_CW_Compliance_Slope, 28, sizeof(s_CW_Compliance_Slope) - 1, 1},\n    {s_CCW_Compliance_Slope, 29, sizeof(s_CCW_Compliance_Slope) - 1, 1},\n    {s_Goal_Position, 30, sizeof(s_Goal_Position) - 1, 2},\n    {s_Moving_Speed, 32, sizeof(s_Moving_Speed) - 1, 2},\n    {s_Torque_Limit, 34, sizeof(s_Torque_Limit) - 1, 2},\n    {s_Present_Position, 36, sizeof(s_Present_Position) - 1, 2},\n    {s_Present_Speed, 38, sizeof(s_Present_Speed) - 1, 2},\n    {s_Present_Load, 40, sizeof(s_Present_Load) - 1, 2},\n    {s_Present_Voltage, 42, sizeof(s_Present_Voltage) - 1, 1},\n    {s_Present_Temperature, 43, sizeof(s_Present_Temperature) - 1, 1},\n    {s_Registered, 44, sizeof(s_Registered) - 1, 1},\n    {s_Moving, 46, sizeof(s_Moving) - 1, 1},\n    {s_Lock, 47, sizeof(s_Lock) - 1, 1},\n    {s_Punch, 48, sizeof(s_Punch) - 1, 2}};\n\n#define COUNT_RX_ITEMS (sizeof(items_RX) / sizeof(items_RX[0]))\n\nstatic const ModelInfo info_RX = {0.11,\n                                  0,\n                                  512,\n                                  1024,\n                                  -2.61799, \n                                  2.61799};\n\n//---------------------------------------------------------\n// EX servos - (num == EX_106)\n//---------------------------------------------------------\nstatic const ControlItem items_EX[]{\n    {s_Model_Number, 0, sizeof(s_Model_Number) - 1, 2},\n    {s_Firmware_Version, 2, sizeof(s_Firmware_Version) - 1, 1},\n    {s_ID, 3, sizeof(s_ID) - 1, 1},\n    {s_Baud_Rate, 4, sizeof(s_Baud_Rate) - 1, 1},\n    {s_Return_Delay_Time, 5, sizeof(s_Return_Delay_Time) - 1, 1},\n    {s_CW_Angle_Limit, 6, sizeof(s_CW_Angle_Limit) - 1, 2},\n    {s_CCW_Angle_Limit, 8, sizeof(s_CCW_Angle_Limit) - 1, 2},\n    {s_Drive_Mode, 10, sizeof(s_Drive_Mode) - 1, 1},\n    {s_Temperature_Limit, 11, sizeof(s_Temperature_Limit) - 1, 1},\n    {s_Min_Voltage_Limit, 12, sizeof(s_Min_Voltage_Limit) - 1, 1},\n    {s_Max_Voltage_Limit, 13, sizeof(s_Max_Voltage_Limit) - 1, 1},\n    {s_Max_Torque, 14, sizeof(s_Max_Torque) - 1, 2},\n    {s_Status_Return_Level, 16, sizeof(s_Status_Return_Level) - 1, 1},\n    {s_Alarm_LED, 17, sizeof(s_Alarm_LED) - 1, 1},\n    {s_Shutdown, 18, sizeof(s_Shutdown) - 1, 1},\n\n    {s_Torque_Enable, 24, sizeof(s_Torque_Enable) - 1, 1},\n    {s_LED, 25, sizeof(s_LED) - 1, 1},\n    {s_CW_Compliance_Margin, 26, sizeof(s_CW_Compliance_Margin) - 1, 1},\n    {s_CCW_Compliance_Margin, 27, sizeof(s_CCW_Compliance_Margin) - 1, 1},\n    {s_CW_Compliance_Slope, 28, sizeof(s_CW_Compliance_Slope) - 1, 1},\n    {s_CCW_Compliance_Slope, 29, sizeof(s_CCW_Compliance_Slope) - 1, 1},\n    {s_Goal_Position, 30, sizeof(s_Goal_Position) - 1, 2},\n    {s_Moving_Speed, 34, sizeof(s_Moving_Speed) - 1, 2},\n    {s_Torque_Limit, 35, sizeof(s_Torque_Limit) - 1, 2},\n    {s_Present_Position, 36, sizeof(s_Present_Position) - 1, 2},\n    {s_Present_Speed, 38, sizeof(s_Present_Speed) - 1, 2},\n    {s_Present_Load, 40, sizeof(s_Present_Load) - 1, 2},\n    {s_Present_Voltage, 42, sizeof(s_Present_Voltage) - 1, 1},\n    {s_Present_Temperature, 43, sizeof(s_Present_Temperature) - 1, 1},\n    {s_Registered, 44, sizeof(s_Registered) - 1, 1},\n    {s_Moving, 46, sizeof(s_Moving) - 1, 1},\n    {s_Lock, 47, sizeof(s_Lock) - 1, 1},\n    {s_Punch, 48, sizeof(s_Punch) - 1, 2},\n    {s_Sensored_Current, 56, sizeof(s_Sensored_Current) - 1, 2}};\n\n#define COUNT_EX_ITEMS (sizeof(items_EX) / sizeof(items_EX[0]))\n\nstatic const ModelInfo info_EX = {0.11,\n                                  0,\n                                  2048,\n                                  4096,\n                                  -2.18969008, \n                                  2.18969008};\n\n//---------------------------------------------------------\n// MX Protocol 1 servos - (num == MX_12W || num == MX_28)\n//---------------------------------------------------------\nstatic const ControlItem items_MX[]{\n    {s_Model_Number, 0, sizeof(s_Model_Number) - 1, 2},\n    {s_Firmware_Version, 2, sizeof(s_Firmware_Version) - 1, 1},\n    {s_ID, 3, sizeof(s_ID) - 1, 1},\n    {s_Baud_Rate, 4, sizeof(s_Baud_Rate) - 1, 1},\n    {s_Return_Delay_Time, 5, sizeof(s_Return_Delay_Time) - 1, 1},\n    {s_CW_Angle_Limit, 6, sizeof(s_CW_Angle_Limit) - 1, 2},\n    {s_CCW_Angle_Limit, 8, sizeof(s_CCW_Angle_Limit) - 1, 2},\n    {s_Temperature_Limit, 11, sizeof(s_Temperature_Limit) - 1, 1},\n    {s_Min_Voltage_Limit, 12, sizeof(s_Min_Voltage_Limit) - 1, 1},\n    {s_Max_Voltage_Limit, 13, sizeof(s_Max_Voltage_Limit) - 1, 1},\n    {s_Max_Torque, 14, sizeof(s_Max_Torque) - 1, 2},\n    {s_Status_Return_Level, 16, sizeof(s_Status_Return_Level) - 1, 1},\n    {s_Alarm_LED, 17, sizeof(s_Alarm_LED) - 1, 1},\n    {s_Shutdown, 18, sizeof(s_Shutdown) - 1, 1},\n    {s_Multi_Turn_Offset, 20, sizeof(s_Multi_Turn_Offset) - 1, 2},\n    {s_Resolution_Divider, 22, sizeof(s_Resolution_Divider) - 1, 1},\n\n    {s_Torque_Enable, 24, sizeof(s_Torque_Enable) - 1, 1},\n    {s_LED, 25, sizeof(s_LED) - 1, 1},\n    {s_D_gain, 26, sizeof(s_D_gain) - 1, 1},\n    {s_I_gain, 27, sizeof(s_I_gain) - 1, 1},\n    {s_P_gain, 28, sizeof(s_P_gain) - 1, 1},\n    {s_Goal_Position, 30, sizeof(s_Goal_Position) - 1, 2},\n    {s_Moving_Speed, 32, sizeof(s_Moving_Speed) - 1, 2},\n    {s_Torque_Limit, 34, sizeof(s_Torque_Limit) - 1, 2},\n    {s_Present_Position, 36, sizeof(s_Present_Position) - 1, 2},\n    {s_Present_Speed, 38, sizeof(s_Present_Speed) - 1, 2},\n    {s_Present_Load, 40, sizeof(s_Present_Load) - 1, 2},\n    {s_Present_Voltage, 42, sizeof(s_Present_Voltage) - 1, 1},\n    {s_Present_Temperature, 43, sizeof(s_Present_Temperature) - 1, 1},\n    {s_Registered, 44, sizeof(s_Registered) - 1, 1},\n    {s_Moving, 46, sizeof(s_Moving) - 1, 1},\n    {s_Lock, 47, sizeof(s_Lock) - 1, 1},\n    {s_Punch, 48, sizeof(s_Punch) - 1, 2},\n    {s_Goal_Acceleration, 73, sizeof(s_Goal_Acceleration) - 1, 1}};\n\n#define COUNT_MX_ITEMS (sizeof(items_MX) / sizeof(items_MX[0]))\n\nstatic const ModelInfo info_MX = {0.11,\n                                  0,\n                                  2048,\n                                  4096,\n                                  -3.14159265, \n                                  3.14159265};\n\n//---------------------------------------------------------\n// MX Protocol 2 servos - (num == MX_28_2)\n//---------------------------------------------------------\nstatic const ControlItem items_MX2[]{\n    {s_Model_Number, 0, sizeof(s_Model_Number) - 1, 2},\n    {s_Firmware_Version, 6, sizeof(s_Firmware_Version) - 1, 1},\n    {s_ID, 7, sizeof(s_ID) - 1, 1},\n    {s_Baud_Rate, 8, sizeof(s_Baud_Rate) - 1, 1},\n    {s_Return_Delay_Time, 9, sizeof(s_Return_Delay_Time) - 1, 1},\n    {s_Drive_Mode, 10, sizeof(s_Drive_Mode) - 1, 1},\n    {s_Operating_Mode, 11, sizeof(s_Operating_Mode) - 1, 1},\n    {s_Secondary_ID, 12, sizeof(s_Secondary_ID) - 1, 1},\n    {s_Protocol_Version, 13, sizeof(s_Protocol_Version) - 1, 1},\n    {s_Homing_Offset, 20, sizeof(s_Homing_Offset) - 1, 4},\n    {s_Moving_Threshold, 24, sizeof(s_Moving_Threshold) - 1, 4},\n    {s_Temperature_Limit, 31, sizeof(s_Temperature_Limit) - 1, 1},\n    {s_Max_Voltage_Limit, 32, sizeof(s_Max_Voltage_Limit) - 1, 2},\n    {s_Min_Voltage_Limit, 34, sizeof(s_Min_Voltage_Limit) - 1, 2},\n    {s_PWM_Limit, 36, sizeof(s_PWM_Limit) - 1, 2},\n    {s_Acceleration_Limit, 40, sizeof(s_Acceleration_Limit) - 1, 4},\n    {s_Velocity_Limit, 44, sizeof(s_Velocity_Limit) - 1, 4},\n    {s_Max_Position_Limit, 48, sizeof(s_Max_Position_Limit) - 1, 4},\n    {s_Min_Position_Limit, 52, sizeof(s_Min_Position_Limit) - 1, 4},\n    {s_Shutdown, 63, sizeof(s_Shutdown) - 1, 1},\n\n    {s_Torque_Enable, 64, sizeof(s_Torque_Enable) - 1, 1},\n    {s_LED, 65, sizeof(s_LED) - 1, 1},\n    {s_Status_Return_Level, 68, sizeof(s_Status_Return_Level) - 1, 1},\n    {s_Registered_Instruction, 69, sizeof(s_Registered_Instruction) - 1, 1},\n    {s_Hardware_Error_Status, 70, sizeof(s_Hardware_Error_Status) - 1, 1},\n    {s_Velocity_I_Gain, 76, sizeof(s_Velocity_I_Gain) - 1, 2},\n    {s_Velocity_P_Gain, 78, sizeof(s_Velocity_P_Gain) - 1, 2},\n    {s_Position_D_Gain, 80, sizeof(s_Position_D_Gain) - 1, 2},\n    {s_Position_I_Gain, 82, sizeof(s_Position_I_Gain) - 1, 2},\n    {s_Position_P_Gain, 84, sizeof(s_Position_P_Gain) - 1, 2},\n    {s_Feedforward_2nd_Gain, 88, sizeof(s_Feedforward_2nd_Gain) - 1, 2},\n    {s_Feedforward_1st_Gain, 90, sizeof(s_Feedforward_1st_Gain) - 1, 2},\n    {s_Bus_Watchdog, 98, sizeof(s_Bus_Watchdog) - 1, 1},\n    {s_Goal_PWM, 100, sizeof(s_Goal_PWM) - 1, 2},\n    {s_Goal_Velocity, 104, sizeof(s_Goal_Velocity) - 1, 4},\n    {s_Profile_Acceleration, 108, sizeof(s_Profile_Acceleration) - 1, 4},\n    {s_Profile_Velocity, 112, sizeof(s_Profile_Velocity) - 1, 4},\n    {s_Goal_Position, 116, sizeof(s_Goal_Position) - 1, 4},\n    {s_Realtime_Tick, 120, sizeof(s_Realtime_Tick) - 1, 2},\n    {s_Moving, 122, sizeof(s_Moving) - 1, 1},\n    {s_Moving_Status, 123, sizeof(s_Moving_Status) - 1, 1},\n    {s_Present_PWM, 124, sizeof(s_Present_PWM) - 1, 2},\n    {s_Present_Load, 126, sizeof(s_Present_Load) - 1, 2},\n    {s_Present_Velocity, 128, sizeof(s_Present_Velocity) - 1, 4},\n    {s_Present_Position, 132, sizeof(s_Present_Position) - 1, 4},\n    {s_Velocity_Trajectory, 136, sizeof(s_Velocity_Trajectory) - 1, 4},\n    {s_Position_Trajectory, 140, sizeof(s_Position_Trajectory) - 1, 4},\n    {s_Present_Input_Voltage, 144, sizeof(s_Present_Input_Voltage) - 1, 2},\n    {s_Present_Temperature, 146, sizeof(s_Present_Temperature) - 1, 1}};\n\n#define COUNT_MX2_ITEMS (sizeof(items_MX2) / sizeof(items_MX2[0]))\n\nstatic const ModelInfo info_MX2 = {0.229,\n                                  0,\n                                  2048,\n                                  4096,\n                                  -3.14159265, \n                                  3.14159265};\n\n//---------------------------------------------------------\n// EXT MX Protocol 1 servos - (num == MX_64 || num == MX_106)\n//---------------------------------------------------------\nstatic const ControlItem items_EXTMX[]{\n    {s_Model_Number, 0, sizeof(s_Model_Number) - 1, 2},\n    {s_Firmware_Version, 2, sizeof(s_Firmware_Version) - 1, 1},\n    {s_ID, 3, sizeof(s_ID) - 1, 1},\n    {s_Baud_Rate, 4, sizeof(s_Baud_Rate) - 1, 1},\n    {s_Return_Delay_Time, 5, sizeof(s_Return_Delay_Time) - 1, 1},\n    {s_CW_Angle_Limit, 6, sizeof(s_CW_Angle_Limit) - 1, 2},\n    {s_CCW_Angle_Limit, 8, sizeof(s_CCW_Angle_Limit) - 1, 2},\n    {s_Temperature_Limit, 11, sizeof(s_Temperature_Limit) - 1, 1},\n    {s_Min_Voltage_Limit, 12, sizeof(s_Min_Voltage_Limit) - 1, 1},\n    {s_Max_Voltage_Limit, 13, sizeof(s_Max_Voltage_Limit) - 1, 1},\n    {s_Max_Torque, 14, sizeof(s_Max_Torque) - 1, 2},\n    {s_Status_Return_Level, 16, sizeof(s_Status_Return_Level) - 1, 1},\n    {s_Alarm_LED, 17, sizeof(s_Alarm_LED) - 1, 1},\n    {s_Shutdown, 18, sizeof(s_Shutdown) - 1, 1},\n    {s_Multi_Turn_Offset, 20, sizeof(s_Multi_Turn_Offset) - 1, 2},\n    {s_Resolution_Divider, 22, sizeof(s_Resolution_Divider) - 1, 1},\n\n    {s_Torque_Enable, 24, sizeof(s_Torque_Enable) - 1, 1},\n    {s_LED, 25, sizeof(s_LED) - 1, 1},\n    {s_D_gain, 26, sizeof(s_D_gain) - 1, 1},\n    {s_I_gain, 27, sizeof(s_I_gain) - 1, 1},\n    {s_P_gain, 28, sizeof(s_P_gain) - 1, 1},\n    {s_Goal_Position, 30, sizeof(s_Goal_Position) - 1, 2},\n    {s_Moving_Speed, 32, sizeof(s_Moving_Speed) - 1, 2},\n    {s_Torque_Limit, 34, sizeof(s_Torque_Limit) - 1, 2},\n    {s_Present_Position, 36, sizeof(s_Present_Position) - 1, 2},\n    {s_Present_Speed, 38, sizeof(s_Present_Speed) - 1, 2},\n    {s_Present_Load, 40, sizeof(s_Present_Load) - 1, 2},\n    {s_Present_Voltage, 42, sizeof(s_Present_Voltage) - 1, 1},\n    {s_Present_Temperature, 43, sizeof(s_Present_Temperature) - 1, 1},\n    {s_Registered, 44, sizeof(s_Registered) - 1, 1},\n    {s_Moving, 46, sizeof(s_Moving) - 1, 1},\n    {s_Lock, 47, sizeof(s_Lock) - 1, 1},\n    {s_Punch, 48, sizeof(s_Punch) - 1, 2},\n    {s_Current, 68, sizeof(s_Current) - 1, 2},\n    {s_Torque_Control_Mode_Enable, 70, sizeof(s_Torque_Control_Mode_Enable) - 1, 1},\n    {s_Goal_Torque, 71, sizeof(s_Goal_Torque) - 1, 2},\n    {s_Goal_Acceleration, 73, sizeof(s_Goal_Acceleration) - 1, 1}};\n\n#define COUNT_EXTMX_ITEMS (sizeof(items_EXTMX) / sizeof(items_EXTMX[0]))\n\nstatic const ModelInfo info_EXTMX = {0.11,\n                                  0,\n                                  2048,\n                                  4096,\n                                  -3.14159265, \n                                  3.14159265};\n\n//---------------------------------------------------------\n// EXT MX Protocol 2 Servos - (num == MX_64_2 || num == MX_106_2)\n//---------------------------------------------------------\nstatic const ControlItem items_EXTMX2[]{\n    {s_Model_Number, 0, sizeof(s_Model_Number) - 1, 2},\n    {s_Firmware_Version, 6, sizeof(s_Firmware_Version) - 1, 1},\n    {s_ID, 7, sizeof(s_ID) - 1, 1},\n    {s_Baud_Rate, 8, sizeof(s_Baud_Rate) - 1, 1},\n    {s_Return_Delay_Time, 9, sizeof(s_Return_Delay_Time) - 1, 1},\n    {s_Drive_Mode, 10, sizeof(s_Drive_Mode) - 1, 1},\n    {s_Operating_Mode, 11, sizeof(s_Operating_Mode) - 1, 1},\n    {s_Secondary_ID, 12, sizeof(s_Secondary_ID) - 1, 1},\n    {s_Protocol_Version, 13, sizeof(s_Protocol_Version) - 1, 1},\n    {s_Homing_Offset, 20, sizeof(s_Homing_Offset) - 1, 4},\n    {s_Moving_Threshold, 24, sizeof(s_Moving_Threshold) - 1, 4},\n    {s_Temperature_Limit, 31, sizeof(s_Temperature_Limit) - 1, 1},\n    {s_Max_Voltage_Limit, 32, sizeof(s_Max_Voltage_Limit) - 1, 2},\n    {s_Min_Voltage_Limit, 34, sizeof(s_Min_Voltage_Limit) - 1, 2},\n    {s_PWM_Limit, 36, sizeof(s_PWM_Limit) - 1, 2},\n    {s_Current_Limit, 38, sizeof(s_Current_Limit) - 1, 2},\n    {s_Acceleration_Limit, 40, sizeof(s_Acceleration_Limit) - 1, 4},\n    {s_Velocity_Limit, 44, sizeof(s_Velocity_Limit) - 1, 4},\n    {s_Max_Position_Limit, 48, sizeof(s_Max_Position_Limit) - 1, 4},\n    {s_Min_Position_Limit, 52, sizeof(s_Min_Position_Limit) - 1, 4},\n    {s_Shutdown, 63, sizeof(s_Shutdown) - 1, 1},\n\n    {s_Torque_Enable, 64, sizeof(s_Torque_Enable) - 1, 1},\n    {s_LED, 65, sizeof(s_LED) - 1, 1},\n    {s_Status_Return_Level, 68, sizeof(s_Status_Return_Level) - 1, 1},\n    {s_Registered_Instruction, 69, sizeof(s_Registered_Instruction) - 1, 1},\n    {s_Hardware_Error_Status, 70, sizeof(s_Hardware_Error_Status) - 1, 1},\n    {s_Velocity_I_Gain, 76, sizeof(s_Velocity_I_Gain) - 1, 2},\n    {s_Velocity_P_Gain, 78, sizeof(s_Velocity_P_Gain) - 1, 2},\n    {s_Position_D_Gain, 80, sizeof(s_Position_D_Gain) - 1, 2},\n    {s_Position_I_Gain, 82, sizeof(s_Position_I_Gain) - 1, 2},\n    {s_Position_P_Gain, 84, sizeof(s_Position_P_Gain) - 1, 2},\n    {s_Feedforward_2nd_Gain, 88, sizeof(s_Feedforward_2nd_Gain) - 1, 2},\n    {s_Feedforward_1st_Gain, 90, sizeof(s_Feedforward_1st_Gain) - 1, 2},\n    {s_Bus_Watchdog, 98, sizeof(s_Bus_Watchdog) - 1, 1},\n    {s_Goal_PWM, 100, sizeof(s_Goal_PWM) - 1, 2},\n    {s_Goal_Current, 102, sizeof(s_Goal_Current) - 1, 2},\n    {s_Goal_Velocity, 104, sizeof(s_Goal_Velocity) - 1, 4},\n    {s_Profile_Acceleration, 108, sizeof(s_Profile_Acceleration) - 1, 4},\n    {s_Profile_Velocity, 112, sizeof(s_Profile_Velocity) - 1, 4},\n    {s_Goal_Position, 116, sizeof(s_Goal_Position) - 1, 4},\n    {s_Realtime_Tick, 120, sizeof(s_Realtime_Tick) - 1, 2},\n    {s_Moving, 122, sizeof(s_Moving) - 1, 1},\n    {s_Moving_Status, 123, sizeof(s_Moving_Status) - 1, 1},\n    {s_Present_PWM, 124, sizeof(s_Present_PWM) - 1, 2},\n    {s_Present_Current, 126, sizeof(s_Present_Current) - 1, 2},\n    {s_Present_Velocity, 128, sizeof(s_Present_Velocity) - 1, 4},\n    {s_Present_Position, 132, sizeof(s_Present_Position) - 1, 4},\n    {s_Velocity_Trajectory, 136, sizeof(s_Velocity_Trajectory) - 1, 4},\n    {s_Position_Trajectory, 140, sizeof(s_Position_Trajectory) - 1, 4},\n    {s_Present_Input_Voltage, 144, sizeof(s_Present_Input_Voltage) - 1, 2},\n    {s_Present_Temperature, 146, sizeof(s_Present_Temperature) - 1, 1}};\n\n#define COUNT_EXTMX2_ITEMS (sizeof(items_EXTMX2) / sizeof(items_EXTMX2[0]))\n\nstatic const ModelInfo info_EXTMX2 = {0.229,\n                                  0,\n                                  2048,\n                                  4096,\n                                  -3.14159265, \n                                  3.14159265};\n\n//---------------------------------------------------------\n// XL320 - (num == XL_320)\n//---------------------------------------------------------\nstatic const ControlItem items_XL320[]{\n    {s_Model_Number, 0, sizeof(s_Model_Number) - 1, 2},\n    {s_Firmware_Version, 2, sizeof(s_Firmware_Version) - 1, 1},\n    {s_ID, 3, sizeof(s_ID) - 1, 1},\n    {s_Baud_Rate, 4, sizeof(s_Baud_Rate) - 1, 1},\n    {s_Return_Delay_Time, 5, sizeof(s_Return_Delay_Time) - 1, 1},\n    {s_CW_Angle_Limit, 6, sizeof(s_CW_Angle_Limit) - 1, 2},\n    {s_CCW_Angle_Limit, 8, sizeof(s_CCW_Angle_Limit) - 1, 2},\n    {s_Control_Mode, 11, sizeof(s_Control_Mode) - 1, 1},\n    {s_Temperature_Limit, 12, sizeof(s_Temperature_Limit) - 1, 1},\n    {s_Min_Voltage_Limit, 13, sizeof(s_Min_Voltage_Limit) - 1, 1},\n    {s_Max_Voltage_Limit, 14, sizeof(s_Max_Voltage_Limit) - 1, 1},\n    {s_Max_Torque, 15, sizeof(s_Max_Torque) - 1, 2},\n    {s_Status_Return_Level, 17, sizeof(s_Status_Return_Level) - 1, 1},\n    {s_Shutdown, 18, sizeof(s_Shutdown) - 1, 1},\n\n    {s_Torque_Enable, 24, sizeof(s_Torque_Enable) - 1, 1},\n    {s_LED, 25, sizeof(s_LED) - 1, 1},\n    {s_D_gain, 27, sizeof(s_D_gain) - 1, 1},\n    {s_I_gain, 28, sizeof(s_I_gain) - 1, 1},\n    {s_P_gain, 29, sizeof(s_P_gain) - 1, 1},\n    {s_Goal_Position, 30, sizeof(s_Goal_Position) - 1, 2},\n    {s_Moving_Speed, 32, sizeof(s_Moving_Speed) - 1, 2},\n    {s_Torque_Limit, 34, sizeof(s_Torque_Limit) - 1, 2},\n    {s_Present_Position, 37, sizeof(s_Present_Position) - 1, 2},\n    {s_Present_Speed, 39, sizeof(s_Present_Speed) - 1, 2},\n    {s_Present_Load, 41, sizeof(s_Present_Load) - 1, 2},\n    {s_Present_Voltage, 45, sizeof(s_Present_Voltage) - 1, 1},\n    {s_Present_Temperature, 46, sizeof(s_Present_Temperature) - 1, 1},\n    {s_Registered, 47, sizeof(s_Registered) - 1, 1},\n    {s_Moving, 49, sizeof(s_Moving) - 1, 1},\n    {s_Hardware_Error_Status, 50, sizeof(s_Hardware_Error_Status) - 1, 1},\n    {s_Punch, 51, sizeof(s_Punch) - 1, 2}};\n\n#define COUNT_XL320_ITEMS (sizeof(items_XL320) / sizeof(items_XL320[0]))\n\nstatic const ModelInfo info_XL320 = {0.11,\n                                  0,\n                                  512,\n                                  1024,\n                                  -2.61799, \n                                  2.61799};\n\n//---------------------------------------------------------\n// XL - (num == XL430_W250, XL430_W250_2, XC430_W150, XC430_W240, XC430_W250_2)\n//---------------------------------------------------------\nstatic const ControlItem items_XL[]{\n    {s_Model_Number, 0, sizeof(s_Model_Number) - 1, 2},\n    {s_Firmware_Version, 6, sizeof(s_Firmware_Version) - 1, 1},\n    {s_ID, 7, sizeof(s_ID) - 1, 1},\n    {s_Baud_Rate, 8, sizeof(s_Baud_Rate) - 1, 1},\n    {s_Return_Delay_Time, 9, sizeof(s_Return_Delay_Time) - 1, 1},\n    {s_Drive_Mode, 10, sizeof(s_Drive_Mode) - 1, 1},\n    {s_Operating_Mode, 11, sizeof(s_Operating_Mode) - 1, 1},\n    {s_Secondary_ID, 12, sizeof(s_Secondary_ID) - 1, 1},\n    {s_Protocol_Version, 13, sizeof(s_Protocol_Version) - 1, 1},\n    {s_Homing_Offset, 20, sizeof(s_Homing_Offset) - 1, 4},\n    {s_Moving_Threshold, 24, sizeof(s_Moving_Threshold) - 1, 4},\n    {s_Temperature_Limit, 31, sizeof(s_Temperature_Limit) - 1, 1},\n    {s_Max_Voltage_Limit, 32, sizeof(s_Max_Voltage_Limit) - 1, 2},\n    {s_Min_Voltage_Limit, 34, sizeof(s_Min_Voltage_Limit) - 1, 2},\n    {s_PWM_Limit, 36, sizeof(s_PWM_Limit) - 1, 2},\n    {s_Acceleration_Limit, 40, sizeof(s_Acceleration_Limit) - 1, 4},\n    {s_Velocity_Limit, 44, sizeof(s_Velocity_Limit) - 1, 4},\n    {s_Max_Position_Limit, 48, sizeof(s_Max_Position_Limit) - 1, 4},\n    {s_Min_Position_Limit, 52, sizeof(s_Min_Position_Limit) - 1, 4},\n    {s_Shutdown, 63, sizeof(s_Shutdown) - 1, 1},\n\n    {s_Torque_Enable, 64, sizeof(s_Torque_Enable) - 1, 1},\n    {s_LED, 65, sizeof(s_LED) - 1, 1},\n    {s_Status_Return_Level, 68, sizeof(s_Status_Return_Level) - 1, 1},\n    {s_Registered_Instruction, 69, sizeof(s_Registered_Instruction) - 1, 1},\n    {s_Hardware_Error_Status, 70, sizeof(s_Hardware_Error_Status) - 1, 1},\n    {s_Velocity_I_Gain, 76, sizeof(s_Velocity_I_Gain) - 1, 2},\n    {s_Velocity_P_Gain, 78, sizeof(s_Velocity_P_Gain) - 1, 2},\n    {s_Position_D_Gain, 80, sizeof(s_Position_D_Gain) - 1, 2},\n    {s_Position_I_Gain, 82, sizeof(s_Position_I_Gain) - 1, 2},\n    {s_Position_P_Gain, 84, sizeof(s_Position_P_Gain) - 1, 2},\n    {s_Feedforward_2nd_Gain, 88, sizeof(s_Feedforward_2nd_Gain) - 1, 2},\n    {s_Feedforward_1st_Gain, 90, sizeof(s_Feedforward_1st_Gain) - 1, 2},\n    {s_Bus_Watchdog, 98, sizeof(s_Bus_Watchdog) - 1, 1},\n    {s_Goal_PWM, 100, sizeof(s_Goal_PWM) - 1, 2},\n    {s_Goal_Velocity, 104, sizeof(s_Goal_Velocity) - 1, 4},\n    {s_Profile_Acceleration, 108, sizeof(s_Profile_Acceleration) - 1, 4},\n    {s_Profile_Velocity, 112, sizeof(s_Profile_Velocity) - 1, 4},\n    {s_Goal_Position, 116, sizeof(s_Goal_Position) - 1, 4},\n    {s_Realtime_Tick, 120, sizeof(s_Realtime_Tick) - 1, 2},\n    {s_Moving, 122, sizeof(s_Moving) - 1, 1},\n    {s_Moving_Status, 123, sizeof(s_Moving_Status) - 1, 1},\n    {s_Present_PWM, 124, sizeof(s_Present_PWM) - 1, 2},\n    {s_Present_Load, 126, sizeof(s_Present_Load) - 1, 2},\n    {s_Present_Velocity, 128, sizeof(s_Present_Velocity) - 1, 4},\n    {s_Present_Position, 132, sizeof(s_Present_Position) - 1, 4},\n    {s_Velocity_Trajectory, 136, sizeof(s_Velocity_Trajectory) - 1, 4},\n    {s_Position_Trajectory, 140, sizeof(s_Position_Trajectory) - 1, 4},\n    {s_Present_Input_Voltage, 144, sizeof(s_Present_Input_Voltage) - 1, 2},\n    {s_Present_Temperature, 146, sizeof(s_Present_Temperature) - 1, 1}};\n\n#define COUNT_XL_ITEMS (sizeof(items_XL) / sizeof(items_XL[0]))\n\nstatic const ModelInfo info_XL = {0.229,\n                                  0,\n                                  2048,\n                                  4096,\n                                  -3.14159265, \n                                  3.14159265};\n\n//---------------------------------------------------------\n// XM - (num == XM430_W210 || num == XM430_W350) || num == XL330_M077 || num == XL330_M288)\n//---------------------------------------------------------\nstatic const ControlItem items_XM[]{\n    {s_Model_Number, 0, sizeof(s_Model_Number) - 1, 2},\n    {s_Firmware_Version, 6, sizeof(s_Firmware_Version) - 1, 1},\n    {s_ID, 7, sizeof(s_ID) - 1, 1},\n    {s_Baud_Rate, 8, sizeof(s_Baud_Rate) - 1, 1},\n    {s_Return_Delay_Time, 9, sizeof(s_Return_Delay_Time) - 1, 1},\n    {s_Drive_Mode, 10, sizeof(s_Drive_Mode) - 1, 1},\n    {s_Operating_Mode, 11, sizeof(s_Operating_Mode) - 1, 1},\n    {s_Secondary_ID, 12, sizeof(s_Secondary_ID) - 1, 1},\n    {s_Protocol_Version, 13, sizeof(s_Protocol_Version) - 1, 1},\n    {s_Homing_Offset, 20, sizeof(s_Homing_Offset) - 1, 4},\n    {s_Moving_Threshold, 24, sizeof(s_Moving_Threshold) - 1, 4},\n    {s_Temperature_Limit, 31, sizeof(s_Temperature_Limit) - 1, 1},\n    {s_Max_Voltage_Limit, 32, sizeof(s_Max_Voltage_Limit) - 1, 2},\n    {s_Min_Voltage_Limit, 34, sizeof(s_Min_Voltage_Limit) - 1, 2},\n    {s_PWM_Limit, 36, sizeof(s_PWM_Limit) - 1, 2},\n    {s_Current_Limit, 38, sizeof(s_Current_Limit) - 1, 2},\n    {s_Acceleration_Limit, 40, sizeof(s_Acceleration_Limit) - 1, 4},\n    {s_Velocity_Limit, 44, sizeof(s_Velocity_Limit) - 1, 4},\n    {s_Max_Position_Limit, 48, sizeof(s_Max_Position_Limit) - 1, 4},\n    {s_Min_Position_Limit, 52, sizeof(s_Min_Position_Limit) - 1, 4},\n    {s_Shutdown, 63, sizeof(s_Shutdown) - 1, 1},\n\n    {s_Torque_Enable, 64, sizeof(s_Torque_Enable) - 1, 1},\n    {s_LED, 65, sizeof(s_LED) - 1, 1},\n    {s_Status_Return_Level, 68, sizeof(s_Status_Return_Level) - 1, 1},\n    {s_Registered_Instruction, 69, sizeof(s_Registered_Instruction) - 1, 1},\n    {s_Hardware_Error_Status, 70, sizeof(s_Hardware_Error_Status) - 1, 1},\n    {s_Velocity_I_Gain, 76, sizeof(s_Velocity_I_Gain) - 1, 2},\n    {s_Velocity_P_Gain, 78, sizeof(s_Velocity_P_Gain) - 1, 2},\n    {s_Position_D_Gain, 80, sizeof(s_Position_D_Gain) - 1, 2},\n    {s_Position_I_Gain, 82, sizeof(s_Position_I_Gain) - 1, 2},\n    {s_Position_P_Gain, 84, sizeof(s_Position_P_Gain) - 1, 2},\n    {s_Feedforward_2nd_Gain, 88, sizeof(s_Feedforward_2nd_Gain) - 1, 2},\n    {s_Feedforward_1st_Gain, 90, sizeof(s_Feedforward_1st_Gain) - 1, 2},\n    {s_Bus_Watchdog, 98, sizeof(s_Bus_Watchdog) - 1, 1},\n    {s_Goal_PWM, 100, sizeof(s_Goal_PWM) - 1, 2},\n    {s_Goal_Current, 102, sizeof(s_Goal_Current) - 1, 2},\n    {s_Goal_Velocity, 104, sizeof(s_Goal_Velocity) - 1, 4},\n    {s_Profile_Acceleration, 108, sizeof(s_Profile_Acceleration) - 1, 4},\n    {s_Profile_Velocity, 112, sizeof(s_Profile_Velocity) - 1, 4},\n    {s_Goal_Position, 116, sizeof(s_Goal_Position) - 1, 4},\n    {s_Realtime_Tick, 120, sizeof(s_Realtime_Tick) - 1, 2},\n    {s_Moving, 122, sizeof(s_Moving) - 1, 1},\n    {s_Moving_Status, 123, sizeof(s_Moving_Status) - 1, 1},\n    {s_Present_PWM, 124, sizeof(s_Present_PWM) - 1, 2},\n    {s_Present_Current, 126, sizeof(s_Present_Current) - 1, 2},\n    {s_Present_Velocity, 128, sizeof(s_Present_Velocity) - 1, 4},\n    {s_Present_Position, 132, sizeof(s_Present_Position) - 1, 4},\n    {s_Velocity_Trajectory, 136, sizeof(s_Velocity_Trajectory) - 1, 4},\n    {s_Position_Trajectory, 140, sizeof(s_Position_Trajectory) - 1, 4},\n    {s_Present_Input_Voltage, 144, sizeof(s_Present_Input_Voltage) - 1, 2},\n    {s_Present_Temperature, 146, sizeof(s_Present_Temperature) - 1, 1}};\n\n#define COUNT_XM_ITEMS (sizeof(items_XM) / sizeof(items_XM[0]))\n\nstatic const ModelInfo info_XM = {0.229,\n                                  0,\n                                  2048,\n                                  4096,\n                                  -3.14159265, \n                                  3.14159265};\n\n//---------------------------------------------------------\n// EXTXM - (num == XM540_W150 || num == XM540_W270)\n//---------------------------------------------------------\nstatic const ControlItem items_EXTXM[]{\n    {s_Model_Number, 0, sizeof(s_Model_Number) - 1, 2},\n    {s_Firmware_Version, 6, sizeof(s_Firmware_Version) - 1, 1},\n    {s_ID, 7, sizeof(s_ID) - 1, 1},\n    {s_Baud_Rate, 8, sizeof(s_Baud_Rate) - 1, 1},\n    {s_Return_Delay_Time, 9, sizeof(s_Return_Delay_Time) - 1, 1},\n    {s_Drive_Mode, 10, sizeof(s_Drive_Mode) - 1, 1},\n    {s_Operating_Mode, 11, sizeof(s_Operating_Mode) - 1, 1},\n    {s_Secondary_ID, 12, sizeof(s_Secondary_ID) - 1, 1},\n    {s_Protocol_Version, 13, sizeof(s_Protocol_Version) - 1, 1},\n    {s_Homing_Offset, 20, sizeof(s_Homing_Offset) - 1, 4},\n    {s_Moving_Threshold, 24, sizeof(s_Moving_Threshold) - 1, 4},\n    {s_Temperature_Limit, 31, sizeof(s_Temperature_Limit) - 1, 1},\n    {s_Max_Voltage_Limit, 32, sizeof(s_Max_Voltage_Limit) - 1, 2},\n    {s_Min_Voltage_Limit, 34, sizeof(s_Min_Voltage_Limit) - 1, 2},\n    {s_PWM_Limit, 36, sizeof(s_PWM_Limit) - 1, 2},\n    {s_Current_Limit, 38, sizeof(s_Current_Limit) - 1, 2},\n    {s_Acceleration_Limit, 40, sizeof(s_Acceleration_Limit) - 1, 4},\n    {s_Velocity_Limit, 44, sizeof(s_Velocity_Limit) - 1, 4},\n    {s_Max_Position_Limit, 48, sizeof(s_Max_Position_Limit) - 1, 4},\n    {s_Min_Position_Limit, 52, sizeof(s_Min_Position_Limit) - 1, 4},\n    {s_External_Port_Mode_1, 56, sizeof(s_External_Port_Mode_1) - 1, 1},\n    {s_External_Port_Mode_2, 57, sizeof(s_External_Port_Mode_2) - 1, 1},\n    {s_External_Port_Mode_3, 58, sizeof(s_External_Port_Mode_3) - 1, 1},\n    {s_Shutdown, 63, sizeof(s_Shutdown) - 1, 1},\n\n    {s_Torque_Enable, 64, sizeof(s_Torque_Enable) - 1, 1},\n    {s_LED, 65, sizeof(s_LED) - 1, 1},\n    {s_Status_Return_Level, 68, sizeof(s_Status_Return_Level) - 1, 1},\n    {s_Registered_Instruction, 69, sizeof(s_Registered_Instruction) - 1, 1},\n    {s_Hardware_Error_Status, 70, sizeof(s_Hardware_Error_Status) - 1, 1},\n    {s_Velocity_I_Gain, 76, sizeof(s_Velocity_I_Gain) - 1, 2},\n    {s_Velocity_P_Gain, 78, sizeof(s_Velocity_P_Gain) - 1, 2},\n    {s_Position_D_Gain, 80, sizeof(s_Position_D_Gain) - 1, 2},\n    {s_Position_I_Gain, 82, sizeof(s_Position_I_Gain) - 1, 2},\n    {s_Position_P_Gain, 84, sizeof(s_Position_P_Gain) - 1, 2},\n    {s_Feedforward_2nd_Gain, 88, sizeof(s_Feedforward_2nd_Gain) - 1, 2},\n    {s_Feedforward_1st_Gain, 90, sizeof(s_Feedforward_1st_Gain) - 1, 2},\n    {s_Bus_Watchdog, 98, sizeof(s_Bus_Watchdog) - 1, 1},\n    {s_Goal_PWM, 100, sizeof(s_Goal_PWM) - 1, 2},\n    {s_Goal_Current, 102, sizeof(s_Goal_Current) - 1, 2},\n    {s_Goal_Velocity, 104, sizeof(s_Goal_Velocity) - 1, 4},\n    {s_Profile_Acceleration, 108, sizeof(s_Profile_Acceleration) - 1, 4},\n    {s_Profile_Velocity, 112, sizeof(s_Profile_Velocity) - 1, 4},\n    {s_Goal_Position, 116, sizeof(s_Goal_Position) - 1, 4},\n    {s_Realtime_Tick, 120, sizeof(s_Realtime_Tick) - 1, 2},\n    {s_Moving, 122, sizeof(s_Moving) - 1, 1},\n    {s_Moving_Status, 123, sizeof(s_Moving_Status) - 1, 1},\n    {s_Present_PWM, 124, sizeof(s_Present_PWM) - 1, 2},\n    {s_Present_Current, 126, sizeof(s_Present_Current) - 1, 2},\n    {s_Present_Velocity, 128, sizeof(s_Present_Velocity) - 1, 4},\n    {s_Present_Position, 132, sizeof(s_Present_Position) - 1, 4},\n    {s_Velocity_Trajectory, 136, sizeof(s_Velocity_Trajectory) - 1, 4},\n    {s_Position_Trajectory, 140, sizeof(s_Position_Trajectory) - 1, 4},\n    {s_Present_Input_Voltage, 144, sizeof(s_Present_Input_Voltage) - 1, 2},\n    {s_Present_Temperature, 146, sizeof(s_Present_Temperature) - 1, 1}};\n\n#define COUNT_EXTXM_ITEMS (sizeof(items_EXTXM) / sizeof(items_EXTXM[0]))\n\nstatic const ModelInfo info_EXTXM = {0.229,\n                                  0,\n                                  2048,\n                                  4096,\n                                  -3.14159265, \n                                  3.14159265};\n\n//---------------------------------------------------------\n// XH - (num == XH430_V210 || num == XH430_V350 || num == XH430_W210 || num == XH430_W350 || num == XW540_T140 || num == XW540_T260)\n//---------------------------------------------------------\nstatic const ControlItem items_XH[]{\n    {s_Model_Number, 0, sizeof(s_Model_Number) - 1, 2},\n    {s_Firmware_Version, 6, sizeof(s_Firmware_Version) - 1, 1},\n    {s_ID, 7, sizeof(s_ID) - 1, 1},\n    {s_Baud_Rate, 8, sizeof(s_Baud_Rate) - 1, 1},\n    {s_Return_Delay_Time, 9, sizeof(s_Return_Delay_Time) - 1, 1},\n    {s_Drive_Mode, 10, sizeof(s_Drive_Mode) - 1, 1},\n    {s_Operating_Mode, 11, sizeof(s_Operating_Mode) - 1, 1},\n    {s_Secondary_ID, 12, sizeof(s_Secondary_ID) - 1, 1},\n    {s_Protocol_Version, 13, sizeof(s_Protocol_Version) - 1, 1},\n    {s_Homing_Offset, 20, sizeof(s_Homing_Offset) - 1, 4},\n    {s_Moving_Threshold, 24, sizeof(s_Moving_Threshold) - 1, 4},\n    {s_Temperature_Limit, 31, sizeof(s_Temperature_Limit) - 1, 1},\n    {s_Max_Voltage_Limit, 32, sizeof(s_Max_Voltage_Limit) - 1, 2},\n    {s_Min_Voltage_Limit, 34, sizeof(s_Min_Voltage_Limit) - 1, 2},\n    {s_PWM_Limit, 36, sizeof(s_PWM_Limit) - 1, 2},\n    {s_Current_Limit, 38, sizeof(s_Current_Limit) - 1, 2},\n    {s_Acceleration_Limit, 40, sizeof(s_Acceleration_Limit) - 1, 4},\n    {s_Velocity_Limit, 44, sizeof(s_Velocity_Limit) - 1, 4},\n    {s_Max_Position_Limit, 48, sizeof(s_Max_Position_Limit) - 1, 4},\n    {s_Min_Position_Limit, 52, sizeof(s_Min_Position_Limit) - 1, 4},\n    {s_Shutdown, 63, sizeof(s_Shutdown) - 1, 1},\n\n    {s_Torque_Enable, 64, sizeof(s_Torque_Enable) - 1, 1},\n    {s_LED, 65, sizeof(s_LED) - 1, 1},\n    {s_Status_Return_Level, 68, sizeof(s_Status_Return_Level) - 1, 1},\n    {s_Registered_Instruction, 69, sizeof(s_Registered_Instruction) - 1, 1},\n    {s_Hardware_Error_Status, 70, sizeof(s_Hardware_Error_Status) - 1, 1},\n    {s_Velocity_I_Gain, 76, sizeof(s_Velocity_I_Gain) - 1, 2},\n    {s_Velocity_P_Gain, 78, sizeof(s_Velocity_P_Gain) - 1, 2},\n    {s_Position_D_Gain, 80, sizeof(s_Position_D_Gain) - 1, 2},\n    {s_Position_I_Gain, 82, sizeof(s_Position_I_Gain) - 1, 2},\n    {s_Position_P_Gain, 84, sizeof(s_Position_P_Gain) - 1, 2},\n    {s_Feedforward_2nd_Gain, 88, sizeof(s_Feedforward_2nd_Gain) - 1, 2},\n    {s_Feedforward_1st_Gain, 90, sizeof(s_Feedforward_1st_Gain) - 1, 2},\n    {s_Bus_Watchdog, 98, sizeof(s_Bus_Watchdog) - 1, 1},\n    {s_Goal_PWM, 100, sizeof(s_Goal_PWM) - 1, 2},\n    {s_Goal_Current, 102, sizeof(s_Goal_Current) - 1, 2},\n    {s_Goal_Velocity, 104, sizeof(s_Goal_Velocity) - 1, 4},\n    {s_Profile_Acceleration, 108, sizeof(s_Profile_Acceleration) - 1, 4},\n    {s_Profile_Velocity, 112, sizeof(s_Profile_Velocity) - 1, 4},\n    {s_Goal_Position, 116, sizeof(s_Goal_Position) - 1, 4},\n    {s_Realtime_Tick, 120, sizeof(s_Realtime_Tick) - 1, 2},\n    {s_Moving, 122, sizeof(s_Moving) - 1, 1},\n    {s_Moving_Status, 123, sizeof(s_Moving_Status) - 1, 1},\n    {s_Present_PWM, 124, sizeof(s_Present_PWM) - 1, 2},\n    {s_Present_Current, 126, sizeof(s_Present_Current) - 1, 2},\n    {s_Present_Velocity, 128, sizeof(s_Present_Velocity) - 1, 4},\n    {s_Present_Position, 132, sizeof(s_Present_Position) - 1, 4},\n    {s_Velocity_Trajectory, 136, sizeof(s_Velocity_Trajectory) - 1, 4},\n    {s_Position_Trajectory, 140, sizeof(s_Position_Trajectory) - 1, 4},\n    {s_Present_Input_Voltage, 144, sizeof(s_Present_Input_Voltage) - 1, 2},\n    {s_Present_Temperature, 146, sizeof(s_Present_Temperature) - 1, 1}};\n\n#define COUNT_XH_ITEMS (sizeof(items_XH) / sizeof(items_XH[0]))\n\nstatic const ModelInfo info_XH = {0.229,\n                                  0,\n                                  2048,\n                                  4096,\n                                  -3.14159265, \n                                  3.14159265};\n\n//---------------------------------------------------------\n// EXTXH - (num == XH540_W150 || num == XH540_W270 || num == XH540_V150 || num == XH540_W270)\n//---------------------------------------------------------\nstatic const ControlItem items_EXTXH[]{\n    {s_Model_Number,       0,  sizeof(s_Model_Number) - 1,       2},\n    {s_Firmware_Version,   6,  sizeof(s_Firmware_Version) - 1,   1},\n    {s_ID,                 7,  sizeof(s_ID) - 1,                 1},\n    {s_Baud_Rate,          8,  sizeof(s_Baud_Rate) - 1,          1},\n    {s_Return_Delay_Time,  9,  sizeof(s_Return_Delay_Time) - 1,  1},\n    {s_Drive_Mode,         10, sizeof(s_Drive_Mode) - 1,         1},\n    {s_Operating_Mode,     11, sizeof(s_Operating_Mode) - 1,     1},\n    {s_Secondary_ID,       12, sizeof(s_Secondary_ID) - 1,       1},\n    {s_Protocol_Version,   13, sizeof(s_Protocol_Version) - 1,   1},\n    {s_Homing_Offset,      20, sizeof(s_Homing_Offset) - 1,      4},\n    {s_Moving_Threshold,   24, sizeof(s_Moving_Threshold) - 1,   4},\n    {s_Temperature_Limit,  31, sizeof(s_Temperature_Limit) - 1,  1},\n    {s_Max_Voltage_Limit,  32, sizeof(s_Max_Voltage_Limit) - 1,  2},\n    {s_Min_Voltage_Limit,  34, sizeof(s_Min_Voltage_Limit) - 1,  2},\n    {s_PWM_Limit,          36, sizeof(s_PWM_Limit) - 1,          2},\n    {s_Current_Limit,      38, sizeof(s_Current_Limit) - 1,      2},\n    {s_Acceleration_Limit, 40, sizeof(s_Acceleration_Limit) - 1, 4},\n    {s_Velocity_Limit,     44, sizeof(s_Velocity_Limit) - 1,     4},\n    {s_Max_Position_Limit, 48, sizeof(s_Max_Position_Limit) - 1, 4},\n    {s_Min_Position_Limit, 52, sizeof(s_Min_Position_Limit) - 1, 4},\n    {s_Shutdown,           63, sizeof(s_Shutdown) - 1, 1},\n\n    {s_Torque_Enable,          64,  sizeof(s_Torque_Enable) - 1,          1},\n    {s_LED,                    65,  sizeof(s_LED) - 1,                    1},\n    {s_Status_Return_Level,    68,  sizeof(s_Status_Return_Level) - 1,    1},\n    {s_Registered_Instruction, 69,  sizeof(s_Registered_Instruction) - 1, 1},\n    {s_Hardware_Error_Status,  70,  sizeof(s_Hardware_Error_Status) - 1,  1},\n    {s_Velocity_I_Gain,        76,  sizeof(s_Velocity_I_Gain) - 1,        2},\n    {s_Velocity_P_Gain,        78,  sizeof(s_Velocity_P_Gain) - 1,        2},\n    {s_Position_D_Gain,        80,  sizeof(s_Position_D_Gain) - 1,        2},\n    {s_Position_I_Gain,        82,  sizeof(s_Position_I_Gain) - 1,        2},\n    {s_Position_P_Gain,        84,  sizeof(s_Position_P_Gain) - 1,        2},\n    {s_Feedforward_2nd_Gain,   88,  sizeof(s_Feedforward_2nd_Gain) - 1,   2},\n    {s_Feedforward_1st_Gain,   90,  sizeof(s_Feedforward_1st_Gain) - 1,   2},\n    {s_Bus_Watchdog,           98,  sizeof(s_Bus_Watchdog) - 1,           1},\n    {s_Goal_PWM,               100, sizeof(s_Goal_PWM) - 1,               2},\n    {s_Goal_Current,           102, sizeof(s_Goal_Current) - 1,           2},\n    {s_Goal_Velocity,          104, sizeof(s_Goal_Velocity) - 1,          4},\n    {s_Profile_Acceleration,   108, sizeof(s_Profile_Acceleration) - 1,   4},\n    {s_Profile_Velocity,       112, sizeof(s_Profile_Velocity) - 1,       4},\n    {s_Goal_Position,          116, sizeof(s_Goal_Position) - 1,          4},\n    {s_Realtime_Tick,          120, sizeof(s_Realtime_Tick) - 1,          2},\n    {s_Moving,                 122, sizeof(s_Moving) - 1,                 1},\n    {s_Moving_Status,          123, sizeof(s_Moving_Status) - 1,          1},\n    {s_Present_PWM,            124, sizeof(s_Present_PWM) - 1,            2},\n    {s_Present_Current,        126, sizeof(s_Present_Current) - 1,        2},\n    {s_Present_Velocity,       128, sizeof(s_Present_Velocity) - 1,       4},\n    {s_Present_Position,       132, sizeof(s_Present_Position) - 1,       4},\n    {s_Velocity_Trajectory,    136, sizeof(s_Velocity_Trajectory) - 1,    4},\n    {s_Position_Trajectory,    140, sizeof(s_Position_Trajectory) - 1,    4},\n    {s_Present_Input_Voltage,  144, sizeof(s_Present_Input_Voltage) - 1,  2},\n    {s_Present_Temperature,    146, sizeof(s_Present_Temperature) - 1,    1}};\n\n#define COUNT_EXTXH_ITEMS (sizeof(items_EXTXH) / sizeof(items_EXTXH[0]))\n\nstatic const ModelInfo info_EXTXH = {0.229,\n                                  0,\n                                  2048,\n                                  4096,\n                                  -3.14159265, \n                                  3.14159265};\n\n//---------------------------------------------------------\n// PRO - (num == PRO_L42_10_S300_R)\n//---------------------------------------------------------\nstatic const ControlItem items_PRO[]{\n    {s_Model_Number, 0, sizeof(s_Model_Number) - 1, 2},\n    {s_Firmware_Version, 6, sizeof(s_Firmware_Version) - 1, 1},\n    {s_ID, 7, sizeof(s_ID) - 1, 1},\n    {s_Baud_Rate, 8, sizeof(s_Baud_Rate) - 1, 1},\n    {s_Return_Delay_Time, 9, sizeof(s_Return_Delay_Time) - 1, 1},\n    {s_Operating_Mode, 11, sizeof(s_Operating_Mode) - 1, 1},\n    {s_Moving_Threshold, 17, sizeof(s_Moving_Threshold) - 1, 4},\n    {s_Temperature_Limit, 21, sizeof(s_Temperature_Limit) - 1, 1},\n    {s_Max_Voltage_Limit, 22, sizeof(s_Max_Voltage_Limit) - 1, 2},\n    {s_Min_Voltage_Limit, 24, sizeof(s_Min_Voltage_Limit) - 1, 2},\n    {s_Acceleration_Limit, 26, sizeof(s_Acceleration_Limit) - 1, 4},\n    {s_Torque_Limit, 30, sizeof(s_Torque_Limit) - 1, 2},\n    {s_Velocity_Limit, 32, sizeof(s_Velocity_Limit) - 1, 4},\n    {s_Max_Position_Limit, 36, sizeof(s_Max_Position_Limit) - 1, 4},\n    {s_Min_Position_Limit, 40, sizeof(s_Min_Position_Limit) - 1, 4},\n    {s_External_Port_Mode_1, 44, sizeof(s_External_Port_Mode_1) - 1, 1},\n    {s_External_Port_Mode_2, 45, sizeof(s_External_Port_Mode_2) - 1, 1},\n    {s_External_Port_Mode_3, 46, sizeof(s_External_Port_Mode_3) - 1, 1},\n    {s_External_Port_Mode_4, 47, sizeof(s_External_Port_Mode_4) - 1, 1},\n    {s_Shutdown, 48, sizeof(s_Shutdown) - 1, 1},\n\n    {s_Torque_Enable, 562, sizeof(s_Torque_Enable) - 1, 1},\n    {s_LED_RED, 563, sizeof(s_LED_RED) - 1, 1},\n    {s_LED_GREEN, 564, sizeof(s_LED_GREEN) - 1, 1},\n    {s_LED_BLUE, 565, sizeof(s_LED_BLUE) - 1, 1},\n    {s_Velocity_I_Gain, 586, sizeof(s_Velocity_I_Gain) - 1, 2},\n    {s_Velocity_P_Gain, 588, sizeof(s_Velocity_P_Gain) - 1, 2},\n    {s_Position_P_Gain, 594, sizeof(s_Position_P_Gain) - 1, 2},\n    {s_Goal_Position, 596, sizeof(s_Goal_Position) - 1, 4},\n    {s_Goal_Velocity, 600, sizeof(s_Goal_Velocity) - 1, 4},\n    {s_Goal_Torque, 604, sizeof(s_Goal_Torque) - 1, 2},\n    {s_Goal_Acceleration, 606, sizeof(s_Goal_Acceleration) - 1, 4},\n    {s_Moving, 610, sizeof(s_Moving) - 1, 1},\n    {s_Present_Position, 611, sizeof(s_Present_Position) - 1, 4},\n    {s_Present_Velocity, 615, sizeof(s_Present_Velocity) - 1, 4},\n    {s_Present_Current, 621, sizeof(s_Present_Current) - 1, 2},\n    {s_Present_Input_Voltage, 623, sizeof(s_Present_Input_Voltage) - 1, 2},\n    {s_Present_Temperature, 625, sizeof(s_Present_Temperature) - 1, 1},\n    {s_External_Port_Mode_1, 626, sizeof(s_External_Port_Mode_1) - 1, 2},\n    {s_External_Port_Mode_2, 628, sizeof(s_External_Port_Mode_2) - 1, 2},\n    {s_External_Port_Mode_3, 630, sizeof(s_External_Port_Mode_3) - 1, 2},\n    {s_External_Port_Mode_4, 632, sizeof(s_External_Port_Mode_4) - 1, 2},\n    {s_Registered_Instruction, 890, sizeof(s_Registered_Instruction) - 1, 1},\n    {s_Status_Return_Level, 891, sizeof(s_Status_Return_Level) - 1, 1},\n    {s_Hardware_Error_Status, 892, sizeof(s_Hardware_Error_Status) - 1, 1}};\n\n#define COUNT_PRO_ITEMS (sizeof(items_PRO) / sizeof(items_PRO[0]))\n\nstatic const ModelInfo info_PRO = {0.114,\n                                  -2048,\n                                  0,\n                                  2048,\n                                  -3.14159265, \n                                  3.14159265};\n\n//---------------------------------------------------------\n// EXT PRO - All Other Pros...\n//---------------------------------------------------------\nstatic const ControlItem items_EXTPRO[]{\n    {s_Model_Number, 0, sizeof(s_Model_Number) - 1, 2},\n    {s_Firmware_Version, 6, sizeof(s_Firmware_Version) - 1, 1},\n    {s_ID, 7, sizeof(s_ID) - 1, 1},\n    {s_Baud_Rate, 8, sizeof(s_Baud_Rate) - 1, 1},\n    {s_Return_Delay_Time, 9, sizeof(s_Return_Delay_Time) - 1, 1},\n    {s_Operating_Mode, 11, sizeof(s_Operating_Mode) - 1, 1},\n    {s_Homing_Offset, 13, sizeof(s_Homing_Offset) - 1, 4},\n    {s_Moving_Threshold, 17, sizeof(s_Moving_Threshold) - 1, 4},\n    {s_Temperature_Limit, 21, sizeof(s_Temperature_Limit) - 1, 1},\n    {s_Max_Voltage_Limit, 22, sizeof(s_Max_Voltage_Limit) - 1, 2},\n    {s_Min_Voltage_Limit, 24, sizeof(s_Min_Voltage_Limit) - 1, 2},\n    {s_Acceleration_Limit, 26, sizeof(s_Acceleration_Limit) - 1, 4},\n    {s_Torque_Limit, 30, sizeof(s_Torque_Limit) - 1, 2},\n    {s_Velocity_Limit, 32, sizeof(s_Velocity_Limit) - 1, 4},\n    {s_Max_Position_Limit, 36, sizeof(s_Max_Position_Limit) - 1, 4},\n    {s_Min_Position_Limit, 40, sizeof(s_Min_Position_Limit) - 1, 4},\n    {s_External_Port_Mode_1, 44, sizeof(s_External_Port_Mode_1) - 1, 1},\n    {s_External_Port_Mode_2, 45, sizeof(s_External_Port_Mode_2) - 1, 1},\n    {s_External_Port_Mode_3, 46, sizeof(s_External_Port_Mode_3) - 1, 1},\n    {s_External_Port_Mode_4, 47, sizeof(s_External_Port_Mode_4) - 1, 1},\n    {s_Shutdown, 48, sizeof(s_Shutdown) - 1, 1},\n\n    {s_Torque_Enable, 562, sizeof(s_Torque_Enable) - 1, 1},\n    {s_LED_RED, 563, sizeof(s_LED_RED) - 1, 1},\n    {s_LED_GREEN, 564, sizeof(s_LED_GREEN) - 1, 1},\n    {s_LED_BLUE, 565, sizeof(s_LED_BLUE) - 1, 1},\n    {s_Velocity_I_Gain, 586, sizeof(s_Velocity_I_Gain) - 1, 2},\n    {s_Velocity_P_Gain, 588, sizeof(s_Velocity_P_Gain) - 1, 2},\n    {s_Position_P_Gain, 594, sizeof(s_Position_P_Gain) - 1, 2},\n    {s_Goal_Position, 596, sizeof(s_Goal_Position) - 1, 4},\n    {s_Goal_Velocity, 600, sizeof(s_Goal_Velocity) - 1, 4},\n    {s_Goal_Torque, 604, sizeof(s_Goal_Torque) - 1, 2},\n    {s_Goal_Acceleration, 606, sizeof(s_Goal_Acceleration) - 1, 4},\n    {s_Moving, 610, sizeof(s_Moving) - 1, 1},\n    {s_Present_Position, 611, sizeof(s_Present_Position) - 1, 4},\n    {s_Present_Velocity, 615, sizeof(s_Present_Velocity) - 1, 4},\n    {s_Present_Current, 621, sizeof(s_Present_Current) - 1, 2},\n    {s_Present_Input_Voltage, 623, sizeof(s_Present_Input_Voltage) - 1, 2},\n    {s_Present_Temperature, 625, sizeof(s_Present_Temperature) - 1, 1},\n    {s_External_Port_Mode_1, 626, sizeof(s_External_Port_Mode_1) - 1, 2},\n    {s_External_Port_Mode_2, 628, sizeof(s_External_Port_Mode_2) - 1, 2},\n    {s_External_Port_Mode_3, 630, sizeof(s_External_Port_Mode_3) - 1, 2},\n    {s_External_Port_Mode_4, 632, sizeof(s_External_Port_Mode_4) - 1, 2},\n    {s_Registered_Instruction, 890, sizeof(s_Registered_Instruction) - 1, 1},\n    {s_Status_Return_Level, 891, sizeof(s_Status_Return_Level) - 1, 1},\n    {s_Hardware_Error_Status, 892, sizeof(s_Hardware_Error_Status) - 1, 1}};\n\n#define COUNT_EXTPRO_ITEMS (sizeof(items_EXTPRO) / sizeof(items_EXTPRO[0]))\n\nstatic const ModelInfo info_EXTPRO[] = {\n      {0.00249657, -144197, 0, 144197, -3.14159265, 3.14159265},  // PRO_L54_30_S400_R\n      {0.00199234, -180692, 0, 180692, -3.14159265, 3.14159265},  // PRO_L54_30_S500_R, PRO_L54_50_S500_R\n      {0.00346667, -103846, 0, 103846, -3.14159265, 3.14159265},  // PRO_L54_50_S290_R\n      {0.00389076, -131593, 0, 131593, -3.14159265, 3.14159265},  // PRO_M42_10_S260_R\n      {0.00397746, -125708, 0, 125708, -3.14159265, 3.14159265},  // PRO_M54_40_S250_R, PRO_M54_60_S250_R\n      {0.00329218, -151875, 0, 151875, -3.14159265, 3.14159265},  // PRO_H42_20_S300_R\n      {0.00199234, -250961, 0, 250961, -3.14159265, 3.14159265}}; // PRO_H54_100_S500_R, PRO_H54_200_S500_R\n\n//---------------------------------------------------------\n// EXT PRO (A Firmware_Version) \n//---------------------------------------------------------\nstatic const ControlItem items_EXTPRO_A[]{\n    {s_Model_Number,         0, sizeof(s_Model_Number) - 1,          2},\n    {s_Firmware_Version,     6, sizeof(s_Firmware_Version) - 1,      1},\n    {s_ID,                   7, sizeof(s_ID) - 1,                    1},\n    {s_Baud_Rate,            8, sizeof(s_Baud_Rate) - 1,             1},\n    {s_Return_Delay_Time,    9, sizeof(s_Return_Delay_Time) - 1,     1},\n    {s_Operating_Mode,       11, sizeof(s_Operating_Mode) - 1,       1},\n    {s_Homing_Offset,        20, sizeof(s_Homing_Offset) - 1,        4},\n    {s_Moving_Threshold,     24, sizeof(s_Moving_Threshold) - 1,     4},\n    {s_Temperature_Limit,    31, sizeof(s_Temperature_Limit) - 1,    1},\n    {s_Max_Voltage_Limit,    32, sizeof(s_Max_Voltage_Limit) - 1,    2},\n    {s_Min_Voltage_Limit,    34, sizeof(s_Min_Voltage_Limit) - 1,    2},\n    {s_Current_Limit,        38, sizeof(s_Current_Limit) - 1,        2},\n    {s_Acceleration_Limit,   40, sizeof(s_Acceleration_Limit) - 1,   4},\n    {s_Velocity_Limit,       44, sizeof(s_Velocity_Limit) - 1,       4},\n    {s_Max_Position_Limit,   48, sizeof(s_Max_Position_Limit) - 1,   4},\n    {s_Min_Position_Limit,   52, sizeof(s_Min_Position_Limit) - 1,   4},\n    {s_External_Port_Mode_1, 56, sizeof(s_External_Port_Mode_1) - 1, 1},\n    {s_External_Port_Mode_2, 57, sizeof(s_External_Port_Mode_2) - 1, 1},\n    {s_External_Port_Mode_3, 58, sizeof(s_External_Port_Mode_3) - 1, 1},\n    {s_External_Port_Mode_4, 59, sizeof(s_External_Port_Mode_4) - 1, 1},\n    {s_Shutdown,             63, sizeof(s_Shutdown) - 1,             1},\n\n    {s_Torque_Enable,          512, sizeof(s_Torque_Enable) - 1,          1},\n    {s_LED_RED,                513, sizeof(s_LED_RED) - 1,                1},\n    {s_LED_GREEN,              514, sizeof(s_LED_GREEN) - 1,              1},\n    {s_LED_BLUE,               515, sizeof(s_LED_BLUE) - 1,               1},\n    {s_Velocity_I_Gain,        524, sizeof(s_Velocity_I_Gain) - 1,        2},\n    {s_Velocity_P_Gain,        526, sizeof(s_Velocity_P_Gain) - 1,        2},\n    {s_Position_D_Gain,        528, sizeof(s_Position_D_Gain) - 1,        2},\n    {s_Position_P_Gain,        532, sizeof(s_Position_P_Gain) - 1,        2},\n    {s_Position_I_Gain,        530, sizeof(s_Position_I_Gain) - 1,        2},\n    {s_Goal_Position,          564, sizeof(s_Goal_Position) - 1,          4},\n    {s_Goal_Velocity,          552, sizeof(s_Goal_Velocity) - 1,          4},\n    {s_Goal_Current,           604, sizeof(s_Goal_Current) - 1,           2},\n    {s_Profile_Acceleration,   556, sizeof(s_Profile_Acceleration) - 1,   4},\n    {s_Profile_Velocity,       560, sizeof(s_Profile_Velocity) - 1,       4},\n    {s_Moving,                 570, sizeof(s_Moving) - 1,                 1},\n    {s_Present_Position,       580, sizeof(s_Present_Position) - 1,       4},\n    {s_Present_Velocity,       576, sizeof(s_Present_Velocity) - 1,       4},\n    {s_Present_Current,        574, sizeof(s_Present_Current) - 1,        2},\n    {s_Present_Input_Voltage,  592, sizeof(s_Present_Input_Voltage) - 1,  2},\n    {s_Present_Temperature,    594, sizeof(s_Present_Temperature) - 1,    1},\n    {s_External_Port_Mode_1,   600, sizeof(s_External_Port_Mode_1) - 1,   2},\n    {s_External_Port_Mode_2,   602, sizeof(s_External_Port_Mode_2) - 1,   2},\n    {s_External_Port_Mode_3,   604, sizeof(s_External_Port_Mode_3) - 1,   2},\n    {s_External_Port_Mode_4,   606, sizeof(s_External_Port_Mode_4) - 1,   2}};\n\n#define COUNT_EXTPRO_A_ITEMS (sizeof(items_EXTPRO_A) / sizeof(items_EXTPRO_A[0]))\n\nstatic const ModelInfo info_EXTPRO_A[] = {\n      {0.00389076, -131593, 0, 131593, -3.14159265, 3.14159265},  // PRO_M42_10_S260_R_A\n      {0.00397746, -125708, 0, 125708, -3.14159265, 3.14159265},  // PRO_M54_40_S250_R_A, PRO_M54_60_S250_R_A\n      {0.00329218, -151875, 0, 151875, -3.14159265, 3.14159265},  // PRO_H42_20_S300_R_A\n      {0.00199234, -250961, 0, 250961, -3.14159265, 3.14159265}}; // PRO_H54_100_S500_R_A, PRO_H54_200_S500_R_A\n\n//---------------------------------------------------------\n// PRO PLUS - (num == PRO_H42P_020_S300_R, PRO_H54P_100_S500_R, PRO_H54P_200_S500_R)\n//---------------------------------------------------------\nstatic const ControlItem items_PRO_PLUS[]{\n    {s_Model_Number, 0, sizeof(s_Model_Number) - 1, 2},\n    {s_Firmware_Version, 6, sizeof(s_Firmware_Version) - 1, 1},\n    {s_ID, 7, sizeof(s_ID) - 1, 1},\n    {s_Baud_Rate, 8, sizeof(s_Baud_Rate) - 1, 1},\n    {s_Return_Delay_Time, 9, sizeof(s_Return_Delay_Time) - 1, 1},\n    {s_Drive_Mode, 10, sizeof(s_Drive_Mode) - 1, 1},\n    {s_Operating_Mode, 11, sizeof(s_Operating_Mode) - 1, 1},\n    {s_Secondary_ID, 12, sizeof(s_Secondary_ID) - 1, 1},\n    {s_Homing_Offset, 20, sizeof(s_Homing_Offset) - 1, 4},\n    {s_Moving_Threshold, 24, sizeof(s_Moving_Threshold) - 1, 4},\n    {s_Temperature_Limit, 31, sizeof(s_Temperature_Limit) - 1, 1},\n    {s_Max_Voltage_Limit, 32, sizeof(s_Max_Voltage_Limit) - 1, 2},\n    {s_Min_Voltage_Limit, 34, sizeof(s_Min_Voltage_Limit) - 1, 2},\n    {s_PWM_Limit, 36, sizeof(s_PWM_Limit) - 1, 2},\n    {s_Current_Limit, 38, sizeof(s_Current_Limit) - 1, 2},\n    {s_Acceleration_Limit, 40, sizeof(s_Acceleration_Limit) - 1, 4},\n    {s_Velocity_Limit, 44, sizeof(s_Velocity_Limit) - 1, 4},\n    {s_Max_Position_Limit, 48, sizeof(s_Max_Position_Limit) - 1, 4},\n    {s_Min_Position_Limit, 52, sizeof(s_Min_Position_Limit) - 1, 4},\n    {s_External_Port_Mode_1, 56, sizeof(s_External_Port_Mode_1) - 1, 1},\n    {s_External_Port_Mode_2, 57, sizeof(s_External_Port_Mode_2) - 1, 1},\n    {s_External_Port_Mode_3, 58, sizeof(s_External_Port_Mode_3) - 1, 1},\n    {s_External_Port_Mode_4, 59, sizeof(s_External_Port_Mode_4) - 1, 1},\n    {s_Shutdown, 63, sizeof(s_Shutdown) - 1, 1},\n\n    {s_Torque_Enable, 512, sizeof(s_Torque_Enable) - 1, 1},\n    {s_LED_RED, 513, sizeof(s_LED_RED) - 1, 1},\n    {s_LED_GREEN, 514, sizeof(s_LED_GREEN) - 1, 1},\n    {s_LED_BLUE, 515, sizeof(s_LED_BLUE) - 1, 1},\n    {s_Status_Return_Level, 516, sizeof(s_Status_Return_Level) - 1, 1},\n    {s_Registered_Instruction, 517, sizeof(s_Registered_Instruction) - 1, 1},\n    {s_Hardware_Error_Status, 518, sizeof(s_Hardware_Error_Status) - 1, 1},\n    {s_Velocity_I_Gain, 524, sizeof(s_Velocity_I_Gain) - 1, 2},\n    {s_Velocity_P_Gain, 526, sizeof(s_Velocity_P_Gain) - 1, 2},\n    {s_Position_D_Gain, 528, sizeof(s_Position_D_Gain) - 1, 2},\n    {s_Position_I_Gain, 530, sizeof(s_Position_I_Gain) - 1, 2},\n    {s_Position_P_Gain, 532, sizeof(s_Position_P_Gain) - 1, 2},\n    {s_Feedforward_2nd_Gain, 536, sizeof(s_Feedforward_2nd_Gain) - 1, 2},\n    {s_Feedforward_1st_Gain, 538, sizeof(s_Feedforward_1st_Gain) - 1, 2},\n    {s_Bus_Watchdog, 546, sizeof(s_Bus_Watchdog) - 1, 1},\n    {s_Goal_PWM, 548, sizeof(s_Goal_PWM) - 1, 2},\n    {s_Goal_Current, 550, sizeof(s_Goal_Current) - 1, 2},\n    {s_Goal_Velocity, 552, sizeof(s_Goal_Velocity) - 1, 4},\n    {s_Profile_Acceleration, 556, sizeof(s_Profile_Acceleration) - 1, 4},\n    {s_Profile_Velocity, 560, sizeof(s_Profile_Velocity) - 1, 4},\n    {s_Goal_Position, 564, sizeof(s_Goal_Position) - 1, 4},    \n    {s_Realtime_Tick, 568, sizeof(s_Realtime_Tick) - 1, 2},\n    {s_Moving, 570, sizeof(s_Moving) - 1, 1},\n    {s_Moving_Status, 571, sizeof(s_Moving) - 1, 1},\n    {s_Present_PWM, 572, sizeof(s_Present_PWM) - 1, 2},\n    {s_Present_Current, 574, sizeof(s_Present_Current) - 1, 2},\n    {s_Present_Velocity, 576, sizeof(s_Present_Velocity) - 1, 4},\n    {s_Present_Position, 580, sizeof(s_Present_Position) - 1, 4},\n    {s_Velocity_Trajectory, 584, sizeof(s_Velocity_Trajectory) - 1, 4},\n    {s_Position_Trajectory, 588, sizeof(s_Position_Trajectory) - 1, 4},    \n    {s_Present_Input_Voltage, 592, sizeof(s_Present_Input_Voltage) - 1, 2},\n    {s_Present_Temperature, 594, sizeof(s_Present_Temperature) - 1, 1},\n    {s_External_Port_Mode_1, 600, sizeof(s_External_Port_Mode_1) - 1, 2},\n    {s_External_Port_Mode_2, 602, sizeof(s_External_Port_Mode_2) - 1, 2},\n    {s_External_Port_Mode_3, 604, sizeof(s_External_Port_Mode_3) - 1, 2},\n    {s_External_Port_Mode_4, 606, sizeof(s_External_Port_Mode_4) - 1, 2}};\n\n#define COUNT_EXTPRO_PLUS_ITEMS (sizeof(items_PRO_PLUS) / sizeof(items_PRO_PLUS[0]))\n\nstatic const ModelInfo info_PRO_PLUS[] = {\n      {0.01, -251173, 0, 251173, -3.14159265, 3.14159265},  // PRO_PLUS_M42P_010_S260_R\n      {0.01, -251173, 0, 251173, -3.14159265, 3.14159265},  // PRO_PLUS_M54P_040_S250_R\n      {0.01, -262931, 0, 262931, -3.14159265, 3.14159265},  // PRO_PLUS_M54P_060_S250_R\n      {0.01, -303454, 0, 303454, -3.14159265, 3.14159265},  // PRO_PLUS_H42P_020_S300_R\n      {0.01, -501433, 0, 501433, -3.14159265, 3.14159265},  // PRO_PLUS_H54P_100_S500_R\n      {0.01, -501433, 0, 501433, -3.14159265, 3.14159265}}; // PRO_PLUS_H54P_200_S500_R\n\n//---------------------------------------------------------\n// Gripper - (num == RH_P12_RN)\n//---------------------------------------------------------\nstatic const ControlItem items_Gripper[]{\n    {s_Model_Number, 0, sizeof(s_Model_Number) - 1, 2},\n    {s_Firmware_Version, 6, sizeof(s_Firmware_Version) - 1, 1},\n    {s_ID, 7, sizeof(s_ID) - 1, 1},\n    {s_Baud_Rate, 8, sizeof(s_Baud_Rate) - 1, 1},\n    {s_Return_Delay_Time, 9, sizeof(s_Return_Delay_Time) - 1, 1},\n    {s_Operating_Mode, 11, sizeof(s_Operating_Mode) - 1, 1},\n    {s_Homing_Offset, 13, sizeof(s_Homing_Offset) - 1, 4},\n    {s_Moving_Threshold, 17, sizeof(s_Moving_Threshold) - 1, 4},\n    {s_Temperature_Limit, 21, sizeof(s_Temperature_Limit) - 1, 1},\n    {s_Max_Voltage_Limit, 22, sizeof(s_Max_Voltage_Limit) - 1, 2},\n    {s_Min_Voltage_Limit, 24, sizeof(s_Min_Voltage_Limit) - 1, 2},\n    {s_Acceleration_Limit, 26, sizeof(s_Acceleration_Limit) - 1, 4},\n    {s_Torque_Limit, 30, sizeof(s_Torque_Limit) - 1, 2},\n    {s_Velocity_Limit, 32, sizeof(s_Velocity_Limit) - 1, 4},\n    {s_Max_Position_Limit, 36, sizeof(s_Max_Position_Limit) - 1, 4},\n    {s_Min_Position_Limit, 40, sizeof(s_Min_Position_Limit) - 1, 4},\n    {s_External_Port_Mode_1, 44, sizeof(s_External_Port_Mode_1) - 1, 1},\n    {s_External_Port_Mode_2, 45, sizeof(s_External_Port_Mode_2) - 1, 1},\n    {s_External_Port_Mode_3, 46, sizeof(s_External_Port_Mode_3) - 1, 1},\n    {s_External_Port_Mode_4, 47, sizeof(s_External_Port_Mode_4) - 1, 1},\n    {s_Shutdown, 48, sizeof(s_Shutdown) - 1, 1},\n\n    {s_Torque_Enable, 562, sizeof(s_Torque_Enable) - 1, 1},\n    {s_LED_RED, 563, sizeof(s_LED_RED) - 1, 1},\n    {s_LED_GREEN, 564, sizeof(s_LED_GREEN) - 1, 1},\n    {s_LED_BLUE, 565, sizeof(s_LED_BLUE) - 1, 1},\n    {s_Velocity_I_Gain, 586, sizeof(s_Velocity_I_Gain) - 1, 2},\n    {s_Velocity_P_Gain, 588, sizeof(s_Velocity_P_Gain) - 1, 2},\n    {s_Position_P_Gain, 594, sizeof(s_Position_P_Gain) - 1, 2},\n    {s_Goal_Position, 596, sizeof(s_Goal_Position) - 1, 4},\n    {s_Goal_Velocity, 600, sizeof(s_Goal_Velocity) - 1, 4},\n    {s_Goal_Torque, 604, sizeof(s_Goal_Torque) - 1, 2},\n    {s_Goal_Acceleration, 606, sizeof(s_Goal_Acceleration) - 1, 4},\n    {s_Moving, 610, sizeof(s_Moving) - 1, 1},\n    {s_Present_Position, 611, sizeof(s_Present_Position) - 1, 4},\n    {s_Present_Velocity, 615, sizeof(s_Present_Velocity) - 1, 4},\n    {s_Present_Current, 621, sizeof(s_Present_Current) - 1, 2},\n    {s_Present_Input_Voltage, 623, sizeof(s_Present_Input_Voltage) - 1, 2},\n    {s_Present_Temperature, 625, sizeof(s_Present_Temperature) - 1, 1},\n    {s_External_Port_Mode_1, 626, sizeof(s_External_Port_Mode_1) - 1, 2},\n    {s_External_Port_Mode_2, 628, sizeof(s_External_Port_Mode_2) - 1, 2},\n    {s_External_Port_Mode_3, 630, sizeof(s_External_Port_Mode_3) - 1, 2},\n    {s_External_Port_Mode_4, 632, sizeof(s_External_Port_Mode_4) - 1, 2},\n    {s_Registered_Instruction, 890, sizeof(s_Registered_Instruction) - 1, 1},\n    {s_Status_Return_Level, 891, sizeof(s_Status_Return_Level) - 1, 1},\n    {s_Hardware_Error_Status, 892, sizeof(s_Hardware_Error_Status) - 1, 1}};\n#define COUNT_Gripper_ITEMS (sizeof(items_Gripper) / sizeof(items_Gripper[0]))\n\nstatic const ModelInfo info_Gripper = {0.01,\n                                       0,\n                                       0,\n                                       740,\n                                       0, \n                                       1.1345703125};\n\n//---------------------------------------------------------\n// Gripper A Firmware - (num == RH_P12_RN_A)\n//---------------------------------------------------------\nstatic const ControlItem items_EXTGripper[]{\n    {s_Model_Number, 0, sizeof(s_Model_Number) - 1, 2},\n    {s_Firmware_Version, 6, sizeof(s_Firmware_Version) - 1, 1},\n    {s_ID, 7, sizeof(s_ID) - 1, 1},\n    {s_Baud_Rate, 8, sizeof(s_Baud_Rate) - 1, 1},\n    {s_Return_Delay_Time, 9, sizeof(s_Return_Delay_Time) - 1, 1},\n    {s_Drive_Mode, 10, sizeof(s_Drive_Mode) - 1, 1},\n    {s_Operating_Mode, 11, sizeof(s_Operating_Mode) - 1, 1},\n    {s_Secondary_ID, 12, sizeof(s_Secondary_ID) - 1, 1},\n    {s_Homing_Offset, 20, sizeof(s_Homing_Offset) - 1, 4},\n    {s_Moving_Threshold, 24, sizeof(s_Moving_Threshold) - 1, 4},\n    {s_Temperature_Limit, 31, sizeof(s_Temperature_Limit) - 1, 1},\n    {s_Max_Voltage_Limit, 32, sizeof(s_Max_Voltage_Limit) - 1, 2},\n    {s_Min_Voltage_Limit, 34, sizeof(s_Min_Voltage_Limit) - 1, 2},\n    {s_PWM_Limit, 36, sizeof(s_PWM_Limit) - 1, 2},\n    {s_Current_Limit, 38, sizeof(s_Current_Limit) - 1, 2},\n    {s_Acceleration_Limit, 40, sizeof(s_Acceleration_Limit) - 1, 4},\n    {s_Velocity_Limit, 44, sizeof(s_Velocity_Limit) - 1, 4},\n    {s_Max_Position_Limit, 48, sizeof(s_Max_Position_Limit) - 1, 4},\n    {s_Min_Position_Limit, 52, sizeof(s_Min_Position_Limit) - 1, 4},\n    {s_External_Port_Mode_1, 56, sizeof(s_External_Port_Mode_1) - 1, 1},\n    {s_External_Port_Mode_2, 57, sizeof(s_External_Port_Mode_2) - 1, 1},\n    {s_External_Port_Mode_3, 58, sizeof(s_External_Port_Mode_3) - 1, 1},\n    {s_External_Port_Mode_4, 59, sizeof(s_External_Port_Mode_4) - 1, 1},\n    {s_Shutdown, 63, sizeof(s_Shutdown) - 1, 1},\n\n    {s_Torque_Enable, 512, sizeof(s_Torque_Enable) - 1, 1},\n    {s_LED_RED, 513, sizeof(s_LED_RED) - 1, 1},\n    {s_LED_GREEN, 514, sizeof(s_LED_GREEN) - 1, 1},\n    {s_LED_BLUE, 515, sizeof(s_LED_BLUE) - 1, 1},\n    {s_Status_Return_Level, 516, sizeof(s_Status_Return_Level) - 1, 1},\n    {s_Registered_Instruction, 517, sizeof(s_Registered_Instruction) - 1, 1},\n    {s_Hardware_Error_Status, 518, sizeof(s_Hardware_Error_Status) - 1, 1},\n    {s_Velocity_I_Gain, 524, sizeof(s_Velocity_I_Gain) - 1, 2},\n    {s_Velocity_P_Gain, 526, sizeof(s_Velocity_P_Gain) - 1, 2},\n    {s_Position_D_Gain, 528, sizeof(s_Position_D_Gain) - 1, 2},\n    {s_Position_I_Gain, 530, sizeof(s_Position_I_Gain) - 1, 2},\n    {s_Position_P_Gain, 532, sizeof(s_Position_P_Gain) - 1, 2},\n    {s_Feedforward_2nd_Gain, 536, sizeof(s_Feedforward_2nd_Gain) - 1, 2},\n    {s_Feedforward_1st_Gain, 538, sizeof(s_Feedforward_1st_Gain) - 1, 2},\n    {s_Bus_Watchdog, 546, sizeof(s_Bus_Watchdog) - 1, 1},\n    {s_Goal_PWM, 548, sizeof(s_Goal_PWM) - 1, 2},\n    {s_Goal_Current, 550, sizeof(s_Goal_Current) - 1, 2},\n    {s_Goal_Velocity, 552, sizeof(s_Goal_Velocity) - 1, 4},\n    {s_Profile_Acceleration, 556, sizeof(s_Profile_Acceleration) - 1, 4},\n    {s_Profile_Velocity, 560, sizeof(s_Profile_Velocity) - 1, 4},\n    {s_Goal_Position, 564, sizeof(s_Goal_Position) - 1, 4},    \n    {s_Realtime_Tick, 568, sizeof(s_Realtime_Tick) - 1, 2},\n    {s_Moving, 570, sizeof(s_Moving) - 1, 1},\n    {s_Moving_Status, 571, sizeof(s_Moving) - 1, 1},\n    {s_Present_PWM, 572, sizeof(s_Present_PWM) - 1, 2},\n    {s_Present_Current, 574, sizeof(s_Present_Current) - 1, 2},\n    {s_Present_Velocity, 576, sizeof(s_Present_Velocity) - 1, 4},\n    {s_Present_Position, 580, sizeof(s_Present_Position) - 1, 4},\n    {s_Velocity_Trajectory, 584, sizeof(s_Velocity_Trajectory) - 1, 4},\n    {s_Position_Trajectory, 588, sizeof(s_Position_Trajectory) - 1, 4},    \n    {s_Present_Input_Voltage, 592, sizeof(s_Present_Input_Voltage) - 1, 2},\n    {s_Present_Temperature, 594, sizeof(s_Present_Temperature) - 1, 1},\n    {s_External_Port_Mode_1, 600, sizeof(s_External_Port_Mode_1) - 1, 2},\n    {s_External_Port_Mode_2, 602, sizeof(s_External_Port_Mode_2) - 1, 2},\n    {s_External_Port_Mode_3, 604, sizeof(s_External_Port_Mode_3) - 1, 2},\n    {s_External_Port_Mode_4, 606, sizeof(s_External_Port_Mode_4) - 1, 2}};\n#define COUNT_EXTGripper_ITEMS (sizeof(items_EXTGripper) / sizeof(items_EXTGripper[0]))\n\nstatic const ModelInfo info_EXTGripper = {0.01,\n                                          0,\n                                          0,\n                                          740,\n                                          0, \n                                          1.1345703125};\n\n//=========================================================\n// Get Servo control table for the specified servo type\n//=========================================================\nstatic uint8_t the_number_of_item = 0;\nconst ControlItem *DynamixelItem::getControlTable(uint16_t model_number)\n{\n  uint16_t num = model_number;\n\n  const ControlItem *control_table;\n  if (num == AX_12A || num == AX_12W || num == AX_18A)\n  {\n    control_table = items_AX;\n    the_number_of_item = COUNT_AX_ITEMS;\n  }\n  else if (num == RX_10 || num == RX_24F || num == RX_28 || num == RX_64)\n  {\n    control_table = items_RX;\n    the_number_of_item = COUNT_RX_ITEMS;\n  }\n  else if (num == EX_106)\n  {\n    control_table = items_EX;\n    the_number_of_item = COUNT_EX_ITEMS;\n  }\n  else if (num == MX_12W || num == MX_28)\n  {\n    control_table = items_MX;\n    the_number_of_item = COUNT_MX_ITEMS;\n  }\n  else if (num == MX_64 || num == MX_106)\n  {\n    control_table = items_EXTMX;\n    the_number_of_item = COUNT_EXTMX_ITEMS;\n  }\n  else if (num == MX_28_2)\n  {\n    control_table = items_MX2;\n    the_number_of_item = COUNT_MX2_ITEMS;\n  }\n  else if (num == MX_64_2 || num == MX_106_2)\n  {\n    control_table = items_EXTMX2;\n    the_number_of_item = COUNT_EXTMX2_ITEMS;\n  }\n  else if (num == XL_320)\n  {\n    control_table = items_XL320;\n    the_number_of_item = COUNT_XL320_ITEMS;\n  }\n  else if (num == XL430_W250 || num == XL430_W250_2 || num == XC430_W150 || num == XC430_W240 || num == XC430_W250_2)\n  {\n    control_table = items_XL;\n    the_number_of_item = COUNT_XL_ITEMS;\n  }\n  else if (num == XM430_W210 || num == XM430_W350 || num == XL330_M077 || num == XL330_M288)\n  {\n    control_table = items_XM;\n    the_number_of_item = COUNT_XM_ITEMS;\n  }\n  else if (num == XM540_W150 || num == XM540_W270)\n  {\n    control_table = items_EXTXM;\n    the_number_of_item = COUNT_EXTXM_ITEMS;\n  }\n  else if (num == XH430_V210 || num == XH430_V350 || num == XH430_W210 || num == XH430_W350 || num == XW540_T140 || num == XW540_T260)\n  {\n    control_table = items_XH;\n    the_number_of_item = COUNT_XH_ITEMS;\n  }\n  else if (num == XH540_W150 || num == XH540_W270 || num == XH540_V150 || num == XH540_V270)\n  {\n    control_table = items_EXTXH;\n    the_number_of_item = COUNT_EXTXH_ITEMS;\n  }\n  else if (num == PRO_L42_10_S300_R)\n  {\n    control_table = items_PRO;\n    the_number_of_item = COUNT_PRO_ITEMS;\n  }\n  else if (num == PRO_L54_30_S400_R || num == PRO_L54_30_S500_R || num == PRO_L54_50_S290_R || num == PRO_L54_50_S500_R ||\n           num == PRO_M42_10_S260_R || num == PRO_M54_40_S250_R || num == PRO_M54_60_S250_R ||\n           num == PRO_H42_20_S300_R || num == PRO_H54_100_S500_R || num == PRO_H54_200_S500_R)\n  {\n    control_table = items_EXTPRO;\n    the_number_of_item = COUNT_EXTPRO_ITEMS;\n  }\n  else if (num == PRO_M42_10_S260_R_A || num == PRO_M54_40_S250_R_A  || num == PRO_M54_60_S250_R_A ||\n           num == PRO_H42_20_S300_R_A || num == PRO_H54_100_S500_R_A || num == PRO_H54_200_S500_R_A)\n  {\n    control_table = items_EXTPRO_A;\n    the_number_of_item = COUNT_EXTPRO_A_ITEMS;\n  }\n  else if (num == PRO_PLUS_H42P_020_S300_R || num == PRO_PLUS_H54P_100_S500_R || num == PRO_PLUS_H54P_200_S500_R ||\n           num == PRO_PLUS_M42P_010_S260_R || num == PRO_PLUS_M54P_040_S250_R || num == PRO_PLUS_M54P_060_S250_R)\n  {\n    control_table = items_PRO_PLUS;\n    the_number_of_item = COUNT_EXTPRO_PLUS_ITEMS;\n  }\n  else if (num == RH_P12_RN)\n  {\n    control_table = items_Gripper;\n    the_number_of_item = COUNT_Gripper_ITEMS;\n  }\n  else if (num == RH_P12_RN_A)\n  {\n    control_table = items_EXTGripper;\n    the_number_of_item = COUNT_EXTGripper_ITEMS;\n  }\n  else\n  {\n    control_table = NULL;\n    the_number_of_item = 0;\n  }\n\n  return control_table;\n}\n\nconst ModelInfo *DynamixelItem::getModelInfo(uint16_t model_number)\n{\n  uint16_t num = model_number;\n\n  const ModelInfo *info;\n\n  if (num == AX_12A || num == AX_12W || num == AX_18A)\n  {\n    info = &info_AX;\n  }\n  else if (num == RX_10 || num == RX_24F || num == RX_28 || num == RX_64)\n  {\n    info = &info_RX;\n  }\n  else if (num == EX_106)\n  {\n    info = &info_EX;\n  }\n  else if (num == MX_12W || num == MX_28)\n  {\n    info = &info_MX;\n  }\n  else if (num == MX_64 || num == MX_106)\n  {\n    info = &info_EXTMX;\n  }\n  else if (num == MX_28_2)\n  {\n    info = &info_MX2;\n  }\n  else if (num == MX_64_2 || num == MX_106_2)\n  {\n    info = &info_EXTMX2;\n  }\n  else if (num == XL_320)\n  {\n    info = &info_XL320;\n  }\n  else if (num == XL430_W250 || num == XL430_W250_2 || num == XC430_W150 || num == XC430_W240 || num == XC430_W250_2)\n  {\n    info = &info_XL;\n  }\n  else if (num == XM430_W210 || num == XM430_W350 || num == XL330_M077 || num == XL330_M288)\n  {\n    info = &info_XM;\n  }\n  else if (num == XM540_W150 || num == XM540_W270)\n  {\n    info = &info_EXTXM;\n  }\n  else if (num == XH430_V210 || num == XH430_V350 || num == XH430_W210 || num == XH430_W350 || num == XW540_T140 || num == XW540_T260)\n  {\n    info = &info_XH;\n  }\n  else if (num == XH540_W150 || num == XH540_W270 || num == XH540_V150 || num == XH540_V270)\n  {\n    info = &info_EXTXH;\n  }\n  else if (num == PRO_L42_10_S300_R)\n  {\n    info = &info_PRO;\n  } \n  else if (num == PRO_L54_30_S400_R)\n  {\n    info = &info_EXTPRO[0];\n  }\n  else if (num == PRO_L54_30_S500_R || num == PRO_L54_50_S500_R)\n  {\n    info = &info_EXTPRO[1];\n  }\n  else if (num == PRO_L54_50_S290_R)\n  {\n    info = &info_EXTPRO[2];\n  }\n  else if (num == PRO_M42_10_S260_R)\n  {\n    info = &info_EXTPRO[3];\n  }\n  else if (num == PRO_M54_40_S250_R || num == PRO_M54_60_S250_R)\n  {\n    info = &info_EXTPRO[4];\n  }\n  else if (num == PRO_H42_20_S300_R)\n  {\n    info = &info_EXTPRO[5];\n  }\n  else if (num == PRO_H54_100_S500_R || num == PRO_H54_200_S500_R)\n  { \n    info = &info_EXTPRO[6];\n  }\n  else if (num == PRO_M42_10_S260_R_A)\n  {\n    info = &info_EXTPRO_A[0];\n  }\n  else if (num == PRO_M54_40_S250_R_A || num == PRO_M54_60_S250_R_A)\n  {\n    info = &info_EXTPRO_A[1];\n  }\n  else if (num == PRO_H42_20_S300_R_A)\n  {\n    info = &info_EXTPRO_A[2];\n  }\n  else if (num == PRO_H54_100_S500_R_A || num == PRO_H54_200_S500_R_A)\n  { \n    info = &info_EXTPRO_A[3];\n  }\n  else if (num == PRO_PLUS_H42P_020_S300_R)\n  { \n    info = &info_PRO_PLUS[0];\n  }\n  else if (num == PRO_PLUS_H54P_100_S500_R)\n  { \n    info = &info_PRO_PLUS[1];\n  }\n  else if (num == PRO_PLUS_H54P_200_S500_R)\n  { \n    info = &info_PRO_PLUS[2];\n  }\n  else if (num == PRO_PLUS_M42P_010_S260_R)\n  { \n    info = &info_PRO_PLUS[3];\n  }\n  else if (num == PRO_PLUS_M54P_040_S250_R)\n  { \n    info = &info_PRO_PLUS[4];\n  }\n  else if (num == PRO_PLUS_M54P_060_S250_R)\n  { \n    info = &info_PRO_PLUS[5];\n  }\n  else if (num == RH_P12_RN)\n  {\n    info = &info_Gripper;\n  } \n  else if (num == RH_P12_RN_A)\n  {\n    info = &info_EXTGripper;\n  }\n  else\n  {\n    info = NULL;\n  }\n\n  return info;\n}\n\nuint8_t DynamixelItem::getTheNumberOfControlItem()\n{\n  return the_number_of_item;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelWorkbench/src/dynamixel_workbench_toolbox/dynamixel_tool.cpp",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Taehun Lim (Darby), Ryan Shim */\n\n#include \"../../include/dynamixel_workbench_toolbox/dynamixel_tool.h\"\n\n//===================================================================\n// Define Serial ID to Namd table\n//===================================================================\ntypedef struct \n{\n  uint16_t      number;\n  const char*   name; \n} DynamixelModel;\n\nstatic const DynamixelModel dynamixel_model_table[] = {\n    {AX_12A, \"AX-12A\"},\n    {AX_12W, \"AX-12W\"},\n    {AX_18A, \"AX-18A\"},\n\n    {RX_10, \"RX-10\"},\n    {RX_24F, \"RX-24F\"},\n    {RX_28, \"RX-28\"},\n    {RX_64, \"RX-64\"},\n\n    {EX_106, \"EX-106\"},\n\n    {MX_12W, \"MX-12W\"},\n    {MX_28, \"MX-28\"},\n    {MX_28_2, \"MX-28-2\"},\n    {MX_64, \"MX-64\"},\n    {MX_64_2, \"MX-64-2\"},\n    {MX_106, \"MX-106\"},\n    {MX_106_2, \"MX-106-2\"},\n\n    {XL_320, \"XL-320\"},\n    {XL430_W250, \"XL430-W250\"},\n    {XL330_M077, \"XL330-M077\"},\n    {XL330_M288, \"XL330-M288\"},\n\n    {XL430_W250_2, \"XL430-W250-2\"}, // 2XL\n    {XC430_W250_2, \"XC430-W240-2\"}, // 2XC\n\n    {XC430_W150, \"XC430-W150\"},\n    {XC430_W240, \"XC430-W240\"},\n\n    {XM430_W210, \"XM430-W210\"},\n    {XM430_W350, \"XM430-W350\"},\n    \n    {XM540_W150, \"XM540-W150\"},\n    {XM540_W270, \"XM540-W270\"},\n\n    {XH430_V210, \"XH430-V210\"},\n    {XH430_V350, \"XH430-V350\"},\n    {XH430_W210, \"XH430-W210\"},\n    {XH430_W350, \"XH430-W350\"},\n\n    {XH540_W150, \"XH540-W150\"},\n    {XH540_W270, \"XH540-W270\"},\n    {XH540_V150, \"XH540-V150\"},\n    {XH540_V270, \"XH540-V270\"},\n\n    {XW540_T140, \"XW540-T140\"},\n    {XW540_T260, \"XW540-T260\"},\n\n    {PRO_L42_10_S300_R, \"PRO-L42-10-S300-R\"},\n    {PRO_L54_30_S400_R, \"PRO-L54-30-S400-R\"},\n    {PRO_L54_30_S500_R, \"PRO-L54-30-S500-R\"},\n    {PRO_L54_50_S290_R, \"PRO-L54-50-S290-R\"},\n    {PRO_L54_50_S500_R, \"PRO-L54-50-S500-R\"},\n\n    {PRO_M42_10_S260_R, \"PRO-M42-10-S260-R\"},\n    {PRO_M54_40_S250_R, \"PRO-M54-40-S250-R\"},\n    {PRO_M54_60_S250_R, \"PRO-M54-60-S250-R\"},\n\n    {PRO_H42_20_S300_R,  \"PRO-H42-20-S300-R\"},\n    {PRO_H54_100_S500_R, \"PRO-H54-100-S500-R\"},\n    {PRO_H54_200_S500_R, \"PRO-H54-200-S500-R\"},\n\n    {PRO_M42_10_S260_R_A, \"PRO-M42-10-S260-R-A\"},\n    {PRO_M54_40_S250_R_A, \"PRO-M54-40-S250-R-A\"},\n    {PRO_M54_60_S250_R_A, \"PRO-M54-60-S250-R-A\"},\n\n    {PRO_H42_20_S300_R_A,  \"PRO-H42-20-S300-R-A\"},\n    {PRO_H54_100_S500_R_A, \"PRO-H54-100-S500-R-A\"},\n    {PRO_H54_200_S500_R_A, \"PRO-H54-200-S500-R-A\"},\n\n    {PRO_PLUS_M42P_010_S260_R, \"PRO-PLUS-M42P-010-S260-R\"},\n    {PRO_PLUS_M54P_040_S250_R, \"PRO-PLUS-M54P-040-S250-R\"},\n    {PRO_PLUS_M54P_060_S250_R, \"PRO-PLUS-M54P-060-S250-R\"},\n\n    {PRO_PLUS_H42P_020_S300_R, \"PRO-PLUS-H42P-020-S300-R\"},\n    {PRO_PLUS_H54P_100_S500_R, \"PRO-PLUS-H54P-100-S500-R\"},\n    {PRO_PLUS_H54P_200_S500_R, \"PRO-PLUS-H54P-200-S500-R\"},\n\n    {RH_P12_RN, \"RH-P12-RN\"},\n\n    {RH_P12_RN_A, \"RH-P12-RN-A\"}\n};\n#define COUNT_DYNAMIXEL_MODEL  (sizeof(dynamixel_model_table)/sizeof(dynamixel_model_table[0]))\n\nDynamixelTool::DynamixelTool() : dxl_cnt_(0), the_number_of_control_item_(0){}\n\nDynamixelTool::~DynamixelTool(){}\n\nvoid DynamixelTool::initTool(void)\n{\n  for (uint8_t i = 0; i < DYNAMIXEL_BUFFER; i++)\n    dxl_id_[i] = 0;\n\n  dxl_cnt_ = 0;\n}\n\nbool DynamixelTool::addTool(const char *model_name, uint8_t id, const char **log)\n{\n  bool result = false;\n  initTool();\n\n  model_name_ = model_name;\n  result = setModelNumber(model_name, log);\n  if (result == false) return false;\n  dxl_id_[dxl_cnt_++] = id;\n\n  result = setControlTable(model_name, log);\n  if (result == false) return false;\n\n  return true;\n}\n\nbool DynamixelTool::addTool(uint16_t model_number, uint8_t id, const char **log)\n{\n  bool result = false;\n  initTool();\n\n  result = setModelName(model_number, log);\n  if (result == false) return false;\n  model_number_ = model_number;\n  dxl_id_[dxl_cnt_++] = id;\n\n  result = setControlTable(model_number, log);\n  if (result == false) return false;\n\n  return result;\n}\n\nvoid DynamixelTool::addDXL(uint8_t id)\n{\n  dxl_id_[dxl_cnt_++] = id;\n}\n\nbool DynamixelTool::setControlTable(const char *model_name, const char **log)\n{  \n  const char* name = model_name;\n  uint8_t name_length = strlen(name);\n\n  for (uint8_t index=0; index < COUNT_DYNAMIXEL_MODEL; index++)\n  {\n    if(strncmp(name, dynamixel_model_table[index].name, name_length) == 0)\n    {\n      return setControlTable(dynamixel_model_table[index].number, log);\n    }\n  }\n\n  if (log != NULL)\n    *log = \"[DynamixelTool] Failed to set control table due to mismatch model name and model number\";\n  return false;\n}\n\nbool DynamixelTool::setControlTable(uint16_t model_number, const char **log)\n{\n  control_table_              = DynamixelItem::getControlTable(model_number);\n  the_number_of_control_item_ = DynamixelItem::getTheNumberOfControlItem();\n  model_info_                 = DynamixelItem::getModelInfo(model_number);\n\n  if (control_table_ == NULL || model_info_ == NULL)\n  {\n    if (log != NULL)\n      *log = \"[DynamixelTool] Failed to get control table or model info\";\n    return false;\n  }\n\n  return true;\n}\n\nbool DynamixelTool::setModelName(uint16_t model_number, const char **log)\n{\n  uint16_t num = model_number;\n\n  for (uint8_t index=0; index < COUNT_DYNAMIXEL_MODEL; index++)\n  {\n    if (num == dynamixel_model_table[index].number)\n    {\n      model_name_ = dynamixel_model_table[index].name;\n      return true;\n    }\n  }\n\n  if (log != NULL)\n    *log = \"[DynamixelTool] Failed to find model name\";\n  return false;\n}\n\nbool DynamixelTool::setModelNumber(const char *model_name, const char **log)\n{\n  const char* name = model_name;\n  uint8_t name_length = strlen(name);\n\n  for (uint8_t index=0; index < COUNT_DYNAMIXEL_MODEL; index++)\n  {\n    if(strncmp(name, model_name_, name_length) == 0)\n    {\n      model_number_ = dynamixel_model_table[index].number;\n      return true;\n    }\n  }\n\n  if (log != NULL)\n    *log = \"[DynamixelTool] Failed to find model number\";\n  return false;\n}\n\nconst char* DynamixelTool::getModelName(void)\n{\n  return model_name_;\n}\n\nuint16_t DynamixelTool::getModelNumber(void)\n{\n  return model_number_;\n}\n\nconst uint8_t* DynamixelTool::getID(void)\n{\n  const uint8_t* id_table_ = dxl_id_;\n\n  return id_table_;\n}\n\nuint8_t DynamixelTool::getDynamixelCount(void)\n{\n  return dxl_cnt_;\n}\n\nuint8_t DynamixelTool::getDynamixelBuffer(void)\n{\n  return DYNAMIXEL_BUFFER;\n}\n\nfloat DynamixelTool::getRPM(void)\n{\n  return model_info_->rpm;\n}\n\nint64_t DynamixelTool::getValueOfMinRadianPosition(void)\n{\n  return model_info_->value_of_min_radian_position;\n}\n\nint64_t DynamixelTool::getValueOfMaxRadianPosition(void)\n{\n  return model_info_->value_of_max_radian_position;\n}\n\nint64_t DynamixelTool::getValueOfZeroRadianPosition(void)\n{\n  return model_info_->value_of_zero_radian_position;\n}\n\nfloat DynamixelTool::getMinRadian(void)\n{\n  return model_info_->min_radian;\n}\n\nfloat DynamixelTool::getMaxRadian(void)\n{\n  return model_info_->max_radian;\n}\n\nuint8_t DynamixelTool::getTheNumberOfControlItem(void)\n{\n  return the_number_of_control_item_;\n}\n\nconst ControlItem *DynamixelTool::getControlItem(const char *item_name, const char **log)\n{\n  const ControlItem* control_item = control_table_;  \n  uint8_t name_length = strlen(item_name);\n\n  for (uint8_t num = 0; num < the_number_of_control_item_; num++)\n  {\n    if ((name_length == control_item->item_name_length) && \n        (memcmp(item_name, control_item->item_name, name_length) == 0))\n    {\n      return control_item;\n    }\n    control_item++;\n  }\n\n  if (log != NULL)\n    *log = \"[DynamixelTool] Can't find Item\";\n  return NULL;\n}\n\nconst ControlItem *DynamixelTool::getControlTable(void)\n{\n  return control_table_;\n}\n\nconst ModelInfo *DynamixelTool::getModelInfo(void)\n{\n  return model_info_;\n}\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/DynamixelWorkbench/src/dynamixel_workbench_toolbox/dynamixel_workbench.cpp",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Taehun Lim (Darby), Ryan Shim */\n\n#include \"../../include/dynamixel_workbench_toolbox/dynamixel_workbench.h\"\n\nstatic const uint8_t WHEEL_MODE = 1;\nstatic const uint8_t JOINT_MODE = 2;\n\nstatic const uint8_t CURRENT_CONTROL_MODE                  = 0;\nstatic const uint8_t VELOCITY_CONTROL_MODE                 = 1;\nstatic const uint8_t POSITION_CONTROL_MODE                 = 3;\nstatic const uint8_t EXTENDED_POSITION_CONTROL_MODE        = 4;\nstatic const uint8_t CURRENT_BASED_POSITION_CONTROL_MODE   = 5;\nstatic const uint8_t PWM_CONTROL_MODE                      = 16;\nstatic const uint8_t TORQUE_CONTROL_MODE                   = 100;\nstatic const uint8_t MULTI_TURN_MODE                       = 101;\n\nstatic const char* model_name = NULL;\nstatic const ModelInfo* model_info = NULL;\n\nDynamixelWorkbench::DynamixelWorkbench(){}\n\nDynamixelWorkbench::~DynamixelWorkbench(){}\n\nbool DynamixelWorkbench::torque(uint8_t id, int32_t onoff, const char **log)\n{\n  bool result = false;\n\n  result = itemWrite(id, \"Torque_Enable\", (int32_t)onoff, log);\n  if (result == false)\n  {\n    if (log != NULL) *log = \"[DynamixelWorkbench] Failed to change torque status!\";\n    return false;\n  }\n\n  if (log != NULL) *log = \"[DynamixelWorkbench] Succeeded to change torque status!\";\n  return result;\n}\n\nbool DynamixelWorkbench::torqueOn(uint8_t id, const char **log)\n{\n  bool result = false;\n\n  result = torque(id, 1, log);\n\n  return result;\n}\n\nbool DynamixelWorkbench::torqueOff(uint8_t id, const char **log)\n{\n  bool result = false;\n\n  result = torque(id, 0, log);\n\n  return result;\n}\n\nbool DynamixelWorkbench::changeID(uint8_t id, uint8_t new_id, const char **log)\n{\n  bool result = false;\n\n  result = torqueOff(id, log);\n  if (result == false) return false;\n\n  result = writeRegister(id, \"ID\", new_id, log);\n  if (result == false) \n  {\n    if (log != NULL) *log = \"[DynamixelWorkbench] Failed to change ID!\";\n    return false;\n  }\n  // millis(1000);\n\n  if (log != NULL) *log = \"[DynamixelWorkbench] Succeeded to change ID!\";\n  return result;\n}\n\nbool DynamixelWorkbench::changeBaudrate(uint8_t id, uint32_t new_baudrate, const char **log)\n{\n  bool result = false;\n\n  result = torqueOff(id, log);\n  if (result == false) return false;\n\n  if (getProtocolVersion() == 1.0f)\n  {\n    switch (new_baudrate)\n    {\n      case 9600:\n        result = writeRegister(id, \"Baud_Rate\", 207, log);\n       break;\n\n      case 19200:\n        result = writeRegister(id, \"Baud_Rate\", 103, log);\n       break;\n\n      case 57600:\n        result = writeRegister(id, \"Baud_Rate\", 34, log);\n       break;\n\n      case 115200:\n        result = writeRegister(id, \"Baud_Rate\", 16, log);\n       break;\n\n      case 200000:\n        result = writeRegister(id, \"Baud_Rate\", 9, log);    \n       break;\n\n      case 250000:\n        result = writeRegister(id, \"Baud_Rate\", 7, log);       \n       break;\n       \n      case 400000:\n        result = writeRegister(id, \"Baud_Rate\", 4, log);       \n       break;\n\n      case 500000:\n        result = writeRegister(id, \"Baud_Rate\", 3, log);       \n       break;\n\n      case 1000000:\n        result = writeRegister(id, \"Baud_Rate\", 1, log);       \n       break;\n\n      case 2250000:\n        result = writeRegister(id, \"Baud_Rate\", 250, log);       \n       break;\n\n      case 2500000:\n        result = writeRegister(id, \"Baud_Rate\", 251, log);       \n       break;\n\n      case 3000000:\n        result = writeRegister(id, \"Baud_Rate\", 252, log);       \n       break;\n       \n      default:\n        result = writeRegister(id, \"Baud_Rate\", 34, log);\n       break;\n    }\n  }\n  else if (getProtocolVersion() == 2.0f)\n  {    \n    switch (new_baudrate)\n    {\n      case 9600:\n        result = writeRegister(id, \"Baud_Rate\", 0, log);       \n       break;\n\n      case 57600:\n        result = writeRegister(id, \"Baud_Rate\", 1, log);       \n       break;\n\n      case 115200:\n        result = writeRegister(id, \"Baud_Rate\", 2, log);       \n       break;\n\n      case 1000000:\n        result = writeRegister(id, \"Baud_Rate\", 3, log);       \n       break;\n\n      case 2000000:\n        result = writeRegister(id, \"Baud_Rate\", 4, log);       \n       break;\n\n      case 3000000:\n        result = writeRegister(id, \"Baud_Rate\", 5, log);       \n       break;\n       \n      case 4000000:\n        result = writeRegister(id, \"Baud_Rate\", 6, log);       \n       break;\n\n      case 4500000:\n        result = writeRegister(id, \"Baud_Rate\", 7, log);       \n       break;\n\n      case 10500000:\n        result = writeRegister(id, \"Baud_Rate\", 8, log);       \n       break;\n       \n      default:\n        result = writeRegister(id, \"Baud_Rate\", 1, log);       \n       break;\n    }\n  }\n#if defined(__OPENCR__) || defined(__OPENCM904__)\n    delay(2000);\n#else\n    usleep(1000*2000);\n#endif\n\n  if (result == false)\n  {\n    if (log != NULL) *log = \"[DynamixelWorkbench] Failed to change Baud Rate!\";\n    return result; \n  } \n\n  if (log != NULL) *log = \"[DynamixelWorkbench] Succeeded to change Baud Rate!\";\n  return result;\n}\n\nbool DynamixelWorkbench::changeProtocolVersion(uint8_t id, uint8_t version, const char **log)\n{\n  bool result = false;\n\n  model_name = getModelName(id, log);\n  if (model_name == NULL) return false;\n\n  if (!strncmp(model_name, \"MX-28-2\", strlen(\"MX-28-2\"))   ||\n      !strncmp(model_name, \"MX-64-2\", strlen(\"MX-64-2\"))   ||\n      !strncmp(model_name, \"MX-106-2\", strlen(\"MX-106-2\")) ||\n      !strncmp(model_name, \"XM\", strlen(\"XM\"))             ||\n      !strncmp(model_name, \"XL430\", strlen(\"XL430\"))       ||\n      !strncmp(model_name, \"XC430\", strlen(\"XC430\"))       ||\n      !strncmp(model_name, \"XH\", strlen(\"XH\")))\n  {    \n    result = writeRegister(id, \"Protocol_Version\", version, log);\n    if (result == false)\n    {\n      if (log != NULL) *log = \"[DynamixelWorkbench] Failed to set protocol version!\";\n      return false;\n    }\n  }\n\n  result = setPacketHandler((float)version, log);\n  \n  if (log != NULL) *log = \"[DynamixelWorkbench] Succeeded to set protocol version!\";\n  return result;\n}\n\nbool DynamixelWorkbench::itemWrite(uint8_t id, const char *item_name, int32_t data, const char **log)\n{\n  return writeRegister(id, item_name, data, log);\n}\n\nbool DynamixelWorkbench::itemRead(uint8_t id, const char *item_name, int32_t *data, const char **log)\n{\n  return readRegister(id, item_name, data, log);\n}\n\nbool DynamixelWorkbench::led(uint8_t id, int32_t onoff, const char **log)\n{\n  bool result = false;\n\n  result = writeRegister(id, \"LED\", onoff, log);\n  if (result == false)\n  {\n    if (log != NULL) *log = \"[DynamixelWorkbench] Failed to change led status!\";\n    return false;\n  }\n\n  if (log != NULL) *log = \"[DynamixelWorkbench] Succeeded to change led status!\";\n  return result;\n}\n\nbool DynamixelWorkbench::ledOn(uint8_t id, const char **log)\n{\n  bool result = false;\n\n  result = led(id, 1, log);\n\n  return result;\n}\n\nbool DynamixelWorkbench::ledOff(uint8_t id, const char **log)\n{\n  bool result = false;\n\n  result = led(id, 0, log);\n\n  return result;\n}\n\nbool DynamixelWorkbench::setNormalDirection(uint8_t id, const char **log)\n{\n  bool result = false;\n  int32_t data = 0;\n\n  model_name = getModelName(id, log);\n  if (model_name == NULL) return false;\n\n  if (!strncmp(model_name, \"MX-28-2\", strlen(\"MX-28-2\"))   ||\n      !strncmp(model_name, \"MX-64-2\", strlen(\"MX-64-2\"))   ||\n      !strncmp(model_name, \"MX-106-2\", strlen(\"MX-106-2\")) ||\n      !strncmp(model_name, \"XM\", strlen(\"XM\"))             ||\n      !strncmp(model_name, \"XL330\", strlen(\"XL330\"))       ||\n      !strncmp(model_name, \"XL430\", strlen(\"XL430\"))       ||\n      !strncmp(model_name, \"XC430\", strlen(\"XC430\"))       ||\n      !strncmp(model_name, \"XH\", strlen(\"XH\"))             ||\n      !strncmp(model_name, \"XW\", strlen(\"XW\")))\n  {    \n    result = readRegister(id, \"Drive_Mode\", &data, log);\n    \n    data = data & 0b00000100;\n    result = writeRegister(id, \"Drive_Mode\", data, log);\n    if (result == false)\n    {\n      if (log != NULL) *log = \"[DynamixelWorkbench] Failed to set normal direction!\";\n      return false;\n    }\n  }\n\n  if (log != NULL) *log = \"[DynamixelWorkbench] Succeeded to set normal direction!\";\n  return result;\n}\n\nbool DynamixelWorkbench::setReverseDirection(uint8_t id, const char **log)\n{\n  bool result = false;\n  int32_t data = 0;\n\n  model_name = getModelName(id, log);\n  if (model_name == NULL) return false;\n\n  if (!strncmp(model_name, \"MX-28-2\", strlen(\"MX-28-2\"))   ||\n      !strncmp(model_name, \"MX-64-2\", strlen(\"MX-64-2\"))   ||\n      !strncmp(model_name, \"MX-106-2\", strlen(\"MX-106-2\")) ||\n      !strncmp(model_name, \"XM\", strlen(\"XM\"))             ||\n      !strncmp(model_name, \"XL330\", strlen(\"XL330\"))       ||\n      !strncmp(model_name, \"XL430\", strlen(\"XL430\"))       ||\n      !strncmp(model_name, \"XC430\", strlen(\"XC430\"))       ||\n      !strncmp(model_name, \"XH\", strlen(\"XH\"))             ||\n      !strncmp(model_name, \"XW\", strlen(\"XW\")))\n  {\n    result = readRegister(id, \"Drive_Mode\", &data, log);\n    \n    data = data | 0b00000001;\n    result = writeRegister(id, \"Drive_Mode\", data, log);\n    if (result == false)\n    {\n      if (log != NULL) *log = \"[DynamixelWorkbench] Failed to set reverse direction!\";\n      return false;\n    }\n  }\n\n  if (log != NULL) *log = \"[DynamixelWorkbench] Succeeded to set reverse direction!\";\n  return result;\n}\n\nbool DynamixelWorkbench::setVelocityBasedProfile(uint8_t id, const char **log)\n{\n  bool result = false;\n  int32_t data = 0;\n\n  model_name = getModelName(id, log);\n  if (model_name == NULL) return false;\n\n  if (!strncmp(model_name, \"MX-28-2\", strlen(\"MX-28-2\"))   ||\n      !strncmp(model_name, \"MX-64-2\", strlen(\"MX-64-2\"))   ||\n      !strncmp(model_name, \"MX-106-2\", strlen(\"MX-106-2\")) ||\n      !strncmp(model_name, \"XM\", strlen(\"XM\"))             ||\n      !strncmp(model_name, \"XL330\", strlen(\"XL330\"))       ||\n      !strncmp(model_name, \"XL430\", strlen(\"XL430\"))       ||\n      !strncmp(model_name, \"XC430\", strlen(\"XC430\"))       ||\n      !strncmp(model_name, \"XH\", strlen(\"XH\"))             ||\n      !strncmp(model_name, \"XW\", strlen(\"XW\")))\n  {\n    result = readRegister(id, \"Drive_Mode\", &data, log);\n    \n    data = data & 0b00000001;\n    result = writeRegister(id, \"Drive_Mode\", data, log);\n    if (result == false)\n    {\n      if (log != NULL) *log = \"[DynamixelWorkbench] Failed to set velocity based profile!\";\n      return false;\n    }\n  }\n\n  if (log != NULL) *log = \"[DynamixelWorkbench] Succeeded to set velocity based profile!\";\n  return result;\n}\n\nbool DynamixelWorkbench::setTimeBasedProfile(uint8_t id, const char **log)\n{\n  bool result = false;\n  int32_t data = 0;\n\n  model_name = getModelName(id, log);\n  if (model_name == NULL) return false;\n\n  if (!strncmp(model_name, \"MX-28-2\", strlen(\"MX-28-2\"))   ||\n      !strncmp(model_name, \"MX-64-2\", strlen(\"MX-64-2\"))   ||\n      !strncmp(model_name, \"MX-106-2\", strlen(\"MX-106-2\")) ||\n      !strncmp(model_name, \"XM\", strlen(\"XM\"))             ||\n      !strncmp(model_name, \"XL330\", strlen(\"XL330\"))       ||\n      !strncmp(model_name, \"XL430\", strlen(\"XL430\"))       ||\n      !strncmp(model_name, \"XC430\", strlen(\"XC430\"))       ||\n      !strncmp(model_name, \"XH\", strlen(\"XH\"))             ||\n      !strncmp(model_name, \"XW\", strlen(\"XW\")))\n  {\n    result = readRegister(id, \"Drive_Mode\", &data, log);\n    \n    data = data | 0b00000100;\n    result = writeRegister(id, \"Drive_Mode\", data, log);\n    if (result == false)\n    {\n      if (log != NULL) *log = \"[DynamixelWorkbench] Failed to set time based profile!\";\n      return false;\n    }\n  }\n\n  if (log != NULL) *log = \"[DynamixelWorkbench] Succeeded to set time based profile!\";\n  return result;\n}\n\nbool DynamixelWorkbench::setSecondaryID(uint8_t id, uint8_t secondary_id, const char **log)\n{\n  bool result = false;\n\n  model_name = getModelName(id, log);\n  if (model_name == NULL) return false;\n\n  if (!strncmp(model_name, \"MX-28-2\", strlen(\"MX-28-2\"))   ||\n      !strncmp(model_name, \"MX-64-2\", strlen(\"MX-64-2\"))   ||\n      !strncmp(model_name, \"MX-106-2\", strlen(\"MX-106-2\")) ||\n      !strncmp(model_name, \"XM\", strlen(\"XM\"))             ||\n      !strncmp(model_name, \"XL330\", strlen(\"XL330\"))       ||\n      !strncmp(model_name, \"XL430\", strlen(\"XL430\"))       ||\n      !strncmp(model_name, \"XC430\", strlen(\"XC430\"))       ||\n      !strncmp(model_name, \"XH\", strlen(\"XH\"))             ||\n      !strncmp(model_name, \"RH\", strlen(\"RH\"))             ||\n      !strncmp(model_name, \"XW\", strlen(\"XW\")))\n  {\n    result = torqueOff(id, log);\n    if (result == false) return false;\n\n    result = writeRegister(id, \"Secondary_ID\", secondary_id, log);\n    if (result == false) \n    {\n      if (log != NULL) *log = \"[DynamixelWorkbench] Failed to set secondary ID!\";\n      return false;\n    }\n  }\n\n  // millis(1000);\n\n  if (log != NULL) *log = \"[DynamixelWorkbench] Succeeded to set secondary ID!\";\n  return result;\n}\n\nbool DynamixelWorkbench::setPositionControlMode(uint8_t id, const char **log)\n{\n  bool result = false;\n\n  result = setOperatingMode(id, POSITION_CONTROL_MODE, log);\n\n  if (result == false)\n  {\n    if (log != NULL) *log = \"[DynamixelWorkbench] Failed to set Position Control Mode!\";\n    return false;\n  }\n\n  if (log != NULL) *log = \"[DynamixelWorkbench] Succeeded to set Position Control Mode!\";\n  return result;\n}\n\nbool DynamixelWorkbench::setVelocityControlMode(uint8_t id, const char **log)\n{\n  bool result = false;\n\n  result = setOperatingMode(id, VELOCITY_CONTROL_MODE, log);\n\n  if (result == false)\n  {\n    if (log != NULL) *log = \"[DynamixelWorkbench] Failed to set Velocity Control Mode!\";\n    return false;\n  }\n\n  if (log != NULL) *log = \"[DynamixelWorkbench] Succeeded to set Velocity Control Mode!\";\n  return result;\n}\n\nbool DynamixelWorkbench::setCurrentControlMode(uint8_t id, const char **log)\n{\n  bool result = false;\n\n  result = setOperatingMode(id, CURRENT_CONTROL_MODE, log);\n\n  if (result == false)\n  {\n    if (log != NULL) *log = \"[DynamixelWorkbench] Failed to set Current Control Mode!\";\n    return false;\n  }\n\n  if (log != NULL) *log = \"[DynamixelWorkbench] Succeeded to set Current Control Mode!\";\n  return result;\n}\n\nbool DynamixelWorkbench::setTorqueControlMode(uint8_t id, const char **log)\n{\n  bool result = false;\n\n  result = setOperatingMode(id, TORQUE_CONTROL_MODE, log);\n\n  if (result == false)\n  {\n    if (log != NULL) *log = \"[DynamixelWorkbench] Failed to set Torque Control Mode!\";\n    return false;\n  }\n\n  if (log != NULL) *log = \"[DynamixelWorkbench] Succeeded to set Torque Control Mode!\";\n  return result;\n}\n\nbool DynamixelWorkbench::setExtendedPositionControlMode(uint8_t id, const char **log)\n{\n  bool result = false;\n\n  result = setOperatingMode(id, EXTENDED_POSITION_CONTROL_MODE, log);\n\n  if (result == false)\n  {\n    if (log != NULL) *log = \"[DynamixelWorkbench] Failed to set Extended Position Control Mode!\";\n    return false;\n  }\n\n  if (log != NULL) *log = \"[DynamixelWorkbench] Succeeded to set Extended Position Control Mode!\";\n  return result;\n}\n\nbool DynamixelWorkbench::setMultiTurnControlMode(uint8_t id, const char **log)\n{\n  bool result = false;\n\n  result = setOperatingMode(id, MULTI_TURN_MODE, log);\n\n  if (result == false)\n  {\n    if (log != NULL) *log = \"[DynamixelWorkbench] Failed to set Multi-Turn Control Mode!\";\n    return false;\n  }\n\n  if (log != NULL) *log = \"[DynamixelWorkbench] Succeeded to set Multi-Turn Control Mode!\";\n  return result;\n}\n\nbool DynamixelWorkbench::setCurrentBasedPositionControlMode(uint8_t id, const char **log)\n{\n  bool result = false;\n\n  result = setOperatingMode(id, CURRENT_BASED_POSITION_CONTROL_MODE, log);\n\n  if (result == false)\n  {\n    if (log != NULL) *log = \"[DynamixelWorkbench] Failed to set Current Based Position Control Mode!\";\n    return false;\n  }\n\n  if (log != NULL) *log = \"[DynamixelWorkbench] Succeeded to set Current Based Position Control Mode!\";\n  return result;\n}\n\nbool DynamixelWorkbench::setPWMControlMode(uint8_t id, const char **log)\n{\n  bool result = false;\n\n  result = setOperatingMode(id, PWM_CONTROL_MODE, log);\n\n  if (result == false)\n  {\n    if (log != NULL) *log = \"[DynamixelWorkbench] Failed to set PWM Control Mode!\";\n    return false;\n  }\n\n  if (log != NULL) *log = \"[DynamixelWorkbench] Succeeded to set PWM Control Mode!\";\n  return result;\n}\n\nbool DynamixelWorkbench::setOperatingMode(uint8_t id, uint8_t index, const char **log)\n{\n  bool result = false;\n\n  model_name = getModelName(id, log);\n  if (model_name == NULL) return false;\n\n  if (getProtocolVersion() == 1.0)\n  {\n    if (index == POSITION_CONTROL_MODE)\n    {\n      if (!strncmp(model_name, \"MX-28-2\", strlen(\"MX-28-2\"))   ||\n          !strncmp(model_name, \"MX-64-2\", strlen(\"MX-64-2\"))   ||\n          !strncmp(model_name, \"MX-106-2\", strlen(\"MX-106-2\")) ||\n          !strncmp(model_name, \"XL330\", strlen(\"XL330\"))       ||\n          !strncmp(model_name, \"XL430\", strlen(\"XL430\"))       ||\n          !strncmp(model_name, \"XC430\", strlen(\"XC430\"))       ||\n          !strncmp(model_name, \"XM\", strlen(\"XM\"))             ||\n          !strncmp(model_name, \"XH\", strlen(\"XH\"))             ||\n          !strncmp(model_name, \"XW\", strlen(\"XW\"))             ||\n          !strncmp(model_name, \"PRO\", strlen(\"PRO\"))           ||\n          !strncmp(model_name, \"RH\", strlen(\"RH\")))\n      {\n        result = writeRegister(id, \"Operating_Mode\", POSITION_CONTROL_MODE, log);\n      }\n      else if (!strncmp(model_name, \"AX\", 2) || !strncmp(model_name, \"RX\", 2))\n      {\n        result = writeRegister(id, \"CW_Angle_Limit\", 0, log);\n        result = writeRegister(id, \"CCW_Angle_Limit\", 1023, log);\n      }\n      else\n      {\n        result = writeRegister(id, \"CW_Angle_Limit\", 0, log);\n        result = writeRegister(id, \"CCW_Angle_Limit\", 4095, log);\n      }\n    }\n    else if (index == VELOCITY_CONTROL_MODE)\n    {\n      if (!strncmp(model_name, \"MX-28-2\", strlen(\"MX-28-2\"))   ||\n          !strncmp(model_name, \"MX-64-2\", strlen(\"MX-64-2\"))   ||\n          !strncmp(model_name, \"MX-106-2\", strlen(\"MX-106-2\")) ||\n          !strncmp(model_name, \"XL330\", strlen(\"XL330\"))       ||\n          !strncmp(model_name, \"XL430\", strlen(\"XL430\"))       ||\n          !strncmp(model_name, \"XC430\", strlen(\"XC430\"))       ||\n          !strncmp(model_name, \"XM\", strlen(\"XM\"))             ||\n          !strncmp(model_name, \"XH\", strlen(\"XH\"))             ||\n          !strncmp(model_name, \"XW\", strlen(\"XW\"))             ||\n          !strncmp(model_name, \"PRO\", strlen(\"PRO\")))\n      {\n        result = writeRegister(id, \"Operating_Mode\", VELOCITY_CONTROL_MODE);\n      }\n      else\n      {\n        result = writeRegister(id, \"CW_Angle_Limit\",  0, log);\n        result = writeRegister(id, \"CCW_Angle_Limit\", 0, log);\n      }\n    }\n    else if (index == CURRENT_CONTROL_MODE)\n    {\n      if (!strncmp(model_name, \"XL330\", strlen(\"XL330\"))       ||\n          !strncmp(model_name, \"XM\", strlen(\"XM\"))             ||\n          !strncmp(model_name, \"XH\", strlen(\"XH\"))             ||\n          !strncmp(model_name, \"MX-64-2\", strlen(\"MX-64-2\"))   ||\n          !strncmp(model_name, \"MX-106-2\", strlen(\"MX-106-2\")) ||\n          !strncmp(model_name, \"XW\", strlen(\"XW\"))             ||\n          !strncmp(model_name, \"RH\", strlen(\"RH\")))\n      {\n        result = writeRegister(id, \"Operating_Mode\", CURRENT_CONTROL_MODE, log);\n      }  \n    }\n    else if (index == TORQUE_CONTROL_MODE)\n    {\n      if (!strncmp(model_name, \"MX-64\", strlen(\"MX-64\"))   ||\n          !strncmp(model_name, \"MX-106\", strlen(\"MX-106\")) )\n      {\n        result = writeRegister(id, \"Torque_Control_Mode_Enable\", 1, log);\n      }\n    }\n    else if (index == MULTI_TURN_MODE)\n    {\n      if (!strncmp(model_name, \"MX-64\", strlen(\"MX-64\"))   ||\n          !strncmp(model_name, \"MX-106\", strlen(\"MX-106\")) )\n      {\n        result = writeRegister(id, \"CW_Angle_Limit\",  4095, log);\n        result = writeRegister(id, \"CCW_Angle_Limit\", 4095, log);\n      }\n    }\n    else if (index == CURRENT_BASED_POSITION_CONTROL_MODE)\n    {\n      if (!strncmp(model_name, \"MX-64-2\", strlen(\"MX-64-2\"))   ||\n          !strncmp(model_name, \"MX-106-2\", strlen(\"MX-106-2\")) ||\n          !strncmp(model_name, \"XL330\", strlen(\"XL330\"))       ||\n          !strncmp(model_name, \"XM\", strlen(\"XM\"))             ||\n          !strncmp(model_name, \"XH\", strlen(\"XH\"))             ||\n          !strncmp(model_name, \"XW\", strlen(\"XW\"))             ||\n          !strncmp(model_name, \"RH\", strlen(\"RH\")))\n      {\n        result = writeRegister(id, \"Operating_Mode\", CURRENT_BASED_POSITION_CONTROL_MODE, log);\n      }\n    }\n    else if (index == PWM_CONTROL_MODE)\n    {\n      if (!strncmp(model_name, \"MX-28-2\", strlen(\"MX-28-2\"))   ||\n          !strncmp(model_name, \"MX-64-2\", strlen(\"MX-64-2\"))   ||\n          !strncmp(model_name, \"MX-106-2\", strlen(\"MX-106-2\")) ||\n          !strncmp(model_name, \"XM\", strlen(\"XM\"))             ||\n          !strncmp(model_name, \"XH\", strlen(\"XH\"))             ||\n          !strncmp(model_name, \"XW\", strlen(\"XW\")))\n      {\n        result = writeRegister(id, \"Operating_Mode\", PWM_CONTROL_MODE, log);\n      }\n    }\n  }\n  else if (getProtocolVersion() == 2.0)\n  {\n    if (index == POSITION_CONTROL_MODE)\n    {\n      if (!strncmp(model_name, \"XL-320\", strlen(\"XL-320\")))\n        result = writeRegister(id, \"Control_Mode\", JOINT_MODE, log);\n      else\n        result = writeRegister(id, \"Operating_Mode\", POSITION_CONTROL_MODE, log);\n    }\n    else if (index == VELOCITY_CONTROL_MODE)\n    {\n      if (!strncmp(model_name, \"XL-320\", strlen(\"XL-320\")))\n        result = writeRegister(id, \"Control_Mode\", WHEEL_MODE, log);\n      else\n        result = writeRegister(id, \"Operating_Mode\", VELOCITY_CONTROL_MODE, log);\n    }\n    else if (index == CURRENT_CONTROL_MODE)\n    {\n      if (!strncmp(model_name, \"XL330\", strlen(\"XL330\"))       ||\n          !strncmp(model_name, \"XM\", strlen(\"XM\"))             ||\n          !strncmp(model_name, \"XH\", strlen(\"XH\"))             ||\n          !strncmp(model_name, \"XW\", strlen(\"XW\"))             ||\n          !strncmp(model_name, \"MX-64-2\", strlen(\"MX-64-2\"))   ||\n          !strncmp(model_name, \"MX-106-2\", strlen(\"MX-106-2\")) ||\n          !strncmp(model_name, \"RH\", strlen(\"RH\")))\n      {\n        result = writeRegister(id, \"Operating_Mode\", CURRENT_CONTROL_MODE, log);\n      }  \n    }\n    else if (index == TORQUE_CONTROL_MODE)\n    {\n      if (!strncmp(model_name, \"PRO\", strlen(\"PRO\"))   ||\n          strncmp(model_name, \"PRO-L42\", strlen(\"PRO-L42\")) )\n      {\n        result = writeRegister(id, \"Operating_Mode\", 0, log);\n      }\n    }\n    else if (index == EXTENDED_POSITION_CONTROL_MODE)\n    {\n      if (!strncmp(model_name, \"PRO\", strlen(\"PRO\"))   ||\n          strncmp(model_name, \"PRO-L42\", strlen(\"PRO-L42\")) )\n      {\n        result = writeRegister(id, \"Operating_Mode\", EXTENDED_POSITION_CONTROL_MODE, log);\n      }\n    }\n    else if (index == CURRENT_BASED_POSITION_CONTROL_MODE)\n    {\n      if (!strncmp(model_name, \"MX-64-2\", strlen(\"MX-64-2\"))   ||\n          !strncmp(model_name, \"MX-106-2\", strlen(\"MX-106-2\")) ||\n          !strncmp(model_name, \"XL330\", strlen(\"XL330\"))       ||\n          !strncmp(model_name, \"XM\", strlen(\"XM\"))             ||\n          !strncmp(model_name, \"XH\", strlen(\"XH\"))             ||\n          !strncmp(model_name, \"XW\", strlen(\"XW\"))             ||\n          !strncmp(model_name, \"RH\", strlen(\"RH\")))\n      {\n        result = writeRegister(id, \"Operating_Mode\", CURRENT_BASED_POSITION_CONTROL_MODE, log);\n      }\n    }\n    else if (index == PWM_CONTROL_MODE)\n    {\n      if (!strncmp(model_name, \"MX-28-2\", strlen(\"MX-28-2\"))   ||\n          !strncmp(model_name, \"MX-64-2\", strlen(\"MX-64-2\"))   ||\n          !strncmp(model_name, \"MX-106-2\", strlen(\"MX-106-2\")) ||\n          !strncmp(model_name, \"XL330\", strlen(\"XL330\"))       ||\n          !strncmp(model_name, \"XL430\", strlen(\"XL430\"))       ||\n          !strncmp(model_name, \"XC430\", strlen(\"XC430\"))       ||\n          !strncmp(model_name, \"XM\", strlen(\"XM\"))             ||\n          !strncmp(model_name, \"XH\", strlen(\"XH\"))             ||\n          !strncmp(model_name, \"XW\", strlen(\"XW\"))             ||\n          !strncmp(model_name, \"PRO\", strlen(\"PRO\")))\n      {\n        result = writeRegister(id, \"Operating_Mode\", PWM_CONTROL_MODE, log);\n      }\n    }\n  }\n\n  if (result == false)\n  {\n    if (log != NULL) *log = \"[DynamixelWorkbench] Failed to set Operating Mode!\";\n    return false;\n  }\n\n  if (log != NULL) *log = \"[DynamixelWorkbench] Succeeded to set Operating Mode!\";\n  return result;\n}\n\n\nbool DynamixelWorkbench::jointMode(uint8_t id, int32_t velocity, int32_t acceleration, const char **log)\n{\n  bool result = false;\n\n  model_name = getModelName(id, log);\n  if (model_name == NULL) return false;\n\n  result = torqueOff(id, log);\n  if (result == false) return false;\n\n  result = setPositionControlMode(id, log);\n  if (result == false) return false;\n\n  if (getProtocolVersion() == 1.0)\n  {\n    if (!strncmp(model_name, \"MX-28-2\", strlen(\"MX-28-2\"))   ||\n        !strncmp(model_name, \"MX-64-2\", strlen(\"MX-64-2\"))   ||\n        !strncmp(model_name, \"MX-106-2\", strlen(\"MX-106-2\")) ||\n        !strncmp(model_name, \"XL330\", strlen(\"XL330\"))       ||\n        !strncmp(model_name, \"XL430\", strlen(\"XL430\"))       ||\n        !strncmp(model_name, \"XC430\", strlen(\"XC430\"))       ||\n        !strncmp(model_name, \"XM\", strlen(\"XM\"))             ||\n        !strncmp(model_name, \"XH\", strlen(\"XH\"))             ||\n        !strncmp(model_name, \"XW\", strlen(\"XW\")))\n    {\n      result = writeRegister(id, \"Profile_Acceleration\", acceleration, log);\n      result = writeRegister(id, \"Profile_Velocity\", velocity, log);\n    }\n    else if (!strncmp(model_name, \"MX-28\", strlen(\"MX-28\"))   ||\n             !strncmp(model_name, \"MX-64\", strlen(\"MX-64\"))   ||\n             !strncmp(model_name, \"MX-106\", strlen(\"MX-106\")))\n    {\n      result = writeRegister(id, \"Moving_Speed\", velocity, log);\n      result = writeRegister(id, \"Goal_Acceleration\", acceleration, log);\n    }\n    else\n    {\n      result = writeRegister(id, \"Moving_Speed\", velocity, log);\n    }\n  }\n  else if (getProtocolVersion() == 2.0)\n  {\n    if (!strncmp(model_name, \"XL-320\", strlen(\"XL-320\")))\n    {\n      result = writeRegister(id, \"Moving_Speed\", velocity, log);\n    }\n    else if (!strncmp(model_name, \"PRO-M42-10-S260-R-A\",  strlen(\"PRO-M42-10-S260-R-A\"))  ||\n             !strncmp(model_name, \"PRO-M54-40-S250-R-A\",  strlen(\"PRO-M54-40-S250-R-A\"))  ||\n             !strncmp(model_name, \"PRO-M54-60-S250-R-A\",  strlen(\"PRO-M54-60-S250-R-A\"))  ||\n             !strncmp(model_name, \"PRO-H42-20-S300-R-A\",  strlen(\"PRO-H42-20-S300-R-A\"))  ||\n             !strncmp(model_name, \"PRO-H54-100-S500-R-A\", strlen(\"PRO-H54-100-S500-R-A\")) ||\n             !strncmp(model_name, \"PRO-H54-200-S500-R-A\", strlen(\"PRO-H54-200-S500-R-A\")))\n    {\n      result = writeRegister(id, \"Profile_Acceleration\", acceleration, log);\n      result = writeRegister(id, \"Profile_Velocity\", velocity, log);\n    }\n    else if (!strncmp(model_name, \"PRO-L\", strlen(\"PRO-L\")) ||\n             !strncmp(model_name, \"PRO-M\", strlen(\"PRO-M\")) ||\n             !strncmp(model_name, \"PRO-H\", strlen(\"PRO-H\")))\n    {\n      result = writeRegister(id, \"Goal_Velocity\", velocity, log);\n      result = writeRegister(id, \"Goal_Acceleration\", acceleration, log);\n    }\n    else\n    {\n      result = writeRegister(id, \"Profile_Acceleration\", acceleration, log);\n      result = writeRegister(id, \"Profile_Velocity\", velocity, log);\n    }\n  }\n\n  if (result == false)\n  {\n    if (log != NULL) *log = \"[DynamixelWorkbench] Failed to set Joint Mode!\";\n    return false;\n  }\n\n  result = torqueOn(id, log);\n  if (result == false) return false;\n\n  if (log != NULL) *log = \"[DynamixelWorkbench] Succeeded to set Joint Mode!\";\n  return result;\n}\n\nbool DynamixelWorkbench::wheelMode(uint8_t id, int32_t acceleration, const char **log)\n{\n  bool result = false;\n\n  model_name = getModelName(id, log);\n  if (model_name == NULL) return false;\n\n  result = torqueOff(id, log);\n  if (result == false) return false;\n\n  result = setVelocityControlMode(id, log);\n  if (result == false) return false;\n\n  if (getProtocolVersion() == 1.0)\n  {\n    if (!strncmp(model_name, \"MX-28-2\", strlen(\"MX-28-2\"))   ||\n        !strncmp(model_name, \"MX-64-2\", strlen(\"MX-64-2\"))   ||\n        !strncmp(model_name, \"MX-106-2\", strlen(\"MX-106-2\")) ||\n        !strncmp(model_name, \"XL330\", strlen(\"XL330\"))       ||\n        !strncmp(model_name, \"XL430\", strlen(\"XL430\"))       ||\n        !strncmp(model_name, \"XC430\", strlen(\"XC430\"))       ||\n        !strncmp(model_name, \"XM\", strlen(\"XM\"))             ||\n        !strncmp(model_name, \"XH\", strlen(\"XH\"))             ||\n        !strncmp(model_name, \"XW\", strlen(\"XW\")))\n    {\n      result = writeRegister(id, \"Profile_Acceleration\", acceleration, log);\n    }\n    else if (!strncmp(model_name, \"MX-28\", strlen(\"MX-28\"))   ||\n             !strncmp(model_name, \"MX-64\", strlen(\"MX-64\"))   ||\n             !strncmp(model_name, \"MX-106\", strlen(\"MX-106\")))\n    {\n      result = writeRegister(id, \"Goal_Acceleration\", acceleration, log);\n    }\n  }\n  else if (getProtocolVersion() == 2.0)\n  {\n    if (!strncmp(model_name, \"PRO-PLUS\", strlen(\"PRO-PLUS\")))\n    {\n      result = writeRegister(id, \"Profile_Acceleration\", acceleration, log);\n    }\n    else if (!strncmp(model_name, \"PRO\", strlen(\"PRO\")))  \n    {\n      result = writeRegister(id, \"Goal_Acceleration\", acceleration, log);\n    }\n    else\n    {\n      result = writeRegister(id, \"Profile_Acceleration\", acceleration, log);\n    }\n  }\n\n  if (result == false)\n  {\n    if (log != NULL) *log = \"[DynamixelWorkbench] Failed to set Wheel Mode!\";\n    return false;\n  }\n\n  result = torqueOn(id, log);\n  if (result == false) return false;\n\n  if (log != NULL) *log = \"[DynamixelWorkbench] Succeeded to set Wheel Mode!\";\n  return result;\n}\n\nbool DynamixelWorkbench::currentBasedPositionMode(uint8_t id, int32_t current, const char **log)\n{\n  bool result = false;\n\n  model_name = getModelName(id, log);\n  if (model_name == NULL) return false;\n\n  result = torqueOff(id, log);\n  if (result == false) return false;\n\n  result = setCurrentBasedPositionControlMode(id, log);\n  if (result == false) return false;\n\n  if (!strncmp(model_name, \"MX-64-2\", strlen(\"MX-64-2\"))   ||\n      !strncmp(model_name, \"MX-106-2\", strlen(\"MX-106-2\")) ||\n      !strncmp(model_name, \"XL330\", strlen(\"XL330\"))       ||\n      !strncmp(model_name, \"XM\", strlen(\"XM\"))             ||\n      !strncmp(model_name, \"XH\", strlen(\"XH\"))             ||\n      !strncmp(model_name, \"XW\", strlen(\"XW\"))             ||\n      !strncmp(model_name, \"RH\", strlen(\"RH\")))\n  {   \n    result = writeRegister(id, \"Goal_Current\", current, log);\n  }\n\n  if (result == false)\n  {\n    if (log != NULL) *log = \"[DynamixelWorkbench] Failed to set Current Based Position Mode!\";\n    return false;\n  }\n\n  result = torqueOn(id, log);\n  if (result == false) return false;\n\n  if (log != NULL) *log = \"[DynamixelWorkbench] Succeeded to set Current Based Position Wheel Mode!\";\n  return result;\n}\n\n//keep compatibility with older codes\nbool DynamixelWorkbench::goalPosition(uint8_t id, int value, const char **log)\n{\n  bool result = false;\n  result = goalPosition(id, (int32_t)value, log);\n  return result;\n}\n\nbool DynamixelWorkbench::goalPosition(uint8_t id, int32_t value, const char **log)\n{\n  bool result = false;\n  \n  result = itemWrite(id, \"Goal_Position\", value, log);\n\n  if (result == false)\n  {\n    if (log != NULL) *log = \"[DynamixelWorkbench] Failed to set goal position!\";\n    return false;\n  }\n\n  if (log != NULL) *log = \"[DynamixelWorkbench] Succeeded to set goal position!\";\n  return result;\n}\n\n//keep compatibility with older codes\nbool DynamixelWorkbench::goalSpeed(uint8_t id, int value, const char **log)\n{\n  bool result = false;\n  result = goalVelocity(id, (int32_t)value, log);\n  return result;\n}\n\n//keep compatibility with older codes\nbool DynamixelWorkbench::goalVelocity(uint8_t id, int value, const char **log)\n{\n  bool result = false;\n  goalVelocity(id, (int32_t)value, log);\n  return result;\n}\n\nbool DynamixelWorkbench::goalVelocity(uint8_t id, int32_t value, const char **log)\n{\n  bool result[2] = {false, false};\n\n  if (getProtocolVersion() == 2.0f)\n  {\n    result[0] = writeRegister(id, \"Goal_Velocity\", value, log);\n    if (result[0] == false)\n    {\n      if (value < 0)\n      {\n        value = (-1) * value;\n        value |= 1024;\n      }\n      result[1] = writeRegister(id, \"Moving_Speed\", value, log);\n      if (result[1] == false)\n      {\n        if (log != NULL) *log = \"[DynamixelWorkbench] Failed to set goal velocity!\";\n        return false;\n      }\n      else\n      {\n        if (log != NULL) *log = \"[DynamixelWorkbench] Succeeded to set goal velocity!\";\n        return true;\n      }\n    }\n    else\n    {\n      if (log != NULL) *log = \"[DynamixelWorkbench] Succeeded to set goal velocity!\";\n      return true;\n    }\n  }\n  else\n  {\n    result[0] = writeRegister(id, \"Goal_Velocity\", value, log);\n    if (result[0] == false)\n    {\n      if (value < 0)\n      {\n        value = (-1) * value;\n        value |= 1024;\n      }\n      result[1] = writeRegister(id, \"Moving_Speed\", value, log);\n      if (result[1] == false)\n      {\n        if (log != NULL) *log = \"[DynamixelWorkbench] Failed to set goal velocity!\";\n        return false;\n      }\n      else\n      {\n        if (log != NULL) *log = \"[DynamixelWorkbench] Succeeded to set goal velocity!\";\n        return true;\n      }\n    }\n    else\n    {\n      if (log != NULL) *log = \"[DynamixelWorkbench] Succeeded to set goal velocity!\";\n      return true;\n    }\n  }\n\n  if (log != NULL) *log = \"[DynamixelWorkbench] Failed to set goal velocity!\";\n  return false;\n}\n\nbool DynamixelWorkbench::goalPosition(uint8_t id, float radian, const char **log)\n{\n  bool result = 0;\n  uint32_t value = 0;\n\n  value = convertRadian2Value(id, radian);\n\n  result = goalPosition(id, (int32_t)value, log);\n  if (result == false)\n  {\n    if (log != NULL) *log = \"[DynamixelWorkbench] Failed to set goal position!\";\n    return false;\n  }\n\n  if (log != NULL) *log = \"[DynamixelWorkbench] Succeeded to set goal position!\";\n  return true;\n}\n\nbool DynamixelWorkbench::goalVelocity(uint8_t id, float velocity, const char **log)\n{\n  bool result = 0;\n  int32_t value = 0;\n\n  value = convertVelocity2Value(id, velocity);\n\n  result = goalVelocity(id, value, log);\n  if (result == false)\n  {\n    if (log != NULL) *log = \"[DynamixelWorkbench] Failed to set goal velocity!\";\n    return result;\n  }\n\n  if (log != NULL) *log = \"[DynamixelWorkbench] Succeeded to set goal velocity!\";\n  return result;\n}\n\nbool DynamixelWorkbench::getPresentPositionData(uint8_t id, int32_t* data, const char **log)\n{\n  bool result = 0;\n  int32_t get_data = 0;\n\n  result = readRegister(id, \"Present_Position\", &get_data, log);\n  if (result == false)\n  {\n    if (log != NULL) *log = \"[DynamixelWorkbench] Failed to get present position data!\";\n    return result;\n  }\n\n  *data = get_data;\n\n  if (log != NULL) *log = \"[DynamixelWorkbench] Succeeded to get present position data!\";\n  return result;\n}\n\nbool DynamixelWorkbench::getRadian(uint8_t id, float* radian, const char **log)\n{\n  bool result = 0;\n  int32_t get_data = 0;\n\n  result = getPresentPositionData(id, &get_data, log);\n  if (result == false)\n  {\n    if (log != NULL) *log = \"[DynamixelWorkbench] Failed to get radian!\";\n    return result;\n  }\n\n  *radian = convertValue2Radian(id, get_data);\n\n  if (log != NULL) *log = \"[DynamixelWorkbench] Succeeded to get radian!\";\n  return result;\n}\n\nbool DynamixelWorkbench::getVelocity(uint8_t id, float* velocity, const char **log)\n{\n  bool result = 0;\n  int32_t get_data = 0;\n\n  result = getPresentVelocityData(id, &get_data, log);\n  if (result == false)\n  {\n    if (log != NULL) *log = \"[DynamixelWorkbench] Failed to get velocity!\";\n    return result;\n  }\n\n  *velocity = convertValue2Velocity(id, get_data);\n\n  if (log != NULL) *log = \"[DynamixelWorkbench] Succeeded to get velocity!\";\n  return result;\n}\n\nbool DynamixelWorkbench::getPresentVelocityData(uint8_t id, int32_t* data, const char **log)\n{\n  bool result[2] = {false, false};\n  int32_t get_data = 0;\n\n  result[0] = readRegister(id, \"Goal_Velocity\", &get_data, log);\n  if (result[0] == false)\n  {\n    result[1] = readRegister(id, \"Moving_Speed\", &get_data, log);\n    if (result[1] == false)\n    {\n      if (log != NULL) *log = \"[DynamixelWorkbench] Failed to get goal velocity!\";\n      return false;\n    }\n    else\n    {\n      *data = get_data;\n      if (log != NULL) *log = \"[DynamixelWorkbench] Succeeded to get goal velocity!\";\n      return true;\n    }\n  }\n  else\n  {\n    *data = get_data;\n    if (log != NULL) *log = \"[DynamixelWorkbench] Succeeded to get goal velocity!\";\n    return true;\n  }\n\n  if (log != NULL) *log = \"[DynamixelWorkbench] Failed to get goal velocity!\";\n  return false;\n}\n\nint32_t DynamixelWorkbench::convertRadian2Value(uint8_t id, float radian)\n{\n  int32_t position = 0;\n\n  model_info = getModelInfo(id);\n  if (model_info == NULL) return false;\n\n  if (radian > 0)\n  {\n    position = (radian * (model_info->value_of_max_radian_position - model_info->value_of_zero_radian_position) / model_info->max_radian) + model_info->value_of_zero_radian_position;\n  }\n  else if (radian < 0)\n  {\n    position = (radian * (model_info->value_of_min_radian_position - model_info->value_of_zero_radian_position) / model_info->min_radian) + model_info->value_of_zero_radian_position;\n  }\n  else\n  {\n    position = model_info->value_of_zero_radian_position;\n  }\n\n  return position;\n}\n\nfloat DynamixelWorkbench::convertValue2Radian(uint8_t id, int32_t value)\n{\n  float radian = 0.0;\n\n  model_info = getModelInfo(id);\n  if (model_info == NULL) return false;\n\n  if (value > model_info->value_of_zero_radian_position)\n  {\n    radian = (float)(value - model_info->value_of_zero_radian_position) * model_info->max_radian / (float)(model_info->value_of_max_radian_position - model_info->value_of_zero_radian_position);\n  }\n  else if (value < model_info->value_of_zero_radian_position)\n  {\n    radian = (float)(value - model_info->value_of_zero_radian_position) * model_info->min_radian / (float)(model_info->value_of_min_radian_position - model_info->value_of_zero_radian_position);\n  }\n\n  return radian;\n}\n\nint32_t DynamixelWorkbench::convertRadian2Value(float radian, int32_t max_position, int32_t min_position, float max_radian, float min_radian)\n{\n  int32_t value = 0;\n  int32_t zero_position = (max_position + min_position)/2;\n\n  if (radian > 0)\n  {\n    value = (radian * (max_position - zero_position) / max_radian) + zero_position;\n  }\n  else if (radian < 0)\n  {\n    value = (radian * (min_position - zero_position) / min_radian) + zero_position;\n  }\n  else\n  {\n    value = zero_position;\n  }\n\n  return value;\n}\n\nfloat DynamixelWorkbench::convertValue2Radian(int32_t value, int32_t max_position, int32_t min_position, float max_radian, float min_radian)\n{\n  float radian = 0.0;\n  int32_t zero_position = (max_position + min_position)/2;\n\n  if (value > zero_position)\n  {\n    radian = (float)(value - zero_position) * max_radian / (float)(max_position - zero_position);\n  }\n  else if (value < zero_position)\n  {\n    radian = (float)(value - zero_position) * min_radian / (float)(min_position - zero_position);\n  }\n\n  return radian;\n}\n\nint32_t DynamixelWorkbench::convertVelocity2Value(uint8_t id, float velocity)\n{\n  int32_t value = 0;\n  const float RPM2RADPERSEC = 0.104719755f;\n\n  model_info = getModelInfo(id);\n  if (model_info == NULL) return false;\n\n  if (getProtocolVersion() == 1.0f)\n  {\n    if (strncmp(getModelName(id), \"AX\", strlen(\"AX\")) == 0 ||\n        strncmp(getModelName(id), \"RX\", strlen(\"RX\")) == 0 ||\n        strncmp(getModelName(id), \"EX\", strlen(\"EX\")) == 0 ||\n        strncmp(getModelName(id), \"MX\", strlen(\"MX\")) == 0)\n    {\n      if (velocity == 0.0f) value = 0;\n      else if (velocity < 0.0f) value = (velocity / (model_info->rpm * RPM2RADPERSEC));\n      else if (velocity > 0.0f) value = (velocity / (model_info->rpm * RPM2RADPERSEC)) + 1023;\n\n      return value;\n    }\n  }\n  else if (getProtocolVersion() == 2.0f)\n  {\n    if (strcmp(getModelName(id), \"XL-320\") == 0)\n    {\n      if (velocity == 0.0f) value = 0;\n      else if (velocity < 0.0f) value = (velocity / (model_info->rpm * RPM2RADPERSEC));\n      else if (velocity > 0.0f) value = (velocity / (model_info->rpm * RPM2RADPERSEC)) + 1023;\n\n      return value;\n    }\n    else\n    {\n      value = velocity / (model_info->rpm * RPM2RADPERSEC);\n    }\n\n    return value;\n  }\n\n  return 0;\n}\n\nfloat DynamixelWorkbench::convertValue2Velocity(uint8_t id, int32_t value)\n{\n  float velocity = 0;\n  const float RPM2RADPERSEC = 0.104719755f;\n\n  model_info = getModelInfo(id);\n  if (model_info == NULL) return false;\n\n  if (getProtocolVersion() == 1.0f)\n  {\n    if (strncmp(getModelName(id), \"AX\", strlen(\"AX\")) == 0 ||\n        strncmp(getModelName(id), \"RX\", strlen(\"RX\")) == 0 ||\n        strncmp(getModelName(id), \"EX\", strlen(\"EX\")) == 0 ||\n        strncmp(getModelName(id), \"MX\", strlen(\"MX\")) == 0)\n    {\n      if (value == 1023 || value == 0) velocity = 0.0f;\n      else if (value > 0 && value < 1023) velocity = value * model_info->rpm * RPM2RADPERSEC;\n      else if (value > 1023 && value < 2048) velocity = (value - 1023) * model_info->rpm * RPM2RADPERSEC  * (-1.0f);\n\n      return velocity;\n    }\n  }\n  else if (getProtocolVersion() == 2.0f)\n  {\n    if (strcmp(getModelName(id), \"XL-320\") == 0)\n    {\n      if (value == 1023 || value == 0) velocity = 0.0f;\n      else if (value > 0 && value < 1023) velocity = value * model_info->rpm * RPM2RADPERSEC;\n      else if (value > 1023 && value < 2048) velocity = (value - 1023) * model_info->rpm * RPM2RADPERSEC * (-1.0f);\n    }\n    else\n    {\n      velocity = value * (model_info->rpm * RPM2RADPERSEC);\n    }\n\n    return velocity;\n  }\n\n  return 0.0f;\n}\n\nint16_t DynamixelWorkbench::convertCurrent2Value(uint8_t id, float current)\n{\n  float CURRENT_UNIT = 2.69f; //Unit : mA, Ref : http://emanual.robotis.com/docs/en/dxl/x/xm430-w350/#goal-current102\n\n  model_info = getModelInfo(id);\n  if (model_info == NULL) return false;\n\n  if (getProtocolVersion() == 1.0f)\n  {\n      return (current / CURRENT_UNIT);\n  }\n  else if (getProtocolVersion() == 2.0f)\n  {\n    if (strncmp(getModelName(id), \"PRO-L\", strlen(\"PRO-L\")) == 0 ||\n        strncmp(getModelName(id), \"PRO-M\", strlen(\"PRO-M\")) == 0 ||\n        strncmp(getModelName(id), \"PRO-H\", strlen(\"PRO-H\")) == 0)\n    {\n      CURRENT_UNIT = 16.11328f;\n      return (current / CURRENT_UNIT);\n    }\n    else if (strncmp(getModelName(id), \"PRO-PLUS\", strlen(\"PRO-PLUS\")) == 0)\n    {\n      CURRENT_UNIT = 1.0f;\n      return (current / CURRENT_UNIT);\n    }\n    else\n    {\n      return (current / CURRENT_UNIT);\n    }\n  }\n\n  return (current / CURRENT_UNIT);\n}\n\nint16_t DynamixelWorkbench::convertCurrent2Value(float current)\n{\n  int16_t value = 0;\n  const float CURRENT_UNIT = 2.69f; //Unit : mA, Ref : http://emanual.robotis.com/docs/en/dxl/x/xm430-w350/#goal-current102\n\n  value = current / CURRENT_UNIT;\n\n  return value;\n}\n\nfloat DynamixelWorkbench::convertValue2Current(uint8_t id, int16_t value)\n{\n  float current = 0;\n  float CURRENT_UNIT = 2.69f; //Unit : mA, Ref : http://emanual.robotis.com/docs/en/dxl/x/xm430-w350/#goal-current102\n\n  model_info = getModelInfo(id);\n  if (model_info == NULL) return false;\n\n  if (getProtocolVersion() == 1.0f)\n  {\n    current = (int16_t)value * CURRENT_UNIT;\n    return current;\n  }\n  else if (getProtocolVersion() == 2.0f)\n  {\n    if (strncmp(getModelName(id), \"PRO-L\", strlen(\"PRO-L\")) == 0 ||\n        strncmp(getModelName(id), \"PRO-M\", strlen(\"PRO-M\")) == 0 ||\n        strncmp(getModelName(id), \"PRO-H\", strlen(\"PRO-H\")) == 0)\n    {\n      CURRENT_UNIT = 16.11328f;\n      current = (int16_t)value * CURRENT_UNIT;\n      return current;\n    }\n    else if (strncmp(getModelName(id), \"PRO-PLUS\", strlen(\"PRO-PLUS\")) == 0)\n    {\n      CURRENT_UNIT = 1.0f;\n      current = (int16_t)value * CURRENT_UNIT;\n      return current;\n    }\n    else\n    {\n      current = (int16_t)value * CURRENT_UNIT;\n      return current;\n    }\n  }\n\n  current = (int16_t)value * CURRENT_UNIT;\n\n  return current;\n}\n\nfloat DynamixelWorkbench::convertValue2Current(int16_t value)\n{\n  float current = 0;\n  const float CURRENT_UNIT = 2.69f; //Unit : mA, Ref : http://emanual.robotis.com/docs/en/dxl/x/xm430-w350/#goal-current102\n\n  current = (int16_t)value * CURRENT_UNIT;\n\n  return current;\n}\n\nfloat DynamixelWorkbench::convertValue2Load(int16_t value)\n{\n  float load = 0;\n  const float LOAD_UNIT = 0.1f; //Unit : %, Ref : http://emanual.robotis.com/docs/en/dxl/mx/mx-28/#present-load\n\n  if (value == 1023 || value == 0) load = 0.0f;\n  else if (value > 0 && value < 1023) load = value * LOAD_UNIT;\n  else if (value > 1023 && value < 2048) load = (value - 1023) * LOAD_UNIT * (-1.0f);\n\n  return load;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/EEPROM/README.md",
    "content": "## **EEPROM Library V2.0** for Arduino\n\n**Written by:** _Christopher Andrews_.  \n\n### **What is the EEPROM library.**\n\nTh EEPROM library provides an easy to use interface to interact with the internal non-volatile storage found in AVR based Arduino boards. This library will work on many AVR devices like ATtiny and ATmega chips.\n\n### **How to use it**\nThe EEPROM library is included in your IDE download. To add its functionality to your sketch you'll need to reference the library header file. You do this by adding an include directive to the top of your sketch.\n\n```Arduino\n#include <EEPROM.h>\n\nvoid setup(){\n\n}\n\nvoid loop(){\n\n}\n\n```\n\nThe library provides a global variable named `EEPROM`, you use this variable to access the library functions. The methods provided in the EEPROM class are listed below.\n\nYou can view all the examples [here](examples/).\n\n### **Library functions**\n\n#### **`EEPROM.read( address )`** [[_example_]](examples/eeprom_read/eeprom_read.ino)\n\nThis function allows you to read a single byte of data from the eeprom.\nIts only parameter is an `int` which should be set to the address you wish to read.\n\nThe function returns an `unsigned char` containing the value read.\n\n#### **`EEPROM.write( address, value )`** [[_example_]](examples/eeprom_write/eeprom_write.ino)\n\nThe `write()` method allows you to write a single byte of data to the EEPROM.\nTwo parameters are needed. The first is an `int` containing the address that is to be written, and the second is a the data to be written (`unsigned char`).\n\nThis function does not return any value.\n\n#### **`EEPROM.update( address, value )`** [[_example_]](examples/eeprom_update/eeprom_update.ino)\n\nThis function is similar to `EEPROM.write()` however this method will only write data if the cell contents pointed to by `address` is different to `value`. This method can help prevent unnecessary wear on the EEPROM cells.\n\nThis function does not return any value.\n\n#### **`EEPROM.get( address, object )`** [[_example_]](examples/eeprom_get/eeprom_get.ino)\n\nThis function will retrieve any object from the EEPROM.\nTwo parameters are needed to call this function. The first is an `int` containing the address that is to be written, and the second is the object you would like to read.\n\nThis function returns a reference to the `object` passed in. It does not need to be used and is only returned for conveience.\n\n#### **`EEPROM.put( address, object )`** [[_example_]](examples/eeprom_put/eeprom_put.ino)\n\nThis function will write any object to the EEPROM.\nTwo parameters are needed to call this function. The first is an `int` containing the address that is to be written, and the second is the object you would like to write.\n\nThis function uses the _update_ method to write its data, and therefore only rewrites changed cells.\n\nThis function returns a reference to the `object` passed in. It does not need to be used and is only returned for conveience.\n\n#### **Subscript operator: `EEPROM[address]`** [[_example_]](examples/eeprom_crc/eeprom_crc.ino)\n\nThis operator allows using the identifier `EEPROM` like an array.  \nEEPROM cells can be read _and_ **_written_** directly using this method.\n\nThis operator returns a reference to the EEPROM cell.\n\n```c++\nunsigned char val;\n\n//Read first EEPROM cell.\nval = EEPROM[ 0 ];\n\n//Write first EEPROM cell.\nEEPROM[ 0 ] = val;\n\n//Compare contents\nif( val == EEPROM[ 0 ] ){\n  //Do something...\n}\n```\n\n#### **`EEPROM.length()`**\n\nThis function returns an `unsigned int` containing the number of cells in the EEPROM.\n\n---\n\n### **Advanced features**\n\nThis library uses a component based approach to provide its functionality. This means you can also use these components to design a customized approach. Two background classes are available for use: `EERef` & `EEPtr`.\n\n#### **`EERef` class**\n\nThis object references an EEPROM cell.\nIts purpose is to mimic a typical byte of RAM, however its storage is the EEPROM.\nThis class has an overhead of two bytes, similar to storing a pointer to an EEPROM cell.\n\n```C++\nEERef ref = EEPROM[ 10 ]; //Create a reference to 11th cell.\n\nref = 4; //write to EEPROM cell.\n\nunsigned char val = ref; //Read referenced cell.\n```\n\n#### **`EEPtr` class**\n\nThis object is a bidirectional pointer to EEPROM cells represented by `EERef` objects.\nJust like a normal pointer type, this type can be dereferenced and repositioned using \nincrement/decrement operators.\n\n```C++\nEEPtr ptr = 10; //Create a pointer to 11th cell.\n\n*ptr = 4; //dereference and write to EEPROM cell.\n\nunsigned char val = *ptr; //dereference and read.\n\nptr++; //Move to next EEPROM cell.\n```\n\n#### **`EEPROM.begin()`**\n\nThis function returns an `EEPtr` pointing to the first cell in the EEPROM.  \nThis is useful for STL objects, custom iteration and C++11 style ranged for loops.\n\n#### **`EEPROM.end()`**\n\nThis function returns an `EEPtr` pointing at the location after the last EEPROM cell.  \nUsed with `begin()` to provide custom iteration.\n\n**Note:** The `EEPtr` returned is invalid as it is out of range. Infact the hardware causes wrapping of the address (overflow) and `EEPROM.end()` actually references the first EEPROM cell.\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/EEPROM/keywords.txt",
    "content": "#######################################\n# Syntax Coloring Map For EEPROM\n#######################################\n\n#######################################\n# Datatypes (KEYWORD1)\n#######################################\n\nEEPROM\tKEYWORD1\nEERef\tKEYWORD1\nEEPtr\tKEYWORD2\n\n#######################################\n# Methods and Functions (KEYWORD2)\n#######################################\n\nupdate\tKEYWORD2\n\n#######################################\n# Constants (LITERAL1)\n#######################################\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/EEPROM/library.properties",
    "content": "name=EEPROM\nversion=2.0\nauthor=Arduino, Christopher Andrews\nmaintainer=Arduino <info@arduino.cc>\nsentence=Enables reading and writing to the permanent board storage.\nparagraph=This library allows to read and write data in a memory type, the EEPROM, that keeps its content also when the board is powered off. The amount of EEPROM available depends on the microcontroller type.\ncategory=Data Storage\nurl=http://www.arduino.cc/en/Reference/EEPROM\narchitectures=OpenCR\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/EEPROM/src/EEPROM.h",
    "content": "/*\n  EEPROM.h - EEPROM library\n  Original Copyright (c) 2006 David A. Mellis.  All right reserved.\n  New version by Christopher Andrews 2015.\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n  Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n#ifndef EEPROM_h\n#define EEPROM_h\n\n#include <inttypes.h>\n#include \"drv_eeprom.h\"\n\n/***\n    EERef class.\n\n    This object references an EEPROM cell.\n    Its purpose is to mimic a typical byte of RAM, however its storage is the EEPROM.\n    This class has an overhead of two bytes, similar to storing a pointer to an EEPROM cell.\n***/\n\nstruct EERef{\n\n    EERef( const int index )\n        : index( index )                 {}\n\n    //Access/read members.\n    uint8_t operator*() const            { return drv_eeprom_read_byte( index ); }\n    operator uint8_t() const       { return **this; }\n\n    //Assignment/write members.\n    EERef &operator=( const EERef &ref ) { return *this = *ref; }\n    EERef &operator=( uint8_t in )       { return drv_eeprom_write_byte( index, in ), *this;  }\n    EERef &operator +=( uint8_t in )     { return *this = **this + in; }\n    EERef &operator -=( uint8_t in )     { return *this = **this - in; }\n    EERef &operator *=( uint8_t in )     { return *this = **this * in; }\n    EERef &operator /=( uint8_t in )     { return *this = **this / in; }\n    EERef &operator ^=( uint8_t in )     { return *this = **this ^ in; }\n    EERef &operator %=( uint8_t in )     { return *this = **this % in; }\n    EERef &operator &=( uint8_t in )     { return *this = **this & in; }\n    EERef &operator |=( uint8_t in )     { return *this = **this | in; }\n    EERef &operator <<=( uint8_t in )    { return *this = **this << in; }\n    EERef &operator >>=( uint8_t in )    { return *this = **this >> in; }\n\n    EERef &update( uint8_t in )          { return  in != *this ? *this = in : *this; }\n\n    /** Prefix increment/decrement **/\n    EERef& operator++()                  { return *this += 1; }\n    EERef& operator--()                  { return *this -= 1; }\n\n    /** Postfix increment/decrement **/\n    uint8_t operator++ (int){\n        uint8_t ret = **this;\n        return ++(*this), ret;\n    }\n\n    uint8_t operator-- (int){\n        uint8_t ret = **this;\n        return --(*this), ret;\n    }\n\n    int index; //Index of current EEPROM cell.\n};\n\n/***\n    EEPtr class.\n\n    This object is a bidirectional pointer to EEPROM cells represented by EERef objects.\n    Just like a normal pointer type, this can be dereferenced and repositioned using\n    increment/decrement operators.\n***/\n\nstruct EEPtr{\n\n    EEPtr( const int index )\n        : index( index )                {}\n\n    operator int() const          { return index; }\n    EEPtr &operator=( int in )          { return index = in, *this; }\n\n    //Iterator functionality.\n    bool operator!=( const EEPtr &ptr ) { return index != ptr.index; }\n    EERef operator*()                   { return index; }\n\n    /** Prefix & Postfix increment/decrement **/\n    EEPtr& operator++()                 { return ++index, *this; }\n    EEPtr& operator--()                 { return --index, *this; }\n    EEPtr operator++ (int)              { return index++; }\n    EEPtr operator-- (int)              { return index--; }\n\n    int index; //Index of current EEPROM cell.\n};\n\n/***\n    EEPROMClass class.\n\n    This object represents the entire EEPROM space.\n    It wraps the functionality of EEPtr and EERef into a basic interface.\n    This class is also 100% backwards compatible with earlier Arduino core releases.\n***/\n\nstruct EEPROMClass{\n\n    //Basic user access methods.\n    EERef operator[]( const int idx )    { return idx; }\n    uint8_t read( int idx )              { return EERef( idx ); }\n    void write( int idx, uint8_t val )   { (EERef( idx )) = val; }\n    void update( int idx, uint8_t val )  { EERef( idx ).update( val ); }\n\n    //STL and C++11 iteration capability.\n    EEPtr begin()                        { return 0x00; }\n    EEPtr end()                          { return length(); } //Standards requires this to be the item after the last valid entry. The returned pointer is invalid.\n    uint16_t length()                    { return drv_eeprom_get_length(); }\n\n    //Functionality to 'get' and 'put' objects to and from EEPROM.\n    template< typename T > T &get( int idx, T &t ){\n        EEPtr e = idx;\n        uint8_t *ptr = (uint8_t*) &t;\n        for( int count = sizeof(T) ; count ; --count, ++e )  *ptr++ = *e;\n        return t;\n    }\n\n    template< typename T > const T &put( int idx, const T &t ){\n        EEPtr e = idx;\n        const uint8_t *ptr = (const uint8_t*) &t;\n        for( int count = sizeof(T) ; count ; --count, ++e )  (*e).update( *ptr++ );\n        return t;\n    }\n};\n\nstatic EEPROMClass EEPROM __attribute__ ((unused));\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/library.properties",
    "content": "name=Eigen\nversion=3.3.1\nauthor=\nmaintainer=\nsentence=Eigen for OpenCR\nparagraph=\ncategory=Data Processing\nurl=http://eigen.tuxfamily.org/index.php?title=Main_Page\narchitectures=OpenCR\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/CMakeLists.txt",
    "content": "include(RegexUtils)\ntest_escape_string_as_regex()\n\nfile(GLOB Eigen_directory_files \"*\")\n\nescape_string_as_regex(ESCAPED_CMAKE_CURRENT_SOURCE_DIR \"${CMAKE_CURRENT_SOURCE_DIR}\")\n\nforeach(f ${Eigen_directory_files})\n  if(NOT f MATCHES \"\\\\.txt\" AND NOT f MATCHES \"${ESCAPED_CMAKE_CURRENT_SOURCE_DIR}/[.].+\" AND NOT f MATCHES \"${ESCAPED_CMAKE_CURRENT_SOURCE_DIR}/src\")\n    list(APPEND Eigen_directory_files_to_install ${f})\n  endif()\nendforeach(f ${Eigen_directory_files})\n\ninstall(FILES\n  ${Eigen_directory_files_to_install}\n  DESTINATION ${INCLUDE_INSTALL_DIR}/Eigen COMPONENT Devel\n  )\n\ninstall(DIRECTORY src DESTINATION ${INCLUDE_INSTALL_DIR}/Eigen COMPONENT Devel FILES_MATCHING PATTERN \"*.h\")\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/Cholesky",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_CHOLESKY_MODULE_H\n#define EIGEN_CHOLESKY_MODULE_H\n\n#include \"Core\"\n\n#include \"src/Core/util/DisableStupidWarnings.h\"\n\n/** \\defgroup Cholesky_Module Cholesky module\n  *\n  *\n  *\n  * This module provides two variants of the Cholesky decomposition for selfadjoint (hermitian) matrices.\n  * Those decompositions are also accessible via the following methods:\n  *  - MatrixBase::llt()\n  *  - MatrixBase::ldlt()\n  *  - SelfAdjointView::llt()\n  *  - SelfAdjointView::ldlt()\n  *\n  * \\code\n  * #include <Eigen/Cholesky>\n  * \\endcode\n  */\n\n#include \"src/Cholesky/LLT.h\"\n#include \"src/Cholesky/LDLT.h\"\n#ifdef EIGEN_USE_LAPACKE\n#include \"src/misc/lapacke.h\"\n#include \"src/Cholesky/LLT_LAPACKE.h\"\n#endif\n\n#include \"src/Core/util/ReenableStupidWarnings.h\"\n\n#endif // EIGEN_CHOLESKY_MODULE_H\n/* vim: set filetype=cpp et sw=2 ts=2 ai: */\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/CholmodSupport",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_CHOLMODSUPPORT_MODULE_H\n#define EIGEN_CHOLMODSUPPORT_MODULE_H\n\n#include \"SparseCore\"\n\n#include \"src/Core/util/DisableStupidWarnings.h\"\n\nextern \"C\" {\n  #include <cholmod.h>\n}\n\n/** \\ingroup Support_modules\n  * \\defgroup CholmodSupport_Module CholmodSupport module\n  *\n  * This module provides an interface to the Cholmod library which is part of the <a href=\"http://www.suitesparse.com\">suitesparse</a> package.\n  * It provides the two following main factorization classes:\n  * - class CholmodSupernodalLLT: a supernodal LLT Cholesky factorization.\n  * - class CholmodDecomposiiton: a general L(D)LT Cholesky factorization with automatic or explicit runtime selection of the underlying factorization method (supernodal or simplicial).\n  *\n  * For the sake of completeness, this module also propose the two following classes:\n  * - class CholmodSimplicialLLT\n  * - class CholmodSimplicialLDLT\n  * Note that these classes does not bring any particular advantage compared to the built-in\n  * SimplicialLLT and SimplicialLDLT factorization classes.\n  *\n  * \\code\n  * #include <Eigen/CholmodSupport>\n  * \\endcode\n  *\n  * In order to use this module, the cholmod headers must be accessible from the include paths, and your binary must be linked to the cholmod library and its dependencies.\n  * The dependencies depend on how cholmod has been compiled.\n  * For a cmake based project, you can use our FindCholmod.cmake module to help you in this task.\n  *\n  */\n\n#include \"src/CholmodSupport/CholmodSupport.h\"\n\n#include \"src/Core/util/ReenableStupidWarnings.h\"\n\n#endif // EIGEN_CHOLMODSUPPORT_MODULE_H\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/Core",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2007-2011 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_CORE_H\n#define EIGEN_CORE_H\n\n// first thing Eigen does: stop the compiler from committing suicide\n#include \"src/Core/util/DisableStupidWarnings.h\"\n\n// Handle NVCC/CUDA/SYCL\n#if defined(__CUDACC__) || defined(__SYCL_DEVICE_ONLY__)\n  // Do not try asserts on CUDA and SYCL!\n  #ifndef EIGEN_NO_DEBUG\n  #define EIGEN_NO_DEBUG\n  #endif\n\n  #ifdef EIGEN_INTERNAL_DEBUGGING\n  #undef EIGEN_INTERNAL_DEBUGGING\n  #endif\n\n  #ifdef EIGEN_EXCEPTIONS\n  #undef EIGEN_EXCEPTIONS\n  #endif\n\n  // All functions callable from CUDA code must be qualified with __device__\n  #ifdef __CUDACC__\n    // Do not try to vectorize on CUDA and SYCL!\n    #ifndef EIGEN_DONT_VECTORIZE\n    #define EIGEN_DONT_VECTORIZE\n    #endif\n\n    #define EIGEN_DEVICE_FUNC __host__ __device__\n    // We need math_functions.hpp to ensure that that EIGEN_USING_STD_MATH macro\n    // works properly on the device side\n    #include <math_functions.hpp>\n  #else\n    #define EIGEN_DEVICE_FUNC\n  #endif\n\n#else\n  #define EIGEN_DEVICE_FUNC\n\n#endif\n\n// When compiling CUDA device code with NVCC, pull in math functions from the\n// global namespace.  In host mode, and when device doee with clang, use the\n// std versions.\n#if defined(__CUDA_ARCH__) && defined(__NVCC__)\n  #define EIGEN_USING_STD_MATH(FUNC) using ::FUNC;\n#else\n  #define EIGEN_USING_STD_MATH(FUNC) using std::FUNC;\n#endif\n\n#if (defined(_CPPUNWIND) || defined(__EXCEPTIONS)) && !defined(__CUDA_ARCH__) && !defined(EIGEN_EXCEPTIONS) && !defined(EIGEN_USE_SYCL)\n  #define EIGEN_EXCEPTIONS\n#endif\n\n#ifdef EIGEN_EXCEPTIONS\n  #include <new>\n#endif\n\n// then include this file where all our macros are defined. It's really important to do it first because\n// it's where we do all the alignment settings (platform detection and honoring the user's will if he\n// defined e.g. EIGEN_DONT_ALIGN) so it needs to be done before we do anything with vectorization.\n#include \"src/Core/util/Macros.h\"\n\n// Disable the ipa-cp-clone optimization flag with MinGW 6.x or newer (enabled by default with -O3)\n// See http://eigen.tuxfamily.org/bz/show_bug.cgi?id=556 for details.\n#if EIGEN_COMP_MINGW && EIGEN_GNUC_AT_LEAST(4,6)\n  #pragma GCC optimize (\"-fno-ipa-cp-clone\")\n#endif\n\n#include <complex>\n\n// this include file manages BLAS and MKL related macros\n// and inclusion of their respective header files\n#include \"src/Core/util/MKL_support.h\"\n\n// if alignment is disabled, then disable vectorization. Note: EIGEN_MAX_ALIGN_BYTES is the proper check, it takes into\n// account both the user's will (EIGEN_MAX_ALIGN_BYTES,EIGEN_DONT_ALIGN) and our own platform checks\n#if EIGEN_MAX_ALIGN_BYTES==0\n  #ifndef EIGEN_DONT_VECTORIZE\n    #define EIGEN_DONT_VECTORIZE\n  #endif\n#endif\n\n#if EIGEN_COMP_MSVC\n  #include <malloc.h> // for _aligned_malloc -- need it regardless of whether vectorization is enabled\n  #if (EIGEN_COMP_MSVC >= 1500) // 2008 or later\n    // Remember that usage of defined() in a #define is undefined by the standard.\n    // a user reported that in 64-bit mode, MSVC doesn't care to define _M_IX86_FP.\n    #if (defined(_M_IX86_FP) && (_M_IX86_FP >= 2)) || EIGEN_ARCH_x86_64\n      #define EIGEN_SSE2_ON_MSVC_2008_OR_LATER\n    #endif\n  #endif\n#else\n  // Remember that usage of defined() in a #define is undefined by the standard\n  #if (defined __SSE2__) && ( (!EIGEN_COMP_GNUC) || EIGEN_COMP_ICC || EIGEN_GNUC_AT_LEAST(4,2) )\n    #define EIGEN_SSE2_ON_NON_MSVC_BUT_NOT_OLD_GCC\n  #endif\n#endif\n\n#ifndef EIGEN_DONT_VECTORIZE\n\n  #if defined (EIGEN_SSE2_ON_NON_MSVC_BUT_NOT_OLD_GCC) || defined(EIGEN_SSE2_ON_MSVC_2008_OR_LATER)\n\n    // Defines symbols for compile-time detection of which instructions are\n    // used.\n    // EIGEN_VECTORIZE_YY is defined if and only if the instruction set YY is used\n    #define EIGEN_VECTORIZE\n    #define EIGEN_VECTORIZE_SSE\n    #define EIGEN_VECTORIZE_SSE2\n\n    // Detect sse3/ssse3/sse4:\n    // gcc and icc defines __SSE3__, ...\n    // there is no way to know about this on msvc. You can define EIGEN_VECTORIZE_SSE* if you\n    // want to force the use of those instructions with msvc.\n    #ifdef __SSE3__\n      #define EIGEN_VECTORIZE_SSE3\n    #endif\n    #ifdef __SSSE3__\n      #define EIGEN_VECTORIZE_SSSE3\n    #endif\n    #ifdef __SSE4_1__\n      #define EIGEN_VECTORIZE_SSE4_1\n    #endif\n    #ifdef __SSE4_2__\n      #define EIGEN_VECTORIZE_SSE4_2\n    #endif\n    #ifdef __AVX__\n      #define EIGEN_VECTORIZE_AVX\n      #define EIGEN_VECTORIZE_SSE3\n      #define EIGEN_VECTORIZE_SSSE3\n      #define EIGEN_VECTORIZE_SSE4_1\n      #define EIGEN_VECTORIZE_SSE4_2\n    #endif\n    #ifdef __AVX2__\n      #define EIGEN_VECTORIZE_AVX2\n    #endif\n    #ifdef __FMA__\n      #define EIGEN_VECTORIZE_FMA\n    #endif\n    #if defined(__AVX512F__) && defined(EIGEN_ENABLE_AVX512)\n      #define EIGEN_VECTORIZE_AVX512\n      #define EIGEN_VECTORIZE_AVX2\n      #define EIGEN_VECTORIZE_AVX\n      #define EIGEN_VECTORIZE_FMA\n      #ifdef __AVX512DQ__\n        #define EIGEN_VECTORIZE_AVX512DQ\n      #endif\n    #endif\n\n    // include files\n\n    // This extern \"C\" works around a MINGW-w64 compilation issue\n    // https://sourceforge.net/tracker/index.php?func=detail&aid=3018394&group_id=202880&atid=983354\n    // In essence, intrin.h is included by windows.h and also declares intrinsics (just as emmintrin.h etc. below do).\n    // However, intrin.h uses an extern \"C\" declaration, and g++ thus complains of duplicate declarations\n    // with conflicting linkage.  The linkage for intrinsics doesn't matter, but at that stage the compiler doesn't know;\n    // so, to avoid compile errors when windows.h is included after Eigen/Core, ensure intrinsics are extern \"C\" here too.\n    // notice that since these are C headers, the extern \"C\" is theoretically needed anyways.\n    extern \"C\" {\n      // In theory we should only include immintrin.h and not the other *mmintrin.h header files directly.\n      // Doing so triggers some issues with ICC. However old gcc versions seems to not have this file, thus:\n      #if EIGEN_COMP_ICC >= 1110\n        #include <immintrin.h>\n      #else\n        #include <mmintrin.h>\n        #include <emmintrin.h>\n        #include <xmmintrin.h>\n        #ifdef  EIGEN_VECTORIZE_SSE3\n        #include <pmmintrin.h>\n        #endif\n        #ifdef EIGEN_VECTORIZE_SSSE3\n        #include <tmmintrin.h>\n        #endif\n        #ifdef EIGEN_VECTORIZE_SSE4_1\n        #include <smmintrin.h>\n        #endif\n        #ifdef EIGEN_VECTORIZE_SSE4_2\n        #include <nmmintrin.h>\n        #endif\n        #if defined(EIGEN_VECTORIZE_AVX) || defined(EIGEN_VECTORIZE_AVX512)\n        #include <immintrin.h>\n        #endif\n      #endif\n    } // end extern \"C\"\n  #elif defined __VSX__\n    #define EIGEN_VECTORIZE\n    #define EIGEN_VECTORIZE_VSX\n    #include <altivec.h>\n    // We need to #undef all these ugly tokens defined in <altivec.h>\n    // => use __vector instead of vector\n    #undef bool\n    #undef vector\n    #undef pixel\n  #elif defined __ALTIVEC__\n    #define EIGEN_VECTORIZE\n    #define EIGEN_VECTORIZE_ALTIVEC\n    #include <altivec.h>\n    // We need to #undef all these ugly tokens defined in <altivec.h>\n    // => use __vector instead of vector\n    #undef bool\n    #undef vector\n    #undef pixel\n  #elif (defined  __ARM_NEON) || (defined __ARM_NEON__)\n    #define EIGEN_VECTORIZE\n    #define EIGEN_VECTORIZE_NEON\n    #include <arm_neon.h>\n  #elif (defined __s390x__ && defined __VEC__)\n    #define EIGEN_VECTORIZE\n    #define EIGEN_VECTORIZE_ZVECTOR\n    #include <vecintrin.h>\n  #endif\n#endif\n\n#if defined(__F16C__) && !defined(EIGEN_COMP_CLANG)\n  // We can use the optimized fp16 to float and float to fp16 conversion routines\n  #define EIGEN_HAS_FP16_C\n#endif\n\n#if defined __CUDACC__\n  #define EIGEN_VECTORIZE_CUDA\n  #include <vector_types.h>\n  #if defined __CUDACC_VER__ && __CUDACC_VER__ >= 70500\n    #define EIGEN_HAS_CUDA_FP16\n  #endif\n#endif\n\n#if defined EIGEN_HAS_CUDA_FP16\n  #include <host_defines.h>\n  #include <cuda_fp16.h>\n#endif\n\n#if (defined _OPENMP) && (!defined EIGEN_DONT_PARALLELIZE)\n  #define EIGEN_HAS_OPENMP\n#endif\n\n#ifdef EIGEN_HAS_OPENMP\n#include <omp.h>\n#endif\n\n// MSVC for windows mobile does not have the errno.h file\n#if !(EIGEN_COMP_MSVC && EIGEN_OS_WINCE) && !EIGEN_COMP_ARM\n#define EIGEN_HAS_ERRNO\n#endif\n\n#ifdef EIGEN_HAS_ERRNO\n#include <cerrno>\n#endif\n#include <cstddef>\n#include <cstdlib>\n#include <cmath>\n#include <cassert>\n#include <functional>\n#include <iosfwd>\n#include <cstring>\n#include <string>\n#include <limits>\n#include <climits> // for CHAR_BIT\n// for min/max:\n#include <algorithm>\n\n// for std::is_nothrow_move_assignable\n#ifdef EIGEN_INCLUDE_TYPE_TRAITS\n#include <type_traits>\n#endif\n\n// for outputting debug info\n#ifdef EIGEN_DEBUG_ASSIGN\n#include <iostream>\n#endif\n\n// required for __cpuid, needs to be included after cmath\n#if EIGEN_COMP_MSVC && EIGEN_ARCH_i386_OR_x86_64 && !EIGEN_OS_WINCE\n  #include <intrin.h>\n#endif\n\n/** \\brief Namespace containing all symbols from the %Eigen library. */\nnamespace Eigen {\n\ninline static const char *SimdInstructionSetsInUse(void) {\n#if defined(EIGEN_VECTORIZE_AVX512)\n  return \"AVX512, FMA, AVX2, AVX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2\";\n#elif defined(EIGEN_VECTORIZE_AVX)\n  return \"AVX SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2\";\n#elif defined(EIGEN_VECTORIZE_SSE4_2)\n  return \"SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2\";\n#elif defined(EIGEN_VECTORIZE_SSE4_1)\n  return \"SSE, SSE2, SSE3, SSSE3, SSE4.1\";\n#elif defined(EIGEN_VECTORIZE_SSSE3)\n  return \"SSE, SSE2, SSE3, SSSE3\";\n#elif defined(EIGEN_VECTORIZE_SSE3)\n  return \"SSE, SSE2, SSE3\";\n#elif defined(EIGEN_VECTORIZE_SSE2)\n  return \"SSE, SSE2\";\n#elif defined(EIGEN_VECTORIZE_ALTIVEC)\n  return \"AltiVec\";\n#elif defined(EIGEN_VECTORIZE_VSX)\n  return \"VSX\";\n#elif defined(EIGEN_VECTORIZE_NEON)\n  return \"ARM NEON\";\n#elif defined(EIGEN_VECTORIZE_ZVECTOR)\n  return \"S390X ZVECTOR\";\n#else\n  return \"None\";\n#endif\n}\n\n} // end namespace Eigen\n\n#if defined EIGEN2_SUPPORT_STAGE40_FULL_EIGEN3_STRICTNESS || defined EIGEN2_SUPPORT_STAGE30_FULL_EIGEN3_API || defined EIGEN2_SUPPORT_STAGE20_RESOLVE_API_CONFLICTS || defined EIGEN2_SUPPORT_STAGE10_FULL_EIGEN2_API || defined EIGEN2_SUPPORT\n// This will generate an error message:\n#error Eigen2-support is only available up to version 3.2. Please go to \"http://eigen.tuxfamily.org/index.php?title=Eigen2\" for further information\n#endif\n\n// we use size_t frequently and we'll never remember to prepend it with std:: everytime just to\n// ensure QNX/QCC support\nusing std::size_t;\n// gcc 4.6.0 wants std:: for ptrdiff_t\nusing std::ptrdiff_t;\n\n/** \\defgroup Core_Module Core module\n  * This is the main module of Eigen providing dense matrix and vector support\n  * (both fixed and dynamic size) with all the features corresponding to a BLAS library\n  * and much more...\n  *\n  * \\code\n  * #include <Eigen/Core>\n  * \\endcode\n  */\n\n#include \"src/Core/util/Constants.h\"\n#include \"src/Core/util/Meta.h\"\n#include \"src/Core/util/ForwardDeclarations.h\"\n#include \"src/Core/util/StaticAssert.h\"\n#include \"src/Core/util/XprHelper.h\"\n#include \"src/Core/util/Memory.h\"\n\n#include \"src/Core/NumTraits.h\"\n#include \"src/Core/MathFunctions.h\"\n#include \"src/Core/GenericPacketMath.h\"\n#include \"src/Core/MathFunctionsImpl.h\"\n\n#if defined EIGEN_VECTORIZE_AVX512\n  #include \"src/Core/arch/SSE/PacketMath.h\"\n  #include \"src/Core/arch/AVX/PacketMath.h\"\n  #include \"src/Core/arch/AVX512/PacketMath.h\"\n  #include \"src/Core/arch/AVX512/MathFunctions.h\"\n#elif defined EIGEN_VECTORIZE_AVX\n  // Use AVX for floats and doubles, SSE for integers\n  #include \"src/Core/arch/SSE/PacketMath.h\"\n  #include \"src/Core/arch/SSE/Complex.h\"\n  #include \"src/Core/arch/SSE/MathFunctions.h\"\n  #include \"src/Core/arch/AVX/PacketMath.h\"\n  #include \"src/Core/arch/AVX/MathFunctions.h\"\n  #include \"src/Core/arch/AVX/Complex.h\"\n  #include \"src/Core/arch/AVX/TypeCasting.h\"\n#elif defined EIGEN_VECTORIZE_SSE\n  #include \"src/Core/arch/SSE/PacketMath.h\"\n  #include \"src/Core/arch/SSE/MathFunctions.h\"\n  #include \"src/Core/arch/SSE/Complex.h\"\n  #include \"src/Core/arch/SSE/TypeCasting.h\"\n#elif defined(EIGEN_VECTORIZE_ALTIVEC) || defined(EIGEN_VECTORIZE_VSX)\n  #include \"src/Core/arch/AltiVec/PacketMath.h\"\n  #include \"src/Core/arch/AltiVec/MathFunctions.h\"\n  #include \"src/Core/arch/AltiVec/Complex.h\"\n#elif defined EIGEN_VECTORIZE_NEON\n  #include \"src/Core/arch/NEON/PacketMath.h\"\n  #include \"src/Core/arch/NEON/MathFunctions.h\"\n  #include \"src/Core/arch/NEON/Complex.h\"\n#elif defined EIGEN_VECTORIZE_ZVECTOR\n  #include \"src/Core/arch/ZVector/PacketMath.h\"\n  #include \"src/Core/arch/ZVector/MathFunctions.h\"\n  #include \"src/Core/arch/ZVector/Complex.h\"\n#endif\n\n// Half float support\n#include \"src/Core/arch/CUDA/Half.h\"\n#include \"src/Core/arch/CUDA/PacketMathHalf.h\"\n#include \"src/Core/arch/CUDA/TypeCasting.h\"\n\n#if defined EIGEN_VECTORIZE_CUDA\n  #include \"src/Core/arch/CUDA/PacketMath.h\"\n  #include \"src/Core/arch/CUDA/MathFunctions.h\"\n#endif\n\n#include \"src/Core/arch/Default/Settings.h\"\n\n#include \"src/Core/functors/TernaryFunctors.h\"\n#include \"src/Core/functors/BinaryFunctors.h\"\n#include \"src/Core/functors/UnaryFunctors.h\"\n#include \"src/Core/functors/NullaryFunctors.h\"\n#include \"src/Core/functors/StlFunctors.h\"\n#include \"src/Core/functors/AssignmentFunctors.h\"\n\n// Specialized functors to enable the processing of complex numbers\n// on CUDA devices\n#include \"src/Core/arch/CUDA/Complex.h\"\n\n#include \"src/Core/DenseCoeffsBase.h\"\n#include \"src/Core/DenseBase.h\"\n#include \"src/Core/MatrixBase.h\"\n#include \"src/Core/EigenBase.h\"\n\n#include \"src/Core/Product.h\"\n#include \"src/Core/CoreEvaluators.h\"\n#include \"src/Core/AssignEvaluator.h\"\n\n#ifndef EIGEN_PARSED_BY_DOXYGEN // work around Doxygen bug triggered by Assign.h r814874\n                                // at least confirmed with Doxygen 1.5.5 and 1.5.6\n  #include \"src/Core/Assign.h\"\n#endif\n\n#include \"src/Core/ArrayBase.h\"\n#include \"src/Core/util/BlasUtil.h\"\n#include \"src/Core/DenseStorage.h\"\n#include \"src/Core/NestByValue.h\"\n\n// #include \"src/Core/ForceAlignedAccess.h\"\n\n#include \"src/Core/ReturnByValue.h\"\n#include \"src/Core/NoAlias.h\"\n#include \"src/Core/PlainObjectBase.h\"\n#include \"src/Core/Matrix.h\"\n#include \"src/Core/Array.h\"\n#include \"src/Core/CwiseTernaryOp.h\"\n#include \"src/Core/CwiseBinaryOp.h\"\n#include \"src/Core/CwiseUnaryOp.h\"\n#include \"src/Core/CwiseNullaryOp.h\"\n#include \"src/Core/CwiseUnaryView.h\"\n#include \"src/Core/SelfCwiseBinaryOp.h\"\n#include \"src/Core/Dot.h\"\n#include \"src/Core/StableNorm.h\"\n#include \"src/Core/Stride.h\"\n#include \"src/Core/MapBase.h\"\n#include \"src/Core/Map.h\"\n#include \"src/Core/Ref.h\"\n#include \"src/Core/Block.h\"\n#include \"src/Core/VectorBlock.h\"\n#include \"src/Core/Transpose.h\"\n#include \"src/Core/DiagonalMatrix.h\"\n#include \"src/Core/Diagonal.h\"\n#include \"src/Core/DiagonalProduct.h\"\n#include \"src/Core/Redux.h\"\n#include \"src/Core/Visitor.h\"\n#include \"src/Core/Fuzzy.h\"\n#include \"src/Core/IO.h\"\n#include \"src/Core/Swap.h\"\n#include \"src/Core/CommaInitializer.h\"\n#include \"src/Core/GeneralProduct.h\"\n#include \"src/Core/Solve.h\"\n#include \"src/Core/Inverse.h\"\n#include \"src/Core/SolverBase.h\"\n#include \"src/Core/PermutationMatrix.h\"\n#include \"src/Core/Transpositions.h\"\n#include \"src/Core/TriangularMatrix.h\"\n#include \"src/Core/SelfAdjointView.h\"\n#include \"src/Core/products/GeneralBlockPanelKernel.h\"\n#include \"src/Core/products/Parallelizer.h\"\n#include \"src/Core/ProductEvaluators.h\"\n#include \"src/Core/products/GeneralMatrixVector.h\"\n#include \"src/Core/products/GeneralMatrixMatrix.h\"\n#include \"src/Core/SolveTriangular.h\"\n#include \"src/Core/products/GeneralMatrixMatrixTriangular.h\"\n#include \"src/Core/products/SelfadjointMatrixVector.h\"\n#include \"src/Core/products/SelfadjointMatrixMatrix.h\"\n#include \"src/Core/products/SelfadjointProduct.h\"\n#include \"src/Core/products/SelfadjointRank2Update.h\"\n#include \"src/Core/products/TriangularMatrixVector.h\"\n#include \"src/Core/products/TriangularMatrixMatrix.h\"\n#include \"src/Core/products/TriangularSolverMatrix.h\"\n#include \"src/Core/products/TriangularSolverVector.h\"\n#include \"src/Core/BandMatrix.h\"\n#include \"src/Core/CoreIterators.h\"\n#include \"src/Core/ConditionEstimator.h\"\n\n#include \"src/Core/BooleanRedux.h\"\n#include \"src/Core/Select.h\"\n#include \"src/Core/VectorwiseOp.h\"\n#include \"src/Core/Random.h\"\n#include \"src/Core/Replicate.h\"\n#include \"src/Core/Reverse.h\"\n#include \"src/Core/ArrayWrapper.h\"\n\n#ifdef EIGEN_USE_BLAS\n#include \"src/Core/products/GeneralMatrixMatrix_BLAS.h\"\n#include \"src/Core/products/GeneralMatrixVector_BLAS.h\"\n#include \"src/Core/products/GeneralMatrixMatrixTriangular_BLAS.h\"\n#include \"src/Core/products/SelfadjointMatrixMatrix_BLAS.h\"\n#include \"src/Core/products/SelfadjointMatrixVector_BLAS.h\"\n#include \"src/Core/products/TriangularMatrixMatrix_BLAS.h\"\n#include \"src/Core/products/TriangularMatrixVector_BLAS.h\"\n#include \"src/Core/products/TriangularSolverMatrix_BLAS.h\"\n#endif // EIGEN_USE_BLAS\n\n#ifdef EIGEN_USE_MKL_VML\n#include \"src/Core/Assign_MKL.h\"\n#endif\n\n#include \"src/Core/GlobalFunctions.h\"\n\n#include \"src/Core/util/ReenableStupidWarnings.h\"\n\n#endif // EIGEN_CORE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/Dense",
    "content": "#include \"Core\"\n#include \"LU\"\n#include \"Cholesky\"\n#include \"QR\"\n#include \"SVD\"\n#include \"Geometry\"\n#include \"Eigenvalues\"\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/Eigen",
    "content": "#include \"Dense\"\n#include \"Sparse\"\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/Eigenvalues",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_EIGENVALUES_MODULE_H\n#define EIGEN_EIGENVALUES_MODULE_H\n\n#include \"Core\"\n\n#include \"src/Core/util/DisableStupidWarnings.h\"\n\n#include \"Cholesky\"\n#include \"Jacobi\"\n#include \"Householder\"\n#include \"LU\"\n#include \"Geometry\"\n\n/** \\defgroup Eigenvalues_Module Eigenvalues module\n  *\n  *\n  *\n  * This module mainly provides various eigenvalue solvers.\n  * This module also provides some MatrixBase methods, including:\n  *  - MatrixBase::eigenvalues(),\n  *  - MatrixBase::operatorNorm()\n  *\n  * \\code\n  * #include <Eigen/Eigenvalues>\n  * \\endcode\n  */\n\n#include \"src/misc/RealSvd2x2.h\"\n#include \"src/Eigenvalues/Tridiagonalization.h\"\n#include \"src/Eigenvalues/RealSchur.h\"\n#include \"src/Eigenvalues/EigenSolver.h\"\n#include \"src/Eigenvalues/SelfAdjointEigenSolver.h\"\n#include \"src/Eigenvalues/GeneralizedSelfAdjointEigenSolver.h\"\n#include \"src/Eigenvalues/HessenbergDecomposition.h\"\n#include \"src/Eigenvalues/ComplexSchur.h\"\n#include \"src/Eigenvalues/ComplexEigenSolver.h\"\n#include \"src/Eigenvalues/RealQZ.h\"\n#include \"src/Eigenvalues/GeneralizedEigenSolver.h\"\n#include \"src/Eigenvalues/MatrixBaseEigenvalues.h\"\n#ifdef EIGEN_USE_LAPACKE\n#include \"src/misc/lapacke.h\"\n#include \"src/Eigenvalues/RealSchur_LAPACKE.h\"\n#include \"src/Eigenvalues/ComplexSchur_LAPACKE.h\"\n#include \"src/Eigenvalues/SelfAdjointEigenSolver_LAPACKE.h\"\n#endif\n\n#include \"src/Core/util/ReenableStupidWarnings.h\"\n\n#endif // EIGEN_EIGENVALUES_MODULE_H\n/* vim: set filetype=cpp et sw=2 ts=2 ai: */\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/Geometry",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_GEOMETRY_MODULE_H\n#define EIGEN_GEOMETRY_MODULE_H\n\n#include \"Core\"\n\n#include \"src/Core/util/DisableStupidWarnings.h\"\n\n#include \"SVD\"\n#include \"LU\"\n#include <limits>\n\n/** \\defgroup Geometry_Module Geometry module\n  *\n  * This module provides support for:\n  *  - fixed-size homogeneous transformations\n  *  - translation, scaling, 2D and 3D rotations\n  *  - \\link Quaternion quaternions \\endlink\n  *  - cross products (\\ref MatrixBase::cross, \\ref MatrixBase::cross3)\n  *  - orthognal vector generation (\\ref MatrixBase::unitOrthogonal)\n  *  - some linear components: \\link ParametrizedLine parametrized-lines \\endlink and \\link Hyperplane hyperplanes \\endlink\n  *  - \\link AlignedBox axis aligned bounding boxes \\endlink\n  *  - \\link umeyama least-square transformation fitting \\endlink\n  *\n  * \\code\n  * #include <Eigen/Geometry>\n  * \\endcode\n  */\n\n#include \"src/Geometry/OrthoMethods.h\"\n#include \"src/Geometry/EulerAngles.h\"\n\n#include \"src/Geometry/Homogeneous.h\"\n#include \"src/Geometry/RotationBase.h\"\n#include \"src/Geometry/Rotation2D.h\"\n#include \"src/Geometry/Quaternion.h\"\n#include \"src/Geometry/AngleAxis.h\"\n#include \"src/Geometry/Transform.h\"\n#include \"src/Geometry/Translation.h\"\n#include \"src/Geometry/Scaling.h\"\n#include \"src/Geometry/Hyperplane.h\"\n#include \"src/Geometry/ParametrizedLine.h\"\n#include \"src/Geometry/AlignedBox.h\"\n#include \"src/Geometry/Umeyama.h\"\n\n// Use the SSE optimized version whenever possible. At the moment the\n// SSE version doesn't compile when AVX is enabled\n#if defined EIGEN_VECTORIZE_SSE && !defined EIGEN_VECTORIZE_AVX\n#include \"src/Geometry/arch/Geometry_SSE.h\"\n#endif\n\n#include \"src/Core/util/ReenableStupidWarnings.h\"\n\n#endif // EIGEN_GEOMETRY_MODULE_H\n/* vim: set filetype=cpp et sw=2 ts=2 ai: */\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/Householder",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_HOUSEHOLDER_MODULE_H\n#define EIGEN_HOUSEHOLDER_MODULE_H\n\n#include \"Core\"\n\n#include \"src/Core/util/DisableStupidWarnings.h\"\n\n/** \\defgroup Householder_Module Householder module\n  * This module provides Householder transformations.\n  *\n  * \\code\n  * #include <Eigen/Householder>\n  * \\endcode\n  */\n\n#include \"src/Householder/Householder.h\"\n#include \"src/Householder/HouseholderSequence.h\"\n#include \"src/Householder/BlockHouseholder.h\"\n\n#include \"src/Core/util/ReenableStupidWarnings.h\"\n\n#endif // EIGEN_HOUSEHOLDER_MODULE_H\n/* vim: set filetype=cpp et sw=2 ts=2 ai: */\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/IterativeLinearSolvers",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_ITERATIVELINEARSOLVERS_MODULE_H\n#define EIGEN_ITERATIVELINEARSOLVERS_MODULE_H\n\n#include \"SparseCore\"\n#include \"OrderingMethods\"\n\n#include \"src/Core/util/DisableStupidWarnings.h\"\n\n/** \n  * \\defgroup IterativeLinearSolvers_Module IterativeLinearSolvers module\n  *\n  * This module currently provides iterative methods to solve problems of the form \\c A \\c x = \\c b, where \\c A is a squared matrix, usually very large and sparse.\n  * Those solvers are accessible via the following classes:\n  *  - ConjugateGradient for selfadjoint (hermitian) matrices,\n  *  - LeastSquaresConjugateGradient for rectangular least-square problems,\n  *  - BiCGSTAB for general square matrices.\n  *\n  * These iterative solvers are associated with some preconditioners:\n  *  - IdentityPreconditioner - not really useful\n  *  - DiagonalPreconditioner - also called Jacobi preconditioner, work very well on diagonal dominant matrices.\n  *  - IncompleteLUT - incomplete LU factorization with dual thresholding\n  *\n  * Such problems can also be solved using the direct sparse decomposition modules: SparseCholesky, CholmodSupport, UmfPackSupport, SuperLUSupport.\n  *\n    \\code\n    #include <Eigen/IterativeLinearSolvers>\n    \\endcode\n  */\n\n#include \"src/IterativeLinearSolvers/SolveWithGuess.h\"\n#include \"src/IterativeLinearSolvers/IterativeSolverBase.h\"\n#include \"src/IterativeLinearSolvers/BasicPreconditioners.h\"\n#include \"src/IterativeLinearSolvers/ConjugateGradient.h\"\n#include \"src/IterativeLinearSolvers/LeastSquareConjugateGradient.h\"\n#include \"src/IterativeLinearSolvers/BiCGSTAB.h\"\n#include \"src/IterativeLinearSolvers/IncompleteLUT.h\"\n#include \"src/IterativeLinearSolvers/IncompleteCholesky.h\"\n\n#include \"src/Core/util/ReenableStupidWarnings.h\"\n\n#endif // EIGEN_ITERATIVELINEARSOLVERS_MODULE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/Jacobi",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_JACOBI_MODULE_H\n#define EIGEN_JACOBI_MODULE_H\n\n#include \"Core\"\n\n#include \"src/Core/util/DisableStupidWarnings.h\"\n\n/** \\defgroup Jacobi_Module Jacobi module\n  * This module provides Jacobi and Givens rotations.\n  *\n  * \\code\n  * #include <Eigen/Jacobi>\n  * \\endcode\n  *\n  * In addition to listed classes, it defines the two following MatrixBase methods to apply a Jacobi or Givens rotation:\n  *  - MatrixBase::applyOnTheLeft()\n  *  - MatrixBase::applyOnTheRight().\n  */\n\n#include \"src/Jacobi/Jacobi.h\"\n\n#include \"src/Core/util/ReenableStupidWarnings.h\"\n\n#endif // EIGEN_JACOBI_MODULE_H\n/* vim: set filetype=cpp et sw=2 ts=2 ai: */\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/LU",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_LU_MODULE_H\n#define EIGEN_LU_MODULE_H\n\n#include \"Core\"\n\n#include \"src/Core/util/DisableStupidWarnings.h\"\n\n/** \\defgroup LU_Module LU module\n  * This module includes %LU decomposition and related notions such as matrix inversion and determinant.\n  * This module defines the following MatrixBase methods:\n  *  - MatrixBase::inverse()\n  *  - MatrixBase::determinant()\n  *\n  * \\code\n  * #include <Eigen/LU>\n  * \\endcode\n  */\n\n#include \"src/misc/Kernel.h\"\n#include \"src/misc/Image.h\"\n#include \"src/LU/FullPivLU.h\"\n#include \"src/LU/PartialPivLU.h\"\n#ifdef EIGEN_USE_LAPACKE\n#include \"src/misc/lapacke.h\"\n#include \"src/LU/PartialPivLU_LAPACKE.h\"\n#endif\n#include \"src/LU/Determinant.h\"\n#include \"src/LU/InverseImpl.h\"\n\n// Use the SSE optimized version whenever possible. At the moment the\n// SSE version doesn't compile when AVX is enabled\n#if defined EIGEN_VECTORIZE_SSE && !defined EIGEN_VECTORIZE_AVX\n  #include \"src/LU/arch/Inverse_SSE.h\"\n#endif\n\n#include \"src/Core/util/ReenableStupidWarnings.h\"\n\n#endif // EIGEN_LU_MODULE_H\n/* vim: set filetype=cpp et sw=2 ts=2 ai: */\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/MetisSupport",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_METISSUPPORT_MODULE_H\n#define EIGEN_METISSUPPORT_MODULE_H\n\n#include \"SparseCore\"\n\n#include \"src/Core/util/DisableStupidWarnings.h\"\n\nextern \"C\" {\n#include <metis.h>\n}\n\n\n/** \\ingroup Support_modules\n  * \\defgroup MetisSupport_Module MetisSupport module\n  *\n  * \\code\n  * #include <Eigen/MetisSupport>\n  * \\endcode\n  * This module defines an interface to the METIS reordering package (http://glaros.dtc.umn.edu/gkhome/views/metis). \n  * It can be used just as any other built-in method as explained in \\link OrderingMethods_Module here. \\endlink\n  */\n\n\n#include \"src/MetisSupport/MetisSupport.h\"\n\n#include \"src/Core/util/ReenableStupidWarnings.h\"\n\n#endif // EIGEN_METISSUPPORT_MODULE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/OrderingMethods",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_ORDERINGMETHODS_MODULE_H\n#define EIGEN_ORDERINGMETHODS_MODULE_H\n\n#include \"SparseCore\"\n\n#include \"src/Core/util/DisableStupidWarnings.h\"\n\n/** \n  * \\defgroup OrderingMethods_Module OrderingMethods module\n  *\n  * This module is currently for internal use only\n  * \n  * It defines various built-in and external ordering methods for sparse matrices. \n  * They are typically used to reduce the number of elements during \n  * the sparse matrix decomposition (LLT, LU, QR).\n  * Precisely, in a preprocessing step, a permutation matrix P is computed using \n  * those ordering methods and applied to the columns of the matrix. \n  * Using for instance the sparse Cholesky decomposition, it is expected that \n  * the nonzeros elements in LLT(A*P) will be much smaller than that in LLT(A).\n  * \n  * \n  * Usage : \n  * \\code\n  * #include <Eigen/OrderingMethods>\n  * \\endcode\n  * \n  * A simple usage is as a template parameter in the sparse decomposition classes : \n  * \n  * \\code \n  * SparseLU<MatrixType, COLAMDOrdering<int> > solver;\n  * \\endcode \n  * \n  * \\code \n  * SparseQR<MatrixType, COLAMDOrdering<int> > solver;\n  * \\endcode\n  * \n  * It is possible as well to call directly a particular ordering method for your own purpose, \n  * \\code \n  * AMDOrdering<int> ordering;\n  * PermutationMatrix<Dynamic, Dynamic, int> perm;\n  * SparseMatrix<double> A; \n  * //Fill the matrix ...\n  * \n  * ordering(A, perm); // Call AMD\n  * \\endcode\n  * \n  * \\note Some of these methods (like AMD or METIS), need the sparsity pattern \n  * of the input matrix to be symmetric. When the matrix is structurally unsymmetric, \n  * Eigen computes internally the pattern of \\f$A^T*A\\f$ before calling the method.\n  * If your matrix is already symmetric (at leat in structure), you can avoid that\n  * by calling the method with a SelfAdjointView type.\n  * \n  * \\code\n  *  // Call the ordering on the pattern of the lower triangular matrix A\n  * ordering(A.selfadjointView<Lower>(), perm);\n  * \\endcode\n  */\n\n#ifndef EIGEN_MPL2_ONLY\n#include \"src/OrderingMethods/Amd.h\"\n#endif\n\n#include \"src/OrderingMethods/Ordering.h\"\n#include \"src/Core/util/ReenableStupidWarnings.h\"\n\n#endif // EIGEN_ORDERINGMETHODS_MODULE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/PaStiXSupport",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_PASTIXSUPPORT_MODULE_H\n#define EIGEN_PASTIXSUPPORT_MODULE_H\n\n#include \"SparseCore\"\n\n#include \"src/Core/util/DisableStupidWarnings.h\"\n\nextern \"C\" {\n#include <pastix_nompi.h>\n#include <pastix.h>\n}\n\n#ifdef complex\n#undef complex\n#endif\n\n/** \\ingroup Support_modules\n  * \\defgroup PaStiXSupport_Module PaStiXSupport module\n  * \n  * This module provides an interface to the <a href=\"http://pastix.gforge.inria.fr/\">PaSTiX</a> library.\n  * PaSTiX is a general \\b supernodal, \\b parallel and \\b opensource sparse solver.\n  * It provides the two following main factorization classes:\n  * - class PastixLLT : a supernodal, parallel LLt Cholesky factorization.\n  * - class PastixLDLT: a supernodal, parallel LDLt Cholesky factorization.\n  * - class PastixLU : a supernodal, parallel LU factorization (optimized for a symmetric pattern).\n  * \n  * \\code\n  * #include <Eigen/PaStiXSupport>\n  * \\endcode\n  *\n  * In order to use this module, the PaSTiX headers must be accessible from the include paths, and your binary must be linked to the PaSTiX library and its dependencies.\n  * The dependencies depend on how PaSTiX has been compiled.\n  * For a cmake based project, you can use our FindPaSTiX.cmake module to help you in this task.\n  *\n  */\n\n#include \"src/PaStiXSupport/PaStiXSupport.h\"\n\n#include \"src/Core/util/ReenableStupidWarnings.h\"\n\n#endif // EIGEN_PASTIXSUPPORT_MODULE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/PardisoSupport",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_PARDISOSUPPORT_MODULE_H\n#define EIGEN_PARDISOSUPPORT_MODULE_H\n\n#include \"SparseCore\"\n\n#include \"src/Core/util/DisableStupidWarnings.h\"\n\n#include <mkl_pardiso.h>\n\n/** \\ingroup Support_modules\n  * \\defgroup PardisoSupport_Module PardisoSupport module\n  *\n  * This module brings support for the Intel(R) MKL PARDISO direct sparse solvers.\n  *\n  * \\code\n  * #include <Eigen/PardisoSupport>\n  * \\endcode\n  *\n  * In order to use this module, the MKL headers must be accessible from the include paths, and your binary must be linked to the MKL library and its dependencies.\n  * See this \\ref TopicUsingIntelMKL \"page\" for more information on MKL-Eigen integration.\n  * \n  */\n\n#include \"src/PardisoSupport/PardisoSupport.h\"\n\n#include \"src/Core/util/ReenableStupidWarnings.h\"\n\n#endif // EIGEN_PARDISOSUPPORT_MODULE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/QR",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_QR_MODULE_H\n#define EIGEN_QR_MODULE_H\n\n#include \"Core\"\n\n#include \"src/Core/util/DisableStupidWarnings.h\"\n\n#include \"Cholesky\"\n#include \"Jacobi\"\n#include \"Householder\"\n\n/** \\defgroup QR_Module QR module\n  *\n  *\n  *\n  * This module provides various QR decompositions\n  * This module also provides some MatrixBase methods, including:\n  *  - MatrixBase::householderQr()\n  *  - MatrixBase::colPivHouseholderQr()\n  *  - MatrixBase::fullPivHouseholderQr()\n  *\n  * \\code\n  * #include <Eigen/QR>\n  * \\endcode\n  */\n\n#include \"src/QR/HouseholderQR.h\"\n#include \"src/QR/FullPivHouseholderQR.h\"\n#include \"src/QR/ColPivHouseholderQR.h\"\n#include \"src/QR/CompleteOrthogonalDecomposition.h\"\n#ifdef EIGEN_USE_LAPACKE\n#include \"src/misc/lapacke.h\"\n#include \"src/QR/HouseholderQR_LAPACKE.h\"\n#include \"src/QR/ColPivHouseholderQR_LAPACKE.h\"\n#endif\n\n#include \"src/Core/util/ReenableStupidWarnings.h\"\n\n#endif // EIGEN_QR_MODULE_H\n/* vim: set filetype=cpp et sw=2 ts=2 ai: */\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/QtAlignedMalloc",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_QTMALLOC_MODULE_H\n#define EIGEN_QTMALLOC_MODULE_H\n\n#include \"Core\"\n\n#if (!EIGEN_MALLOC_ALREADY_ALIGNED)\n\n#include \"src/Core/util/DisableStupidWarnings.h\"\n\nvoid *qMalloc(size_t size)\n{\n  return Eigen::internal::aligned_malloc(size);\n}\n\nvoid qFree(void *ptr)\n{\n  Eigen::internal::aligned_free(ptr);\n}\n\nvoid *qRealloc(void *ptr, size_t size)\n{\n  void* newPtr = Eigen::internal::aligned_malloc(size);\n  memcpy(newPtr, ptr, size);\n  Eigen::internal::aligned_free(ptr);\n  return newPtr;\n}\n\n#include \"src/Core/util/ReenableStupidWarnings.h\"\n\n#endif\n\n#endif // EIGEN_QTMALLOC_MODULE_H\n/* vim: set filetype=cpp et sw=2 ts=2 ai: */\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/SPQRSupport",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SPQRSUPPORT_MODULE_H\n#define EIGEN_SPQRSUPPORT_MODULE_H\n\n#include \"SparseCore\"\n\n#include \"src/Core/util/DisableStupidWarnings.h\"\n\n#include \"SuiteSparseQR.hpp\"\n\n/** \\ingroup Support_modules\n  * \\defgroup SPQRSupport_Module SuiteSparseQR module\n  * \n  * This module provides an interface to the SPQR library, which is part of the <a href=\"http://www.suitesparse.com\">suitesparse</a> package.\n  *\n  * \\code\n  * #include <Eigen/SPQRSupport>\n  * \\endcode\n  *\n  * In order to use this module, the SPQR headers must be accessible from the include paths, and your binary must be linked to the SPQR library and its dependencies (Cholmod, AMD, COLAMD,...).\n  * For a cmake based project, you can use our FindSPQR.cmake and FindCholmod.Cmake modules\n  *\n  */\n\n#include \"src/CholmodSupport/CholmodSupport.h\"\n#include \"src/SPQRSupport/SuiteSparseQRSupport.h\"\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/SVD",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SVD_MODULE_H\n#define EIGEN_SVD_MODULE_H\n\n#include \"QR\"\n#include \"Householder\"\n#include \"Jacobi\"\n\n#include \"src/Core/util/DisableStupidWarnings.h\"\n\n/** \\defgroup SVD_Module SVD module\n  *\n  *\n  *\n  * This module provides SVD decomposition for matrices (both real and complex).\n  * Two decomposition algorithms are provided:\n  *  - JacobiSVD implementing two-sided Jacobi iterations is numerically very accurate, fast for small matrices, but very slow for larger ones.\n  *  - BDCSVD implementing a recursive divide & conquer strategy on top of an upper-bidiagonalization which remains fast for large problems.\n  * These decompositions are accessible via the respective classes and following MatrixBase methods:\n  *  - MatrixBase::jacobiSvd()\n  *  - MatrixBase::bdcSvd()\n  *\n  * \\code\n  * #include <Eigen/SVD>\n  * \\endcode\n  */\n\n#include \"src/misc/RealSvd2x2.h\"\n#include \"src/SVD/UpperBidiagonalization.h\"\n#include \"src/SVD/SVDBase.h\"\n#include \"src/SVD/JacobiSVD.h\"\n#include \"src/SVD/BDCSVD.h\"\n#if defined(EIGEN_USE_LAPACKE) && !defined(EIGEN_USE_LAPACKE_STRICT)\n#include \"src/misc/lapacke.h\"\n#include \"src/SVD/JacobiSVD_LAPACKE.h\"\n#endif\n\n#include \"src/Core/util/ReenableStupidWarnings.h\"\n\n#endif // EIGEN_SVD_MODULE_H\n/* vim: set filetype=cpp et sw=2 ts=2 ai: */\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/Sparse",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SPARSE_MODULE_H\n#define EIGEN_SPARSE_MODULE_H\n\n/** \\defgroup Sparse_Module Sparse meta-module\n  *\n  * Meta-module including all related modules:\n  * - \\ref SparseCore_Module\n  * - \\ref OrderingMethods_Module\n  * - \\ref SparseCholesky_Module\n  * - \\ref SparseLU_Module\n  * - \\ref SparseQR_Module\n  * - \\ref IterativeLinearSolvers_Module\n  *\n    \\code\n    #include <Eigen/Sparse>\n    \\endcode\n  */\n\n#include \"SparseCore\"\n#include \"OrderingMethods\"\n#include \"SparseCholesky\"\n#include \"SparseLU\"\n#include \"SparseQR\"\n#include \"IterativeLinearSolvers\"\n\n#endif // EIGEN_SPARSE_MODULE_H\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/SparseCholesky",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2013 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SPARSECHOLESKY_MODULE_H\n#define EIGEN_SPARSECHOLESKY_MODULE_H\n\n#include \"SparseCore\"\n#include \"OrderingMethods\"\n\n#include \"src/Core/util/DisableStupidWarnings.h\"\n\n/** \n  * \\defgroup SparseCholesky_Module SparseCholesky module\n  *\n  * This module currently provides two variants of the direct sparse Cholesky decomposition for selfadjoint (hermitian) matrices.\n  * Those decompositions are accessible via the following classes:\n  *  - SimplicialLLt,\n  *  - SimplicialLDLt\n  *\n  * Such problems can also be solved using the ConjugateGradient solver from the IterativeLinearSolvers module.\n  *\n  * \\code\n  * #include <Eigen/SparseCholesky>\n  * \\endcode\n  */\n\n#ifdef EIGEN_MPL2_ONLY\n#error The SparseCholesky module has nothing to offer in MPL2 only mode\n#endif\n\n#include \"src/SparseCholesky/SimplicialCholesky.h\"\n\n#ifndef EIGEN_MPL2_ONLY\n#include \"src/SparseCholesky/SimplicialCholesky_impl.h\"\n#endif\n\n#include \"src/Core/util/ReenableStupidWarnings.h\"\n\n#endif // EIGEN_SPARSECHOLESKY_MODULE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/SparseCore",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SPARSECORE_MODULE_H\n#define EIGEN_SPARSECORE_MODULE_H\n\n#include \"Core\"\n\n#include \"src/Core/util/DisableStupidWarnings.h\"\n\n#include <vector>\n#include <map>\n#include <cstdlib>\n#include <cstring>\n#include <algorithm>\n\n/** \n  * \\defgroup SparseCore_Module SparseCore module\n  *\n  * This module provides a sparse matrix representation, and basic associated matrix manipulations\n  * and operations.\n  *\n  * See the \\ref TutorialSparse \"Sparse tutorial\"\n  *\n  * \\code\n  * #include <Eigen/SparseCore>\n  * \\endcode\n  *\n  * This module depends on: Core.\n  */\n\n#include \"src/SparseCore/SparseUtil.h\"\n#include \"src/SparseCore/SparseMatrixBase.h\"\n#include \"src/SparseCore/SparseAssign.h\"\n#include \"src/SparseCore/CompressedStorage.h\"\n#include \"src/SparseCore/AmbiVector.h\"\n#include \"src/SparseCore/SparseCompressedBase.h\"\n#include \"src/SparseCore/SparseMatrix.h\"\n#include \"src/SparseCore/SparseMap.h\"\n#include \"src/SparseCore/MappedSparseMatrix.h\"\n#include \"src/SparseCore/SparseVector.h\"\n#include \"src/SparseCore/SparseRef.h\"\n#include \"src/SparseCore/SparseCwiseUnaryOp.h\"\n#include \"src/SparseCore/SparseCwiseBinaryOp.h\"\n#include \"src/SparseCore/SparseTranspose.h\"\n#include \"src/SparseCore/SparseBlock.h\"\n#include \"src/SparseCore/SparseDot.h\"\n#include \"src/SparseCore/SparseRedux.h\"\n#include \"src/SparseCore/SparseView.h\"\n#include \"src/SparseCore/SparseDiagonalProduct.h\"\n#include \"src/SparseCore/ConservativeSparseSparseProduct.h\"\n#include \"src/SparseCore/SparseSparseProductWithPruning.h\"\n#include \"src/SparseCore/SparseProduct.h\"\n#include \"src/SparseCore/SparseDenseProduct.h\"\n#include \"src/SparseCore/SparseSelfAdjointView.h\"\n#include \"src/SparseCore/SparseTriangularView.h\"\n#include \"src/SparseCore/TriangularSolver.h\"\n#include \"src/SparseCore/SparsePermutation.h\"\n#include \"src/SparseCore/SparseFuzzy.h\"\n#include \"src/SparseCore/SparseSolverBase.h\"\n\n#include \"src/Core/util/ReenableStupidWarnings.h\"\n\n#endif // EIGEN_SPARSECORE_MODULE_H\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/SparseLU",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2012 Désiré Nuentsa-Wakam <desire.nuentsa_wakam@inria.fr>\n// Copyright (C) 2012 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SPARSELU_MODULE_H\n#define EIGEN_SPARSELU_MODULE_H\n\n#include \"SparseCore\"\n\n/** \n  * \\defgroup SparseLU_Module SparseLU module\n  * This module defines a supernodal factorization of general sparse matrices.\n  * The code is fully optimized for supernode-panel updates with specialized kernels.\n  * Please, see the documentation of the SparseLU class for more details.\n  */\n\n// Ordering interface\n#include \"OrderingMethods\"\n\n#include \"src/SparseLU/SparseLU_gemm_kernel.h\"\n\n#include \"src/SparseLU/SparseLU_Structs.h\"\n#include \"src/SparseLU/SparseLU_SupernodalMatrix.h\"\n#include \"src/SparseLU/SparseLUImpl.h\"\n#include \"src/SparseCore/SparseColEtree.h\"\n#include \"src/SparseLU/SparseLU_Memory.h\"\n#include \"src/SparseLU/SparseLU_heap_relax_snode.h\"\n#include \"src/SparseLU/SparseLU_relax_snode.h\"\n#include \"src/SparseLU/SparseLU_pivotL.h\"\n#include \"src/SparseLU/SparseLU_panel_dfs.h\"\n#include \"src/SparseLU/SparseLU_kernel_bmod.h\"\n#include \"src/SparseLU/SparseLU_panel_bmod.h\"\n#include \"src/SparseLU/SparseLU_column_dfs.h\"\n#include \"src/SparseLU/SparseLU_column_bmod.h\"\n#include \"src/SparseLU/SparseLU_copy_to_ucol.h\"\n#include \"src/SparseLU/SparseLU_pruneL.h\"\n#include \"src/SparseLU/SparseLU_Utils.h\"\n#include \"src/SparseLU/SparseLU.h\"\n\n#endif // EIGEN_SPARSELU_MODULE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/SparseQR",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SPARSEQR_MODULE_H\n#define EIGEN_SPARSEQR_MODULE_H\n\n#include \"SparseCore\"\n#include \"OrderingMethods\"\n#include \"src/Core/util/DisableStupidWarnings.h\"\n\n/** \\defgroup SparseQR_Module SparseQR module\n  * \\brief Provides QR decomposition for sparse matrices\n  * \n  * This module provides a simplicial version of the left-looking Sparse QR decomposition. \n  * The columns of the input matrix should be reordered to limit the fill-in during the \n  * decomposition. Built-in methods (COLAMD, AMD) or external  methods (METIS) can be used to this end.\n  * See the \\link OrderingMethods_Module OrderingMethods\\endlink module for the list \n  * of built-in and external ordering methods.\n  * \n  * \\code\n  * #include <Eigen/SparseQR>\n  * \\endcode\n  * \n  * \n  */\n\n#include \"OrderingMethods\"\n#include \"src/SparseCore/SparseColEtree.h\"\n#include \"src/SparseQR/SparseQR.h\"\n\n#include \"src/Core/util/ReenableStupidWarnings.h\"\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/StdDeque",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2009 Hauke Heibel <hauke.heibel@googlemail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_STDDEQUE_MODULE_H\n#define EIGEN_STDDEQUE_MODULE_H\n\n#include \"Core\"\n#include <deque>\n\n#if EIGEN_COMP_MSVC && EIGEN_OS_WIN64 /* MSVC auto aligns in 64 bit builds */\n\n#define EIGEN_DEFINE_STL_DEQUE_SPECIALIZATION(...)\n\n#else\n\n#include \"src/StlSupport/StdDeque.h\"\n\n#endif\n\n#endif // EIGEN_STDDEQUE_MODULE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/StdList",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009 Hauke Heibel <hauke.heibel@googlemail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_STDLIST_MODULE_H\n#define EIGEN_STDLIST_MODULE_H\n\n#include \"Core\"\n#include <list>\n\n#if EIGEN_COMP_MSVC && EIGEN_OS_WIN64 /* MSVC auto aligns in 64 bit builds */    \n\n#define EIGEN_DEFINE_STL_LIST_SPECIALIZATION(...)\n\n#else\n\n#include \"src/StlSupport/StdList.h\"\n\n#endif\n\n#endif // EIGEN_STDLIST_MODULE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/StdVector",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2009 Hauke Heibel <hauke.heibel@googlemail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_STDVECTOR_MODULE_H\n#define EIGEN_STDVECTOR_MODULE_H\n\n#include \"Core\"\n#include <vector>\n\n#if EIGEN_COMP_MSVC && EIGEN_OS_WIN64 /* MSVC auto aligns in 64 bit builds */\n\n#define EIGEN_DEFINE_STL_VECTOR_SPECIALIZATION(...)\n\n#else\n\n#include \"src/StlSupport/StdVector.h\"\n\n#endif\n\n#endif // EIGEN_STDVECTOR_MODULE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/SuperLUSupport",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SUPERLUSUPPORT_MODULE_H\n#define EIGEN_SUPERLUSUPPORT_MODULE_H\n\n#include \"SparseCore\"\n\n#include \"src/Core/util/DisableStupidWarnings.h\"\n\n#ifdef EMPTY\n#define EIGEN_EMPTY_WAS_ALREADY_DEFINED\n#endif\n\ntypedef int int_t;\n#include <slu_Cnames.h>\n#include <supermatrix.h>\n#include <slu_util.h>\n\n// slu_util.h defines a preprocessor token named EMPTY which is really polluting,\n// so we remove it in favor of a SUPERLU_EMPTY token.\n// If EMPTY was already defined then we don't undef it.\n\n#if defined(EIGEN_EMPTY_WAS_ALREADY_DEFINED)\n# undef EIGEN_EMPTY_WAS_ALREADY_DEFINED\n#elif defined(EMPTY)\n# undef EMPTY\n#endif\n\n#define SUPERLU_EMPTY (-1)\n\nnamespace Eigen { struct SluMatrix; }\n\n/** \\ingroup Support_modules\n  * \\defgroup SuperLUSupport_Module SuperLUSupport module\n  *\n  * This module provides an interface to the <a href=\"http://crd-legacy.lbl.gov/~xiaoye/SuperLU/\">SuperLU</a> library.\n  * It provides the following factorization class:\n  * - class SuperLU: a supernodal sequential LU factorization.\n  * - class SuperILU: a supernodal sequential incomplete LU factorization (to be used as a preconditioner for iterative methods).\n  *\n  * \\warning This wrapper requires at least versions 4.0 of SuperLU. The 3.x versions are not supported.\n  *\n  * \\warning When including this module, you have to use SUPERLU_EMPTY instead of EMPTY which is no longer defined because it is too polluting.\n  *\n  * \\code\n  * #include <Eigen/SuperLUSupport>\n  * \\endcode\n  *\n  * In order to use this module, the superlu headers must be accessible from the include paths, and your binary must be linked to the superlu library and its dependencies.\n  * The dependencies depend on how superlu has been compiled.\n  * For a cmake based project, you can use our FindSuperLU.cmake module to help you in this task.\n  *\n  */\n\n#include \"src/SuperLUSupport/SuperLUSupport.h\"\n\n#include \"src/Core/util/ReenableStupidWarnings.h\"\n\n#endif // EIGEN_SUPERLUSUPPORT_MODULE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/UmfPackSupport",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_UMFPACKSUPPORT_MODULE_H\n#define EIGEN_UMFPACKSUPPORT_MODULE_H\n\n#include \"SparseCore\"\n\n#include \"src/Core/util/DisableStupidWarnings.h\"\n\nextern \"C\" {\n#include <umfpack.h>\n}\n\n/** \\ingroup Support_modules\n  * \\defgroup UmfPackSupport_Module UmfPackSupport module\n  *\n  * This module provides an interface to the UmfPack library which is part of the <a href=\"http://www.suitesparse.com\">suitesparse</a> package.\n  * It provides the following factorization class:\n  * - class UmfPackLU: a multifrontal sequential LU factorization.\n  *\n  * \\code\n  * #include <Eigen/UmfPackSupport>\n  * \\endcode\n  *\n  * In order to use this module, the umfpack headers must be accessible from the include paths, and your binary must be linked to the umfpack library and its dependencies.\n  * The dependencies depend on how umfpack has been compiled.\n  * For a cmake based project, you can use our FindUmfPack.cmake module to help you in this task.\n  *\n  */\n\n#include \"src/UmfPackSupport/UmfPackSupport.h\"\n\n#include \"src/Core/util/ReenableStupidWarnings.h\"\n\n#endif // EIGEN_UMFPACKSUPPORT_MODULE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Cholesky/LDLT.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2011 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2009 Keir Mierle <mierle@gmail.com>\n// Copyright (C) 2009 Benoit Jacob <jacob.benoit.1@gmail.com>\n// Copyright (C) 2011 Timothy E. Holy <tim.holy@gmail.com >\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_LDLT_H\n#define EIGEN_LDLT_H\n\nnamespace Eigen {\n\nnamespace internal {\n  template<typename MatrixType, int UpLo> struct LDLT_Traits;\n\n  // PositiveSemiDef means positive semi-definite and non-zero; same for NegativeSemiDef\n  enum SignMatrix { PositiveSemiDef, NegativeSemiDef, ZeroSign, Indefinite };\n}\n\n/** \\ingroup Cholesky_Module\n  *\n  * \\class LDLT\n  *\n  * \\brief Robust Cholesky decomposition of a matrix with pivoting\n  *\n  * \\tparam _MatrixType the type of the matrix of which to compute the LDL^T Cholesky decomposition\n  * \\tparam _UpLo the triangular part that will be used for the decompositon: Lower (default) or Upper.\n  *             The other triangular part won't be read.\n  *\n  * Perform a robust Cholesky decomposition of a positive semidefinite or negative semidefinite\n  * matrix \\f$ A \\f$ such that \\f$ A =  P^TLDL^*P \\f$, where P is a permutation matrix, L\n  * is lower triangular with a unit diagonal and D is a diagonal matrix.\n  *\n  * The decomposition uses pivoting to ensure stability, so that L will have\n  * zeros in the bottom right rank(A) - n submatrix. Avoiding the square root\n  * on D also stabilizes the computation.\n  *\n  * Remember that Cholesky decompositions are not rank-revealing. Also, do not use a Cholesky\n  * decomposition to determine whether a system of equations has a solution.\n  *\n  * This class supports the \\link InplaceDecomposition inplace decomposition \\endlink mechanism.\n  * \n  * \\sa MatrixBase::ldlt(), SelfAdjointView::ldlt(), class LLT\n  */\ntemplate<typename _MatrixType, int _UpLo> class LDLT\n{\n  public:\n    typedef _MatrixType MatrixType;\n    enum {\n      RowsAtCompileTime = MatrixType::RowsAtCompileTime,\n      ColsAtCompileTime = MatrixType::ColsAtCompileTime,\n      MaxRowsAtCompileTime = MatrixType::MaxRowsAtCompileTime,\n      MaxColsAtCompileTime = MatrixType::MaxColsAtCompileTime,\n      UpLo = _UpLo\n    };\n    typedef typename MatrixType::Scalar Scalar;\n    typedef typename NumTraits<typename MatrixType::Scalar>::Real RealScalar;\n    typedef Eigen::Index Index; ///< \\deprecated since Eigen 3.3\n    typedef typename MatrixType::StorageIndex StorageIndex;\n    typedef Matrix<Scalar, RowsAtCompileTime, 1, 0, MaxRowsAtCompileTime, 1> TmpMatrixType;\n\n    typedef Transpositions<RowsAtCompileTime, MaxRowsAtCompileTime> TranspositionType;\n    typedef PermutationMatrix<RowsAtCompileTime, MaxRowsAtCompileTime> PermutationType;\n\n    typedef internal::LDLT_Traits<MatrixType,UpLo> Traits;\n\n    /** \\brief Default Constructor.\n      *\n      * The default constructor is useful in cases in which the user intends to\n      * perform decompositions via LDLT::compute(const MatrixType&).\n      */\n    LDLT()\n      : m_matrix(),\n        m_transpositions(),\n        m_sign(internal::ZeroSign),\n        m_isInitialized(false)\n    {}\n\n    /** \\brief Default Constructor with memory preallocation\n      *\n      * Like the default constructor but with preallocation of the internal data\n      * according to the specified problem \\a size.\n      * \\sa LDLT()\n      */\n    explicit LDLT(Index size)\n      : m_matrix(size, size),\n        m_transpositions(size),\n        m_temporary(size),\n        m_sign(internal::ZeroSign),\n        m_isInitialized(false)\n    {}\n\n    /** \\brief Constructor with decomposition\n      *\n      * This calculates the decomposition for the input \\a matrix.\n      *\n      * \\sa LDLT(Index size)\n      */\n    template<typename InputType>\n    explicit LDLT(const EigenBase<InputType>& matrix)\n      : m_matrix(matrix.rows(), matrix.cols()),\n        m_transpositions(matrix.rows()),\n        m_temporary(matrix.rows()),\n        m_sign(internal::ZeroSign),\n        m_isInitialized(false)\n    {\n      compute(matrix.derived());\n    }\n\n    /** \\brief Constructs a LDLT factorization from a given matrix\n      *\n      * This overloaded constructor is provided for \\link InplaceDecomposition inplace decomposition \\endlink when \\c MatrixType is a Eigen::Ref.\n      *\n      * \\sa LDLT(const EigenBase&)\n      */\n    template<typename InputType>\n    explicit LDLT(EigenBase<InputType>& matrix)\n      : m_matrix(matrix.derived()),\n        m_transpositions(matrix.rows()),\n        m_temporary(matrix.rows()),\n        m_sign(internal::ZeroSign),\n        m_isInitialized(false)\n    {\n      compute(matrix.derived());\n    }\n\n    /** Clear any existing decomposition\n     * \\sa rankUpdate(w,sigma)\n     */\n    void setZero()\n    {\n      m_isInitialized = false;\n    }\n\n    /** \\returns a view of the upper triangular matrix U */\n    inline typename Traits::MatrixU matrixU() const\n    {\n      eigen_assert(m_isInitialized && \"LDLT is not initialized.\");\n      return Traits::getU(m_matrix);\n    }\n\n    /** \\returns a view of the lower triangular matrix L */\n    inline typename Traits::MatrixL matrixL() const\n    {\n      eigen_assert(m_isInitialized && \"LDLT is not initialized.\");\n      return Traits::getL(m_matrix);\n    }\n\n    /** \\returns the permutation matrix P as a transposition sequence.\n      */\n    inline const TranspositionType& transpositionsP() const\n    {\n      eigen_assert(m_isInitialized && \"LDLT is not initialized.\");\n      return m_transpositions;\n    }\n\n    /** \\returns the coefficients of the diagonal matrix D */\n    inline Diagonal<const MatrixType> vectorD() const\n    {\n      eigen_assert(m_isInitialized && \"LDLT is not initialized.\");\n      return m_matrix.diagonal();\n    }\n\n    /** \\returns true if the matrix is positive (semidefinite) */\n    inline bool isPositive() const\n    {\n      eigen_assert(m_isInitialized && \"LDLT is not initialized.\");\n      return m_sign == internal::PositiveSemiDef || m_sign == internal::ZeroSign;\n    }\n\n    /** \\returns true if the matrix is negative (semidefinite) */\n    inline bool isNegative(void) const\n    {\n      eigen_assert(m_isInitialized && \"LDLT is not initialized.\");\n      return m_sign == internal::NegativeSemiDef || m_sign == internal::ZeroSign;\n    }\n\n    /** \\returns a solution x of \\f$ A x = b \\f$ using the current decomposition of A.\n      *\n      * This function also supports in-place solves using the syntax <tt>x = decompositionObject.solve(x)</tt> .\n      *\n      * \\note_about_checking_solutions\n      *\n      * More precisely, this method solves \\f$ A x = b \\f$ using the decomposition \\f$ A = P^T L D L^* P \\f$\n      * by solving the systems \\f$ P^T y_1 = b \\f$, \\f$ L y_2 = y_1 \\f$, \\f$ D y_3 = y_2 \\f$,\n      * \\f$ L^* y_4 = y_3 \\f$ and \\f$ P x = y_4 \\f$ in succession. If the matrix \\f$ A \\f$ is singular, then\n      * \\f$ D \\f$ will also be singular (all the other matrices are invertible). In that case, the\n      * least-square solution of \\f$ D y_3 = y_2 \\f$ is computed. This does not mean that this function\n      * computes the least-square solution of \\f$ A x = b \\f$ is \\f$ A \\f$ is singular.\n      *\n      * \\sa MatrixBase::ldlt(), SelfAdjointView::ldlt()\n      */\n    template<typename Rhs>\n    inline const Solve<LDLT, Rhs>\n    solve(const MatrixBase<Rhs>& b) const\n    {\n      eigen_assert(m_isInitialized && \"LDLT is not initialized.\");\n      eigen_assert(m_matrix.rows()==b.rows()\n                && \"LDLT::solve(): invalid number of rows of the right hand side matrix b\");\n      return Solve<LDLT, Rhs>(*this, b.derived());\n    }\n\n    template<typename Derived>\n    bool solveInPlace(MatrixBase<Derived> &bAndX) const;\n\n    template<typename InputType>\n    LDLT& compute(const EigenBase<InputType>& matrix);\n\n    /** \\returns an estimate of the reciprocal condition number of the matrix of\n     *  which \\c *this is the LDLT decomposition.\n     */\n    RealScalar rcond() const\n    {\n      eigen_assert(m_isInitialized && \"LDLT is not initialized.\");\n      return internal::rcond_estimate_helper(m_l1_norm, *this);\n    }\n\n    template <typename Derived>\n    LDLT& rankUpdate(const MatrixBase<Derived>& w, const RealScalar& alpha=1);\n\n    /** \\returns the internal LDLT decomposition matrix\n      *\n      * TODO: document the storage layout\n      */\n    inline const MatrixType& matrixLDLT() const\n    {\n      eigen_assert(m_isInitialized && \"LDLT is not initialized.\");\n      return m_matrix;\n    }\n\n    MatrixType reconstructedMatrix() const;\n\n    /** \\returns the adjoint of \\c *this, that is, a const reference to the decomposition itself as the underlying matrix is self-adjoint.\n      *\n      * This method is provided for compatibility with other matrix decompositions, thus enabling generic code such as:\n      * \\code x = decomposition.adjoint().solve(b) \\endcode\n      */\n    const LDLT& adjoint() const { return *this; };\n\n    inline Index rows() const { return m_matrix.rows(); }\n    inline Index cols() const { return m_matrix.cols(); }\n\n    /** \\brief Reports whether previous computation was successful.\n      *\n      * \\returns \\c Success if computation was succesful,\n      *          \\c NumericalIssue if the matrix.appears to be negative.\n      */\n    ComputationInfo info() const\n    {\n      eigen_assert(m_isInitialized && \"LDLT is not initialized.\");\n      return m_info;\n    }\n\n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    template<typename RhsType, typename DstType>\n    EIGEN_DEVICE_FUNC\n    void _solve_impl(const RhsType &rhs, DstType &dst) const;\n    #endif\n\n  protected:\n\n    static void check_template_parameters()\n    {\n      EIGEN_STATIC_ASSERT_NON_INTEGER(Scalar);\n    }\n\n    /** \\internal\n      * Used to compute and store the Cholesky decomposition A = L D L^* = U^* D U.\n      * The strict upper part is used during the decomposition, the strict lower\n      * part correspond to the coefficients of L (its diagonal is equal to 1 and\n      * is not stored), and the diagonal entries correspond to D.\n      */\n    MatrixType m_matrix;\n    RealScalar m_l1_norm;\n    TranspositionType m_transpositions;\n    TmpMatrixType m_temporary;\n    internal::SignMatrix m_sign;\n    bool m_isInitialized;\n    ComputationInfo m_info;\n};\n\nnamespace internal {\n\ntemplate<int UpLo> struct ldlt_inplace;\n\ntemplate<> struct ldlt_inplace<Lower>\n{\n  template<typename MatrixType, typename TranspositionType, typename Workspace>\n  static bool unblocked(MatrixType& mat, TranspositionType& transpositions, Workspace& temp, SignMatrix& sign)\n  {\n    using std::abs;\n    typedef typename MatrixType::Scalar Scalar;\n    typedef typename MatrixType::RealScalar RealScalar;\n    typedef typename TranspositionType::StorageIndex IndexType;\n    eigen_assert(mat.rows()==mat.cols());\n    const Index size = mat.rows();\n    bool found_zero_pivot = false;\n    bool ret = true;\n\n    if (size <= 1)\n    {\n      transpositions.setIdentity();\n      if (numext::real(mat.coeff(0,0)) > static_cast<RealScalar>(0) ) sign = PositiveSemiDef;\n      else if (numext::real(mat.coeff(0,0)) < static_cast<RealScalar>(0)) sign = NegativeSemiDef;\n      else sign = ZeroSign;\n      return true;\n    }\n\n    for (Index k = 0; k < size; ++k)\n    {\n      // Find largest diagonal element\n      Index index_of_biggest_in_corner;\n      mat.diagonal().tail(size-k).cwiseAbs().maxCoeff(&index_of_biggest_in_corner);\n      index_of_biggest_in_corner += k;\n\n      transpositions.coeffRef(k) = IndexType(index_of_biggest_in_corner);\n      if(k != index_of_biggest_in_corner)\n      {\n        // apply the transposition while taking care to consider only\n        // the lower triangular part\n        Index s = size-index_of_biggest_in_corner-1; // trailing size after the biggest element\n        mat.row(k).head(k).swap(mat.row(index_of_biggest_in_corner).head(k));\n        mat.col(k).tail(s).swap(mat.col(index_of_biggest_in_corner).tail(s));\n        std::swap(mat.coeffRef(k,k),mat.coeffRef(index_of_biggest_in_corner,index_of_biggest_in_corner));\n        for(Index i=k+1;i<index_of_biggest_in_corner;++i)\n        {\n          Scalar tmp = mat.coeffRef(i,k);\n          mat.coeffRef(i,k) = numext::conj(mat.coeffRef(index_of_biggest_in_corner,i));\n          mat.coeffRef(index_of_biggest_in_corner,i) = numext::conj(tmp);\n        }\n        if(NumTraits<Scalar>::IsComplex)\n          mat.coeffRef(index_of_biggest_in_corner,k) = numext::conj(mat.coeff(index_of_biggest_in_corner,k));\n      }\n\n      // partition the matrix:\n      //       A00 |  -  |  -\n      // lu  = A10 | A11 |  -\n      //       A20 | A21 | A22\n      Index rs = size - k - 1;\n      Block<MatrixType,Dynamic,1> A21(mat,k+1,k,rs,1);\n      Block<MatrixType,1,Dynamic> A10(mat,k,0,1,k);\n      Block<MatrixType,Dynamic,Dynamic> A20(mat,k+1,0,rs,k);\n\n      if(k>0)\n      {\n        temp.head(k) = mat.diagonal().real().head(k).asDiagonal() * A10.adjoint();\n        mat.coeffRef(k,k) -= (A10 * temp.head(k)).value();\n        if(rs>0)\n          A21.noalias() -= A20 * temp.head(k);\n      }\n\n      // In some previous versions of Eigen (e.g., 3.2.1), the scaling was omitted if the pivot\n      // was smaller than the cutoff value. However, since LDLT is not rank-revealing\n      // we should only make sure that we do not introduce INF or NaN values.\n      // Remark that LAPACK also uses 0 as the cutoff value.\n      RealScalar realAkk = numext::real(mat.coeffRef(k,k));\n      bool pivot_is_valid = (abs(realAkk) > RealScalar(0));\n\n      if(k==0 && !pivot_is_valid)\n      {\n        // The entire diagonal is zero, there is nothing more to do\n        // except filling the transpositions, and checking whether the matrix is zero.\n        sign = ZeroSign;\n        for(Index j = 0; j<size; ++j)\n        {\n          transpositions.coeffRef(j) = IndexType(j);\n          ret = ret && (mat.col(j).tail(size-j-1).array()==Scalar(0)).all();\n        }\n        return ret;\n      }\n\n      if((rs>0) && pivot_is_valid)\n        A21 /= realAkk;\n\n      if(found_zero_pivot && pivot_is_valid) ret = false; // factorization failed\n      else if(!pivot_is_valid) found_zero_pivot = true;\n\n      if (sign == PositiveSemiDef) {\n        if (realAkk < static_cast<RealScalar>(0)) sign = Indefinite;\n      } else if (sign == NegativeSemiDef) {\n        if (realAkk > static_cast<RealScalar>(0)) sign = Indefinite;\n      } else if (sign == ZeroSign) {\n        if (realAkk > static_cast<RealScalar>(0)) sign = PositiveSemiDef;\n        else if (realAkk < static_cast<RealScalar>(0)) sign = NegativeSemiDef;\n      }\n    }\n\n    return ret;\n  }\n\n  // Reference for the algorithm: Davis and Hager, \"Multiple Rank\n  // Modifications of a Sparse Cholesky Factorization\" (Algorithm 1)\n  // Trivial rearrangements of their computations (Timothy E. Holy)\n  // allow their algorithm to work for rank-1 updates even if the\n  // original matrix is not of full rank.\n  // Here only rank-1 updates are implemented, to reduce the\n  // requirement for intermediate storage and improve accuracy\n  template<typename MatrixType, typename WDerived>\n  static bool updateInPlace(MatrixType& mat, MatrixBase<WDerived>& w, const typename MatrixType::RealScalar& sigma=1)\n  {\n    using numext::isfinite;\n    typedef typename MatrixType::Scalar Scalar;\n    typedef typename MatrixType::RealScalar RealScalar;\n\n    const Index size = mat.rows();\n    eigen_assert(mat.cols() == size && w.size()==size);\n\n    RealScalar alpha = 1;\n\n    // Apply the update\n    for (Index j = 0; j < size; j++)\n    {\n      // Check for termination due to an original decomposition of low-rank\n      if (!(isfinite)(alpha))\n        break;\n\n      // Update the diagonal terms\n      RealScalar dj = numext::real(mat.coeff(j,j));\n      Scalar wj = w.coeff(j);\n      RealScalar swj2 = sigma*numext::abs2(wj);\n      RealScalar gamma = dj*alpha + swj2;\n\n      mat.coeffRef(j,j) += swj2/alpha;\n      alpha += swj2/dj;\n\n\n      // Update the terms of L\n      Index rs = size-j-1;\n      w.tail(rs) -= wj * mat.col(j).tail(rs);\n      if(gamma != 0)\n        mat.col(j).tail(rs) += (sigma*numext::conj(wj)/gamma)*w.tail(rs);\n    }\n    return true;\n  }\n\n  template<typename MatrixType, typename TranspositionType, typename Workspace, typename WType>\n  static bool update(MatrixType& mat, const TranspositionType& transpositions, Workspace& tmp, const WType& w, const typename MatrixType::RealScalar& sigma=1)\n  {\n    // Apply the permutation to the input w\n    tmp = transpositions * w;\n\n    return ldlt_inplace<Lower>::updateInPlace(mat,tmp,sigma);\n  }\n};\n\ntemplate<> struct ldlt_inplace<Upper>\n{\n  template<typename MatrixType, typename TranspositionType, typename Workspace>\n  static EIGEN_STRONG_INLINE bool unblocked(MatrixType& mat, TranspositionType& transpositions, Workspace& temp, SignMatrix& sign)\n  {\n    Transpose<MatrixType> matt(mat);\n    return ldlt_inplace<Lower>::unblocked(matt, transpositions, temp, sign);\n  }\n\n  template<typename MatrixType, typename TranspositionType, typename Workspace, typename WType>\n  static EIGEN_STRONG_INLINE bool update(MatrixType& mat, TranspositionType& transpositions, Workspace& tmp, WType& w, const typename MatrixType::RealScalar& sigma=1)\n  {\n    Transpose<MatrixType> matt(mat);\n    return ldlt_inplace<Lower>::update(matt, transpositions, tmp, w.conjugate(), sigma);\n  }\n};\n\ntemplate<typename MatrixType> struct LDLT_Traits<MatrixType,Lower>\n{\n  typedef const TriangularView<const MatrixType, UnitLower> MatrixL;\n  typedef const TriangularView<const typename MatrixType::AdjointReturnType, UnitUpper> MatrixU;\n  static inline MatrixL getL(const MatrixType& m) { return MatrixL(m); }\n  static inline MatrixU getU(const MatrixType& m) { return MatrixU(m.adjoint()); }\n};\n\ntemplate<typename MatrixType> struct LDLT_Traits<MatrixType,Upper>\n{\n  typedef const TriangularView<const typename MatrixType::AdjointReturnType, UnitLower> MatrixL;\n  typedef const TriangularView<const MatrixType, UnitUpper> MatrixU;\n  static inline MatrixL getL(const MatrixType& m) { return MatrixL(m.adjoint()); }\n  static inline MatrixU getU(const MatrixType& m) { return MatrixU(m); }\n};\n\n} // end namespace internal\n\n/** Compute / recompute the LDLT decomposition A = L D L^* = U^* D U of \\a matrix\n  */\ntemplate<typename MatrixType, int _UpLo>\ntemplate<typename InputType>\nLDLT<MatrixType,_UpLo>& LDLT<MatrixType,_UpLo>::compute(const EigenBase<InputType>& a)\n{\n  check_template_parameters();\n\n  eigen_assert(a.rows()==a.cols());\n  const Index size = a.rows();\n\n  m_matrix = a.derived();\n\n  // Compute matrix L1 norm = max abs column sum.\n  m_l1_norm = RealScalar(0);\n  // TODO move this code to SelfAdjointView\n  for (Index col = 0; col < size; ++col) {\n    RealScalar abs_col_sum;\n    if (_UpLo == Lower)\n      abs_col_sum = m_matrix.col(col).tail(size - col).template lpNorm<1>() + m_matrix.row(col).head(col).template lpNorm<1>();\n    else\n      abs_col_sum = m_matrix.col(col).head(col).template lpNorm<1>() + m_matrix.row(col).tail(size - col).template lpNorm<1>();\n    if (abs_col_sum > m_l1_norm)\n      m_l1_norm = abs_col_sum;\n  }\n\n  m_transpositions.resize(size);\n  m_isInitialized = false;\n  m_temporary.resize(size);\n  m_sign = internal::ZeroSign;\n\n  m_info = internal::ldlt_inplace<UpLo>::unblocked(m_matrix, m_transpositions, m_temporary, m_sign) ? Success : NumericalIssue;\n\n  m_isInitialized = true;\n  return *this;\n}\n\n/** Update the LDLT decomposition:  given A = L D L^T, efficiently compute the decomposition of A + sigma w w^T.\n * \\param w a vector to be incorporated into the decomposition.\n * \\param sigma a scalar, +1 for updates and -1 for \"downdates,\" which correspond to removing previously-added column vectors. Optional; default value is +1.\n * \\sa setZero()\n  */\ntemplate<typename MatrixType, int _UpLo>\ntemplate<typename Derived>\nLDLT<MatrixType,_UpLo>& LDLT<MatrixType,_UpLo>::rankUpdate(const MatrixBase<Derived>& w, const typename LDLT<MatrixType,_UpLo>::RealScalar& sigma)\n{\n  typedef typename TranspositionType::StorageIndex IndexType;\n  const Index size = w.rows();\n  if (m_isInitialized)\n  {\n    eigen_assert(m_matrix.rows()==size);\n  }\n  else\n  {\n    m_matrix.resize(size,size);\n    m_matrix.setZero();\n    m_transpositions.resize(size);\n    for (Index i = 0; i < size; i++)\n      m_transpositions.coeffRef(i) = IndexType(i);\n    m_temporary.resize(size);\n    m_sign = sigma>=0 ? internal::PositiveSemiDef : internal::NegativeSemiDef;\n    m_isInitialized = true;\n  }\n\n  internal::ldlt_inplace<UpLo>::update(m_matrix, m_transpositions, m_temporary, w, sigma);\n\n  return *this;\n}\n\n#ifndef EIGEN_PARSED_BY_DOXYGEN\ntemplate<typename _MatrixType, int _UpLo>\ntemplate<typename RhsType, typename DstType>\nvoid LDLT<_MatrixType,_UpLo>::_solve_impl(const RhsType &rhs, DstType &dst) const\n{\n  eigen_assert(rhs.rows() == rows());\n  // dst = P b\n  dst = m_transpositions * rhs;\n\n  // dst = L^-1 (P b)\n  matrixL().solveInPlace(dst);\n\n  // dst = D^-1 (L^-1 P b)\n  // more precisely, use pseudo-inverse of D (see bug 241)\n  using std::abs;\n  const typename Diagonal<const MatrixType>::RealReturnType vecD(vectorD());\n  // In some previous versions, tolerance was set to the max of 1/highest and the maximal diagonal entry * epsilon\n  // as motivated by LAPACK's xGELSS:\n  // RealScalar tolerance = numext::maxi(vecD.array().abs().maxCoeff() * NumTraits<RealScalar>::epsilon(),RealScalar(1) / NumTraits<RealScalar>::highest());\n  // However, LDLT is not rank revealing, and so adjusting the tolerance wrt to the highest\n  // diagonal element is not well justified and leads to numerical issues in some cases.\n  // Moreover, Lapack's xSYTRS routines use 0 for the tolerance.\n  RealScalar tolerance = RealScalar(1) / NumTraits<RealScalar>::highest();\n\n  for (Index i = 0; i < vecD.size(); ++i)\n  {\n    if(abs(vecD(i)) > tolerance)\n      dst.row(i) /= vecD(i);\n    else\n      dst.row(i).setZero();\n  }\n\n  // dst = L^-T (D^-1 L^-1 P b)\n  matrixU().solveInPlace(dst);\n\n  // dst = P^-1 (L^-T D^-1 L^-1 P b) = A^-1 b\n  dst = m_transpositions.transpose() * dst;\n}\n#endif\n\n/** \\internal use x = ldlt_object.solve(x);\n  *\n  * This is the \\em in-place version of solve().\n  *\n  * \\param bAndX represents both the right-hand side matrix b and result x.\n  *\n  * \\returns true always! If you need to check for existence of solutions, use another decomposition like LU, QR, or SVD.\n  *\n  * This version avoids a copy when the right hand side matrix b is not\n  * needed anymore.\n  *\n  * \\sa LDLT::solve(), MatrixBase::ldlt()\n  */\ntemplate<typename MatrixType,int _UpLo>\ntemplate<typename Derived>\nbool LDLT<MatrixType,_UpLo>::solveInPlace(MatrixBase<Derived> &bAndX) const\n{\n  eigen_assert(m_isInitialized && \"LDLT is not initialized.\");\n  eigen_assert(m_matrix.rows() == bAndX.rows());\n\n  bAndX = this->solve(bAndX);\n\n  return true;\n}\n\n/** \\returns the matrix represented by the decomposition,\n * i.e., it returns the product: P^T L D L^* P.\n * This function is provided for debug purpose. */\ntemplate<typename MatrixType, int _UpLo>\nMatrixType LDLT<MatrixType,_UpLo>::reconstructedMatrix() const\n{\n  eigen_assert(m_isInitialized && \"LDLT is not initialized.\");\n  const Index size = m_matrix.rows();\n  MatrixType res(size,size);\n\n  // P\n  res.setIdentity();\n  res = transpositionsP() * res;\n  // L^* P\n  res = matrixU() * res;\n  // D(L^*P)\n  res = vectorD().real().asDiagonal() * res;\n  // L(DL^*P)\n  res = matrixL() * res;\n  // P^T (LDL^*P)\n  res = transpositionsP().transpose() * res;\n\n  return res;\n}\n\n/** \\cholesky_module\n  * \\returns the Cholesky decomposition with full pivoting without square root of \\c *this\n  * \\sa MatrixBase::ldlt()\n  */\ntemplate<typename MatrixType, unsigned int UpLo>\ninline const LDLT<typename SelfAdjointView<MatrixType, UpLo>::PlainObject, UpLo>\nSelfAdjointView<MatrixType, UpLo>::ldlt() const\n{\n  return LDLT<PlainObject,UpLo>(m_matrix);\n}\n\n/** \\cholesky_module\n  * \\returns the Cholesky decomposition with full pivoting without square root of \\c *this\n  * \\sa SelfAdjointView::ldlt()\n  */\ntemplate<typename Derived>\ninline const LDLT<typename MatrixBase<Derived>::PlainObject>\nMatrixBase<Derived>::ldlt() const\n{\n  return LDLT<PlainObject>(derived());\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_LDLT_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Cholesky/LLT.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_LLT_H\n#define EIGEN_LLT_H\n\nnamespace Eigen {\n\nnamespace internal{\ntemplate<typename MatrixType, int UpLo> struct LLT_Traits;\n}\n\n/** \\ingroup Cholesky_Module\n  *\n  * \\class LLT\n  *\n  * \\brief Standard Cholesky decomposition (LL^T) of a matrix and associated features\n  *\n  * \\tparam _MatrixType the type of the matrix of which we are computing the LL^T Cholesky decomposition\n  * \\tparam _UpLo the triangular part that will be used for the decompositon: Lower (default) or Upper.\n  *             The other triangular part won't be read.\n  *\n  * This class performs a LL^T Cholesky decomposition of a symmetric, positive definite\n  * matrix A such that A = LL^* = U^*U, where L is lower triangular.\n  *\n  * While the Cholesky decomposition is particularly useful to solve selfadjoint problems like  D^*D x = b,\n  * for that purpose, we recommend the Cholesky decomposition without square root which is more stable\n  * and even faster. Nevertheless, this standard Cholesky decomposition remains useful in many other\n  * situations like generalised eigen problems with hermitian matrices.\n  *\n  * Remember that Cholesky decompositions are not rank-revealing. This LLT decomposition is only stable on positive definite matrices,\n  * use LDLT instead for the semidefinite case. Also, do not use a Cholesky decomposition to determine whether a system of equations\n  * has a solution.\n  *\n  * Example: \\include LLT_example.cpp\n  * Output: \\verbinclude LLT_example.out\n  *\n  * This class supports the \\link InplaceDecomposition inplace decomposition \\endlink mechanism.\n  *\n  * \\sa MatrixBase::llt(), SelfAdjointView::llt(), class LDLT\n  */\n /* HEY THIS DOX IS DISABLED BECAUSE THERE's A BUG EITHER HERE OR IN LDLT ABOUT THAT (OR BOTH)\n  * Note that during the decomposition, only the upper triangular part of A is considered. Therefore,\n  * the strict lower part does not have to store correct values.\n  */\ntemplate<typename _MatrixType, int _UpLo> class LLT\n{\n  public:\n    typedef _MatrixType MatrixType;\n    enum {\n      RowsAtCompileTime = MatrixType::RowsAtCompileTime,\n      ColsAtCompileTime = MatrixType::ColsAtCompileTime,\n      MaxColsAtCompileTime = MatrixType::MaxColsAtCompileTime\n    };\n    typedef typename MatrixType::Scalar Scalar;\n    typedef typename NumTraits<typename MatrixType::Scalar>::Real RealScalar;\n    typedef Eigen::Index Index; ///< \\deprecated since Eigen 3.3\n    typedef typename MatrixType::StorageIndex StorageIndex;\n\n    enum {\n      PacketSize = internal::packet_traits<Scalar>::size,\n      AlignmentMask = int(PacketSize)-1,\n      UpLo = _UpLo\n    };\n\n    typedef internal::LLT_Traits<MatrixType,UpLo> Traits;\n\n    /**\n      * \\brief Default Constructor.\n      *\n      * The default constructor is useful in cases in which the user intends to\n      * perform decompositions via LLT::compute(const MatrixType&).\n      */\n    LLT() : m_matrix(), m_isInitialized(false) {}\n\n    /** \\brief Default Constructor with memory preallocation\n      *\n      * Like the default constructor but with preallocation of the internal data\n      * according to the specified problem \\a size.\n      * \\sa LLT()\n      */\n    explicit LLT(Index size) : m_matrix(size, size),\n                    m_isInitialized(false) {}\n\n    template<typename InputType>\n    explicit LLT(const EigenBase<InputType>& matrix)\n      : m_matrix(matrix.rows(), matrix.cols()),\n        m_isInitialized(false)\n    {\n      compute(matrix.derived());\n    }\n\n    /** \\brief Constructs a LDLT factorization from a given matrix\n      *\n      * This overloaded constructor is provided for \\link InplaceDecomposition inplace decomposition \\endlink when\n      * \\c MatrixType is a Eigen::Ref.\n      *\n      * \\sa LLT(const EigenBase&)\n      */\n    template<typename InputType>\n    explicit LLT(EigenBase<InputType>& matrix)\n      : m_matrix(matrix.derived()),\n        m_isInitialized(false)\n    {\n      compute(matrix.derived());\n    }\n\n    /** \\returns a view of the upper triangular matrix U */\n    inline typename Traits::MatrixU matrixU() const\n    {\n      eigen_assert(m_isInitialized && \"LLT is not initialized.\");\n      return Traits::getU(m_matrix);\n    }\n\n    /** \\returns a view of the lower triangular matrix L */\n    inline typename Traits::MatrixL matrixL() const\n    {\n      eigen_assert(m_isInitialized && \"LLT is not initialized.\");\n      return Traits::getL(m_matrix);\n    }\n\n    /** \\returns the solution x of \\f$ A x = b \\f$ using the current decomposition of A.\n      *\n      * Since this LLT class assumes anyway that the matrix A is invertible, the solution\n      * theoretically exists and is unique regardless of b.\n      *\n      * Example: \\include LLT_solve.cpp\n      * Output: \\verbinclude LLT_solve.out\n      *\n      * \\sa solveInPlace(), MatrixBase::llt(), SelfAdjointView::llt()\n      */\n    template<typename Rhs>\n    inline const Solve<LLT, Rhs>\n    solve(const MatrixBase<Rhs>& b) const\n    {\n      eigen_assert(m_isInitialized && \"LLT is not initialized.\");\n      eigen_assert(m_matrix.rows()==b.rows()\n                && \"LLT::solve(): invalid number of rows of the right hand side matrix b\");\n      return Solve<LLT, Rhs>(*this, b.derived());\n    }\n\n    template<typename Derived>\n    void solveInPlace(MatrixBase<Derived> &bAndX) const;\n\n    template<typename InputType>\n    LLT& compute(const EigenBase<InputType>& matrix);\n\n    /** \\returns an estimate of the reciprocal condition number of the matrix of\n      *  which \\c *this is the Cholesky decomposition.\n      */\n    RealScalar rcond() const\n    {\n      eigen_assert(m_isInitialized && \"LLT is not initialized.\");\n      eigen_assert(m_info == Success && \"LLT failed because matrix appears to be negative\");\n      return internal::rcond_estimate_helper(m_l1_norm, *this);\n    }\n\n    /** \\returns the LLT decomposition matrix\n      *\n      * TODO: document the storage layout\n      */\n    inline const MatrixType& matrixLLT() const\n    {\n      eigen_assert(m_isInitialized && \"LLT is not initialized.\");\n      return m_matrix;\n    }\n\n    MatrixType reconstructedMatrix() const;\n\n\n    /** \\brief Reports whether previous computation was successful.\n      *\n      * \\returns \\c Success if computation was succesful,\n      *          \\c NumericalIssue if the matrix.appears to be negative.\n      */\n    ComputationInfo info() const\n    {\n      eigen_assert(m_isInitialized && \"LLT is not initialized.\");\n      return m_info;\n    }\n\n    /** \\returns the adjoint of \\c *this, that is, a const reference to the decomposition itself as the underlying matrix is self-adjoint.\n      *\n      * This method is provided for compatibility with other matrix decompositions, thus enabling generic code such as:\n      * \\code x = decomposition.adjoint().solve(b) \\endcode\n      */\n    const LLT& adjoint() const { return *this; };\n\n    inline Index rows() const { return m_matrix.rows(); }\n    inline Index cols() const { return m_matrix.cols(); }\n\n    template<typename VectorType>\n    LLT rankUpdate(const VectorType& vec, const RealScalar& sigma = 1);\n\n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    template<typename RhsType, typename DstType>\n    EIGEN_DEVICE_FUNC\n    void _solve_impl(const RhsType &rhs, DstType &dst) const;\n    #endif\n\n  protected:\n\n    static void check_template_parameters()\n    {\n      EIGEN_STATIC_ASSERT_NON_INTEGER(Scalar);\n    }\n\n    /** \\internal\n      * Used to compute and store L\n      * The strict upper part is not used and even not initialized.\n      */\n    MatrixType m_matrix;\n    RealScalar m_l1_norm;\n    bool m_isInitialized;\n    ComputationInfo m_info;\n};\n\nnamespace internal {\n\ntemplate<typename Scalar, int UpLo> struct llt_inplace;\n\ntemplate<typename MatrixType, typename VectorType>\nstatic Index llt_rank_update_lower(MatrixType& mat, const VectorType& vec, const typename MatrixType::RealScalar& sigma)\n{\n  using std::sqrt;\n  typedef typename MatrixType::Scalar Scalar;\n  typedef typename MatrixType::RealScalar RealScalar;\n  typedef typename MatrixType::ColXpr ColXpr;\n  typedef typename internal::remove_all<ColXpr>::type ColXprCleaned;\n  typedef typename ColXprCleaned::SegmentReturnType ColXprSegment;\n  typedef Matrix<Scalar,Dynamic,1> TempVectorType;\n  typedef typename TempVectorType::SegmentReturnType TempVecSegment;\n\n  Index n = mat.cols();\n  eigen_assert(mat.rows()==n && vec.size()==n);\n\n  TempVectorType temp;\n\n  if(sigma>0)\n  {\n    // This version is based on Givens rotations.\n    // It is faster than the other one below, but only works for updates,\n    // i.e., for sigma > 0\n    temp = sqrt(sigma) * vec;\n\n    for(Index i=0; i<n; ++i)\n    {\n      JacobiRotation<Scalar> g;\n      g.makeGivens(mat(i,i), -temp(i), &mat(i,i));\n\n      Index rs = n-i-1;\n      if(rs>0)\n      {\n        ColXprSegment x(mat.col(i).tail(rs));\n        TempVecSegment y(temp.tail(rs));\n        apply_rotation_in_the_plane(x, y, g);\n      }\n    }\n  }\n  else\n  {\n    temp = vec;\n    RealScalar beta = 1;\n    for(Index j=0; j<n; ++j)\n    {\n      RealScalar Ljj = numext::real(mat.coeff(j,j));\n      RealScalar dj = numext::abs2(Ljj);\n      Scalar wj = temp.coeff(j);\n      RealScalar swj2 = sigma*numext::abs2(wj);\n      RealScalar gamma = dj*beta + swj2;\n\n      RealScalar x = dj + swj2/beta;\n      if (x<=RealScalar(0))\n        return j;\n      RealScalar nLjj = sqrt(x);\n      mat.coeffRef(j,j) = nLjj;\n      beta += swj2/dj;\n\n      // Update the terms of L\n      Index rs = n-j-1;\n      if(rs)\n      {\n        temp.tail(rs) -= (wj/Ljj) * mat.col(j).tail(rs);\n        if(gamma != 0)\n          mat.col(j).tail(rs) = (nLjj/Ljj) * mat.col(j).tail(rs) + (nLjj * sigma*numext::conj(wj)/gamma)*temp.tail(rs);\n      }\n    }\n  }\n  return -1;\n}\n\ntemplate<typename Scalar> struct llt_inplace<Scalar, Lower>\n{\n  typedef typename NumTraits<Scalar>::Real RealScalar;\n  template<typename MatrixType>\n  static Index unblocked(MatrixType& mat)\n  {\n    using std::sqrt;\n\n    eigen_assert(mat.rows()==mat.cols());\n    const Index size = mat.rows();\n    for(Index k = 0; k < size; ++k)\n    {\n      Index rs = size-k-1; // remaining size\n\n      Block<MatrixType,Dynamic,1> A21(mat,k+1,k,rs,1);\n      Block<MatrixType,1,Dynamic> A10(mat,k,0,1,k);\n      Block<MatrixType,Dynamic,Dynamic> A20(mat,k+1,0,rs,k);\n\n      RealScalar x = numext::real(mat.coeff(k,k));\n      if (k>0) x -= A10.squaredNorm();\n      if (x<=RealScalar(0))\n        return k;\n      mat.coeffRef(k,k) = x = sqrt(x);\n      if (k>0 && rs>0) A21.noalias() -= A20 * A10.adjoint();\n      if (rs>0) A21 /= x;\n    }\n    return -1;\n  }\n\n  template<typename MatrixType>\n  static Index blocked(MatrixType& m)\n  {\n    eigen_assert(m.rows()==m.cols());\n    Index size = m.rows();\n    if(size<32)\n      return unblocked(m);\n\n    Index blockSize = size/8;\n    blockSize = (blockSize/16)*16;\n    blockSize = (std::min)((std::max)(blockSize,Index(8)), Index(128));\n\n    for (Index k=0; k<size; k+=blockSize)\n    {\n      // partition the matrix:\n      //       A00 |  -  |  -\n      // lu  = A10 | A11 |  -\n      //       A20 | A21 | A22\n      Index bs = (std::min)(blockSize, size-k);\n      Index rs = size - k - bs;\n      Block<MatrixType,Dynamic,Dynamic> A11(m,k,   k,   bs,bs);\n      Block<MatrixType,Dynamic,Dynamic> A21(m,k+bs,k,   rs,bs);\n      Block<MatrixType,Dynamic,Dynamic> A22(m,k+bs,k+bs,rs,rs);\n\n      Index ret;\n      if((ret=unblocked(A11))>=0) return k+ret;\n      if(rs>0) A11.adjoint().template triangularView<Upper>().template solveInPlace<OnTheRight>(A21);\n      if(rs>0) A22.template selfadjointView<Lower>().rankUpdate(A21,typename NumTraits<RealScalar>::Literal(-1)); // bottleneck\n    }\n    return -1;\n  }\n\n  template<typename MatrixType, typename VectorType>\n  static Index rankUpdate(MatrixType& mat, const VectorType& vec, const RealScalar& sigma)\n  {\n    return Eigen::internal::llt_rank_update_lower(mat, vec, sigma);\n  }\n};\n\ntemplate<typename Scalar> struct llt_inplace<Scalar, Upper>\n{\n  typedef typename NumTraits<Scalar>::Real RealScalar;\n\n  template<typename MatrixType>\n  static EIGEN_STRONG_INLINE Index unblocked(MatrixType& mat)\n  {\n    Transpose<MatrixType> matt(mat);\n    return llt_inplace<Scalar, Lower>::unblocked(matt);\n  }\n  template<typename MatrixType>\n  static EIGEN_STRONG_INLINE Index blocked(MatrixType& mat)\n  {\n    Transpose<MatrixType> matt(mat);\n    return llt_inplace<Scalar, Lower>::blocked(matt);\n  }\n  template<typename MatrixType, typename VectorType>\n  static Index rankUpdate(MatrixType& mat, const VectorType& vec, const RealScalar& sigma)\n  {\n    Transpose<MatrixType> matt(mat);\n    return llt_inplace<Scalar, Lower>::rankUpdate(matt, vec.conjugate(), sigma);\n  }\n};\n\ntemplate<typename MatrixType> struct LLT_Traits<MatrixType,Lower>\n{\n  typedef const TriangularView<const MatrixType, Lower> MatrixL;\n  typedef const TriangularView<const typename MatrixType::AdjointReturnType, Upper> MatrixU;\n  static inline MatrixL getL(const MatrixType& m) { return MatrixL(m); }\n  static inline MatrixU getU(const MatrixType& m) { return MatrixU(m.adjoint()); }\n  static bool inplace_decomposition(MatrixType& m)\n  { return llt_inplace<typename MatrixType::Scalar, Lower>::blocked(m)==-1; }\n};\n\ntemplate<typename MatrixType> struct LLT_Traits<MatrixType,Upper>\n{\n  typedef const TriangularView<const typename MatrixType::AdjointReturnType, Lower> MatrixL;\n  typedef const TriangularView<const MatrixType, Upper> MatrixU;\n  static inline MatrixL getL(const MatrixType& m) { return MatrixL(m.adjoint()); }\n  static inline MatrixU getU(const MatrixType& m) { return MatrixU(m); }\n  static bool inplace_decomposition(MatrixType& m)\n  { return llt_inplace<typename MatrixType::Scalar, Upper>::blocked(m)==-1; }\n};\n\n} // end namespace internal\n\n/** Computes / recomputes the Cholesky decomposition A = LL^* = U^*U of \\a matrix\n  *\n  * \\returns a reference to *this\n  *\n  * Example: \\include TutorialLinAlgComputeTwice.cpp\n  * Output: \\verbinclude TutorialLinAlgComputeTwice.out\n  */\ntemplate<typename MatrixType, int _UpLo>\ntemplate<typename InputType>\nLLT<MatrixType,_UpLo>& LLT<MatrixType,_UpLo>::compute(const EigenBase<InputType>& a)\n{\n  check_template_parameters();\n\n  eigen_assert(a.rows()==a.cols());\n  const Index size = a.rows();\n  m_matrix.resize(size, size);\n  m_matrix = a.derived();\n\n  // Compute matrix L1 norm = max abs column sum.\n  m_l1_norm = RealScalar(0);\n  // TODO move this code to SelfAdjointView\n  for (Index col = 0; col < size; ++col) {\n    RealScalar abs_col_sum;\n    if (_UpLo == Lower)\n      abs_col_sum = m_matrix.col(col).tail(size - col).template lpNorm<1>() + m_matrix.row(col).head(col).template lpNorm<1>();\n    else\n      abs_col_sum = m_matrix.col(col).head(col).template lpNorm<1>() + m_matrix.row(col).tail(size - col).template lpNorm<1>();\n    if (abs_col_sum > m_l1_norm)\n      m_l1_norm = abs_col_sum;\n  }\n\n  m_isInitialized = true;\n  bool ok = Traits::inplace_decomposition(m_matrix);\n  m_info = ok ? Success : NumericalIssue;\n\n  return *this;\n}\n\n/** Performs a rank one update (or dowdate) of the current decomposition.\n  * If A = LL^* before the rank one update,\n  * then after it we have LL^* = A + sigma * v v^* where \\a v must be a vector\n  * of same dimension.\n  */\ntemplate<typename _MatrixType, int _UpLo>\ntemplate<typename VectorType>\nLLT<_MatrixType,_UpLo> LLT<_MatrixType,_UpLo>::rankUpdate(const VectorType& v, const RealScalar& sigma)\n{\n  EIGEN_STATIC_ASSERT_VECTOR_ONLY(VectorType);\n  eigen_assert(v.size()==m_matrix.cols());\n  eigen_assert(m_isInitialized);\n  if(internal::llt_inplace<typename MatrixType::Scalar, UpLo>::rankUpdate(m_matrix,v,sigma)>=0)\n    m_info = NumericalIssue;\n  else\n    m_info = Success;\n\n  return *this;\n}\n\n#ifndef EIGEN_PARSED_BY_DOXYGEN\ntemplate<typename _MatrixType,int _UpLo>\ntemplate<typename RhsType, typename DstType>\nvoid LLT<_MatrixType,_UpLo>::_solve_impl(const RhsType &rhs, DstType &dst) const\n{\n  dst = rhs;\n  solveInPlace(dst);\n}\n#endif\n\n/** \\internal use x = llt_object.solve(x);\n  *\n  * This is the \\em in-place version of solve().\n  *\n  * \\param bAndX represents both the right-hand side matrix b and result x.\n  *\n  * This version avoids a copy when the right hand side matrix b is not needed anymore.\n  *\n  * \\sa LLT::solve(), MatrixBase::llt()\n  */\ntemplate<typename MatrixType, int _UpLo>\ntemplate<typename Derived>\nvoid LLT<MatrixType,_UpLo>::solveInPlace(MatrixBase<Derived> &bAndX) const\n{\n  eigen_assert(m_isInitialized && \"LLT is not initialized.\");\n  eigen_assert(m_matrix.rows()==bAndX.rows());\n  matrixL().solveInPlace(bAndX);\n  matrixU().solveInPlace(bAndX);\n}\n\n/** \\returns the matrix represented by the decomposition,\n * i.e., it returns the product: L L^*.\n * This function is provided for debug purpose. */\ntemplate<typename MatrixType, int _UpLo>\nMatrixType LLT<MatrixType,_UpLo>::reconstructedMatrix() const\n{\n  eigen_assert(m_isInitialized && \"LLT is not initialized.\");\n  return matrixL() * matrixL().adjoint().toDenseMatrix();\n}\n\n/** \\cholesky_module\n  * \\returns the LLT decomposition of \\c *this\n  * \\sa SelfAdjointView::llt()\n  */\ntemplate<typename Derived>\ninline const LLT<typename MatrixBase<Derived>::PlainObject>\nMatrixBase<Derived>::llt() const\n{\n  return LLT<PlainObject>(derived());\n}\n\n/** \\cholesky_module\n  * \\returns the LLT decomposition of \\c *this\n  * \\sa SelfAdjointView::llt()\n  */\ntemplate<typename MatrixType, unsigned int UpLo>\ninline const LLT<typename SelfAdjointView<MatrixType, UpLo>::PlainObject, UpLo>\nSelfAdjointView<MatrixType, UpLo>::llt() const\n{\n  return LLT<PlainObject,UpLo>(m_matrix);\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_LLT_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Cholesky/LLT_LAPACKE.h",
    "content": "/*\n Copyright (c) 2011, Intel Corporation. All rights reserved.\n\n Redistribution and use in source and binary forms, with or without modification,\n are permitted provided that the following conditions are met:\n\n * Redistributions of source code must retain the above copyright notice, this\n   list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright notice,\n   this list of conditions and the following disclaimer in the documentation\n   and/or other materials provided with the distribution.\n * Neither the name of Intel Corporation nor the names of its contributors may\n   be used to endorse or promote products derived from this software without\n   specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n ********************************************************************************\n *   Content : Eigen bindings to LAPACKe\n *     LLt decomposition based on LAPACKE_?potrf function.\n ********************************************************************************\n*/\n\n#ifndef EIGEN_LLT_LAPACKE_H\n#define EIGEN_LLT_LAPACKE_H\n\nnamespace Eigen { \n\nnamespace internal {\n\ntemplate<typename Scalar> struct lapacke_llt;\n\n#define EIGEN_LAPACKE_LLT(EIGTYPE, BLASTYPE, LAPACKE_PREFIX) \\\ntemplate<> struct lapacke_llt<EIGTYPE> \\\n{ \\\n  template<typename MatrixType> \\\n  static inline Index potrf(MatrixType& m, char uplo) \\\n  { \\\n    lapack_int matrix_order; \\\n    lapack_int size, lda, info, StorageOrder; \\\n    EIGTYPE* a; \\\n    eigen_assert(m.rows()==m.cols()); \\\n    /* Set up parameters for ?potrf */ \\\n    size = convert_index<lapack_int>(m.rows()); \\\n    StorageOrder = MatrixType::Flags&RowMajorBit?RowMajor:ColMajor; \\\n    matrix_order = StorageOrder==RowMajor ? LAPACK_ROW_MAJOR : LAPACK_COL_MAJOR; \\\n    a = &(m.coeffRef(0,0)); \\\n    lda = convert_index<lapack_int>(m.outerStride()); \\\n\\\n    info = LAPACKE_##LAPACKE_PREFIX##potrf( matrix_order, uplo, size, (BLASTYPE*)a, lda ); \\\n    info = (info==0) ? -1 : info>0 ? info-1 : size; \\\n    return info; \\\n  } \\\n}; \\\ntemplate<> struct llt_inplace<EIGTYPE, Lower> \\\n{ \\\n  template<typename MatrixType> \\\n  static Index blocked(MatrixType& m) \\\n  { \\\n    return lapacke_llt<EIGTYPE>::potrf(m, 'L'); \\\n  } \\\n  template<typename MatrixType, typename VectorType> \\\n  static Index rankUpdate(MatrixType& mat, const VectorType& vec, const typename MatrixType::RealScalar& sigma) \\\n  { return Eigen::internal::llt_rank_update_lower(mat, vec, sigma); } \\\n}; \\\ntemplate<> struct llt_inplace<EIGTYPE, Upper> \\\n{ \\\n  template<typename MatrixType> \\\n  static Index blocked(MatrixType& m) \\\n  { \\\n    return lapacke_llt<EIGTYPE>::potrf(m, 'U'); \\\n  } \\\n  template<typename MatrixType, typename VectorType> \\\n  static Index rankUpdate(MatrixType& mat, const VectorType& vec, const typename MatrixType::RealScalar& sigma) \\\n  { \\\n    Transpose<MatrixType> matt(mat); \\\n    return llt_inplace<EIGTYPE, Lower>::rankUpdate(matt, vec.conjugate(), sigma); \\\n  } \\\n};\n\nEIGEN_LAPACKE_LLT(double, double, d)\nEIGEN_LAPACKE_LLT(float, float, s)\nEIGEN_LAPACKE_LLT(dcomplex, lapack_complex_double, z)\nEIGEN_LAPACKE_LLT(scomplex, lapack_complex_float, c)\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_LLT_LAPACKE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/CholmodSupport/CholmodSupport.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_CHOLMODSUPPORT_H\n#define EIGEN_CHOLMODSUPPORT_H\n\nnamespace Eigen { \n\nnamespace internal {\n\ntemplate<typename Scalar> struct cholmod_configure_matrix;\n\ntemplate<> struct cholmod_configure_matrix<double> {\n  template<typename CholmodType>\n  static void run(CholmodType& mat) {\n    mat.xtype = CHOLMOD_REAL;\n    mat.dtype = CHOLMOD_DOUBLE;\n  }\n};\n\ntemplate<> struct cholmod_configure_matrix<std::complex<double> > {\n  template<typename CholmodType>\n  static void run(CholmodType& mat) {\n    mat.xtype = CHOLMOD_COMPLEX;\n    mat.dtype = CHOLMOD_DOUBLE;\n  }\n};\n\n// Other scalar types are not yet suppotred by Cholmod\n// template<> struct cholmod_configure_matrix<float> {\n//   template<typename CholmodType>\n//   static void run(CholmodType& mat) {\n//     mat.xtype = CHOLMOD_REAL;\n//     mat.dtype = CHOLMOD_SINGLE;\n//   }\n// };\n//\n// template<> struct cholmod_configure_matrix<std::complex<float> > {\n//   template<typename CholmodType>\n//   static void run(CholmodType& mat) {\n//     mat.xtype = CHOLMOD_COMPLEX;\n//     mat.dtype = CHOLMOD_SINGLE;\n//   }\n// };\n\n} // namespace internal\n\n/** Wraps the Eigen sparse matrix \\a mat into a Cholmod sparse matrix object.\n  * Note that the data are shared.\n  */\ntemplate<typename _Scalar, int _Options, typename _StorageIndex>\ncholmod_sparse viewAsCholmod(Ref<SparseMatrix<_Scalar,_Options,_StorageIndex> > mat)\n{\n  cholmod_sparse res;\n  res.nzmax   = mat.nonZeros();\n  res.nrow    = mat.rows();\n  res.ncol    = mat.cols();\n  res.p       = mat.outerIndexPtr();\n  res.i       = mat.innerIndexPtr();\n  res.x       = mat.valuePtr();\n  res.z       = 0;\n  res.sorted  = 1;\n  if(mat.isCompressed())\n  {\n    res.packed  = 1;\n    res.nz = 0;\n  }\n  else\n  {\n    res.packed  = 0;\n    res.nz = mat.innerNonZeroPtr();\n  }\n\n  res.dtype   = 0;\n  res.stype   = -1;\n  \n  if (internal::is_same<_StorageIndex,int>::value)\n  {\n    res.itype = CHOLMOD_INT;\n  }\n  else if (internal::is_same<_StorageIndex,long>::value)\n  {\n    res.itype = CHOLMOD_LONG;\n  }\n  else\n  {\n    eigen_assert(false && \"Index type not supported yet\");\n  }\n\n  // setup res.xtype\n  internal::cholmod_configure_matrix<_Scalar>::run(res);\n  \n  res.stype = 0;\n  \n  return res;\n}\n\ntemplate<typename _Scalar, int _Options, typename _Index>\nconst cholmod_sparse viewAsCholmod(const SparseMatrix<_Scalar,_Options,_Index>& mat)\n{\n  cholmod_sparse res = viewAsCholmod(Ref<SparseMatrix<_Scalar,_Options,_Index> >(mat.const_cast_derived()));\n  return res;\n}\n\ntemplate<typename _Scalar, int _Options, typename _Index>\nconst cholmod_sparse viewAsCholmod(const SparseVector<_Scalar,_Options,_Index>& mat)\n{\n  cholmod_sparse res = viewAsCholmod(Ref<SparseMatrix<_Scalar,_Options,_Index> >(mat.const_cast_derived()));\n  return res;\n}\n\n/** Returns a view of the Eigen sparse matrix \\a mat as Cholmod sparse matrix.\n  * The data are not copied but shared. */\ntemplate<typename _Scalar, int _Options, typename _Index, unsigned int UpLo>\ncholmod_sparse viewAsCholmod(const SparseSelfAdjointView<const SparseMatrix<_Scalar,_Options,_Index>, UpLo>& mat)\n{\n  cholmod_sparse res = viewAsCholmod(Ref<SparseMatrix<_Scalar,_Options,_Index> >(mat.matrix().const_cast_derived()));\n  \n  if(UpLo==Upper) res.stype =  1;\n  if(UpLo==Lower) res.stype = -1;\n\n  return res;\n}\n\n/** Returns a view of the Eigen \\b dense matrix \\a mat as Cholmod dense matrix.\n  * The data are not copied but shared. */\ntemplate<typename Derived>\ncholmod_dense viewAsCholmod(MatrixBase<Derived>& mat)\n{\n  EIGEN_STATIC_ASSERT((internal::traits<Derived>::Flags&RowMajorBit)==0,THIS_METHOD_IS_ONLY_FOR_COLUMN_MAJOR_MATRICES);\n  typedef typename Derived::Scalar Scalar;\n\n  cholmod_dense res;\n  res.nrow   = mat.rows();\n  res.ncol   = mat.cols();\n  res.nzmax  = res.nrow * res.ncol;\n  res.d      = Derived::IsVectorAtCompileTime ? mat.derived().size() : mat.derived().outerStride();\n  res.x      = (void*)(mat.derived().data());\n  res.z      = 0;\n\n  internal::cholmod_configure_matrix<Scalar>::run(res);\n\n  return res;\n}\n\n/** Returns a view of the Cholmod sparse matrix \\a cm as an Eigen sparse matrix.\n  * The data are not copied but shared. */\ntemplate<typename Scalar, int Flags, typename StorageIndex>\nMappedSparseMatrix<Scalar,Flags,StorageIndex> viewAsEigen(cholmod_sparse& cm)\n{\n  return MappedSparseMatrix<Scalar,Flags,StorageIndex>\n         (cm.nrow, cm.ncol, static_cast<StorageIndex*>(cm.p)[cm.ncol],\n          static_cast<StorageIndex*>(cm.p), static_cast<StorageIndex*>(cm.i),static_cast<Scalar*>(cm.x) );\n}\n\nenum CholmodMode {\n  CholmodAuto, CholmodSimplicialLLt, CholmodSupernodalLLt, CholmodLDLt\n};\n\n\n/** \\ingroup CholmodSupport_Module\n  * \\class CholmodBase\n  * \\brief The base class for the direct Cholesky factorization of Cholmod\n  * \\sa class CholmodSupernodalLLT, class CholmodSimplicialLDLT, class CholmodSimplicialLLT\n  */\ntemplate<typename _MatrixType, int _UpLo, typename Derived>\nclass CholmodBase : public SparseSolverBase<Derived>\n{\n  protected:\n    typedef SparseSolverBase<Derived> Base;\n    using Base::derived;\n    using Base::m_isInitialized;\n  public:\n    typedef _MatrixType MatrixType;\n    enum { UpLo = _UpLo };\n    typedef typename MatrixType::Scalar Scalar;\n    typedef typename MatrixType::RealScalar RealScalar;\n    typedef MatrixType CholMatrixType;\n    typedef typename MatrixType::StorageIndex StorageIndex;\n    enum {\n      ColsAtCompileTime = MatrixType::ColsAtCompileTime,\n      MaxColsAtCompileTime = MatrixType::MaxColsAtCompileTime\n    };\n\n  public:\n\n    CholmodBase()\n      : m_cholmodFactor(0), m_info(Success), m_factorizationIsOk(false), m_analysisIsOk(false)\n    {\n      EIGEN_STATIC_ASSERT((internal::is_same<double,RealScalar>::value), CHOLMOD_SUPPORTS_DOUBLE_PRECISION_ONLY);\n      m_shiftOffset[0] = m_shiftOffset[1] = 0.0;\n      cholmod_start(&m_cholmod);\n    }\n\n    explicit CholmodBase(const MatrixType& matrix)\n      : m_cholmodFactor(0), m_info(Success), m_factorizationIsOk(false), m_analysisIsOk(false)\n    {\n      EIGEN_STATIC_ASSERT((internal::is_same<double,RealScalar>::value), CHOLMOD_SUPPORTS_DOUBLE_PRECISION_ONLY);\n      m_shiftOffset[0] = m_shiftOffset[1] = 0.0;\n      cholmod_start(&m_cholmod);\n      compute(matrix);\n    }\n\n    ~CholmodBase()\n    {\n      if(m_cholmodFactor)\n        cholmod_free_factor(&m_cholmodFactor, &m_cholmod);\n      cholmod_finish(&m_cholmod);\n    }\n    \n    inline StorageIndex cols() const { return internal::convert_index<StorageIndex, Index>(m_cholmodFactor->n); }\n    inline StorageIndex rows() const { return internal::convert_index<StorageIndex, Index>(m_cholmodFactor->n); }\n    \n    /** \\brief Reports whether previous computation was successful.\n      *\n      * \\returns \\c Success if computation was succesful,\n      *          \\c NumericalIssue if the matrix.appears to be negative.\n      */\n    ComputationInfo info() const\n    {\n      eigen_assert(m_isInitialized && \"Decomposition is not initialized.\");\n      return m_info;\n    }\n\n    /** Computes the sparse Cholesky decomposition of \\a matrix */\n    Derived& compute(const MatrixType& matrix)\n    {\n      analyzePattern(matrix);\n      factorize(matrix);\n      return derived();\n    }\n    \n    /** Performs a symbolic decomposition on the sparsity pattern of \\a matrix.\n      *\n      * This function is particularly useful when solving for several problems having the same structure.\n      * \n      * \\sa factorize()\n      */\n    void analyzePattern(const MatrixType& matrix)\n    {\n      if(m_cholmodFactor)\n      {\n        cholmod_free_factor(&m_cholmodFactor, &m_cholmod);\n        m_cholmodFactor = 0;\n      }\n      cholmod_sparse A = viewAsCholmod(matrix.template selfadjointView<UpLo>());\n      m_cholmodFactor = cholmod_analyze(&A, &m_cholmod);\n      \n      this->m_isInitialized = true;\n      this->m_info = Success;\n      m_analysisIsOk = true;\n      m_factorizationIsOk = false;\n    }\n    \n    /** Performs a numeric decomposition of \\a matrix\n      *\n      * The given matrix must have the same sparsity pattern as the matrix on which the symbolic decomposition has been performed.\n      *\n      * \\sa analyzePattern()\n      */\n    void factorize(const MatrixType& matrix)\n    {\n      eigen_assert(m_analysisIsOk && \"You must first call analyzePattern()\");\n      cholmod_sparse A = viewAsCholmod(matrix.template selfadjointView<UpLo>());\n      cholmod_factorize_p(&A, m_shiftOffset, 0, 0, m_cholmodFactor, &m_cholmod);\n\n      // If the factorization failed, minor is the column at which it did. On success minor == n.\n      this->m_info = (m_cholmodFactor->minor == m_cholmodFactor->n ? Success : NumericalIssue);\n      m_factorizationIsOk = true;\n    }\n    \n    /** Returns a reference to the Cholmod's configuration structure to get a full control over the performed operations.\n     *  See the Cholmod user guide for details. */\n    cholmod_common& cholmod() { return m_cholmod; }\n    \n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    /** \\internal */\n    template<typename Rhs,typename Dest>\n    void _solve_impl(const MatrixBase<Rhs> &b, MatrixBase<Dest> &dest) const\n    {\n      eigen_assert(m_factorizationIsOk && \"The decomposition is not in a valid state for solving, you must first call either compute() or symbolic()/numeric()\");\n      const Index size = m_cholmodFactor->n;\n      EIGEN_UNUSED_VARIABLE(size);\n      eigen_assert(size==b.rows());\n      \n      // Cholmod needs column-major stoarge without inner-stride, which corresponds to the default behavior of Ref.\n      Ref<const Matrix<typename Rhs::Scalar,Dynamic,Dynamic,ColMajor> > b_ref(b.derived());\n\n      cholmod_dense b_cd = viewAsCholmod(b_ref);\n      cholmod_dense* x_cd = cholmod_solve(CHOLMOD_A, m_cholmodFactor, &b_cd, &m_cholmod);\n      if(!x_cd)\n      {\n        this->m_info = NumericalIssue;\n        return;\n      }\n      // TODO optimize this copy by swapping when possible (be careful with alignment, etc.)\n      dest = Matrix<Scalar,Dest::RowsAtCompileTime,Dest::ColsAtCompileTime>::Map(reinterpret_cast<Scalar*>(x_cd->x),b.rows(),b.cols());\n      cholmod_free_dense(&x_cd, &m_cholmod);\n    }\n    \n    /** \\internal */\n    template<typename RhsDerived, typename DestDerived>\n    void _solve_impl(const SparseMatrixBase<RhsDerived> &b, SparseMatrixBase<DestDerived> &dest) const\n    {\n      eigen_assert(m_factorizationIsOk && \"The decomposition is not in a valid state for solving, you must first call either compute() or symbolic()/numeric()\");\n      const Index size = m_cholmodFactor->n;\n      EIGEN_UNUSED_VARIABLE(size);\n      eigen_assert(size==b.rows());\n\n      // note: cs stands for Cholmod Sparse\n      Ref<SparseMatrix<typename RhsDerived::Scalar,ColMajor,typename RhsDerived::StorageIndex> > b_ref(b.const_cast_derived());\n      cholmod_sparse b_cs = viewAsCholmod(b_ref);\n      cholmod_sparse* x_cs = cholmod_spsolve(CHOLMOD_A, m_cholmodFactor, &b_cs, &m_cholmod);\n      if(!x_cs)\n      {\n        this->m_info = NumericalIssue;\n        return;\n      }\n      // TODO optimize this copy by swapping when possible (be careful with alignment, etc.)\n      dest.derived() = viewAsEigen<typename DestDerived::Scalar,ColMajor,typename DestDerived::StorageIndex>(*x_cs);\n      cholmod_free_sparse(&x_cs, &m_cholmod);\n    }\n    #endif // EIGEN_PARSED_BY_DOXYGEN\n    \n    \n    /** Sets the shift parameter that will be used to adjust the diagonal coefficients during the numerical factorization.\n      *\n      * During the numerical factorization, an offset term is added to the diagonal coefficients:\\n\n      * \\c d_ii = \\a offset + \\c d_ii\n      *\n      * The default is \\a offset=0.\n      *\n      * \\returns a reference to \\c *this.\n      */\n    Derived& setShift(const RealScalar& offset)\n    {\n      m_shiftOffset[0] = double(offset);\n      return derived();\n    }\n    \n    /** \\returns the determinant of the underlying matrix from the current factorization */\n    Scalar determinant() const\n    {\n      using std::exp;\n      return exp(logDeterminant());\n    }\n\n    /** \\returns the log determinant of the underlying matrix from the current factorization */\n    Scalar logDeterminant() const\n    {\n      using std::log;\n      using numext::real;\n      eigen_assert(m_factorizationIsOk && \"The decomposition is not in a valid state for solving, you must first call either compute() or symbolic()/numeric()\");\n\n      RealScalar logDet = 0;\n      Scalar *x = static_cast<Scalar*>(m_cholmodFactor->x);\n      if (m_cholmodFactor->is_super)\n      {\n        // Supernodal factorization stored as a packed list of dense column-major blocs,\n        // as described by the following structure:\n\n        // super[k] == index of the first column of the j-th super node\n        StorageIndex *super = static_cast<StorageIndex*>(m_cholmodFactor->super);\n        // pi[k] == offset to the description of row indices\n        StorageIndex *pi = static_cast<StorageIndex*>(m_cholmodFactor->pi);\n        // px[k] == offset to the respective dense block\n        StorageIndex *px = static_cast<StorageIndex*>(m_cholmodFactor->px);\n\n        Index nb_super_nodes = m_cholmodFactor->nsuper;\n        for (Index k=0; k < nb_super_nodes; ++k)\n        {\n          StorageIndex ncols = super[k + 1] - super[k];\n          StorageIndex nrows = pi[k + 1] - pi[k];\n\n          Map<const Array<Scalar,1,Dynamic>, 0, InnerStride<> > sk(x + px[k], ncols, InnerStride<>(nrows+1));\n          logDet += sk.real().log().sum();\n        }\n      }\n      else\n      {\n        // Simplicial factorization stored as standard CSC matrix.\n        StorageIndex *p = static_cast<StorageIndex*>(m_cholmodFactor->p);\n        Index size = m_cholmodFactor->n;\n        for (Index k=0; k<size; ++k)\n          logDet += log(real( x[p[k]] ));\n      }\n      if (m_cholmodFactor->is_ll)\n        logDet *= 2.0;\n      return logDet;\n    };\n\n    template<typename Stream>\n    void dumpMemory(Stream& /*s*/)\n    {}\n    \n  protected:\n    mutable cholmod_common m_cholmod;\n    cholmod_factor* m_cholmodFactor;\n    double m_shiftOffset[2];\n    mutable ComputationInfo m_info;\n    int m_factorizationIsOk;\n    int m_analysisIsOk;\n};\n\n/** \\ingroup CholmodSupport_Module\n  * \\class CholmodSimplicialLLT\n  * \\brief A simplicial direct Cholesky (LLT) factorization and solver based on Cholmod\n  *\n  * This class allows to solve for A.X = B sparse linear problems via a simplicial LL^T Cholesky factorization\n  * using the Cholmod library.\n  * This simplicial variant is equivalent to Eigen's built-in SimplicialLLT class. Therefore, it has little practical interest.\n  * The sparse matrix A must be selfadjoint and positive definite. The vectors or matrices\n  * X and B can be either dense or sparse.\n  *\n  * \\tparam _MatrixType the type of the sparse matrix A, it must be a SparseMatrix<>\n  * \\tparam _UpLo the triangular part that will be used for the computations. It can be Lower\n  *               or Upper. Default is Lower.\n  *\n  * \\implsparsesolverconcept\n  *\n  * This class supports all kind of SparseMatrix<>: row or column major; upper, lower, or both; compressed or non compressed.\n  *\n  * \\warning Only double precision real and complex scalar types are supported by Cholmod.\n  *\n  * \\sa \\ref TutorialSparseSolverConcept, class CholmodSupernodalLLT, class SimplicialLLT\n  */\ntemplate<typename _MatrixType, int _UpLo = Lower>\nclass CholmodSimplicialLLT : public CholmodBase<_MatrixType, _UpLo, CholmodSimplicialLLT<_MatrixType, _UpLo> >\n{\n    typedef CholmodBase<_MatrixType, _UpLo, CholmodSimplicialLLT> Base;\n    using Base::m_cholmod;\n    \n  public:\n    \n    typedef _MatrixType MatrixType;\n    \n    CholmodSimplicialLLT() : Base() { init(); }\n\n    CholmodSimplicialLLT(const MatrixType& matrix) : Base()\n    {\n      init();\n      this->compute(matrix);\n    }\n\n    ~CholmodSimplicialLLT() {}\n  protected:\n    void init()\n    {\n      m_cholmod.final_asis = 0;\n      m_cholmod.supernodal = CHOLMOD_SIMPLICIAL;\n      m_cholmod.final_ll = 1;\n    }\n};\n\n\n/** \\ingroup CholmodSupport_Module\n  * \\class CholmodSimplicialLDLT\n  * \\brief A simplicial direct Cholesky (LDLT) factorization and solver based on Cholmod\n  *\n  * This class allows to solve for A.X = B sparse linear problems via a simplicial LDL^T Cholesky factorization\n  * using the Cholmod library.\n  * This simplicial variant is equivalent to Eigen's built-in SimplicialLDLT class. Therefore, it has little practical interest.\n  * The sparse matrix A must be selfadjoint and positive definite. The vectors or matrices\n  * X and B can be either dense or sparse.\n  *\n  * \\tparam _MatrixType the type of the sparse matrix A, it must be a SparseMatrix<>\n  * \\tparam _UpLo the triangular part that will be used for the computations. It can be Lower\n  *               or Upper. Default is Lower.\n  *\n  * \\implsparsesolverconcept\n  *\n  * This class supports all kind of SparseMatrix<>: row or column major; upper, lower, or both; compressed or non compressed.\n  *\n  * \\warning Only double precision real and complex scalar types are supported by Cholmod.\n  *\n  * \\sa \\ref TutorialSparseSolverConcept, class CholmodSupernodalLLT, class SimplicialLDLT\n  */\ntemplate<typename _MatrixType, int _UpLo = Lower>\nclass CholmodSimplicialLDLT : public CholmodBase<_MatrixType, _UpLo, CholmodSimplicialLDLT<_MatrixType, _UpLo> >\n{\n    typedef CholmodBase<_MatrixType, _UpLo, CholmodSimplicialLDLT> Base;\n    using Base::m_cholmod;\n    \n  public:\n    \n    typedef _MatrixType MatrixType;\n    \n    CholmodSimplicialLDLT() : Base() { init(); }\n\n    CholmodSimplicialLDLT(const MatrixType& matrix) : Base()\n    {\n      init();\n      this->compute(matrix);\n    }\n\n    ~CholmodSimplicialLDLT() {}\n  protected:\n    void init()\n    {\n      m_cholmod.final_asis = 1;\n      m_cholmod.supernodal = CHOLMOD_SIMPLICIAL;\n    }\n};\n\n/** \\ingroup CholmodSupport_Module\n  * \\class CholmodSupernodalLLT\n  * \\brief A supernodal Cholesky (LLT) factorization and solver based on Cholmod\n  *\n  * This class allows to solve for A.X = B sparse linear problems via a supernodal LL^T Cholesky factorization\n  * using the Cholmod library.\n  * This supernodal variant performs best on dense enough problems, e.g., 3D FEM, or very high order 2D FEM.\n  * The sparse matrix A must be selfadjoint and positive definite. The vectors or matrices\n  * X and B can be either dense or sparse.\n  *\n  * \\tparam _MatrixType the type of the sparse matrix A, it must be a SparseMatrix<>\n  * \\tparam _UpLo the triangular part that will be used for the computations. It can be Lower\n  *               or Upper. Default is Lower.\n  *\n  * \\implsparsesolverconcept\n  *\n  * This class supports all kind of SparseMatrix<>: row or column major; upper, lower, or both; compressed or non compressed.\n  *\n  * \\warning Only double precision real and complex scalar types are supported by Cholmod.\n  *\n  * \\sa \\ref TutorialSparseSolverConcept\n  */\ntemplate<typename _MatrixType, int _UpLo = Lower>\nclass CholmodSupernodalLLT : public CholmodBase<_MatrixType, _UpLo, CholmodSupernodalLLT<_MatrixType, _UpLo> >\n{\n    typedef CholmodBase<_MatrixType, _UpLo, CholmodSupernodalLLT> Base;\n    using Base::m_cholmod;\n    \n  public:\n    \n    typedef _MatrixType MatrixType;\n    \n    CholmodSupernodalLLT() : Base() { init(); }\n\n    CholmodSupernodalLLT(const MatrixType& matrix) : Base()\n    {\n      init();\n      this->compute(matrix);\n    }\n\n    ~CholmodSupernodalLLT() {}\n  protected:\n    void init()\n    {\n      m_cholmod.final_asis = 1;\n      m_cholmod.supernodal = CHOLMOD_SUPERNODAL;\n    }\n};\n\n/** \\ingroup CholmodSupport_Module\n  * \\class CholmodDecomposition\n  * \\brief A general Cholesky factorization and solver based on Cholmod\n  *\n  * This class allows to solve for A.X = B sparse linear problems via a LL^T or LDL^T Cholesky factorization\n  * using the Cholmod library. The sparse matrix A must be selfadjoint and positive definite. The vectors or matrices\n  * X and B can be either dense or sparse.\n  *\n  * This variant permits to change the underlying Cholesky method at runtime.\n  * On the other hand, it does not provide access to the result of the factorization.\n  * The default is to let Cholmod automatically choose between a simplicial and supernodal factorization.\n  *\n  * \\tparam _MatrixType the type of the sparse matrix A, it must be a SparseMatrix<>\n  * \\tparam _UpLo the triangular part that will be used for the computations. It can be Lower\n  *               or Upper. Default is Lower.\n  *\n  * \\implsparsesolverconcept\n  *\n  * This class supports all kind of SparseMatrix<>: row or column major; upper, lower, or both; compressed or non compressed.\n  *\n  * \\warning Only double precision real and complex scalar types are supported by Cholmod.\n  *\n  * \\sa \\ref TutorialSparseSolverConcept\n  */\ntemplate<typename _MatrixType, int _UpLo = Lower>\nclass CholmodDecomposition : public CholmodBase<_MatrixType, _UpLo, CholmodDecomposition<_MatrixType, _UpLo> >\n{\n    typedef CholmodBase<_MatrixType, _UpLo, CholmodDecomposition> Base;\n    using Base::m_cholmod;\n    \n  public:\n    \n    typedef _MatrixType MatrixType;\n    \n    CholmodDecomposition() : Base() { init(); }\n\n    CholmodDecomposition(const MatrixType& matrix) : Base()\n    {\n      init();\n      this->compute(matrix);\n    }\n\n    ~CholmodDecomposition() {}\n    \n    void setMode(CholmodMode mode)\n    {\n      switch(mode)\n      {\n        case CholmodAuto:\n          m_cholmod.final_asis = 1;\n          m_cholmod.supernodal = CHOLMOD_AUTO;\n          break;\n        case CholmodSimplicialLLt:\n          m_cholmod.final_asis = 0;\n          m_cholmod.supernodal = CHOLMOD_SIMPLICIAL;\n          m_cholmod.final_ll = 1;\n          break;\n        case CholmodSupernodalLLt:\n          m_cholmod.final_asis = 1;\n          m_cholmod.supernodal = CHOLMOD_SUPERNODAL;\n          break;\n        case CholmodLDLt:\n          m_cholmod.final_asis = 1;\n          m_cholmod.supernodal = CHOLMOD_SIMPLICIAL;\n          break;\n        default:\n          break;\n      }\n    }\n  protected:\n    void init()\n    {\n      m_cholmod.final_asis = 1;\n      m_cholmod.supernodal = CHOLMOD_AUTO;\n    }\n};\n\n} // end namespace Eigen\n\n#endif // EIGEN_CHOLMODSUPPORT_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/Array.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_ARRAY_H\n#define EIGEN_ARRAY_H\n\nnamespace Eigen {\n\nnamespace internal {\ntemplate<typename _Scalar, int _Rows, int _Cols, int _Options, int _MaxRows, int _MaxCols>\nstruct traits<Array<_Scalar, _Rows, _Cols, _Options, _MaxRows, _MaxCols> > : traits<Matrix<_Scalar, _Rows, _Cols, _Options, _MaxRows, _MaxCols> >\n{\n  typedef ArrayXpr XprKind;\n  typedef ArrayBase<Array<_Scalar, _Rows, _Cols, _Options, _MaxRows, _MaxCols> > XprBase;\n};\n}\n\n/** \\class Array\n  * \\ingroup Core_Module\n  *\n  * \\brief General-purpose arrays with easy API for coefficient-wise operations\n  *\n  * The %Array class is very similar to the Matrix class. It provides\n  * general-purpose one- and two-dimensional arrays. The difference between the\n  * %Array and the %Matrix class is primarily in the API: the API for the\n  * %Array class provides easy access to coefficient-wise operations, while the\n  * API for the %Matrix class provides easy access to linear-algebra\n  * operations.\n  *\n  * See documentation of class Matrix for detailed information on the template parameters\n  * storage layout.\n  *\n  * This class can be extended with the help of the plugin mechanism described on the page\n  * \\ref TopicCustomizing_Plugins by defining the preprocessor symbol \\c EIGEN_ARRAY_PLUGIN.\n  *\n  * \\sa \\blank \\ref TutorialArrayClass, \\ref TopicClassHierarchy\n  */\ntemplate<typename _Scalar, int _Rows, int _Cols, int _Options, int _MaxRows, int _MaxCols>\nclass Array\n  : public PlainObjectBase<Array<_Scalar, _Rows, _Cols, _Options, _MaxRows, _MaxCols> >\n{\n  public:\n\n    typedef PlainObjectBase<Array> Base;\n    EIGEN_DENSE_PUBLIC_INTERFACE(Array)\n\n    enum { Options = _Options };\n    typedef typename Base::PlainObject PlainObject;\n\n  protected:\n    template <typename Derived, typename OtherDerived, bool IsVector>\n    friend struct internal::conservative_resize_like_impl;\n\n    using Base::m_storage;\n\n  public:\n\n    using Base::base;\n    using Base::coeff;\n    using Base::coeffRef;\n\n    /**\n      * The usage of\n      *   using Base::operator=;\n      * fails on MSVC. Since the code below is working with GCC and MSVC, we skipped\n      * the usage of 'using'. This should be done only for operator=.\n      */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Array& operator=(const EigenBase<OtherDerived> &other)\n    {\n      return Base::operator=(other);\n    }\n\n    /** Set all the entries to \\a value.\n      * \\sa DenseBase::setConstant(), DenseBase::fill()\n      */\n    /* This overload is needed because the usage of\n      *   using Base::operator=;\n      * fails on MSVC. Since the code below is working with GCC and MSVC, we skipped\n      * the usage of 'using'. This should be done only for operator=.\n      */\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Array& operator=(const Scalar &value)\n    {\n      Base::setConstant(value);\n      return *this;\n    }\n\n    /** Copies the value of the expression \\a other into \\c *this with automatic resizing.\n      *\n      * *this might be resized to match the dimensions of \\a other. If *this was a null matrix (not already initialized),\n      * it will be initialized.\n      *\n      * Note that copying a row-vector into a vector (and conversely) is allowed.\n      * The resizing, if any, is then done in the appropriate way so that row-vectors\n      * remain row-vectors and vectors remain vectors.\n      */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Array& operator=(const DenseBase<OtherDerived>& other)\n    {\n      return Base::_set(other);\n    }\n\n    /** This is a special case of the templated operator=. Its purpose is to\n      * prevent a default operator= from hiding the templated operator=.\n      */\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Array& operator=(const Array& other)\n    {\n      return Base::_set(other);\n    }\n    \n    /** Default constructor.\n      *\n      * For fixed-size matrices, does nothing.\n      *\n      * For dynamic-size matrices, creates an empty matrix of size 0. Does not allocate any array. Such a matrix\n      * is called a null matrix. This constructor is the unique way to create null matrices: resizing\n      * a matrix to 0 is not supported.\n      *\n      * \\sa resize(Index,Index)\n      */\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Array() : Base()\n    {\n      Base::_check_template_params();\n      EIGEN_INITIALIZE_COEFFS_IF_THAT_OPTION_IS_ENABLED\n    }\n\n#ifndef EIGEN_PARSED_BY_DOXYGEN\n    // FIXME is it still needed ??\n    /** \\internal */\n    EIGEN_DEVICE_FUNC\n    Array(internal::constructor_without_unaligned_array_assert)\n      : Base(internal::constructor_without_unaligned_array_assert())\n    {\n      Base::_check_template_params();\n      EIGEN_INITIALIZE_COEFFS_IF_THAT_OPTION_IS_ENABLED\n    }\n#endif\n\n#if EIGEN_HAS_RVALUE_REFERENCES\n    EIGEN_DEVICE_FUNC\n    Array(Array&& other) EIGEN_NOEXCEPT_IF(std::is_nothrow_move_constructible<Scalar>::value)\n      : Base(std::move(other))\n    {\n      Base::_check_template_params();\n      if (RowsAtCompileTime!=Dynamic && ColsAtCompileTime!=Dynamic)\n        Base::_set_noalias(other);\n    }\n    EIGEN_DEVICE_FUNC\n    Array& operator=(Array&& other) EIGEN_NOEXCEPT_IF(std::is_nothrow_move_assignable<Scalar>::value)\n    {\n      other.swap(*this);\n      return *this;\n    }\n#endif\n\n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    template<typename T>\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE explicit Array(const T& x)\n    {\n      Base::_check_template_params();\n      Base::template _init1<T>(x);\n    }\n\n    template<typename T0, typename T1>\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Array(const T0& val0, const T1& val1)\n    {\n      Base::_check_template_params();\n      this->template _init2<T0,T1>(val0, val1);\n    }\n    #else\n    /** \\brief Constructs a fixed-sized array initialized with coefficients starting at \\a data */\n    EIGEN_DEVICE_FUNC explicit Array(const Scalar *data);\n    /** Constructs a vector or row-vector with given dimension. \\only_for_vectors\n      *\n      * Note that this is only useful for dynamic-size vectors. For fixed-size vectors,\n      * it is redundant to pass the dimension here, so it makes more sense to use the default\n      * constructor Array() instead.\n      */\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE explicit Array(Index dim);\n    /** constructs an initialized 1x1 Array with the given coefficient */\n    Array(const Scalar& value);\n    /** constructs an uninitialized array with \\a rows rows and \\a cols columns.\n      *\n      * This is useful for dynamic-size arrays. For fixed-size arrays,\n      * it is redundant to pass these parameters, so one should use the default constructor\n      * Array() instead. */\n    Array(Index rows, Index cols);\n    /** constructs an initialized 2D vector with given coefficients */\n    Array(const Scalar& val0, const Scalar& val1);\n    #endif\n\n    /** constructs an initialized 3D vector with given coefficients */\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Array(const Scalar& val0, const Scalar& val1, const Scalar& val2)\n    {\n      Base::_check_template_params();\n      EIGEN_STATIC_ASSERT_VECTOR_SPECIFIC_SIZE(Array, 3)\n      m_storage.data()[0] = val0;\n      m_storage.data()[1] = val1;\n      m_storage.data()[2] = val2;\n    }\n    /** constructs an initialized 4D vector with given coefficients */\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Array(const Scalar& val0, const Scalar& val1, const Scalar& val2, const Scalar& val3)\n    {\n      Base::_check_template_params();\n      EIGEN_STATIC_ASSERT_VECTOR_SPECIFIC_SIZE(Array, 4)\n      m_storage.data()[0] = val0;\n      m_storage.data()[1] = val1;\n      m_storage.data()[2] = val2;\n      m_storage.data()[3] = val3;\n    }\n\n    /** Copy constructor */\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Array(const Array& other)\n            : Base(other)\n    { }\n\n    /** \\sa MatrixBase::operator=(const EigenBase<OtherDerived>&) */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Array(const EigenBase<OtherDerived> &other)\n      : Base(other.derived())\n    { }\n\n    EIGEN_DEVICE_FUNC inline Index innerStride() const { return 1; }\n    EIGEN_DEVICE_FUNC inline Index outerStride() const { return this->innerSize(); }\n\n    #ifdef EIGEN_ARRAY_PLUGIN\n    #include EIGEN_ARRAY_PLUGIN\n    #endif\n\n  private:\n\n    template<typename MatrixType, typename OtherDerived, bool SwapPointers>\n    friend struct internal::matrix_swap_impl;\n};\n\n/** \\defgroup arraytypedefs Global array typedefs\n  * \\ingroup Core_Module\n  *\n  * Eigen defines several typedef shortcuts for most common 1D and 2D array types.\n  *\n  * The general patterns are the following:\n  *\n  * \\c ArrayRowsColsType where \\c Rows and \\c Cols can be \\c 2,\\c 3,\\c 4 for fixed size square matrices or \\c X for dynamic size,\n  * and where \\c Type can be \\c i for integer, \\c f for float, \\c d for double, \\c cf for complex float, \\c cd\n  * for complex double.\n  *\n  * For example, \\c Array33d is a fixed-size 3x3 array type of doubles, and \\c ArrayXXf is a dynamic-size matrix of floats.\n  *\n  * There are also \\c ArraySizeType which are self-explanatory. For example, \\c Array4cf is\n  * a fixed-size 1D array of 4 complex floats.\n  *\n  * \\sa class Array\n  */\n\n#define EIGEN_MAKE_ARRAY_TYPEDEFS(Type, TypeSuffix, Size, SizeSuffix)   \\\n/** \\ingroup arraytypedefs */                                    \\\ntypedef Array<Type, Size, Size> Array##SizeSuffix##SizeSuffix##TypeSuffix;  \\\n/** \\ingroup arraytypedefs */                                    \\\ntypedef Array<Type, Size, 1>    Array##SizeSuffix##TypeSuffix;\n\n#define EIGEN_MAKE_ARRAY_FIXED_TYPEDEFS(Type, TypeSuffix, Size)         \\\n/** \\ingroup arraytypedefs */                                    \\\ntypedef Array<Type, Size, Dynamic> Array##Size##X##TypeSuffix;  \\\n/** \\ingroup arraytypedefs */                                    \\\ntypedef Array<Type, Dynamic, Size> Array##X##Size##TypeSuffix;\n\n#define EIGEN_MAKE_ARRAY_TYPEDEFS_ALL_SIZES(Type, TypeSuffix) \\\nEIGEN_MAKE_ARRAY_TYPEDEFS(Type, TypeSuffix, 2, 2) \\\nEIGEN_MAKE_ARRAY_TYPEDEFS(Type, TypeSuffix, 3, 3) \\\nEIGEN_MAKE_ARRAY_TYPEDEFS(Type, TypeSuffix, 4, 4) \\\nEIGEN_MAKE_ARRAY_TYPEDEFS(Type, TypeSuffix, Dynamic, X) \\\nEIGEN_MAKE_ARRAY_FIXED_TYPEDEFS(Type, TypeSuffix, 2) \\\nEIGEN_MAKE_ARRAY_FIXED_TYPEDEFS(Type, TypeSuffix, 3) \\\nEIGEN_MAKE_ARRAY_FIXED_TYPEDEFS(Type, TypeSuffix, 4)\n\nEIGEN_MAKE_ARRAY_TYPEDEFS_ALL_SIZES(int,                  i)\nEIGEN_MAKE_ARRAY_TYPEDEFS_ALL_SIZES(float,                f)\nEIGEN_MAKE_ARRAY_TYPEDEFS_ALL_SIZES(double,               d)\nEIGEN_MAKE_ARRAY_TYPEDEFS_ALL_SIZES(std::complex<float>,  cf)\nEIGEN_MAKE_ARRAY_TYPEDEFS_ALL_SIZES(std::complex<double>, cd)\n\n#undef EIGEN_MAKE_ARRAY_TYPEDEFS_ALL_SIZES\n#undef EIGEN_MAKE_ARRAY_TYPEDEFS\n\n#undef EIGEN_MAKE_ARRAY_TYPEDEFS_LARGE\n\n#define EIGEN_USING_ARRAY_TYPEDEFS_FOR_TYPE_AND_SIZE(TypeSuffix, SizeSuffix) \\\nusing Eigen::Matrix##SizeSuffix##TypeSuffix; \\\nusing Eigen::Vector##SizeSuffix##TypeSuffix; \\\nusing Eigen::RowVector##SizeSuffix##TypeSuffix;\n\n#define EIGEN_USING_ARRAY_TYPEDEFS_FOR_TYPE(TypeSuffix) \\\nEIGEN_USING_ARRAY_TYPEDEFS_FOR_TYPE_AND_SIZE(TypeSuffix, 2) \\\nEIGEN_USING_ARRAY_TYPEDEFS_FOR_TYPE_AND_SIZE(TypeSuffix, 3) \\\nEIGEN_USING_ARRAY_TYPEDEFS_FOR_TYPE_AND_SIZE(TypeSuffix, 4) \\\nEIGEN_USING_ARRAY_TYPEDEFS_FOR_TYPE_AND_SIZE(TypeSuffix, X) \\\n\n#define EIGEN_USING_ARRAY_TYPEDEFS \\\nEIGEN_USING_ARRAY_TYPEDEFS_FOR_TYPE(i) \\\nEIGEN_USING_ARRAY_TYPEDEFS_FOR_TYPE(f) \\\nEIGEN_USING_ARRAY_TYPEDEFS_FOR_TYPE(d) \\\nEIGEN_USING_ARRAY_TYPEDEFS_FOR_TYPE(cf) \\\nEIGEN_USING_ARRAY_TYPEDEFS_FOR_TYPE(cd)\n\n} // end namespace Eigen\n\n#endif // EIGEN_ARRAY_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/ArrayBase.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_ARRAYBASE_H\n#define EIGEN_ARRAYBASE_H\n\nnamespace Eigen { \n\ntemplate<typename ExpressionType> class MatrixWrapper;\n\n/** \\class ArrayBase\n  * \\ingroup Core_Module\n  *\n  * \\brief Base class for all 1D and 2D array, and related expressions\n  *\n  * An array is similar to a dense vector or matrix. While matrices are mathematical\n  * objects with well defined linear algebra operators, an array is just a collection\n  * of scalar values arranged in a one or two dimensionnal fashion. As the main consequence,\n  * all operations applied to an array are performed coefficient wise. Furthermore,\n  * arrays support scalar math functions of the c++ standard library (e.g., std::sin(x)), and convenient\n  * constructors allowing to easily write generic code working for both scalar values\n  * and arrays.\n  *\n  * This class is the base that is inherited by all array expression types.\n  *\n  * \\tparam Derived is the derived type, e.g., an array or an expression type.\n  *\n  * This class can be extended with the help of the plugin mechanism described on the page\n  * \\ref TopicCustomizing_Plugins by defining the preprocessor symbol \\c EIGEN_ARRAYBASE_PLUGIN.\n  *\n  * \\sa class MatrixBase, \\ref TopicClassHierarchy\n  */\ntemplate<typename Derived> class ArrayBase\n  : public DenseBase<Derived>\n{\n  public:\n#ifndef EIGEN_PARSED_BY_DOXYGEN\n    /** The base class for a given storage type. */\n    typedef ArrayBase StorageBaseType;\n\n    typedef ArrayBase Eigen_BaseClassForSpecializationOfGlobalMathFuncImpl;\n\n    typedef typename internal::traits<Derived>::StorageKind StorageKind;\n    typedef typename internal::traits<Derived>::Scalar Scalar;\n    typedef typename internal::packet_traits<Scalar>::type PacketScalar;\n    typedef typename NumTraits<Scalar>::Real RealScalar;\n\n    typedef DenseBase<Derived> Base;\n    using Base::RowsAtCompileTime;\n    using Base::ColsAtCompileTime;\n    using Base::SizeAtCompileTime;\n    using Base::MaxRowsAtCompileTime;\n    using Base::MaxColsAtCompileTime;\n    using Base::MaxSizeAtCompileTime;\n    using Base::IsVectorAtCompileTime;\n    using Base::Flags;\n    \n    using Base::derived;\n    using Base::const_cast_derived;\n    using Base::rows;\n    using Base::cols;\n    using Base::size;\n    using Base::coeff;\n    using Base::coeffRef;\n    using Base::lazyAssign;\n    using Base::operator=;\n    using Base::operator+=;\n    using Base::operator-=;\n    using Base::operator*=;\n    using Base::operator/=;\n\n    typedef typename Base::CoeffReturnType CoeffReturnType;\n\n#endif // not EIGEN_PARSED_BY_DOXYGEN\n\n#ifndef EIGEN_PARSED_BY_DOXYGEN\n    typedef typename Base::PlainObject PlainObject;\n\n    /** \\internal Represents a matrix with all coefficients equal to one another*/\n    typedef CwiseNullaryOp<internal::scalar_constant_op<Scalar>,PlainObject> ConstantReturnType;\n#endif // not EIGEN_PARSED_BY_DOXYGEN\n\n#define EIGEN_CURRENT_STORAGE_BASE_CLASS Eigen::ArrayBase\n#define EIGEN_DOC_UNARY_ADDONS(X,Y)\n#   include \"../plugins/CommonCwiseUnaryOps.h\"\n#   include \"../plugins/MatrixCwiseUnaryOps.h\"\n#   include \"../plugins/ArrayCwiseUnaryOps.h\"\n#   include \"../plugins/CommonCwiseBinaryOps.h\"\n#   include \"../plugins/MatrixCwiseBinaryOps.h\"\n#   include \"../plugins/ArrayCwiseBinaryOps.h\"\n#   ifdef EIGEN_ARRAYBASE_PLUGIN\n#     include EIGEN_ARRAYBASE_PLUGIN\n#   endif\n#undef EIGEN_CURRENT_STORAGE_BASE_CLASS\n#undef EIGEN_DOC_UNARY_ADDONS\n\n    /** Special case of the template operator=, in order to prevent the compiler\n      * from generating a default operator= (issue hit with g++ 4.1)\n      */\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n    Derived& operator=(const ArrayBase& other)\n    {\n      internal::call_assignment(derived(), other.derived());\n      return derived();\n    }\n    \n    /** Set all the entries to \\a value.\n      * \\sa DenseBase::setConstant(), DenseBase::fill() */\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n    Derived& operator=(const Scalar &value)\n    { Base::setConstant(value); return derived(); }\n\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n    Derived& operator+=(const Scalar& scalar);\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n    Derived& operator-=(const Scalar& scalar);\n\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n    Derived& operator+=(const ArrayBase<OtherDerived>& other);\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n    Derived& operator-=(const ArrayBase<OtherDerived>& other);\n\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n    Derived& operator*=(const ArrayBase<OtherDerived>& other);\n\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n    Derived& operator/=(const ArrayBase<OtherDerived>& other);\n\n  public:\n    EIGEN_DEVICE_FUNC\n    ArrayBase<Derived>& array() { return *this; }\n    EIGEN_DEVICE_FUNC\n    const ArrayBase<Derived>& array() const { return *this; }\n\n    /** \\returns an \\link Eigen::MatrixBase Matrix \\endlink expression of this array\n      * \\sa MatrixBase::array() */\n    EIGEN_DEVICE_FUNC\n    MatrixWrapper<Derived> matrix() { return MatrixWrapper<Derived>(derived()); }\n    EIGEN_DEVICE_FUNC\n    const MatrixWrapper<const Derived> matrix() const { return MatrixWrapper<const Derived>(derived()); }\n\n//     template<typename Dest>\n//     inline void evalTo(Dest& dst) const { dst = matrix(); }\n\n  protected:\n    EIGEN_DEVICE_FUNC\n    ArrayBase() : Base() {}\n\n  private:\n    explicit ArrayBase(Index);\n    ArrayBase(Index,Index);\n    template<typename OtherDerived> explicit ArrayBase(const ArrayBase<OtherDerived>&);\n  protected:\n    // mixing arrays and matrices is not legal\n    template<typename OtherDerived> Derived& operator+=(const MatrixBase<OtherDerived>& )\n    {EIGEN_STATIC_ASSERT(std::ptrdiff_t(sizeof(typename OtherDerived::Scalar))==-1,YOU_CANNOT_MIX_ARRAYS_AND_MATRICES); return *this;}\n    // mixing arrays and matrices is not legal\n    template<typename OtherDerived> Derived& operator-=(const MatrixBase<OtherDerived>& )\n    {EIGEN_STATIC_ASSERT(std::ptrdiff_t(sizeof(typename OtherDerived::Scalar))==-1,YOU_CANNOT_MIX_ARRAYS_AND_MATRICES); return *this;}\n};\n\n/** replaces \\c *this by \\c *this - \\a other.\n  *\n  * \\returns a reference to \\c *this\n  */\ntemplate<typename Derived>\ntemplate<typename OtherDerived>\nEIGEN_STRONG_INLINE Derived &\nArrayBase<Derived>::operator-=(const ArrayBase<OtherDerived> &other)\n{\n  call_assignment(derived(), other.derived(), internal::sub_assign_op<Scalar,typename OtherDerived::Scalar>());\n  return derived();\n}\n\n/** replaces \\c *this by \\c *this + \\a other.\n  *\n  * \\returns a reference to \\c *this\n  */\ntemplate<typename Derived>\ntemplate<typename OtherDerived>\nEIGEN_STRONG_INLINE Derived &\nArrayBase<Derived>::operator+=(const ArrayBase<OtherDerived>& other)\n{\n  call_assignment(derived(), other.derived(), internal::add_assign_op<Scalar,typename OtherDerived::Scalar>());\n  return derived();\n}\n\n/** replaces \\c *this by \\c *this * \\a other coefficient wise.\n  *\n  * \\returns a reference to \\c *this\n  */\ntemplate<typename Derived>\ntemplate<typename OtherDerived>\nEIGEN_STRONG_INLINE Derived &\nArrayBase<Derived>::operator*=(const ArrayBase<OtherDerived>& other)\n{\n  call_assignment(derived(), other.derived(), internal::mul_assign_op<Scalar,typename OtherDerived::Scalar>());\n  return derived();\n}\n\n/** replaces \\c *this by \\c *this / \\a other coefficient wise.\n  *\n  * \\returns a reference to \\c *this\n  */\ntemplate<typename Derived>\ntemplate<typename OtherDerived>\nEIGEN_STRONG_INLINE Derived &\nArrayBase<Derived>::operator/=(const ArrayBase<OtherDerived>& other)\n{\n  call_assignment(derived(), other.derived(), internal::div_assign_op<Scalar,typename OtherDerived::Scalar>());\n  return derived();\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_ARRAYBASE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/ArrayWrapper.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009-2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_ARRAYWRAPPER_H\n#define EIGEN_ARRAYWRAPPER_H\n\nnamespace Eigen { \n\n/** \\class ArrayWrapper\n  * \\ingroup Core_Module\n  *\n  * \\brief Expression of a mathematical vector or matrix as an array object\n  *\n  * This class is the return type of MatrixBase::array(), and most of the time\n  * this is the only way it is use.\n  *\n  * \\sa MatrixBase::array(), class MatrixWrapper\n  */\n\nnamespace internal {\ntemplate<typename ExpressionType>\nstruct traits<ArrayWrapper<ExpressionType> >\n  : public traits<typename remove_all<typename ExpressionType::Nested>::type >\n{\n  typedef ArrayXpr XprKind;\n  // Let's remove NestByRefBit\n  enum {\n    Flags0 = traits<typename remove_all<typename ExpressionType::Nested>::type >::Flags,\n    Flags = Flags0 & ~NestByRefBit\n  };\n};\n}\n\ntemplate<typename ExpressionType>\nclass ArrayWrapper : public ArrayBase<ArrayWrapper<ExpressionType> >\n{\n  public:\n    typedef ArrayBase<ArrayWrapper> Base;\n    EIGEN_DENSE_PUBLIC_INTERFACE(ArrayWrapper)\n    EIGEN_INHERIT_ASSIGNMENT_OPERATORS(ArrayWrapper)\n    typedef typename internal::remove_all<ExpressionType>::type NestedExpression;\n\n    typedef typename internal::conditional<\n                       internal::is_lvalue<ExpressionType>::value,\n                       Scalar,\n                       const Scalar\n                     >::type ScalarWithConstIfNotLvalue;\n\n    typedef typename internal::ref_selector<ExpressionType>::non_const_type NestedExpressionType;\n\n    using Base::coeffRef;\n\n    EIGEN_DEVICE_FUNC\n    explicit EIGEN_STRONG_INLINE ArrayWrapper(ExpressionType& matrix) : m_expression(matrix) {}\n\n    EIGEN_DEVICE_FUNC\n    inline Index rows() const { return m_expression.rows(); }\n    EIGEN_DEVICE_FUNC\n    inline Index cols() const { return m_expression.cols(); }\n    EIGEN_DEVICE_FUNC\n    inline Index outerStride() const { return m_expression.outerStride(); }\n    EIGEN_DEVICE_FUNC\n    inline Index innerStride() const { return m_expression.innerStride(); }\n\n    EIGEN_DEVICE_FUNC\n    inline ScalarWithConstIfNotLvalue* data() { return m_expression.data(); }\n    EIGEN_DEVICE_FUNC\n    inline const Scalar* data() const { return m_expression.data(); }\n\n    EIGEN_DEVICE_FUNC\n    inline const Scalar& coeffRef(Index rowId, Index colId) const\n    {\n      return m_expression.coeffRef(rowId, colId);\n    }\n\n    EIGEN_DEVICE_FUNC\n    inline const Scalar& coeffRef(Index index) const\n    {\n      return m_expression.coeffRef(index);\n    }\n\n    template<typename Dest>\n    EIGEN_DEVICE_FUNC\n    inline void evalTo(Dest& dst) const { dst = m_expression; }\n\n    const typename internal::remove_all<NestedExpressionType>::type& \n    EIGEN_DEVICE_FUNC\n    nestedExpression() const \n    {\n      return m_expression;\n    }\n\n    /** Forwards the resizing request to the nested expression\n      * \\sa DenseBase::resize(Index)  */\n    EIGEN_DEVICE_FUNC\n    void resize(Index newSize) { m_expression.resize(newSize); }\n    /** Forwards the resizing request to the nested expression\n      * \\sa DenseBase::resize(Index,Index)*/\n    EIGEN_DEVICE_FUNC\n    void resize(Index rows, Index cols) { m_expression.resize(rows,cols); }\n\n  protected:\n    NestedExpressionType m_expression;\n};\n\n/** \\class MatrixWrapper\n  * \\ingroup Core_Module\n  *\n  * \\brief Expression of an array as a mathematical vector or matrix\n  *\n  * This class is the return type of ArrayBase::matrix(), and most of the time\n  * this is the only way it is use.\n  *\n  * \\sa MatrixBase::matrix(), class ArrayWrapper\n  */\n\nnamespace internal {\ntemplate<typename ExpressionType>\nstruct traits<MatrixWrapper<ExpressionType> >\n : public traits<typename remove_all<typename ExpressionType::Nested>::type >\n{\n  typedef MatrixXpr XprKind;\n  // Let's remove NestByRefBit\n  enum {\n    Flags0 = traits<typename remove_all<typename ExpressionType::Nested>::type >::Flags,\n    Flags = Flags0 & ~NestByRefBit\n  };\n};\n}\n\ntemplate<typename ExpressionType>\nclass MatrixWrapper : public MatrixBase<MatrixWrapper<ExpressionType> >\n{\n  public:\n    typedef MatrixBase<MatrixWrapper<ExpressionType> > Base;\n    EIGEN_DENSE_PUBLIC_INTERFACE(MatrixWrapper)\n    EIGEN_INHERIT_ASSIGNMENT_OPERATORS(MatrixWrapper)\n    typedef typename internal::remove_all<ExpressionType>::type NestedExpression;\n\n    typedef typename internal::conditional<\n                       internal::is_lvalue<ExpressionType>::value,\n                       Scalar,\n                       const Scalar\n                     >::type ScalarWithConstIfNotLvalue;\n\n    typedef typename internal::ref_selector<ExpressionType>::non_const_type NestedExpressionType;\n\n    using Base::coeffRef;\n\n    EIGEN_DEVICE_FUNC\n    explicit inline MatrixWrapper(ExpressionType& matrix) : m_expression(matrix) {}\n\n    EIGEN_DEVICE_FUNC\n    inline Index rows() const { return m_expression.rows(); }\n    EIGEN_DEVICE_FUNC\n    inline Index cols() const { return m_expression.cols(); }\n    EIGEN_DEVICE_FUNC\n    inline Index outerStride() const { return m_expression.outerStride(); }\n    EIGEN_DEVICE_FUNC\n    inline Index innerStride() const { return m_expression.innerStride(); }\n\n    EIGEN_DEVICE_FUNC\n    inline ScalarWithConstIfNotLvalue* data() { return m_expression.data(); }\n    EIGEN_DEVICE_FUNC\n    inline const Scalar* data() const { return m_expression.data(); }\n\n    EIGEN_DEVICE_FUNC\n    inline const Scalar& coeffRef(Index rowId, Index colId) const\n    {\n      return m_expression.derived().coeffRef(rowId, colId);\n    }\n\n    EIGEN_DEVICE_FUNC\n    inline const Scalar& coeffRef(Index index) const\n    {\n      return m_expression.coeffRef(index);\n    }\n\n    EIGEN_DEVICE_FUNC\n    const typename internal::remove_all<NestedExpressionType>::type& \n    nestedExpression() const \n    {\n      return m_expression;\n    }\n\n    /** Forwards the resizing request to the nested expression\n      * \\sa DenseBase::resize(Index)  */\n    EIGEN_DEVICE_FUNC\n    void resize(Index newSize) { m_expression.resize(newSize); }\n    /** Forwards the resizing request to the nested expression\n      * \\sa DenseBase::resize(Index,Index)*/\n    EIGEN_DEVICE_FUNC\n    void resize(Index rows, Index cols) { m_expression.resize(rows,cols); }\n\n  protected:\n    NestedExpressionType m_expression;\n};\n\n} // end namespace Eigen\n\n#endif // EIGEN_ARRAYWRAPPER_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/Assign.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2007 Michael Olbrich <michael.olbrich@gmx.net>\n// Copyright (C) 2006-2010 Benoit Jacob <jacob.benoit.1@gmail.com>\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_ASSIGN_H\n#define EIGEN_ASSIGN_H\n\nnamespace Eigen {\n\ntemplate<typename Derived>\ntemplate<typename OtherDerived>\nEIGEN_STRONG_INLINE Derived& DenseBase<Derived>\n  ::lazyAssign(const DenseBase<OtherDerived>& other)\n{\n  enum{\n    SameType = internal::is_same<typename Derived::Scalar,typename OtherDerived::Scalar>::value\n  };\n\n  EIGEN_STATIC_ASSERT_LVALUE(Derived)\n  EIGEN_STATIC_ASSERT_SAME_MATRIX_SIZE(Derived,OtherDerived)\n  EIGEN_STATIC_ASSERT(SameType,YOU_MIXED_DIFFERENT_NUMERIC_TYPES__YOU_NEED_TO_USE_THE_CAST_METHOD_OF_MATRIXBASE_TO_CAST_NUMERIC_TYPES_EXPLICITLY)\n\n  eigen_assert(rows() == other.rows() && cols() == other.cols());\n  internal::call_assignment_no_alias(derived(),other.derived());\n  \n  return derived();\n}\n\ntemplate<typename Derived>\ntemplate<typename OtherDerived>\nEIGEN_DEVICE_FUNC\nEIGEN_STRONG_INLINE Derived& DenseBase<Derived>::operator=(const DenseBase<OtherDerived>& other)\n{\n  internal::call_assignment(derived(), other.derived());\n  return derived();\n}\n\ntemplate<typename Derived>\nEIGEN_DEVICE_FUNC\nEIGEN_STRONG_INLINE Derived& DenseBase<Derived>::operator=(const DenseBase& other)\n{\n  internal::call_assignment(derived(), other.derived());\n  return derived();\n}\n\ntemplate<typename Derived>\nEIGEN_DEVICE_FUNC\nEIGEN_STRONG_INLINE Derived& MatrixBase<Derived>::operator=(const MatrixBase& other)\n{\n  internal::call_assignment(derived(), other.derived());\n  return derived();\n}\n\ntemplate<typename Derived>\ntemplate <typename OtherDerived>\nEIGEN_DEVICE_FUNC\nEIGEN_STRONG_INLINE Derived& MatrixBase<Derived>::operator=(const DenseBase<OtherDerived>& other)\n{\n  internal::call_assignment(derived(), other.derived());\n  return derived();\n}\n\ntemplate<typename Derived>\ntemplate <typename OtherDerived>\nEIGEN_DEVICE_FUNC\nEIGEN_STRONG_INLINE Derived& MatrixBase<Derived>::operator=(const EigenBase<OtherDerived>& other)\n{\n  internal::call_assignment(derived(), other.derived());\n  return derived();\n}\n\ntemplate<typename Derived>\ntemplate<typename OtherDerived>\nEIGEN_DEVICE_FUNC\nEIGEN_STRONG_INLINE Derived& MatrixBase<Derived>::operator=(const ReturnByValue<OtherDerived>& other)\n{\n  other.derived().evalTo(derived());\n  return derived();\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_ASSIGN_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/AssignEvaluator.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2011 Benoit Jacob <jacob.benoit.1@gmail.com>\n// Copyright (C) 2011-2014 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2011-2012 Jitse Niesen <jitse@maths.leeds.ac.uk>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_ASSIGN_EVALUATOR_H\n#define EIGEN_ASSIGN_EVALUATOR_H\n\nnamespace Eigen {\n\n// This implementation is based on Assign.h\n\nnamespace internal {\n  \n/***************************************************************************\n* Part 1 : the logic deciding a strategy for traversal and unrolling       *\n***************************************************************************/\n\n// copy_using_evaluator_traits is based on assign_traits\n\ntemplate <typename DstEvaluator, typename SrcEvaluator, typename AssignFunc>\nstruct copy_using_evaluator_traits\n{\n  typedef typename DstEvaluator::XprType Dst;\n  typedef typename Dst::Scalar DstScalar;\n  \n  enum {\n    DstFlags = DstEvaluator::Flags,\n    SrcFlags = SrcEvaluator::Flags\n  };\n  \npublic:\n  enum {\n    DstAlignment = DstEvaluator::Alignment,\n    SrcAlignment = SrcEvaluator::Alignment,\n    DstHasDirectAccess = DstFlags & DirectAccessBit,\n    JointAlignment = EIGEN_PLAIN_ENUM_MIN(DstAlignment,SrcAlignment)\n  };\n\nprivate:\n  enum {\n    InnerSize = int(Dst::IsVectorAtCompileTime) ? int(Dst::SizeAtCompileTime)\n              : int(DstFlags)&RowMajorBit ? int(Dst::ColsAtCompileTime)\n              : int(Dst::RowsAtCompileTime),\n    InnerMaxSize = int(Dst::IsVectorAtCompileTime) ? int(Dst::MaxSizeAtCompileTime)\n              : int(DstFlags)&RowMajorBit ? int(Dst::MaxColsAtCompileTime)\n              : int(Dst::MaxRowsAtCompileTime),\n    OuterStride = int(outer_stride_at_compile_time<Dst>::ret),\n    MaxSizeAtCompileTime = Dst::SizeAtCompileTime\n  };\n\n  // TODO distinguish between linear traversal and inner-traversals\n  typedef typename find_best_packet<DstScalar,Dst::SizeAtCompileTime>::type LinearPacketType;\n  typedef typename find_best_packet<DstScalar,InnerSize>::type InnerPacketType;\n\n  enum {\n    LinearPacketSize = unpacket_traits<LinearPacketType>::size,\n    InnerPacketSize = unpacket_traits<InnerPacketType>::size\n  };\n\npublic:\n  enum {\n    LinearRequiredAlignment = unpacket_traits<LinearPacketType>::alignment,\n    InnerRequiredAlignment = unpacket_traits<InnerPacketType>::alignment\n  };\n\nprivate:\n  enum {\n    DstIsRowMajor = DstFlags&RowMajorBit,\n    SrcIsRowMajor = SrcFlags&RowMajorBit,\n    StorageOrdersAgree = (int(DstIsRowMajor) == int(SrcIsRowMajor)),\n    MightVectorize = bool(StorageOrdersAgree)\n                  && (int(DstFlags) & int(SrcFlags) & ActualPacketAccessBit)\n                  && bool(functor_traits<AssignFunc>::PacketAccess),\n    MayInnerVectorize  = MightVectorize\n                       && int(InnerSize)!=Dynamic && int(InnerSize)%int(InnerPacketSize)==0\n                       && int(OuterStride)!=Dynamic && int(OuterStride)%int(InnerPacketSize)==0\n                       && (EIGEN_UNALIGNED_VECTORIZE  || int(JointAlignment)>=int(InnerRequiredAlignment)),\n    MayLinearize = bool(StorageOrdersAgree) && (int(DstFlags) & int(SrcFlags) & LinearAccessBit),\n    MayLinearVectorize = bool(MightVectorize) && MayLinearize && DstHasDirectAccess\n                       && (EIGEN_UNALIGNED_VECTORIZE || (int(DstAlignment)>=int(LinearRequiredAlignment)) || MaxSizeAtCompileTime == Dynamic),\n      /* If the destination isn't aligned, we have to do runtime checks and we don't unroll,\n         so it's only good for large enough sizes. */\n    MaySliceVectorize  = bool(MightVectorize) && bool(DstHasDirectAccess)\n                       && (int(InnerMaxSize)==Dynamic || int(InnerMaxSize)>=(EIGEN_UNALIGNED_VECTORIZE?InnerPacketSize:(3*InnerPacketSize)))\n      /* slice vectorization can be slow, so we only want it if the slices are big, which is\n         indicated by InnerMaxSize rather than InnerSize, think of the case of a dynamic block\n         in a fixed-size matrix\n         However, with EIGEN_UNALIGNED_VECTORIZE and unrolling, slice vectorization is still worth it */\n  };\n\npublic:\n  enum {\n    Traversal = int(MayLinearVectorize) && (LinearPacketSize>InnerPacketSize) ? int(LinearVectorizedTraversal)\n              : int(MayInnerVectorize)   ? int(InnerVectorizedTraversal)\n              : int(MayLinearVectorize)  ? int(LinearVectorizedTraversal)\n              : int(MaySliceVectorize)   ? int(SliceVectorizedTraversal)\n              : int(MayLinearize)        ? int(LinearTraversal)\n                                         : int(DefaultTraversal),\n    Vectorized = int(Traversal) == InnerVectorizedTraversal\n              || int(Traversal) == LinearVectorizedTraversal\n              || int(Traversal) == SliceVectorizedTraversal\n  };\n\n  typedef typename conditional<int(Traversal)==LinearVectorizedTraversal, LinearPacketType, InnerPacketType>::type PacketType;\n\nprivate:\n  enum {\n    ActualPacketSize    = int(Traversal)==LinearVectorizedTraversal ? LinearPacketSize\n                        : Vectorized ? InnerPacketSize\n                        : 1,\n    UnrollingLimit      = EIGEN_UNROLLING_LIMIT * ActualPacketSize,\n    MayUnrollCompletely = int(Dst::SizeAtCompileTime) != Dynamic\n                       && int(Dst::SizeAtCompileTime) * (int(DstEvaluator::CoeffReadCost)+int(SrcEvaluator::CoeffReadCost)) <= int(UnrollingLimit),\n    MayUnrollInner      = int(InnerSize) != Dynamic\n                       && int(InnerSize) * (int(DstEvaluator::CoeffReadCost)+int(SrcEvaluator::CoeffReadCost)) <= int(UnrollingLimit)\n  };\n\npublic:\n  enum {\n    Unrolling = (int(Traversal) == int(InnerVectorizedTraversal) || int(Traversal) == int(DefaultTraversal))\n                ? (\n                    int(MayUnrollCompletely) ? int(CompleteUnrolling)\n                  : int(MayUnrollInner)      ? int(InnerUnrolling)\n                                             : int(NoUnrolling)\n                  )\n              : int(Traversal) == int(LinearVectorizedTraversal)\n                ? ( bool(MayUnrollCompletely) && ( EIGEN_UNALIGNED_VECTORIZE || (int(DstAlignment)>=int(LinearRequiredAlignment)))\n                          ? int(CompleteUnrolling)\n                          : int(NoUnrolling) )\n              : int(Traversal) == int(LinearTraversal)\n                ? ( bool(MayUnrollCompletely) ? int(CompleteUnrolling) \n                                              : int(NoUnrolling) )\n#if EIGEN_UNALIGNED_VECTORIZE\n              : int(Traversal) == int(SliceVectorizedTraversal)\n                ? ( bool(MayUnrollInner) ? int(InnerUnrolling)\n                                         : int(NoUnrolling) )\n#endif\n              : int(NoUnrolling)\n  };\n\n#ifdef EIGEN_DEBUG_ASSIGN\n  static void debug()\n  {\n    std::cerr << \"DstXpr: \" << typeid(typename DstEvaluator::XprType).name() << std::endl;\n    std::cerr << \"SrcXpr: \" << typeid(typename SrcEvaluator::XprType).name() << std::endl;\n    std::cerr.setf(std::ios::hex, std::ios::basefield);\n    std::cerr << \"DstFlags\" << \" = \" << DstFlags << \" (\" << demangle_flags(DstFlags) << \" )\" << std::endl;\n    std::cerr << \"SrcFlags\" << \" = \" << SrcFlags << \" (\" << demangle_flags(SrcFlags) << \" )\" << std::endl;\n    std::cerr.unsetf(std::ios::hex);\n    EIGEN_DEBUG_VAR(DstAlignment)\n    EIGEN_DEBUG_VAR(SrcAlignment)\n    EIGEN_DEBUG_VAR(LinearRequiredAlignment)\n    EIGEN_DEBUG_VAR(InnerRequiredAlignment)\n    EIGEN_DEBUG_VAR(JointAlignment)\n    EIGEN_DEBUG_VAR(InnerSize)\n    EIGEN_DEBUG_VAR(InnerMaxSize)\n    EIGEN_DEBUG_VAR(LinearPacketSize)\n    EIGEN_DEBUG_VAR(InnerPacketSize)\n    EIGEN_DEBUG_VAR(ActualPacketSize)\n    EIGEN_DEBUG_VAR(StorageOrdersAgree)\n    EIGEN_DEBUG_VAR(MightVectorize)\n    EIGEN_DEBUG_VAR(MayLinearize)\n    EIGEN_DEBUG_VAR(MayInnerVectorize)\n    EIGEN_DEBUG_VAR(MayLinearVectorize)\n    EIGEN_DEBUG_VAR(MaySliceVectorize)\n    std::cerr << \"Traversal\" << \" = \" << Traversal << \" (\" << demangle_traversal(Traversal) << \")\" << std::endl;\n    EIGEN_DEBUG_VAR(SrcEvaluator::CoeffReadCost)\n    EIGEN_DEBUG_VAR(UnrollingLimit)\n    EIGEN_DEBUG_VAR(MayUnrollCompletely)\n    EIGEN_DEBUG_VAR(MayUnrollInner)\n    std::cerr << \"Unrolling\" << \" = \" << Unrolling << \" (\" << demangle_unrolling(Unrolling) << \")\" << std::endl;\n    std::cerr << std::endl;\n  }\n#endif\n};\n\n/***************************************************************************\n* Part 2 : meta-unrollers\n***************************************************************************/\n\n/************************\n*** Default traversal ***\n************************/\n\ntemplate<typename Kernel, int Index, int Stop>\nstruct copy_using_evaluator_DefaultTraversal_CompleteUnrolling\n{\n  // FIXME: this is not very clean, perhaps this information should be provided by the kernel?\n  typedef typename Kernel::DstEvaluatorType DstEvaluatorType;\n  typedef typename DstEvaluatorType::XprType DstXprType;\n  \n  enum {\n    outer = Index / DstXprType::InnerSizeAtCompileTime,\n    inner = Index % DstXprType::InnerSizeAtCompileTime\n  };\n\n  EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE void run(Kernel &kernel)\n  {\n    kernel.assignCoeffByOuterInner(outer, inner);\n    copy_using_evaluator_DefaultTraversal_CompleteUnrolling<Kernel, Index+1, Stop>::run(kernel);\n  }\n};\n\ntemplate<typename Kernel, int Stop>\nstruct copy_using_evaluator_DefaultTraversal_CompleteUnrolling<Kernel, Stop, Stop>\n{\n  EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE void run(Kernel&) { }\n};\n\ntemplate<typename Kernel, int Index_, int Stop>\nstruct copy_using_evaluator_DefaultTraversal_InnerUnrolling\n{\n  EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE void run(Kernel &kernel, Index outer)\n  {\n    kernel.assignCoeffByOuterInner(outer, Index_);\n    copy_using_evaluator_DefaultTraversal_InnerUnrolling<Kernel, Index_+1, Stop>::run(kernel, outer);\n  }\n};\n\ntemplate<typename Kernel, int Stop>\nstruct copy_using_evaluator_DefaultTraversal_InnerUnrolling<Kernel, Stop, Stop>\n{\n  EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE void run(Kernel&, Index) { }\n};\n\n/***********************\n*** Linear traversal ***\n***********************/\n\ntemplate<typename Kernel, int Index, int Stop>\nstruct copy_using_evaluator_LinearTraversal_CompleteUnrolling\n{\n  EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE void run(Kernel& kernel)\n  {\n    kernel.assignCoeff(Index);\n    copy_using_evaluator_LinearTraversal_CompleteUnrolling<Kernel, Index+1, Stop>::run(kernel);\n  }\n};\n\ntemplate<typename Kernel, int Stop>\nstruct copy_using_evaluator_LinearTraversal_CompleteUnrolling<Kernel, Stop, Stop>\n{\n  EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE void run(Kernel&) { }\n};\n\n/**************************\n*** Inner vectorization ***\n**************************/\n\ntemplate<typename Kernel, int Index, int Stop>\nstruct copy_using_evaluator_innervec_CompleteUnrolling\n{\n  // FIXME: this is not very clean, perhaps this information should be provided by the kernel?\n  typedef typename Kernel::DstEvaluatorType DstEvaluatorType;\n  typedef typename DstEvaluatorType::XprType DstXprType;\n  typedef typename Kernel::PacketType PacketType;\n  \n  enum {\n    outer = Index / DstXprType::InnerSizeAtCompileTime,\n    inner = Index % DstXprType::InnerSizeAtCompileTime,\n    SrcAlignment = Kernel::AssignmentTraits::SrcAlignment,\n    DstAlignment = Kernel::AssignmentTraits::DstAlignment\n  };\n\n  EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE void run(Kernel &kernel)\n  {\n    kernel.template assignPacketByOuterInner<DstAlignment, SrcAlignment, PacketType>(outer, inner);\n    enum { NextIndex = Index + unpacket_traits<PacketType>::size };\n    copy_using_evaluator_innervec_CompleteUnrolling<Kernel, NextIndex, Stop>::run(kernel);\n  }\n};\n\ntemplate<typename Kernel, int Stop>\nstruct copy_using_evaluator_innervec_CompleteUnrolling<Kernel, Stop, Stop>\n{\n  EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE void run(Kernel&) { }\n};\n\ntemplate<typename Kernel, int Index_, int Stop, int SrcAlignment, int DstAlignment>\nstruct copy_using_evaluator_innervec_InnerUnrolling\n{\n  typedef typename Kernel::PacketType PacketType;\n  EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE void run(Kernel &kernel, Index outer)\n  {\n    kernel.template assignPacketByOuterInner<DstAlignment, SrcAlignment, PacketType>(outer, Index_);\n    enum { NextIndex = Index_ + unpacket_traits<PacketType>::size };\n    copy_using_evaluator_innervec_InnerUnrolling<Kernel, NextIndex, Stop, SrcAlignment, DstAlignment>::run(kernel, outer);\n  }\n};\n\ntemplate<typename Kernel, int Stop, int SrcAlignment, int DstAlignment>\nstruct copy_using_evaluator_innervec_InnerUnrolling<Kernel, Stop, Stop, SrcAlignment, DstAlignment>\n{\n  EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE void run(Kernel &, Index) { }\n};\n\n/***************************************************************************\n* Part 3 : implementation of all cases\n***************************************************************************/\n\n// dense_assignment_loop is based on assign_impl\n\ntemplate<typename Kernel,\n         int Traversal = Kernel::AssignmentTraits::Traversal,\n         int Unrolling = Kernel::AssignmentTraits::Unrolling>\nstruct dense_assignment_loop;\n\n/************************\n*** Default traversal ***\n************************/\n\ntemplate<typename Kernel>\nstruct dense_assignment_loop<Kernel, DefaultTraversal, NoUnrolling>\n{\n  EIGEN_DEVICE_FUNC static void EIGEN_STRONG_INLINE run(Kernel &kernel)\n  {\n    for(Index outer = 0; outer < kernel.outerSize(); ++outer) {\n      for(Index inner = 0; inner < kernel.innerSize(); ++inner) {\n        kernel.assignCoeffByOuterInner(outer, inner);\n      }\n    }\n  }\n};\n\ntemplate<typename Kernel>\nstruct dense_assignment_loop<Kernel, DefaultTraversal, CompleteUnrolling>\n{\n  EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE void run(Kernel &kernel)\n  {\n    typedef typename Kernel::DstEvaluatorType::XprType DstXprType;\n    copy_using_evaluator_DefaultTraversal_CompleteUnrolling<Kernel, 0, DstXprType::SizeAtCompileTime>::run(kernel);\n  }\n};\n\ntemplate<typename Kernel>\nstruct dense_assignment_loop<Kernel, DefaultTraversal, InnerUnrolling>\n{\n  EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE void run(Kernel &kernel)\n  {\n    typedef typename Kernel::DstEvaluatorType::XprType DstXprType;\n\n    const Index outerSize = kernel.outerSize();\n    for(Index outer = 0; outer < outerSize; ++outer)\n      copy_using_evaluator_DefaultTraversal_InnerUnrolling<Kernel, 0, DstXprType::InnerSizeAtCompileTime>::run(kernel, outer);\n  }\n};\n\n/***************************\n*** Linear vectorization ***\n***************************/\n\n\n// The goal of unaligned_dense_assignment_loop is simply to factorize the handling\n// of the non vectorizable beginning and ending parts\n\ntemplate <bool IsAligned = false>\nstruct unaligned_dense_assignment_loop\n{\n  // if IsAligned = true, then do nothing\n  template <typename Kernel>\n  EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE void run(Kernel&, Index, Index) {}\n};\n\ntemplate <>\nstruct unaligned_dense_assignment_loop<false>\n{\n  // MSVC must not inline this functions. If it does, it fails to optimize the\n  // packet access path.\n  // FIXME check which version exhibits this issue\n#if EIGEN_COMP_MSVC\n  template <typename Kernel>\n  static EIGEN_DONT_INLINE void run(Kernel &kernel,\n                                    Index start,\n                                    Index end)\n#else\n  template <typename Kernel>\n  EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE void run(Kernel &kernel,\n                                      Index start,\n                                      Index end)\n#endif\n  {\n    for (Index index = start; index < end; ++index)\n      kernel.assignCoeff(index);\n  }\n};\n\ntemplate<typename Kernel>\nstruct dense_assignment_loop<Kernel, LinearVectorizedTraversal, NoUnrolling>\n{\n  EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE void run(Kernel &kernel)\n  {\n    const Index size = kernel.size();\n    typedef typename Kernel::Scalar Scalar;\n    typedef typename Kernel::PacketType PacketType;\n    enum {\n      requestedAlignment = Kernel::AssignmentTraits::LinearRequiredAlignment,\n      packetSize = unpacket_traits<PacketType>::size,\n      dstIsAligned = int(Kernel::AssignmentTraits::DstAlignment)>=int(requestedAlignment),\n      dstAlignment = packet_traits<Scalar>::AlignedOnScalar ? int(requestedAlignment)\n                                                            : int(Kernel::AssignmentTraits::DstAlignment),\n      srcAlignment = Kernel::AssignmentTraits::JointAlignment\n    };\n    const Index alignedStart = dstIsAligned ? 0 : internal::first_aligned<requestedAlignment>(kernel.dstDataPtr(), size);\n    const Index alignedEnd = alignedStart + ((size-alignedStart)/packetSize)*packetSize;\n\n    unaligned_dense_assignment_loop<dstIsAligned!=0>::run(kernel, 0, alignedStart);\n\n    for(Index index = alignedStart; index < alignedEnd; index += packetSize)\n      kernel.template assignPacket<dstAlignment, srcAlignment, PacketType>(index);\n\n    unaligned_dense_assignment_loop<>::run(kernel, alignedEnd, size);\n  }\n};\n\ntemplate<typename Kernel>\nstruct dense_assignment_loop<Kernel, LinearVectorizedTraversal, CompleteUnrolling>\n{\n  EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE void run(Kernel &kernel)\n  {\n    typedef typename Kernel::DstEvaluatorType::XprType DstXprType;\n    typedef typename Kernel::PacketType PacketType;\n    \n    enum { size = DstXprType::SizeAtCompileTime,\n           packetSize =unpacket_traits<PacketType>::size,\n           alignedSize = (size/packetSize)*packetSize };\n\n    copy_using_evaluator_innervec_CompleteUnrolling<Kernel, 0, alignedSize>::run(kernel);\n    copy_using_evaluator_DefaultTraversal_CompleteUnrolling<Kernel, alignedSize, size>::run(kernel);\n  }\n};\n\n/**************************\n*** Inner vectorization ***\n**************************/\n\ntemplate<typename Kernel>\nstruct dense_assignment_loop<Kernel, InnerVectorizedTraversal, NoUnrolling>\n{\n  typedef typename Kernel::PacketType PacketType;\n  enum {\n    SrcAlignment = Kernel::AssignmentTraits::SrcAlignment,\n    DstAlignment = Kernel::AssignmentTraits::DstAlignment\n  };\n  EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE void run(Kernel &kernel)\n  {\n    const Index innerSize = kernel.innerSize();\n    const Index outerSize = kernel.outerSize();\n    const Index packetSize = unpacket_traits<PacketType>::size;\n    for(Index outer = 0; outer < outerSize; ++outer)\n      for(Index inner = 0; inner < innerSize; inner+=packetSize)\n        kernel.template assignPacketByOuterInner<DstAlignment, SrcAlignment, PacketType>(outer, inner);\n  }\n};\n\ntemplate<typename Kernel>\nstruct dense_assignment_loop<Kernel, InnerVectorizedTraversal, CompleteUnrolling>\n{\n  EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE void run(Kernel &kernel)\n  {\n    typedef typename Kernel::DstEvaluatorType::XprType DstXprType;\n    copy_using_evaluator_innervec_CompleteUnrolling<Kernel, 0, DstXprType::SizeAtCompileTime>::run(kernel);\n  }\n};\n\ntemplate<typename Kernel>\nstruct dense_assignment_loop<Kernel, InnerVectorizedTraversal, InnerUnrolling>\n{\n  EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE void run(Kernel &kernel)\n  {\n    typedef typename Kernel::DstEvaluatorType::XprType DstXprType;\n    typedef typename Kernel::AssignmentTraits Traits;\n    const Index outerSize = kernel.outerSize();\n    for(Index outer = 0; outer < outerSize; ++outer)\n      copy_using_evaluator_innervec_InnerUnrolling<Kernel, 0, DstXprType::InnerSizeAtCompileTime,\n                                                   Traits::SrcAlignment, Traits::DstAlignment>::run(kernel, outer);\n  }\n};\n\n/***********************\n*** Linear traversal ***\n***********************/\n\ntemplate<typename Kernel>\nstruct dense_assignment_loop<Kernel, LinearTraversal, NoUnrolling>\n{\n  EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE void run(Kernel &kernel)\n  {\n    const Index size = kernel.size();\n    for(Index i = 0; i < size; ++i)\n      kernel.assignCoeff(i);\n  }\n};\n\ntemplate<typename Kernel>\nstruct dense_assignment_loop<Kernel, LinearTraversal, CompleteUnrolling>\n{\n  EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE void run(Kernel &kernel)\n  {\n    typedef typename Kernel::DstEvaluatorType::XprType DstXprType;\n    copy_using_evaluator_LinearTraversal_CompleteUnrolling<Kernel, 0, DstXprType::SizeAtCompileTime>::run(kernel);\n  }\n};\n\n/**************************\n*** Slice vectorization ***\n***************************/\n\ntemplate<typename Kernel>\nstruct dense_assignment_loop<Kernel, SliceVectorizedTraversal, NoUnrolling>\n{\n  EIGEN_DEVICE_FUNC static inline void run(Kernel &kernel)\n  {\n    typedef typename Kernel::Scalar Scalar;\n    typedef typename Kernel::PacketType PacketType;\n    enum {\n      packetSize = unpacket_traits<PacketType>::size,\n      requestedAlignment = int(Kernel::AssignmentTraits::InnerRequiredAlignment),\n      alignable = packet_traits<Scalar>::AlignedOnScalar || int(Kernel::AssignmentTraits::DstAlignment)>=sizeof(Scalar),\n      dstIsAligned = int(Kernel::AssignmentTraits::DstAlignment)>=int(requestedAlignment),\n      dstAlignment = alignable ? int(requestedAlignment)\n                               : int(Kernel::AssignmentTraits::DstAlignment)\n    };\n    const Scalar *dst_ptr = kernel.dstDataPtr();\n    if((!bool(dstIsAligned)) && (UIntPtr(dst_ptr) % sizeof(Scalar))>0)\n    {\n      // the pointer is not aligend-on scalar, so alignment is not possible\n      return dense_assignment_loop<Kernel,DefaultTraversal,NoUnrolling>::run(kernel);\n    }\n    const Index packetAlignedMask = packetSize - 1;\n    const Index innerSize = kernel.innerSize();\n    const Index outerSize = kernel.outerSize();\n    const Index alignedStep = alignable ? (packetSize - kernel.outerStride() % packetSize) & packetAlignedMask : 0;\n    Index alignedStart = ((!alignable) || bool(dstIsAligned)) ? 0 : internal::first_aligned<requestedAlignment>(dst_ptr, innerSize);\n\n    for(Index outer = 0; outer < outerSize; ++outer)\n    {\n      const Index alignedEnd = alignedStart + ((innerSize-alignedStart) & ~packetAlignedMask);\n      // do the non-vectorizable part of the assignment\n      for(Index inner = 0; inner<alignedStart ; ++inner)\n        kernel.assignCoeffByOuterInner(outer, inner);\n\n      // do the vectorizable part of the assignment\n      for(Index inner = alignedStart; inner<alignedEnd; inner+=packetSize)\n        kernel.template assignPacketByOuterInner<dstAlignment, Unaligned, PacketType>(outer, inner);\n\n      // do the non-vectorizable part of the assignment\n      for(Index inner = alignedEnd; inner<innerSize ; ++inner)\n        kernel.assignCoeffByOuterInner(outer, inner);\n\n      alignedStart = numext::mini((alignedStart+alignedStep)%packetSize, innerSize);\n    }\n  }\n};\n\n#if EIGEN_UNALIGNED_VECTORIZE\ntemplate<typename Kernel>\nstruct dense_assignment_loop<Kernel, SliceVectorizedTraversal, InnerUnrolling>\n{\n  EIGEN_DEVICE_FUNC static inline void run(Kernel &kernel)\n  {\n    typedef typename Kernel::DstEvaluatorType::XprType DstXprType;\n    typedef typename Kernel::PacketType PacketType;\n\n    enum { size = DstXprType::InnerSizeAtCompileTime,\n           packetSize =unpacket_traits<PacketType>::size,\n           vectorizableSize = (size/packetSize)*packetSize };\n\n    for(Index outer = 0; outer < kernel.outerSize(); ++outer)\n    {\n      copy_using_evaluator_innervec_InnerUnrolling<Kernel, 0, vectorizableSize, 0, 0>::run(kernel, outer);\n      copy_using_evaluator_DefaultTraversal_InnerUnrolling<Kernel, vectorizableSize, size>::run(kernel, outer);\n    }\n  }\n};\n#endif\n\n\n/***************************************************************************\n* Part 4 : Generic dense assignment kernel\n***************************************************************************/\n\n// This class generalize the assignment of a coefficient (or packet) from one dense evaluator\n// to another dense writable evaluator.\n// It is parametrized by the two evaluators, and the actual assignment functor.\n// This abstraction level permits to keep the evaluation loops as simple and as generic as possible.\n// One can customize the assignment using this generic dense_assignment_kernel with different\n// functors, or by completely overloading it, by-passing a functor.\ntemplate<typename DstEvaluatorTypeT, typename SrcEvaluatorTypeT, typename Functor, int Version = Specialized>\nclass generic_dense_assignment_kernel\n{\nprotected:\n  typedef typename DstEvaluatorTypeT::XprType DstXprType;\n  typedef typename SrcEvaluatorTypeT::XprType SrcXprType;\npublic:\n  \n  typedef DstEvaluatorTypeT DstEvaluatorType;\n  typedef SrcEvaluatorTypeT SrcEvaluatorType;\n  typedef typename DstEvaluatorType::Scalar Scalar;\n  typedef copy_using_evaluator_traits<DstEvaluatorTypeT, SrcEvaluatorTypeT, Functor> AssignmentTraits;\n  typedef typename AssignmentTraits::PacketType PacketType;\n  \n  \n  EIGEN_DEVICE_FUNC generic_dense_assignment_kernel(DstEvaluatorType &dst, const SrcEvaluatorType &src, const Functor &func, DstXprType& dstExpr)\n    : m_dst(dst), m_src(src), m_functor(func), m_dstExpr(dstExpr)\n  {\n    #ifdef EIGEN_DEBUG_ASSIGN\n    AssignmentTraits::debug();\n    #endif\n  }\n  \n  EIGEN_DEVICE_FUNC Index size() const        { return m_dstExpr.size(); }\n  EIGEN_DEVICE_FUNC Index innerSize() const   { return m_dstExpr.innerSize(); }\n  EIGEN_DEVICE_FUNC Index outerSize() const   { return m_dstExpr.outerSize(); }\n  EIGEN_DEVICE_FUNC Index rows() const        { return m_dstExpr.rows(); }\n  EIGEN_DEVICE_FUNC Index cols() const        { return m_dstExpr.cols(); }\n  EIGEN_DEVICE_FUNC Index outerStride() const { return m_dstExpr.outerStride(); }\n  \n  EIGEN_DEVICE_FUNC DstEvaluatorType& dstEvaluator() { return m_dst; }\n  EIGEN_DEVICE_FUNC const SrcEvaluatorType& srcEvaluator() const { return m_src; }\n  \n  /// Assign src(row,col) to dst(row,col) through the assignment functor.\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE void assignCoeff(Index row, Index col)\n  {\n    m_functor.assignCoeff(m_dst.coeffRef(row,col), m_src.coeff(row,col));\n  }\n  \n  /// \\sa assignCoeff(Index,Index)\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE void assignCoeff(Index index)\n  {\n    m_functor.assignCoeff(m_dst.coeffRef(index), m_src.coeff(index));\n  }\n  \n  /// \\sa assignCoeff(Index,Index)\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE void assignCoeffByOuterInner(Index outer, Index inner)\n  {\n    Index row = rowIndexByOuterInner(outer, inner); \n    Index col = colIndexByOuterInner(outer, inner); \n    assignCoeff(row, col);\n  }\n  \n  \n  template<int StoreMode, int LoadMode, typename PacketType>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE void assignPacket(Index row, Index col)\n  {\n    m_functor.template assignPacket<StoreMode>(&m_dst.coeffRef(row,col), m_src.template packet<LoadMode,PacketType>(row,col));\n  }\n  \n  template<int StoreMode, int LoadMode, typename PacketType>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE void assignPacket(Index index)\n  {\n    m_functor.template assignPacket<StoreMode>(&m_dst.coeffRef(index), m_src.template packet<LoadMode,PacketType>(index));\n  }\n  \n  template<int StoreMode, int LoadMode, typename PacketType>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE void assignPacketByOuterInner(Index outer, Index inner)\n  {\n    Index row = rowIndexByOuterInner(outer, inner); \n    Index col = colIndexByOuterInner(outer, inner);\n    assignPacket<StoreMode,LoadMode,PacketType>(row, col);\n  }\n  \n  EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE Index rowIndexByOuterInner(Index outer, Index inner)\n  {\n    typedef typename DstEvaluatorType::ExpressionTraits Traits;\n    return int(Traits::RowsAtCompileTime) == 1 ? 0\n      : int(Traits::ColsAtCompileTime) == 1 ? inner\n      : int(DstEvaluatorType::Flags)&RowMajorBit ? outer\n      : inner;\n  }\n\n  EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE Index colIndexByOuterInner(Index outer, Index inner)\n  {\n    typedef typename DstEvaluatorType::ExpressionTraits Traits;\n    return int(Traits::ColsAtCompileTime) == 1 ? 0\n      : int(Traits::RowsAtCompileTime) == 1 ? inner\n      : int(DstEvaluatorType::Flags)&RowMajorBit ? inner\n      : outer;\n  }\n\n  EIGEN_DEVICE_FUNC const Scalar* dstDataPtr() const\n  {\n    return m_dstExpr.data();\n  }\n  \nprotected:\n  DstEvaluatorType& m_dst;\n  const SrcEvaluatorType& m_src;\n  const Functor &m_functor;\n  // TODO find a way to avoid the needs of the original expression\n  DstXprType& m_dstExpr;\n};\n\n/***************************************************************************\n* Part 5 : Entry point for dense rectangular assignment\n***************************************************************************/\n\ntemplate<typename DstXprType, typename SrcXprType, typename Functor>\nEIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE void call_dense_assignment_loop(DstXprType& dst, const SrcXprType& src, const Functor &func)\n{\n  typedef evaluator<DstXprType> DstEvaluatorType;\n  typedef evaluator<SrcXprType> SrcEvaluatorType;\n\n  SrcEvaluatorType srcEvaluator(src);\n\n  // NOTE To properly handle A = (A*A.transpose())/s with A rectangular,\n  // we need to resize the destination after the source evaluator has been created.\n  Index dstRows = src.rows();\n  Index dstCols = src.cols();\n  if((dst.rows()!=dstRows) || (dst.cols()!=dstCols))\n    dst.resize(dstRows, dstCols);\n\n  DstEvaluatorType dstEvaluator(dst);\n    \n  typedef generic_dense_assignment_kernel<DstEvaluatorType,SrcEvaluatorType,Functor> Kernel;\n  Kernel kernel(dstEvaluator, srcEvaluator, func, dst.const_cast_derived());\n\n  dense_assignment_loop<Kernel>::run(kernel);\n}\n\ntemplate<typename DstXprType, typename SrcXprType>\nEIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE void call_dense_assignment_loop(DstXprType& dst, const SrcXprType& src)\n{\n  call_dense_assignment_loop(dst, src, internal::assign_op<typename DstXprType::Scalar,typename SrcXprType::Scalar>());\n}\n\n/***************************************************************************\n* Part 6 : Generic assignment\n***************************************************************************/\n\n// Based on the respective shapes of the destination and source,\n// the class AssignmentKind determine the kind of assignment mechanism.\n// AssignmentKind must define a Kind typedef.\ntemplate<typename DstShape, typename SrcShape> struct AssignmentKind;\n\n// Assignement kind defined in this file:\nstruct Dense2Dense {};\nstruct EigenBase2EigenBase {};\n\ntemplate<typename,typename> struct AssignmentKind { typedef EigenBase2EigenBase Kind; };\ntemplate<> struct AssignmentKind<DenseShape,DenseShape> { typedef Dense2Dense Kind; };\n    \n// This is the main assignment class\ntemplate< typename DstXprType, typename SrcXprType, typename Functor,\n          typename Kind = typename AssignmentKind< typename evaluator_traits<DstXprType>::Shape , typename evaluator_traits<SrcXprType>::Shape >::Kind,\n          typename EnableIf = void>\nstruct Assignment;\n\n\n// The only purpose of this call_assignment() function is to deal with noalias() / \"assume-aliasing\" and automatic transposition.\n// Indeed, I (Gael) think that this concept of \"assume-aliasing\" was a mistake, and it makes thing quite complicated.\n// So this intermediate function removes everything related to \"assume-aliasing\" such that Assignment\n// does not has to bother about these annoying details.\n\ntemplate<typename Dst, typename Src>\nEIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\nvoid call_assignment(Dst& dst, const Src& src)\n{\n  call_assignment(dst, src, internal::assign_op<typename Dst::Scalar,typename Src::Scalar>());\n}\ntemplate<typename Dst, typename Src>\nEIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\nvoid call_assignment(const Dst& dst, const Src& src)\n{\n  call_assignment(dst, src, internal::assign_op<typename Dst::Scalar,typename Src::Scalar>());\n}\n                     \n// Deal with \"assume-aliasing\"\ntemplate<typename Dst, typename Src, typename Func>\nEIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\nvoid call_assignment(Dst& dst, const Src& src, const Func& func, typename enable_if< evaluator_assume_aliasing<Src>::value, void*>::type = 0)\n{\n  typename plain_matrix_type<Src>::type tmp(src);\n  call_assignment_no_alias(dst, tmp, func);\n}\n\ntemplate<typename Dst, typename Src, typename Func>\nEIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\nvoid call_assignment(Dst& dst, const Src& src, const Func& func, typename enable_if<!evaluator_assume_aliasing<Src>::value, void*>::type = 0)\n{\n  call_assignment_no_alias(dst, src, func);\n}\n\n// by-pass \"assume-aliasing\"\n// When there is no aliasing, we require that 'dst' has been properly resized\ntemplate<typename Dst, template <typename> class StorageBase, typename Src, typename Func>\nEIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\nvoid call_assignment(NoAlias<Dst,StorageBase>& dst, const Src& src, const Func& func)\n{\n  call_assignment_no_alias(dst.expression(), src, func);\n}\n\n\ntemplate<typename Dst, typename Src, typename Func>\nEIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\nvoid call_assignment_no_alias(Dst& dst, const Src& src, const Func& func)\n{\n  enum {\n    NeedToTranspose = (    (int(Dst::RowsAtCompileTime) == 1 && int(Src::ColsAtCompileTime) == 1)\n                        || (int(Dst::ColsAtCompileTime) == 1 && int(Src::RowsAtCompileTime) == 1)\n                      ) && int(Dst::SizeAtCompileTime) != 1\n  };\n\n  typedef typename internal::conditional<NeedToTranspose, Transpose<Dst>, Dst>::type ActualDstTypeCleaned;\n  typedef typename internal::conditional<NeedToTranspose, Transpose<Dst>, Dst&>::type ActualDstType;\n  ActualDstType actualDst(dst);\n  \n  // TODO check whether this is the right place to perform these checks:\n  EIGEN_STATIC_ASSERT_LVALUE(Dst)\n  EIGEN_STATIC_ASSERT_SAME_MATRIX_SIZE(ActualDstTypeCleaned,Src)\n  EIGEN_CHECK_BINARY_COMPATIBILIY(Func,typename ActualDstTypeCleaned::Scalar,typename Src::Scalar);\n  \n  Assignment<ActualDstTypeCleaned,Src,Func>::run(actualDst, src, func);\n}\ntemplate<typename Dst, typename Src>\nEIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\nvoid call_assignment_no_alias(Dst& dst, const Src& src)\n{\n  call_assignment_no_alias(dst, src, internal::assign_op<typename Dst::Scalar,typename Src::Scalar>());\n}\n\ntemplate<typename Dst, typename Src, typename Func>\nEIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\nvoid call_assignment_no_alias_no_transpose(Dst& dst, const Src& src, const Func& func)\n{\n  // TODO check whether this is the right place to perform these checks:\n  EIGEN_STATIC_ASSERT_LVALUE(Dst)\n  EIGEN_STATIC_ASSERT_SAME_MATRIX_SIZE(Dst,Src)\n  EIGEN_CHECK_BINARY_COMPATIBILIY(Func,typename Dst::Scalar,typename Src::Scalar);\n\n  Assignment<Dst,Src,Func>::run(dst, src, func);\n}\ntemplate<typename Dst, typename Src>\nEIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\nvoid call_assignment_no_alias_no_transpose(Dst& dst, const Src& src)\n{\n  call_assignment_no_alias_no_transpose(dst, src, internal::assign_op<typename Dst::Scalar,typename Src::Scalar>());\n}\n\n// forward declaration\ntemplate<typename Dst, typename Src> void check_for_aliasing(const Dst &dst, const Src &src);\n\n// Generic Dense to Dense assignment\n// Note that the last template argument \"Weak\" is needed to make it possible to perform\n// both partial specialization+SFINAE without ambiguous specialization\ntemplate< typename DstXprType, typename SrcXprType, typename Functor, typename Weak>\nstruct Assignment<DstXprType, SrcXprType, Functor, Dense2Dense, Weak>\n{\n  EIGEN_DEVICE_FUNC\n  static EIGEN_STRONG_INLINE void run(DstXprType &dst, const SrcXprType &src, const Functor &func)\n  {\n#ifndef EIGEN_NO_DEBUG\n    internal::check_for_aliasing(dst, src);\n#endif\n    \n    call_dense_assignment_loop(dst, src, func);\n  }\n};\n\n// Generic assignment through evalTo.\n// TODO: not sure we have to keep that one, but it helps porting current code to new evaluator mechanism.\n// Note that the last template argument \"Weak\" is needed to make it possible to perform\n// both partial specialization+SFINAE without ambiguous specialization\ntemplate< typename DstXprType, typename SrcXprType, typename Functor, typename Weak>\nstruct Assignment<DstXprType, SrcXprType, Functor, EigenBase2EigenBase, Weak>\n{\n  EIGEN_DEVICE_FUNC\n  static EIGEN_STRONG_INLINE void run(DstXprType &dst, const SrcXprType &src, const internal::assign_op<typename DstXprType::Scalar,typename SrcXprType::Scalar> &/*func*/)\n  {\n    Index dstRows = src.rows();\n    Index dstCols = src.cols();\n    if((dst.rows()!=dstRows) || (dst.cols()!=dstCols))\n      dst.resize(dstRows, dstCols);\n\n    eigen_assert(dst.rows() == src.rows() && dst.cols() == src.cols());\n    src.evalTo(dst);\n  }\n\n  // NOTE The following two functions are templated to avoid their instanciation if not needed\n  //      This is needed because some expressions supports evalTo only and/or have 'void' as scalar type.\n  template<typename SrcScalarType>\n  EIGEN_DEVICE_FUNC\n  static EIGEN_STRONG_INLINE void run(DstXprType &dst, const SrcXprType &src, const internal::add_assign_op<typename DstXprType::Scalar,SrcScalarType> &/*func*/)\n  {\n    Index dstRows = src.rows();\n    Index dstCols = src.cols();\n    if((dst.rows()!=dstRows) || (dst.cols()!=dstCols))\n      dst.resize(dstRows, dstCols);\n\n    eigen_assert(dst.rows() == src.rows() && dst.cols() == src.cols());\n    src.addTo(dst);\n  }\n\n  template<typename SrcScalarType>\n  EIGEN_DEVICE_FUNC\n  static EIGEN_STRONG_INLINE void run(DstXprType &dst, const SrcXprType &src, const internal::sub_assign_op<typename DstXprType::Scalar,SrcScalarType> &/*func*/)\n  {\n    Index dstRows = src.rows();\n    Index dstCols = src.cols();\n    if((dst.rows()!=dstRows) || (dst.cols()!=dstCols))\n      dst.resize(dstRows, dstCols);\n\n    eigen_assert(dst.rows() == src.rows() && dst.cols() == src.cols());\n    src.subTo(dst);\n  }\n};\n\n} // namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_ASSIGN_EVALUATOR_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/Assign_MKL.h",
    "content": "/*\n Copyright (c) 2011, Intel Corporation. All rights reserved.\n Copyright (C) 2015 Gael Guennebaud <gael.guennebaud@inria.fr>\n \n Redistribution and use in source and binary forms, with or without modification,\n are permitted provided that the following conditions are met:\n\n * Redistributions of source code must retain the above copyright notice, this\n   list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright notice,\n   this list of conditions and the following disclaimer in the documentation\n   and/or other materials provided with the distribution.\n * Neither the name of Intel Corporation nor the names of its contributors may\n   be used to endorse or promote products derived from this software without\n   specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n ********************************************************************************\n *   Content : Eigen bindings to Intel(R) MKL\n *   MKL VML support for coefficient-wise unary Eigen expressions like a=b.sin()\n ********************************************************************************\n*/\n\n#ifndef EIGEN_ASSIGN_VML_H\n#define EIGEN_ASSIGN_VML_H\n\nnamespace Eigen { \n\nnamespace internal {\n\ntemplate<typename Dst, typename Src>\nclass vml_assign_traits\n{\n  private:\n    enum {\n      DstHasDirectAccess = Dst::Flags & DirectAccessBit,\n      SrcHasDirectAccess = Src::Flags & DirectAccessBit,\n      StorageOrdersAgree = (int(Dst::IsRowMajor) == int(Src::IsRowMajor)),\n      InnerSize = int(Dst::IsVectorAtCompileTime) ? int(Dst::SizeAtCompileTime)\n                : int(Dst::Flags)&RowMajorBit ? int(Dst::ColsAtCompileTime)\n                : int(Dst::RowsAtCompileTime),\n      InnerMaxSize  = int(Dst::IsVectorAtCompileTime) ? int(Dst::MaxSizeAtCompileTime)\n                    : int(Dst::Flags)&RowMajorBit ? int(Dst::MaxColsAtCompileTime)\n                    : int(Dst::MaxRowsAtCompileTime),\n      MaxSizeAtCompileTime = Dst::SizeAtCompileTime,\n\n      MightEnableVml = StorageOrdersAgree && DstHasDirectAccess && SrcHasDirectAccess && Src::InnerStrideAtCompileTime==1 && Dst::InnerStrideAtCompileTime==1,\n      MightLinearize = MightEnableVml && (int(Dst::Flags) & int(Src::Flags) & LinearAccessBit),\n      VmlSize = MightLinearize ? MaxSizeAtCompileTime : InnerMaxSize,\n      LargeEnough = VmlSize==Dynamic || VmlSize>=EIGEN_MKL_VML_THRESHOLD\n    };\n  public:\n    enum {\n      EnableVml = MightEnableVml && LargeEnough,\n      Traversal = MightLinearize ? LinearTraversal : DefaultTraversal\n    };\n};\n\n#define EIGEN_PP_EXPAND(ARG) ARG\n#if !defined (EIGEN_FAST_MATH) || (EIGEN_FAST_MATH != 1)\n#define EIGEN_VMLMODE_EXPAND_LA , VML_HA\n#else\n#define EIGEN_VMLMODE_EXPAND_LA , VML_LA\n#endif\n\n#define EIGEN_VMLMODE_EXPAND__ \n\n#define EIGEN_VMLMODE_PREFIX_LA vm\n#define EIGEN_VMLMODE_PREFIX__  v\n#define EIGEN_VMLMODE_PREFIX(VMLMODE) EIGEN_CAT(EIGEN_VMLMODE_PREFIX_,VMLMODE)\n\n#define EIGEN_MKL_VML_DECLARE_UNARY_CALL(EIGENOP, VMLOP, EIGENTYPE, VMLTYPE, VMLMODE)                                           \\\n  template< typename DstXprType, typename SrcXprNested>                                                                         \\\n  struct Assignment<DstXprType, CwiseUnaryOp<scalar_##EIGENOP##_op<EIGENTYPE>, SrcXprNested>, assign_op<EIGENTYPE,EIGENTYPE>,   \\\n                   Dense2Dense, typename enable_if<vml_assign_traits<DstXprType,SrcXprNested>::EnableVml>::type> {              \\\n    typedef CwiseUnaryOp<scalar_##EIGENOP##_op<EIGENTYPE>, SrcXprNested> SrcXprType;                                            \\\n    static void run(DstXprType &dst, const SrcXprType &src, const assign_op<EIGENTYPE,EIGENTYPE> &/*func*/) {                   \\\n      eigen_assert(dst.rows() == src.rows() && dst.cols() == src.cols());                                                       \\\n      if(vml_assign_traits<DstXprType,SrcXprNested>::Traversal==LinearTraversal) {                                              \\\n        VMLOP(dst.size(), (const VMLTYPE*)src.nestedExpression().data(),                                                        \\\n              (VMLTYPE*)dst.data() EIGEN_PP_EXPAND(EIGEN_VMLMODE_EXPAND_##VMLMODE) );                                           \\\n      } else {                                                                                                                  \\\n        const Index outerSize = dst.outerSize();                                                                                \\\n        for(Index outer = 0; outer < outerSize; ++outer) {                                                                      \\\n          const EIGENTYPE *src_ptr = src.IsRowMajor ? &(src.nestedExpression().coeffRef(outer,0)) :                             \\\n                                                      &(src.nestedExpression().coeffRef(0, outer));                             \\\n          EIGENTYPE *dst_ptr = dst.IsRowMajor ? &(dst.coeffRef(outer,0)) : &(dst.coeffRef(0, outer));                           \\\n          VMLOP( dst.innerSize(), (const VMLTYPE*)src_ptr,                                                                      \\\n                (VMLTYPE*)dst_ptr EIGEN_PP_EXPAND(EIGEN_VMLMODE_EXPAND_##VMLMODE));                                             \\\n        }                                                                                                                       \\\n      }                                                                                                                         \\\n    }                                                                                                                           \\\n  };                                                                                                                            \\\n\n\n#define EIGEN_MKL_VML_DECLARE_UNARY_CALLS_REAL(EIGENOP, VMLOP, VMLMODE)                                                         \\\n  EIGEN_MKL_VML_DECLARE_UNARY_CALL(EIGENOP, EIGEN_CAT(EIGEN_VMLMODE_PREFIX(VMLMODE),s##VMLOP), float, float, VMLMODE)           \\\n  EIGEN_MKL_VML_DECLARE_UNARY_CALL(EIGENOP, EIGEN_CAT(EIGEN_VMLMODE_PREFIX(VMLMODE),d##VMLOP), double, double, VMLMODE)\n\n#define EIGEN_MKL_VML_DECLARE_UNARY_CALLS_CPLX(EIGENOP, VMLOP, VMLMODE)                                                         \\\n  EIGEN_MKL_VML_DECLARE_UNARY_CALL(EIGENOP, EIGEN_CAT(EIGEN_VMLMODE_PREFIX(VMLMODE),c##VMLOP), scomplex, MKL_Complex8, VMLMODE) \\\n  EIGEN_MKL_VML_DECLARE_UNARY_CALL(EIGENOP, EIGEN_CAT(EIGEN_VMLMODE_PREFIX(VMLMODE),z##VMLOP), dcomplex, MKL_Complex16, VMLMODE)\n  \n#define EIGEN_MKL_VML_DECLARE_UNARY_CALLS(EIGENOP, VMLOP, VMLMODE)                                                              \\\n  EIGEN_MKL_VML_DECLARE_UNARY_CALLS_REAL(EIGENOP, VMLOP, VMLMODE)                                                               \\\n  EIGEN_MKL_VML_DECLARE_UNARY_CALLS_CPLX(EIGENOP, VMLOP, VMLMODE)\n\n  \nEIGEN_MKL_VML_DECLARE_UNARY_CALLS(sin,   Sin,   LA)\nEIGEN_MKL_VML_DECLARE_UNARY_CALLS(asin,  Asin,  LA)\nEIGEN_MKL_VML_DECLARE_UNARY_CALLS(sinh,  Sinh,  LA)\nEIGEN_MKL_VML_DECLARE_UNARY_CALLS(cos,   Cos,   LA)\nEIGEN_MKL_VML_DECLARE_UNARY_CALLS(acos,  Acos,  LA)\nEIGEN_MKL_VML_DECLARE_UNARY_CALLS(cosh,  Cosh,  LA)\nEIGEN_MKL_VML_DECLARE_UNARY_CALLS(tan,   Tan,   LA)\nEIGEN_MKL_VML_DECLARE_UNARY_CALLS(atan,  Atan,  LA)\nEIGEN_MKL_VML_DECLARE_UNARY_CALLS(tanh,  Tanh,  LA)\n// EIGEN_MKL_VML_DECLARE_UNARY_CALLS(abs,   Abs,    _)\nEIGEN_MKL_VML_DECLARE_UNARY_CALLS(exp,   Exp,   LA)\nEIGEN_MKL_VML_DECLARE_UNARY_CALLS(log,   Ln,    LA)\nEIGEN_MKL_VML_DECLARE_UNARY_CALLS(log10, Log10, LA)\nEIGEN_MKL_VML_DECLARE_UNARY_CALLS(sqrt,  Sqrt,  _)\n\nEIGEN_MKL_VML_DECLARE_UNARY_CALLS_REAL(square, Sqr,   _)\nEIGEN_MKL_VML_DECLARE_UNARY_CALLS_CPLX(arg, Arg,      _)\nEIGEN_MKL_VML_DECLARE_UNARY_CALLS_REAL(round, Round,  _)\nEIGEN_MKL_VML_DECLARE_UNARY_CALLS_REAL(floor, Floor,  _)\nEIGEN_MKL_VML_DECLARE_UNARY_CALLS_REAL(ceil,  Ceil,   _)\n\n#define EIGEN_MKL_VML_DECLARE_POW_CALL(EIGENOP, VMLOP, EIGENTYPE, VMLTYPE, VMLMODE)                                           \\\n  template< typename DstXprType, typename SrcXprNested, typename Plain>                                                       \\\n  struct Assignment<DstXprType, CwiseBinaryOp<scalar_##EIGENOP##_op<EIGENTYPE,EIGENTYPE>, SrcXprNested,                       \\\n                    const CwiseNullaryOp<internal::scalar_constant_op<EIGENTYPE>,Plain> >, assign_op<EIGENTYPE,EIGENTYPE>,    \\\n                   Dense2Dense, typename enable_if<vml_assign_traits<DstXprType,SrcXprNested>::EnableVml>::type> {            \\\n    typedef CwiseBinaryOp<scalar_##EIGENOP##_op<EIGENTYPE,EIGENTYPE>, SrcXprNested,                                           \\\n                    const CwiseNullaryOp<internal::scalar_constant_op<EIGENTYPE>,Plain> > SrcXprType;                         \\\n    static void run(DstXprType &dst, const SrcXprType &src, const assign_op<EIGENTYPE,EIGENTYPE> &/*func*/) {                 \\\n      eigen_assert(dst.rows() == src.rows() && dst.cols() == src.cols());                                                     \\\n      VMLTYPE exponent = reinterpret_cast<const VMLTYPE&>(src.rhs().functor().m_other);                                       \\\n      if(vml_assign_traits<DstXprType,SrcXprNested>::Traversal==LinearTraversal)                                              \\\n      {                                                                                                                       \\\n        VMLOP( dst.size(), (const VMLTYPE*)src.lhs().data(), exponent,                                                        \\\n              (VMLTYPE*)dst.data() EIGEN_PP_EXPAND(EIGEN_VMLMODE_EXPAND_##VMLMODE) );                                         \\\n      } else {                                                                                                                \\\n        const Index outerSize = dst.outerSize();                                                                              \\\n        for(Index outer = 0; outer < outerSize; ++outer) {                                                                    \\\n          const EIGENTYPE *src_ptr = src.IsRowMajor ? &(src.lhs().coeffRef(outer,0)) :                                        \\\n                                                      &(src.lhs().coeffRef(0, outer));                                        \\\n          EIGENTYPE *dst_ptr = dst.IsRowMajor ? &(dst.coeffRef(outer,0)) : &(dst.coeffRef(0, outer));                         \\\n          VMLOP( dst.innerSize(), (const VMLTYPE*)src_ptr, exponent,                                                          \\\n                 (VMLTYPE*)dst_ptr EIGEN_PP_EXPAND(EIGEN_VMLMODE_EXPAND_##VMLMODE));                                          \\\n        }                                                                                                                     \\\n      }                                                                                                                       \\\n    }                                                                                                                         \\\n  };\n  \nEIGEN_MKL_VML_DECLARE_POW_CALL(pow, vmsPowx, float,    float,         LA)\nEIGEN_MKL_VML_DECLARE_POW_CALL(pow, vmdPowx, double,   double,        LA)\nEIGEN_MKL_VML_DECLARE_POW_CALL(pow, vmcPowx, scomplex, MKL_Complex8,  LA)\nEIGEN_MKL_VML_DECLARE_POW_CALL(pow, vmzPowx, dcomplex, MKL_Complex16, LA)\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_ASSIGN_VML_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/BandMatrix.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_BANDMATRIX_H\n#define EIGEN_BANDMATRIX_H\n\nnamespace Eigen { \n\nnamespace internal {\n\ntemplate<typename Derived>\nclass BandMatrixBase : public EigenBase<Derived>\n{\n  public:\n\n    enum {\n      Flags = internal::traits<Derived>::Flags,\n      CoeffReadCost = internal::traits<Derived>::CoeffReadCost,\n      RowsAtCompileTime = internal::traits<Derived>::RowsAtCompileTime,\n      ColsAtCompileTime = internal::traits<Derived>::ColsAtCompileTime,\n      MaxRowsAtCompileTime = internal::traits<Derived>::MaxRowsAtCompileTime,\n      MaxColsAtCompileTime = internal::traits<Derived>::MaxColsAtCompileTime,\n      Supers = internal::traits<Derived>::Supers,\n      Subs   = internal::traits<Derived>::Subs,\n      Options = internal::traits<Derived>::Options\n    };\n    typedef typename internal::traits<Derived>::Scalar Scalar;\n    typedef Matrix<Scalar,RowsAtCompileTime,ColsAtCompileTime> DenseMatrixType;\n    typedef typename DenseMatrixType::StorageIndex StorageIndex;\n    typedef typename internal::traits<Derived>::CoefficientsType CoefficientsType;\n    typedef EigenBase<Derived> Base;\n\n  protected:\n    enum {\n      DataRowsAtCompileTime = ((Supers!=Dynamic) && (Subs!=Dynamic))\n                            ? 1 + Supers + Subs\n                            : Dynamic,\n      SizeAtCompileTime = EIGEN_SIZE_MIN_PREFER_DYNAMIC(RowsAtCompileTime,ColsAtCompileTime)\n    };\n\n  public:\n    \n    using Base::derived;\n    using Base::rows;\n    using Base::cols;\n\n    /** \\returns the number of super diagonals */\n    inline Index supers() const { return derived().supers(); }\n\n    /** \\returns the number of sub diagonals */\n    inline Index subs() const { return derived().subs(); }\n    \n    /** \\returns an expression of the underlying coefficient matrix */\n    inline const CoefficientsType& coeffs() const { return derived().coeffs(); }\n    \n    /** \\returns an expression of the underlying coefficient matrix */\n    inline CoefficientsType& coeffs() { return derived().coeffs(); }\n\n    /** \\returns a vector expression of the \\a i -th column,\n      * only the meaningful part is returned.\n      * \\warning the internal storage must be column major. */\n    inline Block<CoefficientsType,Dynamic,1> col(Index i)\n    {\n      EIGEN_STATIC_ASSERT((Options&RowMajor)==0,THIS_METHOD_IS_ONLY_FOR_COLUMN_MAJOR_MATRICES);\n      Index start = 0;\n      Index len = coeffs().rows();\n      if (i<=supers())\n      {\n        start = supers()-i;\n        len = (std::min)(rows(),std::max<Index>(0,coeffs().rows() - (supers()-i)));\n      }\n      else if (i>=rows()-subs())\n        len = std::max<Index>(0,coeffs().rows() - (i + 1 - rows() + subs()));\n      return Block<CoefficientsType,Dynamic,1>(coeffs(), start, i, len, 1);\n    }\n\n    /** \\returns a vector expression of the main diagonal */\n    inline Block<CoefficientsType,1,SizeAtCompileTime> diagonal()\n    { return Block<CoefficientsType,1,SizeAtCompileTime>(coeffs(),supers(),0,1,(std::min)(rows(),cols())); }\n\n    /** \\returns a vector expression of the main diagonal (const version) */\n    inline const Block<const CoefficientsType,1,SizeAtCompileTime> diagonal() const\n    { return Block<const CoefficientsType,1,SizeAtCompileTime>(coeffs(),supers(),0,1,(std::min)(rows(),cols())); }\n\n    template<int Index> struct DiagonalIntReturnType {\n      enum {\n        ReturnOpposite = (Options&SelfAdjoint) && (((Index)>0 && Supers==0) || ((Index)<0 && Subs==0)),\n        Conjugate = ReturnOpposite && NumTraits<Scalar>::IsComplex,\n        ActualIndex = ReturnOpposite ? -Index : Index,\n        DiagonalSize = (RowsAtCompileTime==Dynamic || ColsAtCompileTime==Dynamic)\n                     ? Dynamic\n                     : (ActualIndex<0\n                     ? EIGEN_SIZE_MIN_PREFER_DYNAMIC(ColsAtCompileTime, RowsAtCompileTime + ActualIndex)\n                     : EIGEN_SIZE_MIN_PREFER_DYNAMIC(RowsAtCompileTime, ColsAtCompileTime - ActualIndex))\n      };\n      typedef Block<CoefficientsType,1, DiagonalSize> BuildType;\n      typedef typename internal::conditional<Conjugate,\n                 CwiseUnaryOp<internal::scalar_conjugate_op<Scalar>,BuildType >,\n                 BuildType>::type Type;\n    };\n\n    /** \\returns a vector expression of the \\a N -th sub or super diagonal */\n    template<int N> inline typename DiagonalIntReturnType<N>::Type diagonal()\n    {\n      return typename DiagonalIntReturnType<N>::BuildType(coeffs(), supers()-N, (std::max)(0,N), 1, diagonalLength(N));\n    }\n\n    /** \\returns a vector expression of the \\a N -th sub or super diagonal */\n    template<int N> inline const typename DiagonalIntReturnType<N>::Type diagonal() const\n    {\n      return typename DiagonalIntReturnType<N>::BuildType(coeffs(), supers()-N, (std::max)(0,N), 1, diagonalLength(N));\n    }\n\n    /** \\returns a vector expression of the \\a i -th sub or super diagonal */\n    inline Block<CoefficientsType,1,Dynamic> diagonal(Index i)\n    {\n      eigen_assert((i<0 && -i<=subs()) || (i>=0 && i<=supers()));\n      return Block<CoefficientsType,1,Dynamic>(coeffs(), supers()-i, std::max<Index>(0,i), 1, diagonalLength(i));\n    }\n\n    /** \\returns a vector expression of the \\a i -th sub or super diagonal */\n    inline const Block<const CoefficientsType,1,Dynamic> diagonal(Index i) const\n    {\n      eigen_assert((i<0 && -i<=subs()) || (i>=0 && i<=supers()));\n      return Block<const CoefficientsType,1,Dynamic>(coeffs(), supers()-i, std::max<Index>(0,i), 1, diagonalLength(i));\n    }\n    \n    template<typename Dest> inline void evalTo(Dest& dst) const\n    {\n      dst.resize(rows(),cols());\n      dst.setZero();\n      dst.diagonal() = diagonal();\n      for (Index i=1; i<=supers();++i)\n        dst.diagonal(i) = diagonal(i);\n      for (Index i=1; i<=subs();++i)\n        dst.diagonal(-i) = diagonal(-i);\n    }\n\n    DenseMatrixType toDenseMatrix() const\n    {\n      DenseMatrixType res(rows(),cols());\n      evalTo(res);\n      return res;\n    }\n\n  protected:\n\n    inline Index diagonalLength(Index i) const\n    { return i<0 ? (std::min)(cols(),rows()+i) : (std::min)(rows(),cols()-i); }\n};\n\n/**\n  * \\class BandMatrix\n  * \\ingroup Core_Module\n  *\n  * \\brief Represents a rectangular matrix with a banded storage\n  *\n  * \\tparam _Scalar Numeric type, i.e. float, double, int\n  * \\tparam _Rows Number of rows, or \\b Dynamic\n  * \\tparam _Cols Number of columns, or \\b Dynamic\n  * \\tparam _Supers Number of super diagonal\n  * \\tparam _Subs Number of sub diagonal\n  * \\tparam _Options A combination of either \\b #RowMajor or \\b #ColMajor, and of \\b #SelfAdjoint\n  *                  The former controls \\ref TopicStorageOrders \"storage order\", and defaults to\n  *                  column-major. The latter controls whether the matrix represents a selfadjoint\n  *                  matrix in which case either Supers of Subs have to be null.\n  *\n  * \\sa class TridiagonalMatrix\n  */\n\ntemplate<typename _Scalar, int _Rows, int _Cols, int _Supers, int _Subs, int _Options>\nstruct traits<BandMatrix<_Scalar,_Rows,_Cols,_Supers,_Subs,_Options> >\n{\n  typedef _Scalar Scalar;\n  typedef Dense StorageKind;\n  typedef Eigen::Index StorageIndex;\n  enum {\n    CoeffReadCost = NumTraits<Scalar>::ReadCost,\n    RowsAtCompileTime = _Rows,\n    ColsAtCompileTime = _Cols,\n    MaxRowsAtCompileTime = _Rows,\n    MaxColsAtCompileTime = _Cols,\n    Flags = LvalueBit,\n    Supers = _Supers,\n    Subs = _Subs,\n    Options = _Options,\n    DataRowsAtCompileTime = ((Supers!=Dynamic) && (Subs!=Dynamic)) ? 1 + Supers + Subs : Dynamic\n  };\n  typedef Matrix<Scalar,DataRowsAtCompileTime,ColsAtCompileTime,Options&RowMajor?RowMajor:ColMajor> CoefficientsType;\n};\n\ntemplate<typename _Scalar, int Rows, int Cols, int Supers, int Subs, int Options>\nclass BandMatrix : public BandMatrixBase<BandMatrix<_Scalar,Rows,Cols,Supers,Subs,Options> >\n{\n  public:\n\n    typedef typename internal::traits<BandMatrix>::Scalar Scalar;\n    typedef typename internal::traits<BandMatrix>::StorageIndex StorageIndex;\n    typedef typename internal::traits<BandMatrix>::CoefficientsType CoefficientsType;\n\n    explicit inline BandMatrix(Index rows=Rows, Index cols=Cols, Index supers=Supers, Index subs=Subs)\n      : m_coeffs(1+supers+subs,cols),\n        m_rows(rows), m_supers(supers), m_subs(subs)\n    {\n    }\n\n    /** \\returns the number of columns */\n    inline Index rows() const { return m_rows.value(); }\n\n    /** \\returns the number of rows */\n    inline Index cols() const { return m_coeffs.cols(); }\n\n    /** \\returns the number of super diagonals */\n    inline Index supers() const { return m_supers.value(); }\n\n    /** \\returns the number of sub diagonals */\n    inline Index subs() const { return m_subs.value(); }\n\n    inline const CoefficientsType& coeffs() const { return m_coeffs; }\n    inline CoefficientsType& coeffs() { return m_coeffs; }\n\n  protected:\n\n    CoefficientsType m_coeffs;\n    internal::variable_if_dynamic<Index, Rows>   m_rows;\n    internal::variable_if_dynamic<Index, Supers> m_supers;\n    internal::variable_if_dynamic<Index, Subs>   m_subs;\n};\n\ntemplate<typename _CoefficientsType,int _Rows, int _Cols, int _Supers, int _Subs,int _Options>\nclass BandMatrixWrapper;\n\ntemplate<typename _CoefficientsType,int _Rows, int _Cols, int _Supers, int _Subs,int _Options>\nstruct traits<BandMatrixWrapper<_CoefficientsType,_Rows,_Cols,_Supers,_Subs,_Options> >\n{\n  typedef typename _CoefficientsType::Scalar Scalar;\n  typedef typename _CoefficientsType::StorageKind StorageKind;\n  typedef typename _CoefficientsType::StorageIndex StorageIndex;\n  enum {\n    CoeffReadCost = internal::traits<_CoefficientsType>::CoeffReadCost,\n    RowsAtCompileTime = _Rows,\n    ColsAtCompileTime = _Cols,\n    MaxRowsAtCompileTime = _Rows,\n    MaxColsAtCompileTime = _Cols,\n    Flags = LvalueBit,\n    Supers = _Supers,\n    Subs = _Subs,\n    Options = _Options,\n    DataRowsAtCompileTime = ((Supers!=Dynamic) && (Subs!=Dynamic)) ? 1 + Supers + Subs : Dynamic\n  };\n  typedef _CoefficientsType CoefficientsType;\n};\n\ntemplate<typename _CoefficientsType,int _Rows, int _Cols, int _Supers, int _Subs,int _Options>\nclass BandMatrixWrapper : public BandMatrixBase<BandMatrixWrapper<_CoefficientsType,_Rows,_Cols,_Supers,_Subs,_Options> >\n{\n  public:\n\n    typedef typename internal::traits<BandMatrixWrapper>::Scalar Scalar;\n    typedef typename internal::traits<BandMatrixWrapper>::CoefficientsType CoefficientsType;\n    typedef typename internal::traits<BandMatrixWrapper>::StorageIndex StorageIndex;\n\n    explicit inline BandMatrixWrapper(const CoefficientsType& coeffs, Index rows=_Rows, Index cols=_Cols, Index supers=_Supers, Index subs=_Subs)\n      : m_coeffs(coeffs),\n        m_rows(rows), m_supers(supers), m_subs(subs)\n    {\n      EIGEN_UNUSED_VARIABLE(cols);\n      //internal::assert(coeffs.cols()==cols() && (supers()+subs()+1)==coeffs.rows());\n    }\n\n    /** \\returns the number of columns */\n    inline Index rows() const { return m_rows.value(); }\n\n    /** \\returns the number of rows */\n    inline Index cols() const { return m_coeffs.cols(); }\n\n    /** \\returns the number of super diagonals */\n    inline Index supers() const { return m_supers.value(); }\n\n    /** \\returns the number of sub diagonals */\n    inline Index subs() const { return m_subs.value(); }\n\n    inline const CoefficientsType& coeffs() const { return m_coeffs; }\n\n  protected:\n\n    const CoefficientsType& m_coeffs;\n    internal::variable_if_dynamic<Index, _Rows>   m_rows;\n    internal::variable_if_dynamic<Index, _Supers> m_supers;\n    internal::variable_if_dynamic<Index, _Subs>   m_subs;\n};\n\n/**\n  * \\class TridiagonalMatrix\n  * \\ingroup Core_Module\n  *\n  * \\brief Represents a tridiagonal matrix with a compact banded storage\n  *\n  * \\tparam Scalar Numeric type, i.e. float, double, int\n  * \\tparam Size Number of rows and cols, or \\b Dynamic\n  * \\tparam Options Can be 0 or \\b SelfAdjoint\n  *\n  * \\sa class BandMatrix\n  */\ntemplate<typename Scalar, int Size, int Options>\nclass TridiagonalMatrix : public BandMatrix<Scalar,Size,Size,Options&SelfAdjoint?0:1,1,Options|RowMajor>\n{\n    typedef BandMatrix<Scalar,Size,Size,Options&SelfAdjoint?0:1,1,Options|RowMajor> Base;\n    typedef typename Base::StorageIndex StorageIndex;\n  public:\n    explicit TridiagonalMatrix(Index size = Size) : Base(size,size,Options&SelfAdjoint?0:1,1) {}\n\n    inline typename Base::template DiagonalIntReturnType<1>::Type super()\n    { return Base::template diagonal<1>(); }\n    inline const typename Base::template DiagonalIntReturnType<1>::Type super() const\n    { return Base::template diagonal<1>(); }\n    inline typename Base::template DiagonalIntReturnType<-1>::Type sub()\n    { return Base::template diagonal<-1>(); }\n    inline const typename Base::template DiagonalIntReturnType<-1>::Type sub() const\n    { return Base::template diagonal<-1>(); }\n  protected:\n};\n\n\nstruct BandShape {};\n\ntemplate<typename _Scalar, int _Rows, int _Cols, int _Supers, int _Subs, int _Options>\nstruct evaluator_traits<BandMatrix<_Scalar,_Rows,_Cols,_Supers,_Subs,_Options> >\n  : public evaluator_traits_base<BandMatrix<_Scalar,_Rows,_Cols,_Supers,_Subs,_Options> >\n{\n  typedef BandShape Shape;\n};\n\ntemplate<typename _CoefficientsType,int _Rows, int _Cols, int _Supers, int _Subs,int _Options>\nstruct evaluator_traits<BandMatrixWrapper<_CoefficientsType,_Rows,_Cols,_Supers,_Subs,_Options> >\n  : public evaluator_traits_base<BandMatrixWrapper<_CoefficientsType,_Rows,_Cols,_Supers,_Subs,_Options> >\n{\n  typedef BandShape Shape;\n};\n\ntemplate<> struct AssignmentKind<DenseShape,BandShape> { typedef EigenBase2EigenBase Kind; };\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_BANDMATRIX_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/Block.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2006-2010 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_BLOCK_H\n#define EIGEN_BLOCK_H\n\nnamespace Eigen { \n\nnamespace internal {\ntemplate<typename XprType, int BlockRows, int BlockCols, bool InnerPanel>\nstruct traits<Block<XprType, BlockRows, BlockCols, InnerPanel> > : traits<XprType>\n{\n  typedef typename traits<XprType>::Scalar Scalar;\n  typedef typename traits<XprType>::StorageKind StorageKind;\n  typedef typename traits<XprType>::XprKind XprKind;\n  typedef typename ref_selector<XprType>::type XprTypeNested;\n  typedef typename remove_reference<XprTypeNested>::type _XprTypeNested;\n  enum{\n    MatrixRows = traits<XprType>::RowsAtCompileTime,\n    MatrixCols = traits<XprType>::ColsAtCompileTime,\n    RowsAtCompileTime = MatrixRows == 0 ? 0 : BlockRows,\n    ColsAtCompileTime = MatrixCols == 0 ? 0 : BlockCols,\n    MaxRowsAtCompileTime = BlockRows==0 ? 0\n                         : RowsAtCompileTime != Dynamic ? int(RowsAtCompileTime)\n                         : int(traits<XprType>::MaxRowsAtCompileTime),\n    MaxColsAtCompileTime = BlockCols==0 ? 0\n                         : ColsAtCompileTime != Dynamic ? int(ColsAtCompileTime)\n                         : int(traits<XprType>::MaxColsAtCompileTime),\n\n    XprTypeIsRowMajor = (int(traits<XprType>::Flags)&RowMajorBit) != 0,\n    IsRowMajor = (MaxRowsAtCompileTime==1&&MaxColsAtCompileTime!=1) ? 1\n               : (MaxColsAtCompileTime==1&&MaxRowsAtCompileTime!=1) ? 0\n               : XprTypeIsRowMajor,\n    HasSameStorageOrderAsXprType = (IsRowMajor == XprTypeIsRowMajor),\n    InnerSize = IsRowMajor ? int(ColsAtCompileTime) : int(RowsAtCompileTime),\n    InnerStrideAtCompileTime = HasSameStorageOrderAsXprType\n                             ? int(inner_stride_at_compile_time<XprType>::ret)\n                             : int(outer_stride_at_compile_time<XprType>::ret),\n    OuterStrideAtCompileTime = HasSameStorageOrderAsXprType\n                             ? int(outer_stride_at_compile_time<XprType>::ret)\n                             : int(inner_stride_at_compile_time<XprType>::ret),\n\n    // FIXME, this traits is rather specialized for dense object and it needs to be cleaned further\n    FlagsLvalueBit = is_lvalue<XprType>::value ? LvalueBit : 0,\n    FlagsRowMajorBit = IsRowMajor ? RowMajorBit : 0,\n    Flags = (traits<XprType>::Flags & (DirectAccessBit | (InnerPanel?CompressedAccessBit:0))) | FlagsLvalueBit | FlagsRowMajorBit,\n    // FIXME DirectAccessBit should not be handled by expressions\n    // \n    // Alignment is needed by MapBase's assertions\n    // We can sefely set it to false here. Internal alignment errors will be detected by an eigen_internal_assert in the respective evaluator\n    Alignment = 0\n  };\n};\n\ntemplate<typename XprType, int BlockRows=Dynamic, int BlockCols=Dynamic, bool InnerPanel = false,\n         bool HasDirectAccess = internal::has_direct_access<XprType>::ret> class BlockImpl_dense;\n         \n} // end namespace internal\n\ntemplate<typename XprType, int BlockRows, int BlockCols, bool InnerPanel, typename StorageKind> class BlockImpl;\n\n/** \\class Block\n  * \\ingroup Core_Module\n  *\n  * \\brief Expression of a fixed-size or dynamic-size block\n  *\n  * \\tparam XprType the type of the expression in which we are taking a block\n  * \\tparam BlockRows the number of rows of the block we are taking at compile time (optional)\n  * \\tparam BlockCols the number of columns of the block we are taking at compile time (optional)\n  * \\tparam InnerPanel is true, if the block maps to a set of rows of a row major matrix or\n  *         to set of columns of a column major matrix (optional). The parameter allows to determine\n  *         at compile time whether aligned access is possible on the block expression.\n  *\n  * This class represents an expression of either a fixed-size or dynamic-size block. It is the return\n  * type of DenseBase::block(Index,Index,Index,Index) and DenseBase::block<int,int>(Index,Index) and\n  * most of the time this is the only way it is used.\n  *\n  * However, if you want to directly maniputate block expressions,\n  * for instance if you want to write a function returning such an expression, you\n  * will need to use this class.\n  *\n  * Here is an example illustrating the dynamic case:\n  * \\include class_Block.cpp\n  * Output: \\verbinclude class_Block.out\n  *\n  * \\note Even though this expression has dynamic size, in the case where \\a XprType\n  * has fixed size, this expression inherits a fixed maximal size which means that evaluating\n  * it does not cause a dynamic memory allocation.\n  *\n  * Here is an example illustrating the fixed-size case:\n  * \\include class_FixedBlock.cpp\n  * Output: \\verbinclude class_FixedBlock.out\n  *\n  * \\sa DenseBase::block(Index,Index,Index,Index), DenseBase::block(Index,Index), class VectorBlock\n  */\ntemplate<typename XprType, int BlockRows, int BlockCols, bool InnerPanel> class Block\n  : public BlockImpl<XprType, BlockRows, BlockCols, InnerPanel, typename internal::traits<XprType>::StorageKind>\n{\n    typedef BlockImpl<XprType, BlockRows, BlockCols, InnerPanel, typename internal::traits<XprType>::StorageKind> Impl;\n  public:\n    //typedef typename Impl::Base Base;\n    typedef Impl Base;\n    EIGEN_GENERIC_PUBLIC_INTERFACE(Block)\n    EIGEN_INHERIT_ASSIGNMENT_OPERATORS(Block)\n    \n    typedef typename internal::remove_all<XprType>::type NestedExpression;\n  \n    /** Column or Row constructor\n      */\n    EIGEN_DEVICE_FUNC\n    inline Block(XprType& xpr, Index i) : Impl(xpr,i)\n    {\n      eigen_assert( (i>=0) && (\n          ((BlockRows==1) && (BlockCols==XprType::ColsAtCompileTime) && i<xpr.rows())\n        ||((BlockRows==XprType::RowsAtCompileTime) && (BlockCols==1) && i<xpr.cols())));\n    }\n\n    /** Fixed-size constructor\n      */\n    EIGEN_DEVICE_FUNC\n    inline Block(XprType& xpr, Index startRow, Index startCol)\n      : Impl(xpr, startRow, startCol)\n    {\n      EIGEN_STATIC_ASSERT(RowsAtCompileTime!=Dynamic && ColsAtCompileTime!=Dynamic,THIS_METHOD_IS_ONLY_FOR_FIXED_SIZE)\n      eigen_assert(startRow >= 0 && BlockRows >= 0 && startRow + BlockRows <= xpr.rows()\n             && startCol >= 0 && BlockCols >= 0 && startCol + BlockCols <= xpr.cols());\n    }\n\n    /** Dynamic-size constructor\n      */\n    EIGEN_DEVICE_FUNC\n    inline Block(XprType& xpr,\n          Index startRow, Index startCol,\n          Index blockRows, Index blockCols)\n      : Impl(xpr, startRow, startCol, blockRows, blockCols)\n    {\n      eigen_assert((RowsAtCompileTime==Dynamic || RowsAtCompileTime==blockRows)\n          && (ColsAtCompileTime==Dynamic || ColsAtCompileTime==blockCols));\n      eigen_assert(startRow >= 0 && blockRows >= 0 && startRow  <= xpr.rows() - blockRows\n          && startCol >= 0 && blockCols >= 0 && startCol <= xpr.cols() - blockCols);\n    }\n};\n         \n// The generic default implementation for dense block simplu forward to the internal::BlockImpl_dense\n// that must be specialized for direct and non-direct access...\ntemplate<typename XprType, int BlockRows, int BlockCols, bool InnerPanel>\nclass BlockImpl<XprType, BlockRows, BlockCols, InnerPanel, Dense>\n  : public internal::BlockImpl_dense<XprType, BlockRows, BlockCols, InnerPanel>\n{\n    typedef internal::BlockImpl_dense<XprType, BlockRows, BlockCols, InnerPanel> Impl;\n    typedef typename XprType::StorageIndex StorageIndex;\n  public:\n    typedef Impl Base;\n    EIGEN_INHERIT_ASSIGNMENT_OPERATORS(BlockImpl)\n    EIGEN_DEVICE_FUNC inline BlockImpl(XprType& xpr, Index i) : Impl(xpr,i) {}\n    EIGEN_DEVICE_FUNC inline BlockImpl(XprType& xpr, Index startRow, Index startCol) : Impl(xpr, startRow, startCol) {}\n    EIGEN_DEVICE_FUNC\n    inline BlockImpl(XprType& xpr, Index startRow, Index startCol, Index blockRows, Index blockCols)\n      : Impl(xpr, startRow, startCol, blockRows, blockCols) {}\n};\n\nnamespace internal {\n\n/** \\internal Internal implementation of dense Blocks in the general case. */\ntemplate<typename XprType, int BlockRows, int BlockCols, bool InnerPanel, bool HasDirectAccess> class BlockImpl_dense\n  : public internal::dense_xpr_base<Block<XprType, BlockRows, BlockCols, InnerPanel> >::type\n{\n    typedef Block<XprType, BlockRows, BlockCols, InnerPanel> BlockType;\n    typedef typename internal::ref_selector<XprType>::non_const_type XprTypeNested;\n  public:\n\n    typedef typename internal::dense_xpr_base<BlockType>::type Base;\n    EIGEN_DENSE_PUBLIC_INTERFACE(BlockType)\n    EIGEN_INHERIT_ASSIGNMENT_OPERATORS(BlockImpl_dense)\n\n    // class InnerIterator; // FIXME apparently never used\n\n    /** Column or Row constructor\n      */\n    EIGEN_DEVICE_FUNC\n    inline BlockImpl_dense(XprType& xpr, Index i)\n      : m_xpr(xpr),\n        // It is a row if and only if BlockRows==1 and BlockCols==XprType::ColsAtCompileTime,\n        // and it is a column if and only if BlockRows==XprType::RowsAtCompileTime and BlockCols==1,\n        // all other cases are invalid.\n        // The case a 1x1 matrix seems ambiguous, but the result is the same anyway.\n        m_startRow( (BlockRows==1) && (BlockCols==XprType::ColsAtCompileTime) ? i : 0),\n        m_startCol( (BlockRows==XprType::RowsAtCompileTime) && (BlockCols==1) ? i : 0),\n        m_blockRows(BlockRows==1 ? 1 : xpr.rows()),\n        m_blockCols(BlockCols==1 ? 1 : xpr.cols())\n    {}\n\n    /** Fixed-size constructor\n      */\n    EIGEN_DEVICE_FUNC\n    inline BlockImpl_dense(XprType& xpr, Index startRow, Index startCol)\n      : m_xpr(xpr), m_startRow(startRow), m_startCol(startCol),\n                    m_blockRows(BlockRows), m_blockCols(BlockCols)\n    {}\n\n    /** Dynamic-size constructor\n      */\n    EIGEN_DEVICE_FUNC\n    inline BlockImpl_dense(XprType& xpr,\n          Index startRow, Index startCol,\n          Index blockRows, Index blockCols)\n      : m_xpr(xpr), m_startRow(startRow), m_startCol(startCol),\n                    m_blockRows(blockRows), m_blockCols(blockCols)\n    {}\n\n    EIGEN_DEVICE_FUNC inline Index rows() const { return m_blockRows.value(); }\n    EIGEN_DEVICE_FUNC inline Index cols() const { return m_blockCols.value(); }\n\n    EIGEN_DEVICE_FUNC\n    inline Scalar& coeffRef(Index rowId, Index colId)\n    {\n      EIGEN_STATIC_ASSERT_LVALUE(XprType)\n      return m_xpr.coeffRef(rowId + m_startRow.value(), colId + m_startCol.value());\n    }\n\n    EIGEN_DEVICE_FUNC\n    inline const Scalar& coeffRef(Index rowId, Index colId) const\n    {\n      return m_xpr.derived().coeffRef(rowId + m_startRow.value(), colId + m_startCol.value());\n    }\n\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE const CoeffReturnType coeff(Index rowId, Index colId) const\n    {\n      return m_xpr.coeff(rowId + m_startRow.value(), colId + m_startCol.value());\n    }\n\n    EIGEN_DEVICE_FUNC\n    inline Scalar& coeffRef(Index index)\n    {\n      EIGEN_STATIC_ASSERT_LVALUE(XprType)\n      return m_xpr.coeffRef(m_startRow.value() + (RowsAtCompileTime == 1 ? 0 : index),\n                            m_startCol.value() + (RowsAtCompileTime == 1 ? index : 0));\n    }\n\n    EIGEN_DEVICE_FUNC\n    inline const Scalar& coeffRef(Index index) const\n    {\n      return m_xpr.coeffRef(m_startRow.value() + (RowsAtCompileTime == 1 ? 0 : index),\n                            m_startCol.value() + (RowsAtCompileTime == 1 ? index : 0));\n    }\n\n    EIGEN_DEVICE_FUNC\n    inline const CoeffReturnType coeff(Index index) const\n    {\n      return m_xpr.coeff(m_startRow.value() + (RowsAtCompileTime == 1 ? 0 : index),\n                         m_startCol.value() + (RowsAtCompileTime == 1 ? index : 0));\n    }\n\n    template<int LoadMode>\n    inline PacketScalar packet(Index rowId, Index colId) const\n    {\n      return m_xpr.template packet<Unaligned>(rowId + m_startRow.value(), colId + m_startCol.value());\n    }\n\n    template<int LoadMode>\n    inline void writePacket(Index rowId, Index colId, const PacketScalar& val)\n    {\n      m_xpr.template writePacket<Unaligned>(rowId + m_startRow.value(), colId + m_startCol.value(), val);\n    }\n\n    template<int LoadMode>\n    inline PacketScalar packet(Index index) const\n    {\n      return m_xpr.template packet<Unaligned>\n              (m_startRow.value() + (RowsAtCompileTime == 1 ? 0 : index),\n               m_startCol.value() + (RowsAtCompileTime == 1 ? index : 0));\n    }\n\n    template<int LoadMode>\n    inline void writePacket(Index index, const PacketScalar& val)\n    {\n      m_xpr.template writePacket<Unaligned>\n         (m_startRow.value() + (RowsAtCompileTime == 1 ? 0 : index),\n          m_startCol.value() + (RowsAtCompileTime == 1 ? index : 0), val);\n    }\n\n    #ifdef EIGEN_PARSED_BY_DOXYGEN\n    /** \\sa MapBase::data() */\n    EIGEN_DEVICE_FUNC inline const Scalar* data() const;\n    EIGEN_DEVICE_FUNC inline Index innerStride() const;\n    EIGEN_DEVICE_FUNC inline Index outerStride() const;\n    #endif\n\n    EIGEN_DEVICE_FUNC\n    const typename internal::remove_all<XprTypeNested>::type& nestedExpression() const\n    { \n      return m_xpr; \n    }\n\n    EIGEN_DEVICE_FUNC\n    XprType& nestedExpression() { return m_xpr; }\n      \n    EIGEN_DEVICE_FUNC\n    StorageIndex startRow() const\n    { \n      return m_startRow.value(); \n    }\n      \n    EIGEN_DEVICE_FUNC\n    StorageIndex startCol() const\n    { \n      return m_startCol.value(); \n    }\n\n  protected:\n\n    XprTypeNested m_xpr;\n    const internal::variable_if_dynamic<StorageIndex, (XprType::RowsAtCompileTime == 1 && BlockRows==1) ? 0 : Dynamic> m_startRow;\n    const internal::variable_if_dynamic<StorageIndex, (XprType::ColsAtCompileTime == 1 && BlockCols==1) ? 0 : Dynamic> m_startCol;\n    const internal::variable_if_dynamic<StorageIndex, RowsAtCompileTime> m_blockRows;\n    const internal::variable_if_dynamic<StorageIndex, ColsAtCompileTime> m_blockCols;\n};\n\n/** \\internal Internal implementation of dense Blocks in the direct access case.*/\ntemplate<typename XprType, int BlockRows, int BlockCols, bool InnerPanel>\nclass BlockImpl_dense<XprType,BlockRows,BlockCols, InnerPanel,true>\n  : public MapBase<Block<XprType, BlockRows, BlockCols, InnerPanel> >\n{\n    typedef Block<XprType, BlockRows, BlockCols, InnerPanel> BlockType;\n    typedef typename internal::ref_selector<XprType>::non_const_type XprTypeNested;\n    enum {\n      XprTypeIsRowMajor = (int(traits<XprType>::Flags)&RowMajorBit) != 0\n    };\n  public:\n\n    typedef MapBase<BlockType> Base;\n    EIGEN_DENSE_PUBLIC_INTERFACE(BlockType)\n    EIGEN_INHERIT_ASSIGNMENT_OPERATORS(BlockImpl_dense)\n\n    /** Column or Row constructor\n      */\n    EIGEN_DEVICE_FUNC\n    inline BlockImpl_dense(XprType& xpr, Index i)\n      : Base(xpr.data() + i * (    ((BlockRows==1) && (BlockCols==XprType::ColsAtCompileTime) && (!XprTypeIsRowMajor)) \n                                || ((BlockRows==XprType::RowsAtCompileTime) && (BlockCols==1) && ( XprTypeIsRowMajor)) ? xpr.innerStride() : xpr.outerStride()),\n             BlockRows==1 ? 1 : xpr.rows(),\n             BlockCols==1 ? 1 : xpr.cols()),\n        m_xpr(xpr),\n        m_startRow( (BlockRows==1) && (BlockCols==XprType::ColsAtCompileTime) ? i : 0),\n        m_startCol( (BlockRows==XprType::RowsAtCompileTime) && (BlockCols==1) ? i : 0)\n    {\n      init();\n    }\n\n    /** Fixed-size constructor\n      */\n    EIGEN_DEVICE_FUNC\n    inline BlockImpl_dense(XprType& xpr, Index startRow, Index startCol)\n      : Base(xpr.data()+xpr.innerStride()*(XprTypeIsRowMajor?startCol:startRow) + xpr.outerStride()*(XprTypeIsRowMajor?startRow:startCol)),\n        m_xpr(xpr), m_startRow(startRow), m_startCol(startCol)\n    {\n      init();\n    }\n\n    /** Dynamic-size constructor\n      */\n    EIGEN_DEVICE_FUNC\n    inline BlockImpl_dense(XprType& xpr,\n          Index startRow, Index startCol,\n          Index blockRows, Index blockCols)\n      : Base(xpr.data()+xpr.innerStride()*(XprTypeIsRowMajor?startCol:startRow) + xpr.outerStride()*(XprTypeIsRowMajor?startRow:startCol), blockRows, blockCols),\n        m_xpr(xpr), m_startRow(startRow), m_startCol(startCol)\n    {\n      init();\n    }\n\n    EIGEN_DEVICE_FUNC\n    const typename internal::remove_all<XprTypeNested>::type& nestedExpression() const\n    { \n      return m_xpr; \n    }\n\n    EIGEN_DEVICE_FUNC\n    XprType& nestedExpression() { return m_xpr; }\n      \n    /** \\sa MapBase::innerStride() */\n    EIGEN_DEVICE_FUNC\n    inline Index innerStride() const\n    {\n      return internal::traits<BlockType>::HasSameStorageOrderAsXprType\n             ? m_xpr.innerStride()\n             : m_xpr.outerStride();\n    }\n\n    /** \\sa MapBase::outerStride() */\n    EIGEN_DEVICE_FUNC\n    inline Index outerStride() const\n    {\n      return m_outerStride;\n    }\n\n    EIGEN_DEVICE_FUNC\n    StorageIndex startRow() const\n    {\n      return m_startRow.value();\n    }\n\n    EIGEN_DEVICE_FUNC\n    StorageIndex startCol() const\n    {\n      return m_startCol.value();\n    }\n\n  #ifndef __SUNPRO_CC\n  // FIXME sunstudio is not friendly with the above friend...\n  // META-FIXME there is no 'friend' keyword around here. Is this obsolete?\n  protected:\n  #endif\n\n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    /** \\internal used by allowAligned() */\n    EIGEN_DEVICE_FUNC\n    inline BlockImpl_dense(XprType& xpr, const Scalar* data, Index blockRows, Index blockCols)\n      : Base(data, blockRows, blockCols), m_xpr(xpr)\n    {\n      init();\n    }\n    #endif\n\n  protected:\n    EIGEN_DEVICE_FUNC\n    void init()\n    {\n      m_outerStride = internal::traits<BlockType>::HasSameStorageOrderAsXprType\n                    ? m_xpr.outerStride()\n                    : m_xpr.innerStride();\n    }\n\n    XprTypeNested m_xpr;\n    const internal::variable_if_dynamic<StorageIndex, (XprType::RowsAtCompileTime == 1 && BlockRows==1) ? 0 : Dynamic> m_startRow;\n    const internal::variable_if_dynamic<StorageIndex, (XprType::ColsAtCompileTime == 1 && BlockCols==1) ? 0 : Dynamic> m_startCol;\n    Index m_outerStride;\n};\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_BLOCK_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/BooleanRedux.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_ALLANDANY_H\n#define EIGEN_ALLANDANY_H\n\nnamespace Eigen { \n\nnamespace internal {\n\ntemplate<typename Derived, int UnrollCount>\nstruct all_unroller\n{\n  typedef typename Derived::ExpressionTraits Traits;\n  enum {\n    col = (UnrollCount-1) / Traits::RowsAtCompileTime,\n    row = (UnrollCount-1) % Traits::RowsAtCompileTime\n  };\n\n  static inline bool run(const Derived &mat)\n  {\n    return all_unroller<Derived, UnrollCount-1>::run(mat) && mat.coeff(row, col);\n  }\n};\n\ntemplate<typename Derived>\nstruct all_unroller<Derived, 0>\n{\n  static inline bool run(const Derived &/*mat*/) { return true; }\n};\n\ntemplate<typename Derived>\nstruct all_unroller<Derived, Dynamic>\n{\n  static inline bool run(const Derived &) { return false; }\n};\n\ntemplate<typename Derived, int UnrollCount>\nstruct any_unroller\n{\n  typedef typename Derived::ExpressionTraits Traits;\n  enum {\n    col = (UnrollCount-1) / Traits::RowsAtCompileTime,\n    row = (UnrollCount-1) % Traits::RowsAtCompileTime\n  };\n  \n  static inline bool run(const Derived &mat)\n  {\n    return any_unroller<Derived, UnrollCount-1>::run(mat) || mat.coeff(row, col);\n  }\n};\n\ntemplate<typename Derived>\nstruct any_unroller<Derived, 0>\n{\n  static inline bool run(const Derived & /*mat*/) { return false; }\n};\n\ntemplate<typename Derived>\nstruct any_unroller<Derived, Dynamic>\n{\n  static inline bool run(const Derived &) { return false; }\n};\n\n} // end namespace internal\n\n/** \\returns true if all coefficients are true\n  *\n  * Example: \\include MatrixBase_all.cpp\n  * Output: \\verbinclude MatrixBase_all.out\n  *\n  * \\sa any(), Cwise::operator<()\n  */\ntemplate<typename Derived>\ninline bool DenseBase<Derived>::all() const\n{\n  typedef internal::evaluator<Derived> Evaluator;\n  enum {\n    unroll = SizeAtCompileTime != Dynamic\n          && SizeAtCompileTime * (Evaluator::CoeffReadCost + NumTraits<Scalar>::AddCost) <= EIGEN_UNROLLING_LIMIT\n  };\n  Evaluator evaluator(derived());\n  if(unroll)\n    return internal::all_unroller<Evaluator, unroll ? int(SizeAtCompileTime) : Dynamic>::run(evaluator);\n  else\n  {\n    for(Index j = 0; j < cols(); ++j)\n      for(Index i = 0; i < rows(); ++i)\n        if (!evaluator.coeff(i, j)) return false;\n    return true;\n  }\n}\n\n/** \\returns true if at least one coefficient is true\n  *\n  * \\sa all()\n  */\ntemplate<typename Derived>\ninline bool DenseBase<Derived>::any() const\n{\n  typedef internal::evaluator<Derived> Evaluator;\n  enum {\n    unroll = SizeAtCompileTime != Dynamic\n          && SizeAtCompileTime * (Evaluator::CoeffReadCost + NumTraits<Scalar>::AddCost) <= EIGEN_UNROLLING_LIMIT\n  };\n  Evaluator evaluator(derived());\n  if(unroll)\n    return internal::any_unroller<Evaluator, unroll ? int(SizeAtCompileTime) : Dynamic>::run(evaluator);\n  else\n  {\n    for(Index j = 0; j < cols(); ++j)\n      for(Index i = 0; i < rows(); ++i)\n        if (evaluator.coeff(i, j)) return true;\n    return false;\n  }\n}\n\n/** \\returns the number of coefficients which evaluate to true\n  *\n  * \\sa all(), any()\n  */\ntemplate<typename Derived>\ninline Eigen::Index DenseBase<Derived>::count() const\n{\n  return derived().template cast<bool>().template cast<Index>().sum();\n}\n\n/** \\returns true is \\c *this contains at least one Not A Number (NaN).\n  *\n  * \\sa allFinite()\n  */\ntemplate<typename Derived>\ninline bool DenseBase<Derived>::hasNaN() const\n{\n#if EIGEN_COMP_MSVC || (defined __FAST_MATH__)\n  return derived().array().isNaN().any();\n#else\n  return !((derived().array()==derived().array()).all());\n#endif\n}\n\n/** \\returns true if \\c *this contains only finite numbers, i.e., no NaN and no +/-INF values.\n  *\n  * \\sa hasNaN()\n  */\ntemplate<typename Derived>\ninline bool DenseBase<Derived>::allFinite() const\n{\n#if EIGEN_COMP_MSVC || (defined __FAST_MATH__)\n  return derived().array().isFinite().all();\n#else\n  return !((derived()-derived()).hasNaN());\n#endif\n}\n    \n} // end namespace Eigen\n\n#endif // EIGEN_ALLANDANY_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/CommaInitializer.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2006-2008 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_COMMAINITIALIZER_H\n#define EIGEN_COMMAINITIALIZER_H\n\nnamespace Eigen { \n\n/** \\class CommaInitializer\n  * \\ingroup Core_Module\n  *\n  * \\brief Helper class used by the comma initializer operator\n  *\n  * This class is internally used to implement the comma initializer feature. It is\n  * the return type of MatrixBase::operator<<, and most of the time this is the only\n  * way it is used.\n  *\n  * \\sa \\blank \\ref MatrixBaseCommaInitRef \"MatrixBase::operator<<\", CommaInitializer::finished()\n  */\ntemplate<typename XprType>\nstruct CommaInitializer\n{\n  typedef typename XprType::Scalar Scalar;\n\n  EIGEN_DEVICE_FUNC\n  inline CommaInitializer(XprType& xpr, const Scalar& s)\n    : m_xpr(xpr), m_row(0), m_col(1), m_currentBlockRows(1)\n  {\n    m_xpr.coeffRef(0,0) = s;\n  }\n\n  template<typename OtherDerived>\n  EIGEN_DEVICE_FUNC\n  inline CommaInitializer(XprType& xpr, const DenseBase<OtherDerived>& other)\n    : m_xpr(xpr), m_row(0), m_col(other.cols()), m_currentBlockRows(other.rows())\n  {\n    m_xpr.block(0, 0, other.rows(), other.cols()) = other;\n  }\n\n  /* Copy/Move constructor which transfers ownership. This is crucial in \n   * absence of return value optimization to avoid assertions during destruction. */\n  // FIXME in C++11 mode this could be replaced by a proper RValue constructor\n  EIGEN_DEVICE_FUNC\n  inline CommaInitializer(const CommaInitializer& o)\n  : m_xpr(o.m_xpr), m_row(o.m_row), m_col(o.m_col), m_currentBlockRows(o.m_currentBlockRows) {\n    // Mark original object as finished. In absence of R-value references we need to const_cast:\n    const_cast<CommaInitializer&>(o).m_row = m_xpr.rows();\n    const_cast<CommaInitializer&>(o).m_col = m_xpr.cols();\n    const_cast<CommaInitializer&>(o).m_currentBlockRows = 0;\n  }\n\n  /* inserts a scalar value in the target matrix */\n  EIGEN_DEVICE_FUNC\n  CommaInitializer& operator,(const Scalar& s)\n  {\n    if (m_col==m_xpr.cols())\n    {\n      m_row+=m_currentBlockRows;\n      m_col = 0;\n      m_currentBlockRows = 1;\n      eigen_assert(m_row<m_xpr.rows()\n        && \"Too many rows passed to comma initializer (operator<<)\");\n    }\n    eigen_assert(m_col<m_xpr.cols()\n      && \"Too many coefficients passed to comma initializer (operator<<)\");\n    eigen_assert(m_currentBlockRows==1);\n    m_xpr.coeffRef(m_row, m_col++) = s;\n    return *this;\n  }\n\n  /* inserts a matrix expression in the target matrix */\n  template<typename OtherDerived>\n  EIGEN_DEVICE_FUNC\n  CommaInitializer& operator,(const DenseBase<OtherDerived>& other)\n  {\n    if (m_col==m_xpr.cols() && (other.cols()!=0 || other.rows()!=m_currentBlockRows))\n    {\n      m_row+=m_currentBlockRows;\n      m_col = 0;\n      m_currentBlockRows = other.rows();\n      eigen_assert(m_row+m_currentBlockRows<=m_xpr.rows()\n        && \"Too many rows passed to comma initializer (operator<<)\");\n    }\n    eigen_assert((m_col + other.cols() <= m_xpr.cols())\n      && \"Too many coefficients passed to comma initializer (operator<<)\");\n    eigen_assert(m_currentBlockRows==other.rows());\n    m_xpr.template block<OtherDerived::RowsAtCompileTime, OtherDerived::ColsAtCompileTime>\n                    (m_row, m_col, other.rows(), other.cols()) = other;\n    m_col += other.cols();\n    return *this;\n  }\n\n  EIGEN_DEVICE_FUNC\n  inline ~CommaInitializer()\n#if defined VERIFY_RAISES_ASSERT && (!defined EIGEN_NO_ASSERTION_CHECKING) && defined EIGEN_EXCEPTIONS\n  EIGEN_EXCEPTION_SPEC(Eigen::eigen_assert_exception)\n#endif\n  {\n      finished();\n  }\n\n  /** \\returns the built matrix once all its coefficients have been set.\n    * Calling finished is 100% optional. Its purpose is to write expressions\n    * like this:\n    * \\code\n    * quaternion.fromRotationMatrix((Matrix3f() << axis0, axis1, axis2).finished());\n    * \\endcode\n    */\n  EIGEN_DEVICE_FUNC\n  inline XprType& finished() {\n      eigen_assert(((m_row+m_currentBlockRows) == m_xpr.rows() || m_xpr.cols() == 0)\n           && m_col == m_xpr.cols()\n           && \"Too few coefficients passed to comma initializer (operator<<)\");\n      return m_xpr;\n  }\n\n  XprType& m_xpr;           // target expression\n  Index m_row;              // current row id\n  Index m_col;              // current col id\n  Index m_currentBlockRows; // current block height\n};\n\n/** \\anchor MatrixBaseCommaInitRef\n  * Convenient operator to set the coefficients of a matrix.\n  *\n  * The coefficients must be provided in a row major order and exactly match\n  * the size of the matrix. Otherwise an assertion is raised.\n  *\n  * Example: \\include MatrixBase_set.cpp\n  * Output: \\verbinclude MatrixBase_set.out\n  * \n  * \\note According the c++ standard, the argument expressions of this comma initializer are evaluated in arbitrary order.\n  *\n  * \\sa CommaInitializer::finished(), class CommaInitializer\n  */\ntemplate<typename Derived>\ninline CommaInitializer<Derived> DenseBase<Derived>::operator<< (const Scalar& s)\n{\n  return CommaInitializer<Derived>(*static_cast<Derived*>(this), s);\n}\n\n/** \\sa operator<<(const Scalar&) */\ntemplate<typename Derived>\ntemplate<typename OtherDerived>\ninline CommaInitializer<Derived>\nDenseBase<Derived>::operator<<(const DenseBase<OtherDerived>& other)\n{\n  return CommaInitializer<Derived>(*static_cast<Derived *>(this), other);\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_COMMAINITIALIZER_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/ConditionEstimator.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2016 Rasmus Munk Larsen (rmlarsen@google.com)\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_CONDITIONESTIMATOR_H\n#define EIGEN_CONDITIONESTIMATOR_H\n\nnamespace Eigen {\n\nnamespace internal {\n\ntemplate <typename Vector, typename RealVector, bool IsComplex>\nstruct rcond_compute_sign {\n  static inline Vector run(const Vector& v) {\n    const RealVector v_abs = v.cwiseAbs();\n    return (v_abs.array() == static_cast<typename Vector::RealScalar>(0))\n            .select(Vector::Ones(v.size()), v.cwiseQuotient(v_abs));\n  }\n};\n\n// Partial specialization to avoid elementwise division for real vectors.\ntemplate <typename Vector>\nstruct rcond_compute_sign<Vector, Vector, false> {\n  static inline Vector run(const Vector& v) {\n    return (v.array() < static_cast<typename Vector::RealScalar>(0))\n           .select(-Vector::Ones(v.size()), Vector::Ones(v.size()));\n  }\n};\n\n/**\n  * \\returns an estimate of ||inv(matrix)||_1 given a decomposition of\n  * \\a matrix that implements .solve() and .adjoint().solve() methods.\n  *\n  * This function implements Algorithms 4.1 and 5.1 from\n  *   http://www.maths.manchester.ac.uk/~higham/narep/narep135.pdf\n  * which also forms the basis for the condition number estimators in\n  * LAPACK. Since at most 10 calls to the solve method of dec are\n  * performed, the total cost is O(dims^2), as opposed to O(dims^3)\n  * needed to compute the inverse matrix explicitly.\n  *\n  * The most common usage is in estimating the condition number\n  * ||matrix||_1 * ||inv(matrix)||_1. The first term ||matrix||_1 can be\n  * computed directly in O(n^2) operations.\n  *\n  * Supports the following decompositions: FullPivLU, PartialPivLU, LDLT, and\n  * LLT.\n  *\n  * \\sa FullPivLU, PartialPivLU, LDLT, LLT.\n  */\ntemplate <typename Decomposition>\ntypename Decomposition::RealScalar rcond_invmatrix_L1_norm_estimate(const Decomposition& dec)\n{\n  typedef typename Decomposition::MatrixType MatrixType;\n  typedef typename Decomposition::Scalar Scalar;\n  typedef typename Decomposition::RealScalar RealScalar;\n  typedef typename internal::plain_col_type<MatrixType>::type Vector;\n  typedef typename internal::plain_col_type<MatrixType, RealScalar>::type RealVector;\n  const bool is_complex = (NumTraits<Scalar>::IsComplex != 0);\n\n  eigen_assert(dec.rows() == dec.cols());\n  const Index n = dec.rows();\n  if (n == 0)\n    return 0;\n\n  // Disable Index to float conversion warning\n#ifdef __INTEL_COMPILER\n  #pragma warning push\n  #pragma warning ( disable : 2259 )\n#endif\n  Vector v = dec.solve(Vector::Ones(n) / Scalar(n));\n#ifdef __INTEL_COMPILER\n  #pragma warning pop\n#endif\n\n  // lower_bound is a lower bound on\n  //   ||inv(matrix)||_1  = sup_v ||inv(matrix) v||_1 / ||v||_1\n  // and is the objective maximized by the (\"super-\") gradient ascent\n  // algorithm below.\n  RealScalar lower_bound = v.template lpNorm<1>();\n  if (n == 1)\n    return lower_bound;\n\n  // Gradient ascent algorithm follows: We know that the optimum is achieved at\n  // one of the simplices v = e_i, so in each iteration we follow a\n  // super-gradient to move towards the optimal one.\n  RealScalar old_lower_bound = lower_bound;\n  Vector sign_vector(n);\n  Vector old_sign_vector;\n  Index v_max_abs_index = -1;\n  Index old_v_max_abs_index = v_max_abs_index;\n  for (int k = 0; k < 4; ++k)\n  {\n    sign_vector = internal::rcond_compute_sign<Vector, RealVector, is_complex>::run(v);\n    if (k > 0 && !is_complex && sign_vector == old_sign_vector) {\n      // Break if the solution stagnated.\n      break;\n    }\n    // v_max_abs_index = argmax |real( inv(matrix)^T * sign_vector )|\n    v = dec.adjoint().solve(sign_vector);\n    v.real().cwiseAbs().maxCoeff(&v_max_abs_index);\n    if (v_max_abs_index == old_v_max_abs_index) {\n      // Break if the solution stagnated.\n      break;\n    }\n    // Move to the new simplex e_j, where j = v_max_abs_index.\n    v = dec.solve(Vector::Unit(n, v_max_abs_index));  // v = inv(matrix) * e_j.\n    lower_bound = v.template lpNorm<1>();\n    if (lower_bound <= old_lower_bound) {\n      // Break if the gradient step did not increase the lower_bound.\n      break;\n    }\n    if (!is_complex) {\n      old_sign_vector = sign_vector;\n    }\n    old_v_max_abs_index = v_max_abs_index;\n    old_lower_bound = lower_bound;\n  }\n  // The following calculates an independent estimate of ||matrix||_1 by\n  // multiplying matrix by a vector with entries of slowly increasing\n  // magnitude and alternating sign:\n  //   v_i = (-1)^{i} (1 + (i / (dim-1))), i = 0,...,dim-1.\n  // This improvement to Hager's algorithm above is due to Higham. It was\n  // added to make the algorithm more robust in certain corner cases where\n  // large elements in the matrix might otherwise escape detection due to\n  // exact cancellation (especially when op and op_adjoint correspond to a\n  // sequence of backsubstitutions and permutations), which could cause\n  // Hager's algorithm to vastly underestimate ||matrix||_1.\n  Scalar alternating_sign(RealScalar(1));\n  for (Index i = 0; i < n; ++i) {\n    // The static_cast is needed when Scalar is a complex and RealScalar implements expression templates\n    v[i] = alternating_sign * static_cast<RealScalar>(RealScalar(1) + (RealScalar(i) / (RealScalar(n - 1))));\n    alternating_sign = -alternating_sign;\n  }\n  v = dec.solve(v);\n  const RealScalar alternate_lower_bound = (2 * v.template lpNorm<1>()) / (3 * RealScalar(n));\n  return numext::maxi(lower_bound, alternate_lower_bound);\n}\n\n/** \\brief Reciprocal condition number estimator.\n  *\n  * Computing a decomposition of a dense matrix takes O(n^3) operations, while\n  * this method estimates the condition number quickly and reliably in O(n^2)\n  * operations.\n  *\n  * \\returns an estimate of the reciprocal condition number\n  * (1 / (||matrix||_1 * ||inv(matrix)||_1)) of matrix, given ||matrix||_1 and\n  * its decomposition. Supports the following decompositions: FullPivLU,\n  * PartialPivLU, LDLT, and LLT.\n  *\n  * \\sa FullPivLU, PartialPivLU, LDLT, LLT.\n  */\ntemplate <typename Decomposition>\ntypename Decomposition::RealScalar\nrcond_estimate_helper(typename Decomposition::RealScalar matrix_norm, const Decomposition& dec)\n{\n  typedef typename Decomposition::RealScalar RealScalar;\n  eigen_assert(dec.rows() == dec.cols());\n  if (dec.rows() == 0)              return RealScalar(1);\n  if (matrix_norm == RealScalar(0)) return RealScalar(0);\n  if (dec.rows() == 1)              return RealScalar(1);\n  const RealScalar inverse_matrix_norm = rcond_invmatrix_L1_norm_estimate(dec);\n  return (inverse_matrix_norm == RealScalar(0) ? RealScalar(0)\n                                               : (RealScalar(1) / inverse_matrix_norm) / matrix_norm);\n}\n\n}  // namespace internal\n\n}  // namespace Eigen\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/CoreEvaluators.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2011 Benoit Jacob <jacob.benoit.1@gmail.com>\n// Copyright (C) 2011-2014 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2011-2012 Jitse Niesen <jitse@maths.leeds.ac.uk>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n\n#ifndef EIGEN_COREEVALUATORS_H\n#define EIGEN_COREEVALUATORS_H\n\nnamespace Eigen {\n  \nnamespace internal {\n\n// This class returns the evaluator kind from the expression storage kind.\n// Default assumes index based accessors\ntemplate<typename StorageKind>\nstruct storage_kind_to_evaluator_kind {\n  typedef IndexBased Kind;\n};\n\n// This class returns the evaluator shape from the expression storage kind.\n// It can be Dense, Sparse, Triangular, Diagonal, SelfAdjoint, Band, etc.\ntemplate<typename StorageKind> struct storage_kind_to_shape;\n\ntemplate<> struct storage_kind_to_shape<Dense>                  { typedef DenseShape Shape;           };\ntemplate<> struct storage_kind_to_shape<SolverStorage>          { typedef SolverShape Shape;           };\ntemplate<> struct storage_kind_to_shape<PermutationStorage>     { typedef PermutationShape Shape;     };\ntemplate<> struct storage_kind_to_shape<TranspositionsStorage>  { typedef TranspositionsShape Shape;  };\n\n// Evaluators have to be specialized with respect to various criteria such as:\n//  - storage/structure/shape\n//  - scalar type\n//  - etc.\n// Therefore, we need specialization of evaluator providing additional template arguments for each kind of evaluators.\n// We currently distinguish the following kind of evaluators:\n// - unary_evaluator    for expressions taking only one arguments (CwiseUnaryOp, CwiseUnaryView, Transpose, MatrixWrapper, ArrayWrapper, Reverse, Replicate)\n// - binary_evaluator   for expression taking two arguments (CwiseBinaryOp)\n// - ternary_evaluator   for expression taking three arguments (CwiseTernaryOp)\n// - product_evaluator  for linear algebra products (Product); special case of binary_evaluator because it requires additional tags for dispatching.\n// - mapbase_evaluator  for Map, Block, Ref\n// - block_evaluator    for Block (special dispatching to a mapbase_evaluator or unary_evaluator)\n\ntemplate< typename T,\n          typename Arg1Kind   = typename evaluator_traits<typename T::Arg1>::Kind,\n          typename Arg2Kind   = typename evaluator_traits<typename T::Arg2>::Kind,\n          typename Arg3Kind   = typename evaluator_traits<typename T::Arg3>::Kind,\n          typename Arg1Scalar = typename traits<typename T::Arg1>::Scalar,\n          typename Arg2Scalar = typename traits<typename T::Arg2>::Scalar,\n          typename Arg3Scalar = typename traits<typename T::Arg3>::Scalar> struct ternary_evaluator;\n\ntemplate< typename T,\n          typename LhsKind   = typename evaluator_traits<typename T::Lhs>::Kind,\n          typename RhsKind   = typename evaluator_traits<typename T::Rhs>::Kind,\n          typename LhsScalar = typename traits<typename T::Lhs>::Scalar,\n          typename RhsScalar = typename traits<typename T::Rhs>::Scalar> struct binary_evaluator;\n\ntemplate< typename T,\n          typename Kind   = typename evaluator_traits<typename T::NestedExpression>::Kind,\n          typename Scalar = typename T::Scalar> struct unary_evaluator;\n          \n// evaluator_traits<T> contains traits for evaluator<T> \n\ntemplate<typename T>\nstruct evaluator_traits_base\n{\n  // by default, get evaluator kind and shape from storage\n  typedef typename storage_kind_to_evaluator_kind<typename traits<T>::StorageKind>::Kind Kind;\n  typedef typename storage_kind_to_shape<typename traits<T>::StorageKind>::Shape Shape;\n};\n\n// Default evaluator traits\ntemplate<typename T>\nstruct evaluator_traits : public evaluator_traits_base<T>\n{\n};\n\ntemplate<typename T, typename Shape = typename evaluator_traits<T>::Shape >\nstruct evaluator_assume_aliasing {\n  static const bool value = false;\n};\n\n// By default, we assume a unary expression:\ntemplate<typename T>\nstruct evaluator : public unary_evaluator<T>\n{\n  typedef unary_evaluator<T> Base;\n  EIGEN_DEVICE_FUNC explicit evaluator(const T& xpr) : Base(xpr) {}\n};\n\n\n// TODO: Think about const-correctness\ntemplate<typename T>\nstruct evaluator<const T>\n  : evaluator<T>\n{\n  EIGEN_DEVICE_FUNC\n  explicit evaluator(const T& xpr) : evaluator<T>(xpr) {}\n};\n\n// ---------- base class for all evaluators ----------\n\ntemplate<typename ExpressionType>\nstruct evaluator_base : public noncopyable\n{\n  // TODO that's not very nice to have to propagate all these traits. They are currently only needed to handle outer,inner indices.\n  typedef traits<ExpressionType> ExpressionTraits;\n  \n  enum {\n    Alignment = 0\n  };\n};\n\n// -------------------- Matrix and Array --------------------\n//\n// evaluator<PlainObjectBase> is a common base class for the\n// Matrix and Array evaluators.\n// Here we directly specialize evaluator. This is not really a unary expression, and it is, by definition, dense,\n// so no need for more sophisticated dispatching.\n\ntemplate<typename Derived>\nstruct evaluator<PlainObjectBase<Derived> >\n  : evaluator_base<Derived>\n{\n  typedef PlainObjectBase<Derived> PlainObjectType;\n  typedef typename PlainObjectType::Scalar Scalar;\n  typedef typename PlainObjectType::CoeffReturnType CoeffReturnType;\n\n  enum {\n    IsRowMajor = PlainObjectType::IsRowMajor,\n    IsVectorAtCompileTime = PlainObjectType::IsVectorAtCompileTime,\n    RowsAtCompileTime = PlainObjectType::RowsAtCompileTime,\n    ColsAtCompileTime = PlainObjectType::ColsAtCompileTime,\n    \n    CoeffReadCost = NumTraits<Scalar>::ReadCost,\n    Flags = traits<Derived>::EvaluatorFlags,\n    Alignment = traits<Derived>::Alignment\n  };\n  \n  EIGEN_DEVICE_FUNC evaluator()\n    : m_data(0),\n      m_outerStride(IsVectorAtCompileTime  ? 0 \n                                           : int(IsRowMajor) ? ColsAtCompileTime \n                                           : RowsAtCompileTime)\n  {\n    EIGEN_INTERNAL_CHECK_COST_VALUE(CoeffReadCost);\n  }\n  \n  EIGEN_DEVICE_FUNC explicit evaluator(const PlainObjectType& m)\n    : m_data(m.data()), m_outerStride(IsVectorAtCompileTime ? 0 : m.outerStride()) \n  {\n    EIGEN_INTERNAL_CHECK_COST_VALUE(CoeffReadCost);\n  }\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  CoeffReturnType coeff(Index row, Index col) const\n  {\n    if (IsRowMajor)\n      return m_data[row * m_outerStride.value() + col];\n    else\n      return m_data[row + col * m_outerStride.value()];\n  }\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  CoeffReturnType coeff(Index index) const\n  {\n    return m_data[index];\n  }\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  Scalar& coeffRef(Index row, Index col)\n  {\n    if (IsRowMajor)\n      return const_cast<Scalar*>(m_data)[row * m_outerStride.value() + col];\n    else\n      return const_cast<Scalar*>(m_data)[row + col * m_outerStride.value()];\n  }\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  Scalar& coeffRef(Index index)\n  {\n    return const_cast<Scalar*>(m_data)[index];\n  }\n\n  template<int LoadMode, typename PacketType>\n  EIGEN_STRONG_INLINE\n  PacketType packet(Index row, Index col) const\n  {\n    if (IsRowMajor)\n      return ploadt<PacketType, LoadMode>(m_data + row * m_outerStride.value() + col);\n    else\n      return ploadt<PacketType, LoadMode>(m_data + row + col * m_outerStride.value());\n  }\n\n  template<int LoadMode, typename PacketType>\n  EIGEN_STRONG_INLINE\n  PacketType packet(Index index) const\n  {\n    return ploadt<PacketType, LoadMode>(m_data + index);\n  }\n\n  template<int StoreMode,typename PacketType>\n  EIGEN_STRONG_INLINE\n  void writePacket(Index row, Index col, const PacketType& x)\n  {\n    if (IsRowMajor)\n      return pstoret<Scalar, PacketType, StoreMode>\n\t            (const_cast<Scalar*>(m_data) + row * m_outerStride.value() + col, x);\n    else\n      return pstoret<Scalar, PacketType, StoreMode>\n                    (const_cast<Scalar*>(m_data) + row + col * m_outerStride.value(), x);\n  }\n\n  template<int StoreMode, typename PacketType>\n  EIGEN_STRONG_INLINE\n  void writePacket(Index index, const PacketType& x)\n  {\n    return pstoret<Scalar, PacketType, StoreMode>(const_cast<Scalar*>(m_data) + index, x);\n  }\n\nprotected:\n  const Scalar *m_data;\n\n  // We do not need to know the outer stride for vectors\n  variable_if_dynamic<Index, IsVectorAtCompileTime  ? 0 \n                                                    : int(IsRowMajor) ? ColsAtCompileTime \n                                                    : RowsAtCompileTime> m_outerStride;\n};\n\ntemplate<typename Scalar, int Rows, int Cols, int Options, int MaxRows, int MaxCols>\nstruct evaluator<Matrix<Scalar, Rows, Cols, Options, MaxRows, MaxCols> >\n  : evaluator<PlainObjectBase<Matrix<Scalar, Rows, Cols, Options, MaxRows, MaxCols> > >\n{\n  typedef Matrix<Scalar, Rows, Cols, Options, MaxRows, MaxCols> XprType;\n  \n  EIGEN_DEVICE_FUNC evaluator() {}\n\n  EIGEN_DEVICE_FUNC explicit evaluator(const XprType& m)\n    : evaluator<PlainObjectBase<XprType> >(m) \n  { }\n};\n\ntemplate<typename Scalar, int Rows, int Cols, int Options, int MaxRows, int MaxCols>\nstruct evaluator<Array<Scalar, Rows, Cols, Options, MaxRows, MaxCols> >\n  : evaluator<PlainObjectBase<Array<Scalar, Rows, Cols, Options, MaxRows, MaxCols> > >\n{\n  typedef Array<Scalar, Rows, Cols, Options, MaxRows, MaxCols> XprType;\n\n  EIGEN_DEVICE_FUNC evaluator() {}\n  \n  EIGEN_DEVICE_FUNC explicit evaluator(const XprType& m)\n    : evaluator<PlainObjectBase<XprType> >(m) \n  { }\n};\n\n// -------------------- Transpose --------------------\n\ntemplate<typename ArgType>\nstruct unary_evaluator<Transpose<ArgType>, IndexBased>\n  : evaluator_base<Transpose<ArgType> >\n{\n  typedef Transpose<ArgType> XprType;\n  \n  enum {\n    CoeffReadCost = evaluator<ArgType>::CoeffReadCost,    \n    Flags = evaluator<ArgType>::Flags ^ RowMajorBit,\n    Alignment = evaluator<ArgType>::Alignment\n  };\n\n  EIGEN_DEVICE_FUNC explicit unary_evaluator(const XprType& t) : m_argImpl(t.nestedExpression()) {}\n\n  typedef typename XprType::Scalar Scalar;\n  typedef typename XprType::CoeffReturnType CoeffReturnType;\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  CoeffReturnType coeff(Index row, Index col) const\n  {\n    return m_argImpl.coeff(col, row);\n  }\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  CoeffReturnType coeff(Index index) const\n  {\n    return m_argImpl.coeff(index);\n  }\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  Scalar& coeffRef(Index row, Index col)\n  {\n    return m_argImpl.coeffRef(col, row);\n  }\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  typename XprType::Scalar& coeffRef(Index index)\n  {\n    return m_argImpl.coeffRef(index);\n  }\n\n  template<int LoadMode, typename PacketType>\n  EIGEN_STRONG_INLINE\n  PacketType packet(Index row, Index col) const\n  {\n    return m_argImpl.template packet<LoadMode,PacketType>(col, row);\n  }\n\n  template<int LoadMode, typename PacketType>\n  EIGEN_STRONG_INLINE\n  PacketType packet(Index index) const\n  {\n    return m_argImpl.template packet<LoadMode,PacketType>(index);\n  }\n\n  template<int StoreMode, typename PacketType>\n  EIGEN_STRONG_INLINE\n  void writePacket(Index row, Index col, const PacketType& x)\n  {\n    m_argImpl.template writePacket<StoreMode,PacketType>(col, row, x);\n  }\n\n  template<int StoreMode, typename PacketType>\n  EIGEN_STRONG_INLINE\n  void writePacket(Index index, const PacketType& x)\n  {\n    m_argImpl.template writePacket<StoreMode,PacketType>(index, x);\n  }\n\nprotected:\n  evaluator<ArgType> m_argImpl;\n};\n\n// -------------------- CwiseNullaryOp --------------------\n// Like Matrix and Array, this is not really a unary expression, so we directly specialize evaluator.\n// Likewise, there is not need to more sophisticated dispatching here.\n\ntemplate<typename Scalar,typename NullaryOp,\n         bool has_nullary = has_nullary_operator<NullaryOp>::value,\n         bool has_unary   = has_unary_operator<NullaryOp>::value,\n         bool has_binary  = has_binary_operator<NullaryOp>::value>\nstruct nullary_wrapper\n{\n  template <typename IndexType>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE Scalar operator()(const NullaryOp& op, IndexType i, IndexType j) const { return op(i,j); }\n  template <typename IndexType>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE Scalar operator()(const NullaryOp& op, IndexType i) const { return op(i); }\n\n  template <typename T, typename IndexType> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE T packetOp(const NullaryOp& op, IndexType i, IndexType j) const { return op.template packetOp<T>(i,j); }\n  template <typename T, typename IndexType> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE T packetOp(const NullaryOp& op, IndexType i) const { return op.template packetOp<T>(i); }\n};\n\ntemplate<typename Scalar,typename NullaryOp>\nstruct nullary_wrapper<Scalar,NullaryOp,true,false,false>\n{\n  template <typename IndexType>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE Scalar operator()(const NullaryOp& op, IndexType=0, IndexType=0) const { return op(); }\n  template <typename T, typename IndexType> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE T packetOp(const NullaryOp& op, IndexType=0, IndexType=0) const { return op.template packetOp<T>(); }\n};\n\ntemplate<typename Scalar,typename NullaryOp>\nstruct nullary_wrapper<Scalar,NullaryOp,false,false,true>\n{\n  template <typename IndexType>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE Scalar operator()(const NullaryOp& op, IndexType i, IndexType j=0) const { return op(i,j); }\n  template <typename T, typename IndexType> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE T packetOp(const NullaryOp& op, IndexType i, IndexType j=0) const { return op.template packetOp<T>(i,j); }\n};\n\n// We need the following specialization for vector-only functors assigned to a runtime vector,\n// for instance, using linspace and assigning a RowVectorXd to a MatrixXd or even a row of a MatrixXd.\n// In this case, i==0 and j is used for the actual iteration.\ntemplate<typename Scalar,typename NullaryOp>\nstruct nullary_wrapper<Scalar,NullaryOp,false,true,false>\n{\n  template <typename IndexType>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE Scalar operator()(const NullaryOp& op, IndexType i, IndexType j) const {\n    eigen_assert(i==0 || j==0);\n    return op(i+j);\n  }\n  template <typename T, typename IndexType> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE T packetOp(const NullaryOp& op, IndexType i, IndexType j) const {\n    eigen_assert(i==0 || j==0);\n    return op.template packetOp<T>(i+j);\n  }\n\n  template <typename IndexType>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE Scalar operator()(const NullaryOp& op, IndexType i) const { return op(i); }\n  template <typename T, typename IndexType>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE T packetOp(const NullaryOp& op, IndexType i) const { return op.template packetOp<T>(i); }\n};\n\ntemplate<typename Scalar,typename NullaryOp>\nstruct nullary_wrapper<Scalar,NullaryOp,false,false,false> {};\n\n#if 0 && EIGEN_COMP_MSVC>0\n// Disable this ugly workaround. This is now handled in traits<Ref>::match,\n// but this piece of code might still become handly if some other weird compilation\n// erros pop up again.\n\n// MSVC exhibits a weird compilation error when\n// compiling:\n//    Eigen::MatrixXf A = MatrixXf::Random(3,3);\n//    Ref<const MatrixXf> R = 2.f*A;\n// and that has_*ary_operator<scalar_constant_op<float>> have not been instantiated yet.\n// The \"problem\" is that evaluator<2.f*A> is instantiated by traits<Ref>::match<2.f*A>\n// and at that time has_*ary_operator<T> returns true regardless of T.\n// Then nullary_wrapper is badly instantiated as nullary_wrapper<.,.,true,true,true>.\n// The trick is thus to defer the proper instantiation of nullary_wrapper when coeff(),\n// and packet() are really instantiated as implemented below:\n\n// This is a simple wrapper around Index to enforce the re-instantiation of\n// has_*ary_operator when needed.\ntemplate<typename T> struct nullary_wrapper_workaround_msvc {\n  nullary_wrapper_workaround_msvc(const T&);\n  operator T()const;\n};\n\ntemplate<typename Scalar,typename NullaryOp>\nstruct nullary_wrapper<Scalar,NullaryOp,true,true,true>\n{\n  template <typename IndexType>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE Scalar operator()(const NullaryOp& op, IndexType i, IndexType j) const {\n    return nullary_wrapper<Scalar,NullaryOp,\n    has_nullary_operator<NullaryOp,nullary_wrapper_workaround_msvc<IndexType> >::value,\n    has_unary_operator<NullaryOp,nullary_wrapper_workaround_msvc<IndexType> >::value,\n    has_binary_operator<NullaryOp,nullary_wrapper_workaround_msvc<IndexType> >::value>().operator()(op,i,j);\n  }\n  template <typename IndexType>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE Scalar operator()(const NullaryOp& op, IndexType i) const {\n    return nullary_wrapper<Scalar,NullaryOp,\n    has_nullary_operator<NullaryOp,nullary_wrapper_workaround_msvc<IndexType> >::value,\n    has_unary_operator<NullaryOp,nullary_wrapper_workaround_msvc<IndexType> >::value,\n    has_binary_operator<NullaryOp,nullary_wrapper_workaround_msvc<IndexType> >::value>().operator()(op,i);\n  }\n\n  template <typename T, typename IndexType>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE T packetOp(const NullaryOp& op, IndexType i, IndexType j) const {\n    return nullary_wrapper<Scalar,NullaryOp,\n    has_nullary_operator<NullaryOp,nullary_wrapper_workaround_msvc<IndexType> >::value,\n    has_unary_operator<NullaryOp,nullary_wrapper_workaround_msvc<IndexType> >::value,\n    has_binary_operator<NullaryOp,nullary_wrapper_workaround_msvc<IndexType> >::value>().template packetOp<T>(op,i,j);\n  }\n  template <typename T, typename IndexType>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE T packetOp(const NullaryOp& op, IndexType i) const {\n    return nullary_wrapper<Scalar,NullaryOp,\n    has_nullary_operator<NullaryOp,nullary_wrapper_workaround_msvc<IndexType> >::value,\n    has_unary_operator<NullaryOp,nullary_wrapper_workaround_msvc<IndexType> >::value,\n    has_binary_operator<NullaryOp,nullary_wrapper_workaround_msvc<IndexType> >::value>().template packetOp<T>(op,i);\n  }\n};\n#endif // MSVC workaround\n\ntemplate<typename NullaryOp, typename PlainObjectType>\nstruct evaluator<CwiseNullaryOp<NullaryOp,PlainObjectType> >\n  : evaluator_base<CwiseNullaryOp<NullaryOp,PlainObjectType> >\n{\n  typedef CwiseNullaryOp<NullaryOp,PlainObjectType> XprType;\n  typedef typename internal::remove_all<PlainObjectType>::type PlainObjectTypeCleaned;\n  \n  enum {\n    CoeffReadCost = internal::functor_traits<NullaryOp>::Cost,\n    \n    Flags = (evaluator<PlainObjectTypeCleaned>::Flags\n          &  (  HereditaryBits\n              | (functor_has_linear_access<NullaryOp>::ret  ? LinearAccessBit : 0)\n              | (functor_traits<NullaryOp>::PacketAccess    ? PacketAccessBit : 0)))\n          | (functor_traits<NullaryOp>::IsRepeatable ? 0 : EvalBeforeNestingBit),\n    Alignment = AlignedMax\n  };\n\n  EIGEN_DEVICE_FUNC explicit evaluator(const XprType& n)\n    : m_functor(n.functor()), m_wrapper()\n  {\n    EIGEN_INTERNAL_CHECK_COST_VALUE(CoeffReadCost);\n  }\n\n  typedef typename XprType::CoeffReturnType CoeffReturnType;\n\n  template <typename IndexType>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  CoeffReturnType coeff(IndexType row, IndexType col) const\n  {\n    return m_wrapper(m_functor, row, col);\n  }\n\n  template <typename IndexType>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  CoeffReturnType coeff(IndexType index) const\n  {\n    return m_wrapper(m_functor,index);\n  }\n\n  template<int LoadMode, typename PacketType, typename IndexType>\n  EIGEN_STRONG_INLINE\n  PacketType packet(IndexType row, IndexType col) const\n  {\n    return m_wrapper.template packetOp<PacketType>(m_functor, row, col);\n  }\n\n  template<int LoadMode, typename PacketType, typename IndexType>\n  EIGEN_STRONG_INLINE\n  PacketType packet(IndexType index) const\n  {\n    return m_wrapper.template packetOp<PacketType>(m_functor, index);\n  }\n\nprotected:\n  const NullaryOp m_functor;\n  const internal::nullary_wrapper<CoeffReturnType,NullaryOp> m_wrapper;\n};\n\n// -------------------- CwiseUnaryOp --------------------\n\ntemplate<typename UnaryOp, typename ArgType>\nstruct unary_evaluator<CwiseUnaryOp<UnaryOp, ArgType>, IndexBased >\n  : evaluator_base<CwiseUnaryOp<UnaryOp, ArgType> >\n{\n  typedef CwiseUnaryOp<UnaryOp, ArgType> XprType;\n  \n  enum {\n    CoeffReadCost = evaluator<ArgType>::CoeffReadCost + functor_traits<UnaryOp>::Cost,\n    \n    Flags = evaluator<ArgType>::Flags\n          & (HereditaryBits | LinearAccessBit | (functor_traits<UnaryOp>::PacketAccess ? PacketAccessBit : 0)),\n    Alignment = evaluator<ArgType>::Alignment\n  };\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  explicit unary_evaluator(const XprType& op)\n    : m_functor(op.functor()), \n      m_argImpl(op.nestedExpression()) \n  {\n    EIGEN_INTERNAL_CHECK_COST_VALUE(functor_traits<UnaryOp>::Cost);\n    EIGEN_INTERNAL_CHECK_COST_VALUE(CoeffReadCost);\n  }\n\n  typedef typename XprType::CoeffReturnType CoeffReturnType;\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  CoeffReturnType coeff(Index row, Index col) const\n  {\n    return m_functor(m_argImpl.coeff(row, col));\n  }\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  CoeffReturnType coeff(Index index) const\n  {\n    return m_functor(m_argImpl.coeff(index));\n  }\n\n  template<int LoadMode, typename PacketType>\n  EIGEN_STRONG_INLINE\n  PacketType packet(Index row, Index col) const\n  {\n    return m_functor.packetOp(m_argImpl.template packet<LoadMode, PacketType>(row, col));\n  }\n\n  template<int LoadMode, typename PacketType>\n  EIGEN_STRONG_INLINE\n  PacketType packet(Index index) const\n  {\n    return m_functor.packetOp(m_argImpl.template packet<LoadMode, PacketType>(index));\n  }\n\nprotected:\n  const UnaryOp m_functor;\n  evaluator<ArgType> m_argImpl;\n};\n\n// -------------------- CwiseTernaryOp --------------------\n\n// this is a ternary expression\ntemplate<typename TernaryOp, typename Arg1, typename Arg2, typename Arg3>\nstruct evaluator<CwiseTernaryOp<TernaryOp, Arg1, Arg2, Arg3> >\n  : public ternary_evaluator<CwiseTernaryOp<TernaryOp, Arg1, Arg2, Arg3> >\n{\n  typedef CwiseTernaryOp<TernaryOp, Arg1, Arg2, Arg3> XprType;\n  typedef ternary_evaluator<CwiseTernaryOp<TernaryOp, Arg1, Arg2, Arg3> > Base;\n  \n  EIGEN_DEVICE_FUNC explicit evaluator(const XprType& xpr) : Base(xpr) {}\n};\n\ntemplate<typename TernaryOp, typename Arg1, typename Arg2, typename Arg3>\nstruct ternary_evaluator<CwiseTernaryOp<TernaryOp, Arg1, Arg2, Arg3>, IndexBased, IndexBased>\n  : evaluator_base<CwiseTernaryOp<TernaryOp, Arg1, Arg2, Arg3> >\n{\n  typedef CwiseTernaryOp<TernaryOp, Arg1, Arg2, Arg3> XprType;\n  \n  enum {\n    CoeffReadCost = evaluator<Arg1>::CoeffReadCost + evaluator<Arg2>::CoeffReadCost + evaluator<Arg3>::CoeffReadCost + functor_traits<TernaryOp>::Cost,\n    \n    Arg1Flags = evaluator<Arg1>::Flags,\n    Arg2Flags = evaluator<Arg2>::Flags,\n    Arg3Flags = evaluator<Arg3>::Flags,\n    SameType = is_same<typename Arg1::Scalar,typename Arg2::Scalar>::value && is_same<typename Arg1::Scalar,typename Arg3::Scalar>::value,\n    StorageOrdersAgree = (int(Arg1Flags)&RowMajorBit)==(int(Arg2Flags)&RowMajorBit) && (int(Arg1Flags)&RowMajorBit)==(int(Arg3Flags)&RowMajorBit),\n    Flags0 = (int(Arg1Flags) | int(Arg2Flags) | int(Arg3Flags)) & (\n        HereditaryBits\n        | (int(Arg1Flags) & int(Arg2Flags) & int(Arg3Flags) &\n           ( (StorageOrdersAgree ? LinearAccessBit : 0)\n           | (functor_traits<TernaryOp>::PacketAccess && StorageOrdersAgree && SameType ? PacketAccessBit : 0)\n           )\n        )\n     ),\n    Flags = (Flags0 & ~RowMajorBit) | (Arg1Flags & RowMajorBit),\n    Alignment = EIGEN_PLAIN_ENUM_MIN(\n        EIGEN_PLAIN_ENUM_MIN(evaluator<Arg1>::Alignment, evaluator<Arg2>::Alignment),\n        evaluator<Arg3>::Alignment)\n  };\n\n  EIGEN_DEVICE_FUNC explicit ternary_evaluator(const XprType& xpr)\n    : m_functor(xpr.functor()),\n      m_arg1Impl(xpr.arg1()), \n      m_arg2Impl(xpr.arg2()), \n      m_arg3Impl(xpr.arg3())  \n  {\n    EIGEN_INTERNAL_CHECK_COST_VALUE(functor_traits<TernaryOp>::Cost);\n    EIGEN_INTERNAL_CHECK_COST_VALUE(CoeffReadCost);\n  }\n\n  typedef typename XprType::CoeffReturnType CoeffReturnType;\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  CoeffReturnType coeff(Index row, Index col) const\n  {\n    return m_functor(m_arg1Impl.coeff(row, col), m_arg2Impl.coeff(row, col), m_arg3Impl.coeff(row, col));\n  }\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  CoeffReturnType coeff(Index index) const\n  {\n    return m_functor(m_arg1Impl.coeff(index), m_arg2Impl.coeff(index), m_arg3Impl.coeff(index));\n  }\n\n  template<int LoadMode, typename PacketType>\n  EIGEN_STRONG_INLINE\n  PacketType packet(Index row, Index col) const\n  {\n    return m_functor.packetOp(m_arg1Impl.template packet<LoadMode,PacketType>(row, col),\n                              m_arg2Impl.template packet<LoadMode,PacketType>(row, col),\n                              m_arg3Impl.template packet<LoadMode,PacketType>(row, col));\n  }\n\n  template<int LoadMode, typename PacketType>\n  EIGEN_STRONG_INLINE\n  PacketType packet(Index index) const\n  {\n    return m_functor.packetOp(m_arg1Impl.template packet<LoadMode,PacketType>(index),\n                              m_arg2Impl.template packet<LoadMode,PacketType>(index),\n                              m_arg3Impl.template packet<LoadMode,PacketType>(index));\n  }\n\nprotected:\n  const TernaryOp m_functor;\n  evaluator<Arg1> m_arg1Impl;\n  evaluator<Arg2> m_arg2Impl;\n  evaluator<Arg3> m_arg3Impl;\n};\n\n// -------------------- CwiseBinaryOp --------------------\n\n// this is a binary expression\ntemplate<typename BinaryOp, typename Lhs, typename Rhs>\nstruct evaluator<CwiseBinaryOp<BinaryOp, Lhs, Rhs> >\n  : public binary_evaluator<CwiseBinaryOp<BinaryOp, Lhs, Rhs> >\n{\n  typedef CwiseBinaryOp<BinaryOp, Lhs, Rhs> XprType;\n  typedef binary_evaluator<CwiseBinaryOp<BinaryOp, Lhs, Rhs> > Base;\n  \n  EIGEN_DEVICE_FUNC explicit evaluator(const XprType& xpr) : Base(xpr) {}\n};\n\ntemplate<typename BinaryOp, typename Lhs, typename Rhs>\nstruct binary_evaluator<CwiseBinaryOp<BinaryOp, Lhs, Rhs>, IndexBased, IndexBased>\n  : evaluator_base<CwiseBinaryOp<BinaryOp, Lhs, Rhs> >\n{\n  typedef CwiseBinaryOp<BinaryOp, Lhs, Rhs> XprType;\n  \n  enum {\n    CoeffReadCost = evaluator<Lhs>::CoeffReadCost + evaluator<Rhs>::CoeffReadCost + functor_traits<BinaryOp>::Cost,\n    \n    LhsFlags = evaluator<Lhs>::Flags,\n    RhsFlags = evaluator<Rhs>::Flags,\n    SameType = is_same<typename Lhs::Scalar,typename Rhs::Scalar>::value,\n    StorageOrdersAgree = (int(LhsFlags)&RowMajorBit)==(int(RhsFlags)&RowMajorBit),\n    Flags0 = (int(LhsFlags) | int(RhsFlags)) & (\n        HereditaryBits\n      | (int(LhsFlags) & int(RhsFlags) &\n           ( (StorageOrdersAgree ? LinearAccessBit : 0)\n           | (functor_traits<BinaryOp>::PacketAccess && StorageOrdersAgree && SameType ? PacketAccessBit : 0)\n           )\n        )\n     ),\n    Flags = (Flags0 & ~RowMajorBit) | (LhsFlags & RowMajorBit),\n    Alignment = EIGEN_PLAIN_ENUM_MIN(evaluator<Lhs>::Alignment,evaluator<Rhs>::Alignment)\n  };\n\n  EIGEN_DEVICE_FUNC explicit binary_evaluator(const XprType& xpr)\n    : m_functor(xpr.functor()),\n      m_lhsImpl(xpr.lhs()), \n      m_rhsImpl(xpr.rhs())  \n  {\n    EIGEN_INTERNAL_CHECK_COST_VALUE(functor_traits<BinaryOp>::Cost);\n    EIGEN_INTERNAL_CHECK_COST_VALUE(CoeffReadCost);\n  }\n\n  typedef typename XprType::CoeffReturnType CoeffReturnType;\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  CoeffReturnType coeff(Index row, Index col) const\n  {\n    return m_functor(m_lhsImpl.coeff(row, col), m_rhsImpl.coeff(row, col));\n  }\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  CoeffReturnType coeff(Index index) const\n  {\n    return m_functor(m_lhsImpl.coeff(index), m_rhsImpl.coeff(index));\n  }\n\n  template<int LoadMode, typename PacketType>\n  EIGEN_STRONG_INLINE\n  PacketType packet(Index row, Index col) const\n  {\n    return m_functor.packetOp(m_lhsImpl.template packet<LoadMode,PacketType>(row, col),\n                              m_rhsImpl.template packet<LoadMode,PacketType>(row, col));\n  }\n\n  template<int LoadMode, typename PacketType>\n  EIGEN_STRONG_INLINE\n  PacketType packet(Index index) const\n  {\n    return m_functor.packetOp(m_lhsImpl.template packet<LoadMode,PacketType>(index),\n                              m_rhsImpl.template packet<LoadMode,PacketType>(index));\n  }\n\nprotected:\n  const BinaryOp m_functor;\n  evaluator<Lhs> m_lhsImpl;\n  evaluator<Rhs> m_rhsImpl;\n};\n\n// -------------------- CwiseUnaryView --------------------\n\ntemplate<typename UnaryOp, typename ArgType>\nstruct unary_evaluator<CwiseUnaryView<UnaryOp, ArgType>, IndexBased>\n  : evaluator_base<CwiseUnaryView<UnaryOp, ArgType> >\n{\n  typedef CwiseUnaryView<UnaryOp, ArgType> XprType;\n  \n  enum {\n    CoeffReadCost = evaluator<ArgType>::CoeffReadCost + functor_traits<UnaryOp>::Cost,\n    \n    Flags = (evaluator<ArgType>::Flags & (HereditaryBits | LinearAccessBit | DirectAccessBit)),\n    \n    Alignment = 0 // FIXME it is not very clear why alignment is necessarily lost...\n  };\n\n  EIGEN_DEVICE_FUNC explicit unary_evaluator(const XprType& op)\n    : m_unaryOp(op.functor()), \n      m_argImpl(op.nestedExpression()) \n  {\n    EIGEN_INTERNAL_CHECK_COST_VALUE(functor_traits<UnaryOp>::Cost);\n    EIGEN_INTERNAL_CHECK_COST_VALUE(CoeffReadCost);\n  }\n\n  typedef typename XprType::Scalar Scalar;\n  typedef typename XprType::CoeffReturnType CoeffReturnType;\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  CoeffReturnType coeff(Index row, Index col) const\n  {\n    return m_unaryOp(m_argImpl.coeff(row, col));\n  }\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  CoeffReturnType coeff(Index index) const\n  {\n    return m_unaryOp(m_argImpl.coeff(index));\n  }\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  Scalar& coeffRef(Index row, Index col)\n  {\n    return m_unaryOp(m_argImpl.coeffRef(row, col));\n  }\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  Scalar& coeffRef(Index index)\n  {\n    return m_unaryOp(m_argImpl.coeffRef(index));\n  }\n\nprotected:\n  const UnaryOp m_unaryOp;\n  evaluator<ArgType> m_argImpl;\n};\n\n// -------------------- Map --------------------\n\n// FIXME perhaps the PlainObjectType could be provided by Derived::PlainObject ?\n// but that might complicate template specialization\ntemplate<typename Derived, typename PlainObjectType>\nstruct mapbase_evaluator;\n\ntemplate<typename Derived, typename PlainObjectType>\nstruct mapbase_evaluator : evaluator_base<Derived>\n{\n  typedef Derived  XprType;\n  typedef typename XprType::PointerType PointerType;\n  typedef typename XprType::Scalar Scalar;\n  typedef typename XprType::CoeffReturnType CoeffReturnType;\n  \n  enum {\n    IsRowMajor = XprType::RowsAtCompileTime,\n    ColsAtCompileTime = XprType::ColsAtCompileTime,\n    CoeffReadCost = NumTraits<Scalar>::ReadCost\n  };\n\n  EIGEN_DEVICE_FUNC explicit mapbase_evaluator(const XprType& map)\n    : m_data(const_cast<PointerType>(map.data())),\n      m_innerStride(map.innerStride()),\n      m_outerStride(map.outerStride())\n  {\n    EIGEN_STATIC_ASSERT(EIGEN_IMPLIES(evaluator<Derived>::Flags&PacketAccessBit, internal::inner_stride_at_compile_time<Derived>::ret==1),\n                        PACKET_ACCESS_REQUIRES_TO_HAVE_INNER_STRIDE_FIXED_TO_1);\n    EIGEN_INTERNAL_CHECK_COST_VALUE(CoeffReadCost);\n  }\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  CoeffReturnType coeff(Index row, Index col) const\n  {\n    return m_data[col * colStride() + row * rowStride()];\n  }\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  CoeffReturnType coeff(Index index) const\n  {\n    return m_data[index * m_innerStride.value()];\n  }\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  Scalar& coeffRef(Index row, Index col)\n  {\n    return m_data[col * colStride() + row * rowStride()];\n  }\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  Scalar& coeffRef(Index index)\n  {\n    return m_data[index * m_innerStride.value()];\n  }\n\n  template<int LoadMode, typename PacketType>\n  EIGEN_STRONG_INLINE\n  PacketType packet(Index row, Index col) const\n  {\n    PointerType ptr = m_data + row * rowStride() + col * colStride();\n    return internal::ploadt<PacketType, LoadMode>(ptr);\n  }\n\n  template<int LoadMode, typename PacketType>\n  EIGEN_STRONG_INLINE\n  PacketType packet(Index index) const\n  {\n    return internal::ploadt<PacketType, LoadMode>(m_data + index * m_innerStride.value());\n  }\n\n  template<int StoreMode, typename PacketType>\n  EIGEN_STRONG_INLINE\n  void writePacket(Index row, Index col, const PacketType& x)\n  {\n    PointerType ptr = m_data + row * rowStride() + col * colStride();\n    return internal::pstoret<Scalar, PacketType, StoreMode>(ptr, x);\n  }\n\n  template<int StoreMode, typename PacketType>\n  EIGEN_STRONG_INLINE\n  void writePacket(Index index, const PacketType& x)\n  {\n    internal::pstoret<Scalar, PacketType, StoreMode>(m_data + index * m_innerStride.value(), x);\n  }\nprotected:\n  EIGEN_DEVICE_FUNC\n  inline Index rowStride() const { return XprType::IsRowMajor ? m_outerStride.value() : m_innerStride.value(); }\n  EIGEN_DEVICE_FUNC\n  inline Index colStride() const { return XprType::IsRowMajor ? m_innerStride.value() : m_outerStride.value(); }\n\n  PointerType m_data;\n  const internal::variable_if_dynamic<Index, XprType::InnerStrideAtCompileTime> m_innerStride;\n  const internal::variable_if_dynamic<Index, XprType::OuterStrideAtCompileTime> m_outerStride;\n};\n\ntemplate<typename PlainObjectType, int MapOptions, typename StrideType> \nstruct evaluator<Map<PlainObjectType, MapOptions, StrideType> >\n  : public mapbase_evaluator<Map<PlainObjectType, MapOptions, StrideType>, PlainObjectType>\n{\n  typedef Map<PlainObjectType, MapOptions, StrideType> XprType;\n  typedef typename XprType::Scalar Scalar;\n  // TODO: should check for smaller packet types once we can handle multi-sized packet types\n  typedef typename packet_traits<Scalar>::type PacketScalar;\n  \n  enum {\n    InnerStrideAtCompileTime = StrideType::InnerStrideAtCompileTime == 0\n                             ? int(PlainObjectType::InnerStrideAtCompileTime)\n                             : int(StrideType::InnerStrideAtCompileTime),\n    OuterStrideAtCompileTime = StrideType::OuterStrideAtCompileTime == 0\n                             ? int(PlainObjectType::OuterStrideAtCompileTime)\n                             : int(StrideType::OuterStrideAtCompileTime),\n    HasNoInnerStride = InnerStrideAtCompileTime == 1,\n    HasNoOuterStride = StrideType::OuterStrideAtCompileTime == 0,\n    HasNoStride = HasNoInnerStride && HasNoOuterStride,\n    IsDynamicSize = PlainObjectType::SizeAtCompileTime==Dynamic,\n    \n    PacketAccessMask = bool(HasNoInnerStride) ? ~int(0) : ~int(PacketAccessBit),\n    LinearAccessMask = bool(HasNoStride) || bool(PlainObjectType::IsVectorAtCompileTime) ? ~int(0) : ~int(LinearAccessBit),\n    Flags = int( evaluator<PlainObjectType>::Flags) & (LinearAccessMask&PacketAccessMask),\n    \n    Alignment = int(MapOptions)&int(AlignedMask)\n  };\n\n  EIGEN_DEVICE_FUNC explicit evaluator(const XprType& map)\n    : mapbase_evaluator<XprType, PlainObjectType>(map) \n  { }\n};\n\n// -------------------- Ref --------------------\n\ntemplate<typename PlainObjectType, int RefOptions, typename StrideType> \nstruct evaluator<Ref<PlainObjectType, RefOptions, StrideType> >\n  : public mapbase_evaluator<Ref<PlainObjectType, RefOptions, StrideType>, PlainObjectType>\n{\n  typedef Ref<PlainObjectType, RefOptions, StrideType> XprType;\n  \n  enum {\n    Flags = evaluator<Map<PlainObjectType, RefOptions, StrideType> >::Flags,\n    Alignment = evaluator<Map<PlainObjectType, RefOptions, StrideType> >::Alignment\n  };\n\n  EIGEN_DEVICE_FUNC explicit evaluator(const XprType& ref)\n    : mapbase_evaluator<XprType, PlainObjectType>(ref) \n  { }\n};\n\n// -------------------- Block --------------------\n\ntemplate<typename ArgType, int BlockRows, int BlockCols, bool InnerPanel,\n         bool HasDirectAccess = internal::has_direct_access<ArgType>::ret> struct block_evaluator;\n         \ntemplate<typename ArgType, int BlockRows, int BlockCols, bool InnerPanel> \nstruct evaluator<Block<ArgType, BlockRows, BlockCols, InnerPanel> >\n  : block_evaluator<ArgType, BlockRows, BlockCols, InnerPanel>\n{\n  typedef Block<ArgType, BlockRows, BlockCols, InnerPanel> XprType;\n  typedef typename XprType::Scalar Scalar;\n  // TODO: should check for smaller packet types once we can handle multi-sized packet types\n  typedef typename packet_traits<Scalar>::type PacketScalar;\n  \n  enum {\n    CoeffReadCost = evaluator<ArgType>::CoeffReadCost,\n    \n    RowsAtCompileTime = traits<XprType>::RowsAtCompileTime,\n    ColsAtCompileTime = traits<XprType>::ColsAtCompileTime,\n    MaxRowsAtCompileTime = traits<XprType>::MaxRowsAtCompileTime,\n    MaxColsAtCompileTime = traits<XprType>::MaxColsAtCompileTime,\n    \n    ArgTypeIsRowMajor = (int(evaluator<ArgType>::Flags)&RowMajorBit) != 0,\n    IsRowMajor = (MaxRowsAtCompileTime==1 && MaxColsAtCompileTime!=1) ? 1\n               : (MaxColsAtCompileTime==1 && MaxRowsAtCompileTime!=1) ? 0\n               : ArgTypeIsRowMajor,\n    HasSameStorageOrderAsArgType = (IsRowMajor == ArgTypeIsRowMajor),\n    InnerSize = IsRowMajor ? int(ColsAtCompileTime) : int(RowsAtCompileTime),\n    InnerStrideAtCompileTime = HasSameStorageOrderAsArgType\n                             ? int(inner_stride_at_compile_time<ArgType>::ret)\n                             : int(outer_stride_at_compile_time<ArgType>::ret),\n    OuterStrideAtCompileTime = HasSameStorageOrderAsArgType\n                             ? int(outer_stride_at_compile_time<ArgType>::ret)\n                             : int(inner_stride_at_compile_time<ArgType>::ret),\n    MaskPacketAccessBit = (InnerStrideAtCompileTime == 1) ? PacketAccessBit : 0,\n    \n    FlagsLinearAccessBit = (RowsAtCompileTime == 1 || ColsAtCompileTime == 1 || (InnerPanel && (evaluator<ArgType>::Flags&LinearAccessBit))) ? LinearAccessBit : 0,    \n    FlagsRowMajorBit = XprType::Flags&RowMajorBit,\n    Flags0 = evaluator<ArgType>::Flags & ( (HereditaryBits & ~RowMajorBit) |\n                                           DirectAccessBit |\n                                           MaskPacketAccessBit),\n    Flags = Flags0 | FlagsLinearAccessBit | FlagsRowMajorBit,\n    \n    PacketAlignment = unpacket_traits<PacketScalar>::alignment,\n    Alignment0 = (InnerPanel && (OuterStrideAtCompileTime!=Dynamic) && (((OuterStrideAtCompileTime * int(sizeof(Scalar))) % int(PacketAlignment)) == 0)) ? int(PacketAlignment) : 0,\n    Alignment = EIGEN_PLAIN_ENUM_MIN(evaluator<ArgType>::Alignment, Alignment0)\n  };\n  typedef block_evaluator<ArgType, BlockRows, BlockCols, InnerPanel> block_evaluator_type;\n  EIGEN_DEVICE_FUNC explicit evaluator(const XprType& block) : block_evaluator_type(block)\n  {\n    EIGEN_INTERNAL_CHECK_COST_VALUE(CoeffReadCost);\n  }\n};\n\n// no direct-access => dispatch to a unary evaluator\ntemplate<typename ArgType, int BlockRows, int BlockCols, bool InnerPanel>\nstruct block_evaluator<ArgType, BlockRows, BlockCols, InnerPanel, /*HasDirectAccess*/ false>\n  : unary_evaluator<Block<ArgType, BlockRows, BlockCols, InnerPanel> >\n{\n  typedef Block<ArgType, BlockRows, BlockCols, InnerPanel> XprType;\n\n  EIGEN_DEVICE_FUNC explicit block_evaluator(const XprType& block)\n    : unary_evaluator<XprType>(block) \n  {}\n};\n\ntemplate<typename ArgType, int BlockRows, int BlockCols, bool InnerPanel>\nstruct unary_evaluator<Block<ArgType, BlockRows, BlockCols, InnerPanel>, IndexBased>\n  : evaluator_base<Block<ArgType, BlockRows, BlockCols, InnerPanel> >\n{\n  typedef Block<ArgType, BlockRows, BlockCols, InnerPanel> XprType;\n\n  EIGEN_DEVICE_FUNC explicit unary_evaluator(const XprType& block)\n    : m_argImpl(block.nestedExpression()), \n      m_startRow(block.startRow()), \n      m_startCol(block.startCol()) \n  { }\n \n  typedef typename XprType::Scalar Scalar;\n  typedef typename XprType::CoeffReturnType CoeffReturnType;\n\n  enum {\n    RowsAtCompileTime = XprType::RowsAtCompileTime\n  };\n \n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  CoeffReturnType coeff(Index row, Index col) const\n  { \n    return m_argImpl.coeff(m_startRow.value() + row, m_startCol.value() + col); \n  }\n  \n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  CoeffReturnType coeff(Index index) const\n  { \n    return coeff(RowsAtCompileTime == 1 ? 0 : index, RowsAtCompileTime == 1 ? index : 0);\n  }\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  Scalar& coeffRef(Index row, Index col)\n  { \n    return m_argImpl.coeffRef(m_startRow.value() + row, m_startCol.value() + col); \n  }\n  \n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  Scalar& coeffRef(Index index)\n  { \n    return coeffRef(RowsAtCompileTime == 1 ? 0 : index, RowsAtCompileTime == 1 ? index : 0);\n  }\n \n  template<int LoadMode, typename PacketType>\n  EIGEN_STRONG_INLINE\n  PacketType packet(Index row, Index col) const \n  { \n    return m_argImpl.template packet<LoadMode,PacketType>(m_startRow.value() + row, m_startCol.value() + col); \n  }\n\n  template<int LoadMode, typename PacketType>\n  EIGEN_STRONG_INLINE\n  PacketType packet(Index index) const \n  { \n    return packet<LoadMode,PacketType>(RowsAtCompileTime == 1 ? 0 : index,\n                                       RowsAtCompileTime == 1 ? index : 0);\n  }\n  \n  template<int StoreMode, typename PacketType>\n  EIGEN_STRONG_INLINE\n  void writePacket(Index row, Index col, const PacketType& x) \n  {\n    return m_argImpl.template writePacket<StoreMode,PacketType>(m_startRow.value() + row, m_startCol.value() + col, x); \n  }\n  \n  template<int StoreMode, typename PacketType>\n  EIGEN_STRONG_INLINE\n  void writePacket(Index index, const PacketType& x) \n  {\n    return writePacket<StoreMode,PacketType>(RowsAtCompileTime == 1 ? 0 : index,\n                                             RowsAtCompileTime == 1 ? index : 0,\n                                             x);\n  }\n \nprotected:\n  evaluator<ArgType> m_argImpl;\n  const variable_if_dynamic<Index, (ArgType::RowsAtCompileTime == 1 && BlockRows==1) ? 0 : Dynamic> m_startRow;\n  const variable_if_dynamic<Index, (ArgType::ColsAtCompileTime == 1 && BlockCols==1) ? 0 : Dynamic> m_startCol;\n};\n\n// TODO: This evaluator does not actually use the child evaluator; \n// all action is via the data() as returned by the Block expression.\n\ntemplate<typename ArgType, int BlockRows, int BlockCols, bool InnerPanel> \nstruct block_evaluator<ArgType, BlockRows, BlockCols, InnerPanel, /* HasDirectAccess */ true>\n  : mapbase_evaluator<Block<ArgType, BlockRows, BlockCols, InnerPanel>,\n                      typename Block<ArgType, BlockRows, BlockCols, InnerPanel>::PlainObject>\n{\n  typedef Block<ArgType, BlockRows, BlockCols, InnerPanel> XprType;\n  typedef typename XprType::Scalar Scalar;\n\n  EIGEN_DEVICE_FUNC explicit block_evaluator(const XprType& block)\n    : mapbase_evaluator<XprType, typename XprType::PlainObject>(block) \n  {\n    // TODO: for the 3.3 release, this should be turned to an internal assertion, but let's keep it as is for the beta lifetime\n    eigen_assert(((internal::UIntPtr(block.data()) % EIGEN_PLAIN_ENUM_MAX(1,evaluator<XprType>::Alignment)) == 0) && \"data is not aligned\");\n  }\n};\n\n\n// -------------------- Select --------------------\n// NOTE shall we introduce a ternary_evaluator?\n\n// TODO enable vectorization for Select\ntemplate<typename ConditionMatrixType, typename ThenMatrixType, typename ElseMatrixType>\nstruct evaluator<Select<ConditionMatrixType, ThenMatrixType, ElseMatrixType> >\n  : evaluator_base<Select<ConditionMatrixType, ThenMatrixType, ElseMatrixType> >\n{\n  typedef Select<ConditionMatrixType, ThenMatrixType, ElseMatrixType> XprType;\n  enum {\n    CoeffReadCost = evaluator<ConditionMatrixType>::CoeffReadCost\n                  + EIGEN_PLAIN_ENUM_MAX(evaluator<ThenMatrixType>::CoeffReadCost,\n                                         evaluator<ElseMatrixType>::CoeffReadCost),\n\n    Flags = (unsigned int)evaluator<ThenMatrixType>::Flags & evaluator<ElseMatrixType>::Flags & HereditaryBits,\n    \n    Alignment = EIGEN_PLAIN_ENUM_MIN(evaluator<ThenMatrixType>::Alignment, evaluator<ElseMatrixType>::Alignment)\n  };\n\n  EIGEN_DEVICE_FUNC explicit evaluator(const XprType& select)\n    : m_conditionImpl(select.conditionMatrix()),\n      m_thenImpl(select.thenMatrix()),\n      m_elseImpl(select.elseMatrix())\n  {\n    EIGEN_INTERNAL_CHECK_COST_VALUE(CoeffReadCost);\n  }\n \n  typedef typename XprType::CoeffReturnType CoeffReturnType;\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  CoeffReturnType coeff(Index row, Index col) const\n  {\n    if (m_conditionImpl.coeff(row, col))\n      return m_thenImpl.coeff(row, col);\n    else\n      return m_elseImpl.coeff(row, col);\n  }\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  CoeffReturnType coeff(Index index) const\n  {\n    if (m_conditionImpl.coeff(index))\n      return m_thenImpl.coeff(index);\n    else\n      return m_elseImpl.coeff(index);\n  }\n \nprotected:\n  evaluator<ConditionMatrixType> m_conditionImpl;\n  evaluator<ThenMatrixType> m_thenImpl;\n  evaluator<ElseMatrixType> m_elseImpl;\n};\n\n\n// -------------------- Replicate --------------------\n\ntemplate<typename ArgType, int RowFactor, int ColFactor> \nstruct unary_evaluator<Replicate<ArgType, RowFactor, ColFactor> >\n  : evaluator_base<Replicate<ArgType, RowFactor, ColFactor> >\n{\n  typedef Replicate<ArgType, RowFactor, ColFactor> XprType;\n  typedef typename XprType::CoeffReturnType CoeffReturnType;\n  enum {\n    Factor = (RowFactor==Dynamic || ColFactor==Dynamic) ? Dynamic : RowFactor*ColFactor\n  };\n  typedef typename internal::nested_eval<ArgType,Factor>::type ArgTypeNested;\n  typedef typename internal::remove_all<ArgTypeNested>::type ArgTypeNestedCleaned;\n  \n  enum {\n    CoeffReadCost = evaluator<ArgTypeNestedCleaned>::CoeffReadCost,\n    LinearAccessMask = XprType::IsVectorAtCompileTime ? LinearAccessBit : 0,\n    Flags = (evaluator<ArgTypeNestedCleaned>::Flags & (HereditaryBits|LinearAccessMask) & ~RowMajorBit) | (traits<XprType>::Flags & RowMajorBit),\n    \n    Alignment = evaluator<ArgTypeNestedCleaned>::Alignment\n  };\n\n  EIGEN_DEVICE_FUNC explicit unary_evaluator(const XprType& replicate)\n    : m_arg(replicate.nestedExpression()),\n      m_argImpl(m_arg),\n      m_rows(replicate.nestedExpression().rows()),\n      m_cols(replicate.nestedExpression().cols())\n  {}\n \n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  CoeffReturnType coeff(Index row, Index col) const\n  {\n    // try to avoid using modulo; this is a pure optimization strategy\n    const Index actual_row = internal::traits<XprType>::RowsAtCompileTime==1 ? 0\n                           : RowFactor==1 ? row\n                           : row % m_rows.value();\n    const Index actual_col = internal::traits<XprType>::ColsAtCompileTime==1 ? 0\n                           : ColFactor==1 ? col\n                           : col % m_cols.value();\n    \n    return m_argImpl.coeff(actual_row, actual_col);\n  }\n  \n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  CoeffReturnType coeff(Index index) const\n  {\n    // try to avoid using modulo; this is a pure optimization strategy\n    const Index actual_index = internal::traits<XprType>::RowsAtCompileTime==1\n                                  ? (ColFactor==1 ?  index : index%m_cols.value())\n                                  : (RowFactor==1 ?  index : index%m_rows.value());\n    \n    return m_argImpl.coeff(actual_index);\n  }\n\n  template<int LoadMode, typename PacketType>\n  EIGEN_STRONG_INLINE\n  PacketType packet(Index row, Index col) const\n  {\n    const Index actual_row = internal::traits<XprType>::RowsAtCompileTime==1 ? 0\n                           : RowFactor==1 ? row\n                           : row % m_rows.value();\n    const Index actual_col = internal::traits<XprType>::ColsAtCompileTime==1 ? 0\n                           : ColFactor==1 ? col\n                           : col % m_cols.value();\n\n    return m_argImpl.template packet<LoadMode,PacketType>(actual_row, actual_col);\n  }\n  \n  template<int LoadMode, typename PacketType>\n  EIGEN_STRONG_INLINE\n  PacketType packet(Index index) const\n  {\n    const Index actual_index = internal::traits<XprType>::RowsAtCompileTime==1\n                                  ? (ColFactor==1 ?  index : index%m_cols.value())\n                                  : (RowFactor==1 ?  index : index%m_rows.value());\n\n    return m_argImpl.template packet<LoadMode,PacketType>(actual_index);\n  }\n \nprotected:\n  const ArgTypeNested m_arg;\n  evaluator<ArgTypeNestedCleaned> m_argImpl;\n  const variable_if_dynamic<Index, ArgType::RowsAtCompileTime> m_rows;\n  const variable_if_dynamic<Index, ArgType::ColsAtCompileTime> m_cols;\n};\n\n\n// -------------------- PartialReduxExpr --------------------\n\ntemplate< typename ArgType, typename MemberOp, int Direction>\nstruct evaluator<PartialReduxExpr<ArgType, MemberOp, Direction> >\n  : evaluator_base<PartialReduxExpr<ArgType, MemberOp, Direction> >\n{\n  typedef PartialReduxExpr<ArgType, MemberOp, Direction> XprType;\n  typedef typename internal::nested_eval<ArgType,1>::type ArgTypeNested;\n  typedef typename internal::remove_all<ArgTypeNested>::type ArgTypeNestedCleaned;\n  typedef typename ArgType::Scalar InputScalar;\n  typedef typename XprType::Scalar Scalar;\n  enum {\n    TraversalSize = Direction==int(Vertical) ? int(ArgType::RowsAtCompileTime) :  int(ArgType::ColsAtCompileTime)\n  };\n  typedef typename MemberOp::template Cost<InputScalar,int(TraversalSize)> CostOpType;\n  enum {\n    CoeffReadCost = TraversalSize==Dynamic ? HugeCost\n                  : TraversalSize * evaluator<ArgType>::CoeffReadCost + int(CostOpType::value),\n    \n    Flags = (traits<XprType>::Flags&RowMajorBit) | (evaluator<ArgType>::Flags&(HereditaryBits&(~RowMajorBit))) | LinearAccessBit,\n    \n    Alignment = 0 // FIXME this will need to be improved once PartialReduxExpr is vectorized\n  };\n\n  EIGEN_DEVICE_FUNC explicit evaluator(const XprType xpr)\n    : m_arg(xpr.nestedExpression()), m_functor(xpr.functor())\n  {\n    EIGEN_INTERNAL_CHECK_COST_VALUE(TraversalSize==Dynamic ? HugeCost : int(CostOpType::value));\n    EIGEN_INTERNAL_CHECK_COST_VALUE(CoeffReadCost);\n  }\n\n  typedef typename XprType::CoeffReturnType CoeffReturnType;\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  const Scalar coeff(Index i, Index j) const\n  {\n    if (Direction==Vertical)\n      return m_functor(m_arg.col(j));\n    else\n      return m_functor(m_arg.row(i));\n  }\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  const Scalar coeff(Index index) const\n  {\n    if (Direction==Vertical)\n      return m_functor(m_arg.col(index));\n    else\n      return m_functor(m_arg.row(index));\n  }\n\nprotected:\n  typename internal::add_const_on_value_type<ArgTypeNested>::type m_arg;\n  const MemberOp m_functor;\n};\n\n\n// -------------------- MatrixWrapper and ArrayWrapper --------------------\n//\n// evaluator_wrapper_base<T> is a common base class for the\n// MatrixWrapper and ArrayWrapper evaluators.\n\ntemplate<typename XprType>\nstruct evaluator_wrapper_base\n  : evaluator_base<XprType>\n{\n  typedef typename remove_all<typename XprType::NestedExpressionType>::type ArgType;\n  enum {\n    CoeffReadCost = evaluator<ArgType>::CoeffReadCost,\n    Flags = evaluator<ArgType>::Flags,\n    Alignment = evaluator<ArgType>::Alignment\n  };\n\n  EIGEN_DEVICE_FUNC explicit evaluator_wrapper_base(const ArgType& arg) : m_argImpl(arg) {}\n\n  typedef typename ArgType::Scalar Scalar;\n  typedef typename ArgType::CoeffReturnType CoeffReturnType;\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  CoeffReturnType coeff(Index row, Index col) const\n  {\n    return m_argImpl.coeff(row, col);\n  }\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  CoeffReturnType coeff(Index index) const\n  {\n    return m_argImpl.coeff(index);\n  }\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  Scalar& coeffRef(Index row, Index col)\n  {\n    return m_argImpl.coeffRef(row, col);\n  }\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  Scalar& coeffRef(Index index)\n  {\n    return m_argImpl.coeffRef(index);\n  }\n\n  template<int LoadMode, typename PacketType>\n  EIGEN_STRONG_INLINE\n  PacketType packet(Index row, Index col) const\n  {\n    return m_argImpl.template packet<LoadMode,PacketType>(row, col);\n  }\n\n  template<int LoadMode, typename PacketType>\n  EIGEN_STRONG_INLINE\n  PacketType packet(Index index) const\n  {\n    return m_argImpl.template packet<LoadMode,PacketType>(index);\n  }\n\n  template<int StoreMode, typename PacketType>\n  EIGEN_STRONG_INLINE\n  void writePacket(Index row, Index col, const PacketType& x)\n  {\n    m_argImpl.template writePacket<StoreMode>(row, col, x);\n  }\n\n  template<int StoreMode, typename PacketType>\n  EIGEN_STRONG_INLINE\n  void writePacket(Index index, const PacketType& x)\n  {\n    m_argImpl.template writePacket<StoreMode>(index, x);\n  }\n\nprotected:\n  evaluator<ArgType> m_argImpl;\n};\n\ntemplate<typename TArgType>\nstruct unary_evaluator<MatrixWrapper<TArgType> >\n  : evaluator_wrapper_base<MatrixWrapper<TArgType> >\n{\n  typedef MatrixWrapper<TArgType> XprType;\n\n  EIGEN_DEVICE_FUNC explicit unary_evaluator(const XprType& wrapper)\n    : evaluator_wrapper_base<MatrixWrapper<TArgType> >(wrapper.nestedExpression())\n  { }\n};\n\ntemplate<typename TArgType>\nstruct unary_evaluator<ArrayWrapper<TArgType> >\n  : evaluator_wrapper_base<ArrayWrapper<TArgType> >\n{\n  typedef ArrayWrapper<TArgType> XprType;\n\n  EIGEN_DEVICE_FUNC explicit unary_evaluator(const XprType& wrapper)\n    : evaluator_wrapper_base<ArrayWrapper<TArgType> >(wrapper.nestedExpression())\n  { }\n};\n\n\n// -------------------- Reverse --------------------\n\n// defined in Reverse.h:\ntemplate<typename PacketType, bool ReversePacket> struct reverse_packet_cond;\n\ntemplate<typename ArgType, int Direction>\nstruct unary_evaluator<Reverse<ArgType, Direction> >\n  : evaluator_base<Reverse<ArgType, Direction> >\n{\n  typedef Reverse<ArgType, Direction> XprType;\n  typedef typename XprType::Scalar Scalar;\n  typedef typename XprType::CoeffReturnType CoeffReturnType;\n\n  enum {\n    IsRowMajor = XprType::IsRowMajor,\n    IsColMajor = !IsRowMajor,\n    ReverseRow = (Direction == Vertical)   || (Direction == BothDirections),\n    ReverseCol = (Direction == Horizontal) || (Direction == BothDirections),\n    ReversePacket = (Direction == BothDirections)\n                    || ((Direction == Vertical)   && IsColMajor)\n                    || ((Direction == Horizontal) && IsRowMajor),\n                    \n    CoeffReadCost = evaluator<ArgType>::CoeffReadCost,\n    \n    // let's enable LinearAccess only with vectorization because of the product overhead\n    // FIXME enable DirectAccess with negative strides?\n    Flags0 = evaluator<ArgType>::Flags,\n    LinearAccess = ( (Direction==BothDirections) && (int(Flags0)&PacketAccessBit) )\n                  || ((ReverseRow && XprType::ColsAtCompileTime==1) || (ReverseCol && XprType::RowsAtCompileTime==1))\n                 ? LinearAccessBit : 0,\n\n    Flags = int(Flags0) & (HereditaryBits | PacketAccessBit | LinearAccess),\n    \n    Alignment = 0 // FIXME in some rare cases, Alignment could be preserved, like a Vector4f.\n  };\n\n  EIGEN_DEVICE_FUNC explicit unary_evaluator(const XprType& reverse)\n    : m_argImpl(reverse.nestedExpression()),\n      m_rows(ReverseRow ? reverse.nestedExpression().rows() : 1),\n      m_cols(ReverseCol ? reverse.nestedExpression().cols() : 1)\n  { }\n \n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  CoeffReturnType coeff(Index row, Index col) const\n  {\n    return m_argImpl.coeff(ReverseRow ? m_rows.value() - row - 1 : row,\n                           ReverseCol ? m_cols.value() - col - 1 : col);\n  }\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  CoeffReturnType coeff(Index index) const\n  {\n    return m_argImpl.coeff(m_rows.value() * m_cols.value() - index - 1);\n  }\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  Scalar& coeffRef(Index row, Index col)\n  {\n    return m_argImpl.coeffRef(ReverseRow ? m_rows.value() - row - 1 : row,\n                              ReverseCol ? m_cols.value() - col - 1 : col);\n  }\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  Scalar& coeffRef(Index index)\n  {\n    return m_argImpl.coeffRef(m_rows.value() * m_cols.value() - index - 1);\n  }\n\n  template<int LoadMode, typename PacketType>\n  EIGEN_STRONG_INLINE\n  PacketType packet(Index row, Index col) const\n  {\n    enum {\n      PacketSize = unpacket_traits<PacketType>::size,\n      OffsetRow  = ReverseRow && IsColMajor ? PacketSize : 1,\n      OffsetCol  = ReverseCol && IsRowMajor ? PacketSize : 1\n    };\n    typedef internal::reverse_packet_cond<PacketType,ReversePacket> reverse_packet;\n    return reverse_packet::run(m_argImpl.template packet<LoadMode,PacketType>(\n                                  ReverseRow ? m_rows.value() - row - OffsetRow : row,\n                                  ReverseCol ? m_cols.value() - col - OffsetCol : col));\n  }\n\n  template<int LoadMode, typename PacketType>\n  EIGEN_STRONG_INLINE\n  PacketType packet(Index index) const\n  {\n    enum { PacketSize = unpacket_traits<PacketType>::size };\n    return preverse(m_argImpl.template packet<LoadMode,PacketType>(m_rows.value() * m_cols.value() - index - PacketSize));\n  }\n\n  template<int LoadMode, typename PacketType>\n  EIGEN_STRONG_INLINE\n  void writePacket(Index row, Index col, const PacketType& x)\n  {\n    // FIXME we could factorize some code with packet(i,j)\n    enum {\n      PacketSize = unpacket_traits<PacketType>::size,\n      OffsetRow  = ReverseRow && IsColMajor ? PacketSize : 1,\n      OffsetCol  = ReverseCol && IsRowMajor ? PacketSize : 1\n    };\n    typedef internal::reverse_packet_cond<PacketType,ReversePacket> reverse_packet;\n    m_argImpl.template writePacket<LoadMode>(\n                                  ReverseRow ? m_rows.value() - row - OffsetRow : row,\n                                  ReverseCol ? m_cols.value() - col - OffsetCol : col,\n                                  reverse_packet::run(x));\n  }\n\n  template<int LoadMode, typename PacketType>\n  EIGEN_STRONG_INLINE\n  void writePacket(Index index, const PacketType& x)\n  {\n    enum { PacketSize = unpacket_traits<PacketType>::size };\n    m_argImpl.template writePacket<LoadMode>\n      (m_rows.value() * m_cols.value() - index - PacketSize, preverse(x));\n  }\n \nprotected:\n  evaluator<ArgType> m_argImpl;\n\n  // If we do not reverse rows, then we do not need to know the number of rows; same for columns\n  // Nonetheless, in this case it is important to set to 1 such that the coeff(index) method works fine for vectors.\n  const variable_if_dynamic<Index, ReverseRow ? ArgType::RowsAtCompileTime : 1> m_rows;\n  const variable_if_dynamic<Index, ReverseCol ? ArgType::ColsAtCompileTime : 1> m_cols;\n};\n\n\n// -------------------- Diagonal --------------------\n\ntemplate<typename ArgType, int DiagIndex>\nstruct evaluator<Diagonal<ArgType, DiagIndex> >\n  : evaluator_base<Diagonal<ArgType, DiagIndex> >\n{\n  typedef Diagonal<ArgType, DiagIndex> XprType;\n  \n  enum {\n    CoeffReadCost = evaluator<ArgType>::CoeffReadCost,\n    \n    Flags = (unsigned int)(evaluator<ArgType>::Flags & (HereditaryBits | DirectAccessBit) & ~RowMajorBit) | LinearAccessBit,\n    \n    Alignment = 0\n  };\n\n  EIGEN_DEVICE_FUNC explicit evaluator(const XprType& diagonal)\n    : m_argImpl(diagonal.nestedExpression()),\n      m_index(diagonal.index())\n  { }\n \n  typedef typename XprType::Scalar Scalar;\n  // FIXME having to check whether ArgType is sparse here i not very nice.\n  typedef typename internal::conditional<!internal::is_same<typename ArgType::StorageKind,Sparse>::value,\n                                         typename XprType::CoeffReturnType,Scalar>::type CoeffReturnType;\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  CoeffReturnType coeff(Index row, Index) const\n  {\n    return m_argImpl.coeff(row + rowOffset(), row + colOffset());\n  }\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  CoeffReturnType coeff(Index index) const\n  {\n    return m_argImpl.coeff(index + rowOffset(), index + colOffset());\n  }\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  Scalar& coeffRef(Index row, Index)\n  {\n    return m_argImpl.coeffRef(row + rowOffset(), row + colOffset());\n  }\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  Scalar& coeffRef(Index index)\n  {\n    return m_argImpl.coeffRef(index + rowOffset(), index + colOffset());\n  }\n\nprotected:\n  evaluator<ArgType> m_argImpl;\n  const internal::variable_if_dynamicindex<Index, XprType::DiagIndex> m_index;\n\nprivate:\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE Index rowOffset() const { return m_index.value() > 0 ? 0 : -m_index.value(); }\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE Index colOffset() const { return m_index.value() > 0 ? m_index.value() : 0; }\n};\n\n\n//----------------------------------------------------------------------\n// deprecated code\n//----------------------------------------------------------------------\n\n// -------------------- EvalToTemp --------------------\n\n// expression class for evaluating nested expression to a temporary\n\ntemplate<typename ArgType> class EvalToTemp;\n\ntemplate<typename ArgType>\nstruct traits<EvalToTemp<ArgType> >\n  : public traits<ArgType>\n{ };\n\ntemplate<typename ArgType>\nclass EvalToTemp\n  : public dense_xpr_base<EvalToTemp<ArgType> >::type\n{\n public:\n \n  typedef typename dense_xpr_base<EvalToTemp>::type Base;\n  EIGEN_GENERIC_PUBLIC_INTERFACE(EvalToTemp)\n \n  explicit EvalToTemp(const ArgType& arg)\n    : m_arg(arg)\n  { }\n \n  const ArgType& arg() const\n  {\n    return m_arg;\n  }\n\n  Index rows() const \n  {\n    return m_arg.rows();\n  }\n\n  Index cols() const \n  {\n    return m_arg.cols();\n  }\n\n private:\n  const ArgType& m_arg;\n};\n \ntemplate<typename ArgType>\nstruct evaluator<EvalToTemp<ArgType> >\n  : public evaluator<typename ArgType::PlainObject>\n{\n  typedef EvalToTemp<ArgType>                   XprType;\n  typedef typename ArgType::PlainObject         PlainObject;\n  typedef evaluator<PlainObject> Base;\n  \n  EIGEN_DEVICE_FUNC explicit evaluator(const XprType& xpr)\n    : m_result(xpr.arg())\n  {\n    ::new (static_cast<Base*>(this)) Base(m_result);\n  }\n\n  // This constructor is used when nesting an EvalTo evaluator in another evaluator\n  EIGEN_DEVICE_FUNC evaluator(const ArgType& arg)\n    : m_result(arg)\n  {\n    ::new (static_cast<Base*>(this)) Base(m_result);\n  }\n\nprotected:\n  PlainObject m_result;\n};\n\n} // namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_COREEVALUATORS_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/CoreIterators.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2014 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_COREITERATORS_H\n#define EIGEN_COREITERATORS_H\n\nnamespace Eigen { \n\n/* This file contains the respective InnerIterator definition of the expressions defined in Eigen/Core\n */\n\nnamespace internal {\n\ntemplate<typename XprType, typename EvaluatorKind>\nclass inner_iterator_selector;\n\n}\n\n/** \\class InnerIterator\n  * \\brief An InnerIterator allows to loop over the element of any matrix expression.\n  * \n  * \\warning To be used with care because an evaluator is constructed every time an InnerIterator iterator is constructed.\n  * \n  * TODO: add a usage example\n  */\ntemplate<typename XprType>\nclass InnerIterator\n{\nprotected:\n  typedef internal::inner_iterator_selector<XprType, typename internal::evaluator_traits<XprType>::Kind> IteratorType;\n  typedef internal::evaluator<XprType> EvaluatorType;\n  typedef typename internal::traits<XprType>::Scalar Scalar;\npublic:\n  /** Construct an iterator over the \\a outerId -th row or column of \\a xpr */\n  InnerIterator(const XprType &xpr, const Index &outerId)\n    : m_eval(xpr), m_iter(m_eval, outerId, xpr.innerSize())\n  {}\n  \n  /// \\returns the value of the current coefficient.\n  EIGEN_STRONG_INLINE Scalar value() const          { return m_iter.value(); }\n  /** Increment the iterator \\c *this to the next non-zero coefficient.\n    * Explicit zeros are not skipped over. To skip explicit zeros, see class SparseView\n    */\n  EIGEN_STRONG_INLINE InnerIterator& operator++()   { m_iter.operator++(); return *this; }\n  /// \\returns the column or row index of the current coefficient.\n  EIGEN_STRONG_INLINE Index index() const           { return m_iter.index(); }\n  /// \\returns the row index of the current coefficient.\n  EIGEN_STRONG_INLINE Index row() const             { return m_iter.row(); }\n  /// \\returns the column index of the current coefficient.\n  EIGEN_STRONG_INLINE Index col() const             { return m_iter.col(); }\n  /// \\returns \\c true if the iterator \\c *this still references a valid coefficient.\n  EIGEN_STRONG_INLINE operator bool() const         { return m_iter; }\n  \nprotected:\n  EvaluatorType m_eval;\n  IteratorType m_iter;\nprivate:\n  // If you get here, then you're not using the right InnerIterator type, e.g.:\n  //   SparseMatrix<double,RowMajor> A;\n  //   SparseMatrix<double>::InnerIterator it(A,0);\n  template<typename T> InnerIterator(const EigenBase<T>&,Index outer);\n};\n\nnamespace internal {\n\n// Generic inner iterator implementation for dense objects\ntemplate<typename XprType>\nclass inner_iterator_selector<XprType, IndexBased>\n{\nprotected:\n  typedef evaluator<XprType> EvaluatorType;\n  typedef typename traits<XprType>::Scalar Scalar;\n  enum { IsRowMajor = (XprType::Flags&RowMajorBit)==RowMajorBit };\n  \npublic:\n  EIGEN_STRONG_INLINE inner_iterator_selector(const EvaluatorType &eval, const Index &outerId, const Index &innerSize)\n    : m_eval(eval), m_inner(0), m_outer(outerId), m_end(innerSize)\n  {}\n\n  EIGEN_STRONG_INLINE Scalar value() const\n  {\n    return (IsRowMajor) ? m_eval.coeff(m_outer, m_inner)\n                        : m_eval.coeff(m_inner, m_outer);\n  }\n\n  EIGEN_STRONG_INLINE inner_iterator_selector& operator++() { m_inner++; return *this; }\n\n  EIGEN_STRONG_INLINE Index index() const { return m_inner; }\n  inline Index row() const { return IsRowMajor ? m_outer : index(); }\n  inline Index col() const { return IsRowMajor ? index() : m_outer; }\n\n  EIGEN_STRONG_INLINE operator bool() const { return m_inner < m_end && m_inner>=0; }\n\nprotected:\n  const EvaluatorType& m_eval;\n  Index m_inner;\n  const Index m_outer;\n  const Index m_end;\n};\n\n// For iterator-based evaluator, inner-iterator is already implemented as\n// evaluator<>::InnerIterator\ntemplate<typename XprType>\nclass inner_iterator_selector<XprType, IteratorBased>\n : public evaluator<XprType>::InnerIterator\n{\nprotected:\n  typedef typename evaluator<XprType>::InnerIterator Base;\n  typedef evaluator<XprType> EvaluatorType;\n  \npublic:\n  EIGEN_STRONG_INLINE inner_iterator_selector(const EvaluatorType &eval, const Index &outerId, const Index &/*innerSize*/)\n    : Base(eval, outerId)\n  {}  \n};\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_COREITERATORS_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/CwiseBinaryOp.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2014 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2006-2008 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_CWISE_BINARY_OP_H\n#define EIGEN_CWISE_BINARY_OP_H\n\nnamespace Eigen {\n\nnamespace internal {\ntemplate<typename BinaryOp, typename Lhs, typename Rhs>\nstruct traits<CwiseBinaryOp<BinaryOp, Lhs, Rhs> >\n{\n  // we must not inherit from traits<Lhs> since it has\n  // the potential to cause problems with MSVC\n  typedef typename remove_all<Lhs>::type Ancestor;\n  typedef typename traits<Ancestor>::XprKind XprKind;\n  enum {\n    RowsAtCompileTime = traits<Ancestor>::RowsAtCompileTime,\n    ColsAtCompileTime = traits<Ancestor>::ColsAtCompileTime,\n    MaxRowsAtCompileTime = traits<Ancestor>::MaxRowsAtCompileTime,\n    MaxColsAtCompileTime = traits<Ancestor>::MaxColsAtCompileTime\n  };\n\n  // even though we require Lhs and Rhs to have the same scalar type (see CwiseBinaryOp constructor),\n  // we still want to handle the case when the result type is different.\n  typedef typename result_of<\n                     BinaryOp(\n                       const typename Lhs::Scalar&,\n                       const typename Rhs::Scalar&\n                     )\n                   >::type Scalar;\n  typedef typename cwise_promote_storage_type<typename traits<Lhs>::StorageKind,\n                                              typename traits<Rhs>::StorageKind,\n                                              BinaryOp>::ret StorageKind;\n  typedef typename promote_index_type<typename traits<Lhs>::StorageIndex,\n                                      typename traits<Rhs>::StorageIndex>::type StorageIndex;\n  typedef typename Lhs::Nested LhsNested;\n  typedef typename Rhs::Nested RhsNested;\n  typedef typename remove_reference<LhsNested>::type _LhsNested;\n  typedef typename remove_reference<RhsNested>::type _RhsNested;\n  enum {\n    Flags = _LhsNested::Flags & RowMajorBit\n  };\n};\n} // end namespace internal\n\ntemplate<typename BinaryOp, typename Lhs, typename Rhs, typename StorageKind>\nclass CwiseBinaryOpImpl;\n\n/** \\class CwiseBinaryOp\n  * \\ingroup Core_Module\n  *\n  * \\brief Generic expression where a coefficient-wise binary operator is applied to two expressions\n  *\n  * \\tparam BinaryOp template functor implementing the operator\n  * \\tparam LhsType the type of the left-hand side\n  * \\tparam RhsType the type of the right-hand side\n  *\n  * This class represents an expression  where a coefficient-wise binary operator is applied to two expressions.\n  * It is the return type of binary operators, by which we mean only those binary operators where\n  * both the left-hand side and the right-hand side are Eigen expressions.\n  * For example, the return type of matrix1+matrix2 is a CwiseBinaryOp.\n  *\n  * Most of the time, this is the only way that it is used, so you typically don't have to name\n  * CwiseBinaryOp types explicitly.\n  *\n  * \\sa MatrixBase::binaryExpr(const MatrixBase<OtherDerived> &,const CustomBinaryOp &) const, class CwiseUnaryOp, class CwiseNullaryOp\n  */\ntemplate<typename BinaryOp, typename LhsType, typename RhsType>\nclass CwiseBinaryOp : \n  public CwiseBinaryOpImpl<\n          BinaryOp, LhsType, RhsType,\n          typename internal::cwise_promote_storage_type<typename internal::traits<LhsType>::StorageKind,\n                                                        typename internal::traits<RhsType>::StorageKind,\n                                                        BinaryOp>::ret>,\n  internal::no_assignment_operator\n{\n  public:\n    \n    typedef typename internal::remove_all<BinaryOp>::type Functor;\n    typedef typename internal::remove_all<LhsType>::type Lhs;\n    typedef typename internal::remove_all<RhsType>::type Rhs;\n\n    typedef typename CwiseBinaryOpImpl<\n        BinaryOp, LhsType, RhsType,\n        typename internal::cwise_promote_storage_type<typename internal::traits<LhsType>::StorageKind,\n                                                      typename internal::traits<Rhs>::StorageKind,\n                                                      BinaryOp>::ret>::Base Base;\n    EIGEN_GENERIC_PUBLIC_INTERFACE(CwiseBinaryOp)\n\n    typedef typename internal::ref_selector<LhsType>::type LhsNested;\n    typedef typename internal::ref_selector<RhsType>::type RhsNested;\n    typedef typename internal::remove_reference<LhsNested>::type _LhsNested;\n    typedef typename internal::remove_reference<RhsNested>::type _RhsNested;\n\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE CwiseBinaryOp(const Lhs& aLhs, const Rhs& aRhs, const BinaryOp& func = BinaryOp())\n      : m_lhs(aLhs), m_rhs(aRhs), m_functor(func)\n    {\n      EIGEN_CHECK_BINARY_COMPATIBILIY(BinaryOp,typename Lhs::Scalar,typename Rhs::Scalar);\n      // require the sizes to match\n      EIGEN_STATIC_ASSERT_SAME_MATRIX_SIZE(Lhs, Rhs)\n      eigen_assert(aLhs.rows() == aRhs.rows() && aLhs.cols() == aRhs.cols());\n    }\n\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Index rows() const {\n      // return the fixed size type if available to enable compile time optimizations\n      if (internal::traits<typename internal::remove_all<LhsNested>::type>::RowsAtCompileTime==Dynamic)\n        return m_rhs.rows();\n      else\n        return m_lhs.rows();\n    }\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Index cols() const {\n      // return the fixed size type if available to enable compile time optimizations\n      if (internal::traits<typename internal::remove_all<LhsNested>::type>::ColsAtCompileTime==Dynamic)\n        return m_rhs.cols();\n      else\n        return m_lhs.cols();\n    }\n\n    /** \\returns the left hand side nested expression */\n    EIGEN_DEVICE_FUNC\n    const _LhsNested& lhs() const { return m_lhs; }\n    /** \\returns the right hand side nested expression */\n    EIGEN_DEVICE_FUNC\n    const _RhsNested& rhs() const { return m_rhs; }\n    /** \\returns the functor representing the binary operation */\n    EIGEN_DEVICE_FUNC\n    const BinaryOp& functor() const { return m_functor; }\n\n  protected:\n    LhsNested m_lhs;\n    RhsNested m_rhs;\n    const BinaryOp m_functor;\n};\n\n// Generic API dispatcher\ntemplate<typename BinaryOp, typename Lhs, typename Rhs, typename StorageKind>\nclass CwiseBinaryOpImpl\n  : public internal::generic_xpr_base<CwiseBinaryOp<BinaryOp, Lhs, Rhs> >::type\n{\npublic:\n  typedef typename internal::generic_xpr_base<CwiseBinaryOp<BinaryOp, Lhs, Rhs> >::type Base;\n};\n\n/** replaces \\c *this by \\c *this - \\a other.\n  *\n  * \\returns a reference to \\c *this\n  */\ntemplate<typename Derived>\ntemplate<typename OtherDerived>\nEIGEN_STRONG_INLINE Derived &\nMatrixBase<Derived>::operator-=(const MatrixBase<OtherDerived> &other)\n{\n  call_assignment(derived(), other.derived(), internal::sub_assign_op<Scalar,typename OtherDerived::Scalar>());\n  return derived();\n}\n\n/** replaces \\c *this by \\c *this + \\a other.\n  *\n  * \\returns a reference to \\c *this\n  */\ntemplate<typename Derived>\ntemplate<typename OtherDerived>\nEIGEN_STRONG_INLINE Derived &\nMatrixBase<Derived>::operator+=(const MatrixBase<OtherDerived>& other)\n{\n  call_assignment(derived(), other.derived(), internal::add_assign_op<Scalar,typename OtherDerived::Scalar>());\n  return derived();\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_CWISE_BINARY_OP_H\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/CwiseNullaryOp.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_CWISE_NULLARY_OP_H\n#define EIGEN_CWISE_NULLARY_OP_H\n\nnamespace Eigen {\n\nnamespace internal {\ntemplate<typename NullaryOp, typename PlainObjectType>\nstruct traits<CwiseNullaryOp<NullaryOp, PlainObjectType> > : traits<PlainObjectType>\n{\n  enum {\n    Flags = traits<PlainObjectType>::Flags & RowMajorBit\n  };\n};\n\n} // namespace internal\n\n/** \\class CwiseNullaryOp\n  * \\ingroup Core_Module\n  *\n  * \\brief Generic expression of a matrix where all coefficients are defined by a functor\n  *\n  * \\tparam NullaryOp template functor implementing the operator\n  * \\tparam PlainObjectType the underlying plain matrix/array type\n  *\n  * This class represents an expression of a generic nullary operator.\n  * It is the return type of the Ones(), Zero(), Constant(), Identity() and Random() methods,\n  * and most of the time this is the only way it is used.\n  *\n  * However, if you want to write a function returning such an expression, you\n  * will need to use this class.\n  *\n  * The functor NullaryOp must expose one of the following method:\n    <table class=\"manual\">\n    <tr            ><td>\\c operator()() </td><td>if the procedural generation does not depend on the coefficient entries (e.g., random numbers)</td></tr>\n    <tr class=\"alt\"><td>\\c operator()(Index i)</td><td>if the procedural generation makes sense for vectors only and that it depends on the coefficient index \\c i (e.g., linspace) </td></tr>\n    <tr            ><td>\\c operator()(Index i,Index j)</td><td>if the procedural generation depends on the matrix coordinates \\c i, \\c j (e.g., to generate a checkerboard with 0 and 1)</td></tr>\n    </table>\n  * It is also possible to expose the last two operators if the generation makes sense for matrices but can be optimized for vectors.\n  *\n  * See DenseBase::NullaryExpr(Index,const CustomNullaryOp&) for an example binding\n  * C++11 random number generators.\n  *\n  * A nullary expression can also be used to implement custom sophisticated matrix manipulations\n  * that cannot be covered by the existing set of natively supported matrix manipulations.\n  * See this \\ref TopicCustomizing_NullaryExpr \"page\" for some examples and additional explanations\n  * on the behavior of CwiseNullaryOp.\n  *\n  * \\sa class CwiseUnaryOp, class CwiseBinaryOp, DenseBase::NullaryExpr\n  */\ntemplate<typename NullaryOp, typename PlainObjectType>\nclass CwiseNullaryOp : public internal::dense_xpr_base< CwiseNullaryOp<NullaryOp, PlainObjectType> >::type, internal::no_assignment_operator\n{\n  public:\n\n    typedef typename internal::dense_xpr_base<CwiseNullaryOp>::type Base;\n    EIGEN_DENSE_PUBLIC_INTERFACE(CwiseNullaryOp)\n\n    EIGEN_DEVICE_FUNC\n    CwiseNullaryOp(Index rows, Index cols, const NullaryOp& func = NullaryOp())\n      : m_rows(rows), m_cols(cols), m_functor(func)\n    {\n      eigen_assert(rows >= 0\n            && (RowsAtCompileTime == Dynamic || RowsAtCompileTime == rows)\n            &&  cols >= 0\n            && (ColsAtCompileTime == Dynamic || ColsAtCompileTime == cols));\n    }\n\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Index rows() const { return m_rows.value(); }\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Index cols() const { return m_cols.value(); }\n\n    /** \\returns the functor representing the nullary operation */\n    EIGEN_DEVICE_FUNC\n    const NullaryOp& functor() const { return m_functor; }\n\n  protected:\n    const internal::variable_if_dynamic<Index, RowsAtCompileTime> m_rows;\n    const internal::variable_if_dynamic<Index, ColsAtCompileTime> m_cols;\n    const NullaryOp m_functor;\n};\n\n\n/** \\returns an expression of a matrix defined by a custom functor \\a func\n  *\n  * The parameters \\a rows and \\a cols are the number of rows and of columns of\n  * the returned matrix. Must be compatible with this MatrixBase type.\n  *\n  * This variant is meant to be used for dynamic-size matrix types. For fixed-size types,\n  * it is redundant to pass \\a rows and \\a cols as arguments, so Zero() should be used\n  * instead.\n  *\n  * The template parameter \\a CustomNullaryOp is the type of the functor.\n  *\n  * \\sa class CwiseNullaryOp\n  */\ntemplate<typename Derived>\ntemplate<typename CustomNullaryOp>\nEIGEN_STRONG_INLINE const CwiseNullaryOp<CustomNullaryOp, typename DenseBase<Derived>::PlainObject>\nDenseBase<Derived>::NullaryExpr(Index rows, Index cols, const CustomNullaryOp& func)\n{\n  return CwiseNullaryOp<CustomNullaryOp, PlainObject>(rows, cols, func);\n}\n\n/** \\returns an expression of a matrix defined by a custom functor \\a func\n  *\n  * The parameter \\a size is the size of the returned vector.\n  * Must be compatible with this MatrixBase type.\n  *\n  * \\only_for_vectors\n  *\n  * This variant is meant to be used for dynamic-size vector types. For fixed-size types,\n  * it is redundant to pass \\a size as argument, so Zero() should be used\n  * instead.\n  *\n  * The template parameter \\a CustomNullaryOp is the type of the functor.\n  *\n  * Here is an example with C++11 random generators: \\include random_cpp11.cpp\n  * Output: \\verbinclude random_cpp11.out\n  * \n  * \\sa class CwiseNullaryOp\n  */\ntemplate<typename Derived>\ntemplate<typename CustomNullaryOp>\nEIGEN_STRONG_INLINE const CwiseNullaryOp<CustomNullaryOp, typename DenseBase<Derived>::PlainObject>\nDenseBase<Derived>::NullaryExpr(Index size, const CustomNullaryOp& func)\n{\n  EIGEN_STATIC_ASSERT_VECTOR_ONLY(Derived)\n  if(RowsAtCompileTime == 1) return CwiseNullaryOp<CustomNullaryOp, PlainObject>(1, size, func);\n  else return CwiseNullaryOp<CustomNullaryOp, PlainObject>(size, 1, func);\n}\n\n/** \\returns an expression of a matrix defined by a custom functor \\a func\n  *\n  * This variant is only for fixed-size DenseBase types. For dynamic-size types, you\n  * need to use the variants taking size arguments.\n  *\n  * The template parameter \\a CustomNullaryOp is the type of the functor.\n  *\n  * \\sa class CwiseNullaryOp\n  */\ntemplate<typename Derived>\ntemplate<typename CustomNullaryOp>\nEIGEN_STRONG_INLINE const CwiseNullaryOp<CustomNullaryOp, typename DenseBase<Derived>::PlainObject>\nDenseBase<Derived>::NullaryExpr(const CustomNullaryOp& func)\n{\n  return CwiseNullaryOp<CustomNullaryOp, PlainObject>(RowsAtCompileTime, ColsAtCompileTime, func);\n}\n\n/** \\returns an expression of a constant matrix of value \\a value\n  *\n  * The parameters \\a rows and \\a cols are the number of rows and of columns of\n  * the returned matrix. Must be compatible with this DenseBase type.\n  *\n  * This variant is meant to be used for dynamic-size matrix types. For fixed-size types,\n  * it is redundant to pass \\a rows and \\a cols as arguments, so Zero() should be used\n  * instead.\n  *\n  * The template parameter \\a CustomNullaryOp is the type of the functor.\n  *\n  * \\sa class CwiseNullaryOp\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE const typename DenseBase<Derived>::ConstantReturnType\nDenseBase<Derived>::Constant(Index rows, Index cols, const Scalar& value)\n{\n  return DenseBase<Derived>::NullaryExpr(rows, cols, internal::scalar_constant_op<Scalar>(value));\n}\n\n/** \\returns an expression of a constant matrix of value \\a value\n  *\n  * The parameter \\a size is the size of the returned vector.\n  * Must be compatible with this DenseBase type.\n  *\n  * \\only_for_vectors\n  *\n  * This variant is meant to be used for dynamic-size vector types. For fixed-size types,\n  * it is redundant to pass \\a size as argument, so Zero() should be used\n  * instead.\n  *\n  * The template parameter \\a CustomNullaryOp is the type of the functor.\n  *\n  * \\sa class CwiseNullaryOp\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE const typename DenseBase<Derived>::ConstantReturnType\nDenseBase<Derived>::Constant(Index size, const Scalar& value)\n{\n  return DenseBase<Derived>::NullaryExpr(size, internal::scalar_constant_op<Scalar>(value));\n}\n\n/** \\returns an expression of a constant matrix of value \\a value\n  *\n  * This variant is only for fixed-size DenseBase types. For dynamic-size types, you\n  * need to use the variants taking size arguments.\n  *\n  * The template parameter \\a CustomNullaryOp is the type of the functor.\n  *\n  * \\sa class CwiseNullaryOp\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE const typename DenseBase<Derived>::ConstantReturnType\nDenseBase<Derived>::Constant(const Scalar& value)\n{\n  EIGEN_STATIC_ASSERT_FIXED_SIZE(Derived)\n  return DenseBase<Derived>::NullaryExpr(RowsAtCompileTime, ColsAtCompileTime, internal::scalar_constant_op<Scalar>(value));\n}\n\n/** \\deprecated because of accuracy loss. In Eigen 3.3, it is an alias for LinSpaced(Index,const Scalar&,const Scalar&)\n  *\n  * \\sa LinSpaced(Index,Scalar,Scalar), setLinSpaced(Index,const Scalar&,const Scalar&)\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE const typename DenseBase<Derived>::RandomAccessLinSpacedReturnType\nDenseBase<Derived>::LinSpaced(Sequential_t, Index size, const Scalar& low, const Scalar& high)\n{\n  EIGEN_STATIC_ASSERT_VECTOR_ONLY(Derived)\n  return DenseBase<Derived>::NullaryExpr(size, internal::linspaced_op<Scalar,PacketScalar>(low,high,size));\n}\n\n/** \\deprecated because of accuracy loss. In Eigen 3.3, it is an alias for LinSpaced(const Scalar&,const Scalar&)\n  *\n  * \\sa LinSpaced(Scalar,Scalar)\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE const typename DenseBase<Derived>::RandomAccessLinSpacedReturnType\nDenseBase<Derived>::LinSpaced(Sequential_t, const Scalar& low, const Scalar& high)\n{\n  EIGEN_STATIC_ASSERT_VECTOR_ONLY(Derived)\n  EIGEN_STATIC_ASSERT_FIXED_SIZE(Derived)\n  return DenseBase<Derived>::NullaryExpr(Derived::SizeAtCompileTime, internal::linspaced_op<Scalar,PacketScalar>(low,high,Derived::SizeAtCompileTime));\n}\n\n/**\n  * \\brief Sets a linearly spaced vector.\n  *\n  * The function generates 'size' equally spaced values in the closed interval [low,high].\n  * When size is set to 1, a vector of length 1 containing 'high' is returned.\n  *\n  * \\only_for_vectors\n  *\n  * Example: \\include DenseBase_LinSpaced.cpp\n  * Output: \\verbinclude DenseBase_LinSpaced.out\n  *\n  * For integer scalar types, an even spacing is possible if and only if the length of the range,\n  * i.e., \\c high-low is a scalar multiple of \\c size-1, or if \\c size is a scalar multiple of the\n  * number of values \\c high-low+1 (meaning each value can be repeated the same number of time).\n  * If one of these two considions is not satisfied, then \\c high is lowered to the largest value\n  * satisfying one of this constraint.\n  * Here are some examples:\n  *\n  * Example: \\include DenseBase_LinSpacedInt.cpp\n  * Output: \\verbinclude DenseBase_LinSpacedInt.out\n  *\n  * \\sa setLinSpaced(Index,const Scalar&,const Scalar&), CwiseNullaryOp\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE const typename DenseBase<Derived>::RandomAccessLinSpacedReturnType\nDenseBase<Derived>::LinSpaced(Index size, const Scalar& low, const Scalar& high)\n{\n  EIGEN_STATIC_ASSERT_VECTOR_ONLY(Derived)\n  return DenseBase<Derived>::NullaryExpr(size, internal::linspaced_op<Scalar,PacketScalar>(low,high,size));\n}\n\n/**\n  * \\copydoc DenseBase::LinSpaced(Index, const Scalar&, const Scalar&)\n  * Special version for fixed size types which does not require the size parameter.\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE const typename DenseBase<Derived>::RandomAccessLinSpacedReturnType\nDenseBase<Derived>::LinSpaced(const Scalar& low, const Scalar& high)\n{\n  EIGEN_STATIC_ASSERT_VECTOR_ONLY(Derived)\n  EIGEN_STATIC_ASSERT_FIXED_SIZE(Derived)\n  return DenseBase<Derived>::NullaryExpr(Derived::SizeAtCompileTime, internal::linspaced_op<Scalar,PacketScalar>(low,high,Derived::SizeAtCompileTime));\n}\n\n/** \\returns true if all coefficients in this matrix are approximately equal to \\a val, to within precision \\a prec */\ntemplate<typename Derived>\nbool DenseBase<Derived>::isApproxToConstant\n(const Scalar& val, const RealScalar& prec) const\n{\n  typename internal::nested_eval<Derived,1>::type self(derived());\n  for(Index j = 0; j < cols(); ++j)\n    for(Index i = 0; i < rows(); ++i)\n      if(!internal::isApprox(self.coeff(i, j), val, prec))\n        return false;\n  return true;\n}\n\n/** This is just an alias for isApproxToConstant().\n  *\n  * \\returns true if all coefficients in this matrix are approximately equal to \\a value, to within precision \\a prec */\ntemplate<typename Derived>\nbool DenseBase<Derived>::isConstant\n(const Scalar& val, const RealScalar& prec) const\n{\n  return isApproxToConstant(val, prec);\n}\n\n/** Alias for setConstant(): sets all coefficients in this expression to \\a val.\n  *\n  * \\sa setConstant(), Constant(), class CwiseNullaryOp\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE void DenseBase<Derived>::fill(const Scalar& val)\n{\n  setConstant(val);\n}\n\n/** Sets all coefficients in this expression to value \\a val.\n  *\n  * \\sa fill(), setConstant(Index,const Scalar&), setConstant(Index,Index,const Scalar&), setZero(), setOnes(), Constant(), class CwiseNullaryOp, setZero(), setOnes()\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE Derived& DenseBase<Derived>::setConstant(const Scalar& val)\n{\n  return derived() = Constant(rows(), cols(), val);\n}\n\n/** Resizes to the given \\a size, and sets all coefficients in this expression to the given value \\a val.\n  *\n  * \\only_for_vectors\n  *\n  * Example: \\include Matrix_setConstant_int.cpp\n  * Output: \\verbinclude Matrix_setConstant_int.out\n  *\n  * \\sa MatrixBase::setConstant(const Scalar&), setConstant(Index,Index,const Scalar&), class CwiseNullaryOp, MatrixBase::Constant(const Scalar&)\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE Derived&\nPlainObjectBase<Derived>::setConstant(Index size, const Scalar& val)\n{\n  resize(size);\n  return setConstant(val);\n}\n\n/** Resizes to the given size, and sets all coefficients in this expression to the given value \\a val.\n  *\n  * \\param rows the new number of rows\n  * \\param cols the new number of columns\n  * \\param val the value to which all coefficients are set\n  *\n  * Example: \\include Matrix_setConstant_int_int.cpp\n  * Output: \\verbinclude Matrix_setConstant_int_int.out\n  *\n  * \\sa MatrixBase::setConstant(const Scalar&), setConstant(Index,const Scalar&), class CwiseNullaryOp, MatrixBase::Constant(const Scalar&)\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE Derived&\nPlainObjectBase<Derived>::setConstant(Index rows, Index cols, const Scalar& val)\n{\n  resize(rows, cols);\n  return setConstant(val);\n}\n\n/**\n  * \\brief Sets a linearly spaced vector.\n  *\n  * The function generates 'size' equally spaced values in the closed interval [low,high].\n  * When size is set to 1, a vector of length 1 containing 'high' is returned.\n  *\n  * \\only_for_vectors\n  *\n  * Example: \\include DenseBase_setLinSpaced.cpp\n  * Output: \\verbinclude DenseBase_setLinSpaced.out\n  *\n  * For integer scalar types, do not miss the explanations on the definition\n  * of \\link LinSpaced(Index,const Scalar&,const Scalar&) even spacing \\endlink.\n  *\n  * \\sa LinSpaced(Index,const Scalar&,const Scalar&), CwiseNullaryOp\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE Derived& DenseBase<Derived>::setLinSpaced(Index newSize, const Scalar& low, const Scalar& high)\n{\n  EIGEN_STATIC_ASSERT_VECTOR_ONLY(Derived)\n  return derived() = Derived::NullaryExpr(newSize, internal::linspaced_op<Scalar,PacketScalar>(low,high,newSize));\n}\n\n/**\n  * \\brief Sets a linearly spaced vector.\n  *\n  * The function fills \\c *this with equally spaced values in the closed interval [low,high].\n  * When size is set to 1, a vector of length 1 containing 'high' is returned.\n  *\n  * \\only_for_vectors\n  *\n  * For integer scalar types, do not miss the explanations on the definition\n  * of \\link LinSpaced(Index,const Scalar&,const Scalar&) even spacing \\endlink.\n  *\n  * \\sa LinSpaced(Index,const Scalar&,const Scalar&), setLinSpaced(Index, const Scalar&, const Scalar&), CwiseNullaryOp\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE Derived& DenseBase<Derived>::setLinSpaced(const Scalar& low, const Scalar& high)\n{\n  EIGEN_STATIC_ASSERT_VECTOR_ONLY(Derived)\n  return setLinSpaced(size(), low, high);\n}\n\n// zero:\n\n/** \\returns an expression of a zero matrix.\n  *\n  * The parameters \\a rows and \\a cols are the number of rows and of columns of\n  * the returned matrix. Must be compatible with this MatrixBase type.\n  *\n  * This variant is meant to be used for dynamic-size matrix types. For fixed-size types,\n  * it is redundant to pass \\a rows and \\a cols as arguments, so Zero() should be used\n  * instead.\n  *\n  * Example: \\include MatrixBase_zero_int_int.cpp\n  * Output: \\verbinclude MatrixBase_zero_int_int.out\n  *\n  * \\sa Zero(), Zero(Index)\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE const typename DenseBase<Derived>::ConstantReturnType\nDenseBase<Derived>::Zero(Index rows, Index cols)\n{\n  return Constant(rows, cols, Scalar(0));\n}\n\n/** \\returns an expression of a zero vector.\n  *\n  * The parameter \\a size is the size of the returned vector.\n  * Must be compatible with this MatrixBase type.\n  *\n  * \\only_for_vectors\n  *\n  * This variant is meant to be used for dynamic-size vector types. For fixed-size types,\n  * it is redundant to pass \\a size as argument, so Zero() should be used\n  * instead.\n  *\n  * Example: \\include MatrixBase_zero_int.cpp\n  * Output: \\verbinclude MatrixBase_zero_int.out\n  *\n  * \\sa Zero(), Zero(Index,Index)\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE const typename DenseBase<Derived>::ConstantReturnType\nDenseBase<Derived>::Zero(Index size)\n{\n  return Constant(size, Scalar(0));\n}\n\n/** \\returns an expression of a fixed-size zero matrix or vector.\n  *\n  * This variant is only for fixed-size MatrixBase types. For dynamic-size types, you\n  * need to use the variants taking size arguments.\n  *\n  * Example: \\include MatrixBase_zero.cpp\n  * Output: \\verbinclude MatrixBase_zero.out\n  *\n  * \\sa Zero(Index), Zero(Index,Index)\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE const typename DenseBase<Derived>::ConstantReturnType\nDenseBase<Derived>::Zero()\n{\n  return Constant(Scalar(0));\n}\n\n/** \\returns true if *this is approximately equal to the zero matrix,\n  *          within the precision given by \\a prec.\n  *\n  * Example: \\include MatrixBase_isZero.cpp\n  * Output: \\verbinclude MatrixBase_isZero.out\n  *\n  * \\sa class CwiseNullaryOp, Zero()\n  */\ntemplate<typename Derived>\nbool DenseBase<Derived>::isZero(const RealScalar& prec) const\n{\n  typename internal::nested_eval<Derived,1>::type self(derived());\n  for(Index j = 0; j < cols(); ++j)\n    for(Index i = 0; i < rows(); ++i)\n      if(!internal::isMuchSmallerThan(self.coeff(i, j), static_cast<Scalar>(1), prec))\n        return false;\n  return true;\n}\n\n/** Sets all coefficients in this expression to zero.\n  *\n  * Example: \\include MatrixBase_setZero.cpp\n  * Output: \\verbinclude MatrixBase_setZero.out\n  *\n  * \\sa class CwiseNullaryOp, Zero()\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE Derived& DenseBase<Derived>::setZero()\n{\n  return setConstant(Scalar(0));\n}\n\n/** Resizes to the given \\a size, and sets all coefficients in this expression to zero.\n  *\n  * \\only_for_vectors\n  *\n  * Example: \\include Matrix_setZero_int.cpp\n  * Output: \\verbinclude Matrix_setZero_int.out\n  *\n  * \\sa DenseBase::setZero(), setZero(Index,Index), class CwiseNullaryOp, DenseBase::Zero()\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE Derived&\nPlainObjectBase<Derived>::setZero(Index newSize)\n{\n  resize(newSize);\n  return setConstant(Scalar(0));\n}\n\n/** Resizes to the given size, and sets all coefficients in this expression to zero.\n  *\n  * \\param rows the new number of rows\n  * \\param cols the new number of columns\n  *\n  * Example: \\include Matrix_setZero_int_int.cpp\n  * Output: \\verbinclude Matrix_setZero_int_int.out\n  *\n  * \\sa DenseBase::setZero(), setZero(Index), class CwiseNullaryOp, DenseBase::Zero()\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE Derived&\nPlainObjectBase<Derived>::setZero(Index rows, Index cols)\n{\n  resize(rows, cols);\n  return setConstant(Scalar(0));\n}\n\n// ones:\n\n/** \\returns an expression of a matrix where all coefficients equal one.\n  *\n  * The parameters \\a rows and \\a cols are the number of rows and of columns of\n  * the returned matrix. Must be compatible with this MatrixBase type.\n  *\n  * This variant is meant to be used for dynamic-size matrix types. For fixed-size types,\n  * it is redundant to pass \\a rows and \\a cols as arguments, so Ones() should be used\n  * instead.\n  *\n  * Example: \\include MatrixBase_ones_int_int.cpp\n  * Output: \\verbinclude MatrixBase_ones_int_int.out\n  *\n  * \\sa Ones(), Ones(Index), isOnes(), class Ones\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE const typename DenseBase<Derived>::ConstantReturnType\nDenseBase<Derived>::Ones(Index rows, Index cols)\n{\n  return Constant(rows, cols, Scalar(1));\n}\n\n/** \\returns an expression of a vector where all coefficients equal one.\n  *\n  * The parameter \\a newSize is the size of the returned vector.\n  * Must be compatible with this MatrixBase type.\n  *\n  * \\only_for_vectors\n  *\n  * This variant is meant to be used for dynamic-size vector types. For fixed-size types,\n  * it is redundant to pass \\a size as argument, so Ones() should be used\n  * instead.\n  *\n  * Example: \\include MatrixBase_ones_int.cpp\n  * Output: \\verbinclude MatrixBase_ones_int.out\n  *\n  * \\sa Ones(), Ones(Index,Index), isOnes(), class Ones\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE const typename DenseBase<Derived>::ConstantReturnType\nDenseBase<Derived>::Ones(Index newSize)\n{\n  return Constant(newSize, Scalar(1));\n}\n\n/** \\returns an expression of a fixed-size matrix or vector where all coefficients equal one.\n  *\n  * This variant is only for fixed-size MatrixBase types. For dynamic-size types, you\n  * need to use the variants taking size arguments.\n  *\n  * Example: \\include MatrixBase_ones.cpp\n  * Output: \\verbinclude MatrixBase_ones.out\n  *\n  * \\sa Ones(Index), Ones(Index,Index), isOnes(), class Ones\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE const typename DenseBase<Derived>::ConstantReturnType\nDenseBase<Derived>::Ones()\n{\n  return Constant(Scalar(1));\n}\n\n/** \\returns true if *this is approximately equal to the matrix where all coefficients\n  *          are equal to 1, within the precision given by \\a prec.\n  *\n  * Example: \\include MatrixBase_isOnes.cpp\n  * Output: \\verbinclude MatrixBase_isOnes.out\n  *\n  * \\sa class CwiseNullaryOp, Ones()\n  */\ntemplate<typename Derived>\nbool DenseBase<Derived>::isOnes\n(const RealScalar& prec) const\n{\n  return isApproxToConstant(Scalar(1), prec);\n}\n\n/** Sets all coefficients in this expression to one.\n  *\n  * Example: \\include MatrixBase_setOnes.cpp\n  * Output: \\verbinclude MatrixBase_setOnes.out\n  *\n  * \\sa class CwiseNullaryOp, Ones()\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE Derived& DenseBase<Derived>::setOnes()\n{\n  return setConstant(Scalar(1));\n}\n\n/** Resizes to the given \\a newSize, and sets all coefficients in this expression to one.\n  *\n  * \\only_for_vectors\n  *\n  * Example: \\include Matrix_setOnes_int.cpp\n  * Output: \\verbinclude Matrix_setOnes_int.out\n  *\n  * \\sa MatrixBase::setOnes(), setOnes(Index,Index), class CwiseNullaryOp, MatrixBase::Ones()\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE Derived&\nPlainObjectBase<Derived>::setOnes(Index newSize)\n{\n  resize(newSize);\n  return setConstant(Scalar(1));\n}\n\n/** Resizes to the given size, and sets all coefficients in this expression to one.\n  *\n  * \\param rows the new number of rows\n  * \\param cols the new number of columns\n  *\n  * Example: \\include Matrix_setOnes_int_int.cpp\n  * Output: \\verbinclude Matrix_setOnes_int_int.out\n  *\n  * \\sa MatrixBase::setOnes(), setOnes(Index), class CwiseNullaryOp, MatrixBase::Ones()\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE Derived&\nPlainObjectBase<Derived>::setOnes(Index rows, Index cols)\n{\n  resize(rows, cols);\n  return setConstant(Scalar(1));\n}\n\n// Identity:\n\n/** \\returns an expression of the identity matrix (not necessarily square).\n  *\n  * The parameters \\a rows and \\a cols are the number of rows and of columns of\n  * the returned matrix. Must be compatible with this MatrixBase type.\n  *\n  * This variant is meant to be used for dynamic-size matrix types. For fixed-size types,\n  * it is redundant to pass \\a rows and \\a cols as arguments, so Identity() should be used\n  * instead.\n  *\n  * Example: \\include MatrixBase_identity_int_int.cpp\n  * Output: \\verbinclude MatrixBase_identity_int_int.out\n  *\n  * \\sa Identity(), setIdentity(), isIdentity()\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE const typename MatrixBase<Derived>::IdentityReturnType\nMatrixBase<Derived>::Identity(Index rows, Index cols)\n{\n  return DenseBase<Derived>::NullaryExpr(rows, cols, internal::scalar_identity_op<Scalar>());\n}\n\n/** \\returns an expression of the identity matrix (not necessarily square).\n  *\n  * This variant is only for fixed-size MatrixBase types. For dynamic-size types, you\n  * need to use the variant taking size arguments.\n  *\n  * Example: \\include MatrixBase_identity.cpp\n  * Output: \\verbinclude MatrixBase_identity.out\n  *\n  * \\sa Identity(Index,Index), setIdentity(), isIdentity()\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE const typename MatrixBase<Derived>::IdentityReturnType\nMatrixBase<Derived>::Identity()\n{\n  EIGEN_STATIC_ASSERT_FIXED_SIZE(Derived)\n  return MatrixBase<Derived>::NullaryExpr(RowsAtCompileTime, ColsAtCompileTime, internal::scalar_identity_op<Scalar>());\n}\n\n/** \\returns true if *this is approximately equal to the identity matrix\n  *          (not necessarily square),\n  *          within the precision given by \\a prec.\n  *\n  * Example: \\include MatrixBase_isIdentity.cpp\n  * Output: \\verbinclude MatrixBase_isIdentity.out\n  *\n  * \\sa class CwiseNullaryOp, Identity(), Identity(Index,Index), setIdentity()\n  */\ntemplate<typename Derived>\nbool MatrixBase<Derived>::isIdentity\n(const RealScalar& prec) const\n{\n  typename internal::nested_eval<Derived,1>::type self(derived());\n  for(Index j = 0; j < cols(); ++j)\n  {\n    for(Index i = 0; i < rows(); ++i)\n    {\n      if(i == j)\n      {\n        if(!internal::isApprox(self.coeff(i, j), static_cast<Scalar>(1), prec))\n          return false;\n      }\n      else\n      {\n        if(!internal::isMuchSmallerThan(self.coeff(i, j), static_cast<RealScalar>(1), prec))\n          return false;\n      }\n    }\n  }\n  return true;\n}\n\nnamespace internal {\n\ntemplate<typename Derived, bool Big = (Derived::SizeAtCompileTime>=16)>\nstruct setIdentity_impl\n{\n  EIGEN_DEVICE_FUNC\n  static EIGEN_STRONG_INLINE Derived& run(Derived& m)\n  {\n    return m = Derived::Identity(m.rows(), m.cols());\n  }\n};\n\ntemplate<typename Derived>\nstruct setIdentity_impl<Derived, true>\n{\n  EIGEN_DEVICE_FUNC\n  static EIGEN_STRONG_INLINE Derived& run(Derived& m)\n  {\n    m.setZero();\n    const Index size = numext::mini(m.rows(), m.cols());\n    for(Index i = 0; i < size; ++i) m.coeffRef(i,i) = typename Derived::Scalar(1);\n    return m;\n  }\n};\n\n} // end namespace internal\n\n/** Writes the identity expression (not necessarily square) into *this.\n  *\n  * Example: \\include MatrixBase_setIdentity.cpp\n  * Output: \\verbinclude MatrixBase_setIdentity.out\n  *\n  * \\sa class CwiseNullaryOp, Identity(), Identity(Index,Index), isIdentity()\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE Derived& MatrixBase<Derived>::setIdentity()\n{\n  return internal::setIdentity_impl<Derived>::run(derived());\n}\n\n/** \\brief Resizes to the given size, and writes the identity expression (not necessarily square) into *this.\n  *\n  * \\param rows the new number of rows\n  * \\param cols the new number of columns\n  *\n  * Example: \\include Matrix_setIdentity_int_int.cpp\n  * Output: \\verbinclude Matrix_setIdentity_int_int.out\n  *\n  * \\sa MatrixBase::setIdentity(), class CwiseNullaryOp, MatrixBase::Identity()\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE Derived& MatrixBase<Derived>::setIdentity(Index rows, Index cols)\n{\n  derived().resize(rows, cols);\n  return setIdentity();\n}\n\n/** \\returns an expression of the i-th unit (basis) vector.\n  *\n  * \\only_for_vectors\n  *\n  * \\sa MatrixBase::Unit(Index), MatrixBase::UnitX(), MatrixBase::UnitY(), MatrixBase::UnitZ(), MatrixBase::UnitW()\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE const typename MatrixBase<Derived>::BasisReturnType MatrixBase<Derived>::Unit(Index newSize, Index i)\n{\n  EIGEN_STATIC_ASSERT_VECTOR_ONLY(Derived)\n  return BasisReturnType(SquareMatrixType::Identity(newSize,newSize), i);\n}\n\n/** \\returns an expression of the i-th unit (basis) vector.\n  *\n  * \\only_for_vectors\n  *\n  * This variant is for fixed-size vector only.\n  *\n  * \\sa MatrixBase::Unit(Index,Index), MatrixBase::UnitX(), MatrixBase::UnitY(), MatrixBase::UnitZ(), MatrixBase::UnitW()\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE const typename MatrixBase<Derived>::BasisReturnType MatrixBase<Derived>::Unit(Index i)\n{\n  EIGEN_STATIC_ASSERT_VECTOR_ONLY(Derived)\n  return BasisReturnType(SquareMatrixType::Identity(),i);\n}\n\n/** \\returns an expression of the X axis unit vector (1{,0}^*)\n  *\n  * \\only_for_vectors\n  *\n  * \\sa MatrixBase::Unit(Index,Index), MatrixBase::Unit(Index), MatrixBase::UnitY(), MatrixBase::UnitZ(), MatrixBase::UnitW()\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE const typename MatrixBase<Derived>::BasisReturnType MatrixBase<Derived>::UnitX()\n{ return Derived::Unit(0); }\n\n/** \\returns an expression of the Y axis unit vector (0,1{,0}^*)\n  *\n  * \\only_for_vectors\n  *\n  * \\sa MatrixBase::Unit(Index,Index), MatrixBase::Unit(Index), MatrixBase::UnitY(), MatrixBase::UnitZ(), MatrixBase::UnitW()\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE const typename MatrixBase<Derived>::BasisReturnType MatrixBase<Derived>::UnitY()\n{ return Derived::Unit(1); }\n\n/** \\returns an expression of the Z axis unit vector (0,0,1{,0}^*)\n  *\n  * \\only_for_vectors\n  *\n  * \\sa MatrixBase::Unit(Index,Index), MatrixBase::Unit(Index), MatrixBase::UnitY(), MatrixBase::UnitZ(), MatrixBase::UnitW()\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE const typename MatrixBase<Derived>::BasisReturnType MatrixBase<Derived>::UnitZ()\n{ return Derived::Unit(2); }\n\n/** \\returns an expression of the W axis unit vector (0,0,0,1)\n  *\n  * \\only_for_vectors\n  *\n  * \\sa MatrixBase::Unit(Index,Index), MatrixBase::Unit(Index), MatrixBase::UnitY(), MatrixBase::UnitZ(), MatrixBase::UnitW()\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE const typename MatrixBase<Derived>::BasisReturnType MatrixBase<Derived>::UnitW()\n{ return Derived::Unit(3); }\n\n} // end namespace Eigen\n\n#endif // EIGEN_CWISE_NULLARY_OP_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/CwiseTernaryOp.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2014 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2006-2008 Benoit Jacob <jacob.benoit.1@gmail.com>\n// Copyright (C) 2016 Eugene Brevdo <ebrevdo@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_CWISE_TERNARY_OP_H\n#define EIGEN_CWISE_TERNARY_OP_H\n\nnamespace Eigen {\n\nnamespace internal {\ntemplate <typename TernaryOp, typename Arg1, typename Arg2, typename Arg3>\nstruct traits<CwiseTernaryOp<TernaryOp, Arg1, Arg2, Arg3> > {\n  // we must not inherit from traits<Arg1> since it has\n  // the potential to cause problems with MSVC\n  typedef typename remove_all<Arg1>::type Ancestor;\n  typedef typename traits<Ancestor>::XprKind XprKind;\n  enum {\n    RowsAtCompileTime = traits<Ancestor>::RowsAtCompileTime,\n    ColsAtCompileTime = traits<Ancestor>::ColsAtCompileTime,\n    MaxRowsAtCompileTime = traits<Ancestor>::MaxRowsAtCompileTime,\n    MaxColsAtCompileTime = traits<Ancestor>::MaxColsAtCompileTime\n  };\n\n  // even though we require Arg1, Arg2, and Arg3 to have the same scalar type\n  // (see CwiseTernaryOp constructor),\n  // we still want to handle the case when the result type is different.\n  typedef typename result_of<TernaryOp(\n      const typename Arg1::Scalar&, const typename Arg2::Scalar&,\n      const typename Arg3::Scalar&)>::type Scalar;\n\n  typedef typename internal::traits<Arg1>::StorageKind StorageKind;\n  typedef typename internal::traits<Arg1>::StorageIndex StorageIndex;\n\n  typedef typename Arg1::Nested Arg1Nested;\n  typedef typename Arg2::Nested Arg2Nested;\n  typedef typename Arg3::Nested Arg3Nested;\n  typedef typename remove_reference<Arg1Nested>::type _Arg1Nested;\n  typedef typename remove_reference<Arg2Nested>::type _Arg2Nested;\n  typedef typename remove_reference<Arg3Nested>::type _Arg3Nested;\n  enum { Flags = _Arg1Nested::Flags & RowMajorBit };\n};\n}  // end namespace internal\n\ntemplate <typename TernaryOp, typename Arg1, typename Arg2, typename Arg3,\n          typename StorageKind>\nclass CwiseTernaryOpImpl;\n\n/** \\class CwiseTernaryOp\n  * \\ingroup Core_Module\n  *\n  * \\brief Generic expression where a coefficient-wise ternary operator is\n * applied to two expressions\n  *\n  * \\tparam TernaryOp template functor implementing the operator\n  * \\tparam Arg1Type the type of the first argument\n  * \\tparam Arg2Type the type of the second argument\n  * \\tparam Arg3Type the type of the third argument\n  *\n  * This class represents an expression where a coefficient-wise ternary\n * operator is applied to three expressions.\n  * It is the return type of ternary operators, by which we mean only those\n * ternary operators where\n  * all three arguments are Eigen expressions.\n  * For example, the return type of betainc(matrix1, matrix2, matrix3) is a\n * CwiseTernaryOp.\n  *\n  * Most of the time, this is the only way that it is used, so you typically\n * don't have to name\n  * CwiseTernaryOp types explicitly.\n  *\n  * \\sa MatrixBase::ternaryExpr(const MatrixBase<Argument2> &, const\n * MatrixBase<Argument3> &, const CustomTernaryOp &) const, class CwiseBinaryOp,\n * class CwiseUnaryOp, class CwiseNullaryOp\n  */\ntemplate <typename TernaryOp, typename Arg1Type, typename Arg2Type,\n          typename Arg3Type>\nclass CwiseTernaryOp : public CwiseTernaryOpImpl<\n                           TernaryOp, Arg1Type, Arg2Type, Arg3Type,\n                           typename internal::traits<Arg1Type>::StorageKind>,\n                       internal::no_assignment_operator\n{\n public:\n  typedef typename internal::remove_all<Arg1Type>::type Arg1;\n  typedef typename internal::remove_all<Arg2Type>::type Arg2;\n  typedef typename internal::remove_all<Arg3Type>::type Arg3;\n\n  typedef typename CwiseTernaryOpImpl<\n      TernaryOp, Arg1Type, Arg2Type, Arg3Type,\n      typename internal::traits<Arg1Type>::StorageKind>::Base Base;\n  EIGEN_GENERIC_PUBLIC_INTERFACE(CwiseTernaryOp)\n\n  typedef typename internal::ref_selector<Arg1Type>::type Arg1Nested;\n  typedef typename internal::ref_selector<Arg2Type>::type Arg2Nested;\n  typedef typename internal::ref_selector<Arg3Type>::type Arg3Nested;\n  typedef typename internal::remove_reference<Arg1Nested>::type _Arg1Nested;\n  typedef typename internal::remove_reference<Arg2Nested>::type _Arg2Nested;\n  typedef typename internal::remove_reference<Arg3Nested>::type _Arg3Nested;\n\n  EIGEN_DEVICE_FUNC\n  EIGEN_STRONG_INLINE CwiseTernaryOp(const Arg1& a1, const Arg2& a2,\n                                     const Arg3& a3,\n                                     const TernaryOp& func = TernaryOp())\n      : m_arg1(a1), m_arg2(a2), m_arg3(a3), m_functor(func) {\n    // require the sizes to match\n    EIGEN_STATIC_ASSERT_SAME_MATRIX_SIZE(Arg1, Arg2)\n    EIGEN_STATIC_ASSERT_SAME_MATRIX_SIZE(Arg1, Arg3)\n\n    // The index types should match\n    EIGEN_STATIC_ASSERT((internal::is_same<\n                         typename internal::traits<Arg1Type>::StorageKind,\n                         typename internal::traits<Arg2Type>::StorageKind>::value),\n                        STORAGE_KIND_MUST_MATCH)\n    EIGEN_STATIC_ASSERT((internal::is_same<\n                         typename internal::traits<Arg1Type>::StorageKind,\n                         typename internal::traits<Arg3Type>::StorageKind>::value),\n                        STORAGE_KIND_MUST_MATCH)\n\n    eigen_assert(a1.rows() == a2.rows() && a1.cols() == a2.cols() &&\n                 a1.rows() == a3.rows() && a1.cols() == a3.cols());\n  }\n\n  EIGEN_DEVICE_FUNC\n  EIGEN_STRONG_INLINE Index rows() const {\n    // return the fixed size type if available to enable compile time\n    // optimizations\n    if (internal::traits<typename internal::remove_all<Arg1Nested>::type>::\n                RowsAtCompileTime == Dynamic &&\n        internal::traits<typename internal::remove_all<Arg2Nested>::type>::\n                RowsAtCompileTime == Dynamic)\n      return m_arg3.rows();\n    else if (internal::traits<typename internal::remove_all<Arg1Nested>::type>::\n                     RowsAtCompileTime == Dynamic &&\n             internal::traits<typename internal::remove_all<Arg3Nested>::type>::\n                     RowsAtCompileTime == Dynamic)\n      return m_arg2.rows();\n    else\n      return m_arg1.rows();\n  }\n  EIGEN_DEVICE_FUNC\n  EIGEN_STRONG_INLINE Index cols() const {\n    // return the fixed size type if available to enable compile time\n    // optimizations\n    if (internal::traits<typename internal::remove_all<Arg1Nested>::type>::\n                ColsAtCompileTime == Dynamic &&\n        internal::traits<typename internal::remove_all<Arg2Nested>::type>::\n                ColsAtCompileTime == Dynamic)\n      return m_arg3.cols();\n    else if (internal::traits<typename internal::remove_all<Arg1Nested>::type>::\n                     ColsAtCompileTime == Dynamic &&\n             internal::traits<typename internal::remove_all<Arg3Nested>::type>::\n                     ColsAtCompileTime == Dynamic)\n      return m_arg2.cols();\n    else\n      return m_arg1.cols();\n  }\n\n  /** \\returns the first argument nested expression */\n  EIGEN_DEVICE_FUNC\n  const _Arg1Nested& arg1() const { return m_arg1; }\n  /** \\returns the first argument nested expression */\n  EIGEN_DEVICE_FUNC\n  const _Arg2Nested& arg2() const { return m_arg2; }\n  /** \\returns the third argument nested expression */\n  EIGEN_DEVICE_FUNC\n  const _Arg3Nested& arg3() const { return m_arg3; }\n  /** \\returns the functor representing the ternary operation */\n  EIGEN_DEVICE_FUNC\n  const TernaryOp& functor() const { return m_functor; }\n\n protected:\n  Arg1Nested m_arg1;\n  Arg2Nested m_arg2;\n  Arg3Nested m_arg3;\n  const TernaryOp m_functor;\n};\n\n// Generic API dispatcher\ntemplate <typename TernaryOp, typename Arg1, typename Arg2, typename Arg3,\n          typename StorageKind>\nclass CwiseTernaryOpImpl\n    : public internal::generic_xpr_base<\n          CwiseTernaryOp<TernaryOp, Arg1, Arg2, Arg3> >::type {\n public:\n  typedef typename internal::generic_xpr_base<\n      CwiseTernaryOp<TernaryOp, Arg1, Arg2, Arg3> >::type Base;\n};\n\n}  // end namespace Eigen\n\n#endif  // EIGEN_CWISE_TERNARY_OP_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/CwiseUnaryOp.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2014 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2006-2008 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_CWISE_UNARY_OP_H\n#define EIGEN_CWISE_UNARY_OP_H\n\nnamespace Eigen { \n\nnamespace internal {\ntemplate<typename UnaryOp, typename XprType>\nstruct traits<CwiseUnaryOp<UnaryOp, XprType> >\n : traits<XprType>\n{\n  typedef typename result_of<\n                     UnaryOp(const typename XprType::Scalar&)\n                   >::type Scalar;\n  typedef typename XprType::Nested XprTypeNested;\n  typedef typename remove_reference<XprTypeNested>::type _XprTypeNested;\n  enum {\n    Flags = _XprTypeNested::Flags & RowMajorBit \n  };\n};\n}\n\ntemplate<typename UnaryOp, typename XprType, typename StorageKind>\nclass CwiseUnaryOpImpl;\n\n/** \\class CwiseUnaryOp\n  * \\ingroup Core_Module\n  *\n  * \\brief Generic expression where a coefficient-wise unary operator is applied to an expression\n  *\n  * \\tparam UnaryOp template functor implementing the operator\n  * \\tparam XprType the type of the expression to which we are applying the unary operator\n  *\n  * This class represents an expression where a unary operator is applied to an expression.\n  * It is the return type of all operations taking exactly 1 input expression, regardless of the\n  * presence of other inputs such as scalars. For example, the operator* in the expression 3*matrix\n  * is considered unary, because only the right-hand side is an expression, and its\n  * return type is a specialization of CwiseUnaryOp.\n  *\n  * Most of the time, this is the only way that it is used, so you typically don't have to name\n  * CwiseUnaryOp types explicitly.\n  *\n  * \\sa MatrixBase::unaryExpr(const CustomUnaryOp &) const, class CwiseBinaryOp, class CwiseNullaryOp\n  */\ntemplate<typename UnaryOp, typename XprType>\nclass CwiseUnaryOp : public CwiseUnaryOpImpl<UnaryOp, XprType, typename internal::traits<XprType>::StorageKind>, internal::no_assignment_operator\n{\n  public:\n\n    typedef typename CwiseUnaryOpImpl<UnaryOp, XprType,typename internal::traits<XprType>::StorageKind>::Base Base;\n    EIGEN_GENERIC_PUBLIC_INTERFACE(CwiseUnaryOp)\n    typedef typename internal::ref_selector<XprType>::type XprTypeNested;\n    typedef typename internal::remove_all<XprType>::type NestedExpression;\n\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n    explicit CwiseUnaryOp(const XprType& xpr, const UnaryOp& func = UnaryOp())\n      : m_xpr(xpr), m_functor(func) {}\n\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n    Index rows() const { return m_xpr.rows(); }\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n    Index cols() const { return m_xpr.cols(); }\n\n    /** \\returns the functor representing the unary operation */\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n    const UnaryOp& functor() const { return m_functor; }\n\n    /** \\returns the nested expression */\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n    const typename internal::remove_all<XprTypeNested>::type&\n    nestedExpression() const { return m_xpr; }\n\n    /** \\returns the nested expression */\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n    typename internal::remove_all<XprTypeNested>::type&\n    nestedExpression() { return m_xpr; }\n\n  protected:\n    XprTypeNested m_xpr;\n    const UnaryOp m_functor;\n};\n\n// Generic API dispatcher\ntemplate<typename UnaryOp, typename XprType, typename StorageKind>\nclass CwiseUnaryOpImpl\n  : public internal::generic_xpr_base<CwiseUnaryOp<UnaryOp, XprType> >::type\n{\npublic:\n  typedef typename internal::generic_xpr_base<CwiseUnaryOp<UnaryOp, XprType> >::type Base;\n};\n\n} // end namespace Eigen\n\n#endif // EIGEN_CWISE_UNARY_OP_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/CwiseUnaryView.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009-2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_CWISE_UNARY_VIEW_H\n#define EIGEN_CWISE_UNARY_VIEW_H\n\nnamespace Eigen {\n\nnamespace internal {\ntemplate<typename ViewOp, typename MatrixType>\nstruct traits<CwiseUnaryView<ViewOp, MatrixType> >\n : traits<MatrixType>\n{\n  typedef typename result_of<\n                     ViewOp(const typename traits<MatrixType>::Scalar&)\n                   >::type Scalar;\n  typedef typename MatrixType::Nested MatrixTypeNested;\n  typedef typename remove_all<MatrixTypeNested>::type _MatrixTypeNested;\n  enum {\n    FlagsLvalueBit = is_lvalue<MatrixType>::value ? LvalueBit : 0,\n    Flags = traits<_MatrixTypeNested>::Flags & (RowMajorBit | FlagsLvalueBit | DirectAccessBit), // FIXME DirectAccessBit should not be handled by expressions\n    MatrixTypeInnerStride =  inner_stride_at_compile_time<MatrixType>::ret,\n    // need to cast the sizeof's from size_t to int explicitly, otherwise:\n    // \"error: no integral type can represent all of the enumerator values\n    InnerStrideAtCompileTime = MatrixTypeInnerStride == Dynamic\n                             ? int(Dynamic)\n                             : int(MatrixTypeInnerStride) * int(sizeof(typename traits<MatrixType>::Scalar) / sizeof(Scalar)),\n    OuterStrideAtCompileTime = outer_stride_at_compile_time<MatrixType>::ret == Dynamic\n                             ? int(Dynamic)\n                             : outer_stride_at_compile_time<MatrixType>::ret * int(sizeof(typename traits<MatrixType>::Scalar) / sizeof(Scalar))\n  };\n};\n}\n\ntemplate<typename ViewOp, typename MatrixType, typename StorageKind>\nclass CwiseUnaryViewImpl;\n\n/** \\class CwiseUnaryView\n  * \\ingroup Core_Module\n  *\n  * \\brief Generic lvalue expression of a coefficient-wise unary operator of a matrix or a vector\n  *\n  * \\tparam ViewOp template functor implementing the view\n  * \\tparam MatrixType the type of the matrix we are applying the unary operator\n  *\n  * This class represents a lvalue expression of a generic unary view operator of a matrix or a vector.\n  * It is the return type of real() and imag(), and most of the time this is the only way it is used.\n  *\n  * \\sa MatrixBase::unaryViewExpr(const CustomUnaryOp &) const, class CwiseUnaryOp\n  */\ntemplate<typename ViewOp, typename MatrixType>\nclass CwiseUnaryView : public CwiseUnaryViewImpl<ViewOp, MatrixType, typename internal::traits<MatrixType>::StorageKind>\n{\n  public:\n\n    typedef typename CwiseUnaryViewImpl<ViewOp, MatrixType,typename internal::traits<MatrixType>::StorageKind>::Base Base;\n    EIGEN_GENERIC_PUBLIC_INTERFACE(CwiseUnaryView)\n    typedef typename internal::ref_selector<MatrixType>::non_const_type MatrixTypeNested;\n    typedef typename internal::remove_all<MatrixType>::type NestedExpression;\n\n    explicit inline CwiseUnaryView(MatrixType& mat, const ViewOp& func = ViewOp())\n      : m_matrix(mat), m_functor(func) {}\n\n    EIGEN_INHERIT_ASSIGNMENT_OPERATORS(CwiseUnaryView)\n\n    EIGEN_STRONG_INLINE Index rows() const { return m_matrix.rows(); }\n    EIGEN_STRONG_INLINE Index cols() const { return m_matrix.cols(); }\n\n    /** \\returns the functor representing unary operation */\n    const ViewOp& functor() const { return m_functor; }\n\n    /** \\returns the nested expression */\n    const typename internal::remove_all<MatrixTypeNested>::type&\n    nestedExpression() const { return m_matrix; }\n\n    /** \\returns the nested expression */\n    typename internal::remove_reference<MatrixTypeNested>::type&\n    nestedExpression() { return m_matrix.const_cast_derived(); }\n\n  protected:\n    MatrixTypeNested m_matrix;\n    ViewOp m_functor;\n};\n\n// Generic API dispatcher\ntemplate<typename ViewOp, typename XprType, typename StorageKind>\nclass CwiseUnaryViewImpl\n  : public internal::generic_xpr_base<CwiseUnaryView<ViewOp, XprType> >::type\n{\npublic:\n  typedef typename internal::generic_xpr_base<CwiseUnaryView<ViewOp, XprType> >::type Base;\n};\n\ntemplate<typename ViewOp, typename MatrixType>\nclass CwiseUnaryViewImpl<ViewOp,MatrixType,Dense>\n  : public internal::dense_xpr_base< CwiseUnaryView<ViewOp, MatrixType> >::type\n{\n  public:\n\n    typedef CwiseUnaryView<ViewOp, MatrixType> Derived;\n    typedef typename internal::dense_xpr_base< CwiseUnaryView<ViewOp, MatrixType> >::type Base;\n\n    EIGEN_DENSE_PUBLIC_INTERFACE(Derived)\n    EIGEN_INHERIT_ASSIGNMENT_OPERATORS(CwiseUnaryViewImpl)\n    \n    EIGEN_DEVICE_FUNC inline Scalar* data() { return &(this->coeffRef(0)); }\n    EIGEN_DEVICE_FUNC inline const Scalar* data() const { return &(this->coeff(0)); }\n\n    EIGEN_DEVICE_FUNC inline Index innerStride() const\n    {\n      return derived().nestedExpression().innerStride() * sizeof(typename internal::traits<MatrixType>::Scalar) / sizeof(Scalar);\n    }\n\n    EIGEN_DEVICE_FUNC inline Index outerStride() const\n    {\n      return derived().nestedExpression().outerStride() * sizeof(typename internal::traits<MatrixType>::Scalar) / sizeof(Scalar);\n    }\n};\n\n} // end namespace Eigen\n\n#endif // EIGEN_CWISE_UNARY_VIEW_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/DenseBase.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2007-2010 Benoit Jacob <jacob.benoit.1@gmail.com>\n// Copyright (C) 2008-2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_DENSEBASE_H\n#define EIGEN_DENSEBASE_H\n\nnamespace Eigen {\n\nnamespace internal {\n  \n// The index type defined by EIGEN_DEFAULT_DENSE_INDEX_TYPE must be a signed type.\n// This dummy function simply aims at checking that at compile time.\nstatic inline void check_DenseIndex_is_signed() {\n  EIGEN_STATIC_ASSERT(NumTraits<DenseIndex>::IsSigned,THE_INDEX_TYPE_MUST_BE_A_SIGNED_TYPE); \n}\n\n} // end namespace internal\n  \n/** \\class DenseBase\n  * \\ingroup Core_Module\n  *\n  * \\brief Base class for all dense matrices, vectors, and arrays\n  *\n  * This class is the base that is inherited by all dense objects (matrix, vector, arrays,\n  * and related expression types). The common Eigen API for dense objects is contained in this class.\n  *\n  * \\tparam Derived is the derived type, e.g., a matrix type or an expression.\n  *\n  * This class can be extended with the help of the plugin mechanism described on the page\n  * \\ref TopicCustomizing_Plugins by defining the preprocessor symbol \\c EIGEN_DENSEBASE_PLUGIN.\n  *\n  * \\sa \\blank \\ref TopicClassHierarchy\n  */\ntemplate<typename Derived> class DenseBase\n#ifndef EIGEN_PARSED_BY_DOXYGEN\n  : public DenseCoeffsBase<Derived>\n#else\n  : public DenseCoeffsBase<Derived,DirectWriteAccessors>\n#endif // not EIGEN_PARSED_BY_DOXYGEN\n{\n  public:\n\n    /** Inner iterator type to iterate over the coefficients of a row or column.\n      * \\sa class InnerIterator\n      */\n    typedef Eigen::InnerIterator<Derived> InnerIterator;\n\n    typedef typename internal::traits<Derived>::StorageKind StorageKind;\n\n    /**\n      * \\brief The type used to store indices\n      * \\details This typedef is relevant for types that store multiple indices such as\n      *          PermutationMatrix or Transpositions, otherwise it defaults to Eigen::Index\n      * \\sa \\blank \\ref TopicPreprocessorDirectives, Eigen::Index, SparseMatrixBase.\n     */\n    typedef typename internal::traits<Derived>::StorageIndex StorageIndex;\n\n    /** The numeric type of the expression' coefficients, e.g. float, double, int or std::complex<float>, etc. */\n    typedef typename internal::traits<Derived>::Scalar Scalar;\n    \n    /** The numeric type of the expression' coefficients, e.g. float, double, int or std::complex<float>, etc.\n      *\n      * It is an alias for the Scalar type */\n    typedef Scalar value_type;\n    \n    typedef typename NumTraits<Scalar>::Real RealScalar;\n    typedef DenseCoeffsBase<Derived> Base;\n\n    using Base::derived;\n    using Base::const_cast_derived;\n    using Base::rows;\n    using Base::cols;\n    using Base::size;\n    using Base::rowIndexByOuterInner;\n    using Base::colIndexByOuterInner;\n    using Base::coeff;\n    using Base::coeffByOuterInner;\n    using Base::operator();\n    using Base::operator[];\n    using Base::x;\n    using Base::y;\n    using Base::z;\n    using Base::w;\n    using Base::stride;\n    using Base::innerStride;\n    using Base::outerStride;\n    using Base::rowStride;\n    using Base::colStride;\n    typedef typename Base::CoeffReturnType CoeffReturnType;\n\n    enum {\n\n      RowsAtCompileTime = internal::traits<Derived>::RowsAtCompileTime,\n        /**< The number of rows at compile-time. This is just a copy of the value provided\n          * by the \\a Derived type. If a value is not known at compile-time,\n          * it is set to the \\a Dynamic constant.\n          * \\sa MatrixBase::rows(), MatrixBase::cols(), ColsAtCompileTime, SizeAtCompileTime */\n\n      ColsAtCompileTime = internal::traits<Derived>::ColsAtCompileTime,\n        /**< The number of columns at compile-time. This is just a copy of the value provided\n          * by the \\a Derived type. If a value is not known at compile-time,\n          * it is set to the \\a Dynamic constant.\n          * \\sa MatrixBase::rows(), MatrixBase::cols(), RowsAtCompileTime, SizeAtCompileTime */\n\n\n      SizeAtCompileTime = (internal::size_at_compile_time<internal::traits<Derived>::RowsAtCompileTime,\n                                                   internal::traits<Derived>::ColsAtCompileTime>::ret),\n        /**< This is equal to the number of coefficients, i.e. the number of\n          * rows times the number of columns, or to \\a Dynamic if this is not\n          * known at compile-time. \\sa RowsAtCompileTime, ColsAtCompileTime */\n\n      MaxRowsAtCompileTime = internal::traits<Derived>::MaxRowsAtCompileTime,\n        /**< This value is equal to the maximum possible number of rows that this expression\n          * might have. If this expression might have an arbitrarily high number of rows,\n          * this value is set to \\a Dynamic.\n          *\n          * This value is useful to know when evaluating an expression, in order to determine\n          * whether it is possible to avoid doing a dynamic memory allocation.\n          *\n          * \\sa RowsAtCompileTime, MaxColsAtCompileTime, MaxSizeAtCompileTime\n          */\n\n      MaxColsAtCompileTime = internal::traits<Derived>::MaxColsAtCompileTime,\n        /**< This value is equal to the maximum possible number of columns that this expression\n          * might have. If this expression might have an arbitrarily high number of columns,\n          * this value is set to \\a Dynamic.\n          *\n          * This value is useful to know when evaluating an expression, in order to determine\n          * whether it is possible to avoid doing a dynamic memory allocation.\n          *\n          * \\sa ColsAtCompileTime, MaxRowsAtCompileTime, MaxSizeAtCompileTime\n          */\n\n      MaxSizeAtCompileTime = (internal::size_at_compile_time<internal::traits<Derived>::MaxRowsAtCompileTime,\n                                                      internal::traits<Derived>::MaxColsAtCompileTime>::ret),\n        /**< This value is equal to the maximum possible number of coefficients that this expression\n          * might have. If this expression might have an arbitrarily high number of coefficients,\n          * this value is set to \\a Dynamic.\n          *\n          * This value is useful to know when evaluating an expression, in order to determine\n          * whether it is possible to avoid doing a dynamic memory allocation.\n          *\n          * \\sa SizeAtCompileTime, MaxRowsAtCompileTime, MaxColsAtCompileTime\n          */\n\n      IsVectorAtCompileTime = internal::traits<Derived>::MaxRowsAtCompileTime == 1\n                           || internal::traits<Derived>::MaxColsAtCompileTime == 1,\n        /**< This is set to true if either the number of rows or the number of\n          * columns is known at compile-time to be equal to 1. Indeed, in that case,\n          * we are dealing with a column-vector (if there is only one column) or with\n          * a row-vector (if there is only one row). */\n\n      Flags = internal::traits<Derived>::Flags,\n        /**< This stores expression \\ref flags flags which may or may not be inherited by new expressions\n          * constructed from this one. See the \\ref flags \"list of flags\".\n          */\n\n      IsRowMajor = int(Flags) & RowMajorBit, /**< True if this expression has row-major storage order. */\n\n      InnerSizeAtCompileTime = int(IsVectorAtCompileTime) ? int(SizeAtCompileTime)\n                             : int(IsRowMajor) ? int(ColsAtCompileTime) : int(RowsAtCompileTime),\n\n      InnerStrideAtCompileTime = internal::inner_stride_at_compile_time<Derived>::ret,\n      OuterStrideAtCompileTime = internal::outer_stride_at_compile_time<Derived>::ret\n    };\n    \n    typedef typename internal::find_best_packet<Scalar,SizeAtCompileTime>::type PacketScalar;\n\n    enum { IsPlainObjectBase = 0 };\n    \n    /** The plain matrix type corresponding to this expression.\n      * \\sa PlainObject */\n    typedef Matrix<typename internal::traits<Derived>::Scalar,\n                internal::traits<Derived>::RowsAtCompileTime,\n                internal::traits<Derived>::ColsAtCompileTime,\n                AutoAlign | (internal::traits<Derived>::Flags&RowMajorBit ? RowMajor : ColMajor),\n                internal::traits<Derived>::MaxRowsAtCompileTime,\n                internal::traits<Derived>::MaxColsAtCompileTime\n          > PlainMatrix;\n    \n    /** The plain array type corresponding to this expression.\n      * \\sa PlainObject */\n    typedef Array<typename internal::traits<Derived>::Scalar,\n                internal::traits<Derived>::RowsAtCompileTime,\n                internal::traits<Derived>::ColsAtCompileTime,\n                AutoAlign | (internal::traits<Derived>::Flags&RowMajorBit ? RowMajor : ColMajor),\n                internal::traits<Derived>::MaxRowsAtCompileTime,\n                internal::traits<Derived>::MaxColsAtCompileTime\n          > PlainArray;\n\n    /** \\brief The plain matrix or array type corresponding to this expression.\n      *\n      * This is not necessarily exactly the return type of eval(). In the case of plain matrices,\n      * the return type of eval() is a const reference to a matrix, not a matrix! It is however guaranteed\n      * that the return type of eval() is either PlainObject or const PlainObject&.\n      */\n    typedef typename internal::conditional<internal::is_same<typename internal::traits<Derived>::XprKind,MatrixXpr >::value,\n                                 PlainMatrix, PlainArray>::type PlainObject;\n\n    /** \\returns the number of nonzero coefficients which is in practice the number\n      * of stored coefficients. */\n    EIGEN_DEVICE_FUNC\n    inline Index nonZeros() const { return size(); }\n\n    /** \\returns the outer size.\n      *\n      * \\note For a vector, this returns just 1. For a matrix (non-vector), this is the major dimension\n      * with respect to the \\ref TopicStorageOrders \"storage order\", i.e., the number of columns for a\n      * column-major matrix, and the number of rows for a row-major matrix. */\n    EIGEN_DEVICE_FUNC\n    Index outerSize() const\n    {\n      return IsVectorAtCompileTime ? 1\n           : int(IsRowMajor) ? this->rows() : this->cols();\n    }\n\n    /** \\returns the inner size.\n      *\n      * \\note For a vector, this is just the size. For a matrix (non-vector), this is the minor dimension\n      * with respect to the \\ref TopicStorageOrders \"storage order\", i.e., the number of rows for a \n      * column-major matrix, and the number of columns for a row-major matrix. */\n    EIGEN_DEVICE_FUNC\n    Index innerSize() const\n    {\n      return IsVectorAtCompileTime ? this->size()\n           : int(IsRowMajor) ? this->cols() : this->rows();\n    }\n\n    /** Only plain matrices/arrays, not expressions, may be resized; therefore the only useful resize methods are\n      * Matrix::resize() and Array::resize(). The present method only asserts that the new size equals the old size, and does\n      * nothing else.\n      */\n    EIGEN_DEVICE_FUNC\n    void resize(Index newSize)\n    {\n      EIGEN_ONLY_USED_FOR_DEBUG(newSize);\n      eigen_assert(newSize == this->size()\n                && \"DenseBase::resize() does not actually allow to resize.\");\n    }\n    /** Only plain matrices/arrays, not expressions, may be resized; therefore the only useful resize methods are\n      * Matrix::resize() and Array::resize(). The present method only asserts that the new size equals the old size, and does\n      * nothing else.\n      */\n    EIGEN_DEVICE_FUNC\n    void resize(Index rows, Index cols)\n    {\n      EIGEN_ONLY_USED_FOR_DEBUG(rows);\n      EIGEN_ONLY_USED_FOR_DEBUG(cols);\n      eigen_assert(rows == this->rows() && cols == this->cols()\n                && \"DenseBase::resize() does not actually allow to resize.\");\n    }\n\n#ifndef EIGEN_PARSED_BY_DOXYGEN\n    /** \\internal Represents a matrix with all coefficients equal to one another*/\n    typedef CwiseNullaryOp<internal::scalar_constant_op<Scalar>,PlainObject> ConstantReturnType;\n    /** \\internal \\deprecated Represents a vector with linearly spaced coefficients that allows sequential access only. */\n    typedef CwiseNullaryOp<internal::linspaced_op<Scalar,PacketScalar>,PlainObject> SequentialLinSpacedReturnType;\n    /** \\internal Represents a vector with linearly spaced coefficients that allows random access. */\n    typedef CwiseNullaryOp<internal::linspaced_op<Scalar,PacketScalar>,PlainObject> RandomAccessLinSpacedReturnType;\n    /** \\internal the return type of MatrixBase::eigenvalues() */\n    typedef Matrix<typename NumTraits<typename internal::traits<Derived>::Scalar>::Real, internal::traits<Derived>::ColsAtCompileTime, 1> EigenvaluesReturnType;\n\n#endif // not EIGEN_PARSED_BY_DOXYGEN\n\n    /** Copies \\a other into *this. \\returns a reference to *this. */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n    Derived& operator=(const DenseBase<OtherDerived>& other);\n\n    /** Special case of the template operator=, in order to prevent the compiler\n      * from generating a default operator= (issue hit with g++ 4.1)\n      */\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n    Derived& operator=(const DenseBase& other);\n\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    Derived& operator=(const EigenBase<OtherDerived> &other);\n\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    Derived& operator+=(const EigenBase<OtherDerived> &other);\n\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    Derived& operator-=(const EigenBase<OtherDerived> &other);\n\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    Derived& operator=(const ReturnByValue<OtherDerived>& func);\n\n    /** \\ínternal\n      * Copies \\a other into *this without evaluating other. \\returns a reference to *this.\n      * \\deprecated */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    Derived& lazyAssign(const DenseBase<OtherDerived>& other);\n\n    EIGEN_DEVICE_FUNC\n    CommaInitializer<Derived> operator<< (const Scalar& s);\n\n    /** \\deprecated it now returns \\c *this */\n    template<unsigned int Added,unsigned int Removed>\n    EIGEN_DEPRECATED\n    const Derived& flagged() const\n    { return derived(); }\n\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    CommaInitializer<Derived> operator<< (const DenseBase<OtherDerived>& other);\n\n    typedef Transpose<Derived> TransposeReturnType;\n    EIGEN_DEVICE_FUNC\n    TransposeReturnType transpose();\n    typedef typename internal::add_const<Transpose<const Derived> >::type ConstTransposeReturnType;\n    EIGEN_DEVICE_FUNC\n    ConstTransposeReturnType transpose() const;\n    EIGEN_DEVICE_FUNC\n    void transposeInPlace();\n\n    EIGEN_DEVICE_FUNC static const ConstantReturnType\n    Constant(Index rows, Index cols, const Scalar& value);\n    EIGEN_DEVICE_FUNC static const ConstantReturnType\n    Constant(Index size, const Scalar& value);\n    EIGEN_DEVICE_FUNC static const ConstantReturnType\n    Constant(const Scalar& value);\n\n    EIGEN_DEVICE_FUNC static const SequentialLinSpacedReturnType\n    LinSpaced(Sequential_t, Index size, const Scalar& low, const Scalar& high);\n    EIGEN_DEVICE_FUNC static const RandomAccessLinSpacedReturnType\n    LinSpaced(Index size, const Scalar& low, const Scalar& high);\n    EIGEN_DEVICE_FUNC static const SequentialLinSpacedReturnType\n    LinSpaced(Sequential_t, const Scalar& low, const Scalar& high);\n    EIGEN_DEVICE_FUNC static const RandomAccessLinSpacedReturnType\n    LinSpaced(const Scalar& low, const Scalar& high);\n\n    template<typename CustomNullaryOp> EIGEN_DEVICE_FUNC\n    static const CwiseNullaryOp<CustomNullaryOp, PlainObject>\n    NullaryExpr(Index rows, Index cols, const CustomNullaryOp& func);\n    template<typename CustomNullaryOp> EIGEN_DEVICE_FUNC\n    static const CwiseNullaryOp<CustomNullaryOp, PlainObject>\n    NullaryExpr(Index size, const CustomNullaryOp& func);\n    template<typename CustomNullaryOp> EIGEN_DEVICE_FUNC\n    static const CwiseNullaryOp<CustomNullaryOp, PlainObject>\n    NullaryExpr(const CustomNullaryOp& func);\n\n    EIGEN_DEVICE_FUNC static const ConstantReturnType Zero(Index rows, Index cols);\n    EIGEN_DEVICE_FUNC static const ConstantReturnType Zero(Index size);\n    EIGEN_DEVICE_FUNC static const ConstantReturnType Zero();\n    EIGEN_DEVICE_FUNC static const ConstantReturnType Ones(Index rows, Index cols);\n    EIGEN_DEVICE_FUNC static const ConstantReturnType Ones(Index size);\n    EIGEN_DEVICE_FUNC static const ConstantReturnType Ones();\n\n    EIGEN_DEVICE_FUNC void fill(const Scalar& value);\n    EIGEN_DEVICE_FUNC Derived& setConstant(const Scalar& value);\n    EIGEN_DEVICE_FUNC Derived& setLinSpaced(Index size, const Scalar& low, const Scalar& high);\n    EIGEN_DEVICE_FUNC Derived& setLinSpaced(const Scalar& low, const Scalar& high);\n    EIGEN_DEVICE_FUNC Derived& setZero();\n    EIGEN_DEVICE_FUNC Derived& setOnes();\n    EIGEN_DEVICE_FUNC Derived& setRandom();\n\n    template<typename OtherDerived> EIGEN_DEVICE_FUNC\n    bool isApprox(const DenseBase<OtherDerived>& other,\n                  const RealScalar& prec = NumTraits<Scalar>::dummy_precision()) const;\n    EIGEN_DEVICE_FUNC \n    bool isMuchSmallerThan(const RealScalar& other,\n                           const RealScalar& prec = NumTraits<Scalar>::dummy_precision()) const;\n    template<typename OtherDerived> EIGEN_DEVICE_FUNC\n    bool isMuchSmallerThan(const DenseBase<OtherDerived>& other,\n                           const RealScalar& prec = NumTraits<Scalar>::dummy_precision()) const;\n\n    EIGEN_DEVICE_FUNC bool isApproxToConstant(const Scalar& value, const RealScalar& prec = NumTraits<Scalar>::dummy_precision()) const;\n    EIGEN_DEVICE_FUNC bool isConstant(const Scalar& value, const RealScalar& prec = NumTraits<Scalar>::dummy_precision()) const;\n    EIGEN_DEVICE_FUNC bool isZero(const RealScalar& prec = NumTraits<Scalar>::dummy_precision()) const;\n    EIGEN_DEVICE_FUNC bool isOnes(const RealScalar& prec = NumTraits<Scalar>::dummy_precision()) const;\n    \n    inline bool hasNaN() const;\n    inline bool allFinite() const;\n\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n    Derived& operator*=(const Scalar& other);\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n    Derived& operator/=(const Scalar& other);\n\n    typedef typename internal::add_const_on_value_type<typename internal::eval<Derived>::type>::type EvalReturnType;\n    /** \\returns the matrix or vector obtained by evaluating this expression.\n      *\n      * Notice that in the case of a plain matrix or vector (not an expression) this function just returns\n      * a const reference, in order to avoid a useless copy.\n      * \n      * \\warning Be carefull with eval() and the auto C++ keyword, as detailed in this \\link TopicPitfalls_auto_keyword page \\endlink.\n      */\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE EvalReturnType eval() const\n    {\n      // Even though MSVC does not honor strong inlining when the return type\n      // is a dynamic matrix, we desperately need strong inlining for fixed\n      // size types on MSVC.\n      return typename internal::eval<Derived>::type(derived());\n    }\n    \n    /** swaps *this with the expression \\a other.\n      *\n      */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    void swap(const DenseBase<OtherDerived>& other)\n    {\n      EIGEN_STATIC_ASSERT(!OtherDerived::IsPlainObjectBase,THIS_EXPRESSION_IS_NOT_A_LVALUE__IT_IS_READ_ONLY);\n      eigen_assert(rows()==other.rows() && cols()==other.cols());\n      call_assignment(derived(), other.const_cast_derived(), internal::swap_assign_op<Scalar>());\n    }\n\n    /** swaps *this with the matrix or array \\a other.\n      *\n      */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    void swap(PlainObjectBase<OtherDerived>& other)\n    {\n      eigen_assert(rows()==other.rows() && cols()==other.cols());\n      call_assignment(derived(), other.derived(), internal::swap_assign_op<Scalar>());\n    }\n\n    EIGEN_DEVICE_FUNC inline const NestByValue<Derived> nestByValue() const;\n    EIGEN_DEVICE_FUNC inline const ForceAlignedAccess<Derived> forceAlignedAccess() const;\n    EIGEN_DEVICE_FUNC inline ForceAlignedAccess<Derived> forceAlignedAccess();\n    template<bool Enable> EIGEN_DEVICE_FUNC\n    inline const typename internal::conditional<Enable,ForceAlignedAccess<Derived>,Derived&>::type forceAlignedAccessIf() const;\n    template<bool Enable> EIGEN_DEVICE_FUNC\n    inline typename internal::conditional<Enable,ForceAlignedAccess<Derived>,Derived&>::type forceAlignedAccessIf();\n\n    EIGEN_DEVICE_FUNC Scalar sum() const;\n    EIGEN_DEVICE_FUNC Scalar mean() const;\n    EIGEN_DEVICE_FUNC Scalar trace() const;\n\n    EIGEN_DEVICE_FUNC Scalar prod() const;\n\n    EIGEN_DEVICE_FUNC typename internal::traits<Derived>::Scalar minCoeff() const;\n    EIGEN_DEVICE_FUNC typename internal::traits<Derived>::Scalar maxCoeff() const;\n\n    template<typename IndexType> EIGEN_DEVICE_FUNC\n    typename internal::traits<Derived>::Scalar minCoeff(IndexType* row, IndexType* col) const;\n    template<typename IndexType> EIGEN_DEVICE_FUNC\n    typename internal::traits<Derived>::Scalar maxCoeff(IndexType* row, IndexType* col) const;\n    template<typename IndexType> EIGEN_DEVICE_FUNC\n    typename internal::traits<Derived>::Scalar minCoeff(IndexType* index) const;\n    template<typename IndexType> EIGEN_DEVICE_FUNC\n    typename internal::traits<Derived>::Scalar maxCoeff(IndexType* index) const;\n\n    template<typename BinaryOp>\n    EIGEN_DEVICE_FUNC\n    Scalar redux(const BinaryOp& func) const;\n\n    template<typename Visitor>\n    EIGEN_DEVICE_FUNC\n    void visit(Visitor& func) const;\n\n    inline const WithFormat<Derived> format(const IOFormat& fmt) const;\n\n    /** \\returns the unique coefficient of a 1x1 expression */\n    EIGEN_DEVICE_FUNC\n    CoeffReturnType value() const\n    {\n      EIGEN_STATIC_ASSERT_SIZE_1x1(Derived)\n      eigen_assert(this->rows() == 1 && this->cols() == 1);\n      return derived().coeff(0,0);\n    }\n\n    bool all() const;\n    bool any() const;\n    Index count() const;\n\n    typedef VectorwiseOp<Derived, Horizontal> RowwiseReturnType;\n    typedef const VectorwiseOp<const Derived, Horizontal> ConstRowwiseReturnType;\n    typedef VectorwiseOp<Derived, Vertical> ColwiseReturnType;\n    typedef const VectorwiseOp<const Derived, Vertical> ConstColwiseReturnType;\n\n    /** \\returns a VectorwiseOp wrapper of *this providing additional partial reduction operations\n    *\n    * Example: \\include MatrixBase_rowwise.cpp\n    * Output: \\verbinclude MatrixBase_rowwise.out\n    *\n    * \\sa colwise(), class VectorwiseOp, \\ref TutorialReductionsVisitorsBroadcasting\n    */\n    //Code moved here due to a CUDA compiler bug\n    EIGEN_DEVICE_FUNC inline ConstRowwiseReturnType rowwise() const {\n      return ConstRowwiseReturnType(derived());\n    }\n    EIGEN_DEVICE_FUNC RowwiseReturnType rowwise();\n\n    /** \\returns a VectorwiseOp wrapper of *this providing additional partial reduction operations\n    *\n    * Example: \\include MatrixBase_colwise.cpp\n    * Output: \\verbinclude MatrixBase_colwise.out\n    *\n    * \\sa rowwise(), class VectorwiseOp, \\ref TutorialReductionsVisitorsBroadcasting\n    */\n    EIGEN_DEVICE_FUNC inline ConstColwiseReturnType colwise() const {\n      return ConstColwiseReturnType(derived());\n    }\n    EIGEN_DEVICE_FUNC ColwiseReturnType colwise();\n\n    typedef CwiseNullaryOp<internal::scalar_random_op<Scalar>,PlainObject> RandomReturnType;\n    static const RandomReturnType Random(Index rows, Index cols);\n    static const RandomReturnType Random(Index size);\n    static const RandomReturnType Random();\n\n    template<typename ThenDerived,typename ElseDerived>\n    const Select<Derived,ThenDerived,ElseDerived>\n    select(const DenseBase<ThenDerived>& thenMatrix,\n           const DenseBase<ElseDerived>& elseMatrix) const;\n\n    template<typename ThenDerived>\n    inline const Select<Derived,ThenDerived, typename ThenDerived::ConstantReturnType>\n    select(const DenseBase<ThenDerived>& thenMatrix, const typename ThenDerived::Scalar& elseScalar) const;\n\n    template<typename ElseDerived>\n    inline const Select<Derived, typename ElseDerived::ConstantReturnType, ElseDerived >\n    select(const typename ElseDerived::Scalar& thenScalar, const DenseBase<ElseDerived>& elseMatrix) const;\n\n    template<int p> RealScalar lpNorm() const;\n\n    template<int RowFactor, int ColFactor>\n    EIGEN_DEVICE_FUNC\n    const Replicate<Derived,RowFactor,ColFactor> replicate() const;\n    /**\n    * \\return an expression of the replication of \\c *this\n    *\n    * Example: \\include MatrixBase_replicate_int_int.cpp\n    * Output: \\verbinclude MatrixBase_replicate_int_int.out\n    *\n    * \\sa VectorwiseOp::replicate(), DenseBase::replicate<int,int>(), class Replicate\n    */\n    //Code moved here due to a CUDA compiler bug\n    EIGEN_DEVICE_FUNC\n    const Replicate<Derived, Dynamic, Dynamic> replicate(Index rowFactor, Index colFactor) const\n    {\n      return Replicate<Derived, Dynamic, Dynamic>(derived(), rowFactor, colFactor);\n    }\n\n    typedef Reverse<Derived, BothDirections> ReverseReturnType;\n    typedef const Reverse<const Derived, BothDirections> ConstReverseReturnType;\n    EIGEN_DEVICE_FUNC ReverseReturnType reverse();\n    /** This is the const version of reverse(). */\n    //Code moved here due to a CUDA compiler bug\n    EIGEN_DEVICE_FUNC ConstReverseReturnType reverse() const\n    {\n      return ConstReverseReturnType(derived());\n    }\n    EIGEN_DEVICE_FUNC void reverseInPlace();\n\n#define EIGEN_CURRENT_STORAGE_BASE_CLASS Eigen::DenseBase\n#define EIGEN_DOC_BLOCK_ADDONS_NOT_INNER_PANEL\n#define EIGEN_DOC_BLOCK_ADDONS_INNER_PANEL_IF(COND)\n#   include \"../plugins/BlockMethods.h\"\n#   ifdef EIGEN_DENSEBASE_PLUGIN\n#     include EIGEN_DENSEBASE_PLUGIN\n#   endif\n#undef EIGEN_CURRENT_STORAGE_BASE_CLASS\n#undef EIGEN_DOC_BLOCK_ADDONS_NOT_INNER_PANEL\n#undef EIGEN_DOC_BLOCK_ADDONS_INNER_PANEL_IF\n\n    // disable the use of evalTo for dense objects with a nice compilation error\n    template<typename Dest>\n    EIGEN_DEVICE_FUNC\n    inline void evalTo(Dest& ) const\n    {\n      EIGEN_STATIC_ASSERT((internal::is_same<Dest,void>::value),THE_EVAL_EVALTO_FUNCTION_SHOULD_NEVER_BE_CALLED_FOR_DENSE_OBJECTS);\n    }\n\n  protected:\n    /** Default constructor. Do nothing. */\n    EIGEN_DEVICE_FUNC DenseBase()\n    {\n      /* Just checks for self-consistency of the flags.\n       * Only do it when debugging Eigen, as this borders on paranoiac and could slow compilation down\n       */\n#ifdef EIGEN_INTERNAL_DEBUGGING\n      EIGEN_STATIC_ASSERT((EIGEN_IMPLIES(MaxRowsAtCompileTime==1 && MaxColsAtCompileTime!=1, int(IsRowMajor))\n                        && EIGEN_IMPLIES(MaxColsAtCompileTime==1 && MaxRowsAtCompileTime!=1, int(!IsRowMajor))),\n                          INVALID_STORAGE_ORDER_FOR_THIS_VECTOR_EXPRESSION)\n#endif\n    }\n\n  private:\n    EIGEN_DEVICE_FUNC explicit DenseBase(int);\n    EIGEN_DEVICE_FUNC DenseBase(int,int);\n    template<typename OtherDerived> EIGEN_DEVICE_FUNC explicit DenseBase(const DenseBase<OtherDerived>&);\n};\n\n} // end namespace Eigen\n\n#endif // EIGEN_DENSEBASE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/DenseCoeffsBase.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2006-2010 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_DENSECOEFFSBASE_H\n#define EIGEN_DENSECOEFFSBASE_H\n\nnamespace Eigen {\n\nnamespace internal {\ntemplate<typename T> struct add_const_on_value_type_if_arithmetic\n{\n  typedef typename conditional<is_arithmetic<T>::value, T, typename add_const_on_value_type<T>::type>::type type;\n};\n}\n\n/** \\brief Base class providing read-only coefficient access to matrices and arrays.\n  * \\ingroup Core_Module\n  * \\tparam Derived Type of the derived class\n  * \\tparam #ReadOnlyAccessors Constant indicating read-only access\n  *\n  * This class defines the \\c operator() \\c const function and friends, which can be used to read specific\n  * entries of a matrix or array.\n  * \n  * \\sa DenseCoeffsBase<Derived, WriteAccessors>, DenseCoeffsBase<Derived, DirectAccessors>,\n  *     \\ref TopicClassHierarchy\n  */\ntemplate<typename Derived>\nclass DenseCoeffsBase<Derived,ReadOnlyAccessors> : public EigenBase<Derived>\n{\n  public:\n    typedef typename internal::traits<Derived>::StorageKind StorageKind;\n    typedef typename internal::traits<Derived>::Scalar Scalar;\n    typedef typename internal::packet_traits<Scalar>::type PacketScalar;\n\n    // Explanation for this CoeffReturnType typedef.\n    // - This is the return type of the coeff() method.\n    // - The LvalueBit means exactly that we can offer a coeffRef() method, which means exactly that we can get references\n    // to coeffs, which means exactly that we can have coeff() return a const reference (as opposed to returning a value).\n    // - The is_artihmetic check is required since \"const int\", \"const double\", etc. will cause warnings on some systems\n    // while the declaration of \"const T\", where T is a non arithmetic type does not. Always returning \"const Scalar&\" is\n    // not possible, since the underlying expressions might not offer a valid address the reference could be referring to.\n    typedef typename internal::conditional<bool(internal::traits<Derived>::Flags&LvalueBit),\n                         const Scalar&,\n                         typename internal::conditional<internal::is_arithmetic<Scalar>::value, Scalar, const Scalar>::type\n                     >::type CoeffReturnType;\n\n    typedef typename internal::add_const_on_value_type_if_arithmetic<\n                         typename internal::packet_traits<Scalar>::type\n                     >::type PacketReturnType;\n\n    typedef EigenBase<Derived> Base;\n    using Base::rows;\n    using Base::cols;\n    using Base::size;\n    using Base::derived;\n\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Index rowIndexByOuterInner(Index outer, Index inner) const\n    {\n      return int(Derived::RowsAtCompileTime) == 1 ? 0\n          : int(Derived::ColsAtCompileTime) == 1 ? inner\n          : int(Derived::Flags)&RowMajorBit ? outer\n          : inner;\n    }\n\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Index colIndexByOuterInner(Index outer, Index inner) const\n    {\n      return int(Derived::ColsAtCompileTime) == 1 ? 0\n          : int(Derived::RowsAtCompileTime) == 1 ? inner\n          : int(Derived::Flags)&RowMajorBit ? inner\n          : outer;\n    }\n\n    /** Short version: don't use this function, use\n      * \\link operator()(Index,Index) const \\endlink instead.\n      *\n      * Long version: this function is similar to\n      * \\link operator()(Index,Index) const \\endlink, but without the assertion.\n      * Use this for limiting the performance cost of debugging code when doing\n      * repeated coefficient access. Only use this when it is guaranteed that the\n      * parameters \\a row and \\a col are in range.\n      *\n      * If EIGEN_INTERNAL_DEBUGGING is defined, an assertion will be made, making this\n      * function equivalent to \\link operator()(Index,Index) const \\endlink.\n      *\n      * \\sa operator()(Index,Index) const, coeffRef(Index,Index), coeff(Index) const\n      */\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE CoeffReturnType coeff(Index row, Index col) const\n    {\n      eigen_internal_assert(row >= 0 && row < rows()\n                         && col >= 0 && col < cols());\n      return internal::evaluator<Derived>(derived()).coeff(row,col);\n    }\n\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE CoeffReturnType coeffByOuterInner(Index outer, Index inner) const\n    {\n      return coeff(rowIndexByOuterInner(outer, inner),\n                   colIndexByOuterInner(outer, inner));\n    }\n\n    /** \\returns the coefficient at given the given row and column.\n      *\n      * \\sa operator()(Index,Index), operator[](Index)\n      */\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE CoeffReturnType operator()(Index row, Index col) const\n    {\n      eigen_assert(row >= 0 && row < rows()\n          && col >= 0 && col < cols());\n      return coeff(row, col);\n    }\n\n    /** Short version: don't use this function, use\n      * \\link operator[](Index) const \\endlink instead.\n      *\n      * Long version: this function is similar to\n      * \\link operator[](Index) const \\endlink, but without the assertion.\n      * Use this for limiting the performance cost of debugging code when doing\n      * repeated coefficient access. Only use this when it is guaranteed that the\n      * parameter \\a index is in range.\n      *\n      * If EIGEN_INTERNAL_DEBUGGING is defined, an assertion will be made, making this\n      * function equivalent to \\link operator[](Index) const \\endlink.\n      *\n      * \\sa operator[](Index) const, coeffRef(Index), coeff(Index,Index) const\n      */\n\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE CoeffReturnType\n    coeff(Index index) const\n    {\n      EIGEN_STATIC_ASSERT(internal::evaluator<Derived>::Flags & LinearAccessBit,\n                          THIS_COEFFICIENT_ACCESSOR_TAKING_ONE_ACCESS_IS_ONLY_FOR_EXPRESSIONS_ALLOWING_LINEAR_ACCESS)\n      eigen_internal_assert(index >= 0 && index < size());\n      return internal::evaluator<Derived>(derived()).coeff(index);\n    }\n\n\n    /** \\returns the coefficient at given index.\n      *\n      * This method is allowed only for vector expressions, and for matrix expressions having the LinearAccessBit.\n      *\n      * \\sa operator[](Index), operator()(Index,Index) const, x() const, y() const,\n      * z() const, w() const\n      */\n\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE CoeffReturnType\n    operator[](Index index) const\n    {\n      EIGEN_STATIC_ASSERT(Derived::IsVectorAtCompileTime,\n                          THE_BRACKET_OPERATOR_IS_ONLY_FOR_VECTORS__USE_THE_PARENTHESIS_OPERATOR_INSTEAD)\n      eigen_assert(index >= 0 && index < size());\n      return coeff(index);\n    }\n\n    /** \\returns the coefficient at given index.\n      *\n      * This is synonymous to operator[](Index) const.\n      *\n      * This method is allowed only for vector expressions, and for matrix expressions having the LinearAccessBit.\n      *\n      * \\sa operator[](Index), operator()(Index,Index) const, x() const, y() const,\n      * z() const, w() const\n      */\n\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE CoeffReturnType\n    operator()(Index index) const\n    {\n      eigen_assert(index >= 0 && index < size());\n      return coeff(index);\n    }\n\n    /** equivalent to operator[](0).  */\n\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE CoeffReturnType\n    x() const { return (*this)[0]; }\n\n    /** equivalent to operator[](1).  */\n\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE CoeffReturnType\n    y() const\n    {\n      EIGEN_STATIC_ASSERT(Derived::SizeAtCompileTime==-1 || Derived::SizeAtCompileTime>=2, OUT_OF_RANGE_ACCESS);\n      return (*this)[1];\n    }\n\n    /** equivalent to operator[](2).  */\n\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE CoeffReturnType\n    z() const\n    {\n      EIGEN_STATIC_ASSERT(Derived::SizeAtCompileTime==-1 || Derived::SizeAtCompileTime>=3, OUT_OF_RANGE_ACCESS);\n      return (*this)[2];\n    }\n\n    /** equivalent to operator[](3).  */\n\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE CoeffReturnType\n    w() const\n    {\n      EIGEN_STATIC_ASSERT(Derived::SizeAtCompileTime==-1 || Derived::SizeAtCompileTime>=4, OUT_OF_RANGE_ACCESS);\n      return (*this)[3];\n    }\n\n    /** \\internal\n      * \\returns the packet of coefficients starting at the given row and column. It is your responsibility\n      * to ensure that a packet really starts there. This method is only available on expressions having the\n      * PacketAccessBit.\n      *\n      * The \\a LoadMode parameter may have the value \\a #Aligned or \\a #Unaligned. Its effect is to select\n      * the appropriate vectorization instruction. Aligned access is faster, but is only possible for packets\n      * starting at an address which is a multiple of the packet size.\n      */\n\n    template<int LoadMode>\n    EIGEN_STRONG_INLINE PacketReturnType packet(Index row, Index col) const\n    {\n      typedef typename internal::packet_traits<Scalar>::type DefaultPacketType;\n      eigen_internal_assert(row >= 0 && row < rows() && col >= 0 && col < cols());\n      return internal::evaluator<Derived>(derived()).template packet<LoadMode,DefaultPacketType>(row,col);\n    }\n\n\n    /** \\internal */\n    template<int LoadMode>\n    EIGEN_STRONG_INLINE PacketReturnType packetByOuterInner(Index outer, Index inner) const\n    {\n      return packet<LoadMode>(rowIndexByOuterInner(outer, inner),\n                              colIndexByOuterInner(outer, inner));\n    }\n\n    /** \\internal\n      * \\returns the packet of coefficients starting at the given index. It is your responsibility\n      * to ensure that a packet really starts there. This method is only available on expressions having the\n      * PacketAccessBit and the LinearAccessBit.\n      *\n      * The \\a LoadMode parameter may have the value \\a #Aligned or \\a #Unaligned. Its effect is to select\n      * the appropriate vectorization instruction. Aligned access is faster, but is only possible for packets\n      * starting at an address which is a multiple of the packet size.\n      */\n\n    template<int LoadMode>\n    EIGEN_STRONG_INLINE PacketReturnType packet(Index index) const\n    {\n      EIGEN_STATIC_ASSERT(internal::evaluator<Derived>::Flags & LinearAccessBit,\n                          THIS_COEFFICIENT_ACCESSOR_TAKING_ONE_ACCESS_IS_ONLY_FOR_EXPRESSIONS_ALLOWING_LINEAR_ACCESS)\n      typedef typename internal::packet_traits<Scalar>::type DefaultPacketType;\n      eigen_internal_assert(index >= 0 && index < size());\n      return internal::evaluator<Derived>(derived()).template packet<LoadMode,DefaultPacketType>(index);\n    }\n\n  protected:\n    // explanation: DenseBase is doing \"using ...\" on the methods from DenseCoeffsBase.\n    // But some methods are only available in the DirectAccess case.\n    // So we add dummy methods here with these names, so that \"using... \" doesn't fail.\n    // It's not private so that the child class DenseBase can access them, and it's not public\n    // either since it's an implementation detail, so has to be protected.\n    void coeffRef();\n    void coeffRefByOuterInner();\n    void writePacket();\n    void writePacketByOuterInner();\n    void copyCoeff();\n    void copyCoeffByOuterInner();\n    void copyPacket();\n    void copyPacketByOuterInner();\n    void stride();\n    void innerStride();\n    void outerStride();\n    void rowStride();\n    void colStride();\n};\n\n/** \\brief Base class providing read/write coefficient access to matrices and arrays.\n  * \\ingroup Core_Module\n  * \\tparam Derived Type of the derived class\n  * \\tparam #WriteAccessors Constant indicating read/write access\n  *\n  * This class defines the non-const \\c operator() function and friends, which can be used to write specific\n  * entries of a matrix or array. This class inherits DenseCoeffsBase<Derived, ReadOnlyAccessors> which\n  * defines the const variant for reading specific entries.\n  * \n  * \\sa DenseCoeffsBase<Derived, DirectAccessors>, \\ref TopicClassHierarchy\n  */\ntemplate<typename Derived>\nclass DenseCoeffsBase<Derived, WriteAccessors> : public DenseCoeffsBase<Derived, ReadOnlyAccessors>\n{\n  public:\n\n    typedef DenseCoeffsBase<Derived, ReadOnlyAccessors> Base;\n\n    typedef typename internal::traits<Derived>::StorageKind StorageKind;\n    typedef typename internal::traits<Derived>::Scalar Scalar;\n    typedef typename internal::packet_traits<Scalar>::type PacketScalar;\n    typedef typename NumTraits<Scalar>::Real RealScalar;\n\n    using Base::coeff;\n    using Base::rows;\n    using Base::cols;\n    using Base::size;\n    using Base::derived;\n    using Base::rowIndexByOuterInner;\n    using Base::colIndexByOuterInner;\n    using Base::operator[];\n    using Base::operator();\n    using Base::x;\n    using Base::y;\n    using Base::z;\n    using Base::w;\n\n    /** Short version: don't use this function, use\n      * \\link operator()(Index,Index) \\endlink instead.\n      *\n      * Long version: this function is similar to\n      * \\link operator()(Index,Index) \\endlink, but without the assertion.\n      * Use this for limiting the performance cost of debugging code when doing\n      * repeated coefficient access. Only use this when it is guaranteed that the\n      * parameters \\a row and \\a col are in range.\n      *\n      * If EIGEN_INTERNAL_DEBUGGING is defined, an assertion will be made, making this\n      * function equivalent to \\link operator()(Index,Index) \\endlink.\n      *\n      * \\sa operator()(Index,Index), coeff(Index, Index) const, coeffRef(Index)\n      */\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Scalar& coeffRef(Index row, Index col)\n    {\n      eigen_internal_assert(row >= 0 && row < rows()\n                         && col >= 0 && col < cols());\n      return internal::evaluator<Derived>(derived()).coeffRef(row,col);\n    }\n\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Scalar&\n    coeffRefByOuterInner(Index outer, Index inner)\n    {\n      return coeffRef(rowIndexByOuterInner(outer, inner),\n                      colIndexByOuterInner(outer, inner));\n    }\n\n    /** \\returns a reference to the coefficient at given the given row and column.\n      *\n      * \\sa operator[](Index)\n      */\n\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Scalar&\n    operator()(Index row, Index col)\n    {\n      eigen_assert(row >= 0 && row < rows()\n          && col >= 0 && col < cols());\n      return coeffRef(row, col);\n    }\n\n\n    /** Short version: don't use this function, use\n      * \\link operator[](Index) \\endlink instead.\n      *\n      * Long version: this function is similar to\n      * \\link operator[](Index) \\endlink, but without the assertion.\n      * Use this for limiting the performance cost of debugging code when doing\n      * repeated coefficient access. Only use this when it is guaranteed that the\n      * parameters \\a row and \\a col are in range.\n      *\n      * If EIGEN_INTERNAL_DEBUGGING is defined, an assertion will be made, making this\n      * function equivalent to \\link operator[](Index) \\endlink.\n      *\n      * \\sa operator[](Index), coeff(Index) const, coeffRef(Index,Index)\n      */\n\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Scalar&\n    coeffRef(Index index)\n    {\n      EIGEN_STATIC_ASSERT(internal::evaluator<Derived>::Flags & LinearAccessBit,\n                          THIS_COEFFICIENT_ACCESSOR_TAKING_ONE_ACCESS_IS_ONLY_FOR_EXPRESSIONS_ALLOWING_LINEAR_ACCESS)\n      eigen_internal_assert(index >= 0 && index < size());\n      return internal::evaluator<Derived>(derived()).coeffRef(index);\n    }\n\n    /** \\returns a reference to the coefficient at given index.\n      *\n      * This method is allowed only for vector expressions, and for matrix expressions having the LinearAccessBit.\n      *\n      * \\sa operator[](Index) const, operator()(Index,Index), x(), y(), z(), w()\n      */\n\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Scalar&\n    operator[](Index index)\n    {\n      EIGEN_STATIC_ASSERT(Derived::IsVectorAtCompileTime,\n                          THE_BRACKET_OPERATOR_IS_ONLY_FOR_VECTORS__USE_THE_PARENTHESIS_OPERATOR_INSTEAD)\n      eigen_assert(index >= 0 && index < size());\n      return coeffRef(index);\n    }\n\n    /** \\returns a reference to the coefficient at given index.\n      *\n      * This is synonymous to operator[](Index).\n      *\n      * This method is allowed only for vector expressions, and for matrix expressions having the LinearAccessBit.\n      *\n      * \\sa operator[](Index) const, operator()(Index,Index), x(), y(), z(), w()\n      */\n\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Scalar&\n    operator()(Index index)\n    {\n      eigen_assert(index >= 0 && index < size());\n      return coeffRef(index);\n    }\n\n    /** equivalent to operator[](0).  */\n\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Scalar&\n    x() { return (*this)[0]; }\n\n    /** equivalent to operator[](1).  */\n\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Scalar&\n    y()\n    {\n      EIGEN_STATIC_ASSERT(Derived::SizeAtCompileTime==-1 || Derived::SizeAtCompileTime>=2, OUT_OF_RANGE_ACCESS);\n      return (*this)[1];\n    }\n\n    /** equivalent to operator[](2).  */\n\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Scalar&\n    z()\n    {\n      EIGEN_STATIC_ASSERT(Derived::SizeAtCompileTime==-1 || Derived::SizeAtCompileTime>=3, OUT_OF_RANGE_ACCESS);\n      return (*this)[2];\n    }\n\n    /** equivalent to operator[](3).  */\n\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Scalar&\n    w()\n    {\n      EIGEN_STATIC_ASSERT(Derived::SizeAtCompileTime==-1 || Derived::SizeAtCompileTime>=4, OUT_OF_RANGE_ACCESS);\n      return (*this)[3];\n    }\n};\n\n/** \\brief Base class providing direct read-only coefficient access to matrices and arrays.\n  * \\ingroup Core_Module\n  * \\tparam Derived Type of the derived class\n  * \\tparam #DirectAccessors Constant indicating direct access\n  *\n  * This class defines functions to work with strides which can be used to access entries directly. This class\n  * inherits DenseCoeffsBase<Derived, ReadOnlyAccessors> which defines functions to access entries read-only using\n  * \\c operator() .\n  *\n  * \\sa \\blank \\ref TopicClassHierarchy\n  */\ntemplate<typename Derived>\nclass DenseCoeffsBase<Derived, DirectAccessors> : public DenseCoeffsBase<Derived, ReadOnlyAccessors>\n{\n  public:\n\n    typedef DenseCoeffsBase<Derived, ReadOnlyAccessors> Base;\n    typedef typename internal::traits<Derived>::Scalar Scalar;\n    typedef typename NumTraits<Scalar>::Real RealScalar;\n\n    using Base::rows;\n    using Base::cols;\n    using Base::size;\n    using Base::derived;\n\n    /** \\returns the pointer increment between two consecutive elements within a slice in the inner direction.\n      *\n      * \\sa outerStride(), rowStride(), colStride()\n      */\n    EIGEN_DEVICE_FUNC\n    inline Index innerStride() const\n    {\n      return derived().innerStride();\n    }\n\n    /** \\returns the pointer increment between two consecutive inner slices (for example, between two consecutive columns\n      *          in a column-major matrix).\n      *\n      * \\sa innerStride(), rowStride(), colStride()\n      */\n    EIGEN_DEVICE_FUNC\n    inline Index outerStride() const\n    {\n      return derived().outerStride();\n    }\n\n    // FIXME shall we remove it ?\n    inline Index stride() const\n    {\n      return Derived::IsVectorAtCompileTime ? innerStride() : outerStride();\n    }\n\n    /** \\returns the pointer increment between two consecutive rows.\n      *\n      * \\sa innerStride(), outerStride(), colStride()\n      */\n    EIGEN_DEVICE_FUNC\n    inline Index rowStride() const\n    {\n      return Derived::IsRowMajor ? outerStride() : innerStride();\n    }\n\n    /** \\returns the pointer increment between two consecutive columns.\n      *\n      * \\sa innerStride(), outerStride(), rowStride()\n      */\n    EIGEN_DEVICE_FUNC\n    inline Index colStride() const\n    {\n      return Derived::IsRowMajor ? innerStride() : outerStride();\n    }\n};\n\n/** \\brief Base class providing direct read/write coefficient access to matrices and arrays.\n  * \\ingroup Core_Module\n  * \\tparam Derived Type of the derived class\n  * \\tparam #DirectWriteAccessors Constant indicating direct access\n  *\n  * This class defines functions to work with strides which can be used to access entries directly. This class\n  * inherits DenseCoeffsBase<Derived, WriteAccessors> which defines functions to access entries read/write using\n  * \\c operator().\n  *\n  * \\sa \\blank \\ref TopicClassHierarchy\n  */\ntemplate<typename Derived>\nclass DenseCoeffsBase<Derived, DirectWriteAccessors>\n  : public DenseCoeffsBase<Derived, WriteAccessors>\n{\n  public:\n\n    typedef DenseCoeffsBase<Derived, WriteAccessors> Base;\n    typedef typename internal::traits<Derived>::Scalar Scalar;\n    typedef typename NumTraits<Scalar>::Real RealScalar;\n\n    using Base::rows;\n    using Base::cols;\n    using Base::size;\n    using Base::derived;\n\n    /** \\returns the pointer increment between two consecutive elements within a slice in the inner direction.\n      *\n      * \\sa outerStride(), rowStride(), colStride()\n      */\n    EIGEN_DEVICE_FUNC\n    inline Index innerStride() const\n    {\n      return derived().innerStride();\n    }\n\n    /** \\returns the pointer increment between two consecutive inner slices (for example, between two consecutive columns\n      *          in a column-major matrix).\n      *\n      * \\sa innerStride(), rowStride(), colStride()\n      */\n    EIGEN_DEVICE_FUNC\n    inline Index outerStride() const\n    {\n      return derived().outerStride();\n    }\n\n    // FIXME shall we remove it ?\n    inline Index stride() const\n    {\n      return Derived::IsVectorAtCompileTime ? innerStride() : outerStride();\n    }\n\n    /** \\returns the pointer increment between two consecutive rows.\n      *\n      * \\sa innerStride(), outerStride(), colStride()\n      */\n    EIGEN_DEVICE_FUNC\n    inline Index rowStride() const\n    {\n      return Derived::IsRowMajor ? outerStride() : innerStride();\n    }\n\n    /** \\returns the pointer increment between two consecutive columns.\n      *\n      * \\sa innerStride(), outerStride(), rowStride()\n      */\n    EIGEN_DEVICE_FUNC\n    inline Index colStride() const\n    {\n      return Derived::IsRowMajor ? innerStride() : outerStride();\n    }\n};\n\nnamespace internal {\n\ntemplate<int Alignment, typename Derived, bool JustReturnZero>\nstruct first_aligned_impl\n{\n  static inline Index run(const Derived&)\n  { return 0; }\n};\n\ntemplate<int Alignment, typename Derived>\nstruct first_aligned_impl<Alignment, Derived, false>\n{\n  static inline Index run(const Derived& m)\n  {\n    return internal::first_aligned<Alignment>(m.data(), m.size());\n  }\n};\n\n/** \\internal \\returns the index of the first element of the array stored by \\a m that is properly aligned with respect to \\a Alignment for vectorization.\n  *\n  * \\tparam Alignment requested alignment in Bytes.\n  *\n  * There is also the variant first_aligned(const Scalar*, Integer) defined in Memory.h. See it for more\n  * documentation.\n  */\ntemplate<int Alignment, typename Derived>\nstatic inline Index first_aligned(const DenseBase<Derived>& m)\n{\n  enum { ReturnZero = (int(evaluator<Derived>::Alignment) >= Alignment) || !(Derived::Flags & DirectAccessBit) };\n  return first_aligned_impl<Alignment, Derived, ReturnZero>::run(m.derived());\n}\n\ntemplate<typename Derived>\nstatic inline Index first_default_aligned(const DenseBase<Derived>& m)\n{\n  typedef typename Derived::Scalar Scalar;\n  typedef typename packet_traits<Scalar>::type DefaultPacketType;\n  return internal::first_aligned<int(unpacket_traits<DefaultPacketType>::alignment),Derived>(m);\n}\n\ntemplate<typename Derived, bool HasDirectAccess = has_direct_access<Derived>::ret>\nstruct inner_stride_at_compile_time\n{\n  enum { ret = traits<Derived>::InnerStrideAtCompileTime };\n};\n\ntemplate<typename Derived>\nstruct inner_stride_at_compile_time<Derived, false>\n{\n  enum { ret = 0 };\n};\n\ntemplate<typename Derived, bool HasDirectAccess = has_direct_access<Derived>::ret>\nstruct outer_stride_at_compile_time\n{\n  enum { ret = traits<Derived>::OuterStrideAtCompileTime };\n};\n\ntemplate<typename Derived>\nstruct outer_stride_at_compile_time<Derived, false>\n{\n  enum { ret = 0 };\n};\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_DENSECOEFFSBASE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/DenseStorage.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2006-2009 Benoit Jacob <jacob.benoit.1@gmail.com>\n// Copyright (C) 2010-2013 Hauke Heibel <hauke.heibel@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_MATRIXSTORAGE_H\n#define EIGEN_MATRIXSTORAGE_H\n\n#ifdef EIGEN_DENSE_STORAGE_CTOR_PLUGIN\n  #define EIGEN_INTERNAL_DENSE_STORAGE_CTOR_PLUGIN EIGEN_DENSE_STORAGE_CTOR_PLUGIN;\n#else\n  #define EIGEN_INTERNAL_DENSE_STORAGE_CTOR_PLUGIN\n#endif\n\nnamespace Eigen {\n\nnamespace internal {\n\nstruct constructor_without_unaligned_array_assert {};\n\ntemplate<typename T, int Size>\nEIGEN_DEVICE_FUNC\nvoid check_static_allocation_size()\n{\n  // if EIGEN_STACK_ALLOCATION_LIMIT is defined to 0, then no limit\n  #if EIGEN_STACK_ALLOCATION_LIMIT\n  EIGEN_STATIC_ASSERT(Size * sizeof(T) <= EIGEN_STACK_ALLOCATION_LIMIT, OBJECT_ALLOCATED_ON_STACK_IS_TOO_BIG);\n  #endif\n}\n\n/** \\internal\n  * Static array. If the MatrixOrArrayOptions require auto-alignment, the array will be automatically aligned:\n  * to 16 bytes boundary if the total size is a multiple of 16 bytes.\n  */\ntemplate <typename T, int Size, int MatrixOrArrayOptions,\n          int Alignment = (MatrixOrArrayOptions&DontAlign) ? 0\n                        : compute_default_alignment<T,Size>::value >\nstruct plain_array\n{\n  T array[Size];\n\n  EIGEN_DEVICE_FUNC\n  plain_array()\n  { \n    check_static_allocation_size<T,Size>();\n  }\n\n  EIGEN_DEVICE_FUNC\n  plain_array(constructor_without_unaligned_array_assert)\n  { \n    check_static_allocation_size<T,Size>();\n  }\n};\n\n#if defined(EIGEN_DISABLE_UNALIGNED_ARRAY_ASSERT)\n  #define EIGEN_MAKE_UNALIGNED_ARRAY_ASSERT(sizemask)\n#elif EIGEN_GNUC_AT_LEAST(4,7) \n  // GCC 4.7 is too aggressive in its optimizations and remove the alignement test based on the fact the array is declared to be aligned.\n  // See this bug report: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53900\n  // Hiding the origin of the array pointer behind a function argument seems to do the trick even if the function is inlined:\n  template<typename PtrType>\n  EIGEN_ALWAYS_INLINE PtrType eigen_unaligned_array_assert_workaround_gcc47(PtrType array) { return array; }\n  #define EIGEN_MAKE_UNALIGNED_ARRAY_ASSERT(sizemask) \\\n    eigen_assert((internal::UIntPtr(eigen_unaligned_array_assert_workaround_gcc47(array)) & (sizemask)) == 0 \\\n              && \"this assertion is explained here: \" \\\n              \"http://eigen.tuxfamily.org/dox-devel/group__TopicUnalignedArrayAssert.html\" \\\n              \" **** READ THIS WEB PAGE !!! ****\");\n#else\n  #define EIGEN_MAKE_UNALIGNED_ARRAY_ASSERT(sizemask) \\\n    eigen_assert((internal::UIntPtr(array) & (sizemask)) == 0 \\\n              && \"this assertion is explained here: \" \\\n              \"http://eigen.tuxfamily.org/dox-devel/group__TopicUnalignedArrayAssert.html\" \\\n              \" **** READ THIS WEB PAGE !!! ****\");\n#endif\n\ntemplate <typename T, int Size, int MatrixOrArrayOptions>\nstruct plain_array<T, Size, MatrixOrArrayOptions, 8>\n{\n  EIGEN_ALIGN_TO_BOUNDARY(8) T array[Size];\n\n  EIGEN_DEVICE_FUNC\n  plain_array() \n  {\n    EIGEN_MAKE_UNALIGNED_ARRAY_ASSERT(7);\n    check_static_allocation_size<T,Size>();\n  }\n\n  EIGEN_DEVICE_FUNC\n  plain_array(constructor_without_unaligned_array_assert) \n  { \n    check_static_allocation_size<T,Size>();\n  }\n};\n\ntemplate <typename T, int Size, int MatrixOrArrayOptions>\nstruct plain_array<T, Size, MatrixOrArrayOptions, 16>\n{\n  EIGEN_ALIGN_TO_BOUNDARY(16) T array[Size];\n\n  EIGEN_DEVICE_FUNC\n  plain_array() \n  { \n    EIGEN_MAKE_UNALIGNED_ARRAY_ASSERT(15);\n    check_static_allocation_size<T,Size>();\n  }\n\n  EIGEN_DEVICE_FUNC\n  plain_array(constructor_without_unaligned_array_assert) \n  { \n    check_static_allocation_size<T,Size>();\n  }\n};\n\ntemplate <typename T, int Size, int MatrixOrArrayOptions>\nstruct plain_array<T, Size, MatrixOrArrayOptions, 32>\n{\n  EIGEN_ALIGN_TO_BOUNDARY(32) T array[Size];\n\n  EIGEN_DEVICE_FUNC\n  plain_array() \n  {\n    EIGEN_MAKE_UNALIGNED_ARRAY_ASSERT(31);\n    check_static_allocation_size<T,Size>();\n  }\n\n  EIGEN_DEVICE_FUNC\n  plain_array(constructor_without_unaligned_array_assert) \n  { \n    check_static_allocation_size<T,Size>();\n  }\n};\n\ntemplate <typename T, int Size, int MatrixOrArrayOptions>\nstruct plain_array<T, Size, MatrixOrArrayOptions, 64>\n{\n  EIGEN_ALIGN_TO_BOUNDARY(64) T array[Size];\n\n  EIGEN_DEVICE_FUNC\n  plain_array() \n  { \n    EIGEN_MAKE_UNALIGNED_ARRAY_ASSERT(63);\n    check_static_allocation_size<T,Size>();\n  }\n\n  EIGEN_DEVICE_FUNC\n  plain_array(constructor_without_unaligned_array_assert) \n  { \n    check_static_allocation_size<T,Size>();\n  }\n};\n\ntemplate <typename T, int MatrixOrArrayOptions, int Alignment>\nstruct plain_array<T, 0, MatrixOrArrayOptions, Alignment>\n{\n  T array[1];\n  EIGEN_DEVICE_FUNC plain_array() {}\n  EIGEN_DEVICE_FUNC plain_array(constructor_without_unaligned_array_assert) {}\n};\n\n} // end namespace internal\n\n/** \\internal\n  *\n  * \\class DenseStorage\n  * \\ingroup Core_Module\n  *\n  * \\brief Stores the data of a matrix\n  *\n  * This class stores the data of fixed-size, dynamic-size or mixed matrices\n  * in a way as compact as possible.\n  *\n  * \\sa Matrix\n  */\ntemplate<typename T, int Size, int _Rows, int _Cols, int _Options> class DenseStorage;\n\n// purely fixed-size matrix\ntemplate<typename T, int Size, int _Rows, int _Cols, int _Options> class DenseStorage\n{\n    internal::plain_array<T,Size,_Options> m_data;\n  public:\n    EIGEN_DEVICE_FUNC DenseStorage() {}\n    EIGEN_DEVICE_FUNC\n    explicit DenseStorage(internal::constructor_without_unaligned_array_assert)\n      : m_data(internal::constructor_without_unaligned_array_assert()) {}\n    EIGEN_DEVICE_FUNC \n    DenseStorage(const DenseStorage& other) : m_data(other.m_data) {}\n    EIGEN_DEVICE_FUNC \n    DenseStorage& operator=(const DenseStorage& other)\n    { \n      if (this != &other) m_data = other.m_data;\n      return *this; \n    }\n    EIGEN_DEVICE_FUNC DenseStorage(Index size, Index rows, Index cols) {\n      EIGEN_INTERNAL_DENSE_STORAGE_CTOR_PLUGIN\n      eigen_internal_assert(size==rows*cols && rows==_Rows && cols==_Cols);\n      EIGEN_UNUSED_VARIABLE(size);\n      EIGEN_UNUSED_VARIABLE(rows);\n      EIGEN_UNUSED_VARIABLE(cols);\n    }\n    EIGEN_DEVICE_FUNC void swap(DenseStorage& other) { std::swap(m_data,other.m_data); }\n    EIGEN_DEVICE_FUNC static Index rows(void) {return _Rows;}\n    EIGEN_DEVICE_FUNC static Index cols(void) {return _Cols;}\n    EIGEN_DEVICE_FUNC void conservativeResize(Index,Index,Index) {}\n    EIGEN_DEVICE_FUNC void resize(Index,Index,Index) {}\n    EIGEN_DEVICE_FUNC const T *data() const { return m_data.array; }\n    EIGEN_DEVICE_FUNC T *data() { return m_data.array; }\n};\n\n// null matrix\ntemplate<typename T, int _Rows, int _Cols, int _Options> class DenseStorage<T, 0, _Rows, _Cols, _Options>\n{\n  public:\n    EIGEN_DEVICE_FUNC DenseStorage() {}\n    EIGEN_DEVICE_FUNC explicit DenseStorage(internal::constructor_without_unaligned_array_assert) {}\n    EIGEN_DEVICE_FUNC DenseStorage(const DenseStorage&) {}\n    EIGEN_DEVICE_FUNC DenseStorage& operator=(const DenseStorage&) { return *this; }\n    EIGEN_DEVICE_FUNC DenseStorage(Index,Index,Index) {}\n    EIGEN_DEVICE_FUNC void swap(DenseStorage& ) {}\n    EIGEN_DEVICE_FUNC static Index rows(void) {return _Rows;}\n    EIGEN_DEVICE_FUNC static Index cols(void) {return _Cols;}\n    EIGEN_DEVICE_FUNC void conservativeResize(Index,Index,Index) {}\n    EIGEN_DEVICE_FUNC void resize(Index,Index,Index) {}\n    EIGEN_DEVICE_FUNC const T *data() const { return 0; }\n    EIGEN_DEVICE_FUNC T *data() { return 0; }\n};\n\n// more specializations for null matrices; these are necessary to resolve ambiguities\ntemplate<typename T, int _Options> class DenseStorage<T, 0, Dynamic, Dynamic, _Options>\n: public DenseStorage<T, 0, 0, 0, _Options> { };\n\ntemplate<typename T, int _Rows, int _Options> class DenseStorage<T, 0, _Rows, Dynamic, _Options>\n: public DenseStorage<T, 0, 0, 0, _Options> { };\n\ntemplate<typename T, int _Cols, int _Options> class DenseStorage<T, 0, Dynamic, _Cols, _Options>\n: public DenseStorage<T, 0, 0, 0, _Options> { };\n\n// dynamic-size matrix with fixed-size storage\ntemplate<typename T, int Size, int _Options> class DenseStorage<T, Size, Dynamic, Dynamic, _Options>\n{\n    internal::plain_array<T,Size,_Options> m_data;\n    Index m_rows;\n    Index m_cols;\n  public:\n    EIGEN_DEVICE_FUNC DenseStorage() : m_rows(0), m_cols(0) {}\n    EIGEN_DEVICE_FUNC explicit DenseStorage(internal::constructor_without_unaligned_array_assert)\n      : m_data(internal::constructor_without_unaligned_array_assert()), m_rows(0), m_cols(0) {}\n    EIGEN_DEVICE_FUNC DenseStorage(const DenseStorage& other) : m_data(other.m_data), m_rows(other.m_rows), m_cols(other.m_cols) {}\n    EIGEN_DEVICE_FUNC DenseStorage& operator=(const DenseStorage& other) \n    { \n      if (this != &other)\n      {\n        m_data = other.m_data;\n        m_rows = other.m_rows;\n        m_cols = other.m_cols;\n      }\n      return *this; \n    }\n    EIGEN_DEVICE_FUNC DenseStorage(Index, Index rows, Index cols) : m_rows(rows), m_cols(cols) {}\n    EIGEN_DEVICE_FUNC void swap(DenseStorage& other)\n    { std::swap(m_data,other.m_data); std::swap(m_rows,other.m_rows); std::swap(m_cols,other.m_cols); }\n    EIGEN_DEVICE_FUNC Index rows() const {return m_rows;}\n    EIGEN_DEVICE_FUNC Index cols() const {return m_cols;}\n    EIGEN_DEVICE_FUNC void conservativeResize(Index, Index rows, Index cols) { m_rows = rows; m_cols = cols; }\n    EIGEN_DEVICE_FUNC void resize(Index, Index rows, Index cols) { m_rows = rows; m_cols = cols; }\n    EIGEN_DEVICE_FUNC const T *data() const { return m_data.array; }\n    EIGEN_DEVICE_FUNC T *data() { return m_data.array; }\n};\n\n// dynamic-size matrix with fixed-size storage and fixed width\ntemplate<typename T, int Size, int _Cols, int _Options> class DenseStorage<T, Size, Dynamic, _Cols, _Options>\n{\n    internal::plain_array<T,Size,_Options> m_data;\n    Index m_rows;\n  public:\n    EIGEN_DEVICE_FUNC DenseStorage() : m_rows(0) {}\n    EIGEN_DEVICE_FUNC explicit DenseStorage(internal::constructor_without_unaligned_array_assert)\n      : m_data(internal::constructor_without_unaligned_array_assert()), m_rows(0) {}\n    EIGEN_DEVICE_FUNC DenseStorage(const DenseStorage& other) : m_data(other.m_data), m_rows(other.m_rows) {}\n    EIGEN_DEVICE_FUNC DenseStorage& operator=(const DenseStorage& other) \n    {\n      if (this != &other)\n      {\n        m_data = other.m_data;\n        m_rows = other.m_rows;\n      }\n      return *this; \n    }\n    EIGEN_DEVICE_FUNC DenseStorage(Index, Index rows, Index) : m_rows(rows) {}\n    EIGEN_DEVICE_FUNC void swap(DenseStorage& other) { std::swap(m_data,other.m_data); std::swap(m_rows,other.m_rows); }\n    EIGEN_DEVICE_FUNC Index rows(void) const {return m_rows;}\n    EIGEN_DEVICE_FUNC Index cols(void) const {return _Cols;}\n    EIGEN_DEVICE_FUNC void conservativeResize(Index, Index rows, Index) { m_rows = rows; }\n    EIGEN_DEVICE_FUNC void resize(Index, Index rows, Index) { m_rows = rows; }\n    EIGEN_DEVICE_FUNC const T *data() const { return m_data.array; }\n    EIGEN_DEVICE_FUNC T *data() { return m_data.array; }\n};\n\n// dynamic-size matrix with fixed-size storage and fixed height\ntemplate<typename T, int Size, int _Rows, int _Options> class DenseStorage<T, Size, _Rows, Dynamic, _Options>\n{\n    internal::plain_array<T,Size,_Options> m_data;\n    Index m_cols;\n  public:\n    EIGEN_DEVICE_FUNC DenseStorage() : m_cols(0) {}\n    EIGEN_DEVICE_FUNC explicit DenseStorage(internal::constructor_without_unaligned_array_assert)\n      : m_data(internal::constructor_without_unaligned_array_assert()), m_cols(0) {}\n    EIGEN_DEVICE_FUNC DenseStorage(const DenseStorage& other) : m_data(other.m_data), m_cols(other.m_cols) {}\n    EIGEN_DEVICE_FUNC DenseStorage& operator=(const DenseStorage& other)\n    {\n      if (this != &other)\n      {\n        m_data = other.m_data;\n        m_cols = other.m_cols;\n      }\n      return *this;\n    }\n    EIGEN_DEVICE_FUNC DenseStorage(Index, Index, Index cols) : m_cols(cols) {}\n    EIGEN_DEVICE_FUNC void swap(DenseStorage& other) { std::swap(m_data,other.m_data); std::swap(m_cols,other.m_cols); }\n    EIGEN_DEVICE_FUNC Index rows(void) const {return _Rows;}\n    EIGEN_DEVICE_FUNC Index cols(void) const {return m_cols;}\n    void conservativeResize(Index, Index, Index cols) { m_cols = cols; }\n    void resize(Index, Index, Index cols) { m_cols = cols; }\n    EIGEN_DEVICE_FUNC const T *data() const { return m_data.array; }\n    EIGEN_DEVICE_FUNC T *data() { return m_data.array; }\n};\n\n// purely dynamic matrix.\ntemplate<typename T, int _Options> class DenseStorage<T, Dynamic, Dynamic, Dynamic, _Options>\n{\n    T *m_data;\n    Index m_rows;\n    Index m_cols;\n  public:\n    EIGEN_DEVICE_FUNC DenseStorage() : m_data(0), m_rows(0), m_cols(0) {}\n    EIGEN_DEVICE_FUNC explicit DenseStorage(internal::constructor_without_unaligned_array_assert)\n       : m_data(0), m_rows(0), m_cols(0) {}\n    EIGEN_DEVICE_FUNC DenseStorage(Index size, Index rows, Index cols)\n      : m_data(internal::conditional_aligned_new_auto<T,(_Options&DontAlign)==0>(size)), m_rows(rows), m_cols(cols)\n    {\n      EIGEN_INTERNAL_DENSE_STORAGE_CTOR_PLUGIN\n      eigen_internal_assert(size==rows*cols && rows>=0 && cols >=0);\n    }\n    EIGEN_DEVICE_FUNC DenseStorage(const DenseStorage& other)\n      : m_data(internal::conditional_aligned_new_auto<T,(_Options&DontAlign)==0>(other.m_rows*other.m_cols))\n      , m_rows(other.m_rows)\n      , m_cols(other.m_cols)\n    {\n      internal::smart_copy(other.m_data, other.m_data+other.m_rows*other.m_cols, m_data);\n    }\n    EIGEN_DEVICE_FUNC DenseStorage& operator=(const DenseStorage& other)\n    {\n      if (this != &other)\n      {\n        DenseStorage tmp(other);\n        this->swap(tmp);\n      }\n      return *this;\n    }\n#if EIGEN_HAS_RVALUE_REFERENCES\n    EIGEN_DEVICE_FUNC\n    DenseStorage(DenseStorage&& other) EIGEN_NOEXCEPT\n      : m_data(std::move(other.m_data))\n      , m_rows(std::move(other.m_rows))\n      , m_cols(std::move(other.m_cols))\n    {\n      other.m_data = nullptr;\n      other.m_rows = 0;\n      other.m_cols = 0;\n    }\n    EIGEN_DEVICE_FUNC\n    DenseStorage& operator=(DenseStorage&& other) EIGEN_NOEXCEPT\n    {\n      using std::swap;\n      swap(m_data, other.m_data);\n      swap(m_rows, other.m_rows);\n      swap(m_cols, other.m_cols);\n      return *this;\n    }\n#endif\n    EIGEN_DEVICE_FUNC ~DenseStorage() { internal::conditional_aligned_delete_auto<T,(_Options&DontAlign)==0>(m_data, m_rows*m_cols); }\n    EIGEN_DEVICE_FUNC void swap(DenseStorage& other)\n    { std::swap(m_data,other.m_data); std::swap(m_rows,other.m_rows); std::swap(m_cols,other.m_cols); }\n    EIGEN_DEVICE_FUNC Index rows(void) const {return m_rows;}\n    EIGEN_DEVICE_FUNC Index cols(void) const {return m_cols;}\n    void conservativeResize(Index size, Index rows, Index cols)\n    {\n      m_data = internal::conditional_aligned_realloc_new_auto<T,(_Options&DontAlign)==0>(m_data, size, m_rows*m_cols);\n      m_rows = rows;\n      m_cols = cols;\n    }\n    EIGEN_DEVICE_FUNC void resize(Index size, Index rows, Index cols)\n    {\n      if(size != m_rows*m_cols)\n      {\n        internal::conditional_aligned_delete_auto<T,(_Options&DontAlign)==0>(m_data, m_rows*m_cols);\n        if (size)\n          m_data = internal::conditional_aligned_new_auto<T,(_Options&DontAlign)==0>(size);\n        else\n          m_data = 0;\n        EIGEN_INTERNAL_DENSE_STORAGE_CTOR_PLUGIN\n      }\n      m_rows = rows;\n      m_cols = cols;\n    }\n    EIGEN_DEVICE_FUNC const T *data() const { return m_data; }\n    EIGEN_DEVICE_FUNC T *data() { return m_data; }\n};\n\n// matrix with dynamic width and fixed height (so that matrix has dynamic size).\ntemplate<typename T, int _Rows, int _Options> class DenseStorage<T, Dynamic, _Rows, Dynamic, _Options>\n{\n    T *m_data;\n    Index m_cols;\n  public:\n    EIGEN_DEVICE_FUNC DenseStorage() : m_data(0), m_cols(0) {}\n    explicit DenseStorage(internal::constructor_without_unaligned_array_assert) : m_data(0), m_cols(0) {}\n    EIGEN_DEVICE_FUNC DenseStorage(Index size, Index rows, Index cols) : m_data(internal::conditional_aligned_new_auto<T,(_Options&DontAlign)==0>(size)), m_cols(cols)\n    {\n      EIGEN_INTERNAL_DENSE_STORAGE_CTOR_PLUGIN\n      eigen_internal_assert(size==rows*cols && rows==_Rows && cols >=0);\n      EIGEN_UNUSED_VARIABLE(rows);\n    }\n    EIGEN_DEVICE_FUNC DenseStorage(const DenseStorage& other)\n      : m_data(internal::conditional_aligned_new_auto<T,(_Options&DontAlign)==0>(_Rows*other.m_cols))\n      , m_cols(other.m_cols)\n    {\n      internal::smart_copy(other.m_data, other.m_data+_Rows*m_cols, m_data);\n    }\n    EIGEN_DEVICE_FUNC DenseStorage& operator=(const DenseStorage& other)\n    {\n      if (this != &other)\n      {\n        DenseStorage tmp(other);\n        this->swap(tmp);\n      }\n      return *this;\n    }    \n#if EIGEN_HAS_RVALUE_REFERENCES\n    EIGEN_DEVICE_FUNC\n    DenseStorage(DenseStorage&& other) EIGEN_NOEXCEPT\n      : m_data(std::move(other.m_data))\n      , m_cols(std::move(other.m_cols))\n    {\n      other.m_data = nullptr;\n      other.m_cols = 0;\n    }\n    EIGEN_DEVICE_FUNC\n    DenseStorage& operator=(DenseStorage&& other) EIGEN_NOEXCEPT\n    {\n      using std::swap;\n      swap(m_data, other.m_data);\n      swap(m_cols, other.m_cols);\n      return *this;\n    }\n#endif\n    EIGEN_DEVICE_FUNC ~DenseStorage() { internal::conditional_aligned_delete_auto<T,(_Options&DontAlign)==0>(m_data, _Rows*m_cols); }\n    EIGEN_DEVICE_FUNC void swap(DenseStorage& other) { std::swap(m_data,other.m_data); std::swap(m_cols,other.m_cols); }\n    EIGEN_DEVICE_FUNC static Index rows(void) {return _Rows;}\n    EIGEN_DEVICE_FUNC Index cols(void) const {return m_cols;}\n    EIGEN_DEVICE_FUNC void conservativeResize(Index size, Index, Index cols)\n    {\n      m_data = internal::conditional_aligned_realloc_new_auto<T,(_Options&DontAlign)==0>(m_data, size, _Rows*m_cols);\n      m_cols = cols;\n    }\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE void resize(Index size, Index, Index cols)\n    {\n      if(size != _Rows*m_cols)\n      {\n        internal::conditional_aligned_delete_auto<T,(_Options&DontAlign)==0>(m_data, _Rows*m_cols);\n        if (size)\n          m_data = internal::conditional_aligned_new_auto<T,(_Options&DontAlign)==0>(size);\n        else\n          m_data = 0;\n        EIGEN_INTERNAL_DENSE_STORAGE_CTOR_PLUGIN\n      }\n      m_cols = cols;\n    }\n    EIGEN_DEVICE_FUNC const T *data() const { return m_data; }\n    EIGEN_DEVICE_FUNC T *data() { return m_data; }\n};\n\n// matrix with dynamic height and fixed width (so that matrix has dynamic size).\ntemplate<typename T, int _Cols, int _Options> class DenseStorage<T, Dynamic, Dynamic, _Cols, _Options>\n{\n    T *m_data;\n    Index m_rows;\n  public:\n    EIGEN_DEVICE_FUNC DenseStorage() : m_data(0), m_rows(0) {}\n    explicit DenseStorage(internal::constructor_without_unaligned_array_assert) : m_data(0), m_rows(0) {}\n    EIGEN_DEVICE_FUNC DenseStorage(Index size, Index rows, Index cols) : m_data(internal::conditional_aligned_new_auto<T,(_Options&DontAlign)==0>(size)), m_rows(rows)\n    {\n      EIGEN_INTERNAL_DENSE_STORAGE_CTOR_PLUGIN\n      eigen_internal_assert(size==rows*cols && rows>=0 && cols == _Cols);\n      EIGEN_UNUSED_VARIABLE(cols);\n    }\n    EIGEN_DEVICE_FUNC DenseStorage(const DenseStorage& other)\n      : m_data(internal::conditional_aligned_new_auto<T,(_Options&DontAlign)==0>(other.m_rows*_Cols))\n      , m_rows(other.m_rows)\n    {\n      internal::smart_copy(other.m_data, other.m_data+other.m_rows*_Cols, m_data);\n    }\n    EIGEN_DEVICE_FUNC DenseStorage& operator=(const DenseStorage& other)\n    {\n      if (this != &other)\n      {\n        DenseStorage tmp(other);\n        this->swap(tmp);\n      }\n      return *this;\n    }    \n#if EIGEN_HAS_RVALUE_REFERENCES\n    EIGEN_DEVICE_FUNC\n    DenseStorage(DenseStorage&& other) EIGEN_NOEXCEPT\n      : m_data(std::move(other.m_data))\n      , m_rows(std::move(other.m_rows))\n    {\n      other.m_data = nullptr;\n      other.m_rows = 0;\n    }\n    EIGEN_DEVICE_FUNC\n    DenseStorage& operator=(DenseStorage&& other) EIGEN_NOEXCEPT\n    {\n      using std::swap;\n      swap(m_data, other.m_data);\n      swap(m_rows, other.m_rows);\n      return *this;\n    }\n#endif\n    EIGEN_DEVICE_FUNC ~DenseStorage() { internal::conditional_aligned_delete_auto<T,(_Options&DontAlign)==0>(m_data, _Cols*m_rows); }\n    EIGEN_DEVICE_FUNC void swap(DenseStorage& other) { std::swap(m_data,other.m_data); std::swap(m_rows,other.m_rows); }\n    EIGEN_DEVICE_FUNC Index rows(void) const {return m_rows;}\n    EIGEN_DEVICE_FUNC static Index cols(void) {return _Cols;}\n    void conservativeResize(Index size, Index rows, Index)\n    {\n      m_data = internal::conditional_aligned_realloc_new_auto<T,(_Options&DontAlign)==0>(m_data, size, m_rows*_Cols);\n      m_rows = rows;\n    }\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE void resize(Index size, Index rows, Index)\n    {\n      if(size != m_rows*_Cols)\n      {\n        internal::conditional_aligned_delete_auto<T,(_Options&DontAlign)==0>(m_data, _Cols*m_rows);\n        if (size)\n          m_data = internal::conditional_aligned_new_auto<T,(_Options&DontAlign)==0>(size);\n        else\n          m_data = 0;\n        EIGEN_INTERNAL_DENSE_STORAGE_CTOR_PLUGIN\n      }\n      m_rows = rows;\n    }\n    EIGEN_DEVICE_FUNC const T *data() const { return m_data; }\n    EIGEN_DEVICE_FUNC T *data() { return m_data; }\n};\n\n} // end namespace Eigen\n\n#endif // EIGEN_MATRIX_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/Diagonal.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2007-2009 Benoit Jacob <jacob.benoit.1@gmail.com>\n// Copyright (C) 2009-2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_DIAGONAL_H\n#define EIGEN_DIAGONAL_H\n\nnamespace Eigen { \n\n/** \\class Diagonal\n  * \\ingroup Core_Module\n  *\n  * \\brief Expression of a diagonal/subdiagonal/superdiagonal in a matrix\n  *\n  * \\param MatrixType the type of the object in which we are taking a sub/main/super diagonal\n  * \\param DiagIndex the index of the sub/super diagonal. The default is 0 and it means the main diagonal.\n  *              A positive value means a superdiagonal, a negative value means a subdiagonal.\n  *              You can also use Dynamic so the index can be set at runtime.\n  *\n  * The matrix is not required to be square.\n  *\n  * This class represents an expression of the main diagonal, or any sub/super diagonal\n  * of a square matrix. It is the return type of MatrixBase::diagonal() and MatrixBase::diagonal(Index) and most of the\n  * time this is the only way it is used.\n  *\n  * \\sa MatrixBase::diagonal(), MatrixBase::diagonal(Index)\n  */\n\nnamespace internal {\ntemplate<typename MatrixType, int DiagIndex>\nstruct traits<Diagonal<MatrixType,DiagIndex> >\n : traits<MatrixType>\n{\n  typedef typename ref_selector<MatrixType>::type MatrixTypeNested;\n  typedef typename remove_reference<MatrixTypeNested>::type _MatrixTypeNested;\n  typedef typename MatrixType::StorageKind StorageKind;\n  enum {\n    RowsAtCompileTime = (int(DiagIndex) == DynamicIndex || int(MatrixType::SizeAtCompileTime) == Dynamic) ? Dynamic\n                      : (EIGEN_PLAIN_ENUM_MIN(MatrixType::RowsAtCompileTime - EIGEN_PLAIN_ENUM_MAX(-DiagIndex, 0),\n                                              MatrixType::ColsAtCompileTime - EIGEN_PLAIN_ENUM_MAX( DiagIndex, 0))),\n    ColsAtCompileTime = 1,\n    MaxRowsAtCompileTime = int(MatrixType::MaxSizeAtCompileTime) == Dynamic ? Dynamic\n                         : DiagIndex == DynamicIndex ? EIGEN_SIZE_MIN_PREFER_FIXED(MatrixType::MaxRowsAtCompileTime,\n                                                                              MatrixType::MaxColsAtCompileTime)\n                         : (EIGEN_PLAIN_ENUM_MIN(MatrixType::MaxRowsAtCompileTime - EIGEN_PLAIN_ENUM_MAX(-DiagIndex, 0),\n                                                 MatrixType::MaxColsAtCompileTime - EIGEN_PLAIN_ENUM_MAX( DiagIndex, 0))),\n    MaxColsAtCompileTime = 1,\n    MaskLvalueBit = is_lvalue<MatrixType>::value ? LvalueBit : 0,\n    Flags = (unsigned int)_MatrixTypeNested::Flags & (RowMajorBit | MaskLvalueBit | DirectAccessBit) & ~RowMajorBit, // FIXME DirectAccessBit should not be handled by expressions\n    MatrixTypeOuterStride = outer_stride_at_compile_time<MatrixType>::ret,\n    InnerStrideAtCompileTime = MatrixTypeOuterStride == Dynamic ? Dynamic : MatrixTypeOuterStride+1,\n    OuterStrideAtCompileTime = 0\n  };\n};\n}\n\ntemplate<typename MatrixType, int _DiagIndex> class Diagonal\n   : public internal::dense_xpr_base< Diagonal<MatrixType,_DiagIndex> >::type\n{\n  public:\n\n    enum { DiagIndex = _DiagIndex };\n    typedef typename internal::dense_xpr_base<Diagonal>::type Base;\n    EIGEN_DENSE_PUBLIC_INTERFACE(Diagonal)\n\n    EIGEN_DEVICE_FUNC\n    explicit inline Diagonal(MatrixType& matrix, Index a_index = DiagIndex) : m_matrix(matrix), m_index(a_index) {}\n\n    EIGEN_INHERIT_ASSIGNMENT_OPERATORS(Diagonal)\n\n    EIGEN_DEVICE_FUNC\n    inline Index rows() const\n    {\n      return m_index.value()<0 ? numext::mini<Index>(m_matrix.cols(),m_matrix.rows()+m_index.value())\n                               : numext::mini<Index>(m_matrix.rows(),m_matrix.cols()-m_index.value());\n    }\n\n    EIGEN_DEVICE_FUNC\n    inline Index cols() const { return 1; }\n\n    EIGEN_DEVICE_FUNC\n    inline Index innerStride() const\n    {\n      return m_matrix.outerStride() + 1;\n    }\n\n    EIGEN_DEVICE_FUNC\n    inline Index outerStride() const\n    {\n      return 0;\n    }\n\n    typedef typename internal::conditional<\n                       internal::is_lvalue<MatrixType>::value,\n                       Scalar,\n                       const Scalar\n                     >::type ScalarWithConstIfNotLvalue;\n\n    EIGEN_DEVICE_FUNC\n    inline ScalarWithConstIfNotLvalue* data() { return &(m_matrix.coeffRef(rowOffset(), colOffset())); }\n    EIGEN_DEVICE_FUNC\n    inline const Scalar* data() const { return &(m_matrix.coeffRef(rowOffset(), colOffset())); }\n\n    EIGEN_DEVICE_FUNC\n    inline Scalar& coeffRef(Index row, Index)\n    {\n      EIGEN_STATIC_ASSERT_LVALUE(MatrixType)\n      return m_matrix.coeffRef(row+rowOffset(), row+colOffset());\n    }\n\n    EIGEN_DEVICE_FUNC\n    inline const Scalar& coeffRef(Index row, Index) const\n    {\n      return m_matrix.coeffRef(row+rowOffset(), row+colOffset());\n    }\n\n    EIGEN_DEVICE_FUNC\n    inline CoeffReturnType coeff(Index row, Index) const\n    {\n      return m_matrix.coeff(row+rowOffset(), row+colOffset());\n    }\n\n    EIGEN_DEVICE_FUNC\n    inline Scalar& coeffRef(Index idx)\n    {\n      EIGEN_STATIC_ASSERT_LVALUE(MatrixType)\n      return m_matrix.coeffRef(idx+rowOffset(), idx+colOffset());\n    }\n\n    EIGEN_DEVICE_FUNC\n    inline const Scalar& coeffRef(Index idx) const\n    {\n      return m_matrix.coeffRef(idx+rowOffset(), idx+colOffset());\n    }\n\n    EIGEN_DEVICE_FUNC\n    inline CoeffReturnType coeff(Index idx) const\n    {\n      return m_matrix.coeff(idx+rowOffset(), idx+colOffset());\n    }\n\n    EIGEN_DEVICE_FUNC\n    inline const typename internal::remove_all<typename MatrixType::Nested>::type& \n    nestedExpression() const \n    {\n      return m_matrix;\n    }\n\n    EIGEN_DEVICE_FUNC\n    inline Index index() const\n    {\n      return m_index.value();\n    }\n\n  protected:\n    typename internal::ref_selector<MatrixType>::non_const_type m_matrix;\n    const internal::variable_if_dynamicindex<Index, DiagIndex> m_index;\n\n  private:\n    // some compilers may fail to optimize std::max etc in case of compile-time constants...\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Index absDiagIndex() const { return m_index.value()>0 ? m_index.value() : -m_index.value(); }\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Index rowOffset() const { return m_index.value()>0 ? 0 : -m_index.value(); }\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Index colOffset() const { return m_index.value()>0 ? m_index.value() : 0; }\n    // trigger a compile-time error if someone try to call packet\n    template<int LoadMode> typename MatrixType::PacketReturnType packet(Index) const;\n    template<int LoadMode> typename MatrixType::PacketReturnType packet(Index,Index) const;\n};\n\n/** \\returns an expression of the main diagonal of the matrix \\c *this\n  *\n  * \\c *this is not required to be square.\n  *\n  * Example: \\include MatrixBase_diagonal.cpp\n  * Output: \\verbinclude MatrixBase_diagonal.out\n  *\n  * \\sa class Diagonal */\ntemplate<typename Derived>\ninline typename MatrixBase<Derived>::DiagonalReturnType\nMatrixBase<Derived>::diagonal()\n{\n  return DiagonalReturnType(derived());\n}\n\n/** This is the const version of diagonal(). */\ntemplate<typename Derived>\ninline typename MatrixBase<Derived>::ConstDiagonalReturnType\nMatrixBase<Derived>::diagonal() const\n{\n  return ConstDiagonalReturnType(derived());\n}\n\n/** \\returns an expression of the \\a DiagIndex-th sub or super diagonal of the matrix \\c *this\n  *\n  * \\c *this is not required to be square.\n  *\n  * The template parameter \\a DiagIndex represent a super diagonal if \\a DiagIndex > 0\n  * and a sub diagonal otherwise. \\a DiagIndex == 0 is equivalent to the main diagonal.\n  *\n  * Example: \\include MatrixBase_diagonal_int.cpp\n  * Output: \\verbinclude MatrixBase_diagonal_int.out\n  *\n  * \\sa MatrixBase::diagonal(), class Diagonal */\ntemplate<typename Derived>\ninline typename MatrixBase<Derived>::DiagonalDynamicIndexReturnType\nMatrixBase<Derived>::diagonal(Index index)\n{\n  return DiagonalDynamicIndexReturnType(derived(), index);\n}\n\n/** This is the const version of diagonal(Index). */\ntemplate<typename Derived>\ninline typename MatrixBase<Derived>::ConstDiagonalDynamicIndexReturnType\nMatrixBase<Derived>::diagonal(Index index) const\n{\n  return ConstDiagonalDynamicIndexReturnType(derived(), index);\n}\n\n/** \\returns an expression of the \\a DiagIndex-th sub or super diagonal of the matrix \\c *this\n  *\n  * \\c *this is not required to be square.\n  *\n  * The template parameter \\a DiagIndex represent a super diagonal if \\a DiagIndex > 0\n  * and a sub diagonal otherwise. \\a DiagIndex == 0 is equivalent to the main diagonal.\n  *\n  * Example: \\include MatrixBase_diagonal_template_int.cpp\n  * Output: \\verbinclude MatrixBase_diagonal_template_int.out\n  *\n  * \\sa MatrixBase::diagonal(), class Diagonal */\ntemplate<typename Derived>\ntemplate<int Index_>\ninline typename MatrixBase<Derived>::template DiagonalIndexReturnType<Index_>::Type\nMatrixBase<Derived>::diagonal()\n{\n  return typename DiagonalIndexReturnType<Index_>::Type(derived());\n}\n\n/** This is the const version of diagonal<int>(). */\ntemplate<typename Derived>\ntemplate<int Index_>\ninline typename MatrixBase<Derived>::template ConstDiagonalIndexReturnType<Index_>::Type\nMatrixBase<Derived>::diagonal() const\n{\n  return typename ConstDiagonalIndexReturnType<Index_>::Type(derived());\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_DIAGONAL_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/DiagonalMatrix.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2007-2009 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_DIAGONALMATRIX_H\n#define EIGEN_DIAGONALMATRIX_H\n\nnamespace Eigen { \n\n#ifndef EIGEN_PARSED_BY_DOXYGEN\ntemplate<typename Derived>\nclass DiagonalBase : public EigenBase<Derived>\n{\n  public:\n    typedef typename internal::traits<Derived>::DiagonalVectorType DiagonalVectorType;\n    typedef typename DiagonalVectorType::Scalar Scalar;\n    typedef typename DiagonalVectorType::RealScalar RealScalar;\n    typedef typename internal::traits<Derived>::StorageKind StorageKind;\n    typedef typename internal::traits<Derived>::StorageIndex StorageIndex;\n\n    enum {\n      RowsAtCompileTime = DiagonalVectorType::SizeAtCompileTime,\n      ColsAtCompileTime = DiagonalVectorType::SizeAtCompileTime,\n      MaxRowsAtCompileTime = DiagonalVectorType::MaxSizeAtCompileTime,\n      MaxColsAtCompileTime = DiagonalVectorType::MaxSizeAtCompileTime,\n      IsVectorAtCompileTime = 0,\n      Flags = NoPreferredStorageOrderBit\n    };\n\n    typedef Matrix<Scalar, RowsAtCompileTime, ColsAtCompileTime, 0, MaxRowsAtCompileTime, MaxColsAtCompileTime> DenseMatrixType;\n    typedef DenseMatrixType DenseType;\n    typedef DiagonalMatrix<Scalar,DiagonalVectorType::SizeAtCompileTime,DiagonalVectorType::MaxSizeAtCompileTime> PlainObject;\n\n    EIGEN_DEVICE_FUNC\n    inline const Derived& derived() const { return *static_cast<const Derived*>(this); }\n    EIGEN_DEVICE_FUNC\n    inline Derived& derived() { return *static_cast<Derived*>(this); }\n\n    EIGEN_DEVICE_FUNC\n    DenseMatrixType toDenseMatrix() const { return derived(); }\n    \n    EIGEN_DEVICE_FUNC\n    inline const DiagonalVectorType& diagonal() const { return derived().diagonal(); }\n    EIGEN_DEVICE_FUNC\n    inline DiagonalVectorType& diagonal() { return derived().diagonal(); }\n\n    EIGEN_DEVICE_FUNC\n    inline Index rows() const { return diagonal().size(); }\n    EIGEN_DEVICE_FUNC\n    inline Index cols() const { return diagonal().size(); }\n\n    template<typename MatrixDerived>\n    EIGEN_DEVICE_FUNC\n    const Product<Derived,MatrixDerived,LazyProduct>\n    operator*(const MatrixBase<MatrixDerived> &matrix) const\n    {\n      return Product<Derived, MatrixDerived, LazyProduct>(derived(),matrix.derived());\n    }\n\n    typedef DiagonalWrapper<const CwiseUnaryOp<internal::scalar_inverse_op<Scalar>, const DiagonalVectorType> > InverseReturnType;\n    EIGEN_DEVICE_FUNC\n    inline const InverseReturnType\n    inverse() const\n    {\n      return InverseReturnType(diagonal().cwiseInverse());\n    }\n    \n    EIGEN_DEVICE_FUNC\n    inline const DiagonalWrapper<const EIGEN_EXPR_BINARYOP_SCALAR_RETURN_TYPE(DiagonalVectorType,Scalar,product) >\n    operator*(const Scalar& scalar) const\n    {\n      return DiagonalWrapper<const EIGEN_EXPR_BINARYOP_SCALAR_RETURN_TYPE(DiagonalVectorType,Scalar,product) >(diagonal() * scalar);\n    }\n    EIGEN_DEVICE_FUNC\n    friend inline const DiagonalWrapper<const EIGEN_SCALAR_BINARYOP_EXPR_RETURN_TYPE(Scalar,DiagonalVectorType,product) >\n    operator*(const Scalar& scalar, const DiagonalBase& other)\n    {\n      return DiagonalWrapper<const EIGEN_SCALAR_BINARYOP_EXPR_RETURN_TYPE(Scalar,DiagonalVectorType,product) >(scalar * other.diagonal());\n    }\n};\n\n#endif\n\n/** \\class DiagonalMatrix\n  * \\ingroup Core_Module\n  *\n  * \\brief Represents a diagonal matrix with its storage\n  *\n  * \\param _Scalar the type of coefficients\n  * \\param SizeAtCompileTime the dimension of the matrix, or Dynamic\n  * \\param MaxSizeAtCompileTime the dimension of the matrix, or Dynamic. This parameter is optional and defaults\n  *        to SizeAtCompileTime. Most of the time, you do not need to specify it.\n  *\n  * \\sa class DiagonalWrapper\n  */\n\nnamespace internal {\ntemplate<typename _Scalar, int SizeAtCompileTime, int MaxSizeAtCompileTime>\nstruct traits<DiagonalMatrix<_Scalar,SizeAtCompileTime,MaxSizeAtCompileTime> >\n : traits<Matrix<_Scalar,SizeAtCompileTime,SizeAtCompileTime,0,MaxSizeAtCompileTime,MaxSizeAtCompileTime> >\n{\n  typedef Matrix<_Scalar,SizeAtCompileTime,1,0,MaxSizeAtCompileTime,1> DiagonalVectorType;\n  typedef DiagonalShape StorageKind;\n  enum {\n    Flags = LvalueBit | NoPreferredStorageOrderBit\n  };\n};\n}\ntemplate<typename _Scalar, int SizeAtCompileTime, int MaxSizeAtCompileTime>\nclass DiagonalMatrix\n  : public DiagonalBase<DiagonalMatrix<_Scalar,SizeAtCompileTime,MaxSizeAtCompileTime> >\n{\n  public:\n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    typedef typename internal::traits<DiagonalMatrix>::DiagonalVectorType DiagonalVectorType;\n    typedef const DiagonalMatrix& Nested;\n    typedef _Scalar Scalar;\n    typedef typename internal::traits<DiagonalMatrix>::StorageKind StorageKind;\n    typedef typename internal::traits<DiagonalMatrix>::StorageIndex StorageIndex;\n    #endif\n\n  protected:\n\n    DiagonalVectorType m_diagonal;\n\n  public:\n\n    /** const version of diagonal(). */\n    EIGEN_DEVICE_FUNC\n    inline const DiagonalVectorType& diagonal() const { return m_diagonal; }\n    /** \\returns a reference to the stored vector of diagonal coefficients. */\n    EIGEN_DEVICE_FUNC\n    inline DiagonalVectorType& diagonal() { return m_diagonal; }\n\n    /** Default constructor without initialization */\n    EIGEN_DEVICE_FUNC\n    inline DiagonalMatrix() {}\n\n    /** Constructs a diagonal matrix with given dimension  */\n    EIGEN_DEVICE_FUNC\n    explicit inline DiagonalMatrix(Index dim) : m_diagonal(dim) {}\n\n    /** 2D constructor. */\n    EIGEN_DEVICE_FUNC\n    inline DiagonalMatrix(const Scalar& x, const Scalar& y) : m_diagonal(x,y) {}\n\n    /** 3D constructor. */\n    EIGEN_DEVICE_FUNC\n    inline DiagonalMatrix(const Scalar& x, const Scalar& y, const Scalar& z) : m_diagonal(x,y,z) {}\n\n    /** Copy constructor. */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    inline DiagonalMatrix(const DiagonalBase<OtherDerived>& other) : m_diagonal(other.diagonal()) {}\n\n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    /** copy constructor. prevent a default copy constructor from hiding the other templated constructor */\n    inline DiagonalMatrix(const DiagonalMatrix& other) : m_diagonal(other.diagonal()) {}\n    #endif\n\n    /** generic constructor from expression of the diagonal coefficients */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    explicit inline DiagonalMatrix(const MatrixBase<OtherDerived>& other) : m_diagonal(other)\n    {}\n\n    /** Copy operator. */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    DiagonalMatrix& operator=(const DiagonalBase<OtherDerived>& other)\n    {\n      m_diagonal = other.diagonal();\n      return *this;\n    }\n\n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    /** This is a special case of the templated operator=. Its purpose is to\n      * prevent a default operator= from hiding the templated operator=.\n      */\n    EIGEN_DEVICE_FUNC\n    DiagonalMatrix& operator=(const DiagonalMatrix& other)\n    {\n      m_diagonal = other.diagonal();\n      return *this;\n    }\n    #endif\n\n    /** Resizes to given size. */\n    EIGEN_DEVICE_FUNC\n    inline void resize(Index size) { m_diagonal.resize(size); }\n    /** Sets all coefficients to zero. */\n    EIGEN_DEVICE_FUNC\n    inline void setZero() { m_diagonal.setZero(); }\n    /** Resizes and sets all coefficients to zero. */\n    EIGEN_DEVICE_FUNC\n    inline void setZero(Index size) { m_diagonal.setZero(size); }\n    /** Sets this matrix to be the identity matrix of the current size. */\n    EIGEN_DEVICE_FUNC\n    inline void setIdentity() { m_diagonal.setOnes(); }\n    /** Sets this matrix to be the identity matrix of the given size. */\n    EIGEN_DEVICE_FUNC\n    inline void setIdentity(Index size) { m_diagonal.setOnes(size); }\n};\n\n/** \\class DiagonalWrapper\n  * \\ingroup Core_Module\n  *\n  * \\brief Expression of a diagonal matrix\n  *\n  * \\param _DiagonalVectorType the type of the vector of diagonal coefficients\n  *\n  * This class is an expression of a diagonal matrix, but not storing its own vector of diagonal coefficients,\n  * instead wrapping an existing vector expression. It is the return type of MatrixBase::asDiagonal()\n  * and most of the time this is the only way that it is used.\n  *\n  * \\sa class DiagonalMatrix, class DiagonalBase, MatrixBase::asDiagonal()\n  */\n\nnamespace internal {\ntemplate<typename _DiagonalVectorType>\nstruct traits<DiagonalWrapper<_DiagonalVectorType> >\n{\n  typedef _DiagonalVectorType DiagonalVectorType;\n  typedef typename DiagonalVectorType::Scalar Scalar;\n  typedef typename DiagonalVectorType::StorageIndex StorageIndex;\n  typedef DiagonalShape StorageKind;\n  typedef typename traits<DiagonalVectorType>::XprKind XprKind;\n  enum {\n    RowsAtCompileTime = DiagonalVectorType::SizeAtCompileTime,\n    ColsAtCompileTime = DiagonalVectorType::SizeAtCompileTime,\n    MaxRowsAtCompileTime = DiagonalVectorType::MaxSizeAtCompileTime,\n    MaxColsAtCompileTime = DiagonalVectorType::MaxSizeAtCompileTime,\n    Flags =  (traits<DiagonalVectorType>::Flags & LvalueBit) | NoPreferredStorageOrderBit\n  };\n};\n}\n\ntemplate<typename _DiagonalVectorType>\nclass DiagonalWrapper\n  : public DiagonalBase<DiagonalWrapper<_DiagonalVectorType> >, internal::no_assignment_operator\n{\n  public:\n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    typedef _DiagonalVectorType DiagonalVectorType;\n    typedef DiagonalWrapper Nested;\n    #endif\n\n    /** Constructor from expression of diagonal coefficients to wrap. */\n    EIGEN_DEVICE_FUNC\n    explicit inline DiagonalWrapper(DiagonalVectorType& a_diagonal) : m_diagonal(a_diagonal) {}\n\n    /** \\returns a const reference to the wrapped expression of diagonal coefficients. */\n    EIGEN_DEVICE_FUNC\n    const DiagonalVectorType& diagonal() const { return m_diagonal; }\n\n  protected:\n    typename DiagonalVectorType::Nested m_diagonal;\n};\n\n/** \\returns a pseudo-expression of a diagonal matrix with *this as vector of diagonal coefficients\n  *\n  * \\only_for_vectors\n  *\n  * Example: \\include MatrixBase_asDiagonal.cpp\n  * Output: \\verbinclude MatrixBase_asDiagonal.out\n  *\n  * \\sa class DiagonalWrapper, class DiagonalMatrix, diagonal(), isDiagonal()\n  **/\ntemplate<typename Derived>\ninline const DiagonalWrapper<const Derived>\nMatrixBase<Derived>::asDiagonal() const\n{\n  return DiagonalWrapper<const Derived>(derived());\n}\n\n/** \\returns true if *this is approximately equal to a diagonal matrix,\n  *          within the precision given by \\a prec.\n  *\n  * Example: \\include MatrixBase_isDiagonal.cpp\n  * Output: \\verbinclude MatrixBase_isDiagonal.out\n  *\n  * \\sa asDiagonal()\n  */\ntemplate<typename Derived>\nbool MatrixBase<Derived>::isDiagonal(const RealScalar& prec) const\n{\n  if(cols() != rows()) return false;\n  RealScalar maxAbsOnDiagonal = static_cast<RealScalar>(-1);\n  for(Index j = 0; j < cols(); ++j)\n  {\n    RealScalar absOnDiagonal = numext::abs(coeff(j,j));\n    if(absOnDiagonal > maxAbsOnDiagonal) maxAbsOnDiagonal = absOnDiagonal;\n  }\n  for(Index j = 0; j < cols(); ++j)\n    for(Index i = 0; i < j; ++i)\n    {\n      if(!internal::isMuchSmallerThan(coeff(i, j), maxAbsOnDiagonal, prec)) return false;\n      if(!internal::isMuchSmallerThan(coeff(j, i), maxAbsOnDiagonal, prec)) return false;\n    }\n  return true;\n}\n\nnamespace internal {\n\ntemplate<> struct storage_kind_to_shape<DiagonalShape> { typedef DiagonalShape Shape; };\n\nstruct Diagonal2Dense {};\n\ntemplate<> struct AssignmentKind<DenseShape,DiagonalShape> { typedef Diagonal2Dense Kind; };\n\n// Diagonal matrix to Dense assignment\ntemplate< typename DstXprType, typename SrcXprType, typename Functor>\nstruct Assignment<DstXprType, SrcXprType, Functor, Diagonal2Dense>\n{\n  static void run(DstXprType &dst, const SrcXprType &src, const internal::assign_op<typename DstXprType::Scalar,typename SrcXprType::Scalar> &/*func*/)\n  {\n    Index dstRows = src.rows();\n    Index dstCols = src.cols();\n    if((dst.rows()!=dstRows) || (dst.cols()!=dstCols))\n      dst.resize(dstRows, dstCols);\n    \n    dst.setZero();\n    dst.diagonal() = src.diagonal();\n  }\n  \n  static void run(DstXprType &dst, const SrcXprType &src, const internal::add_assign_op<typename DstXprType::Scalar,typename SrcXprType::Scalar> &/*func*/)\n  { dst.diagonal() += src.diagonal(); }\n  \n  static void run(DstXprType &dst, const SrcXprType &src, const internal::sub_assign_op<typename DstXprType::Scalar,typename SrcXprType::Scalar> &/*func*/)\n  { dst.diagonal() -= src.diagonal(); }\n};\n\n} // namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_DIAGONALMATRIX_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/DiagonalProduct.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2007-2009 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_DIAGONALPRODUCT_H\n#define EIGEN_DIAGONALPRODUCT_H\n\nnamespace Eigen { \n\n/** \\returns the diagonal matrix product of \\c *this by the diagonal matrix \\a diagonal.\n  */\ntemplate<typename Derived>\ntemplate<typename DiagonalDerived>\ninline const Product<Derived, DiagonalDerived, LazyProduct>\nMatrixBase<Derived>::operator*(const DiagonalBase<DiagonalDerived> &a_diagonal) const\n{\n  return Product<Derived, DiagonalDerived, LazyProduct>(derived(),a_diagonal.derived());\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_DIAGONALPRODUCT_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/Dot.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2006-2008, 2010 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_DOT_H\n#define EIGEN_DOT_H\n\nnamespace Eigen { \n\nnamespace internal {\n\n// helper function for dot(). The problem is that if we put that in the body of dot(), then upon calling dot\n// with mismatched types, the compiler emits errors about failing to instantiate cwiseProduct BEFORE\n// looking at the static assertions. Thus this is a trick to get better compile errors.\ntemplate<typename T, typename U,\n// the NeedToTranspose condition here is taken straight from Assign.h\n         bool NeedToTranspose = T::IsVectorAtCompileTime\n                && U::IsVectorAtCompileTime\n                && ((int(T::RowsAtCompileTime) == 1 && int(U::ColsAtCompileTime) == 1)\n                      |  // FIXME | instead of || to please GCC 4.4.0 stupid warning \"suggest parentheses around &&\".\n                         // revert to || as soon as not needed anymore.\n                    (int(T::ColsAtCompileTime) == 1 && int(U::RowsAtCompileTime) == 1))\n>\nstruct dot_nocheck\n{\n  typedef scalar_conj_product_op<typename traits<T>::Scalar,typename traits<U>::Scalar> conj_prod;\n  typedef typename conj_prod::result_type ResScalar;\n  EIGEN_DEVICE_FUNC\n  static inline ResScalar run(const MatrixBase<T>& a, const MatrixBase<U>& b)\n  {\n    return a.template binaryExpr<conj_prod>(b).sum();\n  }\n};\n\ntemplate<typename T, typename U>\nstruct dot_nocheck<T, U, true>\n{\n  typedef scalar_conj_product_op<typename traits<T>::Scalar,typename traits<U>::Scalar> conj_prod;\n  typedef typename conj_prod::result_type ResScalar;\n  EIGEN_DEVICE_FUNC\n  static inline ResScalar run(const MatrixBase<T>& a, const MatrixBase<U>& b)\n  {\n    return a.transpose().template binaryExpr<conj_prod>(b).sum();\n  }\n};\n\n} // end namespace internal\n\n/** \\returns the dot product of *this with other.\n  *\n  * \\only_for_vectors\n  *\n  * \\note If the scalar type is complex numbers, then this function returns the hermitian\n  * (sesquilinear) dot product, conjugate-linear in the first variable and linear in the\n  * second variable.\n  *\n  * \\sa squaredNorm(), norm()\n  */\ntemplate<typename Derived>\ntemplate<typename OtherDerived>\nEIGEN_DEVICE_FUNC\ntypename ScalarBinaryOpTraits<typename internal::traits<Derived>::Scalar,typename internal::traits<OtherDerived>::Scalar>::ReturnType\nMatrixBase<Derived>::dot(const MatrixBase<OtherDerived>& other) const\n{\n  EIGEN_STATIC_ASSERT_VECTOR_ONLY(Derived)\n  EIGEN_STATIC_ASSERT_VECTOR_ONLY(OtherDerived)\n  EIGEN_STATIC_ASSERT_SAME_VECTOR_SIZE(Derived,OtherDerived)\n#if !(defined(EIGEN_NO_STATIC_ASSERT) && defined(EIGEN_NO_DEBUG))\n  typedef internal::scalar_conj_product_op<Scalar,typename OtherDerived::Scalar> func;\n  EIGEN_CHECK_BINARY_COMPATIBILIY(func,Scalar,typename OtherDerived::Scalar);\n#endif\n  \n  eigen_assert(size() == other.size());\n\n  return internal::dot_nocheck<Derived,OtherDerived>::run(*this, other);\n}\n\n//---------- implementation of L2 norm and related functions ----------\n\n/** \\returns, for vectors, the squared \\em l2 norm of \\c *this, and for matrices the Frobenius norm.\n  * In both cases, it consists in the sum of the square of all the matrix entries.\n  * For vectors, this is also equals to the dot product of \\c *this with itself.\n  *\n  * \\sa dot(), norm(), lpNorm()\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE typename NumTraits<typename internal::traits<Derived>::Scalar>::Real MatrixBase<Derived>::squaredNorm() const\n{\n  return numext::real((*this).cwiseAbs2().sum());\n}\n\n/** \\returns, for vectors, the \\em l2 norm of \\c *this, and for matrices the Frobenius norm.\n  * In both cases, it consists in the square root of the sum of the square of all the matrix entries.\n  * For vectors, this is also equals to the square root of the dot product of \\c *this with itself.\n  *\n  * \\sa lpNorm(), dot(), squaredNorm()\n  */\ntemplate<typename Derived>\ninline typename NumTraits<typename internal::traits<Derived>::Scalar>::Real MatrixBase<Derived>::norm() const\n{\n  return numext::sqrt(squaredNorm());\n}\n\n/** \\returns an expression of the quotient of \\c *this by its own norm.\n  *\n  * \\warning If the input vector is too small (i.e., this->norm()==0),\n  *          then this function returns a copy of the input.\n  *\n  * \\only_for_vectors\n  *\n  * \\sa norm(), normalize()\n  */\ntemplate<typename Derived>\ninline const typename MatrixBase<Derived>::PlainObject\nMatrixBase<Derived>::normalized() const\n{\n  typedef typename internal::nested_eval<Derived,2>::type _Nested;\n  _Nested n(derived());\n  RealScalar z = n.squaredNorm();\n  // NOTE: after extensive benchmarking, this conditional does not impact performance, at least on recent x86 CPU\n  if(z>RealScalar(0))\n    return n / numext::sqrt(z);\n  else\n    return n;\n}\n\n/** Normalizes the vector, i.e. divides it by its own norm.\n  *\n  * \\only_for_vectors\n  *\n  * \\warning If the input vector is too small (i.e., this->norm()==0), then \\c *this is left unchanged.\n  *\n  * \\sa norm(), normalized()\n  */\ntemplate<typename Derived>\ninline void MatrixBase<Derived>::normalize()\n{\n  RealScalar z = squaredNorm();\n  // NOTE: after extensive benchmarking, this conditional does not impact performance, at least on recent x86 CPU\n  if(z>RealScalar(0))\n    derived() /= numext::sqrt(z);\n}\n\n/** \\returns an expression of the quotient of \\c *this by its own norm while avoiding underflow and overflow.\n  *\n  * \\only_for_vectors\n  *\n  * This method is analogue to the normalized() method, but it reduces the risk of\n  * underflow and overflow when computing the norm.\n  *\n  * \\warning If the input vector is too small (i.e., this->norm()==0),\n  *          then this function returns a copy of the input.\n  *\n  * \\sa stableNorm(), stableNormalize(), normalized()\n  */\ntemplate<typename Derived>\ninline const typename MatrixBase<Derived>::PlainObject\nMatrixBase<Derived>::stableNormalized() const\n{\n  typedef typename internal::nested_eval<Derived,3>::type _Nested;\n  _Nested n(derived());\n  RealScalar w = n.cwiseAbs().maxCoeff();\n  RealScalar z = (n/w).squaredNorm();\n  if(z>RealScalar(0))\n    return n / (numext::sqrt(z)*w);\n  else\n    return n;\n}\n\n/** Normalizes the vector while avoid underflow and overflow\n  *\n  * \\only_for_vectors\n  *\n  * This method is analogue to the normalize() method, but it reduces the risk of\n  * underflow and overflow when computing the norm.\n  *\n  * \\warning If the input vector is too small (i.e., this->norm()==0), then \\c *this is left unchanged.\n  *\n  * \\sa stableNorm(), stableNormalized(), normalize()\n  */\ntemplate<typename Derived>\ninline void MatrixBase<Derived>::stableNormalize()\n{\n  RealScalar w = cwiseAbs().maxCoeff();\n  RealScalar z = (derived()/w).squaredNorm();\n  if(z>RealScalar(0))\n    derived() /= numext::sqrt(z)*w;\n}\n\n//---------- implementation of other norms ----------\n\nnamespace internal {\n\ntemplate<typename Derived, int p>\nstruct lpNorm_selector\n{\n  typedef typename NumTraits<typename traits<Derived>::Scalar>::Real RealScalar;\n  EIGEN_DEVICE_FUNC\n  static inline RealScalar run(const MatrixBase<Derived>& m)\n  {\n    EIGEN_USING_STD_MATH(pow)\n    return pow(m.cwiseAbs().array().pow(p).sum(), RealScalar(1)/p);\n  }\n};\n\ntemplate<typename Derived>\nstruct lpNorm_selector<Derived, 1>\n{\n  EIGEN_DEVICE_FUNC\n  static inline typename NumTraits<typename traits<Derived>::Scalar>::Real run(const MatrixBase<Derived>& m)\n  {\n    return m.cwiseAbs().sum();\n  }\n};\n\ntemplate<typename Derived>\nstruct lpNorm_selector<Derived, 2>\n{\n  EIGEN_DEVICE_FUNC\n  static inline typename NumTraits<typename traits<Derived>::Scalar>::Real run(const MatrixBase<Derived>& m)\n  {\n    return m.norm();\n  }\n};\n\ntemplate<typename Derived>\nstruct lpNorm_selector<Derived, Infinity>\n{\n  typedef typename NumTraits<typename traits<Derived>::Scalar>::Real RealScalar;\n  EIGEN_DEVICE_FUNC\n  static inline RealScalar run(const MatrixBase<Derived>& m)\n  {\n    if(Derived::SizeAtCompileTime==0 || (Derived::SizeAtCompileTime==Dynamic && m.size()==0))\n      return RealScalar(0);\n    return m.cwiseAbs().maxCoeff();\n  }\n};\n\n} // end namespace internal\n\n/** \\returns the \\b coefficient-wise \\f$ \\ell^p \\f$ norm of \\c *this, that is, returns the p-th root of the sum of the p-th powers of the absolute values\n  *          of the coefficients of \\c *this. If \\a p is the special value \\a Eigen::Infinity, this function returns the \\f$ \\ell^\\infty \\f$\n  *          norm, that is the maximum of the absolute values of the coefficients of \\c *this.\n  *\n  * In all cases, if \\c *this is empty, then the value 0 is returned.\n  *\n  * \\note For matrices, this function does not compute the <a href=\"https://en.wikipedia.org/wiki/Operator_norm\">operator-norm</a>. That is, if \\c *this is a matrix, then its coefficients are interpreted as a 1D vector. Nonetheless, you can easily compute the 1-norm and \\f$\\infty\\f$-norm matrix operator norms using \\link TutorialReductionsVisitorsBroadcastingReductionsNorm partial reductions \\endlink.\n  *\n  * \\sa norm()\n  */\ntemplate<typename Derived>\ntemplate<int p>\n#ifndef EIGEN_PARSED_BY_DOXYGEN\ninline typename NumTraits<typename internal::traits<Derived>::Scalar>::Real\n#else\nMatrixBase<Derived>::RealScalar\n#endif\nMatrixBase<Derived>::lpNorm() const\n{\n  return internal::lpNorm_selector<Derived, p>::run(*this);\n}\n\n//---------- implementation of isOrthogonal / isUnitary ----------\n\n/** \\returns true if *this is approximately orthogonal to \\a other,\n  *          within the precision given by \\a prec.\n  *\n  * Example: \\include MatrixBase_isOrthogonal.cpp\n  * Output: \\verbinclude MatrixBase_isOrthogonal.out\n  */\ntemplate<typename Derived>\ntemplate<typename OtherDerived>\nbool MatrixBase<Derived>::isOrthogonal\n(const MatrixBase<OtherDerived>& other, const RealScalar& prec) const\n{\n  typename internal::nested_eval<Derived,2>::type nested(derived());\n  typename internal::nested_eval<OtherDerived,2>::type otherNested(other.derived());\n  return numext::abs2(nested.dot(otherNested)) <= prec * prec * nested.squaredNorm() * otherNested.squaredNorm();\n}\n\n/** \\returns true if *this is approximately an unitary matrix,\n  *          within the precision given by \\a prec. In the case where the \\a Scalar\n  *          type is real numbers, a unitary matrix is an orthogonal matrix, whence the name.\n  *\n  * \\note This can be used to check whether a family of vectors forms an orthonormal basis.\n  *       Indeed, \\c m.isUnitary() returns true if and only if the columns (equivalently, the rows) of m form an\n  *       orthonormal basis.\n  *\n  * Example: \\include MatrixBase_isUnitary.cpp\n  * Output: \\verbinclude MatrixBase_isUnitary.out\n  */\ntemplate<typename Derived>\nbool MatrixBase<Derived>::isUnitary(const RealScalar& prec) const\n{\n  typename internal::nested_eval<Derived,1>::type self(derived());\n  for(Index i = 0; i < cols(); ++i)\n  {\n    if(!internal::isApprox(self.col(i).squaredNorm(), static_cast<RealScalar>(1), prec))\n      return false;\n    for(Index j = 0; j < i; ++j)\n      if(!internal::isMuchSmallerThan(self.col(i).dot(self.col(j)), static_cast<Scalar>(1), prec))\n        return false;\n  }\n  return true;\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_DOT_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/EigenBase.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009 Benoit Jacob <jacob.benoit.1@gmail.com>\n// Copyright (C) 2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_EIGENBASE_H\n#define EIGEN_EIGENBASE_H\n\nnamespace Eigen {\n\n/** \\class EigenBase\n  * \n  * Common base class for all classes T such that MatrixBase has an operator=(T) and a constructor MatrixBase(T).\n  *\n  * In other words, an EigenBase object is an object that can be copied into a MatrixBase.\n  *\n  * Besides MatrixBase-derived classes, this also includes special matrix classes such as diagonal matrices, etc.\n  *\n  * Notice that this class is trivial, it is only used to disambiguate overloaded functions.\n  *\n  * \\sa \\blank \\ref TopicClassHierarchy\n  */\ntemplate<typename Derived> struct EigenBase\n{\n//   typedef typename internal::plain_matrix_type<Derived>::type PlainObject;\n  \n  /** \\brief The interface type of indices\n    * \\details To change this, \\c \\#define the preprocessor symbol \\c EIGEN_DEFAULT_DENSE_INDEX_TYPE.\n    * \\deprecated Since Eigen 3.3, its usage is deprecated. Use Eigen::Index instead.\n    * \\sa StorageIndex, \\ref TopicPreprocessorDirectives.\n    */\n  typedef Eigen::Index Index;\n\n  // FIXME is it needed?\n  typedef typename internal::traits<Derived>::StorageKind StorageKind;\n\n  /** \\returns a reference to the derived object */\n  EIGEN_DEVICE_FUNC\n  Derived& derived() { return *static_cast<Derived*>(this); }\n  /** \\returns a const reference to the derived object */\n  EIGEN_DEVICE_FUNC\n  const Derived& derived() const { return *static_cast<const Derived*>(this); }\n\n  EIGEN_DEVICE_FUNC\n  inline Derived& const_cast_derived() const\n  { return *static_cast<Derived*>(const_cast<EigenBase*>(this)); }\n  EIGEN_DEVICE_FUNC\n  inline const Derived& const_derived() const\n  { return *static_cast<const Derived*>(this); }\n\n  /** \\returns the number of rows. \\sa cols(), RowsAtCompileTime */\n  EIGEN_DEVICE_FUNC\n  inline Index rows() const { return derived().rows(); }\n  /** \\returns the number of columns. \\sa rows(), ColsAtCompileTime*/\n  EIGEN_DEVICE_FUNC\n  inline Index cols() const { return derived().cols(); }\n  /** \\returns the number of coefficients, which is rows()*cols().\n    * \\sa rows(), cols(), SizeAtCompileTime. */\n  EIGEN_DEVICE_FUNC\n  inline Index size() const { return rows() * cols(); }\n\n  /** \\internal Don't use it, but do the equivalent: \\code dst = *this; \\endcode */\n  template<typename Dest>\n  EIGEN_DEVICE_FUNC\n  inline void evalTo(Dest& dst) const\n  { derived().evalTo(dst); }\n\n  /** \\internal Don't use it, but do the equivalent: \\code dst += *this; \\endcode */\n  template<typename Dest>\n  EIGEN_DEVICE_FUNC\n  inline void addTo(Dest& dst) const\n  {\n    // This is the default implementation,\n    // derived class can reimplement it in a more optimized way.\n    typename Dest::PlainObject res(rows(),cols());\n    evalTo(res);\n    dst += res;\n  }\n\n  /** \\internal Don't use it, but do the equivalent: \\code dst -= *this; \\endcode */\n  template<typename Dest>\n  EIGEN_DEVICE_FUNC\n  inline void subTo(Dest& dst) const\n  {\n    // This is the default implementation,\n    // derived class can reimplement it in a more optimized way.\n    typename Dest::PlainObject res(rows(),cols());\n    evalTo(res);\n    dst -= res;\n  }\n\n  /** \\internal Don't use it, but do the equivalent: \\code dst.applyOnTheRight(*this); \\endcode */\n  template<typename Dest>\n  EIGEN_DEVICE_FUNC inline void applyThisOnTheRight(Dest& dst) const\n  {\n    // This is the default implementation,\n    // derived class can reimplement it in a more optimized way.\n    dst = dst * this->derived();\n  }\n\n  /** \\internal Don't use it, but do the equivalent: \\code dst.applyOnTheLeft(*this); \\endcode */\n  template<typename Dest>\n  EIGEN_DEVICE_FUNC inline void applyThisOnTheLeft(Dest& dst) const\n  {\n    // This is the default implementation,\n    // derived class can reimplement it in a more optimized way.\n    dst = this->derived() * dst;\n  }\n\n};\n\n/***************************************************************************\n* Implementation of matrix base methods\n***************************************************************************/\n\n/** \\brief Copies the generic expression \\a other into *this.\n  *\n  * \\details The expression must provide a (templated) evalTo(Derived& dst) const\n  * function which does the actual job. In practice, this allows any user to write\n  * its own special matrix without having to modify MatrixBase\n  *\n  * \\returns a reference to *this.\n  */\ntemplate<typename Derived>\ntemplate<typename OtherDerived>\nDerived& DenseBase<Derived>::operator=(const EigenBase<OtherDerived> &other)\n{\n  call_assignment(derived(), other.derived());\n  return derived();\n}\n\ntemplate<typename Derived>\ntemplate<typename OtherDerived>\nDerived& DenseBase<Derived>::operator+=(const EigenBase<OtherDerived> &other)\n{\n  call_assignment(derived(), other.derived(), internal::add_assign_op<Scalar,typename OtherDerived::Scalar>());\n  return derived();\n}\n\ntemplate<typename Derived>\ntemplate<typename OtherDerived>\nDerived& DenseBase<Derived>::operator-=(const EigenBase<OtherDerived> &other)\n{\n  call_assignment(derived(), other.derived(), internal::sub_assign_op<Scalar,typename OtherDerived::Scalar>());\n  return derived();\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_EIGENBASE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/ForceAlignedAccess.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009-2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_FORCEALIGNEDACCESS_H\n#define EIGEN_FORCEALIGNEDACCESS_H\n\nnamespace Eigen {\n\n/** \\class ForceAlignedAccess\n  * \\ingroup Core_Module\n  *\n  * \\brief Enforce aligned packet loads and stores regardless of what is requested\n  *\n  * \\param ExpressionType the type of the object of which we are forcing aligned packet access\n  *\n  * This class is the return type of MatrixBase::forceAlignedAccess()\n  * and most of the time this is the only way it is used.\n  *\n  * \\sa MatrixBase::forceAlignedAccess()\n  */\n\nnamespace internal {\ntemplate<typename ExpressionType>\nstruct traits<ForceAlignedAccess<ExpressionType> > : public traits<ExpressionType>\n{};\n}\n\ntemplate<typename ExpressionType> class ForceAlignedAccess\n  : public internal::dense_xpr_base< ForceAlignedAccess<ExpressionType> >::type\n{\n  public:\n\n    typedef typename internal::dense_xpr_base<ForceAlignedAccess>::type Base;\n    EIGEN_DENSE_PUBLIC_INTERFACE(ForceAlignedAccess)\n\n    EIGEN_DEVICE_FUNC explicit inline ForceAlignedAccess(const ExpressionType& matrix) : m_expression(matrix) {}\n\n    EIGEN_DEVICE_FUNC inline Index rows() const { return m_expression.rows(); }\n    EIGEN_DEVICE_FUNC inline Index cols() const { return m_expression.cols(); }\n    EIGEN_DEVICE_FUNC inline Index outerStride() const { return m_expression.outerStride(); }\n    EIGEN_DEVICE_FUNC inline Index innerStride() const { return m_expression.innerStride(); }\n\n    EIGEN_DEVICE_FUNC inline const CoeffReturnType coeff(Index row, Index col) const\n    {\n      return m_expression.coeff(row, col);\n    }\n\n    EIGEN_DEVICE_FUNC inline Scalar& coeffRef(Index row, Index col)\n    {\n      return m_expression.const_cast_derived().coeffRef(row, col);\n    }\n\n    EIGEN_DEVICE_FUNC inline const CoeffReturnType coeff(Index index) const\n    {\n      return m_expression.coeff(index);\n    }\n\n    EIGEN_DEVICE_FUNC inline Scalar& coeffRef(Index index)\n    {\n      return m_expression.const_cast_derived().coeffRef(index);\n    }\n\n    template<int LoadMode>\n    inline const PacketScalar packet(Index row, Index col) const\n    {\n      return m_expression.template packet<Aligned>(row, col);\n    }\n\n    template<int LoadMode>\n    inline void writePacket(Index row, Index col, const PacketScalar& x)\n    {\n      m_expression.const_cast_derived().template writePacket<Aligned>(row, col, x);\n    }\n\n    template<int LoadMode>\n    inline const PacketScalar packet(Index index) const\n    {\n      return m_expression.template packet<Aligned>(index);\n    }\n\n    template<int LoadMode>\n    inline void writePacket(Index index, const PacketScalar& x)\n    {\n      m_expression.const_cast_derived().template writePacket<Aligned>(index, x);\n    }\n\n    EIGEN_DEVICE_FUNC operator const ExpressionType&() const { return m_expression; }\n\n  protected:\n    const ExpressionType& m_expression;\n\n  private:\n    ForceAlignedAccess& operator=(const ForceAlignedAccess&);\n};\n\n/** \\returns an expression of *this with forced aligned access\n  * \\sa forceAlignedAccessIf(),class ForceAlignedAccess\n  */\ntemplate<typename Derived>\ninline const ForceAlignedAccess<Derived>\nMatrixBase<Derived>::forceAlignedAccess() const\n{\n  return ForceAlignedAccess<Derived>(derived());\n}\n\n/** \\returns an expression of *this with forced aligned access\n  * \\sa forceAlignedAccessIf(), class ForceAlignedAccess\n  */\ntemplate<typename Derived>\ninline ForceAlignedAccess<Derived>\nMatrixBase<Derived>::forceAlignedAccess()\n{\n  return ForceAlignedAccess<Derived>(derived());\n}\n\n/** \\returns an expression of *this with forced aligned access if \\a Enable is true.\n  * \\sa forceAlignedAccess(), class ForceAlignedAccess\n  */\ntemplate<typename Derived>\ntemplate<bool Enable>\ninline typename internal::add_const_on_value_type<typename internal::conditional<Enable,ForceAlignedAccess<Derived>,Derived&>::type>::type\nMatrixBase<Derived>::forceAlignedAccessIf() const\n{\n  return derived();  // FIXME This should not work but apparently is never used\n}\n\n/** \\returns an expression of *this with forced aligned access if \\a Enable is true.\n  * \\sa forceAlignedAccess(), class ForceAlignedAccess\n  */\ntemplate<typename Derived>\ntemplate<bool Enable>\ninline typename internal::conditional<Enable,ForceAlignedAccess<Derived>,Derived&>::type\nMatrixBase<Derived>::forceAlignedAccessIf()\n{\n  return derived();  // FIXME This should not work but apparently is never used\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_FORCEALIGNEDACCESS_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/Fuzzy.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2006-2008 Benoit Jacob <jacob.benoit.1@gmail.com>\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_FUZZY_H\n#define EIGEN_FUZZY_H\n\nnamespace Eigen { \n\nnamespace internal\n{\n\ntemplate<typename Derived, typename OtherDerived, bool is_integer = NumTraits<typename Derived::Scalar>::IsInteger>\nstruct isApprox_selector\n{\n  EIGEN_DEVICE_FUNC\n  static bool run(const Derived& x, const OtherDerived& y, const typename Derived::RealScalar& prec)\n  {\n    typename internal::nested_eval<Derived,2>::type nested(x);\n    typename internal::nested_eval<OtherDerived,2>::type otherNested(y);\n    return (nested - otherNested).cwiseAbs2().sum() <= prec * prec * numext::mini(nested.cwiseAbs2().sum(), otherNested.cwiseAbs2().sum());\n  }\n};\n\ntemplate<typename Derived, typename OtherDerived>\nstruct isApprox_selector<Derived, OtherDerived, true>\n{\n  EIGEN_DEVICE_FUNC\n  static bool run(const Derived& x, const OtherDerived& y, const typename Derived::RealScalar&)\n  {\n    return x.matrix() == y.matrix();\n  }\n};\n\ntemplate<typename Derived, typename OtherDerived, bool is_integer = NumTraits<typename Derived::Scalar>::IsInteger>\nstruct isMuchSmallerThan_object_selector\n{\n  EIGEN_DEVICE_FUNC\n  static bool run(const Derived& x, const OtherDerived& y, const typename Derived::RealScalar& prec)\n  {\n    return x.cwiseAbs2().sum() <= numext::abs2(prec) * y.cwiseAbs2().sum();\n  }\n};\n\ntemplate<typename Derived, typename OtherDerived>\nstruct isMuchSmallerThan_object_selector<Derived, OtherDerived, true>\n{\n  EIGEN_DEVICE_FUNC\n  static bool run(const Derived& x, const OtherDerived&, const typename Derived::RealScalar&)\n  {\n    return x.matrix() == Derived::Zero(x.rows(), x.cols()).matrix();\n  }\n};\n\ntemplate<typename Derived, bool is_integer = NumTraits<typename Derived::Scalar>::IsInteger>\nstruct isMuchSmallerThan_scalar_selector\n{\n  EIGEN_DEVICE_FUNC\n  static bool run(const Derived& x, const typename Derived::RealScalar& y, const typename Derived::RealScalar& prec)\n  {\n    return x.cwiseAbs2().sum() <= numext::abs2(prec * y);\n  }\n};\n\ntemplate<typename Derived>\nstruct isMuchSmallerThan_scalar_selector<Derived, true>\n{\n  EIGEN_DEVICE_FUNC\n  static bool run(const Derived& x, const typename Derived::RealScalar&, const typename Derived::RealScalar&)\n  {\n    return x.matrix() == Derived::Zero(x.rows(), x.cols()).matrix();\n  }\n};\n\n} // end namespace internal\n\n\n/** \\returns \\c true if \\c *this is approximately equal to \\a other, within the precision\n  * determined by \\a prec.\n  *\n  * \\note The fuzzy compares are done multiplicatively. Two vectors \\f$ v \\f$ and \\f$ w \\f$\n  * are considered to be approximately equal within precision \\f$ p \\f$ if\n  * \\f[ \\Vert v - w \\Vert \\leqslant p\\,\\min(\\Vert v\\Vert, \\Vert w\\Vert). \\f]\n  * For matrices, the comparison is done using the Hilbert-Schmidt norm (aka Frobenius norm\n  * L2 norm).\n  *\n  * \\note Because of the multiplicativeness of this comparison, one can't use this function\n  * to check whether \\c *this is approximately equal to the zero matrix or vector.\n  * Indeed, \\c isApprox(zero) returns false unless \\c *this itself is exactly the zero matrix\n  * or vector. If you want to test whether \\c *this is zero, use internal::isMuchSmallerThan(const\n  * RealScalar&, RealScalar) instead.\n  *\n  * \\sa internal::isMuchSmallerThan(const RealScalar&, RealScalar) const\n  */\ntemplate<typename Derived>\ntemplate<typename OtherDerived>\nbool DenseBase<Derived>::isApprox(\n  const DenseBase<OtherDerived>& other,\n  const RealScalar& prec\n) const\n{\n  return internal::isApprox_selector<Derived, OtherDerived>::run(derived(), other.derived(), prec);\n}\n\n/** \\returns \\c true if the norm of \\c *this is much smaller than \\a other,\n  * within the precision determined by \\a prec.\n  *\n  * \\note The fuzzy compares are done multiplicatively. A vector \\f$ v \\f$ is\n  * considered to be much smaller than \\f$ x \\f$ within precision \\f$ p \\f$ if\n  * \\f[ \\Vert v \\Vert \\leqslant p\\,\\vert x\\vert. \\f]\n  *\n  * For matrices, the comparison is done using the Hilbert-Schmidt norm. For this reason,\n  * the value of the reference scalar \\a other should come from the Hilbert-Schmidt norm\n  * of a reference matrix of same dimensions.\n  *\n  * \\sa isApprox(), isMuchSmallerThan(const DenseBase<OtherDerived>&, RealScalar) const\n  */\ntemplate<typename Derived>\nbool DenseBase<Derived>::isMuchSmallerThan(\n  const typename NumTraits<Scalar>::Real& other,\n  const RealScalar& prec\n) const\n{\n  return internal::isMuchSmallerThan_scalar_selector<Derived>::run(derived(), other, prec);\n}\n\n/** \\returns \\c true if the norm of \\c *this is much smaller than the norm of \\a other,\n  * within the precision determined by \\a prec.\n  *\n  * \\note The fuzzy compares are done multiplicatively. A vector \\f$ v \\f$ is\n  * considered to be much smaller than a vector \\f$ w \\f$ within precision \\f$ p \\f$ if\n  * \\f[ \\Vert v \\Vert \\leqslant p\\,\\Vert w\\Vert. \\f]\n  * For matrices, the comparison is done using the Hilbert-Schmidt norm.\n  *\n  * \\sa isApprox(), isMuchSmallerThan(const RealScalar&, RealScalar) const\n  */\ntemplate<typename Derived>\ntemplate<typename OtherDerived>\nbool DenseBase<Derived>::isMuchSmallerThan(\n  const DenseBase<OtherDerived>& other,\n  const RealScalar& prec\n) const\n{\n  return internal::isMuchSmallerThan_object_selector<Derived, OtherDerived>::run(derived(), other.derived(), prec);\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_FUZZY_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/GeneralProduct.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2006-2008 Benoit Jacob <jacob.benoit.1@gmail.com>\n// Copyright (C) 2008-2011 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_GENERAL_PRODUCT_H\n#define EIGEN_GENERAL_PRODUCT_H\n\nnamespace Eigen {\n\nenum {\n  Large = 2,\n  Small = 3\n};\n\nnamespace internal {\n\ntemplate<int Rows, int Cols, int Depth> struct product_type_selector;\n\ntemplate<int Size, int MaxSize> struct product_size_category\n{\n  enum { is_large = MaxSize == Dynamic ||\n                    Size >= EIGEN_CACHEFRIENDLY_PRODUCT_THRESHOLD ||\n                    (Size==Dynamic && MaxSize>=EIGEN_CACHEFRIENDLY_PRODUCT_THRESHOLD),\n         value = is_large  ? Large\n               : Size == 1 ? 1\n                           : Small\n  };\n};\n\ntemplate<typename Lhs, typename Rhs> struct product_type\n{\n  typedef typename remove_all<Lhs>::type _Lhs;\n  typedef typename remove_all<Rhs>::type _Rhs;\n  enum {\n    MaxRows = traits<_Lhs>::MaxRowsAtCompileTime,\n    Rows    = traits<_Lhs>::RowsAtCompileTime,\n    MaxCols = traits<_Rhs>::MaxColsAtCompileTime,\n    Cols    = traits<_Rhs>::ColsAtCompileTime,\n    MaxDepth = EIGEN_SIZE_MIN_PREFER_FIXED(traits<_Lhs>::MaxColsAtCompileTime,\n                                           traits<_Rhs>::MaxRowsAtCompileTime),\n    Depth = EIGEN_SIZE_MIN_PREFER_FIXED(traits<_Lhs>::ColsAtCompileTime,\n                                        traits<_Rhs>::RowsAtCompileTime)\n  };\n\n  // the splitting into different lines of code here, introducing the _select enums and the typedef below,\n  // is to work around an internal compiler error with gcc 4.1 and 4.2.\nprivate:\n  enum {\n    rows_select = product_size_category<Rows,MaxRows>::value,\n    cols_select = product_size_category<Cols,MaxCols>::value,\n    depth_select = product_size_category<Depth,MaxDepth>::value\n  };\n  typedef product_type_selector<rows_select, cols_select, depth_select> selector;\n\npublic:\n  enum {\n    value = selector::ret,\n    ret = selector::ret\n  };\n#ifdef EIGEN_DEBUG_PRODUCT\n  static void debug()\n  {\n      EIGEN_DEBUG_VAR(Rows);\n      EIGEN_DEBUG_VAR(Cols);\n      EIGEN_DEBUG_VAR(Depth);\n      EIGEN_DEBUG_VAR(rows_select);\n      EIGEN_DEBUG_VAR(cols_select);\n      EIGEN_DEBUG_VAR(depth_select);\n      EIGEN_DEBUG_VAR(value);\n  }\n#endif\n};\n\n/* The following allows to select the kind of product at compile time\n * based on the three dimensions of the product.\n * This is a compile time mapping from {1,Small,Large}^3 -> {product types} */\n// FIXME I'm not sure the current mapping is the ideal one.\ntemplate<int M, int N>  struct product_type_selector<M,N,1>              { enum { ret = OuterProduct }; };\ntemplate<int M>         struct product_type_selector<M, 1, 1>            { enum { ret = LazyCoeffBasedProductMode }; };\ntemplate<int N>         struct product_type_selector<1, N, 1>            { enum { ret = LazyCoeffBasedProductMode }; };\ntemplate<int Depth>     struct product_type_selector<1,    1,    Depth>  { enum { ret = InnerProduct }; };\ntemplate<>              struct product_type_selector<1,    1,    1>      { enum { ret = InnerProduct }; };\ntemplate<>              struct product_type_selector<Small,1,    Small>  { enum { ret = CoeffBasedProductMode }; };\ntemplate<>              struct product_type_selector<1,    Small,Small>  { enum { ret = CoeffBasedProductMode }; };\ntemplate<>              struct product_type_selector<Small,Small,Small>  { enum { ret = CoeffBasedProductMode }; };\ntemplate<>              struct product_type_selector<Small, Small, 1>    { enum { ret = LazyCoeffBasedProductMode }; };\ntemplate<>              struct product_type_selector<Small, Large, 1>    { enum { ret = LazyCoeffBasedProductMode }; };\ntemplate<>              struct product_type_selector<Large, Small, 1>    { enum { ret = LazyCoeffBasedProductMode }; };\ntemplate<>              struct product_type_selector<1,    Large,Small>  { enum { ret = CoeffBasedProductMode }; };\ntemplate<>              struct product_type_selector<1,    Large,Large>  { enum { ret = GemvProduct }; };\ntemplate<>              struct product_type_selector<1,    Small,Large>  { enum { ret = CoeffBasedProductMode }; };\ntemplate<>              struct product_type_selector<Large,1,    Small>  { enum { ret = CoeffBasedProductMode }; };\ntemplate<>              struct product_type_selector<Large,1,    Large>  { enum { ret = GemvProduct }; };\ntemplate<>              struct product_type_selector<Small,1,    Large>  { enum { ret = CoeffBasedProductMode }; };\ntemplate<>              struct product_type_selector<Small,Small,Large>  { enum { ret = GemmProduct }; };\ntemplate<>              struct product_type_selector<Large,Small,Large>  { enum { ret = GemmProduct }; };\ntemplate<>              struct product_type_selector<Small,Large,Large>  { enum { ret = GemmProduct }; };\ntemplate<>              struct product_type_selector<Large,Large,Large>  { enum { ret = GemmProduct }; };\ntemplate<>              struct product_type_selector<Large,Small,Small>  { enum { ret = CoeffBasedProductMode }; };\ntemplate<>              struct product_type_selector<Small,Large,Small>  { enum { ret = CoeffBasedProductMode }; };\ntemplate<>              struct product_type_selector<Large,Large,Small>  { enum { ret = GemmProduct }; };\n\n} // end namespace internal\n\n/***********************************************************************\n*  Implementation of Inner Vector Vector Product\n***********************************************************************/\n\n// FIXME : maybe the \"inner product\" could return a Scalar\n// instead of a 1x1 matrix ??\n// Pro: more natural for the user\n// Cons: this could be a problem if in a meta unrolled algorithm a matrix-matrix\n// product ends up to a row-vector times col-vector product... To tackle this use\n// case, we could have a specialization for Block<MatrixType,1,1> with: operator=(Scalar x);\n\n/***********************************************************************\n*  Implementation of Outer Vector Vector Product\n***********************************************************************/\n\n/***********************************************************************\n*  Implementation of General Matrix Vector Product\n***********************************************************************/\n\n/*  According to the shape/flags of the matrix we have to distinghish 3 different cases:\n *   1 - the matrix is col-major, BLAS compatible and M is large => call fast BLAS-like colmajor routine\n *   2 - the matrix is row-major, BLAS compatible and N is large => call fast BLAS-like rowmajor routine\n *   3 - all other cases are handled using a simple loop along the outer-storage direction.\n *  Therefore we need a lower level meta selector.\n *  Furthermore, if the matrix is the rhs, then the product has to be transposed.\n */\nnamespace internal {\n\ntemplate<int Side, int StorageOrder, bool BlasCompatible>\nstruct gemv_dense_selector;\n\n} // end namespace internal\n\nnamespace internal {\n\ntemplate<typename Scalar,int Size,int MaxSize,bool Cond> struct gemv_static_vector_if;\n\ntemplate<typename Scalar,int Size,int MaxSize>\nstruct gemv_static_vector_if<Scalar,Size,MaxSize,false>\n{\n  EIGEN_STRONG_INLINE  Scalar* data() { eigen_internal_assert(false && \"should never be called\"); return 0; }\n};\n\ntemplate<typename Scalar,int Size>\nstruct gemv_static_vector_if<Scalar,Size,Dynamic,true>\n{\n  EIGEN_STRONG_INLINE Scalar* data() { return 0; }\n};\n\ntemplate<typename Scalar,int Size,int MaxSize>\nstruct gemv_static_vector_if<Scalar,Size,MaxSize,true>\n{\n  enum {\n    ForceAlignment  = internal::packet_traits<Scalar>::Vectorizable,\n    PacketSize      = internal::packet_traits<Scalar>::size\n  };\n  #if EIGEN_MAX_STATIC_ALIGN_BYTES!=0\n  internal::plain_array<Scalar,EIGEN_SIZE_MIN_PREFER_FIXED(Size,MaxSize),0,EIGEN_PLAIN_ENUM_MIN(AlignedMax,PacketSize)> m_data;\n  EIGEN_STRONG_INLINE Scalar* data() { return m_data.array; }\n  #else\n  // Some architectures cannot align on the stack,\n  // => let's manually enforce alignment by allocating more data and return the address of the first aligned element.\n  internal::plain_array<Scalar,EIGEN_SIZE_MIN_PREFER_FIXED(Size,MaxSize)+(ForceAlignment?EIGEN_MAX_ALIGN_BYTES:0),0> m_data;\n  EIGEN_STRONG_INLINE Scalar* data() {\n    return ForceAlignment\n            ? reinterpret_cast<Scalar*>((internal::UIntPtr(m_data.array) & ~(std::size_t(EIGEN_MAX_ALIGN_BYTES-1))) + EIGEN_MAX_ALIGN_BYTES)\n            : m_data.array;\n  }\n  #endif\n};\n\n// The vector is on the left => transposition\ntemplate<int StorageOrder, bool BlasCompatible>\nstruct gemv_dense_selector<OnTheLeft,StorageOrder,BlasCompatible>\n{\n  template<typename Lhs, typename Rhs, typename Dest>\n  static void run(const Lhs &lhs, const Rhs &rhs, Dest& dest, const typename Dest::Scalar& alpha)\n  {\n    Transpose<Dest> destT(dest);\n    enum { OtherStorageOrder = StorageOrder == RowMajor ? ColMajor : RowMajor };\n    gemv_dense_selector<OnTheRight,OtherStorageOrder,BlasCompatible>\n      ::run(rhs.transpose(), lhs.transpose(), destT, alpha);\n  }\n};\n\ntemplate<> struct gemv_dense_selector<OnTheRight,ColMajor,true>\n{\n  template<typename Lhs, typename Rhs, typename Dest>\n  static inline void run(const Lhs &lhs, const Rhs &rhs, Dest& dest, const typename Dest::Scalar& alpha)\n  {\n    typedef typename Lhs::Scalar   LhsScalar;\n    typedef typename Rhs::Scalar   RhsScalar;\n    typedef typename Dest::Scalar  ResScalar;\n    typedef typename Dest::RealScalar  RealScalar;\n    \n    typedef internal::blas_traits<Lhs> LhsBlasTraits;\n    typedef typename LhsBlasTraits::DirectLinearAccessType ActualLhsType;\n    typedef internal::blas_traits<Rhs> RhsBlasTraits;\n    typedef typename RhsBlasTraits::DirectLinearAccessType ActualRhsType;\n  \n    typedef Map<Matrix<ResScalar,Dynamic,1>, EIGEN_PLAIN_ENUM_MIN(AlignedMax,internal::packet_traits<ResScalar>::size)> MappedDest;\n\n    ActualLhsType actualLhs = LhsBlasTraits::extract(lhs);\n    ActualRhsType actualRhs = RhsBlasTraits::extract(rhs);\n\n    ResScalar actualAlpha = alpha * LhsBlasTraits::extractScalarFactor(lhs)\n                                  * RhsBlasTraits::extractScalarFactor(rhs);\n\n    // make sure Dest is a compile-time vector type (bug 1166)\n    typedef typename conditional<Dest::IsVectorAtCompileTime, Dest, typename Dest::ColXpr>::type ActualDest;\n\n    enum {\n      // FIXME find a way to allow an inner stride on the result if packet_traits<Scalar>::size==1\n      // on, the other hand it is good for the cache to pack the vector anyways...\n      EvalToDestAtCompileTime = (ActualDest::InnerStrideAtCompileTime==1),\n      ComplexByReal = (NumTraits<LhsScalar>::IsComplex) && (!NumTraits<RhsScalar>::IsComplex),\n      MightCannotUseDest = (ActualDest::InnerStrideAtCompileTime!=1) || ComplexByReal\n    };\n\n    gemv_static_vector_if<ResScalar,ActualDest::SizeAtCompileTime,ActualDest::MaxSizeAtCompileTime,MightCannotUseDest> static_dest;\n\n    const bool alphaIsCompatible = (!ComplexByReal) || (numext::imag(actualAlpha)==RealScalar(0));\n    const bool evalToDest = EvalToDestAtCompileTime && alphaIsCompatible;\n\n    RhsScalar compatibleAlpha = get_factor<ResScalar,RhsScalar>::run(actualAlpha);\n\n    ei_declare_aligned_stack_constructed_variable(ResScalar,actualDestPtr,dest.size(),\n                                                  evalToDest ? dest.data() : static_dest.data());\n\n    if(!evalToDest)\n    {\n      #ifdef EIGEN_DENSE_STORAGE_CTOR_PLUGIN\n      Index size = dest.size();\n      EIGEN_DENSE_STORAGE_CTOR_PLUGIN\n      #endif\n      if(!alphaIsCompatible)\n      {\n        MappedDest(actualDestPtr, dest.size()).setZero();\n        compatibleAlpha = RhsScalar(1);\n      }\n      else\n        MappedDest(actualDestPtr, dest.size()) = dest;\n    }\n\n    typedef const_blas_data_mapper<LhsScalar,Index,ColMajor> LhsMapper;\n    typedef const_blas_data_mapper<RhsScalar,Index,RowMajor> RhsMapper;\n    general_matrix_vector_product\n        <Index,LhsScalar,LhsMapper,ColMajor,LhsBlasTraits::NeedToConjugate,RhsScalar,RhsMapper,RhsBlasTraits::NeedToConjugate>::run(\n        actualLhs.rows(), actualLhs.cols(),\n        LhsMapper(actualLhs.data(), actualLhs.outerStride()),\n        RhsMapper(actualRhs.data(), actualRhs.innerStride()),\n        actualDestPtr, 1,\n        compatibleAlpha);\n\n    if (!evalToDest)\n    {\n      if(!alphaIsCompatible)\n        dest.matrix() += actualAlpha * MappedDest(actualDestPtr, dest.size());\n      else\n        dest = MappedDest(actualDestPtr, dest.size());\n    }\n  }\n};\n\ntemplate<> struct gemv_dense_selector<OnTheRight,RowMajor,true>\n{\n  template<typename Lhs, typename Rhs, typename Dest>\n  static void run(const Lhs &lhs, const Rhs &rhs, Dest& dest, const typename Dest::Scalar& alpha)\n  {\n    typedef typename Lhs::Scalar   LhsScalar;\n    typedef typename Rhs::Scalar   RhsScalar;\n    typedef typename Dest::Scalar  ResScalar;\n    \n    typedef internal::blas_traits<Lhs> LhsBlasTraits;\n    typedef typename LhsBlasTraits::DirectLinearAccessType ActualLhsType;\n    typedef internal::blas_traits<Rhs> RhsBlasTraits;\n    typedef typename RhsBlasTraits::DirectLinearAccessType ActualRhsType;\n    typedef typename internal::remove_all<ActualRhsType>::type ActualRhsTypeCleaned;\n\n    typename add_const<ActualLhsType>::type actualLhs = LhsBlasTraits::extract(lhs);\n    typename add_const<ActualRhsType>::type actualRhs = RhsBlasTraits::extract(rhs);\n\n    ResScalar actualAlpha = alpha * LhsBlasTraits::extractScalarFactor(lhs)\n                                  * RhsBlasTraits::extractScalarFactor(rhs);\n\n    enum {\n      // FIXME find a way to allow an inner stride on the result if packet_traits<Scalar>::size==1\n      // on, the other hand it is good for the cache to pack the vector anyways...\n      DirectlyUseRhs = ActualRhsTypeCleaned::InnerStrideAtCompileTime==1\n    };\n\n    gemv_static_vector_if<RhsScalar,ActualRhsTypeCleaned::SizeAtCompileTime,ActualRhsTypeCleaned::MaxSizeAtCompileTime,!DirectlyUseRhs> static_rhs;\n\n    ei_declare_aligned_stack_constructed_variable(RhsScalar,actualRhsPtr,actualRhs.size(),\n        DirectlyUseRhs ? const_cast<RhsScalar*>(actualRhs.data()) : static_rhs.data());\n\n    if(!DirectlyUseRhs)\n    {\n      #ifdef EIGEN_DENSE_STORAGE_CTOR_PLUGIN\n      Index size = actualRhs.size();\n      EIGEN_DENSE_STORAGE_CTOR_PLUGIN\n      #endif\n      Map<typename ActualRhsTypeCleaned::PlainObject>(actualRhsPtr, actualRhs.size()) = actualRhs;\n    }\n\n    typedef const_blas_data_mapper<LhsScalar,Index,RowMajor> LhsMapper;\n    typedef const_blas_data_mapper<RhsScalar,Index,ColMajor> RhsMapper;\n    general_matrix_vector_product\n        <Index,LhsScalar,LhsMapper,RowMajor,LhsBlasTraits::NeedToConjugate,RhsScalar,RhsMapper,RhsBlasTraits::NeedToConjugate>::run(\n        actualLhs.rows(), actualLhs.cols(),\n        LhsMapper(actualLhs.data(), actualLhs.outerStride()),\n        RhsMapper(actualRhsPtr, 1),\n        dest.data(), dest.col(0).innerStride(), //NOTE  if dest is not a vector at compile-time, then dest.innerStride() might be wrong. (bug 1166)\n        actualAlpha);\n  }\n};\n\ntemplate<> struct gemv_dense_selector<OnTheRight,ColMajor,false>\n{\n  template<typename Lhs, typename Rhs, typename Dest>\n  static void run(const Lhs &lhs, const Rhs &rhs, Dest& dest, const typename Dest::Scalar& alpha)\n  {\n    EIGEN_STATIC_ASSERT((!nested_eval<Lhs,1>::Evaluate),EIGEN_INTERNAL_COMPILATION_ERROR_OR_YOU_MADE_A_PROGRAMMING_MISTAKE);\n    // TODO if rhs is large enough it might be beneficial to make sure that dest is sequentially stored in memory, otherwise use a temp\n    typename nested_eval<Rhs,1>::type actual_rhs(rhs);\n    const Index size = rhs.rows();\n    for(Index k=0; k<size; ++k)\n      dest += (alpha*actual_rhs.coeff(k)) * lhs.col(k);\n  }\n};\n\ntemplate<> struct gemv_dense_selector<OnTheRight,RowMajor,false>\n{\n  template<typename Lhs, typename Rhs, typename Dest>\n  static void run(const Lhs &lhs, const Rhs &rhs, Dest& dest, const typename Dest::Scalar& alpha)\n  {\n    EIGEN_STATIC_ASSERT((!nested_eval<Lhs,1>::Evaluate),EIGEN_INTERNAL_COMPILATION_ERROR_OR_YOU_MADE_A_PROGRAMMING_MISTAKE);\n    typename nested_eval<Rhs,Lhs::RowsAtCompileTime>::type actual_rhs(rhs);\n    const Index rows = dest.rows();\n    for(Index i=0; i<rows; ++i)\n      dest.coeffRef(i) += alpha * (lhs.row(i).cwiseProduct(actual_rhs.transpose())).sum();\n  }\n};\n\n} // end namespace internal\n\n/***************************************************************************\n* Implementation of matrix base methods\n***************************************************************************/\n\n/** \\returns the matrix product of \\c *this and \\a other.\n  *\n  * \\note If instead of the matrix product you want the coefficient-wise product, see Cwise::operator*().\n  *\n  * \\sa lazyProduct(), operator*=(const MatrixBase&), Cwise::operator*()\n  */\n#ifndef __CUDACC__\n\ntemplate<typename Derived>\ntemplate<typename OtherDerived>\ninline const Product<Derived, OtherDerived>\nMatrixBase<Derived>::operator*(const MatrixBase<OtherDerived> &other) const\n{\n  // A note regarding the function declaration: In MSVC, this function will sometimes\n  // not be inlined since DenseStorage is an unwindable object for dynamic\n  // matrices and product types are holding a member to store the result.\n  // Thus it does not help tagging this function with EIGEN_STRONG_INLINE.\n  enum {\n    ProductIsValid =  Derived::ColsAtCompileTime==Dynamic\n                   || OtherDerived::RowsAtCompileTime==Dynamic\n                   || int(Derived::ColsAtCompileTime)==int(OtherDerived::RowsAtCompileTime),\n    AreVectors = Derived::IsVectorAtCompileTime && OtherDerived::IsVectorAtCompileTime,\n    SameSizes = EIGEN_PREDICATE_SAME_MATRIX_SIZE(Derived,OtherDerived)\n  };\n  // note to the lost user:\n  //    * for a dot product use: v1.dot(v2)\n  //    * for a coeff-wise product use: v1.cwiseProduct(v2)\n  EIGEN_STATIC_ASSERT(ProductIsValid || !(AreVectors && SameSizes),\n    INVALID_VECTOR_VECTOR_PRODUCT__IF_YOU_WANTED_A_DOT_OR_COEFF_WISE_PRODUCT_YOU_MUST_USE_THE_EXPLICIT_FUNCTIONS)\n  EIGEN_STATIC_ASSERT(ProductIsValid || !(SameSizes && !AreVectors),\n    INVALID_MATRIX_PRODUCT__IF_YOU_WANTED_A_COEFF_WISE_PRODUCT_YOU_MUST_USE_THE_EXPLICIT_FUNCTION)\n  EIGEN_STATIC_ASSERT(ProductIsValid || SameSizes, INVALID_MATRIX_PRODUCT)\n#ifdef EIGEN_DEBUG_PRODUCT\n  internal::product_type<Derived,OtherDerived>::debug();\n#endif\n\n  return Product<Derived, OtherDerived>(derived(), other.derived());\n}\n\n#endif // __CUDACC__\n\n/** \\returns an expression of the matrix product of \\c *this and \\a other without implicit evaluation.\n  *\n  * The returned product will behave like any other expressions: the coefficients of the product will be\n  * computed once at a time as requested. This might be useful in some extremely rare cases when only\n  * a small and no coherent fraction of the result's coefficients have to be computed.\n  *\n  * \\warning This version of the matrix product can be much much slower. So use it only if you know\n  * what you are doing and that you measured a true speed improvement.\n  *\n  * \\sa operator*(const MatrixBase&)\n  */\ntemplate<typename Derived>\ntemplate<typename OtherDerived>\nconst Product<Derived,OtherDerived,LazyProduct>\nMatrixBase<Derived>::lazyProduct(const MatrixBase<OtherDerived> &other) const\n{\n  enum {\n    ProductIsValid =  Derived::ColsAtCompileTime==Dynamic\n                   || OtherDerived::RowsAtCompileTime==Dynamic\n                   || int(Derived::ColsAtCompileTime)==int(OtherDerived::RowsAtCompileTime),\n    AreVectors = Derived::IsVectorAtCompileTime && OtherDerived::IsVectorAtCompileTime,\n    SameSizes = EIGEN_PREDICATE_SAME_MATRIX_SIZE(Derived,OtherDerived)\n  };\n  // note to the lost user:\n  //    * for a dot product use: v1.dot(v2)\n  //    * for a coeff-wise product use: v1.cwiseProduct(v2)\n  EIGEN_STATIC_ASSERT(ProductIsValid || !(AreVectors && SameSizes),\n    INVALID_VECTOR_VECTOR_PRODUCT__IF_YOU_WANTED_A_DOT_OR_COEFF_WISE_PRODUCT_YOU_MUST_USE_THE_EXPLICIT_FUNCTIONS)\n  EIGEN_STATIC_ASSERT(ProductIsValid || !(SameSizes && !AreVectors),\n    INVALID_MATRIX_PRODUCT__IF_YOU_WANTED_A_COEFF_WISE_PRODUCT_YOU_MUST_USE_THE_EXPLICIT_FUNCTION)\n  EIGEN_STATIC_ASSERT(ProductIsValid || SameSizes, INVALID_MATRIX_PRODUCT)\n\n  return Product<Derived,OtherDerived,LazyProduct>(derived(), other.derived());\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_PRODUCT_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/GenericPacketMath.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2006-2008 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_GENERIC_PACKET_MATH_H\n#define EIGEN_GENERIC_PACKET_MATH_H\n\nnamespace Eigen {\n\nnamespace internal {\n\n/** \\internal\n  * \\file GenericPacketMath.h\n  *\n  * Default implementation for types not supported by the vectorization.\n  * In practice these functions are provided to make easier the writing\n  * of generic vectorized code.\n  */\n\n#ifndef EIGEN_DEBUG_ALIGNED_LOAD\n#define EIGEN_DEBUG_ALIGNED_LOAD\n#endif\n\n#ifndef EIGEN_DEBUG_UNALIGNED_LOAD\n#define EIGEN_DEBUG_UNALIGNED_LOAD\n#endif\n\n#ifndef EIGEN_DEBUG_ALIGNED_STORE\n#define EIGEN_DEBUG_ALIGNED_STORE\n#endif\n\n#ifndef EIGEN_DEBUG_UNALIGNED_STORE\n#define EIGEN_DEBUG_UNALIGNED_STORE\n#endif\n\nstruct default_packet_traits\n{\n  enum {\n    HasHalfPacket = 0,\n\n    HasAdd    = 1,\n    HasSub    = 1,\n    HasMul    = 1,\n    HasNegate = 1,\n    HasAbs    = 1,\n    HasArg    = 0,\n    HasAbs2   = 1,\n    HasMin    = 1,\n    HasMax    = 1,\n    HasConj   = 1,\n    HasSetLinear = 1,\n    HasBlend  = 0,\n\n    HasDiv    = 0,\n    HasSqrt   = 0,\n    HasRsqrt  = 0,\n    HasExp    = 0,\n    HasLog    = 0,\n    HasLog1p  = 0,\n    HasLog10  = 0,\n    HasPow    = 0,\n\n    HasSin    = 0,\n    HasCos    = 0,\n    HasTan    = 0,\n    HasASin   = 0,\n    HasACos   = 0,\n    HasATan   = 0,\n    HasSinh   = 0,\n    HasCosh   = 0,\n    HasTanh   = 0,\n    HasLGamma = 0,\n    HasDiGamma = 0,\n    HasZeta = 0,\n    HasPolygamma = 0,\n    HasErf = 0,\n    HasErfc = 0,\n    HasIGamma = 0,\n    HasIGammac = 0,\n    HasBetaInc = 0,\n\n    HasRound  = 0,\n    HasFloor  = 0,\n    HasCeil   = 0,\n\n    HasSign   = 0\n  };\n};\n\ntemplate<typename T> struct packet_traits : default_packet_traits\n{\n  typedef T type;\n  typedef T half;\n  enum {\n    Vectorizable = 0,\n    size = 1,\n    AlignedOnScalar = 0,\n    HasHalfPacket = 0\n  };\n  enum {\n    HasAdd    = 0,\n    HasSub    = 0,\n    HasMul    = 0,\n    HasNegate = 0,\n    HasAbs    = 0,\n    HasAbs2   = 0,\n    HasMin    = 0,\n    HasMax    = 0,\n    HasConj   = 0,\n    HasSetLinear = 0\n  };\n};\n\ntemplate<typename T> struct packet_traits<const T> : packet_traits<T> { };\n\ntemplate <typename Src, typename Tgt> struct type_casting_traits {\n  enum {\n    VectorizedCast = 0,\n    SrcCoeffRatio = 1,\n    TgtCoeffRatio = 1\n  };\n};\n\n\n/** \\internal \\returns static_cast<TgtType>(a) (coeff-wise) */\ntemplate <typename SrcPacket, typename TgtPacket>\nEIGEN_DEVICE_FUNC inline TgtPacket\npcast(const SrcPacket& a) {\n  return static_cast<TgtPacket>(a);\n}\ntemplate <typename SrcPacket, typename TgtPacket>\nEIGEN_DEVICE_FUNC inline TgtPacket\npcast(const SrcPacket& a, const SrcPacket& /*b*/) {\n  return static_cast<TgtPacket>(a);\n}\n\ntemplate <typename SrcPacket, typename TgtPacket>\nEIGEN_DEVICE_FUNC inline TgtPacket\npcast(const SrcPacket& a, const SrcPacket& /*b*/, const SrcPacket& /*c*/, const SrcPacket& /*d*/) {\n  return static_cast<TgtPacket>(a);\n}\n\n/** \\internal \\returns a + b (coeff-wise) */\ntemplate<typename Packet> EIGEN_DEVICE_FUNC inline Packet\npadd(const Packet& a,\n        const Packet& b) { return a+b; }\n\n/** \\internal \\returns a - b (coeff-wise) */\ntemplate<typename Packet> EIGEN_DEVICE_FUNC inline Packet\npsub(const Packet& a,\n        const Packet& b) { return a-b; }\n\n/** \\internal \\returns -a (coeff-wise) */\ntemplate<typename Packet> EIGEN_DEVICE_FUNC inline Packet\npnegate(const Packet& a) { return -a; }\n\n/** \\internal \\returns conj(a) (coeff-wise) */\n\ntemplate<typename Packet> EIGEN_DEVICE_FUNC inline Packet\npconj(const Packet& a) { return numext::conj(a); }\n\n/** \\internal \\returns a * b (coeff-wise) */\ntemplate<typename Packet> EIGEN_DEVICE_FUNC inline Packet\npmul(const Packet& a,\n        const Packet& b) { return a*b; }\n\n/** \\internal \\returns a / b (coeff-wise) */\ntemplate<typename Packet> EIGEN_DEVICE_FUNC inline Packet\npdiv(const Packet& a,\n        const Packet& b) { return a/b; }\n\n/** \\internal \\returns the min of \\a a and \\a b  (coeff-wise) */\ntemplate<typename Packet> EIGEN_DEVICE_FUNC inline Packet\npmin(const Packet& a,\n        const Packet& b) { return numext::mini(a, b); }\n\n/** \\internal \\returns the max of \\a a and \\a b  (coeff-wise) */\ntemplate<typename Packet> EIGEN_DEVICE_FUNC inline Packet\npmax(const Packet& a,\n        const Packet& b) { return numext::maxi(a, b); }\n\n/** \\internal \\returns the absolute value of \\a a */\ntemplate<typename Packet> EIGEN_DEVICE_FUNC inline Packet\npabs(const Packet& a) { using std::abs; return abs(a); }\n\n/** \\internal \\returns the phase angle of \\a a */\ntemplate<typename Packet> EIGEN_DEVICE_FUNC inline Packet\nparg(const Packet& a) { using numext::arg; return arg(a); }\n\n/** \\internal \\returns the bitwise and of \\a a and \\a b */\ntemplate<typename Packet> EIGEN_DEVICE_FUNC inline Packet\npand(const Packet& a, const Packet& b) { return a & b; }\n\n/** \\internal \\returns the bitwise or of \\a a and \\a b */\ntemplate<typename Packet> EIGEN_DEVICE_FUNC inline Packet\npor(const Packet& a, const Packet& b) { return a | b; }\n\n/** \\internal \\returns the bitwise xor of \\a a and \\a b */\ntemplate<typename Packet> EIGEN_DEVICE_FUNC inline Packet\npxor(const Packet& a, const Packet& b) { return a ^ b; }\n\n/** \\internal \\returns the bitwise andnot of \\a a and \\a b */\ntemplate<typename Packet> EIGEN_DEVICE_FUNC inline Packet\npandnot(const Packet& a, const Packet& b) { return a & (!b); }\n\n/** \\internal \\returns a packet version of \\a *from, from must be 16 bytes aligned */\ntemplate<typename Packet> EIGEN_DEVICE_FUNC inline Packet\npload(const typename unpacket_traits<Packet>::type* from) { return *from; }\n\n/** \\internal \\returns a packet version of \\a *from, (un-aligned load) */\ntemplate<typename Packet> EIGEN_DEVICE_FUNC inline Packet\nploadu(const typename unpacket_traits<Packet>::type* from) { return *from; }\n\n/** \\internal \\returns a packet with constant coefficients \\a a, e.g.: (a,a,a,a) */\ntemplate<typename Packet> EIGEN_DEVICE_FUNC inline Packet\npset1(const typename unpacket_traits<Packet>::type& a) { return a; }\n\n/** \\internal \\returns a packet with constant coefficients \\a a[0], e.g.: (a[0],a[0],a[0],a[0]) */\ntemplate<typename Packet> EIGEN_DEVICE_FUNC inline Packet\npload1(const typename unpacket_traits<Packet>::type  *a) { return pset1<Packet>(*a); }\n\n/** \\internal \\returns a packet with elements of \\a *from duplicated.\n  * For instance, for a packet of 8 elements, 4 scalars will be read from \\a *from and\n  * duplicated to form: {from[0],from[0],from[1],from[1],from[2],from[2],from[3],from[3]}\n  * Currently, this function is only used for scalar * complex products.\n  */\ntemplate<typename Packet> EIGEN_DEVICE_FUNC inline Packet\nploaddup(const typename unpacket_traits<Packet>::type* from) { return *from; }\n\n/** \\internal \\returns a packet with elements of \\a *from quadrupled.\n  * For instance, for a packet of 8 elements, 2 scalars will be read from \\a *from and\n  * replicated to form: {from[0],from[0],from[0],from[0],from[1],from[1],from[1],from[1]}\n  * Currently, this function is only used in matrix products.\n  * For packet-size smaller or equal to 4, this function is equivalent to pload1 \n  */\ntemplate<typename Packet> EIGEN_DEVICE_FUNC inline Packet\nploadquad(const typename unpacket_traits<Packet>::type* from)\n{ return pload1<Packet>(from); }\n\n/** \\internal equivalent to\n  * \\code\n  * a0 = pload1(a+0);\n  * a1 = pload1(a+1);\n  * a2 = pload1(a+2);\n  * a3 = pload1(a+3);\n  * \\endcode\n  * \\sa pset1, pload1, ploaddup, pbroadcast2\n  */\ntemplate<typename Packet> EIGEN_DEVICE_FUNC\ninline void pbroadcast4(const typename unpacket_traits<Packet>::type *a,\n                        Packet& a0, Packet& a1, Packet& a2, Packet& a3)\n{\n  a0 = pload1<Packet>(a+0);\n  a1 = pload1<Packet>(a+1);\n  a2 = pload1<Packet>(a+2);\n  a3 = pload1<Packet>(a+3);\n}\n\n/** \\internal equivalent to\n  * \\code\n  * a0 = pload1(a+0);\n  * a1 = pload1(a+1);\n  * \\endcode\n  * \\sa pset1, pload1, ploaddup, pbroadcast4\n  */\ntemplate<typename Packet> EIGEN_DEVICE_FUNC\ninline void pbroadcast2(const typename unpacket_traits<Packet>::type *a,\n                        Packet& a0, Packet& a1)\n{\n  a0 = pload1<Packet>(a+0);\n  a1 = pload1<Packet>(a+1);\n}\n\n/** \\internal \\brief Returns a packet with coefficients (a,a+1,...,a+packet_size-1). */\ntemplate<typename Packet> inline Packet\nplset(const typename unpacket_traits<Packet>::type& a) { return a; }\n\n/** \\internal copy the packet \\a from to \\a *to, \\a to must be 16 bytes aligned */\ntemplate<typename Scalar, typename Packet> EIGEN_DEVICE_FUNC inline void pstore(Scalar* to, const Packet& from)\n{ (*to) = from; }\n\n/** \\internal copy the packet \\a from to \\a *to, (un-aligned store) */\ntemplate<typename Scalar, typename Packet> EIGEN_DEVICE_FUNC inline void pstoreu(Scalar* to, const Packet& from)\n{  (*to) = from; }\n\n template<typename Scalar, typename Packet> EIGEN_DEVICE_FUNC inline Packet pgather(const Scalar* from, Index /*stride*/)\n { return ploadu<Packet>(from); }\n\n template<typename Scalar, typename Packet> EIGEN_DEVICE_FUNC inline void pscatter(Scalar* to, const Packet& from, Index /*stride*/)\n { pstore(to, from); }\n\n/** \\internal tries to do cache prefetching of \\a addr */\ntemplate<typename Scalar> EIGEN_DEVICE_FUNC inline void prefetch(const Scalar* addr)\n{\n#ifdef __CUDA_ARCH__\n#if defined(__LP64__)\n  // 64-bit pointer operand constraint for inlined asm\n  asm(\" prefetch.L1 [ %1 ];\" : \"=l\"(addr) : \"l\"(addr));\n#else\n  // 32-bit pointer operand constraint for inlined asm\n  asm(\" prefetch.L1 [ %1 ];\" : \"=r\"(addr) : \"r\"(addr));\n#endif\n#elif (!EIGEN_COMP_MSVC) && (EIGEN_COMP_GNUC || EIGEN_COMP_CLANG || EIGEN_COMP_ICC)\n  __builtin_prefetch(addr);\n#endif\n}\n\n/** \\internal \\returns the first element of a packet */\ntemplate<typename Packet> EIGEN_DEVICE_FUNC inline typename unpacket_traits<Packet>::type pfirst(const Packet& a)\n{ return a; }\n\n/** \\internal \\returns a packet where the element i contains the sum of the packet of \\a vec[i] */\ntemplate<typename Packet> EIGEN_DEVICE_FUNC inline Packet\npreduxp(const Packet* vecs) { return vecs[0]; }\n\n/** \\internal \\returns the sum of the elements of \\a a*/\ntemplate<typename Packet> EIGEN_DEVICE_FUNC inline typename unpacket_traits<Packet>::type predux(const Packet& a)\n{ return a; }\n\n/** \\internal \\returns the sum of the elements of \\a a by block of 4 elements.\n  * For a packet {a0, a1, a2, a3, a4, a5, a6, a7}, it returns a half packet {a0+a4, a1+a5, a2+a6, a3+a7}\n  * For packet-size smaller or equal to 4, this boils down to a noop.\n  */\ntemplate<typename Packet> EIGEN_DEVICE_FUNC inline\ntypename conditional<(unpacket_traits<Packet>::size%8)==0,typename unpacket_traits<Packet>::half,Packet>::type\npredux_downto4(const Packet& a)\n{ return a; }\n\n/** \\internal \\returns the product of the elements of \\a a*/\ntemplate<typename Packet> EIGEN_DEVICE_FUNC inline typename unpacket_traits<Packet>::type predux_mul(const Packet& a)\n{ return a; }\n\n/** \\internal \\returns the min of the elements of \\a a*/\ntemplate<typename Packet> EIGEN_DEVICE_FUNC inline typename unpacket_traits<Packet>::type predux_min(const Packet& a)\n{ return a; }\n\n/** \\internal \\returns the max of the elements of \\a a*/\ntemplate<typename Packet> EIGEN_DEVICE_FUNC inline typename unpacket_traits<Packet>::type predux_max(const Packet& a)\n{ return a; }\n\n/** \\internal \\returns the reversed elements of \\a a*/\ntemplate<typename Packet> EIGEN_DEVICE_FUNC inline Packet preverse(const Packet& a)\n{ return a; }\n\n/** \\internal \\returns \\a a with real and imaginary part flipped (for complex type only) */\ntemplate<typename Packet> EIGEN_DEVICE_FUNC inline Packet pcplxflip(const Packet& a)\n{\n  // FIXME: uncomment the following in case we drop the internal imag and real functions.\n//   using std::imag;\n//   using std::real;\n  return Packet(imag(a),real(a));\n}\n\n/**************************\n* Special math functions\n***************************/\n\n/** \\internal \\returns the sine of \\a a (coeff-wise) */\ntemplate<typename Packet> EIGEN_DECLARE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS\nPacket psin(const Packet& a) { using std::sin; return sin(a); }\n\n/** \\internal \\returns the cosine of \\a a (coeff-wise) */\ntemplate<typename Packet> EIGEN_DECLARE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS\nPacket pcos(const Packet& a) { using std::cos; return cos(a); }\n\n/** \\internal \\returns the tan of \\a a (coeff-wise) */\ntemplate<typename Packet> EIGEN_DECLARE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS\nPacket ptan(const Packet& a) { using std::tan; return tan(a); }\n\n/** \\internal \\returns the arc sine of \\a a (coeff-wise) */\ntemplate<typename Packet> EIGEN_DECLARE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS\nPacket pasin(const Packet& a) { using std::asin; return asin(a); }\n\n/** \\internal \\returns the arc cosine of \\a a (coeff-wise) */\ntemplate<typename Packet> EIGEN_DECLARE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS\nPacket pacos(const Packet& a) { using std::acos; return acos(a); }\n\n/** \\internal \\returns the arc tangent of \\a a (coeff-wise) */\ntemplate<typename Packet> EIGEN_DECLARE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS\nPacket patan(const Packet& a) { using std::atan; return atan(a); }\n\n/** \\internal \\returns the hyperbolic sine of \\a a (coeff-wise) */\ntemplate<typename Packet> EIGEN_DECLARE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS\nPacket psinh(const Packet& a) { using std::sinh; return sinh(a); }\n\n/** \\internal \\returns the hyperbolic cosine of \\a a (coeff-wise) */\ntemplate<typename Packet> EIGEN_DECLARE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS\nPacket pcosh(const Packet& a) { using std::cosh; return cosh(a); }\n\n/** \\internal \\returns the hyperbolic tan of \\a a (coeff-wise) */\ntemplate<typename Packet> EIGEN_DECLARE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS\nPacket ptanh(const Packet& a) { using std::tanh; return tanh(a); }\n\n/** \\internal \\returns the exp of \\a a (coeff-wise) */\ntemplate<typename Packet> EIGEN_DECLARE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS\nPacket pexp(const Packet& a) { using std::exp; return exp(a); }\n\n/** \\internal \\returns the log of \\a a (coeff-wise) */\ntemplate<typename Packet> EIGEN_DECLARE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS\nPacket plog(const Packet& a) { using std::log; return log(a); }\n\n/** \\internal \\returns the log1p of \\a a (coeff-wise) */\ntemplate<typename Packet> EIGEN_DECLARE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS\nPacket plog1p(const Packet& a) { return numext::log1p(a); }\n\n/** \\internal \\returns the log10 of \\a a (coeff-wise) */\ntemplate<typename Packet> EIGEN_DECLARE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS\nPacket plog10(const Packet& a) { using std::log10; return log10(a); }\n\n/** \\internal \\returns the square-root of \\a a (coeff-wise) */\ntemplate<typename Packet> EIGEN_DECLARE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS\nPacket psqrt(const Packet& a) { using std::sqrt; return sqrt(a); }\n\n/** \\internal \\returns the reciprocal square-root of \\a a (coeff-wise) */\ntemplate<typename Packet> EIGEN_DECLARE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS\nPacket prsqrt(const Packet& a) {\n  return pdiv(pset1<Packet>(1), psqrt(a));\n}\n\n/** \\internal \\returns the rounded value of \\a a (coeff-wise) */\ntemplate<typename Packet> EIGEN_DECLARE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS\nPacket pround(const Packet& a) { using numext::round; return round(a); }\n\n/** \\internal \\returns the floor of \\a a (coeff-wise) */\ntemplate<typename Packet> EIGEN_DECLARE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS\nPacket pfloor(const Packet& a) { using numext::floor; return floor(a); }\n\n/** \\internal \\returns the ceil of \\a a (coeff-wise) */\ntemplate<typename Packet> EIGEN_DECLARE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS\nPacket pceil(const Packet& a) { using numext::ceil; return ceil(a); }\n\n/***************************************************************************\n* The following functions might not have to be overwritten for vectorized types\n***************************************************************************/\n\n/** \\internal copy a packet with constant coeficient \\a a (e.g., [a,a,a,a]) to \\a *to. \\a to must be 16 bytes aligned */\n// NOTE: this function must really be templated on the packet type (think about different packet types for the same scalar type)\ntemplate<typename Packet>\ninline void pstore1(typename unpacket_traits<Packet>::type* to, const typename unpacket_traits<Packet>::type& a)\n{\n  pstore(to, pset1<Packet>(a));\n}\n\n/** \\internal \\returns a * b + c (coeff-wise) */\ntemplate<typename Packet> EIGEN_DEVICE_FUNC inline Packet\npmadd(const Packet&  a,\n         const Packet&  b,\n         const Packet&  c)\n{ return padd(pmul(a, b),c); }\n\n/** \\internal \\returns a packet version of \\a *from.\n  * The pointer \\a from must be aligned on a \\a Alignment bytes boundary. */\ntemplate<typename Packet, int Alignment>\nEIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE Packet ploadt(const typename unpacket_traits<Packet>::type* from)\n{\n  if(Alignment >= unpacket_traits<Packet>::alignment)\n    return pload<Packet>(from);\n  else\n    return ploadu<Packet>(from);\n}\n\n/** \\internal copy the packet \\a from to \\a *to.\n  * The pointer \\a from must be aligned on a \\a Alignment bytes boundary. */\ntemplate<typename Scalar, typename Packet, int Alignment>\nEIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE void pstoret(Scalar* to, const Packet& from)\n{\n  if(Alignment >= unpacket_traits<Packet>::alignment)\n    pstore(to, from);\n  else\n    pstoreu(to, from);\n}\n\n/** \\internal \\returns a packet version of \\a *from.\n  * Unlike ploadt, ploadt_ro takes advantage of the read-only memory path on the\n  * hardware if available to speedup the loading of data that won't be modified\n  * by the current computation.\n  */\ntemplate<typename Packet, int LoadMode>\ninline Packet ploadt_ro(const typename unpacket_traits<Packet>::type* from)\n{\n  return ploadt<Packet, LoadMode>(from);\n}\n\n/** \\internal default implementation of palign() allowing partial specialization */\ntemplate<int Offset,typename PacketType>\nstruct palign_impl\n{\n  // by default data are aligned, so there is nothing to be done :)\n  static inline void run(PacketType&, const PacketType&) {}\n};\n\n/** \\internal update \\a first using the concatenation of the packet_size minus \\a Offset last elements\n  * of \\a first and \\a Offset first elements of \\a second.\n  * \n  * This function is currently only used to optimize matrix-vector products on unligned matrices.\n  * It takes 2 packets that represent a contiguous memory array, and returns a packet starting\n  * at the position \\a Offset. For instance, for packets of 4 elements, we have:\n  *  Input:\n  *  - first = {f0,f1,f2,f3}\n  *  - second = {s0,s1,s2,s3}\n  * Output: \n  *   - if Offset==0 then {f0,f1,f2,f3}\n  *   - if Offset==1 then {f1,f2,f3,s0}\n  *   - if Offset==2 then {f2,f3,s0,s1}\n  *   - if Offset==3 then {f3,s0,s1,s3}\n  */\ntemplate<int Offset,typename PacketType>\ninline void palign(PacketType& first, const PacketType& second)\n{\n  palign_impl<Offset,PacketType>::run(first,second);\n}\n\n/***************************************************************************\n* Fast complex products (GCC generates a function call which is very slow)\n***************************************************************************/\n\n// Eigen+CUDA does not support complexes.\n#ifndef __CUDACC__\n\ntemplate<> inline std::complex<float> pmul(const std::complex<float>& a, const std::complex<float>& b)\n{ return std::complex<float>(real(a)*real(b) - imag(a)*imag(b), imag(a)*real(b) + real(a)*imag(b)); }\n\ntemplate<> inline std::complex<double> pmul(const std::complex<double>& a, const std::complex<double>& b)\n{ return std::complex<double>(real(a)*real(b) - imag(a)*imag(b), imag(a)*real(b) + real(a)*imag(b)); }\n\n#endif\n\n\n/***************************************************************************\n * PacketBlock, that is a collection of N packets where the number of words\n * in the packet is a multiple of N.\n***************************************************************************/\ntemplate <typename Packet,int N=unpacket_traits<Packet>::size> struct PacketBlock {\n  Packet packet[N];\n};\n\ntemplate<typename Packet> EIGEN_DEVICE_FUNC inline void\nptranspose(PacketBlock<Packet,1>& /*kernel*/) {\n  // Nothing to do in the scalar case, i.e. a 1x1 matrix.\n}\n\n/***************************************************************************\n * Selector, i.e. vector of N boolean values used to select (i.e. blend)\n * words from 2 packets.\n***************************************************************************/\ntemplate <size_t N> struct Selector {\n  bool select[N];\n};\n\ntemplate<typename Packet> EIGEN_DEVICE_FUNC inline Packet\npblend(const Selector<unpacket_traits<Packet>::size>& ifPacket, const Packet& thenPacket, const Packet& elsePacket) {\n  return ifPacket.select[0] ? thenPacket : elsePacket;\n}\n\n/** \\internal \\returns \\a a with the first coefficient replaced by the scalar b */\ntemplate<typename Packet> EIGEN_DEVICE_FUNC inline Packet\npinsertfirst(const Packet& a, typename unpacket_traits<Packet>::type b)\n{\n  // Default implementation based on pblend.\n  // It must be specialized for higher performance.\n  Selector<unpacket_traits<Packet>::size> mask;\n  mask.select[0] = true;\n  // This for loop should be optimized away by the compiler.\n  for(Index i=1; i<unpacket_traits<Packet>::size; ++i)\n    mask.select[i] = false;\n  return pblend(mask, pset1<Packet>(b), a);\n}\n\n/** \\internal \\returns \\a a with the last coefficient replaced by the scalar b */\ntemplate<typename Packet> EIGEN_DEVICE_FUNC inline Packet\npinsertlast(const Packet& a, typename unpacket_traits<Packet>::type b)\n{\n  // Default implementation based on pblend.\n  // It must be specialized for higher performance.\n  Selector<unpacket_traits<Packet>::size> mask;\n  // This for loop should be optimized away by the compiler.\n  for(Index i=0; i<unpacket_traits<Packet>::size-1; ++i)\n    mask.select[i] = false;\n  mask.select[unpacket_traits<Packet>::size-1] = true;\n  return pblend(mask, pset1<Packet>(b), a);\n}\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_GENERIC_PACKET_MATH_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/GlobalFunctions.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2010-2016 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2010 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_GLOBAL_FUNCTIONS_H\n#define EIGEN_GLOBAL_FUNCTIONS_H\n\n#ifdef EIGEN_PARSED_BY_DOXYGEN\n\n#define EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(NAME,FUNCTOR,DOC_OP,DOC_DETAILS) \\\n  /** \\returns an expression of the coefficient-wise DOC_OP of \\a x\n\n    DOC_DETAILS\n\n    \\sa <a href=\"group__CoeffwiseMathFunctions.html#cwisetable_##NAME\">Math functions</a>, class CwiseUnaryOp\n    */ \\\n  template<typename Derived> \\\n  inline const Eigen::CwiseUnaryOp<Eigen::internal::FUNCTOR<typename Derived::Scalar>, const Derived> \\\n  NAME(const Eigen::ArrayBase<Derived>& x);\n\n#else\n\n#define EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(NAME,FUNCTOR,DOC_OP,DOC_DETAILS) \\\n  template<typename Derived> \\\n  inline const Eigen::CwiseUnaryOp<Eigen::internal::FUNCTOR<typename Derived::Scalar>, const Derived> \\\n  (NAME)(const Eigen::ArrayBase<Derived>& x) { \\\n    return Eigen::CwiseUnaryOp<Eigen::internal::FUNCTOR<typename Derived::Scalar>, const Derived>(x.derived()); \\\n  }\n\n#endif // EIGEN_PARSED_BY_DOXYGEN\n\n#define EIGEN_ARRAY_DECLARE_GLOBAL_EIGEN_UNARY(NAME,FUNCTOR) \\\n  \\\n  template<typename Derived> \\\n  struct NAME##_retval<ArrayBase<Derived> > \\\n  { \\\n    typedef const Eigen::CwiseUnaryOp<Eigen::internal::FUNCTOR<typename Derived::Scalar>, const Derived> type; \\\n  }; \\\n  template<typename Derived> \\\n  struct NAME##_impl<ArrayBase<Derived> > \\\n  { \\\n    static inline typename NAME##_retval<ArrayBase<Derived> >::type run(const Eigen::ArrayBase<Derived>& x) \\\n    { \\\n      return typename NAME##_retval<ArrayBase<Derived> >::type(x.derived()); \\\n    } \\\n  };\n\nnamespace Eigen\n{\n  EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(real,scalar_real_op,real part,\\sa ArrayBase::real)\n  EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(imag,scalar_imag_op,imaginary part,\\sa ArrayBase::imag)\n  EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(conj,scalar_conjugate_op,complex conjugate,\\sa ArrayBase::conjugate)\n  EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(inverse,scalar_inverse_op,inverse,\\sa ArrayBase::inverse)\n  EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(sin,scalar_sin_op,sine,\\sa ArrayBase::sin)\n  EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(cos,scalar_cos_op,cosine,\\sa ArrayBase::cos)\n  EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(tan,scalar_tan_op,tangent,\\sa ArrayBase::tan)\n  EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(atan,scalar_atan_op,arc-tangent,\\sa ArrayBase::atan)\n  EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(asin,scalar_asin_op,arc-sine,\\sa ArrayBase::asin)\n  EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(acos,scalar_acos_op,arc-consine,\\sa ArrayBase::acos)\n  EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(sinh,scalar_sinh_op,hyperbolic sine,\\sa ArrayBase::sinh)\n  EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(cosh,scalar_cosh_op,hyperbolic cosine,\\sa ArrayBase::cosh)\n  EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(tanh,scalar_tanh_op,hyperbolic tangent,\\sa ArrayBase::tanh)\n  EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(lgamma,scalar_lgamma_op,natural logarithm of the gamma function,\\sa ArrayBase::lgamma)\n  EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(digamma,scalar_digamma_op,derivative of lgamma,\\sa ArrayBase::digamma)\n  EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(erf,scalar_erf_op,error function,\\sa ArrayBase::erf)\n  EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(erfc,scalar_erfc_op,complement error function,\\sa ArrayBase::erfc)\n  EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(exp,scalar_exp_op,exponential,\\sa ArrayBase::exp)\n  EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(log,scalar_log_op,natural logarithm,\\sa Eigen::log10 DOXCOMMA ArrayBase::log)\n  EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(log1p,scalar_log1p_op,natural logarithm of 1 plus the value,\\sa ArrayBase::log1p)\n  EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(log10,scalar_log10_op,base 10 logarithm,\\sa Eigen::log DOXCOMMA ArrayBase::log)\n  EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(abs,scalar_abs_op,absolute value,\\sa ArrayBase::abs DOXCOMMA MatrixBase::cwiseAbs)\n  EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(abs2,scalar_abs2_op,squared absolute value,\\sa ArrayBase::abs2 DOXCOMMA MatrixBase::cwiseAbs2)\n  EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(arg,scalar_arg_op,complex argument,\\sa ArrayBase::arg)\n  EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(sqrt,scalar_sqrt_op,square root,\\sa ArrayBase::sqrt DOXCOMMA MatrixBase::cwiseSqrt)\n  EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(rsqrt,scalar_rsqrt_op,reciprocal square root,\\sa ArrayBase::rsqrt)\n  EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(square,scalar_square_op,square (power 2),\\sa Eigen::abs2 DOXCOMMA Eigen::pow DOXCOMMA ArrayBase::square)\n  EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(cube,scalar_cube_op,cube (power 3),\\sa Eigen::pow DOXCOMMA ArrayBase::cube)\n  EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(round,scalar_round_op,nearest integer,\\sa Eigen::floor DOXCOMMA Eigen::ceil DOXCOMMA ArrayBase::round)\n  EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(floor,scalar_floor_op,nearest integer not greater than the giben value,\\sa Eigen::ceil DOXCOMMA ArrayBase::floor)\n  EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(ceil,scalar_ceil_op,nearest integer not less than the giben value,\\sa Eigen::floor DOXCOMMA ArrayBase::ceil)\n  EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(isnan,scalar_isnan_op,not-a-number test,\\sa Eigen::isinf DOXCOMMA Eigen::isfinite DOXCOMMA ArrayBase::isnan)\n  EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(isinf,scalar_isinf_op,infinite value test,\\sa Eigen::isnan DOXCOMMA Eigen::isfinite DOXCOMMA ArrayBase::isinf)\n  EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(isfinite,scalar_isfinite_op,finite value test,\\sa Eigen::isinf DOXCOMMA Eigen::isnan DOXCOMMA ArrayBase::isfinite)\n  EIGEN_ARRAY_DECLARE_GLOBAL_UNARY(sign,scalar_sign_op,sign (or 0),\\sa ArrayBase::sign)\n  \n  /** \\returns an expression of the coefficient-wise power of \\a x to the given constant \\a exponent.\n    *\n    * \\tparam ScalarExponent is the scalar type of \\a exponent. It must be compatible with the scalar type of the given expression (\\c Derived::Scalar).\n    *\n    * \\sa ArrayBase::pow()\n    *\n    * \\relates ArrayBase\n    */\n#ifdef EIGEN_PARSED_BY_DOXYGEN\n  template<typename Derived,typename ScalarExponent>\n  inline const CwiseBinaryOp<internal::scalar_pow_op<Derived::Scalar,ScalarExponent>,Derived,Constant<ScalarExponent> >\n  pow(const Eigen::ArrayBase<Derived>& x, const ScalarExponent& exponent);\n#else\n  template<typename Derived,typename ScalarExponent>\n  inline typename internal::enable_if<   !(internal::is_same<typename Derived::Scalar,ScalarExponent>::value) && EIGEN_SCALAR_BINARY_SUPPORTED(pow,typename Derived::Scalar,ScalarExponent),\n          const EIGEN_EXPR_BINARYOP_SCALAR_RETURN_TYPE(Derived,ScalarExponent,pow) >::type\n  pow(const Eigen::ArrayBase<Derived>& x, const ScalarExponent& exponent) {\n    return x.derived().pow(exponent);\n  }\n\n  template<typename Derived>\n  inline const EIGEN_EXPR_BINARYOP_SCALAR_RETURN_TYPE(Derived,typename Derived::Scalar,pow)\n  pow(const Eigen::ArrayBase<Derived>& x, const typename Derived::Scalar& exponent) {\n    return x.derived().pow(exponent);\n  }\n#endif\n\n  /** \\returns an expression of the coefficient-wise power of \\a x to the given array of \\a exponents.\n    *\n    * This function computes the coefficient-wise power.\n    *\n    * Example: \\include Cwise_array_power_array.cpp\n    * Output: \\verbinclude Cwise_array_power_array.out\n    * \n    * \\sa ArrayBase::pow()\n    *\n    * \\relates ArrayBase\n    */\n  template<typename Derived,typename ExponentDerived>\n  inline const Eigen::CwiseBinaryOp<Eigen::internal::scalar_pow_op<typename Derived::Scalar, typename ExponentDerived::Scalar>, const Derived, const ExponentDerived>\n  pow(const Eigen::ArrayBase<Derived>& x, const Eigen::ArrayBase<ExponentDerived>& exponents) \n  {\n    return Eigen::CwiseBinaryOp<Eigen::internal::scalar_pow_op<typename Derived::Scalar, typename ExponentDerived::Scalar>, const Derived, const ExponentDerived>(\n      x.derived(),\n      exponents.derived()\n    );\n  }\n  \n  /** \\returns an expression of the coefficient-wise power of the scalar \\a x to the given array of \\a exponents.\n    *\n    * This function computes the coefficient-wise power between a scalar and an array of exponents.\n    *\n    * \\tparam Scalar is the scalar type of \\a x. It must be compatible with the scalar type of the given array expression (\\c Derived::Scalar).\n    *\n    * Example: \\include Cwise_scalar_power_array.cpp\n    * Output: \\verbinclude Cwise_scalar_power_array.out\n    * \n    * \\sa ArrayBase::pow()\n    *\n    * \\relates ArrayBase\n    */\n#ifdef EIGEN_PARSED_BY_DOXYGEN\n  template<typename Scalar,typename Derived>\n  inline const CwiseBinaryOp<internal::scalar_pow_op<Scalar,Derived::Scalar>,Constant<Scalar>,Derived>\n  pow(const Scalar& x,const Eigen::ArrayBase<Derived>& x);\n#else\n  template<typename Scalar, typename Derived>\n  inline typename internal::enable_if<   !(internal::is_same<typename Derived::Scalar,Scalar>::value) && EIGEN_SCALAR_BINARY_SUPPORTED(pow,Scalar,typename Derived::Scalar),\n          const EIGEN_SCALAR_BINARYOP_EXPR_RETURN_TYPE(Scalar,Derived,pow) >::type\n  pow(const Scalar& x, const Eigen::ArrayBase<Derived>& exponents)\n  {\n    return EIGEN_SCALAR_BINARYOP_EXPR_RETURN_TYPE(Scalar,Derived,pow)(\n            typename internal::plain_constant_type<Derived,Scalar>::type(exponents.rows(), exponents.cols(), x), exponents.derived() );\n  }\n\n  template<typename Derived>\n  inline const EIGEN_SCALAR_BINARYOP_EXPR_RETURN_TYPE(typename Derived::Scalar,Derived,pow)\n  pow(const typename Derived::Scalar& x, const Eigen::ArrayBase<Derived>& exponents)\n  {\n    return EIGEN_SCALAR_BINARYOP_EXPR_RETURN_TYPE(typename Derived::Scalar,Derived,pow)(\n      typename internal::plain_constant_type<Derived,typename Derived::Scalar>::type(exponents.rows(), exponents.cols(), x), exponents.derived() );\n  }\n#endif\n\n\n  namespace internal\n  {\n    EIGEN_ARRAY_DECLARE_GLOBAL_EIGEN_UNARY(real,scalar_real_op)\n    EIGEN_ARRAY_DECLARE_GLOBAL_EIGEN_UNARY(imag,scalar_imag_op)\n    EIGEN_ARRAY_DECLARE_GLOBAL_EIGEN_UNARY(abs2,scalar_abs2_op)\n  }\n}\n\n// TODO: cleanly disable those functions that are not supported on Array (numext::real_ref, internal::random, internal::isApprox...)\n\n#endif // EIGEN_GLOBAL_FUNCTIONS_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/IO.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2006-2008 Benoit Jacob <jacob.benoit.1@gmail.com>\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_IO_H\n#define EIGEN_IO_H\n\nnamespace Eigen { \n\nenum { DontAlignCols = 1 };\nenum { StreamPrecision = -1,\n       FullPrecision = -2 };\n\nnamespace internal {\ntemplate<typename Derived>\nstd::ostream & print_matrix(std::ostream & s, const Derived& _m, const IOFormat& fmt);\n}\n\n/** \\class IOFormat\n  * \\ingroup Core_Module\n  *\n  * \\brief Stores a set of parameters controlling the way matrices are printed\n  *\n  * List of available parameters:\n  *  - \\b precision number of digits for floating point values, or one of the special constants \\c StreamPrecision and \\c FullPrecision.\n  *                 The default is the special value \\c StreamPrecision which means to use the\n  *                 stream's own precision setting, as set for instance using \\c cout.precision(3). The other special value\n  *                 \\c FullPrecision means that the number of digits will be computed to match the full precision of each floating-point\n  *                 type.\n  *  - \\b flags an OR-ed combination of flags, the default value is 0, the only currently available flag is \\c DontAlignCols which\n  *             allows to disable the alignment of columns, resulting in faster code.\n  *  - \\b coeffSeparator string printed between two coefficients of the same row\n  *  - \\b rowSeparator string printed between two rows\n  *  - \\b rowPrefix string printed at the beginning of each row\n  *  - \\b rowSuffix string printed at the end of each row\n  *  - \\b matPrefix string printed at the beginning of the matrix\n  *  - \\b matSuffix string printed at the end of the matrix\n  *\n  * Example: \\include IOFormat.cpp\n  * Output: \\verbinclude IOFormat.out\n  *\n  * \\sa DenseBase::format(), class WithFormat\n  */\nstruct IOFormat\n{\n  /** Default constructor, see class IOFormat for the meaning of the parameters */\n  IOFormat(int _precision = StreamPrecision, int _flags = 0,\n    const std::string& _coeffSeparator = \" \",\n    const std::string& _rowSeparator = \"\\n\", const std::string& _rowPrefix=\"\", const std::string& _rowSuffix=\"\",\n    const std::string& _matPrefix=\"\", const std::string& _matSuffix=\"\")\n  : matPrefix(_matPrefix), matSuffix(_matSuffix), rowPrefix(_rowPrefix), rowSuffix(_rowSuffix), rowSeparator(_rowSeparator),\n    rowSpacer(\"\"), coeffSeparator(_coeffSeparator), precision(_precision), flags(_flags)\n  {\n    // TODO check if rowPrefix, rowSuffix or rowSeparator contains a newline\n    // don't add rowSpacer if columns are not to be aligned\n    if((flags & DontAlignCols))\n      return;\n    int i = int(matSuffix.length())-1;\n    while (i>=0 && matSuffix[i]!='\\n')\n    {\n      rowSpacer += ' ';\n      i--;\n    }\n  }\n  std::string matPrefix, matSuffix;\n  std::string rowPrefix, rowSuffix, rowSeparator, rowSpacer;\n  std::string coeffSeparator;\n  int precision;\n  int flags;\n};\n\n/** \\class WithFormat\n  * \\ingroup Core_Module\n  *\n  * \\brief Pseudo expression providing matrix output with given format\n  *\n  * \\tparam ExpressionType the type of the object on which IO stream operations are performed\n  *\n  * This class represents an expression with stream operators controlled by a given IOFormat.\n  * It is the return type of DenseBase::format()\n  * and most of the time this is the only way it is used.\n  *\n  * See class IOFormat for some examples.\n  *\n  * \\sa DenseBase::format(), class IOFormat\n  */\ntemplate<typename ExpressionType>\nclass WithFormat\n{\n  public:\n\n    WithFormat(const ExpressionType& matrix, const IOFormat& format)\n      : m_matrix(matrix), m_format(format)\n    {}\n\n    friend std::ostream & operator << (std::ostream & s, const WithFormat& wf)\n    {\n      return internal::print_matrix(s, wf.m_matrix.eval(), wf.m_format);\n    }\n\n  protected:\n    const typename ExpressionType::Nested m_matrix;\n    IOFormat m_format;\n};\n\n/** \\returns a WithFormat proxy object allowing to print a matrix the with given\n  * format \\a fmt.\n  *\n  * See class IOFormat for some examples.\n  *\n  * \\sa class IOFormat, class WithFormat\n  */\ntemplate<typename Derived>\ninline const WithFormat<Derived>\nDenseBase<Derived>::format(const IOFormat& fmt) const\n{\n  return WithFormat<Derived>(derived(), fmt);\n}\n\nnamespace internal {\n\n// NOTE: This helper is kept for backward compatibility with previous code specializing\n//       this internal::significant_decimals_impl structure. In the future we should directly\n//       call digits10() which has been introduced in July 2016 in 3.3.\ntemplate<typename Scalar>\nstruct significant_decimals_impl\n{\n  static inline int run()\n  {\n    return NumTraits<Scalar>::digits10();\n  }\n};\n\n/** \\internal\n  * print the matrix \\a _m to the output stream \\a s using the output format \\a fmt */\ntemplate<typename Derived>\nstd::ostream & print_matrix(std::ostream & s, const Derived& _m, const IOFormat& fmt)\n{\n  if(_m.size() == 0)\n  {\n    s << fmt.matPrefix << fmt.matSuffix;\n    return s;\n  }\n  \n  typename Derived::Nested m = _m;\n  typedef typename Derived::Scalar Scalar;\n\n  Index width = 0;\n\n  std::streamsize explicit_precision;\n  if(fmt.precision == StreamPrecision)\n  {\n    explicit_precision = 0;\n  }\n  else if(fmt.precision == FullPrecision)\n  {\n    if (NumTraits<Scalar>::IsInteger)\n    {\n      explicit_precision = 0;\n    }\n    else\n    {\n      explicit_precision = significant_decimals_impl<Scalar>::run();\n    }\n  }\n  else\n  {\n    explicit_precision = fmt.precision;\n  }\n\n  std::streamsize old_precision = 0;\n  if(explicit_precision) old_precision = s.precision(explicit_precision);\n\n  bool align_cols = !(fmt.flags & DontAlignCols);\n  if(align_cols)\n  {\n    // compute the largest width\n    for(Index j = 0; j < m.cols(); ++j)\n      for(Index i = 0; i < m.rows(); ++i)\n      {\n        std::stringstream sstr;\n        sstr.copyfmt(s);\n        sstr << m.coeff(i,j);\n        width = std::max<Index>(width, Index(sstr.str().length()));\n      }\n  }\n  s << fmt.matPrefix;\n  for(Index i = 0; i < m.rows(); ++i)\n  {\n    if (i)\n      s << fmt.rowSpacer;\n    s << fmt.rowPrefix;\n    if(width) s.width(width);\n    s << m.coeff(i, 0);\n    for(Index j = 1; j < m.cols(); ++j)\n    {\n      s << fmt.coeffSeparator;\n      if (width) s.width(width);\n      s << m.coeff(i, j);\n    }\n    s << fmt.rowSuffix;\n    if( i < m.rows() - 1)\n      s << fmt.rowSeparator;\n  }\n  s << fmt.matSuffix;\n  if(explicit_precision) s.precision(old_precision);\n  return s;\n}\n\n} // end namespace internal\n\n/** \\relates DenseBase\n  *\n  * Outputs the matrix, to the given stream.\n  *\n  * If you wish to print the matrix with a format different than the default, use DenseBase::format().\n  *\n  * It is also possible to change the default format by defining EIGEN_DEFAULT_IO_FORMAT before including Eigen headers.\n  * If not defined, this will automatically be defined to Eigen::IOFormat(), that is the Eigen::IOFormat with default parameters.\n  *\n  * \\sa DenseBase::format()\n  */\ntemplate<typename Derived>\nstd::ostream & operator <<\n(std::ostream & s,\n const DenseBase<Derived> & m)\n{\n  return internal::print_matrix(s, m.eval(), EIGEN_DEFAULT_IO_FORMAT);\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_IO_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/Inverse.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2014 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_INVERSE_H\n#define EIGEN_INVERSE_H\n\nnamespace Eigen { \n\ntemplate<typename XprType,typename StorageKind> class InverseImpl;\n\nnamespace internal {\n\ntemplate<typename XprType>\nstruct traits<Inverse<XprType> >\n  : traits<typename XprType::PlainObject>\n{\n  typedef typename XprType::PlainObject PlainObject;\n  typedef traits<PlainObject> BaseTraits;\n  enum {\n    Flags = BaseTraits::Flags & RowMajorBit\n  };\n};\n\n} // end namespace internal\n\n/** \\class Inverse\n  *\n  * \\brief Expression of the inverse of another expression\n  *\n  * \\tparam XprType the type of the expression we are taking the inverse\n  *\n  * This class represents an abstract expression of A.inverse()\n  * and most of the time this is the only way it is used.\n  *\n  */\ntemplate<typename XprType>\nclass Inverse : public InverseImpl<XprType,typename internal::traits<XprType>::StorageKind>\n{\npublic:\n  typedef typename XprType::StorageIndex StorageIndex;\n  typedef typename XprType::PlainObject                       PlainObject;\n  typedef typename internal::ref_selector<XprType>::type      XprTypeNested;\n  typedef typename internal::remove_all<XprTypeNested>::type  XprTypeNestedCleaned;\n  typedef typename internal::ref_selector<Inverse>::type Nested;\n  typedef typename internal::remove_all<XprType>::type NestedExpression;\n  \n  explicit EIGEN_DEVICE_FUNC Inverse(const XprType &xpr)\n    : m_xpr(xpr)\n  {}\n\n  EIGEN_DEVICE_FUNC Index rows() const { return m_xpr.rows(); }\n  EIGEN_DEVICE_FUNC Index cols() const { return m_xpr.cols(); }\n\n  EIGEN_DEVICE_FUNC const XprTypeNestedCleaned& nestedExpression() const { return m_xpr; }\n\nprotected:\n  XprTypeNested m_xpr;\n};\n\n// Generic API dispatcher\ntemplate<typename XprType, typename StorageKind>\nclass InverseImpl\n  : public internal::generic_xpr_base<Inverse<XprType> >::type\n{\npublic:\n  typedef typename internal::generic_xpr_base<Inverse<XprType> >::type Base;\n  typedef typename XprType::Scalar Scalar;\nprivate:\n\n  Scalar coeff(Index row, Index col) const;\n  Scalar coeff(Index i) const;\n};\n\nnamespace internal {\n\n/** \\internal\n  * \\brief Default evaluator for Inverse expression.\n  * \n  * This default evaluator for Inverse expression simply evaluate the inverse into a temporary\n  * by a call to internal::call_assignment_no_alias.\n  * Therefore, inverse implementers only have to specialize Assignment<Dst,Inverse<...>, ...> for\n  * there own nested expression.\n  *\n  * \\sa class Inverse\n  */\ntemplate<typename ArgType>\nstruct unary_evaluator<Inverse<ArgType> >\n  : public evaluator<typename Inverse<ArgType>::PlainObject>\n{\n  typedef Inverse<ArgType> InverseType;\n  typedef typename InverseType::PlainObject PlainObject;\n  typedef evaluator<PlainObject> Base;\n  \n  enum { Flags = Base::Flags | EvalBeforeNestingBit };\n\n  unary_evaluator(const InverseType& inv_xpr)\n    : m_result(inv_xpr.rows(), inv_xpr.cols())\n  {\n    ::new (static_cast<Base*>(this)) Base(m_result);\n    internal::call_assignment_no_alias(m_result, inv_xpr);\n  }\n  \nprotected:\n  PlainObject m_result;\n};\n  \n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_INVERSE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/Map.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2007-2010 Benoit Jacob <jacob.benoit.1@gmail.com>\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_MAP_H\n#define EIGEN_MAP_H\n\nnamespace Eigen { \n\nnamespace internal {\ntemplate<typename PlainObjectType, int MapOptions, typename StrideType>\nstruct traits<Map<PlainObjectType, MapOptions, StrideType> >\n  : public traits<PlainObjectType>\n{\n  typedef traits<PlainObjectType> TraitsBase;\n  enum {\n    InnerStrideAtCompileTime = StrideType::InnerStrideAtCompileTime == 0\n                             ? int(PlainObjectType::InnerStrideAtCompileTime)\n                             : int(StrideType::InnerStrideAtCompileTime),\n    OuterStrideAtCompileTime = StrideType::OuterStrideAtCompileTime == 0\n                             ? int(PlainObjectType::OuterStrideAtCompileTime)\n                             : int(StrideType::OuterStrideAtCompileTime),\n    Alignment = int(MapOptions)&int(AlignedMask),\n    Flags0 = TraitsBase::Flags & (~NestByRefBit),\n    Flags = is_lvalue<PlainObjectType>::value ? int(Flags0) : (int(Flags0) & ~LvalueBit)\n  };\nprivate:\n  enum { Options }; // Expressions don't have Options\n};\n}\n\n/** \\class Map\n  * \\ingroup Core_Module\n  *\n  * \\brief A matrix or vector expression mapping an existing array of data.\n  *\n  * \\tparam PlainObjectType the equivalent matrix type of the mapped data\n  * \\tparam MapOptions specifies the pointer alignment in bytes. It can be: \\c #Aligned128, , \\c #Aligned64, \\c #Aligned32, \\c #Aligned16, \\c #Aligned8 or \\c #Unaligned.\n  *                The default is \\c #Unaligned.\n  * \\tparam StrideType optionally specifies strides. By default, Map assumes the memory layout\n  *                   of an ordinary, contiguous array. This can be overridden by specifying strides.\n  *                   The type passed here must be a specialization of the Stride template, see examples below.\n  *\n  * This class represents a matrix or vector expression mapping an existing array of data.\n  * It can be used to let Eigen interface without any overhead with non-Eigen data structures,\n  * such as plain C arrays or structures from other libraries. By default, it assumes that the\n  * data is laid out contiguously in memory. You can however override this by explicitly specifying\n  * inner and outer strides.\n  *\n  * Here's an example of simply mapping a contiguous array as a \\ref TopicStorageOrders \"column-major\" matrix:\n  * \\include Map_simple.cpp\n  * Output: \\verbinclude Map_simple.out\n  *\n  * If you need to map non-contiguous arrays, you can do so by specifying strides:\n  *\n  * Here's an example of mapping an array as a vector, specifying an inner stride, that is, the pointer\n  * increment between two consecutive coefficients. Here, we're specifying the inner stride as a compile-time\n  * fixed value.\n  * \\include Map_inner_stride.cpp\n  * Output: \\verbinclude Map_inner_stride.out\n  *\n  * Here's an example of mapping an array while specifying an outer stride. Here, since we're mapping\n  * as a column-major matrix, 'outer stride' means the pointer increment between two consecutive columns.\n  * Here, we're specifying the outer stride as a runtime parameter. Note that here \\c OuterStride<> is\n  * a short version of \\c OuterStride<Dynamic> because the default template parameter of OuterStride\n  * is  \\c Dynamic\n  * \\include Map_outer_stride.cpp\n  * Output: \\verbinclude Map_outer_stride.out\n  *\n  * For more details and for an example of specifying both an inner and an outer stride, see class Stride.\n  *\n  * \\b Tip: to change the array of data mapped by a Map object, you can use the C++\n  * placement new syntax:\n  *\n  * Example: \\include Map_placement_new.cpp\n  * Output: \\verbinclude Map_placement_new.out\n  *\n  * This class is the return type of PlainObjectBase::Map() but can also be used directly.\n  *\n  * \\sa PlainObjectBase::Map(), \\ref TopicStorageOrders\n  */\ntemplate<typename PlainObjectType, int MapOptions, typename StrideType> class Map\n  : public MapBase<Map<PlainObjectType, MapOptions, StrideType> >\n{\n  public:\n\n    typedef MapBase<Map> Base;\n    EIGEN_DENSE_PUBLIC_INTERFACE(Map)\n\n    typedef typename Base::PointerType PointerType;\n    typedef PointerType PointerArgType;\n    EIGEN_DEVICE_FUNC\n    inline PointerType cast_to_pointer_type(PointerArgType ptr) { return ptr; }\n\n    EIGEN_DEVICE_FUNC\n    inline Index innerStride() const\n    {\n      return StrideType::InnerStrideAtCompileTime != 0 ? m_stride.inner() : 1;\n    }\n\n    EIGEN_DEVICE_FUNC\n    inline Index outerStride() const\n    {\n      return StrideType::OuterStrideAtCompileTime != 0 ? m_stride.outer()\n           : IsVectorAtCompileTime ? this->size()\n           : int(Flags)&RowMajorBit ? this->cols()\n           : this->rows();\n    }\n\n    /** Constructor in the fixed-size case.\n      *\n      * \\param dataPtr pointer to the array to map\n      * \\param stride optional Stride object, passing the strides.\n      */\n    EIGEN_DEVICE_FUNC\n    explicit inline Map(PointerArgType dataPtr, const StrideType& stride = StrideType())\n      : Base(cast_to_pointer_type(dataPtr)), m_stride(stride)\n    {\n      PlainObjectType::Base::_check_template_params();\n    }\n\n    /** Constructor in the dynamic-size vector case.\n      *\n      * \\param dataPtr pointer to the array to map\n      * \\param size the size of the vector expression\n      * \\param stride optional Stride object, passing the strides.\n      */\n    EIGEN_DEVICE_FUNC\n    inline Map(PointerArgType dataPtr, Index size, const StrideType& stride = StrideType())\n      : Base(cast_to_pointer_type(dataPtr), size), m_stride(stride)\n    {\n      PlainObjectType::Base::_check_template_params();\n    }\n\n    /** Constructor in the dynamic-size matrix case.\n      *\n      * \\param dataPtr pointer to the array to map\n      * \\param rows the number of rows of the matrix expression\n      * \\param cols the number of columns of the matrix expression\n      * \\param stride optional Stride object, passing the strides.\n      */\n    EIGEN_DEVICE_FUNC\n    inline Map(PointerArgType dataPtr, Index rows, Index cols, const StrideType& stride = StrideType())\n      : Base(cast_to_pointer_type(dataPtr), rows, cols), m_stride(stride)\n    {\n      PlainObjectType::Base::_check_template_params();\n    }\n\n    EIGEN_INHERIT_ASSIGNMENT_OPERATORS(Map)\n\n  protected:\n    StrideType m_stride;\n};\n\n\n} // end namespace Eigen\n\n#endif // EIGEN_MAP_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/MapBase.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2007-2010 Benoit Jacob <jacob.benoit.1@gmail.com>\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_MAPBASE_H\n#define EIGEN_MAPBASE_H\n\n#define EIGEN_STATIC_ASSERT_INDEX_BASED_ACCESS(Derived) \\\n      EIGEN_STATIC_ASSERT((int(internal::evaluator<Derived>::Flags) & LinearAccessBit) || Derived::IsVectorAtCompileTime, \\\n                          YOU_ARE_TRYING_TO_USE_AN_INDEX_BASED_ACCESSOR_ON_AN_EXPRESSION_THAT_DOES_NOT_SUPPORT_THAT)\n\nnamespace Eigen { \n\n/** \\ingroup Core_Module\n  *\n  * \\brief Base class for dense Map and Block expression with direct access\n  *\n  * This base class provides the const low-level accessors (e.g. coeff, coeffRef) of dense\n  * Map and Block objects with direct access.\n  * Typical users do not have to directly deal with this class.\n  *\n  * This class can be extended by through the macro plugin \\c EIGEN_MAPBASE_PLUGIN.\n  * See \\link TopicCustomizing_Plugins customizing Eigen \\endlink for details.\n  *\n  * The \\c Derived class has to provide the following two methods describing the memory layout:\n  *  \\code Index innerStride() const; \\endcode\n  *  \\code Index outerStride() const; \\endcode\n  *\n  * \\sa class Map, class Block\n  */\ntemplate<typename Derived> class MapBase<Derived, ReadOnlyAccessors>\n  : public internal::dense_xpr_base<Derived>::type\n{\n  public:\n\n    typedef typename internal::dense_xpr_base<Derived>::type Base;\n    enum {\n      RowsAtCompileTime = internal::traits<Derived>::RowsAtCompileTime,\n      ColsAtCompileTime = internal::traits<Derived>::ColsAtCompileTime,\n      SizeAtCompileTime = Base::SizeAtCompileTime\n    };\n\n    typedef typename internal::traits<Derived>::StorageKind StorageKind;\n    typedef typename internal::traits<Derived>::Scalar Scalar;\n    typedef typename internal::packet_traits<Scalar>::type PacketScalar;\n    typedef typename NumTraits<Scalar>::Real RealScalar;\n    typedef typename internal::conditional<\n                         bool(internal::is_lvalue<Derived>::value),\n                         Scalar *,\n                         const Scalar *>::type\n                     PointerType;\n\n    using Base::derived;\n//    using Base::RowsAtCompileTime;\n//    using Base::ColsAtCompileTime;\n//    using Base::SizeAtCompileTime;\n    using Base::MaxRowsAtCompileTime;\n    using Base::MaxColsAtCompileTime;\n    using Base::MaxSizeAtCompileTime;\n    using Base::IsVectorAtCompileTime;\n    using Base::Flags;\n    using Base::IsRowMajor;\n\n    using Base::rows;\n    using Base::cols;\n    using Base::size;\n    using Base::coeff;\n    using Base::coeffRef;\n    using Base::lazyAssign;\n    using Base::eval;\n\n    using Base::innerStride;\n    using Base::outerStride;\n    using Base::rowStride;\n    using Base::colStride;\n\n    // bug 217 - compile error on ICC 11.1\n    using Base::operator=;\n\n    typedef typename Base::CoeffReturnType CoeffReturnType;\n\n    /** \\copydoc DenseBase::rows() */\n    EIGEN_DEVICE_FUNC inline Index rows() const { return m_rows.value(); }\n    /** \\copydoc DenseBase::cols() */\n    EIGEN_DEVICE_FUNC inline Index cols() const { return m_cols.value(); }\n\n    /** Returns a pointer to the first coefficient of the matrix or vector.\n      *\n      * \\note When addressing this data, make sure to honor the strides returned by innerStride() and outerStride().\n      *\n      * \\sa innerStride(), outerStride()\n      */\n    EIGEN_DEVICE_FUNC inline const Scalar* data() const { return m_data; }\n\n    /** \\copydoc PlainObjectBase::coeff(Index,Index) const */\n    EIGEN_DEVICE_FUNC\n    inline const Scalar& coeff(Index rowId, Index colId) const\n    {\n      return m_data[colId * colStride() + rowId * rowStride()];\n    }\n\n    /** \\copydoc PlainObjectBase::coeff(Index) const */\n    EIGEN_DEVICE_FUNC\n    inline const Scalar& coeff(Index index) const\n    {\n      EIGEN_STATIC_ASSERT_INDEX_BASED_ACCESS(Derived)\n      return m_data[index * innerStride()];\n    }\n\n    /** \\copydoc PlainObjectBase::coeffRef(Index,Index) const */\n    EIGEN_DEVICE_FUNC\n    inline const Scalar& coeffRef(Index rowId, Index colId) const\n    {\n      return this->m_data[colId * colStride() + rowId * rowStride()];\n    }\n\n    /** \\copydoc PlainObjectBase::coeffRef(Index) const */\n    EIGEN_DEVICE_FUNC\n    inline const Scalar& coeffRef(Index index) const\n    {\n      EIGEN_STATIC_ASSERT_INDEX_BASED_ACCESS(Derived)\n      return this->m_data[index * innerStride()];\n    }\n\n    /** \\internal */\n    template<int LoadMode>\n    inline PacketScalar packet(Index rowId, Index colId) const\n    {\n      return internal::ploadt<PacketScalar, LoadMode>\n               (m_data + (colId * colStride() + rowId * rowStride()));\n    }\n\n    /** \\internal */\n    template<int LoadMode>\n    inline PacketScalar packet(Index index) const\n    {\n      EIGEN_STATIC_ASSERT_INDEX_BASED_ACCESS(Derived)\n      return internal::ploadt<PacketScalar, LoadMode>(m_data + index * innerStride());\n    }\n\n    /** \\internal Constructor for fixed size matrices or vectors */\n    EIGEN_DEVICE_FUNC\n    explicit inline MapBase(PointerType dataPtr) : m_data(dataPtr), m_rows(RowsAtCompileTime), m_cols(ColsAtCompileTime)\n    {\n      EIGEN_STATIC_ASSERT_FIXED_SIZE(Derived)\n      checkSanity<Derived>();\n    }\n\n    /** \\internal Constructor for dynamically sized vectors */\n    EIGEN_DEVICE_FUNC\n    inline MapBase(PointerType dataPtr, Index vecSize)\n            : m_data(dataPtr),\n              m_rows(RowsAtCompileTime == Dynamic ? vecSize : Index(RowsAtCompileTime)),\n              m_cols(ColsAtCompileTime == Dynamic ? vecSize : Index(ColsAtCompileTime))\n    {\n      EIGEN_STATIC_ASSERT_VECTOR_ONLY(Derived)\n      eigen_assert(vecSize >= 0);\n      eigen_assert(dataPtr == 0 || SizeAtCompileTime == Dynamic || SizeAtCompileTime == vecSize);\n      checkSanity<Derived>();\n    }\n\n    /** \\internal Constructor for dynamically sized matrices */\n    EIGEN_DEVICE_FUNC\n    inline MapBase(PointerType dataPtr, Index rows, Index cols)\n            : m_data(dataPtr), m_rows(rows), m_cols(cols)\n    {\n      eigen_assert( (dataPtr == 0)\n              || (   rows >= 0 && (RowsAtCompileTime == Dynamic || RowsAtCompileTime == rows)\n                  && cols >= 0 && (ColsAtCompileTime == Dynamic || ColsAtCompileTime == cols)));\n      checkSanity<Derived>();\n    }\n\n    #ifdef EIGEN_MAPBASE_PLUGIN\n    #include EIGEN_MAPBASE_PLUGIN\n    #endif\n\n  protected:\n\n    template<typename T>\n    EIGEN_DEVICE_FUNC\n    void checkSanity(typename internal::enable_if<(internal::traits<T>::Alignment>0),void*>::type = 0) const\n    {\n#if EIGEN_MAX_ALIGN_BYTES>0\n      eigen_assert((   ((internal::UIntPtr(m_data) % internal::traits<Derived>::Alignment) == 0)\n                    || (cols() * rows() * innerStride() * sizeof(Scalar)) < internal::traits<Derived>::Alignment ) && \"data is not aligned\");\n#endif\n    }\n\n    template<typename T>\n    EIGEN_DEVICE_FUNC\n    void checkSanity(typename internal::enable_if<internal::traits<T>::Alignment==0,void*>::type = 0) const\n    {}\n\n    PointerType m_data;\n    const internal::variable_if_dynamic<Index, RowsAtCompileTime> m_rows;\n    const internal::variable_if_dynamic<Index, ColsAtCompileTime> m_cols;\n};\n\n/** \\ingroup Core_Module\n  *\n  * \\brief Base class for non-const dense Map and Block expression with direct access\n  *\n  * This base class provides the non-const low-level accessors (e.g. coeff and coeffRef) of\n  * dense Map and Block objects with direct access.\n  * It inherits MapBase<Derived, ReadOnlyAccessors> which defines the const variant for reading specific entries.\n  *\n  * \\sa class Map, class Block\n  */\ntemplate<typename Derived> class MapBase<Derived, WriteAccessors>\n  : public MapBase<Derived, ReadOnlyAccessors>\n{\n    typedef MapBase<Derived, ReadOnlyAccessors> ReadOnlyMapBase;\n  public:\n\n    typedef MapBase<Derived, ReadOnlyAccessors> Base;\n\n    typedef typename Base::Scalar Scalar;\n    typedef typename Base::PacketScalar PacketScalar;\n    typedef typename Base::StorageIndex StorageIndex;\n    typedef typename Base::PointerType PointerType;\n\n    using Base::derived;\n    using Base::rows;\n    using Base::cols;\n    using Base::size;\n    using Base::coeff;\n    using Base::coeffRef;\n\n    using Base::innerStride;\n    using Base::outerStride;\n    using Base::rowStride;\n    using Base::colStride;\n\n    typedef typename internal::conditional<\n                    internal::is_lvalue<Derived>::value,\n                    Scalar,\n                    const Scalar\n                  >::type ScalarWithConstIfNotLvalue;\n\n    EIGEN_DEVICE_FUNC\n    inline const Scalar* data() const { return this->m_data; }\n    EIGEN_DEVICE_FUNC\n    inline ScalarWithConstIfNotLvalue* data() { return this->m_data; } // no const-cast here so non-const-correct code will give a compile error\n\n    EIGEN_DEVICE_FUNC\n    inline ScalarWithConstIfNotLvalue& coeffRef(Index row, Index col)\n    {\n      return this->m_data[col * colStride() + row * rowStride()];\n    }\n\n    EIGEN_DEVICE_FUNC\n    inline ScalarWithConstIfNotLvalue& coeffRef(Index index)\n    {\n      EIGEN_STATIC_ASSERT_INDEX_BASED_ACCESS(Derived)\n      return this->m_data[index * innerStride()];\n    }\n\n    template<int StoreMode>\n    inline void writePacket(Index row, Index col, const PacketScalar& val)\n    {\n      internal::pstoret<Scalar, PacketScalar, StoreMode>\n               (this->m_data + (col * colStride() + row * rowStride()), val);\n    }\n\n    template<int StoreMode>\n    inline void writePacket(Index index, const PacketScalar& val)\n    {\n      EIGEN_STATIC_ASSERT_INDEX_BASED_ACCESS(Derived)\n      internal::pstoret<Scalar, PacketScalar, StoreMode>\n                (this->m_data + index * innerStride(), val);\n    }\n\n    EIGEN_DEVICE_FUNC explicit inline MapBase(PointerType dataPtr) : Base(dataPtr) {}\n    EIGEN_DEVICE_FUNC inline MapBase(PointerType dataPtr, Index vecSize) : Base(dataPtr, vecSize) {}\n    EIGEN_DEVICE_FUNC inline MapBase(PointerType dataPtr, Index rows, Index cols) : Base(dataPtr, rows, cols) {}\n\n    EIGEN_DEVICE_FUNC\n    Derived& operator=(const MapBase& other)\n    {\n      ReadOnlyMapBase::Base::operator=(other);\n      return derived();\n    }\n\n    // In theory we could simply refer to Base:Base::operator=, but MSVC does not like Base::Base,\n    // see bugs 821 and 920.\n    using ReadOnlyMapBase::Base::operator=;\n};\n\n#undef EIGEN_STATIC_ASSERT_INDEX_BASED_ACCESS\n\n} // end namespace Eigen\n\n#endif // EIGEN_MAPBASE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/MathFunctions.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2006-2010 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_MATHFUNCTIONS_H\n#define EIGEN_MATHFUNCTIONS_H\n\n// source: http://www.geom.uiuc.edu/~huberty/math5337/groupe/digits.html\n// TODO this should better be moved to NumTraits\n#define EIGEN_PI 3.141592653589793238462643383279502884197169399375105820974944592307816406L\n\n\nnamespace Eigen {\n\n// On WINCE, std::abs is defined for int only, so let's defined our own overloads:\n// This issue has been confirmed with MSVC 2008 only, but the issue might exist for more recent versions too.\n#if EIGEN_OS_WINCE && EIGEN_COMP_MSVC && EIGEN_COMP_MSVC<=1500\nlong        abs(long        x) { return (labs(x));  }\ndouble      abs(double      x) { return (fabs(x));  }\nfloat       abs(float       x) { return (fabsf(x)); }\nlong double abs(long double x) { return (fabsl(x)); }\n#endif\n\nnamespace internal {\n\n/** \\internal \\class global_math_functions_filtering_base\n  *\n  * What it does:\n  * Defines a typedef 'type' as follows:\n  * - if type T has a member typedef Eigen_BaseClassForSpecializationOfGlobalMathFuncImpl, then\n  *   global_math_functions_filtering_base<T>::type is a typedef for it.\n  * - otherwise, global_math_functions_filtering_base<T>::type is a typedef for T.\n  *\n  * How it's used:\n  * To allow to defined the global math functions (like sin...) in certain cases, like the Array expressions.\n  * When you do sin(array1+array2), the object array1+array2 has a complicated expression type, all what you want to know\n  * is that it inherits ArrayBase. So we implement a partial specialization of sin_impl for ArrayBase<Derived>.\n  * So we must make sure to use sin_impl<ArrayBase<Derived> > and not sin_impl<Derived>, otherwise our partial specialization\n  * won't be used. How does sin know that? That's exactly what global_math_functions_filtering_base tells it.\n  *\n  * How it's implemented:\n  * SFINAE in the style of enable_if. Highly susceptible of breaking compilers. With GCC, it sure does work, but if you replace\n  * the typename dummy by an integer template parameter, it doesn't work anymore!\n  */\n\ntemplate<typename T, typename dummy = void>\nstruct global_math_functions_filtering_base\n{\n  typedef T type;\n};\n\ntemplate<typename T> struct always_void { typedef void type; };\n\ntemplate<typename T>\nstruct global_math_functions_filtering_base\n  <T,\n   typename always_void<typename T::Eigen_BaseClassForSpecializationOfGlobalMathFuncImpl>::type\n  >\n{\n  typedef typename T::Eigen_BaseClassForSpecializationOfGlobalMathFuncImpl type;\n};\n\n#define EIGEN_MATHFUNC_IMPL(func, scalar) Eigen::internal::func##_impl<typename Eigen::internal::global_math_functions_filtering_base<scalar>::type>\n#define EIGEN_MATHFUNC_RETVAL(func, scalar) typename Eigen::internal::func##_retval<typename Eigen::internal::global_math_functions_filtering_base<scalar>::type>::type\n\n/****************************************************************************\n* Implementation of real                                                 *\n****************************************************************************/\n\ntemplate<typename Scalar, bool IsComplex = NumTraits<Scalar>::IsComplex>\nstruct real_default_impl\n{\n  typedef typename NumTraits<Scalar>::Real RealScalar;\n  EIGEN_DEVICE_FUNC\n  static inline RealScalar run(const Scalar& x)\n  {\n    return x;\n  }\n};\n\ntemplate<typename Scalar>\nstruct real_default_impl<Scalar,true>\n{\n  typedef typename NumTraits<Scalar>::Real RealScalar;\n  EIGEN_DEVICE_FUNC\n  static inline RealScalar run(const Scalar& x)\n  {\n    using std::real;\n    return real(x);\n  }\n};\n\ntemplate<typename Scalar> struct real_impl : real_default_impl<Scalar> {};\n\n#ifdef __CUDA_ARCH__\ntemplate<typename T>\nstruct real_impl<std::complex<T> >\n{\n  typedef T RealScalar;\n  EIGEN_DEVICE_FUNC\n  static inline T run(const std::complex<T>& x)\n  {\n    return x.real();\n  }\n};\n#endif\n\ntemplate<typename Scalar>\nstruct real_retval\n{\n  typedef typename NumTraits<Scalar>::Real type;\n};\n\n/****************************************************************************\n* Implementation of imag                                                 *\n****************************************************************************/\n\ntemplate<typename Scalar, bool IsComplex = NumTraits<Scalar>::IsComplex>\nstruct imag_default_impl\n{\n  typedef typename NumTraits<Scalar>::Real RealScalar;\n  EIGEN_DEVICE_FUNC\n  static inline RealScalar run(const Scalar&)\n  {\n    return RealScalar(0);\n  }\n};\n\ntemplate<typename Scalar>\nstruct imag_default_impl<Scalar,true>\n{\n  typedef typename NumTraits<Scalar>::Real RealScalar;\n  EIGEN_DEVICE_FUNC\n  static inline RealScalar run(const Scalar& x)\n  {\n    using std::imag;\n    return imag(x);\n  }\n};\n\ntemplate<typename Scalar> struct imag_impl : imag_default_impl<Scalar> {};\n\n#ifdef __CUDA_ARCH__\ntemplate<typename T>\nstruct imag_impl<std::complex<T> >\n{\n  typedef T RealScalar;\n  EIGEN_DEVICE_FUNC\n  static inline T run(const std::complex<T>& x)\n  {\n    return x.imag();\n  }\n};\n#endif\n\ntemplate<typename Scalar>\nstruct imag_retval\n{\n  typedef typename NumTraits<Scalar>::Real type;\n};\n\n/****************************************************************************\n* Implementation of real_ref                                             *\n****************************************************************************/\n\ntemplate<typename Scalar>\nstruct real_ref_impl\n{\n  typedef typename NumTraits<Scalar>::Real RealScalar;\n  EIGEN_DEVICE_FUNC\n  static inline RealScalar& run(Scalar& x)\n  {\n    return reinterpret_cast<RealScalar*>(&x)[0];\n  }\n  EIGEN_DEVICE_FUNC\n  static inline const RealScalar& run(const Scalar& x)\n  {\n    return reinterpret_cast<const RealScalar*>(&x)[0];\n  }\n};\n\ntemplate<typename Scalar>\nstruct real_ref_retval\n{\n  typedef typename NumTraits<Scalar>::Real & type;\n};\n\n/****************************************************************************\n* Implementation of imag_ref                                             *\n****************************************************************************/\n\ntemplate<typename Scalar, bool IsComplex>\nstruct imag_ref_default_impl\n{\n  typedef typename NumTraits<Scalar>::Real RealScalar;\n  EIGEN_DEVICE_FUNC\n  static inline RealScalar& run(Scalar& x)\n  {\n    return reinterpret_cast<RealScalar*>(&x)[1];\n  }\n  EIGEN_DEVICE_FUNC\n  static inline const RealScalar& run(const Scalar& x)\n  {\n    return reinterpret_cast<RealScalar*>(&x)[1];\n  }\n};\n\ntemplate<typename Scalar>\nstruct imag_ref_default_impl<Scalar, false>\n{\n  EIGEN_DEVICE_FUNC\n  static inline Scalar run(Scalar&)\n  {\n    return Scalar(0);\n  }\n  EIGEN_DEVICE_FUNC\n  static inline const Scalar run(const Scalar&)\n  {\n    return Scalar(0);\n  }\n};\n\ntemplate<typename Scalar>\nstruct imag_ref_impl : imag_ref_default_impl<Scalar, NumTraits<Scalar>::IsComplex> {};\n\ntemplate<typename Scalar>\nstruct imag_ref_retval\n{\n  typedef typename NumTraits<Scalar>::Real & type;\n};\n\n/****************************************************************************\n* Implementation of conj                                                 *\n****************************************************************************/\n\ntemplate<typename Scalar, bool IsComplex = NumTraits<Scalar>::IsComplex>\nstruct conj_impl\n{\n  EIGEN_DEVICE_FUNC\n  static inline Scalar run(const Scalar& x)\n  {\n    return x;\n  }\n};\n\ntemplate<typename Scalar>\nstruct conj_impl<Scalar,true>\n{\n  EIGEN_DEVICE_FUNC\n  static inline Scalar run(const Scalar& x)\n  {\n    using std::conj;\n    return conj(x);\n  }\n};\n\ntemplate<typename Scalar>\nstruct conj_retval\n{\n  typedef Scalar type;\n};\n\n/****************************************************************************\n* Implementation of abs2                                                 *\n****************************************************************************/\n\ntemplate<typename Scalar,bool IsComplex>\nstruct abs2_impl_default\n{\n  typedef typename NumTraits<Scalar>::Real RealScalar;\n  EIGEN_DEVICE_FUNC\n  static inline RealScalar run(const Scalar& x)\n  {\n    return x*x;\n  }\n};\n\ntemplate<typename Scalar>\nstruct abs2_impl_default<Scalar, true> // IsComplex\n{\n  typedef typename NumTraits<Scalar>::Real RealScalar;\n  EIGEN_DEVICE_FUNC\n  static inline RealScalar run(const Scalar& x)\n  {\n    return real(x)*real(x) + imag(x)*imag(x);\n  }\n};\n\ntemplate<typename Scalar>\nstruct abs2_impl\n{\n  typedef typename NumTraits<Scalar>::Real RealScalar;\n  EIGEN_DEVICE_FUNC\n  static inline RealScalar run(const Scalar& x)\n  {\n    return abs2_impl_default<Scalar,NumTraits<Scalar>::IsComplex>::run(x);\n  }\n};\n\ntemplate<typename Scalar>\nstruct abs2_retval\n{\n  typedef typename NumTraits<Scalar>::Real type;\n};\n\n/****************************************************************************\n* Implementation of norm1                                                *\n****************************************************************************/\n\ntemplate<typename Scalar, bool IsComplex>\nstruct norm1_default_impl\n{\n  typedef typename NumTraits<Scalar>::Real RealScalar;\n  EIGEN_DEVICE_FUNC\n  static inline RealScalar run(const Scalar& x)\n  {\n    EIGEN_USING_STD_MATH(abs);\n    return abs(real(x)) + abs(imag(x));\n  }\n};\n\ntemplate<typename Scalar>\nstruct norm1_default_impl<Scalar, false>\n{\n  EIGEN_DEVICE_FUNC\n  static inline Scalar run(const Scalar& x)\n  {\n    EIGEN_USING_STD_MATH(abs);\n    return abs(x);\n  }\n};\n\ntemplate<typename Scalar>\nstruct norm1_impl : norm1_default_impl<Scalar, NumTraits<Scalar>::IsComplex> {};\n\ntemplate<typename Scalar>\nstruct norm1_retval\n{\n  typedef typename NumTraits<Scalar>::Real type;\n};\n\n/****************************************************************************\n* Implementation of hypot                                                *\n****************************************************************************/\n\ntemplate<typename Scalar>\nstruct hypot_impl\n{\n  typedef typename NumTraits<Scalar>::Real RealScalar;\n  static inline RealScalar run(const Scalar& x, const Scalar& y)\n  {\n    EIGEN_USING_STD_MATH(abs);\n    EIGEN_USING_STD_MATH(sqrt);\n    RealScalar _x = abs(x);\n    RealScalar _y = abs(y);\n    Scalar p, qp;\n    if(_x>_y)\n    {\n      p = _x;\n      qp = _y / p;\n    }\n    else\n    {\n      p = _y;\n      qp = _x / p;\n    }\n    if(p==RealScalar(0)) return RealScalar(0);\n    return p * sqrt(RealScalar(1) + qp*qp);\n  }\n};\n\ntemplate<typename Scalar>\nstruct hypot_retval\n{\n  typedef typename NumTraits<Scalar>::Real type;\n};\n\n/****************************************************************************\n* Implementation of cast                                                 *\n****************************************************************************/\n\ntemplate<typename OldType, typename NewType>\nstruct cast_impl\n{\n  EIGEN_DEVICE_FUNC\n  static inline NewType run(const OldType& x)\n  {\n    return static_cast<NewType>(x);\n  }\n};\n\n// here, for once, we're plainly returning NewType: we don't want cast to do weird things.\n\ntemplate<typename OldType, typename NewType>\nEIGEN_DEVICE_FUNC\ninline NewType cast(const OldType& x)\n{\n  return cast_impl<OldType, NewType>::run(x);\n}\n\n/****************************************************************************\n* Implementation of round                                                   *\n****************************************************************************/\n\n#if EIGEN_HAS_CXX11_MATH\n  template<typename Scalar>\n  struct round_impl {\n    static inline Scalar run(const Scalar& x)\n    {\n      EIGEN_STATIC_ASSERT((!NumTraits<Scalar>::IsComplex), NUMERIC_TYPE_MUST_BE_REAL)\n      using std::round;\n      return round(x);\n    }\n  };\n#else\n  template<typename Scalar>\n  struct round_impl\n  {\n    static inline Scalar run(const Scalar& x)\n    {\n      EIGEN_STATIC_ASSERT((!NumTraits<Scalar>::IsComplex), NUMERIC_TYPE_MUST_BE_REAL)\n      EIGEN_USING_STD_MATH(floor);\n      EIGEN_USING_STD_MATH(ceil);\n      return (x > Scalar(0)) ? floor(x + Scalar(0.5)) : ceil(x - Scalar(0.5));\n    }\n  };\n#endif\n\ntemplate<typename Scalar>\nstruct round_retval\n{\n  typedef Scalar type;\n};\n\n/****************************************************************************\n* Implementation of arg                                                     *\n****************************************************************************/\n\n#if EIGEN_HAS_CXX11_MATH\n  template<typename Scalar>\n  struct arg_impl {\n    static inline Scalar run(const Scalar& x)\n    {\n      EIGEN_USING_STD_MATH(arg);\n      return arg(x);\n    }\n  };\n#else\n  template<typename Scalar, bool IsComplex = NumTraits<Scalar>::IsComplex>\n  struct arg_default_impl\n  {\n    typedef typename NumTraits<Scalar>::Real RealScalar;\n    EIGEN_DEVICE_FUNC\n    static inline RealScalar run(const Scalar& x)\n    {\n      return (x < Scalar(0)) ? Scalar(EIGEN_PI) : Scalar(0); }\n  };\n\n  template<typename Scalar>\n  struct arg_default_impl<Scalar,true>\n  {\n    typedef typename NumTraits<Scalar>::Real RealScalar;\n    EIGEN_DEVICE_FUNC\n    static inline RealScalar run(const Scalar& x)\n    {\n      EIGEN_USING_STD_MATH(arg);\n      return arg(x);\n    }\n  };\n\n  template<typename Scalar> struct arg_impl : arg_default_impl<Scalar> {};\n#endif\n\ntemplate<typename Scalar>\nstruct arg_retval\n{\n  typedef typename NumTraits<Scalar>::Real type;\n};\n\n/****************************************************************************\n* Implementation of log1p                                                   *\n****************************************************************************/\n\nnamespace std_fallback {\n  // fallback log1p implementation in case there is no log1p(Scalar) function in namespace of Scalar,\n  // or that there is no suitable std::log1p function available\n  template<typename Scalar>\n  EIGEN_DEVICE_FUNC inline Scalar log1p(const Scalar& x) {\n    EIGEN_STATIC_ASSERT_NON_INTEGER(Scalar)\n    typedef typename NumTraits<Scalar>::Real RealScalar;\n    EIGEN_USING_STD_MATH(log);\n    Scalar x1p = RealScalar(1) + x;\n    return ( x1p == Scalar(1) ) ? x : x * ( log(x1p) / (x1p - RealScalar(1)) );\n  }\n}\n\ntemplate<typename Scalar>\nstruct log1p_impl {\n  static inline Scalar run(const Scalar& x)\n  {\n    EIGEN_STATIC_ASSERT_NON_INTEGER(Scalar)\n    #if EIGEN_HAS_CXX11_MATH\n    using std::log1p;\n    #endif\n    using std_fallback::log1p;\n    return log1p(x);\n  }\n};\n\n\ntemplate<typename Scalar>\nstruct log1p_retval\n{\n  typedef Scalar type;\n};\n\n/****************************************************************************\n* Implementation of pow                                                  *\n****************************************************************************/\n\ntemplate<typename ScalarX,typename ScalarY, bool IsInteger = NumTraits<ScalarX>::IsInteger&&NumTraits<ScalarY>::IsInteger>\nstruct pow_impl\n{\n  //typedef Scalar retval;\n  typedef typename ScalarBinaryOpTraits<ScalarX,ScalarY,internal::scalar_pow_op<ScalarX,ScalarY> >::ReturnType result_type;\n  static EIGEN_DEVICE_FUNC inline result_type run(const ScalarX& x, const ScalarY& y)\n  {\n    EIGEN_USING_STD_MATH(pow);\n    return pow(x, y);\n  }\n};\n\ntemplate<typename ScalarX,typename ScalarY>\nstruct pow_impl<ScalarX,ScalarY, true>\n{\n  typedef ScalarX result_type;\n  static EIGEN_DEVICE_FUNC inline ScalarX run(ScalarX x, ScalarY y)\n  {\n    ScalarX res(1);\n    eigen_assert(!NumTraits<ScalarY>::IsSigned || y >= 0);\n    if(y & 1) res *= x;\n    y >>= 1;\n    while(y)\n    {\n      x *= x;\n      if(y&1) res *= x;\n      y >>= 1;\n    }\n    return res;\n  }\n};\n\n/****************************************************************************\n* Implementation of random                                               *\n****************************************************************************/\n\ntemplate<typename Scalar,\n         bool IsComplex,\n         bool IsInteger>\nstruct random_default_impl {};\n\ntemplate<typename Scalar>\nstruct random_impl : random_default_impl<Scalar, NumTraits<Scalar>::IsComplex, NumTraits<Scalar>::IsInteger> {};\n\ntemplate<typename Scalar>\nstruct random_retval\n{\n  typedef Scalar type;\n};\n\ntemplate<typename Scalar> inline EIGEN_MATHFUNC_RETVAL(random, Scalar) random(const Scalar& x, const Scalar& y);\ntemplate<typename Scalar> inline EIGEN_MATHFUNC_RETVAL(random, Scalar) random();\n\ntemplate<typename Scalar>\nstruct random_default_impl<Scalar, false, false>\n{\n  static inline Scalar run(const Scalar& x, const Scalar& y)\n  {\n    return x + (y-x) * Scalar(std::rand()) / Scalar(RAND_MAX);\n  }\n  static inline Scalar run()\n  {\n    return run(Scalar(NumTraits<Scalar>::IsSigned ? -1 : 0), Scalar(1));\n  }\n};\n\nenum {\n  meta_floor_log2_terminate,\n  meta_floor_log2_move_up,\n  meta_floor_log2_move_down,\n  meta_floor_log2_bogus\n};\n\ntemplate<unsigned int n, int lower, int upper> struct meta_floor_log2_selector\n{\n  enum { middle = (lower + upper) / 2,\n         value = (upper <= lower + 1) ? int(meta_floor_log2_terminate)\n               : (n < (1 << middle)) ? int(meta_floor_log2_move_down)\n               : (n==0) ? int(meta_floor_log2_bogus)\n               : int(meta_floor_log2_move_up)\n  };\n};\n\ntemplate<unsigned int n,\n         int lower = 0,\n         int upper = sizeof(unsigned int) * CHAR_BIT - 1,\n         int selector = meta_floor_log2_selector<n, lower, upper>::value>\nstruct meta_floor_log2 {};\n\ntemplate<unsigned int n, int lower, int upper>\nstruct meta_floor_log2<n, lower, upper, meta_floor_log2_move_down>\n{\n  enum { value = meta_floor_log2<n, lower, meta_floor_log2_selector<n, lower, upper>::middle>::value };\n};\n\ntemplate<unsigned int n, int lower, int upper>\nstruct meta_floor_log2<n, lower, upper, meta_floor_log2_move_up>\n{\n  enum { value = meta_floor_log2<n, meta_floor_log2_selector<n, lower, upper>::middle, upper>::value };\n};\n\ntemplate<unsigned int n, int lower, int upper>\nstruct meta_floor_log2<n, lower, upper, meta_floor_log2_terminate>\n{\n  enum { value = (n >= ((unsigned int)(1) << (lower+1))) ? lower+1 : lower };\n};\n\ntemplate<unsigned int n, int lower, int upper>\nstruct meta_floor_log2<n, lower, upper, meta_floor_log2_bogus>\n{\n  // no value, error at compile time\n};\n\ntemplate<typename Scalar>\nstruct random_default_impl<Scalar, false, true>\n{\n  static inline Scalar run(const Scalar& x, const Scalar& y)\n  { \n    typedef typename conditional<NumTraits<Scalar>::IsSigned,std::ptrdiff_t,std::size_t>::type ScalarX;\n    if(y<x)\n      return x;\n    // the following difference might overflow on a 32 bits system,\n    // but since y>=x the result converted to an unsigned long is still correct.\n    std::size_t range = ScalarX(y)-ScalarX(x);\n    std::size_t offset = 0;\n    // rejection sampling\n    std::size_t divisor = 1;\n    std::size_t multiplier = 1;\n    if(range<RAND_MAX) divisor = (std::size_t(RAND_MAX)+1)/(range+1);\n    else               multiplier = 1 + range/(std::size_t(RAND_MAX)+1);\n    do {\n      offset = (std::size_t(std::rand()) * multiplier) / divisor;\n    } while (offset > range);\n    return Scalar(ScalarX(x) + offset);\n  }\n\n  static inline Scalar run()\n  {\n#ifdef EIGEN_MAKING_DOCS\n    return run(Scalar(NumTraits<Scalar>::IsSigned ? -10 : 0), Scalar(10));\n#else\n    enum { rand_bits = meta_floor_log2<(unsigned int)(RAND_MAX)+1>::value,\n           scalar_bits = sizeof(Scalar) * CHAR_BIT,\n           shift = EIGEN_PLAIN_ENUM_MAX(0, int(rand_bits) - int(scalar_bits)),\n           offset = NumTraits<Scalar>::IsSigned ? (1 << (EIGEN_PLAIN_ENUM_MIN(rand_bits,scalar_bits)-1)) : 0\n    };\n    return Scalar((std::rand() >> shift) - offset);\n#endif\n  }\n};\n\ntemplate<typename Scalar>\nstruct random_default_impl<Scalar, true, false>\n{\n  static inline Scalar run(const Scalar& x, const Scalar& y)\n  {\n    return Scalar(random(real(x), real(y)),\n                  random(imag(x), imag(y)));\n  }\n  static inline Scalar run()\n  {\n    typedef typename NumTraits<Scalar>::Real RealScalar;\n    return Scalar(random<RealScalar>(), random<RealScalar>());\n  }\n};\n\ntemplate<typename Scalar>\ninline EIGEN_MATHFUNC_RETVAL(random, Scalar) random(const Scalar& x, const Scalar& y)\n{\n  return EIGEN_MATHFUNC_IMPL(random, Scalar)::run(x, y);\n}\n\ntemplate<typename Scalar>\ninline EIGEN_MATHFUNC_RETVAL(random, Scalar) random()\n{\n  return EIGEN_MATHFUNC_IMPL(random, Scalar)::run();\n}\n\n// Implementatin of is* functions\n\n// std::is* do not work with fast-math and gcc, std::is* are available on MSVC 2013 and newer, as well as in clang.\n#if (EIGEN_HAS_CXX11_MATH && !(EIGEN_COMP_GNUC_STRICT && __FINITE_MATH_ONLY__)) || (EIGEN_COMP_MSVC>=1800) || (EIGEN_COMP_CLANG)\n#define EIGEN_USE_STD_FPCLASSIFY 1\n#else\n#define EIGEN_USE_STD_FPCLASSIFY 0\n#endif\n\ntemplate<typename T>\nEIGEN_DEVICE_FUNC\ntypename internal::enable_if<internal::is_integral<T>::value,bool>::type\nisnan_impl(const T&) { return false; }\n\ntemplate<typename T>\nEIGEN_DEVICE_FUNC\ntypename internal::enable_if<internal::is_integral<T>::value,bool>::type\nisinf_impl(const T&) { return false; }\n\ntemplate<typename T>\nEIGEN_DEVICE_FUNC\ntypename internal::enable_if<internal::is_integral<T>::value,bool>::type\nisfinite_impl(const T&) { return true; }\n\ntemplate<typename T>\nEIGEN_DEVICE_FUNC\ntypename internal::enable_if<(!internal::is_integral<T>::value)&&(!NumTraits<T>::IsComplex),bool>::type\nisfinite_impl(const T& x)\n{\n  #ifdef __CUDA_ARCH__\n    return (::isfinite)(x);\n  #elif EIGEN_USE_STD_FPCLASSIFY\n    using std::isfinite;\n    return isfinite EIGEN_NOT_A_MACRO (x);\n  #else\n    return x<=NumTraits<T>::highest() && x>=NumTraits<T>::lowest();\n  #endif\n}\n\ntemplate<typename T>\nEIGEN_DEVICE_FUNC\ntypename internal::enable_if<(!internal::is_integral<T>::value)&&(!NumTraits<T>::IsComplex),bool>::type\nisinf_impl(const T& x)\n{\n  #ifdef __CUDA_ARCH__\n    return (::isinf)(x);\n  #elif EIGEN_USE_STD_FPCLASSIFY\n    using std::isinf;\n    return isinf EIGEN_NOT_A_MACRO (x);\n  #else\n    return x>NumTraits<T>::highest() || x<NumTraits<T>::lowest();\n  #endif\n}\n\ntemplate<typename T>\nEIGEN_DEVICE_FUNC\ntypename internal::enable_if<(!internal::is_integral<T>::value)&&(!NumTraits<T>::IsComplex),bool>::type\nisnan_impl(const T& x)\n{\n  #ifdef __CUDA_ARCH__\n    return (::isnan)(x);\n  #elif EIGEN_USE_STD_FPCLASSIFY\n    using std::isnan;\n    return isnan EIGEN_NOT_A_MACRO (x);\n  #else\n    return x != x;\n  #endif\n}\n\n#if (!EIGEN_USE_STD_FPCLASSIFY)\n\n#if EIGEN_COMP_MSVC\n\ntemplate<typename T> EIGEN_DEVICE_FUNC bool isinf_msvc_helper(T x)\n{\n  return _fpclass(x)==_FPCLASS_NINF || _fpclass(x)==_FPCLASS_PINF;\n}\n\n//MSVC defines a _isnan builtin function, but for double only\nEIGEN_DEVICE_FUNC inline bool isnan_impl(const long double& x) { return _isnan(x)!=0; }\nEIGEN_DEVICE_FUNC inline bool isnan_impl(const double& x)      { return _isnan(x)!=0; }\nEIGEN_DEVICE_FUNC inline bool isnan_impl(const float& x)       { return _isnan(x)!=0; }\n\nEIGEN_DEVICE_FUNC inline bool isinf_impl(const long double& x) { return isinf_msvc_helper(x); }\nEIGEN_DEVICE_FUNC inline bool isinf_impl(const double& x)      { return isinf_msvc_helper(x); }\nEIGEN_DEVICE_FUNC inline bool isinf_impl(const float& x)       { return isinf_msvc_helper(x); }\n\n#elif (defined __FINITE_MATH_ONLY__ && __FINITE_MATH_ONLY__ && EIGEN_COMP_GNUC)\n\n#if EIGEN_GNUC_AT_LEAST(5,0)\n  #define EIGEN_TMP_NOOPT_ATTRIB EIGEN_DEVICE_FUNC inline __attribute__((optimize(\"no-finite-math-only\")))\n#else\n  // NOTE the inline qualifier and noinline attribute are both needed: the former is to avoid linking issue (duplicate symbol),\n  //      while the second prevent too aggressive optimizations in fast-math mode:\n  #define EIGEN_TMP_NOOPT_ATTRIB EIGEN_DEVICE_FUNC inline __attribute__((noinline,optimize(\"no-finite-math-only\")))\n#endif\n\ntemplate<> EIGEN_TMP_NOOPT_ATTRIB bool isnan_impl(const long double& x) { return __builtin_isnan(x); }\ntemplate<> EIGEN_TMP_NOOPT_ATTRIB bool isnan_impl(const double& x)      { return __builtin_isnan(x); }\ntemplate<> EIGEN_TMP_NOOPT_ATTRIB bool isnan_impl(const float& x)       { return __builtin_isnan(x); }\ntemplate<> EIGEN_TMP_NOOPT_ATTRIB bool isinf_impl(const double& x)      { return __builtin_isinf(x); }\ntemplate<> EIGEN_TMP_NOOPT_ATTRIB bool isinf_impl(const float& x)       { return __builtin_isinf(x); }\ntemplate<> EIGEN_TMP_NOOPT_ATTRIB bool isinf_impl(const long double& x) { return __builtin_isinf(x); }\n\n#undef EIGEN_TMP_NOOPT_ATTRIB\n\n#endif\n\n#endif\n\n// The following overload are defined at the end of this file\ntemplate<typename T> EIGEN_DEVICE_FUNC bool isfinite_impl(const std::complex<T>& x);\ntemplate<typename T> EIGEN_DEVICE_FUNC bool isnan_impl(const std::complex<T>& x);\ntemplate<typename T> EIGEN_DEVICE_FUNC bool isinf_impl(const std::complex<T>& x);\n\ntemplate<typename T> T generic_fast_tanh_float(const T& a_x);\n\n} // end namespace internal\n\n/****************************************************************************\n* Generic math functions                                                    *\n****************************************************************************/\n\nnamespace numext {\n\n#ifndef __CUDA_ARCH__\ntemplate<typename T>\nEIGEN_DEVICE_FUNC\nEIGEN_ALWAYS_INLINE T mini(const T& x, const T& y)\n{\n  EIGEN_USING_STD_MATH(min);\n  return min EIGEN_NOT_A_MACRO (x,y);\n}\n\ntemplate<typename T>\nEIGEN_DEVICE_FUNC\nEIGEN_ALWAYS_INLINE T maxi(const T& x, const T& y)\n{\n  EIGEN_USING_STD_MATH(max);\n  return max EIGEN_NOT_A_MACRO (x,y);\n}\n#else\ntemplate<typename T>\nEIGEN_DEVICE_FUNC\nEIGEN_ALWAYS_INLINE T mini(const T& x, const T& y)\n{\n  return y < x ? y : x;\n}\ntemplate<>\nEIGEN_DEVICE_FUNC\nEIGEN_ALWAYS_INLINE float mini(const float& x, const float& y)\n{\n  return fminf(x, y);\n}\ntemplate<typename T>\nEIGEN_DEVICE_FUNC\nEIGEN_ALWAYS_INLINE T maxi(const T& x, const T& y)\n{\n  return x < y ? y : x;\n}\ntemplate<>\nEIGEN_DEVICE_FUNC\nEIGEN_ALWAYS_INLINE float maxi(const float& x, const float& y)\n{\n  return fmaxf(x, y);\n}\n#endif\n\n\ntemplate<typename Scalar>\nEIGEN_DEVICE_FUNC\ninline EIGEN_MATHFUNC_RETVAL(real, Scalar) real(const Scalar& x)\n{\n  return EIGEN_MATHFUNC_IMPL(real, Scalar)::run(x);\n}\n\ntemplate<typename Scalar>\nEIGEN_DEVICE_FUNC\ninline typename internal::add_const_on_value_type< EIGEN_MATHFUNC_RETVAL(real_ref, Scalar) >::type real_ref(const Scalar& x)\n{\n  return internal::real_ref_impl<Scalar>::run(x);\n}\n\ntemplate<typename Scalar>\nEIGEN_DEVICE_FUNC\ninline EIGEN_MATHFUNC_RETVAL(real_ref, Scalar) real_ref(Scalar& x)\n{\n  return EIGEN_MATHFUNC_IMPL(real_ref, Scalar)::run(x);\n}\n\ntemplate<typename Scalar>\nEIGEN_DEVICE_FUNC\ninline EIGEN_MATHFUNC_RETVAL(imag, Scalar) imag(const Scalar& x)\n{\n  return EIGEN_MATHFUNC_IMPL(imag, Scalar)::run(x);\n}\n\ntemplate<typename Scalar>\nEIGEN_DEVICE_FUNC\ninline EIGEN_MATHFUNC_RETVAL(arg, Scalar) arg(const Scalar& x)\n{\n  return EIGEN_MATHFUNC_IMPL(arg, Scalar)::run(x);\n}\n\ntemplate<typename Scalar>\nEIGEN_DEVICE_FUNC\ninline typename internal::add_const_on_value_type< EIGEN_MATHFUNC_RETVAL(imag_ref, Scalar) >::type imag_ref(const Scalar& x)\n{\n  return internal::imag_ref_impl<Scalar>::run(x);\n}\n\ntemplate<typename Scalar>\nEIGEN_DEVICE_FUNC\ninline EIGEN_MATHFUNC_RETVAL(imag_ref, Scalar) imag_ref(Scalar& x)\n{\n  return EIGEN_MATHFUNC_IMPL(imag_ref, Scalar)::run(x);\n}\n\ntemplate<typename Scalar>\nEIGEN_DEVICE_FUNC\ninline EIGEN_MATHFUNC_RETVAL(conj, Scalar) conj(const Scalar& x)\n{\n  return EIGEN_MATHFUNC_IMPL(conj, Scalar)::run(x);\n}\n\ntemplate<typename Scalar>\nEIGEN_DEVICE_FUNC\ninline EIGEN_MATHFUNC_RETVAL(abs2, Scalar) abs2(const Scalar& x)\n{\n  return EIGEN_MATHFUNC_IMPL(abs2, Scalar)::run(x);\n}\n\ntemplate<typename Scalar>\nEIGEN_DEVICE_FUNC\ninline EIGEN_MATHFUNC_RETVAL(norm1, Scalar) norm1(const Scalar& x)\n{\n  return EIGEN_MATHFUNC_IMPL(norm1, Scalar)::run(x);\n}\n\ntemplate<typename Scalar>\nEIGEN_DEVICE_FUNC\ninline EIGEN_MATHFUNC_RETVAL(hypot, Scalar) hypot(const Scalar& x, const Scalar& y)\n{\n  return EIGEN_MATHFUNC_IMPL(hypot, Scalar)::run(x, y);\n}\n\ntemplate<typename Scalar>\nEIGEN_DEVICE_FUNC\ninline EIGEN_MATHFUNC_RETVAL(log1p, Scalar) log1p(const Scalar& x)\n{\n  return EIGEN_MATHFUNC_IMPL(log1p, Scalar)::run(x);\n}\n\n#ifdef __CUDACC__\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\nfloat log1p(const float &x) { return ::log1pf(x); }\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\ndouble log1p(const double &x) { return ::log1p(x); }\n#endif\n\ntemplate<typename ScalarX,typename ScalarY>\nEIGEN_DEVICE_FUNC\ninline typename internal::pow_impl<ScalarX,ScalarY>::result_type pow(const ScalarX& x, const ScalarY& y)\n{\n  return internal::pow_impl<ScalarX,ScalarY>::run(x, y);\n}\n\ntemplate<typename T> EIGEN_DEVICE_FUNC bool (isnan)   (const T &x) { return internal::isnan_impl(x); }\ntemplate<typename T> EIGEN_DEVICE_FUNC bool (isinf)   (const T &x) { return internal::isinf_impl(x); }\ntemplate<typename T> EIGEN_DEVICE_FUNC bool (isfinite)(const T &x) { return internal::isfinite_impl(x); }\n\ntemplate<typename Scalar>\nEIGEN_DEVICE_FUNC\ninline EIGEN_MATHFUNC_RETVAL(round, Scalar) round(const Scalar& x)\n{\n  return EIGEN_MATHFUNC_IMPL(round, Scalar)::run(x);\n}\n\ntemplate<typename T>\nEIGEN_DEVICE_FUNC\nT (floor)(const T& x)\n{\n  EIGEN_USING_STD_MATH(floor);\n  return floor(x);\n}\n\n#ifdef __CUDACC__\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\nfloat floor(const float &x) { return ::floorf(x); }\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\ndouble floor(const double &x) { return ::floor(x); }\n#endif\n\ntemplate<typename T>\nEIGEN_DEVICE_FUNC\nT (ceil)(const T& x)\n{\n  EIGEN_USING_STD_MATH(ceil);\n  return ceil(x);\n}\n\n#ifdef __CUDACC__\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\nfloat ceil(const float &x) { return ::ceilf(x); }\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\ndouble ceil(const double &x) { return ::ceil(x); }\n#endif\n\n\n/** Log base 2 for 32 bits positive integers.\n  * Conveniently returns 0 for x==0. */\ninline int log2(int x)\n{\n  eigen_assert(x>=0);\n  unsigned int v(x);\n  static const int table[32] = { 0, 9, 1, 10, 13, 21, 2, 29, 11, 14, 16, 18, 22, 25, 3, 30, 8, 12, 20, 28, 15, 17, 24, 7, 19, 27, 23, 6, 26, 5, 4, 31 };\n  v |= v >> 1;\n  v |= v >> 2;\n  v |= v >> 4;\n  v |= v >> 8;\n  v |= v >> 16;\n  return table[(v * 0x07C4ACDDU) >> 27];\n}\n\n/** \\returns the square root of \\a x.\n  *\n  * It is essentially equivalent to \\code using std::sqrt; return sqrt(x); \\endcode,\n  * but slightly faster for float/double and some compilers (e.g., gcc), thanks to\n  * specializations when SSE is enabled.\n  *\n  * It's usage is justified in performance critical functions, like norm/normalize.\n  */\ntemplate<typename T>\nEIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\nT sqrt(const T &x)\n{\n  EIGEN_USING_STD_MATH(sqrt);\n  return sqrt(x);\n}\n\ntemplate<typename T>\nEIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\nT log(const T &x) {\n  EIGEN_USING_STD_MATH(log);\n  return log(x);\n}\n\n#ifdef __CUDACC__\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\nfloat log(const float &x) { return ::logf(x); }\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\ndouble log(const double &x) { return ::log(x); }\n#endif\n\ntemplate<typename T>\nEIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\ntypename NumTraits<T>::Real abs(const T &x) {\n  EIGEN_USING_STD_MATH(abs);\n  return abs(x);\n}\n\n#ifdef __CUDACC__\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\nfloat abs(const float &x) { return ::fabsf(x); }\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\ndouble abs(const double &x) { return ::fabs(x); }\n\ntemplate <> EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\nfloat abs(const std::complex<float>& x) {\n  return ::hypotf(x.real(), x.imag());\n}\n\ntemplate <> EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\ndouble abs(const std::complex<double>& x) {\n  return ::hypot(x.real(), x.imag());\n}\n#endif\n\ntemplate<typename T>\nEIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\nT exp(const T &x) {\n  EIGEN_USING_STD_MATH(exp);\n  return exp(x);\n}\n\n#ifdef __CUDACC__\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\nfloat exp(const float &x) { return ::expf(x); }\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\ndouble exp(const double &x) { return ::exp(x); }\n#endif\n\ntemplate<typename T>\nEIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\nT cos(const T &x) {\n  EIGEN_USING_STD_MATH(cos);\n  return cos(x);\n}\n\n#ifdef __CUDACC__\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\nfloat cos(const float &x) { return ::cosf(x); }\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\ndouble cos(const double &x) { return ::cos(x); }\n#endif\n\ntemplate<typename T>\nEIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\nT sin(const T &x) {\n  EIGEN_USING_STD_MATH(sin);\n  return sin(x);\n}\n\n#ifdef __CUDACC__\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\nfloat sin(const float &x) { return ::sinf(x); }\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\ndouble sin(const double &x) { return ::sin(x); }\n#endif\n\ntemplate<typename T>\nEIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\nT tan(const T &x) {\n  EIGEN_USING_STD_MATH(tan);\n  return tan(x);\n}\n\n#ifdef __CUDACC__\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\nfloat tan(const float &x) { return ::tanf(x); }\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\ndouble tan(const double &x) { return ::tan(x); }\n#endif\n\ntemplate<typename T>\nEIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\nT acos(const T &x) {\n  EIGEN_USING_STD_MATH(acos);\n  return acos(x);\n}\n\n#ifdef __CUDACC__\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\nfloat acos(const float &x) { return ::acosf(x); }\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\ndouble acos(const double &x) { return ::acos(x); }\n#endif\n\ntemplate<typename T>\nEIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\nT asin(const T &x) {\n  EIGEN_USING_STD_MATH(asin);\n  return asin(x);\n}\n\n#ifdef __CUDACC__\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\nfloat asin(const float &x) { return ::asinf(x); }\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\ndouble asin(const double &x) { return ::asin(x); }\n#endif\n\ntemplate<typename T>\nEIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\nT atan(const T &x) {\n  EIGEN_USING_STD_MATH(atan);\n  return atan(x);\n}\n\n#ifdef __CUDACC__\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\nfloat atan(const float &x) { return ::atanf(x); }\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\ndouble atan(const double &x) { return ::atan(x); }\n#endif\n\n\ntemplate<typename T>\nEIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\nT cosh(const T &x) {\n  EIGEN_USING_STD_MATH(cosh);\n  return cosh(x);\n}\n\n#ifdef __CUDACC__\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\nfloat cosh(const float &x) { return ::coshf(x); }\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\ndouble cosh(const double &x) { return ::cosh(x); }\n#endif\n\ntemplate<typename T>\nEIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\nT sinh(const T &x) {\n  EIGEN_USING_STD_MATH(sinh);\n  return sinh(x);\n}\n\n#ifdef __CUDACC__\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\nfloat sinh(const float &x) { return ::sinhf(x); }\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\ndouble sinh(const double &x) { return ::sinh(x); }\n#endif\n\ntemplate<typename T>\nEIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\nT tanh(const T &x) {\n  EIGEN_USING_STD_MATH(tanh);\n  return tanh(x);\n}\n\n#if (!defined(__CUDACC__)) && EIGEN_FAST_MATH\nEIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\nfloat tanh(float x) { return internal::generic_fast_tanh_float(x); }\n#endif\n\n#ifdef __CUDACC__\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\nfloat tanh(const float &x) { return ::tanhf(x); }\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\ndouble tanh(const double &x) { return ::tanh(x); }\n#endif\n\ntemplate <typename T>\nEIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\nT fmod(const T& a, const T& b) {\n  EIGEN_USING_STD_MATH(fmod);\n  return fmod(a, b);\n}\n\n#ifdef __CUDACC__\ntemplate <>\nEIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\nfloat fmod(const float& a, const float& b) {\n  return ::fmodf(a, b);\n}\n\ntemplate <>\nEIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\ndouble fmod(const double& a, const double& b) {\n  return ::fmod(a, b);\n}\n#endif\n\n} // end namespace numext\n\nnamespace internal {\n\ntemplate<typename T>\nEIGEN_DEVICE_FUNC bool isfinite_impl(const std::complex<T>& x)\n{\n  return (numext::isfinite)(numext::real(x)) && (numext::isfinite)(numext::imag(x));\n}\n\ntemplate<typename T>\nEIGEN_DEVICE_FUNC bool isnan_impl(const std::complex<T>& x)\n{\n  return (numext::isnan)(numext::real(x)) || (numext::isnan)(numext::imag(x));\n}\n\ntemplate<typename T>\nEIGEN_DEVICE_FUNC bool isinf_impl(const std::complex<T>& x)\n{\n  return ((numext::isinf)(numext::real(x)) || (numext::isinf)(numext::imag(x))) && (!(numext::isnan)(x));\n}\n\n/****************************************************************************\n* Implementation of fuzzy comparisons                                       *\n****************************************************************************/\n\ntemplate<typename Scalar,\n         bool IsComplex,\n         bool IsInteger>\nstruct scalar_fuzzy_default_impl {};\n\ntemplate<typename Scalar>\nstruct scalar_fuzzy_default_impl<Scalar, false, false>\n{\n  typedef typename NumTraits<Scalar>::Real RealScalar;\n  template<typename OtherScalar> EIGEN_DEVICE_FUNC\n  static inline bool isMuchSmallerThan(const Scalar& x, const OtherScalar& y, const RealScalar& prec)\n  {\n    return numext::abs(x) <= numext::abs(y) * prec;\n  }\n  EIGEN_DEVICE_FUNC\n  static inline bool isApprox(const Scalar& x, const Scalar& y, const RealScalar& prec)\n  {\n    return numext::abs(x - y) <= numext::mini(numext::abs(x), numext::abs(y)) * prec;\n  }\n  EIGEN_DEVICE_FUNC\n  static inline bool isApproxOrLessThan(const Scalar& x, const Scalar& y, const RealScalar& prec)\n  {\n    return x <= y || isApprox(x, y, prec);\n  }\n};\n\ntemplate<typename Scalar>\nstruct scalar_fuzzy_default_impl<Scalar, false, true>\n{\n  typedef typename NumTraits<Scalar>::Real RealScalar;\n  template<typename OtherScalar> EIGEN_DEVICE_FUNC\n  static inline bool isMuchSmallerThan(const Scalar& x, const Scalar&, const RealScalar&)\n  {\n    return x == Scalar(0);\n  }\n  EIGEN_DEVICE_FUNC\n  static inline bool isApprox(const Scalar& x, const Scalar& y, const RealScalar&)\n  {\n    return x == y;\n  }\n  EIGEN_DEVICE_FUNC\n  static inline bool isApproxOrLessThan(const Scalar& x, const Scalar& y, const RealScalar&)\n  {\n    return x <= y;\n  }\n};\n\ntemplate<typename Scalar>\nstruct scalar_fuzzy_default_impl<Scalar, true, false>\n{\n  typedef typename NumTraits<Scalar>::Real RealScalar;\n  template<typename OtherScalar> EIGEN_DEVICE_FUNC\n  static inline bool isMuchSmallerThan(const Scalar& x, const OtherScalar& y, const RealScalar& prec)\n  {\n    return numext::abs2(x) <= numext::abs2(y) * prec * prec;\n  }\n  EIGEN_DEVICE_FUNC\n  static inline bool isApprox(const Scalar& x, const Scalar& y, const RealScalar& prec)\n  {\n    return numext::abs2(x - y) <= numext::mini(numext::abs2(x), numext::abs2(y)) * prec * prec;\n  }\n};\n\ntemplate<typename Scalar>\nstruct scalar_fuzzy_impl : scalar_fuzzy_default_impl<Scalar, NumTraits<Scalar>::IsComplex, NumTraits<Scalar>::IsInteger> {};\n\ntemplate<typename Scalar, typename OtherScalar> EIGEN_DEVICE_FUNC\ninline bool isMuchSmallerThan(const Scalar& x, const OtherScalar& y,\n                              const typename NumTraits<Scalar>::Real &precision = NumTraits<Scalar>::dummy_precision())\n{\n  return scalar_fuzzy_impl<Scalar>::template isMuchSmallerThan<OtherScalar>(x, y, precision);\n}\n\ntemplate<typename Scalar> EIGEN_DEVICE_FUNC\ninline bool isApprox(const Scalar& x, const Scalar& y,\n                     const typename NumTraits<Scalar>::Real &precision = NumTraits<Scalar>::dummy_precision())\n{\n  return scalar_fuzzy_impl<Scalar>::isApprox(x, y, precision);\n}\n\ntemplate<typename Scalar> EIGEN_DEVICE_FUNC\ninline bool isApproxOrLessThan(const Scalar& x, const Scalar& y,\n                               const typename NumTraits<Scalar>::Real &precision = NumTraits<Scalar>::dummy_precision())\n{\n  return scalar_fuzzy_impl<Scalar>::isApproxOrLessThan(x, y, precision);\n}\n\n/******************************************\n***  The special case of the  bool type ***\n******************************************/\n\ntemplate<> struct random_impl<bool>\n{\n  static inline bool run()\n  {\n    return random<int>(0,1)==0 ? false : true;\n  }\n};\n\ntemplate<> struct scalar_fuzzy_impl<bool>\n{\n  typedef bool RealScalar;\n  \n  template<typename OtherScalar> EIGEN_DEVICE_FUNC\n  static inline bool isMuchSmallerThan(const bool& x, const bool&, const bool&)\n  {\n    return !x;\n  }\n  \n  EIGEN_DEVICE_FUNC\n  static inline bool isApprox(bool x, bool y, bool)\n  {\n    return x == y;\n  }\n\n  EIGEN_DEVICE_FUNC\n  static inline bool isApproxOrLessThan(const bool& x, const bool& y, const bool&)\n  {\n    return (!x) || y;\n  }\n  \n};\n\n  \n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_MATHFUNCTIONS_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/MathFunctionsImpl.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2014 Pedro Gonnet (pedro.gonnet@gmail.com)\n// Copyright (C) 2016 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_MATHFUNCTIONSIMPL_H\n#define EIGEN_MATHFUNCTIONSIMPL_H\n\nnamespace Eigen {\n\nnamespace internal {\n\n/** \\internal \\returns the hyperbolic tan of \\a a (coeff-wise)\n    Doesn't do anything fancy, just a 13/6-degree rational interpolant which\n    is accurate up to a couple of ulp in the range [-9, 9], outside of which\n    the tanh(x) = +/-1.\n\n    This implementation works on both scalars and packets.\n*/\ntemplate<typename T>\nT generic_fast_tanh_float(const T& a_x)\n{\n  // Clamp the inputs to the range [-9, 9] since anything outside\n  // this range is +/-1.0f in single-precision.\n  const T plus_9 = pset1<T>(9.f);\n  const T minus_9 = pset1<T>(-9.f);\n  // NOTE GCC prior to 6.3 might improperly optimize this max/min\n  //      step such that if a_x is nan, x will be either 9 or -9,\n  //      and tanh will return 1 or -1 instead of nan.\n  //      This is supposed to be fixed in gcc6.3,\n  //      see: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=72867\n  const T x = pmax(minus_9,pmin(plus_9,a_x));\n  // The monomial coefficients of the numerator polynomial (odd).\n  const T alpha_1 = pset1<T>(4.89352455891786e-03f);\n  const T alpha_3 = pset1<T>(6.37261928875436e-04f);\n  const T alpha_5 = pset1<T>(1.48572235717979e-05f);\n  const T alpha_7 = pset1<T>(5.12229709037114e-08f);\n  const T alpha_9 = pset1<T>(-8.60467152213735e-11f);\n  const T alpha_11 = pset1<T>(2.00018790482477e-13f);\n  const T alpha_13 = pset1<T>(-2.76076847742355e-16f);\n\n  // The monomial coefficients of the denominator polynomial (even).\n  const T beta_0 = pset1<T>(4.89352518554385e-03f);\n  const T beta_2 = pset1<T>(2.26843463243900e-03f);\n  const T beta_4 = pset1<T>(1.18534705686654e-04f);\n  const T beta_6 = pset1<T>(1.19825839466702e-06f);\n\n  // Since the polynomials are odd/even, we need x^2.\n  const T x2 = pmul(x, x);\n\n  // Evaluate the numerator polynomial p.\n  T p = pmadd(x2, alpha_13, alpha_11);\n  p = pmadd(x2, p, alpha_9);\n  p = pmadd(x2, p, alpha_7);\n  p = pmadd(x2, p, alpha_5);\n  p = pmadd(x2, p, alpha_3);\n  p = pmadd(x2, p, alpha_1);\n  p = pmul(x, p);\n\n  // Evaluate the denominator polynomial p.\n  T q = pmadd(x2, beta_6, beta_4);\n  q = pmadd(x2, q, beta_2);\n  q = pmadd(x2, q, beta_0);\n\n  // Divide the numerator by the denominator.\n  return pdiv(p, q);\n}\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_MATHFUNCTIONSIMPL_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/Matrix.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2006-2010 Benoit Jacob <jacob.benoit.1@gmail.com>\n// Copyright (C) 2008-2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_MATRIX_H\n#define EIGEN_MATRIX_H\n\nnamespace Eigen {\n\nnamespace internal {\ntemplate<typename _Scalar, int _Rows, int _Cols, int _Options, int _MaxRows, int _MaxCols>\nstruct traits<Matrix<_Scalar, _Rows, _Cols, _Options, _MaxRows, _MaxCols> >\n{\nprivate:\n  enum { size = internal::size_at_compile_time<_Rows,_Cols>::ret };\n  typedef typename find_best_packet<_Scalar,size>::type PacketScalar;\n  enum {\n      row_major_bit = _Options&RowMajor ? RowMajorBit : 0,\n      is_dynamic_size_storage = _MaxRows==Dynamic || _MaxCols==Dynamic,\n      max_size = is_dynamic_size_storage ? Dynamic : _MaxRows*_MaxCols,\n      default_alignment = compute_default_alignment<_Scalar,max_size>::value,\n      actual_alignment = ((_Options&DontAlign)==0) ? default_alignment : 0,\n      required_alignment = unpacket_traits<PacketScalar>::alignment,\n      packet_access_bit = (packet_traits<_Scalar>::Vectorizable && (EIGEN_UNALIGNED_VECTORIZE || (actual_alignment>=required_alignment))) ? PacketAccessBit : 0\n    };\n    \npublic:\n  typedef _Scalar Scalar;\n  typedef Dense StorageKind;\n  typedef Eigen::Index StorageIndex;\n  typedef MatrixXpr XprKind;\n  enum {\n    RowsAtCompileTime = _Rows,\n    ColsAtCompileTime = _Cols,\n    MaxRowsAtCompileTime = _MaxRows,\n    MaxColsAtCompileTime = _MaxCols,\n    Flags = compute_matrix_flags<_Scalar, _Rows, _Cols, _Options, _MaxRows, _MaxCols>::ret,\n    Options = _Options,\n    InnerStrideAtCompileTime = 1,\n    OuterStrideAtCompileTime = (Options&RowMajor) ? ColsAtCompileTime : RowsAtCompileTime,\n    \n    // FIXME, the following flag in only used to define NeedsToAlign in PlainObjectBase\n    EvaluatorFlags = LinearAccessBit | DirectAccessBit | packet_access_bit | row_major_bit,\n    Alignment = actual_alignment\n  };\n};\n}\n\n/** \\class Matrix\n  * \\ingroup Core_Module\n  *\n  * \\brief The matrix class, also used for vectors and row-vectors\n  *\n  * The %Matrix class is the work-horse for all \\em dense (\\ref dense \"note\") matrices and vectors within Eigen.\n  * Vectors are matrices with one column, and row-vectors are matrices with one row.\n  *\n  * The %Matrix class encompasses \\em both fixed-size and dynamic-size objects (\\ref fixedsize \"note\").\n  *\n  * The first three template parameters are required:\n  * \\tparam _Scalar Numeric type, e.g. float, double, int or std::complex<float>.\n  *                 User defined scalar types are supported as well (see \\ref user_defined_scalars \"here\").\n  * \\tparam _Rows Number of rows, or \\b Dynamic\n  * \\tparam _Cols Number of columns, or \\b Dynamic\n  *\n  * The remaining template parameters are optional -- in most cases you don't have to worry about them.\n  * \\tparam _Options A combination of either \\b #RowMajor or \\b #ColMajor, and of either\n  *                 \\b #AutoAlign or \\b #DontAlign.\n  *                 The former controls \\ref TopicStorageOrders \"storage order\", and defaults to column-major. The latter controls alignment, which is required\n  *                 for vectorization. It defaults to aligning matrices except for fixed sizes that aren't a multiple of the packet size.\n  * \\tparam _MaxRows Maximum number of rows. Defaults to \\a _Rows (\\ref maxrows \"note\").\n  * \\tparam _MaxCols Maximum number of columns. Defaults to \\a _Cols (\\ref maxrows \"note\").\n  *\n  * Eigen provides a number of typedefs covering the usual cases. Here are some examples:\n  *\n  * \\li \\c Matrix2d is a 2x2 square matrix of doubles (\\c Matrix<double, 2, 2>)\n  * \\li \\c Vector4f is a vector of 4 floats (\\c Matrix<float, 4, 1>)\n  * \\li \\c RowVector3i is a row-vector of 3 ints (\\c Matrix<int, 1, 3>)\n  *\n  * \\li \\c MatrixXf is a dynamic-size matrix of floats (\\c Matrix<float, Dynamic, Dynamic>)\n  * \\li \\c VectorXf is a dynamic-size vector of floats (\\c Matrix<float, Dynamic, 1>)\n  *\n  * \\li \\c Matrix2Xf is a partially fixed-size (dynamic-size) matrix of floats (\\c Matrix<float, 2, Dynamic>)\n  * \\li \\c MatrixX3d is a partially dynamic-size (fixed-size) matrix of double (\\c Matrix<double, Dynamic, 3>)\n  *\n  * See \\link matrixtypedefs this page \\endlink for a complete list of predefined \\em %Matrix and \\em Vector typedefs.\n  *\n  * You can access elements of vectors and matrices using normal subscripting:\n  *\n  * \\code\n  * Eigen::VectorXd v(10);\n  * v[0] = 0.1;\n  * v[1] = 0.2;\n  * v(0) = 0.3;\n  * v(1) = 0.4;\n  *\n  * Eigen::MatrixXi m(10, 10);\n  * m(0, 1) = 1;\n  * m(0, 2) = 2;\n  * m(0, 3) = 3;\n  * \\endcode\n  *\n  * This class can be extended with the help of the plugin mechanism described on the page\n  * \\ref TopicCustomizing_Plugins by defining the preprocessor symbol \\c EIGEN_MATRIX_PLUGIN.\n  *\n  * <i><b>Some notes:</b></i>\n  *\n  * <dl>\n  * <dt><b>\\anchor dense Dense versus sparse:</b></dt>\n  * <dd>This %Matrix class handles dense, not sparse matrices and vectors. For sparse matrices and vectors, see the Sparse module.\n  *\n  * Dense matrices and vectors are plain usual arrays of coefficients. All the coefficients are stored, in an ordinary contiguous array.\n  * This is unlike Sparse matrices and vectors where the coefficients are stored as a list of nonzero coefficients.</dd>\n  *\n  * <dt><b>\\anchor fixedsize Fixed-size versus dynamic-size:</b></dt>\n  * <dd>Fixed-size means that the numbers of rows and columns are known are compile-time. In this case, Eigen allocates the array\n  * of coefficients as a fixed-size array, as a class member. This makes sense for very small matrices, typically up to 4x4, sometimes up\n  * to 16x16. Larger matrices should be declared as dynamic-size even if one happens to know their size at compile-time.\n  *\n  * Dynamic-size means that the numbers of rows or columns are not necessarily known at compile-time. In this case they are runtime\n  * variables, and the array of coefficients is allocated dynamically on the heap.\n  *\n  * Note that \\em dense matrices, be they Fixed-size or Dynamic-size, <em>do not</em> expand dynamically in the sense of a std::map.\n  * If you want this behavior, see the Sparse module.</dd>\n  *\n  * <dt><b>\\anchor maxrows _MaxRows and _MaxCols:</b></dt>\n  * <dd>In most cases, one just leaves these parameters to the default values.\n  * These parameters mean the maximum size of rows and columns that the matrix may have. They are useful in cases\n  * when the exact numbers of rows and columns are not known are compile-time, but it is known at compile-time that they cannot\n  * exceed a certain value. This happens when taking dynamic-size blocks inside fixed-size matrices: in this case _MaxRows and _MaxCols\n  * are the dimensions of the original matrix, while _Rows and _Cols are Dynamic.</dd>\n  * </dl>\n  *\n  * <i><b>ABI and storage layout</b></i>\n  *\n  * The table below summarizes the ABI of some possible Matrix instances which is fixed thorough the lifetime of Eigen 3.\n  * <table  class=\"manual\">\n  * <tr><th>Matrix type</th><th>Equivalent C structure</th></tr>\n  * <tr><td>\\code Matrix<T,Dynamic,Dynamic> \\endcode</td><td>\\code\n  * struct {\n  *   T *data;                  // with (size_t(data)%EIGEN_MAX_ALIGN_BYTES)==0\n  *   Eigen::Index rows, cols;\n  *  };\n  * \\endcode</td></tr>\n  * <tr class=\"alt\"><td>\\code\n  * Matrix<T,Dynamic,1>\n  * Matrix<T,1,Dynamic> \\endcode</td><td>\\code\n  * struct {\n  *   T *data;                  // with (size_t(data)%EIGEN_MAX_ALIGN_BYTES)==0\n  *   Eigen::Index size;\n  *  };\n  * \\endcode</td></tr>\n  * <tr><td>\\code Matrix<T,Rows,Cols> \\endcode</td><td>\\code\n  * struct {\n  *   T data[Rows*Cols];        // with (size_t(data)%A(Rows*Cols*sizeof(T)))==0\n  *  };\n  * \\endcode</td></tr>\n  * <tr class=\"alt\"><td>\\code Matrix<T,Dynamic,Dynamic,0,MaxRows,MaxCols> \\endcode</td><td>\\code\n  * struct {\n  *   T data[MaxRows*MaxCols];  // with (size_t(data)%A(MaxRows*MaxCols*sizeof(T)))==0\n  *   Eigen::Index rows, cols;\n  *  };\n  * \\endcode</td></tr>\n  * </table>\n  * Note that in this table Rows, Cols, MaxRows and MaxCols are all positive integers. A(S) is defined to the largest possible power-of-two\n  * smaller to EIGEN_MAX_STATIC_ALIGN_BYTES.\n  *\n  * \\see MatrixBase for the majority of the API methods for matrices, \\ref TopicClassHierarchy,\n  * \\ref TopicStorageOrders\n  */\n\ntemplate<typename _Scalar, int _Rows, int _Cols, int _Options, int _MaxRows, int _MaxCols>\nclass Matrix\n  : public PlainObjectBase<Matrix<_Scalar, _Rows, _Cols, _Options, _MaxRows, _MaxCols> >\n{\n  public:\n\n    /** \\brief Base class typedef.\n      * \\sa PlainObjectBase\n      */\n    typedef PlainObjectBase<Matrix> Base;\n\n    enum { Options = _Options };\n\n    EIGEN_DENSE_PUBLIC_INTERFACE(Matrix)\n\n    typedef typename Base::PlainObject PlainObject;\n\n    using Base::base;\n    using Base::coeffRef;\n\n    /**\n      * \\brief Assigns matrices to each other.\n      *\n      * \\note This is a special case of the templated operator=. Its purpose is\n      * to prevent a default operator= from hiding the templated operator=.\n      *\n      * \\callgraph\n      */\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Matrix& operator=(const Matrix& other)\n    {\n      return Base::_set(other);\n    }\n\n    /** \\internal\n      * \\brief Copies the value of the expression \\a other into \\c *this with automatic resizing.\n      *\n      * *this might be resized to match the dimensions of \\a other. If *this was a null matrix (not already initialized),\n      * it will be initialized.\n      *\n      * Note that copying a row-vector into a vector (and conversely) is allowed.\n      * The resizing, if any, is then done in the appropriate way so that row-vectors\n      * remain row-vectors and vectors remain vectors.\n      */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Matrix& operator=(const DenseBase<OtherDerived>& other)\n    {\n      return Base::_set(other);\n    }\n\n    /* Here, doxygen failed to copy the brief information when using \\copydoc */\n\n    /**\n      * \\brief Copies the generic expression \\a other into *this.\n      * \\copydetails DenseBase::operator=(const EigenBase<OtherDerived> &other)\n      */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Matrix& operator=(const EigenBase<OtherDerived> &other)\n    {\n      return Base::operator=(other);\n    }\n\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Matrix& operator=(const ReturnByValue<OtherDerived>& func)\n    {\n      return Base::operator=(func);\n    }\n\n    /** \\brief Default constructor.\n      *\n      * For fixed-size matrices, does nothing.\n      *\n      * For dynamic-size matrices, creates an empty matrix of size 0. Does not allocate any array. Such a matrix\n      * is called a null matrix. This constructor is the unique way to create null matrices: resizing\n      * a matrix to 0 is not supported.\n      *\n      * \\sa resize(Index,Index)\n      */\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Matrix() : Base()\n    {\n      Base::_check_template_params();\n      EIGEN_INITIALIZE_COEFFS_IF_THAT_OPTION_IS_ENABLED\n    }\n\n    // FIXME is it still needed\n    EIGEN_DEVICE_FUNC\n    explicit Matrix(internal::constructor_without_unaligned_array_assert)\n      : Base(internal::constructor_without_unaligned_array_assert())\n    { Base::_check_template_params(); EIGEN_INITIALIZE_COEFFS_IF_THAT_OPTION_IS_ENABLED }\n\n#if EIGEN_HAS_RVALUE_REFERENCES\n    EIGEN_DEVICE_FUNC\n    Matrix(Matrix&& other) EIGEN_NOEXCEPT_IF(std::is_nothrow_move_constructible<Scalar>::value)\n      : Base(std::move(other))\n    {\n      Base::_check_template_params();\n      if (RowsAtCompileTime!=Dynamic && ColsAtCompileTime!=Dynamic)\n        Base::_set_noalias(other);\n    }\n    EIGEN_DEVICE_FUNC\n    Matrix& operator=(Matrix&& other) EIGEN_NOEXCEPT_IF(std::is_nothrow_move_assignable<Scalar>::value)\n    {\n      other.swap(*this);\n      return *this;\n    }\n#endif\n\n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n\n    // This constructor is for both 1x1 matrices and dynamic vectors\n    template<typename T>\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE explicit Matrix(const T& x)\n    {\n      Base::_check_template_params();\n      Base::template _init1<T>(x);\n    }\n\n    template<typename T0, typename T1>\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Matrix(const T0& x, const T1& y)\n    {\n      Base::_check_template_params();\n      Base::template _init2<T0,T1>(x, y);\n    }\n    #else\n    /** \\brief Constructs a fixed-sized matrix initialized with coefficients starting at \\a data */\n    EIGEN_DEVICE_FUNC\n    explicit Matrix(const Scalar *data);\n\n    /** \\brief Constructs a vector or row-vector with given dimension. \\only_for_vectors\n      *\n      * This is useful for dynamic-size vectors. For fixed-size vectors,\n      * it is redundant to pass these parameters, so one should use the default constructor\n      * Matrix() instead.\n      * \n      * \\warning This constructor is disabled for fixed-size \\c 1x1 matrices. For instance,\n      * calling Matrix<double,1,1>(1) will call the initialization constructor: Matrix(const Scalar&).\n      * For fixed-size \\c 1x1 matrices it is therefore recommended to use the default\n      * constructor Matrix() instead, especially when using one of the non standard\n      * \\c EIGEN_INITIALIZE_MATRICES_BY_{ZERO,\\c NAN} macros (see \\ref TopicPreprocessorDirectives).\n      */\n    EIGEN_STRONG_INLINE explicit Matrix(Index dim);\n    /** \\brief Constructs an initialized 1x1 matrix with the given coefficient */\n    Matrix(const Scalar& x);\n    /** \\brief Constructs an uninitialized matrix with \\a rows rows and \\a cols columns.\n      *\n      * This is useful for dynamic-size matrices. For fixed-size matrices,\n      * it is redundant to pass these parameters, so one should use the default constructor\n      * Matrix() instead.\n      * \n      * \\warning This constructor is disabled for fixed-size \\c 1x2 and \\c 2x1 vectors. For instance,\n      * calling Matrix2f(2,1) will call the initialization constructor: Matrix(const Scalar& x, const Scalar& y).\n      * For fixed-size \\c 1x2 or \\c 2x1 vectors it is therefore recommended to use the default\n      * constructor Matrix() instead, especially when using one of the non standard\n      * \\c EIGEN_INITIALIZE_MATRICES_BY_{ZERO,\\c NAN} macros (see \\ref TopicPreprocessorDirectives).\n      */\n    EIGEN_DEVICE_FUNC\n    Matrix(Index rows, Index cols);\n    \n    /** \\brief Constructs an initialized 2D vector with given coefficients */\n    Matrix(const Scalar& x, const Scalar& y);\n    #endif\n\n    /** \\brief Constructs an initialized 3D vector with given coefficients */\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Matrix(const Scalar& x, const Scalar& y, const Scalar& z)\n    {\n      Base::_check_template_params();\n      EIGEN_STATIC_ASSERT_VECTOR_SPECIFIC_SIZE(Matrix, 3)\n      m_storage.data()[0] = x;\n      m_storage.data()[1] = y;\n      m_storage.data()[2] = z;\n    }\n    /** \\brief Constructs an initialized 4D vector with given coefficients */\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Matrix(const Scalar& x, const Scalar& y, const Scalar& z, const Scalar& w)\n    {\n      Base::_check_template_params();\n      EIGEN_STATIC_ASSERT_VECTOR_SPECIFIC_SIZE(Matrix, 4)\n      m_storage.data()[0] = x;\n      m_storage.data()[1] = y;\n      m_storage.data()[2] = z;\n      m_storage.data()[3] = w;\n    }\n\n\n    /** \\brief Copy constructor */\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Matrix(const Matrix& other) : Base(other)\n    { }\n\n    /** \\brief Copy constructor for generic expressions.\n      * \\sa MatrixBase::operator=(const EigenBase<OtherDerived>&)\n      */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Matrix(const EigenBase<OtherDerived> &other)\n      : Base(other.derived())\n    { }\n\n    EIGEN_DEVICE_FUNC inline Index innerStride() const { return 1; }\n    EIGEN_DEVICE_FUNC inline Index outerStride() const { return this->innerSize(); }\n\n    /////////// Geometry module ///////////\n\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    explicit Matrix(const RotationBase<OtherDerived,ColsAtCompileTime>& r);\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    Matrix& operator=(const RotationBase<OtherDerived,ColsAtCompileTime>& r);\n\n    // allow to extend Matrix outside Eigen\n    #ifdef EIGEN_MATRIX_PLUGIN\n    #include EIGEN_MATRIX_PLUGIN\n    #endif\n\n  protected:\n    template <typename Derived, typename OtherDerived, bool IsVector>\n    friend struct internal::conservative_resize_like_impl;\n\n    using Base::m_storage;\n};\n\n/** \\defgroup matrixtypedefs Global matrix typedefs\n  *\n  * \\ingroup Core_Module\n  *\n  * Eigen defines several typedef shortcuts for most common matrix and vector types.\n  *\n  * The general patterns are the following:\n  *\n  * \\c MatrixSizeType where \\c Size can be \\c 2,\\c 3,\\c 4 for fixed size square matrices or \\c X for dynamic size,\n  * and where \\c Type can be \\c i for integer, \\c f for float, \\c d for double, \\c cf for complex float, \\c cd\n  * for complex double.\n  *\n  * For example, \\c Matrix3d is a fixed-size 3x3 matrix type of doubles, and \\c MatrixXf is a dynamic-size matrix of floats.\n  *\n  * There are also \\c VectorSizeType and \\c RowVectorSizeType which are self-explanatory. For example, \\c Vector4cf is\n  * a fixed-size vector of 4 complex floats.\n  *\n  * \\sa class Matrix\n  */\n\n#define EIGEN_MAKE_TYPEDEFS(Type, TypeSuffix, Size, SizeSuffix)   \\\n/** \\ingroup matrixtypedefs */                                    \\\ntypedef Matrix<Type, Size, Size> Matrix##SizeSuffix##TypeSuffix;  \\\n/** \\ingroup matrixtypedefs */                                    \\\ntypedef Matrix<Type, Size, 1>    Vector##SizeSuffix##TypeSuffix;  \\\n/** \\ingroup matrixtypedefs */                                    \\\ntypedef Matrix<Type, 1, Size>    RowVector##SizeSuffix##TypeSuffix;\n\n#define EIGEN_MAKE_FIXED_TYPEDEFS(Type, TypeSuffix, Size)         \\\n/** \\ingroup matrixtypedefs */                                    \\\ntypedef Matrix<Type, Size, Dynamic> Matrix##Size##X##TypeSuffix;  \\\n/** \\ingroup matrixtypedefs */                                    \\\ntypedef Matrix<Type, Dynamic, Size> Matrix##X##Size##TypeSuffix;\n\n#define EIGEN_MAKE_TYPEDEFS_ALL_SIZES(Type, TypeSuffix) \\\nEIGEN_MAKE_TYPEDEFS(Type, TypeSuffix, 2, 2) \\\nEIGEN_MAKE_TYPEDEFS(Type, TypeSuffix, 3, 3) \\\nEIGEN_MAKE_TYPEDEFS(Type, TypeSuffix, 4, 4) \\\nEIGEN_MAKE_TYPEDEFS(Type, TypeSuffix, Dynamic, X) \\\nEIGEN_MAKE_FIXED_TYPEDEFS(Type, TypeSuffix, 2) \\\nEIGEN_MAKE_FIXED_TYPEDEFS(Type, TypeSuffix, 3) \\\nEIGEN_MAKE_FIXED_TYPEDEFS(Type, TypeSuffix, 4)\n\nEIGEN_MAKE_TYPEDEFS_ALL_SIZES(int,                  i)\nEIGEN_MAKE_TYPEDEFS_ALL_SIZES(float,                f)\nEIGEN_MAKE_TYPEDEFS_ALL_SIZES(double,               d)\nEIGEN_MAKE_TYPEDEFS_ALL_SIZES(std::complex<float>,  cf)\nEIGEN_MAKE_TYPEDEFS_ALL_SIZES(std::complex<double>, cd)\n\n#undef EIGEN_MAKE_TYPEDEFS_ALL_SIZES\n#undef EIGEN_MAKE_TYPEDEFS\n#undef EIGEN_MAKE_FIXED_TYPEDEFS\n\n} // end namespace Eigen\n\n#endif // EIGEN_MATRIX_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/MatrixBase.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2006-2009 Benoit Jacob <jacob.benoit.1@gmail.com>\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_MATRIXBASE_H\n#define EIGEN_MATRIXBASE_H\n\nnamespace Eigen {\n\n/** \\class MatrixBase\n  * \\ingroup Core_Module\n  *\n  * \\brief Base class for all dense matrices, vectors, and expressions\n  *\n  * This class is the base that is inherited by all matrix, vector, and related expression\n  * types. Most of the Eigen API is contained in this class, and its base classes. Other important\n  * classes for the Eigen API are Matrix, and VectorwiseOp.\n  *\n  * Note that some methods are defined in other modules such as the \\ref LU_Module LU module\n  * for all functions related to matrix inversions.\n  *\n  * \\tparam Derived is the derived type, e.g. a matrix type, or an expression, etc.\n  *\n  * When writing a function taking Eigen objects as argument, if you want your function\n  * to take as argument any matrix, vector, or expression, just let it take a\n  * MatrixBase argument. As an example, here is a function printFirstRow which, given\n  * a matrix, vector, or expression \\a x, prints the first row of \\a x.\n  *\n  * \\code\n    template<typename Derived>\n    void printFirstRow(const Eigen::MatrixBase<Derived>& x)\n    {\n      cout << x.row(0) << endl;\n    }\n  * \\endcode\n  *\n  * This class can be extended with the help of the plugin mechanism described on the page\n  * \\ref TopicCustomizing_Plugins by defining the preprocessor symbol \\c EIGEN_MATRIXBASE_PLUGIN.\n  *\n  * \\sa \\blank \\ref TopicClassHierarchy\n  */\ntemplate<typename Derived> class MatrixBase\n  : public DenseBase<Derived>\n{\n  public:\n#ifndef EIGEN_PARSED_BY_DOXYGEN\n    typedef MatrixBase StorageBaseType;\n    typedef typename internal::traits<Derived>::StorageKind StorageKind;\n    typedef typename internal::traits<Derived>::StorageIndex StorageIndex;\n    typedef typename internal::traits<Derived>::Scalar Scalar;\n    typedef typename internal::packet_traits<Scalar>::type PacketScalar;\n    typedef typename NumTraits<Scalar>::Real RealScalar;\n\n    typedef DenseBase<Derived> Base;\n    using Base::RowsAtCompileTime;\n    using Base::ColsAtCompileTime;\n    using Base::SizeAtCompileTime;\n    using Base::MaxRowsAtCompileTime;\n    using Base::MaxColsAtCompileTime;\n    using Base::MaxSizeAtCompileTime;\n    using Base::IsVectorAtCompileTime;\n    using Base::Flags;\n\n    using Base::derived;\n    using Base::const_cast_derived;\n    using Base::rows;\n    using Base::cols;\n    using Base::size;\n    using Base::coeff;\n    using Base::coeffRef;\n    using Base::lazyAssign;\n    using Base::eval;\n    using Base::operator+=;\n    using Base::operator-=;\n    using Base::operator*=;\n    using Base::operator/=;\n\n    typedef typename Base::CoeffReturnType CoeffReturnType;\n    typedef typename Base::ConstTransposeReturnType ConstTransposeReturnType;\n    typedef typename Base::RowXpr RowXpr;\n    typedef typename Base::ColXpr ColXpr;\n#endif // not EIGEN_PARSED_BY_DOXYGEN\n\n\n\n#ifndef EIGEN_PARSED_BY_DOXYGEN\n    /** type of the equivalent square matrix */\n    typedef Matrix<Scalar,EIGEN_SIZE_MAX(RowsAtCompileTime,ColsAtCompileTime),\n                          EIGEN_SIZE_MAX(RowsAtCompileTime,ColsAtCompileTime)> SquareMatrixType;\n#endif // not EIGEN_PARSED_BY_DOXYGEN\n\n    /** \\returns the size of the main diagonal, which is min(rows(),cols()).\n      * \\sa rows(), cols(), SizeAtCompileTime. */\n    EIGEN_DEVICE_FUNC\n    inline Index diagonalSize() const { return (numext::mini)(rows(),cols()); }\n\n    typedef typename Base::PlainObject PlainObject;\n\n#ifndef EIGEN_PARSED_BY_DOXYGEN\n    /** \\internal Represents a matrix with all coefficients equal to one another*/\n    typedef CwiseNullaryOp<internal::scalar_constant_op<Scalar>,PlainObject> ConstantReturnType;\n    /** \\internal the return type of MatrixBase::adjoint() */\n    typedef typename internal::conditional<NumTraits<Scalar>::IsComplex,\n                        CwiseUnaryOp<internal::scalar_conjugate_op<Scalar>, ConstTransposeReturnType>,\n                        ConstTransposeReturnType\n                     >::type AdjointReturnType;\n    /** \\internal Return type of eigenvalues() */\n    typedef Matrix<std::complex<RealScalar>, internal::traits<Derived>::ColsAtCompileTime, 1, ColMajor> EigenvaluesReturnType;\n    /** \\internal the return type of identity */\n    typedef CwiseNullaryOp<internal::scalar_identity_op<Scalar>,PlainObject> IdentityReturnType;\n    /** \\internal the return type of unit vectors */\n    typedef Block<const CwiseNullaryOp<internal::scalar_identity_op<Scalar>, SquareMatrixType>,\n                  internal::traits<Derived>::RowsAtCompileTime,\n                  internal::traits<Derived>::ColsAtCompileTime> BasisReturnType;\n#endif // not EIGEN_PARSED_BY_DOXYGEN\n\n#define EIGEN_CURRENT_STORAGE_BASE_CLASS Eigen::MatrixBase\n#define EIGEN_DOC_UNARY_ADDONS(X,Y)\n#   include \"../plugins/CommonCwiseUnaryOps.h\"\n#   include \"../plugins/CommonCwiseBinaryOps.h\"\n#   include \"../plugins/MatrixCwiseUnaryOps.h\"\n#   include \"../plugins/MatrixCwiseBinaryOps.h\"\n#   ifdef EIGEN_MATRIXBASE_PLUGIN\n#     include EIGEN_MATRIXBASE_PLUGIN\n#   endif\n#undef EIGEN_CURRENT_STORAGE_BASE_CLASS\n#undef EIGEN_DOC_UNARY_ADDONS\n\n    /** Special case of the template operator=, in order to prevent the compiler\n      * from generating a default operator= (issue hit with g++ 4.1)\n      */\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n    Derived& operator=(const MatrixBase& other);\n\n    // We cannot inherit here via Base::operator= since it is causing\n    // trouble with MSVC.\n\n    template <typename OtherDerived>\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n    Derived& operator=(const DenseBase<OtherDerived>& other);\n\n    template <typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    Derived& operator=(const EigenBase<OtherDerived>& other);\n\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    Derived& operator=(const ReturnByValue<OtherDerived>& other);\n\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n    Derived& operator+=(const MatrixBase<OtherDerived>& other);\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n    Derived& operator-=(const MatrixBase<OtherDerived>& other);\n\n#ifdef __CUDACC__\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    const Product<Derived,OtherDerived,LazyProduct>\n    operator*(const MatrixBase<OtherDerived> &other) const\n    { return this->lazyProduct(other); }\n#else\n\n    template<typename OtherDerived>\n    const Product<Derived,OtherDerived>\n    operator*(const MatrixBase<OtherDerived> &other) const;\n\n#endif\n\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    const Product<Derived,OtherDerived,LazyProduct>\n    lazyProduct(const MatrixBase<OtherDerived> &other) const;\n\n    template<typename OtherDerived>\n    Derived& operator*=(const EigenBase<OtherDerived>& other);\n\n    template<typename OtherDerived>\n    void applyOnTheLeft(const EigenBase<OtherDerived>& other);\n\n    template<typename OtherDerived>\n    void applyOnTheRight(const EigenBase<OtherDerived>& other);\n\n    template<typename DiagonalDerived>\n    EIGEN_DEVICE_FUNC\n    const Product<Derived, DiagonalDerived, LazyProduct>\n    operator*(const DiagonalBase<DiagonalDerived> &diagonal) const;\n\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    typename ScalarBinaryOpTraits<typename internal::traits<Derived>::Scalar,typename internal::traits<OtherDerived>::Scalar>::ReturnType\n    dot(const MatrixBase<OtherDerived>& other) const;\n\n    EIGEN_DEVICE_FUNC RealScalar squaredNorm() const;\n    EIGEN_DEVICE_FUNC RealScalar norm() const;\n    RealScalar stableNorm() const;\n    RealScalar blueNorm() const;\n    RealScalar hypotNorm() const;\n    EIGEN_DEVICE_FUNC const PlainObject normalized() const;\n    EIGEN_DEVICE_FUNC const PlainObject stableNormalized() const;\n    EIGEN_DEVICE_FUNC void normalize();\n    EIGEN_DEVICE_FUNC void stableNormalize();\n\n    EIGEN_DEVICE_FUNC const AdjointReturnType adjoint() const;\n    EIGEN_DEVICE_FUNC void adjointInPlace();\n\n    typedef Diagonal<Derived> DiagonalReturnType;\n    EIGEN_DEVICE_FUNC\n    DiagonalReturnType diagonal();\n\n    typedef typename internal::add_const<Diagonal<const Derived> >::type ConstDiagonalReturnType;\n    EIGEN_DEVICE_FUNC\n    ConstDiagonalReturnType diagonal() const;\n\n    template<int Index> struct DiagonalIndexReturnType { typedef Diagonal<Derived,Index> Type; };\n    template<int Index> struct ConstDiagonalIndexReturnType { typedef const Diagonal<const Derived,Index> Type; };\n\n    template<int Index>\n    EIGEN_DEVICE_FUNC\n    typename DiagonalIndexReturnType<Index>::Type diagonal();\n\n    template<int Index>\n    EIGEN_DEVICE_FUNC\n    typename ConstDiagonalIndexReturnType<Index>::Type diagonal() const;\n\n    typedef Diagonal<Derived,DynamicIndex> DiagonalDynamicIndexReturnType;\n    typedef typename internal::add_const<Diagonal<const Derived,DynamicIndex> >::type ConstDiagonalDynamicIndexReturnType;\n\n    EIGEN_DEVICE_FUNC\n    DiagonalDynamicIndexReturnType diagonal(Index index);\n    EIGEN_DEVICE_FUNC\n    ConstDiagonalDynamicIndexReturnType diagonal(Index index) const;\n\n    template<unsigned int Mode> struct TriangularViewReturnType { typedef TriangularView<Derived, Mode> Type; };\n    template<unsigned int Mode> struct ConstTriangularViewReturnType { typedef const TriangularView<const Derived, Mode> Type; };\n\n    template<unsigned int Mode>\n    EIGEN_DEVICE_FUNC\n    typename TriangularViewReturnType<Mode>::Type triangularView();\n    template<unsigned int Mode>\n    EIGEN_DEVICE_FUNC\n    typename ConstTriangularViewReturnType<Mode>::Type triangularView() const;\n\n    template<unsigned int UpLo> struct SelfAdjointViewReturnType { typedef SelfAdjointView<Derived, UpLo> Type; };\n    template<unsigned int UpLo> struct ConstSelfAdjointViewReturnType { typedef const SelfAdjointView<const Derived, UpLo> Type; };\n\n    template<unsigned int UpLo>\n    EIGEN_DEVICE_FUNC\n    typename SelfAdjointViewReturnType<UpLo>::Type selfadjointView();\n    template<unsigned int UpLo>\n    EIGEN_DEVICE_FUNC\n    typename ConstSelfAdjointViewReturnType<UpLo>::Type selfadjointView() const;\n\n    const SparseView<Derived> sparseView(const Scalar& m_reference = Scalar(0),\n                                         const typename NumTraits<Scalar>::Real& m_epsilon = NumTraits<Scalar>::dummy_precision()) const;\n    EIGEN_DEVICE_FUNC static const IdentityReturnType Identity();\n    EIGEN_DEVICE_FUNC static const IdentityReturnType Identity(Index rows, Index cols);\n    EIGEN_DEVICE_FUNC static const BasisReturnType Unit(Index size, Index i);\n    EIGEN_DEVICE_FUNC static const BasisReturnType Unit(Index i);\n    EIGEN_DEVICE_FUNC static const BasisReturnType UnitX();\n    EIGEN_DEVICE_FUNC static const BasisReturnType UnitY();\n    EIGEN_DEVICE_FUNC static const BasisReturnType UnitZ();\n    EIGEN_DEVICE_FUNC static const BasisReturnType UnitW();\n\n    EIGEN_DEVICE_FUNC\n    const DiagonalWrapper<const Derived> asDiagonal() const;\n    const PermutationWrapper<const Derived> asPermutation() const;\n\n    EIGEN_DEVICE_FUNC\n    Derived& setIdentity();\n    EIGEN_DEVICE_FUNC\n    Derived& setIdentity(Index rows, Index cols);\n\n    bool isIdentity(const RealScalar& prec = NumTraits<Scalar>::dummy_precision()) const;\n    bool isDiagonal(const RealScalar& prec = NumTraits<Scalar>::dummy_precision()) const;\n\n    bool isUpperTriangular(const RealScalar& prec = NumTraits<Scalar>::dummy_precision()) const;\n    bool isLowerTriangular(const RealScalar& prec = NumTraits<Scalar>::dummy_precision()) const;\n\n    template<typename OtherDerived>\n    bool isOrthogonal(const MatrixBase<OtherDerived>& other,\n                      const RealScalar& prec = NumTraits<Scalar>::dummy_precision()) const;\n    bool isUnitary(const RealScalar& prec = NumTraits<Scalar>::dummy_precision()) const;\n\n    /** \\returns true if each coefficients of \\c *this and \\a other are all exactly equal.\n      * \\warning When using floating point scalar values you probably should rather use a\n      *          fuzzy comparison such as isApprox()\n      * \\sa isApprox(), operator!= */\n    template<typename OtherDerived>\n    inline bool operator==(const MatrixBase<OtherDerived>& other) const\n    { return cwiseEqual(other).all(); }\n\n    /** \\returns true if at least one pair of coefficients of \\c *this and \\a other are not exactly equal to each other.\n      * \\warning When using floating point scalar values you probably should rather use a\n      *          fuzzy comparison such as isApprox()\n      * \\sa isApprox(), operator== */\n    template<typename OtherDerived>\n    inline bool operator!=(const MatrixBase<OtherDerived>& other) const\n    { return cwiseNotEqual(other).any(); }\n\n    NoAlias<Derived,Eigen::MatrixBase > noalias();\n\n    // TODO forceAlignedAccess is temporarily disabled\n    // Need to find a nicer workaround.\n    inline const Derived& forceAlignedAccess() const { return derived(); }\n    inline Derived& forceAlignedAccess() { return derived(); }\n    template<bool Enable> inline const Derived& forceAlignedAccessIf() const { return derived(); }\n    template<bool Enable> inline Derived& forceAlignedAccessIf() { return derived(); }\n\n    EIGEN_DEVICE_FUNC Scalar trace() const;\n\n    template<int p> EIGEN_DEVICE_FUNC RealScalar lpNorm() const;\n\n    EIGEN_DEVICE_FUNC MatrixBase<Derived>& matrix() { return *this; }\n    EIGEN_DEVICE_FUNC const MatrixBase<Derived>& matrix() const { return *this; }\n\n    /** \\returns an \\link Eigen::ArrayBase Array \\endlink expression of this matrix\n      * \\sa ArrayBase::matrix() */\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE ArrayWrapper<Derived> array() { return ArrayWrapper<Derived>(derived()); }\n    /** \\returns a const \\link Eigen::ArrayBase Array \\endlink expression of this matrix\n      * \\sa ArrayBase::matrix() */\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const ArrayWrapper<const Derived> array() const { return ArrayWrapper<const Derived>(derived()); }\n\n/////////// LU module ///////////\n\n    inline const FullPivLU<PlainObject> fullPivLu() const;\n    inline const PartialPivLU<PlainObject> partialPivLu() const;\n\n    inline const PartialPivLU<PlainObject> lu() const;\n\n    inline const Inverse<Derived> inverse() const;\n\n    template<typename ResultType>\n    inline void computeInverseAndDetWithCheck(\n      ResultType& inverse,\n      typename ResultType::Scalar& determinant,\n      bool& invertible,\n      const RealScalar& absDeterminantThreshold = NumTraits<Scalar>::dummy_precision()\n    ) const;\n    template<typename ResultType>\n    inline void computeInverseWithCheck(\n      ResultType& inverse,\n      bool& invertible,\n      const RealScalar& absDeterminantThreshold = NumTraits<Scalar>::dummy_precision()\n    ) const;\n    Scalar determinant() const;\n\n/////////// Cholesky module ///////////\n\n    inline const LLT<PlainObject>  llt() const;\n    inline const LDLT<PlainObject> ldlt() const;\n\n/////////// QR module ///////////\n\n    inline const HouseholderQR<PlainObject> householderQr() const;\n    inline const ColPivHouseholderQR<PlainObject> colPivHouseholderQr() const;\n    inline const FullPivHouseholderQR<PlainObject> fullPivHouseholderQr() const;\n    inline const CompleteOrthogonalDecomposition<PlainObject> completeOrthogonalDecomposition() const;\n\n/////////// Eigenvalues module ///////////\n\n    inline EigenvaluesReturnType eigenvalues() const;\n    inline RealScalar operatorNorm() const;\n\n/////////// SVD module ///////////\n\n    inline JacobiSVD<PlainObject> jacobiSvd(unsigned int computationOptions = 0) const;\n    inline BDCSVD<PlainObject>    bdcSvd(unsigned int computationOptions = 0) const;\n\n/////////// Geometry module ///////////\n\n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    /// \\internal helper struct to form the return type of the cross product\n    template<typename OtherDerived> struct cross_product_return_type {\n      typedef typename ScalarBinaryOpTraits<typename internal::traits<Derived>::Scalar,typename internal::traits<OtherDerived>::Scalar>::ReturnType Scalar;\n      typedef Matrix<Scalar,MatrixBase::RowsAtCompileTime,MatrixBase::ColsAtCompileTime> type;\n    };\n    #endif // EIGEN_PARSED_BY_DOXYGEN\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n#ifndef EIGEN_PARSED_BY_DOXYGEN\n    inline typename cross_product_return_type<OtherDerived>::type\n#else\n    inline PlainObject\n#endif\n    cross(const MatrixBase<OtherDerived>& other) const;\n\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    inline PlainObject cross3(const MatrixBase<OtherDerived>& other) const;\n\n    EIGEN_DEVICE_FUNC\n    inline PlainObject unitOrthogonal(void) const;\n\n    EIGEN_DEVICE_FUNC\n    inline Matrix<Scalar,3,1> eulerAngles(Index a0, Index a1, Index a2) const;\n\n    // put this as separate enum value to work around possible GCC 4.3 bug (?)\n    enum { HomogeneousReturnTypeDirection = ColsAtCompileTime==1&&RowsAtCompileTime==1 ? ((internal::traits<Derived>::Flags&RowMajorBit)==RowMajorBit ? Horizontal : Vertical)\n                                          : ColsAtCompileTime==1 ? Vertical : Horizontal };\n    typedef Homogeneous<Derived, HomogeneousReturnTypeDirection> HomogeneousReturnType;\n    EIGEN_DEVICE_FUNC\n    inline HomogeneousReturnType homogeneous() const;\n\n    enum {\n      SizeMinusOne = SizeAtCompileTime==Dynamic ? Dynamic : SizeAtCompileTime-1\n    };\n    typedef Block<const Derived,\n                  internal::traits<Derived>::ColsAtCompileTime==1 ? SizeMinusOne : 1,\n                  internal::traits<Derived>::ColsAtCompileTime==1 ? 1 : SizeMinusOne> ConstStartMinusOne;\n    typedef EIGEN_EXPR_BINARYOP_SCALAR_RETURN_TYPE(ConstStartMinusOne,Scalar,quotient) HNormalizedReturnType;\n    EIGEN_DEVICE_FUNC\n    inline const HNormalizedReturnType hnormalized() const;\n\n////////// Householder module ///////////\n\n    void makeHouseholderInPlace(Scalar& tau, RealScalar& beta);\n    template<typename EssentialPart>\n    void makeHouseholder(EssentialPart& essential,\n                         Scalar& tau, RealScalar& beta) const;\n    template<typename EssentialPart>\n    void applyHouseholderOnTheLeft(const EssentialPart& essential,\n                                   const Scalar& tau,\n                                   Scalar* workspace);\n    template<typename EssentialPart>\n    void applyHouseholderOnTheRight(const EssentialPart& essential,\n                                    const Scalar& tau,\n                                    Scalar* workspace);\n\n///////// Jacobi module /////////\n\n    template<typename OtherScalar>\n    void applyOnTheLeft(Index p, Index q, const JacobiRotation<OtherScalar>& j);\n    template<typename OtherScalar>\n    void applyOnTheRight(Index p, Index q, const JacobiRotation<OtherScalar>& j);\n\n///////// SparseCore module /////////\n\n    template<typename OtherDerived>\n    EIGEN_STRONG_INLINE const typename SparseMatrixBase<OtherDerived>::template CwiseProductDenseReturnType<Derived>::Type\n    cwiseProduct(const SparseMatrixBase<OtherDerived> &other) const\n    {\n      return other.cwiseProduct(derived());\n    }\n\n///////// MatrixFunctions module /////////\n\n    typedef typename internal::stem_function<Scalar>::type StemFunction;\n    const MatrixExponentialReturnValue<Derived> exp() const;\n    const MatrixFunctionReturnValue<Derived> matrixFunction(StemFunction f) const;\n    const MatrixFunctionReturnValue<Derived> cosh() const;\n    const MatrixFunctionReturnValue<Derived> sinh() const;\n    const MatrixFunctionReturnValue<Derived> cos() const;\n    const MatrixFunctionReturnValue<Derived> sin() const;\n    const MatrixSquareRootReturnValue<Derived> sqrt() const;\n    const MatrixLogarithmReturnValue<Derived> log() const;\n    const MatrixPowerReturnValue<Derived> pow(const RealScalar& p) const;\n    const MatrixComplexPowerReturnValue<Derived> pow(const std::complex<RealScalar>& p) const;\n\n  protected:\n    EIGEN_DEVICE_FUNC MatrixBase() : Base() {}\n\n  private:\n    EIGEN_DEVICE_FUNC explicit MatrixBase(int);\n    EIGEN_DEVICE_FUNC MatrixBase(int,int);\n    template<typename OtherDerived> EIGEN_DEVICE_FUNC explicit MatrixBase(const MatrixBase<OtherDerived>&);\n  protected:\n    // mixing arrays and matrices is not legal\n    template<typename OtherDerived> Derived& operator+=(const ArrayBase<OtherDerived>& )\n    {EIGEN_STATIC_ASSERT(std::ptrdiff_t(sizeof(typename OtherDerived::Scalar))==-1,YOU_CANNOT_MIX_ARRAYS_AND_MATRICES); return *this;}\n    // mixing arrays and matrices is not legal\n    template<typename OtherDerived> Derived& operator-=(const ArrayBase<OtherDerived>& )\n    {EIGEN_STATIC_ASSERT(std::ptrdiff_t(sizeof(typename OtherDerived::Scalar))==-1,YOU_CANNOT_MIX_ARRAYS_AND_MATRICES); return *this;}\n};\n\n\n/***************************************************************************\n* Implementation of matrix base methods\n***************************************************************************/\n\n/** replaces \\c *this by \\c *this * \\a other.\n  *\n  * \\returns a reference to \\c *this\n  *\n  * Example: \\include MatrixBase_applyOnTheRight.cpp\n  * Output: \\verbinclude MatrixBase_applyOnTheRight.out\n  */\ntemplate<typename Derived>\ntemplate<typename OtherDerived>\ninline Derived&\nMatrixBase<Derived>::operator*=(const EigenBase<OtherDerived> &other)\n{\n  other.derived().applyThisOnTheRight(derived());\n  return derived();\n}\n\n/** replaces \\c *this by \\c *this * \\a other. It is equivalent to MatrixBase::operator*=().\n  *\n  * Example: \\include MatrixBase_applyOnTheRight.cpp\n  * Output: \\verbinclude MatrixBase_applyOnTheRight.out\n  */\ntemplate<typename Derived>\ntemplate<typename OtherDerived>\ninline void MatrixBase<Derived>::applyOnTheRight(const EigenBase<OtherDerived> &other)\n{\n  other.derived().applyThisOnTheRight(derived());\n}\n\n/** replaces \\c *this by \\a other * \\c *this.\n  *\n  * Example: \\include MatrixBase_applyOnTheLeft.cpp\n  * Output: \\verbinclude MatrixBase_applyOnTheLeft.out\n  */\ntemplate<typename Derived>\ntemplate<typename OtherDerived>\ninline void MatrixBase<Derived>::applyOnTheLeft(const EigenBase<OtherDerived> &other)\n{\n  other.derived().applyThisOnTheLeft(derived());\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_MATRIXBASE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/NestByValue.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2006-2008 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_NESTBYVALUE_H\n#define EIGEN_NESTBYVALUE_H\n\nnamespace Eigen {\n\nnamespace internal {\ntemplate<typename ExpressionType>\nstruct traits<NestByValue<ExpressionType> > : public traits<ExpressionType>\n{};\n}\n\n/** \\class NestByValue\n  * \\ingroup Core_Module\n  *\n  * \\brief Expression which must be nested by value\n  *\n  * \\tparam ExpressionType the type of the object of which we are requiring nesting-by-value\n  *\n  * This class is the return type of MatrixBase::nestByValue()\n  * and most of the time this is the only way it is used.\n  *\n  * \\sa MatrixBase::nestByValue()\n  */\ntemplate<typename ExpressionType> class NestByValue\n  : public internal::dense_xpr_base< NestByValue<ExpressionType> >::type\n{\n  public:\n\n    typedef typename internal::dense_xpr_base<NestByValue>::type Base;\n    EIGEN_DENSE_PUBLIC_INTERFACE(NestByValue)\n\n    EIGEN_DEVICE_FUNC explicit inline NestByValue(const ExpressionType& matrix) : m_expression(matrix) {}\n\n    EIGEN_DEVICE_FUNC inline Index rows() const { return m_expression.rows(); }\n    EIGEN_DEVICE_FUNC inline Index cols() const { return m_expression.cols(); }\n    EIGEN_DEVICE_FUNC inline Index outerStride() const { return m_expression.outerStride(); }\n    EIGEN_DEVICE_FUNC inline Index innerStride() const { return m_expression.innerStride(); }\n\n    EIGEN_DEVICE_FUNC inline const CoeffReturnType coeff(Index row, Index col) const\n    {\n      return m_expression.coeff(row, col);\n    }\n\n    EIGEN_DEVICE_FUNC inline Scalar& coeffRef(Index row, Index col)\n    {\n      return m_expression.const_cast_derived().coeffRef(row, col);\n    }\n\n    EIGEN_DEVICE_FUNC inline const CoeffReturnType coeff(Index index) const\n    {\n      return m_expression.coeff(index);\n    }\n\n    EIGEN_DEVICE_FUNC inline Scalar& coeffRef(Index index)\n    {\n      return m_expression.const_cast_derived().coeffRef(index);\n    }\n\n    template<int LoadMode>\n    inline const PacketScalar packet(Index row, Index col) const\n    {\n      return m_expression.template packet<LoadMode>(row, col);\n    }\n\n    template<int LoadMode>\n    inline void writePacket(Index row, Index col, const PacketScalar& x)\n    {\n      m_expression.const_cast_derived().template writePacket<LoadMode>(row, col, x);\n    }\n\n    template<int LoadMode>\n    inline const PacketScalar packet(Index index) const\n    {\n      return m_expression.template packet<LoadMode>(index);\n    }\n\n    template<int LoadMode>\n    inline void writePacket(Index index, const PacketScalar& x)\n    {\n      m_expression.const_cast_derived().template writePacket<LoadMode>(index, x);\n    }\n\n    EIGEN_DEVICE_FUNC operator const ExpressionType&() const { return m_expression; }\n\n  protected:\n    const ExpressionType m_expression;\n};\n\n/** \\returns an expression of the temporary version of *this.\n  */\ntemplate<typename Derived>\ninline const NestByValue<Derived>\nDenseBase<Derived>::nestByValue() const\n{\n  return NestByValue<Derived>(derived());\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_NESTBYVALUE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/NoAlias.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_NOALIAS_H\n#define EIGEN_NOALIAS_H\n\nnamespace Eigen {\n\n/** \\class NoAlias\n  * \\ingroup Core_Module\n  *\n  * \\brief Pseudo expression providing an operator = assuming no aliasing\n  *\n  * \\tparam ExpressionType the type of the object on which to do the lazy assignment\n  *\n  * This class represents an expression with special assignment operators\n  * assuming no aliasing between the target expression and the source expression.\n  * More precisely it alloas to bypass the EvalBeforeAssignBit flag of the source expression.\n  * It is the return type of MatrixBase::noalias()\n  * and most of the time this is the only way it is used.\n  *\n  * \\sa MatrixBase::noalias()\n  */\ntemplate<typename ExpressionType, template <typename> class StorageBase>\nclass NoAlias\n{\n  public:\n    typedef typename ExpressionType::Scalar Scalar;\n    \n    explicit NoAlias(ExpressionType& expression) : m_expression(expression) {}\n    \n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE ExpressionType& operator=(const StorageBase<OtherDerived>& other)\n    {\n      call_assignment_no_alias(m_expression, other.derived(), internal::assign_op<Scalar,typename OtherDerived::Scalar>());\n      return m_expression;\n    }\n    \n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE ExpressionType& operator+=(const StorageBase<OtherDerived>& other)\n    {\n      call_assignment_no_alias(m_expression, other.derived(), internal::add_assign_op<Scalar,typename OtherDerived::Scalar>());\n      return m_expression;\n    }\n    \n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE ExpressionType& operator-=(const StorageBase<OtherDerived>& other)\n    {\n      call_assignment_no_alias(m_expression, other.derived(), internal::sub_assign_op<Scalar,typename OtherDerived::Scalar>());\n      return m_expression;\n    }\n\n    EIGEN_DEVICE_FUNC\n    ExpressionType& expression() const\n    {\n      return m_expression;\n    }\n\n  protected:\n    ExpressionType& m_expression;\n};\n\n/** \\returns a pseudo expression of \\c *this with an operator= assuming\n  * no aliasing between \\c *this and the source expression.\n  *\n  * More precisely, noalias() allows to bypass the EvalBeforeAssignBit flag.\n  * Currently, even though several expressions may alias, only product\n  * expressions have this flag. Therefore, noalias() is only usefull when\n  * the source expression contains a matrix product.\n  *\n  * Here are some examples where noalias is usefull:\n  * \\code\n  * D.noalias()  = A * B;\n  * D.noalias() += A.transpose() * B;\n  * D.noalias() -= 2 * A * B.adjoint();\n  * \\endcode\n  *\n  * On the other hand the following example will lead to a \\b wrong result:\n  * \\code\n  * A.noalias() = A * B;\n  * \\endcode\n  * because the result matrix A is also an operand of the matrix product. Therefore,\n  * there is no alternative than evaluating A * B in a temporary, that is the default\n  * behavior when you write:\n  * \\code\n  * A = A * B;\n  * \\endcode\n  *\n  * \\sa class NoAlias\n  */\ntemplate<typename Derived>\nNoAlias<Derived,MatrixBase> MatrixBase<Derived>::noalias()\n{\n  return NoAlias<Derived, Eigen::MatrixBase >(derived());\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_NOALIAS_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/NumTraits.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2006-2010 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_NUMTRAITS_H\n#define EIGEN_NUMTRAITS_H\n\nnamespace Eigen {\n\nnamespace internal {\n\n// default implementation of digits10(), based on numeric_limits if specialized,\n// 0 for integer types, and log10(epsilon()) otherwise.\ntemplate< typename T,\n          bool use_numeric_limits = std::numeric_limits<T>::is_specialized,\n          bool is_integer = NumTraits<T>::IsInteger>\nstruct default_digits10_impl\n{\n  static int run() { return std::numeric_limits<T>::digits10; }\n};\n\ntemplate<typename T>\nstruct default_digits10_impl<T,false,false> // Floating point\n{\n  static int run() {\n    using std::log10;\n    using std::ceil;\n    typedef typename NumTraits<T>::Real Real;\n    return int(ceil(-log10(NumTraits<Real>::epsilon())));\n  }\n};\n\ntemplate<typename T>\nstruct default_digits10_impl<T,false,true> // Integer\n{\n  static int run() { return 0; }\n};\n\n} // end namespace internal\n\n/** \\class NumTraits\n  * \\ingroup Core_Module\n  *\n  * \\brief Holds information about the various numeric (i.e. scalar) types allowed by Eigen.\n  *\n  * \\tparam T the numeric type at hand\n  *\n  * This class stores enums, typedefs and static methods giving information about a numeric type.\n  *\n  * The provided data consists of:\n  * \\li A typedef \\c Real, giving the \"real part\" type of \\a T. If \\a T is already real,\n  *     then \\c Real is just a typedef to \\a T. If \\a T is \\c std::complex<U> then \\c Real\n  *     is a typedef to \\a U.\n  * \\li A typedef \\c NonInteger, giving the type that should be used for operations producing non-integral values,\n  *     such as quotients, square roots, etc. If \\a T is a floating-point type, then this typedef just gives\n  *     \\a T again. Note however that many Eigen functions such as internal::sqrt simply refuse to\n  *     take integers. Outside of a few cases, Eigen doesn't do automatic type promotion. Thus, this typedef is\n  *     only intended as a helper for code that needs to explicitly promote types.\n  * \\li A typedef \\c Literal giving the type to use for numeric literals such as \"2\" or \"0.5\". For instance, for \\c std::complex<U>, Literal is defined as \\c U.\n  *     Of course, this type must be fully compatible with \\a T. In doubt, just use \\a T here.\n  * \\li A typedef \\a Nested giving the type to use to nest a value inside of the expression tree. If you don't know what\n  *     this means, just use \\a T here.\n  * \\li An enum value \\a IsComplex. It is equal to 1 if \\a T is a \\c std::complex\n  *     type, and to 0 otherwise.\n  * \\li An enum value \\a IsInteger. It is equal to \\c 1 if \\a T is an integer type such as \\c int,\n  *     and to \\c 0 otherwise.\n  * \\li Enum values ReadCost, AddCost and MulCost representing a rough estimate of the number of CPU cycles needed\n  *     to by move / add / mul instructions respectively, assuming the data is already stored in CPU registers.\n  *     Stay vague here. No need to do architecture-specific stuff.\n  * \\li An enum value \\a IsSigned. It is equal to \\c 1 if \\a T is a signed type and to 0 if \\a T is unsigned.\n  * \\li An enum value \\a RequireInitialization. It is equal to \\c 1 if the constructor of the numeric type \\a T must\n  *     be called, and to 0 if it is safe not to call it. Default is 0 if \\a T is an arithmetic type, and 1 otherwise.\n  * \\li An epsilon() function which, unlike <a href=\"http://en.cppreference.com/w/cpp/types/numeric_limits/epsilon\">std::numeric_limits::epsilon()</a>,\n  *     it returns a \\a Real instead of a \\a T.\n  * \\li A dummy_precision() function returning a weak epsilon value. It is mainly used as a default\n  *     value by the fuzzy comparison operators.\n  * \\li highest() and lowest() functions returning the highest and lowest possible values respectively.\n  * \\li digits10() function returning the number of decimal digits that can be represented without change. This is\n  *     the analogue of <a href=\"http://en.cppreference.com/w/cpp/types/numeric_limits/digits10\">std::numeric_limits<T>::digits10</a>\n  *     which is used as the default implementation if specialized.\n  */\n\ntemplate<typename T> struct GenericNumTraits\n{\n  enum {\n    IsInteger = std::numeric_limits<T>::is_integer,\n    IsSigned = std::numeric_limits<T>::is_signed,\n    IsComplex = 0,\n    RequireInitialization = internal::is_arithmetic<T>::value ? 0 : 1,\n    ReadCost = 1,\n    AddCost = 1,\n    MulCost = 1\n  };\n\n  typedef T Real;\n  typedef typename internal::conditional<\n                     IsInteger,\n                     typename internal::conditional<sizeof(T)<=2, float, double>::type,\n                     T\n                   >::type NonInteger;\n  typedef T Nested;\n  typedef T Literal;\n\n  EIGEN_DEVICE_FUNC\n  static inline Real epsilon()\n  {\n    return numext::numeric_limits<T>::epsilon();\n  }\n\n  EIGEN_DEVICE_FUNC\n  static inline int digits10()\n  {\n    return internal::default_digits10_impl<T>::run();\n  }\n\n  EIGEN_DEVICE_FUNC\n  static inline Real dummy_precision()\n  {\n    // make sure to override this for floating-point types\n    return Real(0);\n  }\n\n\n  EIGEN_DEVICE_FUNC\n  static inline T highest() {\n    return (numext::numeric_limits<T>::max)();\n  }\n\n  EIGEN_DEVICE_FUNC\n  static inline T lowest()  {\n    return IsInteger ? (numext::numeric_limits<T>::min)() : (-(numext::numeric_limits<T>::max)());\n  }\n\n  EIGEN_DEVICE_FUNC\n  static inline T infinity() {\n    return numext::numeric_limits<T>::infinity();\n  }\n\n  EIGEN_DEVICE_FUNC\n  static inline T quiet_NaN() {\n    return numext::numeric_limits<T>::quiet_NaN();\n  }\n};\n\ntemplate<typename T> struct NumTraits : GenericNumTraits<T>\n{};\n\ntemplate<> struct NumTraits<float>\n  : GenericNumTraits<float>\n{\n  EIGEN_DEVICE_FUNC\n  static inline float dummy_precision() { return 1e-5f; }\n};\n\ntemplate<> struct NumTraits<double> : GenericNumTraits<double>\n{\n  EIGEN_DEVICE_FUNC\n  static inline double dummy_precision() { return 1e-12; }\n};\n\ntemplate<> struct NumTraits<long double>\n  : GenericNumTraits<long double>\n{\n  static inline long double dummy_precision() { return 1e-15l; }\n};\n\ntemplate<typename _Real> struct NumTraits<std::complex<_Real> >\n  : GenericNumTraits<std::complex<_Real> >\n{\n  typedef _Real Real;\n  typedef typename NumTraits<_Real>::Literal Literal;\n  enum {\n    IsComplex = 1,\n    RequireInitialization = NumTraits<_Real>::RequireInitialization,\n    ReadCost = 2 * NumTraits<_Real>::ReadCost,\n    AddCost = 2 * NumTraits<Real>::AddCost,\n    MulCost = 4 * NumTraits<Real>::MulCost + 2 * NumTraits<Real>::AddCost\n  };\n\n  EIGEN_DEVICE_FUNC\n  static inline Real epsilon() { return NumTraits<Real>::epsilon(); }\n  EIGEN_DEVICE_FUNC\n  static inline Real dummy_precision() { return NumTraits<Real>::dummy_precision(); }\n  EIGEN_DEVICE_FUNC\n  static inline int digits10() { return NumTraits<Real>::digits10(); }\n};\n\ntemplate<typename Scalar, int Rows, int Cols, int Options, int MaxRows, int MaxCols>\nstruct NumTraits<Array<Scalar, Rows, Cols, Options, MaxRows, MaxCols> >\n{\n  typedef Array<Scalar, Rows, Cols, Options, MaxRows, MaxCols> ArrayType;\n  typedef typename NumTraits<Scalar>::Real RealScalar;\n  typedef Array<RealScalar, Rows, Cols, Options, MaxRows, MaxCols> Real;\n  typedef typename NumTraits<Scalar>::NonInteger NonIntegerScalar;\n  typedef Array<NonIntegerScalar, Rows, Cols, Options, MaxRows, MaxCols> NonInteger;\n  typedef ArrayType & Nested;\n  typedef typename NumTraits<Scalar>::Literal Literal;\n\n  enum {\n    IsComplex = NumTraits<Scalar>::IsComplex,\n    IsInteger = NumTraits<Scalar>::IsInteger,\n    IsSigned  = NumTraits<Scalar>::IsSigned,\n    RequireInitialization = 1,\n    ReadCost = ArrayType::SizeAtCompileTime==Dynamic ? HugeCost : ArrayType::SizeAtCompileTime * NumTraits<Scalar>::ReadCost,\n    AddCost  = ArrayType::SizeAtCompileTime==Dynamic ? HugeCost : ArrayType::SizeAtCompileTime * NumTraits<Scalar>::AddCost,\n    MulCost  = ArrayType::SizeAtCompileTime==Dynamic ? HugeCost : ArrayType::SizeAtCompileTime * NumTraits<Scalar>::MulCost\n  };\n\n  EIGEN_DEVICE_FUNC\n  static inline RealScalar epsilon() { return NumTraits<RealScalar>::epsilon(); }\n  EIGEN_DEVICE_FUNC\n  static inline RealScalar dummy_precision() { return NumTraits<RealScalar>::dummy_precision(); }\n};\n\ntemplate<> struct NumTraits<std::string>\n  : GenericNumTraits<std::string>\n{\n  enum {\n    RequireInitialization = 1,\n    ReadCost = HugeCost,\n    AddCost  = HugeCost,\n    MulCost  = HugeCost\n  };\n\n  static inline int digits10() { return 0; }\n\nprivate:\n  static inline std::string epsilon();\n  static inline std::string dummy_precision();\n  static inline std::string lowest();\n  static inline std::string highest();\n  static inline std::string infinity();\n  static inline std::string quiet_NaN();\n};\n\n// Empty specialization for void to allow template specialization based on NumTraits<T>::Real with T==void and SFINAE.\ntemplate<> struct NumTraits<void> {};\n\n} // end namespace Eigen\n\n#endif // EIGEN_NUMTRAITS_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/PermutationMatrix.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009 Benoit Jacob <jacob.benoit.1@gmail.com>\n// Copyright (C) 2009-2015 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_PERMUTATIONMATRIX_H\n#define EIGEN_PERMUTATIONMATRIX_H\n\nnamespace Eigen { \n\nnamespace internal {\n\nenum PermPermProduct_t {PermPermProduct};\n\n} // end namespace internal\n\n/** \\class PermutationBase\n  * \\ingroup Core_Module\n  *\n  * \\brief Base class for permutations\n  *\n  * \\tparam Derived the derived class\n  *\n  * This class is the base class for all expressions representing a permutation matrix,\n  * internally stored as a vector of integers.\n  * The convention followed here is that if \\f$ \\sigma \\f$ is a permutation, the corresponding permutation matrix\n  * \\f$ P_\\sigma \\f$ is such that if \\f$ (e_1,\\ldots,e_p) \\f$ is the canonical basis, we have:\n  *  \\f[ P_\\sigma(e_i) = e_{\\sigma(i)}. \\f]\n  * This convention ensures that for any two permutations \\f$ \\sigma, \\tau \\f$, we have:\n  *  \\f[ P_{\\sigma\\circ\\tau} = P_\\sigma P_\\tau. \\f]\n  *\n  * Permutation matrices are square and invertible.\n  *\n  * Notice that in addition to the member functions and operators listed here, there also are non-member\n  * operator* to multiply any kind of permutation object with any kind of matrix expression (MatrixBase)\n  * on either side.\n  *\n  * \\sa class PermutationMatrix, class PermutationWrapper\n  */\ntemplate<typename Derived>\nclass PermutationBase : public EigenBase<Derived>\n{\n    typedef internal::traits<Derived> Traits;\n    typedef EigenBase<Derived> Base;\n  public:\n\n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    typedef typename Traits::IndicesType IndicesType;\n    enum {\n      Flags = Traits::Flags,\n      RowsAtCompileTime = Traits::RowsAtCompileTime,\n      ColsAtCompileTime = Traits::ColsAtCompileTime,\n      MaxRowsAtCompileTime = Traits::MaxRowsAtCompileTime,\n      MaxColsAtCompileTime = Traits::MaxColsAtCompileTime\n    };\n    typedef typename Traits::StorageIndex StorageIndex;\n    typedef Matrix<StorageIndex,RowsAtCompileTime,ColsAtCompileTime,0,MaxRowsAtCompileTime,MaxColsAtCompileTime>\n            DenseMatrixType;\n    typedef PermutationMatrix<IndicesType::SizeAtCompileTime,IndicesType::MaxSizeAtCompileTime,StorageIndex>\n            PlainPermutationType;\n    typedef PlainPermutationType PlainObject;\n    using Base::derived;\n    typedef Inverse<Derived> InverseReturnType;\n    typedef void Scalar;\n    #endif\n\n    /** Copies the other permutation into *this */\n    template<typename OtherDerived>\n    Derived& operator=(const PermutationBase<OtherDerived>& other)\n    {\n      indices() = other.indices();\n      return derived();\n    }\n\n    /** Assignment from the Transpositions \\a tr */\n    template<typename OtherDerived>\n    Derived& operator=(const TranspositionsBase<OtherDerived>& tr)\n    {\n      setIdentity(tr.size());\n      for(Index k=size()-1; k>=0; --k)\n        applyTranspositionOnTheRight(k,tr.coeff(k));\n      return derived();\n    }\n\n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    /** This is a special case of the templated operator=. Its purpose is to\n      * prevent a default operator= from hiding the templated operator=.\n      */\n    Derived& operator=(const PermutationBase& other)\n    {\n      indices() = other.indices();\n      return derived();\n    }\n    #endif\n\n    /** \\returns the number of rows */\n    inline Index rows() const { return Index(indices().size()); }\n\n    /** \\returns the number of columns */\n    inline Index cols() const { return Index(indices().size()); }\n\n    /** \\returns the size of a side of the respective square matrix, i.e., the number of indices */\n    inline Index size() const { return Index(indices().size()); }\n\n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    template<typename DenseDerived>\n    void evalTo(MatrixBase<DenseDerived>& other) const\n    {\n      other.setZero();\n      for (Index i=0; i<rows(); ++i)\n        other.coeffRef(indices().coeff(i),i) = typename DenseDerived::Scalar(1);\n    }\n    #endif\n\n    /** \\returns a Matrix object initialized from this permutation matrix. Notice that it\n      * is inefficient to return this Matrix object by value. For efficiency, favor using\n      * the Matrix constructor taking EigenBase objects.\n      */\n    DenseMatrixType toDenseMatrix() const\n    {\n      return derived();\n    }\n\n    /** const version of indices(). */\n    const IndicesType& indices() const { return derived().indices(); }\n    /** \\returns a reference to the stored array representing the permutation. */\n    IndicesType& indices() { return derived().indices(); }\n\n    /** Resizes to given size.\n      */\n    inline void resize(Index newSize)\n    {\n      indices().resize(newSize);\n    }\n\n    /** Sets *this to be the identity permutation matrix */\n    void setIdentity()\n    {\n      StorageIndex n = StorageIndex(size());\n      for(StorageIndex i = 0; i < n; ++i)\n        indices().coeffRef(i) = i;\n    }\n\n    /** Sets *this to be the identity permutation matrix of given size.\n      */\n    void setIdentity(Index newSize)\n    {\n      resize(newSize);\n      setIdentity();\n    }\n\n    /** Multiplies *this by the transposition \\f$(ij)\\f$ on the left.\n      *\n      * \\returns a reference to *this.\n      *\n      * \\warning This is much slower than applyTranspositionOnTheRight(Index,Index):\n      * this has linear complexity and requires a lot of branching.\n      *\n      * \\sa applyTranspositionOnTheRight(Index,Index)\n      */\n    Derived& applyTranspositionOnTheLeft(Index i, Index j)\n    {\n      eigen_assert(i>=0 && j>=0 && i<size() && j<size());\n      for(Index k = 0; k < size(); ++k)\n      {\n        if(indices().coeff(k) == i) indices().coeffRef(k) = StorageIndex(j);\n        else if(indices().coeff(k) == j) indices().coeffRef(k) = StorageIndex(i);\n      }\n      return derived();\n    }\n\n    /** Multiplies *this by the transposition \\f$(ij)\\f$ on the right.\n      *\n      * \\returns a reference to *this.\n      *\n      * This is a fast operation, it only consists in swapping two indices.\n      *\n      * \\sa applyTranspositionOnTheLeft(Index,Index)\n      */\n    Derived& applyTranspositionOnTheRight(Index i, Index j)\n    {\n      eigen_assert(i>=0 && j>=0 && i<size() && j<size());\n      std::swap(indices().coeffRef(i), indices().coeffRef(j));\n      return derived();\n    }\n\n    /** \\returns the inverse permutation matrix.\n      *\n      * \\note \\blank \\note_try_to_help_rvo\n      */\n    inline InverseReturnType inverse() const\n    { return InverseReturnType(derived()); }\n    /** \\returns the tranpose permutation matrix.\n      *\n      * \\note \\blank \\note_try_to_help_rvo\n      */\n    inline InverseReturnType transpose() const\n    { return InverseReturnType(derived()); }\n\n    /**** multiplication helpers to hopefully get RVO ****/\n\n  \n#ifndef EIGEN_PARSED_BY_DOXYGEN\n  protected:\n    template<typename OtherDerived>\n    void assignTranspose(const PermutationBase<OtherDerived>& other)\n    {\n      for (Index i=0; i<rows();++i) indices().coeffRef(other.indices().coeff(i)) = i;\n    }\n    template<typename Lhs,typename Rhs>\n    void assignProduct(const Lhs& lhs, const Rhs& rhs)\n    {\n      eigen_assert(lhs.cols() == rhs.rows());\n      for (Index i=0; i<rows();++i) indices().coeffRef(i) = lhs.indices().coeff(rhs.indices().coeff(i));\n    }\n#endif\n\n  public:\n\n    /** \\returns the product permutation matrix.\n      *\n      * \\note \\blank \\note_try_to_help_rvo\n      */\n    template<typename Other>\n    inline PlainPermutationType operator*(const PermutationBase<Other>& other) const\n    { return PlainPermutationType(internal::PermPermProduct, derived(), other.derived()); }\n\n    /** \\returns the product of a permutation with another inverse permutation.\n      *\n      * \\note \\blank \\note_try_to_help_rvo\n      */\n    template<typename Other>\n    inline PlainPermutationType operator*(const InverseImpl<Other,PermutationStorage>& other) const\n    { return PlainPermutationType(internal::PermPermProduct, *this, other.eval()); }\n\n    /** \\returns the product of an inverse permutation with another permutation.\n      *\n      * \\note \\blank \\note_try_to_help_rvo\n      */\n    template<typename Other> friend\n    inline PlainPermutationType operator*(const InverseImpl<Other, PermutationStorage>& other, const PermutationBase& perm)\n    { return PlainPermutationType(internal::PermPermProduct, other.eval(), perm); }\n    \n    /** \\returns the determinant of the permutation matrix, which is either 1 or -1 depending on the parity of the permutation.\n      *\n      * This function is O(\\c n) procedure allocating a buffer of \\c n booleans.\n      */\n    Index determinant() const\n    {\n      Index res = 1;\n      Index n = size();\n      Matrix<bool,RowsAtCompileTime,1,0,MaxRowsAtCompileTime> mask(n);\n      mask.fill(false);\n      Index r = 0;\n      while(r < n)\n      {\n        // search for the next seed\n        while(r<n && mask[r]) r++;\n        if(r>=n)\n          break;\n        // we got one, let's follow it until we are back to the seed\n        Index k0 = r++;\n        mask.coeffRef(k0) = true;\n        for(Index k=indices().coeff(k0); k!=k0; k=indices().coeff(k))\n        {\n          mask.coeffRef(k) = true;\n          res = -res;\n        }\n      }\n      return res;\n    }\n\n  protected:\n\n};\n\nnamespace internal {\ntemplate<int SizeAtCompileTime, int MaxSizeAtCompileTime, typename _StorageIndex>\nstruct traits<PermutationMatrix<SizeAtCompileTime, MaxSizeAtCompileTime, _StorageIndex> >\n : traits<Matrix<_StorageIndex,SizeAtCompileTime,SizeAtCompileTime,0,MaxSizeAtCompileTime,MaxSizeAtCompileTime> >\n{\n  typedef PermutationStorage StorageKind;\n  typedef Matrix<_StorageIndex, SizeAtCompileTime, 1, 0, MaxSizeAtCompileTime, 1> IndicesType;\n  typedef _StorageIndex StorageIndex;\n  typedef void Scalar;\n};\n}\n\n/** \\class PermutationMatrix\n  * \\ingroup Core_Module\n  *\n  * \\brief Permutation matrix\n  *\n  * \\tparam SizeAtCompileTime the number of rows/cols, or Dynamic\n  * \\tparam MaxSizeAtCompileTime the maximum number of rows/cols, or Dynamic. This optional parameter defaults to SizeAtCompileTime. Most of the time, you should not have to specify it.\n  * \\tparam _StorageIndex the integer type of the indices\n  *\n  * This class represents a permutation matrix, internally stored as a vector of integers.\n  *\n  * \\sa class PermutationBase, class PermutationWrapper, class DiagonalMatrix\n  */\ntemplate<int SizeAtCompileTime, int MaxSizeAtCompileTime, typename _StorageIndex>\nclass PermutationMatrix : public PermutationBase<PermutationMatrix<SizeAtCompileTime, MaxSizeAtCompileTime, _StorageIndex> >\n{\n    typedef PermutationBase<PermutationMatrix> Base;\n    typedef internal::traits<PermutationMatrix> Traits;\n  public:\n\n    typedef const PermutationMatrix& Nested;\n\n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    typedef typename Traits::IndicesType IndicesType;\n    typedef typename Traits::StorageIndex StorageIndex;\n    #endif\n\n    inline PermutationMatrix()\n    {}\n\n    /** Constructs an uninitialized permutation matrix of given size.\n      */\n    explicit inline PermutationMatrix(Index size) : m_indices(size)\n    {\n      eigen_internal_assert(size <= NumTraits<StorageIndex>::highest());\n    }\n\n    /** Copy constructor. */\n    template<typename OtherDerived>\n    inline PermutationMatrix(const PermutationBase<OtherDerived>& other)\n      : m_indices(other.indices()) {}\n\n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    /** Standard copy constructor. Defined only to prevent a default copy constructor\n      * from hiding the other templated constructor */\n    inline PermutationMatrix(const PermutationMatrix& other) : m_indices(other.indices()) {}\n    #endif\n\n    /** Generic constructor from expression of the indices. The indices\n      * array has the meaning that the permutations sends each integer i to indices[i].\n      *\n      * \\warning It is your responsibility to check that the indices array that you passes actually\n      * describes a permutation, i.e., each value between 0 and n-1 occurs exactly once, where n is the\n      * array's size.\n      */\n    template<typename Other>\n    explicit inline PermutationMatrix(const MatrixBase<Other>& indices) : m_indices(indices)\n    {}\n\n    /** Convert the Transpositions \\a tr to a permutation matrix */\n    template<typename Other>\n    explicit PermutationMatrix(const TranspositionsBase<Other>& tr)\n      : m_indices(tr.size())\n    {\n      *this = tr;\n    }\n\n    /** Copies the other permutation into *this */\n    template<typename Other>\n    PermutationMatrix& operator=(const PermutationBase<Other>& other)\n    {\n      m_indices = other.indices();\n      return *this;\n    }\n\n    /** Assignment from the Transpositions \\a tr */\n    template<typename Other>\n    PermutationMatrix& operator=(const TranspositionsBase<Other>& tr)\n    {\n      return Base::operator=(tr.derived());\n    }\n\n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    /** This is a special case of the templated operator=. Its purpose is to\n      * prevent a default operator= from hiding the templated operator=.\n      */\n    PermutationMatrix& operator=(const PermutationMatrix& other)\n    {\n      m_indices = other.m_indices;\n      return *this;\n    }\n    #endif\n\n    /** const version of indices(). */\n    const IndicesType& indices() const { return m_indices; }\n    /** \\returns a reference to the stored array representing the permutation. */\n    IndicesType& indices() { return m_indices; }\n\n\n    /**** multiplication helpers to hopefully get RVO ****/\n\n#ifndef EIGEN_PARSED_BY_DOXYGEN\n    template<typename Other>\n    PermutationMatrix(const InverseImpl<Other,PermutationStorage>& other)\n      : m_indices(other.derived().nestedExpression().size())\n    {\n      eigen_internal_assert(m_indices.size() <= NumTraits<StorageIndex>::highest());\n      StorageIndex end = StorageIndex(m_indices.size());\n      for (StorageIndex i=0; i<end;++i)\n        m_indices.coeffRef(other.derived().nestedExpression().indices().coeff(i)) = i;\n    }\n    template<typename Lhs,typename Rhs>\n    PermutationMatrix(internal::PermPermProduct_t, const Lhs& lhs, const Rhs& rhs)\n      : m_indices(lhs.indices().size())\n    {\n      Base::assignProduct(lhs,rhs);\n    }\n#endif\n\n  protected:\n\n    IndicesType m_indices;\n};\n\n\nnamespace internal {\ntemplate<int SizeAtCompileTime, int MaxSizeAtCompileTime, typename _StorageIndex, int _PacketAccess>\nstruct traits<Map<PermutationMatrix<SizeAtCompileTime, MaxSizeAtCompileTime, _StorageIndex>,_PacketAccess> >\n : traits<Matrix<_StorageIndex,SizeAtCompileTime,SizeAtCompileTime,0,MaxSizeAtCompileTime,MaxSizeAtCompileTime> >\n{\n  typedef PermutationStorage StorageKind;\n  typedef Map<const Matrix<_StorageIndex, SizeAtCompileTime, 1, 0, MaxSizeAtCompileTime, 1>, _PacketAccess> IndicesType;\n  typedef _StorageIndex StorageIndex;\n  typedef void Scalar;\n};\n}\n\ntemplate<int SizeAtCompileTime, int MaxSizeAtCompileTime, typename _StorageIndex, int _PacketAccess>\nclass Map<PermutationMatrix<SizeAtCompileTime, MaxSizeAtCompileTime, _StorageIndex>,_PacketAccess>\n  : public PermutationBase<Map<PermutationMatrix<SizeAtCompileTime, MaxSizeAtCompileTime, _StorageIndex>,_PacketAccess> >\n{\n    typedef PermutationBase<Map> Base;\n    typedef internal::traits<Map> Traits;\n  public:\n\n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    typedef typename Traits::IndicesType IndicesType;\n    typedef typename IndicesType::Scalar StorageIndex;\n    #endif\n\n    inline Map(const StorageIndex* indicesPtr)\n      : m_indices(indicesPtr)\n    {}\n\n    inline Map(const StorageIndex* indicesPtr, Index size)\n      : m_indices(indicesPtr,size)\n    {}\n\n    /** Copies the other permutation into *this */\n    template<typename Other>\n    Map& operator=(const PermutationBase<Other>& other)\n    { return Base::operator=(other.derived()); }\n\n    /** Assignment from the Transpositions \\a tr */\n    template<typename Other>\n    Map& operator=(const TranspositionsBase<Other>& tr)\n    { return Base::operator=(tr.derived()); }\n\n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    /** This is a special case of the templated operator=. Its purpose is to\n      * prevent a default operator= from hiding the templated operator=.\n      */\n    Map& operator=(const Map& other)\n    {\n      m_indices = other.m_indices;\n      return *this;\n    }\n    #endif\n\n    /** const version of indices(). */\n    const IndicesType& indices() const { return m_indices; }\n    /** \\returns a reference to the stored array representing the permutation. */\n    IndicesType& indices() { return m_indices; }\n\n  protected:\n\n    IndicesType m_indices;\n};\n\ntemplate<typename _IndicesType> class TranspositionsWrapper;\nnamespace internal {\ntemplate<typename _IndicesType>\nstruct traits<PermutationWrapper<_IndicesType> >\n{\n  typedef PermutationStorage StorageKind;\n  typedef void Scalar;\n  typedef typename _IndicesType::Scalar StorageIndex;\n  typedef _IndicesType IndicesType;\n  enum {\n    RowsAtCompileTime = _IndicesType::SizeAtCompileTime,\n    ColsAtCompileTime = _IndicesType::SizeAtCompileTime,\n    MaxRowsAtCompileTime = IndicesType::MaxSizeAtCompileTime,\n    MaxColsAtCompileTime = IndicesType::MaxSizeAtCompileTime,\n    Flags = 0\n  };\n};\n}\n\n/** \\class PermutationWrapper\n  * \\ingroup Core_Module\n  *\n  * \\brief Class to view a vector of integers as a permutation matrix\n  *\n  * \\tparam _IndicesType the type of the vector of integer (can be any compatible expression)\n  *\n  * This class allows to view any vector expression of integers as a permutation matrix.\n  *\n  * \\sa class PermutationBase, class PermutationMatrix\n  */\ntemplate<typename _IndicesType>\nclass PermutationWrapper : public PermutationBase<PermutationWrapper<_IndicesType> >\n{\n    typedef PermutationBase<PermutationWrapper> Base;\n    typedef internal::traits<PermutationWrapper> Traits;\n  public:\n\n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    typedef typename Traits::IndicesType IndicesType;\n    #endif\n\n    inline PermutationWrapper(const IndicesType& indices)\n      : m_indices(indices)\n    {}\n\n    /** const version of indices(). */\n    const typename internal::remove_all<typename IndicesType::Nested>::type&\n    indices() const { return m_indices; }\n\n  protected:\n\n    typename IndicesType::Nested m_indices;\n};\n\n\n/** \\returns the matrix with the permutation applied to the columns.\n  */\ntemplate<typename MatrixDerived, typename PermutationDerived>\nEIGEN_DEVICE_FUNC\nconst Product<MatrixDerived, PermutationDerived, AliasFreeProduct>\noperator*(const MatrixBase<MatrixDerived> &matrix,\n          const PermutationBase<PermutationDerived>& permutation)\n{\n  return Product<MatrixDerived, PermutationDerived, AliasFreeProduct>\n            (matrix.derived(), permutation.derived());\n}\n\n/** \\returns the matrix with the permutation applied to the rows.\n  */\ntemplate<typename PermutationDerived, typename MatrixDerived>\nEIGEN_DEVICE_FUNC\nconst Product<PermutationDerived, MatrixDerived, AliasFreeProduct>\noperator*(const PermutationBase<PermutationDerived> &permutation,\n          const MatrixBase<MatrixDerived>& matrix)\n{\n  return Product<PermutationDerived, MatrixDerived, AliasFreeProduct>\n            (permutation.derived(), matrix.derived());\n}\n\n\ntemplate<typename PermutationType>\nclass InverseImpl<PermutationType, PermutationStorage>\n  : public EigenBase<Inverse<PermutationType> >\n{\n    typedef typename PermutationType::PlainPermutationType PlainPermutationType;\n    typedef internal::traits<PermutationType> PermTraits;\n  protected:\n    InverseImpl() {}\n  public:\n    typedef Inverse<PermutationType> InverseType;\n    using EigenBase<Inverse<PermutationType> >::derived;\n\n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    typedef typename PermutationType::DenseMatrixType DenseMatrixType;\n    enum {\n      RowsAtCompileTime = PermTraits::RowsAtCompileTime,\n      ColsAtCompileTime = PermTraits::ColsAtCompileTime,\n      MaxRowsAtCompileTime = PermTraits::MaxRowsAtCompileTime,\n      MaxColsAtCompileTime = PermTraits::MaxColsAtCompileTime\n    };\n    #endif\n\n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    template<typename DenseDerived>\n    void evalTo(MatrixBase<DenseDerived>& other) const\n    {\n      other.setZero();\n      for (Index i=0; i<derived().rows();++i)\n        other.coeffRef(i, derived().nestedExpression().indices().coeff(i)) = typename DenseDerived::Scalar(1);\n    }\n    #endif\n\n    /** \\return the equivalent permutation matrix */\n    PlainPermutationType eval() const { return derived(); }\n\n    DenseMatrixType toDenseMatrix() const { return derived(); }\n\n    /** \\returns the matrix with the inverse permutation applied to the columns.\n      */\n    template<typename OtherDerived> friend\n    const Product<OtherDerived, InverseType, AliasFreeProduct>\n    operator*(const MatrixBase<OtherDerived>& matrix, const InverseType& trPerm)\n    {\n      return Product<OtherDerived, InverseType, AliasFreeProduct>(matrix.derived(), trPerm.derived());\n    }\n\n    /** \\returns the matrix with the inverse permutation applied to the rows.\n      */\n    template<typename OtherDerived>\n    const Product<InverseType, OtherDerived, AliasFreeProduct>\n    operator*(const MatrixBase<OtherDerived>& matrix) const\n    {\n      return Product<InverseType, OtherDerived, AliasFreeProduct>(derived(), matrix.derived());\n    }\n};\n\ntemplate<typename Derived>\nconst PermutationWrapper<const Derived> MatrixBase<Derived>::asPermutation() const\n{\n  return derived();\n}\n\nnamespace internal {\n\ntemplate<> struct AssignmentKind<DenseShape,PermutationShape> { typedef EigenBase2EigenBase Kind; };\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_PERMUTATIONMATRIX_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/PlainObjectBase.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2006-2008 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_DENSESTORAGEBASE_H\n#define EIGEN_DENSESTORAGEBASE_H\n\n#if defined(EIGEN_INITIALIZE_MATRICES_BY_ZERO)\n# define EIGEN_INITIALIZE_COEFFS\n# define EIGEN_INITIALIZE_COEFFS_IF_THAT_OPTION_IS_ENABLED for(int i=0;i<base().size();++i) coeffRef(i)=Scalar(0);\n#elif defined(EIGEN_INITIALIZE_MATRICES_BY_NAN)\n# define EIGEN_INITIALIZE_COEFFS\n# define EIGEN_INITIALIZE_COEFFS_IF_THAT_OPTION_IS_ENABLED for(int i=0;i<base().size();++i) coeffRef(i)=std::numeric_limits<Scalar>::quiet_NaN();\n#else\n# undef EIGEN_INITIALIZE_COEFFS\n# define EIGEN_INITIALIZE_COEFFS_IF_THAT_OPTION_IS_ENABLED\n#endif\n\nnamespace Eigen {\n\nnamespace internal {\n\ntemplate<int MaxSizeAtCompileTime> struct check_rows_cols_for_overflow {\n  template<typename Index>\n  EIGEN_DEVICE_FUNC\n  static EIGEN_ALWAYS_INLINE void run(Index, Index)\n  {\n  }\n};\n\ntemplate<> struct check_rows_cols_for_overflow<Dynamic> {\n  template<typename Index>\n  EIGEN_DEVICE_FUNC\n  static EIGEN_ALWAYS_INLINE void run(Index rows, Index cols)\n  {\n    // http://hg.mozilla.org/mozilla-central/file/6c8a909977d3/xpcom/ds/CheckedInt.h#l242\n    // we assume Index is signed\n    Index max_index = (size_t(1) << (8 * sizeof(Index) - 1)) - 1; // assume Index is signed\n    bool error = (rows == 0 || cols == 0) ? false\n               : (rows > max_index / cols);\n    if (error)\n      throw_std_bad_alloc();\n  }\n};\n\ntemplate <typename Derived,\n          typename OtherDerived = Derived,\n          bool IsVector = bool(Derived::IsVectorAtCompileTime) && bool(OtherDerived::IsVectorAtCompileTime)>\nstruct conservative_resize_like_impl;\n\ntemplate<typename MatrixTypeA, typename MatrixTypeB, bool SwapPointers> struct matrix_swap_impl;\n\n} // end namespace internal\n\n/** \\class PlainObjectBase\n  * \\ingroup Core_Module\n  * \\brief %Dense storage base class for matrices and arrays.\n  *\n  * This class can be extended with the help of the plugin mechanism described on the page\n  * \\ref TopicCustomizing_Plugins by defining the preprocessor symbol \\c EIGEN_PLAINOBJECTBASE_PLUGIN.\n  *\n  * \\sa \\ref TopicClassHierarchy\n  */\n#ifdef EIGEN_PARSED_BY_DOXYGEN\nnamespace doxygen {\n\n// this is a workaround to doxygen not being able to understand the inheritance logic\n// when it is hidden by the dense_xpr_base helper struct.\n/** This class is just a workaround for Doxygen and it does not not actually exist. */\ntemplate<typename Derived> struct dense_xpr_base_dispatcher;\n/** This class is just a workaround for Doxygen and it does not not actually exist. */\ntemplate<typename _Scalar, int _Rows, int _Cols, int _Options, int _MaxRows, int _MaxCols>\nstruct dense_xpr_base_dispatcher<Matrix<_Scalar, _Rows, _Cols, _Options, _MaxRows, _MaxCols> >\n    : public MatrixBase<Matrix<_Scalar, _Rows, _Cols, _Options, _MaxRows, _MaxCols> > {};\n/** This class is just a workaround for Doxygen and it does not not actually exist. */\ntemplate<typename _Scalar, int _Rows, int _Cols, int _Options, int _MaxRows, int _MaxCols>\nstruct dense_xpr_base_dispatcher<Array<_Scalar, _Rows, _Cols, _Options, _MaxRows, _MaxCols> >\n    : public ArrayBase<Array<_Scalar, _Rows, _Cols, _Options, _MaxRows, _MaxCols> > {};\n\n} // namespace doxygen\n\ntemplate<typename Derived>\nclass PlainObjectBase : public doxygen::dense_xpr_base_dispatcher<Derived>\n#else\ntemplate<typename Derived>\nclass PlainObjectBase : public internal::dense_xpr_base<Derived>::type\n#endif\n{\n  public:\n    enum { Options = internal::traits<Derived>::Options };\n    typedef typename internal::dense_xpr_base<Derived>::type Base;\n\n    typedef typename internal::traits<Derived>::StorageKind StorageKind;\n    typedef typename internal::traits<Derived>::Scalar Scalar;\n    \n    typedef typename internal::packet_traits<Scalar>::type PacketScalar;\n    typedef typename NumTraits<Scalar>::Real RealScalar;\n    typedef Derived DenseType;\n\n    using Base::RowsAtCompileTime;\n    using Base::ColsAtCompileTime;\n    using Base::SizeAtCompileTime;\n    using Base::MaxRowsAtCompileTime;\n    using Base::MaxColsAtCompileTime;\n    using Base::MaxSizeAtCompileTime;\n    using Base::IsVectorAtCompileTime;\n    using Base::Flags;\n\n    template<typename PlainObjectType, int MapOptions, typename StrideType> friend class Eigen::Map;\n    friend  class Eigen::Map<Derived, Unaligned>;\n    typedef Eigen::Map<Derived, Unaligned>  MapType;\n    friend  class Eigen::Map<const Derived, Unaligned>;\n    typedef const Eigen::Map<const Derived, Unaligned> ConstMapType;\n#if EIGEN_MAX_ALIGN_BYTES>0\n    // for EIGEN_MAX_ALIGN_BYTES==0, AlignedMax==Unaligned, and many compilers generate warnings for friend-ing a class twice.\n    friend  class Eigen::Map<Derived, AlignedMax>;\n    friend  class Eigen::Map<const Derived, AlignedMax>;\n#endif\n    typedef Eigen::Map<Derived, AlignedMax> AlignedMapType;\n    typedef const Eigen::Map<const Derived, AlignedMax> ConstAlignedMapType;\n    template<typename StrideType> struct StridedMapType { typedef Eigen::Map<Derived, Unaligned, StrideType> type; };\n    template<typename StrideType> struct StridedConstMapType { typedef Eigen::Map<const Derived, Unaligned, StrideType> type; };\n    template<typename StrideType> struct StridedAlignedMapType { typedef Eigen::Map<Derived, AlignedMax, StrideType> type; };\n    template<typename StrideType> struct StridedConstAlignedMapType { typedef Eigen::Map<const Derived, AlignedMax, StrideType> type; };\n\n  protected:\n    DenseStorage<Scalar, Base::MaxSizeAtCompileTime, Base::RowsAtCompileTime, Base::ColsAtCompileTime, Options> m_storage;\n\n  public:\n    enum { NeedsToAlign = (SizeAtCompileTime != Dynamic) && (internal::traits<Derived>::Alignment>0) };\n    EIGEN_MAKE_ALIGNED_OPERATOR_NEW_IF(NeedsToAlign)\n\n    EIGEN_DEVICE_FUNC\n    Base& base() { return *static_cast<Base*>(this); }\n    EIGEN_DEVICE_FUNC\n    const Base& base() const { return *static_cast<const Base*>(this); }\n\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Index rows() const { return m_storage.rows(); }\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Index cols() const { return m_storage.cols(); }\n\n    /** This is an overloaded version of DenseCoeffsBase<Derived,ReadOnlyAccessors>::coeff(Index,Index) const\n      * provided to by-pass the creation of an evaluator of the expression, thus saving compilation efforts.\n      *\n      * See DenseCoeffsBase<Derived,ReadOnlyAccessors>::coeff(Index) const for details. */\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE const Scalar& coeff(Index rowId, Index colId) const\n    {\n      if(Flags & RowMajorBit)\n        return m_storage.data()[colId + rowId * m_storage.cols()];\n      else // column-major\n        return m_storage.data()[rowId + colId * m_storage.rows()];\n    }\n\n    /** This is an overloaded version of DenseCoeffsBase<Derived,ReadOnlyAccessors>::coeff(Index) const\n      * provided to by-pass the creation of an evaluator of the expression, thus saving compilation efforts.\n      *\n      * See DenseCoeffsBase<Derived,ReadOnlyAccessors>::coeff(Index) const for details. */\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE const Scalar& coeff(Index index) const\n    {\n      return m_storage.data()[index];\n    }\n\n    /** This is an overloaded version of DenseCoeffsBase<Derived,WriteAccessors>::coeffRef(Index,Index) const\n      * provided to by-pass the creation of an evaluator of the expression, thus saving compilation efforts.\n      *\n      * See DenseCoeffsBase<Derived,WriteAccessors>::coeffRef(Index,Index) const for details. */\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Scalar& coeffRef(Index rowId, Index colId)\n    {\n      if(Flags & RowMajorBit)\n        return m_storage.data()[colId + rowId * m_storage.cols()];\n      else // column-major\n        return m_storage.data()[rowId + colId * m_storage.rows()];\n    }\n\n    /** This is an overloaded version of DenseCoeffsBase<Derived,WriteAccessors>::coeffRef(Index) const\n      * provided to by-pass the creation of an evaluator of the expression, thus saving compilation efforts.\n      *\n      * See DenseCoeffsBase<Derived,WriteAccessors>::coeffRef(Index) const for details. */\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Scalar& coeffRef(Index index)\n    {\n      return m_storage.data()[index];\n    }\n\n    /** This is the const version of coeffRef(Index,Index) which is thus synonym of coeff(Index,Index).\n      * It is provided for convenience. */\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE const Scalar& coeffRef(Index rowId, Index colId) const\n    {\n      if(Flags & RowMajorBit)\n        return m_storage.data()[colId + rowId * m_storage.cols()];\n      else // column-major\n        return m_storage.data()[rowId + colId * m_storage.rows()];\n    }\n\n    /** This is the const version of coeffRef(Index) which is thus synonym of coeff(Index).\n      * It is provided for convenience. */\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE const Scalar& coeffRef(Index index) const\n    {\n      return m_storage.data()[index];\n    }\n\n    /** \\internal */\n    template<int LoadMode>\n    EIGEN_STRONG_INLINE PacketScalar packet(Index rowId, Index colId) const\n    {\n      return internal::ploadt<PacketScalar, LoadMode>\n               (m_storage.data() + (Flags & RowMajorBit\n                                   ? colId + rowId * m_storage.cols()\n                                   : rowId + colId * m_storage.rows()));\n    }\n\n    /** \\internal */\n    template<int LoadMode>\n    EIGEN_STRONG_INLINE PacketScalar packet(Index index) const\n    {\n      return internal::ploadt<PacketScalar, LoadMode>(m_storage.data() + index);\n    }\n\n    /** \\internal */\n    template<int StoreMode>\n    EIGEN_STRONG_INLINE void writePacket(Index rowId, Index colId, const PacketScalar& val)\n    {\n      internal::pstoret<Scalar, PacketScalar, StoreMode>\n              (m_storage.data() + (Flags & RowMajorBit\n                                   ? colId + rowId * m_storage.cols()\n                                   : rowId + colId * m_storage.rows()), val);\n    }\n\n    /** \\internal */\n    template<int StoreMode>\n    EIGEN_STRONG_INLINE void writePacket(Index index, const PacketScalar& val)\n    {\n      internal::pstoret<Scalar, PacketScalar, StoreMode>(m_storage.data() + index, val);\n    }\n\n    /** \\returns a const pointer to the data array of this matrix */\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const Scalar *data() const\n    { return m_storage.data(); }\n\n    /** \\returns a pointer to the data array of this matrix */\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE Scalar *data()\n    { return m_storage.data(); }\n\n    /** Resizes \\c *this to a \\a rows x \\a cols matrix.\n      *\n      * This method is intended for dynamic-size matrices, although it is legal to call it on any\n      * matrix as long as fixed dimensions are left unchanged. If you only want to change the number\n      * of rows and/or of columns, you can use resize(NoChange_t, Index), resize(Index, NoChange_t).\n      *\n      * If the current number of coefficients of \\c *this exactly matches the\n      * product \\a rows * \\a cols, then no memory allocation is performed and\n      * the current values are left unchanged. In all other cases, including\n      * shrinking, the data is reallocated and all previous values are lost.\n      *\n      * Example: \\include Matrix_resize_int_int.cpp\n      * Output: \\verbinclude Matrix_resize_int_int.out\n      *\n      * \\sa resize(Index) for vectors, resize(NoChange_t, Index), resize(Index, NoChange_t)\n      */\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE void resize(Index rows, Index cols)\n    {\n      eigen_assert(   EIGEN_IMPLIES(RowsAtCompileTime!=Dynamic,rows==RowsAtCompileTime)\n                   && EIGEN_IMPLIES(ColsAtCompileTime!=Dynamic,cols==ColsAtCompileTime)\n                   && EIGEN_IMPLIES(RowsAtCompileTime==Dynamic && MaxRowsAtCompileTime!=Dynamic,rows<=MaxRowsAtCompileTime)\n                   && EIGEN_IMPLIES(ColsAtCompileTime==Dynamic && MaxColsAtCompileTime!=Dynamic,cols<=MaxColsAtCompileTime)\n                   && rows>=0 && cols>=0 && \"Invalid sizes when resizing a matrix or array.\");\n      internal::check_rows_cols_for_overflow<MaxSizeAtCompileTime>::run(rows, cols);\n      #ifdef EIGEN_INITIALIZE_COEFFS\n        Index size = rows*cols;\n        bool size_changed = size != this->size();\n        m_storage.resize(size, rows, cols);\n        if(size_changed) EIGEN_INITIALIZE_COEFFS_IF_THAT_OPTION_IS_ENABLED\n      #else\n        m_storage.resize(rows*cols, rows, cols);\n      #endif\n    }\n\n    /** Resizes \\c *this to a vector of length \\a size\n      *\n      * \\only_for_vectors. This method does not work for\n      * partially dynamic matrices when the static dimension is anything other\n      * than 1. For example it will not work with Matrix<double, 2, Dynamic>.\n      *\n      * Example: \\include Matrix_resize_int.cpp\n      * Output: \\verbinclude Matrix_resize_int.out\n      *\n      * \\sa resize(Index,Index), resize(NoChange_t, Index), resize(Index, NoChange_t)\n      */\n    EIGEN_DEVICE_FUNC\n    inline void resize(Index size)\n    {\n      EIGEN_STATIC_ASSERT_VECTOR_ONLY(PlainObjectBase)\n      eigen_assert(((SizeAtCompileTime == Dynamic && (MaxSizeAtCompileTime==Dynamic || size<=MaxSizeAtCompileTime)) || SizeAtCompileTime == size) && size>=0);\n      #ifdef EIGEN_INITIALIZE_COEFFS\n        bool size_changed = size != this->size();\n      #endif\n      if(RowsAtCompileTime == 1)\n        m_storage.resize(size, 1, size);\n      else\n        m_storage.resize(size, size, 1);\n      #ifdef EIGEN_INITIALIZE_COEFFS\n        if(size_changed) EIGEN_INITIALIZE_COEFFS_IF_THAT_OPTION_IS_ENABLED\n      #endif\n    }\n\n    /** Resizes the matrix, changing only the number of columns. For the parameter of type NoChange_t, just pass the special value \\c NoChange\n      * as in the example below.\n      *\n      * Example: \\include Matrix_resize_NoChange_int.cpp\n      * Output: \\verbinclude Matrix_resize_NoChange_int.out\n      *\n      * \\sa resize(Index,Index)\n      */\n    EIGEN_DEVICE_FUNC\n    inline void resize(NoChange_t, Index cols)\n    {\n      resize(rows(), cols);\n    }\n\n    /** Resizes the matrix, changing only the number of rows. For the parameter of type NoChange_t, just pass the special value \\c NoChange\n      * as in the example below.\n      *\n      * Example: \\include Matrix_resize_int_NoChange.cpp\n      * Output: \\verbinclude Matrix_resize_int_NoChange.out\n      *\n      * \\sa resize(Index,Index)\n      */\n    EIGEN_DEVICE_FUNC\n    inline void resize(Index rows, NoChange_t)\n    {\n      resize(rows, cols());\n    }\n\n    /** Resizes \\c *this to have the same dimensions as \\a other.\n      * Takes care of doing all the checking that's needed.\n      *\n      * Note that copying a row-vector into a vector (and conversely) is allowed.\n      * The resizing, if any, is then done in the appropriate way so that row-vectors\n      * remain row-vectors and vectors remain vectors.\n      */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC \n    EIGEN_STRONG_INLINE void resizeLike(const EigenBase<OtherDerived>& _other)\n    {\n      const OtherDerived& other = _other.derived();\n      internal::check_rows_cols_for_overflow<MaxSizeAtCompileTime>::run(other.rows(), other.cols());\n      const Index othersize = other.rows()*other.cols();\n      if(RowsAtCompileTime == 1)\n      {\n        eigen_assert(other.rows() == 1 || other.cols() == 1);\n        resize(1, othersize);\n      }\n      else if(ColsAtCompileTime == 1)\n      {\n        eigen_assert(other.rows() == 1 || other.cols() == 1);\n        resize(othersize, 1);\n      }\n      else resize(other.rows(), other.cols());\n    }\n\n    /** Resizes the matrix to \\a rows x \\a cols while leaving old values untouched.\n      *\n      * The method is intended for matrices of dynamic size. If you only want to change the number\n      * of rows and/or of columns, you can use conservativeResize(NoChange_t, Index) or\n      * conservativeResize(Index, NoChange_t).\n      *\n      * Matrices are resized relative to the top-left element. In case values need to be \n      * appended to the matrix they will be uninitialized.\n      */\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE void conservativeResize(Index rows, Index cols)\n    {\n      internal::conservative_resize_like_impl<Derived>::run(*this, rows, cols);\n    }\n\n    /** Resizes the matrix to \\a rows x \\a cols while leaving old values untouched.\n      *\n      * As opposed to conservativeResize(Index rows, Index cols), this version leaves\n      * the number of columns unchanged.\n      *\n      * In case the matrix is growing, new rows will be uninitialized.\n      */\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE void conservativeResize(Index rows, NoChange_t)\n    {\n      // Note: see the comment in conservativeResize(Index,Index)\n      conservativeResize(rows, cols());\n    }\n\n    /** Resizes the matrix to \\a rows x \\a cols while leaving old values untouched.\n      *\n      * As opposed to conservativeResize(Index rows, Index cols), this version leaves\n      * the number of rows unchanged.\n      *\n      * In case the matrix is growing, new columns will be uninitialized.\n      */\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE void conservativeResize(NoChange_t, Index cols)\n    {\n      // Note: see the comment in conservativeResize(Index,Index)\n      conservativeResize(rows(), cols);\n    }\n\n    /** Resizes the vector to \\a size while retaining old values.\n      *\n      * \\only_for_vectors. This method does not work for\n      * partially dynamic matrices when the static dimension is anything other\n      * than 1. For example it will not work with Matrix<double, 2, Dynamic>.\n      *\n      * When values are appended, they will be uninitialized.\n      */\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE void conservativeResize(Index size)\n    {\n      internal::conservative_resize_like_impl<Derived>::run(*this, size);\n    }\n\n    /** Resizes the matrix to \\a rows x \\a cols of \\c other, while leaving old values untouched.\n      *\n      * The method is intended for matrices of dynamic size. If you only want to change the number\n      * of rows and/or of columns, you can use conservativeResize(NoChange_t, Index) or\n      * conservativeResize(Index, NoChange_t).\n      *\n      * Matrices are resized relative to the top-left element. In case values need to be \n      * appended to the matrix they will copied from \\c other.\n      */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE void conservativeResizeLike(const DenseBase<OtherDerived>& other)\n    {\n      internal::conservative_resize_like_impl<Derived,OtherDerived>::run(*this, other);\n    }\n\n    /** This is a special case of the templated operator=. Its purpose is to\n      * prevent a default operator= from hiding the templated operator=.\n      */\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Derived& operator=(const PlainObjectBase& other)\n    {\n      return _set(other);\n    }\n\n    /** \\sa MatrixBase::lazyAssign() */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Derived& lazyAssign(const DenseBase<OtherDerived>& other)\n    {\n      _resize_to_match(other);\n      return Base::lazyAssign(other.derived());\n    }\n\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE Derived& operator=(const ReturnByValue<OtherDerived>& func)\n    {\n      resize(func.rows(), func.cols());\n      return Base::operator=(func);\n    }\n\n    // Prevent user from trying to instantiate PlainObjectBase objects\n    // by making all its constructor protected. See bug 1074.\n  protected:\n\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE PlainObjectBase() : m_storage()\n    {\n//       _check_template_params();\n//       EIGEN_INITIALIZE_COEFFS_IF_THAT_OPTION_IS_ENABLED\n    }\n\n#ifndef EIGEN_PARSED_BY_DOXYGEN\n    // FIXME is it still needed ?\n    /** \\internal */\n    EIGEN_DEVICE_FUNC\n    explicit PlainObjectBase(internal::constructor_without_unaligned_array_assert)\n      : m_storage(internal::constructor_without_unaligned_array_assert())\n    {\n//       _check_template_params(); EIGEN_INITIALIZE_COEFFS_IF_THAT_OPTION_IS_ENABLED\n    }\n#endif\n\n#if EIGEN_HAS_RVALUE_REFERENCES\n    EIGEN_DEVICE_FUNC\n    PlainObjectBase(PlainObjectBase&& other) EIGEN_NOEXCEPT\n      : m_storage( std::move(other.m_storage) )\n    {\n    }\n\n    EIGEN_DEVICE_FUNC\n    PlainObjectBase& operator=(PlainObjectBase&& other) EIGEN_NOEXCEPT\n    {\n      using std::swap;\n      swap(m_storage, other.m_storage);\n      return *this;\n    }\n#endif\n\n    /** Copy constructor */\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE PlainObjectBase(const PlainObjectBase& other)\n      : Base(), m_storage(other.m_storage) { }\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE PlainObjectBase(Index size, Index rows, Index cols)\n      : m_storage(size, rows, cols)\n    {\n//       _check_template_params();\n//       EIGEN_INITIALIZE_COEFFS_IF_THAT_OPTION_IS_ENABLED\n    }\n\n    /** \\sa PlainObjectBase::operator=(const EigenBase<OtherDerived>&) */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE PlainObjectBase(const DenseBase<OtherDerived> &other)\n      : m_storage()\n    {\n      _check_template_params();\n      resizeLike(other);\n      _set_noalias(other);\n    }\n\n    /** \\sa PlainObjectBase::operator=(const EigenBase<OtherDerived>&) */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE PlainObjectBase(const EigenBase<OtherDerived> &other)\n      : m_storage()\n    {\n      _check_template_params();\n      resizeLike(other);\n      *this = other.derived();\n    }\n    /** \\brief Copy constructor with in-place evaluation */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE PlainObjectBase(const ReturnByValue<OtherDerived>& other)\n    {\n      _check_template_params();\n      // FIXME this does not automatically transpose vectors if necessary\n      resize(other.rows(), other.cols());\n      other.evalTo(this->derived());\n    }\n\n  public:\n\n    /** \\copydoc DenseBase::operator=(const EigenBase<OtherDerived>&)\n      */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC \n    EIGEN_STRONG_INLINE Derived& operator=(const EigenBase<OtherDerived> &other)\n    {\n      _resize_to_match(other);\n      Base::operator=(other.derived());\n      return this->derived();\n    }\n\n    /** \\name Map\n      * These are convenience functions returning Map objects. The Map() static functions return unaligned Map objects,\n      * while the AlignedMap() functions return aligned Map objects and thus should be called only with 16-byte-aligned\n      * \\a data pointers.\n      *\n      * \\see class Map\n      */\n    //@{\n    static inline ConstMapType Map(const Scalar* data)\n    { return ConstMapType(data); }\n    static inline MapType Map(Scalar* data)\n    { return MapType(data); }\n    static inline ConstMapType Map(const Scalar* data, Index size)\n    { return ConstMapType(data, size); }\n    static inline MapType Map(Scalar* data, Index size)\n    { return MapType(data, size); }\n    static inline ConstMapType Map(const Scalar* data, Index rows, Index cols)\n    { return ConstMapType(data, rows, cols); }\n    static inline MapType Map(Scalar* data, Index rows, Index cols)\n    { return MapType(data, rows, cols); }\n\n    static inline ConstAlignedMapType MapAligned(const Scalar* data)\n    { return ConstAlignedMapType(data); }\n    static inline AlignedMapType MapAligned(Scalar* data)\n    { return AlignedMapType(data); }\n    static inline ConstAlignedMapType MapAligned(const Scalar* data, Index size)\n    { return ConstAlignedMapType(data, size); }\n    static inline AlignedMapType MapAligned(Scalar* data, Index size)\n    { return AlignedMapType(data, size); }\n    static inline ConstAlignedMapType MapAligned(const Scalar* data, Index rows, Index cols)\n    { return ConstAlignedMapType(data, rows, cols); }\n    static inline AlignedMapType MapAligned(Scalar* data, Index rows, Index cols)\n    { return AlignedMapType(data, rows, cols); }\n\n    template<int Outer, int Inner>\n    static inline typename StridedConstMapType<Stride<Outer, Inner> >::type Map(const Scalar* data, const Stride<Outer, Inner>& stride)\n    { return typename StridedConstMapType<Stride<Outer, Inner> >::type(data, stride); }\n    template<int Outer, int Inner>\n    static inline typename StridedMapType<Stride<Outer, Inner> >::type Map(Scalar* data, const Stride<Outer, Inner>& stride)\n    { return typename StridedMapType<Stride<Outer, Inner> >::type(data, stride); }\n    template<int Outer, int Inner>\n    static inline typename StridedConstMapType<Stride<Outer, Inner> >::type Map(const Scalar* data, Index size, const Stride<Outer, Inner>& stride)\n    { return typename StridedConstMapType<Stride<Outer, Inner> >::type(data, size, stride); }\n    template<int Outer, int Inner>\n    static inline typename StridedMapType<Stride<Outer, Inner> >::type Map(Scalar* data, Index size, const Stride<Outer, Inner>& stride)\n    { return typename StridedMapType<Stride<Outer, Inner> >::type(data, size, stride); }\n    template<int Outer, int Inner>\n    static inline typename StridedConstMapType<Stride<Outer, Inner> >::type Map(const Scalar* data, Index rows, Index cols, const Stride<Outer, Inner>& stride)\n    { return typename StridedConstMapType<Stride<Outer, Inner> >::type(data, rows, cols, stride); }\n    template<int Outer, int Inner>\n    static inline typename StridedMapType<Stride<Outer, Inner> >::type Map(Scalar* data, Index rows, Index cols, const Stride<Outer, Inner>& stride)\n    { return typename StridedMapType<Stride<Outer, Inner> >::type(data, rows, cols, stride); }\n\n    template<int Outer, int Inner>\n    static inline typename StridedConstAlignedMapType<Stride<Outer, Inner> >::type MapAligned(const Scalar* data, const Stride<Outer, Inner>& stride)\n    { return typename StridedConstAlignedMapType<Stride<Outer, Inner> >::type(data, stride); }\n    template<int Outer, int Inner>\n    static inline typename StridedAlignedMapType<Stride<Outer, Inner> >::type MapAligned(Scalar* data, const Stride<Outer, Inner>& stride)\n    { return typename StridedAlignedMapType<Stride<Outer, Inner> >::type(data, stride); }\n    template<int Outer, int Inner>\n    static inline typename StridedConstAlignedMapType<Stride<Outer, Inner> >::type MapAligned(const Scalar* data, Index size, const Stride<Outer, Inner>& stride)\n    { return typename StridedConstAlignedMapType<Stride<Outer, Inner> >::type(data, size, stride); }\n    template<int Outer, int Inner>\n    static inline typename StridedAlignedMapType<Stride<Outer, Inner> >::type MapAligned(Scalar* data, Index size, const Stride<Outer, Inner>& stride)\n    { return typename StridedAlignedMapType<Stride<Outer, Inner> >::type(data, size, stride); }\n    template<int Outer, int Inner>\n    static inline typename StridedConstAlignedMapType<Stride<Outer, Inner> >::type MapAligned(const Scalar* data, Index rows, Index cols, const Stride<Outer, Inner>& stride)\n    { return typename StridedConstAlignedMapType<Stride<Outer, Inner> >::type(data, rows, cols, stride); }\n    template<int Outer, int Inner>\n    static inline typename StridedAlignedMapType<Stride<Outer, Inner> >::type MapAligned(Scalar* data, Index rows, Index cols, const Stride<Outer, Inner>& stride)\n    { return typename StridedAlignedMapType<Stride<Outer, Inner> >::type(data, rows, cols, stride); }\n    //@}\n\n    using Base::setConstant;\n    EIGEN_DEVICE_FUNC Derived& setConstant(Index size, const Scalar& val);\n    EIGEN_DEVICE_FUNC Derived& setConstant(Index rows, Index cols, const Scalar& val);\n\n    using Base::setZero;\n    EIGEN_DEVICE_FUNC Derived& setZero(Index size);\n    EIGEN_DEVICE_FUNC Derived& setZero(Index rows, Index cols);\n\n    using Base::setOnes;\n    EIGEN_DEVICE_FUNC Derived& setOnes(Index size);\n    EIGEN_DEVICE_FUNC Derived& setOnes(Index rows, Index cols);\n\n    using Base::setRandom;\n    Derived& setRandom(Index size);\n    Derived& setRandom(Index rows, Index cols);\n\n    #ifdef EIGEN_PLAINOBJECTBASE_PLUGIN\n    #include EIGEN_PLAINOBJECTBASE_PLUGIN\n    #endif\n\n  protected:\n    /** \\internal Resizes *this in preparation for assigning \\a other to it.\n      * Takes care of doing all the checking that's needed.\n      *\n      * Note that copying a row-vector into a vector (and conversely) is allowed.\n      * The resizing, if any, is then done in the appropriate way so that row-vectors\n      * remain row-vectors and vectors remain vectors.\n      */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC \n    EIGEN_STRONG_INLINE void _resize_to_match(const EigenBase<OtherDerived>& other)\n    {\n      #ifdef EIGEN_NO_AUTOMATIC_RESIZING\n      eigen_assert((this->size()==0 || (IsVectorAtCompileTime ? (this->size() == other.size())\n                 : (rows() == other.rows() && cols() == other.cols())))\n        && \"Size mismatch. Automatic resizing is disabled because EIGEN_NO_AUTOMATIC_RESIZING is defined\");\n      EIGEN_ONLY_USED_FOR_DEBUG(other);\n      #else\n      resizeLike(other);\n      #endif\n    }\n\n    /**\n      * \\brief Copies the value of the expression \\a other into \\c *this with automatic resizing.\n      *\n      * *this might be resized to match the dimensions of \\a other. If *this was a null matrix (not already initialized),\n      * it will be initialized.\n      *\n      * Note that copying a row-vector into a vector (and conversely) is allowed.\n      * The resizing, if any, is then done in the appropriate way so that row-vectors\n      * remain row-vectors and vectors remain vectors.\n      *\n      * \\sa operator=(const MatrixBase<OtherDerived>&), _set_noalias()\n      *\n      * \\internal\n      */\n    // aliasing is dealt once in internall::call_assignment\n    // so at this stage we have to assume aliasing... and resising has to be done later.\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC \n    EIGEN_STRONG_INLINE Derived& _set(const DenseBase<OtherDerived>& other)\n    {\n      internal::call_assignment(this->derived(), other.derived());\n      return this->derived();\n    }\n\n    /** \\internal Like _set() but additionally makes the assumption that no aliasing effect can happen (which\n      * is the case when creating a new matrix) so one can enforce lazy evaluation.\n      *\n      * \\sa operator=(const MatrixBase<OtherDerived>&), _set()\n      */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC \n    EIGEN_STRONG_INLINE Derived& _set_noalias(const DenseBase<OtherDerived>& other)\n    {\n      // I don't think we need this resize call since the lazyAssign will anyways resize\n      // and lazyAssign will be called by the assign selector.\n      //_resize_to_match(other);\n      // the 'false' below means to enforce lazy evaluation. We don't use lazyAssign() because\n      // it wouldn't allow to copy a row-vector into a column-vector.\n      internal::call_assignment_no_alias(this->derived(), other.derived(), internal::assign_op<Scalar,typename OtherDerived::Scalar>());\n      return this->derived();\n    }\n\n    template<typename T0, typename T1>\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE void _init2(Index rows, Index cols, typename internal::enable_if<Base::SizeAtCompileTime!=2,T0>::type* = 0)\n    {\n      EIGEN_STATIC_ASSERT(bool(NumTraits<T0>::IsInteger) &&\n                          bool(NumTraits<T1>::IsInteger),\n                          FLOATING_POINT_ARGUMENT_PASSED__INTEGER_WAS_EXPECTED)\n      resize(rows,cols);\n    }\n    \n    template<typename T0, typename T1>\n    EIGEN_DEVICE_FUNC \n    EIGEN_STRONG_INLINE void _init2(const T0& val0, const T1& val1, typename internal::enable_if<Base::SizeAtCompileTime==2,T0>::type* = 0)\n    {\n      EIGEN_STATIC_ASSERT_VECTOR_SPECIFIC_SIZE(PlainObjectBase, 2)\n      m_storage.data()[0] = Scalar(val0);\n      m_storage.data()[1] = Scalar(val1);\n    }\n    \n    template<typename T0, typename T1>\n    EIGEN_DEVICE_FUNC \n    EIGEN_STRONG_INLINE void _init2(const Index& val0, const Index& val1,\n                                    typename internal::enable_if<    (!internal::is_same<Index,Scalar>::value)\n                                                                  && (internal::is_same<T0,Index>::value)\n                                                                  && (internal::is_same<T1,Index>::value)\n                                                                  && Base::SizeAtCompileTime==2,T1>::type* = 0)\n    {\n      EIGEN_STATIC_ASSERT_VECTOR_SPECIFIC_SIZE(PlainObjectBase, 2)\n      m_storage.data()[0] = Scalar(val0);\n      m_storage.data()[1] = Scalar(val1);\n    }\n\n    // The argument is convertible to the Index type and we either have a non 1x1 Matrix, or a dynamic-sized Array,\n    // then the argument is meant to be the size of the object.\n    template<typename T>\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE void _init1(Index size, typename internal::enable_if<    (Base::SizeAtCompileTime!=1 || !internal::is_convertible<T, Scalar>::value)\n                                                                              && ((!internal::is_same<typename internal::traits<Derived>::XprKind,ArrayXpr>::value || Base::SizeAtCompileTime==Dynamic)),T>::type* = 0)\n    {\n      // NOTE MSVC 2008 complains if we directly put bool(NumTraits<T>::IsInteger) as the EIGEN_STATIC_ASSERT argument.\n      const bool is_integer = NumTraits<T>::IsInteger;\n      EIGEN_UNUSED_VARIABLE(is_integer);\n      EIGEN_STATIC_ASSERT(is_integer,\n                          FLOATING_POINT_ARGUMENT_PASSED__INTEGER_WAS_EXPECTED)\n      resize(size);\n    }\n    \n    // We have a 1x1 matrix/array => the argument is interpreted as the value of the unique coefficient (case where scalar type can be implicitely converted)\n    template<typename T>\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE void _init1(const Scalar& val0, typename internal::enable_if<Base::SizeAtCompileTime==1 && internal::is_convertible<T, Scalar>::value,T>::type* = 0)\n    {\n      EIGEN_STATIC_ASSERT_VECTOR_SPECIFIC_SIZE(PlainObjectBase, 1)\n      m_storage.data()[0] = val0;\n    }\n    \n    // We have a 1x1 matrix/array => the argument is interpreted as the value of the unique coefficient (case where scalar type match the index type)\n    template<typename T>\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE void _init1(const Index& val0,\n                                    typename internal::enable_if<    (!internal::is_same<Index,Scalar>::value)\n                                                                  && (internal::is_same<Index,T>::value)\n                                                                  && Base::SizeAtCompileTime==1\n                                                                  && internal::is_convertible<T, Scalar>::value,T*>::type* = 0)\n    {\n      EIGEN_STATIC_ASSERT_VECTOR_SPECIFIC_SIZE(PlainObjectBase, 1)\n      m_storage.data()[0] = Scalar(val0);\n    }\n\n    // Initialize a fixed size matrix from a pointer to raw data\n    template<typename T>\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE void _init1(const Scalar* data){\n      this->_set_noalias(ConstMapType(data));\n    }\n\n    // Initialize an arbitrary matrix from a dense expression\n    template<typename T, typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE void _init1(const DenseBase<OtherDerived>& other){\n      this->_set_noalias(other);\n    }\n\n    // Initialize an arbitrary matrix from a generic Eigen expression\n    template<typename T, typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE void _init1(const EigenBase<OtherDerived>& other){\n      this->derived() = other;\n    }\n\n    template<typename T, typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE void _init1(const ReturnByValue<OtherDerived>& other)\n    {\n      resize(other.rows(), other.cols());\n      other.evalTo(this->derived());\n    }\n\n    template<typename T, typename OtherDerived, int ColsAtCompileTime>\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE void _init1(const RotationBase<OtherDerived,ColsAtCompileTime>& r)\n    {\n      this->derived() = r;\n    }\n    \n    // For fixed -size arrays:\n    template<typename T>\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE void _init1(const Scalar& val0,\n                                    typename internal::enable_if<    Base::SizeAtCompileTime!=Dynamic\n                                                                  && Base::SizeAtCompileTime!=1\n                                                                  && internal::is_convertible<T, Scalar>::value\n                                                                  && internal::is_same<typename internal::traits<Derived>::XprKind,ArrayXpr>::value,T>::type* = 0)\n    {\n      Base::setConstant(val0);\n    }\n    \n    template<typename T>\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE void _init1(const Index& val0,\n                                    typename internal::enable_if<    (!internal::is_same<Index,Scalar>::value)\n                                                                  && (internal::is_same<Index,T>::value)\n                                                                  && Base::SizeAtCompileTime!=Dynamic\n                                                                  && Base::SizeAtCompileTime!=1\n                                                                  && internal::is_convertible<T, Scalar>::value\n                                                                  && internal::is_same<typename internal::traits<Derived>::XprKind,ArrayXpr>::value,T*>::type* = 0)\n    {\n      Base::setConstant(val0);\n    }\n    \n    template<typename MatrixTypeA, typename MatrixTypeB, bool SwapPointers>\n    friend struct internal::matrix_swap_impl;\n\n  public:\n    \n#ifndef EIGEN_PARSED_BY_DOXYGEN\n    /** \\internal\n      * \\brief Override DenseBase::swap() since for dynamic-sized matrices\n      * of same type it is enough to swap the data pointers.\n      */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    void swap(DenseBase<OtherDerived> & other)\n    {\n      enum { SwapPointers = internal::is_same<Derived, OtherDerived>::value && Base::SizeAtCompileTime==Dynamic };\n      internal::matrix_swap_impl<Derived, OtherDerived, bool(SwapPointers)>::run(this->derived(), other.derived());\n    }\n    \n    /** \\internal\n      * \\brief const version forwarded to DenseBase::swap\n      */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    void swap(DenseBase<OtherDerived> const & other)\n    { Base::swap(other.derived()); }\n    \n    EIGEN_DEVICE_FUNC \n    static EIGEN_STRONG_INLINE void _check_template_params()\n    {\n      EIGEN_STATIC_ASSERT((EIGEN_IMPLIES(MaxRowsAtCompileTime==1 && MaxColsAtCompileTime!=1, (Options&RowMajor)==RowMajor)\n                        && EIGEN_IMPLIES(MaxColsAtCompileTime==1 && MaxRowsAtCompileTime!=1, (Options&RowMajor)==0)\n                        && ((RowsAtCompileTime == Dynamic) || (RowsAtCompileTime >= 0))\n                        && ((ColsAtCompileTime == Dynamic) || (ColsAtCompileTime >= 0))\n                        && ((MaxRowsAtCompileTime == Dynamic) || (MaxRowsAtCompileTime >= 0))\n                        && ((MaxColsAtCompileTime == Dynamic) || (MaxColsAtCompileTime >= 0))\n                        && (MaxRowsAtCompileTime == RowsAtCompileTime || RowsAtCompileTime==Dynamic)\n                        && (MaxColsAtCompileTime == ColsAtCompileTime || ColsAtCompileTime==Dynamic)\n                        && (Options & (DontAlign|RowMajor)) == Options),\n        INVALID_MATRIX_TEMPLATE_PARAMETERS)\n    }\n\n    enum { IsPlainObjectBase = 1 };\n#endif\n};\n\nnamespace internal {\n\ntemplate <typename Derived, typename OtherDerived, bool IsVector>\nstruct conservative_resize_like_impl\n{\n  static void run(DenseBase<Derived>& _this, Index rows, Index cols)\n  {\n    if (_this.rows() == rows && _this.cols() == cols) return;\n    EIGEN_STATIC_ASSERT_DYNAMIC_SIZE(Derived)\n\n    if ( ( Derived::IsRowMajor && _this.cols() == cols) || // row-major and we change only the number of rows\n         (!Derived::IsRowMajor && _this.rows() == rows) )  // column-major and we change only the number of columns\n    {\n      internal::check_rows_cols_for_overflow<Derived::MaxSizeAtCompileTime>::run(rows, cols);\n      _this.derived().m_storage.conservativeResize(rows*cols,rows,cols);\n    }\n    else\n    {\n      // The storage order does not allow us to use reallocation.\n      typename Derived::PlainObject tmp(rows,cols);\n      const Index common_rows = numext::mini(rows, _this.rows());\n      const Index common_cols = numext::mini(cols, _this.cols());\n      tmp.block(0,0,common_rows,common_cols) = _this.block(0,0,common_rows,common_cols);\n      _this.derived().swap(tmp);\n    }\n  }\n\n  static void run(DenseBase<Derived>& _this, const DenseBase<OtherDerived>& other)\n  {\n    if (_this.rows() == other.rows() && _this.cols() == other.cols()) return;\n\n    // Note: Here is space for improvement. Basically, for conservativeResize(Index,Index),\n    // neither RowsAtCompileTime or ColsAtCompileTime must be Dynamic. If only one of the\n    // dimensions is dynamic, one could use either conservativeResize(Index rows, NoChange_t) or\n    // conservativeResize(NoChange_t, Index cols). For these methods new static asserts like\n    // EIGEN_STATIC_ASSERT_DYNAMIC_ROWS and EIGEN_STATIC_ASSERT_DYNAMIC_COLS would be good.\n    EIGEN_STATIC_ASSERT_DYNAMIC_SIZE(Derived)\n    EIGEN_STATIC_ASSERT_DYNAMIC_SIZE(OtherDerived)\n\n    if ( ( Derived::IsRowMajor && _this.cols() == other.cols()) || // row-major and we change only the number of rows\n         (!Derived::IsRowMajor && _this.rows() == other.rows()) )  // column-major and we change only the number of columns\n    {\n      const Index new_rows = other.rows() - _this.rows();\n      const Index new_cols = other.cols() - _this.cols();\n      _this.derived().m_storage.conservativeResize(other.size(),other.rows(),other.cols());\n      if (new_rows>0)\n        _this.bottomRightCorner(new_rows, other.cols()) = other.bottomRows(new_rows);\n      else if (new_cols>0)\n        _this.bottomRightCorner(other.rows(), new_cols) = other.rightCols(new_cols);\n    }\n    else\n    {\n      // The storage order does not allow us to use reallocation.\n      typename Derived::PlainObject tmp(other);\n      const Index common_rows = numext::mini(tmp.rows(), _this.rows());\n      const Index common_cols = numext::mini(tmp.cols(), _this.cols());\n      tmp.block(0,0,common_rows,common_cols) = _this.block(0,0,common_rows,common_cols);\n      _this.derived().swap(tmp);\n    }\n  }\n};\n\n// Here, the specialization for vectors inherits from the general matrix case\n// to allow calling .conservativeResize(rows,cols) on vectors.\ntemplate <typename Derived, typename OtherDerived>\nstruct conservative_resize_like_impl<Derived,OtherDerived,true>\n  : conservative_resize_like_impl<Derived,OtherDerived,false>\n{\n  using conservative_resize_like_impl<Derived,OtherDerived,false>::run;\n  \n  static void run(DenseBase<Derived>& _this, Index size)\n  {\n    const Index new_rows = Derived::RowsAtCompileTime==1 ? 1 : size;\n    const Index new_cols = Derived::RowsAtCompileTime==1 ? size : 1;\n    _this.derived().m_storage.conservativeResize(size,new_rows,new_cols);\n  }\n\n  static void run(DenseBase<Derived>& _this, const DenseBase<OtherDerived>& other)\n  {\n    if (_this.rows() == other.rows() && _this.cols() == other.cols()) return;\n\n    const Index num_new_elements = other.size() - _this.size();\n\n    const Index new_rows = Derived::RowsAtCompileTime==1 ? 1 : other.rows();\n    const Index new_cols = Derived::RowsAtCompileTime==1 ? other.cols() : 1;\n    _this.derived().m_storage.conservativeResize(other.size(),new_rows,new_cols);\n\n    if (num_new_elements > 0)\n      _this.tail(num_new_elements) = other.tail(num_new_elements);\n  }\n};\n\ntemplate<typename MatrixTypeA, typename MatrixTypeB, bool SwapPointers>\nstruct matrix_swap_impl\n{\n  EIGEN_DEVICE_FUNC\n  static inline void run(MatrixTypeA& a, MatrixTypeB& b)\n  {\n    a.base().swap(b);\n  }\n};\n\ntemplate<typename MatrixTypeA, typename MatrixTypeB>\nstruct matrix_swap_impl<MatrixTypeA, MatrixTypeB, true>\n{\n  EIGEN_DEVICE_FUNC\n  static inline void run(MatrixTypeA& a, MatrixTypeB& b)\n  {\n    static_cast<typename MatrixTypeA::Base&>(a).m_storage.swap(static_cast<typename MatrixTypeB::Base&>(b).m_storage);\n  }\n};\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_DENSESTORAGEBASE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/Product.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2011 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_PRODUCT_H\n#define EIGEN_PRODUCT_H\n\nnamespace Eigen {\n\ntemplate<typename Lhs, typename Rhs, int Option, typename StorageKind> class ProductImpl;\n\nnamespace internal {\n\ntemplate<typename Lhs, typename Rhs, int Option>\nstruct traits<Product<Lhs, Rhs, Option> >\n{\n  typedef typename remove_all<Lhs>::type LhsCleaned;\n  typedef typename remove_all<Rhs>::type RhsCleaned;\n  typedef traits<LhsCleaned> LhsTraits;\n  typedef traits<RhsCleaned> RhsTraits;\n  \n  typedef MatrixXpr XprKind;\n  \n  typedef typename ScalarBinaryOpTraits<typename traits<LhsCleaned>::Scalar, typename traits<RhsCleaned>::Scalar>::ReturnType Scalar;\n  typedef typename product_promote_storage_type<typename LhsTraits::StorageKind,\n                                                typename RhsTraits::StorageKind,\n                                                internal::product_type<Lhs,Rhs>::ret>::ret StorageKind;\n  typedef typename promote_index_type<typename LhsTraits::StorageIndex,\n                                      typename RhsTraits::StorageIndex>::type StorageIndex;\n  \n  enum {\n    RowsAtCompileTime    = LhsTraits::RowsAtCompileTime,\n    ColsAtCompileTime    = RhsTraits::ColsAtCompileTime,\n    MaxRowsAtCompileTime = LhsTraits::MaxRowsAtCompileTime,\n    MaxColsAtCompileTime = RhsTraits::MaxColsAtCompileTime,\n    \n    // FIXME: only needed by GeneralMatrixMatrixTriangular\n    InnerSize = EIGEN_SIZE_MIN_PREFER_FIXED(LhsTraits::ColsAtCompileTime, RhsTraits::RowsAtCompileTime),\n    \n    // The storage order is somewhat arbitrary here. The correct one will be determined through the evaluator.\n    Flags = (MaxRowsAtCompileTime==1 && MaxColsAtCompileTime!=1) ? RowMajorBit\n          : (MaxColsAtCompileTime==1 && MaxRowsAtCompileTime!=1) ? 0\n          : (   ((LhsTraits::Flags&NoPreferredStorageOrderBit) && (RhsTraits::Flags&RowMajorBit))\n             || ((RhsTraits::Flags&NoPreferredStorageOrderBit) && (LhsTraits::Flags&RowMajorBit)) ) ? RowMajorBit\n          : NoPreferredStorageOrderBit\n  };\n};\n\n} // end namespace internal\n\n/** \\class Product\n  * \\ingroup Core_Module\n  *\n  * \\brief Expression of the product of two arbitrary matrices or vectors\n  *\n  * \\tparam _Lhs the type of the left-hand side expression\n  * \\tparam _Rhs the type of the right-hand side expression\n  *\n  * This class represents an expression of the product of two arbitrary matrices.\n  *\n  * The other template parameters are:\n  * \\tparam Option     can be DefaultProduct, AliasFreeProduct, or LazyProduct\n  *\n  */\ntemplate<typename _Lhs, typename _Rhs, int Option>\nclass Product : public ProductImpl<_Lhs,_Rhs,Option,\n                                   typename internal::product_promote_storage_type<typename internal::traits<_Lhs>::StorageKind,\n                                                                                   typename internal::traits<_Rhs>::StorageKind,\n                                                                                   internal::product_type<_Lhs,_Rhs>::ret>::ret>\n{\n  public:\n    \n    typedef _Lhs Lhs;\n    typedef _Rhs Rhs;\n    \n    typedef typename ProductImpl<\n        Lhs, Rhs, Option,\n        typename internal::product_promote_storage_type<typename internal::traits<Lhs>::StorageKind,\n                                                        typename internal::traits<Rhs>::StorageKind,\n                                                        internal::product_type<Lhs,Rhs>::ret>::ret>::Base Base;\n    EIGEN_GENERIC_PUBLIC_INTERFACE(Product)\n\n    typedef typename internal::ref_selector<Lhs>::type LhsNested;\n    typedef typename internal::ref_selector<Rhs>::type RhsNested;\n    typedef typename internal::remove_all<LhsNested>::type LhsNestedCleaned;\n    typedef typename internal::remove_all<RhsNested>::type RhsNestedCleaned;\n\n    EIGEN_DEVICE_FUNC Product(const Lhs& lhs, const Rhs& rhs) : m_lhs(lhs), m_rhs(rhs)\n    {\n      eigen_assert(lhs.cols() == rhs.rows()\n        && \"invalid matrix product\"\n        && \"if you wanted a coeff-wise or a dot product use the respective explicit functions\");\n    }\n\n    EIGEN_DEVICE_FUNC inline Index rows() const { return m_lhs.rows(); }\n    EIGEN_DEVICE_FUNC inline Index cols() const { return m_rhs.cols(); }\n\n    EIGEN_DEVICE_FUNC const LhsNestedCleaned& lhs() const { return m_lhs; }\n    EIGEN_DEVICE_FUNC const RhsNestedCleaned& rhs() const { return m_rhs; }\n\n  protected:\n\n    LhsNested m_lhs;\n    RhsNested m_rhs;\n};\n\nnamespace internal {\n  \ntemplate<typename Lhs, typename Rhs, int Option, int ProductTag = internal::product_type<Lhs,Rhs>::ret>\nclass dense_product_base\n : public internal::dense_xpr_base<Product<Lhs,Rhs,Option> >::type\n{};\n\n/** Convertion to scalar for inner-products */\ntemplate<typename Lhs, typename Rhs, int Option>\nclass dense_product_base<Lhs, Rhs, Option, InnerProduct>\n : public internal::dense_xpr_base<Product<Lhs,Rhs,Option> >::type\n{\n  typedef Product<Lhs,Rhs,Option> ProductXpr;\n  typedef typename internal::dense_xpr_base<ProductXpr>::type Base;\npublic:\n  using Base::derived;\n  typedef typename Base::Scalar Scalar;\n  \n  operator const Scalar() const\n  {\n    return internal::evaluator<ProductXpr>(derived()).coeff(0,0);\n  }\n};\n\n} // namespace internal\n\n// Generic API dispatcher\ntemplate<typename Lhs, typename Rhs, int Option, typename StorageKind>\nclass ProductImpl : public internal::generic_xpr_base<Product<Lhs,Rhs,Option>, MatrixXpr, StorageKind>::type\n{\n  public:\n    typedef typename internal::generic_xpr_base<Product<Lhs,Rhs,Option>, MatrixXpr, StorageKind>::type Base;\n};\n\ntemplate<typename Lhs, typename Rhs, int Option>\nclass ProductImpl<Lhs,Rhs,Option,Dense>\n  : public internal::dense_product_base<Lhs,Rhs,Option>\n{\n    typedef Product<Lhs, Rhs, Option> Derived;\n    \n  public:\n    \n    typedef typename internal::dense_product_base<Lhs, Rhs, Option> Base;\n    EIGEN_DENSE_PUBLIC_INTERFACE(Derived)\n  protected:\n    enum {\n      IsOneByOne = (RowsAtCompileTime == 1 || RowsAtCompileTime == Dynamic) && \n                   (ColsAtCompileTime == 1 || ColsAtCompileTime == Dynamic),\n      EnableCoeff = IsOneByOne || Option==LazyProduct\n    };\n    \n  public:\n  \n    EIGEN_DEVICE_FUNC Scalar coeff(Index row, Index col) const\n    {\n      EIGEN_STATIC_ASSERT(EnableCoeff, THIS_METHOD_IS_ONLY_FOR_INNER_OR_LAZY_PRODUCTS);\n      eigen_assert( (Option==LazyProduct) || (this->rows() == 1 && this->cols() == 1) );\n      \n      return internal::evaluator<Derived>(derived()).coeff(row,col);\n    }\n\n    EIGEN_DEVICE_FUNC Scalar coeff(Index i) const\n    {\n      EIGEN_STATIC_ASSERT(EnableCoeff, THIS_METHOD_IS_ONLY_FOR_INNER_OR_LAZY_PRODUCTS);\n      eigen_assert( (Option==LazyProduct) || (this->rows() == 1 && this->cols() == 1) );\n      \n      return internal::evaluator<Derived>(derived()).coeff(i);\n    }\n    \n  \n};\n\n} // end namespace Eigen\n\n#endif // EIGEN_PRODUCT_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/ProductEvaluators.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2006-2008 Benoit Jacob <jacob.benoit.1@gmail.com>\n// Copyright (C) 2008-2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2011 Jitse Niesen <jitse@maths.leeds.ac.uk>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n\n#ifndef EIGEN_PRODUCTEVALUATORS_H\n#define EIGEN_PRODUCTEVALUATORS_H\n\nnamespace Eigen {\n  \nnamespace internal {\n\n/** \\internal\n  * Evaluator of a product expression.\n  * Since products require special treatments to handle all possible cases,\n  * we simply deffer the evaluation logic to a product_evaluator class\n  * which offers more partial specialization possibilities.\n  * \n  * \\sa class product_evaluator\n  */\ntemplate<typename Lhs, typename Rhs, int Options>\nstruct evaluator<Product<Lhs, Rhs, Options> > \n : public product_evaluator<Product<Lhs, Rhs, Options> >\n{\n  typedef Product<Lhs, Rhs, Options> XprType;\n  typedef product_evaluator<XprType> Base;\n  \n  EIGEN_DEVICE_FUNC explicit evaluator(const XprType& xpr) : Base(xpr) {}\n};\n \n// Catch \"scalar * ( A * B )\" and transform it to \"(A*scalar) * B\"\n// TODO we should apply that rule only if that's really helpful\ntemplate<typename Lhs, typename Rhs, typename Scalar1, typename Scalar2, typename Plain1>\nstruct evaluator_assume_aliasing<CwiseBinaryOp<internal::scalar_product_op<Scalar1,Scalar2>,\n                                               const CwiseNullaryOp<internal::scalar_constant_op<Scalar1>, Plain1>,\n                                               const Product<Lhs, Rhs, DefaultProduct> > >\n{\n  static const bool value = true;\n};\ntemplate<typename Lhs, typename Rhs, typename Scalar1, typename Scalar2, typename Plain1>\nstruct evaluator<CwiseBinaryOp<internal::scalar_product_op<Scalar1,Scalar2>,\n                               const CwiseNullaryOp<internal::scalar_constant_op<Scalar1>, Plain1>,\n                               const Product<Lhs, Rhs, DefaultProduct> > >\n : public evaluator<Product<EIGEN_SCALAR_BINARYOP_EXPR_RETURN_TYPE(Scalar1,Lhs,product), Rhs, DefaultProduct> >\n{\n  typedef CwiseBinaryOp<internal::scalar_product_op<Scalar1,Scalar2>,\n                               const CwiseNullaryOp<internal::scalar_constant_op<Scalar1>, Plain1>,\n                               const Product<Lhs, Rhs, DefaultProduct> > XprType;\n  typedef evaluator<Product<EIGEN_SCALAR_BINARYOP_EXPR_RETURN_TYPE(Scalar1,Lhs,product), Rhs, DefaultProduct> > Base;\n\n  EIGEN_DEVICE_FUNC explicit evaluator(const XprType& xpr)\n    : Base(xpr.lhs().functor().m_other * xpr.rhs().lhs() * xpr.rhs().rhs())\n  {}\n};\n\n\ntemplate<typename Lhs, typename Rhs, int DiagIndex>\nstruct evaluator<Diagonal<const Product<Lhs, Rhs, DefaultProduct>, DiagIndex> > \n : public evaluator<Diagonal<const Product<Lhs, Rhs, LazyProduct>, DiagIndex> >\n{\n  typedef Diagonal<const Product<Lhs, Rhs, DefaultProduct>, DiagIndex> XprType;\n  typedef evaluator<Diagonal<const Product<Lhs, Rhs, LazyProduct>, DiagIndex> > Base;\n  \n  EIGEN_DEVICE_FUNC explicit evaluator(const XprType& xpr)\n    : Base(Diagonal<const Product<Lhs, Rhs, LazyProduct>, DiagIndex>(\n        Product<Lhs, Rhs, LazyProduct>(xpr.nestedExpression().lhs(), xpr.nestedExpression().rhs()),\n        xpr.index() ))\n  {}\n};\n\n\n// Helper class to perform a matrix product with the destination at hand.\n// Depending on the sizes of the factors, there are different evaluation strategies\n// as controlled by internal::product_type.\ntemplate< typename Lhs, typename Rhs,\n          typename LhsShape = typename evaluator_traits<Lhs>::Shape,\n          typename RhsShape = typename evaluator_traits<Rhs>::Shape,\n          int ProductType = internal::product_type<Lhs,Rhs>::value>\nstruct generic_product_impl;\n\ntemplate<typename Lhs, typename Rhs>\nstruct evaluator_assume_aliasing<Product<Lhs, Rhs, DefaultProduct> > {\n  static const bool value = true;\n};\n\n// This is the default evaluator implementation for products:\n// It creates a temporary and call generic_product_impl\ntemplate<typename Lhs, typename Rhs, int Options, int ProductTag, typename LhsShape, typename RhsShape>\nstruct product_evaluator<Product<Lhs, Rhs, Options>, ProductTag, LhsShape, RhsShape>\n  : public evaluator<typename Product<Lhs, Rhs, Options>::PlainObject>\n{\n  typedef Product<Lhs, Rhs, Options> XprType;\n  typedef typename XprType::PlainObject PlainObject;\n  typedef evaluator<PlainObject> Base;\n  enum {\n    Flags = Base::Flags | EvalBeforeNestingBit\n  };\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  explicit product_evaluator(const XprType& xpr)\n    : m_result(xpr.rows(), xpr.cols())\n  {\n    ::new (static_cast<Base*>(this)) Base(m_result);\n    \n// FIXME shall we handle nested_eval here?,\n// if so, then we must take care at removing the call to nested_eval in the specializations (e.g., in permutation_matrix_product, transposition_matrix_product, etc.)\n//     typedef typename internal::nested_eval<Lhs,Rhs::ColsAtCompileTime>::type LhsNested;\n//     typedef typename internal::nested_eval<Rhs,Lhs::RowsAtCompileTime>::type RhsNested;\n//     typedef typename internal::remove_all<LhsNested>::type LhsNestedCleaned;\n//     typedef typename internal::remove_all<RhsNested>::type RhsNestedCleaned;\n//     \n//     const LhsNested lhs(xpr.lhs());\n//     const RhsNested rhs(xpr.rhs());\n//   \n//     generic_product_impl<LhsNestedCleaned, RhsNestedCleaned>::evalTo(m_result, lhs, rhs);\n\n    generic_product_impl<Lhs, Rhs, LhsShape, RhsShape, ProductTag>::evalTo(m_result, xpr.lhs(), xpr.rhs());\n  }\n  \nprotected:  \n  PlainObject m_result;\n};\n\n// The following three shortcuts are enabled only if the scalar types match excatly.\n// TODO: we could enable them for different scalar types when the product is not vectorized.\n\n// Dense = Product\ntemplate< typename DstXprType, typename Lhs, typename Rhs, int Options, typename Scalar>\nstruct Assignment<DstXprType, Product<Lhs,Rhs,Options>, internal::assign_op<Scalar,Scalar>, Dense2Dense,\n  typename enable_if<(Options==DefaultProduct || Options==AliasFreeProduct)>::type>\n{\n  typedef Product<Lhs,Rhs,Options> SrcXprType;\n  static EIGEN_STRONG_INLINE\n  void run(DstXprType &dst, const SrcXprType &src, const internal::assign_op<Scalar,Scalar> &)\n  {\n    Index dstRows = src.rows();\n    Index dstCols = src.cols();\n    if((dst.rows()!=dstRows) || (dst.cols()!=dstCols))\n      dst.resize(dstRows, dstCols);\n    // FIXME shall we handle nested_eval here?\n    generic_product_impl<Lhs, Rhs>::evalTo(dst, src.lhs(), src.rhs());\n  }\n};\n\n// Dense += Product\ntemplate< typename DstXprType, typename Lhs, typename Rhs, int Options, typename Scalar>\nstruct Assignment<DstXprType, Product<Lhs,Rhs,Options>, internal::add_assign_op<Scalar,Scalar>, Dense2Dense,\n  typename enable_if<(Options==DefaultProduct || Options==AliasFreeProduct)>::type>\n{\n  typedef Product<Lhs,Rhs,Options> SrcXprType;\n  static EIGEN_STRONG_INLINE\n  void run(DstXprType &dst, const SrcXprType &src, const internal::add_assign_op<Scalar,Scalar> &)\n  {\n    Index dstRows = src.rows();\n    Index dstCols = src.cols();\n    if((dst.rows()!=dstRows) || (dst.cols()!=dstCols))\n      dst.resize(dstRows, dstCols);\n    // FIXME shall we handle nested_eval here?\n    generic_product_impl<Lhs, Rhs>::addTo(dst, src.lhs(), src.rhs());\n  }\n};\n\n// Dense -= Product\ntemplate< typename DstXprType, typename Lhs, typename Rhs, int Options, typename Scalar>\nstruct Assignment<DstXprType, Product<Lhs,Rhs,Options>, internal::sub_assign_op<Scalar,Scalar>, Dense2Dense,\n  typename enable_if<(Options==DefaultProduct || Options==AliasFreeProduct)>::type>\n{\n  typedef Product<Lhs,Rhs,Options> SrcXprType;\n  static EIGEN_STRONG_INLINE\n  void run(DstXprType &dst, const SrcXprType &src, const internal::sub_assign_op<Scalar,Scalar> &)\n  {\n    Index dstRows = src.rows();\n    Index dstCols = src.cols();\n    if((dst.rows()!=dstRows) || (dst.cols()!=dstCols))\n      dst.resize(dstRows, dstCols);\n    // FIXME shall we handle nested_eval here?\n    generic_product_impl<Lhs, Rhs>::subTo(dst, src.lhs(), src.rhs());\n  }\n};\n\n\n// Dense ?= scalar * Product\n// TODO we should apply that rule if that's really helpful\n// for instance, this is not good for inner products\ntemplate< typename DstXprType, typename Lhs, typename Rhs, typename AssignFunc, typename Scalar, typename ScalarBis, typename Plain>\nstruct Assignment<DstXprType, CwiseBinaryOp<internal::scalar_product_op<ScalarBis,Scalar>, const CwiseNullaryOp<internal::scalar_constant_op<ScalarBis>,Plain>,\n                                           const Product<Lhs,Rhs,DefaultProduct> >, AssignFunc, Dense2Dense>\n{\n  typedef CwiseBinaryOp<internal::scalar_product_op<ScalarBis,Scalar>,\n                        const CwiseNullaryOp<internal::scalar_constant_op<ScalarBis>,Plain>,\n                        const Product<Lhs,Rhs,DefaultProduct> > SrcXprType;\n  static EIGEN_STRONG_INLINE\n  void run(DstXprType &dst, const SrcXprType &src, const AssignFunc& func)\n  {\n    call_assignment_no_alias(dst, (src.lhs().functor().m_other * src.rhs().lhs())*src.rhs().rhs(), func);\n  }\n};\n\n//----------------------------------------\n// Catch \"Dense ?= xpr + Product<>\" expression to save one temporary\n// FIXME we could probably enable these rules for any product, i.e., not only Dense and DefaultProduct\n\ntemplate<typename OtherXpr, typename Lhs, typename Rhs>\nstruct evaluator_assume_aliasing<CwiseBinaryOp<internal::scalar_sum_op<typename OtherXpr::Scalar,typename Product<Lhs,Rhs,DefaultProduct>::Scalar>, const OtherXpr,\n                                               const Product<Lhs,Rhs,DefaultProduct> >, DenseShape > {\n  static const bool value = true;\n};\n\ntemplate<typename DstXprType, typename OtherXpr, typename ProductType, typename Func1, typename Func2>\nstruct assignment_from_xpr_op_product\n{\n  template<typename SrcXprType, typename InitialFunc>\n  static EIGEN_STRONG_INLINE\n  void run(DstXprType &dst, const SrcXprType &src, const InitialFunc& /*func*/)\n  {\n    call_assignment_no_alias(dst, src.lhs(), Func1());\n    call_assignment_no_alias(dst, src.rhs(), Func2());\n  }\n};\n\n#define EIGEN_CATCH_ASSIGN_XPR_OP_PRODUCT(ASSIGN_OP,BINOP,ASSIGN_OP2) \\\n  template< typename DstXprType, typename OtherXpr, typename Lhs, typename Rhs, typename DstScalar, typename SrcScalar, typename OtherScalar,typename ProdScalar> \\\n  struct Assignment<DstXprType, CwiseBinaryOp<internal::BINOP<OtherScalar,ProdScalar>, const OtherXpr, \\\n                                            const Product<Lhs,Rhs,DefaultProduct> >, internal::ASSIGN_OP<DstScalar,SrcScalar>, Dense2Dense> \\\n    : assignment_from_xpr_op_product<DstXprType, OtherXpr, Product<Lhs,Rhs,DefaultProduct>, internal::ASSIGN_OP<DstScalar,OtherScalar>, internal::ASSIGN_OP2<DstScalar,ProdScalar> > \\\n  {}\n\nEIGEN_CATCH_ASSIGN_XPR_OP_PRODUCT(assign_op,    scalar_sum_op,add_assign_op);\nEIGEN_CATCH_ASSIGN_XPR_OP_PRODUCT(add_assign_op,scalar_sum_op,add_assign_op);\nEIGEN_CATCH_ASSIGN_XPR_OP_PRODUCT(sub_assign_op,scalar_sum_op,sub_assign_op);\n\nEIGEN_CATCH_ASSIGN_XPR_OP_PRODUCT(assign_op,    scalar_difference_op,sub_assign_op);\nEIGEN_CATCH_ASSIGN_XPR_OP_PRODUCT(add_assign_op,scalar_difference_op,sub_assign_op);\nEIGEN_CATCH_ASSIGN_XPR_OP_PRODUCT(sub_assign_op,scalar_difference_op,add_assign_op);\n\n//----------------------------------------\n\ntemplate<typename Lhs, typename Rhs>\nstruct generic_product_impl<Lhs,Rhs,DenseShape,DenseShape,InnerProduct>\n{\n  template<typename Dst>\n  static inline void evalTo(Dst& dst, const Lhs& lhs, const Rhs& rhs)\n  {\n    dst.coeffRef(0,0) = (lhs.transpose().cwiseProduct(rhs)).sum();\n  }\n  \n  template<typename Dst>\n  static inline void addTo(Dst& dst, const Lhs& lhs, const Rhs& rhs)\n  {\n    dst.coeffRef(0,0) += (lhs.transpose().cwiseProduct(rhs)).sum();\n  }\n  \n  template<typename Dst>\n  static void subTo(Dst& dst, const Lhs& lhs, const Rhs& rhs)\n  { dst.coeffRef(0,0) -= (lhs.transpose().cwiseProduct(rhs)).sum(); }\n};\n\n\n/***********************************************************************\n*  Implementation of outer dense * dense vector product\n***********************************************************************/\n\n// Column major result\ntemplate<typename Dst, typename Lhs, typename Rhs, typename Func>\nvoid outer_product_selector_run(Dst& dst, const Lhs &lhs, const Rhs &rhs, const Func& func, const false_type&)\n{\n  evaluator<Rhs> rhsEval(rhs);\n  typename nested_eval<Lhs,Rhs::SizeAtCompileTime>::type actual_lhs(lhs);\n  // FIXME if cols is large enough, then it might be useful to make sure that lhs is sequentially stored\n  // FIXME not very good if rhs is real and lhs complex while alpha is real too\n  const Index cols = dst.cols();\n  for (Index j=0; j<cols; ++j)\n    func(dst.col(j), rhsEval.coeff(Index(0),j) * actual_lhs);\n}\n\n// Row major result\ntemplate<typename Dst, typename Lhs, typename Rhs, typename Func>\nvoid outer_product_selector_run(Dst& dst, const Lhs &lhs, const Rhs &rhs, const Func& func, const true_type&)\n{\n  evaluator<Lhs> lhsEval(lhs);\n  typename nested_eval<Rhs,Lhs::SizeAtCompileTime>::type actual_rhs(rhs);\n  // FIXME if rows is large enough, then it might be useful to make sure that rhs is sequentially stored\n  // FIXME not very good if lhs is real and rhs complex while alpha is real too\n  const Index rows = dst.rows();\n  for (Index i=0; i<rows; ++i)\n    func(dst.row(i), lhsEval.coeff(i,Index(0)) * actual_rhs);\n}\n\ntemplate<typename Lhs, typename Rhs>\nstruct generic_product_impl<Lhs,Rhs,DenseShape,DenseShape,OuterProduct>\n{\n  template<typename T> struct is_row_major : internal::conditional<(int(T::Flags)&RowMajorBit), internal::true_type, internal::false_type>::type {};\n  typedef typename Product<Lhs,Rhs>::Scalar Scalar;\n  \n  // TODO it would be nice to be able to exploit our *_assign_op functors for that purpose\n  struct set  { template<typename Dst, typename Src> void operator()(const Dst& dst, const Src& src) const { dst.const_cast_derived()  = src; } };\n  struct add  { template<typename Dst, typename Src> void operator()(const Dst& dst, const Src& src) const { dst.const_cast_derived() += src; } };\n  struct sub  { template<typename Dst, typename Src> void operator()(const Dst& dst, const Src& src) const { dst.const_cast_derived() -= src; } };\n  struct adds {\n    Scalar m_scale;\n    explicit adds(const Scalar& s) : m_scale(s) {}\n    template<typename Dst, typename Src> void operator()(const Dst& dst, const Src& src) const {\n      dst.const_cast_derived() += m_scale * src;\n    }\n  };\n  \n  template<typename Dst>\n  static inline void evalTo(Dst& dst, const Lhs& lhs, const Rhs& rhs)\n  {\n    internal::outer_product_selector_run(dst, lhs, rhs, set(), is_row_major<Dst>());\n  }\n  \n  template<typename Dst>\n  static inline void addTo(Dst& dst, const Lhs& lhs, const Rhs& rhs)\n  {\n    internal::outer_product_selector_run(dst, lhs, rhs, add(), is_row_major<Dst>());\n  }\n  \n  template<typename Dst>\n  static inline void subTo(Dst& dst, const Lhs& lhs, const Rhs& rhs)\n  {\n    internal::outer_product_selector_run(dst, lhs, rhs, sub(), is_row_major<Dst>());\n  }\n  \n  template<typename Dst>\n  static inline void scaleAndAddTo(Dst& dst, const Lhs& lhs, const Rhs& rhs, const Scalar& alpha)\n  {\n    internal::outer_product_selector_run(dst, lhs, rhs, adds(alpha), is_row_major<Dst>());\n  }\n  \n};\n\n\n// This base class provides default implementations for evalTo, addTo, subTo, in terms of scaleAndAddTo\ntemplate<typename Lhs, typename Rhs, typename Derived>\nstruct generic_product_impl_base\n{\n  typedef typename Product<Lhs,Rhs>::Scalar Scalar;\n  \n  template<typename Dst>\n  static EIGEN_STRONG_INLINE void evalTo(Dst& dst, const Lhs& lhs, const Rhs& rhs)\n  { dst.setZero(); scaleAndAddTo(dst, lhs, rhs, Scalar(1)); }\n\n  template<typename Dst>\n  static EIGEN_STRONG_INLINE void addTo(Dst& dst, const Lhs& lhs, const Rhs& rhs)\n  { scaleAndAddTo(dst,lhs, rhs, Scalar(1)); }\n\n  template<typename Dst>\n  static EIGEN_STRONG_INLINE void subTo(Dst& dst, const Lhs& lhs, const Rhs& rhs)\n  { scaleAndAddTo(dst, lhs, rhs, Scalar(-1)); }\n  \n  template<typename Dst>\n  static EIGEN_STRONG_INLINE void scaleAndAddTo(Dst& dst, const Lhs& lhs, const Rhs& rhs, const Scalar& alpha)\n  { Derived::scaleAndAddTo(dst,lhs,rhs,alpha); }\n\n};\n\ntemplate<typename Lhs, typename Rhs>\nstruct generic_product_impl<Lhs,Rhs,DenseShape,DenseShape,GemvProduct>\n  : generic_product_impl_base<Lhs,Rhs,generic_product_impl<Lhs,Rhs,DenseShape,DenseShape,GemvProduct> >\n{\n  typedef typename nested_eval<Lhs,1>::type LhsNested;\n  typedef typename nested_eval<Rhs,1>::type RhsNested;\n  typedef typename Product<Lhs,Rhs>::Scalar Scalar;\n  enum { Side = Lhs::IsVectorAtCompileTime ? OnTheLeft : OnTheRight };\n  typedef typename internal::remove_all<typename internal::conditional<int(Side)==OnTheRight,LhsNested,RhsNested>::type>::type MatrixType;\n\n  template<typename Dest>\n  static EIGEN_STRONG_INLINE void scaleAndAddTo(Dest& dst, const Lhs& lhs, const Rhs& rhs, const Scalar& alpha)\n  {\n    LhsNested actual_lhs(lhs);\n    RhsNested actual_rhs(rhs);\n\n    internal::gemv_dense_selector<Side,\n                            (int(MatrixType::Flags)&RowMajorBit) ? RowMajor : ColMajor,\n                            bool(internal::blas_traits<MatrixType>::HasUsableDirectAccess)\n                           >::run(actual_lhs, actual_rhs, dst, alpha);\n  }\n};\n\ntemplate<typename Lhs, typename Rhs>\nstruct generic_product_impl<Lhs,Rhs,DenseShape,DenseShape,CoeffBasedProductMode> \n{\n  typedef typename Product<Lhs,Rhs>::Scalar Scalar;\n  \n  template<typename Dst>\n  static EIGEN_STRONG_INLINE void evalTo(Dst& dst, const Lhs& lhs, const Rhs& rhs)\n  {\n    // Same as: dst.noalias() = lhs.lazyProduct(rhs);\n    // but easier on the compiler side\n    call_assignment_no_alias(dst, lhs.lazyProduct(rhs), internal::assign_op<typename Dst::Scalar,Scalar>());\n  }\n  \n  template<typename Dst>\n  static EIGEN_STRONG_INLINE void addTo(Dst& dst, const Lhs& lhs, const Rhs& rhs)\n  {\n    // dst.noalias() += lhs.lazyProduct(rhs);\n    call_assignment_no_alias(dst, lhs.lazyProduct(rhs), internal::add_assign_op<typename Dst::Scalar,Scalar>());\n  }\n  \n  template<typename Dst>\n  static EIGEN_STRONG_INLINE void subTo(Dst& dst, const Lhs& lhs, const Rhs& rhs)\n  {\n    // dst.noalias() -= lhs.lazyProduct(rhs);\n    call_assignment_no_alias(dst, lhs.lazyProduct(rhs), internal::sub_assign_op<typename Dst::Scalar,Scalar>());\n  }\n  \n//   template<typename Dst>\n//   static inline void scaleAndAddTo(Dst& dst, const Lhs& lhs, const Rhs& rhs, const Scalar& alpha)\n//   { dst.noalias() += alpha * lhs.lazyProduct(rhs); }\n};\n\n// This specialization enforces the use of a coefficient-based evaluation strategy\ntemplate<typename Lhs, typename Rhs>\nstruct generic_product_impl<Lhs,Rhs,DenseShape,DenseShape,LazyCoeffBasedProductMode>\n  : generic_product_impl<Lhs,Rhs,DenseShape,DenseShape,CoeffBasedProductMode> {};\n\n// Case 2: Evaluate coeff by coeff\n//\n// This is mostly taken from CoeffBasedProduct.h\n// The main difference is that we add an extra argument to the etor_product_*_impl::run() function\n// for the inner dimension of the product, because evaluator object do not know their size.\n\ntemplate<int Traversal, int UnrollingIndex, typename Lhs, typename Rhs, typename RetScalar>\nstruct etor_product_coeff_impl;\n\ntemplate<int StorageOrder, int UnrollingIndex, typename Lhs, typename Rhs, typename Packet, int LoadMode>\nstruct etor_product_packet_impl;\n\ntemplate<typename Lhs, typename Rhs, int ProductTag>\nstruct product_evaluator<Product<Lhs, Rhs, LazyProduct>, ProductTag, DenseShape, DenseShape>\n    : evaluator_base<Product<Lhs, Rhs, LazyProduct> >\n{\n  typedef Product<Lhs, Rhs, LazyProduct> XprType;\n  typedef typename XprType::Scalar Scalar;\n  typedef typename XprType::CoeffReturnType CoeffReturnType;\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  explicit product_evaluator(const XprType& xpr)\n    : m_lhs(xpr.lhs()),\n      m_rhs(xpr.rhs()),\n      m_lhsImpl(m_lhs),     // FIXME the creation of the evaluator objects should result in a no-op, but check that!\n      m_rhsImpl(m_rhs),     //       Moreover, they are only useful for the packet path, so we could completely disable them when not needed,\n                            //       or perhaps declare them on the fly on the packet method... We have experiment to check what's best.\n      m_innerDim(xpr.lhs().cols())\n  {\n    EIGEN_INTERNAL_CHECK_COST_VALUE(NumTraits<Scalar>::MulCost);\n    EIGEN_INTERNAL_CHECK_COST_VALUE(NumTraits<Scalar>::AddCost);\n    EIGEN_INTERNAL_CHECK_COST_VALUE(CoeffReadCost);\n#if 0\n    std::cerr << \"LhsOuterStrideBytes=  \" << LhsOuterStrideBytes << \"\\n\";\n    std::cerr << \"RhsOuterStrideBytes=  \" << RhsOuterStrideBytes << \"\\n\";\n    std::cerr << \"LhsAlignment=         \" << LhsAlignment << \"\\n\";\n    std::cerr << \"RhsAlignment=         \" << RhsAlignment << \"\\n\";\n    std::cerr << \"CanVectorizeLhs=      \" << CanVectorizeLhs << \"\\n\";\n    std::cerr << \"CanVectorizeRhs=      \" << CanVectorizeRhs << \"\\n\";\n    std::cerr << \"CanVectorizeInner=    \" << CanVectorizeInner << \"\\n\";\n    std::cerr << \"EvalToRowMajor=       \" << EvalToRowMajor << \"\\n\";\n    std::cerr << \"Alignment=            \" << Alignment << \"\\n\";\n    std::cerr << \"Flags=                \" << Flags << \"\\n\";\n#endif\n  }\n\n  // Everything below here is taken from CoeffBasedProduct.h\n\n  typedef typename internal::nested_eval<Lhs,Rhs::ColsAtCompileTime>::type LhsNested;\n  typedef typename internal::nested_eval<Rhs,Lhs::RowsAtCompileTime>::type RhsNested;\n  \n  typedef typename internal::remove_all<LhsNested>::type LhsNestedCleaned;\n  typedef typename internal::remove_all<RhsNested>::type RhsNestedCleaned;\n\n  typedef evaluator<LhsNestedCleaned> LhsEtorType;\n  typedef evaluator<RhsNestedCleaned> RhsEtorType;\n\n  enum {\n    RowsAtCompileTime = LhsNestedCleaned::RowsAtCompileTime,\n    ColsAtCompileTime = RhsNestedCleaned::ColsAtCompileTime,\n    InnerSize = EIGEN_SIZE_MIN_PREFER_FIXED(LhsNestedCleaned::ColsAtCompileTime, RhsNestedCleaned::RowsAtCompileTime),\n    MaxRowsAtCompileTime = LhsNestedCleaned::MaxRowsAtCompileTime,\n    MaxColsAtCompileTime = RhsNestedCleaned::MaxColsAtCompileTime\n  };\n\n  typedef typename find_best_packet<Scalar,RowsAtCompileTime>::type LhsVecPacketType;\n  typedef typename find_best_packet<Scalar,ColsAtCompileTime>::type RhsVecPacketType;\n\n  enum {\n      \n    LhsCoeffReadCost = LhsEtorType::CoeffReadCost,\n    RhsCoeffReadCost = RhsEtorType::CoeffReadCost,\n    CoeffReadCost = InnerSize==0 ? NumTraits<Scalar>::ReadCost\n                  : InnerSize == Dynamic ? HugeCost\n                  : InnerSize * (NumTraits<Scalar>::MulCost + LhsCoeffReadCost + RhsCoeffReadCost)\n                    + (InnerSize - 1) * NumTraits<Scalar>::AddCost,\n\n    Unroll = CoeffReadCost <= EIGEN_UNROLLING_LIMIT,\n    \n    LhsFlags = LhsEtorType::Flags,\n    RhsFlags = RhsEtorType::Flags,\n    \n    LhsRowMajor = LhsFlags & RowMajorBit,\n    RhsRowMajor = RhsFlags & RowMajorBit,\n\n    LhsVecPacketSize = unpacket_traits<LhsVecPacketType>::size,\n    RhsVecPacketSize = unpacket_traits<RhsVecPacketType>::size,\n\n    // Here, we don't care about alignment larger than the usable packet size.\n    LhsAlignment = EIGEN_PLAIN_ENUM_MIN(LhsEtorType::Alignment,LhsVecPacketSize*int(sizeof(typename LhsNestedCleaned::Scalar))),\n    RhsAlignment = EIGEN_PLAIN_ENUM_MIN(RhsEtorType::Alignment,RhsVecPacketSize*int(sizeof(typename RhsNestedCleaned::Scalar))),\n      \n    SameType = is_same<typename LhsNestedCleaned::Scalar,typename RhsNestedCleaned::Scalar>::value,\n\n    CanVectorizeRhs = bool(RhsRowMajor) && (RhsFlags & PacketAccessBit) && (ColsAtCompileTime!=1),\n    CanVectorizeLhs = (!LhsRowMajor) && (LhsFlags & PacketAccessBit) && (RowsAtCompileTime!=1),\n\n    EvalToRowMajor = (MaxRowsAtCompileTime==1&&MaxColsAtCompileTime!=1) ? 1\n                    : (MaxColsAtCompileTime==1&&MaxRowsAtCompileTime!=1) ? 0\n                    : (bool(RhsRowMajor) && !CanVectorizeLhs),\n\n    Flags = ((unsigned int)(LhsFlags | RhsFlags) & HereditaryBits & ~RowMajorBit)\n          | (EvalToRowMajor ? RowMajorBit : 0)\n          // TODO enable vectorization for mixed types\n          | (SameType && (CanVectorizeLhs || CanVectorizeRhs) ? PacketAccessBit : 0)\n          | (XprType::IsVectorAtCompileTime ? LinearAccessBit : 0),\n          \n    LhsOuterStrideBytes = int(LhsNestedCleaned::OuterStrideAtCompileTime) * int(sizeof(typename LhsNestedCleaned::Scalar)),\n    RhsOuterStrideBytes = int(RhsNestedCleaned::OuterStrideAtCompileTime) * int(sizeof(typename RhsNestedCleaned::Scalar)),\n\n    Alignment = bool(CanVectorizeLhs) ? (LhsOuterStrideBytes<=0 || (int(LhsOuterStrideBytes) % EIGEN_PLAIN_ENUM_MAX(1,LhsAlignment))!=0 ? 0 : LhsAlignment)\n              : bool(CanVectorizeRhs) ? (RhsOuterStrideBytes<=0 || (int(RhsOuterStrideBytes) % EIGEN_PLAIN_ENUM_MAX(1,RhsAlignment))!=0 ? 0 : RhsAlignment)\n              : 0,\n\n    /* CanVectorizeInner deserves special explanation. It does not affect the product flags. It is not used outside\n     * of Product. If the Product itself is not a packet-access expression, there is still a chance that the inner\n     * loop of the product might be vectorized. This is the meaning of CanVectorizeInner. Since it doesn't affect\n     * the Flags, it is safe to make this value depend on ActualPacketAccessBit, that doesn't affect the ABI.\n     */\n    CanVectorizeInner =    SameType\n                        && LhsRowMajor\n                        && (!RhsRowMajor)\n                        && (LhsFlags & RhsFlags & ActualPacketAccessBit)\n                        && (InnerSize % packet_traits<Scalar>::size == 0)\n  };\n  \n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const CoeffReturnType coeff(Index row, Index col) const\n  {\n    return (m_lhs.row(row).transpose().cwiseProduct( m_rhs.col(col) )).sum();\n  }\n\n  /* Allow index-based non-packet access. It is impossible though to allow index-based packed access,\n   * which is why we don't set the LinearAccessBit.\n   * TODO: this seems possible when the result is a vector\n   */\n  EIGEN_DEVICE_FUNC const CoeffReturnType coeff(Index index) const\n  {\n    const Index row = (RowsAtCompileTime == 1 || MaxRowsAtCompileTime==1) ? 0 : index;\n    const Index col = (RowsAtCompileTime == 1 || MaxRowsAtCompileTime==1) ? index : 0;\n    return (m_lhs.row(row).transpose().cwiseProduct( m_rhs.col(col) )).sum();\n  }\n\n  template<int LoadMode, typename PacketType>\n  const PacketType packet(Index row, Index col) const\n  {\n    PacketType res;\n    typedef etor_product_packet_impl<bool(int(Flags)&RowMajorBit) ? RowMajor : ColMajor,\n                                     Unroll ? int(InnerSize) : Dynamic,\n                                     LhsEtorType, RhsEtorType, PacketType, LoadMode> PacketImpl;\n    PacketImpl::run(row, col, m_lhsImpl, m_rhsImpl, m_innerDim, res);\n    return res;\n  }\n\n  template<int LoadMode, typename PacketType>\n  const PacketType packet(Index index) const\n  {\n    const Index row = (RowsAtCompileTime == 1 || MaxRowsAtCompileTime==1) ? 0 : index;\n    const Index col = (RowsAtCompileTime == 1 || MaxRowsAtCompileTime==1) ? index : 0;\n    return packet<LoadMode,PacketType>(row,col);\n  }\n\nprotected:\n  typename internal::add_const_on_value_type<LhsNested>::type m_lhs;\n  typename internal::add_const_on_value_type<RhsNested>::type m_rhs;\n  \n  LhsEtorType m_lhsImpl;\n  RhsEtorType m_rhsImpl;\n\n  // TODO: Get rid of m_innerDim if known at compile time\n  Index m_innerDim;\n};\n\ntemplate<typename Lhs, typename Rhs>\nstruct product_evaluator<Product<Lhs, Rhs, DefaultProduct>, LazyCoeffBasedProductMode, DenseShape, DenseShape>\n  : product_evaluator<Product<Lhs, Rhs, LazyProduct>, CoeffBasedProductMode, DenseShape, DenseShape>\n{\n  typedef Product<Lhs, Rhs, DefaultProduct> XprType;\n  typedef Product<Lhs, Rhs, LazyProduct> BaseProduct;\n  typedef product_evaluator<BaseProduct, CoeffBasedProductMode, DenseShape, DenseShape> Base;\n  enum {\n    Flags = Base::Flags | EvalBeforeNestingBit\n  };\n  EIGEN_DEVICE_FUNC explicit product_evaluator(const XprType& xpr)\n    : Base(BaseProduct(xpr.lhs(),xpr.rhs()))\n  {}\n};\n\n/****************************************\n*** Coeff based product, Packet path  ***\n****************************************/\n\ntemplate<int UnrollingIndex, typename Lhs, typename Rhs, typename Packet, int LoadMode>\nstruct etor_product_packet_impl<RowMajor, UnrollingIndex, Lhs, Rhs, Packet, LoadMode>\n{\n  static EIGEN_STRONG_INLINE void run(Index row, Index col, const Lhs& lhs, const Rhs& rhs, Index innerDim, Packet &res)\n  {\n    etor_product_packet_impl<RowMajor, UnrollingIndex-1, Lhs, Rhs, Packet, LoadMode>::run(row, col, lhs, rhs, innerDim, res);\n    res =  pmadd(pset1<Packet>(lhs.coeff(row, Index(UnrollingIndex-1))), rhs.template packet<LoadMode,Packet>(Index(UnrollingIndex-1), col), res);\n  }\n};\n\ntemplate<int UnrollingIndex, typename Lhs, typename Rhs, typename Packet, int LoadMode>\nstruct etor_product_packet_impl<ColMajor, UnrollingIndex, Lhs, Rhs, Packet, LoadMode>\n{\n  static EIGEN_STRONG_INLINE void run(Index row, Index col, const Lhs& lhs, const Rhs& rhs, Index innerDim, Packet &res)\n  {\n    etor_product_packet_impl<ColMajor, UnrollingIndex-1, Lhs, Rhs, Packet, LoadMode>::run(row, col, lhs, rhs, innerDim, res);\n    res =  pmadd(lhs.template packet<LoadMode,Packet>(row, Index(UnrollingIndex-1)), pset1<Packet>(rhs.coeff(Index(UnrollingIndex-1), col)), res);\n  }\n};\n\ntemplate<typename Lhs, typename Rhs, typename Packet, int LoadMode>\nstruct etor_product_packet_impl<RowMajor, 1, Lhs, Rhs, Packet, LoadMode>\n{\n  static EIGEN_STRONG_INLINE void run(Index row, Index col, const Lhs& lhs, const Rhs& rhs, Index /*innerDim*/, Packet &res)\n  {\n    res = pmul(pset1<Packet>(lhs.coeff(row, Index(0))),rhs.template packet<LoadMode,Packet>(Index(0), col));\n  }\n};\n\ntemplate<typename Lhs, typename Rhs, typename Packet, int LoadMode>\nstruct etor_product_packet_impl<ColMajor, 1, Lhs, Rhs, Packet, LoadMode>\n{\n  static EIGEN_STRONG_INLINE void run(Index row, Index col, const Lhs& lhs, const Rhs& rhs, Index /*innerDim*/, Packet &res)\n  {\n    res = pmul(lhs.template packet<LoadMode,Packet>(row, Index(0)), pset1<Packet>(rhs.coeff(Index(0), col)));\n  }\n};\n\ntemplate<typename Lhs, typename Rhs, typename Packet, int LoadMode>\nstruct etor_product_packet_impl<RowMajor, 0, Lhs, Rhs, Packet, LoadMode>\n{\n  static EIGEN_STRONG_INLINE void run(Index /*row*/, Index /*col*/, const Lhs& /*lhs*/, const Rhs& /*rhs*/, Index /*innerDim*/, Packet &res)\n  {\n    res = pset1<Packet>(typename unpacket_traits<Packet>::type(0));\n  }\n};\n\ntemplate<typename Lhs, typename Rhs, typename Packet, int LoadMode>\nstruct etor_product_packet_impl<ColMajor, 0, Lhs, Rhs, Packet, LoadMode>\n{\n  static EIGEN_STRONG_INLINE void run(Index /*row*/, Index /*col*/, const Lhs& /*lhs*/, const Rhs& /*rhs*/, Index /*innerDim*/, Packet &res)\n  {\n    res = pset1<Packet>(typename unpacket_traits<Packet>::type(0));\n  }\n};\n\ntemplate<typename Lhs, typename Rhs, typename Packet, int LoadMode>\nstruct etor_product_packet_impl<RowMajor, Dynamic, Lhs, Rhs, Packet, LoadMode>\n{\n  static EIGEN_STRONG_INLINE void run(Index row, Index col, const Lhs& lhs, const Rhs& rhs, Index innerDim, Packet& res)\n  {\n    res = pset1<Packet>(typename unpacket_traits<Packet>::type(0));\n    for(Index i = 0; i < innerDim; ++i)\n      res =  pmadd(pset1<Packet>(lhs.coeff(row, i)), rhs.template packet<LoadMode,Packet>(i, col), res);\n  }\n};\n\ntemplate<typename Lhs, typename Rhs, typename Packet, int LoadMode>\nstruct etor_product_packet_impl<ColMajor, Dynamic, Lhs, Rhs, Packet, LoadMode>\n{\n  static EIGEN_STRONG_INLINE void run(Index row, Index col, const Lhs& lhs, const Rhs& rhs, Index innerDim, Packet& res)\n  {\n    res = pset1<Packet>(typename unpacket_traits<Packet>::type(0));\n    for(Index i = 0; i < innerDim; ++i)\n      res =  pmadd(lhs.template packet<LoadMode,Packet>(row, i), pset1<Packet>(rhs.coeff(i, col)), res);\n  }\n};\n\n\n/***************************************************************************\n* Triangular products\n***************************************************************************/\ntemplate<int Mode, bool LhsIsTriangular,\n         typename Lhs, bool LhsIsVector,\n         typename Rhs, bool RhsIsVector>\nstruct triangular_product_impl;\n\ntemplate<typename Lhs, typename Rhs, int ProductTag>\nstruct generic_product_impl<Lhs,Rhs,TriangularShape,DenseShape,ProductTag>\n  : generic_product_impl_base<Lhs,Rhs,generic_product_impl<Lhs,Rhs,TriangularShape,DenseShape,ProductTag> >\n{\n  typedef typename Product<Lhs,Rhs>::Scalar Scalar;\n  \n  template<typename Dest>\n  static void scaleAndAddTo(Dest& dst, const Lhs& lhs, const Rhs& rhs, const Scalar& alpha)\n  {\n    triangular_product_impl<Lhs::Mode,true,typename Lhs::MatrixType,false,Rhs, Rhs::ColsAtCompileTime==1>\n        ::run(dst, lhs.nestedExpression(), rhs, alpha);\n  }\n};\n\ntemplate<typename Lhs, typename Rhs, int ProductTag>\nstruct generic_product_impl<Lhs,Rhs,DenseShape,TriangularShape,ProductTag>\n: generic_product_impl_base<Lhs,Rhs,generic_product_impl<Lhs,Rhs,DenseShape,TriangularShape,ProductTag> >\n{\n  typedef typename Product<Lhs,Rhs>::Scalar Scalar;\n  \n  template<typename Dest>\n  static void scaleAndAddTo(Dest& dst, const Lhs& lhs, const Rhs& rhs, const Scalar& alpha)\n  {\n    triangular_product_impl<Rhs::Mode,false,Lhs,Lhs::RowsAtCompileTime==1, typename Rhs::MatrixType, false>::run(dst, lhs, rhs.nestedExpression(), alpha);\n  }\n};\n\n\n/***************************************************************************\n* SelfAdjoint products\n***************************************************************************/\ntemplate <typename Lhs, int LhsMode, bool LhsIsVector,\n          typename Rhs, int RhsMode, bool RhsIsVector>\nstruct selfadjoint_product_impl;\n\ntemplate<typename Lhs, typename Rhs, int ProductTag>\nstruct generic_product_impl<Lhs,Rhs,SelfAdjointShape,DenseShape,ProductTag>\n  : generic_product_impl_base<Lhs,Rhs,generic_product_impl<Lhs,Rhs,SelfAdjointShape,DenseShape,ProductTag> >\n{\n  typedef typename Product<Lhs,Rhs>::Scalar Scalar;\n  \n  template<typename Dest>\n  static void scaleAndAddTo(Dest& dst, const Lhs& lhs, const Rhs& rhs, const Scalar& alpha)\n  {\n    selfadjoint_product_impl<typename Lhs::MatrixType,Lhs::Mode,false,Rhs,0,Rhs::IsVectorAtCompileTime>::run(dst, lhs.nestedExpression(), rhs, alpha);\n  }\n};\n\ntemplate<typename Lhs, typename Rhs, int ProductTag>\nstruct generic_product_impl<Lhs,Rhs,DenseShape,SelfAdjointShape,ProductTag>\n: generic_product_impl_base<Lhs,Rhs,generic_product_impl<Lhs,Rhs,DenseShape,SelfAdjointShape,ProductTag> >\n{\n  typedef typename Product<Lhs,Rhs>::Scalar Scalar;\n  \n  template<typename Dest>\n  static void scaleAndAddTo(Dest& dst, const Lhs& lhs, const Rhs& rhs, const Scalar& alpha)\n  {\n    selfadjoint_product_impl<Lhs,0,Lhs::IsVectorAtCompileTime,typename Rhs::MatrixType,Rhs::Mode,false>::run(dst, lhs, rhs.nestedExpression(), alpha);\n  }\n};\n\n\n/***************************************************************************\n* Diagonal products\n***************************************************************************/\n  \ntemplate<typename MatrixType, typename DiagonalType, typename Derived, int ProductOrder>\nstruct diagonal_product_evaluator_base\n  : evaluator_base<Derived>\n{\n   typedef typename ScalarBinaryOpTraits<typename MatrixType::Scalar, typename DiagonalType::Scalar>::ReturnType Scalar;\npublic:\n  enum {\n    CoeffReadCost = NumTraits<Scalar>::MulCost + evaluator<MatrixType>::CoeffReadCost + evaluator<DiagonalType>::CoeffReadCost,\n    \n    MatrixFlags = evaluator<MatrixType>::Flags,\n    DiagFlags = evaluator<DiagonalType>::Flags,\n    _StorageOrder = MatrixFlags & RowMajorBit ? RowMajor : ColMajor,\n    _ScalarAccessOnDiag =  !((int(_StorageOrder) == ColMajor && int(ProductOrder) == OnTheLeft)\n                           ||(int(_StorageOrder) == RowMajor && int(ProductOrder) == OnTheRight)),\n    _SameTypes = is_same<typename MatrixType::Scalar, typename DiagonalType::Scalar>::value,\n    // FIXME currently we need same types, but in the future the next rule should be the one\n    //_Vectorizable = bool(int(MatrixFlags)&PacketAccessBit) && ((!_PacketOnDiag) || (_SameTypes && bool(int(DiagFlags)&PacketAccessBit))),\n    _Vectorizable = bool(int(MatrixFlags)&PacketAccessBit) && _SameTypes && (_ScalarAccessOnDiag || (bool(int(DiagFlags)&PacketAccessBit))),\n    _LinearAccessMask = (MatrixType::RowsAtCompileTime==1 || MatrixType::ColsAtCompileTime==1) ? LinearAccessBit : 0,\n    Flags = ((HereditaryBits|_LinearAccessMask) & (unsigned int)(MatrixFlags)) | (_Vectorizable ? PacketAccessBit : 0),\n    Alignment = evaluator<MatrixType>::Alignment\n  };\n  \n  diagonal_product_evaluator_base(const MatrixType &mat, const DiagonalType &diag)\n    : m_diagImpl(diag), m_matImpl(mat)\n  {\n    EIGEN_INTERNAL_CHECK_COST_VALUE(NumTraits<Scalar>::MulCost);\n    EIGEN_INTERNAL_CHECK_COST_VALUE(CoeffReadCost);\n  }\n  \n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const Scalar coeff(Index idx) const\n  {\n    return m_diagImpl.coeff(idx) * m_matImpl.coeff(idx);\n  }\n  \nprotected:\n  template<int LoadMode,typename PacketType>\n  EIGEN_STRONG_INLINE PacketType packet_impl(Index row, Index col, Index id, internal::true_type) const\n  {\n    return internal::pmul(m_matImpl.template packet<LoadMode,PacketType>(row, col),\n                          internal::pset1<PacketType>(m_diagImpl.coeff(id)));\n  }\n  \n  template<int LoadMode,typename PacketType>\n  EIGEN_STRONG_INLINE PacketType packet_impl(Index row, Index col, Index id, internal::false_type) const\n  {\n    enum {\n      InnerSize = (MatrixType::Flags & RowMajorBit) ? MatrixType::ColsAtCompileTime : MatrixType::RowsAtCompileTime,\n      DiagonalPacketLoadMode = EIGEN_PLAIN_ENUM_MIN(LoadMode,((InnerSize%16) == 0) ? int(Aligned16) : int(evaluator<DiagonalType>::Alignment)) // FIXME hardcoded 16!!\n    };\n    return internal::pmul(m_matImpl.template packet<LoadMode,PacketType>(row, col),\n                          m_diagImpl.template packet<DiagonalPacketLoadMode,PacketType>(id));\n  }\n  \n  evaluator<DiagonalType> m_diagImpl;\n  evaluator<MatrixType>   m_matImpl;\n};\n\n// diagonal * dense\ntemplate<typename Lhs, typename Rhs, int ProductKind, int ProductTag>\nstruct product_evaluator<Product<Lhs, Rhs, ProductKind>, ProductTag, DiagonalShape, DenseShape>\n  : diagonal_product_evaluator_base<Rhs, typename Lhs::DiagonalVectorType, Product<Lhs, Rhs, LazyProduct>, OnTheLeft>\n{\n  typedef diagonal_product_evaluator_base<Rhs, typename Lhs::DiagonalVectorType, Product<Lhs, Rhs, LazyProduct>, OnTheLeft> Base;\n  using Base::m_diagImpl;\n  using Base::m_matImpl;\n  using Base::coeff;\n  typedef typename Base::Scalar Scalar;\n  \n  typedef Product<Lhs, Rhs, ProductKind> XprType;\n  typedef typename XprType::PlainObject PlainObject;\n  \n  enum {\n    StorageOrder = int(Rhs::Flags) & RowMajorBit ? RowMajor : ColMajor\n  };\n\n  EIGEN_DEVICE_FUNC explicit product_evaluator(const XprType& xpr)\n    : Base(xpr.rhs(), xpr.lhs().diagonal())\n  {\n  }\n  \n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const Scalar coeff(Index row, Index col) const\n  {\n    return m_diagImpl.coeff(row) * m_matImpl.coeff(row, col);\n  }\n  \n#ifndef __CUDACC__\n  template<int LoadMode,typename PacketType>\n  EIGEN_STRONG_INLINE PacketType packet(Index row, Index col) const\n  {\n    // FIXME: NVCC used to complain about the template keyword, but we have to check whether this is still the case.\n    // See also similar calls below.\n    return this->template packet_impl<LoadMode,PacketType>(row,col, row,\n                                 typename internal::conditional<int(StorageOrder)==RowMajor, internal::true_type, internal::false_type>::type());\n  }\n  \n  template<int LoadMode,typename PacketType>\n  EIGEN_STRONG_INLINE PacketType packet(Index idx) const\n  {\n    return packet<LoadMode,PacketType>(int(StorageOrder)==ColMajor?idx:0,int(StorageOrder)==ColMajor?0:idx);\n  }\n#endif\n};\n\n// dense * diagonal\ntemplate<typename Lhs, typename Rhs, int ProductKind, int ProductTag>\nstruct product_evaluator<Product<Lhs, Rhs, ProductKind>, ProductTag, DenseShape, DiagonalShape>\n  : diagonal_product_evaluator_base<Lhs, typename Rhs::DiagonalVectorType, Product<Lhs, Rhs, LazyProduct>, OnTheRight>\n{\n  typedef diagonal_product_evaluator_base<Lhs, typename Rhs::DiagonalVectorType, Product<Lhs, Rhs, LazyProduct>, OnTheRight> Base;\n  using Base::m_diagImpl;\n  using Base::m_matImpl;\n  using Base::coeff;\n  typedef typename Base::Scalar Scalar;\n  \n  typedef Product<Lhs, Rhs, ProductKind> XprType;\n  typedef typename XprType::PlainObject PlainObject;\n  \n  enum { StorageOrder = int(Lhs::Flags) & RowMajorBit ? RowMajor : ColMajor };\n\n  EIGEN_DEVICE_FUNC explicit product_evaluator(const XprType& xpr)\n    : Base(xpr.lhs(), xpr.rhs().diagonal())\n  {\n  }\n  \n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const Scalar coeff(Index row, Index col) const\n  {\n    return m_matImpl.coeff(row, col) * m_diagImpl.coeff(col);\n  }\n  \n#ifndef __CUDACC__\n  template<int LoadMode,typename PacketType>\n  EIGEN_STRONG_INLINE PacketType packet(Index row, Index col) const\n  {\n    return this->template packet_impl<LoadMode,PacketType>(row,col, col,\n                                 typename internal::conditional<int(StorageOrder)==ColMajor, internal::true_type, internal::false_type>::type());\n  }\n  \n  template<int LoadMode,typename PacketType>\n  EIGEN_STRONG_INLINE PacketType packet(Index idx) const\n  {\n    return packet<LoadMode,PacketType>(int(StorageOrder)==ColMajor?idx:0,int(StorageOrder)==ColMajor?0:idx);\n  }\n#endif\n};\n\n/***************************************************************************\n* Products with permutation matrices\n***************************************************************************/\n\n/** \\internal\n  * \\class permutation_matrix_product\n  * Internal helper class implementing the product between a permutation matrix and a matrix.\n  * This class is specialized for DenseShape below and for SparseShape in SparseCore/SparsePermutation.h\n  */\ntemplate<typename ExpressionType, int Side, bool Transposed, typename ExpressionShape>\nstruct permutation_matrix_product;\n\ntemplate<typename ExpressionType, int Side, bool Transposed>\nstruct permutation_matrix_product<ExpressionType, Side, Transposed, DenseShape>\n{\n    typedef typename nested_eval<ExpressionType, 1>::type MatrixType;\n    typedef typename remove_all<MatrixType>::type MatrixTypeCleaned;\n\n    template<typename Dest, typename PermutationType>\n    static inline void run(Dest& dst, const PermutationType& perm, const ExpressionType& xpr)\n    {\n      MatrixType mat(xpr);\n      const Index n = Side==OnTheLeft ? mat.rows() : mat.cols();\n      // FIXME we need an is_same for expression that is not sensitive to constness. For instance\n      // is_same_xpr<Block<const Matrix>, Block<Matrix> >::value should be true.\n      //if(is_same<MatrixTypeCleaned,Dest>::value && extract_data(dst) == extract_data(mat))\n      if(is_same_dense(dst, mat))\n      {\n        // apply the permutation inplace\n        Matrix<bool,PermutationType::RowsAtCompileTime,1,0,PermutationType::MaxRowsAtCompileTime> mask(perm.size());\n        mask.fill(false);\n        Index r = 0;\n        while(r < perm.size())\n        {\n          // search for the next seed\n          while(r<perm.size() && mask[r]) r++;\n          if(r>=perm.size())\n            break;\n          // we got one, let's follow it until we are back to the seed\n          Index k0 = r++;\n          Index kPrev = k0;\n          mask.coeffRef(k0) = true;\n          for(Index k=perm.indices().coeff(k0); k!=k0; k=perm.indices().coeff(k))\n          {\n                  Block<Dest, Side==OnTheLeft ? 1 : Dest::RowsAtCompileTime, Side==OnTheRight ? 1 : Dest::ColsAtCompileTime>(dst, k)\n            .swap(Block<Dest, Side==OnTheLeft ? 1 : Dest::RowsAtCompileTime, Side==OnTheRight ? 1 : Dest::ColsAtCompileTime>\n                       (dst,((Side==OnTheLeft) ^ Transposed) ? k0 : kPrev));\n\n            mask.coeffRef(k) = true;\n            kPrev = k;\n          }\n        }\n      }\n      else\n      {\n        for(Index i = 0; i < n; ++i)\n        {\n          Block<Dest, Side==OnTheLeft ? 1 : Dest::RowsAtCompileTime, Side==OnTheRight ? 1 : Dest::ColsAtCompileTime>\n               (dst, ((Side==OnTheLeft) ^ Transposed) ? perm.indices().coeff(i) : i)\n\n          =\n\n          Block<const MatrixTypeCleaned,Side==OnTheLeft ? 1 : MatrixTypeCleaned::RowsAtCompileTime,Side==OnTheRight ? 1 : MatrixTypeCleaned::ColsAtCompileTime>\n               (mat, ((Side==OnTheRight) ^ Transposed) ? perm.indices().coeff(i) : i);\n        }\n      }\n    }\n};\n\ntemplate<typename Lhs, typename Rhs, int ProductTag, typename MatrixShape>\nstruct generic_product_impl<Lhs, Rhs, PermutationShape, MatrixShape, ProductTag>\n{\n  template<typename Dest>\n  static void evalTo(Dest& dst, const Lhs& lhs, const Rhs& rhs)\n  {\n    permutation_matrix_product<Rhs, OnTheLeft, false, MatrixShape>::run(dst, lhs, rhs);\n  }\n};\n\ntemplate<typename Lhs, typename Rhs, int ProductTag, typename MatrixShape>\nstruct generic_product_impl<Lhs, Rhs, MatrixShape, PermutationShape, ProductTag>\n{\n  template<typename Dest>\n  static void evalTo(Dest& dst, const Lhs& lhs, const Rhs& rhs)\n  {\n    permutation_matrix_product<Lhs, OnTheRight, false, MatrixShape>::run(dst, rhs, lhs);\n  }\n};\n\ntemplate<typename Lhs, typename Rhs, int ProductTag, typename MatrixShape>\nstruct generic_product_impl<Inverse<Lhs>, Rhs, PermutationShape, MatrixShape, ProductTag>\n{\n  template<typename Dest>\n  static void evalTo(Dest& dst, const Inverse<Lhs>& lhs, const Rhs& rhs)\n  {\n    permutation_matrix_product<Rhs, OnTheLeft, true, MatrixShape>::run(dst, lhs.nestedExpression(), rhs);\n  }\n};\n\ntemplate<typename Lhs, typename Rhs, int ProductTag, typename MatrixShape>\nstruct generic_product_impl<Lhs, Inverse<Rhs>, MatrixShape, PermutationShape, ProductTag>\n{\n  template<typename Dest>\n  static void evalTo(Dest& dst, const Lhs& lhs, const Inverse<Rhs>& rhs)\n  {\n    permutation_matrix_product<Lhs, OnTheRight, true, MatrixShape>::run(dst, rhs.nestedExpression(), lhs);\n  }\n};\n\n\n/***************************************************************************\n* Products with transpositions matrices\n***************************************************************************/\n\n// FIXME could we unify Transpositions and Permutation into a single \"shape\"??\n\n/** \\internal\n  * \\class transposition_matrix_product\n  * Internal helper class implementing the product between a permutation matrix and a matrix.\n  */\ntemplate<typename ExpressionType, int Side, bool Transposed, typename ExpressionShape>\nstruct transposition_matrix_product\n{\n  typedef typename nested_eval<ExpressionType, 1>::type MatrixType;\n  typedef typename remove_all<MatrixType>::type MatrixTypeCleaned;\n  \n  template<typename Dest, typename TranspositionType>\n  static inline void run(Dest& dst, const TranspositionType& tr, const ExpressionType& xpr)\n  {\n    MatrixType mat(xpr);\n    typedef typename TranspositionType::StorageIndex StorageIndex;\n    const Index size = tr.size();\n    StorageIndex j = 0;\n\n    if(!is_same_dense(dst,mat))\n      dst = mat;\n\n    for(Index k=(Transposed?size-1:0) ; Transposed?k>=0:k<size ; Transposed?--k:++k)\n      if(Index(j=tr.coeff(k))!=k)\n      {\n        if(Side==OnTheLeft)        dst.row(k).swap(dst.row(j));\n        else if(Side==OnTheRight)  dst.col(k).swap(dst.col(j));\n      }\n  }\n};\n\ntemplate<typename Lhs, typename Rhs, int ProductTag, typename MatrixShape>\nstruct generic_product_impl<Lhs, Rhs, TranspositionsShape, MatrixShape, ProductTag>\n{\n  template<typename Dest>\n  static void evalTo(Dest& dst, const Lhs& lhs, const Rhs& rhs)\n  {\n    transposition_matrix_product<Rhs, OnTheLeft, false, MatrixShape>::run(dst, lhs, rhs);\n  }\n};\n\ntemplate<typename Lhs, typename Rhs, int ProductTag, typename MatrixShape>\nstruct generic_product_impl<Lhs, Rhs, MatrixShape, TranspositionsShape, ProductTag>\n{\n  template<typename Dest>\n  static void evalTo(Dest& dst, const Lhs& lhs, const Rhs& rhs)\n  {\n    transposition_matrix_product<Lhs, OnTheRight, false, MatrixShape>::run(dst, rhs, lhs);\n  }\n};\n\n\ntemplate<typename Lhs, typename Rhs, int ProductTag, typename MatrixShape>\nstruct generic_product_impl<Transpose<Lhs>, Rhs, TranspositionsShape, MatrixShape, ProductTag>\n{\n  template<typename Dest>\n  static void evalTo(Dest& dst, const Transpose<Lhs>& lhs, const Rhs& rhs)\n  {\n    transposition_matrix_product<Rhs, OnTheLeft, true, MatrixShape>::run(dst, lhs.nestedExpression(), rhs);\n  }\n};\n\ntemplate<typename Lhs, typename Rhs, int ProductTag, typename MatrixShape>\nstruct generic_product_impl<Lhs, Transpose<Rhs>, MatrixShape, TranspositionsShape, ProductTag>\n{\n  template<typename Dest>\n  static void evalTo(Dest& dst, const Lhs& lhs, const Transpose<Rhs>& rhs)\n  {\n    transposition_matrix_product<Lhs, OnTheRight, true, MatrixShape>::run(dst, rhs.nestedExpression(), lhs);\n  }\n};\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_PRODUCT_EVALUATORS_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/Random.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_RANDOM_H\n#define EIGEN_RANDOM_H\n\nnamespace Eigen { \n\nnamespace internal {\n\ntemplate<typename Scalar> struct scalar_random_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_random_op)\n  inline const Scalar operator() () const { return random<Scalar>(); }\n};\n\ntemplate<typename Scalar>\nstruct functor_traits<scalar_random_op<Scalar> >\n{ enum { Cost = 5 * NumTraits<Scalar>::MulCost, PacketAccess = false, IsRepeatable = false }; };\n\n} // end namespace internal\n\n/** \\returns a random matrix expression\n  *\n  * Numbers are uniformly spread through their whole definition range for integer types,\n  * and in the [-1:1] range for floating point scalar types.\n  * \n  * The parameters \\a rows and \\a cols are the number of rows and of columns of\n  * the returned matrix. Must be compatible with this MatrixBase type.\n  *\n  * \\not_reentrant\n  * \n  * This variant is meant to be used for dynamic-size matrix types. For fixed-size types,\n  * it is redundant to pass \\a rows and \\a cols as arguments, so Random() should be used\n  * instead.\n  * \n  *\n  * Example: \\include MatrixBase_random_int_int.cpp\n  * Output: \\verbinclude MatrixBase_random_int_int.out\n  *\n  * This expression has the \"evaluate before nesting\" flag so that it will be evaluated into\n  * a temporary matrix whenever it is nested in a larger expression. This prevents unexpected\n  * behavior with expressions involving random matrices.\n  * \n  * See DenseBase::NullaryExpr(Index, const CustomNullaryOp&) for an example using C++11 random generators.\n  *\n  * \\sa DenseBase::setRandom(), DenseBase::Random(Index), DenseBase::Random()\n  */\ntemplate<typename Derived>\ninline const typename DenseBase<Derived>::RandomReturnType\nDenseBase<Derived>::Random(Index rows, Index cols)\n{\n  return NullaryExpr(rows, cols, internal::scalar_random_op<Scalar>());\n}\n\n/** \\returns a random vector expression\n  *\n  * Numbers are uniformly spread through their whole definition range for integer types,\n  * and in the [-1:1] range for floating point scalar types.\n  *\n  * The parameter \\a size is the size of the returned vector.\n  * Must be compatible with this MatrixBase type.\n  *\n  * \\only_for_vectors\n  * \\not_reentrant\n  *\n  * This variant is meant to be used for dynamic-size vector types. For fixed-size types,\n  * it is redundant to pass \\a size as argument, so Random() should be used\n  * instead.\n  *\n  * Example: \\include MatrixBase_random_int.cpp\n  * Output: \\verbinclude MatrixBase_random_int.out\n  *\n  * This expression has the \"evaluate before nesting\" flag so that it will be evaluated into\n  * a temporary vector whenever it is nested in a larger expression. This prevents unexpected\n  * behavior with expressions involving random matrices.\n  *\n  * \\sa DenseBase::setRandom(), DenseBase::Random(Index,Index), DenseBase::Random()\n  */\ntemplate<typename Derived>\ninline const typename DenseBase<Derived>::RandomReturnType\nDenseBase<Derived>::Random(Index size)\n{\n  return NullaryExpr(size, internal::scalar_random_op<Scalar>());\n}\n\n/** \\returns a fixed-size random matrix or vector expression\n  *\n  * Numbers are uniformly spread through their whole definition range for integer types,\n  * and in the [-1:1] range for floating point scalar types.\n  * \n  * This variant is only for fixed-size MatrixBase types. For dynamic-size types, you\n  * need to use the variants taking size arguments.\n  *\n  * Example: \\include MatrixBase_random.cpp\n  * Output: \\verbinclude MatrixBase_random.out\n  *\n  * This expression has the \"evaluate before nesting\" flag so that it will be evaluated into\n  * a temporary matrix whenever it is nested in a larger expression. This prevents unexpected\n  * behavior with expressions involving random matrices.\n  * \n  * \\not_reentrant\n  *\n  * \\sa DenseBase::setRandom(), DenseBase::Random(Index,Index), DenseBase::Random(Index)\n  */\ntemplate<typename Derived>\ninline const typename DenseBase<Derived>::RandomReturnType\nDenseBase<Derived>::Random()\n{\n  return NullaryExpr(RowsAtCompileTime, ColsAtCompileTime, internal::scalar_random_op<Scalar>());\n}\n\n/** Sets all coefficients in this expression to random values.\n  *\n  * Numbers are uniformly spread through their whole definition range for integer types,\n  * and in the [-1:1] range for floating point scalar types.\n  * \n  * \\not_reentrant\n  * \n  * Example: \\include MatrixBase_setRandom.cpp\n  * Output: \\verbinclude MatrixBase_setRandom.out\n  *\n  * \\sa class CwiseNullaryOp, setRandom(Index), setRandom(Index,Index)\n  */\ntemplate<typename Derived>\ninline Derived& DenseBase<Derived>::setRandom()\n{\n  return *this = Random(rows(), cols());\n}\n\n/** Resizes to the given \\a newSize, and sets all coefficients in this expression to random values.\n  *\n  * Numbers are uniformly spread through their whole definition range for integer types,\n  * and in the [-1:1] range for floating point scalar types.\n  * \n  * \\only_for_vectors\n  * \\not_reentrant\n  *\n  * Example: \\include Matrix_setRandom_int.cpp\n  * Output: \\verbinclude Matrix_setRandom_int.out\n  *\n  * \\sa DenseBase::setRandom(), setRandom(Index,Index), class CwiseNullaryOp, DenseBase::Random()\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE Derived&\nPlainObjectBase<Derived>::setRandom(Index newSize)\n{\n  resize(newSize);\n  return setRandom();\n}\n\n/** Resizes to the given size, and sets all coefficients in this expression to random values.\n  *\n  * Numbers are uniformly spread through their whole definition range for integer types,\n  * and in the [-1:1] range for floating point scalar types.\n  *\n  * \\not_reentrant\n  * \n  * \\param rows the new number of rows\n  * \\param cols the new number of columns\n  *\n  * Example: \\include Matrix_setRandom_int_int.cpp\n  * Output: \\verbinclude Matrix_setRandom_int_int.out\n  *\n  * \\sa DenseBase::setRandom(), setRandom(Index), class CwiseNullaryOp, DenseBase::Random()\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE Derived&\nPlainObjectBase<Derived>::setRandom(Index rows, Index cols)\n{\n  resize(rows, cols);\n  return setRandom();\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_RANDOM_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/Redux.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2006-2008 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_REDUX_H\n#define EIGEN_REDUX_H\n\nnamespace Eigen { \n\nnamespace internal {\n\n// TODO\n//  * implement other kind of vectorization\n//  * factorize code\n\n/***************************************************************************\n* Part 1 : the logic deciding a strategy for vectorization and unrolling\n***************************************************************************/\n\ntemplate<typename Func, typename Derived>\nstruct redux_traits\n{\npublic:\n    typedef typename find_best_packet<typename Derived::Scalar,Derived::SizeAtCompileTime>::type PacketType;\n  enum {\n    PacketSize = unpacket_traits<PacketType>::size,\n    InnerMaxSize = int(Derived::IsRowMajor)\n                 ? Derived::MaxColsAtCompileTime\n                 : Derived::MaxRowsAtCompileTime\n  };\n\n  enum {\n    MightVectorize = (int(Derived::Flags)&ActualPacketAccessBit)\n                  && (functor_traits<Func>::PacketAccess),\n    MayLinearVectorize = bool(MightVectorize) && (int(Derived::Flags)&LinearAccessBit),\n    MaySliceVectorize  = bool(MightVectorize) && int(InnerMaxSize)>=3*PacketSize\n  };\n\npublic:\n  enum {\n    Traversal = int(MayLinearVectorize) ? int(LinearVectorizedTraversal)\n              : int(MaySliceVectorize)  ? int(SliceVectorizedTraversal)\n                                        : int(DefaultTraversal)\n  };\n\npublic:\n  enum {\n    Cost = Derived::SizeAtCompileTime == Dynamic ? HugeCost\n         : Derived::SizeAtCompileTime * Derived::CoeffReadCost + (Derived::SizeAtCompileTime-1) * functor_traits<Func>::Cost,\n    UnrollingLimit = EIGEN_UNROLLING_LIMIT * (int(Traversal) == int(DefaultTraversal) ? 1 : int(PacketSize))\n  };\n\npublic:\n  enum {\n    Unrolling = Cost <= UnrollingLimit ? CompleteUnrolling : NoUnrolling\n  };\n  \n#ifdef EIGEN_DEBUG_ASSIGN\n  static void debug()\n  {\n    std::cerr << \"Xpr: \" << typeid(typename Derived::XprType).name() << std::endl;\n    std::cerr.setf(std::ios::hex, std::ios::basefield);\n    EIGEN_DEBUG_VAR(Derived::Flags)\n    std::cerr.unsetf(std::ios::hex);\n    EIGEN_DEBUG_VAR(InnerMaxSize)\n    EIGEN_DEBUG_VAR(PacketSize)\n    EIGEN_DEBUG_VAR(MightVectorize)\n    EIGEN_DEBUG_VAR(MayLinearVectorize)\n    EIGEN_DEBUG_VAR(MaySliceVectorize)\n    EIGEN_DEBUG_VAR(Traversal)\n    EIGEN_DEBUG_VAR(UnrollingLimit)\n    EIGEN_DEBUG_VAR(Unrolling)\n    std::cerr << std::endl;\n  }\n#endif\n};\n\n/***************************************************************************\n* Part 2 : unrollers\n***************************************************************************/\n\n/*** no vectorization ***/\n\ntemplate<typename Func, typename Derived, int Start, int Length>\nstruct redux_novec_unroller\n{\n  enum {\n    HalfLength = Length/2\n  };\n\n  typedef typename Derived::Scalar Scalar;\n\n  EIGEN_DEVICE_FUNC\n  static EIGEN_STRONG_INLINE Scalar run(const Derived &mat, const Func& func)\n  {\n    return func(redux_novec_unroller<Func, Derived, Start, HalfLength>::run(mat,func),\n                redux_novec_unroller<Func, Derived, Start+HalfLength, Length-HalfLength>::run(mat,func));\n  }\n};\n\ntemplate<typename Func, typename Derived, int Start>\nstruct redux_novec_unroller<Func, Derived, Start, 1>\n{\n  enum {\n    outer = Start / Derived::InnerSizeAtCompileTime,\n    inner = Start % Derived::InnerSizeAtCompileTime\n  };\n\n  typedef typename Derived::Scalar Scalar;\n\n  EIGEN_DEVICE_FUNC\n  static EIGEN_STRONG_INLINE Scalar run(const Derived &mat, const Func&)\n  {\n    return mat.coeffByOuterInner(outer, inner);\n  }\n};\n\n// This is actually dead code and will never be called. It is required\n// to prevent false warnings regarding failed inlining though\n// for 0 length run() will never be called at all.\ntemplate<typename Func, typename Derived, int Start>\nstruct redux_novec_unroller<Func, Derived, Start, 0>\n{\n  typedef typename Derived::Scalar Scalar;\n  EIGEN_DEVICE_FUNC \n  static EIGEN_STRONG_INLINE Scalar run(const Derived&, const Func&) { return Scalar(); }\n};\n\n/*** vectorization ***/\n\ntemplate<typename Func, typename Derived, int Start, int Length>\nstruct redux_vec_unroller\n{\n  enum {\n    PacketSize = redux_traits<Func, Derived>::PacketSize,\n    HalfLength = Length/2\n  };\n\n  typedef typename Derived::Scalar Scalar;\n  typedef typename redux_traits<Func, Derived>::PacketType PacketScalar;\n\n  static EIGEN_STRONG_INLINE PacketScalar run(const Derived &mat, const Func& func)\n  {\n    return func.packetOp(\n            redux_vec_unroller<Func, Derived, Start, HalfLength>::run(mat,func),\n            redux_vec_unroller<Func, Derived, Start+HalfLength, Length-HalfLength>::run(mat,func) );\n  }\n};\n\ntemplate<typename Func, typename Derived, int Start>\nstruct redux_vec_unroller<Func, Derived, Start, 1>\n{\n  enum {\n    index = Start * redux_traits<Func, Derived>::PacketSize,\n    outer = index / int(Derived::InnerSizeAtCompileTime),\n    inner = index % int(Derived::InnerSizeAtCompileTime),\n    alignment = Derived::Alignment\n  };\n\n  typedef typename Derived::Scalar Scalar;\n  typedef typename redux_traits<Func, Derived>::PacketType PacketScalar;\n\n  static EIGEN_STRONG_INLINE PacketScalar run(const Derived &mat, const Func&)\n  {\n    return mat.template packetByOuterInner<alignment,PacketScalar>(outer, inner);\n  }\n};\n\n/***************************************************************************\n* Part 3 : implementation of all cases\n***************************************************************************/\n\ntemplate<typename Func, typename Derived,\n         int Traversal = redux_traits<Func, Derived>::Traversal,\n         int Unrolling = redux_traits<Func, Derived>::Unrolling\n>\nstruct redux_impl;\n\ntemplate<typename Func, typename Derived>\nstruct redux_impl<Func, Derived, DefaultTraversal, NoUnrolling>\n{\n  typedef typename Derived::Scalar Scalar;\n  EIGEN_DEVICE_FUNC\n  static EIGEN_STRONG_INLINE Scalar run(const Derived &mat, const Func& func)\n  {\n    eigen_assert(mat.rows()>0 && mat.cols()>0 && \"you are using an empty matrix\");\n    Scalar res;\n    res = mat.coeffByOuterInner(0, 0);\n    for(Index i = 1; i < mat.innerSize(); ++i)\n      res = func(res, mat.coeffByOuterInner(0, i));\n    for(Index i = 1; i < mat.outerSize(); ++i)\n      for(Index j = 0; j < mat.innerSize(); ++j)\n        res = func(res, mat.coeffByOuterInner(i, j));\n    return res;\n  }\n};\n\ntemplate<typename Func, typename Derived>\nstruct redux_impl<Func,Derived, DefaultTraversal, CompleteUnrolling>\n  : public redux_novec_unroller<Func,Derived, 0, Derived::SizeAtCompileTime>\n{};\n\ntemplate<typename Func, typename Derived>\nstruct redux_impl<Func, Derived, LinearVectorizedTraversal, NoUnrolling>\n{\n  typedef typename Derived::Scalar Scalar;\n  typedef typename redux_traits<Func, Derived>::PacketType PacketScalar;\n\n  static Scalar run(const Derived &mat, const Func& func)\n  {\n    const Index size = mat.size();\n    \n    const Index packetSize = redux_traits<Func, Derived>::PacketSize;\n    const int packetAlignment = unpacket_traits<PacketScalar>::alignment;\n    enum {\n      alignment0 = (bool(Derived::Flags & DirectAccessBit) && bool(packet_traits<Scalar>::AlignedOnScalar)) ? int(packetAlignment) : int(Unaligned),\n      alignment = EIGEN_PLAIN_ENUM_MAX(alignment0, Derived::Alignment)\n    };\n    const Index alignedStart = internal::first_default_aligned(mat.nestedExpression());\n    const Index alignedSize2 = ((size-alignedStart)/(2*packetSize))*(2*packetSize);\n    const Index alignedSize = ((size-alignedStart)/(packetSize))*(packetSize);\n    const Index alignedEnd2 = alignedStart + alignedSize2;\n    const Index alignedEnd  = alignedStart + alignedSize;\n    Scalar res;\n    if(alignedSize)\n    {\n      PacketScalar packet_res0 = mat.template packet<alignment,PacketScalar>(alignedStart);\n      if(alignedSize>packetSize) // we have at least two packets to partly unroll the loop\n      {\n        PacketScalar packet_res1 = mat.template packet<alignment,PacketScalar>(alignedStart+packetSize);\n        for(Index index = alignedStart + 2*packetSize; index < alignedEnd2; index += 2*packetSize)\n        {\n          packet_res0 = func.packetOp(packet_res0, mat.template packet<alignment,PacketScalar>(index));\n          packet_res1 = func.packetOp(packet_res1, mat.template packet<alignment,PacketScalar>(index+packetSize));\n        }\n\n        packet_res0 = func.packetOp(packet_res0,packet_res1);\n        if(alignedEnd>alignedEnd2)\n          packet_res0 = func.packetOp(packet_res0, mat.template packet<alignment,PacketScalar>(alignedEnd2));\n      }\n      res = func.predux(packet_res0);\n\n      for(Index index = 0; index < alignedStart; ++index)\n        res = func(res,mat.coeff(index));\n\n      for(Index index = alignedEnd; index < size; ++index)\n        res = func(res,mat.coeff(index));\n    }\n    else // too small to vectorize anything.\n         // since this is dynamic-size hence inefficient anyway for such small sizes, don't try to optimize.\n    {\n      res = mat.coeff(0);\n      for(Index index = 1; index < size; ++index)\n        res = func(res,mat.coeff(index));\n    }\n\n    return res;\n  }\n};\n\n// NOTE: for SliceVectorizedTraversal we simply bypass unrolling\ntemplate<typename Func, typename Derived, int Unrolling>\nstruct redux_impl<Func, Derived, SliceVectorizedTraversal, Unrolling>\n{\n  typedef typename Derived::Scalar Scalar;\n  typedef typename redux_traits<Func, Derived>::PacketType PacketType;\n\n  EIGEN_DEVICE_FUNC static Scalar run(const Derived &mat, const Func& func)\n  {\n    eigen_assert(mat.rows()>0 && mat.cols()>0 && \"you are using an empty matrix\");\n    const Index innerSize = mat.innerSize();\n    const Index outerSize = mat.outerSize();\n    enum {\n      packetSize = redux_traits<Func, Derived>::PacketSize\n    };\n    const Index packetedInnerSize = ((innerSize)/packetSize)*packetSize;\n    Scalar res;\n    if(packetedInnerSize)\n    {\n      PacketType packet_res = mat.template packet<Unaligned,PacketType>(0,0);\n      for(Index j=0; j<outerSize; ++j)\n        for(Index i=(j==0?packetSize:0); i<packetedInnerSize; i+=Index(packetSize))\n          packet_res = func.packetOp(packet_res, mat.template packetByOuterInner<Unaligned,PacketType>(j,i));\n\n      res = func.predux(packet_res);\n      for(Index j=0; j<outerSize; ++j)\n        for(Index i=packetedInnerSize; i<innerSize; ++i)\n          res = func(res, mat.coeffByOuterInner(j,i));\n    }\n    else // too small to vectorize anything.\n         // since this is dynamic-size hence inefficient anyway for such small sizes, don't try to optimize.\n    {\n      res = redux_impl<Func, Derived, DefaultTraversal, NoUnrolling>::run(mat, func);\n    }\n\n    return res;\n  }\n};\n\ntemplate<typename Func, typename Derived>\nstruct redux_impl<Func, Derived, LinearVectorizedTraversal, CompleteUnrolling>\n{\n  typedef typename Derived::Scalar Scalar;\n\n  typedef typename redux_traits<Func, Derived>::PacketType PacketScalar;\n  enum {\n    PacketSize = redux_traits<Func, Derived>::PacketSize,\n    Size = Derived::SizeAtCompileTime,\n    VectorizedSize = (Size / PacketSize) * PacketSize\n  };\n  EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE Scalar run(const Derived &mat, const Func& func)\n  {\n    eigen_assert(mat.rows()>0 && mat.cols()>0 && \"you are using an empty matrix\");\n    if (VectorizedSize > 0) {\n      Scalar res = func.predux(redux_vec_unroller<Func, Derived, 0, Size / PacketSize>::run(mat,func));\n      if (VectorizedSize != Size)\n        res = func(res,redux_novec_unroller<Func, Derived, VectorizedSize, Size-VectorizedSize>::run(mat,func));\n      return res;\n    }\n    else {\n      return redux_novec_unroller<Func, Derived, 0, Size>::run(mat,func);\n    }\n  }\n};\n\n// evaluator adaptor\ntemplate<typename _XprType>\nclass redux_evaluator\n{\npublic:\n  typedef _XprType XprType;\n  EIGEN_DEVICE_FUNC explicit redux_evaluator(const XprType &xpr) : m_evaluator(xpr), m_xpr(xpr) {}\n  \n  typedef typename XprType::Scalar Scalar;\n  typedef typename XprType::CoeffReturnType CoeffReturnType;\n  typedef typename XprType::PacketScalar PacketScalar;\n  typedef typename XprType::PacketReturnType PacketReturnType;\n  \n  enum {\n    MaxRowsAtCompileTime = XprType::MaxRowsAtCompileTime,\n    MaxColsAtCompileTime = XprType::MaxColsAtCompileTime,\n    // TODO we should not remove DirectAccessBit and rather find an elegant way to query the alignment offset at runtime from the evaluator\n    Flags = evaluator<XprType>::Flags & ~DirectAccessBit,\n    IsRowMajor = XprType::IsRowMajor,\n    SizeAtCompileTime = XprType::SizeAtCompileTime,\n    InnerSizeAtCompileTime = XprType::InnerSizeAtCompileTime,\n    CoeffReadCost = evaluator<XprType>::CoeffReadCost,\n    Alignment = evaluator<XprType>::Alignment\n  };\n  \n  EIGEN_DEVICE_FUNC Index rows() const { return m_xpr.rows(); }\n  EIGEN_DEVICE_FUNC Index cols() const { return m_xpr.cols(); }\n  EIGEN_DEVICE_FUNC Index size() const { return m_xpr.size(); }\n  EIGEN_DEVICE_FUNC Index innerSize() const { return m_xpr.innerSize(); }\n  EIGEN_DEVICE_FUNC Index outerSize() const { return m_xpr.outerSize(); }\n\n  EIGEN_DEVICE_FUNC\n  CoeffReturnType coeff(Index row, Index col) const\n  { return m_evaluator.coeff(row, col); }\n\n  EIGEN_DEVICE_FUNC\n  CoeffReturnType coeff(Index index) const\n  { return m_evaluator.coeff(index); }\n\n  template<int LoadMode, typename PacketType>\n  PacketType packet(Index row, Index col) const\n  { return m_evaluator.template packet<LoadMode,PacketType>(row, col); }\n\n  template<int LoadMode, typename PacketType>\n  PacketType packet(Index index) const\n  { return m_evaluator.template packet<LoadMode,PacketType>(index); }\n  \n  EIGEN_DEVICE_FUNC\n  CoeffReturnType coeffByOuterInner(Index outer, Index inner) const\n  { return m_evaluator.coeff(IsRowMajor ? outer : inner, IsRowMajor ? inner : outer); }\n  \n  template<int LoadMode, typename PacketType>\n  PacketType packetByOuterInner(Index outer, Index inner) const\n  { return m_evaluator.template packet<LoadMode,PacketType>(IsRowMajor ? outer : inner, IsRowMajor ? inner : outer); }\n  \n  const XprType & nestedExpression() const { return m_xpr; }\n  \nprotected:\n  internal::evaluator<XprType> m_evaluator;\n  const XprType &m_xpr;\n};\n\n} // end namespace internal\n\n/***************************************************************************\n* Part 4 : public API\n***************************************************************************/\n\n\n/** \\returns the result of a full redux operation on the whole matrix or vector using \\a func\n  *\n  * The template parameter \\a BinaryOp is the type of the functor \\a func which must be\n  * an associative operator. Both current C++98 and C++11 functor styles are handled.\n  *\n  * \\sa DenseBase::sum(), DenseBase::minCoeff(), DenseBase::maxCoeff(), MatrixBase::colwise(), MatrixBase::rowwise()\n  */\ntemplate<typename Derived>\ntemplate<typename Func>\ntypename internal::traits<Derived>::Scalar\nDenseBase<Derived>::redux(const Func& func) const\n{\n  eigen_assert(this->rows()>0 && this->cols()>0 && \"you are using an empty matrix\");\n\n  typedef typename internal::redux_evaluator<Derived> ThisEvaluator;\n  ThisEvaluator thisEval(derived());\n  \n  return internal::redux_impl<Func, ThisEvaluator>::run(thisEval, func);\n}\n\n/** \\returns the minimum of all coefficients of \\c *this.\n  * \\warning the result is undefined if \\c *this contains NaN.\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE typename internal::traits<Derived>::Scalar\nDenseBase<Derived>::minCoeff() const\n{\n  return derived().redux(Eigen::internal::scalar_min_op<Scalar,Scalar>());\n}\n\n/** \\returns the maximum of all coefficients of \\c *this.\n  * \\warning the result is undefined if \\c *this contains NaN.\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE typename internal::traits<Derived>::Scalar\nDenseBase<Derived>::maxCoeff() const\n{\n  return derived().redux(Eigen::internal::scalar_max_op<Scalar,Scalar>());\n}\n\n/** \\returns the sum of all coefficients of \\c *this\n  *\n  * If \\c *this is empty, then the value 0 is returned.\n  *\n  * \\sa trace(), prod(), mean()\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE typename internal::traits<Derived>::Scalar\nDenseBase<Derived>::sum() const\n{\n  if(SizeAtCompileTime==0 || (SizeAtCompileTime==Dynamic && size()==0))\n    return Scalar(0);\n  return derived().redux(Eigen::internal::scalar_sum_op<Scalar,Scalar>());\n}\n\n/** \\returns the mean of all coefficients of *this\n*\n* \\sa trace(), prod(), sum()\n*/\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE typename internal::traits<Derived>::Scalar\nDenseBase<Derived>::mean() const\n{\n#ifdef __INTEL_COMPILER\n  #pragma warning push\n  #pragma warning ( disable : 2259 )\n#endif\n  return Scalar(derived().redux(Eigen::internal::scalar_sum_op<Scalar,Scalar>())) / Scalar(this->size());\n#ifdef __INTEL_COMPILER\n  #pragma warning pop\n#endif\n}\n\n/** \\returns the product of all coefficients of *this\n  *\n  * Example: \\include MatrixBase_prod.cpp\n  * Output: \\verbinclude MatrixBase_prod.out\n  *\n  * \\sa sum(), mean(), trace()\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE typename internal::traits<Derived>::Scalar\nDenseBase<Derived>::prod() const\n{\n  if(SizeAtCompileTime==0 || (SizeAtCompileTime==Dynamic && size()==0))\n    return Scalar(1);\n  return derived().redux(Eigen::internal::scalar_product_op<Scalar>());\n}\n\n/** \\returns the trace of \\c *this, i.e. the sum of the coefficients on the main diagonal.\n  *\n  * \\c *this can be any matrix, not necessarily square.\n  *\n  * \\sa diagonal(), sum()\n  */\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE typename internal::traits<Derived>::Scalar\nMatrixBase<Derived>::trace() const\n{\n  return derived().diagonal().sum();\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_REDUX_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/Ref.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2012 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_REF_H\n#define EIGEN_REF_H\n\nnamespace Eigen { \n\nnamespace internal {\n\ntemplate<typename _PlainObjectType, int _Options, typename _StrideType>\nstruct traits<Ref<_PlainObjectType, _Options, _StrideType> >\n  : public traits<Map<_PlainObjectType, _Options, _StrideType> >\n{\n  typedef _PlainObjectType PlainObjectType;\n  typedef _StrideType StrideType;\n  enum {\n    Options = _Options,\n    Flags = traits<Map<_PlainObjectType, _Options, _StrideType> >::Flags | NestByRefBit,\n    Alignment = traits<Map<_PlainObjectType, _Options, _StrideType> >::Alignment\n  };\n\n  template<typename Derived> struct match {\n    enum {\n      HasDirectAccess = internal::has_direct_access<Derived>::ret,\n      StorageOrderMatch = PlainObjectType::IsVectorAtCompileTime || Derived::IsVectorAtCompileTime || ((PlainObjectType::Flags&RowMajorBit)==(Derived::Flags&RowMajorBit)),\n      InnerStrideMatch = int(StrideType::InnerStrideAtCompileTime)==int(Dynamic)\n                      || int(StrideType::InnerStrideAtCompileTime)==int(Derived::InnerStrideAtCompileTime)\n                      || (int(StrideType::InnerStrideAtCompileTime)==0 && int(Derived::InnerStrideAtCompileTime)==1),\n      OuterStrideMatch = Derived::IsVectorAtCompileTime\n                      || int(StrideType::OuterStrideAtCompileTime)==int(Dynamic) || int(StrideType::OuterStrideAtCompileTime)==int(Derived::OuterStrideAtCompileTime),\n      // NOTE, this indirection of evaluator<Derived>::Alignment is needed\n      // to workaround a very strange bug in MSVC related to the instantiation\n      // of has_*ary_operator in evaluator<CwiseNullaryOp>.\n      // This line is surprisingly very sensitive. For instance, simply adding parenthesis\n      // as \"DerivedAlignment = (int(evaluator<Derived>::Alignment)),\" will make MSVC fail...\n      DerivedAlignment = int(evaluator<Derived>::Alignment),\n      AlignmentMatch = (int(traits<PlainObjectType>::Alignment)==int(Unaligned)) || (DerivedAlignment >= int(Alignment)), // FIXME the first condition is not very clear, it should be replaced by the required alignment\n      ScalarTypeMatch = internal::is_same<typename PlainObjectType::Scalar, typename Derived::Scalar>::value,\n      MatchAtCompileTime = HasDirectAccess && StorageOrderMatch && InnerStrideMatch && OuterStrideMatch && AlignmentMatch && ScalarTypeMatch\n    };\n    typedef typename internal::conditional<MatchAtCompileTime,internal::true_type,internal::false_type>::type type;\n  };\n  \n};\n\ntemplate<typename Derived>\nstruct traits<RefBase<Derived> > : public traits<Derived> {};\n\n}\n\ntemplate<typename Derived> class RefBase\n : public MapBase<Derived>\n{\n  typedef typename internal::traits<Derived>::PlainObjectType PlainObjectType;\n  typedef typename internal::traits<Derived>::StrideType StrideType;\n\npublic:\n\n  typedef MapBase<Derived> Base;\n  EIGEN_DENSE_PUBLIC_INTERFACE(RefBase)\n\n  EIGEN_DEVICE_FUNC inline Index innerStride() const\n  {\n    return StrideType::InnerStrideAtCompileTime != 0 ? m_stride.inner() : 1;\n  }\n\n  EIGEN_DEVICE_FUNC inline Index outerStride() const\n  {\n    return StrideType::OuterStrideAtCompileTime != 0 ? m_stride.outer()\n         : IsVectorAtCompileTime ? this->size()\n         : int(Flags)&RowMajorBit ? this->cols()\n         : this->rows();\n  }\n\n  EIGEN_DEVICE_FUNC RefBase()\n    : Base(0,RowsAtCompileTime==Dynamic?0:RowsAtCompileTime,ColsAtCompileTime==Dynamic?0:ColsAtCompileTime),\n      // Stride<> does not allow default ctor for Dynamic strides, so let' initialize it with dummy values:\n      m_stride(StrideType::OuterStrideAtCompileTime==Dynamic?0:StrideType::OuterStrideAtCompileTime,\n               StrideType::InnerStrideAtCompileTime==Dynamic?0:StrideType::InnerStrideAtCompileTime)\n  {}\n  \n  EIGEN_INHERIT_ASSIGNMENT_OPERATORS(RefBase)\n\nprotected:\n\n  typedef Stride<StrideType::OuterStrideAtCompileTime,StrideType::InnerStrideAtCompileTime> StrideBase;\n\n  template<typename Expression>\n  EIGEN_DEVICE_FUNC void construct(Expression& expr)\n  {\n    if(PlainObjectType::RowsAtCompileTime==1)\n    {\n      eigen_assert(expr.rows()==1 || expr.cols()==1);\n      ::new (static_cast<Base*>(this)) Base(expr.data(), 1, expr.size());\n    }\n    else if(PlainObjectType::ColsAtCompileTime==1)\n    {\n      eigen_assert(expr.rows()==1 || expr.cols()==1);\n      ::new (static_cast<Base*>(this)) Base(expr.data(), expr.size(), 1);\n    }\n    else\n      ::new (static_cast<Base*>(this)) Base(expr.data(), expr.rows(), expr.cols());\n    \n    if(Expression::IsVectorAtCompileTime && (!PlainObjectType::IsVectorAtCompileTime) && ((Expression::Flags&RowMajorBit)!=(PlainObjectType::Flags&RowMajorBit)))\n      ::new (&m_stride) StrideBase(expr.innerStride(), StrideType::InnerStrideAtCompileTime==0?0:1);\n    else\n      ::new (&m_stride) StrideBase(StrideType::OuterStrideAtCompileTime==0?0:expr.outerStride(),\n                                   StrideType::InnerStrideAtCompileTime==0?0:expr.innerStride());    \n  }\n\n  StrideBase m_stride;\n};\n\n/** \\class Ref\n  * \\ingroup Core_Module\n  *\n  * \\brief A matrix or vector expression mapping an existing expression\n  *\n  * \\tparam PlainObjectType the equivalent matrix type of the mapped data\n  * \\tparam Options specifies the pointer alignment in bytes. It can be: \\c #Aligned128, , \\c #Aligned64, \\c #Aligned32, \\c #Aligned16, \\c #Aligned8 or \\c #Unaligned.\n  *                 The default is \\c #Unaligned.\n  * \\tparam StrideType optionally specifies strides. By default, Ref implies a contiguous storage along the inner dimension (inner stride==1),\n  *                   but accepts a variable outer stride (leading dimension).\n  *                   This can be overridden by specifying strides.\n  *                   The type passed here must be a specialization of the Stride template, see examples below.\n  *\n  * This class provides a way to write non-template functions taking Eigen objects as parameters while limiting the number of copies.\n  * A Ref<> object can represent either a const expression or a l-value:\n  * \\code\n  * // in-out argument:\n  * void foo1(Ref<VectorXf> x);\n  *\n  * // read-only const argument:\n  * void foo2(const Ref<const VectorXf>& x);\n  * \\endcode\n  *\n  * In the in-out case, the input argument must satisfy the constraints of the actual Ref<> type, otherwise a compilation issue will be triggered.\n  * By default, a Ref<VectorXf> can reference any dense vector expression of float having a contiguous memory layout.\n  * Likewise, a Ref<MatrixXf> can reference any column-major dense matrix expression of float whose column's elements are contiguously stored with\n  * the possibility to have a constant space in-between each column, i.e. the inner stride must be equal to 1, but the outer stride (or leading dimension)\n  * can be greater than the number of rows.\n  *\n  * In the const case, if the input expression does not match the above requirement, then it is evaluated into a temporary before being passed to the function.\n  * Here are some examples:\n  * \\code\n  * MatrixXf A;\n  * VectorXf a;\n  * foo1(a.head());             // OK\n  * foo1(A.col());              // OK\n  * foo1(A.row());              // Compilation error because here innerstride!=1\n  * foo2(A.row());              // Compilation error because A.row() is a 1xN object while foo2 is expecting a Nx1 object\n  * foo2(A.row().transpose());  // The row is copied into a contiguous temporary\n  * foo2(2*a);                  // The expression is evaluated into a temporary\n  * foo2(A.col().segment(2,4)); // No temporary\n  * \\endcode\n  *\n  * The range of inputs that can be referenced without temporary can be enlarged using the last two template parameters.\n  * Here is an example accepting an innerstride!=1:\n  * \\code\n  * // in-out argument:\n  * void foo3(Ref<VectorXf,0,InnerStride<> > x);\n  * foo3(A.row());              // OK\n  * \\endcode\n  * The downside here is that the function foo3 might be significantly slower than foo1 because it won't be able to exploit vectorization, and will involve more\n  * expensive address computations even if the input is contiguously stored in memory. To overcome this issue, one might propose to overload internally calling a\n  * template function, e.g.:\n  * \\code\n  * // in the .h:\n  * void foo(const Ref<MatrixXf>& A);\n  * void foo(const Ref<MatrixXf,0,Stride<> >& A);\n  *\n  * // in the .cpp:\n  * template<typename TypeOfA> void foo_impl(const TypeOfA& A) {\n  *     ... // crazy code goes here\n  * }\n  * void foo(const Ref<MatrixXf>& A) { foo_impl(A); }\n  * void foo(const Ref<MatrixXf,0,Stride<> >& A) { foo_impl(A); }\n  * \\endcode\n  *\n  *\n  * \\sa PlainObjectBase::Map(), \\ref TopicStorageOrders\n  */\ntemplate<typename PlainObjectType, int Options, typename StrideType> class Ref\n  : public RefBase<Ref<PlainObjectType, Options, StrideType> >\n{\n  private:\n    typedef internal::traits<Ref> Traits;\n    template<typename Derived>\n    EIGEN_DEVICE_FUNC inline Ref(const PlainObjectBase<Derived>& expr,\n                                 typename internal::enable_if<bool(Traits::template match<Derived>::MatchAtCompileTime),Derived>::type* = 0);\n  public:\n\n    typedef RefBase<Ref> Base;\n    EIGEN_DENSE_PUBLIC_INTERFACE(Ref)\n\n\n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    template<typename Derived>\n    EIGEN_DEVICE_FUNC inline Ref(PlainObjectBase<Derived>& expr,\n                                 typename internal::enable_if<bool(Traits::template match<Derived>::MatchAtCompileTime),Derived>::type* = 0)\n    {\n      EIGEN_STATIC_ASSERT(bool(Traits::template match<Derived>::MatchAtCompileTime), STORAGE_LAYOUT_DOES_NOT_MATCH);\n      Base::construct(expr.derived());\n    }\n    template<typename Derived>\n    EIGEN_DEVICE_FUNC inline Ref(const DenseBase<Derived>& expr,\n                                 typename internal::enable_if<bool(Traits::template match<Derived>::MatchAtCompileTime),Derived>::type* = 0)\n    #else\n    /** Implicit constructor from any dense expression */\n    template<typename Derived>\n    inline Ref(DenseBase<Derived>& expr)\n    #endif\n    {\n      EIGEN_STATIC_ASSERT(bool(internal::is_lvalue<Derived>::value), THIS_EXPRESSION_IS_NOT_A_LVALUE__IT_IS_READ_ONLY);\n      EIGEN_STATIC_ASSERT(bool(Traits::template match<Derived>::MatchAtCompileTime), STORAGE_LAYOUT_DOES_NOT_MATCH);\n      EIGEN_STATIC_ASSERT(!Derived::IsPlainObjectBase,THIS_EXPRESSION_IS_NOT_A_LVALUE__IT_IS_READ_ONLY);\n      Base::construct(expr.const_cast_derived());\n    }\n\n    EIGEN_INHERIT_ASSIGNMENT_OPERATORS(Ref)\n\n};\n\n// this is the const ref version\ntemplate<typename TPlainObjectType, int Options, typename StrideType> class Ref<const TPlainObjectType, Options, StrideType>\n  : public RefBase<Ref<const TPlainObjectType, Options, StrideType> >\n{\n    typedef internal::traits<Ref> Traits;\n  public:\n\n    typedef RefBase<Ref> Base;\n    EIGEN_DENSE_PUBLIC_INTERFACE(Ref)\n\n    template<typename Derived>\n    EIGEN_DEVICE_FUNC inline Ref(const DenseBase<Derived>& expr,\n                                 typename internal::enable_if<bool(Traits::template match<Derived>::ScalarTypeMatch),Derived>::type* = 0)\n    {\n//      std::cout << match_helper<Derived>::HasDirectAccess << \",\" << match_helper<Derived>::OuterStrideMatch << \",\" << match_helper<Derived>::InnerStrideMatch << \"\\n\";\n//      std::cout << int(StrideType::OuterStrideAtCompileTime) << \" - \" << int(Derived::OuterStrideAtCompileTime) << \"\\n\";\n//      std::cout << int(StrideType::InnerStrideAtCompileTime) << \" - \" << int(Derived::InnerStrideAtCompileTime) << \"\\n\";\n      construct(expr.derived(), typename Traits::template match<Derived>::type());\n    }\n\n    EIGEN_DEVICE_FUNC inline Ref(const Ref& other) : Base(other) {\n      // copy constructor shall not copy the m_object, to avoid unnecessary malloc and copy\n    }\n\n    template<typename OtherRef>\n    EIGEN_DEVICE_FUNC inline Ref(const RefBase<OtherRef>& other) {\n      construct(other.derived(), typename Traits::template match<OtherRef>::type());\n    }\n\n  protected:\n\n    template<typename Expression>\n    EIGEN_DEVICE_FUNC void construct(const Expression& expr,internal::true_type)\n    {\n      Base::construct(expr);\n    }\n\n    template<typename Expression>\n    EIGEN_DEVICE_FUNC void construct(const Expression& expr, internal::false_type)\n    {\n      internal::call_assignment_no_alias(m_object,expr,internal::assign_op<Scalar,Scalar>());\n      Base::construct(m_object);\n    }\n\n  protected:\n    TPlainObjectType m_object;\n};\n\n} // end namespace Eigen\n\n#endif // EIGEN_REF_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/Replicate.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009-2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_REPLICATE_H\n#define EIGEN_REPLICATE_H\n\nnamespace Eigen { \n\nnamespace internal {\ntemplate<typename MatrixType,int RowFactor,int ColFactor>\nstruct traits<Replicate<MatrixType,RowFactor,ColFactor> >\n : traits<MatrixType>\n{\n  typedef typename MatrixType::Scalar Scalar;\n  typedef typename traits<MatrixType>::StorageKind StorageKind;\n  typedef typename traits<MatrixType>::XprKind XprKind;\n  typedef typename ref_selector<MatrixType>::type MatrixTypeNested;\n  typedef typename remove_reference<MatrixTypeNested>::type _MatrixTypeNested;\n  enum {\n    RowsAtCompileTime = RowFactor==Dynamic || int(MatrixType::RowsAtCompileTime)==Dynamic\n                      ? Dynamic\n                      : RowFactor * MatrixType::RowsAtCompileTime,\n    ColsAtCompileTime = ColFactor==Dynamic || int(MatrixType::ColsAtCompileTime)==Dynamic\n                      ? Dynamic\n                      : ColFactor * MatrixType::ColsAtCompileTime,\n   //FIXME we don't propagate the max sizes !!!\n    MaxRowsAtCompileTime = RowsAtCompileTime,\n    MaxColsAtCompileTime = ColsAtCompileTime,\n    IsRowMajor = MaxRowsAtCompileTime==1 && MaxColsAtCompileTime!=1 ? 1\n               : MaxColsAtCompileTime==1 && MaxRowsAtCompileTime!=1 ? 0\n               : (MatrixType::Flags & RowMajorBit) ? 1 : 0,\n    \n    // FIXME enable DirectAccess with negative strides?\n    Flags = IsRowMajor ? RowMajorBit : 0\n  };\n};\n}\n\n/**\n  * \\class Replicate\n  * \\ingroup Core_Module\n  *\n  * \\brief Expression of the multiple replication of a matrix or vector\n  *\n  * \\tparam MatrixType the type of the object we are replicating\n  * \\tparam RowFactor number of repetitions at compile time along the vertical direction, can be Dynamic.\n  * \\tparam ColFactor number of repetitions at compile time along the horizontal direction, can be Dynamic.\n  *\n  * This class represents an expression of the multiple replication of a matrix or vector.\n  * It is the return type of DenseBase::replicate() and most of the time\n  * this is the only way it is used.\n  *\n  * \\sa DenseBase::replicate()\n  */\ntemplate<typename MatrixType,int RowFactor,int ColFactor> class Replicate\n  : public internal::dense_xpr_base< Replicate<MatrixType,RowFactor,ColFactor> >::type\n{\n    typedef typename internal::traits<Replicate>::MatrixTypeNested MatrixTypeNested;\n    typedef typename internal::traits<Replicate>::_MatrixTypeNested _MatrixTypeNested;\n  public:\n\n    typedef typename internal::dense_xpr_base<Replicate>::type Base;\n    EIGEN_DENSE_PUBLIC_INTERFACE(Replicate)\n    typedef typename internal::remove_all<MatrixType>::type NestedExpression;\n\n    template<typename OriginalMatrixType>\n    EIGEN_DEVICE_FUNC\n    inline explicit Replicate(const OriginalMatrixType& matrix)\n      : m_matrix(matrix), m_rowFactor(RowFactor), m_colFactor(ColFactor)\n    {\n      EIGEN_STATIC_ASSERT((internal::is_same<typename internal::remove_const<MatrixType>::type,OriginalMatrixType>::value),\n                          THE_MATRIX_OR_EXPRESSION_THAT_YOU_PASSED_DOES_NOT_HAVE_THE_EXPECTED_TYPE)\n      eigen_assert(RowFactor!=Dynamic && ColFactor!=Dynamic);\n    }\n\n    template<typename OriginalMatrixType>\n    EIGEN_DEVICE_FUNC\n    inline Replicate(const OriginalMatrixType& matrix, Index rowFactor, Index colFactor)\n      : m_matrix(matrix), m_rowFactor(rowFactor), m_colFactor(colFactor)\n    {\n      EIGEN_STATIC_ASSERT((internal::is_same<typename internal::remove_const<MatrixType>::type,OriginalMatrixType>::value),\n                          THE_MATRIX_OR_EXPRESSION_THAT_YOU_PASSED_DOES_NOT_HAVE_THE_EXPECTED_TYPE)\n    }\n\n    EIGEN_DEVICE_FUNC\n    inline Index rows() const { return m_matrix.rows() * m_rowFactor.value(); }\n    EIGEN_DEVICE_FUNC\n    inline Index cols() const { return m_matrix.cols() * m_colFactor.value(); }\n\n    EIGEN_DEVICE_FUNC\n    const _MatrixTypeNested& nestedExpression() const\n    { \n      return m_matrix; \n    }\n\n  protected:\n    MatrixTypeNested m_matrix;\n    const internal::variable_if_dynamic<Index, RowFactor> m_rowFactor;\n    const internal::variable_if_dynamic<Index, ColFactor> m_colFactor;\n};\n\n/**\n  * \\return an expression of the replication of \\c *this\n  *\n  * Example: \\include MatrixBase_replicate.cpp\n  * Output: \\verbinclude MatrixBase_replicate.out\n  *\n  * \\sa VectorwiseOp::replicate(), DenseBase::replicate(Index,Index), class Replicate\n  */\ntemplate<typename Derived>\ntemplate<int RowFactor, int ColFactor>\nconst Replicate<Derived,RowFactor,ColFactor>\nDenseBase<Derived>::replicate() const\n{\n  return Replicate<Derived,RowFactor,ColFactor>(derived());\n}\n\n/**\n  * \\return an expression of the replication of each column (or row) of \\c *this\n  *\n  * Example: \\include DirectionWise_replicate_int.cpp\n  * Output: \\verbinclude DirectionWise_replicate_int.out\n  *\n  * \\sa VectorwiseOp::replicate(), DenseBase::replicate(), class Replicate\n  */\ntemplate<typename ExpressionType, int Direction>\nconst typename VectorwiseOp<ExpressionType,Direction>::ReplicateReturnType\nVectorwiseOp<ExpressionType,Direction>::replicate(Index factor) const\n{\n  return typename VectorwiseOp<ExpressionType,Direction>::ReplicateReturnType\n          (_expression(),Direction==Vertical?factor:1,Direction==Horizontal?factor:1);\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_REPLICATE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/ReturnByValue.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009-2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2009-2010 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_RETURNBYVALUE_H\n#define EIGEN_RETURNBYVALUE_H\n\nnamespace Eigen {\n\nnamespace internal {\n\ntemplate<typename Derived>\nstruct traits<ReturnByValue<Derived> >\n  : public traits<typename traits<Derived>::ReturnType>\n{\n  enum {\n    // We're disabling the DirectAccess because e.g. the constructor of\n    // the Block-with-DirectAccess expression requires to have a coeffRef method.\n    // Also, we don't want to have to implement the stride stuff.\n    Flags = (traits<typename traits<Derived>::ReturnType>::Flags\n             | EvalBeforeNestingBit) & ~DirectAccessBit\n  };\n};\n\n/* The ReturnByValue object doesn't even have a coeff() method.\n * So the only way that nesting it in an expression can work, is by evaluating it into a plain matrix.\n * So internal::nested always gives the plain return matrix type.\n *\n * FIXME: I don't understand why we need this specialization: isn't this taken care of by the EvalBeforeNestingBit ??\n * Answer: EvalBeforeNestingBit should be deprecated since we have the evaluators\n */\ntemplate<typename Derived,int n,typename PlainObject>\nstruct nested_eval<ReturnByValue<Derived>, n, PlainObject>\n{\n  typedef typename traits<Derived>::ReturnType type;\n};\n\n} // end namespace internal\n\n/** \\class ReturnByValue\n  * \\ingroup Core_Module\n  *\n  */\ntemplate<typename Derived> class ReturnByValue\n  : public internal::dense_xpr_base< ReturnByValue<Derived> >::type, internal::no_assignment_operator\n{\n  public:\n    typedef typename internal::traits<Derived>::ReturnType ReturnType;\n\n    typedef typename internal::dense_xpr_base<ReturnByValue>::type Base;\n    EIGEN_DENSE_PUBLIC_INTERFACE(ReturnByValue)\n\n    template<typename Dest>\n    EIGEN_DEVICE_FUNC\n    inline void evalTo(Dest& dst) const\n    { static_cast<const Derived*>(this)->evalTo(dst); }\n    EIGEN_DEVICE_FUNC inline Index rows() const { return static_cast<const Derived*>(this)->rows(); }\n    EIGEN_DEVICE_FUNC inline Index cols() const { return static_cast<const Derived*>(this)->cols(); }\n\n#ifndef EIGEN_PARSED_BY_DOXYGEN\n#define Unusable YOU_ARE_TRYING_TO_ACCESS_A_SINGLE_COEFFICIENT_IN_A_SPECIAL_EXPRESSION_WHERE_THAT_IS_NOT_ALLOWED_BECAUSE_THAT_WOULD_BE_INEFFICIENT\n    class Unusable{\n      Unusable(const Unusable&) {}\n      Unusable& operator=(const Unusable&) {return *this;}\n    };\n    const Unusable& coeff(Index) const { return *reinterpret_cast<const Unusable*>(this); }\n    const Unusable& coeff(Index,Index) const { return *reinterpret_cast<const Unusable*>(this); }\n    Unusable& coeffRef(Index) { return *reinterpret_cast<Unusable*>(this); }\n    Unusable& coeffRef(Index,Index) { return *reinterpret_cast<Unusable*>(this); }\n#undef Unusable\n#endif\n};\n\ntemplate<typename Derived>\ntemplate<typename OtherDerived>\nDerived& DenseBase<Derived>::operator=(const ReturnByValue<OtherDerived>& other)\n{\n  other.evalTo(derived());\n  return derived();\n}\n\nnamespace internal {\n\n// Expression is evaluated in a temporary; default implementation of Assignment is bypassed so that\n// when a ReturnByValue expression is assigned, the evaluator is not constructed.\n// TODO: Finalize port to new regime; ReturnByValue should not exist in the expression world\n  \ntemplate<typename Derived>\nstruct evaluator<ReturnByValue<Derived> >\n  : public evaluator<typename internal::traits<Derived>::ReturnType>\n{\n  typedef ReturnByValue<Derived> XprType;\n  typedef typename internal::traits<Derived>::ReturnType PlainObject;\n  typedef evaluator<PlainObject> Base;\n  \n  EIGEN_DEVICE_FUNC explicit evaluator(const XprType& xpr)\n    : m_result(xpr.rows(), xpr.cols())\n  {\n    ::new (static_cast<Base*>(this)) Base(m_result);\n    xpr.evalTo(m_result);\n  }\n\nprotected:\n  PlainObject m_result;\n};\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_RETURNBYVALUE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/Reverse.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2006-2008 Benoit Jacob <jacob.benoit.1@gmail.com>\n// Copyright (C) 2009 Ricard Marxer <email@ricardmarxer.com>\n// Copyright (C) 2009-2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_REVERSE_H\n#define EIGEN_REVERSE_H\n\nnamespace Eigen { \n\nnamespace internal {\n\ntemplate<typename MatrixType, int Direction>\nstruct traits<Reverse<MatrixType, Direction> >\n : traits<MatrixType>\n{\n  typedef typename MatrixType::Scalar Scalar;\n  typedef typename traits<MatrixType>::StorageKind StorageKind;\n  typedef typename traits<MatrixType>::XprKind XprKind;\n  typedef typename ref_selector<MatrixType>::type MatrixTypeNested;\n  typedef typename remove_reference<MatrixTypeNested>::type _MatrixTypeNested;\n  enum {\n    RowsAtCompileTime = MatrixType::RowsAtCompileTime,\n    ColsAtCompileTime = MatrixType::ColsAtCompileTime,\n    MaxRowsAtCompileTime = MatrixType::MaxRowsAtCompileTime,\n    MaxColsAtCompileTime = MatrixType::MaxColsAtCompileTime,\n    Flags = _MatrixTypeNested::Flags & (RowMajorBit | LvalueBit)\n  };\n};\n\ntemplate<typename PacketType, bool ReversePacket> struct reverse_packet_cond\n{\n  static inline PacketType run(const PacketType& x) { return preverse(x); }\n};\n\ntemplate<typename PacketType> struct reverse_packet_cond<PacketType,false>\n{\n  static inline PacketType run(const PacketType& x) { return x; }\n};\n\n} // end namespace internal \n\n/** \\class Reverse\n  * \\ingroup Core_Module\n  *\n  * \\brief Expression of the reverse of a vector or matrix\n  *\n  * \\tparam MatrixType the type of the object of which we are taking the reverse\n  * \\tparam Direction defines the direction of the reverse operation, can be Vertical, Horizontal, or BothDirections\n  *\n  * This class represents an expression of the reverse of a vector.\n  * It is the return type of MatrixBase::reverse() and VectorwiseOp::reverse()\n  * and most of the time this is the only way it is used.\n  *\n  * \\sa MatrixBase::reverse(), VectorwiseOp::reverse()\n  */\ntemplate<typename MatrixType, int Direction> class Reverse\n  : public internal::dense_xpr_base< Reverse<MatrixType, Direction> >::type\n{\n  public:\n\n    typedef typename internal::dense_xpr_base<Reverse>::type Base;\n    EIGEN_DENSE_PUBLIC_INTERFACE(Reverse)\n    typedef typename internal::remove_all<MatrixType>::type NestedExpression;\n    using Base::IsRowMajor;\n\n  protected:\n    enum {\n      PacketSize = internal::packet_traits<Scalar>::size,\n      IsColMajor = !IsRowMajor,\n      ReverseRow = (Direction == Vertical)   || (Direction == BothDirections),\n      ReverseCol = (Direction == Horizontal) || (Direction == BothDirections),\n      OffsetRow  = ReverseRow && IsColMajor ? PacketSize : 1,\n      OffsetCol  = ReverseCol && IsRowMajor ? PacketSize : 1,\n      ReversePacket = (Direction == BothDirections)\n                    || ((Direction == Vertical)   && IsColMajor)\n                    || ((Direction == Horizontal) && IsRowMajor)\n    };\n    typedef internal::reverse_packet_cond<PacketScalar,ReversePacket> reverse_packet;\n  public:\n\n    EIGEN_DEVICE_FUNC explicit inline Reverse(const MatrixType& matrix) : m_matrix(matrix) { }\n\n    EIGEN_INHERIT_ASSIGNMENT_OPERATORS(Reverse)\n\n    EIGEN_DEVICE_FUNC inline Index rows() const { return m_matrix.rows(); }\n    EIGEN_DEVICE_FUNC inline Index cols() const { return m_matrix.cols(); }\n\n    EIGEN_DEVICE_FUNC inline Index innerStride() const\n    {\n      return -m_matrix.innerStride();\n    }\n\n    EIGEN_DEVICE_FUNC const typename internal::remove_all<typename MatrixType::Nested>::type&\n    nestedExpression() const \n    {\n      return m_matrix;\n    }\n\n  protected:\n    typename MatrixType::Nested m_matrix;\n};\n\n/** \\returns an expression of the reverse of *this.\n  *\n  * Example: \\include MatrixBase_reverse.cpp\n  * Output: \\verbinclude MatrixBase_reverse.out\n  *\n  */\ntemplate<typename Derived>\ninline typename DenseBase<Derived>::ReverseReturnType\nDenseBase<Derived>::reverse()\n{\n  return ReverseReturnType(derived());\n}\n\n\n//reverse const overload moved DenseBase.h due to a CUDA compiler bug\n\n/** This is the \"in place\" version of reverse: it reverses \\c *this.\n  *\n  * In most cases it is probably better to simply use the reversed expression\n  * of a matrix. However, when reversing the matrix data itself is really needed,\n  * then this \"in-place\" version is probably the right choice because it provides\n  * the following additional benefits:\n  *  - less error prone: doing the same operation with .reverse() requires special care:\n  *    \\code m = m.reverse().eval(); \\endcode\n  *  - this API enables reverse operations without the need for a temporary\n  *  - it allows future optimizations (cache friendliness, etc.)\n  *\n  * \\sa VectorwiseOp::reverseInPlace(), reverse() */\ntemplate<typename Derived>\ninline void DenseBase<Derived>::reverseInPlace()\n{\n  if(cols()>rows())\n  {\n    Index half = cols()/2;\n    leftCols(half).swap(rightCols(half).reverse());\n    if((cols()%2)==1)\n    {\n      Index half2 = rows()/2;\n      col(half).head(half2).swap(col(half).tail(half2).reverse());\n    }\n  }\n  else\n  {\n    Index half = rows()/2;\n    topRows(half).swap(bottomRows(half).reverse());\n    if((rows()%2)==1)\n    {\n      Index half2 = cols()/2;\n      row(half).head(half2).swap(row(half).tail(half2).reverse());\n    }\n  }\n}\n\nnamespace internal {\n  \ntemplate<int Direction>\nstruct vectorwise_reverse_inplace_impl;\n\ntemplate<>\nstruct vectorwise_reverse_inplace_impl<Vertical>\n{\n  template<typename ExpressionType>\n  static void run(ExpressionType &xpr)\n  {\n    Index half = xpr.rows()/2;\n    xpr.topRows(half).swap(xpr.bottomRows(half).colwise().reverse());\n  }\n};\n\ntemplate<>\nstruct vectorwise_reverse_inplace_impl<Horizontal>\n{\n  template<typename ExpressionType>\n  static void run(ExpressionType &xpr)\n  {\n    Index half = xpr.cols()/2;\n    xpr.leftCols(half).swap(xpr.rightCols(half).rowwise().reverse());\n  }\n};\n\n} // end namespace internal\n\n/** This is the \"in place\" version of VectorwiseOp::reverse: it reverses each column or row of \\c *this.\n  *\n  * In most cases it is probably better to simply use the reversed expression\n  * of a matrix. However, when reversing the matrix data itself is really needed,\n  * then this \"in-place\" version is probably the right choice because it provides\n  * the following additional benefits:\n  *  - less error prone: doing the same operation with .reverse() requires special care:\n  *    \\code m = m.reverse().eval(); \\endcode\n  *  - this API enables reverse operations without the need for a temporary\n  *\n  * \\sa DenseBase::reverseInPlace(), reverse() */\ntemplate<typename ExpressionType, int Direction>\nvoid VectorwiseOp<ExpressionType,Direction>::reverseInPlace()\n{\n  internal::vectorwise_reverse_inplace_impl<Direction>::run(_expression().const_cast_derived());\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_REVERSE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/Select.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SELECT_H\n#define EIGEN_SELECT_H\n\nnamespace Eigen { \n\n/** \\class Select\n  * \\ingroup Core_Module\n  *\n  * \\brief Expression of a coefficient wise version of the C++ ternary operator ?:\n  *\n  * \\param ConditionMatrixType the type of the \\em condition expression which must be a boolean matrix\n  * \\param ThenMatrixType the type of the \\em then expression\n  * \\param ElseMatrixType the type of the \\em else expression\n  *\n  * This class represents an expression of a coefficient wise version of the C++ ternary operator ?:.\n  * It is the return type of DenseBase::select() and most of the time this is the only way it is used.\n  *\n  * \\sa DenseBase::select(const DenseBase<ThenDerived>&, const DenseBase<ElseDerived>&) const\n  */\n\nnamespace internal {\ntemplate<typename ConditionMatrixType, typename ThenMatrixType, typename ElseMatrixType>\nstruct traits<Select<ConditionMatrixType, ThenMatrixType, ElseMatrixType> >\n : traits<ThenMatrixType>\n{\n  typedef typename traits<ThenMatrixType>::Scalar Scalar;\n  typedef Dense StorageKind;\n  typedef typename traits<ThenMatrixType>::XprKind XprKind;\n  typedef typename ConditionMatrixType::Nested ConditionMatrixNested;\n  typedef typename ThenMatrixType::Nested ThenMatrixNested;\n  typedef typename ElseMatrixType::Nested ElseMatrixNested;\n  enum {\n    RowsAtCompileTime = ConditionMatrixType::RowsAtCompileTime,\n    ColsAtCompileTime = ConditionMatrixType::ColsAtCompileTime,\n    MaxRowsAtCompileTime = ConditionMatrixType::MaxRowsAtCompileTime,\n    MaxColsAtCompileTime = ConditionMatrixType::MaxColsAtCompileTime,\n    Flags = (unsigned int)ThenMatrixType::Flags & ElseMatrixType::Flags & RowMajorBit\n  };\n};\n}\n\ntemplate<typename ConditionMatrixType, typename ThenMatrixType, typename ElseMatrixType>\nclass Select : public internal::dense_xpr_base< Select<ConditionMatrixType, ThenMatrixType, ElseMatrixType> >::type,\n               internal::no_assignment_operator\n{\n  public:\n\n    typedef typename internal::dense_xpr_base<Select>::type Base;\n    EIGEN_DENSE_PUBLIC_INTERFACE(Select)\n\n    inline EIGEN_DEVICE_FUNC\n    Select(const ConditionMatrixType& a_conditionMatrix,\n           const ThenMatrixType& a_thenMatrix,\n           const ElseMatrixType& a_elseMatrix)\n      : m_condition(a_conditionMatrix), m_then(a_thenMatrix), m_else(a_elseMatrix)\n    {\n      eigen_assert(m_condition.rows() == m_then.rows() && m_condition.rows() == m_else.rows());\n      eigen_assert(m_condition.cols() == m_then.cols() && m_condition.cols() == m_else.cols());\n    }\n\n    inline EIGEN_DEVICE_FUNC Index rows() const { return m_condition.rows(); }\n    inline EIGEN_DEVICE_FUNC Index cols() const { return m_condition.cols(); }\n\n    inline EIGEN_DEVICE_FUNC\n    const Scalar coeff(Index i, Index j) const\n    {\n      if (m_condition.coeff(i,j))\n        return m_then.coeff(i,j);\n      else\n        return m_else.coeff(i,j);\n    }\n\n    inline EIGEN_DEVICE_FUNC\n    const Scalar coeff(Index i) const\n    {\n      if (m_condition.coeff(i))\n        return m_then.coeff(i);\n      else\n        return m_else.coeff(i);\n    }\n\n    inline EIGEN_DEVICE_FUNC const ConditionMatrixType& conditionMatrix() const\n    {\n      return m_condition;\n    }\n\n    inline EIGEN_DEVICE_FUNC const ThenMatrixType& thenMatrix() const\n    {\n      return m_then;\n    }\n\n    inline EIGEN_DEVICE_FUNC const ElseMatrixType& elseMatrix() const\n    {\n      return m_else;\n    }\n\n  protected:\n    typename ConditionMatrixType::Nested m_condition;\n    typename ThenMatrixType::Nested m_then;\n    typename ElseMatrixType::Nested m_else;\n};\n\n\n/** \\returns a matrix where each coefficient (i,j) is equal to \\a thenMatrix(i,j)\n  * if \\c *this(i,j), and \\a elseMatrix(i,j) otherwise.\n  *\n  * Example: \\include MatrixBase_select.cpp\n  * Output: \\verbinclude MatrixBase_select.out\n  *\n  * \\sa class Select\n  */\ntemplate<typename Derived>\ntemplate<typename ThenDerived,typename ElseDerived>\ninline const Select<Derived,ThenDerived,ElseDerived>\nDenseBase<Derived>::select(const DenseBase<ThenDerived>& thenMatrix,\n                            const DenseBase<ElseDerived>& elseMatrix) const\n{\n  return Select<Derived,ThenDerived,ElseDerived>(derived(), thenMatrix.derived(), elseMatrix.derived());\n}\n\n/** Version of DenseBase::select(const DenseBase&, const DenseBase&) with\n  * the \\em else expression being a scalar value.\n  *\n  * \\sa DenseBase::select(const DenseBase<ThenDerived>&, const DenseBase<ElseDerived>&) const, class Select\n  */\ntemplate<typename Derived>\ntemplate<typename ThenDerived>\ninline const Select<Derived,ThenDerived, typename ThenDerived::ConstantReturnType>\nDenseBase<Derived>::select(const DenseBase<ThenDerived>& thenMatrix,\n                           const typename ThenDerived::Scalar& elseScalar) const\n{\n  return Select<Derived,ThenDerived,typename ThenDerived::ConstantReturnType>(\n    derived(), thenMatrix.derived(), ThenDerived::Constant(rows(),cols(),elseScalar));\n}\n\n/** Version of DenseBase::select(const DenseBase&, const DenseBase&) with\n  * the \\em then expression being a scalar value.\n  *\n  * \\sa DenseBase::select(const DenseBase<ThenDerived>&, const DenseBase<ElseDerived>&) const, class Select\n  */\ntemplate<typename Derived>\ntemplate<typename ElseDerived>\ninline const Select<Derived, typename ElseDerived::ConstantReturnType, ElseDerived >\nDenseBase<Derived>::select(const typename ElseDerived::Scalar& thenScalar,\n                           const DenseBase<ElseDerived>& elseMatrix) const\n{\n  return Select<Derived,typename ElseDerived::ConstantReturnType,ElseDerived>(\n    derived(), ElseDerived::Constant(rows(),cols(),thenScalar), elseMatrix.derived());\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_SELECT_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/SelfAdjointView.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SELFADJOINTMATRIX_H\n#define EIGEN_SELFADJOINTMATRIX_H\n\nnamespace Eigen { \n\n/** \\class SelfAdjointView\n  * \\ingroup Core_Module\n  *\n  *\n  * \\brief Expression of a selfadjoint matrix from a triangular part of a dense matrix\n  *\n  * \\param MatrixType the type of the dense matrix storing the coefficients\n  * \\param TriangularPart can be either \\c #Lower or \\c #Upper\n  *\n  * This class is an expression of a sefladjoint matrix from a triangular part of a matrix\n  * with given dense storage of the coefficients. It is the return type of MatrixBase::selfadjointView()\n  * and most of the time this is the only way that it is used.\n  *\n  * \\sa class TriangularBase, MatrixBase::selfadjointView()\n  */\n\nnamespace internal {\ntemplate<typename MatrixType, unsigned int UpLo>\nstruct traits<SelfAdjointView<MatrixType, UpLo> > : traits<MatrixType>\n{\n  typedef typename ref_selector<MatrixType>::non_const_type MatrixTypeNested;\n  typedef typename remove_all<MatrixTypeNested>::type MatrixTypeNestedCleaned;\n  typedef MatrixType ExpressionType;\n  typedef typename MatrixType::PlainObject FullMatrixType;\n  enum {\n    Mode = UpLo | SelfAdjoint,\n    FlagsLvalueBit = is_lvalue<MatrixType>::value ? LvalueBit : 0,\n    Flags =  MatrixTypeNestedCleaned::Flags & (HereditaryBits|FlagsLvalueBit)\n           & (~(PacketAccessBit | DirectAccessBit | LinearAccessBit)) // FIXME these flags should be preserved\n  };\n};\n}\n\n// FIXME could also be called SelfAdjointWrapper to be consistent with DiagonalWrapper ??\ntemplate<typename _MatrixType, unsigned int UpLo> class SelfAdjointView\n  : public TriangularBase<SelfAdjointView<_MatrixType, UpLo> >\n{\n  public:\n\n    typedef _MatrixType MatrixType;\n    typedef TriangularBase<SelfAdjointView> Base;\n    typedef typename internal::traits<SelfAdjointView>::MatrixTypeNested MatrixTypeNested;\n    typedef typename internal::traits<SelfAdjointView>::MatrixTypeNestedCleaned MatrixTypeNestedCleaned;\n    typedef MatrixTypeNestedCleaned NestedExpression;\n\n    /** \\brief The type of coefficients in this matrix */\n    typedef typename internal::traits<SelfAdjointView>::Scalar Scalar; \n    typedef typename MatrixType::StorageIndex StorageIndex;\n\n    enum {\n      Mode = internal::traits<SelfAdjointView>::Mode,\n      Flags = internal::traits<SelfAdjointView>::Flags\n    };\n    typedef typename MatrixType::PlainObject PlainObject;\n\n    EIGEN_DEVICE_FUNC\n    explicit inline SelfAdjointView(MatrixType& matrix) : m_matrix(matrix)\n    {}\n\n    EIGEN_DEVICE_FUNC\n    inline Index rows() const { return m_matrix.rows(); }\n    EIGEN_DEVICE_FUNC\n    inline Index cols() const { return m_matrix.cols(); }\n    EIGEN_DEVICE_FUNC\n    inline Index outerStride() const { return m_matrix.outerStride(); }\n    EIGEN_DEVICE_FUNC\n    inline Index innerStride() const { return m_matrix.innerStride(); }\n\n    /** \\sa MatrixBase::coeff()\n      * \\warning the coordinates must fit into the referenced triangular part\n      */\n    EIGEN_DEVICE_FUNC\n    inline Scalar coeff(Index row, Index col) const\n    {\n      Base::check_coordinates_internal(row, col);\n      return m_matrix.coeff(row, col);\n    }\n\n    /** \\sa MatrixBase::coeffRef()\n      * \\warning the coordinates must fit into the referenced triangular part\n      */\n    EIGEN_DEVICE_FUNC\n    inline Scalar& coeffRef(Index row, Index col)\n    {\n      EIGEN_STATIC_ASSERT_LVALUE(SelfAdjointView);\n      Base::check_coordinates_internal(row, col);\n      return m_matrix.coeffRef(row, col);\n    }\n\n    /** \\internal */\n    EIGEN_DEVICE_FUNC\n    const MatrixTypeNestedCleaned& _expression() const { return m_matrix; }\n\n    EIGEN_DEVICE_FUNC\n    const MatrixTypeNestedCleaned& nestedExpression() const { return m_matrix; }\n    EIGEN_DEVICE_FUNC\n    MatrixTypeNestedCleaned& nestedExpression() { return m_matrix; }\n\n    /** Efficient triangular matrix times vector/matrix product */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    const Product<SelfAdjointView,OtherDerived>\n    operator*(const MatrixBase<OtherDerived>& rhs) const\n    {\n      return Product<SelfAdjointView,OtherDerived>(*this, rhs.derived());\n    }\n\n    /** Efficient vector/matrix times triangular matrix product */\n    template<typename OtherDerived> friend\n    EIGEN_DEVICE_FUNC\n    const Product<OtherDerived,SelfAdjointView>\n    operator*(const MatrixBase<OtherDerived>& lhs, const SelfAdjointView& rhs)\n    {\n      return Product<OtherDerived,SelfAdjointView>(lhs.derived(),rhs);\n    }\n    \n    friend EIGEN_DEVICE_FUNC\n    const SelfAdjointView<const EIGEN_SCALAR_BINARYOP_EXPR_RETURN_TYPE(Scalar,MatrixType,product),UpLo>\n    operator*(const Scalar& s, const SelfAdjointView& mat)\n    {\n      return (s*mat.nestedExpression()).template selfadjointView<UpLo>();\n    }\n\n    /** Perform a symmetric rank 2 update of the selfadjoint matrix \\c *this:\n      * \\f$ this = this + \\alpha u v^* + conj(\\alpha) v u^* \\f$\n      * \\returns a reference to \\c *this\n      *\n      * The vectors \\a u and \\c v \\b must be column vectors, however they can be\n      * a adjoint expression without any overhead. Only the meaningful triangular\n      * part of the matrix is updated, the rest is left unchanged.\n      *\n      * \\sa rankUpdate(const MatrixBase<DerivedU>&, Scalar)\n      */\n    template<typename DerivedU, typename DerivedV>\n    EIGEN_DEVICE_FUNC\n    SelfAdjointView& rankUpdate(const MatrixBase<DerivedU>& u, const MatrixBase<DerivedV>& v, const Scalar& alpha = Scalar(1));\n\n    /** Perform a symmetric rank K update of the selfadjoint matrix \\c *this:\n      * \\f$ this = this + \\alpha ( u u^* ) \\f$ where \\a u is a vector or matrix.\n      *\n      * \\returns a reference to \\c *this\n      *\n      * Note that to perform \\f$ this = this + \\alpha ( u^* u ) \\f$ you can simply\n      * call this function with u.adjoint().\n      *\n      * \\sa rankUpdate(const MatrixBase<DerivedU>&, const MatrixBase<DerivedV>&, Scalar)\n      */\n    template<typename DerivedU>\n    EIGEN_DEVICE_FUNC\n    SelfAdjointView& rankUpdate(const MatrixBase<DerivedU>& u, const Scalar& alpha = Scalar(1));\n\n    /** \\returns an expression of a triangular view extracted from the current selfadjoint view of a given triangular part\n      *\n      * The parameter \\a TriMode can have the following values: \\c #Upper, \\c #StrictlyUpper, \\c #UnitUpper,\n      * \\c #Lower, \\c #StrictlyLower, \\c #UnitLower.\n      *\n      * If \\c TriMode references the same triangular part than \\c *this, then this method simply return a \\c TriangularView of the nested expression,\n      * otherwise, the nested expression is first transposed, thus returning a \\c TriangularView<Transpose<MatrixType>> object.\n      *\n      * \\sa MatrixBase::triangularView(), class TriangularView\n      */\n    template<unsigned int TriMode>\n    EIGEN_DEVICE_FUNC\n    typename internal::conditional<(TriMode&(Upper|Lower))==(UpLo&(Upper|Lower)),\n                                   TriangularView<MatrixType,TriMode>,\n                                   TriangularView<typename MatrixType::AdjointReturnType,TriMode> >::type\n    triangularView() const\n    {\n      typename internal::conditional<(TriMode&(Upper|Lower))==(UpLo&(Upper|Lower)), MatrixType&, typename MatrixType::ConstTransposeReturnType>::type tmp1(m_matrix);\n      typename internal::conditional<(TriMode&(Upper|Lower))==(UpLo&(Upper|Lower)), MatrixType&, typename MatrixType::AdjointReturnType>::type tmp2(tmp1);\n      return typename internal::conditional<(TriMode&(Upper|Lower))==(UpLo&(Upper|Lower)),\n                                   TriangularView<MatrixType,TriMode>,\n                                   TriangularView<typename MatrixType::AdjointReturnType,TriMode> >::type(tmp2);\n    }\n\n    /** \\returns a const expression of the main diagonal of the matrix \\c *this\n      *\n      * This method simply returns the diagonal of the nested expression, thus by-passing the SelfAdjointView decorator.\n      *\n      * \\sa MatrixBase::diagonal(), class Diagonal */\n    EIGEN_DEVICE_FUNC\n    typename MatrixType::ConstDiagonalReturnType diagonal() const\n    {\n      return typename MatrixType::ConstDiagonalReturnType(m_matrix);\n    }\n\n/////////// Cholesky module ///////////\n\n    const LLT<PlainObject, UpLo> llt() const;\n    const LDLT<PlainObject, UpLo> ldlt() const;\n\n/////////// Eigenvalue module ///////////\n\n    /** Real part of #Scalar */\n    typedef typename NumTraits<Scalar>::Real RealScalar;\n    /** Return type of eigenvalues() */\n    typedef Matrix<RealScalar, internal::traits<MatrixType>::ColsAtCompileTime, 1> EigenvaluesReturnType;\n\n    EIGEN_DEVICE_FUNC\n    EigenvaluesReturnType eigenvalues() const;\n    EIGEN_DEVICE_FUNC\n    RealScalar operatorNorm() const;\n\n  protected:\n    MatrixTypeNested m_matrix;\n};\n\n\n// template<typename OtherDerived, typename MatrixType, unsigned int UpLo>\n// internal::selfadjoint_matrix_product_returntype<OtherDerived,SelfAdjointView<MatrixType,UpLo> >\n// operator*(const MatrixBase<OtherDerived>& lhs, const SelfAdjointView<MatrixType,UpLo>& rhs)\n// {\n//   return internal::matrix_selfadjoint_product_returntype<OtherDerived,SelfAdjointView<MatrixType,UpLo> >(lhs.derived(),rhs);\n// }\n\n// selfadjoint to dense matrix\n\nnamespace internal {\n\n// TODO currently a selfadjoint expression has the form SelfAdjointView<.,.>\n//      in the future selfadjoint-ness should be defined by the expression traits\n//      such that Transpose<SelfAdjointView<.,.> > is valid. (currently TriangularBase::transpose() is overloaded to make it work)\ntemplate<typename MatrixType, unsigned int Mode>\nstruct evaluator_traits<SelfAdjointView<MatrixType,Mode> >\n{\n  typedef typename storage_kind_to_evaluator_kind<typename MatrixType::StorageKind>::Kind Kind;\n  typedef SelfAdjointShape Shape;\n};\n\ntemplate<int UpLo, int SetOpposite, typename DstEvaluatorTypeT, typename SrcEvaluatorTypeT, typename Functor, int Version>\nclass triangular_dense_assignment_kernel<UpLo,SelfAdjoint,SetOpposite,DstEvaluatorTypeT,SrcEvaluatorTypeT,Functor,Version>\n  : public generic_dense_assignment_kernel<DstEvaluatorTypeT, SrcEvaluatorTypeT, Functor, Version>\n{\nprotected:\n  typedef generic_dense_assignment_kernel<DstEvaluatorTypeT, SrcEvaluatorTypeT, Functor, Version> Base;\n  typedef typename Base::DstXprType DstXprType;\n  typedef typename Base::SrcXprType SrcXprType;\n  using Base::m_dst;\n  using Base::m_src;\n  using Base::m_functor;\npublic:\n  \n  typedef typename Base::DstEvaluatorType DstEvaluatorType;\n  typedef typename Base::SrcEvaluatorType SrcEvaluatorType;\n  typedef typename Base::Scalar Scalar;\n  typedef typename Base::AssignmentTraits AssignmentTraits;\n  \n  \n  EIGEN_DEVICE_FUNC triangular_dense_assignment_kernel(DstEvaluatorType &dst, const SrcEvaluatorType &src, const Functor &func, DstXprType& dstExpr)\n    : Base(dst, src, func, dstExpr)\n  {}\n  \n  EIGEN_DEVICE_FUNC void assignCoeff(Index row, Index col)\n  {\n    eigen_internal_assert(row!=col);\n    Scalar tmp = m_src.coeff(row,col);\n    m_functor.assignCoeff(m_dst.coeffRef(row,col), tmp);\n    m_functor.assignCoeff(m_dst.coeffRef(col,row), numext::conj(tmp));\n  }\n  \n  EIGEN_DEVICE_FUNC void assignDiagonalCoeff(Index id)\n  {\n    Base::assignCoeff(id,id);\n  }\n  \n  EIGEN_DEVICE_FUNC void assignOppositeCoeff(Index, Index)\n  { eigen_internal_assert(false && \"should never be called\"); }\n};\n\n} // end namespace internal\n\n/***************************************************************************\n* Implementation of MatrixBase methods\n***************************************************************************/\n\ntemplate<typename Derived>\ntemplate<unsigned int UpLo>\ntypename MatrixBase<Derived>::template ConstSelfAdjointViewReturnType<UpLo>::Type\nMatrixBase<Derived>::selfadjointView() const\n{\n  return typename ConstSelfAdjointViewReturnType<UpLo>::Type(derived());\n}\n\ntemplate<typename Derived>\ntemplate<unsigned int UpLo>\ntypename MatrixBase<Derived>::template SelfAdjointViewReturnType<UpLo>::Type\nMatrixBase<Derived>::selfadjointView()\n{\n  return typename SelfAdjointViewReturnType<UpLo>::Type(derived());\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_SELFADJOINTMATRIX_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/SelfCwiseBinaryOp.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009-2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SELFCWISEBINARYOP_H\n#define EIGEN_SELFCWISEBINARYOP_H\n\nnamespace Eigen { \n\n// TODO generalize the scalar type of 'other'\n\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE Derived& DenseBase<Derived>::operator*=(const Scalar& other)\n{\n  typedef typename Derived::PlainObject PlainObject;\n  internal::call_assignment(this->derived(), PlainObject::Constant(rows(),cols(),other), internal::mul_assign_op<Scalar,Scalar>());\n  return derived();\n}\n\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE Derived& ArrayBase<Derived>::operator+=(const Scalar& other)\n{\n  typedef typename Derived::PlainObject PlainObject;\n  internal::call_assignment(this->derived(), PlainObject::Constant(rows(),cols(),other), internal::add_assign_op<Scalar,Scalar>());\n  return derived();\n}\n\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE Derived& ArrayBase<Derived>::operator-=(const Scalar& other)\n{\n  typedef typename Derived::PlainObject PlainObject;\n  internal::call_assignment(this->derived(), PlainObject::Constant(rows(),cols(),other), internal::sub_assign_op<Scalar,Scalar>());\n  return derived();\n}\n\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE Derived& DenseBase<Derived>::operator/=(const Scalar& other)\n{\n  typedef typename Derived::PlainObject PlainObject;\n  internal::call_assignment(this->derived(), PlainObject::Constant(rows(),cols(),other), internal::div_assign_op<Scalar,Scalar>());\n  return derived();\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_SELFCWISEBINARYOP_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/Solve.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2014 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SOLVE_H\n#define EIGEN_SOLVE_H\n\nnamespace Eigen {\n\ntemplate<typename Decomposition, typename RhsType, typename StorageKind> class SolveImpl;\n  \n/** \\class Solve\n  * \\ingroup Core_Module\n  *\n  * \\brief Pseudo expression representing a solving operation\n  *\n  * \\tparam Decomposition the type of the matrix or decomposion object\n  * \\tparam Rhstype the type of the right-hand side\n  *\n  * This class represents an expression of A.solve(B)\n  * and most of the time this is the only way it is used.\n  *\n  */\nnamespace internal {\n\n// this solve_traits class permits to determine the evaluation type with respect to storage kind (Dense vs Sparse)\ntemplate<typename Decomposition, typename RhsType,typename StorageKind> struct solve_traits;\n\ntemplate<typename Decomposition, typename RhsType>\nstruct solve_traits<Decomposition,RhsType,Dense>\n{\n  typedef Matrix<typename RhsType::Scalar,\n                 Decomposition::ColsAtCompileTime,\n                 RhsType::ColsAtCompileTime,\n                 RhsType::PlainObject::Options,\n                 Decomposition::MaxColsAtCompileTime,\n                 RhsType::MaxColsAtCompileTime> PlainObject;  \n};\n\ntemplate<typename Decomposition, typename RhsType>\nstruct traits<Solve<Decomposition, RhsType> >\n  : traits<typename solve_traits<Decomposition,RhsType,typename internal::traits<RhsType>::StorageKind>::PlainObject>\n{\n  typedef typename solve_traits<Decomposition,RhsType,typename internal::traits<RhsType>::StorageKind>::PlainObject PlainObject;\n  typedef typename promote_index_type<typename Decomposition::StorageIndex, typename RhsType::StorageIndex>::type StorageIndex;\n  typedef traits<PlainObject> BaseTraits;\n  enum {\n    Flags = BaseTraits::Flags & RowMajorBit,\n    CoeffReadCost = HugeCost\n  };\n};\n\n}\n\n\ntemplate<typename Decomposition, typename RhsType>\nclass Solve : public SolveImpl<Decomposition,RhsType,typename internal::traits<RhsType>::StorageKind>\n{\npublic:\n  typedef typename internal::traits<Solve>::PlainObject PlainObject;\n  typedef typename internal::traits<Solve>::StorageIndex StorageIndex;\n  \n  Solve(const Decomposition &dec, const RhsType &rhs)\n    : m_dec(dec), m_rhs(rhs)\n  {}\n  \n  EIGEN_DEVICE_FUNC Index rows() const { return m_dec.cols(); }\n  EIGEN_DEVICE_FUNC Index cols() const { return m_rhs.cols(); }\n\n  EIGEN_DEVICE_FUNC const Decomposition& dec() const { return m_dec; }\n  EIGEN_DEVICE_FUNC const RhsType&       rhs() const { return m_rhs; }\n\nprotected:\n  const Decomposition &m_dec;\n  const RhsType       &m_rhs;\n};\n\n\n// Specialization of the Solve expression for dense results\ntemplate<typename Decomposition, typename RhsType>\nclass SolveImpl<Decomposition,RhsType,Dense>\n  : public MatrixBase<Solve<Decomposition,RhsType> >\n{\n  typedef Solve<Decomposition,RhsType> Derived;\n  \npublic:\n  \n  typedef MatrixBase<Solve<Decomposition,RhsType> > Base;\n  EIGEN_DENSE_PUBLIC_INTERFACE(Derived)\n\nprivate:\n  \n  Scalar coeff(Index row, Index col) const;\n  Scalar coeff(Index i) const;\n};\n\n// Generic API dispatcher\ntemplate<typename Decomposition, typename RhsType, typename StorageKind>\nclass SolveImpl : public internal::generic_xpr_base<Solve<Decomposition,RhsType>, MatrixXpr, StorageKind>::type\n{\n  public:\n    typedef typename internal::generic_xpr_base<Solve<Decomposition,RhsType>, MatrixXpr, StorageKind>::type Base;\n};\n\nnamespace internal {\n\n// Evaluator of Solve -> eval into a temporary\ntemplate<typename Decomposition, typename RhsType>\nstruct evaluator<Solve<Decomposition,RhsType> >\n  : public evaluator<typename Solve<Decomposition,RhsType>::PlainObject>\n{\n  typedef Solve<Decomposition,RhsType> SolveType;\n  typedef typename SolveType::PlainObject PlainObject;\n  typedef evaluator<PlainObject> Base;\n\n  enum { Flags = Base::Flags | EvalBeforeNestingBit };\n  \n  EIGEN_DEVICE_FUNC explicit evaluator(const SolveType& solve)\n    : m_result(solve.rows(), solve.cols())\n  {\n    ::new (static_cast<Base*>(this)) Base(m_result);\n    solve.dec()._solve_impl(solve.rhs(), m_result);\n  }\n  \nprotected:  \n  PlainObject m_result;\n};\n\n// Specialization for \"dst = dec.solve(rhs)\"\n// NOTE we need to specialize it for Dense2Dense to avoid ambiguous specialization error and a Sparse2Sparse specialization must exist somewhere\ntemplate<typename DstXprType, typename DecType, typename RhsType, typename Scalar>\nstruct Assignment<DstXprType, Solve<DecType,RhsType>, internal::assign_op<Scalar,Scalar>, Dense2Dense>\n{\n  typedef Solve<DecType,RhsType> SrcXprType;\n  static void run(DstXprType &dst, const SrcXprType &src, const internal::assign_op<Scalar,Scalar> &)\n  {\n    Index dstRows = src.rows();\n    Index dstCols = src.cols();\n    if((dst.rows()!=dstRows) || (dst.cols()!=dstCols))\n      dst.resize(dstRows, dstCols);\n\n    src.dec()._solve_impl(src.rhs(), dst);\n  }\n};\n\n// Specialization for \"dst = dec.transpose().solve(rhs)\"\ntemplate<typename DstXprType, typename DecType, typename RhsType, typename Scalar>\nstruct Assignment<DstXprType, Solve<Transpose<const DecType>,RhsType>, internal::assign_op<Scalar,Scalar>, Dense2Dense>\n{\n  typedef Solve<Transpose<const DecType>,RhsType> SrcXprType;\n  static void run(DstXprType &dst, const SrcXprType &src, const internal::assign_op<Scalar,Scalar> &)\n  {\n    Index dstRows = src.rows();\n    Index dstCols = src.cols();\n    if((dst.rows()!=dstRows) || (dst.cols()!=dstCols))\n      dst.resize(dstRows, dstCols);\n\n    src.dec().nestedExpression().template _solve_impl_transposed<false>(src.rhs(), dst);\n  }\n};\n\n// Specialization for \"dst = dec.adjoint().solve(rhs)\"\ntemplate<typename DstXprType, typename DecType, typename RhsType, typename Scalar>\nstruct Assignment<DstXprType, Solve<CwiseUnaryOp<internal::scalar_conjugate_op<typename DecType::Scalar>, const Transpose<const DecType> >,RhsType>,\n                  internal::assign_op<Scalar,Scalar>, Dense2Dense>\n{\n  typedef Solve<CwiseUnaryOp<internal::scalar_conjugate_op<typename DecType::Scalar>, const Transpose<const DecType> >,RhsType> SrcXprType;\n  static void run(DstXprType &dst, const SrcXprType &src, const internal::assign_op<Scalar,Scalar> &)\n  {\n    Index dstRows = src.rows();\n    Index dstCols = src.cols();\n    if((dst.rows()!=dstRows) || (dst.cols()!=dstCols))\n      dst.resize(dstRows, dstCols);\n    \n    src.dec().nestedExpression().nestedExpression().template _solve_impl_transposed<true>(src.rhs(), dst);\n  }\n};\n\n} // end namepsace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_SOLVE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/SolveTriangular.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SOLVETRIANGULAR_H\n#define EIGEN_SOLVETRIANGULAR_H\n\nnamespace Eigen { \n\nnamespace internal {\n\n// Forward declarations:\n// The following two routines are implemented in the products/TriangularSolver*.h files\ntemplate<typename LhsScalar, typename RhsScalar, typename Index, int Side, int Mode, bool Conjugate, int StorageOrder>\nstruct triangular_solve_vector;\n\ntemplate <typename Scalar, typename Index, int Side, int Mode, bool Conjugate, int TriStorageOrder, int OtherStorageOrder>\nstruct triangular_solve_matrix;\n\n// small helper struct extracting some traits on the underlying solver operation\ntemplate<typename Lhs, typename Rhs, int Side>\nclass trsolve_traits\n{\n  private:\n    enum {\n      RhsIsVectorAtCompileTime = (Side==OnTheLeft ? Rhs::ColsAtCompileTime : Rhs::RowsAtCompileTime)==1\n    };\n  public:\n    enum {\n      Unrolling   = (RhsIsVectorAtCompileTime && Rhs::SizeAtCompileTime != Dynamic && Rhs::SizeAtCompileTime <= 8)\n                  ? CompleteUnrolling : NoUnrolling,\n      RhsVectors  = RhsIsVectorAtCompileTime ? 1 : Dynamic\n    };\n};\n\ntemplate<typename Lhs, typename Rhs,\n  int Side, // can be OnTheLeft/OnTheRight\n  int Mode, // can be Upper/Lower | UnitDiag\n  int Unrolling = trsolve_traits<Lhs,Rhs,Side>::Unrolling,\n  int RhsVectors = trsolve_traits<Lhs,Rhs,Side>::RhsVectors\n  >\nstruct triangular_solver_selector;\n\ntemplate<typename Lhs, typename Rhs, int Side, int Mode>\nstruct triangular_solver_selector<Lhs,Rhs,Side,Mode,NoUnrolling,1>\n{\n  typedef typename Lhs::Scalar LhsScalar;\n  typedef typename Rhs::Scalar RhsScalar;\n  typedef blas_traits<Lhs> LhsProductTraits;\n  typedef typename LhsProductTraits::ExtractType ActualLhsType;\n  typedef Map<Matrix<RhsScalar,Dynamic,1>, Aligned> MappedRhs;\n  static void run(const Lhs& lhs, Rhs& rhs)\n  {\n    ActualLhsType actualLhs = LhsProductTraits::extract(lhs);\n\n    // FIXME find a way to allow an inner stride if packet_traits<Scalar>::size==1\n\n    bool useRhsDirectly = Rhs::InnerStrideAtCompileTime==1 || rhs.innerStride()==1;\n\n    ei_declare_aligned_stack_constructed_variable(RhsScalar,actualRhs,rhs.size(),\n                                                  (useRhsDirectly ? rhs.data() : 0));\n                                                  \n    if(!useRhsDirectly)\n      MappedRhs(actualRhs,rhs.size()) = rhs;\n\n    triangular_solve_vector<LhsScalar, RhsScalar, Index, Side, Mode, LhsProductTraits::NeedToConjugate,\n                            (int(Lhs::Flags) & RowMajorBit) ? RowMajor : ColMajor>\n      ::run(actualLhs.cols(), actualLhs.data(), actualLhs.outerStride(), actualRhs);\n\n    if(!useRhsDirectly)\n      rhs = MappedRhs(actualRhs, rhs.size());\n  }\n};\n\n// the rhs is a matrix\ntemplate<typename Lhs, typename Rhs, int Side, int Mode>\nstruct triangular_solver_selector<Lhs,Rhs,Side,Mode,NoUnrolling,Dynamic>\n{\n  typedef typename Rhs::Scalar Scalar;\n  typedef blas_traits<Lhs> LhsProductTraits;\n  typedef typename LhsProductTraits::DirectLinearAccessType ActualLhsType;\n\n  static void run(const Lhs& lhs, Rhs& rhs)\n  {\n    typename internal::add_const_on_value_type<ActualLhsType>::type actualLhs = LhsProductTraits::extract(lhs);\n\n    const Index size = lhs.rows();\n    const Index othersize = Side==OnTheLeft? rhs.cols() : rhs.rows();\n\n    typedef internal::gemm_blocking_space<(Rhs::Flags&RowMajorBit) ? RowMajor : ColMajor,Scalar,Scalar,\n              Rhs::MaxRowsAtCompileTime, Rhs::MaxColsAtCompileTime, Lhs::MaxRowsAtCompileTime,4> BlockingType;\n\n    BlockingType blocking(rhs.rows(), rhs.cols(), size, 1, false);\n\n    triangular_solve_matrix<Scalar,Index,Side,Mode,LhsProductTraits::NeedToConjugate,(int(Lhs::Flags) & RowMajorBit) ? RowMajor : ColMajor,\n                               (Rhs::Flags&RowMajorBit) ? RowMajor : ColMajor>\n      ::run(size, othersize, &actualLhs.coeffRef(0,0), actualLhs.outerStride(), &rhs.coeffRef(0,0), rhs.outerStride(), blocking);\n  }\n};\n\n/***************************************************************************\n* meta-unrolling implementation\n***************************************************************************/\n\ntemplate<typename Lhs, typename Rhs, int Mode, int LoopIndex, int Size,\n         bool Stop = LoopIndex==Size>\nstruct triangular_solver_unroller;\n\ntemplate<typename Lhs, typename Rhs, int Mode, int LoopIndex, int Size>\nstruct triangular_solver_unroller<Lhs,Rhs,Mode,LoopIndex,Size,false> {\n  enum {\n    IsLower = ((Mode&Lower)==Lower),\n    DiagIndex  = IsLower ? LoopIndex : Size - LoopIndex - 1,\n    StartIndex = IsLower ? 0         : DiagIndex+1\n  };\n  static void run(const Lhs& lhs, Rhs& rhs)\n  {\n    if (LoopIndex>0)\n      rhs.coeffRef(DiagIndex) -= lhs.row(DiagIndex).template segment<LoopIndex>(StartIndex).transpose()\n                                .cwiseProduct(rhs.template segment<LoopIndex>(StartIndex)).sum();\n\n    if(!(Mode & UnitDiag))\n      rhs.coeffRef(DiagIndex) /= lhs.coeff(DiagIndex,DiagIndex);\n\n    triangular_solver_unroller<Lhs,Rhs,Mode,LoopIndex+1,Size>::run(lhs,rhs);\n  }\n};\n\ntemplate<typename Lhs, typename Rhs, int Mode, int LoopIndex, int Size>\nstruct triangular_solver_unroller<Lhs,Rhs,Mode,LoopIndex,Size,true> {\n  static void run(const Lhs&, Rhs&) {}\n};\n\ntemplate<typename Lhs, typename Rhs, int Mode>\nstruct triangular_solver_selector<Lhs,Rhs,OnTheLeft,Mode,CompleteUnrolling,1> {\n  static void run(const Lhs& lhs, Rhs& rhs)\n  { triangular_solver_unroller<Lhs,Rhs,Mode,0,Rhs::SizeAtCompileTime>::run(lhs,rhs); }\n};\n\ntemplate<typename Lhs, typename Rhs, int Mode>\nstruct triangular_solver_selector<Lhs,Rhs,OnTheRight,Mode,CompleteUnrolling,1> {\n  static void run(const Lhs& lhs, Rhs& rhs)\n  {\n    Transpose<const Lhs> trLhs(lhs);\n    Transpose<Rhs> trRhs(rhs);\n    \n    triangular_solver_unroller<Transpose<const Lhs>,Transpose<Rhs>,\n                              ((Mode&Upper)==Upper ? Lower : Upper) | (Mode&UnitDiag),\n                              0,Rhs::SizeAtCompileTime>::run(trLhs,trRhs);\n  }\n};\n\n} // end namespace internal\n\n/***************************************************************************\n* TriangularView methods\n***************************************************************************/\n\ntemplate<typename MatrixType, unsigned int Mode>\ntemplate<int Side, typename OtherDerived>\nvoid TriangularViewImpl<MatrixType,Mode,Dense>::solveInPlace(const MatrixBase<OtherDerived>& _other) const\n{\n  OtherDerived& other = _other.const_cast_derived();\n  eigen_assert( derived().cols() == derived().rows() && ((Side==OnTheLeft && derived().cols() == other.rows()) || (Side==OnTheRight && derived().cols() == other.cols())) );\n  eigen_assert((!(Mode & ZeroDiag)) && bool(Mode & (Upper|Lower)));\n\n  enum { copy = (internal::traits<OtherDerived>::Flags & RowMajorBit)  && OtherDerived::IsVectorAtCompileTime && OtherDerived::SizeAtCompileTime!=1};\n  typedef typename internal::conditional<copy,\n    typename internal::plain_matrix_type_column_major<OtherDerived>::type, OtherDerived&>::type OtherCopy;\n  OtherCopy otherCopy(other);\n\n  internal::triangular_solver_selector<MatrixType, typename internal::remove_reference<OtherCopy>::type,\n    Side, Mode>::run(derived().nestedExpression(), otherCopy);\n\n  if (copy)\n    other = otherCopy;\n}\n\ntemplate<typename Derived, unsigned int Mode>\ntemplate<int Side, typename Other>\nconst internal::triangular_solve_retval<Side,TriangularView<Derived,Mode>,Other>\nTriangularViewImpl<Derived,Mode,Dense>::solve(const MatrixBase<Other>& other) const\n{\n  return internal::triangular_solve_retval<Side,TriangularViewType,Other>(derived(), other.derived());\n}\n\nnamespace internal {\n\n\ntemplate<int Side, typename TriangularType, typename Rhs>\nstruct traits<triangular_solve_retval<Side, TriangularType, Rhs> >\n{\n  typedef typename internal::plain_matrix_type_column_major<Rhs>::type ReturnType;\n};\n\ntemplate<int Side, typename TriangularType, typename Rhs> struct triangular_solve_retval\n : public ReturnByValue<triangular_solve_retval<Side, TriangularType, Rhs> >\n{\n  typedef typename remove_all<typename Rhs::Nested>::type RhsNestedCleaned;\n  typedef ReturnByValue<triangular_solve_retval> Base;\n\n  triangular_solve_retval(const TriangularType& tri, const Rhs& rhs)\n    : m_triangularMatrix(tri), m_rhs(rhs)\n  {}\n\n  inline Index rows() const { return m_rhs.rows(); }\n  inline Index cols() const { return m_rhs.cols(); }\n\n  template<typename Dest> inline void evalTo(Dest& dst) const\n  {\n    if(!is_same_dense(dst,m_rhs))\n      dst = m_rhs;\n    m_triangularMatrix.template solveInPlace<Side>(dst);\n  }\n\n  protected:\n    const TriangularType& m_triangularMatrix;\n    typename Rhs::Nested m_rhs;\n};\n\n} // namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_SOLVETRIANGULAR_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/SolverBase.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2015 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SOLVERBASE_H\n#define EIGEN_SOLVERBASE_H\n\nnamespace Eigen {\n\nnamespace internal {\n\n\n\n} // end namespace internal\n\n/** \\class SolverBase\n  * \\brief A base class for matrix decomposition and solvers\n  *\n  * \\tparam Derived the actual type of the decomposition/solver.\n  *\n  * Any matrix decomposition inheriting this base class provide the following API:\n  *\n  * \\code\n  * MatrixType A, b, x;\n  * DecompositionType dec(A);\n  * x = dec.solve(b);             // solve A   * x = b\n  * x = dec.transpose().solve(b); // solve A^T * x = b\n  * x = dec.adjoint().solve(b);   // solve A'  * x = b\n  * \\endcode\n  *\n  * \\warning Currently, any other usage of transpose() and adjoint() are not supported and will produce compilation errors.\n  *\n  * \\sa class PartialPivLU, class FullPivLU\n  */\ntemplate<typename Derived>\nclass SolverBase : public EigenBase<Derived>\n{\n  public:\n\n    typedef EigenBase<Derived> Base;\n    typedef typename internal::traits<Derived>::Scalar Scalar;\n    typedef Scalar CoeffReturnType;\n\n    enum {\n      RowsAtCompileTime = internal::traits<Derived>::RowsAtCompileTime,\n      ColsAtCompileTime = internal::traits<Derived>::ColsAtCompileTime,\n      SizeAtCompileTime = (internal::size_at_compile_time<internal::traits<Derived>::RowsAtCompileTime,\n                                                          internal::traits<Derived>::ColsAtCompileTime>::ret),\n      MaxRowsAtCompileTime = internal::traits<Derived>::MaxRowsAtCompileTime,\n      MaxColsAtCompileTime = internal::traits<Derived>::MaxColsAtCompileTime,\n      MaxSizeAtCompileTime = (internal::size_at_compile_time<internal::traits<Derived>::MaxRowsAtCompileTime,\n                                                             internal::traits<Derived>::MaxColsAtCompileTime>::ret),\n      IsVectorAtCompileTime = internal::traits<Derived>::MaxRowsAtCompileTime == 1\n                           || internal::traits<Derived>::MaxColsAtCompileTime == 1\n    };\n\n    /** Default constructor */\n    SolverBase()\n    {}\n\n    ~SolverBase()\n    {}\n\n    using Base::derived;\n\n    /** \\returns an expression of the solution x of \\f$ A x = b \\f$ using the current decomposition of A.\n      */\n    template<typename Rhs>\n    inline const Solve<Derived, Rhs>\n    solve(const MatrixBase<Rhs>& b) const\n    {\n      eigen_assert(derived().rows()==b.rows() && \"solve(): invalid number of rows of the right hand side matrix b\");\n      return Solve<Derived, Rhs>(derived(), b.derived());\n    }\n\n    /** \\internal the return type of transpose() */\n    typedef typename internal::add_const<Transpose<const Derived> >::type ConstTransposeReturnType;\n    /** \\returns an expression of the transposed of the factored matrix.\n      *\n      * A typical usage is to solve for the transposed problem A^T x = b:\n      * \\code x = dec.transpose().solve(b); \\endcode\n      *\n      * \\sa adjoint(), solve()\n      */\n    inline ConstTransposeReturnType transpose() const\n    {\n      return ConstTransposeReturnType(derived());\n    }\n\n    /** \\internal the return type of adjoint() */\n    typedef typename internal::conditional<NumTraits<Scalar>::IsComplex,\n                        CwiseUnaryOp<internal::scalar_conjugate_op<Scalar>, ConstTransposeReturnType>,\n                        ConstTransposeReturnType\n                     >::type AdjointReturnType;\n    /** \\returns an expression of the adjoint of the factored matrix\n      *\n      * A typical usage is to solve for the adjoint problem A' x = b:\n      * \\code x = dec.adjoint().solve(b); \\endcode\n      *\n      * For real scalar types, this function is equivalent to transpose().\n      *\n      * \\sa transpose(), solve()\n      */\n    inline AdjointReturnType adjoint() const\n    {\n      return AdjointReturnType(derived().transpose());\n    }\n\n  protected:\n};\n\nnamespace internal {\n\ntemplate<typename Derived>\nstruct generic_xpr_base<Derived, MatrixXpr, SolverStorage>\n{\n  typedef SolverBase<Derived> type;\n\n};\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_SOLVERBASE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/StableNorm.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_STABLENORM_H\n#define EIGEN_STABLENORM_H\n\nnamespace Eigen { \n\nnamespace internal {\n\ntemplate<typename ExpressionType, typename Scalar>\ninline void stable_norm_kernel(const ExpressionType& bl, Scalar& ssq, Scalar& scale, Scalar& invScale)\n{\n  Scalar maxCoeff = bl.cwiseAbs().maxCoeff();\n  \n  if(maxCoeff>scale)\n  {\n    ssq = ssq * numext::abs2(scale/maxCoeff);\n    Scalar tmp = Scalar(1)/maxCoeff;\n    if(tmp > NumTraits<Scalar>::highest())\n    {\n      invScale = NumTraits<Scalar>::highest();\n      scale = Scalar(1)/invScale;\n    }\n    else if(maxCoeff>NumTraits<Scalar>::highest()) // we got a INF\n    {\n      invScale = Scalar(1);\n      scale = maxCoeff;\n    }\n    else\n    {\n      scale = maxCoeff;\n      invScale = tmp;\n    }\n  }\n  else if(maxCoeff!=maxCoeff) // we got a NaN\n  {\n    scale = maxCoeff;\n  }\n  \n  // TODO if the maxCoeff is much much smaller than the current scale,\n  // then we can neglect this sub vector\n  if(scale>Scalar(0)) // if scale==0, then bl is 0 \n    ssq += (bl*invScale).squaredNorm();\n}\n\ntemplate<typename Derived>\ninline typename NumTraits<typename traits<Derived>::Scalar>::Real\nblueNorm_impl(const EigenBase<Derived>& _vec)\n{\n  typedef typename Derived::RealScalar RealScalar;  \n  using std::pow;\n  using std::sqrt;\n  using std::abs;\n  const Derived& vec(_vec.derived());\n  static bool initialized = false;\n  static RealScalar b1, b2, s1m, s2m, rbig, relerr;\n  if(!initialized)\n  {\n    int ibeta, it, iemin, iemax, iexp;\n    RealScalar eps;\n    // This program calculates the machine-dependent constants\n    // bl, b2, slm, s2m, relerr overfl\n    // from the \"basic\" machine-dependent numbers\n    // nbig, ibeta, it, iemin, iemax, rbig.\n    // The following define the basic machine-dependent constants.\n    // For portability, the PORT subprograms \"ilmaeh\" and \"rlmach\"\n    // are used. For any specific computer, each of the assignment\n    // statements can be replaced\n    ibeta = std::numeric_limits<RealScalar>::radix;                 // base for floating-point numbers\n    it    = std::numeric_limits<RealScalar>::digits;                // number of base-beta digits in mantissa\n    iemin = std::numeric_limits<RealScalar>::min_exponent;          // minimum exponent\n    iemax = std::numeric_limits<RealScalar>::max_exponent;          // maximum exponent\n    rbig  = (std::numeric_limits<RealScalar>::max)();               // largest floating-point number\n\n    iexp  = -((1-iemin)/2);\n    b1    = RealScalar(pow(RealScalar(ibeta),RealScalar(iexp)));    // lower boundary of midrange\n    iexp  = (iemax + 1 - it)/2;\n    b2    = RealScalar(pow(RealScalar(ibeta),RealScalar(iexp)));    // upper boundary of midrange\n\n    iexp  = (2-iemin)/2;\n    s1m   = RealScalar(pow(RealScalar(ibeta),RealScalar(iexp)));    // scaling factor for lower range\n    iexp  = - ((iemax+it)/2);\n    s2m   = RealScalar(pow(RealScalar(ibeta),RealScalar(iexp)));    // scaling factor for upper range\n\n    eps     = RealScalar(pow(double(ibeta), 1-it));\n    relerr  = sqrt(eps);                                            // tolerance for neglecting asml\n    initialized = true;\n  }\n  Index n = vec.size();\n  RealScalar ab2 = b2 / RealScalar(n);\n  RealScalar asml = RealScalar(0);\n  RealScalar amed = RealScalar(0);\n  RealScalar abig = RealScalar(0);\n  for(typename Derived::InnerIterator it(vec, 0); it; ++it)\n  {\n    RealScalar ax = abs(it.value());\n    if(ax > ab2)     abig += numext::abs2(ax*s2m);\n    else if(ax < b1) asml += numext::abs2(ax*s1m);\n    else             amed += numext::abs2(ax);\n  }\n  if(amed!=amed)\n    return amed;  // we got a NaN\n  if(abig > RealScalar(0))\n  {\n    abig = sqrt(abig);\n    if(abig > rbig) // overflow, or *this contains INF values\n      return abig;  // return INF\n    if(amed > RealScalar(0))\n    {\n      abig = abig/s2m;\n      amed = sqrt(amed);\n    }\n    else\n      return abig/s2m;\n  }\n  else if(asml > RealScalar(0))\n  {\n    if (amed > RealScalar(0))\n    {\n      abig = sqrt(amed);\n      amed = sqrt(asml) / s1m;\n    }\n    else\n      return sqrt(asml)/s1m;\n  }\n  else\n    return sqrt(amed);\n  asml = numext::mini(abig, amed);\n  abig = numext::maxi(abig, amed);\n  if(asml <= abig*relerr)\n    return abig;\n  else\n    return abig * sqrt(RealScalar(1) + numext::abs2(asml/abig));\n}\n\n} // end namespace internal\n\n/** \\returns the \\em l2 norm of \\c *this avoiding underflow and overflow.\n  * This version use a blockwise two passes algorithm:\n  *  1 - find the absolute largest coefficient \\c s\n  *  2 - compute \\f$ s \\Vert \\frac{*this}{s} \\Vert \\f$ in a standard way\n  *\n  * For architecture/scalar types supporting vectorization, this version\n  * is faster than blueNorm(). Otherwise the blueNorm() is much faster.\n  *\n  * \\sa norm(), blueNorm(), hypotNorm()\n  */\ntemplate<typename Derived>\ninline typename NumTraits<typename internal::traits<Derived>::Scalar>::Real\nMatrixBase<Derived>::stableNorm() const\n{\n  using std::sqrt;\n  using std::abs;\n  const Index blockSize = 4096;\n  RealScalar scale(0);\n  RealScalar invScale(1);\n  RealScalar ssq(0); // sum of square\n  \n  typedef typename internal::nested_eval<Derived,2>::type DerivedCopy;\n  typedef typename internal::remove_all<DerivedCopy>::type DerivedCopyClean;\n  DerivedCopy copy(derived());\n  \n  enum {\n    CanAlign = (   (int(DerivedCopyClean::Flags)&DirectAccessBit)\n                || (int(internal::evaluator<DerivedCopyClean>::Alignment)>0) // FIXME Alignment)>0 might not be enough\n               ) && (blockSize*sizeof(Scalar)*2<EIGEN_STACK_ALLOCATION_LIMIT) // ifwe cannot allocate on the stack, then let's not bother about this optimization\n  };\n  typedef typename internal::conditional<CanAlign, Ref<const Matrix<Scalar,Dynamic,1,0,blockSize,1>, internal::evaluator<DerivedCopyClean>::Alignment>,\n                                                   typename DerivedCopyClean::ConstSegmentReturnType>::type SegmentWrapper;\n  Index n = size();\n  \n  if(n==1)\n    return abs(this->coeff(0));\n  \n  Index bi = internal::first_default_aligned(copy);\n  if (bi>0)\n    internal::stable_norm_kernel(copy.head(bi), ssq, scale, invScale);\n  for (; bi<n; bi+=blockSize)\n    internal::stable_norm_kernel(SegmentWrapper(copy.segment(bi,numext::mini(blockSize, n - bi))), ssq, scale, invScale);\n  return scale * sqrt(ssq);\n}\n\n/** \\returns the \\em l2 norm of \\c *this using the Blue's algorithm.\n  * A Portable Fortran Program to Find the Euclidean Norm of a Vector,\n  * ACM TOMS, Vol 4, Issue 1, 1978.\n  *\n  * For architecture/scalar types without vectorization, this version\n  * is much faster than stableNorm(). Otherwise the stableNorm() is faster.\n  *\n  * \\sa norm(), stableNorm(), hypotNorm()\n  */\ntemplate<typename Derived>\ninline typename NumTraits<typename internal::traits<Derived>::Scalar>::Real\nMatrixBase<Derived>::blueNorm() const\n{\n  return internal::blueNorm_impl(*this);\n}\n\n/** \\returns the \\em l2 norm of \\c *this avoiding undeflow and overflow.\n  * This version use a concatenation of hypot() calls, and it is very slow.\n  *\n  * \\sa norm(), stableNorm()\n  */\ntemplate<typename Derived>\ninline typename NumTraits<typename internal::traits<Derived>::Scalar>::Real\nMatrixBase<Derived>::hypotNorm() const\n{\n  return this->cwiseAbs().redux(internal::scalar_hypot_op<RealScalar>());\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_STABLENORM_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/Stride.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2010 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_STRIDE_H\n#define EIGEN_STRIDE_H\n\nnamespace Eigen { \n\n/** \\class Stride\n  * \\ingroup Core_Module\n  *\n  * \\brief Holds strides information for Map\n  *\n  * This class holds the strides information for mapping arrays with strides with class Map.\n  *\n  * It holds two values: the inner stride and the outer stride.\n  *\n  * The inner stride is the pointer increment between two consecutive entries within a given row of a\n  * row-major matrix or within a given column of a column-major matrix.\n  *\n  * The outer stride is the pointer increment between two consecutive rows of a row-major matrix or\n  * between two consecutive columns of a column-major matrix.\n  *\n  * These two values can be passed either at compile-time as template parameters, or at runtime as\n  * arguments to the constructor.\n  *\n  * Indeed, this class takes two template parameters:\n  *  \\tparam _OuterStrideAtCompileTime the outer stride, or Dynamic if you want to specify it at runtime.\n  *  \\tparam _InnerStrideAtCompileTime the inner stride, or Dynamic if you want to specify it at runtime.\n  *\n  * Here is an example:\n  * \\include Map_general_stride.cpp\n  * Output: \\verbinclude Map_general_stride.out\n  *\n  * \\sa class InnerStride, class OuterStride, \\ref TopicStorageOrders\n  */\ntemplate<int _OuterStrideAtCompileTime, int _InnerStrideAtCompileTime>\nclass Stride\n{\n  public:\n    typedef Eigen::Index Index; ///< \\deprecated since Eigen 3.3\n    enum {\n      InnerStrideAtCompileTime = _InnerStrideAtCompileTime,\n      OuterStrideAtCompileTime = _OuterStrideAtCompileTime\n    };\n\n    /** Default constructor, for use when strides are fixed at compile time */\n    EIGEN_DEVICE_FUNC\n    Stride()\n      : m_outer(OuterStrideAtCompileTime), m_inner(InnerStrideAtCompileTime)\n    {\n      eigen_assert(InnerStrideAtCompileTime != Dynamic && OuterStrideAtCompileTime != Dynamic);\n    }\n\n    /** Constructor allowing to pass the strides at runtime */\n    EIGEN_DEVICE_FUNC\n    Stride(Index outerStride, Index innerStride)\n      : m_outer(outerStride), m_inner(innerStride)\n    {\n      eigen_assert(innerStride>=0 && outerStride>=0);\n    }\n\n    /** Copy constructor */\n    EIGEN_DEVICE_FUNC\n    Stride(const Stride& other)\n      : m_outer(other.outer()), m_inner(other.inner())\n    {}\n\n    /** \\returns the outer stride */\n    EIGEN_DEVICE_FUNC\n    inline Index outer() const { return m_outer.value(); }\n    /** \\returns the inner stride */\n    EIGEN_DEVICE_FUNC\n    inline Index inner() const { return m_inner.value(); }\n\n  protected:\n    internal::variable_if_dynamic<Index, OuterStrideAtCompileTime> m_outer;\n    internal::variable_if_dynamic<Index, InnerStrideAtCompileTime> m_inner;\n};\n\n/** \\brief Convenience specialization of Stride to specify only an inner stride\n  * See class Map for some examples */\ntemplate<int Value>\nclass InnerStride : public Stride<0, Value>\n{\n    typedef Stride<0, Value> Base;\n  public:\n    EIGEN_DEVICE_FUNC InnerStride() : Base() {}\n    EIGEN_DEVICE_FUNC InnerStride(Index v) : Base(0, v) {} // FIXME making this explicit could break valid code\n};\n\n/** \\brief Convenience specialization of Stride to specify only an outer stride\n  * See class Map for some examples */\ntemplate<int Value>\nclass OuterStride : public Stride<Value, 0>\n{\n    typedef Stride<Value, 0> Base;\n  public:\n    EIGEN_DEVICE_FUNC OuterStride() : Base() {}\n    EIGEN_DEVICE_FUNC OuterStride(Index v) : Base(v,0) {} // FIXME making this explicit could break valid code\n};\n\n} // end namespace Eigen\n\n#endif // EIGEN_STRIDE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/Swap.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2006-2008 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SWAP_H\n#define EIGEN_SWAP_H\n\nnamespace Eigen { \n\nnamespace internal {\n\n// Overload default assignPacket behavior for swapping them\ntemplate<typename DstEvaluatorTypeT, typename SrcEvaluatorTypeT>\nclass generic_dense_assignment_kernel<DstEvaluatorTypeT, SrcEvaluatorTypeT, swap_assign_op<typename DstEvaluatorTypeT::Scalar>, Specialized>\n : public generic_dense_assignment_kernel<DstEvaluatorTypeT, SrcEvaluatorTypeT, swap_assign_op<typename DstEvaluatorTypeT::Scalar>, BuiltIn>\n{\nprotected:\n  typedef generic_dense_assignment_kernel<DstEvaluatorTypeT, SrcEvaluatorTypeT, swap_assign_op<typename DstEvaluatorTypeT::Scalar>, BuiltIn> Base;\n  using Base::m_dst;\n  using Base::m_src;\n  using Base::m_functor;\n  \npublic:\n  typedef typename Base::Scalar Scalar;\n  typedef typename Base::DstXprType DstXprType;\n  typedef swap_assign_op<Scalar> Functor;\n  \n  EIGEN_DEVICE_FUNC generic_dense_assignment_kernel(DstEvaluatorTypeT &dst, const SrcEvaluatorTypeT &src, const Functor &func, DstXprType& dstExpr)\n    : Base(dst, src, func, dstExpr)\n  {}\n  \n  template<int StoreMode, int LoadMode, typename PacketType>\n  void assignPacket(Index row, Index col)\n  {\n    PacketType tmp = m_src.template packet<LoadMode,PacketType>(row,col);\n    const_cast<SrcEvaluatorTypeT&>(m_src).template writePacket<LoadMode>(row,col, m_dst.template packet<StoreMode,PacketType>(row,col));\n    m_dst.template writePacket<StoreMode>(row,col,tmp);\n  }\n  \n  template<int StoreMode, int LoadMode, typename PacketType>\n  void assignPacket(Index index)\n  {\n    PacketType tmp = m_src.template packet<LoadMode,PacketType>(index);\n    const_cast<SrcEvaluatorTypeT&>(m_src).template writePacket<LoadMode>(index, m_dst.template packet<StoreMode,PacketType>(index));\n    m_dst.template writePacket<StoreMode>(index,tmp);\n  }\n  \n  // TODO find a simple way not to have to copy/paste this function from generic_dense_assignment_kernel, by simple I mean no CRTP (Gael)\n  template<int StoreMode, int LoadMode, typename PacketType>\n  void assignPacketByOuterInner(Index outer, Index inner)\n  {\n    Index row = Base::rowIndexByOuterInner(outer, inner); \n    Index col = Base::colIndexByOuterInner(outer, inner);\n    assignPacket<StoreMode,LoadMode,PacketType>(row, col);\n  }\n};\n\n} // namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_SWAP_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/Transpose.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2006-2008 Benoit Jacob <jacob.benoit.1@gmail.com>\n// Copyright (C) 2009-2014 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_TRANSPOSE_H\n#define EIGEN_TRANSPOSE_H\n\nnamespace Eigen { \n\nnamespace internal {\ntemplate<typename MatrixType>\nstruct traits<Transpose<MatrixType> > : public traits<MatrixType>\n{\n  typedef typename ref_selector<MatrixType>::type MatrixTypeNested;\n  typedef typename remove_reference<MatrixTypeNested>::type MatrixTypeNestedPlain;\n  enum {\n    RowsAtCompileTime = MatrixType::ColsAtCompileTime,\n    ColsAtCompileTime = MatrixType::RowsAtCompileTime,\n    MaxRowsAtCompileTime = MatrixType::MaxColsAtCompileTime,\n    MaxColsAtCompileTime = MatrixType::MaxRowsAtCompileTime,\n    FlagsLvalueBit = is_lvalue<MatrixType>::value ? LvalueBit : 0,\n    Flags0 = traits<MatrixTypeNestedPlain>::Flags & ~(LvalueBit | NestByRefBit),\n    Flags1 = Flags0 | FlagsLvalueBit,\n    Flags = Flags1 ^ RowMajorBit,\n    InnerStrideAtCompileTime = inner_stride_at_compile_time<MatrixType>::ret,\n    OuterStrideAtCompileTime = outer_stride_at_compile_time<MatrixType>::ret\n  };\n};\n}\n\ntemplate<typename MatrixType, typename StorageKind> class TransposeImpl;\n\n/** \\class Transpose\n  * \\ingroup Core_Module\n  *\n  * \\brief Expression of the transpose of a matrix\n  *\n  * \\tparam MatrixType the type of the object of which we are taking the transpose\n  *\n  * This class represents an expression of the transpose of a matrix.\n  * It is the return type of MatrixBase::transpose() and MatrixBase::adjoint()\n  * and most of the time this is the only way it is used.\n  *\n  * \\sa MatrixBase::transpose(), MatrixBase::adjoint()\n  */\ntemplate<typename MatrixType> class Transpose\n  : public TransposeImpl<MatrixType,typename internal::traits<MatrixType>::StorageKind>\n{\n  public:\n\n    typedef typename internal::ref_selector<MatrixType>::non_const_type MatrixTypeNested;\n\n    typedef typename TransposeImpl<MatrixType,typename internal::traits<MatrixType>::StorageKind>::Base Base;\n    EIGEN_GENERIC_PUBLIC_INTERFACE(Transpose)\n    typedef typename internal::remove_all<MatrixType>::type NestedExpression;\n\n    EIGEN_DEVICE_FUNC\n    explicit inline Transpose(MatrixType& matrix) : m_matrix(matrix) {}\n\n    EIGEN_INHERIT_ASSIGNMENT_OPERATORS(Transpose)\n\n    EIGEN_DEVICE_FUNC inline Index rows() const { return m_matrix.cols(); }\n    EIGEN_DEVICE_FUNC inline Index cols() const { return m_matrix.rows(); }\n\n    /** \\returns the nested expression */\n    EIGEN_DEVICE_FUNC\n    const typename internal::remove_all<MatrixTypeNested>::type&\n    nestedExpression() const { return m_matrix; }\n\n    /** \\returns the nested expression */\n    EIGEN_DEVICE_FUNC\n    typename internal::remove_reference<MatrixTypeNested>::type&\n    nestedExpression() { return m_matrix; }\n\n    /** \\internal */\n    void resize(Index nrows, Index ncols) {\n      m_matrix.resize(ncols,nrows);\n    }\n\n  protected:\n    typename internal::ref_selector<MatrixType>::non_const_type m_matrix;\n};\n\nnamespace internal {\n\ntemplate<typename MatrixType, bool HasDirectAccess = has_direct_access<MatrixType>::ret>\nstruct TransposeImpl_base\n{\n  typedef typename dense_xpr_base<Transpose<MatrixType> >::type type;\n};\n\ntemplate<typename MatrixType>\nstruct TransposeImpl_base<MatrixType, false>\n{\n  typedef typename dense_xpr_base<Transpose<MatrixType> >::type type;\n};\n\n} // end namespace internal\n\n// Generic API dispatcher\ntemplate<typename XprType, typename StorageKind>\nclass TransposeImpl\n  : public internal::generic_xpr_base<Transpose<XprType> >::type\n{\npublic:\n  typedef typename internal::generic_xpr_base<Transpose<XprType> >::type Base;\n};\n\ntemplate<typename MatrixType> class TransposeImpl<MatrixType,Dense>\n  : public internal::TransposeImpl_base<MatrixType>::type\n{\n  public:\n\n    typedef typename internal::TransposeImpl_base<MatrixType>::type Base;\n    using Base::coeffRef;\n    EIGEN_DENSE_PUBLIC_INTERFACE(Transpose<MatrixType>)\n    EIGEN_INHERIT_ASSIGNMENT_OPERATORS(TransposeImpl)\n\n    EIGEN_DEVICE_FUNC inline Index innerStride() const { return derived().nestedExpression().innerStride(); }\n    EIGEN_DEVICE_FUNC inline Index outerStride() const { return derived().nestedExpression().outerStride(); }\n\n    typedef typename internal::conditional<\n                       internal::is_lvalue<MatrixType>::value,\n                       Scalar,\n                       const Scalar\n                     >::type ScalarWithConstIfNotLvalue;\n\n    EIGEN_DEVICE_FUNC inline ScalarWithConstIfNotLvalue* data() { return derived().nestedExpression().data(); }\n    EIGEN_DEVICE_FUNC inline const Scalar* data() const { return derived().nestedExpression().data(); }\n\n    // FIXME: shall we keep the const version of coeffRef?\n    EIGEN_DEVICE_FUNC\n    inline const Scalar& coeffRef(Index rowId, Index colId) const\n    {\n      return derived().nestedExpression().coeffRef(colId, rowId);\n    }\n\n    EIGEN_DEVICE_FUNC\n    inline const Scalar& coeffRef(Index index) const\n    {\n      return derived().nestedExpression().coeffRef(index);\n    }\n};\n\n/** \\returns an expression of the transpose of *this.\n  *\n  * Example: \\include MatrixBase_transpose.cpp\n  * Output: \\verbinclude MatrixBase_transpose.out\n  *\n  * \\warning If you want to replace a matrix by its own transpose, do \\b NOT do this:\n  * \\code\n  * m = m.transpose(); // bug!!! caused by aliasing effect\n  * \\endcode\n  * Instead, use the transposeInPlace() method:\n  * \\code\n  * m.transposeInPlace();\n  * \\endcode\n  * which gives Eigen good opportunities for optimization, or alternatively you can also do:\n  * \\code\n  * m = m.transpose().eval();\n  * \\endcode\n  *\n  * \\sa transposeInPlace(), adjoint() */\ntemplate<typename Derived>\ninline Transpose<Derived>\nDenseBase<Derived>::transpose()\n{\n  return TransposeReturnType(derived());\n}\n\n/** This is the const version of transpose().\n  *\n  * Make sure you read the warning for transpose() !\n  *\n  * \\sa transposeInPlace(), adjoint() */\ntemplate<typename Derived>\ninline typename DenseBase<Derived>::ConstTransposeReturnType\nDenseBase<Derived>::transpose() const\n{\n  return ConstTransposeReturnType(derived());\n}\n\n/** \\returns an expression of the adjoint (i.e. conjugate transpose) of *this.\n  *\n  * Example: \\include MatrixBase_adjoint.cpp\n  * Output: \\verbinclude MatrixBase_adjoint.out\n  *\n  * \\warning If you want to replace a matrix by its own adjoint, do \\b NOT do this:\n  * \\code\n  * m = m.adjoint(); // bug!!! caused by aliasing effect\n  * \\endcode\n  * Instead, use the adjointInPlace() method:\n  * \\code\n  * m.adjointInPlace();\n  * \\endcode\n  * which gives Eigen good opportunities for optimization, or alternatively you can also do:\n  * \\code\n  * m = m.adjoint().eval();\n  * \\endcode\n  *\n  * \\sa adjointInPlace(), transpose(), conjugate(), class Transpose, class internal::scalar_conjugate_op */\ntemplate<typename Derived>\ninline const typename MatrixBase<Derived>::AdjointReturnType\nMatrixBase<Derived>::adjoint() const\n{\n  return AdjointReturnType(this->transpose());\n}\n\n/***************************************************************************\n* \"in place\" transpose implementation\n***************************************************************************/\n\nnamespace internal {\n\ntemplate<typename MatrixType,\n  bool IsSquare = (MatrixType::RowsAtCompileTime == MatrixType::ColsAtCompileTime) && MatrixType::RowsAtCompileTime!=Dynamic,\n  bool MatchPacketSize =\n        (int(MatrixType::RowsAtCompileTime) == int(internal::packet_traits<typename MatrixType::Scalar>::size))\n    &&  (internal::evaluator<MatrixType>::Flags&PacketAccessBit) >\nstruct inplace_transpose_selector;\n\ntemplate<typename MatrixType>\nstruct inplace_transpose_selector<MatrixType,true,false> { // square matrix\n  static void run(MatrixType& m) {\n    m.matrix().template triangularView<StrictlyUpper>().swap(m.matrix().transpose());\n  }\n};\n\n// TODO: vectorized path is currently limited to LargestPacketSize x LargestPacketSize cases only.\ntemplate<typename MatrixType>\nstruct inplace_transpose_selector<MatrixType,true,true> { // PacketSize x PacketSize\n  static void run(MatrixType& m) {\n    typedef typename MatrixType::Scalar Scalar;\n    typedef typename internal::packet_traits<typename MatrixType::Scalar>::type Packet;\n    const Index PacketSize = internal::packet_traits<Scalar>::size;\n    const Index Alignment = internal::evaluator<MatrixType>::Alignment;\n    PacketBlock<Packet> A;\n    for (Index i=0; i<PacketSize; ++i)\n      A.packet[i] = m.template packetByOuterInner<Alignment>(i,0);\n    internal::ptranspose(A);\n    for (Index i=0; i<PacketSize; ++i)\n      m.template writePacket<Alignment>(m.rowIndexByOuterInner(i,0), m.colIndexByOuterInner(i,0), A.packet[i]);\n  }\n};\n\ntemplate<typename MatrixType,bool MatchPacketSize>\nstruct inplace_transpose_selector<MatrixType,false,MatchPacketSize> { // non square matrix\n  static void run(MatrixType& m) {\n    if (m.rows()==m.cols())\n      m.matrix().template triangularView<StrictlyUpper>().swap(m.matrix().transpose());\n    else\n      m = m.transpose().eval();\n  }\n};\n\n} // end namespace internal\n\n/** This is the \"in place\" version of transpose(): it replaces \\c *this by its own transpose.\n  * Thus, doing\n  * \\code\n  * m.transposeInPlace();\n  * \\endcode\n  * has the same effect on m as doing\n  * \\code\n  * m = m.transpose().eval();\n  * \\endcode\n  * and is faster and also safer because in the latter line of code, forgetting the eval() results\n  * in a bug caused by \\ref TopicAliasing \"aliasing\".\n  *\n  * Notice however that this method is only useful if you want to replace a matrix by its own transpose.\n  * If you just need the transpose of a matrix, use transpose().\n  *\n  * \\note if the matrix is not square, then \\c *this must be a resizable matrix. \n  * This excludes (non-square) fixed-size matrices, block-expressions and maps.\n  *\n  * \\sa transpose(), adjoint(), adjointInPlace() */\ntemplate<typename Derived>\ninline void DenseBase<Derived>::transposeInPlace()\n{\n  eigen_assert((rows() == cols() || (RowsAtCompileTime == Dynamic && ColsAtCompileTime == Dynamic))\n               && \"transposeInPlace() called on a non-square non-resizable matrix\");\n  internal::inplace_transpose_selector<Derived>::run(derived());\n}\n\n/***************************************************************************\n* \"in place\" adjoint implementation\n***************************************************************************/\n\n/** This is the \"in place\" version of adjoint(): it replaces \\c *this by its own transpose.\n  * Thus, doing\n  * \\code\n  * m.adjointInPlace();\n  * \\endcode\n  * has the same effect on m as doing\n  * \\code\n  * m = m.adjoint().eval();\n  * \\endcode\n  * and is faster and also safer because in the latter line of code, forgetting the eval() results\n  * in a bug caused by aliasing.\n  *\n  * Notice however that this method is only useful if you want to replace a matrix by its own adjoint.\n  * If you just need the adjoint of a matrix, use adjoint().\n  *\n  * \\note if the matrix is not square, then \\c *this must be a resizable matrix.\n  * This excludes (non-square) fixed-size matrices, block-expressions and maps.\n  *\n  * \\sa transpose(), adjoint(), transposeInPlace() */\ntemplate<typename Derived>\ninline void MatrixBase<Derived>::adjointInPlace()\n{\n  derived() = adjoint().eval();\n}\n\n#ifndef EIGEN_NO_DEBUG\n\n// The following is to detect aliasing problems in most common cases.\n\nnamespace internal {\n\ntemplate<bool DestIsTransposed, typename OtherDerived>\nstruct check_transpose_aliasing_compile_time_selector\n{\n  enum { ret = bool(blas_traits<OtherDerived>::IsTransposed) != DestIsTransposed };\n};\n\ntemplate<bool DestIsTransposed, typename BinOp, typename DerivedA, typename DerivedB>\nstruct check_transpose_aliasing_compile_time_selector<DestIsTransposed,CwiseBinaryOp<BinOp,DerivedA,DerivedB> >\n{\n  enum { ret =    bool(blas_traits<DerivedA>::IsTransposed) != DestIsTransposed\n               || bool(blas_traits<DerivedB>::IsTransposed) != DestIsTransposed\n  };\n};\n\ntemplate<typename Scalar, bool DestIsTransposed, typename OtherDerived>\nstruct check_transpose_aliasing_run_time_selector\n{\n  static bool run(const Scalar* dest, const OtherDerived& src)\n  {\n    return (bool(blas_traits<OtherDerived>::IsTransposed) != DestIsTransposed) && (dest!=0 && dest==(const Scalar*)extract_data(src));\n  }\n};\n\ntemplate<typename Scalar, bool DestIsTransposed, typename BinOp, typename DerivedA, typename DerivedB>\nstruct check_transpose_aliasing_run_time_selector<Scalar,DestIsTransposed,CwiseBinaryOp<BinOp,DerivedA,DerivedB> >\n{\n  static bool run(const Scalar* dest, const CwiseBinaryOp<BinOp,DerivedA,DerivedB>& src)\n  {\n    return ((blas_traits<DerivedA>::IsTransposed != DestIsTransposed) && (dest!=0 && dest==(const Scalar*)extract_data(src.lhs())))\n        || ((blas_traits<DerivedB>::IsTransposed != DestIsTransposed) && (dest!=0 && dest==(const Scalar*)extract_data(src.rhs())));\n  }\n};\n\n// the following selector, checkTransposeAliasing_impl, based on MightHaveTransposeAliasing,\n// is because when the condition controlling the assert is known at compile time, ICC emits a warning.\n// This is actually a good warning: in expressions that don't have any transposing, the condition is\n// known at compile time to be false, and using that, we can avoid generating the code of the assert again\n// and again for all these expressions that don't need it.\n\ntemplate<typename Derived, typename OtherDerived,\n         bool MightHaveTransposeAliasing\n                 = check_transpose_aliasing_compile_time_selector\n                     <blas_traits<Derived>::IsTransposed,OtherDerived>::ret\n        >\nstruct checkTransposeAliasing_impl\n{\n    static void run(const Derived& dst, const OtherDerived& other)\n    {\n        eigen_assert((!check_transpose_aliasing_run_time_selector\n                      <typename Derived::Scalar,blas_traits<Derived>::IsTransposed,OtherDerived>\n                      ::run(extract_data(dst), other))\n          && \"aliasing detected during transposition, use transposeInPlace() \"\n             \"or evaluate the rhs into a temporary using .eval()\");\n\n    }\n};\n\ntemplate<typename Derived, typename OtherDerived>\nstruct checkTransposeAliasing_impl<Derived, OtherDerived, false>\n{\n    static void run(const Derived&, const OtherDerived&)\n    {\n    }\n};\n\ntemplate<typename Dst, typename Src>\nvoid check_for_aliasing(const Dst &dst, const Src &src)\n{\n  internal::checkTransposeAliasing_impl<Dst, Src>::run(dst, src);\n}\n\n} // end namespace internal\n\n#endif // EIGEN_NO_DEBUG\n\n} // end namespace Eigen\n\n#endif // EIGEN_TRANSPOSE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/Transpositions.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2010-2011 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_TRANSPOSITIONS_H\n#define EIGEN_TRANSPOSITIONS_H\n\nnamespace Eigen { \n\ntemplate<typename Derived>\nclass TranspositionsBase\n{\n    typedef internal::traits<Derived> Traits;\n    \n  public:\n\n    typedef typename Traits::IndicesType IndicesType;\n    typedef typename IndicesType::Scalar StorageIndex;\n    typedef Eigen::Index Index; ///< \\deprecated since Eigen 3.3\n\n    Derived& derived() { return *static_cast<Derived*>(this); }\n    const Derived& derived() const { return *static_cast<const Derived*>(this); }\n\n    /** Copies the \\a other transpositions into \\c *this */\n    template<typename OtherDerived>\n    Derived& operator=(const TranspositionsBase<OtherDerived>& other)\n    {\n      indices() = other.indices();\n      return derived();\n    }\n    \n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    /** This is a special case of the templated operator=. Its purpose is to\n      * prevent a default operator= from hiding the templated operator=.\n      */\n    Derived& operator=(const TranspositionsBase& other)\n    {\n      indices() = other.indices();\n      return derived();\n    }\n    #endif\n\n    /** \\returns the number of transpositions */\n    Index size() const { return indices().size(); }\n    /** \\returns the number of rows of the equivalent permutation matrix */\n    Index rows() const { return indices().size(); }\n    /** \\returns the number of columns of the equivalent permutation matrix */\n    Index cols() const { return indices().size(); }\n\n    /** Direct access to the underlying index vector */\n    inline const StorageIndex& coeff(Index i) const { return indices().coeff(i); }\n    /** Direct access to the underlying index vector */\n    inline StorageIndex& coeffRef(Index i) { return indices().coeffRef(i); }\n    /** Direct access to the underlying index vector */\n    inline const StorageIndex& operator()(Index i) const { return indices()(i); }\n    /** Direct access to the underlying index vector */\n    inline StorageIndex& operator()(Index i) { return indices()(i); }\n    /** Direct access to the underlying index vector */\n    inline const StorageIndex& operator[](Index i) const { return indices()(i); }\n    /** Direct access to the underlying index vector */\n    inline StorageIndex& operator[](Index i) { return indices()(i); }\n\n    /** const version of indices(). */\n    const IndicesType& indices() const { return derived().indices(); }\n    /** \\returns a reference to the stored array representing the transpositions. */\n    IndicesType& indices() { return derived().indices(); }\n\n    /** Resizes to given size. */\n    inline void resize(Index newSize)\n    {\n      indices().resize(newSize);\n    }\n\n    /** Sets \\c *this to represents an identity transformation */\n    void setIdentity()\n    {\n      for(StorageIndex i = 0; i < indices().size(); ++i)\n        coeffRef(i) = i;\n    }\n\n    // FIXME: do we want such methods ?\n    // might be usefull when the target matrix expression is complex, e.g.:\n    // object.matrix().block(..,..,..,..) = trans * object.matrix().block(..,..,..,..);\n    /*\n    template<typename MatrixType>\n    void applyForwardToRows(MatrixType& mat) const\n    {\n      for(Index k=0 ; k<size() ; ++k)\n        if(m_indices(k)!=k)\n          mat.row(k).swap(mat.row(m_indices(k)));\n    }\n\n    template<typename MatrixType>\n    void applyBackwardToRows(MatrixType& mat) const\n    {\n      for(Index k=size()-1 ; k>=0 ; --k)\n        if(m_indices(k)!=k)\n          mat.row(k).swap(mat.row(m_indices(k)));\n    }\n    */\n\n    /** \\returns the inverse transformation */\n    inline Transpose<TranspositionsBase> inverse() const\n    { return Transpose<TranspositionsBase>(derived()); }\n\n    /** \\returns the tranpose transformation */\n    inline Transpose<TranspositionsBase> transpose() const\n    { return Transpose<TranspositionsBase>(derived()); }\n\n  protected:\n};\n\nnamespace internal {\ntemplate<int SizeAtCompileTime, int MaxSizeAtCompileTime, typename _StorageIndex>\nstruct traits<Transpositions<SizeAtCompileTime,MaxSizeAtCompileTime,_StorageIndex> >\n : traits<PermutationMatrix<SizeAtCompileTime,MaxSizeAtCompileTime,_StorageIndex> >\n{\n  typedef Matrix<_StorageIndex, SizeAtCompileTime, 1, 0, MaxSizeAtCompileTime, 1> IndicesType;\n  typedef TranspositionsStorage StorageKind;\n};\n}\n\n/** \\class Transpositions\n  * \\ingroup Core_Module\n  *\n  * \\brief Represents a sequence of transpositions (row/column interchange)\n  *\n  * \\tparam SizeAtCompileTime the number of transpositions, or Dynamic\n  * \\tparam MaxSizeAtCompileTime the maximum number of transpositions, or Dynamic. This optional parameter defaults to SizeAtCompileTime. Most of the time, you should not have to specify it.\n  *\n  * This class represents a permutation transformation as a sequence of \\em n transpositions\n  * \\f$[T_{n-1} \\ldots T_{i} \\ldots T_{0}]\\f$. It is internally stored as a vector of integers \\c indices.\n  * Each transposition \\f$ T_{i} \\f$ applied on the left of a matrix (\\f$ T_{i} M\\f$) interchanges\n  * the rows \\c i and \\c indices[i] of the matrix \\c M.\n  * A transposition applied on the right (e.g., \\f$ M T_{i}\\f$) yields a column interchange.\n  *\n  * Compared to the class PermutationMatrix, such a sequence of transpositions is what is\n  * computed during a decomposition with pivoting, and it is faster when applying the permutation in-place.\n  *\n  * To apply a sequence of transpositions to a matrix, simply use the operator * as in the following example:\n  * \\code\n  * Transpositions tr;\n  * MatrixXf mat;\n  * mat = tr * mat;\n  * \\endcode\n  * In this example, we detect that the matrix appears on both side, and so the transpositions\n  * are applied in-place without any temporary or extra copy.\n  *\n  * \\sa class PermutationMatrix\n  */\n\ntemplate<int SizeAtCompileTime, int MaxSizeAtCompileTime, typename _StorageIndex>\nclass Transpositions : public TranspositionsBase<Transpositions<SizeAtCompileTime,MaxSizeAtCompileTime,_StorageIndex> >\n{\n    typedef internal::traits<Transpositions> Traits;\n  public:\n\n    typedef TranspositionsBase<Transpositions> Base;\n    typedef typename Traits::IndicesType IndicesType;\n    typedef typename IndicesType::Scalar StorageIndex;\n\n    inline Transpositions() {}\n\n    /** Copy constructor. */\n    template<typename OtherDerived>\n    inline Transpositions(const TranspositionsBase<OtherDerived>& other)\n      : m_indices(other.indices()) {}\n\n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    /** Standard copy constructor. Defined only to prevent a default copy constructor\n      * from hiding the other templated constructor */\n    inline Transpositions(const Transpositions& other) : m_indices(other.indices()) {}\n    #endif\n\n    /** Generic constructor from expression of the transposition indices. */\n    template<typename Other>\n    explicit inline Transpositions(const MatrixBase<Other>& indices) : m_indices(indices)\n    {}\n\n    /** Copies the \\a other transpositions into \\c *this */\n    template<typename OtherDerived>\n    Transpositions& operator=(const TranspositionsBase<OtherDerived>& other)\n    {\n      return Base::operator=(other);\n    }\n\n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    /** This is a special case of the templated operator=. Its purpose is to\n      * prevent a default operator= from hiding the templated operator=.\n      */\n    Transpositions& operator=(const Transpositions& other)\n    {\n      m_indices = other.m_indices;\n      return *this;\n    }\n    #endif\n\n    /** Constructs an uninitialized permutation matrix of given size.\n      */\n    inline Transpositions(Index size) : m_indices(size)\n    {}\n\n    /** const version of indices(). */\n    const IndicesType& indices() const { return m_indices; }\n    /** \\returns a reference to the stored array representing the transpositions. */\n    IndicesType& indices() { return m_indices; }\n\n  protected:\n\n    IndicesType m_indices;\n};\n\n\nnamespace internal {\ntemplate<int SizeAtCompileTime, int MaxSizeAtCompileTime, typename _StorageIndex, int _PacketAccess>\nstruct traits<Map<Transpositions<SizeAtCompileTime,MaxSizeAtCompileTime,_StorageIndex>,_PacketAccess> >\n : traits<PermutationMatrix<SizeAtCompileTime,MaxSizeAtCompileTime,_StorageIndex> >\n{\n  typedef Map<const Matrix<_StorageIndex,SizeAtCompileTime,1,0,MaxSizeAtCompileTime,1>, _PacketAccess> IndicesType;\n  typedef _StorageIndex StorageIndex;\n  typedef TranspositionsStorage StorageKind;\n};\n}\n\ntemplate<int SizeAtCompileTime, int MaxSizeAtCompileTime, typename _StorageIndex, int PacketAccess>\nclass Map<Transpositions<SizeAtCompileTime,MaxSizeAtCompileTime,_StorageIndex>,PacketAccess>\n : public TranspositionsBase<Map<Transpositions<SizeAtCompileTime,MaxSizeAtCompileTime,_StorageIndex>,PacketAccess> >\n{\n    typedef internal::traits<Map> Traits;\n  public:\n\n    typedef TranspositionsBase<Map> Base;\n    typedef typename Traits::IndicesType IndicesType;\n    typedef typename IndicesType::Scalar StorageIndex;\n\n    explicit inline Map(const StorageIndex* indicesPtr)\n      : m_indices(indicesPtr)\n    {}\n\n    inline Map(const StorageIndex* indicesPtr, Index size)\n      : m_indices(indicesPtr,size)\n    {}\n\n    /** Copies the \\a other transpositions into \\c *this */\n    template<typename OtherDerived>\n    Map& operator=(const TranspositionsBase<OtherDerived>& other)\n    {\n      return Base::operator=(other);\n    }\n\n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    /** This is a special case of the templated operator=. Its purpose is to\n      * prevent a default operator= from hiding the templated operator=.\n      */\n    Map& operator=(const Map& other)\n    {\n      m_indices = other.m_indices;\n      return *this;\n    }\n    #endif\n\n    /** const version of indices(). */\n    const IndicesType& indices() const { return m_indices; }\n    \n    /** \\returns a reference to the stored array representing the transpositions. */\n    IndicesType& indices() { return m_indices; }\n\n  protected:\n\n    IndicesType m_indices;\n};\n\nnamespace internal {\ntemplate<typename _IndicesType>\nstruct traits<TranspositionsWrapper<_IndicesType> >\n : traits<PermutationWrapper<_IndicesType> >\n{\n  typedef TranspositionsStorage StorageKind;\n};\n}\n\ntemplate<typename _IndicesType>\nclass TranspositionsWrapper\n : public TranspositionsBase<TranspositionsWrapper<_IndicesType> >\n{\n    typedef internal::traits<TranspositionsWrapper> Traits;\n  public:\n\n    typedef TranspositionsBase<TranspositionsWrapper> Base;\n    typedef typename Traits::IndicesType IndicesType;\n    typedef typename IndicesType::Scalar StorageIndex;\n\n    explicit inline TranspositionsWrapper(IndicesType& indices)\n      : m_indices(indices)\n    {}\n\n    /** Copies the \\a other transpositions into \\c *this */\n    template<typename OtherDerived>\n    TranspositionsWrapper& operator=(const TranspositionsBase<OtherDerived>& other)\n    {\n      return Base::operator=(other);\n    }\n\n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    /** This is a special case of the templated operator=. Its purpose is to\n      * prevent a default operator= from hiding the templated operator=.\n      */\n    TranspositionsWrapper& operator=(const TranspositionsWrapper& other)\n    {\n      m_indices = other.m_indices;\n      return *this;\n    }\n    #endif\n\n    /** const version of indices(). */\n    const IndicesType& indices() const { return m_indices; }\n\n    /** \\returns a reference to the stored array representing the transpositions. */\n    IndicesType& indices() { return m_indices; }\n\n  protected:\n\n    typename IndicesType::Nested m_indices;\n};\n\n\n\n/** \\returns the \\a matrix with the \\a transpositions applied to the columns.\n  */\ntemplate<typename MatrixDerived, typename TranspositionsDerived>\nEIGEN_DEVICE_FUNC\nconst Product<MatrixDerived, TranspositionsDerived, AliasFreeProduct>\noperator*(const MatrixBase<MatrixDerived> &matrix,\n          const TranspositionsBase<TranspositionsDerived>& transpositions)\n{\n  return Product<MatrixDerived, TranspositionsDerived, AliasFreeProduct>\n            (matrix.derived(), transpositions.derived());\n}\n\n/** \\returns the \\a matrix with the \\a transpositions applied to the rows.\n  */\ntemplate<typename TranspositionsDerived, typename MatrixDerived>\nEIGEN_DEVICE_FUNC\nconst Product<TranspositionsDerived, MatrixDerived, AliasFreeProduct>\noperator*(const TranspositionsBase<TranspositionsDerived> &transpositions,\n          const MatrixBase<MatrixDerived>& matrix)\n{\n  return Product<TranspositionsDerived, MatrixDerived, AliasFreeProduct>\n            (transpositions.derived(), matrix.derived());\n}\n\n// Template partial specialization for transposed/inverse transpositions\n\nnamespace internal {\n\ntemplate<typename Derived>\nstruct traits<Transpose<TranspositionsBase<Derived> > >\n : traits<Derived>\n{};\n\n} // end namespace internal\n\ntemplate<typename TranspositionsDerived>\nclass Transpose<TranspositionsBase<TranspositionsDerived> >\n{\n    typedef TranspositionsDerived TranspositionType;\n    typedef typename TranspositionType::IndicesType IndicesType;\n  public:\n\n    explicit Transpose(const TranspositionType& t) : m_transpositions(t) {}\n\n    Index size() const { return m_transpositions.size(); }\n    Index rows() const { return m_transpositions.size(); }\n    Index cols() const { return m_transpositions.size(); }\n\n    /** \\returns the \\a matrix with the inverse transpositions applied to the columns.\n      */\n    template<typename OtherDerived> friend\n    const Product<OtherDerived, Transpose, AliasFreeProduct>\n    operator*(const MatrixBase<OtherDerived>& matrix, const Transpose& trt)\n    {\n      return Product<OtherDerived, Transpose, AliasFreeProduct>(matrix.derived(), trt.derived());\n    }\n\n    /** \\returns the \\a matrix with the inverse transpositions applied to the rows.\n      */\n    template<typename OtherDerived>\n    const Product<Transpose, OtherDerived, AliasFreeProduct>\n    operator*(const MatrixBase<OtherDerived>& matrix) const\n    {\n      return Product<Transpose, OtherDerived, AliasFreeProduct>(*this, matrix.derived());\n    }\n    \n    const TranspositionType& nestedExpression() const { return m_transpositions; }\n\n  protected:\n    const TranspositionType& m_transpositions;\n};\n\n} // end namespace Eigen\n\n#endif // EIGEN_TRANSPOSITIONS_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/TriangularMatrix.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008 Benoit Jacob <jacob.benoit.1@gmail.com>\n// Copyright (C) 2008-2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_TRIANGULARMATRIX_H\n#define EIGEN_TRIANGULARMATRIX_H\n\nnamespace Eigen { \n\nnamespace internal {\n  \ntemplate<int Side, typename TriangularType, typename Rhs> struct triangular_solve_retval;\n  \n}\n\n/** \\class TriangularBase\n  * \\ingroup Core_Module\n  *\n  * \\brief Base class for triangular part in a matrix\n  */\ntemplate<typename Derived> class TriangularBase : public EigenBase<Derived>\n{\n  public:\n\n    enum {\n      Mode = internal::traits<Derived>::Mode,\n      RowsAtCompileTime = internal::traits<Derived>::RowsAtCompileTime,\n      ColsAtCompileTime = internal::traits<Derived>::ColsAtCompileTime,\n      MaxRowsAtCompileTime = internal::traits<Derived>::MaxRowsAtCompileTime,\n      MaxColsAtCompileTime = internal::traits<Derived>::MaxColsAtCompileTime,\n      \n      SizeAtCompileTime = (internal::size_at_compile_time<internal::traits<Derived>::RowsAtCompileTime,\n                                                   internal::traits<Derived>::ColsAtCompileTime>::ret),\n      /**< This is equal to the number of coefficients, i.e. the number of\n          * rows times the number of columns, or to \\a Dynamic if this is not\n          * known at compile-time. \\sa RowsAtCompileTime, ColsAtCompileTime */\n      \n      MaxSizeAtCompileTime = (internal::size_at_compile_time<internal::traits<Derived>::MaxRowsAtCompileTime,\n                                                   internal::traits<Derived>::MaxColsAtCompileTime>::ret)\n        \n    };\n    typedef typename internal::traits<Derived>::Scalar Scalar;\n    typedef typename internal::traits<Derived>::StorageKind StorageKind;\n    typedef typename internal::traits<Derived>::StorageIndex StorageIndex;\n    typedef typename internal::traits<Derived>::FullMatrixType DenseMatrixType;\n    typedef DenseMatrixType DenseType;\n    typedef Derived const& Nested;\n\n    EIGEN_DEVICE_FUNC\n    inline TriangularBase() { eigen_assert(!((Mode&UnitDiag) && (Mode&ZeroDiag))); }\n\n    EIGEN_DEVICE_FUNC\n    inline Index rows() const { return derived().rows(); }\n    EIGEN_DEVICE_FUNC\n    inline Index cols() const { return derived().cols(); }\n    EIGEN_DEVICE_FUNC\n    inline Index outerStride() const { return derived().outerStride(); }\n    EIGEN_DEVICE_FUNC\n    inline Index innerStride() const { return derived().innerStride(); }\n    \n    // dummy resize function\n    void resize(Index rows, Index cols)\n    {\n      EIGEN_UNUSED_VARIABLE(rows);\n      EIGEN_UNUSED_VARIABLE(cols);\n      eigen_assert(rows==this->rows() && cols==this->cols());\n    }\n\n    EIGEN_DEVICE_FUNC\n    inline Scalar coeff(Index row, Index col) const  { return derived().coeff(row,col); }\n    EIGEN_DEVICE_FUNC\n    inline Scalar& coeffRef(Index row, Index col) { return derived().coeffRef(row,col); }\n\n    /** \\see MatrixBase::copyCoeff(row,col)\n      */\n    template<typename Other>\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE void copyCoeff(Index row, Index col, Other& other)\n    {\n      derived().coeffRef(row, col) = other.coeff(row, col);\n    }\n\n    EIGEN_DEVICE_FUNC\n    inline Scalar operator()(Index row, Index col) const\n    {\n      check_coordinates(row, col);\n      return coeff(row,col);\n    }\n    EIGEN_DEVICE_FUNC\n    inline Scalar& operator()(Index row, Index col)\n    {\n      check_coordinates(row, col);\n      return coeffRef(row,col);\n    }\n\n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    EIGEN_DEVICE_FUNC\n    inline const Derived& derived() const { return *static_cast<const Derived*>(this); }\n    EIGEN_DEVICE_FUNC\n    inline Derived& derived() { return *static_cast<Derived*>(this); }\n    #endif // not EIGEN_PARSED_BY_DOXYGEN\n\n    template<typename DenseDerived>\n    EIGEN_DEVICE_FUNC\n    void evalTo(MatrixBase<DenseDerived> &other) const;\n    template<typename DenseDerived>\n    EIGEN_DEVICE_FUNC\n    void evalToLazy(MatrixBase<DenseDerived> &other) const;\n\n    EIGEN_DEVICE_FUNC\n    DenseMatrixType toDenseMatrix() const\n    {\n      DenseMatrixType res(rows(), cols());\n      evalToLazy(res);\n      return res;\n    }\n\n  protected:\n\n    void check_coordinates(Index row, Index col) const\n    {\n      EIGEN_ONLY_USED_FOR_DEBUG(row);\n      EIGEN_ONLY_USED_FOR_DEBUG(col);\n      eigen_assert(col>=0 && col<cols() && row>=0 && row<rows());\n      const int mode = int(Mode) & ~SelfAdjoint;\n      EIGEN_ONLY_USED_FOR_DEBUG(mode);\n      eigen_assert((mode==Upper && col>=row)\n                || (mode==Lower && col<=row)\n                || ((mode==StrictlyUpper || mode==UnitUpper) && col>row)\n                || ((mode==StrictlyLower || mode==UnitLower) && col<row));\n    }\n\n    #ifdef EIGEN_INTERNAL_DEBUGGING\n    void check_coordinates_internal(Index row, Index col) const\n    {\n      check_coordinates(row, col);\n    }\n    #else\n    void check_coordinates_internal(Index , Index ) const {}\n    #endif\n\n};\n\n/** \\class TriangularView\n  * \\ingroup Core_Module\n  *\n  * \\brief Expression of a triangular part in a matrix\n  *\n  * \\param MatrixType the type of the object in which we are taking the triangular part\n  * \\param Mode the kind of triangular matrix expression to construct. Can be #Upper,\n  *             #Lower, #UnitUpper, #UnitLower, #StrictlyUpper, or #StrictlyLower.\n  *             This is in fact a bit field; it must have either #Upper or #Lower, \n  *             and additionally it may have #UnitDiag or #ZeroDiag or neither.\n  *\n  * This class represents a triangular part of a matrix, not necessarily square. Strictly speaking, for rectangular\n  * matrices one should speak of \"trapezoid\" parts. This class is the return type\n  * of MatrixBase::triangularView() and SparseMatrixBase::triangularView(), and most of the time this is the only way it is used.\n  *\n  * \\sa MatrixBase::triangularView()\n  */\nnamespace internal {\ntemplate<typename MatrixType, unsigned int _Mode>\nstruct traits<TriangularView<MatrixType, _Mode> > : traits<MatrixType>\n{\n  typedef typename ref_selector<MatrixType>::non_const_type MatrixTypeNested;\n  typedef typename remove_reference<MatrixTypeNested>::type MatrixTypeNestedNonRef;\n  typedef typename remove_all<MatrixTypeNested>::type MatrixTypeNestedCleaned;\n  typedef typename MatrixType::PlainObject FullMatrixType;\n  typedef MatrixType ExpressionType;\n  enum {\n    Mode = _Mode,\n    FlagsLvalueBit = is_lvalue<MatrixType>::value ? LvalueBit : 0,\n    Flags = (MatrixTypeNestedCleaned::Flags & (HereditaryBits | FlagsLvalueBit) & (~(PacketAccessBit | DirectAccessBit | LinearAccessBit)))\n  };\n};\n}\n\ntemplate<typename _MatrixType, unsigned int _Mode, typename StorageKind> class TriangularViewImpl;\n\ntemplate<typename _MatrixType, unsigned int _Mode> class TriangularView\n  : public TriangularViewImpl<_MatrixType, _Mode, typename internal::traits<_MatrixType>::StorageKind >\n{\n  public:\n\n    typedef TriangularViewImpl<_MatrixType, _Mode, typename internal::traits<_MatrixType>::StorageKind > Base;\n    typedef typename internal::traits<TriangularView>::Scalar Scalar;\n    typedef _MatrixType MatrixType;\n\n  protected:\n    typedef typename internal::traits<TriangularView>::MatrixTypeNested MatrixTypeNested;\n    typedef typename internal::traits<TriangularView>::MatrixTypeNestedNonRef MatrixTypeNestedNonRef;\n\n    typedef typename internal::remove_all<typename MatrixType::ConjugateReturnType>::type MatrixConjugateReturnType;\n    \n  public:\n\n    typedef typename internal::traits<TriangularView>::StorageKind StorageKind;\n    typedef typename internal::traits<TriangularView>::MatrixTypeNestedCleaned NestedExpression;\n\n    enum {\n      Mode = _Mode,\n      Flags = internal::traits<TriangularView>::Flags,\n      TransposeMode = (Mode & Upper ? Lower : 0)\n                    | (Mode & Lower ? Upper : 0)\n                    | (Mode & (UnitDiag))\n                    | (Mode & (ZeroDiag)),\n      IsVectorAtCompileTime = false\n    };\n\n    EIGEN_DEVICE_FUNC\n    explicit inline TriangularView(MatrixType& matrix) : m_matrix(matrix)\n    {}\n    \n    using Base::operator=;\n    TriangularView& operator=(const TriangularView &other)\n    { return Base::operator=(other); }\n\n    /** \\copydoc EigenBase::rows() */\n    EIGEN_DEVICE_FUNC\n    inline Index rows() const { return m_matrix.rows(); }\n    /** \\copydoc EigenBase::cols() */\n    EIGEN_DEVICE_FUNC\n    inline Index cols() const { return m_matrix.cols(); }\n\n    /** \\returns a const reference to the nested expression */\n    EIGEN_DEVICE_FUNC\n    const NestedExpression& nestedExpression() const { return m_matrix; }\n\n    /** \\returns a reference to the nested expression */\n    EIGEN_DEVICE_FUNC\n    NestedExpression& nestedExpression() { return m_matrix; }\n    \n    typedef TriangularView<const MatrixConjugateReturnType,Mode> ConjugateReturnType;\n    /** \\sa MatrixBase::conjugate() const */\n    EIGEN_DEVICE_FUNC\n    inline const ConjugateReturnType conjugate() const\n    { return ConjugateReturnType(m_matrix.conjugate()); }\n\n    typedef TriangularView<const typename MatrixType::AdjointReturnType,TransposeMode> AdjointReturnType;\n    /** \\sa MatrixBase::adjoint() const */\n    EIGEN_DEVICE_FUNC\n    inline const AdjointReturnType adjoint() const\n    { return AdjointReturnType(m_matrix.adjoint()); }\n\n    typedef TriangularView<typename MatrixType::TransposeReturnType,TransposeMode> TransposeReturnType;\n     /** \\sa MatrixBase::transpose() */\n    EIGEN_DEVICE_FUNC\n    inline TransposeReturnType transpose()\n    {\n      EIGEN_STATIC_ASSERT_LVALUE(MatrixType)\n      typename MatrixType::TransposeReturnType tmp(m_matrix);\n      return TransposeReturnType(tmp);\n    }\n    \n    typedef TriangularView<const typename MatrixType::ConstTransposeReturnType,TransposeMode> ConstTransposeReturnType;\n    /** \\sa MatrixBase::transpose() const */\n    EIGEN_DEVICE_FUNC\n    inline const ConstTransposeReturnType transpose() const\n    {\n      return ConstTransposeReturnType(m_matrix.transpose());\n    }\n\n    template<typename Other>\n    EIGEN_DEVICE_FUNC\n    inline const Solve<TriangularView, Other> \n    solve(const MatrixBase<Other>& other) const\n    { return Solve<TriangularView, Other>(*this, other.derived()); }\n    \n  // workaround MSVC ICE\n  #if EIGEN_COMP_MSVC\n    template<int Side, typename Other>\n    EIGEN_DEVICE_FUNC\n    inline const internal::triangular_solve_retval<Side,TriangularView, Other>\n    solve(const MatrixBase<Other>& other) const\n    { return Base::template solve<Side>(other); }\n  #else\n    using Base::solve;\n  #endif\n\n    /** \\returns a selfadjoint view of the referenced triangular part which must be either \\c #Upper or \\c #Lower.\n      *\n      * This is a shortcut for \\code this->nestedExpression().selfadjointView<(*this)::Mode>() \\endcode\n      * \\sa MatrixBase::selfadjointView() */\n    EIGEN_DEVICE_FUNC\n    SelfAdjointView<MatrixTypeNestedNonRef,Mode> selfadjointView()\n    {\n      EIGEN_STATIC_ASSERT((Mode&(UnitDiag|ZeroDiag))==0,PROGRAMMING_ERROR);\n      return SelfAdjointView<MatrixTypeNestedNonRef,Mode>(m_matrix);\n    }\n\n    /** This is the const version of selfadjointView() */\n    EIGEN_DEVICE_FUNC\n    const SelfAdjointView<MatrixTypeNestedNonRef,Mode> selfadjointView() const\n    {\n      EIGEN_STATIC_ASSERT((Mode&(UnitDiag|ZeroDiag))==0,PROGRAMMING_ERROR);\n      return SelfAdjointView<MatrixTypeNestedNonRef,Mode>(m_matrix);\n    }\n\n\n    /** \\returns the determinant of the triangular matrix\n      * \\sa MatrixBase::determinant() */\n    EIGEN_DEVICE_FUNC\n    Scalar determinant() const\n    {\n      if (Mode & UnitDiag)\n        return 1;\n      else if (Mode & ZeroDiag)\n        return 0;\n      else\n        return m_matrix.diagonal().prod();\n    }\n      \n  protected:\n\n    MatrixTypeNested m_matrix;\n};\n\n/** \\ingroup Core_Module\n  *\n  * \\brief Base class for a triangular part in a \\b dense matrix\n  *\n  * This class is an abstract base class of class TriangularView, and objects of type TriangularViewImpl cannot be instantiated.\n  * It extends class TriangularView with additional methods which available for dense expressions only.\n  *\n  * \\sa class TriangularView, MatrixBase::triangularView()\n  */\ntemplate<typename _MatrixType, unsigned int _Mode> class TriangularViewImpl<_MatrixType,_Mode,Dense>\n  : public TriangularBase<TriangularView<_MatrixType, _Mode> >\n{\n  public:\n\n    typedef TriangularView<_MatrixType, _Mode> TriangularViewType;\n    typedef TriangularBase<TriangularViewType> Base;\n    typedef typename internal::traits<TriangularViewType>::Scalar Scalar;\n\n    typedef _MatrixType MatrixType;\n    typedef typename MatrixType::PlainObject DenseMatrixType;\n    typedef DenseMatrixType PlainObject;\n\n  public:\n    using Base::evalToLazy;\n    using Base::derived;\n\n    typedef typename internal::traits<TriangularViewType>::StorageKind StorageKind;\n\n    enum {\n      Mode = _Mode,\n      Flags = internal::traits<TriangularViewType>::Flags\n    };\n\n    /** \\returns the outer-stride of the underlying dense matrix\n      * \\sa DenseCoeffsBase::outerStride() */\n    EIGEN_DEVICE_FUNC\n    inline Index outerStride() const { return derived().nestedExpression().outerStride(); }\n    /** \\returns the inner-stride of the underlying dense matrix\n      * \\sa DenseCoeffsBase::innerStride() */\n    EIGEN_DEVICE_FUNC\n    inline Index innerStride() const { return derived().nestedExpression().innerStride(); }\n\n    /** \\sa MatrixBase::operator+=() */\n    template<typename Other>\n    EIGEN_DEVICE_FUNC\n    TriangularViewType&  operator+=(const DenseBase<Other>& other) {\n      internal::call_assignment_no_alias(derived(), other.derived(), internal::add_assign_op<Scalar,typename Other::Scalar>());\n      return derived();\n    }\n    /** \\sa MatrixBase::operator-=() */\n    template<typename Other>\n    EIGEN_DEVICE_FUNC\n    TriangularViewType&  operator-=(const DenseBase<Other>& other) {\n      internal::call_assignment_no_alias(derived(), other.derived(), internal::sub_assign_op<Scalar,typename Other::Scalar>());\n      return derived();\n    }\n    \n    /** \\sa MatrixBase::operator*=() */\n    EIGEN_DEVICE_FUNC\n    TriangularViewType&  operator*=(const typename internal::traits<MatrixType>::Scalar& other) { return *this = derived().nestedExpression() * other; }\n    /** \\sa DenseBase::operator/=() */\n    EIGEN_DEVICE_FUNC\n    TriangularViewType&  operator/=(const typename internal::traits<MatrixType>::Scalar& other) { return *this = derived().nestedExpression() / other; }\n\n    /** \\sa MatrixBase::fill() */\n    EIGEN_DEVICE_FUNC\n    void fill(const Scalar& value) { setConstant(value); }\n    /** \\sa MatrixBase::setConstant() */\n    EIGEN_DEVICE_FUNC\n    TriangularViewType& setConstant(const Scalar& value)\n    { return *this = MatrixType::Constant(derived().rows(), derived().cols(), value); }\n    /** \\sa MatrixBase::setZero() */\n    EIGEN_DEVICE_FUNC\n    TriangularViewType& setZero() { return setConstant(Scalar(0)); }\n    /** \\sa MatrixBase::setOnes() */\n    EIGEN_DEVICE_FUNC\n    TriangularViewType& setOnes() { return setConstant(Scalar(1)); }\n\n    /** \\sa MatrixBase::coeff()\n      * \\warning the coordinates must fit into the referenced triangular part\n      */\n    EIGEN_DEVICE_FUNC\n    inline Scalar coeff(Index row, Index col) const\n    {\n      Base::check_coordinates_internal(row, col);\n      return derived().nestedExpression().coeff(row, col);\n    }\n\n    /** \\sa MatrixBase::coeffRef()\n      * \\warning the coordinates must fit into the referenced triangular part\n      */\n    EIGEN_DEVICE_FUNC\n    inline Scalar& coeffRef(Index row, Index col)\n    {\n      EIGEN_STATIC_ASSERT_LVALUE(TriangularViewType);\n      Base::check_coordinates_internal(row, col);\n      return derived().nestedExpression().coeffRef(row, col);\n    }\n\n    /** Assigns a triangular matrix to a triangular part of a dense matrix */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    TriangularViewType& operator=(const TriangularBase<OtherDerived>& other);\n\n    /** Shortcut for\\code *this = other.other.triangularView<(*this)::Mode>() \\endcode */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    TriangularViewType& operator=(const MatrixBase<OtherDerived>& other);\n\n#ifndef EIGEN_PARSED_BY_DOXYGEN\n    EIGEN_DEVICE_FUNC\n    TriangularViewType& operator=(const TriangularViewImpl& other)\n    { return *this = other.derived().nestedExpression(); }\n\n    /** \\deprecated */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    void lazyAssign(const TriangularBase<OtherDerived>& other);\n\n    /** \\deprecated */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    void lazyAssign(const MatrixBase<OtherDerived>& other);\n#endif\n\n    /** Efficient triangular matrix times vector/matrix product */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    const Product<TriangularViewType,OtherDerived>\n    operator*(const MatrixBase<OtherDerived>& rhs) const\n    {\n      return Product<TriangularViewType,OtherDerived>(derived(), rhs.derived());\n    }\n\n    /** Efficient vector/matrix times triangular matrix product */\n    template<typename OtherDerived> friend\n    EIGEN_DEVICE_FUNC\n    const Product<OtherDerived,TriangularViewType>\n    operator*(const MatrixBase<OtherDerived>& lhs, const TriangularViewImpl& rhs)\n    {\n      return Product<OtherDerived,TriangularViewType>(lhs.derived(),rhs.derived());\n    }\n\n    /** \\returns the product of the inverse of \\c *this with \\a other, \\a *this being triangular.\n      *\n      * This function computes the inverse-matrix matrix product inverse(\\c *this) * \\a other if\n      * \\a Side==OnTheLeft (the default), or the right-inverse-multiply  \\a other * inverse(\\c *this) if\n      * \\a Side==OnTheRight.\n      *\n      * The matrix \\c *this must be triangular and invertible (i.e., all the coefficients of the\n      * diagonal must be non zero). It works as a forward (resp. backward) substitution if \\c *this\n      * is an upper (resp. lower) triangular matrix.\n      *\n      * Example: \\include Triangular_solve.cpp\n      * Output: \\verbinclude Triangular_solve.out\n      *\n      * This function returns an expression of the inverse-multiply and can works in-place if it is assigned\n      * to the same matrix or vector \\a other.\n      *\n      * For users coming from BLAS, this function (and more specifically solveInPlace()) offer\n      * all the operations supported by the \\c *TRSV and \\c *TRSM BLAS routines.\n      *\n      * \\sa TriangularView::solveInPlace()\n      */\n    template<int Side, typename Other>\n    EIGEN_DEVICE_FUNC\n    inline const internal::triangular_solve_retval<Side,TriangularViewType, Other>\n    solve(const MatrixBase<Other>& other) const;\n\n    /** \"in-place\" version of TriangularView::solve() where the result is written in \\a other\n      *\n      * \\warning The parameter is only marked 'const' to make the C++ compiler accept a temporary expression here.\n      * This function will const_cast it, so constness isn't honored here.\n      *\n      * See TriangularView:solve() for the details.\n      */\n    template<int Side, typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    void solveInPlace(const MatrixBase<OtherDerived>& other) const;\n\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    void solveInPlace(const MatrixBase<OtherDerived>& other) const\n    { return solveInPlace<OnTheLeft>(other); }\n\n    /** Swaps the coefficients of the common triangular parts of two matrices */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n#ifdef EIGEN_PARSED_BY_DOXYGEN\n    void swap(TriangularBase<OtherDerived> &other)\n#else\n    void swap(TriangularBase<OtherDerived> const & other)\n#endif\n    {\n      EIGEN_STATIC_ASSERT_LVALUE(OtherDerived);\n      call_assignment(derived(), other.const_cast_derived(), internal::swap_assign_op<Scalar>());\n    }\n\n    /** \\deprecated\n      * Shortcut for \\code (*this).swap(other.triangularView<(*this)::Mode>()) \\endcode */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    void swap(MatrixBase<OtherDerived> const & other)\n    {\n      EIGEN_STATIC_ASSERT_LVALUE(OtherDerived);\n      call_assignment(derived(), other.const_cast_derived(), internal::swap_assign_op<Scalar>());\n    }\n\n    template<typename RhsType, typename DstType>\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE void _solve_impl(const RhsType &rhs, DstType &dst) const {\n      if(!internal::is_same_dense(dst,rhs))\n        dst = rhs;\n      this->solveInPlace(dst);\n    }\n\n    template<typename ProductType>\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE TriangularViewType& _assignProduct(const ProductType& prod, const Scalar& alpha);\n};\n\n/***************************************************************************\n* Implementation of triangular evaluation/assignment\n***************************************************************************/\n\n// FIXME should we keep that possibility\ntemplate<typename MatrixType, unsigned int Mode>\ntemplate<typename OtherDerived>\ninline TriangularView<MatrixType, Mode>&\nTriangularViewImpl<MatrixType, Mode, Dense>::operator=(const MatrixBase<OtherDerived>& other)\n{\n  internal::call_assignment_no_alias(derived(), other.derived(), internal::assign_op<Scalar,typename OtherDerived::Scalar>());\n  return derived();\n}\n\n// FIXME should we keep that possibility\ntemplate<typename MatrixType, unsigned int Mode>\ntemplate<typename OtherDerived>\nvoid TriangularViewImpl<MatrixType, Mode, Dense>::lazyAssign(const MatrixBase<OtherDerived>& other)\n{\n  internal::call_assignment_no_alias(derived(), other.template triangularView<Mode>());\n}\n\n\n\ntemplate<typename MatrixType, unsigned int Mode>\ntemplate<typename OtherDerived>\ninline TriangularView<MatrixType, Mode>&\nTriangularViewImpl<MatrixType, Mode, Dense>::operator=(const TriangularBase<OtherDerived>& other)\n{\n  eigen_assert(Mode == int(OtherDerived::Mode));\n  internal::call_assignment(derived(), other.derived());\n  return derived();\n}\n\ntemplate<typename MatrixType, unsigned int Mode>\ntemplate<typename OtherDerived>\nvoid TriangularViewImpl<MatrixType, Mode, Dense>::lazyAssign(const TriangularBase<OtherDerived>& other)\n{\n  eigen_assert(Mode == int(OtherDerived::Mode));\n  internal::call_assignment_no_alias(derived(), other.derived());\n}\n\n/***************************************************************************\n* Implementation of TriangularBase methods\n***************************************************************************/\n\n/** Assigns a triangular or selfadjoint matrix to a dense matrix.\n  * If the matrix is triangular, the opposite part is set to zero. */\ntemplate<typename Derived>\ntemplate<typename DenseDerived>\nvoid TriangularBase<Derived>::evalTo(MatrixBase<DenseDerived> &other) const\n{\n  evalToLazy(other.derived());\n}\n\n/***************************************************************************\n* Implementation of TriangularView methods\n***************************************************************************/\n\n/***************************************************************************\n* Implementation of MatrixBase methods\n***************************************************************************/\n\n/**\n  * \\returns an expression of a triangular view extracted from the current matrix\n  *\n  * The parameter \\a Mode can have the following values: \\c #Upper, \\c #StrictlyUpper, \\c #UnitUpper,\n  * \\c #Lower, \\c #StrictlyLower, \\c #UnitLower.\n  *\n  * Example: \\include MatrixBase_triangularView.cpp\n  * Output: \\verbinclude MatrixBase_triangularView.out\n  *\n  * \\sa class TriangularView\n  */\ntemplate<typename Derived>\ntemplate<unsigned int Mode>\ntypename MatrixBase<Derived>::template TriangularViewReturnType<Mode>::Type\nMatrixBase<Derived>::triangularView()\n{\n  return typename TriangularViewReturnType<Mode>::Type(derived());\n}\n\n/** This is the const version of MatrixBase::triangularView() */\ntemplate<typename Derived>\ntemplate<unsigned int Mode>\ntypename MatrixBase<Derived>::template ConstTriangularViewReturnType<Mode>::Type\nMatrixBase<Derived>::triangularView() const\n{\n  return typename ConstTriangularViewReturnType<Mode>::Type(derived());\n}\n\n/** \\returns true if *this is approximately equal to an upper triangular matrix,\n  *          within the precision given by \\a prec.\n  *\n  * \\sa isLowerTriangular()\n  */\ntemplate<typename Derived>\nbool MatrixBase<Derived>::isUpperTriangular(const RealScalar& prec) const\n{\n  RealScalar maxAbsOnUpperPart = static_cast<RealScalar>(-1);\n  for(Index j = 0; j < cols(); ++j)\n  {\n    Index maxi = numext::mini(j, rows()-1);\n    for(Index i = 0; i <= maxi; ++i)\n    {\n      RealScalar absValue = numext::abs(coeff(i,j));\n      if(absValue > maxAbsOnUpperPart) maxAbsOnUpperPart = absValue;\n    }\n  }\n  RealScalar threshold = maxAbsOnUpperPart * prec;\n  for(Index j = 0; j < cols(); ++j)\n    for(Index i = j+1; i < rows(); ++i)\n      if(numext::abs(coeff(i, j)) > threshold) return false;\n  return true;\n}\n\n/** \\returns true if *this is approximately equal to a lower triangular matrix,\n  *          within the precision given by \\a prec.\n  *\n  * \\sa isUpperTriangular()\n  */\ntemplate<typename Derived>\nbool MatrixBase<Derived>::isLowerTriangular(const RealScalar& prec) const\n{\n  RealScalar maxAbsOnLowerPart = static_cast<RealScalar>(-1);\n  for(Index j = 0; j < cols(); ++j)\n    for(Index i = j; i < rows(); ++i)\n    {\n      RealScalar absValue = numext::abs(coeff(i,j));\n      if(absValue > maxAbsOnLowerPart) maxAbsOnLowerPart = absValue;\n    }\n  RealScalar threshold = maxAbsOnLowerPart * prec;\n  for(Index j = 1; j < cols(); ++j)\n  {\n    Index maxi = numext::mini(j, rows()-1);\n    for(Index i = 0; i < maxi; ++i)\n      if(numext::abs(coeff(i, j)) > threshold) return false;\n  }\n  return true;\n}\n\n\n/***************************************************************************\n****************************************************************************\n* Evaluators and Assignment of triangular expressions\n***************************************************************************\n***************************************************************************/\n\nnamespace internal {\n\n  \n// TODO currently a triangular expression has the form TriangularView<.,.>\n//      in the future triangular-ness should be defined by the expression traits\n//      such that Transpose<TriangularView<.,.> > is valid. (currently TriangularBase::transpose() is overloaded to make it work)\ntemplate<typename MatrixType, unsigned int Mode>\nstruct evaluator_traits<TriangularView<MatrixType,Mode> >\n{\n  typedef typename storage_kind_to_evaluator_kind<typename MatrixType::StorageKind>::Kind Kind;\n  typedef typename glue_shapes<typename evaluator_traits<MatrixType>::Shape, TriangularShape>::type Shape;\n};\n\ntemplate<typename MatrixType, unsigned int Mode>\nstruct unary_evaluator<TriangularView<MatrixType,Mode>, IndexBased>\n : evaluator<typename internal::remove_all<MatrixType>::type>\n{\n  typedef TriangularView<MatrixType,Mode> XprType;\n  typedef evaluator<typename internal::remove_all<MatrixType>::type> Base;\n  unary_evaluator(const XprType &xpr) : Base(xpr.nestedExpression()) {}\n};\n\n// Additional assignment kinds:\nstruct Triangular2Triangular    {};\nstruct Triangular2Dense         {};\nstruct Dense2Triangular         {};\n\n\ntemplate<typename Kernel, unsigned int Mode, int UnrollCount, bool ClearOpposite> struct triangular_assignment_loop;\n\n \n/** \\internal Specialization of the dense assignment kernel for triangular matrices.\n  * The main difference is that the triangular, diagonal, and opposite parts are processed through three different functions.\n  * \\tparam UpLo must be either Lower or Upper\n  * \\tparam Mode must be either 0, UnitDiag, ZeroDiag, or SelfAdjoint\n  */\ntemplate<int UpLo, int Mode, int SetOpposite, typename DstEvaluatorTypeT, typename SrcEvaluatorTypeT, typename Functor, int Version = Specialized>\nclass triangular_dense_assignment_kernel : public generic_dense_assignment_kernel<DstEvaluatorTypeT, SrcEvaluatorTypeT, Functor, Version>\n{\nprotected:\n  typedef generic_dense_assignment_kernel<DstEvaluatorTypeT, SrcEvaluatorTypeT, Functor, Version> Base;\n  typedef typename Base::DstXprType DstXprType;\n  typedef typename Base::SrcXprType SrcXprType;\n  using Base::m_dst;\n  using Base::m_src;\n  using Base::m_functor;\npublic:\n  \n  typedef typename Base::DstEvaluatorType DstEvaluatorType;\n  typedef typename Base::SrcEvaluatorType SrcEvaluatorType;\n  typedef typename Base::Scalar Scalar;\n  typedef typename Base::AssignmentTraits AssignmentTraits;\n  \n  \n  EIGEN_DEVICE_FUNC triangular_dense_assignment_kernel(DstEvaluatorType &dst, const SrcEvaluatorType &src, const Functor &func, DstXprType& dstExpr)\n    : Base(dst, src, func, dstExpr)\n  {}\n  \n#ifdef EIGEN_INTERNAL_DEBUGGING\n  EIGEN_DEVICE_FUNC void assignCoeff(Index row, Index col)\n  {\n    eigen_internal_assert(row!=col);\n    Base::assignCoeff(row,col);\n  }\n#else\n  using Base::assignCoeff;\n#endif\n  \n  EIGEN_DEVICE_FUNC void assignDiagonalCoeff(Index id)\n  {\n         if(Mode==UnitDiag && SetOpposite) m_functor.assignCoeff(m_dst.coeffRef(id,id), Scalar(1));\n    else if(Mode==ZeroDiag && SetOpposite) m_functor.assignCoeff(m_dst.coeffRef(id,id), Scalar(0));\n    else if(Mode==0)                       Base::assignCoeff(id,id);\n  }\n  \n  EIGEN_DEVICE_FUNC void assignOppositeCoeff(Index row, Index col)\n  { \n    eigen_internal_assert(row!=col);\n    if(SetOpposite)\n      m_functor.assignCoeff(m_dst.coeffRef(row,col), Scalar(0));\n  }\n};\n\ntemplate<int Mode, bool SetOpposite, typename DstXprType, typename SrcXprType, typename Functor>\nEIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\nvoid call_triangular_assignment_loop(DstXprType& dst, const SrcXprType& src, const Functor &func)\n{\n  typedef evaluator<DstXprType> DstEvaluatorType;\n  typedef evaluator<SrcXprType> SrcEvaluatorType;\n\n  SrcEvaluatorType srcEvaluator(src);\n\n  Index dstRows = src.rows();\n  Index dstCols = src.cols();\n  if((dst.rows()!=dstRows) || (dst.cols()!=dstCols))\n    dst.resize(dstRows, dstCols);\n  DstEvaluatorType dstEvaluator(dst);\n    \n  typedef triangular_dense_assignment_kernel< Mode&(Lower|Upper),Mode&(UnitDiag|ZeroDiag|SelfAdjoint),SetOpposite,\n                                              DstEvaluatorType,SrcEvaluatorType,Functor> Kernel;\n  Kernel kernel(dstEvaluator, srcEvaluator, func, dst.const_cast_derived());\n  \n  enum {\n      unroll = DstXprType::SizeAtCompileTime != Dynamic\n            && SrcEvaluatorType::CoeffReadCost < HugeCost\n            && DstXprType::SizeAtCompileTime * (DstEvaluatorType::CoeffReadCost+SrcEvaluatorType::CoeffReadCost) / 2 <= EIGEN_UNROLLING_LIMIT\n    };\n  \n  triangular_assignment_loop<Kernel, Mode, unroll ? int(DstXprType::SizeAtCompileTime) : Dynamic, SetOpposite>::run(kernel);\n}\n\ntemplate<int Mode, bool SetOpposite, typename DstXprType, typename SrcXprType>\nEIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\nvoid call_triangular_assignment_loop(DstXprType& dst, const SrcXprType& src)\n{\n  call_triangular_assignment_loop<Mode,SetOpposite>(dst, src, internal::assign_op<typename DstXprType::Scalar,typename SrcXprType::Scalar>());\n}\n\ntemplate<> struct AssignmentKind<TriangularShape,TriangularShape> { typedef Triangular2Triangular Kind; };\ntemplate<> struct AssignmentKind<DenseShape,TriangularShape>      { typedef Triangular2Dense      Kind; };\ntemplate<> struct AssignmentKind<TriangularShape,DenseShape>      { typedef Dense2Triangular      Kind; };\n\n\ntemplate< typename DstXprType, typename SrcXprType, typename Functor>\nstruct Assignment<DstXprType, SrcXprType, Functor, Triangular2Triangular>\n{\n  EIGEN_DEVICE_FUNC static void run(DstXprType &dst, const SrcXprType &src, const Functor &func)\n  {\n    eigen_assert(int(DstXprType::Mode) == int(SrcXprType::Mode));\n    \n    call_triangular_assignment_loop<DstXprType::Mode, false>(dst, src, func);  \n  }\n};\n\ntemplate< typename DstXprType, typename SrcXprType, typename Functor>\nstruct Assignment<DstXprType, SrcXprType, Functor, Triangular2Dense>\n{\n  EIGEN_DEVICE_FUNC static void run(DstXprType &dst, const SrcXprType &src, const Functor &func)\n  {\n    call_triangular_assignment_loop<SrcXprType::Mode, (SrcXprType::Mode&SelfAdjoint)==0>(dst, src, func);  \n  }\n};\n\ntemplate< typename DstXprType, typename SrcXprType, typename Functor>\nstruct Assignment<DstXprType, SrcXprType, Functor, Dense2Triangular>\n{\n  EIGEN_DEVICE_FUNC static void run(DstXprType &dst, const SrcXprType &src, const Functor &func)\n  {\n    call_triangular_assignment_loop<DstXprType::Mode, false>(dst, src, func);  \n  }\n};\n\n\ntemplate<typename Kernel, unsigned int Mode, int UnrollCount, bool SetOpposite>\nstruct triangular_assignment_loop\n{\n  // FIXME: this is not very clean, perhaps this information should be provided by the kernel?\n  typedef typename Kernel::DstEvaluatorType DstEvaluatorType;\n  typedef typename DstEvaluatorType::XprType DstXprType;\n  \n  enum {\n    col = (UnrollCount-1) / DstXprType::RowsAtCompileTime,\n    row = (UnrollCount-1) % DstXprType::RowsAtCompileTime\n  };\n  \n  typedef typename Kernel::Scalar Scalar;\n\n  EIGEN_DEVICE_FUNC\n  static inline void run(Kernel &kernel)\n  {\n    triangular_assignment_loop<Kernel, Mode, UnrollCount-1, SetOpposite>::run(kernel);\n    \n    if(row==col)\n      kernel.assignDiagonalCoeff(row);\n    else if( ((Mode&Lower) && row>col) || ((Mode&Upper) && row<col) )\n      kernel.assignCoeff(row,col);\n    else if(SetOpposite)\n      kernel.assignOppositeCoeff(row,col);\n  }\n};\n\n// prevent buggy user code from causing an infinite recursion\ntemplate<typename Kernel, unsigned int Mode, bool SetOpposite>\nstruct triangular_assignment_loop<Kernel, Mode, 0, SetOpposite>\n{\n  EIGEN_DEVICE_FUNC\n  static inline void run(Kernel &) {}\n};\n\n\n\n// TODO: experiment with a recursive assignment procedure splitting the current\n//       triangular part into one rectangular and two triangular parts.\n\n\ntemplate<typename Kernel, unsigned int Mode, bool SetOpposite>\nstruct triangular_assignment_loop<Kernel, Mode, Dynamic, SetOpposite>\n{\n  typedef typename Kernel::Scalar Scalar;\n  EIGEN_DEVICE_FUNC\n  static inline void run(Kernel &kernel)\n  {\n    for(Index j = 0; j < kernel.cols(); ++j)\n    {\n      Index maxi = numext::mini(j, kernel.rows());\n      Index i = 0;\n      if (((Mode&Lower) && SetOpposite) || (Mode&Upper))\n      {\n        for(; i < maxi; ++i)\n          if(Mode&Upper) kernel.assignCoeff(i, j);\n          else           kernel.assignOppositeCoeff(i, j);\n      }\n      else\n        i = maxi;\n      \n      if(i<kernel.rows()) // then i==j\n        kernel.assignDiagonalCoeff(i++);\n      \n      if (((Mode&Upper) && SetOpposite) || (Mode&Lower))\n      {\n        for(; i < kernel.rows(); ++i)\n          if(Mode&Lower) kernel.assignCoeff(i, j);\n          else           kernel.assignOppositeCoeff(i, j);\n      }\n    }\n  }\n};\n\n} // end namespace internal\n\n/** Assigns a triangular or selfadjoint matrix to a dense matrix.\n  * If the matrix is triangular, the opposite part is set to zero. */\ntemplate<typename Derived>\ntemplate<typename DenseDerived>\nvoid TriangularBase<Derived>::evalToLazy(MatrixBase<DenseDerived> &other) const\n{\n  other.derived().resize(this->rows(), this->cols());\n  internal::call_triangular_assignment_loop<Derived::Mode,(Derived::Mode&SelfAdjoint)==0 /* SetOpposite */>(other.derived(), derived().nestedExpression());\n}\n\nnamespace internal {\n  \n// Triangular = Product\ntemplate< typename DstXprType, typename Lhs, typename Rhs, typename Scalar>\nstruct Assignment<DstXprType, Product<Lhs,Rhs,DefaultProduct>, internal::assign_op<Scalar,typename Product<Lhs,Rhs,DefaultProduct>::Scalar>, Dense2Triangular>\n{\n  typedef Product<Lhs,Rhs,DefaultProduct> SrcXprType;\n  static void run(DstXprType &dst, const SrcXprType &src, const internal::assign_op<Scalar,typename SrcXprType::Scalar> &)\n  {\n    Index dstRows = src.rows();\n    Index dstCols = src.cols();\n    if((dst.rows()!=dstRows) || (dst.cols()!=dstCols))\n      dst.resize(dstRows, dstCols);\n\n    dst.setZero();\n    dst._assignProduct(src, 1);\n  }\n};\n\n// Triangular += Product\ntemplate< typename DstXprType, typename Lhs, typename Rhs, typename Scalar>\nstruct Assignment<DstXprType, Product<Lhs,Rhs,DefaultProduct>, internal::add_assign_op<Scalar,typename Product<Lhs,Rhs,DefaultProduct>::Scalar>, Dense2Triangular>\n{\n  typedef Product<Lhs,Rhs,DefaultProduct> SrcXprType;\n  static void run(DstXprType &dst, const SrcXprType &src, const internal::add_assign_op<Scalar,typename SrcXprType::Scalar> &)\n  {\n    dst._assignProduct(src, 1);\n  }\n};\n\n// Triangular -= Product\ntemplate< typename DstXprType, typename Lhs, typename Rhs, typename Scalar>\nstruct Assignment<DstXprType, Product<Lhs,Rhs,DefaultProduct>, internal::sub_assign_op<Scalar,typename Product<Lhs,Rhs,DefaultProduct>::Scalar>, Dense2Triangular>\n{\n  typedef Product<Lhs,Rhs,DefaultProduct> SrcXprType;\n  static void run(DstXprType &dst, const SrcXprType &src, const internal::sub_assign_op<Scalar,typename SrcXprType::Scalar> &)\n  {\n    dst._assignProduct(src, -1);\n  }\n};\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_TRIANGULARMATRIX_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/VectorBlock.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2006-2008 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_VECTORBLOCK_H\n#define EIGEN_VECTORBLOCK_H\n\nnamespace Eigen { \n\nnamespace internal {\ntemplate<typename VectorType, int Size>\nstruct traits<VectorBlock<VectorType, Size> >\n  : public traits<Block<VectorType,\n                     traits<VectorType>::Flags & RowMajorBit ? 1 : Size,\n                     traits<VectorType>::Flags & RowMajorBit ? Size : 1> >\n{\n};\n}\n\n/** \\class VectorBlock\n  * \\ingroup Core_Module\n  *\n  * \\brief Expression of a fixed-size or dynamic-size sub-vector\n  *\n  * \\tparam VectorType the type of the object in which we are taking a sub-vector\n  * \\tparam Size size of the sub-vector we are taking at compile time (optional)\n  *\n  * This class represents an expression of either a fixed-size or dynamic-size sub-vector.\n  * It is the return type of DenseBase::segment(Index,Index) and DenseBase::segment<int>(Index) and\n  * most of the time this is the only way it is used.\n  *\n  * However, if you want to directly maniputate sub-vector expressions,\n  * for instance if you want to write a function returning such an expression, you\n  * will need to use this class.\n  *\n  * Here is an example illustrating the dynamic case:\n  * \\include class_VectorBlock.cpp\n  * Output: \\verbinclude class_VectorBlock.out\n  *\n  * \\note Even though this expression has dynamic size, in the case where \\a VectorType\n  * has fixed size, this expression inherits a fixed maximal size which means that evaluating\n  * it does not cause a dynamic memory allocation.\n  *\n  * Here is an example illustrating the fixed-size case:\n  * \\include class_FixedVectorBlock.cpp\n  * Output: \\verbinclude class_FixedVectorBlock.out\n  *\n  * \\sa class Block, DenseBase::segment(Index,Index,Index,Index), DenseBase::segment(Index,Index)\n  */\ntemplate<typename VectorType, int Size> class VectorBlock\n  : public Block<VectorType,\n                     internal::traits<VectorType>::Flags & RowMajorBit ? 1 : Size,\n                     internal::traits<VectorType>::Flags & RowMajorBit ? Size : 1>\n{\n    typedef Block<VectorType,\n                     internal::traits<VectorType>::Flags & RowMajorBit ? 1 : Size,\n                     internal::traits<VectorType>::Flags & RowMajorBit ? Size : 1> Base;\n    enum {\n      IsColVector = !(internal::traits<VectorType>::Flags & RowMajorBit)\n    };\n  public:\n    EIGEN_DENSE_PUBLIC_INTERFACE(VectorBlock)\n\n    using Base::operator=;\n\n    /** Dynamic-size constructor\n      */\n    EIGEN_DEVICE_FUNC\n    inline VectorBlock(VectorType& vector, Index start, Index size)\n      : Base(vector,\n             IsColVector ? start : 0, IsColVector ? 0 : start,\n             IsColVector ? size  : 1, IsColVector ? 1 : size)\n    {\n      EIGEN_STATIC_ASSERT_VECTOR_ONLY(VectorBlock);\n    }\n\n    /** Fixed-size constructor\n      */\n    EIGEN_DEVICE_FUNC\n    inline VectorBlock(VectorType& vector, Index start)\n      : Base(vector, IsColVector ? start : 0, IsColVector ? 0 : start)\n    {\n      EIGEN_STATIC_ASSERT_VECTOR_ONLY(VectorBlock);\n    }\n};\n\n\n} // end namespace Eigen\n\n#endif // EIGEN_VECTORBLOCK_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/VectorwiseOp.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2006-2008 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_PARTIAL_REDUX_H\n#define EIGEN_PARTIAL_REDUX_H\n\nnamespace Eigen {\n\n/** \\class PartialReduxExpr\n  * \\ingroup Core_Module\n  *\n  * \\brief Generic expression of a partially reduxed matrix\n  *\n  * \\tparam MatrixType the type of the matrix we are applying the redux operation\n  * \\tparam MemberOp type of the member functor\n  * \\tparam Direction indicates the direction of the redux (#Vertical or #Horizontal)\n  *\n  * This class represents an expression of a partial redux operator of a matrix.\n  * It is the return type of some VectorwiseOp functions,\n  * and most of the time this is the only way it is used.\n  *\n  * \\sa class VectorwiseOp\n  */\n\ntemplate< typename MatrixType, typename MemberOp, int Direction>\nclass PartialReduxExpr;\n\nnamespace internal {\ntemplate<typename MatrixType, typename MemberOp, int Direction>\nstruct traits<PartialReduxExpr<MatrixType, MemberOp, Direction> >\n : traits<MatrixType>\n{\n  typedef typename MemberOp::result_type Scalar;\n  typedef typename traits<MatrixType>::StorageKind StorageKind;\n  typedef typename traits<MatrixType>::XprKind XprKind;\n  typedef typename MatrixType::Scalar InputScalar;\n  enum {\n    RowsAtCompileTime = Direction==Vertical   ? 1 : MatrixType::RowsAtCompileTime,\n    ColsAtCompileTime = Direction==Horizontal ? 1 : MatrixType::ColsAtCompileTime,\n    MaxRowsAtCompileTime = Direction==Vertical   ? 1 : MatrixType::MaxRowsAtCompileTime,\n    MaxColsAtCompileTime = Direction==Horizontal ? 1 : MatrixType::MaxColsAtCompileTime,\n    Flags = RowsAtCompileTime == 1 ? RowMajorBit : 0,\n    TraversalSize = Direction==Vertical ? MatrixType::RowsAtCompileTime :  MatrixType::ColsAtCompileTime\n  };\n};\n}\n\ntemplate< typename MatrixType, typename MemberOp, int Direction>\nclass PartialReduxExpr : public internal::dense_xpr_base< PartialReduxExpr<MatrixType, MemberOp, Direction> >::type,\n                         internal::no_assignment_operator\n{\n  public:\n\n    typedef typename internal::dense_xpr_base<PartialReduxExpr>::type Base;\n    EIGEN_DENSE_PUBLIC_INTERFACE(PartialReduxExpr)\n\n    EIGEN_DEVICE_FUNC\n    explicit PartialReduxExpr(const MatrixType& mat, const MemberOp& func = MemberOp())\n      : m_matrix(mat), m_functor(func) {}\n\n    EIGEN_DEVICE_FUNC\n    Index rows() const { return (Direction==Vertical   ? 1 : m_matrix.rows()); }\n    EIGEN_DEVICE_FUNC\n    Index cols() const { return (Direction==Horizontal ? 1 : m_matrix.cols()); }\n\n    EIGEN_DEVICE_FUNC\n    typename MatrixType::Nested nestedExpression() const { return m_matrix; }\n\n    EIGEN_DEVICE_FUNC\n    const MemberOp& functor() const { return m_functor; }\n\n  protected:\n    typename MatrixType::Nested m_matrix;\n    const MemberOp m_functor;\n};\n\n#define EIGEN_MEMBER_FUNCTOR(MEMBER,COST)                               \\\n  template <typename ResultType>                                        \\\n  struct member_##MEMBER {                                              \\\n    EIGEN_EMPTY_STRUCT_CTOR(member_##MEMBER)                            \\\n    typedef ResultType result_type;                                     \\\n    template<typename Scalar, int Size> struct Cost                     \\\n    { enum { value = COST }; };                                         \\\n    template<typename XprType>                                          \\\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE                               \\\n    ResultType operator()(const XprType& mat) const                     \\\n    { return mat.MEMBER(); } \\\n  }\n\nnamespace internal {\n\nEIGEN_MEMBER_FUNCTOR(squaredNorm, Size * NumTraits<Scalar>::MulCost + (Size-1)*NumTraits<Scalar>::AddCost);\nEIGEN_MEMBER_FUNCTOR(norm, (Size+5) * NumTraits<Scalar>::MulCost + (Size-1)*NumTraits<Scalar>::AddCost);\nEIGEN_MEMBER_FUNCTOR(stableNorm, (Size+5) * NumTraits<Scalar>::MulCost + (Size-1)*NumTraits<Scalar>::AddCost);\nEIGEN_MEMBER_FUNCTOR(blueNorm, (Size+5) * NumTraits<Scalar>::MulCost + (Size-1)*NumTraits<Scalar>::AddCost);\nEIGEN_MEMBER_FUNCTOR(hypotNorm, (Size-1) * functor_traits<scalar_hypot_op<Scalar> >::Cost );\nEIGEN_MEMBER_FUNCTOR(sum, (Size-1)*NumTraits<Scalar>::AddCost);\nEIGEN_MEMBER_FUNCTOR(mean, (Size-1)*NumTraits<Scalar>::AddCost + NumTraits<Scalar>::MulCost);\nEIGEN_MEMBER_FUNCTOR(minCoeff, (Size-1)*NumTraits<Scalar>::AddCost);\nEIGEN_MEMBER_FUNCTOR(maxCoeff, (Size-1)*NumTraits<Scalar>::AddCost);\nEIGEN_MEMBER_FUNCTOR(all, (Size-1)*NumTraits<Scalar>::AddCost);\nEIGEN_MEMBER_FUNCTOR(any, (Size-1)*NumTraits<Scalar>::AddCost);\nEIGEN_MEMBER_FUNCTOR(count, (Size-1)*NumTraits<Scalar>::AddCost);\nEIGEN_MEMBER_FUNCTOR(prod, (Size-1)*NumTraits<Scalar>::MulCost);\n\ntemplate <int p, typename ResultType>\nstruct member_lpnorm {\n  typedef ResultType result_type;\n  template<typename Scalar, int Size> struct Cost\n  { enum { value = (Size+5) * NumTraits<Scalar>::MulCost + (Size-1)*NumTraits<Scalar>::AddCost }; };\n  EIGEN_DEVICE_FUNC member_lpnorm() {}\n  template<typename XprType>\n  EIGEN_DEVICE_FUNC inline ResultType operator()(const XprType& mat) const\n  { return mat.template lpNorm<p>(); }\n};\n\ntemplate <typename BinaryOp, typename Scalar>\nstruct member_redux {\n  typedef typename result_of<\n                     BinaryOp(const Scalar&,const Scalar&)\n                   >::type  result_type;\n  template<typename _Scalar, int Size> struct Cost\n  { enum { value = (Size-1) * functor_traits<BinaryOp>::Cost }; };\n  EIGEN_DEVICE_FUNC explicit member_redux(const BinaryOp func) : m_functor(func) {}\n  template<typename Derived>\n  EIGEN_DEVICE_FUNC inline result_type operator()(const DenseBase<Derived>& mat) const\n  { return mat.redux(m_functor); }\n  const BinaryOp m_functor;\n};\n}\n\n/** \\class VectorwiseOp\n  * \\ingroup Core_Module\n  *\n  * \\brief Pseudo expression providing partial reduction operations\n  *\n  * \\tparam ExpressionType the type of the object on which to do partial reductions\n  * \\tparam Direction indicates the direction of the redux (#Vertical or #Horizontal)\n  *\n  * This class represents a pseudo expression with partial reduction features.\n  * It is the return type of DenseBase::colwise() and DenseBase::rowwise()\n  * and most of the time this is the only way it is used.\n  *\n  * Example: \\include MatrixBase_colwise.cpp\n  * Output: \\verbinclude MatrixBase_colwise.out\n  *\n  * \\sa DenseBase::colwise(), DenseBase::rowwise(), class PartialReduxExpr\n  */\ntemplate<typename ExpressionType, int Direction> class VectorwiseOp\n{\n  public:\n\n    typedef typename ExpressionType::Scalar Scalar;\n    typedef typename ExpressionType::RealScalar RealScalar;\n    typedef Eigen::Index Index; ///< \\deprecated since Eigen 3.3\n    typedef typename internal::ref_selector<ExpressionType>::non_const_type ExpressionTypeNested;\n    typedef typename internal::remove_all<ExpressionTypeNested>::type ExpressionTypeNestedCleaned;\n\n    template<template<typename _Scalar> class Functor,\n                      typename Scalar_=Scalar> struct ReturnType\n    {\n      typedef PartialReduxExpr<ExpressionType,\n                               Functor<Scalar_>,\n                               Direction\n                              > Type;\n    };\n\n    template<typename BinaryOp> struct ReduxReturnType\n    {\n      typedef PartialReduxExpr<ExpressionType,\n                               internal::member_redux<BinaryOp,Scalar>,\n                               Direction\n                              > Type;\n    };\n\n    enum {\n      isVertical   = (Direction==Vertical) ? 1 : 0,\n      isHorizontal = (Direction==Horizontal) ? 1 : 0\n    };\n\n  protected:\n\n    typedef typename internal::conditional<isVertical,\n                               typename ExpressionType::ColXpr,\n                               typename ExpressionType::RowXpr>::type SubVector;\n    /** \\internal\n      * \\returns the i-th subvector according to the \\c Direction */\n    EIGEN_DEVICE_FUNC\n    SubVector subVector(Index i)\n    {\n      return SubVector(m_matrix.derived(),i);\n    }\n\n    /** \\internal\n      * \\returns the number of subvectors in the direction \\c Direction */\n    EIGEN_DEVICE_FUNC\n    Index subVectors() const\n    { return isVertical?m_matrix.cols():m_matrix.rows(); }\n\n    template<typename OtherDerived> struct ExtendedType {\n      typedef Replicate<OtherDerived,\n                        isVertical   ? 1 : ExpressionType::RowsAtCompileTime,\n                        isHorizontal ? 1 : ExpressionType::ColsAtCompileTime> Type;\n    };\n\n    /** \\internal\n      * Replicates a vector to match the size of \\c *this */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    typename ExtendedType<OtherDerived>::Type\n    extendedTo(const DenseBase<OtherDerived>& other) const\n    {\n      EIGEN_STATIC_ASSERT(EIGEN_IMPLIES(isVertical, OtherDerived::MaxColsAtCompileTime==1),\n                          YOU_PASSED_A_ROW_VECTOR_BUT_A_COLUMN_VECTOR_WAS_EXPECTED)\n      EIGEN_STATIC_ASSERT(EIGEN_IMPLIES(isHorizontal, OtherDerived::MaxRowsAtCompileTime==1),\n                          YOU_PASSED_A_COLUMN_VECTOR_BUT_A_ROW_VECTOR_WAS_EXPECTED)\n      return typename ExtendedType<OtherDerived>::Type\n                      (other.derived(),\n                       isVertical   ? 1 : m_matrix.rows(),\n                       isHorizontal ? 1 : m_matrix.cols());\n    }\n\n    template<typename OtherDerived> struct OppositeExtendedType {\n      typedef Replicate<OtherDerived,\n                        isHorizontal ? 1 : ExpressionType::RowsAtCompileTime,\n                        isVertical   ? 1 : ExpressionType::ColsAtCompileTime> Type;\n    };\n\n    /** \\internal\n      * Replicates a vector in the opposite direction to match the size of \\c *this */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    typename OppositeExtendedType<OtherDerived>::Type\n    extendedToOpposite(const DenseBase<OtherDerived>& other) const\n    {\n      EIGEN_STATIC_ASSERT(EIGEN_IMPLIES(isHorizontal, OtherDerived::MaxColsAtCompileTime==1),\n                          YOU_PASSED_A_ROW_VECTOR_BUT_A_COLUMN_VECTOR_WAS_EXPECTED)\n      EIGEN_STATIC_ASSERT(EIGEN_IMPLIES(isVertical, OtherDerived::MaxRowsAtCompileTime==1),\n                          YOU_PASSED_A_COLUMN_VECTOR_BUT_A_ROW_VECTOR_WAS_EXPECTED)\n      return typename OppositeExtendedType<OtherDerived>::Type\n                      (other.derived(),\n                       isHorizontal  ? 1 : m_matrix.rows(),\n                       isVertical    ? 1 : m_matrix.cols());\n    }\n\n  public:\n    EIGEN_DEVICE_FUNC\n    explicit inline VectorwiseOp(ExpressionType& matrix) : m_matrix(matrix) {}\n\n    /** \\internal */\n    EIGEN_DEVICE_FUNC\n    inline const ExpressionType& _expression() const { return m_matrix; }\n\n    /** \\returns a row or column vector expression of \\c *this reduxed by \\a func\n      *\n      * The template parameter \\a BinaryOp is the type of the functor\n      * of the custom redux operator. Note that func must be an associative operator.\n      *\n      * \\sa class VectorwiseOp, DenseBase::colwise(), DenseBase::rowwise()\n      */\n    template<typename BinaryOp>\n    EIGEN_DEVICE_FUNC\n    const typename ReduxReturnType<BinaryOp>::Type\n    redux(const BinaryOp& func = BinaryOp()) const\n    { return typename ReduxReturnType<BinaryOp>::Type(_expression(), internal::member_redux<BinaryOp,Scalar>(func)); }\n\n    typedef typename ReturnType<internal::member_minCoeff>::Type MinCoeffReturnType;\n    typedef typename ReturnType<internal::member_maxCoeff>::Type MaxCoeffReturnType;\n    typedef typename ReturnType<internal::member_squaredNorm,RealScalar>::Type SquaredNormReturnType;\n    typedef typename ReturnType<internal::member_norm,RealScalar>::Type NormReturnType;\n    typedef typename ReturnType<internal::member_blueNorm,RealScalar>::Type BlueNormReturnType;\n    typedef typename ReturnType<internal::member_stableNorm,RealScalar>::Type StableNormReturnType;\n    typedef typename ReturnType<internal::member_hypotNorm,RealScalar>::Type HypotNormReturnType;\n    typedef typename ReturnType<internal::member_sum>::Type SumReturnType;\n    typedef typename ReturnType<internal::member_mean>::Type MeanReturnType;\n    typedef typename ReturnType<internal::member_all>::Type AllReturnType;\n    typedef typename ReturnType<internal::member_any>::Type AnyReturnType;\n    typedef PartialReduxExpr<ExpressionType, internal::member_count<Index>, Direction> CountReturnType;\n    typedef typename ReturnType<internal::member_prod>::Type ProdReturnType;\n    typedef Reverse<const ExpressionType, Direction> ConstReverseReturnType;\n    typedef Reverse<ExpressionType, Direction> ReverseReturnType;\n\n    template<int p> struct LpNormReturnType {\n      typedef PartialReduxExpr<ExpressionType, internal::member_lpnorm<p,RealScalar>,Direction> Type;\n    };\n\n    /** \\returns a row (or column) vector expression of the smallest coefficient\n      * of each column (or row) of the referenced expression.\n      *\n      * \\warning the result is undefined if \\c *this contains NaN.\n      *\n      * Example: \\include PartialRedux_minCoeff.cpp\n      * Output: \\verbinclude PartialRedux_minCoeff.out\n      *\n      * \\sa DenseBase::minCoeff() */\n    EIGEN_DEVICE_FUNC\n    const MinCoeffReturnType minCoeff() const\n    { return MinCoeffReturnType(_expression()); }\n\n    /** \\returns a row (or column) vector expression of the largest coefficient\n      * of each column (or row) of the referenced expression.\n      *\n      * \\warning the result is undefined if \\c *this contains NaN.\n      *\n      * Example: \\include PartialRedux_maxCoeff.cpp\n      * Output: \\verbinclude PartialRedux_maxCoeff.out\n      *\n      * \\sa DenseBase::maxCoeff() */\n    EIGEN_DEVICE_FUNC\n    const MaxCoeffReturnType maxCoeff() const\n    { return MaxCoeffReturnType(_expression()); }\n\n    /** \\returns a row (or column) vector expression of the squared norm\n      * of each column (or row) of the referenced expression.\n      * This is a vector with real entries, even if the original matrix has complex entries.\n      *\n      * Example: \\include PartialRedux_squaredNorm.cpp\n      * Output: \\verbinclude PartialRedux_squaredNorm.out\n      *\n      * \\sa DenseBase::squaredNorm() */\n    EIGEN_DEVICE_FUNC\n    const SquaredNormReturnType squaredNorm() const\n    { return SquaredNormReturnType(_expression()); }\n\n    /** \\returns a row (or column) vector expression of the norm\n      * of each column (or row) of the referenced expression.\n      * This is a vector with real entries, even if the original matrix has complex entries.\n      *\n      * Example: \\include PartialRedux_norm.cpp\n      * Output: \\verbinclude PartialRedux_norm.out\n      *\n      * \\sa DenseBase::norm() */\n    EIGEN_DEVICE_FUNC\n    const NormReturnType norm() const\n    { return NormReturnType(_expression()); }\n\n    /** \\returns a row (or column) vector expression of the norm\n      * of each column (or row) of the referenced expression.\n      * This is a vector with real entries, even if the original matrix has complex entries.\n      *\n      * Example: \\include PartialRedux_norm.cpp\n      * Output: \\verbinclude PartialRedux_norm.out\n      *\n      * \\sa DenseBase::norm() */\n    template<int p>\n    EIGEN_DEVICE_FUNC\n    const typename LpNormReturnType<p>::Type lpNorm() const\n    { return typename LpNormReturnType<p>::Type(_expression()); }\n\n\n    /** \\returns a row (or column) vector expression of the norm\n      * of each column (or row) of the referenced expression, using\n      * Blue's algorithm.\n      * This is a vector with real entries, even if the original matrix has complex entries.\n      *\n      * \\sa DenseBase::blueNorm() */\n    EIGEN_DEVICE_FUNC\n    const BlueNormReturnType blueNorm() const\n    { return BlueNormReturnType(_expression()); }\n\n\n    /** \\returns a row (or column) vector expression of the norm\n      * of each column (or row) of the referenced expression, avoiding\n      * underflow and overflow.\n      * This is a vector with real entries, even if the original matrix has complex entries.\n      *\n      * \\sa DenseBase::stableNorm() */\n    EIGEN_DEVICE_FUNC\n    const StableNormReturnType stableNorm() const\n    { return StableNormReturnType(_expression()); }\n\n\n    /** \\returns a row (or column) vector expression of the norm\n      * of each column (or row) of the referenced expression, avoiding\n      * underflow and overflow using a concatenation of hypot() calls.\n      * This is a vector with real entries, even if the original matrix has complex entries.\n      *\n      * \\sa DenseBase::hypotNorm() */\n    EIGEN_DEVICE_FUNC\n    const HypotNormReturnType hypotNorm() const\n    { return HypotNormReturnType(_expression()); }\n\n    /** \\returns a row (or column) vector expression of the sum\n      * of each column (or row) of the referenced expression.\n      *\n      * Example: \\include PartialRedux_sum.cpp\n      * Output: \\verbinclude PartialRedux_sum.out\n      *\n      * \\sa DenseBase::sum() */\n    EIGEN_DEVICE_FUNC\n    const SumReturnType sum() const\n    { return SumReturnType(_expression()); }\n\n    /** \\returns a row (or column) vector expression of the mean\n    * of each column (or row) of the referenced expression.\n    *\n    * \\sa DenseBase::mean() */\n    EIGEN_DEVICE_FUNC\n    const MeanReturnType mean() const\n    { return MeanReturnType(_expression()); }\n\n    /** \\returns a row (or column) vector expression representing\n      * whether \\b all coefficients of each respective column (or row) are \\c true.\n      * This expression can be assigned to a vector with entries of type \\c bool.\n      *\n      * \\sa DenseBase::all() */\n    EIGEN_DEVICE_FUNC\n    const AllReturnType all() const\n    { return AllReturnType(_expression()); }\n\n    /** \\returns a row (or column) vector expression representing\n      * whether \\b at \\b least one coefficient of each respective column (or row) is \\c true.\n      * This expression can be assigned to a vector with entries of type \\c bool.\n      *\n      * \\sa DenseBase::any() */\n    EIGEN_DEVICE_FUNC\n    const AnyReturnType any() const\n    { return AnyReturnType(_expression()); }\n\n    /** \\returns a row (or column) vector expression representing\n      * the number of \\c true coefficients of each respective column (or row).\n      * This expression can be assigned to a vector whose entries have the same type as is used to\n      * index entries of the original matrix; for dense matrices, this is \\c std::ptrdiff_t .\n      *\n      * Example: \\include PartialRedux_count.cpp\n      * Output: \\verbinclude PartialRedux_count.out\n      *\n      * \\sa DenseBase::count() */\n    EIGEN_DEVICE_FUNC\n    const CountReturnType count() const\n    { return CountReturnType(_expression()); }\n\n    /** \\returns a row (or column) vector expression of the product\n      * of each column (or row) of the referenced expression.\n      *\n      * Example: \\include PartialRedux_prod.cpp\n      * Output: \\verbinclude PartialRedux_prod.out\n      *\n      * \\sa DenseBase::prod() */\n    EIGEN_DEVICE_FUNC\n    const ProdReturnType prod() const\n    { return ProdReturnType(_expression()); }\n\n\n    /** \\returns a matrix expression\n      * where each column (or row) are reversed.\n      *\n      * Example: \\include Vectorwise_reverse.cpp\n      * Output: \\verbinclude Vectorwise_reverse.out\n      *\n      * \\sa DenseBase::reverse() */\n    EIGEN_DEVICE_FUNC\n    const ConstReverseReturnType reverse() const\n    { return ConstReverseReturnType( _expression() ); }\n\n    /** \\returns a writable matrix expression\n      * where each column (or row) are reversed.\n      *\n      * \\sa reverse() const */\n    EIGEN_DEVICE_FUNC\n    ReverseReturnType reverse()\n    { return ReverseReturnType( _expression() ); }\n\n    typedef Replicate<ExpressionType,(isVertical?Dynamic:1),(isHorizontal?Dynamic:1)> ReplicateReturnType;\n    EIGEN_DEVICE_FUNC\n    const ReplicateReturnType replicate(Index factor) const;\n\n    /**\n      * \\return an expression of the replication of each column (or row) of \\c *this\n      *\n      * Example: \\include DirectionWise_replicate.cpp\n      * Output: \\verbinclude DirectionWise_replicate.out\n      *\n      * \\sa VectorwiseOp::replicate(Index), DenseBase::replicate(), class Replicate\n      */\n    // NOTE implemented here because of sunstudio's compilation errors\n    // isVertical*Factor+isHorizontal instead of (isVertical?Factor:1) to handle CUDA bug with ternary operator\n    template<int Factor> const Replicate<ExpressionType,isVertical*Factor+isHorizontal,isHorizontal*Factor+isVertical>\n    EIGEN_DEVICE_FUNC\n    replicate(Index factor = Factor) const\n    {\n      return Replicate<ExpressionType,(isVertical?Factor:1),(isHorizontal?Factor:1)>\n          (_expression(),isVertical?factor:1,isHorizontal?factor:1);\n    }\n\n/////////// Artithmetic operators ///////////\n\n    /** Copies the vector \\a other to each subvector of \\c *this */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    ExpressionType& operator=(const DenseBase<OtherDerived>& other)\n    {\n      EIGEN_STATIC_ASSERT_VECTOR_ONLY(OtherDerived)\n      EIGEN_STATIC_ASSERT_SAME_XPR_KIND(ExpressionType, OtherDerived)\n      //eigen_assert((m_matrix.isNull()) == (other.isNull())); FIXME\n      return const_cast<ExpressionType&>(m_matrix = extendedTo(other.derived()));\n    }\n\n    /** Adds the vector \\a other to each subvector of \\c *this */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    ExpressionType& operator+=(const DenseBase<OtherDerived>& other)\n    {\n      EIGEN_STATIC_ASSERT_VECTOR_ONLY(OtherDerived)\n      EIGEN_STATIC_ASSERT_SAME_XPR_KIND(ExpressionType, OtherDerived)\n      return const_cast<ExpressionType&>(m_matrix += extendedTo(other.derived()));\n    }\n\n    /** Substracts the vector \\a other to each subvector of \\c *this */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    ExpressionType& operator-=(const DenseBase<OtherDerived>& other)\n    {\n      EIGEN_STATIC_ASSERT_VECTOR_ONLY(OtherDerived)\n      EIGEN_STATIC_ASSERT_SAME_XPR_KIND(ExpressionType, OtherDerived)\n      return const_cast<ExpressionType&>(m_matrix -= extendedTo(other.derived()));\n    }\n\n    /** Multiples each subvector of \\c *this by the vector \\a other */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    ExpressionType& operator*=(const DenseBase<OtherDerived>& other)\n    {\n      EIGEN_STATIC_ASSERT_VECTOR_ONLY(OtherDerived)\n      EIGEN_STATIC_ASSERT_ARRAYXPR(ExpressionType)\n      EIGEN_STATIC_ASSERT_SAME_XPR_KIND(ExpressionType, OtherDerived)\n      m_matrix *= extendedTo(other.derived());\n      return const_cast<ExpressionType&>(m_matrix);\n    }\n\n    /** Divides each subvector of \\c *this by the vector \\a other */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    ExpressionType& operator/=(const DenseBase<OtherDerived>& other)\n    {\n      EIGEN_STATIC_ASSERT_VECTOR_ONLY(OtherDerived)\n      EIGEN_STATIC_ASSERT_ARRAYXPR(ExpressionType)\n      EIGEN_STATIC_ASSERT_SAME_XPR_KIND(ExpressionType, OtherDerived)\n      m_matrix /= extendedTo(other.derived());\n      return const_cast<ExpressionType&>(m_matrix);\n    }\n\n    /** Returns the expression of the sum of the vector \\a other to each subvector of \\c *this */\n    template<typename OtherDerived> EIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC\n    CwiseBinaryOp<internal::scalar_sum_op<Scalar,typename OtherDerived::Scalar>,\n                  const ExpressionTypeNestedCleaned,\n                  const typename ExtendedType<OtherDerived>::Type>\n    operator+(const DenseBase<OtherDerived>& other) const\n    {\n      EIGEN_STATIC_ASSERT_VECTOR_ONLY(OtherDerived)\n      EIGEN_STATIC_ASSERT_SAME_XPR_KIND(ExpressionType, OtherDerived)\n      return m_matrix + extendedTo(other.derived());\n    }\n\n    /** Returns the expression of the difference between each subvector of \\c *this and the vector \\a other */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    CwiseBinaryOp<internal::scalar_difference_op<Scalar,typename OtherDerived::Scalar>,\n                  const ExpressionTypeNestedCleaned,\n                  const typename ExtendedType<OtherDerived>::Type>\n    operator-(const DenseBase<OtherDerived>& other) const\n    {\n      EIGEN_STATIC_ASSERT_VECTOR_ONLY(OtherDerived)\n      EIGEN_STATIC_ASSERT_SAME_XPR_KIND(ExpressionType, OtherDerived)\n      return m_matrix - extendedTo(other.derived());\n    }\n\n    /** Returns the expression where each subvector is the product of the vector \\a other\n      * by the corresponding subvector of \\c *this */\n    template<typename OtherDerived> EIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC\n    CwiseBinaryOp<internal::scalar_product_op<Scalar>,\n                  const ExpressionTypeNestedCleaned,\n                  const typename ExtendedType<OtherDerived>::Type>\n    EIGEN_DEVICE_FUNC\n    operator*(const DenseBase<OtherDerived>& other) const\n    {\n      EIGEN_STATIC_ASSERT_VECTOR_ONLY(OtherDerived)\n      EIGEN_STATIC_ASSERT_ARRAYXPR(ExpressionType)\n      EIGEN_STATIC_ASSERT_SAME_XPR_KIND(ExpressionType, OtherDerived)\n      return m_matrix * extendedTo(other.derived());\n    }\n\n    /** Returns the expression where each subvector is the quotient of the corresponding\n      * subvector of \\c *this by the vector \\a other */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    CwiseBinaryOp<internal::scalar_quotient_op<Scalar>,\n                  const ExpressionTypeNestedCleaned,\n                  const typename ExtendedType<OtherDerived>::Type>\n    operator/(const DenseBase<OtherDerived>& other) const\n    {\n      EIGEN_STATIC_ASSERT_VECTOR_ONLY(OtherDerived)\n      EIGEN_STATIC_ASSERT_ARRAYXPR(ExpressionType)\n      EIGEN_STATIC_ASSERT_SAME_XPR_KIND(ExpressionType, OtherDerived)\n      return m_matrix / extendedTo(other.derived());\n    }\n\n    /** \\returns an expression where each column (or row) of the referenced matrix are normalized.\n      * The referenced matrix is \\b not modified.\n      * \\sa MatrixBase::normalized(), normalize()\n      */\n    EIGEN_DEVICE_FUNC\n    CwiseBinaryOp<internal::scalar_quotient_op<Scalar>,\n                  const ExpressionTypeNestedCleaned,\n                  const typename OppositeExtendedType<typename ReturnType<internal::member_norm,RealScalar>::Type>::Type>\n    normalized() const { return m_matrix.cwiseQuotient(extendedToOpposite(this->norm())); }\n\n\n    /** Normalize in-place each row or columns of the referenced matrix.\n      * \\sa MatrixBase::normalize(), normalized()\n      */\n    EIGEN_DEVICE_FUNC void normalize() {\n      m_matrix = this->normalized();\n    }\n\n    EIGEN_DEVICE_FUNC inline void reverseInPlace();\n\n/////////// Geometry module ///////////\n\n    typedef Homogeneous<ExpressionType,Direction> HomogeneousReturnType;\n    EIGEN_DEVICE_FUNC\n    HomogeneousReturnType homogeneous() const;\n\n    typedef typename ExpressionType::PlainObject CrossReturnType;\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC\n    const CrossReturnType cross(const MatrixBase<OtherDerived>& other) const;\n\n    enum {\n      HNormalized_Size = Direction==Vertical ? internal::traits<ExpressionType>::RowsAtCompileTime\n                                             : internal::traits<ExpressionType>::ColsAtCompileTime,\n      HNormalized_SizeMinusOne = HNormalized_Size==Dynamic ? Dynamic : HNormalized_Size-1\n    };\n    typedef Block<const ExpressionType,\n                  Direction==Vertical   ? int(HNormalized_SizeMinusOne)\n                                        : int(internal::traits<ExpressionType>::RowsAtCompileTime),\n                  Direction==Horizontal ? int(HNormalized_SizeMinusOne)\n                                        : int(internal::traits<ExpressionType>::ColsAtCompileTime)>\n            HNormalized_Block;\n    typedef Block<const ExpressionType,\n                  Direction==Vertical   ? 1 : int(internal::traits<ExpressionType>::RowsAtCompileTime),\n                  Direction==Horizontal ? 1 : int(internal::traits<ExpressionType>::ColsAtCompileTime)>\n            HNormalized_Factors;\n    typedef CwiseBinaryOp<internal::scalar_quotient_op<typename internal::traits<ExpressionType>::Scalar>,\n                const HNormalized_Block,\n                const Replicate<HNormalized_Factors,\n                  Direction==Vertical   ? HNormalized_SizeMinusOne : 1,\n                  Direction==Horizontal ? HNormalized_SizeMinusOne : 1> >\n            HNormalizedReturnType;\n\n    EIGEN_DEVICE_FUNC\n    const HNormalizedReturnType hnormalized() const;\n\n  protected:\n    ExpressionTypeNested m_matrix;\n};\n\n//const colwise moved to DenseBase.h due to CUDA compiler bug\n\n\n/** \\returns a writable VectorwiseOp wrapper of *this providing additional partial reduction operations\n  *\n  * \\sa rowwise(), class VectorwiseOp, \\ref TutorialReductionsVisitorsBroadcasting\n  */\ntemplate<typename Derived>\ninline typename DenseBase<Derived>::ColwiseReturnType\nDenseBase<Derived>::colwise()\n{\n  return ColwiseReturnType(derived());\n}\n\n//const rowwise moved to DenseBase.h due to CUDA compiler bug\n\n\n/** \\returns a writable VectorwiseOp wrapper of *this providing additional partial reduction operations\n  *\n  * \\sa colwise(), class VectorwiseOp, \\ref TutorialReductionsVisitorsBroadcasting\n  */\ntemplate<typename Derived>\ninline typename DenseBase<Derived>::RowwiseReturnType\nDenseBase<Derived>::rowwise()\n{\n  return RowwiseReturnType(derived());\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_PARTIAL_REDUX_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/Visitor.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_VISITOR_H\n#define EIGEN_VISITOR_H\n\nnamespace Eigen { \n\nnamespace internal {\n\ntemplate<typename Visitor, typename Derived, int UnrollCount>\nstruct visitor_impl\n{\n  enum {\n    col = (UnrollCount-1) / Derived::RowsAtCompileTime,\n    row = (UnrollCount-1) % Derived::RowsAtCompileTime\n  };\n\n  EIGEN_DEVICE_FUNC\n  static inline void run(const Derived &mat, Visitor& visitor)\n  {\n    visitor_impl<Visitor, Derived, UnrollCount-1>::run(mat, visitor);\n    visitor(mat.coeff(row, col), row, col);\n  }\n};\n\ntemplate<typename Visitor, typename Derived>\nstruct visitor_impl<Visitor, Derived, 1>\n{\n  EIGEN_DEVICE_FUNC\n  static inline void run(const Derived &mat, Visitor& visitor)\n  {\n    return visitor.init(mat.coeff(0, 0), 0, 0);\n  }\n};\n\ntemplate<typename Visitor, typename Derived>\nstruct visitor_impl<Visitor, Derived, Dynamic>\n{\n  EIGEN_DEVICE_FUNC\n  static inline void run(const Derived& mat, Visitor& visitor)\n  {\n    visitor.init(mat.coeff(0,0), 0, 0);\n    for(Index i = 1; i < mat.rows(); ++i)\n      visitor(mat.coeff(i, 0), i, 0);\n    for(Index j = 1; j < mat.cols(); ++j)\n      for(Index i = 0; i < mat.rows(); ++i)\n        visitor(mat.coeff(i, j), i, j);\n  }\n};\n\n// evaluator adaptor\ntemplate<typename XprType>\nclass visitor_evaluator\n{\npublic:\n  EIGEN_DEVICE_FUNC\n  explicit visitor_evaluator(const XprType &xpr) : m_evaluator(xpr), m_xpr(xpr) {}\n  \n  typedef typename XprType::Scalar Scalar;\n  typedef typename XprType::CoeffReturnType CoeffReturnType;\n  \n  enum {\n    RowsAtCompileTime = XprType::RowsAtCompileTime,\n    CoeffReadCost = internal::evaluator<XprType>::CoeffReadCost\n  };\n  \n  EIGEN_DEVICE_FUNC Index rows() const { return m_xpr.rows(); }\n  EIGEN_DEVICE_FUNC Index cols() const { return m_xpr.cols(); }\n  EIGEN_DEVICE_FUNC Index size() const { return m_xpr.size(); }\n\n  EIGEN_DEVICE_FUNC CoeffReturnType coeff(Index row, Index col) const\n  { return m_evaluator.coeff(row, col); }\n  \nprotected:\n  internal::evaluator<XprType> m_evaluator;\n  const XprType &m_xpr;\n};\n} // end namespace internal\n\n/** Applies the visitor \\a visitor to the whole coefficients of the matrix or vector.\n  *\n  * The template parameter \\a Visitor is the type of the visitor and provides the following interface:\n  * \\code\n  * struct MyVisitor {\n  *   // called for the first coefficient\n  *   void init(const Scalar& value, Index i, Index j);\n  *   // called for all other coefficients\n  *   void operator() (const Scalar& value, Index i, Index j);\n  * };\n  * \\endcode\n  *\n  * \\note compared to one or two \\em for \\em loops, visitors offer automatic\n  * unrolling for small fixed size matrix.\n  *\n  * \\sa minCoeff(Index*,Index*), maxCoeff(Index*,Index*), DenseBase::redux()\n  */\ntemplate<typename Derived>\ntemplate<typename Visitor>\nEIGEN_DEVICE_FUNC\nvoid DenseBase<Derived>::visit(Visitor& visitor) const\n{\n  typedef typename internal::visitor_evaluator<Derived> ThisEvaluator;\n  ThisEvaluator thisEval(derived());\n  \n  enum {\n    unroll =  SizeAtCompileTime != Dynamic\n           && SizeAtCompileTime * ThisEvaluator::CoeffReadCost + (SizeAtCompileTime-1) * internal::functor_traits<Visitor>::Cost <= EIGEN_UNROLLING_LIMIT\n  };\n  return internal::visitor_impl<Visitor, ThisEvaluator, unroll ? int(SizeAtCompileTime) : Dynamic>::run(thisEval, visitor);\n}\n\nnamespace internal {\n\n/** \\internal\n  * \\brief Base class to implement min and max visitors\n  */\ntemplate <typename Derived>\nstruct coeff_visitor\n{\n  typedef typename Derived::Scalar Scalar;\n  Index row, col;\n  Scalar res;\n  EIGEN_DEVICE_FUNC\n  inline void init(const Scalar& value, Index i, Index j)\n  {\n    res = value;\n    row = i;\n    col = j;\n  }\n};\n\n/** \\internal\n  * \\brief Visitor computing the min coefficient with its value and coordinates\n  *\n  * \\sa DenseBase::minCoeff(Index*, Index*)\n  */\ntemplate <typename Derived>\nstruct min_coeff_visitor : coeff_visitor<Derived>\n{\n  typedef typename Derived::Scalar Scalar;\n  EIGEN_DEVICE_FUNC\n  void operator() (const Scalar& value, Index i, Index j)\n  {\n    if(value < this->res)\n    {\n      this->res = value;\n      this->row = i;\n      this->col = j;\n    }\n  }\n};\n\ntemplate<typename Scalar>\nstruct functor_traits<min_coeff_visitor<Scalar> > {\n  enum {\n    Cost = NumTraits<Scalar>::AddCost\n  };\n};\n\n/** \\internal\n  * \\brief Visitor computing the max coefficient with its value and coordinates\n  *\n  * \\sa DenseBase::maxCoeff(Index*, Index*)\n  */\ntemplate <typename Derived>\nstruct max_coeff_visitor : coeff_visitor<Derived>\n{\n  typedef typename Derived::Scalar Scalar; \n  EIGEN_DEVICE_FUNC\n  void operator() (const Scalar& value, Index i, Index j)\n  {\n    if(value > this->res)\n    {\n      this->res = value;\n      this->row = i;\n      this->col = j;\n    }\n  }\n};\n\ntemplate<typename Scalar>\nstruct functor_traits<max_coeff_visitor<Scalar> > {\n  enum {\n    Cost = NumTraits<Scalar>::AddCost\n  };\n};\n\n} // end namespace internal\n\n/** \\returns the minimum of all coefficients of *this and puts in *row and *col its location.\n  * \\warning the result is undefined if \\c *this contains NaN.\n  *\n  * \\sa DenseBase::minCoeff(Index*), DenseBase::maxCoeff(Index*,Index*), DenseBase::visit(), DenseBase::minCoeff()\n  */\ntemplate<typename Derived>\ntemplate<typename IndexType>\nEIGEN_DEVICE_FUNC\ntypename internal::traits<Derived>::Scalar\nDenseBase<Derived>::minCoeff(IndexType* rowId, IndexType* colId) const\n{\n  internal::min_coeff_visitor<Derived> minVisitor;\n  this->visit(minVisitor);\n  *rowId = minVisitor.row;\n  if (colId) *colId = minVisitor.col;\n  return minVisitor.res;\n}\n\n/** \\returns the minimum of all coefficients of *this and puts in *index its location.\n  * \\warning the result is undefined if \\c *this contains NaN. \n  *\n  * \\sa DenseBase::minCoeff(IndexType*,IndexType*), DenseBase::maxCoeff(IndexType*,IndexType*), DenseBase::visit(), DenseBase::minCoeff()\n  */\ntemplate<typename Derived>\ntemplate<typename IndexType>\nEIGEN_DEVICE_FUNC\ntypename internal::traits<Derived>::Scalar\nDenseBase<Derived>::minCoeff(IndexType* index) const\n{\n  EIGEN_STATIC_ASSERT_VECTOR_ONLY(Derived)\n  internal::min_coeff_visitor<Derived> minVisitor;\n  this->visit(minVisitor);\n  *index = IndexType((RowsAtCompileTime==1) ? minVisitor.col : minVisitor.row);\n  return minVisitor.res;\n}\n\n/** \\returns the maximum of all coefficients of *this and puts in *row and *col its location.\n  * \\warning the result is undefined if \\c *this contains NaN. \n  *\n  * \\sa DenseBase::minCoeff(IndexType*,IndexType*), DenseBase::visit(), DenseBase::maxCoeff()\n  */\ntemplate<typename Derived>\ntemplate<typename IndexType>\nEIGEN_DEVICE_FUNC\ntypename internal::traits<Derived>::Scalar\nDenseBase<Derived>::maxCoeff(IndexType* rowPtr, IndexType* colPtr) const\n{\n  internal::max_coeff_visitor<Derived> maxVisitor;\n  this->visit(maxVisitor);\n  *rowPtr = maxVisitor.row;\n  if (colPtr) *colPtr = maxVisitor.col;\n  return maxVisitor.res;\n}\n\n/** \\returns the maximum of all coefficients of *this and puts in *index its location.\n  * \\warning the result is undefined if \\c *this contains NaN.\n  *\n  * \\sa DenseBase::maxCoeff(IndexType*,IndexType*), DenseBase::minCoeff(IndexType*,IndexType*), DenseBase::visitor(), DenseBase::maxCoeff()\n  */\ntemplate<typename Derived>\ntemplate<typename IndexType>\nEIGEN_DEVICE_FUNC\ntypename internal::traits<Derived>::Scalar\nDenseBase<Derived>::maxCoeff(IndexType* index) const\n{\n  EIGEN_STATIC_ASSERT_VECTOR_ONLY(Derived)\n  internal::max_coeff_visitor<Derived> maxVisitor;\n  this->visit(maxVisitor);\n  *index = (RowsAtCompileTime==1) ? maxVisitor.col : maxVisitor.row;\n  return maxVisitor.res;\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_VISITOR_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/arch/AVX/Complex.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2014 Benoit Steiner (benoit.steiner.goog@gmail.com)\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_COMPLEX_AVX_H\n#define EIGEN_COMPLEX_AVX_H\n\nnamespace Eigen {\n\nnamespace internal {\n\n//---------- float ----------\nstruct Packet4cf\n{\n  EIGEN_STRONG_INLINE Packet4cf() {}\n  EIGEN_STRONG_INLINE explicit Packet4cf(const __m256& a) : v(a) {}\n  __m256  v;\n};\n\ntemplate<> struct packet_traits<std::complex<float> >  : default_packet_traits\n{\n  typedef Packet4cf type;\n  typedef Packet2cf half;\n  enum {\n    Vectorizable = 1,\n    AlignedOnScalar = 1,\n    size = 4,\n    HasHalfPacket = 1,\n\n    HasAdd    = 1,\n    HasSub    = 1,\n    HasMul    = 1,\n    HasDiv    = 1,\n    HasNegate = 1,\n    HasAbs    = 0,\n    HasAbs2   = 0,\n    HasMin    = 0,\n    HasMax    = 0,\n    HasSetLinear = 0\n  };\n};\n\ntemplate<> struct unpacket_traits<Packet4cf> { typedef std::complex<float> type; enum {size=4, alignment=Aligned32}; typedef Packet2cf half; };\n\ntemplate<> EIGEN_STRONG_INLINE Packet4cf padd<Packet4cf>(const Packet4cf& a, const Packet4cf& b) { return Packet4cf(_mm256_add_ps(a.v,b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet4cf psub<Packet4cf>(const Packet4cf& a, const Packet4cf& b) { return Packet4cf(_mm256_sub_ps(a.v,b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet4cf pnegate(const Packet4cf& a)\n{\n  return Packet4cf(pnegate(a.v));\n}\ntemplate<> EIGEN_STRONG_INLINE Packet4cf pconj(const Packet4cf& a)\n{\n  const __m256 mask = _mm256_castsi256_ps(_mm256_setr_epi32(0x00000000,0x80000000,0x00000000,0x80000000,0x00000000,0x80000000,0x00000000,0x80000000));\n  return Packet4cf(_mm256_xor_ps(a.v,mask));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4cf pmul<Packet4cf>(const Packet4cf& a, const Packet4cf& b)\n{\n  __m256 tmp1 = _mm256_mul_ps(_mm256_moveldup_ps(a.v), b.v);\n  __m256 tmp2 = _mm256_mul_ps(_mm256_movehdup_ps(a.v), _mm256_permute_ps(b.v, _MM_SHUFFLE(2,3,0,1)));\n  __m256 result = _mm256_addsub_ps(tmp1, tmp2);\n  return Packet4cf(result);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4cf pand   <Packet4cf>(const Packet4cf& a, const Packet4cf& b) { return Packet4cf(_mm256_and_ps(a.v,b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet4cf por    <Packet4cf>(const Packet4cf& a, const Packet4cf& b) { return Packet4cf(_mm256_or_ps(a.v,b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet4cf pxor   <Packet4cf>(const Packet4cf& a, const Packet4cf& b) { return Packet4cf(_mm256_xor_ps(a.v,b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet4cf pandnot<Packet4cf>(const Packet4cf& a, const Packet4cf& b) { return Packet4cf(_mm256_andnot_ps(a.v,b.v)); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4cf pload <Packet4cf>(const std::complex<float>* from) { EIGEN_DEBUG_ALIGNED_LOAD return Packet4cf(pload<Packet8f>(&numext::real_ref(*from))); }\ntemplate<> EIGEN_STRONG_INLINE Packet4cf ploadu<Packet4cf>(const std::complex<float>* from) { EIGEN_DEBUG_UNALIGNED_LOAD return Packet4cf(ploadu<Packet8f>(&numext::real_ref(*from))); }\n\n\ntemplate<> EIGEN_STRONG_INLINE Packet4cf pset1<Packet4cf>(const std::complex<float>& from)\n{\n  return Packet4cf(_mm256_castpd_ps(_mm256_broadcast_sd((const double*)(const void*)&from)));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4cf ploaddup<Packet4cf>(const std::complex<float>* from)\n{\n  // FIXME The following might be optimized using _mm256_movedup_pd\n  Packet2cf a = ploaddup<Packet2cf>(from);\n  Packet2cf b = ploaddup<Packet2cf>(from+1);\n  return  Packet4cf(_mm256_insertf128_ps(_mm256_castps128_ps256(a.v), b.v, 1));\n}\n\ntemplate<> EIGEN_STRONG_INLINE void pstore <std::complex<float> >(std::complex<float>* to, const Packet4cf& from) { EIGEN_DEBUG_ALIGNED_STORE pstore(&numext::real_ref(*to), from.v); }\ntemplate<> EIGEN_STRONG_INLINE void pstoreu<std::complex<float> >(std::complex<float>* to, const Packet4cf& from) { EIGEN_DEBUG_UNALIGNED_STORE pstoreu(&numext::real_ref(*to), from.v); }\n\ntemplate<> EIGEN_DEVICE_FUNC inline Packet4cf pgather<std::complex<float>, Packet4cf>(const std::complex<float>* from, Index stride)\n{\n  return Packet4cf(_mm256_set_ps(std::imag(from[3*stride]), std::real(from[3*stride]),\n                                 std::imag(from[2*stride]), std::real(from[2*stride]),\n                                 std::imag(from[1*stride]), std::real(from[1*stride]),\n                                 std::imag(from[0*stride]), std::real(from[0*stride])));\n}\n\ntemplate<> EIGEN_DEVICE_FUNC inline void pscatter<std::complex<float>, Packet4cf>(std::complex<float>* to, const Packet4cf& from, Index stride)\n{\n  __m128 low = _mm256_extractf128_ps(from.v, 0);\n  to[stride*0] = std::complex<float>(_mm_cvtss_f32(_mm_shuffle_ps(low, low, 0)),\n                                     _mm_cvtss_f32(_mm_shuffle_ps(low, low, 1)));\n  to[stride*1] = std::complex<float>(_mm_cvtss_f32(_mm_shuffle_ps(low, low, 2)),\n                                     _mm_cvtss_f32(_mm_shuffle_ps(low, low, 3)));\n\n  __m128 high = _mm256_extractf128_ps(from.v, 1);\n  to[stride*2] = std::complex<float>(_mm_cvtss_f32(_mm_shuffle_ps(high, high, 0)),\n                                     _mm_cvtss_f32(_mm_shuffle_ps(high, high, 1)));\n  to[stride*3] = std::complex<float>(_mm_cvtss_f32(_mm_shuffle_ps(high, high, 2)),\n                                     _mm_cvtss_f32(_mm_shuffle_ps(high, high, 3)));\n\n}\n\ntemplate<> EIGEN_STRONG_INLINE std::complex<float>  pfirst<Packet4cf>(const Packet4cf& a)\n{\n  return pfirst(Packet2cf(_mm256_castps256_ps128(a.v)));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4cf preverse(const Packet4cf& a) {\n  __m128 low  = _mm256_extractf128_ps(a.v, 0);\n  __m128 high = _mm256_extractf128_ps(a.v, 1);\n  __m128d lowd  = _mm_castps_pd(low);\n  __m128d highd = _mm_castps_pd(high);\n  low  = _mm_castpd_ps(_mm_shuffle_pd(lowd,lowd,0x1));\n  high = _mm_castpd_ps(_mm_shuffle_pd(highd,highd,0x1));\n  __m256 result = _mm256_setzero_ps();\n  result = _mm256_insertf128_ps(result, low, 1);\n  result = _mm256_insertf128_ps(result, high, 0);\n  return Packet4cf(result);\n}\n\ntemplate<> EIGEN_STRONG_INLINE std::complex<float> predux<Packet4cf>(const Packet4cf& a)\n{\n  return predux(padd(Packet2cf(_mm256_extractf128_ps(a.v,0)),\n                     Packet2cf(_mm256_extractf128_ps(a.v,1))));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4cf preduxp<Packet4cf>(const Packet4cf* vecs)\n{\n  Packet8f t0 = _mm256_shuffle_ps(vecs[0].v, vecs[0].v, _MM_SHUFFLE(3, 1, 2 ,0));\n  Packet8f t1 = _mm256_shuffle_ps(vecs[1].v, vecs[1].v, _MM_SHUFFLE(3, 1, 2 ,0));\n  t0 = _mm256_hadd_ps(t0,t1);\n  Packet8f t2 = _mm256_shuffle_ps(vecs[2].v, vecs[2].v, _MM_SHUFFLE(3, 1, 2 ,0));\n  Packet8f t3 = _mm256_shuffle_ps(vecs[3].v, vecs[3].v, _MM_SHUFFLE(3, 1, 2 ,0));\n  t2 = _mm256_hadd_ps(t2,t3);\n  \n  t1 = _mm256_permute2f128_ps(t0,t2, 0 + (2<<4));\n  t3 = _mm256_permute2f128_ps(t0,t2, 1 + (3<<4));\n\n  return Packet4cf(_mm256_add_ps(t1,t3));\n}\n\ntemplate<> EIGEN_STRONG_INLINE std::complex<float> predux_mul<Packet4cf>(const Packet4cf& a)\n{\n  return predux_mul(pmul(Packet2cf(_mm256_extractf128_ps(a.v, 0)),\n                         Packet2cf(_mm256_extractf128_ps(a.v, 1))));\n}\n\ntemplate<int Offset>\nstruct palign_impl<Offset,Packet4cf>\n{\n  static EIGEN_STRONG_INLINE void run(Packet4cf& first, const Packet4cf& second)\n  {\n    if (Offset==0) return;\n    palign_impl<Offset*2,Packet8f>::run(first.v, second.v);\n  }\n};\n\ntemplate<> struct conj_helper<Packet4cf, Packet4cf, false,true>\n{\n  EIGEN_STRONG_INLINE Packet4cf pmadd(const Packet4cf& x, const Packet4cf& y, const Packet4cf& c) const\n  { return padd(pmul(x,y),c); }\n\n  EIGEN_STRONG_INLINE Packet4cf pmul(const Packet4cf& a, const Packet4cf& b) const\n  {\n    return internal::pmul(a, pconj(b));\n  }\n};\n\ntemplate<> struct conj_helper<Packet4cf, Packet4cf, true,false>\n{\n  EIGEN_STRONG_INLINE Packet4cf pmadd(const Packet4cf& x, const Packet4cf& y, const Packet4cf& c) const\n  { return padd(pmul(x,y),c); }\n\n  EIGEN_STRONG_INLINE Packet4cf pmul(const Packet4cf& a, const Packet4cf& b) const\n  {\n    return internal::pmul(pconj(a), b);\n  }\n};\n\ntemplate<> struct conj_helper<Packet4cf, Packet4cf, true,true>\n{\n  EIGEN_STRONG_INLINE Packet4cf pmadd(const Packet4cf& x, const Packet4cf& y, const Packet4cf& c) const\n  { return padd(pmul(x,y),c); }\n\n  EIGEN_STRONG_INLINE Packet4cf pmul(const Packet4cf& a, const Packet4cf& b) const\n  {\n    return pconj(internal::pmul(a, b));\n  }\n};\n\ntemplate<> struct conj_helper<Packet8f, Packet4cf, false,false>\n{\n  EIGEN_STRONG_INLINE Packet4cf pmadd(const Packet8f& x, const Packet4cf& y, const Packet4cf& c) const\n  { return padd(c, pmul(x,y)); }\n\n  EIGEN_STRONG_INLINE Packet4cf pmul(const Packet8f& x, const Packet4cf& y) const\n  { return Packet4cf(Eigen::internal::pmul(x, y.v)); }\n};\n\ntemplate<> struct conj_helper<Packet4cf, Packet8f, false,false>\n{\n  EIGEN_STRONG_INLINE Packet4cf pmadd(const Packet4cf& x, const Packet8f& y, const Packet4cf& c) const\n  { return padd(c, pmul(x,y)); }\n\n  EIGEN_STRONG_INLINE Packet4cf pmul(const Packet4cf& x, const Packet8f& y) const\n  { return Packet4cf(Eigen::internal::pmul(x.v, y)); }\n};\n\ntemplate<> EIGEN_STRONG_INLINE Packet4cf pdiv<Packet4cf>(const Packet4cf& a, const Packet4cf& b)\n{\n  Packet4cf num = pmul(a, pconj(b));\n  __m256 tmp = _mm256_mul_ps(b.v, b.v);\n  __m256 tmp2    = _mm256_shuffle_ps(tmp,tmp,0xB1);\n  __m256 denom = _mm256_add_ps(tmp, tmp2);\n  return Packet4cf(_mm256_div_ps(num.v, denom));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4cf pcplxflip<Packet4cf>(const Packet4cf& x)\n{\n  return Packet4cf(_mm256_shuffle_ps(x.v, x.v, _MM_SHUFFLE(2, 3, 0 ,1)));\n}\n\n//---------- double ----------\nstruct Packet2cd\n{\n  EIGEN_STRONG_INLINE Packet2cd() {}\n  EIGEN_STRONG_INLINE explicit Packet2cd(const __m256d& a) : v(a) {}\n  __m256d  v;\n};\n\ntemplate<> struct packet_traits<std::complex<double> >  : default_packet_traits\n{\n  typedef Packet2cd type;\n  typedef Packet1cd half;\n  enum {\n    Vectorizable = 1,\n    AlignedOnScalar = 0,\n    size = 2,\n    HasHalfPacket = 1,\n\n    HasAdd    = 1,\n    HasSub    = 1,\n    HasMul    = 1,\n    HasDiv    = 1,\n    HasNegate = 1,\n    HasAbs    = 0,\n    HasAbs2   = 0,\n    HasMin    = 0,\n    HasMax    = 0,\n    HasSetLinear = 0\n  };\n};\n\ntemplate<> struct unpacket_traits<Packet2cd> { typedef std::complex<double> type; enum {size=2, alignment=Aligned32}; typedef Packet1cd half; };\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cd padd<Packet2cd>(const Packet2cd& a, const Packet2cd& b) { return Packet2cd(_mm256_add_pd(a.v,b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet2cd psub<Packet2cd>(const Packet2cd& a, const Packet2cd& b) { return Packet2cd(_mm256_sub_pd(a.v,b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet2cd pnegate(const Packet2cd& a) { return Packet2cd(pnegate(a.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet2cd pconj(const Packet2cd& a)\n{\n  const __m256d mask = _mm256_castsi256_pd(_mm256_set_epi32(0x80000000,0x0,0x0,0x0,0x80000000,0x0,0x0,0x0));\n  return Packet2cd(_mm256_xor_pd(a.v,mask));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cd pmul<Packet2cd>(const Packet2cd& a, const Packet2cd& b)\n{\n  __m256d tmp1 = _mm256_shuffle_pd(a.v,a.v,0x0);\n  __m256d even = _mm256_mul_pd(tmp1, b.v);\n  __m256d tmp2 = _mm256_shuffle_pd(a.v,a.v,0xF);\n  __m256d tmp3 = _mm256_shuffle_pd(b.v,b.v,0x5);\n  __m256d odd  = _mm256_mul_pd(tmp2, tmp3);\n  return Packet2cd(_mm256_addsub_pd(even, odd));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cd pand   <Packet2cd>(const Packet2cd& a, const Packet2cd& b) { return Packet2cd(_mm256_and_pd(a.v,b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet2cd por    <Packet2cd>(const Packet2cd& a, const Packet2cd& b) { return Packet2cd(_mm256_or_pd(a.v,b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet2cd pxor   <Packet2cd>(const Packet2cd& a, const Packet2cd& b) { return Packet2cd(_mm256_xor_pd(a.v,b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet2cd pandnot<Packet2cd>(const Packet2cd& a, const Packet2cd& b) { return Packet2cd(_mm256_andnot_pd(a.v,b.v)); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cd pload <Packet2cd>(const std::complex<double>* from)\n{ EIGEN_DEBUG_ALIGNED_LOAD return Packet2cd(pload<Packet4d>((const double*)from)); }\ntemplate<> EIGEN_STRONG_INLINE Packet2cd ploadu<Packet2cd>(const std::complex<double>* from)\n{ EIGEN_DEBUG_UNALIGNED_LOAD return Packet2cd(ploadu<Packet4d>((const double*)from)); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cd pset1<Packet2cd>(const std::complex<double>& from)\n{\n  // in case casting to a __m128d* is really not safe, then we can still fallback to this version: (much slower though)\n//   return Packet2cd(_mm256_loadu2_m128d((const double*)&from,(const double*)&from));\n    return Packet2cd(_mm256_broadcast_pd((const __m128d*)(const void*)&from));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cd ploaddup<Packet2cd>(const std::complex<double>* from) { return pset1<Packet2cd>(*from); }\n\ntemplate<> EIGEN_STRONG_INLINE void pstore <std::complex<double> >(std::complex<double> *   to, const Packet2cd& from) { EIGEN_DEBUG_ALIGNED_STORE pstore((double*)to, from.v); }\ntemplate<> EIGEN_STRONG_INLINE void pstoreu<std::complex<double> >(std::complex<double> *   to, const Packet2cd& from) { EIGEN_DEBUG_UNALIGNED_STORE pstoreu((double*)to, from.v); }\n\ntemplate<> EIGEN_DEVICE_FUNC inline Packet2cd pgather<std::complex<double>, Packet2cd>(const std::complex<double>* from, Index stride)\n{\n  return Packet2cd(_mm256_set_pd(std::imag(from[1*stride]), std::real(from[1*stride]),\n\t\t\t\t std::imag(from[0*stride]), std::real(from[0*stride])));\n}\n\ntemplate<> EIGEN_DEVICE_FUNC inline void pscatter<std::complex<double>, Packet2cd>(std::complex<double>* to, const Packet2cd& from, Index stride)\n{\n  __m128d low = _mm256_extractf128_pd(from.v, 0);\n  to[stride*0] = std::complex<double>(_mm_cvtsd_f64(low), _mm_cvtsd_f64(_mm_shuffle_pd(low, low, 1)));\n  __m128d high = _mm256_extractf128_pd(from.v, 1);\n  to[stride*1] = std::complex<double>(_mm_cvtsd_f64(high), _mm_cvtsd_f64(_mm_shuffle_pd(high, high, 1)));\n}\n\ntemplate<> EIGEN_STRONG_INLINE std::complex<double> pfirst<Packet2cd>(const Packet2cd& a)\n{\n  __m128d low = _mm256_extractf128_pd(a.v, 0);\n  EIGEN_ALIGN16 double res[2];\n  _mm_store_pd(res, low);\n  return std::complex<double>(res[0],res[1]);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cd preverse(const Packet2cd& a) {\n  __m256d result = _mm256_permute2f128_pd(a.v, a.v, 1);\n  return Packet2cd(result);\n}\n\ntemplate<> EIGEN_STRONG_INLINE std::complex<double> predux<Packet2cd>(const Packet2cd& a)\n{\n  return predux(padd(Packet1cd(_mm256_extractf128_pd(a.v,0)),\n                     Packet1cd(_mm256_extractf128_pd(a.v,1))));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cd preduxp<Packet2cd>(const Packet2cd* vecs)\n{\n  Packet4d t0 = _mm256_permute2f128_pd(vecs[0].v,vecs[1].v, 0 + (2<<4));\n  Packet4d t1 = _mm256_permute2f128_pd(vecs[0].v,vecs[1].v, 1 + (3<<4));\n\n  return Packet2cd(_mm256_add_pd(t0,t1));\n}\n\ntemplate<> EIGEN_STRONG_INLINE std::complex<double> predux_mul<Packet2cd>(const Packet2cd& a)\n{\n  return predux(pmul(Packet1cd(_mm256_extractf128_pd(a.v,0)),\n                     Packet1cd(_mm256_extractf128_pd(a.v,1))));\n}\n\ntemplate<int Offset>\nstruct palign_impl<Offset,Packet2cd>\n{\n  static EIGEN_STRONG_INLINE void run(Packet2cd& first, const Packet2cd& second)\n  {\n    if (Offset==0) return;\n    palign_impl<Offset*2,Packet4d>::run(first.v, second.v);\n  }\n};\n\ntemplate<> struct conj_helper<Packet2cd, Packet2cd, false,true>\n{\n  EIGEN_STRONG_INLINE Packet2cd pmadd(const Packet2cd& x, const Packet2cd& y, const Packet2cd& c) const\n  { return padd(pmul(x,y),c); }\n\n  EIGEN_STRONG_INLINE Packet2cd pmul(const Packet2cd& a, const Packet2cd& b) const\n  {\n    return internal::pmul(a, pconj(b));\n  }\n};\n\ntemplate<> struct conj_helper<Packet2cd, Packet2cd, true,false>\n{\n  EIGEN_STRONG_INLINE Packet2cd pmadd(const Packet2cd& x, const Packet2cd& y, const Packet2cd& c) const\n  { return padd(pmul(x,y),c); }\n\n  EIGEN_STRONG_INLINE Packet2cd pmul(const Packet2cd& a, const Packet2cd& b) const\n  {\n    return internal::pmul(pconj(a), b);\n  }\n};\n\ntemplate<> struct conj_helper<Packet2cd, Packet2cd, true,true>\n{\n  EIGEN_STRONG_INLINE Packet2cd pmadd(const Packet2cd& x, const Packet2cd& y, const Packet2cd& c) const\n  { return padd(pmul(x,y),c); }\n\n  EIGEN_STRONG_INLINE Packet2cd pmul(const Packet2cd& a, const Packet2cd& b) const\n  {\n    return pconj(internal::pmul(a, b));\n  }\n};\n\ntemplate<> struct conj_helper<Packet4d, Packet2cd, false,false>\n{\n  EIGEN_STRONG_INLINE Packet2cd pmadd(const Packet4d& x, const Packet2cd& y, const Packet2cd& c) const\n  { return padd(c, pmul(x,y)); }\n\n  EIGEN_STRONG_INLINE Packet2cd pmul(const Packet4d& x, const Packet2cd& y) const\n  { return Packet2cd(Eigen::internal::pmul(x, y.v)); }\n};\n\ntemplate<> struct conj_helper<Packet2cd, Packet4d, false,false>\n{\n  EIGEN_STRONG_INLINE Packet2cd pmadd(const Packet2cd& x, const Packet4d& y, const Packet2cd& c) const\n  { return padd(c, pmul(x,y)); }\n\n  EIGEN_STRONG_INLINE Packet2cd pmul(const Packet2cd& x, const Packet4d& y) const\n  { return Packet2cd(Eigen::internal::pmul(x.v, y)); }\n};\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cd pdiv<Packet2cd>(const Packet2cd& a, const Packet2cd& b)\n{\n  Packet2cd num = pmul(a, pconj(b));\n  __m256d tmp = _mm256_mul_pd(b.v, b.v);\n  __m256d denom = _mm256_hadd_pd(tmp, tmp);\n  return Packet2cd(_mm256_div_pd(num.v, denom));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cd pcplxflip<Packet2cd>(const Packet2cd& x)\n{\n  return Packet2cd(_mm256_shuffle_pd(x.v, x.v, 0x5));\n}\n\nEIGEN_DEVICE_FUNC inline void\nptranspose(PacketBlock<Packet4cf,4>& kernel) {\n  __m256d P0 = _mm256_castps_pd(kernel.packet[0].v);\n  __m256d P1 = _mm256_castps_pd(kernel.packet[1].v);\n  __m256d P2 = _mm256_castps_pd(kernel.packet[2].v);\n  __m256d P3 = _mm256_castps_pd(kernel.packet[3].v);\n\n  __m256d T0 = _mm256_shuffle_pd(P0, P1, 15);\n  __m256d T1 = _mm256_shuffle_pd(P0, P1, 0);\n  __m256d T2 = _mm256_shuffle_pd(P2, P3, 15);\n  __m256d T3 = _mm256_shuffle_pd(P2, P3, 0);\n\n  kernel.packet[1].v = _mm256_castpd_ps(_mm256_permute2f128_pd(T0, T2, 32));\n  kernel.packet[3].v = _mm256_castpd_ps(_mm256_permute2f128_pd(T0, T2, 49));\n  kernel.packet[0].v = _mm256_castpd_ps(_mm256_permute2f128_pd(T1, T3, 32));\n  kernel.packet[2].v = _mm256_castpd_ps(_mm256_permute2f128_pd(T1, T3, 49));\n}\n\nEIGEN_DEVICE_FUNC inline void\nptranspose(PacketBlock<Packet2cd,2>& kernel) {\n  __m256d tmp = _mm256_permute2f128_pd(kernel.packet[0].v, kernel.packet[1].v, 0+(2<<4));\n  kernel.packet[1].v = _mm256_permute2f128_pd(kernel.packet[0].v, kernel.packet[1].v, 1+(3<<4));\n kernel.packet[0].v = tmp;\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4cf pinsertfirst(const Packet4cf& a, std::complex<float> b)\n{\n  return Packet4cf(_mm256_blend_ps(a.v,pset1<Packet4cf>(b).v,1|2));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cd pinsertfirst(const Packet2cd& a, std::complex<double> b)\n{\n  return Packet2cd(_mm256_blend_pd(a.v,pset1<Packet2cd>(b).v,1|2));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4cf pinsertlast(const Packet4cf& a, std::complex<float> b)\n{\n  return Packet4cf(_mm256_blend_ps(a.v,pset1<Packet4cf>(b).v,(1<<7)|(1<<6)));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cd pinsertlast(const Packet2cd& a, std::complex<double> b)\n{\n  return Packet2cd(_mm256_blend_pd(a.v,pset1<Packet2cd>(b).v,(1<<3)|(1<<2)));\n}\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_COMPLEX_AVX_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/arch/AVX/MathFunctions.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2014 Pedro Gonnet (pedro.gonnet@gmail.com)\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_MATH_FUNCTIONS_AVX_H\n#define EIGEN_MATH_FUNCTIONS_AVX_H\n\n/* The sin, cos, exp, and log functions of this file are loosely derived from\n * Julien Pommier's sse math library: http://gruntthepeon.free.fr/ssemath/\n */\n\nnamespace Eigen {\n\nnamespace internal {\n\ninline Packet8i pshiftleft(Packet8i v, int n)\n{\n#ifdef EIGEN_VECTORIZE_AVX2\n  return _mm256_slli_epi32(v, n);\n#else\n  __m128i lo = _mm_slli_epi32(_mm256_extractf128_si256(v, 0), n);\n  __m128i hi = _mm_slli_epi32(_mm256_extractf128_si256(v, 1), n);\n  return _mm256_insertf128_si256(_mm256_castsi128_si256(lo), (hi), 1);\n#endif\n}\n\ninline Packet8f pshiftright(Packet8f v, int n)\n{\n#ifdef EIGEN_VECTORIZE_AVX2\n  return _mm256_cvtepi32_ps(_mm256_srli_epi32(_mm256_castps_si256(v), n));\n#else\n  __m128i lo = _mm_srli_epi32(_mm256_extractf128_si256(_mm256_castps_si256(v), 0), n);\n  __m128i hi = _mm_srli_epi32(_mm256_extractf128_si256(_mm256_castps_si256(v), 1), n);\n  return _mm256_cvtepi32_ps(_mm256_insertf128_si256(_mm256_castsi128_si256(lo), (hi), 1));\n#endif\n}\n\n// Sine function\n// Computes sin(x) by wrapping x to the interval [-Pi/4,3*Pi/4] and\n// evaluating interpolants in [-Pi/4,Pi/4] or [Pi/4,3*Pi/4]. The interpolants\n// are (anti-)symmetric and thus have only odd/even coefficients\ntemplate <>\nEIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED Packet8f\npsin<Packet8f>(const Packet8f& _x) {\n  Packet8f x = _x;\n\n  // Some useful values.\n  _EIGEN_DECLARE_CONST_Packet8i(one, 1);\n  _EIGEN_DECLARE_CONST_Packet8f(one, 1.0f);\n  _EIGEN_DECLARE_CONST_Packet8f(two, 2.0f);\n  _EIGEN_DECLARE_CONST_Packet8f(one_over_four, 0.25f);\n  _EIGEN_DECLARE_CONST_Packet8f(one_over_pi, 3.183098861837907e-01f);\n  _EIGEN_DECLARE_CONST_Packet8f(neg_pi_first, -3.140625000000000e+00f);\n  _EIGEN_DECLARE_CONST_Packet8f(neg_pi_second, -9.670257568359375e-04f);\n  _EIGEN_DECLARE_CONST_Packet8f(neg_pi_third, -6.278329571784980e-07f);\n  _EIGEN_DECLARE_CONST_Packet8f(four_over_pi, 1.273239544735163e+00f);\n\n  // Map x from [-Pi/4,3*Pi/4] to z in [-1,3] and subtract the shifted period.\n  Packet8f z = pmul(x, p8f_one_over_pi);\n  Packet8f shift = _mm256_floor_ps(padd(z, p8f_one_over_four));\n  x = pmadd(shift, p8f_neg_pi_first, x);\n  x = pmadd(shift, p8f_neg_pi_second, x);\n  x = pmadd(shift, p8f_neg_pi_third, x);\n  z = pmul(x, p8f_four_over_pi);\n\n  // Make a mask for the entries that need flipping, i.e. wherever the shift\n  // is odd.\n  Packet8i shift_ints = _mm256_cvtps_epi32(shift);\n  Packet8i shift_isodd = _mm256_castps_si256(_mm256_and_ps(_mm256_castsi256_ps(shift_ints), _mm256_castsi256_ps(p8i_one)));\n  Packet8i sign_flip_mask = pshiftleft(shift_isodd, 31);\n\n  // Create a mask for which interpolant to use, i.e. if z > 1, then the mask\n  // is set to ones for that entry.\n  Packet8f ival_mask = _mm256_cmp_ps(z, p8f_one, _CMP_GT_OQ);\n\n  // Evaluate the polynomial for the interval [1,3] in z.\n  _EIGEN_DECLARE_CONST_Packet8f(coeff_right_0, 9.999999724233232e-01f);\n  _EIGEN_DECLARE_CONST_Packet8f(coeff_right_2, -3.084242535619928e-01f);\n  _EIGEN_DECLARE_CONST_Packet8f(coeff_right_4, 1.584991525700324e-02f);\n  _EIGEN_DECLARE_CONST_Packet8f(coeff_right_6, -3.188805084631342e-04f);\n  Packet8f z_minus_two = psub(z, p8f_two);\n  Packet8f z_minus_two2 = pmul(z_minus_two, z_minus_two);\n  Packet8f right = pmadd(p8f_coeff_right_6, z_minus_two2, p8f_coeff_right_4);\n  right = pmadd(right, z_minus_two2, p8f_coeff_right_2);\n  right = pmadd(right, z_minus_two2, p8f_coeff_right_0);\n\n  // Evaluate the polynomial for the interval [-1,1] in z.\n  _EIGEN_DECLARE_CONST_Packet8f(coeff_left_1, 7.853981525427295e-01f);\n  _EIGEN_DECLARE_CONST_Packet8f(coeff_left_3, -8.074536727092352e-02f);\n  _EIGEN_DECLARE_CONST_Packet8f(coeff_left_5, 2.489871967827018e-03f);\n  _EIGEN_DECLARE_CONST_Packet8f(coeff_left_7, -3.587725841214251e-05f);\n  Packet8f z2 = pmul(z, z);\n  Packet8f left = pmadd(p8f_coeff_left_7, z2, p8f_coeff_left_5);\n  left = pmadd(left, z2, p8f_coeff_left_3);\n  left = pmadd(left, z2, p8f_coeff_left_1);\n  left = pmul(left, z);\n\n  // Assemble the results, i.e. select the left and right polynomials.\n  left = _mm256_andnot_ps(ival_mask, left);\n  right = _mm256_and_ps(ival_mask, right);\n  Packet8f res = _mm256_or_ps(left, right);\n\n  // Flip the sign on the odd intervals and return the result.\n  res = _mm256_xor_ps(res, _mm256_castsi256_ps(sign_flip_mask));\n  return res;\n}\n\n// Natural logarithm\n// Computes log(x) as log(2^e * m) = C*e + log(m), where the constant C =log(2)\n// and m is in the range [sqrt(1/2),sqrt(2)). In this range, the logarithm can\n// be easily approximated by a polynomial centered on m=1 for stability.\n// TODO(gonnet): Further reduce the interval allowing for lower-degree\n//               polynomial interpolants -> ... -> profit!\ntemplate <>\nEIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED Packet8f\nplog<Packet8f>(const Packet8f& _x) {\n  Packet8f x = _x;\n  _EIGEN_DECLARE_CONST_Packet8f(1, 1.0f);\n  _EIGEN_DECLARE_CONST_Packet8f(half, 0.5f);\n  _EIGEN_DECLARE_CONST_Packet8f(126f, 126.0f);\n\n  _EIGEN_DECLARE_CONST_Packet8f_FROM_INT(inv_mant_mask, ~0x7f800000);\n\n  // The smallest non denormalized float number.\n  _EIGEN_DECLARE_CONST_Packet8f_FROM_INT(min_norm_pos, 0x00800000);\n  _EIGEN_DECLARE_CONST_Packet8f_FROM_INT(minus_inf, 0xff800000);\n\n  // Polynomial coefficients.\n  _EIGEN_DECLARE_CONST_Packet8f(cephes_SQRTHF, 0.707106781186547524f);\n  _EIGEN_DECLARE_CONST_Packet8f(cephes_log_p0, 7.0376836292E-2f);\n  _EIGEN_DECLARE_CONST_Packet8f(cephes_log_p1, -1.1514610310E-1f);\n  _EIGEN_DECLARE_CONST_Packet8f(cephes_log_p2, 1.1676998740E-1f);\n  _EIGEN_DECLARE_CONST_Packet8f(cephes_log_p3, -1.2420140846E-1f);\n  _EIGEN_DECLARE_CONST_Packet8f(cephes_log_p4, +1.4249322787E-1f);\n  _EIGEN_DECLARE_CONST_Packet8f(cephes_log_p5, -1.6668057665E-1f);\n  _EIGEN_DECLARE_CONST_Packet8f(cephes_log_p6, +2.0000714765E-1f);\n  _EIGEN_DECLARE_CONST_Packet8f(cephes_log_p7, -2.4999993993E-1f);\n  _EIGEN_DECLARE_CONST_Packet8f(cephes_log_p8, +3.3333331174E-1f);\n  _EIGEN_DECLARE_CONST_Packet8f(cephes_log_q1, -2.12194440e-4f);\n  _EIGEN_DECLARE_CONST_Packet8f(cephes_log_q2, 0.693359375f);\n\n  Packet8f invalid_mask = _mm256_cmp_ps(x, _mm256_setzero_ps(), _CMP_NGE_UQ); // not greater equal is true if x is NaN\n  Packet8f iszero_mask = _mm256_cmp_ps(x, _mm256_setzero_ps(), _CMP_EQ_OQ);\n\n  // Truncate input values to the minimum positive normal.\n  x = pmax(x, p8f_min_norm_pos);\n\n  Packet8f emm0 = pshiftright(x,23);\n  Packet8f e = _mm256_sub_ps(emm0, p8f_126f);\n\n  // Set the exponents to -1, i.e. x are in the range [0.5,1).\n  x = _mm256_and_ps(x, p8f_inv_mant_mask);\n  x = _mm256_or_ps(x, p8f_half);\n\n  // part2: Shift the inputs from the range [0.5,1) to [sqrt(1/2),sqrt(2))\n  // and shift by -1. The values are then centered around 0, which improves\n  // the stability of the polynomial evaluation.\n  //   if( x < SQRTHF ) {\n  //     e -= 1;\n  //     x = x + x - 1.0;\n  //   } else { x = x - 1.0; }\n  Packet8f mask = _mm256_cmp_ps(x, p8f_cephes_SQRTHF, _CMP_LT_OQ);\n  Packet8f tmp = _mm256_and_ps(x, mask);\n  x = psub(x, p8f_1);\n  e = psub(e, _mm256_and_ps(p8f_1, mask));\n  x = padd(x, tmp);\n\n  Packet8f x2 = pmul(x, x);\n  Packet8f x3 = pmul(x2, x);\n\n  // Evaluate the polynomial approximant of degree 8 in three parts, probably\n  // to improve instruction-level parallelism.\n  Packet8f y, y1, y2;\n  y = pmadd(p8f_cephes_log_p0, x, p8f_cephes_log_p1);\n  y1 = pmadd(p8f_cephes_log_p3, x, p8f_cephes_log_p4);\n  y2 = pmadd(p8f_cephes_log_p6, x, p8f_cephes_log_p7);\n  y = pmadd(y, x, p8f_cephes_log_p2);\n  y1 = pmadd(y1, x, p8f_cephes_log_p5);\n  y2 = pmadd(y2, x, p8f_cephes_log_p8);\n  y = pmadd(y, x3, y1);\n  y = pmadd(y, x3, y2);\n  y = pmul(y, x3);\n\n  // Add the logarithm of the exponent back to the result of the interpolation.\n  y1 = pmul(e, p8f_cephes_log_q1);\n  tmp = pmul(x2, p8f_half);\n  y = padd(y, y1);\n  x = psub(x, tmp);\n  y2 = pmul(e, p8f_cephes_log_q2);\n  x = padd(x, y);\n  x = padd(x, y2);\n\n  // Filter out invalid inputs, i.e. negative arg will be NAN, 0 will be -INF.\n  return _mm256_or_ps(\n      _mm256_andnot_ps(iszero_mask, _mm256_or_ps(x, invalid_mask)),\n      _mm256_and_ps(iszero_mask, p8f_minus_inf));\n}\n\n// Exponential function. Works by writing \"x = m*log(2) + r\" where\n// \"m = floor(x/log(2)+1/2)\" and \"r\" is the remainder. The result is then\n// \"exp(x) = 2^m*exp(r)\" where exp(r) is in the range [-1,1).\ntemplate <>\nEIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED Packet8f\npexp<Packet8f>(const Packet8f& _x) {\n  _EIGEN_DECLARE_CONST_Packet8f(1, 1.0f);\n  _EIGEN_DECLARE_CONST_Packet8f(half, 0.5f);\n  _EIGEN_DECLARE_CONST_Packet8f(127, 127.0f);\n\n  _EIGEN_DECLARE_CONST_Packet8f(exp_hi, 88.3762626647950f);\n  _EIGEN_DECLARE_CONST_Packet8f(exp_lo, -88.3762626647949f);\n\n  _EIGEN_DECLARE_CONST_Packet8f(cephes_LOG2EF, 1.44269504088896341f);\n\n  _EIGEN_DECLARE_CONST_Packet8f(cephes_exp_p0, 1.9875691500E-4f);\n  _EIGEN_DECLARE_CONST_Packet8f(cephes_exp_p1, 1.3981999507E-3f);\n  _EIGEN_DECLARE_CONST_Packet8f(cephes_exp_p2, 8.3334519073E-3f);\n  _EIGEN_DECLARE_CONST_Packet8f(cephes_exp_p3, 4.1665795894E-2f);\n  _EIGEN_DECLARE_CONST_Packet8f(cephes_exp_p4, 1.6666665459E-1f);\n  _EIGEN_DECLARE_CONST_Packet8f(cephes_exp_p5, 5.0000001201E-1f);\n\n  // Clamp x.\n  Packet8f x = pmax(pmin(_x, p8f_exp_hi), p8f_exp_lo);\n\n  // Express exp(x) as exp(m*ln(2) + r), start by extracting\n  // m = floor(x/ln(2) + 0.5).\n  Packet8f m = _mm256_floor_ps(pmadd(x, p8f_cephes_LOG2EF, p8f_half));\n\n// Get r = x - m*ln(2). If no FMA instructions are available, m*ln(2) is\n// subtracted out in two parts, m*C1+m*C2 = m*ln(2), to avoid accumulating\n// truncation errors. Note that we don't use the \"pmadd\" function here to\n// ensure that a precision-preserving FMA instruction is used.\n#ifdef EIGEN_VECTORIZE_FMA\n  _EIGEN_DECLARE_CONST_Packet8f(nln2, -0.6931471805599453f);\n  Packet8f r = _mm256_fmadd_ps(m, p8f_nln2, x);\n#else\n  _EIGEN_DECLARE_CONST_Packet8f(cephes_exp_C1, 0.693359375f);\n  _EIGEN_DECLARE_CONST_Packet8f(cephes_exp_C2, -2.12194440e-4f);\n  Packet8f r = psub(x, pmul(m, p8f_cephes_exp_C1));\n  r = psub(r, pmul(m, p8f_cephes_exp_C2));\n#endif\n\n  Packet8f r2 = pmul(r, r);\n\n  // TODO(gonnet): Split into odd/even polynomials and try to exploit\n  //               instruction-level parallelism.\n  Packet8f y = p8f_cephes_exp_p0;\n  y = pmadd(y, r, p8f_cephes_exp_p1);\n  y = pmadd(y, r, p8f_cephes_exp_p2);\n  y = pmadd(y, r, p8f_cephes_exp_p3);\n  y = pmadd(y, r, p8f_cephes_exp_p4);\n  y = pmadd(y, r, p8f_cephes_exp_p5);\n  y = pmadd(y, r2, r);\n  y = padd(y, p8f_1);\n\n  // Build emm0 = 2^m.\n  Packet8i emm0 = _mm256_cvttps_epi32(padd(m, p8f_127));\n  emm0 = pshiftleft(emm0, 23);\n\n  // Return 2^m * exp(r).\n  return pmax(pmul(y, _mm256_castsi256_ps(emm0)), _x);\n}\n\n// Hyperbolic Tangent function.\ntemplate <>\nEIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED Packet8f\nptanh<Packet8f>(const Packet8f& x) {\n  return internal::generic_fast_tanh_float(x);\n}\n\ntemplate <>\nEIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED Packet4d\npexp<Packet4d>(const Packet4d& _x) {\n  Packet4d x = _x;\n\n  _EIGEN_DECLARE_CONST_Packet4d(1, 1.0);\n  _EIGEN_DECLARE_CONST_Packet4d(2, 2.0);\n  _EIGEN_DECLARE_CONST_Packet4d(half, 0.5);\n\n  _EIGEN_DECLARE_CONST_Packet4d(exp_hi, 709.437);\n  _EIGEN_DECLARE_CONST_Packet4d(exp_lo, -709.436139303);\n\n  _EIGEN_DECLARE_CONST_Packet4d(cephes_LOG2EF, 1.4426950408889634073599);\n\n  _EIGEN_DECLARE_CONST_Packet4d(cephes_exp_p0, 1.26177193074810590878e-4);\n  _EIGEN_DECLARE_CONST_Packet4d(cephes_exp_p1, 3.02994407707441961300e-2);\n  _EIGEN_DECLARE_CONST_Packet4d(cephes_exp_p2, 9.99999999999999999910e-1);\n\n  _EIGEN_DECLARE_CONST_Packet4d(cephes_exp_q0, 3.00198505138664455042e-6);\n  _EIGEN_DECLARE_CONST_Packet4d(cephes_exp_q1, 2.52448340349684104192e-3);\n  _EIGEN_DECLARE_CONST_Packet4d(cephes_exp_q2, 2.27265548208155028766e-1);\n  _EIGEN_DECLARE_CONST_Packet4d(cephes_exp_q3, 2.00000000000000000009e0);\n\n  _EIGEN_DECLARE_CONST_Packet4d(cephes_exp_C1, 0.693145751953125);\n  _EIGEN_DECLARE_CONST_Packet4d(cephes_exp_C2, 1.42860682030941723212e-6);\n  _EIGEN_DECLARE_CONST_Packet4i(1023, 1023);\n\n  Packet4d tmp, fx;\n\n  // clamp x\n  x = pmax(pmin(x, p4d_exp_hi), p4d_exp_lo);\n  // Express exp(x) as exp(g + n*log(2)).\n  fx = pmadd(p4d_cephes_LOG2EF, x, p4d_half);\n\n  // Get the integer modulus of log(2), i.e. the \"n\" described above.\n  fx = _mm256_floor_pd(fx);\n\n  // Get the remainder modulo log(2), i.e. the \"g\" described above. Subtract\n  // n*log(2) out in two steps, i.e. n*C1 + n*C2, C1+C2=log2 to get the last\n  // digits right.\n  tmp = pmul(fx, p4d_cephes_exp_C1);\n  Packet4d z = pmul(fx, p4d_cephes_exp_C2);\n  x = psub(x, tmp);\n  x = psub(x, z);\n\n  Packet4d x2 = pmul(x, x);\n\n  // Evaluate the numerator polynomial of the rational interpolant.\n  Packet4d px = p4d_cephes_exp_p0;\n  px = pmadd(px, x2, p4d_cephes_exp_p1);\n  px = pmadd(px, x2, p4d_cephes_exp_p2);\n  px = pmul(px, x);\n\n  // Evaluate the denominator polynomial of the rational interpolant.\n  Packet4d qx = p4d_cephes_exp_q0;\n  qx = pmadd(qx, x2, p4d_cephes_exp_q1);\n  qx = pmadd(qx, x2, p4d_cephes_exp_q2);\n  qx = pmadd(qx, x2, p4d_cephes_exp_q3);\n\n  // I don't really get this bit, copied from the SSE2 routines, so...\n  // TODO(gonnet): Figure out what is going on here, perhaps find a better\n  // rational interpolant?\n  x = _mm256_div_pd(px, psub(qx, px));\n  x = pmadd(p4d_2, x, p4d_1);\n\n  // Build e=2^n by constructing the exponents in a 128-bit vector and\n  // shifting them to where they belong in double-precision values.\n  __m128i emm0 = _mm256_cvtpd_epi32(fx);\n  emm0 = _mm_add_epi32(emm0, p4i_1023);\n  emm0 = _mm_shuffle_epi32(emm0, _MM_SHUFFLE(3, 1, 2, 0));\n  __m128i lo = _mm_slli_epi64(emm0, 52);\n  __m128i hi = _mm_slli_epi64(_mm_srli_epi64(emm0, 32), 52);\n  __m256i e = _mm256_insertf128_si256(_mm256_setzero_si256(), lo, 0);\n  e = _mm256_insertf128_si256(e, hi, 1);\n\n  // Construct the result 2^n * exp(g) = e * x. The max is used to catch\n  // non-finite values in the input.\n  return pmax(pmul(x, _mm256_castsi256_pd(e)), _x);\n}\n\n// Functions for sqrt.\n// The EIGEN_FAST_MATH version uses the _mm_rsqrt_ps approximation and one step\n// of Newton's method, at a cost of 1-2 bits of precision as opposed to the\n// exact solution. It does not handle +inf, or denormalized numbers correctly.\n// The main advantage of this approach is not just speed, but also the fact that\n// it can be inlined and pipelined with other computations, further reducing its\n// effective latency. This is similar to Quake3's fast inverse square root.\n// For detail see here: http://www.beyond3d.com/content/articles/8/\n#if EIGEN_FAST_MATH\ntemplate <>\nEIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED Packet8f\npsqrt<Packet8f>(const Packet8f& _x) {\n  Packet8f half = pmul(_x, pset1<Packet8f>(.5f));\n  Packet8f denormal_mask = _mm256_and_ps(\n      _mm256_cmp_ps(_x, pset1<Packet8f>((std::numeric_limits<float>::min)()),\n                    _CMP_LT_OQ),\n      _mm256_cmp_ps(_x, _mm256_setzero_ps(), _CMP_GE_OQ));\n\n  // Compute approximate reciprocal sqrt.\n  Packet8f x = _mm256_rsqrt_ps(_x);\n  // Do a single step of Newton's iteration.\n  x = pmul(x, psub(pset1<Packet8f>(1.5f), pmul(half, pmul(x,x))));\n  // Flush results for denormals to zero.\n  return _mm256_andnot_ps(denormal_mask, pmul(_x,x));\n}\n#else\ntemplate <> EIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED\nPacket8f psqrt<Packet8f>(const Packet8f& x) {\n  return _mm256_sqrt_ps(x);\n}\n#endif\ntemplate <> EIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED\nPacket4d psqrt<Packet4d>(const Packet4d& x) {\n  return _mm256_sqrt_pd(x);\n}\n#if EIGEN_FAST_MATH\n\ntemplate<> EIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED\nPacket8f prsqrt<Packet8f>(const Packet8f& _x) {\n  _EIGEN_DECLARE_CONST_Packet8f_FROM_INT(inf, 0x7f800000);\n  _EIGEN_DECLARE_CONST_Packet8f_FROM_INT(nan, 0x7fc00000);\n  _EIGEN_DECLARE_CONST_Packet8f(one_point_five, 1.5f);\n  _EIGEN_DECLARE_CONST_Packet8f(minus_half, -0.5f);\n  _EIGEN_DECLARE_CONST_Packet8f_FROM_INT(flt_min, 0x00800000);\n\n  Packet8f neg_half = pmul(_x, p8f_minus_half);\n\n  // select only the inverse sqrt of positive normal inputs (denormals are\n  // flushed to zero and cause infs as well).\n  Packet8f le_zero_mask = _mm256_cmp_ps(_x, p8f_flt_min, _CMP_LT_OQ);\n  Packet8f x = _mm256_andnot_ps(le_zero_mask, _mm256_rsqrt_ps(_x));\n\n  // Fill in NaNs and Infs for the negative/zero entries.\n  Packet8f neg_mask = _mm256_cmp_ps(_x, _mm256_setzero_ps(), _CMP_LT_OQ);\n  Packet8f zero_mask = _mm256_andnot_ps(neg_mask, le_zero_mask);\n  Packet8f infs_and_nans = _mm256_or_ps(_mm256_and_ps(neg_mask, p8f_nan),\n                                        _mm256_and_ps(zero_mask, p8f_inf));\n\n  // Do a single step of Newton's iteration.\n  x = pmul(x, pmadd(neg_half, pmul(x, x), p8f_one_point_five));\n\n  // Insert NaNs and Infs in all the right places.\n  return _mm256_or_ps(x, infs_and_nans);\n}\n\n#else\ntemplate <> EIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED\nPacket8f prsqrt<Packet8f>(const Packet8f& x) {\n  _EIGEN_DECLARE_CONST_Packet8f(one, 1.0f);\n  return _mm256_div_ps(p8f_one, _mm256_sqrt_ps(x));\n}\n#endif\n\ntemplate <> EIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED\nPacket4d prsqrt<Packet4d>(const Packet4d& x) {\n  _EIGEN_DECLARE_CONST_Packet4d(one, 1.0);\n  return _mm256_div_pd(p4d_one, _mm256_sqrt_pd(x));\n}\n\n\n}  // end namespace internal\n\n}  // end namespace Eigen\n\n#endif  // EIGEN_MATH_FUNCTIONS_AVX_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/arch/AVX/PacketMath.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2014 Benoit Steiner (benoit.steiner.goog@gmail.com)\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_PACKET_MATH_AVX_H\n#define EIGEN_PACKET_MATH_AVX_H\n\nnamespace Eigen {\n\nnamespace internal {\n\n#ifndef EIGEN_CACHEFRIENDLY_PRODUCT_THRESHOLD\n#define EIGEN_CACHEFRIENDLY_PRODUCT_THRESHOLD 8\n#endif\n\n#ifndef EIGEN_ARCH_DEFAULT_NUMBER_OF_REGISTERS\n#define EIGEN_ARCH_DEFAULT_NUMBER_OF_REGISTERS (2*sizeof(void*))\n#endif\n\n#ifdef __FMA__\n#ifndef EIGEN_HAS_SINGLE_INSTRUCTION_MADD\n#define EIGEN_HAS_SINGLE_INSTRUCTION_MADD\n#endif\n#endif\n\ntypedef __m256  Packet8f;\ntypedef __m256i Packet8i;\ntypedef __m256d Packet4d;\n\ntemplate<> struct is_arithmetic<__m256>  { enum { value = true }; };\ntemplate<> struct is_arithmetic<__m256i> { enum { value = true }; };\ntemplate<> struct is_arithmetic<__m256d> { enum { value = true }; };\n\n#define _EIGEN_DECLARE_CONST_Packet8f(NAME,X) \\\n  const Packet8f p8f_##NAME = pset1<Packet8f>(X)\n\n#define _EIGEN_DECLARE_CONST_Packet4d(NAME,X) \\\n  const Packet4d p4d_##NAME = pset1<Packet4d>(X)\n\n#define _EIGEN_DECLARE_CONST_Packet8f_FROM_INT(NAME,X) \\\n  const Packet8f p8f_##NAME = _mm256_castsi256_ps(pset1<Packet8i>(X))\n\n#define _EIGEN_DECLARE_CONST_Packet8i(NAME,X) \\\n  const Packet8i p8i_##NAME = pset1<Packet8i>(X)\n\n// Use the packet_traits defined in AVX512/PacketMath.h instead if we're going\n// to leverage AVX512 instructions.\n#ifndef EIGEN_VECTORIZE_AVX512\ntemplate<> struct packet_traits<float>  : default_packet_traits\n{\n  typedef Packet8f type;\n  typedef Packet4f half;\n  enum {\n    Vectorizable = 1,\n    AlignedOnScalar = 1,\n    size=8,\n    HasHalfPacket = 1,\n\n    HasDiv  = 1,\n    HasSin  = EIGEN_FAST_MATH,\n    HasCos  = 0,\n    HasLog  = 1,\n    HasExp  = 1,\n    HasSqrt = 1,\n    HasRsqrt = 1,\n    HasTanh  = EIGEN_FAST_MATH,\n    HasBlend = 1,\n    HasRound = 1,\n    HasFloor = 1,\n    HasCeil = 1\n  };\n};\ntemplate<> struct packet_traits<double> : default_packet_traits\n{\n  typedef Packet4d type;\n  typedef Packet2d half;\n  enum {\n    Vectorizable = 1,\n    AlignedOnScalar = 1,\n    size=4,\n    HasHalfPacket = 1,\n\n    HasDiv  = 1,\n    HasExp  = 1,\n    HasSqrt = 1,\n    HasRsqrt = 1,\n    HasBlend = 1,\n    HasRound = 1,\n    HasFloor = 1,\n    HasCeil = 1\n  };\n};\n#endif\n\ntemplate<> struct scalar_div_cost<float,true> { enum { value = 14 }; };\ntemplate<> struct scalar_div_cost<double,true> { enum { value = 16 }; };\n\n/* Proper support for integers is only provided by AVX2. In the meantime, we'll\n   use SSE instructions and packets to deal with integers.\ntemplate<> struct packet_traits<int>    : default_packet_traits\n{\n  typedef Packet8i type;\n  enum {\n    Vectorizable = 1,\n    AlignedOnScalar = 1,\n    size=8\n  };\n};\n*/\n\ntemplate<> struct unpacket_traits<Packet8f> { typedef float  type; typedef Packet4f half; enum {size=8, alignment=Aligned32}; };\ntemplate<> struct unpacket_traits<Packet4d> { typedef double type; typedef Packet2d half; enum {size=4, alignment=Aligned32}; };\ntemplate<> struct unpacket_traits<Packet8i> { typedef int    type; typedef Packet4i half; enum {size=8, alignment=Aligned32}; };\n\ntemplate<> EIGEN_STRONG_INLINE Packet8f pset1<Packet8f>(const float&  from) { return _mm256_set1_ps(from); }\ntemplate<> EIGEN_STRONG_INLINE Packet4d pset1<Packet4d>(const double& from) { return _mm256_set1_pd(from); }\ntemplate<> EIGEN_STRONG_INLINE Packet8i pset1<Packet8i>(const int&    from) { return _mm256_set1_epi32(from); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet8f pload1<Packet8f>(const float*  from) { return _mm256_broadcast_ss(from); }\ntemplate<> EIGEN_STRONG_INLINE Packet4d pload1<Packet4d>(const double* from) { return _mm256_broadcast_sd(from); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet8f plset<Packet8f>(const float& a) { return _mm256_add_ps(_mm256_set1_ps(a), _mm256_set_ps(7.0,6.0,5.0,4.0,3.0,2.0,1.0,0.0)); }\ntemplate<> EIGEN_STRONG_INLINE Packet4d plset<Packet4d>(const double& a) { return _mm256_add_pd(_mm256_set1_pd(a), _mm256_set_pd(3.0,2.0,1.0,0.0)); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet8f padd<Packet8f>(const Packet8f& a, const Packet8f& b) { return _mm256_add_ps(a,b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4d padd<Packet4d>(const Packet4d& a, const Packet4d& b) { return _mm256_add_pd(a,b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet8f psub<Packet8f>(const Packet8f& a, const Packet8f& b) { return _mm256_sub_ps(a,b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4d psub<Packet4d>(const Packet4d& a, const Packet4d& b) { return _mm256_sub_pd(a,b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet8f pnegate(const Packet8f& a)\n{\n  return _mm256_sub_ps(_mm256_set1_ps(0.0),a);\n}\ntemplate<> EIGEN_STRONG_INLINE Packet4d pnegate(const Packet4d& a)\n{\n  return _mm256_sub_pd(_mm256_set1_pd(0.0),a);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet8f pconj(const Packet8f& a) { return a; }\ntemplate<> EIGEN_STRONG_INLINE Packet4d pconj(const Packet4d& a) { return a; }\ntemplate<> EIGEN_STRONG_INLINE Packet8i pconj(const Packet8i& a) { return a; }\n\ntemplate<> EIGEN_STRONG_INLINE Packet8f pmul<Packet8f>(const Packet8f& a, const Packet8f& b) { return _mm256_mul_ps(a,b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4d pmul<Packet4d>(const Packet4d& a, const Packet4d& b) { return _mm256_mul_pd(a,b); }\n\n\ntemplate<> EIGEN_STRONG_INLINE Packet8f pdiv<Packet8f>(const Packet8f& a, const Packet8f& b) { return _mm256_div_ps(a,b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4d pdiv<Packet4d>(const Packet4d& a, const Packet4d& b) { return _mm256_div_pd(a,b); }\ntemplate<> EIGEN_STRONG_INLINE Packet8i pdiv<Packet8i>(const Packet8i& /*a*/, const Packet8i& /*b*/)\n{ eigen_assert(false && \"packet integer division are not supported by AVX\");\n  return pset1<Packet8i>(0);\n}\n\n#ifdef __FMA__\ntemplate<> EIGEN_STRONG_INLINE Packet8f pmadd(const Packet8f& a, const Packet8f& b, const Packet8f& c) {\n#if ( EIGEN_COMP_GNUC_STRICT || (EIGEN_COMP_CLANG && (EIGEN_COMP_CLANG<308)) )\n  // clang stupidly generates a vfmadd213ps instruction plus some vmovaps on registers,\n  // and gcc stupidly generates a vfmadd132ps instruction,\n  // so let's enforce it to generate a vfmadd231ps instruction since the most common use case is to accumulate\n  // the result of the product.\n  Packet8f res = c;\n  __asm__(\"vfmadd231ps %[a], %[b], %[c]\" : [c] \"+x\" (res) : [a] \"x\" (a), [b] \"x\" (b));\n  return res;\n#else\n  return _mm256_fmadd_ps(a,b,c);\n#endif\n}\ntemplate<> EIGEN_STRONG_INLINE Packet4d pmadd(const Packet4d& a, const Packet4d& b, const Packet4d& c) {\n#if ( EIGEN_COMP_GNUC_STRICT || (EIGEN_COMP_CLANG && (EIGEN_COMP_CLANG<308)) )\n  // see above\n  Packet4d res = c;\n  __asm__(\"vfmadd231pd %[a], %[b], %[c]\" : [c] \"+x\" (res) : [a] \"x\" (a), [b] \"x\" (b));\n  return res;\n#else\n  return _mm256_fmadd_pd(a,b,c);\n#endif\n}\n#endif\n\ntemplate<> EIGEN_STRONG_INLINE Packet8f pmin<Packet8f>(const Packet8f& a, const Packet8f& b) { return _mm256_min_ps(a,b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4d pmin<Packet4d>(const Packet4d& a, const Packet4d& b) { return _mm256_min_pd(a,b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet8f pmax<Packet8f>(const Packet8f& a, const Packet8f& b) { return _mm256_max_ps(a,b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4d pmax<Packet4d>(const Packet4d& a, const Packet4d& b) { return _mm256_max_pd(a,b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet8f pround<Packet8f>(const Packet8f& a) { return _mm256_round_ps(a, _MM_FROUND_CUR_DIRECTION); }\ntemplate<> EIGEN_STRONG_INLINE Packet4d pround<Packet4d>(const Packet4d& a) { return _mm256_round_pd(a, _MM_FROUND_CUR_DIRECTION); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet8f pceil<Packet8f>(const Packet8f& a) { return _mm256_ceil_ps(a); }\ntemplate<> EIGEN_STRONG_INLINE Packet4d pceil<Packet4d>(const Packet4d& a) { return _mm256_ceil_pd(a); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet8f pfloor<Packet8f>(const Packet8f& a) { return _mm256_floor_ps(a); }\ntemplate<> EIGEN_STRONG_INLINE Packet4d pfloor<Packet4d>(const Packet4d& a) { return _mm256_floor_pd(a); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet8f pand<Packet8f>(const Packet8f& a, const Packet8f& b) { return _mm256_and_ps(a,b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4d pand<Packet4d>(const Packet4d& a, const Packet4d& b) { return _mm256_and_pd(a,b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet8f por<Packet8f>(const Packet8f& a, const Packet8f& b) { return _mm256_or_ps(a,b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4d por<Packet4d>(const Packet4d& a, const Packet4d& b) { return _mm256_or_pd(a,b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet8f pxor<Packet8f>(const Packet8f& a, const Packet8f& b) { return _mm256_xor_ps(a,b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4d pxor<Packet4d>(const Packet4d& a, const Packet4d& b) { return _mm256_xor_pd(a,b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet8f pandnot<Packet8f>(const Packet8f& a, const Packet8f& b) { return _mm256_andnot_ps(a,b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4d pandnot<Packet4d>(const Packet4d& a, const Packet4d& b) { return _mm256_andnot_pd(a,b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet8f pload<Packet8f>(const float*   from) { EIGEN_DEBUG_ALIGNED_LOAD return _mm256_load_ps(from); }\ntemplate<> EIGEN_STRONG_INLINE Packet4d pload<Packet4d>(const double*  from) { EIGEN_DEBUG_ALIGNED_LOAD return _mm256_load_pd(from); }\ntemplate<> EIGEN_STRONG_INLINE Packet8i pload<Packet8i>(const int*     from) { EIGEN_DEBUG_ALIGNED_LOAD return _mm256_load_si256(reinterpret_cast<const __m256i*>(from)); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet8f ploadu<Packet8f>(const float* from) { EIGEN_DEBUG_UNALIGNED_LOAD return _mm256_loadu_ps(from); }\ntemplate<> EIGEN_STRONG_INLINE Packet4d ploadu<Packet4d>(const double* from) { EIGEN_DEBUG_UNALIGNED_LOAD return _mm256_loadu_pd(from); }\ntemplate<> EIGEN_STRONG_INLINE Packet8i ploadu<Packet8i>(const int* from) { EIGEN_DEBUG_UNALIGNED_LOAD return _mm256_loadu_si256(reinterpret_cast<const __m256i*>(from)); }\n\n// Loads 4 floats from memory a returns the packet {a0, a0  a1, a1, a2, a2, a3, a3}\ntemplate<> EIGEN_STRONG_INLINE Packet8f ploaddup<Packet8f>(const float* from)\n{\n  // TODO try to find a way to avoid the need of a temporary register\n//   Packet8f tmp  = _mm256_castps128_ps256(_mm_loadu_ps(from));\n//   tmp = _mm256_insertf128_ps(tmp, _mm_movehl_ps(_mm256_castps256_ps128(tmp),_mm256_castps256_ps128(tmp)), 1);\n//   return _mm256_unpacklo_ps(tmp,tmp);\n  \n  // _mm256_insertf128_ps is very slow on Haswell, thus:\n  Packet8f tmp = _mm256_broadcast_ps((const __m128*)(const void*)from);\n  // mimic an \"inplace\" permutation of the lower 128bits using a blend\n  tmp = _mm256_blend_ps(tmp,_mm256_castps128_ps256(_mm_permute_ps( _mm256_castps256_ps128(tmp), _MM_SHUFFLE(1,0,1,0))), 15);\n  // then we can perform a consistent permutation on the global register to get everything in shape:\n  return  _mm256_permute_ps(tmp, _MM_SHUFFLE(3,3,2,2));\n}\n// Loads 2 doubles from memory a returns the packet {a0, a0  a1, a1}\ntemplate<> EIGEN_STRONG_INLINE Packet4d ploaddup<Packet4d>(const double* from)\n{\n  Packet4d tmp = _mm256_broadcast_pd((const __m128d*)(const void*)from);\n  return  _mm256_permute_pd(tmp, 3<<2);\n}\n\n// Loads 2 floats from memory a returns the packet {a0, a0  a0, a0, a1, a1, a1, a1}\ntemplate<> EIGEN_STRONG_INLINE Packet8f ploadquad<Packet8f>(const float* from)\n{\n  Packet8f tmp = _mm256_castps128_ps256(_mm_broadcast_ss(from));\n  return _mm256_insertf128_ps(tmp, _mm_broadcast_ss(from+1), 1);\n}\n\ntemplate<> EIGEN_STRONG_INLINE void pstore<float>(float*   to, const Packet8f& from) { EIGEN_DEBUG_ALIGNED_STORE _mm256_store_ps(to, from); }\ntemplate<> EIGEN_STRONG_INLINE void pstore<double>(double* to, const Packet4d& from) { EIGEN_DEBUG_ALIGNED_STORE _mm256_store_pd(to, from); }\ntemplate<> EIGEN_STRONG_INLINE void pstore<int>(int*       to, const Packet8i& from) { EIGEN_DEBUG_ALIGNED_STORE _mm256_storeu_si256(reinterpret_cast<__m256i*>(to), from); }\n\ntemplate<> EIGEN_STRONG_INLINE void pstoreu<float>(float*   to, const Packet8f& from) { EIGEN_DEBUG_UNALIGNED_STORE _mm256_storeu_ps(to, from); }\ntemplate<> EIGEN_STRONG_INLINE void pstoreu<double>(double* to, const Packet4d& from) { EIGEN_DEBUG_UNALIGNED_STORE _mm256_storeu_pd(to, from); }\ntemplate<> EIGEN_STRONG_INLINE void pstoreu<int>(int*       to, const Packet8i& from) { EIGEN_DEBUG_UNALIGNED_STORE _mm256_storeu_si256(reinterpret_cast<__m256i*>(to), from); }\n\n// NOTE: leverage _mm256_i32gather_ps and _mm256_i32gather_pd if AVX2 instructions are available\n// NOTE: for the record the following seems to be slower: return _mm256_i32gather_ps(from, _mm256_set1_epi32(stride), 4);\ntemplate<> EIGEN_DEVICE_FUNC inline Packet8f pgather<float, Packet8f>(const float* from, Index stride)\n{\n  return _mm256_set_ps(from[7*stride], from[6*stride], from[5*stride], from[4*stride],\n                       from[3*stride], from[2*stride], from[1*stride], from[0*stride]);\n}\ntemplate<> EIGEN_DEVICE_FUNC inline Packet4d pgather<double, Packet4d>(const double* from, Index stride)\n{\n  return _mm256_set_pd(from[3*stride], from[2*stride], from[1*stride], from[0*stride]);\n}\n\ntemplate<> EIGEN_DEVICE_FUNC inline void pscatter<float, Packet8f>(float* to, const Packet8f& from, Index stride)\n{\n  __m128 low = _mm256_extractf128_ps(from, 0);\n  to[stride*0] = _mm_cvtss_f32(low);\n  to[stride*1] = _mm_cvtss_f32(_mm_shuffle_ps(low, low, 1));\n  to[stride*2] = _mm_cvtss_f32(_mm_shuffle_ps(low, low, 2));\n  to[stride*3] = _mm_cvtss_f32(_mm_shuffle_ps(low, low, 3));\n\n  __m128 high = _mm256_extractf128_ps(from, 1);\n  to[stride*4] = _mm_cvtss_f32(high);\n  to[stride*5] = _mm_cvtss_f32(_mm_shuffle_ps(high, high, 1));\n  to[stride*6] = _mm_cvtss_f32(_mm_shuffle_ps(high, high, 2));\n  to[stride*7] = _mm_cvtss_f32(_mm_shuffle_ps(high, high, 3));\n}\ntemplate<> EIGEN_DEVICE_FUNC inline void pscatter<double, Packet4d>(double* to, const Packet4d& from, Index stride)\n{\n  __m128d low = _mm256_extractf128_pd(from, 0);\n  to[stride*0] = _mm_cvtsd_f64(low);\n  to[stride*1] = _mm_cvtsd_f64(_mm_shuffle_pd(low, low, 1));\n  __m128d high = _mm256_extractf128_pd(from, 1);\n  to[stride*2] = _mm_cvtsd_f64(high);\n  to[stride*3] = _mm_cvtsd_f64(_mm_shuffle_pd(high, high, 1));\n}\n\ntemplate<> EIGEN_STRONG_INLINE void pstore1<Packet8f>(float* to, const float& a)\n{\n  Packet8f pa = pset1<Packet8f>(a);\n  pstore(to, pa);\n}\ntemplate<> EIGEN_STRONG_INLINE void pstore1<Packet4d>(double* to, const double& a)\n{\n  Packet4d pa = pset1<Packet4d>(a);\n  pstore(to, pa);\n}\ntemplate<> EIGEN_STRONG_INLINE void pstore1<Packet8i>(int* to, const int& a)\n{\n  Packet8i pa = pset1<Packet8i>(a);\n  pstore(to, pa);\n}\n\n#ifndef EIGEN_VECTORIZE_AVX512\ntemplate<> EIGEN_STRONG_INLINE void prefetch<float>(const float*   addr) { _mm_prefetch((const char*)(addr), _MM_HINT_T0); }\ntemplate<> EIGEN_STRONG_INLINE void prefetch<double>(const double* addr) { _mm_prefetch((const char*)(addr), _MM_HINT_T0); }\ntemplate<> EIGEN_STRONG_INLINE void prefetch<int>(const int*       addr) { _mm_prefetch((const char*)(addr), _MM_HINT_T0); }\n#endif\n\ntemplate<> EIGEN_STRONG_INLINE float  pfirst<Packet8f>(const Packet8f& a) {\n  return _mm_cvtss_f32(_mm256_castps256_ps128(a));\n}\ntemplate<> EIGEN_STRONG_INLINE double pfirst<Packet4d>(const Packet4d& a) {\n  return _mm_cvtsd_f64(_mm256_castpd256_pd128(a));\n}\ntemplate<> EIGEN_STRONG_INLINE int    pfirst<Packet8i>(const Packet8i& a) {\n  return _mm_cvtsi128_si32(_mm256_castsi256_si128(a));\n}\n\n\ntemplate<> EIGEN_STRONG_INLINE Packet8f preverse(const Packet8f& a)\n{\n  __m256 tmp = _mm256_shuffle_ps(a,a,0x1b);\n  return _mm256_permute2f128_ps(tmp, tmp, 1);\n}\ntemplate<> EIGEN_STRONG_INLINE Packet4d preverse(const Packet4d& a)\n{\n   __m256d tmp = _mm256_shuffle_pd(a,a,5);\n  return _mm256_permute2f128_pd(tmp, tmp, 1);\n\n  __m256d swap_halves = _mm256_permute2f128_pd(a,a,1);\n    return _mm256_permute_pd(swap_halves,5);\n}\n\n// pabs should be ok\ntemplate<> EIGEN_STRONG_INLINE Packet8f pabs(const Packet8f& a)\n{\n  const Packet8f mask = _mm256_castsi256_ps(_mm256_setr_epi32(0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF));\n  return _mm256_and_ps(a,mask);\n}\ntemplate<> EIGEN_STRONG_INLINE Packet4d pabs(const Packet4d& a)\n{\n  const Packet4d mask = _mm256_castsi256_pd(_mm256_setr_epi32(0xFFFFFFFF,0x7FFFFFFF,0xFFFFFFFF,0x7FFFFFFF,0xFFFFFFFF,0x7FFFFFFF,0xFFFFFFFF,0x7FFFFFFF));\n  return _mm256_and_pd(a,mask);\n}\n\n// preduxp should be ok\n// FIXME: why is this ok? why isn't the simply implementation working as expected?\ntemplate<> EIGEN_STRONG_INLINE Packet8f preduxp<Packet8f>(const Packet8f* vecs)\n{\n    __m256 hsum1 = _mm256_hadd_ps(vecs[0], vecs[1]);\n    __m256 hsum2 = _mm256_hadd_ps(vecs[2], vecs[3]);\n    __m256 hsum3 = _mm256_hadd_ps(vecs[4], vecs[5]);\n    __m256 hsum4 = _mm256_hadd_ps(vecs[6], vecs[7]);\n\n    __m256 hsum5 = _mm256_hadd_ps(hsum1, hsum1);\n    __m256 hsum6 = _mm256_hadd_ps(hsum2, hsum2);\n    __m256 hsum7 = _mm256_hadd_ps(hsum3, hsum3);\n    __m256 hsum8 = _mm256_hadd_ps(hsum4, hsum4);\n\n    __m256 perm1 =  _mm256_permute2f128_ps(hsum5, hsum5, 0x23);\n    __m256 perm2 =  _mm256_permute2f128_ps(hsum6, hsum6, 0x23);\n    __m256 perm3 =  _mm256_permute2f128_ps(hsum7, hsum7, 0x23);\n    __m256 perm4 =  _mm256_permute2f128_ps(hsum8, hsum8, 0x23);\n\n    __m256 sum1 = _mm256_add_ps(perm1, hsum5);\n    __m256 sum2 = _mm256_add_ps(perm2, hsum6);\n    __m256 sum3 = _mm256_add_ps(perm3, hsum7);\n    __m256 sum4 = _mm256_add_ps(perm4, hsum8);\n\n    __m256 blend1 = _mm256_blend_ps(sum1, sum2, 0xcc);\n    __m256 blend2 = _mm256_blend_ps(sum3, sum4, 0xcc);\n\n    __m256 final = _mm256_blend_ps(blend1, blend2, 0xf0);\n    return final;\n}\ntemplate<> EIGEN_STRONG_INLINE Packet4d preduxp<Packet4d>(const Packet4d* vecs)\n{\n Packet4d tmp0, tmp1;\n\n  tmp0 = _mm256_hadd_pd(vecs[0], vecs[1]);\n  tmp0 = _mm256_add_pd(tmp0, _mm256_permute2f128_pd(tmp0, tmp0, 1));\n\n  tmp1 = _mm256_hadd_pd(vecs[2], vecs[3]);\n  tmp1 = _mm256_add_pd(tmp1, _mm256_permute2f128_pd(tmp1, tmp1, 1));\n\n  return _mm256_blend_pd(tmp0, tmp1, 0xC);\n}\n\ntemplate<> EIGEN_STRONG_INLINE float predux<Packet8f>(const Packet8f& a)\n{\n  Packet8f tmp0 = _mm256_hadd_ps(a,_mm256_permute2f128_ps(a,a,1));\n  tmp0 = _mm256_hadd_ps(tmp0,tmp0);\n  return pfirst(_mm256_hadd_ps(tmp0, tmp0));\n}\ntemplate<> EIGEN_STRONG_INLINE double predux<Packet4d>(const Packet4d& a)\n{\n  Packet4d tmp0 = _mm256_hadd_pd(a,_mm256_permute2f128_pd(a,a,1));\n  return pfirst(_mm256_hadd_pd(tmp0,tmp0));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f predux_downto4<Packet8f>(const Packet8f& a)\n{\n  return _mm_add_ps(_mm256_castps256_ps128(a),_mm256_extractf128_ps(a,1));\n}\n\ntemplate<> EIGEN_STRONG_INLINE float predux_mul<Packet8f>(const Packet8f& a)\n{\n  Packet8f tmp;\n  tmp = _mm256_mul_ps(a, _mm256_permute2f128_ps(a,a,1));\n  tmp = _mm256_mul_ps(tmp, _mm256_shuffle_ps(tmp,tmp,_MM_SHUFFLE(1,0,3,2)));\n  return pfirst(_mm256_mul_ps(tmp, _mm256_shuffle_ps(tmp,tmp,1)));\n}\ntemplate<> EIGEN_STRONG_INLINE double predux_mul<Packet4d>(const Packet4d& a)\n{\n  Packet4d tmp;\n  tmp = _mm256_mul_pd(a, _mm256_permute2f128_pd(a,a,1));\n  return pfirst(_mm256_mul_pd(tmp, _mm256_shuffle_pd(tmp,tmp,1)));\n}\n\ntemplate<> EIGEN_STRONG_INLINE float predux_min<Packet8f>(const Packet8f& a)\n{\n  Packet8f tmp = _mm256_min_ps(a, _mm256_permute2f128_ps(a,a,1));\n  tmp = _mm256_min_ps(tmp, _mm256_shuffle_ps(tmp,tmp,_MM_SHUFFLE(1,0,3,2)));\n  return pfirst(_mm256_min_ps(tmp, _mm256_shuffle_ps(tmp,tmp,1)));\n}\ntemplate<> EIGEN_STRONG_INLINE double predux_min<Packet4d>(const Packet4d& a)\n{\n  Packet4d tmp = _mm256_min_pd(a, _mm256_permute2f128_pd(a,a,1));\n  return pfirst(_mm256_min_pd(tmp, _mm256_shuffle_pd(tmp, tmp, 1)));\n}\n\ntemplate<> EIGEN_STRONG_INLINE float predux_max<Packet8f>(const Packet8f& a)\n{\n  Packet8f tmp = _mm256_max_ps(a, _mm256_permute2f128_ps(a,a,1));\n  tmp = _mm256_max_ps(tmp, _mm256_shuffle_ps(tmp,tmp,_MM_SHUFFLE(1,0,3,2)));\n  return pfirst(_mm256_max_ps(tmp, _mm256_shuffle_ps(tmp,tmp,1)));\n}\n\ntemplate<> EIGEN_STRONG_INLINE double predux_max<Packet4d>(const Packet4d& a)\n{\n  Packet4d tmp = _mm256_max_pd(a, _mm256_permute2f128_pd(a,a,1));\n  return pfirst(_mm256_max_pd(tmp, _mm256_shuffle_pd(tmp, tmp, 1)));\n}\n\n\ntemplate<int Offset>\nstruct palign_impl<Offset,Packet8f>\n{\n  static EIGEN_STRONG_INLINE void run(Packet8f& first, const Packet8f& second)\n  {\n    if (Offset==1)\n    {\n      first = _mm256_blend_ps(first, second, 1);\n      Packet8f tmp1 = _mm256_permute_ps (first, _MM_SHUFFLE(0,3,2,1));\n      Packet8f tmp2 = _mm256_permute2f128_ps (tmp1, tmp1, 1);\n      first = _mm256_blend_ps(tmp1, tmp2, 0x88);\n    }\n    else if (Offset==2)\n    {\n      first = _mm256_blend_ps(first, second, 3);\n      Packet8f tmp1 = _mm256_permute_ps (first, _MM_SHUFFLE(1,0,3,2));\n      Packet8f tmp2 = _mm256_permute2f128_ps (tmp1, tmp1, 1);\n      first = _mm256_blend_ps(tmp1, tmp2, 0xcc);\n    }\n    else if (Offset==3)\n    {\n      first = _mm256_blend_ps(first, second, 7);\n      Packet8f tmp1 = _mm256_permute_ps (first, _MM_SHUFFLE(2,1,0,3));\n      Packet8f tmp2 = _mm256_permute2f128_ps (tmp1, tmp1, 1);\n      first = _mm256_blend_ps(tmp1, tmp2, 0xee);\n    }\n    else if (Offset==4)\n    {\n      first = _mm256_blend_ps(first, second, 15);\n      Packet8f tmp1 = _mm256_permute_ps (first, _MM_SHUFFLE(3,2,1,0));\n      Packet8f tmp2 = _mm256_permute2f128_ps (tmp1, tmp1, 1);\n      first = _mm256_permute_ps(tmp2, _MM_SHUFFLE(3,2,1,0));\n    }\n    else if (Offset==5)\n    {\n      first = _mm256_blend_ps(first, second, 31);\n      first = _mm256_permute2f128_ps(first, first, 1);\n      Packet8f tmp = _mm256_permute_ps (first, _MM_SHUFFLE(0,3,2,1));\n      first = _mm256_permute2f128_ps(tmp, tmp, 1);\n      first = _mm256_blend_ps(tmp, first, 0x88);\n    }\n    else if (Offset==6)\n    {\n      first = _mm256_blend_ps(first, second, 63);\n      first = _mm256_permute2f128_ps(first, first, 1);\n      Packet8f tmp = _mm256_permute_ps (first, _MM_SHUFFLE(1,0,3,2));\n      first = _mm256_permute2f128_ps(tmp, tmp, 1);\n      first = _mm256_blend_ps(tmp, first, 0xcc);\n    }\n    else if (Offset==7)\n    {\n      first = _mm256_blend_ps(first, second, 127);\n      first = _mm256_permute2f128_ps(first, first, 1);\n      Packet8f tmp = _mm256_permute_ps (first, _MM_SHUFFLE(2,1,0,3));\n      first = _mm256_permute2f128_ps(tmp, tmp, 1);\n      first = _mm256_blend_ps(tmp, first, 0xee);\n    }\n  }\n};\n\ntemplate<int Offset>\nstruct palign_impl<Offset,Packet4d>\n{\n  static EIGEN_STRONG_INLINE void run(Packet4d& first, const Packet4d& second)\n  {\n    if (Offset==1)\n    {\n      first = _mm256_blend_pd(first, second, 1);\n      __m256d tmp = _mm256_permute_pd(first, 5);\n      first = _mm256_permute2f128_pd(tmp, tmp, 1);\n      first = _mm256_blend_pd(tmp, first, 0xA);\n    }\n    else if (Offset==2)\n    {\n      first = _mm256_blend_pd(first, second, 3);\n      first = _mm256_permute2f128_pd(first, first, 1);\n    }\n    else if (Offset==3)\n    {\n      first = _mm256_blend_pd(first, second, 7);\n      __m256d tmp = _mm256_permute_pd(first, 5);\n      first = _mm256_permute2f128_pd(tmp, tmp, 1);\n      first = _mm256_blend_pd(tmp, first, 5);\n    }\n  }\n};\n\nEIGEN_DEVICE_FUNC inline void\nptranspose(PacketBlock<Packet8f,8>& kernel) {\n  __m256 T0 = _mm256_unpacklo_ps(kernel.packet[0], kernel.packet[1]);\n  __m256 T1 = _mm256_unpackhi_ps(kernel.packet[0], kernel.packet[1]);\n  __m256 T2 = _mm256_unpacklo_ps(kernel.packet[2], kernel.packet[3]);\n  __m256 T3 = _mm256_unpackhi_ps(kernel.packet[2], kernel.packet[3]);\n  __m256 T4 = _mm256_unpacklo_ps(kernel.packet[4], kernel.packet[5]);\n  __m256 T5 = _mm256_unpackhi_ps(kernel.packet[4], kernel.packet[5]);\n  __m256 T6 = _mm256_unpacklo_ps(kernel.packet[6], kernel.packet[7]);\n  __m256 T7 = _mm256_unpackhi_ps(kernel.packet[6], kernel.packet[7]);\n  __m256 S0 = _mm256_shuffle_ps(T0,T2,_MM_SHUFFLE(1,0,1,0));\n  __m256 S1 = _mm256_shuffle_ps(T0,T2,_MM_SHUFFLE(3,2,3,2));\n  __m256 S2 = _mm256_shuffle_ps(T1,T3,_MM_SHUFFLE(1,0,1,0));\n  __m256 S3 = _mm256_shuffle_ps(T1,T3,_MM_SHUFFLE(3,2,3,2));\n  __m256 S4 = _mm256_shuffle_ps(T4,T6,_MM_SHUFFLE(1,0,1,0));\n  __m256 S5 = _mm256_shuffle_ps(T4,T6,_MM_SHUFFLE(3,2,3,2));\n  __m256 S6 = _mm256_shuffle_ps(T5,T7,_MM_SHUFFLE(1,0,1,0));\n  __m256 S7 = _mm256_shuffle_ps(T5,T7,_MM_SHUFFLE(3,2,3,2));\n  kernel.packet[0] = _mm256_permute2f128_ps(S0, S4, 0x20);\n  kernel.packet[1] = _mm256_permute2f128_ps(S1, S5, 0x20);\n  kernel.packet[2] = _mm256_permute2f128_ps(S2, S6, 0x20);\n  kernel.packet[3] = _mm256_permute2f128_ps(S3, S7, 0x20);\n  kernel.packet[4] = _mm256_permute2f128_ps(S0, S4, 0x31);\n  kernel.packet[5] = _mm256_permute2f128_ps(S1, S5, 0x31);\n  kernel.packet[6] = _mm256_permute2f128_ps(S2, S6, 0x31);\n  kernel.packet[7] = _mm256_permute2f128_ps(S3, S7, 0x31);\n}\n\nEIGEN_DEVICE_FUNC inline void\nptranspose(PacketBlock<Packet8f,4>& kernel) {\n  __m256 T0 = _mm256_unpacklo_ps(kernel.packet[0], kernel.packet[1]);\n  __m256 T1 = _mm256_unpackhi_ps(kernel.packet[0], kernel.packet[1]);\n  __m256 T2 = _mm256_unpacklo_ps(kernel.packet[2], kernel.packet[3]);\n  __m256 T3 = _mm256_unpackhi_ps(kernel.packet[2], kernel.packet[3]);\n\n  __m256 S0 = _mm256_shuffle_ps(T0,T2,_MM_SHUFFLE(1,0,1,0));\n  __m256 S1 = _mm256_shuffle_ps(T0,T2,_MM_SHUFFLE(3,2,3,2));\n  __m256 S2 = _mm256_shuffle_ps(T1,T3,_MM_SHUFFLE(1,0,1,0));\n  __m256 S3 = _mm256_shuffle_ps(T1,T3,_MM_SHUFFLE(3,2,3,2));\n\n  kernel.packet[0] = _mm256_permute2f128_ps(S0, S1, 0x20);\n  kernel.packet[1] = _mm256_permute2f128_ps(S2, S3, 0x20);\n  kernel.packet[2] = _mm256_permute2f128_ps(S0, S1, 0x31);\n  kernel.packet[3] = _mm256_permute2f128_ps(S2, S3, 0x31);\n}\n\nEIGEN_DEVICE_FUNC inline void\nptranspose(PacketBlock<Packet4d,4>& kernel) {\n  __m256d T0 = _mm256_shuffle_pd(kernel.packet[0], kernel.packet[1], 15);\n  __m256d T1 = _mm256_shuffle_pd(kernel.packet[0], kernel.packet[1], 0);\n  __m256d T2 = _mm256_shuffle_pd(kernel.packet[2], kernel.packet[3], 15);\n  __m256d T3 = _mm256_shuffle_pd(kernel.packet[2], kernel.packet[3], 0);\n\n  kernel.packet[1] = _mm256_permute2f128_pd(T0, T2, 32);\n  kernel.packet[3] = _mm256_permute2f128_pd(T0, T2, 49);\n  kernel.packet[0] = _mm256_permute2f128_pd(T1, T3, 32);\n  kernel.packet[2] = _mm256_permute2f128_pd(T1, T3, 49);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet8f pblend(const Selector<8>& ifPacket, const Packet8f& thenPacket, const Packet8f& elsePacket) {\n  const __m256 zero = _mm256_setzero_ps();\n  const __m256 select = _mm256_set_ps(ifPacket.select[7], ifPacket.select[6], ifPacket.select[5], ifPacket.select[4], ifPacket.select[3], ifPacket.select[2], ifPacket.select[1], ifPacket.select[0]);\n  __m256 false_mask = _mm256_cmp_ps(select, zero, _CMP_EQ_UQ);\n  return _mm256_blendv_ps(thenPacket, elsePacket, false_mask);\n}\ntemplate<> EIGEN_STRONG_INLINE Packet4d pblend(const Selector<4>& ifPacket, const Packet4d& thenPacket, const Packet4d& elsePacket) {\n  const __m256d zero = _mm256_setzero_pd();\n  const __m256d select = _mm256_set_pd(ifPacket.select[3], ifPacket.select[2], ifPacket.select[1], ifPacket.select[0]);\n  __m256d false_mask = _mm256_cmp_pd(select, zero, _CMP_EQ_UQ);\n  return _mm256_blendv_pd(thenPacket, elsePacket, false_mask);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet8f pinsertfirst(const Packet8f& a, float b)\n{\n  return _mm256_blend_ps(a,pset1<Packet8f>(b),1);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4d pinsertfirst(const Packet4d& a, double b)\n{\n  return _mm256_blend_pd(a,pset1<Packet4d>(b),1);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet8f pinsertlast(const Packet8f& a, float b)\n{\n  return _mm256_blend_ps(a,pset1<Packet8f>(b),(1<<7));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4d pinsertlast(const Packet4d& a, double b)\n{\n  return _mm256_blend_pd(a,pset1<Packet4d>(b),(1<<3));\n}\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_PACKET_MATH_AVX_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/arch/AVX/TypeCasting.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2015 Benoit Steiner <benoit.steiner.goog@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_TYPE_CASTING_AVX_H\n#define EIGEN_TYPE_CASTING_AVX_H\n\nnamespace Eigen {\n\nnamespace internal {\n\n// For now we use SSE to handle integers, so we can't use AVX instructions to cast\n// from int to float\ntemplate <>\nstruct type_casting_traits<float, int> {\n  enum {\n    VectorizedCast = 0,\n    SrcCoeffRatio = 1,\n    TgtCoeffRatio = 1\n  };\n};\n\ntemplate <>\nstruct type_casting_traits<int, float> {\n  enum {\n    VectorizedCast = 0,\n    SrcCoeffRatio = 1,\n    TgtCoeffRatio = 1\n  };\n};\n\n\n\ntemplate<> EIGEN_STRONG_INLINE Packet8i pcast<Packet8f, Packet8i>(const Packet8f& a) {\n  return _mm256_cvtps_epi32(a);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet8f pcast<Packet8i, Packet8f>(const Packet8i& a) {\n  return _mm256_cvtepi32_ps(a);\n}\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_TYPE_CASTING_AVX_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/arch/AVX512/MathFunctions.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2016 Pedro Gonnet (pedro.gonnet@gmail.com)\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef THIRD_PARTY_EIGEN3_EIGEN_SRC_CORE_ARCH_AVX512_MATHFUNCTIONS_H_\n#define THIRD_PARTY_EIGEN3_EIGEN_SRC_CORE_ARCH_AVX512_MATHFUNCTIONS_H_\n\nnamespace Eigen {\n\nnamespace internal {\n\n// Disable the code for older versions of gcc that don't support many of the required avx512 instrinsics.\n#if EIGEN_GNUC_AT_LEAST(5, 3)\n\n#define _EIGEN_DECLARE_CONST_Packet16f(NAME, X) \\\n  const Packet16f p16f_##NAME = pset1<Packet16f>(X)\n\n#define _EIGEN_DECLARE_CONST_Packet16f_FROM_INT(NAME, X) \\\n  const Packet16f p16f_##NAME = (__m512)pset1<Packet16i>(X)\n\n#define _EIGEN_DECLARE_CONST_Packet8d(NAME, X) \\\n  const Packet8d p8d_##NAME = pset1<Packet8d>(X)\n\n#define _EIGEN_DECLARE_CONST_Packet8d_FROM_INT64(NAME, X) \\\n  const Packet8d p8d_##NAME = _mm512_castsi512_pd(_mm512_set1_epi64(X))\n\n// Natural logarithm\n// Computes log(x) as log(2^e * m) = C*e + log(m), where the constant C =log(2)\n// and m is in the range [sqrt(1/2),sqrt(2)). In this range, the logarithm can\n// be easily approximated by a polynomial centered on m=1 for stability.\n#if defined(EIGEN_VECTORIZE_AVX512DQ)\ntemplate <>\nEIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED Packet16f\nplog<Packet16f>(const Packet16f& _x) {\n  Packet16f x = _x;\n  _EIGEN_DECLARE_CONST_Packet16f(1, 1.0f);\n  _EIGEN_DECLARE_CONST_Packet16f(half, 0.5f);\n  _EIGEN_DECLARE_CONST_Packet16f(126f, 126.0f);\n\n  _EIGEN_DECLARE_CONST_Packet16f_FROM_INT(inv_mant_mask, ~0x7f800000);\n\n  // The smallest non denormalized float number.\n  _EIGEN_DECLARE_CONST_Packet16f_FROM_INT(min_norm_pos, 0x00800000);\n  _EIGEN_DECLARE_CONST_Packet16f_FROM_INT(minus_inf, 0xff800000);\n  _EIGEN_DECLARE_CONST_Packet16f_FROM_INT(nan, 0x7fc00000);\n\n  // Polynomial coefficients.\n  _EIGEN_DECLARE_CONST_Packet16f(cephes_SQRTHF, 0.707106781186547524f);\n  _EIGEN_DECLARE_CONST_Packet16f(cephes_log_p0, 7.0376836292E-2f);\n  _EIGEN_DECLARE_CONST_Packet16f(cephes_log_p1, -1.1514610310E-1f);\n  _EIGEN_DECLARE_CONST_Packet16f(cephes_log_p2, 1.1676998740E-1f);\n  _EIGEN_DECLARE_CONST_Packet16f(cephes_log_p3, -1.2420140846E-1f);\n  _EIGEN_DECLARE_CONST_Packet16f(cephes_log_p4, +1.4249322787E-1f);\n  _EIGEN_DECLARE_CONST_Packet16f(cephes_log_p5, -1.6668057665E-1f);\n  _EIGEN_DECLARE_CONST_Packet16f(cephes_log_p6, +2.0000714765E-1f);\n  _EIGEN_DECLARE_CONST_Packet16f(cephes_log_p7, -2.4999993993E-1f);\n  _EIGEN_DECLARE_CONST_Packet16f(cephes_log_p8, +3.3333331174E-1f);\n  _EIGEN_DECLARE_CONST_Packet16f(cephes_log_q1, -2.12194440e-4f);\n  _EIGEN_DECLARE_CONST_Packet16f(cephes_log_q2, 0.693359375f);\n\n  // invalid_mask is set to true when x is NaN\n  __mmask16 invalid_mask =\n      _mm512_cmp_ps_mask(x, _mm512_setzero_ps(), _CMP_NGE_UQ);\n  __mmask16 iszero_mask =\n      _mm512_cmp_ps_mask(x, _mm512_setzero_ps(), _CMP_EQ_UQ);\n\n  // Truncate input values to the minimum positive normal.\n  x = pmax(x, p16f_min_norm_pos);\n\n  // Extract the shifted exponents.\n  Packet16f emm0 = _mm512_cvtepi32_ps(_mm512_srli_epi32((__m512i)x, 23));\n  Packet16f e = _mm512_sub_ps(emm0, p16f_126f);\n\n  // Set the exponents to -1, i.e. x are in the range [0.5,1).\n  x = _mm512_and_ps(x, p16f_inv_mant_mask);\n  x = _mm512_or_ps(x, p16f_half);\n\n  // part2: Shift the inputs from the range [0.5,1) to [sqrt(1/2),sqrt(2))\n  // and shift by -1. The values are then centered around 0, which improves\n  // the stability of the polynomial evaluation.\n  //   if( x < SQRTHF ) {\n  //     e -= 1;\n  //     x = x + x - 1.0;\n  //   } else { x = x - 1.0; }\n  __mmask16 mask = _mm512_cmp_ps_mask(x, p16f_cephes_SQRTHF, _CMP_LT_OQ);\n  Packet16f tmp = _mm512_mask_blend_ps(mask, x, _mm512_setzero_ps());\n  x = psub(x, p16f_1);\n  e = psub(e, _mm512_mask_blend_ps(mask, p16f_1, _mm512_setzero_ps()));\n  x = padd(x, tmp);\n\n  Packet16f x2 = pmul(x, x);\n  Packet16f x3 = pmul(x2, x);\n\n  // Evaluate the polynomial approximant of degree 8 in three parts, probably\n  // to improve instruction-level parallelism.\n  Packet16f y, y1, y2;\n  y = pmadd(p16f_cephes_log_p0, x, p16f_cephes_log_p1);\n  y1 = pmadd(p16f_cephes_log_p3, x, p16f_cephes_log_p4);\n  y2 = pmadd(p16f_cephes_log_p6, x, p16f_cephes_log_p7);\n  y = pmadd(y, x, p16f_cephes_log_p2);\n  y1 = pmadd(y1, x, p16f_cephes_log_p5);\n  y2 = pmadd(y2, x, p16f_cephes_log_p8);\n  y = pmadd(y, x3, y1);\n  y = pmadd(y, x3, y2);\n  y = pmul(y, x3);\n\n  // Add the logarithm of the exponent back to the result of the interpolation.\n  y1 = pmul(e, p16f_cephes_log_q1);\n  tmp = pmul(x2, p16f_half);\n  y = padd(y, y1);\n  x = psub(x, tmp);\n  y2 = pmul(e, p16f_cephes_log_q2);\n  x = padd(x, y);\n  x = padd(x, y2);\n\n  // Filter out invalid inputs, i.e. negative arg will be NAN, 0 will be -INF.\n  return _mm512_mask_blend_ps(iszero_mask, p16f_minus_inf,\n                              _mm512_mask_blend_ps(invalid_mask, p16f_nan, x));\n}\n#endif\n\n// Exponential function. Works by writing \"x = m*log(2) + r\" where\n// \"m = floor(x/log(2)+1/2)\" and \"r\" is the remainder. The result is then\n// \"exp(x) = 2^m*exp(r)\" where exp(r) is in the range [-1,1).\ntemplate <>\nEIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED Packet16f\npexp<Packet16f>(const Packet16f& _x) {\n  _EIGEN_DECLARE_CONST_Packet16f(1, 1.0f);\n  _EIGEN_DECLARE_CONST_Packet16f(half, 0.5f);\n  _EIGEN_DECLARE_CONST_Packet16f(127, 127.0f);\n\n  _EIGEN_DECLARE_CONST_Packet16f(exp_hi, 88.3762626647950f);\n  _EIGEN_DECLARE_CONST_Packet16f(exp_lo, -88.3762626647949f);\n\n  _EIGEN_DECLARE_CONST_Packet16f(cephes_LOG2EF, 1.44269504088896341f);\n\n  _EIGEN_DECLARE_CONST_Packet16f(cephes_exp_p0, 1.9875691500E-4f);\n  _EIGEN_DECLARE_CONST_Packet16f(cephes_exp_p1, 1.3981999507E-3f);\n  _EIGEN_DECLARE_CONST_Packet16f(cephes_exp_p2, 8.3334519073E-3f);\n  _EIGEN_DECLARE_CONST_Packet16f(cephes_exp_p3, 4.1665795894E-2f);\n  _EIGEN_DECLARE_CONST_Packet16f(cephes_exp_p4, 1.6666665459E-1f);\n  _EIGEN_DECLARE_CONST_Packet16f(cephes_exp_p5, 5.0000001201E-1f);\n\n  // Clamp x.\n  Packet16f x = pmax(pmin(_x, p16f_exp_hi), p16f_exp_lo);\n\n  // Express exp(x) as exp(m*ln(2) + r), start by extracting\n  // m = floor(x/ln(2) + 0.5).\n  Packet16f m = _mm512_floor_ps(pmadd(x, p16f_cephes_LOG2EF, p16f_half));\n\n  // Get r = x - m*ln(2). Note that we can do this without losing more than one\n  // ulp precision due to the FMA instruction.\n  _EIGEN_DECLARE_CONST_Packet16f(nln2, -0.6931471805599453f);\n  Packet16f r = _mm512_fmadd_ps(m, p16f_nln2, x);\n  Packet16f r2 = pmul(r, r);\n\n  // TODO(gonnet): Split into odd/even polynomials and try to exploit\n  //               instruction-level parallelism.\n  Packet16f y = p16f_cephes_exp_p0;\n  y = pmadd(y, r, p16f_cephes_exp_p1);\n  y = pmadd(y, r, p16f_cephes_exp_p2);\n  y = pmadd(y, r, p16f_cephes_exp_p3);\n  y = pmadd(y, r, p16f_cephes_exp_p4);\n  y = pmadd(y, r, p16f_cephes_exp_p5);\n  y = pmadd(y, r2, r);\n  y = padd(y, p16f_1);\n\n  // Build emm0 = 2^m.\n  Packet16i emm0 = _mm512_cvttps_epi32(padd(m, p16f_127));\n  emm0 = _mm512_slli_epi32(emm0, 23);\n\n  // Return 2^m * exp(r).\n  return pmax(pmul(y, _mm512_castsi512_ps(emm0)), _x);\n}\n\n/*template <>\nEIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED Packet8d\npexp<Packet8d>(const Packet8d& _x) {\n  Packet8d x = _x;\n\n  _EIGEN_DECLARE_CONST_Packet8d(1, 1.0);\n  _EIGEN_DECLARE_CONST_Packet8d(2, 2.0);\n\n  _EIGEN_DECLARE_CONST_Packet8d(exp_hi, 709.437);\n  _EIGEN_DECLARE_CONST_Packet8d(exp_lo, -709.436139303);\n\n  _EIGEN_DECLARE_CONST_Packet8d(cephes_LOG2EF, 1.4426950408889634073599);\n\n  _EIGEN_DECLARE_CONST_Packet8d(cephes_exp_p0, 1.26177193074810590878e-4);\n  _EIGEN_DECLARE_CONST_Packet8d(cephes_exp_p1, 3.02994407707441961300e-2);\n  _EIGEN_DECLARE_CONST_Packet8d(cephes_exp_p2, 9.99999999999999999910e-1);\n\n  _EIGEN_DECLARE_CONST_Packet8d(cephes_exp_q0, 3.00198505138664455042e-6);\n  _EIGEN_DECLARE_CONST_Packet8d(cephes_exp_q1, 2.52448340349684104192e-3);\n  _EIGEN_DECLARE_CONST_Packet8d(cephes_exp_q2, 2.27265548208155028766e-1);\n  _EIGEN_DECLARE_CONST_Packet8d(cephes_exp_q3, 2.00000000000000000009e0);\n\n  _EIGEN_DECLARE_CONST_Packet8d(cephes_exp_C1, 0.693145751953125);\n  _EIGEN_DECLARE_CONST_Packet8d(cephes_exp_C2, 1.42860682030941723212e-6);\n\n  // clamp x\n  x = pmax(pmin(x, p8d_exp_hi), p8d_exp_lo);\n\n  // Express exp(x) as exp(g + n*log(2)).\n  const Packet8d n =\n      _mm512_mul_round_pd(p8d_cephes_LOG2EF, x, _MM_FROUND_TO_NEAREST_INT);\n\n  // Get the remainder modulo log(2), i.e. the \"g\" described above. Subtract\n  // n*log(2) out in two steps, i.e. n*C1 + n*C2, C1+C2=log2 to get the last\n  // digits right.\n  const Packet8d nC1 = pmul(n, p8d_cephes_exp_C1);\n  const Packet8d nC2 = pmul(n, p8d_cephes_exp_C2);\n  x = psub(x, nC1);\n  x = psub(x, nC2);\n\n  const Packet8d x2 = pmul(x, x);\n\n  // Evaluate the numerator polynomial of the rational interpolant.\n  Packet8d px = p8d_cephes_exp_p0;\n  px = pmadd(px, x2, p8d_cephes_exp_p1);\n  px = pmadd(px, x2, p8d_cephes_exp_p2);\n  px = pmul(px, x);\n\n  // Evaluate the denominator polynomial of the rational interpolant.\n  Packet8d qx = p8d_cephes_exp_q0;\n  qx = pmadd(qx, x2, p8d_cephes_exp_q1);\n  qx = pmadd(qx, x2, p8d_cephes_exp_q2);\n  qx = pmadd(qx, x2, p8d_cephes_exp_q3);\n\n  // I don't really get this bit, copied from the SSE2 routines, so...\n  // TODO(gonnet): Figure out what is going on here, perhaps find a better\n  // rational interpolant?\n  x = _mm512_div_pd(px, psub(qx, px));\n  x = pmadd(p8d_2, x, p8d_1);\n\n  // Build e=2^n.\n  const Packet8d e = _mm512_castsi512_pd(_mm512_slli_epi64(\n      _mm512_add_epi64(_mm512_cvtpd_epi64(n), _mm512_set1_epi64(1023)), 52));\n\n  // Construct the result 2^n * exp(g) = e * x. The max is used to catch\n  // non-finite values in the input.\n  return pmax(pmul(x, e), _x);\n  }*/\n\n// Functions for sqrt.\n// The EIGEN_FAST_MATH version uses the _mm_rsqrt_ps approximation and one step\n// of Newton's method, at a cost of 1-2 bits of precision as opposed to the\n// exact solution. The main advantage of this approach is not just speed, but\n// also the fact that it can be inlined and pipelined with other computations,\n// further reducing its effective latency.\n#if EIGEN_FAST_MATH\ntemplate <>\nEIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED Packet16f\npsqrt<Packet16f>(const Packet16f& _x) {\n  _EIGEN_DECLARE_CONST_Packet16f(one_point_five, 1.5f);\n  _EIGEN_DECLARE_CONST_Packet16f(minus_half, -0.5f);\n  _EIGEN_DECLARE_CONST_Packet16f_FROM_INT(flt_min, 0x00800000);\n\n  Packet16f neg_half = pmul(_x, p16f_minus_half);\n\n  // select only the inverse sqrt of positive normal inputs (denormals are\n  // flushed to zero and cause infs as well).\n  __mmask16 non_zero_mask = _mm512_cmp_ps_mask(_x, p16f_flt_min, _CMP_GE_OQ);\n  Packet16f x = _mm512_mask_blend_ps(non_zero_mask, _mm512_rsqrt14_ps(_x),\n                                     _mm512_setzero_ps());\n\n  // Do a single step of Newton's iteration.\n  x = pmul(x, pmadd(neg_half, pmul(x, x), p16f_one_point_five));\n\n  // Multiply the original _x by it's reciprocal square root to extract the\n  // square root.\n  return pmul(_x, x);\n}\n\ntemplate <>\nEIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED Packet8d\npsqrt<Packet8d>(const Packet8d& _x) {\n  _EIGEN_DECLARE_CONST_Packet8d(one_point_five, 1.5);\n  _EIGEN_DECLARE_CONST_Packet8d(minus_half, -0.5);\n  _EIGEN_DECLARE_CONST_Packet8d_FROM_INT64(dbl_min, 0x0010000000000000LL);\n\n  Packet8d neg_half = pmul(_x, p8d_minus_half);\n\n  // select only the inverse sqrt of positive normal inputs (denormals are\n  // flushed to zero and cause infs as well).\n  __mmask8 non_zero_mask = _mm512_cmp_pd_mask(_x, p8d_dbl_min, _CMP_GE_OQ);\n  Packet8d x = _mm512_mask_blend_pd(non_zero_mask, _mm512_rsqrt14_pd(_x),\n                                    _mm512_setzero_pd());\n\n  // Do a first step of Newton's iteration.\n  x = pmul(x, pmadd(neg_half, pmul(x, x), p8d_one_point_five));\n\n  // Do a second step of Newton's iteration.\n  x = pmul(x, pmadd(neg_half, pmul(x, x), p8d_one_point_five));\n\n  // Multiply the original _x by it's reciprocal square root to extract the\n  // square root.\n  return pmul(_x, x);\n}\n#else\ntemplate <>\nEIGEN_STRONG_INLINE Packet16f psqrt<Packet16f>(const Packet16f& x) {\n  return _mm512_sqrt_ps(x);\n}\ntemplate <>\nEIGEN_STRONG_INLINE Packet8d psqrt<Packet8d>(const Packet8d& x) {\n  return _mm512_sqrt_pd(x);\n}\n#endif\n\n// Functions for rsqrt.\n// Almost identical to the sqrt routine, just leave out the last multiplication\n// and fill in NaN/Inf where needed. Note that this function only exists as an\n// iterative version for doubles since there is no instruction for diretly\n// computing the reciprocal square root in AVX-512.\n#ifdef EIGEN_FAST_MATH\ntemplate <>\nEIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED Packet16f\nprsqrt<Packet16f>(const Packet16f& _x) {\n  _EIGEN_DECLARE_CONST_Packet16f_FROM_INT(inf, 0x7f800000);\n  _EIGEN_DECLARE_CONST_Packet16f_FROM_INT(nan, 0x7fc00000);\n  _EIGEN_DECLARE_CONST_Packet16f(one_point_five, 1.5f);\n  _EIGEN_DECLARE_CONST_Packet16f(minus_half, -0.5f);\n  _EIGEN_DECLARE_CONST_Packet16f_FROM_INT(flt_min, 0x00800000);\n\n  Packet16f neg_half = pmul(_x, p16f_minus_half);\n\n  // select only the inverse sqrt of positive normal inputs (denormals are\n  // flushed to zero and cause infs as well).\n  __mmask16 le_zero_mask = _mm512_cmp_ps_mask(_x, p16f_flt_min, _CMP_LT_OQ);\n  Packet16f x = _mm512_mask_blend_ps(le_zero_mask, _mm512_setzero_ps(),\n                                     _mm512_rsqrt14_ps(_x));\n\n  // Fill in NaNs and Infs for the negative/zero entries.\n  __mmask16 neg_mask = _mm512_cmp_ps_mask(_x, _mm512_setzero_ps(), _CMP_LT_OQ);\n  Packet16f infs_and_nans = _mm512_mask_blend_ps(\n      neg_mask, p16f_nan,\n      _mm512_mask_blend_ps(le_zero_mask, p16f_inf, _mm512_setzero_ps()));\n\n  // Do a single step of Newton's iteration.\n  x = pmul(x, pmadd(neg_half, pmul(x, x), p16f_one_point_five));\n\n  // Insert NaNs and Infs in all the right places.\n  return _mm512_mask_blend_ps(le_zero_mask, infs_and_nans, x);\n}\n\ntemplate <>\nEIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED Packet8d\nprsqrt<Packet8d>(const Packet8d& _x) {\n  _EIGEN_DECLARE_CONST_Packet8d_FROM_INT64(inf, 0x7ff0000000000000LL);\n  _EIGEN_DECLARE_CONST_Packet8d_FROM_INT64(nan, 0x7ff1000000000000LL);\n  _EIGEN_DECLARE_CONST_Packet8d(one_point_five, 1.5);\n  _EIGEN_DECLARE_CONST_Packet8d(minus_half, -0.5);\n  _EIGEN_DECLARE_CONST_Packet8d_FROM_INT64(dbl_min, 0x0010000000000000LL);\n\n  Packet8d neg_half = pmul(_x, p8d_minus_half);\n\n  // select only the inverse sqrt of positive normal inputs (denormals are\n  // flushed to zero and cause infs as well).\n  __mmask8 le_zero_mask = _mm512_cmp_pd_mask(_x, p8d_dbl_min, _CMP_LT_OQ);\n  Packet8d x = _mm512_mask_blend_pd(le_zero_mask, _mm512_setzero_pd(),\n                                    _mm512_rsqrt14_pd(_x));\n\n  // Fill in NaNs and Infs for the negative/zero entries.\n  __mmask8 neg_mask = _mm512_cmp_pd_mask(_x, _mm512_setzero_pd(), _CMP_LT_OQ);\n  Packet8d infs_and_nans = _mm512_mask_blend_pd(\n      neg_mask, p8d_nan,\n      _mm512_mask_blend_pd(le_zero_mask, p8d_inf, _mm512_setzero_pd()));\n\n  // Do a first step of Newton's iteration.\n  x = pmul(x, pmadd(neg_half, pmul(x, x), p8d_one_point_five));\n\n  // Do a second step of Newton's iteration.\n  x = pmul(x, pmadd(neg_half, pmul(x, x), p8d_one_point_five));\n\n  // Insert NaNs and Infs in all the right places.\n  return _mm512_mask_blend_pd(le_zero_mask, infs_and_nans, x);\n}\n#else\ntemplate <>\nEIGEN_STRONG_INLINE Packet16f prsqrt<Packet16f>(const Packet16f& x) {\n  return _mm512_rsqrt28_ps(x);\n}\n#endif\n#endif\n\n}  // end namespace internal\n\n}  // end namespace Eigen\n\n#endif  // THIRD_PARTY_EIGEN3_EIGEN_SRC_CORE_ARCH_AVX512_MATHFUNCTIONS_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/arch/AVX512/PacketMath.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2016 Benoit Steiner (benoit.steiner.goog@gmail.com)\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_PACKET_MATH_AVX512_H\n#define EIGEN_PACKET_MATH_AVX512_H\n\nnamespace Eigen {\n\nnamespace internal {\n\n#ifndef EIGEN_CACHEFRIENDLY_PRODUCT_THRESHOLD\n#define EIGEN_CACHEFRIENDLY_PRODUCT_THRESHOLD 8\n#endif\n\n#ifndef EIGEN_ARCH_DEFAULT_NUMBER_OF_REGISTERS\n#define EIGEN_ARCH_DEFAULT_NUMBER_OF_REGISTERS (2*sizeof(void*))\n#endif\n\n#ifdef __FMA__\n#ifndef EIGEN_HAS_SINGLE_INSTRUCTION_MADD\n#define EIGEN_HAS_SINGLE_INSTRUCTION_MADD\n#endif\n#endif\n\ntypedef __m512 Packet16f;\ntypedef __m512i Packet16i;\ntypedef __m512d Packet8d;\n\ntemplate <>\nstruct is_arithmetic<__m512> {\n  enum { value = true };\n};\ntemplate <>\nstruct is_arithmetic<__m512i> {\n  enum { value = true };\n};\ntemplate <>\nstruct is_arithmetic<__m512d> {\n  enum { value = true };\n};\n\ntemplate<> struct packet_traits<float>  : default_packet_traits\n{\n  typedef Packet16f type;\n  typedef Packet8f half;\n  enum {\n    Vectorizable = 1,\n    AlignedOnScalar = 1,\n    size = 16,\n    HasHalfPacket = 1,\n#if EIGEN_GNUC_AT_LEAST(5, 3)\n#ifdef EIGEN_VECTORIZE_AVX512DQ\n    HasLog = 1,\n#endif\n    HasExp = 1,\n    HasSqrt = 1,\n    HasRsqrt = 1,\n#endif\n    HasDiv = 1\n  };\n };\ntemplate<> struct packet_traits<double> : default_packet_traits\n{\n  typedef Packet8d type;\n  typedef Packet4d half;\n  enum {\n    Vectorizable = 1,\n    AlignedOnScalar = 1,\n    size = 8,\n    HasHalfPacket = 1,\n#if EIGEN_GNUC_AT_LEAST(5, 3)\n    HasSqrt = 1,\n    HasRsqrt = EIGEN_FAST_MATH,\n#endif\n    HasDiv = 1\n  };\n};\n\n/* TODO Implement AVX512 for integers\ntemplate<> struct packet_traits<int>    : default_packet_traits\n{\n  typedef Packet16i type;\n  enum {\n    Vectorizable = 1,\n    AlignedOnScalar = 1,\n    size=8\n  };\n};\n*/\n\ntemplate <>\nstruct unpacket_traits<Packet16f> {\n  typedef float type;\n  typedef Packet8f half;\n  enum { size = 16, alignment=Aligned64 };\n};\ntemplate <>\nstruct unpacket_traits<Packet8d> {\n  typedef double type;\n  typedef Packet4d half;\n  enum { size = 8, alignment=Aligned64 };\n};\ntemplate <>\nstruct unpacket_traits<Packet16i> {\n  typedef int type;\n  typedef Packet8i half;\n  enum { size = 16, alignment=Aligned64 };\n};\n\ntemplate <>\nEIGEN_STRONG_INLINE Packet16f pset1<Packet16f>(const float& from) {\n  return _mm512_set1_ps(from);\n}\ntemplate <>\nEIGEN_STRONG_INLINE Packet8d pset1<Packet8d>(const double& from) {\n  return _mm512_set1_pd(from);\n}\ntemplate <>\nEIGEN_STRONG_INLINE Packet16i pset1<Packet16i>(const int& from) {\n  return _mm512_set1_epi32(from);\n}\n\ntemplate <>\nEIGEN_STRONG_INLINE Packet16f pload1<Packet16f>(const float* from) {\n  return _mm512_broadcastss_ps(_mm_load_ps1(from));\n}\ntemplate <>\nEIGEN_STRONG_INLINE Packet8d pload1<Packet8d>(const double* from) {\n  return _mm512_broadcastsd_pd(_mm_load_pd1(from));\n}\n\ntemplate <>\nEIGEN_STRONG_INLINE Packet16f plset<Packet16f>(const float& a) {\n  return _mm512_add_ps(\n      _mm512_set1_ps(a),\n      _mm512_set_ps(15.0f, 14.0f, 13.0f, 12.0f, 11.0f, 10.0f, 9.0f, 8.0f, 7.0f, 6.0f, 5.0f,\n                    4.0f, 3.0f, 2.0f, 1.0f, 0.0f));\n}\ntemplate <>\nEIGEN_STRONG_INLINE Packet8d plset<Packet8d>(const double& a) {\n  return _mm512_add_pd(_mm512_set1_pd(a),\n                       _mm512_set_pd(7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0, 0.0));\n}\n\ntemplate <>\nEIGEN_STRONG_INLINE Packet16f padd<Packet16f>(const Packet16f& a,\n                                              const Packet16f& b) {\n  return _mm512_add_ps(a, b);\n}\ntemplate <>\nEIGEN_STRONG_INLINE Packet8d padd<Packet8d>(const Packet8d& a,\n                                            const Packet8d& b) {\n  return _mm512_add_pd(a, b);\n}\n\ntemplate <>\nEIGEN_STRONG_INLINE Packet16f psub<Packet16f>(const Packet16f& a,\n                                              const Packet16f& b) {\n  return _mm512_sub_ps(a, b);\n}\ntemplate <>\nEIGEN_STRONG_INLINE Packet8d psub<Packet8d>(const Packet8d& a,\n                                            const Packet8d& b) {\n  return _mm512_sub_pd(a, b);\n}\n\ntemplate <>\nEIGEN_STRONG_INLINE Packet16f pnegate(const Packet16f& a) {\n  return _mm512_sub_ps(_mm512_set1_ps(0.0), a);\n}\ntemplate <>\nEIGEN_STRONG_INLINE Packet8d pnegate(const Packet8d& a) {\n  return _mm512_sub_pd(_mm512_set1_pd(0.0), a);\n}\n\ntemplate <>\nEIGEN_STRONG_INLINE Packet16f pconj(const Packet16f& a) {\n  return a;\n}\ntemplate <>\nEIGEN_STRONG_INLINE Packet8d pconj(const Packet8d& a) {\n  return a;\n}\ntemplate <>\nEIGEN_STRONG_INLINE Packet16i pconj(const Packet16i& a) {\n  return a;\n}\n\ntemplate <>\nEIGEN_STRONG_INLINE Packet16f pmul<Packet16f>(const Packet16f& a,\n                                              const Packet16f& b) {\n  return _mm512_mul_ps(a, b);\n}\ntemplate <>\nEIGEN_STRONG_INLINE Packet8d pmul<Packet8d>(const Packet8d& a,\n                                            const Packet8d& b) {\n  return _mm512_mul_pd(a, b);\n}\n\ntemplate <>\nEIGEN_STRONG_INLINE Packet16f pdiv<Packet16f>(const Packet16f& a,\n                                              const Packet16f& b) {\n  return _mm512_div_ps(a, b);\n}\ntemplate <>\nEIGEN_STRONG_INLINE Packet8d pdiv<Packet8d>(const Packet8d& a,\n                                            const Packet8d& b) {\n  return _mm512_div_pd(a, b);\n}\n\n#ifdef __FMA__\ntemplate <>\nEIGEN_STRONG_INLINE Packet16f pmadd(const Packet16f& a, const Packet16f& b,\n                                    const Packet16f& c) {\n  return _mm512_fmadd_ps(a, b, c);\n}\ntemplate <>\nEIGEN_STRONG_INLINE Packet8d pmadd(const Packet8d& a, const Packet8d& b,\n                                   const Packet8d& c) {\n  return _mm512_fmadd_pd(a, b, c);\n}\n#endif\n\ntemplate <>\nEIGEN_STRONG_INLINE Packet16f pmin<Packet16f>(const Packet16f& a,\n                                              const Packet16f& b) {\n  return _mm512_min_ps(a, b);\n}\ntemplate <>\nEIGEN_STRONG_INLINE Packet8d pmin<Packet8d>(const Packet8d& a,\n                                            const Packet8d& b) {\n  return _mm512_min_pd(a, b);\n}\n\ntemplate <>\nEIGEN_STRONG_INLINE Packet16f pmax<Packet16f>(const Packet16f& a,\n                                              const Packet16f& b) {\n  return _mm512_max_ps(a, b);\n}\ntemplate <>\nEIGEN_STRONG_INLINE Packet8d pmax<Packet8d>(const Packet8d& a,\n                                            const Packet8d& b) {\n  return _mm512_max_pd(a, b);\n}\n\ntemplate <>\nEIGEN_STRONG_INLINE Packet16f pand<Packet16f>(const Packet16f& a,\n                                              const Packet16f& b) {\n#ifdef EIGEN_VECTORIZE_AVX512DQ\n  return _mm512_and_ps(a, b);\n#else\n  Packet16f res = _mm512_undefined_ps();\n  Packet4f lane0_a = _mm512_extractf32x4_ps(a, 0);\n  Packet4f lane0_b = _mm512_extractf32x4_ps(b, 0);\n  res = _mm512_insertf32x4(res, _mm_and_ps(lane0_a, lane0_b), 0);\n\n  Packet4f lane1_a = _mm512_extractf32x4_ps(a, 1);\n  Packet4f lane1_b = _mm512_extractf32x4_ps(b, 1);\n  res = _mm512_insertf32x4(res, _mm_and_ps(lane1_a, lane1_b), 1);\n\n  Packet4f lane2_a = _mm512_extractf32x4_ps(a, 2);\n  Packet4f lane2_b = _mm512_extractf32x4_ps(b, 2);\n  res = _mm512_insertf32x4(res, _mm_and_ps(lane2_a, lane2_b), 2);\n\n  Packet4f lane3_a = _mm512_extractf32x4_ps(a, 3);\n  Packet4f lane3_b = _mm512_extractf32x4_ps(b, 3);\n  res = _mm512_insertf32x4(res, _mm_and_ps(lane3_a, lane3_b), 3);\n\n  return res;\n#endif\n}\ntemplate <>\nEIGEN_STRONG_INLINE Packet8d pand<Packet8d>(const Packet8d& a,\n                                            const Packet8d& b) {\n#ifdef EIGEN_VECTORIZE_AVX512DQ\n  return _mm512_and_pd(a, b);\n#else\n  Packet8d res = _mm512_undefined_pd();\n  Packet4d lane0_a = _mm512_extractf64x4_pd(a, 0);\n  Packet4d lane0_b = _mm512_extractf64x4_pd(b, 0);\n  res = _mm512_insertf64x4(res, _mm256_and_pd(lane0_a, lane0_b), 0);\n\n  Packet4d lane1_a = _mm512_extractf64x4_pd(a, 1);\n  Packet4d lane1_b = _mm512_extractf64x4_pd(b, 1);\n  res = _mm512_insertf64x4(res, _mm256_and_pd(lane1_a, lane1_b), 1);\n\n  return res;\n#endif\n}\ntemplate <>\nEIGEN_STRONG_INLINE Packet16f por<Packet16f>(const Packet16f& a,\n                                             const Packet16f& b) {\n#ifdef EIGEN_VECTORIZE_AVX512DQ\n  return _mm512_or_ps(a, b);\n#else\n  Packet16f res = _mm512_undefined_ps();\n  Packet4f lane0_a = _mm512_extractf32x4_ps(a, 0);\n  Packet4f lane0_b = _mm512_extractf32x4_ps(b, 0);\n  res = _mm512_insertf32x4(res, _mm_or_ps(lane0_a, lane0_b), 0);\n\n  Packet4f lane1_a = _mm512_extractf32x4_ps(a, 1);\n  Packet4f lane1_b = _mm512_extractf32x4_ps(b, 1);\n  res = _mm512_insertf32x4(res, _mm_or_ps(lane1_a, lane1_b), 1);\n\n  Packet4f lane2_a = _mm512_extractf32x4_ps(a, 2);\n  Packet4f lane2_b = _mm512_extractf32x4_ps(b, 2);\n  res = _mm512_insertf32x4(res, _mm_or_ps(lane2_a, lane2_b), 2);\n\n  Packet4f lane3_a = _mm512_extractf32x4_ps(a, 3);\n  Packet4f lane3_b = _mm512_extractf32x4_ps(b, 3);\n  res = _mm512_insertf32x4(res, _mm_or_ps(lane3_a, lane3_b), 3);\n\n  return res;\n#endif\n}\n\ntemplate <>\nEIGEN_STRONG_INLINE Packet8d por<Packet8d>(const Packet8d& a,\n                                           const Packet8d& b) {\n#ifdef EIGEN_VECTORIZE_AVX512DQ\n  return _mm512_or_pd(a, b);\n#else\n  Packet8d res = _mm512_undefined_pd();\n  Packet4d lane0_a = _mm512_extractf64x4_pd(a, 0);\n  Packet4d lane0_b = _mm512_extractf64x4_pd(b, 0);\n  res = _mm512_insertf64x4(res, _mm256_or_pd(lane0_a, lane0_b), 0);\n\n  Packet4d lane1_a = _mm512_extractf64x4_pd(a, 1);\n  Packet4d lane1_b = _mm512_extractf64x4_pd(b, 1);\n  res = _mm512_insertf64x4(res, _mm256_or_pd(lane1_a, lane1_b), 1);\n\n  return res;\n#endif\n}\n\ntemplate <>\nEIGEN_STRONG_INLINE Packet16f pxor<Packet16f>(const Packet16f& a,\n                                              const Packet16f& b) {\n#ifdef EIGEN_VECTORIZE_AVX512DQ\n  return _mm512_xor_ps(a, b);\n#else\n  Packet16f res = _mm512_undefined_ps();\n  Packet4f lane0_a = _mm512_extractf32x4_ps(a, 0);\n  Packet4f lane0_b = _mm512_extractf32x4_ps(b, 0);\n  res = _mm512_insertf32x4(res, _mm_xor_ps(lane0_a, lane0_b), 0);\n\n  Packet4f lane1_a = _mm512_extractf32x4_ps(a, 1);\n  Packet4f lane1_b = _mm512_extractf32x4_ps(b, 1);\n  res = _mm512_insertf32x4(res, _mm_xor_ps(lane1_a, lane1_b), 1);\n\n  Packet4f lane2_a = _mm512_extractf32x4_ps(a, 2);\n  Packet4f lane2_b = _mm512_extractf32x4_ps(b, 2);\n  res = _mm512_insertf32x4(res, _mm_xor_ps(lane2_a, lane2_b), 2);\n\n  Packet4f lane3_a = _mm512_extractf32x4_ps(a, 3);\n  Packet4f lane3_b = _mm512_extractf32x4_ps(b, 3);\n  res = _mm512_insertf32x4(res, _mm_xor_ps(lane3_a, lane3_b), 3);\n\n  return res;\n#endif\n}\ntemplate <>\nEIGEN_STRONG_INLINE Packet8d pxor<Packet8d>(const Packet8d& a,\n                                            const Packet8d& b) {\n#ifdef EIGEN_VECTORIZE_AVX512DQ\n  return _mm512_xor_pd(a, b);\n#else\n  Packet8d res = _mm512_undefined_pd();\n  Packet4d lane0_a = _mm512_extractf64x4_pd(a, 0);\n  Packet4d lane0_b = _mm512_extractf64x4_pd(b, 0);\n  res = _mm512_insertf64x4(res, _mm256_xor_pd(lane0_a, lane0_b), 0);\n\n  Packet4d lane1_a = _mm512_extractf64x4_pd(a, 1);\n  Packet4d lane1_b = _mm512_extractf64x4_pd(b, 1);\n  res = _mm512_insertf64x4(res, _mm256_xor_pd(lane1_a, lane1_b), 1);\n\n  return res;\n#endif\n}\n\ntemplate <>\nEIGEN_STRONG_INLINE Packet16f pandnot<Packet16f>(const Packet16f& a,\n                                                 const Packet16f& b) {\n#ifdef EIGEN_VECTORIZE_AVX512DQ\n  return _mm512_andnot_ps(a, b);\n#else\n  Packet16f res = _mm512_undefined_ps();\n  Packet4f lane0_a = _mm512_extractf32x4_ps(a, 0);\n  Packet4f lane0_b = _mm512_extractf32x4_ps(b, 0);\n  res = _mm512_insertf32x4(res, _mm_andnot_ps(lane0_a, lane0_b), 0);\n\n  Packet4f lane1_a = _mm512_extractf32x4_ps(a, 1);\n  Packet4f lane1_b = _mm512_extractf32x4_ps(b, 1);\n  res = _mm512_insertf32x4(res, _mm_andnot_ps(lane1_a, lane1_b), 1);\n\n  Packet4f lane2_a = _mm512_extractf32x4_ps(a, 2);\n  Packet4f lane2_b = _mm512_extractf32x4_ps(b, 2);\n  res = _mm512_insertf32x4(res, _mm_andnot_ps(lane2_a, lane2_b), 2);\n\n  Packet4f lane3_a = _mm512_extractf32x4_ps(a, 3);\n  Packet4f lane3_b = _mm512_extractf32x4_ps(b, 3);\n  res = _mm512_insertf32x4(res, _mm_andnot_ps(lane3_a, lane3_b), 3);\n\n  return res;\n#endif\n}\ntemplate <>\nEIGEN_STRONG_INLINE Packet8d pandnot<Packet8d>(const Packet8d& a,\n                                               const Packet8d& b) {\n#ifdef EIGEN_VECTORIZE_AVX512DQ\n  return _mm512_andnot_pd(a, b);\n#else\n  Packet8d res = _mm512_undefined_pd();\n  Packet4d lane0_a = _mm512_extractf64x4_pd(a, 0);\n  Packet4d lane0_b = _mm512_extractf64x4_pd(b, 0);\n  res = _mm512_insertf64x4(res, _mm256_andnot_pd(lane0_a, lane0_b), 0);\n\n  Packet4d lane1_a = _mm512_extractf64x4_pd(a, 1);\n  Packet4d lane1_b = _mm512_extractf64x4_pd(b, 1);\n  res = _mm512_insertf64x4(res, _mm256_andnot_pd(lane1_a, lane1_b), 1);\n\n  return res;\n#endif\n}\n\ntemplate <>\nEIGEN_STRONG_INLINE Packet16f pload<Packet16f>(const float* from) {\n  EIGEN_DEBUG_ALIGNED_LOAD return _mm512_load_ps(from);\n}\ntemplate <>\nEIGEN_STRONG_INLINE Packet8d pload<Packet8d>(const double* from) {\n  EIGEN_DEBUG_ALIGNED_LOAD return _mm512_load_pd(from);\n}\ntemplate <>\nEIGEN_STRONG_INLINE Packet16i pload<Packet16i>(const int* from) {\n  EIGEN_DEBUG_ALIGNED_LOAD return _mm512_load_si512(\n      reinterpret_cast<const __m512i*>(from));\n}\n\ntemplate <>\nEIGEN_STRONG_INLINE Packet16f ploadu<Packet16f>(const float* from) {\n  EIGEN_DEBUG_UNALIGNED_LOAD return _mm512_loadu_ps(from);\n}\ntemplate <>\nEIGEN_STRONG_INLINE Packet8d ploadu<Packet8d>(const double* from) {\n  EIGEN_DEBUG_UNALIGNED_LOAD return _mm512_loadu_pd(from);\n}\ntemplate <>\nEIGEN_STRONG_INLINE Packet16i ploadu<Packet16i>(const int* from) {\n  EIGEN_DEBUG_UNALIGNED_LOAD return _mm512_loadu_si512(\n      reinterpret_cast<const __m512i*>(from));\n}\n\n// Loads 8 floats from memory a returns the packet\n// {a0, a0  a1, a1, a2, a2, a3, a3, a4, a4, a5, a5, a6, a6, a7, a7}\ntemplate <>\nEIGEN_STRONG_INLINE Packet16f ploaddup<Packet16f>(const float* from) {\n  Packet8f lane0 = _mm256_broadcast_ps((const __m128*)(const void*)from);\n  // mimic an \"inplace\" permutation of the lower 128bits using a blend\n  lane0 = _mm256_blend_ps(\n      lane0, _mm256_castps128_ps256(_mm_permute_ps(\n                 _mm256_castps256_ps128(lane0), _MM_SHUFFLE(1, 0, 1, 0))),\n      15);\n  // then we can perform a consistent permutation on the global register to get\n  // everything in shape:\n  lane0 = _mm256_permute_ps(lane0, _MM_SHUFFLE(3, 3, 2, 2));\n\n  Packet8f lane1 = _mm256_broadcast_ps((const __m128*)(const void*)(from + 4));\n  // mimic an \"inplace\" permutation of the lower 128bits using a blend\n  lane1 = _mm256_blend_ps(\n      lane1, _mm256_castps128_ps256(_mm_permute_ps(\n                 _mm256_castps256_ps128(lane1), _MM_SHUFFLE(1, 0, 1, 0))),\n      15);\n  // then we can perform a consistent permutation on the global register to get\n  // everything in shape:\n  lane1 = _mm256_permute_ps(lane1, _MM_SHUFFLE(3, 3, 2, 2));\n\n#ifdef EIGEN_VECTORIZE_AVX512DQ\n  Packet16f res = _mm512_undefined_ps();\n  return _mm512_insertf32x8(res, lane0, 0);\n  return _mm512_insertf32x8(res, lane1, 1);\n  return res;\n#else\n  Packet16f res = _mm512_undefined_ps();\n  res = _mm512_insertf32x4(res, _mm256_extractf128_ps(lane0, 0), 0);\n  res = _mm512_insertf32x4(res, _mm256_extractf128_ps(lane0, 1), 1);\n  res = _mm512_insertf32x4(res, _mm256_extractf128_ps(lane1, 0), 2);\n  res = _mm512_insertf32x4(res, _mm256_extractf128_ps(lane1, 1), 3);\n  return res;\n#endif\n}\n// Loads 4 doubles from memory a returns the packet {a0, a0  a1, a1, a2, a2, a3,\n// a3}\ntemplate <>\nEIGEN_STRONG_INLINE Packet8d ploaddup<Packet8d>(const double* from) {\n  Packet4d lane0 = _mm256_broadcast_pd((const __m128d*)(const void*)from);\n  lane0 = _mm256_permute_pd(lane0, 3 << 2);\n\n  Packet4d lane1 = _mm256_broadcast_pd((const __m128d*)(const void*)(from + 2));\n  lane1 = _mm256_permute_pd(lane1, 3 << 2);\n\n  Packet8d res = _mm512_undefined_pd();\n  res = _mm512_insertf64x4(res, lane0, 0);\n  return _mm512_insertf64x4(res, lane1, 1);\n}\n\n// Loads 4 floats from memory a returns the packet\n// {a0, a0  a0, a0, a1, a1, a1, a1, a2, a2, a2, a2, a3, a3, a3, a3}\ntemplate <>\nEIGEN_STRONG_INLINE Packet16f ploadquad<Packet16f>(const float* from) {\n  Packet16f tmp = _mm512_undefined_ps();\n  tmp = _mm512_insertf32x4(tmp, _mm_load_ps1(from), 0);\n  tmp = _mm512_insertf32x4(tmp, _mm_load_ps1(from + 1), 1);\n  tmp = _mm512_insertf32x4(tmp, _mm_load_ps1(from + 2), 2);\n  tmp = _mm512_insertf32x4(tmp, _mm_load_ps1(from + 3), 3);\n  return tmp;\n}\n// Loads 2 doubles from memory a returns the packet\n// {a0, a0  a0, a0, a1, a1, a1, a1}\ntemplate <>\nEIGEN_STRONG_INLINE Packet8d ploadquad<Packet8d>(const double* from) {\n  Packet8d tmp = _mm512_undefined_pd();\n  Packet2d tmp0 = _mm_load_pd1(from);\n  Packet2d tmp1 = _mm_load_pd1(from + 1);\n  Packet4d lane0 = _mm256_broadcastsd_pd(tmp0);\n  Packet4d lane1 = _mm256_broadcastsd_pd(tmp1);\n  tmp = _mm512_insertf64x4(tmp, lane0, 0);\n  return _mm512_insertf64x4(tmp, lane1, 1);\n}\n\ntemplate <>\nEIGEN_STRONG_INLINE void pstore<float>(float* to, const Packet16f& from) {\n  EIGEN_DEBUG_ALIGNED_STORE _mm512_store_ps(to, from);\n}\ntemplate <>\nEIGEN_STRONG_INLINE void pstore<double>(double* to, const Packet8d& from) {\n  EIGEN_DEBUG_ALIGNED_STORE _mm512_store_pd(to, from);\n}\ntemplate <>\nEIGEN_STRONG_INLINE void pstore<int>(int* to, const Packet16i& from) {\n  EIGEN_DEBUG_ALIGNED_STORE _mm512_storeu_si512(reinterpret_cast<__m512i*>(to),\n                                                from);\n}\n\ntemplate <>\nEIGEN_STRONG_INLINE void pstoreu<float>(float* to, const Packet16f& from) {\n  EIGEN_DEBUG_UNALIGNED_STORE _mm512_storeu_ps(to, from);\n}\ntemplate <>\nEIGEN_STRONG_INLINE void pstoreu<double>(double* to, const Packet8d& from) {\n  EIGEN_DEBUG_UNALIGNED_STORE _mm512_storeu_pd(to, from);\n}\ntemplate <>\nEIGEN_STRONG_INLINE void pstoreu<int>(int* to, const Packet16i& from) {\n  EIGEN_DEBUG_UNALIGNED_STORE _mm512_storeu_si512(\n      reinterpret_cast<__m512i*>(to), from);\n}\n\ntemplate <>\nEIGEN_DEVICE_FUNC inline Packet16f pgather<float, Packet16f>(const float* from,\n                                                             Index stride) {\n  Packet16i stride_vector = _mm512_set1_epi32(stride);\n  Packet16i stride_multiplier =\n      _mm512_set_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);\n  Packet16i indices = _mm512_mullo_epi32(stride_vector, stride_multiplier);\n\n  return _mm512_i32gather_ps(indices, from, 4);\n}\ntemplate <>\nEIGEN_DEVICE_FUNC inline Packet8d pgather<double, Packet8d>(const double* from,\n                                                            Index stride) {\n  Packet8i stride_vector = _mm256_set1_epi32(stride);\n  Packet8i stride_multiplier = _mm256_set_epi32(7, 6, 5, 4, 3, 2, 1, 0);\n  Packet8i indices = _mm256_mullo_epi32(stride_vector, stride_multiplier);\n\n  return _mm512_i32gather_pd(indices, from, 8);\n}\n\ntemplate <>\nEIGEN_DEVICE_FUNC inline void pscatter<float, Packet16f>(float* to,\n                                                         const Packet16f& from,\n                                                         Index stride) {\n  Packet16i stride_vector = _mm512_set1_epi32(stride);\n  Packet16i stride_multiplier =\n      _mm512_set_epi32(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);\n  Packet16i indices = _mm512_mullo_epi32(stride_vector, stride_multiplier);\n  _mm512_i32scatter_ps(to, indices, from, 4);\n}\ntemplate <>\nEIGEN_DEVICE_FUNC inline void pscatter<double, Packet8d>(double* to,\n                                                         const Packet8d& from,\n                                                         Index stride) {\n  Packet8i stride_vector = _mm256_set1_epi32(stride);\n  Packet8i stride_multiplier = _mm256_set_epi32(7, 6, 5, 4, 3, 2, 1, 0);\n  Packet8i indices = _mm256_mullo_epi32(stride_vector, stride_multiplier);\n  _mm512_i32scatter_pd(to, indices, from, 8);\n}\n\ntemplate <>\nEIGEN_STRONG_INLINE void pstore1<Packet16f>(float* to, const float& a) {\n  Packet16f pa = pset1<Packet16f>(a);\n  pstore(to, pa);\n}\ntemplate <>\nEIGEN_STRONG_INLINE void pstore1<Packet8d>(double* to, const double& a) {\n  Packet8d pa = pset1<Packet8d>(a);\n  pstore(to, pa);\n}\ntemplate <>\nEIGEN_STRONG_INLINE void pstore1<Packet16i>(int* to, const int& a) {\n  Packet16i pa = pset1<Packet16i>(a);\n  pstore(to, pa);\n}\n\ntemplate<> EIGEN_STRONG_INLINE void prefetch<float>(const float*   addr) { _mm_prefetch((const char*)(addr), _MM_HINT_T0); }\ntemplate<> EIGEN_STRONG_INLINE void prefetch<double>(const double* addr) { _mm_prefetch((const char*)(addr), _MM_HINT_T0); }\ntemplate<> EIGEN_STRONG_INLINE void prefetch<int>(const int*       addr) { _mm_prefetch((const char*)(addr), _MM_HINT_T0); }\n\ntemplate <>\nEIGEN_STRONG_INLINE float pfirst<Packet16f>(const Packet16f& a) {\n  return _mm_cvtss_f32(_mm512_extractf32x4_ps(a, 0));\n}\ntemplate <>\nEIGEN_STRONG_INLINE double pfirst<Packet8d>(const Packet8d& a) {\n  return _mm_cvtsd_f64(_mm256_extractf128_pd(_mm512_extractf64x4_pd(a, 0), 0));\n}\ntemplate <>\nEIGEN_STRONG_INLINE int pfirst<Packet16i>(const Packet16i& a) {\n  return _mm_extract_epi32(_mm512_extracti32x4_epi32(a, 0), 0);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet16f preverse(const Packet16f& a)\n{\n  return _mm512_permutexvar_ps(_mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15), a);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet8d preverse(const Packet8d& a)\n{\n  return _mm512_permutexvar_pd(_mm512_set_epi32(0, 0, 0, 1, 0, 2, 0, 3, 0, 4, 0, 5, 0, 6, 0, 7), a);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet16f pabs(const Packet16f& a)\n{\n  // _mm512_abs_ps intrinsic not found, so hack around it\n  return (__m512)_mm512_and_si512((__m512i)a, _mm512_set1_epi32(0x7fffffff));\n}\ntemplate <>\nEIGEN_STRONG_INLINE Packet8d pabs(const Packet8d& a) {\n  // _mm512_abs_ps intrinsic not found, so hack around it\n  return (__m512d)_mm512_and_si512((__m512i)a,\n                                   _mm512_set1_epi64(0x7fffffffffffffff));\n}\n\n#ifdef EIGEN_VECTORIZE_AVX512DQ\n// AVX512F does not define _mm512_extractf32x8_ps to extract _m256 from _m512\n#define EIGEN_EXTRACT_8f_FROM_16f(INPUT, OUTPUT)                           \\\n  __m256 OUTPUT##_0 = _mm512_extractf32x8_ps(INPUT, 0) __m256 OUTPUT##_1 = \\\n      _mm512_extractf32x8_ps(INPUT, 1)\n#else\n#define EIGEN_EXTRACT_8f_FROM_16f(INPUT, OUTPUT)                \\\n  __m256 OUTPUT##_0 = _mm256_insertf128_ps(                     \\\n      _mm256_castps128_ps256(_mm512_extractf32x4_ps(INPUT, 0)), \\\n      _mm512_extractf32x4_ps(INPUT, 1), 1);                     \\\n  __m256 OUTPUT##_1 = _mm256_insertf128_ps(                     \\\n      _mm256_castps128_ps256(_mm512_extractf32x4_ps(INPUT, 2)), \\\n      _mm512_extractf32x4_ps(INPUT, 3), 1);\n#endif\n\n#ifdef EIGEN_VECTORIZE_AVX512DQ\n#define EIGEN_INSERT_8f_INTO_16f(OUTPUT, INPUTA, INPUTB) \\\n  OUTPUT = _mm512_insertf32x8(OUTPUT, INPUTA, 0);        \\\n  OUTPUT = _mm512_insertf32x8(OUTPUT, INPUTB, 1);\n#else\n#define EIGEN_INSERT_8f_INTO_16f(OUTPUT, INPUTA, INPUTB)                    \\\n  OUTPUT = _mm512_insertf32x4(OUTPUT, _mm256_extractf128_ps(INPUTA, 0), 0); \\\n  OUTPUT = _mm512_insertf32x4(OUTPUT, _mm256_extractf128_ps(INPUTA, 1), 1); \\\n  OUTPUT = _mm512_insertf32x4(OUTPUT, _mm256_extractf128_ps(INPUTB, 0), 2); \\\n  OUTPUT = _mm512_insertf32x4(OUTPUT, _mm256_extractf128_ps(INPUTB, 1), 3);\n#endif\ntemplate<> EIGEN_STRONG_INLINE Packet16f preduxp<Packet16f>(const Packet16f*\nvecs)\n{\n  EIGEN_EXTRACT_8f_FROM_16f(vecs[0], vecs0);\n  EIGEN_EXTRACT_8f_FROM_16f(vecs[1], vecs1);\n  EIGEN_EXTRACT_8f_FROM_16f(vecs[2], vecs2);\n  EIGEN_EXTRACT_8f_FROM_16f(vecs[3], vecs3);\n  EIGEN_EXTRACT_8f_FROM_16f(vecs[4], vecs4);\n  EIGEN_EXTRACT_8f_FROM_16f(vecs[5], vecs5);\n  EIGEN_EXTRACT_8f_FROM_16f(vecs[6], vecs6);\n  EIGEN_EXTRACT_8f_FROM_16f(vecs[7], vecs7);\n  EIGEN_EXTRACT_8f_FROM_16f(vecs[8], vecs8);\n  EIGEN_EXTRACT_8f_FROM_16f(vecs[9], vecs9);\n  EIGEN_EXTRACT_8f_FROM_16f(vecs[10], vecs10);\n  EIGEN_EXTRACT_8f_FROM_16f(vecs[11], vecs11);\n  EIGEN_EXTRACT_8f_FROM_16f(vecs[12], vecs12);\n  EIGEN_EXTRACT_8f_FROM_16f(vecs[13], vecs13);\n  EIGEN_EXTRACT_8f_FROM_16f(vecs[14], vecs14);\n  EIGEN_EXTRACT_8f_FROM_16f(vecs[15], vecs15);\n\n  __m256 hsum1 = _mm256_hadd_ps(vecs0_0, vecs1_0);\n  __m256 hsum2 = _mm256_hadd_ps(vecs2_0, vecs3_0);\n  __m256 hsum3 = _mm256_hadd_ps(vecs4_0, vecs5_0);\n  __m256 hsum4 = _mm256_hadd_ps(vecs6_0, vecs7_0);\n\n  __m256 hsum5 = _mm256_hadd_ps(hsum1, hsum1);\n  __m256 hsum6 = _mm256_hadd_ps(hsum2, hsum2);\n  __m256 hsum7 = _mm256_hadd_ps(hsum3, hsum3);\n  __m256 hsum8 = _mm256_hadd_ps(hsum4, hsum4);\n\n  __m256 perm1 = _mm256_permute2f128_ps(hsum5, hsum5, 0x23);\n  __m256 perm2 = _mm256_permute2f128_ps(hsum6, hsum6, 0x23);\n  __m256 perm3 = _mm256_permute2f128_ps(hsum7, hsum7, 0x23);\n  __m256 perm4 = _mm256_permute2f128_ps(hsum8, hsum8, 0x23);\n\n  __m256 sum1 = _mm256_add_ps(perm1, hsum5);\n  __m256 sum2 = _mm256_add_ps(perm2, hsum6);\n  __m256 sum3 = _mm256_add_ps(perm3, hsum7);\n  __m256 sum4 = _mm256_add_ps(perm4, hsum8);\n\n  __m256 blend1 = _mm256_blend_ps(sum1, sum2, 0xcc);\n  __m256 blend2 = _mm256_blend_ps(sum3, sum4, 0xcc);\n\n  __m256 final = _mm256_blend_ps(blend1, blend2, 0xf0);\n\n  hsum1 = _mm256_hadd_ps(vecs0_1, vecs1_1);\n  hsum2 = _mm256_hadd_ps(vecs2_1, vecs3_1);\n  hsum3 = _mm256_hadd_ps(vecs4_1, vecs5_1);\n  hsum4 = _mm256_hadd_ps(vecs6_1, vecs7_1);\n\n  hsum5 = _mm256_hadd_ps(hsum1, hsum1);\n  hsum6 = _mm256_hadd_ps(hsum2, hsum2);\n  hsum7 = _mm256_hadd_ps(hsum3, hsum3);\n  hsum8 = _mm256_hadd_ps(hsum4, hsum4);\n\n  perm1 = _mm256_permute2f128_ps(hsum5, hsum5, 0x23);\n  perm2 = _mm256_permute2f128_ps(hsum6, hsum6, 0x23);\n  perm3 = _mm256_permute2f128_ps(hsum7, hsum7, 0x23);\n  perm4 = _mm256_permute2f128_ps(hsum8, hsum8, 0x23);\n\n  sum1 = _mm256_add_ps(perm1, hsum5);\n  sum2 = _mm256_add_ps(perm2, hsum6);\n  sum3 = _mm256_add_ps(perm3, hsum7);\n  sum4 = _mm256_add_ps(perm4, hsum8);\n\n  blend1 = _mm256_blend_ps(sum1, sum2, 0xcc);\n  blend2 = _mm256_blend_ps(sum3, sum4, 0xcc);\n\n  final = padd(final, _mm256_blend_ps(blend1, blend2, 0xf0));\n\n  hsum1 = _mm256_hadd_ps(vecs8_0, vecs9_0);\n  hsum2 = _mm256_hadd_ps(vecs10_0, vecs11_0);\n  hsum3 = _mm256_hadd_ps(vecs12_0, vecs13_0);\n  hsum4 = _mm256_hadd_ps(vecs14_0, vecs15_0);\n\n  hsum5 = _mm256_hadd_ps(hsum1, hsum1);\n  hsum6 = _mm256_hadd_ps(hsum2, hsum2);\n  hsum7 = _mm256_hadd_ps(hsum3, hsum3);\n  hsum8 = _mm256_hadd_ps(hsum4, hsum4);\n\n  perm1 = _mm256_permute2f128_ps(hsum5, hsum5, 0x23);\n  perm2 = _mm256_permute2f128_ps(hsum6, hsum6, 0x23);\n  perm3 = _mm256_permute2f128_ps(hsum7, hsum7, 0x23);\n  perm4 = _mm256_permute2f128_ps(hsum8, hsum8, 0x23);\n\n  sum1 = _mm256_add_ps(perm1, hsum5);\n  sum2 = _mm256_add_ps(perm2, hsum6);\n  sum3 = _mm256_add_ps(perm3, hsum7);\n  sum4 = _mm256_add_ps(perm4, hsum8);\n\n  blend1 = _mm256_blend_ps(sum1, sum2, 0xcc);\n  blend2 = _mm256_blend_ps(sum3, sum4, 0xcc);\n\n  __m256 final_1 = _mm256_blend_ps(blend1, blend2, 0xf0);\n\n  hsum1 = _mm256_hadd_ps(vecs8_1, vecs9_1);\n  hsum2 = _mm256_hadd_ps(vecs10_1, vecs11_1);\n  hsum3 = _mm256_hadd_ps(vecs12_1, vecs13_1);\n  hsum4 = _mm256_hadd_ps(vecs14_1, vecs15_1);\n\n  hsum5 = _mm256_hadd_ps(hsum1, hsum1);\n  hsum6 = _mm256_hadd_ps(hsum2, hsum2);\n  hsum7 = _mm256_hadd_ps(hsum3, hsum3);\n  hsum8 = _mm256_hadd_ps(hsum4, hsum4);\n\n  perm1 = _mm256_permute2f128_ps(hsum5, hsum5, 0x23);\n  perm2 = _mm256_permute2f128_ps(hsum6, hsum6, 0x23);\n  perm3 = _mm256_permute2f128_ps(hsum7, hsum7, 0x23);\n  perm4 = _mm256_permute2f128_ps(hsum8, hsum8, 0x23);\n\n  sum1 = _mm256_add_ps(perm1, hsum5);\n  sum2 = _mm256_add_ps(perm2, hsum6);\n  sum3 = _mm256_add_ps(perm3, hsum7);\n  sum4 = _mm256_add_ps(perm4, hsum8);\n\n  blend1 = _mm256_blend_ps(sum1, sum2, 0xcc);\n  blend2 = _mm256_blend_ps(sum3, sum4, 0xcc);\n\n  final_1 = padd(final_1, _mm256_blend_ps(blend1, blend2, 0xf0));\n\n  __m512 final_output;\n\n  EIGEN_INSERT_8f_INTO_16f(final_output, final, final_1);\n  return final_output;\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet8d preduxp<Packet8d>(const Packet8d* vecs)\n{\n  Packet4d vecs0_0 = _mm512_extractf64x4_pd(vecs[0], 0);\n  Packet4d vecs0_1 = _mm512_extractf64x4_pd(vecs[0], 1);\n\n  Packet4d vecs1_0 = _mm512_extractf64x4_pd(vecs[1], 0);\n  Packet4d vecs1_1 = _mm512_extractf64x4_pd(vecs[1], 1);\n\n  Packet4d vecs2_0 = _mm512_extractf64x4_pd(vecs[2], 0);\n  Packet4d vecs2_1 = _mm512_extractf64x4_pd(vecs[2], 1);\n\n  Packet4d vecs3_0 = _mm512_extractf64x4_pd(vecs[3], 0);\n  Packet4d vecs3_1 = _mm512_extractf64x4_pd(vecs[3], 1);\n\n  Packet4d vecs4_0 = _mm512_extractf64x4_pd(vecs[4], 0);\n  Packet4d vecs4_1 = _mm512_extractf64x4_pd(vecs[4], 1);\n\n  Packet4d vecs5_0 = _mm512_extractf64x4_pd(vecs[5], 0);\n  Packet4d vecs5_1 = _mm512_extractf64x4_pd(vecs[5], 1);\n\n  Packet4d vecs6_0 = _mm512_extractf64x4_pd(vecs[6], 0);\n  Packet4d vecs6_1 = _mm512_extractf64x4_pd(vecs[6], 1);\n\n  Packet4d vecs7_0 = _mm512_extractf64x4_pd(vecs[7], 0);\n  Packet4d vecs7_1 = _mm512_extractf64x4_pd(vecs[7], 1);\n\n  Packet4d tmp0, tmp1;\n\n  tmp0 = _mm256_hadd_pd(vecs0_0, vecs1_0);\n  tmp0 = _mm256_add_pd(tmp0, _mm256_permute2f128_pd(tmp0, tmp0, 1));\n\n  tmp1 = _mm256_hadd_pd(vecs2_0, vecs3_0);\n  tmp1 = _mm256_add_pd(tmp1, _mm256_permute2f128_pd(tmp1, tmp1, 1));\n\n  __m256d final_0 = _mm256_blend_pd(tmp0, tmp1, 0xC);\n\n  tmp0 = _mm256_hadd_pd(vecs0_1, vecs1_1);\n  tmp0 = _mm256_add_pd(tmp0, _mm256_permute2f128_pd(tmp0, tmp0, 1));\n\n  tmp1 = _mm256_hadd_pd(vecs2_1, vecs3_1);\n  tmp1 = _mm256_add_pd(tmp1, _mm256_permute2f128_pd(tmp1, tmp1, 1));\n\n  final_0 = padd(final_0, _mm256_blend_pd(tmp0, tmp1, 0xC));\n\n  tmp0 = _mm256_hadd_pd(vecs4_0, vecs5_0);\n  tmp0 = _mm256_add_pd(tmp0, _mm256_permute2f128_pd(tmp0, tmp0, 1));\n\n  tmp1 = _mm256_hadd_pd(vecs6_0, vecs7_0);\n  tmp1 = _mm256_add_pd(tmp1, _mm256_permute2f128_pd(tmp1, tmp1, 1));\n\n  __m256d final_1 = _mm256_blend_pd(tmp0, tmp1, 0xC);\n\n  tmp0 = _mm256_hadd_pd(vecs4_1, vecs5_1);\n  tmp0 = _mm256_add_pd(tmp0, _mm256_permute2f128_pd(tmp0, tmp0, 1));\n\n  tmp1 = _mm256_hadd_pd(vecs6_1, vecs7_1);\n  tmp1 = _mm256_add_pd(tmp1, _mm256_permute2f128_pd(tmp1, tmp1, 1));\n\n  final_1 = padd(final_1, _mm256_blend_pd(tmp0, tmp1, 0xC));\n\n  __m512d final_output = _mm512_insertf64x4(final_output, final_0, 0);\n\n  return _mm512_insertf64x4(final_output, final_1, 1);\n}\n\ntemplate <>\nEIGEN_STRONG_INLINE float predux<Packet16f>(const Packet16f& a) {\n  //#ifdef EIGEN_VECTORIZE_AVX512DQ\n#if 0\n  Packet8f lane0 = _mm512_extractf32x8_ps(a, 0);\n  Packet8f lane1 = _mm512_extractf32x8_ps(a, 1);\n  Packet8f sum = padd(lane0, lane1);\n  Packet8f tmp0 = _mm256_hadd_ps(sum, _mm256_permute2f128_ps(a, a, 1));\n  tmp0 = _mm256_hadd_ps(tmp0, tmp0);\n  return pfirst(_mm256_hadd_ps(tmp0, tmp0));\n#else\n  Packet4f lane0 = _mm512_extractf32x4_ps(a, 0);\n  Packet4f lane1 = _mm512_extractf32x4_ps(a, 1);\n  Packet4f lane2 = _mm512_extractf32x4_ps(a, 2);\n  Packet4f lane3 = _mm512_extractf32x4_ps(a, 3);\n  Packet4f sum = padd(padd(lane0, lane1), padd(lane2, lane3));\n  sum = _mm_hadd_ps(sum, sum);\n  sum = _mm_hadd_ps(sum, _mm_permute_ps(sum, 1));\n  return pfirst(sum);\n#endif\n}\ntemplate <>\nEIGEN_STRONG_INLINE double predux<Packet8d>(const Packet8d& a) {\n  Packet4d lane0 = _mm512_extractf64x4_pd(a, 0);\n  Packet4d lane1 = _mm512_extractf64x4_pd(a, 1);\n  Packet4d sum = padd(lane0, lane1);\n  Packet4d tmp0 = _mm256_hadd_pd(sum, _mm256_permute2f128_pd(sum, sum, 1));\n  return pfirst(_mm256_hadd_pd(tmp0, tmp0));\n}\n\ntemplate <>\nEIGEN_STRONG_INLINE Packet8f predux_downto4<Packet16f>(const Packet16f& a) {\n#ifdef EIGEN_VECTORIZE_AVX512DQ\n  Packet8f lane0 = _mm512_extractf32x8_ps(a, 0);\n  Packet8f lane1 = _mm512_extractf32x8_ps(a, 1);\n  return padd(lane0, lane1);\n#else\n  Packet4f lane0 = _mm512_extractf32x4_ps(a, 0);\n  Packet4f lane1 = _mm512_extractf32x4_ps(a, 1);\n  Packet4f lane2 = _mm512_extractf32x4_ps(a, 2);\n  Packet4f lane3 = _mm512_extractf32x4_ps(a, 3);\n  Packet4f sum0 = padd(lane0, lane2);\n  Packet4f sum1 = padd(lane1, lane3);\n  return _mm256_insertf128_ps(_mm256_castps128_ps256(sum0), sum1, 1);\n#endif\n}\ntemplate <>\nEIGEN_STRONG_INLINE Packet4d predux_downto4<Packet8d>(const Packet8d& a) {\n  Packet4d lane0 = _mm512_extractf64x4_pd(a, 0);\n  Packet4d lane1 = _mm512_extractf64x4_pd(a, 1);\n  Packet4d res = padd(lane0, lane1);\n  return res;\n}\n\ntemplate <>\nEIGEN_STRONG_INLINE float predux_mul<Packet16f>(const Packet16f& a) {\n//#ifdef EIGEN_VECTORIZE_AVX512DQ\n#if 0\n  Packet8f lane0 = _mm512_extractf32x8_ps(a, 0);\n  Packet8f lane1 = _mm512_extractf32x8_ps(a, 1);\n  Packet8f res = pmul(lane0, lane1);\n  res = pmul(res, _mm256_permute2f128_ps(res, res, 1));\n  res = pmul(res, _mm_permute_ps(res, _MM_SHUFFLE(0, 0, 3, 2)));\n  return pfirst(pmul(res, _mm_permute_ps(res, _MM_SHUFFLE(0, 0, 0, 1))));\n#else\n  Packet4f lane0 = _mm512_extractf32x4_ps(a, 0);\n  Packet4f lane1 = _mm512_extractf32x4_ps(a, 1);\n  Packet4f lane2 = _mm512_extractf32x4_ps(a, 2);\n  Packet4f lane3 = _mm512_extractf32x4_ps(a, 3);\n  Packet4f res = pmul(pmul(lane0, lane1), pmul(lane2, lane3));\n  res = pmul(res, _mm_permute_ps(res, _MM_SHUFFLE(0, 0, 3, 2)));\n  return pfirst(pmul(res, _mm_permute_ps(res, _MM_SHUFFLE(0, 0, 0, 1))));\n#endif\n}\ntemplate <>\nEIGEN_STRONG_INLINE double predux_mul<Packet8d>(const Packet8d& a) {\n  Packet4d lane0 = _mm512_extractf64x4_pd(a, 0);\n  Packet4d lane1 = _mm512_extractf64x4_pd(a, 1);\n  Packet4d res = pmul(lane0, lane1);\n  res = pmul(res, _mm256_permute2f128_pd(res, res, 1));\n  return pfirst(pmul(res, _mm256_shuffle_pd(res, res, 1)));\n}\n\ntemplate <>\nEIGEN_STRONG_INLINE float predux_min<Packet16f>(const Packet16f& a) {\n  Packet4f lane0 = _mm512_extractf32x4_ps(a, 0);\n  Packet4f lane1 = _mm512_extractf32x4_ps(a, 1);\n  Packet4f lane2 = _mm512_extractf32x4_ps(a, 2);\n  Packet4f lane3 = _mm512_extractf32x4_ps(a, 3);\n  Packet4f res = _mm_min_ps(_mm_min_ps(lane0, lane1), _mm_min_ps(lane2, lane3));\n  res = _mm_min_ps(res, _mm_permute_ps(res, _MM_SHUFFLE(0, 0, 3, 2)));\n  return pfirst(_mm_min_ps(res, _mm_permute_ps(res, _MM_SHUFFLE(0, 0, 0, 1))));\n}\ntemplate <>\nEIGEN_STRONG_INLINE double predux_min<Packet8d>(const Packet8d& a) {\n  Packet4d lane0 = _mm512_extractf64x4_pd(a, 0);\n  Packet4d lane1 = _mm512_extractf64x4_pd(a, 1);\n  Packet4d res = _mm256_min_pd(lane0, lane1);\n  res = _mm256_min_pd(res, _mm256_permute2f128_pd(res, res, 1));\n  return pfirst(_mm256_min_pd(res, _mm256_shuffle_pd(res, res, 1)));\n}\n\ntemplate <>\nEIGEN_STRONG_INLINE float predux_max<Packet16f>(const Packet16f& a) {\n  Packet4f lane0 = _mm512_extractf32x4_ps(a, 0);\n  Packet4f lane1 = _mm512_extractf32x4_ps(a, 1);\n  Packet4f lane2 = _mm512_extractf32x4_ps(a, 2);\n  Packet4f lane3 = _mm512_extractf32x4_ps(a, 3);\n  Packet4f res = _mm_max_ps(_mm_max_ps(lane0, lane1), _mm_max_ps(lane2, lane3));\n  res = _mm_max_ps(res, _mm_permute_ps(res, _MM_SHUFFLE(0, 0, 3, 2)));\n  return pfirst(_mm_max_ps(res, _mm_permute_ps(res, _MM_SHUFFLE(0, 0, 0, 1))));\n}\ntemplate <>\nEIGEN_STRONG_INLINE double predux_max<Packet8d>(const Packet8d& a) {\n  Packet4d lane0 = _mm512_extractf64x4_pd(a, 0);\n  Packet4d lane1 = _mm512_extractf64x4_pd(a, 1);\n  Packet4d res = _mm256_max_pd(lane0, lane1);\n  res = _mm256_max_pd(res, _mm256_permute2f128_pd(res, res, 1));\n  return pfirst(_mm256_max_pd(res, _mm256_shuffle_pd(res, res, 1)));\n}\n\ntemplate <int Offset>\nstruct palign_impl<Offset, Packet16f> {\n  static EIGEN_STRONG_INLINE void run(Packet16f& first,\n                                      const Packet16f& second) {\n    if (Offset != 0) {\n      __m512i first_idx = _mm512_set_epi32(\n          Offset + 15, Offset + 14, Offset + 13, Offset + 12, Offset + 11,\n          Offset + 10, Offset + 9, Offset + 8, Offset + 7, Offset + 6,\n          Offset + 5, Offset + 4, Offset + 3, Offset + 2, Offset + 1, Offset);\n\n      __m512i second_idx =\n          _mm512_set_epi32(Offset - 1, Offset - 2, Offset - 3, Offset - 4,\n                           Offset - 5, Offset - 6, Offset - 7, Offset - 8,\n                           Offset - 9, Offset - 10, Offset - 11, Offset - 12,\n                           Offset - 13, Offset - 14, Offset - 15, Offset - 16);\n\n      unsigned short mask = 0xFFFF;\n      mask <<= (16 - Offset);\n\n      first = _mm512_permutexvar_ps(first_idx, first);\n      Packet16f tmp = _mm512_permutexvar_ps(second_idx, second);\n      first = _mm512_mask_blend_ps(mask, first, tmp);\n    }\n  }\n};\ntemplate <int Offset>\nstruct palign_impl<Offset, Packet8d> {\n  static EIGEN_STRONG_INLINE void run(Packet8d& first, const Packet8d& second) {\n    if (Offset != 0) {\n      __m512i first_idx = _mm512_set_epi32(\n          0, Offset + 7, 0, Offset + 6, 0, Offset + 5, 0, Offset + 4, 0,\n          Offset + 3, 0, Offset + 2, 0, Offset + 1, 0, Offset);\n\n      __m512i second_idx = _mm512_set_epi32(\n          0, Offset - 1, 0, Offset - 2, 0, Offset - 3, 0, Offset - 4, 0,\n          Offset - 5, 0, Offset - 6, 0, Offset - 7, 0, Offset - 8);\n\n      unsigned char mask = 0xFF;\n      mask <<= (8 - Offset);\n\n      first = _mm512_permutexvar_pd(first_idx, first);\n      Packet8d tmp = _mm512_permutexvar_pd(second_idx, second);\n      first = _mm512_mask_blend_pd(mask, first, tmp);\n    }\n  }\n};\n\n\n#define PACK_OUTPUT(OUTPUT, INPUT, INDEX, STRIDE) \\\n  EIGEN_INSERT_8f_INTO_16f(OUTPUT[INDEX], INPUT[INDEX], INPUT[INDEX + STRIDE]);\n\nEIGEN_DEVICE_FUNC inline void ptranspose(PacketBlock<Packet16f, 16>& kernel) {\n  __m512 T0 = _mm512_unpacklo_ps(kernel.packet[0], kernel.packet[1]);\n  __m512 T1 = _mm512_unpackhi_ps(kernel.packet[0], kernel.packet[1]);\n  __m512 T2 = _mm512_unpacklo_ps(kernel.packet[2], kernel.packet[3]);\n  __m512 T3 = _mm512_unpackhi_ps(kernel.packet[2], kernel.packet[3]);\n  __m512 T4 = _mm512_unpacklo_ps(kernel.packet[4], kernel.packet[5]);\n  __m512 T5 = _mm512_unpackhi_ps(kernel.packet[4], kernel.packet[5]);\n  __m512 T6 = _mm512_unpacklo_ps(kernel.packet[6], kernel.packet[7]);\n  __m512 T7 = _mm512_unpackhi_ps(kernel.packet[6], kernel.packet[7]);\n  __m512 T8 = _mm512_unpacklo_ps(kernel.packet[8], kernel.packet[9]);\n  __m512 T9 = _mm512_unpackhi_ps(kernel.packet[8], kernel.packet[9]);\n  __m512 T10 = _mm512_unpacklo_ps(kernel.packet[10], kernel.packet[11]);\n  __m512 T11 = _mm512_unpackhi_ps(kernel.packet[10], kernel.packet[11]);\n  __m512 T12 = _mm512_unpacklo_ps(kernel.packet[12], kernel.packet[13]);\n  __m512 T13 = _mm512_unpackhi_ps(kernel.packet[12], kernel.packet[13]);\n  __m512 T14 = _mm512_unpacklo_ps(kernel.packet[14], kernel.packet[15]);\n  __m512 T15 = _mm512_unpackhi_ps(kernel.packet[14], kernel.packet[15]);\n  __m512 S0 = _mm512_shuffle_ps(T0, T2, _MM_SHUFFLE(1, 0, 1, 0));\n  __m512 S1 = _mm512_shuffle_ps(T0, T2, _MM_SHUFFLE(3, 2, 3, 2));\n  __m512 S2 = _mm512_shuffle_ps(T1, T3, _MM_SHUFFLE(1, 0, 1, 0));\n  __m512 S3 = _mm512_shuffle_ps(T1, T3, _MM_SHUFFLE(3, 2, 3, 2));\n  __m512 S4 = _mm512_shuffle_ps(T4, T6, _MM_SHUFFLE(1, 0, 1, 0));\n  __m512 S5 = _mm512_shuffle_ps(T4, T6, _MM_SHUFFLE(3, 2, 3, 2));\n  __m512 S6 = _mm512_shuffle_ps(T5, T7, _MM_SHUFFLE(1, 0, 1, 0));\n  __m512 S7 = _mm512_shuffle_ps(T5, T7, _MM_SHUFFLE(3, 2, 3, 2));\n  __m512 S8 = _mm512_shuffle_ps(T8, T10, _MM_SHUFFLE(1, 0, 1, 0));\n  __m512 S9 = _mm512_shuffle_ps(T8, T10, _MM_SHUFFLE(3, 2, 3, 2));\n  __m512 S10 = _mm512_shuffle_ps(T9, T11, _MM_SHUFFLE(1, 0, 1, 0));\n  __m512 S11 = _mm512_shuffle_ps(T9, T11, _MM_SHUFFLE(3, 2, 3, 2));\n  __m512 S12 = _mm512_shuffle_ps(T12, T14, _MM_SHUFFLE(1, 0, 1, 0));\n  __m512 S13 = _mm512_shuffle_ps(T12, T14, _MM_SHUFFLE(3, 2, 3, 2));\n  __m512 S14 = _mm512_shuffle_ps(T13, T15, _MM_SHUFFLE(1, 0, 1, 0));\n  __m512 S15 = _mm512_shuffle_ps(T13, T15, _MM_SHUFFLE(3, 2, 3, 2));\n\n  EIGEN_EXTRACT_8f_FROM_16f(S0, S0);\n  EIGEN_EXTRACT_8f_FROM_16f(S1, S1);\n  EIGEN_EXTRACT_8f_FROM_16f(S2, S2);\n  EIGEN_EXTRACT_8f_FROM_16f(S3, S3);\n  EIGEN_EXTRACT_8f_FROM_16f(S4, S4);\n  EIGEN_EXTRACT_8f_FROM_16f(S5, S5);\n  EIGEN_EXTRACT_8f_FROM_16f(S6, S6);\n  EIGEN_EXTRACT_8f_FROM_16f(S7, S7);\n  EIGEN_EXTRACT_8f_FROM_16f(S8, S8);\n  EIGEN_EXTRACT_8f_FROM_16f(S9, S9);\n  EIGEN_EXTRACT_8f_FROM_16f(S10, S10);\n  EIGEN_EXTRACT_8f_FROM_16f(S11, S11);\n  EIGEN_EXTRACT_8f_FROM_16f(S12, S12);\n  EIGEN_EXTRACT_8f_FROM_16f(S13, S13);\n  EIGEN_EXTRACT_8f_FROM_16f(S14, S14);\n  EIGEN_EXTRACT_8f_FROM_16f(S15, S15);\n\n  PacketBlock<Packet8f, 32> tmp;\n\n  tmp.packet[0] = _mm256_permute2f128_ps(S0_0, S4_0, 0x20);\n  tmp.packet[1] = _mm256_permute2f128_ps(S1_0, S5_0, 0x20);\n  tmp.packet[2] = _mm256_permute2f128_ps(S2_0, S6_0, 0x20);\n  tmp.packet[3] = _mm256_permute2f128_ps(S3_0, S7_0, 0x20);\n  tmp.packet[4] = _mm256_permute2f128_ps(S0_0, S4_0, 0x31);\n  tmp.packet[5] = _mm256_permute2f128_ps(S1_0, S5_0, 0x31);\n  tmp.packet[6] = _mm256_permute2f128_ps(S2_0, S6_0, 0x31);\n  tmp.packet[7] = _mm256_permute2f128_ps(S3_0, S7_0, 0x31);\n\n  tmp.packet[8] = _mm256_permute2f128_ps(S0_1, S4_1, 0x20);\n  tmp.packet[9] = _mm256_permute2f128_ps(S1_1, S5_1, 0x20);\n  tmp.packet[10] = _mm256_permute2f128_ps(S2_1, S6_1, 0x20);\n  tmp.packet[11] = _mm256_permute2f128_ps(S3_1, S7_1, 0x20);\n  tmp.packet[12] = _mm256_permute2f128_ps(S0_1, S4_1, 0x31);\n  tmp.packet[13] = _mm256_permute2f128_ps(S1_1, S5_1, 0x31);\n  tmp.packet[14] = _mm256_permute2f128_ps(S2_1, S6_1, 0x31);\n  tmp.packet[15] = _mm256_permute2f128_ps(S3_1, S7_1, 0x31);\n\n  // Second set of _m256 outputs\n  tmp.packet[16] = _mm256_permute2f128_ps(S8_0, S12_0, 0x20);\n  tmp.packet[17] = _mm256_permute2f128_ps(S9_0, S13_0, 0x20);\n  tmp.packet[18] = _mm256_permute2f128_ps(S10_0, S14_0, 0x20);\n  tmp.packet[19] = _mm256_permute2f128_ps(S11_0, S15_0, 0x20);\n  tmp.packet[20] = _mm256_permute2f128_ps(S8_0, S12_0, 0x31);\n  tmp.packet[21] = _mm256_permute2f128_ps(S9_0, S13_0, 0x31);\n  tmp.packet[22] = _mm256_permute2f128_ps(S10_0, S14_0, 0x31);\n  tmp.packet[23] = _mm256_permute2f128_ps(S11_0, S15_0, 0x31);\n\n  tmp.packet[24] = _mm256_permute2f128_ps(S8_1, S12_1, 0x20);\n  tmp.packet[25] = _mm256_permute2f128_ps(S9_1, S13_1, 0x20);\n  tmp.packet[26] = _mm256_permute2f128_ps(S10_1, S14_1, 0x20);\n  tmp.packet[27] = _mm256_permute2f128_ps(S11_1, S15_1, 0x20);\n  tmp.packet[28] = _mm256_permute2f128_ps(S8_1, S12_1, 0x31);\n  tmp.packet[29] = _mm256_permute2f128_ps(S9_1, S13_1, 0x31);\n  tmp.packet[30] = _mm256_permute2f128_ps(S10_1, S14_1, 0x31);\n  tmp.packet[31] = _mm256_permute2f128_ps(S11_1, S15_1, 0x31);\n\n  // Pack them into the output\n  PACK_OUTPUT(kernel.packet, tmp.packet, 0, 16);\n  PACK_OUTPUT(kernel.packet, tmp.packet, 1, 16);\n  PACK_OUTPUT(kernel.packet, tmp.packet, 2, 16);\n  PACK_OUTPUT(kernel.packet, tmp.packet, 3, 16);\n\n  PACK_OUTPUT(kernel.packet, tmp.packet, 4, 16);\n  PACK_OUTPUT(kernel.packet, tmp.packet, 5, 16);\n  PACK_OUTPUT(kernel.packet, tmp.packet, 6, 16);\n  PACK_OUTPUT(kernel.packet, tmp.packet, 7, 16);\n\n  PACK_OUTPUT(kernel.packet, tmp.packet, 8, 16);\n  PACK_OUTPUT(kernel.packet, tmp.packet, 9, 16);\n  PACK_OUTPUT(kernel.packet, tmp.packet, 10, 16);\n  PACK_OUTPUT(kernel.packet, tmp.packet, 11, 16);\n\n  PACK_OUTPUT(kernel.packet, tmp.packet, 12, 16);\n  PACK_OUTPUT(kernel.packet, tmp.packet, 13, 16);\n  PACK_OUTPUT(kernel.packet, tmp.packet, 14, 16);\n  PACK_OUTPUT(kernel.packet, tmp.packet, 15, 16);\n}\n#define PACK_OUTPUT_2(OUTPUT, INPUT, INDEX, STRIDE)         \\\n  EIGEN_INSERT_8f_INTO_16f(OUTPUT[INDEX], INPUT[2 * INDEX], \\\n                           INPUT[2 * INDEX + STRIDE]);\n\nEIGEN_DEVICE_FUNC inline void ptranspose(PacketBlock<Packet16f, 4>& kernel) {\n  __m512 T0 = _mm512_unpacklo_ps(kernel.packet[0], kernel.packet[1]);\n  __m512 T1 = _mm512_unpackhi_ps(kernel.packet[0], kernel.packet[1]);\n  __m512 T2 = _mm512_unpacklo_ps(kernel.packet[2], kernel.packet[3]);\n  __m512 T3 = _mm512_unpackhi_ps(kernel.packet[2], kernel.packet[3]);\n\n  __m512 S0 = _mm512_shuffle_ps(T0, T2, _MM_SHUFFLE(1, 0, 1, 0));\n  __m512 S1 = _mm512_shuffle_ps(T0, T2, _MM_SHUFFLE(3, 2, 3, 2));\n  __m512 S2 = _mm512_shuffle_ps(T1, T3, _MM_SHUFFLE(1, 0, 1, 0));\n  __m512 S3 = _mm512_shuffle_ps(T1, T3, _MM_SHUFFLE(3, 2, 3, 2));\n\n  EIGEN_EXTRACT_8f_FROM_16f(S0, S0);\n  EIGEN_EXTRACT_8f_FROM_16f(S1, S1);\n  EIGEN_EXTRACT_8f_FROM_16f(S2, S2);\n  EIGEN_EXTRACT_8f_FROM_16f(S3, S3);\n\n  PacketBlock<Packet8f, 8> tmp;\n\n  tmp.packet[0] = _mm256_permute2f128_ps(S0_0, S1_0, 0x20);\n  tmp.packet[1] = _mm256_permute2f128_ps(S2_0, S3_0, 0x20);\n  tmp.packet[2] = _mm256_permute2f128_ps(S0_0, S1_0, 0x31);\n  tmp.packet[3] = _mm256_permute2f128_ps(S2_0, S3_0, 0x31);\n\n  tmp.packet[4] = _mm256_permute2f128_ps(S0_1, S1_1, 0x20);\n  tmp.packet[5] = _mm256_permute2f128_ps(S2_1, S3_1, 0x20);\n  tmp.packet[6] = _mm256_permute2f128_ps(S0_1, S1_1, 0x31);\n  tmp.packet[7] = _mm256_permute2f128_ps(S2_1, S3_1, 0x31);\n\n  PACK_OUTPUT_2(kernel.packet, tmp.packet, 0, 1);\n  PACK_OUTPUT_2(kernel.packet, tmp.packet, 1, 1);\n  PACK_OUTPUT_2(kernel.packet, tmp.packet, 2, 1);\n  PACK_OUTPUT_2(kernel.packet, tmp.packet, 3, 1);\n}\n\n#define PACK_OUTPUT_SQ_D(OUTPUT, INPUT, INDEX, STRIDE)                \\\n  OUTPUT[INDEX] = _mm512_insertf64x4(OUTPUT[INDEX], INPUT[INDEX], 0); \\\n  OUTPUT[INDEX] = _mm512_insertf64x4(OUTPUT[INDEX], INPUT[INDEX + STRIDE], 1);\n\n#define PACK_OUTPUT_D(OUTPUT, INPUT, INDEX, STRIDE)                         \\\n  OUTPUT[INDEX] = _mm512_insertf64x4(OUTPUT[INDEX], INPUT[(2 * INDEX)], 0); \\\n  OUTPUT[INDEX] =                                                           \\\n      _mm512_insertf64x4(OUTPUT[INDEX], INPUT[(2 * INDEX) + STRIDE], 1);\n\nEIGEN_DEVICE_FUNC inline void ptranspose(PacketBlock<Packet8d, 4>& kernel) {\n  __m512d T0 = _mm512_shuffle_pd(kernel.packet[0], kernel.packet[1], 0);\n  __m512d T1 = _mm512_shuffle_pd(kernel.packet[0], kernel.packet[1], 0xff);\n  __m512d T2 = _mm512_shuffle_pd(kernel.packet[2], kernel.packet[3], 0);\n  __m512d T3 = _mm512_shuffle_pd(kernel.packet[2], kernel.packet[3], 0xff);\n\n  PacketBlock<Packet4d, 8> tmp;\n\n  tmp.packet[0] = _mm256_permute2f128_pd(_mm512_extractf64x4_pd(T0, 0),\n                                         _mm512_extractf64x4_pd(T2, 0), 0x20);\n  tmp.packet[1] = _mm256_permute2f128_pd(_mm512_extractf64x4_pd(T1, 0),\n                                         _mm512_extractf64x4_pd(T3, 0), 0x20);\n  tmp.packet[2] = _mm256_permute2f128_pd(_mm512_extractf64x4_pd(T0, 0),\n                                         _mm512_extractf64x4_pd(T2, 0), 0x31);\n  tmp.packet[3] = _mm256_permute2f128_pd(_mm512_extractf64x4_pd(T1, 0),\n                                         _mm512_extractf64x4_pd(T3, 0), 0x31);\n\n  tmp.packet[4] = _mm256_permute2f128_pd(_mm512_extractf64x4_pd(T0, 1),\n                                         _mm512_extractf64x4_pd(T2, 1), 0x20);\n  tmp.packet[5] = _mm256_permute2f128_pd(_mm512_extractf64x4_pd(T1, 1),\n                                         _mm512_extractf64x4_pd(T3, 1), 0x20);\n  tmp.packet[6] = _mm256_permute2f128_pd(_mm512_extractf64x4_pd(T0, 1),\n                                         _mm512_extractf64x4_pd(T2, 1), 0x31);\n  tmp.packet[7] = _mm256_permute2f128_pd(_mm512_extractf64x4_pd(T1, 1),\n                                         _mm512_extractf64x4_pd(T3, 1), 0x31);\n\n  PACK_OUTPUT_D(kernel.packet, tmp.packet, 0, 1);\n  PACK_OUTPUT_D(kernel.packet, tmp.packet, 1, 1);\n  PACK_OUTPUT_D(kernel.packet, tmp.packet, 2, 1);\n  PACK_OUTPUT_D(kernel.packet, tmp.packet, 3, 1);\n}\n\nEIGEN_DEVICE_FUNC inline void ptranspose(PacketBlock<Packet8d, 8>& kernel) {\n  __m512d T0 = _mm512_unpacklo_pd(kernel.packet[0], kernel.packet[1]);\n  __m512d T1 = _mm512_unpackhi_pd(kernel.packet[0], kernel.packet[1]);\n  __m512d T2 = _mm512_unpacklo_pd(kernel.packet[2], kernel.packet[3]);\n  __m512d T3 = _mm512_unpackhi_pd(kernel.packet[2], kernel.packet[3]);\n  __m512d T4 = _mm512_unpacklo_pd(kernel.packet[4], kernel.packet[5]);\n  __m512d T5 = _mm512_unpackhi_pd(kernel.packet[4], kernel.packet[5]);\n  __m512d T6 = _mm512_unpacklo_pd(kernel.packet[6], kernel.packet[7]);\n  __m512d T7 = _mm512_unpackhi_pd(kernel.packet[6], kernel.packet[7]);\n\n  PacketBlock<Packet4d, 16> tmp;\n\n  tmp.packet[0] = _mm256_permute2f128_pd(_mm512_extractf64x4_pd(T0, 0),\n                                         _mm512_extractf64x4_pd(T2, 0), 0x20);\n  tmp.packet[1] = _mm256_permute2f128_pd(_mm512_extractf64x4_pd(T1, 0),\n                                         _mm512_extractf64x4_pd(T3, 0), 0x20);\n  tmp.packet[2] = _mm256_permute2f128_pd(_mm512_extractf64x4_pd(T0, 0),\n                                         _mm512_extractf64x4_pd(T2, 0), 0x31);\n  tmp.packet[3] = _mm256_permute2f128_pd(_mm512_extractf64x4_pd(T1, 0),\n                                         _mm512_extractf64x4_pd(T3, 0), 0x31);\n\n  tmp.packet[4] = _mm256_permute2f128_pd(_mm512_extractf64x4_pd(T0, 1),\n                                         _mm512_extractf64x4_pd(T2, 1), 0x20);\n  tmp.packet[5] = _mm256_permute2f128_pd(_mm512_extractf64x4_pd(T1, 1),\n                                         _mm512_extractf64x4_pd(T3, 1), 0x20);\n  tmp.packet[6] = _mm256_permute2f128_pd(_mm512_extractf64x4_pd(T0, 1),\n                                         _mm512_extractf64x4_pd(T2, 1), 0x31);\n  tmp.packet[7] = _mm256_permute2f128_pd(_mm512_extractf64x4_pd(T1, 1),\n                                         _mm512_extractf64x4_pd(T3, 1), 0x31);\n\n  tmp.packet[8] = _mm256_permute2f128_pd(_mm512_extractf64x4_pd(T4, 0),\n                                         _mm512_extractf64x4_pd(T6, 0), 0x20);\n  tmp.packet[9] = _mm256_permute2f128_pd(_mm512_extractf64x4_pd(T5, 0),\n                                         _mm512_extractf64x4_pd(T7, 0), 0x20);\n  tmp.packet[10] = _mm256_permute2f128_pd(_mm512_extractf64x4_pd(T4, 0),\n                                          _mm512_extractf64x4_pd(T6, 0), 0x31);\n  tmp.packet[11] = _mm256_permute2f128_pd(_mm512_extractf64x4_pd(T5, 0),\n                                          _mm512_extractf64x4_pd(T7, 0), 0x31);\n\n  tmp.packet[12] = _mm256_permute2f128_pd(_mm512_extractf64x4_pd(T4, 1),\n                                          _mm512_extractf64x4_pd(T6, 1), 0x20);\n  tmp.packet[13] = _mm256_permute2f128_pd(_mm512_extractf64x4_pd(T5, 1),\n                                          _mm512_extractf64x4_pd(T7, 1), 0x20);\n  tmp.packet[14] = _mm256_permute2f128_pd(_mm512_extractf64x4_pd(T4, 1),\n                                          _mm512_extractf64x4_pd(T6, 1), 0x31);\n  tmp.packet[15] = _mm256_permute2f128_pd(_mm512_extractf64x4_pd(T5, 1),\n                                          _mm512_extractf64x4_pd(T7, 1), 0x31);\n\n  PACK_OUTPUT_SQ_D(kernel.packet, tmp.packet, 0, 8);\n  PACK_OUTPUT_SQ_D(kernel.packet, tmp.packet, 1, 8);\n  PACK_OUTPUT_SQ_D(kernel.packet, tmp.packet, 2, 8);\n  PACK_OUTPUT_SQ_D(kernel.packet, tmp.packet, 3, 8);\n\n  PACK_OUTPUT_SQ_D(kernel.packet, tmp.packet, 4, 8);\n  PACK_OUTPUT_SQ_D(kernel.packet, tmp.packet, 5, 8);\n  PACK_OUTPUT_SQ_D(kernel.packet, tmp.packet, 6, 8);\n  PACK_OUTPUT_SQ_D(kernel.packet, tmp.packet, 7, 8);\n}\ntemplate <>\nEIGEN_STRONG_INLINE Packet16f pblend(const Selector<16>& /*ifPacket*/,\n                                     const Packet16f& /*thenPacket*/,\n                                     const Packet16f& /*elsePacket*/) {\n  assert(false && \"To be implemented\");\n  return Packet16f();\n}\ntemplate <>\nEIGEN_STRONG_INLINE Packet8d pblend(const Selector<8>& /*ifPacket*/,\n                                    const Packet8d& /*thenPacket*/,\n                                    const Packet8d& /*elsePacket*/) {\n  assert(false && \"To be implemented\");\n  return Packet8d();\n}\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_PACKET_MATH_AVX512_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/arch/AltiVec/Complex.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2010-2016 Konstantinos Margaritis <markos@freevec.org>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_COMPLEX32_ALTIVEC_H\n#define EIGEN_COMPLEX32_ALTIVEC_H\n\nnamespace Eigen {\n\nnamespace internal {\n\nstatic Packet4ui  p4ui_CONJ_XOR = vec_mergeh((Packet4ui)p4i_ZERO, (Packet4ui)p4f_ZERO_);//{ 0x00000000, 0x80000000, 0x00000000, 0x80000000 };\n#ifdef __VSX__\n#if defined(_BIG_ENDIAN)\nstatic Packet2ul  p2ul_CONJ_XOR1 = (Packet2ul) vec_sld((Packet4ui) p2d_ZERO_, (Packet4ui) p2l_ZERO, 8);//{ 0x8000000000000000, 0x0000000000000000 };\nstatic Packet2ul  p2ul_CONJ_XOR2 = (Packet2ul) vec_sld((Packet4ui) p2l_ZERO,  (Packet4ui) p2d_ZERO_, 8);//{ 0x8000000000000000, 0x0000000000000000 };\n#else\nstatic Packet2ul  p2ul_CONJ_XOR1 = (Packet2ul) vec_sld((Packet4ui) p2l_ZERO,  (Packet4ui) p2d_ZERO_, 8);//{ 0x8000000000000000, 0x0000000000000000 };\nstatic Packet2ul  p2ul_CONJ_XOR2 = (Packet2ul) vec_sld((Packet4ui) p2d_ZERO_, (Packet4ui) p2l_ZERO, 8);//{ 0x8000000000000000, 0x0000000000000000 };\n#endif\n#endif\n\n//---------- float ----------\nstruct Packet2cf\n{\n  EIGEN_STRONG_INLINE explicit Packet2cf() : v(p4f_ZERO) {}\n  EIGEN_STRONG_INLINE explicit Packet2cf(const Packet4f& a) : v(a) {}\n  Packet4f  v;\n};\n\ntemplate<> struct packet_traits<std::complex<float> >  : default_packet_traits\n{\n  typedef Packet2cf type;\n  typedef Packet2cf half;\n  enum {\n    Vectorizable = 1,\n    AlignedOnScalar = 1,\n    size = 2,\n    HasHalfPacket = 0,\n\n    HasAdd    = 1,\n    HasSub    = 1,\n    HasMul    = 1,\n    HasDiv    = 1,\n    HasNegate = 1,\n    HasAbs    = 0,\n    HasAbs2   = 0,\n    HasMin    = 0,\n    HasMax    = 0,\n#ifdef __VSX__\n    HasBlend  = 1,\n#endif\n    HasSetLinear = 0\n  };\n};\n\ntemplate<> struct unpacket_traits<Packet2cf> { typedef std::complex<float> type; enum {size=2, alignment=Aligned16}; typedef Packet2cf half; };\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pset1<Packet2cf>(const std::complex<float>&  from)\n{\n  Packet2cf res;\n  if((ptrdiff_t(&from) % 16) == 0)\n    res.v = pload<Packet4f>((const float *)&from);\n  else\n    res.v = ploadu<Packet4f>((const float *)&from);\n  res.v = vec_perm(res.v, res.v, p16uc_PSET64_HI);\n  return res;\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pload<Packet2cf>(const std::complex<float>*        from) { return Packet2cf(pload<Packet4f>((const float *) from)); }\ntemplate<> EIGEN_STRONG_INLINE Packet2cf ploadu<Packet2cf>(const std::complex<float>*       from) { return Packet2cf(ploadu<Packet4f>((const float*) from)); }\ntemplate<> EIGEN_STRONG_INLINE Packet2cf ploaddup<Packet2cf>(const std::complex<float>*     from) { return pset1<Packet2cf>(*from); }\n\ntemplate<> EIGEN_STRONG_INLINE void pstore <std::complex<float> >(std::complex<float> *   to, const Packet2cf& from) { pstore((float*)to, from.v); }\ntemplate<> EIGEN_STRONG_INLINE void pstoreu<std::complex<float> >(std::complex<float> *   to, const Packet2cf& from) { pstoreu((float*)to, from.v); }\n\ntemplate<> EIGEN_DEVICE_FUNC inline Packet2cf pgather<std::complex<float>, Packet2cf>(const std::complex<float>* from, Index stride)\n{\n  std::complex<float> EIGEN_ALIGN16 af[2];\n  af[0] = from[0*stride];\n  af[1] = from[1*stride];\n  return pload<Packet2cf>(af);\n}\ntemplate<> EIGEN_DEVICE_FUNC inline void pscatter<std::complex<float>, Packet2cf>(std::complex<float>* to, const Packet2cf& from, Index stride)\n{\n  std::complex<float> EIGEN_ALIGN16 af[2];\n  pstore<std::complex<float> >((std::complex<float> *) af, from);\n  to[0*stride] = af[0];\n  to[1*stride] = af[1];\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cf padd<Packet2cf>(const Packet2cf& a, const Packet2cf& b) { return Packet2cf(a.v + b.v); }\ntemplate<> EIGEN_STRONG_INLINE Packet2cf psub<Packet2cf>(const Packet2cf& a, const Packet2cf& b) { return Packet2cf(a.v - b.v); }\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pnegate(const Packet2cf& a) { return Packet2cf(pnegate(a.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pconj(const Packet2cf& a) { return Packet2cf(pxor<Packet4f>(a.v, reinterpret_cast<Packet4f>(p4ui_CONJ_XOR))); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pmul<Packet2cf>(const Packet2cf& a, const Packet2cf& b)\n{\n  Packet4f v1, v2;\n\n  // Permute and multiply the real parts of a and b\n  v1 = vec_perm(a.v, a.v, p16uc_PSET32_WODD);\n  // Get the imaginary parts of a\n  v2 = vec_perm(a.v, a.v, p16uc_PSET32_WEVEN);\n  // multiply a_re * b \n  v1 = vec_madd(v1, b.v, p4f_ZERO);\n  // multiply a_im * b and get the conjugate result\n  v2 = vec_madd(v2, b.v, p4f_ZERO);\n  v2 = reinterpret_cast<Packet4f>(pxor(v2, reinterpret_cast<Packet4f>(p4ui_CONJ_XOR)));\n  // permute back to a proper order\n  v2 = vec_perm(v2, v2, p16uc_COMPLEX32_REV);\n  \n  return Packet2cf(padd<Packet4f>(v1, v2));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pand   <Packet2cf>(const Packet2cf& a, const Packet2cf& b) { return Packet2cf(pand<Packet4f>(a.v, b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet2cf por    <Packet2cf>(const Packet2cf& a, const Packet2cf& b) { return Packet2cf(por<Packet4f>(a.v, b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pxor   <Packet2cf>(const Packet2cf& a, const Packet2cf& b) { return Packet2cf(pxor<Packet4f>(a.v, b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pandnot<Packet2cf>(const Packet2cf& a, const Packet2cf& b) { return Packet2cf(pandnot<Packet4f>(a.v, b.v)); }\n\ntemplate<> EIGEN_STRONG_INLINE void prefetch<std::complex<float> >(const std::complex<float> * addr)    { EIGEN_PPC_PREFETCH(addr); }\n\ntemplate<> EIGEN_STRONG_INLINE std::complex<float>  pfirst<Packet2cf>(const Packet2cf& a)\n{\n  std::complex<float> EIGEN_ALIGN16 res[2];\n  pstore((float *)&res, a.v);\n\n  return res[0];\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cf preverse(const Packet2cf& a)\n{\n  Packet4f rev_a;\n  rev_a = vec_perm(a.v, a.v, p16uc_COMPLEX32_REV2);\n  return Packet2cf(rev_a);\n}\n\ntemplate<> EIGEN_STRONG_INLINE std::complex<float> predux<Packet2cf>(const Packet2cf& a)\n{\n  Packet4f b;\n  b = vec_sld(a.v, a.v, 8);\n  b = padd<Packet4f>(a.v, b);\n  return pfirst<Packet2cf>(Packet2cf(b));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cf preduxp<Packet2cf>(const Packet2cf* vecs)\n{\n  Packet4f b1, b2;\n#ifdef _BIG_ENDIAN  \n  b1 = vec_sld(vecs[0].v, vecs[1].v, 8);\n  b2 = vec_sld(vecs[1].v, vecs[0].v, 8);\n#else\n  b1 = vec_sld(vecs[1].v, vecs[0].v, 8);\n  b2 = vec_sld(vecs[0].v, vecs[1].v, 8);\n#endif\n  b2 = vec_sld(b2, b2, 8);\n  b2 = padd<Packet4f>(b1, b2);\n\n  return Packet2cf(b2);\n}\n\ntemplate<> EIGEN_STRONG_INLINE std::complex<float> predux_mul<Packet2cf>(const Packet2cf& a)\n{\n  Packet4f b;\n  Packet2cf prod;\n  b = vec_sld(a.v, a.v, 8);\n  prod = pmul<Packet2cf>(a, Packet2cf(b));\n\n  return pfirst<Packet2cf>(prod);\n}\n\ntemplate<int Offset>\nstruct palign_impl<Offset,Packet2cf>\n{\n  static EIGEN_STRONG_INLINE void run(Packet2cf& first, const Packet2cf& second)\n  {\n    if (Offset==1)\n    {\n#ifdef _BIG_ENDIAN\n      first.v = vec_sld(first.v, second.v, 8);\n#else\n      first.v = vec_sld(second.v, first.v, 8);\n#endif\n    }\n  }\n};\n\ntemplate<> struct conj_helper<Packet2cf, Packet2cf, false,true>\n{\n  EIGEN_STRONG_INLINE Packet2cf pmadd(const Packet2cf& x, const Packet2cf& y, const Packet2cf& c) const\n  { return padd(pmul(x,y),c); }\n\n  EIGEN_STRONG_INLINE Packet2cf pmul(const Packet2cf& a, const Packet2cf& b) const\n  {\n    return internal::pmul(a, pconj(b));\n  }\n};\n\ntemplate<> struct conj_helper<Packet2cf, Packet2cf, true,false>\n{\n  EIGEN_STRONG_INLINE Packet2cf pmadd(const Packet2cf& x, const Packet2cf& y, const Packet2cf& c) const\n  { return padd(pmul(x,y),c); }\n\n  EIGEN_STRONG_INLINE Packet2cf pmul(const Packet2cf& a, const Packet2cf& b) const\n  {\n    return internal::pmul(pconj(a), b);\n  }\n};\n\ntemplate<> struct conj_helper<Packet2cf, Packet2cf, true,true>\n{\n  EIGEN_STRONG_INLINE Packet2cf pmadd(const Packet2cf& x, const Packet2cf& y, const Packet2cf& c) const\n  { return padd(pmul(x,y),c); }\n\n  EIGEN_STRONG_INLINE Packet2cf pmul(const Packet2cf& a, const Packet2cf& b) const\n  {\n    return pconj(internal::pmul(a, b));\n  }\n};\n\ntemplate<> struct conj_helper<Packet4f, Packet2cf, false,false>\n{\n  EIGEN_STRONG_INLINE Packet2cf pmadd(const Packet4f& x, const Packet2cf& y, const Packet2cf& c) const\n  { return padd(c, pmul(x,y)); }\n\n  EIGEN_STRONG_INLINE Packet2cf pmul(const Packet4f& x, const Packet2cf& y) const\n  { return Packet2cf(internal::pmul<Packet4f>(x, y.v)); }\n};\n\ntemplate<> struct conj_helper<Packet2cf, Packet4f, false,false>\n{\n  EIGEN_STRONG_INLINE Packet2cf pmadd(const Packet2cf& x, const Packet4f& y, const Packet2cf& c) const\n  { return padd(c, pmul(x,y)); }\n\n  EIGEN_STRONG_INLINE Packet2cf pmul(const Packet2cf& x, const Packet4f& y) const\n  { return Packet2cf(internal::pmul<Packet4f>(x.v, y)); }\n};\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pdiv<Packet2cf>(const Packet2cf& a, const Packet2cf& b)\n{\n  // TODO optimize it for AltiVec\n  Packet2cf res = conj_helper<Packet2cf,Packet2cf,false,true>().pmul(a, b);\n  Packet4f s = pmul<Packet4f>(b.v, b.v);\n  return Packet2cf(pdiv(res.v, padd<Packet4f>(s, vec_perm(s, s, p16uc_COMPLEX32_REV))));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pcplxflip<Packet2cf>(const Packet2cf& x)\n{\n  return Packet2cf(vec_perm(x.v, x.v, p16uc_COMPLEX32_REV));\n}\n\nEIGEN_STRONG_INLINE void ptranspose(PacketBlock<Packet2cf,2>& kernel)\n{\n  Packet4f tmp = vec_perm(kernel.packet[0].v, kernel.packet[1].v, p16uc_TRANSPOSE64_HI);\n  kernel.packet[1].v = vec_perm(kernel.packet[0].v, kernel.packet[1].v, p16uc_TRANSPOSE64_LO);\n  kernel.packet[0].v = tmp;\n}\n\n#ifdef __VSX__\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pblend(const Selector<2>& ifPacket, const Packet2cf& thenPacket, const Packet2cf& elsePacket) {\n  Packet2cf result;\n  result.v = reinterpret_cast<Packet4f>(pblend<Packet2d>(ifPacket, reinterpret_cast<Packet2d>(thenPacket.v), reinterpret_cast<Packet2d>(elsePacket.v)));\n  return result;\n}\n#endif\n\n//---------- double ----------\n#ifdef __VSX__\nstruct Packet1cd\n{\n  EIGEN_STRONG_INLINE Packet1cd() {}\n  EIGEN_STRONG_INLINE explicit Packet1cd(const Packet2d& a) : v(a) {}\n  Packet2d v;\n};\n\ntemplate<> struct packet_traits<std::complex<double> >  : default_packet_traits\n{\n  typedef Packet1cd type;\n  typedef Packet1cd half;\n  enum {\n    Vectorizable = 1,\n    AlignedOnScalar = 0,\n    size = 1,\n    HasHalfPacket = 0,\n\n    HasAdd    = 1,\n    HasSub    = 1,\n    HasMul    = 1,\n    HasDiv    = 1,\n    HasNegate = 1,\n    HasAbs    = 0,\n    HasAbs2   = 0,\n    HasMin    = 0,\n    HasMax    = 0,\n    HasSetLinear = 0\n  };\n};\n\ntemplate<> struct unpacket_traits<Packet1cd> { typedef std::complex<double> type; enum {size=1, alignment=Aligned16}; typedef Packet1cd half; };\n\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pload <Packet1cd>(const std::complex<double>* from) { return Packet1cd(pload<Packet2d>((const double*)from)); }\ntemplate<> EIGEN_STRONG_INLINE Packet1cd ploadu<Packet1cd>(const std::complex<double>* from) { return Packet1cd(ploadu<Packet2d>((const double*)from)); }\ntemplate<> EIGEN_STRONG_INLINE void pstore <std::complex<double> >(std::complex<double> *   to, const Packet1cd& from) { pstore((double*)to, from.v); }\ntemplate<> EIGEN_STRONG_INLINE void pstoreu<std::complex<double> >(std::complex<double> *   to, const Packet1cd& from) { pstoreu((double*)to, from.v); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pset1<Packet1cd>(const std::complex<double>&  from)\n{ /* here we really have to use unaligned loads :( */ return ploadu<Packet1cd>(&from); }\n\ntemplate<> EIGEN_DEVICE_FUNC inline Packet1cd pgather<std::complex<double>, Packet1cd>(const std::complex<double>* from, Index stride)\n{\n  std::complex<double> EIGEN_ALIGN16 af[2];\n  af[0] = from[0*stride];\n  af[1] = from[1*stride];\n  return pload<Packet1cd>(af);\n}\ntemplate<> EIGEN_DEVICE_FUNC inline void pscatter<std::complex<double>, Packet1cd>(std::complex<double>* to, const Packet1cd& from, Index stride)\n{\n  std::complex<double> EIGEN_ALIGN16 af[2];\n  pstore<std::complex<double> >(af, from);\n  to[0*stride] = af[0];\n  to[1*stride] = af[1];\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet1cd padd<Packet1cd>(const Packet1cd& a, const Packet1cd& b) { return Packet1cd(a.v + b.v); }\ntemplate<> EIGEN_STRONG_INLINE Packet1cd psub<Packet1cd>(const Packet1cd& a, const Packet1cd& b) { return Packet1cd(a.v - b.v); }\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pnegate(const Packet1cd& a) { return Packet1cd(pnegate(Packet2d(a.v))); }\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pconj(const Packet1cd& a) { return Packet1cd(pxor(a.v, reinterpret_cast<Packet2d>(p2ul_CONJ_XOR2))); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pmul<Packet1cd>(const Packet1cd& a, const Packet1cd& b)\n{\n  Packet2d a_re, a_im, v1, v2;\n\n  // Permute and multiply the real parts of a and b\n  a_re = vec_perm(a.v, a.v, p16uc_PSET64_HI);\n  // Get the imaginary parts of a\n  a_im = vec_perm(a.v, a.v, p16uc_PSET64_LO);\n  // multiply a_re * b\n  v1 = vec_madd(a_re, b.v, p2d_ZERO);\n  // multiply a_im * b and get the conjugate result\n  v2 = vec_madd(a_im, b.v, p2d_ZERO);\n  v2 = reinterpret_cast<Packet2d>(vec_sld(reinterpret_cast<Packet4ui>(v2), reinterpret_cast<Packet4ui>(v2), 8));\n  v2 = pxor(v2, reinterpret_cast<Packet2d>(p2ul_CONJ_XOR1));\n\n  return Packet1cd(padd<Packet2d>(v1, v2));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pand   <Packet1cd>(const Packet1cd& a, const Packet1cd& b) { return Packet1cd(pand(a.v,b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet1cd por    <Packet1cd>(const Packet1cd& a, const Packet1cd& b) { return Packet1cd(por(a.v,b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pxor   <Packet1cd>(const Packet1cd& a, const Packet1cd& b) { return Packet1cd(pxor(a.v,b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pandnot<Packet1cd>(const Packet1cd& a, const Packet1cd& b) { return Packet1cd(pandnot(a.v, b.v)); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet1cd ploaddup<Packet1cd>(const std::complex<double>*     from)  { return pset1<Packet1cd>(*from); }\n\ntemplate<> EIGEN_STRONG_INLINE void prefetch<std::complex<double> >(const std::complex<double> * addr)    { EIGEN_PPC_PREFETCH(addr); }\n\ntemplate<> EIGEN_STRONG_INLINE std::complex<double>  pfirst<Packet1cd>(const Packet1cd& a)\n{\n  std::complex<double> EIGEN_ALIGN16 res[2];\n  pstore<std::complex<double> >(res, a);\n\n  return res[0];\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet1cd preverse(const Packet1cd& a) { return a; }\n\ntemplate<> EIGEN_STRONG_INLINE std::complex<double> predux<Packet1cd>(const Packet1cd& a) { return pfirst(a); }\ntemplate<> EIGEN_STRONG_INLINE Packet1cd preduxp<Packet1cd>(const Packet1cd* vecs)        { return vecs[0]; }\n\ntemplate<> EIGEN_STRONG_INLINE std::complex<double> predux_mul<Packet1cd>(const Packet1cd& a) { return pfirst(a); }\n\ntemplate<int Offset>\nstruct palign_impl<Offset,Packet1cd>\n{\n  static EIGEN_STRONG_INLINE void run(Packet1cd& /*first*/, const Packet1cd& /*second*/)\n  {\n    // FIXME is it sure we never have to align a Packet1cd?\n    // Even though a std::complex<double> has 16 bytes, it is not necessarily aligned on a 16 bytes boundary...\n  }\n};\n\ntemplate<> struct conj_helper<Packet1cd, Packet1cd, false,true>\n{\n  EIGEN_STRONG_INLINE Packet1cd pmadd(const Packet1cd& x, const Packet1cd& y, const Packet1cd& c) const\n  { return padd(pmul(x,y),c); }\n\n  EIGEN_STRONG_INLINE Packet1cd pmul(const Packet1cd& a, const Packet1cd& b) const\n  {\n    return internal::pmul(a, pconj(b));\n  }\n};\n\ntemplate<> struct conj_helper<Packet1cd, Packet1cd, true,false>\n{\n  EIGEN_STRONG_INLINE Packet1cd pmadd(const Packet1cd& x, const Packet1cd& y, const Packet1cd& c) const\n  { return padd(pmul(x,y),c); }\n\n  EIGEN_STRONG_INLINE Packet1cd pmul(const Packet1cd& a, const Packet1cd& b) const\n  {\n    return internal::pmul(pconj(a), b);\n  }\n};\n\ntemplate<> struct conj_helper<Packet1cd, Packet1cd, true,true>\n{\n  EIGEN_STRONG_INLINE Packet1cd pmadd(const Packet1cd& x, const Packet1cd& y, const Packet1cd& c) const\n  { return padd(pmul(x,y),c); }\n\n  EIGEN_STRONG_INLINE Packet1cd pmul(const Packet1cd& a, const Packet1cd& b) const\n  {\n    return pconj(internal::pmul(a, b));\n  }\n};\ntemplate<> struct conj_helper<Packet2d, Packet1cd, false,false>\n{\n  EIGEN_STRONG_INLINE Packet1cd pmadd(const Packet2d& x, const Packet1cd& y, const Packet1cd& c) const\n  { return padd(c, pmul(x,y)); }\n\n  EIGEN_STRONG_INLINE Packet1cd pmul(const Packet2d& x, const Packet1cd& y) const\n  { return Packet1cd(internal::pmul<Packet2d>(x, y.v)); }\n};\n\ntemplate<> struct conj_helper<Packet1cd, Packet2d, false,false>\n{\n  EIGEN_STRONG_INLINE Packet1cd pmadd(const Packet1cd& x, const Packet2d& y, const Packet1cd& c) const\n  { return padd(c, pmul(x,y)); }\n\n  EIGEN_STRONG_INLINE Packet1cd pmul(const Packet1cd& x, const Packet2d& y) const\n  { return Packet1cd(internal::pmul<Packet2d>(x.v, y)); }\n};\n\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pdiv<Packet1cd>(const Packet1cd& a, const Packet1cd& b)\n{\n  // TODO optimize it for AltiVec\n  Packet1cd res = conj_helper<Packet1cd,Packet1cd,false,true>().pmul(a,b);\n  Packet2d s = pmul<Packet2d>(b.v, b.v);\n  return Packet1cd(pdiv(res.v, padd<Packet2d>(s, vec_perm(s, s, p16uc_REVERSE64))));\n}\n\nEIGEN_STRONG_INLINE Packet1cd pcplxflip/*<Packet1cd>*/(const Packet1cd& x)\n{\n  return Packet1cd(preverse(Packet2d(x.v)));\n}\n\nEIGEN_STRONG_INLINE void ptranspose(PacketBlock<Packet1cd,2>& kernel)\n{\n  Packet2d tmp = vec_perm(kernel.packet[0].v, kernel.packet[1].v, p16uc_TRANSPOSE64_HI);\n  kernel.packet[1].v = vec_perm(kernel.packet[0].v, kernel.packet[1].v, p16uc_TRANSPOSE64_LO);\n  kernel.packet[0].v = tmp;\n}\n#endif // __VSX__\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_COMPLEX32_ALTIVEC_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/arch/AltiVec/MathFunctions.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2007 Julien Pommier\n// Copyright (C) 2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2016 Konstantinos Margaritis <markos@freevec.org>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n/* The sin, cos, exp, and log functions of this file come from\n * Julien Pommier's sse math library: http://gruntthepeon.free.fr/ssemath/\n */\n\n#ifndef EIGEN_MATH_FUNCTIONS_ALTIVEC_H\n#define EIGEN_MATH_FUNCTIONS_ALTIVEC_H\n\nnamespace Eigen {\n\nnamespace internal {\n\nstatic _EIGEN_DECLARE_CONST_Packet4f(1 , 1.0f);\nstatic _EIGEN_DECLARE_CONST_Packet4f(half, 0.5f);\nstatic _EIGEN_DECLARE_CONST_Packet4i(0x7f, 0x7f);\nstatic _EIGEN_DECLARE_CONST_Packet4i(23, 23);\n\nstatic _EIGEN_DECLARE_CONST_Packet4f_FROM_INT(inv_mant_mask, ~0x7f800000);\n\n/* the smallest non denormalized float number */\nstatic _EIGEN_DECLARE_CONST_Packet4f_FROM_INT(min_norm_pos,  0x00800000);\nstatic _EIGEN_DECLARE_CONST_Packet4f_FROM_INT(minus_inf,     0xff800000); // -1.f/0.f\nstatic _EIGEN_DECLARE_CONST_Packet4f_FROM_INT(minus_nan,     0xffffffff);\n  \n/* natural logarithm computed for 4 simultaneous float\n  return NaN for x <= 0\n*/\nstatic _EIGEN_DECLARE_CONST_Packet4f(cephes_SQRTHF, 0.707106781186547524f);\nstatic _EIGEN_DECLARE_CONST_Packet4f(cephes_log_p0, 7.0376836292E-2f);\nstatic _EIGEN_DECLARE_CONST_Packet4f(cephes_log_p1, - 1.1514610310E-1f);\nstatic _EIGEN_DECLARE_CONST_Packet4f(cephes_log_p2, 1.1676998740E-1f);\nstatic _EIGEN_DECLARE_CONST_Packet4f(cephes_log_p3, - 1.2420140846E-1f);\nstatic _EIGEN_DECLARE_CONST_Packet4f(cephes_log_p4, + 1.4249322787E-1f);\nstatic _EIGEN_DECLARE_CONST_Packet4f(cephes_log_p5, - 1.6668057665E-1f);\nstatic _EIGEN_DECLARE_CONST_Packet4f(cephes_log_p6, + 2.0000714765E-1f);\nstatic _EIGEN_DECLARE_CONST_Packet4f(cephes_log_p7, - 2.4999993993E-1f);\nstatic _EIGEN_DECLARE_CONST_Packet4f(cephes_log_p8, + 3.3333331174E-1f);\nstatic _EIGEN_DECLARE_CONST_Packet4f(cephes_log_q1, -2.12194440e-4f);\nstatic _EIGEN_DECLARE_CONST_Packet4f(cephes_log_q2, 0.693359375f);\n\nstatic _EIGEN_DECLARE_CONST_Packet4f(exp_hi,  88.3762626647950f);\nstatic _EIGEN_DECLARE_CONST_Packet4f(exp_lo, -88.3762626647949f);\n\nstatic _EIGEN_DECLARE_CONST_Packet4f(cephes_LOG2EF, 1.44269504088896341f);\nstatic _EIGEN_DECLARE_CONST_Packet4f(cephes_exp_C1, 0.693359375f);\nstatic _EIGEN_DECLARE_CONST_Packet4f(cephes_exp_C2, -2.12194440e-4f);\n\nstatic _EIGEN_DECLARE_CONST_Packet4f(cephes_exp_p0, 1.9875691500E-4f);\nstatic _EIGEN_DECLARE_CONST_Packet4f(cephes_exp_p1, 1.3981999507E-3f);\nstatic _EIGEN_DECLARE_CONST_Packet4f(cephes_exp_p2, 8.3334519073E-3f);\nstatic _EIGEN_DECLARE_CONST_Packet4f(cephes_exp_p3, 4.1665795894E-2f);\nstatic _EIGEN_DECLARE_CONST_Packet4f(cephes_exp_p4, 1.6666665459E-1f);\nstatic _EIGEN_DECLARE_CONST_Packet4f(cephes_exp_p5, 5.0000001201E-1f);\n\n#ifdef __VSX__\nstatic _EIGEN_DECLARE_CONST_Packet2d(1 , 1.0);\nstatic _EIGEN_DECLARE_CONST_Packet2d(2 , 2.0);\nstatic _EIGEN_DECLARE_CONST_Packet2d(half, 0.5);\n\nstatic _EIGEN_DECLARE_CONST_Packet2d(exp_hi,  709.437);\nstatic _EIGEN_DECLARE_CONST_Packet2d(exp_lo, -709.436139303);\n\nstatic _EIGEN_DECLARE_CONST_Packet2d(cephes_LOG2EF, 1.4426950408889634073599);\n\nstatic _EIGEN_DECLARE_CONST_Packet2d(cephes_exp_p0, 1.26177193074810590878e-4);\nstatic _EIGEN_DECLARE_CONST_Packet2d(cephes_exp_p1, 3.02994407707441961300e-2);\nstatic _EIGEN_DECLARE_CONST_Packet2d(cephes_exp_p2, 9.99999999999999999910e-1);\n\nstatic _EIGEN_DECLARE_CONST_Packet2d(cephes_exp_q0, 3.00198505138664455042e-6);\nstatic _EIGEN_DECLARE_CONST_Packet2d(cephes_exp_q1, 2.52448340349684104192e-3);\nstatic _EIGEN_DECLARE_CONST_Packet2d(cephes_exp_q2, 2.27265548208155028766e-1);\nstatic _EIGEN_DECLARE_CONST_Packet2d(cephes_exp_q3, 2.00000000000000000009e0);\n\nstatic _EIGEN_DECLARE_CONST_Packet2d(cephes_exp_C1, 0.693145751953125);\nstatic _EIGEN_DECLARE_CONST_Packet2d(cephes_exp_C2, 1.42860682030941723212e-6);\n\nstatic Packet2l p2l_1023 = { 1023, 1023 };\nstatic Packet2ul p2ul_52 = { 52, 52 };\n\n#endif\n\ntemplate<> EIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED\nPacket4f plog<Packet4f>(const Packet4f& _x)\n{\n  Packet4f x = _x;\n\n  Packet4i emm0;\n\n  /* isvalid_mask is 0 if x < 0 or x is NaN. */\n  Packet4ui isvalid_mask = reinterpret_cast<Packet4ui>(vec_cmpge(x, p4f_ZERO));\n  Packet4ui iszero_mask = reinterpret_cast<Packet4ui>(vec_cmpeq(x, p4f_ZERO));\n\n  x = pmax(x, p4f_min_norm_pos);  /* cut off denormalized stuff */\n  emm0 = vec_sr(reinterpret_cast<Packet4i>(x),\n                reinterpret_cast<Packet4ui>(p4i_23));\n\n  /* keep only the fractional part */\n  x = pand(x, p4f_inv_mant_mask);\n  x = por(x, p4f_half);\n\n  emm0 = psub(emm0, p4i_0x7f);\n  Packet4f e = padd(vec_ctf(emm0, 0), p4f_1);\n\n  /* part2:\n     if( x < SQRTHF ) {\n       e -= 1;\n       x = x + x - 1.0;\n     } else { x = x - 1.0; }\n  */\n  Packet4f mask = reinterpret_cast<Packet4f>(vec_cmplt(x, p4f_cephes_SQRTHF));\n  Packet4f tmp = pand(x, mask);\n  x = psub(x, p4f_1);\n  e = psub(e, pand(p4f_1, mask));\n  x = padd(x, tmp);\n\n  Packet4f x2 = pmul(x,x);\n  Packet4f x3 = pmul(x2,x);\n\n  Packet4f y, y1, y2;\n  y  = pmadd(p4f_cephes_log_p0, x, p4f_cephes_log_p1);\n  y1 = pmadd(p4f_cephes_log_p3, x, p4f_cephes_log_p4);\n  y2 = pmadd(p4f_cephes_log_p6, x, p4f_cephes_log_p7);\n  y  = pmadd(y , x, p4f_cephes_log_p2);\n  y1 = pmadd(y1, x, p4f_cephes_log_p5);\n  y2 = pmadd(y2, x, p4f_cephes_log_p8);\n  y = pmadd(y, x3, y1);\n  y = pmadd(y, x3, y2);\n  y = pmul(y, x3);\n\n  y1 = pmul(e, p4f_cephes_log_q1);\n  tmp = pmul(x2, p4f_half);\n  y = padd(y, y1);\n  x = psub(x, tmp);\n  y2 = pmul(e, p4f_cephes_log_q2);\n  x = padd(x, y);\n  x = padd(x, y2);\n  // negative arg will be NAN, 0 will be -INF\n  x = vec_sel(x, p4f_minus_inf, iszero_mask);\n  x = vec_sel(p4f_minus_nan, x, isvalid_mask);\n  return x;\n}\n\ntemplate<> EIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED\nPacket4f pexp<Packet4f>(const Packet4f& _x)\n{\n  Packet4f x = _x;\n\n  Packet4f tmp, fx;\n  Packet4i emm0;\n\n  // clamp x\n  x = pmax(pmin(x, p4f_exp_hi), p4f_exp_lo);\n\n  // express exp(x) as exp(g + n*log(2))\n  fx = pmadd(x, p4f_cephes_LOG2EF, p4f_half);\n\n  fx = pfloor(fx);\n\n  tmp = pmul(fx, p4f_cephes_exp_C1);\n  Packet4f z = pmul(fx, p4f_cephes_exp_C2);\n  x = psub(x, tmp);\n  x = psub(x, z);\n\n  z = pmul(x,x);\n\n  Packet4f y = p4f_cephes_exp_p0;\n  y = pmadd(y, x, p4f_cephes_exp_p1);\n  y = pmadd(y, x, p4f_cephes_exp_p2);\n  y = pmadd(y, x, p4f_cephes_exp_p3);\n  y = pmadd(y, x, p4f_cephes_exp_p4);\n  y = pmadd(y, x, p4f_cephes_exp_p5);\n  y = pmadd(y, z, x);\n  y = padd(y, p4f_1);\n\n  // build 2^n\n  emm0 = vec_cts(fx, 0);\n  emm0 = vec_add(emm0, p4i_0x7f);\n  emm0 = vec_sl(emm0, reinterpret_cast<Packet4ui>(p4i_23));\n\n  // Altivec's max & min operators just drop silent NaNs. Check NaNs in \n  // inputs and return them unmodified.\n  Packet4ui isnumber_mask = reinterpret_cast<Packet4ui>(vec_cmpeq(_x, _x));\n  return vec_sel(_x, pmax(pmul(y, reinterpret_cast<Packet4f>(emm0)), _x),\n                 isnumber_mask);\n}\n\n#ifndef EIGEN_COMP_CLANG\ntemplate<> EIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED\nPacket4f prsqrt<Packet4f>(const Packet4f& x)\n{\n  return  vec_rsqrt(x);\n}\n#endif\n\n#ifdef __VSX__\n#ifndef EIGEN_COMP_CLANG\ntemplate<> EIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED\nPacket2d prsqrt<Packet2d>(const Packet2d& x)\n{\n  return  vec_rsqrt(x);\n}\n#endif\n\ntemplate<> EIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED\nPacket4f psqrt<Packet4f>(const Packet4f& x)\n{\n  return  vec_sqrt(x);\n}\n\ntemplate<> EIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED\nPacket2d psqrt<Packet2d>(const Packet2d& x)\n{\n  return  vec_sqrt(x);\n}\n\n// VSX support varies between different compilers and even different\n// versions of the same compiler.  For gcc version >= 4.9.3, we can use\n// vec_cts to efficiently convert Packet2d to Packet2l.  Otherwise, use\n// a slow version that works with older compilers. \n// Update: apparently vec_cts/vec_ctf intrinsics for 64-bit doubles\n// are buggy, https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70963\nstatic inline Packet2l ConvertToPacket2l(const Packet2d& x) {\n#if EIGEN_GNUC_AT_LEAST(5, 4) || \\\n    (EIGEN_GNUC_AT(6, 1) && __GNUC_PATCHLEVEL__ >= 1)\n  return vec_cts(x, 0);    // TODO: check clang version.\n#else\n  double tmp[2];\n  memcpy(tmp, &x, sizeof(tmp));\n  Packet2l l = { static_cast<long long>(tmp[0]),\n                 static_cast<long long>(tmp[1]) };\n  return l;\n#endif\n}\n\ntemplate<> EIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED\nPacket2d pexp<Packet2d>(const Packet2d& _x)\n{\n  Packet2d x = _x;\n\n  Packet2d tmp, fx;\n  Packet2l emm0;\n\n  // clamp x\n  x = pmax(pmin(x, p2d_exp_hi), p2d_exp_lo);\n\n  /* express exp(x) as exp(g + n*log(2)) */\n  fx = pmadd(x, p2d_cephes_LOG2EF, p2d_half);\n\n  fx = pfloor(fx);\n\n  tmp = pmul(fx, p2d_cephes_exp_C1);\n  Packet2d z = pmul(fx, p2d_cephes_exp_C2);\n  x = psub(x, tmp);\n  x = psub(x, z);\n\n  Packet2d x2 = pmul(x,x);\n\n  Packet2d px = p2d_cephes_exp_p0;\n  px = pmadd(px, x2, p2d_cephes_exp_p1);\n  px = pmadd(px, x2, p2d_cephes_exp_p2);\n  px = pmul (px, x);\n\n  Packet2d qx = p2d_cephes_exp_q0;\n  qx = pmadd(qx, x2, p2d_cephes_exp_q1);\n  qx = pmadd(qx, x2, p2d_cephes_exp_q2);\n  qx = pmadd(qx, x2, p2d_cephes_exp_q3);\n\n  x = pdiv(px,psub(qx,px));\n  x = pmadd(p2d_2,x,p2d_1);\n\n  // build 2^n\n  emm0 = ConvertToPacket2l(fx);\n\n#ifdef __POWER8_VECTOR__ \n  emm0 = vec_add(emm0, p2l_1023);\n  emm0 = vec_sl(emm0, p2ul_52);\n#else\n  // Code is a bit complex for POWER7.  There is actually a\n  // vec_xxsldi intrinsic but it is not supported by some gcc versions.\n  // So we shift (52-32) bits and do a word swap with zeros.\n  _EIGEN_DECLARE_CONST_Packet4i(1023, 1023);\n  _EIGEN_DECLARE_CONST_Packet4i(20, 20);    // 52 - 32\n\n  Packet4i emm04i = reinterpret_cast<Packet4i>(emm0);\n  emm04i = vec_add(emm04i, p4i_1023);\n  emm04i = vec_sl(emm04i, reinterpret_cast<Packet4ui>(p4i_20));\n  static const Packet16uc perm = {\n    0x14, 0x15, 0x16, 0x17, 0x00, 0x01, 0x02, 0x03, \n    0x1c, 0x1d, 0x1e, 0x1f, 0x08, 0x09, 0x0a, 0x0b };\n#ifdef  _BIG_ENDIAN\n  emm0 = reinterpret_cast<Packet2l>(vec_perm(p4i_ZERO, emm04i, perm));\n#else\n  emm0 = reinterpret_cast<Packet2l>(vec_perm(emm04i, p4i_ZERO, perm));\n#endif\n\n#endif\n\n  // Altivec's max & min operators just drop silent NaNs. Check NaNs in \n  // inputs and return them unmodified.\n  Packet2ul isnumber_mask = reinterpret_cast<Packet2ul>(vec_cmpeq(_x, _x));\n  return vec_sel(_x, pmax(pmul(x, reinterpret_cast<Packet2d>(emm0)), _x),\n                 isnumber_mask);\n}\n#endif\n\n}  // end namespace internal\n\n}  // end namespace Eigen\n\n#endif  // EIGEN_MATH_FUNCTIONS_ALTIVEC_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/arch/AltiVec/PacketMath.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2016 Konstantinos Margaritis <markos@freevec.org>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_PACKET_MATH_ALTIVEC_H\n#define EIGEN_PACKET_MATH_ALTIVEC_H\n\nnamespace Eigen {\n\nnamespace internal {\n\n#ifndef EIGEN_CACHEFRIENDLY_PRODUCT_THRESHOLD\n#define EIGEN_CACHEFRIENDLY_PRODUCT_THRESHOLD 4\n#endif\n\n#ifndef EIGEN_HAS_SINGLE_INSTRUCTION_MADD\n#define EIGEN_HAS_SINGLE_INSTRUCTION_MADD\n#endif\n\n#ifndef EIGEN_HAS_SINGLE_INSTRUCTION_CJMADD\n#define EIGEN_HAS_SINGLE_INSTRUCTION_CJMADD\n#endif\n\n// NOTE Altivec has 32 registers, but Eigen only accepts a value of 8 or 16\n#ifndef EIGEN_ARCH_DEFAULT_NUMBER_OF_REGISTERS\n#define EIGEN_ARCH_DEFAULT_NUMBER_OF_REGISTERS  32\n#endif\n\ntypedef __vector float          Packet4f;\ntypedef __vector int            Packet4i;\ntypedef __vector unsigned int   Packet4ui;\ntypedef __vector __bool int     Packet4bi;\ntypedef __vector short int      Packet8i;\ntypedef __vector unsigned char  Packet16uc;\n\n// We don't want to write the same code all the time, but we need to reuse the constants\n// and it doesn't really work to declare them global, so we define macros instead\n\n#define _EIGEN_DECLARE_CONST_FAST_Packet4f(NAME,X) \\\n  Packet4f p4f_##NAME = reinterpret_cast<Packet4f>(vec_splat_s32(X))\n\n#define _EIGEN_DECLARE_CONST_FAST_Packet4i(NAME,X) \\\n  Packet4i p4i_##NAME = vec_splat_s32(X)\n\n#define _EIGEN_DECLARE_CONST_Packet4f(NAME,X) \\\n  Packet4f p4f_##NAME = pset1<Packet4f>(X)\n\n#define _EIGEN_DECLARE_CONST_Packet4i(NAME,X) \\\n  Packet4i p4i_##NAME = pset1<Packet4i>(X)\n\n#define _EIGEN_DECLARE_CONST_Packet2d(NAME,X) \\\n  Packet2d p2d_##NAME = pset1<Packet2d>(X)\n\n#define _EIGEN_DECLARE_CONST_Packet2l(NAME,X) \\\n  Packet2l p2l_##NAME = pset1<Packet2l>(X)\n\n#define _EIGEN_DECLARE_CONST_Packet4f_FROM_INT(NAME,X) \\\n  const Packet4f p4f_##NAME = reinterpret_cast<Packet4f>(pset1<Packet4i>(X))\n\n#define DST_CHAN 1\n#define DST_CTRL(size, count, stride) (((size) << 24) | ((count) << 16) | (stride))\n\n\n// These constants are endian-agnostic\nstatic _EIGEN_DECLARE_CONST_FAST_Packet4f(ZERO, 0); //{ 0.0, 0.0, 0.0, 0.0}\nstatic _EIGEN_DECLARE_CONST_FAST_Packet4i(ZERO, 0); //{ 0, 0, 0, 0,}\nstatic _EIGEN_DECLARE_CONST_FAST_Packet4i(ONE,1); //{ 1, 1, 1, 1}\nstatic _EIGEN_DECLARE_CONST_FAST_Packet4i(MINUS16,-16); //{ -16, -16, -16, -16}\nstatic _EIGEN_DECLARE_CONST_FAST_Packet4i(MINUS1,-1); //{ -1, -1, -1, -1}\nstatic Packet4f p4f_ZERO_ = (Packet4f) vec_sl((Packet4ui)p4i_MINUS1, (Packet4ui)p4i_MINUS1); //{ 0x80000000, 0x80000000, 0x80000000, 0x80000000}\n#ifndef __VSX__\nstatic Packet4f p4f_ONE = vec_ctf(p4i_ONE, 0); //{ 1.0, 1.0, 1.0, 1.0}\n#endif\n\nstatic Packet4f p4f_COUNTDOWN = { 0.0, 1.0, 2.0, 3.0 };\nstatic Packet4i p4i_COUNTDOWN = { 0, 1, 2, 3 };\n\nstatic Packet16uc p16uc_REVERSE32 = { 12,13,14,15, 8,9,10,11, 4,5,6,7, 0,1,2,3 };\nstatic Packet16uc p16uc_DUPLICATE32_HI = { 0,1,2,3, 0,1,2,3, 4,5,6,7, 4,5,6,7 };\n\n// Mask alignment\n#ifdef __PPC64__\n#define _EIGEN_MASK_ALIGNMENT\t0xfffffffffffffff0\n#else\n#define _EIGEN_MASK_ALIGNMENT\t0xfffffff0\n#endif\n\n#define _EIGEN_ALIGNED_PTR(x)\t((ptrdiff_t)(x) & _EIGEN_MASK_ALIGNMENT)\n\n// Handle endianness properly while loading constants\n// Define global static constants:\n#ifdef _BIG_ENDIAN\nstatic Packet16uc p16uc_FORWARD = vec_lvsl(0, (float*)0);\n#ifdef __VSX__\nstatic Packet16uc p16uc_REVERSE64 = { 8,9,10,11, 12,13,14,15, 0,1,2,3, 4,5,6,7 };\n#endif\nstatic Packet16uc p16uc_PSET32_WODD   = vec_sld((Packet16uc) vec_splat((Packet4ui)p16uc_FORWARD, 0), (Packet16uc) vec_splat((Packet4ui)p16uc_FORWARD, 2), 8);//{ 0,1,2,3, 0,1,2,3, 8,9,10,11, 8,9,10,11 };\nstatic Packet16uc p16uc_PSET32_WEVEN  = vec_sld(p16uc_DUPLICATE32_HI, (Packet16uc) vec_splat((Packet4ui)p16uc_FORWARD, 3), 8);//{ 4,5,6,7, 4,5,6,7, 12,13,14,15, 12,13,14,15 };\nstatic Packet16uc p16uc_HALF64_0_16 = vec_sld((Packet16uc)p4i_ZERO, vec_splat((Packet16uc) vec_abs(p4i_MINUS16), 3), 8);      //{ 0,0,0,0, 0,0,0,0, 16,16,16,16, 16,16,16,16};\n#else\nstatic Packet16uc p16uc_FORWARD = p16uc_REVERSE32; \nstatic Packet16uc p16uc_REVERSE64 = { 8,9,10,11, 12,13,14,15, 0,1,2,3, 4,5,6,7 };\nstatic Packet16uc p16uc_PSET32_WODD = vec_sld((Packet16uc) vec_splat((Packet4ui)p16uc_FORWARD, 1), (Packet16uc) vec_splat((Packet4ui)p16uc_FORWARD, 3), 8);//{ 0,1,2,3, 0,1,2,3, 8,9,10,11, 8,9,10,11 };\nstatic Packet16uc p16uc_PSET32_WEVEN = vec_sld((Packet16uc) vec_splat((Packet4ui)p16uc_FORWARD, 0), (Packet16uc) vec_splat((Packet4ui)p16uc_FORWARD, 2), 8);//{ 4,5,6,7, 4,5,6,7, 12,13,14,15, 12,13,14,15 };\nstatic Packet16uc p16uc_HALF64_0_16 = vec_sld(vec_splat((Packet16uc) vec_abs(p4i_MINUS16), 0), (Packet16uc)p4i_ZERO, 8);      //{ 0,0,0,0, 0,0,0,0, 16,16,16,16, 16,16,16,16};\n#endif // _BIG_ENDIAN\n\nstatic Packet16uc p16uc_PSET64_HI = (Packet16uc) vec_mergeh((Packet4ui)p16uc_PSET32_WODD, (Packet4ui)p16uc_PSET32_WEVEN);     //{ 0,1,2,3, 4,5,6,7, 0,1,2,3, 4,5,6,7 };\nstatic Packet16uc p16uc_PSET64_LO = (Packet16uc) vec_mergel((Packet4ui)p16uc_PSET32_WODD, (Packet4ui)p16uc_PSET32_WEVEN);     //{ 8,9,10,11, 12,13,14,15, 8,9,10,11, 12,13,14,15 };\nstatic Packet16uc p16uc_TRANSPOSE64_HI = p16uc_PSET64_HI + p16uc_HALF64_0_16;                                         //{ 0,1,2,3, 4,5,6,7, 16,17,18,19, 20,21,22,23};\nstatic Packet16uc p16uc_TRANSPOSE64_LO = p16uc_PSET64_LO + p16uc_HALF64_0_16;                                         //{ 8,9,10,11, 12,13,14,15, 24,25,26,27, 28,29,30,31};\n\nstatic Packet16uc p16uc_COMPLEX32_REV = vec_sld(p16uc_REVERSE32, p16uc_REVERSE32, 8);                                         //{ 4,5,6,7, 0,1,2,3, 12,13,14,15, 8,9,10,11 };\n\n#ifdef _BIG_ENDIAN\nstatic Packet16uc p16uc_COMPLEX32_REV2 = vec_sld(p16uc_FORWARD, p16uc_FORWARD, 8);                                            //{ 8,9,10,11, 12,13,14,15, 0,1,2,3, 4,5,6,7 };\n#else\nstatic Packet16uc p16uc_COMPLEX32_REV2 = vec_sld(p16uc_PSET64_HI, p16uc_PSET64_LO, 8);                                            //{ 8,9,10,11, 12,13,14,15, 0,1,2,3, 4,5,6,7 };\n#endif // _BIG_ENDIAN\n\n#if EIGEN_HAS_BUILTIN(__builtin_prefetch) || EIGEN_COMP_GNUC\n  #define EIGEN_PPC_PREFETCH(ADDR) __builtin_prefetch(ADDR);\n#else\n  #define EIGEN_PPC_PREFETCH(ADDR) asm( \"   dcbt [%[addr]]\\n\" :: [addr] \"r\" (ADDR) : \"cc\" );\n#endif\n\ntemplate<> struct packet_traits<float>  : default_packet_traits\n{\n  typedef Packet4f type;\n  typedef Packet4f half;\n  enum {\n    Vectorizable = 1,\n    AlignedOnScalar = 1,\n    size=4,\n    HasHalfPacket = 1,\n\n    HasAdd  = 1,\n    HasSub  = 1,\n    HasMul  = 1,\n    HasDiv  = 1,\n    HasMin  = 1,\n    HasMax  = 1,\n    HasAbs  = 1,\n    HasSin  = 0,\n    HasCos  = 0,\n    HasLog  = 0,\n    HasExp  = 1,\n#ifdef __VSX__\n    HasSqrt = 1,\n#if !EIGEN_COMP_CLANG\n    HasRsqrt = 1,\n#else\n    HasRsqrt = 0,\n#endif\n#else\n    HasSqrt = 0,\n    HasRsqrt = 0,\n#endif\n    HasRound = 1,\n    HasFloor = 1,\n    HasCeil = 1,\n    HasNegate = 1,\n    HasBlend = 1\n  };\n};\ntemplate<> struct packet_traits<int>    : default_packet_traits\n{\n  typedef Packet4i type;\n  typedef Packet4i half;\n  enum {\n    Vectorizable = 1,\n    AlignedOnScalar = 1,\n    size = 4,\n    HasHalfPacket = 0,\n\n    HasAdd  = 1,\n    HasSub  = 1,\n    HasMul  = 1,\n    HasDiv  = 0,\n    HasBlend = 1\n  };\n};\n\n\ntemplate<> struct unpacket_traits<Packet4f> { typedef float  type; enum {size=4, alignment=Aligned16}; typedef Packet4f half; };\ntemplate<> struct unpacket_traits<Packet4i> { typedef int    type; enum {size=4, alignment=Aligned16}; typedef Packet4i half; };\n\ninline std::ostream & operator <<(std::ostream & s, const Packet16uc & v)\n{\n  union {\n    Packet16uc   v;\n    unsigned char n[16];\n  } vt;\n  vt.v = v;\n  for (int i=0; i< 16; i++)\n    s << (int)vt.n[i] << \", \";\n  return s;\n}\n\ninline std::ostream & operator <<(std::ostream & s, const Packet4f & v)\n{\n  union {\n    Packet4f   v;\n    float n[4];\n  } vt;\n  vt.v = v;\n  s << vt.n[0] << \", \" << vt.n[1] << \", \" << vt.n[2] << \", \" << vt.n[3];\n  return s;\n}\n\ninline std::ostream & operator <<(std::ostream & s, const Packet4i & v)\n{\n  union {\n    Packet4i   v;\n    int n[4];\n  } vt;\n  vt.v = v;\n  s << vt.n[0] << \", \" << vt.n[1] << \", \" << vt.n[2] << \", \" << vt.n[3];\n  return s;\n}\n\ninline std::ostream & operator <<(std::ostream & s, const Packet4ui & v)\n{\n  union {\n    Packet4ui   v;\n    unsigned int n[4];\n  } vt;\n  vt.v = v;\n  s << vt.n[0] << \", \" << vt.n[1] << \", \" << vt.n[2] << \", \" << vt.n[3];\n  return s;\n}\n\n// Need to define them first or we get specialization after instantiation errors\ntemplate<> EIGEN_STRONG_INLINE Packet4f pload<Packet4f>(const float* from)\n{\n  EIGEN_DEBUG_ALIGNED_LOAD\n#ifdef __VSX__\n  return vec_vsx_ld(0, from);\n#else\n  return vec_ld(0, from);\n#endif\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4i pload<Packet4i>(const int*     from)\n{\n  EIGEN_DEBUG_ALIGNED_LOAD\n#ifdef __VSX__\n  return vec_vsx_ld(0, from);\n#else\n  return vec_ld(0, from);\n#endif\n}\n\ntemplate<> EIGEN_STRONG_INLINE void pstore<float>(float*   to, const Packet4f& from)\n{\n  EIGEN_DEBUG_ALIGNED_STORE\n#ifdef __VSX__\n  vec_vsx_st(from, 0, to);\n#else\n  vec_st(from, 0, to);\n#endif\n}\n\ntemplate<> EIGEN_STRONG_INLINE void pstore<int>(int*       to, const Packet4i& from)\n{\n  EIGEN_DEBUG_ALIGNED_STORE\n#ifdef __VSX__\n  vec_vsx_st(from, 0, to);\n#else\n  vec_st(from, 0, to);\n#endif\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pset1<Packet4f>(const float&  from) {\n  Packet4f v = {from, from, from, from};\n  return v;\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4i pset1<Packet4i>(const int&    from)   {\n  Packet4i v = {from, from, from, from};\n  return v;\n}\ntemplate<> EIGEN_STRONG_INLINE void\npbroadcast4<Packet4f>(const float *a,\n                      Packet4f& a0, Packet4f& a1, Packet4f& a2, Packet4f& a3)\n{\n  a3 = pload<Packet4f>(a);\n  a0 = vec_splat(a3, 0);\n  a1 = vec_splat(a3, 1);\n  a2 = vec_splat(a3, 2);\n  a3 = vec_splat(a3, 3);\n}\ntemplate<> EIGEN_STRONG_INLINE void\npbroadcast4<Packet4i>(const int *a,\n                      Packet4i& a0, Packet4i& a1, Packet4i& a2, Packet4i& a3)\n{\n  a3 = pload<Packet4i>(a);\n  a0 = vec_splat(a3, 0);\n  a1 = vec_splat(a3, 1);\n  a2 = vec_splat(a3, 2);\n  a3 = vec_splat(a3, 3);\n}\n\ntemplate<> EIGEN_DEVICE_FUNC inline Packet4f pgather<float, Packet4f>(const float* from, Index stride)\n{\n  float EIGEN_ALIGN16 af[4];\n  af[0] = from[0*stride];\n  af[1] = from[1*stride];\n  af[2] = from[2*stride];\n  af[3] = from[3*stride];\n return pload<Packet4f>(af);\n}\ntemplate<> EIGEN_DEVICE_FUNC inline Packet4i pgather<int, Packet4i>(const int* from, Index stride)\n{\n  int EIGEN_ALIGN16 ai[4];\n  ai[0] = from[0*stride];\n  ai[1] = from[1*stride];\n  ai[2] = from[2*stride];\n  ai[3] = from[3*stride];\n return pload<Packet4i>(ai);\n}\ntemplate<> EIGEN_DEVICE_FUNC inline void pscatter<float, Packet4f>(float* to, const Packet4f& from, Index stride)\n{\n  float EIGEN_ALIGN16 af[4];\n  pstore<float>(af, from);\n  to[0*stride] = af[0];\n  to[1*stride] = af[1];\n  to[2*stride] = af[2];\n  to[3*stride] = af[3];\n}\ntemplate<> EIGEN_DEVICE_FUNC inline void pscatter<int, Packet4i>(int* to, const Packet4i& from, Index stride)\n{\n  int EIGEN_ALIGN16 ai[4];\n  pstore<int>((int *)ai, from);\n  to[0*stride] = ai[0];\n  to[1*stride] = ai[1];\n  to[2*stride] = ai[2];\n  to[3*stride] = ai[3];\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f plset<Packet4f>(const float& a) { return pset1<Packet4f>(a) + p4f_COUNTDOWN; }\ntemplate<> EIGEN_STRONG_INLINE Packet4i plset<Packet4i>(const int& a)   { return pset1<Packet4i>(a) + p4i_COUNTDOWN; }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f padd<Packet4f>(const Packet4f& a, const Packet4f& b) { return a + b; }\ntemplate<> EIGEN_STRONG_INLINE Packet4i padd<Packet4i>(const Packet4i& a, const Packet4i& b) { return a + b; }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f psub<Packet4f>(const Packet4f& a, const Packet4f& b) { return a - b; }\ntemplate<> EIGEN_STRONG_INLINE Packet4i psub<Packet4i>(const Packet4i& a, const Packet4i& b) { return a - b; }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pnegate(const Packet4f& a) { return p4f_ZERO - a; }\ntemplate<> EIGEN_STRONG_INLINE Packet4i pnegate(const Packet4i& a) { return p4i_ZERO - a; }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pconj(const Packet4f& a) { return a; }\ntemplate<> EIGEN_STRONG_INLINE Packet4i pconj(const Packet4i& a) { return a; }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pmul<Packet4f>(const Packet4f& a, const Packet4f& b) { return vec_madd(a,b, p4f_ZERO); }\ntemplate<> EIGEN_STRONG_INLINE Packet4i pmul<Packet4i>(const Packet4i& a, const Packet4i& b) { return a * b; }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pdiv<Packet4f>(const Packet4f& a, const Packet4f& b)\n{\n#ifndef __VSX__  // VSX actually provides a div instruction\n  Packet4f t, y_0, y_1;\n\n  // Altivec does not offer a divide instruction, we have to do a reciprocal approximation\n  y_0 = vec_re(b);\n\n  // Do one Newton-Raphson iteration to get the needed accuracy\n  t   = vec_nmsub(y_0, b, p4f_ONE);\n  y_1 = vec_madd(y_0, t, y_0);\n\n  return vec_madd(a, y_1, p4f_ZERO);\n#else\n  return vec_div(a, b);\n#endif\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4i pdiv<Packet4i>(const Packet4i& /*a*/, const Packet4i& /*b*/)\n{ eigen_assert(false && \"packet integer division are not supported by AltiVec\");\n  return pset1<Packet4i>(0);\n}\n\n// for some weird raisons, it has to be overloaded for packet of integers\ntemplate<> EIGEN_STRONG_INLINE Packet4f pmadd(const Packet4f& a, const Packet4f& b, const Packet4f& c) { return vec_madd(a,b,c); }\ntemplate<> EIGEN_STRONG_INLINE Packet4i pmadd(const Packet4i& a, const Packet4i& b, const Packet4i& c) { return a*b + c; }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pmin<Packet4f>(const Packet4f& a, const Packet4f& b) { return vec_min(a, b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4i pmin<Packet4i>(const Packet4i& a, const Packet4i& b) { return vec_min(a, b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pmax<Packet4f>(const Packet4f& a, const Packet4f& b) { return vec_max(a, b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4i pmax<Packet4i>(const Packet4i& a, const Packet4i& b) { return vec_max(a, b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pand<Packet4f>(const Packet4f& a, const Packet4f& b) { return vec_and(a, b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4i pand<Packet4i>(const Packet4i& a, const Packet4i& b) { return vec_and(a, b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f por<Packet4f>(const Packet4f& a, const Packet4f& b) { return vec_or(a, b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4i por<Packet4i>(const Packet4i& a, const Packet4i& b) { return vec_or(a, b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pxor<Packet4f>(const Packet4f& a, const Packet4f& b) { return vec_xor(a, b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4i pxor<Packet4i>(const Packet4i& a, const Packet4i& b) { return vec_xor(a, b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pandnot<Packet4f>(const Packet4f& a, const Packet4f& b) { return vec_and(a, vec_nor(b, b)); }\ntemplate<> EIGEN_STRONG_INLINE Packet4i pandnot<Packet4i>(const Packet4i& a, const Packet4i& b) { return vec_and(a, vec_nor(b, b)); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pround<Packet4f>(const Packet4f& a) { return vec_round(a); }\ntemplate<> EIGEN_STRONG_INLINE Packet4f pceil<Packet4f>(const  Packet4f& a) { return vec_ceil(a); }\ntemplate<> EIGEN_STRONG_INLINE Packet4f pfloor<Packet4f>(const Packet4f& a) { return vec_floor(a); }\n\n#ifdef _BIG_ENDIAN\ntemplate<> EIGEN_STRONG_INLINE Packet4f ploadu<Packet4f>(const float* from)\n{\n  EIGEN_DEBUG_ALIGNED_LOAD\n  Packet16uc MSQ, LSQ;\n  Packet16uc mask;\n  MSQ = vec_ld(0, (unsigned char *)from);          // most significant quadword\n  LSQ = vec_ld(15, (unsigned char *)from);         // least significant quadword\n  mask = vec_lvsl(0, from);                        // create the permute mask\n  return (Packet4f) vec_perm(MSQ, LSQ, mask);           // align the data\n\n}\ntemplate<> EIGEN_STRONG_INLINE Packet4i ploadu<Packet4i>(const int* from)\n{\n  EIGEN_DEBUG_ALIGNED_LOAD\n  // Taken from http://developer.apple.com/hardwaredrivers/ve/alignment.html\n  Packet16uc MSQ, LSQ;\n  Packet16uc mask;\n  MSQ = vec_ld(0, (unsigned char *)from);          // most significant quadword\n  LSQ = vec_ld(15, (unsigned char *)from);         // least significant quadword\n  mask = vec_lvsl(0, from);                        // create the permute mask\n  return (Packet4i) vec_perm(MSQ, LSQ, mask);    // align the data\n}\n#else\n// We also need ot redefine little endian loading of Packet4i/Packet4f using VSX\ntemplate<> EIGEN_STRONG_INLINE Packet4i ploadu<Packet4i>(const int* from)\n{\n  EIGEN_DEBUG_UNALIGNED_LOAD\n  return (Packet4i) vec_vsx_ld((long)from & 15, (const int*) _EIGEN_ALIGNED_PTR(from));\n}\ntemplate<> EIGEN_STRONG_INLINE Packet4f ploadu<Packet4f>(const float* from)\n{\n  EIGEN_DEBUG_UNALIGNED_LOAD\n  return (Packet4f) vec_vsx_ld((long)from & 15, (const float*) _EIGEN_ALIGNED_PTR(from));\n}\n#endif\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f ploaddup<Packet4f>(const float*   from)\n{\n  Packet4f p;\n  if((ptrdiff_t(from) % 16) == 0)  p = pload<Packet4f>(from);\n  else                             p = ploadu<Packet4f>(from);\n  return vec_perm(p, p, p16uc_DUPLICATE32_HI);\n}\ntemplate<> EIGEN_STRONG_INLINE Packet4i ploaddup<Packet4i>(const int*     from)\n{\n  Packet4i p;\n  if((ptrdiff_t(from) % 16) == 0)  p = pload<Packet4i>(from);\n  else                             p = ploadu<Packet4i>(from);\n  return vec_perm(p, p, p16uc_DUPLICATE32_HI);\n}\n\n#ifdef _BIG_ENDIAN\ntemplate<> EIGEN_STRONG_INLINE void pstoreu<float>(float*  to, const Packet4f& from)\n{\n  EIGEN_DEBUG_UNALIGNED_STORE\n  // Taken from http://developer.apple.com/hardwaredrivers/ve/alignment.html\n  // Warning: not thread safe!\n  Packet16uc MSQ, LSQ, edges;\n  Packet16uc edgeAlign, align;\n\n  MSQ = vec_ld(0, (unsigned char *)to);                     // most significant quadword\n  LSQ = vec_ld(15, (unsigned char *)to);                    // least significant quadword\n  edgeAlign = vec_lvsl(0, to);                              // permute map to extract edges\n  edges=vec_perm(LSQ,MSQ,edgeAlign);                        // extract the edges\n  align = vec_lvsr( 0, to );                                // permute map to misalign data\n  MSQ = vec_perm(edges,(Packet16uc)from,align);             // misalign the data (MSQ)\n  LSQ = vec_perm((Packet16uc)from,edges,align);             // misalign the data (LSQ)\n  vec_st( LSQ, 15, (unsigned char *)to );                   // Store the LSQ part first\n  vec_st( MSQ, 0, (unsigned char *)to );                    // Store the MSQ part\n}\ntemplate<> EIGEN_STRONG_INLINE void pstoreu<int>(int*      to, const Packet4i& from)\n{\n  EIGEN_DEBUG_UNALIGNED_STORE\n  // Taken from http://developer.apple.com/hardwaredrivers/ve/alignment.html\n  // Warning: not thread safe!\n  Packet16uc MSQ, LSQ, edges;\n  Packet16uc edgeAlign, align;\n\n  MSQ = vec_ld(0, (unsigned char *)to);                     // most significant quadword\n  LSQ = vec_ld(15, (unsigned char *)to);                    // least significant quadword\n  edgeAlign = vec_lvsl(0, to);                              // permute map to extract edges\n  edges=vec_perm(LSQ, MSQ, edgeAlign);                      // extract the edges\n  align = vec_lvsr( 0, to );                                // permute map to misalign data\n  MSQ = vec_perm(edges, (Packet16uc) from, align);          // misalign the data (MSQ)\n  LSQ = vec_perm((Packet16uc) from, edges, align);          // misalign the data (LSQ)\n  vec_st( LSQ, 15, (unsigned char *)to );                   // Store the LSQ part first\n  vec_st( MSQ, 0, (unsigned char *)to );                    // Store the MSQ part\n}\n#else\n// We also need ot redefine little endian loading of Packet4i/Packet4f using VSX\ntemplate<> EIGEN_STRONG_INLINE void pstoreu<int>(int*       to, const Packet4i& from)\n{\n  EIGEN_DEBUG_ALIGNED_STORE\n  vec_vsx_st(from, (long)to & 15, (int*) _EIGEN_ALIGNED_PTR(to));\n}\ntemplate<> EIGEN_STRONG_INLINE void pstoreu<float>(float*   to, const Packet4f& from)\n{\n  EIGEN_DEBUG_ALIGNED_STORE\n  vec_vsx_st(from, (long)to & 15, (float*) _EIGEN_ALIGNED_PTR(to));\n}\n#endif\n\ntemplate<> EIGEN_STRONG_INLINE void prefetch<float>(const float* addr)    { EIGEN_PPC_PREFETCH(addr); }\ntemplate<> EIGEN_STRONG_INLINE void prefetch<int>(const int*     addr)    { EIGEN_PPC_PREFETCH(addr); }\n\ntemplate<> EIGEN_STRONG_INLINE float  pfirst<Packet4f>(const Packet4f& a) { float EIGEN_ALIGN16 x; vec_ste(a, 0, &x); return x; }\ntemplate<> EIGEN_STRONG_INLINE int    pfirst<Packet4i>(const Packet4i& a) { int   EIGEN_ALIGN16 x; vec_ste(a, 0, &x); return x; }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f preverse(const Packet4f& a)\n{\n  return reinterpret_cast<Packet4f>(vec_perm(reinterpret_cast<Packet16uc>(a), reinterpret_cast<Packet16uc>(a), p16uc_REVERSE32));\n}\ntemplate<> EIGEN_STRONG_INLINE Packet4i preverse(const Packet4i& a)\n{\n  return reinterpret_cast<Packet4i>(vec_perm(reinterpret_cast<Packet16uc>(a), reinterpret_cast<Packet16uc>(a), p16uc_REVERSE32)); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pabs(const Packet4f& a) { return vec_abs(a); }\ntemplate<> EIGEN_STRONG_INLINE Packet4i pabs(const Packet4i& a) { return vec_abs(a); }\n\ntemplate<> EIGEN_STRONG_INLINE float predux<Packet4f>(const Packet4f& a)\n{\n  Packet4f b, sum;\n  b   = vec_sld(a, a, 8);\n  sum = a + b;\n  b   = vec_sld(sum, sum, 4);\n  sum += b;\n  return pfirst(sum);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f preduxp<Packet4f>(const Packet4f* vecs)\n{\n  Packet4f v[4], sum[4];\n\n  // It's easier and faster to transpose then add as columns\n  // Check: http://www.freevec.org/function/matrix_4x4_transpose_floats for explanation\n  // Do the transpose, first set of moves\n  v[0] = vec_mergeh(vecs[0], vecs[2]);\n  v[1] = vec_mergel(vecs[0], vecs[2]);\n  v[2] = vec_mergeh(vecs[1], vecs[3]);\n  v[3] = vec_mergel(vecs[1], vecs[3]);\n  // Get the resulting vectors\n  sum[0] = vec_mergeh(v[0], v[2]);\n  sum[1] = vec_mergel(v[0], v[2]);\n  sum[2] = vec_mergeh(v[1], v[3]);\n  sum[3] = vec_mergel(v[1], v[3]);\n\n  // Now do the summation:\n  // Lines 0+1\n  sum[0] = sum[0] + sum[1];\n  // Lines 2+3\n  sum[1] = sum[2] + sum[3];\n  // Add the results\n  sum[0] = sum[0] + sum[1];\n\n  return sum[0];\n}\n\ntemplate<> EIGEN_STRONG_INLINE int predux<Packet4i>(const Packet4i& a)\n{\n  Packet4i sum;\n  sum = vec_sums(a, p4i_ZERO);\n#ifdef _BIG_ENDIAN\n  sum = vec_sld(sum, p4i_ZERO, 12);\n#else\n  sum = vec_sld(p4i_ZERO, sum, 4);\n#endif\n  return pfirst(sum);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4i preduxp<Packet4i>(const Packet4i* vecs)\n{\n  Packet4i v[4], sum[4];\n\n  // It's easier and faster to transpose then add as columns\n  // Check: http://www.freevec.org/function/matrix_4x4_transpose_floats for explanation\n  // Do the transpose, first set of moves\n  v[0] = vec_mergeh(vecs[0], vecs[2]);\n  v[1] = vec_mergel(vecs[0], vecs[2]);\n  v[2] = vec_mergeh(vecs[1], vecs[3]);\n  v[3] = vec_mergel(vecs[1], vecs[3]);\n  // Get the resulting vectors\n  sum[0] = vec_mergeh(v[0], v[2]);\n  sum[1] = vec_mergel(v[0], v[2]);\n  sum[2] = vec_mergeh(v[1], v[3]);\n  sum[3] = vec_mergel(v[1], v[3]);\n\n  // Now do the summation:\n  // Lines 0+1\n  sum[0] = sum[0] + sum[1];\n  // Lines 2+3\n  sum[1] = sum[2] + sum[3];\n  // Add the results\n  sum[0] = sum[0] + sum[1];\n\n  return sum[0];\n}\n\n// Other reduction functions:\n// mul\ntemplate<> EIGEN_STRONG_INLINE float predux_mul<Packet4f>(const Packet4f& a)\n{\n  Packet4f prod;\n  prod = pmul(a, vec_sld(a, a, 8));\n  return pfirst(pmul(prod, vec_sld(prod, prod, 4)));\n}\n\ntemplate<> EIGEN_STRONG_INLINE int predux_mul<Packet4i>(const Packet4i& a)\n{\n  EIGEN_ALIGN16 int aux[4];\n  pstore(aux, a);\n  return aux[0] * aux[1] * aux[2] * aux[3];\n}\n\n// min\ntemplate<> EIGEN_STRONG_INLINE float predux_min<Packet4f>(const Packet4f& a)\n{\n  Packet4f b, res;\n  b = vec_min(a, vec_sld(a, a, 8));\n  res = vec_min(b, vec_sld(b, b, 4));\n  return pfirst(res);\n}\n\ntemplate<> EIGEN_STRONG_INLINE int predux_min<Packet4i>(const Packet4i& a)\n{\n  Packet4i b, res;\n  b = vec_min(a, vec_sld(a, a, 8));\n  res = vec_min(b, vec_sld(b, b, 4));\n  return pfirst(res);\n}\n\n// max\ntemplate<> EIGEN_STRONG_INLINE float predux_max<Packet4f>(const Packet4f& a)\n{\n  Packet4f b, res;\n  b = vec_max(a, vec_sld(a, a, 8));\n  res = vec_max(b, vec_sld(b, b, 4));\n  return pfirst(res);\n}\n\ntemplate<> EIGEN_STRONG_INLINE int predux_max<Packet4i>(const Packet4i& a)\n{\n  Packet4i b, res;\n  b = vec_max(a, vec_sld(a, a, 8));\n  res = vec_max(b, vec_sld(b, b, 4));\n  return pfirst(res);\n}\n\ntemplate<int Offset>\nstruct palign_impl<Offset,Packet4f>\n{\n  static EIGEN_STRONG_INLINE void run(Packet4f& first, const Packet4f& second)\n  {\n#ifdef _BIG_ENDIAN\n    switch (Offset % 4) {\n    case 1:\n      first = vec_sld(first, second, 4); break;\n    case 2:\n      first = vec_sld(first, second, 8); break;\n    case 3:\n      first = vec_sld(first, second, 12); break;\n    }\n#else\n    switch (Offset % 4) {\n    case 1:\n      first = vec_sld(second, first, 12); break;\n    case 2:\n      first = vec_sld(second, first, 8); break;\n    case 3:\n      first = vec_sld(second, first, 4); break;\n    }\n#endif\n  }\n};\n\ntemplate<int Offset>\nstruct palign_impl<Offset,Packet4i>\n{\n  static EIGEN_STRONG_INLINE void run(Packet4i& first, const Packet4i& second)\n  {\n#ifdef _BIG_ENDIAN\n    switch (Offset % 4) {\n    case 1:\n      first = vec_sld(first, second, 4); break;\n    case 2:\n      first = vec_sld(first, second, 8); break;\n    case 3:\n      first = vec_sld(first, second, 12); break;\n    }\n#else\n    switch (Offset % 4) {\n    case 1:\n      first = vec_sld(second, first, 12); break;\n    case 2:\n      first = vec_sld(second, first, 8); break;\n    case 3:\n      first = vec_sld(second, first, 4); break;\n    }\n#endif\n  }\n};\n\nEIGEN_DEVICE_FUNC inline void\nptranspose(PacketBlock<Packet4f,4>& kernel) {\n  Packet4f t0, t1, t2, t3;\n  t0 = vec_mergeh(kernel.packet[0], kernel.packet[2]);\n  t1 = vec_mergel(kernel.packet[0], kernel.packet[2]);\n  t2 = vec_mergeh(kernel.packet[1], kernel.packet[3]);\n  t3 = vec_mergel(kernel.packet[1], kernel.packet[3]);\n  kernel.packet[0] = vec_mergeh(t0, t2);\n  kernel.packet[1] = vec_mergel(t0, t2);\n  kernel.packet[2] = vec_mergeh(t1, t3);\n  kernel.packet[3] = vec_mergel(t1, t3);\n}\n\nEIGEN_DEVICE_FUNC inline void\nptranspose(PacketBlock<Packet4i,4>& kernel) {\n  Packet4i t0, t1, t2, t3;\n  t0 = vec_mergeh(kernel.packet[0], kernel.packet[2]);\n  t1 = vec_mergel(kernel.packet[0], kernel.packet[2]);\n  t2 = vec_mergeh(kernel.packet[1], kernel.packet[3]);\n  t3 = vec_mergel(kernel.packet[1], kernel.packet[3]);\n  kernel.packet[0] = vec_mergeh(t0, t2);\n  kernel.packet[1] = vec_mergel(t0, t2);\n  kernel.packet[2] = vec_mergeh(t1, t3);\n  kernel.packet[3] = vec_mergel(t1, t3);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4i pblend(const Selector<4>& ifPacket, const Packet4i& thenPacket, const Packet4i& elsePacket) {\n  Packet4ui select = { ifPacket.select[0], ifPacket.select[1], ifPacket.select[2], ifPacket.select[3] };\n  Packet4ui mask = reinterpret_cast<Packet4ui>(vec_cmpeq(reinterpret_cast<Packet4ui>(select), reinterpret_cast<Packet4ui>(p4i_ONE)));\n  return vec_sel(elsePacket, thenPacket, mask);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pblend(const Selector<4>& ifPacket, const Packet4f& thenPacket, const Packet4f& elsePacket) {\n  Packet4ui select = { ifPacket.select[0], ifPacket.select[1], ifPacket.select[2], ifPacket.select[3] };\n  Packet4ui mask = reinterpret_cast<Packet4ui>(vec_cmpeq(reinterpret_cast<Packet4ui>(select), reinterpret_cast<Packet4ui>(p4i_ONE)));\n  return vec_sel(elsePacket, thenPacket, mask);\n}\n\n\n//---------- double ----------\n#ifdef __VSX__\ntypedef __vector double              Packet2d;\ntypedef __vector unsigned long long  Packet2ul;\ntypedef __vector long long           Packet2l;\n#if EIGEN_COMP_CLANG\ntypedef Packet2ul                    Packet2bl;\n#else\ntypedef __vector __bool long         Packet2bl;\n#endif\n\nstatic Packet2l  p2l_ONE  = { 1, 1 };\nstatic Packet2l  p2l_ZERO = reinterpret_cast<Packet2l>(p4i_ZERO);\nstatic Packet2d  p2d_ONE  = { 1.0, 1.0 }; \nstatic Packet2d  p2d_ZERO = reinterpret_cast<Packet2d>(p4f_ZERO);\nstatic Packet2d  p2d_ZERO_ = { -0.0, -0.0 };\n\n#ifdef _BIG_ENDIAN\nstatic Packet2d p2d_COUNTDOWN = reinterpret_cast<Packet2d>(vec_sld(reinterpret_cast<Packet4f>(p2d_ZERO), reinterpret_cast<Packet4f>(p2d_ONE), 8));\n#else\nstatic Packet2d p2d_COUNTDOWN = reinterpret_cast<Packet2d>(vec_sld(reinterpret_cast<Packet4f>(p2d_ONE), reinterpret_cast<Packet4f>(p2d_ZERO), 8));\n#endif\n\ntemplate<int index> Packet2d vec_splat_dbl(Packet2d& a);\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d vec_splat_dbl<0>(Packet2d& a)\n{\n  return reinterpret_cast<Packet2d>(vec_perm(a, a, p16uc_PSET64_HI));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d vec_splat_dbl<1>(Packet2d& a)\n{\n  return reinterpret_cast<Packet2d>(vec_perm(a, a, p16uc_PSET64_LO));\n}\n\ntemplate<> struct packet_traits<double> : default_packet_traits\n{\n  typedef Packet2d type;\n  typedef Packet2d half;\n  enum {\n    Vectorizable = 1,\n    AlignedOnScalar = 1,\n    size=2,\n    HasHalfPacket = 1,\n\n    HasAdd  = 1,\n    HasSub  = 1,\n    HasMul  = 1,\n    HasDiv  = 1,\n    HasMin  = 1,\n    HasMax  = 1,\n    HasAbs  = 1,\n    HasSin  = 0,\n    HasCos  = 0,\n    HasLog  = 0,\n    HasExp  = 1,\n    HasSqrt = 1,\n    HasRsqrt = 1,\n    HasRound = 1,\n    HasFloor = 1,\n    HasCeil = 1,\n    HasNegate = 1,\n    HasBlend = 1\n  };\n};\n\ntemplate<> struct unpacket_traits<Packet2d> { typedef double type; enum {size=2, alignment=Aligned16}; typedef Packet2d half; };\n\ninline std::ostream & operator <<(std::ostream & s, const Packet2l & v)\n{\n  union {\n    Packet2l   v;\n    int64_t n[2];\n  } vt;\n  vt.v = v;\n  s << vt.n[0] << \", \" << vt.n[1];\n  return s;\n}\n\ninline std::ostream & operator <<(std::ostream & s, const Packet2d & v)\n{\n  union {\n    Packet2d   v;\n    double n[2];\n  } vt;\n  vt.v = v;\n  s << vt.n[0] << \", \" << vt.n[1];\n  return s;\n}\n\n// Need to define them first or we get specialization after instantiation errors\ntemplate<> EIGEN_STRONG_INLINE Packet2d pload<Packet2d>(const double* from)\n{\n  EIGEN_DEBUG_ALIGNED_LOAD\n#ifdef __VSX__\n  return vec_vsx_ld(0, from);\n#else\n  return vec_ld(0, from);\n#endif\n}\n\ntemplate<> EIGEN_STRONG_INLINE void pstore<double>(double*   to, const Packet2d& from)\n{\n  EIGEN_DEBUG_ALIGNED_STORE\n#ifdef __VSX__\n  vec_vsx_st(from, 0, to);\n#else\n  vec_st(from, 0, to);\n#endif\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d pset1<Packet2d>(const double&  from) {\n  Packet2d v = {from, from};\n  return v;\n}\n\ntemplate<> EIGEN_STRONG_INLINE void\npbroadcast4<Packet2d>(const double *a,\n                      Packet2d& a0, Packet2d& a1, Packet2d& a2, Packet2d& a3)\n{\n  a1 = pload<Packet2d>(a);\n  a0 = vec_splat_dbl<0>(a1);\n  a1 = vec_splat_dbl<1>(a1);\n  a3 = pload<Packet2d>(a+2);\n  a2 = vec_splat_dbl<0>(a3);\n  a3 = vec_splat_dbl<1>(a3);\n}\n\ntemplate<> EIGEN_DEVICE_FUNC inline Packet2d pgather<double, Packet2d>(const double* from, Index stride)\n{\n  double EIGEN_ALIGN16 af[2];\n  af[0] = from[0*stride];\n  af[1] = from[1*stride];\n return pload<Packet2d>(af);\n}\ntemplate<> EIGEN_DEVICE_FUNC inline void pscatter<double, Packet2d>(double* to, const Packet2d& from, Index stride)\n{\n  double EIGEN_ALIGN16 af[2];\n  pstore<double>(af, from);\n  to[0*stride] = af[0];\n  to[1*stride] = af[1];\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d plset<Packet2d>(const double& a) { return pset1<Packet2d>(a) + p2d_COUNTDOWN; }\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d padd<Packet2d>(const Packet2d& a, const Packet2d& b) { return a + b; }\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d psub<Packet2d>(const Packet2d& a, const Packet2d& b) { return a - b; }\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d pnegate(const Packet2d& a) { return p2d_ZERO - a; }\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d pconj(const Packet2d& a) { return a; }\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d pmul<Packet2d>(const Packet2d& a, const Packet2d& b) { return vec_madd(a,b,p2d_ZERO); }\ntemplate<> EIGEN_STRONG_INLINE Packet2d pdiv<Packet2d>(const Packet2d& a, const Packet2d& b) { return vec_div(a,b); }\n\n// for some weird raisons, it has to be overloaded for packet of integers\ntemplate<> EIGEN_STRONG_INLINE Packet2d pmadd(const Packet2d& a, const Packet2d& b, const Packet2d& c) { return vec_madd(a, b, c); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d pmin<Packet2d>(const Packet2d& a, const Packet2d& b) { return vec_min(a, b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d pmax<Packet2d>(const Packet2d& a, const Packet2d& b) { return vec_max(a, b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d pand<Packet2d>(const Packet2d& a, const Packet2d& b) { return vec_and(a, b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d por<Packet2d>(const Packet2d& a, const Packet2d& b) { return vec_or(a, b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d pxor<Packet2d>(const Packet2d& a, const Packet2d& b) { return vec_xor(a, b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d pandnot<Packet2d>(const Packet2d& a, const Packet2d& b) { return vec_and(a, vec_nor(b, b)); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d pround<Packet2d>(const Packet2d& a) { return vec_round(a); }\ntemplate<> EIGEN_STRONG_INLINE Packet2d pceil<Packet2d>(const  Packet2d& a) { return vec_ceil(a); }\ntemplate<> EIGEN_STRONG_INLINE Packet2d pfloor<Packet2d>(const Packet2d& a) { return vec_floor(a); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d ploadu<Packet2d>(const double* from)\n{\n  EIGEN_DEBUG_ALIGNED_LOAD\n  return (Packet2d) vec_vsx_ld((long)from & 15, (const double*) _EIGEN_ALIGNED_PTR(from));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d ploaddup<Packet2d>(const double*   from)\n{\n  Packet2d p;\n  if((ptrdiff_t(from) % 16) == 0)  p = pload<Packet2d>(from);\n  else                             p = ploadu<Packet2d>(from);\n  return vec_splat_dbl<0>(p);\n}\n\ntemplate<> EIGEN_STRONG_INLINE void pstoreu<double>(double*  to, const Packet2d& from)\n{\n  EIGEN_DEBUG_ALIGNED_STORE\n  vec_vsx_st((Packet4f)from, (long)to & 15, (float*) _EIGEN_ALIGNED_PTR(to));\n}\n\ntemplate<> EIGEN_STRONG_INLINE void prefetch<double>(const double* addr) { EIGEN_PPC_PREFETCH(addr); }\n\ntemplate<> EIGEN_STRONG_INLINE double  pfirst<Packet2d>(const Packet2d& a) { double EIGEN_ALIGN16 x[2]; pstore<double>(x, a); return x[0]; }\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d preverse(const Packet2d& a)\n{\n  return reinterpret_cast<Packet2d>(vec_perm(reinterpret_cast<Packet16uc>(a), reinterpret_cast<Packet16uc>(a), p16uc_REVERSE64));\n}\ntemplate<> EIGEN_STRONG_INLINE Packet2d pabs(const Packet2d& a) { return vec_abs(a); }\n\ntemplate<> EIGEN_STRONG_INLINE double predux<Packet2d>(const Packet2d& a)\n{\n  Packet2d b, sum;\n  b   = reinterpret_cast<Packet2d>(vec_sld(reinterpret_cast<Packet4f>(a), reinterpret_cast<Packet4f>(a), 8));\n  sum = a + b;\n  return pfirst<Packet2d>(sum);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d preduxp<Packet2d>(const Packet2d* vecs)\n{\n  Packet2d v[2], sum;\n  v[0] = vecs[0] + reinterpret_cast<Packet2d>(vec_sld(reinterpret_cast<Packet4f>(vecs[0]), reinterpret_cast<Packet4f>(vecs[0]), 8));\n  v[1] = vecs[1] + reinterpret_cast<Packet2d>(vec_sld(reinterpret_cast<Packet4f>(vecs[1]), reinterpret_cast<Packet4f>(vecs[1]), 8));\n \n#ifdef _BIG_ENDIAN\n  sum = reinterpret_cast<Packet2d>(vec_sld(reinterpret_cast<Packet4f>(v[0]), reinterpret_cast<Packet4f>(v[1]), 8));\n#else\n  sum = reinterpret_cast<Packet2d>(vec_sld(reinterpret_cast<Packet4f>(v[1]), reinterpret_cast<Packet4f>(v[0]), 8));\n#endif\n\n  return sum;\n}\n// Other reduction functions:\n// mul\ntemplate<> EIGEN_STRONG_INLINE double predux_mul<Packet2d>(const Packet2d& a)\n{\n  return pfirst(pmul(a, reinterpret_cast<Packet2d>(vec_sld(reinterpret_cast<Packet4ui>(a), reinterpret_cast<Packet4ui>(a), 8))));\n}\n\n// min\ntemplate<> EIGEN_STRONG_INLINE double predux_min<Packet2d>(const Packet2d& a)\n{\n  return pfirst(pmin(a, reinterpret_cast<Packet2d>(vec_sld(reinterpret_cast<Packet4ui>(a), reinterpret_cast<Packet4ui>(a), 8))));\n}\n\n// max\ntemplate<> EIGEN_STRONG_INLINE double predux_max<Packet2d>(const Packet2d& a)\n{\n  return pfirst(pmax(a, reinterpret_cast<Packet2d>(vec_sld(reinterpret_cast<Packet4ui>(a), reinterpret_cast<Packet4ui>(a), 8))));\n}\n\ntemplate<int Offset>\nstruct palign_impl<Offset,Packet2d>\n{\n  static EIGEN_STRONG_INLINE void run(Packet2d& first, const Packet2d& second)\n  {\n    if (Offset == 1)\n#ifdef _BIG_ENDIAN\n      first = reinterpret_cast<Packet2d>(vec_sld(reinterpret_cast<Packet4ui>(first), reinterpret_cast<Packet4ui>(second), 8));\n#else\n      first = reinterpret_cast<Packet2d>(vec_sld(reinterpret_cast<Packet4ui>(second), reinterpret_cast<Packet4ui>(first), 8));\n#endif\n  }\n};\n\nEIGEN_DEVICE_FUNC inline void\nptranspose(PacketBlock<Packet2d,2>& kernel) {\n  Packet2d t0, t1;\n  t0 = vec_perm(kernel.packet[0], kernel.packet[1], p16uc_TRANSPOSE64_HI);\n  t1 = vec_perm(kernel.packet[0], kernel.packet[1], p16uc_TRANSPOSE64_LO);\n  kernel.packet[0] = t0;\n  kernel.packet[1] = t1;\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d pblend(const Selector<2>& ifPacket, const Packet2d& thenPacket, const Packet2d& elsePacket) {\n  Packet2l select = { ifPacket.select[0], ifPacket.select[1] };\n  Packet2bl mask = vec_cmpeq(reinterpret_cast<Packet2d>(select), reinterpret_cast<Packet2d>(p2l_ONE));\n  return vec_sel(elsePacket, thenPacket, mask);\n}\n#endif // __VSX__\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_PACKET_MATH_ALTIVEC_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/arch/CUDA/Complex.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2014 Benoit Steiner <benoit.steiner.goog@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_COMPLEX_CUDA_H\n#define EIGEN_COMPLEX_CUDA_H\n\n// clang-format off\n\nnamespace Eigen {\n\nnamespace internal {\n\n#if defined(__CUDACC__) && defined(EIGEN_USE_GPU)\n\n// Many std::complex methods such as operator+, operator-, operator* and\n// operator/ are not constexpr. Due to this, clang does not treat them as device\n// functions and thus Eigen functors making use of these operators fail to\n// compile. Here, we manually specialize these functors for complex types when\n// building for CUDA to avoid non-constexpr methods.\n\n// Sum\ntemplate<typename T> struct scalar_sum_op<const std::complex<T>, const std::complex<T> > : binary_op_base<const std::complex<T>, const std::complex<T> > {\n  typedef typename std::complex<T> result_type;\n\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_sum_op)\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE std::complex<T> operator() (const std::complex<T>& a, const std::complex<T>& b) const {\n    return std::complex<T>(numext::real(a) + numext::real(b),\n                           numext::imag(a) + numext::imag(b));\n  }\n};\n\ntemplate<typename T> struct scalar_sum_op<std::complex<T>, std::complex<T> > : scalar_sum_op<const std::complex<T>, const std::complex<T> > {};\n\n\n// Difference\ntemplate<typename T> struct scalar_difference_op<const std::complex<T>, const std::complex<T> >  : binary_op_base<const std::complex<T>, const std::complex<T> > {\n  typedef typename std::complex<T> result_type;\n\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_difference_op)\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE std::complex<T> operator() (const std::complex<T>& a, const std::complex<T>& b) const {\n    return std::complex<T>(numext::real(a) - numext::real(b),\n                           numext::imag(a) - numext::imag(b));\n  }\n};\n\ntemplate<typename T> struct scalar_difference_op<std::complex<T>, std::complex<T> > : scalar_difference_op<const std::complex<T>, const std::complex<T> > {};\n\n\n// Product\ntemplate<typename T> struct scalar_product_op<const std::complex<T>, const std::complex<T> >  : binary_op_base<const std::complex<T>, const std::complex<T> > {\n  enum {\n    Vectorizable = packet_traits<std::complex<T>>::HasMul\n  };\n  typedef typename std::complex<T> result_type;\n\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_product_op)\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE std::complex<T> operator() (const std::complex<T>& a, const std::complex<T>& b) const {\n    const T a_real = numext::real(a);\n    const T a_imag = numext::imag(a);\n    const T b_real = numext::real(b);\n    const T b_imag = numext::imag(b);\n    return std::complex<T>(a_real * b_real - a_imag * b_imag,\n                           a_real * b_imag + a_imag * b_real);\n  }\n};\n\ntemplate<typename T> struct scalar_product_op<std::complex<T>, std::complex<T> > : scalar_product_op<const std::complex<T>, const std::complex<T> > {};\n\n\n// Quotient\ntemplate<typename T> struct scalar_quotient_op<const std::complex<T>, const std::complex<T> > : binary_op_base<const std::complex<T>, const std::complex<T> > {\n  enum {\n    Vectorizable = packet_traits<std::complex<T>>::HasDiv\n  };\n  typedef typename std::complex<T> result_type;\n\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_quotient_op)\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE std::complex<T> operator() (const std::complex<T>& a, const std::complex<T>& b) const {\n    const T a_real = numext::real(a);\n    const T a_imag = numext::imag(a);\n    const T b_real = numext::real(b);\n    const T b_imag = numext::imag(b);\n    const T norm = T(1) / (b_real * b_real + b_imag * b_imag);\n    return std::complex<T>((a_real * b_real + a_imag * b_imag) * norm,\n                           (a_imag * b_real - a_real * b_imag) * norm);\n  }\n};\n\ntemplate<typename T> struct scalar_quotient_op<std::complex<T>, std::complex<T> > : scalar_quotient_op<const std::complex<T>, const std::complex<T> > {};\n\n#endif\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_COMPLEX_CUDA_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/arch/CUDA/Half.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n//\n// The conversion routines are Copyright (c) Fabian Giesen, 2016.\n// The original license follows:\n//\n// Copyright (c) Fabian Giesen, 2016\n// All rights reserved.\n// Redistribution and use in source and binary forms, with or without\n// modification, are permitted.\n// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n// “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n\n// Standard 16-bit float type, mostly useful for GPUs. Defines a new\n// type Eigen::half (inheriting from CUDA's __half struct) with\n// operator overloads such that it behaves basically as an arithmetic\n// type. It will be quite slow on CPUs (so it is recommended to stay\n// in fp32 for CPUs, except for simple parameter conversions, I/O\n// to disk and the likes), but fast on GPUs.\n\n\n#ifndef EIGEN_HALF_CUDA_H\n#define EIGEN_HALF_CUDA_H\n\n#if __cplusplus > 199711L\n#define EIGEN_EXPLICIT_CAST(tgt_type) explicit operator tgt_type()\n#else\n#define EIGEN_EXPLICIT_CAST(tgt_type) operator tgt_type()\n#endif\n\n\nnamespace Eigen {\n\nstruct half;\n\nnamespace half_impl {\n\n#if !defined(EIGEN_HAS_CUDA_FP16)\n\n// Make our own __half definition that is similar to CUDA's.\nstruct __half {\n  EIGEN_DEVICE_FUNC __half() {}\n  explicit EIGEN_DEVICE_FUNC __half(unsigned short raw) : x(raw) {}\n  unsigned short x;\n};\n\n#endif\n\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC __half raw_uint16_to_half(unsigned short x);\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC __half float_to_half_rtne(float ff);\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC float half_to_float(__half h);\n\nstruct half_base : public __half {\n  EIGEN_DEVICE_FUNC half_base() {}\n  EIGEN_DEVICE_FUNC half_base(const half_base& h) : __half(h) {}\n  EIGEN_DEVICE_FUNC half_base(const __half& h) : __half(h) {}\n};\n\n} // namespace half_impl\n\n// Class definition.\nstruct half : public half_impl::half_base {\n  #if !defined(EIGEN_HAS_CUDA_FP16)\n    typedef half_impl::__half __half;\n  #endif\n\n  EIGEN_DEVICE_FUNC half() {}\n\n  EIGEN_DEVICE_FUNC half(const __half& h) : half_impl::half_base(h) {}\n  EIGEN_DEVICE_FUNC half(const half& h) : half_impl::half_base(h) {}\n\n  explicit EIGEN_DEVICE_FUNC half(bool b)\n      : half_impl::half_base(half_impl::raw_uint16_to_half(b ? 0x3c00 : 0)) {}\n  template<class T>\n  explicit EIGEN_DEVICE_FUNC half(const T& val)\n      : half_impl::half_base(half_impl::float_to_half_rtne(static_cast<float>(val))) {}\n  explicit EIGEN_DEVICE_FUNC half(float f)\n      : half_impl::half_base(half_impl::float_to_half_rtne(f)) {}\n\n  EIGEN_DEVICE_FUNC EIGEN_EXPLICIT_CAST(bool) const {\n    // +0.0 and -0.0 become false, everything else becomes true.\n    return (x & 0x7fff) != 0;\n  }\n  EIGEN_DEVICE_FUNC EIGEN_EXPLICIT_CAST(signed char) const {\n    return static_cast<signed char>(half_impl::half_to_float(*this));\n  }\n  EIGEN_DEVICE_FUNC EIGEN_EXPLICIT_CAST(unsigned char) const {\n    return static_cast<unsigned char>(half_impl::half_to_float(*this));\n  }\n  EIGEN_DEVICE_FUNC EIGEN_EXPLICIT_CAST(short) const {\n    return static_cast<short>(half_impl::half_to_float(*this));\n  }\n  EIGEN_DEVICE_FUNC EIGEN_EXPLICIT_CAST(unsigned short) const {\n    return static_cast<unsigned short>(half_impl::half_to_float(*this));\n  }\n  EIGEN_DEVICE_FUNC EIGEN_EXPLICIT_CAST(int) const {\n    return static_cast<int>(half_impl::half_to_float(*this));\n  }\n  EIGEN_DEVICE_FUNC EIGEN_EXPLICIT_CAST(unsigned int) const {\n    return static_cast<unsigned int>(half_impl::half_to_float(*this));\n  }\n  EIGEN_DEVICE_FUNC EIGEN_EXPLICIT_CAST(long) const {\n    return static_cast<long>(half_impl::half_to_float(*this));\n  }\n  EIGEN_DEVICE_FUNC EIGEN_EXPLICIT_CAST(unsigned long) const {\n    return static_cast<unsigned long>(half_impl::half_to_float(*this));\n  }\n  EIGEN_DEVICE_FUNC EIGEN_EXPLICIT_CAST(long long) const {\n    return static_cast<long long>(half_impl::half_to_float(*this));\n  }\n  EIGEN_DEVICE_FUNC EIGEN_EXPLICIT_CAST(unsigned long long) const {\n    return static_cast<unsigned long long>(half_to_float(*this));\n  }\n  EIGEN_DEVICE_FUNC EIGEN_EXPLICIT_CAST(float) const {\n    return half_impl::half_to_float(*this);\n  }\n  EIGEN_DEVICE_FUNC EIGEN_EXPLICIT_CAST(double) const {\n    return static_cast<double>(half_impl::half_to_float(*this));\n  }\n\n  EIGEN_DEVICE_FUNC half& operator=(const half& other) {\n    x = other.x;\n    return *this;\n  }\n};\n\nnamespace half_impl {\n\n#if defined(EIGEN_HAS_CUDA_FP16) && defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 530\n\n// Intrinsics for native fp16 support. Note that on current hardware,\n// these are no faster than fp32 arithmetic (you need to use the half2\n// versions to get the ALU speed increased), but you do save the\n// conversion steps back and forth.\n\n__device__ half operator + (const half& a, const half& b) {\n  return __hadd(a, b);\n}\n__device__ half operator * (const half& a, const half& b) {\n  return __hmul(a, b);\n}\n__device__ half operator - (const half& a, const half& b) {\n  return __hsub(a, b);\n}\n__device__ half operator / (const half& a, const half& b) {\n  float num = __half2float(a);\n  float denom = __half2float(b);\n  return __float2half(num / denom);\n}\n__device__ half operator - (const half& a) {\n  return __hneg(a);\n}\n__device__ half& operator += (half& a, const half& b) {\n  a = a + b;\n  return a;\n}\n__device__ half& operator *= (half& a, const half& b) {\n  a = a * b;\n  return a;\n}\n__device__ half& operator -= (half& a, const half& b) {\n  a = a - b;\n  return a;\n}\n__device__ half& operator /= (half& a, const half& b) {\n  a = a / b;\n  return a;\n}\n__device__ bool operator == (const half& a, const half& b) {\n  return __heq(a, b);\n}\n__device__ bool operator != (const half& a, const half& b) {\n  return __hne(a, b);\n}\n__device__ bool operator < (const half& a, const half& b) {\n  return __hlt(a, b);\n}\n__device__ bool operator <= (const half& a, const half& b) {\n  return __hle(a, b);\n}\n__device__ bool operator > (const half& a, const half& b) {\n  return __hgt(a, b);\n}\n__device__ bool operator >= (const half& a, const half& b) {\n  return __hge(a, b);\n}\n\n#else  // Emulate support for half floats\n\n// Definitions for CPUs and older CUDA, mostly working through conversion\n// to/from fp32.\n\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC half operator + (const half& a, const half& b) {\n  return half(float(a) + float(b));\n}\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC half operator * (const half& a, const half& b) {\n  return half(float(a) * float(b));\n}\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC half operator - (const half& a, const half& b) {\n  return half(float(a) - float(b));\n}\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC half operator / (const half& a, const half& b) {\n  return half(float(a) / float(b));\n}\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC half operator - (const half& a) {\n  half result;\n  result.x = a.x ^ 0x8000;\n  return result;\n}\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC half& operator += (half& a, const half& b) {\n  a = half(float(a) + float(b));\n  return a;\n}\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC half& operator *= (half& a, const half& b) {\n  a = half(float(a) * float(b));\n  return a;\n}\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC half& operator -= (half& a, const half& b) {\n  a = half(float(a) - float(b));\n  return a;\n}\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC half& operator /= (half& a, const half& b) {\n  a = half(float(a) / float(b));\n  return a;\n}\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC bool operator == (const half& a, const half& b) {\n  return float(a) == float(b);\n}\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC bool operator != (const half& a, const half& b) {\n  return float(a) != float(b);\n}\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC bool operator < (const half& a, const half& b) {\n  return float(a) < float(b);\n}\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC bool operator <= (const half& a, const half& b) {\n  return float(a) <= float(b);\n}\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC bool operator > (const half& a, const half& b) {\n  return float(a) > float(b);\n}\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC bool operator >= (const half& a, const half& b) {\n  return float(a) >= float(b);\n}\n\n#endif  // Emulate support for half floats\n\n// Division by an index. Do it in full float precision to avoid accuracy\n// issues in converting the denominator to half.\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC half operator / (const half& a, Index b) {\n  return half(static_cast<float>(a) / static_cast<float>(b));\n}\n\n// Conversion routines, including fallbacks for the host or older CUDA.\n// Note that newer Intel CPUs (Haswell or newer) have vectorized versions of\n// these in hardware. If we need more performance on older/other CPUs, they are\n// also possible to vectorize directly.\n\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC __half raw_uint16_to_half(unsigned short x) {\n  __half h;\n  h.x = x;\n  return h;\n}\n\nunion FP32 {\n  unsigned int u;\n  float f;\n};\n\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC __half float_to_half_rtne(float ff) {\n#if defined(EIGEN_HAS_CUDA_FP16) && defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 300\n  return __float2half(ff);\n\n#elif defined(EIGEN_HAS_FP16_C)\n  __half h;\n  h.x = _cvtss_sh(ff, 0);\n  return h;\n\n#else\n  FP32 f; f.f = ff;\n\n  const FP32 f32infty = { 255 << 23 };\n  const FP32 f16max = { (127 + 16) << 23 };\n  const FP32 denorm_magic = { ((127 - 15) + (23 - 10) + 1) << 23 };\n  unsigned int sign_mask = 0x80000000u;\n  __half o;\n  o.x = static_cast<unsigned short>(0x0u);\n\n  unsigned int sign = f.u & sign_mask;\n  f.u ^= sign;\n\n  // NOTE all the integer compares in this function can be safely\n  // compiled into signed compares since all operands are below\n  // 0x80000000. Important if you want fast straight SSE2 code\n  // (since there's no unsigned PCMPGTD).\n\n  if (f.u >= f16max.u) {  // result is Inf or NaN (all exponent bits set)\n    o.x = (f.u > f32infty.u) ? 0x7e00 : 0x7c00; // NaN->qNaN and Inf->Inf\n  } else {  // (De)normalized number or zero\n    if (f.u < (113 << 23)) {  // resulting FP16 is subnormal or zero\n      // use a magic value to align our 10 mantissa bits at the bottom of\n      // the float. as long as FP addition is round-to-nearest-even this\n      // just works.\n      f.f += denorm_magic.f;\n\n      // and one integer subtract of the bias later, we have our final float!\n      o.x = static_cast<unsigned short>(f.u - denorm_magic.u);\n    } else {\n      unsigned int mant_odd = (f.u >> 13) & 1; // resulting mantissa is odd\n\n      // update exponent, rounding bias part 1\n      f.u += ((unsigned int)(15 - 127) << 23) + 0xfff;\n      // rounding bias part 2\n      f.u += mant_odd;\n      // take the bits!\n      o.x = static_cast<unsigned short>(f.u >> 13);\n    }\n  }\n\n  o.x |= static_cast<unsigned short>(sign >> 16);\n  return o;\n#endif\n}\n\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC float half_to_float(__half h) {\n#if defined(EIGEN_HAS_CUDA_FP16) && defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 300\n  return __half2float(h);\n\n#elif defined(EIGEN_HAS_FP16_C)\n  return _cvtsh_ss(h.x);\n\n#else\n  const FP32 magic = { 113 << 23 };\n  const unsigned int shifted_exp = 0x7c00 << 13; // exponent mask after shift\n  FP32 o;\n\n  o.u = (h.x & 0x7fff) << 13;             // exponent/mantissa bits\n  unsigned int exp = shifted_exp & o.u;   // just the exponent\n  o.u += (127 - 15) << 23;                // exponent adjust\n\n  // handle exponent special cases\n  if (exp == shifted_exp) {     // Inf/NaN?\n    o.u += (128 - 16) << 23;    // extra exp adjust\n  } else if (exp == 0) {        // Zero/Denormal?\n    o.u += 1 << 23;             // extra exp adjust\n    o.f -= magic.f;             // renormalize\n  }\n\n  o.u |= (h.x & 0x8000) << 16;    // sign bit\n  return o.f;\n#endif\n}\n\n// --- standard functions ---\n\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC bool (isinf)(const half& a) {\n  return (a.x & 0x7fff) == 0x7c00;\n}\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC bool (isnan)(const half& a) {\n#if defined(EIGEN_HAS_CUDA_FP16) && defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 530\n  return __hisnan(a);\n#else\n  return (a.x & 0x7fff) > 0x7c00;\n#endif\n}\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC bool (isfinite)(const half& a) {\n  return !(isinf EIGEN_NOT_A_MACRO (a)) && !(isnan EIGEN_NOT_A_MACRO (a));\n}\n\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC half abs(const half& a) {\n  half result;\n  result.x = a.x & 0x7FFF;\n  return result;\n}\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC half exp(const half& a) {\n  return half(::expf(float(a)));\n}\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC half log(const half& a) {\n#if defined(EIGEN_HAS_CUDA_FP16) && defined __CUDACC_VER__ && __CUDACC_VER__ >= 80000 && defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 530\n  return Eigen::half(::hlog(a));\n#else\n  return half(::logf(float(a)));\n#endif\n}\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC half log1p(const half& a) {\n  return half(numext::log1p(float(a)));\n}\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC half log10(const half& a) {\n  return half(::log10f(float(a)));\n}\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC half sqrt(const half& a) {\n  return half(::sqrtf(float(a)));\n}\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC half pow(const half& a, const half& b) {\n  return half(::powf(float(a), float(b)));\n}\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC half sin(const half& a) {\n  return half(::sinf(float(a)));\n}\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC half cos(const half& a) {\n  return half(::cosf(float(a)));\n}\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC half tan(const half& a) {\n  return half(::tanf(float(a)));\n}\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC half tanh(const half& a) {\n  return half(::tanhf(float(a)));\n}\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC half floor(const half& a) {\n  return half(::floorf(float(a)));\n}\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC half ceil(const half& a) {\n  return half(::ceilf(float(a)));\n}\n\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC half (min)(const half& a, const half& b) {\n#if defined(EIGEN_HAS_CUDA_FP16) && defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 530\n  return __hlt(b, a) ? b : a;\n#else\n  const float f1 = static_cast<float>(a);\n  const float f2 = static_cast<float>(b);\n  return f2 < f1 ? b : a;\n#endif\n}\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC half (max)(const half& a, const half& b) {\n#if defined(EIGEN_HAS_CUDA_FP16) && defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 530\n  return __hlt(a, b) ? b : a;\n#else\n  const float f1 = static_cast<float>(a);\n  const float f2 = static_cast<float>(b);\n  return f1 < f2 ? b : a;\n#endif\n}\n\nEIGEN_ALWAYS_INLINE std::ostream& operator << (std::ostream& os, const half& v) {\n  os << static_cast<float>(v);\n  return os;\n}\n\n} // end namespace half_impl\n\n// import Eigen::half_impl::half into Eigen namespace\n// using half_impl::half;\n\nnamespace internal {\n\ntemplate<>\nstruct random_default_impl<half, false, false>\n{\n  static inline half run(const half& x, const half& y)\n  {\n    return x + (y-x) * half(float(std::rand()) / float(RAND_MAX));\n  }\n  static inline half run()\n  {\n    return run(half(-1.f), half(1.f));\n  }\n};\n\ntemplate<> struct is_arithmetic<half> { enum { value = true }; };\n\n} // end namespace internal\n\ntemplate<> struct NumTraits<Eigen::half>\n    : GenericNumTraits<Eigen::half>\n{\n  EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE Eigen::half epsilon() {\n    return half_impl::raw_uint16_to_half(0x0800);\n  }\n  EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE Eigen::half dummy_precision() { return Eigen::half(1e-2f); }\n  EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE Eigen::half highest() {\n    return half_impl::raw_uint16_to_half(0x7bff);\n  }\n  EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE Eigen::half lowest() {\n    return half_impl::raw_uint16_to_half(0xfbff);\n  }\n  EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE Eigen::half infinity() {\n    return half_impl::raw_uint16_to_half(0x7c00);\n  }\n  EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE Eigen::half quiet_NaN() {\n    return half_impl::raw_uint16_to_half(0x7c01);\n  }\n};\n\n} // end namespace Eigen\n\n// C-like standard mathematical functions and trancendentals.\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC Eigen::half fabsh(const Eigen::half& a) {\n  Eigen::half result;\n  result.x = a.x & 0x7FFF;\n  return result;\n}\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC Eigen::half exph(const Eigen::half& a) {\n  return Eigen::half(::expf(float(a)));\n}\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC Eigen::half logh(const Eigen::half& a) {\n#if defined __CUDACC_VER__ && __CUDACC_VER__ >= 80000 && defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 530\n  return Eigen::half(::hlog(a));\n#else\n  return Eigen::half(::logf(float(a)));\n#endif\n}\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC Eigen::half sqrth(const Eigen::half& a) {\n  return Eigen::half(::sqrtf(float(a)));\n}\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC Eigen::half powh(const Eigen::half& a, const Eigen::half& b) {\n  return Eigen::half(::powf(float(a), float(b)));\n}\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC Eigen::half floorh(const Eigen::half& a) {\n  return Eigen::half(::floorf(float(a)));\n}\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC Eigen::half ceilh(const Eigen::half& a) {\n  return Eigen::half(::ceilf(float(a)));\n}\n\nnamespace std {\n\n#if __cplusplus > 199711L\ntemplate <>\nstruct hash<Eigen::half> {\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE std::size_t operator()(const Eigen::half& a) const {\n    return static_cast<std::size_t>(a.x);\n  }\n};\n#endif\n\n} // end namespace std\n\n\n// Add the missing shfl_xor intrinsic\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 300\n__device__ EIGEN_STRONG_INLINE Eigen::half __shfl_xor(Eigen::half var, int laneMask, int width=warpSize) {\n  return static_cast<Eigen::half>(__shfl_xor(static_cast<float>(var), laneMask, width));\n}\n#endif\n\n// ldg() has an overload for __half, but we also need one for Eigen::half.\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 350\nEIGEN_STRONG_INLINE EIGEN_DEVICE_FUNC Eigen::half __ldg(const Eigen::half* ptr) {\n  return Eigen::half_impl::raw_uint16_to_half(\n      __ldg(reinterpret_cast<const unsigned short*>(ptr)));\n}\n#endif\n\n\n#if defined(__CUDA_ARCH__)\nnamespace Eigen {\nnamespace numext {\n\ntemplate<>\nEIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\nbool (isnan)(const Eigen::half& h) {\n  return (half_impl::isnan)(h);\n}\n\ntemplate<>\nEIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\nbool (isinf)(const Eigen::half& h) {\n  return (half_impl::isinf)(h);\n}\n\ntemplate<>\nEIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\nbool (isfinite)(const Eigen::half& h) {\n  return (half_impl::isfinite)(h);\n}\n\n} // namespace Eigen\n}  // namespace numext\n#endif\n\n#endif // EIGEN_HALF_CUDA_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/arch/CUDA/MathFunctions.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2014 Benoit Steiner <benoit.steiner.goog@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_MATH_FUNCTIONS_CUDA_H\n#define EIGEN_MATH_FUNCTIONS_CUDA_H\n\nnamespace Eigen {\n\nnamespace internal {\n\n// Make sure this is only available when targeting a GPU: we don't want to\n// introduce conflicts between these packet_traits definitions and the ones\n// we'll use on the host side (SSE, AVX, ...)\n#if defined(__CUDACC__) && defined(EIGEN_USE_GPU)\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\nfloat4 plog<float4>(const float4& a)\n{\n  return make_float4(logf(a.x), logf(a.y), logf(a.z), logf(a.w));\n}\n\ntemplate<>  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\ndouble2 plog<double2>(const double2& a)\n{\n  using ::log;\n  return make_double2(log(a.x), log(a.y));\n}\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\nfloat4 plog1p<float4>(const float4& a)\n{\n  return make_float4(log1pf(a.x), log1pf(a.y), log1pf(a.z), log1pf(a.w));\n}\n\ntemplate<>  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\ndouble2 plog1p<double2>(const double2& a)\n{\n  return make_double2(log1p(a.x), log1p(a.y));\n}\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\nfloat4 pexp<float4>(const float4& a)\n{\n  return make_float4(expf(a.x), expf(a.y), expf(a.z), expf(a.w));\n}\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\ndouble2 pexp<double2>(const double2& a)\n{\n  using ::exp;\n  return make_double2(exp(a.x), exp(a.y));\n}\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\nfloat4 psqrt<float4>(const float4& a)\n{\n  return make_float4(sqrtf(a.x), sqrtf(a.y), sqrtf(a.z), sqrtf(a.w));\n}\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\ndouble2 psqrt<double2>(const double2& a)\n{\n  using ::sqrt;\n  return make_double2(sqrt(a.x), sqrt(a.y));\n}\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\nfloat4 prsqrt<float4>(const float4& a)\n{\n  return make_float4(rsqrtf(a.x), rsqrtf(a.y), rsqrtf(a.z), rsqrtf(a.w));\n}\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\ndouble2 prsqrt<double2>(const double2& a)\n{\n  return make_double2(rsqrt(a.x), rsqrt(a.y));\n}\n\n\n#endif\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_MATH_FUNCTIONS_CUDA_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/arch/CUDA/PacketMath.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2014 Benoit Steiner <benoit.steiner.goog@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_PACKET_MATH_CUDA_H\n#define EIGEN_PACKET_MATH_CUDA_H\n\nnamespace Eigen {\n\nnamespace internal {\n\n// Make sure this is only available when targeting a GPU: we don't want to\n// introduce conflicts between these packet_traits definitions and the ones\n// we'll use on the host side (SSE, AVX, ...)\n#if defined(__CUDACC__) && defined(EIGEN_USE_GPU)\ntemplate<> struct is_arithmetic<float4>  { enum { value = true }; };\ntemplate<> struct is_arithmetic<double2> { enum { value = true }; };\n\ntemplate<> struct packet_traits<float> : default_packet_traits\n{\n  typedef float4 type;\n  typedef float4 half;\n  enum {\n    Vectorizable = 1,\n    AlignedOnScalar = 1,\n    size=4,\n    HasHalfPacket = 0,\n\n    HasDiv  = 1,\n    HasSin  = 0,\n    HasCos  = 0,\n    HasLog  = 1,\n    HasExp  = 1,\n    HasSqrt = 1,\n    HasRsqrt = 1,\n    HasLGamma = 1,\n    HasDiGamma = 1,\n    HasZeta = 1,\n    HasPolygamma = 1,\n    HasErf = 1,\n    HasErfc = 1,\n    HasIGamma = 1,\n    HasIGammac = 1,\n    HasBetaInc = 1,\n\n    HasBlend = 0,\n  };\n};\n\ntemplate<> struct packet_traits<double> : default_packet_traits\n{\n  typedef double2 type;\n  typedef double2 half;\n  enum {\n    Vectorizable = 1,\n    AlignedOnScalar = 1,\n    size=2,\n    HasHalfPacket = 0,\n\n    HasDiv  = 1,\n    HasLog  = 1,\n    HasExp  = 1,\n    HasSqrt = 1,\n    HasRsqrt = 1,\n    HasLGamma = 1,\n    HasDiGamma = 1,\n    HasZeta = 1,\n    HasPolygamma = 1,\n    HasErf = 1,\n    HasErfc = 1,\n    HasIGamma = 1,\n    HasIGammac = 1,\n    HasBetaInc = 1,\n\n    HasBlend = 0,\n  };\n};\n\n\ntemplate<> struct unpacket_traits<float4>  { typedef float  type; enum {size=4, alignment=Aligned16}; typedef float4 half; };\ntemplate<> struct unpacket_traits<double2> { typedef double type; enum {size=2, alignment=Aligned16}; typedef double2 half; };\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE float4 pset1<float4>(const float&  from) {\n  return make_float4(from, from, from, from);\n}\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE double2 pset1<double2>(const double& from) {\n  return make_double2(from, from);\n}\n\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE float4 plset<float4>(const float& a) {\n  return make_float4(a, a+1, a+2, a+3);\n}\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE double2 plset<double2>(const double& a) {\n  return make_double2(a, a+1);\n}\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE float4 padd<float4>(const float4& a, const float4& b) {\n  return make_float4(a.x+b.x, a.y+b.y, a.z+b.z, a.w+b.w);\n}\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE double2 padd<double2>(const double2& a, const double2& b) {\n  return make_double2(a.x+b.x, a.y+b.y);\n}\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE float4 psub<float4>(const float4& a, const float4& b) {\n  return make_float4(a.x-b.x, a.y-b.y, a.z-b.z, a.w-b.w);\n}\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE double2 psub<double2>(const double2& a, const double2& b) {\n  return make_double2(a.x-b.x, a.y-b.y);\n}\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE float4 pnegate(const float4& a) {\n  return make_float4(-a.x, -a.y, -a.z, -a.w);\n}\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE double2 pnegate(const double2& a) {\n  return make_double2(-a.x, -a.y);\n}\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE float4 pconj(const float4& a) { return a; }\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE double2 pconj(const double2& a) { return a; }\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE float4 pmul<float4>(const float4& a, const float4& b) {\n  return make_float4(a.x*b.x, a.y*b.y, a.z*b.z, a.w*b.w);\n}\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE double2 pmul<double2>(const double2& a, const double2& b) {\n  return make_double2(a.x*b.x, a.y*b.y);\n}\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE float4 pdiv<float4>(const float4& a, const float4& b) {\n  return make_float4(a.x/b.x, a.y/b.y, a.z/b.z, a.w/b.w);\n}\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE double2 pdiv<double2>(const double2& a, const double2& b) {\n  return make_double2(a.x/b.x, a.y/b.y);\n}\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE float4 pmin<float4>(const float4& a, const float4& b) {\n  return make_float4(fminf(a.x, b.x), fminf(a.y, b.y), fminf(a.z, b.z), fminf(a.w, b.w));\n}\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE double2 pmin<double2>(const double2& a, const double2& b) {\n  return make_double2(fmin(a.x, b.x), fmin(a.y, b.y));\n}\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE float4 pmax<float4>(const float4& a, const float4& b) {\n  return make_float4(fmaxf(a.x, b.x), fmaxf(a.y, b.y), fmaxf(a.z, b.z), fmaxf(a.w, b.w));\n}\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE double2 pmax<double2>(const double2& a, const double2& b) {\n  return make_double2(fmax(a.x, b.x), fmax(a.y, b.y));\n}\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE float4 pload<float4>(const float* from) {\n  return *reinterpret_cast<const float4*>(from);\n}\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE double2 pload<double2>(const double* from) {\n  return *reinterpret_cast<const double2*>(from);\n}\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE float4 ploadu<float4>(const float* from) {\n  return make_float4(from[0], from[1], from[2], from[3]);\n}\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE double2 ploadu<double2>(const double* from) {\n  return make_double2(from[0], from[1]);\n}\n\ntemplate<> EIGEN_STRONG_INLINE float4 ploaddup<float4>(const float*   from) {\n  return make_float4(from[0], from[0], from[1], from[1]);\n}\ntemplate<> EIGEN_STRONG_INLINE double2 ploaddup<double2>(const double*  from) {\n  return make_double2(from[0], from[0]);\n}\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE void pstore<float>(float*   to, const float4& from) {\n  *reinterpret_cast<float4*>(to) = from;\n}\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE void pstore<double>(double* to, const double2& from) {\n  *reinterpret_cast<double2*>(to) = from;\n}\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE void pstoreu<float>(float*  to, const float4& from) {\n  to[0] = from.x;\n  to[1] = from.y;\n  to[2] = from.z;\n  to[3] = from.w;\n}\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE void pstoreu<double>(double* to, const double2& from) {\n  to[0] = from.x;\n  to[1] = from.y;\n}\n\ntemplate<>\nEIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE float4 ploadt_ro<float4, Aligned>(const float* from) {\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 350\n  return __ldg((const float4*)from);\n#else\n  return make_float4(from[0], from[1], from[2], from[3]);\n#endif\n}\ntemplate<>\nEIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE double2 ploadt_ro<double2, Aligned>(const double* from) {\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 350\n  return __ldg((const double2*)from);\n#else\n  return make_double2(from[0], from[1]);\n#endif\n}\n\ntemplate<>\nEIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE float4 ploadt_ro<float4, Unaligned>(const float* from) {\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 350\n  return make_float4(__ldg(from+0), __ldg(from+1), __ldg(from+2), __ldg(from+3));\n#else\n  return make_float4(from[0], from[1], from[2], from[3]);\n#endif\n}\ntemplate<>\nEIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE double2 ploadt_ro<double2, Unaligned>(const double* from) {\n#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 350\n  return make_double2(__ldg(from+0), __ldg(from+1));\n#else\n  return make_double2(from[0], from[1]);\n#endif\n}\n\ntemplate<> EIGEN_DEVICE_FUNC inline float4 pgather<float, float4>(const float* from, Index stride) {\n  return make_float4(from[0*stride], from[1*stride], from[2*stride], from[3*stride]);\n}\n\ntemplate<> EIGEN_DEVICE_FUNC inline double2 pgather<double, double2>(const double* from, Index stride) {\n  return make_double2(from[0*stride], from[1*stride]);\n}\n\ntemplate<> EIGEN_DEVICE_FUNC inline void pscatter<float, float4>(float* to, const float4& from, Index stride) {\n  to[stride*0] = from.x;\n  to[stride*1] = from.y;\n  to[stride*2] = from.z;\n  to[stride*3] = from.w;\n}\ntemplate<> EIGEN_DEVICE_FUNC inline void pscatter<double, double2>(double* to, const double2& from, Index stride) {\n  to[stride*0] = from.x;\n  to[stride*1] = from.y;\n}\n\ntemplate<> EIGEN_DEVICE_FUNC inline float  pfirst<float4>(const float4& a) {\n  return a.x;\n}\ntemplate<> EIGEN_DEVICE_FUNC inline double pfirst<double2>(const double2& a) {\n  return a.x;\n}\n\ntemplate<> EIGEN_DEVICE_FUNC inline float  predux<float4>(const float4& a) {\n  return a.x + a.y + a.z + a.w;\n}\ntemplate<> EIGEN_DEVICE_FUNC inline double predux<double2>(const double2& a) {\n  return a.x + a.y;\n}\n\ntemplate<> EIGEN_DEVICE_FUNC inline float  predux_max<float4>(const float4& a) {\n  return fmaxf(fmaxf(a.x, a.y), fmaxf(a.z, a.w));\n}\ntemplate<> EIGEN_DEVICE_FUNC inline double predux_max<double2>(const double2& a) {\n  return fmax(a.x, a.y);\n}\n\ntemplate<> EIGEN_DEVICE_FUNC inline float  predux_min<float4>(const float4& a) {\n  return fminf(fminf(a.x, a.y), fminf(a.z, a.w));\n}\ntemplate<> EIGEN_DEVICE_FUNC inline double predux_min<double2>(const double2& a) {\n  return fmin(a.x, a.y);\n}\n\ntemplate<> EIGEN_DEVICE_FUNC inline float  predux_mul<float4>(const float4& a) {\n  return a.x * a.y * a.z * a.w;\n}\ntemplate<> EIGEN_DEVICE_FUNC inline double predux_mul<double2>(const double2& a) {\n  return a.x * a.y;\n}\n\ntemplate<> EIGEN_DEVICE_FUNC inline float4  pabs<float4>(const float4& a) {\n  return make_float4(fabsf(a.x), fabsf(a.y), fabsf(a.z), fabsf(a.w));\n}\ntemplate<> EIGEN_DEVICE_FUNC inline double2 pabs<double2>(const double2& a) {\n  return make_double2(fabs(a.x), fabs(a.y));\n}\n\nEIGEN_DEVICE_FUNC inline void\nptranspose(PacketBlock<float4,4>& kernel) {\n  double tmp = kernel.packet[0].y;\n  kernel.packet[0].y = kernel.packet[1].x;\n  kernel.packet[1].x = tmp;\n\n  tmp = kernel.packet[0].z;\n  kernel.packet[0].z = kernel.packet[2].x;\n  kernel.packet[2].x = tmp;\n\n  tmp = kernel.packet[0].w;\n  kernel.packet[0].w = kernel.packet[3].x;\n  kernel.packet[3].x = tmp;\n\n  tmp = kernel.packet[1].z;\n  kernel.packet[1].z = kernel.packet[2].y;\n  kernel.packet[2].y = tmp;\n\n  tmp = kernel.packet[1].w;\n  kernel.packet[1].w = kernel.packet[3].y;\n  kernel.packet[3].y = tmp;\n\n  tmp = kernel.packet[2].w;\n  kernel.packet[2].w = kernel.packet[3].z;\n  kernel.packet[3].z = tmp;\n}\n\nEIGEN_DEVICE_FUNC inline void\nptranspose(PacketBlock<double2,2>& kernel) {\n  double tmp = kernel.packet[0].y;\n  kernel.packet[0].y = kernel.packet[1].x;\n  kernel.packet[1].x = tmp;\n}\n\n#endif\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n\n#endif // EIGEN_PACKET_MATH_CUDA_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/arch/CUDA/PacketMathHalf.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2016 Benoit Steiner <benoit.steiner.goog@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_PACKET_MATH_HALF_CUDA_H\n#define EIGEN_PACKET_MATH_HALF_CUDA_H\n\n\nnamespace Eigen {\nnamespace internal {\n\n// Most of the following operations require arch >= 3.0\n#if defined(EIGEN_HAS_CUDA_FP16) && defined(__CUDACC__) && defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 300\n\ntemplate<> struct is_arithmetic<half2> { enum { value = true }; };\n\ntemplate<> struct packet_traits<Eigen::half> : default_packet_traits\n{\n  typedef half2 type;\n  typedef half2 half;\n  enum {\n    Vectorizable = 1,\n    AlignedOnScalar = 1,\n    size=2,\n    HasHalfPacket = 0,\n    HasAdd    = 1,\n    HasMul    = 1,\n    HasDiv    = 1,\n    HasSqrt   = 1,\n    HasRsqrt  = 1,\n    HasExp    = 1,\n    HasLog    = 1,\n    HasLog1p  = 1\n  };\n};\n\ntemplate<> struct unpacket_traits<half2> { typedef Eigen::half type; enum {size=2, alignment=Aligned16}; typedef half2 half; };\n\ntemplate<> __device__ EIGEN_STRONG_INLINE half2 pset1<half2>(const Eigen::half& from) {\n  return __half2half2(from);\n}\n\ntemplate<> __device__ EIGEN_STRONG_INLINE half2 pload<half2>(const Eigen::half* from) {\n  return *reinterpret_cast<const half2*>(from);\n}\n\ntemplate<> __device__ EIGEN_STRONG_INLINE half2 ploadu<half2>(const Eigen::half* from) {\n  return __halves2half2(from[0], from[1]);\n}\n\ntemplate<> EIGEN_STRONG_INLINE half2 ploaddup<half2>(const Eigen::half*  from) {\n  return __halves2half2(from[0], from[0]);\n}\n\ntemplate<> __device__ EIGEN_STRONG_INLINE void pstore<Eigen::half>(Eigen::half* to, const half2& from) {\n  *reinterpret_cast<half2*>(to) = from;\n}\n\ntemplate<> __device__ EIGEN_STRONG_INLINE void pstoreu<Eigen::half>(Eigen::half* to, const half2& from) {\n  to[0] = __low2half(from);\n  to[1] = __high2half(from);\n}\n\ntemplate<>\n __device__ EIGEN_ALWAYS_INLINE half2 ploadt_ro<half2, Aligned>(const Eigen::half* from) {\n#if __CUDA_ARCH__ >= 350\n   return __ldg((const half2*)from);\n#else\n  return __halves2half2(*(from+0), *(from+1));\n#endif\n}\n\ntemplate<>\n__device__ EIGEN_ALWAYS_INLINE half2 ploadt_ro<half2, Unaligned>(const Eigen::half* from) {\n#if __CUDA_ARCH__ >= 350\n   return __halves2half2(__ldg(from+0), __ldg(from+1));\n#else\n  return __halves2half2(*(from+0), *(from+1));\n#endif\n}\n\ntemplate<> __device__ EIGEN_STRONG_INLINE half2 pgather<Eigen::half, half2>(const Eigen::half* from, Index stride) {\n  return __halves2half2(from[0*stride], from[1*stride]);\n}\n\ntemplate<> __device__ EIGEN_STRONG_INLINE void pscatter<Eigen::half, half2>(Eigen::half* to, const half2& from, Index stride) {\n  to[stride*0] = __low2half(from);\n  to[stride*1] = __high2half(from);\n}\n\ntemplate<> __device__ EIGEN_STRONG_INLINE Eigen::half pfirst<half2>(const half2& a) {\n  return __low2half(a);\n}\n\ntemplate<> __device__ EIGEN_STRONG_INLINE half2 pabs<half2>(const half2& a) {\n  half2 result;\n  result.x = a.x & 0x7FFF7FFF;\n  return result;\n}\n\n\n__device__ EIGEN_STRONG_INLINE void\nptranspose(PacketBlock<half2,2>& kernel) {\n  __half a1 = __low2half(kernel.packet[0]);\n  __half a2 = __high2half(kernel.packet[0]);\n  __half b1 = __low2half(kernel.packet[1]);\n  __half b2 = __high2half(kernel.packet[1]);\n  kernel.packet[0] = __halves2half2(a1, b1);\n  kernel.packet[1] = __halves2half2(a2, b2);\n}\n\ntemplate<> __device__ EIGEN_STRONG_INLINE half2 plset<half2>(const Eigen::half& a) {\n#if __CUDA_ARCH__ >= 530\n  return __halves2half2(a, __hadd(a, __float2half(1.0f)));\n#else\n  float f = __half2float(a) + 1.0f;\n  return __halves2half2(a, __float2half(f));\n#endif\n}\n\ntemplate<> __device__ EIGEN_STRONG_INLINE half2 padd<half2>(const half2& a, const half2& b) {\n#if __CUDA_ARCH__ >= 530\n  return __hadd2(a, b);\n#else\n  float a1 = __low2float(a);\n  float a2 = __high2float(a);\n  float b1 = __low2float(b);\n  float b2 = __high2float(b);\n  float r1 = a1 + b1;\n  float r2 = a2 + b2;\n  return __floats2half2_rn(r1, r2);\n#endif\n}\n\ntemplate<> __device__ EIGEN_STRONG_INLINE half2 psub<half2>(const half2& a, const half2& b) {\n#if __CUDA_ARCH__ >= 530\n  return __hsub2(a, b);\n#else\n  float a1 = __low2float(a);\n  float a2 = __high2float(a);\n  float b1 = __low2float(b);\n  float b2 = __high2float(b);\n  float r1 = a1 - b1;\n  float r2 = a2 - b2;\n  return __floats2half2_rn(r1, r2);\n#endif\n}\n\ntemplate<> __device__ EIGEN_STRONG_INLINE half2 pnegate(const half2& a) {\n#if __CUDA_ARCH__ >= 530\n  return __hneg2(a);\n#else\n  float a1 = __low2float(a);\n  float a2 = __high2float(a);\n  return __floats2half2_rn(-a1, -a2);\n#endif\n}\n\ntemplate<> __device__ EIGEN_STRONG_INLINE half2 pconj(const half2& a) { return a; }\n\ntemplate<> __device__ EIGEN_STRONG_INLINE half2 pmul<half2>(const half2& a, const half2& b) {\n#if __CUDA_ARCH__ >= 530\n  return __hmul2(a, b);\n#else\n  float a1 = __low2float(a);\n  float a2 = __high2float(a);\n  float b1 = __low2float(b);\n  float b2 = __high2float(b);\n  float r1 = a1 * b1;\n  float r2 = a2 * b2;\n  return __floats2half2_rn(r1, r2);\n#endif\n}\n\ntemplate<> __device__ EIGEN_STRONG_INLINE half2 pmadd<half2>(const half2& a, const half2& b, const half2& c) {\n#if __CUDA_ARCH__ >= 530\n   return __hfma2(a, b, c);\n#else\n  float a1 = __low2float(a);\n  float a2 = __high2float(a);\n  float b1 = __low2float(b);\n  float b2 = __high2float(b);\n  float c1 = __low2float(c);\n  float c2 = __high2float(c);\n  float r1 = a1 * b1 + c1;\n  float r2 = a2 * b2 + c2;\n  return __floats2half2_rn(r1, r2);\n#endif\n}\n\ntemplate<> __device__ EIGEN_STRONG_INLINE half2 pdiv<half2>(const half2& a, const half2& b) {\n  float a1 = __low2float(a);\n  float a2 = __high2float(a);\n  float b1 = __low2float(b);\n  float b2 = __high2float(b);\n  float r1 = a1 / b1;\n  float r2 = a2 / b2;\n  return __floats2half2_rn(r1, r2);\n}\n\ntemplate<> __device__ EIGEN_STRONG_INLINE half2 pmin<half2>(const half2& a, const half2& b) {\n  float a1 = __low2float(a);\n  float a2 = __high2float(a);\n  float b1 = __low2float(b);\n  float b2 = __high2float(b);\n  __half r1 = a1 < b1 ? __low2half(a) : __low2half(b);\n  __half r2 = a2 < b2 ? __high2half(a) : __high2half(b);\n  return __halves2half2(r1, r2);\n}\n\ntemplate<> __device__ EIGEN_STRONG_INLINE half2 pmax<half2>(const half2& a, const half2& b) {\n  float a1 = __low2float(a);\n  float a2 = __high2float(a);\n  float b1 = __low2float(b);\n  float b2 = __high2float(b);\n  __half r1 = a1 > b1 ? __low2half(a) : __low2half(b);\n  __half r2 = a2 > b2 ? __high2half(a) : __high2half(b);\n  return __halves2half2(r1, r2);\n}\n\ntemplate<> __device__ EIGEN_STRONG_INLINE Eigen::half predux<half2>(const half2& a) {\n#if __CUDA_ARCH__ >= 530\n  return __hadd(__low2half(a), __high2half(a));\n#else\n  float a1 = __low2float(a);\n  float a2 = __high2float(a);\n  return Eigen::half(half_impl::raw_uint16_to_half(__float2half_rn(a1 + a2)));\n#endif\n}\n\ntemplate<> __device__ EIGEN_STRONG_INLINE Eigen::half predux_max<half2>(const half2& a) {\n#if __CUDA_ARCH__ >= 530\n  __half first = __low2half(a);\n  __half second = __high2half(a);\n  return __hgt(first, second) ? first : second;\n#else\n  float a1 = __low2float(a);\n  float a2 = __high2float(a);\n  return a1 > a2 ? __low2half(a) : __high2half(a);\n#endif\n}\n\ntemplate<> __device__ EIGEN_STRONG_INLINE Eigen::half predux_min<half2>(const half2& a) {\n#if __CUDA_ARCH__ >= 530\n  __half first = __low2half(a);\n  __half second = __high2half(a);\n  return __hlt(first, second) ? first : second;\n#else\n  float a1 = __low2float(a);\n  float a2 = __high2float(a);\n  return a1 < a2 ? __low2half(a) : __high2half(a);\n#endif\n}\n\ntemplate<> __device__ EIGEN_STRONG_INLINE Eigen::half predux_mul<half2>(const half2& a) {\n#if __CUDA_ARCH__ >= 530\n  return __hmul(__low2half(a), __high2half(a));\n#else\n  float a1 = __low2float(a);\n  float a2 = __high2float(a);\n  return Eigen::half(half_impl::raw_uint16_to_half(__float2half_rn(a1 * a2)));\n#endif\n}\n\ntemplate<> __device__ EIGEN_STRONG_INLINE half2 plog1p<half2>(const half2& a) {\n  float a1 = __low2float(a);\n  float a2 = __high2float(a);\n  float r1 = log1pf(a1);\n  float r2 = log1pf(a2);\n  return __floats2half2_rn(r1, r2);\n}\n\n#if defined __CUDACC_VER__ && __CUDACC_VER__ >= 80000 && defined __CUDA_ARCH__ && __CUDA_ARCH__ >= 530\n\ntemplate<>  __device__ EIGEN_STRONG_INLINE\nhalf2 plog<half2>(const half2& a) {\n  return h2log(a);\n}\n\ntemplate<> __device__ EIGEN_STRONG_INLINE\nhalf2 pexp<half2>(const half2& a) {\n  return h2exp(a);\n}\n\ntemplate<> __device__ EIGEN_STRONG_INLINE\nhalf2 psqrt<half2>(const half2& a) {\n  return h2sqrt(a);\n}\n\ntemplate<> __device__ EIGEN_STRONG_INLINE\nhalf2 prsqrt<half2>(const half2& a) {\n  return h2rsqrt(a);\n}\n\n#else\n\ntemplate<> __device__ EIGEN_STRONG_INLINE half2 plog<half2>(const half2& a) {\n  float a1 = __low2float(a);\n  float a2 = __high2float(a);\n  float r1 = logf(a1);\n  float r2 = logf(a2);\n  return __floats2half2_rn(r1, r2);\n}\n\ntemplate<> __device__ EIGEN_STRONG_INLINE half2 pexp<half2>(const half2& a) {\n  float a1 = __low2float(a);\n  float a2 = __high2float(a);\n  float r1 = expf(a1);\n  float r2 = expf(a2);\n  return __floats2half2_rn(r1, r2);\n}\n\ntemplate<> __device__ EIGEN_STRONG_INLINE half2 psqrt<half2>(const half2& a) {\n  float a1 = __low2float(a);\n  float a2 = __high2float(a);\n  float r1 = sqrtf(a1);\n  float r2 = sqrtf(a2);\n  return __floats2half2_rn(r1, r2);\n}\n\ntemplate<> __device__ EIGEN_STRONG_INLINE half2 prsqrt<half2>(const half2& a) {\n  float a1 = __low2float(a);\n  float a2 = __high2float(a);\n  float r1 = rsqrtf(a1);\n  float r2 = rsqrtf(a2);\n  return __floats2half2_rn(r1, r2);\n}\n\n#endif\n\n#elif defined EIGEN_VECTORIZE_AVX512\n\ntypedef struct {\n  __m256i x;\n} Packet16h;\n\n\ntemplate<> struct is_arithmetic<Packet16h> { enum { value = true }; };\n\ntemplate <>\nstruct packet_traits<half> : default_packet_traits {\n  typedef Packet16h type;\n  // There is no half-size packet for Packet16h.\n  typedef Packet16h half;\n  enum {\n    Vectorizable = 1,\n    AlignedOnScalar = 1,\n    size = 16,\n    HasHalfPacket = 0,\n    HasAdd    = 0,\n    HasSub    = 0,\n    HasMul    = 0,\n    HasNegate = 0,\n    HasAbs    = 0,\n    HasAbs2   = 0,\n    HasMin    = 0,\n    HasMax    = 0,\n    HasConj   = 0,\n    HasSetLinear = 0,\n    HasDiv = 0,\n    HasSqrt = 0,\n    HasRsqrt = 0,\n    HasExp = 0,\n    HasLog = 0,\n    HasBlend = 0\n  };\n};\n\n\ntemplate<> struct unpacket_traits<Packet16h> { typedef Eigen::half type; enum {size=16, alignment=Aligned32}; typedef Packet16h half; };\n\ntemplate<> EIGEN_STRONG_INLINE Packet16h pset1<Packet16h>(const Eigen::half& from) {\n  Packet16h result;\n  result.x = _mm256_set1_epi16(from.x);\n  return result;\n}\n\ntemplate<> EIGEN_STRONG_INLINE Eigen::half pfirst<Packet16h>(const Packet16h& from) {\n  return half_impl::raw_uint16_to_half(static_cast<unsigned short>(_mm256_extract_epi16(from.x, 0)));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet16h pload<Packet16h>(const Eigen::half* from) {\n  Packet16h result;\n  result.x = _mm256_load_si256(reinterpret_cast<const __m256i*>(from));\n  return result;\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet16h ploadu<Packet16h>(const Eigen::half* from) {\n  Packet16h result;\n  result.x = _mm256_loadu_si256(reinterpret_cast<const __m256i*>(from));\n  return result;\n}\n\ntemplate<> EIGEN_STRONG_INLINE void pstore<half>(Eigen::half* to, const Packet16h& from) {\n  _mm256_store_si256((__m256i*)to, from.x);\n}\n\ntemplate<> EIGEN_STRONG_INLINE void pstoreu<half>(Eigen::half* to, const Packet16h& from) {\n  _mm256_storeu_si256((__m256i*)to, from.x);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet16h\nploadquad(const Eigen::half* from) {\n  Packet16h result;\n  unsigned short a = from[0].x;\n  unsigned short b = from[1].x;\n  unsigned short c = from[2].x;\n  unsigned short d = from[3].x;\n  result.x = _mm256_set_epi16(d, d, d, d, c, c, c, c, b, b, b, b, a, a, a, a);\n  return result;\n}\n\nEIGEN_STRONG_INLINE Packet16f half2float(const Packet16h& a) {\n#ifdef EIGEN_HAS_FP16_C\n  return _mm512_cvtph_ps(a.x);\n#else\n  EIGEN_ALIGN64 half aux[16];\n  pstore(aux, a);\n  float f0(aux[0]);\n  float f1(aux[1]);\n  float f2(aux[2]);\n  float f3(aux[3]);\n  float f4(aux[4]);\n  float f5(aux[5]);\n  float f6(aux[6]);\n  float f7(aux[7]);\n  float f8(aux[8]);\n  float f9(aux[9]);\n  float fa(aux[10]);\n  float fb(aux[11]);\n  float fc(aux[12]);\n  float fd(aux[13]);\n  float fe(aux[14]);\n  float ff(aux[15]);\n\n  return _mm512_set_ps(\n      ff, fe, fd, fc, fb, fa, f9, f8, f7, f6, f5, f4, f3, f2, f1, f0);\n#endif\n}\n\nEIGEN_STRONG_INLINE Packet16h float2half(const Packet16f& a) {\n#ifdef EIGEN_HAS_FP16_C\n  Packet16h result;\n  result.x = _mm512_cvtps_ph(a, _MM_FROUND_TO_NEAREST_INT|_MM_FROUND_NO_EXC);\n  return result;\n#else\n  EIGEN_ALIGN64 float aux[16];\n  pstore(aux, a);\n  half h0(aux[0]);\n  half h1(aux[1]);\n  half h2(aux[2]);\n  half h3(aux[3]);\n  half h4(aux[4]);\n  half h5(aux[5]);\n  half h6(aux[6]);\n  half h7(aux[7]);\n  half h8(aux[8]);\n  half h9(aux[9]);\n  half ha(aux[10]);\n  half hb(aux[11]);\n  half hc(aux[12]);\n  half hd(aux[13]);\n  half he(aux[14]);\n  half hf(aux[15]);\n\n  Packet16h result;\n  result.x = _mm256_set_epi16(\n      hf.x, he.x, hd.x, hc.x, hb.x, ha.x, h9.x, h8.x,\n      h7.x, h6.x, h5.x, h4.x, h3.x, h2.x, h1.x, h0.x);\n  return result;\n#endif\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet16h padd<Packet16h>(const Packet16h& a, const Packet16h& b) {\n  Packet16f af = half2float(a);\n  Packet16f bf = half2float(b);\n  Packet16f rf = padd(af, bf);\n  return float2half(rf);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet16h pmul<Packet16h>(const Packet16h& a, const Packet16h& b) {\n  Packet16f af = half2float(a);\n  Packet16f bf = half2float(b);\n  Packet16f rf = pmul(af, bf);\n  return float2half(rf);\n}\n\ntemplate<> EIGEN_STRONG_INLINE half predux<Packet16h>(const Packet16h& from) {\n  Packet16f from_float = half2float(from);\n  return half(predux(from_float));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet16h pgather<Eigen::half, Packet16h>(const Eigen::half* from, Index stride)\n{\n  Packet16h result;\n  result.x = _mm256_set_epi16(\n      from[15*stride].x, from[14*stride].x, from[13*stride].x, from[12*stride].x,\n      from[11*stride].x, from[10*stride].x, from[9*stride].x, from[8*stride].x,\n      from[7*stride].x, from[6*stride].x, from[5*stride].x, from[4*stride].x,\n      from[3*stride].x, from[2*stride].x, from[1*stride].x, from[0*stride].x);\n  return result;\n}\n\ntemplate<> EIGEN_STRONG_INLINE void pscatter<half, Packet16h>(half* to, const Packet16h& from, Index stride)\n{\n  EIGEN_ALIGN64 half aux[16];\n  pstore(aux, from);\n  to[stride*0].x = aux[0].x;\n  to[stride*1].x = aux[1].x;\n  to[stride*2].x = aux[2].x;\n  to[stride*3].x = aux[3].x;\n  to[stride*4].x = aux[4].x;\n  to[stride*5].x = aux[5].x;\n  to[stride*6].x = aux[6].x;\n  to[stride*7].x = aux[7].x;\n  to[stride*8].x = aux[8].x;\n  to[stride*9].x = aux[9].x;\n  to[stride*10].x = aux[10].x;\n  to[stride*11].x = aux[11].x;\n  to[stride*12].x = aux[12].x;\n  to[stride*13].x = aux[13].x;\n  to[stride*14].x = aux[14].x;\n  to[stride*15].x = aux[15].x;\n}\n\nEIGEN_STRONG_INLINE void\nptranspose(PacketBlock<Packet16h,16>& kernel) {\n  __m256i a = kernel.packet[0].x;\n  __m256i b = kernel.packet[1].x;\n  __m256i c = kernel.packet[2].x;\n  __m256i d = kernel.packet[3].x;\n  __m256i e = kernel.packet[4].x;\n  __m256i f = kernel.packet[5].x;\n  __m256i g = kernel.packet[6].x;\n  __m256i h = kernel.packet[7].x;\n  __m256i i = kernel.packet[8].x;\n  __m256i j = kernel.packet[9].x;\n  __m256i k = kernel.packet[10].x;\n  __m256i l = kernel.packet[11].x;\n  __m256i m = kernel.packet[12].x;\n  __m256i n = kernel.packet[13].x;\n  __m256i o = kernel.packet[14].x;\n  __m256i p = kernel.packet[15].x;\n\n  __m256i ab_07 = _mm256_unpacklo_epi16(a, b);\n  __m256i cd_07 = _mm256_unpacklo_epi16(c, d);\n  __m256i ef_07 = _mm256_unpacklo_epi16(e, f);\n  __m256i gh_07 = _mm256_unpacklo_epi16(g, h);\n  __m256i ij_07 = _mm256_unpacklo_epi16(i, j);\n  __m256i kl_07 = _mm256_unpacklo_epi16(k, l);\n  __m256i mn_07 = _mm256_unpacklo_epi16(m, n);\n  __m256i op_07 = _mm256_unpacklo_epi16(o, p);\n\n  __m256i ab_8f = _mm256_unpackhi_epi16(a, b);\n  __m256i cd_8f = _mm256_unpackhi_epi16(c, d);\n  __m256i ef_8f = _mm256_unpackhi_epi16(e, f);\n  __m256i gh_8f = _mm256_unpackhi_epi16(g, h);\n  __m256i ij_8f = _mm256_unpackhi_epi16(i, j);\n  __m256i kl_8f = _mm256_unpackhi_epi16(k, l);\n  __m256i mn_8f = _mm256_unpackhi_epi16(m, n);\n  __m256i op_8f = _mm256_unpackhi_epi16(o, p);\n\n  __m256i abcd_03 = _mm256_unpacklo_epi32(ab_07, cd_07);\n  __m256i abcd_47 = _mm256_unpackhi_epi32(ab_07, cd_07);\n  __m256i efgh_03 = _mm256_unpacklo_epi32(ef_07, gh_07);\n  __m256i efgh_47 = _mm256_unpackhi_epi32(ef_07, gh_07);\n  __m256i ijkl_03 = _mm256_unpacklo_epi32(ij_07, kl_07);\n  __m256i ijkl_47 = _mm256_unpackhi_epi32(ij_07, kl_07);\n  __m256i mnop_03 = _mm256_unpacklo_epi32(mn_07, op_07);\n  __m256i mnop_47 = _mm256_unpackhi_epi32(mn_07, op_07);\n\n  __m256i abcd_8b = _mm256_unpacklo_epi32(ab_8f, cd_8f);\n  __m256i abcd_cf = _mm256_unpackhi_epi32(ab_8f, cd_8f);\n  __m256i efgh_8b = _mm256_unpacklo_epi32(ef_8f, gh_8f);\n  __m256i efgh_cf = _mm256_unpackhi_epi32(ef_8f, gh_8f);\n  __m256i ijkl_8b = _mm256_unpacklo_epi32(ij_8f, kl_8f);\n  __m256i ijkl_cf = _mm256_unpackhi_epi32(ij_8f, kl_8f);\n  __m256i mnop_8b = _mm256_unpacklo_epi32(mn_8f, op_8f);\n  __m256i mnop_cf = _mm256_unpackhi_epi32(mn_8f, op_8f);\n\n  __m256i abcdefgh_01 = _mm256_unpacklo_epi64(abcd_03, efgh_03);\n  __m256i abcdefgh_23 = _mm256_unpackhi_epi64(abcd_03, efgh_03);\n  __m256i ijklmnop_01 = _mm256_unpacklo_epi64(ijkl_03, mnop_03);\n  __m256i ijklmnop_23 = _mm256_unpackhi_epi64(ijkl_03, mnop_03);\n  __m256i abcdefgh_45 = _mm256_unpacklo_epi64(abcd_47, efgh_47);\n  __m256i abcdefgh_67 = _mm256_unpackhi_epi64(abcd_47, efgh_47);\n  __m256i ijklmnop_45 = _mm256_unpacklo_epi64(ijkl_47, mnop_47);\n  __m256i ijklmnop_67 = _mm256_unpackhi_epi64(ijkl_47, mnop_47);\n  __m256i abcdefgh_89 = _mm256_unpacklo_epi64(abcd_8b, efgh_8b);\n  __m256i abcdefgh_ab = _mm256_unpackhi_epi64(abcd_8b, efgh_8b);\n  __m256i ijklmnop_89 = _mm256_unpacklo_epi64(ijkl_8b, mnop_8b);\n  __m256i ijklmnop_ab = _mm256_unpackhi_epi64(ijkl_8b, mnop_8b);\n  __m256i abcdefgh_cd = _mm256_unpacklo_epi64(abcd_cf, efgh_cf);\n  __m256i abcdefgh_ef = _mm256_unpackhi_epi64(abcd_cf, efgh_cf);\n  __m256i ijklmnop_cd = _mm256_unpacklo_epi64(ijkl_cf, mnop_cf);\n  __m256i ijklmnop_ef = _mm256_unpackhi_epi64(ijkl_cf, mnop_cf);\n\n  // NOTE: no unpacklo/hi instr in this case, so using permute instr.\n  __m256i a_p_0 = _mm256_permute2x128_si256(abcdefgh_01, ijklmnop_01, 0x20);\n  __m256i a_p_1 = _mm256_permute2x128_si256(abcdefgh_01, ijklmnop_01, 0x31);\n  __m256i a_p_2 = _mm256_permute2x128_si256(abcdefgh_23, ijklmnop_23, 0x20);\n  __m256i a_p_3 = _mm256_permute2x128_si256(abcdefgh_23, ijklmnop_23, 0x31);\n  __m256i a_p_4 = _mm256_permute2x128_si256(abcdefgh_45, ijklmnop_45, 0x20);\n  __m256i a_p_5 = _mm256_permute2x128_si256(abcdefgh_45, ijklmnop_45, 0x31);\n  __m256i a_p_6 = _mm256_permute2x128_si256(abcdefgh_67, ijklmnop_67, 0x20);\n  __m256i a_p_7 = _mm256_permute2x128_si256(abcdefgh_67, ijklmnop_67, 0x31);\n  __m256i a_p_8 = _mm256_permute2x128_si256(abcdefgh_89, ijklmnop_89, 0x20);\n  __m256i a_p_9 = _mm256_permute2x128_si256(abcdefgh_89, ijklmnop_89, 0x31);\n  __m256i a_p_a = _mm256_permute2x128_si256(abcdefgh_ab, ijklmnop_ab, 0x20);\n  __m256i a_p_b = _mm256_permute2x128_si256(abcdefgh_ab, ijklmnop_ab, 0x31);\n  __m256i a_p_c = _mm256_permute2x128_si256(abcdefgh_cd, ijklmnop_cd, 0x20);\n  __m256i a_p_d = _mm256_permute2x128_si256(abcdefgh_cd, ijklmnop_cd, 0x31);\n  __m256i a_p_e = _mm256_permute2x128_si256(abcdefgh_ef, ijklmnop_ef, 0x20);\n  __m256i a_p_f = _mm256_permute2x128_si256(abcdefgh_ef, ijklmnop_ef, 0x31);\n\n  kernel.packet[0].x = a_p_0;\n  kernel.packet[1].x = a_p_1;\n  kernel.packet[2].x = a_p_2;\n  kernel.packet[3].x = a_p_3;\n  kernel.packet[4].x = a_p_4;\n  kernel.packet[5].x = a_p_5;\n  kernel.packet[6].x = a_p_6;\n  kernel.packet[7].x = a_p_7;\n  kernel.packet[8].x = a_p_8;\n  kernel.packet[9].x = a_p_9;\n  kernel.packet[10].x = a_p_a;\n  kernel.packet[11].x = a_p_b;\n  kernel.packet[12].x = a_p_c;\n  kernel.packet[13].x = a_p_d;\n  kernel.packet[14].x = a_p_e;\n  kernel.packet[15].x = a_p_f;\n}\n\nEIGEN_STRONG_INLINE void\nptranspose(PacketBlock<Packet16h,8>& kernel) {\n  EIGEN_ALIGN64 half in[8][16];\n  pstore<half>(in[0], kernel.packet[0]);\n  pstore<half>(in[1], kernel.packet[1]);\n  pstore<half>(in[2], kernel.packet[2]);\n  pstore<half>(in[3], kernel.packet[3]);\n  pstore<half>(in[4], kernel.packet[4]);\n  pstore<half>(in[5], kernel.packet[5]);\n  pstore<half>(in[6], kernel.packet[6]);\n  pstore<half>(in[7], kernel.packet[7]);\n\n  EIGEN_ALIGN64 half out[8][16];\n\n  for (int i = 0; i < 8; ++i) {\n    for (int j = 0; j < 8; ++j) {\n      out[i][j] = in[j][2*i];\n    }\n    for (int j = 0; j < 8; ++j) {\n      out[i][j+8] = in[j][2*i+1];\n    }\n  }\n\n  kernel.packet[0] = pload<Packet16h>(out[0]);\n  kernel.packet[1] = pload<Packet16h>(out[1]);\n  kernel.packet[2] = pload<Packet16h>(out[2]);\n  kernel.packet[3] = pload<Packet16h>(out[3]);\n  kernel.packet[4] = pload<Packet16h>(out[4]);\n  kernel.packet[5] = pload<Packet16h>(out[5]);\n  kernel.packet[6] = pload<Packet16h>(out[6]);\n  kernel.packet[7] = pload<Packet16h>(out[7]);\n}\n\nEIGEN_STRONG_INLINE void\nptranspose(PacketBlock<Packet16h,4>& kernel) {\n  EIGEN_ALIGN64 half in[4][16];\n  pstore<half>(in[0], kernel.packet[0]);\n  pstore<half>(in[1], kernel.packet[1]);\n  pstore<half>(in[2], kernel.packet[2]);\n  pstore<half>(in[3], kernel.packet[3]);\n\n  EIGEN_ALIGN64 half out[4][16];\n\n  for (int i = 0; i < 4; ++i) {\n    for (int j = 0; j < 4; ++j) {\n      out[i][j] = in[j][4*i];\n    }\n    for (int j = 0; j < 4; ++j) {\n      out[i][j+4] = in[j][4*i+1];\n    }\n    for (int j = 0; j < 4; ++j) {\n      out[i][j+8] = in[j][4*i+2];\n    }\n    for (int j = 0; j < 4; ++j) {\n      out[i][j+12] = in[j][4*i+3];\n    }\n  }\n\n  kernel.packet[0] = pload<Packet16h>(out[0]);\n  kernel.packet[1] = pload<Packet16h>(out[1]);\n  kernel.packet[2] = pload<Packet16h>(out[2]);\n  kernel.packet[3] = pload<Packet16h>(out[3]);\n}\n\n\n#elif defined EIGEN_VECTORIZE_AVX\n\ntypedef struct {\n  __m128i x;\n} Packet8h;\n\n\ntemplate<> struct is_arithmetic<Packet8h> { enum { value = true }; };\n\ntemplate <>\nstruct packet_traits<Eigen::half> : default_packet_traits {\n  typedef Packet8h type;\n  // There is no half-size packet for Packet8h.\n  typedef Packet8h half;\n  enum {\n    Vectorizable = 1,\n    AlignedOnScalar = 1,\n    size = 8,\n    HasHalfPacket = 0,\n    HasAdd    = 0,\n    HasSub    = 0,\n    HasMul    = 0,\n    HasNegate = 0,\n    HasAbs    = 0,\n    HasAbs2   = 0,\n    HasMin    = 0,\n    HasMax    = 0,\n    HasConj   = 0,\n    HasSetLinear = 0,\n    HasDiv = 0,\n    HasSqrt = 0,\n    HasRsqrt = 0,\n    HasExp = 0,\n    HasLog = 0,\n    HasBlend = 0\n  };\n};\n\n\ntemplate<> struct unpacket_traits<Packet8h> { typedef Eigen::half type; enum {size=8, alignment=Aligned16}; typedef Packet8h half; };\n\ntemplate<> EIGEN_STRONG_INLINE Packet8h pset1<Packet8h>(const Eigen::half& from) {\n  Packet8h result;\n  result.x = _mm_set1_epi16(from.x);\n  return result;\n}\n\ntemplate<> EIGEN_STRONG_INLINE Eigen::half pfirst<Packet8h>(const Packet8h& from) {\n  return half_impl::raw_uint16_to_half(static_cast<unsigned short>(_mm_extract_epi16(from.x, 0)));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet8h pload<Packet8h>(const Eigen::half* from) {\n  Packet8h result;\n  result.x = _mm_load_si128(reinterpret_cast<const __m128i*>(from));\n  return result;\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet8h ploadu<Packet8h>(const Eigen::half* from) {\n  Packet8h result;\n  result.x = _mm_loadu_si128(reinterpret_cast<const __m128i*>(from));\n  return result;\n}\n\ntemplate<> EIGEN_STRONG_INLINE void pstore<Eigen::half>(Eigen::half* to, const Packet8h& from) {\n  _mm_store_si128(reinterpret_cast<__m128i*>(to), from.x);\n}\n\ntemplate<> EIGEN_STRONG_INLINE void pstoreu<Eigen::half>(Eigen::half* to, const Packet8h& from) {\n  _mm_storeu_si128(reinterpret_cast<__m128i*>(to), from.x);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet8h\nploadquad<Packet8h>(const Eigen::half* from) {\n  Packet8h result;\n  unsigned short a = from[0].x;\n  unsigned short b = from[1].x;\n  result.x = _mm_set_epi16(b, b, b, b, a, a, a, a);\n  return result;\n}\n\nEIGEN_STRONG_INLINE Packet8f half2float(const Packet8h& a) {\n#ifdef EIGEN_HAS_FP16_C\n  return _mm256_cvtph_ps(a.x);\n#else\n  EIGEN_ALIGN32 Eigen::half aux[8];\n  pstore(aux, a);\n  float f0(aux[0]);\n  float f1(aux[1]);\n  float f2(aux[2]);\n  float f3(aux[3]);\n  float f4(aux[4]);\n  float f5(aux[5]);\n  float f6(aux[6]);\n  float f7(aux[7]);\n\n  return _mm256_set_ps(f7, f6, f5, f4, f3, f2, f1, f0);\n#endif\n}\n\nEIGEN_STRONG_INLINE Packet8h float2half(const Packet8f& a) {\n#ifdef EIGEN_HAS_FP16_C\n  Packet8h result;\n  result.x = _mm256_cvtps_ph(a, _MM_FROUND_TO_NEAREST_INT|_MM_FROUND_NO_EXC);\n  return result;\n#else\n  EIGEN_ALIGN32 float aux[8];\n  pstore(aux, a);\n  Eigen::half h0(aux[0]);\n  Eigen::half h1(aux[1]);\n  Eigen::half h2(aux[2]);\n  Eigen::half h3(aux[3]);\n  Eigen::half h4(aux[4]);\n  Eigen::half h5(aux[5]);\n  Eigen::half h6(aux[6]);\n  Eigen::half h7(aux[7]);\n\n  Packet8h result;\n  result.x = _mm_set_epi16(h7.x, h6.x, h5.x, h4.x, h3.x, h2.x, h1.x, h0.x);\n  return result;\n#endif\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet8h pconj(const Packet8h& a) { return a; }\n\ntemplate<> EIGEN_STRONG_INLINE Packet8h padd<Packet8h>(const Packet8h& a, const Packet8h& b) {\n  Packet8f af = half2float(a);\n  Packet8f bf = half2float(b);\n  Packet8f rf = padd(af, bf);\n  return float2half(rf);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet8h pmul<Packet8h>(const Packet8h& a, const Packet8h& b) {\n  Packet8f af = half2float(a);\n  Packet8f bf = half2float(b);\n  Packet8f rf = pmul(af, bf);\n  return float2half(rf);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet8h pgather<Eigen::half, Packet8h>(const Eigen::half* from, Index stride)\n{\n  Packet8h result;\n  result.x = _mm_set_epi16(from[7*stride].x, from[6*stride].x, from[5*stride].x, from[4*stride].x, from[3*stride].x, from[2*stride].x, from[1*stride].x, from[0*stride].x);\n  return result;\n}\n\ntemplate<> EIGEN_STRONG_INLINE void pscatter<Eigen::half, Packet8h>(Eigen::half* to, const Packet8h& from, Index stride)\n{\n  EIGEN_ALIGN32 Eigen::half aux[8];\n  pstore(aux, from);\n  to[stride*0].x = aux[0].x;\n  to[stride*1].x = aux[1].x;\n  to[stride*2].x = aux[2].x;\n  to[stride*3].x = aux[3].x;\n  to[stride*4].x = aux[4].x;\n  to[stride*5].x = aux[5].x;\n  to[stride*6].x = aux[6].x;\n  to[stride*7].x = aux[7].x;\n}\n\ntemplate<> EIGEN_STRONG_INLINE Eigen::half predux<Packet8h>(const Packet8h& a) {\n  Packet8f af = half2float(a);\n  float reduced = predux<Packet8f>(af);\n  return Eigen::half(reduced);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Eigen::half predux_max<Packet8h>(const Packet8h& a) {\n  Packet8f af = half2float(a);\n  float reduced = predux_max<Packet8f>(af);\n  return Eigen::half(reduced);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Eigen::half predux_min<Packet8h>(const Packet8h& a) {\n  Packet8f af = half2float(a);\n  float reduced = predux_min<Packet8f>(af);\n  return Eigen::half(reduced);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Eigen::half predux_mul<Packet8h>(const Packet8h& a) {\n  Packet8f af = half2float(a);\n  float reduced = predux_mul<Packet8f>(af);\n  return Eigen::half(reduced);\n}\n\nEIGEN_STRONG_INLINE void\nptranspose(PacketBlock<Packet8h,8>& kernel) {\n  __m128i a = kernel.packet[0].x;\n  __m128i b = kernel.packet[1].x;\n  __m128i c = kernel.packet[2].x;\n  __m128i d = kernel.packet[3].x;\n  __m128i e = kernel.packet[4].x;\n  __m128i f = kernel.packet[5].x;\n  __m128i g = kernel.packet[6].x;\n  __m128i h = kernel.packet[7].x;\n\n  __m128i a03b03 = _mm_unpacklo_epi16(a, b);\n  __m128i c03d03 = _mm_unpacklo_epi16(c, d);\n  __m128i e03f03 = _mm_unpacklo_epi16(e, f);\n  __m128i g03h03 = _mm_unpacklo_epi16(g, h);\n  __m128i a47b47 = _mm_unpackhi_epi16(a, b);\n  __m128i c47d47 = _mm_unpackhi_epi16(c, d);\n  __m128i e47f47 = _mm_unpackhi_epi16(e, f);\n  __m128i g47h47 = _mm_unpackhi_epi16(g, h);\n\n  __m128i a01b01c01d01 = _mm_unpacklo_epi32(a03b03, c03d03);\n  __m128i a23b23c23d23 = _mm_unpackhi_epi32(a03b03, c03d03);\n  __m128i e01f01g01h01 = _mm_unpacklo_epi32(e03f03, g03h03);\n  __m128i e23f23g23h23 = _mm_unpackhi_epi32(e03f03, g03h03);\n  __m128i a45b45c45d45 = _mm_unpacklo_epi32(a47b47, c47d47);\n  __m128i a67b67c67d67 = _mm_unpackhi_epi32(a47b47, c47d47);\n  __m128i e45f45g45h45 = _mm_unpacklo_epi32(e47f47, g47h47);\n  __m128i e67f67g67h67 = _mm_unpackhi_epi32(e47f47, g47h47);\n\n  __m128i a0b0c0d0e0f0g0h0 = _mm_unpacklo_epi64(a01b01c01d01, e01f01g01h01);\n  __m128i a1b1c1d1e1f1g1h1 = _mm_unpackhi_epi64(a01b01c01d01, e01f01g01h01);\n  __m128i a2b2c2d2e2f2g2h2 = _mm_unpacklo_epi64(a23b23c23d23, e23f23g23h23);\n  __m128i a3b3c3d3e3f3g3h3 = _mm_unpackhi_epi64(a23b23c23d23, e23f23g23h23);\n  __m128i a4b4c4d4e4f4g4h4 = _mm_unpacklo_epi64(a45b45c45d45, e45f45g45h45);\n  __m128i a5b5c5d5e5f5g5h5 = _mm_unpackhi_epi64(a45b45c45d45, e45f45g45h45);\n  __m128i a6b6c6d6e6f6g6h6 = _mm_unpacklo_epi64(a67b67c67d67, e67f67g67h67);\n  __m128i a7b7c7d7e7f7g7h7 = _mm_unpackhi_epi64(a67b67c67d67, e67f67g67h67);\n\n  kernel.packet[0].x = a0b0c0d0e0f0g0h0;\n  kernel.packet[1].x = a1b1c1d1e1f1g1h1;\n  kernel.packet[2].x = a2b2c2d2e2f2g2h2;\n  kernel.packet[3].x = a3b3c3d3e3f3g3h3;\n  kernel.packet[4].x = a4b4c4d4e4f4g4h4;\n  kernel.packet[5].x = a5b5c5d5e5f5g5h5;\n  kernel.packet[6].x = a6b6c6d6e6f6g6h6;\n  kernel.packet[7].x = a7b7c7d7e7f7g7h7;\n}\n\nEIGEN_STRONG_INLINE void\nptranspose(PacketBlock<Packet8h,4>& kernel) {\n  EIGEN_ALIGN32 Eigen::half in[4][8];\n  pstore<Eigen::half>(in[0], kernel.packet[0]);\n  pstore<Eigen::half>(in[1], kernel.packet[1]);\n  pstore<Eigen::half>(in[2], kernel.packet[2]);\n  pstore<Eigen::half>(in[3], kernel.packet[3]);\n\n  EIGEN_ALIGN32 Eigen::half out[4][8];\n\n  for (int i = 0; i < 4; ++i) {\n    for (int j = 0; j < 4; ++j) {\n      out[i][j] = in[j][2*i];\n    }\n    for (int j = 0; j < 4; ++j) {\n      out[i][j+4] = in[j][2*i+1];\n    }\n  }\n\n  kernel.packet[0] = pload<Packet8h>(out[0]);\n  kernel.packet[1] = pload<Packet8h>(out[1]);\n  kernel.packet[2] = pload<Packet8h>(out[2]);\n  kernel.packet[3] = pload<Packet8h>(out[3]);\n}\n\n\n// Disable the following code since it's broken on too many platforms / compilers.\n//#elif defined(EIGEN_VECTORIZE_SSE) && (!EIGEN_ARCH_x86_64) && (!EIGEN_COMP_MSVC)\n#elif 0\n\ntypedef struct {\n  __m64 x;\n} Packet4h;\n\n\ntemplate<> struct is_arithmetic<Packet4h> { enum { value = true }; };\n\ntemplate <>\nstruct packet_traits<Eigen::half> : default_packet_traits {\n  typedef Packet4h type;\n  // There is no half-size packet for Packet4h.\n  typedef Packet4h half;\n  enum {\n    Vectorizable = 1,\n    AlignedOnScalar = 1,\n    size = 4,\n    HasHalfPacket = 0,\n    HasAdd    = 0,\n    HasSub    = 0,\n    HasMul    = 0,\n    HasNegate = 0,\n    HasAbs    = 0,\n    HasAbs2   = 0,\n    HasMin    = 0,\n    HasMax    = 0,\n    HasConj   = 0,\n    HasSetLinear = 0,\n    HasDiv = 0,\n    HasSqrt = 0,\n    HasRsqrt = 0,\n    HasExp = 0,\n    HasLog = 0,\n    HasBlend = 0\n  };\n};\n\n\ntemplate<> struct unpacket_traits<Packet4h> { typedef Eigen::half type; enum {size=4, alignment=Aligned16}; typedef Packet4h half; };\n\ntemplate<> EIGEN_STRONG_INLINE Packet4h pset1<Packet4h>(const Eigen::half& from) {\n  Packet4h result;\n  result.x = _mm_set1_pi16(from.x);\n  return result;\n}\n\ntemplate<> EIGEN_STRONG_INLINE Eigen::half pfirst<Packet4h>(const Packet4h& from) {\n  return half_impl::raw_uint16_to_half(static_cast<unsigned short>(_mm_cvtsi64_si32(from.x)));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4h pconj(const Packet4h& a) { return a; }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4h padd<Packet4h>(const Packet4h& a, const Packet4h& b) {\n  __int64_t a64 = _mm_cvtm64_si64(a.x);\n  __int64_t b64 = _mm_cvtm64_si64(b.x);\n\n  Eigen::half h[4];\n\n  Eigen::half ha = half_impl::raw_uint16_to_half(static_cast<unsigned short>(a64));\n  Eigen::half hb = half_impl::raw_uint16_to_half(static_cast<unsigned short>(b64));\n  h[0] = ha + hb;\n  ha = half_impl::raw_uint16_to_half(static_cast<unsigned short>(a64 >> 16));\n  hb = half_impl::raw_uint16_to_half(static_cast<unsigned short>(b64 >> 16));\n  h[1] = ha + hb;\n  ha = half_impl::raw_uint16_to_half(static_cast<unsigned short>(a64 >> 32));\n  hb = half_impl::raw_uint16_to_half(static_cast<unsigned short>(b64 >> 32));\n  h[2] = ha + hb;\n  ha = half_impl::raw_uint16_to_half(static_cast<unsigned short>(a64 >> 48));\n  hb = half_impl::raw_uint16_to_half(static_cast<unsigned short>(b64 >> 48));\n  h[3] = ha + hb;\n  Packet4h result;\n  result.x = _mm_set_pi16(h[3].x, h[2].x, h[1].x, h[0].x);\n  return result;\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4h pmul<Packet4h>(const Packet4h& a, const Packet4h& b) {\n  __int64_t a64 = _mm_cvtm64_si64(a.x);\n  __int64_t b64 = _mm_cvtm64_si64(b.x);\n\n  Eigen::half h[4];\n\n  Eigen::half ha = half_impl::raw_uint16_to_half(static_cast<unsigned short>(a64));\n  Eigen::half hb = half_impl::raw_uint16_to_half(static_cast<unsigned short>(b64));\n  h[0] = ha * hb;\n  ha = half_impl::raw_uint16_to_half(static_cast<unsigned short>(a64 >> 16));\n  hb = half_impl::raw_uint16_to_half(static_cast<unsigned short>(b64 >> 16));\n  h[1] = ha * hb;\n  ha = half_impl::raw_uint16_to_half(static_cast<unsigned short>(a64 >> 32));\n  hb = half_impl::raw_uint16_to_half(static_cast<unsigned short>(b64 >> 32));\n  h[2] = ha * hb;\n  ha = half_impl::raw_uint16_to_half(static_cast<unsigned short>(a64 >> 48));\n  hb = half_impl::raw_uint16_to_half(static_cast<unsigned short>(b64 >> 48));\n  h[3] = ha * hb;\n  Packet4h result;\n  result.x = _mm_set_pi16(h[3].x, h[2].x, h[1].x, h[0].x);\n  return result;\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4h pload<Packet4h>(const Eigen::half* from) {\n  Packet4h result;\n  result.x = _mm_cvtsi64_m64(*reinterpret_cast<const __int64_t*>(from));\n  return result;\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4h ploadu<Packet4h>(const Eigen::half* from) {\n  Packet4h result;\n  result.x = _mm_cvtsi64_m64(*reinterpret_cast<const __int64_t*>(from));\n  return result;\n}\n\ntemplate<> EIGEN_STRONG_INLINE void pstore<Eigen::half>(Eigen::half* to, const Packet4h& from) {\n  __int64_t r = _mm_cvtm64_si64(from.x);\n  *(reinterpret_cast<__int64_t*>(to)) = r;\n}\n\ntemplate<> EIGEN_STRONG_INLINE void pstoreu<Eigen::half>(Eigen::half* to, const Packet4h& from) {\n  __int64_t r = _mm_cvtm64_si64(from.x);\n  *(reinterpret_cast<__int64_t*>(to)) = r;\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4h\nploadquad<Packet4h>(const Eigen::half* from) {\n  return pset1<Packet4h>(*from);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4h pgather<Eigen::half, Packet4h>(const Eigen::half* from, Index stride)\n{\n  Packet4h result;\n  result.x = _mm_set_pi16(from[3*stride].x, from[2*stride].x, from[1*stride].x, from[0*stride].x);\n  return result;\n}\n\ntemplate<> EIGEN_STRONG_INLINE void pscatter<Eigen::half, Packet4h>(Eigen::half* to, const Packet4h& from, Index stride)\n{\n  __int64_t a = _mm_cvtm64_si64(from.x);\n  to[stride*0].x = static_cast<unsigned short>(a);\n  to[stride*1].x = static_cast<unsigned short>(a >> 16);\n  to[stride*2].x = static_cast<unsigned short>(a >> 32);\n  to[stride*3].x = static_cast<unsigned short>(a >> 48);\n}\n\nEIGEN_STRONG_INLINE void\nptranspose(PacketBlock<Packet4h,4>& kernel) {\n  __m64 T0 = _mm_unpacklo_pi16(kernel.packet[0].x, kernel.packet[1].x);\n  __m64 T1 = _mm_unpacklo_pi16(kernel.packet[2].x, kernel.packet[3].x);\n  __m64 T2 = _mm_unpackhi_pi16(kernel.packet[0].x, kernel.packet[1].x);\n  __m64 T3 = _mm_unpackhi_pi16(kernel.packet[2].x, kernel.packet[3].x);\n\n  kernel.packet[0].x = _mm_unpacklo_pi32(T0, T1);\n  kernel.packet[1].x = _mm_unpackhi_pi32(T0, T1);\n  kernel.packet[2].x = _mm_unpacklo_pi32(T2, T3);\n  kernel.packet[3].x = _mm_unpackhi_pi32(T2, T3);\n}\n\n#endif\n\n}\n}\n\n#endif // EIGEN_PACKET_MATH_HALF_CUDA_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/arch/CUDA/TypeCasting.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2016 Benoit Steiner <benoit.steiner.goog@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_TYPE_CASTING_CUDA_H\n#define EIGEN_TYPE_CASTING_CUDA_H\n\nnamespace Eigen {\n\nnamespace internal {\n\ntemplate<>\nstruct scalar_cast_op<float, Eigen::half> {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_cast_op)\n  typedef Eigen::half result_type;\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE Eigen::half operator() (const float& a) const {\n    #if defined(EIGEN_HAS_CUDA_FP16) && defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 300\n      return __float2half(a);\n    #else\n      return Eigen::half(a);\n    #endif\n  }\n};\n\ntemplate<>\nstruct functor_traits<scalar_cast_op<float, Eigen::half> >\n{ enum { Cost = NumTraits<float>::AddCost, PacketAccess = false }; };\n\n\ntemplate<>\nstruct scalar_cast_op<int, Eigen::half> {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_cast_op)\n  typedef Eigen::half result_type;\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE Eigen::half operator() (const int& a) const {\n    #if defined(EIGEN_HAS_CUDA_FP16) && defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 300\n      return __float2half(static_cast<float>(a));\n    #else\n      return Eigen::half(static_cast<float>(a));\n    #endif\n  }\n};\n\ntemplate<>\nstruct functor_traits<scalar_cast_op<int, Eigen::half> >\n{ enum { Cost = NumTraits<float>::AddCost, PacketAccess = false }; };\n\n\ntemplate<>\nstruct scalar_cast_op<Eigen::half, float> {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_cast_op)\n  typedef float result_type;\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE float operator() (const Eigen::half& a) const {\n    #if defined(EIGEN_HAS_CUDA_FP16) && defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 300\n      return __half2float(a);\n    #else\n      return static_cast<float>(a);\n    #endif\n  }\n};\n\ntemplate<>\nstruct functor_traits<scalar_cast_op<Eigen::half, float> >\n{ enum { Cost = NumTraits<float>::AddCost, PacketAccess = false }; };\n\n\n\n#if defined(EIGEN_HAS_CUDA_FP16) && defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 300\n\ntemplate <>\nstruct type_casting_traits<Eigen::half, float> {\n  enum {\n    VectorizedCast = 1,\n    SrcCoeffRatio = 2,\n    TgtCoeffRatio = 1\n  };\n};\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE float4 pcast<half2, float4>(const half2& a, const half2& b) {\n  float2 r1 = __half22float2(a);\n  float2 r2 = __half22float2(b);\n  return make_float4(r1.x, r1.y, r2.x, r2.y);\n}\n\ntemplate <>\nstruct type_casting_traits<float, Eigen::half> {\n  enum {\n    VectorizedCast = 1,\n    SrcCoeffRatio = 1,\n    TgtCoeffRatio = 2\n  };\n};\n\ntemplate<> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE half2 pcast<float4, half2>(const float4& a) {\n  // Simply discard the second half of the input\n  return __floats2half2_rn(a.x, a.y);\n}\n\n#elif defined EIGEN_VECTORIZE_AVX512\ntemplate <>\nstruct type_casting_traits<half, float> {\n  enum {\n    VectorizedCast = 1,\n    SrcCoeffRatio = 1,\n    TgtCoeffRatio = 1\n  };\n};\n\ntemplate<> EIGEN_STRONG_INLINE Packet16f pcast<Packet16h, Packet16f>(const Packet16h& a) {\n  return half2float(a);\n}\n\ntemplate <>\nstruct type_casting_traits<float, half> {\n  enum {\n    VectorizedCast = 1,\n    SrcCoeffRatio = 1,\n    TgtCoeffRatio = 1\n  };\n};\n\ntemplate<> EIGEN_STRONG_INLINE Packet16h pcast<Packet16f, Packet16h>(const Packet16f& a) {\n  return float2half(a);\n}\n\n#elif defined EIGEN_VECTORIZE_AVX\n\ntemplate <>\nstruct type_casting_traits<Eigen::half, float> {\n  enum {\n    VectorizedCast = 1,\n    SrcCoeffRatio = 1,\n    TgtCoeffRatio = 1\n  };\n};\n\ntemplate<> EIGEN_STRONG_INLINE Packet8f pcast<Packet8h, Packet8f>(const Packet8h& a) {\n  return half2float(a);\n}\n\ntemplate <>\nstruct type_casting_traits<float, Eigen::half> {\n  enum {\n    VectorizedCast = 1,\n    SrcCoeffRatio = 1,\n    TgtCoeffRatio = 1\n  };\n};\n\ntemplate<> EIGEN_STRONG_INLINE Packet8h pcast<Packet8f, Packet8h>(const Packet8f& a) {\n  return float2half(a);\n}\n\n// Disable the following code since it's broken on too many platforms / compilers.\n//#elif defined(EIGEN_VECTORIZE_SSE) && (!EIGEN_ARCH_x86_64) && (!EIGEN_COMP_MSVC)\n#elif 0\n\ntemplate <>\nstruct type_casting_traits<Eigen::half, float> {\n  enum {\n    VectorizedCast = 1,\n    SrcCoeffRatio = 1,\n    TgtCoeffRatio = 1\n  };\n};\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pcast<Packet4h, Packet4f>(const Packet4h& a) {\n  __int64_t a64 = _mm_cvtm64_si64(a.x);\n  Eigen::half h = raw_uint16_to_half(static_cast<unsigned short>(a64));\n  float f1 = static_cast<float>(h);\n  h = raw_uint16_to_half(static_cast<unsigned short>(a64 >> 16));\n  float f2 = static_cast<float>(h);\n  h = raw_uint16_to_half(static_cast<unsigned short>(a64 >> 32));\n  float f3 = static_cast<float>(h);\n  h = raw_uint16_to_half(static_cast<unsigned short>(a64 >> 48));\n  float f4 = static_cast<float>(h);\n  return _mm_set_ps(f4, f3, f2, f1);\n}\n\ntemplate <>\nstruct type_casting_traits<float, Eigen::half> {\n  enum {\n    VectorizedCast = 1,\n    SrcCoeffRatio = 1,\n    TgtCoeffRatio = 1\n  };\n};\n\ntemplate<> EIGEN_STRONG_INLINE Packet4h pcast<Packet4f, Packet4h>(const Packet4f& a) {\n  EIGEN_ALIGN16 float aux[4];\n  pstore(aux, a);\n  Eigen::half h0(aux[0]);\n  Eigen::half h1(aux[1]);\n  Eigen::half h2(aux[2]);\n  Eigen::half h3(aux[3]);\n\n  Packet4h result;\n  result.x = _mm_set_pi16(h3.x, h2.x, h1.x, h0.x);\n  return result;\n}\n\n#endif\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_TYPE_CASTING_CUDA_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/arch/Default/Settings.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2006-2008 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n\n/* All the parameters defined in this file can be specialized in the\n * architecture specific files, and/or by the user.\n * More to come... */\n\n#ifndef EIGEN_DEFAULT_SETTINGS_H\n#define EIGEN_DEFAULT_SETTINGS_H\n\n/** Defines the maximal loop size to enable meta unrolling of loops.\n  * Note that the value here is expressed in Eigen's own notion of \"number of FLOPS\",\n  * it does not correspond to the number of iterations or the number of instructions\n  */\n#ifndef EIGEN_UNROLLING_LIMIT\n#define EIGEN_UNROLLING_LIMIT 100\n#endif\n\n/** Defines the threshold between a \"small\" and a \"large\" matrix.\n  * This threshold is mainly used to select the proper product implementation.\n  */\n#ifndef EIGEN_CACHEFRIENDLY_PRODUCT_THRESHOLD\n#define EIGEN_CACHEFRIENDLY_PRODUCT_THRESHOLD 8\n#endif\n\n/** Defines the maximal width of the blocks used in the triangular product and solver\n  * for vectors (level 2 blas xTRMV and xTRSV). The default is 8.\n  */\n#ifndef EIGEN_TUNE_TRIANGULAR_PANEL_WIDTH\n#define EIGEN_TUNE_TRIANGULAR_PANEL_WIDTH 8\n#endif\n\n\n/** Defines the default number of registers available for that architecture.\n  * Currently it must be 8 or 16. Other values will fail.\n  */\n#ifndef EIGEN_ARCH_DEFAULT_NUMBER_OF_REGISTERS\n#define EIGEN_ARCH_DEFAULT_NUMBER_OF_REGISTERS 8\n#endif\n\n#endif // EIGEN_DEFAULT_SETTINGS_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/arch/NEON/Complex.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2010 Konstantinos Margaritis <markos@freevec.org>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_COMPLEX_NEON_H\n#define EIGEN_COMPLEX_NEON_H\n\nnamespace Eigen {\n\nnamespace internal {\n\ninline uint32x4_t p4ui_CONJ_XOR() {\n// See bug 1325, clang fails to call vld1q_u64.\n#if EIGEN_COMP_CLANG\n  uint32x4_t ret = { 0x00000000, 0x80000000, 0x00000000, 0x80000000 };\n  return ret;\n#else\n  static const uint32_t conj_XOR_DATA[] = { 0x00000000, 0x80000000, 0x00000000, 0x80000000 };\n  return vld1q_u32( conj_XOR_DATA );\n#endif\n}\n\ninline uint32x2_t p2ui_CONJ_XOR() {\n  static const uint32_t conj_XOR_DATA[] = { 0x00000000, 0x80000000 };\n  return vld1_u32( conj_XOR_DATA );\n}\n\n//---------- float ----------\nstruct Packet2cf\n{\n  EIGEN_STRONG_INLINE Packet2cf() {}\n  EIGEN_STRONG_INLINE explicit Packet2cf(const Packet4f& a) : v(a) {}\n  Packet4f  v;\n};\n\ntemplate<> struct packet_traits<std::complex<float> >  : default_packet_traits\n{\n  typedef Packet2cf type;\n  typedef Packet2cf half;\n  enum {\n    Vectorizable = 1,\n    AlignedOnScalar = 1,\n    size = 2,\n    HasHalfPacket = 0,\n\n    HasAdd    = 1,\n    HasSub    = 1,\n    HasMul    = 1,\n    HasDiv    = 1,\n    HasNegate = 1,\n    HasAbs    = 0,\n    HasAbs2   = 0,\n    HasMin    = 0,\n    HasMax    = 0,\n    HasSetLinear = 0\n  };\n};\n\ntemplate<> struct unpacket_traits<Packet2cf> { typedef std::complex<float> type; enum {size=2, alignment=Aligned16}; typedef Packet2cf half; };\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pset1<Packet2cf>(const std::complex<float>&  from)\n{\n  float32x2_t r64;\n  r64 = vld1_f32((float *)&from);\n\n  return Packet2cf(vcombine_f32(r64, r64));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cf padd<Packet2cf>(const Packet2cf& a, const Packet2cf& b) { return Packet2cf(padd<Packet4f>(a.v,b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet2cf psub<Packet2cf>(const Packet2cf& a, const Packet2cf& b) { return Packet2cf(psub<Packet4f>(a.v,b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pnegate(const Packet2cf& a) { return Packet2cf(pnegate<Packet4f>(a.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pconj(const Packet2cf& a)\n{\n  Packet4ui b = vreinterpretq_u32_f32(a.v);\n  return Packet2cf(vreinterpretq_f32_u32(veorq_u32(b, p4ui_CONJ_XOR())));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pmul<Packet2cf>(const Packet2cf& a, const Packet2cf& b)\n{\n  Packet4f v1, v2;\n\n  // Get the real values of a | a1_re | a1_re | a2_re | a2_re |\n  v1 = vcombine_f32(vdup_lane_f32(vget_low_f32(a.v), 0), vdup_lane_f32(vget_high_f32(a.v), 0));\n  // Get the imag values of a | a1_im | a1_im | a2_im | a2_im |\n  v2 = vcombine_f32(vdup_lane_f32(vget_low_f32(a.v), 1), vdup_lane_f32(vget_high_f32(a.v), 1));\n  // Multiply the real a with b\n  v1 = vmulq_f32(v1, b.v);\n  // Multiply the imag a with b\n  v2 = vmulq_f32(v2, b.v);\n  // Conjugate v2 \n  v2 = vreinterpretq_f32_u32(veorq_u32(vreinterpretq_u32_f32(v2), p4ui_CONJ_XOR()));\n  // Swap real/imag elements in v2.\n  v2 = vrev64q_f32(v2);\n  // Add and return the result\n  return Packet2cf(vaddq_f32(v1, v2));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pand   <Packet2cf>(const Packet2cf& a, const Packet2cf& b)\n{\n  return Packet2cf(vreinterpretq_f32_u32(vandq_u32(vreinterpretq_u32_f32(a.v),vreinterpretq_u32_f32(b.v))));\n}\ntemplate<> EIGEN_STRONG_INLINE Packet2cf por    <Packet2cf>(const Packet2cf& a, const Packet2cf& b)\n{\n  return Packet2cf(vreinterpretq_f32_u32(vorrq_u32(vreinterpretq_u32_f32(a.v),vreinterpretq_u32_f32(b.v))));\n}\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pxor   <Packet2cf>(const Packet2cf& a, const Packet2cf& b)\n{\n  return Packet2cf(vreinterpretq_f32_u32(veorq_u32(vreinterpretq_u32_f32(a.v),vreinterpretq_u32_f32(b.v))));\n}\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pandnot<Packet2cf>(const Packet2cf& a, const Packet2cf& b)\n{\n  return Packet2cf(vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(a.v),vreinterpretq_u32_f32(b.v))));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pload<Packet2cf>(const std::complex<float>* from) { EIGEN_DEBUG_ALIGNED_LOAD return Packet2cf(pload<Packet4f>((const float*)from)); }\ntemplate<> EIGEN_STRONG_INLINE Packet2cf ploadu<Packet2cf>(const std::complex<float>* from) { EIGEN_DEBUG_UNALIGNED_LOAD return Packet2cf(ploadu<Packet4f>((const float*)from)); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cf ploaddup<Packet2cf>(const std::complex<float>* from) { return pset1<Packet2cf>(*from); }\n\ntemplate<> EIGEN_STRONG_INLINE void pstore <std::complex<float> >(std::complex<float> *   to, const Packet2cf& from) { EIGEN_DEBUG_ALIGNED_STORE pstore((float*)to, from.v); }\ntemplate<> EIGEN_STRONG_INLINE void pstoreu<std::complex<float> >(std::complex<float> *   to, const Packet2cf& from) { EIGEN_DEBUG_UNALIGNED_STORE pstoreu((float*)to, from.v); }\n\ntemplate<> EIGEN_DEVICE_FUNC inline Packet2cf pgather<std::complex<float>, Packet2cf>(const std::complex<float>* from, Index stride)\n{\n  Packet4f res = pset1<Packet4f>(0.f);\n  res = vsetq_lane_f32(std::real(from[0*stride]), res, 0);\n  res = vsetq_lane_f32(std::imag(from[0*stride]), res, 1);\n  res = vsetq_lane_f32(std::real(from[1*stride]), res, 2);\n  res = vsetq_lane_f32(std::imag(from[1*stride]), res, 3);\n  return Packet2cf(res);\n}\n\ntemplate<> EIGEN_DEVICE_FUNC inline void pscatter<std::complex<float>, Packet2cf>(std::complex<float>* to, const Packet2cf& from, Index stride)\n{\n  to[stride*0] = std::complex<float>(vgetq_lane_f32(from.v, 0), vgetq_lane_f32(from.v, 1));\n  to[stride*1] = std::complex<float>(vgetq_lane_f32(from.v, 2), vgetq_lane_f32(from.v, 3));\n}\n\ntemplate<> EIGEN_STRONG_INLINE void prefetch<std::complex<float> >(const std::complex<float> *   addr) { EIGEN_ARM_PREFETCH((float *)addr); }\n\ntemplate<> EIGEN_STRONG_INLINE std::complex<float>  pfirst<Packet2cf>(const Packet2cf& a)\n{\n  std::complex<float> EIGEN_ALIGN16 x[2];\n  vst1q_f32((float *)x, a.v);\n  return x[0];\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cf preverse(const Packet2cf& a)\n{\n  float32x2_t a_lo, a_hi;\n  Packet4f a_r128;\n\n  a_lo = vget_low_f32(a.v);\n  a_hi = vget_high_f32(a.v);\n  a_r128 = vcombine_f32(a_hi, a_lo);\n\n  return Packet2cf(a_r128);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pcplxflip<Packet2cf>(const Packet2cf& a)\n{\n  return Packet2cf(vrev64q_f32(a.v));\n}\n\ntemplate<> EIGEN_STRONG_INLINE std::complex<float> predux<Packet2cf>(const Packet2cf& a)\n{\n  float32x2_t a1, a2;\n  std::complex<float> s;\n\n  a1 = vget_low_f32(a.v);\n  a2 = vget_high_f32(a.v);\n  a2 = vadd_f32(a1, a2);\n  vst1_f32((float *)&s, a2);\n\n  return s;\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cf preduxp<Packet2cf>(const Packet2cf* vecs)\n{\n  Packet4f sum1, sum2, sum;\n\n  // Add the first two 64-bit float32x2_t of vecs[0]\n  sum1 = vcombine_f32(vget_low_f32(vecs[0].v), vget_low_f32(vecs[1].v));\n  sum2 = vcombine_f32(vget_high_f32(vecs[0].v), vget_high_f32(vecs[1].v));\n  sum = vaddq_f32(sum1, sum2);\n\n  return Packet2cf(sum);\n}\n\ntemplate<> EIGEN_STRONG_INLINE std::complex<float> predux_mul<Packet2cf>(const Packet2cf& a)\n{\n  float32x2_t a1, a2, v1, v2, prod;\n  std::complex<float> s;\n\n  a1 = vget_low_f32(a.v);\n  a2 = vget_high_f32(a.v);\n   // Get the real values of a | a1_re | a1_re | a2_re | a2_re |\n  v1 = vdup_lane_f32(a1, 0);\n  // Get the real values of a | a1_im | a1_im | a2_im | a2_im |\n  v2 = vdup_lane_f32(a1, 1);\n  // Multiply the real a with b\n  v1 = vmul_f32(v1, a2);\n  // Multiply the imag a with b\n  v2 = vmul_f32(v2, a2);\n  // Conjugate v2 \n  v2 = vreinterpret_f32_u32(veor_u32(vreinterpret_u32_f32(v2), p2ui_CONJ_XOR()));\n  // Swap real/imag elements in v2.\n  v2 = vrev64_f32(v2);\n  // Add v1, v2\n  prod = vadd_f32(v1, v2);\n\n  vst1_f32((float *)&s, prod);\n\n  return s;\n}\n\ntemplate<int Offset>\nstruct palign_impl<Offset,Packet2cf>\n{\n  EIGEN_STRONG_INLINE static void run(Packet2cf& first, const Packet2cf& second)\n  {\n    if (Offset==1)\n    {\n      first.v = vextq_f32(first.v, second.v, 2);\n    }\n  }\n};\n\ntemplate<> struct conj_helper<Packet2cf, Packet2cf, false,true>\n{\n  EIGEN_STRONG_INLINE Packet2cf pmadd(const Packet2cf& x, const Packet2cf& y, const Packet2cf& c) const\n  { return padd(pmul(x,y),c); }\n\n  EIGEN_STRONG_INLINE Packet2cf pmul(const Packet2cf& a, const Packet2cf& b) const\n  {\n    return internal::pmul(a, pconj(b));\n  }\n};\n\ntemplate<> struct conj_helper<Packet2cf, Packet2cf, true,false>\n{\n  EIGEN_STRONG_INLINE Packet2cf pmadd(const Packet2cf& x, const Packet2cf& y, const Packet2cf& c) const\n  { return padd(pmul(x,y),c); }\n\n  EIGEN_STRONG_INLINE Packet2cf pmul(const Packet2cf& a, const Packet2cf& b) const\n  {\n    return internal::pmul(pconj(a), b);\n  }\n};\n\ntemplate<> struct conj_helper<Packet2cf, Packet2cf, true,true>\n{\n  EIGEN_STRONG_INLINE Packet2cf pmadd(const Packet2cf& x, const Packet2cf& y, const Packet2cf& c) const\n  { return padd(pmul(x,y),c); }\n\n  EIGEN_STRONG_INLINE Packet2cf pmul(const Packet2cf& a, const Packet2cf& b) const\n  {\n    return pconj(internal::pmul(a, b));\n  }\n};\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pdiv<Packet2cf>(const Packet2cf& a, const Packet2cf& b)\n{\n  // TODO optimize it for NEON\n  Packet2cf res = conj_helper<Packet2cf,Packet2cf,false,true>().pmul(a,b);\n  Packet4f s, rev_s;\n\n  // this computes the norm\n  s = vmulq_f32(b.v, b.v);\n  rev_s = vrev64q_f32(s);\n\n  return Packet2cf(pdiv(res.v, vaddq_f32(s,rev_s)));\n}\n\nEIGEN_DEVICE_FUNC inline void\nptranspose(PacketBlock<Packet2cf,2>& kernel) {\n  Packet4f tmp = vcombine_f32(vget_high_f32(kernel.packet[0].v), vget_high_f32(kernel.packet[1].v));\n  kernel.packet[0].v = vcombine_f32(vget_low_f32(kernel.packet[0].v), vget_low_f32(kernel.packet[1].v));\n  kernel.packet[1].v = tmp;\n}\n\n//---------- double ----------\n#if EIGEN_ARCH_ARM64 && !EIGEN_APPLE_DOUBLE_NEON_BUG\n\n// See bug 1325, clang fails to call vld1q_u64.\n#if EIGEN_COMP_CLANG\n  static uint64x2_t p2ul_CONJ_XOR = {0x0, 0x8000000000000000};\n#else\n  const uint64_t  p2ul_conj_XOR_DATA[] = { 0x0, 0x8000000000000000 };\n  static uint64x2_t p2ul_CONJ_XOR = vld1q_u64( p2ul_conj_XOR_DATA );\n#endif\n\nstruct Packet1cd\n{\n  EIGEN_STRONG_INLINE Packet1cd() {}\n  EIGEN_STRONG_INLINE explicit Packet1cd(const Packet2d& a) : v(a) {}\n  Packet2d v;\n};\n\ntemplate<> struct packet_traits<std::complex<double> >  : default_packet_traits\n{\n  typedef Packet1cd type;\n  typedef Packet1cd half;\n  enum {\n    Vectorizable = 1,\n    AlignedOnScalar = 0,\n    size = 1,\n    HasHalfPacket = 0,\n\n    HasAdd    = 1,\n    HasSub    = 1,\n    HasMul    = 1,\n    HasDiv    = 1,\n    HasNegate = 1,\n    HasAbs    = 0,\n    HasAbs2   = 0,\n    HasMin    = 0,\n    HasMax    = 0,\n    HasSetLinear = 0\n  };\n};\n\ntemplate<> struct unpacket_traits<Packet1cd> { typedef std::complex<double> type; enum {size=1, alignment=Aligned16}; typedef Packet1cd half; };\n\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pload<Packet1cd>(const std::complex<double>* from) { EIGEN_DEBUG_ALIGNED_LOAD return Packet1cd(pload<Packet2d>((const double*)from)); }\ntemplate<> EIGEN_STRONG_INLINE Packet1cd ploadu<Packet1cd>(const std::complex<double>* from) { EIGEN_DEBUG_UNALIGNED_LOAD return Packet1cd(ploadu<Packet2d>((const double*)from)); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pset1<Packet1cd>(const std::complex<double>&  from)\n{ /* here we really have to use unaligned loads :( */ return ploadu<Packet1cd>(&from); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet1cd padd<Packet1cd>(const Packet1cd& a, const Packet1cd& b) { return Packet1cd(padd<Packet2d>(a.v,b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet1cd psub<Packet1cd>(const Packet1cd& a, const Packet1cd& b) { return Packet1cd(psub<Packet2d>(a.v,b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pnegate(const Packet1cd& a) { return Packet1cd(pnegate<Packet2d>(a.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pconj(const Packet1cd& a) { return Packet1cd(vreinterpretq_f64_u64(veorq_u64(vreinterpretq_u64_f64(a.v), p2ul_CONJ_XOR))); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pmul<Packet1cd>(const Packet1cd& a, const Packet1cd& b)\n{\n  Packet2d v1, v2;\n\n  // Get the real values of a \n  v1 = vdupq_lane_f64(vget_low_f64(a.v), 0);\n  // Get the imag values of a\n  v2 = vdupq_lane_f64(vget_high_f64(a.v), 0);\n  // Multiply the real a with b\n  v1 = vmulq_f64(v1, b.v);\n  // Multiply the imag a with b\n  v2 = vmulq_f64(v2, b.v);\n  // Conjugate v2 \n  v2 = vreinterpretq_f64_u64(veorq_u64(vreinterpretq_u64_f64(v2), p2ul_CONJ_XOR));\n  // Swap real/imag elements in v2.\n  v2 = preverse<Packet2d>(v2);\n  // Add and return the result\n  return Packet1cd(vaddq_f64(v1, v2));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pand   <Packet1cd>(const Packet1cd& a, const Packet1cd& b)\n{\n  return Packet1cd(vreinterpretq_f64_u64(vandq_u64(vreinterpretq_u64_f64(a.v),vreinterpretq_u64_f64(b.v))));\n}\ntemplate<> EIGEN_STRONG_INLINE Packet1cd por    <Packet1cd>(const Packet1cd& a, const Packet1cd& b)\n{\n  return Packet1cd(vreinterpretq_f64_u64(vorrq_u64(vreinterpretq_u64_f64(a.v),vreinterpretq_u64_f64(b.v))));\n}\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pxor   <Packet1cd>(const Packet1cd& a, const Packet1cd& b)\n{\n  return Packet1cd(vreinterpretq_f64_u64(veorq_u64(vreinterpretq_u64_f64(a.v),vreinterpretq_u64_f64(b.v))));\n}\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pandnot<Packet1cd>(const Packet1cd& a, const Packet1cd& b)\n{\n  return Packet1cd(vreinterpretq_f64_u64(vbicq_u64(vreinterpretq_u64_f64(a.v),vreinterpretq_u64_f64(b.v))));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet1cd ploaddup<Packet1cd>(const std::complex<double>* from) { return pset1<Packet1cd>(*from); }\n\ntemplate<> EIGEN_STRONG_INLINE void pstore <std::complex<double> >(std::complex<double> *   to, const Packet1cd& from) { EIGEN_DEBUG_ALIGNED_STORE pstore((double*)to, from.v); }\ntemplate<> EIGEN_STRONG_INLINE void pstoreu<std::complex<double> >(std::complex<double> *   to, const Packet1cd& from) { EIGEN_DEBUG_UNALIGNED_STORE pstoreu((double*)to, from.v); }\n\ntemplate<> EIGEN_STRONG_INLINE void prefetch<std::complex<double> >(const std::complex<double> *   addr) { EIGEN_ARM_PREFETCH((double *)addr); }\n\ntemplate<> EIGEN_DEVICE_FUNC inline Packet1cd pgather<std::complex<double>, Packet1cd>(const std::complex<double>* from, Index stride)\n{\n  Packet2d res = pset1<Packet2d>(0.0);\n  res = vsetq_lane_f64(std::real(from[0*stride]), res, 0);\n  res = vsetq_lane_f64(std::imag(from[0*stride]), res, 1);\n  return Packet1cd(res);\n}\n\ntemplate<> EIGEN_DEVICE_FUNC inline void pscatter<std::complex<double>, Packet1cd>(std::complex<double>* to, const Packet1cd& from, Index stride)\n{\n  to[stride*0] = std::complex<double>(vgetq_lane_f64(from.v, 0), vgetq_lane_f64(from.v, 1));\n}\n\n\ntemplate<> EIGEN_STRONG_INLINE std::complex<double>  pfirst<Packet1cd>(const Packet1cd& a)\n{\n  std::complex<double> EIGEN_ALIGN16 res;\n  pstore<std::complex<double> >(&res, a);\n\n  return res;\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet1cd preverse(const Packet1cd& a) { return a; }\n\ntemplate<> EIGEN_STRONG_INLINE std::complex<double> predux<Packet1cd>(const Packet1cd& a) { return pfirst(a); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet1cd preduxp<Packet1cd>(const Packet1cd* vecs) { return vecs[0]; }\n\ntemplate<> EIGEN_STRONG_INLINE std::complex<double> predux_mul<Packet1cd>(const Packet1cd& a) { return pfirst(a); }\n\ntemplate<int Offset>\nstruct palign_impl<Offset,Packet1cd>\n{\n  static EIGEN_STRONG_INLINE void run(Packet1cd& /*first*/, const Packet1cd& /*second*/)\n  {\n    // FIXME is it sure we never have to align a Packet1cd?\n    // Even though a std::complex<double> has 16 bytes, it is not necessarily aligned on a 16 bytes boundary...\n  }\n};\n\ntemplate<> struct conj_helper<Packet1cd, Packet1cd, false,true>\n{\n  EIGEN_STRONG_INLINE Packet1cd pmadd(const Packet1cd& x, const Packet1cd& y, const Packet1cd& c) const\n  { return padd(pmul(x,y),c); }\n\n  EIGEN_STRONG_INLINE Packet1cd pmul(const Packet1cd& a, const Packet1cd& b) const\n  {\n    return internal::pmul(a, pconj(b));\n  }\n};\n\ntemplate<> struct conj_helper<Packet1cd, Packet1cd, true,false>\n{\n  EIGEN_STRONG_INLINE Packet1cd pmadd(const Packet1cd& x, const Packet1cd& y, const Packet1cd& c) const\n  { return padd(pmul(x,y),c); }\n\n  EIGEN_STRONG_INLINE Packet1cd pmul(const Packet1cd& a, const Packet1cd& b) const\n  {\n    return internal::pmul(pconj(a), b);\n  }\n};\n\ntemplate<> struct conj_helper<Packet1cd, Packet1cd, true,true>\n{\n  EIGEN_STRONG_INLINE Packet1cd pmadd(const Packet1cd& x, const Packet1cd& y, const Packet1cd& c) const\n  { return padd(pmul(x,y),c); }\n\n  EIGEN_STRONG_INLINE Packet1cd pmul(const Packet1cd& a, const Packet1cd& b) const\n  {\n    return pconj(internal::pmul(a, b));\n  }\n};\n\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pdiv<Packet1cd>(const Packet1cd& a, const Packet1cd& b)\n{\n  // TODO optimize it for NEON\n  Packet1cd res = conj_helper<Packet1cd,Packet1cd,false,true>().pmul(a,b);\n  Packet2d s = pmul<Packet2d>(b.v, b.v);\n  Packet2d rev_s = preverse<Packet2d>(s);\n\n  return Packet1cd(pdiv(res.v, padd<Packet2d>(s,rev_s)));\n}\n\nEIGEN_STRONG_INLINE Packet1cd pcplxflip/*<Packet1cd>*/(const Packet1cd& x)\n{\n  return Packet1cd(preverse(Packet2d(x.v)));\n}\n\nEIGEN_STRONG_INLINE void ptranspose(PacketBlock<Packet1cd,2>& kernel)\n{\n  Packet2d tmp = vcombine_f64(vget_high_f64(kernel.packet[0].v), vget_high_f64(kernel.packet[1].v));\n  kernel.packet[0].v = vcombine_f64(vget_low_f64(kernel.packet[0].v), vget_low_f64(kernel.packet[1].v));\n  kernel.packet[1].v = tmp;\n}\n#endif // EIGEN_ARCH_ARM64\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_COMPLEX_NEON_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/arch/NEON/MathFunctions.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n/* The sin, cos, exp, and log functions of this file come from\n * Julien Pommier's sse math library: http://gruntthepeon.free.fr/ssemath/\n */\n\n#ifndef EIGEN_MATH_FUNCTIONS_NEON_H\n#define EIGEN_MATH_FUNCTIONS_NEON_H\n\nnamespace Eigen {\n\nnamespace internal {\n\ntemplate<> EIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED\nPacket4f pexp<Packet4f>(const Packet4f& _x)\n{\n  Packet4f x = _x;\n  Packet4f tmp, fx;\n\n  _EIGEN_DECLARE_CONST_Packet4f(1 , 1.0f);\n  _EIGEN_DECLARE_CONST_Packet4f(half, 0.5f);\n  _EIGEN_DECLARE_CONST_Packet4i(0x7f, 0x7f);\n  _EIGEN_DECLARE_CONST_Packet4f(exp_hi,  88.3762626647950f);\n  _EIGEN_DECLARE_CONST_Packet4f(exp_lo, -88.3762626647949f);\n  _EIGEN_DECLARE_CONST_Packet4f(cephes_LOG2EF, 1.44269504088896341f);\n  _EIGEN_DECLARE_CONST_Packet4f(cephes_exp_C1, 0.693359375f);\n  _EIGEN_DECLARE_CONST_Packet4f(cephes_exp_C2, -2.12194440e-4f);\n  _EIGEN_DECLARE_CONST_Packet4f(cephes_exp_p0, 1.9875691500E-4f);\n  _EIGEN_DECLARE_CONST_Packet4f(cephes_exp_p1, 1.3981999507E-3f);\n  _EIGEN_DECLARE_CONST_Packet4f(cephes_exp_p2, 8.3334519073E-3f);\n  _EIGEN_DECLARE_CONST_Packet4f(cephes_exp_p3, 4.1665795894E-2f);\n  _EIGEN_DECLARE_CONST_Packet4f(cephes_exp_p4, 1.6666665459E-1f);\n  _EIGEN_DECLARE_CONST_Packet4f(cephes_exp_p5, 5.0000001201E-1f);\n\n  x = vminq_f32(x, p4f_exp_hi);\n  x = vmaxq_f32(x, p4f_exp_lo);\n\n  /* express exp(x) as exp(g + n*log(2)) */\n  fx = vmlaq_f32(p4f_half, x, p4f_cephes_LOG2EF);\n\n  /* perform a floorf */\n  tmp = vcvtq_f32_s32(vcvtq_s32_f32(fx));\n\n  /* if greater, substract 1 */\n  Packet4ui mask = vcgtq_f32(tmp, fx);\n  mask = vandq_u32(mask, vreinterpretq_u32_f32(p4f_1));\n\n  fx = vsubq_f32(tmp, vreinterpretq_f32_u32(mask));\n\n  tmp = vmulq_f32(fx, p4f_cephes_exp_C1);\n  Packet4f z = vmulq_f32(fx, p4f_cephes_exp_C2);\n  x = vsubq_f32(x, tmp);\n  x = vsubq_f32(x, z);\n\n  Packet4f y = vmulq_f32(p4f_cephes_exp_p0, x);\n  z = vmulq_f32(x, x);\n  y = vaddq_f32(y, p4f_cephes_exp_p1);\n  y = vmulq_f32(y, x);\n  y = vaddq_f32(y, p4f_cephes_exp_p2);\n  y = vmulq_f32(y, x);\n  y = vaddq_f32(y, p4f_cephes_exp_p3);\n  y = vmulq_f32(y, x);\n  y = vaddq_f32(y, p4f_cephes_exp_p4);\n  y = vmulq_f32(y, x);\n  y = vaddq_f32(y, p4f_cephes_exp_p5);\n\n  y = vmulq_f32(y, z);\n  y = vaddq_f32(y, x);\n  y = vaddq_f32(y, p4f_1);\n\n  /* build 2^n */\n  int32x4_t mm;\n  mm = vcvtq_s32_f32(fx);\n  mm = vaddq_s32(mm, p4i_0x7f);\n  mm = vshlq_n_s32(mm, 23);\n  Packet4f pow2n = vreinterpretq_f32_s32(mm);\n\n  y = vmulq_f32(y, pow2n);\n  return y;\n}\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_MATH_FUNCTIONS_NEON_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/arch/NEON/PacketMath.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2010 Konstantinos Margaritis <markos@freevec.org>\n// Heavily based on Gael's SSE version.\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_PACKET_MATH_NEON_H\n#define EIGEN_PACKET_MATH_NEON_H\n\nnamespace Eigen {\n\nnamespace internal {\n\n#ifndef EIGEN_CACHEFRIENDLY_PRODUCT_THRESHOLD\n#define EIGEN_CACHEFRIENDLY_PRODUCT_THRESHOLD 8\n#endif\n\n#ifndef EIGEN_HAS_SINGLE_INSTRUCTION_MADD\n#define EIGEN_HAS_SINGLE_INSTRUCTION_MADD\n#endif\n\n#ifndef EIGEN_HAS_SINGLE_INSTRUCTION_CJMADD\n#define EIGEN_HAS_SINGLE_INSTRUCTION_CJMADD\n#endif\n\n// FIXME NEON has 16 quad registers, but since the current register allocator\n// is so bad, it is much better to reduce it to 8\n#ifndef EIGEN_ARCH_DEFAULT_NUMBER_OF_REGISTERS\n#define EIGEN_ARCH_DEFAULT_NUMBER_OF_REGISTERS 16 \n#endif\n\ntypedef float32x2_t Packet2f;\ntypedef float32x4_t Packet4f;\ntypedef int32x4_t   Packet4i;\ntypedef int32x2_t   Packet2i;\ntypedef uint32x4_t  Packet4ui;\n\n#define _EIGEN_DECLARE_CONST_Packet4f(NAME,X) \\\n  const Packet4f p4f_##NAME = pset1<Packet4f>(X)\n\n#define _EIGEN_DECLARE_CONST_Packet4f_FROM_INT(NAME,X) \\\n  const Packet4f p4f_##NAME = vreinterpretq_f32_u32(pset1<int>(X))\n\n#define _EIGEN_DECLARE_CONST_Packet4i(NAME,X) \\\n  const Packet4i p4i_##NAME = pset1<Packet4i>(X)\n\n// arm64 does have the pld instruction. If available, let's trust the __builtin_prefetch built-in function\n// which available on LLVM and GCC (at least)\n#if EIGEN_HAS_BUILTIN(__builtin_prefetch) || EIGEN_COMP_GNUC\n  #define EIGEN_ARM_PREFETCH(ADDR) __builtin_prefetch(ADDR);\n#elif defined __pld\n  #define EIGEN_ARM_PREFETCH(ADDR) __pld(ADDR)\n#elif !EIGEN_ARCH_ARM64\n  #define EIGEN_ARM_PREFETCH(ADDR) __asm__ __volatile__ ( \"   pld [%[addr]]\\n\" :: [addr] \"r\" (ADDR) : \"cc\" );\n#else\n  // by default no explicit prefetching\n  #define EIGEN_ARM_PREFETCH(ADDR)\n#endif\n\ntemplate<> struct packet_traits<float>  : default_packet_traits\n{\n  typedef Packet4f type;\n  typedef Packet4f half; // Packet2f intrinsics not implemented yet\n  enum {\n    Vectorizable = 1,\n    AlignedOnScalar = 1,\n    size = 4,\n    HasHalfPacket=0, // Packet2f intrinsics not implemented yet\n   \n    HasDiv  = 1,\n    // FIXME check the Has*\n    HasSin  = 0,\n    HasCos  = 0,\n    HasLog  = 0,\n    HasExp  = 1,\n    HasSqrt = 0\n  };\n};\ntemplate<> struct packet_traits<int>    : default_packet_traits\n{\n  typedef Packet4i type;\n  typedef Packet4i half; // Packet2i intrinsics not implemented yet\n  enum {\n    Vectorizable = 1,\n    AlignedOnScalar = 1,\n    size=4,\n    HasHalfPacket=0 // Packet2i intrinsics not implemented yet\n    // FIXME check the Has*\n  };\n};\n\n#if EIGEN_GNUC_AT_MOST(4,4) && !EIGEN_COMP_LLVM\n// workaround gcc 4.2, 4.3 and 4.4 compilatin issue\nEIGEN_STRONG_INLINE float32x4_t vld1q_f32(const float* x) { return ::vld1q_f32((const float32_t*)x); }\nEIGEN_STRONG_INLINE float32x2_t vld1_f32 (const float* x) { return ::vld1_f32 ((const float32_t*)x); }\nEIGEN_STRONG_INLINE float32x2_t vld1_dup_f32 (const float* x) { return ::vld1_dup_f32 ((const float32_t*)x); }\nEIGEN_STRONG_INLINE void        vst1q_f32(float* to, float32x4_t from) { ::vst1q_f32((float32_t*)to,from); }\nEIGEN_STRONG_INLINE void        vst1_f32 (float* to, float32x2_t from) { ::vst1_f32 ((float32_t*)to,from); }\n#endif\n\ntemplate<> struct unpacket_traits<Packet4f> { typedef float  type; enum {size=4, alignment=Aligned16}; typedef Packet4f half; };\ntemplate<> struct unpacket_traits<Packet4i> { typedef int    type; enum {size=4, alignment=Aligned16}; typedef Packet4i half; };\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pset1<Packet4f>(const float&  from) { return vdupq_n_f32(from); }\ntemplate<> EIGEN_STRONG_INLINE Packet4i pset1<Packet4i>(const int&    from)   { return vdupq_n_s32(from); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f plset<Packet4f>(const float& a)\n{\n  const float32_t f[] = {0, 1, 2, 3};\n  Packet4f countdown = vld1q_f32(f);\n  return vaddq_f32(pset1<Packet4f>(a), countdown);\n}\ntemplate<> EIGEN_STRONG_INLINE Packet4i plset<Packet4i>(const int& a)\n{\n  const int32_t i[] = {0, 1, 2, 3};\n  Packet4i countdown = vld1q_s32(i);\n  return vaddq_s32(pset1<Packet4i>(a), countdown);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f padd<Packet4f>(const Packet4f& a, const Packet4f& b) { return vaddq_f32(a,b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4i padd<Packet4i>(const Packet4i& a, const Packet4i& b) { return vaddq_s32(a,b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f psub<Packet4f>(const Packet4f& a, const Packet4f& b) { return vsubq_f32(a,b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4i psub<Packet4i>(const Packet4i& a, const Packet4i& b) { return vsubq_s32(a,b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pnegate(const Packet4f& a) { return vnegq_f32(a); }\ntemplate<> EIGEN_STRONG_INLINE Packet4i pnegate(const Packet4i& a) { return vnegq_s32(a); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pconj(const Packet4f& a) { return a; }\ntemplate<> EIGEN_STRONG_INLINE Packet4i pconj(const Packet4i& a) { return a; }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pmul<Packet4f>(const Packet4f& a, const Packet4f& b) { return vmulq_f32(a,b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4i pmul<Packet4i>(const Packet4i& a, const Packet4i& b) { return vmulq_s32(a,b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pdiv<Packet4f>(const Packet4f& a, const Packet4f& b)\n{\n#if EIGEN_ARCH_ARM64\n  return vdivq_f32(a,b);\n#else\n  Packet4f inv, restep, div;\n\n  // NEON does not offer a divide instruction, we have to do a reciprocal approximation\n  // However NEON in contrast to other SIMD engines (AltiVec/SSE), offers\n  // a reciprocal estimate AND a reciprocal step -which saves a few instructions\n  // vrecpeq_f32() returns an estimate to 1/b, which we will finetune with\n  // Newton-Raphson and vrecpsq_f32()\n  inv = vrecpeq_f32(b);\n\n  // This returns a differential, by which we will have to multiply inv to get a better\n  // approximation of 1/b.\n  restep = vrecpsq_f32(b, inv);\n  inv = vmulq_f32(restep, inv);\n\n  // Finally, multiply a by 1/b and get the wanted result of the division.\n  div = vmulq_f32(a, inv);\n\n  return div;\n#endif\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4i pdiv<Packet4i>(const Packet4i& /*a*/, const Packet4i& /*b*/)\n{ eigen_assert(false && \"packet integer division are not supported by NEON\");\n  return pset1<Packet4i>(0);\n}\n\n// Clang/ARM wrongly advertises __ARM_FEATURE_FMA even when it's not available,\n// then implements a slow software scalar fallback calling fmaf()!\n// Filed LLVM bug:\n//     https://llvm.org/bugs/show_bug.cgi?id=27216\n#if (defined __ARM_FEATURE_FMA) && !(EIGEN_COMP_CLANG && EIGEN_ARCH_ARM)\n// See bug 936.\n// FMA is available on VFPv4 i.e. when compiling with -mfpu=neon-vfpv4.\n// FMA is a true fused multiply-add i.e. only 1 rounding at the end, no intermediate rounding.\n// MLA is not fused i.e. does 2 roundings.\n// In addition to giving better accuracy, FMA also gives better performance here on a Krait (Nexus 4):\n// MLA: 10 GFlop/s ; FMA: 12 GFlops/s.\ntemplate<> EIGEN_STRONG_INLINE Packet4f pmadd(const Packet4f& a, const Packet4f& b, const Packet4f& c) { return vfmaq_f32(c,a,b); }\n#else\ntemplate<> EIGEN_STRONG_INLINE Packet4f pmadd(const Packet4f& a, const Packet4f& b, const Packet4f& c) {\n#if EIGEN_COMP_CLANG && EIGEN_ARCH_ARM\n  // Clang/ARM will replace VMLA by VMUL+VADD at least for some values of -mcpu,\n  // at least -mcpu=cortex-a8 and -mcpu=cortex-a7. Since the former is the default on\n  // -march=armv7-a, that is a very common case.\n  // See e.g. this thread:\n  //     http://lists.llvm.org/pipermail/llvm-dev/2013-December/068806.html\n  // Filed LLVM bug:\n  //     https://llvm.org/bugs/show_bug.cgi?id=27219\n  Packet4f r = c;\n  asm volatile(\n    \"vmla.f32 %q[r], %q[a], %q[b]\"\n    : [r] \"+w\" (r)\n    : [a] \"w\" (a),\n      [b] \"w\" (b)\n    : );\n  return r;\n#else\n  return vmlaq_f32(c,a,b);\n#endif\n}\n#endif\n\n// No FMA instruction for int, so use MLA unconditionally.\ntemplate<> EIGEN_STRONG_INLINE Packet4i pmadd(const Packet4i& a, const Packet4i& b, const Packet4i& c) { return vmlaq_s32(c,a,b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pmin<Packet4f>(const Packet4f& a, const Packet4f& b) { return vminq_f32(a,b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4i pmin<Packet4i>(const Packet4i& a, const Packet4i& b) { return vminq_s32(a,b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pmax<Packet4f>(const Packet4f& a, const Packet4f& b) { return vmaxq_f32(a,b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4i pmax<Packet4i>(const Packet4i& a, const Packet4i& b) { return vmaxq_s32(a,b); }\n\n// Logical Operations are not supported for float, so we have to reinterpret casts using NEON intrinsics\ntemplate<> EIGEN_STRONG_INLINE Packet4f pand<Packet4f>(const Packet4f& a, const Packet4f& b)\n{\n  return vreinterpretq_f32_u32(vandq_u32(vreinterpretq_u32_f32(a),vreinterpretq_u32_f32(b)));\n}\ntemplate<> EIGEN_STRONG_INLINE Packet4i pand<Packet4i>(const Packet4i& a, const Packet4i& b) { return vandq_s32(a,b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f por<Packet4f>(const Packet4f& a, const Packet4f& b)\n{\n  return vreinterpretq_f32_u32(vorrq_u32(vreinterpretq_u32_f32(a),vreinterpretq_u32_f32(b)));\n}\ntemplate<> EIGEN_STRONG_INLINE Packet4i por<Packet4i>(const Packet4i& a, const Packet4i& b) { return vorrq_s32(a,b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pxor<Packet4f>(const Packet4f& a, const Packet4f& b)\n{\n  return vreinterpretq_f32_u32(veorq_u32(vreinterpretq_u32_f32(a),vreinterpretq_u32_f32(b)));\n}\ntemplate<> EIGEN_STRONG_INLINE Packet4i pxor<Packet4i>(const Packet4i& a, const Packet4i& b) { return veorq_s32(a,b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pandnot<Packet4f>(const Packet4f& a, const Packet4f& b)\n{\n  return vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(a),vreinterpretq_u32_f32(b)));\n}\ntemplate<> EIGEN_STRONG_INLINE Packet4i pandnot<Packet4i>(const Packet4i& a, const Packet4i& b) { return vbicq_s32(a,b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pload<Packet4f>(const float* from) { EIGEN_DEBUG_ALIGNED_LOAD return vld1q_f32(from); }\ntemplate<> EIGEN_STRONG_INLINE Packet4i pload<Packet4i>(const int*   from) { EIGEN_DEBUG_ALIGNED_LOAD return vld1q_s32(from); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f ploadu<Packet4f>(const float* from) { EIGEN_DEBUG_UNALIGNED_LOAD return vld1q_f32(from); }\ntemplate<> EIGEN_STRONG_INLINE Packet4i ploadu<Packet4i>(const int* from)   { EIGEN_DEBUG_UNALIGNED_LOAD return vld1q_s32(from); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f ploaddup<Packet4f>(const float*   from)\n{\n  float32x2_t lo, hi;\n  lo = vld1_dup_f32(from);\n  hi = vld1_dup_f32(from+1);\n  return vcombine_f32(lo, hi);\n}\ntemplate<> EIGEN_STRONG_INLINE Packet4i ploaddup<Packet4i>(const int*     from)\n{\n  int32x2_t lo, hi;\n  lo = vld1_dup_s32(from);\n  hi = vld1_dup_s32(from+1);\n  return vcombine_s32(lo, hi);\n}\n\ntemplate<> EIGEN_STRONG_INLINE void pstore<float>(float*   to, const Packet4f& from) { EIGEN_DEBUG_ALIGNED_STORE vst1q_f32(to, from); }\ntemplate<> EIGEN_STRONG_INLINE void pstore<int>(int*       to, const Packet4i& from) { EIGEN_DEBUG_ALIGNED_STORE vst1q_s32(to, from); }\n\ntemplate<> EIGEN_STRONG_INLINE void pstoreu<float>(float*  to, const Packet4f& from) { EIGEN_DEBUG_UNALIGNED_STORE vst1q_f32(to, from); }\ntemplate<> EIGEN_STRONG_INLINE void pstoreu<int>(int*      to, const Packet4i& from) { EIGEN_DEBUG_UNALIGNED_STORE vst1q_s32(to, from); }\n\ntemplate<> EIGEN_DEVICE_FUNC inline Packet4f pgather<float, Packet4f>(const float* from, Index stride)\n{\n  Packet4f res = pset1<Packet4f>(0.f);\n  res = vsetq_lane_f32(from[0*stride], res, 0);\n  res = vsetq_lane_f32(from[1*stride], res, 1);\n  res = vsetq_lane_f32(from[2*stride], res, 2);\n  res = vsetq_lane_f32(from[3*stride], res, 3);\n  return res;\n}\ntemplate<> EIGEN_DEVICE_FUNC inline Packet4i pgather<int, Packet4i>(const int* from, Index stride)\n{\n  Packet4i res = pset1<Packet4i>(0);\n  res = vsetq_lane_s32(from[0*stride], res, 0);\n  res = vsetq_lane_s32(from[1*stride], res, 1);\n  res = vsetq_lane_s32(from[2*stride], res, 2);\n  res = vsetq_lane_s32(from[3*stride], res, 3);\n  return res;\n}\n\ntemplate<> EIGEN_DEVICE_FUNC inline void pscatter<float, Packet4f>(float* to, const Packet4f& from, Index stride)\n{\n  to[stride*0] = vgetq_lane_f32(from, 0);\n  to[stride*1] = vgetq_lane_f32(from, 1);\n  to[stride*2] = vgetq_lane_f32(from, 2);\n  to[stride*3] = vgetq_lane_f32(from, 3);\n}\ntemplate<> EIGEN_DEVICE_FUNC inline void pscatter<int, Packet4i>(int* to, const Packet4i& from, Index stride)\n{\n  to[stride*0] = vgetq_lane_s32(from, 0);\n  to[stride*1] = vgetq_lane_s32(from, 1);\n  to[stride*2] = vgetq_lane_s32(from, 2);\n  to[stride*3] = vgetq_lane_s32(from, 3);\n}\n\ntemplate<> EIGEN_STRONG_INLINE void prefetch<float>(const float* addr) { EIGEN_ARM_PREFETCH(addr); }\ntemplate<> EIGEN_STRONG_INLINE void prefetch<int>(const int*     addr) { EIGEN_ARM_PREFETCH(addr); }\n\n// FIXME only store the 2 first elements ?\ntemplate<> EIGEN_STRONG_INLINE float  pfirst<Packet4f>(const Packet4f& a) { float EIGEN_ALIGN16 x[4]; vst1q_f32(x, a); return x[0]; }\ntemplate<> EIGEN_STRONG_INLINE int    pfirst<Packet4i>(const Packet4i& a) { int   EIGEN_ALIGN16 x[4]; vst1q_s32(x, a); return x[0]; }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f preverse(const Packet4f& a) {\n  float32x2_t a_lo, a_hi;\n  Packet4f a_r64;\n\n  a_r64 = vrev64q_f32(a);\n  a_lo = vget_low_f32(a_r64);\n  a_hi = vget_high_f32(a_r64);\n  return vcombine_f32(a_hi, a_lo);\n}\ntemplate<> EIGEN_STRONG_INLINE Packet4i preverse(const Packet4i& a) {\n  int32x2_t a_lo, a_hi;\n  Packet4i a_r64;\n\n  a_r64 = vrev64q_s32(a);\n  a_lo = vget_low_s32(a_r64);\n  a_hi = vget_high_s32(a_r64);\n  return vcombine_s32(a_hi, a_lo);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pabs(const Packet4f& a) { return vabsq_f32(a); }\ntemplate<> EIGEN_STRONG_INLINE Packet4i pabs(const Packet4i& a) { return vabsq_s32(a); }\n\ntemplate<> EIGEN_STRONG_INLINE float predux<Packet4f>(const Packet4f& a)\n{\n  float32x2_t a_lo, a_hi, sum;\n\n  a_lo = vget_low_f32(a);\n  a_hi = vget_high_f32(a);\n  sum = vpadd_f32(a_lo, a_hi);\n  sum = vpadd_f32(sum, sum);\n  return vget_lane_f32(sum, 0);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f preduxp<Packet4f>(const Packet4f* vecs)\n{\n  float32x4x2_t vtrn1, vtrn2, res1, res2;\n  Packet4f sum1, sum2, sum;\n\n  // NEON zip performs interleaving of the supplied vectors.\n  // We perform two interleaves in a row to acquire the transposed vector\n  vtrn1 = vzipq_f32(vecs[0], vecs[2]);\n  vtrn2 = vzipq_f32(vecs[1], vecs[3]);\n  res1 = vzipq_f32(vtrn1.val[0], vtrn2.val[0]);\n  res2 = vzipq_f32(vtrn1.val[1], vtrn2.val[1]);\n\n  // Do the addition of the resulting vectors\n  sum1 = vaddq_f32(res1.val[0], res1.val[1]);\n  sum2 = vaddq_f32(res2.val[0], res2.val[1]);\n  sum = vaddq_f32(sum1, sum2);\n\n  return sum;\n}\n\ntemplate<> EIGEN_STRONG_INLINE int predux<Packet4i>(const Packet4i& a)\n{\n  int32x2_t a_lo, a_hi, sum;\n\n  a_lo = vget_low_s32(a);\n  a_hi = vget_high_s32(a);\n  sum = vpadd_s32(a_lo, a_hi);\n  sum = vpadd_s32(sum, sum);\n  return vget_lane_s32(sum, 0);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4i preduxp<Packet4i>(const Packet4i* vecs)\n{\n  int32x4x2_t vtrn1, vtrn2, res1, res2;\n  Packet4i sum1, sum2, sum;\n\n  // NEON zip performs interleaving of the supplied vectors.\n  // We perform two interleaves in a row to acquire the transposed vector\n  vtrn1 = vzipq_s32(vecs[0], vecs[2]);\n  vtrn2 = vzipq_s32(vecs[1], vecs[3]);\n  res1 = vzipq_s32(vtrn1.val[0], vtrn2.val[0]);\n  res2 = vzipq_s32(vtrn1.val[1], vtrn2.val[1]);\n\n  // Do the addition of the resulting vectors\n  sum1 = vaddq_s32(res1.val[0], res1.val[1]);\n  sum2 = vaddq_s32(res2.val[0], res2.val[1]);\n  sum = vaddq_s32(sum1, sum2);\n\n  return sum;\n}\n\n// Other reduction functions:\n// mul\ntemplate<> EIGEN_STRONG_INLINE float predux_mul<Packet4f>(const Packet4f& a)\n{\n  float32x2_t a_lo, a_hi, prod;\n\n  // Get a_lo = |a1|a2| and a_hi = |a3|a4|\n  a_lo = vget_low_f32(a);\n  a_hi = vget_high_f32(a);\n  // Get the product of a_lo * a_hi -> |a1*a3|a2*a4|\n  prod = vmul_f32(a_lo, a_hi);\n  // Multiply prod with its swapped value |a2*a4|a1*a3|\n  prod = vmul_f32(prod, vrev64_f32(prod));\n\n  return vget_lane_f32(prod, 0);\n}\ntemplate<> EIGEN_STRONG_INLINE int predux_mul<Packet4i>(const Packet4i& a)\n{\n  int32x2_t a_lo, a_hi, prod;\n\n  // Get a_lo = |a1|a2| and a_hi = |a3|a4|\n  a_lo = vget_low_s32(a);\n  a_hi = vget_high_s32(a);\n  // Get the product of a_lo * a_hi -> |a1*a3|a2*a4|\n  prod = vmul_s32(a_lo, a_hi);\n  // Multiply prod with its swapped value |a2*a4|a1*a3|\n  prod = vmul_s32(prod, vrev64_s32(prod));\n\n  return vget_lane_s32(prod, 0);\n}\n\n// min\ntemplate<> EIGEN_STRONG_INLINE float predux_min<Packet4f>(const Packet4f& a)\n{\n  float32x2_t a_lo, a_hi, min;\n\n  a_lo = vget_low_f32(a);\n  a_hi = vget_high_f32(a);\n  min = vpmin_f32(a_lo, a_hi);\n  min = vpmin_f32(min, min);\n\n  return vget_lane_f32(min, 0);\n}\n\ntemplate<> EIGEN_STRONG_INLINE int predux_min<Packet4i>(const Packet4i& a)\n{\n  int32x2_t a_lo, a_hi, min;\n\n  a_lo = vget_low_s32(a);\n  a_hi = vget_high_s32(a);\n  min = vpmin_s32(a_lo, a_hi);\n  min = vpmin_s32(min, min);\n  \n  return vget_lane_s32(min, 0);\n}\n\n// max\ntemplate<> EIGEN_STRONG_INLINE float predux_max<Packet4f>(const Packet4f& a)\n{\n  float32x2_t a_lo, a_hi, max;\n\n  a_lo = vget_low_f32(a);\n  a_hi = vget_high_f32(a);\n  max = vpmax_f32(a_lo, a_hi);\n  max = vpmax_f32(max, max);\n\n  return vget_lane_f32(max, 0);\n}\n\ntemplate<> EIGEN_STRONG_INLINE int predux_max<Packet4i>(const Packet4i& a)\n{\n  int32x2_t a_lo, a_hi, max;\n\n  a_lo = vget_low_s32(a);\n  a_hi = vget_high_s32(a);\n  max = vpmax_s32(a_lo, a_hi);\n  max = vpmax_s32(max, max);\n\n  return vget_lane_s32(max, 0);\n}\n\n// this PALIGN_NEON business is to work around a bug in LLVM Clang 3.0 causing incorrect compilation errors,\n// see bug 347 and this LLVM bug: http://llvm.org/bugs/show_bug.cgi?id=11074\n#define PALIGN_NEON(Offset,Type,Command) \\\ntemplate<>\\\nstruct palign_impl<Offset,Type>\\\n{\\\n    EIGEN_STRONG_INLINE static void run(Type& first, const Type& second)\\\n    {\\\n        if (Offset!=0)\\\n            first = Command(first, second, Offset);\\\n    }\\\n};\\\n\nPALIGN_NEON(0,Packet4f,vextq_f32)\nPALIGN_NEON(1,Packet4f,vextq_f32)\nPALIGN_NEON(2,Packet4f,vextq_f32)\nPALIGN_NEON(3,Packet4f,vextq_f32)\nPALIGN_NEON(0,Packet4i,vextq_s32)\nPALIGN_NEON(1,Packet4i,vextq_s32)\nPALIGN_NEON(2,Packet4i,vextq_s32)\nPALIGN_NEON(3,Packet4i,vextq_s32)\n\n#undef PALIGN_NEON\n\nEIGEN_DEVICE_FUNC inline void\nptranspose(PacketBlock<Packet4f,4>& kernel) {\n  float32x4x2_t tmp1 = vzipq_f32(kernel.packet[0], kernel.packet[1]);\n  float32x4x2_t tmp2 = vzipq_f32(kernel.packet[2], kernel.packet[3]);\n\n  kernel.packet[0] = vcombine_f32(vget_low_f32(tmp1.val[0]), vget_low_f32(tmp2.val[0]));\n  kernel.packet[1] = vcombine_f32(vget_high_f32(tmp1.val[0]), vget_high_f32(tmp2.val[0]));\n  kernel.packet[2] = vcombine_f32(vget_low_f32(tmp1.val[1]), vget_low_f32(tmp2.val[1]));\n  kernel.packet[3] = vcombine_f32(vget_high_f32(tmp1.val[1]), vget_high_f32(tmp2.val[1]));\n}\n\nEIGEN_DEVICE_FUNC inline void\nptranspose(PacketBlock<Packet4i,4>& kernel) {\n  int32x4x2_t tmp1 = vzipq_s32(kernel.packet[0], kernel.packet[1]);\n  int32x4x2_t tmp2 = vzipq_s32(kernel.packet[2], kernel.packet[3]);\n  kernel.packet[0] = vcombine_s32(vget_low_s32(tmp1.val[0]), vget_low_s32(tmp2.val[0]));\n  kernel.packet[1] = vcombine_s32(vget_high_s32(tmp1.val[0]), vget_high_s32(tmp2.val[0]));\n  kernel.packet[2] = vcombine_s32(vget_low_s32(tmp1.val[1]), vget_low_s32(tmp2.val[1]));\n  kernel.packet[3] = vcombine_s32(vget_high_s32(tmp1.val[1]), vget_high_s32(tmp2.val[1]));\n}\n\n//---------- double ----------\n\n// Clang 3.5 in the iOS toolchain has an ICE triggered by NEON intrisics for double.\n// Confirmed at least with __apple_build_version__ = 6000054.\n#ifdef __apple_build_version__\n// Let's hope that by the time __apple_build_version__ hits the 601* range, the bug will be fixed.\n// https://gist.github.com/yamaya/2924292 suggests that the 3 first digits are only updated with\n// major toolchain updates.\n#define EIGEN_APPLE_DOUBLE_NEON_BUG (__apple_build_version__ < 6010000)\n#else\n#define EIGEN_APPLE_DOUBLE_NEON_BUG 0\n#endif\n\n#if EIGEN_ARCH_ARM64 && !EIGEN_APPLE_DOUBLE_NEON_BUG\n\n// Bug 907: workaround missing declarations of the following two functions in the ADK\n// Defining these functions as templates ensures that if these intrinsics are\n// already defined in arm_neon.h, then our workaround doesn't cause a conflict\n// and has lower priority in overload resolution.\ntemplate <typename T>\nuint64x2_t vreinterpretq_u64_f64(T a)\n{\n  return (uint64x2_t) a;\n}\n\ntemplate <typename T>\nfloat64x2_t vreinterpretq_f64_u64(T a)\n{\n  return (float64x2_t) a;\n}\n\ntypedef float64x2_t Packet2d;\ntypedef float64x1_t Packet1d;\n\ntemplate<> struct packet_traits<double>  : default_packet_traits\n{\n  typedef Packet2d type;\n  typedef Packet2d half;\n  enum {\n    Vectorizable = 1,\n    AlignedOnScalar = 1,\n    size = 2,\n    HasHalfPacket=0,\n   \n    HasDiv  = 1,\n    // FIXME check the Has*\n    HasSin  = 0,\n    HasCos  = 0,\n    HasLog  = 0,\n    HasExp  = 0,\n    HasSqrt = 0\n  };\n};\n\ntemplate<> struct unpacket_traits<Packet2d> { typedef double  type; enum {size=2, alignment=Aligned16}; typedef Packet2d half; };\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d pset1<Packet2d>(const double&  from) { return vdupq_n_f64(from); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d plset<Packet2d>(const double& a)\n{\n  const double countdown_raw[] = {0.0,1.0};\n  const Packet2d countdown = vld1q_f64(countdown_raw);\n  return vaddq_f64(pset1<Packet2d>(a), countdown);\n}\ntemplate<> EIGEN_STRONG_INLINE Packet2d padd<Packet2d>(const Packet2d& a, const Packet2d& b) { return vaddq_f64(a,b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d psub<Packet2d>(const Packet2d& a, const Packet2d& b) { return vsubq_f64(a,b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d pnegate(const Packet2d& a) { return vnegq_f64(a); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d pconj(const Packet2d& a) { return a; }\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d pmul<Packet2d>(const Packet2d& a, const Packet2d& b) { return vmulq_f64(a,b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d pdiv<Packet2d>(const Packet2d& a, const Packet2d& b) { return vdivq_f64(a,b); }\n\n#ifdef __ARM_FEATURE_FMA\n// See bug 936. See above comment about FMA for float.\ntemplate<> EIGEN_STRONG_INLINE Packet2d pmadd(const Packet2d& a, const Packet2d& b, const Packet2d& c) { return vfmaq_f64(c,a,b); }\n#else\ntemplate<> EIGEN_STRONG_INLINE Packet2d pmadd(const Packet2d& a, const Packet2d& b, const Packet2d& c) { return vmlaq_f64(c,a,b); }\n#endif\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d pmin<Packet2d>(const Packet2d& a, const Packet2d& b) { return vminq_f64(a,b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d pmax<Packet2d>(const Packet2d& a, const Packet2d& b) { return vmaxq_f64(a,b); }\n\n// Logical Operations are not supported for float, so we have to reinterpret casts using NEON intrinsics\ntemplate<> EIGEN_STRONG_INLINE Packet2d pand<Packet2d>(const Packet2d& a, const Packet2d& b)\n{\n  return vreinterpretq_f64_u64(vandq_u64(vreinterpretq_u64_f64(a),vreinterpretq_u64_f64(b)));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d por<Packet2d>(const Packet2d& a, const Packet2d& b)\n{\n  return vreinterpretq_f64_u64(vorrq_u64(vreinterpretq_u64_f64(a),vreinterpretq_u64_f64(b)));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d pxor<Packet2d>(const Packet2d& a, const Packet2d& b)\n{\n  return vreinterpretq_f64_u64(veorq_u64(vreinterpretq_u64_f64(a),vreinterpretq_u64_f64(b)));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d pandnot<Packet2d>(const Packet2d& a, const Packet2d& b)\n{\n  return vreinterpretq_f64_u64(vbicq_u64(vreinterpretq_u64_f64(a),vreinterpretq_u64_f64(b)));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d pload<Packet2d>(const double* from) { EIGEN_DEBUG_ALIGNED_LOAD return vld1q_f64(from); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d ploadu<Packet2d>(const double* from) { EIGEN_DEBUG_UNALIGNED_LOAD return vld1q_f64(from); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d ploaddup<Packet2d>(const double*   from)\n{\n  return vld1q_dup_f64(from);\n}\ntemplate<> EIGEN_STRONG_INLINE void pstore<double>(double*   to, const Packet2d& from) { EIGEN_DEBUG_ALIGNED_STORE vst1q_f64(to, from); }\n\ntemplate<> EIGEN_STRONG_INLINE void pstoreu<double>(double*  to, const Packet2d& from) { EIGEN_DEBUG_UNALIGNED_STORE vst1q_f64(to, from); }\n\ntemplate<> EIGEN_DEVICE_FUNC inline Packet2d pgather<double, Packet2d>(const double* from, Index stride)\n{\n  Packet2d res = pset1<Packet2d>(0.0);\n  res = vsetq_lane_f64(from[0*stride], res, 0);\n  res = vsetq_lane_f64(from[1*stride], res, 1);\n  return res;\n}\ntemplate<> EIGEN_DEVICE_FUNC inline void pscatter<double, Packet2d>(double* to, const Packet2d& from, Index stride)\n{\n  to[stride*0] = vgetq_lane_f64(from, 0);\n  to[stride*1] = vgetq_lane_f64(from, 1);\n}\ntemplate<> EIGEN_STRONG_INLINE void prefetch<double>(const double* addr) { EIGEN_ARM_PREFETCH(addr); }\n\n// FIXME only store the 2 first elements ?\ntemplate<> EIGEN_STRONG_INLINE double pfirst<Packet2d>(const Packet2d& a) { return vgetq_lane_f64(a, 0); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d preverse(const Packet2d& a) { return vcombine_f64(vget_high_f64(a), vget_low_f64(a)); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d pabs(const Packet2d& a) { return vabsq_f64(a); }\n\n#if EIGEN_COMP_CLANG && defined(__apple_build_version__)\n// workaround ICE, see bug 907\ntemplate<> EIGEN_STRONG_INLINE double predux<Packet2d>(const Packet2d& a) { return (vget_low_f64(a) + vget_high_f64(a))[0]; }\n#else\ntemplate<> EIGEN_STRONG_INLINE double predux<Packet2d>(const Packet2d& a) { return vget_lane_f64(vget_low_f64(a) + vget_high_f64(a), 0); }\n#endif\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d preduxp<Packet2d>(const Packet2d* vecs)\n{\n  float64x2_t trn1, trn2;\n\n  // NEON zip performs interleaving of the supplied vectors.\n  // We perform two interleaves in a row to acquire the transposed vector\n  trn1 = vzip1q_f64(vecs[0], vecs[1]);\n  trn2 = vzip2q_f64(vecs[0], vecs[1]);\n\n  // Do the addition of the resulting vectors\n  return vaddq_f64(trn1, trn2);\n}\n// Other reduction functions:\n// mul\n#if EIGEN_COMP_CLANG && defined(__apple_build_version__)\ntemplate<> EIGEN_STRONG_INLINE double predux_mul<Packet2d>(const Packet2d& a) { return (vget_low_f64(a) * vget_high_f64(a))[0]; }\n#else\ntemplate<> EIGEN_STRONG_INLINE double predux_mul<Packet2d>(const Packet2d& a) { return vget_lane_f64(vget_low_f64(a) * vget_high_f64(a), 0); }\n#endif\n\n// min\ntemplate<> EIGEN_STRONG_INLINE double predux_min<Packet2d>(const Packet2d& a) { return vgetq_lane_f64(vpminq_f64(a, a), 0); }\n\n// max\ntemplate<> EIGEN_STRONG_INLINE double predux_max<Packet2d>(const Packet2d& a) { return vgetq_lane_f64(vpmaxq_f64(a, a), 0); }\n\n// this PALIGN_NEON business is to work around a bug in LLVM Clang 3.0 causing incorrect compilation errors,\n// see bug 347 and this LLVM bug: http://llvm.org/bugs/show_bug.cgi?id=11074\n#define PALIGN_NEON(Offset,Type,Command) \\\ntemplate<>\\\nstruct palign_impl<Offset,Type>\\\n{\\\n    EIGEN_STRONG_INLINE static void run(Type& first, const Type& second)\\\n    {\\\n        if (Offset!=0)\\\n            first = Command(first, second, Offset);\\\n    }\\\n};\\\n\nPALIGN_NEON(0,Packet2d,vextq_f64)\nPALIGN_NEON(1,Packet2d,vextq_f64)\n#undef PALIGN_NEON\n\nEIGEN_DEVICE_FUNC inline void\nptranspose(PacketBlock<Packet2d,2>& kernel) {\n  float64x2_t trn1 = vzip1q_f64(kernel.packet[0], kernel.packet[1]);\n  float64x2_t trn2 = vzip2q_f64(kernel.packet[0], kernel.packet[1]);\n\n  kernel.packet[0] = trn1;\n  kernel.packet[1] = trn2;\n}\n#endif // EIGEN_ARCH_ARM64 \n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_PACKET_MATH_NEON_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/arch/SSE/Complex.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_COMPLEX_SSE_H\n#define EIGEN_COMPLEX_SSE_H\n\nnamespace Eigen {\n\nnamespace internal {\n\n//---------- float ----------\nstruct Packet2cf\n{\n  EIGEN_STRONG_INLINE Packet2cf() {}\n  EIGEN_STRONG_INLINE explicit Packet2cf(const __m128& a) : v(a) {}\n  __m128  v;\n};\n\n// Use the packet_traits defined in AVX/PacketMath.h instead if we're going\n// to leverage AVX instructions.\n#ifndef EIGEN_VECTORIZE_AVX\ntemplate<> struct packet_traits<std::complex<float> >  : default_packet_traits\n{\n  typedef Packet2cf type;\n  typedef Packet2cf half;\n  enum {\n    Vectorizable = 1,\n    AlignedOnScalar = 1,\n    size = 2,\n    HasHalfPacket = 0,\n\n    HasAdd    = 1,\n    HasSub    = 1,\n    HasMul    = 1,\n    HasDiv    = 1,\n    HasNegate = 1,\n    HasAbs    = 0,\n    HasAbs2   = 0,\n    HasMin    = 0,\n    HasMax    = 0,\n    HasSetLinear = 0,\n    HasBlend = 1\n  };\n};\n#endif\n\ntemplate<> struct unpacket_traits<Packet2cf> { typedef std::complex<float> type; enum {size=2, alignment=Aligned16}; typedef Packet2cf half; };\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cf padd<Packet2cf>(const Packet2cf& a, const Packet2cf& b) { return Packet2cf(_mm_add_ps(a.v,b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet2cf psub<Packet2cf>(const Packet2cf& a, const Packet2cf& b) { return Packet2cf(_mm_sub_ps(a.v,b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pnegate(const Packet2cf& a)\n{\n  const __m128 mask = _mm_castsi128_ps(_mm_setr_epi32(0x80000000,0x80000000,0x80000000,0x80000000));\n  return Packet2cf(_mm_xor_ps(a.v,mask));\n}\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pconj(const Packet2cf& a)\n{\n  const __m128 mask = _mm_castsi128_ps(_mm_setr_epi32(0x00000000,0x80000000,0x00000000,0x80000000));\n  return Packet2cf(_mm_xor_ps(a.v,mask));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pmul<Packet2cf>(const Packet2cf& a, const Packet2cf& b)\n{\n  #ifdef EIGEN_VECTORIZE_SSE3\n  return Packet2cf(_mm_addsub_ps(_mm_mul_ps(_mm_moveldup_ps(a.v), b.v),\n                                 _mm_mul_ps(_mm_movehdup_ps(a.v),\n                                            vec4f_swizzle1(b.v, 1, 0, 3, 2))));\n//   return Packet2cf(_mm_addsub_ps(_mm_mul_ps(vec4f_swizzle1(a.v, 0, 0, 2, 2), b.v),\n//                                  _mm_mul_ps(vec4f_swizzle1(a.v, 1, 1, 3, 3),\n//                                             vec4f_swizzle1(b.v, 1, 0, 3, 2))));\n  #else\n  const __m128 mask = _mm_castsi128_ps(_mm_setr_epi32(0x80000000,0x00000000,0x80000000,0x00000000));\n  return Packet2cf(_mm_add_ps(_mm_mul_ps(vec4f_swizzle1(a.v, 0, 0, 2, 2), b.v),\n                              _mm_xor_ps(_mm_mul_ps(vec4f_swizzle1(a.v, 1, 1, 3, 3),\n                                                    vec4f_swizzle1(b.v, 1, 0, 3, 2)), mask)));\n  #endif\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pand   <Packet2cf>(const Packet2cf& a, const Packet2cf& b) { return Packet2cf(_mm_and_ps(a.v,b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet2cf por    <Packet2cf>(const Packet2cf& a, const Packet2cf& b) { return Packet2cf(_mm_or_ps(a.v,b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pxor   <Packet2cf>(const Packet2cf& a, const Packet2cf& b) { return Packet2cf(_mm_xor_ps(a.v,b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pandnot<Packet2cf>(const Packet2cf& a, const Packet2cf& b) { return Packet2cf(_mm_andnot_ps(a.v,b.v)); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pload <Packet2cf>(const std::complex<float>* from) { EIGEN_DEBUG_ALIGNED_LOAD return Packet2cf(pload<Packet4f>(&numext::real_ref(*from))); }\ntemplate<> EIGEN_STRONG_INLINE Packet2cf ploadu<Packet2cf>(const std::complex<float>* from) { EIGEN_DEBUG_UNALIGNED_LOAD return Packet2cf(ploadu<Packet4f>(&numext::real_ref(*from))); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pset1<Packet2cf>(const std::complex<float>&  from)\n{\n  Packet2cf res;\n#if EIGEN_GNUC_AT_MOST(4,2)\n  // Workaround annoying \"may be used uninitialized in this function\" warning with gcc 4.2\n  res.v = _mm_loadl_pi(_mm_set1_ps(0.0f), reinterpret_cast<const __m64*>(&from));\n#elif EIGEN_GNUC_AT_LEAST(4,6)\n  // Suppress annoying \"may be used uninitialized in this function\" warning with gcc >= 4.6\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wuninitialized\"\n  res.v = _mm_loadl_pi(res.v, (const __m64*)&from);\n  #pragma GCC diagnostic pop\n#else\n  res.v = _mm_loadl_pi(res.v, (const __m64*)&from);\n#endif\n  return Packet2cf(_mm_movelh_ps(res.v,res.v));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cf ploaddup<Packet2cf>(const std::complex<float>* from) { return pset1<Packet2cf>(*from); }\n\ntemplate<> EIGEN_STRONG_INLINE void pstore <std::complex<float> >(std::complex<float> *   to, const Packet2cf& from) { EIGEN_DEBUG_ALIGNED_STORE pstore(&numext::real_ref(*to), Packet4f(from.v)); }\ntemplate<> EIGEN_STRONG_INLINE void pstoreu<std::complex<float> >(std::complex<float> *   to, const Packet2cf& from) { EIGEN_DEBUG_UNALIGNED_STORE pstoreu(&numext::real_ref(*to), Packet4f(from.v)); }\n\n\ntemplate<> EIGEN_DEVICE_FUNC inline Packet2cf pgather<std::complex<float>, Packet2cf>(const std::complex<float>* from, Index stride)\n{\n  return Packet2cf(_mm_set_ps(std::imag(from[1*stride]), std::real(from[1*stride]),\n                              std::imag(from[0*stride]), std::real(from[0*stride])));\n}\n\ntemplate<> EIGEN_DEVICE_FUNC inline void pscatter<std::complex<float>, Packet2cf>(std::complex<float>* to, const Packet2cf& from, Index stride)\n{\n  to[stride*0] = std::complex<float>(_mm_cvtss_f32(_mm_shuffle_ps(from.v, from.v, 0)),\n                                     _mm_cvtss_f32(_mm_shuffle_ps(from.v, from.v, 1)));\n  to[stride*1] = std::complex<float>(_mm_cvtss_f32(_mm_shuffle_ps(from.v, from.v, 2)),\n                                     _mm_cvtss_f32(_mm_shuffle_ps(from.v, from.v, 3)));\n}\n\ntemplate<> EIGEN_STRONG_INLINE void prefetch<std::complex<float> >(const std::complex<float> *   addr) { _mm_prefetch((const char*)(addr), _MM_HINT_T0); }\n\ntemplate<> EIGEN_STRONG_INLINE std::complex<float>  pfirst<Packet2cf>(const Packet2cf& a)\n{\n  #if EIGEN_GNUC_AT_MOST(4,3)\n  // Workaround gcc 4.2 ICE - this is not performance wise ideal, but who cares...\n  // This workaround also fix invalid code generation with gcc 4.3\n  EIGEN_ALIGN16 std::complex<float> res[2];\n  _mm_store_ps((float*)res, a.v);\n  return res[0];\n  #else\n  std::complex<float> res;\n  _mm_storel_pi((__m64*)&res, a.v);\n  return res;\n  #endif\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cf preverse(const Packet2cf& a) { return Packet2cf(_mm_castpd_ps(preverse(Packet2d(_mm_castps_pd(a.v))))); }\n\ntemplate<> EIGEN_STRONG_INLINE std::complex<float> predux<Packet2cf>(const Packet2cf& a)\n{\n  return pfirst(Packet2cf(_mm_add_ps(a.v, _mm_movehl_ps(a.v,a.v))));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cf preduxp<Packet2cf>(const Packet2cf* vecs)\n{\n  return Packet2cf(_mm_add_ps(_mm_movelh_ps(vecs[0].v,vecs[1].v), _mm_movehl_ps(vecs[1].v,vecs[0].v)));\n}\n\ntemplate<> EIGEN_STRONG_INLINE std::complex<float> predux_mul<Packet2cf>(const Packet2cf& a)\n{\n  return pfirst(pmul(a, Packet2cf(_mm_movehl_ps(a.v,a.v))));\n}\n\ntemplate<int Offset>\nstruct palign_impl<Offset,Packet2cf>\n{\n  static EIGEN_STRONG_INLINE void run(Packet2cf& first, const Packet2cf& second)\n  {\n    if (Offset==1)\n    {\n      first.v = _mm_movehl_ps(first.v, first.v);\n      first.v = _mm_movelh_ps(first.v, second.v);\n    }\n  }\n};\n\ntemplate<> struct conj_helper<Packet2cf, Packet2cf, false,true>\n{\n  EIGEN_STRONG_INLINE Packet2cf pmadd(const Packet2cf& x, const Packet2cf& y, const Packet2cf& c) const\n  { return padd(pmul(x,y),c); }\n\n  EIGEN_STRONG_INLINE Packet2cf pmul(const Packet2cf& a, const Packet2cf& b) const\n  {\n    #ifdef EIGEN_VECTORIZE_SSE3\n    return internal::pmul(a, pconj(b));\n    #else\n    const __m128 mask = _mm_castsi128_ps(_mm_setr_epi32(0x00000000,0x80000000,0x00000000,0x80000000));\n    return Packet2cf(_mm_add_ps(_mm_xor_ps(_mm_mul_ps(vec4f_swizzle1(a.v, 0, 0, 2, 2), b.v), mask),\n                                _mm_mul_ps(vec4f_swizzle1(a.v, 1, 1, 3, 3),\n                                           vec4f_swizzle1(b.v, 1, 0, 3, 2))));\n    #endif\n  }\n};\n\ntemplate<> struct conj_helper<Packet2cf, Packet2cf, true,false>\n{\n  EIGEN_STRONG_INLINE Packet2cf pmadd(const Packet2cf& x, const Packet2cf& y, const Packet2cf& c) const\n  { return padd(pmul(x,y),c); }\n\n  EIGEN_STRONG_INLINE Packet2cf pmul(const Packet2cf& a, const Packet2cf& b) const\n  {\n    #ifdef EIGEN_VECTORIZE_SSE3\n    return internal::pmul(pconj(a), b);\n    #else\n    const __m128 mask = _mm_castsi128_ps(_mm_setr_epi32(0x00000000,0x80000000,0x00000000,0x80000000));\n    return Packet2cf(_mm_add_ps(_mm_mul_ps(vec4f_swizzle1(a.v, 0, 0, 2, 2), b.v),\n                                _mm_xor_ps(_mm_mul_ps(vec4f_swizzle1(a.v, 1, 1, 3, 3),\n                                                      vec4f_swizzle1(b.v, 1, 0, 3, 2)), mask)));\n    #endif\n  }\n};\n\ntemplate<> struct conj_helper<Packet2cf, Packet2cf, true,true>\n{\n  EIGEN_STRONG_INLINE Packet2cf pmadd(const Packet2cf& x, const Packet2cf& y, const Packet2cf& c) const\n  { return padd(pmul(x,y),c); }\n\n  EIGEN_STRONG_INLINE Packet2cf pmul(const Packet2cf& a, const Packet2cf& b) const\n  {\n    #ifdef EIGEN_VECTORIZE_SSE3\n    return pconj(internal::pmul(a, b));\n    #else\n    const __m128 mask = _mm_castsi128_ps(_mm_setr_epi32(0x00000000,0x80000000,0x00000000,0x80000000));\n    return Packet2cf(_mm_sub_ps(_mm_xor_ps(_mm_mul_ps(vec4f_swizzle1(a.v, 0, 0, 2, 2), b.v), mask),\n                                _mm_mul_ps(vec4f_swizzle1(a.v, 1, 1, 3, 3),\n                                           vec4f_swizzle1(b.v, 1, 0, 3, 2))));\n    #endif\n  }\n};\n\ntemplate<> struct conj_helper<Packet4f, Packet2cf, false,false>\n{\n  EIGEN_STRONG_INLINE Packet2cf pmadd(const Packet4f& x, const Packet2cf& y, const Packet2cf& c) const\n  { return padd(c, pmul(x,y)); }\n\n  EIGEN_STRONG_INLINE Packet2cf pmul(const Packet4f& x, const Packet2cf& y) const\n  { return Packet2cf(Eigen::internal::pmul<Packet4f>(x, y.v)); }\n};\n\ntemplate<> struct conj_helper<Packet2cf, Packet4f, false,false>\n{\n  EIGEN_STRONG_INLINE Packet2cf pmadd(const Packet2cf& x, const Packet4f& y, const Packet2cf& c) const\n  { return padd(c, pmul(x,y)); }\n\n  EIGEN_STRONG_INLINE Packet2cf pmul(const Packet2cf& x, const Packet4f& y) const\n  { return Packet2cf(Eigen::internal::pmul<Packet4f>(x.v, y)); }\n};\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pdiv<Packet2cf>(const Packet2cf& a, const Packet2cf& b)\n{\n  // TODO optimize it for SSE3 and 4\n  Packet2cf res = conj_helper<Packet2cf,Packet2cf,false,true>().pmul(a,b);\n  __m128 s = _mm_mul_ps(b.v,b.v);\n  return Packet2cf(_mm_div_ps(res.v,_mm_add_ps(s,_mm_castsi128_ps(_mm_shuffle_epi32(_mm_castps_si128(s), 0xb1)))));\n}\n\nEIGEN_STRONG_INLINE Packet2cf pcplxflip/* <Packet2cf> */(const Packet2cf& x)\n{\n  return Packet2cf(vec4f_swizzle1(x.v, 1, 0, 3, 2));\n}\n\n\n//---------- double ----------\nstruct Packet1cd\n{\n  EIGEN_STRONG_INLINE Packet1cd() {}\n  EIGEN_STRONG_INLINE explicit Packet1cd(const __m128d& a) : v(a) {}\n  __m128d  v;\n};\n\n// Use the packet_traits defined in AVX/PacketMath.h instead if we're going\n// to leverage AVX instructions.\n#ifndef EIGEN_VECTORIZE_AVX\ntemplate<> struct packet_traits<std::complex<double> >  : default_packet_traits\n{\n  typedef Packet1cd type;\n  typedef Packet1cd half;\n  enum {\n    Vectorizable = 1,\n    AlignedOnScalar = 0,\n    size = 1,\n    HasHalfPacket = 0,\n\n    HasAdd    = 1,\n    HasSub    = 1,\n    HasMul    = 1,\n    HasDiv    = 1,\n    HasNegate = 1,\n    HasAbs    = 0,\n    HasAbs2   = 0,\n    HasMin    = 0,\n    HasMax    = 0,\n    HasSetLinear = 0\n  };\n};\n#endif\n\ntemplate<> struct unpacket_traits<Packet1cd> { typedef std::complex<double> type; enum {size=1, alignment=Aligned16}; typedef Packet1cd half; };\n\ntemplate<> EIGEN_STRONG_INLINE Packet1cd padd<Packet1cd>(const Packet1cd& a, const Packet1cd& b) { return Packet1cd(_mm_add_pd(a.v,b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet1cd psub<Packet1cd>(const Packet1cd& a, const Packet1cd& b) { return Packet1cd(_mm_sub_pd(a.v,b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pnegate(const Packet1cd& a) { return Packet1cd(pnegate(Packet2d(a.v))); }\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pconj(const Packet1cd& a)\n{\n  const __m128d mask = _mm_castsi128_pd(_mm_set_epi32(0x80000000,0x0,0x0,0x0));\n  return Packet1cd(_mm_xor_pd(a.v,mask));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pmul<Packet1cd>(const Packet1cd& a, const Packet1cd& b)\n{\n  #ifdef EIGEN_VECTORIZE_SSE3\n  return Packet1cd(_mm_addsub_pd(_mm_mul_pd(_mm_movedup_pd(a.v), b.v),\n                                 _mm_mul_pd(vec2d_swizzle1(a.v, 1, 1),\n                                            vec2d_swizzle1(b.v, 1, 0))));\n  #else\n  const __m128d mask = _mm_castsi128_pd(_mm_set_epi32(0x0,0x0,0x80000000,0x0));\n  return Packet1cd(_mm_add_pd(_mm_mul_pd(vec2d_swizzle1(a.v, 0, 0), b.v),\n                              _mm_xor_pd(_mm_mul_pd(vec2d_swizzle1(a.v, 1, 1),\n                                                    vec2d_swizzle1(b.v, 1, 0)), mask)));\n  #endif\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pand   <Packet1cd>(const Packet1cd& a, const Packet1cd& b) { return Packet1cd(_mm_and_pd(a.v,b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet1cd por    <Packet1cd>(const Packet1cd& a, const Packet1cd& b) { return Packet1cd(_mm_or_pd(a.v,b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pxor   <Packet1cd>(const Packet1cd& a, const Packet1cd& b) { return Packet1cd(_mm_xor_pd(a.v,b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pandnot<Packet1cd>(const Packet1cd& a, const Packet1cd& b) { return Packet1cd(_mm_andnot_pd(a.v,b.v)); }\n\n// FIXME force unaligned load, this is a temporary fix\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pload <Packet1cd>(const std::complex<double>* from)\n{ EIGEN_DEBUG_ALIGNED_LOAD return Packet1cd(pload<Packet2d>((const double*)from)); }\ntemplate<> EIGEN_STRONG_INLINE Packet1cd ploadu<Packet1cd>(const std::complex<double>* from)\n{ EIGEN_DEBUG_UNALIGNED_LOAD return Packet1cd(ploadu<Packet2d>((const double*)from)); }\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pset1<Packet1cd>(const std::complex<double>&  from)\n{ /* here we really have to use unaligned loads :( */ return ploadu<Packet1cd>(&from); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet1cd ploaddup<Packet1cd>(const std::complex<double>* from) { return pset1<Packet1cd>(*from); }\n\n// FIXME force unaligned store, this is a temporary fix\ntemplate<> EIGEN_STRONG_INLINE void pstore <std::complex<double> >(std::complex<double> *   to, const Packet1cd& from) { EIGEN_DEBUG_ALIGNED_STORE pstore((double*)to, Packet2d(from.v)); }\ntemplate<> EIGEN_STRONG_INLINE void pstoreu<std::complex<double> >(std::complex<double> *   to, const Packet1cd& from) { EIGEN_DEBUG_UNALIGNED_STORE pstoreu((double*)to, Packet2d(from.v)); }\n\ntemplate<> EIGEN_STRONG_INLINE void prefetch<std::complex<double> >(const std::complex<double> *   addr) { _mm_prefetch((const char*)(addr), _MM_HINT_T0); }\n\ntemplate<> EIGEN_STRONG_INLINE std::complex<double>  pfirst<Packet1cd>(const Packet1cd& a)\n{\n  EIGEN_ALIGN16 double res[2];\n  _mm_store_pd(res, a.v);\n  return std::complex<double>(res[0],res[1]);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet1cd preverse(const Packet1cd& a) { return a; }\n\ntemplate<> EIGEN_STRONG_INLINE std::complex<double> predux<Packet1cd>(const Packet1cd& a)\n{\n  return pfirst(a);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet1cd preduxp<Packet1cd>(const Packet1cd* vecs)\n{\n  return vecs[0];\n}\n\ntemplate<> EIGEN_STRONG_INLINE std::complex<double> predux_mul<Packet1cd>(const Packet1cd& a)\n{\n  return pfirst(a);\n}\n\ntemplate<int Offset>\nstruct palign_impl<Offset,Packet1cd>\n{\n  static EIGEN_STRONG_INLINE void run(Packet1cd& /*first*/, const Packet1cd& /*second*/)\n  {\n    // FIXME is it sure we never have to align a Packet1cd?\n    // Even though a std::complex<double> has 16 bytes, it is not necessarily aligned on a 16 bytes boundary...\n  }\n};\n\ntemplate<> struct conj_helper<Packet1cd, Packet1cd, false,true>\n{\n  EIGEN_STRONG_INLINE Packet1cd pmadd(const Packet1cd& x, const Packet1cd& y, const Packet1cd& c) const\n  { return padd(pmul(x,y),c); }\n\n  EIGEN_STRONG_INLINE Packet1cd pmul(const Packet1cd& a, const Packet1cd& b) const\n  {\n    #ifdef EIGEN_VECTORIZE_SSE3\n    return internal::pmul(a, pconj(b));\n    #else\n    const __m128d mask = _mm_castsi128_pd(_mm_set_epi32(0x80000000,0x0,0x0,0x0));\n    return Packet1cd(_mm_add_pd(_mm_xor_pd(_mm_mul_pd(vec2d_swizzle1(a.v, 0, 0), b.v), mask),\n                                _mm_mul_pd(vec2d_swizzle1(a.v, 1, 1),\n                                           vec2d_swizzle1(b.v, 1, 0))));\n    #endif\n  }\n};\n\ntemplate<> struct conj_helper<Packet1cd, Packet1cd, true,false>\n{\n  EIGEN_STRONG_INLINE Packet1cd pmadd(const Packet1cd& x, const Packet1cd& y, const Packet1cd& c) const\n  { return padd(pmul(x,y),c); }\n\n  EIGEN_STRONG_INLINE Packet1cd pmul(const Packet1cd& a, const Packet1cd& b) const\n  {\n    #ifdef EIGEN_VECTORIZE_SSE3\n    return internal::pmul(pconj(a), b);\n    #else\n    const __m128d mask = _mm_castsi128_pd(_mm_set_epi32(0x80000000,0x0,0x0,0x0));\n    return Packet1cd(_mm_add_pd(_mm_mul_pd(vec2d_swizzle1(a.v, 0, 0), b.v),\n                                _mm_xor_pd(_mm_mul_pd(vec2d_swizzle1(a.v, 1, 1),\n                                                      vec2d_swizzle1(b.v, 1, 0)), mask)));\n    #endif\n  }\n};\n\ntemplate<> struct conj_helper<Packet1cd, Packet1cd, true,true>\n{\n  EIGEN_STRONG_INLINE Packet1cd pmadd(const Packet1cd& x, const Packet1cd& y, const Packet1cd& c) const\n  { return padd(pmul(x,y),c); }\n\n  EIGEN_STRONG_INLINE Packet1cd pmul(const Packet1cd& a, const Packet1cd& b) const\n  {\n    #ifdef EIGEN_VECTORIZE_SSE3\n    return pconj(internal::pmul(a, b));\n    #else\n    const __m128d mask = _mm_castsi128_pd(_mm_set_epi32(0x80000000,0x0,0x0,0x0));\n    return Packet1cd(_mm_sub_pd(_mm_xor_pd(_mm_mul_pd(vec2d_swizzle1(a.v, 0, 0), b.v), mask),\n                                _mm_mul_pd(vec2d_swizzle1(a.v, 1, 1),\n                                           vec2d_swizzle1(b.v, 1, 0))));\n    #endif\n  }\n};\n\ntemplate<> struct conj_helper<Packet2d, Packet1cd, false,false>\n{\n  EIGEN_STRONG_INLINE Packet1cd pmadd(const Packet2d& x, const Packet1cd& y, const Packet1cd& c) const\n  { return padd(c, pmul(x,y)); }\n\n  EIGEN_STRONG_INLINE Packet1cd pmul(const Packet2d& x, const Packet1cd& y) const\n  { return Packet1cd(Eigen::internal::pmul<Packet2d>(x, y.v)); }\n};\n\ntemplate<> struct conj_helper<Packet1cd, Packet2d, false,false>\n{\n  EIGEN_STRONG_INLINE Packet1cd pmadd(const Packet1cd& x, const Packet2d& y, const Packet1cd& c) const\n  { return padd(c, pmul(x,y)); }\n\n  EIGEN_STRONG_INLINE Packet1cd pmul(const Packet1cd& x, const Packet2d& y) const\n  { return Packet1cd(Eigen::internal::pmul<Packet2d>(x.v, y)); }\n};\n\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pdiv<Packet1cd>(const Packet1cd& a, const Packet1cd& b)\n{\n  // TODO optimize it for SSE3 and 4\n  Packet1cd res = conj_helper<Packet1cd,Packet1cd,false,true>().pmul(a,b);\n  __m128d s = _mm_mul_pd(b.v,b.v);\n  return Packet1cd(_mm_div_pd(res.v, _mm_add_pd(s,_mm_shuffle_pd(s, s, 0x1))));\n}\n\nEIGEN_STRONG_INLINE Packet1cd pcplxflip/* <Packet1cd> */(const Packet1cd& x)\n{\n  return Packet1cd(preverse(Packet2d(x.v)));\n}\n\nEIGEN_DEVICE_FUNC inline void\nptranspose(PacketBlock<Packet2cf,2>& kernel) {\n  __m128d w1 = _mm_castps_pd(kernel.packet[0].v);\n  __m128d w2 = _mm_castps_pd(kernel.packet[1].v);\n\n  __m128 tmp = _mm_castpd_ps(_mm_unpackhi_pd(w1, w2));\n  kernel.packet[0].v = _mm_castpd_ps(_mm_unpacklo_pd(w1, w2));\n  kernel.packet[1].v = tmp;\n}\n\ntemplate<>  EIGEN_STRONG_INLINE Packet2cf pblend(const Selector<2>& ifPacket, const Packet2cf& thenPacket, const Packet2cf& elsePacket) {\n  __m128d result = pblend<Packet2d>(ifPacket, _mm_castps_pd(thenPacket.v), _mm_castps_pd(elsePacket.v));\n  return Packet2cf(_mm_castpd_ps(result));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pinsertfirst(const Packet2cf& a, std::complex<float> b)\n{\n  return Packet2cf(_mm_loadl_pi(a.v, reinterpret_cast<const __m64*>(&b)));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pinsertfirst(const Packet1cd&, std::complex<double> b)\n{\n  return pset1<Packet1cd>(b);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pinsertlast(const Packet2cf& a, std::complex<float> b)\n{\n  return Packet2cf(_mm_loadh_pi(a.v, reinterpret_cast<const __m64*>(&b)));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pinsertlast(const Packet1cd&, std::complex<double> b)\n{\n  return pset1<Packet1cd>(b);\n}\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_COMPLEX_SSE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/arch/SSE/MathFunctions.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2007 Julien Pommier\n// Copyright (C) 2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n/* The sin, cos, exp, and log functions of this file come from\n * Julien Pommier's sse math library: http://gruntthepeon.free.fr/ssemath/\n */\n\n#ifndef EIGEN_MATH_FUNCTIONS_SSE_H\n#define EIGEN_MATH_FUNCTIONS_SSE_H\n\nnamespace Eigen {\n\nnamespace internal {\n\ntemplate<> EIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED\nPacket4f plog<Packet4f>(const Packet4f& _x)\n{\n  Packet4f x = _x;\n  _EIGEN_DECLARE_CONST_Packet4f(1 , 1.0f);\n  _EIGEN_DECLARE_CONST_Packet4f(half, 0.5f);\n  _EIGEN_DECLARE_CONST_Packet4i(0x7f, 0x7f);\n\n  _EIGEN_DECLARE_CONST_Packet4f_FROM_INT(inv_mant_mask, ~0x7f800000);\n\n  /* the smallest non denormalized float number */\n  _EIGEN_DECLARE_CONST_Packet4f_FROM_INT(min_norm_pos,  0x00800000);\n  _EIGEN_DECLARE_CONST_Packet4f_FROM_INT(minus_inf,     0xff800000);//-1.f/0.f);\n\n  /* natural logarithm computed for 4 simultaneous float\n    return NaN for x <= 0\n  */\n  _EIGEN_DECLARE_CONST_Packet4f(cephes_SQRTHF, 0.707106781186547524f);\n  _EIGEN_DECLARE_CONST_Packet4f(cephes_log_p0, 7.0376836292E-2f);\n  _EIGEN_DECLARE_CONST_Packet4f(cephes_log_p1, - 1.1514610310E-1f);\n  _EIGEN_DECLARE_CONST_Packet4f(cephes_log_p2, 1.1676998740E-1f);\n  _EIGEN_DECLARE_CONST_Packet4f(cephes_log_p3, - 1.2420140846E-1f);\n  _EIGEN_DECLARE_CONST_Packet4f(cephes_log_p4, + 1.4249322787E-1f);\n  _EIGEN_DECLARE_CONST_Packet4f(cephes_log_p5, - 1.6668057665E-1f);\n  _EIGEN_DECLARE_CONST_Packet4f(cephes_log_p6, + 2.0000714765E-1f);\n  _EIGEN_DECLARE_CONST_Packet4f(cephes_log_p7, - 2.4999993993E-1f);\n  _EIGEN_DECLARE_CONST_Packet4f(cephes_log_p8, + 3.3333331174E-1f);\n  _EIGEN_DECLARE_CONST_Packet4f(cephes_log_q1, -2.12194440e-4f);\n  _EIGEN_DECLARE_CONST_Packet4f(cephes_log_q2, 0.693359375f);\n\n\n  Packet4i emm0;\n\n  Packet4f invalid_mask = _mm_cmpnge_ps(x, _mm_setzero_ps()); // not greater equal is true if x is NaN\n  Packet4f iszero_mask = _mm_cmpeq_ps(x, _mm_setzero_ps());\n\n  x = pmax(x, p4f_min_norm_pos);  /* cut off denormalized stuff */\n  emm0 = _mm_srli_epi32(_mm_castps_si128(x), 23);\n\n  /* keep only the fractional part */\n  x = _mm_and_ps(x, p4f_inv_mant_mask);\n  x = _mm_or_ps(x, p4f_half);\n\n  emm0 = _mm_sub_epi32(emm0, p4i_0x7f);\n  Packet4f e = padd(Packet4f(_mm_cvtepi32_ps(emm0)), p4f_1);\n\n  /* part2:\n     if( x < SQRTHF ) {\n       e -= 1;\n       x = x + x - 1.0;\n     } else { x = x - 1.0; }\n  */\n  Packet4f mask = _mm_cmplt_ps(x, p4f_cephes_SQRTHF);\n  Packet4f tmp = pand(x, mask);\n  x = psub(x, p4f_1);\n  e = psub(e, pand(p4f_1, mask));\n  x = padd(x, tmp);\n\n  Packet4f x2 = pmul(x,x);\n  Packet4f x3 = pmul(x2,x);\n\n  Packet4f y, y1, y2;\n  y  = pmadd(p4f_cephes_log_p0, x, p4f_cephes_log_p1);\n  y1 = pmadd(p4f_cephes_log_p3, x, p4f_cephes_log_p4);\n  y2 = pmadd(p4f_cephes_log_p6, x, p4f_cephes_log_p7);\n  y  = pmadd(y , x, p4f_cephes_log_p2);\n  y1 = pmadd(y1, x, p4f_cephes_log_p5);\n  y2 = pmadd(y2, x, p4f_cephes_log_p8);\n  y = pmadd(y, x3, y1);\n  y = pmadd(y, x3, y2);\n  y = pmul(y, x3);\n\n  y1 = pmul(e, p4f_cephes_log_q1);\n  tmp = pmul(x2, p4f_half);\n  y = padd(y, y1);\n  x = psub(x, tmp);\n  y2 = pmul(e, p4f_cephes_log_q2);\n  x = padd(x, y);\n  x = padd(x, y2);\n  // negative arg will be NAN, 0 will be -INF\n  return _mm_or_ps(_mm_andnot_ps(iszero_mask, _mm_or_ps(x, invalid_mask)),\n                   _mm_and_ps(iszero_mask, p4f_minus_inf));\n}\n\ntemplate<> EIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED\nPacket4f pexp<Packet4f>(const Packet4f& _x)\n{\n  Packet4f x = _x;\n  _EIGEN_DECLARE_CONST_Packet4f(1 , 1.0f);\n  _EIGEN_DECLARE_CONST_Packet4f(half, 0.5f);\n  _EIGEN_DECLARE_CONST_Packet4i(0x7f, 0x7f);\n\n\n  _EIGEN_DECLARE_CONST_Packet4f(exp_hi,  88.3762626647950f);\n  _EIGEN_DECLARE_CONST_Packet4f(exp_lo, -88.3762626647949f);\n\n  _EIGEN_DECLARE_CONST_Packet4f(cephes_LOG2EF, 1.44269504088896341f);\n  _EIGEN_DECLARE_CONST_Packet4f(cephes_exp_C1, 0.693359375f);\n  _EIGEN_DECLARE_CONST_Packet4f(cephes_exp_C2, -2.12194440e-4f);\n\n  _EIGEN_DECLARE_CONST_Packet4f(cephes_exp_p0, 1.9875691500E-4f);\n  _EIGEN_DECLARE_CONST_Packet4f(cephes_exp_p1, 1.3981999507E-3f);\n  _EIGEN_DECLARE_CONST_Packet4f(cephes_exp_p2, 8.3334519073E-3f);\n  _EIGEN_DECLARE_CONST_Packet4f(cephes_exp_p3, 4.1665795894E-2f);\n  _EIGEN_DECLARE_CONST_Packet4f(cephes_exp_p4, 1.6666665459E-1f);\n  _EIGEN_DECLARE_CONST_Packet4f(cephes_exp_p5, 5.0000001201E-1f);\n\n  Packet4f tmp, fx;\n  Packet4i emm0;\n\n  // clamp x\n  x = pmax(pmin(x, p4f_exp_hi), p4f_exp_lo);\n\n  /* express exp(x) as exp(g + n*log(2)) */\n  fx = pmadd(x, p4f_cephes_LOG2EF, p4f_half);\n\n#ifdef EIGEN_VECTORIZE_SSE4_1\n  fx = _mm_floor_ps(fx);\n#else\n  emm0 = _mm_cvttps_epi32(fx);\n  tmp  = _mm_cvtepi32_ps(emm0);\n  /* if greater, substract 1 */\n  Packet4f mask = _mm_cmpgt_ps(tmp, fx);\n  mask = _mm_and_ps(mask, p4f_1);\n  fx = psub(tmp, mask);\n#endif\n\n  tmp = pmul(fx, p4f_cephes_exp_C1);\n  Packet4f z = pmul(fx, p4f_cephes_exp_C2);\n  x = psub(x, tmp);\n  x = psub(x, z);\n\n  z = pmul(x,x);\n\n  Packet4f y = p4f_cephes_exp_p0;\n  y = pmadd(y, x, p4f_cephes_exp_p1);\n  y = pmadd(y, x, p4f_cephes_exp_p2);\n  y = pmadd(y, x, p4f_cephes_exp_p3);\n  y = pmadd(y, x, p4f_cephes_exp_p4);\n  y = pmadd(y, x, p4f_cephes_exp_p5);\n  y = pmadd(y, z, x);\n  y = padd(y, p4f_1);\n\n  // build 2^n\n  emm0 = _mm_cvttps_epi32(fx);\n  emm0 = _mm_add_epi32(emm0, p4i_0x7f);\n  emm0 = _mm_slli_epi32(emm0, 23);\n  return pmax(pmul(y, Packet4f(_mm_castsi128_ps(emm0))), _x);\n}\ntemplate<> EIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED\nPacket2d pexp<Packet2d>(const Packet2d& _x)\n{\n  Packet2d x = _x;\n\n  _EIGEN_DECLARE_CONST_Packet2d(1 , 1.0);\n  _EIGEN_DECLARE_CONST_Packet2d(2 , 2.0);\n  _EIGEN_DECLARE_CONST_Packet2d(half, 0.5);\n\n  _EIGEN_DECLARE_CONST_Packet2d(exp_hi,  709.437);\n  _EIGEN_DECLARE_CONST_Packet2d(exp_lo, -709.436139303);\n\n  _EIGEN_DECLARE_CONST_Packet2d(cephes_LOG2EF, 1.4426950408889634073599);\n\n  _EIGEN_DECLARE_CONST_Packet2d(cephes_exp_p0, 1.26177193074810590878e-4);\n  _EIGEN_DECLARE_CONST_Packet2d(cephes_exp_p1, 3.02994407707441961300e-2);\n  _EIGEN_DECLARE_CONST_Packet2d(cephes_exp_p2, 9.99999999999999999910e-1);\n\n  _EIGEN_DECLARE_CONST_Packet2d(cephes_exp_q0, 3.00198505138664455042e-6);\n  _EIGEN_DECLARE_CONST_Packet2d(cephes_exp_q1, 2.52448340349684104192e-3);\n  _EIGEN_DECLARE_CONST_Packet2d(cephes_exp_q2, 2.27265548208155028766e-1);\n  _EIGEN_DECLARE_CONST_Packet2d(cephes_exp_q3, 2.00000000000000000009e0);\n\n  _EIGEN_DECLARE_CONST_Packet2d(cephes_exp_C1, 0.693145751953125);\n  _EIGEN_DECLARE_CONST_Packet2d(cephes_exp_C2, 1.42860682030941723212e-6);\n  static const __m128i p4i_1023_0 = _mm_setr_epi32(1023, 1023, 0, 0);\n\n  Packet2d tmp, fx;\n  Packet4i emm0;\n\n  // clamp x\n  x = pmax(pmin(x, p2d_exp_hi), p2d_exp_lo);\n  /* express exp(x) as exp(g + n*log(2)) */\n  fx = pmadd(p2d_cephes_LOG2EF, x, p2d_half);\n\n#ifdef EIGEN_VECTORIZE_SSE4_1\n  fx = _mm_floor_pd(fx);\n#else\n  emm0 = _mm_cvttpd_epi32(fx);\n  tmp  = _mm_cvtepi32_pd(emm0);\n  /* if greater, substract 1 */\n  Packet2d mask = _mm_cmpgt_pd(tmp, fx);\n  mask = _mm_and_pd(mask, p2d_1);\n  fx = psub(tmp, mask);\n#endif\n\n  tmp = pmul(fx, p2d_cephes_exp_C1);\n  Packet2d z = pmul(fx, p2d_cephes_exp_C2);\n  x = psub(x, tmp);\n  x = psub(x, z);\n\n  Packet2d x2 = pmul(x,x);\n\n  Packet2d px = p2d_cephes_exp_p0;\n  px = pmadd(px, x2, p2d_cephes_exp_p1);\n  px = pmadd(px, x2, p2d_cephes_exp_p2);\n  px = pmul (px, x);\n\n  Packet2d qx = p2d_cephes_exp_q0;\n  qx = pmadd(qx, x2, p2d_cephes_exp_q1);\n  qx = pmadd(qx, x2, p2d_cephes_exp_q2);\n  qx = pmadd(qx, x2, p2d_cephes_exp_q3);\n\n  x = pdiv(px,psub(qx,px));\n  x = pmadd(p2d_2,x,p2d_1);\n\n  // build 2^n\n  emm0 = _mm_cvttpd_epi32(fx);\n  emm0 = _mm_add_epi32(emm0, p4i_1023_0);\n  emm0 = _mm_slli_epi32(emm0, 20);\n  emm0 = _mm_shuffle_epi32(emm0, _MM_SHUFFLE(1,2,0,3));\n  return pmax(pmul(x, Packet2d(_mm_castsi128_pd(emm0))), _x);\n}\n\n/* evaluation of 4 sines at onces, using SSE2 intrinsics.\n\n   The code is the exact rewriting of the cephes sinf function.\n   Precision is excellent as long as x < 8192 (I did not bother to\n   take into account the special handling they have for greater values\n   -- it does not return garbage for arguments over 8192, though, but\n   the extra precision is missing).\n\n   Note that it is such that sinf((float)M_PI) = 8.74e-8, which is the\n   surprising but correct result.\n*/\n\ntemplate<> EIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED\nPacket4f psin<Packet4f>(const Packet4f& _x)\n{\n  Packet4f x = _x;\n  _EIGEN_DECLARE_CONST_Packet4f(1 , 1.0f);\n  _EIGEN_DECLARE_CONST_Packet4f(half, 0.5f);\n\n  _EIGEN_DECLARE_CONST_Packet4i(1, 1);\n  _EIGEN_DECLARE_CONST_Packet4i(not1, ~1);\n  _EIGEN_DECLARE_CONST_Packet4i(2, 2);\n  _EIGEN_DECLARE_CONST_Packet4i(4, 4);\n\n  _EIGEN_DECLARE_CONST_Packet4f_FROM_INT(sign_mask, 0x80000000);\n\n  _EIGEN_DECLARE_CONST_Packet4f(minus_cephes_DP1,-0.78515625f);\n  _EIGEN_DECLARE_CONST_Packet4f(minus_cephes_DP2, -2.4187564849853515625e-4f);\n  _EIGEN_DECLARE_CONST_Packet4f(minus_cephes_DP3, -3.77489497744594108e-8f);\n  _EIGEN_DECLARE_CONST_Packet4f(sincof_p0, -1.9515295891E-4f);\n  _EIGEN_DECLARE_CONST_Packet4f(sincof_p1,  8.3321608736E-3f);\n  _EIGEN_DECLARE_CONST_Packet4f(sincof_p2, -1.6666654611E-1f);\n  _EIGEN_DECLARE_CONST_Packet4f(coscof_p0,  2.443315711809948E-005f);\n  _EIGEN_DECLARE_CONST_Packet4f(coscof_p1, -1.388731625493765E-003f);\n  _EIGEN_DECLARE_CONST_Packet4f(coscof_p2,  4.166664568298827E-002f);\n  _EIGEN_DECLARE_CONST_Packet4f(cephes_FOPI, 1.27323954473516f); // 4 / M_PI\n\n  Packet4f xmm1, xmm2, xmm3, sign_bit, y;\n\n  Packet4i emm0, emm2;\n  sign_bit = x;\n  /* take the absolute value */\n  x = pabs(x);\n\n  /* take the modulo */\n\n  /* extract the sign bit (upper one) */\n  sign_bit = _mm_and_ps(sign_bit, p4f_sign_mask);\n\n  /* scale by 4/Pi */\n  y = pmul(x, p4f_cephes_FOPI);\n\n  /* store the integer part of y in mm0 */\n  emm2 = _mm_cvttps_epi32(y);\n  /* j=(j+1) & (~1) (see the cephes sources) */\n  emm2 = _mm_add_epi32(emm2, p4i_1);\n  emm2 = _mm_and_si128(emm2, p4i_not1);\n  y = _mm_cvtepi32_ps(emm2);\n  /* get the swap sign flag */\n  emm0 = _mm_and_si128(emm2, p4i_4);\n  emm0 = _mm_slli_epi32(emm0, 29);\n  /* get the polynom selection mask\n     there is one polynom for 0 <= x <= Pi/4\n     and another one for Pi/4<x<=Pi/2\n\n     Both branches will be computed.\n  */\n  emm2 = _mm_and_si128(emm2, p4i_2);\n  emm2 = _mm_cmpeq_epi32(emm2, _mm_setzero_si128());\n\n  Packet4f swap_sign_bit = _mm_castsi128_ps(emm0);\n  Packet4f poly_mask = _mm_castsi128_ps(emm2);\n  sign_bit = _mm_xor_ps(sign_bit, swap_sign_bit);\n\n  /* The magic pass: \"Extended precision modular arithmetic\"\n     x = ((x - y * DP1) - y * DP2) - y * DP3; */\n  xmm1 = pmul(y, p4f_minus_cephes_DP1);\n  xmm2 = pmul(y, p4f_minus_cephes_DP2);\n  xmm3 = pmul(y, p4f_minus_cephes_DP3);\n  x = padd(x, xmm1);\n  x = padd(x, xmm2);\n  x = padd(x, xmm3);\n\n  /* Evaluate the first polynom  (0 <= x <= Pi/4) */\n  y = p4f_coscof_p0;\n  Packet4f z = _mm_mul_ps(x,x);\n\n  y = pmadd(y, z, p4f_coscof_p1);\n  y = pmadd(y, z, p4f_coscof_p2);\n  y = pmul(y, z);\n  y = pmul(y, z);\n  Packet4f tmp = pmul(z, p4f_half);\n  y = psub(y, tmp);\n  y = padd(y, p4f_1);\n\n  /* Evaluate the second polynom  (Pi/4 <= x <= 0) */\n\n  Packet4f y2 = p4f_sincof_p0;\n  y2 = pmadd(y2, z, p4f_sincof_p1);\n  y2 = pmadd(y2, z, p4f_sincof_p2);\n  y2 = pmul(y2, z);\n  y2 = pmul(y2, x);\n  y2 = padd(y2, x);\n\n  /* select the correct result from the two polynoms */\n  y2 = _mm_and_ps(poly_mask, y2);\n  y = _mm_andnot_ps(poly_mask, y);\n  y = _mm_or_ps(y,y2);\n  /* update the sign */\n  return _mm_xor_ps(y, sign_bit);\n}\n\n/* almost the same as psin */\ntemplate<> EIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED\nPacket4f pcos<Packet4f>(const Packet4f& _x)\n{\n  Packet4f x = _x;\n  _EIGEN_DECLARE_CONST_Packet4f(1 , 1.0f);\n  _EIGEN_DECLARE_CONST_Packet4f(half, 0.5f);\n\n  _EIGEN_DECLARE_CONST_Packet4i(1, 1);\n  _EIGEN_DECLARE_CONST_Packet4i(not1, ~1);\n  _EIGEN_DECLARE_CONST_Packet4i(2, 2);\n  _EIGEN_DECLARE_CONST_Packet4i(4, 4);\n\n  _EIGEN_DECLARE_CONST_Packet4f(minus_cephes_DP1,-0.78515625f);\n  _EIGEN_DECLARE_CONST_Packet4f(minus_cephes_DP2, -2.4187564849853515625e-4f);\n  _EIGEN_DECLARE_CONST_Packet4f(minus_cephes_DP3, -3.77489497744594108e-8f);\n  _EIGEN_DECLARE_CONST_Packet4f(sincof_p0, -1.9515295891E-4f);\n  _EIGEN_DECLARE_CONST_Packet4f(sincof_p1,  8.3321608736E-3f);\n  _EIGEN_DECLARE_CONST_Packet4f(sincof_p2, -1.6666654611E-1f);\n  _EIGEN_DECLARE_CONST_Packet4f(coscof_p0,  2.443315711809948E-005f);\n  _EIGEN_DECLARE_CONST_Packet4f(coscof_p1, -1.388731625493765E-003f);\n  _EIGEN_DECLARE_CONST_Packet4f(coscof_p2,  4.166664568298827E-002f);\n  _EIGEN_DECLARE_CONST_Packet4f(cephes_FOPI, 1.27323954473516f); // 4 / M_PI\n\n  Packet4f xmm1, xmm2, xmm3, y;\n  Packet4i emm0, emm2;\n\n  x = pabs(x);\n\n  /* scale by 4/Pi */\n  y = pmul(x, p4f_cephes_FOPI);\n\n  /* get the integer part of y */\n  emm2 = _mm_cvttps_epi32(y);\n  /* j=(j+1) & (~1) (see the cephes sources) */\n  emm2 = _mm_add_epi32(emm2, p4i_1);\n  emm2 = _mm_and_si128(emm2, p4i_not1);\n  y = _mm_cvtepi32_ps(emm2);\n\n  emm2 = _mm_sub_epi32(emm2, p4i_2);\n\n  /* get the swap sign flag */\n  emm0 = _mm_andnot_si128(emm2, p4i_4);\n  emm0 = _mm_slli_epi32(emm0, 29);\n  /* get the polynom selection mask */\n  emm2 = _mm_and_si128(emm2, p4i_2);\n  emm2 = _mm_cmpeq_epi32(emm2, _mm_setzero_si128());\n\n  Packet4f sign_bit = _mm_castsi128_ps(emm0);\n  Packet4f poly_mask = _mm_castsi128_ps(emm2);\n\n  /* The magic pass: \"Extended precision modular arithmetic\"\n     x = ((x - y * DP1) - y * DP2) - y * DP3; */\n  xmm1 = pmul(y, p4f_minus_cephes_DP1);\n  xmm2 = pmul(y, p4f_minus_cephes_DP2);\n  xmm3 = pmul(y, p4f_minus_cephes_DP3);\n  x = padd(x, xmm1);\n  x = padd(x, xmm2);\n  x = padd(x, xmm3);\n\n  /* Evaluate the first polynom  (0 <= x <= Pi/4) */\n  y = p4f_coscof_p0;\n  Packet4f z = pmul(x,x);\n\n  y = pmadd(y,z,p4f_coscof_p1);\n  y = pmadd(y,z,p4f_coscof_p2);\n  y = pmul(y, z);\n  y = pmul(y, z);\n  Packet4f tmp = _mm_mul_ps(z, p4f_half);\n  y = psub(y, tmp);\n  y = padd(y, p4f_1);\n\n  /* Evaluate the second polynom  (Pi/4 <= x <= 0) */\n  Packet4f y2 = p4f_sincof_p0;\n  y2 = pmadd(y2, z, p4f_sincof_p1);\n  y2 = pmadd(y2, z, p4f_sincof_p2);\n  y2 = pmul(y2, z);\n  y2 = pmadd(y2, x, x);\n\n  /* select the correct result from the two polynoms */\n  y2 = _mm_and_ps(poly_mask, y2);\n  y  = _mm_andnot_ps(poly_mask, y);\n  y  = _mm_or_ps(y,y2);\n\n  /* update the sign */\n  return _mm_xor_ps(y, sign_bit);\n}\n\n#if EIGEN_FAST_MATH\n\n// Functions for sqrt.\n// The EIGEN_FAST_MATH version uses the _mm_rsqrt_ps approximation and one step\n// of Newton's method, at a cost of 1-2 bits of precision as opposed to the\n// exact solution. It does not handle +inf, or denormalized numbers correctly.\n// The main advantage of this approach is not just speed, but also the fact that\n// it can be inlined and pipelined with other computations, further reducing its\n// effective latency. This is similar to Quake3's fast inverse square root.\n// For detail see here: http://www.beyond3d.com/content/articles/8/\ntemplate<> EIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED\nPacket4f psqrt<Packet4f>(const Packet4f& _x)\n{\n  Packet4f half = pmul(_x, pset1<Packet4f>(.5f));\n  Packet4f denormal_mask = _mm_and_ps(\n      _mm_cmpge_ps(_x, _mm_setzero_ps()),\n      _mm_cmplt_ps(_x, pset1<Packet4f>((std::numeric_limits<float>::min)())));\n\n  // Compute approximate reciprocal sqrt.\n  Packet4f x = _mm_rsqrt_ps(_x);\n  // Do a single step of Newton's iteration.\n  x = pmul(x, psub(pset1<Packet4f>(1.5f), pmul(half, pmul(x,x))));\n  // Flush results for denormals to zero.\n  return _mm_andnot_ps(denormal_mask, pmul(_x,x));\n}\n\n#else\n\ntemplate<>EIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED\nPacket4f psqrt<Packet4f>(const Packet4f& x) { return _mm_sqrt_ps(x); }\n\n#endif\n\ntemplate<> EIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED\nPacket2d psqrt<Packet2d>(const Packet2d& x) { return _mm_sqrt_pd(x); }\n\n#if EIGEN_FAST_MATH\n\ntemplate<> EIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED\nPacket4f prsqrt<Packet4f>(const Packet4f& _x) {\n  _EIGEN_DECLARE_CONST_Packet4f_FROM_INT(inf, 0x7f800000);\n  _EIGEN_DECLARE_CONST_Packet4f_FROM_INT(nan, 0x7fc00000);\n  _EIGEN_DECLARE_CONST_Packet4f(one_point_five, 1.5f);\n  _EIGEN_DECLARE_CONST_Packet4f(minus_half, -0.5f);\n  _EIGEN_DECLARE_CONST_Packet4f_FROM_INT(flt_min, 0x00800000);\n\n  Packet4f neg_half = pmul(_x, p4f_minus_half);\n\n  // select only the inverse sqrt of positive normal inputs (denormals are\n  // flushed to zero and cause infs as well).\n  Packet4f le_zero_mask = _mm_cmple_ps(_x, p4f_flt_min);\n  Packet4f x = _mm_andnot_ps(le_zero_mask, _mm_rsqrt_ps(_x));\n\n  // Fill in NaNs and Infs for the negative/zero entries.\n  Packet4f neg_mask = _mm_cmplt_ps(_x, _mm_setzero_ps());\n  Packet4f zero_mask = _mm_andnot_ps(neg_mask, le_zero_mask);\n  Packet4f infs_and_nans = _mm_or_ps(_mm_and_ps(neg_mask, p4f_nan),\n                                     _mm_and_ps(zero_mask, p4f_inf));\n\n  // Do a single step of Newton's iteration.\n  x = pmul(x, pmadd(neg_half, pmul(x, x), p4f_one_point_five));\n\n  // Insert NaNs and Infs in all the right places.\n  return _mm_or_ps(x, infs_and_nans);\n}\n\n#else\n\ntemplate<> EIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED\nPacket4f prsqrt<Packet4f>(const Packet4f& x) {\n  // Unfortunately we can't use the much faster mm_rqsrt_ps since it only provides an approximation.\n  return _mm_div_ps(pset1<Packet4f>(1.0f), _mm_sqrt_ps(x));\n}\n\n#endif\n\ntemplate<> EIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED\nPacket2d prsqrt<Packet2d>(const Packet2d& x) {\n  // Unfortunately we can't use the much faster mm_rqsrt_pd since it only provides an approximation.\n  return _mm_div_pd(pset1<Packet2d>(1.0), _mm_sqrt_pd(x));\n}\n\n// Hyperbolic Tangent function.\ntemplate <>\nEIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED Packet4f\nptanh<Packet4f>(const Packet4f& x) {\n  return internal::generic_fast_tanh_float(x);\n}\n\n} // end namespace internal\n\nnamespace numext {\n\ntemplate<>\nEIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\nfloat sqrt(const float &x)\n{\n  return internal::pfirst(internal::Packet4f(_mm_sqrt_ss(_mm_set_ss(x))));\n}\n\ntemplate<>\nEIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE\ndouble sqrt(const double &x)\n{\n#if EIGEN_COMP_GNUC_STRICT\n  // This works around a GCC bug generating poor code for _mm_sqrt_pd\n  // See https://bitbucket.org/eigen/eigen/commits/14f468dba4d350d7c19c9b93072e19f7b3df563b\n  return internal::pfirst(internal::Packet2d(__builtin_ia32_sqrtsd(_mm_set_sd(x))));\n#else\n  return internal::pfirst(internal::Packet2d(_mm_sqrt_pd(_mm_set_sd(x))));\n#endif\n}\n\n} // end namespace numex\n\n} // end namespace Eigen\n\n#endif // EIGEN_MATH_FUNCTIONS_SSE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/arch/SSE/PacketMath.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_PACKET_MATH_SSE_H\n#define EIGEN_PACKET_MATH_SSE_H\n\nnamespace Eigen {\n\nnamespace internal {\n\n#ifndef EIGEN_CACHEFRIENDLY_PRODUCT_THRESHOLD\n#define EIGEN_CACHEFRIENDLY_PRODUCT_THRESHOLD 8\n#endif\n\n#ifndef EIGEN_ARCH_DEFAULT_NUMBER_OF_REGISTERS\n#define EIGEN_ARCH_DEFAULT_NUMBER_OF_REGISTERS (2*sizeof(void*))\n#endif\n\n#ifdef __FMA__\n#ifndef EIGEN_HAS_SINGLE_INSTRUCTION_MADD\n#define EIGEN_HAS_SINGLE_INSTRUCTION_MADD 1\n#endif\n#endif\n\n#if (defined EIGEN_VECTORIZE_AVX) && EIGEN_COMP_GNUC_STRICT && (__GXX_ABI_VERSION < 1004)\n// With GCC's default ABI version, a __m128 or __m256 are the same types and therefore we cannot\n// have overloads for both types without linking error.\n// One solution is to increase ABI version using -fabi-version=4 (or greater).\n// Otherwise, we workaround this inconvenience by wrapping 128bit types into the following helper\n// structure:\ntemplate<typename T>\nstruct eigen_packet_wrapper\n{\n  EIGEN_ALWAYS_INLINE operator T&() { return m_val; }\n  EIGEN_ALWAYS_INLINE operator const T&() const { return m_val; }\n  EIGEN_ALWAYS_INLINE eigen_packet_wrapper() {}\n  EIGEN_ALWAYS_INLINE eigen_packet_wrapper(const T &v) : m_val(v) {}\n  EIGEN_ALWAYS_INLINE eigen_packet_wrapper& operator=(const T &v) {\n    m_val = v;\n    return *this;\n  }\n  \n  T m_val;\n};\ntypedef eigen_packet_wrapper<__m128>  Packet4f;\ntypedef eigen_packet_wrapper<__m128i> Packet4i;\ntypedef eigen_packet_wrapper<__m128d> Packet2d;\n#else\ntypedef __m128  Packet4f;\ntypedef __m128i Packet4i;\ntypedef __m128d Packet2d;\n#endif\n\ntemplate<> struct is_arithmetic<__m128>  { enum { value = true }; };\ntemplate<> struct is_arithmetic<__m128i> { enum { value = true }; };\ntemplate<> struct is_arithmetic<__m128d> { enum { value = true }; };\n\n#define vec4f_swizzle1(v,p,q,r,s) \\\n  (_mm_castsi128_ps(_mm_shuffle_epi32( _mm_castps_si128(v), ((s)<<6|(r)<<4|(q)<<2|(p)))))\n\n#define vec4i_swizzle1(v,p,q,r,s) \\\n  (_mm_shuffle_epi32( v, ((s)<<6|(r)<<4|(q)<<2|(p))))\n\n#define vec2d_swizzle1(v,p,q) \\\n  (_mm_castsi128_pd(_mm_shuffle_epi32( _mm_castpd_si128(v), ((q*2+1)<<6|(q*2)<<4|(p*2+1)<<2|(p*2)))))\n  \n#define vec4f_swizzle2(a,b,p,q,r,s) \\\n  (_mm_shuffle_ps( (a), (b), ((s)<<6|(r)<<4|(q)<<2|(p))))\n\n#define vec4i_swizzle2(a,b,p,q,r,s) \\\n  (_mm_castps_si128( (_mm_shuffle_ps( _mm_castsi128_ps(a), _mm_castsi128_ps(b), ((s)<<6|(r)<<4|(q)<<2|(p))))))\n\n#define _EIGEN_DECLARE_CONST_Packet4f(NAME,X) \\\n  const Packet4f p4f_##NAME = pset1<Packet4f>(X)\n\n#define _EIGEN_DECLARE_CONST_Packet2d(NAME,X) \\\n  const Packet2d p2d_##NAME = pset1<Packet2d>(X)\n\n#define _EIGEN_DECLARE_CONST_Packet4f_FROM_INT(NAME,X) \\\n  const Packet4f p4f_##NAME = _mm_castsi128_ps(pset1<Packet4i>(X))\n\n#define _EIGEN_DECLARE_CONST_Packet4i(NAME,X) \\\n  const Packet4i p4i_##NAME = pset1<Packet4i>(X)\n\n\n// Use the packet_traits defined in AVX/PacketMath.h instead if we're going\n// to leverage AVX instructions.\n#ifndef EIGEN_VECTORIZE_AVX\ntemplate<> struct packet_traits<float>  : default_packet_traits\n{\n  typedef Packet4f type;\n  typedef Packet4f half;\n  enum {\n    Vectorizable = 1,\n    AlignedOnScalar = 1,\n    size=4,\n    HasHalfPacket = 0,\n\n    HasDiv  = 1,\n    HasSin  = EIGEN_FAST_MATH,\n    HasCos  = EIGEN_FAST_MATH,\n    HasLog  = 1,\n    HasExp  = 1,\n    HasSqrt = 1,\n    HasRsqrt = 1,\n    HasTanh  = EIGEN_FAST_MATH,\n    HasBlend = 1\n\n#ifdef EIGEN_VECTORIZE_SSE4_1\n    ,\n    HasRound = 1,\n    HasFloor = 1,\n    HasCeil = 1\n#endif\n  };\n};\ntemplate<> struct packet_traits<double> : default_packet_traits\n{\n  typedef Packet2d type;\n  typedef Packet2d half;\n  enum {\n    Vectorizable = 1,\n    AlignedOnScalar = 1,\n    size=2,\n    HasHalfPacket = 0,\n\n    HasDiv  = 1,\n    HasExp  = 1,\n    HasSqrt = 1,\n    HasRsqrt = 1,\n    HasBlend = 1\n\n#ifdef EIGEN_VECTORIZE_SSE4_1\n    ,\n    HasRound = 1,\n    HasFloor = 1,\n    HasCeil = 1\n#endif\n  };\n};\n#endif\ntemplate<> struct packet_traits<int>    : default_packet_traits\n{\n  typedef Packet4i type;\n  typedef Packet4i half;\n  enum {\n    Vectorizable = 1,\n    AlignedOnScalar = 1,\n    size=4,\n\n    HasBlend = 1\n  };\n};\n\ntemplate<> struct unpacket_traits<Packet4f> { typedef float  type; enum {size=4, alignment=Aligned16}; typedef Packet4f half; };\ntemplate<> struct unpacket_traits<Packet2d> { typedef double type; enum {size=2, alignment=Aligned16}; typedef Packet2d half; };\ntemplate<> struct unpacket_traits<Packet4i> { typedef int    type; enum {size=4, alignment=Aligned16}; typedef Packet4i half; };\n\n#ifndef EIGEN_VECTORIZE_AVX\ntemplate<> struct scalar_div_cost<float,true> { enum { value = 7 }; };\ntemplate<> struct scalar_div_cost<double,true> { enum { value = 8 }; };\n#endif\n\n#if EIGEN_COMP_MSVC==1500\n// Workaround MSVC 9 internal compiler error.\n// TODO: It has been detected with win64 builds (amd64), so let's check whether it also happens in 32bits+SSE mode\n// TODO: let's check whether there does not exist a better fix, like adding a pset0() function. (it crashed on pset1(0)).\ntemplate<> EIGEN_STRONG_INLINE Packet4f pset1<Packet4f>(const float&  from) { return _mm_set_ps(from,from,from,from); }\ntemplate<> EIGEN_STRONG_INLINE Packet2d pset1<Packet2d>(const double& from) { return _mm_set_pd(from,from); }\ntemplate<> EIGEN_STRONG_INLINE Packet4i pset1<Packet4i>(const int&    from) { return _mm_set_epi32(from,from,from,from); }\n#else\ntemplate<> EIGEN_STRONG_INLINE Packet4f pset1<Packet4f>(const float&  from) { return _mm_set_ps1(from); }\ntemplate<> EIGEN_STRONG_INLINE Packet2d pset1<Packet2d>(const double& from) { return _mm_set1_pd(from); }\ntemplate<> EIGEN_STRONG_INLINE Packet4i pset1<Packet4i>(const int&    from) { return _mm_set1_epi32(from); }\n#endif\n\n// GCC generates a shufps instruction for _mm_set1_ps/_mm_load1_ps instead of the more efficient pshufd instruction.\n// However, using inrinsics for pset1 makes gcc to generate crappy code in some cases (see bug 203)\n// Using inline assembly is also not an option because then gcc fails to reorder properly the instructions.\n// Therefore, we introduced the pload1 functions to be used in product kernels for which bug 203 does not apply.\n// Also note that with AVX, we want it to generate a vbroadcastss.\n#if EIGEN_COMP_GNUC_STRICT && (!defined __AVX__)\ntemplate<> EIGEN_STRONG_INLINE Packet4f pload1<Packet4f>(const float *from) {\n  return vec4f_swizzle1(_mm_load_ss(from),0,0,0,0);\n}\n#endif\n  \ntemplate<> EIGEN_STRONG_INLINE Packet4f plset<Packet4f>(const float& a) { return _mm_add_ps(pset1<Packet4f>(a), _mm_set_ps(3,2,1,0)); }\ntemplate<> EIGEN_STRONG_INLINE Packet2d plset<Packet2d>(const double& a) { return _mm_add_pd(pset1<Packet2d>(a),_mm_set_pd(1,0)); }\ntemplate<> EIGEN_STRONG_INLINE Packet4i plset<Packet4i>(const int& a) { return _mm_add_epi32(pset1<Packet4i>(a),_mm_set_epi32(3,2,1,0)); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f padd<Packet4f>(const Packet4f& a, const Packet4f& b) { return _mm_add_ps(a,b); }\ntemplate<> EIGEN_STRONG_INLINE Packet2d padd<Packet2d>(const Packet2d& a, const Packet2d& b) { return _mm_add_pd(a,b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4i padd<Packet4i>(const Packet4i& a, const Packet4i& b) { return _mm_add_epi32(a,b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f psub<Packet4f>(const Packet4f& a, const Packet4f& b) { return _mm_sub_ps(a,b); }\ntemplate<> EIGEN_STRONG_INLINE Packet2d psub<Packet2d>(const Packet2d& a, const Packet2d& b) { return _mm_sub_pd(a,b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4i psub<Packet4i>(const Packet4i& a, const Packet4i& b) { return _mm_sub_epi32(a,b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pnegate(const Packet4f& a)\n{\n  const Packet4f mask = _mm_castsi128_ps(_mm_setr_epi32(0x80000000,0x80000000,0x80000000,0x80000000));\n  return _mm_xor_ps(a,mask);\n}\ntemplate<> EIGEN_STRONG_INLINE Packet2d pnegate(const Packet2d& a)\n{\n  const Packet2d mask = _mm_castsi128_pd(_mm_setr_epi32(0x0,0x80000000,0x0,0x80000000));\n  return _mm_xor_pd(a,mask);\n}\ntemplate<> EIGEN_STRONG_INLINE Packet4i pnegate(const Packet4i& a)\n{\n  return psub(Packet4i(_mm_setr_epi32(0,0,0,0)), a);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pconj(const Packet4f& a) { return a; }\ntemplate<> EIGEN_STRONG_INLINE Packet2d pconj(const Packet2d& a) { return a; }\ntemplate<> EIGEN_STRONG_INLINE Packet4i pconj(const Packet4i& a) { return a; }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pmul<Packet4f>(const Packet4f& a, const Packet4f& b) { return _mm_mul_ps(a,b); }\ntemplate<> EIGEN_STRONG_INLINE Packet2d pmul<Packet2d>(const Packet2d& a, const Packet2d& b) { return _mm_mul_pd(a,b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4i pmul<Packet4i>(const Packet4i& a, const Packet4i& b)\n{\n#ifdef EIGEN_VECTORIZE_SSE4_1\n  return _mm_mullo_epi32(a,b);\n#else\n  // this version is slightly faster than 4 scalar products\n  return vec4i_swizzle1(\n            vec4i_swizzle2(\n              _mm_mul_epu32(a,b),\n              _mm_mul_epu32(vec4i_swizzle1(a,1,0,3,2),\n                            vec4i_swizzle1(b,1,0,3,2)),\n              0,2,0,2),\n            0,2,1,3);\n#endif\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pdiv<Packet4f>(const Packet4f& a, const Packet4f& b) { return _mm_div_ps(a,b); }\ntemplate<> EIGEN_STRONG_INLINE Packet2d pdiv<Packet2d>(const Packet2d& a, const Packet2d& b) { return _mm_div_pd(a,b); }\n\n// for some weird raisons, it has to be overloaded for packet of integers\ntemplate<> EIGEN_STRONG_INLINE Packet4i pmadd(const Packet4i& a, const Packet4i& b, const Packet4i& c) { return padd(pmul(a,b), c); }\n#ifdef __FMA__\ntemplate<> EIGEN_STRONG_INLINE Packet4f pmadd(const Packet4f& a, const Packet4f& b, const Packet4f& c) { return _mm_fmadd_ps(a,b,c); }\ntemplate<> EIGEN_STRONG_INLINE Packet2d pmadd(const Packet2d& a, const Packet2d& b, const Packet2d& c) { return _mm_fmadd_pd(a,b,c); }\n#endif\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pmin<Packet4f>(const Packet4f& a, const Packet4f& b) { return _mm_min_ps(a,b); }\ntemplate<> EIGEN_STRONG_INLINE Packet2d pmin<Packet2d>(const Packet2d& a, const Packet2d& b) { return _mm_min_pd(a,b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4i pmin<Packet4i>(const Packet4i& a, const Packet4i& b)\n{\n#ifdef EIGEN_VECTORIZE_SSE4_1\n  return _mm_min_epi32(a,b);\n#else\n  // after some bench, this version *is* faster than a scalar implementation\n  Packet4i mask = _mm_cmplt_epi32(a,b);\n  return _mm_or_si128(_mm_and_si128(mask,a),_mm_andnot_si128(mask,b));\n#endif\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pmax<Packet4f>(const Packet4f& a, const Packet4f& b) { return _mm_max_ps(a,b); }\ntemplate<> EIGEN_STRONG_INLINE Packet2d pmax<Packet2d>(const Packet2d& a, const Packet2d& b) { return _mm_max_pd(a,b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4i pmax<Packet4i>(const Packet4i& a, const Packet4i& b)\n{\n#ifdef EIGEN_VECTORIZE_SSE4_1\n  return _mm_max_epi32(a,b);\n#else\n  // after some bench, this version *is* faster than a scalar implementation\n  Packet4i mask = _mm_cmpgt_epi32(a,b);\n  return _mm_or_si128(_mm_and_si128(mask,a),_mm_andnot_si128(mask,b));\n#endif\n}\n\n#ifdef EIGEN_VECTORIZE_SSE4_1\ntemplate<> EIGEN_STRONG_INLINE Packet4f pround<Packet4f>(const Packet4f& a) { return _mm_round_ps(a, 0); }\ntemplate<> EIGEN_STRONG_INLINE Packet2d pround<Packet2d>(const Packet2d& a) { return _mm_round_pd(a, 0); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pceil<Packet4f>(const Packet4f& a) { return _mm_ceil_ps(a); }\ntemplate<> EIGEN_STRONG_INLINE Packet2d pceil<Packet2d>(const Packet2d& a) { return _mm_ceil_pd(a); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pfloor<Packet4f>(const Packet4f& a) { return _mm_floor_ps(a); }\ntemplate<> EIGEN_STRONG_INLINE Packet2d pfloor<Packet2d>(const Packet2d& a) { return _mm_floor_pd(a); }\n#endif\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pand<Packet4f>(const Packet4f& a, const Packet4f& b) { return _mm_and_ps(a,b); }\ntemplate<> EIGEN_STRONG_INLINE Packet2d pand<Packet2d>(const Packet2d& a, const Packet2d& b) { return _mm_and_pd(a,b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4i pand<Packet4i>(const Packet4i& a, const Packet4i& b) { return _mm_and_si128(a,b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f por<Packet4f>(const Packet4f& a, const Packet4f& b) { return _mm_or_ps(a,b); }\ntemplate<> EIGEN_STRONG_INLINE Packet2d por<Packet2d>(const Packet2d& a, const Packet2d& b) { return _mm_or_pd(a,b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4i por<Packet4i>(const Packet4i& a, const Packet4i& b) { return _mm_or_si128(a,b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pxor<Packet4f>(const Packet4f& a, const Packet4f& b) { return _mm_xor_ps(a,b); }\ntemplate<> EIGEN_STRONG_INLINE Packet2d pxor<Packet2d>(const Packet2d& a, const Packet2d& b) { return _mm_xor_pd(a,b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4i pxor<Packet4i>(const Packet4i& a, const Packet4i& b) { return _mm_xor_si128(a,b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pandnot<Packet4f>(const Packet4f& a, const Packet4f& b) { return _mm_andnot_ps(a,b); }\ntemplate<> EIGEN_STRONG_INLINE Packet2d pandnot<Packet2d>(const Packet2d& a, const Packet2d& b) { return _mm_andnot_pd(a,b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4i pandnot<Packet4i>(const Packet4i& a, const Packet4i& b) { return _mm_andnot_si128(a,b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pload<Packet4f>(const float*   from) { EIGEN_DEBUG_ALIGNED_LOAD return _mm_load_ps(from); }\ntemplate<> EIGEN_STRONG_INLINE Packet2d pload<Packet2d>(const double*  from) { EIGEN_DEBUG_ALIGNED_LOAD return _mm_load_pd(from); }\ntemplate<> EIGEN_STRONG_INLINE Packet4i pload<Packet4i>(const int*     from) { EIGEN_DEBUG_ALIGNED_LOAD return _mm_load_si128(reinterpret_cast<const __m128i*>(from)); }\n\n#if EIGEN_COMP_MSVC\n  template<> EIGEN_STRONG_INLINE Packet4f ploadu<Packet4f>(const float*  from) {\n    EIGEN_DEBUG_UNALIGNED_LOAD\n    #if (EIGEN_COMP_MSVC==1600)\n    // NOTE Some version of MSVC10 generates bad code when using _mm_loadu_ps\n    // (i.e., it does not generate an unaligned load!!\n    __m128 res = _mm_loadl_pi(_mm_set1_ps(0.0f), (const __m64*)(from));\n    res = _mm_loadh_pi(res, (const __m64*)(from+2));\n    return res;\n    #else\n    return _mm_loadu_ps(from);\n    #endif\n  }\n#else\n// NOTE: with the code below, MSVC's compiler crashes!\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f ploadu<Packet4f>(const float* from)\n{\n  EIGEN_DEBUG_UNALIGNED_LOAD\n  return _mm_loadu_ps(from);\n}\n#endif\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d ploadu<Packet2d>(const double* from)\n{\n  EIGEN_DEBUG_UNALIGNED_LOAD\n  return _mm_loadu_pd(from);\n}\ntemplate<> EIGEN_STRONG_INLINE Packet4i ploadu<Packet4i>(const int* from)\n{\n  EIGEN_DEBUG_UNALIGNED_LOAD\n  return _mm_loadu_si128(reinterpret_cast<const __m128i*>(from));\n}\n\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f ploaddup<Packet4f>(const float*   from)\n{\n  return vec4f_swizzle1(_mm_castpd_ps(_mm_load_sd(reinterpret_cast<const double*>(from))), 0, 0, 1, 1);\n}\ntemplate<> EIGEN_STRONG_INLINE Packet2d ploaddup<Packet2d>(const double*  from)\n{ return pset1<Packet2d>(from[0]); }\ntemplate<> EIGEN_STRONG_INLINE Packet4i ploaddup<Packet4i>(const int*     from)\n{\n  Packet4i tmp;\n  tmp = _mm_loadl_epi64(reinterpret_cast<const __m128i*>(from));\n  return vec4i_swizzle1(tmp, 0, 0, 1, 1);\n}\n\ntemplate<> EIGEN_STRONG_INLINE void pstore<float>(float*   to, const Packet4f& from) { EIGEN_DEBUG_ALIGNED_STORE _mm_store_ps(to, from); }\ntemplate<> EIGEN_STRONG_INLINE void pstore<double>(double* to, const Packet2d& from) { EIGEN_DEBUG_ALIGNED_STORE _mm_store_pd(to, from); }\ntemplate<> EIGEN_STRONG_INLINE void pstore<int>(int*       to, const Packet4i& from) { EIGEN_DEBUG_ALIGNED_STORE _mm_store_si128(reinterpret_cast<__m128i*>(to), from); }\n\ntemplate<> EIGEN_STRONG_INLINE void pstoreu<double>(double* to, const Packet2d& from) { EIGEN_DEBUG_UNALIGNED_STORE _mm_storeu_pd(to, from); }\ntemplate<> EIGEN_STRONG_INLINE void pstoreu<float>(float*   to, const Packet4f& from) { EIGEN_DEBUG_UNALIGNED_STORE _mm_storeu_ps(to, from); }\ntemplate<> EIGEN_STRONG_INLINE void pstoreu<int>(int*       to, const Packet4i& from) { EIGEN_DEBUG_UNALIGNED_STORE _mm_storeu_si128(reinterpret_cast<__m128i*>(to), from); }\n\ntemplate<> EIGEN_DEVICE_FUNC inline Packet4f pgather<float, Packet4f>(const float* from, Index stride)\n{\n return _mm_set_ps(from[3*stride], from[2*stride], from[1*stride], from[0*stride]);\n}\ntemplate<> EIGEN_DEVICE_FUNC inline Packet2d pgather<double, Packet2d>(const double* from, Index stride)\n{\n return _mm_set_pd(from[1*stride], from[0*stride]);\n}\ntemplate<> EIGEN_DEVICE_FUNC inline Packet4i pgather<int, Packet4i>(const int* from, Index stride)\n{\n return _mm_set_epi32(from[3*stride], from[2*stride], from[1*stride], from[0*stride]);\n }\n\ntemplate<> EIGEN_DEVICE_FUNC inline void pscatter<float, Packet4f>(float* to, const Packet4f& from, Index stride)\n{\n  to[stride*0] = _mm_cvtss_f32(from);\n  to[stride*1] = _mm_cvtss_f32(_mm_shuffle_ps(from, from, 1));\n  to[stride*2] = _mm_cvtss_f32(_mm_shuffle_ps(from, from, 2));\n  to[stride*3] = _mm_cvtss_f32(_mm_shuffle_ps(from, from, 3));\n}\ntemplate<> EIGEN_DEVICE_FUNC inline void pscatter<double, Packet2d>(double* to, const Packet2d& from, Index stride)\n{\n  to[stride*0] = _mm_cvtsd_f64(from);\n  to[stride*1] = _mm_cvtsd_f64(_mm_shuffle_pd(from, from, 1));\n}\ntemplate<> EIGEN_DEVICE_FUNC inline void pscatter<int, Packet4i>(int* to, const Packet4i& from, Index stride)\n{\n  to[stride*0] = _mm_cvtsi128_si32(from);\n  to[stride*1] = _mm_cvtsi128_si32(_mm_shuffle_epi32(from, 1));\n  to[stride*2] = _mm_cvtsi128_si32(_mm_shuffle_epi32(from, 2));\n  to[stride*3] = _mm_cvtsi128_si32(_mm_shuffle_epi32(from, 3));\n}\n\n// some compilers might be tempted to perform multiple moves instead of using a vector path.\ntemplate<> EIGEN_STRONG_INLINE void pstore1<Packet4f>(float* to, const float& a)\n{\n  Packet4f pa = _mm_set_ss(a);\n  pstore(to, Packet4f(vec4f_swizzle1(pa,0,0,0,0)));\n}\n// some compilers might be tempted to perform multiple moves instead of using a vector path.\ntemplate<> EIGEN_STRONG_INLINE void pstore1<Packet2d>(double* to, const double& a)\n{\n  Packet2d pa = _mm_set_sd(a);\n  pstore(to, Packet2d(vec2d_swizzle1(pa,0,0)));\n}\n\n#ifndef EIGEN_VECTORIZE_AVX\ntemplate<> EIGEN_STRONG_INLINE void prefetch<float>(const float*   addr) { _mm_prefetch((const char*)(addr), _MM_HINT_T0); }\ntemplate<> EIGEN_STRONG_INLINE void prefetch<double>(const double* addr) { _mm_prefetch((const char*)(addr), _MM_HINT_T0); }\ntemplate<> EIGEN_STRONG_INLINE void prefetch<int>(const int*       addr) { _mm_prefetch((const char*)(addr), _MM_HINT_T0); }\n#endif\n\n#if EIGEN_COMP_MSVC_STRICT && EIGEN_OS_WIN64\n// The temporary variable fixes an internal compilation error in vs <= 2008 and a wrong-result bug in vs 2010\n// Direct of the struct members fixed bug #62.\ntemplate<> EIGEN_STRONG_INLINE float  pfirst<Packet4f>(const Packet4f& a) { return a.m128_f32[0]; }\ntemplate<> EIGEN_STRONG_INLINE double pfirst<Packet2d>(const Packet2d& a) { return a.m128d_f64[0]; }\ntemplate<> EIGEN_STRONG_INLINE int    pfirst<Packet4i>(const Packet4i& a) { int x = _mm_cvtsi128_si32(a); return x; }\n#elif EIGEN_COMP_MSVC_STRICT\n// The temporary variable fixes an internal compilation error in vs <= 2008 and a wrong-result bug in vs 2010\ntemplate<> EIGEN_STRONG_INLINE float  pfirst<Packet4f>(const Packet4f& a) { float x = _mm_cvtss_f32(a); return x; }\ntemplate<> EIGEN_STRONG_INLINE double pfirst<Packet2d>(const Packet2d& a) { double x = _mm_cvtsd_f64(a); return x; }\ntemplate<> EIGEN_STRONG_INLINE int    pfirst<Packet4i>(const Packet4i& a) { int x = _mm_cvtsi128_si32(a); return x; }\n#else\ntemplate<> EIGEN_STRONG_INLINE float  pfirst<Packet4f>(const Packet4f& a) { return _mm_cvtss_f32(a); }\ntemplate<> EIGEN_STRONG_INLINE double pfirst<Packet2d>(const Packet2d& a) { return _mm_cvtsd_f64(a); }\ntemplate<> EIGEN_STRONG_INLINE int    pfirst<Packet4i>(const Packet4i& a) { return _mm_cvtsi128_si32(a); }\n#endif\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f preverse(const Packet4f& a)\n{ return _mm_shuffle_ps(a,a,0x1B); }\ntemplate<> EIGEN_STRONG_INLINE Packet2d preverse(const Packet2d& a)\n{ return _mm_shuffle_pd(a,a,0x1); }\ntemplate<> EIGEN_STRONG_INLINE Packet4i preverse(const Packet4i& a)\n{ return _mm_shuffle_epi32(a,0x1B); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pabs(const Packet4f& a)\n{\n  const Packet4f mask = _mm_castsi128_ps(_mm_setr_epi32(0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF));\n  return _mm_and_ps(a,mask);\n}\ntemplate<> EIGEN_STRONG_INLINE Packet2d pabs(const Packet2d& a)\n{\n  const Packet2d mask = _mm_castsi128_pd(_mm_setr_epi32(0xFFFFFFFF,0x7FFFFFFF,0xFFFFFFFF,0x7FFFFFFF));\n  return _mm_and_pd(a,mask);\n}\ntemplate<> EIGEN_STRONG_INLINE Packet4i pabs(const Packet4i& a)\n{\n  #ifdef EIGEN_VECTORIZE_SSSE3\n  return _mm_abs_epi32(a);\n  #else\n  Packet4i aux = _mm_srai_epi32(a,31);\n  return _mm_sub_epi32(_mm_xor_si128(a,aux),aux);\n  #endif\n}\n\n// with AVX, the default implementations based on pload1 are faster\n#ifndef __AVX__\ntemplate<> EIGEN_STRONG_INLINE void\npbroadcast4<Packet4f>(const float *a,\n                      Packet4f& a0, Packet4f& a1, Packet4f& a2, Packet4f& a3)\n{\n  a3 = pload<Packet4f>(a);\n  a0 = vec4f_swizzle1(a3, 0,0,0,0);\n  a1 = vec4f_swizzle1(a3, 1,1,1,1);\n  a2 = vec4f_swizzle1(a3, 2,2,2,2);\n  a3 = vec4f_swizzle1(a3, 3,3,3,3);\n}\ntemplate<> EIGEN_STRONG_INLINE void\npbroadcast4<Packet2d>(const double *a,\n                      Packet2d& a0, Packet2d& a1, Packet2d& a2, Packet2d& a3)\n{\n#ifdef EIGEN_VECTORIZE_SSE3\n  a0 = _mm_loaddup_pd(a+0);\n  a1 = _mm_loaddup_pd(a+1);\n  a2 = _mm_loaddup_pd(a+2);\n  a3 = _mm_loaddup_pd(a+3);\n#else\n  a1 = pload<Packet2d>(a);\n  a0 = vec2d_swizzle1(a1, 0,0);\n  a1 = vec2d_swizzle1(a1, 1,1);\n  a3 = pload<Packet2d>(a+2);\n  a2 = vec2d_swizzle1(a3, 0,0);\n  a3 = vec2d_swizzle1(a3, 1,1);\n#endif\n}\n#endif\n\nEIGEN_STRONG_INLINE void punpackp(Packet4f* vecs)\n{\n  vecs[1] = _mm_castsi128_ps(_mm_shuffle_epi32(_mm_castps_si128(vecs[0]), 0x55));\n  vecs[2] = _mm_castsi128_ps(_mm_shuffle_epi32(_mm_castps_si128(vecs[0]), 0xAA));\n  vecs[3] = _mm_castsi128_ps(_mm_shuffle_epi32(_mm_castps_si128(vecs[0]), 0xFF));\n  vecs[0] = _mm_castsi128_ps(_mm_shuffle_epi32(_mm_castps_si128(vecs[0]), 0x00));\n}\n\n#ifdef EIGEN_VECTORIZE_SSE3\ntemplate<> EIGEN_STRONG_INLINE Packet4f preduxp<Packet4f>(const Packet4f* vecs)\n{\n  return _mm_hadd_ps(_mm_hadd_ps(vecs[0], vecs[1]),_mm_hadd_ps(vecs[2], vecs[3]));\n}\ntemplate<> EIGEN_STRONG_INLINE Packet2d preduxp<Packet2d>(const Packet2d* vecs)\n{\n  return _mm_hadd_pd(vecs[0], vecs[1]);\n}\n\ntemplate<> EIGEN_STRONG_INLINE float predux<Packet4f>(const Packet4f& a)\n{\n  Packet4f tmp0 = _mm_hadd_ps(a,a);\n  return pfirst<Packet4f>(_mm_hadd_ps(tmp0, tmp0));\n}\n\ntemplate<> EIGEN_STRONG_INLINE double predux<Packet2d>(const Packet2d& a) { return pfirst<Packet2d>(_mm_hadd_pd(a, a)); }\n#else\n// SSE2 versions\ntemplate<> EIGEN_STRONG_INLINE float predux<Packet4f>(const Packet4f& a)\n{\n  Packet4f tmp = _mm_add_ps(a, _mm_movehl_ps(a,a));\n  return pfirst<Packet4f>(_mm_add_ss(tmp, _mm_shuffle_ps(tmp,tmp, 1)));\n}\ntemplate<> EIGEN_STRONG_INLINE double predux<Packet2d>(const Packet2d& a)\n{\n  return pfirst<Packet2d>(_mm_add_sd(a, _mm_unpackhi_pd(a,a)));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f preduxp<Packet4f>(const Packet4f* vecs)\n{\n  Packet4f tmp0, tmp1, tmp2;\n  tmp0 = _mm_unpacklo_ps(vecs[0], vecs[1]);\n  tmp1 = _mm_unpackhi_ps(vecs[0], vecs[1]);\n  tmp2 = _mm_unpackhi_ps(vecs[2], vecs[3]);\n  tmp0 = _mm_add_ps(tmp0, tmp1);\n  tmp1 = _mm_unpacklo_ps(vecs[2], vecs[3]);\n  tmp1 = _mm_add_ps(tmp1, tmp2);\n  tmp2 = _mm_movehl_ps(tmp1, tmp0);\n  tmp0 = _mm_movelh_ps(tmp0, tmp1);\n  return _mm_add_ps(tmp0, tmp2);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d preduxp<Packet2d>(const Packet2d* vecs)\n{\n  return _mm_add_pd(_mm_unpacklo_pd(vecs[0], vecs[1]), _mm_unpackhi_pd(vecs[0], vecs[1]));\n}\n#endif  // SSE3\n\n\n#ifdef EIGEN_VECTORIZE_SSSE3\ntemplate<> EIGEN_STRONG_INLINE Packet4i preduxp<Packet4i>(const Packet4i* vecs)\n{\n  return _mm_hadd_epi32(_mm_hadd_epi32(vecs[0], vecs[1]),_mm_hadd_epi32(vecs[2], vecs[3]));\n}\ntemplate<> EIGEN_STRONG_INLINE int predux<Packet4i>(const Packet4i& a)\n{\n  Packet4i tmp0 = _mm_hadd_epi32(a,a);\n  return pfirst<Packet4i>(_mm_hadd_epi32(tmp0,tmp0));\n}\n#else\ntemplate<> EIGEN_STRONG_INLINE int predux<Packet4i>(const Packet4i& a)\n{\n  Packet4i tmp = _mm_add_epi32(a, _mm_unpackhi_epi64(a,a));\n  return pfirst(tmp) + pfirst<Packet4i>(_mm_shuffle_epi32(tmp, 1));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4i preduxp<Packet4i>(const Packet4i* vecs)\n{\n  Packet4i tmp0, tmp1, tmp2;\n  tmp0 = _mm_unpacklo_epi32(vecs[0], vecs[1]);\n  tmp1 = _mm_unpackhi_epi32(vecs[0], vecs[1]);\n  tmp2 = _mm_unpackhi_epi32(vecs[2], vecs[3]);\n  tmp0 = _mm_add_epi32(tmp0, tmp1);\n  tmp1 = _mm_unpacklo_epi32(vecs[2], vecs[3]);\n  tmp1 = _mm_add_epi32(tmp1, tmp2);\n  tmp2 = _mm_unpacklo_epi64(tmp0, tmp1);\n  tmp0 = _mm_unpackhi_epi64(tmp0, tmp1);\n  return _mm_add_epi32(tmp0, tmp2);\n}\n#endif\n// Other reduction functions:\n\n// mul\ntemplate<> EIGEN_STRONG_INLINE float predux_mul<Packet4f>(const Packet4f& a)\n{\n  Packet4f tmp = _mm_mul_ps(a, _mm_movehl_ps(a,a));\n  return pfirst<Packet4f>(_mm_mul_ss(tmp, _mm_shuffle_ps(tmp,tmp, 1)));\n}\ntemplate<> EIGEN_STRONG_INLINE double predux_mul<Packet2d>(const Packet2d& a)\n{\n  return pfirst<Packet2d>(_mm_mul_sd(a, _mm_unpackhi_pd(a,a)));\n}\ntemplate<> EIGEN_STRONG_INLINE int predux_mul<Packet4i>(const Packet4i& a)\n{\n  // after some experiments, it is seems this is the fastest way to implement it\n  // for GCC (eg., reusing pmul is very slow !)\n  // TODO try to call _mm_mul_epu32 directly\n  EIGEN_ALIGN16 int aux[4];\n  pstore(aux, a);\n  return  (aux[0] * aux[1]) * (aux[2] * aux[3]);;\n}\n\n// min\ntemplate<> EIGEN_STRONG_INLINE float predux_min<Packet4f>(const Packet4f& a)\n{\n  Packet4f tmp = _mm_min_ps(a, _mm_movehl_ps(a,a));\n  return pfirst<Packet4f>(_mm_min_ss(tmp, _mm_shuffle_ps(tmp,tmp, 1)));\n}\ntemplate<> EIGEN_STRONG_INLINE double predux_min<Packet2d>(const Packet2d& a)\n{\n  return pfirst<Packet2d>(_mm_min_sd(a, _mm_unpackhi_pd(a,a)));\n}\ntemplate<> EIGEN_STRONG_INLINE int predux_min<Packet4i>(const Packet4i& a)\n{\n#ifdef EIGEN_VECTORIZE_SSE4_1\n  Packet4i tmp = _mm_min_epi32(a, _mm_shuffle_epi32(a, _MM_SHUFFLE(0,0,3,2)));\n  return pfirst<Packet4i>(_mm_min_epi32(tmp,_mm_shuffle_epi32(tmp, 1)));\n#else\n  // after some experiments, it is seems this is the fastest way to implement it\n  // for GCC (eg., it does not like using std::min after the pstore !!)\n  EIGEN_ALIGN16 int aux[4];\n  pstore(aux, a);\n  int aux0 = aux[0]<aux[1] ? aux[0] : aux[1];\n  int aux2 = aux[2]<aux[3] ? aux[2] : aux[3];\n  return aux0<aux2 ? aux0 : aux2;\n#endif // EIGEN_VECTORIZE_SSE4_1\n}\n\n// max\ntemplate<> EIGEN_STRONG_INLINE float predux_max<Packet4f>(const Packet4f& a)\n{\n  Packet4f tmp = _mm_max_ps(a, _mm_movehl_ps(a,a));\n  return pfirst<Packet4f>(_mm_max_ss(tmp, _mm_shuffle_ps(tmp,tmp, 1)));\n}\ntemplate<> EIGEN_STRONG_INLINE double predux_max<Packet2d>(const Packet2d& a)\n{\n  return pfirst<Packet2d>(_mm_max_sd(a, _mm_unpackhi_pd(a,a)));\n}\ntemplate<> EIGEN_STRONG_INLINE int predux_max<Packet4i>(const Packet4i& a)\n{\n#ifdef EIGEN_VECTORIZE_SSE4_1\n  Packet4i tmp = _mm_max_epi32(a, _mm_shuffle_epi32(a, _MM_SHUFFLE(0,0,3,2)));\n  return pfirst<Packet4i>(_mm_max_epi32(tmp,_mm_shuffle_epi32(tmp, 1)));\n#else\n  // after some experiments, it is seems this is the fastest way to implement it\n  // for GCC (eg., it does not like using std::min after the pstore !!)\n  EIGEN_ALIGN16 int aux[4];\n  pstore(aux, a);\n  int aux0 = aux[0]>aux[1] ? aux[0] : aux[1];\n  int aux2 = aux[2]>aux[3] ? aux[2] : aux[3];\n  return aux0>aux2 ? aux0 : aux2;\n#endif // EIGEN_VECTORIZE_SSE4_1\n}\n\n#if EIGEN_COMP_GNUC\n// template <> EIGEN_STRONG_INLINE Packet4f pmadd(const Packet4f&  a, const Packet4f&  b, const Packet4f&  c)\n// {\n//   Packet4f res = b;\n//   asm(\"mulps %[a], %[b] \\n\\taddps %[c], %[b]\" : [b] \"+x\" (res) : [a] \"x\" (a), [c] \"x\" (c));\n//   return res;\n// }\n// EIGEN_STRONG_INLINE Packet4i _mm_alignr_epi8(const Packet4i&  a, const Packet4i&  b, const int i)\n// {\n//   Packet4i res = a;\n//   asm(\"palignr %[i], %[a], %[b] \" : [b] \"+x\" (res) : [a] \"x\" (a), [i] \"i\" (i));\n//   return res;\n// }\n#endif\n\n#ifdef EIGEN_VECTORIZE_SSSE3\n// SSSE3 versions\ntemplate<int Offset>\nstruct palign_impl<Offset,Packet4f>\n{\n  static EIGEN_STRONG_INLINE void run(Packet4f& first, const Packet4f& second)\n  {\n    if (Offset!=0)\n      first = _mm_castsi128_ps(_mm_alignr_epi8(_mm_castps_si128(second), _mm_castps_si128(first), Offset*4));\n  }\n};\n\ntemplate<int Offset>\nstruct palign_impl<Offset,Packet4i>\n{\n  static EIGEN_STRONG_INLINE void run(Packet4i& first, const Packet4i& second)\n  {\n    if (Offset!=0)\n      first = _mm_alignr_epi8(second,first, Offset*4);\n  }\n};\n\ntemplate<int Offset>\nstruct palign_impl<Offset,Packet2d>\n{\n  static EIGEN_STRONG_INLINE void run(Packet2d& first, const Packet2d& second)\n  {\n    if (Offset==1)\n      first = _mm_castsi128_pd(_mm_alignr_epi8(_mm_castpd_si128(second), _mm_castpd_si128(first), 8));\n  }\n};\n#else\n// SSE2 versions\ntemplate<int Offset>\nstruct palign_impl<Offset,Packet4f>\n{\n  static EIGEN_STRONG_INLINE void run(Packet4f& first, const Packet4f& second)\n  {\n    if (Offset==1)\n    {\n      first = _mm_move_ss(first,second);\n      first = _mm_castsi128_ps(_mm_shuffle_epi32(_mm_castps_si128(first),0x39));\n    }\n    else if (Offset==2)\n    {\n      first = _mm_movehl_ps(first,first);\n      first = _mm_movelh_ps(first,second);\n    }\n    else if (Offset==3)\n    {\n      first = _mm_move_ss(first,second);\n      first = _mm_shuffle_ps(first,second,0x93);\n    }\n  }\n};\n\ntemplate<int Offset>\nstruct palign_impl<Offset,Packet4i>\n{\n  static EIGEN_STRONG_INLINE void run(Packet4i& first, const Packet4i& second)\n  {\n    if (Offset==1)\n    {\n      first = _mm_castps_si128(_mm_move_ss(_mm_castsi128_ps(first),_mm_castsi128_ps(second)));\n      first = _mm_shuffle_epi32(first,0x39);\n    }\n    else if (Offset==2)\n    {\n      first = _mm_castps_si128(_mm_movehl_ps(_mm_castsi128_ps(first),_mm_castsi128_ps(first)));\n      first = _mm_castps_si128(_mm_movelh_ps(_mm_castsi128_ps(first),_mm_castsi128_ps(second)));\n    }\n    else if (Offset==3)\n    {\n      first = _mm_castps_si128(_mm_move_ss(_mm_castsi128_ps(first),_mm_castsi128_ps(second)));\n      first = _mm_castps_si128(_mm_shuffle_ps(_mm_castsi128_ps(first),_mm_castsi128_ps(second),0x93));\n    }\n  }\n};\n\ntemplate<int Offset>\nstruct palign_impl<Offset,Packet2d>\n{\n  static EIGEN_STRONG_INLINE void run(Packet2d& first, const Packet2d& second)\n  {\n    if (Offset==1)\n    {\n      first = _mm_castps_pd(_mm_movehl_ps(_mm_castpd_ps(first),_mm_castpd_ps(first)));\n      first = _mm_castps_pd(_mm_movelh_ps(_mm_castpd_ps(first),_mm_castpd_ps(second)));\n    }\n  }\n};\n#endif\n\nEIGEN_DEVICE_FUNC inline void\nptranspose(PacketBlock<Packet4f,4>& kernel) {\n  _MM_TRANSPOSE4_PS(kernel.packet[0], kernel.packet[1], kernel.packet[2], kernel.packet[3]);\n}\n\nEIGEN_DEVICE_FUNC inline void\nptranspose(PacketBlock<Packet2d,2>& kernel) {\n  __m128d tmp = _mm_unpackhi_pd(kernel.packet[0], kernel.packet[1]);\n  kernel.packet[0] = _mm_unpacklo_pd(kernel.packet[0], kernel.packet[1]);\n  kernel.packet[1] = tmp;\n}\n\nEIGEN_DEVICE_FUNC inline void\nptranspose(PacketBlock<Packet4i,4>& kernel) {\n  __m128i T0 = _mm_unpacklo_epi32(kernel.packet[0], kernel.packet[1]);\n  __m128i T1 = _mm_unpacklo_epi32(kernel.packet[2], kernel.packet[3]);\n  __m128i T2 = _mm_unpackhi_epi32(kernel.packet[0], kernel.packet[1]);\n  __m128i T3 = _mm_unpackhi_epi32(kernel.packet[2], kernel.packet[3]);\n\n  kernel.packet[0] = _mm_unpacklo_epi64(T0, T1);\n  kernel.packet[1] = _mm_unpackhi_epi64(T0, T1);\n  kernel.packet[2] = _mm_unpacklo_epi64(T2, T3);\n  kernel.packet[3] = _mm_unpackhi_epi64(T2, T3);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4i pblend(const Selector<4>& ifPacket, const Packet4i& thenPacket, const Packet4i& elsePacket) {\n  const __m128i zero = _mm_setzero_si128();\n  const __m128i select = _mm_set_epi32(ifPacket.select[3], ifPacket.select[2], ifPacket.select[1], ifPacket.select[0]);\n  __m128i false_mask = _mm_cmpeq_epi32(select, zero);\n#ifdef EIGEN_VECTORIZE_SSE4_1\n  return _mm_blendv_epi8(thenPacket, elsePacket, false_mask);\n#else\n  return _mm_or_si128(_mm_andnot_si128(false_mask, thenPacket), _mm_and_si128(false_mask, elsePacket));\n#endif\n}\ntemplate<> EIGEN_STRONG_INLINE Packet4f pblend(const Selector<4>& ifPacket, const Packet4f& thenPacket, const Packet4f& elsePacket) {\n  const __m128 zero = _mm_setzero_ps();\n  const __m128 select = _mm_set_ps(ifPacket.select[3], ifPacket.select[2], ifPacket.select[1], ifPacket.select[0]);\n  __m128 false_mask = _mm_cmpeq_ps(select, zero);\n#ifdef EIGEN_VECTORIZE_SSE4_1\n  return _mm_blendv_ps(thenPacket, elsePacket, false_mask);\n#else\n  return _mm_or_ps(_mm_andnot_ps(false_mask, thenPacket), _mm_and_ps(false_mask, elsePacket));\n#endif\n}\ntemplate<> EIGEN_STRONG_INLINE Packet2d pblend(const Selector<2>& ifPacket, const Packet2d& thenPacket, const Packet2d& elsePacket) {\n  const __m128d zero = _mm_setzero_pd();\n  const __m128d select = _mm_set_pd(ifPacket.select[1], ifPacket.select[0]);\n  __m128d false_mask = _mm_cmpeq_pd(select, zero);\n#ifdef EIGEN_VECTORIZE_SSE4_1\n  return _mm_blendv_pd(thenPacket, elsePacket, false_mask);\n#else\n  return _mm_or_pd(_mm_andnot_pd(false_mask, thenPacket), _mm_and_pd(false_mask, elsePacket));\n#endif\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pinsertfirst(const Packet4f& a, float b)\n{\n#ifdef EIGEN_VECTORIZE_SSE4_1\n  return _mm_blend_ps(a,pset1<Packet4f>(b),1);\n#else\n  return _mm_move_ss(a, _mm_load_ss(&b));\n#endif\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d pinsertfirst(const Packet2d& a, double b)\n{\n#ifdef EIGEN_VECTORIZE_SSE4_1\n  return _mm_blend_pd(a,pset1<Packet2d>(b),1);\n#else\n  return _mm_move_sd(a, _mm_load_sd(&b));\n#endif\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pinsertlast(const Packet4f& a, float b)\n{\n#ifdef EIGEN_VECTORIZE_SSE4_1\n  return _mm_blend_ps(a,pset1<Packet4f>(b),(1<<3));\n#else\n  const Packet4f mask = _mm_castsi128_ps(_mm_setr_epi32(0x0,0x0,0x0,0xFFFFFFFF));\n  return _mm_or_ps(_mm_andnot_ps(mask, a), _mm_and_ps(mask, pset1<Packet4f>(b)));\n#endif\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d pinsertlast(const Packet2d& a, double b)\n{\n#ifdef EIGEN_VECTORIZE_SSE4_1\n  return _mm_blend_pd(a,pset1<Packet2d>(b),(1<<1));\n#else\n  const Packet2d mask = _mm_castsi128_pd(_mm_setr_epi32(0x0,0x0,0xFFFFFFFF,0xFFFFFFFF));\n  return _mm_or_pd(_mm_andnot_pd(mask, a), _mm_and_pd(mask, pset1<Packet2d>(b)));\n#endif\n}\n\n// Scalar path for pmadd with FMA to ensure consistency with vectorized path.\n#ifdef __FMA__\ntemplate<> EIGEN_STRONG_INLINE float pmadd(const float& a, const float& b, const float& c) {\n  return ::fmaf(a,b,c);\n}\ntemplate<> EIGEN_STRONG_INLINE double pmadd(const double& a, const double& b, const double& c) {\n  return ::fma(a,b,c);\n}\n#endif\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_PACKET_MATH_SSE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/arch/SSE/TypeCasting.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2015 Benoit Steiner <benoit.steiner.goog@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_TYPE_CASTING_SSE_H\n#define EIGEN_TYPE_CASTING_SSE_H\n\nnamespace Eigen {\n\nnamespace internal {\n\ntemplate <>\nstruct type_casting_traits<float, int> {\n  enum {\n    VectorizedCast = 1,\n    SrcCoeffRatio = 1,\n    TgtCoeffRatio = 1\n  };\n};\n\ntemplate<> EIGEN_STRONG_INLINE Packet4i pcast<Packet4f, Packet4i>(const Packet4f& a) {\n  return _mm_cvttps_epi32(a);\n}\n\n\ntemplate <>\nstruct type_casting_traits<int, float> {\n  enum {\n    VectorizedCast = 1,\n    SrcCoeffRatio = 1,\n    TgtCoeffRatio = 1\n  };\n};\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pcast<Packet4i, Packet4f>(const Packet4i& a) {\n  return _mm_cvtepi32_ps(a);\n}\n\n\ntemplate <>\nstruct type_casting_traits<double, float> {\n  enum {\n    VectorizedCast = 1,\n    SrcCoeffRatio = 2,\n    TgtCoeffRatio = 1\n  };\n};\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pcast<Packet2d, Packet4f>(const Packet2d& a, const Packet2d& b) {\n  return _mm_shuffle_ps(_mm_cvtpd_ps(a), _mm_cvtpd_ps(b), (1 << 2) | (1 << 6));\n}\n\ntemplate <>\nstruct type_casting_traits<float, double> {\n  enum {\n    VectorizedCast = 1,\n    SrcCoeffRatio = 1,\n    TgtCoeffRatio = 2\n  };\n};\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d pcast<Packet4f, Packet2d>(const Packet4f& a) {\n  // Simply discard the second half of the input\n  return _mm_cvtps_pd(a);\n}\n\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_TYPE_CASTING_SSE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/arch/ZVector/Complex.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2016 Konstantinos Margaritis <markos@freevec.org>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_COMPLEX32_ALTIVEC_H\n#define EIGEN_COMPLEX32_ALTIVEC_H\n\nnamespace Eigen {\n\nnamespace internal {\n\nstatic Packet2ul  p2ul_CONJ_XOR1 = (Packet2ul) vec_sld((Packet4ui) p2d_ZERO_, (Packet4ui) p2l_ZERO, 8);//{ 0x8000000000000000, 0x0000000000000000 };\nstatic Packet2ul  p2ul_CONJ_XOR2 = (Packet2ul) vec_sld((Packet4ui) p2l_ZERO,  (Packet4ui) p2d_ZERO_, 8);//{ 0x8000000000000000, 0x0000000000000000 };\n\nstruct Packet1cd\n{\n  EIGEN_STRONG_INLINE Packet1cd() {}\n  EIGEN_STRONG_INLINE explicit Packet1cd(const Packet2d& a) : v(a) {}\n  Packet2d v;\n};\n\nstruct Packet2cf\n{\n  EIGEN_STRONG_INLINE Packet2cf() {}\n  EIGEN_STRONG_INLINE explicit Packet2cf(const Packet4f& a) : v(a) {}\n  union {\n    Packet4f v;\n    Packet1cd cd[2];\n  };\n};\n\ntemplate<> struct packet_traits<std::complex<float> >  : default_packet_traits\n{\n  typedef Packet2cf type;\n  typedef Packet2cf half;\n  enum {\n    Vectorizable = 1,\n    AlignedOnScalar = 1,\n    size = 2,\n    HasHalfPacket = 0,\n\n    HasAdd    = 1,\n    HasSub    = 1,\n    HasMul    = 1,\n    HasDiv    = 1,\n    HasNegate = 1,\n    HasAbs    = 0,\n    HasAbs2   = 0,\n    HasMin    = 0,\n    HasMax    = 0,\n    HasBlend  = 1,\n    HasSetLinear = 0\n  };\n};\n\n\ntemplate<> struct packet_traits<std::complex<double> >  : default_packet_traits\n{\n  typedef Packet1cd type;\n  typedef Packet1cd half;\n  enum {\n    Vectorizable = 1,\n    AlignedOnScalar = 1,\n    size = 1,\n    HasHalfPacket = 0,\n\n    HasAdd    = 1,\n    HasSub    = 1,\n    HasMul    = 1,\n    HasDiv    = 1,\n    HasNegate = 1,\n    HasAbs    = 0,\n    HasAbs2   = 0,\n    HasMin    = 0,\n    HasMax    = 0,\n    HasSetLinear = 0\n  };\n};\n\ntemplate<> struct unpacket_traits<Packet2cf> { typedef std::complex<float>  type; enum {size=2, alignment=Aligned16}; typedef Packet2cf half; };\ntemplate<> struct unpacket_traits<Packet1cd> { typedef std::complex<double> type; enum {size=1, alignment=Aligned16}; typedef Packet1cd half; };\n\n/* Forward declaration */\nEIGEN_STRONG_INLINE void ptranspose(PacketBlock<Packet2cf,2>& kernel);\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pload <Packet2cf>(const std::complex<float>* from)  { EIGEN_DEBUG_ALIGNED_LOAD return Packet2cf(pload<Packet4f>((const float*)from)); }\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pload <Packet1cd>(const std::complex<double>* from) { EIGEN_DEBUG_ALIGNED_LOAD return Packet1cd(pload<Packet2d>((const double*)from)); }\ntemplate<> EIGEN_STRONG_INLINE Packet2cf ploadu<Packet2cf>(const std::complex<float>* from)  { EIGEN_DEBUG_UNALIGNED_LOAD return Packet2cf(ploadu<Packet4f>((const float*)from)); }\ntemplate<> EIGEN_STRONG_INLINE Packet1cd ploadu<Packet1cd>(const std::complex<double>* from) { EIGEN_DEBUG_UNALIGNED_LOAD return Packet1cd(ploadu<Packet2d>((const double*)from)); }\ntemplate<> EIGEN_STRONG_INLINE void pstore <std::complex<float> >(std::complex<float> *     to, const Packet2cf& from) { EIGEN_DEBUG_ALIGNED_STORE pstore((float*)to, from.v); }\ntemplate<> EIGEN_STRONG_INLINE void pstore <std::complex<double> >(std::complex<double> *   to, const Packet1cd& from) { EIGEN_DEBUG_ALIGNED_STORE pstore((double*)to, from.v); }\ntemplate<> EIGEN_STRONG_INLINE void pstoreu<std::complex<float> >(std::complex<float> *     to, const Packet2cf& from) { EIGEN_DEBUG_UNALIGNED_STORE pstoreu((float*)to, from.v); }\ntemplate<> EIGEN_STRONG_INLINE void pstoreu<std::complex<double> >(std::complex<double> *   to, const Packet1cd& from) { EIGEN_DEBUG_UNALIGNED_STORE pstoreu((double*)to, from.v); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pset1<Packet1cd>(const std::complex<double>&  from)\n{ /* here we really have to use unaligned loads :( */ return ploadu<Packet1cd>(&from); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pset1<Packet2cf>(const std::complex<float>&  from)\n{\n  Packet2cf res;\n  res.cd[0] = Packet1cd(vec_ld2f((const float *)&from));\n  res.cd[1] = res.cd[0];\n  return res;\n}\ntemplate<> EIGEN_DEVICE_FUNC inline Packet2cf pgather<std::complex<float>, Packet2cf>(const std::complex<float>* from, Index stride)\n{\n  std::complex<float> EIGEN_ALIGN16 af[2];\n  af[0] = from[0*stride];\n  af[1] = from[1*stride];\n  return pload<Packet2cf>(af);\n}\ntemplate<> EIGEN_DEVICE_FUNC inline Packet1cd pgather<std::complex<double>, Packet1cd>(const std::complex<double>* from, Index stride EIGEN_UNUSED)\n{\n  return pload<Packet1cd>(from);\n}\ntemplate<> EIGEN_DEVICE_FUNC inline void pscatter<std::complex<float>, Packet2cf>(std::complex<float>* to, const Packet2cf& from, Index stride)\n{\n  std::complex<float> EIGEN_ALIGN16 af[2];\n  pstore<std::complex<float> >((std::complex<float> *) af, from);\n  to[0*stride] = af[0];\n  to[1*stride] = af[1];\n}\ntemplate<> EIGEN_DEVICE_FUNC inline void pscatter<std::complex<double>, Packet1cd>(std::complex<double>* to, const Packet1cd& from, Index stride EIGEN_UNUSED)\n{\n  pstore<std::complex<double> >(to, from);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cf padd<Packet2cf>(const Packet2cf& a, const Packet2cf& b) { return Packet2cf(padd<Packet4f>(a.v, b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet1cd padd<Packet1cd>(const Packet1cd& a, const Packet1cd& b) { return Packet1cd(a.v + b.v); }\ntemplate<> EIGEN_STRONG_INLINE Packet2cf psub<Packet2cf>(const Packet2cf& a, const Packet2cf& b) { return Packet2cf(psub<Packet4f>(a.v, b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet1cd psub<Packet1cd>(const Packet1cd& a, const Packet1cd& b) { return Packet1cd(a.v - b.v); }\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pnegate(const Packet1cd& a) { return Packet1cd(pnegate(Packet2d(a.v))); }\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pnegate(const Packet2cf& a) { return Packet2cf(pnegate(Packet4f(a.v))); }\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pconj(const Packet1cd& a) { return Packet1cd((Packet2d)vec_xor((Packet2d)a.v, (Packet2d)p2ul_CONJ_XOR2)); }\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pconj(const Packet2cf& a)\n{\n  Packet2cf res;\n  res.v.v4f[0] = pconj(Packet1cd(reinterpret_cast<Packet2d>(a.v.v4f[0]))).v;\n  res.v.v4f[1] = pconj(Packet1cd(reinterpret_cast<Packet2d>(a.v.v4f[1]))).v;\n  return res;\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pmul<Packet1cd>(const Packet1cd& a, const Packet1cd& b)\n{\n  Packet2d a_re, a_im, v1, v2;\n\n  // Permute and multiply the real parts of a and b\n  a_re = vec_perm(a.v, a.v, p16uc_PSET64_HI);\n  // Get the imaginary parts of a\n  a_im = vec_perm(a.v, a.v, p16uc_PSET64_LO);\n  // multiply a_re * b\n  v1 = vec_madd(a_re, b.v, p2d_ZERO);\n  // multiply a_im * b and get the conjugate result\n  v2 = vec_madd(a_im, b.v, p2d_ZERO);\n  v2 = (Packet2d) vec_sld((Packet4ui)v2, (Packet4ui)v2, 8);\n  v2 = (Packet2d) vec_xor((Packet2d)v2, (Packet2d) p2ul_CONJ_XOR1);\n\n  return Packet1cd(v1 + v2);\n}\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pmul<Packet2cf>(const Packet2cf& a, const Packet2cf& b)\n{\n  Packet2cf res;\n  res.v.v4f[0] = pmul(Packet1cd(reinterpret_cast<Packet2d>(a.v.v4f[0])), Packet1cd(reinterpret_cast<Packet2d>(b.v.v4f[0]))).v;\n  res.v.v4f[1] = pmul(Packet1cd(reinterpret_cast<Packet2d>(a.v.v4f[1])), Packet1cd(reinterpret_cast<Packet2d>(b.v.v4f[1]))).v;\n  return res;\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pand   <Packet1cd>(const Packet1cd& a, const Packet1cd& b) { return Packet1cd(vec_and(a.v,b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pand   <Packet2cf>(const Packet2cf& a, const Packet2cf& b) { return Packet2cf(pand<Packet4f>(a.v,b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet1cd por    <Packet1cd>(const Packet1cd& a, const Packet1cd& b) { return Packet1cd(vec_or(a.v,b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet2cf por    <Packet2cf>(const Packet2cf& a, const Packet2cf& b) { return Packet2cf(por<Packet4f>(a.v,b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pxor   <Packet1cd>(const Packet1cd& a, const Packet1cd& b) { return Packet1cd(vec_xor(a.v,b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pxor   <Packet2cf>(const Packet2cf& a, const Packet2cf& b) { return Packet2cf(pxor<Packet4f>(a.v,b.v)); }\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pandnot<Packet1cd>(const Packet1cd& a, const Packet1cd& b) { return Packet1cd(vec_and(a.v, vec_nor(b.v,b.v))); }\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pandnot<Packet2cf>(const Packet2cf& a, const Packet2cf& b) { return Packet2cf(pandnot<Packet4f>(a.v,b.v)); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet1cd ploaddup<Packet1cd>(const std::complex<double>*     from) {  return pset1<Packet1cd>(*from); }\ntemplate<> EIGEN_STRONG_INLINE Packet2cf ploaddup<Packet2cf>(const std::complex<float>*      from) {  return pset1<Packet2cf>(*from); }\n\ntemplate<> EIGEN_STRONG_INLINE void prefetch<std::complex<float> >(const std::complex<float> *     addr) { EIGEN_ZVECTOR_PREFETCH(addr); }\ntemplate<> EIGEN_STRONG_INLINE void prefetch<std::complex<double> >(const std::complex<double> *   addr) { EIGEN_ZVECTOR_PREFETCH(addr); }\n\ntemplate<> EIGEN_STRONG_INLINE std::complex<double>  pfirst<Packet1cd>(const Packet1cd& a)\n{\n  std::complex<double> EIGEN_ALIGN16 res;\n  pstore<std::complex<double> >(&res, a);\n\n  return res;\n}\ntemplate<> EIGEN_STRONG_INLINE std::complex<float>  pfirst<Packet2cf>(const Packet2cf& a)\n{\n  std::complex<float> EIGEN_ALIGN16 res[2];\n  pstore<std::complex<float> >(res, a);\n\n  return res[0];\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet1cd preverse(const Packet1cd& a) { return a; }\ntemplate<> EIGEN_STRONG_INLINE Packet2cf preverse(const Packet2cf& a)\n{\n  Packet2cf res;\n  res.cd[0] = a.cd[1];\n  res.cd[1] = a.cd[0];\n  return res;\n}\n\ntemplate<> EIGEN_STRONG_INLINE std::complex<double> predux<Packet1cd>(const Packet1cd& a)\n{\n  return pfirst(a);\n}\ntemplate<> EIGEN_STRONG_INLINE std::complex<float> predux<Packet2cf>(const Packet2cf& a)\n{\n  std::complex<float> res;\n  Packet1cd b = padd<Packet1cd>(a.cd[0], a.cd[1]);\n  vec_st2f(b.v, (float*)&res);\n  return res;\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet1cd preduxp<Packet1cd>(const Packet1cd* vecs)\n{\n  return vecs[0];\n}\ntemplate<> EIGEN_STRONG_INLINE Packet2cf preduxp<Packet2cf>(const Packet2cf* vecs)\n{\n  PacketBlock<Packet2cf,2> transpose;\n  transpose.packet[0] = vecs[0];\n  transpose.packet[1] = vecs[1];\n  ptranspose(transpose);\n\n  return padd<Packet2cf>(transpose.packet[0], transpose.packet[1]);\n} \n\ntemplate<> EIGEN_STRONG_INLINE std::complex<double> predux_mul<Packet1cd>(const Packet1cd& a)\n{\n  return pfirst(a);\n}\ntemplate<> EIGEN_STRONG_INLINE std::complex<float> predux_mul<Packet2cf>(const Packet2cf& a)\n{\n  std::complex<float> res;\n  Packet1cd b = pmul<Packet1cd>(a.cd[0], a.cd[1]);\n  vec_st2f(b.v, (float*)&res);\n  return res;\n}\n\ntemplate<int Offset>\nstruct palign_impl<Offset,Packet1cd>\n{\n  static EIGEN_STRONG_INLINE void run(Packet1cd& /*first*/, const Packet1cd& /*second*/)\n  {\n    // FIXME is it sure we never have to align a Packet1cd?\n    // Even though a std::complex<double> has 16 bytes, it is not necessarily aligned on a 16 bytes boundary...\n  }\n};\n\ntemplate<int Offset>\nstruct palign_impl<Offset,Packet2cf>\n{\n  static EIGEN_STRONG_INLINE void run(Packet2cf& first, const Packet2cf& second)\n  {\n    if (Offset == 1) {\n      first.cd[0] = first.cd[1];\n      first.cd[1] = second.cd[0];\n    }\n  }\n};\n\ntemplate<> struct conj_helper<Packet1cd, Packet1cd, false,true>\n{\n  EIGEN_STRONG_INLINE Packet1cd pmadd(const Packet1cd& x, const Packet1cd& y, const Packet1cd& c) const\n  { return padd(pmul(x,y),c); }\n\n  EIGEN_STRONG_INLINE Packet1cd pmul(const Packet1cd& a, const Packet1cd& b) const\n  {\n    return internal::pmul(a, pconj(b));\n  }\n};\n\ntemplate<> struct conj_helper<Packet1cd, Packet1cd, true,false>\n{\n  EIGEN_STRONG_INLINE Packet1cd pmadd(const Packet1cd& x, const Packet1cd& y, const Packet1cd& c) const\n  { return padd(pmul(x,y),c); }\n\n  EIGEN_STRONG_INLINE Packet1cd pmul(const Packet1cd& a, const Packet1cd& b) const\n  {\n    return internal::pmul(pconj(a), b);\n  }\n};\n\ntemplate<> struct conj_helper<Packet1cd, Packet1cd, true,true>\n{\n  EIGEN_STRONG_INLINE Packet1cd pmadd(const Packet1cd& x, const Packet1cd& y, const Packet1cd& c) const\n  { return padd(pmul(x,y),c); }\n\n  EIGEN_STRONG_INLINE Packet1cd pmul(const Packet1cd& a, const Packet1cd& b) const\n  {\n    return pconj(internal::pmul(a, b));\n  }\n};\n\ntemplate<> struct conj_helper<Packet2cf, Packet2cf, false,true>\n{\n  EIGEN_STRONG_INLINE Packet2cf pmadd(const Packet2cf& x, const Packet2cf& y, const Packet2cf& c) const\n  { return padd(pmul(x,y),c); }\n\n  EIGEN_STRONG_INLINE Packet2cf pmul(const Packet2cf& a, const Packet2cf& b) const\n  {\n    return internal::pmul(a, pconj(b));\n  }\n};\n\ntemplate<> struct conj_helper<Packet2cf, Packet2cf, true,false>\n{\n  EIGEN_STRONG_INLINE Packet2cf pmadd(const Packet2cf& x, const Packet2cf& y, const Packet2cf& c) const\n  { return padd(pmul(x,y),c); }\n\n  EIGEN_STRONG_INLINE Packet2cf pmul(const Packet2cf& a, const Packet2cf& b) const\n  {\n    return internal::pmul(pconj(a), b);\n  }\n};\n\ntemplate<> struct conj_helper<Packet2cf, Packet2cf, true,true>\n{\n  EIGEN_STRONG_INLINE Packet2cf pmadd(const Packet2cf& x, const Packet2cf& y, const Packet2cf& c) const\n  { return padd(pmul(x,y),c); }\n\n  EIGEN_STRONG_INLINE Packet2cf pmul(const Packet2cf& a, const Packet2cf& b) const\n  {\n    return pconj(internal::pmul(a, b));\n  }\n};\n\ntemplate<> EIGEN_STRONG_INLINE Packet1cd pdiv<Packet1cd>(const Packet1cd& a, const Packet1cd& b)\n{\n  // TODO optimize it for AltiVec\n  Packet1cd res = conj_helper<Packet1cd,Packet1cd,false,true>().pmul(a,b);\n  Packet2d s = vec_madd(b.v, b.v, p2d_ZERO_);\n  return Packet1cd(pdiv(res.v, s + vec_perm(s, s, p16uc_REVERSE64)));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pdiv<Packet2cf>(const Packet2cf& a, const Packet2cf& b)\n{\n  // TODO optimize it for AltiVec\n  Packet2cf res;\n  res.cd[0] = pdiv<Packet1cd>(a.cd[0], b.cd[0]);\n  res.cd[1] = pdiv<Packet1cd>(a.cd[1], b.cd[1]);\n  return res;\n}\n\nEIGEN_STRONG_INLINE Packet1cd pcplxflip/*<Packet1cd>*/(const Packet1cd& x)\n{\n  return Packet1cd(preverse(Packet2d(x.v)));\n}\n\nEIGEN_STRONG_INLINE Packet2cf pcplxflip/*<Packet2cf>*/(const Packet2cf& x)\n{\n  Packet2cf res;\n  res.cd[0] = pcplxflip(x.cd[0]);\n  res.cd[1] = pcplxflip(x.cd[1]);\n  return res;\n}\n\nEIGEN_STRONG_INLINE void ptranspose(PacketBlock<Packet1cd,2>& kernel)\n{\n  Packet2d tmp = vec_perm(kernel.packet[0].v, kernel.packet[1].v, p16uc_TRANSPOSE64_HI);\n  kernel.packet[1].v = vec_perm(kernel.packet[0].v, kernel.packet[1].v, p16uc_TRANSPOSE64_LO);\n  kernel.packet[0].v = tmp;\n}\n\nEIGEN_STRONG_INLINE void ptranspose(PacketBlock<Packet2cf,2>& kernel)\n{\n  Packet1cd tmp = kernel.packet[0].cd[1];\n  kernel.packet[0].cd[1] = kernel.packet[1].cd[0];\n  kernel.packet[1].cd[0] = tmp;\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2cf pblend(const Selector<2>& ifPacket, const Packet2cf& thenPacket, const Packet2cf& elsePacket) {\n  Packet2cf result;\n  const Selector<4> ifPacket4 = { ifPacket.select[0], ifPacket.select[0], ifPacket.select[1], ifPacket.select[1] };\n  result.v = pblend<Packet4f>(ifPacket4, thenPacket.v, elsePacket.v);\n  return result;\n}\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_COMPLEX32_ALTIVEC_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/arch/ZVector/MathFunctions.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2007 Julien Pommier\n// Copyright (C) 2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2016 Konstantinos Margaritis <markos@freevec.org>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n/* The sin, cos, exp, and log functions of this file come from\n * Julien Pommier's sse math library: http://gruntthepeon.free.fr/ssemath/\n */\n\n#ifndef EIGEN_MATH_FUNCTIONS_ALTIVEC_H\n#define EIGEN_MATH_FUNCTIONS_ALTIVEC_H\n\nnamespace Eigen {\n\nnamespace internal {\n\nstatic _EIGEN_DECLARE_CONST_Packet2d(1 , 1.0);\nstatic _EIGEN_DECLARE_CONST_Packet2d(2 , 2.0);\nstatic _EIGEN_DECLARE_CONST_Packet2d(half, 0.5);\n\nstatic _EIGEN_DECLARE_CONST_Packet2d(exp_hi,  709.437);\nstatic _EIGEN_DECLARE_CONST_Packet2d(exp_lo, -709.436139303);\n\nstatic _EIGEN_DECLARE_CONST_Packet2d(cephes_LOG2EF, 1.4426950408889634073599);\n\nstatic _EIGEN_DECLARE_CONST_Packet2d(cephes_exp_p0, 1.26177193074810590878e-4);\nstatic _EIGEN_DECLARE_CONST_Packet2d(cephes_exp_p1, 3.02994407707441961300e-2);\nstatic _EIGEN_DECLARE_CONST_Packet2d(cephes_exp_p2, 9.99999999999999999910e-1);\n\nstatic _EIGEN_DECLARE_CONST_Packet2d(cephes_exp_q0, 3.00198505138664455042e-6);\nstatic _EIGEN_DECLARE_CONST_Packet2d(cephes_exp_q1, 2.52448340349684104192e-3);\nstatic _EIGEN_DECLARE_CONST_Packet2d(cephes_exp_q2, 2.27265548208155028766e-1);\nstatic _EIGEN_DECLARE_CONST_Packet2d(cephes_exp_q3, 2.00000000000000000009e0);\n\nstatic _EIGEN_DECLARE_CONST_Packet2d(cephes_exp_C1, 0.693145751953125);\nstatic _EIGEN_DECLARE_CONST_Packet2d(cephes_exp_C2, 1.42860682030941723212e-6);\n\ntemplate<> EIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED\nPacket2d pexp<Packet2d>(const Packet2d& _x)\n{\n  Packet2d x = _x;\n\n  Packet2d tmp, fx;\n  Packet2l emm0;\n\n  // clamp x\n  x = pmax(pmin(x, p2d_exp_hi), p2d_exp_lo);\n  /* express exp(x) as exp(g + n*log(2)) */\n  fx = pmadd(p2d_cephes_LOG2EF, x, p2d_half);\n\n  fx = vec_floor(fx);\n\n  tmp = pmul(fx, p2d_cephes_exp_C1);\n  Packet2d z = pmul(fx, p2d_cephes_exp_C2);\n  x = psub(x, tmp);\n  x = psub(x, z);\n\n  Packet2d x2 = pmul(x,x);\n\n  Packet2d px = p2d_cephes_exp_p0;\n  px = pmadd(px, x2, p2d_cephes_exp_p1);\n  px = pmadd(px, x2, p2d_cephes_exp_p2);\n  px = pmul (px, x);\n\n  Packet2d qx = p2d_cephes_exp_q0;\n  qx = pmadd(qx, x2, p2d_cephes_exp_q1);\n  qx = pmadd(qx, x2, p2d_cephes_exp_q2);\n  qx = pmadd(qx, x2, p2d_cephes_exp_q3);\n\n  x = pdiv(px,psub(qx,px));\n  x = pmadd(p2d_2,x,p2d_1);\n\n  // build 2^n\n  emm0 = vec_ctsl(fx, 0);\n\n  static const Packet2l p2l_1023 = { 1023, 1023 };\n  static const Packet2ul p2ul_52 = { 52, 52 };\n\n  emm0 = emm0 + p2l_1023;\n  emm0 = emm0 << reinterpret_cast<Packet2l>(p2ul_52);\n\n  // Altivec's max & min operators just drop silent NaNs. Check NaNs in \n  // inputs and return them unmodified.\n  Packet2ul isnumber_mask = reinterpret_cast<Packet2ul>(vec_cmpeq(_x, _x));\n  return vec_sel(_x, pmax(pmul(x, reinterpret_cast<Packet2d>(emm0)), _x),\n                 isnumber_mask);\n}\n\ntemplate<> EIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED\nPacket4f pexp<Packet4f>(const Packet4f& x)\n{\n  Packet4f res;\n  res.v4f[0] = pexp<Packet2d>(x.v4f[0]);\n  res.v4f[1] = pexp<Packet2d>(x.v4f[1]);\n  return res;\n}\n\ntemplate<> EIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED\nPacket2d psqrt<Packet2d>(const Packet2d& x)\n{\n  return  __builtin_s390_vfsqdb(x);\n}\n\ntemplate<> EIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED\nPacket4f psqrt<Packet4f>(const Packet4f& x)\n{\n  Packet4f res;\n  res.v4f[0] = psqrt<Packet2d>(x.v4f[0]);\n  res.v4f[1] = psqrt<Packet2d>(x.v4f[1]);\n  return res;\n}\n\ntemplate<> EIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED\nPacket2d prsqrt<Packet2d>(const Packet2d& x) {\n  // Unfortunately we can't use the much faster mm_rqsrt_pd since it only provides an approximation.\n  return pset1<Packet2d>(1.0) / psqrt<Packet2d>(x);\n}\n\ntemplate<> EIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS EIGEN_UNUSED\nPacket4f prsqrt<Packet4f>(const Packet4f& x) {\n  Packet4f res;\n  res.v4f[0] = prsqrt<Packet2d>(x.v4f[0]);\n  res.v4f[1] = prsqrt<Packet2d>(x.v4f[1]);\n  return res;\n}\n\n}  // end namespace internal\n\n}  // end namespace Eigen\n\n#endif  // EIGEN_MATH_FUNCTIONS_ALTIVEC_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/arch/ZVector/PacketMath.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2016 Konstantinos Margaritis <markos@freevec.org>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_PACKET_MATH_ZVECTOR_H\n#define EIGEN_PACKET_MATH_ZVECTOR_H\n\n#include <stdint.h>\n\nnamespace Eigen {\n\nnamespace internal {\n\n#ifndef EIGEN_CACHEFRIENDLY_PRODUCT_THRESHOLD\n#define EIGEN_CACHEFRIENDLY_PRODUCT_THRESHOLD 4\n#endif\n\n#ifndef EIGEN_HAS_SINGLE_INSTRUCTION_MADD\n#define EIGEN_HAS_SINGLE_INSTRUCTION_MADD\n#endif\n\n#ifndef EIGEN_HAS_SINGLE_INSTRUCTION_CJMADD\n#define EIGEN_HAS_SINGLE_INSTRUCTION_CJMADD\n#endif\n\n#ifndef EIGEN_ARCH_DEFAULT_NUMBER_OF_REGISTERS\n#define EIGEN_ARCH_DEFAULT_NUMBER_OF_REGISTERS  16\n#endif\n\ntypedef __vector int                 Packet4i;\ntypedef __vector unsigned int        Packet4ui;\ntypedef __vector __bool int          Packet4bi;\ntypedef __vector short int           Packet8i;\ntypedef __vector unsigned char       Packet16uc;\ntypedef __vector double              Packet2d;\ntypedef __vector unsigned long long  Packet2ul;\ntypedef __vector long long           Packet2l;\n\ntypedef struct {\n\tPacket2d  v4f[2];\n} Packet4f;\n\ntypedef union {\n  int32_t   i[4];\n  uint32_t ui[4];\n  int64_t   l[2];\n  uint64_t ul[2];\n  double    d[2];\n  Packet4i  v4i;\n  Packet4ui v4ui;\n  Packet2l  v2l;\n  Packet2ul v2ul;\n  Packet2d  v2d;\n} Packet;\n\n// We don't want to write the same code all the time, but we need to reuse the constants\n// and it doesn't really work to declare them global, so we define macros instead\n\n#define _EIGEN_DECLARE_CONST_FAST_Packet4i(NAME,X) \\\n  Packet4i p4i_##NAME = reinterpret_cast<Packet4i>(vec_splat_s32(X))\n\n#define _EIGEN_DECLARE_CONST_FAST_Packet2d(NAME,X) \\\n  Packet2d p2d_##NAME = reinterpret_cast<Packet2d>(vec_splat_s64(X))\n\n#define _EIGEN_DECLARE_CONST_FAST_Packet2l(NAME,X) \\\n  Packet2l p2l_##NAME = reinterpret_cast<Packet2l>(vec_splat_s64(X))\n\n#define _EIGEN_DECLARE_CONST_Packet4i(NAME,X) \\\n  Packet4i p4i_##NAME = pset1<Packet4i>(X)\n\n#define _EIGEN_DECLARE_CONST_Packet2d(NAME,X) \\\n  Packet2d p2d_##NAME = pset1<Packet2d>(X)\n\n#define _EIGEN_DECLARE_CONST_Packet2l(NAME,X) \\\n  Packet2l p2l_##NAME = pset1<Packet2l>(X)\n\n// These constants are endian-agnostic\n//static _EIGEN_DECLARE_CONST_FAST_Packet4i(ZERO, 0); //{ 0, 0, 0, 0,}\nstatic _EIGEN_DECLARE_CONST_FAST_Packet4i(ONE, 1); //{ 1, 1, 1, 1}\n\nstatic _EIGEN_DECLARE_CONST_FAST_Packet2d(ZERO, 0);\nstatic _EIGEN_DECLARE_CONST_FAST_Packet2l(ZERO, 0);\nstatic _EIGEN_DECLARE_CONST_FAST_Packet2l(ONE, 1);\n\nstatic Packet2d p2d_ONE = { 1.0, 1.0 }; \nstatic Packet2d p2d_ZERO_ = { -0.0, -0.0 };\n\nstatic Packet4i p4i_COUNTDOWN = { 0, 1, 2, 3 };\nstatic Packet4f p4f_COUNTDOWN = { 0.0, 1.0, 2.0, 3.0 };\nstatic Packet2d p2d_COUNTDOWN = reinterpret_cast<Packet2d>(vec_sld(reinterpret_cast<Packet16uc>(p2d_ZERO), reinterpret_cast<Packet16uc>(p2d_ONE), 8));\n\nstatic Packet16uc p16uc_PSET64_HI = { 0,1,2,3, 4,5,6,7, 0,1,2,3, 4,5,6,7 };\nstatic Packet16uc p16uc_DUPLICATE32_HI = { 0,1,2,3, 0,1,2,3, 4,5,6,7, 4,5,6,7 };\n\n// Mask alignment\n#define _EIGEN_MASK_ALIGNMENT\t0xfffffffffffffff0\n\n#define _EIGEN_ALIGNED_PTR(x)\t((ptrdiff_t)(x) & _EIGEN_MASK_ALIGNMENT)\n\n// Handle endianness properly while loading constants\n// Define global static constants:\n\nstatic Packet16uc p16uc_FORWARD =   { 0,1,2,3, 4,5,6,7, 8,9,10,11, 12,13,14,15 };\nstatic Packet16uc p16uc_REVERSE32 = { 12,13,14,15, 8,9,10,11, 4,5,6,7, 0,1,2,3 };\nstatic Packet16uc p16uc_REVERSE64 = { 8,9,10,11, 12,13,14,15, 0,1,2,3, 4,5,6,7 };\n\nstatic Packet16uc p16uc_PSET32_WODD   = vec_sld((Packet16uc) vec_splat((Packet4ui)p16uc_FORWARD, 0), (Packet16uc) vec_splat((Packet4ui)p16uc_FORWARD, 2), 8);//{ 0,1,2,3, 0,1,2,3, 8,9,10,11, 8,9,10,11 };\nstatic Packet16uc p16uc_PSET32_WEVEN  = vec_sld(p16uc_DUPLICATE32_HI, (Packet16uc) vec_splat((Packet4ui)p16uc_FORWARD, 3), 8);//{ 4,5,6,7, 4,5,6,7, 12,13,14,15, 12,13,14,15 };\n/*static Packet16uc p16uc_HALF64_0_16 = vec_sld((Packet16uc)p4i_ZERO, vec_splat((Packet16uc) vec_abs(p4i_MINUS16), 3), 8);      //{ 0,0,0,0, 0,0,0,0, 16,16,16,16, 16,16,16,16};\n\nstatic Packet16uc p16uc_PSET64_HI = (Packet16uc) vec_mergeh((Packet4ui)p16uc_PSET32_WODD, (Packet4ui)p16uc_PSET32_WEVEN);     //{ 0,1,2,3, 4,5,6,7, 0,1,2,3, 4,5,6,7 };*/\nstatic Packet16uc p16uc_PSET64_LO = (Packet16uc) vec_mergel((Packet4ui)p16uc_PSET32_WODD, (Packet4ui)p16uc_PSET32_WEVEN);     //{ 8,9,10,11, 12,13,14,15, 8,9,10,11, 12,13,14,15 };\n/*static Packet16uc p16uc_TRANSPOSE64_HI = vec_add(p16uc_PSET64_HI, p16uc_HALF64_0_16);                                         //{ 0,1,2,3, 4,5,6,7, 16,17,18,19, 20,21,22,23};\nstatic Packet16uc p16uc_TRANSPOSE64_LO = vec_add(p16uc_PSET64_LO, p16uc_HALF64_0_16);                                         //{ 8,9,10,11, 12,13,14,15, 24,25,26,27, 28,29,30,31};*/\nstatic Packet16uc p16uc_TRANSPOSE64_HI = { 0,1,2,3, 4,5,6,7, 16,17,18,19, 20,21,22,23};\nstatic Packet16uc p16uc_TRANSPOSE64_LO = { 8,9,10,11, 12,13,14,15, 24,25,26,27, 28,29,30,31};\n\n//static Packet16uc p16uc_COMPLEX32_REV = vec_sld(p16uc_REVERSE32, p16uc_REVERSE32, 8);                                         //{ 4,5,6,7, 0,1,2,3, 12,13,14,15, 8,9,10,11 };\n\n//static Packet16uc p16uc_COMPLEX32_REV2 = vec_sld(p16uc_FORWARD, p16uc_FORWARD, 8);                                            //{ 8,9,10,11, 12,13,14,15, 0,1,2,3, 4,5,6,7 };\n\n\n#if EIGEN_HAS_BUILTIN(__builtin_prefetch) || EIGEN_COMP_GNUC\n  #define EIGEN_ZVECTOR_PREFETCH(ADDR) __builtin_prefetch(ADDR);\n#else\n  #define EIGEN_ZVECTOR_PREFETCH(ADDR) asm( \"   pfd [%[addr]]\\n\" :: [addr] \"r\" (ADDR) : \"cc\" );\n#endif\n\ntemplate<> struct packet_traits<int>    : default_packet_traits\n{\n  typedef Packet4i type;\n  typedef Packet4i half;\n  enum {\n    Vectorizable = 1,\n    AlignedOnScalar = 1,\n    size = 4,\n    HasHalfPacket = 0,\n\n    HasAdd  = 1,\n    HasSub  = 1,\n    HasMul  = 1,\n    HasDiv  = 1,\n    HasBlend = 1\n  };\n};\n\ntemplate<> struct packet_traits<float> : default_packet_traits\n{\n  typedef Packet4f type;\n  typedef Packet4f half;\n  enum {\n    Vectorizable = 1,\n    AlignedOnScalar = 1,\n    size=4,\n    HasHalfPacket = 0,\n\n    HasAdd  = 1,\n    HasSub  = 1,\n    HasMul  = 1,\n    HasDiv  = 1,\n    HasMin  = 1,\n    HasMax  = 1,\n    HasAbs  = 1,\n    HasSin  = 0,\n    HasCos  = 0,\n    HasLog  = 0,\n    HasExp  = 1,\n    HasSqrt = 1,\n    HasRsqrt = 1,\n    HasRound = 1,\n    HasFloor = 1,\n    HasCeil = 1,\n    HasNegate = 1,\n    HasBlend = 1\n  };\n};\n\ntemplate<> struct packet_traits<double> : default_packet_traits\n{\n  typedef Packet2d type;\n  typedef Packet2d half;\n  enum {\n    Vectorizable = 1,\n    AlignedOnScalar = 1,\n    size=2,\n    HasHalfPacket = 1,\n\n    HasAdd  = 1,\n    HasSub  = 1,\n    HasMul  = 1,\n    HasDiv  = 1,\n    HasMin  = 1,\n    HasMax  = 1,\n    HasAbs  = 1,\n    HasSin  = 0,\n    HasCos  = 0,\n    HasLog  = 0,\n    HasExp  = 1,\n    HasSqrt = 1,\n    HasRsqrt = 1,\n    HasRound = 1,\n    HasFloor = 1,\n    HasCeil = 1,\n    HasNegate = 1,\n    HasBlend = 1\n  };\n};\n\ntemplate<> struct unpacket_traits<Packet4i> { typedef int    type; enum {size=4, alignment=Aligned16}; typedef Packet4i half; };\ntemplate<> struct unpacket_traits<Packet4f> { typedef float  type; enum {size=4, alignment=Aligned16}; typedef Packet4f half; };\ntemplate<> struct unpacket_traits<Packet2d> { typedef double type; enum {size=2, alignment=Aligned16}; typedef Packet2d half; };\n\n/* Forward declaration */\nEIGEN_DEVICE_FUNC inline void ptranspose(PacketBlock<Packet4f,4>& kernel);\n \ninline std::ostream & operator <<(std::ostream & s, const Packet4i & v)\n{\n  Packet vt;\n  vt.v4i = v;\n  s << vt.i[0] << \", \" << vt.i[1] << \", \" << vt.i[2] << \", \" << vt.i[3];\n  return s;\n}\n\ninline std::ostream & operator <<(std::ostream & s, const Packet4ui & v)\n{\n  Packet vt;\n  vt.v4ui = v;\n  s << vt.ui[0] << \", \" << vt.ui[1] << \", \" << vt.ui[2] << \", \" << vt.ui[3];\n  return s;\n}\n\ninline std::ostream & operator <<(std::ostream & s, const Packet2l & v)\n{\n  Packet vt;\n  vt.v2l = v;\n  s << vt.l[0] << \", \" << vt.l[1];\n  return s;\n}\n\ninline std::ostream & operator <<(std::ostream & s, const Packet2ul & v)\n{\n  Packet vt;\n  vt.v2ul = v;\n  s << vt.ul[0] << \", \" << vt.ul[1] ;\n  return s;\n}\n\ninline std::ostream & operator <<(std::ostream & s, const Packet2d & v)\n{\n  Packet vt;\n  vt.v2d = v;\n  s << vt.d[0] << \", \" << vt.d[1];\n  return s;\n}\n\n/* Helper function to simulate a vec_splat_packet4f\n */\ntemplate<int element> EIGEN_STRONG_INLINE Packet4f vec_splat_packet4f(const Packet4f&   from)\n{\n  Packet4f splat;\n  switch (element) {\n  case 0:\n    splat.v4f[0] = vec_splat(from.v4f[0], 0);\n    splat.v4f[1] = splat.v4f[0];\n    break;\n  case 1:\n    splat.v4f[0] = vec_splat(from.v4f[0], 1);\n    splat.v4f[1] = splat.v4f[0];\n    break;\n  case 2:\n    splat.v4f[0] = vec_splat(from.v4f[1], 0);\n    splat.v4f[1] = splat.v4f[0];\n    break;\n  case 3:\n    splat.v4f[0] = vec_splat(from.v4f[1], 1);\n    splat.v4f[1] = splat.v4f[0];\n    break;\n  }\n  return splat;\n}\n\ntemplate<int Offset>\nstruct palign_impl<Offset,Packet4i>\n{\n  static EIGEN_STRONG_INLINE void run(Packet4i& first, const Packet4i& second)\n  {\n    switch (Offset % 4) {\n    case 1:\n      first = vec_sld(first, second, 4); break;\n    case 2:\n      first = vec_sld(first, second, 8); break;\n    case 3:\n      first = vec_sld(first, second, 12); break;\n    }\n  }\n};\n\n/* This is a tricky one, we have to translate float alignment to vector elements of sizeof double\n */\ntemplate<int Offset>\nstruct palign_impl<Offset,Packet4f>\n{\n  static EIGEN_STRONG_INLINE void run(Packet4f& first, const Packet4f& second)\n  {\n    switch (Offset % 4) {\n    case 1:\n      first.v4f[0] = vec_sld(first.v4f[0], first.v4f[1], 8);\n      first.v4f[1] = vec_sld(first.v4f[1], second.v4f[0], 8);\n      break;\n    case 2:\n      first.v4f[0] = first.v4f[1];\n      first.v4f[1] = second.v4f[0];\n      break;\n    case 3:\n      first.v4f[0] = vec_sld(first.v4f[1],  second.v4f[0], 8);\n      first.v4f[1] = vec_sld(second.v4f[0], second.v4f[1], 8);\n      break;\n    }\n  }\n};\n\n\ntemplate<int Offset>\nstruct palign_impl<Offset,Packet2d>\n{\n  static EIGEN_STRONG_INLINE void run(Packet2d& first, const Packet2d& second)\n  {\n    if (Offset == 1)\n      first = reinterpret_cast<Packet2d>(vec_sld(reinterpret_cast<Packet4i>(first), reinterpret_cast<Packet4i>(second), 8));\n  }\n};\n\ntemplate<> EIGEN_STRONG_INLINE Packet4i pload<Packet4i>(const int*     from)\n{\n  // FIXME: No intrinsic yet\n  EIGEN_DEBUG_ALIGNED_LOAD\n  Packet *vfrom;\n  vfrom = (Packet *) from;\n  return vfrom->v4i;\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pload<Packet4f>(const float*   from)\n{\n  // FIXME: No intrinsic yet\n  EIGEN_DEBUG_ALIGNED_LOAD\n  Packet4f vfrom;\n  vfrom.v4f[0] = vec_ld2f(&from[0]);\n  vfrom.v4f[1] = vec_ld2f(&from[2]);\n  return vfrom;\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d pload<Packet2d>(const double* from)\n{\n  // FIXME: No intrinsic yet\n  EIGEN_DEBUG_ALIGNED_LOAD\n  Packet *vfrom;\n  vfrom = (Packet *) from;\n  return vfrom->v2d;\n}\n\ntemplate<> EIGEN_STRONG_INLINE void pstore<int>(int*       to, const Packet4i& from)\n{\n  // FIXME: No intrinsic yet\n  EIGEN_DEBUG_ALIGNED_STORE\n  Packet *vto;\n  vto = (Packet *) to;\n  vto->v4i = from;\n}\n\ntemplate<> EIGEN_STRONG_INLINE void pstore<float>(float*   to, const Packet4f& from)\n{\n  // FIXME: No intrinsic yet\n  EIGEN_DEBUG_ALIGNED_STORE\n  vec_st2f(from.v4f[0], &to[0]);\n  vec_st2f(from.v4f[1], &to[2]);\n}\n\n\ntemplate<> EIGEN_STRONG_INLINE void pstore<double>(double*   to, const Packet2d& from)\n{\n  // FIXME: No intrinsic yet\n  EIGEN_DEBUG_ALIGNED_STORE\n  Packet *vto;\n  vto = (Packet *) to;\n  vto->v2d = from;\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4i pset1<Packet4i>(const int&    from)\n{\n  return vec_splats(from);\n}\ntemplate<> EIGEN_STRONG_INLINE Packet2d pset1<Packet2d>(const double& from) {\n  return vec_splats(from);\n}\ntemplate<> EIGEN_STRONG_INLINE Packet4f pset1<Packet4f>(const float&    from)\n{\n  Packet4f to;\n  to.v4f[0] = pset1<Packet2d>(static_cast<const double&>(from));\n  to.v4f[1] = to.v4f[0];\n  return to;\n}\n\ntemplate<> EIGEN_STRONG_INLINE void\npbroadcast4<Packet4i>(const int *a,\n                      Packet4i& a0, Packet4i& a1, Packet4i& a2, Packet4i& a3)\n{\n  a3 = pload<Packet4i>(a);\n  a0 = vec_splat(a3, 0);\n  a1 = vec_splat(a3, 1);\n  a2 = vec_splat(a3, 2);\n  a3 = vec_splat(a3, 3);\n}\n\ntemplate<> EIGEN_STRONG_INLINE void\npbroadcast4<Packet4f>(const float *a,\n                      Packet4f& a0, Packet4f& a1, Packet4f& a2, Packet4f& a3)\n{\n  a3 = pload<Packet4f>(a);\n  a0 = vec_splat_packet4f<0>(a3);\n  a1 = vec_splat_packet4f<1>(a3);\n  a2 = vec_splat_packet4f<2>(a3);\n  a3 = vec_splat_packet4f<3>(a3);\n}\n\ntemplate<> EIGEN_STRONG_INLINE void\npbroadcast4<Packet2d>(const double *a,\n                      Packet2d& a0, Packet2d& a1, Packet2d& a2, Packet2d& a3)\n{\n  a1 = pload<Packet2d>(a);\n  a0 = vec_splat(a1, 0);\n  a1 = vec_splat(a1, 1);\n  a3 = pload<Packet2d>(a+2);\n  a2 = vec_splat(a3, 0);\n  a3 = vec_splat(a3, 1);\n}\n\ntemplate<> EIGEN_DEVICE_FUNC inline Packet4i pgather<int, Packet4i>(const int* from, Index stride)\n{\n  int EIGEN_ALIGN16 ai[4];\n  ai[0] = from[0*stride];\n  ai[1] = from[1*stride];\n  ai[2] = from[2*stride];\n  ai[3] = from[3*stride];\n return pload<Packet4i>(ai);\n}\n\ntemplate<> EIGEN_DEVICE_FUNC inline Packet4f pgather<float, Packet4f>(const float* from, Index stride)\n{\n  float EIGEN_ALIGN16 ai[4];\n  ai[0] = from[0*stride];\n  ai[1] = from[1*stride];\n  ai[2] = from[2*stride];\n  ai[3] = from[3*stride];\n return pload<Packet4f>(ai);\n}\n\ntemplate<> EIGEN_DEVICE_FUNC inline Packet2d pgather<double, Packet2d>(const double* from, Index stride)\n{\n  double EIGEN_ALIGN16 af[2];\n  af[0] = from[0*stride];\n  af[1] = from[1*stride];\n return pload<Packet2d>(af);\n}\n\ntemplate<> EIGEN_DEVICE_FUNC inline void pscatter<int, Packet4i>(int* to, const Packet4i& from, Index stride)\n{\n  int EIGEN_ALIGN16 ai[4];\n  pstore<int>((int *)ai, from);\n  to[0*stride] = ai[0];\n  to[1*stride] = ai[1];\n  to[2*stride] = ai[2];\n  to[3*stride] = ai[3];\n}\n\ntemplate<> EIGEN_DEVICE_FUNC inline void pscatter<float, Packet4f>(float* to, const Packet4f& from, Index stride)\n{\n  float EIGEN_ALIGN16 ai[4];\n  pstore<float>((float *)ai, from);\n  to[0*stride] = ai[0];\n  to[1*stride] = ai[1];\n  to[2*stride] = ai[2];\n  to[3*stride] = ai[3];\n}\n\ntemplate<> EIGEN_DEVICE_FUNC inline void pscatter<double, Packet2d>(double* to, const Packet2d& from, Index stride)\n{\n  double EIGEN_ALIGN16 af[2];\n  pstore<double>(af, from);\n  to[0*stride] = af[0];\n  to[1*stride] = af[1];\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4i padd<Packet4i>(const Packet4i& a, const Packet4i& b) { return (a + b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4f padd<Packet4f>(const Packet4f& a, const Packet4f& b)\n{\n  Packet4f c;\n  c.v4f[0] = a.v4f[0] + b.v4f[0];\n  c.v4f[1] = a.v4f[1] + b.v4f[1];\n  return c;\n}\ntemplate<> EIGEN_STRONG_INLINE Packet2d padd<Packet2d>(const Packet2d& a, const Packet2d& b) { return (a + b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4i psub<Packet4i>(const Packet4i& a, const Packet4i& b) { return (a - b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4f psub<Packet4f>(const Packet4f& a, const Packet4f& b)\n{\n  Packet4f c;\n  c.v4f[0] = a.v4f[0] - b.v4f[0];\n  c.v4f[1] = a.v4f[1] - b.v4f[1];\n  return c;\n}\ntemplate<> EIGEN_STRONG_INLINE Packet2d psub<Packet2d>(const Packet2d& a, const Packet2d& b) { return (a - b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4i pmul<Packet4i>(const Packet4i& a, const Packet4i& b) { return (a * b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4f pmul<Packet4f>(const Packet4f& a, const Packet4f& b)\n{\n  Packet4f c;\n  c.v4f[0] = a.v4f[0] * b.v4f[0];\n  c.v4f[1] = a.v4f[1] * b.v4f[1];\n  return c;\n}\ntemplate<> EIGEN_STRONG_INLINE Packet2d pmul<Packet2d>(const Packet2d& a, const Packet2d& b) { return (a * b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4i pdiv<Packet4i>(const Packet4i& a, const Packet4i& b) { return (a / b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4f pdiv<Packet4f>(const Packet4f& a, const Packet4f& b)\n{\n  Packet4f c;\n  c.v4f[0] = a.v4f[0] / b.v4f[0];\n  c.v4f[1] = a.v4f[1] / b.v4f[1];\n  return c;\n}\ntemplate<> EIGEN_STRONG_INLINE Packet2d pdiv<Packet2d>(const Packet2d& a, const Packet2d& b) { return (a / b); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4i pnegate(const Packet4i& a) { return (-a); }\ntemplate<> EIGEN_STRONG_INLINE Packet4f pnegate(const Packet4f& a)\n{\n  Packet4f c;\n  c.v4f[0] = -a.v4f[0];\n  c.v4f[1] = -a.v4f[1];\n  return c;\n}\ntemplate<> EIGEN_STRONG_INLINE Packet2d pnegate(const Packet2d& a) { return (-a); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4i pconj(const Packet4i& a) { return a; }\ntemplate<> EIGEN_STRONG_INLINE Packet4f pconj(const Packet4f& a) { return a; }\ntemplate<> EIGEN_STRONG_INLINE Packet2d pconj(const Packet2d& a) { return a; }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4i pmadd(const Packet4i& a, const Packet4i& b, const Packet4i& c) { return padd<Packet4i>(pmul<Packet4i>(a, b), c); }\ntemplate<> EIGEN_STRONG_INLINE Packet4f pmadd(const Packet4f& a, const Packet4f& b, const Packet4f& c)\n{\n  Packet4f res;\n  res.v4f[0] = vec_madd(a.v4f[0], b.v4f[0], c.v4f[0]);\n  res.v4f[1] = vec_madd(a.v4f[1], b.v4f[1], c.v4f[1]);\n  return res;\n}\ntemplate<> EIGEN_STRONG_INLINE Packet2d pmadd(const Packet2d& a, const Packet2d& b, const Packet2d& c) { return vec_madd(a, b, c); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4i plset<Packet4i>(const int& a)    { return padd<Packet4i>(pset1<Packet4i>(a), p4i_COUNTDOWN); }\ntemplate<> EIGEN_STRONG_INLINE Packet4f plset<Packet4f>(const float& a)  { return padd<Packet4f>(pset1<Packet4f>(a), p4f_COUNTDOWN); }\ntemplate<> EIGEN_STRONG_INLINE Packet2d plset<Packet2d>(const double& a) { return padd<Packet2d>(pset1<Packet2d>(a), p2d_COUNTDOWN); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4i pmin<Packet4i>(const Packet4i& a, const Packet4i& b) { return vec_min(a, b); }\ntemplate<> EIGEN_STRONG_INLINE Packet2d pmin<Packet2d>(const Packet2d& a, const Packet2d& b) { return vec_min(a, b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4f pmin<Packet4f>(const Packet4f& a, const Packet4f& b)\n{\n  Packet4f res;\n  res.v4f[0] = pmin(a.v4f[0], b.v4f[0]);\n  res.v4f[1] = pmin(a.v4f[1], b.v4f[1]);\n  return res;\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4i pmax<Packet4i>(const Packet4i& a, const Packet4i& b) { return vec_max(a, b); }\ntemplate<> EIGEN_STRONG_INLINE Packet2d pmax<Packet2d>(const Packet2d& a, const Packet2d& b) { return vec_max(a, b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4f pmax<Packet4f>(const Packet4f& a, const Packet4f& b)\n{\n  Packet4f res;\n  res.v4f[0] = pmax(a.v4f[0], b.v4f[0]);\n  res.v4f[1] = pmax(a.v4f[1], b.v4f[1]);\n  return res;\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4i pand<Packet4i>(const Packet4i& a, const Packet4i& b) { return vec_and(a, b); }\ntemplate<> EIGEN_STRONG_INLINE Packet2d pand<Packet2d>(const Packet2d& a, const Packet2d& b) { return vec_and(a, b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4f pand<Packet4f>(const Packet4f& a, const Packet4f& b)\n{\n  Packet4f res;\n  res.v4f[0] = pand(a.v4f[0], b.v4f[0]);\n  res.v4f[1] = pand(a.v4f[1], b.v4f[1]);\n  return res;\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4i por<Packet4i>(const Packet4i& a, const Packet4i& b) { return vec_or(a, b); }\ntemplate<> EIGEN_STRONG_INLINE Packet2d por<Packet2d>(const Packet2d& a, const Packet2d& b) { return vec_or(a, b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4f por<Packet4f>(const Packet4f& a, const Packet4f& b)\n{\n  Packet4f res;\n  res.v4f[0] = pand(a.v4f[0], b.v4f[0]);\n  res.v4f[1] = pand(a.v4f[1], b.v4f[1]);\n  return res;\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4i pxor<Packet4i>(const Packet4i& a, const Packet4i& b) { return vec_xor(a, b); }\ntemplate<> EIGEN_STRONG_INLINE Packet2d pxor<Packet2d>(const Packet2d& a, const Packet2d& b) { return vec_xor(a, b); }\ntemplate<> EIGEN_STRONG_INLINE Packet4f pxor<Packet4f>(const Packet4f& a, const Packet4f& b)\n{\n  Packet4f res;\n  res.v4f[0] = pand(a.v4f[0], b.v4f[0]);\n  res.v4f[1] = pand(a.v4f[1], b.v4f[1]);\n  return res;\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4i pandnot<Packet4i>(const Packet4i& a, const Packet4i& b) { return pand<Packet4i>(a, vec_nor(b, b)); }\ntemplate<> EIGEN_STRONG_INLINE Packet2d pandnot<Packet2d>(const Packet2d& a, const Packet2d& b) { return vec_and(a, vec_nor(b, b)); }\ntemplate<> EIGEN_STRONG_INLINE Packet4f pandnot<Packet4f>(const Packet4f& a, const Packet4f& b)\n{\n  Packet4f res;\n  res.v4f[0] = pandnot(a.v4f[0], b.v4f[0]);\n  res.v4f[1] = pandnot(a.v4f[1], b.v4f[1]);\n  return res;\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pround<Packet4f>(const Packet4f& a)\n{\n  Packet4f res;\n  res.v4f[0] = vec_round(a.v4f[0]);\n  res.v4f[1] = vec_round(a.v4f[1]);\n  return res;\n}\ntemplate<> EIGEN_STRONG_INLINE Packet2d pround<Packet2d>(const Packet2d& a) { return vec_round(a); }\ntemplate<> EIGEN_STRONG_INLINE Packet4f pceil<Packet4f>(const  Packet4f& a)\n{\n  Packet4f res;\n  res.v4f[0] = vec_ceil(a.v4f[0]);\n  res.v4f[1] = vec_ceil(a.v4f[1]);\n  return res;\n}\ntemplate<> EIGEN_STRONG_INLINE Packet2d pceil<Packet2d>(const  Packet2d& a) { return vec_ceil(a); }\ntemplate<> EIGEN_STRONG_INLINE Packet4f pfloor<Packet4f>(const Packet4f& a)\n{\n  Packet4f res;\n  res.v4f[0] = vec_floor(a.v4f[0]);\n  res.v4f[1] = vec_floor(a.v4f[1]);\n  return res;\n}\ntemplate<> EIGEN_STRONG_INLINE Packet2d pfloor<Packet2d>(const Packet2d& a) { return vec_floor(a); }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4i ploadu<Packet4i>(const int*       from) { return pload<Packet4i>(from); }\ntemplate<> EIGEN_STRONG_INLINE Packet4f ploadu<Packet4f>(const float*     from) { return pload<Packet4f>(from); }\ntemplate<> EIGEN_STRONG_INLINE Packet2d ploadu<Packet2d>(const double*    from) { return pload<Packet2d>(from); }\n\n\ntemplate<> EIGEN_STRONG_INLINE Packet4i ploaddup<Packet4i>(const int*     from)\n{\n  Packet4i p = pload<Packet4i>(from);\n  return vec_perm(p, p, p16uc_DUPLICATE32_HI);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f ploaddup<Packet4f>(const float*    from)\n{\n  Packet4f p = pload<Packet4f>(from);\n  p.v4f[1] = vec_splat(p.v4f[0], 1);\n  p.v4f[0] = vec_splat(p.v4f[0], 0);\n  return p;\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d ploaddup<Packet2d>(const double*   from)\n{\n  Packet2d p = pload<Packet2d>(from);\n  return vec_perm(p, p, p16uc_PSET64_HI);\n}\n\ntemplate<> EIGEN_STRONG_INLINE void pstoreu<int>(int*        to, const Packet4i& from) { pstore<int>(to, from); }\ntemplate<> EIGEN_STRONG_INLINE void pstoreu<float>(float*    to, const Packet4f& from) { pstore<float>(to, from); }\ntemplate<> EIGEN_STRONG_INLINE void pstoreu<double>(double*  to, const Packet2d& from) { pstore<double>(to, from); }\n\ntemplate<> EIGEN_STRONG_INLINE void prefetch<int>(const int*       addr) { EIGEN_ZVECTOR_PREFETCH(addr); }\ntemplate<> EIGEN_STRONG_INLINE void prefetch<float>(const float*   addr) { EIGEN_ZVECTOR_PREFETCH(addr); }\ntemplate<> EIGEN_STRONG_INLINE void prefetch<double>(const double* addr) { EIGEN_ZVECTOR_PREFETCH(addr); }\n\ntemplate<> EIGEN_STRONG_INLINE int    pfirst<Packet4i>(const Packet4i& a) { int    EIGEN_ALIGN16 x[4]; pstore(x, a); return x[0]; }\ntemplate<> EIGEN_STRONG_INLINE float  pfirst<Packet4f>(const Packet4f& a) { float  EIGEN_ALIGN16 x[2]; vec_st2f(a.v4f[0], &x[0]); return x[0]; }\ntemplate<> EIGEN_STRONG_INLINE double pfirst<Packet2d>(const Packet2d& a) { double EIGEN_ALIGN16 x[2]; pstore(x, a); return x[0]; }\n\ntemplate<> EIGEN_STRONG_INLINE Packet4i preverse(const Packet4i& a)\n{\n  return reinterpret_cast<Packet4i>(vec_perm(reinterpret_cast<Packet16uc>(a), reinterpret_cast<Packet16uc>(a), p16uc_REVERSE32));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d preverse(const Packet2d& a)\n{\n  return reinterpret_cast<Packet2d>(vec_perm(reinterpret_cast<Packet16uc>(a), reinterpret_cast<Packet16uc>(a), p16uc_REVERSE64));\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f preverse(const Packet4f& a)\n{\n  Packet4f rev;\n  rev.v4f[0] = preverse<Packet2d>(a.v4f[1]);\n  rev.v4f[1] = preverse<Packet2d>(a.v4f[0]);\n  return rev;\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4i pabs<Packet4i>(const Packet4i& a) { return vec_abs(a); }\ntemplate<> EIGEN_STRONG_INLINE Packet2d pabs<Packet2d>(const Packet2d& a) { return vec_abs(a); }\ntemplate<> EIGEN_STRONG_INLINE Packet4f pabs<Packet4f>(const Packet4f& a)\n{\n  Packet4f res;\n  res.v4f[0] = pabs(a.v4f[0]);\n  res.v4f[1] = pabs(a.v4f[1]);\n  return res;\n}\n\ntemplate<> EIGEN_STRONG_INLINE int predux<Packet4i>(const Packet4i& a)\n{\n  Packet4i b, sum;\n  b   = vec_sld(a, a, 8);\n  sum = padd<Packet4i>(a, b);\n  b   = vec_sld(sum, sum, 4);\n  sum = padd<Packet4i>(sum, b);\n  return pfirst(sum);\n}\n\ntemplate<> EIGEN_STRONG_INLINE double predux<Packet2d>(const Packet2d& a)\n{\n  Packet2d b, sum;\n  b   = reinterpret_cast<Packet2d>(vec_sld(reinterpret_cast<Packet4i>(a), reinterpret_cast<Packet4i>(a), 8));\n  sum = padd<Packet2d>(a, b);\n  return pfirst(sum);\n}\ntemplate<> EIGEN_STRONG_INLINE float predux<Packet4f>(const Packet4f& a)\n{\n  Packet2d sum;\n  sum = padd<Packet2d>(a.v4f[0], a.v4f[1]);\n  double first = predux<Packet2d>(sum);\n  return static_cast<float>(first);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4i preduxp<Packet4i>(const Packet4i* vecs)\n{\n  Packet4i v[4], sum[4];\n\n  // It's easier and faster to transpose then add as columns\n  // Check: http://www.freevec.org/function/matrix_4x4_transpose_floats for explanation\n  // Do the transpose, first set of moves\n  v[0] = vec_mergeh(vecs[0], vecs[2]);\n  v[1] = vec_mergel(vecs[0], vecs[2]);\n  v[2] = vec_mergeh(vecs[1], vecs[3]);\n  v[3] = vec_mergel(vecs[1], vecs[3]);\n  // Get the resulting vectors\n  sum[0] = vec_mergeh(v[0], v[2]);\n  sum[1] = vec_mergel(v[0], v[2]);\n  sum[2] = vec_mergeh(v[1], v[3]);\n  sum[3] = vec_mergel(v[1], v[3]);\n\n  // Now do the summation:\n  // Lines 0+1\n  sum[0] = padd<Packet4i>(sum[0], sum[1]);\n  // Lines 2+3\n  sum[1] = padd<Packet4i>(sum[2], sum[3]);\n  // Add the results\n  sum[0] = padd<Packet4i>(sum[0], sum[1]);\n\n  return sum[0];\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d preduxp<Packet2d>(const Packet2d* vecs)\n{\n  Packet2d v[2], sum;\n  v[0] = padd<Packet2d>(vecs[0], reinterpret_cast<Packet2d>(vec_sld(reinterpret_cast<Packet4ui>(vecs[0]), reinterpret_cast<Packet4ui>(vecs[0]), 8)));\n  v[1] = padd<Packet2d>(vecs[1], reinterpret_cast<Packet2d>(vec_sld(reinterpret_cast<Packet4ui>(vecs[1]), reinterpret_cast<Packet4ui>(vecs[1]), 8)));\n \n  sum = reinterpret_cast<Packet2d>(vec_sld(reinterpret_cast<Packet4ui>(v[0]), reinterpret_cast<Packet4ui>(v[1]), 8));\n\n  return sum;\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f preduxp<Packet4f>(const Packet4f* vecs)\n{\n  PacketBlock<Packet4f,4> transpose;\n  transpose.packet[0] = vecs[0];\n  transpose.packet[1] = vecs[1];\n  transpose.packet[2] = vecs[2];\n  transpose.packet[3] = vecs[3];\n  ptranspose(transpose);\n\n  Packet4f sum = padd(transpose.packet[0], transpose.packet[1]);\n  sum = padd(sum, transpose.packet[2]);\n  sum = padd(sum, transpose.packet[3]);\n  return sum;\n}\n\n// Other reduction functions:\n// mul\ntemplate<> EIGEN_STRONG_INLINE int predux_mul<Packet4i>(const Packet4i& a)\n{\n  EIGEN_ALIGN16 int aux[4];\n  pstore(aux, a);\n  return aux[0] * aux[1] * aux[2] * aux[3];\n}\n\ntemplate<> EIGEN_STRONG_INLINE double predux_mul<Packet2d>(const Packet2d& a)\n{\n  return pfirst(pmul(a, reinterpret_cast<Packet2d>(vec_sld(reinterpret_cast<Packet4i>(a), reinterpret_cast<Packet4i>(a), 8))));\n}\n\ntemplate<> EIGEN_STRONG_INLINE float predux_mul<Packet4f>(const Packet4f& a)\n{\n  // Return predux_mul<Packet2d> of the subvectors product\n  return static_cast<float>(pfirst(predux_mul(pmul(a.v4f[0], a.v4f[1]))));\n}\n\n// min\ntemplate<> EIGEN_STRONG_INLINE int predux_min<Packet4i>(const Packet4i& a)\n{\n  Packet4i b, res;\n  b   = pmin<Packet4i>(a, vec_sld(a, a, 8));\n  res = pmin<Packet4i>(b, vec_sld(b, b, 4));\n  return pfirst(res);\n}\n\ntemplate<> EIGEN_STRONG_INLINE double predux_min<Packet2d>(const Packet2d& a)\n{\n  return pfirst(pmin<Packet2d>(a, reinterpret_cast<Packet2d>(vec_sld(reinterpret_cast<Packet4i>(a), reinterpret_cast<Packet4i>(a), 8))));\n}\n\ntemplate<> EIGEN_STRONG_INLINE float predux_min<Packet4f>(const Packet4f& a)\n{\n  Packet2d b, res;\n  b   = pmin<Packet2d>(a.v4f[0], a.v4f[1]);\n  res = pmin<Packet2d>(b, reinterpret_cast<Packet2d>(vec_sld(reinterpret_cast<Packet4i>(b), reinterpret_cast<Packet4i>(b), 8)));\n  return static_cast<float>(pfirst(res));\n}\n\n// max\ntemplate<> EIGEN_STRONG_INLINE int predux_max<Packet4i>(const Packet4i& a)\n{\n  Packet4i b, res;\n  b = pmax<Packet4i>(a, vec_sld(a, a, 8));\n  res = pmax<Packet4i>(b, vec_sld(b, b, 4));\n  return pfirst(res);\n}\n\n// max\ntemplate<> EIGEN_STRONG_INLINE double predux_max<Packet2d>(const Packet2d& a)\n{\n  return pfirst(pmax<Packet2d>(a, reinterpret_cast<Packet2d>(vec_sld(reinterpret_cast<Packet4i>(a), reinterpret_cast<Packet4i>(a), 8))));\n}\n\ntemplate<> EIGEN_STRONG_INLINE float predux_max<Packet4f>(const Packet4f& a)\n{\n  Packet2d b, res;\n  b   = pmax<Packet2d>(a.v4f[0], a.v4f[1]);\n  res = pmax<Packet2d>(b, reinterpret_cast<Packet2d>(vec_sld(reinterpret_cast<Packet4i>(b), reinterpret_cast<Packet4i>(b), 8)));\n  return static_cast<float>(pfirst(res));\n}\n\nEIGEN_DEVICE_FUNC inline void\nptranspose(PacketBlock<Packet4i,4>& kernel) {\n  Packet4i t0 = vec_mergeh(kernel.packet[0], kernel.packet[2]);\n  Packet4i t1 = vec_mergel(kernel.packet[0], kernel.packet[2]);\n  Packet4i t2 = vec_mergeh(kernel.packet[1], kernel.packet[3]);\n  Packet4i t3 = vec_mergel(kernel.packet[1], kernel.packet[3]);\n  kernel.packet[0] = vec_mergeh(t0, t2);\n  kernel.packet[1] = vec_mergel(t0, t2);\n  kernel.packet[2] = vec_mergeh(t1, t3);\n  kernel.packet[3] = vec_mergel(t1, t3);\n}\n\nEIGEN_DEVICE_FUNC inline void\nptranspose(PacketBlock<Packet2d,2>& kernel) {\n  Packet2d t0 = vec_perm(kernel.packet[0], kernel.packet[1], p16uc_TRANSPOSE64_HI);\n  Packet2d t1 = vec_perm(kernel.packet[0], kernel.packet[1], p16uc_TRANSPOSE64_LO);\n  kernel.packet[0] = t0;\n  kernel.packet[1] = t1;\n}\n\n/* Split the Packet4f PacketBlock into 4 Packet2d PacketBlocks and transpose each one\n */\nEIGEN_DEVICE_FUNC inline void\nptranspose(PacketBlock<Packet4f,4>& kernel) {\n  PacketBlock<Packet2d,2> t0,t1,t2,t3;\n  // copy top-left 2x2 Packet2d block\n  t0.packet[0] = kernel.packet[0].v4f[0];\n  t0.packet[1] = kernel.packet[1].v4f[0];\n\n  // copy top-right 2x2 Packet2d block\n  t1.packet[0] = kernel.packet[0].v4f[1];\n  t1.packet[1] = kernel.packet[1].v4f[1];\n\n  // copy bottom-left 2x2 Packet2d block\n  t2.packet[0] = kernel.packet[2].v4f[0];\n  t2.packet[1] = kernel.packet[3].v4f[0];\n\n  // copy bottom-right 2x2 Packet2d block\n  t3.packet[0] = kernel.packet[2].v4f[1];\n  t3.packet[1] = kernel.packet[3].v4f[1];\n\n  // Transpose all 2x2 blocks\n  ptranspose(t0);\n  ptranspose(t1);\n  ptranspose(t2);\n  ptranspose(t3);\n\n  // Copy back transposed blocks, but exchange t1 and t2 due to transposition\n  kernel.packet[0].v4f[0] = t0.packet[0];\n  kernel.packet[0].v4f[1] = t2.packet[0];\n  kernel.packet[1].v4f[0] = t0.packet[1];\n  kernel.packet[1].v4f[1] = t2.packet[1];\n  kernel.packet[2].v4f[0] = t1.packet[0];\n  kernel.packet[2].v4f[1] = t3.packet[0];\n  kernel.packet[3].v4f[0] = t1.packet[1];\n  kernel.packet[3].v4f[1] = t3.packet[1];\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4i pblend(const Selector<4>& ifPacket, const Packet4i& thenPacket, const Packet4i& elsePacket) {\n  Packet4ui select = { ifPacket.select[0], ifPacket.select[1], ifPacket.select[2], ifPacket.select[3] };\n  Packet4ui mask = vec_cmpeq(select, reinterpret_cast<Packet4ui>(p4i_ONE));\n  return vec_sel(elsePacket, thenPacket, mask);\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet4f pblend(const Selector<4>& ifPacket, const Packet4f& thenPacket, const Packet4f& elsePacket) {\n  Packet2ul select_hi = { ifPacket.select[0], ifPacket.select[1] };\n  Packet2ul select_lo = { ifPacket.select[2], ifPacket.select[3] };\n  Packet2ul mask_hi = vec_cmpeq(select_hi, reinterpret_cast<Packet2ul>(p2l_ONE));\n  Packet2ul mask_lo = vec_cmpeq(select_lo, reinterpret_cast<Packet2ul>(p2l_ONE));\n  Packet4f result;\n  result.v4f[0] = vec_sel(elsePacket.v4f[0], thenPacket.v4f[0], mask_hi);\n  result.v4f[1] = vec_sel(elsePacket.v4f[1], thenPacket.v4f[1], mask_lo);\n  return result;\n}\n\ntemplate<> EIGEN_STRONG_INLINE Packet2d pblend(const Selector<2>& ifPacket, const Packet2d& thenPacket, const Packet2d& elsePacket) {\n  Packet2ul select = { ifPacket.select[0], ifPacket.select[1] };\n  Packet2ul mask = vec_cmpeq(select, reinterpret_cast<Packet2ul>(p2l_ONE));\n  return vec_sel(elsePacket, thenPacket, mask);\n}\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_PACKET_MATH_ZVECTOR_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/functors/AssignmentFunctors.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_ASSIGNMENT_FUNCTORS_H\n#define EIGEN_ASSIGNMENT_FUNCTORS_H\n\nnamespace Eigen {\n\nnamespace internal {\n  \n/** \\internal\n  * \\brief Template functor for scalar/packet assignment\n  *\n  */\ntemplate<typename DstScalar,typename SrcScalar> struct assign_op {\n\n  EIGEN_EMPTY_STRUCT_CTOR(assign_op)\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE void assignCoeff(DstScalar& a, const SrcScalar& b) const { a = b; }\n  \n  template<int Alignment, typename Packet>\n  EIGEN_STRONG_INLINE void assignPacket(DstScalar* a, const Packet& b) const\n  { internal::pstoret<DstScalar,Packet,Alignment>(a,b); }\n};\n\n// Empty overload for void type (used by PermutationMatrix\ntemplate<typename DstScalar> struct assign_op<DstScalar,void> {};\n\ntemplate<typename DstScalar,typename SrcScalar>\nstruct functor_traits<assign_op<DstScalar,SrcScalar> > {\n  enum {\n    Cost = NumTraits<DstScalar>::ReadCost,\n    PacketAccess = is_same<DstScalar,SrcScalar>::value && packet_traits<DstScalar>::Vectorizable && packet_traits<SrcScalar>::Vectorizable\n  };\n};\n\n/** \\internal\n  * \\brief Template functor for scalar/packet assignment with addition\n  *\n  */\ntemplate<typename DstScalar,typename SrcScalar> struct add_assign_op {\n\n  EIGEN_EMPTY_STRUCT_CTOR(add_assign_op)\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE void assignCoeff(DstScalar& a, const SrcScalar& b) const { a += b; }\n  \n  template<int Alignment, typename Packet>\n  EIGEN_STRONG_INLINE void assignPacket(DstScalar* a, const Packet& b) const\n  { internal::pstoret<DstScalar,Packet,Alignment>(a,internal::padd(internal::ploadt<Packet,Alignment>(a),b)); }\n};\ntemplate<typename DstScalar,typename SrcScalar>\nstruct functor_traits<add_assign_op<DstScalar,SrcScalar> > {\n  enum {\n    Cost = NumTraits<DstScalar>::ReadCost + NumTraits<DstScalar>::AddCost,\n    PacketAccess = is_same<DstScalar,SrcScalar>::value && packet_traits<DstScalar>::HasAdd\n  };\n};\n\n/** \\internal\n  * \\brief Template functor for scalar/packet assignment with subtraction\n  *\n  */\ntemplate<typename DstScalar,typename SrcScalar> struct sub_assign_op {\n\n  EIGEN_EMPTY_STRUCT_CTOR(sub_assign_op)\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE void assignCoeff(DstScalar& a, const SrcScalar& b) const { a -= b; }\n  \n  template<int Alignment, typename Packet>\n  EIGEN_STRONG_INLINE void assignPacket(DstScalar* a, const Packet& b) const\n  { internal::pstoret<DstScalar,Packet,Alignment>(a,internal::psub(internal::ploadt<Packet,Alignment>(a),b)); }\n};\ntemplate<typename DstScalar,typename SrcScalar>\nstruct functor_traits<sub_assign_op<DstScalar,SrcScalar> > {\n  enum {\n    Cost = NumTraits<DstScalar>::ReadCost + NumTraits<DstScalar>::AddCost,\n    PacketAccess = is_same<DstScalar,SrcScalar>::value && packet_traits<DstScalar>::HasSub\n  };\n};\n\n/** \\internal\n  * \\brief Template functor for scalar/packet assignment with multiplication\n  *\n  */\ntemplate<typename DstScalar, typename SrcScalar=DstScalar>\nstruct mul_assign_op {\n\n  EIGEN_EMPTY_STRUCT_CTOR(mul_assign_op)\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE void assignCoeff(DstScalar& a, const SrcScalar& b) const { a *= b; }\n  \n  template<int Alignment, typename Packet>\n  EIGEN_STRONG_INLINE void assignPacket(DstScalar* a, const Packet& b) const\n  { internal::pstoret<DstScalar,Packet,Alignment>(a,internal::pmul(internal::ploadt<Packet,Alignment>(a),b)); }\n};\ntemplate<typename DstScalar, typename SrcScalar>\nstruct functor_traits<mul_assign_op<DstScalar,SrcScalar> > {\n  enum {\n    Cost = NumTraits<DstScalar>::ReadCost + NumTraits<DstScalar>::MulCost,\n    PacketAccess = is_same<DstScalar,SrcScalar>::value && packet_traits<DstScalar>::HasMul\n  };\n};\n\n/** \\internal\n  * \\brief Template functor for scalar/packet assignment with diviving\n  *\n  */\ntemplate<typename DstScalar, typename SrcScalar=DstScalar> struct div_assign_op {\n\n  EIGEN_EMPTY_STRUCT_CTOR(div_assign_op)\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE void assignCoeff(DstScalar& a, const SrcScalar& b) const { a /= b; }\n  \n  template<int Alignment, typename Packet>\n  EIGEN_STRONG_INLINE void assignPacket(DstScalar* a, const Packet& b) const\n  { internal::pstoret<DstScalar,Packet,Alignment>(a,internal::pdiv(internal::ploadt<Packet,Alignment>(a),b)); }\n};\ntemplate<typename DstScalar, typename SrcScalar>\nstruct functor_traits<div_assign_op<DstScalar,SrcScalar> > {\n  enum {\n    Cost = NumTraits<DstScalar>::ReadCost + NumTraits<DstScalar>::MulCost,\n    PacketAccess = is_same<DstScalar,SrcScalar>::value && packet_traits<DstScalar>::HasDiv\n  };\n};\n\n/** \\internal\n  * \\brief Template functor for scalar/packet assignment with swapping\n  *\n  * It works as follow. For a non-vectorized evaluation loop, we have:\n  *   for(i) func(A.coeffRef(i), B.coeff(i));\n  * where B is a SwapWrapper expression. The trick is to make SwapWrapper::coeff behaves like a non-const coeffRef.\n  * Actually, SwapWrapper might not even be needed since even if B is a plain expression, since it has to be writable\n  * B.coeff already returns a const reference to the underlying scalar value.\n  * \n  * The case of a vectorized loop is more tricky:\n  *   for(i,j) func.assignPacket<A_Align>(&A.coeffRef(i,j), B.packet<B_Align>(i,j));\n  * Here, B must be a SwapWrapper whose packet function actually returns a proxy object holding a Scalar*,\n  * the actual alignment and Packet type.\n  *\n  */\ntemplate<typename Scalar> struct swap_assign_op {\n\n  EIGEN_EMPTY_STRUCT_CTOR(swap_assign_op)\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE void assignCoeff(Scalar& a, const Scalar& b) const\n  {\n#ifdef __CUDACC__\n    // FIXME is there some kind of cuda::swap?\n    Scalar t=b; const_cast<Scalar&>(b)=a; a=t;\n#else\n    using std::swap;\n    swap(a,const_cast<Scalar&>(b));\n#endif\n  }\n};\ntemplate<typename Scalar>\nstruct functor_traits<swap_assign_op<Scalar> > {\n  enum {\n    Cost = 3 * NumTraits<Scalar>::ReadCost,\n    PacketAccess = packet_traits<Scalar>::Vectorizable\n  };\n};\n\n} // namespace internal\n\n} // namespace Eigen\n\n#endif // EIGEN_ASSIGNMENT_FUNCTORS_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/functors/BinaryFunctors.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_BINARY_FUNCTORS_H\n#define EIGEN_BINARY_FUNCTORS_H\n\nnamespace Eigen {\n\nnamespace internal {\n\n//---------- associative binary functors ----------\n\ntemplate<typename Arg1, typename Arg2>\nstruct binary_op_base\n{\n  typedef Arg1 first_argument_type;\n  typedef Arg2 second_argument_type;\n};\n\n/** \\internal\n  * \\brief Template functor to compute the sum of two scalars\n  *\n  * \\sa class CwiseBinaryOp, MatrixBase::operator+, class VectorwiseOp, DenseBase::sum()\n  */\ntemplate<typename LhsScalar,typename RhsScalar>\nstruct scalar_sum_op : binary_op_base<LhsScalar,RhsScalar>\n{\n  typedef typename ScalarBinaryOpTraits<LhsScalar,RhsScalar,scalar_sum_op>::ReturnType result_type;\n#ifndef EIGEN_SCALAR_BINARY_OP_PLUGIN\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_sum_op)\n#else\n  scalar_sum_op() {\n    EIGEN_SCALAR_BINARY_OP_PLUGIN\n  }\n#endif\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const result_type operator() (const LhsScalar& a, const RhsScalar& b) const { return a + b; }\n  template<typename Packet>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const Packet packetOp(const Packet& a, const Packet& b) const\n  { return internal::padd(a,b); }\n  template<typename Packet>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const result_type predux(const Packet& a) const\n  { return internal::predux(a); }\n};\ntemplate<typename LhsScalar,typename RhsScalar>\nstruct functor_traits<scalar_sum_op<LhsScalar,RhsScalar> > {\n  enum {\n    Cost = (NumTraits<LhsScalar>::AddCost+NumTraits<RhsScalar>::AddCost)/2, // rough estimate!\n    PacketAccess = is_same<LhsScalar,RhsScalar>::value && packet_traits<LhsScalar>::HasAdd && packet_traits<RhsScalar>::HasAdd\n    // TODO vectorize mixed sum\n  };\n};\n\n/** \\internal\n  * \\brief Template specialization to deprecate the summation of boolean expressions.\n  * This is required to solve Bug 426.\n  * \\sa DenseBase::count(), DenseBase::any(), ArrayBase::cast(), MatrixBase::cast()\n  */\ntemplate<> struct scalar_sum_op<bool,bool> : scalar_sum_op<int,int> {\n  EIGEN_DEPRECATED\n  scalar_sum_op() {}\n};\n\n\n/** \\internal\n  * \\brief Template functor to compute the product of two scalars\n  *\n  * \\sa class CwiseBinaryOp, Cwise::operator*(), class VectorwiseOp, MatrixBase::redux()\n  */\ntemplate<typename LhsScalar,typename RhsScalar>\nstruct scalar_product_op  : binary_op_base<LhsScalar,RhsScalar>\n{\n  typedef typename ScalarBinaryOpTraits<LhsScalar,RhsScalar,scalar_product_op>::ReturnType result_type;\n#ifndef EIGEN_SCALAR_BINARY_OP_PLUGIN\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_product_op)\n#else\n  scalar_product_op() {\n    EIGEN_SCALAR_BINARY_OP_PLUGIN\n  }\n#endif\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const result_type operator() (const LhsScalar& a, const RhsScalar& b) const { return a * b; }\n  template<typename Packet>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const Packet packetOp(const Packet& a, const Packet& b) const\n  { return internal::pmul(a,b); }\n  template<typename Packet>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const result_type predux(const Packet& a) const\n  { return internal::predux_mul(a); }\n};\ntemplate<typename LhsScalar,typename RhsScalar>\nstruct functor_traits<scalar_product_op<LhsScalar,RhsScalar> > {\n  enum {\n    Cost = (NumTraits<LhsScalar>::MulCost + NumTraits<RhsScalar>::MulCost)/2, // rough estimate!\n    PacketAccess = is_same<LhsScalar,RhsScalar>::value && packet_traits<LhsScalar>::HasMul && packet_traits<RhsScalar>::HasMul\n    // TODO vectorize mixed product\n  };\n};\n\n/** \\internal\n  * \\brief Template functor to compute the conjugate product of two scalars\n  *\n  * This is a short cut for conj(x) * y which is needed for optimization purpose; in Eigen2 support mode, this becomes x * conj(y)\n  */\ntemplate<typename LhsScalar,typename RhsScalar>\nstruct scalar_conj_product_op  : binary_op_base<LhsScalar,RhsScalar>\n{\n\n  enum {\n    Conj = NumTraits<LhsScalar>::IsComplex\n  };\n  \n  typedef typename ScalarBinaryOpTraits<LhsScalar,RhsScalar,scalar_conj_product_op>::ReturnType result_type;\n  \n  EIGEN_EMPTY_STRUCT_CTOR(scalar_conj_product_op)\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const result_type operator() (const LhsScalar& a, const RhsScalar& b) const\n  { return conj_helper<LhsScalar,RhsScalar,Conj,false>().pmul(a,b); }\n  \n  template<typename Packet>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const Packet packetOp(const Packet& a, const Packet& b) const\n  { return conj_helper<Packet,Packet,Conj,false>().pmul(a,b); }\n};\ntemplate<typename LhsScalar,typename RhsScalar>\nstruct functor_traits<scalar_conj_product_op<LhsScalar,RhsScalar> > {\n  enum {\n    Cost = NumTraits<LhsScalar>::MulCost,\n    PacketAccess = internal::is_same<LhsScalar, RhsScalar>::value && packet_traits<LhsScalar>::HasMul\n  };\n};\n\n/** \\internal\n  * \\brief Template functor to compute the min of two scalars\n  *\n  * \\sa class CwiseBinaryOp, MatrixBase::cwiseMin, class VectorwiseOp, MatrixBase::minCoeff()\n  */\ntemplate<typename LhsScalar,typename RhsScalar>\nstruct scalar_min_op : binary_op_base<LhsScalar,RhsScalar>\n{\n  typedef typename ScalarBinaryOpTraits<LhsScalar,RhsScalar,scalar_min_op>::ReturnType result_type;\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_min_op)\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const result_type operator() (const LhsScalar& a, const RhsScalar& b) const { return numext::mini(a, b); }\n  template<typename Packet>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const Packet packetOp(const Packet& a, const Packet& b) const\n  { return internal::pmin(a,b); }\n  template<typename Packet>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const result_type predux(const Packet& a) const\n  { return internal::predux_min(a); }\n};\ntemplate<typename LhsScalar,typename RhsScalar>\nstruct functor_traits<scalar_min_op<LhsScalar,RhsScalar> > {\n  enum {\n    Cost = (NumTraits<LhsScalar>::AddCost+NumTraits<RhsScalar>::AddCost)/2,\n    PacketAccess = internal::is_same<LhsScalar, RhsScalar>::value && packet_traits<LhsScalar>::HasMin\n  };\n};\n\n/** \\internal\n  * \\brief Template functor to compute the max of two scalars\n  *\n  * \\sa class CwiseBinaryOp, MatrixBase::cwiseMax, class VectorwiseOp, MatrixBase::maxCoeff()\n  */\ntemplate<typename LhsScalar,typename RhsScalar>\nstruct scalar_max_op  : binary_op_base<LhsScalar,RhsScalar>\n{\n  typedef typename ScalarBinaryOpTraits<LhsScalar,RhsScalar,scalar_max_op>::ReturnType result_type;\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_max_op)\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const result_type operator() (const LhsScalar& a, const RhsScalar& b) const { return numext::maxi(a, b); }\n  template<typename Packet>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const Packet packetOp(const Packet& a, const Packet& b) const\n  { return internal::pmax(a,b); }\n  template<typename Packet>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const result_type predux(const Packet& a) const\n  { return internal::predux_max(a); }\n};\ntemplate<typename LhsScalar,typename RhsScalar>\nstruct functor_traits<scalar_max_op<LhsScalar,RhsScalar> > {\n  enum {\n    Cost = (NumTraits<LhsScalar>::AddCost+NumTraits<RhsScalar>::AddCost)/2,\n    PacketAccess = internal::is_same<LhsScalar, RhsScalar>::value && packet_traits<LhsScalar>::HasMax\n  };\n};\n\n/** \\internal\n  * \\brief Template functors for comparison of two scalars\n  * \\todo Implement packet-comparisons\n  */\ntemplate<typename LhsScalar, typename RhsScalar, ComparisonName cmp> struct scalar_cmp_op;\n\ntemplate<typename LhsScalar, typename RhsScalar, ComparisonName cmp>\nstruct functor_traits<scalar_cmp_op<LhsScalar,RhsScalar, cmp> > {\n  enum {\n    Cost = (NumTraits<LhsScalar>::AddCost+NumTraits<RhsScalar>::AddCost)/2,\n    PacketAccess = false\n  };\n};\n\ntemplate<ComparisonName Cmp, typename LhsScalar, typename RhsScalar>\nstruct result_of<scalar_cmp_op<LhsScalar, RhsScalar, Cmp>(LhsScalar,RhsScalar)> {\n  typedef bool type;\n};\n\n\ntemplate<typename LhsScalar, typename RhsScalar>\nstruct scalar_cmp_op<LhsScalar,RhsScalar, cmp_EQ> : binary_op_base<LhsScalar,RhsScalar>\n{\n  typedef bool result_type;\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_cmp_op)\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE bool operator()(const LhsScalar& a, const RhsScalar& b) const {return a==b;}\n};\ntemplate<typename LhsScalar, typename RhsScalar>\nstruct scalar_cmp_op<LhsScalar,RhsScalar, cmp_LT> : binary_op_base<LhsScalar,RhsScalar>\n{\n  typedef bool result_type;\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_cmp_op)\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE bool operator()(const LhsScalar& a, const RhsScalar& b) const {return a<b;}\n};\ntemplate<typename LhsScalar, typename RhsScalar>\nstruct scalar_cmp_op<LhsScalar,RhsScalar, cmp_LE> : binary_op_base<LhsScalar,RhsScalar>\n{\n  typedef bool result_type;\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_cmp_op)\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE bool operator()(const LhsScalar& a, const RhsScalar& b) const {return a<=b;}\n};\ntemplate<typename LhsScalar, typename RhsScalar>\nstruct scalar_cmp_op<LhsScalar,RhsScalar, cmp_GT> : binary_op_base<LhsScalar,RhsScalar>\n{\n  typedef bool result_type;\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_cmp_op)\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE bool operator()(const LhsScalar& a, const RhsScalar& b) const {return a>b;}\n};\ntemplate<typename LhsScalar, typename RhsScalar>\nstruct scalar_cmp_op<LhsScalar,RhsScalar, cmp_GE> : binary_op_base<LhsScalar,RhsScalar>\n{\n  typedef bool result_type;\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_cmp_op)\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE bool operator()(const LhsScalar& a, const RhsScalar& b) const {return a>=b;}\n};\ntemplate<typename LhsScalar, typename RhsScalar>\nstruct scalar_cmp_op<LhsScalar,RhsScalar, cmp_UNORD> : binary_op_base<LhsScalar,RhsScalar>\n{\n  typedef bool result_type;\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_cmp_op)\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE bool operator()(const LhsScalar& a, const RhsScalar& b) const {return !(a<=b || b<=a);}\n};\ntemplate<typename LhsScalar, typename RhsScalar>\nstruct scalar_cmp_op<LhsScalar,RhsScalar, cmp_NEQ> : binary_op_base<LhsScalar,RhsScalar>\n{\n  typedef bool result_type;\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_cmp_op)\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE bool operator()(const LhsScalar& a, const RhsScalar& b) const {return a!=b;}\n};\n\n\n/** \\internal\n  * \\brief Template functor to compute the hypot of two scalars\n  *\n  * \\sa MatrixBase::stableNorm(), class Redux\n  */\ntemplate<typename Scalar>\nstruct scalar_hypot_op<Scalar,Scalar> : binary_op_base<Scalar,Scalar>\n{\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_hypot_op)\n//   typedef typename NumTraits<Scalar>::Real result_type;\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const Scalar operator() (const Scalar& _x, const Scalar& _y) const\n  {\n    EIGEN_USING_STD_MATH(sqrt)\n    Scalar p, qp;\n    if(_x>_y)\n    {\n      p = _x;\n      qp = _y / p;\n    }\n    else\n    {\n      p = _y;\n      qp = _x / p;\n    }\n    return p * sqrt(Scalar(1) + qp*qp);\n  }\n};\ntemplate<typename Scalar>\nstruct functor_traits<scalar_hypot_op<Scalar,Scalar> > {\n  enum\n  {\n    Cost = 3 * NumTraits<Scalar>::AddCost +\n           2 * NumTraits<Scalar>::MulCost +\n           2 * scalar_div_cost<Scalar,false>::value,\n    PacketAccess = false\n  };\n};\n\n/** \\internal\n  * \\brief Template functor to compute the pow of two scalars\n  */\ntemplate<typename Scalar, typename Exponent>\nstruct scalar_pow_op  : binary_op_base<Scalar,Exponent>\n{\n  typedef typename ScalarBinaryOpTraits<Scalar,Exponent,scalar_pow_op>::ReturnType result_type;\n#ifndef EIGEN_SCALAR_BINARY_OP_PLUGIN\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_pow_op)\n#else\n  scalar_pow_op() {\n    typedef Scalar LhsScalar;\n    typedef Exponent RhsScalar;\n    EIGEN_SCALAR_BINARY_OP_PLUGIN\n  }\n#endif\n  EIGEN_DEVICE_FUNC\n  inline result_type operator() (const Scalar& a, const Exponent& b) const { return numext::pow(a, b); }\n};\ntemplate<typename Scalar, typename Exponent>\nstruct functor_traits<scalar_pow_op<Scalar,Exponent> > {\n  enum { Cost = 5 * NumTraits<Scalar>::MulCost, PacketAccess = false };\n};\n\n\n\n//---------- non associative binary functors ----------\n\n/** \\internal\n  * \\brief Template functor to compute the difference of two scalars\n  *\n  * \\sa class CwiseBinaryOp, MatrixBase::operator-\n  */\ntemplate<typename LhsScalar,typename RhsScalar>\nstruct scalar_difference_op : binary_op_base<LhsScalar,RhsScalar>\n{\n  typedef typename ScalarBinaryOpTraits<LhsScalar,RhsScalar,scalar_difference_op>::ReturnType result_type;\n#ifndef EIGEN_SCALAR_BINARY_OP_PLUGIN\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_difference_op)\n#else\n  scalar_difference_op() {\n    EIGEN_SCALAR_BINARY_OP_PLUGIN\n  }\n#endif\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const result_type operator() (const LhsScalar& a, const RhsScalar& b) const { return a - b; }\n  template<typename Packet>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const Packet packetOp(const Packet& a, const Packet& b) const\n  { return internal::psub(a,b); }\n};\ntemplate<typename LhsScalar,typename RhsScalar>\nstruct functor_traits<scalar_difference_op<LhsScalar,RhsScalar> > {\n  enum {\n    Cost = (NumTraits<LhsScalar>::AddCost+NumTraits<RhsScalar>::AddCost)/2,\n    PacketAccess = is_same<LhsScalar,RhsScalar>::value && packet_traits<LhsScalar>::HasSub && packet_traits<RhsScalar>::HasSub\n  };\n};\n\n/** \\internal\n  * \\brief Template functor to compute the quotient of two scalars\n  *\n  * \\sa class CwiseBinaryOp, Cwise::operator/()\n  */\ntemplate<typename LhsScalar,typename RhsScalar>\nstruct scalar_quotient_op  : binary_op_base<LhsScalar,RhsScalar>\n{\n  typedef typename ScalarBinaryOpTraits<LhsScalar,RhsScalar,scalar_quotient_op>::ReturnType result_type;\n#ifndef EIGEN_SCALAR_BINARY_OP_PLUGIN\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_quotient_op)\n#else\n  scalar_quotient_op() {\n    EIGEN_SCALAR_BINARY_OP_PLUGIN\n  }\n#endif\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const result_type operator() (const LhsScalar& a, const RhsScalar& b) const { return a / b; }\n  template<typename Packet>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const Packet packetOp(const Packet& a, const Packet& b) const\n  { return internal::pdiv(a,b); }\n};\ntemplate<typename LhsScalar,typename RhsScalar>\nstruct functor_traits<scalar_quotient_op<LhsScalar,RhsScalar> > {\n  typedef typename scalar_quotient_op<LhsScalar,RhsScalar>::result_type result_type;\n  enum {\n    PacketAccess = is_same<LhsScalar,RhsScalar>::value && packet_traits<LhsScalar>::HasDiv && packet_traits<RhsScalar>::HasDiv,\n    Cost = scalar_div_cost<result_type,PacketAccess>::value\n  };\n};\n\n\n\n/** \\internal\n  * \\brief Template functor to compute the and of two booleans\n  *\n  * \\sa class CwiseBinaryOp, ArrayBase::operator&&\n  */\nstruct scalar_boolean_and_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_boolean_and_op)\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE bool operator() (const bool& a, const bool& b) const { return a && b; }\n};\ntemplate<> struct functor_traits<scalar_boolean_and_op> {\n  enum {\n    Cost = NumTraits<bool>::AddCost,\n    PacketAccess = false\n  };\n};\n\n/** \\internal\n  * \\brief Template functor to compute the or of two booleans\n  *\n  * \\sa class CwiseBinaryOp, ArrayBase::operator||\n  */\nstruct scalar_boolean_or_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_boolean_or_op)\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE bool operator() (const bool& a, const bool& b) const { return a || b; }\n};\ntemplate<> struct functor_traits<scalar_boolean_or_op> {\n  enum {\n    Cost = NumTraits<bool>::AddCost,\n    PacketAccess = false\n  };\n};\n\n/** \\internal\n * \\brief Template functor to compute the xor of two booleans\n *\n * \\sa class CwiseBinaryOp, ArrayBase::operator^\n */\nstruct scalar_boolean_xor_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_boolean_xor_op)\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE bool operator() (const bool& a, const bool& b) const { return a ^ b; }\n};\ntemplate<> struct functor_traits<scalar_boolean_xor_op> {\n  enum {\n    Cost = NumTraits<bool>::AddCost,\n    PacketAccess = false\n  };\n};\n\n\n\n//---------- binary functors bound to a constant, thus appearing as a unary functor ----------\n\n// The following two classes permits to turn any binary functor into a unary one with one argument bound to a constant value.\n// They are analogues to std::binder1st/binder2nd but with the following differences:\n//  - they are compatible with packetOp\n//  - they are portable across C++ versions (the std::binder* are deprecated in C++11)\ntemplate<typename BinaryOp> struct bind1st_op : BinaryOp {\n\n  typedef typename BinaryOp::first_argument_type  first_argument_type;\n  typedef typename BinaryOp::second_argument_type second_argument_type;\n  typedef typename BinaryOp::result_type          result_type;\n\n  bind1st_op(const first_argument_type &val) : m_value(val) {}\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const result_type operator() (const second_argument_type& b) const { return BinaryOp::operator()(m_value,b); }\n\n  template<typename Packet>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const Packet packetOp(const Packet& b) const\n  { return BinaryOp::packetOp(internal::pset1<Packet>(m_value), b); }\n\n  first_argument_type m_value;\n};\ntemplate<typename BinaryOp> struct functor_traits<bind1st_op<BinaryOp> > : functor_traits<BinaryOp> {};\n\n\ntemplate<typename BinaryOp> struct bind2nd_op : BinaryOp {\n\n  typedef typename BinaryOp::first_argument_type  first_argument_type;\n  typedef typename BinaryOp::second_argument_type second_argument_type;\n  typedef typename BinaryOp::result_type          result_type;\n\n  bind2nd_op(const second_argument_type &val) : m_value(val) {}\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const result_type operator() (const first_argument_type& a) const { return BinaryOp::operator()(a,m_value); }\n\n  template<typename Packet>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const Packet packetOp(const Packet& a) const\n  { return BinaryOp::packetOp(a,internal::pset1<Packet>(m_value)); }\n\n  second_argument_type m_value;\n};\ntemplate<typename BinaryOp> struct functor_traits<bind2nd_op<BinaryOp> > : functor_traits<BinaryOp> {};\n\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_BINARY_FUNCTORS_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/functors/NullaryFunctors.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2016 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_NULLARY_FUNCTORS_H\n#define EIGEN_NULLARY_FUNCTORS_H\n\nnamespace Eigen {\n\nnamespace internal {\n\ntemplate<typename Scalar>\nstruct scalar_constant_op {\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE scalar_constant_op(const scalar_constant_op& other) : m_other(other.m_other) { }\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE scalar_constant_op(const Scalar& other) : m_other(other) { }\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const Scalar operator() () const { return m_other; }\n  template<typename PacketType>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const PacketType packetOp() const { return internal::pset1<PacketType>(m_other); }\n  const Scalar m_other;\n};\ntemplate<typename Scalar>\nstruct functor_traits<scalar_constant_op<Scalar> >\n{ enum { Cost = 0 /* as the constant value should be loaded in register only once for the whole expression */,\n         PacketAccess = packet_traits<Scalar>::Vectorizable, IsRepeatable = true }; };\n\ntemplate<typename Scalar> struct scalar_identity_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_identity_op)\n  template<typename IndexType>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const Scalar operator() (IndexType row, IndexType col) const { return row==col ? Scalar(1) : Scalar(0); }\n};\ntemplate<typename Scalar>\nstruct functor_traits<scalar_identity_op<Scalar> >\n{ enum { Cost = NumTraits<Scalar>::AddCost, PacketAccess = false, IsRepeatable = true }; };\n\ntemplate <typename Scalar, typename Packet, bool IsInteger> struct linspaced_op_impl;\n\ntemplate <typename Scalar, typename Packet>\nstruct linspaced_op_impl<Scalar,Packet,/*IsInteger*/false>\n{\n  linspaced_op_impl(const Scalar& low, const Scalar& high, Index num_steps) :\n    m_low(low), m_high(high), m_size1(num_steps==1 ? 1 : num_steps-1), m_step(num_steps==1 ? Scalar() : (high-low)/Scalar(num_steps-1)),\n    m_interPacket(plset<Packet>(0)),\n    m_flip(numext::abs(high)<numext::abs(low))\n  {}\n\n  template<typename IndexType>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const Scalar operator() (IndexType i) const {\n    if(m_flip)\n      return (i==0)? m_low : (m_high - (m_size1-i)*m_step);\n    else\n      return (i==m_size1)? m_high : (m_low + i*m_step);\n  }\n\n  template<typename IndexType>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const Packet packetOp(IndexType i) const\n  {\n    // Principle:\n    // [low, ..., low] + ( [step, ..., step] * ( [i, ..., i] + [0, ..., size] ) )\n    if(m_flip)\n    {\n      Packet pi = padd(pset1<Packet>(Scalar(i-m_size1)),m_interPacket);\n      Packet res = padd(pset1<Packet>(m_high), pmul(pset1<Packet>(m_step), pi));\n      if(i==0)\n        res = pinsertfirst(res, m_low);\n      return res;\n    }\n    else\n    {\n      Packet pi = padd(pset1<Packet>(Scalar(i)),m_interPacket);\n      Packet res = padd(pset1<Packet>(m_low), pmul(pset1<Packet>(m_step), pi));\n      if(i==m_size1-unpacket_traits<Packet>::size+1)\n        res = pinsertlast(res, m_high);\n      return res;\n    }\n  }\n\n  const Scalar m_low;\n  const Scalar m_high;\n  const Index m_size1;\n  const Scalar m_step;\n  const Packet m_interPacket;\n  const bool m_flip;\n};\n\ntemplate <typename Scalar, typename Packet>\nstruct linspaced_op_impl<Scalar,Packet,/*IsInteger*/true>\n{\n  linspaced_op_impl(const Scalar& low, const Scalar& high, Index num_steps) :\n    m_low(low),\n    m_multiplier((high-low)/convert_index<Scalar>(num_steps<=1 ? 1 : num_steps-1)),\n    m_divisor(convert_index<Scalar>(num_steps+high-low)/(high-low+1)),\n    m_use_divisor((high+1)<(low+num_steps))\n  {}\n\n  template<typename IndexType>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE\n  const Scalar operator() (IndexType i) const\n  {\n    if(m_use_divisor) return m_low + convert_index<Scalar>(i)/m_divisor;\n    else              return m_low + convert_index<Scalar>(i)*m_multiplier;\n  }\n\n  const Scalar m_low;\n  const Scalar m_multiplier;\n  const Scalar m_divisor;\n  const bool m_use_divisor;\n};\n\n// ----- Linspace functor ----------------------------------------------------------------\n\n// Forward declaration (we default to random access which does not really give\n// us a speed gain when using packet access but it allows to use the functor in\n// nested expressions).\ntemplate <typename Scalar, typename PacketType> struct linspaced_op;\ntemplate <typename Scalar, typename PacketType> struct functor_traits< linspaced_op<Scalar,PacketType> >\n{\n  enum\n  {\n    Cost = 1,\n    PacketAccess =   (!NumTraits<Scalar>::IsInteger) && packet_traits<Scalar>::HasSetLinear && packet_traits<Scalar>::HasBlend,\n                  /*&& ((!NumTraits<Scalar>::IsInteger) || packet_traits<Scalar>::HasDiv),*/ // <- vectorization for integer is currently disabled\n    IsRepeatable = true\n  };\n};\ntemplate <typename Scalar, typename PacketType> struct linspaced_op\n{\n  linspaced_op(const Scalar& low, const Scalar& high, Index num_steps)\n    : impl((num_steps==1 ? high : low),high,num_steps)\n  {}\n\n  template<typename IndexType>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const Scalar operator() (IndexType i) const { return impl(i); }\n\n  template<typename Packet,typename IndexType>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const Packet packetOp(IndexType i) const { return impl.packetOp(i); }\n\n  // This proxy object handles the actual required temporaries and the different\n  // implementations (integer vs. floating point).\n  const linspaced_op_impl<Scalar,PacketType,NumTraits<Scalar>::IsInteger> impl;\n};\n\n// Linear access is automatically determined from the operator() prototypes available for the given functor.\n// If it exposes an operator()(i,j), then we assume the i and j coefficients are required independently\n// and linear access is not possible. In all other cases, linear access is enabled.\n// Users should not have to deal with this structure.\ntemplate<typename Functor> struct functor_has_linear_access { enum { ret = !has_binary_operator<Functor>::value }; };\n\n// For unreliable compilers, let's specialize the has_*ary_operator\n// helpers so that at least built-in nullary functors work fine.\n#if !( (EIGEN_COMP_MSVC>1600) || (EIGEN_GNUC_AT_LEAST(4,8)) || (EIGEN_COMP_ICC>=1600))\ntemplate<typename Scalar,typename IndexType>\nstruct has_nullary_operator<scalar_constant_op<Scalar>,IndexType> { enum { value = 1}; };\ntemplate<typename Scalar,typename IndexType>\nstruct has_unary_operator<scalar_constant_op<Scalar>,IndexType> { enum { value = 0}; };\ntemplate<typename Scalar,typename IndexType>\nstruct has_binary_operator<scalar_constant_op<Scalar>,IndexType> { enum { value = 0}; };\n\ntemplate<typename Scalar,typename IndexType>\nstruct has_nullary_operator<scalar_identity_op<Scalar>,IndexType> { enum { value = 0}; };\ntemplate<typename Scalar,typename IndexType>\nstruct has_unary_operator<scalar_identity_op<Scalar>,IndexType> { enum { value = 0}; };\ntemplate<typename Scalar,typename IndexType>\nstruct has_binary_operator<scalar_identity_op<Scalar>,IndexType> { enum { value = 1}; };\n\ntemplate<typename Scalar, typename PacketType,typename IndexType>\nstruct has_nullary_operator<linspaced_op<Scalar,PacketType>,IndexType> { enum { value = 0}; };\ntemplate<typename Scalar, typename PacketType,typename IndexType>\nstruct has_unary_operator<linspaced_op<Scalar,PacketType>,IndexType> { enum { value = 1}; };\ntemplate<typename Scalar, typename PacketType,typename IndexType>\nstruct has_binary_operator<linspaced_op<Scalar,PacketType>,IndexType> { enum { value = 0}; };\n\ntemplate<typename Scalar,typename IndexType>\nstruct has_nullary_operator<scalar_random_op<Scalar>,IndexType> { enum { value = 1}; };\ntemplate<typename Scalar,typename IndexType>\nstruct has_unary_operator<scalar_random_op<Scalar>,IndexType> { enum { value = 0}; };\ntemplate<typename Scalar,typename IndexType>\nstruct has_binary_operator<scalar_random_op<Scalar>,IndexType> { enum { value = 0}; };\n#endif\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_NULLARY_FUNCTORS_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/functors/StlFunctors.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_STL_FUNCTORS_H\n#define EIGEN_STL_FUNCTORS_H\n\nnamespace Eigen {\n\nnamespace internal {\n\n// default functor traits for STL functors:\n\ntemplate<typename T>\nstruct functor_traits<std::multiplies<T> >\n{ enum { Cost = NumTraits<T>::MulCost, PacketAccess = false }; };\n\ntemplate<typename T>\nstruct functor_traits<std::divides<T> >\n{ enum { Cost = NumTraits<T>::MulCost, PacketAccess = false }; };\n\ntemplate<typename T>\nstruct functor_traits<std::plus<T> >\n{ enum { Cost = NumTraits<T>::AddCost, PacketAccess = false }; };\n\ntemplate<typename T>\nstruct functor_traits<std::minus<T> >\n{ enum { Cost = NumTraits<T>::AddCost, PacketAccess = false }; };\n\ntemplate<typename T>\nstruct functor_traits<std::negate<T> >\n{ enum { Cost = NumTraits<T>::AddCost, PacketAccess = false }; };\n\ntemplate<typename T>\nstruct functor_traits<std::logical_or<T> >\n{ enum { Cost = 1, PacketAccess = false }; };\n\ntemplate<typename T>\nstruct functor_traits<std::logical_and<T> >\n{ enum { Cost = 1, PacketAccess = false }; };\n\ntemplate<typename T>\nstruct functor_traits<std::logical_not<T> >\n{ enum { Cost = 1, PacketAccess = false }; };\n\ntemplate<typename T>\nstruct functor_traits<std::greater<T> >\n{ enum { Cost = 1, PacketAccess = false }; };\n\ntemplate<typename T>\nstruct functor_traits<std::less<T> >\n{ enum { Cost = 1, PacketAccess = false }; };\n\ntemplate<typename T>\nstruct functor_traits<std::greater_equal<T> >\n{ enum { Cost = 1, PacketAccess = false }; };\n\ntemplate<typename T>\nstruct functor_traits<std::less_equal<T> >\n{ enum { Cost = 1, PacketAccess = false }; };\n\ntemplate<typename T>\nstruct functor_traits<std::equal_to<T> >\n{ enum { Cost = 1, PacketAccess = false }; };\n\ntemplate<typename T>\nstruct functor_traits<std::not_equal_to<T> >\n{ enum { Cost = 1, PacketAccess = false }; };\n\n#if(__cplusplus < 201103L)\n// std::binder* are deprecated since c++11 and will be removed in c++17\ntemplate<typename T>\nstruct functor_traits<std::binder2nd<T> >\n{ enum { Cost = functor_traits<T>::Cost, PacketAccess = false }; };\n\ntemplate<typename T>\nstruct functor_traits<std::binder1st<T> >\n{ enum { Cost = functor_traits<T>::Cost, PacketAccess = false }; };\n#endif\n\ntemplate<typename T>\nstruct functor_traits<std::unary_negate<T> >\n{ enum { Cost = 1 + functor_traits<T>::Cost, PacketAccess = false }; };\n\ntemplate<typename T>\nstruct functor_traits<std::binary_negate<T> >\n{ enum { Cost = 1 + functor_traits<T>::Cost, PacketAccess = false }; };\n\n#ifdef EIGEN_STDEXT_SUPPORT\n\ntemplate<typename T0,typename T1>\nstruct functor_traits<std::project1st<T0,T1> >\n{ enum { Cost = 0, PacketAccess = false }; };\n\ntemplate<typename T0,typename T1>\nstruct functor_traits<std::project2nd<T0,T1> >\n{ enum { Cost = 0, PacketAccess = false }; };\n\ntemplate<typename T0,typename T1>\nstruct functor_traits<std::select2nd<std::pair<T0,T1> > >\n{ enum { Cost = 0, PacketAccess = false }; };\n\ntemplate<typename T0,typename T1>\nstruct functor_traits<std::select1st<std::pair<T0,T1> > >\n{ enum { Cost = 0, PacketAccess = false }; };\n\ntemplate<typename T0,typename T1>\nstruct functor_traits<std::unary_compose<T0,T1> >\n{ enum { Cost = functor_traits<T0>::Cost + functor_traits<T1>::Cost, PacketAccess = false }; };\n\ntemplate<typename T0,typename T1,typename T2>\nstruct functor_traits<std::binary_compose<T0,T1,T2> >\n{ enum { Cost = functor_traits<T0>::Cost + functor_traits<T1>::Cost + functor_traits<T2>::Cost, PacketAccess = false }; };\n\n#endif // EIGEN_STDEXT_SUPPORT\n\n// allow to add new functors and specializations of functor_traits from outside Eigen.\n// this macro is really needed because functor_traits must be specialized after it is declared but before it is used...\n#ifdef EIGEN_FUNCTORS_PLUGIN\n#include EIGEN_FUNCTORS_PLUGIN\n#endif\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_STL_FUNCTORS_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/functors/TernaryFunctors.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2016 Eugene Brevdo <ebrevdo@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_TERNARY_FUNCTORS_H\n#define EIGEN_TERNARY_FUNCTORS_H\n\nnamespace Eigen {\n\nnamespace internal {\n\n//---------- associative ternary functors ----------\n\n\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_TERNARY_FUNCTORS_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/functors/UnaryFunctors.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2016 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_UNARY_FUNCTORS_H\n#define EIGEN_UNARY_FUNCTORS_H\n\nnamespace Eigen {\n\nnamespace internal {\n\n/** \\internal\n  * \\brief Template functor to compute the opposite of a scalar\n  *\n  * \\sa class CwiseUnaryOp, MatrixBase::operator-\n  */\ntemplate<typename Scalar> struct scalar_opposite_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_opposite_op)\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const Scalar operator() (const Scalar& a) const { return -a; }\n  template<typename Packet>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const Packet packetOp(const Packet& a) const\n  { return internal::pnegate(a); }\n};\ntemplate<typename Scalar>\nstruct functor_traits<scalar_opposite_op<Scalar> >\n{ enum {\n    Cost = NumTraits<Scalar>::AddCost,\n    PacketAccess = packet_traits<Scalar>::HasNegate };\n};\n\n/** \\internal\n  * \\brief Template functor to compute the absolute value of a scalar\n  *\n  * \\sa class CwiseUnaryOp, Cwise::abs\n  */\ntemplate<typename Scalar> struct scalar_abs_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_abs_op)\n  typedef typename NumTraits<Scalar>::Real result_type;\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const result_type operator() (const Scalar& a) const { return numext::abs(a); }\n  template<typename Packet>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const Packet packetOp(const Packet& a) const\n  { return internal::pabs(a); }\n};\ntemplate<typename Scalar>\nstruct functor_traits<scalar_abs_op<Scalar> >\n{\n  enum {\n    Cost = NumTraits<Scalar>::AddCost,\n    PacketAccess = packet_traits<Scalar>::HasAbs\n  };\n};\n\n/** \\internal\n  * \\brief Template functor to compute the score of a scalar, to chose a pivot\n  *\n  * \\sa class CwiseUnaryOp\n  */\ntemplate<typename Scalar> struct scalar_score_coeff_op : scalar_abs_op<Scalar>\n{\n  typedef void Score_is_abs;\n};\ntemplate<typename Scalar>\nstruct functor_traits<scalar_score_coeff_op<Scalar> > : functor_traits<scalar_abs_op<Scalar> > {};\n\n/* Avoid recomputing abs when we know the score and they are the same. Not a true Eigen functor.  */\ntemplate<typename Scalar, typename=void> struct abs_knowing_score\n{\n  EIGEN_EMPTY_STRUCT_CTOR(abs_knowing_score)\n  typedef typename NumTraits<Scalar>::Real result_type;\n  template<typename Score>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const result_type operator() (const Scalar& a, const Score&) const { return numext::abs(a); }\n};\ntemplate<typename Scalar> struct abs_knowing_score<Scalar, typename scalar_score_coeff_op<Scalar>::Score_is_abs>\n{\n  EIGEN_EMPTY_STRUCT_CTOR(abs_knowing_score)\n  typedef typename NumTraits<Scalar>::Real result_type;\n  template<typename Scal>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const result_type operator() (const Scal&, const result_type& a) const { return a; }\n};\n\n/** \\internal\n  * \\brief Template functor to compute the squared absolute value of a scalar\n  *\n  * \\sa class CwiseUnaryOp, Cwise::abs2\n  */\ntemplate<typename Scalar> struct scalar_abs2_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_abs2_op)\n  typedef typename NumTraits<Scalar>::Real result_type;\n  EIGEN_DEVICE_FUNC\n  EIGEN_STRONG_INLINE const result_type operator() (const Scalar& a) const { return numext::abs2(a); }\n  template<typename Packet>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const Packet packetOp(const Packet& a) const\n  { return internal::pmul(a,a); }\n};\ntemplate<typename Scalar>\nstruct functor_traits<scalar_abs2_op<Scalar> >\n{ enum { Cost = NumTraits<Scalar>::MulCost, PacketAccess = packet_traits<Scalar>::HasAbs2 }; };\n\n/** \\internal\n  * \\brief Template functor to compute the conjugate of a complex value\n  *\n  * \\sa class CwiseUnaryOp, MatrixBase::conjugate()\n  */\ntemplate<typename Scalar> struct scalar_conjugate_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_conjugate_op)\n  EIGEN_DEVICE_FUNC\n  EIGEN_STRONG_INLINE const Scalar operator() (const Scalar& a) const { using numext::conj; return conj(a); }\n  template<typename Packet>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const Packet packetOp(const Packet& a) const { return internal::pconj(a); }\n};\ntemplate<typename Scalar>\nstruct functor_traits<scalar_conjugate_op<Scalar> >\n{\n  enum {\n    Cost = NumTraits<Scalar>::IsComplex ? NumTraits<Scalar>::AddCost : 0,\n    PacketAccess = packet_traits<Scalar>::HasConj\n  };\n};\n\n/** \\internal\n  * \\brief Template functor to compute the phase angle of a complex\n  *\n  * \\sa class CwiseUnaryOp, Cwise::arg\n  */\ntemplate<typename Scalar> struct scalar_arg_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_arg_op)\n  typedef typename NumTraits<Scalar>::Real result_type;\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const result_type operator() (const Scalar& a) const { using numext::arg; return arg(a); }\n  template<typename Packet>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const Packet packetOp(const Packet& a) const\n  { return internal::parg(a); }\n};\ntemplate<typename Scalar>\nstruct functor_traits<scalar_arg_op<Scalar> >\n{\n  enum {\n    Cost = NumTraits<Scalar>::IsComplex ? 5 * NumTraits<Scalar>::MulCost : NumTraits<Scalar>::AddCost,\n    PacketAccess = packet_traits<Scalar>::HasArg\n  };\n};\n/** \\internal\n  * \\brief Template functor to cast a scalar to another type\n  *\n  * \\sa class CwiseUnaryOp, MatrixBase::cast()\n  */\ntemplate<typename Scalar, typename NewType>\nstruct scalar_cast_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_cast_op)\n  typedef NewType result_type;\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const NewType operator() (const Scalar& a) const { return cast<Scalar, NewType>(a); }\n};\ntemplate<typename Scalar, typename NewType>\nstruct functor_traits<scalar_cast_op<Scalar,NewType> >\n{ enum { Cost = is_same<Scalar, NewType>::value ? 0 : NumTraits<NewType>::AddCost, PacketAccess = false }; };\n\n/** \\internal\n  * \\brief Template functor to extract the real part of a complex\n  *\n  * \\sa class CwiseUnaryOp, MatrixBase::real()\n  */\ntemplate<typename Scalar>\nstruct scalar_real_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_real_op)\n  typedef typename NumTraits<Scalar>::Real result_type;\n  EIGEN_DEVICE_FUNC\n  EIGEN_STRONG_INLINE result_type operator() (const Scalar& a) const { return numext::real(a); }\n};\ntemplate<typename Scalar>\nstruct functor_traits<scalar_real_op<Scalar> >\n{ enum { Cost = 0, PacketAccess = false }; };\n\n/** \\internal\n  * \\brief Template functor to extract the imaginary part of a complex\n  *\n  * \\sa class CwiseUnaryOp, MatrixBase::imag()\n  */\ntemplate<typename Scalar>\nstruct scalar_imag_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_imag_op)\n  typedef typename NumTraits<Scalar>::Real result_type;\n  EIGEN_DEVICE_FUNC\n  EIGEN_STRONG_INLINE result_type operator() (const Scalar& a) const { return numext::imag(a); }\n};\ntemplate<typename Scalar>\nstruct functor_traits<scalar_imag_op<Scalar> >\n{ enum { Cost = 0, PacketAccess = false }; };\n\n/** \\internal\n  * \\brief Template functor to extract the real part of a complex as a reference\n  *\n  * \\sa class CwiseUnaryOp, MatrixBase::real()\n  */\ntemplate<typename Scalar>\nstruct scalar_real_ref_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_real_ref_op)\n  typedef typename NumTraits<Scalar>::Real result_type;\n  EIGEN_DEVICE_FUNC\n  EIGEN_STRONG_INLINE result_type& operator() (const Scalar& a) const { return numext::real_ref(*const_cast<Scalar*>(&a)); }\n};\ntemplate<typename Scalar>\nstruct functor_traits<scalar_real_ref_op<Scalar> >\n{ enum { Cost = 0, PacketAccess = false }; };\n\n/** \\internal\n  * \\brief Template functor to extract the imaginary part of a complex as a reference\n  *\n  * \\sa class CwiseUnaryOp, MatrixBase::imag()\n  */\ntemplate<typename Scalar>\nstruct scalar_imag_ref_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_imag_ref_op)\n  typedef typename NumTraits<Scalar>::Real result_type;\n  EIGEN_DEVICE_FUNC\n  EIGEN_STRONG_INLINE result_type& operator() (const Scalar& a) const { return numext::imag_ref(*const_cast<Scalar*>(&a)); }\n};\ntemplate<typename Scalar>\nstruct functor_traits<scalar_imag_ref_op<Scalar> >\n{ enum { Cost = 0, PacketAccess = false }; };\n\n/** \\internal\n  *\n  * \\brief Template functor to compute the exponential of a scalar\n  *\n  * \\sa class CwiseUnaryOp, Cwise::exp()\n  */\ntemplate<typename Scalar> struct scalar_exp_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_exp_op)\n  EIGEN_DEVICE_FUNC inline const Scalar operator() (const Scalar& a) const { return numext::exp(a); }\n  template <typename Packet>\n  EIGEN_DEVICE_FUNC inline Packet packetOp(const Packet& a) const { return internal::pexp(a); }\n};\ntemplate <typename Scalar>\nstruct functor_traits<scalar_exp_op<Scalar> > {\n  enum {\n    PacketAccess = packet_traits<Scalar>::HasExp,\n    // The following numbers are based on the AVX implementation.\n#ifdef EIGEN_VECTORIZE_FMA\n    // Haswell can issue 2 add/mul/madd per cycle.\n    Cost =\n    (sizeof(Scalar) == 4\n     // float: 8 pmadd, 4 pmul, 2 padd/psub, 6 other\n     ? (8 * NumTraits<Scalar>::AddCost + 6 * NumTraits<Scalar>::MulCost)\n     // double: 7 pmadd, 5 pmul, 3 padd/psub, 1 div,  13 other\n     : (14 * NumTraits<Scalar>::AddCost +\n        6 * NumTraits<Scalar>::MulCost +\n        scalar_div_cost<Scalar,packet_traits<Scalar>::HasDiv>::value))\n#else\n    Cost =\n    (sizeof(Scalar) == 4\n     // float: 7 pmadd, 6 pmul, 4 padd/psub, 10 other\n     ? (21 * NumTraits<Scalar>::AddCost + 13 * NumTraits<Scalar>::MulCost)\n     // double: 7 pmadd, 5 pmul, 3 padd/psub, 1 div,  13 other\n     : (23 * NumTraits<Scalar>::AddCost +\n        12 * NumTraits<Scalar>::MulCost +\n        scalar_div_cost<Scalar,packet_traits<Scalar>::HasDiv>::value))\n#endif\n  };\n};\n\n/** \\internal\n  *\n  * \\brief Template functor to compute the logarithm of a scalar\n  *\n  * \\sa class CwiseUnaryOp, ArrayBase::log()\n  */\ntemplate<typename Scalar> struct scalar_log_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_log_op)\n  EIGEN_DEVICE_FUNC inline const Scalar operator() (const Scalar& a) const { return numext::log(a); }\n  template <typename Packet>\n  EIGEN_DEVICE_FUNC inline Packet packetOp(const Packet& a) const { return internal::plog(a); }\n};\ntemplate <typename Scalar>\nstruct functor_traits<scalar_log_op<Scalar> > {\n  enum {\n    PacketAccess = packet_traits<Scalar>::HasLog,\n    Cost =\n    (PacketAccess\n     // The following numbers are based on the AVX implementation.\n#ifdef EIGEN_VECTORIZE_FMA\n     // 8 pmadd, 6 pmul, 8 padd/psub, 16 other, can issue 2 add/mul/madd per cycle.\n     ? (20 * NumTraits<Scalar>::AddCost + 7 * NumTraits<Scalar>::MulCost)\n#else\n     // 8 pmadd, 6 pmul, 8 padd/psub, 20 other\n     ? (36 * NumTraits<Scalar>::AddCost + 14 * NumTraits<Scalar>::MulCost)\n#endif\n     // Measured cost of std::log.\n     : sizeof(Scalar)==4 ? 40 : 85)\n  };\n};\n\n/** \\internal\n  *\n  * \\brief Template functor to compute the logarithm of 1 plus a scalar value\n  *\n  * \\sa class CwiseUnaryOp, ArrayBase::log1p()\n  */\ntemplate<typename Scalar> struct scalar_log1p_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_log1p_op)\n  EIGEN_DEVICE_FUNC inline const Scalar operator() (const Scalar& a) const { return numext::log1p(a); }\n  template <typename Packet>\n  EIGEN_DEVICE_FUNC inline Packet packetOp(const Packet& a) const { return internal::plog1p(a); }\n};\ntemplate <typename Scalar>\nstruct functor_traits<scalar_log1p_op<Scalar> > {\n  enum {\n    PacketAccess = packet_traits<Scalar>::HasLog1p,\n    Cost = functor_traits<scalar_log_op<Scalar> >::Cost // TODO measure cost of log1p\n  };\n};\n\n/** \\internal\n  *\n  * \\brief Template functor to compute the base-10 logarithm of a scalar\n  *\n  * \\sa class CwiseUnaryOp, Cwise::log10()\n  */\ntemplate<typename Scalar> struct scalar_log10_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_log10_op)\n  EIGEN_DEVICE_FUNC inline const Scalar operator() (const Scalar& a) const { EIGEN_USING_STD_MATH(log10) return log10(a); }\n  template <typename Packet>\n  EIGEN_DEVICE_FUNC inline Packet packetOp(const Packet& a) const { return internal::plog10(a); }\n};\ntemplate<typename Scalar>\nstruct functor_traits<scalar_log10_op<Scalar> >\n{ enum { Cost = 5 * NumTraits<Scalar>::MulCost, PacketAccess = packet_traits<Scalar>::HasLog10 }; };\n\n/** \\internal\n  * \\brief Template functor to compute the square root of a scalar\n  * \\sa class CwiseUnaryOp, Cwise::sqrt()\n  */\ntemplate<typename Scalar> struct scalar_sqrt_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_sqrt_op)\n  EIGEN_DEVICE_FUNC inline const Scalar operator() (const Scalar& a) const { return numext::sqrt(a); }\n  template <typename Packet>\n  EIGEN_DEVICE_FUNC inline Packet packetOp(const Packet& a) const { return internal::psqrt(a); }\n};\ntemplate <typename Scalar>\nstruct functor_traits<scalar_sqrt_op<Scalar> > {\n  enum {\n#if EIGEN_FAST_MATH\n    // The following numbers are based on the AVX implementation.\n    Cost = (sizeof(Scalar) == 8 ? 28\n                                // 4 pmul, 1 pmadd, 3 other\n                                : (3 * NumTraits<Scalar>::AddCost +\n                                   5 * NumTraits<Scalar>::MulCost)),\n#else\n    // The following numbers are based on min VSQRT throughput on Haswell.\n    Cost = (sizeof(Scalar) == 8 ? 28 : 14),\n#endif\n    PacketAccess = packet_traits<Scalar>::HasSqrt\n  };\n};\n\n/** \\internal\n  * \\brief Template functor to compute the reciprocal square root of a scalar\n  * \\sa class CwiseUnaryOp, Cwise::rsqrt()\n  */\ntemplate<typename Scalar> struct scalar_rsqrt_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_rsqrt_op)\n  EIGEN_DEVICE_FUNC inline const Scalar operator() (const Scalar& a) const { return Scalar(1)/numext::sqrt(a); }\n  template <typename Packet>\n  EIGEN_DEVICE_FUNC inline Packet packetOp(const Packet& a) const { return internal::prsqrt(a); }\n};\n\ntemplate<typename Scalar>\nstruct functor_traits<scalar_rsqrt_op<Scalar> >\n{ enum {\n    Cost = 5 * NumTraits<Scalar>::MulCost,\n    PacketAccess = packet_traits<Scalar>::HasRsqrt\n  };\n};\n\n/** \\internal\n  * \\brief Template functor to compute the cosine of a scalar\n  * \\sa class CwiseUnaryOp, ArrayBase::cos()\n  */\ntemplate<typename Scalar> struct scalar_cos_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_cos_op)\n  EIGEN_DEVICE_FUNC inline Scalar operator() (const Scalar& a) const { return numext::cos(a); }\n  template <typename Packet>\n  EIGEN_DEVICE_FUNC inline Packet packetOp(const Packet& a) const { return internal::pcos(a); }\n};\ntemplate<typename Scalar>\nstruct functor_traits<scalar_cos_op<Scalar> >\n{\n  enum {\n    Cost = 5 * NumTraits<Scalar>::MulCost,\n    PacketAccess = packet_traits<Scalar>::HasCos\n  };\n};\n\n/** \\internal\n  * \\brief Template functor to compute the sine of a scalar\n  * \\sa class CwiseUnaryOp, ArrayBase::sin()\n  */\ntemplate<typename Scalar> struct scalar_sin_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_sin_op)\n  EIGEN_DEVICE_FUNC inline const Scalar operator() (const Scalar& a) const { return numext::sin(a); }\n  template <typename Packet>\n  EIGEN_DEVICE_FUNC inline Packet packetOp(const Packet& a) const { return internal::psin(a); }\n};\ntemplate<typename Scalar>\nstruct functor_traits<scalar_sin_op<Scalar> >\n{\n  enum {\n    Cost = 5 * NumTraits<Scalar>::MulCost,\n    PacketAccess = packet_traits<Scalar>::HasSin\n  };\n};\n\n\n/** \\internal\n  * \\brief Template functor to compute the tan of a scalar\n  * \\sa class CwiseUnaryOp, ArrayBase::tan()\n  */\ntemplate<typename Scalar> struct scalar_tan_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_tan_op)\n  EIGEN_DEVICE_FUNC inline const Scalar operator() (const Scalar& a) const { return numext::tan(a); }\n  template <typename Packet>\n  EIGEN_DEVICE_FUNC inline Packet packetOp(const Packet& a) const { return internal::ptan(a); }\n};\ntemplate<typename Scalar>\nstruct functor_traits<scalar_tan_op<Scalar> >\n{\n  enum {\n    Cost = 5 * NumTraits<Scalar>::MulCost,\n    PacketAccess = packet_traits<Scalar>::HasTan\n  };\n};\n\n/** \\internal\n  * \\brief Template functor to compute the arc cosine of a scalar\n  * \\sa class CwiseUnaryOp, ArrayBase::acos()\n  */\ntemplate<typename Scalar> struct scalar_acos_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_acos_op)\n  EIGEN_DEVICE_FUNC inline const Scalar operator() (const Scalar& a) const { return numext::acos(a); }\n  template <typename Packet>\n  EIGEN_DEVICE_FUNC inline Packet packetOp(const Packet& a) const { return internal::pacos(a); }\n};\ntemplate<typename Scalar>\nstruct functor_traits<scalar_acos_op<Scalar> >\n{\n  enum {\n    Cost = 5 * NumTraits<Scalar>::MulCost,\n    PacketAccess = packet_traits<Scalar>::HasACos\n  };\n};\n\n/** \\internal\n  * \\brief Template functor to compute the arc sine of a scalar\n  * \\sa class CwiseUnaryOp, ArrayBase::asin()\n  */\ntemplate<typename Scalar> struct scalar_asin_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_asin_op)\n  EIGEN_DEVICE_FUNC inline const Scalar operator() (const Scalar& a) const { return numext::asin(a); }\n  template <typename Packet>\n  EIGEN_DEVICE_FUNC inline Packet packetOp(const Packet& a) const { return internal::pasin(a); }\n};\ntemplate<typename Scalar>\nstruct functor_traits<scalar_asin_op<Scalar> >\n{\n  enum {\n    Cost = 5 * NumTraits<Scalar>::MulCost,\n    PacketAccess = packet_traits<Scalar>::HasASin\n  };\n};\n\n\n/** \\internal\n  * \\brief Template functor to compute the atan of a scalar\n  * \\sa class CwiseUnaryOp, ArrayBase::atan()\n  */\ntemplate<typename Scalar> struct scalar_atan_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_atan_op)\n  EIGEN_DEVICE_FUNC inline const Scalar operator() (const Scalar& a) const { return numext::atan(a); }\n  template <typename Packet>\n  EIGEN_DEVICE_FUNC inline Packet packetOp(const Packet& a) const { return internal::patan(a); }\n};\ntemplate<typename Scalar>\nstruct functor_traits<scalar_atan_op<Scalar> >\n{\n  enum {\n    Cost = 5 * NumTraits<Scalar>::MulCost,\n    PacketAccess = packet_traits<Scalar>::HasATan\n  };\n};\n\n/** \\internal\n  * \\brief Template functor to compute the tanh of a scalar\n  * \\sa class CwiseUnaryOp, ArrayBase::tanh()\n  */\ntemplate <typename Scalar>\nstruct scalar_tanh_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_tanh_op)\n  EIGEN_DEVICE_FUNC inline const Scalar operator()(const Scalar& a) const { return numext::tanh(a); }\n  template <typename Packet>\n  EIGEN_DEVICE_FUNC inline Packet packetOp(const Packet& x) const { return ptanh(x); }\n};\n\ntemplate <typename Scalar>\nstruct functor_traits<scalar_tanh_op<Scalar> > {\n  enum {\n    PacketAccess = packet_traits<Scalar>::HasTanh,\n    Cost = ( (EIGEN_FAST_MATH && is_same<Scalar,float>::value)\n// The following numbers are based on the AVX implementation,\n#ifdef EIGEN_VECTORIZE_FMA\n                // Haswell can issue 2 add/mul/madd per cycle.\n                // 9 pmadd, 2 pmul, 1 div, 2 other\n                ? (2 * NumTraits<Scalar>::AddCost +\n                   6 * NumTraits<Scalar>::MulCost +\n                   scalar_div_cost<Scalar,packet_traits<Scalar>::HasDiv>::value)\n#else\n                ? (11 * NumTraits<Scalar>::AddCost +\n                   11 * NumTraits<Scalar>::MulCost +\n                   scalar_div_cost<Scalar,packet_traits<Scalar>::HasDiv>::value)\n#endif\n                // This number assumes a naive implementation of tanh\n                : (6 * NumTraits<Scalar>::AddCost +\n                   3 * NumTraits<Scalar>::MulCost +\n                   2 * scalar_div_cost<Scalar,packet_traits<Scalar>::HasDiv>::value +\n                   functor_traits<scalar_exp_op<Scalar> >::Cost))\n  };\n};\n\n/** \\internal\n  * \\brief Template functor to compute the sinh of a scalar\n  * \\sa class CwiseUnaryOp, ArrayBase::sinh()\n  */\ntemplate<typename Scalar> struct scalar_sinh_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_sinh_op)\n  EIGEN_DEVICE_FUNC inline const Scalar operator() (const Scalar& a) const { return numext::sinh(a); }\n  template <typename Packet>\n  EIGEN_DEVICE_FUNC inline Packet packetOp(const Packet& a) const { return internal::psinh(a); }\n};\ntemplate<typename Scalar>\nstruct functor_traits<scalar_sinh_op<Scalar> >\n{\n  enum {\n    Cost = 5 * NumTraits<Scalar>::MulCost,\n    PacketAccess = packet_traits<Scalar>::HasSinh\n  };\n};\n\n/** \\internal\n  * \\brief Template functor to compute the cosh of a scalar\n  * \\sa class CwiseUnaryOp, ArrayBase::cosh()\n  */\ntemplate<typename Scalar> struct scalar_cosh_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_cosh_op)\n  EIGEN_DEVICE_FUNC inline const Scalar operator() (const Scalar& a) const { return numext::cosh(a); }\n  template <typename Packet>\n  EIGEN_DEVICE_FUNC inline Packet packetOp(const Packet& a) const { return internal::pcosh(a); }\n};\ntemplate<typename Scalar>\nstruct functor_traits<scalar_cosh_op<Scalar> >\n{\n  enum {\n    Cost = 5 * NumTraits<Scalar>::MulCost,\n    PacketAccess = packet_traits<Scalar>::HasCosh\n  };\n};\n\n/** \\internal\n  * \\brief Template functor to compute the inverse of a scalar\n  * \\sa class CwiseUnaryOp, Cwise::inverse()\n  */\ntemplate<typename Scalar>\nstruct scalar_inverse_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_inverse_op)\n  EIGEN_DEVICE_FUNC inline Scalar operator() (const Scalar& a) const { return Scalar(1)/a; }\n  template<typename Packet>\n  EIGEN_DEVICE_FUNC inline const Packet packetOp(const Packet& a) const\n  { return internal::pdiv(pset1<Packet>(Scalar(1)),a); }\n};\ntemplate<typename Scalar>\nstruct functor_traits<scalar_inverse_op<Scalar> >\n{ enum { Cost = NumTraits<Scalar>::MulCost, PacketAccess = packet_traits<Scalar>::HasDiv }; };\n\n/** \\internal\n  * \\brief Template functor to compute the square of a scalar\n  * \\sa class CwiseUnaryOp, Cwise::square()\n  */\ntemplate<typename Scalar>\nstruct scalar_square_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_square_op)\n  EIGEN_DEVICE_FUNC inline Scalar operator() (const Scalar& a) const { return a*a; }\n  template<typename Packet>\n  EIGEN_DEVICE_FUNC inline const Packet packetOp(const Packet& a) const\n  { return internal::pmul(a,a); }\n};\ntemplate<typename Scalar>\nstruct functor_traits<scalar_square_op<Scalar> >\n{ enum { Cost = NumTraits<Scalar>::MulCost, PacketAccess = packet_traits<Scalar>::HasMul }; };\n\n/** \\internal\n  * \\brief Template functor to compute the cube of a scalar\n  * \\sa class CwiseUnaryOp, Cwise::cube()\n  */\ntemplate<typename Scalar>\nstruct scalar_cube_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_cube_op)\n  EIGEN_DEVICE_FUNC inline Scalar operator() (const Scalar& a) const { return a*a*a; }\n  template<typename Packet>\n  EIGEN_DEVICE_FUNC inline const Packet packetOp(const Packet& a) const\n  { return internal::pmul(a,pmul(a,a)); }\n};\ntemplate<typename Scalar>\nstruct functor_traits<scalar_cube_op<Scalar> >\n{ enum { Cost = 2*NumTraits<Scalar>::MulCost, PacketAccess = packet_traits<Scalar>::HasMul }; };\n\n/** \\internal\n  * \\brief Template functor to compute the rounded value of a scalar\n  * \\sa class CwiseUnaryOp, ArrayBase::round()\n  */\ntemplate<typename Scalar> struct scalar_round_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_round_op)\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const Scalar operator() (const Scalar& a) const { return numext::round(a); }\n  template <typename Packet>\n  EIGEN_DEVICE_FUNC inline Packet packetOp(const Packet& a) const { return internal::pround(a); }\n};\ntemplate<typename Scalar>\nstruct functor_traits<scalar_round_op<Scalar> >\n{\n  enum {\n    Cost = NumTraits<Scalar>::MulCost,\n    PacketAccess = packet_traits<Scalar>::HasRound\n  };\n};\n\n/** \\internal\n  * \\brief Template functor to compute the floor of a scalar\n  * \\sa class CwiseUnaryOp, ArrayBase::floor()\n  */\ntemplate<typename Scalar> struct scalar_floor_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_floor_op)\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const Scalar operator() (const Scalar& a) const { return numext::floor(a); }\n  template <typename Packet>\n  EIGEN_DEVICE_FUNC inline Packet packetOp(const Packet& a) const { return internal::pfloor(a); }\n};\ntemplate<typename Scalar>\nstruct functor_traits<scalar_floor_op<Scalar> >\n{\n  enum {\n    Cost = NumTraits<Scalar>::MulCost,\n    PacketAccess = packet_traits<Scalar>::HasFloor\n  };\n};\n\n/** \\internal\n  * \\brief Template functor to compute the ceil of a scalar\n  * \\sa class CwiseUnaryOp, ArrayBase::ceil()\n  */\ntemplate<typename Scalar> struct scalar_ceil_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_ceil_op)\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const Scalar operator() (const Scalar& a) const { return numext::ceil(a); }\n  template <typename Packet>\n  EIGEN_DEVICE_FUNC inline Packet packetOp(const Packet& a) const { return internal::pceil(a); }\n};\ntemplate<typename Scalar>\nstruct functor_traits<scalar_ceil_op<Scalar> >\n{\n  enum {\n    Cost = NumTraits<Scalar>::MulCost,\n    PacketAccess = packet_traits<Scalar>::HasCeil\n  };\n};\n\n/** \\internal\n  * \\brief Template functor to compute whether a scalar is NaN\n  * \\sa class CwiseUnaryOp, ArrayBase::isnan()\n  */\ntemplate<typename Scalar> struct scalar_isnan_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_isnan_op)\n  typedef bool result_type;\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE result_type operator() (const Scalar& a) const { return (numext::isnan)(a); }\n};\ntemplate<typename Scalar>\nstruct functor_traits<scalar_isnan_op<Scalar> >\n{\n  enum {\n    Cost = NumTraits<Scalar>::MulCost,\n    PacketAccess = false\n  };\n};\n\n/** \\internal\n  * \\brief Template functor to check whether a scalar is +/-inf\n  * \\sa class CwiseUnaryOp, ArrayBase::isinf()\n  */\ntemplate<typename Scalar> struct scalar_isinf_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_isinf_op)\n  typedef bool result_type;\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE result_type operator() (const Scalar& a) const { return (numext::isinf)(a); }\n};\ntemplate<typename Scalar>\nstruct functor_traits<scalar_isinf_op<Scalar> >\n{\n  enum {\n    Cost = NumTraits<Scalar>::MulCost,\n    PacketAccess = false\n  };\n};\n\n/** \\internal\n  * \\brief Template functor to check whether a scalar has a finite value\n  * \\sa class CwiseUnaryOp, ArrayBase::isfinite()\n  */\ntemplate<typename Scalar> struct scalar_isfinite_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_isfinite_op)\n  typedef bool result_type;\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE result_type operator() (const Scalar& a) const { return (numext::isfinite)(a); }\n};\ntemplate<typename Scalar>\nstruct functor_traits<scalar_isfinite_op<Scalar> >\n{\n  enum {\n    Cost = NumTraits<Scalar>::MulCost,\n    PacketAccess = false\n  };\n};\n\n/** \\internal\n  * \\brief Template functor to compute the logical not of a boolean\n  *\n  * \\sa class CwiseUnaryOp, ArrayBase::operator!\n  */\ntemplate<typename Scalar> struct scalar_boolean_not_op {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_boolean_not_op)\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE bool operator() (const bool& a) const { return !a; }\n};\ntemplate<typename Scalar>\nstruct functor_traits<scalar_boolean_not_op<Scalar> > {\n  enum {\n    Cost = NumTraits<bool>::AddCost,\n    PacketAccess = false\n  };\n};\n\n/** \\internal\n  * \\brief Template functor to compute the signum of a scalar\n  * \\sa class CwiseUnaryOp, Cwise::sign()\n  */\ntemplate<typename Scalar,bool iscpx=(NumTraits<Scalar>::IsComplex!=0) > struct scalar_sign_op;\ntemplate<typename Scalar>\nstruct scalar_sign_op<Scalar,false> {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_sign_op)\n  EIGEN_DEVICE_FUNC inline const Scalar operator() (const Scalar& a) const\n  {\n      return Scalar( (a>Scalar(0)) - (a<Scalar(0)) );\n  }\n  //TODO\n  //template <typename Packet>\n  //EIGEN_DEVICE_FUNC inline Packet packetOp(const Packet& a) const { return internal::psign(a); }\n};\ntemplate<typename Scalar>\nstruct scalar_sign_op<Scalar,true> {\n  EIGEN_EMPTY_STRUCT_CTOR(scalar_sign_op)\n  EIGEN_DEVICE_FUNC inline const Scalar operator() (const Scalar& a) const\n  {\n    typedef typename NumTraits<Scalar>::Real real_type;\n    real_type aa = numext::abs(a);\n    if (aa==real_type(0))\n      return Scalar(0);\n    aa = real_type(1)/aa;\n    return Scalar(real(a)*aa, imag(a)*aa );\n  }\n  //TODO\n  //template <typename Packet>\n  //EIGEN_DEVICE_FUNC inline Packet packetOp(const Packet& a) const { return internal::psign(a); }\n};\ntemplate<typename Scalar>\nstruct functor_traits<scalar_sign_op<Scalar> >\n{ enum {\n    Cost = \n        NumTraits<Scalar>::IsComplex\n        ? ( 8*NumTraits<Scalar>::MulCost  ) // roughly\n        : ( 3*NumTraits<Scalar>::AddCost),\n    PacketAccess = packet_traits<Scalar>::HasSign\n  };\n};\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_FUNCTORS_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/products/GeneralBlockPanelKernel.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_GENERAL_BLOCK_PANEL_H\n#define EIGEN_GENERAL_BLOCK_PANEL_H\n\n\nnamespace Eigen {\n\nnamespace internal {\n\ntemplate<typename _LhsScalar, typename _RhsScalar, bool _ConjLhs=false, bool _ConjRhs=false>\nclass gebp_traits;\n\n\n/** \\internal \\returns b if a<=0, and returns a otherwise. */\ninline std::ptrdiff_t manage_caching_sizes_helper(std::ptrdiff_t a, std::ptrdiff_t b)\n{\n  return a<=0 ? b : a;\n}\n\n#if EIGEN_ARCH_i386_OR_x86_64\nconst std::ptrdiff_t defaultL1CacheSize = 32*1024;\nconst std::ptrdiff_t defaultL2CacheSize = 256*1024;\nconst std::ptrdiff_t defaultL3CacheSize = 2*1024*1024;\n#else\nconst std::ptrdiff_t defaultL1CacheSize = 16*1024;\nconst std::ptrdiff_t defaultL2CacheSize = 512*1024;\nconst std::ptrdiff_t defaultL3CacheSize = 512*1024;\n#endif\n\n/** \\internal */\nstruct CacheSizes {\n  CacheSizes(): m_l1(-1),m_l2(-1),m_l3(-1) {\n    int l1CacheSize, l2CacheSize, l3CacheSize;\n    queryCacheSizes(l1CacheSize, l2CacheSize, l3CacheSize);\n    m_l1 = manage_caching_sizes_helper(l1CacheSize, defaultL1CacheSize);\n    m_l2 = manage_caching_sizes_helper(l2CacheSize, defaultL2CacheSize);\n    m_l3 = manage_caching_sizes_helper(l3CacheSize, defaultL3CacheSize);\n  }\n\n  std::ptrdiff_t m_l1;\n  std::ptrdiff_t m_l2;\n  std::ptrdiff_t m_l3;\n};\n\n\n/** \\internal */\ninline void manage_caching_sizes(Action action, std::ptrdiff_t* l1, std::ptrdiff_t* l2, std::ptrdiff_t* l3)\n{\n  static CacheSizes m_cacheSizes;\n\n  if(action==SetAction)\n  {\n    // set the cpu cache size and cache all block sizes from a global cache size in byte\n    eigen_internal_assert(l1!=0 && l2!=0);\n    m_cacheSizes.m_l1 = *l1;\n    m_cacheSizes.m_l2 = *l2;\n    m_cacheSizes.m_l3 = *l3;\n  }\n  else if(action==GetAction)\n  {\n    eigen_internal_assert(l1!=0 && l2!=0);\n    *l1 = m_cacheSizes.m_l1;\n    *l2 = m_cacheSizes.m_l2;\n    *l3 = m_cacheSizes.m_l3;\n  }\n  else\n  {\n    eigen_internal_assert(false);\n  }\n}\n\n/* Helper for computeProductBlockingSizes.\n *\n * Given a m x k times k x n matrix product of scalar types \\c LhsScalar and \\c RhsScalar,\n * this function computes the blocking size parameters along the respective dimensions\n * for matrix products and related algorithms. The blocking sizes depends on various\n * parameters:\n * - the L1 and L2 cache sizes,\n * - the register level blocking sizes defined by gebp_traits,\n * - the number of scalars that fit into a packet (when vectorization is enabled).\n *\n * \\sa setCpuCacheSizes */\n\ntemplate<typename LhsScalar, typename RhsScalar, int KcFactor, typename Index>\nvoid evaluateProductBlockingSizesHeuristic(Index& k, Index& m, Index& n, Index num_threads = 1)\n{\n  typedef gebp_traits<LhsScalar,RhsScalar> Traits;\n\n  // Explanations:\n  // Let's recall that the product algorithms form mc x kc vertical panels A' on the lhs and\n  // kc x nc blocks B' on the rhs. B' has to fit into L2/L3 cache. Moreover, A' is processed\n  // per mr x kc horizontal small panels where mr is the blocking size along the m dimension\n  // at the register level. This small horizontal panel has to stay within L1 cache.\n  std::ptrdiff_t l1, l2, l3;\n  manage_caching_sizes(GetAction, &l1, &l2, &l3);\n\n  if (num_threads > 1) {\n    typedef typename Traits::ResScalar ResScalar;\n    enum {\n      kdiv = KcFactor * (Traits::mr * sizeof(LhsScalar) + Traits::nr * sizeof(RhsScalar)),\n      ksub = Traits::mr * Traits::nr * sizeof(ResScalar),\n      kr = 8,\n      mr = Traits::mr,\n      nr = Traits::nr\n    };\n    // Increasing k gives us more time to prefetch the content of the \"C\"\n    // registers. However once the latency is hidden there is no point in\n    // increasing the value of k, so we'll cap it at 320 (value determined\n    // experimentally).\n    const Index k_cache = (numext::mini<Index>)((l1-ksub)/kdiv, 320);\n    if (k_cache < k) {\n      k = k_cache - (k_cache % kr);\n      eigen_internal_assert(k > 0);\n    }\n\n    const Index n_cache = (l2-l1) / (nr * sizeof(RhsScalar) * k);\n    const Index n_per_thread = numext::div_ceil(n, num_threads);\n    if (n_cache <= n_per_thread) {\n      // Don't exceed the capacity of the l2 cache.\n      eigen_internal_assert(n_cache >= static_cast<Index>(nr));\n      n = n_cache - (n_cache % nr);\n      eigen_internal_assert(n > 0);\n    } else {\n      n = (numext::mini<Index>)(n, (n_per_thread + nr - 1) - ((n_per_thread + nr - 1) % nr));\n    }\n\n    if (l3 > l2) {\n      // l3 is shared between all cores, so we'll give each thread its own chunk of l3.\n      const Index m_cache = (l3-l2) / (sizeof(LhsScalar) * k * num_threads);\n      const Index m_per_thread = numext::div_ceil(m, num_threads);\n      if(m_cache < m_per_thread && m_cache >= static_cast<Index>(mr)) {\n        m = m_cache - (m_cache % mr);\n        eigen_internal_assert(m > 0);\n      } else {\n        m = (numext::mini<Index>)(m, (m_per_thread + mr - 1) - ((m_per_thread + mr - 1) % mr));\n      }\n    }\n  }\n  else {\n    // In unit tests we do not want to use extra large matrices,\n    // so we reduce the cache size to check the blocking strategy is not flawed\n#ifdef EIGEN_DEBUG_SMALL_PRODUCT_BLOCKS\n    l1 = 9*1024;\n    l2 = 32*1024;\n    l3 = 512*1024;\n#endif\n\n    // Early return for small problems because the computation below are time consuming for small problems.\n    // Perhaps it would make more sense to consider k*n*m??\n    // Note that for very tiny problem, this function should be bypassed anyway\n    // because we use the coefficient-based implementation for them.\n    if((numext::maxi)(k,(numext::maxi)(m,n))<48)\n      return;\n\n    typedef typename Traits::ResScalar ResScalar;\n    enum {\n      k_peeling = 8,\n      k_div = KcFactor * (Traits::mr * sizeof(LhsScalar) + Traits::nr * sizeof(RhsScalar)),\n      k_sub = Traits::mr * Traits::nr * sizeof(ResScalar)\n    };\n\n    // ---- 1st level of blocking on L1, yields kc ----\n\n    // Blocking on the third dimension (i.e., k) is chosen so that an horizontal panel\n    // of size mr x kc of the lhs plus a vertical panel of kc x nr of the rhs both fits within L1 cache.\n    // We also include a register-level block of the result (mx x nr).\n    // (In an ideal world only the lhs panel would stay in L1)\n    // Moreover, kc has to be a multiple of 8 to be compatible with loop peeling, leading to a maximum blocking size of:\n    const Index max_kc = numext::maxi<Index>(((l1-k_sub)/k_div) & (~(k_peeling-1)),1);\n    const Index old_k = k;\n    if(k>max_kc)\n    {\n      // We are really blocking on the third dimension:\n      // -> reduce blocking size to make sure the last block is as large as possible\n      //    while keeping the same number of sweeps over the result.\n      k = (k%max_kc)==0 ? max_kc\n                        : max_kc - k_peeling * ((max_kc-1-(k%max_kc))/(k_peeling*(k/max_kc+1)));\n\n      eigen_internal_assert(((old_k/k) == (old_k/max_kc)) && \"the number of sweeps has to remain the same\");\n    }\n\n    // ---- 2nd level of blocking on max(L2,L3), yields nc ----\n\n    // TODO find a reliable way to get the actual amount of cache per core to use for 2nd level blocking, that is:\n    //      actual_l2 = max(l2, l3/nb_core_sharing_l3)\n    // The number below is quite conservative: it is better to underestimate the cache size rather than overestimating it)\n    // For instance, it corresponds to 6MB of L3 shared among 4 cores.\n    #ifdef EIGEN_DEBUG_SMALL_PRODUCT_BLOCKS\n    const Index actual_l2 = l3;\n    #else\n    const Index actual_l2 = 1572864; // == 1.5 MB\n    #endif\n\n    // Here, nc is chosen such that a block of kc x nc of the rhs fit within half of L2.\n    // The second half is implicitly reserved to access the result and lhs coefficients.\n    // When k<max_kc, then nc can arbitrarily growth. In practice, it seems to be fruitful\n    // to limit this growth: we bound nc to growth by a factor x1.5.\n    // However, if the entire lhs block fit within L1, then we are not going to block on the rows at all,\n    // and it becomes fruitful to keep the packed rhs blocks in L1 if there is enough remaining space.\n    Index max_nc;\n    const Index lhs_bytes = m * k * sizeof(LhsScalar);\n    const Index remaining_l1 = l1- k_sub - lhs_bytes;\n    if(remaining_l1 >= Index(Traits::nr*sizeof(RhsScalar))*k)\n    {\n      // L1 blocking\n      max_nc = remaining_l1 / (k*sizeof(RhsScalar));\n    }\n    else\n    {\n      // L2 blocking\n      max_nc = (3*actual_l2)/(2*2*max_kc*sizeof(RhsScalar));\n    }\n    // WARNING Below, we assume that Traits::nr is a power of two.\n    Index nc = numext::mini<Index>(actual_l2/(2*k*sizeof(RhsScalar)), max_nc) & (~(Traits::nr-1));\n    if(n>nc)\n    {\n      // We are really blocking over the columns:\n      // -> reduce blocking size to make sure the last block is as large as possible\n      //    while keeping the same number of sweeps over the packed lhs.\n      //    Here we allow one more sweep if this gives us a perfect match, thus the commented \"-1\"\n      n = (n%nc)==0 ? nc\n                    : (nc - Traits::nr * ((nc/*-1*/-(n%nc))/(Traits::nr*(n/nc+1))));\n    }\n    else if(old_k==k)\n    {\n      // So far, no blocking at all, i.e., kc==k, and nc==n.\n      // In this case, let's perform a blocking over the rows such that the packed lhs data is kept in cache L1/L2\n      // TODO: part of this blocking strategy is now implemented within the kernel itself, so the L1-based heuristic here should be obsolete.\n      Index problem_size = k*n*sizeof(LhsScalar);\n      Index actual_lm = actual_l2;\n      Index max_mc = m;\n      if(problem_size<=1024)\n      {\n        // problem is small enough to keep in L1\n        // Let's choose m such that lhs's block fit in 1/3 of L1\n        actual_lm = l1;\n      }\n      else if(l3!=0 && problem_size<=32768)\n      {\n        // we have both L2 and L3, and problem is small enough to be kept in L2\n        // Let's choose m such that lhs's block fit in 1/3 of L2\n        actual_lm = l2;\n        max_mc = (numext::mini<Index>)(576,max_mc);\n      }\n      Index mc = (numext::mini<Index>)(actual_lm/(3*k*sizeof(LhsScalar)), max_mc);\n      if (mc > Traits::mr) mc -= mc % Traits::mr;\n      else if (mc==0) return;\n      m = (m%mc)==0 ? mc\n                    : (mc - Traits::mr * ((mc/*-1*/-(m%mc))/(Traits::mr*(m/mc+1))));\n    }\n  }\n}\n\ntemplate <typename Index>\ninline bool useSpecificBlockingSizes(Index& k, Index& m, Index& n)\n{\n#ifdef EIGEN_TEST_SPECIFIC_BLOCKING_SIZES\n  if (EIGEN_TEST_SPECIFIC_BLOCKING_SIZES) {\n    k = numext::mini<Index>(k, EIGEN_TEST_SPECIFIC_BLOCKING_SIZE_K);\n    m = numext::mini<Index>(m, EIGEN_TEST_SPECIFIC_BLOCKING_SIZE_M);\n    n = numext::mini<Index>(n, EIGEN_TEST_SPECIFIC_BLOCKING_SIZE_N);\n    return true;\n  }\n#else\n  EIGEN_UNUSED_VARIABLE(k)\n  EIGEN_UNUSED_VARIABLE(m)\n  EIGEN_UNUSED_VARIABLE(n)\n#endif\n  return false;\n}\n\n/** \\brief Computes the blocking parameters for a m x k times k x n matrix product\n  *\n  * \\param[in,out] k Input: the third dimension of the product. Output: the blocking size along the same dimension.\n  * \\param[in,out] m Input: the number of rows of the left hand side. Output: the blocking size along the same dimension.\n  * \\param[in,out] n Input: the number of columns of the right hand side. Output: the blocking size along the same dimension.\n  *\n  * Given a m x k times k x n matrix product of scalar types \\c LhsScalar and \\c RhsScalar,\n  * this function computes the blocking size parameters along the respective dimensions\n  * for matrix products and related algorithms.\n  *\n  * The blocking size parameters may be evaluated:\n  *   - either by a heuristic based on cache sizes;\n  *   - or using fixed prescribed values (for testing purposes).\n  *\n  * \\sa setCpuCacheSizes */\n\ntemplate<typename LhsScalar, typename RhsScalar, int KcFactor, typename Index>\nvoid computeProductBlockingSizes(Index& k, Index& m, Index& n, Index num_threads = 1)\n{\n  if (!useSpecificBlockingSizes(k, m, n)) {\n    evaluateProductBlockingSizesHeuristic<LhsScalar, RhsScalar, KcFactor, Index>(k, m, n, num_threads);\n  }\n}\n\ntemplate<typename LhsScalar, typename RhsScalar, typename Index>\ninline void computeProductBlockingSizes(Index& k, Index& m, Index& n, Index num_threads = 1)\n{\n  computeProductBlockingSizes<LhsScalar,RhsScalar,1,Index>(k, m, n, num_threads);\n}\n\n#ifdef EIGEN_HAS_SINGLE_INSTRUCTION_CJMADD\n  #define CJMADD(CJ,A,B,C,T)  C = CJ.pmadd(A,B,C);\n#else\n\n  // FIXME (a bit overkill maybe ?)\n\n  template<typename CJ, typename A, typename B, typename C, typename T> struct gebp_madd_selector {\n    EIGEN_ALWAYS_INLINE static void run(const CJ& cj, A& a, B& b, C& c, T& /*t*/)\n    {\n      c = cj.pmadd(a,b,c);\n    }\n  };\n\n  template<typename CJ, typename T> struct gebp_madd_selector<CJ,T,T,T,T> {\n    EIGEN_ALWAYS_INLINE static void run(const CJ& cj, T& a, T& b, T& c, T& t)\n    {\n      t = b; t = cj.pmul(a,t); c = padd(c,t);\n    }\n  };\n\n  template<typename CJ, typename A, typename B, typename C, typename T>\n  EIGEN_STRONG_INLINE void gebp_madd(const CJ& cj, A& a, B& b, C& c, T& t)\n  {\n    gebp_madd_selector<CJ,A,B,C,T>::run(cj,a,b,c,t);\n  }\n\n  #define CJMADD(CJ,A,B,C,T)  gebp_madd(CJ,A,B,C,T);\n//   #define CJMADD(CJ,A,B,C,T)  T = B; T = CJ.pmul(A,T); C = padd(C,T);\n#endif\n\n/* Vectorization logic\n *  real*real: unpack rhs to constant packets, ...\n * \n *  cd*cd : unpack rhs to (b_r,b_r), (b_i,b_i), mul to get (a_r b_r,a_i b_r) (a_r b_i,a_i b_i),\n *          storing each res packet into two packets (2x2),\n *          at the end combine them: swap the second and addsub them \n *  cf*cf : same but with 2x4 blocks\n *  cplx*real : unpack rhs to constant packets, ...\n *  real*cplx : load lhs as (a0,a0,a1,a1), and mul as usual\n */\ntemplate<typename _LhsScalar, typename _RhsScalar, bool _ConjLhs, bool _ConjRhs>\nclass gebp_traits\n{\npublic:\n  typedef _LhsScalar LhsScalar;\n  typedef _RhsScalar RhsScalar;\n  typedef typename ScalarBinaryOpTraits<LhsScalar, RhsScalar>::ReturnType ResScalar;\n\n  enum {\n    ConjLhs = _ConjLhs,\n    ConjRhs = _ConjRhs,\n    Vectorizable = packet_traits<LhsScalar>::Vectorizable && packet_traits<RhsScalar>::Vectorizable,\n    LhsPacketSize = Vectorizable ? packet_traits<LhsScalar>::size : 1,\n    RhsPacketSize = Vectorizable ? packet_traits<RhsScalar>::size : 1,\n    ResPacketSize = Vectorizable ? packet_traits<ResScalar>::size : 1,\n    \n    NumberOfRegisters = EIGEN_ARCH_DEFAULT_NUMBER_OF_REGISTERS,\n\n    // register block size along the N direction must be 1 or 4\n    nr = 4,\n\n    // register block size along the M direction (currently, this one cannot be modified)\n    default_mr = (EIGEN_PLAIN_ENUM_MIN(16,NumberOfRegisters)/2/nr)*LhsPacketSize,\n#if defined(EIGEN_HAS_SINGLE_INSTRUCTION_MADD) && !defined(EIGEN_VECTORIZE_ALTIVEC) && !defined(EIGEN_VECTORIZE_VSX)\n    // we assume 16 registers\n    // See bug 992, if the scalar type is not vectorizable but that EIGEN_HAS_SINGLE_INSTRUCTION_MADD is defined,\n    // then using 3*LhsPacketSize triggers non-implemented paths in syrk.\n    mr = Vectorizable ? 3*LhsPacketSize : default_mr,\n#else\n    mr = default_mr,\n#endif\n    \n    LhsProgress = LhsPacketSize,\n    RhsProgress = 1\n  };\n\n  typedef typename packet_traits<LhsScalar>::type  _LhsPacket;\n  typedef typename packet_traits<RhsScalar>::type  _RhsPacket;\n  typedef typename packet_traits<ResScalar>::type  _ResPacket;\n\n  typedef typename conditional<Vectorizable,_LhsPacket,LhsScalar>::type LhsPacket;\n  typedef typename conditional<Vectorizable,_RhsPacket,RhsScalar>::type RhsPacket;\n  typedef typename conditional<Vectorizable,_ResPacket,ResScalar>::type ResPacket;\n\n  typedef ResPacket AccPacket;\n  \n  EIGEN_STRONG_INLINE void initAcc(AccPacket& p)\n  {\n    p = pset1<ResPacket>(ResScalar(0));\n  }\n  \n  EIGEN_STRONG_INLINE void broadcastRhs(const RhsScalar* b, RhsPacket& b0, RhsPacket& b1, RhsPacket& b2, RhsPacket& b3)\n  {\n    pbroadcast4(b, b0, b1, b2, b3);\n  }\n  \n//   EIGEN_STRONG_INLINE void broadcastRhs(const RhsScalar* b, RhsPacket& b0, RhsPacket& b1)\n//   {\n//     pbroadcast2(b, b0, b1);\n//   }\n  \n  template<typename RhsPacketType>\n  EIGEN_STRONG_INLINE void loadRhs(const RhsScalar* b, RhsPacketType& dest) const\n  {\n    dest = pset1<RhsPacketType>(*b);\n  }\n  \n  EIGEN_STRONG_INLINE void loadRhsQuad(const RhsScalar* b, RhsPacket& dest) const\n  {\n    dest = ploadquad<RhsPacket>(b);\n  }\n\n  template<typename LhsPacketType>\n  EIGEN_STRONG_INLINE void loadLhs(const LhsScalar* a, LhsPacketType& dest) const\n  {\n    dest = pload<LhsPacketType>(a);\n  }\n\n  template<typename LhsPacketType>\n  EIGEN_STRONG_INLINE void loadLhsUnaligned(const LhsScalar* a, LhsPacketType& dest) const\n  {\n    dest = ploadu<LhsPacketType>(a);\n  }\n\n  template<typename LhsPacketType, typename RhsPacketType, typename AccPacketType>\n  EIGEN_STRONG_INLINE void madd(const LhsPacketType& a, const RhsPacketType& b, AccPacketType& c, AccPacketType& tmp) const\n  {\n    conj_helper<LhsPacketType,RhsPacketType,ConjLhs,ConjRhs> cj;\n    // It would be a lot cleaner to call pmadd all the time. Unfortunately if we\n    // let gcc allocate the register in which to store the result of the pmul\n    // (in the case where there is no FMA) gcc fails to figure out how to avoid\n    // spilling register.\n#ifdef EIGEN_HAS_SINGLE_INSTRUCTION_MADD\n    EIGEN_UNUSED_VARIABLE(tmp);\n    c = cj.pmadd(a,b,c);\n#else\n    tmp = b; tmp = cj.pmul(a,tmp); c = padd(c,tmp);\n#endif\n  }\n\n  EIGEN_STRONG_INLINE void acc(const AccPacket& c, const ResPacket& alpha, ResPacket& r) const\n  {\n    r = pmadd(c,alpha,r);\n  }\n  \n  template<typename ResPacketHalf>\n  EIGEN_STRONG_INLINE void acc(const ResPacketHalf& c, const ResPacketHalf& alpha, ResPacketHalf& r) const\n  {\n    r = pmadd(c,alpha,r);\n  }\n\n};\n\ntemplate<typename RealScalar, bool _ConjLhs>\nclass gebp_traits<std::complex<RealScalar>, RealScalar, _ConjLhs, false>\n{\npublic:\n  typedef std::complex<RealScalar> LhsScalar;\n  typedef RealScalar RhsScalar;\n  typedef typename ScalarBinaryOpTraits<LhsScalar, RhsScalar>::ReturnType ResScalar;\n\n  enum {\n    ConjLhs = _ConjLhs,\n    ConjRhs = false,\n    Vectorizable = packet_traits<LhsScalar>::Vectorizable && packet_traits<RhsScalar>::Vectorizable,\n    LhsPacketSize = Vectorizable ? packet_traits<LhsScalar>::size : 1,\n    RhsPacketSize = Vectorizable ? packet_traits<RhsScalar>::size : 1,\n    ResPacketSize = Vectorizable ? packet_traits<ResScalar>::size : 1,\n    \n    NumberOfRegisters = EIGEN_ARCH_DEFAULT_NUMBER_OF_REGISTERS,\n    nr = 4,\n#if defined(EIGEN_HAS_SINGLE_INSTRUCTION_MADD) && !defined(EIGEN_VECTORIZE_ALTIVEC) && !defined(EIGEN_VECTORIZE_VSX)\n    // we assume 16 registers\n    mr = 3*LhsPacketSize,\n#else\n    mr = (EIGEN_PLAIN_ENUM_MIN(16,NumberOfRegisters)/2/nr)*LhsPacketSize,\n#endif\n\n    LhsProgress = LhsPacketSize,\n    RhsProgress = 1\n  };\n\n  typedef typename packet_traits<LhsScalar>::type  _LhsPacket;\n  typedef typename packet_traits<RhsScalar>::type  _RhsPacket;\n  typedef typename packet_traits<ResScalar>::type  _ResPacket;\n\n  typedef typename conditional<Vectorizable,_LhsPacket,LhsScalar>::type LhsPacket;\n  typedef typename conditional<Vectorizable,_RhsPacket,RhsScalar>::type RhsPacket;\n  typedef typename conditional<Vectorizable,_ResPacket,ResScalar>::type ResPacket;\n\n  typedef ResPacket AccPacket;\n\n  EIGEN_STRONG_INLINE void initAcc(AccPacket& p)\n  {\n    p = pset1<ResPacket>(ResScalar(0));\n  }\n\n  EIGEN_STRONG_INLINE void loadRhs(const RhsScalar* b, RhsPacket& dest) const\n  {\n    dest = pset1<RhsPacket>(*b);\n  }\n  \n  EIGEN_STRONG_INLINE void loadRhsQuad(const RhsScalar* b, RhsPacket& dest) const\n  {\n    dest = pset1<RhsPacket>(*b);\n  }\n\n  EIGEN_STRONG_INLINE void loadLhs(const LhsScalar* a, LhsPacket& dest) const\n  {\n    dest = pload<LhsPacket>(a);\n  }\n\n  EIGEN_STRONG_INLINE void loadLhsUnaligned(const LhsScalar* a, LhsPacket& dest) const\n  {\n    dest = ploadu<LhsPacket>(a);\n  }\n\n  EIGEN_STRONG_INLINE void broadcastRhs(const RhsScalar* b, RhsPacket& b0, RhsPacket& b1, RhsPacket& b2, RhsPacket& b3)\n  {\n    pbroadcast4(b, b0, b1, b2, b3);\n  }\n  \n//   EIGEN_STRONG_INLINE void broadcastRhs(const RhsScalar* b, RhsPacket& b0, RhsPacket& b1)\n//   {\n//     pbroadcast2(b, b0, b1);\n//   }\n\n  EIGEN_STRONG_INLINE void madd(const LhsPacket& a, const RhsPacket& b, AccPacket& c, RhsPacket& tmp) const\n  {\n    madd_impl(a, b, c, tmp, typename conditional<Vectorizable,true_type,false_type>::type());\n  }\n\n  EIGEN_STRONG_INLINE void madd_impl(const LhsPacket& a, const RhsPacket& b, AccPacket& c, RhsPacket& tmp, const true_type&) const\n  {\n#ifdef EIGEN_HAS_SINGLE_INSTRUCTION_MADD\n    EIGEN_UNUSED_VARIABLE(tmp);\n    c.v = pmadd(a.v,b,c.v);\n#else\n    tmp = b; tmp = pmul(a.v,tmp); c.v = padd(c.v,tmp);\n#endif\n  }\n\n  EIGEN_STRONG_INLINE void madd_impl(const LhsScalar& a, const RhsScalar& b, ResScalar& c, RhsScalar& /*tmp*/, const false_type&) const\n  {\n    c += a * b;\n  }\n\n  EIGEN_STRONG_INLINE void acc(const AccPacket& c, const ResPacket& alpha, ResPacket& r) const\n  {\n    r = cj.pmadd(c,alpha,r);\n  }\n\nprotected:\n  conj_helper<ResPacket,ResPacket,ConjLhs,false> cj;\n};\n\ntemplate<typename Packet>\nstruct DoublePacket\n{\n  Packet first;\n  Packet second;\n};\n\ntemplate<typename Packet>\nDoublePacket<Packet> padd(const DoublePacket<Packet> &a, const DoublePacket<Packet> &b)\n{\n  DoublePacket<Packet> res;\n  res.first  = padd(a.first, b.first);\n  res.second = padd(a.second,b.second);\n  return res;\n}\n\ntemplate<typename Packet>\nconst DoublePacket<Packet>& predux_downto4(const DoublePacket<Packet> &a)\n{\n  return a;\n}\n\ntemplate<typename Packet> struct unpacket_traits<DoublePacket<Packet> > { typedef DoublePacket<Packet> half; };\n// template<typename Packet>\n// DoublePacket<Packet> pmadd(const DoublePacket<Packet> &a, const DoublePacket<Packet> &b)\n// {\n//   DoublePacket<Packet> res;\n//   res.first  = padd(a.first, b.first);\n//   res.second = padd(a.second,b.second);\n//   return res;\n// }\n\ntemplate<typename RealScalar, bool _ConjLhs, bool _ConjRhs>\nclass gebp_traits<std::complex<RealScalar>, std::complex<RealScalar>, _ConjLhs, _ConjRhs >\n{\npublic:\n  typedef std::complex<RealScalar>  Scalar;\n  typedef std::complex<RealScalar>  LhsScalar;\n  typedef std::complex<RealScalar>  RhsScalar;\n  typedef std::complex<RealScalar>  ResScalar;\n  \n  enum {\n    ConjLhs = _ConjLhs,\n    ConjRhs = _ConjRhs,\n    Vectorizable = packet_traits<RealScalar>::Vectorizable\n                && packet_traits<Scalar>::Vectorizable,\n    RealPacketSize  = Vectorizable ? packet_traits<RealScalar>::size : 1,\n    ResPacketSize   = Vectorizable ? packet_traits<ResScalar>::size : 1,\n    LhsPacketSize = Vectorizable ? packet_traits<LhsScalar>::size : 1,\n    RhsPacketSize = Vectorizable ? packet_traits<RhsScalar>::size : 1,\n\n    // FIXME: should depend on NumberOfRegisters\n    nr = 4,\n    mr = ResPacketSize,\n\n    LhsProgress = ResPacketSize,\n    RhsProgress = 1\n  };\n  \n  typedef typename packet_traits<RealScalar>::type RealPacket;\n  typedef typename packet_traits<Scalar>::type     ScalarPacket;\n  typedef DoublePacket<RealPacket> DoublePacketType;\n\n  typedef typename conditional<Vectorizable,RealPacket,  Scalar>::type LhsPacket;\n  typedef typename conditional<Vectorizable,DoublePacketType,Scalar>::type RhsPacket;\n  typedef typename conditional<Vectorizable,ScalarPacket,Scalar>::type ResPacket;\n  typedef typename conditional<Vectorizable,DoublePacketType,Scalar>::type AccPacket;\n  \n  EIGEN_STRONG_INLINE void initAcc(Scalar& p) { p = Scalar(0); }\n\n  EIGEN_STRONG_INLINE void initAcc(DoublePacketType& p)\n  {\n    p.first   = pset1<RealPacket>(RealScalar(0));\n    p.second  = pset1<RealPacket>(RealScalar(0));\n  }\n\n  // Scalar path\n  EIGEN_STRONG_INLINE void loadRhs(const RhsScalar* b, ResPacket& dest) const\n  {\n    dest = pset1<ResPacket>(*b);\n  }\n\n  // Vectorized path\n  EIGEN_STRONG_INLINE void loadRhs(const RhsScalar* b, DoublePacketType& dest) const\n  {\n    dest.first  = pset1<RealPacket>(real(*b));\n    dest.second = pset1<RealPacket>(imag(*b));\n  }\n  \n  EIGEN_STRONG_INLINE void loadRhsQuad(const RhsScalar* b, ResPacket& dest) const\n  {\n    loadRhs(b,dest);\n  }\n  EIGEN_STRONG_INLINE void loadRhsQuad(const RhsScalar* b, DoublePacketType& dest) const\n  {\n    eigen_internal_assert(unpacket_traits<ScalarPacket>::size<=4);\n    loadRhs(b,dest);\n  }\n  \n  EIGEN_STRONG_INLINE void broadcastRhs(const RhsScalar* b, RhsPacket& b0, RhsPacket& b1, RhsPacket& b2, RhsPacket& b3)\n  {\n    // FIXME not sure that's the best way to implement it!\n    loadRhs(b+0, b0);\n    loadRhs(b+1, b1);\n    loadRhs(b+2, b2);\n    loadRhs(b+3, b3);\n  }\n  \n  // Vectorized path\n  EIGEN_STRONG_INLINE void broadcastRhs(const RhsScalar* b, DoublePacketType& b0, DoublePacketType& b1)\n  {\n    // FIXME not sure that's the best way to implement it!\n    loadRhs(b+0, b0);\n    loadRhs(b+1, b1);\n  }\n  \n  // Scalar path\n  EIGEN_STRONG_INLINE void broadcastRhs(const RhsScalar* b, RhsScalar& b0, RhsScalar& b1)\n  {\n    // FIXME not sure that's the best way to implement it!\n    loadRhs(b+0, b0);\n    loadRhs(b+1, b1);\n  }\n\n  // nothing special here\n  EIGEN_STRONG_INLINE void loadLhs(const LhsScalar* a, LhsPacket& dest) const\n  {\n    dest = pload<LhsPacket>((const typename unpacket_traits<LhsPacket>::type*)(a));\n  }\n\n  EIGEN_STRONG_INLINE void loadLhsUnaligned(const LhsScalar* a, LhsPacket& dest) const\n  {\n    dest = ploadu<LhsPacket>((const typename unpacket_traits<LhsPacket>::type*)(a));\n  }\n\n  EIGEN_STRONG_INLINE void madd(const LhsPacket& a, const RhsPacket& b, DoublePacketType& c, RhsPacket& /*tmp*/) const\n  {\n    c.first   = padd(pmul(a,b.first), c.first);\n    c.second  = padd(pmul(a,b.second),c.second);\n  }\n\n  EIGEN_STRONG_INLINE void madd(const LhsPacket& a, const RhsPacket& b, ResPacket& c, RhsPacket& /*tmp*/) const\n  {\n    c = cj.pmadd(a,b,c);\n  }\n  \n  EIGEN_STRONG_INLINE void acc(const Scalar& c, const Scalar& alpha, Scalar& r) const { r += alpha * c; }\n  \n  EIGEN_STRONG_INLINE void acc(const DoublePacketType& c, const ResPacket& alpha, ResPacket& r) const\n  {\n    // assemble c\n    ResPacket tmp;\n    if((!ConjLhs)&&(!ConjRhs))\n    {\n      tmp = pcplxflip(pconj(ResPacket(c.second)));\n      tmp = padd(ResPacket(c.first),tmp);\n    }\n    else if((!ConjLhs)&&(ConjRhs))\n    {\n      tmp = pconj(pcplxflip(ResPacket(c.second)));\n      tmp = padd(ResPacket(c.first),tmp);\n    }\n    else if((ConjLhs)&&(!ConjRhs))\n    {\n      tmp = pcplxflip(ResPacket(c.second));\n      tmp = padd(pconj(ResPacket(c.first)),tmp);\n    }\n    else if((ConjLhs)&&(ConjRhs))\n    {\n      tmp = pcplxflip(ResPacket(c.second));\n      tmp = psub(pconj(ResPacket(c.first)),tmp);\n    }\n    \n    r = pmadd(tmp,alpha,r);\n  }\n\nprotected:\n  conj_helper<LhsScalar,RhsScalar,ConjLhs,ConjRhs> cj;\n};\n\ntemplate<typename RealScalar, bool _ConjRhs>\nclass gebp_traits<RealScalar, std::complex<RealScalar>, false, _ConjRhs >\n{\npublic:\n  typedef std::complex<RealScalar>  Scalar;\n  typedef RealScalar  LhsScalar;\n  typedef Scalar      RhsScalar;\n  typedef Scalar      ResScalar;\n\n  enum {\n    ConjLhs = false,\n    ConjRhs = _ConjRhs,\n    Vectorizable = packet_traits<RealScalar>::Vectorizable\n                && packet_traits<Scalar>::Vectorizable,\n    LhsPacketSize = Vectorizable ? packet_traits<LhsScalar>::size : 1,\n    RhsPacketSize = Vectorizable ? packet_traits<RhsScalar>::size : 1,\n    ResPacketSize = Vectorizable ? packet_traits<ResScalar>::size : 1,\n    \n    NumberOfRegisters = EIGEN_ARCH_DEFAULT_NUMBER_OF_REGISTERS,\n    // FIXME: should depend on NumberOfRegisters\n    nr = 4,\n    mr = (EIGEN_PLAIN_ENUM_MIN(16,NumberOfRegisters)/2/nr)*ResPacketSize,\n\n    LhsProgress = ResPacketSize,\n    RhsProgress = 1\n  };\n\n  typedef typename packet_traits<LhsScalar>::type  _LhsPacket;\n  typedef typename packet_traits<RhsScalar>::type  _RhsPacket;\n  typedef typename packet_traits<ResScalar>::type  _ResPacket;\n\n  typedef typename conditional<Vectorizable,_LhsPacket,LhsScalar>::type LhsPacket;\n  typedef typename conditional<Vectorizable,_RhsPacket,RhsScalar>::type RhsPacket;\n  typedef typename conditional<Vectorizable,_ResPacket,ResScalar>::type ResPacket;\n\n  typedef ResPacket AccPacket;\n\n  EIGEN_STRONG_INLINE void initAcc(AccPacket& p)\n  {\n    p = pset1<ResPacket>(ResScalar(0));\n  }\n\n  EIGEN_STRONG_INLINE void loadRhs(const RhsScalar* b, RhsPacket& dest) const\n  {\n    dest = pset1<RhsPacket>(*b);\n  }\n  \n  void broadcastRhs(const RhsScalar* b, RhsPacket& b0, RhsPacket& b1, RhsPacket& b2, RhsPacket& b3)\n  {\n    pbroadcast4(b, b0, b1, b2, b3);\n  }\n  \n//   EIGEN_STRONG_INLINE void broadcastRhs(const RhsScalar* b, RhsPacket& b0, RhsPacket& b1)\n//   {\n//     // FIXME not sure that's the best way to implement it!\n//     b0 = pload1<RhsPacket>(b+0);\n//     b1 = pload1<RhsPacket>(b+1);\n//   }\n\n  EIGEN_STRONG_INLINE void loadLhs(const LhsScalar* a, LhsPacket& dest) const\n  {\n    dest = ploaddup<LhsPacket>(a);\n  }\n  \n  EIGEN_STRONG_INLINE void loadRhsQuad(const RhsScalar* b, RhsPacket& dest) const\n  {\n    eigen_internal_assert(unpacket_traits<RhsPacket>::size<=4);\n    loadRhs(b,dest);\n  }\n\n  EIGEN_STRONG_INLINE void loadLhsUnaligned(const LhsScalar* a, LhsPacket& dest) const\n  {\n    dest = ploaddup<LhsPacket>(a);\n  }\n\n  EIGEN_STRONG_INLINE void madd(const LhsPacket& a, const RhsPacket& b, AccPacket& c, RhsPacket& tmp) const\n  {\n    madd_impl(a, b, c, tmp, typename conditional<Vectorizable,true_type,false_type>::type());\n  }\n\n  EIGEN_STRONG_INLINE void madd_impl(const LhsPacket& a, const RhsPacket& b, AccPacket& c, RhsPacket& tmp, const true_type&) const\n  {\n#ifdef EIGEN_HAS_SINGLE_INSTRUCTION_MADD\n    EIGEN_UNUSED_VARIABLE(tmp);\n    c.v = pmadd(a,b.v,c.v);\n#else\n    tmp = b; tmp.v = pmul(a,tmp.v); c = padd(c,tmp);\n#endif\n    \n  }\n\n  EIGEN_STRONG_INLINE void madd_impl(const LhsScalar& a, const RhsScalar& b, ResScalar& c, RhsScalar& /*tmp*/, const false_type&) const\n  {\n    c += a * b;\n  }\n\n  EIGEN_STRONG_INLINE void acc(const AccPacket& c, const ResPacket& alpha, ResPacket& r) const\n  {\n    r = cj.pmadd(alpha,c,r);\n  }\n\nprotected:\n  conj_helper<ResPacket,ResPacket,false,ConjRhs> cj;\n};\n\n/* optimized GEneral packed Block * packed Panel product kernel\n *\n * Mixing type logic: C += A * B\n *  |  A  |  B  | comments\n *  |real |cplx | no vectorization yet, would require to pack A with duplication\n *  |cplx |real | easy vectorization\n */\ntemplate<typename LhsScalar, typename RhsScalar, typename Index, typename DataMapper, int mr, int nr, bool ConjugateLhs, bool ConjugateRhs>\nstruct gebp_kernel\n{\n  typedef gebp_traits<LhsScalar,RhsScalar,ConjugateLhs,ConjugateRhs> Traits;\n  typedef typename Traits::ResScalar ResScalar;\n  typedef typename Traits::LhsPacket LhsPacket;\n  typedef typename Traits::RhsPacket RhsPacket;\n  typedef typename Traits::ResPacket ResPacket;\n  typedef typename Traits::AccPacket AccPacket;\n\n  typedef gebp_traits<RhsScalar,LhsScalar,ConjugateRhs,ConjugateLhs> SwappedTraits;\n  typedef typename SwappedTraits::ResScalar SResScalar;\n  typedef typename SwappedTraits::LhsPacket SLhsPacket;\n  typedef typename SwappedTraits::RhsPacket SRhsPacket;\n  typedef typename SwappedTraits::ResPacket SResPacket;\n  typedef typename SwappedTraits::AccPacket SAccPacket;\n\n  typedef typename DataMapper::LinearMapper LinearMapper;\n\n  enum {\n    Vectorizable  = Traits::Vectorizable,\n    LhsProgress   = Traits::LhsProgress,\n    RhsProgress   = Traits::RhsProgress,\n    ResPacketSize = Traits::ResPacketSize\n  };\n\n  EIGEN_DONT_INLINE\n  void operator()(const DataMapper& res, const LhsScalar* blockA, const RhsScalar* blockB,\n                  Index rows, Index depth, Index cols, ResScalar alpha,\n                  Index strideA=-1, Index strideB=-1, Index offsetA=0, Index offsetB=0);\n};\n\ntemplate<typename LhsScalar, typename RhsScalar, typename Index, typename DataMapper, int mr, int nr, bool ConjugateLhs, bool ConjugateRhs>\nEIGEN_DONT_INLINE\nvoid gebp_kernel<LhsScalar,RhsScalar,Index,DataMapper,mr,nr,ConjugateLhs,ConjugateRhs>\n  ::operator()(const DataMapper& res, const LhsScalar* blockA, const RhsScalar* blockB,\n               Index rows, Index depth, Index cols, ResScalar alpha,\n               Index strideA, Index strideB, Index offsetA, Index offsetB)\n  {\n    Traits traits;\n    SwappedTraits straits;\n    \n    if(strideA==-1) strideA = depth;\n    if(strideB==-1) strideB = depth;\n    conj_helper<LhsScalar,RhsScalar,ConjugateLhs,ConjugateRhs> cj;\n    Index packet_cols4 = nr>=4 ? (cols/4) * 4 : 0;\n    const Index peeled_mc3 = mr>=3*Traits::LhsProgress ? (rows/(3*LhsProgress))*(3*LhsProgress) : 0;\n    const Index peeled_mc2 = mr>=2*Traits::LhsProgress ? peeled_mc3+((rows-peeled_mc3)/(2*LhsProgress))*(2*LhsProgress) : 0;\n    const Index peeled_mc1 = mr>=1*Traits::LhsProgress ? (rows/(1*LhsProgress))*(1*LhsProgress) : 0;\n    enum { pk = 8 }; // NOTE Such a large peeling factor is important for large matrices (~ +5% when >1000 on Haswell)\n    const Index peeled_kc  = depth & ~(pk-1);\n    const Index prefetch_res_offset = 32/sizeof(ResScalar);    \n//     const Index depth2     = depth & ~1;\n\n    //---------- Process 3 * LhsProgress rows at once ----------\n    // This corresponds to 3*LhsProgress x nr register blocks.\n    // Usually, make sense only with FMA\n    if(mr>=3*Traits::LhsProgress)\n    {\n      // Here, the general idea is to loop on each largest micro horizontal panel of the lhs (3*Traits::LhsProgress x depth)\n      // and on each largest micro vertical panel of the rhs (depth * nr).\n      // Blocking sizes, i.e., 'depth' has been computed so that the micro horizontal panel of the lhs fit in L1.\n      // However, if depth is too small, we can extend the number of rows of these horizontal panels.\n      // This actual number of rows is computed as follow:\n      const Index l1 = defaultL1CacheSize; // in Bytes, TODO, l1 should be passed to this function.\n      // The max(1, ...) here is needed because we may be using blocking params larger than what our known l1 cache size\n      // suggests we should be using: either because our known l1 cache size is inaccurate (e.g. on Android, we can only guess),\n      // or because we are testing specific blocking sizes.\n      const Index actual_panel_rows = (3*LhsProgress) * std::max<Index>(1,( (l1 - sizeof(ResScalar)*mr*nr - depth*nr*sizeof(RhsScalar)) / (depth * sizeof(LhsScalar) * 3*LhsProgress) ));\n      for(Index i1=0; i1<peeled_mc3; i1+=actual_panel_rows)\n      {\n        const Index actual_panel_end = (std::min)(i1+actual_panel_rows, peeled_mc3);\n        for(Index j2=0; j2<packet_cols4; j2+=nr)\n        {\n          for(Index i=i1; i<actual_panel_end; i+=3*LhsProgress)\n          {\n          \n          // We selected a 3*Traits::LhsProgress x nr micro block of res which is entirely\n          // stored into 3 x nr registers.\n          \n          const LhsScalar* blA = &blockA[i*strideA+offsetA*(3*LhsProgress)];\n          prefetch(&blA[0]);\n\n          // gets res block as register\n          AccPacket C0, C1, C2,  C3,\n                    C4, C5, C6,  C7,\n                    C8, C9, C10, C11;\n          traits.initAcc(C0);  traits.initAcc(C1);  traits.initAcc(C2);  traits.initAcc(C3);\n          traits.initAcc(C4);  traits.initAcc(C5);  traits.initAcc(C6);  traits.initAcc(C7);\n          traits.initAcc(C8);  traits.initAcc(C9);  traits.initAcc(C10); traits.initAcc(C11);\n\n          LinearMapper r0 = res.getLinearMapper(i, j2 + 0);\n          LinearMapper r1 = res.getLinearMapper(i, j2 + 1);\n          LinearMapper r2 = res.getLinearMapper(i, j2 + 2);\n          LinearMapper r3 = res.getLinearMapper(i, j2 + 3);\n\n          r0.prefetch(0);\n          r1.prefetch(0);\n          r2.prefetch(0);\n          r3.prefetch(0);\n\n          // performs \"inner\" products\n          const RhsScalar* blB = &blockB[j2*strideB+offsetB*nr];\n          prefetch(&blB[0]);\n          LhsPacket A0, A1;\n\n          for(Index k=0; k<peeled_kc; k+=pk)\n          {\n            EIGEN_ASM_COMMENT(\"begin gebp micro kernel 3pX4\");\n            RhsPacket B_0, T0;\n            LhsPacket A2;\n\n#define EIGEN_GEBP_ONESTEP(K) \\\n            do { \\\n              EIGEN_ASM_COMMENT(\"begin step of gebp micro kernel 3pX4\"); \\\n              EIGEN_ASM_COMMENT(\"Note: these asm comments work around bug 935!\"); \\\n              internal::prefetch(blA+(3*K+16)*LhsProgress); \\\n              if (EIGEN_ARCH_ARM) { internal::prefetch(blB+(4*K+16)*RhsProgress); } /* Bug 953 */ \\\n              traits.loadLhs(&blA[(0+3*K)*LhsProgress], A0);  \\\n              traits.loadLhs(&blA[(1+3*K)*LhsProgress], A1);  \\\n              traits.loadLhs(&blA[(2+3*K)*LhsProgress], A2);  \\\n              traits.loadRhs(blB + (0+4*K)*Traits::RhsProgress, B_0); \\\n              traits.madd(A0, B_0, C0, T0); \\\n              traits.madd(A1, B_0, C4, T0); \\\n              traits.madd(A2, B_0, C8, B_0); \\\n              traits.loadRhs(blB + (1+4*K)*Traits::RhsProgress, B_0); \\\n              traits.madd(A0, B_0, C1, T0); \\\n              traits.madd(A1, B_0, C5, T0); \\\n              traits.madd(A2, B_0, C9, B_0); \\\n              traits.loadRhs(blB + (2+4*K)*Traits::RhsProgress, B_0); \\\n              traits.madd(A0, B_0, C2,  T0); \\\n              traits.madd(A1, B_0, C6,  T0); \\\n              traits.madd(A2, B_0, C10, B_0); \\\n              traits.loadRhs(blB + (3+4*K)*Traits::RhsProgress, B_0); \\\n              traits.madd(A0, B_0, C3 , T0); \\\n              traits.madd(A1, B_0, C7,  T0); \\\n              traits.madd(A2, B_0, C11, B_0); \\\n              EIGEN_ASM_COMMENT(\"end step of gebp micro kernel 3pX4\"); \\\n            } while(false)\n\n            internal::prefetch(blB);\n            EIGEN_GEBP_ONESTEP(0);\n            EIGEN_GEBP_ONESTEP(1);\n            EIGEN_GEBP_ONESTEP(2);\n            EIGEN_GEBP_ONESTEP(3);\n            EIGEN_GEBP_ONESTEP(4);\n            EIGEN_GEBP_ONESTEP(5);\n            EIGEN_GEBP_ONESTEP(6);\n            EIGEN_GEBP_ONESTEP(7);\n\n            blB += pk*4*RhsProgress;\n            blA += pk*3*Traits::LhsProgress;\n\n            EIGEN_ASM_COMMENT(\"end gebp micro kernel 3pX4\");\n          }\n          // process remaining peeled loop\n          for(Index k=peeled_kc; k<depth; k++)\n          {\n            RhsPacket B_0, T0;\n            LhsPacket A2;\n            EIGEN_GEBP_ONESTEP(0);\n            blB += 4*RhsProgress;\n            blA += 3*Traits::LhsProgress;\n          }\n\n#undef EIGEN_GEBP_ONESTEP\n\n          ResPacket R0, R1, R2;\n          ResPacket alphav = pset1<ResPacket>(alpha);\n\n          R0 = r0.loadPacket(0 * Traits::ResPacketSize);\n          R1 = r0.loadPacket(1 * Traits::ResPacketSize);\n          R2 = r0.loadPacket(2 * Traits::ResPacketSize);\n          traits.acc(C0, alphav, R0);\n          traits.acc(C4, alphav, R1);\n          traits.acc(C8, alphav, R2);\n          r0.storePacket(0 * Traits::ResPacketSize, R0);\n          r0.storePacket(1 * Traits::ResPacketSize, R1);\n          r0.storePacket(2 * Traits::ResPacketSize, R2);\n\n          R0 = r1.loadPacket(0 * Traits::ResPacketSize);\n          R1 = r1.loadPacket(1 * Traits::ResPacketSize);\n          R2 = r1.loadPacket(2 * Traits::ResPacketSize);\n          traits.acc(C1, alphav, R0);\n          traits.acc(C5, alphav, R1);\n          traits.acc(C9, alphav, R2);\n          r1.storePacket(0 * Traits::ResPacketSize, R0);\n          r1.storePacket(1 * Traits::ResPacketSize, R1);\n          r1.storePacket(2 * Traits::ResPacketSize, R2);\n\n          R0 = r2.loadPacket(0 * Traits::ResPacketSize);\n          R1 = r2.loadPacket(1 * Traits::ResPacketSize);\n          R2 = r2.loadPacket(2 * Traits::ResPacketSize);\n          traits.acc(C2, alphav, R0);\n          traits.acc(C6, alphav, R1);\n          traits.acc(C10, alphav, R2);\n          r2.storePacket(0 * Traits::ResPacketSize, R0);\n          r2.storePacket(1 * Traits::ResPacketSize, R1);\n          r2.storePacket(2 * Traits::ResPacketSize, R2);\n\n          R0 = r3.loadPacket(0 * Traits::ResPacketSize);\n          R1 = r3.loadPacket(1 * Traits::ResPacketSize);\n          R2 = r3.loadPacket(2 * Traits::ResPacketSize);\n          traits.acc(C3, alphav, R0);\n          traits.acc(C7, alphav, R1);\n          traits.acc(C11, alphav, R2);\n          r3.storePacket(0 * Traits::ResPacketSize, R0);\n          r3.storePacket(1 * Traits::ResPacketSize, R1);\n          r3.storePacket(2 * Traits::ResPacketSize, R2);          \n          }\n        }\n\n        // Deal with remaining columns of the rhs\n        for(Index j2=packet_cols4; j2<cols; j2++)\n        {\n          for(Index i=i1; i<actual_panel_end; i+=3*LhsProgress)\n          {\n          // One column at a time\n          const LhsScalar* blA = &blockA[i*strideA+offsetA*(3*Traits::LhsProgress)];\n          prefetch(&blA[0]);\n\n          // gets res block as register\n          AccPacket C0, C4, C8;\n          traits.initAcc(C0);\n          traits.initAcc(C4);\n          traits.initAcc(C8);\n\n          LinearMapper r0 = res.getLinearMapper(i, j2);\n          r0.prefetch(0);\n\n          // performs \"inner\" products\n          const RhsScalar* blB = &blockB[j2*strideB+offsetB];\n          LhsPacket A0, A1, A2;\n          \n          for(Index k=0; k<peeled_kc; k+=pk)\n          {\n            EIGEN_ASM_COMMENT(\"begin gebp micro kernel 3pX1\");\n            RhsPacket B_0;\n#define EIGEN_GEBGP_ONESTEP(K) \\\n            do { \\\n              EIGEN_ASM_COMMENT(\"begin step of gebp micro kernel 3pX1\"); \\\n              EIGEN_ASM_COMMENT(\"Note: these asm comments work around bug 935!\"); \\\n              traits.loadLhs(&blA[(0+3*K)*LhsProgress], A0);  \\\n              traits.loadLhs(&blA[(1+3*K)*LhsProgress], A1);  \\\n              traits.loadLhs(&blA[(2+3*K)*LhsProgress], A2);  \\\n              traits.loadRhs(&blB[(0+K)*RhsProgress], B_0);   \\\n              traits.madd(A0, B_0, C0, B_0); \\\n              traits.madd(A1, B_0, C4, B_0); \\\n              traits.madd(A2, B_0, C8, B_0); \\\n              EIGEN_ASM_COMMENT(\"end step of gebp micro kernel 3pX1\"); \\\n            } while(false)\n        \n            EIGEN_GEBGP_ONESTEP(0);\n            EIGEN_GEBGP_ONESTEP(1);\n            EIGEN_GEBGP_ONESTEP(2);\n            EIGEN_GEBGP_ONESTEP(3);\n            EIGEN_GEBGP_ONESTEP(4);\n            EIGEN_GEBGP_ONESTEP(5);\n            EIGEN_GEBGP_ONESTEP(6);\n            EIGEN_GEBGP_ONESTEP(7);\n\n            blB += pk*RhsProgress;\n            blA += pk*3*Traits::LhsProgress;\n\n            EIGEN_ASM_COMMENT(\"end gebp micro kernel 3pX1\");\n          }\n\n          // process remaining peeled loop\n          for(Index k=peeled_kc; k<depth; k++)\n          {\n            RhsPacket B_0;\n            EIGEN_GEBGP_ONESTEP(0);\n            blB += RhsProgress;\n            blA += 3*Traits::LhsProgress;\n          }\n#undef EIGEN_GEBGP_ONESTEP\n          ResPacket R0, R1, R2;\n          ResPacket alphav = pset1<ResPacket>(alpha);\n\n          R0 = r0.loadPacket(0 * Traits::ResPacketSize);\n          R1 = r0.loadPacket(1 * Traits::ResPacketSize);\n          R2 = r0.loadPacket(2 * Traits::ResPacketSize);\n          traits.acc(C0, alphav, R0);\n          traits.acc(C4, alphav, R1);\n          traits.acc(C8, alphav, R2);\n          r0.storePacket(0 * Traits::ResPacketSize, R0);\n          r0.storePacket(1 * Traits::ResPacketSize, R1);\n          r0.storePacket(2 * Traits::ResPacketSize, R2);          \n          }\n        }\n      }\n    }\n\n    //---------- Process 2 * LhsProgress rows at once ----------\n    if(mr>=2*Traits::LhsProgress)\n    {\n      const Index l1 = defaultL1CacheSize; // in Bytes, TODO, l1 should be passed to this function.\n      // The max(1, ...) here is needed because we may be using blocking params larger than what our known l1 cache size\n      // suggests we should be using: either because our known l1 cache size is inaccurate (e.g. on Android, we can only guess),\n      // or because we are testing specific blocking sizes.\n      Index actual_panel_rows = (2*LhsProgress) * std::max<Index>(1,( (l1 - sizeof(ResScalar)*mr*nr - depth*nr*sizeof(RhsScalar)) / (depth * sizeof(LhsScalar) * 2*LhsProgress) ));\n\n      for(Index i1=peeled_mc3; i1<peeled_mc2; i1+=actual_panel_rows)\n      {\n        Index actual_panel_end = (std::min)(i1+actual_panel_rows, peeled_mc2);\n        for(Index j2=0; j2<packet_cols4; j2+=nr)\n        {\n          for(Index i=i1; i<actual_panel_end; i+=2*LhsProgress)\n          {\n          \n          // We selected a 2*Traits::LhsProgress x nr micro block of res which is entirely\n          // stored into 2 x nr registers.\n          \n          const LhsScalar* blA = &blockA[i*strideA+offsetA*(2*Traits::LhsProgress)];\n          prefetch(&blA[0]);\n\n          // gets res block as register\n          AccPacket C0, C1, C2, C3,\n                    C4, C5, C6, C7;\n          traits.initAcc(C0); traits.initAcc(C1); traits.initAcc(C2); traits.initAcc(C3);\n          traits.initAcc(C4); traits.initAcc(C5); traits.initAcc(C6); traits.initAcc(C7);\n\n          LinearMapper r0 = res.getLinearMapper(i, j2 + 0);\n          LinearMapper r1 = res.getLinearMapper(i, j2 + 1);\n          LinearMapper r2 = res.getLinearMapper(i, j2 + 2);\n          LinearMapper r3 = res.getLinearMapper(i, j2 + 3);\n\n          r0.prefetch(prefetch_res_offset);\n          r1.prefetch(prefetch_res_offset);\n          r2.prefetch(prefetch_res_offset);\n          r3.prefetch(prefetch_res_offset);\n\n          // performs \"inner\" products\n          const RhsScalar* blB = &blockB[j2*strideB+offsetB*nr];\n          prefetch(&blB[0]);\n          LhsPacket A0, A1;\n\n          for(Index k=0; k<peeled_kc; k+=pk)\n          {\n            EIGEN_ASM_COMMENT(\"begin gebp micro kernel 2pX4\");\n            RhsPacket B_0, B1, B2, B3, T0;\n\n   #define EIGEN_GEBGP_ONESTEP(K) \\\n            do {                                                                \\\n              EIGEN_ASM_COMMENT(\"begin step of gebp micro kernel 2pX4\");        \\\n              EIGEN_ASM_COMMENT(\"Note: these asm comments work around bug 935!\"); \\\n              traits.loadLhs(&blA[(0+2*K)*LhsProgress], A0);                    \\\n              traits.loadLhs(&blA[(1+2*K)*LhsProgress], A1);                    \\\n              traits.broadcastRhs(&blB[(0+4*K)*RhsProgress], B_0, B1, B2, B3);  \\\n              traits.madd(A0, B_0, C0, T0);                                     \\\n              traits.madd(A1, B_0, C4, B_0);                                    \\\n              traits.madd(A0, B1,  C1, T0);                                     \\\n              traits.madd(A1, B1,  C5, B1);                                     \\\n              traits.madd(A0, B2,  C2, T0);                                     \\\n              traits.madd(A1, B2,  C6, B2);                                     \\\n              traits.madd(A0, B3,  C3, T0);                                     \\\n              traits.madd(A1, B3,  C7, B3);                                     \\\n              EIGEN_ASM_COMMENT(\"end step of gebp micro kernel 2pX4\");          \\\n            } while(false)\n            \n            internal::prefetch(blB+(48+0));\n            EIGEN_GEBGP_ONESTEP(0);\n            EIGEN_GEBGP_ONESTEP(1);\n            EIGEN_GEBGP_ONESTEP(2);\n            EIGEN_GEBGP_ONESTEP(3);\n            internal::prefetch(blB+(48+16));\n            EIGEN_GEBGP_ONESTEP(4);\n            EIGEN_GEBGP_ONESTEP(5);\n            EIGEN_GEBGP_ONESTEP(6);\n            EIGEN_GEBGP_ONESTEP(7);\n\n            blB += pk*4*RhsProgress;\n            blA += pk*(2*Traits::LhsProgress);\n\n            EIGEN_ASM_COMMENT(\"end gebp micro kernel 2pX4\");\n          }\n          // process remaining peeled loop\n          for(Index k=peeled_kc; k<depth; k++)\n          {\n            RhsPacket B_0, B1, B2, B3, T0;\n            EIGEN_GEBGP_ONESTEP(0);\n            blB += 4*RhsProgress;\n            blA += 2*Traits::LhsProgress;\n          }\n#undef EIGEN_GEBGP_ONESTEP\n\n          ResPacket R0, R1, R2, R3;\n          ResPacket alphav = pset1<ResPacket>(alpha);\n\n          R0 = r0.loadPacket(0 * Traits::ResPacketSize);\n          R1 = r0.loadPacket(1 * Traits::ResPacketSize);\n          R2 = r1.loadPacket(0 * Traits::ResPacketSize);\n          R3 = r1.loadPacket(1 * Traits::ResPacketSize);\n          traits.acc(C0, alphav, R0);\n          traits.acc(C4, alphav, R1);\n          traits.acc(C1, alphav, R2);\n          traits.acc(C5, alphav, R3);\n          r0.storePacket(0 * Traits::ResPacketSize, R0);\n          r0.storePacket(1 * Traits::ResPacketSize, R1);\n          r1.storePacket(0 * Traits::ResPacketSize, R2);\n          r1.storePacket(1 * Traits::ResPacketSize, R3);\n\n          R0 = r2.loadPacket(0 * Traits::ResPacketSize);\n          R1 = r2.loadPacket(1 * Traits::ResPacketSize);\n          R2 = r3.loadPacket(0 * Traits::ResPacketSize);\n          R3 = r3.loadPacket(1 * Traits::ResPacketSize);\n          traits.acc(C2,  alphav, R0);\n          traits.acc(C6,  alphav, R1);\n          traits.acc(C3,  alphav, R2);\n          traits.acc(C7,  alphav, R3);\n          r2.storePacket(0 * Traits::ResPacketSize, R0);\n          r2.storePacket(1 * Traits::ResPacketSize, R1);\n          r3.storePacket(0 * Traits::ResPacketSize, R2);\n          r3.storePacket(1 * Traits::ResPacketSize, R3);\n          }\n        }\n      \n        // Deal with remaining columns of the rhs\n        for(Index j2=packet_cols4; j2<cols; j2++)\n        {\n          for(Index i=i1; i<actual_panel_end; i+=2*LhsProgress)\n          {\n          // One column at a time\n          const LhsScalar* blA = &blockA[i*strideA+offsetA*(2*Traits::LhsProgress)];\n          prefetch(&blA[0]);\n\n          // gets res block as register\n          AccPacket C0, C4;\n          traits.initAcc(C0);\n          traits.initAcc(C4);\n\n          LinearMapper r0 = res.getLinearMapper(i, j2);\n          r0.prefetch(prefetch_res_offset);\n\n          // performs \"inner\" products\n          const RhsScalar* blB = &blockB[j2*strideB+offsetB];\n          LhsPacket A0, A1;\n\n          for(Index k=0; k<peeled_kc; k+=pk)\n          {\n            EIGEN_ASM_COMMENT(\"begin gebp micro kernel 2pX1\");\n            RhsPacket B_0, B1;\n        \n#define EIGEN_GEBGP_ONESTEP(K) \\\n            do {                                                                  \\\n              EIGEN_ASM_COMMENT(\"begin step of gebp micro kernel 2pX1\");          \\\n              EIGEN_ASM_COMMENT(\"Note: these asm comments work around bug 935!\"); \\\n              traits.loadLhs(&blA[(0+2*K)*LhsProgress], A0);                      \\\n              traits.loadLhs(&blA[(1+2*K)*LhsProgress], A1);                      \\\n              traits.loadRhs(&blB[(0+K)*RhsProgress], B_0);                       \\\n              traits.madd(A0, B_0, C0, B1);                                       \\\n              traits.madd(A1, B_0, C4, B_0);                                      \\\n              EIGEN_ASM_COMMENT(\"end step of gebp micro kernel 2pX1\");            \\\n            } while(false)\n        \n            EIGEN_GEBGP_ONESTEP(0);\n            EIGEN_GEBGP_ONESTEP(1);\n            EIGEN_GEBGP_ONESTEP(2);\n            EIGEN_GEBGP_ONESTEP(3);\n            EIGEN_GEBGP_ONESTEP(4);\n            EIGEN_GEBGP_ONESTEP(5);\n            EIGEN_GEBGP_ONESTEP(6);\n            EIGEN_GEBGP_ONESTEP(7);\n\n            blB += pk*RhsProgress;\n            blA += pk*2*Traits::LhsProgress;\n\n            EIGEN_ASM_COMMENT(\"end gebp micro kernel 2pX1\");\n          }\n\n          // process remaining peeled loop\n          for(Index k=peeled_kc; k<depth; k++)\n          {\n            RhsPacket B_0, B1;\n            EIGEN_GEBGP_ONESTEP(0);\n            blB += RhsProgress;\n            blA += 2*Traits::LhsProgress;\n          }\n#undef EIGEN_GEBGP_ONESTEP\n          ResPacket R0, R1;\n          ResPacket alphav = pset1<ResPacket>(alpha);\n\n          R0 = r0.loadPacket(0 * Traits::ResPacketSize);\n          R1 = r0.loadPacket(1 * Traits::ResPacketSize);\n          traits.acc(C0, alphav, R0);\n          traits.acc(C4, alphav, R1);\n          r0.storePacket(0 * Traits::ResPacketSize, R0);\n          r0.storePacket(1 * Traits::ResPacketSize, R1);\n          }\n        }\n      }\n    }\n    //---------- Process 1 * LhsProgress rows at once ----------\n    if(mr>=1*Traits::LhsProgress)\n    {\n      // loops on each largest micro horizontal panel of lhs (1*LhsProgress x depth)\n      for(Index i=peeled_mc2; i<peeled_mc1; i+=1*LhsProgress)\n      {\n        // loops on each largest micro vertical panel of rhs (depth * nr)\n        for(Index j2=0; j2<packet_cols4; j2+=nr)\n        {\n          // We select a 1*Traits::LhsProgress x nr micro block of res which is entirely\n          // stored into 1 x nr registers.\n          \n          const LhsScalar* blA = &blockA[i*strideA+offsetA*(1*Traits::LhsProgress)];\n          prefetch(&blA[0]);\n\n          // gets res block as register\n          AccPacket C0, C1, C2, C3;\n          traits.initAcc(C0);\n          traits.initAcc(C1);\n          traits.initAcc(C2);\n          traits.initAcc(C3);\n\n          LinearMapper r0 = res.getLinearMapper(i, j2 + 0);\n          LinearMapper r1 = res.getLinearMapper(i, j2 + 1);\n          LinearMapper r2 = res.getLinearMapper(i, j2 + 2);\n          LinearMapper r3 = res.getLinearMapper(i, j2 + 3);\n\n          r0.prefetch(prefetch_res_offset);\n          r1.prefetch(prefetch_res_offset);\n          r2.prefetch(prefetch_res_offset);\n          r3.prefetch(prefetch_res_offset);\n\n          // performs \"inner\" products\n          const RhsScalar* blB = &blockB[j2*strideB+offsetB*nr];\n          prefetch(&blB[0]);\n          LhsPacket A0;\n\n          for(Index k=0; k<peeled_kc; k+=pk)\n          {\n            EIGEN_ASM_COMMENT(\"begin gebp micro kernel 1pX4\");\n            RhsPacket B_0, B1, B2, B3;\n               \n#define EIGEN_GEBGP_ONESTEP(K) \\\n            do {                                                                \\\n              EIGEN_ASM_COMMENT(\"begin step of gebp micro kernel 1pX4\");        \\\n              EIGEN_ASM_COMMENT(\"Note: these asm comments work around bug 935!\"); \\\n              traits.loadLhs(&blA[(0+1*K)*LhsProgress], A0);                    \\\n              traits.broadcastRhs(&blB[(0+4*K)*RhsProgress], B_0, B1, B2, B3);  \\\n              traits.madd(A0, B_0, C0, B_0);                                    \\\n              traits.madd(A0, B1,  C1, B1);                                     \\\n              traits.madd(A0, B2,  C2, B2);                                     \\\n              traits.madd(A0, B3,  C3, B3);                                     \\\n              EIGEN_ASM_COMMENT(\"end step of gebp micro kernel 1pX4\");          \\\n            } while(false)\n            \n            internal::prefetch(blB+(48+0));\n            EIGEN_GEBGP_ONESTEP(0);\n            EIGEN_GEBGP_ONESTEP(1);\n            EIGEN_GEBGP_ONESTEP(2);\n            EIGEN_GEBGP_ONESTEP(3);\n            internal::prefetch(blB+(48+16));\n            EIGEN_GEBGP_ONESTEP(4);\n            EIGEN_GEBGP_ONESTEP(5);\n            EIGEN_GEBGP_ONESTEP(6);\n            EIGEN_GEBGP_ONESTEP(7);\n\n            blB += pk*4*RhsProgress;\n            blA += pk*1*LhsProgress;\n\n            EIGEN_ASM_COMMENT(\"end gebp micro kernel 1pX4\");\n          }\n          // process remaining peeled loop\n          for(Index k=peeled_kc; k<depth; k++)\n          {\n            RhsPacket B_0, B1, B2, B3;\n            EIGEN_GEBGP_ONESTEP(0);\n            blB += 4*RhsProgress;\n            blA += 1*LhsProgress;\n          }\n#undef EIGEN_GEBGP_ONESTEP\n\n          ResPacket R0, R1;\n          ResPacket alphav = pset1<ResPacket>(alpha);\n\n          R0 = r0.loadPacket(0 * Traits::ResPacketSize);\n          R1 = r1.loadPacket(0 * Traits::ResPacketSize);\n          traits.acc(C0, alphav, R0);\n          traits.acc(C1,  alphav, R1);\n          r0.storePacket(0 * Traits::ResPacketSize, R0);\n          r1.storePacket(0 * Traits::ResPacketSize, R1);\n\n          R0 = r2.loadPacket(0 * Traits::ResPacketSize);\n          R1 = r3.loadPacket(0 * Traits::ResPacketSize);\n          traits.acc(C2,  alphav, R0);\n          traits.acc(C3,  alphav, R1);\n          r2.storePacket(0 * Traits::ResPacketSize, R0);\n          r3.storePacket(0 * Traits::ResPacketSize, R1);\n        }\n\n        // Deal with remaining columns of the rhs\n        for(Index j2=packet_cols4; j2<cols; j2++)\n        {\n          // One column at a time\n          const LhsScalar* blA = &blockA[i*strideA+offsetA*(1*Traits::LhsProgress)];\n          prefetch(&blA[0]);\n\n          // gets res block as register\n          AccPacket C0;\n          traits.initAcc(C0);\n\n          LinearMapper r0 = res.getLinearMapper(i, j2);\n\n          // performs \"inner\" products\n          const RhsScalar* blB = &blockB[j2*strideB+offsetB];\n          LhsPacket A0;\n\n          for(Index k=0; k<peeled_kc; k+=pk)\n          {\n            EIGEN_ASM_COMMENT(\"begin gebp micro kernel 1pX1\");\n            RhsPacket B_0;\n        \n#define EIGEN_GEBGP_ONESTEP(K) \\\n            do {                                                                \\\n              EIGEN_ASM_COMMENT(\"begin step of gebp micro kernel 1pX1\");        \\\n              EIGEN_ASM_COMMENT(\"Note: these asm comments work around bug 935!\"); \\\n              traits.loadLhs(&blA[(0+1*K)*LhsProgress], A0);                    \\\n              traits.loadRhs(&blB[(0+K)*RhsProgress], B_0);                     \\\n              traits.madd(A0, B_0, C0, B_0);                                    \\\n              EIGEN_ASM_COMMENT(\"end step of gebp micro kernel 1pX1\");          \\\n            } while(false);\n\n            EIGEN_GEBGP_ONESTEP(0);\n            EIGEN_GEBGP_ONESTEP(1);\n            EIGEN_GEBGP_ONESTEP(2);\n            EIGEN_GEBGP_ONESTEP(3);\n            EIGEN_GEBGP_ONESTEP(4);\n            EIGEN_GEBGP_ONESTEP(5);\n            EIGEN_GEBGP_ONESTEP(6);\n            EIGEN_GEBGP_ONESTEP(7);\n\n            blB += pk*RhsProgress;\n            blA += pk*1*Traits::LhsProgress;\n\n            EIGEN_ASM_COMMENT(\"end gebp micro kernel 1pX1\");\n          }\n\n          // process remaining peeled loop\n          for(Index k=peeled_kc; k<depth; k++)\n          {\n            RhsPacket B_0;\n            EIGEN_GEBGP_ONESTEP(0);\n            blB += RhsProgress;\n            blA += 1*Traits::LhsProgress;\n          }\n#undef EIGEN_GEBGP_ONESTEP\n          ResPacket R0;\n          ResPacket alphav = pset1<ResPacket>(alpha);\n          R0 = r0.loadPacket(0 * Traits::ResPacketSize);\n          traits.acc(C0, alphav, R0);\n          r0.storePacket(0 * Traits::ResPacketSize, R0);\n        }\n      }\n    }\n    //---------- Process remaining rows, 1 at once ----------\n    if(peeled_mc1<rows)\n    {\n      // loop on each panel of the rhs\n      for(Index j2=0; j2<packet_cols4; j2+=nr)\n      {\n        // loop on each row of the lhs (1*LhsProgress x depth)\n        for(Index i=peeled_mc1; i<rows; i+=1)\n        {\n          const LhsScalar* blA = &blockA[i*strideA+offsetA];\n          prefetch(&blA[0]);\n          const RhsScalar* blB = &blockB[j2*strideB+offsetB*nr];\n\n          // The following piece of code wont work for 512 bit registers\n          // Moreover, if LhsProgress==8 it assumes that there is a half packet of the same size\n          // as nr (which is currently 4) for the return type.\n          typedef typename unpacket_traits<SResPacket>::half SResPacketHalf;\n          if ((SwappedTraits::LhsProgress % 4) == 0 &&\n              (SwappedTraits::LhsProgress <= 8) &&\n              (SwappedTraits::LhsProgress!=8 || unpacket_traits<SResPacketHalf>::size==nr))\n          {\n            SAccPacket C0, C1, C2, C3;\n            straits.initAcc(C0);\n            straits.initAcc(C1);\n            straits.initAcc(C2);\n            straits.initAcc(C3);\n\n            const Index spk   = (std::max)(1,SwappedTraits::LhsProgress/4);\n            const Index endk  = (depth/spk)*spk;\n            const Index endk4 = (depth/(spk*4))*(spk*4);\n\n            Index k=0;\n            for(; k<endk4; k+=4*spk)\n            {\n              SLhsPacket A0,A1;\n              SRhsPacket B_0,B_1;\n\n              straits.loadLhsUnaligned(blB+0*SwappedTraits::LhsProgress, A0);\n              straits.loadLhsUnaligned(blB+1*SwappedTraits::LhsProgress, A1);\n\n              straits.loadRhsQuad(blA+0*spk, B_0);\n              straits.loadRhsQuad(blA+1*spk, B_1);\n              straits.madd(A0,B_0,C0,B_0);\n              straits.madd(A1,B_1,C1,B_1);\n\n              straits.loadLhsUnaligned(blB+2*SwappedTraits::LhsProgress, A0);\n              straits.loadLhsUnaligned(blB+3*SwappedTraits::LhsProgress, A1);\n              straits.loadRhsQuad(blA+2*spk, B_0);\n              straits.loadRhsQuad(blA+3*spk, B_1);\n              straits.madd(A0,B_0,C2,B_0);\n              straits.madd(A1,B_1,C3,B_1);\n\n              blB += 4*SwappedTraits::LhsProgress;\n              blA += 4*spk;\n            }\n            C0 = padd(padd(C0,C1),padd(C2,C3));\n            for(; k<endk; k+=spk)\n            {\n              SLhsPacket A0;\n              SRhsPacket B_0;\n\n              straits.loadLhsUnaligned(blB, A0);\n              straits.loadRhsQuad(blA, B_0);\n              straits.madd(A0,B_0,C0,B_0);\n\n              blB += SwappedTraits::LhsProgress;\n              blA += spk;\n            }\n            if(SwappedTraits::LhsProgress==8)\n            {\n              // Special case where we have to first reduce the accumulation register C0\n              typedef typename conditional<SwappedTraits::LhsProgress>=8,typename unpacket_traits<SResPacket>::half,SResPacket>::type SResPacketHalf;\n              typedef typename conditional<SwappedTraits::LhsProgress>=8,typename unpacket_traits<SLhsPacket>::half,SLhsPacket>::type SLhsPacketHalf;\n              typedef typename conditional<SwappedTraits::LhsProgress>=8,typename unpacket_traits<SLhsPacket>::half,SRhsPacket>::type SRhsPacketHalf;\n              typedef typename conditional<SwappedTraits::LhsProgress>=8,typename unpacket_traits<SAccPacket>::half,SAccPacket>::type SAccPacketHalf;\n\n              SResPacketHalf R = res.template gatherPacket<SResPacketHalf>(i, j2);\n              SResPacketHalf alphav = pset1<SResPacketHalf>(alpha);\n\n              if(depth-endk>0)\n              {\n                // We have to handle the last row of the rhs which corresponds to a half-packet\n                SLhsPacketHalf a0;\n                SRhsPacketHalf b0;\n                straits.loadLhsUnaligned(blB, a0);\n                straits.loadRhs(blA, b0);\n                SAccPacketHalf c0 = predux_downto4(C0);\n                straits.madd(a0,b0,c0,b0);\n                straits.acc(c0, alphav, R);\n              }\n              else\n              {\n                straits.acc(predux_downto4(C0), alphav, R);\n              }\n              res.scatterPacket(i, j2, R);\n            }\n            else\n            {\n              SResPacket R = res.template gatherPacket<SResPacket>(i, j2);\n              SResPacket alphav = pset1<SResPacket>(alpha);\n              straits.acc(C0, alphav, R);\n              res.scatterPacket(i, j2, R);\n            }\n          }\n          else // scalar path\n          {\n            // get a 1 x 4 res block as registers\n            ResScalar C0(0), C1(0), C2(0), C3(0);\n\n            for(Index k=0; k<depth; k++)\n            {\n              LhsScalar A0;\n              RhsScalar B_0, B_1;\n\n              A0 = blA[k];\n\n              B_0 = blB[0];\n              B_1 = blB[1];\n              CJMADD(cj,A0,B_0,C0,  B_0);\n              CJMADD(cj,A0,B_1,C1,  B_1);\n              \n              B_0 = blB[2];\n              B_1 = blB[3];\n              CJMADD(cj,A0,B_0,C2,  B_0);\n              CJMADD(cj,A0,B_1,C3,  B_1);\n              \n              blB += 4;\n            }\n            res(i, j2 + 0) += alpha * C0;\n            res(i, j2 + 1) += alpha * C1;\n            res(i, j2 + 2) += alpha * C2;\n            res(i, j2 + 3) += alpha * C3;\n          }\n        }\n      }\n      // remaining columns\n      for(Index j2=packet_cols4; j2<cols; j2++)\n      {\n        // loop on each row of the lhs (1*LhsProgress x depth)\n        for(Index i=peeled_mc1; i<rows; i+=1)\n        {\n          const LhsScalar* blA = &blockA[i*strideA+offsetA];\n          prefetch(&blA[0]);\n          // gets a 1 x 1 res block as registers\n          ResScalar C0(0);\n          const RhsScalar* blB = &blockB[j2*strideB+offsetB];\n          for(Index k=0; k<depth; k++)\n          {\n            LhsScalar A0 = blA[k];\n            RhsScalar B_0 = blB[k];\n            CJMADD(cj, A0, B_0, C0, B_0);\n          }\n          res(i, j2) += alpha * C0;\n        }\n      }\n    }\n  }\n\n\n#undef CJMADD\n\n// pack a block of the lhs\n// The traversal is as follow (mr==4):\n//   0  4  8 12 ...\n//   1  5  9 13 ...\n//   2  6 10 14 ...\n//   3  7 11 15 ...\n//\n//  16 20 24 28 ...\n//  17 21 25 29 ...\n//  18 22 26 30 ...\n//  19 23 27 31 ...\n//\n//  32 33 34 35 ...\n//  36 36 38 39 ...\ntemplate<typename Scalar, typename Index, typename DataMapper, int Pack1, int Pack2, bool Conjugate, bool PanelMode>\nstruct gemm_pack_lhs<Scalar, Index, DataMapper, Pack1, Pack2, ColMajor, Conjugate, PanelMode>\n{\n  typedef typename DataMapper::LinearMapper LinearMapper;\n  EIGEN_DONT_INLINE void operator()(Scalar* blockA, const DataMapper& lhs, Index depth, Index rows, Index stride=0, Index offset=0);\n};\n\ntemplate<typename Scalar, typename Index, typename DataMapper, int Pack1, int Pack2, bool Conjugate, bool PanelMode>\nEIGEN_DONT_INLINE void gemm_pack_lhs<Scalar, Index, DataMapper, Pack1, Pack2, ColMajor, Conjugate, PanelMode>\n  ::operator()(Scalar* blockA, const DataMapper& lhs, Index depth, Index rows, Index stride, Index offset)\n{\n  typedef typename packet_traits<Scalar>::type Packet;\n  enum { PacketSize = packet_traits<Scalar>::size };\n\n  EIGEN_ASM_COMMENT(\"EIGEN PRODUCT PACK LHS\");\n  EIGEN_UNUSED_VARIABLE(stride);\n  EIGEN_UNUSED_VARIABLE(offset);\n  eigen_assert(((!PanelMode) && stride==0 && offset==0) || (PanelMode && stride>=depth && offset<=stride));\n  eigen_assert( ((Pack1%PacketSize)==0 && Pack1<=4*PacketSize) || (Pack1<=4) );\n  conj_if<NumTraits<Scalar>::IsComplex && Conjugate> cj;\n  Index count = 0;\n\n  const Index peeled_mc3 = Pack1>=3*PacketSize ? (rows/(3*PacketSize))*(3*PacketSize) : 0;\n  const Index peeled_mc2 = Pack1>=2*PacketSize ? peeled_mc3+((rows-peeled_mc3)/(2*PacketSize))*(2*PacketSize) : 0;\n  const Index peeled_mc1 = Pack1>=1*PacketSize ? (rows/(1*PacketSize))*(1*PacketSize) : 0;\n  const Index peeled_mc0 = Pack2>=1*PacketSize ? peeled_mc1\n                         : Pack2>1             ? (rows/Pack2)*Pack2 : 0;\n\n  Index i=0;\n\n  // Pack 3 packets\n  if(Pack1>=3*PacketSize)\n  {\n    for(; i<peeled_mc3; i+=3*PacketSize)\n    {\n      if(PanelMode) count += (3*PacketSize) * offset;\n\n      for(Index k=0; k<depth; k++)\n      {\n        Packet A, B, C;\n        A = lhs.loadPacket(i+0*PacketSize, k);\n        B = lhs.loadPacket(i+1*PacketSize, k);\n        C = lhs.loadPacket(i+2*PacketSize, k);\n        pstore(blockA+count, cj.pconj(A)); count+=PacketSize;\n        pstore(blockA+count, cj.pconj(B)); count+=PacketSize;\n        pstore(blockA+count, cj.pconj(C)); count+=PacketSize;\n      }\n      if(PanelMode) count += (3*PacketSize) * (stride-offset-depth);\n    }\n  }\n  // Pack 2 packets\n  if(Pack1>=2*PacketSize)\n  {\n    for(; i<peeled_mc2; i+=2*PacketSize)\n    {\n      if(PanelMode) count += (2*PacketSize) * offset;\n\n      for(Index k=0; k<depth; k++)\n      {\n        Packet A, B;\n        A = lhs.loadPacket(i+0*PacketSize, k);\n        B = lhs.loadPacket(i+1*PacketSize, k);\n        pstore(blockA+count, cj.pconj(A)); count+=PacketSize;\n        pstore(blockA+count, cj.pconj(B)); count+=PacketSize;\n      }\n      if(PanelMode) count += (2*PacketSize) * (stride-offset-depth);\n    }\n  }\n  // Pack 1 packets\n  if(Pack1>=1*PacketSize)\n  {\n    for(; i<peeled_mc1; i+=1*PacketSize)\n    {\n      if(PanelMode) count += (1*PacketSize) * offset;\n\n      for(Index k=0; k<depth; k++)\n      {\n        Packet A;\n        A = lhs.loadPacket(i+0*PacketSize, k);\n        pstore(blockA+count, cj.pconj(A));\n        count+=PacketSize;\n      }\n      if(PanelMode) count += (1*PacketSize) * (stride-offset-depth);\n    }\n  }\n  // Pack scalars\n  if(Pack2<PacketSize && Pack2>1)\n  {\n    for(; i<peeled_mc0; i+=Pack2)\n    {\n      if(PanelMode) count += Pack2 * offset;\n\n      for(Index k=0; k<depth; k++)\n        for(Index w=0; w<Pack2; w++)\n          blockA[count++] = cj(lhs(i+w, k));\n\n      if(PanelMode) count += Pack2 * (stride-offset-depth);\n    }\n  }\n  for(; i<rows; i++)\n  {\n    if(PanelMode) count += offset;\n    for(Index k=0; k<depth; k++)\n      blockA[count++] = cj(lhs(i, k));\n    if(PanelMode) count += (stride-offset-depth);\n  }\n}\n\ntemplate<typename Scalar, typename Index, typename DataMapper, int Pack1, int Pack2, bool Conjugate, bool PanelMode>\nstruct gemm_pack_lhs<Scalar, Index, DataMapper, Pack1, Pack2, RowMajor, Conjugate, PanelMode>\n{\n  typedef typename DataMapper::LinearMapper LinearMapper;\n  EIGEN_DONT_INLINE void operator()(Scalar* blockA, const DataMapper& lhs, Index depth, Index rows, Index stride=0, Index offset=0);\n};\n\ntemplate<typename Scalar, typename Index, typename DataMapper, int Pack1, int Pack2, bool Conjugate, bool PanelMode>\nEIGEN_DONT_INLINE void gemm_pack_lhs<Scalar, Index, DataMapper, Pack1, Pack2, RowMajor, Conjugate, PanelMode>\n  ::operator()(Scalar* blockA, const DataMapper& lhs, Index depth, Index rows, Index stride, Index offset)\n{\n  typedef typename packet_traits<Scalar>::type Packet;\n  enum { PacketSize = packet_traits<Scalar>::size };\n\n  EIGEN_ASM_COMMENT(\"EIGEN PRODUCT PACK LHS\");\n  EIGEN_UNUSED_VARIABLE(stride);\n  EIGEN_UNUSED_VARIABLE(offset);\n  eigen_assert(((!PanelMode) && stride==0 && offset==0) || (PanelMode && stride>=depth && offset<=stride));\n  conj_if<NumTraits<Scalar>::IsComplex && Conjugate> cj;\n  Index count = 0;\n\n//   const Index peeled_mc3 = Pack1>=3*PacketSize ? (rows/(3*PacketSize))*(3*PacketSize) : 0;\n//   const Index peeled_mc2 = Pack1>=2*PacketSize ? peeled_mc3+((rows-peeled_mc3)/(2*PacketSize))*(2*PacketSize) : 0;\n//   const Index peeled_mc1 = Pack1>=1*PacketSize ? (rows/(1*PacketSize))*(1*PacketSize) : 0;\n\n  int pack = Pack1;\n  Index i = 0;\n  while(pack>0)\n  {\n    Index remaining_rows = rows-i;\n    Index peeled_mc = i+(remaining_rows/pack)*pack;\n    for(; i<peeled_mc; i+=pack)\n    {\n      if(PanelMode) count += pack * offset;\n\n      const Index peeled_k = (depth/PacketSize)*PacketSize;\n      Index k=0;\n      if(pack>=PacketSize)\n      {\n        for(; k<peeled_k; k+=PacketSize)\n        {\n          for (Index m = 0; m < pack; m += PacketSize)\n          {\n            PacketBlock<Packet> kernel;\n            for (int p = 0; p < PacketSize; ++p) kernel.packet[p] = lhs.loadPacket(i+p+m, k);\n            ptranspose(kernel);\n            for (int p = 0; p < PacketSize; ++p) pstore(blockA+count+m+(pack)*p, cj.pconj(kernel.packet[p]));\n          }\n          count += PacketSize*pack;\n        }\n      }\n      for(; k<depth; k++)\n      {\n        Index w=0;\n        for(; w<pack-3; w+=4)\n        {\n          Scalar a(cj(lhs(i+w+0, k))),\n                 b(cj(lhs(i+w+1, k))),\n                 c(cj(lhs(i+w+2, k))),\n                 d(cj(lhs(i+w+3, k)));\n          blockA[count++] = a;\n          blockA[count++] = b;\n          blockA[count++] = c;\n          blockA[count++] = d;\n        }\n        if(pack%4)\n          for(;w<pack;++w)\n            blockA[count++] = cj(lhs(i+w, k));\n      }\n\n      if(PanelMode) count += pack * (stride-offset-depth);\n    }\n\n    pack -= PacketSize;\n    if(pack<Pack2 && (pack+PacketSize)!=Pack2)\n      pack = Pack2;\n  }\n\n  for(; i<rows; i++)\n  {\n    if(PanelMode) count += offset;\n    for(Index k=0; k<depth; k++)\n      blockA[count++] = cj(lhs(i, k));\n    if(PanelMode) count += (stride-offset-depth);\n  }\n}\n\n// copy a complete panel of the rhs\n// this version is optimized for column major matrices\n// The traversal order is as follow: (nr==4):\n//  0  1  2  3   12 13 14 15   24 27\n//  4  5  6  7   16 17 18 19   25 28\n//  8  9 10 11   20 21 22 23   26 29\n//  .  .  .  .    .  .  .  .    .  .\ntemplate<typename Scalar, typename Index, typename DataMapper, int nr, bool Conjugate, bool PanelMode>\nstruct gemm_pack_rhs<Scalar, Index, DataMapper, nr, ColMajor, Conjugate, PanelMode>\n{\n  typedef typename packet_traits<Scalar>::type Packet;\n  typedef typename DataMapper::LinearMapper LinearMapper;\n  enum { PacketSize = packet_traits<Scalar>::size };\n  EIGEN_DONT_INLINE void operator()(Scalar* blockB, const DataMapper& rhs, Index depth, Index cols, Index stride=0, Index offset=0);\n};\n\ntemplate<typename Scalar, typename Index, typename DataMapper, int nr, bool Conjugate, bool PanelMode>\nEIGEN_DONT_INLINE void gemm_pack_rhs<Scalar, Index, DataMapper, nr, ColMajor, Conjugate, PanelMode>\n  ::operator()(Scalar* blockB, const DataMapper& rhs, Index depth, Index cols, Index stride, Index offset)\n{\n  EIGEN_ASM_COMMENT(\"EIGEN PRODUCT PACK RHS COLMAJOR\");\n  EIGEN_UNUSED_VARIABLE(stride);\n  EIGEN_UNUSED_VARIABLE(offset);\n  eigen_assert(((!PanelMode) && stride==0 && offset==0) || (PanelMode && stride>=depth && offset<=stride));\n  conj_if<NumTraits<Scalar>::IsComplex && Conjugate> cj;\n  Index packet_cols8 = nr>=8 ? (cols/8) * 8 : 0;\n  Index packet_cols4 = nr>=4 ? (cols/4) * 4 : 0;\n  Index count = 0;\n  const Index peeled_k = (depth/PacketSize)*PacketSize;\n//   if(nr>=8)\n//   {\n//     for(Index j2=0; j2<packet_cols8; j2+=8)\n//     {\n//       // skip what we have before\n//       if(PanelMode) count += 8 * offset;\n//       const Scalar* b0 = &rhs[(j2+0)*rhsStride];\n//       const Scalar* b1 = &rhs[(j2+1)*rhsStride];\n//       const Scalar* b2 = &rhs[(j2+2)*rhsStride];\n//       const Scalar* b3 = &rhs[(j2+3)*rhsStride];\n//       const Scalar* b4 = &rhs[(j2+4)*rhsStride];\n//       const Scalar* b5 = &rhs[(j2+5)*rhsStride];\n//       const Scalar* b6 = &rhs[(j2+6)*rhsStride];\n//       const Scalar* b7 = &rhs[(j2+7)*rhsStride];\n//       Index k=0;\n//       if(PacketSize==8) // TODO enbale vectorized transposition for PacketSize==4\n//       {\n//         for(; k<peeled_k; k+=PacketSize) {\n//           PacketBlock<Packet> kernel;\n//           for (int p = 0; p < PacketSize; ++p) {\n//             kernel.packet[p] = ploadu<Packet>(&rhs[(j2+p)*rhsStride+k]);\n//           }\n//           ptranspose(kernel);\n//           for (int p = 0; p < PacketSize; ++p) {\n//             pstoreu(blockB+count, cj.pconj(kernel.packet[p]));\n//             count+=PacketSize;\n//           }\n//         }\n//       }\n//       for(; k<depth; k++)\n//       {\n//         blockB[count+0] = cj(b0[k]);\n//         blockB[count+1] = cj(b1[k]);\n//         blockB[count+2] = cj(b2[k]);\n//         blockB[count+3] = cj(b3[k]);\n//         blockB[count+4] = cj(b4[k]);\n//         blockB[count+5] = cj(b5[k]);\n//         blockB[count+6] = cj(b6[k]);\n//         blockB[count+7] = cj(b7[k]);\n//         count += 8;\n//       }\n//       // skip what we have after\n//       if(PanelMode) count += 8 * (stride-offset-depth);\n//     }\n//   }\n\n  if(nr>=4)\n  {\n    for(Index j2=packet_cols8; j2<packet_cols4; j2+=4)\n    {\n      // skip what we have before\n      if(PanelMode) count += 4 * offset;\n      const LinearMapper dm0 = rhs.getLinearMapper(0, j2 + 0);\n      const LinearMapper dm1 = rhs.getLinearMapper(0, j2 + 1);\n      const LinearMapper dm2 = rhs.getLinearMapper(0, j2 + 2);\n      const LinearMapper dm3 = rhs.getLinearMapper(0, j2 + 3);\n\n      Index k=0;\n      if((PacketSize%4)==0) // TODO enable vectorized transposition for PacketSize==2 ??\n      {\n        for(; k<peeled_k; k+=PacketSize) {\n          PacketBlock<Packet,(PacketSize%4)==0?4:PacketSize> kernel;\n          kernel.packet[0] = dm0.loadPacket(k);\n          kernel.packet[1%PacketSize] = dm1.loadPacket(k);\n          kernel.packet[2%PacketSize] = dm2.loadPacket(k);\n          kernel.packet[3%PacketSize] = dm3.loadPacket(k);\n          ptranspose(kernel);\n          pstoreu(blockB+count+0*PacketSize, cj.pconj(kernel.packet[0]));\n          pstoreu(blockB+count+1*PacketSize, cj.pconj(kernel.packet[1%PacketSize]));\n          pstoreu(blockB+count+2*PacketSize, cj.pconj(kernel.packet[2%PacketSize]));\n          pstoreu(blockB+count+3*PacketSize, cj.pconj(kernel.packet[3%PacketSize]));\n          count+=4*PacketSize;\n        }\n      }\n      for(; k<depth; k++)\n      {\n        blockB[count+0] = cj(dm0(k));\n        blockB[count+1] = cj(dm1(k));\n        blockB[count+2] = cj(dm2(k));\n        blockB[count+3] = cj(dm3(k));\n        count += 4;\n      }\n      // skip what we have after\n      if(PanelMode) count += 4 * (stride-offset-depth);\n    }\n  }\n\n  // copy the remaining columns one at a time (nr==1)\n  for(Index j2=packet_cols4; j2<cols; ++j2)\n  {\n    if(PanelMode) count += offset;\n    const LinearMapper dm0 = rhs.getLinearMapper(0, j2);\n    for(Index k=0; k<depth; k++)\n    {\n      blockB[count] = cj(dm0(k));\n      count += 1;\n    }\n    if(PanelMode) count += (stride-offset-depth);\n  }\n}\n\n// this version is optimized for row major matrices\ntemplate<typename Scalar, typename Index, typename DataMapper, int nr, bool Conjugate, bool PanelMode>\nstruct gemm_pack_rhs<Scalar, Index, DataMapper, nr, RowMajor, Conjugate, PanelMode>\n{\n  typedef typename packet_traits<Scalar>::type Packet;\n  typedef typename DataMapper::LinearMapper LinearMapper;\n  enum { PacketSize = packet_traits<Scalar>::size };\n  EIGEN_DONT_INLINE void operator()(Scalar* blockB, const DataMapper& rhs, Index depth, Index cols, Index stride=0, Index offset=0);\n};\n\ntemplate<typename Scalar, typename Index, typename DataMapper, int nr, bool Conjugate, bool PanelMode>\nEIGEN_DONT_INLINE void gemm_pack_rhs<Scalar, Index, DataMapper, nr, RowMajor, Conjugate, PanelMode>\n  ::operator()(Scalar* blockB, const DataMapper& rhs, Index depth, Index cols, Index stride, Index offset)\n{\n  EIGEN_ASM_COMMENT(\"EIGEN PRODUCT PACK RHS ROWMAJOR\");\n  EIGEN_UNUSED_VARIABLE(stride);\n  EIGEN_UNUSED_VARIABLE(offset);\n  eigen_assert(((!PanelMode) && stride==0 && offset==0) || (PanelMode && stride>=depth && offset<=stride));\n  conj_if<NumTraits<Scalar>::IsComplex && Conjugate> cj;\n  Index packet_cols8 = nr>=8 ? (cols/8) * 8 : 0;\n  Index packet_cols4 = nr>=4 ? (cols/4) * 4 : 0;\n  Index count = 0;\n\n//   if(nr>=8)\n//   {\n//     for(Index j2=0; j2<packet_cols8; j2+=8)\n//     {\n//       // skip what we have before\n//       if(PanelMode) count += 8 * offset;\n//       for(Index k=0; k<depth; k++)\n//       {\n//         if (PacketSize==8) {\n//           Packet A = ploadu<Packet>(&rhs[k*rhsStride + j2]);\n//           pstoreu(blockB+count, cj.pconj(A));\n//         } else if (PacketSize==4) {\n//           Packet A = ploadu<Packet>(&rhs[k*rhsStride + j2]);\n//           Packet B = ploadu<Packet>(&rhs[k*rhsStride + j2 + PacketSize]);\n//           pstoreu(blockB+count, cj.pconj(A));\n//           pstoreu(blockB+count+PacketSize, cj.pconj(B));\n//         } else {\n//           const Scalar* b0 = &rhs[k*rhsStride + j2];\n//           blockB[count+0] = cj(b0[0]);\n//           blockB[count+1] = cj(b0[1]);\n//           blockB[count+2] = cj(b0[2]);\n//           blockB[count+3] = cj(b0[3]);\n//           blockB[count+4] = cj(b0[4]);\n//           blockB[count+5] = cj(b0[5]);\n//           blockB[count+6] = cj(b0[6]);\n//           blockB[count+7] = cj(b0[7]);\n//         }\n//         count += 8;\n//       }\n//       // skip what we have after\n//       if(PanelMode) count += 8 * (stride-offset-depth);\n//     }\n//   }\n  if(nr>=4)\n  {\n    for(Index j2=packet_cols8; j2<packet_cols4; j2+=4)\n    {\n      // skip what we have before\n      if(PanelMode) count += 4 * offset;\n      for(Index k=0; k<depth; k++)\n      {\n        if (PacketSize==4) {\n          Packet A = rhs.loadPacket(k, j2);\n          pstoreu(blockB+count, cj.pconj(A));\n          count += PacketSize;\n        } else {\n          const LinearMapper dm0 = rhs.getLinearMapper(k, j2);\n          blockB[count+0] = cj(dm0(0));\n          blockB[count+1] = cj(dm0(1));\n          blockB[count+2] = cj(dm0(2));\n          blockB[count+3] = cj(dm0(3));\n          count += 4;\n        }\n      }\n      // skip what we have after\n      if(PanelMode) count += 4 * (stride-offset-depth);\n    }\n  }\n  // copy the remaining columns one at a time (nr==1)\n  for(Index j2=packet_cols4; j2<cols; ++j2)\n  {\n    if(PanelMode) count += offset;\n    for(Index k=0; k<depth; k++)\n    {\n      blockB[count] = cj(rhs(k, j2));\n      count += 1;\n    }\n    if(PanelMode) count += stride-offset-depth;\n  }\n}\n\n} // end namespace internal\n\n/** \\returns the currently set level 1 cpu cache size (in bytes) used to estimate the ideal blocking size parameters.\n  * \\sa setCpuCacheSize */\ninline std::ptrdiff_t l1CacheSize()\n{\n  std::ptrdiff_t l1, l2, l3;\n  internal::manage_caching_sizes(GetAction, &l1, &l2, &l3);\n  return l1;\n}\n\n/** \\returns the currently set level 2 cpu cache size (in bytes) used to estimate the ideal blocking size parameters.\n  * \\sa setCpuCacheSize */\ninline std::ptrdiff_t l2CacheSize()\n{\n  std::ptrdiff_t l1, l2, l3;\n  internal::manage_caching_sizes(GetAction, &l1, &l2, &l3);\n  return l2;\n}\n\n/** \\returns the currently set level 3 cpu cache size (in bytes) used to estimate the ideal blocking size paramete\\\nrs.                                                                                                                \n* \\sa setCpuCacheSize */\ninline std::ptrdiff_t l3CacheSize()\n{\n  std::ptrdiff_t l1, l2, l3;\n  internal::manage_caching_sizes(GetAction, &l1, &l2, &l3);\n  return l3;\n}\n\n/** Set the cpu L1 and L2 cache sizes (in bytes).\n  * These values are use to adjust the size of the blocks\n  * for the algorithms working per blocks.\n  *\n  * \\sa computeProductBlockingSizes */\ninline void setCpuCacheSizes(std::ptrdiff_t l1, std::ptrdiff_t l2, std::ptrdiff_t l3)\n{\n  internal::manage_caching_sizes(SetAction, &l1, &l2, &l3);\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_GENERAL_BLOCK_PANEL_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/products/GeneralMatrixMatrix.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_GENERAL_MATRIX_MATRIX_H\n#define EIGEN_GENERAL_MATRIX_MATRIX_H\n\nnamespace Eigen {\n\nnamespace internal {\n\ntemplate<typename _LhsScalar, typename _RhsScalar> class level3_blocking;\n\n/* Specialization for a row-major destination matrix => simple transposition of the product */\ntemplate<\n  typename Index,\n  typename LhsScalar, int LhsStorageOrder, bool ConjugateLhs,\n  typename RhsScalar, int RhsStorageOrder, bool ConjugateRhs>\nstruct general_matrix_matrix_product<Index,LhsScalar,LhsStorageOrder,ConjugateLhs,RhsScalar,RhsStorageOrder,ConjugateRhs,RowMajor>\n{\n  typedef gebp_traits<RhsScalar,LhsScalar> Traits;\n\n  typedef typename ScalarBinaryOpTraits<LhsScalar, RhsScalar>::ReturnType ResScalar;\n  static EIGEN_STRONG_INLINE void run(\n    Index rows, Index cols, Index depth,\n    const LhsScalar* lhs, Index lhsStride,\n    const RhsScalar* rhs, Index rhsStride,\n    ResScalar* res, Index resStride,\n    ResScalar alpha,\n    level3_blocking<RhsScalar,LhsScalar>& blocking,\n    GemmParallelInfo<Index>* info = 0)\n  {\n    // transpose the product such that the result is column major\n    general_matrix_matrix_product<Index,\n      RhsScalar, RhsStorageOrder==RowMajor ? ColMajor : RowMajor, ConjugateRhs,\n      LhsScalar, LhsStorageOrder==RowMajor ? ColMajor : RowMajor, ConjugateLhs,\n      ColMajor>\n    ::run(cols,rows,depth,rhs,rhsStride,lhs,lhsStride,res,resStride,alpha,blocking,info);\n  }\n};\n\n/*  Specialization for a col-major destination matrix\n *    => Blocking algorithm following Goto's paper */\ntemplate<\n  typename Index,\n  typename LhsScalar, int LhsStorageOrder, bool ConjugateLhs,\n  typename RhsScalar, int RhsStorageOrder, bool ConjugateRhs>\nstruct general_matrix_matrix_product<Index,LhsScalar,LhsStorageOrder,ConjugateLhs,RhsScalar,RhsStorageOrder,ConjugateRhs,ColMajor>\n{\n\ntypedef gebp_traits<LhsScalar,RhsScalar> Traits;\n\ntypedef typename ScalarBinaryOpTraits<LhsScalar, RhsScalar>::ReturnType ResScalar;\nstatic void run(Index rows, Index cols, Index depth,\n  const LhsScalar* _lhs, Index lhsStride,\n  const RhsScalar* _rhs, Index rhsStride,\n  ResScalar* _res, Index resStride,\n  ResScalar alpha,\n  level3_blocking<LhsScalar,RhsScalar>& blocking,\n  GemmParallelInfo<Index>* info = 0)\n{\n  typedef const_blas_data_mapper<LhsScalar, Index, LhsStorageOrder> LhsMapper;\n  typedef const_blas_data_mapper<RhsScalar, Index, RhsStorageOrder> RhsMapper;\n  typedef blas_data_mapper<typename Traits::ResScalar, Index, ColMajor> ResMapper;\n  LhsMapper lhs(_lhs,lhsStride);\n  RhsMapper rhs(_rhs,rhsStride);\n  ResMapper res(_res, resStride);\n\n  Index kc = blocking.kc();                   // cache block size along the K direction\n  Index mc = (std::min)(rows,blocking.mc());  // cache block size along the M direction\n  Index nc = (std::min)(cols,blocking.nc());  // cache block size along the N direction\n\n  gemm_pack_lhs<LhsScalar, Index, LhsMapper, Traits::mr, Traits::LhsProgress, LhsStorageOrder> pack_lhs;\n  gemm_pack_rhs<RhsScalar, Index, RhsMapper, Traits::nr, RhsStorageOrder> pack_rhs;\n  gebp_kernel<LhsScalar, RhsScalar, Index, ResMapper, Traits::mr, Traits::nr, ConjugateLhs, ConjugateRhs> gebp;\n\n#ifdef EIGEN_HAS_OPENMP\n  if(info)\n  {\n    // this is the parallel version!\n    Index tid = omp_get_thread_num();\n    Index threads = omp_get_num_threads();\n\n    LhsScalar* blockA = blocking.blockA();\n    eigen_internal_assert(blockA!=0);\n\n    std::size_t sizeB = kc*nc;\n    ei_declare_aligned_stack_constructed_variable(RhsScalar, blockB, sizeB, 0);\n\n    // For each horizontal panel of the rhs, and corresponding vertical panel of the lhs...\n    for(Index k=0; k<depth; k+=kc)\n    {\n      const Index actual_kc = (std::min)(k+kc,depth)-k; // => rows of B', and cols of the A'\n\n      // In order to reduce the chance that a thread has to wait for the other,\n      // let's start by packing B'.\n      pack_rhs(blockB, rhs.getSubMapper(k,0), actual_kc, nc);\n\n      // Pack A_k to A' in a parallel fashion:\n      // each thread packs the sub block A_k,i to A'_i where i is the thread id.\n\n      // However, before copying to A'_i, we have to make sure that no other thread is still using it,\n      // i.e., we test that info[tid].users equals 0.\n      // Then, we set info[tid].users to the number of threads to mark that all other threads are going to use it.\n      while(info[tid].users!=0) {}\n      info[tid].users += threads;\n\n      pack_lhs(blockA+info[tid].lhs_start*actual_kc, lhs.getSubMapper(info[tid].lhs_start,k), actual_kc, info[tid].lhs_length);\n\n      // Notify the other threads that the part A'_i is ready to go.\n      info[tid].sync = k;\n\n      // Computes C_i += A' * B' per A'_i\n      for(Index shift=0; shift<threads; ++shift)\n      {\n        Index i = (tid+shift)%threads;\n\n        // At this point we have to make sure that A'_i has been updated by the thread i,\n        // we use testAndSetOrdered to mimic a volatile access.\n        // However, no need to wait for the B' part which has been updated by the current thread!\n        if (shift>0) {\n          while(info[i].sync!=k) {\n          }\n        }\n\n        gebp(res.getSubMapper(info[i].lhs_start, 0), blockA+info[i].lhs_start*actual_kc, blockB, info[i].lhs_length, actual_kc, nc, alpha);\n      }\n\n      // Then keep going as usual with the remaining B'\n      for(Index j=nc; j<cols; j+=nc)\n      {\n        const Index actual_nc = (std::min)(j+nc,cols)-j;\n\n        // pack B_k,j to B'\n        pack_rhs(blockB, rhs.getSubMapper(k,j), actual_kc, actual_nc);\n\n        // C_j += A' * B'\n        gebp(res.getSubMapper(0, j), blockA, blockB, rows, actual_kc, actual_nc, alpha);\n      }\n\n      // Release all the sub blocks A'_i of A' for the current thread,\n      // i.e., we simply decrement the number of users by 1\n      for(Index i=0; i<threads; ++i)\n        #pragma omp atomic\n        info[i].users -= 1;\n    }\n  }\n  else\n#endif // EIGEN_HAS_OPENMP\n  {\n    EIGEN_UNUSED_VARIABLE(info);\n\n    // this is the sequential version!\n    std::size_t sizeA = kc*mc;\n    std::size_t sizeB = kc*nc;\n\n    ei_declare_aligned_stack_constructed_variable(LhsScalar, blockA, sizeA, blocking.blockA());\n    ei_declare_aligned_stack_constructed_variable(RhsScalar, blockB, sizeB, blocking.blockB());\n\n    const bool pack_rhs_once = mc!=rows && kc==depth && nc==cols;\n\n    // For each horizontal panel of the rhs, and corresponding panel of the lhs...\n    for(Index i2=0; i2<rows; i2+=mc)\n    {\n      const Index actual_mc = (std::min)(i2+mc,rows)-i2;\n\n      for(Index k2=0; k2<depth; k2+=kc)\n      {\n        const Index actual_kc = (std::min)(k2+kc,depth)-k2;\n\n        // OK, here we have selected one horizontal panel of rhs and one vertical panel of lhs.\n        // => Pack lhs's panel into a sequential chunk of memory (L2/L3 caching)\n        // Note that this panel will be read as many times as the number of blocks in the rhs's\n        // horizontal panel which is, in practice, a very low number.\n        pack_lhs(blockA, lhs.getSubMapper(i2,k2), actual_kc, actual_mc);\n\n        // For each kc x nc block of the rhs's horizontal panel...\n        for(Index j2=0; j2<cols; j2+=nc)\n        {\n          const Index actual_nc = (std::min)(j2+nc,cols)-j2;\n\n          // We pack the rhs's block into a sequential chunk of memory (L2 caching)\n          // Note that this block will be read a very high number of times, which is equal to the number of\n          // micro horizontal panel of the large rhs's panel (e.g., rows/12 times).\n          if((!pack_rhs_once) || i2==0)\n            pack_rhs(blockB, rhs.getSubMapper(k2,j2), actual_kc, actual_nc);\n\n          // Everything is packed, we can now call the panel * block kernel:\n          gebp(res.getSubMapper(i2, j2), blockA, blockB, actual_mc, actual_kc, actual_nc, alpha);\n        }\n      }\n    }\n  }\n}\n\n};\n\n/*********************************************************************************\n*  Specialization of generic_product_impl for \"large\" GEMM, i.e.,\n*  implementation of the high level wrapper to general_matrix_matrix_product\n**********************************************************************************/\n\ntemplate<typename Scalar, typename Index, typename Gemm, typename Lhs, typename Rhs, typename Dest, typename BlockingType>\nstruct gemm_functor\n{\n  gemm_functor(const Lhs& lhs, const Rhs& rhs, Dest& dest, const Scalar& actualAlpha, BlockingType& blocking)\n    : m_lhs(lhs), m_rhs(rhs), m_dest(dest), m_actualAlpha(actualAlpha), m_blocking(blocking)\n  {}\n\n  void initParallelSession(Index num_threads) const\n  {\n    m_blocking.initParallel(m_lhs.rows(), m_rhs.cols(), m_lhs.cols(), num_threads);\n    m_blocking.allocateA();\n  }\n\n  void operator() (Index row, Index rows, Index col=0, Index cols=-1, GemmParallelInfo<Index>* info=0) const\n  {\n    if(cols==-1)\n      cols = m_rhs.cols();\n\n    Gemm::run(rows, cols, m_lhs.cols(),\n              &m_lhs.coeffRef(row,0), m_lhs.outerStride(),\n              &m_rhs.coeffRef(0,col), m_rhs.outerStride(),\n              (Scalar*)&(m_dest.coeffRef(row,col)), m_dest.outerStride(),\n              m_actualAlpha, m_blocking, info);\n  }\n\n  typedef typename Gemm::Traits Traits;\n\n  protected:\n    const Lhs& m_lhs;\n    const Rhs& m_rhs;\n    Dest& m_dest;\n    Scalar m_actualAlpha;\n    BlockingType& m_blocking;\n};\n\ntemplate<int StorageOrder, typename LhsScalar, typename RhsScalar, int MaxRows, int MaxCols, int MaxDepth, int KcFactor=1,\nbool FiniteAtCompileTime = MaxRows!=Dynamic && MaxCols!=Dynamic && MaxDepth != Dynamic> class gemm_blocking_space;\n\ntemplate<typename _LhsScalar, typename _RhsScalar>\nclass level3_blocking\n{\n    typedef _LhsScalar LhsScalar;\n    typedef _RhsScalar RhsScalar;\n\n  protected:\n    LhsScalar* m_blockA;\n    RhsScalar* m_blockB;\n\n    Index m_mc;\n    Index m_nc;\n    Index m_kc;\n\n  public:\n\n    level3_blocking()\n      : m_blockA(0), m_blockB(0), m_mc(0), m_nc(0), m_kc(0)\n    {}\n\n    inline Index mc() const { return m_mc; }\n    inline Index nc() const { return m_nc; }\n    inline Index kc() const { return m_kc; }\n\n    inline LhsScalar* blockA() { return m_blockA; }\n    inline RhsScalar* blockB() { return m_blockB; }\n};\n\ntemplate<int StorageOrder, typename _LhsScalar, typename _RhsScalar, int MaxRows, int MaxCols, int MaxDepth, int KcFactor>\nclass gemm_blocking_space<StorageOrder,_LhsScalar,_RhsScalar,MaxRows, MaxCols, MaxDepth, KcFactor, true /* == FiniteAtCompileTime */>\n  : public level3_blocking<\n      typename conditional<StorageOrder==RowMajor,_RhsScalar,_LhsScalar>::type,\n      typename conditional<StorageOrder==RowMajor,_LhsScalar,_RhsScalar>::type>\n{\n    enum {\n      Transpose = StorageOrder==RowMajor,\n      ActualRows = Transpose ? MaxCols : MaxRows,\n      ActualCols = Transpose ? MaxRows : MaxCols\n    };\n    typedef typename conditional<Transpose,_RhsScalar,_LhsScalar>::type LhsScalar;\n    typedef typename conditional<Transpose,_LhsScalar,_RhsScalar>::type RhsScalar;\n    typedef gebp_traits<LhsScalar,RhsScalar> Traits;\n    enum {\n      SizeA = ActualRows * MaxDepth,\n      SizeB = ActualCols * MaxDepth\n    };\n\n#if EIGEN_MAX_STATIC_ALIGN_BYTES >= EIGEN_DEFAULT_ALIGN_BYTES\n    EIGEN_ALIGN_MAX LhsScalar m_staticA[SizeA];\n    EIGEN_ALIGN_MAX RhsScalar m_staticB[SizeB];\n#else\n    EIGEN_ALIGN_MAX char m_staticA[SizeA * sizeof(LhsScalar) + EIGEN_DEFAULT_ALIGN_BYTES-1];\n    EIGEN_ALIGN_MAX char m_staticB[SizeB * sizeof(RhsScalar) + EIGEN_DEFAULT_ALIGN_BYTES-1];\n#endif\n\n  public:\n\n    gemm_blocking_space(Index /*rows*/, Index /*cols*/, Index /*depth*/, Index /*num_threads*/, bool /*full_rows = false*/)\n    {\n      this->m_mc = ActualRows;\n      this->m_nc = ActualCols;\n      this->m_kc = MaxDepth;\n#if EIGEN_MAX_STATIC_ALIGN_BYTES >= EIGEN_DEFAULT_ALIGN_BYTES\n      this->m_blockA = m_staticA;\n      this->m_blockB = m_staticB;\n#else\n      this->m_blockA = reinterpret_cast<LhsScalar*>((internal::UIntPtr(m_staticA) + (EIGEN_DEFAULT_ALIGN_BYTES-1)) & ~std::size_t(EIGEN_DEFAULT_ALIGN_BYTES-1));\n      this->m_blockB = reinterpret_cast<RhsScalar*>((internal::UIntPtr(m_staticB) + (EIGEN_DEFAULT_ALIGN_BYTES-1)) & ~std::size_t(EIGEN_DEFAULT_ALIGN_BYTES-1));\n#endif\n    }\n\n    void initParallel(Index, Index, Index, Index)\n    {}\n\n    inline void allocateA() {}\n    inline void allocateB() {}\n    inline void allocateAll() {}\n};\n\ntemplate<int StorageOrder, typename _LhsScalar, typename _RhsScalar, int MaxRows, int MaxCols, int MaxDepth, int KcFactor>\nclass gemm_blocking_space<StorageOrder,_LhsScalar,_RhsScalar,MaxRows, MaxCols, MaxDepth, KcFactor, false>\n  : public level3_blocking<\n      typename conditional<StorageOrder==RowMajor,_RhsScalar,_LhsScalar>::type,\n      typename conditional<StorageOrder==RowMajor,_LhsScalar,_RhsScalar>::type>\n{\n    enum {\n      Transpose = StorageOrder==RowMajor\n    };\n    typedef typename conditional<Transpose,_RhsScalar,_LhsScalar>::type LhsScalar;\n    typedef typename conditional<Transpose,_LhsScalar,_RhsScalar>::type RhsScalar;\n    typedef gebp_traits<LhsScalar,RhsScalar> Traits;\n\n    Index m_sizeA;\n    Index m_sizeB;\n\n  public:\n\n    gemm_blocking_space(Index rows, Index cols, Index depth, Index num_threads, bool l3_blocking)\n    {\n      this->m_mc = Transpose ? cols : rows;\n      this->m_nc = Transpose ? rows : cols;\n      this->m_kc = depth;\n\n      if(l3_blocking)\n      {\n        computeProductBlockingSizes<LhsScalar,RhsScalar,KcFactor>(this->m_kc, this->m_mc, this->m_nc, num_threads);\n      }\n      else  // no l3 blocking\n      {\n        Index n = this->m_nc;\n        computeProductBlockingSizes<LhsScalar,RhsScalar,KcFactor>(this->m_kc, this->m_mc, n, num_threads);\n      }\n\n      m_sizeA = this->m_mc * this->m_kc;\n      m_sizeB = this->m_kc * this->m_nc;\n    }\n\n    void initParallel(Index rows, Index cols, Index depth, Index num_threads)\n    {\n      this->m_mc = Transpose ? cols : rows;\n      this->m_nc = Transpose ? rows : cols;\n      this->m_kc = depth;\n\n      eigen_internal_assert(this->m_blockA==0 && this->m_blockB==0);\n      Index m = this->m_mc;\n      computeProductBlockingSizes<LhsScalar,RhsScalar,KcFactor>(this->m_kc, m, this->m_nc, num_threads);\n      m_sizeA = this->m_mc * this->m_kc;\n      m_sizeB = this->m_kc * this->m_nc;\n    }\n\n    void allocateA()\n    {\n      if(this->m_blockA==0)\n        this->m_blockA = aligned_new<LhsScalar>(m_sizeA);\n    }\n\n    void allocateB()\n    {\n      if(this->m_blockB==0)\n        this->m_blockB = aligned_new<RhsScalar>(m_sizeB);\n    }\n\n    void allocateAll()\n    {\n      allocateA();\n      allocateB();\n    }\n\n    ~gemm_blocking_space()\n    {\n      aligned_delete(this->m_blockA, m_sizeA);\n      aligned_delete(this->m_blockB, m_sizeB);\n    }\n};\n\n} // end namespace internal\n\nnamespace internal {\n\ntemplate<typename Lhs, typename Rhs>\nstruct generic_product_impl<Lhs,Rhs,DenseShape,DenseShape,GemmProduct>\n  : generic_product_impl_base<Lhs,Rhs,generic_product_impl<Lhs,Rhs,DenseShape,DenseShape,GemmProduct> >\n{\n  typedef typename Product<Lhs,Rhs>::Scalar Scalar;\n  typedef typename Lhs::Scalar LhsScalar;\n  typedef typename Rhs::Scalar RhsScalar;\n\n  typedef internal::blas_traits<Lhs> LhsBlasTraits;\n  typedef typename LhsBlasTraits::DirectLinearAccessType ActualLhsType;\n  typedef typename internal::remove_all<ActualLhsType>::type ActualLhsTypeCleaned;\n\n  typedef internal::blas_traits<Rhs> RhsBlasTraits;\n  typedef typename RhsBlasTraits::DirectLinearAccessType ActualRhsType;\n  typedef typename internal::remove_all<ActualRhsType>::type ActualRhsTypeCleaned;\n\n  enum {\n    MaxDepthAtCompileTime = EIGEN_SIZE_MIN_PREFER_FIXED(Lhs::MaxColsAtCompileTime,Rhs::MaxRowsAtCompileTime)\n  };\n\n  typedef generic_product_impl<Lhs,Rhs,DenseShape,DenseShape,CoeffBasedProductMode> lazyproduct;\n\n  template<typename Dst>\n  static void evalTo(Dst& dst, const Lhs& lhs, const Rhs& rhs)\n  {\n    if((rhs.rows()+dst.rows()+dst.cols())<20 && rhs.rows()>0)\n      lazyproduct::evalTo(dst, lhs, rhs);\n    else\n    {\n      dst.setZero();\n      scaleAndAddTo(dst, lhs, rhs, Scalar(1));\n    }\n  }\n\n  template<typename Dst>\n  static void addTo(Dst& dst, const Lhs& lhs, const Rhs& rhs)\n  {\n    if((rhs.rows()+dst.rows()+dst.cols())<20 && rhs.rows()>0)\n      lazyproduct::addTo(dst, lhs, rhs);\n    else\n      scaleAndAddTo(dst,lhs, rhs, Scalar(1));\n  }\n\n  template<typename Dst>\n  static void subTo(Dst& dst, const Lhs& lhs, const Rhs& rhs)\n  {\n    if((rhs.rows()+dst.rows()+dst.cols())<20 && rhs.rows()>0)\n      lazyproduct::subTo(dst, lhs, rhs);\n    else\n      scaleAndAddTo(dst, lhs, rhs, Scalar(-1));\n  }\n\n  template<typename Dest>\n  static void scaleAndAddTo(Dest& dst, const Lhs& a_lhs, const Rhs& a_rhs, const Scalar& alpha)\n  {\n    eigen_assert(dst.rows()==a_lhs.rows() && dst.cols()==a_rhs.cols());\n    if(a_lhs.cols()==0 || a_lhs.rows()==0 || a_rhs.cols()==0)\n      return;\n\n    typename internal::add_const_on_value_type<ActualLhsType>::type lhs = LhsBlasTraits::extract(a_lhs);\n    typename internal::add_const_on_value_type<ActualRhsType>::type rhs = RhsBlasTraits::extract(a_rhs);\n\n    Scalar actualAlpha = alpha * LhsBlasTraits::extractScalarFactor(a_lhs)\n                               * RhsBlasTraits::extractScalarFactor(a_rhs);\n\n    typedef internal::gemm_blocking_space<(Dest::Flags&RowMajorBit) ? RowMajor : ColMajor,LhsScalar,RhsScalar,\n            Dest::MaxRowsAtCompileTime,Dest::MaxColsAtCompileTime,MaxDepthAtCompileTime> BlockingType;\n\n    typedef internal::gemm_functor<\n      Scalar, Index,\n      internal::general_matrix_matrix_product<\n        Index,\n        LhsScalar, (ActualLhsTypeCleaned::Flags&RowMajorBit) ? RowMajor : ColMajor, bool(LhsBlasTraits::NeedToConjugate),\n        RhsScalar, (ActualRhsTypeCleaned::Flags&RowMajorBit) ? RowMajor : ColMajor, bool(RhsBlasTraits::NeedToConjugate),\n        (Dest::Flags&RowMajorBit) ? RowMajor : ColMajor>,\n      ActualLhsTypeCleaned, ActualRhsTypeCleaned, Dest, BlockingType> GemmFunctor;\n\n    BlockingType blocking(dst.rows(), dst.cols(), lhs.cols(), 1, true);\n    internal::parallelize_gemm<(Dest::MaxRowsAtCompileTime>32 || Dest::MaxRowsAtCompileTime==Dynamic)>\n        (GemmFunctor(lhs, rhs, dst, actualAlpha, blocking), a_lhs.rows(), a_rhs.cols(), a_lhs.cols(), Dest::Flags&RowMajorBit);\n  }\n};\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_GENERAL_MATRIX_MATRIX_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/products/GeneralMatrixMatrixTriangular.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009-2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_GENERAL_MATRIX_MATRIX_TRIANGULAR_H\n#define EIGEN_GENERAL_MATRIX_MATRIX_TRIANGULAR_H\n\nnamespace Eigen { \n\ntemplate<typename Scalar, typename Index, int StorageOrder, int UpLo, bool ConjLhs, bool ConjRhs>\nstruct selfadjoint_rank1_update;\n\nnamespace internal {\n\n/**********************************************************************\n* This file implements a general A * B product while\n* evaluating only one triangular part of the product.\n* This is a more general version of self adjoint product (C += A A^T)\n* as the level 3 SYRK Blas routine.\n**********************************************************************/\n\n// forward declarations (defined at the end of this file)\ntemplate<typename LhsScalar, typename RhsScalar, typename Index, int mr, int nr, bool ConjLhs, bool ConjRhs, int UpLo>\nstruct tribb_kernel;\n  \n/* Optimized matrix-matrix product evaluating only one triangular half */\ntemplate <typename Index,\n          typename LhsScalar, int LhsStorageOrder, bool ConjugateLhs,\n          typename RhsScalar, int RhsStorageOrder, bool ConjugateRhs,\n                              int ResStorageOrder, int  UpLo, int Version = Specialized>\nstruct general_matrix_matrix_triangular_product;\n\n// as usual if the result is row major => we transpose the product\ntemplate <typename Index, typename LhsScalar, int LhsStorageOrder, bool ConjugateLhs,\n                          typename RhsScalar, int RhsStorageOrder, bool ConjugateRhs, int  UpLo, int Version>\nstruct general_matrix_matrix_triangular_product<Index,LhsScalar,LhsStorageOrder,ConjugateLhs,RhsScalar,RhsStorageOrder,ConjugateRhs,RowMajor,UpLo,Version>\n{\n  typedef typename ScalarBinaryOpTraits<LhsScalar, RhsScalar>::ReturnType ResScalar;\n  static EIGEN_STRONG_INLINE void run(Index size, Index depth,const LhsScalar* lhs, Index lhsStride,\n                                      const RhsScalar* rhs, Index rhsStride, ResScalar* res, Index resStride,\n                                      const ResScalar& alpha, level3_blocking<RhsScalar,LhsScalar>& blocking)\n  {\n    general_matrix_matrix_triangular_product<Index,\n        RhsScalar, RhsStorageOrder==RowMajor ? ColMajor : RowMajor, ConjugateRhs,\n        LhsScalar, LhsStorageOrder==RowMajor ? ColMajor : RowMajor, ConjugateLhs,\n        ColMajor, UpLo==Lower?Upper:Lower>\n      ::run(size,depth,rhs,rhsStride,lhs,lhsStride,res,resStride,alpha,blocking);\n  }\n};\n\ntemplate <typename Index, typename LhsScalar, int LhsStorageOrder, bool ConjugateLhs,\n                          typename RhsScalar, int RhsStorageOrder, bool ConjugateRhs, int  UpLo, int Version>\nstruct general_matrix_matrix_triangular_product<Index,LhsScalar,LhsStorageOrder,ConjugateLhs,RhsScalar,RhsStorageOrder,ConjugateRhs,ColMajor,UpLo,Version>\n{\n  typedef typename ScalarBinaryOpTraits<LhsScalar, RhsScalar>::ReturnType ResScalar;\n  static EIGEN_STRONG_INLINE void run(Index size, Index depth,const LhsScalar* _lhs, Index lhsStride,\n                                      const RhsScalar* _rhs, Index rhsStride, ResScalar* _res, Index resStride,\n                                      const ResScalar& alpha, level3_blocking<LhsScalar,RhsScalar>& blocking)\n  {\n    typedef gebp_traits<LhsScalar,RhsScalar> Traits;\n\n    typedef const_blas_data_mapper<LhsScalar, Index, LhsStorageOrder> LhsMapper;\n    typedef const_blas_data_mapper<RhsScalar, Index, RhsStorageOrder> RhsMapper;\n    typedef blas_data_mapper<typename Traits::ResScalar, Index, ColMajor> ResMapper;\n    LhsMapper lhs(_lhs,lhsStride);\n    RhsMapper rhs(_rhs,rhsStride);\n    ResMapper res(_res, resStride);\n\n    Index kc = blocking.kc();\n    Index mc = (std::min)(size,blocking.mc());\n\n    // !!! mc must be a multiple of nr:\n    if(mc > Traits::nr)\n      mc = (mc/Traits::nr)*Traits::nr;\n\n    std::size_t sizeA = kc*mc;\n    std::size_t sizeB = kc*size;\n\n    ei_declare_aligned_stack_constructed_variable(LhsScalar, blockA, sizeA, blocking.blockA());\n    ei_declare_aligned_stack_constructed_variable(RhsScalar, blockB, sizeB, blocking.blockB());\n\n    gemm_pack_lhs<LhsScalar, Index, LhsMapper, Traits::mr, Traits::LhsProgress, LhsStorageOrder> pack_lhs;\n    gemm_pack_rhs<RhsScalar, Index, RhsMapper, Traits::nr, RhsStorageOrder> pack_rhs;\n    gebp_kernel<LhsScalar, RhsScalar, Index, ResMapper, Traits::mr, Traits::nr, ConjugateLhs, ConjugateRhs> gebp;\n    tribb_kernel<LhsScalar, RhsScalar, Index, Traits::mr, Traits::nr, ConjugateLhs, ConjugateRhs, UpLo> sybb;\n\n    for(Index k2=0; k2<depth; k2+=kc)\n    {\n      const Index actual_kc = (std::min)(k2+kc,depth)-k2;\n\n      // note that the actual rhs is the transpose/adjoint of mat\n      pack_rhs(blockB, rhs.getSubMapper(k2,0), actual_kc, size);\n\n      for(Index i2=0; i2<size; i2+=mc)\n      {\n        const Index actual_mc = (std::min)(i2+mc,size)-i2;\n\n        pack_lhs(blockA, lhs.getSubMapper(i2, k2), actual_kc, actual_mc);\n\n        // the selected actual_mc * size panel of res is split into three different part:\n        //  1 - before the diagonal => processed with gebp or skipped\n        //  2 - the actual_mc x actual_mc symmetric block => processed with a special kernel\n        //  3 - after the diagonal => processed with gebp or skipped\n        if (UpLo==Lower)\n          gebp(res.getSubMapper(i2, 0), blockA, blockB, actual_mc, actual_kc,\n               (std::min)(size,i2), alpha, -1, -1, 0, 0);\n\n\n        sybb(_res+resStride*i2 + i2, resStride, blockA, blockB + actual_kc*i2, actual_mc, actual_kc, alpha);\n\n        if (UpLo==Upper)\n        {\n          Index j2 = i2+actual_mc;\n          gebp(res.getSubMapper(i2, j2), blockA, blockB+actual_kc*j2, actual_mc,\n               actual_kc, (std::max)(Index(0), size-j2), alpha, -1, -1, 0, 0);\n        }\n      }\n    }\n  }\n};\n\n// Optimized packed Block * packed Block product kernel evaluating only one given triangular part\n// This kernel is built on top of the gebp kernel:\n// - the current destination block is processed per panel of actual_mc x BlockSize\n//   where BlockSize is set to the minimal value allowing gebp to be as fast as possible\n// - then, as usual, each panel is split into three parts along the diagonal,\n//   the sub blocks above and below the diagonal are processed as usual,\n//   while the triangular block overlapping the diagonal is evaluated into a\n//   small temporary buffer which is then accumulated into the result using a\n//   triangular traversal.\ntemplate<typename LhsScalar, typename RhsScalar, typename Index, int mr, int nr, bool ConjLhs, bool ConjRhs, int UpLo>\nstruct tribb_kernel\n{\n  typedef gebp_traits<LhsScalar,RhsScalar,ConjLhs,ConjRhs> Traits;\n  typedef typename Traits::ResScalar ResScalar;\n\n  enum {\n    BlockSize  = meta_least_common_multiple<EIGEN_PLAIN_ENUM_MAX(mr,nr),EIGEN_PLAIN_ENUM_MIN(mr,nr)>::ret\n  };\n  void operator()(ResScalar* _res, Index resStride, const LhsScalar* blockA, const RhsScalar* blockB, Index size, Index depth, const ResScalar& alpha)\n  {\n    typedef blas_data_mapper<ResScalar, Index, ColMajor> ResMapper;\n    ResMapper res(_res, resStride);\n    gebp_kernel<LhsScalar, RhsScalar, Index, ResMapper, mr, nr, ConjLhs, ConjRhs> gebp_kernel;\n\n    Matrix<ResScalar,BlockSize,BlockSize,ColMajor> buffer;\n\n    // let's process the block per panel of actual_mc x BlockSize,\n    // again, each is split into three parts, etc.\n    for (Index j=0; j<size; j+=BlockSize)\n    {\n      Index actualBlockSize = std::min<Index>(BlockSize,size - j);\n      const RhsScalar* actual_b = blockB+j*depth;\n\n      if(UpLo==Upper)\n        gebp_kernel(res.getSubMapper(0, j), blockA, actual_b, j, depth, actualBlockSize, alpha,\n                    -1, -1, 0, 0);\n\n      // selfadjoint micro block\n      {\n        Index i = j;\n        buffer.setZero();\n        // 1 - apply the kernel on the temporary buffer\n        gebp_kernel(ResMapper(buffer.data(), BlockSize), blockA+depth*i, actual_b, actualBlockSize, depth, actualBlockSize, alpha,\n                    -1, -1, 0, 0);\n        // 2 - triangular accumulation\n        for(Index j1=0; j1<actualBlockSize; ++j1)\n        {\n          ResScalar* r = &res(i, j + j1);\n          for(Index i1=UpLo==Lower ? j1 : 0;\n              UpLo==Lower ? i1<actualBlockSize : i1<=j1; ++i1)\n            r[i1] += buffer(i1,j1);\n        }\n      }\n\n      if(UpLo==Lower)\n      {\n        Index i = j+actualBlockSize;\n        gebp_kernel(res.getSubMapper(i, j), blockA+depth*i, actual_b, size-i, \n                    depth, actualBlockSize, alpha, -1, -1, 0, 0);\n      }\n    }\n  }\n};\n\n} // end namespace internal\n\n// high level API\n\ntemplate<typename MatrixType, typename ProductType, int UpLo, bool IsOuterProduct>\nstruct general_product_to_triangular_selector;\n\n\ntemplate<typename MatrixType, typename ProductType, int UpLo>\nstruct general_product_to_triangular_selector<MatrixType,ProductType,UpLo,true>\n{\n  static void run(MatrixType& mat, const ProductType& prod, const typename MatrixType::Scalar& alpha)\n  {\n    typedef typename MatrixType::Scalar Scalar;\n    \n    typedef typename internal::remove_all<typename ProductType::LhsNested>::type Lhs;\n    typedef internal::blas_traits<Lhs> LhsBlasTraits;\n    typedef typename LhsBlasTraits::DirectLinearAccessType ActualLhs;\n    typedef typename internal::remove_all<ActualLhs>::type _ActualLhs;\n    typename internal::add_const_on_value_type<ActualLhs>::type actualLhs = LhsBlasTraits::extract(prod.lhs());\n    \n    typedef typename internal::remove_all<typename ProductType::RhsNested>::type Rhs;\n    typedef internal::blas_traits<Rhs> RhsBlasTraits;\n    typedef typename RhsBlasTraits::DirectLinearAccessType ActualRhs;\n    typedef typename internal::remove_all<ActualRhs>::type _ActualRhs;\n    typename internal::add_const_on_value_type<ActualRhs>::type actualRhs = RhsBlasTraits::extract(prod.rhs());\n\n    Scalar actualAlpha = alpha * LhsBlasTraits::extractScalarFactor(prod.lhs().derived()) * RhsBlasTraits::extractScalarFactor(prod.rhs().derived());\n\n    enum {\n      StorageOrder = (internal::traits<MatrixType>::Flags&RowMajorBit) ? RowMajor : ColMajor,\n      UseLhsDirectly = _ActualLhs::InnerStrideAtCompileTime==1,\n      UseRhsDirectly = _ActualRhs::InnerStrideAtCompileTime==1\n    };\n    \n    internal::gemv_static_vector_if<Scalar,Lhs::SizeAtCompileTime,Lhs::MaxSizeAtCompileTime,!UseLhsDirectly> static_lhs;\n    ei_declare_aligned_stack_constructed_variable(Scalar, actualLhsPtr, actualLhs.size(),\n      (UseLhsDirectly ? const_cast<Scalar*>(actualLhs.data()) : static_lhs.data()));\n    if(!UseLhsDirectly) Map<typename _ActualLhs::PlainObject>(actualLhsPtr, actualLhs.size()) = actualLhs;\n    \n    internal::gemv_static_vector_if<Scalar,Rhs::SizeAtCompileTime,Rhs::MaxSizeAtCompileTime,!UseRhsDirectly> static_rhs;\n    ei_declare_aligned_stack_constructed_variable(Scalar, actualRhsPtr, actualRhs.size(),\n      (UseRhsDirectly ? const_cast<Scalar*>(actualRhs.data()) : static_rhs.data()));\n    if(!UseRhsDirectly) Map<typename _ActualRhs::PlainObject>(actualRhsPtr, actualRhs.size()) = actualRhs;\n    \n    \n    selfadjoint_rank1_update<Scalar,Index,StorageOrder,UpLo,\n                              LhsBlasTraits::NeedToConjugate && NumTraits<Scalar>::IsComplex,\n                              RhsBlasTraits::NeedToConjugate && NumTraits<Scalar>::IsComplex>\n          ::run(actualLhs.size(), mat.data(), mat.outerStride(), actualLhsPtr, actualRhsPtr, actualAlpha);\n  }\n};\n\ntemplate<typename MatrixType, typename ProductType, int UpLo>\nstruct general_product_to_triangular_selector<MatrixType,ProductType,UpLo,false>\n{\n  static void run(MatrixType& mat, const ProductType& prod, const typename MatrixType::Scalar& alpha)\n  {\n    typedef typename internal::remove_all<typename ProductType::LhsNested>::type Lhs;\n    typedef internal::blas_traits<Lhs> LhsBlasTraits;\n    typedef typename LhsBlasTraits::DirectLinearAccessType ActualLhs;\n    typedef typename internal::remove_all<ActualLhs>::type _ActualLhs;\n    typename internal::add_const_on_value_type<ActualLhs>::type actualLhs = LhsBlasTraits::extract(prod.lhs());\n    \n    typedef typename internal::remove_all<typename ProductType::RhsNested>::type Rhs;\n    typedef internal::blas_traits<Rhs> RhsBlasTraits;\n    typedef typename RhsBlasTraits::DirectLinearAccessType ActualRhs;\n    typedef typename internal::remove_all<ActualRhs>::type _ActualRhs;\n    typename internal::add_const_on_value_type<ActualRhs>::type actualRhs = RhsBlasTraits::extract(prod.rhs());\n\n    typename ProductType::Scalar actualAlpha = alpha * LhsBlasTraits::extractScalarFactor(prod.lhs().derived()) * RhsBlasTraits::extractScalarFactor(prod.rhs().derived());\n\n    enum {\n      IsRowMajor = (internal::traits<MatrixType>::Flags&RowMajorBit) ? 1 : 0,\n      LhsIsRowMajor = _ActualLhs::Flags&RowMajorBit ? 1 : 0,\n      RhsIsRowMajor = _ActualRhs::Flags&RowMajorBit ? 1 : 0\n    };\n\n    Index size = mat.cols();\n    Index depth = actualLhs.cols();\n\n    typedef internal::gemm_blocking_space<IsRowMajor ? RowMajor : ColMajor,typename Lhs::Scalar,typename Rhs::Scalar,\n          MatrixType::MaxColsAtCompileTime, MatrixType::MaxColsAtCompileTime, _ActualRhs::MaxColsAtCompileTime> BlockingType;\n\n    BlockingType blocking(size, size, depth, 1, false);\n\n    internal::general_matrix_matrix_triangular_product<Index,\n      typename Lhs::Scalar, LhsIsRowMajor ? RowMajor : ColMajor, LhsBlasTraits::NeedToConjugate,\n      typename Rhs::Scalar, RhsIsRowMajor ? RowMajor : ColMajor, RhsBlasTraits::NeedToConjugate,\n      IsRowMajor ? RowMajor : ColMajor, UpLo>\n      ::run(size, depth,\n            &actualLhs.coeffRef(0,0), actualLhs.outerStride(), &actualRhs.coeffRef(0,0), actualRhs.outerStride(),\n            mat.data(), mat.outerStride(), actualAlpha, blocking);\n  }\n};\n\ntemplate<typename MatrixType, unsigned int UpLo>\ntemplate<typename ProductType>\nTriangularView<MatrixType,UpLo>& TriangularViewImpl<MatrixType,UpLo,Dense>::_assignProduct(const ProductType& prod, const Scalar& alpha)\n{\n  eigen_assert(derived().nestedExpression().rows() == prod.rows() && derived().cols() == prod.cols());\n  \n  general_product_to_triangular_selector<MatrixType, ProductType, UpLo, internal::traits<ProductType>::InnerSize==1>::run(derived().nestedExpression().const_cast_derived(), prod, alpha);\n  \n  return derived();\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_GENERAL_MATRIX_MATRIX_TRIANGULAR_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/products/GeneralMatrixMatrixTriangular_BLAS.h",
    "content": "/*\n Copyright (c) 2011, Intel Corporation. All rights reserved.\n\n Redistribution and use in source and binary forms, with or without modification,\n are permitted provided that the following conditions are met:\n\n * Redistributions of source code must retain the above copyright notice, this\n   list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright notice,\n   this list of conditions and the following disclaimer in the documentation\n   and/or other materials provided with the distribution.\n * Neither the name of Intel Corporation nor the names of its contributors may\n   be used to endorse or promote products derived from this software without\n   specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n ********************************************************************************\n *   Content : Eigen bindings to BLAS F77\n *   Level 3 BLAS SYRK/HERK implementation.\n ********************************************************************************\n*/\n\n#ifndef EIGEN_GENERAL_MATRIX_MATRIX_TRIANGULAR_BLAS_H\n#define EIGEN_GENERAL_MATRIX_MATRIX_TRIANGULAR_BLAS_H\n\nnamespace Eigen { \n\nnamespace internal {\n\ntemplate <typename Index, typename Scalar, int AStorageOrder, bool ConjugateA, int ResStorageOrder, int  UpLo>\nstruct general_matrix_matrix_rankupdate :\n       general_matrix_matrix_triangular_product<\n         Index,Scalar,AStorageOrder,ConjugateA,Scalar,AStorageOrder,ConjugateA,ResStorageOrder,UpLo,BuiltIn> {};\n\n\n// try to go to BLAS specialization\n#define EIGEN_BLAS_RANKUPDATE_SPECIALIZE(Scalar) \\\ntemplate <typename Index, int LhsStorageOrder, bool ConjugateLhs, \\\n                          int RhsStorageOrder, bool ConjugateRhs, int  UpLo> \\\nstruct general_matrix_matrix_triangular_product<Index,Scalar,LhsStorageOrder,ConjugateLhs, \\\n               Scalar,RhsStorageOrder,ConjugateRhs,ColMajor,UpLo,Specialized> { \\\n  static EIGEN_STRONG_INLINE void run(Index size, Index depth,const Scalar* lhs, Index lhsStride, \\\n                          const Scalar* rhs, Index rhsStride, Scalar* res, Index resStride, Scalar alpha, level3_blocking<Scalar, Scalar>& blocking) \\\n  { \\\n    if (lhs==rhs) { \\\n      general_matrix_matrix_rankupdate<Index,Scalar,LhsStorageOrder,ConjugateLhs,ColMajor,UpLo> \\\n      ::run(size,depth,lhs,lhsStride,rhs,rhsStride,res,resStride,alpha,blocking); \\\n    } else { \\\n      general_matrix_matrix_triangular_product<Index, \\\n        Scalar, LhsStorageOrder, ConjugateLhs, \\\n        Scalar, RhsStorageOrder, ConjugateRhs, \\\n        ColMajor, UpLo, BuiltIn> \\\n      ::run(size,depth,lhs,lhsStride,rhs,rhsStride,res,resStride,alpha,blocking); \\\n    } \\\n  } \\\n};\n\nEIGEN_BLAS_RANKUPDATE_SPECIALIZE(double)\nEIGEN_BLAS_RANKUPDATE_SPECIALIZE(float)\n// TODO handle complex cases\n// EIGEN_BLAS_RANKUPDATE_SPECIALIZE(dcomplex)\n// EIGEN_BLAS_RANKUPDATE_SPECIALIZE(scomplex)\n\n// SYRK for float/double\n#define EIGEN_BLAS_RANKUPDATE_R(EIGTYPE, BLASTYPE, BLASFUNC) \\\ntemplate <typename Index, int AStorageOrder, bool ConjugateA, int  UpLo> \\\nstruct general_matrix_matrix_rankupdate<Index,EIGTYPE,AStorageOrder,ConjugateA,ColMajor,UpLo> { \\\n  enum { \\\n    IsLower = (UpLo&Lower) == Lower, \\\n    LowUp = IsLower ? Lower : Upper, \\\n    conjA = ((AStorageOrder==ColMajor) && ConjugateA) ? 1 : 0 \\\n  }; \\\n  static EIGEN_STRONG_INLINE void run(Index size, Index depth,const EIGTYPE* lhs, Index lhsStride, \\\n                          const EIGTYPE* /*rhs*/, Index /*rhsStride*/, EIGTYPE* res, Index resStride, EIGTYPE alpha, level3_blocking<EIGTYPE, EIGTYPE>& /*blocking*/) \\\n  { \\\n  /* typedef Matrix<EIGTYPE, Dynamic, Dynamic, RhsStorageOrder> MatrixRhs;*/ \\\n\\\n   BlasIndex lda=convert_index<BlasIndex>(lhsStride), ldc=convert_index<BlasIndex>(resStride), n=convert_index<BlasIndex>(size), k=convert_index<BlasIndex>(depth); \\\n   char uplo=(IsLower) ? 'L' : 'U', trans=(AStorageOrder==RowMajor) ? 'T':'N'; \\\n   EIGTYPE beta; \\\n   BLASFUNC(&uplo, &trans, &n, &k, &numext::real_ref(alpha), lhs, &lda, &numext::real_ref(beta), res, &ldc); \\\n  } \\\n};\n\n// HERK for complex data\n#define EIGEN_BLAS_RANKUPDATE_C(EIGTYPE, BLASTYPE, RTYPE, BLASFUNC) \\\ntemplate <typename Index, int AStorageOrder, bool ConjugateA, int  UpLo> \\\nstruct general_matrix_matrix_rankupdate<Index,EIGTYPE,AStorageOrder,ConjugateA,ColMajor,UpLo> { \\\n  enum { \\\n    IsLower = (UpLo&Lower) == Lower, \\\n    LowUp = IsLower ? Lower : Upper, \\\n    conjA = (((AStorageOrder==ColMajor) && ConjugateA) || ((AStorageOrder==RowMajor) && !ConjugateA)) ? 1 : 0 \\\n  }; \\\n  static EIGEN_STRONG_INLINE void run(Index size, Index depth,const EIGTYPE* lhs, Index lhsStride, \\\n                          const EIGTYPE* /*rhs*/, Index /*rhsStride*/, EIGTYPE* res, Index resStride, EIGTYPE alpha, level3_blocking<EIGTYPE, EIGTYPE>& /*blocking*/) \\\n  { \\\n   typedef Matrix<EIGTYPE, Dynamic, Dynamic, AStorageOrder> MatrixType; \\\n\\\n   BlasIndex lda=convert_index<BlasIndex>(lhsStride), ldc=convert_index<BlasIndex>(resStride), n=convert_index<BlasIndex>(size), k=convert_index<BlasIndex>(depth); \\\n   char uplo=(IsLower) ? 'L' : 'U', trans=(AStorageOrder==RowMajor) ? 'C':'N'; \\\n   RTYPE alpha_, beta_; \\\n   const EIGTYPE* a_ptr; \\\n\\\n   alpha_ = alpha.real(); \\\n   beta_ = 1.0; \\\n/* Copy with conjugation in some cases*/ \\\n   MatrixType a; \\\n   if (conjA) { \\\n     Map<const MatrixType, 0, OuterStride<> > mapA(lhs,n,k,OuterStride<>(lhsStride)); \\\n     a = mapA.conjugate(); \\\n     lda = a.outerStride(); \\\n     a_ptr = a.data(); \\\n   } else a_ptr=lhs; \\\n   BLASFUNC(&uplo, &trans, &n, &k, &alpha_, (BLASTYPE*)a_ptr, &lda, &beta_, (BLASTYPE*)res, &ldc); \\\n  } \\\n};\n\n\nEIGEN_BLAS_RANKUPDATE_R(double, double, dsyrk_)\nEIGEN_BLAS_RANKUPDATE_R(float,  float,  ssyrk_)\n\n// TODO hanlde complex cases\n// EIGEN_BLAS_RANKUPDATE_C(dcomplex, double, double, zherk_)\n// EIGEN_BLAS_RANKUPDATE_C(scomplex, float,  float, cherk_)\n\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_GENERAL_MATRIX_MATRIX_TRIANGULAR_BLAS_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/products/GeneralMatrixMatrix_BLAS.h",
    "content": "/*\n Copyright (c) 2011, Intel Corporation. All rights reserved.\n\n Redistribution and use in source and binary forms, with or without modification,\n are permitted provided that the following conditions are met:\n\n * Redistributions of source code must retain the above copyright notice, this\n   list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright notice,\n   this list of conditions and the following disclaimer in the documentation\n   and/or other materials provided with the distribution.\n * Neither the name of Intel Corporation nor the names of its contributors may\n   be used to endorse or promote products derived from this software without\n   specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n ********************************************************************************\n *   Content : Eigen bindings to BLAS F77\n *   General matrix-matrix product functionality based on ?GEMM.\n ********************************************************************************\n*/\n\n#ifndef EIGEN_GENERAL_MATRIX_MATRIX_BLAS_H\n#define EIGEN_GENERAL_MATRIX_MATRIX_BLAS_H\n\nnamespace Eigen { \n\nnamespace internal {\n\n/**********************************************************************\n* This file implements general matrix-matrix multiplication using BLAS\n* gemm function via partial specialization of\n* general_matrix_matrix_product::run(..) method for float, double,\n* std::complex<float> and std::complex<double> types\n**********************************************************************/\n\n// gemm specialization\n\n#define GEMM_SPECIALIZATION(EIGTYPE, EIGPREFIX, BLASTYPE, BLASPREFIX) \\\ntemplate< \\\n  typename Index, \\\n  int LhsStorageOrder, bool ConjugateLhs, \\\n  int RhsStorageOrder, bool ConjugateRhs> \\\nstruct general_matrix_matrix_product<Index,EIGTYPE,LhsStorageOrder,ConjugateLhs,EIGTYPE,RhsStorageOrder,ConjugateRhs,ColMajor> \\\n{ \\\ntypedef gebp_traits<EIGTYPE,EIGTYPE> Traits; \\\n\\\nstatic void run(Index rows, Index cols, Index depth, \\\n  const EIGTYPE* _lhs, Index lhsStride, \\\n  const EIGTYPE* _rhs, Index rhsStride, \\\n  EIGTYPE* res, Index resStride, \\\n  EIGTYPE alpha, \\\n  level3_blocking<EIGTYPE, EIGTYPE>& /*blocking*/, \\\n  GemmParallelInfo<Index>* /*info = 0*/) \\\n{ \\\n  using std::conj; \\\n\\\n  char transa, transb; \\\n  BlasIndex m, n, k, lda, ldb, ldc; \\\n  const EIGTYPE *a, *b; \\\n  EIGTYPE beta(1); \\\n  MatrixX##EIGPREFIX a_tmp, b_tmp; \\\n\\\n/* Set transpose options */ \\\n  transa = (LhsStorageOrder==RowMajor) ? ((ConjugateLhs) ? 'C' : 'T') : 'N'; \\\n  transb = (RhsStorageOrder==RowMajor) ? ((ConjugateRhs) ? 'C' : 'T') : 'N'; \\\n\\\n/* Set m, n, k */ \\\n  m = convert_index<BlasIndex>(rows);  \\\n  n = convert_index<BlasIndex>(cols);  \\\n  k = convert_index<BlasIndex>(depth); \\\n\\\n/* Set lda, ldb, ldc */ \\\n  lda = convert_index<BlasIndex>(lhsStride); \\\n  ldb = convert_index<BlasIndex>(rhsStride); \\\n  ldc = convert_index<BlasIndex>(resStride); \\\n\\\n/* Set a, b, c */ \\\n  if ((LhsStorageOrder==ColMajor) && (ConjugateLhs)) { \\\n    Map<const MatrixX##EIGPREFIX, 0, OuterStride<> > lhs(_lhs,m,k,OuterStride<>(lhsStride)); \\\n    a_tmp = lhs.conjugate(); \\\n    a = a_tmp.data(); \\\n    lda = convert_index<BlasIndex>(a_tmp.outerStride()); \\\n  } else a = _lhs; \\\n\\\n  if ((RhsStorageOrder==ColMajor) && (ConjugateRhs)) { \\\n    Map<const MatrixX##EIGPREFIX, 0, OuterStride<> > rhs(_rhs,k,n,OuterStride<>(rhsStride)); \\\n    b_tmp = rhs.conjugate(); \\\n    b = b_tmp.data(); \\\n    ldb = convert_index<BlasIndex>(b_tmp.outerStride()); \\\n  } else b = _rhs; \\\n\\\n  BLASPREFIX##gemm_(&transa, &transb, &m, &n, &k, &numext::real_ref(alpha), (const BLASTYPE*)a, &lda, (const BLASTYPE*)b, &ldb, &numext::real_ref(beta), (BLASTYPE*)res, &ldc); \\\n}};\n\nGEMM_SPECIALIZATION(double,   d,  double, d)\nGEMM_SPECIALIZATION(float,    f,  float,  s)\nGEMM_SPECIALIZATION(dcomplex, cd, double, z)\nGEMM_SPECIALIZATION(scomplex, cf, float,  c)\n\n} // end namespase internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_GENERAL_MATRIX_MATRIX_BLAS_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/products/GeneralMatrixVector.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_GENERAL_MATRIX_VECTOR_H\n#define EIGEN_GENERAL_MATRIX_VECTOR_H\n\nnamespace Eigen {\n\nnamespace internal {\n\n/* Optimized col-major matrix * vector product:\n * This algorithm processes 4 columns at onces that allows to both reduce\n * the number of load/stores of the result by a factor 4 and to reduce\n * the instruction dependency. Moreover, we know that all bands have the\n * same alignment pattern.\n *\n * Mixing type logic: C += alpha * A * B\n *  |  A  |  B  |alpha| comments\n *  |real |cplx |cplx | no vectorization\n *  |real |cplx |real | alpha is converted to a cplx when calling the run function, no vectorization\n *  |cplx |real |cplx | invalid, the caller has to do tmp: = A * B; C += alpha*tmp\n *  |cplx |real |real | optimal case, vectorization possible via real-cplx mul\n *\n * Accesses to the matrix coefficients follow the following logic:\n *\n * - if all columns have the same alignment then\n *   - if the columns have the same alignment as the result vector, then easy! (-> AllAligned case)\n *   - otherwise perform unaligned loads only (-> NoneAligned case)\n * - otherwise\n *   - if even columns have the same alignment then\n *     // odd columns are guaranteed to have the same alignment too\n *     - if even or odd columns have the same alignment as the result, then\n *       // for a register size of 2 scalars, this is guarantee to be the case (e.g., SSE with double)\n *       - perform half aligned and half unaligned loads (-> EvenAligned case)\n *     - otherwise perform unaligned loads only (-> NoneAligned case)\n *   - otherwise, if the register size is 4 scalars (e.g., SSE with float) then\n *     - one over 4 consecutive columns is guaranteed to be aligned with the result vector,\n *       perform simple aligned loads for this column and aligned loads plus re-alignment for the other. (-> FirstAligned case)\n *       // this re-alignment is done by the palign function implemented for SSE in Eigen/src/Core/arch/SSE/PacketMath.h\n *   - otherwise,\n *     // if we get here, this means the register size is greater than 4 (e.g., AVX with floats),\n *     // we currently fall back to the NoneAligned case\n *\n * The same reasoning apply for the transposed case.\n *\n * The last case (PacketSize>4) could probably be improved by generalizing the FirstAligned case, but since we do not support AVX yet...\n * One might also wonder why in the EvenAligned case we perform unaligned loads instead of using the aligned-loads plus re-alignment\n * strategy as in the FirstAligned case. The reason is that we observed that unaligned loads on a 8 byte boundary are not too slow\n * compared to unaligned loads on a 4 byte boundary.\n *\n */\ntemplate<typename Index, typename LhsScalar, typename LhsMapper, bool ConjugateLhs, typename RhsScalar, typename RhsMapper, bool ConjugateRhs, int Version>\nstruct general_matrix_vector_product<Index,LhsScalar,LhsMapper,ColMajor,ConjugateLhs,RhsScalar,RhsMapper,ConjugateRhs,Version>\n{\n  typedef typename ScalarBinaryOpTraits<LhsScalar, RhsScalar>::ReturnType ResScalar;\n\nenum {\n  Vectorizable = packet_traits<LhsScalar>::Vectorizable && packet_traits<RhsScalar>::Vectorizable\n              && int(packet_traits<LhsScalar>::size)==int(packet_traits<RhsScalar>::size),\n  LhsPacketSize = Vectorizable ? packet_traits<LhsScalar>::size : 1,\n  RhsPacketSize = Vectorizable ? packet_traits<RhsScalar>::size : 1,\n  ResPacketSize = Vectorizable ? packet_traits<ResScalar>::size : 1\n};\n\ntypedef typename packet_traits<LhsScalar>::type  _LhsPacket;\ntypedef typename packet_traits<RhsScalar>::type  _RhsPacket;\ntypedef typename packet_traits<ResScalar>::type  _ResPacket;\n\ntypedef typename conditional<Vectorizable,_LhsPacket,LhsScalar>::type LhsPacket;\ntypedef typename conditional<Vectorizable,_RhsPacket,RhsScalar>::type RhsPacket;\ntypedef typename conditional<Vectorizable,_ResPacket,ResScalar>::type ResPacket;\n\nEIGEN_DONT_INLINE static void run(\n  Index rows, Index cols,\n  const LhsMapper& lhs,\n  const RhsMapper& rhs,\n        ResScalar* res, Index resIncr,\n  RhsScalar alpha);\n};\n\ntemplate<typename Index, typename LhsScalar, typename LhsMapper, bool ConjugateLhs, typename RhsScalar, typename RhsMapper, bool ConjugateRhs, int Version>\nEIGEN_DONT_INLINE void general_matrix_vector_product<Index,LhsScalar,LhsMapper,ColMajor,ConjugateLhs,RhsScalar,RhsMapper,ConjugateRhs,Version>::run(\n  Index rows, Index cols,\n  const LhsMapper& lhs,\n  const RhsMapper& rhs,\n        ResScalar* res, Index resIncr,\n  RhsScalar alpha)\n{\n  EIGEN_UNUSED_VARIABLE(resIncr);\n  eigen_internal_assert(resIncr==1);\n  #ifdef _EIGEN_ACCUMULATE_PACKETS\n  #error _EIGEN_ACCUMULATE_PACKETS has already been defined\n  #endif\n  #define _EIGEN_ACCUMULATE_PACKETS(Alignment0,Alignment13,Alignment2) \\\n    pstore(&res[j], \\\n      padd(pload<ResPacket>(&res[j]), \\\n        padd( \\\n      padd(pcj.pmul(lhs0.template load<LhsPacket, Alignment0>(j),    ptmp0), \\\n      pcj.pmul(lhs1.template load<LhsPacket, Alignment13>(j),   ptmp1)),   \\\n      padd(pcj.pmul(lhs2.template load<LhsPacket, Alignment2>(j),    ptmp2), \\\n      pcj.pmul(lhs3.template load<LhsPacket, Alignment13>(j),   ptmp3)) )))\n\n  typedef typename LhsMapper::VectorMapper LhsScalars;\n\n  conj_helper<LhsScalar,RhsScalar,ConjugateLhs,ConjugateRhs> cj;\n  conj_helper<LhsPacket,RhsPacket,ConjugateLhs,ConjugateRhs> pcj;\n  if(ConjugateRhs)\n    alpha = numext::conj(alpha);\n\n  enum { AllAligned = 0, EvenAligned, FirstAligned, NoneAligned };\n  const Index columnsAtOnce = 4;\n  const Index peels = 2;\n  const Index LhsPacketAlignedMask = LhsPacketSize-1;\n  const Index ResPacketAlignedMask = ResPacketSize-1;\n//  const Index PeelAlignedMask = ResPacketSize*peels-1;\n  const Index size = rows;\n\n  const Index lhsStride = lhs.stride();\n\n  // How many coeffs of the result do we have to skip to be aligned.\n  // Here we assume data are at least aligned on the base scalar type.\n  Index alignedStart = internal::first_default_aligned(res,size);\n  Index alignedSize = ResPacketSize>1 ? alignedStart + ((size-alignedStart) & ~ResPacketAlignedMask) : 0;\n  const Index peeledSize = alignedSize - RhsPacketSize*peels - RhsPacketSize + 1;\n\n  const Index alignmentStep = LhsPacketSize>1 ? (LhsPacketSize - lhsStride % LhsPacketSize) & LhsPacketAlignedMask : 0;\n  Index alignmentPattern = alignmentStep==0 ? AllAligned\n                       : alignmentStep==(LhsPacketSize/2) ? EvenAligned\n                       : FirstAligned;\n\n  // we cannot assume the first element is aligned because of sub-matrices\n  const Index lhsAlignmentOffset = lhs.firstAligned(size);\n\n  // find how many columns do we have to skip to be aligned with the result (if possible)\n  Index skipColumns = 0;\n  // if the data cannot be aligned (TODO add some compile time tests when possible, e.g. for floats)\n  if( (lhsAlignmentOffset < 0) || (lhsAlignmentOffset == size) || (UIntPtr(res)%sizeof(ResScalar)) )\n  {\n    alignedSize = 0;\n    alignedStart = 0;\n    alignmentPattern = NoneAligned;\n  }\n  else if(LhsPacketSize > 4)\n  {\n    // TODO: extend the code to support aligned loads whenever possible when LhsPacketSize > 4.\n    // Currently, it seems to be better to perform unaligned loads anyway\n    alignmentPattern = NoneAligned;\n  }\n  else if (LhsPacketSize>1)\n  {\n  //    eigen_internal_assert(size_t(firstLhs+lhsAlignmentOffset)%sizeof(LhsPacket)==0 || size<LhsPacketSize);\n\n    while (skipColumns<LhsPacketSize &&\n          alignedStart != ((lhsAlignmentOffset + alignmentStep*skipColumns)%LhsPacketSize))\n      ++skipColumns;\n    if (skipColumns==LhsPacketSize)\n    {\n      // nothing can be aligned, no need to skip any column\n      alignmentPattern = NoneAligned;\n      skipColumns = 0;\n    }\n    else\n    {\n      skipColumns = (std::min)(skipColumns,cols);\n      // note that the skiped columns are processed later.\n    }\n\n    /*    eigen_internal_assert(  (alignmentPattern==NoneAligned)\n                      || (skipColumns + columnsAtOnce >= cols)\n                      || LhsPacketSize > size\n                      || (size_t(firstLhs+alignedStart+lhsStride*skipColumns)%sizeof(LhsPacket))==0);*/\n  }\n  else if(Vectorizable)\n  {\n    alignedStart = 0;\n    alignedSize = size;\n    alignmentPattern = AllAligned;\n  }\n\n  const Index offset1 = (FirstAligned && alignmentStep==1)?3:1;\n  const Index offset3 = (FirstAligned && alignmentStep==1)?1:3;\n\n  Index columnBound = ((cols-skipColumns)/columnsAtOnce)*columnsAtOnce + skipColumns;\n  for (Index i=skipColumns; i<columnBound; i+=columnsAtOnce)\n  {\n    RhsPacket ptmp0 = pset1<RhsPacket>(alpha*rhs(i, 0)),\n              ptmp1 = pset1<RhsPacket>(alpha*rhs(i+offset1, 0)),\n              ptmp2 = pset1<RhsPacket>(alpha*rhs(i+2, 0)),\n              ptmp3 = pset1<RhsPacket>(alpha*rhs(i+offset3, 0));\n\n    // this helps a lot generating better binary code\n    const LhsScalars lhs0 = lhs.getVectorMapper(0, i+0),   lhs1 = lhs.getVectorMapper(0, i+offset1),\n                     lhs2 = lhs.getVectorMapper(0, i+2),   lhs3 = lhs.getVectorMapper(0, i+offset3);\n\n    if (Vectorizable)\n    {\n      /* explicit vectorization */\n      // process initial unaligned coeffs\n      for (Index j=0; j<alignedStart; ++j)\n      {\n        res[j] = cj.pmadd(lhs0(j), pfirst(ptmp0), res[j]);\n        res[j] = cj.pmadd(lhs1(j), pfirst(ptmp1), res[j]);\n        res[j] = cj.pmadd(lhs2(j), pfirst(ptmp2), res[j]);\n        res[j] = cj.pmadd(lhs3(j), pfirst(ptmp3), res[j]);\n      }\n\n      if (alignedSize>alignedStart)\n      {\n        switch(alignmentPattern)\n        {\n          case AllAligned:\n            for (Index j = alignedStart; j<alignedSize; j+=ResPacketSize)\n              _EIGEN_ACCUMULATE_PACKETS(Aligned,Aligned,Aligned);\n            break;\n          case EvenAligned:\n            for (Index j = alignedStart; j<alignedSize; j+=ResPacketSize)\n              _EIGEN_ACCUMULATE_PACKETS(Aligned,Unaligned,Aligned);\n            break;\n          case FirstAligned:\n          {\n            Index j = alignedStart;\n            if(peels>1)\n            {\n              LhsPacket A00, A01, A02, A03, A10, A11, A12, A13;\n              ResPacket T0, T1;\n\n              A01 = lhs1.template load<LhsPacket, Aligned>(alignedStart-1);\n              A02 = lhs2.template load<LhsPacket, Aligned>(alignedStart-2);\n              A03 = lhs3.template load<LhsPacket, Aligned>(alignedStart-3);\n\n              for (; j<peeledSize; j+=peels*ResPacketSize)\n              {\n                A11 = lhs1.template load<LhsPacket, Aligned>(j-1+LhsPacketSize);  palign<1>(A01,A11);\n                A12 = lhs2.template load<LhsPacket, Aligned>(j-2+LhsPacketSize);  palign<2>(A02,A12);\n                A13 = lhs3.template load<LhsPacket, Aligned>(j-3+LhsPacketSize);  palign<3>(A03,A13);\n\n                A00 = lhs0.template load<LhsPacket, Aligned>(j);\n                A10 = lhs0.template load<LhsPacket, Aligned>(j+LhsPacketSize);\n                T0  = pcj.pmadd(A00, ptmp0, pload<ResPacket>(&res[j]));\n                T1  = pcj.pmadd(A10, ptmp0, pload<ResPacket>(&res[j+ResPacketSize]));\n\n                T0  = pcj.pmadd(A01, ptmp1, T0);\n                A01 = lhs1.template load<LhsPacket, Aligned>(j-1+2*LhsPacketSize);  palign<1>(A11,A01);\n                T0  = pcj.pmadd(A02, ptmp2, T0);\n                A02 = lhs2.template load<LhsPacket, Aligned>(j-2+2*LhsPacketSize);  palign<2>(A12,A02);\n                T0  = pcj.pmadd(A03, ptmp3, T0);\n                pstore(&res[j],T0);\n                A03 = lhs3.template load<LhsPacket, Aligned>(j-3+2*LhsPacketSize);  palign<3>(A13,A03);\n                T1  = pcj.pmadd(A11, ptmp1, T1);\n                T1  = pcj.pmadd(A12, ptmp2, T1);\n                T1  = pcj.pmadd(A13, ptmp3, T1);\n                pstore(&res[j+ResPacketSize],T1);\n              }\n            }\n            for (; j<alignedSize; j+=ResPacketSize)\n              _EIGEN_ACCUMULATE_PACKETS(Aligned,Unaligned,Unaligned);\n            break;\n          }\n          default:\n            for (Index j = alignedStart; j<alignedSize; j+=ResPacketSize)\n              _EIGEN_ACCUMULATE_PACKETS(Unaligned,Unaligned,Unaligned);\n            break;\n        }\n      }\n    } // end explicit vectorization\n\n    /* process remaining coeffs (or all if there is no explicit vectorization) */\n    for (Index j=alignedSize; j<size; ++j)\n    {\n      res[j] = cj.pmadd(lhs0(j), pfirst(ptmp0), res[j]);\n      res[j] = cj.pmadd(lhs1(j), pfirst(ptmp1), res[j]);\n      res[j] = cj.pmadd(lhs2(j), pfirst(ptmp2), res[j]);\n      res[j] = cj.pmadd(lhs3(j), pfirst(ptmp3), res[j]);\n    }\n  }\n\n  // process remaining first and last columns (at most columnsAtOnce-1)\n  Index end = cols;\n  Index start = columnBound;\n  do\n  {\n    for (Index k=start; k<end; ++k)\n    {\n      RhsPacket ptmp0 = pset1<RhsPacket>(alpha*rhs(k, 0));\n      const LhsScalars lhs0 = lhs.getVectorMapper(0, k);\n\n      if (Vectorizable)\n      {\n        /* explicit vectorization */\n        // process first unaligned result's coeffs\n        for (Index j=0; j<alignedStart; ++j)\n          res[j] += cj.pmul(lhs0(j), pfirst(ptmp0));\n        // process aligned result's coeffs\n        if (lhs0.template aligned<LhsPacket>(alignedStart))\n          for (Index i = alignedStart;i<alignedSize;i+=ResPacketSize)\n            pstore(&res[i], pcj.pmadd(lhs0.template load<LhsPacket, Aligned>(i), ptmp0, pload<ResPacket>(&res[i])));\n        else\n          for (Index i = alignedStart;i<alignedSize;i+=ResPacketSize)\n            pstore(&res[i], pcj.pmadd(lhs0.template load<LhsPacket, Unaligned>(i), ptmp0, pload<ResPacket>(&res[i])));\n      }\n\n      // process remaining scalars (or all if no explicit vectorization)\n      for (Index i=alignedSize; i<size; ++i)\n        res[i] += cj.pmul(lhs0(i), pfirst(ptmp0));\n    }\n    if (skipColumns)\n    {\n      start = 0;\n      end = skipColumns;\n      skipColumns = 0;\n    }\n    else\n      break;\n  } while(Vectorizable);\n  #undef _EIGEN_ACCUMULATE_PACKETS\n}\n\n/* Optimized row-major matrix * vector product:\n * This algorithm processes 4 rows at onces that allows to both reduce\n * the number of load/stores of the result by a factor 4 and to reduce\n * the instruction dependency. Moreover, we know that all bands have the\n * same alignment pattern.\n *\n * Mixing type logic:\n *  - alpha is always a complex (or converted to a complex)\n *  - no vectorization\n */\ntemplate<typename Index, typename LhsScalar, typename LhsMapper, bool ConjugateLhs, typename RhsScalar, typename RhsMapper, bool ConjugateRhs, int Version>\nstruct general_matrix_vector_product<Index,LhsScalar,LhsMapper,RowMajor,ConjugateLhs,RhsScalar,RhsMapper,ConjugateRhs,Version>\n{\ntypedef typename ScalarBinaryOpTraits<LhsScalar, RhsScalar>::ReturnType ResScalar;\n\nenum {\n  Vectorizable = packet_traits<LhsScalar>::Vectorizable && packet_traits<RhsScalar>::Vectorizable\n              && int(packet_traits<LhsScalar>::size)==int(packet_traits<RhsScalar>::size),\n  LhsPacketSize = Vectorizable ? packet_traits<LhsScalar>::size : 1,\n  RhsPacketSize = Vectorizable ? packet_traits<RhsScalar>::size : 1,\n  ResPacketSize = Vectorizable ? packet_traits<ResScalar>::size : 1\n};\n\ntypedef typename packet_traits<LhsScalar>::type  _LhsPacket;\ntypedef typename packet_traits<RhsScalar>::type  _RhsPacket;\ntypedef typename packet_traits<ResScalar>::type  _ResPacket;\n\ntypedef typename conditional<Vectorizable,_LhsPacket,LhsScalar>::type LhsPacket;\ntypedef typename conditional<Vectorizable,_RhsPacket,RhsScalar>::type RhsPacket;\ntypedef typename conditional<Vectorizable,_ResPacket,ResScalar>::type ResPacket;\n\nEIGEN_DONT_INLINE static void run(\n  Index rows, Index cols,\n  const LhsMapper& lhs,\n  const RhsMapper& rhs,\n        ResScalar* res, Index resIncr,\n  ResScalar alpha);\n};\n\ntemplate<typename Index, typename LhsScalar, typename LhsMapper, bool ConjugateLhs, typename RhsScalar, typename RhsMapper, bool ConjugateRhs, int Version>\nEIGEN_DONT_INLINE void general_matrix_vector_product<Index,LhsScalar,LhsMapper,RowMajor,ConjugateLhs,RhsScalar,RhsMapper,ConjugateRhs,Version>::run(\n  Index rows, Index cols,\n  const LhsMapper& lhs,\n  const RhsMapper& rhs,\n  ResScalar* res, Index resIncr,\n  ResScalar alpha)\n{\n  eigen_internal_assert(rhs.stride()==1);\n\n  #ifdef _EIGEN_ACCUMULATE_PACKETS\n  #error _EIGEN_ACCUMULATE_PACKETS has already been defined\n  #endif\n\n  #define _EIGEN_ACCUMULATE_PACKETS(Alignment0,Alignment13,Alignment2) {\\\n    RhsPacket b = rhs.getVectorMapper(j, 0).template load<RhsPacket, Aligned>(0);  \\\n    ptmp0 = pcj.pmadd(lhs0.template load<LhsPacket, Alignment0>(j), b, ptmp0); \\\n    ptmp1 = pcj.pmadd(lhs1.template load<LhsPacket, Alignment13>(j), b, ptmp1); \\\n    ptmp2 = pcj.pmadd(lhs2.template load<LhsPacket, Alignment2>(j), b, ptmp2); \\\n    ptmp3 = pcj.pmadd(lhs3.template load<LhsPacket, Alignment13>(j), b, ptmp3); }\n\n  conj_helper<LhsScalar,RhsScalar,ConjugateLhs,ConjugateRhs> cj;\n  conj_helper<LhsPacket,RhsPacket,ConjugateLhs,ConjugateRhs> pcj;\n\n  typedef typename LhsMapper::VectorMapper LhsScalars;\n\n  enum { AllAligned=0, EvenAligned=1, FirstAligned=2, NoneAligned=3 };\n  const Index rowsAtOnce = 4;\n  const Index peels = 2;\n  const Index RhsPacketAlignedMask = RhsPacketSize-1;\n  const Index LhsPacketAlignedMask = LhsPacketSize-1;\n  const Index depth = cols;\n  const Index lhsStride = lhs.stride();\n\n  // How many coeffs of the result do we have to skip to be aligned.\n  // Here we assume data are at least aligned on the base scalar type\n  // if that's not the case then vectorization is discarded, see below.\n  Index alignedStart = rhs.firstAligned(depth);\n  Index alignedSize = RhsPacketSize>1 ? alignedStart + ((depth-alignedStart) & ~RhsPacketAlignedMask) : 0;\n  const Index peeledSize = alignedSize - RhsPacketSize*peels - RhsPacketSize + 1;\n\n  const Index alignmentStep = LhsPacketSize>1 ? (LhsPacketSize - lhsStride % LhsPacketSize) & LhsPacketAlignedMask : 0;\n  Index alignmentPattern = alignmentStep==0 ? AllAligned\n                           : alignmentStep==(LhsPacketSize/2) ? EvenAligned\n                           : FirstAligned;\n\n  // we cannot assume the first element is aligned because of sub-matrices\n  const Index lhsAlignmentOffset = lhs.firstAligned(depth);\n  const Index rhsAlignmentOffset = rhs.firstAligned(rows);\n\n  // find how many rows do we have to skip to be aligned with rhs (if possible)\n  Index skipRows = 0;\n  // if the data cannot be aligned (TODO add some compile time tests when possible, e.g. for floats)\n  if( (sizeof(LhsScalar)!=sizeof(RhsScalar)) ||\n      (lhsAlignmentOffset < 0) || (lhsAlignmentOffset == depth) ||\n      (rhsAlignmentOffset < 0) || (rhsAlignmentOffset == rows) )\n  {\n    alignedSize = 0;\n    alignedStart = 0;\n    alignmentPattern = NoneAligned;\n  }\n  else if(LhsPacketSize > 4)\n  {\n    // TODO: extend the code to support aligned loads whenever possible when LhsPacketSize > 4.\n    alignmentPattern = NoneAligned;\n  }\n  else if (LhsPacketSize>1)\n  {\n  //    eigen_internal_assert(size_t(firstLhs+lhsAlignmentOffset)%sizeof(LhsPacket)==0  || depth<LhsPacketSize);\n\n    while (skipRows<LhsPacketSize &&\n           alignedStart != ((lhsAlignmentOffset + alignmentStep*skipRows)%LhsPacketSize))\n      ++skipRows;\n    if (skipRows==LhsPacketSize)\n    {\n      // nothing can be aligned, no need to skip any column\n      alignmentPattern = NoneAligned;\n      skipRows = 0;\n    }\n    else\n    {\n      skipRows = (std::min)(skipRows,Index(rows));\n      // note that the skiped columns are processed later.\n    }\n    /*    eigen_internal_assert(  alignmentPattern==NoneAligned\n                      || LhsPacketSize==1\n                      || (skipRows + rowsAtOnce >= rows)\n                      || LhsPacketSize > depth\n                      || (size_t(firstLhs+alignedStart+lhsStride*skipRows)%sizeof(LhsPacket))==0);*/\n  }\n  else if(Vectorizable)\n  {\n    alignedStart = 0;\n    alignedSize = depth;\n    alignmentPattern = AllAligned;\n  }\n\n  const Index offset1 = (FirstAligned && alignmentStep==1)?3:1;\n  const Index offset3 = (FirstAligned && alignmentStep==1)?1:3;\n\n  Index rowBound = ((rows-skipRows)/rowsAtOnce)*rowsAtOnce + skipRows;\n  for (Index i=skipRows; i<rowBound; i+=rowsAtOnce)\n  {\n    // FIXME: what is the purpose of this EIGEN_ALIGN_DEFAULT ??\n    EIGEN_ALIGN_MAX ResScalar tmp0 = ResScalar(0);\n    ResScalar tmp1 = ResScalar(0), tmp2 = ResScalar(0), tmp3 = ResScalar(0);\n\n    // this helps the compiler generating good binary code\n    const LhsScalars lhs0 = lhs.getVectorMapper(i+0, 0),    lhs1 = lhs.getVectorMapper(i+offset1, 0),\n                     lhs2 = lhs.getVectorMapper(i+2, 0),    lhs3 = lhs.getVectorMapper(i+offset3, 0);\n\n    if (Vectorizable)\n    {\n      /* explicit vectorization */\n      ResPacket ptmp0 = pset1<ResPacket>(ResScalar(0)), ptmp1 = pset1<ResPacket>(ResScalar(0)),\n                ptmp2 = pset1<ResPacket>(ResScalar(0)), ptmp3 = pset1<ResPacket>(ResScalar(0));\n\n      // process initial unaligned coeffs\n      // FIXME this loop get vectorized by the compiler !\n      for (Index j=0; j<alignedStart; ++j)\n      {\n        RhsScalar b = rhs(j, 0);\n        tmp0 += cj.pmul(lhs0(j),b); tmp1 += cj.pmul(lhs1(j),b);\n        tmp2 += cj.pmul(lhs2(j),b); tmp3 += cj.pmul(lhs3(j),b);\n      }\n\n      if (alignedSize>alignedStart)\n      {\n        switch(alignmentPattern)\n        {\n          case AllAligned:\n            for (Index j = alignedStart; j<alignedSize; j+=RhsPacketSize)\n              _EIGEN_ACCUMULATE_PACKETS(Aligned,Aligned,Aligned);\n            break;\n          case EvenAligned:\n            for (Index j = alignedStart; j<alignedSize; j+=RhsPacketSize)\n              _EIGEN_ACCUMULATE_PACKETS(Aligned,Unaligned,Aligned);\n            break;\n          case FirstAligned:\n          {\n            Index j = alignedStart;\n            if (peels>1)\n            {\n              /* Here we proccess 4 rows with with two peeled iterations to hide\n               * the overhead of unaligned loads. Moreover unaligned loads are handled\n               * using special shift/move operations between the two aligned packets\n               * overlaping the desired unaligned packet. This is *much* more efficient\n               * than basic unaligned loads.\n               */\n              LhsPacket A01, A02, A03, A11, A12, A13;\n              A01 = lhs1.template load<LhsPacket, Aligned>(alignedStart-1);\n              A02 = lhs2.template load<LhsPacket, Aligned>(alignedStart-2);\n              A03 = lhs3.template load<LhsPacket, Aligned>(alignedStart-3);\n\n              for (; j<peeledSize; j+=peels*RhsPacketSize)\n              {\n                RhsPacket b = rhs.getVectorMapper(j, 0).template load<RhsPacket, Aligned>(0);\n                A11 = lhs1.template load<LhsPacket, Aligned>(j-1+LhsPacketSize);  palign<1>(A01,A11);\n                A12 = lhs2.template load<LhsPacket, Aligned>(j-2+LhsPacketSize);  palign<2>(A02,A12);\n                A13 = lhs3.template load<LhsPacket, Aligned>(j-3+LhsPacketSize);  palign<3>(A03,A13);\n\n                ptmp0 = pcj.pmadd(lhs0.template load<LhsPacket, Aligned>(j), b, ptmp0);\n                ptmp1 = pcj.pmadd(A01, b, ptmp1);\n                A01 = lhs1.template load<LhsPacket, Aligned>(j-1+2*LhsPacketSize);  palign<1>(A11,A01);\n                ptmp2 = pcj.pmadd(A02, b, ptmp2);\n                A02 = lhs2.template load<LhsPacket, Aligned>(j-2+2*LhsPacketSize);  palign<2>(A12,A02);\n                ptmp3 = pcj.pmadd(A03, b, ptmp3);\n                A03 = lhs3.template load<LhsPacket, Aligned>(j-3+2*LhsPacketSize);  palign<3>(A13,A03);\n\n                b = rhs.getVectorMapper(j+RhsPacketSize, 0).template load<RhsPacket, Aligned>(0);\n                ptmp0 = pcj.pmadd(lhs0.template load<LhsPacket, Aligned>(j+LhsPacketSize), b, ptmp0);\n                ptmp1 = pcj.pmadd(A11, b, ptmp1);\n                ptmp2 = pcj.pmadd(A12, b, ptmp2);\n                ptmp3 = pcj.pmadd(A13, b, ptmp3);\n              }\n            }\n            for (; j<alignedSize; j+=RhsPacketSize)\n              _EIGEN_ACCUMULATE_PACKETS(Aligned,Unaligned,Unaligned);\n            break;\n          }\n          default:\n            for (Index j = alignedStart; j<alignedSize; j+=RhsPacketSize)\n              _EIGEN_ACCUMULATE_PACKETS(Unaligned,Unaligned,Unaligned);\n            break;\n        }\n        tmp0 += predux(ptmp0);\n        tmp1 += predux(ptmp1);\n        tmp2 += predux(ptmp2);\n        tmp3 += predux(ptmp3);\n      }\n    } // end explicit vectorization\n\n    // process remaining coeffs (or all if no explicit vectorization)\n    // FIXME this loop get vectorized by the compiler !\n    for (Index j=alignedSize; j<depth; ++j)\n    {\n      RhsScalar b = rhs(j, 0);\n      tmp0 += cj.pmul(lhs0(j),b); tmp1 += cj.pmul(lhs1(j),b);\n      tmp2 += cj.pmul(lhs2(j),b); tmp3 += cj.pmul(lhs3(j),b);\n    }\n    res[i*resIncr]            += alpha*tmp0;\n    res[(i+offset1)*resIncr]  += alpha*tmp1;\n    res[(i+2)*resIncr]        += alpha*tmp2;\n    res[(i+offset3)*resIncr]  += alpha*tmp3;\n  }\n\n  // process remaining first and last rows (at most columnsAtOnce-1)\n  Index end = rows;\n  Index start = rowBound;\n  do\n  {\n    for (Index i=start; i<end; ++i)\n    {\n      EIGEN_ALIGN_MAX ResScalar tmp0 = ResScalar(0);\n      ResPacket ptmp0 = pset1<ResPacket>(tmp0);\n      const LhsScalars lhs0 = lhs.getVectorMapper(i, 0);\n      // process first unaligned result's coeffs\n      // FIXME this loop get vectorized by the compiler !\n      for (Index j=0; j<alignedStart; ++j)\n        tmp0 += cj.pmul(lhs0(j), rhs(j, 0));\n\n      if (alignedSize>alignedStart)\n      {\n        // process aligned rhs coeffs\n        if (lhs0.template aligned<LhsPacket>(alignedStart))\n          for (Index j = alignedStart;j<alignedSize;j+=RhsPacketSize)\n            ptmp0 = pcj.pmadd(lhs0.template load<LhsPacket, Aligned>(j), rhs.getVectorMapper(j, 0).template load<RhsPacket, Aligned>(0), ptmp0);\n        else\n          for (Index j = alignedStart;j<alignedSize;j+=RhsPacketSize)\n            ptmp0 = pcj.pmadd(lhs0.template load<LhsPacket, Unaligned>(j), rhs.getVectorMapper(j, 0).template load<RhsPacket, Aligned>(0), ptmp0);\n        tmp0 += predux(ptmp0);\n      }\n\n      // process remaining scalars\n      // FIXME this loop get vectorized by the compiler !\n      for (Index j=alignedSize; j<depth; ++j)\n        tmp0 += cj.pmul(lhs0(j), rhs(j, 0));\n      res[i*resIncr] += alpha*tmp0;\n    }\n    if (skipRows)\n    {\n      start = 0;\n      end = skipRows;\n      skipRows = 0;\n    }\n    else\n      break;\n  } while(Vectorizable);\n\n  #undef _EIGEN_ACCUMULATE_PACKETS\n}\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_GENERAL_MATRIX_VECTOR_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/products/GeneralMatrixVector_BLAS.h",
    "content": "/*\n Copyright (c) 2011, Intel Corporation. All rights reserved.\n\n Redistribution and use in source and binary forms, with or without modification,\n are permitted provided that the following conditions are met:\n\n * Redistributions of source code must retain the above copyright notice, this\n   list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright notice,\n   this list of conditions and the following disclaimer in the documentation\n   and/or other materials provided with the distribution.\n * Neither the name of Intel Corporation nor the names of its contributors may\n   be used to endorse or promote products derived from this software without\n   specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n ********************************************************************************\n *   Content : Eigen bindings to BLAS F77\n *   General matrix-vector product functionality based on ?GEMV.\n ********************************************************************************\n*/\n\n#ifndef EIGEN_GENERAL_MATRIX_VECTOR_BLAS_H\n#define EIGEN_GENERAL_MATRIX_VECTOR_BLAS_H\n\nnamespace Eigen { \n\nnamespace internal {\n\n/**********************************************************************\n* This file implements general matrix-vector multiplication using BLAS\n* gemv function via partial specialization of\n* general_matrix_vector_product::run(..) method for float, double,\n* std::complex<float> and std::complex<double> types\n**********************************************************************/\n\n// gemv specialization\n\ntemplate<typename Index, typename LhsScalar, int StorageOrder, bool ConjugateLhs, typename RhsScalar, bool ConjugateRhs>\nstruct general_matrix_vector_product_gemv;\n\n#define EIGEN_BLAS_GEMV_SPECIALIZE(Scalar) \\\ntemplate<typename Index, bool ConjugateLhs, bool ConjugateRhs> \\\nstruct general_matrix_vector_product<Index,Scalar,const_blas_data_mapper<Scalar,Index,ColMajor>,ColMajor,ConjugateLhs,Scalar,const_blas_data_mapper<Scalar,Index,RowMajor>,ConjugateRhs,Specialized> { \\\nstatic void run( \\\n  Index rows, Index cols, \\\n  const const_blas_data_mapper<Scalar,Index,ColMajor> &lhs, \\\n  const const_blas_data_mapper<Scalar,Index,RowMajor> &rhs, \\\n  Scalar* res, Index resIncr, Scalar alpha) \\\n{ \\\n  if (ConjugateLhs) { \\\n    general_matrix_vector_product<Index,Scalar,const_blas_data_mapper<Scalar,Index,ColMajor>,ColMajor,ConjugateLhs,Scalar,const_blas_data_mapper<Scalar,Index,RowMajor>,ConjugateRhs,BuiltIn>::run( \\\n      rows, cols, lhs, rhs, res, resIncr, alpha); \\\n  } else { \\\n    general_matrix_vector_product_gemv<Index,Scalar,ColMajor,ConjugateLhs,Scalar,ConjugateRhs>::run( \\\n      rows, cols, lhs.data(), lhs.stride(), rhs.data(), rhs.stride(), res, resIncr, alpha); \\\n  } \\\n} \\\n}; \\\ntemplate<typename Index, bool ConjugateLhs, bool ConjugateRhs> \\\nstruct general_matrix_vector_product<Index,Scalar,const_blas_data_mapper<Scalar,Index,RowMajor>,RowMajor,ConjugateLhs,Scalar,const_blas_data_mapper<Scalar,Index,ColMajor>,ConjugateRhs,Specialized> { \\\nstatic void run( \\\n  Index rows, Index cols, \\\n  const const_blas_data_mapper<Scalar,Index,RowMajor> &lhs, \\\n  const const_blas_data_mapper<Scalar,Index,ColMajor> &rhs, \\\n  Scalar* res, Index resIncr, Scalar alpha) \\\n{ \\\n    general_matrix_vector_product_gemv<Index,Scalar,RowMajor,ConjugateLhs,Scalar,ConjugateRhs>::run( \\\n      rows, cols, lhs.data(), lhs.stride(), rhs.data(), rhs.stride(), res, resIncr, alpha); \\\n} \\\n}; \\\n\nEIGEN_BLAS_GEMV_SPECIALIZE(double)\nEIGEN_BLAS_GEMV_SPECIALIZE(float)\nEIGEN_BLAS_GEMV_SPECIALIZE(dcomplex)\nEIGEN_BLAS_GEMV_SPECIALIZE(scomplex)\n\n#define EIGEN_BLAS_GEMV_SPECIALIZATION(EIGTYPE,BLASTYPE,BLASPREFIX) \\\ntemplate<typename Index, int LhsStorageOrder, bool ConjugateLhs, bool ConjugateRhs> \\\nstruct general_matrix_vector_product_gemv<Index,EIGTYPE,LhsStorageOrder,ConjugateLhs,EIGTYPE,ConjugateRhs> \\\n{ \\\ntypedef Matrix<EIGTYPE,Dynamic,1,ColMajor> GEMVVector;\\\n\\\nstatic void run( \\\n  Index rows, Index cols, \\\n  const EIGTYPE* lhs, Index lhsStride, \\\n  const EIGTYPE* rhs, Index rhsIncr, \\\n  EIGTYPE* res, Index resIncr, EIGTYPE alpha) \\\n{ \\\n  BlasIndex m=convert_index<BlasIndex>(rows), n=convert_index<BlasIndex>(cols), \\\n            lda=convert_index<BlasIndex>(lhsStride), incx=convert_index<BlasIndex>(rhsIncr), incy=convert_index<BlasIndex>(resIncr); \\\n  const EIGTYPE beta(1); \\\n  const EIGTYPE *x_ptr; \\\n  char trans=(LhsStorageOrder==ColMajor) ? 'N' : (ConjugateLhs) ? 'C' : 'T'; \\\n  if (LhsStorageOrder==RowMajor) { \\\n    m = convert_index<BlasIndex>(cols); \\\n    n = convert_index<BlasIndex>(rows); \\\n  }\\\n  GEMVVector x_tmp; \\\n  if (ConjugateRhs) { \\\n    Map<const GEMVVector, 0, InnerStride<> > map_x(rhs,cols,1,InnerStride<>(incx)); \\\n    x_tmp=map_x.conjugate(); \\\n    x_ptr=x_tmp.data(); \\\n    incx=1; \\\n  } else x_ptr=rhs; \\\n  BLASPREFIX##gemv_(&trans, &m, &n, &numext::real_ref(alpha), (const BLASTYPE*)lhs, &lda, (const BLASTYPE*)x_ptr, &incx, &numext::real_ref(beta), (BLASTYPE*)res, &incy); \\\n}\\\n};\n\nEIGEN_BLAS_GEMV_SPECIALIZATION(double,   double, d)\nEIGEN_BLAS_GEMV_SPECIALIZATION(float,    float,  s)\nEIGEN_BLAS_GEMV_SPECIALIZATION(dcomplex, double, z)\nEIGEN_BLAS_GEMV_SPECIALIZATION(scomplex, float,  c)\n\n} // end namespase internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_GENERAL_MATRIX_VECTOR_BLAS_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/products/Parallelizer.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_PARALLELIZER_H\n#define EIGEN_PARALLELIZER_H\n\nnamespace Eigen {\n\nnamespace internal {\n\n/** \\internal */\ninline void manage_multi_threading(Action action, int* v)\n{\n  static EIGEN_UNUSED int m_maxThreads = -1;\n\n  if(action==SetAction)\n  {\n    eigen_internal_assert(v!=0);\n    m_maxThreads = *v;\n  }\n  else if(action==GetAction)\n  {\n    eigen_internal_assert(v!=0);\n    #ifdef EIGEN_HAS_OPENMP\n    if(m_maxThreads>0)\n      *v = m_maxThreads;\n    else\n      *v = omp_get_max_threads();\n    #else\n    *v = 1;\n    #endif\n  }\n  else\n  {\n    eigen_internal_assert(false);\n  }\n}\n\n}\n\n/** Must be call first when calling Eigen from multiple threads */\ninline void initParallel()\n{\n  int nbt;\n  internal::manage_multi_threading(GetAction, &nbt);\n  std::ptrdiff_t l1, l2, l3;\n  internal::manage_caching_sizes(GetAction, &l1, &l2, &l3);\n}\n\n/** \\returns the max number of threads reserved for Eigen\n  * \\sa setNbThreads */\ninline int nbThreads()\n{\n  int ret;\n  internal::manage_multi_threading(GetAction, &ret);\n  return ret;\n}\n\n/** Sets the max number of threads reserved for Eigen\n  * \\sa nbThreads */\ninline void setNbThreads(int v)\n{\n  internal::manage_multi_threading(SetAction, &v);\n}\n\nnamespace internal {\n\ntemplate<typename Index> struct GemmParallelInfo\n{\n  GemmParallelInfo() : sync(-1), users(0), lhs_start(0), lhs_length(0) {}\n\n  int volatile sync;\n  int volatile users;\n\n  Index lhs_start;\n  Index lhs_length;\n};\n\ntemplate<bool Condition, typename Functor, typename Index>\nvoid parallelize_gemm(const Functor& func, Index rows, Index cols, Index depth, bool transpose)\n{\n  // TODO when EIGEN_USE_BLAS is defined,\n  // we should still enable OMP for other scalar types\n#if !(defined (EIGEN_HAS_OPENMP)) || defined (EIGEN_USE_BLAS)\n  // FIXME the transpose variable is only needed to properly split\n  // the matrix product when multithreading is enabled. This is a temporary\n  // fix to support row-major destination matrices. This whole\n  // parallelizer mechanism has to be redisigned anyway.\n  EIGEN_UNUSED_VARIABLE(depth);\n  EIGEN_UNUSED_VARIABLE(transpose);\n  func(0,rows, 0,cols);\n#else\n\n  // Dynamically check whether we should enable or disable OpenMP.\n  // The conditions are:\n  // - the max number of threads we can create is greater than 1\n  // - we are not already in a parallel code\n  // - the sizes are large enough\n\n  // compute the maximal number of threads from the size of the product:\n  // FIXME this has to be fine tuned\n  Index size = transpose ? rows : cols;\n  Index pb_max_threads = std::max<Index>(1,size / 32);\n  // compute the maximal number of threads from the total amount of work:\n  double work = static_cast<double>(rows) * static_cast<double>(cols) *\n      static_cast<double>(depth);\n  double kMinTaskSize = 50000;  // Heuristic.\n  pb_max_threads = std::max<Index>(1, std::min<Index>(pb_max_threads, work / kMinTaskSize));\n\n  // compute the number of threads we are going to use\n  Index threads = std::min<Index>(nbThreads(), pb_max_threads);\n\n  // if multi-threading is explicitely disabled, not useful, or if we already are in a parallel session,\n  // then abort multi-threading\n  // FIXME omp_get_num_threads()>1 only works for openmp, what if the user does not use openmp?\n  if((!Condition) || (threads==1) || (omp_get_num_threads()>1))\n    return func(0,rows, 0,cols);\n\n  Eigen::initParallel();\n  func.initParallelSession(threads);\n\n  if(transpose)\n    std::swap(rows,cols);\n\n  ei_declare_aligned_stack_constructed_variable(GemmParallelInfo<Index>,info,threads,0);\n\n  #pragma omp parallel num_threads(threads)\n  {\n    Index i = omp_get_thread_num();\n    // Note that the actual number of threads might be lower than the number of request ones.\n    Index actual_threads = omp_get_num_threads();\n\n    Index blockCols = (cols / actual_threads) & ~Index(0x3);\n    Index blockRows = (rows / actual_threads);\n    blockRows = (blockRows/Functor::Traits::mr)*Functor::Traits::mr;\n\n    Index r0 = i*blockRows;\n    Index actualBlockRows = (i+1==actual_threads) ? rows-r0 : blockRows;\n\n    Index c0 = i*blockCols;\n    Index actualBlockCols = (i+1==actual_threads) ? cols-c0 : blockCols;\n\n    info[i].lhs_start = r0;\n    info[i].lhs_length = actualBlockRows;\n\n    if(transpose) func(c0, actualBlockCols, 0, rows, info);\n    else          func(0, rows, c0, actualBlockCols, info);\n  }\n#endif\n}\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_PARALLELIZER_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/products/SelfadjointMatrixMatrix.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SELFADJOINT_MATRIX_MATRIX_H\n#define EIGEN_SELFADJOINT_MATRIX_MATRIX_H\n\nnamespace Eigen { \n\nnamespace internal {\n\n// pack a selfadjoint block diagonal for use with the gebp_kernel\ntemplate<typename Scalar, typename Index, int Pack1, int Pack2_dummy, int StorageOrder>\nstruct symm_pack_lhs\n{\n  template<int BlockRows> inline\n  void pack(Scalar* blockA, const const_blas_data_mapper<Scalar,Index,StorageOrder>& lhs, Index cols, Index i, Index& count)\n  {\n    // normal copy\n    for(Index k=0; k<i; k++)\n      for(Index w=0; w<BlockRows; w++)\n        blockA[count++] = lhs(i+w,k);           // normal\n    // symmetric copy\n    Index h = 0;\n    for(Index k=i; k<i+BlockRows; k++)\n    {\n      for(Index w=0; w<h; w++)\n        blockA[count++] = numext::conj(lhs(k, i+w)); // transposed\n\n      blockA[count++] = numext::real(lhs(k,k));   // real (diagonal)\n\n      for(Index w=h+1; w<BlockRows; w++)\n        blockA[count++] = lhs(i+w, k);          // normal\n      ++h;\n    }\n    // transposed copy\n    for(Index k=i+BlockRows; k<cols; k++)\n      for(Index w=0; w<BlockRows; w++)\n        blockA[count++] = numext::conj(lhs(k, i+w)); // transposed\n  }\n  void operator()(Scalar* blockA, const Scalar* _lhs, Index lhsStride, Index cols, Index rows)\n  {\n    enum { PacketSize = packet_traits<Scalar>::size };\n    const_blas_data_mapper<Scalar,Index,StorageOrder> lhs(_lhs,lhsStride);\n    Index count = 0;\n    //Index peeled_mc3 = (rows/Pack1)*Pack1;\n    \n    const Index peeled_mc3 = Pack1>=3*PacketSize ? (rows/(3*PacketSize))*(3*PacketSize) : 0;\n    const Index peeled_mc2 = Pack1>=2*PacketSize ? peeled_mc3+((rows-peeled_mc3)/(2*PacketSize))*(2*PacketSize) : 0;\n    const Index peeled_mc1 = Pack1>=1*PacketSize ? (rows/(1*PacketSize))*(1*PacketSize) : 0;\n    \n    if(Pack1>=3*PacketSize)\n      for(Index i=0; i<peeled_mc3; i+=3*PacketSize)\n        pack<3*PacketSize>(blockA, lhs, cols, i, count);\n    \n    if(Pack1>=2*PacketSize)\n      for(Index i=peeled_mc3; i<peeled_mc2; i+=2*PacketSize)\n        pack<2*PacketSize>(blockA, lhs, cols, i, count);\n    \n    if(Pack1>=1*PacketSize)\n      for(Index i=peeled_mc2; i<peeled_mc1; i+=1*PacketSize)\n        pack<1*PacketSize>(blockA, lhs, cols, i, count);\n\n    // do the same with mr==1\n    for(Index i=peeled_mc1; i<rows; i++)\n    {\n      for(Index k=0; k<i; k++)\n        blockA[count++] = lhs(i, k);                   // normal\n\n      blockA[count++] = numext::real(lhs(i, i));       // real (diagonal)\n\n      for(Index k=i+1; k<cols; k++)\n        blockA[count++] = numext::conj(lhs(k, i));     // transposed\n    }\n  }\n};\n\ntemplate<typename Scalar, typename Index, int nr, int StorageOrder>\nstruct symm_pack_rhs\n{\n  enum { PacketSize = packet_traits<Scalar>::size };\n  void operator()(Scalar* blockB, const Scalar* _rhs, Index rhsStride, Index rows, Index cols, Index k2)\n  {\n    Index end_k = k2 + rows;\n    Index count = 0;\n    const_blas_data_mapper<Scalar,Index,StorageOrder> rhs(_rhs,rhsStride);\n    Index packet_cols8 = nr>=8 ? (cols/8) * 8 : 0;\n    Index packet_cols4 = nr>=4 ? (cols/4) * 4 : 0;\n\n    // first part: normal case\n    for(Index j2=0; j2<k2; j2+=nr)\n    {\n      for(Index k=k2; k<end_k; k++)\n      {\n        blockB[count+0] = rhs(k,j2+0);\n        blockB[count+1] = rhs(k,j2+1);\n        if (nr>=4)\n        {\n          blockB[count+2] = rhs(k,j2+2);\n          blockB[count+3] = rhs(k,j2+3);\n        }\n        if (nr>=8)\n        {\n          blockB[count+4] = rhs(k,j2+4);\n          blockB[count+5] = rhs(k,j2+5);\n          blockB[count+6] = rhs(k,j2+6);\n          blockB[count+7] = rhs(k,j2+7);\n        }\n        count += nr;\n      }\n    }\n\n    // second part: diagonal block\n    Index end8 = nr>=8 ? (std::min)(k2+rows,packet_cols8) : k2;\n    if(nr>=8)\n    {\n      for(Index j2=k2; j2<end8; j2+=8)\n      {\n        // again we can split vertically in three different parts (transpose, symmetric, normal)\n        // transpose\n        for(Index k=k2; k<j2; k++)\n        {\n          blockB[count+0] = numext::conj(rhs(j2+0,k));\n          blockB[count+1] = numext::conj(rhs(j2+1,k));\n          blockB[count+2] = numext::conj(rhs(j2+2,k));\n          blockB[count+3] = numext::conj(rhs(j2+3,k));\n          blockB[count+4] = numext::conj(rhs(j2+4,k));\n          blockB[count+5] = numext::conj(rhs(j2+5,k));\n          blockB[count+6] = numext::conj(rhs(j2+6,k));\n          blockB[count+7] = numext::conj(rhs(j2+7,k));\n          count += 8;\n        }\n        // symmetric\n        Index h = 0;\n        for(Index k=j2; k<j2+8; k++)\n        {\n          // normal\n          for (Index w=0 ; w<h; ++w)\n            blockB[count+w] = rhs(k,j2+w);\n\n          blockB[count+h] = numext::real(rhs(k,k));\n\n          // transpose\n          for (Index w=h+1 ; w<8; ++w)\n            blockB[count+w] = numext::conj(rhs(j2+w,k));\n          count += 8;\n          ++h;\n        }\n        // normal\n        for(Index k=j2+8; k<end_k; k++)\n        {\n          blockB[count+0] = rhs(k,j2+0);\n          blockB[count+1] = rhs(k,j2+1);\n          blockB[count+2] = rhs(k,j2+2);\n          blockB[count+3] = rhs(k,j2+3);\n          blockB[count+4] = rhs(k,j2+4);\n          blockB[count+5] = rhs(k,j2+5);\n          blockB[count+6] = rhs(k,j2+6);\n          blockB[count+7] = rhs(k,j2+7);\n          count += 8;\n        }\n      }\n    }\n    if(nr>=4)\n    {\n      for(Index j2=end8; j2<(std::min)(k2+rows,packet_cols4); j2+=4)\n      {\n        // again we can split vertically in three different parts (transpose, symmetric, normal)\n        // transpose\n        for(Index k=k2; k<j2; k++)\n        {\n          blockB[count+0] = numext::conj(rhs(j2+0,k));\n          blockB[count+1] = numext::conj(rhs(j2+1,k));\n          blockB[count+2] = numext::conj(rhs(j2+2,k));\n          blockB[count+3] = numext::conj(rhs(j2+3,k));\n          count += 4;\n        }\n        // symmetric\n        Index h = 0;\n        for(Index k=j2; k<j2+4; k++)\n        {\n          // normal\n          for (Index w=0 ; w<h; ++w)\n            blockB[count+w] = rhs(k,j2+w);\n\n          blockB[count+h] = numext::real(rhs(k,k));\n\n          // transpose\n          for (Index w=h+1 ; w<4; ++w)\n            blockB[count+w] = numext::conj(rhs(j2+w,k));\n          count += 4;\n          ++h;\n        }\n        // normal\n        for(Index k=j2+4; k<end_k; k++)\n        {\n          blockB[count+0] = rhs(k,j2+0);\n          blockB[count+1] = rhs(k,j2+1);\n          blockB[count+2] = rhs(k,j2+2);\n          blockB[count+3] = rhs(k,j2+3);\n          count += 4;\n        }\n      }\n    }\n\n    // third part: transposed\n    if(nr>=8)\n    {\n      for(Index j2=k2+rows; j2<packet_cols8; j2+=8)\n      {\n        for(Index k=k2; k<end_k; k++)\n        {\n          blockB[count+0] = numext::conj(rhs(j2+0,k));\n          blockB[count+1] = numext::conj(rhs(j2+1,k));\n          blockB[count+2] = numext::conj(rhs(j2+2,k));\n          blockB[count+3] = numext::conj(rhs(j2+3,k));\n          blockB[count+4] = numext::conj(rhs(j2+4,k));\n          blockB[count+5] = numext::conj(rhs(j2+5,k));\n          blockB[count+6] = numext::conj(rhs(j2+6,k));\n          blockB[count+7] = numext::conj(rhs(j2+7,k));\n          count += 8;\n        }\n      }\n    }\n    if(nr>=4)\n    {\n      for(Index j2=(std::max)(packet_cols8,k2+rows); j2<packet_cols4; j2+=4)\n      {\n        for(Index k=k2; k<end_k; k++)\n        {\n          blockB[count+0] = numext::conj(rhs(j2+0,k));\n          blockB[count+1] = numext::conj(rhs(j2+1,k));\n          blockB[count+2] = numext::conj(rhs(j2+2,k));\n          blockB[count+3] = numext::conj(rhs(j2+3,k));\n          count += 4;\n        }\n      }\n    }\n\n    // copy the remaining columns one at a time (=> the same with nr==1)\n    for(Index j2=packet_cols4; j2<cols; ++j2)\n    {\n      // transpose\n      Index half = (std::min)(end_k,j2);\n      for(Index k=k2; k<half; k++)\n      {\n        blockB[count] = numext::conj(rhs(j2,k));\n        count += 1;\n      }\n\n      if(half==j2 && half<k2+rows)\n      {\n        blockB[count] = numext::real(rhs(j2,j2));\n        count += 1;\n      }\n      else\n        half--;\n\n      // normal\n      for(Index k=half+1; k<k2+rows; k++)\n      {\n        blockB[count] = rhs(k,j2);\n        count += 1;\n      }\n    }\n  }\n};\n\n/* Optimized selfadjoint matrix * matrix (_SYMM) product built on top of\n * the general matrix matrix product.\n */\ntemplate <typename Scalar, typename Index,\n          int LhsStorageOrder, bool LhsSelfAdjoint, bool ConjugateLhs,\n          int RhsStorageOrder, bool RhsSelfAdjoint, bool ConjugateRhs,\n          int ResStorageOrder>\nstruct product_selfadjoint_matrix;\n\ntemplate <typename Scalar, typename Index,\n          int LhsStorageOrder, bool LhsSelfAdjoint, bool ConjugateLhs,\n          int RhsStorageOrder, bool RhsSelfAdjoint, bool ConjugateRhs>\nstruct product_selfadjoint_matrix<Scalar,Index,LhsStorageOrder,LhsSelfAdjoint,ConjugateLhs, RhsStorageOrder,RhsSelfAdjoint,ConjugateRhs,RowMajor>\n{\n\n  static EIGEN_STRONG_INLINE void run(\n    Index rows, Index cols,\n    const Scalar* lhs, Index lhsStride,\n    const Scalar* rhs, Index rhsStride,\n    Scalar* res,       Index resStride,\n    const Scalar& alpha, level3_blocking<Scalar,Scalar>& blocking)\n  {\n    product_selfadjoint_matrix<Scalar, Index,\n      EIGEN_LOGICAL_XOR(RhsSelfAdjoint,RhsStorageOrder==RowMajor) ? ColMajor : RowMajor,\n      RhsSelfAdjoint, NumTraits<Scalar>::IsComplex && EIGEN_LOGICAL_XOR(RhsSelfAdjoint,ConjugateRhs),\n      EIGEN_LOGICAL_XOR(LhsSelfAdjoint,LhsStorageOrder==RowMajor) ? ColMajor : RowMajor,\n      LhsSelfAdjoint, NumTraits<Scalar>::IsComplex && EIGEN_LOGICAL_XOR(LhsSelfAdjoint,ConjugateLhs),\n      ColMajor>\n      ::run(cols, rows,  rhs, rhsStride,  lhs, lhsStride,  res, resStride,  alpha, blocking);\n  }\n};\n\ntemplate <typename Scalar, typename Index,\n          int LhsStorageOrder, bool ConjugateLhs,\n          int RhsStorageOrder, bool ConjugateRhs>\nstruct product_selfadjoint_matrix<Scalar,Index,LhsStorageOrder,true,ConjugateLhs, RhsStorageOrder,false,ConjugateRhs,ColMajor>\n{\n\n  static EIGEN_DONT_INLINE void run(\n    Index rows, Index cols,\n    const Scalar* _lhs, Index lhsStride,\n    const Scalar* _rhs, Index rhsStride,\n    Scalar* res,        Index resStride,\n    const Scalar& alpha, level3_blocking<Scalar,Scalar>& blocking);\n};\n\ntemplate <typename Scalar, typename Index,\n          int LhsStorageOrder, bool ConjugateLhs,\n          int RhsStorageOrder, bool ConjugateRhs>\nEIGEN_DONT_INLINE void product_selfadjoint_matrix<Scalar,Index,LhsStorageOrder,true,ConjugateLhs, RhsStorageOrder,false,ConjugateRhs,ColMajor>::run(\n    Index rows, Index cols,\n    const Scalar* _lhs, Index lhsStride,\n    const Scalar* _rhs, Index rhsStride,\n    Scalar* _res,        Index resStride,\n    const Scalar& alpha, level3_blocking<Scalar,Scalar>& blocking)\n  {\n    Index size = rows;\n\n    typedef gebp_traits<Scalar,Scalar> Traits;\n\n    typedef const_blas_data_mapper<Scalar, Index, LhsStorageOrder> LhsMapper;\n    typedef const_blas_data_mapper<Scalar, Index, (LhsStorageOrder == RowMajor) ? ColMajor : RowMajor> LhsTransposeMapper;\n    typedef const_blas_data_mapper<Scalar, Index, RhsStorageOrder> RhsMapper;\n    typedef blas_data_mapper<typename Traits::ResScalar, Index, ColMajor> ResMapper;\n    LhsMapper lhs(_lhs,lhsStride);\n    LhsTransposeMapper lhs_transpose(_lhs,lhsStride);\n    RhsMapper rhs(_rhs,rhsStride);\n    ResMapper res(_res, resStride);\n\n    Index kc = blocking.kc();                   // cache block size along the K direction\n    Index mc = (std::min)(rows,blocking.mc());  // cache block size along the M direction\n    // kc must be smaller than mc\n    kc = (std::min)(kc,mc);\n    std::size_t sizeA = kc*mc;\n    std::size_t sizeB = kc*cols;\n    ei_declare_aligned_stack_constructed_variable(Scalar, blockA, sizeA, blocking.blockA());\n    ei_declare_aligned_stack_constructed_variable(Scalar, blockB, sizeB, blocking.blockB());\n\n    gebp_kernel<Scalar, Scalar, Index, ResMapper, Traits::mr, Traits::nr, ConjugateLhs, ConjugateRhs> gebp_kernel;\n    symm_pack_lhs<Scalar, Index, Traits::mr, Traits::LhsProgress, LhsStorageOrder> pack_lhs;\n    gemm_pack_rhs<Scalar, Index, RhsMapper, Traits::nr,RhsStorageOrder> pack_rhs;\n    gemm_pack_lhs<Scalar, Index, LhsTransposeMapper, Traits::mr, Traits::LhsProgress, LhsStorageOrder==RowMajor?ColMajor:RowMajor, true> pack_lhs_transposed;\n\n    for(Index k2=0; k2<size; k2+=kc)\n    {\n      const Index actual_kc = (std::min)(k2+kc,size)-k2;\n\n      // we have selected one row panel of rhs and one column panel of lhs\n      // pack rhs's panel into a sequential chunk of memory\n      // and expand each coeff to a constant packet for further reuse\n      pack_rhs(blockB, rhs.getSubMapper(k2,0), actual_kc, cols);\n\n      // the select lhs's panel has to be split in three different parts:\n      //  1 - the transposed panel above the diagonal block => transposed packed copy\n      //  2 - the diagonal block => special packed copy\n      //  3 - the panel below the diagonal block => generic packed copy\n      for(Index i2=0; i2<k2; i2+=mc)\n      {\n        const Index actual_mc = (std::min)(i2+mc,k2)-i2;\n        // transposed packed copy\n        pack_lhs_transposed(blockA, lhs_transpose.getSubMapper(i2, k2), actual_kc, actual_mc);\n\n        gebp_kernel(res.getSubMapper(i2, 0), blockA, blockB, actual_mc, actual_kc, cols, alpha);\n      }\n      // the block diagonal\n      {\n        const Index actual_mc = (std::min)(k2+kc,size)-k2;\n        // symmetric packed copy\n        pack_lhs(blockA, &lhs(k2,k2), lhsStride, actual_kc, actual_mc);\n\n        gebp_kernel(res.getSubMapper(k2, 0), blockA, blockB, actual_mc, actual_kc, cols, alpha);\n      }\n\n      for(Index i2=k2+kc; i2<size; i2+=mc)\n      {\n        const Index actual_mc = (std::min)(i2+mc,size)-i2;\n        gemm_pack_lhs<Scalar, Index, LhsMapper, Traits::mr, Traits::LhsProgress, LhsStorageOrder,false>()\n          (blockA, lhs.getSubMapper(i2, k2), actual_kc, actual_mc);\n\n        gebp_kernel(res.getSubMapper(i2, 0), blockA, blockB, actual_mc, actual_kc, cols, alpha);\n      }\n    }\n  }\n\n// matrix * selfadjoint product\ntemplate <typename Scalar, typename Index,\n          int LhsStorageOrder, bool ConjugateLhs,\n          int RhsStorageOrder, bool ConjugateRhs>\nstruct product_selfadjoint_matrix<Scalar,Index,LhsStorageOrder,false,ConjugateLhs, RhsStorageOrder,true,ConjugateRhs,ColMajor>\n{\n\n  static EIGEN_DONT_INLINE void run(\n    Index rows, Index cols,\n    const Scalar* _lhs, Index lhsStride,\n    const Scalar* _rhs, Index rhsStride,\n    Scalar* res,        Index resStride,\n    const Scalar& alpha, level3_blocking<Scalar,Scalar>& blocking);\n};\n\ntemplate <typename Scalar, typename Index,\n          int LhsStorageOrder, bool ConjugateLhs,\n          int RhsStorageOrder, bool ConjugateRhs>\nEIGEN_DONT_INLINE void product_selfadjoint_matrix<Scalar,Index,LhsStorageOrder,false,ConjugateLhs, RhsStorageOrder,true,ConjugateRhs,ColMajor>::run(\n    Index rows, Index cols,\n    const Scalar* _lhs, Index lhsStride,\n    const Scalar* _rhs, Index rhsStride,\n    Scalar* _res,        Index resStride,\n    const Scalar& alpha, level3_blocking<Scalar,Scalar>& blocking)\n  {\n    Index size = cols;\n\n    typedef gebp_traits<Scalar,Scalar> Traits;\n\n    typedef const_blas_data_mapper<Scalar, Index, LhsStorageOrder> LhsMapper;\n    typedef blas_data_mapper<typename Traits::ResScalar, Index, ColMajor> ResMapper;\n    LhsMapper lhs(_lhs,lhsStride);\n    ResMapper res(_res,resStride);\n\n    Index kc = blocking.kc();                   // cache block size along the K direction\n    Index mc = (std::min)(rows,blocking.mc());  // cache block size along the M direction\n    std::size_t sizeA = kc*mc;\n    std::size_t sizeB = kc*cols;\n    ei_declare_aligned_stack_constructed_variable(Scalar, blockA, sizeA, blocking.blockA());\n    ei_declare_aligned_stack_constructed_variable(Scalar, blockB, sizeB, blocking.blockB());\n\n    gebp_kernel<Scalar, Scalar, Index, ResMapper, Traits::mr, Traits::nr, ConjugateLhs, ConjugateRhs> gebp_kernel;\n    gemm_pack_lhs<Scalar, Index, LhsMapper, Traits::mr, Traits::LhsProgress, LhsStorageOrder> pack_lhs;\n    symm_pack_rhs<Scalar, Index, Traits::nr,RhsStorageOrder> pack_rhs;\n\n    for(Index k2=0; k2<size; k2+=kc)\n    {\n      const Index actual_kc = (std::min)(k2+kc,size)-k2;\n\n      pack_rhs(blockB, _rhs, rhsStride, actual_kc, cols, k2);\n\n      // => GEPP\n      for(Index i2=0; i2<rows; i2+=mc)\n      {\n        const Index actual_mc = (std::min)(i2+mc,rows)-i2;\n        pack_lhs(blockA, lhs.getSubMapper(i2, k2), actual_kc, actual_mc);\n\n        gebp_kernel(res.getSubMapper(i2, 0), blockA, blockB, actual_mc, actual_kc, cols, alpha);\n      }\n    }\n  }\n\n} // end namespace internal\n\n/***************************************************************************\n* Wrapper to product_selfadjoint_matrix\n***************************************************************************/\n\nnamespace internal {\n  \ntemplate<typename Lhs, int LhsMode, typename Rhs, int RhsMode>\nstruct selfadjoint_product_impl<Lhs,LhsMode,false,Rhs,RhsMode,false>\n{\n  typedef typename Product<Lhs,Rhs>::Scalar Scalar;\n  \n  typedef internal::blas_traits<Lhs> LhsBlasTraits;\n  typedef typename LhsBlasTraits::DirectLinearAccessType ActualLhsType;\n  typedef internal::blas_traits<Rhs> RhsBlasTraits;\n  typedef typename RhsBlasTraits::DirectLinearAccessType ActualRhsType;\n  \n  enum {\n    LhsIsUpper = (LhsMode&(Upper|Lower))==Upper,\n    LhsIsSelfAdjoint = (LhsMode&SelfAdjoint)==SelfAdjoint,\n    RhsIsUpper = (RhsMode&(Upper|Lower))==Upper,\n    RhsIsSelfAdjoint = (RhsMode&SelfAdjoint)==SelfAdjoint\n  };\n  \n  template<typename Dest>\n  static void run(Dest &dst, const Lhs &a_lhs, const Rhs &a_rhs, const Scalar& alpha)\n  {\n    eigen_assert(dst.rows()==a_lhs.rows() && dst.cols()==a_rhs.cols());\n\n    typename internal::add_const_on_value_type<ActualLhsType>::type lhs = LhsBlasTraits::extract(a_lhs);\n    typename internal::add_const_on_value_type<ActualRhsType>::type rhs = RhsBlasTraits::extract(a_rhs);\n\n    Scalar actualAlpha = alpha * LhsBlasTraits::extractScalarFactor(a_lhs)\n                               * RhsBlasTraits::extractScalarFactor(a_rhs);\n\n    typedef internal::gemm_blocking_space<(Dest::Flags&RowMajorBit) ? RowMajor : ColMajor,Scalar,Scalar,\n              Lhs::MaxRowsAtCompileTime, Rhs::MaxColsAtCompileTime, Lhs::MaxColsAtCompileTime,1> BlockingType;\n\n    BlockingType blocking(lhs.rows(), rhs.cols(), lhs.cols(), 1, false);\n\n    internal::product_selfadjoint_matrix<Scalar, Index,\n      EIGEN_LOGICAL_XOR(LhsIsUpper,internal::traits<Lhs>::Flags &RowMajorBit) ? RowMajor : ColMajor, LhsIsSelfAdjoint,\n      NumTraits<Scalar>::IsComplex && EIGEN_LOGICAL_XOR(LhsIsUpper,bool(LhsBlasTraits::NeedToConjugate)),\n      EIGEN_LOGICAL_XOR(RhsIsUpper,internal::traits<Rhs>::Flags &RowMajorBit) ? RowMajor : ColMajor, RhsIsSelfAdjoint,\n      NumTraits<Scalar>::IsComplex && EIGEN_LOGICAL_XOR(RhsIsUpper,bool(RhsBlasTraits::NeedToConjugate)),\n      internal::traits<Dest>::Flags&RowMajorBit  ? RowMajor : ColMajor>\n      ::run(\n        lhs.rows(), rhs.cols(),                 // sizes\n        &lhs.coeffRef(0,0), lhs.outerStride(),  // lhs info\n        &rhs.coeffRef(0,0), rhs.outerStride(),  // rhs info\n        &dst.coeffRef(0,0), dst.outerStride(),  // result info\n        actualAlpha, blocking                   // alpha\n      );\n  }\n};\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_SELFADJOINT_MATRIX_MATRIX_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/products/SelfadjointMatrixMatrix_BLAS.h",
    "content": "/*\n Copyright (c) 2011, Intel Corporation. All rights reserved.\n\n Redistribution and use in source and binary forms, with or without modification,\n are permitted provided that the following conditions are met:\n\n * Redistributions of source code must retain the above copyright notice, this\n   list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright notice,\n   this list of conditions and the following disclaimer in the documentation\n   and/or other materials provided with the distribution.\n * Neither the name of Intel Corporation nor the names of its contributors may\n   be used to endorse or promote products derived from this software without\n   specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n//\n ********************************************************************************\n *   Content : Eigen bindings to BLAS F77\n *   Self adjoint matrix * matrix product functionality based on ?SYMM/?HEMM.\n ********************************************************************************\n*/\n\n#ifndef EIGEN_SELFADJOINT_MATRIX_MATRIX_BLAS_H\n#define EIGEN_SELFADJOINT_MATRIX_MATRIX_BLAS_H\n\nnamespace Eigen { \n\nnamespace internal {\n\n\n/* Optimized selfadjoint matrix * matrix (?SYMM/?HEMM) product */\n\n#define EIGEN_BLAS_SYMM_L(EIGTYPE, BLASTYPE, EIGPREFIX, BLASPREFIX) \\\ntemplate <typename Index, \\\n          int LhsStorageOrder, bool ConjugateLhs, \\\n          int RhsStorageOrder, bool ConjugateRhs> \\\nstruct product_selfadjoint_matrix<EIGTYPE,Index,LhsStorageOrder,true,ConjugateLhs,RhsStorageOrder,false,ConjugateRhs,ColMajor> \\\n{\\\n\\\n  static void run( \\\n    Index rows, Index cols, \\\n    const EIGTYPE* _lhs, Index lhsStride, \\\n    const EIGTYPE* _rhs, Index rhsStride, \\\n    EIGTYPE* res,        Index resStride, \\\n    EIGTYPE alpha, level3_blocking<EIGTYPE, EIGTYPE>& /*blocking*/) \\\n  { \\\n    char side='L', uplo='L'; \\\n    BlasIndex m, n, lda, ldb, ldc; \\\n    const EIGTYPE *a, *b; \\\n    EIGTYPE beta(1); \\\n    MatrixX##EIGPREFIX b_tmp; \\\n\\\n/* Set transpose options */ \\\n/* Set m, n, k */ \\\n    m = convert_index<BlasIndex>(rows);  \\\n    n = convert_index<BlasIndex>(cols);  \\\n\\\n/* Set lda, ldb, ldc */ \\\n    lda = convert_index<BlasIndex>(lhsStride); \\\n    ldb = convert_index<BlasIndex>(rhsStride); \\\n    ldc = convert_index<BlasIndex>(resStride); \\\n\\\n/* Set a, b, c */ \\\n    if (LhsStorageOrder==RowMajor) uplo='U'; \\\n    a = _lhs; \\\n\\\n    if (RhsStorageOrder==RowMajor) { \\\n      Map<const MatrixX##EIGPREFIX, 0, OuterStride<> > rhs(_rhs,n,m,OuterStride<>(rhsStride)); \\\n      b_tmp = rhs.adjoint(); \\\n      b = b_tmp.data(); \\\n      ldb = convert_index<BlasIndex>(b_tmp.outerStride()); \\\n    } else b = _rhs; \\\n\\\n    BLASPREFIX##symm_(&side, &uplo, &m, &n, &numext::real_ref(alpha), (const BLASTYPE*)a, &lda, (const BLASTYPE*)b, &ldb, &numext::real_ref(beta), (BLASTYPE*)res, &ldc); \\\n\\\n  } \\\n};\n\n\n#define EIGEN_BLAS_HEMM_L(EIGTYPE, BLASTYPE, EIGPREFIX, BLASPREFIX) \\\ntemplate <typename Index, \\\n          int LhsStorageOrder, bool ConjugateLhs, \\\n          int RhsStorageOrder, bool ConjugateRhs> \\\nstruct product_selfadjoint_matrix<EIGTYPE,Index,LhsStorageOrder,true,ConjugateLhs,RhsStorageOrder,false,ConjugateRhs,ColMajor> \\\n{\\\n  static void run( \\\n    Index rows, Index cols, \\\n    const EIGTYPE* _lhs, Index lhsStride, \\\n    const EIGTYPE* _rhs, Index rhsStride, \\\n    EIGTYPE* res,        Index resStride, \\\n    EIGTYPE alpha, level3_blocking<EIGTYPE, EIGTYPE>& /*blocking*/) \\\n  { \\\n    char side='L', uplo='L'; \\\n    BlasIndex m, n, lda, ldb, ldc; \\\n    const EIGTYPE *a, *b; \\\n    EIGTYPE beta(1); \\\n    MatrixX##EIGPREFIX b_tmp; \\\n    Matrix<EIGTYPE, Dynamic, Dynamic, LhsStorageOrder> a_tmp; \\\n\\\n/* Set transpose options */ \\\n/* Set m, n, k */ \\\n    m = convert_index<BlasIndex>(rows); \\\n    n = convert_index<BlasIndex>(cols); \\\n\\\n/* Set lda, ldb, ldc */ \\\n    lda = convert_index<BlasIndex>(lhsStride); \\\n    ldb = convert_index<BlasIndex>(rhsStride); \\\n    ldc = convert_index<BlasIndex>(resStride); \\\n\\\n/* Set a, b, c */ \\\n    if (((LhsStorageOrder==ColMajor) && ConjugateLhs) || ((LhsStorageOrder==RowMajor) && (!ConjugateLhs))) { \\\n      Map<const Matrix<EIGTYPE, Dynamic, Dynamic, LhsStorageOrder>, 0, OuterStride<> > lhs(_lhs,m,m,OuterStride<>(lhsStride)); \\\n      a_tmp = lhs.conjugate(); \\\n      a = a_tmp.data(); \\\n      lda = convert_index<BlasIndex>(a_tmp.outerStride()); \\\n    } else a = _lhs; \\\n    if (LhsStorageOrder==RowMajor) uplo='U'; \\\n\\\n    if (RhsStorageOrder==ColMajor && (!ConjugateRhs)) { \\\n       b = _rhs; } \\\n    else { \\\n      if (RhsStorageOrder==ColMajor && ConjugateRhs) { \\\n        Map<const MatrixX##EIGPREFIX, 0, OuterStride<> > rhs(_rhs,m,n,OuterStride<>(rhsStride)); \\\n        b_tmp = rhs.conjugate(); \\\n      } else \\\n      if (ConjugateRhs) { \\\n        Map<const MatrixX##EIGPREFIX, 0, OuterStride<> > rhs(_rhs,n,m,OuterStride<>(rhsStride)); \\\n        b_tmp = rhs.adjoint(); \\\n      } else { \\\n        Map<const MatrixX##EIGPREFIX, 0, OuterStride<> > rhs(_rhs,n,m,OuterStride<>(rhsStride)); \\\n        b_tmp = rhs.transpose(); \\\n      } \\\n      b = b_tmp.data(); \\\n      ldb = convert_index<BlasIndex>(b_tmp.outerStride()); \\\n    } \\\n\\\n    BLASPREFIX##hemm_(&side, &uplo, &m, &n, &numext::real_ref(alpha), (const BLASTYPE*)a, &lda, (const BLASTYPE*)b, &ldb, &numext::real_ref(beta), (BLASTYPE*)res, &ldc); \\\n\\\n  } \\\n};\n\nEIGEN_BLAS_SYMM_L(double, double, d, d)\nEIGEN_BLAS_SYMM_L(float, float, f, s)\nEIGEN_BLAS_HEMM_L(dcomplex, double, cd, z)\nEIGEN_BLAS_HEMM_L(scomplex, float, cf, c)\n\n\n/* Optimized matrix * selfadjoint matrix (?SYMM/?HEMM) product */\n\n#define EIGEN_BLAS_SYMM_R(EIGTYPE, BLASTYPE, EIGPREFIX, BLASPREFIX) \\\ntemplate <typename Index, \\\n          int LhsStorageOrder, bool ConjugateLhs, \\\n          int RhsStorageOrder, bool ConjugateRhs> \\\nstruct product_selfadjoint_matrix<EIGTYPE,Index,LhsStorageOrder,false,ConjugateLhs,RhsStorageOrder,true,ConjugateRhs,ColMajor> \\\n{\\\n\\\n  static void run( \\\n    Index rows, Index cols, \\\n    const EIGTYPE* _lhs, Index lhsStride, \\\n    const EIGTYPE* _rhs, Index rhsStride, \\\n    EIGTYPE* res,        Index resStride, \\\n    EIGTYPE alpha, level3_blocking<EIGTYPE, EIGTYPE>& /*blocking*/) \\\n  { \\\n    char side='R', uplo='L'; \\\n    BlasIndex m, n, lda, ldb, ldc; \\\n    const EIGTYPE *a, *b; \\\n    EIGTYPE beta(1); \\\n    MatrixX##EIGPREFIX b_tmp; \\\n\\\n/* Set m, n, k */ \\\n    m = convert_index<BlasIndex>(rows);  \\\n    n = convert_index<BlasIndex>(cols);  \\\n\\\n/* Set lda, ldb, ldc */ \\\n    lda = convert_index<BlasIndex>(rhsStride); \\\n    ldb = convert_index<BlasIndex>(lhsStride); \\\n    ldc = convert_index<BlasIndex>(resStride); \\\n\\\n/* Set a, b, c */ \\\n    if (RhsStorageOrder==RowMajor) uplo='U'; \\\n    a = _rhs; \\\n\\\n    if (LhsStorageOrder==RowMajor) { \\\n      Map<const MatrixX##EIGPREFIX, 0, OuterStride<> > lhs(_lhs,n,m,OuterStride<>(rhsStride)); \\\n      b_tmp = lhs.adjoint(); \\\n      b = b_tmp.data(); \\\n      ldb = convert_index<BlasIndex>(b_tmp.outerStride()); \\\n    } else b = _lhs; \\\n\\\n    BLASPREFIX##symm_(&side, &uplo, &m, &n, &numext::real_ref(alpha), (const BLASTYPE*)a, &lda, (const BLASTYPE*)b, &ldb, &numext::real_ref(beta), (BLASTYPE*)res, &ldc); \\\n\\\n  } \\\n};\n\n\n#define EIGEN_BLAS_HEMM_R(EIGTYPE, BLASTYPE, EIGPREFIX, BLASPREFIX) \\\ntemplate <typename Index, \\\n          int LhsStorageOrder, bool ConjugateLhs, \\\n          int RhsStorageOrder, bool ConjugateRhs> \\\nstruct product_selfadjoint_matrix<EIGTYPE,Index,LhsStorageOrder,false,ConjugateLhs,RhsStorageOrder,true,ConjugateRhs,ColMajor> \\\n{\\\n  static void run( \\\n    Index rows, Index cols, \\\n    const EIGTYPE* _lhs, Index lhsStride, \\\n    const EIGTYPE* _rhs, Index rhsStride, \\\n    EIGTYPE* res,        Index resStride, \\\n    EIGTYPE alpha, level3_blocking<EIGTYPE, EIGTYPE>& /*blocking*/) \\\n  { \\\n    char side='R', uplo='L'; \\\n    BlasIndex m, n, lda, ldb, ldc; \\\n    const EIGTYPE *a, *b; \\\n    EIGTYPE beta(1); \\\n    MatrixX##EIGPREFIX b_tmp; \\\n    Matrix<EIGTYPE, Dynamic, Dynamic, RhsStorageOrder> a_tmp; \\\n\\\n/* Set m, n, k */ \\\n    m = convert_index<BlasIndex>(rows); \\\n    n = convert_index<BlasIndex>(cols); \\\n\\\n/* Set lda, ldb, ldc */ \\\n    lda = convert_index<BlasIndex>(rhsStride); \\\n    ldb = convert_index<BlasIndex>(lhsStride); \\\n    ldc = convert_index<BlasIndex>(resStride); \\\n\\\n/* Set a, b, c */ \\\n    if (((RhsStorageOrder==ColMajor) && ConjugateRhs) || ((RhsStorageOrder==RowMajor) && (!ConjugateRhs))) { \\\n      Map<const Matrix<EIGTYPE, Dynamic, Dynamic, RhsStorageOrder>, 0, OuterStride<> > rhs(_rhs,n,n,OuterStride<>(rhsStride)); \\\n      a_tmp = rhs.conjugate(); \\\n      a = a_tmp.data(); \\\n      lda = convert_index<BlasIndex>(a_tmp.outerStride()); \\\n    } else a = _rhs; \\\n    if (RhsStorageOrder==RowMajor) uplo='U'; \\\n\\\n    if (LhsStorageOrder==ColMajor && (!ConjugateLhs)) { \\\n       b = _lhs; } \\\n    else { \\\n      if (LhsStorageOrder==ColMajor && ConjugateLhs) { \\\n        Map<const MatrixX##EIGPREFIX, 0, OuterStride<> > lhs(_lhs,m,n,OuterStride<>(lhsStride)); \\\n        b_tmp = lhs.conjugate(); \\\n      } else \\\n      if (ConjugateLhs) { \\\n        Map<const MatrixX##EIGPREFIX, 0, OuterStride<> > lhs(_lhs,n,m,OuterStride<>(lhsStride)); \\\n        b_tmp = lhs.adjoint(); \\\n      } else { \\\n        Map<const MatrixX##EIGPREFIX, 0, OuterStride<> > lhs(_lhs,n,m,OuterStride<>(lhsStride)); \\\n        b_tmp = lhs.transpose(); \\\n      } \\\n      b = b_tmp.data(); \\\n      ldb = convert_index<BlasIndex>(b_tmp.outerStride()); \\\n    } \\\n\\\n    BLASPREFIX##hemm_(&side, &uplo, &m, &n, &numext::real_ref(alpha), (const BLASTYPE*)a, &lda, (const BLASTYPE*)b, &ldb, &numext::real_ref(beta), (BLASTYPE*)res, &ldc); \\\n  } \\\n};\n\nEIGEN_BLAS_SYMM_R(double, double, d, d)\nEIGEN_BLAS_SYMM_R(float, float, f, s)\nEIGEN_BLAS_HEMM_R(dcomplex, double, cd, z)\nEIGEN_BLAS_HEMM_R(scomplex, float, cf, c)\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_SELFADJOINT_MATRIX_MATRIX_BLAS_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/products/SelfadjointMatrixVector.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SELFADJOINT_MATRIX_VECTOR_H\n#define EIGEN_SELFADJOINT_MATRIX_VECTOR_H\n\nnamespace Eigen { \n\nnamespace internal {\n\n/* Optimized selfadjoint matrix * vector product:\n * This algorithm processes 2 columns at onces that allows to both reduce\n * the number of load/stores of the result by a factor 2 and to reduce\n * the instruction dependency.\n */\n\ntemplate<typename Scalar, typename Index, int StorageOrder, int UpLo, bool ConjugateLhs, bool ConjugateRhs, int Version=Specialized>\nstruct selfadjoint_matrix_vector_product;\n\ntemplate<typename Scalar, typename Index, int StorageOrder, int UpLo, bool ConjugateLhs, bool ConjugateRhs, int Version>\nstruct selfadjoint_matrix_vector_product\n\n{\nstatic EIGEN_DONT_INLINE void run(\n  Index size,\n  const Scalar*  lhs, Index lhsStride,\n  const Scalar*  rhs,\n  Scalar* res,\n  Scalar alpha);\n};\n\ntemplate<typename Scalar, typename Index, int StorageOrder, int UpLo, bool ConjugateLhs, bool ConjugateRhs, int Version>\nEIGEN_DONT_INLINE void selfadjoint_matrix_vector_product<Scalar,Index,StorageOrder,UpLo,ConjugateLhs,ConjugateRhs,Version>::run(\n  Index size,\n  const Scalar*  lhs, Index lhsStride,\n  const Scalar*  rhs,\n  Scalar* res,\n  Scalar alpha)\n{\n  typedef typename packet_traits<Scalar>::type Packet;\n  typedef typename NumTraits<Scalar>::Real RealScalar;\n  const Index PacketSize = sizeof(Packet)/sizeof(Scalar);\n\n  enum {\n    IsRowMajor = StorageOrder==RowMajor ? 1 : 0,\n    IsLower = UpLo == Lower ? 1 : 0,\n    FirstTriangular = IsRowMajor == IsLower\n  };\n\n  conj_helper<Scalar,Scalar,NumTraits<Scalar>::IsComplex && EIGEN_LOGICAL_XOR(ConjugateLhs,  IsRowMajor), ConjugateRhs> cj0;\n  conj_helper<Scalar,Scalar,NumTraits<Scalar>::IsComplex && EIGEN_LOGICAL_XOR(ConjugateLhs, !IsRowMajor), ConjugateRhs> cj1;\n  conj_helper<RealScalar,Scalar,false, ConjugateRhs> cjd;\n\n  conj_helper<Packet,Packet,NumTraits<Scalar>::IsComplex && EIGEN_LOGICAL_XOR(ConjugateLhs,  IsRowMajor), ConjugateRhs> pcj0;\n  conj_helper<Packet,Packet,NumTraits<Scalar>::IsComplex && EIGEN_LOGICAL_XOR(ConjugateLhs, !IsRowMajor), ConjugateRhs> pcj1;\n\n  Scalar cjAlpha = ConjugateRhs ? numext::conj(alpha) : alpha;\n\n\n  Index bound = (std::max)(Index(0),size-8) & 0xfffffffe;\n  if (FirstTriangular)\n    bound = size - bound;\n\n  for (Index j=FirstTriangular ? bound : 0;\n       j<(FirstTriangular ? size : bound);j+=2)\n  {\n    const Scalar* EIGEN_RESTRICT A0 = lhs + j*lhsStride;\n    const Scalar* EIGEN_RESTRICT A1 = lhs + (j+1)*lhsStride;\n\n    Scalar t0 = cjAlpha * rhs[j];\n    Packet ptmp0 = pset1<Packet>(t0);\n    Scalar t1 = cjAlpha * rhs[j+1];\n    Packet ptmp1 = pset1<Packet>(t1);\n\n    Scalar t2(0);\n    Packet ptmp2 = pset1<Packet>(t2);\n    Scalar t3(0);\n    Packet ptmp3 = pset1<Packet>(t3);\n\n    size_t starti = FirstTriangular ? 0 : j+2;\n    size_t endi   = FirstTriangular ? j : size;\n    size_t alignedStart = (starti) + internal::first_default_aligned(&res[starti], endi-starti);\n    size_t alignedEnd = alignedStart + ((endi-alignedStart)/(PacketSize))*(PacketSize);\n\n    res[j]   += cjd.pmul(numext::real(A0[j]), t0);\n    res[j+1] += cjd.pmul(numext::real(A1[j+1]), t1);\n    if(FirstTriangular)\n    {\n      res[j]   += cj0.pmul(A1[j],   t1);\n      t3       += cj1.pmul(A1[j],   rhs[j]);\n    }\n    else\n    {\n      res[j+1] += cj0.pmul(A0[j+1],t0);\n      t2 += cj1.pmul(A0[j+1], rhs[j+1]);\n    }\n\n    for (size_t i=starti; i<alignedStart; ++i)\n    {\n      res[i] += cj0.pmul(A0[i], t0) + cj0.pmul(A1[i],t1);\n      t2 += cj1.pmul(A0[i], rhs[i]);\n      t3 += cj1.pmul(A1[i], rhs[i]);\n    }\n    // Yes this an optimization for gcc 4.3 and 4.4 (=> huge speed up)\n    // gcc 4.2 does this optimization automatically.\n    const Scalar* EIGEN_RESTRICT a0It  = A0  + alignedStart;\n    const Scalar* EIGEN_RESTRICT a1It  = A1  + alignedStart;\n    const Scalar* EIGEN_RESTRICT rhsIt = rhs + alignedStart;\n          Scalar* EIGEN_RESTRICT resIt = res + alignedStart;\n    for (size_t i=alignedStart; i<alignedEnd; i+=PacketSize)\n    {\n      Packet A0i = ploadu<Packet>(a0It);  a0It  += PacketSize;\n      Packet A1i = ploadu<Packet>(a1It);  a1It  += PacketSize;\n      Packet Bi  = ploadu<Packet>(rhsIt); rhsIt += PacketSize; // FIXME should be aligned in most cases\n      Packet Xi  = pload <Packet>(resIt);\n\n      Xi    = pcj0.pmadd(A0i,ptmp0, pcj0.pmadd(A1i,ptmp1,Xi));\n      ptmp2 = pcj1.pmadd(A0i,  Bi, ptmp2);\n      ptmp3 = pcj1.pmadd(A1i,  Bi, ptmp3);\n      pstore(resIt,Xi); resIt += PacketSize;\n    }\n    for (size_t i=alignedEnd; i<endi; i++)\n    {\n      res[i] += cj0.pmul(A0[i], t0) + cj0.pmul(A1[i],t1);\n      t2 += cj1.pmul(A0[i], rhs[i]);\n      t3 += cj1.pmul(A1[i], rhs[i]);\n    }\n\n    res[j]   += alpha * (t2 + predux(ptmp2));\n    res[j+1] += alpha * (t3 + predux(ptmp3));\n  }\n  for (Index j=FirstTriangular ? 0 : bound;j<(FirstTriangular ? bound : size);j++)\n  {\n    const Scalar* EIGEN_RESTRICT A0 = lhs + j*lhsStride;\n\n    Scalar t1 = cjAlpha * rhs[j];\n    Scalar t2(0);\n    res[j] += cjd.pmul(numext::real(A0[j]), t1);\n    for (Index i=FirstTriangular ? 0 : j+1; i<(FirstTriangular ? j : size); i++)\n    {\n      res[i] += cj0.pmul(A0[i], t1);\n      t2 += cj1.pmul(A0[i], rhs[i]);\n    }\n    res[j] += alpha * t2;\n  }\n}\n\n} // end namespace internal \n\n/***************************************************************************\n* Wrapper to product_selfadjoint_vector\n***************************************************************************/\n\nnamespace internal {\n\ntemplate<typename Lhs, int LhsMode, typename Rhs>\nstruct selfadjoint_product_impl<Lhs,LhsMode,false,Rhs,0,true>\n{\n  typedef typename Product<Lhs,Rhs>::Scalar Scalar;\n  \n  typedef internal::blas_traits<Lhs> LhsBlasTraits;\n  typedef typename LhsBlasTraits::DirectLinearAccessType ActualLhsType;\n  typedef typename internal::remove_all<ActualLhsType>::type ActualLhsTypeCleaned;\n  \n  typedef internal::blas_traits<Rhs> RhsBlasTraits;\n  typedef typename RhsBlasTraits::DirectLinearAccessType ActualRhsType;\n  typedef typename internal::remove_all<ActualRhsType>::type ActualRhsTypeCleaned;\n\n  enum { LhsUpLo = LhsMode&(Upper|Lower) };\n\n  template<typename Dest>\n  static void run(Dest& dest, const Lhs &a_lhs, const Rhs &a_rhs, const Scalar& alpha)\n  {\n    typedef typename Dest::Scalar ResScalar;\n    typedef typename Rhs::Scalar RhsScalar;\n    typedef Map<Matrix<ResScalar,Dynamic,1>, EIGEN_PLAIN_ENUM_MIN(AlignedMax,internal::packet_traits<ResScalar>::size)> MappedDest;\n    \n    eigen_assert(dest.rows()==a_lhs.rows() && dest.cols()==a_rhs.cols());\n\n    typename internal::add_const_on_value_type<ActualLhsType>::type lhs = LhsBlasTraits::extract(a_lhs);\n    typename internal::add_const_on_value_type<ActualRhsType>::type rhs = RhsBlasTraits::extract(a_rhs);\n\n    Scalar actualAlpha = alpha * LhsBlasTraits::extractScalarFactor(a_lhs)\n                               * RhsBlasTraits::extractScalarFactor(a_rhs);\n\n    enum {\n      EvalToDest = (Dest::InnerStrideAtCompileTime==1),\n      UseRhs = (ActualRhsTypeCleaned::InnerStrideAtCompileTime==1)\n    };\n    \n    internal::gemv_static_vector_if<ResScalar,Dest::SizeAtCompileTime,Dest::MaxSizeAtCompileTime,!EvalToDest> static_dest;\n    internal::gemv_static_vector_if<RhsScalar,ActualRhsTypeCleaned::SizeAtCompileTime,ActualRhsTypeCleaned::MaxSizeAtCompileTime,!UseRhs> static_rhs;\n\n    ei_declare_aligned_stack_constructed_variable(ResScalar,actualDestPtr,dest.size(),\n                                                  EvalToDest ? dest.data() : static_dest.data());\n                                                  \n    ei_declare_aligned_stack_constructed_variable(RhsScalar,actualRhsPtr,rhs.size(),\n        UseRhs ? const_cast<RhsScalar*>(rhs.data()) : static_rhs.data());\n    \n    if(!EvalToDest)\n    {\n      #ifdef EIGEN_DENSE_STORAGE_CTOR_PLUGIN\n      Index size = dest.size();\n      EIGEN_DENSE_STORAGE_CTOR_PLUGIN\n      #endif\n      MappedDest(actualDestPtr, dest.size()) = dest;\n    }\n      \n    if(!UseRhs)\n    {\n      #ifdef EIGEN_DENSE_STORAGE_CTOR_PLUGIN\n      Index size = rhs.size();\n      EIGEN_DENSE_STORAGE_CTOR_PLUGIN\n      #endif\n      Map<typename ActualRhsTypeCleaned::PlainObject>(actualRhsPtr, rhs.size()) = rhs;\n    }\n      \n      \n    internal::selfadjoint_matrix_vector_product<Scalar, Index, (internal::traits<ActualLhsTypeCleaned>::Flags&RowMajorBit) ? RowMajor : ColMajor,\n                                                int(LhsUpLo), bool(LhsBlasTraits::NeedToConjugate), bool(RhsBlasTraits::NeedToConjugate)>::run\n      (\n        lhs.rows(),                             // size\n        &lhs.coeffRef(0,0),  lhs.outerStride(), // lhs info\n        actualRhsPtr,                           // rhs info\n        actualDestPtr,                          // result info\n        actualAlpha                             // scale factor\n      );\n    \n    if(!EvalToDest)\n      dest = MappedDest(actualDestPtr, dest.size());\n  }\n};\n\ntemplate<typename Lhs, typename Rhs, int RhsMode>\nstruct selfadjoint_product_impl<Lhs,0,true,Rhs,RhsMode,false>\n{\n  typedef typename Product<Lhs,Rhs>::Scalar Scalar;\n  enum { RhsUpLo = RhsMode&(Upper|Lower)  };\n\n  template<typename Dest>\n  static void run(Dest& dest, const Lhs &a_lhs, const Rhs &a_rhs, const Scalar& alpha)\n  {\n    // let's simply transpose the product\n    Transpose<Dest> destT(dest);\n    selfadjoint_product_impl<Transpose<const Rhs>, int(RhsUpLo)==Upper ? Lower : Upper, false,\n                             Transpose<const Lhs>, 0, true>::run(destT, a_rhs.transpose(), a_lhs.transpose(), alpha);\n  }\n};\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_SELFADJOINT_MATRIX_VECTOR_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/products/SelfadjointMatrixVector_BLAS.h",
    "content": "/*\n Copyright (c) 2011, Intel Corporation. All rights reserved.\n\n Redistribution and use in source and binary forms, with or without modification,\n are permitted provided that the following conditions are met:\n\n * Redistributions of source code must retain the above copyright notice, this\n   list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright notice,\n   this list of conditions and the following disclaimer in the documentation\n   and/or other materials provided with the distribution.\n * Neither the name of Intel Corporation nor the names of its contributors may\n   be used to endorse or promote products derived from this software without\n   specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n ********************************************************************************\n *   Content : Eigen bindings to BLAS F77\n *   Selfadjoint matrix-vector product functionality based on ?SYMV/HEMV.\n ********************************************************************************\n*/\n\n#ifndef EIGEN_SELFADJOINT_MATRIX_VECTOR_BLAS_H\n#define EIGEN_SELFADJOINT_MATRIX_VECTOR_BLAS_H\n\nnamespace Eigen { \n\nnamespace internal {\n\n/**********************************************************************\n* This file implements selfadjoint matrix-vector multiplication using BLAS\n**********************************************************************/\n\n// symv/hemv specialization\n\ntemplate<typename Scalar, typename Index, int StorageOrder, int UpLo, bool ConjugateLhs, bool ConjugateRhs>\nstruct selfadjoint_matrix_vector_product_symv :\n  selfadjoint_matrix_vector_product<Scalar,Index,StorageOrder,UpLo,ConjugateLhs,ConjugateRhs,BuiltIn> {};\n\n#define EIGEN_BLAS_SYMV_SPECIALIZE(Scalar) \\\ntemplate<typename Index, int StorageOrder, int UpLo, bool ConjugateLhs, bool ConjugateRhs> \\\nstruct selfadjoint_matrix_vector_product<Scalar,Index,StorageOrder,UpLo,ConjugateLhs,ConjugateRhs,Specialized> { \\\nstatic void run( \\\n  Index size, const Scalar*  lhs, Index lhsStride, \\\n  const Scalar* _rhs, Scalar* res, Scalar alpha) { \\\n    enum {\\\n      IsColMajor = StorageOrder==ColMajor \\\n    }; \\\n    if (IsColMajor == ConjugateLhs) {\\\n      selfadjoint_matrix_vector_product<Scalar,Index,StorageOrder,UpLo,ConjugateLhs,ConjugateRhs,BuiltIn>::run( \\\n        size, lhs, lhsStride, _rhs, res, alpha);  \\\n    } else {\\\n      selfadjoint_matrix_vector_product_symv<Scalar,Index,StorageOrder,UpLo,ConjugateLhs,ConjugateRhs>::run( \\\n        size, lhs, lhsStride, _rhs, res, alpha);  \\\n    }\\\n  } \\\n}; \\\n\nEIGEN_BLAS_SYMV_SPECIALIZE(double)\nEIGEN_BLAS_SYMV_SPECIALIZE(float)\nEIGEN_BLAS_SYMV_SPECIALIZE(dcomplex)\nEIGEN_BLAS_SYMV_SPECIALIZE(scomplex)\n\n#define EIGEN_BLAS_SYMV_SPECIALIZATION(EIGTYPE,BLASTYPE,BLASFUNC) \\\ntemplate<typename Index, int StorageOrder, int UpLo, bool ConjugateLhs, bool ConjugateRhs> \\\nstruct selfadjoint_matrix_vector_product_symv<EIGTYPE,Index,StorageOrder,UpLo,ConjugateLhs,ConjugateRhs> \\\n{ \\\ntypedef Matrix<EIGTYPE,Dynamic,1,ColMajor> SYMVVector;\\\n\\\nstatic void run( \\\nIndex size, const EIGTYPE*  lhs, Index lhsStride, \\\nconst EIGTYPE* _rhs, EIGTYPE* res, EIGTYPE alpha) \\\n{ \\\n  enum {\\\n    IsRowMajor = StorageOrder==RowMajor ? 1 : 0, \\\n    IsLower = UpLo == Lower ? 1 : 0 \\\n  }; \\\n  BlasIndex n=convert_index<BlasIndex>(size), lda=convert_index<BlasIndex>(lhsStride), incx=1, incy=1; \\\n  EIGTYPE beta(1); \\\n  const EIGTYPE *x_ptr; \\\n  char uplo=(IsRowMajor) ? (IsLower ? 'U' : 'L') : (IsLower ? 'L' : 'U'); \\\n  SYMVVector x_tmp; \\\n  if (ConjugateRhs) { \\\n    Map<const SYMVVector, 0 > map_x(_rhs,size,1); \\\n    x_tmp=map_x.conjugate(); \\\n    x_ptr=x_tmp.data(); \\\n  } else x_ptr=_rhs; \\\n  BLASFUNC(&uplo, &n, &numext::real_ref(alpha), (const BLASTYPE*)lhs, &lda, (const BLASTYPE*)x_ptr, &incx, &numext::real_ref(beta), (BLASTYPE*)res, &incy); \\\n}\\\n};\n\nEIGEN_BLAS_SYMV_SPECIALIZATION(double,   double, dsymv_)\nEIGEN_BLAS_SYMV_SPECIALIZATION(float,    float,  ssymv_)\nEIGEN_BLAS_SYMV_SPECIALIZATION(dcomplex, double, zhemv_)\nEIGEN_BLAS_SYMV_SPECIALIZATION(scomplex, float,  chemv_)\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_SELFADJOINT_MATRIX_VECTOR_BLAS_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/products/SelfadjointProduct.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SELFADJOINT_PRODUCT_H\n#define EIGEN_SELFADJOINT_PRODUCT_H\n\n/**********************************************************************\n* This file implements a self adjoint product: C += A A^T updating only\n* half of the selfadjoint matrix C.\n* It corresponds to the level 3 SYRK and level 2 SYR Blas routines.\n**********************************************************************/\n\nnamespace Eigen { \n\n\ntemplate<typename Scalar, typename Index, int UpLo, bool ConjLhs, bool ConjRhs>\nstruct selfadjoint_rank1_update<Scalar,Index,ColMajor,UpLo,ConjLhs,ConjRhs>\n{\n  static void run(Index size, Scalar* mat, Index stride, const Scalar* vecX, const Scalar* vecY, const Scalar& alpha)\n  {\n    internal::conj_if<ConjRhs> cj;\n    typedef Map<const Matrix<Scalar,Dynamic,1> > OtherMap;\n    typedef typename internal::conditional<ConjLhs,typename OtherMap::ConjugateReturnType,const OtherMap&>::type ConjLhsType;\n    for (Index i=0; i<size; ++i)\n    {\n      Map<Matrix<Scalar,Dynamic,1> >(mat+stride*i+(UpLo==Lower ? i : 0), (UpLo==Lower ? size-i : (i+1)))\n          += (alpha * cj(vecY[i])) * ConjLhsType(OtherMap(vecX+(UpLo==Lower ? i : 0),UpLo==Lower ? size-i : (i+1)));\n    }\n  }\n};\n\ntemplate<typename Scalar, typename Index, int UpLo, bool ConjLhs, bool ConjRhs>\nstruct selfadjoint_rank1_update<Scalar,Index,RowMajor,UpLo,ConjLhs,ConjRhs>\n{\n  static void run(Index size, Scalar* mat, Index stride, const Scalar* vecX, const Scalar* vecY, const Scalar& alpha)\n  {\n    selfadjoint_rank1_update<Scalar,Index,ColMajor,UpLo==Lower?Upper:Lower,ConjRhs,ConjLhs>::run(size,mat,stride,vecY,vecX,alpha);\n  }\n};\n\ntemplate<typename MatrixType, typename OtherType, int UpLo, bool OtherIsVector = OtherType::IsVectorAtCompileTime>\nstruct selfadjoint_product_selector;\n\ntemplate<typename MatrixType, typename OtherType, int UpLo>\nstruct selfadjoint_product_selector<MatrixType,OtherType,UpLo,true>\n{\n  static void run(MatrixType& mat, const OtherType& other, const typename MatrixType::Scalar& alpha)\n  {\n    typedef typename MatrixType::Scalar Scalar;\n    typedef internal::blas_traits<OtherType> OtherBlasTraits;\n    typedef typename OtherBlasTraits::DirectLinearAccessType ActualOtherType;\n    typedef typename internal::remove_all<ActualOtherType>::type _ActualOtherType;\n    typename internal::add_const_on_value_type<ActualOtherType>::type actualOther = OtherBlasTraits::extract(other.derived());\n\n    Scalar actualAlpha = alpha * OtherBlasTraits::extractScalarFactor(other.derived());\n\n    enum {\n      StorageOrder = (internal::traits<MatrixType>::Flags&RowMajorBit) ? RowMajor : ColMajor,\n      UseOtherDirectly = _ActualOtherType::InnerStrideAtCompileTime==1\n    };\n    internal::gemv_static_vector_if<Scalar,OtherType::SizeAtCompileTime,OtherType::MaxSizeAtCompileTime,!UseOtherDirectly> static_other;\n\n    ei_declare_aligned_stack_constructed_variable(Scalar, actualOtherPtr, other.size(),\n      (UseOtherDirectly ? const_cast<Scalar*>(actualOther.data()) : static_other.data()));\n      \n    if(!UseOtherDirectly)\n      Map<typename _ActualOtherType::PlainObject>(actualOtherPtr, actualOther.size()) = actualOther;\n    \n    selfadjoint_rank1_update<Scalar,Index,StorageOrder,UpLo,\n                              OtherBlasTraits::NeedToConjugate  && NumTraits<Scalar>::IsComplex,\n                            (!OtherBlasTraits::NeedToConjugate) && NumTraits<Scalar>::IsComplex>\n          ::run(other.size(), mat.data(), mat.outerStride(), actualOtherPtr, actualOtherPtr, actualAlpha);\n  }\n};\n\ntemplate<typename MatrixType, typename OtherType, int UpLo>\nstruct selfadjoint_product_selector<MatrixType,OtherType,UpLo,false>\n{\n  static void run(MatrixType& mat, const OtherType& other, const typename MatrixType::Scalar& alpha)\n  {\n    typedef typename MatrixType::Scalar Scalar;\n    typedef internal::blas_traits<OtherType> OtherBlasTraits;\n    typedef typename OtherBlasTraits::DirectLinearAccessType ActualOtherType;\n    typedef typename internal::remove_all<ActualOtherType>::type _ActualOtherType;\n    typename internal::add_const_on_value_type<ActualOtherType>::type actualOther = OtherBlasTraits::extract(other.derived());\n\n    Scalar actualAlpha = alpha * OtherBlasTraits::extractScalarFactor(other.derived());\n\n    enum {\n      IsRowMajor = (internal::traits<MatrixType>::Flags&RowMajorBit) ? 1 : 0,\n      OtherIsRowMajor = _ActualOtherType::Flags&RowMajorBit ? 1 : 0\n    };\n\n    Index size = mat.cols();\n    Index depth = actualOther.cols();\n\n    typedef internal::gemm_blocking_space<IsRowMajor ? RowMajor : ColMajor,Scalar,Scalar,\n              MatrixType::MaxColsAtCompileTime, MatrixType::MaxColsAtCompileTime, _ActualOtherType::MaxColsAtCompileTime> BlockingType;\n\n    BlockingType blocking(size, size, depth, 1, false);\n\n\n    internal::general_matrix_matrix_triangular_product<Index,\n      Scalar, OtherIsRowMajor ? RowMajor : ColMajor,   OtherBlasTraits::NeedToConjugate  && NumTraits<Scalar>::IsComplex,\n      Scalar, OtherIsRowMajor ? ColMajor : RowMajor, (!OtherBlasTraits::NeedToConjugate) && NumTraits<Scalar>::IsComplex,\n      IsRowMajor ? RowMajor : ColMajor, UpLo>\n      ::run(size, depth,\n            &actualOther.coeffRef(0,0), actualOther.outerStride(), &actualOther.coeffRef(0,0), actualOther.outerStride(),\n            mat.data(), mat.outerStride(), actualAlpha, blocking);\n  }\n};\n\n// high level API\n\ntemplate<typename MatrixType, unsigned int UpLo>\ntemplate<typename DerivedU>\nSelfAdjointView<MatrixType,UpLo>& SelfAdjointView<MatrixType,UpLo>\n::rankUpdate(const MatrixBase<DerivedU>& u, const Scalar& alpha)\n{\n  selfadjoint_product_selector<MatrixType,DerivedU,UpLo>::run(_expression().const_cast_derived(), u.derived(), alpha);\n\n  return *this;\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_SELFADJOINT_PRODUCT_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/products/SelfadjointRank2Update.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SELFADJOINTRANK2UPTADE_H\n#define EIGEN_SELFADJOINTRANK2UPTADE_H\n\nnamespace Eigen { \n\nnamespace internal {\n\n/* Optimized selfadjoint matrix += alpha * uv' + conj(alpha)*vu'\n * It corresponds to the Level2 syr2 BLAS routine\n */\n\ntemplate<typename Scalar, typename Index, typename UType, typename VType, int UpLo>\nstruct selfadjoint_rank2_update_selector;\n\ntemplate<typename Scalar, typename Index, typename UType, typename VType>\nstruct selfadjoint_rank2_update_selector<Scalar,Index,UType,VType,Lower>\n{\n  static void run(Scalar* mat, Index stride, const UType& u, const VType& v, const Scalar& alpha)\n  {\n    const Index size = u.size();\n    for (Index i=0; i<size; ++i)\n    {\n      Map<Matrix<Scalar,Dynamic,1> >(mat+stride*i+i, size-i) +=\n                        (numext::conj(alpha) * numext::conj(u.coeff(i))) * v.tail(size-i)\n                      + (alpha * numext::conj(v.coeff(i))) * u.tail(size-i);\n    }\n  }\n};\n\ntemplate<typename Scalar, typename Index, typename UType, typename VType>\nstruct selfadjoint_rank2_update_selector<Scalar,Index,UType,VType,Upper>\n{\n  static void run(Scalar* mat, Index stride, const UType& u, const VType& v, const Scalar& alpha)\n  {\n    const Index size = u.size();\n    for (Index i=0; i<size; ++i)\n      Map<Matrix<Scalar,Dynamic,1> >(mat+stride*i, i+1) +=\n                        (numext::conj(alpha)  * numext::conj(u.coeff(i))) * v.head(i+1)\n                      + (alpha * numext::conj(v.coeff(i))) * u.head(i+1);\n  }\n};\n\ntemplate<bool Cond, typename T> struct conj_expr_if\n  : conditional<!Cond, const T&,\n      CwiseUnaryOp<scalar_conjugate_op<typename traits<T>::Scalar>,T> > {};\n\n} // end namespace internal\n\ntemplate<typename MatrixType, unsigned int UpLo>\ntemplate<typename DerivedU, typename DerivedV>\nSelfAdjointView<MatrixType,UpLo>& SelfAdjointView<MatrixType,UpLo>\n::rankUpdate(const MatrixBase<DerivedU>& u, const MatrixBase<DerivedV>& v, const Scalar& alpha)\n{\n  typedef internal::blas_traits<DerivedU> UBlasTraits;\n  typedef typename UBlasTraits::DirectLinearAccessType ActualUType;\n  typedef typename internal::remove_all<ActualUType>::type _ActualUType;\n  typename internal::add_const_on_value_type<ActualUType>::type actualU = UBlasTraits::extract(u.derived());\n\n  typedef internal::blas_traits<DerivedV> VBlasTraits;\n  typedef typename VBlasTraits::DirectLinearAccessType ActualVType;\n  typedef typename internal::remove_all<ActualVType>::type _ActualVType;\n  typename internal::add_const_on_value_type<ActualVType>::type actualV = VBlasTraits::extract(v.derived());\n\n  // If MatrixType is row major, then we use the routine for lower triangular in the upper triangular case and\n  // vice versa, and take the complex conjugate of all coefficients and vector entries.\n\n  enum { IsRowMajor = (internal::traits<MatrixType>::Flags&RowMajorBit) ? 1 : 0 };\n  Scalar actualAlpha = alpha * UBlasTraits::extractScalarFactor(u.derived())\n                             * numext::conj(VBlasTraits::extractScalarFactor(v.derived()));\n  if (IsRowMajor)\n    actualAlpha = numext::conj(actualAlpha);\n\n  typedef typename internal::remove_all<typename internal::conj_expr_if<IsRowMajor ^ UBlasTraits::NeedToConjugate,_ActualUType>::type>::type UType;\n  typedef typename internal::remove_all<typename internal::conj_expr_if<IsRowMajor ^ VBlasTraits::NeedToConjugate,_ActualVType>::type>::type VType;\n  internal::selfadjoint_rank2_update_selector<Scalar, Index, UType, VType,\n    (IsRowMajor ? int(UpLo==Upper ? Lower : Upper) : UpLo)>\n    ::run(_expression().const_cast_derived().data(),_expression().outerStride(),UType(actualU),VType(actualV),actualAlpha);\n\n  return *this;\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_SELFADJOINTRANK2UPTADE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/products/TriangularMatrixMatrix.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_TRIANGULAR_MATRIX_MATRIX_H\n#define EIGEN_TRIANGULAR_MATRIX_MATRIX_H\n\nnamespace Eigen { \n\nnamespace internal {\n\n// template<typename Scalar, int mr, int StorageOrder, bool Conjugate, int Mode>\n// struct gemm_pack_lhs_triangular\n// {\n//   Matrix<Scalar,mr,mr,\n//   void operator()(Scalar* blockA, const EIGEN_RESTRICT Scalar* _lhs, int lhsStride, int depth, int rows)\n//   {\n//     conj_if<NumTraits<Scalar>::IsComplex && Conjugate> cj;\n//     const_blas_data_mapper<Scalar, StorageOrder> lhs(_lhs,lhsStride);\n//     int count = 0;\n//     const int peeled_mc = (rows/mr)*mr;\n//     for(int i=0; i<peeled_mc; i+=mr)\n//     {\n//       for(int k=0; k<depth; k++)\n//         for(int w=0; w<mr; w++)\n//           blockA[count++] = cj(lhs(i+w, k));\n//     }\n//     for(int i=peeled_mc; i<rows; i++)\n//     {\n//       for(int k=0; k<depth; k++)\n//         blockA[count++] = cj(lhs(i, k));\n//     }\n//   }\n// };\n\n/* Optimized triangular matrix * matrix (_TRMM++) product built on top of\n * the general matrix matrix product.\n */\ntemplate <typename Scalar, typename Index,\n          int Mode, bool LhsIsTriangular,\n          int LhsStorageOrder, bool ConjugateLhs,\n          int RhsStorageOrder, bool ConjugateRhs,\n          int ResStorageOrder, int Version = Specialized>\nstruct product_triangular_matrix_matrix;\n\ntemplate <typename Scalar, typename Index,\n          int Mode, bool LhsIsTriangular,\n          int LhsStorageOrder, bool ConjugateLhs,\n          int RhsStorageOrder, bool ConjugateRhs, int Version>\nstruct product_triangular_matrix_matrix<Scalar,Index,Mode,LhsIsTriangular,\n                                           LhsStorageOrder,ConjugateLhs,\n                                           RhsStorageOrder,ConjugateRhs,RowMajor,Version>\n{\n  static EIGEN_STRONG_INLINE void run(\n    Index rows, Index cols, Index depth,\n    const Scalar* lhs, Index lhsStride,\n    const Scalar* rhs, Index rhsStride,\n    Scalar* res,       Index resStride,\n    const Scalar& alpha, level3_blocking<Scalar,Scalar>& blocking)\n  {\n    product_triangular_matrix_matrix<Scalar, Index,\n      (Mode&(UnitDiag|ZeroDiag)) | ((Mode&Upper) ? Lower : Upper),\n      (!LhsIsTriangular),\n      RhsStorageOrder==RowMajor ? ColMajor : RowMajor,\n      ConjugateRhs,\n      LhsStorageOrder==RowMajor ? ColMajor : RowMajor,\n      ConjugateLhs,\n      ColMajor>\n      ::run(cols, rows, depth, rhs, rhsStride, lhs, lhsStride, res, resStride, alpha, blocking);\n  }\n};\n\n// implements col-major += alpha * op(triangular) * op(general)\ntemplate <typename Scalar, typename Index, int Mode,\n          int LhsStorageOrder, bool ConjugateLhs,\n          int RhsStorageOrder, bool ConjugateRhs, int Version>\nstruct product_triangular_matrix_matrix<Scalar,Index,Mode,true,\n                                           LhsStorageOrder,ConjugateLhs,\n                                           RhsStorageOrder,ConjugateRhs,ColMajor,Version>\n{\n  \n  typedef gebp_traits<Scalar,Scalar> Traits;\n  enum {\n    SmallPanelWidth   = 2 * EIGEN_PLAIN_ENUM_MAX(Traits::mr,Traits::nr),\n    IsLower = (Mode&Lower) == Lower,\n    SetDiag = (Mode&(ZeroDiag|UnitDiag)) ? 0 : 1\n  };\n\n  static EIGEN_DONT_INLINE void run(\n    Index _rows, Index _cols, Index _depth,\n    const Scalar* _lhs, Index lhsStride,\n    const Scalar* _rhs, Index rhsStride,\n    Scalar* res,        Index resStride,\n    const Scalar& alpha, level3_blocking<Scalar,Scalar>& blocking);\n};\n\ntemplate <typename Scalar, typename Index, int Mode,\n          int LhsStorageOrder, bool ConjugateLhs,\n          int RhsStorageOrder, bool ConjugateRhs, int Version>\nEIGEN_DONT_INLINE void product_triangular_matrix_matrix<Scalar,Index,Mode,true,\n                                                        LhsStorageOrder,ConjugateLhs,\n                                                        RhsStorageOrder,ConjugateRhs,ColMajor,Version>::run(\n    Index _rows, Index _cols, Index _depth,\n    const Scalar* _lhs, Index lhsStride,\n    const Scalar* _rhs, Index rhsStride,\n    Scalar* _res,        Index resStride,\n    const Scalar& alpha, level3_blocking<Scalar,Scalar>& blocking)\n  {\n    // strip zeros\n    Index diagSize  = (std::min)(_rows,_depth);\n    Index rows      = IsLower ? _rows : diagSize;\n    Index depth     = IsLower ? diagSize : _depth;\n    Index cols      = _cols;\n    \n    typedef const_blas_data_mapper<Scalar, Index, LhsStorageOrder> LhsMapper;\n    typedef const_blas_data_mapper<Scalar, Index, RhsStorageOrder> RhsMapper;\n    typedef blas_data_mapper<typename Traits::ResScalar, Index, ColMajor> ResMapper;\n    LhsMapper lhs(_lhs,lhsStride);\n    RhsMapper rhs(_rhs,rhsStride);\n    ResMapper res(_res, resStride);\n\n    Index kc = blocking.kc();                   // cache block size along the K direction\n    Index mc = (std::min)(rows,blocking.mc());  // cache block size along the M direction\n    // The small panel size must not be larger than blocking size.\n    // Usually this should never be the case because SmallPanelWidth^2 is very small\n    // compared to L2 cache size, but let's be safe:\n    Index panelWidth = (std::min)(Index(SmallPanelWidth),(std::min)(kc,mc));\n\n    std::size_t sizeA = kc*mc;\n    std::size_t sizeB = kc*cols;\n\n    ei_declare_aligned_stack_constructed_variable(Scalar, blockA, sizeA, blocking.blockA());\n    ei_declare_aligned_stack_constructed_variable(Scalar, blockB, sizeB, blocking.blockB());\n\n    Matrix<Scalar,SmallPanelWidth,SmallPanelWidth,LhsStorageOrder> triangularBuffer;\n    triangularBuffer.setZero();\n    if((Mode&ZeroDiag)==ZeroDiag)\n      triangularBuffer.diagonal().setZero();\n    else\n      triangularBuffer.diagonal().setOnes();\n\n    gebp_kernel<Scalar, Scalar, Index, ResMapper, Traits::mr, Traits::nr, ConjugateLhs, ConjugateRhs> gebp_kernel;\n    gemm_pack_lhs<Scalar, Index, LhsMapper, Traits::mr, Traits::LhsProgress, LhsStorageOrder> pack_lhs;\n    gemm_pack_rhs<Scalar, Index, RhsMapper, Traits::nr,RhsStorageOrder> pack_rhs;\n\n    for(Index k2=IsLower ? depth : 0;\n        IsLower ? k2>0 : k2<depth;\n        IsLower ? k2-=kc : k2+=kc)\n    {\n      Index actual_kc = (std::min)(IsLower ? k2 : depth-k2, kc);\n      Index actual_k2 = IsLower ? k2-actual_kc : k2;\n\n      // align blocks with the end of the triangular part for trapezoidal lhs\n      if((!IsLower)&&(k2<rows)&&(k2+actual_kc>rows))\n      {\n        actual_kc = rows-k2;\n        k2 = k2+actual_kc-kc;\n      }\n\n      pack_rhs(blockB, rhs.getSubMapper(actual_k2,0), actual_kc, cols);\n\n      // the selected lhs's panel has to be split in three different parts:\n      //  1 - the part which is zero => skip it\n      //  2 - the diagonal block => special kernel\n      //  3 - the dense panel below (lower case) or above (upper case) the diagonal block => GEPP\n\n      // the block diagonal, if any:\n      if(IsLower || actual_k2<rows)\n      {\n        // for each small vertical panels of lhs\n        for (Index k1=0; k1<actual_kc; k1+=panelWidth)\n        {\n          Index actualPanelWidth = std::min<Index>(actual_kc-k1, panelWidth);\n          Index lengthTarget = IsLower ? actual_kc-k1-actualPanelWidth : k1;\n          Index startBlock   = actual_k2+k1;\n          Index blockBOffset = k1;\n\n          // => GEBP with the micro triangular block\n          // The trick is to pack this micro block while filling the opposite triangular part with zeros.\n          // To this end we do an extra triangular copy to a small temporary buffer\n          for (Index k=0;k<actualPanelWidth;++k)\n          {\n            if (SetDiag)\n              triangularBuffer.coeffRef(k,k) = lhs(startBlock+k,startBlock+k);\n            for (Index i=IsLower ? k+1 : 0; IsLower ? i<actualPanelWidth : i<k; ++i)\n              triangularBuffer.coeffRef(i,k) = lhs(startBlock+i,startBlock+k);\n          }\n          pack_lhs(blockA, LhsMapper(triangularBuffer.data(), triangularBuffer.outerStride()), actualPanelWidth, actualPanelWidth);\n\n          gebp_kernel(res.getSubMapper(startBlock, 0), blockA, blockB,\n                      actualPanelWidth, actualPanelWidth, cols, alpha,\n                      actualPanelWidth, actual_kc, 0, blockBOffset);\n\n          // GEBP with remaining micro panel\n          if (lengthTarget>0)\n          {\n            Index startTarget  = IsLower ? actual_k2+k1+actualPanelWidth : actual_k2;\n\n            pack_lhs(blockA, lhs.getSubMapper(startTarget,startBlock), actualPanelWidth, lengthTarget);\n\n            gebp_kernel(res.getSubMapper(startTarget, 0), blockA, blockB,\n                        lengthTarget, actualPanelWidth, cols, alpha,\n                        actualPanelWidth, actual_kc, 0, blockBOffset);\n          }\n        }\n      }\n      // the part below (lower case) or above (upper case) the diagonal => GEPP\n      {\n        Index start = IsLower ? k2 : 0;\n        Index end   = IsLower ? rows : (std::min)(actual_k2,rows);\n        for(Index i2=start; i2<end; i2+=mc)\n        {\n          const Index actual_mc = (std::min)(i2+mc,end)-i2;\n          gemm_pack_lhs<Scalar, Index, LhsMapper, Traits::mr,Traits::LhsProgress, LhsStorageOrder,false>()\n            (blockA, lhs.getSubMapper(i2, actual_k2), actual_kc, actual_mc);\n\n          gebp_kernel(res.getSubMapper(i2, 0), blockA, blockB, actual_mc,\n                      actual_kc, cols, alpha, -1, -1, 0, 0);\n        }\n      }\n    }\n  }\n\n// implements col-major += alpha * op(general) * op(triangular)\ntemplate <typename Scalar, typename Index, int Mode,\n          int LhsStorageOrder, bool ConjugateLhs,\n          int RhsStorageOrder, bool ConjugateRhs, int Version>\nstruct product_triangular_matrix_matrix<Scalar,Index,Mode,false,\n                                        LhsStorageOrder,ConjugateLhs,\n                                        RhsStorageOrder,ConjugateRhs,ColMajor,Version>\n{\n  typedef gebp_traits<Scalar,Scalar> Traits;\n  enum {\n    SmallPanelWidth   = EIGEN_PLAIN_ENUM_MAX(Traits::mr,Traits::nr),\n    IsLower = (Mode&Lower) == Lower,\n    SetDiag = (Mode&(ZeroDiag|UnitDiag)) ? 0 : 1\n  };\n\n  static EIGEN_DONT_INLINE void run(\n    Index _rows, Index _cols, Index _depth,\n    const Scalar* _lhs, Index lhsStride,\n    const Scalar* _rhs, Index rhsStride,\n    Scalar* res,        Index resStride,\n    const Scalar& alpha, level3_blocking<Scalar,Scalar>& blocking);\n};\n\ntemplate <typename Scalar, typename Index, int Mode,\n          int LhsStorageOrder, bool ConjugateLhs,\n          int RhsStorageOrder, bool ConjugateRhs, int Version>\nEIGEN_DONT_INLINE void product_triangular_matrix_matrix<Scalar,Index,Mode,false,\n                                                        LhsStorageOrder,ConjugateLhs,\n                                                        RhsStorageOrder,ConjugateRhs,ColMajor,Version>::run(\n    Index _rows, Index _cols, Index _depth,\n    const Scalar* _lhs, Index lhsStride,\n    const Scalar* _rhs, Index rhsStride,\n    Scalar* _res,        Index resStride,\n    const Scalar& alpha, level3_blocking<Scalar,Scalar>& blocking)\n  {\n    const Index PacketBytes = packet_traits<Scalar>::size*sizeof(Scalar);\n    // strip zeros\n    Index diagSize  = (std::min)(_cols,_depth);\n    Index rows      = _rows;\n    Index depth     = IsLower ? _depth : diagSize;\n    Index cols      = IsLower ? diagSize : _cols;\n    \n    typedef const_blas_data_mapper<Scalar, Index, LhsStorageOrder> LhsMapper;\n    typedef const_blas_data_mapper<Scalar, Index, RhsStorageOrder> RhsMapper;\n    typedef blas_data_mapper<typename Traits::ResScalar, Index, ColMajor> ResMapper;\n    LhsMapper lhs(_lhs,lhsStride);\n    RhsMapper rhs(_rhs,rhsStride);\n    ResMapper res(_res, resStride);\n\n    Index kc = blocking.kc();                   // cache block size along the K direction\n    Index mc = (std::min)(rows,blocking.mc());  // cache block size along the M direction\n\n    std::size_t sizeA = kc*mc;\n    std::size_t sizeB = kc*cols+EIGEN_MAX_ALIGN_BYTES/sizeof(Scalar);\n\n    ei_declare_aligned_stack_constructed_variable(Scalar, blockA, sizeA, blocking.blockA());\n    ei_declare_aligned_stack_constructed_variable(Scalar, blockB, sizeB, blocking.blockB());\n\n    Matrix<Scalar,SmallPanelWidth,SmallPanelWidth,RhsStorageOrder> triangularBuffer;\n    triangularBuffer.setZero();\n    if((Mode&ZeroDiag)==ZeroDiag)\n      triangularBuffer.diagonal().setZero();\n    else\n      triangularBuffer.diagonal().setOnes();\n\n    gebp_kernel<Scalar, Scalar, Index, ResMapper, Traits::mr, Traits::nr, ConjugateLhs, ConjugateRhs> gebp_kernel;\n    gemm_pack_lhs<Scalar, Index, LhsMapper, Traits::mr, Traits::LhsProgress, LhsStorageOrder> pack_lhs;\n    gemm_pack_rhs<Scalar, Index, RhsMapper, Traits::nr,RhsStorageOrder> pack_rhs;\n    gemm_pack_rhs<Scalar, Index, RhsMapper, Traits::nr,RhsStorageOrder,false,true> pack_rhs_panel;\n\n    for(Index k2=IsLower ? 0 : depth;\n        IsLower ? k2<depth  : k2>0;\n        IsLower ? k2+=kc   : k2-=kc)\n    {\n      Index actual_kc = (std::min)(IsLower ? depth-k2 : k2, kc);\n      Index actual_k2 = IsLower ? k2 : k2-actual_kc;\n\n      // align blocks with the end of the triangular part for trapezoidal rhs\n      if(IsLower && (k2<cols) && (actual_k2+actual_kc>cols))\n      {\n        actual_kc = cols-k2;\n        k2 = actual_k2 + actual_kc - kc;\n      }\n\n      // remaining size\n      Index rs = IsLower ? (std::min)(cols,actual_k2) : cols - k2;\n      // size of the triangular part\n      Index ts = (IsLower && actual_k2>=cols) ? 0 : actual_kc;\n\n      Scalar* geb = blockB+ts*ts;\n      geb = geb + internal::first_aligned<PacketBytes>(geb,PacketBytes/sizeof(Scalar));\n\n      pack_rhs(geb, rhs.getSubMapper(actual_k2,IsLower ? 0 : k2), actual_kc, rs);\n\n      // pack the triangular part of the rhs padding the unrolled blocks with zeros\n      if(ts>0)\n      {\n        for (Index j2=0; j2<actual_kc; j2+=SmallPanelWidth)\n        {\n          Index actualPanelWidth = std::min<Index>(actual_kc-j2, SmallPanelWidth);\n          Index actual_j2 = actual_k2 + j2;\n          Index panelOffset = IsLower ? j2+actualPanelWidth : 0;\n          Index panelLength = IsLower ? actual_kc-j2-actualPanelWidth : j2;\n          // general part\n          pack_rhs_panel(blockB+j2*actual_kc,\n                         rhs.getSubMapper(actual_k2+panelOffset, actual_j2),\n                         panelLength, actualPanelWidth,\n                         actual_kc, panelOffset);\n\n          // append the triangular part via a temporary buffer\n          for (Index j=0;j<actualPanelWidth;++j)\n          {\n            if (SetDiag)\n              triangularBuffer.coeffRef(j,j) = rhs(actual_j2+j,actual_j2+j);\n            for (Index k=IsLower ? j+1 : 0; IsLower ? k<actualPanelWidth : k<j; ++k)\n              triangularBuffer.coeffRef(k,j) = rhs(actual_j2+k,actual_j2+j);\n          }\n\n          pack_rhs_panel(blockB+j2*actual_kc,\n                         RhsMapper(triangularBuffer.data(), triangularBuffer.outerStride()),\n                         actualPanelWidth, actualPanelWidth,\n                         actual_kc, j2);\n        }\n      }\n\n      for (Index i2=0; i2<rows; i2+=mc)\n      {\n        const Index actual_mc = (std::min)(mc,rows-i2);\n        pack_lhs(blockA, lhs.getSubMapper(i2, actual_k2), actual_kc, actual_mc);\n\n        // triangular kernel\n        if(ts>0)\n        {\n          for (Index j2=0; j2<actual_kc; j2+=SmallPanelWidth)\n          {\n            Index actualPanelWidth = std::min<Index>(actual_kc-j2, SmallPanelWidth);\n            Index panelLength = IsLower ? actual_kc-j2 : j2+actualPanelWidth;\n            Index blockOffset = IsLower ? j2 : 0;\n\n            gebp_kernel(res.getSubMapper(i2, actual_k2 + j2),\n                        blockA, blockB+j2*actual_kc,\n                        actual_mc, panelLength, actualPanelWidth,\n                        alpha,\n                        actual_kc, actual_kc,  // strides\n                        blockOffset, blockOffset);// offsets\n          }\n        }\n        gebp_kernel(res.getSubMapper(i2, IsLower ? 0 : k2),\n                    blockA, geb, actual_mc, actual_kc, rs,\n                    alpha,\n                    -1, -1, 0, 0);\n      }\n    }\n  }\n\n/***************************************************************************\n* Wrapper to product_triangular_matrix_matrix\n***************************************************************************/\n\n} // end namespace internal\n\nnamespace internal {\ntemplate<int Mode, bool LhsIsTriangular, typename Lhs, typename Rhs>\nstruct triangular_product_impl<Mode,LhsIsTriangular,Lhs,false,Rhs,false>\n{\n  template<typename Dest> static void run(Dest& dst, const Lhs &a_lhs, const Rhs &a_rhs, const typename Dest::Scalar& alpha)\n  {\n    typedef typename Dest::Scalar     Scalar;\n    \n    typedef internal::blas_traits<Lhs> LhsBlasTraits;\n    typedef typename LhsBlasTraits::DirectLinearAccessType ActualLhsType;\n    typedef typename internal::remove_all<ActualLhsType>::type ActualLhsTypeCleaned;\n    typedef internal::blas_traits<Rhs> RhsBlasTraits;\n    typedef typename RhsBlasTraits::DirectLinearAccessType ActualRhsType;\n    typedef typename internal::remove_all<ActualRhsType>::type ActualRhsTypeCleaned;\n    \n    typename internal::add_const_on_value_type<ActualLhsType>::type lhs = LhsBlasTraits::extract(a_lhs);\n    typename internal::add_const_on_value_type<ActualRhsType>::type rhs = RhsBlasTraits::extract(a_rhs);\n\n    Scalar actualAlpha = alpha * LhsBlasTraits::extractScalarFactor(a_lhs)\n                               * RhsBlasTraits::extractScalarFactor(a_rhs);\n\n    typedef internal::gemm_blocking_space<(Dest::Flags&RowMajorBit) ? RowMajor : ColMajor,Scalar,Scalar,\n              Lhs::MaxRowsAtCompileTime, Rhs::MaxColsAtCompileTime, Lhs::MaxColsAtCompileTime,4> BlockingType;\n\n    enum { IsLower = (Mode&Lower) == Lower };\n    Index stripedRows  = ((!LhsIsTriangular) || (IsLower))  ? lhs.rows() : (std::min)(lhs.rows(),lhs.cols());\n    Index stripedCols  = ((LhsIsTriangular)  || (!IsLower)) ? rhs.cols() : (std::min)(rhs.cols(),rhs.rows());\n    Index stripedDepth = LhsIsTriangular ? ((!IsLower) ? lhs.cols() : (std::min)(lhs.cols(),lhs.rows()))\n                                         : ((IsLower)  ? rhs.rows() : (std::min)(rhs.rows(),rhs.cols()));\n\n    BlockingType blocking(stripedRows, stripedCols, stripedDepth, 1, false);\n\n    internal::product_triangular_matrix_matrix<Scalar, Index,\n      Mode, LhsIsTriangular,\n      (internal::traits<ActualLhsTypeCleaned>::Flags&RowMajorBit) ? RowMajor : ColMajor, LhsBlasTraits::NeedToConjugate,\n      (internal::traits<ActualRhsTypeCleaned>::Flags&RowMajorBit) ? RowMajor : ColMajor, RhsBlasTraits::NeedToConjugate,\n      (internal::traits<Dest          >::Flags&RowMajorBit) ? RowMajor : ColMajor>\n      ::run(\n        stripedRows, stripedCols, stripedDepth,   // sizes\n        &lhs.coeffRef(0,0), lhs.outerStride(),    // lhs info\n        &rhs.coeffRef(0,0), rhs.outerStride(),    // rhs info\n        &dst.coeffRef(0,0), dst.outerStride(),    // result info\n        actualAlpha, blocking\n      );\n  }\n};\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_TRIANGULAR_MATRIX_MATRIX_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/products/TriangularMatrixMatrix_BLAS.h",
    "content": "/*\n Copyright (c) 2011, Intel Corporation. All rights reserved.\n\n Redistribution and use in source and binary forms, with or without modification,\n are permitted provided that the following conditions are met:\n\n * Redistributions of source code must retain the above copyright notice, this\n   list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright notice,\n   this list of conditions and the following disclaimer in the documentation\n   and/or other materials provided with the distribution.\n * Neither the name of Intel Corporation nor the names of its contributors may\n   be used to endorse or promote products derived from this software without\n   specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n ********************************************************************************\n *   Content : Eigen bindings to BLAS F77\n *   Triangular matrix * matrix product functionality based on ?TRMM.\n ********************************************************************************\n*/\n\n#ifndef EIGEN_TRIANGULAR_MATRIX_MATRIX_BLAS_H\n#define EIGEN_TRIANGULAR_MATRIX_MATRIX_BLAS_H\n\nnamespace Eigen { \n\nnamespace internal {\n\n\ntemplate <typename Scalar, typename Index,\n          int Mode, bool LhsIsTriangular,\n          int LhsStorageOrder, bool ConjugateLhs,\n          int RhsStorageOrder, bool ConjugateRhs,\n          int ResStorageOrder>\nstruct product_triangular_matrix_matrix_trmm :\n       product_triangular_matrix_matrix<Scalar,Index,Mode,\n          LhsIsTriangular,LhsStorageOrder,ConjugateLhs,\n          RhsStorageOrder, ConjugateRhs, ResStorageOrder, BuiltIn> {};\n\n\n// try to go to BLAS specialization\n#define EIGEN_BLAS_TRMM_SPECIALIZE(Scalar, LhsIsTriangular) \\\ntemplate <typename Index, int Mode, \\\n          int LhsStorageOrder, bool ConjugateLhs, \\\n          int RhsStorageOrder, bool ConjugateRhs> \\\nstruct product_triangular_matrix_matrix<Scalar,Index, Mode, LhsIsTriangular, \\\n           LhsStorageOrder,ConjugateLhs, RhsStorageOrder,ConjugateRhs,ColMajor,Specialized> { \\\n  static inline void run(Index _rows, Index _cols, Index _depth, const Scalar* _lhs, Index lhsStride,\\\n    const Scalar* _rhs, Index rhsStride, Scalar* res, Index resStride, Scalar alpha, level3_blocking<Scalar,Scalar>& blocking) { \\\n      product_triangular_matrix_matrix_trmm<Scalar,Index,Mode, \\\n        LhsIsTriangular,LhsStorageOrder,ConjugateLhs, \\\n        RhsStorageOrder, ConjugateRhs, ColMajor>::run( \\\n        _rows, _cols, _depth, _lhs, lhsStride, _rhs, rhsStride, res, resStride, alpha, blocking); \\\n  } \\\n};\n\nEIGEN_BLAS_TRMM_SPECIALIZE(double, true)\nEIGEN_BLAS_TRMM_SPECIALIZE(double, false)\nEIGEN_BLAS_TRMM_SPECIALIZE(dcomplex, true)\nEIGEN_BLAS_TRMM_SPECIALIZE(dcomplex, false)\nEIGEN_BLAS_TRMM_SPECIALIZE(float, true)\nEIGEN_BLAS_TRMM_SPECIALIZE(float, false)\nEIGEN_BLAS_TRMM_SPECIALIZE(scomplex, true)\nEIGEN_BLAS_TRMM_SPECIALIZE(scomplex, false)\n\n// implements col-major += alpha * op(triangular) * op(general)\n#define EIGEN_BLAS_TRMM_L(EIGTYPE, BLASTYPE, EIGPREFIX, BLASPREFIX) \\\ntemplate <typename Index, int Mode, \\\n          int LhsStorageOrder, bool ConjugateLhs, \\\n          int RhsStorageOrder, bool ConjugateRhs> \\\nstruct product_triangular_matrix_matrix_trmm<EIGTYPE,Index,Mode,true, \\\n         LhsStorageOrder,ConjugateLhs,RhsStorageOrder,ConjugateRhs,ColMajor> \\\n{ \\\n  enum { \\\n    IsLower = (Mode&Lower) == Lower, \\\n    SetDiag = (Mode&(ZeroDiag|UnitDiag)) ? 0 : 1, \\\n    IsUnitDiag  = (Mode&UnitDiag) ? 1 : 0, \\\n    IsZeroDiag  = (Mode&ZeroDiag) ? 1 : 0, \\\n    LowUp = IsLower ? Lower : Upper, \\\n    conjA = ((LhsStorageOrder==ColMajor) && ConjugateLhs) ? 1 : 0 \\\n  }; \\\n\\\n  static void run( \\\n    Index _rows, Index _cols, Index _depth, \\\n    const EIGTYPE* _lhs, Index lhsStride, \\\n    const EIGTYPE* _rhs, Index rhsStride, \\\n    EIGTYPE* res,        Index resStride, \\\n    EIGTYPE alpha, level3_blocking<EIGTYPE,EIGTYPE>& blocking) \\\n  { \\\n   Index diagSize  = (std::min)(_rows,_depth); \\\n   Index rows      = IsLower ? _rows : diagSize; \\\n   Index depth     = IsLower ? diagSize : _depth; \\\n   Index cols      = _cols; \\\n\\\n   typedef Matrix<EIGTYPE, Dynamic, Dynamic, LhsStorageOrder> MatrixLhs; \\\n   typedef Matrix<EIGTYPE, Dynamic, Dynamic, RhsStorageOrder> MatrixRhs; \\\n\\\n/* Non-square case - doesn't fit to BLAS ?TRMM. Fall to default triangular product or call BLAS ?GEMM*/ \\\n   if (rows != depth) { \\\n\\\n     /* FIXME handle mkl_domain_get_max_threads */ \\\n     /*int nthr = mkl_domain_get_max_threads(EIGEN_BLAS_DOMAIN_BLAS);*/ int nthr = 1;\\\n\\\n     if (((nthr==1) && (((std::max)(rows,depth)-diagSize)/(double)diagSize < 0.5))) { \\\n     /* Most likely no benefit to call TRMM or GEMM from BLAS */ \\\n       product_triangular_matrix_matrix<EIGTYPE,Index,Mode,true, \\\n       LhsStorageOrder,ConjugateLhs, RhsStorageOrder, ConjugateRhs, ColMajor, BuiltIn>::run( \\\n           _rows, _cols, _depth, _lhs, lhsStride, _rhs, rhsStride, res, resStride, alpha, blocking); \\\n     /*std::cout << \"TRMM_L: A is not square! Go to Eigen TRMM implementation!\\n\";*/ \\\n     } else { \\\n     /* Make sense to call GEMM */ \\\n       Map<const MatrixLhs, 0, OuterStride<> > lhsMap(_lhs,rows,depth,OuterStride<>(lhsStride)); \\\n       MatrixLhs aa_tmp=lhsMap.template triangularView<Mode>(); \\\n       BlasIndex aStride = convert_index<BlasIndex>(aa_tmp.outerStride()); \\\n       gemm_blocking_space<ColMajor,EIGTYPE,EIGTYPE,Dynamic,Dynamic,Dynamic> gemm_blocking(_rows,_cols,_depth, 1, true); \\\n       general_matrix_matrix_product<Index,EIGTYPE,LhsStorageOrder,ConjugateLhs,EIGTYPE,RhsStorageOrder,ConjugateRhs,ColMajor>::run( \\\n       rows, cols, depth, aa_tmp.data(), aStride, _rhs, rhsStride, res, resStride, alpha, gemm_blocking, 0); \\\n\\\n     /*std::cout << \"TRMM_L: A is not square! Go to BLAS GEMM implementation! \" << nthr<<\" \\n\";*/ \\\n     } \\\n     return; \\\n   } \\\n   char side = 'L', transa, uplo, diag = 'N'; \\\n   EIGTYPE *b; \\\n   const EIGTYPE *a; \\\n   BlasIndex m, n, lda, ldb; \\\n\\\n/* Set m, n */ \\\n   m = convert_index<BlasIndex>(diagSize); \\\n   n = convert_index<BlasIndex>(cols); \\\n\\\n/* Set trans */ \\\n   transa = (LhsStorageOrder==RowMajor) ? ((ConjugateLhs) ? 'C' : 'T') : 'N'; \\\n\\\n/* Set b, ldb */ \\\n   Map<const MatrixRhs, 0, OuterStride<> > rhs(_rhs,depth,cols,OuterStride<>(rhsStride)); \\\n   MatrixX##EIGPREFIX b_tmp; \\\n\\\n   if (ConjugateRhs) b_tmp = rhs.conjugate(); else b_tmp = rhs; \\\n   b = b_tmp.data(); \\\n   ldb = convert_index<BlasIndex>(b_tmp.outerStride()); \\\n\\\n/* Set uplo */ \\\n   uplo = IsLower ? 'L' : 'U'; \\\n   if (LhsStorageOrder==RowMajor) uplo = (uplo == 'L') ? 'U' : 'L'; \\\n/* Set a, lda */ \\\n   Map<const MatrixLhs, 0, OuterStride<> > lhs(_lhs,rows,depth,OuterStride<>(lhsStride)); \\\n   MatrixLhs a_tmp; \\\n\\\n   if ((conjA!=0) || (SetDiag==0)) { \\\n     if (conjA) a_tmp = lhs.conjugate(); else a_tmp = lhs; \\\n     if (IsZeroDiag) \\\n       a_tmp.diagonal().setZero(); \\\n     else if (IsUnitDiag) \\\n       a_tmp.diagonal().setOnes();\\\n     a = a_tmp.data(); \\\n     lda = convert_index<BlasIndex>(a_tmp.outerStride()); \\\n   } else { \\\n     a = _lhs; \\\n     lda = convert_index<BlasIndex>(lhsStride); \\\n   } \\\n   /*std::cout << \"TRMM_L: A is square! Go to BLAS TRMM implementation! \\n\";*/ \\\n/* call ?trmm*/ \\\n   BLASPREFIX##trmm_(&side, &uplo, &transa, &diag, &m, &n, &numext::real_ref(alpha), (const BLASTYPE*)a, &lda, (BLASTYPE*)b, &ldb); \\\n\\\n/* Add op(a_triangular)*b into res*/ \\\n   Map<MatrixX##EIGPREFIX, 0, OuterStride<> > res_tmp(res,rows,cols,OuterStride<>(resStride)); \\\n   res_tmp=res_tmp+b_tmp; \\\n  } \\\n};\n\nEIGEN_BLAS_TRMM_L(double, double, d, d)\nEIGEN_BLAS_TRMM_L(dcomplex, double, cd, z)\nEIGEN_BLAS_TRMM_L(float, float, f, s)\nEIGEN_BLAS_TRMM_L(scomplex, float, cf, c)\n\n// implements col-major += alpha * op(general) * op(triangular)\n#define EIGEN_BLAS_TRMM_R(EIGTYPE, BLASTYPE, EIGPREFIX, BLASPREFIX) \\\ntemplate <typename Index, int Mode, \\\n          int LhsStorageOrder, bool ConjugateLhs, \\\n          int RhsStorageOrder, bool ConjugateRhs> \\\nstruct product_triangular_matrix_matrix_trmm<EIGTYPE,Index,Mode,false, \\\n         LhsStorageOrder,ConjugateLhs,RhsStorageOrder,ConjugateRhs,ColMajor> \\\n{ \\\n  enum { \\\n    IsLower = (Mode&Lower) == Lower, \\\n    SetDiag = (Mode&(ZeroDiag|UnitDiag)) ? 0 : 1, \\\n    IsUnitDiag  = (Mode&UnitDiag) ? 1 : 0, \\\n    IsZeroDiag  = (Mode&ZeroDiag) ? 1 : 0, \\\n    LowUp = IsLower ? Lower : Upper, \\\n    conjA = ((RhsStorageOrder==ColMajor) && ConjugateRhs) ? 1 : 0 \\\n  }; \\\n\\\n  static void run( \\\n    Index _rows, Index _cols, Index _depth, \\\n    const EIGTYPE* _lhs, Index lhsStride, \\\n    const EIGTYPE* _rhs, Index rhsStride, \\\n    EIGTYPE* res,        Index resStride, \\\n    EIGTYPE alpha, level3_blocking<EIGTYPE,EIGTYPE>& blocking) \\\n  { \\\n   Index diagSize  = (std::min)(_cols,_depth); \\\n   Index rows      = _rows; \\\n   Index depth     = IsLower ? _depth : diagSize; \\\n   Index cols      = IsLower ? diagSize : _cols; \\\n\\\n   typedef Matrix<EIGTYPE, Dynamic, Dynamic, LhsStorageOrder> MatrixLhs; \\\n   typedef Matrix<EIGTYPE, Dynamic, Dynamic, RhsStorageOrder> MatrixRhs; \\\n\\\n/* Non-square case - doesn't fit to BLAS ?TRMM. Fall to default triangular product or call BLAS ?GEMM*/ \\\n   if (cols != depth) { \\\n\\\n     int nthr = 1 /*mkl_domain_get_max_threads(EIGEN_BLAS_DOMAIN_BLAS)*/; \\\n\\\n     if ((nthr==1) && (((std::max)(cols,depth)-diagSize)/(double)diagSize < 0.5)) { \\\n     /* Most likely no benefit to call TRMM or GEMM from BLAS*/ \\\n       product_triangular_matrix_matrix<EIGTYPE,Index,Mode,false, \\\n       LhsStorageOrder,ConjugateLhs, RhsStorageOrder, ConjugateRhs, ColMajor, BuiltIn>::run( \\\n           _rows, _cols, _depth, _lhs, lhsStride, _rhs, rhsStride, res, resStride, alpha, blocking); \\\n       /*std::cout << \"TRMM_R: A is not square! Go to Eigen TRMM implementation!\\n\";*/ \\\n     } else { \\\n     /* Make sense to call GEMM */ \\\n       Map<const MatrixRhs, 0, OuterStride<> > rhsMap(_rhs,depth,cols, OuterStride<>(rhsStride)); \\\n       MatrixRhs aa_tmp=rhsMap.template triangularView<Mode>(); \\\n       BlasIndex aStride = convert_index<BlasIndex>(aa_tmp.outerStride()); \\\n       gemm_blocking_space<ColMajor,EIGTYPE,EIGTYPE,Dynamic,Dynamic,Dynamic> gemm_blocking(_rows,_cols,_depth, 1, true); \\\n       general_matrix_matrix_product<Index,EIGTYPE,LhsStorageOrder,ConjugateLhs,EIGTYPE,RhsStorageOrder,ConjugateRhs,ColMajor>::run( \\\n       rows, cols, depth, _lhs, lhsStride, aa_tmp.data(), aStride, res, resStride, alpha, gemm_blocking, 0); \\\n\\\n     /*std::cout << \"TRMM_R: A is not square! Go to BLAS GEMM implementation! \" << nthr<<\" \\n\";*/ \\\n     } \\\n     return; \\\n   } \\\n   char side = 'R', transa, uplo, diag = 'N'; \\\n   EIGTYPE *b; \\\n   const EIGTYPE *a; \\\n   BlasIndex m, n, lda, ldb; \\\n\\\n/* Set m, n */ \\\n   m = convert_index<BlasIndex>(rows); \\\n   n = convert_index<BlasIndex>(diagSize); \\\n\\\n/* Set trans */ \\\n   transa = (RhsStorageOrder==RowMajor) ? ((ConjugateRhs) ? 'C' : 'T') : 'N'; \\\n\\\n/* Set b, ldb */ \\\n   Map<const MatrixLhs, 0, OuterStride<> > lhs(_lhs,rows,depth,OuterStride<>(lhsStride)); \\\n   MatrixX##EIGPREFIX b_tmp; \\\n\\\n   if (ConjugateLhs) b_tmp = lhs.conjugate(); else b_tmp = lhs; \\\n   b = b_tmp.data(); \\\n   ldb = convert_index<BlasIndex>(b_tmp.outerStride()); \\\n\\\n/* Set uplo */ \\\n   uplo = IsLower ? 'L' : 'U'; \\\n   if (RhsStorageOrder==RowMajor) uplo = (uplo == 'L') ? 'U' : 'L'; \\\n/* Set a, lda */ \\\n   Map<const MatrixRhs, 0, OuterStride<> > rhs(_rhs,depth,cols, OuterStride<>(rhsStride)); \\\n   MatrixRhs a_tmp; \\\n\\\n   if ((conjA!=0) || (SetDiag==0)) { \\\n     if (conjA) a_tmp = rhs.conjugate(); else a_tmp = rhs; \\\n     if (IsZeroDiag) \\\n       a_tmp.diagonal().setZero(); \\\n     else if (IsUnitDiag) \\\n       a_tmp.diagonal().setOnes();\\\n     a = a_tmp.data(); \\\n     lda = convert_index<BlasIndex>(a_tmp.outerStride()); \\\n   } else { \\\n     a = _rhs; \\\n     lda = convert_index<BlasIndex>(rhsStride); \\\n   } \\\n   /*std::cout << \"TRMM_R: A is square! Go to BLAS TRMM implementation! \\n\";*/ \\\n/* call ?trmm*/ \\\n   BLASPREFIX##trmm_(&side, &uplo, &transa, &diag, &m, &n, &numext::real_ref(alpha), (const BLASTYPE*)a, &lda, (BLASTYPE*)b, &ldb); \\\n\\\n/* Add op(a_triangular)*b into res*/ \\\n   Map<MatrixX##EIGPREFIX, 0, OuterStride<> > res_tmp(res,rows,cols,OuterStride<>(resStride)); \\\n   res_tmp=res_tmp+b_tmp; \\\n  } \\\n};\n\nEIGEN_BLAS_TRMM_R(double, double, d, d)\nEIGEN_BLAS_TRMM_R(dcomplex, double, cd, z)\nEIGEN_BLAS_TRMM_R(float, float, f, s)\nEIGEN_BLAS_TRMM_R(scomplex, float, cf, c)\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_TRIANGULAR_MATRIX_MATRIX_BLAS_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/products/TriangularMatrixVector.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_TRIANGULARMATRIXVECTOR_H\n#define EIGEN_TRIANGULARMATRIXVECTOR_H\n\nnamespace Eigen {\n\nnamespace internal {\n\ntemplate<typename Index, int Mode, typename LhsScalar, bool ConjLhs, typename RhsScalar, bool ConjRhs, int StorageOrder, int Version=Specialized>\nstruct triangular_matrix_vector_product;\n\ntemplate<typename Index, int Mode, typename LhsScalar, bool ConjLhs, typename RhsScalar, bool ConjRhs, int Version>\nstruct triangular_matrix_vector_product<Index,Mode,LhsScalar,ConjLhs,RhsScalar,ConjRhs,ColMajor,Version>\n{\n  typedef typename ScalarBinaryOpTraits<LhsScalar, RhsScalar>::ReturnType ResScalar;\n  enum {\n    IsLower = ((Mode&Lower)==Lower),\n    HasUnitDiag = (Mode & UnitDiag)==UnitDiag,\n    HasZeroDiag = (Mode & ZeroDiag)==ZeroDiag\n  };\n  static EIGEN_DONT_INLINE  void run(Index _rows, Index _cols, const LhsScalar* _lhs, Index lhsStride,\n                                     const RhsScalar* _rhs, Index rhsIncr, ResScalar* _res, Index resIncr, const RhsScalar& alpha);\n};\n\ntemplate<typename Index, int Mode, typename LhsScalar, bool ConjLhs, typename RhsScalar, bool ConjRhs, int Version>\nEIGEN_DONT_INLINE void triangular_matrix_vector_product<Index,Mode,LhsScalar,ConjLhs,RhsScalar,ConjRhs,ColMajor,Version>\n  ::run(Index _rows, Index _cols, const LhsScalar* _lhs, Index lhsStride,\n        const RhsScalar* _rhs, Index rhsIncr, ResScalar* _res, Index resIncr, const RhsScalar& alpha)\n  {\n    static const Index PanelWidth = EIGEN_TUNE_TRIANGULAR_PANEL_WIDTH;\n    Index size = (std::min)(_rows,_cols);\n    Index rows = IsLower ? _rows : (std::min)(_rows,_cols);\n    Index cols = IsLower ? (std::min)(_rows,_cols) : _cols;\n\n    typedef Map<const Matrix<LhsScalar,Dynamic,Dynamic,ColMajor>, 0, OuterStride<> > LhsMap;\n    const LhsMap lhs(_lhs,rows,cols,OuterStride<>(lhsStride));\n    typename conj_expr_if<ConjLhs,LhsMap>::type cjLhs(lhs);\n\n    typedef Map<const Matrix<RhsScalar,Dynamic,1>, 0, InnerStride<> > RhsMap;\n    const RhsMap rhs(_rhs,cols,InnerStride<>(rhsIncr));\n    typename conj_expr_if<ConjRhs,RhsMap>::type cjRhs(rhs);\n\n    typedef Map<Matrix<ResScalar,Dynamic,1> > ResMap;\n    ResMap res(_res,rows);\n\n    typedef const_blas_data_mapper<LhsScalar,Index,ColMajor> LhsMapper;\n    typedef const_blas_data_mapper<RhsScalar,Index,RowMajor> RhsMapper;\n\n    for (Index pi=0; pi<size; pi+=PanelWidth)\n    {\n      Index actualPanelWidth = (std::min)(PanelWidth, size-pi);\n      for (Index k=0; k<actualPanelWidth; ++k)\n      {\n        Index i = pi + k;\n        Index s = IsLower ? ((HasUnitDiag||HasZeroDiag) ? i+1 : i ) : pi;\n        Index r = IsLower ? actualPanelWidth-k : k+1;\n        if ((!(HasUnitDiag||HasZeroDiag)) || (--r)>0)\n          res.segment(s,r) += (alpha * cjRhs.coeff(i)) * cjLhs.col(i).segment(s,r);\n        if (HasUnitDiag)\n          res.coeffRef(i) += alpha * cjRhs.coeff(i);\n      }\n      Index r = IsLower ? rows - pi - actualPanelWidth : pi;\n      if (r>0)\n      {\n        Index s = IsLower ? pi+actualPanelWidth : 0;\n        general_matrix_vector_product<Index,LhsScalar,LhsMapper,ColMajor,ConjLhs,RhsScalar,RhsMapper,ConjRhs,BuiltIn>::run(\n            r, actualPanelWidth,\n            LhsMapper(&lhs.coeffRef(s,pi), lhsStride),\n            RhsMapper(&rhs.coeffRef(pi), rhsIncr),\n            &res.coeffRef(s), resIncr, alpha);\n      }\n    }\n    if((!IsLower) && cols>size)\n    {\n      general_matrix_vector_product<Index,LhsScalar,LhsMapper,ColMajor,ConjLhs,RhsScalar,RhsMapper,ConjRhs>::run(\n          rows, cols-size,\n          LhsMapper(&lhs.coeffRef(0,size), lhsStride),\n          RhsMapper(&rhs.coeffRef(size), rhsIncr),\n          _res, resIncr, alpha);\n    }\n  }\n\ntemplate<typename Index, int Mode, typename LhsScalar, bool ConjLhs, typename RhsScalar, bool ConjRhs,int Version>\nstruct triangular_matrix_vector_product<Index,Mode,LhsScalar,ConjLhs,RhsScalar,ConjRhs,RowMajor,Version>\n{\n  typedef typename ScalarBinaryOpTraits<LhsScalar, RhsScalar>::ReturnType ResScalar;\n  enum {\n    IsLower = ((Mode&Lower)==Lower),\n    HasUnitDiag = (Mode & UnitDiag)==UnitDiag,\n    HasZeroDiag = (Mode & ZeroDiag)==ZeroDiag\n  };\n  static EIGEN_DONT_INLINE void run(Index _rows, Index _cols, const LhsScalar* _lhs, Index lhsStride,\n                                    const RhsScalar* _rhs, Index rhsIncr, ResScalar* _res, Index resIncr, const ResScalar& alpha);\n};\n\ntemplate<typename Index, int Mode, typename LhsScalar, bool ConjLhs, typename RhsScalar, bool ConjRhs,int Version>\nEIGEN_DONT_INLINE void triangular_matrix_vector_product<Index,Mode,LhsScalar,ConjLhs,RhsScalar,ConjRhs,RowMajor,Version>\n  ::run(Index _rows, Index _cols, const LhsScalar* _lhs, Index lhsStride,\n        const RhsScalar* _rhs, Index rhsIncr, ResScalar* _res, Index resIncr, const ResScalar& alpha)\n  {\n    static const Index PanelWidth = EIGEN_TUNE_TRIANGULAR_PANEL_WIDTH;\n    Index diagSize = (std::min)(_rows,_cols);\n    Index rows = IsLower ? _rows : diagSize;\n    Index cols = IsLower ? diagSize : _cols;\n\n    typedef Map<const Matrix<LhsScalar,Dynamic,Dynamic,RowMajor>, 0, OuterStride<> > LhsMap;\n    const LhsMap lhs(_lhs,rows,cols,OuterStride<>(lhsStride));\n    typename conj_expr_if<ConjLhs,LhsMap>::type cjLhs(lhs);\n\n    typedef Map<const Matrix<RhsScalar,Dynamic,1> > RhsMap;\n    const RhsMap rhs(_rhs,cols);\n    typename conj_expr_if<ConjRhs,RhsMap>::type cjRhs(rhs);\n\n    typedef Map<Matrix<ResScalar,Dynamic,1>, 0, InnerStride<> > ResMap;\n    ResMap res(_res,rows,InnerStride<>(resIncr));\n\n    typedef const_blas_data_mapper<LhsScalar,Index,RowMajor> LhsMapper;\n    typedef const_blas_data_mapper<RhsScalar,Index,RowMajor> RhsMapper;\n\n    for (Index pi=0; pi<diagSize; pi+=PanelWidth)\n    {\n      Index actualPanelWidth = (std::min)(PanelWidth, diagSize-pi);\n      for (Index k=0; k<actualPanelWidth; ++k)\n      {\n        Index i = pi + k;\n        Index s = IsLower ? pi  : ((HasUnitDiag||HasZeroDiag) ? i+1 : i);\n        Index r = IsLower ? k+1 : actualPanelWidth-k;\n        if ((!(HasUnitDiag||HasZeroDiag)) || (--r)>0)\n          res.coeffRef(i) += alpha * (cjLhs.row(i).segment(s,r).cwiseProduct(cjRhs.segment(s,r).transpose())).sum();\n        if (HasUnitDiag)\n          res.coeffRef(i) += alpha * cjRhs.coeff(i);\n      }\n      Index r = IsLower ? pi : cols - pi - actualPanelWidth;\n      if (r>0)\n      {\n        Index s = IsLower ? 0 : pi + actualPanelWidth;\n        general_matrix_vector_product<Index,LhsScalar,LhsMapper,RowMajor,ConjLhs,RhsScalar,RhsMapper,ConjRhs,BuiltIn>::run(\n            actualPanelWidth, r,\n            LhsMapper(&lhs.coeffRef(pi,s), lhsStride),\n            RhsMapper(&rhs.coeffRef(s), rhsIncr),\n            &res.coeffRef(pi), resIncr, alpha);\n      }\n    }\n    if(IsLower && rows>diagSize)\n    {\n      general_matrix_vector_product<Index,LhsScalar,LhsMapper,RowMajor,ConjLhs,RhsScalar,RhsMapper,ConjRhs>::run(\n            rows-diagSize, cols,\n            LhsMapper(&lhs.coeffRef(diagSize,0), lhsStride),\n            RhsMapper(&rhs.coeffRef(0), rhsIncr),\n            &res.coeffRef(diagSize), resIncr, alpha);\n    }\n  }\n\n/***************************************************************************\n* Wrapper to product_triangular_vector\n***************************************************************************/\n\ntemplate<int Mode,int StorageOrder>\nstruct trmv_selector;\n\n} // end namespace internal\n\nnamespace internal {\n\ntemplate<int Mode, typename Lhs, typename Rhs>\nstruct triangular_product_impl<Mode,true,Lhs,false,Rhs,true>\n{\n  template<typename Dest> static void run(Dest& dst, const Lhs &lhs, const Rhs &rhs, const typename Dest::Scalar& alpha)\n  {\n    eigen_assert(dst.rows()==lhs.rows() && dst.cols()==rhs.cols());\n  \n    internal::trmv_selector<Mode,(int(internal::traits<Lhs>::Flags)&RowMajorBit) ? RowMajor : ColMajor>::run(lhs, rhs, dst, alpha);\n  }\n};\n\ntemplate<int Mode, typename Lhs, typename Rhs>\nstruct triangular_product_impl<Mode,false,Lhs,true,Rhs,false>\n{\n  template<typename Dest> static void run(Dest& dst, const Lhs &lhs, const Rhs &rhs, const typename Dest::Scalar& alpha)\n  {\n    eigen_assert(dst.rows()==lhs.rows() && dst.cols()==rhs.cols());\n\n    Transpose<Dest> dstT(dst);\n    internal::trmv_selector<(Mode & (UnitDiag|ZeroDiag)) | ((Mode & Lower) ? Upper : Lower),\n                            (int(internal::traits<Rhs>::Flags)&RowMajorBit) ? ColMajor : RowMajor>\n            ::run(rhs.transpose(),lhs.transpose(), dstT, alpha);\n  }\n};\n\n} // end namespace internal\n\nnamespace internal {\n\n// TODO: find a way to factorize this piece of code with gemv_selector since the logic is exactly the same.\n  \ntemplate<int Mode> struct trmv_selector<Mode,ColMajor>\n{\n  template<typename Lhs, typename Rhs, typename Dest>\n  static void run(const Lhs &lhs, const Rhs &rhs, Dest& dest, const typename Dest::Scalar& alpha)\n  {\n    typedef typename Lhs::Scalar      LhsScalar;\n    typedef typename Rhs::Scalar      RhsScalar;\n    typedef typename Dest::Scalar     ResScalar;\n    typedef typename Dest::RealScalar RealScalar;\n    \n    typedef internal::blas_traits<Lhs> LhsBlasTraits;\n    typedef typename LhsBlasTraits::DirectLinearAccessType ActualLhsType;\n    typedef internal::blas_traits<Rhs> RhsBlasTraits;\n    typedef typename RhsBlasTraits::DirectLinearAccessType ActualRhsType;\n    \n    typedef Map<Matrix<ResScalar,Dynamic,1>, EIGEN_PLAIN_ENUM_MIN(AlignedMax,internal::packet_traits<ResScalar>::size)> MappedDest;\n\n    typename internal::add_const_on_value_type<ActualLhsType>::type actualLhs = LhsBlasTraits::extract(lhs);\n    typename internal::add_const_on_value_type<ActualRhsType>::type actualRhs = RhsBlasTraits::extract(rhs);\n\n    ResScalar actualAlpha = alpha * LhsBlasTraits::extractScalarFactor(lhs)\n                                  * RhsBlasTraits::extractScalarFactor(rhs);\n\n    enum {\n      // FIXME find a way to allow an inner stride on the result if packet_traits<Scalar>::size==1\n      // on, the other hand it is good for the cache to pack the vector anyways...\n      EvalToDestAtCompileTime = Dest::InnerStrideAtCompileTime==1,\n      ComplexByReal = (NumTraits<LhsScalar>::IsComplex) && (!NumTraits<RhsScalar>::IsComplex),\n      MightCannotUseDest = (Dest::InnerStrideAtCompileTime!=1) || ComplexByReal\n    };\n\n    gemv_static_vector_if<ResScalar,Dest::SizeAtCompileTime,Dest::MaxSizeAtCompileTime,MightCannotUseDest> static_dest;\n\n    bool alphaIsCompatible = (!ComplexByReal) || (numext::imag(actualAlpha)==RealScalar(0));\n    bool evalToDest = EvalToDestAtCompileTime && alphaIsCompatible;\n\n    RhsScalar compatibleAlpha = get_factor<ResScalar,RhsScalar>::run(actualAlpha);\n\n    ei_declare_aligned_stack_constructed_variable(ResScalar,actualDestPtr,dest.size(),\n                                                  evalToDest ? dest.data() : static_dest.data());\n\n    if(!evalToDest)\n    {\n      #ifdef EIGEN_DENSE_STORAGE_CTOR_PLUGIN\n      Index size = dest.size();\n      EIGEN_DENSE_STORAGE_CTOR_PLUGIN\n      #endif\n      if(!alphaIsCompatible)\n      {\n        MappedDest(actualDestPtr, dest.size()).setZero();\n        compatibleAlpha = RhsScalar(1);\n      }\n      else\n        MappedDest(actualDestPtr, dest.size()) = dest;\n    }\n\n    internal::triangular_matrix_vector_product\n      <Index,Mode,\n       LhsScalar, LhsBlasTraits::NeedToConjugate,\n       RhsScalar, RhsBlasTraits::NeedToConjugate,\n       ColMajor>\n      ::run(actualLhs.rows(),actualLhs.cols(),\n            actualLhs.data(),actualLhs.outerStride(),\n            actualRhs.data(),actualRhs.innerStride(),\n            actualDestPtr,1,compatibleAlpha);\n\n    if (!evalToDest)\n    {\n      if(!alphaIsCompatible)\n        dest += actualAlpha * MappedDest(actualDestPtr, dest.size());\n      else\n        dest = MappedDest(actualDestPtr, dest.size());\n    }\n  }\n};\n\ntemplate<int Mode> struct trmv_selector<Mode,RowMajor>\n{\n  template<typename Lhs, typename Rhs, typename Dest>\n  static void run(const Lhs &lhs, const Rhs &rhs, Dest& dest, const typename Dest::Scalar& alpha)\n  {\n    typedef typename Lhs::Scalar      LhsScalar;\n    typedef typename Rhs::Scalar      RhsScalar;\n    typedef typename Dest::Scalar     ResScalar;\n    \n    typedef internal::blas_traits<Lhs> LhsBlasTraits;\n    typedef typename LhsBlasTraits::DirectLinearAccessType ActualLhsType;\n    typedef internal::blas_traits<Rhs> RhsBlasTraits;\n    typedef typename RhsBlasTraits::DirectLinearAccessType ActualRhsType;\n    typedef typename internal::remove_all<ActualRhsType>::type ActualRhsTypeCleaned;\n\n    typename add_const<ActualLhsType>::type actualLhs = LhsBlasTraits::extract(lhs);\n    typename add_const<ActualRhsType>::type actualRhs = RhsBlasTraits::extract(rhs);\n\n    ResScalar actualAlpha = alpha * LhsBlasTraits::extractScalarFactor(lhs)\n                                  * RhsBlasTraits::extractScalarFactor(rhs);\n\n    enum {\n      DirectlyUseRhs = ActualRhsTypeCleaned::InnerStrideAtCompileTime==1\n    };\n\n    gemv_static_vector_if<RhsScalar,ActualRhsTypeCleaned::SizeAtCompileTime,ActualRhsTypeCleaned::MaxSizeAtCompileTime,!DirectlyUseRhs> static_rhs;\n\n    ei_declare_aligned_stack_constructed_variable(RhsScalar,actualRhsPtr,actualRhs.size(),\n        DirectlyUseRhs ? const_cast<RhsScalar*>(actualRhs.data()) : static_rhs.data());\n\n    if(!DirectlyUseRhs)\n    {\n      #ifdef EIGEN_DENSE_STORAGE_CTOR_PLUGIN\n      Index size = actualRhs.size();\n      EIGEN_DENSE_STORAGE_CTOR_PLUGIN\n      #endif\n      Map<typename ActualRhsTypeCleaned::PlainObject>(actualRhsPtr, actualRhs.size()) = actualRhs;\n    }\n\n    internal::triangular_matrix_vector_product\n      <Index,Mode,\n       LhsScalar, LhsBlasTraits::NeedToConjugate,\n       RhsScalar, RhsBlasTraits::NeedToConjugate,\n       RowMajor>\n      ::run(actualLhs.rows(),actualLhs.cols(),\n            actualLhs.data(),actualLhs.outerStride(),\n            actualRhsPtr,1,\n            dest.data(),dest.innerStride(),\n            actualAlpha);\n  }\n};\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_TRIANGULARMATRIXVECTOR_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/products/TriangularMatrixVector_BLAS.h",
    "content": "/*\n Copyright (c) 2011, Intel Corporation. All rights reserved.\n\n Redistribution and use in source and binary forms, with or without modification,\n are permitted provided that the following conditions are met:\n\n * Redistributions of source code must retain the above copyright notice, this\n   list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright notice,\n   this list of conditions and the following disclaimer in the documentation\n   and/or other materials provided with the distribution.\n * Neither the name of Intel Corporation nor the names of its contributors may\n   be used to endorse or promote products derived from this software without\n   specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n ********************************************************************************\n *   Content : Eigen bindings to BLAS F77\n *   Triangular matrix-vector product functionality based on ?TRMV.\n ********************************************************************************\n*/\n\n#ifndef EIGEN_TRIANGULAR_MATRIX_VECTOR_BLAS_H\n#define EIGEN_TRIANGULAR_MATRIX_VECTOR_BLAS_H\n\nnamespace Eigen { \n\nnamespace internal {\n\n/**********************************************************************\n* This file implements triangular matrix-vector multiplication using BLAS\n**********************************************************************/\n\n// trmv/hemv specialization\n\ntemplate<typename Index, int Mode, typename LhsScalar, bool ConjLhs, typename RhsScalar, bool ConjRhs, int StorageOrder>\nstruct triangular_matrix_vector_product_trmv :\n  triangular_matrix_vector_product<Index,Mode,LhsScalar,ConjLhs,RhsScalar,ConjRhs,StorageOrder,BuiltIn> {};\n\n#define EIGEN_BLAS_TRMV_SPECIALIZE(Scalar) \\\ntemplate<typename Index, int Mode, bool ConjLhs, bool ConjRhs> \\\nstruct triangular_matrix_vector_product<Index,Mode,Scalar,ConjLhs,Scalar,ConjRhs,ColMajor,Specialized> { \\\n static void run(Index _rows, Index _cols, const Scalar* _lhs, Index lhsStride, \\\n                                     const Scalar* _rhs, Index rhsIncr, Scalar* _res, Index resIncr, Scalar alpha) { \\\n      triangular_matrix_vector_product_trmv<Index,Mode,Scalar,ConjLhs,Scalar,ConjRhs,ColMajor>::run( \\\n        _rows, _cols, _lhs, lhsStride, _rhs, rhsIncr, _res, resIncr, alpha); \\\n  } \\\n}; \\\ntemplate<typename Index, int Mode, bool ConjLhs, bool ConjRhs> \\\nstruct triangular_matrix_vector_product<Index,Mode,Scalar,ConjLhs,Scalar,ConjRhs,RowMajor,Specialized> { \\\n static void run(Index _rows, Index _cols, const Scalar* _lhs, Index lhsStride, \\\n                                     const Scalar* _rhs, Index rhsIncr, Scalar* _res, Index resIncr, Scalar alpha) { \\\n      triangular_matrix_vector_product_trmv<Index,Mode,Scalar,ConjLhs,Scalar,ConjRhs,RowMajor>::run( \\\n        _rows, _cols, _lhs, lhsStride, _rhs, rhsIncr, _res, resIncr, alpha); \\\n  } \\\n};\n\nEIGEN_BLAS_TRMV_SPECIALIZE(double)\nEIGEN_BLAS_TRMV_SPECIALIZE(float)\nEIGEN_BLAS_TRMV_SPECIALIZE(dcomplex)\nEIGEN_BLAS_TRMV_SPECIALIZE(scomplex)\n\n// implements col-major: res += alpha * op(triangular) * vector\n#define EIGEN_BLAS_TRMV_CM(EIGTYPE, BLASTYPE, EIGPREFIX, BLASPREFIX) \\\ntemplate<typename Index, int Mode, bool ConjLhs, bool ConjRhs> \\\nstruct triangular_matrix_vector_product_trmv<Index,Mode,EIGTYPE,ConjLhs,EIGTYPE,ConjRhs,ColMajor> { \\\n  enum { \\\n    IsLower = (Mode&Lower) == Lower, \\\n    SetDiag = (Mode&(ZeroDiag|UnitDiag)) ? 0 : 1, \\\n    IsUnitDiag  = (Mode&UnitDiag) ? 1 : 0, \\\n    IsZeroDiag  = (Mode&ZeroDiag) ? 1 : 0, \\\n    LowUp = IsLower ? Lower : Upper \\\n  }; \\\n static void run(Index _rows, Index _cols, const EIGTYPE* _lhs, Index lhsStride, \\\n                 const EIGTYPE* _rhs, Index rhsIncr, EIGTYPE* _res, Index resIncr, EIGTYPE alpha) \\\n { \\\n   if (ConjLhs || IsZeroDiag) { \\\n     triangular_matrix_vector_product<Index,Mode,EIGTYPE,ConjLhs,EIGTYPE,ConjRhs,ColMajor,BuiltIn>::run( \\\n       _rows, _cols, _lhs, lhsStride, _rhs, rhsIncr, _res, resIncr, alpha); \\\n     return; \\\n   }\\\n   Index size = (std::min)(_rows,_cols); \\\n   Index rows = IsLower ? _rows : size; \\\n   Index cols = IsLower ? size : _cols; \\\n\\\n   typedef VectorX##EIGPREFIX VectorRhs; \\\n   EIGTYPE *x, *y;\\\n\\\n/* Set x*/ \\\n   Map<const VectorRhs, 0, InnerStride<> > rhs(_rhs,cols,InnerStride<>(rhsIncr)); \\\n   VectorRhs x_tmp; \\\n   if (ConjRhs) x_tmp = rhs.conjugate(); else x_tmp = rhs; \\\n   x = x_tmp.data(); \\\n\\\n/* Square part handling */\\\n\\\n   char trans, uplo, diag; \\\n   BlasIndex m, n, lda, incx, incy; \\\n   EIGTYPE const *a; \\\n   EIGTYPE beta(1); \\\n\\\n/* Set m, n */ \\\n   n = convert_index<BlasIndex>(size); \\\n   lda = convert_index<BlasIndex>(lhsStride); \\\n   incx = 1; \\\n   incy = convert_index<BlasIndex>(resIncr); \\\n\\\n/* Set uplo, trans and diag*/ \\\n   trans = 'N'; \\\n   uplo = IsLower ? 'L' : 'U'; \\\n   diag = IsUnitDiag ? 'U' : 'N'; \\\n\\\n/* call ?TRMV*/ \\\n   BLASPREFIX##trmv_(&uplo, &trans, &diag, &n, (const BLASTYPE*)_lhs, &lda, (BLASTYPE*)x, &incx); \\\n\\\n/* Add op(a_tr)rhs into res*/ \\\n   BLASPREFIX##axpy_(&n, &numext::real_ref(alpha),(const BLASTYPE*)x, &incx, (BLASTYPE*)_res, &incy); \\\n/* Non-square case - doesn't fit to BLAS ?TRMV. Fall to default triangular product*/ \\\n   if (size<(std::max)(rows,cols)) { \\\n     if (ConjRhs) x_tmp = rhs.conjugate(); else x_tmp = rhs; \\\n     x = x_tmp.data(); \\\n     if (size<rows) { \\\n       y = _res + size*resIncr; \\\n       a = _lhs + size; \\\n       m = convert_index<BlasIndex>(rows-size); \\\n       n = convert_index<BlasIndex>(size); \\\n     } \\\n     else { \\\n       x += size; \\\n       y = _res; \\\n       a = _lhs + size*lda; \\\n       m = convert_index<BlasIndex>(size); \\\n       n = convert_index<BlasIndex>(cols-size); \\\n     } \\\n     BLASPREFIX##gemv_(&trans, &m, &n, &numext::real_ref(alpha), (const BLASTYPE*)a, &lda, (const BLASTYPE*)x, &incx, &numext::real_ref(beta), (BLASTYPE*)y, &incy); \\\n   } \\\n  } \\\n};\n\nEIGEN_BLAS_TRMV_CM(double,   double, d,  d)\nEIGEN_BLAS_TRMV_CM(dcomplex, double, cd, z)\nEIGEN_BLAS_TRMV_CM(float,    float,  f,  s)\nEIGEN_BLAS_TRMV_CM(scomplex, float,  cf, c)\n\n// implements row-major: res += alpha * op(triangular) * vector\n#define EIGEN_BLAS_TRMV_RM(EIGTYPE, BLASTYPE, EIGPREFIX, BLASPREFIX) \\\ntemplate<typename Index, int Mode, bool ConjLhs, bool ConjRhs> \\\nstruct triangular_matrix_vector_product_trmv<Index,Mode,EIGTYPE,ConjLhs,EIGTYPE,ConjRhs,RowMajor> { \\\n  enum { \\\n    IsLower = (Mode&Lower) == Lower, \\\n    SetDiag = (Mode&(ZeroDiag|UnitDiag)) ? 0 : 1, \\\n    IsUnitDiag  = (Mode&UnitDiag) ? 1 : 0, \\\n    IsZeroDiag  = (Mode&ZeroDiag) ? 1 : 0, \\\n    LowUp = IsLower ? Lower : Upper \\\n  }; \\\n static void run(Index _rows, Index _cols, const EIGTYPE* _lhs, Index lhsStride, \\\n                 const EIGTYPE* _rhs, Index rhsIncr, EIGTYPE* _res, Index resIncr, EIGTYPE alpha) \\\n { \\\n   if (IsZeroDiag) { \\\n     triangular_matrix_vector_product<Index,Mode,EIGTYPE,ConjLhs,EIGTYPE,ConjRhs,RowMajor,BuiltIn>::run( \\\n       _rows, _cols, _lhs, lhsStride, _rhs, rhsIncr, _res, resIncr, alpha); \\\n     return; \\\n   }\\\n   Index size = (std::min)(_rows,_cols); \\\n   Index rows = IsLower ? _rows : size; \\\n   Index cols = IsLower ? size : _cols; \\\n\\\n   typedef VectorX##EIGPREFIX VectorRhs; \\\n   EIGTYPE *x, *y;\\\n\\\n/* Set x*/ \\\n   Map<const VectorRhs, 0, InnerStride<> > rhs(_rhs,cols,InnerStride<>(rhsIncr)); \\\n   VectorRhs x_tmp; \\\n   if (ConjRhs) x_tmp = rhs.conjugate(); else x_tmp = rhs; \\\n   x = x_tmp.data(); \\\n\\\n/* Square part handling */\\\n\\\n   char trans, uplo, diag; \\\n   BlasIndex m, n, lda, incx, incy; \\\n   EIGTYPE const *a; \\\n   EIGTYPE beta(1); \\\n\\\n/* Set m, n */ \\\n   n = convert_index<BlasIndex>(size); \\\n   lda = convert_index<BlasIndex>(lhsStride); \\\n   incx = 1; \\\n   incy = convert_index<BlasIndex>(resIncr); \\\n\\\n/* Set uplo, trans and diag*/ \\\n   trans = ConjLhs ? 'C' : 'T'; \\\n   uplo = IsLower ? 'U' : 'L'; \\\n   diag = IsUnitDiag ? 'U' : 'N'; \\\n\\\n/* call ?TRMV*/ \\\n   BLASPREFIX##trmv_(&uplo, &trans, &diag, &n, (const BLASTYPE*)_lhs, &lda, (BLASTYPE*)x, &incx); \\\n\\\n/* Add op(a_tr)rhs into res*/ \\\n   BLASPREFIX##axpy_(&n, &numext::real_ref(alpha),(const BLASTYPE*)x, &incx, (BLASTYPE*)_res, &incy); \\\n/* Non-square case - doesn't fit to BLAS ?TRMV. Fall to default triangular product*/ \\\n   if (size<(std::max)(rows,cols)) { \\\n     if (ConjRhs) x_tmp = rhs.conjugate(); else x_tmp = rhs; \\\n     x = x_tmp.data(); \\\n     if (size<rows) { \\\n       y = _res + size*resIncr; \\\n       a = _lhs + size*lda; \\\n       m = convert_index<BlasIndex>(rows-size); \\\n       n = convert_index<BlasIndex>(size); \\\n     } \\\n     else { \\\n       x += size; \\\n       y = _res; \\\n       a = _lhs + size; \\\n       m = convert_index<BlasIndex>(size); \\\n       n = convert_index<BlasIndex>(cols-size); \\\n     } \\\n     BLASPREFIX##gemv_(&trans, &n, &m, &numext::real_ref(alpha), (const BLASTYPE*)a, &lda, (const BLASTYPE*)x, &incx, &numext::real_ref(beta), (BLASTYPE*)y, &incy); \\\n   } \\\n  } \\\n};\n\nEIGEN_BLAS_TRMV_RM(double,   double, d,  d)\nEIGEN_BLAS_TRMV_RM(dcomplex, double, cd, z)\nEIGEN_BLAS_TRMV_RM(float,    float,  f,  s)\nEIGEN_BLAS_TRMV_RM(scomplex, float,  cf, c)\n\n} // end namespase internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_TRIANGULAR_MATRIX_VECTOR_BLAS_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/products/TriangularSolverMatrix.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_TRIANGULAR_SOLVER_MATRIX_H\n#define EIGEN_TRIANGULAR_SOLVER_MATRIX_H\n\nnamespace Eigen { \n\nnamespace internal {\n\n// if the rhs is row major, let's transpose the product\ntemplate <typename Scalar, typename Index, int Side, int Mode, bool Conjugate, int TriStorageOrder>\nstruct triangular_solve_matrix<Scalar,Index,Side,Mode,Conjugate,TriStorageOrder,RowMajor>\n{\n  static void run(\n    Index size, Index cols,\n    const Scalar*  tri, Index triStride,\n    Scalar* _other, Index otherStride,\n    level3_blocking<Scalar,Scalar>& blocking)\n  {\n    triangular_solve_matrix<\n      Scalar, Index, Side==OnTheLeft?OnTheRight:OnTheLeft,\n      (Mode&UnitDiag) | ((Mode&Upper) ? Lower : Upper),\n      NumTraits<Scalar>::IsComplex && Conjugate,\n      TriStorageOrder==RowMajor ? ColMajor : RowMajor, ColMajor>\n      ::run(size, cols, tri, triStride, _other, otherStride, blocking);\n  }\n};\n\n/* Optimized triangular solver with multiple right hand side and the triangular matrix on the left\n */\ntemplate <typename Scalar, typename Index, int Mode, bool Conjugate, int TriStorageOrder>\nstruct triangular_solve_matrix<Scalar,Index,OnTheLeft,Mode,Conjugate,TriStorageOrder,ColMajor>\n{\n  static EIGEN_DONT_INLINE void run(\n    Index size, Index otherSize,\n    const Scalar* _tri, Index triStride,\n    Scalar* _other, Index otherStride,\n    level3_blocking<Scalar,Scalar>& blocking);\n};\ntemplate <typename Scalar, typename Index, int Mode, bool Conjugate, int TriStorageOrder>\nEIGEN_DONT_INLINE void triangular_solve_matrix<Scalar,Index,OnTheLeft,Mode,Conjugate,TriStorageOrder,ColMajor>::run(\n    Index size, Index otherSize,\n    const Scalar* _tri, Index triStride,\n    Scalar* _other, Index otherStride,\n    level3_blocking<Scalar,Scalar>& blocking)\n  {\n    Index cols = otherSize;\n\n    typedef const_blas_data_mapper<Scalar, Index, TriStorageOrder> TriMapper;\n    typedef blas_data_mapper<Scalar, Index, ColMajor> OtherMapper;\n    TriMapper tri(_tri, triStride);\n    OtherMapper other(_other, otherStride);\n\n    typedef gebp_traits<Scalar,Scalar> Traits;\n\n    enum {\n      SmallPanelWidth   = EIGEN_PLAIN_ENUM_MAX(Traits::mr,Traits::nr),\n      IsLower = (Mode&Lower) == Lower\n    };\n\n    Index kc = blocking.kc();                   // cache block size along the K direction\n    Index mc = (std::min)(size,blocking.mc());  // cache block size along the M direction\n\n    std::size_t sizeA = kc*mc;\n    std::size_t sizeB = kc*cols;\n\n    ei_declare_aligned_stack_constructed_variable(Scalar, blockA, sizeA, blocking.blockA());\n    ei_declare_aligned_stack_constructed_variable(Scalar, blockB, sizeB, blocking.blockB());\n\n    conj_if<Conjugate> conj;\n    gebp_kernel<Scalar, Scalar, Index, OtherMapper, Traits::mr, Traits::nr, Conjugate, false> gebp_kernel;\n    gemm_pack_lhs<Scalar, Index, TriMapper, Traits::mr, Traits::LhsProgress, TriStorageOrder> pack_lhs;\n    gemm_pack_rhs<Scalar, Index, OtherMapper, Traits::nr, ColMajor, false, true> pack_rhs;\n\n    // the goal here is to subdivise the Rhs panels such that we keep some cache\n    // coherence when accessing the rhs elements\n    std::ptrdiff_t l1, l2, l3;\n    manage_caching_sizes(GetAction, &l1, &l2, &l3);\n    Index subcols = cols>0 ? l2/(4 * sizeof(Scalar) * std::max<Index>(otherStride,size)) : 0;\n    subcols = std::max<Index>((subcols/Traits::nr)*Traits::nr, Traits::nr);\n\n    for(Index k2=IsLower ? 0 : size;\n        IsLower ? k2<size : k2>0;\n        IsLower ? k2+=kc : k2-=kc)\n    {\n      const Index actual_kc = (std::min)(IsLower ? size-k2 : k2, kc);\n\n      // We have selected and packed a big horizontal panel R1 of rhs. Let B be the packed copy of this panel,\n      // and R2 the remaining part of rhs. The corresponding vertical panel of lhs is split into\n      // A11 (the triangular part) and A21 the remaining rectangular part.\n      // Then the high level algorithm is:\n      //  - B = R1                    => general block copy (done during the next step)\n      //  - R1 = A11^-1 B             => tricky part\n      //  - update B from the new R1  => actually this has to be performed continuously during the above step\n      //  - R2 -= A21 * B             => GEPP\n\n      // The tricky part: compute R1 = A11^-1 B while updating B from R1\n      // The idea is to split A11 into multiple small vertical panels.\n      // Each panel can be split into a small triangular part T1k which is processed without optimization,\n      // and the remaining small part T2k which is processed using gebp with appropriate block strides\n      for(Index j2=0; j2<cols; j2+=subcols)\n      {\n        Index actual_cols = (std::min)(cols-j2,subcols);\n        // for each small vertical panels [T1k^T, T2k^T]^T of lhs\n        for (Index k1=0; k1<actual_kc; k1+=SmallPanelWidth)\n        {\n          Index actualPanelWidth = std::min<Index>(actual_kc-k1, SmallPanelWidth);\n          // tr solve\n          for (Index k=0; k<actualPanelWidth; ++k)\n          {\n            // TODO write a small kernel handling this (can be shared with trsv)\n            Index i  = IsLower ? k2+k1+k : k2-k1-k-1;\n            Index rs = actualPanelWidth - k - 1; // remaining size\n            Index s  = TriStorageOrder==RowMajor ? (IsLower ? k2+k1 : i+1)\n                                                 :  IsLower ? i+1 : i-rs;\n\n            Scalar a = (Mode & UnitDiag) ? Scalar(1) : Scalar(1)/conj(tri(i,i));\n            for (Index j=j2; j<j2+actual_cols; ++j)\n            {\n              if (TriStorageOrder==RowMajor)\n              {\n                Scalar b(0);\n                const Scalar* l = &tri(i,s);\n                Scalar* r = &other(s,j);\n                for (Index i3=0; i3<k; ++i3)\n                  b += conj(l[i3]) * r[i3];\n\n                other(i,j) = (other(i,j) - b)*a;\n              }\n              else\n              {\n                Scalar b = (other(i,j) *= a);\n                Scalar* r = &other(s,j);\n                const Scalar* l = &tri(s,i);\n                for (Index i3=0;i3<rs;++i3)\n                  r[i3] -= b * conj(l[i3]);\n              }\n            }\n          }\n\n          Index lengthTarget = actual_kc-k1-actualPanelWidth;\n          Index startBlock   = IsLower ? k2+k1 : k2-k1-actualPanelWidth;\n          Index blockBOffset = IsLower ? k1 : lengthTarget;\n\n          // update the respective rows of B from other\n          pack_rhs(blockB+actual_kc*j2, other.getSubMapper(startBlock,j2), actualPanelWidth, actual_cols, actual_kc, blockBOffset);\n\n          // GEBP\n          if (lengthTarget>0)\n          {\n            Index startTarget  = IsLower ? k2+k1+actualPanelWidth : k2-actual_kc;\n\n            pack_lhs(blockA, tri.getSubMapper(startTarget,startBlock), actualPanelWidth, lengthTarget);\n\n            gebp_kernel(other.getSubMapper(startTarget,j2), blockA, blockB+actual_kc*j2, lengthTarget, actualPanelWidth, actual_cols, Scalar(-1),\n                        actualPanelWidth, actual_kc, 0, blockBOffset);\n          }\n        }\n      }\n      \n      // R2 -= A21 * B => GEPP\n      {\n        Index start = IsLower ? k2+kc : 0;\n        Index end   = IsLower ? size : k2-kc;\n        for(Index i2=start; i2<end; i2+=mc)\n        {\n          const Index actual_mc = (std::min)(mc,end-i2);\n          if (actual_mc>0)\n          {\n            pack_lhs(blockA, tri.getSubMapper(i2, IsLower ? k2 : k2-kc), actual_kc, actual_mc);\n\n            gebp_kernel(other.getSubMapper(i2, 0), blockA, blockB, actual_mc, actual_kc, cols, Scalar(-1), -1, -1, 0, 0);\n          }\n        }\n      }\n    }\n  }\n\n/* Optimized triangular solver with multiple left hand sides and the trinagular matrix on the right\n */\ntemplate <typename Scalar, typename Index, int Mode, bool Conjugate, int TriStorageOrder>\nstruct triangular_solve_matrix<Scalar,Index,OnTheRight,Mode,Conjugate,TriStorageOrder,ColMajor>\n{\n  static EIGEN_DONT_INLINE void run(\n    Index size, Index otherSize,\n    const Scalar* _tri, Index triStride,\n    Scalar* _other, Index otherStride,\n    level3_blocking<Scalar,Scalar>& blocking);\n};\ntemplate <typename Scalar, typename Index, int Mode, bool Conjugate, int TriStorageOrder>\nEIGEN_DONT_INLINE void triangular_solve_matrix<Scalar,Index,OnTheRight,Mode,Conjugate,TriStorageOrder,ColMajor>::run(\n    Index size, Index otherSize,\n    const Scalar* _tri, Index triStride,\n    Scalar* _other, Index otherStride,\n    level3_blocking<Scalar,Scalar>& blocking)\n  {\n    Index rows = otherSize;\n\n    typedef blas_data_mapper<Scalar, Index, ColMajor> LhsMapper;\n    typedef const_blas_data_mapper<Scalar, Index, TriStorageOrder> RhsMapper;\n    LhsMapper lhs(_other, otherStride);\n    RhsMapper rhs(_tri, triStride);\n\n    typedef gebp_traits<Scalar,Scalar> Traits;\n    enum {\n      RhsStorageOrder   = TriStorageOrder,\n      SmallPanelWidth   = EIGEN_PLAIN_ENUM_MAX(Traits::mr,Traits::nr),\n      IsLower = (Mode&Lower) == Lower\n    };\n\n    Index kc = blocking.kc();                   // cache block size along the K direction\n    Index mc = (std::min)(rows,blocking.mc());  // cache block size along the M direction\n\n    std::size_t sizeA = kc*mc;\n    std::size_t sizeB = kc*size;\n\n    ei_declare_aligned_stack_constructed_variable(Scalar, blockA, sizeA, blocking.blockA());\n    ei_declare_aligned_stack_constructed_variable(Scalar, blockB, sizeB, blocking.blockB());\n\n    conj_if<Conjugate> conj;\n    gebp_kernel<Scalar, Scalar, Index, LhsMapper, Traits::mr, Traits::nr, false, Conjugate> gebp_kernel;\n    gemm_pack_rhs<Scalar, Index, RhsMapper, Traits::nr, RhsStorageOrder> pack_rhs;\n    gemm_pack_rhs<Scalar, Index, RhsMapper, Traits::nr, RhsStorageOrder,false,true> pack_rhs_panel;\n    gemm_pack_lhs<Scalar, Index, LhsMapper, Traits::mr, Traits::LhsProgress, ColMajor, false, true> pack_lhs_panel;\n\n    for(Index k2=IsLower ? size : 0;\n        IsLower ? k2>0 : k2<size;\n        IsLower ? k2-=kc : k2+=kc)\n    {\n      const Index actual_kc = (std::min)(IsLower ? k2 : size-k2, kc);\n      Index actual_k2 = IsLower ? k2-actual_kc : k2 ;\n\n      Index startPanel = IsLower ? 0 : k2+actual_kc;\n      Index rs = IsLower ? actual_k2 : size - actual_k2 - actual_kc;\n      Scalar* geb = blockB+actual_kc*actual_kc;\n\n      if (rs>0) pack_rhs(geb, rhs.getSubMapper(actual_k2,startPanel), actual_kc, rs);\n\n      // triangular packing (we only pack the panels off the diagonal,\n      // neglecting the blocks overlapping the diagonal\n      {\n        for (Index j2=0; j2<actual_kc; j2+=SmallPanelWidth)\n        {\n          Index actualPanelWidth = std::min<Index>(actual_kc-j2, SmallPanelWidth);\n          Index actual_j2 = actual_k2 + j2;\n          Index panelOffset = IsLower ? j2+actualPanelWidth : 0;\n          Index panelLength = IsLower ? actual_kc-j2-actualPanelWidth : j2;\n\n          if (panelLength>0)\n          pack_rhs_panel(blockB+j2*actual_kc,\n                         rhs.getSubMapper(actual_k2+panelOffset, actual_j2),\n                         panelLength, actualPanelWidth,\n                         actual_kc, panelOffset);\n        }\n      }\n\n      for(Index i2=0; i2<rows; i2+=mc)\n      {\n        const Index actual_mc = (std::min)(mc,rows-i2);\n\n        // triangular solver kernel\n        {\n          // for each small block of the diagonal (=> vertical panels of rhs)\n          for (Index j2 = IsLower\n                      ? (actual_kc - ((actual_kc%SmallPanelWidth) ? Index(actual_kc%SmallPanelWidth)\n                                                                  : Index(SmallPanelWidth)))\n                      : 0;\n               IsLower ? j2>=0 : j2<actual_kc;\n               IsLower ? j2-=SmallPanelWidth : j2+=SmallPanelWidth)\n          {\n            Index actualPanelWidth = std::min<Index>(actual_kc-j2, SmallPanelWidth);\n            Index absolute_j2 = actual_k2 + j2;\n            Index panelOffset = IsLower ? j2+actualPanelWidth : 0;\n            Index panelLength = IsLower ? actual_kc - j2 - actualPanelWidth : j2;\n\n            // GEBP\n            if(panelLength>0)\n            {\n              gebp_kernel(lhs.getSubMapper(i2,absolute_j2),\n                          blockA, blockB+j2*actual_kc,\n                          actual_mc, panelLength, actualPanelWidth,\n                          Scalar(-1),\n                          actual_kc, actual_kc, // strides\n                          panelOffset, panelOffset); // offsets\n            }\n\n            // unblocked triangular solve\n            for (Index k=0; k<actualPanelWidth; ++k)\n            {\n              Index j = IsLower ? absolute_j2+actualPanelWidth-k-1 : absolute_j2+k;\n\n              Scalar* r = &lhs(i2,j);\n              for (Index k3=0; k3<k; ++k3)\n              {\n                Scalar b = conj(rhs(IsLower ? j+1+k3 : absolute_j2+k3,j));\n                Scalar* a = &lhs(i2,IsLower ? j+1+k3 : absolute_j2+k3);\n                for (Index i=0; i<actual_mc; ++i)\n                  r[i] -= a[i] * b;\n              }\n              if((Mode & UnitDiag)==0)\n              {\n                Scalar b = conj(rhs(j,j));\n                for (Index i=0; i<actual_mc; ++i)\n                  r[i] /= b;\n              }\n            }\n\n            // pack the just computed part of lhs to A\n            pack_lhs_panel(blockA, LhsMapper(_other+absolute_j2*otherStride+i2, otherStride),\n                           actualPanelWidth, actual_mc,\n                           actual_kc, j2);\n          }\n        }\n\n        if (rs>0)\n          gebp_kernel(lhs.getSubMapper(i2, startPanel), blockA, geb,\n                      actual_mc, actual_kc, rs, Scalar(-1),\n                      -1, -1, 0, 0);\n      }\n    }\n  }\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_TRIANGULAR_SOLVER_MATRIX_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/products/TriangularSolverMatrix_BLAS.h",
    "content": "/*\n Copyright (c) 2011, Intel Corporation. All rights reserved.\n\n Redistribution and use in source and binary forms, with or without modification,\n are permitted provided that the following conditions are met:\n\n * Redistributions of source code must retain the above copyright notice, this\n   list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright notice,\n   this list of conditions and the following disclaimer in the documentation\n   and/or other materials provided with the distribution.\n * Neither the name of Intel Corporation nor the names of its contributors may\n   be used to endorse or promote products derived from this software without\n   specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n ********************************************************************************\n *   Content : Eigen bindings to BLAS F77\n *   Triangular matrix * matrix product functionality based on ?TRMM.\n ********************************************************************************\n*/\n\n#ifndef EIGEN_TRIANGULAR_SOLVER_MATRIX_BLAS_H\n#define EIGEN_TRIANGULAR_SOLVER_MATRIX_BLAS_H\n\nnamespace Eigen {\n\nnamespace internal {\n\n// implements LeftSide op(triangular)^-1 * general\n#define EIGEN_BLAS_TRSM_L(EIGTYPE, BLASTYPE, BLASPREFIX) \\\ntemplate <typename Index, int Mode, bool Conjugate, int TriStorageOrder> \\\nstruct triangular_solve_matrix<EIGTYPE,Index,OnTheLeft,Mode,Conjugate,TriStorageOrder,ColMajor> \\\n{ \\\n  enum { \\\n    IsLower = (Mode&Lower) == Lower, \\\n    IsUnitDiag  = (Mode&UnitDiag) ? 1 : 0, \\\n    IsZeroDiag  = (Mode&ZeroDiag) ? 1 : 0, \\\n    conjA = ((TriStorageOrder==ColMajor) && Conjugate) ? 1 : 0 \\\n  }; \\\n  static void run( \\\n      Index size, Index otherSize, \\\n      const EIGTYPE* _tri, Index triStride, \\\n      EIGTYPE* _other, Index otherStride, level3_blocking<EIGTYPE,EIGTYPE>& /*blocking*/) \\\n  { \\\n   BlasIndex m = convert_index<BlasIndex>(size), n = convert_index<BlasIndex>(otherSize), lda, ldb; \\\n   char side = 'L', uplo, diag='N', transa; \\\n   /* Set alpha_ */ \\\n   EIGTYPE alpha(1); \\\n   ldb = convert_index<BlasIndex>(otherStride);\\\n\\\n   const EIGTYPE *a; \\\n/* Set trans */ \\\n   transa = (TriStorageOrder==RowMajor) ? ((Conjugate) ? 'C' : 'T') : 'N'; \\\n/* Set uplo */ \\\n   uplo = IsLower ? 'L' : 'U'; \\\n   if (TriStorageOrder==RowMajor) uplo = (uplo == 'L') ? 'U' : 'L'; \\\n/* Set a, lda */ \\\n   typedef Matrix<EIGTYPE, Dynamic, Dynamic, TriStorageOrder> MatrixTri; \\\n   Map<const MatrixTri, 0, OuterStride<> > tri(_tri,size,size,OuterStride<>(triStride)); \\\n   MatrixTri a_tmp; \\\n\\\n   if (conjA) { \\\n     a_tmp = tri.conjugate(); \\\n     a = a_tmp.data(); \\\n     lda = convert_index<BlasIndex>(a_tmp.outerStride()); \\\n   } else { \\\n     a = _tri; \\\n     lda = convert_index<BlasIndex>(triStride); \\\n   } \\\n   if (IsUnitDiag) diag='U'; \\\n/* call ?trsm*/ \\\n   BLASPREFIX##trsm_(&side, &uplo, &transa, &diag, &m, &n, &numext::real_ref(alpha), (const BLASTYPE*)a, &lda, (BLASTYPE*)_other, &ldb); \\\n } \\\n};\n\nEIGEN_BLAS_TRSM_L(double,   double, d)\nEIGEN_BLAS_TRSM_L(dcomplex, double, z)\nEIGEN_BLAS_TRSM_L(float,    float,  s)\nEIGEN_BLAS_TRSM_L(scomplex, float,  c)\n\n\n// implements RightSide general * op(triangular)^-1\n#define EIGEN_BLAS_TRSM_R(EIGTYPE, BLASTYPE, BLASPREFIX) \\\ntemplate <typename Index, int Mode, bool Conjugate, int TriStorageOrder> \\\nstruct triangular_solve_matrix<EIGTYPE,Index,OnTheRight,Mode,Conjugate,TriStorageOrder,ColMajor> \\\n{ \\\n  enum { \\\n    IsLower = (Mode&Lower) == Lower, \\\n    IsUnitDiag  = (Mode&UnitDiag) ? 1 : 0, \\\n    IsZeroDiag  = (Mode&ZeroDiag) ? 1 : 0, \\\n    conjA = ((TriStorageOrder==ColMajor) && Conjugate) ? 1 : 0 \\\n  }; \\\n  static void run( \\\n      Index size, Index otherSize, \\\n      const EIGTYPE* _tri, Index triStride, \\\n      EIGTYPE* _other, Index otherStride, level3_blocking<EIGTYPE,EIGTYPE>& /*blocking*/) \\\n  { \\\n   BlasIndex m = convert_index<BlasIndex>(otherSize), n = convert_index<BlasIndex>(size), lda, ldb; \\\n   char side = 'R', uplo, diag='N', transa; \\\n   /* Set alpha_ */ \\\n   EIGTYPE alpha(1); \\\n   ldb = convert_index<BlasIndex>(otherStride);\\\n\\\n   const EIGTYPE *a; \\\n/* Set trans */ \\\n   transa = (TriStorageOrder==RowMajor) ? ((Conjugate) ? 'C' : 'T') : 'N'; \\\n/* Set uplo */ \\\n   uplo = IsLower ? 'L' : 'U'; \\\n   if (TriStorageOrder==RowMajor) uplo = (uplo == 'L') ? 'U' : 'L'; \\\n/* Set a, lda */ \\\n   typedef Matrix<EIGTYPE, Dynamic, Dynamic, TriStorageOrder> MatrixTri; \\\n   Map<const MatrixTri, 0, OuterStride<> > tri(_tri,size,size,OuterStride<>(triStride)); \\\n   MatrixTri a_tmp; \\\n\\\n   if (conjA) { \\\n     a_tmp = tri.conjugate(); \\\n     a = a_tmp.data(); \\\n     lda = convert_index<BlasIndex>(a_tmp.outerStride()); \\\n   } else { \\\n     a = _tri; \\\n     lda = convert_index<BlasIndex>(triStride); \\\n   } \\\n   if (IsUnitDiag) diag='U'; \\\n/* call ?trsm*/ \\\n   BLASPREFIX##trsm_(&side, &uplo, &transa, &diag, &m, &n, &numext::real_ref(alpha), (const BLASTYPE*)a, &lda, (BLASTYPE*)_other, &ldb); \\\n   /*std::cout << \"TRMS_L specialization!\\n\";*/ \\\n } \\\n};\n\nEIGEN_BLAS_TRSM_R(double,   double, d)\nEIGEN_BLAS_TRSM_R(dcomplex, double, z)\nEIGEN_BLAS_TRSM_R(float,    float,  s)\nEIGEN_BLAS_TRSM_R(scomplex, float,  c)\n\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_TRIANGULAR_SOLVER_MATRIX_BLAS_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/products/TriangularSolverVector.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_TRIANGULAR_SOLVER_VECTOR_H\n#define EIGEN_TRIANGULAR_SOLVER_VECTOR_H\n\nnamespace Eigen {\n\nnamespace internal {\n\ntemplate<typename LhsScalar, typename RhsScalar, typename Index, int Mode, bool Conjugate, int StorageOrder>\nstruct triangular_solve_vector<LhsScalar, RhsScalar, Index, OnTheRight, Mode, Conjugate, StorageOrder>\n{\n  static void run(Index size, const LhsScalar* _lhs, Index lhsStride, RhsScalar* rhs)\n  {\n    triangular_solve_vector<LhsScalar,RhsScalar,Index,OnTheLeft,\n        ((Mode&Upper)==Upper ? Lower : Upper) | (Mode&UnitDiag),\n        Conjugate,StorageOrder==RowMajor?ColMajor:RowMajor\n      >::run(size, _lhs, lhsStride, rhs);\n  }\n};\n\n// forward and backward substitution, row-major, rhs is a vector\ntemplate<typename LhsScalar, typename RhsScalar, typename Index, int Mode, bool Conjugate>\nstruct triangular_solve_vector<LhsScalar, RhsScalar, Index, OnTheLeft, Mode, Conjugate, RowMajor>\n{\n  enum {\n    IsLower = ((Mode&Lower)==Lower)\n  };\n  static void run(Index size, const LhsScalar* _lhs, Index lhsStride, RhsScalar* rhs)\n  {\n    typedef Map<const Matrix<LhsScalar,Dynamic,Dynamic,RowMajor>, 0, OuterStride<> > LhsMap;\n    const LhsMap lhs(_lhs,size,size,OuterStride<>(lhsStride));\n\n    typedef const_blas_data_mapper<LhsScalar,Index,RowMajor> LhsMapper;\n    typedef const_blas_data_mapper<RhsScalar,Index,ColMajor> RhsMapper;\n\n    typename internal::conditional<\n                          Conjugate,\n                          const CwiseUnaryOp<typename internal::scalar_conjugate_op<LhsScalar>,LhsMap>,\n                          const LhsMap&>\n                        ::type cjLhs(lhs);\n    static const Index PanelWidth = EIGEN_TUNE_TRIANGULAR_PANEL_WIDTH;\n    for(Index pi=IsLower ? 0 : size;\n        IsLower ? pi<size : pi>0;\n        IsLower ? pi+=PanelWidth : pi-=PanelWidth)\n    {\n      Index actualPanelWidth = (std::min)(IsLower ? size - pi : pi, PanelWidth);\n\n      Index r = IsLower ? pi : size - pi; // remaining size\n      if (r > 0)\n      {\n        // let's directly call the low level product function because:\n        // 1 - it is faster to compile\n        // 2 - it is slighlty faster at runtime\n        Index startRow = IsLower ? pi : pi-actualPanelWidth;\n        Index startCol = IsLower ? 0 : pi;\n\n        general_matrix_vector_product<Index,LhsScalar,LhsMapper,RowMajor,Conjugate,RhsScalar,RhsMapper,false>::run(\n          actualPanelWidth, r,\n          LhsMapper(&lhs.coeffRef(startRow,startCol), lhsStride),\n          RhsMapper(rhs + startCol, 1),\n          rhs + startRow, 1,\n          RhsScalar(-1));\n      }\n\n      for(Index k=0; k<actualPanelWidth; ++k)\n      {\n        Index i = IsLower ? pi+k : pi-k-1;\n        Index s = IsLower ? pi   : i+1;\n        if (k>0)\n          rhs[i] -= (cjLhs.row(i).segment(s,k).transpose().cwiseProduct(Map<const Matrix<RhsScalar,Dynamic,1> >(rhs+s,k))).sum();\n\n        if(!(Mode & UnitDiag))\n          rhs[i] /= cjLhs(i,i);\n      }\n    }\n  }\n};\n\n// forward and backward substitution, column-major, rhs is a vector\ntemplate<typename LhsScalar, typename RhsScalar, typename Index, int Mode, bool Conjugate>\nstruct triangular_solve_vector<LhsScalar, RhsScalar, Index, OnTheLeft, Mode, Conjugate, ColMajor>\n{\n  enum {\n    IsLower = ((Mode&Lower)==Lower)\n  };\n  static void run(Index size, const LhsScalar* _lhs, Index lhsStride, RhsScalar* rhs)\n  {\n    typedef Map<const Matrix<LhsScalar,Dynamic,Dynamic,ColMajor>, 0, OuterStride<> > LhsMap;\n    const LhsMap lhs(_lhs,size,size,OuterStride<>(lhsStride));\n    typedef const_blas_data_mapper<LhsScalar,Index,ColMajor> LhsMapper;\n    typedef const_blas_data_mapper<RhsScalar,Index,ColMajor> RhsMapper;\n    typename internal::conditional<Conjugate,\n                                   const CwiseUnaryOp<typename internal::scalar_conjugate_op<LhsScalar>,LhsMap>,\n                                   const LhsMap&\n                                  >::type cjLhs(lhs);\n    static const Index PanelWidth = EIGEN_TUNE_TRIANGULAR_PANEL_WIDTH;\n\n    for(Index pi=IsLower ? 0 : size;\n        IsLower ? pi<size : pi>0;\n        IsLower ? pi+=PanelWidth : pi-=PanelWidth)\n    {\n      Index actualPanelWidth = (std::min)(IsLower ? size - pi : pi, PanelWidth);\n      Index startBlock = IsLower ? pi : pi-actualPanelWidth;\n      Index endBlock = IsLower ? pi + actualPanelWidth : 0;\n\n      for(Index k=0; k<actualPanelWidth; ++k)\n      {\n        Index i = IsLower ? pi+k : pi-k-1;\n        if(!(Mode & UnitDiag))\n          rhs[i] /= cjLhs.coeff(i,i);\n\n        Index r = actualPanelWidth - k - 1; // remaining size\n        Index s = IsLower ? i+1 : i-r;\n        if (r>0)\n          Map<Matrix<RhsScalar,Dynamic,1> >(rhs+s,r) -= rhs[i] * cjLhs.col(i).segment(s,r);\n      }\n      Index r = IsLower ? size - endBlock : startBlock; // remaining size\n      if (r > 0)\n      {\n        // let's directly call the low level product function because:\n        // 1 - it is faster to compile\n        // 2 - it is slighlty faster at runtime\n        general_matrix_vector_product<Index,LhsScalar,LhsMapper,ColMajor,Conjugate,RhsScalar,RhsMapper,false>::run(\n            r, actualPanelWidth,\n            LhsMapper(&lhs.coeffRef(endBlock,startBlock), lhsStride),\n            RhsMapper(rhs+startBlock, 1),\n            rhs+endBlock, 1, RhsScalar(-1));\n      }\n    }\n  }\n};\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_TRIANGULAR_SOLVER_VECTOR_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/util/BlasUtil.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009-2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_BLASUTIL_H\n#define EIGEN_BLASUTIL_H\n\n// This file contains many lightweight helper classes used to\n// implement and control fast level 2 and level 3 BLAS-like routines.\n\nnamespace Eigen {\n\nnamespace internal {\n\n// forward declarations\ntemplate<typename LhsScalar, typename RhsScalar, typename Index, typename DataMapper, int mr, int nr, bool ConjugateLhs=false, bool ConjugateRhs=false>\nstruct gebp_kernel;\n\ntemplate<typename Scalar, typename Index, typename DataMapper, int nr, int StorageOrder, bool Conjugate = false, bool PanelMode=false>\nstruct gemm_pack_rhs;\n\ntemplate<typename Scalar, typename Index, typename DataMapper, int Pack1, int Pack2, int StorageOrder, bool Conjugate = false, bool PanelMode = false>\nstruct gemm_pack_lhs;\n\ntemplate<\n  typename Index,\n  typename LhsScalar, int LhsStorageOrder, bool ConjugateLhs,\n  typename RhsScalar, int RhsStorageOrder, bool ConjugateRhs,\n  int ResStorageOrder>\nstruct general_matrix_matrix_product;\n\ntemplate<typename Index,\n         typename LhsScalar, typename LhsMapper, int LhsStorageOrder, bool ConjugateLhs,\n         typename RhsScalar, typename RhsMapper, bool ConjugateRhs, int Version=Specialized>\nstruct general_matrix_vector_product;\n\n\ntemplate<bool Conjugate> struct conj_if;\n\ntemplate<> struct conj_if<true> {\n  template<typename T>\n  inline T operator()(const T& x) const { return numext::conj(x); }\n  template<typename T>\n  inline T pconj(const T& x) const { return internal::pconj(x); }\n};\n\ntemplate<> struct conj_if<false> {\n  template<typename T>\n  inline const T& operator()(const T& x) const { return x; }\n  template<typename T>\n  inline const T& pconj(const T& x) const { return x; }\n};\n\n// Generic implementation for custom complex types.\ntemplate<typename LhsScalar, typename RhsScalar, bool ConjLhs, bool ConjRhs>\nstruct conj_helper\n{\n  typedef typename ScalarBinaryOpTraits<LhsScalar,RhsScalar>::ReturnType Scalar;\n\n  EIGEN_STRONG_INLINE Scalar pmadd(const LhsScalar& x, const RhsScalar& y, const Scalar& c) const\n  { return padd(c, pmul(x,y)); }\n\n  EIGEN_STRONG_INLINE Scalar pmul(const LhsScalar& x, const RhsScalar& y) const\n  { return conj_if<ConjLhs>()(x) *  conj_if<ConjRhs>()(y); }\n};\n\ntemplate<typename Scalar> struct conj_helper<Scalar,Scalar,false,false>\n{\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE Scalar pmadd(const Scalar& x, const Scalar& y, const Scalar& c) const { return internal::pmadd(x,y,c); }\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE Scalar pmul(const Scalar& x, const Scalar& y) const { return internal::pmul(x,y); }\n};\n\ntemplate<typename RealScalar> struct conj_helper<std::complex<RealScalar>, std::complex<RealScalar>, false,true>\n{\n  typedef std::complex<RealScalar> Scalar;\n  EIGEN_STRONG_INLINE Scalar pmadd(const Scalar& x, const Scalar& y, const Scalar& c) const\n  { return c + pmul(x,y); }\n\n  EIGEN_STRONG_INLINE Scalar pmul(const Scalar& x, const Scalar& y) const\n  { return Scalar(numext::real(x)*numext::real(y) + numext::imag(x)*numext::imag(y), numext::imag(x)*numext::real(y) - numext::real(x)*numext::imag(y)); }\n};\n\ntemplate<typename RealScalar> struct conj_helper<std::complex<RealScalar>, std::complex<RealScalar>, true,false>\n{\n  typedef std::complex<RealScalar> Scalar;\n  EIGEN_STRONG_INLINE Scalar pmadd(const Scalar& x, const Scalar& y, const Scalar& c) const\n  { return c + pmul(x,y); }\n\n  EIGEN_STRONG_INLINE Scalar pmul(const Scalar& x, const Scalar& y) const\n  { return Scalar(numext::real(x)*numext::real(y) + numext::imag(x)*numext::imag(y), numext::real(x)*numext::imag(y) - numext::imag(x)*numext::real(y)); }\n};\n\ntemplate<typename RealScalar> struct conj_helper<std::complex<RealScalar>, std::complex<RealScalar>, true,true>\n{\n  typedef std::complex<RealScalar> Scalar;\n  EIGEN_STRONG_INLINE Scalar pmadd(const Scalar& x, const Scalar& y, const Scalar& c) const\n  { return c + pmul(x,y); }\n\n  EIGEN_STRONG_INLINE Scalar pmul(const Scalar& x, const Scalar& y) const\n  { return Scalar(numext::real(x)*numext::real(y) - numext::imag(x)*numext::imag(y), - numext::real(x)*numext::imag(y) - numext::imag(x)*numext::real(y)); }\n};\n\ntemplate<typename RealScalar,bool Conj> struct conj_helper<std::complex<RealScalar>, RealScalar, Conj,false>\n{\n  typedef std::complex<RealScalar> Scalar;\n  EIGEN_STRONG_INLINE Scalar pmadd(const Scalar& x, const RealScalar& y, const Scalar& c) const\n  { return padd(c, pmul(x,y)); }\n  EIGEN_STRONG_INLINE Scalar pmul(const Scalar& x, const RealScalar& y) const\n  { return conj_if<Conj>()(x)*y; }\n};\n\ntemplate<typename RealScalar,bool Conj> struct conj_helper<RealScalar, std::complex<RealScalar>, false,Conj>\n{\n  typedef std::complex<RealScalar> Scalar;\n  EIGEN_STRONG_INLINE Scalar pmadd(const RealScalar& x, const Scalar& y, const Scalar& c) const\n  { return padd(c, pmul(x,y)); }\n  EIGEN_STRONG_INLINE Scalar pmul(const RealScalar& x, const Scalar& y) const\n  { return x*conj_if<Conj>()(y); }\n};\n\ntemplate<typename From,typename To> struct get_factor {\n  EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE To run(const From& x) { return To(x); }\n};\n\ntemplate<typename Scalar> struct get_factor<Scalar,typename NumTraits<Scalar>::Real> {\n  EIGEN_DEVICE_FUNC\n  static EIGEN_STRONG_INLINE typename NumTraits<Scalar>::Real run(const Scalar& x) { return numext::real(x); }\n};\n\n\ntemplate<typename Scalar, typename Index>\nclass BlasVectorMapper {\n  public:\n  EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE BlasVectorMapper(Scalar *data) : m_data(data) {}\n\n  EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE Scalar operator()(Index i) const {\n    return m_data[i];\n  }\n  template <typename Packet, int AlignmentType>\n  EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE Packet load(Index i) const {\n    return ploadt<Packet, AlignmentType>(m_data + i);\n  }\n\n  template <typename Packet>\n  EIGEN_DEVICE_FUNC bool aligned(Index i) const {\n    return (UIntPtr(m_data+i)%sizeof(Packet))==0;\n  }\n\n  protected:\n  Scalar* m_data;\n};\n\ntemplate<typename Scalar, typename Index, int AlignmentType>\nclass BlasLinearMapper {\n  public:\n  typedef typename packet_traits<Scalar>::type Packet;\n  typedef typename packet_traits<Scalar>::half HalfPacket;\n\n  EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE BlasLinearMapper(Scalar *data) : m_data(data) {}\n\n  EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE void prefetch(int i) const {\n    internal::prefetch(&operator()(i));\n  }\n\n  EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE Scalar& operator()(Index i) const {\n    return m_data[i];\n  }\n\n  EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE Packet loadPacket(Index i) const {\n    return ploadt<Packet, AlignmentType>(m_data + i);\n  }\n\n  EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE HalfPacket loadHalfPacket(Index i) const {\n    return ploadt<HalfPacket, AlignmentType>(m_data + i);\n  }\n\n  EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE void storePacket(Index i, const Packet &p) const {\n    pstoret<Scalar, Packet, AlignmentType>(m_data + i, p);\n  }\n\n  protected:\n  Scalar *m_data;\n};\n\n// Lightweight helper class to access matrix coefficients.\ntemplate<typename Scalar, typename Index, int StorageOrder, int AlignmentType = Unaligned>\nclass blas_data_mapper {\n  public:\n  typedef typename packet_traits<Scalar>::type Packet;\n  typedef typename packet_traits<Scalar>::half HalfPacket;\n\n  typedef BlasLinearMapper<Scalar, Index, AlignmentType> LinearMapper;\n  typedef BlasVectorMapper<Scalar, Index> VectorMapper;\n\n  EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE blas_data_mapper(Scalar* data, Index stride) : m_data(data), m_stride(stride) {}\n\n  EIGEN_DEVICE_FUNC  EIGEN_ALWAYS_INLINE blas_data_mapper<Scalar, Index, StorageOrder, AlignmentType>\n  getSubMapper(Index i, Index j) const {\n    return blas_data_mapper<Scalar, Index, StorageOrder, AlignmentType>(&operator()(i, j), m_stride);\n  }\n\n  EIGEN_DEVICE_FUNC  EIGEN_ALWAYS_INLINE LinearMapper getLinearMapper(Index i, Index j) const {\n    return LinearMapper(&operator()(i, j));\n  }\n\n  EIGEN_DEVICE_FUNC  EIGEN_ALWAYS_INLINE VectorMapper getVectorMapper(Index i, Index j) const {\n    return VectorMapper(&operator()(i, j));\n  }\n\n\n  EIGEN_DEVICE_FUNC\n  EIGEN_ALWAYS_INLINE Scalar& operator()(Index i, Index j) const {\n    return m_data[StorageOrder==RowMajor ? j + i*m_stride : i + j*m_stride];\n  }\n\n  EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE Packet loadPacket(Index i, Index j) const {\n    return ploadt<Packet, AlignmentType>(&operator()(i, j));\n  }\n\n  EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE HalfPacket loadHalfPacket(Index i, Index j) const {\n    return ploadt<HalfPacket, AlignmentType>(&operator()(i, j));\n  }\n\n  template<typename SubPacket>\n  EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE void scatterPacket(Index i, Index j, const SubPacket &p) const {\n    pscatter<Scalar, SubPacket>(&operator()(i, j), p, m_stride);\n  }\n\n  template<typename SubPacket>\n  EIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE SubPacket gatherPacket(Index i, Index j) const {\n    return pgather<Scalar, SubPacket>(&operator()(i, j), m_stride);\n  }\n\n  EIGEN_DEVICE_FUNC const Index stride() const { return m_stride; }\n  EIGEN_DEVICE_FUNC const Scalar* data() const { return m_data; }\n\n  EIGEN_DEVICE_FUNC Index firstAligned(Index size) const {\n    if (UIntPtr(m_data)%sizeof(Scalar)) {\n      return -1;\n    }\n    return internal::first_default_aligned(m_data, size);\n  }\n\n  protected:\n  Scalar* EIGEN_RESTRICT m_data;\n  const Index m_stride;\n};\n\n// lightweight helper class to access matrix coefficients (const version)\ntemplate<typename Scalar, typename Index, int StorageOrder>\nclass const_blas_data_mapper : public blas_data_mapper<const Scalar, Index, StorageOrder> {\n  public:\n  EIGEN_ALWAYS_INLINE const_blas_data_mapper(const Scalar *data, Index stride) : blas_data_mapper<const Scalar, Index, StorageOrder>(data, stride) {}\n\n  EIGEN_ALWAYS_INLINE const_blas_data_mapper<Scalar, Index, StorageOrder> getSubMapper(Index i, Index j) const {\n    return const_blas_data_mapper<Scalar, Index, StorageOrder>(&(this->operator()(i, j)), this->m_stride);\n  }\n};\n\n\n/* Helper class to analyze the factors of a Product expression.\n * In particular it allows to pop out operator-, scalar multiples,\n * and conjugate */\ntemplate<typename XprType> struct blas_traits\n{\n  typedef typename traits<XprType>::Scalar Scalar;\n  typedef const XprType& ExtractType;\n  typedef XprType _ExtractType;\n  enum {\n    IsComplex = NumTraits<Scalar>::IsComplex,\n    IsTransposed = false,\n    NeedToConjugate = false,\n    HasUsableDirectAccess = (    (int(XprType::Flags)&DirectAccessBit)\n                              && (   bool(XprType::IsVectorAtCompileTime)\n                                  || int(inner_stride_at_compile_time<XprType>::ret) == 1)\n                             ) ?  1 : 0\n  };\n  typedef typename conditional<bool(HasUsableDirectAccess),\n    ExtractType,\n    typename _ExtractType::PlainObject\n    >::type DirectLinearAccessType;\n  static inline ExtractType extract(const XprType& x) { return x; }\n  static inline const Scalar extractScalarFactor(const XprType&) { return Scalar(1); }\n};\n\n// pop conjugate\ntemplate<typename Scalar, typename NestedXpr>\nstruct blas_traits<CwiseUnaryOp<scalar_conjugate_op<Scalar>, NestedXpr> >\n : blas_traits<NestedXpr>\n{\n  typedef blas_traits<NestedXpr> Base;\n  typedef CwiseUnaryOp<scalar_conjugate_op<Scalar>, NestedXpr> XprType;\n  typedef typename Base::ExtractType ExtractType;\n\n  enum {\n    IsComplex = NumTraits<Scalar>::IsComplex,\n    NeedToConjugate = Base::NeedToConjugate ? 0 : IsComplex\n  };\n  static inline ExtractType extract(const XprType& x) { return Base::extract(x.nestedExpression()); }\n  static inline Scalar extractScalarFactor(const XprType& x) { return conj(Base::extractScalarFactor(x.nestedExpression())); }\n};\n\n// pop scalar multiple\ntemplate<typename Scalar, typename NestedXpr, typename Plain>\nstruct blas_traits<CwiseBinaryOp<scalar_product_op<Scalar>, const CwiseNullaryOp<scalar_constant_op<Scalar>,Plain>, NestedXpr> >\n : blas_traits<NestedXpr>\n{\n  typedef blas_traits<NestedXpr> Base;\n  typedef CwiseBinaryOp<scalar_product_op<Scalar>, const CwiseNullaryOp<scalar_constant_op<Scalar>,Plain>, NestedXpr> XprType;\n  typedef typename Base::ExtractType ExtractType;\n  static inline ExtractType extract(const XprType& x) { return Base::extract(x.rhs()); }\n  static inline Scalar extractScalarFactor(const XprType& x)\n  { return x.lhs().functor().m_other * Base::extractScalarFactor(x.rhs()); }\n};\ntemplate<typename Scalar, typename NestedXpr, typename Plain>\nstruct blas_traits<CwiseBinaryOp<scalar_product_op<Scalar>, NestedXpr, const CwiseNullaryOp<scalar_constant_op<Scalar>,Plain> > >\n : blas_traits<NestedXpr>\n{\n  typedef blas_traits<NestedXpr> Base;\n  typedef CwiseBinaryOp<scalar_product_op<Scalar>, NestedXpr, const CwiseNullaryOp<scalar_constant_op<Scalar>,Plain> > XprType;\n  typedef typename Base::ExtractType ExtractType;\n  static inline ExtractType extract(const XprType& x) { return Base::extract(x.lhs()); }\n  static inline Scalar extractScalarFactor(const XprType& x)\n  { return Base::extractScalarFactor(x.lhs()) * x.rhs().functor().m_other; }\n};\ntemplate<typename Scalar, typename Plain1, typename Plain2>\nstruct blas_traits<CwiseBinaryOp<scalar_product_op<Scalar>, const CwiseNullaryOp<scalar_constant_op<Scalar>,Plain1>,\n                                                            const CwiseNullaryOp<scalar_constant_op<Scalar>,Plain2> > >\n : blas_traits<CwiseNullaryOp<scalar_constant_op<Scalar>,Plain1> >\n{};\n\n// pop opposite\ntemplate<typename Scalar, typename NestedXpr>\nstruct blas_traits<CwiseUnaryOp<scalar_opposite_op<Scalar>, NestedXpr> >\n : blas_traits<NestedXpr>\n{\n  typedef blas_traits<NestedXpr> Base;\n  typedef CwiseUnaryOp<scalar_opposite_op<Scalar>, NestedXpr> XprType;\n  typedef typename Base::ExtractType ExtractType;\n  static inline ExtractType extract(const XprType& x) { return Base::extract(x.nestedExpression()); }\n  static inline Scalar extractScalarFactor(const XprType& x)\n  { return - Base::extractScalarFactor(x.nestedExpression()); }\n};\n\n// pop/push transpose\ntemplate<typename NestedXpr>\nstruct blas_traits<Transpose<NestedXpr> >\n : blas_traits<NestedXpr>\n{\n  typedef typename NestedXpr::Scalar Scalar;\n  typedef blas_traits<NestedXpr> Base;\n  typedef Transpose<NestedXpr> XprType;\n  typedef Transpose<const typename Base::_ExtractType>  ExtractType; // const to get rid of a compile error; anyway blas traits are only used on the RHS\n  typedef Transpose<const typename Base::_ExtractType> _ExtractType;\n  typedef typename conditional<bool(Base::HasUsableDirectAccess),\n    ExtractType,\n    typename ExtractType::PlainObject\n    >::type DirectLinearAccessType;\n  enum {\n    IsTransposed = Base::IsTransposed ? 0 : 1\n  };\n  static inline ExtractType extract(const XprType& x) { return ExtractType(Base::extract(x.nestedExpression())); }\n  static inline Scalar extractScalarFactor(const XprType& x) { return Base::extractScalarFactor(x.nestedExpression()); }\n};\n\ntemplate<typename T>\nstruct blas_traits<const T>\n     : blas_traits<T>\n{};\n\ntemplate<typename T, bool HasUsableDirectAccess=blas_traits<T>::HasUsableDirectAccess>\nstruct extract_data_selector {\n  static const typename T::Scalar* run(const T& m)\n  {\n    return blas_traits<T>::extract(m).data();\n  }\n};\n\ntemplate<typename T>\nstruct extract_data_selector<T,false> {\n  static typename T::Scalar* run(const T&) { return 0; }\n};\n\ntemplate<typename T> const typename T::Scalar* extract_data(const T& m)\n{\n  return extract_data_selector<T>::run(m);\n}\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_BLASUTIL_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/util/Constants.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2015 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2007-2009 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_CONSTANTS_H\n#define EIGEN_CONSTANTS_H\n\nnamespace Eigen {\n\n/** This value means that a positive quantity (e.g., a size) is not known at compile-time, and that instead the value is\n  * stored in some runtime variable.\n  *\n  * Changing the value of Dynamic breaks the ABI, as Dynamic is often used as a template parameter for Matrix.\n  */\nconst int Dynamic = -1;\n\n/** This value means that a signed quantity (e.g., a signed index) is not known at compile-time, and that instead its value\n  * has to be specified at runtime.\n  */\nconst int DynamicIndex = 0xffffff;\n\n/** This value means +Infinity; it is currently used only as the p parameter to MatrixBase::lpNorm<int>().\n  * The value Infinity there means the L-infinity norm.\n  */\nconst int Infinity = -1;\n\n/** This value means that the cost to evaluate an expression coefficient is either very expensive or\n  * cannot be known at compile time.\n  *\n  * This value has to be positive to (1) simplify cost computation, and (2) allow to distinguish between a very expensive and very very expensive expressions.\n  * It thus must also be large enough to make sure unrolling won't happen and that sub expressions will be evaluated, but not too large to avoid overflow.\n  */\nconst int HugeCost = 10000;\n\n/** \\defgroup flags Flags\n  * \\ingroup Core_Module\n  *\n  * These are the possible bits which can be OR'ed to constitute the flags of a matrix or\n  * expression.\n  *\n  * It is important to note that these flags are a purely compile-time notion. They are a compile-time property of\n  * an expression type, implemented as enum's. They are not stored in memory at runtime, and they do not incur any\n  * runtime overhead.\n  *\n  * \\sa MatrixBase::Flags\n  */\n\n/** \\ingroup flags\n  *\n  * for a matrix, this means that the storage order is row-major.\n  * If this bit is not set, the storage order is column-major.\n  * For an expression, this determines the storage order of\n  * the matrix created by evaluation of that expression.\n  * \\sa \\blank  \\ref TopicStorageOrders */\nconst unsigned int RowMajorBit = 0x1;\n\n/** \\ingroup flags\n  * means the expression should be evaluated by the calling expression */\nconst unsigned int EvalBeforeNestingBit = 0x2;\n\n/** \\ingroup flags\n  * \\deprecated\n  * means the expression should be evaluated before any assignment */\nEIGEN_DEPRECATED\nconst unsigned int EvalBeforeAssigningBit = 0x4; // FIXME deprecated\n\n/** \\ingroup flags\n  *\n  * Short version: means the expression might be vectorized\n  *\n  * Long version: means that the coefficients can be handled by packets\n  * and start at a memory location whose alignment meets the requirements\n  * of the present CPU architecture for optimized packet access. In the fixed-size\n  * case, there is the additional condition that it be possible to access all the\n  * coefficients by packets (this implies the requirement that the size be a multiple of 16 bytes,\n  * and that any nontrivial strides don't break the alignment). In the dynamic-size case,\n  * there is no such condition on the total size and strides, so it might not be possible to access\n  * all coeffs by packets.\n  *\n  * \\note This bit can be set regardless of whether vectorization is actually enabled.\n  *       To check for actual vectorizability, see \\a ActualPacketAccessBit.\n  */\nconst unsigned int PacketAccessBit = 0x8;\n\n#ifdef EIGEN_VECTORIZE\n/** \\ingroup flags\n  *\n  * If vectorization is enabled (EIGEN_VECTORIZE is defined) this constant\n  * is set to the value \\a PacketAccessBit.\n  *\n  * If vectorization is not enabled (EIGEN_VECTORIZE is not defined) this constant\n  * is set to the value 0.\n  */\nconst unsigned int ActualPacketAccessBit = PacketAccessBit;\n#else\nconst unsigned int ActualPacketAccessBit = 0x0;\n#endif\n\n/** \\ingroup flags\n  *\n  * Short version: means the expression can be seen as 1D vector.\n  *\n  * Long version: means that one can access the coefficients\n  * of this expression by coeff(int), and coeffRef(int) in the case of a lvalue expression. These\n  * index-based access methods are guaranteed\n  * to not have to do any runtime computation of a (row, col)-pair from the index, so that it\n  * is guaranteed that whenever it is available, index-based access is at least as fast as\n  * (row,col)-based access. Expressions for which that isn't possible don't have the LinearAccessBit.\n  *\n  * If both PacketAccessBit and LinearAccessBit are set, then the\n  * packets of this expression can be accessed by packet(int), and writePacket(int) in the case of a\n  * lvalue expression.\n  *\n  * Typically, all vector expressions have the LinearAccessBit, but there is one exception:\n  * Product expressions don't have it, because it would be troublesome for vectorization, even when the\n  * Product is a vector expression. Thus, vector Product expressions allow index-based coefficient access but\n  * not index-based packet access, so they don't have the LinearAccessBit.\n  */\nconst unsigned int LinearAccessBit = 0x10;\n\n/** \\ingroup flags\n  *\n  * Means the expression has a coeffRef() method, i.e. is writable as its individual coefficients are directly addressable.\n  * This rules out read-only expressions.\n  *\n  * Note that DirectAccessBit and LvalueBit are mutually orthogonal, as there are examples of expression having one but note\n  * the other:\n  *   \\li writable expressions that don't have a very simple memory layout as a strided array, have LvalueBit but not DirectAccessBit\n  *   \\li Map-to-const expressions, for example Map<const Matrix>, have DirectAccessBit but not LvalueBit\n  *\n  * Expressions having LvalueBit also have their coeff() method returning a const reference instead of returning a new value.\n  */\nconst unsigned int LvalueBit = 0x20;\n\n/** \\ingroup flags\n  *\n  * Means that the underlying array of coefficients can be directly accessed as a plain strided array. The memory layout\n  * of the array of coefficients must be exactly the natural one suggested by rows(), cols(),\n  * outerStride(), innerStride(), and the RowMajorBit. This rules out expressions such as Diagonal, whose coefficients,\n  * though referencable, do not have such a regular memory layout.\n  *\n  * See the comment on LvalueBit for an explanation of how LvalueBit and DirectAccessBit are mutually orthogonal.\n  */\nconst unsigned int DirectAccessBit = 0x40;\n\n/** \\deprecated \\ingroup flags\n  *\n  * means the first coefficient packet is guaranteed to be aligned.\n  * An expression cannot has the AlignedBit without the PacketAccessBit flag.\n  * In other words, this means we are allow to perform an aligned packet access to the first element regardless\n  * of the expression kind:\n  * \\code\n  * expression.packet<Aligned>(0);\n  * \\endcode\n  */\nEIGEN_DEPRECATED const unsigned int AlignedBit = 0x80;\n\nconst unsigned int NestByRefBit = 0x100;\n\n/** \\ingroup flags\n  *\n  * for an expression, this means that the storage order\n  * can be either row-major or column-major.\n  * The precise choice will be decided at evaluation time or when\n  * combined with other expressions.\n  * \\sa \\blank  \\ref RowMajorBit, \\ref TopicStorageOrders */\nconst unsigned int NoPreferredStorageOrderBit = 0x200;\n\n/** \\ingroup flags\n  *\n  * Means that the underlying coefficients can be accessed through pointers to the sparse (un)compressed storage format,\n  * that is, the expression provides:\n  * \\code\n    inline const Scalar* valuePtr() const;\n    inline const Index* innerIndexPtr() const;\n    inline const Index* outerIndexPtr() const;\n    inline const Index* innerNonZeroPtr() const;\n    \\endcode\n  */\nconst unsigned int CompressedAccessBit = 0x400;\n\n\n// list of flags that are inherited by default\nconst unsigned int HereditaryBits = RowMajorBit\n                                  | EvalBeforeNestingBit;\n\n/** \\defgroup enums Enumerations\n  * \\ingroup Core_Module\n  *\n  * Various enumerations used in %Eigen. Many of these are used as template parameters.\n  */\n\n/** \\ingroup enums\n  * Enum containing possible values for the \\c Mode or \\c UpLo parameter of\n  * MatrixBase::selfadjointView() and MatrixBase::triangularView(), and selfadjoint solvers. */\nenum UpLoType {\n  /** View matrix as a lower triangular matrix. */\n  Lower=0x1,                      \n  /** View matrix as an upper triangular matrix. */\n  Upper=0x2,                      \n  /** %Matrix has ones on the diagonal; to be used in combination with #Lower or #Upper. */\n  UnitDiag=0x4, \n  /** %Matrix has zeros on the diagonal; to be used in combination with #Lower or #Upper. */\n  ZeroDiag=0x8,\n  /** View matrix as a lower triangular matrix with ones on the diagonal. */\n  UnitLower=UnitDiag|Lower, \n  /** View matrix as an upper triangular matrix with ones on the diagonal. */\n  UnitUpper=UnitDiag|Upper,\n  /** View matrix as a lower triangular matrix with zeros on the diagonal. */\n  StrictlyLower=ZeroDiag|Lower, \n  /** View matrix as an upper triangular matrix with zeros on the diagonal. */\n  StrictlyUpper=ZeroDiag|Upper,\n  /** Used in BandMatrix and SelfAdjointView to indicate that the matrix is self-adjoint. */\n  SelfAdjoint=0x10,\n  /** Used to support symmetric, non-selfadjoint, complex matrices. */\n  Symmetric=0x20\n};\n\n/** \\ingroup enums\n  * Enum for indicating whether a buffer is aligned or not. */\nenum AlignmentType {\n  Unaligned=0,        /**< Data pointer has no specific alignment. */\n  Aligned8=8,         /**< Data pointer is aligned on a 8 bytes boundary. */\n  Aligned16=16,       /**< Data pointer is aligned on a 16 bytes boundary. */\n  Aligned32=32,       /**< Data pointer is aligned on a 32 bytes boundary. */\n  Aligned64=64,       /**< Data pointer is aligned on a 64 bytes boundary. */\n  Aligned128=128,     /**< Data pointer is aligned on a 128 bytes boundary. */\n  AlignedMask=255,\n  Aligned=16,         /**< \\deprecated Synonym for Aligned16. */\n#if EIGEN_MAX_ALIGN_BYTES==128\n  AlignedMax = Aligned128\n#elif EIGEN_MAX_ALIGN_BYTES==64\n  AlignedMax = Aligned64\n#elif EIGEN_MAX_ALIGN_BYTES==32\n  AlignedMax = Aligned32\n#elif EIGEN_MAX_ALIGN_BYTES==16\n  AlignedMax = Aligned16\n#elif EIGEN_MAX_ALIGN_BYTES==8\n  AlignedMax = Aligned8\n#elif EIGEN_MAX_ALIGN_BYTES==0\n  AlignedMax = Unaligned\n#else\n#error Invalid value for EIGEN_MAX_ALIGN_BYTES\n#endif\n};\n\n/** \\ingroup enums\n * Enum used by DenseBase::corner() in Eigen2 compatibility mode. */\n// FIXME after the corner() API change, this was not needed anymore, except by AlignedBox\n// TODO: find out what to do with that. Adapt the AlignedBox API ?\nenum CornerType { TopLeft, TopRight, BottomLeft, BottomRight };\n\n/** \\ingroup enums\n  * Enum containing possible values for the \\p Direction parameter of\n  * Reverse, PartialReduxExpr and VectorwiseOp. */\nenum DirectionType { \n  /** For Reverse, all columns are reversed; \n    * for PartialReduxExpr and VectorwiseOp, act on columns. */\n  Vertical, \n  /** For Reverse, all rows are reversed; \n    * for PartialReduxExpr and VectorwiseOp, act on rows. */\n  Horizontal, \n  /** For Reverse, both rows and columns are reversed; \n    * not used for PartialReduxExpr and VectorwiseOp. */\n  BothDirections \n};\n\n/** \\internal \\ingroup enums\n  * Enum to specify how to traverse the entries of a matrix. */\nenum TraversalType {\n  /** \\internal Default traversal, no vectorization, no index-based access */\n  DefaultTraversal,\n  /** \\internal No vectorization, use index-based access to have only one for loop instead of 2 nested loops */\n  LinearTraversal,\n  /** \\internal Equivalent to a slice vectorization for fixed-size matrices having good alignment\n    * and good size */\n  InnerVectorizedTraversal,\n  /** \\internal Vectorization path using a single loop plus scalar loops for the\n    * unaligned boundaries */\n  LinearVectorizedTraversal,\n  /** \\internal Generic vectorization path using one vectorized loop per row/column with some\n    * scalar loops to handle the unaligned boundaries */\n  SliceVectorizedTraversal,\n  /** \\internal Special case to properly handle incompatible scalar types or other defecting cases*/\n  InvalidTraversal,\n  /** \\internal Evaluate all entries at once */\n  AllAtOnceTraversal\n};\n\n/** \\internal \\ingroup enums\n  * Enum to specify whether to unroll loops when traversing over the entries of a matrix. */\nenum UnrollingType {\n  /** \\internal Do not unroll loops. */\n  NoUnrolling,\n  /** \\internal Unroll only the inner loop, but not the outer loop. */\n  InnerUnrolling,\n  /** \\internal Unroll both the inner and the outer loop. If there is only one loop, \n    * because linear traversal is used, then unroll that loop. */\n  CompleteUnrolling\n};\n\n/** \\internal \\ingroup enums\n  * Enum to specify whether to use the default (built-in) implementation or the specialization. */\nenum SpecializedType {\n  Specialized,\n  BuiltIn\n};\n\n/** \\ingroup enums\n  * Enum containing possible values for the \\p _Options template parameter of\n  * Matrix, Array and BandMatrix. */\nenum StorageOptions {\n  /** Storage order is column major (see \\ref TopicStorageOrders). */\n  ColMajor = 0,\n  /** Storage order is row major (see \\ref TopicStorageOrders). */\n  RowMajor = 0x1,  // it is only a coincidence that this is equal to RowMajorBit -- don't rely on that\n  /** Align the matrix itself if it is vectorizable fixed-size */\n  AutoAlign = 0,\n  /** Don't require alignment for the matrix itself (the array of coefficients, if dynamically allocated, may still be requested to be aligned) */ // FIXME --- clarify the situation\n  DontAlign = 0x2\n};\n\n/** \\ingroup enums\n  * Enum for specifying whether to apply or solve on the left or right. */\nenum SideType {\n  /** Apply transformation on the left. */\n  OnTheLeft = 1,  \n  /** Apply transformation on the right. */\n  OnTheRight = 2  \n};\n\n/* the following used to be written as:\n *\n *   struct NoChange_t {};\n *   namespace {\n *     EIGEN_UNUSED NoChange_t NoChange;\n *   }\n *\n * on the ground that it feels dangerous to disambiguate overloaded functions on enum/integer types.  \n * However, this leads to \"variable declared but never referenced\" warnings on Intel Composer XE,\n * and we do not know how to get rid of them (bug 450).\n */\n\nenum NoChange_t   { NoChange };\nenum Sequential_t { Sequential };\nenum Default_t    { Default };\n\n/** \\internal \\ingroup enums\n  * Used in AmbiVector. */\nenum AmbiVectorMode {\n  IsDense         = 0,\n  IsSparse\n};\n\n/** \\ingroup enums\n  * Used as template parameter in DenseCoeffBase and MapBase to indicate \n  * which accessors should be provided. */\nenum AccessorLevels {\n  /** Read-only access via a member function. */\n  ReadOnlyAccessors, \n  /** Read/write access via member functions. */\n  WriteAccessors, \n  /** Direct read-only access to the coefficients. */\n  DirectAccessors, \n  /** Direct read/write access to the coefficients. */\n  DirectWriteAccessors\n};\n\n/** \\ingroup enums\n  * Enum with options to give to various decompositions. */\nenum DecompositionOptions {\n  /** \\internal Not used (meant for LDLT?). */\n  Pivoting            = 0x01, \n  /** \\internal Not used (meant for LDLT?). */\n  NoPivoting          = 0x02, \n  /** Used in JacobiSVD to indicate that the square matrix U is to be computed. */\n  ComputeFullU        = 0x04,\n  /** Used in JacobiSVD to indicate that the thin matrix U is to be computed. */\n  ComputeThinU        = 0x08,\n  /** Used in JacobiSVD to indicate that the square matrix V is to be computed. */\n  ComputeFullV        = 0x10,\n  /** Used in JacobiSVD to indicate that the thin matrix V is to be computed. */\n  ComputeThinV        = 0x20,\n  /** Used in SelfAdjointEigenSolver and GeneralizedSelfAdjointEigenSolver to specify\n    * that only the eigenvalues are to be computed and not the eigenvectors. */\n  EigenvaluesOnly     = 0x40,\n  /** Used in SelfAdjointEigenSolver and GeneralizedSelfAdjointEigenSolver to specify\n    * that both the eigenvalues and the eigenvectors are to be computed. */\n  ComputeEigenvectors = 0x80,\n  /** \\internal */\n  EigVecMask = EigenvaluesOnly | ComputeEigenvectors,\n  /** Used in GeneralizedSelfAdjointEigenSolver to indicate that it should\n    * solve the generalized eigenproblem \\f$ Ax = \\lambda B x \\f$. */\n  Ax_lBx              = 0x100,\n  /** Used in GeneralizedSelfAdjointEigenSolver to indicate that it should\n    * solve the generalized eigenproblem \\f$ ABx = \\lambda x \\f$. */\n  ABx_lx              = 0x200,\n  /** Used in GeneralizedSelfAdjointEigenSolver to indicate that it should\n    * solve the generalized eigenproblem \\f$ BAx = \\lambda x \\f$. */\n  BAx_lx              = 0x400,\n  /** \\internal */\n  GenEigMask = Ax_lBx | ABx_lx | BAx_lx\n};\n\n/** \\ingroup enums\n  * Possible values for the \\p QRPreconditioner template parameter of JacobiSVD. */\nenum QRPreconditioners {\n  /** Do not specify what is to be done if the SVD of a non-square matrix is asked for. */\n  NoQRPreconditioner,\n  /** Use a QR decomposition without pivoting as the first step. */\n  HouseholderQRPreconditioner,\n  /** Use a QR decomposition with column pivoting as the first step. */\n  ColPivHouseholderQRPreconditioner,\n  /** Use a QR decomposition with full pivoting as the first step. */\n  FullPivHouseholderQRPreconditioner\n};\n\n#ifdef Success\n#error The preprocessor symbol 'Success' is defined, possibly by the X11 header file X.h\n#endif\n\n/** \\ingroup enums\n  * Enum for reporting the status of a computation. */\nenum ComputationInfo {\n  /** Computation was successful. */\n  Success = 0,        \n  /** The provided data did not satisfy the prerequisites. */\n  NumericalIssue = 1, \n  /** Iterative procedure did not converge. */\n  NoConvergence = 2,\n  /** The inputs are invalid, or the algorithm has been improperly called.\n    * When assertions are enabled, such errors trigger an assert. */\n  InvalidInput = 3\n};\n\n/** \\ingroup enums\n  * Enum used to specify how a particular transformation is stored in a matrix.\n  * \\sa Transform, Hyperplane::transform(). */\nenum TransformTraits {\n  /** Transformation is an isometry. */\n  Isometry      = 0x1,\n  /** Transformation is an affine transformation stored as a (Dim+1)^2 matrix whose last row is \n    * assumed to be [0 ... 0 1]. */\n  Affine        = 0x2,\n  /** Transformation is an affine transformation stored as a (Dim) x (Dim+1) matrix. */\n  AffineCompact = 0x10 | Affine,\n  /** Transformation is a general projective transformation stored as a (Dim+1)^2 matrix. */\n  Projective    = 0x20\n};\n\n/** \\internal \\ingroup enums\n  * Enum used to choose between implementation depending on the computer architecture. */\nnamespace Architecture\n{\n  enum Type {\n    Generic = 0x0,\n    SSE = 0x1,\n    AltiVec = 0x2,\n    VSX = 0x3,\n    NEON = 0x4,\n#if defined EIGEN_VECTORIZE_SSE\n    Target = SSE\n#elif defined EIGEN_VECTORIZE_ALTIVEC\n    Target = AltiVec\n#elif defined EIGEN_VECTORIZE_VSX\n    Target = VSX\n#elif defined EIGEN_VECTORIZE_NEON\n    Target = NEON\n#else\n    Target = Generic\n#endif\n  };\n}\n\n/** \\internal \\ingroup enums\n  * Enum used as template parameter in Product and product evaluators. */\nenum ProductImplType\n{ DefaultProduct=0, LazyProduct, AliasFreeProduct, CoeffBasedProductMode, LazyCoeffBasedProductMode, OuterProduct, InnerProduct, GemvProduct, GemmProduct };\n\n/** \\internal \\ingroup enums\n  * Enum used in experimental parallel implementation. */\nenum Action {GetAction, SetAction};\n\n/** The type used to identify a dense storage. */\nstruct Dense {};\n\n/** The type used to identify a general sparse storage. */\nstruct Sparse {};\n\n/** The type used to identify a general solver (factored) storage. */\nstruct SolverStorage {};\n\n/** The type used to identify a permutation storage. */\nstruct PermutationStorage {};\n\n/** The type used to identify a permutation storage. */\nstruct TranspositionsStorage {};\n\n/** The type used to identify a matrix expression */\nstruct MatrixXpr {};\n\n/** The type used to identify an array expression */\nstruct ArrayXpr {};\n\n// An evaluator must define its shape. By default, it can be one of the following:\nstruct DenseShape             { static std::string debugName() { return \"DenseShape\"; } };\nstruct SolverShape            { static std::string debugName() { return \"SolverShape\"; } };\nstruct HomogeneousShape       { static std::string debugName() { return \"HomogeneousShape\"; } };\nstruct DiagonalShape          { static std::string debugName() { return \"DiagonalShape\"; } };\nstruct BandShape              { static std::string debugName() { return \"BandShape\"; } };\nstruct TriangularShape        { static std::string debugName() { return \"TriangularShape\"; } };\nstruct SelfAdjointShape       { static std::string debugName() { return \"SelfAdjointShape\"; } };\nstruct PermutationShape       { static std::string debugName() { return \"PermutationShape\"; } };\nstruct TranspositionsShape    { static std::string debugName() { return \"TranspositionsShape\"; } };\nstruct SparseShape            { static std::string debugName() { return \"SparseShape\"; } };\n\nnamespace internal {\n\n  // random access iterators based on coeff*() accessors.\nstruct IndexBased {};\n\n// evaluator based on iterators to access coefficients. \nstruct IteratorBased {};\n\n/** \\internal\n * Constants for comparison functors\n */\nenum ComparisonName {\n  cmp_EQ = 0,\n  cmp_LT = 1,\n  cmp_LE = 2,\n  cmp_UNORD = 3,\n  cmp_NEQ = 4,\n  cmp_GT = 5,\n  cmp_GE = 6\n};\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_CONSTANTS_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/util/DisableStupidWarnings.h",
    "content": "#ifndef EIGEN_WARNINGS_DISABLED\n#define EIGEN_WARNINGS_DISABLED\n\n#ifdef _MSC_VER\n  // 4100 - unreferenced formal parameter (occurred e.g. in aligned_allocator::destroy(pointer p))\n  // 4101 - unreferenced local variable\n  // 4127 - conditional expression is constant\n  // 4181 - qualifier applied to reference type ignored\n  // 4211 - nonstandard extension used : redefined extern to static\n  // 4244 - 'argument' : conversion from 'type1' to 'type2', possible loss of data\n  // 4273 - QtAlignedMalloc, inconsistent DLL linkage\n  // 4324 - structure was padded due to declspec(align())\n  // 4503 - decorated name length exceeded, name was truncated\n  // 4512 - assignment operator could not be generated\n  // 4522 - 'class' : multiple assignment operators specified\n  // 4700 - uninitialized local variable 'xyz' used\n  // 4714 - function marked as __forceinline not inlined\n  // 4717 - 'function' : recursive on all control paths, function will cause runtime stack overflow\n  // 4800 - 'type' : forcing value to bool 'true' or 'false' (performance warning)\n  #ifndef EIGEN_PERMANENTLY_DISABLE_STUPID_WARNINGS\n    #pragma warning( push )\n  #endif\n  #pragma warning( disable : 4100 4101 4127 4181 4211 4244 4273 4324 4503 4512 4522 4700 4714 4717 4800)\n\n#elif defined __INTEL_COMPILER\n  // 2196 - routine is both \"inline\" and \"noinline\" (\"noinline\" assumed)\n  //        ICC 12 generates this warning even without any inline keyword, when defining class methods 'inline' i.e. inside of class body\n  //        typedef that may be a reference type.\n  // 279  - controlling expression is constant\n  //        ICC 12 generates this warning on assert(constant_expression_depending_on_template_params) and frankly this is a legitimate use case.\n  // 1684 - conversion from pointer to same-sized integral type (potential portability problem)\n  // 2259 - non-pointer conversion from \"Eigen::Index={ptrdiff_t={long}}\" to \"int\" may lose significant bits\n  #ifndef EIGEN_PERMANENTLY_DISABLE_STUPID_WARNINGS\n    #pragma warning push\n  #endif\n  #pragma warning disable 2196 279 1684 2259\n\n#elif defined __clang__\n  // -Wconstant-logical-operand - warning: use of logical && with constant operand; switch to bitwise & or remove constant\n  //     this is really a stupid warning as it warns on compile-time expressions involving enums\n  #ifndef EIGEN_PERMANENTLY_DISABLE_STUPID_WARNINGS\n    #pragma clang diagnostic push\n  #endif\n  #pragma clang diagnostic ignored \"-Wconstant-logical-operand\"\n\n#elif defined __GNUC__ && __GNUC__>=6\n\n  #ifndef EIGEN_PERMANENTLY_DISABLE_STUPID_WARNINGS\n    #pragma GCC diagnostic push\n  #endif\n  #pragma GCC diagnostic ignored \"-Wignored-attributes\"\n\n#endif\n\n#if defined __NVCC__\n  // Disable the \"statement is unreachable\" message\n  #pragma diag_suppress code_is_unreachable\n  // Disable the \"dynamic initialization in unreachable code\" message\n  #pragma diag_suppress initialization_not_reachable\n  // Disable the \"invalid error number\" message that we get with older versions of nvcc\n  #pragma diag_suppress 1222\n  // Disable the \"calling a __host__ function from a __host__ __device__ function is not allowed\" messages (yes, there are many of them and they seem to change with every version of the compiler)\n  #pragma diag_suppress 2527\n  #pragma diag_suppress 2529\n  #pragma diag_suppress 2651\n  #pragma diag_suppress 2653\n  #pragma diag_suppress 2668\n  #pragma diag_suppress 2669\n  #pragma diag_suppress 2670\n  #pragma diag_suppress 2671\n  #pragma diag_suppress 2735\n  #pragma diag_suppress 2737\n#endif\n\n#endif // not EIGEN_WARNINGS_DISABLED\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/util/ForwardDeclarations.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2007-2010 Benoit Jacob <jacob.benoit.1@gmail.com>\n// Copyright (C) 2008-2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_FORWARDDECLARATIONS_H\n#define EIGEN_FORWARDDECLARATIONS_H\n\nnamespace Eigen {\nnamespace internal {\n\ntemplate<typename T> struct traits;\n\n// here we say once and for all that traits<const T> == traits<T>\n// When constness must affect traits, it has to be constness on template parameters on which T itself depends.\n// For example, traits<Map<const T> > != traits<Map<T> >, but\n//              traits<const Map<T> > == traits<Map<T> >\ntemplate<typename T> struct traits<const T> : traits<T> {};\n\ntemplate<typename Derived> struct has_direct_access\n{\n  enum { ret = (traits<Derived>::Flags & DirectAccessBit) ? 1 : 0 };\n};\n\ntemplate<typename Derived> struct accessors_level\n{\n  enum { has_direct_access = (traits<Derived>::Flags & DirectAccessBit) ? 1 : 0,\n         has_write_access = (traits<Derived>::Flags & LvalueBit) ? 1 : 0,\n         value = has_direct_access ? (has_write_access ? DirectWriteAccessors : DirectAccessors)\n                                   : (has_write_access ? WriteAccessors       : ReadOnlyAccessors)\n  };\n};\n\ntemplate<typename T> struct evaluator_traits;\n\ntemplate< typename T> struct evaluator;\n\n} // end namespace internal\n\ntemplate<typename T> struct NumTraits;\n\ntemplate<typename Derived> struct EigenBase;\ntemplate<typename Derived> class DenseBase;\ntemplate<typename Derived> class PlainObjectBase;\n\n\ntemplate<typename Derived,\n         int Level = internal::accessors_level<Derived>::value >\nclass DenseCoeffsBase;\n\ntemplate<typename _Scalar, int _Rows, int _Cols,\n         int _Options = AutoAlign |\n#if EIGEN_GNUC_AT(3,4)\n    // workaround a bug in at least gcc 3.4.6\n    // the innermost ?: ternary operator is misparsed. We write it slightly\n    // differently and this makes gcc 3.4.6 happy, but it's ugly.\n    // The error would only show up with EIGEN_DEFAULT_TO_ROW_MAJOR is defined\n    // (when EIGEN_DEFAULT_MATRIX_STORAGE_ORDER_OPTION is RowMajor)\n                          ( (_Rows==1 && _Cols!=1) ? Eigen::RowMajor\n                          : !(_Cols==1 && _Rows!=1) ?  EIGEN_DEFAULT_MATRIX_STORAGE_ORDER_OPTION\n                          : Eigen::ColMajor ),\n#else\n                          ( (_Rows==1 && _Cols!=1) ? Eigen::RowMajor\n                          : (_Cols==1 && _Rows!=1) ? Eigen::ColMajor\n                          : EIGEN_DEFAULT_MATRIX_STORAGE_ORDER_OPTION ),\n#endif\n         int _MaxRows = _Rows,\n         int _MaxCols = _Cols\n> class Matrix;\n\ntemplate<typename Derived> class MatrixBase;\ntemplate<typename Derived> class ArrayBase;\n\ntemplate<typename ExpressionType, unsigned int Added, unsigned int Removed> class Flagged;\ntemplate<typename ExpressionType, template <typename> class StorageBase > class NoAlias;\ntemplate<typename ExpressionType> class NestByValue;\ntemplate<typename ExpressionType> class ForceAlignedAccess;\ntemplate<typename ExpressionType> class SwapWrapper;\n\ntemplate<typename XprType, int BlockRows=Dynamic, int BlockCols=Dynamic, bool InnerPanel = false> class Block;\n\ntemplate<typename MatrixType, int Size=Dynamic> class VectorBlock;\ntemplate<typename MatrixType> class Transpose;\ntemplate<typename MatrixType> class Conjugate;\ntemplate<typename NullaryOp, typename MatrixType>         class CwiseNullaryOp;\ntemplate<typename UnaryOp,   typename MatrixType>         class CwiseUnaryOp;\ntemplate<typename ViewOp,    typename MatrixType>         class CwiseUnaryView;\ntemplate<typename BinaryOp,  typename Lhs, typename Rhs>  class CwiseBinaryOp;\ntemplate<typename TernaryOp, typename Arg1, typename Arg2, typename Arg3>  class CwiseTernaryOp;\ntemplate<typename Decomposition, typename Rhstype>        class Solve;\ntemplate<typename XprType>                                class Inverse;\n\ntemplate<typename Lhs, typename Rhs, int Option = DefaultProduct> class Product;\n\ntemplate<typename Derived> class DiagonalBase;\ntemplate<typename _DiagonalVectorType> class DiagonalWrapper;\ntemplate<typename _Scalar, int SizeAtCompileTime, int MaxSizeAtCompileTime=SizeAtCompileTime> class DiagonalMatrix;\ntemplate<typename MatrixType, typename DiagonalType, int ProductOrder> class DiagonalProduct;\ntemplate<typename MatrixType, int Index = 0> class Diagonal;\ntemplate<int SizeAtCompileTime, int MaxSizeAtCompileTime = SizeAtCompileTime, typename IndexType=int> class PermutationMatrix;\ntemplate<int SizeAtCompileTime, int MaxSizeAtCompileTime = SizeAtCompileTime, typename IndexType=int> class Transpositions;\ntemplate<typename Derived> class PermutationBase;\ntemplate<typename Derived> class TranspositionsBase;\ntemplate<typename _IndicesType> class PermutationWrapper;\ntemplate<typename _IndicesType> class TranspositionsWrapper;\n\ntemplate<typename Derived,\n         int Level = internal::accessors_level<Derived>::has_write_access ? WriteAccessors : ReadOnlyAccessors\n> class MapBase;\ntemplate<int InnerStrideAtCompileTime, int OuterStrideAtCompileTime> class Stride;\ntemplate<int Value = Dynamic> class InnerStride;\ntemplate<int Value = Dynamic> class OuterStride;\ntemplate<typename MatrixType, int MapOptions=Unaligned, typename StrideType = Stride<0,0> > class Map;\ntemplate<typename Derived> class RefBase;\ntemplate<typename PlainObjectType, int Options = 0,\n         typename StrideType = typename internal::conditional<PlainObjectType::IsVectorAtCompileTime,InnerStride<1>,OuterStride<> >::type > class Ref;\n\ntemplate<typename Derived> class TriangularBase;\ntemplate<typename MatrixType, unsigned int Mode> class TriangularView;\ntemplate<typename MatrixType, unsigned int Mode> class SelfAdjointView;\ntemplate<typename MatrixType> class SparseView;\ntemplate<typename ExpressionType> class WithFormat;\ntemplate<typename MatrixType> struct CommaInitializer;\ntemplate<typename Derived> class ReturnByValue;\ntemplate<typename ExpressionType> class ArrayWrapper;\ntemplate<typename ExpressionType> class MatrixWrapper;\ntemplate<typename Derived> class SolverBase;\ntemplate<typename XprType> class InnerIterator;\n\nnamespace internal {\ntemplate<typename DecompositionType> struct kernel_retval_base;\ntemplate<typename DecompositionType> struct kernel_retval;\ntemplate<typename DecompositionType> struct image_retval_base;\ntemplate<typename DecompositionType> struct image_retval;\n} // end namespace internal\n\nnamespace internal {\ntemplate<typename _Scalar, int Rows=Dynamic, int Cols=Dynamic, int Supers=Dynamic, int Subs=Dynamic, int Options=0> class BandMatrix;\n}\n\nnamespace internal {\ntemplate<typename Lhs, typename Rhs> struct product_type;\n\ntemplate<bool> struct EnableIf;\n\n/** \\internal\n  * \\class product_evaluator\n  * Products need their own evaluator with more template arguments allowing for\n  * easier partial template specializations.\n  */\ntemplate< typename T,\n          int ProductTag = internal::product_type<typename T::Lhs,typename T::Rhs>::ret,\n          typename LhsShape = typename evaluator_traits<typename T::Lhs>::Shape,\n          typename RhsShape = typename evaluator_traits<typename T::Rhs>::Shape,\n          typename LhsScalar = typename traits<typename T::Lhs>::Scalar,\n          typename RhsScalar = typename traits<typename T::Rhs>::Scalar\n        > struct product_evaluator;\n}\n\ntemplate<typename Lhs, typename Rhs,\n         int ProductType = internal::product_type<Lhs,Rhs>::value>\nstruct ProductReturnType;\n\n// this is a workaround for sun CC\ntemplate<typename Lhs, typename Rhs> struct LazyProductReturnType;\n\nnamespace internal {\n\n// Provides scalar/packet-wise product and product with accumulation\n// with optional conjugation of the arguments.\ntemplate<typename LhsScalar, typename RhsScalar, bool ConjLhs=false, bool ConjRhs=false> struct conj_helper;\n\ntemplate<typename LhsScalar,typename RhsScalar=LhsScalar> struct scalar_sum_op;\ntemplate<typename LhsScalar,typename RhsScalar=LhsScalar> struct scalar_difference_op;\ntemplate<typename LhsScalar,typename RhsScalar=LhsScalar> struct scalar_conj_product_op;\ntemplate<typename LhsScalar,typename RhsScalar=LhsScalar> struct scalar_min_op;\ntemplate<typename LhsScalar,typename RhsScalar=LhsScalar> struct scalar_max_op;\ntemplate<typename Scalar> struct scalar_opposite_op;\ntemplate<typename Scalar> struct scalar_conjugate_op;\ntemplate<typename Scalar> struct scalar_real_op;\ntemplate<typename Scalar> struct scalar_imag_op;\ntemplate<typename Scalar> struct scalar_abs_op;\ntemplate<typename Scalar> struct scalar_abs2_op;\ntemplate<typename Scalar> struct scalar_sqrt_op;\ntemplate<typename Scalar> struct scalar_rsqrt_op;\ntemplate<typename Scalar> struct scalar_exp_op;\ntemplate<typename Scalar> struct scalar_log_op;\ntemplate<typename Scalar> struct scalar_cos_op;\ntemplate<typename Scalar> struct scalar_sin_op;\ntemplate<typename Scalar> struct scalar_acos_op;\ntemplate<typename Scalar> struct scalar_asin_op;\ntemplate<typename Scalar> struct scalar_tan_op;\ntemplate<typename Scalar> struct scalar_inverse_op;\ntemplate<typename Scalar> struct scalar_square_op;\ntemplate<typename Scalar> struct scalar_cube_op;\ntemplate<typename Scalar, typename NewType> struct scalar_cast_op;\ntemplate<typename Scalar> struct scalar_random_op;\ntemplate<typename Scalar> struct scalar_constant_op;\ntemplate<typename Scalar> struct scalar_identity_op;\ntemplate<typename Scalar,bool iscpx> struct scalar_sign_op;\ntemplate<typename Scalar,typename ScalarExponent> struct scalar_pow_op;\ntemplate<typename LhsScalar,typename RhsScalar=LhsScalar> struct scalar_hypot_op;\ntemplate<typename LhsScalar,typename RhsScalar=LhsScalar> struct scalar_product_op;\ntemplate<typename LhsScalar,typename RhsScalar=LhsScalar> struct scalar_quotient_op;\n\n// SpecialFunctions module\ntemplate<typename Scalar> struct scalar_lgamma_op;\ntemplate<typename Scalar> struct scalar_digamma_op;\ntemplate<typename Scalar> struct scalar_erf_op;\ntemplate<typename Scalar> struct scalar_erfc_op;\ntemplate<typename Scalar> struct scalar_igamma_op;\ntemplate<typename Scalar> struct scalar_igammac_op;\ntemplate<typename Scalar> struct scalar_zeta_op;\ntemplate<typename Scalar> struct scalar_betainc_op;\n\n} // end namespace internal\n\nstruct IOFormat;\n\n// Array module\ntemplate<typename _Scalar, int _Rows, int _Cols,\n         int _Options = AutoAlign |\n#if EIGEN_GNUC_AT(3,4)\n    // workaround a bug in at least gcc 3.4.6\n    // the innermost ?: ternary operator is misparsed. We write it slightly\n    // differently and this makes gcc 3.4.6 happy, but it's ugly.\n    // The error would only show up with EIGEN_DEFAULT_TO_ROW_MAJOR is defined\n    // (when EIGEN_DEFAULT_MATRIX_STORAGE_ORDER_OPTION is RowMajor)\n                          ( (_Rows==1 && _Cols!=1) ? Eigen::RowMajor\n                          : !(_Cols==1 && _Rows!=1) ?  EIGEN_DEFAULT_MATRIX_STORAGE_ORDER_OPTION\n                          : Eigen::ColMajor ),\n#else\n                          ( (_Rows==1 && _Cols!=1) ? Eigen::RowMajor\n                          : (_Cols==1 && _Rows!=1) ? Eigen::ColMajor\n                          : EIGEN_DEFAULT_MATRIX_STORAGE_ORDER_OPTION ),\n#endif\n         int _MaxRows = _Rows, int _MaxCols = _Cols> class Array;\ntemplate<typename ConditionMatrixType, typename ThenMatrixType, typename ElseMatrixType> class Select;\ntemplate<typename MatrixType, typename BinaryOp, int Direction> class PartialReduxExpr;\ntemplate<typename ExpressionType, int Direction> class VectorwiseOp;\ntemplate<typename MatrixType,int RowFactor,int ColFactor> class Replicate;\ntemplate<typename MatrixType, int Direction = BothDirections> class Reverse;\n\ntemplate<typename MatrixType> class FullPivLU;\ntemplate<typename MatrixType> class PartialPivLU;\nnamespace internal {\ntemplate<typename MatrixType> struct inverse_impl;\n}\ntemplate<typename MatrixType> class HouseholderQR;\ntemplate<typename MatrixType> class ColPivHouseholderQR;\ntemplate<typename MatrixType> class FullPivHouseholderQR;\ntemplate<typename MatrixType> class CompleteOrthogonalDecomposition;\ntemplate<typename MatrixType, int QRPreconditioner = ColPivHouseholderQRPreconditioner> class JacobiSVD;\ntemplate<typename MatrixType> class BDCSVD;\ntemplate<typename MatrixType, int UpLo = Lower> class LLT;\ntemplate<typename MatrixType, int UpLo = Lower> class LDLT;\ntemplate<typename VectorsType, typename CoeffsType, int Side=OnTheLeft> class HouseholderSequence;\ntemplate<typename Scalar>     class JacobiRotation;\n\n// Geometry module:\ntemplate<typename Derived, int _Dim> class RotationBase;\ntemplate<typename Lhs, typename Rhs> class Cross;\ntemplate<typename Derived> class QuaternionBase;\ntemplate<typename Scalar> class Rotation2D;\ntemplate<typename Scalar> class AngleAxis;\ntemplate<typename Scalar,int Dim> class Translation;\ntemplate<typename Scalar,int Dim> class AlignedBox;\ntemplate<typename Scalar, int Options = AutoAlign> class Quaternion;\ntemplate<typename Scalar,int Dim,int Mode,int _Options=AutoAlign> class Transform;\ntemplate <typename _Scalar, int _AmbientDim, int Options=AutoAlign> class ParametrizedLine;\ntemplate <typename _Scalar, int _AmbientDim, int Options=AutoAlign> class Hyperplane;\ntemplate<typename Scalar> class UniformScaling;\ntemplate<typename MatrixType,int Direction> class Homogeneous;\n\n// Sparse module:\ntemplate<typename Derived> class SparseMatrixBase;\n\n// MatrixFunctions module\ntemplate<typename Derived> struct MatrixExponentialReturnValue;\ntemplate<typename Derived> class MatrixFunctionReturnValue;\ntemplate<typename Derived> class MatrixSquareRootReturnValue;\ntemplate<typename Derived> class MatrixLogarithmReturnValue;\ntemplate<typename Derived> class MatrixPowerReturnValue;\ntemplate<typename Derived> class MatrixComplexPowerReturnValue;\n\nnamespace internal {\ntemplate <typename Scalar>\nstruct stem_function\n{\n  typedef std::complex<typename NumTraits<Scalar>::Real> ComplexScalar;\n  typedef ComplexScalar type(ComplexScalar, int);\n};\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_FORWARDDECLARATIONS_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/util/MKL_support.h",
    "content": "/*\n Copyright (c) 2011, Intel Corporation. All rights reserved.\n\n Redistribution and use in source and binary forms, with or without modification,\n are permitted provided that the following conditions are met:\n\n * Redistributions of source code must retain the above copyright notice, this\n   list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright notice,\n   this list of conditions and the following disclaimer in the documentation\n   and/or other materials provided with the distribution.\n * Neither the name of Intel Corporation nor the names of its contributors may\n   be used to endorse or promote products derived from this software without\n   specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n ********************************************************************************\n *   Content : Eigen bindings to Intel(R) MKL\n *   Include file with common MKL declarations\n ********************************************************************************\n*/\n\n#ifndef EIGEN_MKL_SUPPORT_H\n#define EIGEN_MKL_SUPPORT_H\n\n#ifdef EIGEN_USE_MKL_ALL\n  #ifndef EIGEN_USE_BLAS\n    #define EIGEN_USE_BLAS\n  #endif\n  #ifndef EIGEN_USE_LAPACKE\n    #define EIGEN_USE_LAPACKE\n  #endif\n  #ifndef EIGEN_USE_MKL_VML\n    #define EIGEN_USE_MKL_VML\n  #endif\n#endif\n\n#ifdef EIGEN_USE_LAPACKE_STRICT\n  #define EIGEN_USE_LAPACKE\n#endif\n\n#if defined(EIGEN_USE_MKL_VML)\n  #define EIGEN_USE_MKL\n#endif\n\n#if defined EIGEN_USE_MKL\n#   include <mkl.h> \n/*Check IMKL version for compatibility: < 10.3 is not usable with Eigen*/\n#   ifndef INTEL_MKL_VERSION\n#       undef EIGEN_USE_MKL /* INTEL_MKL_VERSION is not even defined on older versions */\n#   elif INTEL_MKL_VERSION < 100305    /* the intel-mkl-103-release-notes say this was when the lapacke.h interface was added*/\n#       undef EIGEN_USE_MKL\n#   endif\n#   ifndef EIGEN_USE_MKL\n    /*If the MKL version is too old, undef everything*/\n#       undef   EIGEN_USE_MKL_ALL\n#       undef   EIGEN_USE_LAPACKE\n#       undef   EIGEN_USE_MKL_VML\n#       undef   EIGEN_USE_LAPACKE_STRICT\n#       undef   EIGEN_USE_LAPACKE\n#   endif\n#endif\n\n#if defined EIGEN_USE_MKL\n\n#define EIGEN_MKL_VML_THRESHOLD 128\n\n/* MKL_DOMAIN_BLAS, etc are defined only in 10.3 update 7 */\n/* MKL_BLAS, etc are not defined in 11.2 */\n#ifdef MKL_DOMAIN_ALL\n#define EIGEN_MKL_DOMAIN_ALL MKL_DOMAIN_ALL\n#else\n#define EIGEN_MKL_DOMAIN_ALL MKL_ALL\n#endif\n\n#ifdef MKL_DOMAIN_BLAS\n#define EIGEN_MKL_DOMAIN_BLAS MKL_DOMAIN_BLAS\n#else\n#define EIGEN_MKL_DOMAIN_BLAS MKL_BLAS\n#endif\n\n#ifdef MKL_DOMAIN_FFT\n#define EIGEN_MKL_DOMAIN_FFT MKL_DOMAIN_FFT\n#else\n#define EIGEN_MKL_DOMAIN_FFT MKL_FFT\n#endif\n\n#ifdef MKL_DOMAIN_VML\n#define EIGEN_MKL_DOMAIN_VML MKL_DOMAIN_VML\n#else\n#define EIGEN_MKL_DOMAIN_VML MKL_VML\n#endif\n\n#ifdef MKL_DOMAIN_PARDISO\n#define EIGEN_MKL_DOMAIN_PARDISO MKL_DOMAIN_PARDISO\n#else\n#define EIGEN_MKL_DOMAIN_PARDISO MKL_PARDISO\n#endif\n#endif\n\nnamespace Eigen {\n\ntypedef std::complex<double> dcomplex;\ntypedef std::complex<float>  scomplex;\n\n#if defined(EIGEN_USE_MKL)\ntypedef MKL_INT BlasIndex;\n#else\ntypedef int BlasIndex;\n#endif\n\n} // end namespace Eigen\n\n#if defined(EIGEN_USE_BLAS)\n#include \"../../misc/blas.h\"\n#endif\n\n#endif // EIGEN_MKL_SUPPORT_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/util/Macros.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2015 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2006-2008 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_MACROS_H\n#define EIGEN_MACROS_H\n\n#define EIGEN_WORLD_VERSION 3\n#define EIGEN_MAJOR_VERSION 3\n#define EIGEN_MINOR_VERSION 1\n\n#define EIGEN_VERSION_AT_LEAST(x,y,z) (EIGEN_WORLD_VERSION>x || (EIGEN_WORLD_VERSION>=x && \\\n                                      (EIGEN_MAJOR_VERSION>y || (EIGEN_MAJOR_VERSION>=y && \\\n                                                                 EIGEN_MINOR_VERSION>=z))))\n\n// Compiler identification, EIGEN_COMP_*\n\n/// \\internal EIGEN_COMP_GNUC set to 1 for all compilers compatible with GCC\n#ifdef __GNUC__\n  #define EIGEN_COMP_GNUC 1\n#else\n  #define EIGEN_COMP_GNUC 0\n#endif\n\n/// \\internal EIGEN_COMP_CLANG set to major+minor version (e.g., 307 for clang 3.7) if the compiler is clang\n#if defined(__clang__)\n  #define EIGEN_COMP_CLANG (__clang_major__*100+__clang_minor__)\n#else\n  #define EIGEN_COMP_CLANG 0\n#endif\n\n\n/// \\internal EIGEN_COMP_LLVM set to 1 if the compiler backend is llvm\n#if defined(__llvm__)\n  #define EIGEN_COMP_LLVM 1\n#else\n  #define EIGEN_COMP_LLVM 0\n#endif\n\n/// \\internal EIGEN_COMP_ICC set to __INTEL_COMPILER if the compiler is Intel compiler, 0 otherwise\n#if defined(__INTEL_COMPILER)\n  #define EIGEN_COMP_ICC __INTEL_COMPILER\n#else\n  #define EIGEN_COMP_ICC 0\n#endif\n\n/// \\internal EIGEN_COMP_MINGW set to 1 if the compiler is mingw\n#if defined(__MINGW32__)\n  #define EIGEN_COMP_MINGW 1\n#else\n  #define EIGEN_COMP_MINGW 0\n#endif\n\n/// \\internal EIGEN_COMP_SUNCC set to 1 if the compiler is Solaris Studio\n#if defined(__SUNPRO_CC)\n  #define EIGEN_COMP_SUNCC 1\n#else\n  #define EIGEN_COMP_SUNCC 0\n#endif\n\n/// \\internal EIGEN_COMP_MSVC set to _MSC_VER if the compiler is Microsoft Visual C++, 0 otherwise.\n#if defined(_MSC_VER)\n  #define EIGEN_COMP_MSVC _MSC_VER\n#else\n  #define EIGEN_COMP_MSVC 0\n#endif\n\n// For the record, here is a table summarizing the possible values for EIGEN_COMP_MSVC:\n//  name  ver   MSC_VER\n//  2008    9      1500\n//  2010   10      1600\n//  2012   11      1700\n//  2013   12      1800\n//  2015   14      1900\n//  \"15\"   15      1900\n\n/// \\internal EIGEN_COMP_MSVC_STRICT set to 1 if the compiler is really Microsoft Visual C++ and not ,e.g., ICC\n#if EIGEN_COMP_MSVC && !(EIGEN_COMP_ICC)\n  #define EIGEN_COMP_MSVC_STRICT _MSC_VER\n#else\n  #define EIGEN_COMP_MSVC_STRICT 0\n#endif\n\n/// \\internal EIGEN_COMP_IBM set to 1 if the compiler is IBM XL C++\n#if defined(__IBMCPP__) || defined(__xlc__)\n  #define EIGEN_COMP_IBM 1\n#else\n  #define EIGEN_COMP_IBM 0\n#endif\n\n/// \\internal EIGEN_COMP_PGI set to 1 if the compiler is Portland Group Compiler\n#if defined(__PGI)\n  #define EIGEN_COMP_PGI 1\n#else\n  #define EIGEN_COMP_PGI 0\n#endif\n\n/// \\internal EIGEN_COMP_ARM set to 1 if the compiler is ARM Compiler\n#if defined(__CC_ARM) || defined(__ARMCC_VERSION)\n  #define EIGEN_COMP_ARM 1\n#else\n  #define EIGEN_COMP_ARM 0\n#endif\n\n/// \\internal EIGEN_COMP_ARM set to 1 if the compiler is ARM Compiler\n#if defined(__EMSCRIPTEN__)\n  #define EIGEN_COMP_EMSCRIPTEN 1\n#else\n  #define EIGEN_COMP_EMSCRIPTEN 0\n#endif\n\n\n/// \\internal EIGEN_GNUC_STRICT set to 1 if the compiler is really GCC and not a compatible compiler (e.g., ICC, clang, mingw, etc.)\n#if EIGEN_COMP_GNUC && !(EIGEN_COMP_CLANG || EIGEN_COMP_ICC || EIGEN_COMP_MINGW || EIGEN_COMP_PGI || EIGEN_COMP_IBM || EIGEN_COMP_ARM || EIGEN_COMP_EMSCRIPTEN)\n  #define EIGEN_COMP_GNUC_STRICT 1\n#else\n  #define EIGEN_COMP_GNUC_STRICT 0\n#endif\n\n\n#if EIGEN_COMP_GNUC\n  #define EIGEN_GNUC_AT_LEAST(x,y) ((__GNUC__==x && __GNUC_MINOR__>=y) || __GNUC__>x)\n  #define EIGEN_GNUC_AT_MOST(x,y)  ((__GNUC__==x && __GNUC_MINOR__<=y) || __GNUC__<x)\n  #define EIGEN_GNUC_AT(x,y)       ( __GNUC__==x && __GNUC_MINOR__==y )\n#else\n  #define EIGEN_GNUC_AT_LEAST(x,y) 0\n  #define EIGEN_GNUC_AT_MOST(x,y)  0\n  #define EIGEN_GNUC_AT(x,y)       0\n#endif\n\n// FIXME: could probably be removed as we do not support gcc 3.x anymore\n#if EIGEN_COMP_GNUC && (__GNUC__ <= 3)\n#define EIGEN_GCC3_OR_OLDER 1\n#else\n#define EIGEN_GCC3_OR_OLDER 0\n#endif\n\n\n// Architecture identification, EIGEN_ARCH_*\n\n#if defined(__x86_64__) || defined(_M_X64) || defined(__amd64)\n  #define EIGEN_ARCH_x86_64 1\n#else\n  #define EIGEN_ARCH_x86_64 0\n#endif\n\n#if defined(__i386__) || defined(_M_IX86) || defined(_X86_) || defined(__i386)\n  #define EIGEN_ARCH_i386 1\n#else\n  #define EIGEN_ARCH_i386 0\n#endif\n\n#if EIGEN_ARCH_x86_64 || EIGEN_ARCH_i386\n  #define EIGEN_ARCH_i386_OR_x86_64 1\n#else\n  #define EIGEN_ARCH_i386_OR_x86_64 0\n#endif\n\n/// \\internal EIGEN_ARCH_ARM set to 1 if the architecture is ARM\n#if defined(__arm__)\n  #define EIGEN_ARCH_ARM 1\n#else\n  #define EIGEN_ARCH_ARM 0\n#endif\n\n/// \\internal EIGEN_ARCH_ARM64 set to 1 if the architecture is ARM64\n#if defined(__aarch64__)\n  #define EIGEN_ARCH_ARM64 1\n#else\n  #define EIGEN_ARCH_ARM64 0\n#endif\n\n#if EIGEN_ARCH_ARM || EIGEN_ARCH_ARM64\n  #define EIGEN_ARCH_ARM_OR_ARM64 1\n#else\n  #define EIGEN_ARCH_ARM_OR_ARM64 0\n#endif\n\n/// \\internal EIGEN_ARCH_MIPS set to 1 if the architecture is MIPS\n#if defined(__mips__) || defined(__mips)\n  #define EIGEN_ARCH_MIPS 1\n#else\n  #define EIGEN_ARCH_MIPS 0\n#endif\n\n/// \\internal EIGEN_ARCH_SPARC set to 1 if the architecture is SPARC\n#if defined(__sparc__) || defined(__sparc)\n  #define EIGEN_ARCH_SPARC 1\n#else\n  #define EIGEN_ARCH_SPARC 0\n#endif\n\n/// \\internal EIGEN_ARCH_IA64 set to 1 if the architecture is Intel Itanium\n#if defined(__ia64__)\n  #define EIGEN_ARCH_IA64 1\n#else\n  #define EIGEN_ARCH_IA64 0\n#endif\n\n/// \\internal EIGEN_ARCH_PPC set to 1 if the architecture is PowerPC\n#if defined(__powerpc__) || defined(__ppc__) || defined(_M_PPC)\n  #define EIGEN_ARCH_PPC 1\n#else\n  #define EIGEN_ARCH_PPC 0\n#endif\n\n\n\n// Operating system identification, EIGEN_OS_*\n\n/// \\internal EIGEN_OS_UNIX set to 1 if the OS is a unix variant\n#if defined(__unix__) || defined(__unix)\n  #define EIGEN_OS_UNIX 1\n#else\n  #define EIGEN_OS_UNIX 0\n#endif\n\n/// \\internal EIGEN_OS_LINUX set to 1 if the OS is based on Linux kernel\n#if defined(__linux__)\n  #define EIGEN_OS_LINUX 1\n#else\n  #define EIGEN_OS_LINUX 0\n#endif\n\n/// \\internal EIGEN_OS_ANDROID set to 1 if the OS is Android\n// note: ANDROID is defined when using ndk_build, __ANDROID__ is defined when using a standalone toolchain.\n#if defined(__ANDROID__) || defined(ANDROID)\n  #define EIGEN_OS_ANDROID 1\n#else\n  #define EIGEN_OS_ANDROID 0\n#endif\n\n/// \\internal EIGEN_OS_GNULINUX set to 1 if the OS is GNU Linux and not Linux-based OS (e.g., not android)\n#if defined(__gnu_linux__) && !(EIGEN_OS_ANDROID)\n  #define EIGEN_OS_GNULINUX 1\n#else\n  #define EIGEN_OS_GNULINUX 0\n#endif\n\n/// \\internal EIGEN_OS_BSD set to 1 if the OS is a BSD variant\n#if defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__bsdi__) || defined(__DragonFly__)\n  #define EIGEN_OS_BSD 1\n#else\n  #define EIGEN_OS_BSD 0\n#endif\n\n/// \\internal EIGEN_OS_MAC set to 1 if the OS is MacOS\n#if defined(__APPLE__)\n  #define EIGEN_OS_MAC 1\n#else\n  #define EIGEN_OS_MAC 0\n#endif\n\n/// \\internal EIGEN_OS_QNX set to 1 if the OS is QNX\n#if defined(__QNX__)\n  #define EIGEN_OS_QNX 1\n#else\n  #define EIGEN_OS_QNX 0\n#endif\n\n/// \\internal EIGEN_OS_WIN set to 1 if the OS is Windows based\n#if defined(_WIN32)\n  #define EIGEN_OS_WIN 1\n#else\n  #define EIGEN_OS_WIN 0\n#endif\n\n/// \\internal EIGEN_OS_WIN64 set to 1 if the OS is Windows 64bits\n#if defined(_WIN64)\n  #define EIGEN_OS_WIN64 1\n#else\n  #define EIGEN_OS_WIN64 0\n#endif\n\n/// \\internal EIGEN_OS_WINCE set to 1 if the OS is Windows CE\n#if defined(_WIN32_WCE)\n  #define EIGEN_OS_WINCE 1\n#else\n  #define EIGEN_OS_WINCE 0\n#endif\n\n/// \\internal EIGEN_OS_CYGWIN set to 1 if the OS is Windows/Cygwin\n#if defined(__CYGWIN__)\n  #define EIGEN_OS_CYGWIN 1\n#else\n  #define EIGEN_OS_CYGWIN 0\n#endif\n\n/// \\internal EIGEN_OS_WIN_STRICT set to 1 if the OS is really Windows and not some variants\n#if EIGEN_OS_WIN && !( EIGEN_OS_WINCE || EIGEN_OS_CYGWIN )\n  #define EIGEN_OS_WIN_STRICT 1\n#else\n  #define EIGEN_OS_WIN_STRICT 0\n#endif\n\n/// \\internal EIGEN_OS_SUN set to 1 if the OS is SUN\n#if (defined(sun) || defined(__sun)) && !(defined(__SVR4) || defined(__svr4__))\n  #define EIGEN_OS_SUN 1\n#else\n  #define EIGEN_OS_SUN 0\n#endif\n\n/// \\internal EIGEN_OS_SOLARIS set to 1 if the OS is Solaris\n#if (defined(sun) || defined(__sun)) && (defined(__SVR4) || defined(__svr4__))\n  #define EIGEN_OS_SOLARIS 1\n#else\n  #define EIGEN_OS_SOLARIS 0\n#endif\n\n\n\n#if EIGEN_GNUC_AT_MOST(4,3) && !EIGEN_COMP_CLANG\n  // see bug 89\n  #define EIGEN_SAFE_TO_USE_STANDARD_ASSERT_MACRO 0\n#else\n  #define EIGEN_SAFE_TO_USE_STANDARD_ASSERT_MACRO 1\n#endif\n\n// This macro can be used to prevent from macro expansion, e.g.:\n//   std::max EIGEN_NOT_A_MACRO(a,b)\n#define EIGEN_NOT_A_MACRO\n\n#ifdef EIGEN_DEFAULT_TO_ROW_MAJOR\n#define EIGEN_DEFAULT_MATRIX_STORAGE_ORDER_OPTION Eigen::RowMajor\n#else\n#define EIGEN_DEFAULT_MATRIX_STORAGE_ORDER_OPTION Eigen::ColMajor\n#endif\n\n#ifndef EIGEN_DEFAULT_DENSE_INDEX_TYPE\n#define EIGEN_DEFAULT_DENSE_INDEX_TYPE std::ptrdiff_t\n#endif\n\n// Cross compiler wrapper around LLVM's __has_builtin\n#ifdef __has_builtin\n#  define EIGEN_HAS_BUILTIN(x) __has_builtin(x)\n#else\n#  define EIGEN_HAS_BUILTIN(x) 0\n#endif\n\n// A Clang feature extension to determine compiler features.\n// We use it to determine 'cxx_rvalue_references'\n#ifndef __has_feature\n# define __has_feature(x) 0\n#endif\n\n// Upperbound on the C++ version to use.\n// Expected values are 03, 11, 14, 17, etc.\n// By default, let's use an arbitrarily large C++ version.\n#ifndef EIGEN_MAX_CPP_VER\n#define EIGEN_MAX_CPP_VER 99\n#endif\n\n#if EIGEN_MAX_CPP_VER>=11 && defined(__cplusplus) && (__cplusplus >= 201103L)\n#define EIGEN_HAS_CXX11 1\n#else\n#define EIGEN_HAS_CXX11 0\n#endif\n\n\n// Do we support r-value references?\n#ifndef EIGEN_HAS_RVALUE_REFERENCES\n#if EIGEN_MAX_CPP_VER>=11 && \\\n    (__has_feature(cxx_rvalue_references) || \\\n    (defined(__cplusplus) && __cplusplus >= 201103L) || \\\n    (EIGEN_COMP_MSVC >= 1600))\n  #define EIGEN_HAS_RVALUE_REFERENCES 1\n#else\n  #define EIGEN_HAS_RVALUE_REFERENCES 0\n#endif\n#endif\n\n// Does the compiler support C99?\n#ifndef EIGEN_HAS_C99_MATH\n#if EIGEN_MAX_CPP_VER>=11 && \\\n    ((defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901))       \\\n  || (defined(__GNUC__) && defined(_GLIBCXX_USE_C99)) \\\n  || (defined(_LIBCPP_VERSION) && !defined(_MSC_VER)))\n  #define EIGEN_HAS_C99_MATH 1\n#else\n  #define EIGEN_HAS_C99_MATH 0\n#endif\n#endif\n\n// Does the compiler support result_of?\n#ifndef EIGEN_HAS_STD_RESULT_OF\n#if EIGEN_MAX_CPP_VER>=11 && ((__has_feature(cxx_lambdas) || (defined(__cplusplus) && __cplusplus >= 201103L)))\n#define EIGEN_HAS_STD_RESULT_OF 1\n#else\n#define EIGEN_HAS_STD_RESULT_OF 0\n#endif\n#endif\n\n// Does the compiler support variadic templates?\n#ifndef EIGEN_HAS_VARIADIC_TEMPLATES\n#if EIGEN_MAX_CPP_VER>=11 && (__cplusplus > 199711L || EIGEN_COMP_MSVC >= 1900) \\\n  && ( !defined(__NVCC__) || !EIGEN_ARCH_ARM_OR_ARM64 || (defined __CUDACC_VER__ && __CUDACC_VER__ >= 80000) )\n    // ^^ Disable the use of variadic templates when compiling with versions of nvcc older than 8.0 on ARM devices:\n    //    this prevents nvcc from crashing when compiling Eigen on Tegra X1\n#define EIGEN_HAS_VARIADIC_TEMPLATES 1\n#else\n#define EIGEN_HAS_VARIADIC_TEMPLATES 0\n#endif\n#endif\n\n// Does the compiler fully support const expressions? (as in c++14)\n#ifndef EIGEN_HAS_CONSTEXPR\n\n#ifdef __CUDACC__\n// Const expressions are supported provided that c++11 is enabled and we're using either clang or nvcc 7.5 or above\n#if EIGEN_MAX_CPP_VER>=14 && (__cplusplus > 199711L && defined(__CUDACC_VER__) && (EIGEN_COMP_CLANG || __CUDACC_VER__ >= 70500))\n  #define EIGEN_HAS_CONSTEXPR 1\n#endif\n#elif EIGEN_MAX_CPP_VER>=14 && (__has_feature(cxx_relaxed_constexpr) || (defined(__cplusplus) && __cplusplus >= 201402L) || \\\n  (EIGEN_GNUC_AT_LEAST(4,8) && (__cplusplus > 199711L)))\n#define EIGEN_HAS_CONSTEXPR 1\n#endif\n\n#ifndef EIGEN_HAS_CONSTEXPR\n#define EIGEN_HAS_CONSTEXPR 0\n#endif\n\n#endif\n\n// Does the compiler support C++11 math?\n// Let's be conservative and enable the default C++11 implementation only if we are sure it exists\n#ifndef EIGEN_HAS_CXX11_MATH\n  #if EIGEN_MAX_CPP_VER>=11 && ((__cplusplus > 201103L) || (__cplusplus >= 201103L) && (EIGEN_COMP_GNUC_STRICT || EIGEN_COMP_CLANG || EIGEN_COMP_MSVC || EIGEN_COMP_ICC)  \\\n      && (EIGEN_ARCH_i386_OR_x86_64) && (EIGEN_OS_GNULINUX || EIGEN_OS_WIN_STRICT || EIGEN_OS_MAC))\n    #define EIGEN_HAS_CXX11_MATH 1\n  #else\n    #define EIGEN_HAS_CXX11_MATH 0\n  #endif\n#endif\n\n// Does the compiler support proper C++11 containers?\n#ifndef EIGEN_HAS_CXX11_CONTAINERS\n  #if    EIGEN_MAX_CPP_VER>=11 && \\\n         ((__cplusplus > 201103L) \\\n      || ((__cplusplus >= 201103L) && (EIGEN_COMP_GNUC_STRICT || EIGEN_COMP_CLANG || EIGEN_COMP_ICC>=1400)) \\\n      || EIGEN_COMP_MSVC >= 1900)\n    #define EIGEN_HAS_CXX11_CONTAINERS 1\n  #else\n    #define EIGEN_HAS_CXX11_CONTAINERS 0\n  #endif\n#endif\n\n// Does the compiler support C++11 noexcept?\n#ifndef EIGEN_HAS_CXX11_NOEXCEPT\n  #if    EIGEN_MAX_CPP_VER>=11 && \\\n         (__has_feature(cxx_noexcept) \\\n      || (__cplusplus > 201103L) \\\n      || ((__cplusplus >= 201103L) && (EIGEN_COMP_GNUC_STRICT || EIGEN_COMP_CLANG || EIGEN_COMP_ICC>=1400)) \\\n      || EIGEN_COMP_MSVC >= 1900)\n    #define EIGEN_HAS_CXX11_NOEXCEPT 1\n  #else\n    #define EIGEN_HAS_CXX11_NOEXCEPT 0\n  #endif\n#endif\n\n/** Allows to disable some optimizations which might affect the accuracy of the result.\n  * Such optimization are enabled by default, and set EIGEN_FAST_MATH to 0 to disable them.\n  * They currently include:\n  *   - single precision ArrayBase::sin() and ArrayBase::cos() for SSE and AVX vectorization.\n  */\n#ifndef EIGEN_FAST_MATH\n#define EIGEN_FAST_MATH 1\n#endif\n\n#define EIGEN_DEBUG_VAR(x) std::cerr << #x << \" = \" << x << std::endl;\n\n// concatenate two tokens\n#define EIGEN_CAT2(a,b) a ## b\n#define EIGEN_CAT(a,b) EIGEN_CAT2(a,b)\n\n#define EIGEN_COMMA ,\n\n// convert a token to a string\n#define EIGEN_MAKESTRING2(a) #a\n#define EIGEN_MAKESTRING(a) EIGEN_MAKESTRING2(a)\n\n// EIGEN_STRONG_INLINE is a stronger version of the inline, using __forceinline on MSVC,\n// but it still doesn't use GCC's always_inline. This is useful in (common) situations where MSVC needs forceinline\n// but GCC is still doing fine with just inline.\n#if EIGEN_COMP_MSVC || EIGEN_COMP_ICC\n#define EIGEN_STRONG_INLINE __forceinline\n#else\n#define EIGEN_STRONG_INLINE inline\n#endif\n\n// EIGEN_ALWAYS_INLINE is the stronget, it has the effect of making the function inline and adding every possible\n// attribute to maximize inlining. This should only be used when really necessary: in particular,\n// it uses __attribute__((always_inline)) on GCC, which most of the time is useless and can severely harm compile times.\n// FIXME with the always_inline attribute,\n// gcc 3.4.x reports the following compilation error:\n//   Eval.h:91: sorry, unimplemented: inlining failed in call to 'const Eigen::Eval<Derived> Eigen::MatrixBase<Scalar, Derived>::eval() const'\n//    : function body not available\n#if EIGEN_GNUC_AT_LEAST(4,0)\n#define EIGEN_ALWAYS_INLINE __attribute__((always_inline)) inline\n#else\n#define EIGEN_ALWAYS_INLINE EIGEN_STRONG_INLINE\n#endif\n\n#if EIGEN_COMP_GNUC\n#define EIGEN_DONT_INLINE __attribute__((noinline))\n#elif EIGEN_COMP_MSVC\n#define EIGEN_DONT_INLINE __declspec(noinline)\n#else\n#define EIGEN_DONT_INLINE\n#endif\n\n#if EIGEN_COMP_GNUC\n#define EIGEN_PERMISSIVE_EXPR __extension__\n#else\n#define EIGEN_PERMISSIVE_EXPR\n#endif\n\n// this macro allows to get rid of linking errors about multiply defined functions.\n//  - static is not very good because it prevents definitions from different object files to be merged.\n//           So static causes the resulting linked executable to be bloated with multiple copies of the same function.\n//  - inline is not perfect either as it unwantedly hints the compiler toward inlining the function.\n#define EIGEN_DECLARE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS\n#define EIGEN_DEFINE_FUNCTION_ALLOWING_MULTIPLE_DEFINITIONS inline\n\n#ifdef NDEBUG\n# ifndef EIGEN_NO_DEBUG\n#  define EIGEN_NO_DEBUG\n# endif\n#endif\n\n// eigen_plain_assert is where we implement the workaround for the assert() bug in GCC <= 4.3, see bug 89\n#ifdef EIGEN_NO_DEBUG\n  #define eigen_plain_assert(x)\n#else\n  #if EIGEN_SAFE_TO_USE_STANDARD_ASSERT_MACRO\n    namespace Eigen {\n    namespace internal {\n    inline bool copy_bool(bool b) { return b; }\n    }\n    }\n    #define eigen_plain_assert(x) assert(x)\n  #else\n    // work around bug 89\n    #include <cstdlib>   // for abort\n    #include <iostream>  // for std::cerr\n\n    namespace Eigen {\n    namespace internal {\n    // trivial function copying a bool. Must be EIGEN_DONT_INLINE, so we implement it after including Eigen headers.\n    // see bug 89.\n    namespace {\n    EIGEN_DONT_INLINE bool copy_bool(bool b) { return b; }\n    }\n    inline void assert_fail(const char *condition, const char *function, const char *file, int line)\n    {\n      std::cerr << \"assertion failed: \" << condition << \" in function \" << function << \" at \" << file << \":\" << line << std::endl;\n      abort();\n    }\n    }\n    }\n    #define eigen_plain_assert(x) \\\n      do { \\\n        if(!Eigen::internal::copy_bool(x)) \\\n          Eigen::internal::assert_fail(EIGEN_MAKESTRING(x), __PRETTY_FUNCTION__, __FILE__, __LINE__); \\\n      } while(false)\n  #endif\n#endif\n\n// eigen_assert can be overridden\n#ifndef eigen_assert\n#define eigen_assert(x) eigen_plain_assert(x)\n#endif\n\n#ifdef EIGEN_INTERNAL_DEBUGGING\n#define eigen_internal_assert(x) eigen_assert(x)\n#else\n#define eigen_internal_assert(x)\n#endif\n\n#ifdef EIGEN_NO_DEBUG\n#define EIGEN_ONLY_USED_FOR_DEBUG(x) EIGEN_UNUSED_VARIABLE(x)\n#else\n#define EIGEN_ONLY_USED_FOR_DEBUG(x)\n#endif\n\n#ifndef EIGEN_NO_DEPRECATED_WARNING\n  #if EIGEN_COMP_GNUC\n    #define EIGEN_DEPRECATED __attribute__((deprecated))\n  #elif EIGEN_COMP_MSVC\n    #define EIGEN_DEPRECATED __declspec(deprecated)\n  #else\n    #define EIGEN_DEPRECATED\n  #endif\n#else\n  #define EIGEN_DEPRECATED\n#endif\n\n#if EIGEN_COMP_GNUC\n#define EIGEN_UNUSED __attribute__((unused))\n#else\n#define EIGEN_UNUSED\n#endif\n\n// Suppresses 'unused variable' warnings.\nnamespace Eigen {\n  namespace internal {\n    template<typename T> EIGEN_DEVICE_FUNC void ignore_unused_variable(const T&) {}\n  }\n}\n#define EIGEN_UNUSED_VARIABLE(var) Eigen::internal::ignore_unused_variable(var);\n\n#if !defined(EIGEN_ASM_COMMENT)\n  #if EIGEN_COMP_GNUC && (EIGEN_ARCH_i386_OR_x86_64 || EIGEN_ARCH_ARM_OR_ARM64)\n    #define EIGEN_ASM_COMMENT(X)  __asm__(\"#\" X)\n  #else\n    #define EIGEN_ASM_COMMENT(X)\n  #endif\n#endif\n\n\n//------------------------------------------------------------------------------------------\n// Static and dynamic alignment control\n//\n// The main purpose of this section is to define EIGEN_MAX_ALIGN_BYTES and EIGEN_MAX_STATIC_ALIGN_BYTES\n// as the maximal boundary in bytes on which dynamically and statically allocated data may be alignment respectively.\n// The values of EIGEN_MAX_ALIGN_BYTES and EIGEN_MAX_STATIC_ALIGN_BYTES can be specified by the user. If not,\n// a default value is automatically computed based on architecture, compiler, and OS.\n//\n// This section also defines macros EIGEN_ALIGN_TO_BOUNDARY(N) and the shortcuts EIGEN_ALIGN{8,16,32,_MAX}\n// to be used to declare statically aligned buffers.\n//------------------------------------------------------------------------------------------\n\n\n/* EIGEN_ALIGN_TO_BOUNDARY(n) forces data to be n-byte aligned. This is used to satisfy SIMD requirements.\n * However, we do that EVEN if vectorization (EIGEN_VECTORIZE) is disabled,\n * so that vectorization doesn't affect binary compatibility.\n *\n * If we made alignment depend on whether or not EIGEN_VECTORIZE is defined, it would be impossible to link\n * vectorized and non-vectorized code.\n */\n#if (defined __CUDACC__)\n  #define EIGEN_ALIGN_TO_BOUNDARY(n) __align__(n)\n#elif EIGEN_COMP_GNUC || EIGEN_COMP_PGI || EIGEN_COMP_IBM || EIGEN_COMP_ARM\n  #define EIGEN_ALIGN_TO_BOUNDARY(n) __attribute__((aligned(n)))\n#elif EIGEN_COMP_MSVC\n  #define EIGEN_ALIGN_TO_BOUNDARY(n) __declspec(align(n))\n#elif EIGEN_COMP_SUNCC\n  // FIXME not sure about this one:\n  #define EIGEN_ALIGN_TO_BOUNDARY(n) __attribute__((aligned(n)))\n#else\n  #error Please tell me what is the equivalent of __attribute__((aligned(n))) for your compiler\n#endif\n\n// If the user explicitly disable vectorization, then we also disable alignment\n#if defined(EIGEN_DONT_VECTORIZE)\n  #define EIGEN_IDEAL_MAX_ALIGN_BYTES 0\n#elif defined(EIGEN_VECTORIZE_AVX512)\n  // 64 bytes static alignmeent is preferred only if really required\n  #define EIGEN_IDEAL_MAX_ALIGN_BYTES 64\n#elif defined(__AVX__)\n  // 32 bytes static alignmeent is preferred only if really required\n  #define EIGEN_IDEAL_MAX_ALIGN_BYTES 32\n#else\n  #define EIGEN_IDEAL_MAX_ALIGN_BYTES 16\n#endif\n\n\n// EIGEN_MIN_ALIGN_BYTES defines the minimal value for which the notion of explicit alignment makes sense\n#define EIGEN_MIN_ALIGN_BYTES 16\n\n// Defined the boundary (in bytes) on which the data needs to be aligned. Note\n// that unless EIGEN_ALIGN is defined and not equal to 0, the data may not be\n// aligned at all regardless of the value of this #define.\n\n#if (defined(EIGEN_DONT_ALIGN_STATICALLY) || defined(EIGEN_DONT_ALIGN))  && defined(EIGEN_MAX_STATIC_ALIGN_BYTES) && EIGEN_MAX_STATIC_ALIGN_BYTES>0\n#error EIGEN_MAX_STATIC_ALIGN_BYTES and EIGEN_DONT_ALIGN[_STATICALLY] are both defined with EIGEN_MAX_STATIC_ALIGN_BYTES!=0. Use EIGEN_MAX_STATIC_ALIGN_BYTES=0 as a synonym of EIGEN_DONT_ALIGN_STATICALLY.\n#endif\n\n// EIGEN_DONT_ALIGN_STATICALLY and EIGEN_DONT_ALIGN are deprectated\n// They imply EIGEN_MAX_STATIC_ALIGN_BYTES=0\n#if defined(EIGEN_DONT_ALIGN_STATICALLY) || defined(EIGEN_DONT_ALIGN)\n  #ifdef EIGEN_MAX_STATIC_ALIGN_BYTES\n    #undef EIGEN_MAX_STATIC_ALIGN_BYTES\n  #endif\n  #define EIGEN_MAX_STATIC_ALIGN_BYTES 0\n#endif\n\n#ifndef EIGEN_MAX_STATIC_ALIGN_BYTES\n\n  // Try to automatically guess what is the best default value for EIGEN_MAX_STATIC_ALIGN_BYTES\n\n  // 16 byte alignment is only useful for vectorization. Since it affects the ABI, we need to enable\n  // 16 byte alignment on all platforms where vectorization might be enabled. In theory we could always\n  // enable alignment, but it can be a cause of problems on some platforms, so we just disable it in\n  // certain common platform (compiler+architecture combinations) to avoid these problems.\n  // Only static alignment is really problematic (relies on nonstandard compiler extensions),\n  // try to keep heap alignment even when we have to disable static alignment.\n  #if EIGEN_COMP_GNUC && !(EIGEN_ARCH_i386_OR_x86_64 || EIGEN_ARCH_ARM_OR_ARM64 || EIGEN_ARCH_PPC || EIGEN_ARCH_IA64)\n  #define EIGEN_GCC_AND_ARCH_DOESNT_WANT_STACK_ALIGNMENT 1\n  #elif EIGEN_ARCH_ARM_OR_ARM64 && EIGEN_COMP_GNUC_STRICT && EIGEN_GNUC_AT_MOST(4, 6)\n  // Old versions of GCC on ARM, at least 4.4, were once seen to have buggy static alignment support.\n  // Not sure which version fixed it, hopefully it doesn't affect 4.7, which is still somewhat in use.\n  // 4.8 and newer seem definitely unaffected.\n  #define EIGEN_GCC_AND_ARCH_DOESNT_WANT_STACK_ALIGNMENT 1\n  #else\n  #define EIGEN_GCC_AND_ARCH_DOESNT_WANT_STACK_ALIGNMENT 0\n  #endif\n\n  // static alignment is completely disabled with GCC 3, Sun Studio, and QCC/QNX\n  #if !EIGEN_GCC_AND_ARCH_DOESNT_WANT_STACK_ALIGNMENT \\\n  && !EIGEN_GCC3_OR_OLDER \\\n  && !EIGEN_COMP_SUNCC \\\n  && !EIGEN_OS_QNX\n    #define EIGEN_ARCH_WANTS_STACK_ALIGNMENT 1\n  #else\n    #define EIGEN_ARCH_WANTS_STACK_ALIGNMENT 0\n  #endif\n\n  #if EIGEN_ARCH_WANTS_STACK_ALIGNMENT\n    #define EIGEN_MAX_STATIC_ALIGN_BYTES EIGEN_IDEAL_MAX_ALIGN_BYTES\n  #else\n    #define EIGEN_MAX_STATIC_ALIGN_BYTES 0\n  #endif\n\n#endif\n\n// If EIGEN_MAX_ALIGN_BYTES is defined, then it is considered as an upper bound for EIGEN_MAX_ALIGN_BYTES\n#if defined(EIGEN_MAX_ALIGN_BYTES) && EIGEN_MAX_ALIGN_BYTES<EIGEN_MAX_STATIC_ALIGN_BYTES\n#undef EIGEN_MAX_STATIC_ALIGN_BYTES\n#define EIGEN_MAX_STATIC_ALIGN_BYTES EIGEN_MAX_ALIGN_BYTES\n#endif\n\n#if EIGEN_MAX_STATIC_ALIGN_BYTES==0 && !defined(EIGEN_DISABLE_UNALIGNED_ARRAY_ASSERT)\n  #define EIGEN_DISABLE_UNALIGNED_ARRAY_ASSERT\n#endif\n\n// At this stage, EIGEN_MAX_STATIC_ALIGN_BYTES>0 is the true test whether we want to align arrays on the stack or not.\n// It takes into account both the user choice to explicitly enable/disable alignment (by settting EIGEN_MAX_STATIC_ALIGN_BYTES)\n// and the architecture config (EIGEN_ARCH_WANTS_STACK_ALIGNMENT).\n// Henceforth, only EIGEN_MAX_STATIC_ALIGN_BYTES should be used.\n\n\n// Shortcuts to EIGEN_ALIGN_TO_BOUNDARY\n#define EIGEN_ALIGN8  EIGEN_ALIGN_TO_BOUNDARY(8)\n#define EIGEN_ALIGN16 EIGEN_ALIGN_TO_BOUNDARY(16)\n#define EIGEN_ALIGN32 EIGEN_ALIGN_TO_BOUNDARY(32)\n#define EIGEN_ALIGN64 EIGEN_ALIGN_TO_BOUNDARY(64)\n#if EIGEN_MAX_STATIC_ALIGN_BYTES>0\n#define EIGEN_ALIGN_MAX EIGEN_ALIGN_TO_BOUNDARY(EIGEN_MAX_STATIC_ALIGN_BYTES)\n#else\n#define EIGEN_ALIGN_MAX\n#endif\n\n\n// Dynamic alignment control\n\n#if defined(EIGEN_DONT_ALIGN) && defined(EIGEN_MAX_ALIGN_BYTES) && EIGEN_MAX_ALIGN_BYTES>0\n#error EIGEN_MAX_ALIGN_BYTES and EIGEN_DONT_ALIGN are both defined with EIGEN_MAX_ALIGN_BYTES!=0. Use EIGEN_MAX_ALIGN_BYTES=0 as a synonym of EIGEN_DONT_ALIGN.\n#endif\n\n#ifdef EIGEN_DONT_ALIGN\n  #ifdef EIGEN_MAX_ALIGN_BYTES\n    #undef EIGEN_MAX_ALIGN_BYTES\n  #endif\n  #define EIGEN_MAX_ALIGN_BYTES 0\n#elif !defined(EIGEN_MAX_ALIGN_BYTES)\n  #define EIGEN_MAX_ALIGN_BYTES EIGEN_IDEAL_MAX_ALIGN_BYTES\n#endif\n\n#if EIGEN_IDEAL_MAX_ALIGN_BYTES > EIGEN_MAX_ALIGN_BYTES\n#define EIGEN_DEFAULT_ALIGN_BYTES EIGEN_IDEAL_MAX_ALIGN_BYTES\n#else\n#define EIGEN_DEFAULT_ALIGN_BYTES EIGEN_MAX_ALIGN_BYTES\n#endif\n\n\n#ifndef EIGEN_UNALIGNED_VECTORIZE\n#define EIGEN_UNALIGNED_VECTORIZE 1\n#endif\n\n//----------------------------------------------------------------------\n\n\n#ifdef EIGEN_DONT_USE_RESTRICT_KEYWORD\n  #define EIGEN_RESTRICT\n#endif\n#ifndef EIGEN_RESTRICT\n  #define EIGEN_RESTRICT __restrict\n#endif\n\n#ifndef EIGEN_STACK_ALLOCATION_LIMIT\n// 131072 == 128 KB\n#define EIGEN_STACK_ALLOCATION_LIMIT 131072\n#endif\n\n#ifndef EIGEN_DEFAULT_IO_FORMAT\n#ifdef EIGEN_MAKING_DOCS\n// format used in Eigen's documentation\n// needed to define it here as escaping characters in CMake add_definition's argument seems very problematic.\n#define EIGEN_DEFAULT_IO_FORMAT Eigen::IOFormat(3, 0, \" \", \"\\n\", \"\", \"\")\n#else\n#define EIGEN_DEFAULT_IO_FORMAT Eigen::IOFormat()\n#endif\n#endif\n\n// just an empty macro !\n#define EIGEN_EMPTY\n\n#if EIGEN_COMP_MSVC_STRICT && (EIGEN_COMP_MSVC < 1900 ||  __CUDACC_VER__) // for older MSVC versions, as well as 1900 && CUDA 8, using the base operator is sufficient (cf Bugs 1000, 1324)\n  #define EIGEN_INHERIT_ASSIGNMENT_EQUAL_OPERATOR(Derived) \\\n    using Base::operator =;\n#elif EIGEN_COMP_CLANG // workaround clang bug (see http://forum.kde.org/viewtopic.php?f=74&t=102653)\n  #define EIGEN_INHERIT_ASSIGNMENT_EQUAL_OPERATOR(Derived) \\\n    using Base::operator =; \\\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE Derived& operator=(const Derived& other) { Base::operator=(other); return *this; } \\\n    template <typename OtherDerived> \\\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE Derived& operator=(const DenseBase<OtherDerived>& other) { Base::operator=(other.derived()); return *this; }\n#else\n  #define EIGEN_INHERIT_ASSIGNMENT_EQUAL_OPERATOR(Derived) \\\n    using Base::operator =; \\\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE Derived& operator=(const Derived& other) \\\n    { \\\n      Base::operator=(other); \\\n      return *this; \\\n    }\n#endif\n\n\n/** \\internal\n * \\brief Macro to manually inherit assignment operators.\n * This is necessary, because the implicitly defined assignment operator gets deleted when a custom operator= is defined.\n */\n#define EIGEN_INHERIT_ASSIGNMENT_OPERATORS(Derived) EIGEN_INHERIT_ASSIGNMENT_EQUAL_OPERATOR(Derived)\n\n/**\n* Just a side note. Commenting within defines works only by documenting\n* behind the object (via '!<'). Comments cannot be multi-line and thus\n* we have these extra long lines. What is confusing doxygen over here is\n* that we use '\\' and basically have a bunch of typedefs with their\n* documentation in a single line.\n**/\n\n#define EIGEN_GENERIC_PUBLIC_INTERFACE(Derived) \\\n  typedef typename Eigen::internal::traits<Derived>::Scalar Scalar; /*!< \\brief Numeric type, e.g. float, double, int or std::complex<float>. */ \\\n  typedef typename Eigen::NumTraits<Scalar>::Real RealScalar; /*!< \\brief The underlying numeric type for composed scalar types. \\details In cases where Scalar is e.g. std::complex<T>, T were corresponding to RealScalar. */ \\\n  typedef typename Base::CoeffReturnType CoeffReturnType; /*!< \\brief The return type for coefficient access. \\details Depending on whether the object allows direct coefficient access (e.g. for a MatrixXd), this type is either 'const Scalar&' or simply 'Scalar' for objects that do not allow direct coefficient access. */ \\\n  typedef typename Eigen::internal::ref_selector<Derived>::type Nested; \\\n  typedef typename Eigen::internal::traits<Derived>::StorageKind StorageKind; \\\n  typedef typename Eigen::internal::traits<Derived>::StorageIndex StorageIndex; \\\n  enum { RowsAtCompileTime = Eigen::internal::traits<Derived>::RowsAtCompileTime, \\\n        ColsAtCompileTime = Eigen::internal::traits<Derived>::ColsAtCompileTime, \\\n        Flags = Eigen::internal::traits<Derived>::Flags, \\\n        SizeAtCompileTime = Base::SizeAtCompileTime, \\\n        MaxSizeAtCompileTime = Base::MaxSizeAtCompileTime, \\\n        IsVectorAtCompileTime = Base::IsVectorAtCompileTime }; \\\n  using Base::derived; \\\n  using Base::const_cast_derived;\n\n\n// FIXME Maybe the EIGEN_DENSE_PUBLIC_INTERFACE could be removed as importing PacketScalar is rarely needed\n#define EIGEN_DENSE_PUBLIC_INTERFACE(Derived) \\\n  EIGEN_GENERIC_PUBLIC_INTERFACE(Derived) \\\n  typedef typename Base::PacketScalar PacketScalar;\n\n\n#define EIGEN_PLAIN_ENUM_MIN(a,b) (((int)a <= (int)b) ? (int)a : (int)b)\n#define EIGEN_PLAIN_ENUM_MAX(a,b) (((int)a >= (int)b) ? (int)a : (int)b)\n\n// EIGEN_SIZE_MIN_PREFER_DYNAMIC gives the min between compile-time sizes. 0 has absolute priority, followed by 1,\n// followed by Dynamic, followed by other finite values. The reason for giving Dynamic the priority over\n// finite values is that min(3, Dynamic) should be Dynamic, since that could be anything between 0 and 3.\n#define EIGEN_SIZE_MIN_PREFER_DYNAMIC(a,b) (((int)a == 0 || (int)b == 0) ? 0 \\\n                           : ((int)a == 1 || (int)b == 1) ? 1 \\\n                           : ((int)a == Dynamic || (int)b == Dynamic) ? Dynamic \\\n                           : ((int)a <= (int)b) ? (int)a : (int)b)\n\n// EIGEN_SIZE_MIN_PREFER_FIXED is a variant of EIGEN_SIZE_MIN_PREFER_DYNAMIC comparing MaxSizes. The difference is that finite values\n// now have priority over Dynamic, so that min(3, Dynamic) gives 3. Indeed, whatever the actual value is\n// (between 0 and 3), it is not more than 3.\n#define EIGEN_SIZE_MIN_PREFER_FIXED(a,b)  (((int)a == 0 || (int)b == 0) ? 0 \\\n                           : ((int)a == 1 || (int)b == 1) ? 1 \\\n                           : ((int)a == Dynamic && (int)b == Dynamic) ? Dynamic \\\n                           : ((int)a == Dynamic) ? (int)b \\\n                           : ((int)b == Dynamic) ? (int)a \\\n                           : ((int)a <= (int)b) ? (int)a : (int)b)\n\n// see EIGEN_SIZE_MIN_PREFER_DYNAMIC. No need for a separate variant for MaxSizes here.\n#define EIGEN_SIZE_MAX(a,b) (((int)a == Dynamic || (int)b == Dynamic) ? Dynamic \\\n                           : ((int)a >= (int)b) ? (int)a : (int)b)\n\n#define EIGEN_LOGICAL_XOR(a,b) (((a) || (b)) && !((a) && (b)))\n\n#define EIGEN_IMPLIES(a,b) (!(a) || (b))\n\n// the expression type of a standard coefficient wise binary operation\n#define EIGEN_CWISE_BINARY_RETURN_TYPE(LHS,RHS,OPNAME) \\\n    CwiseBinaryOp< \\\n      EIGEN_CAT(EIGEN_CAT(internal::scalar_,OPNAME),_op)< \\\n          typename internal::traits<LHS>::Scalar, \\\n          typename internal::traits<RHS>::Scalar \\\n      >, \\\n      const LHS, \\\n      const RHS \\\n    >\n\n#define EIGEN_MAKE_CWISE_BINARY_OP(METHOD,OPNAME) \\\n  template<typename OtherDerived> \\\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const EIGEN_CWISE_BINARY_RETURN_TYPE(Derived,OtherDerived,OPNAME) \\\n  (METHOD)(const EIGEN_CURRENT_STORAGE_BASE_CLASS<OtherDerived> &other) const \\\n  { \\\n    return EIGEN_CWISE_BINARY_RETURN_TYPE(Derived,OtherDerived,OPNAME)(derived(), other.derived()); \\\n  }\n\n#define EIGEN_SCALAR_BINARY_SUPPORTED(OPNAME,TYPEA,TYPEB) \\\n  (Eigen::internal::has_ReturnType<Eigen::ScalarBinaryOpTraits<TYPEA,TYPEB,EIGEN_CAT(EIGEN_CAT(Eigen::internal::scalar_,OPNAME),_op)<TYPEA,TYPEB>  > >::value)\n\n#define EIGEN_EXPR_BINARYOP_SCALAR_RETURN_TYPE(EXPR,SCALAR,OPNAME) \\\n  CwiseBinaryOp<EIGEN_CAT(EIGEN_CAT(internal::scalar_,OPNAME),_op)<typename internal::traits<EXPR>::Scalar,SCALAR>, const EXPR, \\\n                const typename internal::plain_constant_type<EXPR,SCALAR>::type>\n\n#define EIGEN_SCALAR_BINARYOP_EXPR_RETURN_TYPE(SCALAR,EXPR,OPNAME) \\\n  CwiseBinaryOp<EIGEN_CAT(EIGEN_CAT(internal::scalar_,OPNAME),_op)<SCALAR,typename internal::traits<EXPR>::Scalar>, \\\n                const typename internal::plain_constant_type<EXPR,SCALAR>::type, const EXPR>\n\n// Workaround for MSVC 2010 (see ML thread \"patch with compile for for MSVC 2010\")\n#if EIGEN_COMP_MSVC_STRICT<=1600\n#define EIGEN_MSVC10_WORKAROUND_BINARYOP_RETURN_TYPE(X) typename internal::enable_if<true,X>::type\n#else\n#define EIGEN_MSVC10_WORKAROUND_BINARYOP_RETURN_TYPE(X) X\n#endif\n\n#define EIGEN_MAKE_SCALAR_BINARY_OP_ONTHERIGHT(METHOD,OPNAME) \\\n  template <typename T> EIGEN_DEVICE_FUNC inline \\\n  EIGEN_MSVC10_WORKAROUND_BINARYOP_RETURN_TYPE(const EIGEN_EXPR_BINARYOP_SCALAR_RETURN_TYPE(Derived,typename internal::promote_scalar_arg<Scalar EIGEN_COMMA T EIGEN_COMMA EIGEN_SCALAR_BINARY_SUPPORTED(OPNAME,Scalar,T)>::type,OPNAME))\\\n  (METHOD)(const T& scalar) const { \\\n    typedef typename internal::promote_scalar_arg<Scalar,T,EIGEN_SCALAR_BINARY_SUPPORTED(OPNAME,Scalar,T)>::type PromotedT; \\\n    return EIGEN_EXPR_BINARYOP_SCALAR_RETURN_TYPE(Derived,PromotedT,OPNAME)(derived(), \\\n           typename internal::plain_constant_type<Derived,PromotedT>::type(derived().rows(), derived().cols(), internal::scalar_constant_op<PromotedT>(scalar))); \\\n  }\n\n#define EIGEN_MAKE_SCALAR_BINARY_OP_ONTHELEFT(METHOD,OPNAME) \\\n  template <typename T> EIGEN_DEVICE_FUNC inline friend \\\n  EIGEN_MSVC10_WORKAROUND_BINARYOP_RETURN_TYPE(const EIGEN_SCALAR_BINARYOP_EXPR_RETURN_TYPE(typename internal::promote_scalar_arg<Scalar EIGEN_COMMA T EIGEN_COMMA EIGEN_SCALAR_BINARY_SUPPORTED(OPNAME,T,Scalar)>::type,Derived,OPNAME)) \\\n  (METHOD)(const T& scalar, const StorageBaseType& matrix) { \\\n    typedef typename internal::promote_scalar_arg<Scalar,T,EIGEN_SCALAR_BINARY_SUPPORTED(OPNAME,T,Scalar)>::type PromotedT; \\\n    return EIGEN_SCALAR_BINARYOP_EXPR_RETURN_TYPE(PromotedT,Derived,OPNAME)( \\\n           typename internal::plain_constant_type<Derived,PromotedT>::type(matrix.derived().rows(), matrix.derived().cols(), internal::scalar_constant_op<PromotedT>(scalar)), matrix.derived()); \\\n  }\n\n#define EIGEN_MAKE_SCALAR_BINARY_OP(METHOD,OPNAME) \\\n  EIGEN_MAKE_SCALAR_BINARY_OP_ONTHELEFT(METHOD,OPNAME) \\\n  EIGEN_MAKE_SCALAR_BINARY_OP_ONTHERIGHT(METHOD,OPNAME)\n\n\n#ifdef EIGEN_EXCEPTIONS\n#  define EIGEN_THROW_X(X) throw X\n#  define EIGEN_THROW throw\n#  define EIGEN_TRY try\n#  define EIGEN_CATCH(X) catch (X)\n#else\n#  ifdef __CUDA_ARCH__\n#    define EIGEN_THROW_X(X) asm(\"trap;\")\n#    define EIGEN_THROW asm(\"trap;\")\n#  else\n#    define EIGEN_THROW_X(X) std::abort()\n#    define EIGEN_THROW std::abort()\n#  endif\n#  define EIGEN_TRY if (true)\n#  define EIGEN_CATCH(X) else\n#endif\n\n\n#if EIGEN_HAS_CXX11_NOEXCEPT\n#   define EIGEN_INCLUDE_TYPE_TRAITS\n#   define EIGEN_NOEXCEPT noexcept\n#   define EIGEN_NOEXCEPT_IF(x) noexcept(x)\n#   define EIGEN_NO_THROW noexcept(true)\n#   define EIGEN_EXCEPTION_SPEC(X) noexcept(false)\n#else\n#   define EIGEN_NOEXCEPT\n#   define EIGEN_NOEXCEPT_IF(x)\n#   define EIGEN_NO_THROW throw()\n#   define EIGEN_EXCEPTION_SPEC(X) throw(X)\n#endif\n\n#endif // EIGEN_MACROS_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/util/Memory.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2015 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2008-2009 Benoit Jacob <jacob.benoit.1@gmail.com>\n// Copyright (C) 2009 Kenneth Riddile <kfriddile@yahoo.com>\n// Copyright (C) 2010 Hauke Heibel <hauke.heibel@gmail.com>\n// Copyright (C) 2010 Thomas Capricelli <orzel@freehackers.org>\n// Copyright (C) 2013 Pavel Holoborodko <pavel@holoborodko.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n\n/*****************************************************************************\n*** Platform checks for aligned malloc functions                           ***\n*****************************************************************************/\n\n#ifndef EIGEN_MEMORY_H\n#define EIGEN_MEMORY_H\n\n#ifndef EIGEN_MALLOC_ALREADY_ALIGNED\n\n// Try to determine automatically if malloc is already aligned.\n\n// On 64-bit systems, glibc's malloc returns 16-byte-aligned pointers, see:\n//   http://www.gnu.org/s/libc/manual/html_node/Aligned-Memory-Blocks.html\n// This is true at least since glibc 2.8.\n// This leaves the question how to detect 64-bit. According to this document,\n//   http://gcc.fyxm.net/summit/2003/Porting%20to%2064%20bit.pdf\n// page 114, \"[The] LP64 model [...] is used by all 64-bit UNIX ports\" so it's indeed\n// quite safe, at least within the context of glibc, to equate 64-bit with LP64.\n#if defined(__GLIBC__) && ((__GLIBC__>=2 && __GLIBC_MINOR__ >= 8) || __GLIBC__>2) \\\n && defined(__LP64__) && ! defined( __SANITIZE_ADDRESS__ ) && (EIGEN_DEFAULT_ALIGN_BYTES == 16)\n  #define EIGEN_GLIBC_MALLOC_ALREADY_ALIGNED 1\n#else\n  #define EIGEN_GLIBC_MALLOC_ALREADY_ALIGNED 0\n#endif\n\n// FreeBSD 6 seems to have 16-byte aligned malloc\n//   See http://svn.freebsd.org/viewvc/base/stable/6/lib/libc/stdlib/malloc.c?view=markup\n// FreeBSD 7 seems to have 16-byte aligned malloc except on ARM and MIPS architectures\n//   See http://svn.freebsd.org/viewvc/base/stable/7/lib/libc/stdlib/malloc.c?view=markup\n#if defined(__FreeBSD__) && !(EIGEN_ARCH_ARM || EIGEN_ARCH_MIPS) && (EIGEN_DEFAULT_ALIGN_BYTES == 16)\n  #define EIGEN_FREEBSD_MALLOC_ALREADY_ALIGNED 1\n#else\n  #define EIGEN_FREEBSD_MALLOC_ALREADY_ALIGNED 0\n#endif\n\n#if (EIGEN_OS_MAC && (EIGEN_DEFAULT_ALIGN_BYTES == 16))     \\\n || (EIGEN_OS_WIN64 && (EIGEN_DEFAULT_ALIGN_BYTES == 16))   \\\n || EIGEN_GLIBC_MALLOC_ALREADY_ALIGNED              \\\n || EIGEN_FREEBSD_MALLOC_ALREADY_ALIGNED\n  #define EIGEN_MALLOC_ALREADY_ALIGNED 1\n#else\n  #define EIGEN_MALLOC_ALREADY_ALIGNED 0\n#endif\n\n#endif\n\nnamespace Eigen {\n\nnamespace internal {\n\nEIGEN_DEVICE_FUNC \ninline void throw_std_bad_alloc()\n{\n  #ifdef EIGEN_EXCEPTIONS\n    throw std::bad_alloc();\n  #else\n    std::size_t huge = static_cast<std::size_t>(-1);\n    new int[huge];\n  #endif\n}\n\n/*****************************************************************************\n*** Implementation of handmade aligned functions                           ***\n*****************************************************************************/\n\n/* ----- Hand made implementations of aligned malloc/free and realloc ----- */\n\n/** \\internal Like malloc, but the returned pointer is guaranteed to be 16-byte aligned.\n  * Fast, but wastes 16 additional bytes of memory. Does not throw any exception.\n  */\ninline void* handmade_aligned_malloc(std::size_t size)\n{\n  void *original = std::malloc(size+EIGEN_DEFAULT_ALIGN_BYTES);\n  if (original == 0) return 0;\n  void *aligned = reinterpret_cast<void*>((reinterpret_cast<std::size_t>(original) & ~(std::size_t(EIGEN_DEFAULT_ALIGN_BYTES-1))) + EIGEN_DEFAULT_ALIGN_BYTES);\n  *(reinterpret_cast<void**>(aligned) - 1) = original;\n  return aligned;\n}\n\n/** \\internal Frees memory allocated with handmade_aligned_malloc */\ninline void handmade_aligned_free(void *ptr)\n{\n  if (ptr) std::free(*(reinterpret_cast<void**>(ptr) - 1));\n}\n\n/** \\internal\n  * \\brief Reallocates aligned memory.\n  * Since we know that our handmade version is based on std::malloc\n  * we can use std::realloc to implement efficient reallocation.\n  */\ninline void* handmade_aligned_realloc(void* ptr, std::size_t size, std::size_t = 0)\n{\n  if (ptr == 0) return handmade_aligned_malloc(size);\n  void *original = *(reinterpret_cast<void**>(ptr) - 1);\n  std::ptrdiff_t previous_offset = static_cast<char *>(ptr)-static_cast<char *>(original);\n  original = std::realloc(original,size+EIGEN_DEFAULT_ALIGN_BYTES);\n  if (original == 0) return 0;\n  void *aligned = reinterpret_cast<void*>((reinterpret_cast<std::size_t>(original) & ~(std::size_t(EIGEN_DEFAULT_ALIGN_BYTES-1))) + EIGEN_DEFAULT_ALIGN_BYTES);\n  void *previous_aligned = static_cast<char *>(original)+previous_offset;\n  if(aligned!=previous_aligned)\n    std::memmove(aligned, previous_aligned, size);\n  \n  *(reinterpret_cast<void**>(aligned) - 1) = original;\n  return aligned;\n}\n\n/*****************************************************************************\n*** Implementation of portable aligned versions of malloc/free/realloc     ***\n*****************************************************************************/\n\n#ifdef EIGEN_NO_MALLOC\nEIGEN_DEVICE_FUNC inline void check_that_malloc_is_allowed()\n{\n  eigen_assert(false && \"heap allocation is forbidden (EIGEN_NO_MALLOC is defined)\");\n}\n#elif defined EIGEN_RUNTIME_NO_MALLOC\nEIGEN_DEVICE_FUNC inline bool is_malloc_allowed_impl(bool update, bool new_value = false)\n{\n  static bool value = true;\n  if (update == 1)\n    value = new_value;\n  return value;\n}\nEIGEN_DEVICE_FUNC inline bool is_malloc_allowed() { return is_malloc_allowed_impl(false); }\nEIGEN_DEVICE_FUNC inline bool set_is_malloc_allowed(bool new_value) { return is_malloc_allowed_impl(true, new_value); }\nEIGEN_DEVICE_FUNC inline void check_that_malloc_is_allowed()\n{\n  eigen_assert(is_malloc_allowed() && \"heap allocation is forbidden (EIGEN_RUNTIME_NO_MALLOC is defined and g_is_malloc_allowed is false)\");\n}\n#else \nEIGEN_DEVICE_FUNC inline void check_that_malloc_is_allowed()\n{}\n#endif\n\n/** \\internal Allocates \\a size bytes. The returned pointer is guaranteed to have 16 or 32 bytes alignment depending on the requirements.\n  * On allocation error, the returned pointer is null, and std::bad_alloc is thrown.\n  */\nEIGEN_DEVICE_FUNC inline void* aligned_malloc(size_t size)\n{\n  check_that_malloc_is_allowed();\n\n  void *result;\n  #if (EIGEN_DEFAULT_ALIGN_BYTES==0) || EIGEN_MALLOC_ALREADY_ALIGNED\n    result = std::malloc(size);\n    #if EIGEN_DEFAULT_ALIGN_BYTES==16\n    eigen_assert((size<16 || (std::size_t(result)%16)==0) && \"System's malloc returned an unaligned pointer. Compile with EIGEN_MALLOC_ALREADY_ALIGNED=0 to fallback to handmade alignd memory allocator.\");\n    #endif\n  #else\n    result = handmade_aligned_malloc(size);\n  #endif\n\n  if(!result && size)\n    throw_std_bad_alloc();\n\n  return result;\n}\n\n/** \\internal Frees memory allocated with aligned_malloc. */\nEIGEN_DEVICE_FUNC inline void aligned_free(void *ptr)\n{\n  #if (EIGEN_DEFAULT_ALIGN_BYTES==0) || EIGEN_MALLOC_ALREADY_ALIGNED\n    std::free(ptr);\n  #else\n    handmade_aligned_free(ptr);\n  #endif\n}\n\n/**\n  * \\internal\n  * \\brief Reallocates an aligned block of memory.\n  * \\throws std::bad_alloc on allocation failure\n  */\ninline void* aligned_realloc(void *ptr, size_t new_size, size_t old_size)\n{\n  EIGEN_UNUSED_VARIABLE(old_size);\n\n  void *result;\n#if (EIGEN_DEFAULT_ALIGN_BYTES==0) || EIGEN_MALLOC_ALREADY_ALIGNED\n  result = std::realloc(ptr,new_size);\n#else\n  result = handmade_aligned_realloc(ptr,new_size,old_size);\n#endif\n\n  if (!result && new_size)\n    throw_std_bad_alloc();\n\n  return result;\n}\n\n/*****************************************************************************\n*** Implementation of conditionally aligned functions                      ***\n*****************************************************************************/\n\n/** \\internal Allocates \\a size bytes. If Align is true, then the returned ptr is 16-byte-aligned.\n  * On allocation error, the returned pointer is null, and a std::bad_alloc is thrown.\n  */\ntemplate<bool Align> EIGEN_DEVICE_FUNC inline void* conditional_aligned_malloc(size_t size)\n{\n  return aligned_malloc(size);\n}\n\ntemplate<> EIGEN_DEVICE_FUNC inline void* conditional_aligned_malloc<false>(size_t size)\n{\n  check_that_malloc_is_allowed();\n\n  void *result = std::malloc(size);\n  if(!result && size)\n    throw_std_bad_alloc();\n  return result;\n}\n\n/** \\internal Frees memory allocated with conditional_aligned_malloc */\ntemplate<bool Align> EIGEN_DEVICE_FUNC inline void conditional_aligned_free(void *ptr)\n{\n  aligned_free(ptr);\n}\n\ntemplate<> EIGEN_DEVICE_FUNC inline void conditional_aligned_free<false>(void *ptr)\n{\n  std::free(ptr);\n}\n\ntemplate<bool Align> inline void* conditional_aligned_realloc(void* ptr, size_t new_size, size_t old_size)\n{\n  return aligned_realloc(ptr, new_size, old_size);\n}\n\ntemplate<> inline void* conditional_aligned_realloc<false>(void* ptr, size_t new_size, size_t)\n{\n  return std::realloc(ptr, new_size);\n}\n\n/*****************************************************************************\n*** Construction/destruction of array elements                             ***\n*****************************************************************************/\n\n/** \\internal Destructs the elements of an array.\n  * The \\a size parameters tells on how many objects to call the destructor of T.\n  */\ntemplate<typename T> EIGEN_DEVICE_FUNC inline void destruct_elements_of_array(T *ptr, size_t size)\n{\n  // always destruct an array starting from the end.\n  if(ptr)\n    while(size) ptr[--size].~T();\n}\n\n/** \\internal Constructs the elements of an array.\n  * The \\a size parameter tells on how many objects to call the constructor of T.\n  */\ntemplate<typename T> EIGEN_DEVICE_FUNC inline T* construct_elements_of_array(T *ptr, size_t size)\n{\n  size_t i;\n  EIGEN_TRY\n  {\n      for (i = 0; i < size; ++i) ::new (ptr + i) T;\n      return ptr;\n  }\n  EIGEN_CATCH(...)\n  {\n    destruct_elements_of_array(ptr, i);\n    EIGEN_THROW;\n  }\n  return NULL;\n}\n\n/*****************************************************************************\n*** Implementation of aligned new/delete-like functions                    ***\n*****************************************************************************/\n\ntemplate<typename T>\nEIGEN_DEVICE_FUNC EIGEN_ALWAYS_INLINE void check_size_for_overflow(size_t size)\n{\n  if(size > size_t(-1) / sizeof(T))\n    throw_std_bad_alloc();\n}\n\n/** \\internal Allocates \\a size objects of type T. The returned pointer is guaranteed to have 16 bytes alignment.\n  * On allocation error, the returned pointer is undefined, but a std::bad_alloc is thrown.\n  * The default constructor of T is called.\n  */\ntemplate<typename T> EIGEN_DEVICE_FUNC inline T* aligned_new(size_t size)\n{\n  check_size_for_overflow<T>(size);\n  T *result = reinterpret_cast<T*>(aligned_malloc(sizeof(T)*size));\n  EIGEN_TRY\n  {\n    return construct_elements_of_array(result, size);\n  }\n  EIGEN_CATCH(...)\n  {\n    aligned_free(result);\n    EIGEN_THROW;\n  }\n  return result;\n}\n\ntemplate<typename T, bool Align> EIGEN_DEVICE_FUNC inline T* conditional_aligned_new(size_t size)\n{\n  check_size_for_overflow<T>(size);\n  T *result = reinterpret_cast<T*>(conditional_aligned_malloc<Align>(sizeof(T)*size));\n  EIGEN_TRY\n  {\n    return construct_elements_of_array(result, size);\n  }\n  EIGEN_CATCH(...)\n  {\n    conditional_aligned_free<Align>(result);\n    EIGEN_THROW;\n  }\n  return result;\n}\n\n/** \\internal Deletes objects constructed with aligned_new\n  * The \\a size parameters tells on how many objects to call the destructor of T.\n  */\ntemplate<typename T> EIGEN_DEVICE_FUNC inline void aligned_delete(T *ptr, size_t size)\n{\n  destruct_elements_of_array<T>(ptr, size);\n  aligned_free(ptr);\n}\n\n/** \\internal Deletes objects constructed with conditional_aligned_new\n  * The \\a size parameters tells on how many objects to call the destructor of T.\n  */\ntemplate<typename T, bool Align> EIGEN_DEVICE_FUNC inline void conditional_aligned_delete(T *ptr, size_t size)\n{\n  destruct_elements_of_array<T>(ptr, size);\n  conditional_aligned_free<Align>(ptr);\n}\n\ntemplate<typename T, bool Align> EIGEN_DEVICE_FUNC inline T* conditional_aligned_realloc_new(T* pts, size_t new_size, size_t old_size)\n{\n  check_size_for_overflow<T>(new_size);\n  check_size_for_overflow<T>(old_size);\n  if(new_size < old_size)\n    destruct_elements_of_array(pts+new_size, old_size-new_size);\n  T *result = reinterpret_cast<T*>(conditional_aligned_realloc<Align>(reinterpret_cast<void*>(pts), sizeof(T)*new_size, sizeof(T)*old_size));\n  if(new_size > old_size)\n  {\n    EIGEN_TRY\n    {\n      construct_elements_of_array(result+old_size, new_size-old_size);\n    }\n    EIGEN_CATCH(...)\n    {\n      conditional_aligned_free<Align>(result);\n      EIGEN_THROW;\n    }\n  }\n  return result;\n}\n\n\ntemplate<typename T, bool Align> EIGEN_DEVICE_FUNC inline T* conditional_aligned_new_auto(size_t size)\n{\n  if(size==0)\n    return 0; // short-cut. Also fixes Bug 884\n  check_size_for_overflow<T>(size);\n  T *result = reinterpret_cast<T*>(conditional_aligned_malloc<Align>(sizeof(T)*size));\n  if(NumTraits<T>::RequireInitialization)\n  {\n    EIGEN_TRY\n    {\n      construct_elements_of_array(result, size);\n    }\n    EIGEN_CATCH(...)\n    {\n      conditional_aligned_free<Align>(result);\n      EIGEN_THROW;\n    }\n  }\n  return result;\n}\n\ntemplate<typename T, bool Align> inline T* conditional_aligned_realloc_new_auto(T* pts, size_t new_size, size_t old_size)\n{\n  check_size_for_overflow<T>(new_size);\n  check_size_for_overflow<T>(old_size);\n  if(NumTraits<T>::RequireInitialization && (new_size < old_size))\n    destruct_elements_of_array(pts+new_size, old_size-new_size);\n  T *result = reinterpret_cast<T*>(conditional_aligned_realloc<Align>(reinterpret_cast<void*>(pts), sizeof(T)*new_size, sizeof(T)*old_size));\n  if(NumTraits<T>::RequireInitialization && (new_size > old_size))\n  {\n    EIGEN_TRY\n    {\n      construct_elements_of_array(result+old_size, new_size-old_size);\n    }\n    EIGEN_CATCH(...)\n    {\n      conditional_aligned_free<Align>(result);\n      EIGEN_THROW;\n    }\n  }\n  return result;\n}\n\ntemplate<typename T, bool Align> EIGEN_DEVICE_FUNC inline void conditional_aligned_delete_auto(T *ptr, size_t size)\n{\n  if(NumTraits<T>::RequireInitialization)\n    destruct_elements_of_array<T>(ptr, size);\n  conditional_aligned_free<Align>(ptr);\n}\n\n/****************************************************************************/\n\n/** \\internal Returns the index of the first element of the array that is well aligned with respect to the requested \\a Alignment.\n  *\n  * \\tparam Alignment requested alignment in Bytes.\n  * \\param array the address of the start of the array\n  * \\param size the size of the array\n  *\n  * \\note If no element of the array is well aligned or the requested alignment is not a multiple of a scalar,\n  * the size of the array is returned. For example with SSE, the requested alignment is typically 16-bytes. If\n  * packet size for the given scalar type is 1, then everything is considered well-aligned.\n  *\n  * \\note Otherwise, if the Alignment is larger that the scalar size, we rely on the assumptions that sizeof(Scalar) is a\n  * power of 2. On the other hand, we do not assume that the array address is a multiple of sizeof(Scalar), as that fails for\n  * example with Scalar=double on certain 32-bit platforms, see bug #79.\n  *\n  * There is also the variant first_aligned(const MatrixBase&) defined in DenseCoeffsBase.h.\n  * \\sa first_default_aligned()\n  */\ntemplate<int Alignment, typename Scalar, typename Index>\nEIGEN_DEVICE_FUNC inline Index first_aligned(const Scalar* array, Index size)\n{\n  const Index ScalarSize = sizeof(Scalar);\n  const Index AlignmentSize = Alignment / ScalarSize;\n  const Index AlignmentMask = AlignmentSize-1;\n\n  if(AlignmentSize<=1)\n  {\n    // Either the requested alignment if smaller than a scalar, or it exactly match a 1 scalar\n    // so that all elements of the array have the same alignment.\n    return 0;\n  }\n  else if( (UIntPtr(array) & (sizeof(Scalar)-1)) || (Alignment%ScalarSize)!=0)\n  {\n    // The array is not aligned to the size of a single scalar, or the requested alignment is not a multiple of the scalar size.\n    // Consequently, no element of the array is well aligned.\n    return size;\n  }\n  else\n  {\n    Index first = (AlignmentSize - (Index((UIntPtr(array)/sizeof(Scalar))) & AlignmentMask)) & AlignmentMask;\n    return (first < size) ? first : size;\n  }\n}\n\n/** \\internal Returns the index of the first element of the array that is well aligned with respect the largest packet requirement.\n   * \\sa first_aligned(Scalar*,Index) and first_default_aligned(DenseBase<Derived>) */\ntemplate<typename Scalar, typename Index>\nEIGEN_DEVICE_FUNC inline Index first_default_aligned(const Scalar* array, Index size)\n{\n  typedef typename packet_traits<Scalar>::type DefaultPacketType;\n  return first_aligned<unpacket_traits<DefaultPacketType>::alignment>(array, size);\n}\n\n/** \\internal Returns the smallest integer multiple of \\a base and greater or equal to \\a size\n  */ \ntemplate<typename Index> \ninline Index first_multiple(Index size, Index base)\n{\n  return ((size+base-1)/base)*base;\n}\n\n// std::copy is much slower than memcpy, so let's introduce a smart_copy which\n// use memcpy on trivial types, i.e., on types that does not require an initialization ctor.\ntemplate<typename T, bool UseMemcpy> struct smart_copy_helper;\n\ntemplate<typename T> EIGEN_DEVICE_FUNC void smart_copy(const T* start, const T* end, T* target)\n{\n  smart_copy_helper<T,!NumTraits<T>::RequireInitialization>::run(start, end, target);\n}\n\ntemplate<typename T> struct smart_copy_helper<T,true> {\n  EIGEN_DEVICE_FUNC static inline void run(const T* start, const T* end, T* target)\n  {\n    IntPtr size = IntPtr(end)-IntPtr(start);\n    if(size==0) return;\n    eigen_internal_assert(start!=0 && end!=0 && target!=0);\n    memcpy(target, start, size);\n  }\n};\n\ntemplate<typename T> struct smart_copy_helper<T,false> {\n  EIGEN_DEVICE_FUNC static inline void run(const T* start, const T* end, T* target)\n  { std::copy(start, end, target); }\n};\n\n// intelligent memmove. falls back to std::memmove for POD types, uses std::copy otherwise. \ntemplate<typename T, bool UseMemmove> struct smart_memmove_helper;\n\ntemplate<typename T> void smart_memmove(const T* start, const T* end, T* target)\n{\n  smart_memmove_helper<T,!NumTraits<T>::RequireInitialization>::run(start, end, target);\n}\n\ntemplate<typename T> struct smart_memmove_helper<T,true> {\n  static inline void run(const T* start, const T* end, T* target)\n  {\n    IntPtr size = IntPtr(end)-IntPtr(start);\n    if(size==0) return;\n    eigen_internal_assert(start!=0 && end!=0 && target!=0);\n    std::memmove(target, start, size);\n  }\n};\n\ntemplate<typename T> struct smart_memmove_helper<T,false> {\n  static inline void run(const T* start, const T* end, T* target)\n  { \n    if (UIntPtr(target) < UIntPtr(start))\n    {\n      std::copy(start, end, target);\n    }\n    else                                 \n    {\n      std::ptrdiff_t count = (std::ptrdiff_t(end)-std::ptrdiff_t(start)) / sizeof(T);\n      std::copy_backward(start, end, target + count); \n    }\n  }\n};\n\n\n/*****************************************************************************\n*** Implementation of runtime stack allocation (falling back to malloc)    ***\n*****************************************************************************/\n\n// you can overwrite Eigen's default behavior regarding alloca by defining EIGEN_ALLOCA\n// to the appropriate stack allocation function\n#ifndef EIGEN_ALLOCA\n  #if EIGEN_OS_LINUX || EIGEN_OS_MAC || (defined alloca)\n    #define EIGEN_ALLOCA alloca\n  #elif EIGEN_COMP_MSVC\n    #define EIGEN_ALLOCA _alloca\n  #endif\n#endif\n\n// This helper class construct the allocated memory, and takes care of destructing and freeing the handled data\n// at destruction time. In practice this helper class is mainly useful to avoid memory leak in case of exceptions.\ntemplate<typename T> class aligned_stack_memory_handler : noncopyable\n{\n  public:\n    /* Creates a stack_memory_handler responsible for the buffer \\a ptr of size \\a size.\n     * Note that \\a ptr can be 0 regardless of the other parameters.\n     * This constructor takes care of constructing/initializing the elements of the buffer if required by the scalar type T (see NumTraits<T>::RequireInitialization).\n     * In this case, the buffer elements will also be destructed when this handler will be destructed.\n     * Finally, if \\a dealloc is true, then the pointer \\a ptr is freed.\n     **/\n    aligned_stack_memory_handler(T* ptr, size_t size, bool dealloc)\n      : m_ptr(ptr), m_size(size), m_deallocate(dealloc)\n    {\n      if(NumTraits<T>::RequireInitialization && m_ptr)\n        Eigen::internal::construct_elements_of_array(m_ptr, size);\n    }\n    ~aligned_stack_memory_handler()\n    {\n      if(NumTraits<T>::RequireInitialization && m_ptr)\n        Eigen::internal::destruct_elements_of_array<T>(m_ptr, m_size);\n      if(m_deallocate)\n        Eigen::internal::aligned_free(m_ptr);\n    }\n  protected:\n    T* m_ptr;\n    size_t m_size;\n    bool m_deallocate;\n};\n\ntemplate<typename T> class scoped_array : noncopyable\n{\n  T* m_ptr;\npublic:\n  explicit scoped_array(std::ptrdiff_t size)\n  {\n    m_ptr = new T[size];\n  }\n  ~scoped_array()\n  {\n    delete[] m_ptr;\n  }\n  T& operator[](std::ptrdiff_t i) { return m_ptr[i]; }\n  const T& operator[](std::ptrdiff_t i) const { return m_ptr[i]; }\n  T* &ptr() { return m_ptr; }\n  const T* ptr() const { return m_ptr; }\n  operator const T*() const { return m_ptr; }\n};\n\ntemplate<typename T> void swap(scoped_array<T> &a,scoped_array<T> &b)\n{\n  std::swap(a.ptr(),b.ptr());\n}\n    \n} // end namespace internal\n\n/** \\internal\n  * Declares, allocates and construct an aligned buffer named NAME of SIZE elements of type TYPE on the stack\n  * if SIZE is smaller than EIGEN_STACK_ALLOCATION_LIMIT, and if stack allocation is supported by the platform\n  * (currently, this is Linux and Visual Studio only). Otherwise the memory is allocated on the heap.\n  * The allocated buffer is automatically deleted when exiting the scope of this declaration.\n  * If BUFFER is non null, then the declared variable is simply an alias for BUFFER, and no allocation/deletion occurs.\n  * Here is an example:\n  * \\code\n  * {\n  *   ei_declare_aligned_stack_constructed_variable(float,data,size,0);\n  *   // use data[0] to data[size-1]\n  * }\n  * \\endcode\n  * The underlying stack allocation function can controlled with the EIGEN_ALLOCA preprocessor token.\n  */\n#ifdef EIGEN_ALLOCA\n  \n  #if EIGEN_DEFAULT_ALIGN_BYTES>0\n    // We always manually re-align the result of EIGEN_ALLOCA.\n    // If alloca is already aligned, the compiler should be smart enough to optimize away the re-alignment.\n    #define EIGEN_ALIGNED_ALLOCA(SIZE) reinterpret_cast<void*>((internal::UIntPtr(EIGEN_ALLOCA(SIZE+EIGEN_DEFAULT_ALIGN_BYTES-1)) + EIGEN_DEFAULT_ALIGN_BYTES-1) & ~(std::size_t(EIGEN_DEFAULT_ALIGN_BYTES-1)))\n  #else\n    #define EIGEN_ALIGNED_ALLOCA(SIZE) EIGEN_ALLOCA(SIZE)\n  #endif\n\n  #define ei_declare_aligned_stack_constructed_variable(TYPE,NAME,SIZE,BUFFER) \\\n    Eigen::internal::check_size_for_overflow<TYPE>(SIZE); \\\n    TYPE* NAME = (BUFFER)!=0 ? (BUFFER) \\\n               : reinterpret_cast<TYPE*>( \\\n                      (sizeof(TYPE)*SIZE<=EIGEN_STACK_ALLOCATION_LIMIT) ? EIGEN_ALIGNED_ALLOCA(sizeof(TYPE)*SIZE) \\\n                    : Eigen::internal::aligned_malloc(sizeof(TYPE)*SIZE) );  \\\n    Eigen::internal::aligned_stack_memory_handler<TYPE> EIGEN_CAT(NAME,_stack_memory_destructor)((BUFFER)==0 ? NAME : 0,SIZE,sizeof(TYPE)*SIZE>EIGEN_STACK_ALLOCATION_LIMIT)\n\n#else\n\n  #define ei_declare_aligned_stack_constructed_variable(TYPE,NAME,SIZE,BUFFER) \\\n    Eigen::internal::check_size_for_overflow<TYPE>(SIZE); \\\n    TYPE* NAME = (BUFFER)!=0 ? BUFFER : reinterpret_cast<TYPE*>(Eigen::internal::aligned_malloc(sizeof(TYPE)*SIZE));    \\\n    Eigen::internal::aligned_stack_memory_handler<TYPE> EIGEN_CAT(NAME,_stack_memory_destructor)((BUFFER)==0 ? NAME : 0,SIZE,true)\n    \n#endif\n\n\n/*****************************************************************************\n*** Implementation of EIGEN_MAKE_ALIGNED_OPERATOR_NEW [_IF]                ***\n*****************************************************************************/\n\n#if EIGEN_MAX_ALIGN_BYTES!=0\n  #define EIGEN_MAKE_ALIGNED_OPERATOR_NEW_NOTHROW(NeedsToAlign) \\\n      void* operator new(size_t size, const std::nothrow_t&) EIGEN_NO_THROW { \\\n        EIGEN_TRY { return Eigen::internal::conditional_aligned_malloc<NeedsToAlign>(size); } \\\n        EIGEN_CATCH (...) { return 0; } \\\n      }\n  #define EIGEN_MAKE_ALIGNED_OPERATOR_NEW_IF(NeedsToAlign) \\\n      void *operator new(size_t size) { \\\n        return Eigen::internal::conditional_aligned_malloc<NeedsToAlign>(size); \\\n      } \\\n      void *operator new[](size_t size) { \\\n        return Eigen::internal::conditional_aligned_malloc<NeedsToAlign>(size); \\\n      } \\\n      void operator delete(void * ptr) EIGEN_NO_THROW { Eigen::internal::conditional_aligned_free<NeedsToAlign>(ptr); } \\\n      void operator delete[](void * ptr) EIGEN_NO_THROW { Eigen::internal::conditional_aligned_free<NeedsToAlign>(ptr); } \\\n      void operator delete(void * ptr, std::size_t /* sz */) EIGEN_NO_THROW { Eigen::internal::conditional_aligned_free<NeedsToAlign>(ptr); } \\\n      void operator delete[](void * ptr, std::size_t /* sz */) EIGEN_NO_THROW { Eigen::internal::conditional_aligned_free<NeedsToAlign>(ptr); } \\\n      /* in-place new and delete. since (at least afaik) there is no actual   */ \\\n      /* memory allocated we can safely let the default implementation handle */ \\\n      /* this particular case. */ \\\n      static void *operator new(size_t size, void *ptr) { return ::operator new(size,ptr); } \\\n      static void *operator new[](size_t size, void* ptr) { return ::operator new[](size,ptr); } \\\n      void operator delete(void * memory, void *ptr) EIGEN_NO_THROW { return ::operator delete(memory,ptr); } \\\n      void operator delete[](void * memory, void *ptr) EIGEN_NO_THROW { return ::operator delete[](memory,ptr); } \\\n      /* nothrow-new (returns zero instead of std::bad_alloc) */ \\\n      EIGEN_MAKE_ALIGNED_OPERATOR_NEW_NOTHROW(NeedsToAlign) \\\n      void operator delete(void *ptr, const std::nothrow_t&) EIGEN_NO_THROW { \\\n        Eigen::internal::conditional_aligned_free<NeedsToAlign>(ptr); \\\n      } \\\n      typedef void eigen_aligned_operator_new_marker_type;\n#else\n  #define EIGEN_MAKE_ALIGNED_OPERATOR_NEW_IF(NeedsToAlign)\n#endif\n\n#define EIGEN_MAKE_ALIGNED_OPERATOR_NEW EIGEN_MAKE_ALIGNED_OPERATOR_NEW_IF(true)\n#define EIGEN_MAKE_ALIGNED_OPERATOR_NEW_IF_VECTORIZABLE_FIXED_SIZE(Scalar,Size) \\\n  EIGEN_MAKE_ALIGNED_OPERATOR_NEW_IF(bool(((Size)!=Eigen::Dynamic) && ((sizeof(Scalar)*(Size))%EIGEN_MAX_ALIGN_BYTES==0)))\n\n/****************************************************************************/\n\n/** \\class aligned_allocator\n* \\ingroup Core_Module\n*\n* \\brief STL compatible allocator to use with with 16 byte aligned types\n*\n* Example:\n* \\code\n* // Matrix4f requires 16 bytes alignment:\n* std::map< int, Matrix4f, std::less<int>, \n*           aligned_allocator<std::pair<const int, Matrix4f> > > my_map_mat4;\n* // Vector3f does not require 16 bytes alignment, no need to use Eigen's allocator:\n* std::map< int, Vector3f > my_map_vec3;\n* \\endcode\n*\n* \\sa \\blank \\ref TopicStlContainers.\n*/\ntemplate<class T>\nclass aligned_allocator : public std::allocator<T>\n{\npublic:\n  typedef size_t          size_type;\n  typedef std::ptrdiff_t  difference_type;\n  typedef T*              pointer;\n  typedef const T*        const_pointer;\n  typedef T&              reference;\n  typedef const T&        const_reference;\n  typedef T               value_type;\n\n  template<class U>\n  struct rebind\n  {\n    typedef aligned_allocator<U> other;\n  };\n\n  aligned_allocator() : std::allocator<T>() {}\n\n  aligned_allocator(const aligned_allocator& other) : std::allocator<T>(other) {}\n\n  template<class U>\n  aligned_allocator(const aligned_allocator<U>& other) : std::allocator<T>(other) {}\n\n  ~aligned_allocator() {}\n\n  pointer allocate(size_type num, const void* /*hint*/ = 0)\n  {\n    internal::check_size_for_overflow<T>(num);\n    return static_cast<pointer>( internal::aligned_malloc(num * sizeof(T)) );\n  }\n\n  void deallocate(pointer p, size_type /*num*/)\n  {\n    internal::aligned_free(p);\n  }\n};\n\n//---------- Cache sizes ----------\n\n#if !defined(EIGEN_NO_CPUID)\n#  if EIGEN_COMP_GNUC && EIGEN_ARCH_i386_OR_x86_64\n#    if defined(__PIC__) && EIGEN_ARCH_i386\n       // Case for x86 with PIC\n#      define EIGEN_CPUID(abcd,func,id) \\\n         __asm__ __volatile__ (\"xchgl %%ebx, %k1;cpuid; xchgl %%ebx,%k1\": \"=a\" (abcd[0]), \"=&r\" (abcd[1]), \"=c\" (abcd[2]), \"=d\" (abcd[3]) : \"a\" (func), \"c\" (id));\n#    elif defined(__PIC__) && EIGEN_ARCH_x86_64\n       // Case for x64 with PIC. In theory this is only a problem with recent gcc and with medium or large code model, not with the default small code model.\n       // However, we cannot detect which code model is used, and the xchg overhead is negligible anyway.\n#      define EIGEN_CPUID(abcd,func,id) \\\n        __asm__ __volatile__ (\"xchg{q}\\t{%%}rbx, %q1; cpuid; xchg{q}\\t{%%}rbx, %q1\": \"=a\" (abcd[0]), \"=&r\" (abcd[1]), \"=c\" (abcd[2]), \"=d\" (abcd[3]) : \"0\" (func), \"2\" (id));\n#    else\n       // Case for x86_64 or x86 w/o PIC\n#      define EIGEN_CPUID(abcd,func,id) \\\n         __asm__ __volatile__ (\"cpuid\": \"=a\" (abcd[0]), \"=b\" (abcd[1]), \"=c\" (abcd[2]), \"=d\" (abcd[3]) : \"0\" (func), \"2\" (id) );\n#    endif\n#  elif EIGEN_COMP_MSVC\n#    if (EIGEN_COMP_MSVC > 1500) && EIGEN_ARCH_i386_OR_x86_64\n#      define EIGEN_CPUID(abcd,func,id) __cpuidex((int*)abcd,func,id)\n#    endif\n#  endif\n#endif\n\nnamespace internal {\n\n#ifdef EIGEN_CPUID\n\ninline bool cpuid_is_vendor(int abcd[4], const int vendor[3])\n{\n  return abcd[1]==vendor[0] && abcd[3]==vendor[1] && abcd[2]==vendor[2];\n}\n\ninline void queryCacheSizes_intel_direct(int& l1, int& l2, int& l3)\n{\n  int abcd[4];\n  l1 = l2 = l3 = 0;\n  int cache_id = 0;\n  int cache_type = 0;\n  do {\n    abcd[0] = abcd[1] = abcd[2] = abcd[3] = 0;\n    EIGEN_CPUID(abcd,0x4,cache_id);\n    cache_type  = (abcd[0] & 0x0F) >> 0;\n    if(cache_type==1||cache_type==3) // data or unified cache\n    {\n      int cache_level = (abcd[0] & 0xE0) >> 5;  // A[7:5]\n      int ways        = (abcd[1] & 0xFFC00000) >> 22; // B[31:22]\n      int partitions  = (abcd[1] & 0x003FF000) >> 12; // B[21:12]\n      int line_size   = (abcd[1] & 0x00000FFF) >>  0; // B[11:0]\n      int sets        = (abcd[2]);                    // C[31:0]\n\n      int cache_size = (ways+1) * (partitions+1) * (line_size+1) * (sets+1);\n\n      switch(cache_level)\n      {\n        case 1: l1 = cache_size; break;\n        case 2: l2 = cache_size; break;\n        case 3: l3 = cache_size; break;\n        default: break;\n      }\n    }\n    cache_id++;\n  } while(cache_type>0 && cache_id<16);\n}\n\ninline void queryCacheSizes_intel_codes(int& l1, int& l2, int& l3)\n{\n  int abcd[4];\n  abcd[0] = abcd[1] = abcd[2] = abcd[3] = 0;\n  l1 = l2 = l3 = 0;\n  EIGEN_CPUID(abcd,0x00000002,0);\n  unsigned char * bytes = reinterpret_cast<unsigned char *>(abcd)+2;\n  bool check_for_p2_core2 = false;\n  for(int i=0; i<14; ++i)\n  {\n    switch(bytes[i])\n    {\n      case 0x0A: l1 = 8; break;   // 0Ah   data L1 cache, 8 KB, 2 ways, 32 byte lines\n      case 0x0C: l1 = 16; break;  // 0Ch   data L1 cache, 16 KB, 4 ways, 32 byte lines\n      case 0x0E: l1 = 24; break;  // 0Eh   data L1 cache, 24 KB, 6 ways, 64 byte lines\n      case 0x10: l1 = 16; break;  // 10h   data L1 cache, 16 KB, 4 ways, 32 byte lines (IA-64)\n      case 0x15: l1 = 16; break;  // 15h   code L1 cache, 16 KB, 4 ways, 32 byte lines (IA-64)\n      case 0x2C: l1 = 32; break;  // 2Ch   data L1 cache, 32 KB, 8 ways, 64 byte lines\n      case 0x30: l1 = 32; break;  // 30h   code L1 cache, 32 KB, 8 ways, 64 byte lines\n      case 0x60: l1 = 16; break;  // 60h   data L1 cache, 16 KB, 8 ways, 64 byte lines, sectored\n      case 0x66: l1 = 8; break;   // 66h   data L1 cache, 8 KB, 4 ways, 64 byte lines, sectored\n      case 0x67: l1 = 16; break;  // 67h   data L1 cache, 16 KB, 4 ways, 64 byte lines, sectored\n      case 0x68: l1 = 32; break;  // 68h   data L1 cache, 32 KB, 4 ways, 64 byte lines, sectored\n      case 0x1A: l2 = 96; break;   // code and data L2 cache, 96 KB, 6 ways, 64 byte lines (IA-64)\n      case 0x22: l3 = 512; break;   // code and data L3 cache, 512 KB, 4 ways (!), 64 byte lines, dual-sectored\n      case 0x23: l3 = 1024; break;   // code and data L3 cache, 1024 KB, 8 ways, 64 byte lines, dual-sectored\n      case 0x25: l3 = 2048; break;   // code and data L3 cache, 2048 KB, 8 ways, 64 byte lines, dual-sectored\n      case 0x29: l3 = 4096; break;   // code and data L3 cache, 4096 KB, 8 ways, 64 byte lines, dual-sectored\n      case 0x39: l2 = 128; break;   // code and data L2 cache, 128 KB, 4 ways, 64 byte lines, sectored\n      case 0x3A: l2 = 192; break;   // code and data L2 cache, 192 KB, 6 ways, 64 byte lines, sectored\n      case 0x3B: l2 = 128; break;   // code and data L2 cache, 128 KB, 2 ways, 64 byte lines, sectored\n      case 0x3C: l2 = 256; break;   // code and data L2 cache, 256 KB, 4 ways, 64 byte lines, sectored\n      case 0x3D: l2 = 384; break;   // code and data L2 cache, 384 KB, 6 ways, 64 byte lines, sectored\n      case 0x3E: l2 = 512; break;   // code and data L2 cache, 512 KB, 4 ways, 64 byte lines, sectored\n      case 0x40: l2 = 0; break;   // no integrated L2 cache (P6 core) or L3 cache (P4 core)\n      case 0x41: l2 = 128; break;   // code and data L2 cache, 128 KB, 4 ways, 32 byte lines\n      case 0x42: l2 = 256; break;   // code and data L2 cache, 256 KB, 4 ways, 32 byte lines\n      case 0x43: l2 = 512; break;   // code and data L2 cache, 512 KB, 4 ways, 32 byte lines\n      case 0x44: l2 = 1024; break;   // code and data L2 cache, 1024 KB, 4 ways, 32 byte lines\n      case 0x45: l2 = 2048; break;   // code and data L2 cache, 2048 KB, 4 ways, 32 byte lines\n      case 0x46: l3 = 4096; break;   // code and data L3 cache, 4096 KB, 4 ways, 64 byte lines\n      case 0x47: l3 = 8192; break;   // code and data L3 cache, 8192 KB, 8 ways, 64 byte lines\n      case 0x48: l2 = 3072; break;   // code and data L2 cache, 3072 KB, 12 ways, 64 byte lines\n      case 0x49: if(l2!=0) l3 = 4096; else {check_for_p2_core2=true; l3 = l2 = 4096;} break;// code and data L3 cache, 4096 KB, 16 ways, 64 byte lines (P4) or L2 for core2\n      case 0x4A: l3 = 6144; break;   // code and data L3 cache, 6144 KB, 12 ways, 64 byte lines\n      case 0x4B: l3 = 8192; break;   // code and data L3 cache, 8192 KB, 16 ways, 64 byte lines\n      case 0x4C: l3 = 12288; break;   // code and data L3 cache, 12288 KB, 12 ways, 64 byte lines\n      case 0x4D: l3 = 16384; break;   // code and data L3 cache, 16384 KB, 16 ways, 64 byte lines\n      case 0x4E: l2 = 6144; break;   // code and data L2 cache, 6144 KB, 24 ways, 64 byte lines\n      case 0x78: l2 = 1024; break;   // code and data L2 cache, 1024 KB, 4 ways, 64 byte lines\n      case 0x79: l2 = 128; break;   // code and data L2 cache, 128 KB, 8 ways, 64 byte lines, dual-sectored\n      case 0x7A: l2 = 256; break;   // code and data L2 cache, 256 KB, 8 ways, 64 byte lines, dual-sectored\n      case 0x7B: l2 = 512; break;   // code and data L2 cache, 512 KB, 8 ways, 64 byte lines, dual-sectored\n      case 0x7C: l2 = 1024; break;   // code and data L2 cache, 1024 KB, 8 ways, 64 byte lines, dual-sectored\n      case 0x7D: l2 = 2048; break;   // code and data L2 cache, 2048 KB, 8 ways, 64 byte lines\n      case 0x7E: l2 = 256; break;   // code and data L2 cache, 256 KB, 8 ways, 128 byte lines, sect. (IA-64)\n      case 0x7F: l2 = 512; break;   // code and data L2 cache, 512 KB, 2 ways, 64 byte lines\n      case 0x80: l2 = 512; break;   // code and data L2 cache, 512 KB, 8 ways, 64 byte lines\n      case 0x81: l2 = 128; break;   // code and data L2 cache, 128 KB, 8 ways, 32 byte lines\n      case 0x82: l2 = 256; break;   // code and data L2 cache, 256 KB, 8 ways, 32 byte lines\n      case 0x83: l2 = 512; break;   // code and data L2 cache, 512 KB, 8 ways, 32 byte lines\n      case 0x84: l2 = 1024; break;   // code and data L2 cache, 1024 KB, 8 ways, 32 byte lines\n      case 0x85: l2 = 2048; break;   // code and data L2 cache, 2048 KB, 8 ways, 32 byte lines\n      case 0x86: l2 = 512; break;   // code and data L2 cache, 512 KB, 4 ways, 64 byte lines\n      case 0x87: l2 = 1024; break;   // code and data L2 cache, 1024 KB, 8 ways, 64 byte lines\n      case 0x88: l3 = 2048; break;   // code and data L3 cache, 2048 KB, 4 ways, 64 byte lines (IA-64)\n      case 0x89: l3 = 4096; break;   // code and data L3 cache, 4096 KB, 4 ways, 64 byte lines (IA-64)\n      case 0x8A: l3 = 8192; break;   // code and data L3 cache, 8192 KB, 4 ways, 64 byte lines (IA-64)\n      case 0x8D: l3 = 3072; break;   // code and data L3 cache, 3072 KB, 12 ways, 128 byte lines (IA-64)\n\n      default: break;\n    }\n  }\n  if(check_for_p2_core2 && l2 == l3)\n    l3 = 0;\n  l1 *= 1024;\n  l2 *= 1024;\n  l3 *= 1024;\n}\n\ninline void queryCacheSizes_intel(int& l1, int& l2, int& l3, int max_std_funcs)\n{\n  if(max_std_funcs>=4)\n    queryCacheSizes_intel_direct(l1,l2,l3);\n  else\n    queryCacheSizes_intel_codes(l1,l2,l3);\n}\n\ninline void queryCacheSizes_amd(int& l1, int& l2, int& l3)\n{\n  int abcd[4];\n  abcd[0] = abcd[1] = abcd[2] = abcd[3] = 0;\n  EIGEN_CPUID(abcd,0x80000005,0);\n  l1 = (abcd[2] >> 24) * 1024; // C[31:24] = L1 size in KB\n  abcd[0] = abcd[1] = abcd[2] = abcd[3] = 0;\n  EIGEN_CPUID(abcd,0x80000006,0);\n  l2 = (abcd[2] >> 16) * 1024; // C[31;16] = l2 cache size in KB\n  l3 = ((abcd[3] & 0xFFFC000) >> 18) * 512 * 1024; // D[31;18] = l3 cache size in 512KB\n}\n#endif\n\n/** \\internal\n * Queries and returns the cache sizes in Bytes of the L1, L2, and L3 data caches respectively */\ninline void queryCacheSizes(int& l1, int& l2, int& l3)\n{\n  #ifdef EIGEN_CPUID\n  int abcd[4];\n  const int GenuineIntel[] = {0x756e6547, 0x49656e69, 0x6c65746e};\n  const int AuthenticAMD[] = {0x68747541, 0x69746e65, 0x444d4163};\n  const int AMDisbetter_[] = {0x69444d41, 0x74656273, 0x21726574}; // \"AMDisbetter!\"\n\n  // identify the CPU vendor\n  EIGEN_CPUID(abcd,0x0,0);\n  int max_std_funcs = abcd[1];\n  if(cpuid_is_vendor(abcd,GenuineIntel))\n    queryCacheSizes_intel(l1,l2,l3,max_std_funcs);\n  else if(cpuid_is_vendor(abcd,AuthenticAMD) || cpuid_is_vendor(abcd,AMDisbetter_))\n    queryCacheSizes_amd(l1,l2,l3);\n  else\n    // by default let's use Intel's API\n    queryCacheSizes_intel(l1,l2,l3,max_std_funcs);\n\n  // here is the list of other vendors:\n//   ||cpuid_is_vendor(abcd,\"VIA VIA VIA \")\n//   ||cpuid_is_vendor(abcd,\"CyrixInstead\")\n//   ||cpuid_is_vendor(abcd,\"CentaurHauls\")\n//   ||cpuid_is_vendor(abcd,\"GenuineTMx86\")\n//   ||cpuid_is_vendor(abcd,\"TransmetaCPU\")\n//   ||cpuid_is_vendor(abcd,\"RiseRiseRise\")\n//   ||cpuid_is_vendor(abcd,\"Geode by NSC\")\n//   ||cpuid_is_vendor(abcd,\"SiS SiS SiS \")\n//   ||cpuid_is_vendor(abcd,\"UMC UMC UMC \")\n//   ||cpuid_is_vendor(abcd,\"NexGenDriven\")\n  #else\n  l1 = l2 = l3 = -1;\n  #endif\n}\n\n/** \\internal\n * \\returns the size in Bytes of the L1 data cache */\ninline int queryL1CacheSize()\n{\n  int l1(-1), l2, l3;\n  queryCacheSizes(l1,l2,l3);\n  return l1;\n}\n\n/** \\internal\n * \\returns the size in Bytes of the L2 or L3 cache if this later is present */\ninline int queryTopLevelCacheSize()\n{\n  int l1, l2(-1), l3(-1);\n  queryCacheSizes(l1,l2,l3);\n  return (std::max)(l2,l3);\n}\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_MEMORY_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/util/Meta.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2015 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2006-2008 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_META_H\n#define EIGEN_META_H\n\n#if defined(__CUDA_ARCH__)\n#include <cfloat>\n#include <math_constants.h>\n#endif\n\n#if EIGEN_COMP_ICC>=1600 &&  __cplusplus >= 201103L\n#include <cstdint>\n#endif\n\nnamespace Eigen {\n\ntypedef EIGEN_DEFAULT_DENSE_INDEX_TYPE DenseIndex;\n\n/**\n * \\brief The Index type as used for the API.\n * \\details To change this, \\c \\#define the preprocessor symbol \\c EIGEN_DEFAULT_DENSE_INDEX_TYPE.\n * \\sa \\blank \\ref TopicPreprocessorDirectives, StorageIndex.\n */\n\ntypedef EIGEN_DEFAULT_DENSE_INDEX_TYPE Index;\n\nnamespace internal {\n\n/** \\internal\n  * \\file Meta.h\n  * This file contains generic metaprogramming classes which are not specifically related to Eigen.\n  * \\note In case you wonder, yes we're aware that Boost already provides all these features,\n  * we however don't want to add a dependency to Boost.\n  */\n\n// Only recent versions of ICC complain about using ptrdiff_t to hold pointers,\n// and older versions do not provide *intptr_t types.\n#if EIGEN_COMP_ICC>=1600 &&  __cplusplus >= 201103L\ntypedef std::intptr_t  IntPtr;\ntypedef std::uintptr_t UIntPtr;\n#else\ntypedef std::ptrdiff_t IntPtr;\ntypedef std::size_t UIntPtr;\n#endif\n\nstruct true_type {  enum { value = 1 }; };\nstruct false_type { enum { value = 0 }; };\n\ntemplate<bool Condition, typename Then, typename Else>\nstruct conditional { typedef Then type; };\n\ntemplate<typename Then, typename Else>\nstruct conditional <false, Then, Else> { typedef Else type; };\n\ntemplate<typename T, typename U> struct is_same { enum { value = 0 }; };\ntemplate<typename T> struct is_same<T,T> { enum { value = 1 }; };\n\ntemplate<typename T> struct remove_reference { typedef T type; };\ntemplate<typename T> struct remove_reference<T&> { typedef T type; };\n\ntemplate<typename T> struct remove_pointer { typedef T type; };\ntemplate<typename T> struct remove_pointer<T*> { typedef T type; };\ntemplate<typename T> struct remove_pointer<T*const> { typedef T type; };\n\ntemplate <class T> struct remove_const { typedef T type; };\ntemplate <class T> struct remove_const<const T> { typedef T type; };\ntemplate <class T> struct remove_const<const T[]> { typedef T type[]; };\ntemplate <class T, unsigned int Size> struct remove_const<const T[Size]> { typedef T type[Size]; };\n\ntemplate<typename T> struct remove_all { typedef T type; };\ntemplate<typename T> struct remove_all<const T>   { typedef typename remove_all<T>::type type; };\ntemplate<typename T> struct remove_all<T const&>  { typedef typename remove_all<T>::type type; };\ntemplate<typename T> struct remove_all<T&>        { typedef typename remove_all<T>::type type; };\ntemplate<typename T> struct remove_all<T const*>  { typedef typename remove_all<T>::type type; };\ntemplate<typename T> struct remove_all<T*>        { typedef typename remove_all<T>::type type; };\n\ntemplate<typename T> struct is_arithmetic      { enum { value = false }; };\ntemplate<> struct is_arithmetic<float>         { enum { value = true }; };\ntemplate<> struct is_arithmetic<double>        { enum { value = true }; };\ntemplate<> struct is_arithmetic<long double>   { enum { value = true }; };\ntemplate<> struct is_arithmetic<bool>          { enum { value = true }; };\ntemplate<> struct is_arithmetic<char>          { enum { value = true }; };\ntemplate<> struct is_arithmetic<signed char>   { enum { value = true }; };\ntemplate<> struct is_arithmetic<unsigned char> { enum { value = true }; };\ntemplate<> struct is_arithmetic<signed short>  { enum { value = true }; };\ntemplate<> struct is_arithmetic<unsigned short>{ enum { value = true }; };\ntemplate<> struct is_arithmetic<signed int>    { enum { value = true }; };\ntemplate<> struct is_arithmetic<unsigned int>  { enum { value = true }; };\ntemplate<> struct is_arithmetic<signed long>   { enum { value = true }; };\ntemplate<> struct is_arithmetic<unsigned long> { enum { value = true }; };\n\ntemplate<typename T> struct is_integral        { enum { value = false }; };\ntemplate<> struct is_integral<bool>            { enum { value = true }; };\ntemplate<> struct is_integral<char>            { enum { value = true }; };\ntemplate<> struct is_integral<signed char>     { enum { value = true }; };\ntemplate<> struct is_integral<unsigned char>   { enum { value = true }; };\ntemplate<> struct is_integral<signed short>    { enum { value = true }; };\ntemplate<> struct is_integral<unsigned short>  { enum { value = true }; };\ntemplate<> struct is_integral<signed int>      { enum { value = true }; };\ntemplate<> struct is_integral<unsigned int>    { enum { value = true }; };\ntemplate<> struct is_integral<signed long>     { enum { value = true }; };\ntemplate<> struct is_integral<unsigned long>   { enum { value = true }; };\n\ntemplate <typename T> struct add_const { typedef const T type; };\ntemplate <typename T> struct add_const<T&> { typedef T& type; };\n\ntemplate <typename T> struct is_const { enum { value = 0 }; };\ntemplate <typename T> struct is_const<T const> { enum { value = 1 }; };\n\ntemplate<typename T> struct add_const_on_value_type            { typedef const T type;  };\ntemplate<typename T> struct add_const_on_value_type<T&>        { typedef T const& type; };\ntemplate<typename T> struct add_const_on_value_type<T*>        { typedef T const* type; };\ntemplate<typename T> struct add_const_on_value_type<T* const>  { typedef T const* const type; };\ntemplate<typename T> struct add_const_on_value_type<T const* const>  { typedef T const* const type; };\n\n\ntemplate<typename From, typename To>\nstruct is_convertible_impl\n{\nprivate:\n  struct any_conversion\n  {\n    template <typename T> any_conversion(const volatile T&);\n    template <typename T> any_conversion(T&);\n  };\n  struct yes {int a[1];};\n  struct no  {int a[2];};\n\n  static yes test(const To&, int);\n  static no  test(any_conversion, ...);\n\npublic:\n  static From ms_from;\n#ifdef __INTEL_COMPILER\n  #pragma warning push\n  #pragma warning ( disable : 2259 )\n#endif\n  enum { value = sizeof(test(ms_from, 0))==sizeof(yes) };\n#ifdef __INTEL_COMPILER\n  #pragma warning pop\n#endif\n};\n\ntemplate<typename From, typename To>\nstruct is_convertible\n{\n  enum { value = is_convertible_impl<typename remove_all<From>::type,\n                                     typename remove_all<To  >::type>::value };\n};\n\n/** \\internal Allows to enable/disable an overload\n  * according to a compile time condition.\n  */\ntemplate<bool Condition, typename T=void> struct enable_if;\n\ntemplate<typename T> struct enable_if<true,T>\n{ typedef T type; };\n\n#if defined(__CUDA_ARCH__)\n#if !defined(__FLT_EPSILON__)\n#define __FLT_EPSILON__ FLT_EPSILON\n#define __DBL_EPSILON__ DBL_EPSILON\n#endif\n\nnamespace device {\n\ntemplate<typename T> struct numeric_limits\n{\n  EIGEN_DEVICE_FUNC\n  static T epsilon() { return 0; }\n  static T (max)() { assert(false && \"Highest not supported for this type\"); }\n  static T (min)() { assert(false && \"Lowest not supported for this type\"); }\n  static T infinity() { assert(false && \"Infinity not supported for this type\"); }\n  static T quiet_NaN() { assert(false && \"quiet_NaN not supported for this type\"); }\n};\ntemplate<> struct numeric_limits<float>\n{\n  EIGEN_DEVICE_FUNC\n  static float epsilon() { return __FLT_EPSILON__; }\n  EIGEN_DEVICE_FUNC\n  static float (max)() { return CUDART_MAX_NORMAL_F; }\n  EIGEN_DEVICE_FUNC\n  static float (min)() { return FLT_MIN; }\n  EIGEN_DEVICE_FUNC\n  static float infinity() { return CUDART_INF_F; }\n  EIGEN_DEVICE_FUNC\n  static float quiet_NaN() { return CUDART_NAN_F; }\n};\ntemplate<> struct numeric_limits<double>\n{\n  EIGEN_DEVICE_FUNC\n  static double epsilon() { return __DBL_EPSILON__; }\n  EIGEN_DEVICE_FUNC\n  static double (max)() { return DBL_MAX; }\n  EIGEN_DEVICE_FUNC\n  static double (min)() { return DBL_MIN; }\n  EIGEN_DEVICE_FUNC\n  static double infinity() { return CUDART_INF; }\n  EIGEN_DEVICE_FUNC\n  static double quiet_NaN() { return CUDART_NAN; }\n};\ntemplate<> struct numeric_limits<int>\n{\n  EIGEN_DEVICE_FUNC\n  static int epsilon() { return 0; }\n  EIGEN_DEVICE_FUNC\n  static int (max)() { return INT_MAX; }\n  EIGEN_DEVICE_FUNC\n  static int (min)() { return INT_MIN; }\n};\ntemplate<> struct numeric_limits<unsigned int>\n{\n  EIGEN_DEVICE_FUNC\n  static unsigned int epsilon() { return 0; }\n  EIGEN_DEVICE_FUNC\n  static unsigned int (max)() { return UINT_MAX; }\n  EIGEN_DEVICE_FUNC\n  static unsigned int (min)() { return 0; }\n};\ntemplate<> struct numeric_limits<long>\n{\n  EIGEN_DEVICE_FUNC\n  static long epsilon() { return 0; }\n  EIGEN_DEVICE_FUNC\n  static long (max)() { return LONG_MAX; }\n  EIGEN_DEVICE_FUNC\n  static long (min)() { return LONG_MIN; }\n};\ntemplate<> struct numeric_limits<unsigned long>\n{\n  EIGEN_DEVICE_FUNC\n  static unsigned long epsilon() { return 0; }\n  EIGEN_DEVICE_FUNC\n  static unsigned long (max)() { return ULONG_MAX; }\n  EIGEN_DEVICE_FUNC\n  static unsigned long (min)() { return 0; }\n};\ntemplate<> struct numeric_limits<long long>\n{\n  EIGEN_DEVICE_FUNC\n  static long long epsilon() { return 0; }\n  EIGEN_DEVICE_FUNC\n  static long long (max)() { return LLONG_MAX; }\n  EIGEN_DEVICE_FUNC\n  static long long (min)() { return LLONG_MIN; }\n};\ntemplate<> struct numeric_limits<unsigned long long>\n{\n  EIGEN_DEVICE_FUNC\n  static unsigned long long epsilon() { return 0; }\n  EIGEN_DEVICE_FUNC\n  static unsigned long long (max)() { return ULLONG_MAX; }\n  EIGEN_DEVICE_FUNC\n  static unsigned long long (min)() { return 0; }\n};\n\n}\n\n#endif\n\n/** \\internal\n  * A base class do disable default copy ctor and copy assignement operator.\n  */\nclass noncopyable\n{\n  EIGEN_DEVICE_FUNC noncopyable(const noncopyable&);\n  EIGEN_DEVICE_FUNC const noncopyable& operator=(const noncopyable&);\nprotected:\n  EIGEN_DEVICE_FUNC noncopyable() {}\n  EIGEN_DEVICE_FUNC ~noncopyable() {}\n};\n\n/** \\internal\n  * Convenient struct to get the result type of a unary or binary functor.\n  *\n  * It supports both the current STL mechanism (using the result_type member) as well as\n  * upcoming next STL generation (using a templated result member).\n  * If none of these members is provided, then the type of the first argument is returned. FIXME, that behavior is a pretty bad hack.\n  */\n#if EIGEN_HAS_STD_RESULT_OF\ntemplate<typename T> struct result_of {\n  typedef typename std::result_of<T>::type type1;\n  typedef typename remove_all<type1>::type type;\n};\n#else\ntemplate<typename T> struct result_of { };\n\nstruct has_none {int a[1];};\nstruct has_std_result_type {int a[2];};\nstruct has_tr1_result {int a[3];};\n\ntemplate<typename Func, typename ArgType, int SizeOf=sizeof(has_none)>\nstruct unary_result_of_select {typedef typename internal::remove_all<ArgType>::type type;};\n\ntemplate<typename Func, typename ArgType>\nstruct unary_result_of_select<Func, ArgType, sizeof(has_std_result_type)> {typedef typename Func::result_type type;};\n\ntemplate<typename Func, typename ArgType>\nstruct unary_result_of_select<Func, ArgType, sizeof(has_tr1_result)> {typedef typename Func::template result<Func(ArgType)>::type type;};\n\ntemplate<typename Func, typename ArgType>\nstruct result_of<Func(ArgType)> {\n    template<typename T>\n    static has_std_result_type    testFunctor(T const *, typename T::result_type const * = 0);\n    template<typename T>\n    static has_tr1_result         testFunctor(T const *, typename T::template result<T(ArgType)>::type const * = 0);\n    static has_none               testFunctor(...);\n\n    // note that the following indirection is needed for gcc-3.3\n    enum {FunctorType = sizeof(testFunctor(static_cast<Func*>(0)))};\n    typedef typename unary_result_of_select<Func, ArgType, FunctorType>::type type;\n};\n\ntemplate<typename Func, typename ArgType0, typename ArgType1, int SizeOf=sizeof(has_none)>\nstruct binary_result_of_select {typedef typename internal::remove_all<ArgType0>::type type;};\n\ntemplate<typename Func, typename ArgType0, typename ArgType1>\nstruct binary_result_of_select<Func, ArgType0, ArgType1, sizeof(has_std_result_type)>\n{typedef typename Func::result_type type;};\n\ntemplate<typename Func, typename ArgType0, typename ArgType1>\nstruct binary_result_of_select<Func, ArgType0, ArgType1, sizeof(has_tr1_result)>\n{typedef typename Func::template result<Func(ArgType0,ArgType1)>::type type;};\n\ntemplate<typename Func, typename ArgType0, typename ArgType1>\nstruct result_of<Func(ArgType0,ArgType1)> {\n    template<typename T>\n    static has_std_result_type    testFunctor(T const *, typename T::result_type const * = 0);\n    template<typename T>\n    static has_tr1_result         testFunctor(T const *, typename T::template result<T(ArgType0,ArgType1)>::type const * = 0);\n    static has_none               testFunctor(...);\n\n    // note that the following indirection is needed for gcc-3.3\n    enum {FunctorType = sizeof(testFunctor(static_cast<Func*>(0)))};\n    typedef typename binary_result_of_select<Func, ArgType0, ArgType1, FunctorType>::type type;\n};\n\ntemplate<typename Func, typename ArgType0, typename ArgType1, typename ArgType2, int SizeOf=sizeof(has_none)>\nstruct ternary_result_of_select {typedef typename internal::remove_all<ArgType0>::type type;};\n\ntemplate<typename Func, typename ArgType0, typename ArgType1, typename ArgType2>\nstruct ternary_result_of_select<Func, ArgType0, ArgType1, ArgType2, sizeof(has_std_result_type)>\n{typedef typename Func::result_type type;};\n\ntemplate<typename Func, typename ArgType0, typename ArgType1, typename ArgType2>\nstruct ternary_result_of_select<Func, ArgType0, ArgType1, ArgType2, sizeof(has_tr1_result)>\n{typedef typename Func::template result<Func(ArgType0,ArgType1,ArgType2)>::type type;};\n\ntemplate<typename Func, typename ArgType0, typename ArgType1, typename ArgType2>\nstruct result_of<Func(ArgType0,ArgType1,ArgType2)> {\n    template<typename T>\n    static has_std_result_type    testFunctor(T const *, typename T::result_type const * = 0);\n    template<typename T>\n    static has_tr1_result         testFunctor(T const *, typename T::template result<T(ArgType0,ArgType1,ArgType2)>::type const * = 0);\n    static has_none               testFunctor(...);\n\n    // note that the following indirection is needed for gcc-3.3\n    enum {FunctorType = sizeof(testFunctor(static_cast<Func*>(0)))};\n    typedef typename ternary_result_of_select<Func, ArgType0, ArgType1, ArgType2, FunctorType>::type type;\n};\n#endif\n\nstruct meta_yes { char a[1]; };\nstruct meta_no  { char a[2]; };\n\n// Check whether T::ReturnType does exist\ntemplate <typename T>\nstruct has_ReturnType\n{\n  template <typename C> static meta_yes testFunctor(typename C::ReturnType const *);\n  template <typename C> static meta_no testFunctor(...);\n\n  enum { value = sizeof(testFunctor<T>(0)) == sizeof(meta_yes) };\n};\n\ntemplate<typename T> const T* return_ptr();\n\ntemplate <typename T, typename IndexType=Index>\nstruct has_nullary_operator\n{\n  template <typename C> static meta_yes testFunctor(C const *,typename enable_if<(sizeof(return_ptr<C>()->operator()())>0)>::type * = 0);\n  static meta_no testFunctor(...);\n\n  enum { value = sizeof(testFunctor(static_cast<T*>(0))) == sizeof(meta_yes) };\n};\n\ntemplate <typename T, typename IndexType=Index>\nstruct has_unary_operator\n{\n  template <typename C> static meta_yes testFunctor(C const *,typename enable_if<(sizeof(return_ptr<C>()->operator()(IndexType(0)))>0)>::type * = 0);\n  static meta_no testFunctor(...);\n\n  enum { value = sizeof(testFunctor(static_cast<T*>(0))) == sizeof(meta_yes) };\n};\n\ntemplate <typename T, typename IndexType=Index>\nstruct has_binary_operator\n{\n  template <typename C> static meta_yes testFunctor(C const *,typename enable_if<(sizeof(return_ptr<C>()->operator()(IndexType(0),IndexType(0)))>0)>::type * = 0);\n  static meta_no testFunctor(...);\n\n  enum { value = sizeof(testFunctor(static_cast<T*>(0))) == sizeof(meta_yes) };\n};\n\n/** \\internal In short, it computes int(sqrt(\\a Y)) with \\a Y an integer.\n  * Usage example: \\code meta_sqrt<1023>::ret \\endcode\n  */\ntemplate<int Y,\n         int InfX = 0,\n         int SupX = ((Y==1) ? 1 : Y/2),\n         bool Done = ((SupX-InfX)<=1 ? true : ((SupX*SupX <= Y) && ((SupX+1)*(SupX+1) > Y))) >\n                                // use ?: instead of || just to shut up a stupid gcc 4.3 warning\nclass meta_sqrt\n{\n    enum {\n      MidX = (InfX+SupX)/2,\n      TakeInf = MidX*MidX > Y ? 1 : 0,\n      NewInf = int(TakeInf) ? InfX : int(MidX),\n      NewSup = int(TakeInf) ? int(MidX) : SupX\n    };\n  public:\n    enum { ret = meta_sqrt<Y,NewInf,NewSup>::ret };\n};\n\ntemplate<int Y, int InfX, int SupX>\nclass meta_sqrt<Y, InfX, SupX, true> { public:  enum { ret = (SupX*SupX <= Y) ? SupX : InfX }; };\n\n\n/** \\internal Computes the least common multiple of two positive integer A and B\n  * at compile-time. It implements a naive algorithm testing all multiples of A.\n  * It thus works better if A>=B.\n  */\ntemplate<int A, int B, int K=1, bool Done = ((A*K)%B)==0>\nstruct meta_least_common_multiple\n{\n  enum { ret = meta_least_common_multiple<A,B,K+1>::ret };\n};\ntemplate<int A, int B, int K>\nstruct meta_least_common_multiple<A,B,K,true>\n{\n  enum { ret = A*K };\n};\n\n/** \\internal determines whether the product of two numeric types is allowed and what the return type is */\ntemplate<typename T, typename U> struct scalar_product_traits\n{\n  enum { Defined = 0 };\n};\n\n// FIXME quick workaround around current limitation of result_of\n// template<typename Scalar, typename ArgType0, typename ArgType1>\n// struct result_of<scalar_product_op<Scalar>(ArgType0,ArgType1)> {\n// typedef typename scalar_product_traits<typename remove_all<ArgType0>::type, typename remove_all<ArgType1>::type>::ReturnType type;\n// };\n\n} // end namespace internal\n\nnamespace numext {\n  \n#if defined(__CUDA_ARCH__)\ntemplate<typename T> EIGEN_DEVICE_FUNC   void swap(T &a, T &b) { T tmp = b; b = a; a = tmp; }\n#else\ntemplate<typename T> EIGEN_STRONG_INLINE void swap(T &a, T &b) { std::swap(a,b); }\n#endif\n\n#if defined(__CUDA_ARCH__)\nusing internal::device::numeric_limits;\n#else\nusing std::numeric_limits;\n#endif\n\n// Integer division with rounding up.\n// T is assumed to be an integer type with a>=0, and b>0\ntemplate<typename T>\nT div_ceil(const T &a, const T &b)\n{\n  return (a+b-1) / b;\n}\n\n} // end namespace numext\n\n} // end namespace Eigen\n\n#endif // EIGEN_META_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/util/NonMPL2.h",
    "content": "#ifdef EIGEN_MPL2_ONLY\n#error Including non-MPL2 code in EIGEN_MPL2_ONLY mode\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/util/ReenableStupidWarnings.h",
    "content": "#ifdef EIGEN_WARNINGS_DISABLED\n#undef EIGEN_WARNINGS_DISABLED\n\n#ifndef EIGEN_PERMANENTLY_DISABLE_STUPID_WARNINGS\n  #ifdef _MSC_VER\n    #pragma warning( pop )\n  #elif defined __INTEL_COMPILER\n    #pragma warning pop\n  #elif defined __clang__\n    #pragma clang diagnostic pop\n  #elif defined __GNUC__ && __GNUC__>=6\n    #pragma GCC diagnostic pop\n  #endif\n\n  #if defined __NVCC__\n//    Don't reenable the diagnostic messages, as it turns out these messages need\n//    to be disabled at the point of the template instantiation (i.e the user code)\n//    otherwise they'll be triggered by nvcc.\n//    #pragma diag_default code_is_unreachable\n//    #pragma diag_default initialization_not_reachable\n//    #pragma diag_default 2651\n//    #pragma diag_default 2653\n  #endif\n\n#endif\n\n#endif // EIGEN_WARNINGS_DISABLED\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/util/StaticAssert.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2008 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_STATIC_ASSERT_H\n#define EIGEN_STATIC_ASSERT_H\n\n/* Some notes on Eigen's static assertion mechanism:\n *\n *  - in EIGEN_STATIC_ASSERT(CONDITION,MSG) the parameter CONDITION must be a compile time boolean\n *    expression, and MSG an enum listed in struct internal::static_assertion<true>\n *\n *  - define EIGEN_NO_STATIC_ASSERT to disable them (and save compilation time)\n *    in that case, the static assertion is converted to the following runtime assert:\n *      eigen_assert(CONDITION && \"MSG\")\n *\n *  - currently EIGEN_STATIC_ASSERT can only be used in function scope\n *\n */\n\n#ifndef EIGEN_NO_STATIC_ASSERT\n\n  #if EIGEN_MAX_CPP_VER>=11 && (__has_feature(cxx_static_assert) || (defined(__cplusplus) && __cplusplus >= 201103L) || (EIGEN_COMP_MSVC >= 1600))\n\n    // if native static_assert is enabled, let's use it\n    #define EIGEN_STATIC_ASSERT(X,MSG) static_assert(X,#MSG);\n\n  #else // not CXX0X\n\n    namespace Eigen {\n\n    namespace internal {\n\n    template<bool condition>\n    struct static_assertion {};\n\n    template<>\n    struct static_assertion<true>\n    {\n      enum {\n        YOU_TRIED_CALLING_A_VECTOR_METHOD_ON_A_MATRIX,\n        YOU_MIXED_VECTORS_OF_DIFFERENT_SIZES,\n        YOU_MIXED_MATRICES_OF_DIFFERENT_SIZES,\n        THIS_METHOD_IS_ONLY_FOR_VECTORS_OF_A_SPECIFIC_SIZE,\n        THIS_METHOD_IS_ONLY_FOR_MATRICES_OF_A_SPECIFIC_SIZE,\n        THIS_METHOD_IS_ONLY_FOR_OBJECTS_OF_A_SPECIFIC_SIZE,\n        OUT_OF_RANGE_ACCESS,\n        YOU_MADE_A_PROGRAMMING_MISTAKE,\n        EIGEN_INTERNAL_ERROR_PLEASE_FILE_A_BUG_REPORT,\n        EIGEN_INTERNAL_COMPILATION_ERROR_OR_YOU_MADE_A_PROGRAMMING_MISTAKE,\n        YOU_CALLED_A_FIXED_SIZE_METHOD_ON_A_DYNAMIC_SIZE_MATRIX_OR_VECTOR,\n        YOU_CALLED_A_DYNAMIC_SIZE_METHOD_ON_A_FIXED_SIZE_MATRIX_OR_VECTOR,\n        UNALIGNED_LOAD_AND_STORE_OPERATIONS_UNIMPLEMENTED_ON_ALTIVEC,\n        THIS_FUNCTION_IS_NOT_FOR_INTEGER_NUMERIC_TYPES,\n        FLOATING_POINT_ARGUMENT_PASSED__INTEGER_WAS_EXPECTED,\n        NUMERIC_TYPE_MUST_BE_REAL,\n        COEFFICIENT_WRITE_ACCESS_TO_SELFADJOINT_NOT_SUPPORTED,\n        WRITING_TO_TRIANGULAR_PART_WITH_UNIT_DIAGONAL_IS_NOT_SUPPORTED,\n        THIS_METHOD_IS_ONLY_FOR_FIXED_SIZE,\n        INVALID_MATRIX_PRODUCT,\n        INVALID_VECTOR_VECTOR_PRODUCT__IF_YOU_WANTED_A_DOT_OR_COEFF_WISE_PRODUCT_YOU_MUST_USE_THE_EXPLICIT_FUNCTIONS,\n        INVALID_MATRIX_PRODUCT__IF_YOU_WANTED_A_COEFF_WISE_PRODUCT_YOU_MUST_USE_THE_EXPLICIT_FUNCTION,\n        YOU_MIXED_DIFFERENT_NUMERIC_TYPES__YOU_NEED_TO_USE_THE_CAST_METHOD_OF_MATRIXBASE_TO_CAST_NUMERIC_TYPES_EXPLICITLY,\n        THIS_METHOD_IS_ONLY_FOR_COLUMN_MAJOR_MATRICES,\n        THIS_METHOD_IS_ONLY_FOR_ROW_MAJOR_MATRICES,\n        INVALID_MATRIX_TEMPLATE_PARAMETERS,\n        INVALID_MATRIXBASE_TEMPLATE_PARAMETERS,\n        BOTH_MATRICES_MUST_HAVE_THE_SAME_STORAGE_ORDER,\n        THIS_METHOD_IS_ONLY_FOR_DIAGONAL_MATRIX,\n        THE_MATRIX_OR_EXPRESSION_THAT_YOU_PASSED_DOES_NOT_HAVE_THE_EXPECTED_TYPE,\n        THIS_METHOD_IS_ONLY_FOR_EXPRESSIONS_WITH_DIRECT_MEMORY_ACCESS_SUCH_AS_MAP_OR_PLAIN_MATRICES,\n        YOU_ALREADY_SPECIFIED_THIS_STRIDE,\n        INVALID_STORAGE_ORDER_FOR_THIS_VECTOR_EXPRESSION,\n        THE_BRACKET_OPERATOR_IS_ONLY_FOR_VECTORS__USE_THE_PARENTHESIS_OPERATOR_INSTEAD,\n        PACKET_ACCESS_REQUIRES_TO_HAVE_INNER_STRIDE_FIXED_TO_1,\n        THIS_METHOD_IS_ONLY_FOR_SPECIFIC_TRANSFORMATIONS,\n        YOU_CANNOT_MIX_ARRAYS_AND_MATRICES,\n        YOU_PERFORMED_AN_INVALID_TRANSFORMATION_CONVERSION,\n        THIS_EXPRESSION_IS_NOT_A_LVALUE__IT_IS_READ_ONLY,\n        YOU_ARE_TRYING_TO_USE_AN_INDEX_BASED_ACCESSOR_ON_AN_EXPRESSION_THAT_DOES_NOT_SUPPORT_THAT,\n        THIS_METHOD_IS_ONLY_FOR_1x1_EXPRESSIONS,\n        THIS_METHOD_IS_ONLY_FOR_INNER_OR_LAZY_PRODUCTS,\n        THIS_METHOD_IS_ONLY_FOR_EXPRESSIONS_OF_BOOL,\n        THIS_METHOD_IS_ONLY_FOR_ARRAYS_NOT_MATRICES,\n        YOU_PASSED_A_ROW_VECTOR_BUT_A_COLUMN_VECTOR_WAS_EXPECTED,\n        YOU_PASSED_A_COLUMN_VECTOR_BUT_A_ROW_VECTOR_WAS_EXPECTED,\n        THE_INDEX_TYPE_MUST_BE_A_SIGNED_TYPE,\n        THE_STORAGE_ORDER_OF_BOTH_SIDES_MUST_MATCH,\n        OBJECT_ALLOCATED_ON_STACK_IS_TOO_BIG,\n        IMPLICIT_CONVERSION_TO_SCALAR_IS_FOR_INNER_PRODUCT_ONLY,\n        STORAGE_LAYOUT_DOES_NOT_MATCH,\n        EIGEN_INTERNAL_ERROR_PLEASE_FILE_A_BUG_REPORT__INVALID_COST_VALUE,\n        THIS_COEFFICIENT_ACCESSOR_TAKING_ONE_ACCESS_IS_ONLY_FOR_EXPRESSIONS_ALLOWING_LINEAR_ACCESS,\n        MATRIX_FREE_CONJUGATE_GRADIENT_IS_COMPATIBLE_WITH_UPPER_UNION_LOWER_MODE_ONLY,\n        THIS_TYPE_IS_NOT_SUPPORTED,\n        STORAGE_KIND_MUST_MATCH,\n        STORAGE_INDEX_MUST_MATCH,\n        CHOLMOD_SUPPORTS_DOUBLE_PRECISION_ONLY\n      };\n    };\n\n    } // end namespace internal\n\n    } // end namespace Eigen\n\n    // Specialized implementation for MSVC to avoid \"conditional\n    // expression is constant\" warnings.  This implementation doesn't\n    // appear to work under GCC, hence the multiple implementations.\n    #if EIGEN_COMP_MSVC\n\n      #define EIGEN_STATIC_ASSERT(CONDITION,MSG) \\\n        {Eigen::internal::static_assertion<bool(CONDITION)>::MSG;}\n\n    #else\n      // In some cases clang interprets bool(CONDITION) as function declaration\n      #define EIGEN_STATIC_ASSERT(CONDITION,MSG) \\\n        if (Eigen::internal::static_assertion<static_cast<bool>(CONDITION)>::MSG) {}\n\n    #endif\n\n  #endif // not CXX0X\n\n#else // EIGEN_NO_STATIC_ASSERT\n\n  #define EIGEN_STATIC_ASSERT(CONDITION,MSG) eigen_assert((CONDITION) && #MSG);\n\n#endif // EIGEN_NO_STATIC_ASSERT\n\n\n// static assertion failing if the type \\a TYPE is not a vector type\n#define EIGEN_STATIC_ASSERT_VECTOR_ONLY(TYPE) \\\n  EIGEN_STATIC_ASSERT(TYPE::IsVectorAtCompileTime, \\\n                      YOU_TRIED_CALLING_A_VECTOR_METHOD_ON_A_MATRIX)\n\n// static assertion failing if the type \\a TYPE is not fixed-size\n#define EIGEN_STATIC_ASSERT_FIXED_SIZE(TYPE) \\\n  EIGEN_STATIC_ASSERT(TYPE::SizeAtCompileTime!=Eigen::Dynamic, \\\n                      YOU_CALLED_A_FIXED_SIZE_METHOD_ON_A_DYNAMIC_SIZE_MATRIX_OR_VECTOR)\n\n// static assertion failing if the type \\a TYPE is not dynamic-size\n#define EIGEN_STATIC_ASSERT_DYNAMIC_SIZE(TYPE) \\\n  EIGEN_STATIC_ASSERT(TYPE::SizeAtCompileTime==Eigen::Dynamic, \\\n                      YOU_CALLED_A_DYNAMIC_SIZE_METHOD_ON_A_FIXED_SIZE_MATRIX_OR_VECTOR)\n\n// static assertion failing if the type \\a TYPE is not a vector type of the given size\n#define EIGEN_STATIC_ASSERT_VECTOR_SPECIFIC_SIZE(TYPE, SIZE) \\\n  EIGEN_STATIC_ASSERT(TYPE::IsVectorAtCompileTime && TYPE::SizeAtCompileTime==SIZE, \\\n                      THIS_METHOD_IS_ONLY_FOR_VECTORS_OF_A_SPECIFIC_SIZE)\n\n// static assertion failing if the type \\a TYPE is not a vector type of the given size\n#define EIGEN_STATIC_ASSERT_MATRIX_SPECIFIC_SIZE(TYPE, ROWS, COLS) \\\n  EIGEN_STATIC_ASSERT(TYPE::RowsAtCompileTime==ROWS && TYPE::ColsAtCompileTime==COLS, \\\n                      THIS_METHOD_IS_ONLY_FOR_MATRICES_OF_A_SPECIFIC_SIZE)\n\n// static assertion failing if the two vector expression types are not compatible (same fixed-size or dynamic size)\n#define EIGEN_STATIC_ASSERT_SAME_VECTOR_SIZE(TYPE0,TYPE1) \\\n  EIGEN_STATIC_ASSERT( \\\n      (int(TYPE0::SizeAtCompileTime)==Eigen::Dynamic \\\n    || int(TYPE1::SizeAtCompileTime)==Eigen::Dynamic \\\n    || int(TYPE0::SizeAtCompileTime)==int(TYPE1::SizeAtCompileTime)),\\\n    YOU_MIXED_VECTORS_OF_DIFFERENT_SIZES)\n\n#define EIGEN_PREDICATE_SAME_MATRIX_SIZE(TYPE0,TYPE1) \\\n     ( \\\n        (int(Eigen::internal::size_of_xpr_at_compile_time<TYPE0>::ret)==0 && int(Eigen::internal::size_of_xpr_at_compile_time<TYPE1>::ret)==0) \\\n    || (\\\n          (int(TYPE0::RowsAtCompileTime)==Eigen::Dynamic \\\n        || int(TYPE1::RowsAtCompileTime)==Eigen::Dynamic \\\n        || int(TYPE0::RowsAtCompileTime)==int(TYPE1::RowsAtCompileTime)) \\\n      &&  (int(TYPE0::ColsAtCompileTime)==Eigen::Dynamic \\\n        || int(TYPE1::ColsAtCompileTime)==Eigen::Dynamic \\\n        || int(TYPE0::ColsAtCompileTime)==int(TYPE1::ColsAtCompileTime))\\\n       ) \\\n     )\n\n#define EIGEN_STATIC_ASSERT_NON_INTEGER(TYPE) \\\n    EIGEN_STATIC_ASSERT(!NumTraits<TYPE>::IsInteger, THIS_FUNCTION_IS_NOT_FOR_INTEGER_NUMERIC_TYPES)\n\n\n// static assertion failing if it is guaranteed at compile-time that the two matrix expression types have different sizes\n#define EIGEN_STATIC_ASSERT_SAME_MATRIX_SIZE(TYPE0,TYPE1) \\\n  EIGEN_STATIC_ASSERT( \\\n     EIGEN_PREDICATE_SAME_MATRIX_SIZE(TYPE0,TYPE1),\\\n    YOU_MIXED_MATRICES_OF_DIFFERENT_SIZES)\n\n#define EIGEN_STATIC_ASSERT_SIZE_1x1(TYPE) \\\n      EIGEN_STATIC_ASSERT((TYPE::RowsAtCompileTime == 1 || TYPE::RowsAtCompileTime == Dynamic) && \\\n                          (TYPE::ColsAtCompileTime == 1 || TYPE::ColsAtCompileTime == Dynamic), \\\n                          THIS_METHOD_IS_ONLY_FOR_1x1_EXPRESSIONS)\n\n#define EIGEN_STATIC_ASSERT_LVALUE(Derived) \\\n      EIGEN_STATIC_ASSERT(Eigen::internal::is_lvalue<Derived>::value, \\\n                          THIS_EXPRESSION_IS_NOT_A_LVALUE__IT_IS_READ_ONLY)\n\n#define EIGEN_STATIC_ASSERT_ARRAYXPR(Derived) \\\n      EIGEN_STATIC_ASSERT((Eigen::internal::is_same<typename Eigen::internal::traits<Derived>::XprKind, ArrayXpr>::value), \\\n                          THIS_METHOD_IS_ONLY_FOR_ARRAYS_NOT_MATRICES)\n\n#define EIGEN_STATIC_ASSERT_SAME_XPR_KIND(Derived1, Derived2) \\\n      EIGEN_STATIC_ASSERT((Eigen::internal::is_same<typename Eigen::internal::traits<Derived1>::XprKind, \\\n                                             typename Eigen::internal::traits<Derived2>::XprKind \\\n                                            >::value), \\\n                          YOU_CANNOT_MIX_ARRAYS_AND_MATRICES)\n\n// Check that a cost value is positive, and that is stay within a reasonable range\n// TODO this check could be enabled for internal debugging only\n#define EIGEN_INTERNAL_CHECK_COST_VALUE(C) \\\n      EIGEN_STATIC_ASSERT((C)>=0 && (C)<=HugeCost*HugeCost, EIGEN_INTERNAL_ERROR_PLEASE_FILE_A_BUG_REPORT__INVALID_COST_VALUE);\n\n#endif // EIGEN_STATIC_ASSERT_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Core/util/XprHelper.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2006-2008 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_XPRHELPER_H\n#define EIGEN_XPRHELPER_H\n\n// just a workaround because GCC seems to not really like empty structs\n// FIXME: gcc 4.3 generates bad code when strict-aliasing is enabled\n// so currently we simply disable this optimization for gcc 4.3\n#if EIGEN_COMP_GNUC && !EIGEN_GNUC_AT(4,3)\n  #define EIGEN_EMPTY_STRUCT_CTOR(X) \\\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE X() {} \\\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE X(const X& ) {}\n#else\n  #define EIGEN_EMPTY_STRUCT_CTOR(X)\n#endif\n\nnamespace Eigen {\n\nnamespace internal {\n\ntemplate<typename IndexDest, typename IndexSrc>\nEIGEN_DEVICE_FUNC\ninline IndexDest convert_index(const IndexSrc& idx) {\n  // for sizeof(IndexDest)>=sizeof(IndexSrc) compilers should be able to optimize this away:\n  eigen_internal_assert(idx <= NumTraits<IndexDest>::highest() && \"Index value to big for target type\");\n  return IndexDest(idx);\n}\n\n\n// promote_scalar_arg is an helper used in operation between an expression and a scalar, like:\n//    expression * scalar\n// Its role is to determine how the type T of the scalar operand should be promoted given the scalar type ExprScalar of the given expression.\n// The IsSupported template parameter must be provided by the caller as: internal::has_ReturnType<ScalarBinaryOpTraits<ExprScalar,T,op> >::value using the proper order for ExprScalar and T.\n// Then the logic is as follows:\n//  - if the operation is natively supported as defined by IsSupported, then the scalar type is not promoted, and T is returned.\n//  - otherwise, NumTraits<ExprScalar>::Literal is returned if T is implicitly convertible to NumTraits<ExprScalar>::Literal AND that this does not imply a float to integer conversion.\n//  - otherwise, ExprScalar is returned if T is implicitly convertible to ExprScalar AND that this does not imply a float to integer conversion.\n//  - In all other cases, the promoted type is not defined, and the respective operation is thus invalid and not available (SFINAE).\ntemplate<typename ExprScalar,typename T, bool IsSupported>\nstruct promote_scalar_arg;\n\ntemplate<typename S,typename T>\nstruct promote_scalar_arg<S,T,true>\n{\n  typedef T type;\n};\n\n// Recursively check safe conversion to PromotedType, and then ExprScalar if they are different.\ntemplate<typename ExprScalar,typename T,typename PromotedType,\n  bool ConvertibleToLiteral = internal::is_convertible<T,PromotedType>::value,\n  bool IsSafe = NumTraits<T>::IsInteger || !NumTraits<PromotedType>::IsInteger>\nstruct promote_scalar_arg_unsupported;\n\n// Start recursion with NumTraits<ExprScalar>::Literal\ntemplate<typename S,typename T>\nstruct promote_scalar_arg<S,T,false> : promote_scalar_arg_unsupported<S,T,typename NumTraits<S>::Literal> {};\n\n// We found a match!\ntemplate<typename S,typename T, typename PromotedType>\nstruct promote_scalar_arg_unsupported<S,T,PromotedType,true,true>\n{\n  typedef PromotedType type;\n};\n\n// No match, but no real-to-integer issues, and ExprScalar and current PromotedType are different,\n// so let's try to promote to ExprScalar\ntemplate<typename ExprScalar,typename T, typename PromotedType>\nstruct promote_scalar_arg_unsupported<ExprScalar,T,PromotedType,false,true>\n   : promote_scalar_arg_unsupported<ExprScalar,T,ExprScalar>\n{};\n\n// Unsafe real-to-integer, let's stop.\ntemplate<typename S,typename T, typename PromotedType, bool ConvertibleToLiteral>\nstruct promote_scalar_arg_unsupported<S,T,PromotedType,ConvertibleToLiteral,false> {};\n\n// T is not even convertible to ExprScalar, let's stop.\ntemplate<typename S,typename T>\nstruct promote_scalar_arg_unsupported<S,T,S,false,true> {};\n\n//classes inheriting no_assignment_operator don't generate a default operator=.\nclass no_assignment_operator\n{\n  private:\n    no_assignment_operator& operator=(const no_assignment_operator&);\n};\n\n/** \\internal return the index type with the largest number of bits */\ntemplate<typename I1, typename I2>\nstruct promote_index_type\n{\n  typedef typename conditional<(sizeof(I1)<sizeof(I2)), I2, I1>::type type;\n};\n\n/** \\internal If the template parameter Value is Dynamic, this class is just a wrapper around a T variable that\n  * can be accessed using value() and setValue().\n  * Otherwise, this class is an empty structure and value() just returns the template parameter Value.\n  */\ntemplate<typename T, int Value> class variable_if_dynamic\n{\n  public:\n    EIGEN_EMPTY_STRUCT_CTOR(variable_if_dynamic)\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE explicit variable_if_dynamic(T v) { EIGEN_ONLY_USED_FOR_DEBUG(v); eigen_assert(v == T(Value)); }\n    EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE T value() { return T(Value); }\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE void setValue(T) {}\n};\n\ntemplate<typename T> class variable_if_dynamic<T, Dynamic>\n{\n    T m_value;\n    EIGEN_DEVICE_FUNC variable_if_dynamic() { eigen_assert(false); }\n  public:\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE explicit variable_if_dynamic(T value) : m_value(value) {}\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE T value() const { return m_value; }\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE void setValue(T value) { m_value = value; }\n};\n\n/** \\internal like variable_if_dynamic but for DynamicIndex\n  */\ntemplate<typename T, int Value> class variable_if_dynamicindex\n{\n  public:\n    EIGEN_EMPTY_STRUCT_CTOR(variable_if_dynamicindex)\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE explicit variable_if_dynamicindex(T v) { EIGEN_ONLY_USED_FOR_DEBUG(v); eigen_assert(v == T(Value)); }\n    EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE T value() { return T(Value); }\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE void setValue(T) {}\n};\n\ntemplate<typename T> class variable_if_dynamicindex<T, DynamicIndex>\n{\n    T m_value;\n    EIGEN_DEVICE_FUNC variable_if_dynamicindex() { eigen_assert(false); }\n  public:\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE explicit variable_if_dynamicindex(T value) : m_value(value) {}\n    EIGEN_DEVICE_FUNC T EIGEN_STRONG_INLINE value() const { return m_value; }\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE void setValue(T value) { m_value = value; }\n};\n\ntemplate<typename T> struct functor_traits\n{\n  enum\n  {\n    Cost = 10,\n    PacketAccess = false,\n    IsRepeatable = false\n  };\n};\n\ntemplate<typename T> struct packet_traits;\n\ntemplate<typename T> struct unpacket_traits\n{\n  typedef T type;\n  typedef T half;\n  enum\n  {\n    size = 1,\n    alignment = 1\n  };\n};\n\ntemplate<int Size, typename PacketType,\n         bool Stop = Size==Dynamic || (Size%unpacket_traits<PacketType>::size)==0 || is_same<PacketType,typename unpacket_traits<PacketType>::half>::value>\nstruct find_best_packet_helper;\n\ntemplate< int Size, typename PacketType>\nstruct find_best_packet_helper<Size,PacketType,true>\n{\n  typedef PacketType type;\n};\n\ntemplate<int Size, typename PacketType>\nstruct find_best_packet_helper<Size,PacketType,false>\n{\n  typedef typename find_best_packet_helper<Size,typename unpacket_traits<PacketType>::half>::type type;\n};\n\ntemplate<typename T, int Size>\nstruct find_best_packet\n{\n  typedef typename find_best_packet_helper<Size,typename packet_traits<T>::type>::type type;\n};\n\n#if EIGEN_MAX_STATIC_ALIGN_BYTES>0\ntemplate<int ArrayBytes, int AlignmentBytes,\n         bool Match     =  bool((ArrayBytes%AlignmentBytes)==0),\n         bool TryHalf   =  bool(EIGEN_MIN_ALIGN_BYTES<AlignmentBytes) >\nstruct compute_default_alignment_helper\n{\n  enum { value = 0 };\n};\n\ntemplate<int ArrayBytes, int AlignmentBytes, bool TryHalf>\nstruct compute_default_alignment_helper<ArrayBytes, AlignmentBytes, true, TryHalf> // Match\n{\n  enum { value = AlignmentBytes };\n};\n\ntemplate<int ArrayBytes, int AlignmentBytes>\nstruct compute_default_alignment_helper<ArrayBytes, AlignmentBytes, false, true> // Try-half\n{\n  // current packet too large, try with an half-packet\n  enum { value = compute_default_alignment_helper<ArrayBytes, AlignmentBytes/2>::value };\n};\n#else\n// If static alignment is disabled, no need to bother.\n// This also avoids a division by zero in \"bool Match =  bool((ArrayBytes%AlignmentBytes)==0)\"\ntemplate<int ArrayBytes, int AlignmentBytes>\nstruct compute_default_alignment_helper\n{\n  enum { value = 0 };\n};\n#endif\n\ntemplate<typename T, int Size> struct compute_default_alignment {\n  enum { value = compute_default_alignment_helper<Size*sizeof(T),EIGEN_MAX_STATIC_ALIGN_BYTES>::value };\n};\n\ntemplate<typename T> struct compute_default_alignment<T,Dynamic> {\n  enum { value = EIGEN_MAX_ALIGN_BYTES };\n};\n\ntemplate<typename _Scalar, int _Rows, int _Cols,\n         int _Options = AutoAlign |\n                          ( (_Rows==1 && _Cols!=1) ? RowMajor\n                          : (_Cols==1 && _Rows!=1) ? ColMajor\n                          : EIGEN_DEFAULT_MATRIX_STORAGE_ORDER_OPTION ),\n         int _MaxRows = _Rows,\n         int _MaxCols = _Cols\n> class make_proper_matrix_type\n{\n    enum {\n      IsColVector = _Cols==1 && _Rows!=1,\n      IsRowVector = _Rows==1 && _Cols!=1,\n      Options = IsColVector ? (_Options | ColMajor) & ~RowMajor\n              : IsRowVector ? (_Options | RowMajor) & ~ColMajor\n              : _Options\n    };\n  public:\n    typedef Matrix<_Scalar, _Rows, _Cols, Options, _MaxRows, _MaxCols> type;\n};\n\ntemplate<typename Scalar, int Rows, int Cols, int Options, int MaxRows, int MaxCols>\nclass compute_matrix_flags\n{\n    enum { row_major_bit = Options&RowMajor ? RowMajorBit : 0 };\n  public:\n    // FIXME currently we still have to handle DirectAccessBit at the expression level to handle DenseCoeffsBase<>\n    // and then propagate this information to the evaluator's flags.\n    // However, I (Gael) think that DirectAccessBit should only matter at the evaluation stage.\n    enum { ret = DirectAccessBit | LvalueBit | NestByRefBit | row_major_bit };\n};\n\ntemplate<int _Rows, int _Cols> struct size_at_compile_time\n{\n  enum { ret = (_Rows==Dynamic || _Cols==Dynamic) ? Dynamic : _Rows * _Cols };\n};\n\ntemplate<typename XprType> struct size_of_xpr_at_compile_time\n{\n  enum { ret = size_at_compile_time<traits<XprType>::RowsAtCompileTime,traits<XprType>::ColsAtCompileTime>::ret };\n};\n\n/* plain_matrix_type : the difference from eval is that plain_matrix_type is always a plain matrix type,\n * whereas eval is a const reference in the case of a matrix\n */\n\ntemplate<typename T, typename StorageKind = typename traits<T>::StorageKind> struct plain_matrix_type;\ntemplate<typename T, typename BaseClassType, int Flags> struct plain_matrix_type_dense;\ntemplate<typename T> struct plain_matrix_type<T,Dense>\n{\n  typedef typename plain_matrix_type_dense<T,typename traits<T>::XprKind, traits<T>::Flags>::type type;\n};\ntemplate<typename T> struct plain_matrix_type<T,DiagonalShape>\n{\n  typedef typename T::PlainObject type;\n};\n\ntemplate<typename T, int Flags> struct plain_matrix_type_dense<T,MatrixXpr,Flags>\n{\n  typedef Matrix<typename traits<T>::Scalar,\n                traits<T>::RowsAtCompileTime,\n                traits<T>::ColsAtCompileTime,\n                AutoAlign | (Flags&RowMajorBit ? RowMajor : ColMajor),\n                traits<T>::MaxRowsAtCompileTime,\n                traits<T>::MaxColsAtCompileTime\n          > type;\n};\n\ntemplate<typename T, int Flags> struct plain_matrix_type_dense<T,ArrayXpr,Flags>\n{\n  typedef Array<typename traits<T>::Scalar,\n                traits<T>::RowsAtCompileTime,\n                traits<T>::ColsAtCompileTime,\n                AutoAlign | (Flags&RowMajorBit ? RowMajor : ColMajor),\n                traits<T>::MaxRowsAtCompileTime,\n                traits<T>::MaxColsAtCompileTime\n          > type;\n};\n\n/* eval : the return type of eval(). For matrices, this is just a const reference\n * in order to avoid a useless copy\n */\n\ntemplate<typename T, typename StorageKind = typename traits<T>::StorageKind> struct eval;\n\ntemplate<typename T> struct eval<T,Dense>\n{\n  typedef typename plain_matrix_type<T>::type type;\n//   typedef typename T::PlainObject type;\n//   typedef T::Matrix<typename traits<T>::Scalar,\n//                 traits<T>::RowsAtCompileTime,\n//                 traits<T>::ColsAtCompileTime,\n//                 AutoAlign | (traits<T>::Flags&RowMajorBit ? RowMajor : ColMajor),\n//                 traits<T>::MaxRowsAtCompileTime,\n//                 traits<T>::MaxColsAtCompileTime\n//           > type;\n};\n\ntemplate<typename T> struct eval<T,DiagonalShape>\n{\n  typedef typename plain_matrix_type<T>::type type;\n};\n\n// for matrices, no need to evaluate, just use a const reference to avoid a useless copy\ntemplate<typename _Scalar, int _Rows, int _Cols, int _Options, int _MaxRows, int _MaxCols>\nstruct eval<Matrix<_Scalar, _Rows, _Cols, _Options, _MaxRows, _MaxCols>, Dense>\n{\n  typedef const Matrix<_Scalar, _Rows, _Cols, _Options, _MaxRows, _MaxCols>& type;\n};\n\ntemplate<typename _Scalar, int _Rows, int _Cols, int _Options, int _MaxRows, int _MaxCols>\nstruct eval<Array<_Scalar, _Rows, _Cols, _Options, _MaxRows, _MaxCols>, Dense>\n{\n  typedef const Array<_Scalar, _Rows, _Cols, _Options, _MaxRows, _MaxCols>& type;\n};\n\n\n/* similar to plain_matrix_type, but using the evaluator's Flags */\ntemplate<typename T, typename StorageKind = typename traits<T>::StorageKind> struct plain_object_eval;\n\ntemplate<typename T>\nstruct plain_object_eval<T,Dense>\n{\n  typedef typename plain_matrix_type_dense<T,typename traits<T>::XprKind, evaluator<T>::Flags>::type type;\n};\n\n\n/* plain_matrix_type_column_major : same as plain_matrix_type but guaranteed to be column-major\n */\ntemplate<typename T> struct plain_matrix_type_column_major\n{\n  enum { Rows = traits<T>::RowsAtCompileTime,\n         Cols = traits<T>::ColsAtCompileTime,\n         MaxRows = traits<T>::MaxRowsAtCompileTime,\n         MaxCols = traits<T>::MaxColsAtCompileTime\n  };\n  typedef Matrix<typename traits<T>::Scalar,\n                Rows,\n                Cols,\n                (MaxRows==1&&MaxCols!=1) ? RowMajor : ColMajor,\n                MaxRows,\n                MaxCols\n          > type;\n};\n\n/* plain_matrix_type_row_major : same as plain_matrix_type but guaranteed to be row-major\n */\ntemplate<typename T> struct plain_matrix_type_row_major\n{\n  enum { Rows = traits<T>::RowsAtCompileTime,\n         Cols = traits<T>::ColsAtCompileTime,\n         MaxRows = traits<T>::MaxRowsAtCompileTime,\n         MaxCols = traits<T>::MaxColsAtCompileTime\n  };\n  typedef Matrix<typename traits<T>::Scalar,\n                Rows,\n                Cols,\n                (MaxCols==1&&MaxRows!=1) ? RowMajor : ColMajor,\n                MaxRows,\n                MaxCols\n          > type;\n};\n\n/** \\internal The reference selector for template expressions. The idea is that we don't\n  * need to use references for expressions since they are light weight proxy\n  * objects which should generate no copying overhead. */\ntemplate <typename T>\nstruct ref_selector\n{\n  typedef typename conditional<\n    bool(traits<T>::Flags & NestByRefBit),\n    T const&,\n    const T\n  >::type type;\n  \n  typedef typename conditional<\n    bool(traits<T>::Flags & NestByRefBit),\n    T &,\n    T\n  >::type non_const_type;\n};\n\n/** \\internal Adds the const qualifier on the value-type of T2 if and only if T1 is a const type */\ntemplate<typename T1, typename T2>\nstruct transfer_constness\n{\n  typedef typename conditional<\n    bool(internal::is_const<T1>::value),\n    typename internal::add_const_on_value_type<T2>::type,\n    T2\n  >::type type;\n};\n\n\n// However, we still need a mechanism to detect whether an expression which is evaluated multiple time\n// has to be evaluated into a temporary.\n// That's the purpose of this new nested_eval helper:\n/** \\internal Determines how a given expression should be nested when evaluated multiple times.\n  * For example, when you do a * (b+c), Eigen will determine how the expression b+c should be\n  * evaluated into the bigger product expression. The choice is between nesting the expression b+c as-is, or\n  * evaluating that expression b+c into a temporary variable d, and nest d so that the resulting expression is\n  * a*d. Evaluating can be beneficial for example if every coefficient access in the resulting expression causes\n  * many coefficient accesses in the nested expressions -- as is the case with matrix product for example.\n  *\n  * \\tparam T the type of the expression being nested.\n  * \\tparam n the number of coefficient accesses in the nested expression for each coefficient access in the bigger expression.\n  * \\tparam PlainObject the type of the temporary if needed.\n  */\ntemplate<typename T, int n, typename PlainObject = typename plain_object_eval<T>::type> struct nested_eval\n{\n  enum {\n    ScalarReadCost = NumTraits<typename traits<T>::Scalar>::ReadCost,\n    CoeffReadCost = evaluator<T>::CoeffReadCost,  // NOTE What if an evaluator evaluate itself into a tempory?\n                                                  //      Then CoeffReadCost will be small (e.g., 1) but we still have to evaluate, especially if n>1.\n                                                  //      This situation is already taken care by the EvalBeforeNestingBit flag, which is turned ON\n                                                  //      for all evaluator creating a temporary. This flag is then propagated by the parent evaluators.\n                                                  //      Another solution could be to count the number of temps?\n    NAsInteger = n == Dynamic ? HugeCost : n,\n    CostEval   = (NAsInteger+1) * ScalarReadCost + CoeffReadCost,\n    CostNoEval = NAsInteger * CoeffReadCost,\n    Evaluate = (int(evaluator<T>::Flags) & EvalBeforeNestingBit) || (int(CostEval) < int(CostNoEval))\n  };\n\n  typedef typename conditional<Evaluate, PlainObject, typename ref_selector<T>::type>::type type;\n};\n\ntemplate<typename T>\nEIGEN_DEVICE_FUNC\ninline T* const_cast_ptr(const T* ptr)\n{\n  return const_cast<T*>(ptr);\n}\n\ntemplate<typename Derived, typename XprKind = typename traits<Derived>::XprKind>\nstruct dense_xpr_base\n{\n  /* dense_xpr_base should only ever be used on dense expressions, thus falling either into the MatrixXpr or into the ArrayXpr cases */\n};\n\ntemplate<typename Derived>\nstruct dense_xpr_base<Derived, MatrixXpr>\n{\n  typedef MatrixBase<Derived> type;\n};\n\ntemplate<typename Derived>\nstruct dense_xpr_base<Derived, ArrayXpr>\n{\n  typedef ArrayBase<Derived> type;\n};\n\ntemplate<typename Derived, typename XprKind = typename traits<Derived>::XprKind, typename StorageKind = typename traits<Derived>::StorageKind>\nstruct generic_xpr_base;\n\ntemplate<typename Derived, typename XprKind>\nstruct generic_xpr_base<Derived, XprKind, Dense>\n{\n  typedef typename dense_xpr_base<Derived,XprKind>::type type;\n};\n\ntemplate<typename XprType, typename CastType> struct cast_return_type\n{\n  typedef typename XprType::Scalar CurrentScalarType;\n  typedef typename remove_all<CastType>::type _CastType;\n  typedef typename _CastType::Scalar NewScalarType;\n  typedef typename conditional<is_same<CurrentScalarType,NewScalarType>::value,\n                              const XprType&,CastType>::type type;\n};\n\ntemplate <typename A, typename B> struct promote_storage_type;\n\ntemplate <typename A> struct promote_storage_type<A,A>\n{\n  typedef A ret;\n};\ntemplate <typename A> struct promote_storage_type<A, const A>\n{\n  typedef A ret;\n};\ntemplate <typename A> struct promote_storage_type<const A, A>\n{\n  typedef A ret;\n};\n\n/** \\internal Specify the \"storage kind\" of applying a coefficient-wise\n  * binary operations between two expressions of kinds A and B respectively.\n  * The template parameter Functor permits to specialize the resulting storage kind wrt to\n  * the functor.\n  * The default rules are as follows:\n  * \\code\n  * A      op A      -> A\n  * A      op dense  -> dense\n  * dense  op B      -> dense\n  * sparse op dense  -> sparse\n  * dense  op sparse -> sparse\n  * \\endcode\n  */\ntemplate <typename A, typename B, typename Functor> struct cwise_promote_storage_type;\n\ntemplate <typename A, typename Functor>                   struct cwise_promote_storage_type<A,A,Functor>                                      { typedef A      ret; };\ntemplate <typename Functor>                               struct cwise_promote_storage_type<Dense,Dense,Functor>                              { typedef Dense  ret; };\ntemplate <typename A, typename Functor>                   struct cwise_promote_storage_type<A,Dense,Functor>                                  { typedef Dense  ret; };\ntemplate <typename B, typename Functor>                   struct cwise_promote_storage_type<Dense,B,Functor>                                  { typedef Dense  ret; };\ntemplate <typename Functor>                               struct cwise_promote_storage_type<Sparse,Dense,Functor>                             { typedef Sparse ret; };\ntemplate <typename Functor>                               struct cwise_promote_storage_type<Dense,Sparse,Functor>                             { typedef Sparse ret; };\n\n/** \\internal Specify the \"storage kind\" of multiplying an expression of kind A with kind B.\n  * The template parameter ProductTag permits to specialize the resulting storage kind wrt to\n  * some compile-time properties of the product: GemmProduct, GemvProduct, OuterProduct, InnerProduct.\n  * The default rules are as follows:\n  * \\code\n  *  K * K            -> K\n  *  dense * K        -> dense\n  *  K * dense        -> dense\n  *  diag * K         -> K\n  *  K * diag         -> K\n  *  Perm * K         -> K\n  * K * Perm          -> K\n  * \\endcode\n  */\ntemplate <typename A, typename B, int ProductTag> struct product_promote_storage_type;\n\ntemplate <typename A, int ProductTag> struct product_promote_storage_type<A,                  A,                  ProductTag> { typedef A     ret;};\ntemplate <int ProductTag>             struct product_promote_storage_type<Dense,              Dense,              ProductTag> { typedef Dense ret;};\ntemplate <typename A, int ProductTag> struct product_promote_storage_type<A,                  Dense,              ProductTag> { typedef Dense ret; };\ntemplate <typename B, int ProductTag> struct product_promote_storage_type<Dense,              B,                  ProductTag> { typedef Dense ret; };\n\ntemplate <typename A, int ProductTag> struct product_promote_storage_type<A,                  DiagonalShape,      ProductTag> { typedef A ret; };\ntemplate <typename B, int ProductTag> struct product_promote_storage_type<DiagonalShape,      B,                  ProductTag> { typedef B ret; };\ntemplate <int ProductTag>             struct product_promote_storage_type<Dense,              DiagonalShape,      ProductTag> { typedef Dense ret; };\ntemplate <int ProductTag>             struct product_promote_storage_type<DiagonalShape,      Dense,              ProductTag> { typedef Dense ret; };\n\ntemplate <typename A, int ProductTag> struct product_promote_storage_type<A,                  PermutationStorage, ProductTag> { typedef A ret; };\ntemplate <typename B, int ProductTag> struct product_promote_storage_type<PermutationStorage, B,                  ProductTag> { typedef B ret; };\ntemplate <int ProductTag>             struct product_promote_storage_type<Dense,              PermutationStorage, ProductTag> { typedef Dense ret; };\ntemplate <int ProductTag>             struct product_promote_storage_type<PermutationStorage, Dense,              ProductTag> { typedef Dense ret; };\n\n/** \\internal gives the plain matrix or array type to store a row/column/diagonal of a matrix type.\n  * \\tparam Scalar optional parameter allowing to pass a different scalar type than the one of the MatrixType.\n  */\ntemplate<typename ExpressionType, typename Scalar = typename ExpressionType::Scalar>\nstruct plain_row_type\n{\n  typedef Matrix<Scalar, 1, ExpressionType::ColsAtCompileTime,\n                 ExpressionType::PlainObject::Options | RowMajor, 1, ExpressionType::MaxColsAtCompileTime> MatrixRowType;\n  typedef Array<Scalar, 1, ExpressionType::ColsAtCompileTime,\n                 ExpressionType::PlainObject::Options | RowMajor, 1, ExpressionType::MaxColsAtCompileTime> ArrayRowType;\n\n  typedef typename conditional<\n    is_same< typename traits<ExpressionType>::XprKind, MatrixXpr >::value,\n    MatrixRowType,\n    ArrayRowType \n  >::type type;\n};\n\ntemplate<typename ExpressionType, typename Scalar = typename ExpressionType::Scalar>\nstruct plain_col_type\n{\n  typedef Matrix<Scalar, ExpressionType::RowsAtCompileTime, 1,\n                 ExpressionType::PlainObject::Options & ~RowMajor, ExpressionType::MaxRowsAtCompileTime, 1> MatrixColType;\n  typedef Array<Scalar, ExpressionType::RowsAtCompileTime, 1,\n                 ExpressionType::PlainObject::Options & ~RowMajor, ExpressionType::MaxRowsAtCompileTime, 1> ArrayColType;\n\n  typedef typename conditional<\n    is_same< typename traits<ExpressionType>::XprKind, MatrixXpr >::value,\n    MatrixColType,\n    ArrayColType \n  >::type type;\n};\n\ntemplate<typename ExpressionType, typename Scalar = typename ExpressionType::Scalar>\nstruct plain_diag_type\n{\n  enum { diag_size = EIGEN_SIZE_MIN_PREFER_DYNAMIC(ExpressionType::RowsAtCompileTime, ExpressionType::ColsAtCompileTime),\n         max_diag_size = EIGEN_SIZE_MIN_PREFER_FIXED(ExpressionType::MaxRowsAtCompileTime, ExpressionType::MaxColsAtCompileTime)\n  };\n  typedef Matrix<Scalar, diag_size, 1, ExpressionType::PlainObject::Options & ~RowMajor, max_diag_size, 1> MatrixDiagType;\n  typedef Array<Scalar, diag_size, 1, ExpressionType::PlainObject::Options & ~RowMajor, max_diag_size, 1> ArrayDiagType;\n\n  typedef typename conditional<\n    is_same< typename traits<ExpressionType>::XprKind, MatrixXpr >::value,\n    MatrixDiagType,\n    ArrayDiagType \n  >::type type;\n};\n\ntemplate<typename Expr,typename Scalar = typename Expr::Scalar>\nstruct plain_constant_type\n{\n  enum { Options = (traits<Expr>::Flags&RowMajorBit)?RowMajor:0 };\n\n  typedef Array<Scalar,  traits<Expr>::RowsAtCompileTime,   traits<Expr>::ColsAtCompileTime,\n                Options, traits<Expr>::MaxRowsAtCompileTime,traits<Expr>::MaxColsAtCompileTime> array_type;\n\n  typedef Matrix<Scalar,  traits<Expr>::RowsAtCompileTime,   traits<Expr>::ColsAtCompileTime,\n                 Options, traits<Expr>::MaxRowsAtCompileTime,traits<Expr>::MaxColsAtCompileTime> matrix_type;\n\n  typedef CwiseNullaryOp<scalar_constant_op<Scalar>, const typename conditional<is_same< typename traits<Expr>::XprKind, MatrixXpr >::value, matrix_type, array_type>::type > type;\n};\n\ntemplate<typename ExpressionType>\nstruct is_lvalue\n{\n  enum { value = !bool(is_const<ExpressionType>::value) &&\n                 bool(traits<ExpressionType>::Flags & LvalueBit) };\n};\n\ntemplate<typename T> struct is_diagonal\n{ enum { ret = false }; };\n\ntemplate<typename T> struct is_diagonal<DiagonalBase<T> >\n{ enum { ret = true }; };\n\ntemplate<typename T> struct is_diagonal<DiagonalWrapper<T> >\n{ enum { ret = true }; };\n\ntemplate<typename T, int S> struct is_diagonal<DiagonalMatrix<T,S> >\n{ enum { ret = true }; };\n\ntemplate<typename S1, typename S2> struct glue_shapes;\ntemplate<> struct glue_shapes<DenseShape,TriangularShape> { typedef TriangularShape type;  };\n\ntemplate<typename T1, typename T2>\nbool is_same_dense(const T1 &mat1, const T2 &mat2, typename enable_if<has_direct_access<T1>::ret&&has_direct_access<T2>::ret, T1>::type * = 0)\n{\n  return (mat1.data()==mat2.data()) && (mat1.innerStride()==mat2.innerStride()) && (mat1.outerStride()==mat2.outerStride());\n}\n\ntemplate<typename T1, typename T2>\nbool is_same_dense(const T1 &, const T2 &, typename enable_if<!(has_direct_access<T1>::ret&&has_direct_access<T2>::ret), T1>::type * = 0)\n{\n  return false;\n}\n\n// Internal helper defining the cost of a scalar division for the type T.\n// The default heuristic can be specialized for each scalar type and architecture.\ntemplate<typename T,bool Vectorized=false,typename EnaleIf = void>\nstruct scalar_div_cost {\n  enum { value = 8*NumTraits<T>::MulCost };\n};\n\ntemplate<typename T,bool Vectorized>\nstruct scalar_div_cost<std::complex<T>, Vectorized> {\n  enum { value = 2*scalar_div_cost<T>::value\n               + 6*NumTraits<T>::MulCost\n               + 3*NumTraits<T>::AddCost\n  };\n};\n\n\ntemplate<bool Vectorized>\nstruct scalar_div_cost<signed long,Vectorized,typename conditional<sizeof(long)==8,void,false_type>::type> { enum { value = 24 }; };\ntemplate<bool Vectorized>\nstruct scalar_div_cost<unsigned long,Vectorized,typename conditional<sizeof(long)==8,void,false_type>::type> { enum { value = 21 }; };\n\n\n#ifdef EIGEN_DEBUG_ASSIGN\nstd::string demangle_traversal(int t)\n{\n  if(t==DefaultTraversal) return \"DefaultTraversal\";\n  if(t==LinearTraversal) return \"LinearTraversal\";\n  if(t==InnerVectorizedTraversal) return \"InnerVectorizedTraversal\";\n  if(t==LinearVectorizedTraversal) return \"LinearVectorizedTraversal\";\n  if(t==SliceVectorizedTraversal) return \"SliceVectorizedTraversal\";\n  return \"?\";\n}\nstd::string demangle_unrolling(int t)\n{\n  if(t==NoUnrolling) return \"NoUnrolling\";\n  if(t==InnerUnrolling) return \"InnerUnrolling\";\n  if(t==CompleteUnrolling) return \"CompleteUnrolling\";\n  return \"?\";\n}\nstd::string demangle_flags(int f)\n{\n  std::string res;\n  if(f&RowMajorBit)                 res += \" | RowMajor\";\n  if(f&PacketAccessBit)             res += \" | Packet\";\n  if(f&LinearAccessBit)             res += \" | Linear\";\n  if(f&LvalueBit)                   res += \" | Lvalue\";\n  if(f&DirectAccessBit)             res += \" | Direct\";\n  if(f&NestByRefBit)                res += \" | NestByRef\";\n  if(f&NoPreferredStorageOrderBit)  res += \" | NoPreferredStorageOrderBit\";\n  \n  return res;\n}\n#endif\n\n} // end namespace internal\n\n\n/** \\class ScalarBinaryOpTraits\n  * \\ingroup Core_Module\n  *\n  * \\brief Determines whether the given binary operation of two numeric types is allowed and what the scalar return type is.\n  *\n  * This class permits to control the scalar return type of any binary operation performed on two different scalar types through (partial) template specializations.\n  *\n  * For instance, let \\c U1, \\c U2 and \\c U3 be three user defined scalar types for which most operations between instances of \\c U1 and \\c U2 returns an \\c U3.\n  * You can let %Eigen knows that by defining:\n    \\code\n    template<typename BinaryOp>\n    struct ScalarBinaryOpTraits<U1,U2,BinaryOp> { typedef U3 ReturnType;  };\n    template<typename BinaryOp>\n    struct ScalarBinaryOpTraits<U2,U1,BinaryOp> { typedef U3 ReturnType;  };\n    \\endcode\n  * You can then explicitly disable some particular operations to get more explicit error messages:\n    \\code\n    template<>\n    struct ScalarBinaryOpTraits<U1,U2,internal::scalar_max_op<U1,U2> > {};\n    \\endcode\n  * Or customize the return type for individual operation:\n    \\code\n    template<>\n    struct ScalarBinaryOpTraits<U1,U2,internal::scalar_sum_op<U1,U2> > { typedef U1 ReturnType; };\n    \\endcode\n  *\n  * By default, the following generic combinations are supported:\n  <table class=\"manual\">\n  <tr><th>ScalarA</th><th>ScalarB</th><th>BinaryOp</th><th>ReturnType</th><th>Note</th></tr>\n  <tr            ><td>\\c T </td><td>\\c T </td><td>\\c * </td><td>\\c T </td><td></td></tr>\n  <tr class=\"alt\"><td>\\c NumTraits<T>::Real </td><td>\\c T </td><td>\\c * </td><td>\\c T </td><td>Only if \\c NumTraits<T>::IsComplex </td></tr>\n  <tr            ><td>\\c T </td><td>\\c NumTraits<T>::Real </td><td>\\c * </td><td>\\c T </td><td>Only if \\c NumTraits<T>::IsComplex </td></tr>\n  </table>\n  *\n  * \\sa CwiseBinaryOp\n  */\ntemplate<typename ScalarA, typename ScalarB, typename BinaryOp=internal::scalar_product_op<ScalarA,ScalarB> >\nstruct ScalarBinaryOpTraits\n#ifndef EIGEN_PARSED_BY_DOXYGEN\n  // for backward compatibility, use the hints given by the (deprecated) internal::scalar_product_traits class.\n  : internal::scalar_product_traits<ScalarA,ScalarB>\n#endif // EIGEN_PARSED_BY_DOXYGEN\n{};\n\ntemplate<typename T, typename BinaryOp>\nstruct ScalarBinaryOpTraits<T,T,BinaryOp>\n{\n  typedef T ReturnType;\n};\n\ntemplate <typename T, typename BinaryOp>\nstruct ScalarBinaryOpTraits<T, typename NumTraits<typename internal::enable_if<NumTraits<T>::IsComplex,T>::type>::Real, BinaryOp>\n{\n  typedef T ReturnType;\n};\ntemplate <typename T, typename BinaryOp>\nstruct ScalarBinaryOpTraits<typename NumTraits<typename internal::enable_if<NumTraits<T>::IsComplex,T>::type>::Real, T, BinaryOp>\n{\n  typedef T ReturnType;\n};\n\n// For Matrix * Permutation\ntemplate<typename T, typename BinaryOp>\nstruct ScalarBinaryOpTraits<T,void,BinaryOp>\n{\n  typedef T ReturnType;\n};\n\n// For Permutation * Matrix\ntemplate<typename T, typename BinaryOp>\nstruct ScalarBinaryOpTraits<void,T,BinaryOp>\n{\n  typedef T ReturnType;\n};\n\n// for Permutation*Permutation\ntemplate<typename BinaryOp>\nstruct ScalarBinaryOpTraits<void,void,BinaryOp>\n{\n  typedef void ReturnType;\n};\n\n// We require Lhs and Rhs to have \"compatible\" scalar types.\n// It is tempting to always allow mixing different types but remember that this is often impossible in the vectorized paths.\n// So allowing mixing different types gives very unexpected errors when enabling vectorization, when the user tries to\n// add together a float matrix and a double matrix.\n#define EIGEN_CHECK_BINARY_COMPATIBILIY(BINOP,LHS,RHS) \\\n  EIGEN_STATIC_ASSERT((Eigen::internal::has_ReturnType<ScalarBinaryOpTraits<LHS, RHS,BINOP> >::value), \\\n    YOU_MIXED_DIFFERENT_NUMERIC_TYPES__YOU_NEED_TO_USE_THE_CAST_METHOD_OF_MATRIXBASE_TO_CAST_NUMERIC_TYPES_EXPLICITLY)\n    \n} // end namespace Eigen\n\n#endif // EIGEN_XPRHELPER_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Eigenvalues/ComplexEigenSolver.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009 Claire Maurice\n// Copyright (C) 2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2010,2012 Jitse Niesen <jitse@maths.leeds.ac.uk>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_COMPLEX_EIGEN_SOLVER_H\n#define EIGEN_COMPLEX_EIGEN_SOLVER_H\n\n#include \"./ComplexSchur.h\"\n\nnamespace Eigen { \n\n/** \\eigenvalues_module \\ingroup Eigenvalues_Module\n  *\n  *\n  * \\class ComplexEigenSolver\n  *\n  * \\brief Computes eigenvalues and eigenvectors of general complex matrices\n  *\n  * \\tparam _MatrixType the type of the matrix of which we are\n  * computing the eigendecomposition; this is expected to be an\n  * instantiation of the Matrix class template.\n  *\n  * The eigenvalues and eigenvectors of a matrix \\f$ A \\f$ are scalars\n  * \\f$ \\lambda \\f$ and vectors \\f$ v \\f$ such that \\f$ Av = \\lambda v\n  * \\f$.  If \\f$ D \\f$ is a diagonal matrix with the eigenvalues on\n  * the diagonal, and \\f$ V \\f$ is a matrix with the eigenvectors as\n  * its columns, then \\f$ A V = V D \\f$. The matrix \\f$ V \\f$ is\n  * almost always invertible, in which case we have \\f$ A = V D V^{-1}\n  * \\f$. This is called the eigendecomposition.\n  *\n  * The main function in this class is compute(), which computes the\n  * eigenvalues and eigenvectors of a given function. The\n  * documentation for that function contains an example showing the\n  * main features of the class.\n  *\n  * \\sa class EigenSolver, class SelfAdjointEigenSolver\n  */\ntemplate<typename _MatrixType> class ComplexEigenSolver\n{\n  public:\n\n    /** \\brief Synonym for the template parameter \\p _MatrixType. */\n    typedef _MatrixType MatrixType;\n\n    enum {\n      RowsAtCompileTime = MatrixType::RowsAtCompileTime,\n      ColsAtCompileTime = MatrixType::ColsAtCompileTime,\n      Options = MatrixType::Options,\n      MaxRowsAtCompileTime = MatrixType::MaxRowsAtCompileTime,\n      MaxColsAtCompileTime = MatrixType::MaxColsAtCompileTime\n    };\n\n    /** \\brief Scalar type for matrices of type #MatrixType. */\n    typedef typename MatrixType::Scalar Scalar;\n    typedef typename NumTraits<Scalar>::Real RealScalar;\n    typedef Eigen::Index Index; ///< \\deprecated since Eigen 3.3\n\n    /** \\brief Complex scalar type for #MatrixType.\n      *\n      * This is \\c std::complex<Scalar> if #Scalar is real (e.g.,\n      * \\c float or \\c double) and just \\c Scalar if #Scalar is\n      * complex.\n      */\n    typedef std::complex<RealScalar> ComplexScalar;\n\n    /** \\brief Type for vector of eigenvalues as returned by eigenvalues().\n      *\n      * This is a column vector with entries of type #ComplexScalar.\n      * The length of the vector is the size of #MatrixType.\n      */\n    typedef Matrix<ComplexScalar, ColsAtCompileTime, 1, Options&(~RowMajor), MaxColsAtCompileTime, 1> EigenvalueType;\n\n    /** \\brief Type for matrix of eigenvectors as returned by eigenvectors().\n      *\n      * This is a square matrix with entries of type #ComplexScalar.\n      * The size is the same as the size of #MatrixType.\n      */\n    typedef Matrix<ComplexScalar, RowsAtCompileTime, ColsAtCompileTime, Options, MaxRowsAtCompileTime, MaxColsAtCompileTime> EigenvectorType;\n\n    /** \\brief Default constructor.\n      *\n      * The default constructor is useful in cases in which the user intends to\n      * perform decompositions via compute().\n      */\n    ComplexEigenSolver()\n            : m_eivec(),\n              m_eivalues(),\n              m_schur(),\n              m_isInitialized(false),\n              m_eigenvectorsOk(false),\n              m_matX()\n    {}\n\n    /** \\brief Default Constructor with memory preallocation\n      *\n      * Like the default constructor but with preallocation of the internal data\n      * according to the specified problem \\a size.\n      * \\sa ComplexEigenSolver()\n      */\n    explicit ComplexEigenSolver(Index size)\n            : m_eivec(size, size),\n              m_eivalues(size),\n              m_schur(size),\n              m_isInitialized(false),\n              m_eigenvectorsOk(false),\n              m_matX(size, size)\n    {}\n\n    /** \\brief Constructor; computes eigendecomposition of given matrix.\n      *\n      * \\param[in]  matrix  Square matrix whose eigendecomposition is to be computed.\n      * \\param[in]  computeEigenvectors  If true, both the eigenvectors and the\n      *    eigenvalues are computed; if false, only the eigenvalues are\n      *    computed.\n      *\n      * This constructor calls compute() to compute the eigendecomposition.\n      */\n    template<typename InputType>\n    explicit ComplexEigenSolver(const EigenBase<InputType>& matrix, bool computeEigenvectors = true)\n            : m_eivec(matrix.rows(),matrix.cols()),\n              m_eivalues(matrix.cols()),\n              m_schur(matrix.rows()),\n              m_isInitialized(false),\n              m_eigenvectorsOk(false),\n              m_matX(matrix.rows(),matrix.cols())\n    {\n      compute(matrix.derived(), computeEigenvectors);\n    }\n\n    /** \\brief Returns the eigenvectors of given matrix.\n      *\n      * \\returns  A const reference to the matrix whose columns are the eigenvectors.\n      *\n      * \\pre Either the constructor\n      * ComplexEigenSolver(const MatrixType& matrix, bool) or the member\n      * function compute(const MatrixType& matrix, bool) has been called before\n      * to compute the eigendecomposition of a matrix, and\n      * \\p computeEigenvectors was set to true (the default).\n      *\n      * This function returns a matrix whose columns are the eigenvectors. Column\n      * \\f$ k \\f$ is an eigenvector corresponding to eigenvalue number \\f$ k\n      * \\f$ as returned by eigenvalues().  The eigenvectors are normalized to\n      * have (Euclidean) norm equal to one. The matrix returned by this\n      * function is the matrix \\f$ V \\f$ in the eigendecomposition \\f$ A = V D\n      * V^{-1} \\f$, if it exists.\n      *\n      * Example: \\include ComplexEigenSolver_eigenvectors.cpp\n      * Output: \\verbinclude ComplexEigenSolver_eigenvectors.out\n      */\n    const EigenvectorType& eigenvectors() const\n    {\n      eigen_assert(m_isInitialized && \"ComplexEigenSolver is not initialized.\");\n      eigen_assert(m_eigenvectorsOk && \"The eigenvectors have not been computed together with the eigenvalues.\");\n      return m_eivec;\n    }\n\n    /** \\brief Returns the eigenvalues of given matrix.\n      *\n      * \\returns A const reference to the column vector containing the eigenvalues.\n      *\n      * \\pre Either the constructor\n      * ComplexEigenSolver(const MatrixType& matrix, bool) or the member\n      * function compute(const MatrixType& matrix, bool) has been called before\n      * to compute the eigendecomposition of a matrix.\n      *\n      * This function returns a column vector containing the\n      * eigenvalues. Eigenvalues are repeated according to their\n      * algebraic multiplicity, so there are as many eigenvalues as\n      * rows in the matrix. The eigenvalues are not sorted in any particular\n      * order.\n      *\n      * Example: \\include ComplexEigenSolver_eigenvalues.cpp\n      * Output: \\verbinclude ComplexEigenSolver_eigenvalues.out\n      */\n    const EigenvalueType& eigenvalues() const\n    {\n      eigen_assert(m_isInitialized && \"ComplexEigenSolver is not initialized.\");\n      return m_eivalues;\n    }\n\n    /** \\brief Computes eigendecomposition of given matrix.\n      *\n      * \\param[in]  matrix  Square matrix whose eigendecomposition is to be computed.\n      * \\param[in]  computeEigenvectors  If true, both the eigenvectors and the\n      *    eigenvalues are computed; if false, only the eigenvalues are\n      *    computed.\n      * \\returns    Reference to \\c *this\n      *\n      * This function computes the eigenvalues of the complex matrix \\p matrix.\n      * The eigenvalues() function can be used to retrieve them.  If\n      * \\p computeEigenvectors is true, then the eigenvectors are also computed\n      * and can be retrieved by calling eigenvectors().\n      *\n      * The matrix is first reduced to Schur form using the\n      * ComplexSchur class. The Schur decomposition is then used to\n      * compute the eigenvalues and eigenvectors.\n      *\n      * The cost of the computation is dominated by the cost of the\n      * Schur decomposition, which is \\f$ O(n^3) \\f$ where \\f$ n \\f$\n      * is the size of the matrix.\n      *\n      * Example: \\include ComplexEigenSolver_compute.cpp\n      * Output: \\verbinclude ComplexEigenSolver_compute.out\n      */\n    template<typename InputType>\n    ComplexEigenSolver& compute(const EigenBase<InputType>& matrix, bool computeEigenvectors = true);\n\n    /** \\brief Reports whether previous computation was successful.\n      *\n      * \\returns \\c Success if computation was succesful, \\c NoConvergence otherwise.\n      */\n    ComputationInfo info() const\n    {\n      eigen_assert(m_isInitialized && \"ComplexEigenSolver is not initialized.\");\n      return m_schur.info();\n    }\n\n    /** \\brief Sets the maximum number of iterations allowed. */\n    ComplexEigenSolver& setMaxIterations(Index maxIters)\n    {\n      m_schur.setMaxIterations(maxIters);\n      return *this;\n    }\n\n    /** \\brief Returns the maximum number of iterations. */\n    Index getMaxIterations()\n    {\n      return m_schur.getMaxIterations();\n    }\n\n  protected:\n    \n    static void check_template_parameters()\n    {\n      EIGEN_STATIC_ASSERT_NON_INTEGER(Scalar);\n    }\n    \n    EigenvectorType m_eivec;\n    EigenvalueType m_eivalues;\n    ComplexSchur<MatrixType> m_schur;\n    bool m_isInitialized;\n    bool m_eigenvectorsOk;\n    EigenvectorType m_matX;\n\n  private:\n    void doComputeEigenvectors(const RealScalar& matrixnorm);\n    void sortEigenvalues(bool computeEigenvectors);\n};\n\n\ntemplate<typename MatrixType>\ntemplate<typename InputType>\nComplexEigenSolver<MatrixType>& \nComplexEigenSolver<MatrixType>::compute(const EigenBase<InputType>& matrix, bool computeEigenvectors)\n{\n  check_template_parameters();\n  \n  // this code is inspired from Jampack\n  eigen_assert(matrix.cols() == matrix.rows());\n\n  // Do a complex Schur decomposition, A = U T U^*\n  // The eigenvalues are on the diagonal of T.\n  m_schur.compute(matrix.derived(), computeEigenvectors);\n\n  if(m_schur.info() == Success)\n  {\n    m_eivalues = m_schur.matrixT().diagonal();\n    if(computeEigenvectors)\n      doComputeEigenvectors(m_schur.matrixT().norm());\n    sortEigenvalues(computeEigenvectors);\n  }\n\n  m_isInitialized = true;\n  m_eigenvectorsOk = computeEigenvectors;\n  return *this;\n}\n\n\ntemplate<typename MatrixType>\nvoid ComplexEigenSolver<MatrixType>::doComputeEigenvectors(const RealScalar& matrixnorm)\n{\n  const Index n = m_eivalues.size();\n\n  // Compute X such that T = X D X^(-1), where D is the diagonal of T.\n  // The matrix X is unit triangular.\n  m_matX = EigenvectorType::Zero(n, n);\n  for(Index k=n-1 ; k>=0 ; k--)\n  {\n    m_matX.coeffRef(k,k) = ComplexScalar(1.0,0.0);\n    // Compute X(i,k) using the (i,k) entry of the equation X T = D X\n    for(Index i=k-1 ; i>=0 ; i--)\n    {\n      m_matX.coeffRef(i,k) = -m_schur.matrixT().coeff(i,k);\n      if(k-i-1>0)\n        m_matX.coeffRef(i,k) -= (m_schur.matrixT().row(i).segment(i+1,k-i-1) * m_matX.col(k).segment(i+1,k-i-1)).value();\n      ComplexScalar z = m_schur.matrixT().coeff(i,i) - m_schur.matrixT().coeff(k,k);\n      if(z==ComplexScalar(0))\n      {\n        // If the i-th and k-th eigenvalue are equal, then z equals 0.\n        // Use a small value instead, to prevent division by zero.\n        numext::real_ref(z) = NumTraits<RealScalar>::epsilon() * matrixnorm;\n      }\n      m_matX.coeffRef(i,k) = m_matX.coeff(i,k) / z;\n    }\n  }\n\n  // Compute V as V = U X; now A = U T U^* = U X D X^(-1) U^* = V D V^(-1)\n  m_eivec.noalias() = m_schur.matrixU() * m_matX;\n  // .. and normalize the eigenvectors\n  for(Index k=0 ; k<n ; k++)\n  {\n    m_eivec.col(k).normalize();\n  }\n}\n\n\ntemplate<typename MatrixType>\nvoid ComplexEigenSolver<MatrixType>::sortEigenvalues(bool computeEigenvectors)\n{\n  const Index n =  m_eivalues.size();\n  for (Index i=0; i<n; i++)\n  {\n    Index k;\n    m_eivalues.cwiseAbs().tail(n-i).minCoeff(&k);\n    if (k != 0)\n    {\n      k += i;\n      std::swap(m_eivalues[k],m_eivalues[i]);\n      if(computeEigenvectors)\n\tm_eivec.col(i).swap(m_eivec.col(k));\n    }\n  }\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_COMPLEX_EIGEN_SOLVER_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Eigenvalues/ComplexSchur.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009 Claire Maurice\n// Copyright (C) 2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2010,2012 Jitse Niesen <jitse@maths.leeds.ac.uk>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_COMPLEX_SCHUR_H\n#define EIGEN_COMPLEX_SCHUR_H\n\n#include \"./HessenbergDecomposition.h\"\n\nnamespace Eigen { \n\nnamespace internal {\ntemplate<typename MatrixType, bool IsComplex> struct complex_schur_reduce_to_hessenberg;\n}\n\n/** \\eigenvalues_module \\ingroup Eigenvalues_Module\n  *\n  *\n  * \\class ComplexSchur\n  *\n  * \\brief Performs a complex Schur decomposition of a real or complex square matrix\n  *\n  * \\tparam _MatrixType the type of the matrix of which we are\n  * computing the Schur decomposition; this is expected to be an\n  * instantiation of the Matrix class template.\n  *\n  * Given a real or complex square matrix A, this class computes the\n  * Schur decomposition: \\f$ A = U T U^*\\f$ where U is a unitary\n  * complex matrix, and T is a complex upper triangular matrix.  The\n  * diagonal of the matrix T corresponds to the eigenvalues of the\n  * matrix A.\n  *\n  * Call the function compute() to compute the Schur decomposition of\n  * a given matrix. Alternatively, you can use the \n  * ComplexSchur(const MatrixType&, bool) constructor which computes\n  * the Schur decomposition at construction time. Once the\n  * decomposition is computed, you can use the matrixU() and matrixT()\n  * functions to retrieve the matrices U and V in the decomposition.\n  *\n  * \\note This code is inspired from Jampack\n  *\n  * \\sa class RealSchur, class EigenSolver, class ComplexEigenSolver\n  */\ntemplate<typename _MatrixType> class ComplexSchur\n{\n  public:\n    typedef _MatrixType MatrixType;\n    enum {\n      RowsAtCompileTime = MatrixType::RowsAtCompileTime,\n      ColsAtCompileTime = MatrixType::ColsAtCompileTime,\n      Options = MatrixType::Options,\n      MaxRowsAtCompileTime = MatrixType::MaxRowsAtCompileTime,\n      MaxColsAtCompileTime = MatrixType::MaxColsAtCompileTime\n    };\n\n    /** \\brief Scalar type for matrices of type \\p _MatrixType. */\n    typedef typename MatrixType::Scalar Scalar;\n    typedef typename NumTraits<Scalar>::Real RealScalar;\n    typedef Eigen::Index Index; ///< \\deprecated since Eigen 3.3\n\n    /** \\brief Complex scalar type for \\p _MatrixType. \n      *\n      * This is \\c std::complex<Scalar> if #Scalar is real (e.g.,\n      * \\c float or \\c double) and just \\c Scalar if #Scalar is\n      * complex.\n      */\n    typedef std::complex<RealScalar> ComplexScalar;\n\n    /** \\brief Type for the matrices in the Schur decomposition.\n      *\n      * This is a square matrix with entries of type #ComplexScalar. \n      * The size is the same as the size of \\p _MatrixType.\n      */\n    typedef Matrix<ComplexScalar, RowsAtCompileTime, ColsAtCompileTime, Options, MaxRowsAtCompileTime, MaxColsAtCompileTime> ComplexMatrixType;\n\n    /** \\brief Default constructor.\n      *\n      * \\param [in] size  Positive integer, size of the matrix whose Schur decomposition will be computed.\n      *\n      * The default constructor is useful in cases in which the user\n      * intends to perform decompositions via compute().  The \\p size\n      * parameter is only used as a hint. It is not an error to give a\n      * wrong \\p size, but it may impair performance.\n      *\n      * \\sa compute() for an example.\n      */\n    explicit ComplexSchur(Index size = RowsAtCompileTime==Dynamic ? 1 : RowsAtCompileTime)\n      : m_matT(size,size),\n        m_matU(size,size),\n        m_hess(size),\n        m_isInitialized(false),\n        m_matUisUptodate(false),\n        m_maxIters(-1)\n    {}\n\n    /** \\brief Constructor; computes Schur decomposition of given matrix. \n      * \n      * \\param[in]  matrix    Square matrix whose Schur decomposition is to be computed.\n      * \\param[in]  computeU  If true, both T and U are computed; if false, only T is computed.\n      *\n      * This constructor calls compute() to compute the Schur decomposition.\n      *\n      * \\sa matrixT() and matrixU() for examples.\n      */\n    template<typename InputType>\n    explicit ComplexSchur(const EigenBase<InputType>& matrix, bool computeU = true)\n      : m_matT(matrix.rows(),matrix.cols()),\n        m_matU(matrix.rows(),matrix.cols()),\n        m_hess(matrix.rows()),\n        m_isInitialized(false),\n        m_matUisUptodate(false),\n        m_maxIters(-1)\n    {\n      compute(matrix.derived(), computeU);\n    }\n\n    /** \\brief Returns the unitary matrix in the Schur decomposition. \n      *\n      * \\returns A const reference to the matrix U.\n      *\n      * It is assumed that either the constructor\n      * ComplexSchur(const MatrixType& matrix, bool computeU) or the\n      * member function compute(const MatrixType& matrix, bool computeU)\n      * has been called before to compute the Schur decomposition of a\n      * matrix, and that \\p computeU was set to true (the default\n      * value).\n      *\n      * Example: \\include ComplexSchur_matrixU.cpp\n      * Output: \\verbinclude ComplexSchur_matrixU.out\n      */\n    const ComplexMatrixType& matrixU() const\n    {\n      eigen_assert(m_isInitialized && \"ComplexSchur is not initialized.\");\n      eigen_assert(m_matUisUptodate && \"The matrix U has not been computed during the ComplexSchur decomposition.\");\n      return m_matU;\n    }\n\n    /** \\brief Returns the triangular matrix in the Schur decomposition. \n      *\n      * \\returns A const reference to the matrix T.\n      *\n      * It is assumed that either the constructor\n      * ComplexSchur(const MatrixType& matrix, bool computeU) or the\n      * member function compute(const MatrixType& matrix, bool computeU)\n      * has been called before to compute the Schur decomposition of a\n      * matrix.\n      *\n      * Note that this function returns a plain square matrix. If you want to reference\n      * only the upper triangular part, use:\n      * \\code schur.matrixT().triangularView<Upper>() \\endcode \n      *\n      * Example: \\include ComplexSchur_matrixT.cpp\n      * Output: \\verbinclude ComplexSchur_matrixT.out\n      */\n    const ComplexMatrixType& matrixT() const\n    {\n      eigen_assert(m_isInitialized && \"ComplexSchur is not initialized.\");\n      return m_matT;\n    }\n\n    /** \\brief Computes Schur decomposition of given matrix. \n      * \n      * \\param[in]  matrix  Square matrix whose Schur decomposition is to be computed.\n      * \\param[in]  computeU  If true, both T and U are computed; if false, only T is computed.\n\n      * \\returns    Reference to \\c *this\n      *\n      * The Schur decomposition is computed by first reducing the\n      * matrix to Hessenberg form using the class\n      * HessenbergDecomposition. The Hessenberg matrix is then reduced\n      * to triangular form by performing QR iterations with a single\n      * shift. The cost of computing the Schur decomposition depends\n      * on the number of iterations; as a rough guide, it may be taken\n      * on the number of iterations; as a rough guide, it may be taken\n      * to be \\f$25n^3\\f$ complex flops, or \\f$10n^3\\f$ complex flops\n      * if \\a computeU is false.\n      *\n      * Example: \\include ComplexSchur_compute.cpp\n      * Output: \\verbinclude ComplexSchur_compute.out\n      *\n      * \\sa compute(const MatrixType&, bool, Index)\n      */\n    template<typename InputType>\n    ComplexSchur& compute(const EigenBase<InputType>& matrix, bool computeU = true);\n    \n    /** \\brief Compute Schur decomposition from a given Hessenberg matrix\n     *  \\param[in] matrixH Matrix in Hessenberg form H\n     *  \\param[in] matrixQ orthogonal matrix Q that transform a matrix A to H : A = Q H Q^T\n     *  \\param computeU Computes the matriX U of the Schur vectors\n     * \\return Reference to \\c *this\n     * \n     *  This routine assumes that the matrix is already reduced in Hessenberg form matrixH\n     *  using either the class HessenbergDecomposition or another mean. \n     *  It computes the upper quasi-triangular matrix T of the Schur decomposition of H\n     *  When computeU is true, this routine computes the matrix U such that \n     *  A = U T U^T =  (QZ) T (QZ)^T = Q H Q^T where A is the initial matrix\n     * \n     * NOTE Q is referenced if computeU is true; so, if the initial orthogonal matrix\n     * is not available, the user should give an identity matrix (Q.setIdentity())\n     * \n     * \\sa compute(const MatrixType&, bool)\n     */\n    template<typename HessMatrixType, typename OrthMatrixType>\n    ComplexSchur& computeFromHessenberg(const HessMatrixType& matrixH, const OrthMatrixType& matrixQ,  bool computeU=true);\n\n    /** \\brief Reports whether previous computation was successful.\n      *\n      * \\returns \\c Success if computation was succesful, \\c NoConvergence otherwise.\n      */\n    ComputationInfo info() const\n    {\n      eigen_assert(m_isInitialized && \"ComplexSchur is not initialized.\");\n      return m_info;\n    }\n\n    /** \\brief Sets the maximum number of iterations allowed. \n      *\n      * If not specified by the user, the maximum number of iterations is m_maxIterationsPerRow times the size\n      * of the matrix.\n      */\n    ComplexSchur& setMaxIterations(Index maxIters)\n    {\n      m_maxIters = maxIters;\n      return *this;\n    }\n\n    /** \\brief Returns the maximum number of iterations. */\n    Index getMaxIterations()\n    {\n      return m_maxIters;\n    }\n\n    /** \\brief Maximum number of iterations per row.\n      *\n      * If not otherwise specified, the maximum number of iterations is this number times the size of the\n      * matrix. It is currently set to 30.\n      */\n    static const int m_maxIterationsPerRow = 30;\n\n  protected:\n    ComplexMatrixType m_matT, m_matU;\n    HessenbergDecomposition<MatrixType> m_hess;\n    ComputationInfo m_info;\n    bool m_isInitialized;\n    bool m_matUisUptodate;\n    Index m_maxIters;\n\n  private:  \n    bool subdiagonalEntryIsNeglegible(Index i);\n    ComplexScalar computeShift(Index iu, Index iter);\n    void reduceToTriangularForm(bool computeU);\n    friend struct internal::complex_schur_reduce_to_hessenberg<MatrixType, NumTraits<Scalar>::IsComplex>;\n};\n\n/** If m_matT(i+1,i) is neglegible in floating point arithmetic\n  * compared to m_matT(i,i) and m_matT(j,j), then set it to zero and\n  * return true, else return false. */\ntemplate<typename MatrixType>\ninline bool ComplexSchur<MatrixType>::subdiagonalEntryIsNeglegible(Index i)\n{\n  RealScalar d = numext::norm1(m_matT.coeff(i,i)) + numext::norm1(m_matT.coeff(i+1,i+1));\n  RealScalar sd = numext::norm1(m_matT.coeff(i+1,i));\n  if (internal::isMuchSmallerThan(sd, d, NumTraits<RealScalar>::epsilon()))\n  {\n    m_matT.coeffRef(i+1,i) = ComplexScalar(0);\n    return true;\n  }\n  return false;\n}\n\n\n/** Compute the shift in the current QR iteration. */\ntemplate<typename MatrixType>\ntypename ComplexSchur<MatrixType>::ComplexScalar ComplexSchur<MatrixType>::computeShift(Index iu, Index iter)\n{\n  using std::abs;\n  if (iter == 10 || iter == 20) \n  {\n    // exceptional shift, taken from http://www.netlib.org/eispack/comqr.f\n    return abs(numext::real(m_matT.coeff(iu,iu-1))) + abs(numext::real(m_matT.coeff(iu-1,iu-2)));\n  }\n\n  // compute the shift as one of the eigenvalues of t, the 2x2\n  // diagonal block on the bottom of the active submatrix\n  Matrix<ComplexScalar,2,2> t = m_matT.template block<2,2>(iu-1,iu-1);\n  RealScalar normt = t.cwiseAbs().sum();\n  t /= normt;     // the normalization by sf is to avoid under/overflow\n\n  ComplexScalar b = t.coeff(0,1) * t.coeff(1,0);\n  ComplexScalar c = t.coeff(0,0) - t.coeff(1,1);\n  ComplexScalar disc = sqrt(c*c + RealScalar(4)*b);\n  ComplexScalar det = t.coeff(0,0) * t.coeff(1,1) - b;\n  ComplexScalar trace = t.coeff(0,0) + t.coeff(1,1);\n  ComplexScalar eival1 = (trace + disc) / RealScalar(2);\n  ComplexScalar eival2 = (trace - disc) / RealScalar(2);\n\n  if(numext::norm1(eival1) > numext::norm1(eival2))\n    eival2 = det / eival1;\n  else\n    eival1 = det / eival2;\n\n  // choose the eigenvalue closest to the bottom entry of the diagonal\n  if(numext::norm1(eival1-t.coeff(1,1)) < numext::norm1(eival2-t.coeff(1,1)))\n    return normt * eival1;\n  else\n    return normt * eival2;\n}\n\n\ntemplate<typename MatrixType>\ntemplate<typename InputType>\nComplexSchur<MatrixType>& ComplexSchur<MatrixType>::compute(const EigenBase<InputType>& matrix, bool computeU)\n{\n  m_matUisUptodate = false;\n  eigen_assert(matrix.cols() == matrix.rows());\n\n  if(matrix.cols() == 1)\n  {\n    m_matT = matrix.derived().template cast<ComplexScalar>();\n    if(computeU)  m_matU = ComplexMatrixType::Identity(1,1);\n    m_info = Success;\n    m_isInitialized = true;\n    m_matUisUptodate = computeU;\n    return *this;\n  }\n\n  internal::complex_schur_reduce_to_hessenberg<MatrixType, NumTraits<Scalar>::IsComplex>::run(*this, matrix.derived(), computeU);\n  computeFromHessenberg(m_matT, m_matU, computeU);\n  return *this;\n}\n\ntemplate<typename MatrixType>\ntemplate<typename HessMatrixType, typename OrthMatrixType>\nComplexSchur<MatrixType>& ComplexSchur<MatrixType>::computeFromHessenberg(const HessMatrixType& matrixH, const OrthMatrixType& matrixQ, bool computeU)\n{\n  m_matT = matrixH;\n  if(computeU)\n    m_matU = matrixQ;\n  reduceToTriangularForm(computeU);\n  return *this;\n}\nnamespace internal {\n\n/* Reduce given matrix to Hessenberg form */\ntemplate<typename MatrixType, bool IsComplex>\nstruct complex_schur_reduce_to_hessenberg\n{\n  // this is the implementation for the case IsComplex = true\n  static void run(ComplexSchur<MatrixType>& _this, const MatrixType& matrix, bool computeU)\n  {\n    _this.m_hess.compute(matrix);\n    _this.m_matT = _this.m_hess.matrixH();\n    if(computeU)  _this.m_matU = _this.m_hess.matrixQ();\n  }\n};\n\ntemplate<typename MatrixType>\nstruct complex_schur_reduce_to_hessenberg<MatrixType, false>\n{\n  static void run(ComplexSchur<MatrixType>& _this, const MatrixType& matrix, bool computeU)\n  {\n    typedef typename ComplexSchur<MatrixType>::ComplexScalar ComplexScalar;\n\n    // Note: m_hess is over RealScalar; m_matT and m_matU is over ComplexScalar\n    _this.m_hess.compute(matrix);\n    _this.m_matT = _this.m_hess.matrixH().template cast<ComplexScalar>();\n    if(computeU)  \n    {\n      // This may cause an allocation which seems to be avoidable\n      MatrixType Q = _this.m_hess.matrixQ(); \n      _this.m_matU = Q.template cast<ComplexScalar>();\n    }\n  }\n};\n\n} // end namespace internal\n\n// Reduce the Hessenberg matrix m_matT to triangular form by QR iteration.\ntemplate<typename MatrixType>\nvoid ComplexSchur<MatrixType>::reduceToTriangularForm(bool computeU)\n{  \n  Index maxIters = m_maxIters;\n  if (maxIters == -1)\n    maxIters = m_maxIterationsPerRow * m_matT.rows();\n\n  // The matrix m_matT is divided in three parts. \n  // Rows 0,...,il-1 are decoupled from the rest because m_matT(il,il-1) is zero. \n  // Rows il,...,iu is the part we are working on (the active submatrix).\n  // Rows iu+1,...,end are already brought in triangular form.\n  Index iu = m_matT.cols() - 1;\n  Index il;\n  Index iter = 0; // number of iterations we are working on the (iu,iu) element\n  Index totalIter = 0; // number of iterations for whole matrix\n\n  while(true)\n  {\n    // find iu, the bottom row of the active submatrix\n    while(iu > 0)\n    {\n      if(!subdiagonalEntryIsNeglegible(iu-1)) break;\n      iter = 0;\n      --iu;\n    }\n\n    // if iu is zero then we are done; the whole matrix is triangularized\n    if(iu==0) break;\n\n    // if we spent too many iterations, we give up\n    iter++;\n    totalIter++;\n    if(totalIter > maxIters) break;\n\n    // find il, the top row of the active submatrix\n    il = iu-1;\n    while(il > 0 && !subdiagonalEntryIsNeglegible(il-1))\n    {\n      --il;\n    }\n\n    /* perform the QR step using Givens rotations. The first rotation\n       creates a bulge; the (il+2,il) element becomes nonzero. This\n       bulge is chased down to the bottom of the active submatrix. */\n\n    ComplexScalar shift = computeShift(iu, iter);\n    JacobiRotation<ComplexScalar> rot;\n    rot.makeGivens(m_matT.coeff(il,il) - shift, m_matT.coeff(il+1,il));\n    m_matT.rightCols(m_matT.cols()-il).applyOnTheLeft(il, il+1, rot.adjoint());\n    m_matT.topRows((std::min)(il+2,iu)+1).applyOnTheRight(il, il+1, rot);\n    if(computeU) m_matU.applyOnTheRight(il, il+1, rot);\n\n    for(Index i=il+1 ; i<iu ; i++)\n    {\n      rot.makeGivens(m_matT.coeffRef(i,i-1), m_matT.coeffRef(i+1,i-1), &m_matT.coeffRef(i,i-1));\n      m_matT.coeffRef(i+1,i-1) = ComplexScalar(0);\n      m_matT.rightCols(m_matT.cols()-i).applyOnTheLeft(i, i+1, rot.adjoint());\n      m_matT.topRows((std::min)(i+2,iu)+1).applyOnTheRight(i, i+1, rot);\n      if(computeU) m_matU.applyOnTheRight(i, i+1, rot);\n    }\n  }\n\n  if(totalIter <= maxIters)\n    m_info = Success;\n  else\n    m_info = NoConvergence;\n\n  m_isInitialized = true;\n  m_matUisUptodate = computeU;\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_COMPLEX_SCHUR_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Eigenvalues/ComplexSchur_LAPACKE.h",
    "content": "/*\n Copyright (c) 2011, Intel Corporation. All rights reserved.\n\n Redistribution and use in source and binary forms, with or without modification,\n are permitted provided that the following conditions are met:\n\n * Redistributions of source code must retain the above copyright notice, this\n   list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright notice,\n   this list of conditions and the following disclaimer in the documentation\n   and/or other materials provided with the distribution.\n * Neither the name of Intel Corporation nor the names of its contributors may\n   be used to endorse or promote products derived from this software without\n   specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n ********************************************************************************\n *   Content : Eigen bindings to LAPACKe\n *    Complex Schur needed to complex unsymmetrical eigenvalues/eigenvectors.\n ********************************************************************************\n*/\n\n#ifndef EIGEN_COMPLEX_SCHUR_LAPACKE_H\n#define EIGEN_COMPLEX_SCHUR_LAPACKE_H\n\nnamespace Eigen { \n\n/** \\internal Specialization for the data types supported by LAPACKe */\n\n#define EIGEN_LAPACKE_SCHUR_COMPLEX(EIGTYPE, LAPACKE_TYPE, LAPACKE_PREFIX, LAPACKE_PREFIX_U, EIGCOLROW, LAPACKE_COLROW) \\\ntemplate<> template<typename InputType> inline \\\nComplexSchur<Matrix<EIGTYPE, Dynamic, Dynamic, EIGCOLROW> >& \\\nComplexSchur<Matrix<EIGTYPE, Dynamic, Dynamic, EIGCOLROW> >::compute(const EigenBase<InputType>& matrix, bool computeU) \\\n{ \\\n  typedef Matrix<EIGTYPE, Dynamic, Dynamic, EIGCOLROW> MatrixType; \\\n  typedef MatrixType::RealScalar RealScalar; \\\n  typedef std::complex<RealScalar> ComplexScalar; \\\n\\\n  eigen_assert(matrix.cols() == matrix.rows()); \\\n\\\n  m_matUisUptodate = false; \\\n  if(matrix.cols() == 1) \\\n  { \\\n    m_matT = matrix.derived().template cast<ComplexScalar>(); \\\n    if(computeU)  m_matU = ComplexMatrixType::Identity(1,1); \\\n      m_info = Success; \\\n      m_isInitialized = true; \\\n      m_matUisUptodate = computeU; \\\n      return *this; \\\n  } \\\n  lapack_int n = internal::convert_index<lapack_int>(matrix.cols()), sdim, info; \\\n  lapack_int matrix_order = LAPACKE_COLROW; \\\n  char jobvs, sort='N'; \\\n  LAPACK_##LAPACKE_PREFIX_U##_SELECT1 select = 0; \\\n  jobvs = (computeU) ? 'V' : 'N'; \\\n  m_matU.resize(n, n); \\\n  lapack_int ldvs  = internal::convert_index<lapack_int>(m_matU.outerStride()); \\\n  m_matT = matrix; \\\n  lapack_int lda = internal::convert_index<lapack_int>(m_matT.outerStride()); \\\n  Matrix<EIGTYPE, Dynamic, Dynamic> w; \\\n  w.resize(n, 1);\\\n  info = LAPACKE_##LAPACKE_PREFIX##gees( matrix_order, jobvs, sort, select, n, (LAPACKE_TYPE*)m_matT.data(), lda, &sdim, (LAPACKE_TYPE*)w.data(), (LAPACKE_TYPE*)m_matU.data(), ldvs ); \\\n  if(info == 0) \\\n    m_info = Success; \\\n  else \\\n    m_info = NoConvergence; \\\n\\\n  m_isInitialized = true; \\\n  m_matUisUptodate = computeU; \\\n  return *this; \\\n\\\n}\n\nEIGEN_LAPACKE_SCHUR_COMPLEX(dcomplex, lapack_complex_double, z, Z, ColMajor, LAPACK_COL_MAJOR)\nEIGEN_LAPACKE_SCHUR_COMPLEX(scomplex, lapack_complex_float,  c, C, ColMajor, LAPACK_COL_MAJOR)\nEIGEN_LAPACKE_SCHUR_COMPLEX(dcomplex, lapack_complex_double, z, Z, RowMajor, LAPACK_ROW_MAJOR)\nEIGEN_LAPACKE_SCHUR_COMPLEX(scomplex, lapack_complex_float,  c, C, RowMajor, LAPACK_ROW_MAJOR)\n\n} // end namespace Eigen\n\n#endif // EIGEN_COMPLEX_SCHUR_LAPACKE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Eigenvalues/EigenSolver.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2010,2012 Jitse Niesen <jitse@maths.leeds.ac.uk>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_EIGENSOLVER_H\n#define EIGEN_EIGENSOLVER_H\n\n#include \"./RealSchur.h\"\n\nnamespace Eigen { \n\n/** \\eigenvalues_module \\ingroup Eigenvalues_Module\n  *\n  *\n  * \\class EigenSolver\n  *\n  * \\brief Computes eigenvalues and eigenvectors of general matrices\n  *\n  * \\tparam _MatrixType the type of the matrix of which we are computing the\n  * eigendecomposition; this is expected to be an instantiation of the Matrix\n  * class template. Currently, only real matrices are supported.\n  *\n  * The eigenvalues and eigenvectors of a matrix \\f$ A \\f$ are scalars\n  * \\f$ \\lambda \\f$ and vectors \\f$ v \\f$ such that \\f$ Av = \\lambda v \\f$.  If\n  * \\f$ D \\f$ is a diagonal matrix with the eigenvalues on the diagonal, and\n  * \\f$ V \\f$ is a matrix with the eigenvectors as its columns, then \\f$ A V =\n  * V D \\f$. The matrix \\f$ V \\f$ is almost always invertible, in which case we\n  * have \\f$ A = V D V^{-1} \\f$. This is called the eigendecomposition.\n  *\n  * The eigenvalues and eigenvectors of a matrix may be complex, even when the\n  * matrix is real. However, we can choose real matrices \\f$ V \\f$ and \\f$ D\n  * \\f$ satisfying \\f$ A V = V D \\f$, just like the eigendecomposition, if the\n  * matrix \\f$ D \\f$ is not required to be diagonal, but if it is allowed to\n  * have blocks of the form\n  * \\f[ \\begin{bmatrix} u & v \\\\ -v & u \\end{bmatrix} \\f]\n  * (where \\f$ u \\f$ and \\f$ v \\f$ are real numbers) on the diagonal.  These\n  * blocks correspond to complex eigenvalue pairs \\f$ u \\pm iv \\f$. We call\n  * this variant of the eigendecomposition the pseudo-eigendecomposition.\n  *\n  * Call the function compute() to compute the eigenvalues and eigenvectors of\n  * a given matrix. Alternatively, you can use the \n  * EigenSolver(const MatrixType&, bool) constructor which computes the\n  * eigenvalues and eigenvectors at construction time. Once the eigenvalue and\n  * eigenvectors are computed, they can be retrieved with the eigenvalues() and\n  * eigenvectors() functions. The pseudoEigenvalueMatrix() and\n  * pseudoEigenvectors() methods allow the construction of the\n  * pseudo-eigendecomposition.\n  *\n  * The documentation for EigenSolver(const MatrixType&, bool) contains an\n  * example of the typical use of this class.\n  *\n  * \\note The implementation is adapted from\n  * <a href=\"http://math.nist.gov/javanumerics/jama/\">JAMA</a> (public domain).\n  * Their code is based on EISPACK.\n  *\n  * \\sa MatrixBase::eigenvalues(), class ComplexEigenSolver, class SelfAdjointEigenSolver\n  */\ntemplate<typename _MatrixType> class EigenSolver\n{\n  public:\n\n    /** \\brief Synonym for the template parameter \\p _MatrixType. */\n    typedef _MatrixType MatrixType;\n\n    enum {\n      RowsAtCompileTime = MatrixType::RowsAtCompileTime,\n      ColsAtCompileTime = MatrixType::ColsAtCompileTime,\n      Options = MatrixType::Options,\n      MaxRowsAtCompileTime = MatrixType::MaxRowsAtCompileTime,\n      MaxColsAtCompileTime = MatrixType::MaxColsAtCompileTime\n    };\n\n    /** \\brief Scalar type for matrices of type #MatrixType. */\n    typedef typename MatrixType::Scalar Scalar;\n    typedef typename NumTraits<Scalar>::Real RealScalar;\n    typedef Eigen::Index Index; ///< \\deprecated since Eigen 3.3\n\n    /** \\brief Complex scalar type for #MatrixType. \n      *\n      * This is \\c std::complex<Scalar> if #Scalar is real (e.g.,\n      * \\c float or \\c double) and just \\c Scalar if #Scalar is\n      * complex.\n      */\n    typedef std::complex<RealScalar> ComplexScalar;\n\n    /** \\brief Type for vector of eigenvalues as returned by eigenvalues(). \n      *\n      * This is a column vector with entries of type #ComplexScalar.\n      * The length of the vector is the size of #MatrixType.\n      */\n    typedef Matrix<ComplexScalar, ColsAtCompileTime, 1, Options & ~RowMajor, MaxColsAtCompileTime, 1> EigenvalueType;\n\n    /** \\brief Type for matrix of eigenvectors as returned by eigenvectors(). \n      *\n      * This is a square matrix with entries of type #ComplexScalar. \n      * The size is the same as the size of #MatrixType.\n      */\n    typedef Matrix<ComplexScalar, RowsAtCompileTime, ColsAtCompileTime, Options, MaxRowsAtCompileTime, MaxColsAtCompileTime> EigenvectorsType;\n\n    /** \\brief Default constructor.\n      *\n      * The default constructor is useful in cases in which the user intends to\n      * perform decompositions via EigenSolver::compute(const MatrixType&, bool).\n      *\n      * \\sa compute() for an example.\n      */\n    EigenSolver() : m_eivec(), m_eivalues(), m_isInitialized(false), m_realSchur(), m_matT(), m_tmp() {}\n\n    /** \\brief Default constructor with memory preallocation\n      *\n      * Like the default constructor but with preallocation of the internal data\n      * according to the specified problem \\a size.\n      * \\sa EigenSolver()\n      */\n    explicit EigenSolver(Index size)\n      : m_eivec(size, size),\n        m_eivalues(size),\n        m_isInitialized(false),\n        m_eigenvectorsOk(false),\n        m_realSchur(size),\n        m_matT(size, size), \n        m_tmp(size)\n    {}\n\n    /** \\brief Constructor; computes eigendecomposition of given matrix. \n      * \n      * \\param[in]  matrix  Square matrix whose eigendecomposition is to be computed.\n      * \\param[in]  computeEigenvectors  If true, both the eigenvectors and the\n      *    eigenvalues are computed; if false, only the eigenvalues are\n      *    computed. \n      *\n      * This constructor calls compute() to compute the eigenvalues\n      * and eigenvectors.\n      *\n      * Example: \\include EigenSolver_EigenSolver_MatrixType.cpp\n      * Output: \\verbinclude EigenSolver_EigenSolver_MatrixType.out\n      *\n      * \\sa compute()\n      */\n    template<typename InputType>\n    explicit EigenSolver(const EigenBase<InputType>& matrix, bool computeEigenvectors = true)\n      : m_eivec(matrix.rows(), matrix.cols()),\n        m_eivalues(matrix.cols()),\n        m_isInitialized(false),\n        m_eigenvectorsOk(false),\n        m_realSchur(matrix.cols()),\n        m_matT(matrix.rows(), matrix.cols()), \n        m_tmp(matrix.cols())\n    {\n      compute(matrix.derived(), computeEigenvectors);\n    }\n\n    /** \\brief Returns the eigenvectors of given matrix. \n      *\n      * \\returns  %Matrix whose columns are the (possibly complex) eigenvectors.\n      *\n      * \\pre Either the constructor \n      * EigenSolver(const MatrixType&,bool) or the member function\n      * compute(const MatrixType&, bool) has been called before, and\n      * \\p computeEigenvectors was set to true (the default).\n      *\n      * Column \\f$ k \\f$ of the returned matrix is an eigenvector corresponding\n      * to eigenvalue number \\f$ k \\f$ as returned by eigenvalues().  The\n      * eigenvectors are normalized to have (Euclidean) norm equal to one. The\n      * matrix returned by this function is the matrix \\f$ V \\f$ in the\n      * eigendecomposition \\f$ A = V D V^{-1} \\f$, if it exists.\n      *\n      * Example: \\include EigenSolver_eigenvectors.cpp\n      * Output: \\verbinclude EigenSolver_eigenvectors.out\n      *\n      * \\sa eigenvalues(), pseudoEigenvectors()\n      */\n    EigenvectorsType eigenvectors() const;\n\n    /** \\brief Returns the pseudo-eigenvectors of given matrix. \n      *\n      * \\returns  Const reference to matrix whose columns are the pseudo-eigenvectors.\n      *\n      * \\pre Either the constructor \n      * EigenSolver(const MatrixType&,bool) or the member function\n      * compute(const MatrixType&, bool) has been called before, and\n      * \\p computeEigenvectors was set to true (the default).\n      *\n      * The real matrix \\f$ V \\f$ returned by this function and the\n      * block-diagonal matrix \\f$ D \\f$ returned by pseudoEigenvalueMatrix()\n      * satisfy \\f$ AV = VD \\f$.\n      *\n      * Example: \\include EigenSolver_pseudoEigenvectors.cpp\n      * Output: \\verbinclude EigenSolver_pseudoEigenvectors.out\n      *\n      * \\sa pseudoEigenvalueMatrix(), eigenvectors()\n      */\n    const MatrixType& pseudoEigenvectors() const\n    {\n      eigen_assert(m_isInitialized && \"EigenSolver is not initialized.\");\n      eigen_assert(m_eigenvectorsOk && \"The eigenvectors have not been computed together with the eigenvalues.\");\n      return m_eivec;\n    }\n\n    /** \\brief Returns the block-diagonal matrix in the pseudo-eigendecomposition.\n      *\n      * \\returns  A block-diagonal matrix.\n      *\n      * \\pre Either the constructor \n      * EigenSolver(const MatrixType&,bool) or the member function\n      * compute(const MatrixType&, bool) has been called before.\n      *\n      * The matrix \\f$ D \\f$ returned by this function is real and\n      * block-diagonal. The blocks on the diagonal are either 1-by-1 or 2-by-2\n      * blocks of the form\n      * \\f$ \\begin{bmatrix} u & v \\\\ -v & u \\end{bmatrix} \\f$.\n      * These blocks are not sorted in any particular order.\n      * The matrix \\f$ D \\f$ and the matrix \\f$ V \\f$ returned by\n      * pseudoEigenvectors() satisfy \\f$ AV = VD \\f$.\n      *\n      * \\sa pseudoEigenvectors() for an example, eigenvalues()\n      */\n    MatrixType pseudoEigenvalueMatrix() const;\n\n    /** \\brief Returns the eigenvalues of given matrix. \n      *\n      * \\returns A const reference to the column vector containing the eigenvalues.\n      *\n      * \\pre Either the constructor \n      * EigenSolver(const MatrixType&,bool) or the member function\n      * compute(const MatrixType&, bool) has been called before.\n      *\n      * The eigenvalues are repeated according to their algebraic multiplicity,\n      * so there are as many eigenvalues as rows in the matrix. The eigenvalues \n      * are not sorted in any particular order.\n      *\n      * Example: \\include EigenSolver_eigenvalues.cpp\n      * Output: \\verbinclude EigenSolver_eigenvalues.out\n      *\n      * \\sa eigenvectors(), pseudoEigenvalueMatrix(),\n      *     MatrixBase::eigenvalues()\n      */\n    const EigenvalueType& eigenvalues() const\n    {\n      eigen_assert(m_isInitialized && \"EigenSolver is not initialized.\");\n      return m_eivalues;\n    }\n\n    /** \\brief Computes eigendecomposition of given matrix. \n      * \n      * \\param[in]  matrix  Square matrix whose eigendecomposition is to be computed.\n      * \\param[in]  computeEigenvectors  If true, both the eigenvectors and the\n      *    eigenvalues are computed; if false, only the eigenvalues are\n      *    computed. \n      * \\returns    Reference to \\c *this\n      *\n      * This function computes the eigenvalues of the real matrix \\p matrix.\n      * The eigenvalues() function can be used to retrieve them.  If \n      * \\p computeEigenvectors is true, then the eigenvectors are also computed\n      * and can be retrieved by calling eigenvectors().\n      *\n      * The matrix is first reduced to real Schur form using the RealSchur\n      * class. The Schur decomposition is then used to compute the eigenvalues\n      * and eigenvectors.\n      *\n      * The cost of the computation is dominated by the cost of the\n      * Schur decomposition, which is very approximately \\f$ 25n^3 \\f$\n      * (where \\f$ n \\f$ is the size of the matrix) if \\p computeEigenvectors \n      * is true, and \\f$ 10n^3 \\f$ if \\p computeEigenvectors is false.\n      *\n      * This method reuses of the allocated data in the EigenSolver object.\n      *\n      * Example: \\include EigenSolver_compute.cpp\n      * Output: \\verbinclude EigenSolver_compute.out\n      */\n    template<typename InputType>\n    EigenSolver& compute(const EigenBase<InputType>& matrix, bool computeEigenvectors = true);\n\n    /** \\returns NumericalIssue if the input contains INF or NaN values or overflow occured. Returns Success otherwise. */\n    ComputationInfo info() const\n    {\n      eigen_assert(m_isInitialized && \"EigenSolver is not initialized.\");\n      return m_info;\n    }\n\n    /** \\brief Sets the maximum number of iterations allowed. */\n    EigenSolver& setMaxIterations(Index maxIters)\n    {\n      m_realSchur.setMaxIterations(maxIters);\n      return *this;\n    }\n\n    /** \\brief Returns the maximum number of iterations. */\n    Index getMaxIterations()\n    {\n      return m_realSchur.getMaxIterations();\n    }\n\n  private:\n    void doComputeEigenvectors();\n\n  protected:\n    \n    static void check_template_parameters()\n    {\n      EIGEN_STATIC_ASSERT_NON_INTEGER(Scalar);\n      EIGEN_STATIC_ASSERT(!NumTraits<Scalar>::IsComplex, NUMERIC_TYPE_MUST_BE_REAL);\n    }\n    \n    MatrixType m_eivec;\n    EigenvalueType m_eivalues;\n    bool m_isInitialized;\n    bool m_eigenvectorsOk;\n    ComputationInfo m_info;\n    RealSchur<MatrixType> m_realSchur;\n    MatrixType m_matT;\n\n    typedef Matrix<Scalar, ColsAtCompileTime, 1, Options & ~RowMajor, MaxColsAtCompileTime, 1> ColumnVectorType;\n    ColumnVectorType m_tmp;\n};\n\ntemplate<typename MatrixType>\nMatrixType EigenSolver<MatrixType>::pseudoEigenvalueMatrix() const\n{\n  eigen_assert(m_isInitialized && \"EigenSolver is not initialized.\");\n  const RealScalar precision = RealScalar(2)*NumTraits<RealScalar>::epsilon();\n  Index n = m_eivalues.rows();\n  MatrixType matD = MatrixType::Zero(n,n);\n  for (Index i=0; i<n; ++i)\n  {\n    if (internal::isMuchSmallerThan(numext::imag(m_eivalues.coeff(i)), numext::real(m_eivalues.coeff(i)), precision))\n      matD.coeffRef(i,i) = numext::real(m_eivalues.coeff(i));\n    else\n    {\n      matD.template block<2,2>(i,i) <<  numext::real(m_eivalues.coeff(i)), numext::imag(m_eivalues.coeff(i)),\n                                       -numext::imag(m_eivalues.coeff(i)), numext::real(m_eivalues.coeff(i));\n      ++i;\n    }\n  }\n  return matD;\n}\n\ntemplate<typename MatrixType>\ntypename EigenSolver<MatrixType>::EigenvectorsType EigenSolver<MatrixType>::eigenvectors() const\n{\n  eigen_assert(m_isInitialized && \"EigenSolver is not initialized.\");\n  eigen_assert(m_eigenvectorsOk && \"The eigenvectors have not been computed together with the eigenvalues.\");\n  const RealScalar precision = RealScalar(2)*NumTraits<RealScalar>::epsilon();\n  Index n = m_eivec.cols();\n  EigenvectorsType matV(n,n);\n  for (Index j=0; j<n; ++j)\n  {\n    if (internal::isMuchSmallerThan(numext::imag(m_eivalues.coeff(j)), numext::real(m_eivalues.coeff(j)), precision) || j+1==n)\n    {\n      // we have a real eigen value\n      matV.col(j) = m_eivec.col(j).template cast<ComplexScalar>();\n      matV.col(j).normalize();\n    }\n    else\n    {\n      // we have a pair of complex eigen values\n      for (Index i=0; i<n; ++i)\n      {\n        matV.coeffRef(i,j)   = ComplexScalar(m_eivec.coeff(i,j),  m_eivec.coeff(i,j+1));\n        matV.coeffRef(i,j+1) = ComplexScalar(m_eivec.coeff(i,j), -m_eivec.coeff(i,j+1));\n      }\n      matV.col(j).normalize();\n      matV.col(j+1).normalize();\n      ++j;\n    }\n  }\n  return matV;\n}\n\ntemplate<typename MatrixType>\ntemplate<typename InputType>\nEigenSolver<MatrixType>& \nEigenSolver<MatrixType>::compute(const EigenBase<InputType>& matrix, bool computeEigenvectors)\n{\n  check_template_parameters();\n  \n  using std::sqrt;\n  using std::abs;\n  using numext::isfinite;\n  eigen_assert(matrix.cols() == matrix.rows());\n\n  // Reduce to real Schur form.\n  m_realSchur.compute(matrix.derived(), computeEigenvectors);\n  \n  m_info = m_realSchur.info();\n\n  if (m_info == Success)\n  {\n    m_matT = m_realSchur.matrixT();\n    if (computeEigenvectors)\n      m_eivec = m_realSchur.matrixU();\n  \n    // Compute eigenvalues from matT\n    m_eivalues.resize(matrix.cols());\n    Index i = 0;\n    while (i < matrix.cols()) \n    {\n      if (i == matrix.cols() - 1 || m_matT.coeff(i+1, i) == Scalar(0)) \n      {\n        m_eivalues.coeffRef(i) = m_matT.coeff(i, i);\n        if(!(isfinite)(m_eivalues.coeffRef(i)))\n        {\n          m_isInitialized = true;\n          m_eigenvectorsOk = false;\n          m_info = NumericalIssue;\n          return *this;\n        }\n        ++i;\n      }\n      else\n      {\n        Scalar p = Scalar(0.5) * (m_matT.coeff(i, i) - m_matT.coeff(i+1, i+1));\n        Scalar z;\n        // Compute z = sqrt(abs(p * p + m_matT.coeff(i+1, i) * m_matT.coeff(i, i+1)));\n        // without overflow\n        {\n          Scalar t0 = m_matT.coeff(i+1, i);\n          Scalar t1 = m_matT.coeff(i, i+1);\n          Scalar maxval = numext::maxi<Scalar>(abs(p),numext::maxi<Scalar>(abs(t0),abs(t1)));\n          t0 /= maxval;\n          t1 /= maxval;\n          Scalar p0 = p/maxval;\n          z = maxval * sqrt(abs(p0 * p0 + t0 * t1));\n        }\n        \n        m_eivalues.coeffRef(i)   = ComplexScalar(m_matT.coeff(i+1, i+1) + p, z);\n        m_eivalues.coeffRef(i+1) = ComplexScalar(m_matT.coeff(i+1, i+1) + p, -z);\n        if(!((isfinite)(m_eivalues.coeffRef(i)) && (isfinite)(m_eivalues.coeffRef(i+1))))\n        {\n          m_isInitialized = true;\n          m_eigenvectorsOk = false;\n          m_info = NumericalIssue;\n          return *this;\n        }\n        i += 2;\n      }\n    }\n    \n    // Compute eigenvectors.\n    if (computeEigenvectors)\n      doComputeEigenvectors();\n  }\n\n  m_isInitialized = true;\n  m_eigenvectorsOk = computeEigenvectors;\n\n  return *this;\n}\n\n\ntemplate<typename MatrixType>\nvoid EigenSolver<MatrixType>::doComputeEigenvectors()\n{\n  using std::abs;\n  const Index size = m_eivec.cols();\n  const Scalar eps = NumTraits<Scalar>::epsilon();\n\n  // inefficient! this is already computed in RealSchur\n  Scalar norm(0);\n  for (Index j = 0; j < size; ++j)\n  {\n    norm += m_matT.row(j).segment((std::max)(j-1,Index(0)), size-(std::max)(j-1,Index(0))).cwiseAbs().sum();\n  }\n  \n  // Backsubstitute to find vectors of upper triangular form\n  if (norm == Scalar(0))\n  {\n    return;\n  }\n\n  for (Index n = size-1; n >= 0; n--)\n  {\n    Scalar p = m_eivalues.coeff(n).real();\n    Scalar q = m_eivalues.coeff(n).imag();\n\n    // Scalar vector\n    if (q == Scalar(0))\n    {\n      Scalar lastr(0), lastw(0);\n      Index l = n;\n\n      m_matT.coeffRef(n,n) = Scalar(1);\n      for (Index i = n-1; i >= 0; i--)\n      {\n        Scalar w = m_matT.coeff(i,i) - p;\n        Scalar r = m_matT.row(i).segment(l,n-l+1).dot(m_matT.col(n).segment(l, n-l+1));\n\n        if (m_eivalues.coeff(i).imag() < Scalar(0))\n        {\n          lastw = w;\n          lastr = r;\n        }\n        else\n        {\n          l = i;\n          if (m_eivalues.coeff(i).imag() == Scalar(0))\n          {\n            if (w != Scalar(0))\n              m_matT.coeffRef(i,n) = -r / w;\n            else\n              m_matT.coeffRef(i,n) = -r / (eps * norm);\n          }\n          else // Solve real equations\n          {\n            Scalar x = m_matT.coeff(i,i+1);\n            Scalar y = m_matT.coeff(i+1,i);\n            Scalar denom = (m_eivalues.coeff(i).real() - p) * (m_eivalues.coeff(i).real() - p) + m_eivalues.coeff(i).imag() * m_eivalues.coeff(i).imag();\n            Scalar t = (x * lastr - lastw * r) / denom;\n            m_matT.coeffRef(i,n) = t;\n            if (abs(x) > abs(lastw))\n              m_matT.coeffRef(i+1,n) = (-r - w * t) / x;\n            else\n              m_matT.coeffRef(i+1,n) = (-lastr - y * t) / lastw;\n          }\n\n          // Overflow control\n          Scalar t = abs(m_matT.coeff(i,n));\n          if ((eps * t) * t > Scalar(1))\n            m_matT.col(n).tail(size-i) /= t;\n        }\n      }\n    }\n    else if (q < Scalar(0) && n > 0) // Complex vector\n    {\n      Scalar lastra(0), lastsa(0), lastw(0);\n      Index l = n-1;\n\n      // Last vector component imaginary so matrix is triangular\n      if (abs(m_matT.coeff(n,n-1)) > abs(m_matT.coeff(n-1,n)))\n      {\n        m_matT.coeffRef(n-1,n-1) = q / m_matT.coeff(n,n-1);\n        m_matT.coeffRef(n-1,n) = -(m_matT.coeff(n,n) - p) / m_matT.coeff(n,n-1);\n      }\n      else\n      {\n        ComplexScalar cc = ComplexScalar(Scalar(0),-m_matT.coeff(n-1,n)) / ComplexScalar(m_matT.coeff(n-1,n-1)-p,q);\n        m_matT.coeffRef(n-1,n-1) = numext::real(cc);\n        m_matT.coeffRef(n-1,n) = numext::imag(cc);\n      }\n      m_matT.coeffRef(n,n-1) = Scalar(0);\n      m_matT.coeffRef(n,n) = Scalar(1);\n      for (Index i = n-2; i >= 0; i--)\n      {\n        Scalar ra = m_matT.row(i).segment(l, n-l+1).dot(m_matT.col(n-1).segment(l, n-l+1));\n        Scalar sa = m_matT.row(i).segment(l, n-l+1).dot(m_matT.col(n).segment(l, n-l+1));\n        Scalar w = m_matT.coeff(i,i) - p;\n\n        if (m_eivalues.coeff(i).imag() < Scalar(0))\n        {\n          lastw = w;\n          lastra = ra;\n          lastsa = sa;\n        }\n        else\n        {\n          l = i;\n          if (m_eivalues.coeff(i).imag() == RealScalar(0))\n          {\n            ComplexScalar cc = ComplexScalar(-ra,-sa) / ComplexScalar(w,q);\n            m_matT.coeffRef(i,n-1) = numext::real(cc);\n            m_matT.coeffRef(i,n) = numext::imag(cc);\n          }\n          else\n          {\n            // Solve complex equations\n            Scalar x = m_matT.coeff(i,i+1);\n            Scalar y = m_matT.coeff(i+1,i);\n            Scalar vr = (m_eivalues.coeff(i).real() - p) * (m_eivalues.coeff(i).real() - p) + m_eivalues.coeff(i).imag() * m_eivalues.coeff(i).imag() - q * q;\n            Scalar vi = (m_eivalues.coeff(i).real() - p) * Scalar(2) * q;\n            if ((vr == Scalar(0)) && (vi == Scalar(0)))\n              vr = eps * norm * (abs(w) + abs(q) + abs(x) + abs(y) + abs(lastw));\n\n            ComplexScalar cc = ComplexScalar(x*lastra-lastw*ra+q*sa,x*lastsa-lastw*sa-q*ra) / ComplexScalar(vr,vi);\n            m_matT.coeffRef(i,n-1) = numext::real(cc);\n            m_matT.coeffRef(i,n) = numext::imag(cc);\n            if (abs(x) > (abs(lastw) + abs(q)))\n            {\n              m_matT.coeffRef(i+1,n-1) = (-ra - w * m_matT.coeff(i,n-1) + q * m_matT.coeff(i,n)) / x;\n              m_matT.coeffRef(i+1,n) = (-sa - w * m_matT.coeff(i,n) - q * m_matT.coeff(i,n-1)) / x;\n            }\n            else\n            {\n              cc = ComplexScalar(-lastra-y*m_matT.coeff(i,n-1),-lastsa-y*m_matT.coeff(i,n)) / ComplexScalar(lastw,q);\n              m_matT.coeffRef(i+1,n-1) = numext::real(cc);\n              m_matT.coeffRef(i+1,n) = numext::imag(cc);\n            }\n          }\n\n          // Overflow control\n          Scalar t = numext::maxi<Scalar>(abs(m_matT.coeff(i,n-1)),abs(m_matT.coeff(i,n)));\n          if ((eps * t) * t > Scalar(1))\n            m_matT.block(i, n-1, size-i, 2) /= t;\n\n        }\n      }\n      \n      // We handled a pair of complex conjugate eigenvalues, so need to skip them both\n      n--;\n    }\n    else\n    {\n      eigen_assert(0 && \"Internal bug in EigenSolver (INF or NaN has not been detected)\"); // this should not happen\n    }\n  }\n\n  // Back transformation to get eigenvectors of original matrix\n  for (Index j = size-1; j >= 0; j--)\n  {\n    m_tmp.noalias() = m_eivec.leftCols(j+1) * m_matT.col(j).segment(0, j+1);\n    m_eivec.col(j) = m_tmp;\n  }\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_EIGENSOLVER_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Eigenvalues/GeneralizedEigenSolver.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2012-2016 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2010,2012 Jitse Niesen <jitse@maths.leeds.ac.uk>\n// Copyright (C) 2016 Tobias Wood <tobias@spinicist.org.uk>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_GENERALIZEDEIGENSOLVER_H\n#define EIGEN_GENERALIZEDEIGENSOLVER_H\n\n#include \"./RealQZ.h\"\n\nnamespace Eigen { \n\n/** \\eigenvalues_module \\ingroup Eigenvalues_Module\n  *\n  *\n  * \\class GeneralizedEigenSolver\n  *\n  * \\brief Computes the generalized eigenvalues and eigenvectors of a pair of general matrices\n  *\n  * \\tparam _MatrixType the type of the matrices of which we are computing the\n  * eigen-decomposition; this is expected to be an instantiation of the Matrix\n  * class template. Currently, only real matrices are supported.\n  *\n  * The generalized eigenvalues and eigenvectors of a matrix pair \\f$ A \\f$ and \\f$ B \\f$ are scalars\n  * \\f$ \\lambda \\f$ and vectors \\f$ v \\f$ such that \\f$ Av = \\lambda Bv \\f$.  If\n  * \\f$ D \\f$ is a diagonal matrix with the eigenvalues on the diagonal, and\n  * \\f$ V \\f$ is a matrix with the eigenvectors as its columns, then \\f$ A V =\n  * B V D \\f$. The matrix \\f$ V \\f$ is almost always invertible, in which case we\n  * have \\f$ A = B V D V^{-1} \\f$. This is called the generalized eigen-decomposition.\n  *\n  * The generalized eigenvalues and eigenvectors of a matrix pair may be complex, even when the\n  * matrices are real. Moreover, the generalized eigenvalue might be infinite if the matrix B is\n  * singular. To workaround this difficulty, the eigenvalues are provided as a pair of complex \\f$ \\alpha \\f$\n  * and real \\f$ \\beta \\f$ such that: \\f$ \\lambda_i = \\alpha_i / \\beta_i \\f$. If \\f$ \\beta_i \\f$ is (nearly) zero,\n  * then one can consider the well defined left eigenvalue \\f$ \\mu = \\beta_i / \\alpha_i\\f$ such that:\n  * \\f$ \\mu_i A v_i = B v_i \\f$, or even \\f$ \\mu_i u_i^T A  = u_i^T B \\f$ where \\f$ u_i \\f$ is\n  * called the left eigenvector.\n  *\n  * Call the function compute() to compute the generalized eigenvalues and eigenvectors of\n  * a given matrix pair. Alternatively, you can use the\n  * GeneralizedEigenSolver(const MatrixType&, const MatrixType&, bool) constructor which computes the\n  * eigenvalues and eigenvectors at construction time. Once the eigenvalue and\n  * eigenvectors are computed, they can be retrieved with the eigenvalues() and\n  * eigenvectors() functions.\n  *\n  * Here is an usage example of this class:\n  * Example: \\include GeneralizedEigenSolver.cpp\n  * Output: \\verbinclude GeneralizedEigenSolver.out\n  *\n  * \\sa MatrixBase::eigenvalues(), class ComplexEigenSolver, class SelfAdjointEigenSolver\n  */\ntemplate<typename _MatrixType> class GeneralizedEigenSolver\n{\n  public:\n\n    /** \\brief Synonym for the template parameter \\p _MatrixType. */\n    typedef _MatrixType MatrixType;\n\n    enum {\n      RowsAtCompileTime = MatrixType::RowsAtCompileTime,\n      ColsAtCompileTime = MatrixType::ColsAtCompileTime,\n      Options = MatrixType::Options,\n      MaxRowsAtCompileTime = MatrixType::MaxRowsAtCompileTime,\n      MaxColsAtCompileTime = MatrixType::MaxColsAtCompileTime\n    };\n\n    /** \\brief Scalar type for matrices of type #MatrixType. */\n    typedef typename MatrixType::Scalar Scalar;\n    typedef typename NumTraits<Scalar>::Real RealScalar;\n    typedef Eigen::Index Index; ///< \\deprecated since Eigen 3.3\n\n    /** \\brief Complex scalar type for #MatrixType. \n      *\n      * This is \\c std::complex<Scalar> if #Scalar is real (e.g.,\n      * \\c float or \\c double) and just \\c Scalar if #Scalar is\n      * complex.\n      */\n    typedef std::complex<RealScalar> ComplexScalar;\n\n    /** \\brief Type for vector of real scalar values eigenvalues as returned by betas().\n      *\n      * This is a column vector with entries of type #Scalar.\n      * The length of the vector is the size of #MatrixType.\n      */\n    typedef Matrix<Scalar, ColsAtCompileTime, 1, Options & ~RowMajor, MaxColsAtCompileTime, 1> VectorType;\n\n    /** \\brief Type for vector of complex scalar values eigenvalues as returned by alphas().\n      *\n      * This is a column vector with entries of type #ComplexScalar.\n      * The length of the vector is the size of #MatrixType.\n      */\n    typedef Matrix<ComplexScalar, ColsAtCompileTime, 1, Options & ~RowMajor, MaxColsAtCompileTime, 1> ComplexVectorType;\n\n    /** \\brief Expression type for the eigenvalues as returned by eigenvalues().\n      */\n    typedef CwiseBinaryOp<internal::scalar_quotient_op<ComplexScalar,Scalar>,ComplexVectorType,VectorType> EigenvalueType;\n\n    /** \\brief Type for matrix of eigenvectors as returned by eigenvectors(). \n      *\n      * This is a square matrix with entries of type #ComplexScalar. \n      * The size is the same as the size of #MatrixType.\n      */\n    typedef Matrix<ComplexScalar, RowsAtCompileTime, ColsAtCompileTime, Options, MaxRowsAtCompileTime, MaxColsAtCompileTime> EigenvectorsType;\n\n    /** \\brief Default constructor.\n      *\n      * The default constructor is useful in cases in which the user intends to\n      * perform decompositions via EigenSolver::compute(const MatrixType&, bool).\n      *\n      * \\sa compute() for an example.\n      */\n    GeneralizedEigenSolver()\n      : m_eivec(),\n        m_alphas(),\n        m_betas(),\n        m_valuesOkay(false),\n        m_vectorsOkay(false),\n        m_realQZ()\n    {}\n\n    /** \\brief Default constructor with memory preallocation\n      *\n      * Like the default constructor but with preallocation of the internal data\n      * according to the specified problem \\a size.\n      * \\sa GeneralizedEigenSolver()\n      */\n    explicit GeneralizedEigenSolver(Index size)\n      : m_eivec(size, size),\n        m_alphas(size),\n        m_betas(size),\n        m_valuesOkay(false),\n        m_vectorsOkay(false),\n        m_realQZ(size),\n        m_tmp(size)\n    {}\n\n    /** \\brief Constructor; computes the generalized eigendecomposition of given matrix pair.\n      * \n      * \\param[in]  A  Square matrix whose eigendecomposition is to be computed.\n      * \\param[in]  B  Square matrix whose eigendecomposition is to be computed.\n      * \\param[in]  computeEigenvectors  If true, both the eigenvectors and the\n      *    eigenvalues are computed; if false, only the eigenvalues are computed.\n      *\n      * This constructor calls compute() to compute the generalized eigenvalues\n      * and eigenvectors.\n      *\n      * \\sa compute()\n      */\n    GeneralizedEigenSolver(const MatrixType& A, const MatrixType& B, bool computeEigenvectors = true)\n      : m_eivec(A.rows(), A.cols()),\n        m_alphas(A.cols()),\n        m_betas(A.cols()),\n        m_valuesOkay(false),\n        m_vectorsOkay(false),\n        m_realQZ(A.cols()),\n        m_tmp(A.cols())\n    {\n      compute(A, B, computeEigenvectors);\n    }\n\n    /* \\brief Returns the computed generalized eigenvectors.\n      *\n      * \\returns  %Matrix whose columns are the (possibly complex) right eigenvectors.\n      * i.e. the eigenvectors that solve (A - l*B)x = 0. The ordering matches the eigenvalues.\n      *\n      * \\pre Either the constructor \n      * GeneralizedEigenSolver(const MatrixType&,const MatrixType&, bool) or the member function\n      * compute(const MatrixType&, const MatrixType& bool) has been called before, and\n      * \\p computeEigenvectors was set to true (the default).\n      *\n      * \\sa eigenvalues()\n      */\n    EigenvectorsType eigenvectors() const {\n      eigen_assert(m_vectorsOkay && \"Eigenvectors for GeneralizedEigenSolver were not calculated.\");\n      return m_eivec;\n    }\n\n    /** \\brief Returns an expression of the computed generalized eigenvalues.\n      *\n      * \\returns An expression of the column vector containing the eigenvalues.\n      *\n      * It is a shortcut for \\code this->alphas().cwiseQuotient(this->betas()); \\endcode\n      * Not that betas might contain zeros. It is therefore not recommended to use this function,\n      * but rather directly deal with the alphas and betas vectors.\n      *\n      * \\pre Either the constructor \n      * GeneralizedEigenSolver(const MatrixType&,const MatrixType&,bool) or the member function\n      * compute(const MatrixType&,const MatrixType&,bool) has been called before.\n      *\n      * The eigenvalues are repeated according to their algebraic multiplicity,\n      * so there are as many eigenvalues as rows in the matrix. The eigenvalues \n      * are not sorted in any particular order.\n      *\n      * \\sa alphas(), betas(), eigenvectors()\n      */\n    EigenvalueType eigenvalues() const\n    {\n      eigen_assert(m_valuesOkay && \"GeneralizedEigenSolver is not initialized.\");\n      return EigenvalueType(m_alphas,m_betas);\n    }\n\n    /** \\returns A const reference to the vectors containing the alpha values\n      *\n      * This vector permits to reconstruct the j-th eigenvalues as alphas(i)/betas(j).\n      *\n      * \\sa betas(), eigenvalues() */\n    ComplexVectorType alphas() const\n    {\n      eigen_assert(m_valuesOkay && \"GeneralizedEigenSolver is not initialized.\");\n      return m_alphas;\n    }\n\n    /** \\returns A const reference to the vectors containing the beta values\n      *\n      * This vector permits to reconstruct the j-th eigenvalues as alphas(i)/betas(j).\n      *\n      * \\sa alphas(), eigenvalues() */\n    VectorType betas() const\n    {\n      eigen_assert(m_valuesOkay && \"GeneralizedEigenSolver is not initialized.\");\n      return m_betas;\n    }\n\n    /** \\brief Computes generalized eigendecomposition of given matrix.\n      * \n      * \\param[in]  A  Square matrix whose eigendecomposition is to be computed.\n      * \\param[in]  B  Square matrix whose eigendecomposition is to be computed.\n      * \\param[in]  computeEigenvectors  If true, both the eigenvectors and the\n      *    eigenvalues are computed; if false, only the eigenvalues are\n      *    computed. \n      * \\returns    Reference to \\c *this\n      *\n      * This function computes the eigenvalues of the real matrix \\p matrix.\n      * The eigenvalues() function can be used to retrieve them.  If \n      * \\p computeEigenvectors is true, then the eigenvectors are also computed\n      * and can be retrieved by calling eigenvectors().\n      *\n      * The matrix is first reduced to real generalized Schur form using the RealQZ\n      * class. The generalized Schur decomposition is then used to compute the eigenvalues\n      * and eigenvectors.\n      *\n      * The cost of the computation is dominated by the cost of the\n      * generalized Schur decomposition.\n      *\n      * This method reuses of the allocated data in the GeneralizedEigenSolver object.\n      */\n    GeneralizedEigenSolver& compute(const MatrixType& A, const MatrixType& B, bool computeEigenvectors = true);\n\n    ComputationInfo info() const\n    {\n      eigen_assert(m_valuesOkay && \"EigenSolver is not initialized.\");\n      return m_realQZ.info();\n    }\n\n    /** Sets the maximal number of iterations allowed.\n    */\n    GeneralizedEigenSolver& setMaxIterations(Index maxIters)\n    {\n      m_realQZ.setMaxIterations(maxIters);\n      return *this;\n    }\n\n  protected:\n    \n    static void check_template_parameters()\n    {\n      EIGEN_STATIC_ASSERT_NON_INTEGER(Scalar);\n      EIGEN_STATIC_ASSERT(!NumTraits<Scalar>::IsComplex, NUMERIC_TYPE_MUST_BE_REAL);\n    }\n    \n    EigenvectorsType m_eivec;\n    ComplexVectorType m_alphas;\n    VectorType m_betas;\n    bool m_valuesOkay, m_vectorsOkay;\n    RealQZ<MatrixType> m_realQZ;\n    ComplexVectorType m_tmp;\n};\n\ntemplate<typename MatrixType>\nGeneralizedEigenSolver<MatrixType>&\nGeneralizedEigenSolver<MatrixType>::compute(const MatrixType& A, const MatrixType& B, bool computeEigenvectors)\n{\n  check_template_parameters();\n  \n  using std::sqrt;\n  using std::abs;\n  eigen_assert(A.cols() == A.rows() && B.cols() == A.rows() && B.cols() == B.rows());\n  Index size = A.cols();\n  m_valuesOkay = false;\n  m_vectorsOkay = false;\n  // Reduce to generalized real Schur form:\n  // A = Q S Z and B = Q T Z\n  m_realQZ.compute(A, B, computeEigenvectors);\n  if (m_realQZ.info() == Success)\n  {\n    // Resize storage\n    m_alphas.resize(size);\n    m_betas.resize(size);\n    if (computeEigenvectors)\n    {\n      m_eivec.resize(size,size);\n      m_tmp.resize(size);\n    }\n\n    // Aliases:\n    Map<VectorType> v(reinterpret_cast<Scalar*>(m_tmp.data()), size);\n    ComplexVectorType &cv = m_tmp;\n    const MatrixType &mZ = m_realQZ.matrixZ();\n    const MatrixType &mS = m_realQZ.matrixS();\n    const MatrixType &mT = m_realQZ.matrixT();\n\n    Index i = 0;\n    while (i < size)\n    {\n      if (i == size - 1 || mS.coeff(i+1, i) == Scalar(0))\n      {\n        // Real eigenvalue\n        m_alphas.coeffRef(i) = mS.diagonal().coeff(i);\n        m_betas.coeffRef(i)  = mT.diagonal().coeff(i);\n        if (computeEigenvectors)\n        {\n          v.setConstant(Scalar(0.0));\n          v.coeffRef(i) = Scalar(1.0);\n          // For singular eigenvalues do nothing more\n          if(abs(m_betas.coeffRef(i)) >= (std::numeric_limits<RealScalar>::min)())\n          {\n            // Non-singular eigenvalue\n            const Scalar alpha = real(m_alphas.coeffRef(i));\n            const Scalar beta = m_betas.coeffRef(i);\n            for (Index j = i-1; j >= 0; j--)\n            {\n              const Index st = j+1;\n              const Index sz = i-j;\n              if (j > 0 && mS.coeff(j, j-1) != Scalar(0))\n              {\n                // 2x2 block\n                Matrix<Scalar, 2, 1> rhs = (alpha*mT.template block<2,Dynamic>(j-1,st,2,sz) - beta*mS.template block<2,Dynamic>(j-1,st,2,sz)) .lazyProduct( v.segment(st,sz) );\n                Matrix<Scalar, 2, 2> lhs = beta * mS.template block<2,2>(j-1,j-1) - alpha * mT.template block<2,2>(j-1,j-1);\n                v.template segment<2>(j-1) = lhs.partialPivLu().solve(rhs);\n                j--;\n              }\n              else\n              {\n                v.coeffRef(j) = -v.segment(st,sz).transpose().cwiseProduct(beta*mS.block(j,st,1,sz) - alpha*mT.block(j,st,1,sz)).sum() / (beta*mS.coeffRef(j,j) - alpha*mT.coeffRef(j,j));\n              }\n            }\n          }\n          m_eivec.col(i).real().noalias() = mZ.transpose() * v;\n          m_eivec.col(i).real().normalize();\n          m_eivec.col(i).imag().setConstant(0);\n        }\n        ++i;\n      }\n      else\n      {\n        // We need to extract the generalized eigenvalues of the pair of a general 2x2 block S and a positive diagonal 2x2 block T\n        // Then taking beta=T_00*T_11, we can avoid any division, and alpha is the eigenvalues of A = (U^-1 * S * U) * diag(T_11,T_00):\n\n        // T =  [a 0]\n        //      [0 b]\n        RealScalar a = mT.diagonal().coeff(i),\n                   b = mT.diagonal().coeff(i+1);\n        const RealScalar beta = m_betas.coeffRef(i) = m_betas.coeffRef(i+1) = a*b;\n\n        // ^^ NOTE: using diagonal()(i) instead of coeff(i,i) workarounds a MSVC bug.\n        Matrix<RealScalar,2,2> S2 = mS.template block<2,2>(i,i) * Matrix<Scalar,2,1>(b,a).asDiagonal();\n\n        Scalar p = Scalar(0.5) * (S2.coeff(0,0) - S2.coeff(1,1));\n        Scalar z = sqrt(abs(p * p + S2.coeff(1,0) * S2.coeff(0,1)));\n        const ComplexScalar alpha = ComplexScalar(S2.coeff(1,1) + p, (beta > 0) ? z : -z);\n        m_alphas.coeffRef(i)   = conj(alpha);\n        m_alphas.coeffRef(i+1) = alpha;\n\n        if (computeEigenvectors) {\n          // Compute eigenvector in position (i+1) and then position (i) is just the conjugate\n          cv.setZero();\n          cv.coeffRef(i+1) = Scalar(1.0);\n          // here, the \"static_cast\" workaound expression template issues.\n          cv.coeffRef(i) = -(static_cast<Scalar>(beta*mS.coeffRef(i,i+1)) - alpha*mT.coeffRef(i,i+1))\n                          / (static_cast<Scalar>(beta*mS.coeffRef(i,i))   - alpha*mT.coeffRef(i,i));\n          for (Index j = i-1; j >= 0; j--)\n          {\n            const Index st = j+1;\n            const Index sz = i+1-j;\n            if (j > 0 && mS.coeff(j, j-1) != Scalar(0))\n            {\n              // 2x2 block\n              Matrix<ComplexScalar, 2, 1> rhs = (alpha*mT.template block<2,Dynamic>(j-1,st,2,sz) - beta*mS.template block<2,Dynamic>(j-1,st,2,sz)) .lazyProduct( cv.segment(st,sz) );\n              Matrix<ComplexScalar, 2, 2> lhs = beta * mS.template block<2,2>(j-1,j-1) - alpha * mT.template block<2,2>(j-1,j-1);\n              cv.template segment<2>(j-1) = lhs.partialPivLu().solve(rhs);\n              j--;\n            } else {\n              cv.coeffRef(j) =  cv.segment(st,sz).transpose().cwiseProduct(beta*mS.block(j,st,1,sz) - alpha*mT.block(j,st,1,sz)).sum()\n                              / (alpha*mT.coeffRef(j,j) - static_cast<Scalar>(beta*mS.coeffRef(j,j)));\n            }\n          }\n          m_eivec.col(i+1).noalias() = (mZ.transpose() * cv);\n          m_eivec.col(i+1).normalize();\n          m_eivec.col(i) = m_eivec.col(i+1).conjugate();\n        }\n        i += 2;\n      }\n    }\n\n    m_valuesOkay = true;\n    m_vectorsOkay = computeEigenvectors;\n  }\n  return *this;\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_GENERALIZEDEIGENSOLVER_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Eigenvalues/GeneralizedSelfAdjointEigenSolver.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2010 Jitse Niesen <jitse@maths.leeds.ac.uk>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_GENERALIZEDSELFADJOINTEIGENSOLVER_H\n#define EIGEN_GENERALIZEDSELFADJOINTEIGENSOLVER_H\n\n#include \"./Tridiagonalization.h\"\n\nnamespace Eigen { \n\n/** \\eigenvalues_module \\ingroup Eigenvalues_Module\n  *\n  *\n  * \\class GeneralizedSelfAdjointEigenSolver\n  *\n  * \\brief Computes eigenvalues and eigenvectors of the generalized selfadjoint eigen problem\n  *\n  * \\tparam _MatrixType the type of the matrix of which we are computing the\n  * eigendecomposition; this is expected to be an instantiation of the Matrix\n  * class template.\n  *\n  * This class solves the generalized eigenvalue problem\n  * \\f$ Av = \\lambda Bv \\f$. In this case, the matrix \\f$ A \\f$ should be\n  * selfadjoint and the matrix \\f$ B \\f$ should be positive definite.\n  *\n  * Only the \\b lower \\b triangular \\b part of the input matrix is referenced.\n  *\n  * Call the function compute() to compute the eigenvalues and eigenvectors of\n  * a given matrix. Alternatively, you can use the\n  * GeneralizedSelfAdjointEigenSolver(const MatrixType&, const MatrixType&, int)\n  * constructor which computes the eigenvalues and eigenvectors at construction time.\n  * Once the eigenvalue and eigenvectors are computed, they can be retrieved with the eigenvalues()\n  * and eigenvectors() functions.\n  *\n  * The documentation for GeneralizedSelfAdjointEigenSolver(const MatrixType&, const MatrixType&, int)\n  * contains an example of the typical use of this class.\n  *\n  * \\sa class SelfAdjointEigenSolver, class EigenSolver, class ComplexEigenSolver\n  */\ntemplate<typename _MatrixType>\nclass GeneralizedSelfAdjointEigenSolver : public SelfAdjointEigenSolver<_MatrixType>\n{\n    typedef SelfAdjointEigenSolver<_MatrixType> Base;\n  public:\n\n    typedef _MatrixType MatrixType;\n\n    /** \\brief Default constructor for fixed-size matrices.\n      *\n      * The default constructor is useful in cases in which the user intends to\n      * perform decompositions via compute(). This constructor\n      * can only be used if \\p _MatrixType is a fixed-size matrix; use\n      * GeneralizedSelfAdjointEigenSolver(Index) for dynamic-size matrices.\n      */\n    GeneralizedSelfAdjointEigenSolver() : Base() {}\n\n    /** \\brief Constructor, pre-allocates memory for dynamic-size matrices.\n      *\n      * \\param [in]  size  Positive integer, size of the matrix whose\n      * eigenvalues and eigenvectors will be computed.\n      *\n      * This constructor is useful for dynamic-size matrices, when the user\n      * intends to perform decompositions via compute(). The \\p size\n      * parameter is only used as a hint. It is not an error to give a wrong\n      * \\p size, but it may impair performance.\n      *\n      * \\sa compute() for an example\n      */\n    explicit GeneralizedSelfAdjointEigenSolver(Index size)\n        : Base(size)\n    {}\n\n    /** \\brief Constructor; computes generalized eigendecomposition of given matrix pencil.\n      *\n      * \\param[in]  matA  Selfadjoint matrix in matrix pencil.\n      *                   Only the lower triangular part of the matrix is referenced.\n      * \\param[in]  matB  Positive-definite matrix in matrix pencil.\n      *                   Only the lower triangular part of the matrix is referenced.\n      * \\param[in]  options A or-ed set of flags {#ComputeEigenvectors,#EigenvaluesOnly} | {#Ax_lBx,#ABx_lx,#BAx_lx}.\n      *                     Default is #ComputeEigenvectors|#Ax_lBx.\n      *\n      * This constructor calls compute(const MatrixType&, const MatrixType&, int)\n      * to compute the eigenvalues and (if requested) the eigenvectors of the\n      * generalized eigenproblem \\f$ Ax = \\lambda B x \\f$ with \\a matA the\n      * selfadjoint matrix \\f$ A \\f$ and \\a matB the positive definite matrix\n      * \\f$ B \\f$. Each eigenvector \\f$ x \\f$ satisfies the property\n      * \\f$ x^* B x = 1 \\f$. The eigenvectors are computed if\n      * \\a options contains ComputeEigenvectors.\n      *\n      * In addition, the two following variants can be solved via \\p options:\n      * - \\c ABx_lx: \\f$ ABx = \\lambda x \\f$\n      * - \\c BAx_lx: \\f$ BAx = \\lambda x \\f$\n      *\n      * Example: \\include SelfAdjointEigenSolver_SelfAdjointEigenSolver_MatrixType2.cpp\n      * Output: \\verbinclude SelfAdjointEigenSolver_SelfAdjointEigenSolver_MatrixType2.out\n      *\n      * \\sa compute(const MatrixType&, const MatrixType&, int)\n      */\n    GeneralizedSelfAdjointEigenSolver(const MatrixType& matA, const MatrixType& matB,\n                                      int options = ComputeEigenvectors|Ax_lBx)\n      : Base(matA.cols())\n    {\n      compute(matA, matB, options);\n    }\n\n    /** \\brief Computes generalized eigendecomposition of given matrix pencil.\n      *\n      * \\param[in]  matA  Selfadjoint matrix in matrix pencil.\n      *                   Only the lower triangular part of the matrix is referenced.\n      * \\param[in]  matB  Positive-definite matrix in matrix pencil.\n      *                   Only the lower triangular part of the matrix is referenced.\n      * \\param[in]  options A or-ed set of flags {#ComputeEigenvectors,#EigenvaluesOnly} | {#Ax_lBx,#ABx_lx,#BAx_lx}.\n      *                     Default is #ComputeEigenvectors|#Ax_lBx.\n      *\n      * \\returns    Reference to \\c *this\n      *\n      * Accoring to \\p options, this function computes eigenvalues and (if requested)\n      * the eigenvectors of one of the following three generalized eigenproblems:\n      * - \\c Ax_lBx: \\f$ Ax = \\lambda B x \\f$\n      * - \\c ABx_lx: \\f$ ABx = \\lambda x \\f$\n      * - \\c BAx_lx: \\f$ BAx = \\lambda x \\f$\n      * with \\a matA the selfadjoint matrix \\f$ A \\f$ and \\a matB the positive definite\n      * matrix \\f$ B \\f$.\n      * In addition, each eigenvector \\f$ x \\f$ satisfies the property \\f$ x^* B x = 1 \\f$.\n      *\n      * The eigenvalues() function can be used to retrieve\n      * the eigenvalues. If \\p options contains ComputeEigenvectors, then the\n      * eigenvectors are also computed and can be retrieved by calling\n      * eigenvectors().\n      *\n      * The implementation uses LLT to compute the Cholesky decomposition\n      * \\f$ B = LL^* \\f$ and computes the classical eigendecomposition\n      * of the selfadjoint matrix \\f$ L^{-1} A (L^*)^{-1} \\f$ if \\p options contains Ax_lBx\n      * and of \\f$ L^{*} A L \\f$ otherwise. This solves the\n      * generalized eigenproblem, because any solution of the generalized\n      * eigenproblem \\f$ Ax = \\lambda B x \\f$ corresponds to a solution\n      * \\f$ L^{-1} A (L^*)^{-1} (L^* x) = \\lambda (L^* x) \\f$ of the\n      * eigenproblem for \\f$ L^{-1} A (L^*)^{-1} \\f$. Similar statements\n      * can be made for the two other variants.\n      *\n      * Example: \\include SelfAdjointEigenSolver_compute_MatrixType2.cpp\n      * Output: \\verbinclude SelfAdjointEigenSolver_compute_MatrixType2.out\n      *\n      * \\sa GeneralizedSelfAdjointEigenSolver(const MatrixType&, const MatrixType&, int)\n      */\n    GeneralizedSelfAdjointEigenSolver& compute(const MatrixType& matA, const MatrixType& matB,\n                                               int options = ComputeEigenvectors|Ax_lBx);\n\n  protected:\n\n};\n\n\ntemplate<typename MatrixType>\nGeneralizedSelfAdjointEigenSolver<MatrixType>& GeneralizedSelfAdjointEigenSolver<MatrixType>::\ncompute(const MatrixType& matA, const MatrixType& matB, int options)\n{\n  eigen_assert(matA.cols()==matA.rows() && matB.rows()==matA.rows() && matB.cols()==matB.rows());\n  eigen_assert((options&~(EigVecMask|GenEigMask))==0\n          && (options&EigVecMask)!=EigVecMask\n          && ((options&GenEigMask)==0 || (options&GenEigMask)==Ax_lBx\n           || (options&GenEigMask)==ABx_lx || (options&GenEigMask)==BAx_lx)\n          && \"invalid option parameter\");\n\n  bool computeEigVecs = ((options&EigVecMask)==0) || ((options&EigVecMask)==ComputeEigenvectors);\n\n  // Compute the cholesky decomposition of matB = L L' = U'U\n  LLT<MatrixType> cholB(matB);\n\n  int type = (options&GenEigMask);\n  if(type==0)\n    type = Ax_lBx;\n\n  if(type==Ax_lBx)\n  {\n    // compute C = inv(L) A inv(L')\n    MatrixType matC = matA.template selfadjointView<Lower>();\n    cholB.matrixL().template solveInPlace<OnTheLeft>(matC);\n    cholB.matrixU().template solveInPlace<OnTheRight>(matC);\n\n    Base::compute(matC, computeEigVecs ? ComputeEigenvectors : EigenvaluesOnly );\n\n    // transform back the eigen vectors: evecs = inv(U) * evecs\n    if(computeEigVecs)\n      cholB.matrixU().solveInPlace(Base::m_eivec);\n  }\n  else if(type==ABx_lx)\n  {\n    // compute C = L' A L\n    MatrixType matC = matA.template selfadjointView<Lower>();\n    matC = matC * cholB.matrixL();\n    matC = cholB.matrixU() * matC;\n\n    Base::compute(matC, computeEigVecs ? ComputeEigenvectors : EigenvaluesOnly);\n\n    // transform back the eigen vectors: evecs = inv(U) * evecs\n    if(computeEigVecs)\n      cholB.matrixU().solveInPlace(Base::m_eivec);\n  }\n  else if(type==BAx_lx)\n  {\n    // compute C = L' A L\n    MatrixType matC = matA.template selfadjointView<Lower>();\n    matC = matC * cholB.matrixL();\n    matC = cholB.matrixU() * matC;\n\n    Base::compute(matC, computeEigVecs ? ComputeEigenvectors : EigenvaluesOnly);\n\n    // transform back the eigen vectors: evecs = L * evecs\n    if(computeEigVecs)\n      Base::m_eivec = cholB.matrixL() * Base::m_eivec;\n  }\n\n  return *this;\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_GENERALIZEDSELFADJOINTEIGENSOLVER_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Eigenvalues/HessenbergDecomposition.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2010 Jitse Niesen <jitse@maths.leeds.ac.uk>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_HESSENBERGDECOMPOSITION_H\n#define EIGEN_HESSENBERGDECOMPOSITION_H\n\nnamespace Eigen { \n\nnamespace internal {\n  \ntemplate<typename MatrixType> struct HessenbergDecompositionMatrixHReturnType;\ntemplate<typename MatrixType>\nstruct traits<HessenbergDecompositionMatrixHReturnType<MatrixType> >\n{\n  typedef MatrixType ReturnType;\n};\n\n}\n\n/** \\eigenvalues_module \\ingroup Eigenvalues_Module\n  *\n  *\n  * \\class HessenbergDecomposition\n  *\n  * \\brief Reduces a square matrix to Hessenberg form by an orthogonal similarity transformation\n  *\n  * \\tparam _MatrixType the type of the matrix of which we are computing the Hessenberg decomposition\n  *\n  * This class performs an Hessenberg decomposition of a matrix \\f$ A \\f$. In\n  * the real case, the Hessenberg decomposition consists of an orthogonal\n  * matrix \\f$ Q \\f$ and a Hessenberg matrix \\f$ H \\f$ such that \\f$ A = Q H\n  * Q^T \\f$. An orthogonal matrix is a matrix whose inverse equals its\n  * transpose (\\f$ Q^{-1} = Q^T \\f$). A Hessenberg matrix has zeros below the\n  * subdiagonal, so it is almost upper triangular. The Hessenberg decomposition\n  * of a complex matrix is \\f$ A = Q H Q^* \\f$ with \\f$ Q \\f$ unitary (that is,\n  * \\f$ Q^{-1} = Q^* \\f$).\n  *\n  * Call the function compute() to compute the Hessenberg decomposition of a\n  * given matrix. Alternatively, you can use the\n  * HessenbergDecomposition(const MatrixType&) constructor which computes the\n  * Hessenberg decomposition at construction time. Once the decomposition is\n  * computed, you can use the matrixH() and matrixQ() functions to construct\n  * the matrices H and Q in the decomposition.\n  *\n  * The documentation for matrixH() contains an example of the typical use of\n  * this class.\n  *\n  * \\sa class ComplexSchur, class Tridiagonalization, \\ref QR_Module \"QR Module\"\n  */\ntemplate<typename _MatrixType> class HessenbergDecomposition\n{\n  public:\n\n    /** \\brief Synonym for the template parameter \\p _MatrixType. */\n    typedef _MatrixType MatrixType;\n\n    enum {\n      Size = MatrixType::RowsAtCompileTime,\n      SizeMinusOne = Size == Dynamic ? Dynamic : Size - 1,\n      Options = MatrixType::Options,\n      MaxSize = MatrixType::MaxRowsAtCompileTime,\n      MaxSizeMinusOne = MaxSize == Dynamic ? Dynamic : MaxSize - 1\n    };\n\n    /** \\brief Scalar type for matrices of type #MatrixType. */\n    typedef typename MatrixType::Scalar Scalar;\n    typedef Eigen::Index Index; ///< \\deprecated since Eigen 3.3\n\n    /** \\brief Type for vector of Householder coefficients.\n      *\n      * This is column vector with entries of type #Scalar. The length of the\n      * vector is one less than the size of #MatrixType, if it is a fixed-side\n      * type.\n      */\n    typedef Matrix<Scalar, SizeMinusOne, 1, Options & ~RowMajor, MaxSizeMinusOne, 1> CoeffVectorType;\n\n    /** \\brief Return type of matrixQ() */\n    typedef HouseholderSequence<MatrixType,typename internal::remove_all<typename CoeffVectorType::ConjugateReturnType>::type> HouseholderSequenceType;\n    \n    typedef internal::HessenbergDecompositionMatrixHReturnType<MatrixType> MatrixHReturnType;\n\n    /** \\brief Default constructor; the decomposition will be computed later.\n      *\n      * \\param [in] size  The size of the matrix whose Hessenberg decomposition will be computed.\n      *\n      * The default constructor is useful in cases in which the user intends to\n      * perform decompositions via compute().  The \\p size parameter is only\n      * used as a hint. It is not an error to give a wrong \\p size, but it may\n      * impair performance.\n      *\n      * \\sa compute() for an example.\n      */\n    explicit HessenbergDecomposition(Index size = Size==Dynamic ? 2 : Size)\n      : m_matrix(size,size),\n        m_temp(size),\n        m_isInitialized(false)\n    {\n      if(size>1)\n        m_hCoeffs.resize(size-1);\n    }\n\n    /** \\brief Constructor; computes Hessenberg decomposition of given matrix.\n      *\n      * \\param[in]  matrix  Square matrix whose Hessenberg decomposition is to be computed.\n      *\n      * This constructor calls compute() to compute the Hessenberg\n      * decomposition.\n      *\n      * \\sa matrixH() for an example.\n      */\n    template<typename InputType>\n    explicit HessenbergDecomposition(const EigenBase<InputType>& matrix)\n      : m_matrix(matrix.derived()),\n        m_temp(matrix.rows()),\n        m_isInitialized(false)\n    {\n      if(matrix.rows()<2)\n      {\n        m_isInitialized = true;\n        return;\n      }\n      m_hCoeffs.resize(matrix.rows()-1,1);\n      _compute(m_matrix, m_hCoeffs, m_temp);\n      m_isInitialized = true;\n    }\n\n    /** \\brief Computes Hessenberg decomposition of given matrix.\n      *\n      * \\param[in]  matrix  Square matrix whose Hessenberg decomposition is to be computed.\n      * \\returns    Reference to \\c *this\n      *\n      * The Hessenberg decomposition is computed by bringing the columns of the\n      * matrix successively in the required form using Householder reflections\n      * (see, e.g., Algorithm 7.4.2 in Golub \\& Van Loan, <i>%Matrix\n      * Computations</i>). The cost is \\f$ 10n^3/3 \\f$ flops, where \\f$ n \\f$\n      * denotes the size of the given matrix.\n      *\n      * This method reuses of the allocated data in the HessenbergDecomposition\n      * object.\n      *\n      * Example: \\include HessenbergDecomposition_compute.cpp\n      * Output: \\verbinclude HessenbergDecomposition_compute.out\n      */\n    template<typename InputType>\n    HessenbergDecomposition& compute(const EigenBase<InputType>& matrix)\n    {\n      m_matrix = matrix.derived();\n      if(matrix.rows()<2)\n      {\n        m_isInitialized = true;\n        return *this;\n      }\n      m_hCoeffs.resize(matrix.rows()-1,1);\n      _compute(m_matrix, m_hCoeffs, m_temp);\n      m_isInitialized = true;\n      return *this;\n    }\n\n    /** \\brief Returns the Householder coefficients.\n      *\n      * \\returns a const reference to the vector of Householder coefficients\n      *\n      * \\pre Either the constructor HessenbergDecomposition(const MatrixType&)\n      * or the member function compute(const MatrixType&) has been called\n      * before to compute the Hessenberg decomposition of a matrix.\n      *\n      * The Householder coefficients allow the reconstruction of the matrix\n      * \\f$ Q \\f$ in the Hessenberg decomposition from the packed data.\n      *\n      * \\sa packedMatrix(), \\ref Householder_Module \"Householder module\"\n      */\n    const CoeffVectorType& householderCoefficients() const\n    {\n      eigen_assert(m_isInitialized && \"HessenbergDecomposition is not initialized.\");\n      return m_hCoeffs;\n    }\n\n    /** \\brief Returns the internal representation of the decomposition\n      *\n      *\t\\returns a const reference to a matrix with the internal representation\n      *\t         of the decomposition.\n      *\n      * \\pre Either the constructor HessenbergDecomposition(const MatrixType&)\n      * or the member function compute(const MatrixType&) has been called\n      * before to compute the Hessenberg decomposition of a matrix.\n      *\n      * The returned matrix contains the following information:\n      *  - the upper part and lower sub-diagonal represent the Hessenberg matrix H\n      *  - the rest of the lower part contains the Householder vectors that, combined with\n      *    Householder coefficients returned by householderCoefficients(),\n      *    allows to reconstruct the matrix Q as\n      *       \\f$ Q = H_{N-1} \\ldots H_1 H_0 \\f$.\n      *    Here, the matrices \\f$ H_i \\f$ are the Householder transformations\n      *       \\f$ H_i = (I - h_i v_i v_i^T) \\f$\n      *    where \\f$ h_i \\f$ is the \\f$ i \\f$th Householder coefficient and\n      *    \\f$ v_i \\f$ is the Householder vector defined by\n      *       \\f$ v_i = [ 0, \\ldots, 0, 1, M(i+2,i), \\ldots, M(N-1,i) ]^T \\f$\n      *    with M the matrix returned by this function.\n      *\n      * See LAPACK for further details on this packed storage.\n      *\n      * Example: \\include HessenbergDecomposition_packedMatrix.cpp\n      * Output: \\verbinclude HessenbergDecomposition_packedMatrix.out\n      *\n      * \\sa householderCoefficients()\n      */\n    const MatrixType& packedMatrix() const\n    {\n      eigen_assert(m_isInitialized && \"HessenbergDecomposition is not initialized.\");\n      return m_matrix;\n    }\n\n    /** \\brief Reconstructs the orthogonal matrix Q in the decomposition\n      *\n      * \\returns object representing the matrix Q\n      *\n      * \\pre Either the constructor HessenbergDecomposition(const MatrixType&)\n      * or the member function compute(const MatrixType&) has been called\n      * before to compute the Hessenberg decomposition of a matrix.\n      *\n      * This function returns a light-weight object of template class\n      * HouseholderSequence. You can either apply it directly to a matrix or\n      * you can convert it to a matrix of type #MatrixType.\n      *\n      * \\sa matrixH() for an example, class HouseholderSequence\n      */\n    HouseholderSequenceType matrixQ() const\n    {\n      eigen_assert(m_isInitialized && \"HessenbergDecomposition is not initialized.\");\n      return HouseholderSequenceType(m_matrix, m_hCoeffs.conjugate())\n             .setLength(m_matrix.rows() - 1)\n             .setShift(1);\n    }\n\n    /** \\brief Constructs the Hessenberg matrix H in the decomposition\n      *\n      * \\returns expression object representing the matrix H\n      *\n      * \\pre Either the constructor HessenbergDecomposition(const MatrixType&)\n      * or the member function compute(const MatrixType&) has been called\n      * before to compute the Hessenberg decomposition of a matrix.\n      *\n      * The object returned by this function constructs the Hessenberg matrix H\n      * when it is assigned to a matrix or otherwise evaluated. The matrix H is\n      * constructed from the packed matrix as returned by packedMatrix(): The\n      * upper part (including the subdiagonal) of the packed matrix contains\n      * the matrix H. It may sometimes be better to directly use the packed\n      * matrix instead of constructing the matrix H.\n      *\n      * Example: \\include HessenbergDecomposition_matrixH.cpp\n      * Output: \\verbinclude HessenbergDecomposition_matrixH.out\n      *\n      * \\sa matrixQ(), packedMatrix()\n      */\n    MatrixHReturnType matrixH() const\n    {\n      eigen_assert(m_isInitialized && \"HessenbergDecomposition is not initialized.\");\n      return MatrixHReturnType(*this);\n    }\n\n  private:\n\n    typedef Matrix<Scalar, 1, Size, Options | RowMajor, 1, MaxSize> VectorType;\n    typedef typename NumTraits<Scalar>::Real RealScalar;\n    static void _compute(MatrixType& matA, CoeffVectorType& hCoeffs, VectorType& temp);\n\n  protected:\n    MatrixType m_matrix;\n    CoeffVectorType m_hCoeffs;\n    VectorType m_temp;\n    bool m_isInitialized;\n};\n\n/** \\internal\n  * Performs a tridiagonal decomposition of \\a matA in place.\n  *\n  * \\param matA the input selfadjoint matrix\n  * \\param hCoeffs returned Householder coefficients\n  *\n  * The result is written in the lower triangular part of \\a matA.\n  *\n  * Implemented from Golub's \"%Matrix Computations\", algorithm 8.3.1.\n  *\n  * \\sa packedMatrix()\n  */\ntemplate<typename MatrixType>\nvoid HessenbergDecomposition<MatrixType>::_compute(MatrixType& matA, CoeffVectorType& hCoeffs, VectorType& temp)\n{\n  eigen_assert(matA.rows()==matA.cols());\n  Index n = matA.rows();\n  temp.resize(n);\n  for (Index i = 0; i<n-1; ++i)\n  {\n    // let's consider the vector v = i-th column starting at position i+1\n    Index remainingSize = n-i-1;\n    RealScalar beta;\n    Scalar h;\n    matA.col(i).tail(remainingSize).makeHouseholderInPlace(h, beta);\n    matA.col(i).coeffRef(i+1) = beta;\n    hCoeffs.coeffRef(i) = h;\n\n    // Apply similarity transformation to remaining columns,\n    // i.e., compute A = H A H'\n\n    // A = H A\n    matA.bottomRightCorner(remainingSize, remainingSize)\n        .applyHouseholderOnTheLeft(matA.col(i).tail(remainingSize-1), h, &temp.coeffRef(0));\n\n    // A = A H'\n    matA.rightCols(remainingSize)\n        .applyHouseholderOnTheRight(matA.col(i).tail(remainingSize-1).conjugate(), numext::conj(h), &temp.coeffRef(0));\n  }\n}\n\nnamespace internal {\n\n/** \\eigenvalues_module \\ingroup Eigenvalues_Module\n  *\n  *\n  * \\brief Expression type for return value of HessenbergDecomposition::matrixH()\n  *\n  * \\tparam MatrixType type of matrix in the Hessenberg decomposition\n  *\n  * Objects of this type represent the Hessenberg matrix in the Hessenberg\n  * decomposition of some matrix. The object holds a reference to the\n  * HessenbergDecomposition class until the it is assigned or evaluated for\n  * some other reason (the reference should remain valid during the life time\n  * of this object). This class is the return type of\n  * HessenbergDecomposition::matrixH(); there is probably no other use for this\n  * class.\n  */\ntemplate<typename MatrixType> struct HessenbergDecompositionMatrixHReturnType\n: public ReturnByValue<HessenbergDecompositionMatrixHReturnType<MatrixType> >\n{\n  public:\n    /** \\brief Constructor.\n      *\n      * \\param[in] hess  Hessenberg decomposition\n      */\n    HessenbergDecompositionMatrixHReturnType(const HessenbergDecomposition<MatrixType>& hess) : m_hess(hess) { }\n\n    /** \\brief Hessenberg matrix in decomposition.\n      *\n      * \\param[out] result  Hessenberg matrix in decomposition \\p hess which\n      *                     was passed to the constructor\n      */\n    template <typename ResultType>\n    inline void evalTo(ResultType& result) const\n    {\n      result = m_hess.packedMatrix();\n      Index n = result.rows();\n      if (n>2)\n        result.bottomLeftCorner(n-2, n-2).template triangularView<Lower>().setZero();\n    }\n\n    Index rows() const { return m_hess.packedMatrix().rows(); }\n    Index cols() const { return m_hess.packedMatrix().cols(); }\n\n  protected:\n    const HessenbergDecomposition<MatrixType>& m_hess;\n};\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_HESSENBERGDECOMPOSITION_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Eigenvalues/MatrixBaseEigenvalues.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2010 Jitse Niesen <jitse@maths.leeds.ac.uk>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_MATRIXBASEEIGENVALUES_H\n#define EIGEN_MATRIXBASEEIGENVALUES_H\n\nnamespace Eigen { \n\nnamespace internal {\n\ntemplate<typename Derived, bool IsComplex>\nstruct eigenvalues_selector\n{\n  // this is the implementation for the case IsComplex = true\n  static inline typename MatrixBase<Derived>::EigenvaluesReturnType const\n  run(const MatrixBase<Derived>& m)\n  {\n    typedef typename Derived::PlainObject PlainObject;\n    PlainObject m_eval(m);\n    return ComplexEigenSolver<PlainObject>(m_eval, false).eigenvalues();\n  }\n};\n\ntemplate<typename Derived>\nstruct eigenvalues_selector<Derived, false>\n{\n  static inline typename MatrixBase<Derived>::EigenvaluesReturnType const\n  run(const MatrixBase<Derived>& m)\n  {\n    typedef typename Derived::PlainObject PlainObject;\n    PlainObject m_eval(m);\n    return EigenSolver<PlainObject>(m_eval, false).eigenvalues();\n  }\n};\n\n} // end namespace internal\n\n/** \\brief Computes the eigenvalues of a matrix \n  * \\returns Column vector containing the eigenvalues.\n  *\n  * \\eigenvalues_module\n  * This function computes the eigenvalues with the help of the EigenSolver\n  * class (for real matrices) or the ComplexEigenSolver class (for complex\n  * matrices). \n  *\n  * The eigenvalues are repeated according to their algebraic multiplicity,\n  * so there are as many eigenvalues as rows in the matrix.\n  *\n  * The SelfAdjointView class provides a better algorithm for selfadjoint\n  * matrices.\n  *\n  * Example: \\include MatrixBase_eigenvalues.cpp\n  * Output: \\verbinclude MatrixBase_eigenvalues.out\n  *\n  * \\sa EigenSolver::eigenvalues(), ComplexEigenSolver::eigenvalues(),\n  *     SelfAdjointView::eigenvalues()\n  */\ntemplate<typename Derived>\ninline typename MatrixBase<Derived>::EigenvaluesReturnType\nMatrixBase<Derived>::eigenvalues() const\n{\n  typedef typename internal::traits<Derived>::Scalar Scalar;\n  return internal::eigenvalues_selector<Derived, NumTraits<Scalar>::IsComplex>::run(derived());\n}\n\n/** \\brief Computes the eigenvalues of a matrix\n  * \\returns Column vector containing the eigenvalues.\n  *\n  * \\eigenvalues_module\n  * This function computes the eigenvalues with the help of the\n  * SelfAdjointEigenSolver class.  The eigenvalues are repeated according to\n  * their algebraic multiplicity, so there are as many eigenvalues as rows in\n  * the matrix.\n  *\n  * Example: \\include SelfAdjointView_eigenvalues.cpp\n  * Output: \\verbinclude SelfAdjointView_eigenvalues.out\n  *\n  * \\sa SelfAdjointEigenSolver::eigenvalues(), MatrixBase::eigenvalues()\n  */\ntemplate<typename MatrixType, unsigned int UpLo> \ninline typename SelfAdjointView<MatrixType, UpLo>::EigenvaluesReturnType\nSelfAdjointView<MatrixType, UpLo>::eigenvalues() const\n{\n  typedef typename SelfAdjointView<MatrixType, UpLo>::PlainObject PlainObject;\n  PlainObject thisAsMatrix(*this);\n  return SelfAdjointEigenSolver<PlainObject>(thisAsMatrix, false).eigenvalues();\n}\n\n\n\n/** \\brief Computes the L2 operator norm\n  * \\returns Operator norm of the matrix.\n  *\n  * \\eigenvalues_module\n  * This function computes the L2 operator norm of a matrix, which is also\n  * known as the spectral norm. The norm of a matrix \\f$ A \\f$ is defined to be\n  * \\f[ \\|A\\|_2 = \\max_x \\frac{\\|Ax\\|_2}{\\|x\\|_2} \\f]\n  * where the maximum is over all vectors and the norm on the right is the\n  * Euclidean vector norm. The norm equals the largest singular value, which is\n  * the square root of the largest eigenvalue of the positive semi-definite\n  * matrix \\f$ A^*A \\f$.\n  *\n  * The current implementation uses the eigenvalues of \\f$ A^*A \\f$, as computed\n  * by SelfAdjointView::eigenvalues(), to compute the operator norm of a\n  * matrix.  The SelfAdjointView class provides a better algorithm for\n  * selfadjoint matrices.\n  *\n  * Example: \\include MatrixBase_operatorNorm.cpp\n  * Output: \\verbinclude MatrixBase_operatorNorm.out\n  *\n  * \\sa SelfAdjointView::eigenvalues(), SelfAdjointView::operatorNorm()\n  */\ntemplate<typename Derived>\ninline typename MatrixBase<Derived>::RealScalar\nMatrixBase<Derived>::operatorNorm() const\n{\n  using std::sqrt;\n  typename Derived::PlainObject m_eval(derived());\n  // FIXME if it is really guaranteed that the eigenvalues are already sorted,\n  // then we don't need to compute a maxCoeff() here, comparing the 1st and last ones is enough.\n  return sqrt((m_eval*m_eval.adjoint())\n                 .eval()\n\t\t .template selfadjointView<Lower>()\n\t\t .eigenvalues()\n\t\t .maxCoeff()\n\t\t );\n}\n\n/** \\brief Computes the L2 operator norm\n  * \\returns Operator norm of the matrix.\n  *\n  * \\eigenvalues_module\n  * This function computes the L2 operator norm of a self-adjoint matrix. For a\n  * self-adjoint matrix, the operator norm is the largest eigenvalue.\n  *\n  * The current implementation uses the eigenvalues of the matrix, as computed\n  * by eigenvalues(), to compute the operator norm of the matrix.\n  *\n  * Example: \\include SelfAdjointView_operatorNorm.cpp\n  * Output: \\verbinclude SelfAdjointView_operatorNorm.out\n  *\n  * \\sa eigenvalues(), MatrixBase::operatorNorm()\n  */\ntemplate<typename MatrixType, unsigned int UpLo>\ninline typename SelfAdjointView<MatrixType, UpLo>::RealScalar\nSelfAdjointView<MatrixType, UpLo>::operatorNorm() const\n{\n  return eigenvalues().cwiseAbs().maxCoeff();\n}\n\n} // end namespace Eigen\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Eigenvalues/RealQZ.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2012 Alexey Korepanov <kaikaikai@yandex.ru>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_REAL_QZ_H\n#define EIGEN_REAL_QZ_H\n\nnamespace Eigen {\n\n  /** \\eigenvalues_module \\ingroup Eigenvalues_Module\n   *\n   *\n   * \\class RealQZ\n   *\n   * \\brief Performs a real QZ decomposition of a pair of square matrices\n   *\n   * \\tparam _MatrixType the type of the matrix of which we are computing the\n   * real QZ decomposition; this is expected to be an instantiation of the\n   * Matrix class template.\n   *\n   * Given a real square matrices A and B, this class computes the real QZ\n   * decomposition: \\f$ A = Q S Z \\f$, \\f$ B = Q T Z \\f$ where Q and Z are\n   * real orthogonal matrixes, T is upper-triangular matrix, and S is upper\n   * quasi-triangular matrix. An orthogonal matrix is a matrix whose\n   * inverse is equal to its transpose, \\f$ U^{-1} = U^T \\f$. A quasi-triangular\n   * matrix is a block-triangular matrix whose diagonal consists of 1-by-1\n   * blocks and 2-by-2 blocks where further reduction is impossible due to\n   * complex eigenvalues. \n   *\n   * The eigenvalues of the pencil \\f$ A - z B \\f$ can be obtained from\n   * 1x1 and 2x2 blocks on the diagonals of S and T.\n   *\n   * Call the function compute() to compute the real QZ decomposition of a\n   * given pair of matrices. Alternatively, you can use the \n   * RealQZ(const MatrixType& B, const MatrixType& B, bool computeQZ)\n   * constructor which computes the real QZ decomposition at construction\n   * time. Once the decomposition is computed, you can use the matrixS(),\n   * matrixT(), matrixQ() and matrixZ() functions to retrieve the matrices\n   * S, T, Q and Z in the decomposition. If computeQZ==false, some time\n   * is saved by not computing matrices Q and Z.\n   *\n   * Example: \\include RealQZ_compute.cpp\n   * Output: \\include RealQZ_compute.out\n   *\n   * \\note The implementation is based on the algorithm in \"Matrix Computations\"\n   * by Gene H. Golub and Charles F. Van Loan, and a paper \"An algorithm for\n   * generalized eigenvalue problems\" by C.B.Moler and G.W.Stewart.\n   *\n   * \\sa class RealSchur, class ComplexSchur, class EigenSolver, class ComplexEigenSolver\n   */\n\n  template<typename _MatrixType> class RealQZ\n  {\n    public:\n      typedef _MatrixType MatrixType;\n      enum {\n        RowsAtCompileTime = MatrixType::RowsAtCompileTime,\n        ColsAtCompileTime = MatrixType::ColsAtCompileTime,\n        Options = MatrixType::Options,\n        MaxRowsAtCompileTime = MatrixType::MaxRowsAtCompileTime,\n        MaxColsAtCompileTime = MatrixType::MaxColsAtCompileTime\n      };\n      typedef typename MatrixType::Scalar Scalar;\n      typedef std::complex<typename NumTraits<Scalar>::Real> ComplexScalar;\n      typedef Eigen::Index Index; ///< \\deprecated since Eigen 3.3\n\n      typedef Matrix<ComplexScalar, ColsAtCompileTime, 1, Options & ~RowMajor, MaxColsAtCompileTime, 1> EigenvalueType;\n      typedef Matrix<Scalar, ColsAtCompileTime, 1, Options & ~RowMajor, MaxColsAtCompileTime, 1> ColumnVectorType;\n\n      /** \\brief Default constructor.\n       *\n       * \\param [in] size  Positive integer, size of the matrix whose QZ decomposition will be computed.\n       *\n       * The default constructor is useful in cases in which the user intends to\n       * perform decompositions via compute().  The \\p size parameter is only\n       * used as a hint. It is not an error to give a wrong \\p size, but it may\n       * impair performance.\n       *\n       * \\sa compute() for an example.\n       */\n      explicit RealQZ(Index size = RowsAtCompileTime==Dynamic ? 1 : RowsAtCompileTime) :\n        m_S(size, size),\n        m_T(size, size),\n        m_Q(size, size),\n        m_Z(size, size),\n        m_workspace(size*2),\n        m_maxIters(400),\n        m_isInitialized(false)\n        { }\n\n      /** \\brief Constructor; computes real QZ decomposition of given matrices\n       * \n       * \\param[in]  A          Matrix A.\n       * \\param[in]  B          Matrix B.\n       * \\param[in]  computeQZ  If false, A and Z are not computed.\n       *\n       * This constructor calls compute() to compute the QZ decomposition.\n       */\n      RealQZ(const MatrixType& A, const MatrixType& B, bool computeQZ = true) :\n        m_S(A.rows(),A.cols()),\n        m_T(A.rows(),A.cols()),\n        m_Q(A.rows(),A.cols()),\n        m_Z(A.rows(),A.cols()),\n        m_workspace(A.rows()*2),\n        m_maxIters(400),\n        m_isInitialized(false) {\n          compute(A, B, computeQZ);\n        }\n\n      /** \\brief Returns matrix Q in the QZ decomposition. \n       *\n       * \\returns A const reference to the matrix Q.\n       */\n      const MatrixType& matrixQ() const {\n        eigen_assert(m_isInitialized && \"RealQZ is not initialized.\");\n        eigen_assert(m_computeQZ && \"The matrices Q and Z have not been computed during the QZ decomposition.\");\n        return m_Q;\n      }\n\n      /** \\brief Returns matrix Z in the QZ decomposition. \n       *\n       * \\returns A const reference to the matrix Z.\n       */\n      const MatrixType& matrixZ() const {\n        eigen_assert(m_isInitialized && \"RealQZ is not initialized.\");\n        eigen_assert(m_computeQZ && \"The matrices Q and Z have not been computed during the QZ decomposition.\");\n        return m_Z;\n      }\n\n      /** \\brief Returns matrix S in the QZ decomposition. \n       *\n       * \\returns A const reference to the matrix S.\n       */\n      const MatrixType& matrixS() const {\n        eigen_assert(m_isInitialized && \"RealQZ is not initialized.\");\n        return m_S;\n      }\n\n      /** \\brief Returns matrix S in the QZ decomposition. \n       *\n       * \\returns A const reference to the matrix S.\n       */\n      const MatrixType& matrixT() const {\n        eigen_assert(m_isInitialized && \"RealQZ is not initialized.\");\n        return m_T;\n      }\n\n      /** \\brief Computes QZ decomposition of given matrix. \n       * \n       * \\param[in]  A          Matrix A.\n       * \\param[in]  B          Matrix B.\n       * \\param[in]  computeQZ  If false, A and Z are not computed.\n       * \\returns    Reference to \\c *this\n       */\n      RealQZ& compute(const MatrixType& A, const MatrixType& B, bool computeQZ = true);\n\n      /** \\brief Reports whether previous computation was successful.\n       *\n       * \\returns \\c Success if computation was succesful, \\c NoConvergence otherwise.\n       */\n      ComputationInfo info() const\n      {\n        eigen_assert(m_isInitialized && \"RealQZ is not initialized.\");\n        return m_info;\n      }\n\n      /** \\brief Returns number of performed QR-like iterations.\n      */\n      Index iterations() const\n      {\n        eigen_assert(m_isInitialized && \"RealQZ is not initialized.\");\n        return m_global_iter;\n      }\n\n      /** Sets the maximal number of iterations allowed to converge to one eigenvalue\n       * or decouple the problem.\n      */\n      RealQZ& setMaxIterations(Index maxIters)\n      {\n        m_maxIters = maxIters;\n        return *this;\n      }\n\n    private:\n\n      MatrixType m_S, m_T, m_Q, m_Z;\n      Matrix<Scalar,Dynamic,1> m_workspace;\n      ComputationInfo m_info;\n      Index m_maxIters;\n      bool m_isInitialized;\n      bool m_computeQZ;\n      Scalar m_normOfT, m_normOfS;\n      Index m_global_iter;\n\n      typedef Matrix<Scalar,3,1> Vector3s;\n      typedef Matrix<Scalar,2,1> Vector2s;\n      typedef Matrix<Scalar,2,2> Matrix2s;\n      typedef JacobiRotation<Scalar> JRs;\n\n      void hessenbergTriangular();\n      void computeNorms();\n      Index findSmallSubdiagEntry(Index iu);\n      Index findSmallDiagEntry(Index f, Index l);\n      void splitOffTwoRows(Index i);\n      void pushDownZero(Index z, Index f, Index l);\n      void step(Index f, Index l, Index iter);\n\n  }; // RealQZ\n\n  /** \\internal Reduces S and T to upper Hessenberg - triangular form */\n  template<typename MatrixType>\n    void RealQZ<MatrixType>::hessenbergTriangular()\n    {\n\n      const Index dim = m_S.cols();\n\n      // perform QR decomposition of T, overwrite T with R, save Q\n      HouseholderQR<MatrixType> qrT(m_T);\n      m_T = qrT.matrixQR();\n      m_T.template triangularView<StrictlyLower>().setZero();\n      m_Q = qrT.householderQ();\n      // overwrite S with Q* S\n      m_S.applyOnTheLeft(m_Q.adjoint());\n      // init Z as Identity\n      if (m_computeQZ)\n        m_Z = MatrixType::Identity(dim,dim);\n      // reduce S to upper Hessenberg with Givens rotations\n      for (Index j=0; j<=dim-3; j++) {\n        for (Index i=dim-1; i>=j+2; i--) {\n          JRs G;\n          // kill S(i,j)\n          if(m_S.coeff(i,j) != 0)\n          {\n            G.makeGivens(m_S.coeff(i-1,j), m_S.coeff(i,j), &m_S.coeffRef(i-1, j));\n            m_S.coeffRef(i,j) = Scalar(0.0);\n            m_S.rightCols(dim-j-1).applyOnTheLeft(i-1,i,G.adjoint());\n            m_T.rightCols(dim-i+1).applyOnTheLeft(i-1,i,G.adjoint());\n            // update Q\n            if (m_computeQZ)\n              m_Q.applyOnTheRight(i-1,i,G);\n          }\n          // kill T(i,i-1)\n          if(m_T.coeff(i,i-1)!=Scalar(0))\n          {\n            G.makeGivens(m_T.coeff(i,i), m_T.coeff(i,i-1), &m_T.coeffRef(i,i));\n            m_T.coeffRef(i,i-1) = Scalar(0.0);\n            m_S.applyOnTheRight(i,i-1,G);\n            m_T.topRows(i).applyOnTheRight(i,i-1,G);\n            // update Z\n            if (m_computeQZ)\n              m_Z.applyOnTheLeft(i,i-1,G.adjoint());\n          }\n        }\n      }\n    }\n\n  /** \\internal Computes vector L1 norms of S and T when in Hessenberg-Triangular form already */\n  template<typename MatrixType>\n    inline void RealQZ<MatrixType>::computeNorms()\n    {\n      const Index size = m_S.cols();\n      m_normOfS = Scalar(0.0);\n      m_normOfT = Scalar(0.0);\n      for (Index j = 0; j < size; ++j)\n      {\n        m_normOfS += m_S.col(j).segment(0, (std::min)(size,j+2)).cwiseAbs().sum();\n        m_normOfT += m_T.row(j).segment(j, size - j).cwiseAbs().sum();\n      }\n    }\n\n\n  /** \\internal Look for single small sub-diagonal element S(res, res-1) and return res (or 0) */\n  template<typename MatrixType>\n    inline Index RealQZ<MatrixType>::findSmallSubdiagEntry(Index iu)\n    {\n      using std::abs;\n      Index res = iu;\n      while (res > 0)\n      {\n        Scalar s = abs(m_S.coeff(res-1,res-1)) + abs(m_S.coeff(res,res));\n        if (s == Scalar(0.0))\n          s = m_normOfS;\n        if (abs(m_S.coeff(res,res-1)) < NumTraits<Scalar>::epsilon() * s)\n          break;\n        res--;\n      }\n      return res;\n    }\n\n  /** \\internal Look for single small diagonal element T(res, res) for res between f and l, and return res (or f-1)  */\n  template<typename MatrixType>\n    inline Index RealQZ<MatrixType>::findSmallDiagEntry(Index f, Index l)\n    {\n      using std::abs;\n      Index res = l;\n      while (res >= f) {\n        if (abs(m_T.coeff(res,res)) <= NumTraits<Scalar>::epsilon() * m_normOfT)\n          break;\n        res--;\n      }\n      return res;\n    }\n\n  /** \\internal decouple 2x2 diagonal block in rows i, i+1 if eigenvalues are real */\n  template<typename MatrixType>\n    inline void RealQZ<MatrixType>::splitOffTwoRows(Index i)\n    {\n      using std::abs;\n      using std::sqrt;\n      const Index dim=m_S.cols();\n      if (abs(m_S.coeff(i+1,i))==Scalar(0))\n        return;\n      Index j = findSmallDiagEntry(i,i+1);\n      if (j==i-1)\n      {\n        // block of (S T^{-1})\n        Matrix2s STi = m_T.template block<2,2>(i,i).template triangularView<Upper>().\n          template solve<OnTheRight>(m_S.template block<2,2>(i,i));\n        Scalar p = Scalar(0.5)*(STi(0,0)-STi(1,1));\n        Scalar q = p*p + STi(1,0)*STi(0,1);\n        if (q>=0) {\n          Scalar z = sqrt(q);\n          // one QR-like iteration for ABi - lambda I\n          // is enough - when we know exact eigenvalue in advance,\n          // convergence is immediate\n          JRs G;\n          if (p>=0)\n            G.makeGivens(p + z, STi(1,0));\n          else\n            G.makeGivens(p - z, STi(1,0));\n          m_S.rightCols(dim-i).applyOnTheLeft(i,i+1,G.adjoint());\n          m_T.rightCols(dim-i).applyOnTheLeft(i,i+1,G.adjoint());\n          // update Q\n          if (m_computeQZ)\n            m_Q.applyOnTheRight(i,i+1,G);\n\n          G.makeGivens(m_T.coeff(i+1,i+1), m_T.coeff(i+1,i));\n          m_S.topRows(i+2).applyOnTheRight(i+1,i,G);\n          m_T.topRows(i+2).applyOnTheRight(i+1,i,G);\n          // update Z\n          if (m_computeQZ)\n            m_Z.applyOnTheLeft(i+1,i,G.adjoint());\n\n          m_S.coeffRef(i+1,i) = Scalar(0.0);\n          m_T.coeffRef(i+1,i) = Scalar(0.0);\n        }\n      }\n      else\n      {\n        pushDownZero(j,i,i+1);\n      }\n    }\n\n  /** \\internal use zero in T(z,z) to zero S(l,l-1), working in block f..l */\n  template<typename MatrixType>\n    inline void RealQZ<MatrixType>::pushDownZero(Index z, Index f, Index l)\n    {\n      JRs G;\n      const Index dim = m_S.cols();\n      for (Index zz=z; zz<l; zz++)\n      {\n        // push 0 down\n        Index firstColS = zz>f ? (zz-1) : zz;\n        G.makeGivens(m_T.coeff(zz, zz+1), m_T.coeff(zz+1, zz+1));\n        m_S.rightCols(dim-firstColS).applyOnTheLeft(zz,zz+1,G.adjoint());\n        m_T.rightCols(dim-zz).applyOnTheLeft(zz,zz+1,G.adjoint());\n        m_T.coeffRef(zz+1,zz+1) = Scalar(0.0);\n        // update Q\n        if (m_computeQZ)\n          m_Q.applyOnTheRight(zz,zz+1,G);\n        // kill S(zz+1, zz-1)\n        if (zz>f)\n        {\n          G.makeGivens(m_S.coeff(zz+1, zz), m_S.coeff(zz+1,zz-1));\n          m_S.topRows(zz+2).applyOnTheRight(zz, zz-1,G);\n          m_T.topRows(zz+1).applyOnTheRight(zz, zz-1,G);\n          m_S.coeffRef(zz+1,zz-1) = Scalar(0.0);\n          // update Z\n          if (m_computeQZ)\n            m_Z.applyOnTheLeft(zz,zz-1,G.adjoint());\n        }\n      }\n      // finally kill S(l,l-1)\n      G.makeGivens(m_S.coeff(l,l), m_S.coeff(l,l-1));\n      m_S.applyOnTheRight(l,l-1,G);\n      m_T.applyOnTheRight(l,l-1,G);\n      m_S.coeffRef(l,l-1)=Scalar(0.0);\n      // update Z\n      if (m_computeQZ)\n        m_Z.applyOnTheLeft(l,l-1,G.adjoint());\n    }\n\n  /** \\internal QR-like iterative step for block f..l */\n  template<typename MatrixType>\n    inline void RealQZ<MatrixType>::step(Index f, Index l, Index iter)\n    {\n      using std::abs;\n      const Index dim = m_S.cols();\n\n      // x, y, z\n      Scalar x, y, z;\n      if (iter==10)\n      {\n        // Wilkinson ad hoc shift\n        const Scalar\n          a11=m_S.coeff(f+0,f+0), a12=m_S.coeff(f+0,f+1),\n          a21=m_S.coeff(f+1,f+0), a22=m_S.coeff(f+1,f+1), a32=m_S.coeff(f+2,f+1),\n          b12=m_T.coeff(f+0,f+1),\n          b11i=Scalar(1.0)/m_T.coeff(f+0,f+0),\n          b22i=Scalar(1.0)/m_T.coeff(f+1,f+1),\n          a87=m_S.coeff(l-1,l-2),\n          a98=m_S.coeff(l-0,l-1),\n          b77i=Scalar(1.0)/m_T.coeff(l-2,l-2),\n          b88i=Scalar(1.0)/m_T.coeff(l-1,l-1);\n        Scalar ss = abs(a87*b77i) + abs(a98*b88i),\n               lpl = Scalar(1.5)*ss,\n               ll = ss*ss;\n        x = ll + a11*a11*b11i*b11i - lpl*a11*b11i + a12*a21*b11i*b22i\n          - a11*a21*b12*b11i*b11i*b22i;\n        y = a11*a21*b11i*b11i - lpl*a21*b11i + a21*a22*b11i*b22i \n          - a21*a21*b12*b11i*b11i*b22i;\n        z = a21*a32*b11i*b22i;\n      }\n      else if (iter==16)\n      {\n        // another exceptional shift\n        x = m_S.coeff(f,f)/m_T.coeff(f,f)-m_S.coeff(l,l)/m_T.coeff(l,l) + m_S.coeff(l,l-1)*m_T.coeff(l-1,l) /\n          (m_T.coeff(l-1,l-1)*m_T.coeff(l,l));\n        y = m_S.coeff(f+1,f)/m_T.coeff(f,f);\n        z = 0;\n      }\n      else if (iter>23 && !(iter%8))\n      {\n        // extremely exceptional shift\n        x = internal::random<Scalar>(-1.0,1.0);\n        y = internal::random<Scalar>(-1.0,1.0);\n        z = internal::random<Scalar>(-1.0,1.0);\n      }\n      else\n      {\n        // Compute the shifts: (x,y,z,0...) = (AB^-1 - l1 I) (AB^-1 - l2 I) e1\n        // where l1 and l2 are the eigenvalues of the 2x2 matrix C = U V^-1 where\n        // U and V are 2x2 bottom right sub matrices of A and B. Thus:\n        //  = AB^-1AB^-1 + l1 l2 I - (l1+l2)(AB^-1)\n        //  = AB^-1AB^-1 + det(M) - tr(M)(AB^-1)\n        // Since we are only interested in having x, y, z with a correct ratio, we have:\n        const Scalar\n          a11 = m_S.coeff(f,f),     a12 = m_S.coeff(f,f+1),\n          a21 = m_S.coeff(f+1,f),   a22 = m_S.coeff(f+1,f+1),\n                                    a32 = m_S.coeff(f+2,f+1),\n\n          a88 = m_S.coeff(l-1,l-1), a89 = m_S.coeff(l-1,l),\n          a98 = m_S.coeff(l,l-1),   a99 = m_S.coeff(l,l),\n\n          b11 = m_T.coeff(f,f),     b12 = m_T.coeff(f,f+1),\n                                    b22 = m_T.coeff(f+1,f+1),\n\n          b88 = m_T.coeff(l-1,l-1), b89 = m_T.coeff(l-1,l),\n                                    b99 = m_T.coeff(l,l);\n\n        x = ( (a88/b88 - a11/b11)*(a99/b99 - a11/b11) - (a89/b99)*(a98/b88) + (a98/b88)*(b89/b99)*(a11/b11) ) * (b11/a21)\n          + a12/b22 - (a11/b11)*(b12/b22);\n        y = (a22/b22-a11/b11) - (a21/b11)*(b12/b22) - (a88/b88-a11/b11) - (a99/b99-a11/b11) + (a98/b88)*(b89/b99);\n        z = a32/b22;\n      }\n\n      JRs G;\n\n      for (Index k=f; k<=l-2; k++)\n      {\n        // variables for Householder reflections\n        Vector2s essential2;\n        Scalar tau, beta;\n\n        Vector3s hr(x,y,z);\n\n        // Q_k to annihilate S(k+1,k-1) and S(k+2,k-1)\n        hr.makeHouseholderInPlace(tau, beta);\n        essential2 = hr.template bottomRows<2>();\n        Index fc=(std::max)(k-1,Index(0));  // first col to update\n        m_S.template middleRows<3>(k).rightCols(dim-fc).applyHouseholderOnTheLeft(essential2, tau, m_workspace.data());\n        m_T.template middleRows<3>(k).rightCols(dim-fc).applyHouseholderOnTheLeft(essential2, tau, m_workspace.data());\n        if (m_computeQZ)\n          m_Q.template middleCols<3>(k).applyHouseholderOnTheRight(essential2, tau, m_workspace.data());\n        if (k>f)\n          m_S.coeffRef(k+2,k-1) = m_S.coeffRef(k+1,k-1) = Scalar(0.0);\n\n        // Z_{k1} to annihilate T(k+2,k+1) and T(k+2,k)\n        hr << m_T.coeff(k+2,k+2),m_T.coeff(k+2,k),m_T.coeff(k+2,k+1);\n        hr.makeHouseholderInPlace(tau, beta);\n        essential2 = hr.template bottomRows<2>();\n        {\n          Index lr = (std::min)(k+4,dim); // last row to update\n          Map<Matrix<Scalar,Dynamic,1> > tmp(m_workspace.data(),lr);\n          // S\n          tmp = m_S.template middleCols<2>(k).topRows(lr) * essential2;\n          tmp += m_S.col(k+2).head(lr);\n          m_S.col(k+2).head(lr) -= tau*tmp;\n          m_S.template middleCols<2>(k).topRows(lr) -= (tau*tmp) * essential2.adjoint();\n          // T\n          tmp = m_T.template middleCols<2>(k).topRows(lr) * essential2;\n          tmp += m_T.col(k+2).head(lr);\n          m_T.col(k+2).head(lr) -= tau*tmp;\n          m_T.template middleCols<2>(k).topRows(lr) -= (tau*tmp) * essential2.adjoint();\n        }\n        if (m_computeQZ)\n        {\n          // Z\n          Map<Matrix<Scalar,1,Dynamic> > tmp(m_workspace.data(),dim);\n          tmp = essential2.adjoint()*(m_Z.template middleRows<2>(k));\n          tmp += m_Z.row(k+2);\n          m_Z.row(k+2) -= tau*tmp;\n          m_Z.template middleRows<2>(k) -= essential2 * (tau*tmp);\n        }\n        m_T.coeffRef(k+2,k) = m_T.coeffRef(k+2,k+1) = Scalar(0.0);\n\n        // Z_{k2} to annihilate T(k+1,k)\n        G.makeGivens(m_T.coeff(k+1,k+1), m_T.coeff(k+1,k));\n        m_S.applyOnTheRight(k+1,k,G);\n        m_T.applyOnTheRight(k+1,k,G);\n        // update Z\n        if (m_computeQZ)\n          m_Z.applyOnTheLeft(k+1,k,G.adjoint());\n        m_T.coeffRef(k+1,k) = Scalar(0.0);\n\n        // update x,y,z\n        x = m_S.coeff(k+1,k);\n        y = m_S.coeff(k+2,k);\n        if (k < l-2)\n          z = m_S.coeff(k+3,k);\n      } // loop over k\n\n      // Q_{n-1} to annihilate y = S(l,l-2)\n      G.makeGivens(x,y);\n      m_S.applyOnTheLeft(l-1,l,G.adjoint());\n      m_T.applyOnTheLeft(l-1,l,G.adjoint());\n      if (m_computeQZ)\n        m_Q.applyOnTheRight(l-1,l,G);\n      m_S.coeffRef(l,l-2) = Scalar(0.0);\n\n      // Z_{n-1} to annihilate T(l,l-1)\n      G.makeGivens(m_T.coeff(l,l),m_T.coeff(l,l-1));\n      m_S.applyOnTheRight(l,l-1,G);\n      m_T.applyOnTheRight(l,l-1,G);\n      if (m_computeQZ)\n        m_Z.applyOnTheLeft(l,l-1,G.adjoint());\n      m_T.coeffRef(l,l-1) = Scalar(0.0);\n    }\n\n  template<typename MatrixType>\n    RealQZ<MatrixType>& RealQZ<MatrixType>::compute(const MatrixType& A_in, const MatrixType& B_in, bool computeQZ)\n    {\n\n      const Index dim = A_in.cols();\n\n      eigen_assert (A_in.rows()==dim && A_in.cols()==dim \n          && B_in.rows()==dim && B_in.cols()==dim \n          && \"Need square matrices of the same dimension\");\n\n      m_isInitialized = true;\n      m_computeQZ = computeQZ;\n      m_S = A_in; m_T = B_in;\n      m_workspace.resize(dim*2);\n      m_global_iter = 0;\n\n      // entrance point: hessenberg triangular decomposition\n      hessenbergTriangular();\n      // compute L1 vector norms of T, S into m_normOfS, m_normOfT\n      computeNorms();\n\n      Index l = dim-1, \n            f, \n            local_iter = 0;\n\n      while (l>0 && local_iter<m_maxIters)\n      {\n        f = findSmallSubdiagEntry(l);\n        // now rows and columns f..l (including) decouple from the rest of the problem\n        if (f>0) m_S.coeffRef(f,f-1) = Scalar(0.0);\n        if (f == l) // One root found\n        {\n          l--;\n          local_iter = 0;\n        }\n        else if (f == l-1) // Two roots found\n        {\n          splitOffTwoRows(f);\n          l -= 2;\n          local_iter = 0;\n        }\n        else // No convergence yet\n        {\n          // if there's zero on diagonal of T, we can isolate an eigenvalue with Givens rotations\n          Index z = findSmallDiagEntry(f,l);\n          if (z>=f)\n          {\n            // zero found\n            pushDownZero(z,f,l);\n          }\n          else\n          {\n            // We are sure now that S.block(f,f, l-f+1,l-f+1) is underuced upper-Hessenberg \n            // and T.block(f,f, l-f+1,l-f+1) is invertible uper-triangular, which allows to\n            // apply a QR-like iteration to rows and columns f..l.\n            step(f,l, local_iter);\n            local_iter++;\n            m_global_iter++;\n          }\n        }\n      }\n      // check if we converged before reaching iterations limit\n      m_info = (local_iter<m_maxIters) ? Success : NoConvergence;\n\n      // For each non triangular 2x2 diagonal block of S,\n      //    reduce the respective 2x2 diagonal block of T to positive diagonal form using 2x2 SVD.\n      // This step is not mandatory for QZ, but it does help further extraction of eigenvalues/eigenvectors,\n      // and is in par with Lapack/Matlab QZ.\n      if(m_info==Success)\n      {\n        for(Index i=0; i<dim-1; ++i)\n        {\n          if(m_S.coeff(i+1, i) != Scalar(0))\n          {\n            JacobiRotation<Scalar> j_left, j_right;\n            internal::real_2x2_jacobi_svd(m_T, i, i+1, &j_left, &j_right);\n\n            // Apply resulting Jacobi rotations\n            m_S.applyOnTheLeft(i,i+1,j_left);\n            m_S.applyOnTheRight(i,i+1,j_right);\n            m_T.applyOnTheLeft(i,i+1,j_left);\n            m_T.applyOnTheRight(i,i+1,j_right);\n            m_T(i+1,i) = m_T(i,i+1) = Scalar(0);\n\n            if(m_computeQZ) {\n              m_Q.applyOnTheRight(i,i+1,j_left.transpose());\n              m_Z.applyOnTheLeft(i,i+1,j_right.transpose());\n            }\n\n            i++;\n          }\n        }\n      }\n\n      return *this;\n    } // end compute\n\n} // end namespace Eigen\n\n#endif //EIGEN_REAL_QZ\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Eigenvalues/RealSchur.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2010,2012 Jitse Niesen <jitse@maths.leeds.ac.uk>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_REAL_SCHUR_H\n#define EIGEN_REAL_SCHUR_H\n\n#include \"./HessenbergDecomposition.h\"\n\nnamespace Eigen { \n\n/** \\eigenvalues_module \\ingroup Eigenvalues_Module\n  *\n  *\n  * \\class RealSchur\n  *\n  * \\brief Performs a real Schur decomposition of a square matrix\n  *\n  * \\tparam _MatrixType the type of the matrix of which we are computing the\n  * real Schur decomposition; this is expected to be an instantiation of the\n  * Matrix class template.\n  *\n  * Given a real square matrix A, this class computes the real Schur\n  * decomposition: \\f$ A = U T U^T \\f$ where U is a real orthogonal matrix and\n  * T is a real quasi-triangular matrix. An orthogonal matrix is a matrix whose\n  * inverse is equal to its transpose, \\f$ U^{-1} = U^T \\f$. A quasi-triangular\n  * matrix is a block-triangular matrix whose diagonal consists of 1-by-1\n  * blocks and 2-by-2 blocks with complex eigenvalues. The eigenvalues of the\n  * blocks on the diagonal of T are the same as the eigenvalues of the matrix\n  * A, and thus the real Schur decomposition is used in EigenSolver to compute\n  * the eigendecomposition of a matrix.\n  *\n  * Call the function compute() to compute the real Schur decomposition of a\n  * given matrix. Alternatively, you can use the RealSchur(const MatrixType&, bool)\n  * constructor which computes the real Schur decomposition at construction\n  * time. Once the decomposition is computed, you can use the matrixU() and\n  * matrixT() functions to retrieve the matrices U and T in the decomposition.\n  *\n  * The documentation of RealSchur(const MatrixType&, bool) contains an example\n  * of the typical use of this class.\n  *\n  * \\note The implementation is adapted from\n  * <a href=\"http://math.nist.gov/javanumerics/jama/\">JAMA</a> (public domain).\n  * Their code is based on EISPACK.\n  *\n  * \\sa class ComplexSchur, class EigenSolver, class ComplexEigenSolver\n  */\ntemplate<typename _MatrixType> class RealSchur\n{\n  public:\n    typedef _MatrixType MatrixType;\n    enum {\n      RowsAtCompileTime = MatrixType::RowsAtCompileTime,\n      ColsAtCompileTime = MatrixType::ColsAtCompileTime,\n      Options = MatrixType::Options,\n      MaxRowsAtCompileTime = MatrixType::MaxRowsAtCompileTime,\n      MaxColsAtCompileTime = MatrixType::MaxColsAtCompileTime\n    };\n    typedef typename MatrixType::Scalar Scalar;\n    typedef std::complex<typename NumTraits<Scalar>::Real> ComplexScalar;\n    typedef Eigen::Index Index; ///< \\deprecated since Eigen 3.3\n\n    typedef Matrix<ComplexScalar, ColsAtCompileTime, 1, Options & ~RowMajor, MaxColsAtCompileTime, 1> EigenvalueType;\n    typedef Matrix<Scalar, ColsAtCompileTime, 1, Options & ~RowMajor, MaxColsAtCompileTime, 1> ColumnVectorType;\n\n    /** \\brief Default constructor.\n      *\n      * \\param [in] size  Positive integer, size of the matrix whose Schur decomposition will be computed.\n      *\n      * The default constructor is useful in cases in which the user intends to\n      * perform decompositions via compute().  The \\p size parameter is only\n      * used as a hint. It is not an error to give a wrong \\p size, but it may\n      * impair performance.\n      *\n      * \\sa compute() for an example.\n      */\n    explicit RealSchur(Index size = RowsAtCompileTime==Dynamic ? 1 : RowsAtCompileTime)\n            : m_matT(size, size),\n              m_matU(size, size),\n              m_workspaceVector(size),\n              m_hess(size),\n              m_isInitialized(false),\n              m_matUisUptodate(false),\n              m_maxIters(-1)\n    { }\n\n    /** \\brief Constructor; computes real Schur decomposition of given matrix. \n      * \n      * \\param[in]  matrix    Square matrix whose Schur decomposition is to be computed.\n      * \\param[in]  computeU  If true, both T and U are computed; if false, only T is computed.\n      *\n      * This constructor calls compute() to compute the Schur decomposition.\n      *\n      * Example: \\include RealSchur_RealSchur_MatrixType.cpp\n      * Output: \\verbinclude RealSchur_RealSchur_MatrixType.out\n      */\n    template<typename InputType>\n    explicit RealSchur(const EigenBase<InputType>& matrix, bool computeU = true)\n            : m_matT(matrix.rows(),matrix.cols()),\n              m_matU(matrix.rows(),matrix.cols()),\n              m_workspaceVector(matrix.rows()),\n              m_hess(matrix.rows()),\n              m_isInitialized(false),\n              m_matUisUptodate(false),\n              m_maxIters(-1)\n    {\n      compute(matrix.derived(), computeU);\n    }\n\n    /** \\brief Returns the orthogonal matrix in the Schur decomposition. \n      *\n      * \\returns A const reference to the matrix U.\n      *\n      * \\pre Either the constructor RealSchur(const MatrixType&, bool) or the\n      * member function compute(const MatrixType&, bool) has been called before\n      * to compute the Schur decomposition of a matrix, and \\p computeU was set\n      * to true (the default value).\n      *\n      * \\sa RealSchur(const MatrixType&, bool) for an example\n      */\n    const MatrixType& matrixU() const\n    {\n      eigen_assert(m_isInitialized && \"RealSchur is not initialized.\");\n      eigen_assert(m_matUisUptodate && \"The matrix U has not been computed during the RealSchur decomposition.\");\n      return m_matU;\n    }\n\n    /** \\brief Returns the quasi-triangular matrix in the Schur decomposition. \n      *\n      * \\returns A const reference to the matrix T.\n      *\n      * \\pre Either the constructor RealSchur(const MatrixType&, bool) or the\n      * member function compute(const MatrixType&, bool) has been called before\n      * to compute the Schur decomposition of a matrix.\n      *\n      * \\sa RealSchur(const MatrixType&, bool) for an example\n      */\n    const MatrixType& matrixT() const\n    {\n      eigen_assert(m_isInitialized && \"RealSchur is not initialized.\");\n      return m_matT;\n    }\n  \n    /** \\brief Computes Schur decomposition of given matrix. \n      * \n      * \\param[in]  matrix    Square matrix whose Schur decomposition is to be computed.\n      * \\param[in]  computeU  If true, both T and U are computed; if false, only T is computed.\n      * \\returns    Reference to \\c *this\n      *\n      * The Schur decomposition is computed by first reducing the matrix to\n      * Hessenberg form using the class HessenbergDecomposition. The Hessenberg\n      * matrix is then reduced to triangular form by performing Francis QR\n      * iterations with implicit double shift. The cost of computing the Schur\n      * decomposition depends on the number of iterations; as a rough guide, it\n      * may be taken to be \\f$25n^3\\f$ flops if \\a computeU is true and\n      * \\f$10n^3\\f$ flops if \\a computeU is false.\n      *\n      * Example: \\include RealSchur_compute.cpp\n      * Output: \\verbinclude RealSchur_compute.out\n      *\n      * \\sa compute(const MatrixType&, bool, Index)\n      */\n    template<typename InputType>\n    RealSchur& compute(const EigenBase<InputType>& matrix, bool computeU = true);\n\n    /** \\brief Computes Schur decomposition of a Hessenberg matrix H = Z T Z^T\n     *  \\param[in] matrixH Matrix in Hessenberg form H\n     *  \\param[in] matrixQ orthogonal matrix Q that transform a matrix A to H : A = Q H Q^T\n     *  \\param computeU Computes the matriX U of the Schur vectors\n     * \\return Reference to \\c *this\n     * \n     *  This routine assumes that the matrix is already reduced in Hessenberg form matrixH\n     *  using either the class HessenbergDecomposition or another mean. \n     *  It computes the upper quasi-triangular matrix T of the Schur decomposition of H\n     *  When computeU is true, this routine computes the matrix U such that \n     *  A = U T U^T =  (QZ) T (QZ)^T = Q H Q^T where A is the initial matrix\n     * \n     * NOTE Q is referenced if computeU is true; so, if the initial orthogonal matrix\n     * is not available, the user should give an identity matrix (Q.setIdentity())\n     * \n     * \\sa compute(const MatrixType&, bool)\n     */\n    template<typename HessMatrixType, typename OrthMatrixType>\n    RealSchur& computeFromHessenberg(const HessMatrixType& matrixH, const OrthMatrixType& matrixQ,  bool computeU);\n    /** \\brief Reports whether previous computation was successful.\n      *\n      * \\returns \\c Success if computation was succesful, \\c NoConvergence otherwise.\n      */\n    ComputationInfo info() const\n    {\n      eigen_assert(m_isInitialized && \"RealSchur is not initialized.\");\n      return m_info;\n    }\n\n    /** \\brief Sets the maximum number of iterations allowed. \n      *\n      * If not specified by the user, the maximum number of iterations is m_maxIterationsPerRow times the size\n      * of the matrix.\n      */\n    RealSchur& setMaxIterations(Index maxIters)\n    {\n      m_maxIters = maxIters;\n      return *this;\n    }\n\n    /** \\brief Returns the maximum number of iterations. */\n    Index getMaxIterations()\n    {\n      return m_maxIters;\n    }\n\n    /** \\brief Maximum number of iterations per row.\n      *\n      * If not otherwise specified, the maximum number of iterations is this number times the size of the\n      * matrix. It is currently set to 40.\n      */\n    static const int m_maxIterationsPerRow = 40;\n\n  private:\n    \n    MatrixType m_matT;\n    MatrixType m_matU;\n    ColumnVectorType m_workspaceVector;\n    HessenbergDecomposition<MatrixType> m_hess;\n    ComputationInfo m_info;\n    bool m_isInitialized;\n    bool m_matUisUptodate;\n    Index m_maxIters;\n\n    typedef Matrix<Scalar,3,1> Vector3s;\n\n    Scalar computeNormOfT();\n    Index findSmallSubdiagEntry(Index iu);\n    void splitOffTwoRows(Index iu, bool computeU, const Scalar& exshift);\n    void computeShift(Index iu, Index iter, Scalar& exshift, Vector3s& shiftInfo);\n    void initFrancisQRStep(Index il, Index iu, const Vector3s& shiftInfo, Index& im, Vector3s& firstHouseholderVector);\n    void performFrancisQRStep(Index il, Index im, Index iu, bool computeU, const Vector3s& firstHouseholderVector, Scalar* workspace);\n};\n\n\ntemplate<typename MatrixType>\ntemplate<typename InputType>\nRealSchur<MatrixType>& RealSchur<MatrixType>::compute(const EigenBase<InputType>& matrix, bool computeU)\n{\n  eigen_assert(matrix.cols() == matrix.rows());\n  Index maxIters = m_maxIters;\n  if (maxIters == -1)\n    maxIters = m_maxIterationsPerRow * matrix.rows();\n\n  Scalar scale = matrix.derived().cwiseAbs().maxCoeff();\n\n  // Step 1. Reduce to Hessenberg form\n  m_hess.compute(matrix.derived()/scale);\n\n  // Step 2. Reduce to real Schur form  \n  computeFromHessenberg(m_hess.matrixH(), m_hess.matrixQ(), computeU);\n\n  m_matT *= scale;\n  \n  return *this;\n}\ntemplate<typename MatrixType>\ntemplate<typename HessMatrixType, typename OrthMatrixType>\nRealSchur<MatrixType>& RealSchur<MatrixType>::computeFromHessenberg(const HessMatrixType& matrixH, const OrthMatrixType& matrixQ,  bool computeU)\n{\n  using std::abs;\n\n  m_matT = matrixH;\n  if(computeU)\n    m_matU = matrixQ;\n  \n  Index maxIters = m_maxIters;\n  if (maxIters == -1)\n    maxIters = m_maxIterationsPerRow * matrixH.rows();\n  m_workspaceVector.resize(m_matT.cols());\n  Scalar* workspace = &m_workspaceVector.coeffRef(0);\n\n  // The matrix m_matT is divided in three parts. \n  // Rows 0,...,il-1 are decoupled from the rest because m_matT(il,il-1) is zero. \n  // Rows il,...,iu is the part we are working on (the active window).\n  // Rows iu+1,...,end are already brought in triangular form.\n  Index iu = m_matT.cols() - 1;\n  Index iter = 0;      // iteration count for current eigenvalue\n  Index totalIter = 0; // iteration count for whole matrix\n  Scalar exshift(0);   // sum of exceptional shifts\n  Scalar norm = computeNormOfT();\n\n  if(norm!=0)\n  {\n    while (iu >= 0)\n    {\n      Index il = findSmallSubdiagEntry(iu);\n\n      // Check for convergence\n      if (il == iu) // One root found\n      {\n        m_matT.coeffRef(iu,iu) = m_matT.coeff(iu,iu) + exshift;\n        if (iu > 0)\n          m_matT.coeffRef(iu, iu-1) = Scalar(0);\n        iu--;\n        iter = 0;\n      }\n      else if (il == iu-1) // Two roots found\n      {\n        splitOffTwoRows(iu, computeU, exshift);\n        iu -= 2;\n        iter = 0;\n      }\n      else // No convergence yet\n      {\n        // The firstHouseholderVector vector has to be initialized to something to get rid of a silly GCC warning (-O1 -Wall -DNDEBUG )\n        Vector3s firstHouseholderVector(0,0,0), shiftInfo;\n        computeShift(iu, iter, exshift, shiftInfo);\n        iter = iter + 1;\n        totalIter = totalIter + 1;\n        if (totalIter > maxIters) break;\n        Index im;\n        initFrancisQRStep(il, iu, shiftInfo, im, firstHouseholderVector);\n        performFrancisQRStep(il, im, iu, computeU, firstHouseholderVector, workspace);\n      }\n    }\n  }\n  if(totalIter <= maxIters)\n    m_info = Success;\n  else\n    m_info = NoConvergence;\n\n  m_isInitialized = true;\n  m_matUisUptodate = computeU;\n  return *this;\n}\n\n/** \\internal Computes and returns vector L1 norm of T */\ntemplate<typename MatrixType>\ninline typename MatrixType::Scalar RealSchur<MatrixType>::computeNormOfT()\n{\n  const Index size = m_matT.cols();\n  // FIXME to be efficient the following would requires a triangular reduxion code\n  // Scalar norm = m_matT.upper().cwiseAbs().sum() \n  //               + m_matT.bottomLeftCorner(size-1,size-1).diagonal().cwiseAbs().sum();\n  Scalar norm(0);\n  for (Index j = 0; j < size; ++j)\n    norm += m_matT.col(j).segment(0, (std::min)(size,j+2)).cwiseAbs().sum();\n  return norm;\n}\n\n/** \\internal Look for single small sub-diagonal element and returns its index */\ntemplate<typename MatrixType>\ninline Index RealSchur<MatrixType>::findSmallSubdiagEntry(Index iu)\n{\n  using std::abs;\n  Index res = iu;\n  while (res > 0)\n  {\n    Scalar s = abs(m_matT.coeff(res-1,res-1)) + abs(m_matT.coeff(res,res));\n    if (abs(m_matT.coeff(res,res-1)) <= NumTraits<Scalar>::epsilon() * s)\n      break;\n    res--;\n  }\n  return res;\n}\n\n/** \\internal Update T given that rows iu-1 and iu decouple from the rest. */\ntemplate<typename MatrixType>\ninline void RealSchur<MatrixType>::splitOffTwoRows(Index iu, bool computeU, const Scalar& exshift)\n{\n  using std::sqrt;\n  using std::abs;\n  const Index size = m_matT.cols();\n\n  // The eigenvalues of the 2x2 matrix [a b; c d] are \n  // trace +/- sqrt(discr/4) where discr = tr^2 - 4*det, tr = a + d, det = ad - bc\n  Scalar p = Scalar(0.5) * (m_matT.coeff(iu-1,iu-1) - m_matT.coeff(iu,iu));\n  Scalar q = p * p + m_matT.coeff(iu,iu-1) * m_matT.coeff(iu-1,iu);   // q = tr^2 / 4 - det = discr/4\n  m_matT.coeffRef(iu,iu) += exshift;\n  m_matT.coeffRef(iu-1,iu-1) += exshift;\n\n  if (q >= Scalar(0)) // Two real eigenvalues\n  {\n    Scalar z = sqrt(abs(q));\n    JacobiRotation<Scalar> rot;\n    if (p >= Scalar(0))\n      rot.makeGivens(p + z, m_matT.coeff(iu, iu-1));\n    else\n      rot.makeGivens(p - z, m_matT.coeff(iu, iu-1));\n\n    m_matT.rightCols(size-iu+1).applyOnTheLeft(iu-1, iu, rot.adjoint());\n    m_matT.topRows(iu+1).applyOnTheRight(iu-1, iu, rot);\n    m_matT.coeffRef(iu, iu-1) = Scalar(0); \n    if (computeU)\n      m_matU.applyOnTheRight(iu-1, iu, rot);\n  }\n\n  if (iu > 1) \n    m_matT.coeffRef(iu-1, iu-2) = Scalar(0);\n}\n\n/** \\internal Form shift in shiftInfo, and update exshift if an exceptional shift is performed. */\ntemplate<typename MatrixType>\ninline void RealSchur<MatrixType>::computeShift(Index iu, Index iter, Scalar& exshift, Vector3s& shiftInfo)\n{\n  using std::sqrt;\n  using std::abs;\n  shiftInfo.coeffRef(0) = m_matT.coeff(iu,iu);\n  shiftInfo.coeffRef(1) = m_matT.coeff(iu-1,iu-1);\n  shiftInfo.coeffRef(2) = m_matT.coeff(iu,iu-1) * m_matT.coeff(iu-1,iu);\n\n  // Wilkinson's original ad hoc shift\n  if (iter == 10)\n  {\n    exshift += shiftInfo.coeff(0);\n    for (Index i = 0; i <= iu; ++i)\n      m_matT.coeffRef(i,i) -= shiftInfo.coeff(0);\n    Scalar s = abs(m_matT.coeff(iu,iu-1)) + abs(m_matT.coeff(iu-1,iu-2));\n    shiftInfo.coeffRef(0) = Scalar(0.75) * s;\n    shiftInfo.coeffRef(1) = Scalar(0.75) * s;\n    shiftInfo.coeffRef(2) = Scalar(-0.4375) * s * s;\n  }\n\n  // MATLAB's new ad hoc shift\n  if (iter == 30)\n  {\n    Scalar s = (shiftInfo.coeff(1) - shiftInfo.coeff(0)) / Scalar(2.0);\n    s = s * s + shiftInfo.coeff(2);\n    if (s > Scalar(0))\n    {\n      s = sqrt(s);\n      if (shiftInfo.coeff(1) < shiftInfo.coeff(0))\n        s = -s;\n      s = s + (shiftInfo.coeff(1) - shiftInfo.coeff(0)) / Scalar(2.0);\n      s = shiftInfo.coeff(0) - shiftInfo.coeff(2) / s;\n      exshift += s;\n      for (Index i = 0; i <= iu; ++i)\n        m_matT.coeffRef(i,i) -= s;\n      shiftInfo.setConstant(Scalar(0.964));\n    }\n  }\n}\n\n/** \\internal Compute index im at which Francis QR step starts and the first Householder vector. */\ntemplate<typename MatrixType>\ninline void RealSchur<MatrixType>::initFrancisQRStep(Index il, Index iu, const Vector3s& shiftInfo, Index& im, Vector3s& firstHouseholderVector)\n{\n  using std::abs;\n  Vector3s& v = firstHouseholderVector; // alias to save typing\n\n  for (im = iu-2; im >= il; --im)\n  {\n    const Scalar Tmm = m_matT.coeff(im,im);\n    const Scalar r = shiftInfo.coeff(0) - Tmm;\n    const Scalar s = shiftInfo.coeff(1) - Tmm;\n    v.coeffRef(0) = (r * s - shiftInfo.coeff(2)) / m_matT.coeff(im+1,im) + m_matT.coeff(im,im+1);\n    v.coeffRef(1) = m_matT.coeff(im+1,im+1) - Tmm - r - s;\n    v.coeffRef(2) = m_matT.coeff(im+2,im+1);\n    if (im == il) {\n      break;\n    }\n    const Scalar lhs = m_matT.coeff(im,im-1) * (abs(v.coeff(1)) + abs(v.coeff(2)));\n    const Scalar rhs = v.coeff(0) * (abs(m_matT.coeff(im-1,im-1)) + abs(Tmm) + abs(m_matT.coeff(im+1,im+1)));\n    if (abs(lhs) < NumTraits<Scalar>::epsilon() * rhs)\n      break;\n  }\n}\n\n/** \\internal Perform a Francis QR step involving rows il:iu and columns im:iu. */\ntemplate<typename MatrixType>\ninline void RealSchur<MatrixType>::performFrancisQRStep(Index il, Index im, Index iu, bool computeU, const Vector3s& firstHouseholderVector, Scalar* workspace)\n{\n  eigen_assert(im >= il);\n  eigen_assert(im <= iu-2);\n\n  const Index size = m_matT.cols();\n\n  for (Index k = im; k <= iu-2; ++k)\n  {\n    bool firstIteration = (k == im);\n\n    Vector3s v;\n    if (firstIteration)\n      v = firstHouseholderVector;\n    else\n      v = m_matT.template block<3,1>(k,k-1);\n\n    Scalar tau, beta;\n    Matrix<Scalar, 2, 1> ess;\n    v.makeHouseholder(ess, tau, beta);\n    \n    if (beta != Scalar(0)) // if v is not zero\n    {\n      if (firstIteration && k > il)\n        m_matT.coeffRef(k,k-1) = -m_matT.coeff(k,k-1);\n      else if (!firstIteration)\n        m_matT.coeffRef(k,k-1) = beta;\n\n      // These Householder transformations form the O(n^3) part of the algorithm\n      m_matT.block(k, k, 3, size-k).applyHouseholderOnTheLeft(ess, tau, workspace);\n      m_matT.block(0, k, (std::min)(iu,k+3) + 1, 3).applyHouseholderOnTheRight(ess, tau, workspace);\n      if (computeU)\n        m_matU.block(0, k, size, 3).applyHouseholderOnTheRight(ess, tau, workspace);\n    }\n  }\n\n  Matrix<Scalar, 2, 1> v = m_matT.template block<2,1>(iu-1, iu-2);\n  Scalar tau, beta;\n  Matrix<Scalar, 1, 1> ess;\n  v.makeHouseholder(ess, tau, beta);\n\n  if (beta != Scalar(0)) // if v is not zero\n  {\n    m_matT.coeffRef(iu-1, iu-2) = beta;\n    m_matT.block(iu-1, iu-1, 2, size-iu+1).applyHouseholderOnTheLeft(ess, tau, workspace);\n    m_matT.block(0, iu-1, iu+1, 2).applyHouseholderOnTheRight(ess, tau, workspace);\n    if (computeU)\n      m_matU.block(0, iu-1, size, 2).applyHouseholderOnTheRight(ess, tau, workspace);\n  }\n\n  // clean up pollution due to round-off errors\n  for (Index i = im+2; i <= iu; ++i)\n  {\n    m_matT.coeffRef(i,i-2) = Scalar(0);\n    if (i > im+2)\n      m_matT.coeffRef(i,i-3) = Scalar(0);\n  }\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_REAL_SCHUR_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Eigenvalues/RealSchur_LAPACKE.h",
    "content": "/*\n Copyright (c) 2011, Intel Corporation. All rights reserved.\n\n Redistribution and use in source and binary forms, with or without modification,\n are permitted provided that the following conditions are met:\n\n * Redistributions of source code must retain the above copyright notice, this\n   list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright notice,\n   this list of conditions and the following disclaimer in the documentation\n   and/or other materials provided with the distribution.\n * Neither the name of Intel Corporation nor the names of its contributors may\n   be used to endorse or promote products derived from this software without\n   specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n ********************************************************************************\n *   Content : Eigen bindings to LAPACKe\n *    Real Schur needed to real unsymmetrical eigenvalues/eigenvectors.\n ********************************************************************************\n*/\n\n#ifndef EIGEN_REAL_SCHUR_LAPACKE_H\n#define EIGEN_REAL_SCHUR_LAPACKE_H\n\nnamespace Eigen { \n\n/** \\internal Specialization for the data types supported by LAPACKe */\n\n#define EIGEN_LAPACKE_SCHUR_REAL(EIGTYPE, LAPACKE_TYPE, LAPACKE_PREFIX, LAPACKE_PREFIX_U, EIGCOLROW, LAPACKE_COLROW) \\\ntemplate<> template<typename InputType> inline \\\nRealSchur<Matrix<EIGTYPE, Dynamic, Dynamic, EIGCOLROW> >& \\\nRealSchur<Matrix<EIGTYPE, Dynamic, Dynamic, EIGCOLROW> >::compute(const EigenBase<InputType>& matrix, bool computeU) \\\n{ \\\n  eigen_assert(matrix.cols() == matrix.rows()); \\\n\\\n  lapack_int n = internal::convert_index<lapack_int>(matrix.cols()), sdim, info; \\\n  lapack_int matrix_order = LAPACKE_COLROW; \\\n  char jobvs, sort='N'; \\\n  LAPACK_##LAPACKE_PREFIX_U##_SELECT2 select = 0; \\\n  jobvs = (computeU) ? 'V' : 'N'; \\\n  m_matU.resize(n, n); \\\n  lapack_int ldvs  = internal::convert_index<lapack_int>(m_matU.outerStride()); \\\n  m_matT = matrix; \\\n  lapack_int lda = internal::convert_index<lapack_int>(m_matT.outerStride()); \\\n  Matrix<EIGTYPE, Dynamic, Dynamic> wr, wi; \\\n  wr.resize(n, 1); wi.resize(n, 1); \\\n  info = LAPACKE_##LAPACKE_PREFIX##gees( matrix_order, jobvs, sort, select, n, (LAPACKE_TYPE*)m_matT.data(), lda, &sdim, (LAPACKE_TYPE*)wr.data(), (LAPACKE_TYPE*)wi.data(), (LAPACKE_TYPE*)m_matU.data(), ldvs ); \\\n  if(info == 0) \\\n    m_info = Success; \\\n  else \\\n    m_info = NoConvergence; \\\n\\\n  m_isInitialized = true; \\\n  m_matUisUptodate = computeU; \\\n  return *this; \\\n\\\n}\n\nEIGEN_LAPACKE_SCHUR_REAL(double,   double, d, D, ColMajor, LAPACK_COL_MAJOR)\nEIGEN_LAPACKE_SCHUR_REAL(float,    float,  s, S, ColMajor, LAPACK_COL_MAJOR)\nEIGEN_LAPACKE_SCHUR_REAL(double,   double, d, D, RowMajor, LAPACK_ROW_MAJOR)\nEIGEN_LAPACKE_SCHUR_REAL(float,    float,  s, S, RowMajor, LAPACK_ROW_MAJOR)\n\n} // end namespace Eigen\n\n#endif // EIGEN_REAL_SCHUR_LAPACKE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Eigenvalues/SelfAdjointEigenSolver.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2010 Jitse Niesen <jitse@maths.leeds.ac.uk>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SELFADJOINTEIGENSOLVER_H\n#define EIGEN_SELFADJOINTEIGENSOLVER_H\n\n#include \"./Tridiagonalization.h\"\n\nnamespace Eigen { \n\ntemplate<typename _MatrixType>\nclass GeneralizedSelfAdjointEigenSolver;\n\nnamespace internal {\ntemplate<typename SolverType,int Size,bool IsComplex> struct direct_selfadjoint_eigenvalues;\ntemplate<typename MatrixType, typename DiagType, typename SubDiagType>\nComputationInfo computeFromTridiagonal_impl(DiagType& diag, SubDiagType& subdiag, const Index maxIterations, bool computeEigenvectors, MatrixType& eivec);\n}\n\n/** \\eigenvalues_module \\ingroup Eigenvalues_Module\n  *\n  *\n  * \\class SelfAdjointEigenSolver\n  *\n  * \\brief Computes eigenvalues and eigenvectors of selfadjoint matrices\n  *\n  * \\tparam _MatrixType the type of the matrix of which we are computing the\n  * eigendecomposition; this is expected to be an instantiation of the Matrix\n  * class template.\n  *\n  * A matrix \\f$ A \\f$ is selfadjoint if it equals its adjoint. For real\n  * matrices, this means that the matrix is symmetric: it equals its\n  * transpose. This class computes the eigenvalues and eigenvectors of a\n  * selfadjoint matrix. These are the scalars \\f$ \\lambda \\f$ and vectors\n  * \\f$ v \\f$ such that \\f$ Av = \\lambda v \\f$.  The eigenvalues of a\n  * selfadjoint matrix are always real. If \\f$ D \\f$ is a diagonal matrix with\n  * the eigenvalues on the diagonal, and \\f$ V \\f$ is a matrix with the\n  * eigenvectors as its columns, then \\f$ A = V D V^{-1} \\f$ (for selfadjoint\n  * matrices, the matrix \\f$ V \\f$ is always invertible). This is called the\n  * eigendecomposition.\n  *\n  * The algorithm exploits the fact that the matrix is selfadjoint, making it\n  * faster and more accurate than the general purpose eigenvalue algorithms\n  * implemented in EigenSolver and ComplexEigenSolver.\n  *\n  * Only the \\b lower \\b triangular \\b part of the input matrix is referenced.\n  *\n  * Call the function compute() to compute the eigenvalues and eigenvectors of\n  * a given matrix. Alternatively, you can use the\n  * SelfAdjointEigenSolver(const MatrixType&, int) constructor which computes\n  * the eigenvalues and eigenvectors at construction time. Once the eigenvalue\n  * and eigenvectors are computed, they can be retrieved with the eigenvalues()\n  * and eigenvectors() functions.\n  *\n  * The documentation for SelfAdjointEigenSolver(const MatrixType&, int)\n  * contains an example of the typical use of this class.\n  *\n  * To solve the \\em generalized eigenvalue problem \\f$ Av = \\lambda Bv \\f$ and\n  * the likes, see the class GeneralizedSelfAdjointEigenSolver.\n  *\n  * \\sa MatrixBase::eigenvalues(), class EigenSolver, class ComplexEigenSolver\n  */\ntemplate<typename _MatrixType> class SelfAdjointEigenSolver\n{\n  public:\n\n    typedef _MatrixType MatrixType;\n    enum {\n      Size = MatrixType::RowsAtCompileTime,\n      ColsAtCompileTime = MatrixType::ColsAtCompileTime,\n      Options = MatrixType::Options,\n      MaxColsAtCompileTime = MatrixType::MaxColsAtCompileTime\n    };\n    \n    /** \\brief Scalar type for matrices of type \\p _MatrixType. */\n    typedef typename MatrixType::Scalar Scalar;\n    typedef Eigen::Index Index; ///< \\deprecated since Eigen 3.3\n    \n    typedef Matrix<Scalar,Size,Size,ColMajor,MaxColsAtCompileTime,MaxColsAtCompileTime> EigenvectorsType;\n\n    /** \\brief Real scalar type for \\p _MatrixType.\n      *\n      * This is just \\c Scalar if #Scalar is real (e.g., \\c float or\n      * \\c double), and the type of the real part of \\c Scalar if #Scalar is\n      * complex.\n      */\n    typedef typename NumTraits<Scalar>::Real RealScalar;\n    \n    friend struct internal::direct_selfadjoint_eigenvalues<SelfAdjointEigenSolver,Size,NumTraits<Scalar>::IsComplex>;\n\n    /** \\brief Type for vector of eigenvalues as returned by eigenvalues().\n      *\n      * This is a column vector with entries of type #RealScalar.\n      * The length of the vector is the size of \\p _MatrixType.\n      */\n    typedef typename internal::plain_col_type<MatrixType, RealScalar>::type RealVectorType;\n    typedef Tridiagonalization<MatrixType> TridiagonalizationType;\n    typedef typename TridiagonalizationType::SubDiagonalType SubDiagonalType;\n\n    /** \\brief Default constructor for fixed-size matrices.\n      *\n      * The default constructor is useful in cases in which the user intends to\n      * perform decompositions via compute(). This constructor\n      * can only be used if \\p _MatrixType is a fixed-size matrix; use\n      * SelfAdjointEigenSolver(Index) for dynamic-size matrices.\n      *\n      * Example: \\include SelfAdjointEigenSolver_SelfAdjointEigenSolver.cpp\n      * Output: \\verbinclude SelfAdjointEigenSolver_SelfAdjointEigenSolver.out\n      */\n    EIGEN_DEVICE_FUNC\n    SelfAdjointEigenSolver()\n        : m_eivec(),\n          m_eivalues(),\n          m_subdiag(),\n          m_isInitialized(false)\n    { }\n\n    /** \\brief Constructor, pre-allocates memory for dynamic-size matrices.\n      *\n      * \\param [in]  size  Positive integer, size of the matrix whose\n      * eigenvalues and eigenvectors will be computed.\n      *\n      * This constructor is useful for dynamic-size matrices, when the user\n      * intends to perform decompositions via compute(). The \\p size\n      * parameter is only used as a hint. It is not an error to give a wrong\n      * \\p size, but it may impair performance.\n      *\n      * \\sa compute() for an example\n      */\n    EIGEN_DEVICE_FUNC\n    explicit SelfAdjointEigenSolver(Index size)\n        : m_eivec(size, size),\n          m_eivalues(size),\n          m_subdiag(size > 1 ? size - 1 : 1),\n          m_isInitialized(false)\n    {}\n\n    /** \\brief Constructor; computes eigendecomposition of given matrix.\n      *\n      * \\param[in]  matrix  Selfadjoint matrix whose eigendecomposition is to\n      *    be computed. Only the lower triangular part of the matrix is referenced.\n      * \\param[in]  options Can be #ComputeEigenvectors (default) or #EigenvaluesOnly.\n      *\n      * This constructor calls compute(const MatrixType&, int) to compute the\n      * eigenvalues of the matrix \\p matrix. The eigenvectors are computed if\n      * \\p options equals #ComputeEigenvectors.\n      *\n      * Example: \\include SelfAdjointEigenSolver_SelfAdjointEigenSolver_MatrixType.cpp\n      * Output: \\verbinclude SelfAdjointEigenSolver_SelfAdjointEigenSolver_MatrixType.out\n      *\n      * \\sa compute(const MatrixType&, int)\n      */\n    template<typename InputType>\n    EIGEN_DEVICE_FUNC\n    explicit SelfAdjointEigenSolver(const EigenBase<InputType>& matrix, int options = ComputeEigenvectors)\n      : m_eivec(matrix.rows(), matrix.cols()),\n        m_eivalues(matrix.cols()),\n        m_subdiag(matrix.rows() > 1 ? matrix.rows() - 1 : 1),\n        m_isInitialized(false)\n    {\n      compute(matrix.derived(), options);\n    }\n\n    /** \\brief Computes eigendecomposition of given matrix.\n      *\n      * \\param[in]  matrix  Selfadjoint matrix whose eigendecomposition is to\n      *    be computed. Only the lower triangular part of the matrix is referenced.\n      * \\param[in]  options Can be #ComputeEigenvectors (default) or #EigenvaluesOnly.\n      * \\returns    Reference to \\c *this\n      *\n      * This function computes the eigenvalues of \\p matrix.  The eigenvalues()\n      * function can be used to retrieve them.  If \\p options equals #ComputeEigenvectors,\n      * then the eigenvectors are also computed and can be retrieved by\n      * calling eigenvectors().\n      *\n      * This implementation uses a symmetric QR algorithm. The matrix is first\n      * reduced to tridiagonal form using the Tridiagonalization class. The\n      * tridiagonal matrix is then brought to diagonal form with implicit\n      * symmetric QR steps with Wilkinson shift. Details can be found in\n      * Section 8.3 of Golub \\& Van Loan, <i>%Matrix Computations</i>.\n      *\n      * The cost of the computation is about \\f$ 9n^3 \\f$ if the eigenvectors\n      * are required and \\f$ 4n^3/3 \\f$ if they are not required.\n      *\n      * This method reuses the memory in the SelfAdjointEigenSolver object that\n      * was allocated when the object was constructed, if the size of the\n      * matrix does not change.\n      *\n      * Example: \\include SelfAdjointEigenSolver_compute_MatrixType.cpp\n      * Output: \\verbinclude SelfAdjointEigenSolver_compute_MatrixType.out\n      *\n      * \\sa SelfAdjointEigenSolver(const MatrixType&, int)\n      */\n    template<typename InputType>\n    EIGEN_DEVICE_FUNC\n    SelfAdjointEigenSolver& compute(const EigenBase<InputType>& matrix, int options = ComputeEigenvectors);\n    \n    /** \\brief Computes eigendecomposition of given matrix using a closed-form algorithm\n      *\n      * This is a variant of compute(const MatrixType&, int options) which\n      * directly solves the underlying polynomial equation.\n      * \n      * Currently only 2x2 and 3x3 matrices for which the sizes are known at compile time are supported (e.g., Matrix3d).\n      * \n      * This method is usually significantly faster than the QR iterative algorithm\n      * but it might also be less accurate. It is also worth noting that\n      * for 3x3 matrices it involves trigonometric operations which are\n      * not necessarily available for all scalar types.\n      * \n      * For the 3x3 case, we observed the following worst case relative error regarding the eigenvalues:\n      *   - double: 1e-8\n      *   - float:  1e-3\n      *\n      * \\sa compute(const MatrixType&, int options)\n      */\n    EIGEN_DEVICE_FUNC\n    SelfAdjointEigenSolver& computeDirect(const MatrixType& matrix, int options = ComputeEigenvectors);\n\n    /**\n      *\\brief Computes the eigen decomposition from a tridiagonal symmetric matrix\n      *\n      * \\param[in] diag The vector containing the diagonal of the matrix.\n      * \\param[in] subdiag The subdiagonal of the matrix.\n      * \\param[in] options Can be #ComputeEigenvectors (default) or #EigenvaluesOnly.\n      * \\returns Reference to \\c *this\n      *\n      * This function assumes that the matrix has been reduced to tridiagonal form.\n      *\n      * \\sa compute(const MatrixType&, int) for more information\n      */\n    SelfAdjointEigenSolver& computeFromTridiagonal(const RealVectorType& diag, const SubDiagonalType& subdiag , int options=ComputeEigenvectors);\n\n    /** \\brief Returns the eigenvectors of given matrix.\n      *\n      * \\returns  A const reference to the matrix whose columns are the eigenvectors.\n      *\n      * \\pre The eigenvectors have been computed before.\n      *\n      * Column \\f$ k \\f$ of the returned matrix is an eigenvector corresponding\n      * to eigenvalue number \\f$ k \\f$ as returned by eigenvalues().  The\n      * eigenvectors are normalized to have (Euclidean) norm equal to one. If\n      * this object was used to solve the eigenproblem for the selfadjoint\n      * matrix \\f$ A \\f$, then the matrix returned by this function is the\n      * matrix \\f$ V \\f$ in the eigendecomposition \\f$ A = V D V^{-1} \\f$.\n      *\n      * Example: \\include SelfAdjointEigenSolver_eigenvectors.cpp\n      * Output: \\verbinclude SelfAdjointEigenSolver_eigenvectors.out\n      *\n      * \\sa eigenvalues()\n      */\n    EIGEN_DEVICE_FUNC\n    const EigenvectorsType& eigenvectors() const\n    {\n      eigen_assert(m_isInitialized && \"SelfAdjointEigenSolver is not initialized.\");\n      eigen_assert(m_eigenvectorsOk && \"The eigenvectors have not been computed together with the eigenvalues.\");\n      return m_eivec;\n    }\n\n    /** \\brief Returns the eigenvalues of given matrix.\n      *\n      * \\returns A const reference to the column vector containing the eigenvalues.\n      *\n      * \\pre The eigenvalues have been computed before.\n      *\n      * The eigenvalues are repeated according to their algebraic multiplicity,\n      * so there are as many eigenvalues as rows in the matrix. The eigenvalues\n      * are sorted in increasing order.\n      *\n      * Example: \\include SelfAdjointEigenSolver_eigenvalues.cpp\n      * Output: \\verbinclude SelfAdjointEigenSolver_eigenvalues.out\n      *\n      * \\sa eigenvectors(), MatrixBase::eigenvalues()\n      */\n    EIGEN_DEVICE_FUNC\n    const RealVectorType& eigenvalues() const\n    {\n      eigen_assert(m_isInitialized && \"SelfAdjointEigenSolver is not initialized.\");\n      return m_eivalues;\n    }\n\n    /** \\brief Computes the positive-definite square root of the matrix.\n      *\n      * \\returns the positive-definite square root of the matrix\n      *\n      * \\pre The eigenvalues and eigenvectors of a positive-definite matrix\n      * have been computed before.\n      *\n      * The square root of a positive-definite matrix \\f$ A \\f$ is the\n      * positive-definite matrix whose square equals \\f$ A \\f$. This function\n      * uses the eigendecomposition \\f$ A = V D V^{-1} \\f$ to compute the\n      * square root as \\f$ A^{1/2} = V D^{1/2} V^{-1} \\f$.\n      *\n      * Example: \\include SelfAdjointEigenSolver_operatorSqrt.cpp\n      * Output: \\verbinclude SelfAdjointEigenSolver_operatorSqrt.out\n      *\n      * \\sa operatorInverseSqrt(), <a href=\"unsupported/group__MatrixFunctions__Module.html\">MatrixFunctions Module</a>\n      */\n    EIGEN_DEVICE_FUNC\n    MatrixType operatorSqrt() const\n    {\n      eigen_assert(m_isInitialized && \"SelfAdjointEigenSolver is not initialized.\");\n      eigen_assert(m_eigenvectorsOk && \"The eigenvectors have not been computed together with the eigenvalues.\");\n      return m_eivec * m_eivalues.cwiseSqrt().asDiagonal() * m_eivec.adjoint();\n    }\n\n    /** \\brief Computes the inverse square root of the matrix.\n      *\n      * \\returns the inverse positive-definite square root of the matrix\n      *\n      * \\pre The eigenvalues and eigenvectors of a positive-definite matrix\n      * have been computed before.\n      *\n      * This function uses the eigendecomposition \\f$ A = V D V^{-1} \\f$ to\n      * compute the inverse square root as \\f$ V D^{-1/2} V^{-1} \\f$. This is\n      * cheaper than first computing the square root with operatorSqrt() and\n      * then its inverse with MatrixBase::inverse().\n      *\n      * Example: \\include SelfAdjointEigenSolver_operatorInverseSqrt.cpp\n      * Output: \\verbinclude SelfAdjointEigenSolver_operatorInverseSqrt.out\n      *\n      * \\sa operatorSqrt(), MatrixBase::inverse(), <a href=\"unsupported/group__MatrixFunctions__Module.html\">MatrixFunctions Module</a>\n      */\n    EIGEN_DEVICE_FUNC\n    MatrixType operatorInverseSqrt() const\n    {\n      eigen_assert(m_isInitialized && \"SelfAdjointEigenSolver is not initialized.\");\n      eigen_assert(m_eigenvectorsOk && \"The eigenvectors have not been computed together with the eigenvalues.\");\n      return m_eivec * m_eivalues.cwiseInverse().cwiseSqrt().asDiagonal() * m_eivec.adjoint();\n    }\n\n    /** \\brief Reports whether previous computation was successful.\n      *\n      * \\returns \\c Success if computation was succesful, \\c NoConvergence otherwise.\n      */\n    EIGEN_DEVICE_FUNC\n    ComputationInfo info() const\n    {\n      eigen_assert(m_isInitialized && \"SelfAdjointEigenSolver is not initialized.\");\n      return m_info;\n    }\n\n    /** \\brief Maximum number of iterations.\n      *\n      * The algorithm terminates if it does not converge within m_maxIterations * n iterations, where n\n      * denotes the size of the matrix. This value is currently set to 30 (copied from LAPACK).\n      */\n    static const int m_maxIterations = 30;\n\n  protected:\n    static void check_template_parameters()\n    {\n      EIGEN_STATIC_ASSERT_NON_INTEGER(Scalar);\n    }\n    \n    EigenvectorsType m_eivec;\n    RealVectorType m_eivalues;\n    typename TridiagonalizationType::SubDiagonalType m_subdiag;\n    ComputationInfo m_info;\n    bool m_isInitialized;\n    bool m_eigenvectorsOk;\n};\n\nnamespace internal {\n/** \\internal\n  *\n  * \\eigenvalues_module \\ingroup Eigenvalues_Module\n  *\n  * Performs a QR step on a tridiagonal symmetric matrix represented as a\n  * pair of two vectors \\a diag and \\a subdiag.\n  *\n  * \\param diag the diagonal part of the input selfadjoint tridiagonal matrix\n  * \\param subdiag the sub-diagonal part of the input selfadjoint tridiagonal matrix\n  * \\param start starting index of the submatrix to work on\n  * \\param end last+1 index of the submatrix to work on\n  * \\param matrixQ pointer to the column-major matrix holding the eigenvectors, can be 0\n  * \\param n size of the input matrix\n  *\n  * For compilation efficiency reasons, this procedure does not use eigen expression\n  * for its arguments.\n  *\n  * Implemented from Golub's \"Matrix Computations\", algorithm 8.3.2:\n  * \"implicit symmetric QR step with Wilkinson shift\"\n  */\ntemplate<int StorageOrder,typename RealScalar, typename Scalar, typename Index>\nEIGEN_DEVICE_FUNC\nstatic void tridiagonal_qr_step(RealScalar* diag, RealScalar* subdiag, Index start, Index end, Scalar* matrixQ, Index n);\n}\n\ntemplate<typename MatrixType>\ntemplate<typename InputType>\nEIGEN_DEVICE_FUNC\nSelfAdjointEigenSolver<MatrixType>& SelfAdjointEigenSolver<MatrixType>\n::compute(const EigenBase<InputType>& a_matrix, int options)\n{\n  check_template_parameters();\n  \n  const InputType &matrix(a_matrix.derived());\n  \n  using std::abs;\n  eigen_assert(matrix.cols() == matrix.rows());\n  eigen_assert((options&~(EigVecMask|GenEigMask))==0\n          && (options&EigVecMask)!=EigVecMask\n          && \"invalid option parameter\");\n  bool computeEigenvectors = (options&ComputeEigenvectors)==ComputeEigenvectors;\n  Index n = matrix.cols();\n  m_eivalues.resize(n,1);\n\n  if(n==1)\n  {\n    m_eivalues.coeffRef(0,0) = numext::real(matrix.diagonal()[0]);\n    if(computeEigenvectors)\n      m_eivec.setOnes(n,n);\n    m_info = Success;\n    m_isInitialized = true;\n    m_eigenvectorsOk = computeEigenvectors;\n    return *this;\n  }\n\n  // declare some aliases\n  RealVectorType& diag = m_eivalues;\n  EigenvectorsType& mat = m_eivec;\n\n  // map the matrix coefficients to [-1:1] to avoid over- and underflow.\n  mat = matrix.template triangularView<Lower>();\n  RealScalar scale = mat.cwiseAbs().maxCoeff();\n  if(scale==RealScalar(0)) scale = RealScalar(1);\n  mat.template triangularView<Lower>() /= scale;\n  m_subdiag.resize(n-1);\n  internal::tridiagonalization_inplace(mat, diag, m_subdiag, computeEigenvectors);\n\n  m_info = internal::computeFromTridiagonal_impl(diag, m_subdiag, m_maxIterations, computeEigenvectors, m_eivec);\n  \n  // scale back the eigen values\n  m_eivalues *= scale;\n\n  m_isInitialized = true;\n  m_eigenvectorsOk = computeEigenvectors;\n  return *this;\n}\n\ntemplate<typename MatrixType>\nSelfAdjointEigenSolver<MatrixType>& SelfAdjointEigenSolver<MatrixType>\n::computeFromTridiagonal(const RealVectorType& diag, const SubDiagonalType& subdiag , int options)\n{\n  //TODO : Add an option to scale the values beforehand\n  bool computeEigenvectors = (options&ComputeEigenvectors)==ComputeEigenvectors;\n\n  m_eivalues = diag;\n  m_subdiag = subdiag;\n  if (computeEigenvectors)\n  {\n    m_eivec.setIdentity(diag.size(), diag.size());\n  }\n  m_info = internal::computeFromTridiagonal_impl(m_eivalues, m_subdiag, m_maxIterations, computeEigenvectors, m_eivec);\n\n  m_isInitialized = true;\n  m_eigenvectorsOk = computeEigenvectors;\n  return *this;\n}\n\nnamespace internal {\n/**\n  * \\internal\n  * \\brief Compute the eigendecomposition from a tridiagonal matrix\n  *\n  * \\param[in,out] diag : On input, the diagonal of the matrix, on output the eigenvalues\n  * \\param[in,out] subdiag : The subdiagonal part of the matrix (entries are modified during the decomposition)\n  * \\param[in] maxIterations : the maximum number of iterations\n  * \\param[in] computeEigenvectors : whether the eigenvectors have to be computed or not\n  * \\param[out] eivec : The matrix to store the eigenvectors if computeEigenvectors==true. Must be allocated on input.\n  * \\returns \\c Success or \\c NoConvergence\n  */\ntemplate<typename MatrixType, typename DiagType, typename SubDiagType>\nComputationInfo computeFromTridiagonal_impl(DiagType& diag, SubDiagType& subdiag, const Index maxIterations, bool computeEigenvectors, MatrixType& eivec)\n{\n  using std::abs;\n\n  ComputationInfo info;\n  typedef typename MatrixType::Scalar Scalar;\n\n  Index n = diag.size();\n  Index end = n-1;\n  Index start = 0;\n  Index iter = 0; // total number of iterations\n  \n  typedef typename DiagType::RealScalar RealScalar;\n  const RealScalar considerAsZero = (std::numeric_limits<RealScalar>::min)();\n  const RealScalar precision = RealScalar(2)*NumTraits<RealScalar>::epsilon();\n  \n  while (end>0)\n  {\n    for (Index i = start; i<end; ++i)\n      if (internal::isMuchSmallerThan(abs(subdiag[i]),(abs(diag[i])+abs(diag[i+1])),precision) || abs(subdiag[i]) <= considerAsZero)\n        subdiag[i] = 0;\n\n    // find the largest unreduced block\n    while (end>0 && subdiag[end-1]==RealScalar(0))\n    {\n      end--;\n    }\n    if (end<=0)\n      break;\n\n    // if we spent too many iterations, we give up\n    iter++;\n    if(iter > maxIterations * n) break;\n\n    start = end - 1;\n    while (start>0 && subdiag[start-1]!=0)\n      start--;\n\n    internal::tridiagonal_qr_step<MatrixType::Flags&RowMajorBit ? RowMajor : ColMajor>(diag.data(), subdiag.data(), start, end, computeEigenvectors ? eivec.data() : (Scalar*)0, n);\n  }\n  if (iter <= maxIterations * n)\n    info = Success;\n  else\n    info = NoConvergence;\n\n  // Sort eigenvalues and corresponding vectors.\n  // TODO make the sort optional ?\n  // TODO use a better sort algorithm !!\n  if (info == Success)\n  {\n    for (Index i = 0; i < n-1; ++i)\n    {\n      Index k;\n      diag.segment(i,n-i).minCoeff(&k);\n      if (k > 0)\n      {\n        std::swap(diag[i], diag[k+i]);\n        if(computeEigenvectors)\n          eivec.col(i).swap(eivec.col(k+i));\n      }\n    }\n  }\n  return info;\n}\n  \ntemplate<typename SolverType,int Size,bool IsComplex> struct direct_selfadjoint_eigenvalues\n{\n  EIGEN_DEVICE_FUNC\n  static inline void run(SolverType& eig, const typename SolverType::MatrixType& A, int options)\n  { eig.compute(A,options); }\n};\n\ntemplate<typename SolverType> struct direct_selfadjoint_eigenvalues<SolverType,3,false>\n{\n  typedef typename SolverType::MatrixType MatrixType;\n  typedef typename SolverType::RealVectorType VectorType;\n  typedef typename SolverType::Scalar Scalar;\n  typedef typename SolverType::EigenvectorsType EigenvectorsType;\n  \n\n  /** \\internal\n   * Computes the roots of the characteristic polynomial of \\a m.\n   * For numerical stability m.trace() should be near zero and to avoid over- or underflow m should be normalized.\n   */\n  EIGEN_DEVICE_FUNC\n  static inline void computeRoots(const MatrixType& m, VectorType& roots)\n  {\n    EIGEN_USING_STD_MATH(sqrt)\n    EIGEN_USING_STD_MATH(atan2)\n    EIGEN_USING_STD_MATH(cos)\n    EIGEN_USING_STD_MATH(sin)\n    const Scalar s_inv3 = Scalar(1)/Scalar(3);\n    const Scalar s_sqrt3 = sqrt(Scalar(3));\n\n    // The characteristic equation is x^3 - c2*x^2 + c1*x - c0 = 0.  The\n    // eigenvalues are the roots to this equation, all guaranteed to be\n    // real-valued, because the matrix is symmetric.\n    Scalar c0 = m(0,0)*m(1,1)*m(2,2) + Scalar(2)*m(1,0)*m(2,0)*m(2,1) - m(0,0)*m(2,1)*m(2,1) - m(1,1)*m(2,0)*m(2,0) - m(2,2)*m(1,0)*m(1,0);\n    Scalar c1 = m(0,0)*m(1,1) - m(1,0)*m(1,0) + m(0,0)*m(2,2) - m(2,0)*m(2,0) + m(1,1)*m(2,2) - m(2,1)*m(2,1);\n    Scalar c2 = m(0,0) + m(1,1) + m(2,2);\n\n    // Construct the parameters used in classifying the roots of the equation\n    // and in solving the equation for the roots in closed form.\n    Scalar c2_over_3 = c2*s_inv3;\n    Scalar a_over_3 = (c2*c2_over_3 - c1)*s_inv3;\n    a_over_3 = numext::maxi(a_over_3, Scalar(0));\n\n    Scalar half_b = Scalar(0.5)*(c0 + c2_over_3*(Scalar(2)*c2_over_3*c2_over_3 - c1));\n\n    Scalar q = a_over_3*a_over_3*a_over_3 - half_b*half_b;\n    q = numext::maxi(q, Scalar(0));\n\n    // Compute the eigenvalues by solving for the roots of the polynomial.\n    Scalar rho = sqrt(a_over_3);\n    Scalar theta = atan2(sqrt(q),half_b)*s_inv3;  // since sqrt(q) > 0, atan2 is in [0, pi] and theta is in [0, pi/3]\n    Scalar cos_theta = cos(theta);\n    Scalar sin_theta = sin(theta);\n    // roots are already sorted, since cos is monotonically decreasing on [0, pi]\n    roots(0) = c2_over_3 - rho*(cos_theta + s_sqrt3*sin_theta); // == 2*rho*cos(theta+2pi/3)\n    roots(1) = c2_over_3 - rho*(cos_theta - s_sqrt3*sin_theta); // == 2*rho*cos(theta+ pi/3)\n    roots(2) = c2_over_3 + Scalar(2)*rho*cos_theta;\n  }\n\n  EIGEN_DEVICE_FUNC\n  static inline bool extract_kernel(MatrixType& mat, Ref<VectorType> res, Ref<VectorType> representative)\n  {\n    using std::abs;\n    Index i0;\n    // Find non-zero column i0 (by construction, there must exist a non zero coefficient on the diagonal):\n    mat.diagonal().cwiseAbs().maxCoeff(&i0);\n    // mat.col(i0) is a good candidate for an orthogonal vector to the current eigenvector,\n    // so let's save it:\n    representative = mat.col(i0);\n    Scalar n0, n1;\n    VectorType c0, c1;\n    n0 = (c0 = representative.cross(mat.col((i0+1)%3))).squaredNorm();\n    n1 = (c1 = representative.cross(mat.col((i0+2)%3))).squaredNorm();\n    if(n0>n1) res = c0/std::sqrt(n0);\n    else      res = c1/std::sqrt(n1);\n\n    return true;\n  }\n\n  EIGEN_DEVICE_FUNC\n  static inline void run(SolverType& solver, const MatrixType& mat, int options)\n  {\n    eigen_assert(mat.cols() == 3 && mat.cols() == mat.rows());\n    eigen_assert((options&~(EigVecMask|GenEigMask))==0\n            && (options&EigVecMask)!=EigVecMask\n            && \"invalid option parameter\");\n    bool computeEigenvectors = (options&ComputeEigenvectors)==ComputeEigenvectors;\n    \n    EigenvectorsType& eivecs = solver.m_eivec;\n    VectorType& eivals = solver.m_eivalues;\n  \n    // Shift the matrix to the mean eigenvalue and map the matrix coefficients to [-1:1] to avoid over- and underflow.\n    Scalar shift = mat.trace() / Scalar(3);\n    // TODO Avoid this copy. Currently it is necessary to suppress bogus values when determining maxCoeff and for computing the eigenvectors later\n    MatrixType scaledMat = mat.template selfadjointView<Lower>();\n    scaledMat.diagonal().array() -= shift;\n    Scalar scale = scaledMat.cwiseAbs().maxCoeff();\n    if(scale > 0) scaledMat /= scale;   // TODO for scale==0 we could save the remaining operations\n\n    // compute the eigenvalues\n    computeRoots(scaledMat,eivals);\n\n    // compute the eigenvectors\n    if(computeEigenvectors)\n    {\n      if((eivals(2)-eivals(0))<=Eigen::NumTraits<Scalar>::epsilon())\n      {\n        // All three eigenvalues are numerically the same\n        eivecs.setIdentity();\n      }\n      else\n      {\n        MatrixType tmp;\n        tmp = scaledMat;\n\n        // Compute the eigenvector of the most distinct eigenvalue\n        Scalar d0 = eivals(2) - eivals(1);\n        Scalar d1 = eivals(1) - eivals(0);\n        Index k(0), l(2);\n        if(d0 > d1)\n        {\n          numext::swap(k,l);\n          d0 = d1;\n        }\n\n        // Compute the eigenvector of index k\n        {\n          tmp.diagonal().array () -= eivals(k);\n          // By construction, 'tmp' is of rank 2, and its kernel corresponds to the respective eigenvector.\n          extract_kernel(tmp, eivecs.col(k), eivecs.col(l));\n        }\n\n        // Compute eigenvector of index l\n        if(d0<=2*Eigen::NumTraits<Scalar>::epsilon()*d1)\n        {\n          // If d0 is too small, then the two other eigenvalues are numerically the same,\n          // and thus we only have to ortho-normalize the near orthogonal vector we saved above.\n          eivecs.col(l) -= eivecs.col(k).dot(eivecs.col(l))*eivecs.col(l);\n          eivecs.col(l).normalize();\n        }\n        else\n        {\n          tmp = scaledMat;\n          tmp.diagonal().array () -= eivals(l);\n\n          VectorType dummy;\n          extract_kernel(tmp, eivecs.col(l), dummy);\n        }\n\n        // Compute last eigenvector from the other two\n        eivecs.col(1) = eivecs.col(2).cross(eivecs.col(0)).normalized();\n      }\n    }\n\n    // Rescale back to the original size.\n    eivals *= scale;\n    eivals.array() += shift;\n    \n    solver.m_info = Success;\n    solver.m_isInitialized = true;\n    solver.m_eigenvectorsOk = computeEigenvectors;\n  }\n};\n\n// 2x2 direct eigenvalues decomposition, code from Hauke Heibel\ntemplate<typename SolverType> \nstruct direct_selfadjoint_eigenvalues<SolverType,2,false>\n{\n  typedef typename SolverType::MatrixType MatrixType;\n  typedef typename SolverType::RealVectorType VectorType;\n  typedef typename SolverType::Scalar Scalar;\n  typedef typename SolverType::EigenvectorsType EigenvectorsType;\n  \n  EIGEN_DEVICE_FUNC\n  static inline void computeRoots(const MatrixType& m, VectorType& roots)\n  {\n    using std::sqrt;\n    const Scalar t0 = Scalar(0.5) * sqrt( numext::abs2(m(0,0)-m(1,1)) + Scalar(4)*numext::abs2(m(1,0)));\n    const Scalar t1 = Scalar(0.5) * (m(0,0) + m(1,1));\n    roots(0) = t1 - t0;\n    roots(1) = t1 + t0;\n  }\n  \n  EIGEN_DEVICE_FUNC\n  static inline void run(SolverType& solver, const MatrixType& mat, int options)\n  {\n    EIGEN_USING_STD_MATH(sqrt);\n    EIGEN_USING_STD_MATH(abs);\n    \n    eigen_assert(mat.cols() == 2 && mat.cols() == mat.rows());\n    eigen_assert((options&~(EigVecMask|GenEigMask))==0\n            && (options&EigVecMask)!=EigVecMask\n            && \"invalid option parameter\");\n    bool computeEigenvectors = (options&ComputeEigenvectors)==ComputeEigenvectors;\n    \n    EigenvectorsType& eivecs = solver.m_eivec;\n    VectorType& eivals = solver.m_eivalues;\n  \n    // Shift the matrix to the mean eigenvalue and map the matrix coefficients to [-1:1] to avoid over- and underflow.\n    Scalar shift = mat.trace() / Scalar(2);\n    MatrixType scaledMat = mat;\n    scaledMat.coeffRef(0,1) = mat.coeff(1,0);\n    scaledMat.diagonal().array() -= shift;\n    Scalar scale = scaledMat.cwiseAbs().maxCoeff();\n    if(scale > Scalar(0))\n      scaledMat /= scale;\n\n    // Compute the eigenvalues\n    computeRoots(scaledMat,eivals);\n\n    // compute the eigen vectors\n    if(computeEigenvectors)\n    {\n      if((eivals(1)-eivals(0))<=abs(eivals(1))*Eigen::NumTraits<Scalar>::epsilon())\n      {\n        eivecs.setIdentity();\n      }\n      else\n      {\n        scaledMat.diagonal().array () -= eivals(1);\n        Scalar a2 = numext::abs2(scaledMat(0,0));\n        Scalar c2 = numext::abs2(scaledMat(1,1));\n        Scalar b2 = numext::abs2(scaledMat(1,0));\n        if(a2>c2)\n        {\n          eivecs.col(1) << -scaledMat(1,0), scaledMat(0,0);\n          eivecs.col(1) /= sqrt(a2+b2);\n        }\n        else\n        {\n          eivecs.col(1) << -scaledMat(1,1), scaledMat(1,0);\n          eivecs.col(1) /= sqrt(c2+b2);\n        }\n\n        eivecs.col(0) << eivecs.col(1).unitOrthogonal();\n      }\n    }\n\n    // Rescale back to the original size.\n    eivals *= scale;\n    eivals.array() += shift;\n\n    solver.m_info = Success;\n    solver.m_isInitialized = true;\n    solver.m_eigenvectorsOk = computeEigenvectors;\n  }\n};\n\n}\n\ntemplate<typename MatrixType>\nEIGEN_DEVICE_FUNC\nSelfAdjointEigenSolver<MatrixType>& SelfAdjointEigenSolver<MatrixType>\n::computeDirect(const MatrixType& matrix, int options)\n{\n  internal::direct_selfadjoint_eigenvalues<SelfAdjointEigenSolver,Size,NumTraits<Scalar>::IsComplex>::run(*this,matrix,options);\n  return *this;\n}\n\nnamespace internal {\ntemplate<int StorageOrder,typename RealScalar, typename Scalar, typename Index>\nEIGEN_DEVICE_FUNC\nstatic void tridiagonal_qr_step(RealScalar* diag, RealScalar* subdiag, Index start, Index end, Scalar* matrixQ, Index n)\n{\n  using std::abs;\n  RealScalar td = (diag[end-1] - diag[end])*RealScalar(0.5);\n  RealScalar e = subdiag[end-1];\n  // Note that thanks to scaling, e^2 or td^2 cannot overflow, however they can still\n  // underflow thus leading to inf/NaN values when using the following commented code:\n//   RealScalar e2 = numext::abs2(subdiag[end-1]);\n//   RealScalar mu = diag[end] - e2 / (td + (td>0 ? 1 : -1) * sqrt(td*td + e2));\n  // This explain the following, somewhat more complicated, version:\n  RealScalar mu = diag[end];\n  if(td==RealScalar(0))\n    mu -= abs(e);\n  else\n  {\n    RealScalar e2 = numext::abs2(subdiag[end-1]);\n    RealScalar h = numext::hypot(td,e);\n    if(e2==RealScalar(0)) mu -= (e / (td + (td>RealScalar(0) ? RealScalar(1) : RealScalar(-1)))) * (e / h);\n    else                  mu -= e2 / (td + (td>RealScalar(0) ? h : -h));\n  }\n  \n  RealScalar x = diag[start] - mu;\n  RealScalar z = subdiag[start];\n  for (Index k = start; k < end; ++k)\n  {\n    JacobiRotation<RealScalar> rot;\n    rot.makeGivens(x, z);\n\n    // do T = G' T G\n    RealScalar sdk = rot.s() * diag[k] + rot.c() * subdiag[k];\n    RealScalar dkp1 = rot.s() * subdiag[k] + rot.c() * diag[k+1];\n\n    diag[k] = rot.c() * (rot.c() * diag[k] - rot.s() * subdiag[k]) - rot.s() * (rot.c() * subdiag[k] - rot.s() * diag[k+1]);\n    diag[k+1] = rot.s() * sdk + rot.c() * dkp1;\n    subdiag[k] = rot.c() * sdk - rot.s() * dkp1;\n    \n\n    if (k > start)\n      subdiag[k - 1] = rot.c() * subdiag[k-1] - rot.s() * z;\n\n    x = subdiag[k];\n\n    if (k < end - 1)\n    {\n      z = -rot.s() * subdiag[k+1];\n      subdiag[k + 1] = rot.c() * subdiag[k+1];\n    }\n    \n    // apply the givens rotation to the unit matrix Q = Q * G\n    if (matrixQ)\n    {\n      // FIXME if StorageOrder == RowMajor this operation is not very efficient\n      Map<Matrix<Scalar,Dynamic,Dynamic,StorageOrder> > q(matrixQ,n,n);\n      q.applyOnTheRight(k,k+1,rot);\n    }\n  }\n}\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_SELFADJOINTEIGENSOLVER_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Eigenvalues/SelfAdjointEigenSolver_LAPACKE.h",
    "content": "/*\n Copyright (c) 2011, Intel Corporation. All rights reserved.\n\n Redistribution and use in source and binary forms, with or without modification,\n are permitted provided that the following conditions are met:\n\n * Redistributions of source code must retain the above copyright notice, this\n   list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright notice,\n   this list of conditions and the following disclaimer in the documentation\n   and/or other materials provided with the distribution.\n * Neither the name of Intel Corporation nor the names of its contributors may\n   be used to endorse or promote products derived from this software without\n   specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n ********************************************************************************\n *   Content : Eigen bindings to LAPACKe\n *    Self-adjoint eigenvalues/eigenvectors.\n ********************************************************************************\n*/\n\n#ifndef EIGEN_SAEIGENSOLVER_LAPACKE_H\n#define EIGEN_SAEIGENSOLVER_LAPACKE_H\n\nnamespace Eigen { \n\n/** \\internal Specialization for the data types supported by LAPACKe */\n\n#define EIGEN_LAPACKE_EIG_SELFADJ(EIGTYPE, LAPACKE_TYPE, LAPACKE_RTYPE, LAPACKE_NAME, EIGCOLROW, LAPACKE_COLROW ) \\\ntemplate<> template<typename InputType> inline \\\nSelfAdjointEigenSolver<Matrix<EIGTYPE, Dynamic, Dynamic, EIGCOLROW> >& \\\nSelfAdjointEigenSolver<Matrix<EIGTYPE, Dynamic, Dynamic, EIGCOLROW> >::compute(const EigenBase<InputType>& matrix, int options) \\\n{ \\\n  eigen_assert(matrix.cols() == matrix.rows()); \\\n  eigen_assert((options&~(EigVecMask|GenEigMask))==0 \\\n          && (options&EigVecMask)!=EigVecMask \\\n          && \"invalid option parameter\"); \\\n  bool computeEigenvectors = (options&ComputeEigenvectors)==ComputeEigenvectors; \\\n  lapack_int n = internal::convert_index<lapack_int>(matrix.cols()), lda, matrix_order, info; \\\n  m_eivalues.resize(n,1); \\\n  m_subdiag.resize(n-1); \\\n  m_eivec = matrix; \\\n\\\n  if(n==1) \\\n  { \\\n    m_eivalues.coeffRef(0,0) = numext::real(m_eivec.coeff(0,0)); \\\n    if(computeEigenvectors) m_eivec.setOnes(n,n); \\\n    m_info = Success; \\\n    m_isInitialized = true; \\\n    m_eigenvectorsOk = computeEigenvectors; \\\n    return *this; \\\n  } \\\n\\\n  lda = internal::convert_index<lapack_int>(m_eivec.outerStride()); \\\n  matrix_order=LAPACKE_COLROW; \\\n  char jobz, uplo='L'/*, range='A'*/; \\\n  jobz = computeEigenvectors ? 'V' : 'N'; \\\n\\\n  info = LAPACKE_##LAPACKE_NAME( matrix_order, jobz, uplo, n, (LAPACKE_TYPE*)m_eivec.data(), lda, (LAPACKE_RTYPE*)m_eivalues.data() ); \\\n  m_info = (info==0) ? Success : NoConvergence; \\\n  m_isInitialized = true; \\\n  m_eigenvectorsOk = computeEigenvectors; \\\n  return *this; \\\n}\n\n\nEIGEN_LAPACKE_EIG_SELFADJ(double,   double,                double, dsyev, ColMajor, LAPACK_COL_MAJOR)\nEIGEN_LAPACKE_EIG_SELFADJ(float,    float,                 float,  ssyev, ColMajor, LAPACK_COL_MAJOR)\nEIGEN_LAPACKE_EIG_SELFADJ(dcomplex, lapack_complex_double, double, zheev, ColMajor, LAPACK_COL_MAJOR)\nEIGEN_LAPACKE_EIG_SELFADJ(scomplex, lapack_complex_float,  float,  cheev, ColMajor, LAPACK_COL_MAJOR)\n\nEIGEN_LAPACKE_EIG_SELFADJ(double,   double,                double, dsyev, RowMajor, LAPACK_ROW_MAJOR)\nEIGEN_LAPACKE_EIG_SELFADJ(float,    float,                 float,  ssyev, RowMajor, LAPACK_ROW_MAJOR)\nEIGEN_LAPACKE_EIG_SELFADJ(dcomplex, lapack_complex_double, double, zheev, RowMajor, LAPACK_ROW_MAJOR)\nEIGEN_LAPACKE_EIG_SELFADJ(scomplex, lapack_complex_float,  float,  cheev, RowMajor, LAPACK_ROW_MAJOR)\n\n} // end namespace Eigen\n\n#endif // EIGEN_SAEIGENSOLVER_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Eigenvalues/Tridiagonalization.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2010 Jitse Niesen <jitse@maths.leeds.ac.uk>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_TRIDIAGONALIZATION_H\n#define EIGEN_TRIDIAGONALIZATION_H\n\nnamespace Eigen { \n\nnamespace internal {\n  \ntemplate<typename MatrixType> struct TridiagonalizationMatrixTReturnType;\ntemplate<typename MatrixType>\nstruct traits<TridiagonalizationMatrixTReturnType<MatrixType> >\n  : public traits<typename MatrixType::PlainObject>\n{\n  typedef typename MatrixType::PlainObject ReturnType; // FIXME shall it be a BandMatrix?\n  enum { Flags = 0 };\n};\n\ntemplate<typename MatrixType, typename CoeffVectorType>\nvoid tridiagonalization_inplace(MatrixType& matA, CoeffVectorType& hCoeffs);\n}\n\n/** \\eigenvalues_module \\ingroup Eigenvalues_Module\n  *\n  *\n  * \\class Tridiagonalization\n  *\n  * \\brief Tridiagonal decomposition of a selfadjoint matrix\n  *\n  * \\tparam _MatrixType the type of the matrix of which we are computing the\n  * tridiagonal decomposition; this is expected to be an instantiation of the\n  * Matrix class template.\n  *\n  * This class performs a tridiagonal decomposition of a selfadjoint matrix \\f$ A \\f$ such that:\n  * \\f$ A = Q T Q^* \\f$ where \\f$ Q \\f$ is unitary and \\f$ T \\f$ a real symmetric tridiagonal matrix.\n  *\n  * A tridiagonal matrix is a matrix which has nonzero elements only on the\n  * main diagonal and the first diagonal below and above it. The Hessenberg\n  * decomposition of a selfadjoint matrix is in fact a tridiagonal\n  * decomposition. This class is used in SelfAdjointEigenSolver to compute the\n  * eigenvalues and eigenvectors of a selfadjoint matrix.\n  *\n  * Call the function compute() to compute the tridiagonal decomposition of a\n  * given matrix. Alternatively, you can use the Tridiagonalization(const MatrixType&)\n  * constructor which computes the tridiagonal Schur decomposition at\n  * construction time. Once the decomposition is computed, you can use the\n  * matrixQ() and matrixT() functions to retrieve the matrices Q and T in the\n  * decomposition.\n  *\n  * The documentation of Tridiagonalization(const MatrixType&) contains an\n  * example of the typical use of this class.\n  *\n  * \\sa class HessenbergDecomposition, class SelfAdjointEigenSolver\n  */\ntemplate<typename _MatrixType> class Tridiagonalization\n{\n  public:\n\n    /** \\brief Synonym for the template parameter \\p _MatrixType. */\n    typedef _MatrixType MatrixType;\n\n    typedef typename MatrixType::Scalar Scalar;\n    typedef typename NumTraits<Scalar>::Real RealScalar;\n    typedef Eigen::Index Index; ///< \\deprecated since Eigen 3.3\n\n    enum {\n      Size = MatrixType::RowsAtCompileTime,\n      SizeMinusOne = Size == Dynamic ? Dynamic : (Size > 1 ? Size - 1 : 1),\n      Options = MatrixType::Options,\n      MaxSize = MatrixType::MaxRowsAtCompileTime,\n      MaxSizeMinusOne = MaxSize == Dynamic ? Dynamic : (MaxSize > 1 ? MaxSize - 1 : 1)\n    };\n\n    typedef Matrix<Scalar, SizeMinusOne, 1, Options & ~RowMajor, MaxSizeMinusOne, 1> CoeffVectorType;\n    typedef typename internal::plain_col_type<MatrixType, RealScalar>::type DiagonalType;\n    typedef Matrix<RealScalar, SizeMinusOne, 1, Options & ~RowMajor, MaxSizeMinusOne, 1> SubDiagonalType;\n    typedef typename internal::remove_all<typename MatrixType::RealReturnType>::type MatrixTypeRealView;\n    typedef internal::TridiagonalizationMatrixTReturnType<MatrixTypeRealView> MatrixTReturnType;\n\n    typedef typename internal::conditional<NumTraits<Scalar>::IsComplex,\n              typename internal::add_const_on_value_type<typename Diagonal<const MatrixType>::RealReturnType>::type,\n              const Diagonal<const MatrixType>\n            >::type DiagonalReturnType;\n\n    typedef typename internal::conditional<NumTraits<Scalar>::IsComplex,\n              typename internal::add_const_on_value_type<typename Diagonal<const MatrixType, -1>::RealReturnType>::type,\n              const Diagonal<const MatrixType, -1>\n            >::type SubDiagonalReturnType;\n\n    /** \\brief Return type of matrixQ() */\n    typedef HouseholderSequence<MatrixType,typename internal::remove_all<typename CoeffVectorType::ConjugateReturnType>::type> HouseholderSequenceType;\n\n    /** \\brief Default constructor.\n      *\n      * \\param [in]  size  Positive integer, size of the matrix whose tridiagonal\n      * decomposition will be computed.\n      *\n      * The default constructor is useful in cases in which the user intends to\n      * perform decompositions via compute().  The \\p size parameter is only\n      * used as a hint. It is not an error to give a wrong \\p size, but it may\n      * impair performance.\n      *\n      * \\sa compute() for an example.\n      */\n    explicit Tridiagonalization(Index size = Size==Dynamic ? 2 : Size)\n      : m_matrix(size,size),\n        m_hCoeffs(size > 1 ? size-1 : 1),\n        m_isInitialized(false)\n    {}\n\n    /** \\brief Constructor; computes tridiagonal decomposition of given matrix.\n      *\n      * \\param[in]  matrix  Selfadjoint matrix whose tridiagonal decomposition\n      * is to be computed.\n      *\n      * This constructor calls compute() to compute the tridiagonal decomposition.\n      *\n      * Example: \\include Tridiagonalization_Tridiagonalization_MatrixType.cpp\n      * Output: \\verbinclude Tridiagonalization_Tridiagonalization_MatrixType.out\n      */\n    template<typename InputType>\n    explicit Tridiagonalization(const EigenBase<InputType>& matrix)\n      : m_matrix(matrix.derived()),\n        m_hCoeffs(matrix.cols() > 1 ? matrix.cols()-1 : 1),\n        m_isInitialized(false)\n    {\n      internal::tridiagonalization_inplace(m_matrix, m_hCoeffs);\n      m_isInitialized = true;\n    }\n\n    /** \\brief Computes tridiagonal decomposition of given matrix.\n      *\n      * \\param[in]  matrix  Selfadjoint matrix whose tridiagonal decomposition\n      * is to be computed.\n      * \\returns    Reference to \\c *this\n      *\n      * The tridiagonal decomposition is computed by bringing the columns of\n      * the matrix successively in the required form using Householder\n      * reflections. The cost is \\f$ 4n^3/3 \\f$ flops, where \\f$ n \\f$ denotes\n      * the size of the given matrix.\n      *\n      * This method reuses of the allocated data in the Tridiagonalization\n      * object, if the size of the matrix does not change.\n      *\n      * Example: \\include Tridiagonalization_compute.cpp\n      * Output: \\verbinclude Tridiagonalization_compute.out\n      */\n    template<typename InputType>\n    Tridiagonalization& compute(const EigenBase<InputType>& matrix)\n    {\n      m_matrix = matrix.derived();\n      m_hCoeffs.resize(matrix.rows()-1, 1);\n      internal::tridiagonalization_inplace(m_matrix, m_hCoeffs);\n      m_isInitialized = true;\n      return *this;\n    }\n\n    /** \\brief Returns the Householder coefficients.\n      *\n      * \\returns a const reference to the vector of Householder coefficients\n      *\n      * \\pre Either the constructor Tridiagonalization(const MatrixType&) or\n      * the member function compute(const MatrixType&) has been called before\n      * to compute the tridiagonal decomposition of a matrix.\n      *\n      * The Householder coefficients allow the reconstruction of the matrix\n      * \\f$ Q \\f$ in the tridiagonal decomposition from the packed data.\n      *\n      * Example: \\include Tridiagonalization_householderCoefficients.cpp\n      * Output: \\verbinclude Tridiagonalization_householderCoefficients.out\n      *\n      * \\sa packedMatrix(), \\ref Householder_Module \"Householder module\"\n      */\n    inline CoeffVectorType householderCoefficients() const\n    {\n      eigen_assert(m_isInitialized && \"Tridiagonalization is not initialized.\");\n      return m_hCoeffs;\n    }\n\n    /** \\brief Returns the internal representation of the decomposition\n      *\n      *\t\\returns a const reference to a matrix with the internal representation\n      *\t         of the decomposition.\n      *\n      * \\pre Either the constructor Tridiagonalization(const MatrixType&) or\n      * the member function compute(const MatrixType&) has been called before\n      * to compute the tridiagonal decomposition of a matrix.\n      *\n      * The returned matrix contains the following information:\n      *  - the strict upper triangular part is equal to the input matrix A.\n      *  - the diagonal and lower sub-diagonal represent the real tridiagonal\n      *    symmetric matrix T.\n      *  - the rest of the lower part contains the Householder vectors that,\n      *    combined with Householder coefficients returned by\n      *    householderCoefficients(), allows to reconstruct the matrix Q as\n      *       \\f$ Q = H_{N-1} \\ldots H_1 H_0 \\f$.\n      *    Here, the matrices \\f$ H_i \\f$ are the Householder transformations\n      *       \\f$ H_i = (I - h_i v_i v_i^T) \\f$\n      *    where \\f$ h_i \\f$ is the \\f$ i \\f$th Householder coefficient and\n      *    \\f$ v_i \\f$ is the Householder vector defined by\n      *       \\f$ v_i = [ 0, \\ldots, 0, 1, M(i+2,i), \\ldots, M(N-1,i) ]^T \\f$\n      *    with M the matrix returned by this function.\n      *\n      * See LAPACK for further details on this packed storage.\n      *\n      * Example: \\include Tridiagonalization_packedMatrix.cpp\n      * Output: \\verbinclude Tridiagonalization_packedMatrix.out\n      *\n      * \\sa householderCoefficients()\n      */\n    inline const MatrixType& packedMatrix() const\n    {\n      eigen_assert(m_isInitialized && \"Tridiagonalization is not initialized.\");\n      return m_matrix;\n    }\n\n    /** \\brief Returns the unitary matrix Q in the decomposition\n      *\n      * \\returns object representing the matrix Q\n      *\n      * \\pre Either the constructor Tridiagonalization(const MatrixType&) or\n      * the member function compute(const MatrixType&) has been called before\n      * to compute the tridiagonal decomposition of a matrix.\n      *\n      * This function returns a light-weight object of template class\n      * HouseholderSequence. You can either apply it directly to a matrix or\n      * you can convert it to a matrix of type #MatrixType.\n      *\n      * \\sa Tridiagonalization(const MatrixType&) for an example,\n      *     matrixT(), class HouseholderSequence\n      */\n    HouseholderSequenceType matrixQ() const\n    {\n      eigen_assert(m_isInitialized && \"Tridiagonalization is not initialized.\");\n      return HouseholderSequenceType(m_matrix, m_hCoeffs.conjugate())\n             .setLength(m_matrix.rows() - 1)\n             .setShift(1);\n    }\n\n    /** \\brief Returns an expression of the tridiagonal matrix T in the decomposition\n      *\n      * \\returns expression object representing the matrix T\n      *\n      * \\pre Either the constructor Tridiagonalization(const MatrixType&) or\n      * the member function compute(const MatrixType&) has been called before\n      * to compute the tridiagonal decomposition of a matrix.\n      *\n      * Currently, this function can be used to extract the matrix T from internal\n      * data and copy it to a dense matrix object. In most cases, it may be\n      * sufficient to directly use the packed matrix or the vector expressions\n      * returned by diagonal() and subDiagonal() instead of creating a new\n      * dense copy matrix with this function.\n      *\n      * \\sa Tridiagonalization(const MatrixType&) for an example,\n      * matrixQ(), packedMatrix(), diagonal(), subDiagonal()\n      */\n    MatrixTReturnType matrixT() const\n    {\n      eigen_assert(m_isInitialized && \"Tridiagonalization is not initialized.\");\n      return MatrixTReturnType(m_matrix.real());\n    }\n\n    /** \\brief Returns the diagonal of the tridiagonal matrix T in the decomposition.\n      *\n      * \\returns expression representing the diagonal of T\n      *\n      * \\pre Either the constructor Tridiagonalization(const MatrixType&) or\n      * the member function compute(const MatrixType&) has been called before\n      * to compute the tridiagonal decomposition of a matrix.\n      *\n      * Example: \\include Tridiagonalization_diagonal.cpp\n      * Output: \\verbinclude Tridiagonalization_diagonal.out\n      *\n      * \\sa matrixT(), subDiagonal()\n      */\n    DiagonalReturnType diagonal() const;\n\n    /** \\brief Returns the subdiagonal of the tridiagonal matrix T in the decomposition.\n      *\n      * \\returns expression representing the subdiagonal of T\n      *\n      * \\pre Either the constructor Tridiagonalization(const MatrixType&) or\n      * the member function compute(const MatrixType&) has been called before\n      * to compute the tridiagonal decomposition of a matrix.\n      *\n      * \\sa diagonal() for an example, matrixT()\n      */\n    SubDiagonalReturnType subDiagonal() const;\n\n  protected:\n\n    MatrixType m_matrix;\n    CoeffVectorType m_hCoeffs;\n    bool m_isInitialized;\n};\n\ntemplate<typename MatrixType>\ntypename Tridiagonalization<MatrixType>::DiagonalReturnType\nTridiagonalization<MatrixType>::diagonal() const\n{\n  eigen_assert(m_isInitialized && \"Tridiagonalization is not initialized.\");\n  return m_matrix.diagonal().real();\n}\n\ntemplate<typename MatrixType>\ntypename Tridiagonalization<MatrixType>::SubDiagonalReturnType\nTridiagonalization<MatrixType>::subDiagonal() const\n{\n  eigen_assert(m_isInitialized && \"Tridiagonalization is not initialized.\");\n  return m_matrix.template diagonal<-1>().real();\n}\n\nnamespace internal {\n\n/** \\internal\n  * Performs a tridiagonal decomposition of the selfadjoint matrix \\a matA in-place.\n  *\n  * \\param[in,out] matA On input the selfadjoint matrix. Only the \\b lower triangular part is referenced.\n  *                     On output, the strict upper part is left unchanged, and the lower triangular part\n  *                     represents the T and Q matrices in packed format has detailed below.\n  * \\param[out]    hCoeffs returned Householder coefficients (see below)\n  *\n  * On output, the tridiagonal selfadjoint matrix T is stored in the diagonal\n  * and lower sub-diagonal of the matrix \\a matA.\n  * The unitary matrix Q is represented in a compact way as a product of\n  * Householder reflectors \\f$ H_i \\f$ such that:\n  *       \\f$ Q = H_{N-1} \\ldots H_1 H_0 \\f$.\n  * The Householder reflectors are defined as\n  *       \\f$ H_i = (I - h_i v_i v_i^T) \\f$\n  * where \\f$ h_i = hCoeffs[i]\\f$ is the \\f$ i \\f$th Householder coefficient and\n  * \\f$ v_i \\f$ is the Householder vector defined by\n  *       \\f$ v_i = [ 0, \\ldots, 0, 1, matA(i+2,i), \\ldots, matA(N-1,i) ]^T \\f$.\n  *\n  * Implemented from Golub's \"Matrix Computations\", algorithm 8.3.1.\n  *\n  * \\sa Tridiagonalization::packedMatrix()\n  */\ntemplate<typename MatrixType, typename CoeffVectorType>\nvoid tridiagonalization_inplace(MatrixType& matA, CoeffVectorType& hCoeffs)\n{\n  using numext::conj;\n  typedef typename MatrixType::Scalar Scalar;\n  typedef typename MatrixType::RealScalar RealScalar;\n  Index n = matA.rows();\n  eigen_assert(n==matA.cols());\n  eigen_assert(n==hCoeffs.size()+1 || n==1);\n  \n  for (Index i = 0; i<n-1; ++i)\n  {\n    Index remainingSize = n-i-1;\n    RealScalar beta;\n    Scalar h;\n    matA.col(i).tail(remainingSize).makeHouseholderInPlace(h, beta);\n\n    // Apply similarity transformation to remaining columns,\n    // i.e., A = H A H' where H = I - h v v' and v = matA.col(i).tail(n-i-1)\n    matA.col(i).coeffRef(i+1) = 1;\n\n    hCoeffs.tail(n-i-1).noalias() = (matA.bottomRightCorner(remainingSize,remainingSize).template selfadjointView<Lower>()\n                                  * (conj(h) * matA.col(i).tail(remainingSize)));\n\n    hCoeffs.tail(n-i-1) += (conj(h)*RealScalar(-0.5)*(hCoeffs.tail(remainingSize).dot(matA.col(i).tail(remainingSize)))) * matA.col(i).tail(n-i-1);\n\n    matA.bottomRightCorner(remainingSize, remainingSize).template selfadjointView<Lower>()\n      .rankUpdate(matA.col(i).tail(remainingSize), hCoeffs.tail(remainingSize), Scalar(-1));\n\n    matA.col(i).coeffRef(i+1) = beta;\n    hCoeffs.coeffRef(i) = h;\n  }\n}\n\n// forward declaration, implementation at the end of this file\ntemplate<typename MatrixType,\n         int Size=MatrixType::ColsAtCompileTime,\n         bool IsComplex=NumTraits<typename MatrixType::Scalar>::IsComplex>\nstruct tridiagonalization_inplace_selector;\n\n/** \\brief Performs a full tridiagonalization in place\n  *\n  * \\param[in,out]  mat  On input, the selfadjoint matrix whose tridiagonal\n  *    decomposition is to be computed. Only the lower triangular part referenced.\n  *    The rest is left unchanged. On output, the orthogonal matrix Q\n  *    in the decomposition if \\p extractQ is true.\n  * \\param[out]  diag  The diagonal of the tridiagonal matrix T in the\n  *    decomposition.\n  * \\param[out]  subdiag  The subdiagonal of the tridiagonal matrix T in\n  *    the decomposition.\n  * \\param[in]  extractQ  If true, the orthogonal matrix Q in the\n  *    decomposition is computed and stored in \\p mat.\n  *\n  * Computes the tridiagonal decomposition of the selfadjoint matrix \\p mat in place\n  * such that \\f$ mat = Q T Q^* \\f$ where \\f$ Q \\f$ is unitary and \\f$ T \\f$ a real\n  * symmetric tridiagonal matrix.\n  *\n  * The tridiagonal matrix T is passed to the output parameters \\p diag and \\p subdiag. If\n  * \\p extractQ is true, then the orthogonal matrix Q is passed to \\p mat. Otherwise the lower\n  * part of the matrix \\p mat is destroyed.\n  *\n  * The vectors \\p diag and \\p subdiag are not resized. The function\n  * assumes that they are already of the correct size. The length of the\n  * vector \\p diag should equal the number of rows in \\p mat, and the\n  * length of the vector \\p subdiag should be one left.\n  *\n  * This implementation contains an optimized path for 3-by-3 matrices\n  * which is especially useful for plane fitting.\n  *\n  * \\note Currently, it requires two temporary vectors to hold the intermediate\n  * Householder coefficients, and to reconstruct the matrix Q from the Householder\n  * reflectors.\n  *\n  * Example (this uses the same matrix as the example in\n  *    Tridiagonalization::Tridiagonalization(const MatrixType&)):\n  *    \\include Tridiagonalization_decomposeInPlace.cpp\n  * Output: \\verbinclude Tridiagonalization_decomposeInPlace.out\n  *\n  * \\sa class Tridiagonalization\n  */\ntemplate<typename MatrixType, typename DiagonalType, typename SubDiagonalType>\nvoid tridiagonalization_inplace(MatrixType& mat, DiagonalType& diag, SubDiagonalType& subdiag, bool extractQ)\n{\n  eigen_assert(mat.cols()==mat.rows() && diag.size()==mat.rows() && subdiag.size()==mat.rows()-1);\n  tridiagonalization_inplace_selector<MatrixType>::run(mat, diag, subdiag, extractQ);\n}\n\n/** \\internal\n  * General full tridiagonalization\n  */\ntemplate<typename MatrixType, int Size, bool IsComplex>\nstruct tridiagonalization_inplace_selector\n{\n  typedef typename Tridiagonalization<MatrixType>::CoeffVectorType CoeffVectorType;\n  typedef typename Tridiagonalization<MatrixType>::HouseholderSequenceType HouseholderSequenceType;\n  template<typename DiagonalType, typename SubDiagonalType>\n  static void run(MatrixType& mat, DiagonalType& diag, SubDiagonalType& subdiag, bool extractQ)\n  {\n    CoeffVectorType hCoeffs(mat.cols()-1);\n    tridiagonalization_inplace(mat,hCoeffs);\n    diag = mat.diagonal().real();\n    subdiag = mat.template diagonal<-1>().real();\n    if(extractQ)\n      mat = HouseholderSequenceType(mat, hCoeffs.conjugate())\n            .setLength(mat.rows() - 1)\n            .setShift(1);\n  }\n};\n\n/** \\internal\n  * Specialization for 3x3 real matrices.\n  * Especially useful for plane fitting.\n  */\ntemplate<typename MatrixType>\nstruct tridiagonalization_inplace_selector<MatrixType,3,false>\n{\n  typedef typename MatrixType::Scalar Scalar;\n  typedef typename MatrixType::RealScalar RealScalar;\n\n  template<typename DiagonalType, typename SubDiagonalType>\n  static void run(MatrixType& mat, DiagonalType& diag, SubDiagonalType& subdiag, bool extractQ)\n  {\n    using std::sqrt;\n    const RealScalar tol = (std::numeric_limits<RealScalar>::min)();\n    diag[0] = mat(0,0);\n    RealScalar v1norm2 = numext::abs2(mat(2,0));\n    if(v1norm2 <= tol)\n    {\n      diag[1] = mat(1,1);\n      diag[2] = mat(2,2);\n      subdiag[0] = mat(1,0);\n      subdiag[1] = mat(2,1);\n      if (extractQ)\n        mat.setIdentity();\n    }\n    else\n    {\n      RealScalar beta = sqrt(numext::abs2(mat(1,0)) + v1norm2);\n      RealScalar invBeta = RealScalar(1)/beta;\n      Scalar m01 = mat(1,0) * invBeta;\n      Scalar m02 = mat(2,0) * invBeta;\n      Scalar q = RealScalar(2)*m01*mat(2,1) + m02*(mat(2,2) - mat(1,1));\n      diag[1] = mat(1,1) + m02*q;\n      diag[2] = mat(2,2) - m02*q;\n      subdiag[0] = beta;\n      subdiag[1] = mat(2,1) - m01 * q;\n      if (extractQ)\n      {\n        mat << 1,   0,    0,\n               0, m01,  m02,\n               0, m02, -m01;\n      }\n    }\n  }\n};\n\n/** \\internal\n  * Trivial specialization for 1x1 matrices\n  */\ntemplate<typename MatrixType, bool IsComplex>\nstruct tridiagonalization_inplace_selector<MatrixType,1,IsComplex>\n{\n  typedef typename MatrixType::Scalar Scalar;\n\n  template<typename DiagonalType, typename SubDiagonalType>\n  static void run(MatrixType& mat, DiagonalType& diag, SubDiagonalType&, bool extractQ)\n  {\n    diag(0,0) = numext::real(mat(0,0));\n    if(extractQ)\n      mat(0,0) = Scalar(1);\n  }\n};\n\n/** \\internal\n  * \\eigenvalues_module \\ingroup Eigenvalues_Module\n  *\n  * \\brief Expression type for return value of Tridiagonalization::matrixT()\n  *\n  * \\tparam MatrixType type of underlying dense matrix\n  */\ntemplate<typename MatrixType> struct TridiagonalizationMatrixTReturnType\n: public ReturnByValue<TridiagonalizationMatrixTReturnType<MatrixType> >\n{\n  public:\n    /** \\brief Constructor.\n      *\n      * \\param[in] mat The underlying dense matrix\n      */\n    TridiagonalizationMatrixTReturnType(const MatrixType& mat) : m_matrix(mat) { }\n\n    template <typename ResultType>\n    inline void evalTo(ResultType& result) const\n    {\n      result.setZero();\n      result.template diagonal<1>() = m_matrix.template diagonal<-1>().conjugate();\n      result.diagonal() = m_matrix.diagonal();\n      result.template diagonal<-1>() = m_matrix.template diagonal<-1>();\n    }\n\n    Index rows() const { return m_matrix.rows(); }\n    Index cols() const { return m_matrix.cols(); }\n\n  protected:\n    typename MatrixType::Nested m_matrix;\n};\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_TRIDIAGONALIZATION_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Geometry/AlignedBox.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_ALIGNEDBOX_H\n#define EIGEN_ALIGNEDBOX_H\n\nnamespace Eigen { \n\n/** \\geometry_module \\ingroup Geometry_Module\n  *\n  *\n  * \\class AlignedBox\n  *\n  * \\brief An axis aligned box\n  *\n  * \\tparam _Scalar the type of the scalar coefficients\n  * \\tparam _AmbientDim the dimension of the ambient space, can be a compile time value or Dynamic.\n  *\n  * This class represents an axis aligned box as a pair of the minimal and maximal corners.\n  * \\warning The result of most methods is undefined when applied to an empty box. You can check for empty boxes using isEmpty().\n  * \\sa alignedboxtypedefs\n  */\ntemplate <typename _Scalar, int _AmbientDim>\nclass AlignedBox\n{\npublic:\nEIGEN_MAKE_ALIGNED_OPERATOR_NEW_IF_VECTORIZABLE_FIXED_SIZE(_Scalar,_AmbientDim)\n  enum { AmbientDimAtCompileTime = _AmbientDim };\n  typedef _Scalar                                   Scalar;\n  typedef NumTraits<Scalar>                         ScalarTraits;\n  typedef Eigen::Index                              Index; ///< \\deprecated since Eigen 3.3\n  typedef typename ScalarTraits::Real               RealScalar;\n  typedef typename ScalarTraits::NonInteger         NonInteger;\n  typedef Matrix<Scalar,AmbientDimAtCompileTime,1>  VectorType;\n  typedef CwiseBinaryOp<internal::scalar_sum_op<Scalar>, const VectorType, const VectorType> VectorTypeSum;\n\n  /** Define constants to name the corners of a 1D, 2D or 3D axis aligned bounding box */\n  enum CornerType\n  {\n    /** 1D names @{ */\n    Min=0, Max=1,\n    /** @} */\n\n    /** Identifier for 2D corner @{ */\n    BottomLeft=0, BottomRight=1,\n    TopLeft=2, TopRight=3,\n    /** @} */\n\n    /** Identifier for 3D corner  @{ */\n    BottomLeftFloor=0, BottomRightFloor=1,\n    TopLeftFloor=2, TopRightFloor=3,\n    BottomLeftCeil=4, BottomRightCeil=5,\n    TopLeftCeil=6, TopRightCeil=7\n    /** @} */\n  };\n\n\n  /** Default constructor initializing a null box. */\n  EIGEN_DEVICE_FUNC inline AlignedBox()\n  { if (AmbientDimAtCompileTime!=Dynamic) setEmpty(); }\n\n  /** Constructs a null box with \\a _dim the dimension of the ambient space. */\n  EIGEN_DEVICE_FUNC inline explicit AlignedBox(Index _dim) : m_min(_dim), m_max(_dim)\n  { setEmpty(); }\n\n  /** Constructs a box with extremities \\a _min and \\a _max.\n   * \\warning If either component of \\a _min is larger than the same component of \\a _max, the constructed box is empty. */\n  template<typename OtherVectorType1, typename OtherVectorType2>\n  EIGEN_DEVICE_FUNC inline AlignedBox(const OtherVectorType1& _min, const OtherVectorType2& _max) : m_min(_min), m_max(_max) {}\n\n  /** Constructs a box containing a single point \\a p. */\n  template<typename Derived>\n  EIGEN_DEVICE_FUNC inline explicit AlignedBox(const MatrixBase<Derived>& p) : m_min(p), m_max(m_min)\n  { }\n\n  EIGEN_DEVICE_FUNC ~AlignedBox() {}\n\n  /** \\returns the dimension in which the box holds */\n  EIGEN_DEVICE_FUNC inline Index dim() const { return AmbientDimAtCompileTime==Dynamic ? m_min.size() : Index(AmbientDimAtCompileTime); }\n\n  /** \\deprecated use isEmpty() */\n  EIGEN_DEVICE_FUNC inline bool isNull() const { return isEmpty(); }\n\n  /** \\deprecated use setEmpty() */\n  EIGEN_DEVICE_FUNC inline void setNull() { setEmpty(); }\n\n  /** \\returns true if the box is empty.\n   * \\sa setEmpty */\n  EIGEN_DEVICE_FUNC inline bool isEmpty() const { return (m_min.array() > m_max.array()).any(); }\n\n  /** Makes \\c *this an empty box.\n   * \\sa isEmpty */\n  EIGEN_DEVICE_FUNC inline void setEmpty()\n  {\n    m_min.setConstant( ScalarTraits::highest() );\n    m_max.setConstant( ScalarTraits::lowest() );\n  }\n\n  /** \\returns the minimal corner */\n  EIGEN_DEVICE_FUNC inline const VectorType& (min)() const { return m_min; }\n  /** \\returns a non const reference to the minimal corner */\n  EIGEN_DEVICE_FUNC inline VectorType& (min)() { return m_min; }\n  /** \\returns the maximal corner */\n  EIGEN_DEVICE_FUNC inline const VectorType& (max)() const { return m_max; }\n  /** \\returns a non const reference to the maximal corner */\n  EIGEN_DEVICE_FUNC inline VectorType& (max)() { return m_max; }\n\n  /** \\returns the center of the box */\n  EIGEN_DEVICE_FUNC inline const EIGEN_EXPR_BINARYOP_SCALAR_RETURN_TYPE(VectorTypeSum, RealScalar, quotient)\n  center() const\n  { return (m_min+m_max)/RealScalar(2); }\n\n  /** \\returns the lengths of the sides of the bounding box.\n    * Note that this function does not get the same\n    * result for integral or floating scalar types: see\n    */\n  EIGEN_DEVICE_FUNC inline const CwiseBinaryOp< internal::scalar_difference_op<Scalar,Scalar>, const VectorType, const VectorType> sizes() const\n  { return m_max - m_min; }\n\n  /** \\returns the volume of the bounding box */\n  EIGEN_DEVICE_FUNC inline Scalar volume() const\n  { return sizes().prod(); }\n\n  /** \\returns an expression for the bounding box diagonal vector\n    * if the length of the diagonal is needed: diagonal().norm()\n    * will provide it.\n    */\n  EIGEN_DEVICE_FUNC inline CwiseBinaryOp< internal::scalar_difference_op<Scalar,Scalar>, const VectorType, const VectorType> diagonal() const\n  { return sizes(); }\n\n  /** \\returns the vertex of the bounding box at the corner defined by\n    * the corner-id corner. It works only for a 1D, 2D or 3D bounding box.\n    * For 1D bounding boxes corners are named by 2 enum constants:\n    * BottomLeft and BottomRight.\n    * For 2D bounding boxes, corners are named by 4 enum constants:\n    * BottomLeft, BottomRight, TopLeft, TopRight.\n    * For 3D bounding boxes, the following names are added:\n    * BottomLeftCeil, BottomRightCeil, TopLeftCeil, TopRightCeil.\n    */\n  EIGEN_DEVICE_FUNC inline VectorType corner(CornerType corner) const\n  {\n    EIGEN_STATIC_ASSERT(_AmbientDim <= 3, THIS_METHOD_IS_ONLY_FOR_VECTORS_OF_A_SPECIFIC_SIZE);\n\n    VectorType res;\n\n    Index mult = 1;\n    for(Index d=0; d<dim(); ++d)\n    {\n      if( mult & corner ) res[d] = m_max[d];\n      else                res[d] = m_min[d];\n      mult *= 2;\n    }\n    return res;\n  }\n\n  /** \\returns a random point inside the bounding box sampled with\n   * a uniform distribution */\n  EIGEN_DEVICE_FUNC inline VectorType sample() const\n  {\n    VectorType r(dim());\n    for(Index d=0; d<dim(); ++d)\n    {\n      if(!ScalarTraits::IsInteger)\n      {\n        r[d] = m_min[d] + (m_max[d]-m_min[d])\n             * internal::random<Scalar>(Scalar(0), Scalar(1));\n      }\n      else\n        r[d] = internal::random(m_min[d], m_max[d]);\n    }\n    return r;\n  }\n\n  /** \\returns true if the point \\a p is inside the box \\c *this. */\n  template<typename Derived>\n  EIGEN_DEVICE_FUNC inline bool contains(const MatrixBase<Derived>& p) const\n  {\n    typename internal::nested_eval<Derived,2>::type p_n(p.derived());\n    return (m_min.array()<=p_n.array()).all() && (p_n.array()<=m_max.array()).all();\n  }\n\n  /** \\returns true if the box \\a b is entirely inside the box \\c *this. */\n  EIGEN_DEVICE_FUNC inline bool contains(const AlignedBox& b) const\n  { return (m_min.array()<=(b.min)().array()).all() && ((b.max)().array()<=m_max.array()).all(); }\n\n  /** \\returns true if the box \\a b is intersecting the box \\c *this.\n   * \\sa intersection, clamp */\n  EIGEN_DEVICE_FUNC inline bool intersects(const AlignedBox& b) const\n  { return (m_min.array()<=(b.max)().array()).all() && ((b.min)().array()<=m_max.array()).all(); }\n\n  /** Extends \\c *this such that it contains the point \\a p and returns a reference to \\c *this.\n   * \\sa extend(const AlignedBox&) */\n  template<typename Derived>\n  EIGEN_DEVICE_FUNC inline AlignedBox& extend(const MatrixBase<Derived>& p)\n  {\n    typename internal::nested_eval<Derived,2>::type p_n(p.derived());\n    m_min = m_min.cwiseMin(p_n);\n    m_max = m_max.cwiseMax(p_n);\n    return *this;\n  }\n\n  /** Extends \\c *this such that it contains the box \\a b and returns a reference to \\c *this.\n   * \\sa merged, extend(const MatrixBase&) */\n  EIGEN_DEVICE_FUNC inline AlignedBox& extend(const AlignedBox& b)\n  {\n    m_min = m_min.cwiseMin(b.m_min);\n    m_max = m_max.cwiseMax(b.m_max);\n    return *this;\n  }\n\n  /** Clamps \\c *this by the box \\a b and returns a reference to \\c *this.\n   * \\note If the boxes don't intersect, the resulting box is empty.\n   * \\sa intersection(), intersects() */\n  EIGEN_DEVICE_FUNC inline AlignedBox& clamp(const AlignedBox& b)\n  {\n    m_min = m_min.cwiseMax(b.m_min);\n    m_max = m_max.cwiseMin(b.m_max);\n    return *this;\n  }\n\n  /** Returns an AlignedBox that is the intersection of \\a b and \\c *this\n   * \\note If the boxes don't intersect, the resulting box is empty.\n   * \\sa intersects(), clamp, contains()  */\n  EIGEN_DEVICE_FUNC inline AlignedBox intersection(const AlignedBox& b) const\n  {return AlignedBox(m_min.cwiseMax(b.m_min), m_max.cwiseMin(b.m_max)); }\n\n  /** Returns an AlignedBox that is the union of \\a b and \\c *this.\n   * \\note Merging with an empty box may result in a box bigger than \\c *this. \n   * \\sa extend(const AlignedBox&) */\n  EIGEN_DEVICE_FUNC inline AlignedBox merged(const AlignedBox& b) const\n  { return AlignedBox(m_min.cwiseMin(b.m_min), m_max.cwiseMax(b.m_max)); }\n\n  /** Translate \\c *this by the vector \\a t and returns a reference to \\c *this. */\n  template<typename Derived>\n  EIGEN_DEVICE_FUNC inline AlignedBox& translate(const MatrixBase<Derived>& a_t)\n  {\n    const typename internal::nested_eval<Derived,2>::type t(a_t.derived());\n    m_min += t;\n    m_max += t;\n    return *this;\n  }\n\n  /** \\returns the squared distance between the point \\a p and the box \\c *this,\n    * and zero if \\a p is inside the box.\n    * \\sa exteriorDistance(const MatrixBase&), squaredExteriorDistance(const AlignedBox&)\n    */\n  template<typename Derived>\n  EIGEN_DEVICE_FUNC inline Scalar squaredExteriorDistance(const MatrixBase<Derived>& p) const;\n\n  /** \\returns the squared distance between the boxes \\a b and \\c *this,\n    * and zero if the boxes intersect.\n    * \\sa exteriorDistance(const AlignedBox&), squaredExteriorDistance(const MatrixBase&)\n    */\n  EIGEN_DEVICE_FUNC inline Scalar squaredExteriorDistance(const AlignedBox& b) const;\n\n  /** \\returns the distance between the point \\a p and the box \\c *this,\n    * and zero if \\a p is inside the box.\n    * \\sa squaredExteriorDistance(const MatrixBase&), exteriorDistance(const AlignedBox&)\n    */\n  template<typename Derived>\n  EIGEN_DEVICE_FUNC inline NonInteger exteriorDistance(const MatrixBase<Derived>& p) const\n  { EIGEN_USING_STD_MATH(sqrt) return sqrt(NonInteger(squaredExteriorDistance(p))); }\n\n  /** \\returns the distance between the boxes \\a b and \\c *this,\n    * and zero if the boxes intersect.\n    * \\sa squaredExteriorDistance(const AlignedBox&), exteriorDistance(const MatrixBase&)\n    */\n  EIGEN_DEVICE_FUNC inline NonInteger exteriorDistance(const AlignedBox& b) const\n  { EIGEN_USING_STD_MATH(sqrt) return sqrt(NonInteger(squaredExteriorDistance(b))); }\n\n  /** \\returns \\c *this with scalar type casted to \\a NewScalarType\n    *\n    * Note that if \\a NewScalarType is equal to the current scalar type of \\c *this\n    * then this function smartly returns a const reference to \\c *this.\n    */\n  template<typename NewScalarType>\n  EIGEN_DEVICE_FUNC inline typename internal::cast_return_type<AlignedBox,\n           AlignedBox<NewScalarType,AmbientDimAtCompileTime> >::type cast() const\n  {\n    return typename internal::cast_return_type<AlignedBox,\n                    AlignedBox<NewScalarType,AmbientDimAtCompileTime> >::type(*this);\n  }\n\n  /** Copy constructor with scalar type conversion */\n  template<typename OtherScalarType>\n  EIGEN_DEVICE_FUNC inline explicit AlignedBox(const AlignedBox<OtherScalarType,AmbientDimAtCompileTime>& other)\n  {\n    m_min = (other.min)().template cast<Scalar>();\n    m_max = (other.max)().template cast<Scalar>();\n  }\n\n  /** \\returns \\c true if \\c *this is approximately equal to \\a other, within the precision\n    * determined by \\a prec.\n    *\n    * \\sa MatrixBase::isApprox() */\n  EIGEN_DEVICE_FUNC bool isApprox(const AlignedBox& other, const RealScalar& prec = ScalarTraits::dummy_precision()) const\n  { return m_min.isApprox(other.m_min, prec) && m_max.isApprox(other.m_max, prec); }\n\nprotected:\n\n  VectorType m_min, m_max;\n};\n\n\n\ntemplate<typename Scalar,int AmbientDim>\ntemplate<typename Derived>\nEIGEN_DEVICE_FUNC inline Scalar AlignedBox<Scalar,AmbientDim>::squaredExteriorDistance(const MatrixBase<Derived>& a_p) const\n{\n  typename internal::nested_eval<Derived,2*AmbientDim>::type p(a_p.derived());\n  Scalar dist2(0);\n  Scalar aux;\n  for (Index k=0; k<dim(); ++k)\n  {\n    if( m_min[k] > p[k] )\n    {\n      aux = m_min[k] - p[k];\n      dist2 += aux*aux;\n    }\n    else if( p[k] > m_max[k] )\n    {\n      aux = p[k] - m_max[k];\n      dist2 += aux*aux;\n    }\n  }\n  return dist2;\n}\n\ntemplate<typename Scalar,int AmbientDim>\nEIGEN_DEVICE_FUNC inline Scalar AlignedBox<Scalar,AmbientDim>::squaredExteriorDistance(const AlignedBox& b) const\n{\n  Scalar dist2(0);\n  Scalar aux;\n  for (Index k=0; k<dim(); ++k)\n  {\n    if( m_min[k] > b.m_max[k] )\n    {\n      aux = m_min[k] - b.m_max[k];\n      dist2 += aux*aux;\n    }\n    else if( b.m_min[k] > m_max[k] )\n    {\n      aux = b.m_min[k] - m_max[k];\n      dist2 += aux*aux;\n    }\n  }\n  return dist2;\n}\n\n/** \\defgroup alignedboxtypedefs Global aligned box typedefs\n  *\n  * \\ingroup Geometry_Module\n  *\n  * Eigen defines several typedef shortcuts for most common aligned box types.\n  *\n  * The general patterns are the following:\n  *\n  * \\c AlignedBoxSizeType where \\c Size can be \\c 1, \\c 2,\\c 3,\\c 4 for fixed size boxes or \\c X for dynamic size,\n  * and where \\c Type can be \\c i for integer, \\c f for float, \\c d for double.\n  *\n  * For example, \\c AlignedBox3d is a fixed-size 3x3 aligned box type of doubles, and \\c AlignedBoxXf is a dynamic-size aligned box of floats.\n  *\n  * \\sa class AlignedBox\n  */\n\n#define EIGEN_MAKE_TYPEDEFS(Type, TypeSuffix, Size, SizeSuffix)    \\\n/** \\ingroup alignedboxtypedefs */                                 \\\ntypedef AlignedBox<Type, Size>   AlignedBox##SizeSuffix##TypeSuffix;\n\n#define EIGEN_MAKE_TYPEDEFS_ALL_SIZES(Type, TypeSuffix) \\\nEIGEN_MAKE_TYPEDEFS(Type, TypeSuffix, 1, 1) \\\nEIGEN_MAKE_TYPEDEFS(Type, TypeSuffix, 2, 2) \\\nEIGEN_MAKE_TYPEDEFS(Type, TypeSuffix, 3, 3) \\\nEIGEN_MAKE_TYPEDEFS(Type, TypeSuffix, 4, 4) \\\nEIGEN_MAKE_TYPEDEFS(Type, TypeSuffix, Dynamic, X)\n\nEIGEN_MAKE_TYPEDEFS_ALL_SIZES(int,                  i)\nEIGEN_MAKE_TYPEDEFS_ALL_SIZES(float,                f)\nEIGEN_MAKE_TYPEDEFS_ALL_SIZES(double,               d)\n\n#undef EIGEN_MAKE_TYPEDEFS_ALL_SIZES\n#undef EIGEN_MAKE_TYPEDEFS\n\n} // end namespace Eigen\n\n#endif // EIGEN_ALIGNEDBOX_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Geometry/AngleAxis.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_ANGLEAXIS_H\n#define EIGEN_ANGLEAXIS_H\n\nnamespace Eigen { \n\n/** \\geometry_module \\ingroup Geometry_Module\n  *\n  * \\class AngleAxis\n  *\n  * \\brief Represents a 3D rotation as a rotation angle around an arbitrary 3D axis\n  *\n  * \\param _Scalar the scalar type, i.e., the type of the coefficients.\n  *\n  * \\warning When setting up an AngleAxis object, the axis vector \\b must \\b be \\b normalized.\n  *\n  * The following two typedefs are provided for convenience:\n  * \\li \\c AngleAxisf for \\c float\n  * \\li \\c AngleAxisd for \\c double\n  *\n  * Combined with MatrixBase::Unit{X,Y,Z}, AngleAxis can be used to easily\n  * mimic Euler-angles. Here is an example:\n  * \\include AngleAxis_mimic_euler.cpp\n  * Output: \\verbinclude AngleAxis_mimic_euler.out\n  *\n  * \\note This class is not aimed to be used to store a rotation transformation,\n  * but rather to make easier the creation of other rotation (Quaternion, rotation Matrix)\n  * and transformation objects.\n  *\n  * \\sa class Quaternion, class Transform, MatrixBase::UnitX()\n  */\n\nnamespace internal {\ntemplate<typename _Scalar> struct traits<AngleAxis<_Scalar> >\n{\n  typedef _Scalar Scalar;\n};\n}\n\ntemplate<typename _Scalar>\nclass AngleAxis : public RotationBase<AngleAxis<_Scalar>,3>\n{\n  typedef RotationBase<AngleAxis<_Scalar>,3> Base;\n\npublic:\n\n  using Base::operator*;\n\n  enum { Dim = 3 };\n  /** the scalar type of the coefficients */\n  typedef _Scalar Scalar;\n  typedef Matrix<Scalar,3,3> Matrix3;\n  typedef Matrix<Scalar,3,1> Vector3;\n  typedef Quaternion<Scalar> QuaternionType;\n\nprotected:\n\n  Vector3 m_axis;\n  Scalar m_angle;\n\npublic:\n\n  /** Default constructor without initialization. */\n  EIGEN_DEVICE_FUNC AngleAxis() {}\n  /** Constructs and initialize the angle-axis rotation from an \\a angle in radian\n    * and an \\a axis which \\b must \\b be \\b normalized.\n    *\n    * \\warning If the \\a axis vector is not normalized, then the angle-axis object\n    *          represents an invalid rotation. */\n  template<typename Derived>\n  EIGEN_DEVICE_FUNC \n  inline AngleAxis(const Scalar& angle, const MatrixBase<Derived>& axis) : m_axis(axis), m_angle(angle) {}\n  /** Constructs and initialize the angle-axis rotation from a quaternion \\a q.\n    * This function implicitly normalizes the quaternion \\a q.\n    */\n  template<typename QuatDerived> \n  EIGEN_DEVICE_FUNC inline explicit AngleAxis(const QuaternionBase<QuatDerived>& q) { *this = q; }\n  /** Constructs and initialize the angle-axis rotation from a 3x3 rotation matrix. */\n  template<typename Derived>\n  EIGEN_DEVICE_FUNC inline explicit AngleAxis(const MatrixBase<Derived>& m) { *this = m; }\n\n  /** \\returns the value of the rotation angle in radian */\n  EIGEN_DEVICE_FUNC Scalar angle() const { return m_angle; }\n  /** \\returns a read-write reference to the stored angle in radian */\n  EIGEN_DEVICE_FUNC Scalar& angle() { return m_angle; }\n\n  /** \\returns the rotation axis */\n  EIGEN_DEVICE_FUNC const Vector3& axis() const { return m_axis; }\n  /** \\returns a read-write reference to the stored rotation axis.\n    *\n    * \\warning The rotation axis must remain a \\b unit vector.\n    */\n  EIGEN_DEVICE_FUNC Vector3& axis() { return m_axis; }\n\n  /** Concatenates two rotations */\n  EIGEN_DEVICE_FUNC inline QuaternionType operator* (const AngleAxis& other) const\n  { return QuaternionType(*this) * QuaternionType(other); }\n\n  /** Concatenates two rotations */\n  EIGEN_DEVICE_FUNC inline QuaternionType operator* (const QuaternionType& other) const\n  { return QuaternionType(*this) * other; }\n\n  /** Concatenates two rotations */\n  friend EIGEN_DEVICE_FUNC inline QuaternionType operator* (const QuaternionType& a, const AngleAxis& b)\n  { return a * QuaternionType(b); }\n\n  /** \\returns the inverse rotation, i.e., an angle-axis with opposite rotation angle */\n  EIGEN_DEVICE_FUNC AngleAxis inverse() const\n  { return AngleAxis(-m_angle, m_axis); }\n\n  template<class QuatDerived>\n  EIGEN_DEVICE_FUNC AngleAxis& operator=(const QuaternionBase<QuatDerived>& q);\n  template<typename Derived>\n  EIGEN_DEVICE_FUNC AngleAxis& operator=(const MatrixBase<Derived>& m);\n\n  template<typename Derived>\n  EIGEN_DEVICE_FUNC AngleAxis& fromRotationMatrix(const MatrixBase<Derived>& m);\n  EIGEN_DEVICE_FUNC Matrix3 toRotationMatrix(void) const;\n\n  /** \\returns \\c *this with scalar type casted to \\a NewScalarType\n    *\n    * Note that if \\a NewScalarType is equal to the current scalar type of \\c *this\n    * then this function smartly returns a const reference to \\c *this.\n    */\n  template<typename NewScalarType>\n  EIGEN_DEVICE_FUNC inline typename internal::cast_return_type<AngleAxis,AngleAxis<NewScalarType> >::type cast() const\n  { return typename internal::cast_return_type<AngleAxis,AngleAxis<NewScalarType> >::type(*this); }\n\n  /** Copy constructor with scalar type conversion */\n  template<typename OtherScalarType>\n  EIGEN_DEVICE_FUNC inline explicit AngleAxis(const AngleAxis<OtherScalarType>& other)\n  {\n    m_axis = other.axis().template cast<Scalar>();\n    m_angle = Scalar(other.angle());\n  }\n\n  EIGEN_DEVICE_FUNC static inline const AngleAxis Identity() { return AngleAxis(Scalar(0), Vector3::UnitX()); }\n\n  /** \\returns \\c true if \\c *this is approximately equal to \\a other, within the precision\n    * determined by \\a prec.\n    *\n    * \\sa MatrixBase::isApprox() */\n  EIGEN_DEVICE_FUNC bool isApprox(const AngleAxis& other, const typename NumTraits<Scalar>::Real& prec = NumTraits<Scalar>::dummy_precision()) const\n  { return m_axis.isApprox(other.m_axis, prec) && internal::isApprox(m_angle,other.m_angle, prec); }\n};\n\n/** \\ingroup Geometry_Module\n  * single precision angle-axis type */\ntypedef AngleAxis<float> AngleAxisf;\n/** \\ingroup Geometry_Module\n  * double precision angle-axis type */\ntypedef AngleAxis<double> AngleAxisd;\n\n/** Set \\c *this from a \\b unit quaternion.\n  *\n  * The resulting axis is normalized, and the computed angle is in the [0,pi] range.\n  * \n  * This function implicitly normalizes the quaternion \\a q.\n  */\ntemplate<typename Scalar>\ntemplate<typename QuatDerived>\nEIGEN_DEVICE_FUNC AngleAxis<Scalar>& AngleAxis<Scalar>::operator=(const QuaternionBase<QuatDerived>& q)\n{\n  EIGEN_USING_STD_MATH(atan2)\n  EIGEN_USING_STD_MATH(abs)\n  Scalar n = q.vec().norm();\n  if(n<NumTraits<Scalar>::epsilon())\n    n = q.vec().stableNorm();\n\n  if (n != Scalar(0))\n  {\n    m_angle = Scalar(2)*atan2(n, abs(q.w()));\n    if(q.w() < 0)\n      n = -n;\n    m_axis  = q.vec() / n;\n  }\n  else\n  {\n    m_angle = Scalar(0);\n    m_axis << Scalar(1), Scalar(0), Scalar(0);\n  }\n  return *this;\n}\n\n/** Set \\c *this from a 3x3 rotation matrix \\a mat.\n  */\ntemplate<typename Scalar>\ntemplate<typename Derived>\nEIGEN_DEVICE_FUNC AngleAxis<Scalar>& AngleAxis<Scalar>::operator=(const MatrixBase<Derived>& mat)\n{\n  // Since a direct conversion would not be really faster,\n  // let's use the robust Quaternion implementation:\n  return *this = QuaternionType(mat);\n}\n\n/**\n* \\brief Sets \\c *this from a 3x3 rotation matrix.\n**/\ntemplate<typename Scalar>\ntemplate<typename Derived>\nEIGEN_DEVICE_FUNC AngleAxis<Scalar>& AngleAxis<Scalar>::fromRotationMatrix(const MatrixBase<Derived>& mat)\n{\n  return *this = QuaternionType(mat);\n}\n\n/** Constructs and \\returns an equivalent 3x3 rotation matrix.\n  */\ntemplate<typename Scalar>\ntypename AngleAxis<Scalar>::Matrix3\nEIGEN_DEVICE_FUNC AngleAxis<Scalar>::toRotationMatrix(void) const\n{\n  EIGEN_USING_STD_MATH(sin)\n  EIGEN_USING_STD_MATH(cos)\n  Matrix3 res;\n  Vector3 sin_axis  = sin(m_angle) * m_axis;\n  Scalar c = cos(m_angle);\n  Vector3 cos1_axis = (Scalar(1)-c) * m_axis;\n\n  Scalar tmp;\n  tmp = cos1_axis.x() * m_axis.y();\n  res.coeffRef(0,1) = tmp - sin_axis.z();\n  res.coeffRef(1,0) = tmp + sin_axis.z();\n\n  tmp = cos1_axis.x() * m_axis.z();\n  res.coeffRef(0,2) = tmp + sin_axis.y();\n  res.coeffRef(2,0) = tmp - sin_axis.y();\n\n  tmp = cos1_axis.y() * m_axis.z();\n  res.coeffRef(1,2) = tmp - sin_axis.x();\n  res.coeffRef(2,1) = tmp + sin_axis.x();\n\n  res.diagonal() = (cos1_axis.cwiseProduct(m_axis)).array() + c;\n\n  return res;\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_ANGLEAXIS_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Geometry/EulerAngles.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_EULERANGLES_H\n#define EIGEN_EULERANGLES_H\n\nnamespace Eigen { \n\n/** \\geometry_module \\ingroup Geometry_Module\n  *\n  *\n  * \\returns the Euler-angles of the rotation matrix \\c *this using the convention defined by the triplet (\\a a0,\\a a1,\\a a2)\n  *\n  * Each of the three parameters \\a a0,\\a a1,\\a a2 represents the respective rotation axis as an integer in {0,1,2}.\n  * For instance, in:\n  * \\code Vector3f ea = mat.eulerAngles(2, 0, 2); \\endcode\n  * \"2\" represents the z axis and \"0\" the x axis, etc. The returned angles are such that\n  * we have the following equality:\n  * \\code\n  * mat == AngleAxisf(ea[0], Vector3f::UnitZ())\n  *      * AngleAxisf(ea[1], Vector3f::UnitX())\n  *      * AngleAxisf(ea[2], Vector3f::UnitZ()); \\endcode\n  * This corresponds to the right-multiply conventions (with right hand side frames).\n  * \n  * The returned angles are in the ranges [0:pi]x[-pi:pi]x[-pi:pi].\n  * \n  * \\sa class AngleAxis\n  */\ntemplate<typename Derived>\nEIGEN_DEVICE_FUNC inline Matrix<typename MatrixBase<Derived>::Scalar,3,1>\nMatrixBase<Derived>::eulerAngles(Index a0, Index a1, Index a2) const\n{\n  EIGEN_USING_STD_MATH(atan2)\n  EIGEN_USING_STD_MATH(sin)\n  EIGEN_USING_STD_MATH(cos)\n  /* Implemented from Graphics Gems IV */\n  EIGEN_STATIC_ASSERT_MATRIX_SPECIFIC_SIZE(Derived,3,3)\n\n  Matrix<Scalar,3,1> res;\n  typedef Matrix<typename Derived::Scalar,2,1> Vector2;\n\n  const Index odd = ((a0+1)%3 == a1) ? 0 : 1;\n  const Index i = a0;\n  const Index j = (a0 + 1 + odd)%3;\n  const Index k = (a0 + 2 - odd)%3;\n  \n  if (a0==a2)\n  {\n    res[0] = atan2(coeff(j,i), coeff(k,i));\n    if((odd && res[0]<Scalar(0)) || ((!odd) && res[0]>Scalar(0)))\n    {\n      if(res[0] > Scalar(0)) {\n        res[0] -= Scalar(EIGEN_PI);\n      }\n      else {\n        res[0] += Scalar(EIGEN_PI);\n      }\n      Scalar s2 = Vector2(coeff(j,i), coeff(k,i)).norm();\n      res[1] = -atan2(s2, coeff(i,i));\n    }\n    else\n    {\n      Scalar s2 = Vector2(coeff(j,i), coeff(k,i)).norm();\n      res[1] = atan2(s2, coeff(i,i));\n    }\n    \n    // With a=(0,1,0), we have i=0; j=1; k=2, and after computing the first two angles,\n    // we can compute their respective rotation, and apply its inverse to M. Since the result must\n    // be a rotation around x, we have:\n    //\n    //  c2  s1.s2 c1.s2                   1  0   0 \n    //  0   c1    -s1       *    M    =   0  c3  s3\n    //  -s2 s1.c2 c1.c2                   0 -s3  c3\n    //\n    //  Thus:  m11.c1 - m21.s1 = c3  &   m12.c1 - m22.s1 = s3\n    \n    Scalar s1 = sin(res[0]);\n    Scalar c1 = cos(res[0]);\n    res[2] = atan2(c1*coeff(j,k)-s1*coeff(k,k), c1*coeff(j,j) - s1 * coeff(k,j));\n  } \n  else\n  {\n    res[0] = atan2(coeff(j,k), coeff(k,k));\n    Scalar c2 = Vector2(coeff(i,i), coeff(i,j)).norm();\n    if((odd && res[0]<Scalar(0)) || ((!odd) && res[0]>Scalar(0))) {\n      if(res[0] > Scalar(0)) {\n        res[0] -= Scalar(EIGEN_PI);\n      }\n      else {\n        res[0] += Scalar(EIGEN_PI);\n      }\n      res[1] = atan2(-coeff(i,k), -c2);\n    }\n    else\n      res[1] = atan2(-coeff(i,k), c2);\n    Scalar s1 = sin(res[0]);\n    Scalar c1 = cos(res[0]);\n    res[2] = atan2(s1*coeff(k,i)-c1*coeff(j,i), c1*coeff(j,j) - s1 * coeff(k,j));\n  }\n  if (!odd)\n    res = -res;\n  \n  return res;\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_EULERANGLES_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Geometry/Homogeneous.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009-2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_HOMOGENEOUS_H\n#define EIGEN_HOMOGENEOUS_H\n\nnamespace Eigen { \n\n/** \\geometry_module \\ingroup Geometry_Module\n  *\n  * \\class Homogeneous\n  *\n  * \\brief Expression of one (or a set of) homogeneous vector(s)\n  *\n  * \\param MatrixType the type of the object in which we are making homogeneous\n  *\n  * This class represents an expression of one (or a set of) homogeneous vector(s).\n  * It is the return type of MatrixBase::homogeneous() and most of the time\n  * this is the only way it is used.\n  *\n  * \\sa MatrixBase::homogeneous()\n  */\n\nnamespace internal {\n\ntemplate<typename MatrixType,int Direction>\nstruct traits<Homogeneous<MatrixType,Direction> >\n : traits<MatrixType>\n{\n  typedef typename traits<MatrixType>::StorageKind StorageKind;\n  typedef typename ref_selector<MatrixType>::type MatrixTypeNested;\n  typedef typename remove_reference<MatrixTypeNested>::type _MatrixTypeNested;\n  enum {\n    RowsPlusOne = (MatrixType::RowsAtCompileTime != Dynamic) ?\n                  int(MatrixType::RowsAtCompileTime) + 1 : Dynamic,\n    ColsPlusOne = (MatrixType::ColsAtCompileTime != Dynamic) ?\n                  int(MatrixType::ColsAtCompileTime) + 1 : Dynamic,\n    RowsAtCompileTime = Direction==Vertical  ?  RowsPlusOne : MatrixType::RowsAtCompileTime,\n    ColsAtCompileTime = Direction==Horizontal ? ColsPlusOne : MatrixType::ColsAtCompileTime,\n    MaxRowsAtCompileTime = RowsAtCompileTime,\n    MaxColsAtCompileTime = ColsAtCompileTime,\n    TmpFlags = _MatrixTypeNested::Flags & HereditaryBits,\n    Flags = ColsAtCompileTime==1 ? (TmpFlags & ~RowMajorBit)\n          : RowsAtCompileTime==1 ? (TmpFlags | RowMajorBit)\n          : TmpFlags\n  };\n};\n\ntemplate<typename MatrixType,typename Lhs> struct homogeneous_left_product_impl;\ntemplate<typename MatrixType,typename Rhs> struct homogeneous_right_product_impl;\n\n} // end namespace internal\n\ntemplate<typename MatrixType,int _Direction> class Homogeneous\n  : public MatrixBase<Homogeneous<MatrixType,_Direction> >, internal::no_assignment_operator\n{\n  public:\n\n    typedef MatrixType NestedExpression;\n    enum { Direction = _Direction };\n\n    typedef MatrixBase<Homogeneous> Base;\n    EIGEN_DENSE_PUBLIC_INTERFACE(Homogeneous)\n\n    EIGEN_DEVICE_FUNC explicit inline Homogeneous(const MatrixType& matrix)\n      : m_matrix(matrix)\n    {}\n\n    EIGEN_DEVICE_FUNC inline Index rows() const { return m_matrix.rows() + (int(Direction)==Vertical   ? 1 : 0); }\n    EIGEN_DEVICE_FUNC inline Index cols() const { return m_matrix.cols() + (int(Direction)==Horizontal ? 1 : 0); }\n    \n    EIGEN_DEVICE_FUNC const NestedExpression& nestedExpression() const { return m_matrix; }\n\n    template<typename Rhs>\n    EIGEN_DEVICE_FUNC inline const Product<Homogeneous,Rhs>\n    operator* (const MatrixBase<Rhs>& rhs) const\n    {\n      eigen_assert(int(Direction)==Horizontal);\n      return Product<Homogeneous,Rhs>(*this,rhs.derived());\n    }\n\n    template<typename Lhs> friend\n    EIGEN_DEVICE_FUNC inline const Product<Lhs,Homogeneous>\n    operator* (const MatrixBase<Lhs>& lhs, const Homogeneous& rhs)\n    {\n      eigen_assert(int(Direction)==Vertical);\n      return Product<Lhs,Homogeneous>(lhs.derived(),rhs);\n    }\n\n    template<typename Scalar, int Dim, int Mode, int Options> friend\n    EIGEN_DEVICE_FUNC inline const Product<Transform<Scalar,Dim,Mode,Options>, Homogeneous >\n    operator* (const Transform<Scalar,Dim,Mode,Options>& lhs, const Homogeneous& rhs)\n    {\n      eigen_assert(int(Direction)==Vertical);\n      return Product<Transform<Scalar,Dim,Mode,Options>, Homogeneous>(lhs,rhs);\n    }\n\n    template<typename Func>\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE typename internal::result_of<Func(Scalar,Scalar)>::type\n    redux(const Func& func) const\n    {\n      return func(m_matrix.redux(func), Scalar(1));\n    }\n\n  protected:\n    typename MatrixType::Nested m_matrix;\n};\n\n/** \\geometry_module \\ingroup Geometry_Module\n  *\n  * \\returns a vector expression that is one longer than the vector argument, with the value 1 symbolically appended as the last coefficient.\n  *\n  * This can be used to convert affine coordinates to homogeneous coordinates.\n  *\n  * \\only_for_vectors\n  *\n  * Example: \\include MatrixBase_homogeneous.cpp\n  * Output: \\verbinclude MatrixBase_homogeneous.out\n  *\n  * \\sa VectorwiseOp::homogeneous(), class Homogeneous\n  */\ntemplate<typename Derived>\nEIGEN_DEVICE_FUNC inline typename MatrixBase<Derived>::HomogeneousReturnType\nMatrixBase<Derived>::homogeneous() const\n{\n  EIGEN_STATIC_ASSERT_VECTOR_ONLY(Derived);\n  return HomogeneousReturnType(derived());\n}\n\n/** \\geometry_module \\ingroup Geometry_Module\n  *\n  * \\returns an expression where the value 1 is symbolically appended as the final coefficient to each column (or row) of the matrix.\n  *\n  * This can be used to convert affine coordinates to homogeneous coordinates.\n  *\n  * Example: \\include VectorwiseOp_homogeneous.cpp\n  * Output: \\verbinclude VectorwiseOp_homogeneous.out\n  *\n  * \\sa MatrixBase::homogeneous(), class Homogeneous */\ntemplate<typename ExpressionType, int Direction>\nEIGEN_DEVICE_FUNC inline Homogeneous<ExpressionType,Direction>\nVectorwiseOp<ExpressionType,Direction>::homogeneous() const\n{\n  return HomogeneousReturnType(_expression());\n}\n\n/** \\geometry_module \\ingroup Geometry_Module\n  *\n  * \\brief homogeneous normalization\n  *\n  * \\returns a vector expression of the N-1 first coefficients of \\c *this divided by that last coefficient.\n  *\n  * This can be used to convert homogeneous coordinates to affine coordinates.\n  *\n  * It is essentially a shortcut for:\n  * \\code\n    this->head(this->size()-1)/this->coeff(this->size()-1);\n    \\endcode\n  *\n  * Example: \\include MatrixBase_hnormalized.cpp\n  * Output: \\verbinclude MatrixBase_hnormalized.out\n  *\n  * \\sa VectorwiseOp::hnormalized() */\ntemplate<typename Derived>\nEIGEN_DEVICE_FUNC inline const typename MatrixBase<Derived>::HNormalizedReturnType\nMatrixBase<Derived>::hnormalized() const\n{\n  EIGEN_STATIC_ASSERT_VECTOR_ONLY(Derived);\n  return ConstStartMinusOne(derived(),0,0,\n    ColsAtCompileTime==1?size()-1:1,\n    ColsAtCompileTime==1?1:size()-1) / coeff(size()-1);\n}\n\n/** \\geometry_module \\ingroup Geometry_Module\n  *\n  * \\brief column or row-wise homogeneous normalization\n  *\n  * \\returns an expression of the first N-1 coefficients of each column (or row) of \\c *this divided by the last coefficient of each column (or row).\n  *\n  * This can be used to convert homogeneous coordinates to affine coordinates.\n  *\n  * It is conceptually equivalent to calling MatrixBase::hnormalized() to each column (or row) of \\c *this.\n  *\n  * Example: \\include DirectionWise_hnormalized.cpp\n  * Output: \\verbinclude DirectionWise_hnormalized.out\n  *\n  * \\sa MatrixBase::hnormalized() */\ntemplate<typename ExpressionType, int Direction>\nEIGEN_DEVICE_FUNC inline const typename VectorwiseOp<ExpressionType,Direction>::HNormalizedReturnType\nVectorwiseOp<ExpressionType,Direction>::hnormalized() const\n{\n  return HNormalized_Block(_expression(),0,0,\n      Direction==Vertical   ? _expression().rows()-1 : _expression().rows(),\n      Direction==Horizontal ? _expression().cols()-1 : _expression().cols()).cwiseQuotient(\n      Replicate<HNormalized_Factors,\n                Direction==Vertical   ? HNormalized_SizeMinusOne : 1,\n                Direction==Horizontal ? HNormalized_SizeMinusOne : 1>\n        (HNormalized_Factors(_expression(),\n          Direction==Vertical    ? _expression().rows()-1:0,\n          Direction==Horizontal  ? _expression().cols()-1:0,\n          Direction==Vertical    ? 1 : _expression().rows(),\n          Direction==Horizontal  ? 1 : _expression().cols()),\n         Direction==Vertical   ? _expression().rows()-1 : 1,\n         Direction==Horizontal ? _expression().cols()-1 : 1));\n}\n\nnamespace internal {\n\ntemplate<typename MatrixOrTransformType>\nstruct take_matrix_for_product\n{\n  typedef MatrixOrTransformType type;\n  EIGEN_DEVICE_FUNC static const type& run(const type &x) { return x; }\n};\n\ntemplate<typename Scalar, int Dim, int Mode,int Options>\nstruct take_matrix_for_product<Transform<Scalar, Dim, Mode, Options> >\n{\n  typedef Transform<Scalar, Dim, Mode, Options> TransformType;\n  typedef typename internal::add_const<typename TransformType::ConstAffinePart>::type type;\n  EIGEN_DEVICE_FUNC static type run (const TransformType& x) { return x.affine(); }\n};\n\ntemplate<typename Scalar, int Dim, int Options>\nstruct take_matrix_for_product<Transform<Scalar, Dim, Projective, Options> >\n{\n  typedef Transform<Scalar, Dim, Projective, Options> TransformType;\n  typedef typename TransformType::MatrixType type;\n  EIGEN_DEVICE_FUNC static const type& run (const TransformType& x) { return x.matrix(); }\n};\n\ntemplate<typename MatrixType,typename Lhs>\nstruct traits<homogeneous_left_product_impl<Homogeneous<MatrixType,Vertical>,Lhs> >\n{\n  typedef typename take_matrix_for_product<Lhs>::type LhsMatrixType;\n  typedef typename remove_all<MatrixType>::type MatrixTypeCleaned;\n  typedef typename remove_all<LhsMatrixType>::type LhsMatrixTypeCleaned;\n  typedef typename make_proper_matrix_type<\n                 typename traits<MatrixTypeCleaned>::Scalar,\n                 LhsMatrixTypeCleaned::RowsAtCompileTime,\n                 MatrixTypeCleaned::ColsAtCompileTime,\n                 MatrixTypeCleaned::PlainObject::Options,\n                 LhsMatrixTypeCleaned::MaxRowsAtCompileTime,\n                 MatrixTypeCleaned::MaxColsAtCompileTime>::type ReturnType;\n};\n\ntemplate<typename MatrixType,typename Lhs>\nstruct homogeneous_left_product_impl<Homogeneous<MatrixType,Vertical>,Lhs>\n  : public ReturnByValue<homogeneous_left_product_impl<Homogeneous<MatrixType,Vertical>,Lhs> >\n{\n  typedef typename traits<homogeneous_left_product_impl>::LhsMatrixType LhsMatrixType;\n  typedef typename remove_all<LhsMatrixType>::type LhsMatrixTypeCleaned;\n  typedef typename remove_all<typename LhsMatrixTypeCleaned::Nested>::type LhsMatrixTypeNested;\n  EIGEN_DEVICE_FUNC homogeneous_left_product_impl(const Lhs& lhs, const MatrixType& rhs)\n    : m_lhs(take_matrix_for_product<Lhs>::run(lhs)),\n      m_rhs(rhs)\n  {}\n\n  EIGEN_DEVICE_FUNC inline Index rows() const { return m_lhs.rows(); }\n  EIGEN_DEVICE_FUNC inline Index cols() const { return m_rhs.cols(); }\n\n  template<typename Dest> EIGEN_DEVICE_FUNC void evalTo(Dest& dst) const\n  {\n    // FIXME investigate how to allow lazy evaluation of this product when possible\n    dst = Block<const LhsMatrixTypeNested,\n              LhsMatrixTypeNested::RowsAtCompileTime,\n              LhsMatrixTypeNested::ColsAtCompileTime==Dynamic?Dynamic:LhsMatrixTypeNested::ColsAtCompileTime-1>\n            (m_lhs,0,0,m_lhs.rows(),m_lhs.cols()-1) * m_rhs;\n    dst += m_lhs.col(m_lhs.cols()-1).rowwise()\n            .template replicate<MatrixType::ColsAtCompileTime>(m_rhs.cols());\n  }\n\n  typename LhsMatrixTypeCleaned::Nested m_lhs;\n  typename MatrixType::Nested m_rhs;\n};\n\ntemplate<typename MatrixType,typename Rhs>\nstruct traits<homogeneous_right_product_impl<Homogeneous<MatrixType,Horizontal>,Rhs> >\n{\n  typedef typename make_proper_matrix_type<typename traits<MatrixType>::Scalar,\n                 MatrixType::RowsAtCompileTime,\n                 Rhs::ColsAtCompileTime,\n                 MatrixType::PlainObject::Options,\n                 MatrixType::MaxRowsAtCompileTime,\n                 Rhs::MaxColsAtCompileTime>::type ReturnType;\n};\n\ntemplate<typename MatrixType,typename Rhs>\nstruct homogeneous_right_product_impl<Homogeneous<MatrixType,Horizontal>,Rhs>\n  : public ReturnByValue<homogeneous_right_product_impl<Homogeneous<MatrixType,Horizontal>,Rhs> >\n{\n  typedef typename remove_all<typename Rhs::Nested>::type RhsNested;\n  EIGEN_DEVICE_FUNC homogeneous_right_product_impl(const MatrixType& lhs, const Rhs& rhs)\n    : m_lhs(lhs), m_rhs(rhs)\n  {}\n\n  EIGEN_DEVICE_FUNC inline Index rows() const { return m_lhs.rows(); }\n  EIGEN_DEVICE_FUNC inline Index cols() const { return m_rhs.cols(); }\n\n  template<typename Dest> EIGEN_DEVICE_FUNC void evalTo(Dest& dst) const\n  {\n    // FIXME investigate how to allow lazy evaluation of this product when possible\n    dst = m_lhs * Block<const RhsNested,\n                        RhsNested::RowsAtCompileTime==Dynamic?Dynamic:RhsNested::RowsAtCompileTime-1,\n                        RhsNested::ColsAtCompileTime>\n            (m_rhs,0,0,m_rhs.rows()-1,m_rhs.cols());\n    dst += m_rhs.row(m_rhs.rows()-1).colwise()\n            .template replicate<MatrixType::RowsAtCompileTime>(m_lhs.rows());\n  }\n\n  typename MatrixType::Nested m_lhs;\n  typename Rhs::Nested m_rhs;\n};\n\ntemplate<typename ArgType,int Direction>\nstruct evaluator_traits<Homogeneous<ArgType,Direction> >\n{\n  typedef typename storage_kind_to_evaluator_kind<typename ArgType::StorageKind>::Kind Kind;\n  typedef HomogeneousShape Shape;  \n};\n\ntemplate<> struct AssignmentKind<DenseShape,HomogeneousShape> { typedef Dense2Dense Kind; };\n\n\ntemplate<typename ArgType,int Direction>\nstruct unary_evaluator<Homogeneous<ArgType,Direction>, IndexBased>\n  : evaluator<typename Homogeneous<ArgType,Direction>::PlainObject >\n{\n  typedef Homogeneous<ArgType,Direction> XprType;\n  typedef typename XprType::PlainObject PlainObject;\n  typedef evaluator<PlainObject> Base;\n\n  EIGEN_DEVICE_FUNC explicit unary_evaluator(const XprType& op)\n    : Base(), m_temp(op)\n  {\n    ::new (static_cast<Base*>(this)) Base(m_temp);\n  }\n\nprotected:\n  PlainObject m_temp;\n};\n\n// dense = homogeneous\ntemplate< typename DstXprType, typename ArgType, typename Scalar>\nstruct Assignment<DstXprType, Homogeneous<ArgType,Vertical>, internal::assign_op<Scalar,typename ArgType::Scalar>, Dense2Dense>\n{\n  typedef Homogeneous<ArgType,Vertical> SrcXprType;\n  EIGEN_DEVICE_FUNC static void run(DstXprType &dst, const SrcXprType &src, const internal::assign_op<Scalar,typename ArgType::Scalar> &)\n  {\n    Index dstRows = src.rows();\n    Index dstCols = src.cols();\n    if((dst.rows()!=dstRows) || (dst.cols()!=dstCols))\n      dst.resize(dstRows, dstCols);\n\n    dst.template topRows<ArgType::RowsAtCompileTime>(src.nestedExpression().rows()) = src.nestedExpression();\n    dst.row(dst.rows()-1).setOnes();\n  }\n};\n\n// dense = homogeneous\ntemplate< typename DstXprType, typename ArgType, typename Scalar>\nstruct Assignment<DstXprType, Homogeneous<ArgType,Horizontal>, internal::assign_op<Scalar,typename ArgType::Scalar>, Dense2Dense>\n{\n  typedef Homogeneous<ArgType,Horizontal> SrcXprType;\n  EIGEN_DEVICE_FUNC static void run(DstXprType &dst, const SrcXprType &src, const internal::assign_op<Scalar,typename ArgType::Scalar> &)\n  {\n    Index dstRows = src.rows();\n    Index dstCols = src.cols();\n    if((dst.rows()!=dstRows) || (dst.cols()!=dstCols))\n      dst.resize(dstRows, dstCols);\n\n    dst.template leftCols<ArgType::ColsAtCompileTime>(src.nestedExpression().cols()) = src.nestedExpression();\n    dst.col(dst.cols()-1).setOnes();\n  }\n};\n\ntemplate<typename LhsArg, typename Rhs, int ProductTag>\nstruct generic_product_impl<Homogeneous<LhsArg,Horizontal>, Rhs, HomogeneousShape, DenseShape, ProductTag>\n{\n  template<typename Dest>\n  EIGEN_DEVICE_FUNC static void evalTo(Dest& dst, const Homogeneous<LhsArg,Horizontal>& lhs, const Rhs& rhs)\n  {\n    homogeneous_right_product_impl<Homogeneous<LhsArg,Horizontal>, Rhs>(lhs.nestedExpression(), rhs).evalTo(dst);\n  }\n};\n\ntemplate<typename Lhs,typename Rhs>\nstruct homogeneous_right_product_refactoring_helper\n{\n  enum {\n    Dim  = Lhs::ColsAtCompileTime,\n    Rows = Lhs::RowsAtCompileTime\n  };\n  typedef typename Rhs::template ConstNRowsBlockXpr<Dim>::Type          LinearBlockConst;\n  typedef typename remove_const<LinearBlockConst>::type                 LinearBlock;\n  typedef typename Rhs::ConstRowXpr                                     ConstantColumn;\n  typedef Replicate<const ConstantColumn,Rows,1>                        ConstantBlock;\n  typedef Product<Lhs,LinearBlock,LazyProduct>                          LinearProduct;\n  typedef CwiseBinaryOp<internal::scalar_sum_op<typename Lhs::Scalar,typename Rhs::Scalar>, const LinearProduct, const ConstantBlock> Xpr;\n};\n\ntemplate<typename Lhs, typename Rhs, int ProductTag>\nstruct product_evaluator<Product<Lhs, Rhs, LazyProduct>, ProductTag, HomogeneousShape, DenseShape>\n : public evaluator<typename homogeneous_right_product_refactoring_helper<typename Lhs::NestedExpression,Rhs>::Xpr>\n{\n  typedef Product<Lhs, Rhs, LazyProduct> XprType;\n  typedef homogeneous_right_product_refactoring_helper<typename Lhs::NestedExpression,Rhs> helper;\n  typedef typename helper::ConstantBlock ConstantBlock;\n  typedef typename helper::Xpr RefactoredXpr;\n  typedef evaluator<RefactoredXpr> Base;\n  \n  EIGEN_DEVICE_FUNC explicit product_evaluator(const XprType& xpr)\n    : Base(  xpr.lhs().nestedExpression() .lazyProduct(  xpr.rhs().template topRows<helper::Dim>(xpr.lhs().nestedExpression().cols()) )\n            + ConstantBlock(xpr.rhs().row(xpr.rhs().rows()-1),xpr.lhs().rows(), 1) )\n  {}\n};\n\ntemplate<typename Lhs, typename RhsArg, int ProductTag>\nstruct generic_product_impl<Lhs, Homogeneous<RhsArg,Vertical>, DenseShape, HomogeneousShape, ProductTag>\n{\n  template<typename Dest>\n  EIGEN_DEVICE_FUNC static void evalTo(Dest& dst, const Lhs& lhs, const Homogeneous<RhsArg,Vertical>& rhs)\n  {\n    homogeneous_left_product_impl<Homogeneous<RhsArg,Vertical>, Lhs>(lhs, rhs.nestedExpression()).evalTo(dst);\n  }\n};\n\n// TODO: the following specialization is to address a regression from 3.2 to 3.3\n// In the future, this path should be optimized.\ntemplate<typename Lhs, typename RhsArg, int ProductTag>\nstruct generic_product_impl<Lhs, Homogeneous<RhsArg,Vertical>, TriangularShape, HomogeneousShape, ProductTag>\n{\n  template<typename Dest>\n  static void evalTo(Dest& dst, const Lhs& lhs, const Homogeneous<RhsArg,Vertical>& rhs)\n  {\n    dst.noalias() = lhs * rhs.eval();\n  }\n};\n\ntemplate<typename Lhs,typename Rhs>\nstruct homogeneous_left_product_refactoring_helper\n{\n  enum {\n    Dim = Rhs::RowsAtCompileTime,\n    Cols = Rhs::ColsAtCompileTime\n  };\n  typedef typename Lhs::template ConstNColsBlockXpr<Dim>::Type          LinearBlockConst;\n  typedef typename remove_const<LinearBlockConst>::type                 LinearBlock;\n  typedef typename Lhs::ConstColXpr                                     ConstantColumn;\n  typedef Replicate<const ConstantColumn,1,Cols>                        ConstantBlock;\n  typedef Product<LinearBlock,Rhs,LazyProduct>                          LinearProduct;\n  typedef CwiseBinaryOp<internal::scalar_sum_op<typename Lhs::Scalar,typename Rhs::Scalar>, const LinearProduct, const ConstantBlock> Xpr;\n};\n\ntemplate<typename Lhs, typename Rhs, int ProductTag>\nstruct product_evaluator<Product<Lhs, Rhs, LazyProduct>, ProductTag, DenseShape, HomogeneousShape>\n : public evaluator<typename homogeneous_left_product_refactoring_helper<Lhs,typename Rhs::NestedExpression>::Xpr>\n{\n  typedef Product<Lhs, Rhs, LazyProduct> XprType;\n  typedef homogeneous_left_product_refactoring_helper<Lhs,typename Rhs::NestedExpression> helper;\n  typedef typename helper::ConstantBlock ConstantBlock;\n  typedef typename helper::Xpr RefactoredXpr;\n  typedef evaluator<RefactoredXpr> Base;\n  \n  EIGEN_DEVICE_FUNC explicit product_evaluator(const XprType& xpr)\n    : Base(   xpr.lhs().template leftCols<helper::Dim>(xpr.rhs().nestedExpression().rows()) .lazyProduct( xpr.rhs().nestedExpression() )\n            + ConstantBlock(xpr.lhs().col(xpr.lhs().cols()-1),1,xpr.rhs().cols()) )\n  {}\n};\n\ntemplate<typename Scalar, int Dim, int Mode,int Options, typename RhsArg, int ProductTag>\nstruct generic_product_impl<Transform<Scalar,Dim,Mode,Options>, Homogeneous<RhsArg,Vertical>, DenseShape, HomogeneousShape, ProductTag>\n{\n  typedef Transform<Scalar,Dim,Mode,Options> TransformType;\n  template<typename Dest>\n  EIGEN_DEVICE_FUNC static void evalTo(Dest& dst, const TransformType& lhs, const Homogeneous<RhsArg,Vertical>& rhs)\n  {\n    homogeneous_left_product_impl<Homogeneous<RhsArg,Vertical>, TransformType>(lhs, rhs.nestedExpression()).evalTo(dst);\n  }\n};\n\ntemplate<typename ExpressionType, int Side, bool Transposed>\nstruct permutation_matrix_product<ExpressionType, Side, Transposed, HomogeneousShape>\n  : public permutation_matrix_product<ExpressionType, Side, Transposed, DenseShape>\n{};\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_HOMOGENEOUS_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Geometry/Hyperplane.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2008 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_HYPERPLANE_H\n#define EIGEN_HYPERPLANE_H\n\nnamespace Eigen { \n\n/** \\geometry_module \\ingroup Geometry_Module\n  *\n  * \\class Hyperplane\n  *\n  * \\brief A hyperplane\n  *\n  * A hyperplane is an affine subspace of dimension n-1 in a space of dimension n.\n  * For example, a hyperplane in a plane is a line; a hyperplane in 3-space is a plane.\n  *\n  * \\tparam _Scalar the scalar type, i.e., the type of the coefficients\n  * \\tparam _AmbientDim the dimension of the ambient space, can be a compile time value or Dynamic.\n  *             Notice that the dimension of the hyperplane is _AmbientDim-1.\n  *\n  * This class represents an hyperplane as the zero set of the implicit equation\n  * \\f$ n \\cdot x + d = 0 \\f$ where \\f$ n \\f$ is a unit normal vector of the plane (linear part)\n  * and \\f$ d \\f$ is the distance (offset) to the origin.\n  */\ntemplate <typename _Scalar, int _AmbientDim, int _Options>\nclass Hyperplane\n{\npublic:\n  EIGEN_MAKE_ALIGNED_OPERATOR_NEW_IF_VECTORIZABLE_FIXED_SIZE(_Scalar,_AmbientDim==Dynamic ? Dynamic : _AmbientDim+1)\n  enum {\n    AmbientDimAtCompileTime = _AmbientDim,\n    Options = _Options\n  };\n  typedef _Scalar Scalar;\n  typedef typename NumTraits<Scalar>::Real RealScalar;\n  typedef Eigen::Index Index; ///< \\deprecated since Eigen 3.3\n  typedef Matrix<Scalar,AmbientDimAtCompileTime,1> VectorType;\n  typedef Matrix<Scalar,Index(AmbientDimAtCompileTime)==Dynamic\n                        ? Dynamic\n                        : Index(AmbientDimAtCompileTime)+1,1,Options> Coefficients;\n  typedef Block<Coefficients,AmbientDimAtCompileTime,1> NormalReturnType;\n  typedef const Block<const Coefficients,AmbientDimAtCompileTime,1> ConstNormalReturnType;\n\n  /** Default constructor without initialization */\n  EIGEN_DEVICE_FUNC inline Hyperplane() {}\n  \n  template<int OtherOptions>\n  EIGEN_DEVICE_FUNC Hyperplane(const Hyperplane<Scalar,AmbientDimAtCompileTime,OtherOptions>& other)\n   : m_coeffs(other.coeffs())\n  {}\n\n  /** Constructs a dynamic-size hyperplane with \\a _dim the dimension\n    * of the ambient space */\n  EIGEN_DEVICE_FUNC inline explicit Hyperplane(Index _dim) : m_coeffs(_dim+1) {}\n\n  /** Construct a plane from its normal \\a n and a point \\a e onto the plane.\n    * \\warning the vector normal is assumed to be normalized.\n    */\n  EIGEN_DEVICE_FUNC inline Hyperplane(const VectorType& n, const VectorType& e)\n    : m_coeffs(n.size()+1)\n  {\n    normal() = n;\n    offset() = -n.dot(e);\n  }\n\n  /** Constructs a plane from its normal \\a n and distance to the origin \\a d\n    * such that the algebraic equation of the plane is \\f$ n \\cdot x + d = 0 \\f$.\n    * \\warning the vector normal is assumed to be normalized.\n    */\n  EIGEN_DEVICE_FUNC inline Hyperplane(const VectorType& n, const Scalar& d)\n    : m_coeffs(n.size()+1)\n  {\n    normal() = n;\n    offset() = d;\n  }\n\n  /** Constructs a hyperplane passing through the two points. If the dimension of the ambient space\n    * is greater than 2, then there isn't uniqueness, so an arbitrary choice is made.\n    */\n  EIGEN_DEVICE_FUNC static inline Hyperplane Through(const VectorType& p0, const VectorType& p1)\n  {\n    Hyperplane result(p0.size());\n    result.normal() = (p1 - p0).unitOrthogonal();\n    result.offset() = -p0.dot(result.normal());\n    return result;\n  }\n\n  /** Constructs a hyperplane passing through the three points. The dimension of the ambient space\n    * is required to be exactly 3.\n    */\n  EIGEN_DEVICE_FUNC static inline Hyperplane Through(const VectorType& p0, const VectorType& p1, const VectorType& p2)\n  {\n    EIGEN_STATIC_ASSERT_VECTOR_SPECIFIC_SIZE(VectorType, 3)\n    Hyperplane result(p0.size());\n    VectorType v0(p2 - p0), v1(p1 - p0);\n    result.normal() = v0.cross(v1);\n    RealScalar norm = result.normal().norm();\n    if(norm <= v0.norm() * v1.norm() * NumTraits<RealScalar>::epsilon())\n    {\n      Matrix<Scalar,2,3> m; m << v0.transpose(), v1.transpose();\n      JacobiSVD<Matrix<Scalar,2,3> > svd(m, ComputeFullV);\n      result.normal() = svd.matrixV().col(2);\n    }\n    else\n      result.normal() /= norm;\n    result.offset() = -p0.dot(result.normal());\n    return result;\n  }\n\n  /** Constructs a hyperplane passing through the parametrized line \\a parametrized.\n    * If the dimension of the ambient space is greater than 2, then there isn't uniqueness,\n    * so an arbitrary choice is made.\n    */\n  // FIXME to be consitent with the rest this could be implemented as a static Through function ??\n  EIGEN_DEVICE_FUNC explicit Hyperplane(const ParametrizedLine<Scalar, AmbientDimAtCompileTime>& parametrized)\n  {\n    normal() = parametrized.direction().unitOrthogonal();\n    offset() = -parametrized.origin().dot(normal());\n  }\n\n  EIGEN_DEVICE_FUNC ~Hyperplane() {}\n\n  /** \\returns the dimension in which the plane holds */\n  EIGEN_DEVICE_FUNC inline Index dim() const { return AmbientDimAtCompileTime==Dynamic ? m_coeffs.size()-1 : Index(AmbientDimAtCompileTime); }\n\n  /** normalizes \\c *this */\n  EIGEN_DEVICE_FUNC void normalize(void)\n  {\n    m_coeffs /= normal().norm();\n  }\n\n  /** \\returns the signed distance between the plane \\c *this and a point \\a p.\n    * \\sa absDistance()\n    */\n  EIGEN_DEVICE_FUNC inline Scalar signedDistance(const VectorType& p) const { return normal().dot(p) + offset(); }\n\n  /** \\returns the absolute distance between the plane \\c *this and a point \\a p.\n    * \\sa signedDistance()\n    */\n  EIGEN_DEVICE_FUNC inline Scalar absDistance(const VectorType& p) const { return numext::abs(signedDistance(p)); }\n\n  /** \\returns the projection of a point \\a p onto the plane \\c *this.\n    */\n  EIGEN_DEVICE_FUNC inline VectorType projection(const VectorType& p) const { return p - signedDistance(p) * normal(); }\n\n  /** \\returns a constant reference to the unit normal vector of the plane, which corresponds\n    * to the linear part of the implicit equation.\n    */\n  EIGEN_DEVICE_FUNC inline ConstNormalReturnType normal() const { return ConstNormalReturnType(m_coeffs,0,0,dim(),1); }\n\n  /** \\returns a non-constant reference to the unit normal vector of the plane, which corresponds\n    * to the linear part of the implicit equation.\n    */\n  EIGEN_DEVICE_FUNC inline NormalReturnType normal() { return NormalReturnType(m_coeffs,0,0,dim(),1); }\n\n  /** \\returns the distance to the origin, which is also the \"constant term\" of the implicit equation\n    * \\warning the vector normal is assumed to be normalized.\n    */\n  EIGEN_DEVICE_FUNC inline const Scalar& offset() const { return m_coeffs.coeff(dim()); }\n\n  /** \\returns a non-constant reference to the distance to the origin, which is also the constant part\n    * of the implicit equation */\n  EIGEN_DEVICE_FUNC inline Scalar& offset() { return m_coeffs(dim()); }\n\n  /** \\returns a constant reference to the coefficients c_i of the plane equation:\n    * \\f$ c_0*x_0 + ... + c_{d-1}*x_{d-1} + c_d = 0 \\f$\n    */\n  EIGEN_DEVICE_FUNC inline const Coefficients& coeffs() const { return m_coeffs; }\n\n  /** \\returns a non-constant reference to the coefficients c_i of the plane equation:\n    * \\f$ c_0*x_0 + ... + c_{d-1}*x_{d-1} + c_d = 0 \\f$\n    */\n  EIGEN_DEVICE_FUNC inline Coefficients& coeffs() { return m_coeffs; }\n\n  /** \\returns the intersection of *this with \\a other.\n    *\n    * \\warning The ambient space must be a plane, i.e. have dimension 2, so that \\c *this and \\a other are lines.\n    *\n    * \\note If \\a other is approximately parallel to *this, this method will return any point on *this.\n    */\n  EIGEN_DEVICE_FUNC VectorType intersection(const Hyperplane& other) const\n  {\n    EIGEN_STATIC_ASSERT_VECTOR_SPECIFIC_SIZE(VectorType, 2)\n    Scalar det = coeffs().coeff(0) * other.coeffs().coeff(1) - coeffs().coeff(1) * other.coeffs().coeff(0);\n    // since the line equations ax+by=c are normalized with a^2+b^2=1, the following tests\n    // whether the two lines are approximately parallel.\n    if(internal::isMuchSmallerThan(det, Scalar(1)))\n    {   // special case where the two lines are approximately parallel. Pick any point on the first line.\n        if(numext::abs(coeffs().coeff(1))>numext::abs(coeffs().coeff(0)))\n            return VectorType(coeffs().coeff(1), -coeffs().coeff(2)/coeffs().coeff(1)-coeffs().coeff(0));\n        else\n            return VectorType(-coeffs().coeff(2)/coeffs().coeff(0)-coeffs().coeff(1), coeffs().coeff(0));\n    }\n    else\n    {   // general case\n        Scalar invdet = Scalar(1) / det;\n        return VectorType(invdet*(coeffs().coeff(1)*other.coeffs().coeff(2)-other.coeffs().coeff(1)*coeffs().coeff(2)),\n                          invdet*(other.coeffs().coeff(0)*coeffs().coeff(2)-coeffs().coeff(0)*other.coeffs().coeff(2)));\n    }\n  }\n\n  /** Applies the transformation matrix \\a mat to \\c *this and returns a reference to \\c *this.\n    *\n    * \\param mat the Dim x Dim transformation matrix\n    * \\param traits specifies whether the matrix \\a mat represents an #Isometry\n    *               or a more generic #Affine transformation. The default is #Affine.\n    */\n  template<typename XprType>\n  EIGEN_DEVICE_FUNC inline Hyperplane& transform(const MatrixBase<XprType>& mat, TransformTraits traits = Affine)\n  {\n    if (traits==Affine)\n      normal() = mat.inverse().transpose() * normal();\n    else if (traits==Isometry)\n      normal() = mat * normal();\n    else\n    {\n      eigen_assert(0 && \"invalid traits value in Hyperplane::transform()\");\n    }\n    return *this;\n  }\n\n  /** Applies the transformation \\a t to \\c *this and returns a reference to \\c *this.\n    *\n    * \\param t the transformation of dimension Dim\n    * \\param traits specifies whether the transformation \\a t represents an #Isometry\n    *               or a more generic #Affine transformation. The default is #Affine.\n    *               Other kind of transformations are not supported.\n    */\n  template<int TrOptions>\n  EIGEN_DEVICE_FUNC inline Hyperplane& transform(const Transform<Scalar,AmbientDimAtCompileTime,Affine,TrOptions>& t,\n                                TransformTraits traits = Affine)\n  {\n    transform(t.linear(), traits);\n    offset() -= normal().dot(t.translation());\n    return *this;\n  }\n\n  /** \\returns \\c *this with scalar type casted to \\a NewScalarType\n    *\n    * Note that if \\a NewScalarType is equal to the current scalar type of \\c *this\n    * then this function smartly returns a const reference to \\c *this.\n    */\n  template<typename NewScalarType>\n  EIGEN_DEVICE_FUNC inline typename internal::cast_return_type<Hyperplane,\n           Hyperplane<NewScalarType,AmbientDimAtCompileTime,Options> >::type cast() const\n  {\n    return typename internal::cast_return_type<Hyperplane,\n                    Hyperplane<NewScalarType,AmbientDimAtCompileTime,Options> >::type(*this);\n  }\n\n  /** Copy constructor with scalar type conversion */\n  template<typename OtherScalarType,int OtherOptions>\n  EIGEN_DEVICE_FUNC inline explicit Hyperplane(const Hyperplane<OtherScalarType,AmbientDimAtCompileTime,OtherOptions>& other)\n  { m_coeffs = other.coeffs().template cast<Scalar>(); }\n\n  /** \\returns \\c true if \\c *this is approximately equal to \\a other, within the precision\n    * determined by \\a prec.\n    *\n    * \\sa MatrixBase::isApprox() */\n  template<int OtherOptions>\n  EIGEN_DEVICE_FUNC bool isApprox(const Hyperplane<Scalar,AmbientDimAtCompileTime,OtherOptions>& other, const typename NumTraits<Scalar>::Real& prec = NumTraits<Scalar>::dummy_precision()) const\n  { return m_coeffs.isApprox(other.m_coeffs, prec); }\n\nprotected:\n\n  Coefficients m_coeffs;\n};\n\n} // end namespace Eigen\n\n#endif // EIGEN_HYPERPLANE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Geometry/OrthoMethods.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2006-2008 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_ORTHOMETHODS_H\n#define EIGEN_ORTHOMETHODS_H\n\nnamespace Eigen { \n\n/** \\geometry_module \\ingroup Geometry_Module\n  *\n  * \\returns the cross product of \\c *this and \\a other\n  *\n  * Here is a very good explanation of cross-product: http://xkcd.com/199/\n  * \n  * With complex numbers, the cross product is implemented as\n  * \\f$ (\\mathbf{a}+i\\mathbf{b}) \\times (\\mathbf{c}+i\\mathbf{d}) = (\\mathbf{a} \\times \\mathbf{c} - \\mathbf{b} \\times \\mathbf{d}) - i(\\mathbf{a} \\times \\mathbf{d} - \\mathbf{b} \\times \\mathbf{c})\\f$\n  * \n  * \\sa MatrixBase::cross3()\n  */\ntemplate<typename Derived>\ntemplate<typename OtherDerived>\n#ifndef EIGEN_PARSED_BY_DOXYGEN\nEIGEN_DEVICE_FUNC inline typename MatrixBase<Derived>::template cross_product_return_type<OtherDerived>::type\n#else\ninline typename MatrixBase<Derived>::PlainObject\n#endif\nMatrixBase<Derived>::cross(const MatrixBase<OtherDerived>& other) const\n{\n  EIGEN_STATIC_ASSERT_VECTOR_SPECIFIC_SIZE(Derived,3)\n  EIGEN_STATIC_ASSERT_VECTOR_SPECIFIC_SIZE(OtherDerived,3)\n\n  // Note that there is no need for an expression here since the compiler\n  // optimize such a small temporary very well (even within a complex expression)\n  typename internal::nested_eval<Derived,2>::type lhs(derived());\n  typename internal::nested_eval<OtherDerived,2>::type rhs(other.derived());\n  return typename cross_product_return_type<OtherDerived>::type(\n    numext::conj(lhs.coeff(1) * rhs.coeff(2) - lhs.coeff(2) * rhs.coeff(1)),\n    numext::conj(lhs.coeff(2) * rhs.coeff(0) - lhs.coeff(0) * rhs.coeff(2)),\n    numext::conj(lhs.coeff(0) * rhs.coeff(1) - lhs.coeff(1) * rhs.coeff(0))\n  );\n}\n\nnamespace internal {\n\ntemplate< int Arch,typename VectorLhs,typename VectorRhs,\n          typename Scalar = typename VectorLhs::Scalar,\n          bool Vectorizable = bool((VectorLhs::Flags&VectorRhs::Flags)&PacketAccessBit)>\nstruct cross3_impl {\n  EIGEN_DEVICE_FUNC static inline typename internal::plain_matrix_type<VectorLhs>::type\n  run(const VectorLhs& lhs, const VectorRhs& rhs)\n  {\n    return typename internal::plain_matrix_type<VectorLhs>::type(\n      numext::conj(lhs.coeff(1) * rhs.coeff(2) - lhs.coeff(2) * rhs.coeff(1)),\n      numext::conj(lhs.coeff(2) * rhs.coeff(0) - lhs.coeff(0) * rhs.coeff(2)),\n      numext::conj(lhs.coeff(0) * rhs.coeff(1) - lhs.coeff(1) * rhs.coeff(0)),\n      0\n    );\n  }\n};\n\n}\n\n/** \\geometry_module \\ingroup Geometry_Module\n  *\n  * \\returns the cross product of \\c *this and \\a other using only the x, y, and z coefficients\n  *\n  * The size of \\c *this and \\a other must be four. This function is especially useful\n  * when using 4D vectors instead of 3D ones to get advantage of SSE/AltiVec vectorization.\n  *\n  * \\sa MatrixBase::cross()\n  */\ntemplate<typename Derived>\ntemplate<typename OtherDerived>\nEIGEN_DEVICE_FUNC inline typename MatrixBase<Derived>::PlainObject\nMatrixBase<Derived>::cross3(const MatrixBase<OtherDerived>& other) const\n{\n  EIGEN_STATIC_ASSERT_VECTOR_SPECIFIC_SIZE(Derived,4)\n  EIGEN_STATIC_ASSERT_VECTOR_SPECIFIC_SIZE(OtherDerived,4)\n\n  typedef typename internal::nested_eval<Derived,2>::type DerivedNested;\n  typedef typename internal::nested_eval<OtherDerived,2>::type OtherDerivedNested;\n  DerivedNested lhs(derived());\n  OtherDerivedNested rhs(other.derived());\n\n  return internal::cross3_impl<Architecture::Target,\n                        typename internal::remove_all<DerivedNested>::type,\n                        typename internal::remove_all<OtherDerivedNested>::type>::run(lhs,rhs);\n}\n\n/** \\geometry_module \\ingroup Geometry_Module\n  *\n  * \\returns a matrix expression of the cross product of each column or row\n  * of the referenced expression with the \\a other vector.\n  *\n  * The referenced matrix must have one dimension equal to 3.\n  * The result matrix has the same dimensions than the referenced one.\n  *\n  * \\sa MatrixBase::cross() */\ntemplate<typename ExpressionType, int Direction>\ntemplate<typename OtherDerived>\nEIGEN_DEVICE_FUNC \nconst typename VectorwiseOp<ExpressionType,Direction>::CrossReturnType\nVectorwiseOp<ExpressionType,Direction>::cross(const MatrixBase<OtherDerived>& other) const\n{\n  EIGEN_STATIC_ASSERT_VECTOR_SPECIFIC_SIZE(OtherDerived,3)\n  EIGEN_STATIC_ASSERT((internal::is_same<Scalar, typename OtherDerived::Scalar>::value),\n    YOU_MIXED_DIFFERENT_NUMERIC_TYPES__YOU_NEED_TO_USE_THE_CAST_METHOD_OF_MATRIXBASE_TO_CAST_NUMERIC_TYPES_EXPLICITLY)\n  \n  typename internal::nested_eval<ExpressionType,2>::type mat(_expression());\n  typename internal::nested_eval<OtherDerived,2>::type vec(other.derived());\n\n  CrossReturnType res(_expression().rows(),_expression().cols());\n  if(Direction==Vertical)\n  {\n    eigen_assert(CrossReturnType::RowsAtCompileTime==3 && \"the matrix must have exactly 3 rows\");\n    res.row(0) = (mat.row(1) * vec.coeff(2) - mat.row(2) * vec.coeff(1)).conjugate();\n    res.row(1) = (mat.row(2) * vec.coeff(0) - mat.row(0) * vec.coeff(2)).conjugate();\n    res.row(2) = (mat.row(0) * vec.coeff(1) - mat.row(1) * vec.coeff(0)).conjugate();\n  }\n  else\n  {\n    eigen_assert(CrossReturnType::ColsAtCompileTime==3 && \"the matrix must have exactly 3 columns\");\n    res.col(0) = (mat.col(1) * vec.coeff(2) - mat.col(2) * vec.coeff(1)).conjugate();\n    res.col(1) = (mat.col(2) * vec.coeff(0) - mat.col(0) * vec.coeff(2)).conjugate();\n    res.col(2) = (mat.col(0) * vec.coeff(1) - mat.col(1) * vec.coeff(0)).conjugate();\n  }\n  return res;\n}\n\nnamespace internal {\n\ntemplate<typename Derived, int Size = Derived::SizeAtCompileTime>\nstruct unitOrthogonal_selector\n{\n  typedef typename plain_matrix_type<Derived>::type VectorType;\n  typedef typename traits<Derived>::Scalar Scalar;\n  typedef typename NumTraits<Scalar>::Real RealScalar;\n  typedef Matrix<Scalar,2,1> Vector2;\n  EIGEN_DEVICE_FUNC\n  static inline VectorType run(const Derived& src)\n  {\n    VectorType perp = VectorType::Zero(src.size());\n    Index maxi = 0;\n    Index sndi = 0;\n    src.cwiseAbs().maxCoeff(&maxi);\n    if (maxi==0)\n      sndi = 1;\n    RealScalar invnm = RealScalar(1)/(Vector2() << src.coeff(sndi),src.coeff(maxi)).finished().norm();\n    perp.coeffRef(maxi) = -numext::conj(src.coeff(sndi)) * invnm;\n    perp.coeffRef(sndi) =  numext::conj(src.coeff(maxi)) * invnm;\n\n    return perp;\n   }\n};\n\ntemplate<typename Derived>\nstruct unitOrthogonal_selector<Derived,3>\n{\n  typedef typename plain_matrix_type<Derived>::type VectorType;\n  typedef typename traits<Derived>::Scalar Scalar;\n  typedef typename NumTraits<Scalar>::Real RealScalar;\n  EIGEN_DEVICE_FUNC\n  static inline VectorType run(const Derived& src)\n  {\n    VectorType perp;\n    /* Let us compute the crossed product of *this with a vector\n     * that is not too close to being colinear to *this.\n     */\n\n    /* unless the x and y coords are both close to zero, we can\n     * simply take ( -y, x, 0 ) and normalize it.\n     */\n    if((!isMuchSmallerThan(src.x(), src.z()))\n    || (!isMuchSmallerThan(src.y(), src.z())))\n    {\n      RealScalar invnm = RealScalar(1)/src.template head<2>().norm();\n      perp.coeffRef(0) = -numext::conj(src.y())*invnm;\n      perp.coeffRef(1) = numext::conj(src.x())*invnm;\n      perp.coeffRef(2) = 0;\n    }\n    /* if both x and y are close to zero, then the vector is close\n     * to the z-axis, so it's far from colinear to the x-axis for instance.\n     * So we take the crossed product with (1,0,0) and normalize it.\n     */\n    else\n    {\n      RealScalar invnm = RealScalar(1)/src.template tail<2>().norm();\n      perp.coeffRef(0) = 0;\n      perp.coeffRef(1) = -numext::conj(src.z())*invnm;\n      perp.coeffRef(2) = numext::conj(src.y())*invnm;\n    }\n\n    return perp;\n   }\n};\n\ntemplate<typename Derived>\nstruct unitOrthogonal_selector<Derived,2>\n{\n  typedef typename plain_matrix_type<Derived>::type VectorType;\n  EIGEN_DEVICE_FUNC\n  static inline VectorType run(const Derived& src)\n  { return VectorType(-numext::conj(src.y()), numext::conj(src.x())).normalized(); }\n};\n\n} // end namespace internal\n\n/** \\geometry_module \\ingroup Geometry_Module\n  *\n  * \\returns a unit vector which is orthogonal to \\c *this\n  *\n  * The size of \\c *this must be at least 2. If the size is exactly 2,\n  * then the returned vector is a counter clock wise rotation of \\c *this, i.e., (-y,x).normalized().\n  *\n  * \\sa cross()\n  */\ntemplate<typename Derived>\nEIGEN_DEVICE_FUNC typename MatrixBase<Derived>::PlainObject\nMatrixBase<Derived>::unitOrthogonal() const\n{\n  EIGEN_STATIC_ASSERT_VECTOR_ONLY(Derived)\n  return internal::unitOrthogonal_selector<Derived>::run(derived());\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_ORTHOMETHODS_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Geometry/ParametrizedLine.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2008 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_PARAMETRIZEDLINE_H\n#define EIGEN_PARAMETRIZEDLINE_H\n\nnamespace Eigen { \n\n/** \\geometry_module \\ingroup Geometry_Module\n  *\n  * \\class ParametrizedLine\n  *\n  * \\brief A parametrized line\n  *\n  * A parametrized line is defined by an origin point \\f$ \\mathbf{o} \\f$ and a unit\n  * direction vector \\f$ \\mathbf{d} \\f$ such that the line corresponds to\n  * the set \\f$ l(t) = \\mathbf{o} + t \\mathbf{d} \\f$, \\f$ t \\in \\mathbf{R} \\f$.\n  *\n  * \\tparam _Scalar the scalar type, i.e., the type of the coefficients\n  * \\tparam _AmbientDim the dimension of the ambient space, can be a compile time value or Dynamic.\n  */\ntemplate <typename _Scalar, int _AmbientDim, int _Options>\nclass ParametrizedLine\n{\npublic:\n  EIGEN_MAKE_ALIGNED_OPERATOR_NEW_IF_VECTORIZABLE_FIXED_SIZE(_Scalar,_AmbientDim)\n  enum {\n    AmbientDimAtCompileTime = _AmbientDim,\n    Options = _Options\n  };\n  typedef _Scalar Scalar;\n  typedef typename NumTraits<Scalar>::Real RealScalar;\n  typedef Eigen::Index Index; ///< \\deprecated since Eigen 3.3\n  typedef Matrix<Scalar,AmbientDimAtCompileTime,1,Options> VectorType;\n\n  /** Default constructor without initialization */\n  EIGEN_DEVICE_FUNC inline ParametrizedLine() {}\n  \n  template<int OtherOptions>\n  EIGEN_DEVICE_FUNC ParametrizedLine(const ParametrizedLine<Scalar,AmbientDimAtCompileTime,OtherOptions>& other)\n   : m_origin(other.origin()), m_direction(other.direction())\n  {}\n\n  /** Constructs a dynamic-size line with \\a _dim the dimension\n    * of the ambient space */\n  EIGEN_DEVICE_FUNC inline explicit ParametrizedLine(Index _dim) : m_origin(_dim), m_direction(_dim) {}\n\n  /** Initializes a parametrized line of direction \\a direction and origin \\a origin.\n    * \\warning the vector direction is assumed to be normalized.\n    */\n  EIGEN_DEVICE_FUNC ParametrizedLine(const VectorType& origin, const VectorType& direction)\n    : m_origin(origin), m_direction(direction) {}\n\n  template <int OtherOptions>\n  EIGEN_DEVICE_FUNC explicit ParametrizedLine(const Hyperplane<_Scalar, _AmbientDim, OtherOptions>& hyperplane);\n\n  /** Constructs a parametrized line going from \\a p0 to \\a p1. */\n  EIGEN_DEVICE_FUNC static inline ParametrizedLine Through(const VectorType& p0, const VectorType& p1)\n  { return ParametrizedLine(p0, (p1-p0).normalized()); }\n\n  EIGEN_DEVICE_FUNC ~ParametrizedLine() {}\n\n  /** \\returns the dimension in which the line holds */\n  EIGEN_DEVICE_FUNC inline Index dim() const { return m_direction.size(); }\n\n  EIGEN_DEVICE_FUNC const VectorType& origin() const { return m_origin; }\n  EIGEN_DEVICE_FUNC VectorType& origin() { return m_origin; }\n\n  EIGEN_DEVICE_FUNC const VectorType& direction() const { return m_direction; }\n  EIGEN_DEVICE_FUNC VectorType& direction() { return m_direction; }\n\n  /** \\returns the squared distance of a point \\a p to its projection onto the line \\c *this.\n    * \\sa distance()\n    */\n  EIGEN_DEVICE_FUNC RealScalar squaredDistance(const VectorType& p) const\n  {\n    VectorType diff = p - origin();\n    return (diff - direction().dot(diff) * direction()).squaredNorm();\n  }\n  /** \\returns the distance of a point \\a p to its projection onto the line \\c *this.\n    * \\sa squaredDistance()\n    */\n  EIGEN_DEVICE_FUNC RealScalar distance(const VectorType& p) const { EIGEN_USING_STD_MATH(sqrt) return sqrt(squaredDistance(p)); }\n\n  /** \\returns the projection of a point \\a p onto the line \\c *this. */\n  EIGEN_DEVICE_FUNC VectorType projection(const VectorType& p) const\n  { return origin() + direction().dot(p-origin()) * direction(); }\n\n  EIGEN_DEVICE_FUNC VectorType pointAt(const Scalar& t) const;\n  \n  template <int OtherOptions>\n  EIGEN_DEVICE_FUNC Scalar intersectionParameter(const Hyperplane<_Scalar, _AmbientDim, OtherOptions>& hyperplane) const;\n \n  template <int OtherOptions>\n  EIGEN_DEVICE_FUNC Scalar intersection(const Hyperplane<_Scalar, _AmbientDim, OtherOptions>& hyperplane) const;\n  \n  template <int OtherOptions>\n  EIGEN_DEVICE_FUNC VectorType intersectionPoint(const Hyperplane<_Scalar, _AmbientDim, OtherOptions>& hyperplane) const;\n\n  /** \\returns \\c *this with scalar type casted to \\a NewScalarType\n    *\n    * Note that if \\a NewScalarType is equal to the current scalar type of \\c *this\n    * then this function smartly returns a const reference to \\c *this.\n    */\n  template<typename NewScalarType>\n  EIGEN_DEVICE_FUNC inline typename internal::cast_return_type<ParametrizedLine,\n           ParametrizedLine<NewScalarType,AmbientDimAtCompileTime,Options> >::type cast() const\n  {\n    return typename internal::cast_return_type<ParametrizedLine,\n                    ParametrizedLine<NewScalarType,AmbientDimAtCompileTime,Options> >::type(*this);\n  }\n\n  /** Copy constructor with scalar type conversion */\n  template<typename OtherScalarType,int OtherOptions>\n  EIGEN_DEVICE_FUNC inline explicit ParametrizedLine(const ParametrizedLine<OtherScalarType,AmbientDimAtCompileTime,OtherOptions>& other)\n  {\n    m_origin = other.origin().template cast<Scalar>();\n    m_direction = other.direction().template cast<Scalar>();\n  }\n\n  /** \\returns \\c true if \\c *this is approximately equal to \\a other, within the precision\n    * determined by \\a prec.\n    *\n    * \\sa MatrixBase::isApprox() */\n  EIGEN_DEVICE_FUNC bool isApprox(const ParametrizedLine& other, const typename NumTraits<Scalar>::Real& prec = NumTraits<Scalar>::dummy_precision()) const\n  { return m_origin.isApprox(other.m_origin, prec) && m_direction.isApprox(other.m_direction, prec); }\n\nprotected:\n\n  VectorType m_origin, m_direction;\n};\n\n/** Constructs a parametrized line from a 2D hyperplane\n  *\n  * \\warning the ambient space must have dimension 2 such that the hyperplane actually describes a line\n  */\ntemplate <typename _Scalar, int _AmbientDim, int _Options>\ntemplate <int OtherOptions>\nEIGEN_DEVICE_FUNC inline ParametrizedLine<_Scalar, _AmbientDim,_Options>::ParametrizedLine(const Hyperplane<_Scalar, _AmbientDim,OtherOptions>& hyperplane)\n{\n  EIGEN_STATIC_ASSERT_VECTOR_SPECIFIC_SIZE(VectorType, 2)\n  direction() = hyperplane.normal().unitOrthogonal();\n  origin() = -hyperplane.normal()*hyperplane.offset();\n}\n\n/** \\returns the point at \\a t along this line\n  */\ntemplate <typename _Scalar, int _AmbientDim, int _Options>\nEIGEN_DEVICE_FUNC inline typename ParametrizedLine<_Scalar, _AmbientDim,_Options>::VectorType\nParametrizedLine<_Scalar, _AmbientDim,_Options>::pointAt(const _Scalar& t) const\n{\n  return origin() + (direction()*t); \n}\n\n/** \\returns the parameter value of the intersection between \\c *this and the given \\a hyperplane\n  */\ntemplate <typename _Scalar, int _AmbientDim, int _Options>\ntemplate <int OtherOptions>\nEIGEN_DEVICE_FUNC inline _Scalar ParametrizedLine<_Scalar, _AmbientDim,_Options>::intersectionParameter(const Hyperplane<_Scalar, _AmbientDim, OtherOptions>& hyperplane) const\n{\n  return -(hyperplane.offset()+hyperplane.normal().dot(origin()))\n          / hyperplane.normal().dot(direction());\n}\n\n\n/** \\deprecated use intersectionParameter()\n  * \\returns the parameter value of the intersection between \\c *this and the given \\a hyperplane\n  */\ntemplate <typename _Scalar, int _AmbientDim, int _Options>\ntemplate <int OtherOptions>\nEIGEN_DEVICE_FUNC inline _Scalar ParametrizedLine<_Scalar, _AmbientDim,_Options>::intersection(const Hyperplane<_Scalar, _AmbientDim, OtherOptions>& hyperplane) const\n{\n  return intersectionParameter(hyperplane);\n}\n\n/** \\returns the point of the intersection between \\c *this and the given hyperplane\n  */\ntemplate <typename _Scalar, int _AmbientDim, int _Options>\ntemplate <int OtherOptions>\nEIGEN_DEVICE_FUNC inline typename ParametrizedLine<_Scalar, _AmbientDim,_Options>::VectorType\nParametrizedLine<_Scalar, _AmbientDim,_Options>::intersectionPoint(const Hyperplane<_Scalar, _AmbientDim, OtherOptions>& hyperplane) const\n{\n  return pointAt(intersectionParameter(hyperplane));\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_PARAMETRIZEDLINE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Geometry/Quaternion.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2009 Mathieu Gautier <mathieu.gautier@cea.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_QUATERNION_H\n#define EIGEN_QUATERNION_H\nnamespace Eigen { \n\n\n/***************************************************************************\n* Definition of QuaternionBase<Derived>\n* The implementation is at the end of the file\n***************************************************************************/\n\nnamespace internal {\ntemplate<typename Other,\n         int OtherRows=Other::RowsAtCompileTime,\n         int OtherCols=Other::ColsAtCompileTime>\nstruct quaternionbase_assign_impl;\n}\n\n/** \\geometry_module \\ingroup Geometry_Module\n  * \\class QuaternionBase\n  * \\brief Base class for quaternion expressions\n  * \\tparam Derived derived type (CRTP)\n  * \\sa class Quaternion\n  */\ntemplate<class Derived>\nclass QuaternionBase : public RotationBase<Derived, 3>\n{\n public:\n  typedef RotationBase<Derived, 3> Base;\n\n  using Base::operator*;\n  using Base::derived;\n\n  typedef typename internal::traits<Derived>::Scalar Scalar;\n  typedef typename NumTraits<Scalar>::Real RealScalar;\n  typedef typename internal::traits<Derived>::Coefficients Coefficients;\n  enum {\n    Flags = Eigen::internal::traits<Derived>::Flags\n  };\n\n // typedef typename Matrix<Scalar,4,1> Coefficients;\n  /** the type of a 3D vector */\n  typedef Matrix<Scalar,3,1> Vector3;\n  /** the equivalent rotation matrix type */\n  typedef Matrix<Scalar,3,3> Matrix3;\n  /** the equivalent angle-axis type */\n  typedef AngleAxis<Scalar> AngleAxisType;\n\n\n\n  /** \\returns the \\c x coefficient */\n  EIGEN_DEVICE_FUNC inline Scalar x() const { return this->derived().coeffs().coeff(0); }\n  /** \\returns the \\c y coefficient */\n  EIGEN_DEVICE_FUNC inline Scalar y() const { return this->derived().coeffs().coeff(1); }\n  /** \\returns the \\c z coefficient */\n  EIGEN_DEVICE_FUNC inline Scalar z() const { return this->derived().coeffs().coeff(2); }\n  /** \\returns the \\c w coefficient */\n  EIGEN_DEVICE_FUNC inline Scalar w() const { return this->derived().coeffs().coeff(3); }\n\n  /** \\returns a reference to the \\c x coefficient */\n  EIGEN_DEVICE_FUNC inline Scalar& x() { return this->derived().coeffs().coeffRef(0); }\n  /** \\returns a reference to the \\c y coefficient */\n  EIGEN_DEVICE_FUNC inline Scalar& y() { return this->derived().coeffs().coeffRef(1); }\n  /** \\returns a reference to the \\c z coefficient */\n  EIGEN_DEVICE_FUNC inline Scalar& z() { return this->derived().coeffs().coeffRef(2); }\n  /** \\returns a reference to the \\c w coefficient */\n  EIGEN_DEVICE_FUNC inline Scalar& w() { return this->derived().coeffs().coeffRef(3); }\n\n  /** \\returns a read-only vector expression of the imaginary part (x,y,z) */\n  EIGEN_DEVICE_FUNC inline const VectorBlock<const Coefficients,3> vec() const { return coeffs().template head<3>(); }\n\n  /** \\returns a vector expression of the imaginary part (x,y,z) */\n  EIGEN_DEVICE_FUNC inline VectorBlock<Coefficients,3> vec() { return coeffs().template head<3>(); }\n\n  /** \\returns a read-only vector expression of the coefficients (x,y,z,w) */\n  EIGEN_DEVICE_FUNC inline const typename internal::traits<Derived>::Coefficients& coeffs() const { return derived().coeffs(); }\n\n  /** \\returns a vector expression of the coefficients (x,y,z,w) */\n  EIGEN_DEVICE_FUNC inline typename internal::traits<Derived>::Coefficients& coeffs() { return derived().coeffs(); }\n\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE QuaternionBase<Derived>& operator=(const QuaternionBase<Derived>& other);\n  template<class OtherDerived> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE Derived& operator=(const QuaternionBase<OtherDerived>& other);\n\n// disabled this copy operator as it is giving very strange compilation errors when compiling\n// test_stdvector with GCC 4.4.2. This looks like a GCC bug though, so feel free to re-enable it if it's\n// useful; however notice that we already have the templated operator= above and e.g. in MatrixBase\n// we didn't have to add, in addition to templated operator=, such a non-templated copy operator.\n//  Derived& operator=(const QuaternionBase& other)\n//  { return operator=<Derived>(other); }\n\n  EIGEN_DEVICE_FUNC Derived& operator=(const AngleAxisType& aa);\n  template<class OtherDerived> EIGEN_DEVICE_FUNC Derived& operator=(const MatrixBase<OtherDerived>& m);\n\n  /** \\returns a quaternion representing an identity rotation\n    * \\sa MatrixBase::Identity()\n    */\n  EIGEN_DEVICE_FUNC static inline Quaternion<Scalar> Identity() { return Quaternion<Scalar>(Scalar(1), Scalar(0), Scalar(0), Scalar(0)); }\n\n  /** \\sa QuaternionBase::Identity(), MatrixBase::setIdentity()\n    */\n  EIGEN_DEVICE_FUNC inline QuaternionBase& setIdentity() { coeffs() << Scalar(0), Scalar(0), Scalar(0), Scalar(1); return *this; }\n\n  /** \\returns the squared norm of the quaternion's coefficients\n    * \\sa QuaternionBase::norm(), MatrixBase::squaredNorm()\n    */\n  EIGEN_DEVICE_FUNC inline Scalar squaredNorm() const { return coeffs().squaredNorm(); }\n\n  /** \\returns the norm of the quaternion's coefficients\n    * \\sa QuaternionBase::squaredNorm(), MatrixBase::norm()\n    */\n  EIGEN_DEVICE_FUNC inline Scalar norm() const { return coeffs().norm(); }\n\n  /** Normalizes the quaternion \\c *this\n    * \\sa normalized(), MatrixBase::normalize() */\n  EIGEN_DEVICE_FUNC inline void normalize() { coeffs().normalize(); }\n  /** \\returns a normalized copy of \\c *this\n    * \\sa normalize(), MatrixBase::normalized() */\n  EIGEN_DEVICE_FUNC inline Quaternion<Scalar> normalized() const { return Quaternion<Scalar>(coeffs().normalized()); }\n\n    /** \\returns the dot product of \\c *this and \\a other\n    * Geometrically speaking, the dot product of two unit quaternions\n    * corresponds to the cosine of half the angle between the two rotations.\n    * \\sa angularDistance()\n    */\n  template<class OtherDerived> EIGEN_DEVICE_FUNC inline Scalar dot(const QuaternionBase<OtherDerived>& other) const { return coeffs().dot(other.coeffs()); }\n\n  template<class OtherDerived> EIGEN_DEVICE_FUNC Scalar angularDistance(const QuaternionBase<OtherDerived>& other) const;\n\n  /** \\returns an equivalent 3x3 rotation matrix */\n  EIGEN_DEVICE_FUNC Matrix3 toRotationMatrix() const;\n\n  /** \\returns the quaternion which transform \\a a into \\a b through a rotation */\n  template<typename Derived1, typename Derived2>\n  EIGEN_DEVICE_FUNC Derived& setFromTwoVectors(const MatrixBase<Derived1>& a, const MatrixBase<Derived2>& b);\n\n  template<class OtherDerived> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE Quaternion<Scalar> operator* (const QuaternionBase<OtherDerived>& q) const;\n  template<class OtherDerived> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE Derived& operator*= (const QuaternionBase<OtherDerived>& q);\n\n  /** \\returns the quaternion describing the inverse rotation */\n  EIGEN_DEVICE_FUNC Quaternion<Scalar> inverse() const;\n\n  /** \\returns the conjugated quaternion */\n  EIGEN_DEVICE_FUNC Quaternion<Scalar> conjugate() const;\n\n  template<class OtherDerived> EIGEN_DEVICE_FUNC Quaternion<Scalar> slerp(const Scalar& t, const QuaternionBase<OtherDerived>& other) const;\n\n  /** \\returns \\c true if \\c *this is approximately equal to \\a other, within the precision\n    * determined by \\a prec.\n    *\n    * \\sa MatrixBase::isApprox() */\n  template<class OtherDerived>\n  EIGEN_DEVICE_FUNC bool isApprox(const QuaternionBase<OtherDerived>& other, const RealScalar& prec = NumTraits<Scalar>::dummy_precision()) const\n  { return coeffs().isApprox(other.coeffs(), prec); }\n\n  /** return the result vector of \\a v through the rotation*/\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE Vector3 _transformVector(const Vector3& v) const;\n\n  /** \\returns \\c *this with scalar type casted to \\a NewScalarType\n    *\n    * Note that if \\a NewScalarType is equal to the current scalar type of \\c *this\n    * then this function smartly returns a const reference to \\c *this.\n    */\n  template<typename NewScalarType>\n  EIGEN_DEVICE_FUNC inline typename internal::cast_return_type<Derived,Quaternion<NewScalarType> >::type cast() const\n  {\n    return typename internal::cast_return_type<Derived,Quaternion<NewScalarType> >::type(derived());\n  }\n\n#ifdef EIGEN_QUATERNIONBASE_PLUGIN\n# include EIGEN_QUATERNIONBASE_PLUGIN\n#endif\n};\n\n/***************************************************************************\n* Definition/implementation of Quaternion<Scalar>\n***************************************************************************/\n\n/** \\geometry_module \\ingroup Geometry_Module\n  *\n  * \\class Quaternion\n  *\n  * \\brief The quaternion class used to represent 3D orientations and rotations\n  *\n  * \\tparam _Scalar the scalar type, i.e., the type of the coefficients\n  * \\tparam _Options controls the memory alignment of the coefficients. Can be \\# AutoAlign or \\# DontAlign. Default is AutoAlign.\n  *\n  * This class represents a quaternion \\f$ w+xi+yj+zk \\f$ that is a convenient representation of\n  * orientations and rotations of objects in three dimensions. Compared to other representations\n  * like Euler angles or 3x3 matrices, quaternions offer the following advantages:\n  * \\li \\b compact storage (4 scalars)\n  * \\li \\b efficient to compose (28 flops),\n  * \\li \\b stable spherical interpolation\n  *\n  * The following two typedefs are provided for convenience:\n  * \\li \\c Quaternionf for \\c float\n  * \\li \\c Quaterniond for \\c double\n  *\n  * \\warning Operations interpreting the quaternion as rotation have undefined behavior if the quaternion is not normalized.\n  *\n  * \\sa  class AngleAxis, class Transform\n  */\n\nnamespace internal {\ntemplate<typename _Scalar,int _Options>\nstruct traits<Quaternion<_Scalar,_Options> >\n{\n  typedef Quaternion<_Scalar,_Options> PlainObject;\n  typedef _Scalar Scalar;\n  typedef Matrix<_Scalar,4,1,_Options> Coefficients;\n  enum{\n    Alignment = internal::traits<Coefficients>::Alignment,\n    Flags = LvalueBit\n  };\n};\n}\n\ntemplate<typename _Scalar, int _Options>\nclass Quaternion : public QuaternionBase<Quaternion<_Scalar,_Options> >\n{\npublic:\n  typedef QuaternionBase<Quaternion<_Scalar,_Options> > Base;\n  enum { NeedsAlignment = internal::traits<Quaternion>::Alignment>0 };\n\n  typedef _Scalar Scalar;\n\n  EIGEN_INHERIT_ASSIGNMENT_OPERATORS(Quaternion)\n  using Base::operator*=;\n\n  typedef typename internal::traits<Quaternion>::Coefficients Coefficients;\n  typedef typename Base::AngleAxisType AngleAxisType;\n\n  /** Default constructor leaving the quaternion uninitialized. */\n  EIGEN_DEVICE_FUNC inline Quaternion() {}\n\n  /** Constructs and initializes the quaternion \\f$ w+xi+yj+zk \\f$ from\n    * its four coefficients \\a w, \\a x, \\a y and \\a z.\n    *\n    * \\warning Note the order of the arguments: the real \\a w coefficient first,\n    * while internally the coefficients are stored in the following order:\n    * [\\c x, \\c y, \\c z, \\c w]\n    */\n  EIGEN_DEVICE_FUNC inline Quaternion(const Scalar& w, const Scalar& x, const Scalar& y, const Scalar& z) : m_coeffs(x, y, z, w){}\n\n  /** Constructs and initialize a quaternion from the array data */\n  EIGEN_DEVICE_FUNC explicit inline Quaternion(const Scalar* data) : m_coeffs(data) {}\n\n  /** Copy constructor */\n  template<class Derived> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE Quaternion(const QuaternionBase<Derived>& other) { this->Base::operator=(other); }\n\n  /** Constructs and initializes a quaternion from the angle-axis \\a aa */\n  EIGEN_DEVICE_FUNC explicit inline Quaternion(const AngleAxisType& aa) { *this = aa; }\n\n  /** Constructs and initializes a quaternion from either:\n    *  - a rotation matrix expression,\n    *  - a 4D vector expression representing quaternion coefficients.\n    */\n  template<typename Derived>\n  EIGEN_DEVICE_FUNC explicit inline Quaternion(const MatrixBase<Derived>& other) { *this = other; }\n\n  /** Explicit copy constructor with scalar conversion */\n  template<typename OtherScalar, int OtherOptions>\n  EIGEN_DEVICE_FUNC explicit inline Quaternion(const Quaternion<OtherScalar, OtherOptions>& other)\n  { m_coeffs = other.coeffs().template cast<Scalar>(); }\n\n  EIGEN_DEVICE_FUNC static Quaternion UnitRandom();\n\n  template<typename Derived1, typename Derived2>\n  EIGEN_DEVICE_FUNC static Quaternion FromTwoVectors(const MatrixBase<Derived1>& a, const MatrixBase<Derived2>& b);\n\n  EIGEN_DEVICE_FUNC inline Coefficients& coeffs() { return m_coeffs;}\n  EIGEN_DEVICE_FUNC inline const Coefficients& coeffs() const { return m_coeffs;}\n\n  EIGEN_MAKE_ALIGNED_OPERATOR_NEW_IF(bool(NeedsAlignment))\n  \n#ifdef EIGEN_QUATERNION_PLUGIN\n# include EIGEN_QUATERNION_PLUGIN\n#endif\n\nprotected:\n  Coefficients m_coeffs;\n  \n#ifndef EIGEN_PARSED_BY_DOXYGEN\n    static EIGEN_STRONG_INLINE void _check_template_params()\n    {\n      EIGEN_STATIC_ASSERT( (_Options & DontAlign) == _Options,\n        INVALID_MATRIX_TEMPLATE_PARAMETERS)\n    }\n#endif\n};\n\n/** \\ingroup Geometry_Module\n  * single precision quaternion type */\ntypedef Quaternion<float> Quaternionf;\n/** \\ingroup Geometry_Module\n  * double precision quaternion type */\ntypedef Quaternion<double> Quaterniond;\n\n/***************************************************************************\n* Specialization of Map<Quaternion<Scalar>>\n***************************************************************************/\n\nnamespace internal {\n  template<typename _Scalar, int _Options>\n  struct traits<Map<Quaternion<_Scalar>, _Options> > : traits<Quaternion<_Scalar, (int(_Options)&Aligned)==Aligned ? AutoAlign : DontAlign> >\n  {\n    typedef Map<Matrix<_Scalar,4,1>, _Options> Coefficients;\n  };\n}\n\nnamespace internal {\n  template<typename _Scalar, int _Options>\n  struct traits<Map<const Quaternion<_Scalar>, _Options> > : traits<Quaternion<_Scalar, (int(_Options)&Aligned)==Aligned ? AutoAlign : DontAlign> >\n  {\n    typedef Map<const Matrix<_Scalar,4,1>, _Options> Coefficients;\n    typedef traits<Quaternion<_Scalar, (int(_Options)&Aligned)==Aligned ? AutoAlign : DontAlign> > TraitsBase;\n    enum {\n      Flags = TraitsBase::Flags & ~LvalueBit\n    };\n  };\n}\n\n/** \\ingroup Geometry_Module\n  * \\brief Quaternion expression mapping a constant memory buffer\n  *\n  * \\tparam _Scalar the type of the Quaternion coefficients\n  * \\tparam _Options see class Map\n  *\n  * This is a specialization of class Map for Quaternion. This class allows to view\n  * a 4 scalar memory buffer as an Eigen's Quaternion object.\n  *\n  * \\sa class Map, class Quaternion, class QuaternionBase\n  */\ntemplate<typename _Scalar, int _Options>\nclass Map<const Quaternion<_Scalar>, _Options >\n  : public QuaternionBase<Map<const Quaternion<_Scalar>, _Options> >\n{\n  public:\n    typedef QuaternionBase<Map<const Quaternion<_Scalar>, _Options> > Base;\n\n    typedef _Scalar Scalar;\n    typedef typename internal::traits<Map>::Coefficients Coefficients;\n    EIGEN_INHERIT_ASSIGNMENT_OPERATORS(Map)\n    using Base::operator*=;\n\n    /** Constructs a Mapped Quaternion object from the pointer \\a coeffs\n      *\n      * The pointer \\a coeffs must reference the four coefficients of Quaternion in the following order:\n      * \\code *coeffs == {x, y, z, w} \\endcode\n      *\n      * If the template parameter _Options is set to #Aligned, then the pointer coeffs must be aligned. */\n    EIGEN_DEVICE_FUNC explicit EIGEN_STRONG_INLINE Map(const Scalar* coeffs) : m_coeffs(coeffs) {}\n\n    EIGEN_DEVICE_FUNC inline const Coefficients& coeffs() const { return m_coeffs;}\n\n  protected:\n    const Coefficients m_coeffs;\n};\n\n/** \\ingroup Geometry_Module\n  * \\brief Expression of a quaternion from a memory buffer\n  *\n  * \\tparam _Scalar the type of the Quaternion coefficients\n  * \\tparam _Options see class Map\n  *\n  * This is a specialization of class Map for Quaternion. This class allows to view\n  * a 4 scalar memory buffer as an Eigen's  Quaternion object.\n  *\n  * \\sa class Map, class Quaternion, class QuaternionBase\n  */\ntemplate<typename _Scalar, int _Options>\nclass Map<Quaternion<_Scalar>, _Options >\n  : public QuaternionBase<Map<Quaternion<_Scalar>, _Options> >\n{\n  public:\n    typedef QuaternionBase<Map<Quaternion<_Scalar>, _Options> > Base;\n\n    typedef _Scalar Scalar;\n    typedef typename internal::traits<Map>::Coefficients Coefficients;\n    EIGEN_INHERIT_ASSIGNMENT_OPERATORS(Map)\n    using Base::operator*=;\n\n    /** Constructs a Mapped Quaternion object from the pointer \\a coeffs\n      *\n      * The pointer \\a coeffs must reference the four coefficients of Quaternion in the following order:\n      * \\code *coeffs == {x, y, z, w} \\endcode\n      *\n      * If the template parameter _Options is set to #Aligned, then the pointer coeffs must be aligned. */\n    EIGEN_DEVICE_FUNC explicit EIGEN_STRONG_INLINE Map(Scalar* coeffs) : m_coeffs(coeffs) {}\n\n    EIGEN_DEVICE_FUNC inline Coefficients& coeffs() { return m_coeffs; }\n    EIGEN_DEVICE_FUNC inline const Coefficients& coeffs() const { return m_coeffs; }\n\n  protected:\n    Coefficients m_coeffs;\n};\n\n/** \\ingroup Geometry_Module\n  * Map an unaligned array of single precision scalars as a quaternion */\ntypedef Map<Quaternion<float>, 0>         QuaternionMapf;\n/** \\ingroup Geometry_Module\n  * Map an unaligned array of double precision scalars as a quaternion */\ntypedef Map<Quaternion<double>, 0>        QuaternionMapd;\n/** \\ingroup Geometry_Module\n  * Map a 16-byte aligned array of single precision scalars as a quaternion */\ntypedef Map<Quaternion<float>, Aligned>   QuaternionMapAlignedf;\n/** \\ingroup Geometry_Module\n  * Map a 16-byte aligned array of double precision scalars as a quaternion */\ntypedef Map<Quaternion<double>, Aligned>  QuaternionMapAlignedd;\n\n/***************************************************************************\n* Implementation of QuaternionBase methods\n***************************************************************************/\n\n// Generic Quaternion * Quaternion product\n// This product can be specialized for a given architecture via the Arch template argument.\nnamespace internal {\ntemplate<int Arch, class Derived1, class Derived2, typename Scalar, int _Options> struct quat_product\n{\n  EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE Quaternion<Scalar> run(const QuaternionBase<Derived1>& a, const QuaternionBase<Derived2>& b){\n    return Quaternion<Scalar>\n    (\n      a.w() * b.w() - a.x() * b.x() - a.y() * b.y() - a.z() * b.z(),\n      a.w() * b.x() + a.x() * b.w() + a.y() * b.z() - a.z() * b.y(),\n      a.w() * b.y() + a.y() * b.w() + a.z() * b.x() - a.x() * b.z(),\n      a.w() * b.z() + a.z() * b.w() + a.x() * b.y() - a.y() * b.x()\n    );\n  }\n};\n}\n\n/** \\returns the concatenation of two rotations as a quaternion-quaternion product */\ntemplate <class Derived>\ntemplate <class OtherDerived>\nEIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE Quaternion<typename internal::traits<Derived>::Scalar>\nQuaternionBase<Derived>::operator* (const QuaternionBase<OtherDerived>& other) const\n{\n  EIGEN_STATIC_ASSERT((internal::is_same<typename Derived::Scalar, typename OtherDerived::Scalar>::value),\n   YOU_MIXED_DIFFERENT_NUMERIC_TYPES__YOU_NEED_TO_USE_THE_CAST_METHOD_OF_MATRIXBASE_TO_CAST_NUMERIC_TYPES_EXPLICITLY)\n  return internal::quat_product<Architecture::Target, Derived, OtherDerived,\n                         typename internal::traits<Derived>::Scalar,\n                         EIGEN_PLAIN_ENUM_MIN(internal::traits<Derived>::Alignment, internal::traits<OtherDerived>::Alignment)>::run(*this, other);\n}\n\n/** \\sa operator*(Quaternion) */\ntemplate <class Derived>\ntemplate <class OtherDerived>\nEIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE Derived& QuaternionBase<Derived>::operator*= (const QuaternionBase<OtherDerived>& other)\n{\n  derived() = derived() * other.derived();\n  return derived();\n}\n\n/** Rotation of a vector by a quaternion.\n  * \\remarks If the quaternion is used to rotate several points (>1)\n  * then it is much more efficient to first convert it to a 3x3 Matrix.\n  * Comparison of the operation cost for n transformations:\n  *   - Quaternion2:    30n\n  *   - Via a Matrix3: 24 + 15n\n  */\ntemplate <class Derived>\nEIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE typename QuaternionBase<Derived>::Vector3\nQuaternionBase<Derived>::_transformVector(const Vector3& v) const\n{\n    // Note that this algorithm comes from the optimization by hand\n    // of the conversion to a Matrix followed by a Matrix/Vector product.\n    // It appears to be much faster than the common algorithm found\n    // in the literature (30 versus 39 flops). It also requires two\n    // Vector3 as temporaries.\n    Vector3 uv = this->vec().cross(v);\n    uv += uv;\n    return v + this->w() * uv + this->vec().cross(uv);\n}\n\ntemplate<class Derived>\nEIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE QuaternionBase<Derived>& QuaternionBase<Derived>::operator=(const QuaternionBase<Derived>& other)\n{\n  coeffs() = other.coeffs();\n  return derived();\n}\n\ntemplate<class Derived>\ntemplate<class OtherDerived>\nEIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE Derived& QuaternionBase<Derived>::operator=(const QuaternionBase<OtherDerived>& other)\n{\n  coeffs() = other.coeffs();\n  return derived();\n}\n\n/** Set \\c *this from an angle-axis \\a aa and returns a reference to \\c *this\n  */\ntemplate<class Derived>\nEIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE Derived& QuaternionBase<Derived>::operator=(const AngleAxisType& aa)\n{\n  EIGEN_USING_STD_MATH(cos)\n  EIGEN_USING_STD_MATH(sin)\n  Scalar ha = Scalar(0.5)*aa.angle(); // Scalar(0.5) to suppress precision loss warnings\n  this->w() = cos(ha);\n  this->vec() = sin(ha) * aa.axis();\n  return derived();\n}\n\n/** Set \\c *this from the expression \\a xpr:\n  *   - if \\a xpr is a 4x1 vector, then \\a xpr is assumed to be a quaternion\n  *   - if \\a xpr is a 3x3 matrix, then \\a xpr is assumed to be rotation matrix\n  *     and \\a xpr is converted to a quaternion\n  */\n\ntemplate<class Derived>\ntemplate<class MatrixDerived>\nEIGEN_DEVICE_FUNC inline Derived& QuaternionBase<Derived>::operator=(const MatrixBase<MatrixDerived>& xpr)\n{\n  EIGEN_STATIC_ASSERT((internal::is_same<typename Derived::Scalar, typename MatrixDerived::Scalar>::value),\n   YOU_MIXED_DIFFERENT_NUMERIC_TYPES__YOU_NEED_TO_USE_THE_CAST_METHOD_OF_MATRIXBASE_TO_CAST_NUMERIC_TYPES_EXPLICITLY)\n  internal::quaternionbase_assign_impl<MatrixDerived>::run(*this, xpr.derived());\n  return derived();\n}\n\n/** Convert the quaternion to a 3x3 rotation matrix. The quaternion is required to\n  * be normalized, otherwise the result is undefined.\n  */\ntemplate<class Derived>\nEIGEN_DEVICE_FUNC inline typename QuaternionBase<Derived>::Matrix3\nQuaternionBase<Derived>::toRotationMatrix(void) const\n{\n  // NOTE if inlined, then gcc 4.2 and 4.4 get rid of the temporary (not gcc 4.3 !!)\n  // if not inlined then the cost of the return by value is huge ~ +35%,\n  // however, not inlining this function is an order of magnitude slower, so\n  // it has to be inlined, and so the return by value is not an issue\n  Matrix3 res;\n\n  const Scalar tx  = Scalar(2)*this->x();\n  const Scalar ty  = Scalar(2)*this->y();\n  const Scalar tz  = Scalar(2)*this->z();\n  const Scalar twx = tx*this->w();\n  const Scalar twy = ty*this->w();\n  const Scalar twz = tz*this->w();\n  const Scalar txx = tx*this->x();\n  const Scalar txy = ty*this->x();\n  const Scalar txz = tz*this->x();\n  const Scalar tyy = ty*this->y();\n  const Scalar tyz = tz*this->y();\n  const Scalar tzz = tz*this->z();\n\n  res.coeffRef(0,0) = Scalar(1)-(tyy+tzz);\n  res.coeffRef(0,1) = txy-twz;\n  res.coeffRef(0,2) = txz+twy;\n  res.coeffRef(1,0) = txy+twz;\n  res.coeffRef(1,1) = Scalar(1)-(txx+tzz);\n  res.coeffRef(1,2) = tyz-twx;\n  res.coeffRef(2,0) = txz-twy;\n  res.coeffRef(2,1) = tyz+twx;\n  res.coeffRef(2,2) = Scalar(1)-(txx+tyy);\n\n  return res;\n}\n\n/** Sets \\c *this to be a quaternion representing a rotation between\n  * the two arbitrary vectors \\a a and \\a b. In other words, the built\n  * rotation represent a rotation sending the line of direction \\a a\n  * to the line of direction \\a b, both lines passing through the origin.\n  *\n  * \\returns a reference to \\c *this.\n  *\n  * Note that the two input vectors do \\b not have to be normalized, and\n  * do not need to have the same norm.\n  */\ntemplate<class Derived>\ntemplate<typename Derived1, typename Derived2>\nEIGEN_DEVICE_FUNC inline Derived& QuaternionBase<Derived>::setFromTwoVectors(const MatrixBase<Derived1>& a, const MatrixBase<Derived2>& b)\n{\n  EIGEN_USING_STD_MATH(sqrt)\n  Vector3 v0 = a.normalized();\n  Vector3 v1 = b.normalized();\n  Scalar c = v1.dot(v0);\n\n  // if dot == -1, vectors are nearly opposites\n  // => accurately compute the rotation axis by computing the\n  //    intersection of the two planes. This is done by solving:\n  //       x^T v0 = 0\n  //       x^T v1 = 0\n  //    under the constraint:\n  //       ||x|| = 1\n  //    which yields a singular value problem\n  if (c < Scalar(-1)+NumTraits<Scalar>::dummy_precision())\n  {\n    c = numext::maxi(c,Scalar(-1));\n    Matrix<Scalar,2,3> m; m << v0.transpose(), v1.transpose();\n    JacobiSVD<Matrix<Scalar,2,3> > svd(m, ComputeFullV);\n    Vector3 axis = svd.matrixV().col(2);\n\n    Scalar w2 = (Scalar(1)+c)*Scalar(0.5);\n    this->w() = sqrt(w2);\n    this->vec() = axis * sqrt(Scalar(1) - w2);\n    return derived();\n  }\n  Vector3 axis = v0.cross(v1);\n  Scalar s = sqrt((Scalar(1)+c)*Scalar(2));\n  Scalar invs = Scalar(1)/s;\n  this->vec() = axis * invs;\n  this->w() = s * Scalar(0.5);\n\n  return derived();\n}\n\n/** \\returns a random unit quaternion following a uniform distribution law on SO(3)\n  *\n  * \\note The implementation is based on http://planning.cs.uiuc.edu/node198.html\n  */\ntemplate<typename Scalar, int Options>\nEIGEN_DEVICE_FUNC Quaternion<Scalar,Options> Quaternion<Scalar,Options>::UnitRandom()\n{\n  EIGEN_USING_STD_MATH(sqrt)\n  EIGEN_USING_STD_MATH(sin)\n  EIGEN_USING_STD_MATH(cos)\n  const Scalar u1 = internal::random<Scalar>(0, 1),\n               u2 = internal::random<Scalar>(0, 2*EIGEN_PI),\n               u3 = internal::random<Scalar>(0, 2*EIGEN_PI);\n  const Scalar a = sqrt(1 - u1),\n               b = sqrt(u1);\n  return Quaternion (a * sin(u2), a * cos(u2), b * sin(u3), b * cos(u3));\n}\n\n\n/** Returns a quaternion representing a rotation between\n  * the two arbitrary vectors \\a a and \\a b. In other words, the built\n  * rotation represent a rotation sending the line of direction \\a a\n  * to the line of direction \\a b, both lines passing through the origin.\n  *\n  * \\returns resulting quaternion\n  *\n  * Note that the two input vectors do \\b not have to be normalized, and\n  * do not need to have the same norm.\n  */\ntemplate<typename Scalar, int Options>\ntemplate<typename Derived1, typename Derived2>\nEIGEN_DEVICE_FUNC Quaternion<Scalar,Options> Quaternion<Scalar,Options>::FromTwoVectors(const MatrixBase<Derived1>& a, const MatrixBase<Derived2>& b)\n{\n    Quaternion quat;\n    quat.setFromTwoVectors(a, b);\n    return quat;\n}\n\n\n/** \\returns the multiplicative inverse of \\c *this\n  * Note that in most cases, i.e., if you simply want the opposite rotation,\n  * and/or the quaternion is normalized, then it is enough to use the conjugate.\n  *\n  * \\sa QuaternionBase::conjugate()\n  */\ntemplate <class Derived>\nEIGEN_DEVICE_FUNC inline Quaternion<typename internal::traits<Derived>::Scalar> QuaternionBase<Derived>::inverse() const\n{\n  // FIXME should this function be called multiplicativeInverse and conjugate() be called inverse() or opposite()  ??\n  Scalar n2 = this->squaredNorm();\n  if (n2 > Scalar(0))\n    return Quaternion<Scalar>(conjugate().coeffs() / n2);\n  else\n  {\n    // return an invalid result to flag the error\n    return Quaternion<Scalar>(Coefficients::Zero());\n  }\n}\n\n// Generic conjugate of a Quaternion\nnamespace internal {\ntemplate<int Arch, class Derived, typename Scalar, int _Options> struct quat_conj\n{\n  EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE Quaternion<Scalar> run(const QuaternionBase<Derived>& q){\n    return Quaternion<Scalar>(q.w(),-q.x(),-q.y(),-q.z());\n  }\n};\n}\n                         \n/** \\returns the conjugate of the \\c *this which is equal to the multiplicative inverse\n  * if the quaternion is normalized.\n  * The conjugate of a quaternion represents the opposite rotation.\n  *\n  * \\sa Quaternion2::inverse()\n  */\ntemplate <class Derived>\nEIGEN_DEVICE_FUNC inline Quaternion<typename internal::traits<Derived>::Scalar>\nQuaternionBase<Derived>::conjugate() const\n{\n  return internal::quat_conj<Architecture::Target, Derived,\n                         typename internal::traits<Derived>::Scalar,\n                         internal::traits<Derived>::Alignment>::run(*this);\n                         \n}\n\n/** \\returns the angle (in radian) between two rotations\n  * \\sa dot()\n  */\ntemplate <class Derived>\ntemplate <class OtherDerived>\nEIGEN_DEVICE_FUNC inline typename internal::traits<Derived>::Scalar\nQuaternionBase<Derived>::angularDistance(const QuaternionBase<OtherDerived>& other) const\n{\n  EIGEN_USING_STD_MATH(atan2)\n  Quaternion<Scalar> d = (*this) * other.conjugate();\n  return Scalar(2) * atan2( d.vec().norm(), numext::abs(d.w()) );\n}\n\n \n    \n/** \\returns the spherical linear interpolation between the two quaternions\n  * \\c *this and \\a other at the parameter \\a t in [0;1].\n  * \n  * This represents an interpolation for a constant motion between \\c *this and \\a other,\n  * see also http://en.wikipedia.org/wiki/Slerp.\n  */\ntemplate <class Derived>\ntemplate <class OtherDerived>\nEIGEN_DEVICE_FUNC Quaternion<typename internal::traits<Derived>::Scalar>\nQuaternionBase<Derived>::slerp(const Scalar& t, const QuaternionBase<OtherDerived>& other) const\n{\n  EIGEN_USING_STD_MATH(acos)\n  EIGEN_USING_STD_MATH(sin)\n  const Scalar one = Scalar(1) - NumTraits<Scalar>::epsilon();\n  Scalar d = this->dot(other);\n  Scalar absD = numext::abs(d);\n\n  Scalar scale0;\n  Scalar scale1;\n\n  if(absD>=one)\n  {\n    scale0 = Scalar(1) - t;\n    scale1 = t;\n  }\n  else\n  {\n    // theta is the angle between the 2 quaternions\n    Scalar theta = acos(absD);\n    Scalar sinTheta = sin(theta);\n\n    scale0 = sin( ( Scalar(1) - t ) * theta) / sinTheta;\n    scale1 = sin( ( t * theta) ) / sinTheta;\n  }\n  if(d<Scalar(0)) scale1 = -scale1;\n\n  return Quaternion<Scalar>(scale0 * coeffs() + scale1 * other.coeffs());\n}\n\nnamespace internal {\n\n// set from a rotation matrix\ntemplate<typename Other>\nstruct quaternionbase_assign_impl<Other,3,3>\n{\n  typedef typename Other::Scalar Scalar;\n  template<class Derived> EIGEN_DEVICE_FUNC static inline void run(QuaternionBase<Derived>& q, const Other& a_mat)\n  {\n    const typename internal::nested_eval<Other,2>::type mat(a_mat);\n    EIGEN_USING_STD_MATH(sqrt)\n    // This algorithm comes from  \"Quaternion Calculus and Fast Animation\",\n    // Ken Shoemake, 1987 SIGGRAPH course notes\n    Scalar t = mat.trace();\n    if (t > Scalar(0))\n    {\n      t = sqrt(t + Scalar(1.0));\n      q.w() = Scalar(0.5)*t;\n      t = Scalar(0.5)/t;\n      q.x() = (mat.coeff(2,1) - mat.coeff(1,2)) * t;\n      q.y() = (mat.coeff(0,2) - mat.coeff(2,0)) * t;\n      q.z() = (mat.coeff(1,0) - mat.coeff(0,1)) * t;\n    }\n    else\n    {\n      Index i = 0;\n      if (mat.coeff(1,1) > mat.coeff(0,0))\n        i = 1;\n      if (mat.coeff(2,2) > mat.coeff(i,i))\n        i = 2;\n      Index j = (i+1)%3;\n      Index k = (j+1)%3;\n\n      t = sqrt(mat.coeff(i,i)-mat.coeff(j,j)-mat.coeff(k,k) + Scalar(1.0));\n      q.coeffs().coeffRef(i) = Scalar(0.5) * t;\n      t = Scalar(0.5)/t;\n      q.w() = (mat.coeff(k,j)-mat.coeff(j,k))*t;\n      q.coeffs().coeffRef(j) = (mat.coeff(j,i)+mat.coeff(i,j))*t;\n      q.coeffs().coeffRef(k) = (mat.coeff(k,i)+mat.coeff(i,k))*t;\n    }\n  }\n};\n\n// set from a vector of coefficients assumed to be a quaternion\ntemplate<typename Other>\nstruct quaternionbase_assign_impl<Other,4,1>\n{\n  typedef typename Other::Scalar Scalar;\n  template<class Derived> EIGEN_DEVICE_FUNC static inline void run(QuaternionBase<Derived>& q, const Other& vec)\n  {\n    q.coeffs() = vec;\n  }\n};\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_QUATERNION_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Geometry/Rotation2D.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_ROTATION2D_H\n#define EIGEN_ROTATION2D_H\n\nnamespace Eigen { \n\n/** \\geometry_module \\ingroup Geometry_Module\n  *\n  * \\class Rotation2D\n  *\n  * \\brief Represents a rotation/orientation in a 2 dimensional space.\n  *\n  * \\tparam _Scalar the scalar type, i.e., the type of the coefficients\n  *\n  * This class is equivalent to a single scalar representing a counter clock wise rotation\n  * as a single angle in radian. It provides some additional features such as the automatic\n  * conversion from/to a 2x2 rotation matrix. Moreover this class aims to provide a similar\n  * interface to Quaternion in order to facilitate the writing of generic algorithms\n  * dealing with rotations.\n  *\n  * \\sa class Quaternion, class Transform\n  */\n\nnamespace internal {\n\ntemplate<typename _Scalar> struct traits<Rotation2D<_Scalar> >\n{\n  typedef _Scalar Scalar;\n};\n} // end namespace internal\n\ntemplate<typename _Scalar>\nclass Rotation2D : public RotationBase<Rotation2D<_Scalar>,2>\n{\n  typedef RotationBase<Rotation2D<_Scalar>,2> Base;\n\npublic:\n\n  using Base::operator*;\n\n  enum { Dim = 2 };\n  /** the scalar type of the coefficients */\n  typedef _Scalar Scalar;\n  typedef Matrix<Scalar,2,1> Vector2;\n  typedef Matrix<Scalar,2,2> Matrix2;\n\nprotected:\n\n  Scalar m_angle;\n\npublic:\n\n  /** Construct a 2D counter clock wise rotation from the angle \\a a in radian. */\n  EIGEN_DEVICE_FUNC explicit inline Rotation2D(const Scalar& a) : m_angle(a) {}\n  \n  /** Default constructor wihtout initialization. The represented rotation is undefined. */\n  EIGEN_DEVICE_FUNC Rotation2D() {}\n\n  /** Construct a 2D rotation from a 2x2 rotation matrix \\a mat.\n    *\n    * \\sa fromRotationMatrix()\n    */\n  template<typename Derived>\n  EIGEN_DEVICE_FUNC explicit Rotation2D(const MatrixBase<Derived>& m)\n  {\n    fromRotationMatrix(m.derived());\n  }\n\n  /** \\returns the rotation angle */\n  EIGEN_DEVICE_FUNC inline Scalar angle() const { return m_angle; }\n\n  /** \\returns a read-write reference to the rotation angle */\n  EIGEN_DEVICE_FUNC inline Scalar& angle() { return m_angle; }\n  \n  /** \\returns the rotation angle in [0,2pi] */\n  EIGEN_DEVICE_FUNC inline Scalar smallestPositiveAngle() const {\n    Scalar tmp = numext::fmod(m_angle,Scalar(2*EIGEN_PI));\n    return tmp<Scalar(0) ? tmp + Scalar(2*EIGEN_PI) : tmp;\n  }\n  \n  /** \\returns the rotation angle in [-pi,pi] */\n  EIGEN_DEVICE_FUNC inline Scalar smallestAngle() const {\n    Scalar tmp = numext::fmod(m_angle,Scalar(2*EIGEN_PI));\n    if(tmp>Scalar(EIGEN_PI))       tmp -= Scalar(2*EIGEN_PI);\n    else if(tmp<-Scalar(EIGEN_PI)) tmp += Scalar(2*EIGEN_PI);\n    return tmp;\n  }\n\n  /** \\returns the inverse rotation */\n  EIGEN_DEVICE_FUNC inline Rotation2D inverse() const { return Rotation2D(-m_angle); }\n\n  /** Concatenates two rotations */\n  EIGEN_DEVICE_FUNC inline Rotation2D operator*(const Rotation2D& other) const\n  { return Rotation2D(m_angle + other.m_angle); }\n\n  /** Concatenates two rotations */\n  EIGEN_DEVICE_FUNC inline Rotation2D& operator*=(const Rotation2D& other)\n  { m_angle += other.m_angle; return *this; }\n\n  /** Applies the rotation to a 2D vector */\n  EIGEN_DEVICE_FUNC Vector2 operator* (const Vector2& vec) const\n  { return toRotationMatrix() * vec; }\n  \n  template<typename Derived>\n  EIGEN_DEVICE_FUNC Rotation2D& fromRotationMatrix(const MatrixBase<Derived>& m);\n  EIGEN_DEVICE_FUNC Matrix2 toRotationMatrix() const;\n\n  /** Set \\c *this from a 2x2 rotation matrix \\a mat.\n    * In other words, this function extract the rotation angle from the rotation matrix.\n    *\n    * This method is an alias for fromRotationMatrix()\n    *\n    * \\sa fromRotationMatrix()\n    */\n  template<typename Derived>\n  EIGEN_DEVICE_FUNC Rotation2D& operator=(const  MatrixBase<Derived>& m)\n  { return fromRotationMatrix(m.derived()); }\n\n  /** \\returns the spherical interpolation between \\c *this and \\a other using\n    * parameter \\a t. It is in fact equivalent to a linear interpolation.\n    */\n  EIGEN_DEVICE_FUNC inline Rotation2D slerp(const Scalar& t, const Rotation2D& other) const\n  {\n    Scalar dist = Rotation2D(other.m_angle-m_angle).smallestAngle();\n    return Rotation2D(m_angle + dist*t);\n  }\n\n  /** \\returns \\c *this with scalar type casted to \\a NewScalarType\n    *\n    * Note that if \\a NewScalarType is equal to the current scalar type of \\c *this\n    * then this function smartly returns a const reference to \\c *this.\n    */\n  template<typename NewScalarType>\n  EIGEN_DEVICE_FUNC inline typename internal::cast_return_type<Rotation2D,Rotation2D<NewScalarType> >::type cast() const\n  { return typename internal::cast_return_type<Rotation2D,Rotation2D<NewScalarType> >::type(*this); }\n\n  /** Copy constructor with scalar type conversion */\n  template<typename OtherScalarType>\n  EIGEN_DEVICE_FUNC inline explicit Rotation2D(const Rotation2D<OtherScalarType>& other)\n  {\n    m_angle = Scalar(other.angle());\n  }\n\n  EIGEN_DEVICE_FUNC static inline Rotation2D Identity() { return Rotation2D(0); }\n\n  /** \\returns \\c true if \\c *this is approximately equal to \\a other, within the precision\n    * determined by \\a prec.\n    *\n    * \\sa MatrixBase::isApprox() */\n  EIGEN_DEVICE_FUNC bool isApprox(const Rotation2D& other, const typename NumTraits<Scalar>::Real& prec = NumTraits<Scalar>::dummy_precision()) const\n  { return internal::isApprox(m_angle,other.m_angle, prec); }\n  \n};\n\n/** \\ingroup Geometry_Module\n  * single precision 2D rotation type */\ntypedef Rotation2D<float> Rotation2Df;\n/** \\ingroup Geometry_Module\n  * double precision 2D rotation type */\ntypedef Rotation2D<double> Rotation2Dd;\n\n/** Set \\c *this from a 2x2 rotation matrix \\a mat.\n  * In other words, this function extract the rotation angle\n  * from the rotation matrix.\n  */\ntemplate<typename Scalar>\ntemplate<typename Derived>\nEIGEN_DEVICE_FUNC Rotation2D<Scalar>& Rotation2D<Scalar>::fromRotationMatrix(const MatrixBase<Derived>& mat)\n{\n  EIGEN_USING_STD_MATH(atan2)\n  EIGEN_STATIC_ASSERT(Derived::RowsAtCompileTime==2 && Derived::ColsAtCompileTime==2,YOU_MADE_A_PROGRAMMING_MISTAKE)\n  m_angle = atan2(mat.coeff(1,0), mat.coeff(0,0));\n  return *this;\n}\n\n/** Constructs and \\returns an equivalent 2x2 rotation matrix.\n  */\ntemplate<typename Scalar>\ntypename Rotation2D<Scalar>::Matrix2\nEIGEN_DEVICE_FUNC Rotation2D<Scalar>::toRotationMatrix(void) const\n{\n  EIGEN_USING_STD_MATH(sin)\n  EIGEN_USING_STD_MATH(cos)\n  Scalar sinA = sin(m_angle);\n  Scalar cosA = cos(m_angle);\n  return (Matrix2() << cosA, -sinA, sinA, cosA).finished();\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_ROTATION2D_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Geometry/RotationBase.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_ROTATIONBASE_H\n#define EIGEN_ROTATIONBASE_H\n\nnamespace Eigen { \n\n// forward declaration\nnamespace internal {\ntemplate<typename RotationDerived, typename MatrixType, bool IsVector=MatrixType::IsVectorAtCompileTime>\nstruct rotation_base_generic_product_selector;\n}\n\n/** \\class RotationBase\n  *\n  * \\brief Common base class for compact rotation representations\n  *\n  * \\tparam Derived is the derived type, i.e., a rotation type\n  * \\tparam _Dim the dimension of the space\n  */\ntemplate<typename Derived, int _Dim>\nclass RotationBase\n{\n  public:\n    enum { Dim = _Dim };\n    /** the scalar type of the coefficients */\n    typedef typename internal::traits<Derived>::Scalar Scalar;\n\n    /** corresponding linear transformation matrix type */\n    typedef Matrix<Scalar,Dim,Dim> RotationMatrixType;\n    typedef Matrix<Scalar,Dim,1> VectorType;\n\n  public:\n    EIGEN_DEVICE_FUNC inline const Derived& derived() const { return *static_cast<const Derived*>(this); }\n    EIGEN_DEVICE_FUNC inline Derived& derived() { return *static_cast<Derived*>(this); }\n\n    /** \\returns an equivalent rotation matrix */\n    EIGEN_DEVICE_FUNC inline RotationMatrixType toRotationMatrix() const { return derived().toRotationMatrix(); }\n\n    /** \\returns an equivalent rotation matrix \n      * This function is added to be conform with the Transform class' naming scheme.\n      */\n    EIGEN_DEVICE_FUNC inline RotationMatrixType matrix() const { return derived().toRotationMatrix(); }\n\n    /** \\returns the inverse rotation */\n    EIGEN_DEVICE_FUNC inline Derived inverse() const { return derived().inverse(); }\n\n    /** \\returns the concatenation of the rotation \\c *this with a translation \\a t */\n    EIGEN_DEVICE_FUNC inline Transform<Scalar,Dim,Isometry> operator*(const Translation<Scalar,Dim>& t) const\n    { return Transform<Scalar,Dim,Isometry>(*this) * t; }\n\n    /** \\returns the concatenation of the rotation \\c *this with a uniform scaling \\a s */\n    EIGEN_DEVICE_FUNC inline RotationMatrixType operator*(const UniformScaling<Scalar>& s) const\n    { return toRotationMatrix() * s.factor(); }\n\n    /** \\returns the concatenation of the rotation \\c *this with a generic expression \\a e\n      * \\a e can be:\n      *  - a DimxDim linear transformation matrix\n      *  - a DimxDim diagonal matrix (axis aligned scaling)\n      *  - a vector of size Dim\n      */\n    template<typename OtherDerived>\n    EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE typename internal::rotation_base_generic_product_selector<Derived,OtherDerived,OtherDerived::IsVectorAtCompileTime>::ReturnType\n    operator*(const EigenBase<OtherDerived>& e) const\n    { return internal::rotation_base_generic_product_selector<Derived,OtherDerived>::run(derived(), e.derived()); }\n\n    /** \\returns the concatenation of a linear transformation \\a l with the rotation \\a r */\n    template<typename OtherDerived> friend\n    EIGEN_DEVICE_FUNC inline RotationMatrixType operator*(const EigenBase<OtherDerived>& l, const Derived& r)\n    { return l.derived() * r.toRotationMatrix(); }\n\n    /** \\returns the concatenation of a scaling \\a l with the rotation \\a r */\n    EIGEN_DEVICE_FUNC friend inline Transform<Scalar,Dim,Affine> operator*(const DiagonalMatrix<Scalar,Dim>& l, const Derived& r)\n    { \n      Transform<Scalar,Dim,Affine> res(r);\n      res.linear().applyOnTheLeft(l);\n      return res;\n    }\n\n    /** \\returns the concatenation of the rotation \\c *this with a transformation \\a t */\n    template<int Mode, int Options>\n    EIGEN_DEVICE_FUNC inline Transform<Scalar,Dim,Mode> operator*(const Transform<Scalar,Dim,Mode,Options>& t) const\n    { return toRotationMatrix() * t; }\n\n    template<typename OtherVectorType>\n    EIGEN_DEVICE_FUNC inline VectorType _transformVector(const OtherVectorType& v) const\n    { return toRotationMatrix() * v; }\n};\n\nnamespace internal {\n\n// implementation of the generic product rotation * matrix\ntemplate<typename RotationDerived, typename MatrixType>\nstruct rotation_base_generic_product_selector<RotationDerived,MatrixType,false>\n{\n  enum { Dim = RotationDerived::Dim };\n  typedef Matrix<typename RotationDerived::Scalar,Dim,Dim> ReturnType;\n  EIGEN_DEVICE_FUNC static inline ReturnType run(const RotationDerived& r, const MatrixType& m)\n  { return r.toRotationMatrix() * m; }\n};\n\ntemplate<typename RotationDerived, typename Scalar, int Dim, int MaxDim>\nstruct rotation_base_generic_product_selector< RotationDerived, DiagonalMatrix<Scalar,Dim,MaxDim>, false >\n{\n  typedef Transform<Scalar,Dim,Affine> ReturnType;\n  EIGEN_DEVICE_FUNC static inline ReturnType run(const RotationDerived& r, const DiagonalMatrix<Scalar,Dim,MaxDim>& m)\n  {\n    ReturnType res(r);\n    res.linear() *= m;\n    return res;\n  }\n};\n\ntemplate<typename RotationDerived,typename OtherVectorType>\nstruct rotation_base_generic_product_selector<RotationDerived,OtherVectorType,true>\n{\n  enum { Dim = RotationDerived::Dim };\n  typedef Matrix<typename RotationDerived::Scalar,Dim,1> ReturnType;\n  EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE ReturnType run(const RotationDerived& r, const OtherVectorType& v)\n  {\n    return r._transformVector(v);\n  }\n};\n\n} // end namespace internal\n\n/** \\geometry_module\n  *\n  * \\brief Constructs a Dim x Dim rotation matrix from the rotation \\a r\n  */\ntemplate<typename _Scalar, int _Rows, int _Cols, int _Storage, int _MaxRows, int _MaxCols>\ntemplate<typename OtherDerived>\nEIGEN_DEVICE_FUNC Matrix<_Scalar, _Rows, _Cols, _Storage, _MaxRows, _MaxCols>\n::Matrix(const RotationBase<OtherDerived,ColsAtCompileTime>& r)\n{\n  EIGEN_STATIC_ASSERT_MATRIX_SPECIFIC_SIZE(Matrix,int(OtherDerived::Dim),int(OtherDerived::Dim))\n  *this = r.toRotationMatrix();\n}\n\n/** \\geometry_module\n  *\n  * \\brief Set a Dim x Dim rotation matrix from the rotation \\a r\n  */\ntemplate<typename _Scalar, int _Rows, int _Cols, int _Storage, int _MaxRows, int _MaxCols>\ntemplate<typename OtherDerived>\nEIGEN_DEVICE_FUNC Matrix<_Scalar, _Rows, _Cols, _Storage, _MaxRows, _MaxCols>&\nMatrix<_Scalar, _Rows, _Cols, _Storage, _MaxRows, _MaxCols>\n::operator=(const RotationBase<OtherDerived,ColsAtCompileTime>& r)\n{\n  EIGEN_STATIC_ASSERT_MATRIX_SPECIFIC_SIZE(Matrix,int(OtherDerived::Dim),int(OtherDerived::Dim))\n  return *this = r.toRotationMatrix();\n}\n\nnamespace internal {\n\n/** \\internal\n  *\n  * Helper function to return an arbitrary rotation object to a rotation matrix.\n  *\n  * \\tparam Scalar the numeric type of the matrix coefficients\n  * \\tparam Dim the dimension of the current space\n  *\n  * It returns a Dim x Dim fixed size matrix.\n  *\n  * Default specializations are provided for:\n  *   - any scalar type (2D),\n  *   - any matrix expression,\n  *   - any type based on RotationBase (e.g., Quaternion, AngleAxis, Rotation2D)\n  *\n  * Currently toRotationMatrix is only used by Transform.\n  *\n  * \\sa class Transform, class Rotation2D, class Quaternion, class AngleAxis\n  */\ntemplate<typename Scalar, int Dim>\nEIGEN_DEVICE_FUNC static inline Matrix<Scalar,2,2> toRotationMatrix(const Scalar& s)\n{\n  EIGEN_STATIC_ASSERT(Dim==2,YOU_MADE_A_PROGRAMMING_MISTAKE)\n  return Rotation2D<Scalar>(s).toRotationMatrix();\n}\n\ntemplate<typename Scalar, int Dim, typename OtherDerived>\nEIGEN_DEVICE_FUNC static inline Matrix<Scalar,Dim,Dim> toRotationMatrix(const RotationBase<OtherDerived,Dim>& r)\n{\n  return r.toRotationMatrix();\n}\n\ntemplate<typename Scalar, int Dim, typename OtherDerived>\nEIGEN_DEVICE_FUNC static inline const MatrixBase<OtherDerived>& toRotationMatrix(const MatrixBase<OtherDerived>& mat)\n{\n  EIGEN_STATIC_ASSERT(OtherDerived::RowsAtCompileTime==Dim && OtherDerived::ColsAtCompileTime==Dim,\n    YOU_MADE_A_PROGRAMMING_MISTAKE)\n  return mat;\n}\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_ROTATIONBASE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Geometry/Scaling.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SCALING_H\n#define EIGEN_SCALING_H\n\nnamespace Eigen { \n\n/** \\geometry_module \\ingroup Geometry_Module\n  *\n  * \\class Scaling\n  *\n  * \\brief Represents a generic uniform scaling transformation\n  *\n  * \\tparam _Scalar the scalar type, i.e., the type of the coefficients.\n  *\n  * This class represent a uniform scaling transformation. It is the return\n  * type of Scaling(Scalar), and most of the time this is the only way it\n  * is used. In particular, this class is not aimed to be used to store a scaling transformation,\n  * but rather to make easier the constructions and updates of Transform objects.\n  *\n  * To represent an axis aligned scaling, use the DiagonalMatrix class.\n  *\n  * \\sa Scaling(), class DiagonalMatrix, MatrixBase::asDiagonal(), class Translation, class Transform\n  */\ntemplate<typename _Scalar>\nclass UniformScaling\n{\npublic:\n  /** the scalar type of the coefficients */\n  typedef _Scalar Scalar;\n\nprotected:\n\n  Scalar m_factor;\n\npublic:\n\n  /** Default constructor without initialization. */\n  UniformScaling() {}\n  /** Constructs and initialize a uniform scaling transformation */\n  explicit inline UniformScaling(const Scalar& s) : m_factor(s) {}\n\n  inline const Scalar& factor() const { return m_factor; }\n  inline Scalar& factor() { return m_factor; }\n\n  /** Concatenates two uniform scaling */\n  inline UniformScaling operator* (const UniformScaling& other) const\n  { return UniformScaling(m_factor * other.factor()); }\n\n  /** Concatenates a uniform scaling and a translation */\n  template<int Dim>\n  inline Transform<Scalar,Dim,Affine> operator* (const Translation<Scalar,Dim>& t) const;\n\n  /** Concatenates a uniform scaling and an affine transformation */\n  template<int Dim, int Mode, int Options>\n  inline Transform<Scalar,Dim,(int(Mode)==int(Isometry)?Affine:Mode)> operator* (const Transform<Scalar,Dim, Mode, Options>& t) const\n  {\n    Transform<Scalar,Dim,(int(Mode)==int(Isometry)?Affine:Mode)> res = t;\n    res.prescale(factor());\n    return res;\n  }\n\n  /** Concatenates a uniform scaling and a linear transformation matrix */\n  // TODO returns an expression\n  template<typename Derived>\n  inline typename internal::plain_matrix_type<Derived>::type operator* (const MatrixBase<Derived>& other) const\n  { return other * m_factor; }\n\n  template<typename Derived,int Dim>\n  inline Matrix<Scalar,Dim,Dim> operator*(const RotationBase<Derived,Dim>& r) const\n  { return r.toRotationMatrix() * m_factor; }\n\n  /** \\returns the inverse scaling */\n  inline UniformScaling inverse() const\n  { return UniformScaling(Scalar(1)/m_factor); }\n\n  /** \\returns \\c *this with scalar type casted to \\a NewScalarType\n    *\n    * Note that if \\a NewScalarType is equal to the current scalar type of \\c *this\n    * then this function smartly returns a const reference to \\c *this.\n    */\n  template<typename NewScalarType>\n  inline UniformScaling<NewScalarType> cast() const\n  { return UniformScaling<NewScalarType>(NewScalarType(m_factor)); }\n\n  /** Copy constructor with scalar type conversion */\n  template<typename OtherScalarType>\n  inline explicit UniformScaling(const UniformScaling<OtherScalarType>& other)\n  { m_factor = Scalar(other.factor()); }\n\n  /** \\returns \\c true if \\c *this is approximately equal to \\a other, within the precision\n    * determined by \\a prec.\n    *\n    * \\sa MatrixBase::isApprox() */\n  bool isApprox(const UniformScaling& other, const typename NumTraits<Scalar>::Real& prec = NumTraits<Scalar>::dummy_precision()) const\n  { return internal::isApprox(m_factor, other.factor(), prec); }\n\n};\n\n/** \\addtogroup Geometry_Module */\n//@{\n\n/** Concatenates a linear transformation matrix and a uniform scaling\n  * \\relates UniformScaling\n  */\n// NOTE this operator is defiend in MatrixBase and not as a friend function\n// of UniformScaling to fix an internal crash of Intel's ICC\ntemplate<typename Derived,typename Scalar>\nEIGEN_EXPR_BINARYOP_SCALAR_RETURN_TYPE(Derived,Scalar,product)\noperator*(const MatrixBase<Derived>& matrix, const UniformScaling<Scalar>& s)\n{ return matrix.derived() * s.factor(); }\n\n/** Constructs a uniform scaling from scale factor \\a s */\ninline UniformScaling<float> Scaling(float s) { return UniformScaling<float>(s); }\n/** Constructs a uniform scaling from scale factor \\a s */\ninline UniformScaling<double> Scaling(double s) { return UniformScaling<double>(s); }\n/** Constructs a uniform scaling from scale factor \\a s */\ntemplate<typename RealScalar>\ninline UniformScaling<std::complex<RealScalar> > Scaling(const std::complex<RealScalar>& s)\n{ return UniformScaling<std::complex<RealScalar> >(s); }\n\n/** Constructs a 2D axis aligned scaling */\ntemplate<typename Scalar>\ninline DiagonalMatrix<Scalar,2> Scaling(const Scalar& sx, const Scalar& sy)\n{ return DiagonalMatrix<Scalar,2>(sx, sy); }\n/** Constructs a 3D axis aligned scaling */\ntemplate<typename Scalar>\ninline DiagonalMatrix<Scalar,3> Scaling(const Scalar& sx, const Scalar& sy, const Scalar& sz)\n{ return DiagonalMatrix<Scalar,3>(sx, sy, sz); }\n\n/** Constructs an axis aligned scaling expression from vector expression \\a coeffs\n  * This is an alias for coeffs.asDiagonal()\n  */\ntemplate<typename Derived>\ninline const DiagonalWrapper<const Derived> Scaling(const MatrixBase<Derived>& coeffs)\n{ return coeffs.asDiagonal(); }\n\n/** \\deprecated */\ntypedef DiagonalMatrix<float, 2> AlignedScaling2f;\n/** \\deprecated */\ntypedef DiagonalMatrix<double,2> AlignedScaling2d;\n/** \\deprecated */\ntypedef DiagonalMatrix<float, 3> AlignedScaling3f;\n/** \\deprecated */\ntypedef DiagonalMatrix<double,3> AlignedScaling3d;\n//@}\n\ntemplate<typename Scalar>\ntemplate<int Dim>\ninline Transform<Scalar,Dim,Affine>\nUniformScaling<Scalar>::operator* (const Translation<Scalar,Dim>& t) const\n{\n  Transform<Scalar,Dim,Affine> res;\n  res.matrix().setZero();\n  res.linear().diagonal().fill(factor());\n  res.translation() = factor() * t.vector();\n  res(Dim,Dim) = Scalar(1);\n  return res;\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_SCALING_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Geometry/Transform.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2009 Benoit Jacob <jacob.benoit.1@gmail.com>\n// Copyright (C) 2010 Hauke Heibel <hauke.heibel@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_TRANSFORM_H\n#define EIGEN_TRANSFORM_H\n\nnamespace Eigen { \n\nnamespace internal {\n\ntemplate<typename Transform>\nstruct transform_traits\n{\n  enum\n  {\n    Dim = Transform::Dim,\n    HDim = Transform::HDim,\n    Mode = Transform::Mode,\n    IsProjective = (int(Mode)==int(Projective))\n  };\n};\n\ntemplate< typename TransformType,\n          typename MatrixType,\n          int Case = transform_traits<TransformType>::IsProjective ? 0\n                   : int(MatrixType::RowsAtCompileTime) == int(transform_traits<TransformType>::HDim) ? 1\n                   : 2,\n          int RhsCols = MatrixType::ColsAtCompileTime>\nstruct transform_right_product_impl;\n\ntemplate< typename Other,\n          int Mode,\n          int Options,\n          int Dim,\n          int HDim,\n          int OtherRows=Other::RowsAtCompileTime,\n          int OtherCols=Other::ColsAtCompileTime>\nstruct transform_left_product_impl;\n\ntemplate< typename Lhs,\n          typename Rhs,\n          bool AnyProjective = \n            transform_traits<Lhs>::IsProjective ||\n            transform_traits<Rhs>::IsProjective>\nstruct transform_transform_product_impl;\n\ntemplate< typename Other,\n          int Mode,\n          int Options,\n          int Dim,\n          int HDim,\n          int OtherRows=Other::RowsAtCompileTime,\n          int OtherCols=Other::ColsAtCompileTime>\nstruct transform_construct_from_matrix;\n\ntemplate<typename TransformType> struct transform_take_affine_part;\n\ntemplate<typename _Scalar, int _Dim, int _Mode, int _Options>\nstruct traits<Transform<_Scalar,_Dim,_Mode,_Options> >\n{\n  typedef _Scalar Scalar;\n  typedef Eigen::Index StorageIndex;\n  typedef Dense StorageKind;\n  enum {\n    Dim1 = _Dim==Dynamic ? _Dim : _Dim + 1,\n    RowsAtCompileTime = _Mode==Projective ? Dim1 : _Dim,\n    ColsAtCompileTime = Dim1,\n    MaxRowsAtCompileTime = RowsAtCompileTime,\n    MaxColsAtCompileTime = ColsAtCompileTime,\n    Flags = 0\n  };\n};\n\ntemplate<int Mode> struct transform_make_affine;\n\n} // end namespace internal\n\n/** \\geometry_module \\ingroup Geometry_Module\n  *\n  * \\class Transform\n  *\n  * \\brief Represents an homogeneous transformation in a N dimensional space\n  *\n  * \\tparam _Scalar the scalar type, i.e., the type of the coefficients\n  * \\tparam _Dim the dimension of the space\n  * \\tparam _Mode the type of the transformation. Can be:\n  *              - #Affine: the transformation is stored as a (Dim+1)^2 matrix,\n  *                         where the last row is assumed to be [0 ... 0 1].\n  *              - #AffineCompact: the transformation is stored as a (Dim)x(Dim+1) matrix.\n  *              - #Projective: the transformation is stored as a (Dim+1)^2 matrix\n  *                             without any assumption.\n  * \\tparam _Options has the same meaning as in class Matrix. It allows to specify DontAlign and/or RowMajor.\n  *                  These Options are passed directly to the underlying matrix type.\n  *\n  * The homography is internally represented and stored by a matrix which\n  * is available through the matrix() method. To understand the behavior of\n  * this class you have to think a Transform object as its internal\n  * matrix representation. The chosen convention is right multiply:\n  *\n  * \\code v' = T * v \\endcode\n  *\n  * Therefore, an affine transformation matrix M is shaped like this:\n  *\n  * \\f$ \\left( \\begin{array}{cc}\n  * linear & translation\\\\\n  * 0 ... 0 & 1\n  * \\end{array} \\right) \\f$\n  *\n  * Note that for a projective transformation the last row can be anything,\n  * and then the interpretation of different parts might be sightly different.\n  *\n  * However, unlike a plain matrix, the Transform class provides many features\n  * simplifying both its assembly and usage. In particular, it can be composed\n  * with any other transformations (Transform,Translation,RotationBase,DiagonalMatrix)\n  * and can be directly used to transform implicit homogeneous vectors. All these\n  * operations are handled via the operator*. For the composition of transformations,\n  * its principle consists to first convert the right/left hand sides of the product\n  * to a compatible (Dim+1)^2 matrix and then perform a pure matrix product.\n  * Of course, internally, operator* tries to perform the minimal number of operations\n  * according to the nature of each terms. Likewise, when applying the transform\n  * to points, the latters are automatically promoted to homogeneous vectors\n  * before doing the matrix product. The conventions to homogeneous representations\n  * are performed as follow:\n  *\n  * \\b Translation t (Dim)x(1):\n  * \\f$ \\left( \\begin{array}{cc}\n  * I & t \\\\\n  * 0\\,...\\,0 & 1\n  * \\end{array} \\right) \\f$\n  *\n  * \\b Rotation R (Dim)x(Dim):\n  * \\f$ \\left( \\begin{array}{cc}\n  * R & 0\\\\\n  * 0\\,...\\,0 & 1\n  * \\end{array} \\right) \\f$\n  *<!--\n  * \\b Linear \\b Matrix L (Dim)x(Dim):\n  * \\f$ \\left( \\begin{array}{cc}\n  * L & 0\\\\\n  * 0\\,...\\,0 & 1\n  * \\end{array} \\right) \\f$\n  *\n  * \\b Affine \\b Matrix A (Dim)x(Dim+1):\n  * \\f$ \\left( \\begin{array}{c}\n  * A\\\\\n  * 0\\,...\\,0\\,1\n  * \\end{array} \\right) \\f$\n  *-->\n  * \\b Scaling \\b DiagonalMatrix S (Dim)x(Dim):\n  * \\f$ \\left( \\begin{array}{cc}\n  * S & 0\\\\\n  * 0\\,...\\,0 & 1\n  * \\end{array} \\right) \\f$\n  *\n  * \\b Column \\b point v (Dim)x(1):\n  * \\f$ \\left( \\begin{array}{c}\n  * v\\\\\n  * 1\n  * \\end{array} \\right) \\f$\n  *\n  * \\b Set \\b of \\b column \\b points V1...Vn (Dim)x(n):\n  * \\f$ \\left( \\begin{array}{ccc}\n  * v_1 & ... & v_n\\\\\n  * 1 & ... & 1\n  * \\end{array} \\right) \\f$\n  *\n  * The concatenation of a Transform object with any kind of other transformation\n  * always returns a Transform object.\n  *\n  * A little exception to the \"as pure matrix product\" rule is the case of the\n  * transformation of non homogeneous vectors by an affine transformation. In\n  * that case the last matrix row can be ignored, and the product returns non\n  * homogeneous vectors.\n  *\n  * Since, for instance, a Dim x Dim matrix is interpreted as a linear transformation,\n  * it is not possible to directly transform Dim vectors stored in a Dim x Dim matrix.\n  * The solution is either to use a Dim x Dynamic matrix or explicitly request a\n  * vector transformation by making the vector homogeneous:\n  * \\code\n  * m' = T * m.colwise().homogeneous();\n  * \\endcode\n  * Note that there is zero overhead.\n  *\n  * Conversion methods from/to Qt's QMatrix and QTransform are available if the\n  * preprocessor token EIGEN_QT_SUPPORT is defined.\n  *\n  * This class can be extended with the help of the plugin mechanism described on the page\n  * \\ref TopicCustomizing_Plugins by defining the preprocessor symbol \\c EIGEN_TRANSFORM_PLUGIN.\n  *\n  * \\sa class Matrix, class Quaternion\n  */\ntemplate<typename _Scalar, int _Dim, int _Mode, int _Options>\nclass Transform\n{\npublic:\n  EIGEN_MAKE_ALIGNED_OPERATOR_NEW_IF_VECTORIZABLE_FIXED_SIZE(_Scalar,_Dim==Dynamic ? Dynamic : (_Dim+1)*(_Dim+1))\n  enum {\n    Mode = _Mode,\n    Options = _Options,\n    Dim = _Dim,     ///< space dimension in which the transformation holds\n    HDim = _Dim+1,  ///< size of a respective homogeneous vector\n    Rows = int(Mode)==(AffineCompact) ? Dim : HDim\n  };\n  /** the scalar type of the coefficients */\n  typedef _Scalar Scalar;\n  typedef Eigen::Index StorageIndex;\n  typedef Eigen::Index Index; ///< \\deprecated since Eigen 3.3\n  /** type of the matrix used to represent the transformation */\n  typedef typename internal::make_proper_matrix_type<Scalar,Rows,HDim,Options>::type MatrixType;\n  /** constified MatrixType */\n  typedef const MatrixType ConstMatrixType;\n  /** type of the matrix used to represent the linear part of the transformation */\n  typedef Matrix<Scalar,Dim,Dim,Options> LinearMatrixType;\n  /** type of read/write reference to the linear part of the transformation */\n  typedef Block<MatrixType,Dim,Dim,int(Mode)==(AffineCompact) && (Options&RowMajor)==0> LinearPart;\n  /** type of read reference to the linear part of the transformation */\n  typedef const Block<ConstMatrixType,Dim,Dim,int(Mode)==(AffineCompact) && (Options&RowMajor)==0> ConstLinearPart;\n  /** type of read/write reference to the affine part of the transformation */\n  typedef typename internal::conditional<int(Mode)==int(AffineCompact),\n                              MatrixType&,\n                              Block<MatrixType,Dim,HDim> >::type AffinePart;\n  /** type of read reference to the affine part of the transformation */\n  typedef typename internal::conditional<int(Mode)==int(AffineCompact),\n                              const MatrixType&,\n                              const Block<const MatrixType,Dim,HDim> >::type ConstAffinePart;\n  /** type of a vector */\n  typedef Matrix<Scalar,Dim,1> VectorType;\n  /** type of a read/write reference to the translation part of the rotation */\n  typedef Block<MatrixType,Dim,1,!(internal::traits<MatrixType>::Flags & RowMajorBit)> TranslationPart;\n  /** type of a read reference to the translation part of the rotation */\n  typedef const Block<ConstMatrixType,Dim,1,!(internal::traits<MatrixType>::Flags & RowMajorBit)> ConstTranslationPart;\n  /** corresponding translation type */\n  typedef Translation<Scalar,Dim> TranslationType;\n  \n  // this intermediate enum is needed to avoid an ICE with gcc 3.4 and 4.0\n  enum { TransformTimeDiagonalMode = ((Mode==int(Isometry))?Affine:int(Mode)) };\n  /** The return type of the product between a diagonal matrix and a transform */\n  typedef Transform<Scalar,Dim,TransformTimeDiagonalMode> TransformTimeDiagonalReturnType;\n\nprotected:\n\n  MatrixType m_matrix;\n\npublic:\n\n  /** Default constructor without initialization of the meaningful coefficients.\n    * If Mode==Affine, then the last row is set to [0 ... 0 1] */\n  EIGEN_DEVICE_FUNC inline Transform()\n  {\n    check_template_params();\n    internal::transform_make_affine<(int(Mode)==Affine) ? Affine : AffineCompact>::run(m_matrix);\n  }\n\n  EIGEN_DEVICE_FUNC inline Transform(const Transform& other)\n  {\n    check_template_params();\n    m_matrix = other.m_matrix;\n  }\n\n  EIGEN_DEVICE_FUNC inline explicit Transform(const TranslationType& t)\n  {\n    check_template_params();\n    *this = t;\n  }\n  EIGEN_DEVICE_FUNC inline explicit Transform(const UniformScaling<Scalar>& s)\n  {\n    check_template_params();\n    *this = s;\n  }\n  template<typename Derived>\n  EIGEN_DEVICE_FUNC inline explicit Transform(const RotationBase<Derived, Dim>& r)\n  {\n    check_template_params();\n    *this = r;\n  }\n\n  EIGEN_DEVICE_FUNC inline Transform& operator=(const Transform& other)\n  { m_matrix = other.m_matrix; return *this; }\n\n  typedef internal::transform_take_affine_part<Transform> take_affine_part;\n\n  /** Constructs and initializes a transformation from a Dim^2 or a (Dim+1)^2 matrix. */\n  template<typename OtherDerived>\n  EIGEN_DEVICE_FUNC inline explicit Transform(const EigenBase<OtherDerived>& other)\n  {\n    EIGEN_STATIC_ASSERT((internal::is_same<Scalar,typename OtherDerived::Scalar>::value),\n      YOU_MIXED_DIFFERENT_NUMERIC_TYPES__YOU_NEED_TO_USE_THE_CAST_METHOD_OF_MATRIXBASE_TO_CAST_NUMERIC_TYPES_EXPLICITLY);\n\n    check_template_params();\n    internal::transform_construct_from_matrix<OtherDerived,Mode,Options,Dim,HDim>::run(this, other.derived());\n  }\n\n  /** Set \\c *this from a Dim^2 or (Dim+1)^2 matrix. */\n  template<typename OtherDerived>\n  EIGEN_DEVICE_FUNC inline Transform& operator=(const EigenBase<OtherDerived>& other)\n  {\n    EIGEN_STATIC_ASSERT((internal::is_same<Scalar,typename OtherDerived::Scalar>::value),\n      YOU_MIXED_DIFFERENT_NUMERIC_TYPES__YOU_NEED_TO_USE_THE_CAST_METHOD_OF_MATRIXBASE_TO_CAST_NUMERIC_TYPES_EXPLICITLY);\n\n    internal::transform_construct_from_matrix<OtherDerived,Mode,Options,Dim,HDim>::run(this, other.derived());\n    return *this;\n  }\n  \n  template<int OtherOptions>\n  EIGEN_DEVICE_FUNC inline Transform(const Transform<Scalar,Dim,Mode,OtherOptions>& other)\n  {\n    check_template_params();\n    // only the options change, we can directly copy the matrices\n    m_matrix = other.matrix();\n  }\n\n  template<int OtherMode,int OtherOptions>\n  EIGEN_DEVICE_FUNC inline Transform(const Transform<Scalar,Dim,OtherMode,OtherOptions>& other)\n  {\n    check_template_params();\n    // prevent conversions as:\n    // Affine | AffineCompact | Isometry = Projective\n    EIGEN_STATIC_ASSERT(EIGEN_IMPLIES(OtherMode==int(Projective), Mode==int(Projective)),\n                        YOU_PERFORMED_AN_INVALID_TRANSFORMATION_CONVERSION)\n\n    // prevent conversions as:\n    // Isometry = Affine | AffineCompact\n    EIGEN_STATIC_ASSERT(EIGEN_IMPLIES(OtherMode==int(Affine)||OtherMode==int(AffineCompact), Mode!=int(Isometry)),\n                        YOU_PERFORMED_AN_INVALID_TRANSFORMATION_CONVERSION)\n\n    enum { ModeIsAffineCompact = Mode == int(AffineCompact),\n           OtherModeIsAffineCompact = OtherMode == int(AffineCompact)\n    };\n\n    if(ModeIsAffineCompact == OtherModeIsAffineCompact)\n    {\n      // We need the block expression because the code is compiled for all\n      // combinations of transformations and will trigger a compile time error\n      // if one tries to assign the matrices directly\n      m_matrix.template block<Dim,Dim+1>(0,0) = other.matrix().template block<Dim,Dim+1>(0,0);\n      makeAffine();\n    }\n    else if(OtherModeIsAffineCompact)\n    {\n      typedef typename Transform<Scalar,Dim,OtherMode,OtherOptions>::MatrixType OtherMatrixType;\n      internal::transform_construct_from_matrix<OtherMatrixType,Mode,Options,Dim,HDim>::run(this, other.matrix());\n    }\n    else\n    {\n      // here we know that Mode == AffineCompact and OtherMode != AffineCompact.\n      // if OtherMode were Projective, the static assert above would already have caught it.\n      // So the only possibility is that OtherMode == Affine\n      linear() = other.linear();\n      translation() = other.translation();\n    }\n  }\n\n  template<typename OtherDerived>\n  EIGEN_DEVICE_FUNC Transform(const ReturnByValue<OtherDerived>& other)\n  {\n    check_template_params();\n    other.evalTo(*this);\n  }\n\n  template<typename OtherDerived>\n  EIGEN_DEVICE_FUNC Transform& operator=(const ReturnByValue<OtherDerived>& other)\n  {\n    other.evalTo(*this);\n    return *this;\n  }\n\n  #ifdef EIGEN_QT_SUPPORT\n  inline Transform(const QMatrix& other);\n  inline Transform& operator=(const QMatrix& other);\n  inline QMatrix toQMatrix(void) const;\n  inline Transform(const QTransform& other);\n  inline Transform& operator=(const QTransform& other);\n  inline QTransform toQTransform(void) const;\n  #endif\n  \n  EIGEN_DEVICE_FUNC Index rows() const { return int(Mode)==int(Projective) ? m_matrix.cols() : (m_matrix.cols()-1); }\n  EIGEN_DEVICE_FUNC Index cols() const { return m_matrix.cols(); }\n\n  /** shortcut for m_matrix(row,col);\n    * \\sa MatrixBase::operator(Index,Index) const */\n  EIGEN_DEVICE_FUNC inline Scalar operator() (Index row, Index col) const { return m_matrix(row,col); }\n  /** shortcut for m_matrix(row,col);\n    * \\sa MatrixBase::operator(Index,Index) */\n  EIGEN_DEVICE_FUNC inline Scalar& operator() (Index row, Index col) { return m_matrix(row,col); }\n\n  /** \\returns a read-only expression of the transformation matrix */\n  EIGEN_DEVICE_FUNC inline const MatrixType& matrix() const { return m_matrix; }\n  /** \\returns a writable expression of the transformation matrix */\n  EIGEN_DEVICE_FUNC inline MatrixType& matrix() { return m_matrix; }\n\n  /** \\returns a read-only expression of the linear part of the transformation */\n  EIGEN_DEVICE_FUNC inline ConstLinearPart linear() const { return ConstLinearPart(m_matrix,0,0); }\n  /** \\returns a writable expression of the linear part of the transformation */\n  EIGEN_DEVICE_FUNC inline LinearPart linear() { return LinearPart(m_matrix,0,0); }\n\n  /** \\returns a read-only expression of the Dim x HDim affine part of the transformation */\n  EIGEN_DEVICE_FUNC inline ConstAffinePart affine() const { return take_affine_part::run(m_matrix); }\n  /** \\returns a writable expression of the Dim x HDim affine part of the transformation */\n  EIGEN_DEVICE_FUNC inline AffinePart affine() { return take_affine_part::run(m_matrix); }\n\n  /** \\returns a read-only expression of the translation vector of the transformation */\n  EIGEN_DEVICE_FUNC inline ConstTranslationPart translation() const { return ConstTranslationPart(m_matrix,0,Dim); }\n  /** \\returns a writable expression of the translation vector of the transformation */\n  EIGEN_DEVICE_FUNC inline TranslationPart translation() { return TranslationPart(m_matrix,0,Dim); }\n\n  /** \\returns an expression of the product between the transform \\c *this and a matrix expression \\a other.\n    *\n    * The right-hand-side \\a other can be either:\n    * \\li an homogeneous vector of size Dim+1,\n    * \\li a set of homogeneous vectors of size Dim+1 x N,\n    * \\li a transformation matrix of size Dim+1 x Dim+1.\n    *\n    * Moreover, if \\c *this represents an affine transformation (i.e., Mode!=Projective), then \\a other can also be:\n    * \\li a point of size Dim (computes: \\code this->linear() * other + this->translation()\\endcode),\n    * \\li a set of N points as a Dim x N matrix (computes: \\code (this->linear() * other).colwise() + this->translation()\\endcode),\n    *\n    * In all cases, the return type is a matrix or vector of same sizes as the right-hand-side \\a other.\n    *\n    * If you want to interpret \\a other as a linear or affine transformation, then first convert it to a Transform<> type,\n    * or do your own cooking.\n    *\n    * Finally, if you want to apply Affine transformations to vectors, then explicitly apply the linear part only:\n    * \\code\n    * Affine3f A;\n    * Vector3f v1, v2;\n    * v2 = A.linear() * v1;\n    * \\endcode\n    *\n    */\n  // note: this function is defined here because some compilers cannot find the respective declaration\n  template<typename OtherDerived>\n  EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const typename internal::transform_right_product_impl<Transform, OtherDerived>::ResultType\n  operator * (const EigenBase<OtherDerived> &other) const\n  { return internal::transform_right_product_impl<Transform, OtherDerived>::run(*this,other.derived()); }\n\n  /** \\returns the product expression of a transformation matrix \\a a times a transform \\a b\n    *\n    * The left hand side \\a other can be either:\n    * \\li a linear transformation matrix of size Dim x Dim,\n    * \\li an affine transformation matrix of size Dim x Dim+1,\n    * \\li a general transformation matrix of size Dim+1 x Dim+1.\n    */\n  template<typename OtherDerived> friend\n  EIGEN_DEVICE_FUNC inline const typename internal::transform_left_product_impl<OtherDerived,Mode,Options,_Dim,_Dim+1>::ResultType\n    operator * (const EigenBase<OtherDerived> &a, const Transform &b)\n  { return internal::transform_left_product_impl<OtherDerived,Mode,Options,Dim,HDim>::run(a.derived(),b); }\n\n  /** \\returns The product expression of a transform \\a a times a diagonal matrix \\a b\n    *\n    * The rhs diagonal matrix is interpreted as an affine scaling transformation. The\n    * product results in a Transform of the same type (mode) as the lhs only if the lhs \n    * mode is no isometry. In that case, the returned transform is an affinity.\n    */\n  template<typename DiagonalDerived>\n  EIGEN_DEVICE_FUNC inline const TransformTimeDiagonalReturnType\n    operator * (const DiagonalBase<DiagonalDerived> &b) const\n  {\n    TransformTimeDiagonalReturnType res(*this);\n    res.linearExt() *= b;\n    return res;\n  }\n\n  /** \\returns The product expression of a diagonal matrix \\a a times a transform \\a b\n    *\n    * The lhs diagonal matrix is interpreted as an affine scaling transformation. The\n    * product results in a Transform of the same type (mode) as the lhs only if the lhs \n    * mode is no isometry. In that case, the returned transform is an affinity.\n    */\n  template<typename DiagonalDerived>\n  EIGEN_DEVICE_FUNC friend inline TransformTimeDiagonalReturnType\n    operator * (const DiagonalBase<DiagonalDerived> &a, const Transform &b)\n  {\n    TransformTimeDiagonalReturnType res;\n    res.linear().noalias() = a*b.linear();\n    res.translation().noalias() = a*b.translation();\n    if (Mode!=int(AffineCompact))\n      res.matrix().row(Dim) = b.matrix().row(Dim);\n    return res;\n  }\n\n  template<typename OtherDerived>\n  EIGEN_DEVICE_FUNC inline Transform& operator*=(const EigenBase<OtherDerived>& other) { return *this = *this * other; }\n\n  /** Concatenates two transformations */\n  EIGEN_DEVICE_FUNC inline const Transform operator * (const Transform& other) const\n  {\n    return internal::transform_transform_product_impl<Transform,Transform>::run(*this,other);\n  }\n  \n  #if EIGEN_COMP_ICC\nprivate:\n  // this intermediate structure permits to workaround a bug in ICC 11:\n  //   error: template instantiation resulted in unexpected function type of \"Eigen::Transform<double, 3, 32, 0>\n  //             (const Eigen::Transform<double, 3, 2, 0> &) const\"\n  //  (the meaning of a name may have changed since the template declaration -- the type of the template is:\n  // \"Eigen::internal::transform_transform_product_impl<Eigen::Transform<double, 3, 32, 0>,\n  //     Eigen::Transform<double, 3, Mode, Options>, <expression>>::ResultType (const Eigen::Transform<double, 3, Mode, Options> &) const\")\n  // \n  template<int OtherMode,int OtherOptions> struct icc_11_workaround\n  {\n    typedef internal::transform_transform_product_impl<Transform,Transform<Scalar,Dim,OtherMode,OtherOptions> > ProductType;\n    typedef typename ProductType::ResultType ResultType;\n  };\n  \npublic:\n  /** Concatenates two different transformations */\n  template<int OtherMode,int OtherOptions>\n  inline typename icc_11_workaround<OtherMode,OtherOptions>::ResultType\n    operator * (const Transform<Scalar,Dim,OtherMode,OtherOptions>& other) const\n  {\n    typedef typename icc_11_workaround<OtherMode,OtherOptions>::ProductType ProductType;\n    return ProductType::run(*this,other);\n  }\n  #else\n  /** Concatenates two different transformations */\n  template<int OtherMode,int OtherOptions>\n  EIGEN_DEVICE_FUNC inline typename internal::transform_transform_product_impl<Transform,Transform<Scalar,Dim,OtherMode,OtherOptions> >::ResultType\n    operator * (const Transform<Scalar,Dim,OtherMode,OtherOptions>& other) const\n  {\n    return internal::transform_transform_product_impl<Transform,Transform<Scalar,Dim,OtherMode,OtherOptions> >::run(*this,other);\n  }\n  #endif\n\n  /** \\sa MatrixBase::setIdentity() */\n  EIGEN_DEVICE_FUNC void setIdentity() { m_matrix.setIdentity(); }\n\n  /**\n   * \\brief Returns an identity transformation.\n   * \\todo In the future this function should be returning a Transform expression.\n   */\n  EIGEN_DEVICE_FUNC static const Transform Identity()\n  {\n    return Transform(MatrixType::Identity());\n  }\n\n  template<typename OtherDerived>\n  EIGEN_DEVICE_FUNC \n  inline Transform& scale(const MatrixBase<OtherDerived> &other);\n\n  template<typename OtherDerived>\n  EIGEN_DEVICE_FUNC\n  inline Transform& prescale(const MatrixBase<OtherDerived> &other);\n\n  EIGEN_DEVICE_FUNC inline Transform& scale(const Scalar& s);\n  EIGEN_DEVICE_FUNC inline Transform& prescale(const Scalar& s);\n\n  template<typename OtherDerived>\n  EIGEN_DEVICE_FUNC\n  inline Transform& translate(const MatrixBase<OtherDerived> &other);\n\n  template<typename OtherDerived>\n  EIGEN_DEVICE_FUNC\n  inline Transform& pretranslate(const MatrixBase<OtherDerived> &other);\n\n  template<typename RotationType>\n  EIGEN_DEVICE_FUNC\n  inline Transform& rotate(const RotationType& rotation);\n\n  template<typename RotationType>\n  EIGEN_DEVICE_FUNC\n  inline Transform& prerotate(const RotationType& rotation);\n\n  EIGEN_DEVICE_FUNC Transform& shear(const Scalar& sx, const Scalar& sy);\n  EIGEN_DEVICE_FUNC Transform& preshear(const Scalar& sx, const Scalar& sy);\n\n  EIGEN_DEVICE_FUNC inline Transform& operator=(const TranslationType& t);\n  \n  EIGEN_DEVICE_FUNC\n  inline Transform& operator*=(const TranslationType& t) { return translate(t.vector()); }\n  \n  EIGEN_DEVICE_FUNC inline Transform operator*(const TranslationType& t) const;\n\n  EIGEN_DEVICE_FUNC \n  inline Transform& operator=(const UniformScaling<Scalar>& t);\n  \n  EIGEN_DEVICE_FUNC\n  inline Transform& operator*=(const UniformScaling<Scalar>& s) { return scale(s.factor()); }\n  \n  EIGEN_DEVICE_FUNC\n  inline TransformTimeDiagonalReturnType operator*(const UniformScaling<Scalar>& s) const\n  {\n    TransformTimeDiagonalReturnType res = *this;\n    res.scale(s.factor());\n    return res;\n  }\n\n  EIGEN_DEVICE_FUNC\n  inline Transform& operator*=(const DiagonalMatrix<Scalar,Dim>& s) { linearExt() *= s; return *this; }\n\n  template<typename Derived>\n  EIGEN_DEVICE_FUNC inline Transform& operator=(const RotationBase<Derived,Dim>& r);\n  template<typename Derived>\n  EIGEN_DEVICE_FUNC inline Transform& operator*=(const RotationBase<Derived,Dim>& r) { return rotate(r.toRotationMatrix()); }\n  template<typename Derived>\n  EIGEN_DEVICE_FUNC inline Transform operator*(const RotationBase<Derived,Dim>& r) const;\n\n  EIGEN_DEVICE_FUNC const LinearMatrixType rotation() const;\n  template<typename RotationMatrixType, typename ScalingMatrixType>\n  EIGEN_DEVICE_FUNC\n  void computeRotationScaling(RotationMatrixType *rotation, ScalingMatrixType *scaling) const;\n  template<typename ScalingMatrixType, typename RotationMatrixType>\n  EIGEN_DEVICE_FUNC\n  void computeScalingRotation(ScalingMatrixType *scaling, RotationMatrixType *rotation) const;\n\n  template<typename PositionDerived, typename OrientationType, typename ScaleDerived>\n  EIGEN_DEVICE_FUNC\n  Transform& fromPositionOrientationScale(const MatrixBase<PositionDerived> &position,\n    const OrientationType& orientation, const MatrixBase<ScaleDerived> &scale);\n\n  EIGEN_DEVICE_FUNC\n  inline Transform inverse(TransformTraits traits = (TransformTraits)Mode) const;\n\n  /** \\returns a const pointer to the column major internal matrix */\n  EIGEN_DEVICE_FUNC const Scalar* data() const { return m_matrix.data(); }\n  /** \\returns a non-const pointer to the column major internal matrix */\n  EIGEN_DEVICE_FUNC Scalar* data() { return m_matrix.data(); }\n\n  /** \\returns \\c *this with scalar type casted to \\a NewScalarType\n    *\n    * Note that if \\a NewScalarType is equal to the current scalar type of \\c *this\n    * then this function smartly returns a const reference to \\c *this.\n    */\n  template<typename NewScalarType>\n  EIGEN_DEVICE_FUNC inline typename internal::cast_return_type<Transform,Transform<NewScalarType,Dim,Mode,Options> >::type cast() const\n  { return typename internal::cast_return_type<Transform,Transform<NewScalarType,Dim,Mode,Options> >::type(*this); }\n\n  /** Copy constructor with scalar type conversion */\n  template<typename OtherScalarType>\n  EIGEN_DEVICE_FUNC inline explicit Transform(const Transform<OtherScalarType,Dim,Mode,Options>& other)\n  {\n    check_template_params();\n    m_matrix = other.matrix().template cast<Scalar>();\n  }\n\n  /** \\returns \\c true if \\c *this is approximately equal to \\a other, within the precision\n    * determined by \\a prec.\n    *\n    * \\sa MatrixBase::isApprox() */\n  EIGEN_DEVICE_FUNC bool isApprox(const Transform& other, const typename NumTraits<Scalar>::Real& prec = NumTraits<Scalar>::dummy_precision()) const\n  { return m_matrix.isApprox(other.m_matrix, prec); }\n\n  /** Sets the last row to [0 ... 0 1]\n    */\n  EIGEN_DEVICE_FUNC void makeAffine()\n  {\n    internal::transform_make_affine<int(Mode)>::run(m_matrix);\n  }\n\n  /** \\internal\n    * \\returns the Dim x Dim linear part if the transformation is affine,\n    *          and the HDim x Dim part for projective transformations.\n    */\n  EIGEN_DEVICE_FUNC inline Block<MatrixType,int(Mode)==int(Projective)?HDim:Dim,Dim> linearExt()\n  { return m_matrix.template block<int(Mode)==int(Projective)?HDim:Dim,Dim>(0,0); }\n  /** \\internal\n    * \\returns the Dim x Dim linear part if the transformation is affine,\n    *          and the HDim x Dim part for projective transformations.\n    */\n  EIGEN_DEVICE_FUNC inline const Block<MatrixType,int(Mode)==int(Projective)?HDim:Dim,Dim> linearExt() const\n  { return m_matrix.template block<int(Mode)==int(Projective)?HDim:Dim,Dim>(0,0); }\n\n  /** \\internal\n    * \\returns the translation part if the transformation is affine,\n    *          and the last column for projective transformations.\n    */\n  EIGEN_DEVICE_FUNC inline Block<MatrixType,int(Mode)==int(Projective)?HDim:Dim,1> translationExt()\n  { return m_matrix.template block<int(Mode)==int(Projective)?HDim:Dim,1>(0,Dim); }\n  /** \\internal\n    * \\returns the translation part if the transformation is affine,\n    *          and the last column for projective transformations.\n    */\n  EIGEN_DEVICE_FUNC inline const Block<MatrixType,int(Mode)==int(Projective)?HDim:Dim,1> translationExt() const\n  { return m_matrix.template block<int(Mode)==int(Projective)?HDim:Dim,1>(0,Dim); }\n\n\n  #ifdef EIGEN_TRANSFORM_PLUGIN\n  #include EIGEN_TRANSFORM_PLUGIN\n  #endif\n  \nprotected:\n  #ifndef EIGEN_PARSED_BY_DOXYGEN\n    EIGEN_DEVICE_FUNC static EIGEN_STRONG_INLINE void check_template_params()\n    {\n      EIGEN_STATIC_ASSERT((Options & (DontAlign|RowMajor)) == Options, INVALID_MATRIX_TEMPLATE_PARAMETERS)\n    }\n  #endif\n\n};\n\n/** \\ingroup Geometry_Module */\ntypedef Transform<float,2,Isometry> Isometry2f;\n/** \\ingroup Geometry_Module */\ntypedef Transform<float,3,Isometry> Isometry3f;\n/** \\ingroup Geometry_Module */\ntypedef Transform<double,2,Isometry> Isometry2d;\n/** \\ingroup Geometry_Module */\ntypedef Transform<double,3,Isometry> Isometry3d;\n\n/** \\ingroup Geometry_Module */\ntypedef Transform<float,2,Affine> Affine2f;\n/** \\ingroup Geometry_Module */\ntypedef Transform<float,3,Affine> Affine3f;\n/** \\ingroup Geometry_Module */\ntypedef Transform<double,2,Affine> Affine2d;\n/** \\ingroup Geometry_Module */\ntypedef Transform<double,3,Affine> Affine3d;\n\n/** \\ingroup Geometry_Module */\ntypedef Transform<float,2,AffineCompact> AffineCompact2f;\n/** \\ingroup Geometry_Module */\ntypedef Transform<float,3,AffineCompact> AffineCompact3f;\n/** \\ingroup Geometry_Module */\ntypedef Transform<double,2,AffineCompact> AffineCompact2d;\n/** \\ingroup Geometry_Module */\ntypedef Transform<double,3,AffineCompact> AffineCompact3d;\n\n/** \\ingroup Geometry_Module */\ntypedef Transform<float,2,Projective> Projective2f;\n/** \\ingroup Geometry_Module */\ntypedef Transform<float,3,Projective> Projective3f;\n/** \\ingroup Geometry_Module */\ntypedef Transform<double,2,Projective> Projective2d;\n/** \\ingroup Geometry_Module */\ntypedef Transform<double,3,Projective> Projective3d;\n\n/**************************\n*** Optional QT support ***\n**************************/\n\n#ifdef EIGEN_QT_SUPPORT\n/** Initializes \\c *this from a QMatrix assuming the dimension is 2.\n  *\n  * This function is available only if the token EIGEN_QT_SUPPORT is defined.\n  */\ntemplate<typename Scalar, int Dim, int Mode,int Options>\nTransform<Scalar,Dim,Mode,Options>::Transform(const QMatrix& other)\n{\n  check_template_params();\n  *this = other;\n}\n\n/** Set \\c *this from a QMatrix assuming the dimension is 2.\n  *\n  * This function is available only if the token EIGEN_QT_SUPPORT is defined.\n  */\ntemplate<typename Scalar, int Dim, int Mode,int Options>\nTransform<Scalar,Dim,Mode,Options>& Transform<Scalar,Dim,Mode,Options>::operator=(const QMatrix& other)\n{\n  EIGEN_STATIC_ASSERT(Dim==2, YOU_MADE_A_PROGRAMMING_MISTAKE)\n  if (Mode == int(AffineCompact))\n    m_matrix << other.m11(), other.m21(), other.dx(),\n                other.m12(), other.m22(), other.dy();\n  else\n    m_matrix << other.m11(), other.m21(), other.dx(),\n                other.m12(), other.m22(), other.dy(),\n                0, 0, 1;\n  return *this;\n}\n\n/** \\returns a QMatrix from \\c *this assuming the dimension is 2.\n  *\n  * \\warning this conversion might loss data if \\c *this is not affine\n  *\n  * This function is available only if the token EIGEN_QT_SUPPORT is defined.\n  */\ntemplate<typename Scalar, int Dim, int Mode, int Options>\nQMatrix Transform<Scalar,Dim,Mode,Options>::toQMatrix(void) const\n{\n  check_template_params();\n  EIGEN_STATIC_ASSERT(Dim==2, YOU_MADE_A_PROGRAMMING_MISTAKE)\n  return QMatrix(m_matrix.coeff(0,0), m_matrix.coeff(1,0),\n                 m_matrix.coeff(0,1), m_matrix.coeff(1,1),\n                 m_matrix.coeff(0,2), m_matrix.coeff(1,2));\n}\n\n/** Initializes \\c *this from a QTransform assuming the dimension is 2.\n  *\n  * This function is available only if the token EIGEN_QT_SUPPORT is defined.\n  */\ntemplate<typename Scalar, int Dim, int Mode,int Options>\nTransform<Scalar,Dim,Mode,Options>::Transform(const QTransform& other)\n{\n  check_template_params();\n  *this = other;\n}\n\n/** Set \\c *this from a QTransform assuming the dimension is 2.\n  *\n  * This function is available only if the token EIGEN_QT_SUPPORT is defined.\n  */\ntemplate<typename Scalar, int Dim, int Mode, int Options>\nTransform<Scalar,Dim,Mode,Options>& Transform<Scalar,Dim,Mode,Options>::operator=(const QTransform& other)\n{\n  check_template_params();\n  EIGEN_STATIC_ASSERT(Dim==2, YOU_MADE_A_PROGRAMMING_MISTAKE)\n  if (Mode == int(AffineCompact))\n    m_matrix << other.m11(), other.m21(), other.dx(),\n                other.m12(), other.m22(), other.dy();\n  else\n    m_matrix << other.m11(), other.m21(), other.dx(),\n                other.m12(), other.m22(), other.dy(),\n                other.m13(), other.m23(), other.m33();\n  return *this;\n}\n\n/** \\returns a QTransform from \\c *this assuming the dimension is 2.\n  *\n  * This function is available only if the token EIGEN_QT_SUPPORT is defined.\n  */\ntemplate<typename Scalar, int Dim, int Mode, int Options>\nQTransform Transform<Scalar,Dim,Mode,Options>::toQTransform(void) const\n{\n  EIGEN_STATIC_ASSERT(Dim==2, YOU_MADE_A_PROGRAMMING_MISTAKE)\n  if (Mode == int(AffineCompact))\n    return QTransform(m_matrix.coeff(0,0), m_matrix.coeff(1,0),\n                      m_matrix.coeff(0,1), m_matrix.coeff(1,1),\n                      m_matrix.coeff(0,2), m_matrix.coeff(1,2));\n  else\n    return QTransform(m_matrix.coeff(0,0), m_matrix.coeff(1,0), m_matrix.coeff(2,0),\n                      m_matrix.coeff(0,1), m_matrix.coeff(1,1), m_matrix.coeff(2,1),\n                      m_matrix.coeff(0,2), m_matrix.coeff(1,2), m_matrix.coeff(2,2));\n}\n#endif\n\n/*********************\n*** Procedural API ***\n*********************/\n\n/** Applies on the right the non uniform scale transformation represented\n  * by the vector \\a other to \\c *this and returns a reference to \\c *this.\n  * \\sa prescale()\n  */\ntemplate<typename Scalar, int Dim, int Mode, int Options>\ntemplate<typename OtherDerived>\nEIGEN_DEVICE_FUNC Transform<Scalar,Dim,Mode,Options>&\nTransform<Scalar,Dim,Mode,Options>::scale(const MatrixBase<OtherDerived> &other)\n{\n  EIGEN_STATIC_ASSERT_VECTOR_SPECIFIC_SIZE(OtherDerived,int(Dim))\n  EIGEN_STATIC_ASSERT(Mode!=int(Isometry), THIS_METHOD_IS_ONLY_FOR_SPECIFIC_TRANSFORMATIONS)\n  linearExt().noalias() = (linearExt() * other.asDiagonal());\n  return *this;\n}\n\n/** Applies on the right a uniform scale of a factor \\a c to \\c *this\n  * and returns a reference to \\c *this.\n  * \\sa prescale(Scalar)\n  */\ntemplate<typename Scalar, int Dim, int Mode, int Options>\nEIGEN_DEVICE_FUNC inline Transform<Scalar,Dim,Mode,Options>& Transform<Scalar,Dim,Mode,Options>::scale(const Scalar& s)\n{\n  EIGEN_STATIC_ASSERT(Mode!=int(Isometry), THIS_METHOD_IS_ONLY_FOR_SPECIFIC_TRANSFORMATIONS)\n  linearExt() *= s;\n  return *this;\n}\n\n/** Applies on the left the non uniform scale transformation represented\n  * by the vector \\a other to \\c *this and returns a reference to \\c *this.\n  * \\sa scale()\n  */\ntemplate<typename Scalar, int Dim, int Mode, int Options>\ntemplate<typename OtherDerived>\nEIGEN_DEVICE_FUNC Transform<Scalar,Dim,Mode,Options>&\nTransform<Scalar,Dim,Mode,Options>::prescale(const MatrixBase<OtherDerived> &other)\n{\n  EIGEN_STATIC_ASSERT_VECTOR_SPECIFIC_SIZE(OtherDerived,int(Dim))\n  EIGEN_STATIC_ASSERT(Mode!=int(Isometry), THIS_METHOD_IS_ONLY_FOR_SPECIFIC_TRANSFORMATIONS)\n  affine().noalias() = (other.asDiagonal() * affine());\n  return *this;\n}\n\n/** Applies on the left a uniform scale of a factor \\a c to \\c *this\n  * and returns a reference to \\c *this.\n  * \\sa scale(Scalar)\n  */\ntemplate<typename Scalar, int Dim, int Mode, int Options>\nEIGEN_DEVICE_FUNC inline Transform<Scalar,Dim,Mode,Options>& Transform<Scalar,Dim,Mode,Options>::prescale(const Scalar& s)\n{\n  EIGEN_STATIC_ASSERT(Mode!=int(Isometry), THIS_METHOD_IS_ONLY_FOR_SPECIFIC_TRANSFORMATIONS)\n  m_matrix.template topRows<Dim>() *= s;\n  return *this;\n}\n\n/** Applies on the right the translation matrix represented by the vector \\a other\n  * to \\c *this and returns a reference to \\c *this.\n  * \\sa pretranslate()\n  */\ntemplate<typename Scalar, int Dim, int Mode, int Options>\ntemplate<typename OtherDerived>\nEIGEN_DEVICE_FUNC Transform<Scalar,Dim,Mode,Options>&\nTransform<Scalar,Dim,Mode,Options>::translate(const MatrixBase<OtherDerived> &other)\n{\n  EIGEN_STATIC_ASSERT_VECTOR_SPECIFIC_SIZE(OtherDerived,int(Dim))\n  translationExt() += linearExt() * other;\n  return *this;\n}\n\n/** Applies on the left the translation matrix represented by the vector \\a other\n  * to \\c *this and returns a reference to \\c *this.\n  * \\sa translate()\n  */\ntemplate<typename Scalar, int Dim, int Mode, int Options>\ntemplate<typename OtherDerived>\nEIGEN_DEVICE_FUNC Transform<Scalar,Dim,Mode,Options>&\nTransform<Scalar,Dim,Mode,Options>::pretranslate(const MatrixBase<OtherDerived> &other)\n{\n  EIGEN_STATIC_ASSERT_VECTOR_SPECIFIC_SIZE(OtherDerived,int(Dim))\n  if(int(Mode)==int(Projective))\n    affine() += other * m_matrix.row(Dim);\n  else\n    translation() += other;\n  return *this;\n}\n\n/** Applies on the right the rotation represented by the rotation \\a rotation\n  * to \\c *this and returns a reference to \\c *this.\n  *\n  * The template parameter \\a RotationType is the type of the rotation which\n  * must be known by internal::toRotationMatrix<>.\n  *\n  * Natively supported types includes:\n  *   - any scalar (2D),\n  *   - a Dim x Dim matrix expression,\n  *   - a Quaternion (3D),\n  *   - a AngleAxis (3D)\n  *\n  * This mechanism is easily extendable to support user types such as Euler angles,\n  * or a pair of Quaternion for 4D rotations.\n  *\n  * \\sa rotate(Scalar), class Quaternion, class AngleAxis, prerotate(RotationType)\n  */\ntemplate<typename Scalar, int Dim, int Mode, int Options>\ntemplate<typename RotationType>\nEIGEN_DEVICE_FUNC Transform<Scalar,Dim,Mode,Options>&\nTransform<Scalar,Dim,Mode,Options>::rotate(const RotationType& rotation)\n{\n  linearExt() *= internal::toRotationMatrix<Scalar,Dim>(rotation);\n  return *this;\n}\n\n/** Applies on the left the rotation represented by the rotation \\a rotation\n  * to \\c *this and returns a reference to \\c *this.\n  *\n  * See rotate() for further details.\n  *\n  * \\sa rotate()\n  */\ntemplate<typename Scalar, int Dim, int Mode, int Options>\ntemplate<typename RotationType>\nEIGEN_DEVICE_FUNC Transform<Scalar,Dim,Mode,Options>&\nTransform<Scalar,Dim,Mode,Options>::prerotate(const RotationType& rotation)\n{\n  m_matrix.template block<Dim,HDim>(0,0) = internal::toRotationMatrix<Scalar,Dim>(rotation)\n                                         * m_matrix.template block<Dim,HDim>(0,0);\n  return *this;\n}\n\n/** Applies on the right the shear transformation represented\n  * by the vector \\a other to \\c *this and returns a reference to \\c *this.\n  * \\warning 2D only.\n  * \\sa preshear()\n  */\ntemplate<typename Scalar, int Dim, int Mode, int Options>\nEIGEN_DEVICE_FUNC Transform<Scalar,Dim,Mode,Options>&\nTransform<Scalar,Dim,Mode,Options>::shear(const Scalar& sx, const Scalar& sy)\n{\n  EIGEN_STATIC_ASSERT(int(Dim)==2, YOU_MADE_A_PROGRAMMING_MISTAKE)\n  EIGEN_STATIC_ASSERT(Mode!=int(Isometry), THIS_METHOD_IS_ONLY_FOR_SPECIFIC_TRANSFORMATIONS)\n  VectorType tmp = linear().col(0)*sy + linear().col(1);\n  linear() << linear().col(0) + linear().col(1)*sx, tmp;\n  return *this;\n}\n\n/** Applies on the left the shear transformation represented\n  * by the vector \\a other to \\c *this and returns a reference to \\c *this.\n  * \\warning 2D only.\n  * \\sa shear()\n  */\ntemplate<typename Scalar, int Dim, int Mode, int Options>\nEIGEN_DEVICE_FUNC Transform<Scalar,Dim,Mode,Options>&\nTransform<Scalar,Dim,Mode,Options>::preshear(const Scalar& sx, const Scalar& sy)\n{\n  EIGEN_STATIC_ASSERT(int(Dim)==2, YOU_MADE_A_PROGRAMMING_MISTAKE)\n  EIGEN_STATIC_ASSERT(Mode!=int(Isometry), THIS_METHOD_IS_ONLY_FOR_SPECIFIC_TRANSFORMATIONS)\n  m_matrix.template block<Dim,HDim>(0,0) = LinearMatrixType(1, sx, sy, 1) * m_matrix.template block<Dim,HDim>(0,0);\n  return *this;\n}\n\n/******************************************************\n*** Scaling, Translation and Rotation compatibility ***\n******************************************************/\n\ntemplate<typename Scalar, int Dim, int Mode, int Options>\nEIGEN_DEVICE_FUNC inline Transform<Scalar,Dim,Mode,Options>& Transform<Scalar,Dim,Mode,Options>::operator=(const TranslationType& t)\n{\n  linear().setIdentity();\n  translation() = t.vector();\n  makeAffine();\n  return *this;\n}\n\ntemplate<typename Scalar, int Dim, int Mode, int Options>\nEIGEN_DEVICE_FUNC inline Transform<Scalar,Dim,Mode,Options> Transform<Scalar,Dim,Mode,Options>::operator*(const TranslationType& t) const\n{\n  Transform res = *this;\n  res.translate(t.vector());\n  return res;\n}\n\ntemplate<typename Scalar, int Dim, int Mode, int Options>\nEIGEN_DEVICE_FUNC inline Transform<Scalar,Dim,Mode,Options>& Transform<Scalar,Dim,Mode,Options>::operator=(const UniformScaling<Scalar>& s)\n{\n  m_matrix.setZero();\n  linear().diagonal().fill(s.factor());\n  makeAffine();\n  return *this;\n}\n\ntemplate<typename Scalar, int Dim, int Mode, int Options>\ntemplate<typename Derived>\nEIGEN_DEVICE_FUNC inline Transform<Scalar,Dim,Mode,Options>& Transform<Scalar,Dim,Mode,Options>::operator=(const RotationBase<Derived,Dim>& r)\n{\n  linear() = internal::toRotationMatrix<Scalar,Dim>(r);\n  translation().setZero();\n  makeAffine();\n  return *this;\n}\n\ntemplate<typename Scalar, int Dim, int Mode, int Options>\ntemplate<typename Derived>\nEIGEN_DEVICE_FUNC inline Transform<Scalar,Dim,Mode,Options> Transform<Scalar,Dim,Mode,Options>::operator*(const RotationBase<Derived,Dim>& r) const\n{\n  Transform res = *this;\n  res.rotate(r.derived());\n  return res;\n}\n\n/************************\n*** Special functions ***\n************************/\n\n/** \\returns the rotation part of the transformation\n  *\n  *\n  * \\svd_module\n  *\n  * \\sa computeRotationScaling(), computeScalingRotation(), class SVD\n  */\ntemplate<typename Scalar, int Dim, int Mode, int Options>\nEIGEN_DEVICE_FUNC const typename Transform<Scalar,Dim,Mode,Options>::LinearMatrixType\nTransform<Scalar,Dim,Mode,Options>::rotation() const\n{\n  LinearMatrixType result;\n  computeRotationScaling(&result, (LinearMatrixType*)0);\n  return result;\n}\n\n\n/** decomposes the linear part of the transformation as a product rotation x scaling, the scaling being\n  * not necessarily positive.\n  *\n  * If either pointer is zero, the corresponding computation is skipped.\n  *\n  *\n  *\n  * \\svd_module\n  *\n  * \\sa computeScalingRotation(), rotation(), class SVD\n  */\ntemplate<typename Scalar, int Dim, int Mode, int Options>\ntemplate<typename RotationMatrixType, typename ScalingMatrixType>\nEIGEN_DEVICE_FUNC void Transform<Scalar,Dim,Mode,Options>::computeRotationScaling(RotationMatrixType *rotation, ScalingMatrixType *scaling) const\n{\n  JacobiSVD<LinearMatrixType> svd(linear(), ComputeFullU | ComputeFullV);\n\n  Scalar x = (svd.matrixU() * svd.matrixV().adjoint()).determinant(); // so x has absolute value 1\n  VectorType sv(svd.singularValues());\n  sv.coeffRef(0) *= x;\n  if(scaling) scaling->lazyAssign(svd.matrixV() * sv.asDiagonal() * svd.matrixV().adjoint());\n  if(rotation)\n  {\n    LinearMatrixType m(svd.matrixU());\n    m.col(0) /= x;\n    rotation->lazyAssign(m * svd.matrixV().adjoint());\n  }\n}\n\n/** decomposes the linear part of the transformation as a product scaling x rotation, the scaling being\n  * not necessarily positive.\n  *\n  * If either pointer is zero, the corresponding computation is skipped.\n  *\n  *\n  *\n  * \\svd_module\n  *\n  * \\sa computeRotationScaling(), rotation(), class SVD\n  */\ntemplate<typename Scalar, int Dim, int Mode, int Options>\ntemplate<typename ScalingMatrixType, typename RotationMatrixType>\nEIGEN_DEVICE_FUNC void Transform<Scalar,Dim,Mode,Options>::computeScalingRotation(ScalingMatrixType *scaling, RotationMatrixType *rotation) const\n{\n  JacobiSVD<LinearMatrixType> svd(linear(), ComputeFullU | ComputeFullV);\n\n  Scalar x = (svd.matrixU() * svd.matrixV().adjoint()).determinant(); // so x has absolute value 1\n  VectorType sv(svd.singularValues());\n  sv.coeffRef(0) *= x;\n  if(scaling) scaling->lazyAssign(svd.matrixU() * sv.asDiagonal() * svd.matrixU().adjoint());\n  if(rotation)\n  {\n    LinearMatrixType m(svd.matrixU());\n    m.col(0) /= x;\n    rotation->lazyAssign(m * svd.matrixV().adjoint());\n  }\n}\n\n/** Convenient method to set \\c *this from a position, orientation and scale\n  * of a 3D object.\n  */\ntemplate<typename Scalar, int Dim, int Mode, int Options>\ntemplate<typename PositionDerived, typename OrientationType, typename ScaleDerived>\nEIGEN_DEVICE_FUNC Transform<Scalar,Dim,Mode,Options>&\nTransform<Scalar,Dim,Mode,Options>::fromPositionOrientationScale(const MatrixBase<PositionDerived> &position,\n  const OrientationType& orientation, const MatrixBase<ScaleDerived> &scale)\n{\n  linear() = internal::toRotationMatrix<Scalar,Dim>(orientation);\n  linear() *= scale.asDiagonal();\n  translation() = position;\n  makeAffine();\n  return *this;\n}\n\nnamespace internal {\n\ntemplate<int Mode>\nstruct transform_make_affine\n{\n  template<typename MatrixType>\n  EIGEN_DEVICE_FUNC static void run(MatrixType &mat)\n  {\n    static const int Dim = MatrixType::ColsAtCompileTime-1;\n    mat.template block<1,Dim>(Dim,0).setZero();\n    mat.coeffRef(Dim,Dim) = typename MatrixType::Scalar(1);\n  }\n};\n\ntemplate<>\nstruct transform_make_affine<AffineCompact>\n{\n  template<typename MatrixType> EIGEN_DEVICE_FUNC static void run(MatrixType &) { }\n};\n    \n// selector needed to avoid taking the inverse of a 3x4 matrix\ntemplate<typename TransformType, int Mode=TransformType::Mode>\nstruct projective_transform_inverse\n{\n  EIGEN_DEVICE_FUNC static inline void run(const TransformType&, TransformType&)\n  {}\n};\n\ntemplate<typename TransformType>\nstruct projective_transform_inverse<TransformType, Projective>\n{\n  EIGEN_DEVICE_FUNC static inline void run(const TransformType& m, TransformType& res)\n  {\n    res.matrix() = m.matrix().inverse();\n  }\n};\n\n} // end namespace internal\n\n\n/**\n  *\n  * \\returns the inverse transformation according to some given knowledge\n  * on \\c *this.\n  *\n  * \\param hint allows to optimize the inversion process when the transformation\n  * is known to be not a general transformation (optional). The possible values are:\n  *  - #Projective if the transformation is not necessarily affine, i.e., if the\n  *    last row is not guaranteed to be [0 ... 0 1]\n  *  - #Affine if the last row can be assumed to be [0 ... 0 1]\n  *  - #Isometry if the transformation is only a concatenations of translations\n  *    and rotations.\n  *  The default is the template class parameter \\c Mode.\n  *\n  * \\warning unless \\a traits is always set to NoShear or NoScaling, this function\n  * requires the generic inverse method of MatrixBase defined in the LU module. If\n  * you forget to include this module, then you will get hard to debug linking errors.\n  *\n  * \\sa MatrixBase::inverse()\n  */\ntemplate<typename Scalar, int Dim, int Mode, int Options>\nEIGEN_DEVICE_FUNC Transform<Scalar,Dim,Mode,Options>\nTransform<Scalar,Dim,Mode,Options>::inverse(TransformTraits hint) const\n{\n  Transform res;\n  if (hint == Projective)\n  {\n    internal::projective_transform_inverse<Transform>::run(*this, res);\n  }\n  else\n  {\n    if (hint == Isometry)\n    {\n      res.matrix().template topLeftCorner<Dim,Dim>() = linear().transpose();\n    }\n    else if(hint&Affine)\n    {\n      res.matrix().template topLeftCorner<Dim,Dim>() = linear().inverse();\n    }\n    else\n    {\n      eigen_assert(false && \"Invalid transform traits in Transform::Inverse\");\n    }\n    // translation and remaining parts\n    res.matrix().template topRightCorner<Dim,1>()\n      = - res.matrix().template topLeftCorner<Dim,Dim>() * translation();\n    res.makeAffine(); // we do need this, because in the beginning res is uninitialized\n  }\n  return res;\n}\n\nnamespace internal {\n\n/*****************************************************\n*** Specializations of take affine part            ***\n*****************************************************/\n\ntemplate<typename TransformType> struct transform_take_affine_part {\n  typedef typename TransformType::MatrixType MatrixType;\n  typedef typename TransformType::AffinePart AffinePart;\n  typedef typename TransformType::ConstAffinePart ConstAffinePart;\n  static inline AffinePart run(MatrixType& m)\n  { return m.template block<TransformType::Dim,TransformType::HDim>(0,0); }\n  static inline ConstAffinePart run(const MatrixType& m)\n  { return m.template block<TransformType::Dim,TransformType::HDim>(0,0); }\n};\n\ntemplate<typename Scalar, int Dim, int Options>\nstruct transform_take_affine_part<Transform<Scalar,Dim,AffineCompact, Options> > {\n  typedef typename Transform<Scalar,Dim,AffineCompact,Options>::MatrixType MatrixType;\n  static inline MatrixType& run(MatrixType& m) { return m; }\n  static inline const MatrixType& run(const MatrixType& m) { return m; }\n};\n\n/*****************************************************\n*** Specializations of construct from matrix       ***\n*****************************************************/\n\ntemplate<typename Other, int Mode, int Options, int Dim, int HDim>\nstruct transform_construct_from_matrix<Other, Mode,Options,Dim,HDim, Dim,Dim>\n{\n  static inline void run(Transform<typename Other::Scalar,Dim,Mode,Options> *transform, const Other& other)\n  {\n    transform->linear() = other;\n    transform->translation().setZero();\n    transform->makeAffine();\n  }\n};\n\ntemplate<typename Other, int Mode, int Options, int Dim, int HDim>\nstruct transform_construct_from_matrix<Other, Mode,Options,Dim,HDim, Dim,HDim>\n{\n  static inline void run(Transform<typename Other::Scalar,Dim,Mode,Options> *transform, const Other& other)\n  {\n    transform->affine() = other;\n    transform->makeAffine();\n  }\n};\n\ntemplate<typename Other, int Mode, int Options, int Dim, int HDim>\nstruct transform_construct_from_matrix<Other, Mode,Options,Dim,HDim, HDim,HDim>\n{\n  static inline void run(Transform<typename Other::Scalar,Dim,Mode,Options> *transform, const Other& other)\n  { transform->matrix() = other; }\n};\n\ntemplate<typename Other, int Options, int Dim, int HDim>\nstruct transform_construct_from_matrix<Other, AffineCompact,Options,Dim,HDim, HDim,HDim>\n{\n  static inline void run(Transform<typename Other::Scalar,Dim,AffineCompact,Options> *transform, const Other& other)\n  { transform->matrix() = other.template block<Dim,HDim>(0,0); }\n};\n\n/**********************************************************\n***   Specializations of operator* with rhs EigenBase   ***\n**********************************************************/\n\ntemplate<int LhsMode,int RhsMode>\nstruct transform_product_result\n{\n  enum \n  { \n    Mode =\n      (LhsMode == (int)Projective    || RhsMode == (int)Projective    ) ? Projective :\n      (LhsMode == (int)Affine        || RhsMode == (int)Affine        ) ? Affine :\n      (LhsMode == (int)AffineCompact || RhsMode == (int)AffineCompact ) ? AffineCompact :\n      (LhsMode == (int)Isometry      || RhsMode == (int)Isometry      ) ? Isometry : Projective\n  };\n};\n\ntemplate< typename TransformType, typename MatrixType, int RhsCols>\nstruct transform_right_product_impl< TransformType, MatrixType, 0, RhsCols>\n{\n  typedef typename MatrixType::PlainObject ResultType;\n\n  static EIGEN_STRONG_INLINE ResultType run(const TransformType& T, const MatrixType& other)\n  {\n    return T.matrix() * other;\n  }\n};\n\ntemplate< typename TransformType, typename MatrixType, int RhsCols>\nstruct transform_right_product_impl< TransformType, MatrixType, 1, RhsCols>\n{\n  enum { \n    Dim = TransformType::Dim, \n    HDim = TransformType::HDim,\n    OtherRows = MatrixType::RowsAtCompileTime,\n    OtherCols = MatrixType::ColsAtCompileTime\n  };\n\n  typedef typename MatrixType::PlainObject ResultType;\n\n  static EIGEN_STRONG_INLINE ResultType run(const TransformType& T, const MatrixType& other)\n  {\n    EIGEN_STATIC_ASSERT(OtherRows==HDim, YOU_MIXED_MATRICES_OF_DIFFERENT_SIZES);\n\n    typedef Block<ResultType, Dim, OtherCols, int(MatrixType::RowsAtCompileTime)==Dim> TopLeftLhs;\n\n    ResultType res(other.rows(),other.cols());\n    TopLeftLhs(res, 0, 0, Dim, other.cols()).noalias() = T.affine() * other;\n    res.row(OtherRows-1) = other.row(OtherRows-1);\n    \n    return res;\n  }\n};\n\ntemplate< typename TransformType, typename MatrixType, int RhsCols>\nstruct transform_right_product_impl< TransformType, MatrixType, 2, RhsCols>\n{\n  enum { \n    Dim = TransformType::Dim, \n    HDim = TransformType::HDim,\n    OtherRows = MatrixType::RowsAtCompileTime,\n    OtherCols = MatrixType::ColsAtCompileTime\n  };\n\n  typedef typename MatrixType::PlainObject ResultType;\n\n  static EIGEN_STRONG_INLINE ResultType run(const TransformType& T, const MatrixType& other)\n  {\n    EIGEN_STATIC_ASSERT(OtherRows==Dim, YOU_MIXED_MATRICES_OF_DIFFERENT_SIZES);\n\n    typedef Block<ResultType, Dim, OtherCols, true> TopLeftLhs;\n    ResultType res(Replicate<typename TransformType::ConstTranslationPart, 1, OtherCols>(T.translation(),1,other.cols()));\n    TopLeftLhs(res, 0, 0, Dim, other.cols()).noalias() += T.linear() * other;\n\n    return res;\n  }\n};\n\ntemplate< typename TransformType, typename MatrixType >\nstruct transform_right_product_impl< TransformType, MatrixType, 2, 1> // rhs is a vector of size Dim\n{\n  typedef typename TransformType::MatrixType TransformMatrix;\n  enum {\n    Dim = TransformType::Dim,\n    HDim = TransformType::HDim,\n    OtherRows = MatrixType::RowsAtCompileTime,\n    WorkingRows = EIGEN_PLAIN_ENUM_MIN(TransformMatrix::RowsAtCompileTime,HDim)\n  };\n\n  typedef typename MatrixType::PlainObject ResultType;\n\n  static EIGEN_STRONG_INLINE ResultType run(const TransformType& T, const MatrixType& other)\n  {\n    EIGEN_STATIC_ASSERT(OtherRows==Dim, YOU_MIXED_MATRICES_OF_DIFFERENT_SIZES);\n\n    Matrix<typename ResultType::Scalar, Dim+1, 1> rhs;\n    rhs.template head<Dim>() = other; rhs[Dim] = typename ResultType::Scalar(1);\n    Matrix<typename ResultType::Scalar, WorkingRows, 1> res(T.matrix() * rhs);\n    return res.template head<Dim>();\n  }\n};\n\n/**********************************************************\n***   Specializations of operator* with lhs EigenBase   ***\n**********************************************************/\n\n// generic HDim x HDim matrix * T => Projective\ntemplate<typename Other,int Mode, int Options, int Dim, int HDim>\nstruct transform_left_product_impl<Other,Mode,Options,Dim,HDim, HDim,HDim>\n{\n  typedef Transform<typename Other::Scalar,Dim,Mode,Options> TransformType;\n  typedef typename TransformType::MatrixType MatrixType;\n  typedef Transform<typename Other::Scalar,Dim,Projective,Options> ResultType;\n  static ResultType run(const Other& other,const TransformType& tr)\n  { return ResultType(other * tr.matrix()); }\n};\n\n// generic HDim x HDim matrix * AffineCompact => Projective\ntemplate<typename Other, int Options, int Dim, int HDim>\nstruct transform_left_product_impl<Other,AffineCompact,Options,Dim,HDim, HDim,HDim>\n{\n  typedef Transform<typename Other::Scalar,Dim,AffineCompact,Options> TransformType;\n  typedef typename TransformType::MatrixType MatrixType;\n  typedef Transform<typename Other::Scalar,Dim,Projective,Options> ResultType;\n  static ResultType run(const Other& other,const TransformType& tr)\n  {\n    ResultType res;\n    res.matrix().noalias() = other.template block<HDim,Dim>(0,0) * tr.matrix();\n    res.matrix().col(Dim) += other.col(Dim);\n    return res;\n  }\n};\n\n// affine matrix * T\ntemplate<typename Other,int Mode, int Options, int Dim, int HDim>\nstruct transform_left_product_impl<Other,Mode,Options,Dim,HDim, Dim,HDim>\n{\n  typedef Transform<typename Other::Scalar,Dim,Mode,Options> TransformType;\n  typedef typename TransformType::MatrixType MatrixType;\n  typedef TransformType ResultType;\n  static ResultType run(const Other& other,const TransformType& tr)\n  {\n    ResultType res;\n    res.affine().noalias() = other * tr.matrix();\n    res.matrix().row(Dim) = tr.matrix().row(Dim);\n    return res;\n  }\n};\n\n// affine matrix * AffineCompact\ntemplate<typename Other, int Options, int Dim, int HDim>\nstruct transform_left_product_impl<Other,AffineCompact,Options,Dim,HDim, Dim,HDim>\n{\n  typedef Transform<typename Other::Scalar,Dim,AffineCompact,Options> TransformType;\n  typedef typename TransformType::MatrixType MatrixType;\n  typedef TransformType ResultType;\n  static ResultType run(const Other& other,const TransformType& tr)\n  {\n    ResultType res;\n    res.matrix().noalias() = other.template block<Dim,Dim>(0,0) * tr.matrix();\n    res.translation() += other.col(Dim);\n    return res;\n  }\n};\n\n// linear matrix * T\ntemplate<typename Other,int Mode, int Options, int Dim, int HDim>\nstruct transform_left_product_impl<Other,Mode,Options,Dim,HDim, Dim,Dim>\n{\n  typedef Transform<typename Other::Scalar,Dim,Mode,Options> TransformType;\n  typedef typename TransformType::MatrixType MatrixType;\n  typedef TransformType ResultType;\n  static ResultType run(const Other& other, const TransformType& tr)\n  {\n    TransformType res;\n    if(Mode!=int(AffineCompact))\n      res.matrix().row(Dim) = tr.matrix().row(Dim);\n    res.matrix().template topRows<Dim>().noalias()\n      = other * tr.matrix().template topRows<Dim>();\n    return res;\n  }\n};\n\n/**********************************************************\n*** Specializations of operator* with another Transform ***\n**********************************************************/\n\ntemplate<typename Scalar, int Dim, int LhsMode, int LhsOptions, int RhsMode, int RhsOptions>\nstruct transform_transform_product_impl<Transform<Scalar,Dim,LhsMode,LhsOptions>,Transform<Scalar,Dim,RhsMode,RhsOptions>,false >\n{\n  enum { ResultMode = transform_product_result<LhsMode,RhsMode>::Mode };\n  typedef Transform<Scalar,Dim,LhsMode,LhsOptions> Lhs;\n  typedef Transform<Scalar,Dim,RhsMode,RhsOptions> Rhs;\n  typedef Transform<Scalar,Dim,ResultMode,LhsOptions> ResultType;\n  static ResultType run(const Lhs& lhs, const Rhs& rhs)\n  {\n    ResultType res;\n    res.linear() = lhs.linear() * rhs.linear();\n    res.translation() = lhs.linear() * rhs.translation() + lhs.translation();\n    res.makeAffine();\n    return res;\n  }\n};\n\ntemplate<typename Scalar, int Dim, int LhsMode, int LhsOptions, int RhsMode, int RhsOptions>\nstruct transform_transform_product_impl<Transform<Scalar,Dim,LhsMode,LhsOptions>,Transform<Scalar,Dim,RhsMode,RhsOptions>,true >\n{\n  typedef Transform<Scalar,Dim,LhsMode,LhsOptions> Lhs;\n  typedef Transform<Scalar,Dim,RhsMode,RhsOptions> Rhs;\n  typedef Transform<Scalar,Dim,Projective> ResultType;\n  static ResultType run(const Lhs& lhs, const Rhs& rhs)\n  {\n    return ResultType( lhs.matrix() * rhs.matrix() );\n  }\n};\n\ntemplate<typename Scalar, int Dim, int LhsOptions, int RhsOptions>\nstruct transform_transform_product_impl<Transform<Scalar,Dim,AffineCompact,LhsOptions>,Transform<Scalar,Dim,Projective,RhsOptions>,true >\n{\n  typedef Transform<Scalar,Dim,AffineCompact,LhsOptions> Lhs;\n  typedef Transform<Scalar,Dim,Projective,RhsOptions> Rhs;\n  typedef Transform<Scalar,Dim,Projective> ResultType;\n  static ResultType run(const Lhs& lhs, const Rhs& rhs)\n  {\n    ResultType res;\n    res.matrix().template topRows<Dim>() = lhs.matrix() * rhs.matrix();\n    res.matrix().row(Dim) = rhs.matrix().row(Dim);\n    return res;\n  }\n};\n\ntemplate<typename Scalar, int Dim, int LhsOptions, int RhsOptions>\nstruct transform_transform_product_impl<Transform<Scalar,Dim,Projective,LhsOptions>,Transform<Scalar,Dim,AffineCompact,RhsOptions>,true >\n{\n  typedef Transform<Scalar,Dim,Projective,LhsOptions> Lhs;\n  typedef Transform<Scalar,Dim,AffineCompact,RhsOptions> Rhs;\n  typedef Transform<Scalar,Dim,Projective> ResultType;\n  static ResultType run(const Lhs& lhs, const Rhs& rhs)\n  {\n    ResultType res(lhs.matrix().template leftCols<Dim>() * rhs.matrix());\n    res.matrix().col(Dim) += lhs.matrix().col(Dim);\n    return res;\n  }\n};\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_TRANSFORM_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Geometry/Translation.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_TRANSLATION_H\n#define EIGEN_TRANSLATION_H\n\nnamespace Eigen { \n\n/** \\geometry_module \\ingroup Geometry_Module\n  *\n  * \\class Translation\n  *\n  * \\brief Represents a translation transformation\n  *\n  * \\tparam _Scalar the scalar type, i.e., the type of the coefficients.\n  * \\tparam _Dim the  dimension of the space, can be a compile time value or Dynamic\n  *\n  * \\note This class is not aimed to be used to store a translation transformation,\n  * but rather to make easier the constructions and updates of Transform objects.\n  *\n  * \\sa class Scaling, class Transform\n  */\ntemplate<typename _Scalar, int _Dim>\nclass Translation\n{\npublic:\n  EIGEN_MAKE_ALIGNED_OPERATOR_NEW_IF_VECTORIZABLE_FIXED_SIZE(_Scalar,_Dim)\n  /** dimension of the space */\n  enum { Dim = _Dim };\n  /** the scalar type of the coefficients */\n  typedef _Scalar Scalar;\n  /** corresponding vector type */\n  typedef Matrix<Scalar,Dim,1> VectorType;\n  /** corresponding linear transformation matrix type */\n  typedef Matrix<Scalar,Dim,Dim> LinearMatrixType;\n  /** corresponding affine transformation type */\n  typedef Transform<Scalar,Dim,Affine> AffineTransformType;\n  /** corresponding isometric transformation type */\n  typedef Transform<Scalar,Dim,Isometry> IsometryTransformType;\n\nprotected:\n\n  VectorType m_coeffs;\n\npublic:\n\n  /** Default constructor without initialization. */\n  EIGEN_DEVICE_FUNC Translation() {}\n  /**  */\n  EIGEN_DEVICE_FUNC inline Translation(const Scalar& sx, const Scalar& sy)\n  {\n    eigen_assert(Dim==2);\n    m_coeffs.x() = sx;\n    m_coeffs.y() = sy;\n  }\n  /**  */\n  EIGEN_DEVICE_FUNC inline Translation(const Scalar& sx, const Scalar& sy, const Scalar& sz)\n  {\n    eigen_assert(Dim==3);\n    m_coeffs.x() = sx;\n    m_coeffs.y() = sy;\n    m_coeffs.z() = sz;\n  }\n  /** Constructs and initialize the translation transformation from a vector of translation coefficients */\n  EIGEN_DEVICE_FUNC explicit inline Translation(const VectorType& vector) : m_coeffs(vector) {}\n\n  /** \\brief Retruns the x-translation by value. **/\n  EIGEN_DEVICE_FUNC inline Scalar x() const { return m_coeffs.x(); }\n  /** \\brief Retruns the y-translation by value. **/\n  EIGEN_DEVICE_FUNC inline Scalar y() const { return m_coeffs.y(); }\n  /** \\brief Retruns the z-translation by value. **/\n  EIGEN_DEVICE_FUNC inline Scalar z() const { return m_coeffs.z(); }\n\n  /** \\brief Retruns the x-translation as a reference. **/\n  EIGEN_DEVICE_FUNC inline Scalar& x() { return m_coeffs.x(); }\n  /** \\brief Retruns the y-translation as a reference. **/\n  EIGEN_DEVICE_FUNC inline Scalar& y() { return m_coeffs.y(); }\n  /** \\brief Retruns the z-translation as a reference. **/\n  EIGEN_DEVICE_FUNC inline Scalar& z() { return m_coeffs.z(); }\n\n  EIGEN_DEVICE_FUNC const VectorType& vector() const { return m_coeffs; }\n  EIGEN_DEVICE_FUNC VectorType& vector() { return m_coeffs; }\n\n  EIGEN_DEVICE_FUNC const VectorType& translation() const { return m_coeffs; }\n  EIGEN_DEVICE_FUNC VectorType& translation() { return m_coeffs; }\n\n  /** Concatenates two translation */\n  EIGEN_DEVICE_FUNC inline Translation operator* (const Translation& other) const\n  { return Translation(m_coeffs + other.m_coeffs); }\n\n  /** Concatenates a translation and a uniform scaling */\n  EIGEN_DEVICE_FUNC inline AffineTransformType operator* (const UniformScaling<Scalar>& other) const;\n\n  /** Concatenates a translation and a linear transformation */\n  template<typename OtherDerived>\n  EIGEN_DEVICE_FUNC inline AffineTransformType operator* (const EigenBase<OtherDerived>& linear) const;\n\n  /** Concatenates a translation and a rotation */\n  template<typename Derived>\n  EIGEN_DEVICE_FUNC inline IsometryTransformType operator*(const RotationBase<Derived,Dim>& r) const\n  { return *this * IsometryTransformType(r); }\n\n  /** \\returns the concatenation of a linear transformation \\a l with the translation \\a t */\n  // its a nightmare to define a templated friend function outside its declaration\n  template<typename OtherDerived> friend\n  EIGEN_DEVICE_FUNC inline AffineTransformType operator*(const EigenBase<OtherDerived>& linear, const Translation& t)\n  {\n    AffineTransformType res;\n    res.matrix().setZero();\n    res.linear() = linear.derived();\n    res.translation() = linear.derived() * t.m_coeffs;\n    res.matrix().row(Dim).setZero();\n    res(Dim,Dim) = Scalar(1);\n    return res;\n  }\n\n  /** Concatenates a translation and a transformation */\n  template<int Mode, int Options>\n  EIGEN_DEVICE_FUNC inline Transform<Scalar,Dim,Mode> operator* (const Transform<Scalar,Dim,Mode,Options>& t) const\n  {\n    Transform<Scalar,Dim,Mode> res = t;\n    res.pretranslate(m_coeffs);\n    return res;\n  }\n\n  /** Applies translation to vector */\n  template<typename Derived>\n  inline typename internal::enable_if<Derived::IsVectorAtCompileTime,VectorType>::type\n  operator* (const MatrixBase<Derived>& vec) const\n  { return m_coeffs + vec.derived(); }\n\n  /** \\returns the inverse translation (opposite) */\n  Translation inverse() const { return Translation(-m_coeffs); }\n\n  Translation& operator=(const Translation& other)\n  {\n    m_coeffs = other.m_coeffs;\n    return *this;\n  }\n\n  static const Translation Identity() { return Translation(VectorType::Zero()); }\n\n  /** \\returns \\c *this with scalar type casted to \\a NewScalarType\n    *\n    * Note that if \\a NewScalarType is equal to the current scalar type of \\c *this\n    * then this function smartly returns a const reference to \\c *this.\n    */\n  template<typename NewScalarType>\n  EIGEN_DEVICE_FUNC inline typename internal::cast_return_type<Translation,Translation<NewScalarType,Dim> >::type cast() const\n  { return typename internal::cast_return_type<Translation,Translation<NewScalarType,Dim> >::type(*this); }\n\n  /** Copy constructor with scalar type conversion */\n  template<typename OtherScalarType>\n  EIGEN_DEVICE_FUNC inline explicit Translation(const Translation<OtherScalarType,Dim>& other)\n  { m_coeffs = other.vector().template cast<Scalar>(); }\n\n  /** \\returns \\c true if \\c *this is approximately equal to \\a other, within the precision\n    * determined by \\a prec.\n    *\n    * \\sa MatrixBase::isApprox() */\n  EIGEN_DEVICE_FUNC bool isApprox(const Translation& other, const typename NumTraits<Scalar>::Real& prec = NumTraits<Scalar>::dummy_precision()) const\n  { return m_coeffs.isApprox(other.m_coeffs, prec); }\n\n};\n\n/** \\addtogroup Geometry_Module */\n//@{\ntypedef Translation<float, 2> Translation2f;\ntypedef Translation<double,2> Translation2d;\ntypedef Translation<float, 3> Translation3f;\ntypedef Translation<double,3> Translation3d;\n//@}\n\ntemplate<typename Scalar, int Dim>\nEIGEN_DEVICE_FUNC inline typename Translation<Scalar,Dim>::AffineTransformType\nTranslation<Scalar,Dim>::operator* (const UniformScaling<Scalar>& other) const\n{\n  AffineTransformType res;\n  res.matrix().setZero();\n  res.linear().diagonal().fill(other.factor());\n  res.translation() = m_coeffs;\n  res(Dim,Dim) = Scalar(1);\n  return res;\n}\n\ntemplate<typename Scalar, int Dim>\ntemplate<typename OtherDerived>\nEIGEN_DEVICE_FUNC inline typename Translation<Scalar,Dim>::AffineTransformType\nTranslation<Scalar,Dim>::operator* (const EigenBase<OtherDerived>& linear) const\n{\n  AffineTransformType res;\n  res.matrix().setZero();\n  res.linear() = linear.derived();\n  res.translation() = m_coeffs;\n  res.matrix().row(Dim).setZero();\n  res(Dim,Dim) = Scalar(1);\n  return res;\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_TRANSLATION_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Geometry/Umeyama.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009 Hauke Heibel <hauke.heibel@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_UMEYAMA_H\n#define EIGEN_UMEYAMA_H\n\n// This file requires the user to include \n// * Eigen/Core\n// * Eigen/LU \n// * Eigen/SVD\n// * Eigen/Array\n\nnamespace Eigen { \n\n#ifndef EIGEN_PARSED_BY_DOXYGEN\n\n// These helpers are required since it allows to use mixed types as parameters\n// for the Umeyama. The problem with mixed parameters is that the return type\n// cannot trivially be deduced when float and double types are mixed.\nnamespace internal {\n\n// Compile time return type deduction for different MatrixBase types.\n// Different means here different alignment and parameters but the same underlying\n// real scalar type.\ntemplate<typename MatrixType, typename OtherMatrixType>\nstruct umeyama_transform_matrix_type\n{\n  enum {\n    MinRowsAtCompileTime = EIGEN_SIZE_MIN_PREFER_DYNAMIC(MatrixType::RowsAtCompileTime, OtherMatrixType::RowsAtCompileTime),\n\n    // When possible we want to choose some small fixed size value since the result\n    // is likely to fit on the stack. So here, EIGEN_SIZE_MIN_PREFER_DYNAMIC is not what we want.\n    HomogeneousDimension = int(MinRowsAtCompileTime) == Dynamic ? Dynamic : int(MinRowsAtCompileTime)+1\n  };\n\n  typedef Matrix<typename traits<MatrixType>::Scalar,\n    HomogeneousDimension,\n    HomogeneousDimension,\n    AutoAlign | (traits<MatrixType>::Flags & RowMajorBit ? RowMajor : ColMajor),\n    HomogeneousDimension,\n    HomogeneousDimension\n  > type;\n};\n\n}\n\n#endif\n\n/**\n* \\geometry_module \\ingroup Geometry_Module\n*\n* \\brief Returns the transformation between two point sets.\n*\n* The algorithm is based on:\n* \"Least-squares estimation of transformation parameters between two point patterns\",\n* Shinji Umeyama, PAMI 1991, DOI: 10.1109/34.88573\n*\n* It estimates parameters \\f$ c, \\mathbf{R}, \\f$ and \\f$ \\mathbf{t} \\f$ such that\n* \\f{align*}\n*   \\frac{1}{n} \\sum_{i=1}^n \\vert\\vert y_i - (c\\mathbf{R}x_i + \\mathbf{t}) \\vert\\vert_2^2\n* \\f}\n* is minimized.\n*\n* The algorithm is based on the analysis of the covariance matrix\n* \\f$ \\Sigma_{\\mathbf{x}\\mathbf{y}} \\in \\mathbb{R}^{d \\times d} \\f$\n* of the input point sets \\f$ \\mathbf{x} \\f$ and \\f$ \\mathbf{y} \\f$ where \n* \\f$d\\f$ is corresponding to the dimension (which is typically small).\n* The analysis is involving the SVD having a complexity of \\f$O(d^3)\\f$\n* though the actual computational effort lies in the covariance\n* matrix computation which has an asymptotic lower bound of \\f$O(dm)\\f$ when \n* the input point sets have dimension \\f$d \\times m\\f$.\n*\n* Currently the method is working only for floating point matrices.\n*\n* \\todo Should the return type of umeyama() become a Transform?\n*\n* \\param src Source points \\f$ \\mathbf{x} = \\left( x_1, \\hdots, x_n \\right) \\f$.\n* \\param dst Destination points \\f$ \\mathbf{y} = \\left( y_1, \\hdots, y_n \\right) \\f$.\n* \\param with_scaling Sets \\f$ c=1 \\f$ when <code>false</code> is passed.\n* \\return The homogeneous transformation \n* \\f{align*}\n*   T = \\begin{bmatrix} c\\mathbf{R} & \\mathbf{t} \\\\ \\mathbf{0} & 1 \\end{bmatrix}\n* \\f}\n* minimizing the resudiual above. This transformation is always returned as an \n* Eigen::Matrix.\n*/\ntemplate <typename Derived, typename OtherDerived>\ntypename internal::umeyama_transform_matrix_type<Derived, OtherDerived>::type\numeyama(const MatrixBase<Derived>& src, const MatrixBase<OtherDerived>& dst, bool with_scaling = true)\n{\n  typedef typename internal::umeyama_transform_matrix_type<Derived, OtherDerived>::type TransformationMatrixType;\n  typedef typename internal::traits<TransformationMatrixType>::Scalar Scalar;\n  typedef typename NumTraits<Scalar>::Real RealScalar;\n\n  EIGEN_STATIC_ASSERT(!NumTraits<Scalar>::IsComplex, NUMERIC_TYPE_MUST_BE_REAL)\n  EIGEN_STATIC_ASSERT((internal::is_same<Scalar, typename internal::traits<OtherDerived>::Scalar>::value),\n    YOU_MIXED_DIFFERENT_NUMERIC_TYPES__YOU_NEED_TO_USE_THE_CAST_METHOD_OF_MATRIXBASE_TO_CAST_NUMERIC_TYPES_EXPLICITLY)\n\n  enum { Dimension = EIGEN_SIZE_MIN_PREFER_DYNAMIC(Derived::RowsAtCompileTime, OtherDerived::RowsAtCompileTime) };\n\n  typedef Matrix<Scalar, Dimension, 1> VectorType;\n  typedef Matrix<Scalar, Dimension, Dimension> MatrixType;\n  typedef typename internal::plain_matrix_type_row_major<Derived>::type RowMajorMatrixType;\n\n  const Index m = src.rows(); // dimension\n  const Index n = src.cols(); // number of measurements\n\n  // required for demeaning ...\n  const RealScalar one_over_n = RealScalar(1) / static_cast<RealScalar>(n);\n\n  // computation of mean\n  const VectorType src_mean = src.rowwise().sum() * one_over_n;\n  const VectorType dst_mean = dst.rowwise().sum() * one_over_n;\n\n  // demeaning of src and dst points\n  const RowMajorMatrixType src_demean = src.colwise() - src_mean;\n  const RowMajorMatrixType dst_demean = dst.colwise() - dst_mean;\n\n  // Eq. (36)-(37)\n  const Scalar src_var = src_demean.rowwise().squaredNorm().sum() * one_over_n;\n\n  // Eq. (38)\n  const MatrixType sigma = one_over_n * dst_demean * src_demean.transpose();\n\n  JacobiSVD<MatrixType> svd(sigma, ComputeFullU | ComputeFullV);\n\n  // Initialize the resulting transformation with an identity matrix...\n  TransformationMatrixType Rt = TransformationMatrixType::Identity(m+1,m+1);\n\n  // Eq. (39)\n  VectorType S = VectorType::Ones(m);\n\n  if  ( svd.matrixU().determinant() * svd.matrixV().determinant() < 0 )\n    S(m-1) = -1;\n\n  // Eq. (40) and (43)\n  Rt.block(0,0,m,m).noalias() = svd.matrixU() * S.asDiagonal() * svd.matrixV().transpose();\n\n  if (with_scaling)\n  {\n    // Eq. (42)\n    const Scalar c = Scalar(1)/src_var * svd.singularValues().dot(S);\n\n    // Eq. (41)\n    Rt.col(m).head(m) = dst_mean;\n    Rt.col(m).head(m).noalias() -= c*Rt.topLeftCorner(m,m)*src_mean;\n    Rt.block(0,0,m,m) *= c;\n  }\n  else\n  {\n    Rt.col(m).head(m) = dst_mean;\n    Rt.col(m).head(m).noalias() -= Rt.topLeftCorner(m,m)*src_mean;\n  }\n\n  return Rt;\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_UMEYAMA_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Geometry/arch/Geometry_SSE.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009 Rohit Garg <rpg.314@gmail.com>\n// Copyright (C) 2009-2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_GEOMETRY_SSE_H\n#define EIGEN_GEOMETRY_SSE_H\n\nnamespace Eigen { \n\nnamespace internal {\n\ntemplate<class Derived, class OtherDerived>\nstruct quat_product<Architecture::SSE, Derived, OtherDerived, float, Aligned16>\n{\n  static inline Quaternion<float> run(const QuaternionBase<Derived>& _a, const QuaternionBase<OtherDerived>& _b)\n  {\n    Quaternion<float> res;\n    const __m128 mask = _mm_setr_ps(0.f,0.f,0.f,-0.f);\n    __m128 a = _a.coeffs().template packet<Aligned16>(0);\n    __m128 b = _b.coeffs().template packet<Aligned16>(0);\n    __m128 s1 = _mm_mul_ps(vec4f_swizzle1(a,1,2,0,2),vec4f_swizzle1(b,2,0,1,2));\n    __m128 s2 = _mm_mul_ps(vec4f_swizzle1(a,3,3,3,1),vec4f_swizzle1(b,0,1,2,1));\n    pstore(&res.x(),\n              _mm_add_ps(_mm_sub_ps(_mm_mul_ps(a,vec4f_swizzle1(b,3,3,3,3)),\n                                    _mm_mul_ps(vec4f_swizzle1(a,2,0,1,0),\n                                               vec4f_swizzle1(b,1,2,0,0))),\n                         _mm_xor_ps(mask,_mm_add_ps(s1,s2))));\n    \n    return res;\n  }\n};\n\ntemplate<class Derived, int Alignment>\nstruct quat_conj<Architecture::SSE, Derived, float, Alignment>\n{\n  static inline Quaternion<float> run(const QuaternionBase<Derived>& q)\n  {\n    Quaternion<float> res;\n    const __m128 mask = _mm_setr_ps(-0.f,-0.f,-0.f,0.f);\n    pstore(&res.x(), _mm_xor_ps(mask, q.coeffs().template packet<Alignment>(0)));\n    return res;\n  }\n};\n\n\ntemplate<typename VectorLhs,typename VectorRhs>\nstruct cross3_impl<Architecture::SSE,VectorLhs,VectorRhs,float,true>\n{\n  static inline typename plain_matrix_type<VectorLhs>::type\n  run(const VectorLhs& lhs, const VectorRhs& rhs)\n  {\n    __m128 a = lhs.template packet<traits<VectorLhs>::Alignment>(0);\n    __m128 b = rhs.template packet<traits<VectorRhs>::Alignment>(0);\n    __m128 mul1=_mm_mul_ps(vec4f_swizzle1(a,1,2,0,3),vec4f_swizzle1(b,2,0,1,3));\n    __m128 mul2=_mm_mul_ps(vec4f_swizzle1(a,2,0,1,3),vec4f_swizzle1(b,1,2,0,3));\n    typename plain_matrix_type<VectorLhs>::type res;\n    pstore(&res.x(),_mm_sub_ps(mul1,mul2));\n    return res;\n  }\n};\n\n\n\n\ntemplate<class Derived, class OtherDerived, int Alignment>\nstruct quat_product<Architecture::SSE, Derived, OtherDerived, double, Alignment>\n{\n  static inline Quaternion<double> run(const QuaternionBase<Derived>& _a, const QuaternionBase<OtherDerived>& _b)\n  {\n  const Packet2d mask = _mm_castsi128_pd(_mm_set_epi32(0x0,0x0,0x80000000,0x0));\n\n  Quaternion<double> res;\n\n  const double* a = _a.coeffs().data();\n  Packet2d b_xy = _b.coeffs().template packet<Alignment>(0);\n  Packet2d b_zw = _b.coeffs().template packet<Alignment>(2);\n  Packet2d a_xx = pset1<Packet2d>(a[0]);\n  Packet2d a_yy = pset1<Packet2d>(a[1]);\n  Packet2d a_zz = pset1<Packet2d>(a[2]);\n  Packet2d a_ww = pset1<Packet2d>(a[3]);\n\n  // two temporaries:\n  Packet2d t1, t2;\n\n  /*\n   * t1 = ww*xy + yy*zw\n   * t2 = zz*xy - xx*zw\n   * res.xy = t1 +/- swap(t2)\n   */\n  t1 = padd(pmul(a_ww, b_xy), pmul(a_yy, b_zw));\n  t2 = psub(pmul(a_zz, b_xy), pmul(a_xx, b_zw));\n#ifdef EIGEN_VECTORIZE_SSE3\n  EIGEN_UNUSED_VARIABLE(mask)\n  pstore(&res.x(), _mm_addsub_pd(t1, preverse(t2)));\n#else\n  pstore(&res.x(), padd(t1, pxor(mask,preverse(t2))));\n#endif\n  \n  /*\n   * t1 = ww*zw - yy*xy\n   * t2 = zz*zw + xx*xy\n   * res.zw = t1 -/+ swap(t2) = swap( swap(t1) +/- t2)\n   */\n  t1 = psub(pmul(a_ww, b_zw), pmul(a_yy, b_xy));\n  t2 = padd(pmul(a_zz, b_zw), pmul(a_xx, b_xy));\n#ifdef EIGEN_VECTORIZE_SSE3\n  EIGEN_UNUSED_VARIABLE(mask)\n  pstore(&res.z(), preverse(_mm_addsub_pd(preverse(t1), t2)));\n#else\n  pstore(&res.z(), psub(t1, pxor(mask,preverse(t2))));\n#endif\n\n  return res;\n}\n};\n\ntemplate<class Derived, int Alignment>\nstruct quat_conj<Architecture::SSE, Derived, double, Alignment>\n{\n  static inline Quaternion<double> run(const QuaternionBase<Derived>& q)\n  {\n    Quaternion<double> res;\n    const __m128d mask0 = _mm_setr_pd(-0.,-0.);\n    const __m128d mask2 = _mm_setr_pd(-0.,0.);\n    pstore(&res.x(), _mm_xor_pd(mask0, q.coeffs().template packet<Alignment>(0)));\n    pstore(&res.z(), _mm_xor_pd(mask2, q.coeffs().template packet<Alignment>(2)));\n    return res;\n  }\n};\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_GEOMETRY_SSE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Householder/BlockHouseholder.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2010 Vincent Lejeune\n// Copyright (C) 2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_BLOCK_HOUSEHOLDER_H\n#define EIGEN_BLOCK_HOUSEHOLDER_H\n\n// This file contains some helper function to deal with block householder reflectors\n\nnamespace Eigen { \n\nnamespace internal {\n  \n/** \\internal */\n// template<typename TriangularFactorType,typename VectorsType,typename CoeffsType>\n// void make_block_householder_triangular_factor(TriangularFactorType& triFactor, const VectorsType& vectors, const CoeffsType& hCoeffs)\n// {\n//   typedef typename VectorsType::Scalar Scalar;\n//   const Index nbVecs = vectors.cols();\n//   eigen_assert(triFactor.rows() == nbVecs && triFactor.cols() == nbVecs && vectors.rows()>=nbVecs);\n// \n//   for(Index i = 0; i < nbVecs; i++)\n//   {\n//     Index rs = vectors.rows() - i;\n//     // Warning, note that hCoeffs may alias with vectors.\n//     // It is then necessary to copy it before modifying vectors(i,i). \n//     typename CoeffsType::Scalar h = hCoeffs(i);\n//     // This hack permits to pass trough nested Block<> and Transpose<> expressions.\n//     Scalar *Vii_ptr = const_cast<Scalar*>(vectors.data() + vectors.outerStride()*i + vectors.innerStride()*i);\n//     Scalar Vii = *Vii_ptr;\n//     *Vii_ptr = Scalar(1);\n//     triFactor.col(i).head(i).noalias() = -h * vectors.block(i, 0, rs, i).adjoint()\n//                                        * vectors.col(i).tail(rs);\n//     *Vii_ptr = Vii;\n//     // FIXME add .noalias() once the triangular product can work inplace\n//     triFactor.col(i).head(i) = triFactor.block(0,0,i,i).template triangularView<Upper>()\n//                              * triFactor.col(i).head(i);\n//     triFactor(i,i) = hCoeffs(i);\n//   }\n// }\n\n/** \\internal */\n// This variant avoid modifications in vectors\ntemplate<typename TriangularFactorType,typename VectorsType,typename CoeffsType>\nvoid make_block_householder_triangular_factor(TriangularFactorType& triFactor, const VectorsType& vectors, const CoeffsType& hCoeffs)\n{\n  const Index nbVecs = vectors.cols();\n  eigen_assert(triFactor.rows() == nbVecs && triFactor.cols() == nbVecs && vectors.rows()>=nbVecs);\n\n  for(Index i = nbVecs-1; i >=0 ; --i)\n  {\n    Index rs = vectors.rows() - i - 1;\n    Index rt = nbVecs-i-1;\n\n    if(rt>0)\n    {\n      triFactor.row(i).tail(rt).noalias() = -hCoeffs(i) * vectors.col(i).tail(rs).adjoint()\n                                                        * vectors.bottomRightCorner(rs, rt).template triangularView<UnitLower>();\n            \n      // FIXME add .noalias() once the triangular product can work inplace\n      triFactor.row(i).tail(rt) = triFactor.row(i).tail(rt) * triFactor.bottomRightCorner(rt,rt).template triangularView<Upper>();\n      \n    }\n    triFactor(i,i) = hCoeffs(i);\n  }\n}\n\n/** \\internal\n  * if forward then perform   mat = H0 * H1 * H2 * mat\n  * otherwise perform         mat = H2 * H1 * H0 * mat\n  */\ntemplate<typename MatrixType,typename VectorsType,typename CoeffsType>\nvoid apply_block_householder_on_the_left(MatrixType& mat, const VectorsType& vectors, const CoeffsType& hCoeffs, bool forward)\n{\n  enum { TFactorSize = MatrixType::ColsAtCompileTime };\n  Index nbVecs = vectors.cols();\n  Matrix<typename MatrixType::Scalar, TFactorSize, TFactorSize, RowMajor> T(nbVecs,nbVecs);\n  \n  if(forward) make_block_householder_triangular_factor(T, vectors, hCoeffs);\n  else        make_block_householder_triangular_factor(T, vectors, hCoeffs.conjugate());  \n  const TriangularView<const VectorsType, UnitLower> V(vectors);\n\n  // A -= V T V^* A\n  Matrix<typename MatrixType::Scalar,VectorsType::ColsAtCompileTime,MatrixType::ColsAtCompileTime,0,\n         VectorsType::MaxColsAtCompileTime,MatrixType::MaxColsAtCompileTime> tmp = V.adjoint() * mat;\n  // FIXME add .noalias() once the triangular product can work inplace\n  if(forward) tmp = T.template triangularView<Upper>()           * tmp;\n  else        tmp = T.template triangularView<Upper>().adjoint() * tmp;\n  mat.noalias() -= V * tmp;\n}\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_BLOCK_HOUSEHOLDER_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Householder/Householder.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2010 Benoit Jacob <jacob.benoit.1@gmail.com>\n// Copyright (C) 2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_HOUSEHOLDER_H\n#define EIGEN_HOUSEHOLDER_H\n\nnamespace Eigen { \n\nnamespace internal {\ntemplate<int n> struct decrement_size\n{\n  enum {\n    ret = n==Dynamic ? n : n-1\n  };\n};\n}\n\n/** Computes the elementary reflector H such that:\n  * \\f$ H *this = [ beta 0 ... 0]^T \\f$\n  * where the transformation H is:\n  * \\f$ H = I - tau v v^*\\f$\n  * and the vector v is:\n  * \\f$ v^T = [1 essential^T] \\f$\n  *\n  * The essential part of the vector \\c v is stored in *this.\n  * \n  * On output:\n  * \\param tau the scaling factor of the Householder transformation\n  * \\param beta the result of H * \\c *this\n  *\n  * \\sa MatrixBase::makeHouseholder(), MatrixBase::applyHouseholderOnTheLeft(),\n  *     MatrixBase::applyHouseholderOnTheRight()\n  */\ntemplate<typename Derived>\nvoid MatrixBase<Derived>::makeHouseholderInPlace(Scalar& tau, RealScalar& beta)\n{\n  VectorBlock<Derived, internal::decrement_size<Base::SizeAtCompileTime>::ret> essentialPart(derived(), 1, size()-1);\n  makeHouseholder(essentialPart, tau, beta);\n}\n\n/** Computes the elementary reflector H such that:\n  * \\f$ H *this = [ beta 0 ... 0]^T \\f$\n  * where the transformation H is:\n  * \\f$ H = I - tau v v^*\\f$\n  * and the vector v is:\n  * \\f$ v^T = [1 essential^T] \\f$\n  *\n  * On output:\n  * \\param essential the essential part of the vector \\c v\n  * \\param tau the scaling factor of the Householder transformation\n  * \\param beta the result of H * \\c *this\n  *\n  * \\sa MatrixBase::makeHouseholderInPlace(), MatrixBase::applyHouseholderOnTheLeft(),\n  *     MatrixBase::applyHouseholderOnTheRight()\n  */\ntemplate<typename Derived>\ntemplate<typename EssentialPart>\nvoid MatrixBase<Derived>::makeHouseholder(\n  EssentialPart& essential,\n  Scalar& tau,\n  RealScalar& beta) const\n{\n  using std::sqrt;\n  using numext::conj;\n  \n  EIGEN_STATIC_ASSERT_VECTOR_ONLY(EssentialPart)\n  VectorBlock<const Derived, EssentialPart::SizeAtCompileTime> tail(derived(), 1, size()-1);\n  \n  RealScalar tailSqNorm = size()==1 ? RealScalar(0) : tail.squaredNorm();\n  Scalar c0 = coeff(0);\n  const RealScalar tol = (std::numeric_limits<RealScalar>::min)();\n\n  if(tailSqNorm <= tol && numext::abs2(numext::imag(c0))<=tol)\n  {\n    tau = RealScalar(0);\n    beta = numext::real(c0);\n    essential.setZero();\n  }\n  else\n  {\n    beta = sqrt(numext::abs2(c0) + tailSqNorm);\n    if (numext::real(c0)>=RealScalar(0))\n      beta = -beta;\n    essential = tail / (c0 - beta);\n    tau = conj((beta - c0) / beta);\n  }\n}\n\n/** Apply the elementary reflector H given by\n  * \\f$ H = I - tau v v^*\\f$\n  * with\n  * \\f$ v^T = [1 essential^T] \\f$\n  * from the left to a vector or matrix.\n  *\n  * On input:\n  * \\param essential the essential part of the vector \\c v\n  * \\param tau the scaling factor of the Householder transformation\n  * \\param workspace a pointer to working space with at least\n  *                  this->cols() * essential.size() entries\n  *\n  * \\sa MatrixBase::makeHouseholder(), MatrixBase::makeHouseholderInPlace(), \n  *     MatrixBase::applyHouseholderOnTheRight()\n  */\ntemplate<typename Derived>\ntemplate<typename EssentialPart>\nvoid MatrixBase<Derived>::applyHouseholderOnTheLeft(\n  const EssentialPart& essential,\n  const Scalar& tau,\n  Scalar* workspace)\n{\n  if(rows() == 1)\n  {\n    *this *= Scalar(1)-tau;\n  }\n  else if(tau!=Scalar(0))\n  {\n    Map<typename internal::plain_row_type<PlainObject>::type> tmp(workspace,cols());\n    Block<Derived, EssentialPart::SizeAtCompileTime, Derived::ColsAtCompileTime> bottom(derived(), 1, 0, rows()-1, cols());\n    tmp.noalias() = essential.adjoint() * bottom;\n    tmp += this->row(0);\n    this->row(0) -= tau * tmp;\n    bottom.noalias() -= tau * essential * tmp;\n  }\n}\n\n/** Apply the elementary reflector H given by\n  * \\f$ H = I - tau v v^*\\f$\n  * with\n  * \\f$ v^T = [1 essential^T] \\f$\n  * from the right to a vector or matrix.\n  *\n  * On input:\n  * \\param essential the essential part of the vector \\c v\n  * \\param tau the scaling factor of the Householder transformation\n  * \\param workspace a pointer to working space with at least\n  *                  this->cols() * essential.size() entries\n  *\n  * \\sa MatrixBase::makeHouseholder(), MatrixBase::makeHouseholderInPlace(), \n  *     MatrixBase::applyHouseholderOnTheLeft()\n  */\ntemplate<typename Derived>\ntemplate<typename EssentialPart>\nvoid MatrixBase<Derived>::applyHouseholderOnTheRight(\n  const EssentialPart& essential,\n  const Scalar& tau,\n  Scalar* workspace)\n{\n  if(cols() == 1)\n  {\n    *this *= Scalar(1)-tau;\n  }\n  else if(tau!=Scalar(0))\n  {\n    Map<typename internal::plain_col_type<PlainObject>::type> tmp(workspace,rows());\n    Block<Derived, Derived::RowsAtCompileTime, EssentialPart::SizeAtCompileTime> right(derived(), 0, 1, rows(), cols()-1);\n    tmp.noalias() = right * essential.conjugate();\n    tmp += this->col(0);\n    this->col(0) -= tau * tmp;\n    right.noalias() -= tau * tmp * essential.transpose();\n  }\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_HOUSEHOLDER_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Householder/HouseholderSequence.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2010 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_HOUSEHOLDER_SEQUENCE_H\n#define EIGEN_HOUSEHOLDER_SEQUENCE_H\n\nnamespace Eigen { \n\n/** \\ingroup Householder_Module\n  * \\householder_module\n  * \\class HouseholderSequence\n  * \\brief Sequence of Householder reflections acting on subspaces with decreasing size\n  * \\tparam VectorsType type of matrix containing the Householder vectors\n  * \\tparam CoeffsType  type of vector containing the Householder coefficients\n  * \\tparam Side        either OnTheLeft (the default) or OnTheRight\n  *\n  * This class represents a product sequence of Householder reflections where the first Householder reflection\n  * acts on the whole space, the second Householder reflection leaves the one-dimensional subspace spanned by\n  * the first unit vector invariant, the third Householder reflection leaves the two-dimensional subspace\n  * spanned by the first two unit vectors invariant, and so on up to the last reflection which leaves all but\n  * one dimensions invariant and acts only on the last dimension. Such sequences of Householder reflections\n  * are used in several algorithms to zero out certain parts of a matrix. Indeed, the methods\n  * HessenbergDecomposition::matrixQ(), Tridiagonalization::matrixQ(), HouseholderQR::householderQ(),\n  * and ColPivHouseholderQR::householderQ() all return a %HouseholderSequence.\n  *\n  * More precisely, the class %HouseholderSequence represents an \\f$ n \\times n \\f$ matrix \\f$ H \\f$ of the\n  * form \\f$ H = \\prod_{i=0}^{n-1} H_i \\f$ where the i-th Householder reflection is \\f$ H_i = I - h_i v_i\n  * v_i^* \\f$. The i-th Householder coefficient \\f$ h_i \\f$ is a scalar and the i-th Householder vector \\f$\n  * v_i \\f$ is a vector of the form\n  * \\f[ \n  * v_i = [\\underbrace{0, \\ldots, 0}_{i-1\\mbox{ zeros}}, 1, \\underbrace{*, \\ldots,*}_{n-i\\mbox{ arbitrary entries}} ]. \n  * \\f]\n  * The last \\f$ n-i \\f$ entries of \\f$ v_i \\f$ are called the essential part of the Householder vector.\n  *\n  * Typical usages are listed below, where H is a HouseholderSequence:\n  * \\code\n  * A.applyOnTheRight(H);             // A = A * H\n  * A.applyOnTheLeft(H);              // A = H * A\n  * A.applyOnTheRight(H.adjoint());   // A = A * H^*\n  * A.applyOnTheLeft(H.adjoint());    // A = H^* * A\n  * MatrixXd Q = H;                   // conversion to a dense matrix\n  * \\endcode\n  * In addition to the adjoint, you can also apply the inverse (=adjoint), the transpose, and the conjugate operators.\n  *\n  * See the documentation for HouseholderSequence(const VectorsType&, const CoeffsType&) for an example.\n  *\n  * \\sa MatrixBase::applyOnTheLeft(), MatrixBase::applyOnTheRight()\n  */\n\nnamespace internal {\n\ntemplate<typename VectorsType, typename CoeffsType, int Side>\nstruct traits<HouseholderSequence<VectorsType,CoeffsType,Side> >\n{\n  typedef typename VectorsType::Scalar Scalar;\n  typedef typename VectorsType::StorageIndex StorageIndex;\n  typedef typename VectorsType::StorageKind StorageKind;\n  enum {\n    RowsAtCompileTime = Side==OnTheLeft ? traits<VectorsType>::RowsAtCompileTime\n                                        : traits<VectorsType>::ColsAtCompileTime,\n    ColsAtCompileTime = RowsAtCompileTime,\n    MaxRowsAtCompileTime = Side==OnTheLeft ? traits<VectorsType>::MaxRowsAtCompileTime\n                                           : traits<VectorsType>::MaxColsAtCompileTime,\n    MaxColsAtCompileTime = MaxRowsAtCompileTime,\n    Flags = 0\n  };\n};\n\nstruct HouseholderSequenceShape {};\n\ntemplate<typename VectorsType, typename CoeffsType, int Side>\nstruct evaluator_traits<HouseholderSequence<VectorsType,CoeffsType,Side> >\n  : public evaluator_traits_base<HouseholderSequence<VectorsType,CoeffsType,Side> >\n{\n  typedef HouseholderSequenceShape Shape;\n};\n\ntemplate<typename VectorsType, typename CoeffsType, int Side>\nstruct hseq_side_dependent_impl\n{\n  typedef Block<const VectorsType, Dynamic, 1> EssentialVectorType;\n  typedef HouseholderSequence<VectorsType, CoeffsType, OnTheLeft> HouseholderSequenceType;\n  static inline const EssentialVectorType essentialVector(const HouseholderSequenceType& h, Index k)\n  {\n    Index start = k+1+h.m_shift;\n    return Block<const VectorsType,Dynamic,1>(h.m_vectors, start, k, h.rows()-start, 1);\n  }\n};\n\ntemplate<typename VectorsType, typename CoeffsType>\nstruct hseq_side_dependent_impl<VectorsType, CoeffsType, OnTheRight>\n{\n  typedef Transpose<Block<const VectorsType, 1, Dynamic> > EssentialVectorType;\n  typedef HouseholderSequence<VectorsType, CoeffsType, OnTheRight> HouseholderSequenceType;\n  static inline const EssentialVectorType essentialVector(const HouseholderSequenceType& h, Index k)\n  {\n    Index start = k+1+h.m_shift;\n    return Block<const VectorsType,1,Dynamic>(h.m_vectors, k, start, 1, h.rows()-start).transpose();\n  }\n};\n\ntemplate<typename OtherScalarType, typename MatrixType> struct matrix_type_times_scalar_type\n{\n  typedef typename ScalarBinaryOpTraits<OtherScalarType, typename MatrixType::Scalar>::ReturnType\n    ResultScalar;\n  typedef Matrix<ResultScalar, MatrixType::RowsAtCompileTime, MatrixType::ColsAtCompileTime,\n                 0, MatrixType::MaxRowsAtCompileTime, MatrixType::MaxColsAtCompileTime> Type;\n};\n\n} // end namespace internal\n\ntemplate<typename VectorsType, typename CoeffsType, int Side> class HouseholderSequence\n  : public EigenBase<HouseholderSequence<VectorsType,CoeffsType,Side> >\n{\n    typedef typename internal::hseq_side_dependent_impl<VectorsType,CoeffsType,Side>::EssentialVectorType EssentialVectorType;\n  \n  public:\n    enum {\n      RowsAtCompileTime = internal::traits<HouseholderSequence>::RowsAtCompileTime,\n      ColsAtCompileTime = internal::traits<HouseholderSequence>::ColsAtCompileTime,\n      MaxRowsAtCompileTime = internal::traits<HouseholderSequence>::MaxRowsAtCompileTime,\n      MaxColsAtCompileTime = internal::traits<HouseholderSequence>::MaxColsAtCompileTime\n    };\n    typedef typename internal::traits<HouseholderSequence>::Scalar Scalar;\n\n    typedef HouseholderSequence<\n      typename internal::conditional<NumTraits<Scalar>::IsComplex,\n        typename internal::remove_all<typename VectorsType::ConjugateReturnType>::type,\n        VectorsType>::type,\n      typename internal::conditional<NumTraits<Scalar>::IsComplex,\n        typename internal::remove_all<typename CoeffsType::ConjugateReturnType>::type,\n        CoeffsType>::type,\n      Side\n    > ConjugateReturnType;\n\n    /** \\brief Constructor.\n      * \\param[in]  v      %Matrix containing the essential parts of the Householder vectors\n      * \\param[in]  h      Vector containing the Householder coefficients\n      *\n      * Constructs the Householder sequence with coefficients given by \\p h and vectors given by \\p v. The\n      * i-th Householder coefficient \\f$ h_i \\f$ is given by \\p h(i) and the essential part of the i-th\n      * Householder vector \\f$ v_i \\f$ is given by \\p v(k,i) with \\p k > \\p i (the subdiagonal part of the\n      * i-th column). If \\p v has fewer columns than rows, then the Householder sequence contains as many\n      * Householder reflections as there are columns.\n      *\n      * \\note The %HouseholderSequence object stores \\p v and \\p h by reference.\n      *\n      * Example: \\include HouseholderSequence_HouseholderSequence.cpp\n      * Output: \\verbinclude HouseholderSequence_HouseholderSequence.out\n      *\n      * \\sa setLength(), setShift()\n      */\n    HouseholderSequence(const VectorsType& v, const CoeffsType& h)\n      : m_vectors(v), m_coeffs(h), m_trans(false), m_length(v.diagonalSize()),\n        m_shift(0)\n    {\n    }\n\n    /** \\brief Copy constructor. */\n    HouseholderSequence(const HouseholderSequence& other)\n      : m_vectors(other.m_vectors),\n        m_coeffs(other.m_coeffs),\n        m_trans(other.m_trans),\n        m_length(other.m_length),\n        m_shift(other.m_shift)\n    {\n    }\n\n    /** \\brief Number of rows of transformation viewed as a matrix.\n      * \\returns Number of rows \n      * \\details This equals the dimension of the space that the transformation acts on.\n      */\n    Index rows() const { return Side==OnTheLeft ? m_vectors.rows() : m_vectors.cols(); }\n\n    /** \\brief Number of columns of transformation viewed as a matrix.\n      * \\returns Number of columns\n      * \\details This equals the dimension of the space that the transformation acts on.\n      */\n    Index cols() const { return rows(); }\n\n    /** \\brief Essential part of a Householder vector.\n      * \\param[in]  k  Index of Householder reflection\n      * \\returns    Vector containing non-trivial entries of k-th Householder vector\n      *\n      * This function returns the essential part of the Householder vector \\f$ v_i \\f$. This is a vector of\n      * length \\f$ n-i \\f$ containing the last \\f$ n-i \\f$ entries of the vector\n      * \\f[ \n      * v_i = [\\underbrace{0, \\ldots, 0}_{i-1\\mbox{ zeros}}, 1, \\underbrace{*, \\ldots,*}_{n-i\\mbox{ arbitrary entries}} ]. \n      * \\f]\n      * The index \\f$ i \\f$ equals \\p k + shift(), corresponding to the k-th column of the matrix \\p v\n      * passed to the constructor.\n      *\n      * \\sa setShift(), shift()\n      */\n    const EssentialVectorType essentialVector(Index k) const\n    {\n      eigen_assert(k >= 0 && k < m_length);\n      return internal::hseq_side_dependent_impl<VectorsType,CoeffsType,Side>::essentialVector(*this, k);\n    }\n\n    /** \\brief %Transpose of the Householder sequence. */\n    HouseholderSequence transpose() const\n    {\n      return HouseholderSequence(*this).setTrans(!m_trans);\n    }\n\n    /** \\brief Complex conjugate of the Householder sequence. */\n    ConjugateReturnType conjugate() const\n    {\n      return ConjugateReturnType(m_vectors.conjugate(), m_coeffs.conjugate())\n             .setTrans(m_trans)\n             .setLength(m_length)\n             .setShift(m_shift);\n    }\n\n    /** \\brief Adjoint (conjugate transpose) of the Householder sequence. */\n    ConjugateReturnType adjoint() const\n    {\n      return conjugate().setTrans(!m_trans);\n    }\n\n    /** \\brief Inverse of the Householder sequence (equals the adjoint). */\n    ConjugateReturnType inverse() const { return adjoint(); }\n\n    /** \\internal */\n    template<typename DestType> inline void evalTo(DestType& dst) const\n    {\n      Matrix<Scalar, DestType::RowsAtCompileTime, 1,\n             AutoAlign|ColMajor, DestType::MaxRowsAtCompileTime, 1> workspace(rows());\n      evalTo(dst, workspace);\n    }\n\n    /** \\internal */\n    template<typename Dest, typename Workspace>\n    void evalTo(Dest& dst, Workspace& workspace) const\n    {\n      workspace.resize(rows());\n      Index vecs = m_length;\n      if(internal::is_same_dense(dst,m_vectors))\n      {\n        // in-place\n        dst.diagonal().setOnes();\n        dst.template triangularView<StrictlyUpper>().setZero();\n        for(Index k = vecs-1; k >= 0; --k)\n        {\n          Index cornerSize = rows() - k - m_shift;\n          if(m_trans)\n            dst.bottomRightCorner(cornerSize, cornerSize)\n               .applyHouseholderOnTheRight(essentialVector(k), m_coeffs.coeff(k), workspace.data());\n          else\n            dst.bottomRightCorner(cornerSize, cornerSize)\n               .applyHouseholderOnTheLeft(essentialVector(k), m_coeffs.coeff(k), workspace.data());\n\n          // clear the off diagonal vector\n          dst.col(k).tail(rows()-k-1).setZero();\n        }\n        // clear the remaining columns if needed\n        for(Index k = 0; k<cols()-vecs ; ++k)\n          dst.col(k).tail(rows()-k-1).setZero();\n      }\n      else\n      {\n        dst.setIdentity(rows(), rows());\n        for(Index k = vecs-1; k >= 0; --k)\n        {\n          Index cornerSize = rows() - k - m_shift;\n          if(m_trans)\n            dst.bottomRightCorner(cornerSize, cornerSize)\n               .applyHouseholderOnTheRight(essentialVector(k), m_coeffs.coeff(k), &workspace.coeffRef(0));\n          else\n            dst.bottomRightCorner(cornerSize, cornerSize)\n               .applyHouseholderOnTheLeft(essentialVector(k), m_coeffs.coeff(k), &workspace.coeffRef(0));\n        }\n      }\n    }\n\n    /** \\internal */\n    template<typename Dest> inline void applyThisOnTheRight(Dest& dst) const\n    {\n      Matrix<Scalar,1,Dest::RowsAtCompileTime,RowMajor,1,Dest::MaxRowsAtCompileTime> workspace(dst.rows());\n      applyThisOnTheRight(dst, workspace);\n    }\n\n    /** \\internal */\n    template<typename Dest, typename Workspace>\n    inline void applyThisOnTheRight(Dest& dst, Workspace& workspace) const\n    {\n      workspace.resize(dst.rows());\n      for(Index k = 0; k < m_length; ++k)\n      {\n        Index actual_k = m_trans ? m_length-k-1 : k;\n        dst.rightCols(rows()-m_shift-actual_k)\n           .applyHouseholderOnTheRight(essentialVector(actual_k), m_coeffs.coeff(actual_k), workspace.data());\n      }\n    }\n\n    /** \\internal */\n    template<typename Dest> inline void applyThisOnTheLeft(Dest& dst) const\n    {\n      Matrix<Scalar,1,Dest::ColsAtCompileTime,RowMajor,1,Dest::MaxColsAtCompileTime> workspace;\n      applyThisOnTheLeft(dst, workspace);\n    }\n\n    /** \\internal */\n    template<typename Dest, typename Workspace>\n    inline void applyThisOnTheLeft(Dest& dst, Workspace& workspace) const\n    {\n      const Index BlockSize = 48;\n      // if the entries are large enough, then apply the reflectors by block\n      if(m_length>=BlockSize && dst.cols()>1)\n      {\n        for(Index i = 0; i < m_length; i+=BlockSize)\n        {\n          Index end = m_trans ? (std::min)(m_length,i+BlockSize) : m_length-i;\n          Index k = m_trans ? i : (std::max)(Index(0),end-BlockSize);\n          Index bs = end-k;\n          Index start = k + m_shift;\n          \n          typedef Block<typename internal::remove_all<VectorsType>::type,Dynamic,Dynamic> SubVectorsType;\n          SubVectorsType sub_vecs1(m_vectors.const_cast_derived(), Side==OnTheRight ? k : start,\n                                                                   Side==OnTheRight ? start : k,\n                                                                   Side==OnTheRight ? bs : m_vectors.rows()-start,\n                                                                   Side==OnTheRight ? m_vectors.cols()-start : bs);\n          typename internal::conditional<Side==OnTheRight, Transpose<SubVectorsType>, SubVectorsType&>::type sub_vecs(sub_vecs1);\n          Block<Dest,Dynamic,Dynamic> sub_dst(dst,dst.rows()-rows()+m_shift+k,0, rows()-m_shift-k,dst.cols());\n          apply_block_householder_on_the_left(sub_dst, sub_vecs, m_coeffs.segment(k, bs), !m_trans);\n        }\n      }\n      else\n      {\n        workspace.resize(dst.cols());\n        for(Index k = 0; k < m_length; ++k)\n        {\n          Index actual_k = m_trans ? k : m_length-k-1;\n          dst.bottomRows(rows()-m_shift-actual_k)\n            .applyHouseholderOnTheLeft(essentialVector(actual_k), m_coeffs.coeff(actual_k), workspace.data());\n        }\n      }\n    }\n\n    /** \\brief Computes the product of a Householder sequence with a matrix.\n      * \\param[in]  other  %Matrix being multiplied.\n      * \\returns    Expression object representing the product.\n      *\n      * This function computes \\f$ HM \\f$ where \\f$ H \\f$ is the Householder sequence represented by \\p *this\n      * and \\f$ M \\f$ is the matrix \\p other.\n      */\n    template<typename OtherDerived>\n    typename internal::matrix_type_times_scalar_type<Scalar, OtherDerived>::Type operator*(const MatrixBase<OtherDerived>& other) const\n    {\n      typename internal::matrix_type_times_scalar_type<Scalar, OtherDerived>::Type\n        res(other.template cast<typename internal::matrix_type_times_scalar_type<Scalar,OtherDerived>::ResultScalar>());\n      applyThisOnTheLeft(res);\n      return res;\n    }\n\n    template<typename _VectorsType, typename _CoeffsType, int _Side> friend struct internal::hseq_side_dependent_impl;\n\n    /** \\brief Sets the length of the Householder sequence.\n      * \\param [in]  length  New value for the length.\n      *\n      * By default, the length \\f$ n \\f$ of the Householder sequence \\f$ H = H_0 H_1 \\ldots H_{n-1} \\f$ is set\n      * to the number of columns of the matrix \\p v passed to the constructor, or the number of rows if that\n      * is smaller. After this function is called, the length equals \\p length.\n      *\n      * \\sa length()\n      */\n    HouseholderSequence& setLength(Index length)\n    {\n      m_length = length;\n      return *this;\n    }\n\n    /** \\brief Sets the shift of the Householder sequence.\n      * \\param [in]  shift  New value for the shift.\n      *\n      * By default, a %HouseholderSequence object represents \\f$ H = H_0 H_1 \\ldots H_{n-1} \\f$ and the i-th\n      * column of the matrix \\p v passed to the constructor corresponds to the i-th Householder\n      * reflection. After this function is called, the object represents \\f$ H = H_{\\mathrm{shift}}\n      * H_{\\mathrm{shift}+1} \\ldots H_{n-1} \\f$ and the i-th column of \\p v corresponds to the (shift+i)-th\n      * Householder reflection.\n      *\n      * \\sa shift()\n      */\n    HouseholderSequence& setShift(Index shift)\n    {\n      m_shift = shift;\n      return *this;\n    }\n\n    Index length() const { return m_length; }  /**< \\brief Returns the length of the Householder sequence. */\n    Index shift() const { return m_shift; }    /**< \\brief Returns the shift of the Householder sequence. */\n\n    /* Necessary for .adjoint() and .conjugate() */\n    template <typename VectorsType2, typename CoeffsType2, int Side2> friend class HouseholderSequence;\n\n  protected:\n\n    /** \\brief Sets the transpose flag.\n      * \\param [in]  trans  New value of the transpose flag.\n      *\n      * By default, the transpose flag is not set. If the transpose flag is set, then this object represents \n      * \\f$ H^T = H_{n-1}^T \\ldots H_1^T H_0^T \\f$ instead of \\f$ H = H_0 H_1 \\ldots H_{n-1} \\f$.\n      *\n      * \\sa trans()\n      */\n    HouseholderSequence& setTrans(bool trans)\n    {\n      m_trans = trans;\n      return *this;\n    }\n\n    bool trans() const { return m_trans; }     /**< \\brief Returns the transpose flag. */\n\n    typename VectorsType::Nested m_vectors;\n    typename CoeffsType::Nested m_coeffs;\n    bool m_trans;\n    Index m_length;\n    Index m_shift;\n};\n\n/** \\brief Computes the product of a matrix with a Householder sequence.\n  * \\param[in]  other  %Matrix being multiplied.\n  * \\param[in]  h      %HouseholderSequence being multiplied.\n  * \\returns    Expression object representing the product.\n  *\n  * This function computes \\f$ MH \\f$ where \\f$ M \\f$ is the matrix \\p other and \\f$ H \\f$ is the\n  * Householder sequence represented by \\p h.\n  */\ntemplate<typename OtherDerived, typename VectorsType, typename CoeffsType, int Side>\ntypename internal::matrix_type_times_scalar_type<typename VectorsType::Scalar,OtherDerived>::Type operator*(const MatrixBase<OtherDerived>& other, const HouseholderSequence<VectorsType,CoeffsType,Side>& h)\n{\n  typename internal::matrix_type_times_scalar_type<typename VectorsType::Scalar,OtherDerived>::Type\n    res(other.template cast<typename internal::matrix_type_times_scalar_type<typename VectorsType::Scalar,OtherDerived>::ResultScalar>());\n  h.applyThisOnTheRight(res);\n  return res;\n}\n\n/** \\ingroup Householder_Module \\householder_module\n  * \\brief Convenience function for constructing a Householder sequence. \n  * \\returns A HouseholderSequence constructed from the specified arguments.\n  */\ntemplate<typename VectorsType, typename CoeffsType>\nHouseholderSequence<VectorsType,CoeffsType> householderSequence(const VectorsType& v, const CoeffsType& h)\n{\n  return HouseholderSequence<VectorsType,CoeffsType,OnTheLeft>(v, h);\n}\n\n/** \\ingroup Householder_Module \\householder_module\n  * \\brief Convenience function for constructing a Householder sequence. \n  * \\returns A HouseholderSequence constructed from the specified arguments.\n  * \\details This function differs from householderSequence() in that the template argument \\p OnTheSide of\n  * the constructed HouseholderSequence is set to OnTheRight, instead of the default OnTheLeft.\n  */\ntemplate<typename VectorsType, typename CoeffsType>\nHouseholderSequence<VectorsType,CoeffsType,OnTheRight> rightHouseholderSequence(const VectorsType& v, const CoeffsType& h)\n{\n  return HouseholderSequence<VectorsType,CoeffsType,OnTheRight>(v, h);\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_HOUSEHOLDER_SEQUENCE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/IterativeLinearSolvers/BasicPreconditioners.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2011-2014 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_BASIC_PRECONDITIONERS_H\n#define EIGEN_BASIC_PRECONDITIONERS_H\n\nnamespace Eigen { \n\n/** \\ingroup IterativeLinearSolvers_Module\n  * \\brief A preconditioner based on the digonal entries\n  *\n  * This class allows to approximately solve for A.x = b problems assuming A is a diagonal matrix.\n  * In other words, this preconditioner neglects all off diagonal entries and, in Eigen's language, solves for:\n    \\code\n    A.diagonal().asDiagonal() . x = b\n    \\endcode\n  *\n  * \\tparam _Scalar the type of the scalar.\n  *\n  * \\implsparsesolverconcept\n  *\n  * This preconditioner is suitable for both selfadjoint and general problems.\n  * The diagonal entries are pre-inverted and stored into a dense vector.\n  *\n  * \\note A variant that has yet to be implemented would attempt to preserve the norm of each column.\n  *\n  * \\sa class LeastSquareDiagonalPreconditioner, class ConjugateGradient\n  */\ntemplate <typename _Scalar>\nclass DiagonalPreconditioner\n{\n    typedef _Scalar Scalar;\n    typedef Matrix<Scalar,Dynamic,1> Vector;\n  public:\n    typedef typename Vector::StorageIndex StorageIndex;\n    enum {\n      ColsAtCompileTime = Dynamic,\n      MaxColsAtCompileTime = Dynamic\n    };\n\n    DiagonalPreconditioner() : m_isInitialized(false) {}\n\n    template<typename MatType>\n    explicit DiagonalPreconditioner(const MatType& mat) : m_invdiag(mat.cols())\n    {\n      compute(mat);\n    }\n\n    Index rows() const { return m_invdiag.size(); }\n    Index cols() const { return m_invdiag.size(); }\n    \n    template<typename MatType>\n    DiagonalPreconditioner& analyzePattern(const MatType& )\n    {\n      return *this;\n    }\n    \n    template<typename MatType>\n    DiagonalPreconditioner& factorize(const MatType& mat)\n    {\n      m_invdiag.resize(mat.cols());\n      for(int j=0; j<mat.outerSize(); ++j)\n      {\n        typename MatType::InnerIterator it(mat,j);\n        while(it && it.index()!=j) ++it;\n        if(it && it.index()==j && it.value()!=Scalar(0))\n          m_invdiag(j) = Scalar(1)/it.value();\n        else\n          m_invdiag(j) = Scalar(1);\n      }\n      m_isInitialized = true;\n      return *this;\n    }\n    \n    template<typename MatType>\n    DiagonalPreconditioner& compute(const MatType& mat)\n    {\n      return factorize(mat);\n    }\n\n    /** \\internal */\n    template<typename Rhs, typename Dest>\n    void _solve_impl(const Rhs& b, Dest& x) const\n    {\n      x = m_invdiag.array() * b.array() ;\n    }\n\n    template<typename Rhs> inline const Solve<DiagonalPreconditioner, Rhs>\n    solve(const MatrixBase<Rhs>& b) const\n    {\n      eigen_assert(m_isInitialized && \"DiagonalPreconditioner is not initialized.\");\n      eigen_assert(m_invdiag.size()==b.rows()\n                && \"DiagonalPreconditioner::solve(): invalid number of rows of the right hand side matrix b\");\n      return Solve<DiagonalPreconditioner, Rhs>(*this, b.derived());\n    }\n    \n    ComputationInfo info() { return Success; }\n\n  protected:\n    Vector m_invdiag;\n    bool m_isInitialized;\n};\n\n/** \\ingroup IterativeLinearSolvers_Module\n  * \\brief Jacobi preconditioner for LeastSquaresConjugateGradient\n  *\n  * This class allows to approximately solve for A' A x  = A' b problems assuming A' A is a diagonal matrix.\n  * In other words, this preconditioner neglects all off diagonal entries and, in Eigen's language, solves for:\n    \\code\n    (A.adjoint() * A).diagonal().asDiagonal() * x = b\n    \\endcode\n  *\n  * \\tparam _Scalar the type of the scalar.\n  *\n  * \\implsparsesolverconcept\n  *\n  * The diagonal entries are pre-inverted and stored into a dense vector.\n  * \n  * \\sa class LeastSquaresConjugateGradient, class DiagonalPreconditioner\n  */\ntemplate <typename _Scalar>\nclass LeastSquareDiagonalPreconditioner : public DiagonalPreconditioner<_Scalar>\n{\n    typedef _Scalar Scalar;\n    typedef typename NumTraits<Scalar>::Real RealScalar;\n    typedef DiagonalPreconditioner<_Scalar> Base;\n    using Base::m_invdiag;\n  public:\n\n    LeastSquareDiagonalPreconditioner() : Base() {}\n\n    template<typename MatType>\n    explicit LeastSquareDiagonalPreconditioner(const MatType& mat) : Base()\n    {\n      compute(mat);\n    }\n\n    template<typename MatType>\n    LeastSquareDiagonalPreconditioner& analyzePattern(const MatType& )\n    {\n      return *this;\n    }\n    \n    template<typename MatType>\n    LeastSquareDiagonalPreconditioner& factorize(const MatType& mat)\n    {\n      // Compute the inverse squared-norm of each column of mat\n      m_invdiag.resize(mat.cols());\n      for(Index j=0; j<mat.outerSize(); ++j)\n      {\n        RealScalar sum = mat.innerVector(j).squaredNorm();\n        if(sum>0)\n          m_invdiag(j) = RealScalar(1)/sum;\n        else\n          m_invdiag(j) = RealScalar(1);\n      }\n      Base::m_isInitialized = true;\n      return *this;\n    }\n    \n    template<typename MatType>\n    LeastSquareDiagonalPreconditioner& compute(const MatType& mat)\n    {\n      return factorize(mat);\n    }\n    \n    ComputationInfo info() { return Success; }\n\n  protected:\n};\n\n/** \\ingroup IterativeLinearSolvers_Module\n  * \\brief A naive preconditioner which approximates any matrix as the identity matrix\n  *\n  * \\implsparsesolverconcept\n  *\n  * \\sa class DiagonalPreconditioner\n  */\nclass IdentityPreconditioner\n{\n  public:\n\n    IdentityPreconditioner() {}\n\n    template<typename MatrixType>\n    explicit IdentityPreconditioner(const MatrixType& ) {}\n    \n    template<typename MatrixType>\n    IdentityPreconditioner& analyzePattern(const MatrixType& ) { return *this; }\n    \n    template<typename MatrixType>\n    IdentityPreconditioner& factorize(const MatrixType& ) { return *this; }\n\n    template<typename MatrixType>\n    IdentityPreconditioner& compute(const MatrixType& ) { return *this; }\n    \n    template<typename Rhs>\n    inline const Rhs& solve(const Rhs& b) const { return b; }\n    \n    ComputationInfo info() { return Success; }\n};\n\n} // end namespace Eigen\n\n#endif // EIGEN_BASIC_PRECONDITIONERS_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/IterativeLinearSolvers/BiCGSTAB.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2011-2014 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2012 Désiré Nuentsa-Wakam <desire.nuentsa_wakam@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_BICGSTAB_H\n#define EIGEN_BICGSTAB_H\n\nnamespace Eigen { \n\nnamespace internal {\n\n/** \\internal Low-level bi conjugate gradient stabilized algorithm\n  * \\param mat The matrix A\n  * \\param rhs The right hand side vector b\n  * \\param x On input and initial solution, on output the computed solution.\n  * \\param precond A preconditioner being able to efficiently solve for an\n  *                approximation of Ax=b (regardless of b)\n  * \\param iters On input the max number of iteration, on output the number of performed iterations.\n  * \\param tol_error On input the tolerance error, on output an estimation of the relative error.\n  * \\return false in the case of numerical issue, for example a break down of BiCGSTAB. \n  */\ntemplate<typename MatrixType, typename Rhs, typename Dest, typename Preconditioner>\nbool bicgstab(const MatrixType& mat, const Rhs& rhs, Dest& x,\n              const Preconditioner& precond, Index& iters,\n              typename Dest::RealScalar& tol_error)\n{\n  using std::sqrt;\n  using std::abs;\n  typedef typename Dest::RealScalar RealScalar;\n  typedef typename Dest::Scalar Scalar;\n  typedef Matrix<Scalar,Dynamic,1> VectorType;\n  RealScalar tol = tol_error;\n  Index maxIters = iters;\n\n  Index n = mat.cols();\n  VectorType r  = rhs - mat * x;\n  VectorType r0 = r;\n  \n  RealScalar r0_sqnorm = r0.squaredNorm();\n  RealScalar rhs_sqnorm = rhs.squaredNorm();\n  if(rhs_sqnorm == 0)\n  {\n    x.setZero();\n    return true;\n  }\n  Scalar rho    = 1;\n  Scalar alpha  = 1;\n  Scalar w      = 1;\n  \n  VectorType v = VectorType::Zero(n), p = VectorType::Zero(n);\n  VectorType y(n),  z(n);\n  VectorType kt(n), ks(n);\n\n  VectorType s(n), t(n);\n\n  RealScalar tol2 = tol*tol*rhs_sqnorm;\n  RealScalar eps2 = NumTraits<Scalar>::epsilon()*NumTraits<Scalar>::epsilon();\n  Index i = 0;\n  Index restarts = 0;\n\n  while ( r.squaredNorm() > tol2 && i<maxIters )\n  {\n    Scalar rho_old = rho;\n\n    rho = r0.dot(r);\n    if (abs(rho) < eps2*r0_sqnorm)\n    {\n      // The new residual vector became too orthogonal to the arbitrarily chosen direction r0\n      // Let's restart with a new r0:\n      r  = rhs - mat * x;\n      r0 = r;\n      rho = r0_sqnorm = r.squaredNorm();\n      if(restarts++ == 0)\n        i = 0;\n    }\n    Scalar beta = (rho/rho_old) * (alpha / w);\n    p = r + beta * (p - w * v);\n    \n    y = precond.solve(p);\n    \n    v.noalias() = mat * y;\n\n    alpha = rho / r0.dot(v);\n    s = r - alpha * v;\n\n    z = precond.solve(s);\n    t.noalias() = mat * z;\n\n    RealScalar tmp = t.squaredNorm();\n    if(tmp>RealScalar(0))\n      w = t.dot(s) / tmp;\n    else\n      w = Scalar(0);\n    x += alpha * y + w * z;\n    r = s - w * t;\n    ++i;\n  }\n  tol_error = sqrt(r.squaredNorm()/rhs_sqnorm);\n  iters = i;\n  return true; \n}\n\n}\n\ntemplate< typename _MatrixType,\n          typename _Preconditioner = DiagonalPreconditioner<typename _MatrixType::Scalar> >\nclass BiCGSTAB;\n\nnamespace internal {\n\ntemplate< typename _MatrixType, typename _Preconditioner>\nstruct traits<BiCGSTAB<_MatrixType,_Preconditioner> >\n{\n  typedef _MatrixType MatrixType;\n  typedef _Preconditioner Preconditioner;\n};\n\n}\n\n/** \\ingroup IterativeLinearSolvers_Module\n  * \\brief A bi conjugate gradient stabilized solver for sparse square problems\n  *\n  * This class allows to solve for A.x = b sparse linear problems using a bi conjugate gradient\n  * stabilized algorithm. The vectors x and b can be either dense or sparse.\n  *\n  * \\tparam _MatrixType the type of the sparse matrix A, can be a dense or a sparse matrix.\n  * \\tparam _Preconditioner the type of the preconditioner. Default is DiagonalPreconditioner\n  *\n  * \\implsparsesolverconcept\n  *\n  * The maximal number of iterations and tolerance value can be controlled via the setMaxIterations()\n  * and setTolerance() methods. The defaults are the size of the problem for the maximal number of iterations\n  * and NumTraits<Scalar>::epsilon() for the tolerance.\n  * \n  * The tolerance corresponds to the relative residual error: |Ax-b|/|b|\n  * \n  * \\b Performance: when using sparse matrices, best performance is achied for a row-major sparse matrix format.\n  * Moreover, in this case multi-threading can be exploited if the user code is compiled with OpenMP enabled.\n  * See \\ref TopicMultiThreading for details.\n  * \n  * This class can be used as the direct solver classes. Here is a typical usage example:\n  * \\include BiCGSTAB_simple.cpp\n  * \n  * By default the iterations start with x=0 as an initial guess of the solution.\n  * One can control the start using the solveWithGuess() method.\n  * \n  * BiCGSTAB can also be used in a matrix-free context, see the following \\link MatrixfreeSolverExample example \\endlink.\n  *\n  * \\sa class SimplicialCholesky, DiagonalPreconditioner, IdentityPreconditioner\n  */\ntemplate< typename _MatrixType, typename _Preconditioner>\nclass BiCGSTAB : public IterativeSolverBase<BiCGSTAB<_MatrixType,_Preconditioner> >\n{\n  typedef IterativeSolverBase<BiCGSTAB> Base;\n  using Base::matrix;\n  using Base::m_error;\n  using Base::m_iterations;\n  using Base::m_info;\n  using Base::m_isInitialized;\npublic:\n  typedef _MatrixType MatrixType;\n  typedef typename MatrixType::Scalar Scalar;\n  typedef typename MatrixType::RealScalar RealScalar;\n  typedef _Preconditioner Preconditioner;\n\npublic:\n\n  /** Default constructor. */\n  BiCGSTAB() : Base() {}\n\n  /** Initialize the solver with matrix \\a A for further \\c Ax=b solving.\n    * \n    * This constructor is a shortcut for the default constructor followed\n    * by a call to compute().\n    * \n    * \\warning this class stores a reference to the matrix A as well as some\n    * precomputed values that depend on it. Therefore, if \\a A is changed\n    * this class becomes invalid. Call compute() to update it with the new\n    * matrix A, or modify a copy of A.\n    */\n  template<typename MatrixDerived>\n  explicit BiCGSTAB(const EigenBase<MatrixDerived>& A) : Base(A.derived()) {}\n\n  ~BiCGSTAB() {}\n\n  /** \\internal */\n  template<typename Rhs,typename Dest>\n  void _solve_with_guess_impl(const Rhs& b, Dest& x) const\n  {    \n    bool failed = false;\n    for(Index j=0; j<b.cols(); ++j)\n    {\n      m_iterations = Base::maxIterations();\n      m_error = Base::m_tolerance;\n      \n      typename Dest::ColXpr xj(x,j);\n      if(!internal::bicgstab(matrix(), b.col(j), xj, Base::m_preconditioner, m_iterations, m_error))\n        failed = true;\n    }\n    m_info = failed ? NumericalIssue\n           : m_error <= Base::m_tolerance ? Success\n           : NoConvergence;\n    m_isInitialized = true;\n  }\n\n  /** \\internal */\n  using Base::_solve_impl;\n  template<typename Rhs,typename Dest>\n  void _solve_impl(const MatrixBase<Rhs>& b, Dest& x) const\n  {\n    x.resize(this->rows(),b.cols());\n    x.setZero();\n    _solve_with_guess_impl(b,x);\n  }\n\nprotected:\n\n};\n\n} // end namespace Eigen\n\n#endif // EIGEN_BICGSTAB_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/IterativeLinearSolvers/ConjugateGradient.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2011-2014 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_CONJUGATE_GRADIENT_H\n#define EIGEN_CONJUGATE_GRADIENT_H\n\nnamespace Eigen { \n\nnamespace internal {\n\n/** \\internal Low-level conjugate gradient algorithm\n  * \\param mat The matrix A\n  * \\param rhs The right hand side vector b\n  * \\param x On input and initial solution, on output the computed solution.\n  * \\param precond A preconditioner being able to efficiently solve for an\n  *                approximation of Ax=b (regardless of b)\n  * \\param iters On input the max number of iteration, on output the number of performed iterations.\n  * \\param tol_error On input the tolerance error, on output an estimation of the relative error.\n  */\ntemplate<typename MatrixType, typename Rhs, typename Dest, typename Preconditioner>\nEIGEN_DONT_INLINE\nvoid conjugate_gradient(const MatrixType& mat, const Rhs& rhs, Dest& x,\n                        const Preconditioner& precond, Index& iters,\n                        typename Dest::RealScalar& tol_error)\n{\n  using std::sqrt;\n  using std::abs;\n  typedef typename Dest::RealScalar RealScalar;\n  typedef typename Dest::Scalar Scalar;\n  typedef Matrix<Scalar,Dynamic,1> VectorType;\n  \n  RealScalar tol = tol_error;\n  Index maxIters = iters;\n  \n  Index n = mat.cols();\n\n  VectorType residual = rhs - mat * x; //initial residual\n\n  RealScalar rhsNorm2 = rhs.squaredNorm();\n  if(rhsNorm2 == 0) \n  {\n    x.setZero();\n    iters = 0;\n    tol_error = 0;\n    return;\n  }\n  RealScalar threshold = tol*tol*rhsNorm2;\n  RealScalar residualNorm2 = residual.squaredNorm();\n  if (residualNorm2 < threshold)\n  {\n    iters = 0;\n    tol_error = sqrt(residualNorm2 / rhsNorm2);\n    return;\n  }\n  \n  VectorType p(n);\n  p = precond.solve(residual);      // initial search direction\n\n  VectorType z(n), tmp(n);\n  RealScalar absNew = numext::real(residual.dot(p));  // the square of the absolute value of r scaled by invM\n  Index i = 0;\n  while(i < maxIters)\n  {\n    tmp.noalias() = mat * p;                    // the bottleneck of the algorithm\n\n    Scalar alpha = absNew / p.dot(tmp);         // the amount we travel on dir\n    x += alpha * p;                             // update solution\n    residual -= alpha * tmp;                    // update residual\n    \n    residualNorm2 = residual.squaredNorm();\n    if(residualNorm2 < threshold)\n      break;\n    \n    z = precond.solve(residual);                // approximately solve for \"A z = residual\"\n\n    RealScalar absOld = absNew;\n    absNew = numext::real(residual.dot(z));     // update the absolute value of r\n    RealScalar beta = absNew / absOld;          // calculate the Gram-Schmidt value used to create the new search direction\n    p = z + beta * p;                           // update search direction\n    i++;\n  }\n  tol_error = sqrt(residualNorm2 / rhsNorm2);\n  iters = i;\n}\n\n}\n\ntemplate< typename _MatrixType, int _UpLo=Lower,\n          typename _Preconditioner = DiagonalPreconditioner<typename _MatrixType::Scalar> >\nclass ConjugateGradient;\n\nnamespace internal {\n\ntemplate< typename _MatrixType, int _UpLo, typename _Preconditioner>\nstruct traits<ConjugateGradient<_MatrixType,_UpLo,_Preconditioner> >\n{\n  typedef _MatrixType MatrixType;\n  typedef _Preconditioner Preconditioner;\n};\n\n}\n\n/** \\ingroup IterativeLinearSolvers_Module\n  * \\brief A conjugate gradient solver for sparse (or dense) self-adjoint problems\n  *\n  * This class allows to solve for A.x = b linear problems using an iterative conjugate gradient algorithm.\n  * The matrix A must be selfadjoint. The matrix A and the vectors x and b can be either dense or sparse.\n  *\n  * \\tparam _MatrixType the type of the matrix A, can be a dense or a sparse matrix.\n  * \\tparam _UpLo the triangular part that will be used for the computations. It can be Lower,\n  *               \\c Upper, or \\c Lower|Upper in which the full matrix entries will be considered.\n  *               Default is \\c Lower, best performance is \\c Lower|Upper.\n  * \\tparam _Preconditioner the type of the preconditioner. Default is DiagonalPreconditioner\n  *\n  * \\implsparsesolverconcept\n  *\n  * The maximal number of iterations and tolerance value can be controlled via the setMaxIterations()\n  * and setTolerance() methods. The defaults are the size of the problem for the maximal number of iterations\n  * and NumTraits<Scalar>::epsilon() for the tolerance.\n  * \n  * The tolerance corresponds to the relative residual error: |Ax-b|/|b|\n  * \n  * \\b Performance: Even though the default value of \\c _UpLo is \\c Lower, significantly higher performance is\n  * achieved when using a complete matrix and \\b Lower|Upper as the \\a _UpLo template parameter. Moreover, in this\n  * case multi-threading can be exploited if the user code is compiled with OpenMP enabled.\n  * See \\ref TopicMultiThreading for details.\n  * \n  * This class can be used as the direct solver classes. Here is a typical usage example:\n    \\code\n    int n = 10000;\n    VectorXd x(n), b(n);\n    SparseMatrix<double> A(n,n);\n    // fill A and b\n    ConjugateGradient<SparseMatrix<double>, Lower|Upper> cg;\n    cg.compute(A);\n    x = cg.solve(b);\n    std::cout << \"#iterations:     \" << cg.iterations() << std::endl;\n    std::cout << \"estimated error: \" << cg.error()      << std::endl;\n    // update b, and solve again\n    x = cg.solve(b);\n    \\endcode\n  * \n  * By default the iterations start with x=0 as an initial guess of the solution.\n  * One can control the start using the solveWithGuess() method.\n  * \n  * ConjugateGradient can also be used in a matrix-free context, see the following \\link MatrixfreeSolverExample example \\endlink.\n  *\n  * \\sa class LeastSquaresConjugateGradient, class SimplicialCholesky, DiagonalPreconditioner, IdentityPreconditioner\n  */\ntemplate< typename _MatrixType, int _UpLo, typename _Preconditioner>\nclass ConjugateGradient : public IterativeSolverBase<ConjugateGradient<_MatrixType,_UpLo,_Preconditioner> >\n{\n  typedef IterativeSolverBase<ConjugateGradient> Base;\n  using Base::matrix;\n  using Base::m_error;\n  using Base::m_iterations;\n  using Base::m_info;\n  using Base::m_isInitialized;\npublic:\n  typedef _MatrixType MatrixType;\n  typedef typename MatrixType::Scalar Scalar;\n  typedef typename MatrixType::RealScalar RealScalar;\n  typedef _Preconditioner Preconditioner;\n\n  enum {\n    UpLo = _UpLo\n  };\n\npublic:\n\n  /** Default constructor. */\n  ConjugateGradient() : Base() {}\n\n  /** Initialize the solver with matrix \\a A for further \\c Ax=b solving.\n    * \n    * This constructor is a shortcut for the default constructor followed\n    * by a call to compute().\n    * \n    * \\warning this class stores a reference to the matrix A as well as some\n    * precomputed values that depend on it. Therefore, if \\a A is changed\n    * this class becomes invalid. Call compute() to update it with the new\n    * matrix A, or modify a copy of A.\n    */\n  template<typename MatrixDerived>\n  explicit ConjugateGradient(const EigenBase<MatrixDerived>& A) : Base(A.derived()) {}\n\n  ~ConjugateGradient() {}\n\n  /** \\internal */\n  template<typename Rhs,typename Dest>\n  void _solve_with_guess_impl(const Rhs& b, Dest& x) const\n  {\n    typedef typename Base::MatrixWrapper MatrixWrapper;\n    typedef typename Base::ActualMatrixType ActualMatrixType;\n    enum {\n      TransposeInput  =   (!MatrixWrapper::MatrixFree)\n                      &&  (UpLo==(Lower|Upper))\n                      &&  (!MatrixType::IsRowMajor)\n                      &&  (!NumTraits<Scalar>::IsComplex)\n    };\n    typedef typename internal::conditional<TransposeInput,Transpose<const ActualMatrixType>, ActualMatrixType const&>::type RowMajorWrapper;\n    EIGEN_STATIC_ASSERT(EIGEN_IMPLIES(MatrixWrapper::MatrixFree,UpLo==(Lower|Upper)),MATRIX_FREE_CONJUGATE_GRADIENT_IS_COMPATIBLE_WITH_UPPER_UNION_LOWER_MODE_ONLY);\n    typedef typename internal::conditional<UpLo==(Lower|Upper),\n                                           RowMajorWrapper,\n                                           typename MatrixWrapper::template ConstSelfAdjointViewReturnType<UpLo>::Type\n                                          >::type SelfAdjointWrapper;\n    m_iterations = Base::maxIterations();\n    m_error = Base::m_tolerance;\n\n    for(Index j=0; j<b.cols(); ++j)\n    {\n      m_iterations = Base::maxIterations();\n      m_error = Base::m_tolerance;\n\n      typename Dest::ColXpr xj(x,j);\n      RowMajorWrapper row_mat(matrix());\n      internal::conjugate_gradient(SelfAdjointWrapper(row_mat), b.col(j), xj, Base::m_preconditioner, m_iterations, m_error);\n    }\n\n    m_isInitialized = true;\n    m_info = m_error <= Base::m_tolerance ? Success : NoConvergence;\n  }\n  \n  /** \\internal */\n  using Base::_solve_impl;\n  template<typename Rhs,typename Dest>\n  void _solve_impl(const MatrixBase<Rhs>& b, Dest& x) const\n  {\n    x.setZero();\n    _solve_with_guess_impl(b.derived(),x);\n  }\n\nprotected:\n\n};\n\n} // end namespace Eigen\n\n#endif // EIGEN_CONJUGATE_GRADIENT_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/IterativeLinearSolvers/IncompleteCholesky.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2012 Désiré Nuentsa-Wakam <desire.nuentsa_wakam@inria.fr>\n// Copyright (C) 2015 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_INCOMPLETE_CHOlESKY_H\n#define EIGEN_INCOMPLETE_CHOlESKY_H\n\n#include <vector>\n#include <list>\n\nnamespace Eigen {  \n/** \n  * \\brief Modified Incomplete Cholesky with dual threshold\n  *\n  * References : C-J. Lin and J. J. Moré, Incomplete Cholesky Factorizations with\n  *              Limited memory, SIAM J. Sci. Comput.  21(1), pp. 24-45, 1999\n  *\n  * \\tparam Scalar the scalar type of the input matrices\n  * \\tparam _UpLo The triangular part that will be used for the computations. It can be Lower\n    *               or Upper. Default is Lower.\n  * \\tparam _OrderingType The ordering method to use, either AMDOrdering<> or NaturalOrdering<>. Default is AMDOrdering<int>,\n  *                       unless EIGEN_MPL2_ONLY is defined, in which case the default is NaturalOrdering<int>.\n  *\n  * \\implsparsesolverconcept\n  *\n  * It performs the following incomplete factorization: \\f$ S P A P' S \\approx L L' \\f$\n  * where L is a lower triangular factor, S is a diagonal scaling matrix, and P is a\n  * fill-in reducing permutation as computed by the ordering method.\n  *\n  * \\b Shifting \\b strategy: Let \\f$ B = S P A P' S \\f$  be the scaled matrix on which the factorization is carried out,\n  * and \\f$ \\beta \\f$ be the minimum value of the diagonal. If \\f$ \\beta > 0 \\f$ then, the factorization is directly performed\n  * on the matrix B. Otherwise, the factorization is performed on the shifted matrix \\f$ B + (\\sigma+|\\beta| I \\f$ where\n  * \\f$ \\sigma \\f$ is the initial shift value as returned and set by setInitialShift() method. The default value is \\f$ \\sigma = 10^{-3} \\f$.\n  * If the factorization fails, then the shift in doubled until it succeed or a maximum of ten attempts. If it still fails, as returned by\n  * the info() method, then you can either increase the initial shift, or better use another preconditioning technique.\n  *\n  */\ntemplate <typename Scalar, int _UpLo = Lower, typename _OrderingType =\n#ifndef EIGEN_MPL2_ONLY\nAMDOrdering<int>\n#else\nNaturalOrdering<int>\n#endif\n>\nclass IncompleteCholesky : public SparseSolverBase<IncompleteCholesky<Scalar,_UpLo,_OrderingType> >\n{\n  protected:\n    typedef SparseSolverBase<IncompleteCholesky<Scalar,_UpLo,_OrderingType> > Base;\n    using Base::m_isInitialized;\n  public:\n    typedef typename NumTraits<Scalar>::Real RealScalar; \n    typedef _OrderingType OrderingType;\n    typedef typename OrderingType::PermutationType PermutationType;\n    typedef typename PermutationType::StorageIndex StorageIndex; \n    typedef SparseMatrix<Scalar,ColMajor,StorageIndex> FactorType;\n    typedef Matrix<Scalar,Dynamic,1> VectorSx;\n    typedef Matrix<RealScalar,Dynamic,1> VectorRx;\n    typedef Matrix<StorageIndex,Dynamic, 1> VectorIx;\n    typedef std::vector<std::list<StorageIndex> > VectorList; \n    enum { UpLo = _UpLo };\n    enum {\n      ColsAtCompileTime = Dynamic,\n      MaxColsAtCompileTime = Dynamic\n    };\n  public:\n\n    /** Default constructor leaving the object in a partly non-initialized stage.\n      *\n      * You must call compute() or the pair analyzePattern()/factorize() to make it valid.\n      *\n      * \\sa IncompleteCholesky(const MatrixType&)\n      */\n    IncompleteCholesky() : m_initialShift(1e-3),m_factorizationIsOk(false) {}\n    \n    /** Constructor computing the incomplete factorization for the given matrix \\a matrix.\n      */\n    template<typename MatrixType>\n    IncompleteCholesky(const MatrixType& matrix) : m_initialShift(1e-3),m_factorizationIsOk(false)\n    {\n      compute(matrix);\n    }\n    \n    /** \\returns number of rows of the factored matrix */\n    Index rows() const { return m_L.rows(); }\n    \n    /** \\returns number of columns of the factored matrix */\n    Index cols() const { return m_L.cols(); }\n    \n\n    /** \\brief Reports whether previous computation was successful.\n      *\n      * It triggers an assertion if \\c *this has not been initialized through the respective constructor,\n      * or a call to compute() or analyzePattern().\n      *\n      * \\returns \\c Success if computation was successful,\n      *          \\c NumericalIssue if the matrix appears to be negative.\n      */\n    ComputationInfo info() const\n    {\n      eigen_assert(m_isInitialized && \"IncompleteCholesky is not initialized.\");\n      return m_info;\n    }\n    \n    /** \\brief Set the initial shift parameter \\f$ \\sigma \\f$.\n      */\n    void setInitialShift(RealScalar shift) { m_initialShift = shift; }\n    \n    /** \\brief Computes the fill reducing permutation vector using the sparsity pattern of \\a mat\n      */\n    template<typename MatrixType>\n    void analyzePattern(const MatrixType& mat)\n    {\n      OrderingType ord; \n      PermutationType pinv;\n      ord(mat.template selfadjointView<UpLo>(), pinv); \n      if(pinv.size()>0) m_perm = pinv.inverse();\n      else              m_perm.resize(0);\n      m_L.resize(mat.rows(), mat.cols());\n      m_analysisIsOk = true;\n      m_isInitialized = true;\n      m_info = Success;\n    }\n    \n    /** \\brief Performs the numerical factorization of the input matrix \\a mat\n      *\n      * The method analyzePattern() or compute() must have been called beforehand\n      * with a matrix having the same pattern.\n      *\n      * \\sa compute(), analyzePattern()\n      */\n    template<typename MatrixType>\n    void factorize(const MatrixType& mat);\n    \n    /** Computes or re-computes the incomplete Cholesky factorization of the input matrix \\a mat\n      *\n      * It is a shortcut for a sequential call to the analyzePattern() and factorize() methods.\n      *\n      * \\sa analyzePattern(), factorize()\n      */\n    template<typename MatrixType>\n    void compute(const MatrixType& mat)\n    {\n      analyzePattern(mat);\n      factorize(mat);\n    }\n    \n    // internal\n    template<typename Rhs, typename Dest>\n    void _solve_impl(const Rhs& b, Dest& x) const\n    {\n      eigen_assert(m_factorizationIsOk && \"factorize() should be called first\");\n      if (m_perm.rows() == b.rows())  x = m_perm * b;\n      else                            x = b;\n      x = m_scale.asDiagonal() * x;\n      x = m_L.template triangularView<Lower>().solve(x);\n      x = m_L.adjoint().template triangularView<Upper>().solve(x);\n      x = m_scale.asDiagonal() * x;\n      if (m_perm.rows() == b.rows())\n        x = m_perm.inverse() * x;\n    }\n\n    /** \\returns the sparse lower triangular factor L */\n    const FactorType& matrixL() const { eigen_assert(\"m_factorizationIsOk\"); return m_L; }\n\n    /** \\returns a vector representing the scaling factor S */\n    const VectorRx& scalingS() const { eigen_assert(\"m_factorizationIsOk\"); return m_scale; }\n\n    /** \\returns the fill-in reducing permutation P (can be empty for a natural ordering) */\n    const PermutationType& permutationP() const { eigen_assert(\"m_analysisIsOk\"); return m_perm; }\n\n  protected:\n    FactorType m_L;              // The lower part stored in CSC\n    VectorRx m_scale;            // The vector for scaling the matrix \n    RealScalar m_initialShift;   // The initial shift parameter\n    bool m_analysisIsOk; \n    bool m_factorizationIsOk; \n    ComputationInfo m_info;\n    PermutationType m_perm; \n\n  private:\n    inline void updateList(Ref<const VectorIx> colPtr, Ref<VectorIx> rowIdx, Ref<VectorSx> vals, const Index& col, const Index& jk, VectorIx& firstElt, VectorList& listCol); \n}; \n\n// Based on the following paper:\n//   C-J. Lin and J. J. Moré, Incomplete Cholesky Factorizations with\n//   Limited memory, SIAM J. Sci. Comput.  21(1), pp. 24-45, 1999\n//   http://ftp.mcs.anl.gov/pub/tech_reports/reports/P682.pdf\ntemplate<typename Scalar, int _UpLo, typename OrderingType>\ntemplate<typename _MatrixType>\nvoid IncompleteCholesky<Scalar,_UpLo, OrderingType>::factorize(const _MatrixType& mat)\n{\n  using std::sqrt;\n  eigen_assert(m_analysisIsOk && \"analyzePattern() should be called first\"); \n    \n  // Dropping strategy : Keep only the p largest elements per column, where p is the number of elements in the column of the original matrix. Other strategies will be added\n  \n  // Apply the fill-reducing permutation computed in analyzePattern()\n  if (m_perm.rows() == mat.rows() ) // To detect the null permutation\n  {\n    // The temporary is needed to make sure that the diagonal entry is properly sorted\n    FactorType tmp(mat.rows(), mat.cols());\n    tmp = mat.template selfadjointView<_UpLo>().twistedBy(m_perm);\n    m_L.template selfadjointView<Lower>() = tmp.template selfadjointView<Lower>();\n  }\n  else\n  {\n    m_L.template selfadjointView<Lower>() = mat.template selfadjointView<_UpLo>();\n  }\n  \n  Index n = m_L.cols(); \n  Index nnz = m_L.nonZeros();\n  Map<VectorSx> vals(m_L.valuePtr(), nnz);         //values\n  Map<VectorIx> rowIdx(m_L.innerIndexPtr(), nnz);  //Row indices\n  Map<VectorIx> colPtr( m_L.outerIndexPtr(), n+1); // Pointer to the beginning of each row\n  VectorIx firstElt(n-1); // for each j, points to the next entry in vals that will be used in the factorization\n  VectorList listCol(n);  // listCol(j) is a linked list of columns to update column j\n  VectorSx col_vals(n);   // Store a  nonzero values in each column\n  VectorIx col_irow(n);   // Row indices of nonzero elements in each column\n  VectorIx col_pattern(n);\n  col_pattern.fill(-1);\n  StorageIndex col_nnz;\n  \n  \n  // Computes the scaling factors \n  m_scale.resize(n);\n  m_scale.setZero();\n  for (Index j = 0; j < n; j++)\n    for (Index k = colPtr[j]; k < colPtr[j+1]; k++)\n    {\n      m_scale(j) += numext::abs2(vals(k));\n      if(rowIdx[k]!=j)\n        m_scale(rowIdx[k]) += numext::abs2(vals(k));\n    }\n  \n  m_scale = m_scale.cwiseSqrt().cwiseSqrt();\n\n  for (Index j = 0; j < n; ++j)\n    if(m_scale(j)>(std::numeric_limits<RealScalar>::min)())\n      m_scale(j) = RealScalar(1)/m_scale(j);\n    else\n      m_scale(j) = 1;\n\n  // TODO disable scaling if not needed, i.e., if it is roughly uniform? (this will make solve() faster)\n  \n  // Scale and compute the shift for the matrix \n  RealScalar mindiag = NumTraits<RealScalar>::highest();\n  for (Index j = 0; j < n; j++)\n  {\n    for (Index k = colPtr[j]; k < colPtr[j+1]; k++)\n      vals[k] *= (m_scale(j)*m_scale(rowIdx[k]));\n    eigen_internal_assert(rowIdx[colPtr[j]]==j && \"IncompleteCholesky: only the lower triangular part must be stored\");\n    mindiag = numext::mini(numext::real(vals[colPtr[j]]), mindiag);\n  }\n\n  FactorType L_save = m_L;\n  \n  RealScalar shift = 0;\n  if(mindiag <= RealScalar(0.))\n    shift = m_initialShift - mindiag;\n\n  m_info = NumericalIssue;\n\n  // Try to perform the incomplete factorization using the current shift\n  int iter = 0;\n  do\n  {\n    // Apply the shift to the diagonal elements of the matrix\n    for (Index j = 0; j < n; j++)\n      vals[colPtr[j]] += shift;\n\n    // jki version of the Cholesky factorization\n    Index j=0;\n    for (; j < n; ++j)\n    {\n      // Left-looking factorization of the j-th column\n      // First, load the j-th column into col_vals\n      Scalar diag = vals[colPtr[j]];  // It is assumed that only the lower part is stored\n      col_nnz = 0;\n      for (Index i = colPtr[j] + 1; i < colPtr[j+1]; i++)\n      {\n        StorageIndex l = rowIdx[i];\n        col_vals(col_nnz) = vals[i];\n        col_irow(col_nnz) = l;\n        col_pattern(l) = col_nnz;\n        col_nnz++;\n      }\n      {\n        typename std::list<StorageIndex>::iterator k;\n        // Browse all previous columns that will update column j\n        for(k = listCol[j].begin(); k != listCol[j].end(); k++)\n        {\n          Index jk = firstElt(*k); // First element to use in the column\n          eigen_internal_assert(rowIdx[jk]==j);\n          Scalar v_j_jk = numext::conj(vals[jk]);\n\n          jk += 1;\n          for (Index i = jk; i < colPtr[*k+1]; i++)\n          {\n            StorageIndex l = rowIdx[i];\n            if(col_pattern[l]<0)\n            {\n              col_vals(col_nnz) = vals[i] * v_j_jk;\n              col_irow[col_nnz] = l;\n              col_pattern(l) = col_nnz;\n              col_nnz++;\n            }\n            else\n              col_vals(col_pattern[l]) -= vals[i] * v_j_jk;\n          }\n          updateList(colPtr,rowIdx,vals, *k, jk, firstElt, listCol);\n        }\n      }\n\n      // Scale the current column\n      if(numext::real(diag) <= 0)\n      {\n        if(++iter>=10)\n          return;\n\n        // increase shift\n        shift = numext::maxi(m_initialShift,RealScalar(2)*shift);\n        // restore m_L, col_pattern, and listCol\n        vals = Map<const VectorSx>(L_save.valuePtr(), nnz);\n        rowIdx = Map<const VectorIx>(L_save.innerIndexPtr(), nnz);\n        colPtr = Map<const VectorIx>(L_save.outerIndexPtr(), n+1);\n        col_pattern.fill(-1);\n        for(Index i=0; i<n; ++i)\n          listCol[i].clear();\n\n        break;\n      }\n\n      RealScalar rdiag = sqrt(numext::real(diag));\n      vals[colPtr[j]] = rdiag;\n      for (Index k = 0; k<col_nnz; ++k)\n      {\n        Index i = col_irow[k];\n        //Scale\n        col_vals(k) /= rdiag;\n        //Update the remaining diagonals with col_vals\n        vals[colPtr[i]] -= numext::abs2(col_vals(k));\n      }\n      // Select the largest p elements\n      // p is the original number of elements in the column (without the diagonal)\n      Index p = colPtr[j+1] - colPtr[j] - 1 ;\n      Ref<VectorSx> cvals = col_vals.head(col_nnz);\n      Ref<VectorIx> cirow = col_irow.head(col_nnz);\n      internal::QuickSplit(cvals,cirow, p);\n      // Insert the largest p elements in the matrix\n      Index cpt = 0;\n      for (Index i = colPtr[j]+1; i < colPtr[j+1]; i++)\n      {\n        vals[i] = col_vals(cpt);\n        rowIdx[i] = col_irow(cpt);\n        // restore col_pattern:\n        col_pattern(col_irow(cpt)) = -1;\n        cpt++;\n      }\n      // Get the first smallest row index and put it after the diagonal element\n      Index jk = colPtr(j)+1;\n      updateList(colPtr,rowIdx,vals,j,jk,firstElt,listCol);\n    }\n\n    if(j==n)\n    {\n      m_factorizationIsOk = true;\n      m_info = Success;\n    }\n  } while(m_info!=Success);\n}\n\ntemplate<typename Scalar, int _UpLo, typename OrderingType>\ninline void IncompleteCholesky<Scalar,_UpLo, OrderingType>::updateList(Ref<const VectorIx> colPtr, Ref<VectorIx> rowIdx, Ref<VectorSx> vals, const Index& col, const Index& jk, VectorIx& firstElt, VectorList& listCol)\n{\n  if (jk < colPtr(col+1) )\n  {\n    Index p = colPtr(col+1) - jk;\n    Index minpos; \n    rowIdx.segment(jk,p).minCoeff(&minpos);\n    minpos += jk;\n    if (rowIdx(minpos) != rowIdx(jk))\n    {\n      //Swap\n      std::swap(rowIdx(jk),rowIdx(minpos));\n      std::swap(vals(jk),vals(minpos));\n    }\n    firstElt(col) = internal::convert_index<StorageIndex,Index>(jk);\n    listCol[rowIdx(jk)].push_back(internal::convert_index<StorageIndex,Index>(col));\n  }\n}\n\n} // end namespace Eigen \n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/IterativeLinearSolvers/IncompleteLUT.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2012 Désiré Nuentsa-Wakam <desire.nuentsa_wakam@inria.fr>\n// Copyright (C) 2014 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_INCOMPLETE_LUT_H\n#define EIGEN_INCOMPLETE_LUT_H\n\n\nnamespace Eigen { \n\nnamespace internal {\n    \n/** \\internal\n  * Compute a quick-sort split of a vector \n  * On output, the vector row is permuted such that its elements satisfy\n  * abs(row(i)) >= abs(row(ncut)) if i<ncut\n  * abs(row(i)) <= abs(row(ncut)) if i>ncut \n  * \\param row The vector of values\n  * \\param ind The array of index for the elements in @p row\n  * \\param ncut  The number of largest elements to keep\n  **/ \ntemplate <typename VectorV, typename VectorI>\nIndex QuickSplit(VectorV &row, VectorI &ind, Index ncut)\n{\n  typedef typename VectorV::RealScalar RealScalar;\n  using std::swap;\n  using std::abs;\n  Index mid;\n  Index n = row.size(); /* length of the vector */\n  Index first, last ;\n  \n  ncut--; /* to fit the zero-based indices */\n  first = 0; \n  last = n-1; \n  if (ncut < first || ncut > last ) return 0;\n  \n  do {\n    mid = first; \n    RealScalar abskey = abs(row(mid)); \n    for (Index j = first + 1; j <= last; j++) {\n      if ( abs(row(j)) > abskey) {\n        ++mid;\n        swap(row(mid), row(j));\n        swap(ind(mid), ind(j));\n      }\n    }\n    /* Interchange for the pivot element */\n    swap(row(mid), row(first));\n    swap(ind(mid), ind(first));\n    \n    if (mid > ncut) last = mid - 1;\n    else if (mid < ncut ) first = mid + 1; \n  } while (mid != ncut );\n  \n  return 0; /* mid is equal to ncut */ \n}\n\n}// end namespace internal\n\n/** \\ingroup IterativeLinearSolvers_Module\n  * \\class IncompleteLUT\n  * \\brief Incomplete LU factorization with dual-threshold strategy\n  *\n  * \\implsparsesolverconcept\n  *\n  * During the numerical factorization, two dropping rules are used :\n  *  1) any element whose magnitude is less than some tolerance is dropped.\n  *    This tolerance is obtained by multiplying the input tolerance @p droptol \n  *    by the average magnitude of all the original elements in the current row.\n  *  2) After the elimination of the row, only the @p fill largest elements in \n  *    the L part and the @p fill largest elements in the U part are kept \n  *    (in addition to the diagonal element ). Note that @p fill is computed from \n  *    the input parameter @p fillfactor which is used the ratio to control the fill_in \n  *    relatively to the initial number of nonzero elements.\n  * \n  * The two extreme cases are when @p droptol=0 (to keep all the @p fill*2 largest elements)\n  * and when @p fill=n/2 with @p droptol being different to zero. \n  * \n  * References : Yousef Saad, ILUT: A dual threshold incomplete LU factorization, \n  *              Numerical Linear Algebra with Applications, 1(4), pp 387-402, 1994.\n  * \n  * NOTE : The following implementation is derived from the ILUT implementation\n  * in the SPARSKIT package, Copyright (C) 2005, the Regents of the University of Minnesota \n  *  released under the terms of the GNU LGPL: \n  *    http://www-users.cs.umn.edu/~saad/software/SPARSKIT/README\n  * However, Yousef Saad gave us permission to relicense his ILUT code to MPL2.\n  * See the Eigen mailing list archive, thread: ILUT, date: July 8, 2012:\n  *   http://listengine.tuxfamily.org/lists.tuxfamily.org/eigen/2012/07/msg00064.html\n  * alternatively, on GMANE:\n  *   http://comments.gmane.org/gmane.comp.lib.eigen/3302\n  */\ntemplate <typename _Scalar, typename _StorageIndex = int>\nclass IncompleteLUT : public SparseSolverBase<IncompleteLUT<_Scalar, _StorageIndex> >\n{\n  protected:\n    typedef SparseSolverBase<IncompleteLUT> Base;\n    using Base::m_isInitialized;\n  public:\n    typedef _Scalar Scalar;\n    typedef _StorageIndex StorageIndex;\n    typedef typename NumTraits<Scalar>::Real RealScalar;\n    typedef Matrix<Scalar,Dynamic,1> Vector;\n    typedef Matrix<StorageIndex,Dynamic,1> VectorI;\n    typedef SparseMatrix<Scalar,RowMajor,StorageIndex> FactorType;\n\n    enum {\n      ColsAtCompileTime = Dynamic,\n      MaxColsAtCompileTime = Dynamic\n    };\n\n  public:\n    \n    IncompleteLUT()\n      : m_droptol(NumTraits<Scalar>::dummy_precision()), m_fillfactor(10),\n        m_analysisIsOk(false), m_factorizationIsOk(false)\n    {}\n    \n    template<typename MatrixType>\n    explicit IncompleteLUT(const MatrixType& mat, const RealScalar& droptol=NumTraits<Scalar>::dummy_precision(), int fillfactor = 10)\n      : m_droptol(droptol),m_fillfactor(fillfactor),\n        m_analysisIsOk(false),m_factorizationIsOk(false)\n    {\n      eigen_assert(fillfactor != 0);\n      compute(mat); \n    }\n    \n    Index rows() const { return m_lu.rows(); }\n    \n    Index cols() const { return m_lu.cols(); }\n\n    /** \\brief Reports whether previous computation was successful.\n      *\n      * \\returns \\c Success if computation was succesful,\n      *          \\c NumericalIssue if the matrix.appears to be negative.\n      */\n    ComputationInfo info() const\n    {\n      eigen_assert(m_isInitialized && \"IncompleteLUT is not initialized.\");\n      return m_info;\n    }\n    \n    template<typename MatrixType>\n    void analyzePattern(const MatrixType& amat);\n    \n    template<typename MatrixType>\n    void factorize(const MatrixType& amat);\n    \n    /**\n      * Compute an incomplete LU factorization with dual threshold on the matrix mat\n      * No pivoting is done in this version\n      * \n      **/\n    template<typename MatrixType>\n    IncompleteLUT& compute(const MatrixType& amat)\n    {\n      analyzePattern(amat); \n      factorize(amat);\n      return *this;\n    }\n\n    void setDroptol(const RealScalar& droptol); \n    void setFillfactor(int fillfactor); \n    \n    template<typename Rhs, typename Dest>\n    void _solve_impl(const Rhs& b, Dest& x) const\n    {\n      x = m_Pinv * b;\n      x = m_lu.template triangularView<UnitLower>().solve(x);\n      x = m_lu.template triangularView<Upper>().solve(x);\n      x = m_P * x; \n    }\n\nprotected:\n\n    /** keeps off-diagonal entries; drops diagonal entries */\n    struct keep_diag {\n      inline bool operator() (const Index& row, const Index& col, const Scalar&) const\n      {\n        return row!=col;\n      }\n    };\n\nprotected:\n\n    FactorType m_lu;\n    RealScalar m_droptol;\n    int m_fillfactor;\n    bool m_analysisIsOk;\n    bool m_factorizationIsOk;\n    ComputationInfo m_info;\n    PermutationMatrix<Dynamic,Dynamic,StorageIndex> m_P;     // Fill-reducing permutation\n    PermutationMatrix<Dynamic,Dynamic,StorageIndex> m_Pinv;  // Inverse permutation\n};\n\n/**\n * Set control parameter droptol\n *  \\param droptol   Drop any element whose magnitude is less than this tolerance \n **/ \ntemplate<typename Scalar, typename StorageIndex>\nvoid IncompleteLUT<Scalar,StorageIndex>::setDroptol(const RealScalar& droptol)\n{\n  this->m_droptol = droptol;   \n}\n\n/**\n * Set control parameter fillfactor\n * \\param fillfactor  This is used to compute the  number @p fill_in of largest elements to keep on each row. \n **/ \ntemplate<typename Scalar, typename StorageIndex>\nvoid IncompleteLUT<Scalar,StorageIndex>::setFillfactor(int fillfactor)\n{\n  this->m_fillfactor = fillfactor;   \n}\n\ntemplate <typename Scalar, typename StorageIndex>\ntemplate<typename _MatrixType>\nvoid IncompleteLUT<Scalar,StorageIndex>::analyzePattern(const _MatrixType& amat)\n{\n  // Compute the Fill-reducing permutation\n  // Since ILUT does not perform any numerical pivoting,\n  // it is highly preferable to keep the diagonal through symmetric permutations.\n#ifndef EIGEN_MPL2_ONLY\n  // To this end, let's symmetrize the pattern and perform AMD on it.\n  SparseMatrix<Scalar,ColMajor, StorageIndex> mat1 = amat;\n  SparseMatrix<Scalar,ColMajor, StorageIndex> mat2 = amat.transpose();\n  // FIXME for a matrix with nearly symmetric pattern, mat2+mat1 is the appropriate choice.\n  //       on the other hand for a really non-symmetric pattern, mat2*mat1 should be prefered...\n  SparseMatrix<Scalar,ColMajor, StorageIndex> AtA = mat2 + mat1;\n  AMDOrdering<StorageIndex> ordering;\n  ordering(AtA,m_P);\n  m_Pinv  = m_P.inverse(); // cache the inverse permutation\n#else\n  // If AMD is not available, (MPL2-only), then let's use the slower COLAMD routine.\n  SparseMatrix<Scalar,ColMajor, StorageIndex> mat1 = amat;\n  COLAMDOrdering<StorageIndex> ordering;\n  ordering(mat1,m_Pinv);\n  m_P = m_Pinv.inverse();\n#endif\n\n  m_analysisIsOk = true;\n  m_factorizationIsOk = false;\n  m_isInitialized = true;\n}\n\ntemplate <typename Scalar, typename StorageIndex>\ntemplate<typename _MatrixType>\nvoid IncompleteLUT<Scalar,StorageIndex>::factorize(const _MatrixType& amat)\n{\n  using std::sqrt;\n  using std::swap;\n  using std::abs;\n  using internal::convert_index;\n\n  eigen_assert((amat.rows() == amat.cols()) && \"The factorization should be done on a square matrix\");\n  Index n = amat.cols();  // Size of the matrix\n  m_lu.resize(n,n);\n  // Declare Working vectors and variables\n  Vector u(n) ;     // real values of the row -- maximum size is n --\n  VectorI ju(n);   // column position of the values in u -- maximum size  is n\n  VectorI jr(n);   // Indicate the position of the nonzero elements in the vector u -- A zero location is indicated by -1\n\n  // Apply the fill-reducing permutation\n  eigen_assert(m_analysisIsOk && \"You must first call analyzePattern()\");\n  SparseMatrix<Scalar,RowMajor, StorageIndex> mat;\n  mat = amat.twistedBy(m_Pinv);\n\n  // Initialization\n  jr.fill(-1);\n  ju.fill(0);\n  u.fill(0);\n\n  // number of largest elements to keep in each row:\n  Index fill_in = (amat.nonZeros()*m_fillfactor)/n + 1;\n  if (fill_in > n) fill_in = n;\n\n  // number of largest nonzero elements to keep in the L and the U part of the current row:\n  Index nnzL = fill_in/2;\n  Index nnzU = nnzL;\n  m_lu.reserve(n * (nnzL + nnzU + 1));\n\n  // global loop over the rows of the sparse matrix\n  for (Index ii = 0; ii < n; ii++)\n  {\n    // 1 - copy the lower and the upper part of the row i of mat in the working vector u\n\n    Index sizeu = 1; // number of nonzero elements in the upper part of the current row\n    Index sizel = 0; // number of nonzero elements in the lower part of the current row\n    ju(ii)    = convert_index<StorageIndex>(ii);\n    u(ii)     = 0;\n    jr(ii)    = convert_index<StorageIndex>(ii);\n    RealScalar rownorm = 0;\n\n    typename FactorType::InnerIterator j_it(mat, ii); // Iterate through the current row ii\n    for (; j_it; ++j_it)\n    {\n      Index k = j_it.index();\n      if (k < ii)\n      {\n        // copy the lower part\n        ju(sizel) = convert_index<StorageIndex>(k);\n        u(sizel) = j_it.value();\n        jr(k) = convert_index<StorageIndex>(sizel);\n        ++sizel;\n      }\n      else if (k == ii)\n      {\n        u(ii) = j_it.value();\n      }\n      else\n      {\n        // copy the upper part\n        Index jpos = ii + sizeu;\n        ju(jpos) = convert_index<StorageIndex>(k);\n        u(jpos) = j_it.value();\n        jr(k) = convert_index<StorageIndex>(jpos);\n        ++sizeu;\n      }\n      rownorm += numext::abs2(j_it.value());\n    }\n\n    // 2 - detect possible zero row\n    if(rownorm==0)\n    {\n      m_info = NumericalIssue;\n      return;\n    }\n    // Take the 2-norm of the current row as a relative tolerance\n    rownorm = sqrt(rownorm);\n\n    // 3 - eliminate the previous nonzero rows\n    Index jj = 0;\n    Index len = 0;\n    while (jj < sizel)\n    {\n      // In order to eliminate in the correct order,\n      // we must select first the smallest column index among  ju(jj:sizel)\n      Index k;\n      Index minrow = ju.segment(jj,sizel-jj).minCoeff(&k); // k is relative to the segment\n      k += jj;\n      if (minrow != ju(jj))\n      {\n        // swap the two locations\n        Index j = ju(jj);\n        swap(ju(jj), ju(k));\n        jr(minrow) = convert_index<StorageIndex>(jj);\n        jr(j) = convert_index<StorageIndex>(k);\n        swap(u(jj), u(k));\n      }\n      // Reset this location\n      jr(minrow) = -1;\n\n      // Start elimination\n      typename FactorType::InnerIterator ki_it(m_lu, minrow);\n      while (ki_it && ki_it.index() < minrow) ++ki_it;\n      eigen_internal_assert(ki_it && ki_it.col()==minrow);\n      Scalar fact = u(jj) / ki_it.value();\n\n      // drop too small elements\n      if(abs(fact) <= m_droptol)\n      {\n        jj++;\n        continue;\n      }\n\n      // linear combination of the current row ii and the row minrow\n      ++ki_it;\n      for (; ki_it; ++ki_it)\n      {\n        Scalar prod = fact * ki_it.value();\n        Index j     = ki_it.index();\n        Index jpos  = jr(j);\n        if (jpos == -1) // fill-in element\n        {\n          Index newpos;\n          if (j >= ii) // dealing with the upper part\n          {\n            newpos = ii + sizeu;\n            sizeu++;\n            eigen_internal_assert(sizeu<=n);\n          }\n          else // dealing with the lower part\n          {\n            newpos = sizel;\n            sizel++;\n            eigen_internal_assert(sizel<=ii);\n          }\n          ju(newpos) = convert_index<StorageIndex>(j);\n          u(newpos) = -prod;\n          jr(j) = convert_index<StorageIndex>(newpos);\n        }\n        else\n          u(jpos) -= prod;\n      }\n      // store the pivot element\n      u(len)  = fact;\n      ju(len) = convert_index<StorageIndex>(minrow);\n      ++len;\n\n      jj++;\n    } // end of the elimination on the row ii\n\n    // reset the upper part of the pointer jr to zero\n    for(Index k = 0; k <sizeu; k++) jr(ju(ii+k)) = -1;\n\n    // 4 - partially sort and insert the elements in the m_lu matrix\n\n    // sort the L-part of the row\n    sizel = len;\n    len = (std::min)(sizel, nnzL);\n    typename Vector::SegmentReturnType ul(u.segment(0, sizel));\n    typename VectorI::SegmentReturnType jul(ju.segment(0, sizel));\n    internal::QuickSplit(ul, jul, len);\n\n    // store the largest m_fill elements of the L part\n    m_lu.startVec(ii);\n    for(Index k = 0; k < len; k++)\n      m_lu.insertBackByOuterInnerUnordered(ii,ju(k)) = u(k);\n\n    // store the diagonal element\n    // apply a shifting rule to avoid zero pivots (we are doing an incomplete factorization)\n    if (u(ii) == Scalar(0))\n      u(ii) = sqrt(m_droptol) * rownorm;\n    m_lu.insertBackByOuterInnerUnordered(ii, ii) = u(ii);\n\n    // sort the U-part of the row\n    // apply the dropping rule first\n    len = 0;\n    for(Index k = 1; k < sizeu; k++)\n    {\n      if(abs(u(ii+k)) > m_droptol * rownorm )\n      {\n        ++len;\n        u(ii + len)  = u(ii + k);\n        ju(ii + len) = ju(ii + k);\n      }\n    }\n    sizeu = len + 1; // +1 to take into account the diagonal element\n    len = (std::min)(sizeu, nnzU);\n    typename Vector::SegmentReturnType uu(u.segment(ii+1, sizeu-1));\n    typename VectorI::SegmentReturnType juu(ju.segment(ii+1, sizeu-1));\n    internal::QuickSplit(uu, juu, len);\n\n    // store the largest elements of the U part\n    for(Index k = ii + 1; k < ii + len; k++)\n      m_lu.insertBackByOuterInnerUnordered(ii,ju(k)) = u(k);\n  }\n  m_lu.finalize();\n  m_lu.makeCompressed();\n\n  m_factorizationIsOk = true;\n  m_info = Success;\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_INCOMPLETE_LUT_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/IterativeLinearSolvers/IterativeSolverBase.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2011-2014 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_ITERATIVE_SOLVER_BASE_H\n#define EIGEN_ITERATIVE_SOLVER_BASE_H\n\nnamespace Eigen { \n\nnamespace internal {\n\ntemplate<typename MatrixType>\nstruct is_ref_compatible_impl\n{\nprivate:\n  template <typename T0>\n  struct any_conversion\n  {\n    template <typename T> any_conversion(const volatile T&);\n    template <typename T> any_conversion(T&);\n  };\n  struct yes {int a[1];};\n  struct no  {int a[2];};\n\n  template<typename T>\n  static yes test(const Ref<const T>&, int);\n  template<typename T>\n  static no  test(any_conversion<T>, ...);\n\npublic:\n  static MatrixType ms_from;\n  enum { value = sizeof(test<MatrixType>(ms_from, 0))==sizeof(yes) };\n};\n\ntemplate<typename MatrixType>\nstruct is_ref_compatible\n{\n  enum { value = is_ref_compatible_impl<typename remove_all<MatrixType>::type>::value };\n};\n\ntemplate<typename MatrixType, bool MatrixFree = !internal::is_ref_compatible<MatrixType>::value>\nclass generic_matrix_wrapper;\n\n// We have an explicit matrix at hand, compatible with Ref<>\ntemplate<typename MatrixType>\nclass generic_matrix_wrapper<MatrixType,false>\n{\npublic:\n  typedef Ref<const MatrixType> ActualMatrixType;\n  template<int UpLo> struct ConstSelfAdjointViewReturnType {\n    typedef typename ActualMatrixType::template ConstSelfAdjointViewReturnType<UpLo>::Type Type;\n  };\n\n  enum {\n    MatrixFree = false\n  };\n\n  generic_matrix_wrapper()\n    : m_dummy(0,0), m_matrix(m_dummy)\n  {}\n\n  template<typename InputType>\n  generic_matrix_wrapper(const InputType &mat)\n    : m_matrix(mat)\n  {}\n\n  const ActualMatrixType& matrix() const\n  {\n    return m_matrix;\n  }\n\n  template<typename MatrixDerived>\n  void grab(const EigenBase<MatrixDerived> &mat)\n  {\n    m_matrix.~Ref<const MatrixType>();\n    ::new (&m_matrix) Ref<const MatrixType>(mat.derived());\n  }\n\n  void grab(const Ref<const MatrixType> &mat)\n  {\n    if(&(mat.derived()) != &m_matrix)\n    {\n      m_matrix.~Ref<const MatrixType>();\n      ::new (&m_matrix) Ref<const MatrixType>(mat);\n    }\n  }\n\nprotected:\n  MatrixType m_dummy; // used to default initialize the Ref<> object\n  ActualMatrixType m_matrix;\n};\n\n// MatrixType is not compatible with Ref<> -> matrix-free wrapper\ntemplate<typename MatrixType>\nclass generic_matrix_wrapper<MatrixType,true>\n{\npublic:\n  typedef MatrixType ActualMatrixType;\n  template<int UpLo> struct ConstSelfAdjointViewReturnType\n  {\n    typedef ActualMatrixType Type;\n  };\n\n  enum {\n    MatrixFree = true\n  };\n\n  generic_matrix_wrapper()\n    : mp_matrix(0)\n  {}\n\n  generic_matrix_wrapper(const MatrixType &mat)\n    : mp_matrix(&mat)\n  {}\n\n  const ActualMatrixType& matrix() const\n  {\n    return *mp_matrix;\n  }\n\n  void grab(const MatrixType &mat)\n  {\n    mp_matrix = &mat;\n  }\n\nprotected:\n  const ActualMatrixType *mp_matrix;\n};\n\n}\n\n/** \\ingroup IterativeLinearSolvers_Module\n  * \\brief Base class for linear iterative solvers\n  *\n  * \\sa class SimplicialCholesky, DiagonalPreconditioner, IdentityPreconditioner\n  */\ntemplate< typename Derived>\nclass IterativeSolverBase : public SparseSolverBase<Derived>\n{\nprotected:\n  typedef SparseSolverBase<Derived> Base;\n  using Base::m_isInitialized;\n  \npublic:\n  typedef typename internal::traits<Derived>::MatrixType MatrixType;\n  typedef typename internal::traits<Derived>::Preconditioner Preconditioner;\n  typedef typename MatrixType::Scalar Scalar;\n  typedef typename MatrixType::StorageIndex StorageIndex;\n  typedef typename MatrixType::RealScalar RealScalar;\n\n  enum {\n    ColsAtCompileTime = MatrixType::ColsAtCompileTime,\n    MaxColsAtCompileTime = MatrixType::MaxColsAtCompileTime\n  };\n\npublic:\n\n  using Base::derived;\n\n  /** Default constructor. */\n  IterativeSolverBase()\n  {\n    init();\n  }\n\n  /** Initialize the solver with matrix \\a A for further \\c Ax=b solving.\n    * \n    * This constructor is a shortcut for the default constructor followed\n    * by a call to compute().\n    * \n    * \\warning this class stores a reference to the matrix A as well as some\n    * precomputed values that depend on it. Therefore, if \\a A is changed\n    * this class becomes invalid. Call compute() to update it with the new\n    * matrix A, or modify a copy of A.\n    */\n  template<typename MatrixDerived>\n  explicit IterativeSolverBase(const EigenBase<MatrixDerived>& A)\n    : m_matrixWrapper(A.derived())\n  {\n    init();\n    compute(matrix());\n  }\n\n  ~IterativeSolverBase() {}\n  \n  /** Initializes the iterative solver for the sparsity pattern of the matrix \\a A for further solving \\c Ax=b problems.\n    *\n    * Currently, this function mostly calls analyzePattern on the preconditioner. In the future\n    * we might, for instance, implement column reordering for faster matrix vector products.\n    */\n  template<typename MatrixDerived>\n  Derived& analyzePattern(const EigenBase<MatrixDerived>& A)\n  {\n    grab(A.derived());\n    m_preconditioner.analyzePattern(matrix());\n    m_isInitialized = true;\n    m_analysisIsOk = true;\n    m_info = m_preconditioner.info();\n    return derived();\n  }\n  \n  /** Initializes the iterative solver with the numerical values of the matrix \\a A for further solving \\c Ax=b problems.\n    *\n    * Currently, this function mostly calls factorize on the preconditioner.\n    *\n    * \\warning this class stores a reference to the matrix A as well as some\n    * precomputed values that depend on it. Therefore, if \\a A is changed\n    * this class becomes invalid. Call compute() to update it with the new\n    * matrix A, or modify a copy of A.\n    */\n  template<typename MatrixDerived>\n  Derived& factorize(const EigenBase<MatrixDerived>& A)\n  {\n    eigen_assert(m_analysisIsOk && \"You must first call analyzePattern()\"); \n    grab(A.derived());\n    m_preconditioner.factorize(matrix());\n    m_factorizationIsOk = true;\n    m_info = m_preconditioner.info();\n    return derived();\n  }\n\n  /** Initializes the iterative solver with the matrix \\a A for further solving \\c Ax=b problems.\n    *\n    * Currently, this function mostly initializes/computes the preconditioner. In the future\n    * we might, for instance, implement column reordering for faster matrix vector products.\n    *\n    * \\warning this class stores a reference to the matrix A as well as some\n    * precomputed values that depend on it. Therefore, if \\a A is changed\n    * this class becomes invalid. Call compute() to update it with the new\n    * matrix A, or modify a copy of A.\n    */\n  template<typename MatrixDerived>\n  Derived& compute(const EigenBase<MatrixDerived>& A)\n  {\n    grab(A.derived());\n    m_preconditioner.compute(matrix());\n    m_isInitialized = true;\n    m_analysisIsOk = true;\n    m_factorizationIsOk = true;\n    m_info = m_preconditioner.info();\n    return derived();\n  }\n\n  /** \\internal */\n  Index rows() const { return matrix().rows(); }\n\n  /** \\internal */\n  Index cols() const { return matrix().cols(); }\n\n  /** \\returns the tolerance threshold used by the stopping criteria.\n    * \\sa setTolerance()\n    */\n  RealScalar tolerance() const { return m_tolerance; }\n  \n  /** Sets the tolerance threshold used by the stopping criteria.\n    *\n    * This value is used as an upper bound to the relative residual error: |Ax-b|/|b|.\n    * The default value is the machine precision given by NumTraits<Scalar>::epsilon()\n    */\n  Derived& setTolerance(const RealScalar& tolerance)\n  {\n    m_tolerance = tolerance;\n    return derived();\n  }\n\n  /** \\returns a read-write reference to the preconditioner for custom configuration. */\n  Preconditioner& preconditioner() { return m_preconditioner; }\n  \n  /** \\returns a read-only reference to the preconditioner. */\n  const Preconditioner& preconditioner() const { return m_preconditioner; }\n\n  /** \\returns the max number of iterations.\n    * It is either the value setted by setMaxIterations or, by default,\n    * twice the number of columns of the matrix.\n    */\n  Index maxIterations() const\n  {\n    return (m_maxIterations<0) ? 2*matrix().cols() : m_maxIterations;\n  }\n  \n  /** Sets the max number of iterations.\n    * Default is twice the number of columns of the matrix.\n    */\n  Derived& setMaxIterations(Index maxIters)\n  {\n    m_maxIterations = maxIters;\n    return derived();\n  }\n\n  /** \\returns the number of iterations performed during the last solve */\n  Index iterations() const\n  {\n    eigen_assert(m_isInitialized && \"ConjugateGradient is not initialized.\");\n    return m_iterations;\n  }\n\n  /** \\returns the tolerance error reached during the last solve.\n    * It is a close approximation of the true relative residual error |Ax-b|/|b|.\n    */\n  RealScalar error() const\n  {\n    eigen_assert(m_isInitialized && \"ConjugateGradient is not initialized.\");\n    return m_error;\n  }\n\n  /** \\returns the solution x of \\f$ A x = b \\f$ using the current decomposition of A\n    * and \\a x0 as an initial solution.\n    *\n    * \\sa solve(), compute()\n    */\n  template<typename Rhs,typename Guess>\n  inline const SolveWithGuess<Derived, Rhs, Guess>\n  solveWithGuess(const MatrixBase<Rhs>& b, const Guess& x0) const\n  {\n    eigen_assert(m_isInitialized && \"Solver is not initialized.\");\n    eigen_assert(derived().rows()==b.rows() && \"solve(): invalid number of rows of the right hand side matrix b\");\n    return SolveWithGuess<Derived, Rhs, Guess>(derived(), b.derived(), x0);\n  }\n\n  /** \\returns Success if the iterations converged, and NoConvergence otherwise. */\n  ComputationInfo info() const\n  {\n    eigen_assert(m_isInitialized && \"IterativeSolverBase is not initialized.\");\n    return m_info;\n  }\n  \n  /** \\internal */\n  template<typename Rhs, typename DestDerived>\n  void _solve_impl(const Rhs& b, SparseMatrixBase<DestDerived> &aDest) const\n  {\n    eigen_assert(rows()==b.rows());\n    \n    Index rhsCols = b.cols();\n    Index size = b.rows();\n    DestDerived& dest(aDest.derived());\n    typedef typename DestDerived::Scalar DestScalar;\n    Eigen::Matrix<DestScalar,Dynamic,1> tb(size);\n    Eigen::Matrix<DestScalar,Dynamic,1> tx(cols());\n    // We do not directly fill dest because sparse expressions have to be free of aliasing issue.\n    // For non square least-square problems, b and dest might not have the same size whereas they might alias each-other.\n    typename DestDerived::PlainObject tmp(cols(),rhsCols);\n    for(Index k=0; k<rhsCols; ++k)\n    {\n      tb = b.col(k);\n      tx = derived().solve(tb);\n      tmp.col(k) = tx.sparseView(0);\n    }\n    dest.swap(tmp);\n  }\n\nprotected:\n  void init()\n  {\n    m_isInitialized = false;\n    m_analysisIsOk = false;\n    m_factorizationIsOk = false;\n    m_maxIterations = -1;\n    m_tolerance = NumTraits<Scalar>::epsilon();\n  }\n\n  typedef internal::generic_matrix_wrapper<MatrixType> MatrixWrapper;\n  typedef typename MatrixWrapper::ActualMatrixType ActualMatrixType;\n\n  const ActualMatrixType& matrix() const\n  {\n    return m_matrixWrapper.matrix();\n  }\n  \n  template<typename InputType>\n  void grab(const InputType &A)\n  {\n    m_matrixWrapper.grab(A);\n  }\n  \n  MatrixWrapper m_matrixWrapper;\n  Preconditioner m_preconditioner;\n\n  Index m_maxIterations;\n  RealScalar m_tolerance;\n  \n  mutable RealScalar m_error;\n  mutable Index m_iterations;\n  mutable ComputationInfo m_info;\n  mutable bool m_analysisIsOk, m_factorizationIsOk;\n};\n\n} // end namespace Eigen\n\n#endif // EIGEN_ITERATIVE_SOLVER_BASE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/IterativeLinearSolvers/LeastSquareConjugateGradient.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2015 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_LEAST_SQUARE_CONJUGATE_GRADIENT_H\n#define EIGEN_LEAST_SQUARE_CONJUGATE_GRADIENT_H\n\nnamespace Eigen { \n\nnamespace internal {\n\n/** \\internal Low-level conjugate gradient algorithm for least-square problems\n  * \\param mat The matrix A\n  * \\param rhs The right hand side vector b\n  * \\param x On input and initial solution, on output the computed solution.\n  * \\param precond A preconditioner being able to efficiently solve for an\n  *                approximation of A'Ax=b (regardless of b)\n  * \\param iters On input the max number of iteration, on output the number of performed iterations.\n  * \\param tol_error On input the tolerance error, on output an estimation of the relative error.\n  */\ntemplate<typename MatrixType, typename Rhs, typename Dest, typename Preconditioner>\nEIGEN_DONT_INLINE\nvoid least_square_conjugate_gradient(const MatrixType& mat, const Rhs& rhs, Dest& x,\n                                     const Preconditioner& precond, Index& iters,\n                                     typename Dest::RealScalar& tol_error)\n{\n  using std::sqrt;\n  using std::abs;\n  typedef typename Dest::RealScalar RealScalar;\n  typedef typename Dest::Scalar Scalar;\n  typedef Matrix<Scalar,Dynamic,1> VectorType;\n  \n  RealScalar tol = tol_error;\n  Index maxIters = iters;\n  \n  Index m = mat.rows(), n = mat.cols();\n\n  VectorType residual        = rhs - mat * x;\n  VectorType normal_residual = mat.adjoint() * residual;\n\n  RealScalar rhsNorm2 = (mat.adjoint()*rhs).squaredNorm();\n  if(rhsNorm2 == 0) \n  {\n    x.setZero();\n    iters = 0;\n    tol_error = 0;\n    return;\n  }\n  RealScalar threshold = tol*tol*rhsNorm2;\n  RealScalar residualNorm2 = normal_residual.squaredNorm();\n  if (residualNorm2 < threshold)\n  {\n    iters = 0;\n    tol_error = sqrt(residualNorm2 / rhsNorm2);\n    return;\n  }\n  \n  VectorType p(n);\n  p = precond.solve(normal_residual);                         // initial search direction\n\n  VectorType z(n), tmp(m);\n  RealScalar absNew = numext::real(normal_residual.dot(p));  // the square of the absolute value of r scaled by invM\n  Index i = 0;\n  while(i < maxIters)\n  {\n    tmp.noalias() = mat * p;\n\n    Scalar alpha = absNew / tmp.squaredNorm();      // the amount we travel on dir\n    x += alpha * p;                                 // update solution\n    residual -= alpha * tmp;                        // update residual\n    normal_residual = mat.adjoint() * residual;     // update residual of the normal equation\n    \n    residualNorm2 = normal_residual.squaredNorm();\n    if(residualNorm2 < threshold)\n      break;\n    \n    z = precond.solve(normal_residual);             // approximately solve for \"A'A z = normal_residual\"\n\n    RealScalar absOld = absNew;\n    absNew = numext::real(normal_residual.dot(z));  // update the absolute value of r\n    RealScalar beta = absNew / absOld;              // calculate the Gram-Schmidt value used to create the new search direction\n    p = z + beta * p;                               // update search direction\n    i++;\n  }\n  tol_error = sqrt(residualNorm2 / rhsNorm2);\n  iters = i;\n}\n\n}\n\ntemplate< typename _MatrixType,\n          typename _Preconditioner = LeastSquareDiagonalPreconditioner<typename _MatrixType::Scalar> >\nclass LeastSquaresConjugateGradient;\n\nnamespace internal {\n\ntemplate< typename _MatrixType, typename _Preconditioner>\nstruct traits<LeastSquaresConjugateGradient<_MatrixType,_Preconditioner> >\n{\n  typedef _MatrixType MatrixType;\n  typedef _Preconditioner Preconditioner;\n};\n\n}\n\n/** \\ingroup IterativeLinearSolvers_Module\n  * \\brief A conjugate gradient solver for sparse (or dense) least-square problems\n  *\n  * This class allows to solve for A x = b linear problems using an iterative conjugate gradient algorithm.\n  * The matrix A can be non symmetric and rectangular, but the matrix A' A should be positive-definite to guaranty stability.\n  * Otherwise, the SparseLU or SparseQR classes might be preferable.\n  * The matrix A and the vectors x and b can be either dense or sparse.\n  *\n  * \\tparam _MatrixType the type of the matrix A, can be a dense or a sparse matrix.\n  * \\tparam _Preconditioner the type of the preconditioner. Default is LeastSquareDiagonalPreconditioner\n  *\n  * \\implsparsesolverconcept\n  * \n  * The maximal number of iterations and tolerance value can be controlled via the setMaxIterations()\n  * and setTolerance() methods. The defaults are the size of the problem for the maximal number of iterations\n  * and NumTraits<Scalar>::epsilon() for the tolerance.\n  * \n  * This class can be used as the direct solver classes. Here is a typical usage example:\n    \\code\n    int m=1000000, n = 10000;\n    VectorXd x(n), b(m);\n    SparseMatrix<double> A(m,n);\n    // fill A and b\n    LeastSquaresConjugateGradient<SparseMatrix<double> > lscg;\n    lscg.compute(A);\n    x = lscg.solve(b);\n    std::cout << \"#iterations:     \" << lscg.iterations() << std::endl;\n    std::cout << \"estimated error: \" << lscg.error()      << std::endl;\n    // update b, and solve again\n    x = lscg.solve(b);\n    \\endcode\n  * \n  * By default the iterations start with x=0 as an initial guess of the solution.\n  * One can control the start using the solveWithGuess() method.\n  * \n  * \\sa class ConjugateGradient, SparseLU, SparseQR\n  */\ntemplate< typename _MatrixType, typename _Preconditioner>\nclass LeastSquaresConjugateGradient : public IterativeSolverBase<LeastSquaresConjugateGradient<_MatrixType,_Preconditioner> >\n{\n  typedef IterativeSolverBase<LeastSquaresConjugateGradient> Base;\n  using Base::matrix;\n  using Base::m_error;\n  using Base::m_iterations;\n  using Base::m_info;\n  using Base::m_isInitialized;\npublic:\n  typedef _MatrixType MatrixType;\n  typedef typename MatrixType::Scalar Scalar;\n  typedef typename MatrixType::RealScalar RealScalar;\n  typedef _Preconditioner Preconditioner;\n\npublic:\n\n  /** Default constructor. */\n  LeastSquaresConjugateGradient() : Base() {}\n\n  /** Initialize the solver with matrix \\a A for further \\c Ax=b solving.\n    * \n    * This constructor is a shortcut for the default constructor followed\n    * by a call to compute().\n    * \n    * \\warning this class stores a reference to the matrix A as well as some\n    * precomputed values that depend on it. Therefore, if \\a A is changed\n    * this class becomes invalid. Call compute() to update it with the new\n    * matrix A, or modify a copy of A.\n    */\n  template<typename MatrixDerived>\n  explicit LeastSquaresConjugateGradient(const EigenBase<MatrixDerived>& A) : Base(A.derived()) {}\n\n  ~LeastSquaresConjugateGradient() {}\n\n  /** \\internal */\n  template<typename Rhs,typename Dest>\n  void _solve_with_guess_impl(const Rhs& b, Dest& x) const\n  {\n    m_iterations = Base::maxIterations();\n    m_error = Base::m_tolerance;\n\n    for(Index j=0; j<b.cols(); ++j)\n    {\n      m_iterations = Base::maxIterations();\n      m_error = Base::m_tolerance;\n\n      typename Dest::ColXpr xj(x,j);\n      internal::least_square_conjugate_gradient(matrix(), b.col(j), xj, Base::m_preconditioner, m_iterations, m_error);\n    }\n\n    m_isInitialized = true;\n    m_info = m_error <= Base::m_tolerance ? Success : NoConvergence;\n  }\n  \n  /** \\internal */\n  using Base::_solve_impl;\n  template<typename Rhs,typename Dest>\n  void _solve_impl(const MatrixBase<Rhs>& b, Dest& x) const\n  {\n    x.setZero();\n    _solve_with_guess_impl(b.derived(),x);\n  }\n\n};\n\n} // end namespace Eigen\n\n#endif // EIGEN_LEAST_SQUARE_CONJUGATE_GRADIENT_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/IterativeLinearSolvers/SolveWithGuess.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2014 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SOLVEWITHGUESS_H\n#define EIGEN_SOLVEWITHGUESS_H\n\nnamespace Eigen {\n\ntemplate<typename Decomposition, typename RhsType, typename GuessType> class SolveWithGuess;\n  \n/** \\class SolveWithGuess\n  * \\ingroup IterativeLinearSolvers_Module\n  *\n  * \\brief Pseudo expression representing a solving operation\n  *\n  * \\tparam Decomposition the type of the matrix or decomposion object\n  * \\tparam Rhstype the type of the right-hand side\n  *\n  * This class represents an expression of A.solve(B)\n  * and most of the time this is the only way it is used.\n  *\n  */\nnamespace internal {\n\n\ntemplate<typename Decomposition, typename RhsType, typename GuessType>\nstruct traits<SolveWithGuess<Decomposition, RhsType, GuessType> >\n  : traits<Solve<Decomposition,RhsType> >\n{};\n\n}\n\n\ntemplate<typename Decomposition, typename RhsType, typename GuessType>\nclass SolveWithGuess : public internal::generic_xpr_base<SolveWithGuess<Decomposition,RhsType,GuessType>, MatrixXpr, typename internal::traits<RhsType>::StorageKind>::type\n{\npublic:\n  typedef typename internal::traits<SolveWithGuess>::Scalar Scalar;\n  typedef typename internal::traits<SolveWithGuess>::PlainObject PlainObject;\n  typedef typename internal::generic_xpr_base<SolveWithGuess<Decomposition,RhsType,GuessType>, MatrixXpr, typename internal::traits<RhsType>::StorageKind>::type Base;\n  typedef typename internal::ref_selector<SolveWithGuess>::type Nested;\n  \n  SolveWithGuess(const Decomposition &dec, const RhsType &rhs, const GuessType &guess)\n    : m_dec(dec), m_rhs(rhs), m_guess(guess)\n  {}\n  \n  EIGEN_DEVICE_FUNC Index rows() const { return m_dec.cols(); }\n  EIGEN_DEVICE_FUNC Index cols() const { return m_rhs.cols(); }\n\n  EIGEN_DEVICE_FUNC const Decomposition& dec()   const { return m_dec; }\n  EIGEN_DEVICE_FUNC const RhsType&       rhs()   const { return m_rhs; }\n  EIGEN_DEVICE_FUNC const GuessType&     guess() const { return m_guess; }\n\nprotected:\n  const Decomposition &m_dec;\n  const RhsType       &m_rhs;\n  const GuessType     &m_guess;\n  \nprivate:\n  Scalar coeff(Index row, Index col) const;\n  Scalar coeff(Index i) const;\n};\n\nnamespace internal {\n\n// Evaluator of SolveWithGuess -> eval into a temporary\ntemplate<typename Decomposition, typename RhsType, typename GuessType>\nstruct evaluator<SolveWithGuess<Decomposition,RhsType, GuessType> >\n  : public evaluator<typename SolveWithGuess<Decomposition,RhsType,GuessType>::PlainObject>\n{\n  typedef SolveWithGuess<Decomposition,RhsType,GuessType> SolveType;\n  typedef typename SolveType::PlainObject PlainObject;\n  typedef evaluator<PlainObject> Base;\n\n  evaluator(const SolveType& solve)\n    : m_result(solve.rows(), solve.cols())\n  {\n    ::new (static_cast<Base*>(this)) Base(m_result);\n    m_result = solve.guess();\n    solve.dec()._solve_with_guess_impl(solve.rhs(), m_result);\n  }\n  \nprotected:  \n  PlainObject m_result;\n};\n\n// Specialization for \"dst = dec.solveWithGuess(rhs)\"\n// NOTE we need to specialize it for Dense2Dense to avoid ambiguous specialization error and a Sparse2Sparse specialization must exist somewhere\ntemplate<typename DstXprType, typename DecType, typename RhsType, typename GuessType, typename Scalar>\nstruct Assignment<DstXprType, SolveWithGuess<DecType,RhsType,GuessType>, internal::assign_op<Scalar,Scalar>, Dense2Dense>\n{\n  typedef SolveWithGuess<DecType,RhsType,GuessType> SrcXprType;\n  static void run(DstXprType &dst, const SrcXprType &src, const internal::assign_op<Scalar,Scalar> &)\n  {\n    Index dstRows = src.rows();\n    Index dstCols = src.cols();\n    if((dst.rows()!=dstRows) || (dst.cols()!=dstCols))\n      dst.resize(dstRows, dstCols);\n\n    dst = src.guess();\n    src.dec()._solve_with_guess_impl(src.rhs(), dst/*, src.guess()*/);\n  }\n};\n\n} // end namepsace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_SOLVEWITHGUESS_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/Jacobi/Jacobi.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009 Benoit Jacob <jacob.benoit.1@gmail.com>\n// Copyright (C) 2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_JACOBI_H\n#define EIGEN_JACOBI_H\n\nnamespace Eigen { \n\n/** \\ingroup Jacobi_Module\n  * \\jacobi_module\n  * \\class JacobiRotation\n  * \\brief Rotation given by a cosine-sine pair.\n  *\n  * This class represents a Jacobi or Givens rotation.\n  * This is a 2D rotation in the plane \\c J of angle \\f$ \\theta \\f$ defined by\n  * its cosine \\c c and sine \\c s as follow:\n  * \\f$ J = \\left ( \\begin{array}{cc} c & \\overline s \\\\ -s  & \\overline c \\end{array} \\right ) \\f$\n  *\n  * You can apply the respective counter-clockwise rotation to a column vector \\c v by\n  * applying its adjoint on the left: \\f$ v = J^* v \\f$ that translates to the following Eigen code:\n  * \\code\n  * v.applyOnTheLeft(J.adjoint());\n  * \\endcode\n  *\n  * \\sa MatrixBase::applyOnTheLeft(), MatrixBase::applyOnTheRight()\n  */\ntemplate<typename Scalar> class JacobiRotation\n{\n  public:\n    typedef typename NumTraits<Scalar>::Real RealScalar;\n\n    /** Default constructor without any initialization. */\n    JacobiRotation() {}\n\n    /** Construct a planar rotation from a cosine-sine pair (\\a c, \\c s). */\n    JacobiRotation(const Scalar& c, const Scalar& s) : m_c(c), m_s(s) {}\n\n    Scalar& c() { return m_c; }\n    Scalar c() const { return m_c; }\n    Scalar& s() { return m_s; }\n    Scalar s() const { return m_s; }\n\n    /** Concatenates two planar rotation */\n    JacobiRotation operator*(const JacobiRotation& other)\n    {\n      using numext::conj;\n      return JacobiRotation(m_c * other.m_c - conj(m_s) * other.m_s,\n                            conj(m_c * conj(other.m_s) + conj(m_s) * conj(other.m_c)));\n    }\n\n    /** Returns the transposed transformation */\n    JacobiRotation transpose() const { using numext::conj; return JacobiRotation(m_c, -conj(m_s)); }\n\n    /** Returns the adjoint transformation */\n    JacobiRotation adjoint() const { using numext::conj; return JacobiRotation(conj(m_c), -m_s); }\n\n    template<typename Derived>\n    bool makeJacobi(const MatrixBase<Derived>&, Index p, Index q);\n    bool makeJacobi(const RealScalar& x, const Scalar& y, const RealScalar& z);\n\n    void makeGivens(const Scalar& p, const Scalar& q, Scalar* z=0);\n\n  protected:\n    void makeGivens(const Scalar& p, const Scalar& q, Scalar* z, internal::true_type);\n    void makeGivens(const Scalar& p, const Scalar& q, Scalar* z, internal::false_type);\n\n    Scalar m_c, m_s;\n};\n\n/** Makes \\c *this as a Jacobi rotation \\a J such that applying \\a J on both the right and left sides of the selfadjoint 2x2 matrix\n  * \\f$ B = \\left ( \\begin{array}{cc} x & y \\\\ \\overline y & z \\end{array} \\right )\\f$ yields a diagonal matrix \\f$ A = J^* B J \\f$\n  *\n  * \\sa MatrixBase::makeJacobi(const MatrixBase<Derived>&, Index, Index), MatrixBase::applyOnTheLeft(), MatrixBase::applyOnTheRight()\n  */\ntemplate<typename Scalar>\nbool JacobiRotation<Scalar>::makeJacobi(const RealScalar& x, const Scalar& y, const RealScalar& z)\n{\n  using std::sqrt;\n  using std::abs;\n  typedef typename NumTraits<Scalar>::Real RealScalar;\n  RealScalar deno = RealScalar(2)*abs(y);\n  if(deno < (std::numeric_limits<RealScalar>::min)())\n  {\n    m_c = Scalar(1);\n    m_s = Scalar(0);\n    return false;\n  }\n  else\n  {\n    RealScalar tau = (x-z)/deno;\n    RealScalar w = sqrt(numext::abs2(tau) + RealScalar(1));\n    RealScalar t;\n    if(tau>RealScalar(0))\n    {\n      t = RealScalar(1) / (tau + w);\n    }\n    else\n    {\n      t = RealScalar(1) / (tau - w);\n    }\n    RealScalar sign_t = t > RealScalar(0) ? RealScalar(1) : RealScalar(-1);\n    RealScalar n = RealScalar(1) / sqrt(numext::abs2(t)+RealScalar(1));\n    m_s = - sign_t * (numext::conj(y) / abs(y)) * abs(t) * n;\n    m_c = n;\n    return true;\n  }\n}\n\n/** Makes \\c *this as a Jacobi rotation \\c J such that applying \\a J on both the right and left sides of the 2x2 selfadjoint matrix\n  * \\f$ B = \\left ( \\begin{array}{cc} \\text{this}_{pp} & \\text{this}_{pq} \\\\ (\\text{this}_{pq})^* & \\text{this}_{qq} \\end{array} \\right )\\f$ yields\n  * a diagonal matrix \\f$ A = J^* B J \\f$\n  *\n  * Example: \\include Jacobi_makeJacobi.cpp\n  * Output: \\verbinclude Jacobi_makeJacobi.out\n  *\n  * \\sa JacobiRotation::makeJacobi(RealScalar, Scalar, RealScalar), MatrixBase::applyOnTheLeft(), MatrixBase::applyOnTheRight()\n  */\ntemplate<typename Scalar>\ntemplate<typename Derived>\ninline bool JacobiRotation<Scalar>::makeJacobi(const MatrixBase<Derived>& m, Index p, Index q)\n{\n  return makeJacobi(numext::real(m.coeff(p,p)), m.coeff(p,q), numext::real(m.coeff(q,q)));\n}\n\n/** Makes \\c *this as a Givens rotation \\c G such that applying \\f$ G^* \\f$ to the left of the vector\n  * \\f$ V = \\left ( \\begin{array}{c} p \\\\ q \\end{array} \\right )\\f$ yields:\n  * \\f$ G^* V = \\left ( \\begin{array}{c} r \\\\ 0 \\end{array} \\right )\\f$.\n  *\n  * The value of \\a z is returned if \\a z is not null (the default is null).\n  * Also note that G is built such that the cosine is always real.\n  *\n  * Example: \\include Jacobi_makeGivens.cpp\n  * Output: \\verbinclude Jacobi_makeGivens.out\n  *\n  * This function implements the continuous Givens rotation generation algorithm\n  * found in Anderson (2000), Discontinuous Plane Rotations and the Symmetric Eigenvalue Problem.\n  * LAPACK Working Note 150, University of Tennessee, UT-CS-00-454, December 4, 2000.\n  *\n  * \\sa MatrixBase::applyOnTheLeft(), MatrixBase::applyOnTheRight()\n  */\ntemplate<typename Scalar>\nvoid JacobiRotation<Scalar>::makeGivens(const Scalar& p, const Scalar& q, Scalar* z)\n{\n  makeGivens(p, q, z, typename internal::conditional<NumTraits<Scalar>::IsComplex, internal::true_type, internal::false_type>::type());\n}\n\n\n// specialization for complexes\ntemplate<typename Scalar>\nvoid JacobiRotation<Scalar>::makeGivens(const Scalar& p, const Scalar& q, Scalar* r, internal::true_type)\n{\n  using std::sqrt;\n  using std::abs;\n  using numext::conj;\n  \n  if(q==Scalar(0))\n  {\n    m_c = numext::real(p)<0 ? Scalar(-1) : Scalar(1);\n    m_s = 0;\n    if(r) *r = m_c * p;\n  }\n  else if(p==Scalar(0))\n  {\n    m_c = 0;\n    m_s = -q/abs(q);\n    if(r) *r = abs(q);\n  }\n  else\n  {\n    RealScalar p1 = numext::norm1(p);\n    RealScalar q1 = numext::norm1(q);\n    if(p1>=q1)\n    {\n      Scalar ps = p / p1;\n      RealScalar p2 = numext::abs2(ps);\n      Scalar qs = q / p1;\n      RealScalar q2 = numext::abs2(qs);\n\n      RealScalar u = sqrt(RealScalar(1) + q2/p2);\n      if(numext::real(p)<RealScalar(0))\n        u = -u;\n\n      m_c = Scalar(1)/u;\n      m_s = -qs*conj(ps)*(m_c/p2);\n      if(r) *r = p * u;\n    }\n    else\n    {\n      Scalar ps = p / q1;\n      RealScalar p2 = numext::abs2(ps);\n      Scalar qs = q / q1;\n      RealScalar q2 = numext::abs2(qs);\n\n      RealScalar u = q1 * sqrt(p2 + q2);\n      if(numext::real(p)<RealScalar(0))\n        u = -u;\n\n      p1 = abs(p);\n      ps = p/p1;\n      m_c = p1/u;\n      m_s = -conj(ps) * (q/u);\n      if(r) *r = ps * u;\n    }\n  }\n}\n\n// specialization for reals\ntemplate<typename Scalar>\nvoid JacobiRotation<Scalar>::makeGivens(const Scalar& p, const Scalar& q, Scalar* r, internal::false_type)\n{\n  using std::sqrt;\n  using std::abs;\n  if(q==Scalar(0))\n  {\n    m_c = p<Scalar(0) ? Scalar(-1) : Scalar(1);\n    m_s = Scalar(0);\n    if(r) *r = abs(p);\n  }\n  else if(p==Scalar(0))\n  {\n    m_c = Scalar(0);\n    m_s = q<Scalar(0) ? Scalar(1) : Scalar(-1);\n    if(r) *r = abs(q);\n  }\n  else if(abs(p) > abs(q))\n  {\n    Scalar t = q/p;\n    Scalar u = sqrt(Scalar(1) + numext::abs2(t));\n    if(p<Scalar(0))\n      u = -u;\n    m_c = Scalar(1)/u;\n    m_s = -t * m_c;\n    if(r) *r = p * u;\n  }\n  else\n  {\n    Scalar t = p/q;\n    Scalar u = sqrt(Scalar(1) + numext::abs2(t));\n    if(q<Scalar(0))\n      u = -u;\n    m_s = -Scalar(1)/u;\n    m_c = -t * m_s;\n    if(r) *r = q * u;\n  }\n\n}\n\n/****************************************************************************************\n*   Implementation of MatrixBase methods\n****************************************************************************************/\n\nnamespace internal {\n/** \\jacobi_module\n  * Applies the clock wise 2D rotation \\a j to the set of 2D vectors of cordinates \\a x and \\a y:\n  * \\f$ \\left ( \\begin{array}{cc} x \\\\ y \\end{array} \\right )  =  J \\left ( \\begin{array}{cc} x \\\\ y \\end{array} \\right ) \\f$\n  *\n  * \\sa MatrixBase::applyOnTheLeft(), MatrixBase::applyOnTheRight()\n  */\ntemplate<typename VectorX, typename VectorY, typename OtherScalar>\nvoid apply_rotation_in_the_plane(DenseBase<VectorX>& xpr_x, DenseBase<VectorY>& xpr_y, const JacobiRotation<OtherScalar>& j);\n}\n\n/** \\jacobi_module\n  * Applies the rotation in the plane \\a j to the rows \\a p and \\a q of \\c *this, i.e., it computes B = J * B,\n  * with \\f$ B = \\left ( \\begin{array}{cc} \\text{*this.row}(p) \\\\ \\text{*this.row}(q) \\end{array} \\right ) \\f$.\n  *\n  * \\sa class JacobiRotation, MatrixBase::applyOnTheRight(), internal::apply_rotation_in_the_plane()\n  */\ntemplate<typename Derived>\ntemplate<typename OtherScalar>\ninline void MatrixBase<Derived>::applyOnTheLeft(Index p, Index q, const JacobiRotation<OtherScalar>& j)\n{\n  RowXpr x(this->row(p));\n  RowXpr y(this->row(q));\n  internal::apply_rotation_in_the_plane(x, y, j);\n}\n\n/** \\ingroup Jacobi_Module\n  * Applies the rotation in the plane \\a j to the columns \\a p and \\a q of \\c *this, i.e., it computes B = B * J\n  * with \\f$ B = \\left ( \\begin{array}{cc} \\text{*this.col}(p) & \\text{*this.col}(q) \\end{array} \\right ) \\f$.\n  *\n  * \\sa class JacobiRotation, MatrixBase::applyOnTheLeft(), internal::apply_rotation_in_the_plane()\n  */\ntemplate<typename Derived>\ntemplate<typename OtherScalar>\ninline void MatrixBase<Derived>::applyOnTheRight(Index p, Index q, const JacobiRotation<OtherScalar>& j)\n{\n  ColXpr x(this->col(p));\n  ColXpr y(this->col(q));\n  internal::apply_rotation_in_the_plane(x, y, j.transpose());\n}\n\nnamespace internal {\ntemplate<typename VectorX, typename VectorY, typename OtherScalar>\nvoid /*EIGEN_DONT_INLINE*/ apply_rotation_in_the_plane(DenseBase<VectorX>& xpr_x, DenseBase<VectorY>& xpr_y, const JacobiRotation<OtherScalar>& j)\n{\n  typedef typename VectorX::Scalar Scalar;\n  enum { PacketSize = packet_traits<Scalar>::size };\n  typedef typename packet_traits<Scalar>::type Packet;\n  eigen_assert(xpr_x.size() == xpr_y.size());\n  Index size = xpr_x.size();\n  Index incrx = xpr_x.derived().innerStride();\n  Index incry = xpr_y.derived().innerStride();\n\n  Scalar* EIGEN_RESTRICT x = &xpr_x.derived().coeffRef(0);\n  Scalar* EIGEN_RESTRICT y = &xpr_y.derived().coeffRef(0);\n  \n  OtherScalar c = j.c();\n  OtherScalar s = j.s();\n  if (c==OtherScalar(1) && s==OtherScalar(0))\n    return;\n\n  /*** dynamic-size vectorized paths ***/\n\n  if(VectorX::SizeAtCompileTime == Dynamic &&\n    (VectorX::Flags & VectorY::Flags & PacketAccessBit) &&\n    ((incrx==1 && incry==1) || PacketSize == 1))\n  {\n    // both vectors are sequentially stored in memory => vectorization\n    enum { Peeling = 2 };\n\n    Index alignedStart = internal::first_default_aligned(y, size);\n    Index alignedEnd = alignedStart + ((size-alignedStart)/PacketSize)*PacketSize;\n\n    const Packet pc = pset1<Packet>(c);\n    const Packet ps = pset1<Packet>(s);\n    conj_helper<Packet,Packet,NumTraits<Scalar>::IsComplex,false> pcj;\n\n    for(Index i=0; i<alignedStart; ++i)\n    {\n      Scalar xi = x[i];\n      Scalar yi = y[i];\n      x[i] =  c * xi + numext::conj(s) * yi;\n      y[i] = -s * xi + numext::conj(c) * yi;\n    }\n\n    Scalar* EIGEN_RESTRICT px = x + alignedStart;\n    Scalar* EIGEN_RESTRICT py = y + alignedStart;\n\n    if(internal::first_default_aligned(x, size)==alignedStart)\n    {\n      for(Index i=alignedStart; i<alignedEnd; i+=PacketSize)\n      {\n        Packet xi = pload<Packet>(px);\n        Packet yi = pload<Packet>(py);\n        pstore(px, padd(pmul(pc,xi),pcj.pmul(ps,yi)));\n        pstore(py, psub(pcj.pmul(pc,yi),pmul(ps,xi)));\n        px += PacketSize;\n        py += PacketSize;\n      }\n    }\n    else\n    {\n      Index peelingEnd = alignedStart + ((size-alignedStart)/(Peeling*PacketSize))*(Peeling*PacketSize);\n      for(Index i=alignedStart; i<peelingEnd; i+=Peeling*PacketSize)\n      {\n        Packet xi   = ploadu<Packet>(px);\n        Packet xi1  = ploadu<Packet>(px+PacketSize);\n        Packet yi   = pload <Packet>(py);\n        Packet yi1  = pload <Packet>(py+PacketSize);\n        pstoreu(px, padd(pmul(pc,xi),pcj.pmul(ps,yi)));\n        pstoreu(px+PacketSize, padd(pmul(pc,xi1),pcj.pmul(ps,yi1)));\n        pstore (py, psub(pcj.pmul(pc,yi),pmul(ps,xi)));\n        pstore (py+PacketSize, psub(pcj.pmul(pc,yi1),pmul(ps,xi1)));\n        px += Peeling*PacketSize;\n        py += Peeling*PacketSize;\n      }\n      if(alignedEnd!=peelingEnd)\n      {\n        Packet xi = ploadu<Packet>(x+peelingEnd);\n        Packet yi = pload <Packet>(y+peelingEnd);\n        pstoreu(x+peelingEnd, padd(pmul(pc,xi),pcj.pmul(ps,yi)));\n        pstore (y+peelingEnd, psub(pcj.pmul(pc,yi),pmul(ps,xi)));\n      }\n    }\n\n    for(Index i=alignedEnd; i<size; ++i)\n    {\n      Scalar xi = x[i];\n      Scalar yi = y[i];\n      x[i] =  c * xi + numext::conj(s) * yi;\n      y[i] = -s * xi + numext::conj(c) * yi;\n    }\n  }\n\n  /*** fixed-size vectorized path ***/\n  else if(VectorX::SizeAtCompileTime != Dynamic &&\n          (VectorX::Flags & VectorY::Flags & PacketAccessBit) &&\n          (EIGEN_PLAIN_ENUM_MIN(evaluator<VectorX>::Alignment, evaluator<VectorY>::Alignment)>0)) // FIXME should be compared to the required alignment\n  {\n    const Packet pc = pset1<Packet>(c);\n    const Packet ps = pset1<Packet>(s);\n    conj_helper<Packet,Packet,NumTraits<Scalar>::IsComplex,false> pcj;\n    Scalar* EIGEN_RESTRICT px = x;\n    Scalar* EIGEN_RESTRICT py = y;\n    for(Index i=0; i<size; i+=PacketSize)\n    {\n      Packet xi = pload<Packet>(px);\n      Packet yi = pload<Packet>(py);\n      pstore(px, padd(pmul(pc,xi),pcj.pmul(ps,yi)));\n      pstore(py, psub(pcj.pmul(pc,yi),pmul(ps,xi)));\n      px += PacketSize;\n      py += PacketSize;\n    }\n  }\n\n  /*** non-vectorized path ***/\n  else\n  {\n    for(Index i=0; i<size; ++i)\n    {\n      Scalar xi = *x;\n      Scalar yi = *y;\n      *x =  c * xi + numext::conj(s) * yi;\n      *y = -s * xi + numext::conj(c) * yi;\n      x += incrx;\n      y += incry;\n    }\n  }\n}\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_JACOBI_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/LU/Determinant.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_DETERMINANT_H\n#define EIGEN_DETERMINANT_H\n\nnamespace Eigen { \n\nnamespace internal {\n\ntemplate<typename Derived>\ninline const typename Derived::Scalar bruteforce_det3_helper\n(const MatrixBase<Derived>& matrix, int a, int b, int c)\n{\n  return matrix.coeff(0,a)\n         * (matrix.coeff(1,b) * matrix.coeff(2,c) - matrix.coeff(1,c) * matrix.coeff(2,b));\n}\n\ntemplate<typename Derived>\nconst typename Derived::Scalar bruteforce_det4_helper\n(const MatrixBase<Derived>& matrix, int j, int k, int m, int n)\n{\n  return (matrix.coeff(j,0) * matrix.coeff(k,1) - matrix.coeff(k,0) * matrix.coeff(j,1))\n       * (matrix.coeff(m,2) * matrix.coeff(n,3) - matrix.coeff(n,2) * matrix.coeff(m,3));\n}\n\ntemplate<typename Derived,\n         int DeterminantType = Derived::RowsAtCompileTime\n> struct determinant_impl\n{\n  static inline typename traits<Derived>::Scalar run(const Derived& m)\n  {\n    if(Derived::ColsAtCompileTime==Dynamic && m.rows()==0)\n      return typename traits<Derived>::Scalar(1);\n    return m.partialPivLu().determinant();\n  }\n};\n\ntemplate<typename Derived> struct determinant_impl<Derived, 1>\n{\n  static inline typename traits<Derived>::Scalar run(const Derived& m)\n  {\n    return m.coeff(0,0);\n  }\n};\n\ntemplate<typename Derived> struct determinant_impl<Derived, 2>\n{\n  static inline typename traits<Derived>::Scalar run(const Derived& m)\n  {\n    return m.coeff(0,0) * m.coeff(1,1) - m.coeff(1,0) * m.coeff(0,1);\n  }\n};\n\ntemplate<typename Derived> struct determinant_impl<Derived, 3>\n{\n  static inline typename traits<Derived>::Scalar run(const Derived& m)\n  {\n    return bruteforce_det3_helper(m,0,1,2)\n          - bruteforce_det3_helper(m,1,0,2)\n          + bruteforce_det3_helper(m,2,0,1);\n  }\n};\n\ntemplate<typename Derived> struct determinant_impl<Derived, 4>\n{\n  static typename traits<Derived>::Scalar run(const Derived& m)\n  {\n    // trick by Martin Costabel to compute 4x4 det with only 30 muls\n    return bruteforce_det4_helper(m,0,1,2,3)\n          - bruteforce_det4_helper(m,0,2,1,3)\n          + bruteforce_det4_helper(m,0,3,1,2)\n          + bruteforce_det4_helper(m,1,2,0,3)\n          - bruteforce_det4_helper(m,1,3,0,2)\n          + bruteforce_det4_helper(m,2,3,0,1);\n  }\n};\n\n} // end namespace internal\n\n/** \\lu_module\n  *\n  * \\returns the determinant of this matrix\n  */\ntemplate<typename Derived>\ninline typename internal::traits<Derived>::Scalar MatrixBase<Derived>::determinant() const\n{\n  eigen_assert(rows() == cols());\n  typedef typename internal::nested_eval<Derived,Base::RowsAtCompileTime>::type Nested;\n  return internal::determinant_impl<typename internal::remove_all<Nested>::type>::run(derived());\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_DETERMINANT_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/LU/FullPivLU.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2006-2009 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_LU_H\n#define EIGEN_LU_H\n\nnamespace Eigen {\n\nnamespace internal {\ntemplate<typename _MatrixType> struct traits<FullPivLU<_MatrixType> >\n : traits<_MatrixType>\n{\n  typedef MatrixXpr XprKind;\n  typedef SolverStorage StorageKind;\n  enum { Flags = 0 };\n};\n\n} // end namespace internal\n\n/** \\ingroup LU_Module\n  *\n  * \\class FullPivLU\n  *\n  * \\brief LU decomposition of a matrix with complete pivoting, and related features\n  *\n  * \\tparam _MatrixType the type of the matrix of which we are computing the LU decomposition\n  *\n  * This class represents a LU decomposition of any matrix, with complete pivoting: the matrix A is\n  * decomposed as \\f$ A = P^{-1} L U Q^{-1} \\f$ where L is unit-lower-triangular, U is\n  * upper-triangular, and P and Q are permutation matrices. This is a rank-revealing LU\n  * decomposition. The eigenvalues (diagonal coefficients) of U are sorted in such a way that any\n  * zeros are at the end.\n  *\n  * This decomposition provides the generic approach to solving systems of linear equations, computing\n  * the rank, invertibility, inverse, kernel, and determinant.\n  *\n  * This LU decomposition is very stable and well tested with large matrices. However there are use cases where the SVD\n  * decomposition is inherently more stable and/or flexible. For example, when computing the kernel of a matrix,\n  * working with the SVD allows to select the smallest singular values of the matrix, something that\n  * the LU decomposition doesn't see.\n  *\n  * The data of the LU decomposition can be directly accessed through the methods matrixLU(),\n  * permutationP(), permutationQ().\n  *\n  * As an exemple, here is how the original matrix can be retrieved:\n  * \\include class_FullPivLU.cpp\n  * Output: \\verbinclude class_FullPivLU.out\n  *\n  * This class supports the \\link InplaceDecomposition inplace decomposition \\endlink mechanism.\n  * \n  * \\sa MatrixBase::fullPivLu(), MatrixBase::determinant(), MatrixBase::inverse()\n  */\ntemplate<typename _MatrixType> class FullPivLU\n  : public SolverBase<FullPivLU<_MatrixType> >\n{\n  public:\n    typedef _MatrixType MatrixType;\n    typedef SolverBase<FullPivLU> Base;\n\n    EIGEN_GENERIC_PUBLIC_INTERFACE(FullPivLU)\n    // FIXME StorageIndex defined in EIGEN_GENERIC_PUBLIC_INTERFACE should be int\n    enum {\n      MaxRowsAtCompileTime = MatrixType::MaxRowsAtCompileTime,\n      MaxColsAtCompileTime = MatrixType::MaxColsAtCompileTime\n    };\n    typedef typename internal::plain_row_type<MatrixType, StorageIndex>::type IntRowVectorType;\n    typedef typename internal::plain_col_type<MatrixType, StorageIndex>::type IntColVectorType;\n    typedef PermutationMatrix<ColsAtCompileTime, MaxColsAtCompileTime> PermutationQType;\n    typedef PermutationMatrix<RowsAtCompileTime, MaxRowsAtCompileTime> PermutationPType;\n    typedef typename MatrixType::PlainObject PlainObject;\n\n    /**\n      * \\brief Default Constructor.\n      *\n      * The default constructor is useful in cases in which the user intends to\n      * perform decompositions via LU::compute(const MatrixType&).\n      */\n    FullPivLU();\n\n    /** \\brief Default Constructor with memory preallocation\n      *\n      * Like the default constructor but with preallocation of the internal data\n      * according to the specified problem \\a size.\n      * \\sa FullPivLU()\n      */\n    FullPivLU(Index rows, Index cols);\n\n    /** Constructor.\n      *\n      * \\param matrix the matrix of which to compute the LU decomposition.\n      *               It is required to be nonzero.\n      */\n    template<typename InputType>\n    explicit FullPivLU(const EigenBase<InputType>& matrix);\n\n    /** \\brief Constructs a LU factorization from a given matrix\n      *\n      * This overloaded constructor is provided for \\link InplaceDecomposition inplace decomposition \\endlink when \\c MatrixType is a Eigen::Ref.\n      *\n      * \\sa FullPivLU(const EigenBase&)\n      */\n    template<typename InputType>\n    explicit FullPivLU(EigenBase<InputType>& matrix);\n\n    /** Computes the LU decomposition of the given matrix.\n      *\n      * \\param matrix the matrix of which to compute the LU decomposition.\n      *               It is required to be nonzero.\n      *\n      * \\returns a reference to *this\n      */\n    template<typename InputType>\n    FullPivLU& compute(const EigenBase<InputType>& matrix) {\n      m_lu = matrix.derived();\n      computeInPlace();\n      return *this;\n    }\n\n    /** \\returns the LU decomposition matrix: the upper-triangular part is U, the\n      * unit-lower-triangular part is L (at least for square matrices; in the non-square\n      * case, special care is needed, see the documentation of class FullPivLU).\n      *\n      * \\sa matrixL(), matrixU()\n      */\n    inline const MatrixType& matrixLU() const\n    {\n      eigen_assert(m_isInitialized && \"LU is not initialized.\");\n      return m_lu;\n    }\n\n    /** \\returns the number of nonzero pivots in the LU decomposition.\n      * Here nonzero is meant in the exact sense, not in a fuzzy sense.\n      * So that notion isn't really intrinsically interesting, but it is\n      * still useful when implementing algorithms.\n      *\n      * \\sa rank()\n      */\n    inline Index nonzeroPivots() const\n    {\n      eigen_assert(m_isInitialized && \"LU is not initialized.\");\n      return m_nonzero_pivots;\n    }\n\n    /** \\returns the absolute value of the biggest pivot, i.e. the biggest\n      *          diagonal coefficient of U.\n      */\n    RealScalar maxPivot() const { return m_maxpivot; }\n\n    /** \\returns the permutation matrix P\n      *\n      * \\sa permutationQ()\n      */\n    EIGEN_DEVICE_FUNC inline const PermutationPType& permutationP() const\n    {\n      eigen_assert(m_isInitialized && \"LU is not initialized.\");\n      return m_p;\n    }\n\n    /** \\returns the permutation matrix Q\n      *\n      * \\sa permutationP()\n      */\n    inline const PermutationQType& permutationQ() const\n    {\n      eigen_assert(m_isInitialized && \"LU is not initialized.\");\n      return m_q;\n    }\n\n    /** \\returns the kernel of the matrix, also called its null-space. The columns of the returned matrix\n      * will form a basis of the kernel.\n      *\n      * \\note If the kernel has dimension zero, then the returned matrix is a column-vector filled with zeros.\n      *\n      * \\note This method has to determine which pivots should be considered nonzero.\n      *       For that, it uses the threshold value that you can control by calling\n      *       setThreshold(const RealScalar&).\n      *\n      * Example: \\include FullPivLU_kernel.cpp\n      * Output: \\verbinclude FullPivLU_kernel.out\n      *\n      * \\sa image()\n      */\n    inline const internal::kernel_retval<FullPivLU> kernel() const\n    {\n      eigen_assert(m_isInitialized && \"LU is not initialized.\");\n      return internal::kernel_retval<FullPivLU>(*this);\n    }\n\n    /** \\returns the image of the matrix, also called its column-space. The columns of the returned matrix\n      * will form a basis of the image (column-space).\n      *\n      * \\param originalMatrix the original matrix, of which *this is the LU decomposition.\n      *                       The reason why it is needed to pass it here, is that this allows\n      *                       a large optimization, as otherwise this method would need to reconstruct it\n      *                       from the LU decomposition.\n      *\n      * \\note If the image has dimension zero, then the returned matrix is a column-vector filled with zeros.\n      *\n      * \\note This method has to determine which pivots should be considered nonzero.\n      *       For that, it uses the threshold value that you can control by calling\n      *       setThreshold(const RealScalar&).\n      *\n      * Example: \\include FullPivLU_image.cpp\n      * Output: \\verbinclude FullPivLU_image.out\n      *\n      * \\sa kernel()\n      */\n    inline const internal::image_retval<FullPivLU>\n      image(const MatrixType& originalMatrix) const\n    {\n      eigen_assert(m_isInitialized && \"LU is not initialized.\");\n      return internal::image_retval<FullPivLU>(*this, originalMatrix);\n    }\n\n    /** \\return a solution x to the equation Ax=b, where A is the matrix of which\n      * *this is the LU decomposition.\n      *\n      * \\param b the right-hand-side of the equation to solve. Can be a vector or a matrix,\n      *          the only requirement in order for the equation to make sense is that\n      *          b.rows()==A.rows(), where A is the matrix of which *this is the LU decomposition.\n      *\n      * \\returns a solution.\n      *\n      * \\note_about_checking_solutions\n      *\n      * \\note_about_arbitrary_choice_of_solution\n      * \\note_about_using_kernel_to_study_multiple_solutions\n      *\n      * Example: \\include FullPivLU_solve.cpp\n      * Output: \\verbinclude FullPivLU_solve.out\n      *\n      * \\sa TriangularView::solve(), kernel(), inverse()\n      */\n    // FIXME this is a copy-paste of the base-class member to add the isInitialized assertion.\n    template<typename Rhs>\n    inline const Solve<FullPivLU, Rhs>\n    solve(const MatrixBase<Rhs>& b) const\n    {\n      eigen_assert(m_isInitialized && \"LU is not initialized.\");\n      return Solve<FullPivLU, Rhs>(*this, b.derived());\n    }\n\n    /** \\returns an estimate of the reciprocal condition number of the matrix of which \\c *this is\n        the LU decomposition.\n      */\n    inline RealScalar rcond() const\n    {\n      eigen_assert(m_isInitialized && \"PartialPivLU is not initialized.\");\n      return internal::rcond_estimate_helper(m_l1_norm, *this);\n    }\n\n    /** \\returns the determinant of the matrix of which\n      * *this is the LU decomposition. It has only linear complexity\n      * (that is, O(n) where n is the dimension of the square matrix)\n      * as the LU decomposition has already been computed.\n      *\n      * \\note This is only for square matrices.\n      *\n      * \\note For fixed-size matrices of size up to 4, MatrixBase::determinant() offers\n      *       optimized paths.\n      *\n      * \\warning a determinant can be very big or small, so for matrices\n      * of large enough dimension, there is a risk of overflow/underflow.\n      *\n      * \\sa MatrixBase::determinant()\n      */\n    typename internal::traits<MatrixType>::Scalar determinant() const;\n\n    /** Allows to prescribe a threshold to be used by certain methods, such as rank(),\n      * who need to determine when pivots are to be considered nonzero. This is not used for the\n      * LU decomposition itself.\n      *\n      * When it needs to get the threshold value, Eigen calls threshold(). By default, this\n      * uses a formula to automatically determine a reasonable threshold.\n      * Once you have called the present method setThreshold(const RealScalar&),\n      * your value is used instead.\n      *\n      * \\param threshold The new value to use as the threshold.\n      *\n      * A pivot will be considered nonzero if its absolute value is strictly greater than\n      *  \\f$ \\vert pivot \\vert \\leqslant threshold \\times \\vert maxpivot \\vert \\f$\n      * where maxpivot is the biggest pivot.\n      *\n      * If you want to come back to the default behavior, call setThreshold(Default_t)\n      */\n    FullPivLU& setThreshold(const RealScalar& threshold)\n    {\n      m_usePrescribedThreshold = true;\n      m_prescribedThreshold = threshold;\n      return *this;\n    }\n\n    /** Allows to come back to the default behavior, letting Eigen use its default formula for\n      * determining the threshold.\n      *\n      * You should pass the special object Eigen::Default as parameter here.\n      * \\code lu.setThreshold(Eigen::Default); \\endcode\n      *\n      * See the documentation of setThreshold(const RealScalar&).\n      */\n    FullPivLU& setThreshold(Default_t)\n    {\n      m_usePrescribedThreshold = false;\n      return *this;\n    }\n\n    /** Returns the threshold that will be used by certain methods such as rank().\n      *\n      * See the documentation of setThreshold(const RealScalar&).\n      */\n    RealScalar threshold() const\n    {\n      eigen_assert(m_isInitialized || m_usePrescribedThreshold);\n      return m_usePrescribedThreshold ? m_prescribedThreshold\n      // this formula comes from experimenting (see \"LU precision tuning\" thread on the list)\n      // and turns out to be identical to Higham's formula used already in LDLt.\n                                      : NumTraits<Scalar>::epsilon() * m_lu.diagonalSize();\n    }\n\n    /** \\returns the rank of the matrix of which *this is the LU decomposition.\n      *\n      * \\note This method has to determine which pivots should be considered nonzero.\n      *       For that, it uses the threshold value that you can control by calling\n      *       setThreshold(const RealScalar&).\n      */\n    inline Index rank() const\n    {\n      using std::abs;\n      eigen_assert(m_isInitialized && \"LU is not initialized.\");\n      RealScalar premultiplied_threshold = abs(m_maxpivot) * threshold();\n      Index result = 0;\n      for(Index i = 0; i < m_nonzero_pivots; ++i)\n        result += (abs(m_lu.coeff(i,i)) > premultiplied_threshold);\n      return result;\n    }\n\n    /** \\returns the dimension of the kernel of the matrix of which *this is the LU decomposition.\n      *\n      * \\note This method has to determine which pivots should be considered nonzero.\n      *       For that, it uses the threshold value that you can control by calling\n      *       setThreshold(const RealScalar&).\n      */\n    inline Index dimensionOfKernel() const\n    {\n      eigen_assert(m_isInitialized && \"LU is not initialized.\");\n      return cols() - rank();\n    }\n\n    /** \\returns true if the matrix of which *this is the LU decomposition represents an injective\n      *          linear map, i.e. has trivial kernel; false otherwise.\n      *\n      * \\note This method has to determine which pivots should be considered nonzero.\n      *       For that, it uses the threshold value that you can control by calling\n      *       setThreshold(const RealScalar&).\n      */\n    inline bool isInjective() const\n    {\n      eigen_assert(m_isInitialized && \"LU is not initialized.\");\n      return rank() == cols();\n    }\n\n    /** \\returns true if the matrix of which *this is the LU decomposition represents a surjective\n      *          linear map; false otherwise.\n      *\n      * \\note This method has to determine which pivots should be considered nonzero.\n      *       For that, it uses the threshold value that you can control by calling\n      *       setThreshold(const RealScalar&).\n      */\n    inline bool isSurjective() const\n    {\n      eigen_assert(m_isInitialized && \"LU is not initialized.\");\n      return rank() == rows();\n    }\n\n    /** \\returns true if the matrix of which *this is the LU decomposition is invertible.\n      *\n      * \\note This method has to determine which pivots should be considered nonzero.\n      *       For that, it uses the threshold value that you can control by calling\n      *       setThreshold(const RealScalar&).\n      */\n    inline bool isInvertible() const\n    {\n      eigen_assert(m_isInitialized && \"LU is not initialized.\");\n      return isInjective() && (m_lu.rows() == m_lu.cols());\n    }\n\n    /** \\returns the inverse of the matrix of which *this is the LU decomposition.\n      *\n      * \\note If this matrix is not invertible, the returned matrix has undefined coefficients.\n      *       Use isInvertible() to first determine whether this matrix is invertible.\n      *\n      * \\sa MatrixBase::inverse()\n      */\n    inline const Inverse<FullPivLU> inverse() const\n    {\n      eigen_assert(m_isInitialized && \"LU is not initialized.\");\n      eigen_assert(m_lu.rows() == m_lu.cols() && \"You can't take the inverse of a non-square matrix!\");\n      return Inverse<FullPivLU>(*this);\n    }\n\n    MatrixType reconstructedMatrix() const;\n\n    EIGEN_DEVICE_FUNC inline Index rows() const { return m_lu.rows(); }\n    EIGEN_DEVICE_FUNC inline Index cols() const { return m_lu.cols(); }\n\n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    template<typename RhsType, typename DstType>\n    EIGEN_DEVICE_FUNC\n    void _solve_impl(const RhsType &rhs, DstType &dst) const;\n\n    template<bool Conjugate, typename RhsType, typename DstType>\n    EIGEN_DEVICE_FUNC\n    void _solve_impl_transposed(const RhsType &rhs, DstType &dst) const;\n    #endif\n\n  protected:\n\n    static void check_template_parameters()\n    {\n      EIGEN_STATIC_ASSERT_NON_INTEGER(Scalar);\n    }\n\n    void computeInPlace();\n\n    MatrixType m_lu;\n    PermutationPType m_p;\n    PermutationQType m_q;\n    IntColVectorType m_rowsTranspositions;\n    IntRowVectorType m_colsTranspositions;\n    Index m_nonzero_pivots;\n    RealScalar m_l1_norm;\n    RealScalar m_maxpivot, m_prescribedThreshold;\n    signed char m_det_pq;\n    bool m_isInitialized, m_usePrescribedThreshold;\n};\n\ntemplate<typename MatrixType>\nFullPivLU<MatrixType>::FullPivLU()\n  : m_isInitialized(false), m_usePrescribedThreshold(false)\n{\n}\n\ntemplate<typename MatrixType>\nFullPivLU<MatrixType>::FullPivLU(Index rows, Index cols)\n  : m_lu(rows, cols),\n    m_p(rows),\n    m_q(cols),\n    m_rowsTranspositions(rows),\n    m_colsTranspositions(cols),\n    m_isInitialized(false),\n    m_usePrescribedThreshold(false)\n{\n}\n\ntemplate<typename MatrixType>\ntemplate<typename InputType>\nFullPivLU<MatrixType>::FullPivLU(const EigenBase<InputType>& matrix)\n  : m_lu(matrix.rows(), matrix.cols()),\n    m_p(matrix.rows()),\n    m_q(matrix.cols()),\n    m_rowsTranspositions(matrix.rows()),\n    m_colsTranspositions(matrix.cols()),\n    m_isInitialized(false),\n    m_usePrescribedThreshold(false)\n{\n  compute(matrix.derived());\n}\n\ntemplate<typename MatrixType>\ntemplate<typename InputType>\nFullPivLU<MatrixType>::FullPivLU(EigenBase<InputType>& matrix)\n  : m_lu(matrix.derived()),\n    m_p(matrix.rows()),\n    m_q(matrix.cols()),\n    m_rowsTranspositions(matrix.rows()),\n    m_colsTranspositions(matrix.cols()),\n    m_isInitialized(false),\n    m_usePrescribedThreshold(false)\n{\n  computeInPlace();\n}\n\ntemplate<typename MatrixType>\nvoid FullPivLU<MatrixType>::computeInPlace()\n{\n  check_template_parameters();\n\n  // the permutations are stored as int indices, so just to be sure:\n  eigen_assert(m_lu.rows()<=NumTraits<int>::highest() && m_lu.cols()<=NumTraits<int>::highest());\n\n  m_l1_norm = m_lu.cwiseAbs().colwise().sum().maxCoeff();\n\n  const Index size = m_lu.diagonalSize();\n  const Index rows = m_lu.rows();\n  const Index cols = m_lu.cols();\n\n  // will store the transpositions, before we accumulate them at the end.\n  // can't accumulate on-the-fly because that will be done in reverse order for the rows.\n  m_rowsTranspositions.resize(m_lu.rows());\n  m_colsTranspositions.resize(m_lu.cols());\n  Index number_of_transpositions = 0; // number of NONTRIVIAL transpositions, i.e. m_rowsTranspositions[i]!=i\n\n  m_nonzero_pivots = size; // the generic case is that in which all pivots are nonzero (invertible case)\n  m_maxpivot = RealScalar(0);\n\n  for(Index k = 0; k < size; ++k)\n  {\n    // First, we need to find the pivot.\n\n    // biggest coefficient in the remaining bottom-right corner (starting at row k, col k)\n    Index row_of_biggest_in_corner, col_of_biggest_in_corner;\n    typedef internal::scalar_score_coeff_op<Scalar> Scoring;\n    typedef typename Scoring::result_type Score;\n    Score biggest_in_corner;\n    biggest_in_corner = m_lu.bottomRightCorner(rows-k, cols-k)\n                        .unaryExpr(Scoring())\n                        .maxCoeff(&row_of_biggest_in_corner, &col_of_biggest_in_corner);\n    row_of_biggest_in_corner += k; // correct the values! since they were computed in the corner,\n    col_of_biggest_in_corner += k; // need to add k to them.\n\n    if(biggest_in_corner==Score(0))\n    {\n      // before exiting, make sure to initialize the still uninitialized transpositions\n      // in a sane state without destroying what we already have.\n      m_nonzero_pivots = k;\n      for(Index i = k; i < size; ++i)\n      {\n        m_rowsTranspositions.coeffRef(i) = i;\n        m_colsTranspositions.coeffRef(i) = i;\n      }\n      break;\n    }\n\n    RealScalar abs_pivot = internal::abs_knowing_score<Scalar>()(m_lu(row_of_biggest_in_corner, col_of_biggest_in_corner), biggest_in_corner);\n    if(abs_pivot > m_maxpivot) m_maxpivot = abs_pivot;\n\n    // Now that we've found the pivot, we need to apply the row/col swaps to\n    // bring it to the location (k,k).\n\n    m_rowsTranspositions.coeffRef(k) = row_of_biggest_in_corner;\n    m_colsTranspositions.coeffRef(k) = col_of_biggest_in_corner;\n    if(k != row_of_biggest_in_corner) {\n      m_lu.row(k).swap(m_lu.row(row_of_biggest_in_corner));\n      ++number_of_transpositions;\n    }\n    if(k != col_of_biggest_in_corner) {\n      m_lu.col(k).swap(m_lu.col(col_of_biggest_in_corner));\n      ++number_of_transpositions;\n    }\n\n    // Now that the pivot is at the right location, we update the remaining\n    // bottom-right corner by Gaussian elimination.\n\n    if(k<rows-1)\n      m_lu.col(k).tail(rows-k-1) /= m_lu.coeff(k,k);\n    if(k<size-1)\n      m_lu.block(k+1,k+1,rows-k-1,cols-k-1).noalias() -= m_lu.col(k).tail(rows-k-1) * m_lu.row(k).tail(cols-k-1);\n  }\n\n  // the main loop is over, we still have to accumulate the transpositions to find the\n  // permutations P and Q\n\n  m_p.setIdentity(rows);\n  for(Index k = size-1; k >= 0; --k)\n    m_p.applyTranspositionOnTheRight(k, m_rowsTranspositions.coeff(k));\n\n  m_q.setIdentity(cols);\n  for(Index k = 0; k < size; ++k)\n    m_q.applyTranspositionOnTheRight(k, m_colsTranspositions.coeff(k));\n\n  m_det_pq = (number_of_transpositions%2) ? -1 : 1;\n\n  m_isInitialized = true;\n}\n\ntemplate<typename MatrixType>\ntypename internal::traits<MatrixType>::Scalar FullPivLU<MatrixType>::determinant() const\n{\n  eigen_assert(m_isInitialized && \"LU is not initialized.\");\n  eigen_assert(m_lu.rows() == m_lu.cols() && \"You can't take the determinant of a non-square matrix!\");\n  return Scalar(m_det_pq) * Scalar(m_lu.diagonal().prod());\n}\n\n/** \\returns the matrix represented by the decomposition,\n * i.e., it returns the product: \\f$ P^{-1} L U Q^{-1} \\f$.\n * This function is provided for debug purposes. */\ntemplate<typename MatrixType>\nMatrixType FullPivLU<MatrixType>::reconstructedMatrix() const\n{\n  eigen_assert(m_isInitialized && \"LU is not initialized.\");\n  const Index smalldim = (std::min)(m_lu.rows(), m_lu.cols());\n  // LU\n  MatrixType res(m_lu.rows(),m_lu.cols());\n  // FIXME the .toDenseMatrix() should not be needed...\n  res = m_lu.leftCols(smalldim)\n            .template triangularView<UnitLower>().toDenseMatrix()\n      * m_lu.topRows(smalldim)\n            .template triangularView<Upper>().toDenseMatrix();\n\n  // P^{-1}(LU)\n  res = m_p.inverse() * res;\n\n  // (P^{-1}LU)Q^{-1}\n  res = res * m_q.inverse();\n\n  return res;\n}\n\n/********* Implementation of kernel() **************************************************/\n\nnamespace internal {\ntemplate<typename _MatrixType>\nstruct kernel_retval<FullPivLU<_MatrixType> >\n  : kernel_retval_base<FullPivLU<_MatrixType> >\n{\n  EIGEN_MAKE_KERNEL_HELPERS(FullPivLU<_MatrixType>)\n\n  enum { MaxSmallDimAtCompileTime = EIGEN_SIZE_MIN_PREFER_FIXED(\n            MatrixType::MaxColsAtCompileTime,\n            MatrixType::MaxRowsAtCompileTime)\n  };\n\n  template<typename Dest> void evalTo(Dest& dst) const\n  {\n    using std::abs;\n    const Index cols = dec().matrixLU().cols(), dimker = cols - rank();\n    if(dimker == 0)\n    {\n      // The Kernel is just {0}, so it doesn't have a basis properly speaking, but let's\n      // avoid crashing/asserting as that depends on floating point calculations. Let's\n      // just return a single column vector filled with zeros.\n      dst.setZero();\n      return;\n    }\n\n    /* Let us use the following lemma:\n      *\n      * Lemma: If the matrix A has the LU decomposition PAQ = LU,\n      * then Ker A = Q(Ker U).\n      *\n      * Proof: trivial: just keep in mind that P, Q, L are invertible.\n      */\n\n    /* Thus, all we need to do is to compute Ker U, and then apply Q.\n      *\n      * U is upper triangular, with eigenvalues sorted so that any zeros appear at the end.\n      * Thus, the diagonal of U ends with exactly\n      * dimKer zero's. Let us use that to construct dimKer linearly\n      * independent vectors in Ker U.\n      */\n\n    Matrix<Index, Dynamic, 1, 0, MaxSmallDimAtCompileTime, 1> pivots(rank());\n    RealScalar premultiplied_threshold = dec().maxPivot() * dec().threshold();\n    Index p = 0;\n    for(Index i = 0; i < dec().nonzeroPivots(); ++i)\n      if(abs(dec().matrixLU().coeff(i,i)) > premultiplied_threshold)\n        pivots.coeffRef(p++) = i;\n    eigen_internal_assert(p == rank());\n\n    // we construct a temporaty trapezoid matrix m, by taking the U matrix and\n    // permuting the rows and cols to bring the nonnegligible pivots to the top of\n    // the main diagonal. We need that to be able to apply our triangular solvers.\n    // FIXME when we get triangularView-for-rectangular-matrices, this can be simplified\n    Matrix<typename MatrixType::Scalar, Dynamic, Dynamic, MatrixType::Options,\n           MaxSmallDimAtCompileTime, MatrixType::MaxColsAtCompileTime>\n      m(dec().matrixLU().block(0, 0, rank(), cols));\n    for(Index i = 0; i < rank(); ++i)\n    {\n      if(i) m.row(i).head(i).setZero();\n      m.row(i).tail(cols-i) = dec().matrixLU().row(pivots.coeff(i)).tail(cols-i);\n    }\n    m.block(0, 0, rank(), rank());\n    m.block(0, 0, rank(), rank()).template triangularView<StrictlyLower>().setZero();\n    for(Index i = 0; i < rank(); ++i)\n      m.col(i).swap(m.col(pivots.coeff(i)));\n\n    // ok, we have our trapezoid matrix, we can apply the triangular solver.\n    // notice that the math behind this suggests that we should apply this to the\n    // negative of the RHS, but for performance we just put the negative sign elsewhere, see below.\n    m.topLeftCorner(rank(), rank())\n     .template triangularView<Upper>().solveInPlace(\n        m.topRightCorner(rank(), dimker)\n      );\n\n    // now we must undo the column permutation that we had applied!\n    for(Index i = rank()-1; i >= 0; --i)\n      m.col(i).swap(m.col(pivots.coeff(i)));\n\n    // see the negative sign in the next line, that's what we were talking about above.\n    for(Index i = 0; i < rank(); ++i) dst.row(dec().permutationQ().indices().coeff(i)) = -m.row(i).tail(dimker);\n    for(Index i = rank(); i < cols; ++i) dst.row(dec().permutationQ().indices().coeff(i)).setZero();\n    for(Index k = 0; k < dimker; ++k) dst.coeffRef(dec().permutationQ().indices().coeff(rank()+k), k) = Scalar(1);\n  }\n};\n\n/***** Implementation of image() *****************************************************/\n\ntemplate<typename _MatrixType>\nstruct image_retval<FullPivLU<_MatrixType> >\n  : image_retval_base<FullPivLU<_MatrixType> >\n{\n  EIGEN_MAKE_IMAGE_HELPERS(FullPivLU<_MatrixType>)\n\n  enum { MaxSmallDimAtCompileTime = EIGEN_SIZE_MIN_PREFER_FIXED(\n            MatrixType::MaxColsAtCompileTime,\n            MatrixType::MaxRowsAtCompileTime)\n  };\n\n  template<typename Dest> void evalTo(Dest& dst) const\n  {\n    using std::abs;\n    if(rank() == 0)\n    {\n      // The Image is just {0}, so it doesn't have a basis properly speaking, but let's\n      // avoid crashing/asserting as that depends on floating point calculations. Let's\n      // just return a single column vector filled with zeros.\n      dst.setZero();\n      return;\n    }\n\n    Matrix<Index, Dynamic, 1, 0, MaxSmallDimAtCompileTime, 1> pivots(rank());\n    RealScalar premultiplied_threshold = dec().maxPivot() * dec().threshold();\n    Index p = 0;\n    for(Index i = 0; i < dec().nonzeroPivots(); ++i)\n      if(abs(dec().matrixLU().coeff(i,i)) > premultiplied_threshold)\n        pivots.coeffRef(p++) = i;\n    eigen_internal_assert(p == rank());\n\n    for(Index i = 0; i < rank(); ++i)\n      dst.col(i) = originalMatrix().col(dec().permutationQ().indices().coeff(pivots.coeff(i)));\n  }\n};\n\n/***** Implementation of solve() *****************************************************/\n\n} // end namespace internal\n\n#ifndef EIGEN_PARSED_BY_DOXYGEN\ntemplate<typename _MatrixType>\ntemplate<typename RhsType, typename DstType>\nvoid FullPivLU<_MatrixType>::_solve_impl(const RhsType &rhs, DstType &dst) const\n{\n  /* The decomposition PAQ = LU can be rewritten as A = P^{-1} L U Q^{-1}.\n  * So we proceed as follows:\n  * Step 1: compute c = P * rhs.\n  * Step 2: replace c by the solution x to Lx = c. Exists because L is invertible.\n  * Step 3: replace c by the solution x to Ux = c. May or may not exist.\n  * Step 4: result = Q * c;\n  */\n\n  const Index rows = this->rows(),\n              cols = this->cols(),\n              nonzero_pivots = this->rank();\n  eigen_assert(rhs.rows() == rows);\n  const Index smalldim = (std::min)(rows, cols);\n\n  if(nonzero_pivots == 0)\n  {\n    dst.setZero();\n    return;\n  }\n\n  typename RhsType::PlainObject c(rhs.rows(), rhs.cols());\n\n  // Step 1\n  c = permutationP() * rhs;\n\n  // Step 2\n  m_lu.topLeftCorner(smalldim,smalldim)\n      .template triangularView<UnitLower>()\n      .solveInPlace(c.topRows(smalldim));\n  if(rows>cols)\n    c.bottomRows(rows-cols) -= m_lu.bottomRows(rows-cols) * c.topRows(cols);\n\n  // Step 3\n  m_lu.topLeftCorner(nonzero_pivots, nonzero_pivots)\n      .template triangularView<Upper>()\n      .solveInPlace(c.topRows(nonzero_pivots));\n\n  // Step 4\n  for(Index i = 0; i < nonzero_pivots; ++i)\n    dst.row(permutationQ().indices().coeff(i)) = c.row(i);\n  for(Index i = nonzero_pivots; i < m_lu.cols(); ++i)\n    dst.row(permutationQ().indices().coeff(i)).setZero();\n}\n\ntemplate<typename _MatrixType>\ntemplate<bool Conjugate, typename RhsType, typename DstType>\nvoid FullPivLU<_MatrixType>::_solve_impl_transposed(const RhsType &rhs, DstType &dst) const\n{\n  /* The decomposition PAQ = LU can be rewritten as A = P^{-1} L U Q^{-1},\n   * and since permutations are real and unitary, we can write this\n   * as   A^T = Q U^T L^T P,\n   * So we proceed as follows:\n   * Step 1: compute c = Q^T rhs.\n   * Step 2: replace c by the solution x to U^T x = c. May or may not exist.\n   * Step 3: replace c by the solution x to L^T x = c.\n   * Step 4: result = P^T c.\n   * If Conjugate is true, replace \"^T\" by \"^*\" above.\n   */\n\n  const Index rows = this->rows(), cols = this->cols(),\n    nonzero_pivots = this->rank();\n   eigen_assert(rhs.rows() == cols);\n  const Index smalldim = (std::min)(rows, cols);\n\n  if(nonzero_pivots == 0)\n  {\n    dst.setZero();\n    return;\n  }\n\n  typename RhsType::PlainObject c(rhs.rows(), rhs.cols());\n\n  // Step 1\n  c = permutationQ().inverse() * rhs;\n\n  if (Conjugate) {\n    // Step 2\n    m_lu.topLeftCorner(nonzero_pivots, nonzero_pivots)\n        .template triangularView<Upper>()\n        .adjoint()\n        .solveInPlace(c.topRows(nonzero_pivots));\n    // Step 3\n    m_lu.topLeftCorner(smalldim, smalldim)\n        .template triangularView<UnitLower>()\n        .adjoint()\n        .solveInPlace(c.topRows(smalldim));\n  } else {\n    // Step 2\n    m_lu.topLeftCorner(nonzero_pivots, nonzero_pivots)\n        .template triangularView<Upper>()\n        .transpose()\n        .solveInPlace(c.topRows(nonzero_pivots));\n    // Step 3\n    m_lu.topLeftCorner(smalldim, smalldim)\n        .template triangularView<UnitLower>()\n        .transpose()\n        .solveInPlace(c.topRows(smalldim));\n  }\n\n  // Step 4\n  PermutationPType invp = permutationP().inverse().eval();\n  for(Index i = 0; i < smalldim; ++i)\n    dst.row(invp.indices().coeff(i)) = c.row(i);\n  for(Index i = smalldim; i < rows; ++i)\n    dst.row(invp.indices().coeff(i)).setZero();\n}\n\n#endif\n\nnamespace internal {\n\n\n/***** Implementation of inverse() *****************************************************/\ntemplate<typename DstXprType, typename MatrixType>\nstruct Assignment<DstXprType, Inverse<FullPivLU<MatrixType> >, internal::assign_op<typename DstXprType::Scalar,typename FullPivLU<MatrixType>::Scalar>, Dense2Dense>\n{\n  typedef FullPivLU<MatrixType> LuType;\n  typedef Inverse<LuType> SrcXprType;\n  static void run(DstXprType &dst, const SrcXprType &src, const internal::assign_op<typename DstXprType::Scalar,typename MatrixType::Scalar> &)\n  {\n    dst = src.nestedExpression().solve(MatrixType::Identity(src.rows(), src.cols()));\n  }\n};\n} // end namespace internal\n\n/******* MatrixBase methods *****************************************************************/\n\n/** \\lu_module\n  *\n  * \\return the full-pivoting LU decomposition of \\c *this.\n  *\n  * \\sa class FullPivLU\n  */\ntemplate<typename Derived>\ninline const FullPivLU<typename MatrixBase<Derived>::PlainObject>\nMatrixBase<Derived>::fullPivLu() const\n{\n  return FullPivLU<PlainObject>(eval());\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_LU_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/LU/InverseImpl.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2010 Benoit Jacob <jacob.benoit.1@gmail.com>\n// Copyright (C) 2014 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_INVERSE_IMPL_H\n#define EIGEN_INVERSE_IMPL_H\n\nnamespace Eigen { \n\nnamespace internal {\n\n/**********************************\n*** General case implementation ***\n**********************************/\n\ntemplate<typename MatrixType, typename ResultType, int Size = MatrixType::RowsAtCompileTime>\nstruct compute_inverse\n{\n  EIGEN_DEVICE_FUNC\n  static inline void run(const MatrixType& matrix, ResultType& result)\n  {\n    result = matrix.partialPivLu().inverse();\n  }\n};\n\ntemplate<typename MatrixType, typename ResultType, int Size = MatrixType::RowsAtCompileTime>\nstruct compute_inverse_and_det_with_check { /* nothing! general case not supported. */ };\n\n/****************************\n*** Size 1 implementation ***\n****************************/\n\ntemplate<typename MatrixType, typename ResultType>\nstruct compute_inverse<MatrixType, ResultType, 1>\n{\n  EIGEN_DEVICE_FUNC\n  static inline void run(const MatrixType& matrix, ResultType& result)\n  {\n    typedef typename MatrixType::Scalar Scalar;\n    internal::evaluator<MatrixType> matrixEval(matrix);\n    result.coeffRef(0,0) = Scalar(1) / matrixEval.coeff(0,0);\n  }\n};\n\ntemplate<typename MatrixType, typename ResultType>\nstruct compute_inverse_and_det_with_check<MatrixType, ResultType, 1>\n{\n  EIGEN_DEVICE_FUNC\n  static inline void run(\n    const MatrixType& matrix,\n    const typename MatrixType::RealScalar& absDeterminantThreshold,\n    ResultType& result,\n    typename ResultType::Scalar& determinant,\n    bool& invertible\n  )\n  {\n    using std::abs;\n    determinant = matrix.coeff(0,0);\n    invertible = abs(determinant) > absDeterminantThreshold;\n    if(invertible) result.coeffRef(0,0) = typename ResultType::Scalar(1) / determinant;\n  }\n};\n\n/****************************\n*** Size 2 implementation ***\n****************************/\n\ntemplate<typename MatrixType, typename ResultType>\nEIGEN_DEVICE_FUNC \ninline void compute_inverse_size2_helper(\n    const MatrixType& matrix, const typename ResultType::Scalar& invdet,\n    ResultType& result)\n{\n  result.coeffRef(0,0) =  matrix.coeff(1,1) * invdet;\n  result.coeffRef(1,0) = -matrix.coeff(1,0) * invdet;\n  result.coeffRef(0,1) = -matrix.coeff(0,1) * invdet;\n  result.coeffRef(1,1) =  matrix.coeff(0,0) * invdet;\n}\n\ntemplate<typename MatrixType, typename ResultType>\nstruct compute_inverse<MatrixType, ResultType, 2>\n{\n  EIGEN_DEVICE_FUNC\n  static inline void run(const MatrixType& matrix, ResultType& result)\n  {\n    typedef typename ResultType::Scalar Scalar;\n    const Scalar invdet = typename MatrixType::Scalar(1) / matrix.determinant();\n    compute_inverse_size2_helper(matrix, invdet, result);\n  }\n};\n\ntemplate<typename MatrixType, typename ResultType>\nstruct compute_inverse_and_det_with_check<MatrixType, ResultType, 2>\n{\n  EIGEN_DEVICE_FUNC\n  static inline void run(\n    const MatrixType& matrix,\n    const typename MatrixType::RealScalar& absDeterminantThreshold,\n    ResultType& inverse,\n    typename ResultType::Scalar& determinant,\n    bool& invertible\n  )\n  {\n    using std::abs;\n    typedef typename ResultType::Scalar Scalar;\n    determinant = matrix.determinant();\n    invertible = abs(determinant) > absDeterminantThreshold;\n    if(!invertible) return;\n    const Scalar invdet = Scalar(1) / determinant;\n    compute_inverse_size2_helper(matrix, invdet, inverse);\n  }\n};\n\n/****************************\n*** Size 3 implementation ***\n****************************/\n\ntemplate<typename MatrixType, int i, int j>\nEIGEN_DEVICE_FUNC \ninline typename MatrixType::Scalar cofactor_3x3(const MatrixType& m)\n{\n  enum {\n    i1 = (i+1) % 3,\n    i2 = (i+2) % 3,\n    j1 = (j+1) % 3,\n    j2 = (j+2) % 3\n  };\n  return m.coeff(i1, j1) * m.coeff(i2, j2)\n       - m.coeff(i1, j2) * m.coeff(i2, j1);\n}\n\ntemplate<typename MatrixType, typename ResultType>\nEIGEN_DEVICE_FUNC\ninline void compute_inverse_size3_helper(\n    const MatrixType& matrix,\n    const typename ResultType::Scalar& invdet,\n    const Matrix<typename ResultType::Scalar,3,1>& cofactors_col0,\n    ResultType& result)\n{\n  result.row(0) = cofactors_col0 * invdet;\n  result.coeffRef(1,0) =  cofactor_3x3<MatrixType,0,1>(matrix) * invdet;\n  result.coeffRef(1,1) =  cofactor_3x3<MatrixType,1,1>(matrix) * invdet;\n  result.coeffRef(1,2) =  cofactor_3x3<MatrixType,2,1>(matrix) * invdet;\n  result.coeffRef(2,0) =  cofactor_3x3<MatrixType,0,2>(matrix) * invdet;\n  result.coeffRef(2,1) =  cofactor_3x3<MatrixType,1,2>(matrix) * invdet;\n  result.coeffRef(2,2) =  cofactor_3x3<MatrixType,2,2>(matrix) * invdet;\n}\n\ntemplate<typename MatrixType, typename ResultType>\nstruct compute_inverse<MatrixType, ResultType, 3>\n{\n  EIGEN_DEVICE_FUNC\n  static inline void run(const MatrixType& matrix, ResultType& result)\n  {\n    typedef typename ResultType::Scalar Scalar;\n    Matrix<typename MatrixType::Scalar,3,1> cofactors_col0;\n    cofactors_col0.coeffRef(0) =  cofactor_3x3<MatrixType,0,0>(matrix);\n    cofactors_col0.coeffRef(1) =  cofactor_3x3<MatrixType,1,0>(matrix);\n    cofactors_col0.coeffRef(2) =  cofactor_3x3<MatrixType,2,0>(matrix);\n    const Scalar det = (cofactors_col0.cwiseProduct(matrix.col(0))).sum();\n    const Scalar invdet = Scalar(1) / det;\n    compute_inverse_size3_helper(matrix, invdet, cofactors_col0, result);\n  }\n};\n\ntemplate<typename MatrixType, typename ResultType>\nstruct compute_inverse_and_det_with_check<MatrixType, ResultType, 3>\n{\n  EIGEN_DEVICE_FUNC\n  static inline void run(\n    const MatrixType& matrix,\n    const typename MatrixType::RealScalar& absDeterminantThreshold,\n    ResultType& inverse,\n    typename ResultType::Scalar& determinant,\n    bool& invertible\n  )\n  {\n    using std::abs;\n    typedef typename ResultType::Scalar Scalar;\n    Matrix<Scalar,3,1> cofactors_col0;\n    cofactors_col0.coeffRef(0) =  cofactor_3x3<MatrixType,0,0>(matrix);\n    cofactors_col0.coeffRef(1) =  cofactor_3x3<MatrixType,1,0>(matrix);\n    cofactors_col0.coeffRef(2) =  cofactor_3x3<MatrixType,2,0>(matrix);\n    determinant = (cofactors_col0.cwiseProduct(matrix.col(0))).sum();\n    invertible = abs(determinant) > absDeterminantThreshold;\n    if(!invertible) return;\n    const Scalar invdet = Scalar(1) / determinant;\n    compute_inverse_size3_helper(matrix, invdet, cofactors_col0, inverse);\n  }\n};\n\n/****************************\n*** Size 4 implementation ***\n****************************/\n\ntemplate<typename Derived>\nEIGEN_DEVICE_FUNC \ninline const typename Derived::Scalar general_det3_helper\n(const MatrixBase<Derived>& matrix, int i1, int i2, int i3, int j1, int j2, int j3)\n{\n  return matrix.coeff(i1,j1)\n         * (matrix.coeff(i2,j2) * matrix.coeff(i3,j3) - matrix.coeff(i2,j3) * matrix.coeff(i3,j2));\n}\n\ntemplate<typename MatrixType, int i, int j>\nEIGEN_DEVICE_FUNC \ninline typename MatrixType::Scalar cofactor_4x4(const MatrixType& matrix)\n{\n  enum {\n    i1 = (i+1) % 4,\n    i2 = (i+2) % 4,\n    i3 = (i+3) % 4,\n    j1 = (j+1) % 4,\n    j2 = (j+2) % 4,\n    j3 = (j+3) % 4\n  };\n  return general_det3_helper(matrix, i1, i2, i3, j1, j2, j3)\n       + general_det3_helper(matrix, i2, i3, i1, j1, j2, j3)\n       + general_det3_helper(matrix, i3, i1, i2, j1, j2, j3);\n}\n\ntemplate<int Arch, typename Scalar, typename MatrixType, typename ResultType>\nstruct compute_inverse_size4\n{\n  EIGEN_DEVICE_FUNC\n  static void run(const MatrixType& matrix, ResultType& result)\n  {\n    result.coeffRef(0,0) =  cofactor_4x4<MatrixType,0,0>(matrix);\n    result.coeffRef(1,0) = -cofactor_4x4<MatrixType,0,1>(matrix);\n    result.coeffRef(2,0) =  cofactor_4x4<MatrixType,0,2>(matrix);\n    result.coeffRef(3,0) = -cofactor_4x4<MatrixType,0,3>(matrix);\n    result.coeffRef(0,2) =  cofactor_4x4<MatrixType,2,0>(matrix);\n    result.coeffRef(1,2) = -cofactor_4x4<MatrixType,2,1>(matrix);\n    result.coeffRef(2,2) =  cofactor_4x4<MatrixType,2,2>(matrix);\n    result.coeffRef(3,2) = -cofactor_4x4<MatrixType,2,3>(matrix);\n    result.coeffRef(0,1) = -cofactor_4x4<MatrixType,1,0>(matrix);\n    result.coeffRef(1,1) =  cofactor_4x4<MatrixType,1,1>(matrix);\n    result.coeffRef(2,1) = -cofactor_4x4<MatrixType,1,2>(matrix);\n    result.coeffRef(3,1) =  cofactor_4x4<MatrixType,1,3>(matrix);\n    result.coeffRef(0,3) = -cofactor_4x4<MatrixType,3,0>(matrix);\n    result.coeffRef(1,3) =  cofactor_4x4<MatrixType,3,1>(matrix);\n    result.coeffRef(2,3) = -cofactor_4x4<MatrixType,3,2>(matrix);\n    result.coeffRef(3,3) =  cofactor_4x4<MatrixType,3,3>(matrix);\n    result /= (matrix.col(0).cwiseProduct(result.row(0).transpose())).sum();\n  }\n};\n\ntemplate<typename MatrixType, typename ResultType>\nstruct compute_inverse<MatrixType, ResultType, 4>\n : compute_inverse_size4<Architecture::Target, typename MatrixType::Scalar,\n                            MatrixType, ResultType>\n{\n};\n\ntemplate<typename MatrixType, typename ResultType>\nstruct compute_inverse_and_det_with_check<MatrixType, ResultType, 4>\n{\n  EIGEN_DEVICE_FUNC\n  static inline void run(\n    const MatrixType& matrix,\n    const typename MatrixType::RealScalar& absDeterminantThreshold,\n    ResultType& inverse,\n    typename ResultType::Scalar& determinant,\n    bool& invertible\n  )\n  {\n    using std::abs;\n    determinant = matrix.determinant();\n    invertible = abs(determinant) > absDeterminantThreshold;\n    if(invertible) compute_inverse<MatrixType, ResultType>::run(matrix, inverse);\n  }\n};\n\n/*************************\n*** MatrixBase methods ***\n*************************/\n\n} // end namespace internal\n\nnamespace internal {\n\n// Specialization for \"dense = dense_xpr.inverse()\"\ntemplate<typename DstXprType, typename XprType>\nstruct Assignment<DstXprType, Inverse<XprType>, internal::assign_op<typename DstXprType::Scalar,typename XprType::Scalar>, Dense2Dense>\n{\n  typedef Inverse<XprType> SrcXprType;\n  static void run(DstXprType &dst, const SrcXprType &src, const internal::assign_op<typename DstXprType::Scalar,typename XprType::Scalar> &)\n  {\n    Index dstRows = src.rows();\n    Index dstCols = src.cols();\n    if((dst.rows()!=dstRows) || (dst.cols()!=dstCols))\n      dst.resize(dstRows, dstCols);\n    \n    const int Size = EIGEN_PLAIN_ENUM_MIN(XprType::ColsAtCompileTime,DstXprType::ColsAtCompileTime);\n    EIGEN_ONLY_USED_FOR_DEBUG(Size);\n    eigen_assert(( (Size<=1) || (Size>4) || (extract_data(src.nestedExpression())!=extract_data(dst)))\n              && \"Aliasing problem detected in inverse(), you need to do inverse().eval() here.\");\n\n    typedef typename internal::nested_eval<XprType,XprType::ColsAtCompileTime>::type  ActualXprType;\n    typedef typename internal::remove_all<ActualXprType>::type                        ActualXprTypeCleanded;\n    \n    ActualXprType actual_xpr(src.nestedExpression());\n    \n    compute_inverse<ActualXprTypeCleanded, DstXprType>::run(actual_xpr, dst);\n  }\n};\n\n  \n} // end namespace internal\n\n/** \\lu_module\n  *\n  * \\returns the matrix inverse of this matrix.\n  *\n  * For small fixed sizes up to 4x4, this method uses cofactors.\n  * In the general case, this method uses class PartialPivLU.\n  *\n  * \\note This matrix must be invertible, otherwise the result is undefined. If you need an\n  * invertibility check, do the following:\n  * \\li for fixed sizes up to 4x4, use computeInverseAndDetWithCheck().\n  * \\li for the general case, use class FullPivLU.\n  *\n  * Example: \\include MatrixBase_inverse.cpp\n  * Output: \\verbinclude MatrixBase_inverse.out\n  *\n  * \\sa computeInverseAndDetWithCheck()\n  */\ntemplate<typename Derived>\ninline const Inverse<Derived> MatrixBase<Derived>::inverse() const\n{\n  EIGEN_STATIC_ASSERT(!NumTraits<Scalar>::IsInteger,THIS_FUNCTION_IS_NOT_FOR_INTEGER_NUMERIC_TYPES)\n  eigen_assert(rows() == cols());\n  return Inverse<Derived>(derived());\n}\n\n/** \\lu_module\n  *\n  * Computation of matrix inverse and determinant, with invertibility check.\n  *\n  * This is only for fixed-size square matrices of size up to 4x4.\n  *\n  * \\param inverse Reference to the matrix in which to store the inverse.\n  * \\param determinant Reference to the variable in which to store the determinant.\n  * \\param invertible Reference to the bool variable in which to store whether the matrix is invertible.\n  * \\param absDeterminantThreshold Optional parameter controlling the invertibility check.\n  *                                The matrix will be declared invertible if the absolute value of its\n  *                                determinant is greater than this threshold.\n  *\n  * Example: \\include MatrixBase_computeInverseAndDetWithCheck.cpp\n  * Output: \\verbinclude MatrixBase_computeInverseAndDetWithCheck.out\n  *\n  * \\sa inverse(), computeInverseWithCheck()\n  */\ntemplate<typename Derived>\ntemplate<typename ResultType>\ninline void MatrixBase<Derived>::computeInverseAndDetWithCheck(\n    ResultType& inverse,\n    typename ResultType::Scalar& determinant,\n    bool& invertible,\n    const RealScalar& absDeterminantThreshold\n  ) const\n{\n  // i'd love to put some static assertions there, but SFINAE means that they have no effect...\n  eigen_assert(rows() == cols());\n  // for 2x2, it's worth giving a chance to avoid evaluating.\n  // for larger sizes, evaluating has negligible cost and limits code size.\n  typedef typename internal::conditional<\n    RowsAtCompileTime == 2,\n    typename internal::remove_all<typename internal::nested_eval<Derived, 2>::type>::type,\n    PlainObject\n  >::type MatrixType;\n  internal::compute_inverse_and_det_with_check<MatrixType, ResultType>::run\n    (derived(), absDeterminantThreshold, inverse, determinant, invertible);\n}\n\n/** \\lu_module\n  *\n  * Computation of matrix inverse, with invertibility check.\n  *\n  * This is only for fixed-size square matrices of size up to 4x4.\n  *\n  * \\param inverse Reference to the matrix in which to store the inverse.\n  * \\param invertible Reference to the bool variable in which to store whether the matrix is invertible.\n  * \\param absDeterminantThreshold Optional parameter controlling the invertibility check.\n  *                                The matrix will be declared invertible if the absolute value of its\n  *                                determinant is greater than this threshold.\n  *\n  * Example: \\include MatrixBase_computeInverseWithCheck.cpp\n  * Output: \\verbinclude MatrixBase_computeInverseWithCheck.out\n  *\n  * \\sa inverse(), computeInverseAndDetWithCheck()\n  */\ntemplate<typename Derived>\ntemplate<typename ResultType>\ninline void MatrixBase<Derived>::computeInverseWithCheck(\n    ResultType& inverse,\n    bool& invertible,\n    const RealScalar& absDeterminantThreshold\n  ) const\n{\n  RealScalar determinant;\n  // i'd love to put some static assertions there, but SFINAE means that they have no effect...\n  eigen_assert(rows() == cols());\n  computeInverseAndDetWithCheck(inverse,determinant,invertible,absDeterminantThreshold);\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_INVERSE_IMPL_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/LU/PartialPivLU.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2006-2009 Benoit Jacob <jacob.benoit.1@gmail.com>\n// Copyright (C) 2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_PARTIALLU_H\n#define EIGEN_PARTIALLU_H\n\nnamespace Eigen {\n\nnamespace internal {\ntemplate<typename _MatrixType> struct traits<PartialPivLU<_MatrixType> >\n : traits<_MatrixType>\n{\n  typedef MatrixXpr XprKind;\n  typedef SolverStorage StorageKind;\n  typedef traits<_MatrixType> BaseTraits;\n  enum {\n    Flags = BaseTraits::Flags & RowMajorBit,\n    CoeffReadCost = Dynamic\n  };\n};\n\ntemplate<typename T,typename Derived>\nstruct enable_if_ref;\n// {\n//   typedef Derived type;\n// };\n\ntemplate<typename T,typename Derived>\nstruct enable_if_ref<Ref<T>,Derived> {\n  typedef Derived type;\n};\n\n} // end namespace internal\n\n/** \\ingroup LU_Module\n  *\n  * \\class PartialPivLU\n  *\n  * \\brief LU decomposition of a matrix with partial pivoting, and related features\n  *\n  * \\tparam _MatrixType the type of the matrix of which we are computing the LU decomposition\n  *\n  * This class represents a LU decomposition of a \\b square \\b invertible matrix, with partial pivoting: the matrix A\n  * is decomposed as A = PLU where L is unit-lower-triangular, U is upper-triangular, and P\n  * is a permutation matrix.\n  *\n  * Typically, partial pivoting LU decomposition is only considered numerically stable for square invertible\n  * matrices. Thus LAPACK's dgesv and dgesvx require the matrix to be square and invertible. The present class\n  * does the same. It will assert that the matrix is square, but it won't (actually it can't) check that the\n  * matrix is invertible: it is your task to check that you only use this decomposition on invertible matrices.\n  *\n  * The guaranteed safe alternative, working for all matrices, is the full pivoting LU decomposition, provided\n  * by class FullPivLU.\n  *\n  * This is \\b not a rank-revealing LU decomposition. Many features are intentionally absent from this class,\n  * such as rank computation. If you need these features, use class FullPivLU.\n  *\n  * This LU decomposition is suitable to invert invertible matrices. It is what MatrixBase::inverse() uses\n  * in the general case.\n  * On the other hand, it is \\b not suitable to determine whether a given matrix is invertible.\n  *\n  * The data of the LU decomposition can be directly accessed through the methods matrixLU(), permutationP().\n  *\n  * This class supports the \\link InplaceDecomposition inplace decomposition \\endlink mechanism.\n  * \n  * \\sa MatrixBase::partialPivLu(), MatrixBase::determinant(), MatrixBase::inverse(), MatrixBase::computeInverse(), class FullPivLU\n  */\ntemplate<typename _MatrixType> class PartialPivLU\n  : public SolverBase<PartialPivLU<_MatrixType> >\n{\n  public:\n\n    typedef _MatrixType MatrixType;\n    typedef SolverBase<PartialPivLU> Base;\n    EIGEN_GENERIC_PUBLIC_INTERFACE(PartialPivLU)\n    // FIXME StorageIndex defined in EIGEN_GENERIC_PUBLIC_INTERFACE should be int\n    enum {\n      MaxRowsAtCompileTime = MatrixType::MaxRowsAtCompileTime,\n      MaxColsAtCompileTime = MatrixType::MaxColsAtCompileTime\n    };\n    typedef PermutationMatrix<RowsAtCompileTime, MaxRowsAtCompileTime> PermutationType;\n    typedef Transpositions<RowsAtCompileTime, MaxRowsAtCompileTime> TranspositionType;\n    typedef typename MatrixType::PlainObject PlainObject;\n\n    /**\n      * \\brief Default Constructor.\n      *\n      * The default constructor is useful in cases in which the user intends to\n      * perform decompositions via PartialPivLU::compute(const MatrixType&).\n      */\n    PartialPivLU();\n\n    /** \\brief Default Constructor with memory preallocation\n      *\n      * Like the default constructor but with preallocation of the internal data\n      * according to the specified problem \\a size.\n      * \\sa PartialPivLU()\n      */\n    explicit PartialPivLU(Index size);\n\n    /** Constructor.\n      *\n      * \\param matrix the matrix of which to compute the LU decomposition.\n      *\n      * \\warning The matrix should have full rank (e.g. if it's square, it should be invertible).\n      * If you need to deal with non-full rank, use class FullPivLU instead.\n      */\n    template<typename InputType>\n    explicit PartialPivLU(const EigenBase<InputType>& matrix);\n\n    /** Constructor for \\link InplaceDecomposition inplace decomposition \\endlink\n      *\n      * \\param matrix the matrix of which to compute the LU decomposition.\n      *\n      * \\warning The matrix should have full rank (e.g. if it's square, it should be invertible).\n      * If you need to deal with non-full rank, use class FullPivLU instead.\n      */\n    template<typename InputType>\n    explicit PartialPivLU(EigenBase<InputType>& matrix);\n\n    template<typename InputType>\n    PartialPivLU& compute(const EigenBase<InputType>& matrix) {\n      m_lu = matrix.derived();\n      compute();\n      return *this;\n    }\n\n    /** \\returns the LU decomposition matrix: the upper-triangular part is U, the\n      * unit-lower-triangular part is L (at least for square matrices; in the non-square\n      * case, special care is needed, see the documentation of class FullPivLU).\n      *\n      * \\sa matrixL(), matrixU()\n      */\n    inline const MatrixType& matrixLU() const\n    {\n      eigen_assert(m_isInitialized && \"PartialPivLU is not initialized.\");\n      return m_lu;\n    }\n\n    /** \\returns the permutation matrix P.\n      */\n    inline const PermutationType& permutationP() const\n    {\n      eigen_assert(m_isInitialized && \"PartialPivLU is not initialized.\");\n      return m_p;\n    }\n\n    /** This method returns the solution x to the equation Ax=b, where A is the matrix of which\n      * *this is the LU decomposition.\n      *\n      * \\param b the right-hand-side of the equation to solve. Can be a vector or a matrix,\n      *          the only requirement in order for the equation to make sense is that\n      *          b.rows()==A.rows(), where A is the matrix of which *this is the LU decomposition.\n      *\n      * \\returns the solution.\n      *\n      * Example: \\include PartialPivLU_solve.cpp\n      * Output: \\verbinclude PartialPivLU_solve.out\n      *\n      * Since this PartialPivLU class assumes anyway that the matrix A is invertible, the solution\n      * theoretically exists and is unique regardless of b.\n      *\n      * \\sa TriangularView::solve(), inverse(), computeInverse()\n      */\n    // FIXME this is a copy-paste of the base-class member to add the isInitialized assertion.\n    template<typename Rhs>\n    inline const Solve<PartialPivLU, Rhs>\n    solve(const MatrixBase<Rhs>& b) const\n    {\n      eigen_assert(m_isInitialized && \"PartialPivLU is not initialized.\");\n      return Solve<PartialPivLU, Rhs>(*this, b.derived());\n    }\n\n    /** \\returns an estimate of the reciprocal condition number of the matrix of which \\c *this is\n        the LU decomposition.\n      */\n    inline RealScalar rcond() const\n    {\n      eigen_assert(m_isInitialized && \"PartialPivLU is not initialized.\");\n      return internal::rcond_estimate_helper(m_l1_norm, *this);\n    }\n\n    /** \\returns the inverse of the matrix of which *this is the LU decomposition.\n      *\n      * \\warning The matrix being decomposed here is assumed to be invertible. If you need to check for\n      *          invertibility, use class FullPivLU instead.\n      *\n      * \\sa MatrixBase::inverse(), LU::inverse()\n      */\n    inline const Inverse<PartialPivLU> inverse() const\n    {\n      eigen_assert(m_isInitialized && \"PartialPivLU is not initialized.\");\n      return Inverse<PartialPivLU>(*this);\n    }\n\n    /** \\returns the determinant of the matrix of which\n      * *this is the LU decomposition. It has only linear complexity\n      * (that is, O(n) where n is the dimension of the square matrix)\n      * as the LU decomposition has already been computed.\n      *\n      * \\note For fixed-size matrices of size up to 4, MatrixBase::determinant() offers\n      *       optimized paths.\n      *\n      * \\warning a determinant can be very big or small, so for matrices\n      * of large enough dimension, there is a risk of overflow/underflow.\n      *\n      * \\sa MatrixBase::determinant()\n      */\n    Scalar determinant() const;\n\n    MatrixType reconstructedMatrix() const;\n\n    inline Index rows() const { return m_lu.rows(); }\n    inline Index cols() const { return m_lu.cols(); }\n\n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    template<typename RhsType, typename DstType>\n    EIGEN_DEVICE_FUNC\n    void _solve_impl(const RhsType &rhs, DstType &dst) const {\n     /* The decomposition PA = LU can be rewritten as A = P^{-1} L U.\n      * So we proceed as follows:\n      * Step 1: compute c = Pb.\n      * Step 2: replace c by the solution x to Lx = c.\n      * Step 3: replace c by the solution x to Ux = c.\n      */\n\n      eigen_assert(rhs.rows() == m_lu.rows());\n\n      // Step 1\n      dst = permutationP() * rhs;\n\n      // Step 2\n      m_lu.template triangularView<UnitLower>().solveInPlace(dst);\n\n      // Step 3\n      m_lu.template triangularView<Upper>().solveInPlace(dst);\n    }\n\n    template<bool Conjugate, typename RhsType, typename DstType>\n    EIGEN_DEVICE_FUNC\n    void _solve_impl_transposed(const RhsType &rhs, DstType &dst) const {\n     /* The decomposition PA = LU can be rewritten as A = P^{-1} L U.\n      * So we proceed as follows:\n      * Step 1: compute c = Pb.\n      * Step 2: replace c by the solution x to Lx = c.\n      * Step 3: replace c by the solution x to Ux = c.\n      */\n\n      eigen_assert(rhs.rows() == m_lu.cols());\n\n      if (Conjugate) {\n        // Step 1\n        dst = m_lu.template triangularView<Upper>().adjoint().solve(rhs);\n        // Step 2\n        m_lu.template triangularView<UnitLower>().adjoint().solveInPlace(dst);\n      } else {\n        // Step 1\n        dst = m_lu.template triangularView<Upper>().transpose().solve(rhs);\n        // Step 2\n        m_lu.template triangularView<UnitLower>().transpose().solveInPlace(dst);\n      }\n      // Step 3\n      dst = permutationP().transpose() * dst;\n    }\n    #endif\n\n  protected:\n\n    static void check_template_parameters()\n    {\n      EIGEN_STATIC_ASSERT_NON_INTEGER(Scalar);\n    }\n\n    void compute();\n\n    MatrixType m_lu;\n    PermutationType m_p;\n    TranspositionType m_rowsTranspositions;\n    RealScalar m_l1_norm;\n    signed char m_det_p;\n    bool m_isInitialized;\n};\n\ntemplate<typename MatrixType>\nPartialPivLU<MatrixType>::PartialPivLU()\n  : m_lu(),\n    m_p(),\n    m_rowsTranspositions(),\n    m_l1_norm(0),\n    m_det_p(0),\n    m_isInitialized(false)\n{\n}\n\ntemplate<typename MatrixType>\nPartialPivLU<MatrixType>::PartialPivLU(Index size)\n  : m_lu(size, size),\n    m_p(size),\n    m_rowsTranspositions(size),\n    m_l1_norm(0),\n    m_det_p(0),\n    m_isInitialized(false)\n{\n}\n\ntemplate<typename MatrixType>\ntemplate<typename InputType>\nPartialPivLU<MatrixType>::PartialPivLU(const EigenBase<InputType>& matrix)\n  : m_lu(matrix.rows(),matrix.cols()),\n    m_p(matrix.rows()),\n    m_rowsTranspositions(matrix.rows()),\n    m_l1_norm(0),\n    m_det_p(0),\n    m_isInitialized(false)\n{\n  compute(matrix.derived());\n}\n\ntemplate<typename MatrixType>\ntemplate<typename InputType>\nPartialPivLU<MatrixType>::PartialPivLU(EigenBase<InputType>& matrix)\n  : m_lu(matrix.derived()),\n    m_p(matrix.rows()),\n    m_rowsTranspositions(matrix.rows()),\n    m_l1_norm(0),\n    m_det_p(0),\n    m_isInitialized(false)\n{\n  compute();\n}\n\nnamespace internal {\n\n/** \\internal This is the blocked version of fullpivlu_unblocked() */\ntemplate<typename Scalar, int StorageOrder, typename PivIndex>\nstruct partial_lu_impl\n{\n  // FIXME add a stride to Map, so that the following mapping becomes easier,\n  // another option would be to create an expression being able to automatically\n  // warp any Map, Matrix, and Block expressions as a unique type, but since that's exactly\n  // a Map + stride, why not adding a stride to Map, and convenient ctors from a Matrix,\n  // and Block.\n  typedef Map<Matrix<Scalar, Dynamic, Dynamic, StorageOrder> > MapLU;\n  typedef Block<MapLU, Dynamic, Dynamic> MatrixType;\n  typedef Block<MatrixType,Dynamic,Dynamic> BlockType;\n  typedef typename MatrixType::RealScalar RealScalar;\n\n  /** \\internal performs the LU decomposition in-place of the matrix \\a lu\n    * using an unblocked algorithm.\n    *\n    * In addition, this function returns the row transpositions in the\n    * vector \\a row_transpositions which must have a size equal to the number\n    * of columns of the matrix \\a lu, and an integer \\a nb_transpositions\n    * which returns the actual number of transpositions.\n    *\n    * \\returns The index of the first pivot which is exactly zero if any, or a negative number otherwise.\n    */\n  static Index unblocked_lu(MatrixType& lu, PivIndex* row_transpositions, PivIndex& nb_transpositions)\n  {\n    typedef scalar_score_coeff_op<Scalar> Scoring;\n    typedef typename Scoring::result_type Score;\n    const Index rows = lu.rows();\n    const Index cols = lu.cols();\n    const Index size = (std::min)(rows,cols);\n    nb_transpositions = 0;\n    Index first_zero_pivot = -1;\n    for(Index k = 0; k < size; ++k)\n    {\n      Index rrows = rows-k-1;\n      Index rcols = cols-k-1;\n\n      Index row_of_biggest_in_col;\n      Score biggest_in_corner\n        = lu.col(k).tail(rows-k).unaryExpr(Scoring()).maxCoeff(&row_of_biggest_in_col);\n      row_of_biggest_in_col += k;\n\n      row_transpositions[k] = PivIndex(row_of_biggest_in_col);\n\n      if(biggest_in_corner != Score(0))\n      {\n        if(k != row_of_biggest_in_col)\n        {\n          lu.row(k).swap(lu.row(row_of_biggest_in_col));\n          ++nb_transpositions;\n        }\n\n        // FIXME shall we introduce a safe quotient expression in cas 1/lu.coeff(k,k)\n        // overflow but not the actual quotient?\n        lu.col(k).tail(rrows) /= lu.coeff(k,k);\n      }\n      else if(first_zero_pivot==-1)\n      {\n        // the pivot is exactly zero, we record the index of the first pivot which is exactly 0,\n        // and continue the factorization such we still have A = PLU\n        first_zero_pivot = k;\n      }\n\n      if(k<rows-1)\n        lu.bottomRightCorner(rrows,rcols).noalias() -= lu.col(k).tail(rrows) * lu.row(k).tail(rcols);\n    }\n    return first_zero_pivot;\n  }\n\n  /** \\internal performs the LU decomposition in-place of the matrix represented\n    * by the variables \\a rows, \\a cols, \\a lu_data, and \\a lu_stride using a\n    * recursive, blocked algorithm.\n    *\n    * In addition, this function returns the row transpositions in the\n    * vector \\a row_transpositions which must have a size equal to the number\n    * of columns of the matrix \\a lu, and an integer \\a nb_transpositions\n    * which returns the actual number of transpositions.\n    *\n    * \\returns The index of the first pivot which is exactly zero if any, or a negative number otherwise.\n    *\n    * \\note This very low level interface using pointers, etc. is to:\n    *   1 - reduce the number of instanciations to the strict minimum\n    *   2 - avoid infinite recursion of the instanciations with Block<Block<Block<...> > >\n    */\n  static Index blocked_lu(Index rows, Index cols, Scalar* lu_data, Index luStride, PivIndex* row_transpositions, PivIndex& nb_transpositions, Index maxBlockSize=256)\n  {\n    MapLU lu1(lu_data,StorageOrder==RowMajor?rows:luStride,StorageOrder==RowMajor?luStride:cols);\n    MatrixType lu(lu1,0,0,rows,cols);\n\n    const Index size = (std::min)(rows,cols);\n\n    // if the matrix is too small, no blocking:\n    if(size<=16)\n    {\n      return unblocked_lu(lu, row_transpositions, nb_transpositions);\n    }\n\n    // automatically adjust the number of subdivisions to the size\n    // of the matrix so that there is enough sub blocks:\n    Index blockSize;\n    {\n      blockSize = size/8;\n      blockSize = (blockSize/16)*16;\n      blockSize = (std::min)((std::max)(blockSize,Index(8)), maxBlockSize);\n    }\n\n    nb_transpositions = 0;\n    Index first_zero_pivot = -1;\n    for(Index k = 0; k < size; k+=blockSize)\n    {\n      Index bs = (std::min)(size-k,blockSize); // actual size of the block\n      Index trows = rows - k - bs; // trailing rows\n      Index tsize = size - k - bs; // trailing size\n\n      // partition the matrix:\n      //                          A00 | A01 | A02\n      // lu  = A_0 | A_1 | A_2 =  A10 | A11 | A12\n      //                          A20 | A21 | A22\n      BlockType A_0(lu,0,0,rows,k);\n      BlockType A_2(lu,0,k+bs,rows,tsize);\n      BlockType A11(lu,k,k,bs,bs);\n      BlockType A12(lu,k,k+bs,bs,tsize);\n      BlockType A21(lu,k+bs,k,trows,bs);\n      BlockType A22(lu,k+bs,k+bs,trows,tsize);\n\n      PivIndex nb_transpositions_in_panel;\n      // recursively call the blocked LU algorithm on [A11^T A21^T]^T\n      // with a very small blocking size:\n      Index ret = blocked_lu(trows+bs, bs, &lu.coeffRef(k,k), luStride,\n                   row_transpositions+k, nb_transpositions_in_panel, 16);\n      if(ret>=0 && first_zero_pivot==-1)\n        first_zero_pivot = k+ret;\n\n      nb_transpositions += nb_transpositions_in_panel;\n      // update permutations and apply them to A_0\n      for(Index i=k; i<k+bs; ++i)\n      {\n        Index piv = (row_transpositions[i] += internal::convert_index<PivIndex>(k));\n        A_0.row(i).swap(A_0.row(piv));\n      }\n\n      if(trows)\n      {\n        // apply permutations to A_2\n        for(Index i=k;i<k+bs; ++i)\n          A_2.row(i).swap(A_2.row(row_transpositions[i]));\n\n        // A12 = A11^-1 A12\n        A11.template triangularView<UnitLower>().solveInPlace(A12);\n\n        A22.noalias() -= A21 * A12;\n      }\n    }\n    return first_zero_pivot;\n  }\n};\n\n/** \\internal performs the LU decomposition with partial pivoting in-place.\n  */\ntemplate<typename MatrixType, typename TranspositionType>\nvoid partial_lu_inplace(MatrixType& lu, TranspositionType& row_transpositions, typename TranspositionType::StorageIndex& nb_transpositions)\n{\n  eigen_assert(lu.cols() == row_transpositions.size());\n  eigen_assert((&row_transpositions.coeffRef(1)-&row_transpositions.coeffRef(0)) == 1);\n\n  partial_lu_impl\n    <typename MatrixType::Scalar, MatrixType::Flags&RowMajorBit?RowMajor:ColMajor, typename TranspositionType::StorageIndex>\n    ::blocked_lu(lu.rows(), lu.cols(), &lu.coeffRef(0,0), lu.outerStride(), &row_transpositions.coeffRef(0), nb_transpositions);\n}\n\n} // end namespace internal\n\ntemplate<typename MatrixType>\nvoid PartialPivLU<MatrixType>::compute()\n{\n  check_template_parameters();\n\n  // the row permutation is stored as int indices, so just to be sure:\n  eigen_assert(m_lu.rows()<NumTraits<int>::highest());\n\n  m_l1_norm = m_lu.cwiseAbs().colwise().sum().maxCoeff();\n\n  eigen_assert(m_lu.rows() == m_lu.cols() && \"PartialPivLU is only for square (and moreover invertible) matrices\");\n  const Index size = m_lu.rows();\n\n  m_rowsTranspositions.resize(size);\n\n  typename TranspositionType::StorageIndex nb_transpositions;\n  internal::partial_lu_inplace(m_lu, m_rowsTranspositions, nb_transpositions);\n  m_det_p = (nb_transpositions%2) ? -1 : 1;\n\n  m_p = m_rowsTranspositions;\n\n  m_isInitialized = true;\n}\n\ntemplate<typename MatrixType>\ntypename PartialPivLU<MatrixType>::Scalar PartialPivLU<MatrixType>::determinant() const\n{\n  eigen_assert(m_isInitialized && \"PartialPivLU is not initialized.\");\n  return Scalar(m_det_p) * m_lu.diagonal().prod();\n}\n\n/** \\returns the matrix represented by the decomposition,\n * i.e., it returns the product: P^{-1} L U.\n * This function is provided for debug purpose. */\ntemplate<typename MatrixType>\nMatrixType PartialPivLU<MatrixType>::reconstructedMatrix() const\n{\n  eigen_assert(m_isInitialized && \"LU is not initialized.\");\n  // LU\n  MatrixType res = m_lu.template triangularView<UnitLower>().toDenseMatrix()\n                 * m_lu.template triangularView<Upper>();\n\n  // P^{-1}(LU)\n  res = m_p.inverse() * res;\n\n  return res;\n}\n\n/***** Implementation details *****************************************************/\n\nnamespace internal {\n\n/***** Implementation of inverse() *****************************************************/\ntemplate<typename DstXprType, typename MatrixType>\nstruct Assignment<DstXprType, Inverse<PartialPivLU<MatrixType> >, internal::assign_op<typename DstXprType::Scalar,typename PartialPivLU<MatrixType>::Scalar>, Dense2Dense>\n{\n  typedef PartialPivLU<MatrixType> LuType;\n  typedef Inverse<LuType> SrcXprType;\n  static void run(DstXprType &dst, const SrcXprType &src, const internal::assign_op<typename DstXprType::Scalar,typename LuType::Scalar> &)\n  {\n    dst = src.nestedExpression().solve(MatrixType::Identity(src.rows(), src.cols()));\n  }\n};\n} // end namespace internal\n\n/******** MatrixBase methods *******/\n\n/** \\lu_module\n  *\n  * \\return the partial-pivoting LU decomposition of \\c *this.\n  *\n  * \\sa class PartialPivLU\n  */\ntemplate<typename Derived>\ninline const PartialPivLU<typename MatrixBase<Derived>::PlainObject>\nMatrixBase<Derived>::partialPivLu() const\n{\n  return PartialPivLU<PlainObject>(eval());\n}\n\n/** \\lu_module\n  *\n  * Synonym of partialPivLu().\n  *\n  * \\return the partial-pivoting LU decomposition of \\c *this.\n  *\n  * \\sa class PartialPivLU\n  */\ntemplate<typename Derived>\ninline const PartialPivLU<typename MatrixBase<Derived>::PlainObject>\nMatrixBase<Derived>::lu() const\n{\n  return PartialPivLU<PlainObject>(eval());\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_PARTIALLU_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/LU/PartialPivLU_LAPACKE.h",
    "content": "/*\n Copyright (c) 2011, Intel Corporation. All rights reserved.\n\n Redistribution and use in source and binary forms, with or without modification,\n are permitted provided that the following conditions are met:\n\n * Redistributions of source code must retain the above copyright notice, this\n   list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright notice,\n   this list of conditions and the following disclaimer in the documentation\n   and/or other materials provided with the distribution.\n * Neither the name of Intel Corporation nor the names of its contributors may\n   be used to endorse or promote products derived from this software without\n   specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n ********************************************************************************\n *   Content : Eigen bindings to LAPACKe\n *     LU decomposition with partial pivoting based on LAPACKE_?getrf function.\n ********************************************************************************\n*/\n\n#ifndef EIGEN_PARTIALLU_LAPACK_H\n#define EIGEN_PARTIALLU_LAPACK_H\n\nnamespace Eigen { \n\nnamespace internal {\n\n/** \\internal Specialization for the data types supported by LAPACKe */\n\n#define EIGEN_LAPACKE_LU_PARTPIV(EIGTYPE, LAPACKE_TYPE, LAPACKE_PREFIX) \\\ntemplate<int StorageOrder> \\\nstruct partial_lu_impl<EIGTYPE, StorageOrder, lapack_int> \\\n{ \\\n  /* \\internal performs the LU decomposition in-place of the matrix represented */ \\\n  static lapack_int blocked_lu(Index rows, Index cols, EIGTYPE* lu_data, Index luStride, lapack_int* row_transpositions, lapack_int& nb_transpositions, lapack_int maxBlockSize=256) \\\n  { \\\n    EIGEN_UNUSED_VARIABLE(maxBlockSize);\\\n    lapack_int matrix_order, first_zero_pivot; \\\n    lapack_int m, n, lda, *ipiv, info; \\\n    EIGTYPE* a; \\\n/* Set up parameters for ?getrf */ \\\n    matrix_order = StorageOrder==RowMajor ? LAPACK_ROW_MAJOR : LAPACK_COL_MAJOR; \\\n    lda = convert_index<lapack_int>(luStride); \\\n    a = lu_data; \\\n    ipiv = row_transpositions; \\\n    m = convert_index<lapack_int>(rows); \\\n    n = convert_index<lapack_int>(cols); \\\n    nb_transpositions = 0; \\\n\\\n    info = LAPACKE_##LAPACKE_PREFIX##getrf( matrix_order, m, n, (LAPACKE_TYPE*)a, lda, ipiv ); \\\n\\\n    for(int i=0;i<m;i++) { ipiv[i]--; if (ipiv[i]!=i) nb_transpositions++; } \\\n\\\n    eigen_assert(info >= 0); \\\n/* something should be done with nb_transpositions */ \\\n\\\n    first_zero_pivot = info; \\\n    return first_zero_pivot; \\\n  } \\\n};\n\nEIGEN_LAPACKE_LU_PARTPIV(double, double, d)\nEIGEN_LAPACKE_LU_PARTPIV(float, float, s)\nEIGEN_LAPACKE_LU_PARTPIV(dcomplex, lapack_complex_double, z)\nEIGEN_LAPACKE_LU_PARTPIV(scomplex, lapack_complex_float,  c)\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_PARTIALLU_LAPACK_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/LU/arch/Inverse_SSE.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2001 Intel Corporation\n// Copyright (C) 2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2009 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n// The SSE code for the 4x4 float and double matrix inverse in this file\n// comes from the following Intel's library:\n// http://software.intel.com/en-us/articles/optimized-matrix-library-for-use-with-the-intel-pentiumr-4-processors-sse2-instructions/\n//\n// Here is the respective copyright and license statement:\n//\n//   Copyright (c) 2001 Intel Corporation.\n//\n// Permition is granted to use, copy, distribute and prepare derivative works\n// of this library for any purpose and without fee, provided, that the above\n// copyright notice and this statement appear in all copies.\n// Intel makes no representations about the suitability of this software for\n// any purpose, and specifically disclaims all warranties.\n// See LEGAL.TXT for all the legal information.\n\n#ifndef EIGEN_INVERSE_SSE_H\n#define EIGEN_INVERSE_SSE_H\n\nnamespace Eigen { \n\nnamespace internal {\n\ntemplate<typename MatrixType, typename ResultType>\nstruct compute_inverse_size4<Architecture::SSE, float, MatrixType, ResultType>\n{\n  enum {\n    MatrixAlignment     = traits<MatrixType>::Alignment,\n    ResultAlignment     = traits<ResultType>::Alignment,\n    StorageOrdersMatch  = (MatrixType::Flags&RowMajorBit) == (ResultType::Flags&RowMajorBit)\n  };\n  typedef typename conditional<(MatrixType::Flags&LinearAccessBit),MatrixType const &,typename MatrixType::PlainObject>::type ActualMatrixType;\n  \n  static void run(const MatrixType& mat, ResultType& result)\n  {\n    ActualMatrixType matrix(mat);\n    EIGEN_ALIGN16 const unsigned int _Sign_PNNP[4] = { 0x00000000, 0x80000000, 0x80000000, 0x00000000 };\n\n    // Load the full matrix into registers\n    __m128 _L1 = matrix.template packet<MatrixAlignment>( 0);\n    __m128 _L2 = matrix.template packet<MatrixAlignment>( 4);\n    __m128 _L3 = matrix.template packet<MatrixAlignment>( 8);\n    __m128 _L4 = matrix.template packet<MatrixAlignment>(12);\n\n    // The inverse is calculated using \"Divide and Conquer\" technique. The\n    // original matrix is divide into four 2x2 sub-matrices. Since each\n    // register holds four matrix element, the smaller matrices are\n    // represented as a registers. Hence we get a better locality of the\n    // calculations.\n\n    __m128 A, B, C, D; // the four sub-matrices\n    if(!StorageOrdersMatch)\n    {\n      A = _mm_unpacklo_ps(_L1, _L2);\n      B = _mm_unpacklo_ps(_L3, _L4);\n      C = _mm_unpackhi_ps(_L1, _L2);\n      D = _mm_unpackhi_ps(_L3, _L4);\n    }\n    else\n    {\n      A = _mm_movelh_ps(_L1, _L2);\n      B = _mm_movehl_ps(_L2, _L1);\n      C = _mm_movelh_ps(_L3, _L4);\n      D = _mm_movehl_ps(_L4, _L3);\n    }\n\n    __m128 iA, iB, iC, iD,                 // partial inverse of the sub-matrices\n            DC, AB;\n    __m128 dA, dB, dC, dD;                 // determinant of the sub-matrices\n    __m128 det, d, d1, d2;\n    __m128 rd;                             // reciprocal of the determinant\n\n    //  AB = A# * B\n    AB = _mm_mul_ps(_mm_shuffle_ps(A,A,0x0F), B);\n    AB = _mm_sub_ps(AB,_mm_mul_ps(_mm_shuffle_ps(A,A,0xA5), _mm_shuffle_ps(B,B,0x4E)));\n    //  DC = D# * C\n    DC = _mm_mul_ps(_mm_shuffle_ps(D,D,0x0F), C);\n    DC = _mm_sub_ps(DC,_mm_mul_ps(_mm_shuffle_ps(D,D,0xA5), _mm_shuffle_ps(C,C,0x4E)));\n\n    //  dA = |A|\n    dA = _mm_mul_ps(_mm_shuffle_ps(A, A, 0x5F),A);\n    dA = _mm_sub_ss(dA, _mm_movehl_ps(dA,dA));\n    //  dB = |B|\n    dB = _mm_mul_ps(_mm_shuffle_ps(B, B, 0x5F),B);\n    dB = _mm_sub_ss(dB, _mm_movehl_ps(dB,dB));\n\n    //  dC = |C|\n    dC = _mm_mul_ps(_mm_shuffle_ps(C, C, 0x5F),C);\n    dC = _mm_sub_ss(dC, _mm_movehl_ps(dC,dC));\n    //  dD = |D|\n    dD = _mm_mul_ps(_mm_shuffle_ps(D, D, 0x5F),D);\n    dD = _mm_sub_ss(dD, _mm_movehl_ps(dD,dD));\n\n    //  d = trace(AB*DC) = trace(A#*B*D#*C)\n    d = _mm_mul_ps(_mm_shuffle_ps(DC,DC,0xD8),AB);\n\n    //  iD = C*A#*B\n    iD = _mm_mul_ps(_mm_shuffle_ps(C,C,0xA0), _mm_movelh_ps(AB,AB));\n    iD = _mm_add_ps(iD,_mm_mul_ps(_mm_shuffle_ps(C,C,0xF5), _mm_movehl_ps(AB,AB)));\n    //  iA = B*D#*C\n    iA = _mm_mul_ps(_mm_shuffle_ps(B,B,0xA0), _mm_movelh_ps(DC,DC));\n    iA = _mm_add_ps(iA,_mm_mul_ps(_mm_shuffle_ps(B,B,0xF5), _mm_movehl_ps(DC,DC)));\n\n    //  d = trace(AB*DC) = trace(A#*B*D#*C) [continue]\n    d  = _mm_add_ps(d, _mm_movehl_ps(d, d));\n    d  = _mm_add_ss(d, _mm_shuffle_ps(d, d, 1));\n    d1 = _mm_mul_ss(dA,dD);\n    d2 = _mm_mul_ss(dB,dC);\n\n    //  iD = D*|A| - C*A#*B\n    iD = _mm_sub_ps(_mm_mul_ps(D,_mm_shuffle_ps(dA,dA,0)), iD);\n\n    //  iA = A*|D| - B*D#*C;\n    iA = _mm_sub_ps(_mm_mul_ps(A,_mm_shuffle_ps(dD,dD,0)), iA);\n\n    //  det = |A|*|D| + |B|*|C| - trace(A#*B*D#*C)\n    det = _mm_sub_ss(_mm_add_ss(d1,d2),d);\n    rd  = _mm_div_ss(_mm_set_ss(1.0f), det);\n\n//     #ifdef ZERO_SINGULAR\n//         rd = _mm_and_ps(_mm_cmpneq_ss(det,_mm_setzero_ps()), rd);\n//     #endif\n\n    //  iB = D * (A#B)# = D*B#*A\n    iB = _mm_mul_ps(D, _mm_shuffle_ps(AB,AB,0x33));\n    iB = _mm_sub_ps(iB, _mm_mul_ps(_mm_shuffle_ps(D,D,0xB1), _mm_shuffle_ps(AB,AB,0x66)));\n    //  iC = A * (D#C)# = A*C#*D\n    iC = _mm_mul_ps(A, _mm_shuffle_ps(DC,DC,0x33));\n    iC = _mm_sub_ps(iC, _mm_mul_ps(_mm_shuffle_ps(A,A,0xB1), _mm_shuffle_ps(DC,DC,0x66)));\n\n    rd = _mm_shuffle_ps(rd,rd,0);\n    rd = _mm_xor_ps(rd, _mm_load_ps((float*)_Sign_PNNP));\n\n    //  iB = C*|B| - D*B#*A\n    iB = _mm_sub_ps(_mm_mul_ps(C,_mm_shuffle_ps(dB,dB,0)), iB);\n\n    //  iC = B*|C| - A*C#*D;\n    iC = _mm_sub_ps(_mm_mul_ps(B,_mm_shuffle_ps(dC,dC,0)), iC);\n\n    //  iX = iX / det\n    iA = _mm_mul_ps(rd,iA);\n    iB = _mm_mul_ps(rd,iB);\n    iC = _mm_mul_ps(rd,iC);\n    iD = _mm_mul_ps(rd,iD);\n\n    Index res_stride = result.outerStride();\n    float* res = result.data();\n    pstoret<float, Packet4f, ResultAlignment>(res+0,            _mm_shuffle_ps(iA,iB,0x77));\n    pstoret<float, Packet4f, ResultAlignment>(res+res_stride,   _mm_shuffle_ps(iA,iB,0x22));\n    pstoret<float, Packet4f, ResultAlignment>(res+2*res_stride, _mm_shuffle_ps(iC,iD,0x77));\n    pstoret<float, Packet4f, ResultAlignment>(res+3*res_stride, _mm_shuffle_ps(iC,iD,0x22));\n  }\n\n};\n\ntemplate<typename MatrixType, typename ResultType>\nstruct compute_inverse_size4<Architecture::SSE, double, MatrixType, ResultType>\n{\n  enum {\n    MatrixAlignment     = traits<MatrixType>::Alignment,\n    ResultAlignment     = traits<ResultType>::Alignment,\n    StorageOrdersMatch  = (MatrixType::Flags&RowMajorBit) == (ResultType::Flags&RowMajorBit)\n  };\n  typedef typename conditional<(MatrixType::Flags&LinearAccessBit),MatrixType const &,typename MatrixType::PlainObject>::type ActualMatrixType;\n  \n  static void run(const MatrixType& mat, ResultType& result)\n  {\n    ActualMatrixType matrix(mat);\n    const __m128d _Sign_NP = _mm_castsi128_pd(_mm_set_epi32(0x0,0x0,0x80000000,0x0));\n    const __m128d _Sign_PN = _mm_castsi128_pd(_mm_set_epi32(0x80000000,0x0,0x0,0x0));\n\n    // The inverse is calculated using \"Divide and Conquer\" technique. The\n    // original matrix is divide into four 2x2 sub-matrices. Since each\n    // register of the matrix holds two elements, the smaller matrices are\n    // consisted of two registers. Hence we get a better locality of the\n    // calculations.\n\n    // the four sub-matrices\n    __m128d A1, A2, B1, B2, C1, C2, D1, D2;\n    \n    if(StorageOrdersMatch)\n    {\n      A1 = matrix.template packet<MatrixAlignment>( 0); B1 = matrix.template packet<MatrixAlignment>( 2);\n      A2 = matrix.template packet<MatrixAlignment>( 4); B2 = matrix.template packet<MatrixAlignment>( 6);\n      C1 = matrix.template packet<MatrixAlignment>( 8); D1 = matrix.template packet<MatrixAlignment>(10);\n      C2 = matrix.template packet<MatrixAlignment>(12); D2 = matrix.template packet<MatrixAlignment>(14);\n    }\n    else\n    {\n      __m128d tmp;\n      A1 = matrix.template packet<MatrixAlignment>( 0); C1 = matrix.template packet<MatrixAlignment>( 2);\n      A2 = matrix.template packet<MatrixAlignment>( 4); C2 = matrix.template packet<MatrixAlignment>( 6);\n      tmp = A1;\n      A1 = _mm_unpacklo_pd(A1,A2);\n      A2 = _mm_unpackhi_pd(tmp,A2);\n      tmp = C1;\n      C1 = _mm_unpacklo_pd(C1,C2);\n      C2 = _mm_unpackhi_pd(tmp,C2);\n      \n      B1 = matrix.template packet<MatrixAlignment>( 8); D1 = matrix.template packet<MatrixAlignment>(10);\n      B2 = matrix.template packet<MatrixAlignment>(12); D2 = matrix.template packet<MatrixAlignment>(14);\n      tmp = B1;\n      B1 = _mm_unpacklo_pd(B1,B2);\n      B2 = _mm_unpackhi_pd(tmp,B2);\n      tmp = D1;\n      D1 = _mm_unpacklo_pd(D1,D2);\n      D2 = _mm_unpackhi_pd(tmp,D2);\n    }\n    \n    __m128d iA1, iA2, iB1, iB2, iC1, iC2, iD1, iD2,     // partial invese of the sub-matrices\n            DC1, DC2, AB1, AB2;\n    __m128d dA, dB, dC, dD;     // determinant of the sub-matrices\n    __m128d det, d1, d2, rd;\n\n    //  dA = |A|\n    dA = _mm_shuffle_pd(A2, A2, 1);\n    dA = _mm_mul_pd(A1, dA);\n    dA = _mm_sub_sd(dA, _mm_shuffle_pd(dA,dA,3));\n    //  dB = |B|\n    dB = _mm_shuffle_pd(B2, B2, 1);\n    dB = _mm_mul_pd(B1, dB);\n    dB = _mm_sub_sd(dB, _mm_shuffle_pd(dB,dB,3));\n\n    //  AB = A# * B\n    AB1 = _mm_mul_pd(B1, _mm_shuffle_pd(A2,A2,3));\n    AB2 = _mm_mul_pd(B2, _mm_shuffle_pd(A1,A1,0));\n    AB1 = _mm_sub_pd(AB1, _mm_mul_pd(B2, _mm_shuffle_pd(A1,A1,3)));\n    AB2 = _mm_sub_pd(AB2, _mm_mul_pd(B1, _mm_shuffle_pd(A2,A2,0)));\n\n    //  dC = |C|\n    dC = _mm_shuffle_pd(C2, C2, 1);\n    dC = _mm_mul_pd(C1, dC);\n    dC = _mm_sub_sd(dC, _mm_shuffle_pd(dC,dC,3));\n    //  dD = |D|\n    dD = _mm_shuffle_pd(D2, D2, 1);\n    dD = _mm_mul_pd(D1, dD);\n    dD = _mm_sub_sd(dD, _mm_shuffle_pd(dD,dD,3));\n\n    //  DC = D# * C\n    DC1 = _mm_mul_pd(C1, _mm_shuffle_pd(D2,D2,3));\n    DC2 = _mm_mul_pd(C2, _mm_shuffle_pd(D1,D1,0));\n    DC1 = _mm_sub_pd(DC1, _mm_mul_pd(C2, _mm_shuffle_pd(D1,D1,3)));\n    DC2 = _mm_sub_pd(DC2, _mm_mul_pd(C1, _mm_shuffle_pd(D2,D2,0)));\n\n    //  rd = trace(AB*DC) = trace(A#*B*D#*C)\n    d1 = _mm_mul_pd(AB1, _mm_shuffle_pd(DC1, DC2, 0));\n    d2 = _mm_mul_pd(AB2, _mm_shuffle_pd(DC1, DC2, 3));\n    rd = _mm_add_pd(d1, d2);\n    rd = _mm_add_sd(rd, _mm_shuffle_pd(rd, rd,3));\n\n    //  iD = C*A#*B\n    iD1 = _mm_mul_pd(AB1, _mm_shuffle_pd(C1,C1,0));\n    iD2 = _mm_mul_pd(AB1, _mm_shuffle_pd(C2,C2,0));\n    iD1 = _mm_add_pd(iD1, _mm_mul_pd(AB2, _mm_shuffle_pd(C1,C1,3)));\n    iD2 = _mm_add_pd(iD2, _mm_mul_pd(AB2, _mm_shuffle_pd(C2,C2,3)));\n\n    //  iA = B*D#*C\n    iA1 = _mm_mul_pd(DC1, _mm_shuffle_pd(B1,B1,0));\n    iA2 = _mm_mul_pd(DC1, _mm_shuffle_pd(B2,B2,0));\n    iA1 = _mm_add_pd(iA1, _mm_mul_pd(DC2, _mm_shuffle_pd(B1,B1,3)));\n    iA2 = _mm_add_pd(iA2, _mm_mul_pd(DC2, _mm_shuffle_pd(B2,B2,3)));\n\n    //  iD = D*|A| - C*A#*B\n    dA = _mm_shuffle_pd(dA,dA,0);\n    iD1 = _mm_sub_pd(_mm_mul_pd(D1, dA), iD1);\n    iD2 = _mm_sub_pd(_mm_mul_pd(D2, dA), iD2);\n\n    //  iA = A*|D| - B*D#*C;\n    dD = _mm_shuffle_pd(dD,dD,0);\n    iA1 = _mm_sub_pd(_mm_mul_pd(A1, dD), iA1);\n    iA2 = _mm_sub_pd(_mm_mul_pd(A2, dD), iA2);\n\n    d1 = _mm_mul_sd(dA, dD);\n    d2 = _mm_mul_sd(dB, dC);\n\n    //  iB = D * (A#B)# = D*B#*A\n    iB1 = _mm_mul_pd(D1, _mm_shuffle_pd(AB2,AB1,1));\n    iB2 = _mm_mul_pd(D2, _mm_shuffle_pd(AB2,AB1,1));\n    iB1 = _mm_sub_pd(iB1, _mm_mul_pd(_mm_shuffle_pd(D1,D1,1), _mm_shuffle_pd(AB2,AB1,2)));\n    iB2 = _mm_sub_pd(iB2, _mm_mul_pd(_mm_shuffle_pd(D2,D2,1), _mm_shuffle_pd(AB2,AB1,2)));\n\n    //  det = |A|*|D| + |B|*|C| - trace(A#*B*D#*C)\n    det = _mm_add_sd(d1, d2);\n    det = _mm_sub_sd(det, rd);\n\n    //  iC = A * (D#C)# = A*C#*D\n    iC1 = _mm_mul_pd(A1, _mm_shuffle_pd(DC2,DC1,1));\n    iC2 = _mm_mul_pd(A2, _mm_shuffle_pd(DC2,DC1,1));\n    iC1 = _mm_sub_pd(iC1, _mm_mul_pd(_mm_shuffle_pd(A1,A1,1), _mm_shuffle_pd(DC2,DC1,2)));\n    iC2 = _mm_sub_pd(iC2, _mm_mul_pd(_mm_shuffle_pd(A2,A2,1), _mm_shuffle_pd(DC2,DC1,2)));\n\n    rd = _mm_div_sd(_mm_set_sd(1.0), det);\n//     #ifdef ZERO_SINGULAR\n//         rd = _mm_and_pd(_mm_cmpneq_sd(det,_mm_setzero_pd()), rd);\n//     #endif\n    rd = _mm_shuffle_pd(rd,rd,0);\n\n    //  iB = C*|B| - D*B#*A\n    dB = _mm_shuffle_pd(dB,dB,0);\n    iB1 = _mm_sub_pd(_mm_mul_pd(C1, dB), iB1);\n    iB2 = _mm_sub_pd(_mm_mul_pd(C2, dB), iB2);\n\n    d1 = _mm_xor_pd(rd, _Sign_PN);\n    d2 = _mm_xor_pd(rd, _Sign_NP);\n\n    //  iC = B*|C| - A*C#*D;\n    dC = _mm_shuffle_pd(dC,dC,0);\n    iC1 = _mm_sub_pd(_mm_mul_pd(B1, dC), iC1);\n    iC2 = _mm_sub_pd(_mm_mul_pd(B2, dC), iC2);\n\n    Index res_stride = result.outerStride();\n    double* res = result.data();\n    pstoret<double, Packet2d, ResultAlignment>(res+0,             _mm_mul_pd(_mm_shuffle_pd(iA2, iA1, 3), d1));\n    pstoret<double, Packet2d, ResultAlignment>(res+res_stride,    _mm_mul_pd(_mm_shuffle_pd(iA2, iA1, 0), d2));\n    pstoret<double, Packet2d, ResultAlignment>(res+2,             _mm_mul_pd(_mm_shuffle_pd(iB2, iB1, 3), d1));\n    pstoret<double, Packet2d, ResultAlignment>(res+res_stride+2,  _mm_mul_pd(_mm_shuffle_pd(iB2, iB1, 0), d2));\n    pstoret<double, Packet2d, ResultAlignment>(res+2*res_stride,  _mm_mul_pd(_mm_shuffle_pd(iC2, iC1, 3), d1));\n    pstoret<double, Packet2d, ResultAlignment>(res+3*res_stride,  _mm_mul_pd(_mm_shuffle_pd(iC2, iC1, 0), d2));\n    pstoret<double, Packet2d, ResultAlignment>(res+2*res_stride+2,_mm_mul_pd(_mm_shuffle_pd(iD2, iD1, 3), d1));\n    pstoret<double, Packet2d, ResultAlignment>(res+3*res_stride+2,_mm_mul_pd(_mm_shuffle_pd(iD2, iD1, 0), d2));\n  }\n};\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_INVERSE_SSE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/MetisSupport/MetisSupport.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2012 Désiré Nuentsa-Wakam <desire.nuentsa_wakam@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n#ifndef METIS_SUPPORT_H\n#define METIS_SUPPORT_H\n\nnamespace Eigen {\n/**\n * Get the fill-reducing ordering from the METIS package\n * \n * If A is the original matrix and Ap is the permuted matrix, \n * the fill-reducing permutation is defined as follows :\n * Row (column) i of A is the matperm(i) row (column) of Ap. \n * WARNING: As computed by METIS, this corresponds to the vector iperm (instead of perm)\n */\ntemplate <typename StorageIndex>\nclass MetisOrdering\n{\npublic:\n  typedef PermutationMatrix<Dynamic,Dynamic,StorageIndex> PermutationType;\n  typedef Matrix<StorageIndex,Dynamic,1> IndexVector; \n  \n  template <typename MatrixType>\n  void get_symmetrized_graph(const MatrixType& A)\n  {\n    Index m = A.cols(); \n    eigen_assert((A.rows() == A.cols()) && \"ONLY FOR SQUARED MATRICES\");\n    // Get the transpose of the input matrix \n    MatrixType At = A.transpose(); \n    // Get the number of nonzeros elements in each row/col of At+A\n    Index TotNz = 0; \n    IndexVector visited(m); \n    visited.setConstant(-1); \n    for (StorageIndex j = 0; j < m; j++)\n    {\n      // Compute the union structure of of A(j,:) and At(j,:)\n      visited(j) = j; // Do not include the diagonal element\n      // Get the nonzeros in row/column j of A\n      for (typename MatrixType::InnerIterator it(A, j); it; ++it)\n      {\n        Index idx = it.index(); // Get the row index (for column major) or column index (for row major)\n        if (visited(idx) != j ) \n        {\n          visited(idx) = j; \n          ++TotNz; \n        }\n      }\n      //Get the nonzeros in row/column j of At\n      for (typename MatrixType::InnerIterator it(At, j); it; ++it)\n      {\n        Index idx = it.index(); \n        if(visited(idx) != j)\n        {\n          visited(idx) = j; \n          ++TotNz; \n        }\n      }\n    }\n    // Reserve place for A + At\n    m_indexPtr.resize(m+1);\n    m_innerIndices.resize(TotNz); \n\n    // Now compute the real adjacency list of each column/row \n    visited.setConstant(-1); \n    StorageIndex CurNz = 0; \n    for (StorageIndex j = 0; j < m; j++)\n    {\n      m_indexPtr(j) = CurNz; \n      \n      visited(j) = j; // Do not include the diagonal element\n      // Add the pattern of row/column j of A to A+At\n      for (typename MatrixType::InnerIterator it(A,j); it; ++it)\n      {\n        StorageIndex idx = it.index(); // Get the row index (for column major) or column index (for row major)\n        if (visited(idx) != j ) \n        {\n          visited(idx) = j; \n          m_innerIndices(CurNz) = idx; \n          CurNz++; \n        }\n      }\n      //Add the pattern of row/column j of At to A+At\n      for (typename MatrixType::InnerIterator it(At, j); it; ++it)\n      {\n        StorageIndex idx = it.index(); \n        if(visited(idx) != j)\n        {\n          visited(idx) = j; \n          m_innerIndices(CurNz) = idx; \n          ++CurNz; \n        }\n      }\n    }\n    m_indexPtr(m) = CurNz;    \n  }\n  \n  template <typename MatrixType>\n  void operator() (const MatrixType& A, PermutationType& matperm)\n  {\n     StorageIndex m = internal::convert_index<StorageIndex>(A.cols()); // must be StorageIndex, because it is passed by address to METIS\n     IndexVector perm(m),iperm(m); \n    // First, symmetrize the matrix graph. \n     get_symmetrized_graph(A); \n     int output_error;\n     \n     // Call the fill-reducing routine from METIS \n     output_error = METIS_NodeND(&m, m_indexPtr.data(), m_innerIndices.data(), NULL, NULL, perm.data(), iperm.data());\n     \n    if(output_error != METIS_OK) \n    {\n      //FIXME The ordering interface should define a class of possible errors \n     std::cerr << \"ERROR WHILE CALLING THE METIS PACKAGE \\n\"; \n     return; \n    }\n    \n    // Get the fill-reducing permutation \n    //NOTE:  If Ap is the permuted matrix then perm and iperm vectors are defined as follows \n    // Row (column) i of Ap is the perm(i) row(column) of A, and row (column) i of A is the iperm(i) row(column) of Ap\n    \n     matperm.resize(m);\n     for (int j = 0; j < m; j++)\n       matperm.indices()(iperm(j)) = j;\n   \n  }\n  \n  protected:\n    IndexVector m_indexPtr; // Pointer to the adjacenccy list of each row/column\n    IndexVector m_innerIndices; // Adjacency list \n};\n\n}// end namespace eigen \n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/OrderingMethods/Amd.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n\n/*\n\nNOTE: this routine has been adapted from the CSparse library:\n\nCopyright (c) 2006, Timothy A. Davis.\nhttp://www.suitesparse.com\n\nCSparse is free software; you can redistribute it and/or\nmodify it under the terms of the GNU Lesser General Public\nLicense as published by the Free Software Foundation; either\nversion 2.1 of the License, or (at your option) any later version.\n\nCSparse is distributed in the hope that it will be useful,\nbut WITHOUT ANY WARRANTY; without even the implied warranty of\nMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\nLesser General Public License for more details.\n\nYou should have received a copy of the GNU Lesser General Public\nLicense along with this Module; if not, write to the Free Software\nFoundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n\n*/\n\n#include \"../Core/util/NonMPL2.h\"\n\n#ifndef EIGEN_SPARSE_AMD_H\n#define EIGEN_SPARSE_AMD_H\n\nnamespace Eigen { \n\nnamespace internal {\n  \ntemplate<typename T> inline T amd_flip(const T& i) { return -i-2; }\ntemplate<typename T> inline T amd_unflip(const T& i) { return i<0 ? amd_flip(i) : i; }\ntemplate<typename T0, typename T1> inline bool amd_marked(const T0* w, const T1& j) { return w[j]<0; }\ntemplate<typename T0, typename T1> inline void amd_mark(const T0* w, const T1& j) { return w[j] = amd_flip(w[j]); }\n\n/* clear w */\ntemplate<typename StorageIndex>\nstatic StorageIndex cs_wclear (StorageIndex mark, StorageIndex lemax, StorageIndex *w, StorageIndex n)\n{\n  StorageIndex k;\n  if(mark < 2 || (mark + lemax < 0))\n  {\n    for(k = 0; k < n; k++)\n      if(w[k] != 0)\n        w[k] = 1;\n    mark = 2;\n  }\n  return (mark);     /* at this point, w[0..n-1] < mark holds */\n}\n\n/* depth-first search and postorder of a tree rooted at node j */\ntemplate<typename StorageIndex>\nStorageIndex cs_tdfs(StorageIndex j, StorageIndex k, StorageIndex *head, const StorageIndex *next, StorageIndex *post, StorageIndex *stack)\n{\n  StorageIndex i, p, top = 0;\n  if(!head || !next || !post || !stack) return (-1);    /* check inputs */\n  stack[0] = j;                 /* place j on the stack */\n  while (top >= 0)                /* while (stack is not empty) */\n  {\n    p = stack[top];           /* p = top of stack */\n    i = head[p];              /* i = youngest child of p */\n    if(i == -1)\n    {\n      top--;                 /* p has no unordered children left */\n      post[k++] = p;        /* node p is the kth postordered node */\n    }\n    else\n    {\n      head[p] = next[i];   /* remove i from children of p */\n      stack[++top] = i;     /* start dfs on child node i */\n    }\n  }\n  return k;\n}\n\n\n/** \\internal\n  * \\ingroup OrderingMethods_Module \n  * Approximate minimum degree ordering algorithm.\n  *\n  * \\param[in] C the input selfadjoint matrix stored in compressed column major format.\n  * \\param[out] perm the permutation P reducing the fill-in of the input matrix \\a C\n  *\n  * Note that the input matrix \\a C must be complete, that is both the upper and lower parts have to be stored, as well as the diagonal entries.\n  * On exit the values of C are destroyed */\ntemplate<typename Scalar, typename StorageIndex>\nvoid minimum_degree_ordering(SparseMatrix<Scalar,ColMajor,StorageIndex>& C, PermutationMatrix<Dynamic,Dynamic,StorageIndex>& perm)\n{\n  using std::sqrt;\n  \n  StorageIndex d, dk, dext, lemax = 0, e, elenk, eln, i, j, k, k1,\n                k2, k3, jlast, ln, dense, nzmax, mindeg = 0, nvi, nvj, nvk, mark, wnvi,\n                ok, nel = 0, p, p1, p2, p3, p4, pj, pk, pk1, pk2, pn, q, t, h;\n  \n  StorageIndex n = StorageIndex(C.cols());\n  dense = std::max<StorageIndex> (16, StorageIndex(10 * sqrt(double(n))));   /* find dense threshold */\n  dense = (std::min)(n-2, dense);\n  \n  StorageIndex cnz = StorageIndex(C.nonZeros());\n  perm.resize(n+1);\n  t = cnz + cnz/5 + 2*n;                 /* add elbow room to C */\n  C.resizeNonZeros(t);\n  \n  // get workspace\n  ei_declare_aligned_stack_constructed_variable(StorageIndex,W,8*(n+1),0);\n  StorageIndex* len     = W;\n  StorageIndex* nv      = W +   (n+1);\n  StorageIndex* next    = W + 2*(n+1);\n  StorageIndex* head    = W + 3*(n+1);\n  StorageIndex* elen    = W + 4*(n+1);\n  StorageIndex* degree  = W + 5*(n+1);\n  StorageIndex* w       = W + 6*(n+1);\n  StorageIndex* hhead   = W + 7*(n+1);\n  StorageIndex* last    = perm.indices().data();                              /* use P as workspace for last */\n  \n  /* --- Initialize quotient graph ---------------------------------------- */\n  StorageIndex* Cp = C.outerIndexPtr();\n  StorageIndex* Ci = C.innerIndexPtr();\n  for(k = 0; k < n; k++)\n    len[k] = Cp[k+1] - Cp[k];\n  len[n] = 0;\n  nzmax = t;\n  \n  for(i = 0; i <= n; i++)\n  {\n    head[i]   = -1;                     // degree list i is empty\n    last[i]   = -1;\n    next[i]   = -1;\n    hhead[i]  = -1;                     // hash list i is empty \n    nv[i]     = 1;                      // node i is just one node\n    w[i]      = 1;                      // node i is alive\n    elen[i]   = 0;                      // Ek of node i is empty\n    degree[i] = len[i];                 // degree of node i\n  }\n  mark = internal::cs_wclear<StorageIndex>(0, 0, w, n);         /* clear w */\n  \n  /* --- Initialize degree lists ------------------------------------------ */\n  for(i = 0; i < n; i++)\n  {\n    bool has_diag = false;\n    for(p = Cp[i]; p<Cp[i+1]; ++p)\n      if(Ci[p]==i)\n      {\n        has_diag = true;\n        break;\n      }\n   \n    d = degree[i];\n    if(d == 1 && has_diag)           /* node i is empty */\n    {\n      elen[i] = -2;                 /* element i is dead */\n      nel++;\n      Cp[i] = -1;                   /* i is a root of assembly tree */\n      w[i] = 0;\n    }\n    else if(d > dense || !has_diag)  /* node i is dense or has no structural diagonal element */\n    {\n      nv[i] = 0;                    /* absorb i into element n */\n      elen[i] = -1;                 /* node i is dead */\n      nel++;\n      Cp[i] = amd_flip (n);\n      nv[n]++;\n    }\n    else\n    {\n      if(head[d] != -1) last[head[d]] = i;\n      next[i] = head[d];           /* put node i in degree list d */\n      head[d] = i;\n    }\n  }\n  \n  elen[n] = -2;                         /* n is a dead element */\n  Cp[n] = -1;                           /* n is a root of assembly tree */\n  w[n] = 0;                             /* n is a dead element */\n  \n  while (nel < n)                         /* while (selecting pivots) do */\n  {\n    /* --- Select node of minimum approximate degree -------------------- */\n    for(k = -1; mindeg < n && (k = head[mindeg]) == -1; mindeg++) {}\n    if(next[k] != -1) last[next[k]] = -1;\n    head[mindeg] = next[k];          /* remove k from degree list */\n    elenk = elen[k];                  /* elenk = |Ek| */\n    nvk = nv[k];                      /* # of nodes k represents */\n    nel += nvk;                        /* nv[k] nodes of A eliminated */\n    \n    /* --- Garbage collection ------------------------------------------- */\n    if(elenk > 0 && cnz + mindeg >= nzmax)\n    {\n      for(j = 0; j < n; j++)\n      {\n        if((p = Cp[j]) >= 0)      /* j is a live node or element */\n        {\n          Cp[j] = Ci[p];          /* save first entry of object */\n          Ci[p] = amd_flip (j);    /* first entry is now amd_flip(j) */\n        }\n      }\n      for(q = 0, p = 0; p < cnz; ) /* scan all of memory */\n      {\n        if((j = amd_flip (Ci[p++])) >= 0)  /* found object j */\n        {\n          Ci[q] = Cp[j];       /* restore first entry of object */\n          Cp[j] = q++;          /* new pointer to object j */\n          for(k3 = 0; k3 < len[j]-1; k3++) Ci[q++] = Ci[p++];\n        }\n      }\n      cnz = q;                       /* Ci[cnz...nzmax-1] now free */\n    }\n    \n    /* --- Construct new element ---------------------------------------- */\n    dk = 0;\n    nv[k] = -nvk;                     /* flag k as in Lk */\n    p = Cp[k];\n    pk1 = (elenk == 0) ? p : cnz;      /* do in place if elen[k] == 0 */\n    pk2 = pk1;\n    for(k1 = 1; k1 <= elenk + 1; k1++)\n    {\n      if(k1 > elenk)\n      {\n        e = k;                     /* search the nodes in k */\n        pj = p;                    /* list of nodes starts at Ci[pj]*/\n        ln = len[k] - elenk;      /* length of list of nodes in k */\n      }\n      else\n      {\n        e = Ci[p++];              /* search the nodes in e */\n        pj = Cp[e];\n        ln = len[e];              /* length of list of nodes in e */\n      }\n      for(k2 = 1; k2 <= ln; k2++)\n      {\n        i = Ci[pj++];\n        if((nvi = nv[i]) <= 0) continue; /* node i dead, or seen */\n        dk += nvi;                 /* degree[Lk] += size of node i */\n        nv[i] = -nvi;             /* negate nv[i] to denote i in Lk*/\n        Ci[pk2++] = i;            /* place i in Lk */\n        if(next[i] != -1) last[next[i]] = last[i];\n        if(last[i] != -1)         /* remove i from degree list */\n        {\n          next[last[i]] = next[i];\n        }\n        else\n        {\n          head[degree[i]] = next[i];\n        }\n      }\n      if(e != k)\n      {\n        Cp[e] = amd_flip (k);      /* absorb e into k */\n        w[e] = 0;                 /* e is now a dead element */\n      }\n    }\n    if(elenk != 0) cnz = pk2;         /* Ci[cnz...nzmax] is free */\n    degree[k] = dk;                   /* external degree of k - |Lk\\i| */\n    Cp[k] = pk1;                      /* element k is in Ci[pk1..pk2-1] */\n    len[k] = pk2 - pk1;\n    elen[k] = -2;                     /* k is now an element */\n    \n    /* --- Find set differences ----------------------------------------- */\n    mark = internal::cs_wclear<StorageIndex>(mark, lemax, w, n);  /* clear w if necessary */\n    for(pk = pk1; pk < pk2; pk++)    /* scan 1: find |Le\\Lk| */\n    {\n      i = Ci[pk];\n      if((eln = elen[i]) <= 0) continue;/* skip if elen[i] empty */\n      nvi = -nv[i];                      /* nv[i] was negated */\n      wnvi = mark - nvi;\n      for(p = Cp[i]; p <= Cp[i] + eln - 1; p++)  /* scan Ei */\n      {\n        e = Ci[p];\n        if(w[e] >= mark)\n        {\n          w[e] -= nvi;          /* decrement |Le\\Lk| */\n        }\n        else if(w[e] != 0)        /* ensure e is a live element */\n        {\n          w[e] = degree[e] + wnvi; /* 1st time e seen in scan 1 */\n        }\n      }\n    }\n    \n    /* --- Degree update ------------------------------------------------ */\n    for(pk = pk1; pk < pk2; pk++)    /* scan2: degree update */\n    {\n      i = Ci[pk];                   /* consider node i in Lk */\n      p1 = Cp[i];\n      p2 = p1 + elen[i] - 1;\n      pn = p1;\n      for(h = 0, d = 0, p = p1; p <= p2; p++)    /* scan Ei */\n      {\n        e = Ci[p];\n        if(w[e] != 0)             /* e is an unabsorbed element */\n        {\n          dext = w[e] - mark;   /* dext = |Le\\Lk| */\n          if(dext > 0)\n          {\n            d += dext;         /* sum up the set differences */\n            Ci[pn++] = e;     /* keep e in Ei */\n            h += e;            /* compute the hash of node i */\n          }\n          else\n          {\n            Cp[e] = amd_flip (k);  /* aggressive absorb. e->k */\n            w[e] = 0;             /* e is a dead element */\n          }\n        }\n      }\n      elen[i] = pn - p1 + 1;        /* elen[i] = |Ei| */\n      p3 = pn;\n      p4 = p1 + len[i];\n      for(p = p2 + 1; p < p4; p++) /* prune edges in Ai */\n      {\n        j = Ci[p];\n        if((nvj = nv[j]) <= 0) continue; /* node j dead or in Lk */\n        d += nvj;                  /* degree(i) += |j| */\n        Ci[pn++] = j;             /* place j in node list of i */\n        h += j;                    /* compute hash for node i */\n      }\n      if(d == 0)                     /* check for mass elimination */\n      {\n        Cp[i] = amd_flip (k);      /* absorb i into k */\n        nvi = -nv[i];\n        dk -= nvi;                 /* |Lk| -= |i| */\n        nvk += nvi;                /* |k| += nv[i] */\n        nel += nvi;\n        nv[i] = 0;\n        elen[i] = -1;             /* node i is dead */\n      }\n      else\n      {\n        degree[i] = std::min<StorageIndex> (degree[i], d);   /* update degree(i) */\n        Ci[pn] = Ci[p3];         /* move first node to end */\n        Ci[p3] = Ci[p1];         /* move 1st el. to end of Ei */\n        Ci[p1] = k;               /* add k as 1st element in of Ei */\n        len[i] = pn - p1 + 1;     /* new len of adj. list of node i */\n        h %= n;                    /* finalize hash of i */\n        next[i] = hhead[h];      /* place i in hash bucket */\n        hhead[h] = i;\n        last[i] = h;      /* save hash of i in last[i] */\n      }\n    }                                   /* scan2 is done */\n    degree[k] = dk;                   /* finalize |Lk| */\n    lemax = std::max<StorageIndex>(lemax, dk);\n    mark = internal::cs_wclear<StorageIndex>(mark+lemax, lemax, w, n);    /* clear w */\n    \n    /* --- Supernode detection ------------------------------------------ */\n    for(pk = pk1; pk < pk2; pk++)\n    {\n      i = Ci[pk];\n      if(nv[i] >= 0) continue;         /* skip if i is dead */\n      h = last[i];                      /* scan hash bucket of node i */\n      i = hhead[h];\n      hhead[h] = -1;                    /* hash bucket will be empty */\n      for(; i != -1 && next[i] != -1; i = next[i], mark++)\n      {\n        ln = len[i];\n        eln = elen[i];\n        for(p = Cp[i]+1; p <= Cp[i] + ln-1; p++) w[Ci[p]] = mark;\n        jlast = i;\n        for(j = next[i]; j != -1; ) /* compare i with all j */\n        {\n          ok = (len[j] == ln) && (elen[j] == eln);\n          for(p = Cp[j] + 1; ok && p <= Cp[j] + ln - 1; p++)\n          {\n            if(w[Ci[p]] != mark) ok = 0;    /* compare i and j*/\n          }\n          if(ok)                     /* i and j are identical */\n          {\n            Cp[j] = amd_flip (i);  /* absorb j into i */\n            nv[i] += nv[j];\n            nv[j] = 0;\n            elen[j] = -1;         /* node j is dead */\n            j = next[j];          /* delete j from hash bucket */\n            next[jlast] = j;\n          }\n          else\n          {\n            jlast = j;             /* j and i are different */\n            j = next[j];\n          }\n        }\n      }\n    }\n    \n    /* --- Finalize new element------------------------------------------ */\n    for(p = pk1, pk = pk1; pk < pk2; pk++)   /* finalize Lk */\n    {\n      i = Ci[pk];\n      if((nvi = -nv[i]) <= 0) continue;/* skip if i is dead */\n      nv[i] = nvi;                      /* restore nv[i] */\n      d = degree[i] + dk - nvi;         /* compute external degree(i) */\n      d = std::min<StorageIndex> (d, n - nel - nvi);\n      if(head[d] != -1) last[head[d]] = i;\n      next[i] = head[d];               /* put i back in degree list */\n      last[i] = -1;\n      head[d] = i;\n      mindeg = std::min<StorageIndex> (mindeg, d);       /* find new minimum degree */\n      degree[i] = d;\n      Ci[p++] = i;                      /* place i in Lk */\n    }\n    nv[k] = nvk;                      /* # nodes absorbed into k */\n    if((len[k] = p-pk1) == 0)         /* length of adj list of element k*/\n    {\n      Cp[k] = -1;                   /* k is a root of the tree */\n      w[k] = 0;                     /* k is now a dead element */\n    }\n    if(elenk != 0) cnz = p;           /* free unused space in Lk */\n  }\n  \n  /* --- Postordering ----------------------------------------------------- */\n  for(i = 0; i < n; i++) Cp[i] = amd_flip (Cp[i]);/* fix assembly tree */\n  for(j = 0; j <= n; j++) head[j] = -1;\n  for(j = n; j >= 0; j--)              /* place unordered nodes in lists */\n  {\n    if(nv[j] > 0) continue;          /* skip if j is an element */\n    next[j] = head[Cp[j]];          /* place j in list of its parent */\n    head[Cp[j]] = j;\n  }\n  for(e = n; e >= 0; e--)              /* place elements in lists */\n  {\n    if(nv[e] <= 0) continue;         /* skip unless e is an element */\n    if(Cp[e] != -1)\n    {\n      next[e] = head[Cp[e]];      /* place e in list of its parent */\n      head[Cp[e]] = e;\n    }\n  }\n  for(k = 0, i = 0; i <= n; i++)       /* postorder the assembly tree */\n  {\n    if(Cp[i] == -1) k = internal::cs_tdfs<StorageIndex>(i, k, head, next, perm.indices().data(), w);\n  }\n  \n  perm.indices().conservativeResize(n);\n}\n\n} // namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_SPARSE_AMD_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/OrderingMethods/Eigen_Colamd.h",
    "content": "// // This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2012 Desire Nuentsa Wakam <desire.nuentsa_wakam@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n// This file is modified from the colamd/symamd library. The copyright is below\n\n//   The authors of the code itself are Stefan I. Larimore and Timothy A.\n//   Davis (davis@cise.ufl.edu), University of Florida.  The algorithm was\n//   developed in collaboration with John Gilbert, Xerox PARC, and Esmond\n//   Ng, Oak Ridge National Laboratory.\n// \n//     Date:\n// \n//   September 8, 2003.  Version 2.3.\n// \n//     Acknowledgements:\n// \n//   This work was supported by the National Science Foundation, under\n//   grants DMS-9504974 and DMS-9803599.\n// \n//     Notice:\n// \n//   Copyright (c) 1998-2003 by the University of Florida.\n//   All Rights Reserved.\n// \n//   THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY\n//   EXPRESSED OR IMPLIED.  ANY USE IS AT YOUR OWN RISK.\n// \n//   Permission is hereby granted to use, copy, modify, and/or distribute\n//   this program, provided that the Copyright, this License, and the\n//   Availability of the original version is retained on all copies and made\n//   accessible to the end-user of any code or package that includes COLAMD\n//   or any modified version of COLAMD. \n// \n//     Availability:\n// \n//   The colamd/symamd library is available at\n// \n//       http://www.suitesparse.com\n\n  \n#ifndef EIGEN_COLAMD_H\n#define EIGEN_COLAMD_H\n\nnamespace internal {\n/* Ensure that debugging is turned off: */\n#ifndef COLAMD_NDEBUG\n#define COLAMD_NDEBUG\n#endif /* NDEBUG */\n/* ========================================================================== */\n/* === Knob and statistics definitions ====================================== */\n/* ========================================================================== */\n\n/* size of the knobs [ ] array.  Only knobs [0..1] are currently used. */\n#define COLAMD_KNOBS 20\n\n/* number of output statistics.  Only stats [0..6] are currently used. */\n#define COLAMD_STATS 20 \n\n/* knobs [0] and stats [0]: dense row knob and output statistic. */\n#define COLAMD_DENSE_ROW 0\n\n/* knobs [1] and stats [1]: dense column knob and output statistic. */\n#define COLAMD_DENSE_COL 1\n\n/* stats [2]: memory defragmentation count output statistic */\n#define COLAMD_DEFRAG_COUNT 2\n\n/* stats [3]: colamd status:  zero OK, > 0 warning or notice, < 0 error */\n#define COLAMD_STATUS 3\n\n/* stats [4..6]: error info, or info on jumbled columns */ \n#define COLAMD_INFO1 4\n#define COLAMD_INFO2 5\n#define COLAMD_INFO3 6\n\n/* error codes returned in stats [3]: */\n#define COLAMD_OK       (0)\n#define COLAMD_OK_BUT_JUMBLED     (1)\n#define COLAMD_ERROR_A_not_present    (-1)\n#define COLAMD_ERROR_p_not_present    (-2)\n#define COLAMD_ERROR_nrow_negative    (-3)\n#define COLAMD_ERROR_ncol_negative    (-4)\n#define COLAMD_ERROR_nnz_negative   (-5)\n#define COLAMD_ERROR_p0_nonzero     (-6)\n#define COLAMD_ERROR_A_too_small    (-7)\n#define COLAMD_ERROR_col_length_negative  (-8)\n#define COLAMD_ERROR_row_index_out_of_bounds  (-9)\n#define COLAMD_ERROR_out_of_memory    (-10)\n#define COLAMD_ERROR_internal_error   (-999)\n\n/* ========================================================================== */\n/* === Definitions ========================================================== */\n/* ========================================================================== */\n\n#define ONES_COMPLEMENT(r) (-(r)-1)\n\n/* -------------------------------------------------------------------------- */\n\n#define COLAMD_EMPTY (-1)\n\n/* Row and column status */\n#define ALIVE (0)\n#define DEAD  (-1)\n\n/* Column status */\n#define DEAD_PRINCIPAL    (-1)\n#define DEAD_NON_PRINCIPAL  (-2)\n\n/* Macros for row and column status update and checking. */\n#define ROW_IS_DEAD(r)      ROW_IS_MARKED_DEAD (Row[r].shared2.mark)\n#define ROW_IS_MARKED_DEAD(row_mark)  (row_mark < ALIVE)\n#define ROW_IS_ALIVE(r)     (Row [r].shared2.mark >= ALIVE)\n#define COL_IS_DEAD(c)      (Col [c].start < ALIVE)\n#define COL_IS_ALIVE(c)     (Col [c].start >= ALIVE)\n#define COL_IS_DEAD_PRINCIPAL(c)  (Col [c].start == DEAD_PRINCIPAL)\n#define KILL_ROW(r)     { Row [r].shared2.mark = DEAD ; }\n#define KILL_PRINCIPAL_COL(c)   { Col [c].start = DEAD_PRINCIPAL ; }\n#define KILL_NON_PRINCIPAL_COL(c) { Col [c].start = DEAD_NON_PRINCIPAL ; }\n\n/* ========================================================================== */\n/* === Colamd reporting mechanism =========================================== */\n/* ========================================================================== */\n\n// == Row and Column structures ==\ntemplate <typename IndexType>\nstruct colamd_col\n{\n  IndexType start ;   /* index for A of first row in this column, or DEAD */\n  /* if column is dead */\n  IndexType length ;  /* number of rows in this column */\n  union\n  {\n    IndexType thickness ; /* number of original columns represented by this */\n    /* col, if the column is alive */\n    IndexType parent ;  /* parent in parent tree super-column structure, if */\n    /* the column is dead */\n  } shared1 ;\n  union\n  {\n    IndexType score ; /* the score used to maintain heap, if col is alive */\n    IndexType order ; /* pivot ordering of this column, if col is dead */\n  } shared2 ;\n  union\n  {\n    IndexType headhash ;  /* head of a hash bucket, if col is at the head of */\n    /* a degree list */\n    IndexType hash ;  /* hash value, if col is not in a degree list */\n    IndexType prev ;  /* previous column in degree list, if col is in a */\n    /* degree list (but not at the head of a degree list) */\n  } shared3 ;\n  union\n  {\n    IndexType degree_next ; /* next column, if col is in a degree list */\n    IndexType hash_next ;   /* next column, if col is in a hash list */\n  } shared4 ;\n  \n};\n \ntemplate <typename IndexType>\nstruct Colamd_Row\n{\n  IndexType start ;   /* index for A of first col in this row */\n  IndexType length ;  /* number of principal columns in this row */\n  union\n  {\n    IndexType degree ;  /* number of principal & non-principal columns in row */\n    IndexType p ;   /* used as a row pointer in init_rows_cols () */\n  } shared1 ;\n  union\n  {\n    IndexType mark ;  /* for computing set differences and marking dead rows*/\n    IndexType first_column ;/* first column in row (used in garbage collection) */\n  } shared2 ;\n  \n};\n \n/* ========================================================================== */\n/* === Colamd recommended memory size ======================================= */\n/* ========================================================================== */\n \n/*\n  The recommended length Alen of the array A passed to colamd is given by\n  the COLAMD_RECOMMENDED (nnz, n_row, n_col) macro.  It returns -1 if any\n  argument is negative.  2*nnz space is required for the row and column\n  indices of the matrix. colamd_c (n_col) + colamd_r (n_row) space is\n  required for the Col and Row arrays, respectively, which are internal to\n  colamd.  An additional n_col space is the minimal amount of \"elbow room\",\n  and nnz/5 more space is recommended for run time efficiency.\n  \n  This macro is not needed when using symamd.\n  \n  Explicit typecast to IndexType added Sept. 23, 2002, COLAMD version 2.2, to avoid\n  gcc -pedantic warning messages.\n*/\ntemplate <typename IndexType>\ninline IndexType colamd_c(IndexType n_col) \n{ return IndexType( ((n_col) + 1) * sizeof (colamd_col<IndexType>) / sizeof (IndexType) ) ; }\n\ntemplate <typename IndexType>\ninline IndexType  colamd_r(IndexType n_row)\n{ return IndexType(((n_row) + 1) * sizeof (Colamd_Row<IndexType>) / sizeof (IndexType)); }\n\n// Prototypes of non-user callable routines\ntemplate <typename IndexType>\nstatic IndexType init_rows_cols (IndexType n_row, IndexType n_col, Colamd_Row<IndexType> Row [], colamd_col<IndexType> col [], IndexType A [], IndexType p [], IndexType stats[COLAMD_STATS] ); \n\ntemplate <typename IndexType>\nstatic void init_scoring (IndexType n_row, IndexType n_col, Colamd_Row<IndexType> Row [], colamd_col<IndexType> Col [], IndexType A [], IndexType head [], double knobs[COLAMD_KNOBS], IndexType *p_n_row2, IndexType *p_n_col2, IndexType *p_max_deg);\n\ntemplate <typename IndexType>\nstatic IndexType find_ordering (IndexType n_row, IndexType n_col, IndexType Alen, Colamd_Row<IndexType> Row [], colamd_col<IndexType> Col [], IndexType A [], IndexType head [], IndexType n_col2, IndexType max_deg, IndexType pfree);\n\ntemplate <typename IndexType>\nstatic void order_children (IndexType n_col, colamd_col<IndexType> Col [], IndexType p []);\n\ntemplate <typename IndexType>\nstatic void detect_super_cols (colamd_col<IndexType> Col [], IndexType A [], IndexType head [], IndexType row_start, IndexType row_length ) ;\n\ntemplate <typename IndexType>\nstatic IndexType garbage_collection (IndexType n_row, IndexType n_col, Colamd_Row<IndexType> Row [], colamd_col<IndexType> Col [], IndexType A [], IndexType *pfree) ;\n\ntemplate <typename IndexType>\nstatic inline  IndexType clear_mark (IndexType n_row, Colamd_Row<IndexType> Row [] ) ;\n\n/* === No debugging ========================================================= */\n\n#define COLAMD_DEBUG0(params) ;\n#define COLAMD_DEBUG1(params) ;\n#define COLAMD_DEBUG2(params) ;\n#define COLAMD_DEBUG3(params) ;\n#define COLAMD_DEBUG4(params) ;\n\n#define COLAMD_ASSERT(expression) ((void) 0)\n\n\n/**\n * \\brief Returns the recommended value of Alen \n * \n * Returns recommended value of Alen for use by colamd.  \n * Returns -1 if any input argument is negative.  \n * The use of this routine or macro is optional.  \n * Note that the macro uses its arguments   more than once, \n * so be careful for side effects, if you pass expressions as arguments to COLAMD_RECOMMENDED.  \n * \n * \\param nnz nonzeros in A\n * \\param n_row number of rows in A\n * \\param n_col number of columns in A\n * \\return recommended value of Alen for use by colamd\n */\ntemplate <typename IndexType>\ninline IndexType colamd_recommended ( IndexType nnz, IndexType n_row, IndexType n_col)\n{\n  if ((nnz) < 0 || (n_row) < 0 || (n_col) < 0)\n    return (-1);\n  else\n    return (2 * (nnz) + colamd_c (n_col) + colamd_r (n_row) + (n_col) + ((nnz) / 5)); \n}\n\n/**\n * \\brief set default parameters  The use of this routine is optional.\n * \n * Colamd: rows with more than (knobs [COLAMD_DENSE_ROW] * n_col)\n * entries are removed prior to ordering.  Columns with more than\n * (knobs [COLAMD_DENSE_COL] * n_row) entries are removed prior to\n * ordering, and placed last in the output column ordering. \n *\n * COLAMD_DENSE_ROW and COLAMD_DENSE_COL are defined as 0 and 1,\n * respectively, in colamd.h.  Default values of these two knobs\n * are both 0.5.  Currently, only knobs [0] and knobs [1] are\n * used, but future versions may use more knobs.  If so, they will\n * be properly set to their defaults by the future version of\n * colamd_set_defaults, so that the code that calls colamd will\n * not need to change, assuming that you either use\n * colamd_set_defaults, or pass a (double *) NULL pointer as the\n * knobs array to colamd or symamd.\n * \n * \\param knobs parameter settings for colamd\n */\n\nstatic inline void colamd_set_defaults(double knobs[COLAMD_KNOBS])\n{\n  /* === Local variables ================================================== */\n  \n  int i ;\n\n  if (!knobs)\n  {\n    return ;      /* no knobs to initialize */\n  }\n  for (i = 0 ; i < COLAMD_KNOBS ; i++)\n  {\n    knobs [i] = 0 ;\n  }\n  knobs [COLAMD_DENSE_ROW] = 0.5 ;  /* ignore rows over 50% dense */\n  knobs [COLAMD_DENSE_COL] = 0.5 ;  /* ignore columns over 50% dense */\n}\n\n/** \n * \\brief  Computes a column ordering using the column approximate minimum degree ordering\n * \n * Computes a column ordering (Q) of A such that P(AQ)=LU or\n * (AQ)'AQ=LL' have less fill-in and require fewer floating point\n * operations than factorizing the unpermuted matrix A or A'A,\n * respectively.\n * \n * \n * \\param n_row number of rows in A\n * \\param n_col number of columns in A\n * \\param Alen, size of the array A\n * \\param A row indices of the matrix, of size ALen\n * \\param p column pointers of A, of size n_col+1\n * \\param knobs parameter settings for colamd\n * \\param stats colamd output statistics and error codes\n */\ntemplate <typename IndexType>\nstatic bool colamd(IndexType n_row, IndexType n_col, IndexType Alen, IndexType *A, IndexType *p, double knobs[COLAMD_KNOBS], IndexType stats[COLAMD_STATS])\n{\n  /* === Local variables ================================================== */\n  \n  IndexType i ;     /* loop index */\n  IndexType nnz ;     /* nonzeros in A */\n  IndexType Row_size ;    /* size of Row [], in integers */\n  IndexType Col_size ;    /* size of Col [], in integers */\n  IndexType need ;      /* minimum required length of A */\n  Colamd_Row<IndexType> *Row ;   /* pointer into A of Row [0..n_row] array */\n  colamd_col<IndexType> *Col ;   /* pointer into A of Col [0..n_col] array */\n  IndexType n_col2 ;    /* number of non-dense, non-empty columns */\n  IndexType n_row2 ;    /* number of non-dense, non-empty rows */\n  IndexType ngarbage ;    /* number of garbage collections performed */\n  IndexType max_deg ;   /* maximum row degree */\n  double default_knobs [COLAMD_KNOBS] ; /* default knobs array */\n  \n  \n  /* === Check the input arguments ======================================== */\n  \n  if (!stats)\n  {\n    COLAMD_DEBUG0 ((\"colamd: stats not present\\n\")) ;\n    return (false) ;\n  }\n  for (i = 0 ; i < COLAMD_STATS ; i++)\n  {\n    stats [i] = 0 ;\n  }\n  stats [COLAMD_STATUS] = COLAMD_OK ;\n  stats [COLAMD_INFO1] = -1 ;\n  stats [COLAMD_INFO2] = -1 ;\n  \n  if (!A)   /* A is not present */\n  {\n    stats [COLAMD_STATUS] = COLAMD_ERROR_A_not_present ;\n    COLAMD_DEBUG0 ((\"colamd: A not present\\n\")) ;\n    return (false) ;\n  }\n  \n  if (!p)   /* p is not present */\n  {\n    stats [COLAMD_STATUS] = COLAMD_ERROR_p_not_present ;\n    COLAMD_DEBUG0 ((\"colamd: p not present\\n\")) ;\n    return (false) ;\n  }\n  \n  if (n_row < 0)  /* n_row must be >= 0 */\n  {\n    stats [COLAMD_STATUS] = COLAMD_ERROR_nrow_negative ;\n    stats [COLAMD_INFO1] = n_row ;\n    COLAMD_DEBUG0 ((\"colamd: nrow negative %d\\n\", n_row)) ;\n    return (false) ;\n  }\n  \n  if (n_col < 0)  /* n_col must be >= 0 */\n  {\n    stats [COLAMD_STATUS] = COLAMD_ERROR_ncol_negative ;\n    stats [COLAMD_INFO1] = n_col ;\n    COLAMD_DEBUG0 ((\"colamd: ncol negative %d\\n\", n_col)) ;\n    return (false) ;\n  }\n  \n  nnz = p [n_col] ;\n  if (nnz < 0)  /* nnz must be >= 0 */\n  {\n    stats [COLAMD_STATUS] = COLAMD_ERROR_nnz_negative ;\n    stats [COLAMD_INFO1] = nnz ;\n    COLAMD_DEBUG0 ((\"colamd: number of entries negative %d\\n\", nnz)) ;\n    return (false) ;\n  }\n  \n  if (p [0] != 0)\n  {\n    stats [COLAMD_STATUS] = COLAMD_ERROR_p0_nonzero ;\n    stats [COLAMD_INFO1] = p [0] ;\n    COLAMD_DEBUG0 ((\"colamd: p[0] not zero %d\\n\", p [0])) ;\n    return (false) ;\n  }\n  \n  /* === If no knobs, set default knobs =================================== */\n  \n  if (!knobs)\n  {\n    colamd_set_defaults (default_knobs) ;\n    knobs = default_knobs ;\n  }\n  \n  /* === Allocate the Row and Col arrays from array A ===================== */\n  \n  Col_size = colamd_c (n_col) ;\n  Row_size = colamd_r (n_row) ;\n  need = 2*nnz + n_col + Col_size + Row_size ;\n  \n  if (need > Alen)\n  {\n    /* not enough space in array A to perform the ordering */\n    stats [COLAMD_STATUS] = COLAMD_ERROR_A_too_small ;\n    stats [COLAMD_INFO1] = need ;\n    stats [COLAMD_INFO2] = Alen ;\n    COLAMD_DEBUG0 ((\"colamd: Need Alen >= %d, given only Alen = %d\\n\", need,Alen));\n    return (false) ;\n  }\n  \n  Alen -= Col_size + Row_size ;\n  Col = (colamd_col<IndexType> *) &A [Alen] ;\n  Row = (Colamd_Row<IndexType> *) &A [Alen + Col_size] ;\n\n  /* === Construct the row and column data structures ===================== */\n  \n  if (!Eigen::internal::init_rows_cols (n_row, n_col, Row, Col, A, p, stats))\n  {\n    /* input matrix is invalid */\n    COLAMD_DEBUG0 ((\"colamd: Matrix invalid\\n\")) ;\n    return (false) ;\n  }\n  \n  /* === Initialize scores, kill dense rows/columns ======================= */\n\n  Eigen::internal::init_scoring (n_row, n_col, Row, Col, A, p, knobs,\n\t\t&n_row2, &n_col2, &max_deg) ;\n  \n  /* === Order the supercolumns =========================================== */\n  \n  ngarbage = Eigen::internal::find_ordering (n_row, n_col, Alen, Row, Col, A, p,\n\t\t\t    n_col2, max_deg, 2*nnz) ;\n  \n  /* === Order the non-principal columns ================================== */\n  \n  Eigen::internal::order_children (n_col, Col, p) ;\n  \n  /* === Return statistics in stats ======================================= */\n  \n  stats [COLAMD_DENSE_ROW] = n_row - n_row2 ;\n  stats [COLAMD_DENSE_COL] = n_col - n_col2 ;\n  stats [COLAMD_DEFRAG_COUNT] = ngarbage ;\n  COLAMD_DEBUG0 ((\"colamd: done.\\n\")) ; \n  return (true) ;\n}\n\n/* ========================================================================== */\n/* === NON-USER-CALLABLE ROUTINES: ========================================== */\n/* ========================================================================== */\n\n/* There are no user-callable routines beyond this point in the file */\n\n\n/* ========================================================================== */\n/* === init_rows_cols ======================================================= */\n/* ========================================================================== */\n\n/*\n  Takes the column form of the matrix in A and creates the row form of the\n  matrix.  Also, row and column attributes are stored in the Col and Row\n  structs.  If the columns are un-sorted or contain duplicate row indices,\n  this routine will also sort and remove duplicate row indices from the\n  column form of the matrix.  Returns false if the matrix is invalid,\n  true otherwise.  Not user-callable.\n*/\ntemplate <typename IndexType>\nstatic IndexType init_rows_cols  /* returns true if OK, or false otherwise */\n  (\n    /* === Parameters ======================================================= */\n\n    IndexType n_row,      /* number of rows of A */\n    IndexType n_col,      /* number of columns of A */\n    Colamd_Row<IndexType> Row [],    /* of size n_row+1 */\n    colamd_col<IndexType> Col [],    /* of size n_col+1 */\n    IndexType A [],     /* row indices of A, of size Alen */\n    IndexType p [],     /* pointers to columns in A, of size n_col+1 */\n    IndexType stats [COLAMD_STATS]  /* colamd statistics */ \n    )\n{\n  /* === Local variables ================================================== */\n\n  IndexType col ;     /* a column index */\n  IndexType row ;     /* a row index */\n  IndexType *cp ;     /* a column pointer */\n  IndexType *cp_end ;   /* a pointer to the end of a column */\n  IndexType *rp ;     /* a row pointer */\n  IndexType *rp_end ;   /* a pointer to the end of a row */\n  IndexType last_row ;    /* previous row */\n\n  /* === Initialize columns, and check column pointers ==================== */\n\n  for (col = 0 ; col < n_col ; col++)\n  {\n    Col [col].start = p [col] ;\n    Col [col].length = p [col+1] - p [col] ;\n\n    if ((Col [col].length) < 0) // extra parentheses to work-around gcc bug 10200\n    {\n      /* column pointers must be non-decreasing */\n      stats [COLAMD_STATUS] = COLAMD_ERROR_col_length_negative ;\n      stats [COLAMD_INFO1] = col ;\n      stats [COLAMD_INFO2] = Col [col].length ;\n      COLAMD_DEBUG0 ((\"colamd: col %d length %d < 0\\n\", col, Col [col].length)) ;\n      return (false) ;\n    }\n\n    Col [col].shared1.thickness = 1 ;\n    Col [col].shared2.score = 0 ;\n    Col [col].shared3.prev = COLAMD_EMPTY ;\n    Col [col].shared4.degree_next = COLAMD_EMPTY ;\n  }\n\n  /* p [0..n_col] no longer needed, used as \"head\" in subsequent routines */\n\n  /* === Scan columns, compute row degrees, and check row indices ========= */\n\n  stats [COLAMD_INFO3] = 0 ;  /* number of duplicate or unsorted row indices*/\n\n  for (row = 0 ; row < n_row ; row++)\n  {\n    Row [row].length = 0 ;\n    Row [row].shared2.mark = -1 ;\n  }\n\n  for (col = 0 ; col < n_col ; col++)\n  {\n    last_row = -1 ;\n\n    cp = &A [p [col]] ;\n    cp_end = &A [p [col+1]] ;\n\n    while (cp < cp_end)\n    {\n      row = *cp++ ;\n\n      /* make sure row indices within range */\n      if (row < 0 || row >= n_row)\n      {\n\tstats [COLAMD_STATUS] = COLAMD_ERROR_row_index_out_of_bounds ;\n\tstats [COLAMD_INFO1] = col ;\n\tstats [COLAMD_INFO2] = row ;\n\tstats [COLAMD_INFO3] = n_row ;\n\tCOLAMD_DEBUG0 ((\"colamd: row %d col %d out of bounds\\n\", row, col)) ;\n\treturn (false) ;\n      }\n\n      if (row <= last_row || Row [row].shared2.mark == col)\n      {\n\t/* row index are unsorted or repeated (or both), thus col */\n\t/* is jumbled.  This is a notice, not an error condition. */\n\tstats [COLAMD_STATUS] = COLAMD_OK_BUT_JUMBLED ;\n\tstats [COLAMD_INFO1] = col ;\n\tstats [COLAMD_INFO2] = row ;\n\t(stats [COLAMD_INFO3]) ++ ;\n\tCOLAMD_DEBUG1 ((\"colamd: row %d col %d unsorted/duplicate\\n\",row,col));\n      }\n\n      if (Row [row].shared2.mark != col)\n      {\n\tRow [row].length++ ;\n      }\n      else\n      {\n\t/* this is a repeated entry in the column, */\n\t/* it will be removed */\n\tCol [col].length-- ;\n      }\n\n      /* mark the row as having been seen in this column */\n      Row [row].shared2.mark = col ;\n\n      last_row = row ;\n    }\n  }\n\n  /* === Compute row pointers ============================================= */\n\n  /* row form of the matrix starts directly after the column */\n  /* form of matrix in A */\n  Row [0].start = p [n_col] ;\n  Row [0].shared1.p = Row [0].start ;\n  Row [0].shared2.mark = -1 ;\n  for (row = 1 ; row < n_row ; row++)\n  {\n    Row [row].start = Row [row-1].start + Row [row-1].length ;\n    Row [row].shared1.p = Row [row].start ;\n    Row [row].shared2.mark = -1 ;\n  }\n\n  /* === Create row form ================================================== */\n\n  if (stats [COLAMD_STATUS] == COLAMD_OK_BUT_JUMBLED)\n  {\n    /* if cols jumbled, watch for repeated row indices */\n    for (col = 0 ; col < n_col ; col++)\n    {\n      cp = &A [p [col]] ;\n      cp_end = &A [p [col+1]] ;\n      while (cp < cp_end)\n      {\n\trow = *cp++ ;\n\tif (Row [row].shared2.mark != col)\n\t{\n\t  A [(Row [row].shared1.p)++] = col ;\n\t  Row [row].shared2.mark = col ;\n\t}\n      }\n    }\n  }\n  else\n  {\n    /* if cols not jumbled, we don't need the mark (this is faster) */\n    for (col = 0 ; col < n_col ; col++)\n    {\n      cp = &A [p [col]] ;\n      cp_end = &A [p [col+1]] ;\n      while (cp < cp_end)\n      {\n\tA [(Row [*cp++].shared1.p)++] = col ;\n      }\n    }\n  }\n\n  /* === Clear the row marks and set row degrees ========================== */\n\n  for (row = 0 ; row < n_row ; row++)\n  {\n    Row [row].shared2.mark = 0 ;\n    Row [row].shared1.degree = Row [row].length ;\n  }\n\n  /* === See if we need to re-create columns ============================== */\n\n  if (stats [COLAMD_STATUS] == COLAMD_OK_BUT_JUMBLED)\n  {\n    COLAMD_DEBUG0 ((\"colamd: reconstructing column form, matrix jumbled\\n\")) ;\n\n\n    /* === Compute col pointers ========================================= */\n\n    /* col form of the matrix starts at A [0]. */\n    /* Note, we may have a gap between the col form and the row */\n    /* form if there were duplicate entries, if so, it will be */\n    /* removed upon the first garbage collection */\n    Col [0].start = 0 ;\n    p [0] = Col [0].start ;\n    for (col = 1 ; col < n_col ; col++)\n    {\n      /* note that the lengths here are for pruned columns, i.e. */\n      /* no duplicate row indices will exist for these columns */\n      Col [col].start = Col [col-1].start + Col [col-1].length ;\n      p [col] = Col [col].start ;\n    }\n\n    /* === Re-create col form =========================================== */\n\n    for (row = 0 ; row < n_row ; row++)\n    {\n      rp = &A [Row [row].start] ;\n      rp_end = rp + Row [row].length ;\n      while (rp < rp_end)\n      {\n\tA [(p [*rp++])++] = row ;\n      }\n    }\n  }\n\n  /* === Done.  Matrix is not (or no longer) jumbled ====================== */\n\n  return (true) ;\n}\n\n\n/* ========================================================================== */\n/* === init_scoring ========================================================= */\n/* ========================================================================== */\n\n/*\n  Kills dense or empty columns and rows, calculates an initial score for\n  each column, and places all columns in the degree lists.  Not user-callable.\n*/\ntemplate <typename IndexType>\nstatic void init_scoring\n  (\n    /* === Parameters ======================================================= */\n\n    IndexType n_row,      /* number of rows of A */\n    IndexType n_col,      /* number of columns of A */\n    Colamd_Row<IndexType> Row [],    /* of size n_row+1 */\n    colamd_col<IndexType> Col [],    /* of size n_col+1 */\n    IndexType A [],     /* column form and row form of A */\n    IndexType head [],    /* of size n_col+1 */\n    double knobs [COLAMD_KNOBS],/* parameters */\n    IndexType *p_n_row2,    /* number of non-dense, non-empty rows */\n    IndexType *p_n_col2,    /* number of non-dense, non-empty columns */\n    IndexType *p_max_deg    /* maximum row degree */\n    )\n{\n  /* === Local variables ================================================== */\n\n  IndexType c ;     /* a column index */\n  IndexType r, row ;    /* a row index */\n  IndexType *cp ;     /* a column pointer */\n  IndexType deg ;     /* degree of a row or column */\n  IndexType *cp_end ;   /* a pointer to the end of a column */\n  IndexType *new_cp ;   /* new column pointer */\n  IndexType col_length ;    /* length of pruned column */\n  IndexType score ;     /* current column score */\n  IndexType n_col2 ;    /* number of non-dense, non-empty columns */\n  IndexType n_row2 ;    /* number of non-dense, non-empty rows */\n  IndexType dense_row_count ; /* remove rows with more entries than this */\n  IndexType dense_col_count ; /* remove cols with more entries than this */\n  IndexType min_score ;   /* smallest column score */\n  IndexType max_deg ;   /* maximum row degree */\n  IndexType next_col ;    /* Used to add to degree list.*/\n\n\n  /* === Extract knobs ==================================================== */\n\n  dense_row_count = numext::maxi(IndexType(0), numext::mini(IndexType(knobs [COLAMD_DENSE_ROW] * n_col), n_col)) ;\n  dense_col_count = numext::maxi(IndexType(0), numext::mini(IndexType(knobs [COLAMD_DENSE_COL] * n_row), n_row)) ;\n  COLAMD_DEBUG1 ((\"colamd: densecount: %d %d\\n\", dense_row_count, dense_col_count)) ;\n  max_deg = 0 ;\n  n_col2 = n_col ;\n  n_row2 = n_row ;\n\n  /* === Kill empty columns =============================================== */\n\n  /* Put the empty columns at the end in their natural order, so that LU */\n  /* factorization can proceed as far as possible. */\n  for (c = n_col-1 ; c >= 0 ; c--)\n  {\n    deg = Col [c].length ;\n    if (deg == 0)\n    {\n      /* this is a empty column, kill and order it last */\n      Col [c].shared2.order = --n_col2 ;\n      KILL_PRINCIPAL_COL (c) ;\n    }\n  }\n  COLAMD_DEBUG1 ((\"colamd: null columns killed: %d\\n\", n_col - n_col2)) ;\n\n  /* === Kill dense columns =============================================== */\n\n  /* Put the dense columns at the end, in their natural order */\n  for (c = n_col-1 ; c >= 0 ; c--)\n  {\n    /* skip any dead columns */\n    if (COL_IS_DEAD (c))\n    {\n      continue ;\n    }\n    deg = Col [c].length ;\n    if (deg > dense_col_count)\n    {\n      /* this is a dense column, kill and order it last */\n      Col [c].shared2.order = --n_col2 ;\n      /* decrement the row degrees */\n      cp = &A [Col [c].start] ;\n      cp_end = cp + Col [c].length ;\n      while (cp < cp_end)\n      {\n\tRow [*cp++].shared1.degree-- ;\n      }\n      KILL_PRINCIPAL_COL (c) ;\n    }\n  }\n  COLAMD_DEBUG1 ((\"colamd: Dense and null columns killed: %d\\n\", n_col - n_col2)) ;\n\n  /* === Kill dense and empty rows ======================================== */\n\n  for (r = 0 ; r < n_row ; r++)\n  {\n    deg = Row [r].shared1.degree ;\n    COLAMD_ASSERT (deg >= 0 && deg <= n_col) ;\n    if (deg > dense_row_count || deg == 0)\n    {\n      /* kill a dense or empty row */\n      KILL_ROW (r) ;\n      --n_row2 ;\n    }\n    else\n    {\n      /* keep track of max degree of remaining rows */\n      max_deg = numext::maxi(max_deg, deg) ;\n    }\n  }\n  COLAMD_DEBUG1 ((\"colamd: Dense and null rows killed: %d\\n\", n_row - n_row2)) ;\n\n  /* === Compute initial column scores ==================================== */\n\n  /* At this point the row degrees are accurate.  They reflect the number */\n  /* of \"live\" (non-dense) columns in each row.  No empty rows exist. */\n  /* Some \"live\" columns may contain only dead rows, however.  These are */\n  /* pruned in the code below. */\n\n  /* now find the initial matlab score for each column */\n  for (c = n_col-1 ; c >= 0 ; c--)\n  {\n    /* skip dead column */\n    if (COL_IS_DEAD (c))\n    {\n      continue ;\n    }\n    score = 0 ;\n    cp = &A [Col [c].start] ;\n    new_cp = cp ;\n    cp_end = cp + Col [c].length ;\n    while (cp < cp_end)\n    {\n      /* get a row */\n      row = *cp++ ;\n      /* skip if dead */\n      if (ROW_IS_DEAD (row))\n      {\n\tcontinue ;\n      }\n      /* compact the column */\n      *new_cp++ = row ;\n      /* add row's external degree */\n      score += Row [row].shared1.degree - 1 ;\n      /* guard against integer overflow */\n      score = numext::mini(score, n_col) ;\n    }\n    /* determine pruned column length */\n    col_length = (IndexType) (new_cp - &A [Col [c].start]) ;\n    if (col_length == 0)\n    {\n      /* a newly-made null column (all rows in this col are \"dense\" */\n      /* and have already been killed) */\n      COLAMD_DEBUG2 ((\"Newly null killed: %d\\n\", c)) ;\n      Col [c].shared2.order = --n_col2 ;\n      KILL_PRINCIPAL_COL (c) ;\n    }\n    else\n    {\n      /* set column length and set score */\n      COLAMD_ASSERT (score >= 0) ;\n      COLAMD_ASSERT (score <= n_col) ;\n      Col [c].length = col_length ;\n      Col [c].shared2.score = score ;\n    }\n  }\n  COLAMD_DEBUG1 ((\"colamd: Dense, null, and newly-null columns killed: %d\\n\",\n\t\t  n_col-n_col2)) ;\n\n  /* At this point, all empty rows and columns are dead.  All live columns */\n  /* are \"clean\" (containing no dead rows) and simplicial (no supercolumns */\n  /* yet).  Rows may contain dead columns, but all live rows contain at */\n  /* least one live column. */\n\n  /* === Initialize degree lists ========================================== */\n\n\n  /* clear the hash buckets */\n  for (c = 0 ; c <= n_col ; c++)\n  {\n    head [c] = COLAMD_EMPTY ;\n  }\n  min_score = n_col ;\n  /* place in reverse order, so low column indices are at the front */\n  /* of the lists.  This is to encourage natural tie-breaking */\n  for (c = n_col-1 ; c >= 0 ; c--)\n  {\n    /* only add principal columns to degree lists */\n    if (COL_IS_ALIVE (c))\n    {\n      COLAMD_DEBUG4 ((\"place %d score %d minscore %d ncol %d\\n\",\n\t\t      c, Col [c].shared2.score, min_score, n_col)) ;\n\n      /* === Add columns score to DList =============================== */\n\n      score = Col [c].shared2.score ;\n\n      COLAMD_ASSERT (min_score >= 0) ;\n      COLAMD_ASSERT (min_score <= n_col) ;\n      COLAMD_ASSERT (score >= 0) ;\n      COLAMD_ASSERT (score <= n_col) ;\n      COLAMD_ASSERT (head [score] >= COLAMD_EMPTY) ;\n\n      /* now add this column to dList at proper score location */\n      next_col = head [score] ;\n      Col [c].shared3.prev = COLAMD_EMPTY ;\n      Col [c].shared4.degree_next = next_col ;\n\n      /* if there already was a column with the same score, set its */\n      /* previous pointer to this new column */\n      if (next_col != COLAMD_EMPTY)\n      {\n\tCol [next_col].shared3.prev = c ;\n      }\n      head [score] = c ;\n\n      /* see if this score is less than current min */\n      min_score = numext::mini(min_score, score) ;\n\n\n    }\n  }\n\n\n  /* === Return number of remaining columns, and max row degree =========== */\n\n  *p_n_col2 = n_col2 ;\n  *p_n_row2 = n_row2 ;\n  *p_max_deg = max_deg ;\n}\n\n\n/* ========================================================================== */\n/* === find_ordering ======================================================== */\n/* ========================================================================== */\n\n/*\n  Order the principal columns of the supercolumn form of the matrix\n  (no supercolumns on input).  Uses a minimum approximate column minimum\n  degree ordering method.  Not user-callable.\n*/\ntemplate <typename IndexType>\nstatic IndexType find_ordering /* return the number of garbage collections */\n  (\n    /* === Parameters ======================================================= */\n\n    IndexType n_row,      /* number of rows of A */\n    IndexType n_col,      /* number of columns of A */\n    IndexType Alen,     /* size of A, 2*nnz + n_col or larger */\n    Colamd_Row<IndexType> Row [],    /* of size n_row+1 */\n    colamd_col<IndexType> Col [],    /* of size n_col+1 */\n    IndexType A [],     /* column form and row form of A */\n    IndexType head [],    /* of size n_col+1 */\n    IndexType n_col2,     /* Remaining columns to order */\n    IndexType max_deg,    /* Maximum row degree */\n    IndexType pfree     /* index of first free slot (2*nnz on entry) */\n    )\n{\n  /* === Local variables ================================================== */\n\n  IndexType k ;     /* current pivot ordering step */\n  IndexType pivot_col ;   /* current pivot column */\n  IndexType *cp ;     /* a column pointer */\n  IndexType *rp ;     /* a row pointer */\n  IndexType pivot_row ;   /* current pivot row */\n  IndexType *new_cp ;   /* modified column pointer */\n  IndexType *new_rp ;   /* modified row pointer */\n  IndexType pivot_row_start ; /* pointer to start of pivot row */\n  IndexType pivot_row_degree ;  /* number of columns in pivot row */\n  IndexType pivot_row_length ;  /* number of supercolumns in pivot row */\n  IndexType pivot_col_score ; /* score of pivot column */\n  IndexType needed_memory ;   /* free space needed for pivot row */\n  IndexType *cp_end ;   /* pointer to the end of a column */\n  IndexType *rp_end ;   /* pointer to the end of a row */\n  IndexType row ;     /* a row index */\n  IndexType col ;     /* a column index */\n  IndexType max_score ;   /* maximum possible score */\n  IndexType cur_score ;   /* score of current column */\n  unsigned int hash ;   /* hash value for supernode detection */\n  IndexType head_column ;   /* head of hash bucket */\n  IndexType first_col ;   /* first column in hash bucket */\n  IndexType tag_mark ;    /* marker value for mark array */\n  IndexType row_mark ;    /* Row [row].shared2.mark */\n  IndexType set_difference ;  /* set difference size of row with pivot row */\n  IndexType min_score ;   /* smallest column score */\n  IndexType col_thickness ;   /* \"thickness\" (no. of columns in a supercol) */\n  IndexType max_mark ;    /* maximum value of tag_mark */\n  IndexType pivot_col_thickness ; /* number of columns represented by pivot col */\n  IndexType prev_col ;    /* Used by Dlist operations. */\n  IndexType next_col ;    /* Used by Dlist operations. */\n  IndexType ngarbage ;    /* number of garbage collections performed */\n\n\n  /* === Initialization and clear mark ==================================== */\n\n  max_mark = INT_MAX - n_col ;  /* INT_MAX defined in <limits.h> */\n  tag_mark = Eigen::internal::clear_mark (n_row, Row) ;\n  min_score = 0 ;\n  ngarbage = 0 ;\n  COLAMD_DEBUG1 ((\"colamd: Ordering, n_col2=%d\\n\", n_col2)) ;\n\n  /* === Order the columns ================================================ */\n\n  for (k = 0 ; k < n_col2 ; /* 'k' is incremented below */)\n  {\n\n    /* === Select pivot column, and order it ============================ */\n\n    /* make sure degree list isn't empty */\n    COLAMD_ASSERT (min_score >= 0) ;\n    COLAMD_ASSERT (min_score <= n_col) ;\n    COLAMD_ASSERT (head [min_score] >= COLAMD_EMPTY) ;\n\n    /* get pivot column from head of minimum degree list */\n    while (head [min_score] == COLAMD_EMPTY && min_score < n_col)\n    {\n      min_score++ ;\n    }\n    pivot_col = head [min_score] ;\n    COLAMD_ASSERT (pivot_col >= 0 && pivot_col <= n_col) ;\n    next_col = Col [pivot_col].shared4.degree_next ;\n    head [min_score] = next_col ;\n    if (next_col != COLAMD_EMPTY)\n    {\n      Col [next_col].shared3.prev = COLAMD_EMPTY ;\n    }\n\n    COLAMD_ASSERT (COL_IS_ALIVE (pivot_col)) ;\n    COLAMD_DEBUG3 ((\"Pivot col: %d\\n\", pivot_col)) ;\n\n    /* remember score for defrag check */\n    pivot_col_score = Col [pivot_col].shared2.score ;\n\n    /* the pivot column is the kth column in the pivot order */\n    Col [pivot_col].shared2.order = k ;\n\n    /* increment order count by column thickness */\n    pivot_col_thickness = Col [pivot_col].shared1.thickness ;\n    k += pivot_col_thickness ;\n    COLAMD_ASSERT (pivot_col_thickness > 0) ;\n\n    /* === Garbage_collection, if necessary ============================= */\n\n    needed_memory = numext::mini(pivot_col_score, n_col - k) ;\n    if (pfree + needed_memory >= Alen)\n    {\n      pfree = Eigen::internal::garbage_collection (n_row, n_col, Row, Col, A, &A [pfree]) ;\n      ngarbage++ ;\n      /* after garbage collection we will have enough */\n      COLAMD_ASSERT (pfree + needed_memory < Alen) ;\n      /* garbage collection has wiped out the Row[].shared2.mark array */\n      tag_mark = Eigen::internal::clear_mark (n_row, Row) ;\n\n    }\n\n    /* === Compute pivot row pattern ==================================== */\n\n    /* get starting location for this new merged row */\n    pivot_row_start = pfree ;\n\n    /* initialize new row counts to zero */\n    pivot_row_degree = 0 ;\n\n    /* tag pivot column as having been visited so it isn't included */\n    /* in merged pivot row */\n    Col [pivot_col].shared1.thickness = -pivot_col_thickness ;\n\n    /* pivot row is the union of all rows in the pivot column pattern */\n    cp = &A [Col [pivot_col].start] ;\n    cp_end = cp + Col [pivot_col].length ;\n    while (cp < cp_end)\n    {\n      /* get a row */\n      row = *cp++ ;\n      COLAMD_DEBUG4 ((\"Pivot col pattern %d %d\\n\", ROW_IS_ALIVE (row), row)) ;\n      /* skip if row is dead */\n      if (ROW_IS_DEAD (row))\n      {\n\tcontinue ;\n      }\n      rp = &A [Row [row].start] ;\n      rp_end = rp + Row [row].length ;\n      while (rp < rp_end)\n      {\n\t/* get a column */\n\tcol = *rp++ ;\n\t/* add the column, if alive and untagged */\n\tcol_thickness = Col [col].shared1.thickness ;\n\tif (col_thickness > 0 && COL_IS_ALIVE (col))\n\t{\n\t  /* tag column in pivot row */\n\t  Col [col].shared1.thickness = -col_thickness ;\n\t  COLAMD_ASSERT (pfree < Alen) ;\n\t  /* place column in pivot row */\n\t  A [pfree++] = col ;\n\t  pivot_row_degree += col_thickness ;\n\t}\n      }\n    }\n\n    /* clear tag on pivot column */\n    Col [pivot_col].shared1.thickness = pivot_col_thickness ;\n    max_deg = numext::maxi(max_deg, pivot_row_degree) ;\n\n\n    /* === Kill all rows used to construct pivot row ==================== */\n\n    /* also kill pivot row, temporarily */\n    cp = &A [Col [pivot_col].start] ;\n    cp_end = cp + Col [pivot_col].length ;\n    while (cp < cp_end)\n    {\n      /* may be killing an already dead row */\n      row = *cp++ ;\n      COLAMD_DEBUG3 ((\"Kill row in pivot col: %d\\n\", row)) ;\n      KILL_ROW (row) ;\n    }\n\n    /* === Select a row index to use as the new pivot row =============== */\n\n    pivot_row_length = pfree - pivot_row_start ;\n    if (pivot_row_length > 0)\n    {\n      /* pick the \"pivot\" row arbitrarily (first row in col) */\n      pivot_row = A [Col [pivot_col].start] ;\n      COLAMD_DEBUG3 ((\"Pivotal row is %d\\n\", pivot_row)) ;\n    }\n    else\n    {\n      /* there is no pivot row, since it is of zero length */\n      pivot_row = COLAMD_EMPTY ;\n      COLAMD_ASSERT (pivot_row_length == 0) ;\n    }\n    COLAMD_ASSERT (Col [pivot_col].length > 0 || pivot_row_length == 0) ;\n\n    /* === Approximate degree computation =============================== */\n\n    /* Here begins the computation of the approximate degree.  The column */\n    /* score is the sum of the pivot row \"length\", plus the size of the */\n    /* set differences of each row in the column minus the pattern of the */\n    /* pivot row itself.  The column (\"thickness\") itself is also */\n    /* excluded from the column score (we thus use an approximate */\n    /* external degree). */\n\n    /* The time taken by the following code (compute set differences, and */\n    /* add them up) is proportional to the size of the data structure */\n    /* being scanned - that is, the sum of the sizes of each column in */\n    /* the pivot row.  Thus, the amortized time to compute a column score */\n    /* is proportional to the size of that column (where size, in this */\n    /* context, is the column \"length\", or the number of row indices */\n    /* in that column).  The number of row indices in a column is */\n    /* monotonically non-decreasing, from the length of the original */\n    /* column on input to colamd. */\n\n    /* === Compute set differences ====================================== */\n\n    COLAMD_DEBUG3 ((\"** Computing set differences phase. **\\n\")) ;\n\n    /* pivot row is currently dead - it will be revived later. */\n\n    COLAMD_DEBUG3 ((\"Pivot row: \")) ;\n    /* for each column in pivot row */\n    rp = &A [pivot_row_start] ;\n    rp_end = rp + pivot_row_length ;\n    while (rp < rp_end)\n    {\n      col = *rp++ ;\n      COLAMD_ASSERT (COL_IS_ALIVE (col) && col != pivot_col) ;\n      COLAMD_DEBUG3 ((\"Col: %d\\n\", col)) ;\n\n      /* clear tags used to construct pivot row pattern */\n      col_thickness = -Col [col].shared1.thickness ;\n      COLAMD_ASSERT (col_thickness > 0) ;\n      Col [col].shared1.thickness = col_thickness ;\n\n      /* === Remove column from degree list =========================== */\n\n      cur_score = Col [col].shared2.score ;\n      prev_col = Col [col].shared3.prev ;\n      next_col = Col [col].shared4.degree_next ;\n      COLAMD_ASSERT (cur_score >= 0) ;\n      COLAMD_ASSERT (cur_score <= n_col) ;\n      COLAMD_ASSERT (cur_score >= COLAMD_EMPTY) ;\n      if (prev_col == COLAMD_EMPTY)\n      {\n\thead [cur_score] = next_col ;\n      }\n      else\n      {\n\tCol [prev_col].shared4.degree_next = next_col ;\n      }\n      if (next_col != COLAMD_EMPTY)\n      {\n\tCol [next_col].shared3.prev = prev_col ;\n      }\n\n      /* === Scan the column ========================================== */\n\n      cp = &A [Col [col].start] ;\n      cp_end = cp + Col [col].length ;\n      while (cp < cp_end)\n      {\n\t/* get a row */\n\trow = *cp++ ;\n\trow_mark = Row [row].shared2.mark ;\n\t/* skip if dead */\n\tif (ROW_IS_MARKED_DEAD (row_mark))\n\t{\n\t  continue ;\n\t}\n\tCOLAMD_ASSERT (row != pivot_row) ;\n\tset_difference = row_mark - tag_mark ;\n\t/* check if the row has been seen yet */\n\tif (set_difference < 0)\n\t{\n\t  COLAMD_ASSERT (Row [row].shared1.degree <= max_deg) ;\n\t  set_difference = Row [row].shared1.degree ;\n\t}\n\t/* subtract column thickness from this row's set difference */\n\tset_difference -= col_thickness ;\n\tCOLAMD_ASSERT (set_difference >= 0) ;\n\t/* absorb this row if the set difference becomes zero */\n\tif (set_difference == 0)\n\t{\n\t  COLAMD_DEBUG3 ((\"aggressive absorption. Row: %d\\n\", row)) ;\n\t  KILL_ROW (row) ;\n\t}\n\telse\n\t{\n\t  /* save the new mark */\n\t  Row [row].shared2.mark = set_difference + tag_mark ;\n\t}\n      }\n    }\n\n\n    /* === Add up set differences for each column ======================= */\n\n    COLAMD_DEBUG3 ((\"** Adding set differences phase. **\\n\")) ;\n\n    /* for each column in pivot row */\n    rp = &A [pivot_row_start] ;\n    rp_end = rp + pivot_row_length ;\n    while (rp < rp_end)\n    {\n      /* get a column */\n      col = *rp++ ;\n      COLAMD_ASSERT (COL_IS_ALIVE (col) && col != pivot_col) ;\n      hash = 0 ;\n      cur_score = 0 ;\n      cp = &A [Col [col].start] ;\n      /* compact the column */\n      new_cp = cp ;\n      cp_end = cp + Col [col].length ;\n\n      COLAMD_DEBUG4 ((\"Adding set diffs for Col: %d.\\n\", col)) ;\n\n      while (cp < cp_end)\n      {\n\t/* get a row */\n\trow = *cp++ ;\n\tCOLAMD_ASSERT(row >= 0 && row < n_row) ;\n\trow_mark = Row [row].shared2.mark ;\n\t/* skip if dead */\n\tif (ROW_IS_MARKED_DEAD (row_mark))\n\t{\n\t  continue ;\n\t}\n\tCOLAMD_ASSERT (row_mark > tag_mark) ;\n\t/* compact the column */\n\t*new_cp++ = row ;\n\t/* compute hash function */\n\thash += row ;\n\t/* add set difference */\n\tcur_score += row_mark - tag_mark ;\n\t/* integer overflow... */\n\tcur_score = numext::mini(cur_score, n_col) ;\n      }\n\n      /* recompute the column's length */\n      Col [col].length = (IndexType) (new_cp - &A [Col [col].start]) ;\n\n      /* === Further mass elimination ================================= */\n\n      if (Col [col].length == 0)\n      {\n\tCOLAMD_DEBUG4 ((\"further mass elimination. Col: %d\\n\", col)) ;\n\t/* nothing left but the pivot row in this column */\n\tKILL_PRINCIPAL_COL (col) ;\n\tpivot_row_degree -= Col [col].shared1.thickness ;\n\tCOLAMD_ASSERT (pivot_row_degree >= 0) ;\n\t/* order it */\n\tCol [col].shared2.order = k ;\n\t/* increment order count by column thickness */\n\tk += Col [col].shared1.thickness ;\n      }\n      else\n      {\n\t/* === Prepare for supercolumn detection ==================== */\n\n\tCOLAMD_DEBUG4 ((\"Preparing supercol detection for Col: %d.\\n\", col)) ;\n\n\t/* save score so far */\n\tCol [col].shared2.score = cur_score ;\n\n\t/* add column to hash table, for supercolumn detection */\n\thash %= n_col + 1 ;\n\n\tCOLAMD_DEBUG4 ((\" Hash = %d, n_col = %d.\\n\", hash, n_col)) ;\n\tCOLAMD_ASSERT (hash <= n_col) ;\n\n\thead_column = head [hash] ;\n\tif (head_column > COLAMD_EMPTY)\n\t{\n\t  /* degree list \"hash\" is non-empty, use prev (shared3) of */\n\t  /* first column in degree list as head of hash bucket */\n\t  first_col = Col [head_column].shared3.headhash ;\n\t  Col [head_column].shared3.headhash = col ;\n\t}\n\telse\n\t{\n\t  /* degree list \"hash\" is empty, use head as hash bucket */\n\t  first_col = - (head_column + 2) ;\n\t  head [hash] = - (col + 2) ;\n\t}\n\tCol [col].shared4.hash_next = first_col ;\n\n\t/* save hash function in Col [col].shared3.hash */\n\tCol [col].shared3.hash = (IndexType) hash ;\n\tCOLAMD_ASSERT (COL_IS_ALIVE (col)) ;\n      }\n    }\n\n    /* The approximate external column degree is now computed.  */\n\n    /* === Supercolumn detection ======================================== */\n\n    COLAMD_DEBUG3 ((\"** Supercolumn detection phase. **\\n\")) ;\n\n    Eigen::internal::detect_super_cols (Col, A, head, pivot_row_start, pivot_row_length) ;\n\n    /* === Kill the pivotal column ====================================== */\n\n    KILL_PRINCIPAL_COL (pivot_col) ;\n\n    /* === Clear mark =================================================== */\n\n    tag_mark += (max_deg + 1) ;\n    if (tag_mark >= max_mark)\n    {\n      COLAMD_DEBUG2 ((\"clearing tag_mark\\n\")) ;\n      tag_mark = Eigen::internal::clear_mark (n_row, Row) ;\n    }\n\n    /* === Finalize the new pivot row, and column scores ================ */\n\n    COLAMD_DEBUG3 ((\"** Finalize scores phase. **\\n\")) ;\n\n    /* for each column in pivot row */\n    rp = &A [pivot_row_start] ;\n    /* compact the pivot row */\n    new_rp = rp ;\n    rp_end = rp + pivot_row_length ;\n    while (rp < rp_end)\n    {\n      col = *rp++ ;\n      /* skip dead columns */\n      if (COL_IS_DEAD (col))\n      {\n\tcontinue ;\n      }\n      *new_rp++ = col ;\n      /* add new pivot row to column */\n      A [Col [col].start + (Col [col].length++)] = pivot_row ;\n\n      /* retrieve score so far and add on pivot row's degree. */\n      /* (we wait until here for this in case the pivot */\n      /* row's degree was reduced due to mass elimination). */\n      cur_score = Col [col].shared2.score + pivot_row_degree ;\n\n      /* calculate the max possible score as the number of */\n      /* external columns minus the 'k' value minus the */\n      /* columns thickness */\n      max_score = n_col - k - Col [col].shared1.thickness ;\n\n      /* make the score the external degree of the union-of-rows */\n      cur_score -= Col [col].shared1.thickness ;\n\n      /* make sure score is less or equal than the max score */\n      cur_score = numext::mini(cur_score, max_score) ;\n      COLAMD_ASSERT (cur_score >= 0) ;\n\n      /* store updated score */\n      Col [col].shared2.score = cur_score ;\n\n      /* === Place column back in degree list ========================= */\n\n      COLAMD_ASSERT (min_score >= 0) ;\n      COLAMD_ASSERT (min_score <= n_col) ;\n      COLAMD_ASSERT (cur_score >= 0) ;\n      COLAMD_ASSERT (cur_score <= n_col) ;\n      COLAMD_ASSERT (head [cur_score] >= COLAMD_EMPTY) ;\n      next_col = head [cur_score] ;\n      Col [col].shared4.degree_next = next_col ;\n      Col [col].shared3.prev = COLAMD_EMPTY ;\n      if (next_col != COLAMD_EMPTY)\n      {\n\tCol [next_col].shared3.prev = col ;\n      }\n      head [cur_score] = col ;\n\n      /* see if this score is less than current min */\n      min_score = numext::mini(min_score, cur_score) ;\n\n    }\n\n    /* === Resurrect the new pivot row ================================== */\n\n    if (pivot_row_degree > 0)\n    {\n      /* update pivot row length to reflect any cols that were killed */\n      /* during super-col detection and mass elimination */\n      Row [pivot_row].start  = pivot_row_start ;\n      Row [pivot_row].length = (IndexType) (new_rp - &A[pivot_row_start]) ;\n      Row [pivot_row].shared1.degree = pivot_row_degree ;\n      Row [pivot_row].shared2.mark = 0 ;\n      /* pivot row is no longer dead */\n    }\n  }\n\n  /* === All principal columns have now been ordered ====================== */\n\n  return (ngarbage) ;\n}\n\n\n/* ========================================================================== */\n/* === order_children ======================================================= */\n/* ========================================================================== */\n\n/*\n  The find_ordering routine has ordered all of the principal columns (the\n  representatives of the supercolumns).  The non-principal columns have not\n  yet been ordered.  This routine orders those columns by walking up the\n  parent tree (a column is a child of the column which absorbed it).  The\n  final permutation vector is then placed in p [0 ... n_col-1], with p [0]\n  being the first column, and p [n_col-1] being the last.  It doesn't look\n  like it at first glance, but be assured that this routine takes time linear\n  in the number of columns.  Although not immediately obvious, the time\n  taken by this routine is O (n_col), that is, linear in the number of\n  columns.  Not user-callable.\n*/\ntemplate <typename IndexType>\nstatic inline  void order_children\n(\n  /* === Parameters ======================================================= */\n\n  IndexType n_col,      /* number of columns of A */\n  colamd_col<IndexType> Col [],    /* of size n_col+1 */\n  IndexType p []      /* p [0 ... n_col-1] is the column permutation*/\n  )\n{\n  /* === Local variables ================================================== */\n\n  IndexType i ;     /* loop counter for all columns */\n  IndexType c ;     /* column index */\n  IndexType parent ;    /* index of column's parent */\n  IndexType order ;     /* column's order */\n\n  /* === Order each non-principal column ================================== */\n\n  for (i = 0 ; i < n_col ; i++)\n  {\n    /* find an un-ordered non-principal column */\n    COLAMD_ASSERT (COL_IS_DEAD (i)) ;\n    if (!COL_IS_DEAD_PRINCIPAL (i) && Col [i].shared2.order == COLAMD_EMPTY)\n    {\n      parent = i ;\n      /* once found, find its principal parent */\n      do\n      {\n\tparent = Col [parent].shared1.parent ;\n      } while (!COL_IS_DEAD_PRINCIPAL (parent)) ;\n\n      /* now, order all un-ordered non-principal columns along path */\n      /* to this parent.  collapse tree at the same time */\n      c = i ;\n      /* get order of parent */\n      order = Col [parent].shared2.order ;\n\n      do\n      {\n\tCOLAMD_ASSERT (Col [c].shared2.order == COLAMD_EMPTY) ;\n\n\t/* order this column */\n\tCol [c].shared2.order = order++ ;\n\t/* collaps tree */\n\tCol [c].shared1.parent = parent ;\n\n\t/* get immediate parent of this column */\n\tc = Col [c].shared1.parent ;\n\n\t/* continue until we hit an ordered column.  There are */\n\t/* guarranteed not to be anymore unordered columns */\n\t/* above an ordered column */\n      } while (Col [c].shared2.order == COLAMD_EMPTY) ;\n\n      /* re-order the super_col parent to largest order for this group */\n      Col [parent].shared2.order = order ;\n    }\n  }\n\n  /* === Generate the permutation ========================================= */\n\n  for (c = 0 ; c < n_col ; c++)\n  {\n    p [Col [c].shared2.order] = c ;\n  }\n}\n\n\n/* ========================================================================== */\n/* === detect_super_cols ==================================================== */\n/* ========================================================================== */\n\n/*\n  Detects supercolumns by finding matches between columns in the hash buckets.\n  Check amongst columns in the set A [row_start ... row_start + row_length-1].\n  The columns under consideration are currently *not* in the degree lists,\n  and have already been placed in the hash buckets.\n\n  The hash bucket for columns whose hash function is equal to h is stored\n  as follows:\n\n  if head [h] is >= 0, then head [h] contains a degree list, so:\n\n  head [h] is the first column in degree bucket h.\n  Col [head [h]].headhash gives the first column in hash bucket h.\n\n  otherwise, the degree list is empty, and:\n\n  -(head [h] + 2) is the first column in hash bucket h.\n\n  For a column c in a hash bucket, Col [c].shared3.prev is NOT a \"previous\n  column\" pointer.  Col [c].shared3.hash is used instead as the hash number\n  for that column.  The value of Col [c].shared4.hash_next is the next column\n  in the same hash bucket.\n\n  Assuming no, or \"few\" hash collisions, the time taken by this routine is\n  linear in the sum of the sizes (lengths) of each column whose score has\n  just been computed in the approximate degree computation.\n  Not user-callable.\n*/\ntemplate <typename IndexType>\nstatic void detect_super_cols\n(\n  /* === Parameters ======================================================= */\n  \n  colamd_col<IndexType> Col [],    /* of size n_col+1 */\n  IndexType A [],     /* row indices of A */\n  IndexType head [],    /* head of degree lists and hash buckets */\n  IndexType row_start,    /* pointer to set of columns to check */\n  IndexType row_length    /* number of columns to check */\n)\n{\n  /* === Local variables ================================================== */\n\n  IndexType hash ;      /* hash value for a column */\n  IndexType *rp ;     /* pointer to a row */\n  IndexType c ;     /* a column index */\n  IndexType super_c ;   /* column index of the column to absorb into */\n  IndexType *cp1 ;      /* column pointer for column super_c */\n  IndexType *cp2 ;      /* column pointer for column c */\n  IndexType length ;    /* length of column super_c */\n  IndexType prev_c ;    /* column preceding c in hash bucket */\n  IndexType i ;     /* loop counter */\n  IndexType *rp_end ;   /* pointer to the end of the row */\n  IndexType col ;     /* a column index in the row to check */\n  IndexType head_column ;   /* first column in hash bucket or degree list */\n  IndexType first_col ;   /* first column in hash bucket */\n\n  /* === Consider each column in the row ================================== */\n\n  rp = &A [row_start] ;\n  rp_end = rp + row_length ;\n  while (rp < rp_end)\n  {\n    col = *rp++ ;\n    if (COL_IS_DEAD (col))\n    {\n      continue ;\n    }\n\n    /* get hash number for this column */\n    hash = Col [col].shared3.hash ;\n    COLAMD_ASSERT (hash <= n_col) ;\n\n    /* === Get the first column in this hash bucket ===================== */\n\n    head_column = head [hash] ;\n    if (head_column > COLAMD_EMPTY)\n    {\n      first_col = Col [head_column].shared3.headhash ;\n    }\n    else\n    {\n      first_col = - (head_column + 2) ;\n    }\n\n    /* === Consider each column in the hash bucket ====================== */\n\n    for (super_c = first_col ; super_c != COLAMD_EMPTY ;\n\t super_c = Col [super_c].shared4.hash_next)\n    {\n      COLAMD_ASSERT (COL_IS_ALIVE (super_c)) ;\n      COLAMD_ASSERT (Col [super_c].shared3.hash == hash) ;\n      length = Col [super_c].length ;\n\n      /* prev_c is the column preceding column c in the hash bucket */\n      prev_c = super_c ;\n\n      /* === Compare super_c with all columns after it ================ */\n\n      for (c = Col [super_c].shared4.hash_next ;\n\t   c != COLAMD_EMPTY ; c = Col [c].shared4.hash_next)\n      {\n\tCOLAMD_ASSERT (c != super_c) ;\n\tCOLAMD_ASSERT (COL_IS_ALIVE (c)) ;\n\tCOLAMD_ASSERT (Col [c].shared3.hash == hash) ;\n\n\t/* not identical if lengths or scores are different */\n\tif (Col [c].length != length ||\n\t    Col [c].shared2.score != Col [super_c].shared2.score)\n\t{\n\t  prev_c = c ;\n\t  continue ;\n\t}\n\n\t/* compare the two columns */\n\tcp1 = &A [Col [super_c].start] ;\n\tcp2 = &A [Col [c].start] ;\n\n\tfor (i = 0 ; i < length ; i++)\n\t{\n\t  /* the columns are \"clean\" (no dead rows) */\n\t  COLAMD_ASSERT (ROW_IS_ALIVE (*cp1))  ;\n\t  COLAMD_ASSERT (ROW_IS_ALIVE (*cp2))  ;\n\t  /* row indices will same order for both supercols, */\n\t  /* no gather scatter nessasary */\n\t  if (*cp1++ != *cp2++)\n\t  {\n\t    break ;\n\t  }\n\t}\n\n\t/* the two columns are different if the for-loop \"broke\" */\n\tif (i != length)\n\t{\n\t  prev_c = c ;\n\t  continue ;\n\t}\n\n\t/* === Got it!  two columns are identical =================== */\n\n\tCOLAMD_ASSERT (Col [c].shared2.score == Col [super_c].shared2.score) ;\n\n\tCol [super_c].shared1.thickness += Col [c].shared1.thickness ;\n\tCol [c].shared1.parent = super_c ;\n\tKILL_NON_PRINCIPAL_COL (c) ;\n\t/* order c later, in order_children() */\n\tCol [c].shared2.order = COLAMD_EMPTY ;\n\t/* remove c from hash bucket */\n\tCol [prev_c].shared4.hash_next = Col [c].shared4.hash_next ;\n      }\n    }\n\n    /* === Empty this hash bucket ======================================= */\n\n    if (head_column > COLAMD_EMPTY)\n    {\n      /* corresponding degree list \"hash\" is not empty */\n      Col [head_column].shared3.headhash = COLAMD_EMPTY ;\n    }\n    else\n    {\n      /* corresponding degree list \"hash\" is empty */\n      head [hash] = COLAMD_EMPTY ;\n    }\n  }\n}\n\n\n/* ========================================================================== */\n/* === garbage_collection =================================================== */\n/* ========================================================================== */\n\n/*\n  Defragments and compacts columns and rows in the workspace A.  Used when\n  all available memory has been used while performing row merging.  Returns\n  the index of the first free position in A, after garbage collection.  The\n  time taken by this routine is linear is the size of the array A, which is\n  itself linear in the number of nonzeros in the input matrix.\n  Not user-callable.\n*/\ntemplate <typename IndexType>\nstatic IndexType garbage_collection  /* returns the new value of pfree */\n  (\n    /* === Parameters ======================================================= */\n    \n    IndexType n_row,      /* number of rows */\n    IndexType n_col,      /* number of columns */\n    Colamd_Row<IndexType> Row [],    /* row info */\n    colamd_col<IndexType> Col [],    /* column info */\n    IndexType A [],     /* A [0 ... Alen-1] holds the matrix */\n    IndexType *pfree      /* &A [0] ... pfree is in use */\n    )\n{\n  /* === Local variables ================================================== */\n\n  IndexType *psrc ;     /* source pointer */\n  IndexType *pdest ;    /* destination pointer */\n  IndexType j ;     /* counter */\n  IndexType r ;     /* a row index */\n  IndexType c ;     /* a column index */\n  IndexType length ;    /* length of a row or column */\n\n  /* === Defragment the columns =========================================== */\n\n  pdest = &A[0] ;\n  for (c = 0 ; c < n_col ; c++)\n  {\n    if (COL_IS_ALIVE (c))\n    {\n      psrc = &A [Col [c].start] ;\n\n      /* move and compact the column */\n      COLAMD_ASSERT (pdest <= psrc) ;\n      Col [c].start = (IndexType) (pdest - &A [0]) ;\n      length = Col [c].length ;\n      for (j = 0 ; j < length ; j++)\n      {\n\tr = *psrc++ ;\n\tif (ROW_IS_ALIVE (r))\n\t{\n\t  *pdest++ = r ;\n\t}\n      }\n      Col [c].length = (IndexType) (pdest - &A [Col [c].start]) ;\n    }\n  }\n\n  /* === Prepare to defragment the rows =================================== */\n\n  for (r = 0 ; r < n_row ; r++)\n  {\n    if (ROW_IS_ALIVE (r))\n    {\n      if (Row [r].length == 0)\n      {\n\t/* this row is of zero length.  cannot compact it, so kill it */\n\tCOLAMD_DEBUG3 ((\"Defrag row kill\\n\")) ;\n\tKILL_ROW (r) ;\n      }\n      else\n      {\n\t/* save first column index in Row [r].shared2.first_column */\n\tpsrc = &A [Row [r].start] ;\n\tRow [r].shared2.first_column = *psrc ;\n\tCOLAMD_ASSERT (ROW_IS_ALIVE (r)) ;\n\t/* flag the start of the row with the one's complement of row */\n\t*psrc = ONES_COMPLEMENT (r) ;\n\n      }\n    }\n  }\n\n  /* === Defragment the rows ============================================== */\n\n  psrc = pdest ;\n  while (psrc < pfree)\n  {\n    /* find a negative number ... the start of a row */\n    if (*psrc++ < 0)\n    {\n      psrc-- ;\n      /* get the row index */\n      r = ONES_COMPLEMENT (*psrc) ;\n      COLAMD_ASSERT (r >= 0 && r < n_row) ;\n      /* restore first column index */\n      *psrc = Row [r].shared2.first_column ;\n      COLAMD_ASSERT (ROW_IS_ALIVE (r)) ;\n\n      /* move and compact the row */\n      COLAMD_ASSERT (pdest <= psrc) ;\n      Row [r].start = (IndexType) (pdest - &A [0]) ;\n      length = Row [r].length ;\n      for (j = 0 ; j < length ; j++)\n      {\n\tc = *psrc++ ;\n\tif (COL_IS_ALIVE (c))\n\t{\n\t  *pdest++ = c ;\n\t}\n      }\n      Row [r].length = (IndexType) (pdest - &A [Row [r].start]) ;\n\n    }\n  }\n  /* ensure we found all the rows */\n  COLAMD_ASSERT (debug_rows == 0) ;\n\n  /* === Return the new value of pfree ==================================== */\n\n  return ((IndexType) (pdest - &A [0])) ;\n}\n\n\n/* ========================================================================== */\n/* === clear_mark =========================================================== */\n/* ========================================================================== */\n\n/*\n  Clears the Row [].shared2.mark array, and returns the new tag_mark.\n  Return value is the new tag_mark.  Not user-callable.\n*/\ntemplate <typename IndexType>\nstatic inline  IndexType clear_mark  /* return the new value for tag_mark */\n  (\n      /* === Parameters ======================================================= */\n\n    IndexType n_row,    /* number of rows in A */\n    Colamd_Row<IndexType> Row [] /* Row [0 ... n_row-1].shared2.mark is set to zero */\n    )\n{\n  /* === Local variables ================================================== */\n\n  IndexType r ;\n\n  for (r = 0 ; r < n_row ; r++)\n  {\n    if (ROW_IS_ALIVE (r))\n    {\n      Row [r].shared2.mark = 0 ;\n    }\n  }\n  return (1) ;\n}\n\n\n} // namespace internal \n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/OrderingMethods/Ordering.h",
    "content": " \n// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2012  Désiré Nuentsa-Wakam <desire.nuentsa_wakam@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_ORDERING_H\n#define EIGEN_ORDERING_H\n\nnamespace Eigen {\n  \n#include \"Eigen_Colamd.h\"\n\nnamespace internal {\n    \n/** \\internal\n  * \\ingroup OrderingMethods_Module\n  * \\param[in] A the input non-symmetric matrix\n  * \\param[out] symmat the symmetric pattern A^T+A from the input matrix \\a A.\n  * FIXME: The values should not be considered here\n  */\ntemplate<typename MatrixType> \nvoid ordering_helper_at_plus_a(const MatrixType& A, MatrixType& symmat)\n{\n  MatrixType C;\n  C = A.transpose(); // NOTE: Could be  costly\n  for (int i = 0; i < C.rows(); i++) \n  {\n      for (typename MatrixType::InnerIterator it(C, i); it; ++it)\n        it.valueRef() = 0.0;\n  }\n  symmat = C + A;\n}\n    \n}\n\n#ifndef EIGEN_MPL2_ONLY\n\n/** \\ingroup OrderingMethods_Module\n  * \\class AMDOrdering\n  *\n  * Functor computing the \\em approximate \\em minimum \\em degree ordering\n  * If the matrix is not structurally symmetric, an ordering of A^T+A is computed\n  * \\tparam  StorageIndex The type of indices of the matrix \n  * \\sa COLAMDOrdering\n  */\ntemplate <typename StorageIndex>\nclass AMDOrdering\n{\n  public:\n    typedef PermutationMatrix<Dynamic, Dynamic, StorageIndex> PermutationType;\n    \n    /** Compute the permutation vector from a sparse matrix\n     * This routine is much faster if the input matrix is column-major     \n     */\n    template <typename MatrixType>\n    void operator()(const MatrixType& mat, PermutationType& perm)\n    {\n      // Compute the symmetric pattern\n      SparseMatrix<typename MatrixType::Scalar, ColMajor, StorageIndex> symm;\n      internal::ordering_helper_at_plus_a(mat,symm); \n    \n      // Call the AMD routine \n      //m_mat.prune(keep_diag());\n      internal::minimum_degree_ordering(symm, perm);\n    }\n    \n    /** Compute the permutation with a selfadjoint matrix */\n    template <typename SrcType, unsigned int SrcUpLo> \n    void operator()(const SparseSelfAdjointView<SrcType, SrcUpLo>& mat, PermutationType& perm)\n    { \n      SparseMatrix<typename SrcType::Scalar, ColMajor, StorageIndex> C; C = mat;\n      \n      // Call the AMD routine \n      // m_mat.prune(keep_diag()); //Remove the diagonal elements \n      internal::minimum_degree_ordering(C, perm);\n    }\n};\n\n#endif // EIGEN_MPL2_ONLY\n\n/** \\ingroup OrderingMethods_Module\n  * \\class NaturalOrdering\n  *\n  * Functor computing the natural ordering (identity)\n  * \n  * \\note Returns an empty permutation matrix\n  * \\tparam  StorageIndex The type of indices of the matrix \n  */\ntemplate <typename StorageIndex>\nclass NaturalOrdering\n{\n  public:\n    typedef PermutationMatrix<Dynamic, Dynamic, StorageIndex> PermutationType;\n    \n    /** Compute the permutation vector from a column-major sparse matrix */\n    template <typename MatrixType>\n    void operator()(const MatrixType& /*mat*/, PermutationType& perm)\n    {\n      perm.resize(0); \n    }\n    \n};\n\n/** \\ingroup OrderingMethods_Module\n  * \\class COLAMDOrdering\n  *\n  * \\tparam  StorageIndex The type of indices of the matrix \n  * \n  * Functor computing the \\em column \\em approximate \\em minimum \\em degree ordering \n  * The matrix should be in column-major and \\b compressed format (see SparseMatrix::makeCompressed()).\n  */\ntemplate<typename StorageIndex>\nclass COLAMDOrdering\n{\n  public:\n    typedef PermutationMatrix<Dynamic, Dynamic, StorageIndex> PermutationType; \n    typedef Matrix<StorageIndex, Dynamic, 1> IndexVector;\n    \n    /** Compute the permutation vector \\a perm form the sparse matrix \\a mat\n      * \\warning The input sparse matrix \\a mat must be in compressed mode (see SparseMatrix::makeCompressed()).\n      */\n    template <typename MatrixType>\n    void operator() (const MatrixType& mat, PermutationType& perm)\n    {\n      eigen_assert(mat.isCompressed() && \"COLAMDOrdering requires a sparse matrix in compressed mode. Call .makeCompressed() before passing it to COLAMDOrdering\");\n      \n      StorageIndex m = StorageIndex(mat.rows());\n      StorageIndex n = StorageIndex(mat.cols());\n      StorageIndex nnz = StorageIndex(mat.nonZeros());\n      // Get the recommended value of Alen to be used by colamd\n      StorageIndex Alen = internal::colamd_recommended(nnz, m, n); \n      // Set the default parameters\n      double knobs [COLAMD_KNOBS]; \n      StorageIndex stats [COLAMD_STATS];\n      internal::colamd_set_defaults(knobs);\n      \n      IndexVector p(n+1), A(Alen); \n      for(StorageIndex i=0; i <= n; i++)   p(i) = mat.outerIndexPtr()[i];\n      for(StorageIndex i=0; i < nnz; i++)  A(i) = mat.innerIndexPtr()[i];\n      // Call Colamd routine to compute the ordering \n      StorageIndex info = internal::colamd(m, n, Alen, A.data(), p.data(), knobs, stats); \n      EIGEN_UNUSED_VARIABLE(info);\n      eigen_assert( info && \"COLAMD failed \" );\n      \n      perm.resize(n);\n      for (StorageIndex i = 0; i < n; i++) perm.indices()(p(i)) = i;\n    }\n};\n\n} // end namespace Eigen\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/PaStiXSupport/PaStiXSupport.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2012 Désiré Nuentsa-Wakam <desire.nuentsa_wakam@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_PASTIXSUPPORT_H\n#define EIGEN_PASTIXSUPPORT_H\n\nnamespace Eigen { \n\n#if defined(DCOMPLEX)\n  #define PASTIX_COMPLEX  COMPLEX\n  #define PASTIX_DCOMPLEX DCOMPLEX\n#else\n  #define PASTIX_COMPLEX  std::complex<float>\n  #define PASTIX_DCOMPLEX std::complex<double>\n#endif\n\n/** \\ingroup PaStiXSupport_Module\n  * \\brief Interface to the PaStix solver\n  * \n  * This class is used to solve the linear systems A.X = B via the PaStix library. \n  * The matrix can be either real or complex, symmetric or not.\n  *\n  * \\sa TutorialSparseDirectSolvers\n  */\ntemplate<typename _MatrixType, bool IsStrSym = false> class PastixLU;\ntemplate<typename _MatrixType, int Options> class PastixLLT;\ntemplate<typename _MatrixType, int Options> class PastixLDLT;\n\nnamespace internal\n{\n    \n  template<class Pastix> struct pastix_traits;\n\n  template<typename _MatrixType>\n  struct pastix_traits< PastixLU<_MatrixType> >\n  {\n    typedef _MatrixType MatrixType;\n    typedef typename _MatrixType::Scalar Scalar;\n    typedef typename _MatrixType::RealScalar RealScalar;\n    typedef typename _MatrixType::StorageIndex StorageIndex;\n  };\n\n  template<typename _MatrixType, int Options>\n  struct pastix_traits< PastixLLT<_MatrixType,Options> >\n  {\n    typedef _MatrixType MatrixType;\n    typedef typename _MatrixType::Scalar Scalar;\n    typedef typename _MatrixType::RealScalar RealScalar;\n    typedef typename _MatrixType::StorageIndex StorageIndex;\n  };\n\n  template<typename _MatrixType, int Options>\n  struct pastix_traits< PastixLDLT<_MatrixType,Options> >\n  {\n    typedef _MatrixType MatrixType;\n    typedef typename _MatrixType::Scalar Scalar;\n    typedef typename _MatrixType::RealScalar RealScalar;\n    typedef typename _MatrixType::StorageIndex StorageIndex;\n  };\n  \n  void eigen_pastix(pastix_data_t **pastix_data, int pastix_comm, int n, int *ptr, int *idx, float *vals, int *perm, int * invp, float *x, int nbrhs, int *iparm, double *dparm)\n  {\n    if (n == 0) { ptr = NULL; idx = NULL; vals = NULL; }\n    if (nbrhs == 0) {x = NULL; nbrhs=1;}\n    s_pastix(pastix_data, pastix_comm, n, ptr, idx, vals, perm, invp, x, nbrhs, iparm, dparm); \n  }\n  \n  void eigen_pastix(pastix_data_t **pastix_data, int pastix_comm, int n, int *ptr, int *idx, double *vals, int *perm, int * invp, double *x, int nbrhs, int *iparm, double *dparm)\n  {\n    if (n == 0) { ptr = NULL; idx = NULL; vals = NULL; }\n    if (nbrhs == 0) {x = NULL; nbrhs=1;}\n    d_pastix(pastix_data, pastix_comm, n, ptr, idx, vals, perm, invp, x, nbrhs, iparm, dparm); \n  }\n  \n  void eigen_pastix(pastix_data_t **pastix_data, int pastix_comm, int n, int *ptr, int *idx, std::complex<float> *vals, int *perm, int * invp, std::complex<float> *x, int nbrhs, int *iparm, double *dparm)\n  {\n    if (n == 0) { ptr = NULL; idx = NULL; vals = NULL; }\n    if (nbrhs == 0) {x = NULL; nbrhs=1;}\n    c_pastix(pastix_data, pastix_comm, n, ptr, idx, reinterpret_cast<PASTIX_COMPLEX*>(vals), perm, invp, reinterpret_cast<PASTIX_COMPLEX*>(x), nbrhs, iparm, dparm); \n  }\n  \n  void eigen_pastix(pastix_data_t **pastix_data, int pastix_comm, int n, int *ptr, int *idx, std::complex<double> *vals, int *perm, int * invp, std::complex<double> *x, int nbrhs, int *iparm, double *dparm)\n  {\n    if (n == 0) { ptr = NULL; idx = NULL; vals = NULL; }\n    if (nbrhs == 0) {x = NULL; nbrhs=1;}\n    z_pastix(pastix_data, pastix_comm, n, ptr, idx, reinterpret_cast<PASTIX_DCOMPLEX*>(vals), perm, invp, reinterpret_cast<PASTIX_DCOMPLEX*>(x), nbrhs, iparm, dparm); \n  }\n\n  // Convert the matrix  to Fortran-style Numbering\n  template <typename MatrixType>\n  void c_to_fortran_numbering (MatrixType& mat)\n  {\n    if ( !(mat.outerIndexPtr()[0]) ) \n    { \n      int i;\n      for(i = 0; i <= mat.rows(); ++i)\n        ++mat.outerIndexPtr()[i];\n      for(i = 0; i < mat.nonZeros(); ++i)\n        ++mat.innerIndexPtr()[i];\n    }\n  }\n  \n  // Convert to C-style Numbering\n  template <typename MatrixType>\n  void fortran_to_c_numbering (MatrixType& mat)\n  {\n    // Check the Numbering\n    if ( mat.outerIndexPtr()[0] == 1 ) \n    { // Convert to C-style numbering\n      int i;\n      for(i = 0; i <= mat.rows(); ++i)\n        --mat.outerIndexPtr()[i];\n      for(i = 0; i < mat.nonZeros(); ++i)\n        --mat.innerIndexPtr()[i];\n    }\n  }\n}\n\n// This is the base class to interface with PaStiX functions. \n// Users should not used this class directly. \ntemplate <class Derived>\nclass PastixBase : public SparseSolverBase<Derived>\n{\n  protected:\n    typedef SparseSolverBase<Derived> Base;\n    using Base::derived;\n    using Base::m_isInitialized;\n  public:\n    using Base::_solve_impl;\n    \n    typedef typename internal::pastix_traits<Derived>::MatrixType _MatrixType;\n    typedef _MatrixType MatrixType;\n    typedef typename MatrixType::Scalar Scalar;\n    typedef typename MatrixType::RealScalar RealScalar;\n    typedef typename MatrixType::StorageIndex StorageIndex;\n    typedef Matrix<Scalar,Dynamic,1> Vector;\n    typedef SparseMatrix<Scalar, ColMajor> ColSpMatrix;\n    enum {\n      ColsAtCompileTime = MatrixType::ColsAtCompileTime,\n      MaxColsAtCompileTime = MatrixType::MaxColsAtCompileTime\n    };\n    \n  public:\n    \n    PastixBase() : m_initisOk(false), m_analysisIsOk(false), m_factorizationIsOk(false), m_pastixdata(0), m_size(0)\n    {\n      init();\n    }\n    \n    ~PastixBase() \n    {\n      clean();\n    }\n    \n    template<typename Rhs,typename Dest>\n    bool _solve_impl(const MatrixBase<Rhs> &b, MatrixBase<Dest> &x) const;\n    \n    /** Returns a reference to the integer vector IPARM of PaStiX parameters\n      * to modify the default parameters. \n      * The statistics related to the different phases of factorization and solve are saved here as well\n      * \\sa analyzePattern() factorize()\n      */\n    Array<StorageIndex,IPARM_SIZE,1>& iparm()\n    {\n      return m_iparm; \n    }\n    \n    /** Return a reference to a particular index parameter of the IPARM vector \n     * \\sa iparm()\n     */\n    \n    int& iparm(int idxparam)\n    {\n      return m_iparm(idxparam);\n    }\n    \n     /** Returns a reference to the double vector DPARM of PaStiX parameters \n      * The statistics related to the different phases of factorization and solve are saved here as well\n      * \\sa analyzePattern() factorize()\n      */\n    Array<double,DPARM_SIZE,1>& dparm()\n    {\n      return m_dparm; \n    }\n    \n    \n    /** Return a reference to a particular index parameter of the DPARM vector \n     * \\sa dparm()\n     */\n    double& dparm(int idxparam)\n    {\n      return m_dparm(idxparam);\n    }\n    \n    inline Index cols() const { return m_size; }\n    inline Index rows() const { return m_size; }\n    \n     /** \\brief Reports whether previous computation was successful.\n      *\n      * \\returns \\c Success if computation was succesful,\n      *          \\c NumericalIssue if the PaStiX reports a problem\n      *          \\c InvalidInput if the input matrix is invalid\n      *\n      * \\sa iparm()          \n      */\n    ComputationInfo info() const\n    {\n      eigen_assert(m_isInitialized && \"Decomposition is not initialized.\");\n      return m_info;\n    }\n    \n  protected:\n\n    // Initialize the Pastix data structure, check the matrix\n    void init(); \n    \n    // Compute the ordering and the symbolic factorization\n    void analyzePattern(ColSpMatrix& mat);\n    \n    // Compute the numerical factorization\n    void factorize(ColSpMatrix& mat);\n    \n    // Free all the data allocated by Pastix\n    void clean()\n    {\n      eigen_assert(m_initisOk && \"The Pastix structure should be allocated first\"); \n      m_iparm(IPARM_START_TASK) = API_TASK_CLEAN;\n      m_iparm(IPARM_END_TASK) = API_TASK_CLEAN;\n      internal::eigen_pastix(&m_pastixdata, MPI_COMM_WORLD, 0, 0, 0, (Scalar*)0,\n                             m_perm.data(), m_invp.data(), 0, 0, m_iparm.data(), m_dparm.data());\n    }\n    \n    void compute(ColSpMatrix& mat);\n    \n    int m_initisOk; \n    int m_analysisIsOk;\n    int m_factorizationIsOk;\n    mutable ComputationInfo m_info; \n    mutable pastix_data_t *m_pastixdata; // Data structure for pastix\n    mutable int m_comm; // The MPI communicator identifier\n    mutable Array<int,IPARM_SIZE,1> m_iparm; // integer vector for the input parameters\n    mutable Array<double,DPARM_SIZE,1> m_dparm; // Scalar vector for the input parameters\n    mutable Matrix<StorageIndex,Dynamic,1> m_perm;  // Permutation vector\n    mutable Matrix<StorageIndex,Dynamic,1> m_invp;  // Inverse permutation vector\n    mutable int m_size; // Size of the matrix \n}; \n\n /** Initialize the PaStiX data structure. \n   *A first call to this function fills iparm and dparm with the default PaStiX parameters\n   * \\sa iparm() dparm()\n   */\ntemplate <class Derived>\nvoid PastixBase<Derived>::init()\n{\n  m_size = 0; \n  m_iparm.setZero(IPARM_SIZE);\n  m_dparm.setZero(DPARM_SIZE);\n  \n  m_iparm(IPARM_MODIFY_PARAMETER) = API_NO;\n  pastix(&m_pastixdata, MPI_COMM_WORLD,\n         0, 0, 0, 0,\n         0, 0, 0, 1, m_iparm.data(), m_dparm.data());\n  \n  m_iparm[IPARM_MATRIX_VERIFICATION] = API_NO;\n  m_iparm[IPARM_VERBOSE]             = API_VERBOSE_NOT;\n  m_iparm[IPARM_ORDERING]            = API_ORDER_SCOTCH;\n  m_iparm[IPARM_INCOMPLETE]          = API_NO;\n  m_iparm[IPARM_OOC_LIMIT]           = 2000;\n  m_iparm[IPARM_RHS_MAKING]          = API_RHS_B;\n  m_iparm(IPARM_MATRIX_VERIFICATION) = API_NO;\n  \n  m_iparm(IPARM_START_TASK) = API_TASK_INIT;\n  m_iparm(IPARM_END_TASK) = API_TASK_INIT;\n  internal::eigen_pastix(&m_pastixdata, MPI_COMM_WORLD, 0, 0, 0, (Scalar*)0,\n                         0, 0, 0, 0, m_iparm.data(), m_dparm.data());\n  \n  // Check the returned error\n  if(m_iparm(IPARM_ERROR_NUMBER)) {\n    m_info = InvalidInput;\n    m_initisOk = false;\n  }\n  else { \n    m_info = Success;\n    m_initisOk = true;\n  }\n}\n\ntemplate <class Derived>\nvoid PastixBase<Derived>::compute(ColSpMatrix& mat)\n{\n  eigen_assert(mat.rows() == mat.cols() && \"The input matrix should be squared\");\n  \n  analyzePattern(mat);  \n  factorize(mat);\n  \n  m_iparm(IPARM_MATRIX_VERIFICATION) = API_NO;\n}\n\n\ntemplate <class Derived>\nvoid PastixBase<Derived>::analyzePattern(ColSpMatrix& mat)\n{                         \n  eigen_assert(m_initisOk && \"The initialization of PaSTiX failed\");\n  \n  // clean previous calls\n  if(m_size>0)\n    clean();\n  \n  m_size = internal::convert_index<int>(mat.rows());\n  m_perm.resize(m_size);\n  m_invp.resize(m_size);\n  \n  m_iparm(IPARM_START_TASK) = API_TASK_ORDERING;\n  m_iparm(IPARM_END_TASK) = API_TASK_ANALYSE;\n  internal::eigen_pastix(&m_pastixdata, MPI_COMM_WORLD, m_size, mat.outerIndexPtr(), mat.innerIndexPtr(),\n               mat.valuePtr(), m_perm.data(), m_invp.data(), 0, 0, m_iparm.data(), m_dparm.data());\n  \n  // Check the returned error\n  if(m_iparm(IPARM_ERROR_NUMBER))\n  {\n    m_info = NumericalIssue;\n    m_analysisIsOk = false;\n  }\n  else\n  { \n    m_info = Success;\n    m_analysisIsOk = true;\n  }\n}\n\ntemplate <class Derived>\nvoid PastixBase<Derived>::factorize(ColSpMatrix& mat)\n{\n//   if(&m_cpyMat != &mat) m_cpyMat = mat;\n  eigen_assert(m_analysisIsOk && \"The analysis phase should be called before the factorization phase\");\n  m_iparm(IPARM_START_TASK) = API_TASK_NUMFACT;\n  m_iparm(IPARM_END_TASK) = API_TASK_NUMFACT;\n  m_size = internal::convert_index<int>(mat.rows());\n  \n  internal::eigen_pastix(&m_pastixdata, MPI_COMM_WORLD, m_size, mat.outerIndexPtr(), mat.innerIndexPtr(),\n               mat.valuePtr(), m_perm.data(), m_invp.data(), 0, 0, m_iparm.data(), m_dparm.data());\n  \n  // Check the returned error\n  if(m_iparm(IPARM_ERROR_NUMBER))\n  {\n    m_info = NumericalIssue;\n    m_factorizationIsOk = false;\n    m_isInitialized = false;\n  }\n  else\n  {\n    m_info = Success;\n    m_factorizationIsOk = true;\n    m_isInitialized = true;\n  }\n}\n\n/* Solve the system */\ntemplate<typename Base>\ntemplate<typename Rhs,typename Dest>\nbool PastixBase<Base>::_solve_impl(const MatrixBase<Rhs> &b, MatrixBase<Dest> &x) const\n{\n  eigen_assert(m_isInitialized && \"The matrix should be factorized first\");\n  EIGEN_STATIC_ASSERT((Dest::Flags&RowMajorBit)==0,\n                     THIS_METHOD_IS_ONLY_FOR_COLUMN_MAJOR_MATRICES);\n  int rhs = 1;\n  \n  x = b; /* on return, x is overwritten by the computed solution */\n  \n  for (int i = 0; i < b.cols(); i++){\n    m_iparm[IPARM_START_TASK]          = API_TASK_SOLVE;\n    m_iparm[IPARM_END_TASK]            = API_TASK_REFINE;\n  \n    internal::eigen_pastix(&m_pastixdata, MPI_COMM_WORLD, internal::convert_index<int>(x.rows()), 0, 0, 0,\n                           m_perm.data(), m_invp.data(), &x(0, i), rhs, m_iparm.data(), m_dparm.data());\n  }\n  \n  // Check the returned error\n  m_info = m_iparm(IPARM_ERROR_NUMBER)==0 ? Success : NumericalIssue;\n  \n  return m_iparm(IPARM_ERROR_NUMBER)==0;\n}\n\n/** \\ingroup PaStiXSupport_Module\n  * \\class PastixLU\n  * \\brief Sparse direct LU solver based on PaStiX library\n  * \n  * This class is used to solve the linear systems A.X = B with a supernodal LU \n  * factorization in the PaStiX library. The matrix A should be squared and nonsingular\n  * PaStiX requires that the matrix A has a symmetric structural pattern. \n  * This interface can symmetrize the input matrix otherwise. \n  * The vectors or matrices X and B can be either dense or sparse.\n  * \n  * \\tparam _MatrixType the type of the sparse matrix A, it must be a SparseMatrix<>\n  * \\tparam IsStrSym Indicates if the input matrix has a symmetric pattern, default is false\n  * NOTE : Note that if the analysis and factorization phase are called separately, \n  * the input matrix will be symmetrized at each call, hence it is advised to \n  * symmetrize the matrix in a end-user program and set \\p IsStrSym to true\n  *\n  * \\implsparsesolverconcept\n  *\n  * \\sa \\ref TutorialSparseSolverConcept, class SparseLU\n  * \n  */\ntemplate<typename _MatrixType, bool IsStrSym>\nclass PastixLU : public PastixBase< PastixLU<_MatrixType> >\n{\n  public:\n    typedef _MatrixType MatrixType;\n    typedef PastixBase<PastixLU<MatrixType> > Base;\n    typedef typename Base::ColSpMatrix ColSpMatrix;\n    typedef typename MatrixType::StorageIndex StorageIndex;\n    \n  public:\n    PastixLU() : Base()\n    {\n      init();\n    }\n    \n    explicit PastixLU(const MatrixType& matrix):Base()\n    {\n      init();\n      compute(matrix);\n    }\n    /** Compute the LU supernodal factorization of \\p matrix. \n      * iparm and dparm can be used to tune the PaStiX parameters. \n      * see the PaStiX user's manual\n      * \\sa analyzePattern() factorize()\n      */\n    void compute (const MatrixType& matrix)\n    {\n      m_structureIsUptodate = false;\n      ColSpMatrix temp;\n      grabMatrix(matrix, temp);\n      Base::compute(temp);\n    }\n    /** Compute the LU symbolic factorization of \\p matrix using its sparsity pattern. \n      * Several ordering methods can be used at this step. See the PaStiX user's manual. \n      * The result of this operation can be used with successive matrices having the same pattern as \\p matrix\n      * \\sa factorize()\n      */\n    void analyzePattern(const MatrixType& matrix)\n    {\n      m_structureIsUptodate = false;\n      ColSpMatrix temp;\n      grabMatrix(matrix, temp);\n      Base::analyzePattern(temp);\n    }\n\n    /** Compute the LU supernodal factorization of \\p matrix\n      * WARNING The matrix \\p matrix should have the same structural pattern \n      * as the same used in the analysis phase.\n      * \\sa analyzePattern()\n      */ \n    void factorize(const MatrixType& matrix)\n    {\n      ColSpMatrix temp;\n      grabMatrix(matrix, temp);\n      Base::factorize(temp);\n    }\n  protected:\n    \n    void init()\n    {\n      m_structureIsUptodate = false;\n      m_iparm(IPARM_SYM) = API_SYM_NO;\n      m_iparm(IPARM_FACTORIZATION) = API_FACT_LU;\n    }\n    \n    void grabMatrix(const MatrixType& matrix, ColSpMatrix& out)\n    {\n      if(IsStrSym)\n        out = matrix;\n      else\n      {\n        if(!m_structureIsUptodate)\n        {\n          // update the transposed structure\n          m_transposedStructure = matrix.transpose();\n          \n          // Set the elements of the matrix to zero \n          for (Index j=0; j<m_transposedStructure.outerSize(); ++j) \n            for(typename ColSpMatrix::InnerIterator it(m_transposedStructure, j); it; ++it)\n              it.valueRef() = 0.0;\n\n          m_structureIsUptodate = true;\n        }\n        \n        out = m_transposedStructure + matrix;\n      }\n      internal::c_to_fortran_numbering(out);\n    }\n    \n    using Base::m_iparm;\n    using Base::m_dparm;\n    \n    ColSpMatrix m_transposedStructure;\n    bool m_structureIsUptodate;\n};\n\n/** \\ingroup PaStiXSupport_Module\n  * \\class PastixLLT\n  * \\brief A sparse direct supernodal Cholesky (LLT) factorization and solver based on the PaStiX library\n  * \n  * This class is used to solve the linear systems A.X = B via a LL^T supernodal Cholesky factorization\n  * available in the PaStiX library. The matrix A should be symmetric and positive definite\n  * WARNING Selfadjoint complex matrices are not supported in the current version of PaStiX\n  * The vectors or matrices X and B can be either dense or sparse\n  * \n  * \\tparam MatrixType the type of the sparse matrix A, it must be a SparseMatrix<>\n  * \\tparam UpLo The part of the matrix to use : Lower or Upper. The default is Lower as required by PaStiX\n  *\n  * \\implsparsesolverconcept\n  *\n  * \\sa \\ref TutorialSparseSolverConcept, class SimplicialLLT\n  */\ntemplate<typename _MatrixType, int _UpLo>\nclass PastixLLT : public PastixBase< PastixLLT<_MatrixType, _UpLo> >\n{\n  public:\n    typedef _MatrixType MatrixType;\n    typedef PastixBase<PastixLLT<MatrixType, _UpLo> > Base;\n    typedef typename Base::ColSpMatrix ColSpMatrix;\n    \n  public:\n    enum { UpLo = _UpLo };\n    PastixLLT() : Base()\n    {\n      init();\n    }\n    \n    explicit PastixLLT(const MatrixType& matrix):Base()\n    {\n      init();\n      compute(matrix);\n    }\n\n    /** Compute the L factor of the LL^T supernodal factorization of \\p matrix \n      * \\sa analyzePattern() factorize()\n      */\n    void compute (const MatrixType& matrix)\n    {\n      ColSpMatrix temp;\n      grabMatrix(matrix, temp);\n      Base::compute(temp);\n    }\n\n     /** Compute the LL^T symbolic factorization of \\p matrix using its sparsity pattern\n      * The result of this operation can be used with successive matrices having the same pattern as \\p matrix\n      * \\sa factorize()\n      */\n    void analyzePattern(const MatrixType& matrix)\n    {\n      ColSpMatrix temp;\n      grabMatrix(matrix, temp);\n      Base::analyzePattern(temp);\n    }\n      /** Compute the LL^T supernodal numerical factorization of \\p matrix \n        * \\sa analyzePattern()\n        */\n    void factorize(const MatrixType& matrix)\n    {\n      ColSpMatrix temp;\n      grabMatrix(matrix, temp);\n      Base::factorize(temp);\n    }\n  protected:\n    using Base::m_iparm;\n    \n    void init()\n    {\n      m_iparm(IPARM_SYM) = API_SYM_YES;\n      m_iparm(IPARM_FACTORIZATION) = API_FACT_LLT;\n    }\n    \n    void grabMatrix(const MatrixType& matrix, ColSpMatrix& out)\n    {\n      out.resize(matrix.rows(), matrix.cols());\n      // Pastix supports only lower, column-major matrices \n      out.template selfadjointView<Lower>() = matrix.template selfadjointView<UpLo>();\n      internal::c_to_fortran_numbering(out);\n    }\n};\n\n/** \\ingroup PaStiXSupport_Module\n  * \\class PastixLDLT\n  * \\brief A sparse direct supernodal Cholesky (LLT) factorization and solver based on the PaStiX library\n  * \n  * This class is used to solve the linear systems A.X = B via a LDL^T supernodal Cholesky factorization\n  * available in the PaStiX library. The matrix A should be symmetric and positive definite\n  * WARNING Selfadjoint complex matrices are not supported in the current version of PaStiX\n  * The vectors or matrices X and B can be either dense or sparse\n  * \n  * \\tparam MatrixType the type of the sparse matrix A, it must be a SparseMatrix<>\n  * \\tparam UpLo The part of the matrix to use : Lower or Upper. The default is Lower as required by PaStiX\n  *\n  * \\implsparsesolverconcept\n  *\n  * \\sa \\ref TutorialSparseSolverConcept, class SimplicialLDLT\n  */\ntemplate<typename _MatrixType, int _UpLo>\nclass PastixLDLT : public PastixBase< PastixLDLT<_MatrixType, _UpLo> >\n{\n  public:\n    typedef _MatrixType MatrixType;\n    typedef PastixBase<PastixLDLT<MatrixType, _UpLo> > Base; \n    typedef typename Base::ColSpMatrix ColSpMatrix;\n    \n  public:\n    enum { UpLo = _UpLo };\n    PastixLDLT():Base()\n    {\n      init();\n    }\n    \n    explicit PastixLDLT(const MatrixType& matrix):Base()\n    {\n      init();\n      compute(matrix);\n    }\n\n    /** Compute the L and D factors of the LDL^T factorization of \\p matrix \n      * \\sa analyzePattern() factorize()\n      */\n    void compute (const MatrixType& matrix)\n    {\n      ColSpMatrix temp;\n      grabMatrix(matrix, temp);\n      Base::compute(temp);\n    }\n\n    /** Compute the LDL^T symbolic factorization of \\p matrix using its sparsity pattern\n      * The result of this operation can be used with successive matrices having the same pattern as \\p matrix\n      * \\sa factorize()\n      */\n    void analyzePattern(const MatrixType& matrix)\n    { \n      ColSpMatrix temp;\n      grabMatrix(matrix, temp);\n      Base::analyzePattern(temp);\n    }\n    /** Compute the LDL^T supernodal numerical factorization of \\p matrix \n      * \n      */\n    void factorize(const MatrixType& matrix)\n    {\n      ColSpMatrix temp;\n      grabMatrix(matrix, temp);\n      Base::factorize(temp);\n    }\n\n  protected:\n    using Base::m_iparm;\n    \n    void init()\n    {\n      m_iparm(IPARM_SYM) = API_SYM_YES;\n      m_iparm(IPARM_FACTORIZATION) = API_FACT_LDLT;\n    }\n    \n    void grabMatrix(const MatrixType& matrix, ColSpMatrix& out)\n    {\n      // Pastix supports only lower, column-major matrices \n      out.resize(matrix.rows(), matrix.cols());\n      out.template selfadjointView<Lower>() = matrix.template selfadjointView<UpLo>();\n      internal::c_to_fortran_numbering(out);\n    }\n};\n\n} // end namespace Eigen\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/PardisoSupport/PardisoSupport.h",
    "content": "/*\n Copyright (c) 2011, Intel Corporation. All rights reserved.\n\n Redistribution and use in source and binary forms, with or without modification,\n are permitted provided that the following conditions are met:\n\n * Redistributions of source code must retain the above copyright notice, this\n   list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright notice,\n   this list of conditions and the following disclaimer in the documentation\n   and/or other materials provided with the distribution.\n * Neither the name of Intel Corporation nor the names of its contributors may\n   be used to endorse or promote products derived from this software without\n   specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n ********************************************************************************\n *   Content : Eigen bindings to Intel(R) MKL PARDISO\n ********************************************************************************\n*/\n\n#ifndef EIGEN_PARDISOSUPPORT_H\n#define EIGEN_PARDISOSUPPORT_H\n\nnamespace Eigen { \n\ntemplate<typename _MatrixType> class PardisoLU;\ntemplate<typename _MatrixType, int Options=Upper> class PardisoLLT;\ntemplate<typename _MatrixType, int Options=Upper> class PardisoLDLT;\n\nnamespace internal\n{\n  template<typename IndexType>\n  struct pardiso_run_selector\n  {\n    static IndexType run( _MKL_DSS_HANDLE_t pt, IndexType maxfct, IndexType mnum, IndexType type, IndexType phase, IndexType n, void *a,\n                      IndexType *ia, IndexType *ja, IndexType *perm, IndexType nrhs, IndexType *iparm, IndexType msglvl, void *b, void *x)\n    {\n      IndexType error = 0;\n      ::pardiso(pt, &maxfct, &mnum, &type, &phase, &n, a, ia, ja, perm, &nrhs, iparm, &msglvl, b, x, &error);\n      return error;\n    }\n  };\n  template<>\n  struct pardiso_run_selector<long long int>\n  {\n    typedef long long int IndexType;\n    static IndexType run( _MKL_DSS_HANDLE_t pt, IndexType maxfct, IndexType mnum, IndexType type, IndexType phase, IndexType n, void *a,\n                      IndexType *ia, IndexType *ja, IndexType *perm, IndexType nrhs, IndexType *iparm, IndexType msglvl, void *b, void *x)\n    {\n      IndexType error = 0;\n      ::pardiso_64(pt, &maxfct, &mnum, &type, &phase, &n, a, ia, ja, perm, &nrhs, iparm, &msglvl, b, x, &error);\n      return error;\n    }\n  };\n\n  template<class Pardiso> struct pardiso_traits;\n\n  template<typename _MatrixType>\n  struct pardiso_traits< PardisoLU<_MatrixType> >\n  {\n    typedef _MatrixType MatrixType;\n    typedef typename _MatrixType::Scalar Scalar;\n    typedef typename _MatrixType::RealScalar RealScalar;\n    typedef typename _MatrixType::StorageIndex StorageIndex;\n  };\n\n  template<typename _MatrixType, int Options>\n  struct pardiso_traits< PardisoLLT<_MatrixType, Options> >\n  {\n    typedef _MatrixType MatrixType;\n    typedef typename _MatrixType::Scalar Scalar;\n    typedef typename _MatrixType::RealScalar RealScalar;\n    typedef typename _MatrixType::StorageIndex StorageIndex;\n  };\n\n  template<typename _MatrixType, int Options>\n  struct pardiso_traits< PardisoLDLT<_MatrixType, Options> >\n  {\n    typedef _MatrixType MatrixType;\n    typedef typename _MatrixType::Scalar Scalar;\n    typedef typename _MatrixType::RealScalar RealScalar;\n    typedef typename _MatrixType::StorageIndex StorageIndex;    \n  };\n\n} // end namespace internal\n\ntemplate<class Derived>\nclass PardisoImpl : public SparseSolverBase<Derived>\n{\n  protected:\n    typedef SparseSolverBase<Derived> Base;\n    using Base::derived;\n    using Base::m_isInitialized;\n    \n    typedef internal::pardiso_traits<Derived> Traits;\n  public:\n    using Base::_solve_impl;\n    \n    typedef typename Traits::MatrixType MatrixType;\n    typedef typename Traits::Scalar Scalar;\n    typedef typename Traits::RealScalar RealScalar;\n    typedef typename Traits::StorageIndex StorageIndex;\n    typedef SparseMatrix<Scalar,RowMajor,StorageIndex> SparseMatrixType;\n    typedef Matrix<Scalar,Dynamic,1> VectorType;\n    typedef Matrix<StorageIndex, 1, MatrixType::ColsAtCompileTime> IntRowVectorType;\n    typedef Matrix<StorageIndex, MatrixType::RowsAtCompileTime, 1> IntColVectorType;\n    typedef Array<StorageIndex,64,1,DontAlign> ParameterType;\n    enum {\n      ScalarIsComplex = NumTraits<Scalar>::IsComplex,\n      ColsAtCompileTime = Dynamic,\n      MaxColsAtCompileTime = Dynamic\n    };\n\n    PardisoImpl()\n    {\n      eigen_assert((sizeof(StorageIndex) >= sizeof(_INTEGER_t) && sizeof(StorageIndex) <= 8) && \"Non-supported index type\");\n      m_iparm.setZero();\n      m_msglvl = 0; // No output\n      m_isInitialized = false;\n    }\n\n    ~PardisoImpl()\n    {\n      pardisoRelease();\n    }\n\n    inline Index cols() const { return m_size; }\n    inline Index rows() const { return m_size; }\n  \n    /** \\brief Reports whether previous computation was successful.\n      *\n      * \\returns \\c Success if computation was succesful,\n      *          \\c NumericalIssue if the matrix appears to be negative.\n      */\n    ComputationInfo info() const\n    {\n      eigen_assert(m_isInitialized && \"Decomposition is not initialized.\");\n      return m_info;\n    }\n\n    /** \\warning for advanced usage only.\n      * \\returns a reference to the parameter array controlling PARDISO.\n      * See the PARDISO manual to know how to use it. */\n    ParameterType& pardisoParameterArray()\n    {\n      return m_iparm;\n    }\n    \n    /** Performs a symbolic decomposition on the sparcity of \\a matrix.\n      *\n      * This function is particularly useful when solving for several problems having the same structure.\n      * \n      * \\sa factorize()\n      */\n    Derived& analyzePattern(const MatrixType& matrix);\n    \n    /** Performs a numeric decomposition of \\a matrix\n      *\n      * The given matrix must has the same sparcity than the matrix on which the symbolic decomposition has been performed.\n      *\n      * \\sa analyzePattern()\n      */\n    Derived& factorize(const MatrixType& matrix);\n\n    Derived& compute(const MatrixType& matrix);\n\n    template<typename Rhs,typename Dest>\n    void _solve_impl(const MatrixBase<Rhs> &b, MatrixBase<Dest> &dest) const;\n\n  protected:\n    void pardisoRelease()\n    {\n      if(m_isInitialized) // Factorization ran at least once\n      {\n        internal::pardiso_run_selector<StorageIndex>::run(m_pt, 1, 1, m_type, -1, internal::convert_index<StorageIndex>(m_size),0, 0, 0, m_perm.data(), 0,\n                                                          m_iparm.data(), m_msglvl, NULL, NULL);\n        m_isInitialized = false;\n      }\n    }\n\n    void pardisoInit(int type)\n    {\n      m_type = type;\n      bool symmetric = std::abs(m_type) < 10;\n      m_iparm[0] = 1;   // No solver default\n      m_iparm[1] = 2;   // use Metis for the ordering\n      m_iparm[2] = 0;   // Reserved. Set to zero. (??Numbers of processors, value of OMP_NUM_THREADS??)\n      m_iparm[3] = 0;   // No iterative-direct algorithm\n      m_iparm[4] = 0;   // No user fill-in reducing permutation\n      m_iparm[5] = 0;   // Write solution into x, b is left unchanged\n      m_iparm[6] = 0;   // Not in use\n      m_iparm[7] = 2;   // Max numbers of iterative refinement steps\n      m_iparm[8] = 0;   // Not in use\n      m_iparm[9] = 13;  // Perturb the pivot elements with 1E-13\n      m_iparm[10] = symmetric ? 0 : 1; // Use nonsymmetric permutation and scaling MPS\n      m_iparm[11] = 0;  // Not in use\n      m_iparm[12] = symmetric ? 0 : 1;  // Maximum weighted matching algorithm is switched-off (default for symmetric).\n                                        // Try m_iparm[12] = 1 in case of inappropriate accuracy\n      m_iparm[13] = 0;  // Output: Number of perturbed pivots\n      m_iparm[14] = 0;  // Not in use\n      m_iparm[15] = 0;  // Not in use\n      m_iparm[16] = 0;  // Not in use\n      m_iparm[17] = -1; // Output: Number of nonzeros in the factor LU\n      m_iparm[18] = -1; // Output: Mflops for LU factorization\n      m_iparm[19] = 0;  // Output: Numbers of CG Iterations\n      \n      m_iparm[20] = 0;  // 1x1 pivoting\n      m_iparm[26] = 0;  // No matrix checker\n      m_iparm[27] = (sizeof(RealScalar) == 4) ? 1 : 0;\n      m_iparm[34] = 1;  // C indexing\n      m_iparm[36] = 0;  // CSR\n      m_iparm[59] = 0;  // 0 - In-Core ; 1 - Automatic switch between In-Core and Out-of-Core modes ; 2 - Out-of-Core\n      \n      memset(m_pt, 0, sizeof(m_pt));\n    }\n\n  protected:\n    // cached data to reduce reallocation, etc.\n    \n    void manageErrorCode(Index error) const\n    {\n      switch(error)\n      {\n        case 0:\n          m_info = Success;\n          break;\n        case -4:\n        case -7:\n          m_info = NumericalIssue;\n          break;\n        default:\n          m_info = InvalidInput;\n      }\n    }\n\n    mutable SparseMatrixType m_matrix;\n    mutable ComputationInfo m_info;\n    bool m_analysisIsOk, m_factorizationIsOk;\n    StorageIndex m_type, m_msglvl;\n    mutable void *m_pt[64];\n    mutable ParameterType m_iparm;\n    mutable IntColVectorType m_perm;\n    Index m_size;\n    \n};\n\ntemplate<class Derived>\nDerived& PardisoImpl<Derived>::compute(const MatrixType& a)\n{\n  m_size = a.rows();\n  eigen_assert(a.rows() == a.cols());\n\n  pardisoRelease();\n  m_perm.setZero(m_size);\n  derived().getMatrix(a);\n  \n  Index error;\n  error = internal::pardiso_run_selector<StorageIndex>::run(m_pt, 1, 1, m_type, 12, internal::convert_index<StorageIndex>(m_size),\n                                                            m_matrix.valuePtr(), m_matrix.outerIndexPtr(), m_matrix.innerIndexPtr(),\n                                                            m_perm.data(), 0, m_iparm.data(), m_msglvl, NULL, NULL);\n  manageErrorCode(error);\n  m_analysisIsOk = true;\n  m_factorizationIsOk = true;\n  m_isInitialized = true;\n  return derived();\n}\n\ntemplate<class Derived>\nDerived& PardisoImpl<Derived>::analyzePattern(const MatrixType& a)\n{\n  m_size = a.rows();\n  eigen_assert(m_size == a.cols());\n\n  pardisoRelease();\n  m_perm.setZero(m_size);\n  derived().getMatrix(a);\n  \n  Index error;\n  error = internal::pardiso_run_selector<StorageIndex>::run(m_pt, 1, 1, m_type, 11, internal::convert_index<StorageIndex>(m_size),\n                                                            m_matrix.valuePtr(), m_matrix.outerIndexPtr(), m_matrix.innerIndexPtr(),\n                                                            m_perm.data(), 0, m_iparm.data(), m_msglvl, NULL, NULL);\n  \n  manageErrorCode(error);\n  m_analysisIsOk = true;\n  m_factorizationIsOk = false;\n  m_isInitialized = true;\n  return derived();\n}\n\ntemplate<class Derived>\nDerived& PardisoImpl<Derived>::factorize(const MatrixType& a)\n{\n  eigen_assert(m_analysisIsOk && \"You must first call analyzePattern()\");\n  eigen_assert(m_size == a.rows() && m_size == a.cols());\n  \n  derived().getMatrix(a);\n\n  Index error;\n  error = internal::pardiso_run_selector<StorageIndex>::run(m_pt, 1, 1, m_type, 22, internal::convert_index<StorageIndex>(m_size),\n                                                            m_matrix.valuePtr(), m_matrix.outerIndexPtr(), m_matrix.innerIndexPtr(),\n                                                            m_perm.data(), 0, m_iparm.data(), m_msglvl, NULL, NULL);\n  \n  manageErrorCode(error);\n  m_factorizationIsOk = true;\n  return derived();\n}\n\ntemplate<class Derived>\ntemplate<typename BDerived,typename XDerived>\nvoid PardisoImpl<Derived>::_solve_impl(const MatrixBase<BDerived> &b, MatrixBase<XDerived>& x) const\n{\n  if(m_iparm[0] == 0) // Factorization was not computed\n  {\n    m_info = InvalidInput;\n    return;\n  }\n\n  //Index n = m_matrix.rows();\n  Index nrhs = Index(b.cols());\n  eigen_assert(m_size==b.rows());\n  eigen_assert(((MatrixBase<BDerived>::Flags & RowMajorBit) == 0 || nrhs == 1) && \"Row-major right hand sides are not supported\");\n  eigen_assert(((MatrixBase<XDerived>::Flags & RowMajorBit) == 0 || nrhs == 1) && \"Row-major matrices of unknowns are not supported\");\n  eigen_assert(((nrhs == 1) || b.outerStride() == b.rows()));\n\n\n//  switch (transposed) {\n//    case SvNoTrans    : m_iparm[11] = 0 ; break;\n//    case SvTranspose  : m_iparm[11] = 2 ; break;\n//    case SvAdjoint    : m_iparm[11] = 1 ; break;\n//    default:\n//      //std::cerr << \"Eigen: transposition  option \\\"\" << transposed << \"\\\" not supported by the PARDISO backend\\n\";\n//      m_iparm[11] = 0;\n//  }\n\n  Scalar* rhs_ptr = const_cast<Scalar*>(b.derived().data());\n  Matrix<Scalar,Dynamic,Dynamic,ColMajor> tmp;\n  \n  // Pardiso cannot solve in-place\n  if(rhs_ptr == x.derived().data())\n  {\n    tmp = b;\n    rhs_ptr = tmp.data();\n  }\n  \n  Index error;\n  error = internal::pardiso_run_selector<StorageIndex>::run(m_pt, 1, 1, m_type, 33, internal::convert_index<StorageIndex>(m_size),\n                                                            m_matrix.valuePtr(), m_matrix.outerIndexPtr(), m_matrix.innerIndexPtr(),\n                                                            m_perm.data(), internal::convert_index<StorageIndex>(nrhs), m_iparm.data(), m_msglvl,\n                                                            rhs_ptr, x.derived().data());\n\n  manageErrorCode(error);\n}\n\n\n/** \\ingroup PardisoSupport_Module\n  * \\class PardisoLU\n  * \\brief A sparse direct LU factorization and solver based on the PARDISO library\n  *\n  * This class allows to solve for A.X = B sparse linear problems via a direct LU factorization\n  * using the Intel MKL PARDISO library. The sparse matrix A must be squared and invertible.\n  * The vectors or matrices X and B can be either dense or sparse.\n  *\n  * By default, it runs in in-core mode. To enable PARDISO's out-of-core feature, set:\n  * \\code solver.pardisoParameterArray()[59] = 1; \\endcode\n  *\n  * \\tparam _MatrixType the type of the sparse matrix A, it must be a SparseMatrix<>\n  *\n  * \\implsparsesolverconcept\n  *\n  * \\sa \\ref TutorialSparseSolverConcept, class SparseLU\n  */\ntemplate<typename MatrixType>\nclass PardisoLU : public PardisoImpl< PardisoLU<MatrixType> >\n{\n  protected:\n    typedef PardisoImpl<PardisoLU> Base;\n    typedef typename Base::Scalar Scalar;\n    typedef typename Base::RealScalar RealScalar;\n    using Base::pardisoInit;\n    using Base::m_matrix;\n    friend class PardisoImpl< PardisoLU<MatrixType> >;\n\n  public:\n\n    using Base::compute;\n    using Base::solve;\n\n    PardisoLU()\n      : Base()\n    {\n      pardisoInit(Base::ScalarIsComplex ? 13 : 11);\n    }\n\n    explicit PardisoLU(const MatrixType& matrix)\n      : Base()\n    {\n      pardisoInit(Base::ScalarIsComplex ? 13 : 11);\n      compute(matrix);\n    }\n  protected:\n    void getMatrix(const MatrixType& matrix)\n    {\n      m_matrix = matrix;\n      m_matrix.makeCompressed();\n    }\n};\n\n/** \\ingroup PardisoSupport_Module\n  * \\class PardisoLLT\n  * \\brief A sparse direct Cholesky (LLT) factorization and solver based on the PARDISO library\n  *\n  * This class allows to solve for A.X = B sparse linear problems via a LL^T Cholesky factorization\n  * using the Intel MKL PARDISO library. The sparse matrix A must be selfajoint and positive definite.\n  * The vectors or matrices X and B can be either dense or sparse.\n  *\n  * By default, it runs in in-core mode. To enable PARDISO's out-of-core feature, set:\n  * \\code solver.pardisoParameterArray()[59] = 1; \\endcode\n  *\n  * \\tparam MatrixType the type of the sparse matrix A, it must be a SparseMatrix<>\n  * \\tparam UpLo can be any bitwise combination of Upper, Lower. The default is Upper, meaning only the upper triangular part has to be used.\n  *         Upper|Lower can be used to tell both triangular parts can be used as input.\n  *\n  * \\implsparsesolverconcept\n  *\n  * \\sa \\ref TutorialSparseSolverConcept, class SimplicialLLT\n  */\ntemplate<typename MatrixType, int _UpLo>\nclass PardisoLLT : public PardisoImpl< PardisoLLT<MatrixType,_UpLo> >\n{\n  protected:\n    typedef PardisoImpl< PardisoLLT<MatrixType,_UpLo> > Base;\n    typedef typename Base::Scalar Scalar;\n    typedef typename Base::RealScalar RealScalar;\n    using Base::pardisoInit;\n    using Base::m_matrix;\n    friend class PardisoImpl< PardisoLLT<MatrixType,_UpLo> >;\n\n  public:\n\n    typedef typename Base::StorageIndex StorageIndex;\n    enum { UpLo = _UpLo };\n    using Base::compute;\n\n    PardisoLLT()\n      : Base()\n    {\n      pardisoInit(Base::ScalarIsComplex ? 4 : 2);\n    }\n\n    explicit PardisoLLT(const MatrixType& matrix)\n      : Base()\n    {\n      pardisoInit(Base::ScalarIsComplex ? 4 : 2);\n      compute(matrix);\n    }\n    \n  protected:\n    \n    void getMatrix(const MatrixType& matrix)\n    {\n      // PARDISO supports only upper, row-major matrices\n      PermutationMatrix<Dynamic,Dynamic,StorageIndex> p_null;\n      m_matrix.resize(matrix.rows(), matrix.cols());\n      m_matrix.template selfadjointView<Upper>() = matrix.template selfadjointView<UpLo>().twistedBy(p_null);\n      m_matrix.makeCompressed();\n    }\n};\n\n/** \\ingroup PardisoSupport_Module\n  * \\class PardisoLDLT\n  * \\brief A sparse direct Cholesky (LDLT) factorization and solver based on the PARDISO library\n  *\n  * This class allows to solve for A.X = B sparse linear problems via a LDL^T Cholesky factorization\n  * using the Intel MKL PARDISO library. The sparse matrix A is assumed to be selfajoint and positive definite.\n  * For complex matrices, A can also be symmetric only, see the \\a Options template parameter.\n  * The vectors or matrices X and B can be either dense or sparse.\n  *\n  * By default, it runs in in-core mode. To enable PARDISO's out-of-core feature, set:\n  * \\code solver.pardisoParameterArray()[59] = 1; \\endcode\n  *\n  * \\tparam MatrixType the type of the sparse matrix A, it must be a SparseMatrix<>\n  * \\tparam Options can be any bitwise combination of Upper, Lower, and Symmetric. The default is Upper, meaning only the upper triangular part has to be used.\n  *         Symmetric can be used for symmetric, non-selfadjoint complex matrices, the default being to assume a selfadjoint matrix.\n  *         Upper|Lower can be used to tell both triangular parts can be used as input.\n  *\n  * \\implsparsesolverconcept\n  *\n  * \\sa \\ref TutorialSparseSolverConcept, class SimplicialLDLT\n  */\ntemplate<typename MatrixType, int Options>\nclass PardisoLDLT : public PardisoImpl< PardisoLDLT<MatrixType,Options> >\n{\n  protected:\n    typedef PardisoImpl< PardisoLDLT<MatrixType,Options> > Base;\n    typedef typename Base::Scalar Scalar;\n    typedef typename Base::RealScalar RealScalar;\n    using Base::pardisoInit;\n    using Base::m_matrix;\n    friend class PardisoImpl< PardisoLDLT<MatrixType,Options> >;\n\n  public:\n\n    typedef typename Base::StorageIndex StorageIndex;\n    using Base::compute;\n    enum { UpLo = Options&(Upper|Lower) };\n\n    PardisoLDLT()\n      : Base()\n    {\n      pardisoInit(Base::ScalarIsComplex ? ( bool(Options&Symmetric) ? 6 : -4 ) : -2);\n    }\n\n    explicit PardisoLDLT(const MatrixType& matrix)\n      : Base()\n    {\n      pardisoInit(Base::ScalarIsComplex ? ( bool(Options&Symmetric) ? 6 : -4 ) : -2);\n      compute(matrix);\n    }\n    \n    void getMatrix(const MatrixType& matrix)\n    {\n      // PARDISO supports only upper, row-major matrices\n      PermutationMatrix<Dynamic,Dynamic,StorageIndex> p_null;\n      m_matrix.resize(matrix.rows(), matrix.cols());\n      m_matrix.template selfadjointView<Upper>() = matrix.template selfadjointView<UpLo>().twistedBy(p_null);\n      m_matrix.makeCompressed();\n    }\n};\n\n} // end namespace Eigen\n\n#endif // EIGEN_PARDISOSUPPORT_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/QR/ColPivHouseholderQR.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2009 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_COLPIVOTINGHOUSEHOLDERQR_H\n#define EIGEN_COLPIVOTINGHOUSEHOLDERQR_H\n\nnamespace Eigen {\n\nnamespace internal {\ntemplate<typename _MatrixType> struct traits<ColPivHouseholderQR<_MatrixType> >\n : traits<_MatrixType>\n{\n  enum { Flags = 0 };\n};\n\n} // end namespace internal\n\n/** \\ingroup QR_Module\n  *\n  * \\class ColPivHouseholderQR\n  *\n  * \\brief Householder rank-revealing QR decomposition of a matrix with column-pivoting\n  *\n  * \\tparam _MatrixType the type of the matrix of which we are computing the QR decomposition\n  *\n  * This class performs a rank-revealing QR decomposition of a matrix \\b A into matrices \\b P, \\b Q and \\b R\n  * such that\n  * \\f[\n  *  \\mathbf{A} \\, \\mathbf{P} = \\mathbf{Q} \\, \\mathbf{R}\n  * \\f]\n  * by using Householder transformations. Here, \\b P is a permutation matrix, \\b Q a unitary matrix and \\b R an\n  * upper triangular matrix.\n  *\n  * This decomposition performs column pivoting in order to be rank-revealing and improve\n  * numerical stability. It is slower than HouseholderQR, and faster than FullPivHouseholderQR.\n  *\n  * This class supports the \\link InplaceDecomposition inplace decomposition \\endlink mechanism.\n  * \n  * \\sa MatrixBase::colPivHouseholderQr()\n  */\ntemplate<typename _MatrixType> class ColPivHouseholderQR\n{\n  public:\n\n    typedef _MatrixType MatrixType;\n    enum {\n      RowsAtCompileTime = MatrixType::RowsAtCompileTime,\n      ColsAtCompileTime = MatrixType::ColsAtCompileTime,\n      MaxRowsAtCompileTime = MatrixType::MaxRowsAtCompileTime,\n      MaxColsAtCompileTime = MatrixType::MaxColsAtCompileTime\n    };\n    typedef typename MatrixType::Scalar Scalar;\n    typedef typename MatrixType::RealScalar RealScalar;\n    // FIXME should be int\n    typedef typename MatrixType::StorageIndex StorageIndex;\n    typedef typename internal::plain_diag_type<MatrixType>::type HCoeffsType;\n    typedef PermutationMatrix<ColsAtCompileTime, MaxColsAtCompileTime> PermutationType;\n    typedef typename internal::plain_row_type<MatrixType, Index>::type IntRowVectorType;\n    typedef typename internal::plain_row_type<MatrixType>::type RowVectorType;\n    typedef typename internal::plain_row_type<MatrixType, RealScalar>::type RealRowVectorType;\n    typedef HouseholderSequence<MatrixType,typename internal::remove_all<typename HCoeffsType::ConjugateReturnType>::type> HouseholderSequenceType;\n    typedef typename MatrixType::PlainObject PlainObject;\n\n  private:\n\n    typedef typename PermutationType::StorageIndex PermIndexType;\n\n  public:\n\n    /**\n    * \\brief Default Constructor.\n    *\n    * The default constructor is useful in cases in which the user intends to\n    * perform decompositions via ColPivHouseholderQR::compute(const MatrixType&).\n    */\n    ColPivHouseholderQR()\n      : m_qr(),\n        m_hCoeffs(),\n        m_colsPermutation(),\n        m_colsTranspositions(),\n        m_temp(),\n        m_colNormsUpdated(),\n        m_colNormsDirect(),\n        m_isInitialized(false),\n        m_usePrescribedThreshold(false) {}\n\n    /** \\brief Default Constructor with memory preallocation\n      *\n      * Like the default constructor but with preallocation of the internal data\n      * according to the specified problem \\a size.\n      * \\sa ColPivHouseholderQR()\n      */\n    ColPivHouseholderQR(Index rows, Index cols)\n      : m_qr(rows, cols),\n        m_hCoeffs((std::min)(rows,cols)),\n        m_colsPermutation(PermIndexType(cols)),\n        m_colsTranspositions(cols),\n        m_temp(cols),\n        m_colNormsUpdated(cols),\n        m_colNormsDirect(cols),\n        m_isInitialized(false),\n        m_usePrescribedThreshold(false) {}\n\n    /** \\brief Constructs a QR factorization from a given matrix\n      *\n      * This constructor computes the QR factorization of the matrix \\a matrix by calling\n      * the method compute(). It is a short cut for:\n      *\n      * \\code\n      * ColPivHouseholderQR<MatrixType> qr(matrix.rows(), matrix.cols());\n      * qr.compute(matrix);\n      * \\endcode\n      *\n      * \\sa compute()\n      */\n    template<typename InputType>\n    explicit ColPivHouseholderQR(const EigenBase<InputType>& matrix)\n      : m_qr(matrix.rows(), matrix.cols()),\n        m_hCoeffs((std::min)(matrix.rows(),matrix.cols())),\n        m_colsPermutation(PermIndexType(matrix.cols())),\n        m_colsTranspositions(matrix.cols()),\n        m_temp(matrix.cols()),\n        m_colNormsUpdated(matrix.cols()),\n        m_colNormsDirect(matrix.cols()),\n        m_isInitialized(false),\n        m_usePrescribedThreshold(false)\n    {\n      compute(matrix.derived());\n    }\n\n    /** \\brief Constructs a QR factorization from a given matrix\n      *\n      * This overloaded constructor is provided for \\link InplaceDecomposition inplace decomposition \\endlink when \\c MatrixType is a Eigen::Ref.\n      *\n      * \\sa ColPivHouseholderQR(const EigenBase&)\n      */\n    template<typename InputType>\n    explicit ColPivHouseholderQR(EigenBase<InputType>& matrix)\n      : m_qr(matrix.derived()),\n        m_hCoeffs((std::min)(matrix.rows(),matrix.cols())),\n        m_colsPermutation(PermIndexType(matrix.cols())),\n        m_colsTranspositions(matrix.cols()),\n        m_temp(matrix.cols()),\n        m_colNormsUpdated(matrix.cols()),\n        m_colNormsDirect(matrix.cols()),\n        m_isInitialized(false),\n        m_usePrescribedThreshold(false)\n    {\n      computeInPlace();\n    }\n\n    /** This method finds a solution x to the equation Ax=b, where A is the matrix of which\n      * *this is the QR decomposition, if any exists.\n      *\n      * \\param b the right-hand-side of the equation to solve.\n      *\n      * \\returns a solution.\n      *\n      * \\note_about_checking_solutions\n      *\n      * \\note_about_arbitrary_choice_of_solution\n      *\n      * Example: \\include ColPivHouseholderQR_solve.cpp\n      * Output: \\verbinclude ColPivHouseholderQR_solve.out\n      */\n    template<typename Rhs>\n    inline const Solve<ColPivHouseholderQR, Rhs>\n    solve(const MatrixBase<Rhs>& b) const\n    {\n      eigen_assert(m_isInitialized && \"ColPivHouseholderQR is not initialized.\");\n      return Solve<ColPivHouseholderQR, Rhs>(*this, b.derived());\n    }\n\n    HouseholderSequenceType householderQ() const;\n    HouseholderSequenceType matrixQ() const\n    {\n      return householderQ();\n    }\n\n    /** \\returns a reference to the matrix where the Householder QR decomposition is stored\n      */\n    const MatrixType& matrixQR() const\n    {\n      eigen_assert(m_isInitialized && \"ColPivHouseholderQR is not initialized.\");\n      return m_qr;\n    }\n\n    /** \\returns a reference to the matrix where the result Householder QR is stored\n     * \\warning The strict lower part of this matrix contains internal values.\n     * Only the upper triangular part should be referenced. To get it, use\n     * \\code matrixR().template triangularView<Upper>() \\endcode\n     * For rank-deficient matrices, use\n     * \\code\n     * matrixR().topLeftCorner(rank(), rank()).template triangularView<Upper>()\n     * \\endcode\n     */\n    const MatrixType& matrixR() const\n    {\n      eigen_assert(m_isInitialized && \"ColPivHouseholderQR is not initialized.\");\n      return m_qr;\n    }\n\n    template<typename InputType>\n    ColPivHouseholderQR& compute(const EigenBase<InputType>& matrix);\n\n    /** \\returns a const reference to the column permutation matrix */\n    const PermutationType& colsPermutation() const\n    {\n      eigen_assert(m_isInitialized && \"ColPivHouseholderQR is not initialized.\");\n      return m_colsPermutation;\n    }\n\n    /** \\returns the absolute value of the determinant of the matrix of which\n      * *this is the QR decomposition. It has only linear complexity\n      * (that is, O(n) where n is the dimension of the square matrix)\n      * as the QR decomposition has already been computed.\n      *\n      * \\note This is only for square matrices.\n      *\n      * \\warning a determinant can be very big or small, so for matrices\n      * of large enough dimension, there is a risk of overflow/underflow.\n      * One way to work around that is to use logAbsDeterminant() instead.\n      *\n      * \\sa logAbsDeterminant(), MatrixBase::determinant()\n      */\n    typename MatrixType::RealScalar absDeterminant() const;\n\n    /** \\returns the natural log of the absolute value of the determinant of the matrix of which\n      * *this is the QR decomposition. It has only linear complexity\n      * (that is, O(n) where n is the dimension of the square matrix)\n      * as the QR decomposition has already been computed.\n      *\n      * \\note This is only for square matrices.\n      *\n      * \\note This method is useful to work around the risk of overflow/underflow that's inherent\n      * to determinant computation.\n      *\n      * \\sa absDeterminant(), MatrixBase::determinant()\n      */\n    typename MatrixType::RealScalar logAbsDeterminant() const;\n\n    /** \\returns the rank of the matrix of which *this is the QR decomposition.\n      *\n      * \\note This method has to determine which pivots should be considered nonzero.\n      *       For that, it uses the threshold value that you can control by calling\n      *       setThreshold(const RealScalar&).\n      */\n    inline Index rank() const\n    {\n      using std::abs;\n      eigen_assert(m_isInitialized && \"ColPivHouseholderQR is not initialized.\");\n      RealScalar premultiplied_threshold = abs(m_maxpivot) * threshold();\n      Index result = 0;\n      for(Index i = 0; i < m_nonzero_pivots; ++i)\n        result += (abs(m_qr.coeff(i,i)) > premultiplied_threshold);\n      return result;\n    }\n\n    /** \\returns the dimension of the kernel of the matrix of which *this is the QR decomposition.\n      *\n      * \\note This method has to determine which pivots should be considered nonzero.\n      *       For that, it uses the threshold value that you can control by calling\n      *       setThreshold(const RealScalar&).\n      */\n    inline Index dimensionOfKernel() const\n    {\n      eigen_assert(m_isInitialized && \"ColPivHouseholderQR is not initialized.\");\n      return cols() - rank();\n    }\n\n    /** \\returns true if the matrix of which *this is the QR decomposition represents an injective\n      *          linear map, i.e. has trivial kernel; false otherwise.\n      *\n      * \\note This method has to determine which pivots should be considered nonzero.\n      *       For that, it uses the threshold value that you can control by calling\n      *       setThreshold(const RealScalar&).\n      */\n    inline bool isInjective() const\n    {\n      eigen_assert(m_isInitialized && \"ColPivHouseholderQR is not initialized.\");\n      return rank() == cols();\n    }\n\n    /** \\returns true if the matrix of which *this is the QR decomposition represents a surjective\n      *          linear map; false otherwise.\n      *\n      * \\note This method has to determine which pivots should be considered nonzero.\n      *       For that, it uses the threshold value that you can control by calling\n      *       setThreshold(const RealScalar&).\n      */\n    inline bool isSurjective() const\n    {\n      eigen_assert(m_isInitialized && \"ColPivHouseholderQR is not initialized.\");\n      return rank() == rows();\n    }\n\n    /** \\returns true if the matrix of which *this is the QR decomposition is invertible.\n      *\n      * \\note This method has to determine which pivots should be considered nonzero.\n      *       For that, it uses the threshold value that you can control by calling\n      *       setThreshold(const RealScalar&).\n      */\n    inline bool isInvertible() const\n    {\n      eigen_assert(m_isInitialized && \"ColPivHouseholderQR is not initialized.\");\n      return isInjective() && isSurjective();\n    }\n\n    /** \\returns the inverse of the matrix of which *this is the QR decomposition.\n      *\n      * \\note If this matrix is not invertible, the returned matrix has undefined coefficients.\n      *       Use isInvertible() to first determine whether this matrix is invertible.\n      */\n    inline const Inverse<ColPivHouseholderQR> inverse() const\n    {\n      eigen_assert(m_isInitialized && \"ColPivHouseholderQR is not initialized.\");\n      return Inverse<ColPivHouseholderQR>(*this);\n    }\n\n    inline Index rows() const { return m_qr.rows(); }\n    inline Index cols() const { return m_qr.cols(); }\n\n    /** \\returns a const reference to the vector of Householder coefficients used to represent the factor \\c Q.\n      *\n      * For advanced uses only.\n      */\n    const HCoeffsType& hCoeffs() const { return m_hCoeffs; }\n\n    /** Allows to prescribe a threshold to be used by certain methods, such as rank(),\n      * who need to determine when pivots are to be considered nonzero. This is not used for the\n      * QR decomposition itself.\n      *\n      * When it needs to get the threshold value, Eigen calls threshold(). By default, this\n      * uses a formula to automatically determine a reasonable threshold.\n      * Once you have called the present method setThreshold(const RealScalar&),\n      * your value is used instead.\n      *\n      * \\param threshold The new value to use as the threshold.\n      *\n      * A pivot will be considered nonzero if its absolute value is strictly greater than\n      *  \\f$ \\vert pivot \\vert \\leqslant threshold \\times \\vert maxpivot \\vert \\f$\n      * where maxpivot is the biggest pivot.\n      *\n      * If you want to come back to the default behavior, call setThreshold(Default_t)\n      */\n    ColPivHouseholderQR& setThreshold(const RealScalar& threshold)\n    {\n      m_usePrescribedThreshold = true;\n      m_prescribedThreshold = threshold;\n      return *this;\n    }\n\n    /** Allows to come back to the default behavior, letting Eigen use its default formula for\n      * determining the threshold.\n      *\n      * You should pass the special object Eigen::Default as parameter here.\n      * \\code qr.setThreshold(Eigen::Default); \\endcode\n      *\n      * See the documentation of setThreshold(const RealScalar&).\n      */\n    ColPivHouseholderQR& setThreshold(Default_t)\n    {\n      m_usePrescribedThreshold = false;\n      return *this;\n    }\n\n    /** Returns the threshold that will be used by certain methods such as rank().\n      *\n      * See the documentation of setThreshold(const RealScalar&).\n      */\n    RealScalar threshold() const\n    {\n      eigen_assert(m_isInitialized || m_usePrescribedThreshold);\n      return m_usePrescribedThreshold ? m_prescribedThreshold\n      // this formula comes from experimenting (see \"LU precision tuning\" thread on the list)\n      // and turns out to be identical to Higham's formula used already in LDLt.\n                                      : NumTraits<Scalar>::epsilon() * RealScalar(m_qr.diagonalSize());\n    }\n\n    /** \\returns the number of nonzero pivots in the QR decomposition.\n      * Here nonzero is meant in the exact sense, not in a fuzzy sense.\n      * So that notion isn't really intrinsically interesting, but it is\n      * still useful when implementing algorithms.\n      *\n      * \\sa rank()\n      */\n    inline Index nonzeroPivots() const\n    {\n      eigen_assert(m_isInitialized && \"ColPivHouseholderQR is not initialized.\");\n      return m_nonzero_pivots;\n    }\n\n    /** \\returns the absolute value of the biggest pivot, i.e. the biggest\n      *          diagonal coefficient of R.\n      */\n    RealScalar maxPivot() const { return m_maxpivot; }\n\n    /** \\brief Reports whether the QR factorization was succesful.\n      *\n      * \\note This function always returns \\c Success. It is provided for compatibility\n      * with other factorization routines.\n      * \\returns \\c Success\n      */\n    ComputationInfo info() const\n    {\n      eigen_assert(m_isInitialized && \"Decomposition is not initialized.\");\n      return Success;\n    }\n\n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    template<typename RhsType, typename DstType>\n    EIGEN_DEVICE_FUNC\n    void _solve_impl(const RhsType &rhs, DstType &dst) const;\n    #endif\n\n  protected:\n\n    friend class CompleteOrthogonalDecomposition<MatrixType>;\n\n    static void check_template_parameters()\n    {\n      EIGEN_STATIC_ASSERT_NON_INTEGER(Scalar);\n    }\n\n    void computeInPlace();\n\n    MatrixType m_qr;\n    HCoeffsType m_hCoeffs;\n    PermutationType m_colsPermutation;\n    IntRowVectorType m_colsTranspositions;\n    RowVectorType m_temp;\n    RealRowVectorType m_colNormsUpdated;\n    RealRowVectorType m_colNormsDirect;\n    bool m_isInitialized, m_usePrescribedThreshold;\n    RealScalar m_prescribedThreshold, m_maxpivot;\n    Index m_nonzero_pivots;\n    Index m_det_pq;\n};\n\ntemplate<typename MatrixType>\ntypename MatrixType::RealScalar ColPivHouseholderQR<MatrixType>::absDeterminant() const\n{\n  using std::abs;\n  eigen_assert(m_isInitialized && \"ColPivHouseholderQR is not initialized.\");\n  eigen_assert(m_qr.rows() == m_qr.cols() && \"You can't take the determinant of a non-square matrix!\");\n  return abs(m_qr.diagonal().prod());\n}\n\ntemplate<typename MatrixType>\ntypename MatrixType::RealScalar ColPivHouseholderQR<MatrixType>::logAbsDeterminant() const\n{\n  eigen_assert(m_isInitialized && \"ColPivHouseholderQR is not initialized.\");\n  eigen_assert(m_qr.rows() == m_qr.cols() && \"You can't take the determinant of a non-square matrix!\");\n  return m_qr.diagonal().cwiseAbs().array().log().sum();\n}\n\n/** Performs the QR factorization of the given matrix \\a matrix. The result of\n  * the factorization is stored into \\c *this, and a reference to \\c *this\n  * is returned.\n  *\n  * \\sa class ColPivHouseholderQR, ColPivHouseholderQR(const MatrixType&)\n  */\ntemplate<typename MatrixType>\ntemplate<typename InputType>\nColPivHouseholderQR<MatrixType>& ColPivHouseholderQR<MatrixType>::compute(const EigenBase<InputType>& matrix)\n{\n  m_qr = matrix.derived();\n  computeInPlace();\n  return *this;\n}\n\ntemplate<typename MatrixType>\nvoid ColPivHouseholderQR<MatrixType>::computeInPlace()\n{\n  check_template_parameters();\n\n  // the column permutation is stored as int indices, so just to be sure:\n  eigen_assert(m_qr.cols()<=NumTraits<int>::highest());\n\n  using std::abs;\n\n  Index rows = m_qr.rows();\n  Index cols = m_qr.cols();\n  Index size = m_qr.diagonalSize();\n\n  m_hCoeffs.resize(size);\n\n  m_temp.resize(cols);\n\n  m_colsTranspositions.resize(m_qr.cols());\n  Index number_of_transpositions = 0;\n\n  m_colNormsUpdated.resize(cols);\n  m_colNormsDirect.resize(cols);\n  for (Index k = 0; k < cols; ++k) {\n    // colNormsDirect(k) caches the most recent directly computed norm of\n    // column k.\n    m_colNormsDirect.coeffRef(k) = m_qr.col(k).norm();\n    m_colNormsUpdated.coeffRef(k) = m_colNormsDirect.coeffRef(k);\n  }\n\n  RealScalar threshold_helper =  numext::abs2<Scalar>(m_colNormsUpdated.maxCoeff() * NumTraits<Scalar>::epsilon()) / RealScalar(rows);\n  RealScalar norm_downdate_threshold = numext::sqrt(NumTraits<Scalar>::epsilon());\n\n  m_nonzero_pivots = size; // the generic case is that in which all pivots are nonzero (invertible case)\n  m_maxpivot = RealScalar(0);\n\n  for(Index k = 0; k < size; ++k)\n  {\n    // first, we look up in our table m_colNormsUpdated which column has the biggest norm\n    Index biggest_col_index;\n    RealScalar biggest_col_sq_norm = numext::abs2(m_colNormsUpdated.tail(cols-k).maxCoeff(&biggest_col_index));\n    biggest_col_index += k;\n\n    // Track the number of meaningful pivots but do not stop the decomposition to make\n    // sure that the initial matrix is properly reproduced. See bug 941.\n    if(m_nonzero_pivots==size && biggest_col_sq_norm < threshold_helper * RealScalar(rows-k))\n      m_nonzero_pivots = k;\n\n    // apply the transposition to the columns\n    m_colsTranspositions.coeffRef(k) = biggest_col_index;\n    if(k != biggest_col_index) {\n      m_qr.col(k).swap(m_qr.col(biggest_col_index));\n      std::swap(m_colNormsUpdated.coeffRef(k), m_colNormsUpdated.coeffRef(biggest_col_index));\n      std::swap(m_colNormsDirect.coeffRef(k), m_colNormsDirect.coeffRef(biggest_col_index));\n      ++number_of_transpositions;\n    }\n\n    // generate the householder vector, store it below the diagonal\n    RealScalar beta;\n    m_qr.col(k).tail(rows-k).makeHouseholderInPlace(m_hCoeffs.coeffRef(k), beta);\n\n    // apply the householder transformation to the diagonal coefficient\n    m_qr.coeffRef(k,k) = beta;\n\n    // remember the maximum absolute value of diagonal coefficients\n    if(abs(beta) > m_maxpivot) m_maxpivot = abs(beta);\n\n    // apply the householder transformation\n    m_qr.bottomRightCorner(rows-k, cols-k-1)\n        .applyHouseholderOnTheLeft(m_qr.col(k).tail(rows-k-1), m_hCoeffs.coeffRef(k), &m_temp.coeffRef(k+1));\n\n    // update our table of norms of the columns\n    for (Index j = k + 1; j < cols; ++j) {\n      // The following implements the stable norm downgrade step discussed in\n      // http://www.netlib.org/lapack/lawnspdf/lawn176.pdf\n      // and used in LAPACK routines xGEQPF and xGEQP3.\n      // See lines 278-297 in http://www.netlib.org/lapack/explore-html/dc/df4/sgeqpf_8f_source.html\n      if (m_colNormsUpdated.coeffRef(j) != 0) {\n        RealScalar temp = abs(m_qr.coeffRef(k, j)) / m_colNormsUpdated.coeffRef(j);\n        temp = (RealScalar(1) + temp) * (RealScalar(1) - temp);\n        temp = temp < 0 ? 0 : temp;\n        RealScalar temp2 = temp * numext::abs2<Scalar>(m_colNormsUpdated.coeffRef(j) /\n                                                       m_colNormsDirect.coeffRef(j));\n        if (temp2 <= norm_downdate_threshold) {\n          // The updated norm has become too inaccurate so re-compute the column\n          // norm directly.\n          m_colNormsDirect.coeffRef(j) = m_qr.col(j).tail(rows - k - 1).norm();\n          m_colNormsUpdated.coeffRef(j) = m_colNormsDirect.coeffRef(j);\n        } else {\n          m_colNormsUpdated.coeffRef(j) *= numext::sqrt(temp);\n        }\n      }\n    }\n  }\n\n  m_colsPermutation.setIdentity(PermIndexType(cols));\n  for(PermIndexType k = 0; k < size/*m_nonzero_pivots*/; ++k)\n    m_colsPermutation.applyTranspositionOnTheRight(k, PermIndexType(m_colsTranspositions.coeff(k)));\n\n  m_det_pq = (number_of_transpositions%2) ? -1 : 1;\n  m_isInitialized = true;\n}\n\n#ifndef EIGEN_PARSED_BY_DOXYGEN\ntemplate<typename _MatrixType>\ntemplate<typename RhsType, typename DstType>\nvoid ColPivHouseholderQR<_MatrixType>::_solve_impl(const RhsType &rhs, DstType &dst) const\n{\n  eigen_assert(rhs.rows() == rows());\n\n  const Index nonzero_pivots = nonzeroPivots();\n\n  if(nonzero_pivots == 0)\n  {\n    dst.setZero();\n    return;\n  }\n\n  typename RhsType::PlainObject c(rhs);\n\n  // Note that the matrix Q = H_0^* H_1^*... so its inverse is Q^* = (H_0 H_1 ...)^T\n  c.applyOnTheLeft(householderSequence(m_qr, m_hCoeffs)\n                    .setLength(nonzero_pivots)\n                    .transpose()\n    );\n\n  m_qr.topLeftCorner(nonzero_pivots, nonzero_pivots)\n      .template triangularView<Upper>()\n      .solveInPlace(c.topRows(nonzero_pivots));\n\n  for(Index i = 0; i < nonzero_pivots; ++i) dst.row(m_colsPermutation.indices().coeff(i)) = c.row(i);\n  for(Index i = nonzero_pivots; i < cols(); ++i) dst.row(m_colsPermutation.indices().coeff(i)).setZero();\n}\n#endif\n\nnamespace internal {\n\ntemplate<typename DstXprType, typename MatrixType>\nstruct Assignment<DstXprType, Inverse<ColPivHouseholderQR<MatrixType> >, internal::assign_op<typename DstXprType::Scalar,typename ColPivHouseholderQR<MatrixType>::Scalar>, Dense2Dense>\n{\n  typedef ColPivHouseholderQR<MatrixType> QrType;\n  typedef Inverse<QrType> SrcXprType;\n  static void run(DstXprType &dst, const SrcXprType &src, const internal::assign_op<typename DstXprType::Scalar,typename QrType::Scalar> &)\n  {\n    dst = src.nestedExpression().solve(MatrixType::Identity(src.rows(), src.cols()));\n  }\n};\n\n} // end namespace internal\n\n/** \\returns the matrix Q as a sequence of householder transformations.\n  * You can extract the meaningful part only by using:\n  * \\code qr.householderQ().setLength(qr.nonzeroPivots()) \\endcode*/\ntemplate<typename MatrixType>\ntypename ColPivHouseholderQR<MatrixType>::HouseholderSequenceType ColPivHouseholderQR<MatrixType>\n  ::householderQ() const\n{\n  eigen_assert(m_isInitialized && \"ColPivHouseholderQR is not initialized.\");\n  return HouseholderSequenceType(m_qr, m_hCoeffs.conjugate());\n}\n\n/** \\return the column-pivoting Householder QR decomposition of \\c *this.\n  *\n  * \\sa class ColPivHouseholderQR\n  */\ntemplate<typename Derived>\nconst ColPivHouseholderQR<typename MatrixBase<Derived>::PlainObject>\nMatrixBase<Derived>::colPivHouseholderQr() const\n{\n  return ColPivHouseholderQR<PlainObject>(eval());\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_COLPIVOTINGHOUSEHOLDERQR_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/QR/ColPivHouseholderQR_LAPACKE.h",
    "content": "/*\n Copyright (c) 2011, Intel Corporation. All rights reserved.\n\n Redistribution and use in source and binary forms, with or without modification,\n are permitted provided that the following conditions are met:\n\n * Redistributions of source code must retain the above copyright notice, this\n   list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright notice,\n   this list of conditions and the following disclaimer in the documentation\n   and/or other materials provided with the distribution.\n * Neither the name of Intel Corporation nor the names of its contributors may\n   be used to endorse or promote products derived from this software without\n   specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n ********************************************************************************\n *   Content : Eigen bindings to LAPACKe\n *    Householder QR decomposition of a matrix with column pivoting based on\n *    LAPACKE_?geqp3 function.\n ********************************************************************************\n*/\n\n#ifndef EIGEN_COLPIVOTINGHOUSEHOLDERQR_LAPACKE_H\n#define EIGEN_COLPIVOTINGHOUSEHOLDERQR_LAPACKE_H\n\nnamespace Eigen { \n\n/** \\internal Specialization for the data types supported by LAPACKe */\n\n#define EIGEN_LAPACKE_QR_COLPIV(EIGTYPE, LAPACKE_TYPE, LAPACKE_PREFIX, EIGCOLROW, LAPACKE_COLROW) \\\ntemplate<> template<typename InputType> inline \\\nColPivHouseholderQR<Matrix<EIGTYPE, Dynamic, Dynamic, EIGCOLROW, Dynamic, Dynamic> >& \\\nColPivHouseholderQR<Matrix<EIGTYPE, Dynamic, Dynamic, EIGCOLROW, Dynamic, Dynamic> >::compute( \\\n              const EigenBase<InputType>& matrix) \\\n\\\n{ \\\n  using std::abs; \\\n  typedef Matrix<EIGTYPE, Dynamic, Dynamic, EIGCOLROW, Dynamic, Dynamic> MatrixType; \\\n  typedef MatrixType::RealScalar RealScalar; \\\n  Index rows = matrix.rows();\\\n  Index cols = matrix.cols();\\\n\\\n  m_qr = matrix;\\\n  Index size = m_qr.diagonalSize();\\\n  m_hCoeffs.resize(size);\\\n\\\n  m_colsTranspositions.resize(cols);\\\n  /*Index number_of_transpositions = 0;*/ \\\n\\\n  m_nonzero_pivots = 0; \\\n  m_maxpivot = RealScalar(0);\\\n  m_colsPermutation.resize(cols); \\\n  m_colsPermutation.indices().setZero(); \\\n\\\n  lapack_int lda = internal::convert_index<lapack_int,Index>(m_qr.outerStride()); \\\n  lapack_int matrix_order = LAPACKE_COLROW; \\\n  LAPACKE_##LAPACKE_PREFIX##geqp3( matrix_order, internal::convert_index<lapack_int,Index>(rows), internal::convert_index<lapack_int,Index>(cols), \\\n                              (LAPACKE_TYPE*)m_qr.data(), lda, (lapack_int*)m_colsPermutation.indices().data(), (LAPACKE_TYPE*)m_hCoeffs.data()); \\\n  m_isInitialized = true; \\\n  m_maxpivot=m_qr.diagonal().cwiseAbs().maxCoeff(); \\\n  m_hCoeffs.adjointInPlace(); \\\n  RealScalar premultiplied_threshold = abs(m_maxpivot) * threshold(); \\\n  lapack_int *perm = m_colsPermutation.indices().data(); \\\n  for(Index i=0;i<size;i++) { \\\n    m_nonzero_pivots += (abs(m_qr.coeff(i,i)) > premultiplied_threshold);\\\n  } \\\n  for(Index i=0;i<cols;i++) perm[i]--;\\\n\\\n  /*m_det_pq = (number_of_transpositions%2) ? -1 : 1;  // TODO: It's not needed now; fix upon availability in Eigen */ \\\n\\\n  return *this; \\\n}\n\nEIGEN_LAPACKE_QR_COLPIV(double,   double,        d, ColMajor, LAPACK_COL_MAJOR)\nEIGEN_LAPACKE_QR_COLPIV(float,    float,         s, ColMajor, LAPACK_COL_MAJOR)\nEIGEN_LAPACKE_QR_COLPIV(dcomplex, lapack_complex_double, z, ColMajor, LAPACK_COL_MAJOR)\nEIGEN_LAPACKE_QR_COLPIV(scomplex, lapack_complex_float,  c, ColMajor, LAPACK_COL_MAJOR)\n\nEIGEN_LAPACKE_QR_COLPIV(double,   double,        d, RowMajor, LAPACK_ROW_MAJOR)\nEIGEN_LAPACKE_QR_COLPIV(float,    float,         s, RowMajor, LAPACK_ROW_MAJOR)\nEIGEN_LAPACKE_QR_COLPIV(dcomplex, lapack_complex_double, z, RowMajor, LAPACK_ROW_MAJOR)\nEIGEN_LAPACKE_QR_COLPIV(scomplex, lapack_complex_float,  c, RowMajor, LAPACK_ROW_MAJOR)\n\n} // end namespace Eigen\n\n#endif // EIGEN_COLPIVOTINGHOUSEHOLDERQR_LAPACKE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/QR/CompleteOrthogonalDecomposition.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2016 Rasmus Munk Larsen <rmlarsen@google.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_COMPLETEORTHOGONALDECOMPOSITION_H\n#define EIGEN_COMPLETEORTHOGONALDECOMPOSITION_H\n\nnamespace Eigen {\n\nnamespace internal {\ntemplate <typename _MatrixType>\nstruct traits<CompleteOrthogonalDecomposition<_MatrixType> >\n    : traits<_MatrixType> {\n  enum { Flags = 0 };\n};\n\n}  // end namespace internal\n\n/** \\ingroup QR_Module\n  *\n  * \\class CompleteOrthogonalDecomposition\n  *\n  * \\brief Complete orthogonal decomposition (COD) of a matrix.\n  *\n  * \\param MatrixType the type of the matrix of which we are computing the COD.\n  *\n  * This class performs a rank-revealing complete orthogonal decomposition of a\n  * matrix  \\b A into matrices \\b P, \\b Q, \\b T, and \\b Z such that\n  * \\f[\n  *  \\mathbf{A} \\, \\mathbf{P} = \\mathbf{Q} \\,\n  *                     \\begin{bmatrix} \\mathbf{T} &  \\mathbf{0} \\\\\n  *                                     \\mathbf{0} & \\mathbf{0} \\end{bmatrix} \\, \\mathbf{Z}\n  * \\f]\n  * by using Householder transformations. Here, \\b P is a permutation matrix,\n  * \\b Q and \\b Z are unitary matrices and \\b T an upper triangular matrix of\n  * size rank-by-rank. \\b A may be rank deficient.\n  *\n  * This class supports the \\link InplaceDecomposition inplace decomposition \\endlink mechanism.\n  * \n  * \\sa MatrixBase::completeOrthogonalDecomposition()\n  */\ntemplate <typename _MatrixType>\nclass CompleteOrthogonalDecomposition {\n public:\n  typedef _MatrixType MatrixType;\n  enum {\n    RowsAtCompileTime = MatrixType::RowsAtCompileTime,\n    ColsAtCompileTime = MatrixType::ColsAtCompileTime,\n    MaxRowsAtCompileTime = MatrixType::MaxRowsAtCompileTime,\n    MaxColsAtCompileTime = MatrixType::MaxColsAtCompileTime\n  };\n  typedef typename MatrixType::Scalar Scalar;\n  typedef typename MatrixType::RealScalar RealScalar;\n  typedef typename MatrixType::StorageIndex StorageIndex;\n  typedef typename internal::plain_diag_type<MatrixType>::type HCoeffsType;\n  typedef PermutationMatrix<ColsAtCompileTime, MaxColsAtCompileTime>\n      PermutationType;\n  typedef typename internal::plain_row_type<MatrixType, Index>::type\n      IntRowVectorType;\n  typedef typename internal::plain_row_type<MatrixType>::type RowVectorType;\n  typedef typename internal::plain_row_type<MatrixType, RealScalar>::type\n      RealRowVectorType;\n  typedef HouseholderSequence<\n      MatrixType, typename internal::remove_all<\n                      typename HCoeffsType::ConjugateReturnType>::type>\n      HouseholderSequenceType;\n  typedef typename MatrixType::PlainObject PlainObject;\n\n private:\n  typedef typename PermutationType::Index PermIndexType;\n\n public:\n  /**\n   * \\brief Default Constructor.\n   *\n   * The default constructor is useful in cases in which the user intends to\n   * perform decompositions via\n   * \\c CompleteOrthogonalDecomposition::compute(const* MatrixType&).\n   */\n  CompleteOrthogonalDecomposition() : m_cpqr(), m_zCoeffs(), m_temp() {}\n\n  /** \\brief Default Constructor with memory preallocation\n   *\n   * Like the default constructor but with preallocation of the internal data\n   * according to the specified problem \\a size.\n   * \\sa CompleteOrthogonalDecomposition()\n   */\n  CompleteOrthogonalDecomposition(Index rows, Index cols)\n      : m_cpqr(rows, cols), m_zCoeffs((std::min)(rows, cols)), m_temp(cols) {}\n\n  /** \\brief Constructs a complete orthogonal decomposition from a given\n   * matrix.\n   *\n   * This constructor computes the complete orthogonal decomposition of the\n   * matrix \\a matrix by calling the method compute(). The default\n   * threshold for rank determination will be used. It is a short cut for:\n   *\n   * \\code\n   * CompleteOrthogonalDecomposition<MatrixType> cod(matrix.rows(),\n   *                                                 matrix.cols());\n   * cod.setThreshold(Default);\n   * cod.compute(matrix);\n   * \\endcode\n   *\n   * \\sa compute()\n   */\n  template <typename InputType>\n  explicit CompleteOrthogonalDecomposition(const EigenBase<InputType>& matrix)\n      : m_cpqr(matrix.rows(), matrix.cols()),\n        m_zCoeffs((std::min)(matrix.rows(), matrix.cols())),\n        m_temp(matrix.cols())\n  {\n    compute(matrix.derived());\n  }\n\n  /** \\brief Constructs a complete orthogonal decomposition from a given matrix\n    *\n    * This overloaded constructor is provided for \\link InplaceDecomposition inplace decomposition \\endlink when \\c MatrixType is a Eigen::Ref.\n    *\n    * \\sa CompleteOrthogonalDecomposition(const EigenBase&)\n    */\n  template<typename InputType>\n  explicit CompleteOrthogonalDecomposition(EigenBase<InputType>& matrix)\n    : m_cpqr(matrix.derived()),\n      m_zCoeffs((std::min)(matrix.rows(), matrix.cols())),\n      m_temp(matrix.cols())\n  {\n    computeInPlace();\n  }\n\n\n  /** This method computes the minimum-norm solution X to a least squares\n   * problem \\f[\\mathrm{minimize} \\|A X - B\\|, \\f] where \\b A is the matrix of\n   * which \\c *this is the complete orthogonal decomposition.\n   *\n   * \\param B the right-hand sides of the problem to solve.\n   *\n   * \\returns a solution.\n   *\n   */\n  template <typename Rhs>\n  inline const Solve<CompleteOrthogonalDecomposition, Rhs> solve(\n      const MatrixBase<Rhs>& b) const {\n    eigen_assert(m_cpqr.m_isInitialized &&\n                 \"CompleteOrthogonalDecomposition is not initialized.\");\n    return Solve<CompleteOrthogonalDecomposition, Rhs>(*this, b.derived());\n  }\n\n  HouseholderSequenceType householderQ(void) const;\n  HouseholderSequenceType matrixQ(void) const { return m_cpqr.householderQ(); }\n\n  /** \\returns the matrix \\b Z.\n   */\n  MatrixType matrixZ() const {\n    MatrixType Z = MatrixType::Identity(m_cpqr.cols(), m_cpqr.cols());\n    applyZAdjointOnTheLeftInPlace(Z);\n    return Z.adjoint();\n  }\n\n  /** \\returns a reference to the matrix where the complete orthogonal\n   * decomposition is stored\n   */\n  const MatrixType& matrixQTZ() const { return m_cpqr.matrixQR(); }\n\n  /** \\returns a reference to the matrix where the complete orthogonal\n   * decomposition is stored.\n   * \\warning The strict lower part and \\code cols() - rank() \\endcode right\n   * columns of this matrix contains internal values.\n   * Only the upper triangular part should be referenced. To get it, use\n   * \\code matrixT().template triangularView<Upper>() \\endcode\n   * For rank-deficient matrices, use\n   * \\code\n   * matrixR().topLeftCorner(rank(), rank()).template triangularView<Upper>()\n   * \\endcode\n   */\n  const MatrixType& matrixT() const { return m_cpqr.matrixQR(); }\n\n  template <typename InputType>\n  CompleteOrthogonalDecomposition& compute(const EigenBase<InputType>& matrix) {\n    // Compute the column pivoted QR factorization A P = Q R.\n    m_cpqr.compute(matrix);\n    computeInPlace();\n    return *this;\n  }\n\n  /** \\returns a const reference to the column permutation matrix */\n  const PermutationType& colsPermutation() const {\n    return m_cpqr.colsPermutation();\n  }\n\n  /** \\returns the absolute value of the determinant of the matrix of which\n   * *this is the complete orthogonal decomposition. It has only linear\n   * complexity (that is, O(n) where n is the dimension of the square matrix)\n   * as the complete orthogonal decomposition has already been computed.\n   *\n   * \\note This is only for square matrices.\n   *\n   * \\warning a determinant can be very big or small, so for matrices\n   * of large enough dimension, there is a risk of overflow/underflow.\n   * One way to work around that is to use logAbsDeterminant() instead.\n   *\n   * \\sa logAbsDeterminant(), MatrixBase::determinant()\n   */\n  typename MatrixType::RealScalar absDeterminant() const;\n\n  /** \\returns the natural log of the absolute value of the determinant of the\n   * matrix of which *this is the complete orthogonal decomposition. It has\n   * only linear complexity (that is, O(n) where n is the dimension of the\n   * square matrix) as the complete orthogonal decomposition has already been\n   * computed.\n   *\n   * \\note This is only for square matrices.\n   *\n   * \\note This method is useful to work around the risk of overflow/underflow\n   * that's inherent to determinant computation.\n   *\n   * \\sa absDeterminant(), MatrixBase::determinant()\n   */\n  typename MatrixType::RealScalar logAbsDeterminant() const;\n\n  /** \\returns the rank of the matrix of which *this is the complete orthogonal\n   * decomposition.\n   *\n   * \\note This method has to determine which pivots should be considered\n   * nonzero. For that, it uses the threshold value that you can control by\n   * calling setThreshold(const RealScalar&).\n   */\n  inline Index rank() const { return m_cpqr.rank(); }\n\n  /** \\returns the dimension of the kernel of the matrix of which *this is the\n   * complete orthogonal decomposition.\n   *\n   * \\note This method has to determine which pivots should be considered\n   * nonzero. For that, it uses the threshold value that you can control by\n   * calling setThreshold(const RealScalar&).\n   */\n  inline Index dimensionOfKernel() const { return m_cpqr.dimensionOfKernel(); }\n\n  /** \\returns true if the matrix of which *this is the decomposition represents\n   * an injective linear map, i.e. has trivial kernel; false otherwise.\n   *\n   * \\note This method has to determine which pivots should be considered\n   * nonzero. For that, it uses the threshold value that you can control by\n   * calling setThreshold(const RealScalar&).\n   */\n  inline bool isInjective() const { return m_cpqr.isInjective(); }\n\n  /** \\returns true if the matrix of which *this is the decomposition represents\n   * a surjective linear map; false otherwise.\n   *\n   * \\note This method has to determine which pivots should be considered\n   * nonzero. For that, it uses the threshold value that you can control by\n   * calling setThreshold(const RealScalar&).\n   */\n  inline bool isSurjective() const { return m_cpqr.isSurjective(); }\n\n  /** \\returns true if the matrix of which *this is the complete orthogonal\n   * decomposition is invertible.\n   *\n   * \\note This method has to determine which pivots should be considered\n   * nonzero. For that, it uses the threshold value that you can control by\n   * calling setThreshold(const RealScalar&).\n   */\n  inline bool isInvertible() const { return m_cpqr.isInvertible(); }\n\n  /** \\returns the pseudo-inverse of the matrix of which *this is the complete\n   * orthogonal decomposition.\n   * \\warning: Do not compute \\c this->pseudoInverse()*rhs to solve a linear systems.\n   * It is more efficient and numerically stable to call \\c this->solve(rhs).\n   */\n  inline const Inverse<CompleteOrthogonalDecomposition> pseudoInverse() const\n  {\n    return Inverse<CompleteOrthogonalDecomposition>(*this);\n  }\n\n  inline Index rows() const { return m_cpqr.rows(); }\n  inline Index cols() const { return m_cpqr.cols(); }\n\n  /** \\returns a const reference to the vector of Householder coefficients used\n   * to represent the factor \\c Q.\n   *\n   * For advanced uses only.\n   */\n  inline const HCoeffsType& hCoeffs() const { return m_cpqr.hCoeffs(); }\n\n  /** \\returns a const reference to the vector of Householder coefficients\n   * used to represent the factor \\c Z.\n   *\n   * For advanced uses only.\n   */\n  const HCoeffsType& zCoeffs() const { return m_zCoeffs; }\n\n  /** Allows to prescribe a threshold to be used by certain methods, such as\n   * rank(), who need to determine when pivots are to be considered nonzero.\n   * Most be called before calling compute().\n   *\n   * When it needs to get the threshold value, Eigen calls threshold(). By\n   * default, this uses a formula to automatically determine a reasonable\n   * threshold. Once you have called the present method\n   * setThreshold(const RealScalar&), your value is used instead.\n   *\n   * \\param threshold The new value to use as the threshold.\n   *\n   * A pivot will be considered nonzero if its absolute value is strictly\n   * greater than\n   *  \\f$ \\vert pivot \\vert \\leqslant threshold \\times \\vert maxpivot \\vert \\f$\n   * where maxpivot is the biggest pivot.\n   *\n   * If you want to come back to the default behavior, call\n   * setThreshold(Default_t)\n   */\n  CompleteOrthogonalDecomposition& setThreshold(const RealScalar& threshold) {\n    m_cpqr.setThreshold(threshold);\n    return *this;\n  }\n\n  /** Allows to come back to the default behavior, letting Eigen use its default\n   * formula for determining the threshold.\n   *\n   * You should pass the special object Eigen::Default as parameter here.\n   * \\code qr.setThreshold(Eigen::Default); \\endcode\n   *\n   * See the documentation of setThreshold(const RealScalar&).\n   */\n  CompleteOrthogonalDecomposition& setThreshold(Default_t) {\n    m_cpqr.setThreshold(Default);\n    return *this;\n  }\n\n  /** Returns the threshold that will be used by certain methods such as rank().\n   *\n   * See the documentation of setThreshold(const RealScalar&).\n   */\n  RealScalar threshold() const { return m_cpqr.threshold(); }\n\n  /** \\returns the number of nonzero pivots in the complete orthogonal\n   * decomposition. Here nonzero is meant in the exact sense, not in a\n   * fuzzy sense. So that notion isn't really intrinsically interesting,\n   * but it is still useful when implementing algorithms.\n   *\n   * \\sa rank()\n   */\n  inline Index nonzeroPivots() const { return m_cpqr.nonzeroPivots(); }\n\n  /** \\returns the absolute value of the biggest pivot, i.e. the biggest\n   *          diagonal coefficient of R.\n   */\n  inline RealScalar maxPivot() const { return m_cpqr.maxPivot(); }\n\n  /** \\brief Reports whether the complete orthogonal decomposition was\n   * succesful.\n   *\n   * \\note This function always returns \\c Success. It is provided for\n   * compatibility\n   * with other factorization routines.\n   * \\returns \\c Success\n   */\n  ComputationInfo info() const {\n    eigen_assert(m_cpqr.m_isInitialized && \"Decomposition is not initialized.\");\n    return Success;\n  }\n\n#ifndef EIGEN_PARSED_BY_DOXYGEN\n  template <typename RhsType, typename DstType>\n  EIGEN_DEVICE_FUNC void _solve_impl(const RhsType& rhs, DstType& dst) const;\n#endif\n\n protected:\n  static void check_template_parameters() {\n    EIGEN_STATIC_ASSERT_NON_INTEGER(Scalar);\n  }\n\n  void computeInPlace();\n\n  /** Overwrites \\b rhs with \\f$ \\mathbf{Z}^* * \\mathbf{rhs} \\f$.\n   */\n  template <typename Rhs>\n  void applyZAdjointOnTheLeftInPlace(Rhs& rhs) const;\n\n  ColPivHouseholderQR<MatrixType> m_cpqr;\n  HCoeffsType m_zCoeffs;\n  RowVectorType m_temp;\n};\n\ntemplate <typename MatrixType>\ntypename MatrixType::RealScalar\nCompleteOrthogonalDecomposition<MatrixType>::absDeterminant() const {\n  return m_cpqr.absDeterminant();\n}\n\ntemplate <typename MatrixType>\ntypename MatrixType::RealScalar\nCompleteOrthogonalDecomposition<MatrixType>::logAbsDeterminant() const {\n  return m_cpqr.logAbsDeterminant();\n}\n\n/** Performs the complete orthogonal decomposition of the given matrix \\a\n * matrix. The result of the factorization is stored into \\c *this, and a\n * reference to \\c *this is returned.\n *\n * \\sa class CompleteOrthogonalDecomposition,\n * CompleteOrthogonalDecomposition(const MatrixType&)\n */\ntemplate <typename MatrixType>\nvoid CompleteOrthogonalDecomposition<MatrixType>::computeInPlace()\n{\n  check_template_parameters();\n\n  // the column permutation is stored as int indices, so just to be sure:\n  eigen_assert(m_cpqr.cols() <= NumTraits<int>::highest());\n\n  const Index rank = m_cpqr.rank();\n  const Index cols = m_cpqr.cols();\n  const Index rows = m_cpqr.rows();\n  m_zCoeffs.resize((std::min)(rows, cols));\n  m_temp.resize(cols);\n\n  if (rank < cols) {\n    // We have reduced the (permuted) matrix to the form\n    //   [R11 R12]\n    //   [ 0  R22]\n    // where R11 is r-by-r (r = rank) upper triangular, R12 is\n    // r-by-(n-r), and R22 is empty or the norm of R22 is negligible.\n    // We now compute the complete orthogonal decomposition by applying\n    // Householder transformations from the right to the upper trapezoidal\n    // matrix X = [R11 R12] to zero out R12 and obtain the factorization\n    // [R11 R12] = [T11 0] * Z, where T11 is r-by-r upper triangular and\n    // Z = Z(0) * Z(1) ... Z(r-1) is an n-by-n orthogonal matrix.\n    // We store the data representing Z in R12 and m_zCoeffs.\n    for (Index k = rank - 1; k >= 0; --k) {\n      if (k != rank - 1) {\n        // Given the API for Householder reflectors, it is more convenient if\n        // we swap the leading parts of columns k and r-1 (zero-based) to form\n        // the matrix X_k = [X(0:k, k), X(0:k, r:n)]\n        m_cpqr.m_qr.col(k).head(k + 1).swap(\n            m_cpqr.m_qr.col(rank - 1).head(k + 1));\n      }\n      // Construct Householder reflector Z(k) to zero out the last row of X_k,\n      // i.e. choose Z(k) such that\n      // [X(k, k), X(k, r:n)] * Z(k) = [beta, 0, .., 0].\n      RealScalar beta;\n      m_cpqr.m_qr.row(k)\n          .tail(cols - rank + 1)\n          .makeHouseholderInPlace(m_zCoeffs(k), beta);\n      m_cpqr.m_qr(k, rank - 1) = beta;\n      if (k > 0) {\n        // Apply Z(k) to the first k rows of X_k\n        m_cpqr.m_qr.topRightCorner(k, cols - rank + 1)\n            .applyHouseholderOnTheRight(\n                m_cpqr.m_qr.row(k).tail(cols - rank).transpose(), m_zCoeffs(k),\n                &m_temp(0));\n      }\n      if (k != rank - 1) {\n        // Swap X(0:k,k) back to its proper location.\n        m_cpqr.m_qr.col(k).head(k + 1).swap(\n            m_cpqr.m_qr.col(rank - 1).head(k + 1));\n      }\n    }\n  }\n}\n\ntemplate <typename MatrixType>\ntemplate <typename Rhs>\nvoid CompleteOrthogonalDecomposition<MatrixType>::applyZAdjointOnTheLeftInPlace(\n    Rhs& rhs) const {\n  const Index cols = this->cols();\n  const Index nrhs = rhs.cols();\n  const Index rank = this->rank();\n  Matrix<typename MatrixType::Scalar, Dynamic, 1> temp((std::max)(cols, nrhs));\n  for (Index k = 0; k < rank; ++k) {\n    if (k != rank - 1) {\n      rhs.row(k).swap(rhs.row(rank - 1));\n    }\n    rhs.middleRows(rank - 1, cols - rank + 1)\n        .applyHouseholderOnTheLeft(\n            matrixQTZ().row(k).tail(cols - rank).adjoint(), zCoeffs()(k),\n            &temp(0));\n    if (k != rank - 1) {\n      rhs.row(k).swap(rhs.row(rank - 1));\n    }\n  }\n}\n\n#ifndef EIGEN_PARSED_BY_DOXYGEN\ntemplate <typename _MatrixType>\ntemplate <typename RhsType, typename DstType>\nvoid CompleteOrthogonalDecomposition<_MatrixType>::_solve_impl(\n    const RhsType& rhs, DstType& dst) const {\n  eigen_assert(rhs.rows() == this->rows());\n\n  const Index rank = this->rank();\n  if (rank == 0) {\n    dst.setZero();\n    return;\n  }\n\n  // Compute c = Q^* * rhs\n  // Note that the matrix Q = H_0^* H_1^*... so its inverse is\n  // Q^* = (H_0 H_1 ...)^T\n  typename RhsType::PlainObject c(rhs);\n  c.applyOnTheLeft(\n      householderSequence(matrixQTZ(), hCoeffs()).setLength(rank).transpose());\n\n  // Solve T z = c(1:rank, :)\n  dst.topRows(rank) = matrixT()\n                          .topLeftCorner(rank, rank)\n                          .template triangularView<Upper>()\n                          .solve(c.topRows(rank));\n\n  const Index cols = this->cols();\n  if (rank < cols) {\n    // Compute y = Z^* * [ z ]\n    //                   [ 0 ]\n    dst.bottomRows(cols - rank).setZero();\n    applyZAdjointOnTheLeftInPlace(dst);\n  }\n\n  // Undo permutation to get x = P^{-1} * y.\n  dst = colsPermutation() * dst;\n}\n#endif\n\nnamespace internal {\n\ntemplate<typename DstXprType, typename MatrixType>\nstruct Assignment<DstXprType, Inverse<CompleteOrthogonalDecomposition<MatrixType> >, internal::assign_op<typename DstXprType::Scalar,typename CompleteOrthogonalDecomposition<MatrixType>::Scalar>, Dense2Dense>\n{\n  typedef CompleteOrthogonalDecomposition<MatrixType> CodType;\n  typedef Inverse<CodType> SrcXprType;\n  static void run(DstXprType &dst, const SrcXprType &src, const internal::assign_op<typename DstXprType::Scalar,typename CodType::Scalar> &)\n  {\n    dst = src.nestedExpression().solve(MatrixType::Identity(src.rows(), src.rows()));\n  }\n};\n\n} // end namespace internal\n\n/** \\returns the matrix Q as a sequence of householder transformations */\ntemplate <typename MatrixType>\ntypename CompleteOrthogonalDecomposition<MatrixType>::HouseholderSequenceType\nCompleteOrthogonalDecomposition<MatrixType>::householderQ() const {\n  return m_cpqr.householderQ();\n}\n\n/** \\return the complete orthogonal decomposition of \\c *this.\n  *\n  * \\sa class CompleteOrthogonalDecomposition\n  */\ntemplate <typename Derived>\nconst CompleteOrthogonalDecomposition<typename MatrixBase<Derived>::PlainObject>\nMatrixBase<Derived>::completeOrthogonalDecomposition() const {\n  return CompleteOrthogonalDecomposition<PlainObject>(eval());\n}\n\n}  // end namespace Eigen\n\n#endif  // EIGEN_COMPLETEORTHOGONALDECOMPOSITION_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/QR/FullPivHouseholderQR.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2009 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_FULLPIVOTINGHOUSEHOLDERQR_H\n#define EIGEN_FULLPIVOTINGHOUSEHOLDERQR_H\n\nnamespace Eigen { \n\nnamespace internal {\n\ntemplate<typename _MatrixType> struct traits<FullPivHouseholderQR<_MatrixType> >\n : traits<_MatrixType>\n{\n  enum { Flags = 0 };\n};\n\ntemplate<typename MatrixType> struct FullPivHouseholderQRMatrixQReturnType;\n\ntemplate<typename MatrixType>\nstruct traits<FullPivHouseholderQRMatrixQReturnType<MatrixType> >\n{\n  typedef typename MatrixType::PlainObject ReturnType;\n};\n\n} // end namespace internal\n\n/** \\ingroup QR_Module\n  *\n  * \\class FullPivHouseholderQR\n  *\n  * \\brief Householder rank-revealing QR decomposition of a matrix with full pivoting\n  *\n  * \\tparam _MatrixType the type of the matrix of which we are computing the QR decomposition\n  *\n  * This class performs a rank-revealing QR decomposition of a matrix \\b A into matrices \\b P, \\b P', \\b Q and \\b R\n  * such that \n  * \\f[\n  *  \\mathbf{P} \\, \\mathbf{A} \\, \\mathbf{P}' = \\mathbf{Q} \\, \\mathbf{R}\n  * \\f]\n  * by using Householder transformations. Here, \\b P and \\b P' are permutation matrices, \\b Q a unitary matrix \n  * and \\b R an upper triangular matrix.\n  *\n  * This decomposition performs a very prudent full pivoting in order to be rank-revealing and achieve optimal\n  * numerical stability. The trade-off is that it is slower than HouseholderQR and ColPivHouseholderQR.\n  *\n  * This class supports the \\link InplaceDecomposition inplace decomposition \\endlink mechanism.\n  * \n  * \\sa MatrixBase::fullPivHouseholderQr()\n  */\ntemplate<typename _MatrixType> class FullPivHouseholderQR\n{\n  public:\n\n    typedef _MatrixType MatrixType;\n    enum {\n      RowsAtCompileTime = MatrixType::RowsAtCompileTime,\n      ColsAtCompileTime = MatrixType::ColsAtCompileTime,\n      MaxRowsAtCompileTime = MatrixType::MaxRowsAtCompileTime,\n      MaxColsAtCompileTime = MatrixType::MaxColsAtCompileTime\n    };\n    typedef typename MatrixType::Scalar Scalar;\n    typedef typename MatrixType::RealScalar RealScalar;\n    // FIXME should be int\n    typedef typename MatrixType::StorageIndex StorageIndex;\n    typedef internal::FullPivHouseholderQRMatrixQReturnType<MatrixType> MatrixQReturnType;\n    typedef typename internal::plain_diag_type<MatrixType>::type HCoeffsType;\n    typedef Matrix<StorageIndex, 1,\n                   EIGEN_SIZE_MIN_PREFER_DYNAMIC(ColsAtCompileTime,RowsAtCompileTime), RowMajor, 1,\n                   EIGEN_SIZE_MIN_PREFER_FIXED(MaxColsAtCompileTime,MaxRowsAtCompileTime)> IntDiagSizeVectorType;\n    typedef PermutationMatrix<ColsAtCompileTime, MaxColsAtCompileTime> PermutationType;\n    typedef typename internal::plain_row_type<MatrixType>::type RowVectorType;\n    typedef typename internal::plain_col_type<MatrixType>::type ColVectorType;\n    typedef typename MatrixType::PlainObject PlainObject;\n\n    /** \\brief Default Constructor.\n      *\n      * The default constructor is useful in cases in which the user intends to\n      * perform decompositions via FullPivHouseholderQR::compute(const MatrixType&).\n      */\n    FullPivHouseholderQR()\n      : m_qr(),\n        m_hCoeffs(),\n        m_rows_transpositions(),\n        m_cols_transpositions(),\n        m_cols_permutation(),\n        m_temp(),\n        m_isInitialized(false),\n        m_usePrescribedThreshold(false) {}\n\n    /** \\brief Default Constructor with memory preallocation\n      *\n      * Like the default constructor but with preallocation of the internal data\n      * according to the specified problem \\a size.\n      * \\sa FullPivHouseholderQR()\n      */\n    FullPivHouseholderQR(Index rows, Index cols)\n      : m_qr(rows, cols),\n        m_hCoeffs((std::min)(rows,cols)),\n        m_rows_transpositions((std::min)(rows,cols)),\n        m_cols_transpositions((std::min)(rows,cols)),\n        m_cols_permutation(cols),\n        m_temp(cols),\n        m_isInitialized(false),\n        m_usePrescribedThreshold(false) {}\n\n    /** \\brief Constructs a QR factorization from a given matrix\n      *\n      * This constructor computes the QR factorization of the matrix \\a matrix by calling\n      * the method compute(). It is a short cut for:\n      * \n      * \\code\n      * FullPivHouseholderQR<MatrixType> qr(matrix.rows(), matrix.cols());\n      * qr.compute(matrix);\n      * \\endcode\n      * \n      * \\sa compute()\n      */\n    template<typename InputType>\n    explicit FullPivHouseholderQR(const EigenBase<InputType>& matrix)\n      : m_qr(matrix.rows(), matrix.cols()),\n        m_hCoeffs((std::min)(matrix.rows(), matrix.cols())),\n        m_rows_transpositions((std::min)(matrix.rows(), matrix.cols())),\n        m_cols_transpositions((std::min)(matrix.rows(), matrix.cols())),\n        m_cols_permutation(matrix.cols()),\n        m_temp(matrix.cols()),\n        m_isInitialized(false),\n        m_usePrescribedThreshold(false)\n    {\n      compute(matrix.derived());\n    }\n\n    /** \\brief Constructs a QR factorization from a given matrix\n      *\n      * This overloaded constructor is provided for \\link InplaceDecomposition inplace decomposition \\endlink when \\c MatrixType is a Eigen::Ref.\n      *\n      * \\sa FullPivHouseholderQR(const EigenBase&)\n      */\n    template<typename InputType>\n    explicit FullPivHouseholderQR(EigenBase<InputType>& matrix)\n      : m_qr(matrix.derived()),\n        m_hCoeffs((std::min)(matrix.rows(), matrix.cols())),\n        m_rows_transpositions((std::min)(matrix.rows(), matrix.cols())),\n        m_cols_transpositions((std::min)(matrix.rows(), matrix.cols())),\n        m_cols_permutation(matrix.cols()),\n        m_temp(matrix.cols()),\n        m_isInitialized(false),\n        m_usePrescribedThreshold(false)\n    {\n      computeInPlace();\n    }\n\n    /** This method finds a solution x to the equation Ax=b, where A is the matrix of which\n      * \\c *this is the QR decomposition.\n      *\n      * \\param b the right-hand-side of the equation to solve.\n      *\n      * \\returns the exact or least-square solution if the rank is greater or equal to the number of columns of A,\n      * and an arbitrary solution otherwise.\n      *\n      * \\note_about_checking_solutions\n      *\n      * \\note_about_arbitrary_choice_of_solution\n      *\n      * Example: \\include FullPivHouseholderQR_solve.cpp\n      * Output: \\verbinclude FullPivHouseholderQR_solve.out\n      */\n    template<typename Rhs>\n    inline const Solve<FullPivHouseholderQR, Rhs>\n    solve(const MatrixBase<Rhs>& b) const\n    {\n      eigen_assert(m_isInitialized && \"FullPivHouseholderQR is not initialized.\");\n      return Solve<FullPivHouseholderQR, Rhs>(*this, b.derived());\n    }\n\n    /** \\returns Expression object representing the matrix Q\n      */\n    MatrixQReturnType matrixQ(void) const;\n\n    /** \\returns a reference to the matrix where the Householder QR decomposition is stored\n      */\n    const MatrixType& matrixQR() const\n    {\n      eigen_assert(m_isInitialized && \"FullPivHouseholderQR is not initialized.\");\n      return m_qr;\n    }\n\n    template<typename InputType>\n    FullPivHouseholderQR& compute(const EigenBase<InputType>& matrix);\n\n    /** \\returns a const reference to the column permutation matrix */\n    const PermutationType& colsPermutation() const\n    {\n      eigen_assert(m_isInitialized && \"FullPivHouseholderQR is not initialized.\");\n      return m_cols_permutation;\n    }\n\n    /** \\returns a const reference to the vector of indices representing the rows transpositions */\n    const IntDiagSizeVectorType& rowsTranspositions() const\n    {\n      eigen_assert(m_isInitialized && \"FullPivHouseholderQR is not initialized.\");\n      return m_rows_transpositions;\n    }\n\n    /** \\returns the absolute value of the determinant of the matrix of which\n      * *this is the QR decomposition. It has only linear complexity\n      * (that is, O(n) where n is the dimension of the square matrix)\n      * as the QR decomposition has already been computed.\n      *\n      * \\note This is only for square matrices.\n      *\n      * \\warning a determinant can be very big or small, so for matrices\n      * of large enough dimension, there is a risk of overflow/underflow.\n      * One way to work around that is to use logAbsDeterminant() instead.\n      *\n      * \\sa logAbsDeterminant(), MatrixBase::determinant()\n      */\n    typename MatrixType::RealScalar absDeterminant() const;\n\n    /** \\returns the natural log of the absolute value of the determinant of the matrix of which\n      * *this is the QR decomposition. It has only linear complexity\n      * (that is, O(n) where n is the dimension of the square matrix)\n      * as the QR decomposition has already been computed.\n      *\n      * \\note This is only for square matrices.\n      *\n      * \\note This method is useful to work around the risk of overflow/underflow that's inherent\n      * to determinant computation.\n      *\n      * \\sa absDeterminant(), MatrixBase::determinant()\n      */\n    typename MatrixType::RealScalar logAbsDeterminant() const;\n\n    /** \\returns the rank of the matrix of which *this is the QR decomposition.\n      *\n      * \\note This method has to determine which pivots should be considered nonzero.\n      *       For that, it uses the threshold value that you can control by calling\n      *       setThreshold(const RealScalar&).\n      */\n    inline Index rank() const\n    {\n      using std::abs;\n      eigen_assert(m_isInitialized && \"FullPivHouseholderQR is not initialized.\");\n      RealScalar premultiplied_threshold = abs(m_maxpivot) * threshold();\n      Index result = 0;\n      for(Index i = 0; i < m_nonzero_pivots; ++i)\n        result += (abs(m_qr.coeff(i,i)) > premultiplied_threshold);\n      return result;\n    }\n\n    /** \\returns the dimension of the kernel of the matrix of which *this is the QR decomposition.\n      *\n      * \\note This method has to determine which pivots should be considered nonzero.\n      *       For that, it uses the threshold value that you can control by calling\n      *       setThreshold(const RealScalar&).\n      */\n    inline Index dimensionOfKernel() const\n    {\n      eigen_assert(m_isInitialized && \"FullPivHouseholderQR is not initialized.\");\n      return cols() - rank();\n    }\n\n    /** \\returns true if the matrix of which *this is the QR decomposition represents an injective\n      *          linear map, i.e. has trivial kernel; false otherwise.\n      *\n      * \\note This method has to determine which pivots should be considered nonzero.\n      *       For that, it uses the threshold value that you can control by calling\n      *       setThreshold(const RealScalar&).\n      */\n    inline bool isInjective() const\n    {\n      eigen_assert(m_isInitialized && \"FullPivHouseholderQR is not initialized.\");\n      return rank() == cols();\n    }\n\n    /** \\returns true if the matrix of which *this is the QR decomposition represents a surjective\n      *          linear map; false otherwise.\n      *\n      * \\note This method has to determine which pivots should be considered nonzero.\n      *       For that, it uses the threshold value that you can control by calling\n      *       setThreshold(const RealScalar&).\n      */\n    inline bool isSurjective() const\n    {\n      eigen_assert(m_isInitialized && \"FullPivHouseholderQR is not initialized.\");\n      return rank() == rows();\n    }\n\n    /** \\returns true if the matrix of which *this is the QR decomposition is invertible.\n      *\n      * \\note This method has to determine which pivots should be considered nonzero.\n      *       For that, it uses the threshold value that you can control by calling\n      *       setThreshold(const RealScalar&).\n      */\n    inline bool isInvertible() const\n    {\n      eigen_assert(m_isInitialized && \"FullPivHouseholderQR is not initialized.\");\n      return isInjective() && isSurjective();\n    }\n\n    /** \\returns the inverse of the matrix of which *this is the QR decomposition.\n      *\n      * \\note If this matrix is not invertible, the returned matrix has undefined coefficients.\n      *       Use isInvertible() to first determine whether this matrix is invertible.\n      */\n    inline const Inverse<FullPivHouseholderQR> inverse() const\n    {\n      eigen_assert(m_isInitialized && \"FullPivHouseholderQR is not initialized.\");\n      return Inverse<FullPivHouseholderQR>(*this);\n    }\n\n    inline Index rows() const { return m_qr.rows(); }\n    inline Index cols() const { return m_qr.cols(); }\n    \n    /** \\returns a const reference to the vector of Householder coefficients used to represent the factor \\c Q.\n      * \n      * For advanced uses only.\n      */\n    const HCoeffsType& hCoeffs() const { return m_hCoeffs; }\n\n    /** Allows to prescribe a threshold to be used by certain methods, such as rank(),\n      * who need to determine when pivots are to be considered nonzero. This is not used for the\n      * QR decomposition itself.\n      *\n      * When it needs to get the threshold value, Eigen calls threshold(). By default, this\n      * uses a formula to automatically determine a reasonable threshold.\n      * Once you have called the present method setThreshold(const RealScalar&),\n      * your value is used instead.\n      *\n      * \\param threshold The new value to use as the threshold.\n      *\n      * A pivot will be considered nonzero if its absolute value is strictly greater than\n      *  \\f$ \\vert pivot \\vert \\leqslant threshold \\times \\vert maxpivot \\vert \\f$\n      * where maxpivot is the biggest pivot.\n      *\n      * If you want to come back to the default behavior, call setThreshold(Default_t)\n      */\n    FullPivHouseholderQR& setThreshold(const RealScalar& threshold)\n    {\n      m_usePrescribedThreshold = true;\n      m_prescribedThreshold = threshold;\n      return *this;\n    }\n\n    /** Allows to come back to the default behavior, letting Eigen use its default formula for\n      * determining the threshold.\n      *\n      * You should pass the special object Eigen::Default as parameter here.\n      * \\code qr.setThreshold(Eigen::Default); \\endcode\n      *\n      * See the documentation of setThreshold(const RealScalar&).\n      */\n    FullPivHouseholderQR& setThreshold(Default_t)\n    {\n      m_usePrescribedThreshold = false;\n      return *this;\n    }\n\n    /** Returns the threshold that will be used by certain methods such as rank().\n      *\n      * See the documentation of setThreshold(const RealScalar&).\n      */\n    RealScalar threshold() const\n    {\n      eigen_assert(m_isInitialized || m_usePrescribedThreshold);\n      return m_usePrescribedThreshold ? m_prescribedThreshold\n      // this formula comes from experimenting (see \"LU precision tuning\" thread on the list)\n      // and turns out to be identical to Higham's formula used already in LDLt.\n                                      : NumTraits<Scalar>::epsilon() * RealScalar(m_qr.diagonalSize());\n    }\n\n    /** \\returns the number of nonzero pivots in the QR decomposition.\n      * Here nonzero is meant in the exact sense, not in a fuzzy sense.\n      * So that notion isn't really intrinsically interesting, but it is\n      * still useful when implementing algorithms.\n      *\n      * \\sa rank()\n      */\n    inline Index nonzeroPivots() const\n    {\n      eigen_assert(m_isInitialized && \"LU is not initialized.\");\n      return m_nonzero_pivots;\n    }\n\n    /** \\returns the absolute value of the biggest pivot, i.e. the biggest\n      *          diagonal coefficient of U.\n      */\n    RealScalar maxPivot() const { return m_maxpivot; }\n    \n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    template<typename RhsType, typename DstType>\n    EIGEN_DEVICE_FUNC\n    void _solve_impl(const RhsType &rhs, DstType &dst) const;\n    #endif\n\n  protected:\n    \n    static void check_template_parameters()\n    {\n      EIGEN_STATIC_ASSERT_NON_INTEGER(Scalar);\n    }\n    \n    void computeInPlace();\n    \n    MatrixType m_qr;\n    HCoeffsType m_hCoeffs;\n    IntDiagSizeVectorType m_rows_transpositions;\n    IntDiagSizeVectorType m_cols_transpositions;\n    PermutationType m_cols_permutation;\n    RowVectorType m_temp;\n    bool m_isInitialized, m_usePrescribedThreshold;\n    RealScalar m_prescribedThreshold, m_maxpivot;\n    Index m_nonzero_pivots;\n    RealScalar m_precision;\n    Index m_det_pq;\n};\n\ntemplate<typename MatrixType>\ntypename MatrixType::RealScalar FullPivHouseholderQR<MatrixType>::absDeterminant() const\n{\n  using std::abs;\n  eigen_assert(m_isInitialized && \"FullPivHouseholderQR is not initialized.\");\n  eigen_assert(m_qr.rows() == m_qr.cols() && \"You can't take the determinant of a non-square matrix!\");\n  return abs(m_qr.diagonal().prod());\n}\n\ntemplate<typename MatrixType>\ntypename MatrixType::RealScalar FullPivHouseholderQR<MatrixType>::logAbsDeterminant() const\n{\n  eigen_assert(m_isInitialized && \"FullPivHouseholderQR is not initialized.\");\n  eigen_assert(m_qr.rows() == m_qr.cols() && \"You can't take the determinant of a non-square matrix!\");\n  return m_qr.diagonal().cwiseAbs().array().log().sum();\n}\n\n/** Performs the QR factorization of the given matrix \\a matrix. The result of\n  * the factorization is stored into \\c *this, and a reference to \\c *this\n  * is returned.\n  *\n  * \\sa class FullPivHouseholderQR, FullPivHouseholderQR(const MatrixType&)\n  */\ntemplate<typename MatrixType>\ntemplate<typename InputType>\nFullPivHouseholderQR<MatrixType>& FullPivHouseholderQR<MatrixType>::compute(const EigenBase<InputType>& matrix)\n{\n  m_qr = matrix.derived();\n  computeInPlace();\n  return *this;\n}\n\ntemplate<typename MatrixType>\nvoid FullPivHouseholderQR<MatrixType>::computeInPlace()\n{\n  check_template_parameters();\n\n  using std::abs;\n  Index rows = m_qr.rows();\n  Index cols = m_qr.cols();\n  Index size = (std::min)(rows,cols);\n\n  \n  m_hCoeffs.resize(size);\n\n  m_temp.resize(cols);\n\n  m_precision = NumTraits<Scalar>::epsilon() * RealScalar(size);\n\n  m_rows_transpositions.resize(size);\n  m_cols_transpositions.resize(size);\n  Index number_of_transpositions = 0;\n\n  RealScalar biggest(0);\n\n  m_nonzero_pivots = size; // the generic case is that in which all pivots are nonzero (invertible case)\n  m_maxpivot = RealScalar(0);\n\n  for (Index k = 0; k < size; ++k)\n  {\n    Index row_of_biggest_in_corner, col_of_biggest_in_corner;\n    typedef internal::scalar_score_coeff_op<Scalar> Scoring;\n    typedef typename Scoring::result_type Score;\n\n    Score score = m_qr.bottomRightCorner(rows-k, cols-k)\n                      .unaryExpr(Scoring())\n                      .maxCoeff(&row_of_biggest_in_corner, &col_of_biggest_in_corner);\n    row_of_biggest_in_corner += k;\n    col_of_biggest_in_corner += k;\n    RealScalar biggest_in_corner = internal::abs_knowing_score<Scalar>()(m_qr(row_of_biggest_in_corner, col_of_biggest_in_corner), score);\n    if(k==0) biggest = biggest_in_corner;\n\n    // if the corner is negligible, then we have less than full rank, and we can finish early\n    if(internal::isMuchSmallerThan(biggest_in_corner, biggest, m_precision))\n    {\n      m_nonzero_pivots = k;\n      for(Index i = k; i < size; i++)\n      {\n        m_rows_transpositions.coeffRef(i) = i;\n        m_cols_transpositions.coeffRef(i) = i;\n        m_hCoeffs.coeffRef(i) = Scalar(0);\n      }\n      break;\n    }\n\n    m_rows_transpositions.coeffRef(k) = row_of_biggest_in_corner;\n    m_cols_transpositions.coeffRef(k) = col_of_biggest_in_corner;\n    if(k != row_of_biggest_in_corner) {\n      m_qr.row(k).tail(cols-k).swap(m_qr.row(row_of_biggest_in_corner).tail(cols-k));\n      ++number_of_transpositions;\n    }\n    if(k != col_of_biggest_in_corner) {\n      m_qr.col(k).swap(m_qr.col(col_of_biggest_in_corner));\n      ++number_of_transpositions;\n    }\n\n    RealScalar beta;\n    m_qr.col(k).tail(rows-k).makeHouseholderInPlace(m_hCoeffs.coeffRef(k), beta);\n    m_qr.coeffRef(k,k) = beta;\n\n    // remember the maximum absolute value of diagonal coefficients\n    if(abs(beta) > m_maxpivot) m_maxpivot = abs(beta);\n\n    m_qr.bottomRightCorner(rows-k, cols-k-1)\n        .applyHouseholderOnTheLeft(m_qr.col(k).tail(rows-k-1), m_hCoeffs.coeffRef(k), &m_temp.coeffRef(k+1));\n  }\n\n  m_cols_permutation.setIdentity(cols);\n  for(Index k = 0; k < size; ++k)\n    m_cols_permutation.applyTranspositionOnTheRight(k, m_cols_transpositions.coeff(k));\n\n  m_det_pq = (number_of_transpositions%2) ? -1 : 1;\n  m_isInitialized = true;\n}\n\n#ifndef EIGEN_PARSED_BY_DOXYGEN\ntemplate<typename _MatrixType>\ntemplate<typename RhsType, typename DstType>\nvoid FullPivHouseholderQR<_MatrixType>::_solve_impl(const RhsType &rhs, DstType &dst) const\n{\n  eigen_assert(rhs.rows() == rows());\n  const Index l_rank = rank();\n\n  // FIXME introduce nonzeroPivots() and use it here. and more generally,\n  // make the same improvements in this dec as in FullPivLU.\n  if(l_rank==0)\n  {\n    dst.setZero();\n    return;\n  }\n\n  typename RhsType::PlainObject c(rhs);\n\n  Matrix<Scalar,1,RhsType::ColsAtCompileTime> temp(rhs.cols());\n  for (Index k = 0; k < l_rank; ++k)\n  {\n    Index remainingSize = rows()-k;\n    c.row(k).swap(c.row(m_rows_transpositions.coeff(k)));\n    c.bottomRightCorner(remainingSize, rhs.cols())\n      .applyHouseholderOnTheLeft(m_qr.col(k).tail(remainingSize-1),\n                               m_hCoeffs.coeff(k), &temp.coeffRef(0));\n  }\n\n  m_qr.topLeftCorner(l_rank, l_rank)\n      .template triangularView<Upper>()\n      .solveInPlace(c.topRows(l_rank));\n\n  for(Index i = 0; i < l_rank; ++i) dst.row(m_cols_permutation.indices().coeff(i)) = c.row(i);\n  for(Index i = l_rank; i < cols(); ++i) dst.row(m_cols_permutation.indices().coeff(i)).setZero();\n}\n#endif\n\nnamespace internal {\n  \ntemplate<typename DstXprType, typename MatrixType>\nstruct Assignment<DstXprType, Inverse<FullPivHouseholderQR<MatrixType> >, internal::assign_op<typename DstXprType::Scalar,typename FullPivHouseholderQR<MatrixType>::Scalar>, Dense2Dense>\n{\n  typedef FullPivHouseholderQR<MatrixType> QrType;\n  typedef Inverse<QrType> SrcXprType;\n  static void run(DstXprType &dst, const SrcXprType &src, const internal::assign_op<typename DstXprType::Scalar,typename QrType::Scalar> &)\n  {    \n    dst = src.nestedExpression().solve(MatrixType::Identity(src.rows(), src.cols()));\n  }\n};\n\n/** \\ingroup QR_Module\n  *\n  * \\brief Expression type for return value of FullPivHouseholderQR::matrixQ()\n  *\n  * \\tparam MatrixType type of underlying dense matrix\n  */\ntemplate<typename MatrixType> struct FullPivHouseholderQRMatrixQReturnType\n  : public ReturnByValue<FullPivHouseholderQRMatrixQReturnType<MatrixType> >\n{\npublic:\n  typedef typename FullPivHouseholderQR<MatrixType>::IntDiagSizeVectorType IntDiagSizeVectorType;\n  typedef typename internal::plain_diag_type<MatrixType>::type HCoeffsType;\n  typedef Matrix<typename MatrixType::Scalar, 1, MatrixType::RowsAtCompileTime, RowMajor, 1,\n                 MatrixType::MaxRowsAtCompileTime> WorkVectorType;\n\n  FullPivHouseholderQRMatrixQReturnType(const MatrixType&       qr,\n                                        const HCoeffsType&      hCoeffs,\n                                        const IntDiagSizeVectorType& rowsTranspositions)\n    : m_qr(qr),\n      m_hCoeffs(hCoeffs),\n      m_rowsTranspositions(rowsTranspositions)\n  {}\n\n  template <typename ResultType>\n  void evalTo(ResultType& result) const\n  {\n    const Index rows = m_qr.rows();\n    WorkVectorType workspace(rows);\n    evalTo(result, workspace);\n  }\n\n  template <typename ResultType>\n  void evalTo(ResultType& result, WorkVectorType& workspace) const\n  {\n    using numext::conj;\n    // compute the product H'_0 H'_1 ... H'_n-1,\n    // where H_k is the k-th Householder transformation I - h_k v_k v_k'\n    // and v_k is the k-th Householder vector [1,m_qr(k+1,k), m_qr(k+2,k), ...]\n    const Index rows = m_qr.rows();\n    const Index cols = m_qr.cols();\n    const Index size = (std::min)(rows, cols);\n    workspace.resize(rows);\n    result.setIdentity(rows, rows);\n    for (Index k = size-1; k >= 0; k--)\n    {\n      result.block(k, k, rows-k, rows-k)\n            .applyHouseholderOnTheLeft(m_qr.col(k).tail(rows-k-1), conj(m_hCoeffs.coeff(k)), &workspace.coeffRef(k));\n      result.row(k).swap(result.row(m_rowsTranspositions.coeff(k)));\n    }\n  }\n\n  Index rows() const { return m_qr.rows(); }\n  Index cols() const { return m_qr.rows(); }\n\nprotected:\n  typename MatrixType::Nested m_qr;\n  typename HCoeffsType::Nested m_hCoeffs;\n  typename IntDiagSizeVectorType::Nested m_rowsTranspositions;\n};\n\n// template<typename MatrixType>\n// struct evaluator<FullPivHouseholderQRMatrixQReturnType<MatrixType> >\n//  : public evaluator<ReturnByValue<FullPivHouseholderQRMatrixQReturnType<MatrixType> > >\n// {};\n\n} // end namespace internal\n\ntemplate<typename MatrixType>\ninline typename FullPivHouseholderQR<MatrixType>::MatrixQReturnType FullPivHouseholderQR<MatrixType>::matrixQ() const\n{\n  eigen_assert(m_isInitialized && \"FullPivHouseholderQR is not initialized.\");\n  return MatrixQReturnType(m_qr, m_hCoeffs, m_rows_transpositions);\n}\n\n/** \\return the full-pivoting Householder QR decomposition of \\c *this.\n  *\n  * \\sa class FullPivHouseholderQR\n  */\ntemplate<typename Derived>\nconst FullPivHouseholderQR<typename MatrixBase<Derived>::PlainObject>\nMatrixBase<Derived>::fullPivHouseholderQr() const\n{\n  return FullPivHouseholderQR<PlainObject>(eval());\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_FULLPIVOTINGHOUSEHOLDERQR_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/QR/HouseholderQR.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2009 Benoit Jacob <jacob.benoit.1@gmail.com>\n// Copyright (C) 2010 Vincent Lejeune\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_QR_H\n#define EIGEN_QR_H\n\nnamespace Eigen { \n\n/** \\ingroup QR_Module\n  *\n  *\n  * \\class HouseholderQR\n  *\n  * \\brief Householder QR decomposition of a matrix\n  *\n  * \\tparam _MatrixType the type of the matrix of which we are computing the QR decomposition\n  *\n  * This class performs a QR decomposition of a matrix \\b A into matrices \\b Q and \\b R\n  * such that \n  * \\f[\n  *  \\mathbf{A} = \\mathbf{Q} \\, \\mathbf{R}\n  * \\f]\n  * by using Householder transformations. Here, \\b Q a unitary matrix and \\b R an upper triangular matrix.\n  * The result is stored in a compact way compatible with LAPACK.\n  *\n  * Note that no pivoting is performed. This is \\b not a rank-revealing decomposition.\n  * If you want that feature, use FullPivHouseholderQR or ColPivHouseholderQR instead.\n  *\n  * This Householder QR decomposition is faster, but less numerically stable and less feature-full than\n  * FullPivHouseholderQR or ColPivHouseholderQR.\n  *\n  * This class supports the \\link InplaceDecomposition inplace decomposition \\endlink mechanism.\n  *\n  * \\sa MatrixBase::householderQr()\n  */\ntemplate<typename _MatrixType> class HouseholderQR\n{\n  public:\n\n    typedef _MatrixType MatrixType;\n    enum {\n      RowsAtCompileTime = MatrixType::RowsAtCompileTime,\n      ColsAtCompileTime = MatrixType::ColsAtCompileTime,\n      MaxRowsAtCompileTime = MatrixType::MaxRowsAtCompileTime,\n      MaxColsAtCompileTime = MatrixType::MaxColsAtCompileTime\n    };\n    typedef typename MatrixType::Scalar Scalar;\n    typedef typename MatrixType::RealScalar RealScalar;\n    // FIXME should be int\n    typedef typename MatrixType::StorageIndex StorageIndex;\n    typedef Matrix<Scalar, RowsAtCompileTime, RowsAtCompileTime, (MatrixType::Flags&RowMajorBit) ? RowMajor : ColMajor, MaxRowsAtCompileTime, MaxRowsAtCompileTime> MatrixQType;\n    typedef typename internal::plain_diag_type<MatrixType>::type HCoeffsType;\n    typedef typename internal::plain_row_type<MatrixType>::type RowVectorType;\n    typedef HouseholderSequence<MatrixType,typename internal::remove_all<typename HCoeffsType::ConjugateReturnType>::type> HouseholderSequenceType;\n\n    /**\n      * \\brief Default Constructor.\n      *\n      * The default constructor is useful in cases in which the user intends to\n      * perform decompositions via HouseholderQR::compute(const MatrixType&).\n      */\n    HouseholderQR() : m_qr(), m_hCoeffs(), m_temp(), m_isInitialized(false) {}\n\n    /** \\brief Default Constructor with memory preallocation\n      *\n      * Like the default constructor but with preallocation of the internal data\n      * according to the specified problem \\a size.\n      * \\sa HouseholderQR()\n      */\n    HouseholderQR(Index rows, Index cols)\n      : m_qr(rows, cols),\n        m_hCoeffs((std::min)(rows,cols)),\n        m_temp(cols),\n        m_isInitialized(false) {}\n\n    /** \\brief Constructs a QR factorization from a given matrix\n      *\n      * This constructor computes the QR factorization of the matrix \\a matrix by calling\n      * the method compute(). It is a short cut for:\n      * \n      * \\code\n      * HouseholderQR<MatrixType> qr(matrix.rows(), matrix.cols());\n      * qr.compute(matrix);\n      * \\endcode\n      * \n      * \\sa compute()\n      */\n    template<typename InputType>\n    explicit HouseholderQR(const EigenBase<InputType>& matrix)\n      : m_qr(matrix.rows(), matrix.cols()),\n        m_hCoeffs((std::min)(matrix.rows(),matrix.cols())),\n        m_temp(matrix.cols()),\n        m_isInitialized(false)\n    {\n      compute(matrix.derived());\n    }\n\n\n    /** \\brief Constructs a QR factorization from a given matrix\n      *\n      * This overloaded constructor is provided for \\link InplaceDecomposition inplace decomposition \\endlink when\n      * \\c MatrixType is a Eigen::Ref.\n      *\n      * \\sa HouseholderQR(const EigenBase&)\n      */\n    template<typename InputType>\n    explicit HouseholderQR(EigenBase<InputType>& matrix)\n      : m_qr(matrix.derived()),\n        m_hCoeffs((std::min)(matrix.rows(),matrix.cols())),\n        m_temp(matrix.cols()),\n        m_isInitialized(false)\n    {\n      computeInPlace();\n    }\n\n    /** This method finds a solution x to the equation Ax=b, where A is the matrix of which\n      * *this is the QR decomposition, if any exists.\n      *\n      * \\param b the right-hand-side of the equation to solve.\n      *\n      * \\returns a solution.\n      *\n      * \\note_about_checking_solutions\n      *\n      * \\note_about_arbitrary_choice_of_solution\n      *\n      * Example: \\include HouseholderQR_solve.cpp\n      * Output: \\verbinclude HouseholderQR_solve.out\n      */\n    template<typename Rhs>\n    inline const Solve<HouseholderQR, Rhs>\n    solve(const MatrixBase<Rhs>& b) const\n    {\n      eigen_assert(m_isInitialized && \"HouseholderQR is not initialized.\");\n      return Solve<HouseholderQR, Rhs>(*this, b.derived());\n    }\n\n    /** This method returns an expression of the unitary matrix Q as a sequence of Householder transformations.\n      *\n      * The returned expression can directly be used to perform matrix products. It can also be assigned to a dense Matrix object.\n      * Here is an example showing how to recover the full or thin matrix Q, as well as how to perform matrix products using operator*:\n      *\n      * Example: \\include HouseholderQR_householderQ.cpp\n      * Output: \\verbinclude HouseholderQR_householderQ.out\n      */\n    HouseholderSequenceType householderQ() const\n    {\n      eigen_assert(m_isInitialized && \"HouseholderQR is not initialized.\");\n      return HouseholderSequenceType(m_qr, m_hCoeffs.conjugate());\n    }\n\n    /** \\returns a reference to the matrix where the Householder QR decomposition is stored\n      * in a LAPACK-compatible way.\n      */\n    const MatrixType& matrixQR() const\n    {\n        eigen_assert(m_isInitialized && \"HouseholderQR is not initialized.\");\n        return m_qr;\n    }\n\n    template<typename InputType>\n    HouseholderQR& compute(const EigenBase<InputType>& matrix) {\n      m_qr = matrix.derived();\n      computeInPlace();\n      return *this;\n    }\n\n    /** \\returns the absolute value of the determinant of the matrix of which\n      * *this is the QR decomposition. It has only linear complexity\n      * (that is, O(n) where n is the dimension of the square matrix)\n      * as the QR decomposition has already been computed.\n      *\n      * \\note This is only for square matrices.\n      *\n      * \\warning a determinant can be very big or small, so for matrices\n      * of large enough dimension, there is a risk of overflow/underflow.\n      * One way to work around that is to use logAbsDeterminant() instead.\n      *\n      * \\sa logAbsDeterminant(), MatrixBase::determinant()\n      */\n    typename MatrixType::RealScalar absDeterminant() const;\n\n    /** \\returns the natural log of the absolute value of the determinant of the matrix of which\n      * *this is the QR decomposition. It has only linear complexity\n      * (that is, O(n) where n is the dimension of the square matrix)\n      * as the QR decomposition has already been computed.\n      *\n      * \\note This is only for square matrices.\n      *\n      * \\note This method is useful to work around the risk of overflow/underflow that's inherent\n      * to determinant computation.\n      *\n      * \\sa absDeterminant(), MatrixBase::determinant()\n      */\n    typename MatrixType::RealScalar logAbsDeterminant() const;\n\n    inline Index rows() const { return m_qr.rows(); }\n    inline Index cols() const { return m_qr.cols(); }\n    \n    /** \\returns a const reference to the vector of Householder coefficients used to represent the factor \\c Q.\n      * \n      * For advanced uses only.\n      */\n    const HCoeffsType& hCoeffs() const { return m_hCoeffs; }\n    \n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    template<typename RhsType, typename DstType>\n    EIGEN_DEVICE_FUNC\n    void _solve_impl(const RhsType &rhs, DstType &dst) const;\n    #endif\n\n  protected:\n    \n    static void check_template_parameters()\n    {\n      EIGEN_STATIC_ASSERT_NON_INTEGER(Scalar);\n    }\n\n    void computeInPlace();\n    \n    MatrixType m_qr;\n    HCoeffsType m_hCoeffs;\n    RowVectorType m_temp;\n    bool m_isInitialized;\n};\n\ntemplate<typename MatrixType>\ntypename MatrixType::RealScalar HouseholderQR<MatrixType>::absDeterminant() const\n{\n  using std::abs;\n  eigen_assert(m_isInitialized && \"HouseholderQR is not initialized.\");\n  eigen_assert(m_qr.rows() == m_qr.cols() && \"You can't take the determinant of a non-square matrix!\");\n  return abs(m_qr.diagonal().prod());\n}\n\ntemplate<typename MatrixType>\ntypename MatrixType::RealScalar HouseholderQR<MatrixType>::logAbsDeterminant() const\n{\n  eigen_assert(m_isInitialized && \"HouseholderQR is not initialized.\");\n  eigen_assert(m_qr.rows() == m_qr.cols() && \"You can't take the determinant of a non-square matrix!\");\n  return m_qr.diagonal().cwiseAbs().array().log().sum();\n}\n\nnamespace internal {\n\n/** \\internal */\ntemplate<typename MatrixQR, typename HCoeffs>\nvoid householder_qr_inplace_unblocked(MatrixQR& mat, HCoeffs& hCoeffs, typename MatrixQR::Scalar* tempData = 0)\n{\n  typedef typename MatrixQR::Scalar Scalar;\n  typedef typename MatrixQR::RealScalar RealScalar;\n  Index rows = mat.rows();\n  Index cols = mat.cols();\n  Index size = (std::min)(rows,cols);\n\n  eigen_assert(hCoeffs.size() == size);\n\n  typedef Matrix<Scalar,MatrixQR::ColsAtCompileTime,1> TempType;\n  TempType tempVector;\n  if(tempData==0)\n  {\n    tempVector.resize(cols);\n    tempData = tempVector.data();\n  }\n\n  for(Index k = 0; k < size; ++k)\n  {\n    Index remainingRows = rows - k;\n    Index remainingCols = cols - k - 1;\n\n    RealScalar beta;\n    mat.col(k).tail(remainingRows).makeHouseholderInPlace(hCoeffs.coeffRef(k), beta);\n    mat.coeffRef(k,k) = beta;\n\n    // apply H to remaining part of m_qr from the left\n    mat.bottomRightCorner(remainingRows, remainingCols)\n        .applyHouseholderOnTheLeft(mat.col(k).tail(remainingRows-1), hCoeffs.coeffRef(k), tempData+k+1);\n  }\n}\n\n/** \\internal */\ntemplate<typename MatrixQR, typename HCoeffs,\n  typename MatrixQRScalar = typename MatrixQR::Scalar,\n  bool InnerStrideIsOne = (MatrixQR::InnerStrideAtCompileTime == 1 && HCoeffs::InnerStrideAtCompileTime == 1)>\nstruct householder_qr_inplace_blocked\n{\n  // This is specialized for MKL-supported Scalar types in HouseholderQR_MKL.h\n  static void run(MatrixQR& mat, HCoeffs& hCoeffs, Index maxBlockSize=32,\n      typename MatrixQR::Scalar* tempData = 0)\n  {\n    typedef typename MatrixQR::Scalar Scalar;\n    typedef Block<MatrixQR,Dynamic,Dynamic> BlockType;\n\n    Index rows = mat.rows();\n    Index cols = mat.cols();\n    Index size = (std::min)(rows, cols);\n\n    typedef Matrix<Scalar,Dynamic,1,ColMajor,MatrixQR::MaxColsAtCompileTime,1> TempType;\n    TempType tempVector;\n    if(tempData==0)\n    {\n      tempVector.resize(cols);\n      tempData = tempVector.data();\n    }\n\n    Index blockSize = (std::min)(maxBlockSize,size);\n\n    Index k = 0;\n    for (k = 0; k < size; k += blockSize)\n    {\n      Index bs = (std::min)(size-k,blockSize);  // actual size of the block\n      Index tcols = cols - k - bs;              // trailing columns\n      Index brows = rows-k;                     // rows of the block\n\n      // partition the matrix:\n      //        A00 | A01 | A02\n      // mat  = A10 | A11 | A12\n      //        A20 | A21 | A22\n      // and performs the qr dec of [A11^T A12^T]^T\n      // and update [A21^T A22^T]^T using level 3 operations.\n      // Finally, the algorithm continue on A22\n\n      BlockType A11_21 = mat.block(k,k,brows,bs);\n      Block<HCoeffs,Dynamic,1> hCoeffsSegment = hCoeffs.segment(k,bs);\n\n      householder_qr_inplace_unblocked(A11_21, hCoeffsSegment, tempData);\n\n      if(tcols)\n      {\n        BlockType A21_22 = mat.block(k,k+bs,brows,tcols);\n        apply_block_householder_on_the_left(A21_22,A11_21,hCoeffsSegment, false); // false == backward\n      }\n    }\n  }\n};\n\n} // end namespace internal\n\n#ifndef EIGEN_PARSED_BY_DOXYGEN\ntemplate<typename _MatrixType>\ntemplate<typename RhsType, typename DstType>\nvoid HouseholderQR<_MatrixType>::_solve_impl(const RhsType &rhs, DstType &dst) const\n{\n  const Index rank = (std::min)(rows(), cols());\n  eigen_assert(rhs.rows() == rows());\n\n  typename RhsType::PlainObject c(rhs);\n\n  // Note that the matrix Q = H_0^* H_1^*... so its inverse is Q^* = (H_0 H_1 ...)^T\n  c.applyOnTheLeft(householderSequence(\n    m_qr.leftCols(rank),\n    m_hCoeffs.head(rank)).transpose()\n  );\n\n  m_qr.topLeftCorner(rank, rank)\n      .template triangularView<Upper>()\n      .solveInPlace(c.topRows(rank));\n\n  dst.topRows(rank) = c.topRows(rank);\n  dst.bottomRows(cols()-rank).setZero();\n}\n#endif\n\n/** Performs the QR factorization of the given matrix \\a matrix. The result of\n  * the factorization is stored into \\c *this, and a reference to \\c *this\n  * is returned.\n  *\n  * \\sa class HouseholderQR, HouseholderQR(const MatrixType&)\n  */\ntemplate<typename MatrixType>\nvoid HouseholderQR<MatrixType>::computeInPlace()\n{\n  check_template_parameters();\n  \n  Index rows = m_qr.rows();\n  Index cols = m_qr.cols();\n  Index size = (std::min)(rows,cols);\n\n  m_hCoeffs.resize(size);\n\n  m_temp.resize(cols);\n\n  internal::householder_qr_inplace_blocked<MatrixType, HCoeffsType>::run(m_qr, m_hCoeffs, 48, m_temp.data());\n\n  m_isInitialized = true;\n}\n\n/** \\return the Householder QR decomposition of \\c *this.\n  *\n  * \\sa class HouseholderQR\n  */\ntemplate<typename Derived>\nconst HouseholderQR<typename MatrixBase<Derived>::PlainObject>\nMatrixBase<Derived>::householderQr() const\n{\n  return HouseholderQR<PlainObject>(eval());\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_QR_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/QR/HouseholderQR_LAPACKE.h",
    "content": "/*\n Copyright (c) 2011, Intel Corporation. All rights reserved.\n\n Redistribution and use in source and binary forms, with or without modification,\n are permitted provided that the following conditions are met:\n\n * Redistributions of source code must retain the above copyright notice, this\n   list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright notice,\n   this list of conditions and the following disclaimer in the documentation\n   and/or other materials provided with the distribution.\n * Neither the name of Intel Corporation nor the names of its contributors may\n   be used to endorse or promote products derived from this software without\n   specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n ********************************************************************************\n *   Content : Eigen bindings to LAPACKe\n *    Householder QR decomposition of a matrix w/o pivoting based on\n *    LAPACKE_?geqrf function.\n ********************************************************************************\n*/\n\n#ifndef EIGEN_QR_LAPACKE_H\n#define EIGEN_QR_LAPACKE_H\n\nnamespace Eigen { \n\nnamespace internal {\n\n/** \\internal Specialization for the data types supported by LAPACKe */\n\n#define EIGEN_LAPACKE_QR_NOPIV(EIGTYPE, LAPACKE_TYPE, LAPACKE_PREFIX) \\\ntemplate<typename MatrixQR, typename HCoeffs> \\\nstruct householder_qr_inplace_blocked<MatrixQR, HCoeffs, EIGTYPE, true> \\\n{ \\\n  static void run(MatrixQR& mat, HCoeffs& hCoeffs, Index = 32, \\\n      typename MatrixQR::Scalar* = 0) \\\n  { \\\n    lapack_int m = (lapack_int) mat.rows(); \\\n    lapack_int n = (lapack_int) mat.cols(); \\\n    lapack_int lda = (lapack_int) mat.outerStride(); \\\n    lapack_int matrix_order = (MatrixQR::IsRowMajor) ? LAPACK_ROW_MAJOR : LAPACK_COL_MAJOR; \\\n    LAPACKE_##LAPACKE_PREFIX##geqrf( matrix_order, m, n, (LAPACKE_TYPE*)mat.data(), lda, (LAPACKE_TYPE*)hCoeffs.data()); \\\n    hCoeffs.adjointInPlace(); \\\n  } \\\n};\n\nEIGEN_LAPACKE_QR_NOPIV(double, double, d)\nEIGEN_LAPACKE_QR_NOPIV(float, float, s)\nEIGEN_LAPACKE_QR_NOPIV(dcomplex, lapack_complex_double, z)\nEIGEN_LAPACKE_QR_NOPIV(scomplex, lapack_complex_float, c)\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_QR_LAPACKE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SPQRSupport/SuiteSparseQRSupport.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2012 Desire Nuentsa <desire.nuentsa_wakam@inria.fr>\n// Copyright (C) 2014 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SUITESPARSEQRSUPPORT_H\n#define EIGEN_SUITESPARSEQRSUPPORT_H\n\nnamespace Eigen {\n  \n  template<typename MatrixType> class SPQR; \n  template<typename SPQRType> struct SPQRMatrixQReturnType; \n  template<typename SPQRType> struct SPQRMatrixQTransposeReturnType; \n  template <typename SPQRType, typename Derived> struct SPQR_QProduct;\n  namespace internal {\n    template <typename SPQRType> struct traits<SPQRMatrixQReturnType<SPQRType> >\n    {\n      typedef typename SPQRType::MatrixType ReturnType;\n    };\n    template <typename SPQRType> struct traits<SPQRMatrixQTransposeReturnType<SPQRType> >\n    {\n      typedef typename SPQRType::MatrixType ReturnType;\n    };\n    template <typename SPQRType, typename Derived> struct traits<SPQR_QProduct<SPQRType, Derived> >\n    {\n      typedef typename Derived::PlainObject ReturnType;\n    };\n  } // End namespace internal\n  \n/**\n  * \\ingroup SPQRSupport_Module\n  * \\class SPQR\n  * \\brief Sparse QR factorization based on SuiteSparseQR library\n  *\n  * This class is used to perform a multithreaded and multifrontal rank-revealing QR decomposition\n  * of sparse matrices. The result is then used to solve linear leasts_square systems.\n  * Clearly, a QR factorization is returned such that A*P = Q*R where :\n  *\n  * P is the column permutation. Use colsPermutation() to get it.\n  *\n  * Q is the orthogonal matrix represented as Householder reflectors.\n  * Use matrixQ() to get an expression and matrixQ().transpose() to get the transpose.\n  * You can then apply it to a vector.\n  *\n  * R is the sparse triangular factor. Use matrixQR() to get it as SparseMatrix.\n  * NOTE : The Index type of R is always SuiteSparse_long. You can get it with SPQR::Index\n  *\n  * \\tparam _MatrixType The type of the sparse matrix A, must be a column-major SparseMatrix<>\n  *\n  * \\implsparsesolverconcept\n  *\n  *\n  */\ntemplate<typename _MatrixType>\nclass SPQR : public SparseSolverBase<SPQR<_MatrixType> >\n{\n  protected:\n    typedef SparseSolverBase<SPQR<_MatrixType> > Base;\n    using Base::m_isInitialized;\n  public:\n    typedef typename _MatrixType::Scalar Scalar;\n    typedef typename _MatrixType::RealScalar RealScalar;\n    typedef SuiteSparse_long StorageIndex ;\n    typedef SparseMatrix<Scalar, ColMajor, StorageIndex> MatrixType;\n    typedef Map<PermutationMatrix<Dynamic, Dynamic, StorageIndex> > PermutationType;\n    enum {\n      ColsAtCompileTime = Dynamic,\n      MaxColsAtCompileTime = Dynamic\n    };\n  public:\n    SPQR() \n      : m_ordering(SPQR_ORDERING_DEFAULT), m_allow_tol(SPQR_DEFAULT_TOL), m_tolerance (NumTraits<Scalar>::epsilon()), m_useDefaultThreshold(true)\n    { \n      cholmod_l_start(&m_cc);\n    }\n    \n    explicit SPQR(const _MatrixType& matrix)\n    : m_ordering(SPQR_ORDERING_DEFAULT), m_allow_tol(SPQR_DEFAULT_TOL), m_tolerance (NumTraits<Scalar>::epsilon()), m_useDefaultThreshold(true)\n    {\n      cholmod_l_start(&m_cc);\n      compute(matrix);\n    }\n    \n    ~SPQR()\n    {\n      SPQR_free();\n      cholmod_l_finish(&m_cc);\n    }\n    void SPQR_free()\n    {\n      cholmod_l_free_sparse(&m_H, &m_cc);\n      cholmod_l_free_sparse(&m_cR, &m_cc);\n      cholmod_l_free_dense(&m_HTau, &m_cc);\n      std::free(m_E);\n      std::free(m_HPinv);\n    }\n\n    void compute(const _MatrixType& matrix)\n    {\n      if(m_isInitialized) SPQR_free();\n\n      MatrixType mat(matrix);\n      \n      /* Compute the default threshold as in MatLab, see:\n       * Tim Davis, \"Algorithm 915, SuiteSparseQR: Multifrontal Multithreaded Rank-Revealing\n       * Sparse QR Factorization, ACM Trans. on Math. Soft. 38(1), 2011, Page 8:3 \n       */\n      RealScalar pivotThreshold = m_tolerance;\n      if(m_useDefaultThreshold) \n      {\n        RealScalar max2Norm = 0.0;\n        for (int j = 0; j < mat.cols(); j++) max2Norm = numext::maxi(max2Norm, mat.col(j).norm());\n        if(max2Norm==RealScalar(0))\n          max2Norm = RealScalar(1);\n        pivotThreshold = 20 * (mat.rows() + mat.cols()) * max2Norm * NumTraits<RealScalar>::epsilon();\n      }\n      cholmod_sparse A; \n      A = viewAsCholmod(mat);\n      m_rows = matrix.rows();\n      Index col = matrix.cols();\n      m_rank = SuiteSparseQR<Scalar>(m_ordering, pivotThreshold, col, &A, \n                             &m_cR, &m_E, &m_H, &m_HPinv, &m_HTau, &m_cc);\n\n      if (!m_cR)\n      {\n        m_info = NumericalIssue;\n        m_isInitialized = false;\n        return;\n      }\n      m_info = Success;\n      m_isInitialized = true;\n      m_isRUpToDate = false;\n    }\n    /** \n     * Get the number of rows of the input matrix and the Q matrix\n     */\n    inline Index rows() const {return m_rows; }\n    \n    /** \n     * Get the number of columns of the input matrix. \n     */\n    inline Index cols() const { return m_cR->ncol; }\n    \n    template<typename Rhs, typename Dest>\n    void _solve_impl(const MatrixBase<Rhs> &b, MatrixBase<Dest> &dest) const\n    {\n      eigen_assert(m_isInitialized && \" The QR factorization should be computed first, call compute()\");\n      eigen_assert(b.cols()==1 && \"This method is for vectors only\");\n\n      //Compute Q^T * b\n      typename Dest::PlainObject y, y2;\n      y = matrixQ().transpose() * b;\n      \n      // Solves with the triangular matrix R\n      Index rk = this->rank();\n      y2 = y;\n      y.resize((std::max)(cols(),Index(y.rows())),y.cols());\n      y.topRows(rk) = this->matrixR().topLeftCorner(rk, rk).template triangularView<Upper>().solve(y2.topRows(rk));\n\n      // Apply the column permutation \n      // colsPermutation() performs a copy of the permutation,\n      // so let's apply it manually:\n      for(Index i = 0; i < rk; ++i) dest.row(m_E[i]) = y.row(i);\n      for(Index i = rk; i < cols(); ++i) dest.row(m_E[i]).setZero();\n      \n//       y.bottomRows(y.rows()-rk).setZero();\n//       dest = colsPermutation() * y.topRows(cols());\n      \n      m_info = Success;\n    }\n    \n    /** \\returns the sparse triangular factor R. It is a sparse matrix\n     */\n    const MatrixType matrixR() const\n    {\n      eigen_assert(m_isInitialized && \" The QR factorization should be computed first, call compute()\");\n      if(!m_isRUpToDate) {\n        m_R = viewAsEigen<Scalar,ColMajor, typename MatrixType::StorageIndex>(*m_cR);\n        m_isRUpToDate = true;\n      }\n      return m_R;\n    }\n    /// Get an expression of the matrix Q\n    SPQRMatrixQReturnType<SPQR> matrixQ() const\n    {\n      return SPQRMatrixQReturnType<SPQR>(*this);\n    }\n    /// Get the permutation that was applied to columns of A\n    PermutationType colsPermutation() const\n    { \n      eigen_assert(m_isInitialized && \"Decomposition is not initialized.\");\n      return PermutationType(m_E, m_cR->ncol);\n    }\n    /**\n     * Gets the rank of the matrix. \n     * It should be equal to matrixQR().cols if the matrix is full-rank\n     */\n    Index rank() const\n    {\n      eigen_assert(m_isInitialized && \"Decomposition is not initialized.\");\n      return m_cc.SPQR_istat[4];\n    }\n    /// Set the fill-reducing ordering method to be used\n    void setSPQROrdering(int ord) { m_ordering = ord;}\n    /// Set the tolerance tol to treat columns with 2-norm < =tol as zero\n    void setPivotThreshold(const RealScalar& tol)\n    {\n      m_useDefaultThreshold = false;\n      m_tolerance = tol;\n    }\n    \n    /** \\returns a pointer to the SPQR workspace */\n    cholmod_common *cholmodCommon() const { return &m_cc; }\n    \n    \n    /** \\brief Reports whether previous computation was successful.\n      *\n      * \\returns \\c Success if computation was succesful,\n      *          \\c NumericalIssue if the sparse QR can not be computed\n      */\n    ComputationInfo info() const\n    {\n      eigen_assert(m_isInitialized && \"Decomposition is not initialized.\");\n      return m_info;\n    }\n  protected:\n    bool m_analysisIsOk;\n    bool m_factorizationIsOk;\n    mutable bool m_isRUpToDate;\n    mutable ComputationInfo m_info;\n    int m_ordering; // Ordering method to use, see SPQR's manual\n    int m_allow_tol; // Allow to use some tolerance during numerical factorization.\n    RealScalar m_tolerance; // treat columns with 2-norm below this tolerance as zero\n    mutable cholmod_sparse *m_cR; // The sparse R factor in cholmod format\n    mutable MatrixType m_R; // The sparse matrix R in Eigen format\n    mutable StorageIndex *m_E; // The permutation applied to columns\n    mutable cholmod_sparse *m_H;  //The householder vectors\n    mutable StorageIndex *m_HPinv; // The row permutation of H\n    mutable cholmod_dense *m_HTau; // The Householder coefficients\n    mutable Index m_rank; // The rank of the matrix\n    mutable cholmod_common m_cc; // Workspace and parameters\n    bool m_useDefaultThreshold;     // Use default threshold\n    Index m_rows;\n    template<typename ,typename > friend struct SPQR_QProduct;\n};\n\ntemplate <typename SPQRType, typename Derived>\nstruct SPQR_QProduct : ReturnByValue<SPQR_QProduct<SPQRType,Derived> >\n{\n  typedef typename SPQRType::Scalar Scalar;\n  typedef typename SPQRType::StorageIndex StorageIndex;\n  //Define the constructor to get reference to argument types\n  SPQR_QProduct(const SPQRType& spqr, const Derived& other, bool transpose) : m_spqr(spqr),m_other(other),m_transpose(transpose) {}\n  \n  inline Index rows() const { return m_transpose ? m_spqr.rows() : m_spqr.cols(); }\n  inline Index cols() const { return m_other.cols(); }\n  // Assign to a vector\n  template<typename ResType>\n  void evalTo(ResType& res) const\n  {\n    cholmod_dense y_cd;\n    cholmod_dense *x_cd; \n    int method = m_transpose ? SPQR_QTX : SPQR_QX; \n    cholmod_common *cc = m_spqr.cholmodCommon();\n    y_cd = viewAsCholmod(m_other.const_cast_derived());\n    x_cd = SuiteSparseQR_qmult<Scalar>(method, m_spqr.m_H, m_spqr.m_HTau, m_spqr.m_HPinv, &y_cd, cc);\n    res = Matrix<Scalar,ResType::RowsAtCompileTime,ResType::ColsAtCompileTime>::Map(reinterpret_cast<Scalar*>(x_cd->x), x_cd->nrow, x_cd->ncol);\n    cholmod_l_free_dense(&x_cd, cc);\n  }\n  const SPQRType& m_spqr; \n  const Derived& m_other; \n  bool m_transpose; \n  \n};\ntemplate<typename SPQRType>\nstruct SPQRMatrixQReturnType{\n  \n  SPQRMatrixQReturnType(const SPQRType& spqr) : m_spqr(spqr) {}\n  template<typename Derived>\n  SPQR_QProduct<SPQRType, Derived> operator*(const MatrixBase<Derived>& other)\n  {\n    return SPQR_QProduct<SPQRType,Derived>(m_spqr,other.derived(),false);\n  }\n  SPQRMatrixQTransposeReturnType<SPQRType> adjoint() const\n  {\n    return SPQRMatrixQTransposeReturnType<SPQRType>(m_spqr);\n  }\n  // To use for operations with the transpose of Q\n  SPQRMatrixQTransposeReturnType<SPQRType> transpose() const\n  {\n    return SPQRMatrixQTransposeReturnType<SPQRType>(m_spqr);\n  }\n  const SPQRType& m_spqr;\n};\n\ntemplate<typename SPQRType>\nstruct SPQRMatrixQTransposeReturnType{\n  SPQRMatrixQTransposeReturnType(const SPQRType& spqr) : m_spqr(spqr) {}\n  template<typename Derived>\n  SPQR_QProduct<SPQRType,Derived> operator*(const MatrixBase<Derived>& other)\n  {\n    return SPQR_QProduct<SPQRType,Derived>(m_spqr,other.derived(), true);\n  }\n  const SPQRType& m_spqr;\n};\n\n}// End namespace Eigen\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SVD/BDCSVD.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n// \n// We used the \"A Divide-And-Conquer Algorithm for the Bidiagonal SVD\"\n// research report written by Ming Gu and Stanley C.Eisenstat\n// The code variable names correspond to the names they used in their \n// report\n//\n// Copyright (C) 2013 Gauthier Brun <brun.gauthier@gmail.com>\n// Copyright (C) 2013 Nicolas Carre <nicolas.carre@ensimag.fr>\n// Copyright (C) 2013 Jean Ceccato <jean.ceccato@ensimag.fr>\n// Copyright (C) 2013 Pierre Zoppitelli <pierre.zoppitelli@ensimag.fr>\n// Copyright (C) 2013 Jitse Niesen <jitse@maths.leeds.ac.uk>\n// Copyright (C) 2014-2016 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_BDCSVD_H\n#define EIGEN_BDCSVD_H\n// #define EIGEN_BDCSVD_DEBUG_VERBOSE\n// #define EIGEN_BDCSVD_SANITY_CHECKS\n\nnamespace Eigen {\n\n#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE\nIOFormat bdcsvdfmt(8, 0, \", \", \"\\n\", \"  [\", \"]\");\n#endif\n  \ntemplate<typename _MatrixType> class BDCSVD;\n\nnamespace internal {\n\ntemplate<typename _MatrixType> \nstruct traits<BDCSVD<_MatrixType> >\n{\n  typedef _MatrixType MatrixType;\n};  \n\n} // end namespace internal\n  \n  \n/** \\ingroup SVD_Module\n *\n *\n * \\class BDCSVD\n *\n * \\brief class Bidiagonal Divide and Conquer SVD\n *\n * \\tparam _MatrixType the type of the matrix of which we are computing the SVD decomposition\n *\n * This class first reduces the input matrix to bi-diagonal form using class UpperBidiagonalization,\n * and then performs a divide-and-conquer diagonalization. Small blocks are diagonalized using class JacobiSVD.\n * You can control the switching size with the setSwitchSize() method, default is 16.\n * For small matrice (<16), it is thus preferable to directly use JacobiSVD. For larger ones, BDCSVD is highly\n * recommended and can several order of magnitude faster.\n *\n * \\warning this algorithm is unlikely to provide accurate result when compiled with unsafe math optimizations.\n * For instance, this concerns Intel's compiler (ICC), which perfroms such optimization by default unless\n * you compile with the \\c -fp-model \\c precise option. Likewise, the \\c -ffast-math option of GCC or clang will\n * significantly degrade the accuracy.\n *\n * \\sa class JacobiSVD\n */\ntemplate<typename _MatrixType> \nclass BDCSVD : public SVDBase<BDCSVD<_MatrixType> >\n{\n  typedef SVDBase<BDCSVD> Base;\n    \npublic:\n  using Base::rows;\n  using Base::cols;\n  using Base::computeU;\n  using Base::computeV;\n  \n  typedef _MatrixType MatrixType;\n  typedef typename MatrixType::Scalar Scalar;\n  typedef typename NumTraits<typename MatrixType::Scalar>::Real RealScalar;\n  enum {\n    RowsAtCompileTime = MatrixType::RowsAtCompileTime, \n    ColsAtCompileTime = MatrixType::ColsAtCompileTime, \n    DiagSizeAtCompileTime = EIGEN_SIZE_MIN_PREFER_DYNAMIC(RowsAtCompileTime, ColsAtCompileTime), \n    MaxRowsAtCompileTime = MatrixType::MaxRowsAtCompileTime, \n    MaxColsAtCompileTime = MatrixType::MaxColsAtCompileTime, \n    MaxDiagSizeAtCompileTime = EIGEN_SIZE_MIN_PREFER_FIXED(MaxRowsAtCompileTime, MaxColsAtCompileTime), \n    MatrixOptions = MatrixType::Options\n  };\n\n  typedef typename Base::MatrixUType MatrixUType;\n  typedef typename Base::MatrixVType MatrixVType;\n  typedef typename Base::SingularValuesType SingularValuesType;\n  \n  typedef Matrix<Scalar, Dynamic, Dynamic, ColMajor> MatrixX;\n  typedef Matrix<RealScalar, Dynamic, Dynamic, ColMajor> MatrixXr;\n  typedef Matrix<RealScalar, Dynamic, 1> VectorType;\n  typedef Array<RealScalar, Dynamic, 1> ArrayXr;\n  typedef Array<Index,1,Dynamic> ArrayXi;\n  typedef Ref<ArrayXr> ArrayRef;\n  typedef Ref<ArrayXi> IndicesRef;\n\n  /** \\brief Default Constructor.\n   *\n   * The default constructor is useful in cases in which the user intends to\n   * perform decompositions via BDCSVD::compute(const MatrixType&).\n   */\n  BDCSVD() : m_algoswap(16), m_numIters(0)\n  {}\n\n\n  /** \\brief Default Constructor with memory preallocation\n   *\n   * Like the default constructor but with preallocation of the internal data\n   * according to the specified problem size.\n   * \\sa BDCSVD()\n   */\n  BDCSVD(Index rows, Index cols, unsigned int computationOptions = 0)\n    : m_algoswap(16), m_numIters(0)\n  {\n    allocate(rows, cols, computationOptions);\n  }\n\n  /** \\brief Constructor performing the decomposition of given matrix.\n   *\n   * \\param matrix the matrix to decompose\n   * \\param computationOptions optional parameter allowing to specify if you want full or thin U or V unitaries to be computed.\n   *                           By default, none is computed. This is a bit - field, the possible bits are #ComputeFullU, #ComputeThinU, \n   *                           #ComputeFullV, #ComputeThinV.\n   *\n   * Thin unitaries are only available if your matrix type has a Dynamic number of columns (for example MatrixXf). They also are not\n   * available with the (non - default) FullPivHouseholderQR preconditioner.\n   */\n  BDCSVD(const MatrixType& matrix, unsigned int computationOptions = 0)\n    : m_algoswap(16), m_numIters(0)\n  {\n    compute(matrix, computationOptions);\n  }\n\n  ~BDCSVD() \n  {\n  }\n  \n  /** \\brief Method performing the decomposition of given matrix using custom options.\n   *\n   * \\param matrix the matrix to decompose\n   * \\param computationOptions optional parameter allowing to specify if you want full or thin U or V unitaries to be computed.\n   *                           By default, none is computed. This is a bit - field, the possible bits are #ComputeFullU, #ComputeThinU, \n   *                           #ComputeFullV, #ComputeThinV.\n   *\n   * Thin unitaries are only available if your matrix type has a Dynamic number of columns (for example MatrixXf). They also are not\n   * available with the (non - default) FullPivHouseholderQR preconditioner.\n   */\n  BDCSVD& compute(const MatrixType& matrix, unsigned int computationOptions);\n\n  /** \\brief Method performing the decomposition of given matrix using current options.\n   *\n   * \\param matrix the matrix to decompose\n   *\n   * This method uses the current \\a computationOptions, as already passed to the constructor or to compute(const MatrixType&, unsigned int).\n   */\n  BDCSVD& compute(const MatrixType& matrix)\n  {\n    return compute(matrix, this->m_computationOptions);\n  }\n\n  void setSwitchSize(int s) \n  {\n    eigen_assert(s>3 && \"BDCSVD the size of the algo switch has to be greater than 3\");\n    m_algoswap = s;\n  }\n \nprivate:\n  void allocate(Index rows, Index cols, unsigned int computationOptions);\n  void divide(Index firstCol, Index lastCol, Index firstRowW, Index firstColW, Index shift);\n  void computeSVDofM(Index firstCol, Index n, MatrixXr& U, VectorType& singVals, MatrixXr& V);\n  void computeSingVals(const ArrayRef& col0, const ArrayRef& diag, const IndicesRef& perm, VectorType& singVals, ArrayRef shifts, ArrayRef mus);\n  void perturbCol0(const ArrayRef& col0, const ArrayRef& diag, const IndicesRef& perm, const VectorType& singVals, const ArrayRef& shifts, const ArrayRef& mus, ArrayRef zhat);\n  void computeSingVecs(const ArrayRef& zhat, const ArrayRef& diag, const IndicesRef& perm, const VectorType& singVals, const ArrayRef& shifts, const ArrayRef& mus, MatrixXr& U, MatrixXr& V);\n  void deflation43(Index firstCol, Index shift, Index i, Index size);\n  void deflation44(Index firstColu , Index firstColm, Index firstRowW, Index firstColW, Index i, Index j, Index size);\n  void deflation(Index firstCol, Index lastCol, Index k, Index firstRowW, Index firstColW, Index shift);\n  template<typename HouseholderU, typename HouseholderV, typename NaiveU, typename NaiveV>\n  void copyUV(const HouseholderU &householderU, const HouseholderV &householderV, const NaiveU &naiveU, const NaiveV &naivev);\n  void structured_update(Block<MatrixXr,Dynamic,Dynamic> A, const MatrixXr &B, Index n1);\n  static RealScalar secularEq(RealScalar x, const ArrayRef& col0, const ArrayRef& diag, const IndicesRef &perm, const ArrayRef& diagShifted, RealScalar shift);\n\nprotected:\n  MatrixXr m_naiveU, m_naiveV;\n  MatrixXr m_computed;\n  Index m_nRec;\n  ArrayXr m_workspace;\n  ArrayXi m_workspaceI;\n  int m_algoswap;\n  bool m_isTranspose, m_compU, m_compV;\n  \n  using Base::m_singularValues;\n  using Base::m_diagSize;\n  using Base::m_computeFullU;\n  using Base::m_computeFullV;\n  using Base::m_computeThinU;\n  using Base::m_computeThinV;\n  using Base::m_matrixU;\n  using Base::m_matrixV;\n  using Base::m_isInitialized;\n  using Base::m_nonzeroSingularValues;\n\npublic:  \n  int m_numIters;\n}; //end class BDCSVD\n\n\n// Method to allocate and initialize matrix and attributes\ntemplate<typename MatrixType>\nvoid BDCSVD<MatrixType>::allocate(Index rows, Index cols, unsigned int computationOptions)\n{\n  m_isTranspose = (cols > rows);\n\n  if (Base::allocate(rows, cols, computationOptions))\n    return;\n  \n  m_computed = MatrixXr::Zero(m_diagSize + 1, m_diagSize );\n  m_compU = computeV();\n  m_compV = computeU();\n  if (m_isTranspose)\n    std::swap(m_compU, m_compV);\n  \n  if (m_compU) m_naiveU = MatrixXr::Zero(m_diagSize + 1, m_diagSize + 1 );\n  else         m_naiveU = MatrixXr::Zero(2, m_diagSize + 1 );\n  \n  if (m_compV) m_naiveV = MatrixXr::Zero(m_diagSize, m_diagSize);\n  \n  m_workspace.resize((m_diagSize+1)*(m_diagSize+1)*3);\n  m_workspaceI.resize(3*m_diagSize);\n}// end allocate\n\ntemplate<typename MatrixType>\nBDCSVD<MatrixType>& BDCSVD<MatrixType>::compute(const MatrixType& matrix, unsigned int computationOptions) \n{\n#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE\n  std::cout << \"\\n\\n\\n======================================================================================================================\\n\\n\\n\";\n#endif\n  allocate(matrix.rows(), matrix.cols(), computationOptions);\n  using std::abs;\n\n  const RealScalar considerZero = (std::numeric_limits<RealScalar>::min)();\n  \n  //**** step -1 - If the problem is too small, directly falls back to JacobiSVD and return\n  if(matrix.cols() < m_algoswap)\n  {\n    // FIXME this line involves temporaries\n    JacobiSVD<MatrixType> jsvd(matrix,computationOptions);\n    if(computeU()) m_matrixU = jsvd.matrixU();\n    if(computeV()) m_matrixV = jsvd.matrixV();\n    m_singularValues = jsvd.singularValues();\n    m_nonzeroSingularValues = jsvd.nonzeroSingularValues();\n    m_isInitialized = true;\n    return *this;\n  }\n  \n  //**** step 0 - Copy the input matrix and apply scaling to reduce over/under-flows\n  RealScalar scale = matrix.cwiseAbs().maxCoeff();\n  if(scale==RealScalar(0)) scale = RealScalar(1);\n  MatrixX copy;\n  if (m_isTranspose) copy = matrix.adjoint()/scale;\n  else               copy = matrix/scale;\n  \n  //**** step 1 - Bidiagonalization\n  // FIXME this line involves temporaries\n  internal::UpperBidiagonalization<MatrixX> bid(copy);\n\n  //**** step 2 - Divide & Conquer\n  m_naiveU.setZero();\n  m_naiveV.setZero();\n  // FIXME this line involves a temporary matrix\n  m_computed.topRows(m_diagSize) = bid.bidiagonal().toDenseMatrix().transpose();\n  m_computed.template bottomRows<1>().setZero();\n  divide(0, m_diagSize - 1, 0, 0, 0);\n\n  //**** step 3 - Copy singular values and vectors\n  for (int i=0; i<m_diagSize; i++)\n  {\n    RealScalar a = abs(m_computed.coeff(i, i));\n    m_singularValues.coeffRef(i) = a * scale;\n    if (a<considerZero)\n    {\n      m_nonzeroSingularValues = i;\n      m_singularValues.tail(m_diagSize - i - 1).setZero();\n      break;\n    }\n    else if (i == m_diagSize - 1)\n    {\n      m_nonzeroSingularValues = i + 1;\n      break;\n    }\n  }\n\n#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE\n//   std::cout << \"m_naiveU\\n\" << m_naiveU << \"\\n\\n\";\n//   std::cout << \"m_naiveV\\n\" << m_naiveV << \"\\n\\n\";\n#endif\n  if(m_isTranspose) copyUV(bid.householderV(), bid.householderU(), m_naiveV, m_naiveU);\n  else              copyUV(bid.householderU(), bid.householderV(), m_naiveU, m_naiveV);\n\n  m_isInitialized = true;\n  return *this;\n}// end compute\n\n\ntemplate<typename MatrixType>\ntemplate<typename HouseholderU, typename HouseholderV, typename NaiveU, typename NaiveV>\nvoid BDCSVD<MatrixType>::copyUV(const HouseholderU &householderU, const HouseholderV &householderV, const NaiveU &naiveU, const NaiveV &naiveV)\n{\n  // Note exchange of U and V: m_matrixU is set from m_naiveV and vice versa\n  if (computeU())\n  {\n    Index Ucols = m_computeThinU ? m_diagSize : householderU.cols();\n    m_matrixU = MatrixX::Identity(householderU.cols(), Ucols);\n    m_matrixU.topLeftCorner(m_diagSize, m_diagSize) = naiveV.template cast<Scalar>().topLeftCorner(m_diagSize, m_diagSize);\n    householderU.applyThisOnTheLeft(m_matrixU); // FIXME this line involves a temporary buffer\n  }\n  if (computeV())\n  {\n    Index Vcols = m_computeThinV ? m_diagSize : householderV.cols();\n    m_matrixV = MatrixX::Identity(householderV.cols(), Vcols);\n    m_matrixV.topLeftCorner(m_diagSize, m_diagSize) = naiveU.template cast<Scalar>().topLeftCorner(m_diagSize, m_diagSize);\n    householderV.applyThisOnTheLeft(m_matrixV); // FIXME this line involves a temporary buffer\n  }\n}\n\n/** \\internal\n  * Performs A = A * B exploiting the special structure of the matrix A. Splitting A as:\n  *  A = [A1]\n  *      [A2]\n  * such that A1.rows()==n1, then we assume that at least half of the columns of A1 and A2 are zeros.\n  * We can thus pack them prior to the the matrix product. However, this is only worth the effort if the matrix is large\n  * enough.\n  */\ntemplate<typename MatrixType>\nvoid BDCSVD<MatrixType>::structured_update(Block<MatrixXr,Dynamic,Dynamic> A, const MatrixXr &B, Index n1)\n{\n  Index n = A.rows();\n  if(n>100)\n  {\n    // If the matrices are large enough, let's exploit the sparse structure of A by\n    // splitting it in half (wrt n1), and packing the non-zero columns.\n    Index n2 = n - n1;\n    Map<MatrixXr> A1(m_workspace.data()      , n1, n);\n    Map<MatrixXr> A2(m_workspace.data()+ n1*n, n2, n);\n    Map<MatrixXr> B1(m_workspace.data()+  n*n, n,  n);\n    Map<MatrixXr> B2(m_workspace.data()+2*n*n, n,  n);\n    Index k1=0, k2=0;\n    for(Index j=0; j<n; ++j)\n    {\n      if( (A.col(j).head(n1).array()!=0).any() )\n      {\n        A1.col(k1) = A.col(j).head(n1);\n        B1.row(k1) = B.row(j);\n        ++k1;\n      }\n      if( (A.col(j).tail(n2).array()!=0).any() )\n      {\n        A2.col(k2) = A.col(j).tail(n2);\n        B2.row(k2) = B.row(j);\n        ++k2;\n      }\n    }\n  \n    A.topRows(n1).noalias()    = A1.leftCols(k1) * B1.topRows(k1);\n    A.bottomRows(n2).noalias() = A2.leftCols(k2) * B2.topRows(k2);\n  }\n  else\n  {\n    Map<MatrixXr,Aligned> tmp(m_workspace.data(),n,n);\n    tmp.noalias() = A*B;\n    A = tmp;\n  }\n}\n\n// The divide algorithm is done \"in place\", we are always working on subsets of the same matrix. The divide methods takes as argument the \n// place of the submatrix we are currently working on.\n\n//@param firstCol : The Index of the first column of the submatrix of m_computed and for m_naiveU;\n//@param lastCol : The Index of the last column of the submatrix of m_computed and for m_naiveU; \n// lastCol + 1 - firstCol is the size of the submatrix.\n//@param firstRowW : The Index of the first row of the matrix W that we are to change. (see the reference paper section 1 for more information on W)\n//@param firstRowW : Same as firstRowW with the column.\n//@param shift : Each time one takes the left submatrix, one must add 1 to the shift. Why? Because! We actually want the last column of the U submatrix \n// to become the first column (*coeff) and to shift all the other columns to the right. There are more details on the reference paper.\ntemplate<typename MatrixType>\nvoid BDCSVD<MatrixType>::divide (Index firstCol, Index lastCol, Index firstRowW, Index firstColW, Index shift)\n{\n  // requires rows = cols + 1;\n  using std::pow;\n  using std::sqrt;\n  using std::abs;\n  const Index n = lastCol - firstCol + 1;\n  const Index k = n/2;\n  const RealScalar considerZero = (std::numeric_limits<RealScalar>::min)();\n  RealScalar alphaK;\n  RealScalar betaK; \n  RealScalar r0; \n  RealScalar lambda, phi, c0, s0;\n  VectorType l, f;\n  // We use the other algorithm which is more efficient for small \n  // matrices.\n  if (n < m_algoswap)\n  {\n    // FIXME this line involves temporaries\n    JacobiSVD<MatrixXr> b(m_computed.block(firstCol, firstCol, n + 1, n), ComputeFullU | (m_compV ? ComputeFullV : 0));\n    if (m_compU)\n      m_naiveU.block(firstCol, firstCol, n + 1, n + 1).real() = b.matrixU();\n    else \n    {\n      m_naiveU.row(0).segment(firstCol, n + 1).real() = b.matrixU().row(0);\n      m_naiveU.row(1).segment(firstCol, n + 1).real() = b.matrixU().row(n);\n    }\n    if (m_compV) m_naiveV.block(firstRowW, firstColW, n, n).real() = b.matrixV();\n    m_computed.block(firstCol + shift, firstCol + shift, n + 1, n).setZero();\n    m_computed.diagonal().segment(firstCol + shift, n) = b.singularValues().head(n);\n    return;\n  }\n  // We use the divide and conquer algorithm\n  alphaK =  m_computed(firstCol + k, firstCol + k);\n  betaK = m_computed(firstCol + k + 1, firstCol + k);\n  // The divide must be done in that order in order to have good results. Divide change the data inside the submatrices\n  // and the divide of the right submatrice reads one column of the left submatrice. That's why we need to treat the \n  // right submatrix before the left one. \n  divide(k + 1 + firstCol, lastCol, k + 1 + firstRowW, k + 1 + firstColW, shift);\n  divide(firstCol, k - 1 + firstCol, firstRowW, firstColW + 1, shift + 1);\n\n  if (m_compU)\n  {\n    lambda = m_naiveU(firstCol + k, firstCol + k);\n    phi = m_naiveU(firstCol + k + 1, lastCol + 1);\n  } \n  else \n  {\n    lambda = m_naiveU(1, firstCol + k);\n    phi = m_naiveU(0, lastCol + 1);\n  }\n  r0 = sqrt((abs(alphaK * lambda) * abs(alphaK * lambda)) + abs(betaK * phi) * abs(betaK * phi));\n  if (m_compU)\n  {\n    l = m_naiveU.row(firstCol + k).segment(firstCol, k);\n    f = m_naiveU.row(firstCol + k + 1).segment(firstCol + k + 1, n - k - 1);\n  } \n  else \n  {\n    l = m_naiveU.row(1).segment(firstCol, k);\n    f = m_naiveU.row(0).segment(firstCol + k + 1, n - k - 1);\n  }\n  if (m_compV) m_naiveV(firstRowW+k, firstColW) = 1;\n  if (r0<considerZero)\n  {\n    c0 = 1;\n    s0 = 0;\n  }\n  else\n  {\n    c0 = alphaK * lambda / r0;\n    s0 = betaK * phi / r0;\n  }\n  \n#ifdef EIGEN_BDCSVD_SANITY_CHECKS\n  assert(m_naiveU.allFinite());\n  assert(m_naiveV.allFinite());\n  assert(m_computed.allFinite());\n#endif\n  \n  if (m_compU)\n  {\n    MatrixXr q1 (m_naiveU.col(firstCol + k).segment(firstCol, k + 1));     \n    // we shiftW Q1 to the right\n    for (Index i = firstCol + k - 1; i >= firstCol; i--) \n      m_naiveU.col(i + 1).segment(firstCol, k + 1) = m_naiveU.col(i).segment(firstCol, k + 1);\n    // we shift q1 at the left with a factor c0\n    m_naiveU.col(firstCol).segment( firstCol, k + 1) = (q1 * c0);\n    // last column = q1 * - s0\n    m_naiveU.col(lastCol + 1).segment(firstCol, k + 1) = (q1 * ( - s0));\n    // first column = q2 * s0\n    m_naiveU.col(firstCol).segment(firstCol + k + 1, n - k) = m_naiveU.col(lastCol + 1).segment(firstCol + k + 1, n - k) * s0; \n    // q2 *= c0\n    m_naiveU.col(lastCol + 1).segment(firstCol + k + 1, n - k) *= c0;\n  } \n  else \n  {\n    RealScalar q1 = m_naiveU(0, firstCol + k);\n    // we shift Q1 to the right\n    for (Index i = firstCol + k - 1; i >= firstCol; i--) \n      m_naiveU(0, i + 1) = m_naiveU(0, i);\n    // we shift q1 at the left with a factor c0\n    m_naiveU(0, firstCol) = (q1 * c0);\n    // last column = q1 * - s0\n    m_naiveU(0, lastCol + 1) = (q1 * ( - s0));\n    // first column = q2 * s0\n    m_naiveU(1, firstCol) = m_naiveU(1, lastCol + 1) *s0; \n    // q2 *= c0\n    m_naiveU(1, lastCol + 1) *= c0;\n    m_naiveU.row(1).segment(firstCol + 1, k).setZero();\n    m_naiveU.row(0).segment(firstCol + k + 1, n - k - 1).setZero();\n  }\n  \n#ifdef EIGEN_BDCSVD_SANITY_CHECKS\n  assert(m_naiveU.allFinite());\n  assert(m_naiveV.allFinite());\n  assert(m_computed.allFinite());\n#endif\n  \n  m_computed(firstCol + shift, firstCol + shift) = r0;\n  m_computed.col(firstCol + shift).segment(firstCol + shift + 1, k) = alphaK * l.transpose().real();\n  m_computed.col(firstCol + shift).segment(firstCol + shift + k + 1, n - k - 1) = betaK * f.transpose().real();\n\n#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE\n  ArrayXr tmp1 = (m_computed.block(firstCol+shift, firstCol+shift, n, n)).jacobiSvd().singularValues();\n#endif\n  // Second part: try to deflate singular values in combined matrix\n  deflation(firstCol, lastCol, k, firstRowW, firstColW, shift);\n#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE\n  ArrayXr tmp2 = (m_computed.block(firstCol+shift, firstCol+shift, n, n)).jacobiSvd().singularValues();\n  std::cout << \"\\n\\nj1 = \" << tmp1.transpose().format(bdcsvdfmt) << \"\\n\";\n  std::cout << \"j2 = \" << tmp2.transpose().format(bdcsvdfmt) << \"\\n\\n\";\n  std::cout << \"err:      \" << ((tmp1-tmp2).abs()>1e-12*tmp2.abs()).transpose() << \"\\n\";\n  static int count = 0;\n  std::cout << \"# \" << ++count << \"\\n\\n\";\n  assert((tmp1-tmp2).matrix().norm() < 1e-14*tmp2.matrix().norm());\n//   assert(count<681);\n//   assert(((tmp1-tmp2).abs()<1e-13*tmp2.abs()).all());\n#endif\n  \n  // Third part: compute SVD of combined matrix\n  MatrixXr UofSVD, VofSVD;\n  VectorType singVals;\n  computeSVDofM(firstCol + shift, n, UofSVD, singVals, VofSVD);\n  \n#ifdef EIGEN_BDCSVD_SANITY_CHECKS\n  assert(UofSVD.allFinite());\n  assert(VofSVD.allFinite());\n#endif\n  \n  if (m_compU)\n    structured_update(m_naiveU.block(firstCol, firstCol, n + 1, n + 1), UofSVD, (n+2)/2);\n  else\n  {\n    Map<Matrix<RealScalar,2,Dynamic>,Aligned> tmp(m_workspace.data(),2,n+1);\n    tmp.noalias() = m_naiveU.middleCols(firstCol, n+1) * UofSVD;\n    m_naiveU.middleCols(firstCol, n + 1) = tmp;\n  }\n  \n  if (m_compV)  structured_update(m_naiveV.block(firstRowW, firstColW, n, n), VofSVD, (n+1)/2);\n  \n#ifdef EIGEN_BDCSVD_SANITY_CHECKS\n  assert(m_naiveU.allFinite());\n  assert(m_naiveV.allFinite());\n  assert(m_computed.allFinite());\n#endif\n  \n  m_computed.block(firstCol + shift, firstCol + shift, n, n).setZero();\n  m_computed.block(firstCol + shift, firstCol + shift, n, n).diagonal() = singVals;\n}// end divide\n\n// Compute SVD of m_computed.block(firstCol, firstCol, n + 1, n); this block only has non-zeros in\n// the first column and on the diagonal and has undergone deflation, so diagonal is in increasing\n// order except for possibly the (0,0) entry. The computed SVD is stored U, singVals and V, except\n// that if m_compV is false, then V is not computed. Singular values are sorted in decreasing order.\n//\n// TODO Opportunities for optimization: better root finding algo, better stopping criterion, better\n// handling of round-off errors, be consistent in ordering\n// For instance, to solve the secular equation using FMM, see http://www.stat.uchicago.edu/~lekheng/courses/302/classics/greengard-rokhlin.pdf\ntemplate <typename MatrixType>\nvoid BDCSVD<MatrixType>::computeSVDofM(Index firstCol, Index n, MatrixXr& U, VectorType& singVals, MatrixXr& V)\n{\n  const RealScalar considerZero = (std::numeric_limits<RealScalar>::min)();\n  using std::abs;\n  ArrayRef col0 = m_computed.col(firstCol).segment(firstCol, n);\n  m_workspace.head(n) =  m_computed.block(firstCol, firstCol, n, n).diagonal();\n  ArrayRef diag = m_workspace.head(n);\n  diag(0) = 0;\n\n  // Allocate space for singular values and vectors\n  singVals.resize(n);\n  U.resize(n+1, n+1);\n  if (m_compV) V.resize(n, n);\n\n#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE\n  if (col0.hasNaN() || diag.hasNaN())\n    std::cout << \"\\n\\nHAS NAN\\n\\n\";\n#endif\n  \n  // Many singular values might have been deflated, the zero ones have been moved to the end,\n  // but others are interleaved and we must ignore them at this stage.\n  // To this end, let's compute a permutation skipping them:\n  Index actual_n = n;\n  while(actual_n>1 && diag(actual_n-1)==0) --actual_n;\n  Index m = 0; // size of the deflated problem\n  for(Index k=0;k<actual_n;++k)\n    if(abs(col0(k))>considerZero)\n      m_workspaceI(m++) = k;\n  Map<ArrayXi> perm(m_workspaceI.data(),m);\n  \n  Map<ArrayXr> shifts(m_workspace.data()+1*n, n);\n  Map<ArrayXr> mus(m_workspace.data()+2*n, n);\n  Map<ArrayXr> zhat(m_workspace.data()+3*n, n);\n\n#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE\n  std::cout << \"computeSVDofM using:\\n\";\n  std::cout << \"  z: \" << col0.transpose() << \"\\n\";\n  std::cout << \"  d: \" << diag.transpose() << \"\\n\";\n#endif\n  \n  // Compute singVals, shifts, and mus\n  computeSingVals(col0, diag, perm, singVals, shifts, mus);\n  \n#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE\n  std::cout << \"  j:        \" << (m_computed.block(firstCol, firstCol, n, n)).jacobiSvd().singularValues().transpose().reverse() << \"\\n\\n\";\n  std::cout << \"  sing-val: \" << singVals.transpose() << \"\\n\";\n  std::cout << \"  mu:       \" << mus.transpose() << \"\\n\";\n  std::cout << \"  shift:    \" << shifts.transpose() << \"\\n\";\n  \n  {\n    Index actual_n = n;\n    while(actual_n>1 && abs(col0(actual_n-1))<considerZero) --actual_n;\n    std::cout << \"\\n\\n    mus:    \" << mus.head(actual_n).transpose() << \"\\n\\n\";\n    std::cout << \"    check1 (expect0) : \" << ((singVals.array()-(shifts+mus)) / singVals.array()).head(actual_n).transpose() << \"\\n\\n\";\n    std::cout << \"    check2 (>0)      : \" << ((singVals.array()-diag) / singVals.array()).head(actual_n).transpose() << \"\\n\\n\";\n    std::cout << \"    check3 (>0)      : \" << ((diag.segment(1,actual_n-1)-singVals.head(actual_n-1).array()) / singVals.head(actual_n-1).array()).transpose() << \"\\n\\n\\n\";\n    std::cout << \"    check4 (>0)      : \" << ((singVals.segment(1,actual_n-1)-singVals.head(actual_n-1))).transpose() << \"\\n\\n\\n\";\n  }\n#endif\n  \n#ifdef EIGEN_BDCSVD_SANITY_CHECKS\n  assert(singVals.allFinite());\n  assert(mus.allFinite());\n  assert(shifts.allFinite());\n#endif\n  \n  // Compute zhat\n  perturbCol0(col0, diag, perm, singVals, shifts, mus, zhat);\n#ifdef  EIGEN_BDCSVD_DEBUG_VERBOSE\n  std::cout << \"  zhat: \" << zhat.transpose() << \"\\n\";\n#endif\n  \n#ifdef EIGEN_BDCSVD_SANITY_CHECKS\n  assert(zhat.allFinite());\n#endif\n  \n  computeSingVecs(zhat, diag, perm, singVals, shifts, mus, U, V);\n  \n#ifdef  EIGEN_BDCSVD_DEBUG_VERBOSE\n  std::cout << \"U^T U: \" << (U.transpose() * U - MatrixXr(MatrixXr::Identity(U.cols(),U.cols()))).norm() << \"\\n\";\n  std::cout << \"V^T V: \" << (V.transpose() * V - MatrixXr(MatrixXr::Identity(V.cols(),V.cols()))).norm() << \"\\n\";\n#endif\n  \n#ifdef EIGEN_BDCSVD_SANITY_CHECKS\n  assert(U.allFinite());\n  assert(V.allFinite());\n  assert((U.transpose() * U - MatrixXr(MatrixXr::Identity(U.cols(),U.cols()))).norm() < 1e-14 * n);\n  assert((V.transpose() * V - MatrixXr(MatrixXr::Identity(V.cols(),V.cols()))).norm() < 1e-14 * n);\n  assert(m_naiveU.allFinite());\n  assert(m_naiveV.allFinite());\n  assert(m_computed.allFinite());\n#endif\n  \n  // Because of deflation, the singular values might not be completely sorted.\n  // Fortunately, reordering them is a O(n) problem\n  for(Index i=0; i<actual_n-1; ++i)\n  {\n    if(singVals(i)>singVals(i+1))\n    {\n      using std::swap;\n      swap(singVals(i),singVals(i+1));\n      U.col(i).swap(U.col(i+1));\n      if(m_compV) V.col(i).swap(V.col(i+1));\n    }\n  }\n  \n  // Reverse order so that singular values in increased order\n  // Because of deflation, the zeros singular-values are already at the end\n  singVals.head(actual_n).reverseInPlace();\n  U.leftCols(actual_n).rowwise().reverseInPlace();\n  if (m_compV) V.leftCols(actual_n).rowwise().reverseInPlace();\n  \n#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE\n  JacobiSVD<MatrixXr> jsvd(m_computed.block(firstCol, firstCol, n, n) );\n  std::cout << \"  * j:        \" << jsvd.singularValues().transpose() << \"\\n\\n\";\n  std::cout << \"  * sing-val: \" << singVals.transpose() << \"\\n\";\n//   std::cout << \"  * err:      \" << ((jsvd.singularValues()-singVals)>1e-13*singVals.norm()).transpose() << \"\\n\";\n#endif\n}\n\ntemplate <typename MatrixType>\ntypename BDCSVD<MatrixType>::RealScalar BDCSVD<MatrixType>::secularEq(RealScalar mu, const ArrayRef& col0, const ArrayRef& diag, const IndicesRef &perm, const ArrayRef& diagShifted, RealScalar shift)\n{\n  Index m = perm.size();\n  RealScalar res = 1;\n  for(Index i=0; i<m; ++i)\n  {\n    Index j = perm(i);\n    res += numext::abs2(col0(j)) / ((diagShifted(j) - mu) * (diag(j) + shift + mu));\n  }\n  return res;\n\n}\n\ntemplate <typename MatrixType>\nvoid BDCSVD<MatrixType>::computeSingVals(const ArrayRef& col0, const ArrayRef& diag, const IndicesRef &perm,\n                                         VectorType& singVals, ArrayRef shifts, ArrayRef mus)\n{\n  using std::abs;\n  using std::swap;\n\n  Index n = col0.size();\n  Index actual_n = n;\n  while(actual_n>1 && col0(actual_n-1)==0) --actual_n;\n\n  for (Index k = 0; k < n; ++k)\n  {\n    if (col0(k) == 0 || actual_n==1)\n    {\n      // if col0(k) == 0, then entry is deflated, so singular value is on diagonal\n      // if actual_n==1, then the deflated problem is already diagonalized\n      singVals(k) = k==0 ? col0(0) : diag(k);\n      mus(k) = 0;\n      shifts(k) = k==0 ? col0(0) : diag(k);\n      continue;\n    } \n\n    // otherwise, use secular equation to find singular value\n    RealScalar left = diag(k);\n    RealScalar right; // was: = (k != actual_n-1) ? diag(k+1) : (diag(actual_n-1) + col0.matrix().norm());\n    if(k==actual_n-1)\n      right = (diag(actual_n-1) + col0.matrix().norm());\n    else\n    {\n      // Skip deflated singular values\n      Index l = k+1;\n      while(col0(l)==0) { ++l; eigen_internal_assert(l<actual_n); }\n      right = diag(l);\n    }\n\n    // first decide whether it's closer to the left end or the right end\n    RealScalar mid = left + (right-left) / 2;\n    RealScalar fMid = secularEq(mid, col0, diag, perm, diag, 0);\n#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE\n    std::cout << right-left << \"\\n\";\n    std::cout << \"fMid = \" << fMid << \" \" << secularEq(mid-left, col0, diag, perm, diag-left, left) << \" \" << secularEq(mid-right, col0, diag, perm, diag-right, right)   << \"\\n\";\n    std::cout << \"     = \" << secularEq(0.1*(left+right), col0, diag, perm, diag, 0)\n              << \" \"       << secularEq(0.2*(left+right), col0, diag, perm, diag, 0)\n              << \" \"       << secularEq(0.3*(left+right), col0, diag, perm, diag, 0)\n              << \" \"       << secularEq(0.4*(left+right), col0, diag, perm, diag, 0)\n              << \" \"       << secularEq(0.49*(left+right), col0, diag, perm, diag, 0)\n              << \" \"       << secularEq(0.5*(left+right), col0, diag, perm, diag, 0)\n              << \" \"       << secularEq(0.51*(left+right), col0, diag, perm, diag, 0)\n              << \" \"       << secularEq(0.6*(left+right), col0, diag, perm, diag, 0)\n              << \" \"       << secularEq(0.7*(left+right), col0, diag, perm, diag, 0)\n              << \" \"       << secularEq(0.8*(left+right), col0, diag, perm, diag, 0)\n              << \" \"       << secularEq(0.9*(left+right), col0, diag, perm, diag, 0) << \"\\n\";\n#endif\n    RealScalar shift = (k == actual_n-1 || fMid > 0) ? left : right;\n    \n    // measure everything relative to shift\n    Map<ArrayXr> diagShifted(m_workspace.data()+4*n, n);\n    diagShifted = diag - shift;\n    \n    // initial guess\n    RealScalar muPrev, muCur;\n    if (shift == left)\n    {\n      muPrev = (right - left) * RealScalar(0.1);\n      if (k == actual_n-1) muCur = right - left;\n      else                 muCur = (right - left) * RealScalar(0.5);\n    }\n    else\n    {\n      muPrev = -(right - left) * RealScalar(0.1);\n      muCur = -(right - left) * RealScalar(0.5);\n    }\n\n    RealScalar fPrev = secularEq(muPrev, col0, diag, perm, diagShifted, shift);\n    RealScalar fCur = secularEq(muCur, col0, diag, perm, diagShifted, shift);\n    if (abs(fPrev) < abs(fCur))\n    {\n      swap(fPrev, fCur);\n      swap(muPrev, muCur);\n    }\n\n    // rational interpolation: fit a function of the form a / mu + b through the two previous\n    // iterates and use its zero to compute the next iterate\n    bool useBisection = fPrev*fCur>0;\n    while (fCur!=0 && abs(muCur - muPrev) > 8 * NumTraits<RealScalar>::epsilon() * numext::maxi<RealScalar>(abs(muCur), abs(muPrev)) && abs(fCur - fPrev)>NumTraits<RealScalar>::epsilon() && !useBisection)\n    {\n      ++m_numIters;\n\n      // Find a and b such that the function f(mu) = a / mu + b matches the current and previous samples.\n      RealScalar a = (fCur - fPrev) / (1/muCur - 1/muPrev);\n      RealScalar b = fCur - a / muCur;\n      // And find mu such that f(mu)==0:\n      RealScalar muZero = -a/b;\n      RealScalar fZero = secularEq(muZero, col0, diag, perm, diagShifted, shift);\n      \n      muPrev = muCur;\n      fPrev = fCur;\n      muCur = muZero;\n      fCur = fZero;\n      \n      \n      if (shift == left  && (muCur < 0 || muCur > right - left)) useBisection = true;\n      if (shift == right && (muCur < -(right - left) || muCur > 0)) useBisection = true;\n      if (abs(fCur)>abs(fPrev)) useBisection = true;\n    }\n\n    // fall back on bisection method if rational interpolation did not work\n    if (useBisection)\n    {\n#ifdef  EIGEN_BDCSVD_DEBUG_VERBOSE\n      std::cout << \"useBisection for k = \" << k << \", actual_n = \" << actual_n << \"\\n\";\n#endif\n      RealScalar leftShifted, rightShifted;\n      if (shift == left)\n      {\n        leftShifted = (std::numeric_limits<RealScalar>::min)();\n        // I don't understand why the case k==0 would be special there:\n        // if (k == 0) rightShifted = right - left; else \n        rightShifted = (k==actual_n-1) ? right : ((right - left) * RealScalar(0.6)); // theoretically we can take 0.5, but let's be safe\n      }\n      else\n      {\n        leftShifted = -(right - left) * RealScalar(0.6);\n        rightShifted = -(std::numeric_limits<RealScalar>::min)();\n      }\n      \n      RealScalar fLeft = secularEq(leftShifted, col0, diag, perm, diagShifted, shift);\n\n#if defined EIGEN_INTERNAL_DEBUGGING || defined EIGEN_BDCSVD_DEBUG_VERBOSE\n      RealScalar fRight = secularEq(rightShifted, col0, diag, perm, diagShifted, shift);\n#endif\n\n#ifdef  EIGEN_BDCSVD_DEBUG_VERBOSE\n      if(!(fLeft * fRight<0))\n      {\n        std::cout << \"fLeft: \" << leftShifted << \" - \" << diagShifted.head(10).transpose()  << \"\\n ; \" << bool(left==shift) << \" \" << (left-shift) << \"\\n\";\n        std::cout << k << \" : \" <<  fLeft << \" * \" << fRight << \" == \" << fLeft * fRight << \"  ;  \" << left << \" - \" << right << \" -> \" <<  leftShifted << \" \" << rightShifted << \"   shift=\" << shift << \"\\n\";\n      }\n#endif\n      eigen_internal_assert(fLeft * fRight < 0);\n      \n      while (rightShifted - leftShifted > 2 * NumTraits<RealScalar>::epsilon() * numext::maxi<RealScalar>(abs(leftShifted), abs(rightShifted)))\n      {\n        RealScalar midShifted = (leftShifted + rightShifted) / 2;\n        fMid = secularEq(midShifted, col0, diag, perm, diagShifted, shift);\n        if (fLeft * fMid < 0)\n        {\n          rightShifted = midShifted;\n        }\n        else\n        {\n          leftShifted = midShifted;\n          fLeft = fMid;\n        }\n      }\n\n      muCur = (leftShifted + rightShifted) / 2;\n    }\n      \n    singVals[k] = shift + muCur;\n    shifts[k] = shift;\n    mus[k] = muCur;\n\n    // perturb singular value slightly if it equals diagonal entry to avoid division by zero later\n    // (deflation is supposed to avoid this from happening)\n    // - this does no seem to be necessary anymore -\n//     if (singVals[k] == left) singVals[k] *= 1 + NumTraits<RealScalar>::epsilon();\n//     if (singVals[k] == right) singVals[k] *= 1 - NumTraits<RealScalar>::epsilon();\n  }\n}\n\n\n// zhat is perturbation of col0 for which singular vectors can be computed stably (see Section 3.1)\ntemplate <typename MatrixType>\nvoid BDCSVD<MatrixType>::perturbCol0\n   (const ArrayRef& col0, const ArrayRef& diag, const IndicesRef &perm, const VectorType& singVals,\n    const ArrayRef& shifts, const ArrayRef& mus, ArrayRef zhat)\n{\n  using std::sqrt;\n  Index n = col0.size();\n  Index m = perm.size();\n  if(m==0)\n  {\n    zhat.setZero();\n    return;\n  }\n  Index last = perm(m-1);\n  // The offset permits to skip deflated entries while computing zhat\n  for (Index k = 0; k < n; ++k)\n  {\n    if (col0(k) == 0) // deflated\n      zhat(k) = 0;\n    else\n    {\n      // see equation (3.6)\n      RealScalar dk = diag(k);\n      RealScalar prod = (singVals(last) + dk) * (mus(last) + (shifts(last) - dk));\n\n      for(Index l = 0; l<m; ++l)\n      {\n        Index i = perm(l);\n        if(i!=k)\n        {\n          Index j = i<k ? i : perm(l-1);\n          prod *= ((singVals(j)+dk) / ((diag(i)+dk))) * ((mus(j)+(shifts(j)-dk)) / ((diag(i)-dk)));\n#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE\n          if(i!=k && std::abs(((singVals(j)+dk)*(mus(j)+(shifts(j)-dk)))/((diag(i)+dk)*(diag(i)-dk)) - 1) > 0.9 )\n            std::cout << \"     \" << ((singVals(j)+dk)*(mus(j)+(shifts(j)-dk)))/((diag(i)+dk)*(diag(i)-dk)) << \" == (\" << (singVals(j)+dk) << \" * \" << (mus(j)+(shifts(j)-dk))\n                       << \") / (\" << (diag(i)+dk) << \" * \" << (diag(i)-dk) << \")\\n\";\n#endif\n        }\n      }\n#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE\n      std::cout << \"zhat(\" << k << \") =  sqrt( \" << prod << \")  ;  \" << (singVals(last) + dk) << \" * \" << mus(last) + shifts(last) << \" - \" << dk << \"\\n\";\n#endif\n      RealScalar tmp = sqrt(prod);\n      zhat(k) = col0(k) > 0 ? tmp : -tmp;\n    }\n  }\n}\n\n// compute singular vectors\ntemplate <typename MatrixType>\nvoid BDCSVD<MatrixType>::computeSingVecs\n   (const ArrayRef& zhat, const ArrayRef& diag, const IndicesRef &perm, const VectorType& singVals,\n    const ArrayRef& shifts, const ArrayRef& mus, MatrixXr& U, MatrixXr& V)\n{\n  Index n = zhat.size();\n  Index m = perm.size();\n  \n  for (Index k = 0; k < n; ++k)\n  {\n    if (zhat(k) == 0)\n    {\n      U.col(k) = VectorType::Unit(n+1, k);\n      if (m_compV) V.col(k) = VectorType::Unit(n, k);\n    }\n    else\n    {\n      U.col(k).setZero();\n      for(Index l=0;l<m;++l)\n      {\n        Index i = perm(l);\n        U(i,k) = zhat(i)/(((diag(i) - shifts(k)) - mus(k)) )/( (diag(i) + singVals[k]));\n      }\n      U(n,k) = 0;      \n      U.col(k).normalize();\n    \n      if (m_compV)\n      {\n        V.col(k).setZero();\n        for(Index l=1;l<m;++l)\n        {\n          Index i = perm(l);\n          V(i,k) = diag(i) * zhat(i) / (((diag(i) - shifts(k)) - mus(k)) )/( (diag(i) + singVals[k]));\n        }\n        V(0,k) = -1;\n        V.col(k).normalize();\n      }\n    }\n  }\n  U.col(n) = VectorType::Unit(n+1, n);\n}\n\n\n// page 12_13\n// i >= 1, di almost null and zi non null.\n// We use a rotation to zero out zi applied to the left of M\ntemplate <typename MatrixType>\nvoid BDCSVD<MatrixType>::deflation43(Index firstCol, Index shift, Index i, Index size)\n{\n  using std::abs;\n  using std::sqrt;\n  using std::pow;\n  Index start = firstCol + shift;\n  RealScalar c = m_computed(start, start);\n  RealScalar s = m_computed(start+i, start);\n  RealScalar r = sqrt(numext::abs2(c) + numext::abs2(s));\n  if (r == 0)\n  {\n    m_computed(start+i, start+i) = 0;\n    return;\n  }\n  m_computed(start,start) = r;  \n  m_computed(start+i, start) = 0;\n  m_computed(start+i, start+i) = 0;\n  \n  JacobiRotation<RealScalar> J(c/r,-s/r);\n  if (m_compU)  m_naiveU.middleRows(firstCol, size+1).applyOnTheRight(firstCol, firstCol+i, J);\n  else          m_naiveU.applyOnTheRight(firstCol, firstCol+i, J);\n}// end deflation 43\n\n\n// page 13\n// i,j >= 1, i!=j and |di - dj| < epsilon * norm2(M)\n// We apply two rotations to have zj = 0;\n// TODO deflation44 is still broken and not properly tested\ntemplate <typename MatrixType>\nvoid BDCSVD<MatrixType>::deflation44(Index firstColu , Index firstColm, Index firstRowW, Index firstColW, Index i, Index j, Index size)\n{\n  using std::abs;\n  using std::sqrt;\n  using std::conj;\n  using std::pow;\n  RealScalar c = m_computed(firstColm+i, firstColm);\n  RealScalar s = m_computed(firstColm+j, firstColm);\n  RealScalar r = sqrt(numext::abs2(c) + numext::abs2(s));\n#ifdef  EIGEN_BDCSVD_DEBUG_VERBOSE\n  std::cout << \"deflation 4.4: \" << i << \",\" << j << \" -> \" << c << \" \" << s << \" \" << r << \" ; \"\n    << m_computed(firstColm + i-1, firstColm)  << \" \"\n    << m_computed(firstColm + i, firstColm)  << \" \"\n    << m_computed(firstColm + i+1, firstColm) << \" \"\n    << m_computed(firstColm + i+2, firstColm) << \"\\n\";\n  std::cout << m_computed(firstColm + i-1, firstColm + i-1)  << \" \"\n    << m_computed(firstColm + i, firstColm+i)  << \" \"\n    << m_computed(firstColm + i+1, firstColm+i+1) << \" \"\n    << m_computed(firstColm + i+2, firstColm+i+2) << \"\\n\";\n#endif\n  if (r==0)\n  {\n    m_computed(firstColm + i, firstColm + i) = m_computed(firstColm + j, firstColm + j);\n    return;\n  }\n  c/=r;\n  s/=r;\n  m_computed(firstColm + i, firstColm) = r;  \n  m_computed(firstColm + j, firstColm + j) = m_computed(firstColm + i, firstColm + i);\n  m_computed(firstColm + j, firstColm) = 0;\n\n  JacobiRotation<RealScalar> J(c,-s);\n  if (m_compU)  m_naiveU.middleRows(firstColu, size+1).applyOnTheRight(firstColu + i, firstColu + j, J);\n  else          m_naiveU.applyOnTheRight(firstColu+i, firstColu+j, J);\n  if (m_compV)  m_naiveV.middleRows(firstRowW, size).applyOnTheRight(firstColW + i, firstColW + j, J);\n}// end deflation 44\n\n\n// acts on block from (firstCol+shift, firstCol+shift) to (lastCol+shift, lastCol+shift) [inclusive]\ntemplate <typename MatrixType>\nvoid BDCSVD<MatrixType>::deflation(Index firstCol, Index lastCol, Index k, Index firstRowW, Index firstColW, Index shift)\n{\n  using std::sqrt;\n  using std::abs;\n  const Index length = lastCol + 1 - firstCol;\n  \n  Block<MatrixXr,Dynamic,1> col0(m_computed, firstCol+shift, firstCol+shift, length, 1);\n  Diagonal<MatrixXr> fulldiag(m_computed);\n  VectorBlock<Diagonal<MatrixXr>,Dynamic> diag(fulldiag, firstCol+shift, length);\n  \n  const RealScalar considerZero = (std::numeric_limits<RealScalar>::min)();\n  RealScalar maxDiag = diag.tail((std::max)(Index(1),length-1)).cwiseAbs().maxCoeff();\n  RealScalar epsilon_strict = numext::maxi<RealScalar>(considerZero,NumTraits<RealScalar>::epsilon() * maxDiag);\n  RealScalar epsilon_coarse = 8 * NumTraits<RealScalar>::epsilon() * numext::maxi<RealScalar>(col0.cwiseAbs().maxCoeff(), maxDiag);\n  \n#ifdef EIGEN_BDCSVD_SANITY_CHECKS\n  assert(m_naiveU.allFinite());\n  assert(m_naiveV.allFinite());\n  assert(m_computed.allFinite());\n#endif\n\n#ifdef  EIGEN_BDCSVD_DEBUG_VERBOSE  \n  std::cout << \"\\ndeflate:\" << diag.head(k+1).transpose() << \"  |  \" << diag.segment(k+1,length-k-1).transpose() << \"\\n\";\n#endif\n  \n  //condition 4.1\n  if (diag(0) < epsilon_coarse)\n  { \n#ifdef  EIGEN_BDCSVD_DEBUG_VERBOSE\n    std::cout << \"deflation 4.1, because \" << diag(0) << \" < \" << epsilon_coarse << \"\\n\";\n#endif\n    diag(0) = epsilon_coarse;\n  }\n\n  //condition 4.2\n  for (Index i=1;i<length;++i)\n    if (abs(col0(i)) < epsilon_strict)\n    {\n#ifdef  EIGEN_BDCSVD_DEBUG_VERBOSE\n      std::cout << \"deflation 4.2, set z(\" << i << \") to zero because \" << abs(col0(i)) << \" < \" << epsilon_strict << \"  (diag(\" << i << \")=\" << diag(i) << \")\\n\";\n#endif\n      col0(i) = 0;\n    }\n\n  //condition 4.3\n  for (Index i=1;i<length; i++)\n    if (diag(i) < epsilon_coarse)\n    {\n#ifdef  EIGEN_BDCSVD_DEBUG_VERBOSE\n      std::cout << \"deflation 4.3, cancel z(\" << i << \")=\" << col0(i) << \" because diag(\" << i << \")=\" << diag(i) << \" < \" << epsilon_coarse << \"\\n\";\n#endif\n      deflation43(firstCol, shift, i, length);\n    }\n\n#ifdef EIGEN_BDCSVD_SANITY_CHECKS\n  assert(m_naiveU.allFinite());\n  assert(m_naiveV.allFinite());\n  assert(m_computed.allFinite());\n#endif\n#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE\n  std::cout << \"to be sorted: \" << diag.transpose() << \"\\n\\n\";\n#endif\n  {\n    // Check for total deflation\n    // If we have a total deflation, then we have to consider col0(0)==diag(0) as a singular value during sorting\n    bool total_deflation = (col0.tail(length-1).array()<considerZero).all();\n    \n    // Sort the diagonal entries, since diag(1:k-1) and diag(k:length) are already sorted, let's do a sorted merge.\n    // First, compute the respective permutation.\n    Index *permutation = m_workspaceI.data();\n    {\n      permutation[0] = 0;\n      Index p = 1;\n      \n      // Move deflated diagonal entries at the end.\n      for(Index i=1; i<length; ++i)\n        if(abs(diag(i))<considerZero)\n          permutation[p++] = i;\n        \n      Index i=1, j=k+1;\n      for( ; p < length; ++p)\n      {\n             if (i > k)             permutation[p] = j++;\n        else if (j >= length)       permutation[p] = i++;\n        else if (diag(i) < diag(j)) permutation[p] = j++;\n        else                        permutation[p] = i++;\n      }\n    }\n    \n    // If we have a total deflation, then we have to insert diag(0) at the right place\n    if(total_deflation)\n    {\n      for(Index i=1; i<length; ++i)\n      {\n        Index pi = permutation[i];\n        if(abs(diag(pi))<considerZero || diag(0)<diag(pi))\n          permutation[i-1] = permutation[i];\n        else\n        {\n          permutation[i-1] = 0;\n          break;\n        }\n      }\n    }\n    \n    // Current index of each col, and current column of each index\n    Index *realInd = m_workspaceI.data()+length;\n    Index *realCol = m_workspaceI.data()+2*length;\n    \n    for(int pos = 0; pos< length; pos++)\n    {\n      realCol[pos] = pos;\n      realInd[pos] = pos;\n    }\n    \n    for(Index i = total_deflation?0:1; i < length; i++)\n    {\n      const Index pi = permutation[length - (total_deflation ? i+1 : i)];\n      const Index J = realCol[pi];\n      \n      using std::swap;\n      // swap diagonal and first column entries:\n      swap(diag(i), diag(J));\n      if(i!=0 && J!=0) swap(col0(i), col0(J));\n\n      // change columns\n      if (m_compU) m_naiveU.col(firstCol+i).segment(firstCol, length + 1).swap(m_naiveU.col(firstCol+J).segment(firstCol, length + 1));\n      else         m_naiveU.col(firstCol+i).segment(0, 2)                .swap(m_naiveU.col(firstCol+J).segment(0, 2));\n      if (m_compV) m_naiveV.col(firstColW + i).segment(firstRowW, length).swap(m_naiveV.col(firstColW + J).segment(firstRowW, length));\n\n      //update real pos\n      const Index realI = realInd[i];\n      realCol[realI] = J;\n      realCol[pi] = i;\n      realInd[J] = realI;\n      realInd[i] = pi;\n    }\n  }\n#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE\n  std::cout << \"sorted: \" << diag.transpose().format(bdcsvdfmt) << \"\\n\";\n  std::cout << \"      : \" << col0.transpose() << \"\\n\\n\";\n#endif\n    \n  //condition 4.4\n  {\n    Index i = length-1;\n    while(i>0 && (abs(diag(i))<considerZero || abs(col0(i))<considerZero)) --i;\n    for(; i>1;--i)\n       if( (diag(i) - diag(i-1)) < NumTraits<RealScalar>::epsilon()*maxDiag )\n      {\n#ifdef EIGEN_BDCSVD_DEBUG_VERBOSE\n        std::cout << \"deflation 4.4 with i = \" << i << \" because \" << (diag(i) - diag(i-1)) << \" < \" << NumTraits<RealScalar>::epsilon()*diag(i) << \"\\n\";\n#endif\n        eigen_internal_assert(abs(diag(i) - diag(i-1))<epsilon_coarse && \" diagonal entries are not properly sorted\");\n        deflation44(firstCol, firstCol + shift, firstRowW, firstColW, i-1, i, length);\n      }\n  }\n  \n#ifdef EIGEN_BDCSVD_SANITY_CHECKS\n  for(Index j=2;j<length;++j)\n    assert(diag(j-1)<=diag(j) || abs(diag(j))<considerZero);\n#endif\n  \n#ifdef EIGEN_BDCSVD_SANITY_CHECKS\n  assert(m_naiveU.allFinite());\n  assert(m_naiveV.allFinite());\n  assert(m_computed.allFinite());\n#endif\n}//end deflation\n\n#ifndef __CUDACC__\n/** \\svd_module\n  *\n  * \\return the singular value decomposition of \\c *this computed by Divide & Conquer algorithm\n  *\n  * \\sa class BDCSVD\n  */\ntemplate<typename Derived>\nBDCSVD<typename MatrixBase<Derived>::PlainObject>\nMatrixBase<Derived>::bdcSvd(unsigned int computationOptions) const\n{\n  return BDCSVD<PlainObject>(*this, computationOptions);\n}\n#endif\n\n} // end namespace Eigen\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SVD/JacobiSVD.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009-2010 Benoit Jacob <jacob.benoit.1@gmail.com>\n// Copyright (C) 2013-2014 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_JACOBISVD_H\n#define EIGEN_JACOBISVD_H\n\nnamespace Eigen { \n\nnamespace internal {\n// forward declaration (needed by ICC)\n// the empty body is required by MSVC\ntemplate<typename MatrixType, int QRPreconditioner,\n         bool IsComplex = NumTraits<typename MatrixType::Scalar>::IsComplex>\nstruct svd_precondition_2x2_block_to_be_real {};\n\n/*** QR preconditioners (R-SVD)\n ***\n *** Their role is to reduce the problem of computing the SVD to the case of a square matrix.\n *** This approach, known as R-SVD, is an optimization for rectangular-enough matrices, and is a requirement for\n *** JacobiSVD which by itself is only able to work on square matrices.\n ***/\n\nenum { PreconditionIfMoreColsThanRows, PreconditionIfMoreRowsThanCols };\n\ntemplate<typename MatrixType, int QRPreconditioner, int Case>\nstruct qr_preconditioner_should_do_anything\n{\n  enum { a = MatrixType::RowsAtCompileTime != Dynamic &&\n             MatrixType::ColsAtCompileTime != Dynamic &&\n             MatrixType::ColsAtCompileTime <= MatrixType::RowsAtCompileTime,\n         b = MatrixType::RowsAtCompileTime != Dynamic &&\n             MatrixType::ColsAtCompileTime != Dynamic &&\n             MatrixType::RowsAtCompileTime <= MatrixType::ColsAtCompileTime,\n         ret = !( (QRPreconditioner == NoQRPreconditioner) ||\n                  (Case == PreconditionIfMoreColsThanRows && bool(a)) ||\n                  (Case == PreconditionIfMoreRowsThanCols && bool(b)) )\n  };\n};\n\ntemplate<typename MatrixType, int QRPreconditioner, int Case,\n         bool DoAnything = qr_preconditioner_should_do_anything<MatrixType, QRPreconditioner, Case>::ret\n> struct qr_preconditioner_impl {};\n\ntemplate<typename MatrixType, int QRPreconditioner, int Case>\nclass qr_preconditioner_impl<MatrixType, QRPreconditioner, Case, false>\n{\npublic:\n  void allocate(const JacobiSVD<MatrixType, QRPreconditioner>&) {}\n  bool run(JacobiSVD<MatrixType, QRPreconditioner>&, const MatrixType&)\n  {\n    return false;\n  }\n};\n\n/*** preconditioner using FullPivHouseholderQR ***/\n\ntemplate<typename MatrixType>\nclass qr_preconditioner_impl<MatrixType, FullPivHouseholderQRPreconditioner, PreconditionIfMoreRowsThanCols, true>\n{\npublic:\n  typedef typename MatrixType::Scalar Scalar;\n  enum\n  {\n    RowsAtCompileTime = MatrixType::RowsAtCompileTime,\n    MaxRowsAtCompileTime = MatrixType::MaxRowsAtCompileTime\n  };\n  typedef Matrix<Scalar, 1, RowsAtCompileTime, RowMajor, 1, MaxRowsAtCompileTime> WorkspaceType;\n\n  void allocate(const JacobiSVD<MatrixType, FullPivHouseholderQRPreconditioner>& svd)\n  {\n    if (svd.rows() != m_qr.rows() || svd.cols() != m_qr.cols())\n    {\n      m_qr.~QRType();\n      ::new (&m_qr) QRType(svd.rows(), svd.cols());\n    }\n    if (svd.m_computeFullU) m_workspace.resize(svd.rows());\n  }\n\n  bool run(JacobiSVD<MatrixType, FullPivHouseholderQRPreconditioner>& svd, const MatrixType& matrix)\n  {\n    if(matrix.rows() > matrix.cols())\n    {\n      m_qr.compute(matrix);\n      svd.m_workMatrix = m_qr.matrixQR().block(0,0,matrix.cols(),matrix.cols()).template triangularView<Upper>();\n      if(svd.m_computeFullU) m_qr.matrixQ().evalTo(svd.m_matrixU, m_workspace);\n      if(svd.computeV()) svd.m_matrixV = m_qr.colsPermutation();\n      return true;\n    }\n    return false;\n  }\nprivate:\n  typedef FullPivHouseholderQR<MatrixType> QRType;\n  QRType m_qr;\n  WorkspaceType m_workspace;\n};\n\ntemplate<typename MatrixType>\nclass qr_preconditioner_impl<MatrixType, FullPivHouseholderQRPreconditioner, PreconditionIfMoreColsThanRows, true>\n{\npublic:\n  typedef typename MatrixType::Scalar Scalar;\n  enum\n  {\n    RowsAtCompileTime = MatrixType::RowsAtCompileTime,\n    ColsAtCompileTime = MatrixType::ColsAtCompileTime,\n    MaxRowsAtCompileTime = MatrixType::MaxRowsAtCompileTime,\n    MaxColsAtCompileTime = MatrixType::MaxColsAtCompileTime,\n    Options = MatrixType::Options\n  };\n  typedef Matrix<Scalar, ColsAtCompileTime, RowsAtCompileTime, Options, MaxColsAtCompileTime, MaxRowsAtCompileTime>\n          TransposeTypeWithSameStorageOrder;\n\n  void allocate(const JacobiSVD<MatrixType, FullPivHouseholderQRPreconditioner>& svd)\n  {\n    if (svd.cols() != m_qr.rows() || svd.rows() != m_qr.cols())\n    {\n      m_qr.~QRType();\n      ::new (&m_qr) QRType(svd.cols(), svd.rows());\n    }\n    m_adjoint.resize(svd.cols(), svd.rows());\n    if (svd.m_computeFullV) m_workspace.resize(svd.cols());\n  }\n\n  bool run(JacobiSVD<MatrixType, FullPivHouseholderQRPreconditioner>& svd, const MatrixType& matrix)\n  {\n    if(matrix.cols() > matrix.rows())\n    {\n      m_adjoint = matrix.adjoint();\n      m_qr.compute(m_adjoint);\n      svd.m_workMatrix = m_qr.matrixQR().block(0,0,matrix.rows(),matrix.rows()).template triangularView<Upper>().adjoint();\n      if(svd.m_computeFullV) m_qr.matrixQ().evalTo(svd.m_matrixV, m_workspace);\n      if(svd.computeU()) svd.m_matrixU = m_qr.colsPermutation();\n      return true;\n    }\n    else return false;\n  }\nprivate:\n  typedef FullPivHouseholderQR<TransposeTypeWithSameStorageOrder> QRType;\n  QRType m_qr;\n  TransposeTypeWithSameStorageOrder m_adjoint;\n  typename internal::plain_row_type<MatrixType>::type m_workspace;\n};\n\n/*** preconditioner using ColPivHouseholderQR ***/\n\ntemplate<typename MatrixType>\nclass qr_preconditioner_impl<MatrixType, ColPivHouseholderQRPreconditioner, PreconditionIfMoreRowsThanCols, true>\n{\npublic:\n  void allocate(const JacobiSVD<MatrixType, ColPivHouseholderQRPreconditioner>& svd)\n  {\n    if (svd.rows() != m_qr.rows() || svd.cols() != m_qr.cols())\n    {\n      m_qr.~QRType();\n      ::new (&m_qr) QRType(svd.rows(), svd.cols());\n    }\n    if (svd.m_computeFullU) m_workspace.resize(svd.rows());\n    else if (svd.m_computeThinU) m_workspace.resize(svd.cols());\n  }\n\n  bool run(JacobiSVD<MatrixType, ColPivHouseholderQRPreconditioner>& svd, const MatrixType& matrix)\n  {\n    if(matrix.rows() > matrix.cols())\n    {\n      m_qr.compute(matrix);\n      svd.m_workMatrix = m_qr.matrixQR().block(0,0,matrix.cols(),matrix.cols()).template triangularView<Upper>();\n      if(svd.m_computeFullU) m_qr.householderQ().evalTo(svd.m_matrixU, m_workspace);\n      else if(svd.m_computeThinU)\n      {\n        svd.m_matrixU.setIdentity(matrix.rows(), matrix.cols());\n        m_qr.householderQ().applyThisOnTheLeft(svd.m_matrixU, m_workspace);\n      }\n      if(svd.computeV()) svd.m_matrixV = m_qr.colsPermutation();\n      return true;\n    }\n    return false;\n  }\n\nprivate:\n  typedef ColPivHouseholderQR<MatrixType> QRType;\n  QRType m_qr;\n  typename internal::plain_col_type<MatrixType>::type m_workspace;\n};\n\ntemplate<typename MatrixType>\nclass qr_preconditioner_impl<MatrixType, ColPivHouseholderQRPreconditioner, PreconditionIfMoreColsThanRows, true>\n{\npublic:\n  typedef typename MatrixType::Scalar Scalar;\n  enum\n  {\n    RowsAtCompileTime = MatrixType::RowsAtCompileTime,\n    ColsAtCompileTime = MatrixType::ColsAtCompileTime,\n    MaxRowsAtCompileTime = MatrixType::MaxRowsAtCompileTime,\n    MaxColsAtCompileTime = MatrixType::MaxColsAtCompileTime,\n    Options = MatrixType::Options\n  };\n\n  typedef Matrix<Scalar, ColsAtCompileTime, RowsAtCompileTime, Options, MaxColsAtCompileTime, MaxRowsAtCompileTime>\n          TransposeTypeWithSameStorageOrder;\n\n  void allocate(const JacobiSVD<MatrixType, ColPivHouseholderQRPreconditioner>& svd)\n  {\n    if (svd.cols() != m_qr.rows() || svd.rows() != m_qr.cols())\n    {\n      m_qr.~QRType();\n      ::new (&m_qr) QRType(svd.cols(), svd.rows());\n    }\n    if (svd.m_computeFullV) m_workspace.resize(svd.cols());\n    else if (svd.m_computeThinV) m_workspace.resize(svd.rows());\n    m_adjoint.resize(svd.cols(), svd.rows());\n  }\n\n  bool run(JacobiSVD<MatrixType, ColPivHouseholderQRPreconditioner>& svd, const MatrixType& matrix)\n  {\n    if(matrix.cols() > matrix.rows())\n    {\n      m_adjoint = matrix.adjoint();\n      m_qr.compute(m_adjoint);\n\n      svd.m_workMatrix = m_qr.matrixQR().block(0,0,matrix.rows(),matrix.rows()).template triangularView<Upper>().adjoint();\n      if(svd.m_computeFullV) m_qr.householderQ().evalTo(svd.m_matrixV, m_workspace);\n      else if(svd.m_computeThinV)\n      {\n        svd.m_matrixV.setIdentity(matrix.cols(), matrix.rows());\n        m_qr.householderQ().applyThisOnTheLeft(svd.m_matrixV, m_workspace);\n      }\n      if(svd.computeU()) svd.m_matrixU = m_qr.colsPermutation();\n      return true;\n    }\n    else return false;\n  }\n\nprivate:\n  typedef ColPivHouseholderQR<TransposeTypeWithSameStorageOrder> QRType;\n  QRType m_qr;\n  TransposeTypeWithSameStorageOrder m_adjoint;\n  typename internal::plain_row_type<MatrixType>::type m_workspace;\n};\n\n/*** preconditioner using HouseholderQR ***/\n\ntemplate<typename MatrixType>\nclass qr_preconditioner_impl<MatrixType, HouseholderQRPreconditioner, PreconditionIfMoreRowsThanCols, true>\n{\npublic:\n  void allocate(const JacobiSVD<MatrixType, HouseholderQRPreconditioner>& svd)\n  {\n    if (svd.rows() != m_qr.rows() || svd.cols() != m_qr.cols())\n    {\n      m_qr.~QRType();\n      ::new (&m_qr) QRType(svd.rows(), svd.cols());\n    }\n    if (svd.m_computeFullU) m_workspace.resize(svd.rows());\n    else if (svd.m_computeThinU) m_workspace.resize(svd.cols());\n  }\n\n  bool run(JacobiSVD<MatrixType, HouseholderQRPreconditioner>& svd, const MatrixType& matrix)\n  {\n    if(matrix.rows() > matrix.cols())\n    {\n      m_qr.compute(matrix);\n      svd.m_workMatrix = m_qr.matrixQR().block(0,0,matrix.cols(),matrix.cols()).template triangularView<Upper>();\n      if(svd.m_computeFullU) m_qr.householderQ().evalTo(svd.m_matrixU, m_workspace);\n      else if(svd.m_computeThinU)\n      {\n        svd.m_matrixU.setIdentity(matrix.rows(), matrix.cols());\n        m_qr.householderQ().applyThisOnTheLeft(svd.m_matrixU, m_workspace);\n      }\n      if(svd.computeV()) svd.m_matrixV.setIdentity(matrix.cols(), matrix.cols());\n      return true;\n    }\n    return false;\n  }\nprivate:\n  typedef HouseholderQR<MatrixType> QRType;\n  QRType m_qr;\n  typename internal::plain_col_type<MatrixType>::type m_workspace;\n};\n\ntemplate<typename MatrixType>\nclass qr_preconditioner_impl<MatrixType, HouseholderQRPreconditioner, PreconditionIfMoreColsThanRows, true>\n{\npublic:\n  typedef typename MatrixType::Scalar Scalar;\n  enum\n  {\n    RowsAtCompileTime = MatrixType::RowsAtCompileTime,\n    ColsAtCompileTime = MatrixType::ColsAtCompileTime,\n    MaxRowsAtCompileTime = MatrixType::MaxRowsAtCompileTime,\n    MaxColsAtCompileTime = MatrixType::MaxColsAtCompileTime,\n    Options = MatrixType::Options\n  };\n\n  typedef Matrix<Scalar, ColsAtCompileTime, RowsAtCompileTime, Options, MaxColsAtCompileTime, MaxRowsAtCompileTime>\n          TransposeTypeWithSameStorageOrder;\n\n  void allocate(const JacobiSVD<MatrixType, HouseholderQRPreconditioner>& svd)\n  {\n    if (svd.cols() != m_qr.rows() || svd.rows() != m_qr.cols())\n    {\n      m_qr.~QRType();\n      ::new (&m_qr) QRType(svd.cols(), svd.rows());\n    }\n    if (svd.m_computeFullV) m_workspace.resize(svd.cols());\n    else if (svd.m_computeThinV) m_workspace.resize(svd.rows());\n    m_adjoint.resize(svd.cols(), svd.rows());\n  }\n\n  bool run(JacobiSVD<MatrixType, HouseholderQRPreconditioner>& svd, const MatrixType& matrix)\n  {\n    if(matrix.cols() > matrix.rows())\n    {\n      m_adjoint = matrix.adjoint();\n      m_qr.compute(m_adjoint);\n\n      svd.m_workMatrix = m_qr.matrixQR().block(0,0,matrix.rows(),matrix.rows()).template triangularView<Upper>().adjoint();\n      if(svd.m_computeFullV) m_qr.householderQ().evalTo(svd.m_matrixV, m_workspace);\n      else if(svd.m_computeThinV)\n      {\n        svd.m_matrixV.setIdentity(matrix.cols(), matrix.rows());\n        m_qr.householderQ().applyThisOnTheLeft(svd.m_matrixV, m_workspace);\n      }\n      if(svd.computeU()) svd.m_matrixU.setIdentity(matrix.rows(), matrix.rows());\n      return true;\n    }\n    else return false;\n  }\n\nprivate:\n  typedef HouseholderQR<TransposeTypeWithSameStorageOrder> QRType;\n  QRType m_qr;\n  TransposeTypeWithSameStorageOrder m_adjoint;\n  typename internal::plain_row_type<MatrixType>::type m_workspace;\n};\n\n/*** 2x2 SVD implementation\n ***\n *** JacobiSVD consists in performing a series of 2x2 SVD subproblems\n ***/\n\ntemplate<typename MatrixType, int QRPreconditioner>\nstruct svd_precondition_2x2_block_to_be_real<MatrixType, QRPreconditioner, false>\n{\n  typedef JacobiSVD<MatrixType, QRPreconditioner> SVD;\n  typedef typename MatrixType::RealScalar RealScalar;\n  static bool run(typename SVD::WorkMatrixType&, SVD&, Index, Index, RealScalar&) { return true; }\n};\n\ntemplate<typename MatrixType, int QRPreconditioner>\nstruct svd_precondition_2x2_block_to_be_real<MatrixType, QRPreconditioner, true>\n{\n  typedef JacobiSVD<MatrixType, QRPreconditioner> SVD;\n  typedef typename MatrixType::Scalar Scalar;\n  typedef typename MatrixType::RealScalar RealScalar;\n  static bool run(typename SVD::WorkMatrixType& work_matrix, SVD& svd, Index p, Index q, RealScalar& maxDiagEntry)\n  {\n    using std::sqrt;\n    using std::abs;\n    Scalar z;\n    JacobiRotation<Scalar> rot;\n    RealScalar n = sqrt(numext::abs2(work_matrix.coeff(p,p)) + numext::abs2(work_matrix.coeff(q,p)));\n\n    const RealScalar considerAsZero = (std::numeric_limits<RealScalar>::min)();\n    const RealScalar precision = NumTraits<Scalar>::epsilon();\n\n    if(n==0)\n    {\n      // make sure first column is zero\n      work_matrix.coeffRef(p,p) = work_matrix.coeffRef(q,p) = Scalar(0);\n\n      if(abs(numext::imag(work_matrix.coeff(p,q)))>considerAsZero)\n      {\n        // work_matrix.coeff(p,q) can be zero if work_matrix.coeff(q,p) is not zero but small enough to underflow when computing n\n        z = abs(work_matrix.coeff(p,q)) / work_matrix.coeff(p,q);\n        work_matrix.row(p) *= z;\n        if(svd.computeU()) svd.m_matrixU.col(p) *= conj(z);\n      }\n      if(abs(numext::imag(work_matrix.coeff(q,q)))>considerAsZero)\n      {\n        z = abs(work_matrix.coeff(q,q)) / work_matrix.coeff(q,q);\n        work_matrix.row(q) *= z;\n        if(svd.computeU()) svd.m_matrixU.col(q) *= conj(z);\n      }\n      // otherwise the second row is already zero, so we have nothing to do.\n    }\n    else\n    {\n      rot.c() = conj(work_matrix.coeff(p,p)) / n;\n      rot.s() = work_matrix.coeff(q,p) / n;\n      work_matrix.applyOnTheLeft(p,q,rot);\n      if(svd.computeU()) svd.m_matrixU.applyOnTheRight(p,q,rot.adjoint());\n      if(abs(numext::imag(work_matrix.coeff(p,q)))>considerAsZero)\n      {\n        z = abs(work_matrix.coeff(p,q)) / work_matrix.coeff(p,q);\n        work_matrix.col(q) *= z;\n        if(svd.computeV()) svd.m_matrixV.col(q) *= z;\n      }\n      if(abs(numext::imag(work_matrix.coeff(q,q)))>considerAsZero)\n      {\n        z = abs(work_matrix.coeff(q,q)) / work_matrix.coeff(q,q);\n        work_matrix.row(q) *= z;\n        if(svd.computeU()) svd.m_matrixU.col(q) *= conj(z);\n      }\n    }\n\n    // update largest diagonal entry\n    maxDiagEntry = numext::maxi<RealScalar>(maxDiagEntry,numext::maxi<RealScalar>(abs(work_matrix.coeff(p,p)), abs(work_matrix.coeff(q,q))));\n    // and check whether the 2x2 block is already diagonal\n    RealScalar threshold = numext::maxi<RealScalar>(considerAsZero, precision * maxDiagEntry);\n    return abs(work_matrix.coeff(p,q))>threshold || abs(work_matrix.coeff(q,p)) > threshold;\n  }\n};\n\ntemplate<typename _MatrixType, int QRPreconditioner> \nstruct traits<JacobiSVD<_MatrixType,QRPreconditioner> >\n{\n  typedef _MatrixType MatrixType;\n};\n\n} // end namespace internal\n\n/** \\ingroup SVD_Module\n  *\n  *\n  * \\class JacobiSVD\n  *\n  * \\brief Two-sided Jacobi SVD decomposition of a rectangular matrix\n  *\n  * \\tparam _MatrixType the type of the matrix of which we are computing the SVD decomposition\n  * \\tparam QRPreconditioner this optional parameter allows to specify the type of QR decomposition that will be used internally\n  *                        for the R-SVD step for non-square matrices. See discussion of possible values below.\n  *\n  * SVD decomposition consists in decomposing any n-by-p matrix \\a A as a product\n  *   \\f[ A = U S V^* \\f]\n  * where \\a U is a n-by-n unitary, \\a V is a p-by-p unitary, and \\a S is a n-by-p real positive matrix which is zero outside of its main diagonal;\n  * the diagonal entries of S are known as the \\em singular \\em values of \\a A and the columns of \\a U and \\a V are known as the left\n  * and right \\em singular \\em vectors of \\a A respectively.\n  *\n  * Singular values are always sorted in decreasing order.\n  *\n  * This JacobiSVD decomposition computes only the singular values by default. If you want \\a U or \\a V, you need to ask for them explicitly.\n  *\n  * You can ask for only \\em thin \\a U or \\a V to be computed, meaning the following. In case of a rectangular n-by-p matrix, letting \\a m be the\n  * smaller value among \\a n and \\a p, there are only \\a m singular vectors; the remaining columns of \\a U and \\a V do not correspond to actual\n  * singular vectors. Asking for \\em thin \\a U or \\a V means asking for only their \\a m first columns to be formed. So \\a U is then a n-by-m matrix,\n  * and \\a V is then a p-by-m matrix. Notice that thin \\a U and \\a V are all you need for (least squares) solving.\n  *\n  * Here's an example demonstrating basic usage:\n  * \\include JacobiSVD_basic.cpp\n  * Output: \\verbinclude JacobiSVD_basic.out\n  *\n  * This JacobiSVD class is a two-sided Jacobi R-SVD decomposition, ensuring optimal reliability and accuracy. The downside is that it's slower than\n  * bidiagonalizing SVD algorithms for large square matrices; however its complexity is still \\f$ O(n^2p) \\f$ where \\a n is the smaller dimension and\n  * \\a p is the greater dimension, meaning that it is still of the same order of complexity as the faster bidiagonalizing R-SVD algorithms.\n  * In particular, like any R-SVD, it takes advantage of non-squareness in that its complexity is only linear in the greater dimension.\n  *\n  * If the input matrix has inf or nan coefficients, the result of the computation is undefined, but the computation is guaranteed to\n  * terminate in finite (and reasonable) time.\n  *\n  * The possible values for QRPreconditioner are:\n  * \\li ColPivHouseholderQRPreconditioner is the default. In practice it's very safe. It uses column-pivoting QR.\n  * \\li FullPivHouseholderQRPreconditioner, is the safest and slowest. It uses full-pivoting QR.\n  *     Contrary to other QRs, it doesn't allow computing thin unitaries.\n  * \\li HouseholderQRPreconditioner is the fastest, and less safe and accurate than the pivoting variants. It uses non-pivoting QR.\n  *     This is very similar in safety and accuracy to the bidiagonalization process used by bidiagonalizing SVD algorithms (since bidiagonalization\n  *     is inherently non-pivoting). However the resulting SVD is still more reliable than bidiagonalizing SVDs because the Jacobi-based iterarive\n  *     process is more reliable than the optimized bidiagonal SVD iterations.\n  * \\li NoQRPreconditioner allows not to use a QR preconditioner at all. This is useful if you know that you will only be computing\n  *     JacobiSVD decompositions of square matrices. Non-square matrices require a QR preconditioner. Using this option will result in\n  *     faster compilation and smaller executable code. It won't significantly speed up computation, since JacobiSVD is always checking\n  *     if QR preconditioning is needed before applying it anyway.\n  *\n  * \\sa MatrixBase::jacobiSvd()\n  */\ntemplate<typename _MatrixType, int QRPreconditioner> class JacobiSVD\n : public SVDBase<JacobiSVD<_MatrixType,QRPreconditioner> >\n{\n    typedef SVDBase<JacobiSVD> Base;\n  public:\n\n    typedef _MatrixType MatrixType;\n    typedef typename MatrixType::Scalar Scalar;\n    typedef typename NumTraits<typename MatrixType::Scalar>::Real RealScalar;\n    enum {\n      RowsAtCompileTime = MatrixType::RowsAtCompileTime,\n      ColsAtCompileTime = MatrixType::ColsAtCompileTime,\n      DiagSizeAtCompileTime = EIGEN_SIZE_MIN_PREFER_DYNAMIC(RowsAtCompileTime,ColsAtCompileTime),\n      MaxRowsAtCompileTime = MatrixType::MaxRowsAtCompileTime,\n      MaxColsAtCompileTime = MatrixType::MaxColsAtCompileTime,\n      MaxDiagSizeAtCompileTime = EIGEN_SIZE_MIN_PREFER_FIXED(MaxRowsAtCompileTime,MaxColsAtCompileTime),\n      MatrixOptions = MatrixType::Options\n    };\n\n    typedef typename Base::MatrixUType MatrixUType;\n    typedef typename Base::MatrixVType MatrixVType;\n    typedef typename Base::SingularValuesType SingularValuesType;\n    \n    typedef typename internal::plain_row_type<MatrixType>::type RowType;\n    typedef typename internal::plain_col_type<MatrixType>::type ColType;\n    typedef Matrix<Scalar, DiagSizeAtCompileTime, DiagSizeAtCompileTime,\n                   MatrixOptions, MaxDiagSizeAtCompileTime, MaxDiagSizeAtCompileTime>\n            WorkMatrixType;\n\n    /** \\brief Default Constructor.\n      *\n      * The default constructor is useful in cases in which the user intends to\n      * perform decompositions via JacobiSVD::compute(const MatrixType&).\n      */\n    JacobiSVD()\n    {}\n\n\n    /** \\brief Default Constructor with memory preallocation\n      *\n      * Like the default constructor but with preallocation of the internal data\n      * according to the specified problem size.\n      * \\sa JacobiSVD()\n      */\n    JacobiSVD(Index rows, Index cols, unsigned int computationOptions = 0)\n    {\n      allocate(rows, cols, computationOptions);\n    }\n\n    /** \\brief Constructor performing the decomposition of given matrix.\n     *\n     * \\param matrix the matrix to decompose\n     * \\param computationOptions optional parameter allowing to specify if you want full or thin U or V unitaries to be computed.\n     *                           By default, none is computed. This is a bit-field, the possible bits are #ComputeFullU, #ComputeThinU,\n     *                           #ComputeFullV, #ComputeThinV.\n     *\n     * Thin unitaries are only available if your matrix type has a Dynamic number of columns (for example MatrixXf). They also are not\n     * available with the (non-default) FullPivHouseholderQR preconditioner.\n     */\n    explicit JacobiSVD(const MatrixType& matrix, unsigned int computationOptions = 0)\n    {\n      compute(matrix, computationOptions);\n    }\n\n    /** \\brief Method performing the decomposition of given matrix using custom options.\n     *\n     * \\param matrix the matrix to decompose\n     * \\param computationOptions optional parameter allowing to specify if you want full or thin U or V unitaries to be computed.\n     *                           By default, none is computed. This is a bit-field, the possible bits are #ComputeFullU, #ComputeThinU,\n     *                           #ComputeFullV, #ComputeThinV.\n     *\n     * Thin unitaries are only available if your matrix type has a Dynamic number of columns (for example MatrixXf). They also are not\n     * available with the (non-default) FullPivHouseholderQR preconditioner.\n     */\n    JacobiSVD& compute(const MatrixType& matrix, unsigned int computationOptions);\n\n    /** \\brief Method performing the decomposition of given matrix using current options.\n     *\n     * \\param matrix the matrix to decompose\n     *\n     * This method uses the current \\a computationOptions, as already passed to the constructor or to compute(const MatrixType&, unsigned int).\n     */\n    JacobiSVD& compute(const MatrixType& matrix)\n    {\n      return compute(matrix, m_computationOptions);\n    }\n\n    using Base::computeU;\n    using Base::computeV;\n    using Base::rows;\n    using Base::cols;\n    using Base::rank;\n\n  private:\n    void allocate(Index rows, Index cols, unsigned int computationOptions);\n\n  protected:\n    using Base::m_matrixU;\n    using Base::m_matrixV;\n    using Base::m_singularValues;\n    using Base::m_isInitialized;\n    using Base::m_isAllocated;\n    using Base::m_usePrescribedThreshold;\n    using Base::m_computeFullU;\n    using Base::m_computeThinU;\n    using Base::m_computeFullV;\n    using Base::m_computeThinV;\n    using Base::m_computationOptions;\n    using Base::m_nonzeroSingularValues;\n    using Base::m_rows;\n    using Base::m_cols;\n    using Base::m_diagSize;\n    using Base::m_prescribedThreshold;\n    WorkMatrixType m_workMatrix;\n\n    template<typename __MatrixType, int _QRPreconditioner, bool _IsComplex>\n    friend struct internal::svd_precondition_2x2_block_to_be_real;\n    template<typename __MatrixType, int _QRPreconditioner, int _Case, bool _DoAnything>\n    friend struct internal::qr_preconditioner_impl;\n\n    internal::qr_preconditioner_impl<MatrixType, QRPreconditioner, internal::PreconditionIfMoreColsThanRows> m_qr_precond_morecols;\n    internal::qr_preconditioner_impl<MatrixType, QRPreconditioner, internal::PreconditionIfMoreRowsThanCols> m_qr_precond_morerows;\n    MatrixType m_scaledMatrix;\n};\n\ntemplate<typename MatrixType, int QRPreconditioner>\nvoid JacobiSVD<MatrixType, QRPreconditioner>::allocate(Index rows, Index cols, unsigned int computationOptions)\n{\n  eigen_assert(rows >= 0 && cols >= 0);\n\n  if (m_isAllocated &&\n      rows == m_rows &&\n      cols == m_cols &&\n      computationOptions == m_computationOptions)\n  {\n    return;\n  }\n\n  m_rows = rows;\n  m_cols = cols;\n  m_isInitialized = false;\n  m_isAllocated = true;\n  m_computationOptions = computationOptions;\n  m_computeFullU = (computationOptions & ComputeFullU) != 0;\n  m_computeThinU = (computationOptions & ComputeThinU) != 0;\n  m_computeFullV = (computationOptions & ComputeFullV) != 0;\n  m_computeThinV = (computationOptions & ComputeThinV) != 0;\n  eigen_assert(!(m_computeFullU && m_computeThinU) && \"JacobiSVD: you can't ask for both full and thin U\");\n  eigen_assert(!(m_computeFullV && m_computeThinV) && \"JacobiSVD: you can't ask for both full and thin V\");\n  eigen_assert(EIGEN_IMPLIES(m_computeThinU || m_computeThinV, MatrixType::ColsAtCompileTime==Dynamic) &&\n              \"JacobiSVD: thin U and V are only available when your matrix has a dynamic number of columns.\");\n  if (QRPreconditioner == FullPivHouseholderQRPreconditioner)\n  {\n      eigen_assert(!(m_computeThinU || m_computeThinV) &&\n              \"JacobiSVD: can't compute thin U or thin V with the FullPivHouseholderQR preconditioner. \"\n              \"Use the ColPivHouseholderQR preconditioner instead.\");\n  }\n  m_diagSize = (std::min)(m_rows, m_cols);\n  m_singularValues.resize(m_diagSize);\n  if(RowsAtCompileTime==Dynamic)\n    m_matrixU.resize(m_rows, m_computeFullU ? m_rows\n                            : m_computeThinU ? m_diagSize\n                            : 0);\n  if(ColsAtCompileTime==Dynamic)\n    m_matrixV.resize(m_cols, m_computeFullV ? m_cols\n                            : m_computeThinV ? m_diagSize\n                            : 0);\n  m_workMatrix.resize(m_diagSize, m_diagSize);\n  \n  if(m_cols>m_rows)   m_qr_precond_morecols.allocate(*this);\n  if(m_rows>m_cols)   m_qr_precond_morerows.allocate(*this);\n  if(m_rows!=m_cols)  m_scaledMatrix.resize(rows,cols);\n}\n\ntemplate<typename MatrixType, int QRPreconditioner>\nJacobiSVD<MatrixType, QRPreconditioner>&\nJacobiSVD<MatrixType, QRPreconditioner>::compute(const MatrixType& matrix, unsigned int computationOptions)\n{\n  using std::abs;\n  allocate(matrix.rows(), matrix.cols(), computationOptions);\n\n  // currently we stop when we reach precision 2*epsilon as the last bit of precision can require an unreasonable number of iterations,\n  // only worsening the precision of U and V as we accumulate more rotations\n  const RealScalar precision = RealScalar(2) * NumTraits<Scalar>::epsilon();\n\n  // limit for denormal numbers to be considered zero in order to avoid infinite loops (see bug 286)\n  const RealScalar considerAsZero = (std::numeric_limits<RealScalar>::min)();\n\n  // Scaling factor to reduce over/under-flows\n  RealScalar scale = matrix.cwiseAbs().maxCoeff();\n  if(scale==RealScalar(0)) scale = RealScalar(1);\n  \n  /*** step 1. The R-SVD step: we use a QR decomposition to reduce to the case of a square matrix */\n\n  if(m_rows!=m_cols)\n  {\n    m_scaledMatrix = matrix / scale;\n    m_qr_precond_morecols.run(*this, m_scaledMatrix);\n    m_qr_precond_morerows.run(*this, m_scaledMatrix);\n  }\n  else\n  {\n    m_workMatrix = matrix.block(0,0,m_diagSize,m_diagSize) / scale;\n    if(m_computeFullU) m_matrixU.setIdentity(m_rows,m_rows);\n    if(m_computeThinU) m_matrixU.setIdentity(m_rows,m_diagSize);\n    if(m_computeFullV) m_matrixV.setIdentity(m_cols,m_cols);\n    if(m_computeThinV) m_matrixV.setIdentity(m_cols, m_diagSize);\n  }\n\n  /*** step 2. The main Jacobi SVD iteration. ***/\n  RealScalar maxDiagEntry = m_workMatrix.cwiseAbs().diagonal().maxCoeff();\n\n  bool finished = false;\n  while(!finished)\n  {\n    finished = true;\n\n    // do a sweep: for all index pairs (p,q), perform SVD of the corresponding 2x2 sub-matrix\n\n    for(Index p = 1; p < m_diagSize; ++p)\n    {\n      for(Index q = 0; q < p; ++q)\n      {\n        // if this 2x2 sub-matrix is not diagonal already...\n        // notice that this comparison will evaluate to false if any NaN is involved, ensuring that NaN's don't\n        // keep us iterating forever. Similarly, small denormal numbers are considered zero.\n        RealScalar threshold = numext::maxi<RealScalar>(considerAsZero, precision * maxDiagEntry);\n        if(abs(m_workMatrix.coeff(p,q))>threshold || abs(m_workMatrix.coeff(q,p)) > threshold)\n        {\n          finished = false;\n          // perform SVD decomposition of 2x2 sub-matrix corresponding to indices p,q to make it diagonal\n          // the complex to real operation returns true if the updated 2x2 block is not already diagonal\n          if(internal::svd_precondition_2x2_block_to_be_real<MatrixType, QRPreconditioner>::run(m_workMatrix, *this, p, q, maxDiagEntry))\n          {\n            JacobiRotation<RealScalar> j_left, j_right;\n            internal::real_2x2_jacobi_svd(m_workMatrix, p, q, &j_left, &j_right);\n\n            // accumulate resulting Jacobi rotations\n            m_workMatrix.applyOnTheLeft(p,q,j_left);\n            if(computeU()) m_matrixU.applyOnTheRight(p,q,j_left.transpose());\n\n            m_workMatrix.applyOnTheRight(p,q,j_right);\n            if(computeV()) m_matrixV.applyOnTheRight(p,q,j_right);\n\n            // keep track of the largest diagonal coefficient\n            maxDiagEntry = numext::maxi<RealScalar>(maxDiagEntry,numext::maxi<RealScalar>(abs(m_workMatrix.coeff(p,p)), abs(m_workMatrix.coeff(q,q))));\n          }\n        }\n      }\n    }\n  }\n\n  /*** step 3. The work matrix is now diagonal, so ensure it's positive so its diagonal entries are the singular values ***/\n\n  for(Index i = 0; i < m_diagSize; ++i)\n  {\n    // For a complex matrix, some diagonal coefficients might note have been\n    // treated by svd_precondition_2x2_block_to_be_real, and the imaginary part\n    // of some diagonal entry might not be null.\n    if(NumTraits<Scalar>::IsComplex && abs(numext::imag(m_workMatrix.coeff(i,i)))>considerAsZero)\n    {\n      RealScalar a = abs(m_workMatrix.coeff(i,i));\n      m_singularValues.coeffRef(i) = abs(a);\n      if(computeU()) m_matrixU.col(i) *= m_workMatrix.coeff(i,i)/a;\n    }\n    else\n    {\n      // m_workMatrix.coeff(i,i) is already real, no difficulty:\n      RealScalar a = numext::real(m_workMatrix.coeff(i,i));\n      m_singularValues.coeffRef(i) = abs(a);\n      if(computeU() && (a<RealScalar(0))) m_matrixU.col(i) = -m_matrixU.col(i);\n    }\n  }\n  \n  m_singularValues *= scale;\n\n  /*** step 4. Sort singular values in descending order and compute the number of nonzero singular values ***/\n\n  m_nonzeroSingularValues = m_diagSize;\n  for(Index i = 0; i < m_diagSize; i++)\n  {\n    Index pos;\n    RealScalar maxRemainingSingularValue = m_singularValues.tail(m_diagSize-i).maxCoeff(&pos);\n    if(maxRemainingSingularValue == RealScalar(0))\n    {\n      m_nonzeroSingularValues = i;\n      break;\n    }\n    if(pos)\n    {\n      pos += i;\n      std::swap(m_singularValues.coeffRef(i), m_singularValues.coeffRef(pos));\n      if(computeU()) m_matrixU.col(pos).swap(m_matrixU.col(i));\n      if(computeV()) m_matrixV.col(pos).swap(m_matrixV.col(i));\n    }\n  }\n\n  m_isInitialized = true;\n  return *this;\n}\n\n/** \\svd_module\n  *\n  * \\return the singular value decomposition of \\c *this computed by two-sided\n  * Jacobi transformations.\n  *\n  * \\sa class JacobiSVD\n  */\ntemplate<typename Derived>\nJacobiSVD<typename MatrixBase<Derived>::PlainObject>\nMatrixBase<Derived>::jacobiSvd(unsigned int computationOptions) const\n{\n  return JacobiSVD<PlainObject>(*this, computationOptions);\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_JACOBISVD_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SVD/JacobiSVD_LAPACKE.h",
    "content": "/*\n Copyright (c) 2011, Intel Corporation. All rights reserved.\n\n Redistribution and use in source and binary forms, with or without modification,\n are permitted provided that the following conditions are met:\n\n * Redistributions of source code must retain the above copyright notice, this\n   list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright notice,\n   this list of conditions and the following disclaimer in the documentation\n   and/or other materials provided with the distribution.\n * Neither the name of Intel Corporation nor the names of its contributors may\n   be used to endorse or promote products derived from this software without\n   specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n ********************************************************************************\n *   Content : Eigen bindings to LAPACKe\n *    Singular Value Decomposition - SVD.\n ********************************************************************************\n*/\n\n#ifndef EIGEN_JACOBISVD_LAPACKE_H\n#define EIGEN_JACOBISVD_LAPACKE_H\n\nnamespace Eigen { \n\n/** \\internal Specialization for the data types supported by LAPACKe */\n\n#define EIGEN_LAPACKE_SVD(EIGTYPE, LAPACKE_TYPE, LAPACKE_RTYPE, LAPACKE_PREFIX, EIGCOLROW, LAPACKE_COLROW) \\\ntemplate<> inline \\\nJacobiSVD<Matrix<EIGTYPE, Dynamic, Dynamic, EIGCOLROW, Dynamic, Dynamic>, ColPivHouseholderQRPreconditioner>& \\\nJacobiSVD<Matrix<EIGTYPE, Dynamic, Dynamic, EIGCOLROW, Dynamic, Dynamic>, ColPivHouseholderQRPreconditioner>::compute(const Matrix<EIGTYPE, Dynamic, Dynamic, EIGCOLROW, Dynamic, Dynamic>& matrix, unsigned int computationOptions) \\\n{ \\\n  typedef Matrix<EIGTYPE, Dynamic, Dynamic, EIGCOLROW, Dynamic, Dynamic> MatrixType; \\\n  /*typedef MatrixType::Scalar Scalar;*/ \\\n  /*typedef MatrixType::RealScalar RealScalar;*/ \\\n  allocate(matrix.rows(), matrix.cols(), computationOptions); \\\n\\\n  /*const RealScalar precision = RealScalar(2) * NumTraits<Scalar>::epsilon();*/ \\\n  m_nonzeroSingularValues = m_diagSize; \\\n\\\n  lapack_int lda = internal::convert_index<lapack_int>(matrix.outerStride()), ldu, ldvt; \\\n  lapack_int matrix_order = LAPACKE_COLROW; \\\n  char jobu, jobvt; \\\n  LAPACKE_TYPE *u, *vt, dummy; \\\n  jobu  = (m_computeFullU) ? 'A' : (m_computeThinU) ? 'S' : 'N'; \\\n  jobvt = (m_computeFullV) ? 'A' : (m_computeThinV) ? 'S' : 'N'; \\\n  if (computeU()) { \\\n    ldu  = internal::convert_index<lapack_int>(m_matrixU.outerStride()); \\\n    u    = (LAPACKE_TYPE*)m_matrixU.data(); \\\n  } else { ldu=1; u=&dummy; }\\\n  MatrixType localV; \\\n  ldvt = (m_computeFullV) ? internal::convert_index<lapack_int>(m_cols) : (m_computeThinV) ? internal::convert_index<lapack_int>(m_diagSize) : 1; \\\n  if (computeV()) { \\\n    localV.resize(ldvt, m_cols); \\\n    vt   = (LAPACKE_TYPE*)localV.data(); \\\n  } else { ldvt=1; vt=&dummy; }\\\n  Matrix<LAPACKE_RTYPE, Dynamic, Dynamic> superb; superb.resize(m_diagSize, 1); \\\n  MatrixType m_temp; m_temp = matrix; \\\n  LAPACKE_##LAPACKE_PREFIX##gesvd( matrix_order, jobu, jobvt, internal::convert_index<lapack_int>(m_rows), internal::convert_index<lapack_int>(m_cols), (LAPACKE_TYPE*)m_temp.data(), lda, (LAPACKE_RTYPE*)m_singularValues.data(), u, ldu, vt, ldvt, superb.data()); \\\n  if (computeV()) m_matrixV = localV.adjoint(); \\\n /* for(int i=0;i<m_diagSize;i++) if (m_singularValues.coeffRef(i) < precision) { m_nonzeroSingularValues--; m_singularValues.coeffRef(i)=RealScalar(0);}*/ \\\n  m_isInitialized = true; \\\n  return *this; \\\n}\n\nEIGEN_LAPACKE_SVD(double,   double,                double, d, ColMajor, LAPACK_COL_MAJOR)\nEIGEN_LAPACKE_SVD(float,    float,                 float , s, ColMajor, LAPACK_COL_MAJOR)\nEIGEN_LAPACKE_SVD(dcomplex, lapack_complex_double, double, z, ColMajor, LAPACK_COL_MAJOR)\nEIGEN_LAPACKE_SVD(scomplex, lapack_complex_float,  float , c, ColMajor, LAPACK_COL_MAJOR)\n\nEIGEN_LAPACKE_SVD(double,   double,                double, d, RowMajor, LAPACK_ROW_MAJOR)\nEIGEN_LAPACKE_SVD(float,    float,                 float , s, RowMajor, LAPACK_ROW_MAJOR)\nEIGEN_LAPACKE_SVD(dcomplex, lapack_complex_double, double, z, RowMajor, LAPACK_ROW_MAJOR)\nEIGEN_LAPACKE_SVD(scomplex, lapack_complex_float,  float , c, RowMajor, LAPACK_ROW_MAJOR)\n\n} // end namespace Eigen\n\n#endif // EIGEN_JACOBISVD_LAPACKE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SVD/SVDBase.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009-2010 Benoit Jacob <jacob.benoit.1@gmail.com>\n// Copyright (C) 2014 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// Copyright (C) 2013 Gauthier Brun <brun.gauthier@gmail.com>\n// Copyright (C) 2013 Nicolas Carre <nicolas.carre@ensimag.fr>\n// Copyright (C) 2013 Jean Ceccato <jean.ceccato@ensimag.fr>\n// Copyright (C) 2013 Pierre Zoppitelli <pierre.zoppitelli@ensimag.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SVDBASE_H\n#define EIGEN_SVDBASE_H\n\nnamespace Eigen {\n/** \\ingroup SVD_Module\n *\n *\n * \\class SVDBase\n *\n * \\brief Base class of SVD algorithms\n *\n * \\tparam Derived the type of the actual SVD decomposition\n *\n * SVD decomposition consists in decomposing any n-by-p matrix \\a A as a product\n *   \\f[ A = U S V^* \\f]\n * where \\a U is a n-by-n unitary, \\a V is a p-by-p unitary, and \\a S is a n-by-p real positive matrix which is zero outside of its main diagonal;\n * the diagonal entries of S are known as the \\em singular \\em values of \\a A and the columns of \\a U and \\a V are known as the left\n * and right \\em singular \\em vectors of \\a A respectively.\n *\n * Singular values are always sorted in decreasing order.\n *\n * \n * You can ask for only \\em thin \\a U or \\a V to be computed, meaning the following. In case of a rectangular n-by-p matrix, letting \\a m be the\n * smaller value among \\a n and \\a p, there are only \\a m singular vectors; the remaining columns of \\a U and \\a V do not correspond to actual\n * singular vectors. Asking for \\em thin \\a U or \\a V means asking for only their \\a m first columns to be formed. So \\a U is then a n-by-m matrix,\n * and \\a V is then a p-by-m matrix. Notice that thin \\a U and \\a V are all you need for (least squares) solving.\n *  \n * If the input matrix has inf or nan coefficients, the result of the computation is undefined, but the computation is guaranteed to\n * terminate in finite (and reasonable) time.\n * \\sa class BDCSVD, class JacobiSVD\n */\ntemplate<typename Derived>\nclass SVDBase\n{\n\npublic:\n  typedef typename internal::traits<Derived>::MatrixType MatrixType;\n  typedef typename MatrixType::Scalar Scalar;\n  typedef typename NumTraits<typename MatrixType::Scalar>::Real RealScalar;\n  typedef typename MatrixType::StorageIndex StorageIndex;\n  typedef Eigen::Index Index; ///< \\deprecated since Eigen 3.3\n  enum {\n    RowsAtCompileTime = MatrixType::RowsAtCompileTime,\n    ColsAtCompileTime = MatrixType::ColsAtCompileTime,\n    DiagSizeAtCompileTime = EIGEN_SIZE_MIN_PREFER_DYNAMIC(RowsAtCompileTime,ColsAtCompileTime),\n    MaxRowsAtCompileTime = MatrixType::MaxRowsAtCompileTime,\n    MaxColsAtCompileTime = MatrixType::MaxColsAtCompileTime,\n    MaxDiagSizeAtCompileTime = EIGEN_SIZE_MIN_PREFER_FIXED(MaxRowsAtCompileTime,MaxColsAtCompileTime),\n    MatrixOptions = MatrixType::Options\n  };\n\n  typedef Matrix<Scalar, RowsAtCompileTime, RowsAtCompileTime, MatrixOptions, MaxRowsAtCompileTime, MaxRowsAtCompileTime> MatrixUType;\n  typedef Matrix<Scalar, ColsAtCompileTime, ColsAtCompileTime, MatrixOptions, MaxColsAtCompileTime, MaxColsAtCompileTime> MatrixVType;\n  typedef typename internal::plain_diag_type<MatrixType, RealScalar>::type SingularValuesType;\n  \n  Derived& derived() { return *static_cast<Derived*>(this); }\n  const Derived& derived() const { return *static_cast<const Derived*>(this); }\n\n  /** \\returns the \\a U matrix.\n   *\n   * For the SVD decomposition of a n-by-p matrix, letting \\a m be the minimum of \\a n and \\a p,\n   * the U matrix is n-by-n if you asked for \\link Eigen::ComputeFullU ComputeFullU \\endlink, and is n-by-m if you asked for \\link Eigen::ComputeThinU ComputeThinU \\endlink.\n   *\n   * The \\a m first columns of \\a U are the left singular vectors of the matrix being decomposed.\n   *\n   * This method asserts that you asked for \\a U to be computed.\n   */\n  const MatrixUType& matrixU() const\n  {\n    eigen_assert(m_isInitialized && \"SVD is not initialized.\");\n    eigen_assert(computeU() && \"This SVD decomposition didn't compute U. Did you ask for it?\");\n    return m_matrixU;\n  }\n\n  /** \\returns the \\a V matrix.\n   *\n   * For the SVD decomposition of a n-by-p matrix, letting \\a m be the minimum of \\a n and \\a p,\n   * the V matrix is p-by-p if you asked for \\link Eigen::ComputeFullV ComputeFullV \\endlink, and is p-by-m if you asked for \\link Eigen::ComputeThinV ComputeThinV \\endlink.\n   *\n   * The \\a m first columns of \\a V are the right singular vectors of the matrix being decomposed.\n   *\n   * This method asserts that you asked for \\a V to be computed.\n   */\n  const MatrixVType& matrixV() const\n  {\n    eigen_assert(m_isInitialized && \"SVD is not initialized.\");\n    eigen_assert(computeV() && \"This SVD decomposition didn't compute V. Did you ask for it?\");\n    return m_matrixV;\n  }\n\n  /** \\returns the vector of singular values.\n   *\n   * For the SVD decomposition of a n-by-p matrix, letting \\a m be the minimum of \\a n and \\a p, the\n   * returned vector has size \\a m.  Singular values are always sorted in decreasing order.\n   */\n  const SingularValuesType& singularValues() const\n  {\n    eigen_assert(m_isInitialized && \"SVD is not initialized.\");\n    return m_singularValues;\n  }\n\n  /** \\returns the number of singular values that are not exactly 0 */\n  Index nonzeroSingularValues() const\n  {\n    eigen_assert(m_isInitialized && \"SVD is not initialized.\");\n    return m_nonzeroSingularValues;\n  }\n  \n  /** \\returns the rank of the matrix of which \\c *this is the SVD.\n    *\n    * \\note This method has to determine which singular values should be considered nonzero.\n    *       For that, it uses the threshold value that you can control by calling\n    *       setThreshold(const RealScalar&).\n    */\n  inline Index rank() const\n  {\n    using std::abs;\n    eigen_assert(m_isInitialized && \"JacobiSVD is not initialized.\");\n    if(m_singularValues.size()==0) return 0;\n    RealScalar premultiplied_threshold = numext::maxi<RealScalar>(m_singularValues.coeff(0) * threshold(), (std::numeric_limits<RealScalar>::min)());\n    Index i = m_nonzeroSingularValues-1;\n    while(i>=0 && m_singularValues.coeff(i) < premultiplied_threshold) --i;\n    return i+1;\n  }\n  \n  /** Allows to prescribe a threshold to be used by certain methods, such as rank() and solve(),\n    * which need to determine when singular values are to be considered nonzero.\n    * This is not used for the SVD decomposition itself.\n    *\n    * When it needs to get the threshold value, Eigen calls threshold().\n    * The default is \\c NumTraits<Scalar>::epsilon()\n    *\n    * \\param threshold The new value to use as the threshold.\n    *\n    * A singular value will be considered nonzero if its value is strictly greater than\n    *  \\f$ \\vert singular value \\vert \\leqslant threshold \\times \\vert max singular value \\vert \\f$.\n    *\n    * If you want to come back to the default behavior, call setThreshold(Default_t)\n    */\n  Derived& setThreshold(const RealScalar& threshold)\n  {\n    m_usePrescribedThreshold = true;\n    m_prescribedThreshold = threshold;\n    return derived();\n  }\n\n  /** Allows to come back to the default behavior, letting Eigen use its default formula for\n    * determining the threshold.\n    *\n    * You should pass the special object Eigen::Default as parameter here.\n    * \\code svd.setThreshold(Eigen::Default); \\endcode\n    *\n    * See the documentation of setThreshold(const RealScalar&).\n    */\n  Derived& setThreshold(Default_t)\n  {\n    m_usePrescribedThreshold = false;\n    return derived();\n  }\n\n  /** Returns the threshold that will be used by certain methods such as rank().\n    *\n    * See the documentation of setThreshold(const RealScalar&).\n    */\n  RealScalar threshold() const\n  {\n    eigen_assert(m_isInitialized || m_usePrescribedThreshold);\n    return m_usePrescribedThreshold ? m_prescribedThreshold\n                                    : (std::max<Index>)(1,m_diagSize)*NumTraits<Scalar>::epsilon();\n  }\n\n  /** \\returns true if \\a U (full or thin) is asked for in this SVD decomposition */\n  inline bool computeU() const { return m_computeFullU || m_computeThinU; }\n  /** \\returns true if \\a V (full or thin) is asked for in this SVD decomposition */\n  inline bool computeV() const { return m_computeFullV || m_computeThinV; }\n\n  inline Index rows() const { return m_rows; }\n  inline Index cols() const { return m_cols; }\n  \n  /** \\returns a (least squares) solution of \\f$ A x = b \\f$ using the current SVD decomposition of A.\n    *\n    * \\param b the right-hand-side of the equation to solve.\n    *\n    * \\note Solving requires both U and V to be computed. Thin U and V are enough, there is no need for full U or V.\n    *\n    * \\note SVD solving is implicitly least-squares. Thus, this method serves both purposes of exact solving and least-squares solving.\n    * In other words, the returned solution is guaranteed to minimize the Euclidean norm \\f$ \\Vert A x - b \\Vert \\f$.\n    */\n  template<typename Rhs>\n  inline const Solve<Derived, Rhs>\n  solve(const MatrixBase<Rhs>& b) const\n  {\n    eigen_assert(m_isInitialized && \"SVD is not initialized.\");\n    eigen_assert(computeU() && computeV() && \"SVD::solve() requires both unitaries U and V to be computed (thin unitaries suffice).\");\n    return Solve<Derived, Rhs>(derived(), b.derived());\n  }\n  \n  #ifndef EIGEN_PARSED_BY_DOXYGEN\n  template<typename RhsType, typename DstType>\n  EIGEN_DEVICE_FUNC\n  void _solve_impl(const RhsType &rhs, DstType &dst) const;\n  #endif\n\nprotected:\n  \n  static void check_template_parameters()\n  {\n    EIGEN_STATIC_ASSERT_NON_INTEGER(Scalar);\n  }\n  \n  // return true if already allocated\n  bool allocate(Index rows, Index cols, unsigned int computationOptions) ;\n\n  MatrixUType m_matrixU;\n  MatrixVType m_matrixV;\n  SingularValuesType m_singularValues;\n  bool m_isInitialized, m_isAllocated, m_usePrescribedThreshold;\n  bool m_computeFullU, m_computeThinU;\n  bool m_computeFullV, m_computeThinV;\n  unsigned int m_computationOptions;\n  Index m_nonzeroSingularValues, m_rows, m_cols, m_diagSize;\n  RealScalar m_prescribedThreshold;\n\n  /** \\brief Default Constructor.\n   *\n   * Default constructor of SVDBase\n   */\n  SVDBase()\n    : m_isInitialized(false),\n      m_isAllocated(false),\n      m_usePrescribedThreshold(false),\n      m_computationOptions(0),\n      m_rows(-1), m_cols(-1), m_diagSize(0)\n  {\n    check_template_parameters();\n  }\n\n\n};\n\n#ifndef EIGEN_PARSED_BY_DOXYGEN\ntemplate<typename Derived>\ntemplate<typename RhsType, typename DstType>\nvoid SVDBase<Derived>::_solve_impl(const RhsType &rhs, DstType &dst) const\n{\n  eigen_assert(rhs.rows() == rows());\n\n  // A = U S V^*\n  // So A^{-1} = V S^{-1} U^*\n\n  Matrix<Scalar, Dynamic, RhsType::ColsAtCompileTime, 0, MatrixType::MaxRowsAtCompileTime, RhsType::MaxColsAtCompileTime> tmp;\n  Index l_rank = rank();\n  tmp.noalias() =  m_matrixU.leftCols(l_rank).adjoint() * rhs;\n  tmp = m_singularValues.head(l_rank).asDiagonal().inverse() * tmp;\n  dst = m_matrixV.leftCols(l_rank) * tmp;\n}\n#endif\n\ntemplate<typename MatrixType>\nbool SVDBase<MatrixType>::allocate(Index rows, Index cols, unsigned int computationOptions)\n{\n  eigen_assert(rows >= 0 && cols >= 0);\n\n  if (m_isAllocated &&\n      rows == m_rows &&\n      cols == m_cols &&\n      computationOptions == m_computationOptions)\n  {\n    return true;\n  }\n\n  m_rows = rows;\n  m_cols = cols;\n  m_isInitialized = false;\n  m_isAllocated = true;\n  m_computationOptions = computationOptions;\n  m_computeFullU = (computationOptions & ComputeFullU) != 0;\n  m_computeThinU = (computationOptions & ComputeThinU) != 0;\n  m_computeFullV = (computationOptions & ComputeFullV) != 0;\n  m_computeThinV = (computationOptions & ComputeThinV) != 0;\n  eigen_assert(!(m_computeFullU && m_computeThinU) && \"SVDBase: you can't ask for both full and thin U\");\n  eigen_assert(!(m_computeFullV && m_computeThinV) && \"SVDBase: you can't ask for both full and thin V\");\n  eigen_assert(EIGEN_IMPLIES(m_computeThinU || m_computeThinV, MatrixType::ColsAtCompileTime==Dynamic) &&\n\t       \"SVDBase: thin U and V are only available when your matrix has a dynamic number of columns.\");\n\n  m_diagSize = (std::min)(m_rows, m_cols);\n  m_singularValues.resize(m_diagSize);\n  if(RowsAtCompileTime==Dynamic)\n    m_matrixU.resize(m_rows, m_computeFullU ? m_rows : m_computeThinU ? m_diagSize : 0);\n  if(ColsAtCompileTime==Dynamic)\n    m_matrixV.resize(m_cols, m_computeFullV ? m_cols : m_computeThinV ? m_diagSize : 0);\n\n  return false;\n}\n\n}// end namespace\n\n#endif // EIGEN_SVDBASE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SVD/UpperBidiagonalization.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2010 Benoit Jacob <jacob.benoit.1@gmail.com>\n// Copyright (C) 2013-2014 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_BIDIAGONALIZATION_H\n#define EIGEN_BIDIAGONALIZATION_H\n\nnamespace Eigen { \n\nnamespace internal {\n// UpperBidiagonalization will probably be replaced by a Bidiagonalization class, don't want to make it stable API.\n// At the same time, it's useful to keep for now as it's about the only thing that is testing the BandMatrix class.\n\ntemplate<typename _MatrixType> class UpperBidiagonalization\n{\n  public:\n\n    typedef _MatrixType MatrixType;\n    enum {\n      RowsAtCompileTime = MatrixType::RowsAtCompileTime,\n      ColsAtCompileTime = MatrixType::ColsAtCompileTime,\n      ColsAtCompileTimeMinusOne = internal::decrement_size<ColsAtCompileTime>::ret\n    };\n    typedef typename MatrixType::Scalar Scalar;\n    typedef typename MatrixType::RealScalar RealScalar;\n    typedef Eigen::Index Index; ///< \\deprecated since Eigen 3.3\n    typedef Matrix<Scalar, 1, ColsAtCompileTime> RowVectorType;\n    typedef Matrix<Scalar, RowsAtCompileTime, 1> ColVectorType;\n    typedef BandMatrix<RealScalar, ColsAtCompileTime, ColsAtCompileTime, 1, 0, RowMajor> BidiagonalType;\n    typedef Matrix<Scalar, ColsAtCompileTime, 1> DiagVectorType;\n    typedef Matrix<Scalar, ColsAtCompileTimeMinusOne, 1> SuperDiagVectorType;\n    typedef HouseholderSequence<\n              const MatrixType,\n              const typename internal::remove_all<typename Diagonal<const MatrixType,0>::ConjugateReturnType>::type\n            > HouseholderUSequenceType;\n    typedef HouseholderSequence<\n              const typename internal::remove_all<typename MatrixType::ConjugateReturnType>::type,\n              Diagonal<const MatrixType,1>,\n              OnTheRight\n            > HouseholderVSequenceType;\n    \n    /**\n    * \\brief Default Constructor.\n    *\n    * The default constructor is useful in cases in which the user intends to\n    * perform decompositions via Bidiagonalization::compute(const MatrixType&).\n    */\n    UpperBidiagonalization() : m_householder(), m_bidiagonal(), m_isInitialized(false) {}\n\n    explicit UpperBidiagonalization(const MatrixType& matrix)\n      : m_householder(matrix.rows(), matrix.cols()),\n        m_bidiagonal(matrix.cols(), matrix.cols()),\n        m_isInitialized(false)\n    {\n      compute(matrix);\n    }\n    \n    UpperBidiagonalization& compute(const MatrixType& matrix);\n    UpperBidiagonalization& computeUnblocked(const MatrixType& matrix);\n    \n    const MatrixType& householder() const { return m_householder; }\n    const BidiagonalType& bidiagonal() const { return m_bidiagonal; }\n    \n    const HouseholderUSequenceType householderU() const\n    {\n      eigen_assert(m_isInitialized && \"UpperBidiagonalization is not initialized.\");\n      return HouseholderUSequenceType(m_householder, m_householder.diagonal().conjugate());\n    }\n\n    const HouseholderVSequenceType householderV() // const here gives nasty errors and i'm lazy\n    {\n      eigen_assert(m_isInitialized && \"UpperBidiagonalization is not initialized.\");\n      return HouseholderVSequenceType(m_householder.conjugate(), m_householder.const_derived().template diagonal<1>())\n             .setLength(m_householder.cols()-1)\n             .setShift(1);\n    }\n    \n  protected:\n    MatrixType m_householder;\n    BidiagonalType m_bidiagonal;\n    bool m_isInitialized;\n};\n\n// Standard upper bidiagonalization without fancy optimizations\n// This version should be faster for small matrix size\ntemplate<typename MatrixType>\nvoid upperbidiagonalization_inplace_unblocked(MatrixType& mat,\n                                              typename MatrixType::RealScalar *diagonal,\n                                              typename MatrixType::RealScalar *upper_diagonal,\n                                              typename MatrixType::Scalar* tempData = 0)\n{\n  typedef typename MatrixType::Scalar Scalar;\n\n  Index rows = mat.rows();\n  Index cols = mat.cols();\n\n  typedef Matrix<Scalar,Dynamic,1,ColMajor,MatrixType::MaxRowsAtCompileTime,1> TempType;\n  TempType tempVector;\n  if(tempData==0)\n  {\n    tempVector.resize(rows);\n    tempData = tempVector.data();\n  }\n\n  for (Index k = 0; /* breaks at k==cols-1 below */ ; ++k)\n  {\n    Index remainingRows = rows - k;\n    Index remainingCols = cols - k - 1;\n\n    // construct left householder transform in-place in A\n    mat.col(k).tail(remainingRows)\n       .makeHouseholderInPlace(mat.coeffRef(k,k), diagonal[k]);\n    // apply householder transform to remaining part of A on the left\n    mat.bottomRightCorner(remainingRows, remainingCols)\n       .applyHouseholderOnTheLeft(mat.col(k).tail(remainingRows-1), mat.coeff(k,k), tempData);\n\n    if(k == cols-1) break;\n\n    // construct right householder transform in-place in mat\n    mat.row(k).tail(remainingCols)\n       .makeHouseholderInPlace(mat.coeffRef(k,k+1), upper_diagonal[k]);\n    // apply householder transform to remaining part of mat on the left\n    mat.bottomRightCorner(remainingRows-1, remainingCols)\n       .applyHouseholderOnTheRight(mat.row(k).tail(remainingCols-1).transpose(), mat.coeff(k,k+1), tempData);\n  }\n}\n\n/** \\internal\n  * Helper routine for the block reduction to upper bidiagonal form.\n  *\n  * Let's partition the matrix A:\n  * \n  *      | A00 A01 |\n  *  A = |         |\n  *      | A10 A11 |\n  *\n  * This function reduces to bidiagonal form the left \\c rows x \\a blockSize vertical panel [A00/A10]\n  * and the \\a blockSize x \\c cols horizontal panel [A00 A01] of the matrix \\a A. The bottom-right block A11\n  * is updated using matrix-matrix products:\n  *   A22 -= V * Y^T - X * U^T\n  * where V and U contains the left and right Householder vectors. U and V are stored in A10, and A01\n  * respectively, and the update matrices X and Y are computed during the reduction.\n  * \n  */\ntemplate<typename MatrixType>\nvoid upperbidiagonalization_blocked_helper(MatrixType& A,\n                                           typename MatrixType::RealScalar *diagonal,\n                                           typename MatrixType::RealScalar *upper_diagonal,\n                                           Index bs,\n                                           Ref<Matrix<typename MatrixType::Scalar, Dynamic, Dynamic,\n                                                      traits<MatrixType>::Flags & RowMajorBit> > X,\n                                           Ref<Matrix<typename MatrixType::Scalar, Dynamic, Dynamic,\n                                                      traits<MatrixType>::Flags & RowMajorBit> > Y)\n{\n  typedef typename MatrixType::Scalar Scalar;\n  enum { StorageOrder = traits<MatrixType>::Flags & RowMajorBit };\n  typedef InnerStride<int(StorageOrder) == int(ColMajor) ? 1 : Dynamic> ColInnerStride;\n  typedef InnerStride<int(StorageOrder) == int(ColMajor) ? Dynamic : 1> RowInnerStride;\n  typedef Ref<Matrix<Scalar, Dynamic, 1>, 0, ColInnerStride>    SubColumnType;\n  typedef Ref<Matrix<Scalar, 1, Dynamic>, 0, RowInnerStride>    SubRowType;\n  typedef Ref<Matrix<Scalar, Dynamic, Dynamic, StorageOrder > > SubMatType;\n  \n  Index brows = A.rows();\n  Index bcols = A.cols();\n\n  Scalar tau_u, tau_u_prev(0), tau_v;\n\n  for(Index k = 0; k < bs; ++k)\n  {\n    Index remainingRows = brows - k;\n    Index remainingCols = bcols - k - 1;\n\n    SubMatType X_k1( X.block(k,0, remainingRows,k) );\n    SubMatType V_k1( A.block(k,0, remainingRows,k) );\n\n    // 1 - update the k-th column of A\n    SubColumnType v_k = A.col(k).tail(remainingRows);\n          v_k -= V_k1 * Y.row(k).head(k).adjoint();\n    if(k) v_k -= X_k1 * A.col(k).head(k);\n    \n    // 2 - construct left Householder transform in-place\n    v_k.makeHouseholderInPlace(tau_v, diagonal[k]);\n       \n    if(k+1<bcols)\n    {\n      SubMatType Y_k  ( Y.block(k+1,0, remainingCols, k+1) );\n      SubMatType U_k1 ( A.block(0,k+1, k,remainingCols) );\n      \n      // this eases the application of Householder transforAions\n      // A(k,k) will store tau_v later\n      A(k,k) = Scalar(1);\n\n      // 3 - Compute y_k^T = tau_v * ( A^T*v_k - Y_k-1*V_k-1^T*v_k - U_k-1*X_k-1^T*v_k )\n      {\n        SubColumnType y_k( Y.col(k).tail(remainingCols) );\n        \n        // let's use the begining of column k of Y as a temporary vector\n        SubColumnType tmp( Y.col(k).head(k) );\n        y_k.noalias()  = A.block(k,k+1, remainingRows,remainingCols).adjoint() * v_k; // bottleneck\n        tmp.noalias()  = V_k1.adjoint()  * v_k;\n        y_k.noalias() -= Y_k.leftCols(k) * tmp;\n        tmp.noalias()  = X_k1.adjoint()  * v_k;\n        y_k.noalias() -= U_k1.adjoint()  * tmp;\n        y_k *= numext::conj(tau_v);\n      }\n\n      // 4 - update k-th row of A (it will become u_k)\n      SubRowType u_k( A.row(k).tail(remainingCols) );\n      u_k = u_k.conjugate();\n      {\n        u_k -= Y_k * A.row(k).head(k+1).adjoint();\n        if(k) u_k -= U_k1.adjoint() * X.row(k).head(k).adjoint();\n      }\n\n      // 5 - construct right Householder transform in-place\n      u_k.makeHouseholderInPlace(tau_u, upper_diagonal[k]);\n\n      // this eases the application of Householder transformations\n      // A(k,k+1) will store tau_u later\n      A(k,k+1) = Scalar(1);\n\n      // 6 - Compute x_k = tau_u * ( A*u_k - X_k-1*U_k-1^T*u_k - V_k*Y_k^T*u_k )\n      {\n        SubColumnType x_k ( X.col(k).tail(remainingRows-1) );\n        \n        // let's use the begining of column k of X as a temporary vectors\n        // note that tmp0 and tmp1 overlaps\n        SubColumnType tmp0 ( X.col(k).head(k) ),\n                      tmp1 ( X.col(k).head(k+1) );\n                    \n        x_k.noalias()   = A.block(k+1,k+1, remainingRows-1,remainingCols) * u_k.transpose(); // bottleneck\n        tmp0.noalias()  = U_k1 * u_k.transpose();\n        x_k.noalias()  -= X_k1.bottomRows(remainingRows-1) * tmp0;\n        tmp1.noalias()  = Y_k.adjoint() * u_k.transpose();\n        x_k.noalias()  -= A.block(k+1,0, remainingRows-1,k+1) * tmp1;\n        x_k *= numext::conj(tau_u);\n        tau_u = numext::conj(tau_u);\n        u_k = u_k.conjugate();\n      }\n\n      if(k>0) A.coeffRef(k-1,k) = tau_u_prev;\n      tau_u_prev = tau_u;\n    }\n    else\n      A.coeffRef(k-1,k) = tau_u_prev;\n\n    A.coeffRef(k,k) = tau_v;\n  }\n  \n  if(bs<bcols)\n    A.coeffRef(bs-1,bs) = tau_u_prev;\n\n  // update A22\n  if(bcols>bs && brows>bs)\n  {\n    SubMatType A11( A.bottomRightCorner(brows-bs,bcols-bs) );\n    SubMatType A10( A.block(bs,0, brows-bs,bs) );\n    SubMatType A01( A.block(0,bs, bs,bcols-bs) );\n    Scalar tmp = A01(bs-1,0);\n    A01(bs-1,0) = 1;\n    A11.noalias() -= A10 * Y.topLeftCorner(bcols,bs).bottomRows(bcols-bs).adjoint();\n    A11.noalias() -= X.topLeftCorner(brows,bs).bottomRows(brows-bs) * A01;\n    A01(bs-1,0) = tmp;\n  }\n}\n\n/** \\internal\n  *\n  * Implementation of a block-bidiagonal reduction.\n  * It is based on the following paper:\n  *   The Design of a Parallel Dense Linear Algebra Software Library: Reduction to Hessenberg, Tridiagonal, and Bidiagonal Form.\n  *   by Jaeyoung Choi, Jack J. Dongarra, David W. Walker. (1995)\n  *   section 3.3\n  */\ntemplate<typename MatrixType, typename BidiagType>\nvoid upperbidiagonalization_inplace_blocked(MatrixType& A, BidiagType& bidiagonal,\n                                            Index maxBlockSize=32,\n                                            typename MatrixType::Scalar* /*tempData*/ = 0)\n{\n  typedef typename MatrixType::Scalar Scalar;\n  typedef Block<MatrixType,Dynamic,Dynamic> BlockType;\n\n  Index rows = A.rows();\n  Index cols = A.cols();\n  Index size = (std::min)(rows, cols);\n\n  // X and Y are work space\n  enum { StorageOrder = traits<MatrixType>::Flags & RowMajorBit };\n  Matrix<Scalar,\n         MatrixType::RowsAtCompileTime,\n         Dynamic,\n         StorageOrder,\n         MatrixType::MaxRowsAtCompileTime> X(rows,maxBlockSize);\n  Matrix<Scalar,\n         MatrixType::ColsAtCompileTime,\n         Dynamic,\n         StorageOrder,\n         MatrixType::MaxColsAtCompileTime> Y(cols,maxBlockSize);\n  Index blockSize = (std::min)(maxBlockSize,size);\n\n  Index k = 0;\n  for(k = 0; k < size; k += blockSize)\n  {\n    Index bs = (std::min)(size-k,blockSize);  // actual size of the block\n    Index brows = rows - k;                   // rows of the block\n    Index bcols = cols - k;                   // columns of the block\n\n    // partition the matrix A:\n    // \n    //      | A00 A01 A02 |\n    //      |             |\n    // A  = | A10 A11 A12 |\n    //      |             |\n    //      | A20 A21 A22 |\n    //\n    // where A11 is a bs x bs diagonal block,\n    // and let:\n    //      | A11 A12 |\n    //  B = |         |\n    //      | A21 A22 |\n\n    BlockType B = A.block(k,k,brows,bcols);\n    \n    // This stage performs the bidiagonalization of A11, A21, A12, and updating of A22.\n    // Finally, the algorithm continue on the updated A22.\n    //\n    // However, if B is too small, or A22 empty, then let's use an unblocked strategy\n    if(k+bs==cols || bcols<48) // somewhat arbitrary threshold\n    {\n      upperbidiagonalization_inplace_unblocked(B,\n                                               &(bidiagonal.template diagonal<0>().coeffRef(k)),\n                                               &(bidiagonal.template diagonal<1>().coeffRef(k)),\n                                               X.data()\n                                              );\n      break; // We're done\n    }\n    else\n    {\n      upperbidiagonalization_blocked_helper<BlockType>( B,\n                                                        &(bidiagonal.template diagonal<0>().coeffRef(k)),\n                                                        &(bidiagonal.template diagonal<1>().coeffRef(k)),\n                                                        bs,\n                                                        X.topLeftCorner(brows,bs),\n                                                        Y.topLeftCorner(bcols,bs)\n                                                      );\n    }\n  }\n}\n\ntemplate<typename _MatrixType>\nUpperBidiagonalization<_MatrixType>& UpperBidiagonalization<_MatrixType>::computeUnblocked(const _MatrixType& matrix)\n{\n  Index rows = matrix.rows();\n  Index cols = matrix.cols();\n  EIGEN_ONLY_USED_FOR_DEBUG(cols);\n\n  eigen_assert(rows >= cols && \"UpperBidiagonalization is only for Arices satisfying rows>=cols.\");\n\n  m_householder = matrix;\n\n  ColVectorType temp(rows);\n\n  upperbidiagonalization_inplace_unblocked(m_householder,\n                                           &(m_bidiagonal.template diagonal<0>().coeffRef(0)),\n                                           &(m_bidiagonal.template diagonal<1>().coeffRef(0)),\n                                           temp.data());\n\n  m_isInitialized = true;\n  return *this;\n}\n\ntemplate<typename _MatrixType>\nUpperBidiagonalization<_MatrixType>& UpperBidiagonalization<_MatrixType>::compute(const _MatrixType& matrix)\n{\n  Index rows = matrix.rows();\n  Index cols = matrix.cols();\n  EIGEN_ONLY_USED_FOR_DEBUG(rows);\n  EIGEN_ONLY_USED_FOR_DEBUG(cols);\n\n  eigen_assert(rows >= cols && \"UpperBidiagonalization is only for Arices satisfying rows>=cols.\");\n\n  m_householder = matrix;\n  upperbidiagonalization_inplace_blocked(m_householder, m_bidiagonal);\n            \n  m_isInitialized = true;\n  return *this;\n}\n\n#if 0\n/** \\return the Householder QR decomposition of \\c *this.\n  *\n  * \\sa class Bidiagonalization\n  */\ntemplate<typename Derived>\nconst UpperBidiagonalization<typename MatrixBase<Derived>::PlainObject>\nMatrixBase<Derived>::bidiagonalization() const\n{\n  return UpperBidiagonalization<PlainObject>(eval());\n}\n#endif\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_BIDIAGONALIZATION_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseCholesky/SimplicialCholesky.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2012 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SIMPLICIAL_CHOLESKY_H\n#define EIGEN_SIMPLICIAL_CHOLESKY_H\n\nnamespace Eigen { \n\nenum SimplicialCholeskyMode {\n  SimplicialCholeskyLLT,\n  SimplicialCholeskyLDLT\n};\n\nnamespace internal {\n  template<typename CholMatrixType, typename InputMatrixType>\n  struct simplicial_cholesky_grab_input {\n    typedef CholMatrixType const * ConstCholMatrixPtr;\n    static void run(const InputMatrixType& input, ConstCholMatrixPtr &pmat, CholMatrixType &tmp)\n    {\n      tmp = input;\n      pmat = &tmp;\n    }\n  };\n  \n  template<typename MatrixType>\n  struct simplicial_cholesky_grab_input<MatrixType,MatrixType> {\n    typedef MatrixType const * ConstMatrixPtr;\n    static void run(const MatrixType& input, ConstMatrixPtr &pmat, MatrixType &/*tmp*/)\n    {\n      pmat = &input;\n    }\n  };\n} // end namespace internal\n\n/** \\ingroup SparseCholesky_Module\n  * \\brief A base class for direct sparse Cholesky factorizations\n  *\n  * This is a base class for LL^T and LDL^T Cholesky factorizations of sparse matrices that are\n  * selfadjoint and positive definite. These factorizations allow for solving A.X = B where\n  * X and B can be either dense or sparse.\n  * \n  * In order to reduce the fill-in, a symmetric permutation P is applied prior to the factorization\n  * such that the factorized matrix is P A P^-1.\n  *\n  * \\tparam Derived the type of the derived class, that is the actual factorization type.\n  *\n  */\ntemplate<typename Derived>\nclass SimplicialCholeskyBase : public SparseSolverBase<Derived>\n{\n    typedef SparseSolverBase<Derived> Base;\n    using Base::m_isInitialized;\n    \n  public:\n    typedef typename internal::traits<Derived>::MatrixType MatrixType;\n    typedef typename internal::traits<Derived>::OrderingType OrderingType;\n    enum { UpLo = internal::traits<Derived>::UpLo };\n    typedef typename MatrixType::Scalar Scalar;\n    typedef typename MatrixType::RealScalar RealScalar;\n    typedef typename MatrixType::StorageIndex StorageIndex;\n    typedef SparseMatrix<Scalar,ColMajor,StorageIndex> CholMatrixType;\n    typedef CholMatrixType const * ConstCholMatrixPtr;\n    typedef Matrix<Scalar,Dynamic,1> VectorType;\n    typedef Matrix<StorageIndex,Dynamic,1> VectorI;\n\n    enum {\n      ColsAtCompileTime = MatrixType::ColsAtCompileTime,\n      MaxColsAtCompileTime = MatrixType::MaxColsAtCompileTime\n    };\n\n  public:\n    \n    using Base::derived;\n\n    /** Default constructor */\n    SimplicialCholeskyBase()\n      : m_info(Success), m_shiftOffset(0), m_shiftScale(1)\n    {}\n\n    explicit SimplicialCholeskyBase(const MatrixType& matrix)\n      : m_info(Success), m_shiftOffset(0), m_shiftScale(1)\n    {\n      derived().compute(matrix);\n    }\n\n    ~SimplicialCholeskyBase()\n    {\n    }\n\n    Derived& derived() { return *static_cast<Derived*>(this); }\n    const Derived& derived() const { return *static_cast<const Derived*>(this); }\n    \n    inline Index cols() const { return m_matrix.cols(); }\n    inline Index rows() const { return m_matrix.rows(); }\n    \n    /** \\brief Reports whether previous computation was successful.\n      *\n      * \\returns \\c Success if computation was succesful,\n      *          \\c NumericalIssue if the matrix.appears to be negative.\n      */\n    ComputationInfo info() const\n    {\n      eigen_assert(m_isInitialized && \"Decomposition is not initialized.\");\n      return m_info;\n    }\n    \n    /** \\returns the permutation P\n      * \\sa permutationPinv() */\n    const PermutationMatrix<Dynamic,Dynamic,StorageIndex>& permutationP() const\n    { return m_P; }\n    \n    /** \\returns the inverse P^-1 of the permutation P\n      * \\sa permutationP() */\n    const PermutationMatrix<Dynamic,Dynamic,StorageIndex>& permutationPinv() const\n    { return m_Pinv; }\n\n    /** Sets the shift parameters that will be used to adjust the diagonal coefficients during the numerical factorization.\n      *\n      * During the numerical factorization, the diagonal coefficients are transformed by the following linear model:\\n\n      * \\c d_ii = \\a offset + \\a scale * \\c d_ii\n      *\n      * The default is the identity transformation with \\a offset=0, and \\a scale=1.\n      *\n      * \\returns a reference to \\c *this.\n      */\n    Derived& setShift(const RealScalar& offset, const RealScalar& scale = 1)\n    {\n      m_shiftOffset = offset;\n      m_shiftScale = scale;\n      return derived();\n    }\n\n#ifndef EIGEN_PARSED_BY_DOXYGEN\n    /** \\internal */\n    template<typename Stream>\n    void dumpMemory(Stream& s)\n    {\n      int total = 0;\n      s << \"  L:        \" << ((total+=(m_matrix.cols()+1) * sizeof(int) + m_matrix.nonZeros()*(sizeof(int)+sizeof(Scalar))) >> 20) << \"Mb\" << \"\\n\";\n      s << \"  diag:     \" << ((total+=m_diag.size() * sizeof(Scalar)) >> 20) << \"Mb\" << \"\\n\";\n      s << \"  tree:     \" << ((total+=m_parent.size() * sizeof(int)) >> 20) << \"Mb\" << \"\\n\";\n      s << \"  nonzeros: \" << ((total+=m_nonZerosPerCol.size() * sizeof(int)) >> 20) << \"Mb\" << \"\\n\";\n      s << \"  perm:     \" << ((total+=m_P.size() * sizeof(int)) >> 20) << \"Mb\" << \"\\n\";\n      s << \"  perm^-1:  \" << ((total+=m_Pinv.size() * sizeof(int)) >> 20) << \"Mb\" << \"\\n\";\n      s << \"  TOTAL:    \" << (total>> 20) << \"Mb\" << \"\\n\";\n    }\n\n    /** \\internal */\n    template<typename Rhs,typename Dest>\n    void _solve_impl(const MatrixBase<Rhs> &b, MatrixBase<Dest> &dest) const\n    {\n      eigen_assert(m_factorizationIsOk && \"The decomposition is not in a valid state for solving, you must first call either compute() or symbolic()/numeric()\");\n      eigen_assert(m_matrix.rows()==b.rows());\n\n      if(m_info!=Success)\n        return;\n\n      if(m_P.size()>0)\n        dest = m_P * b;\n      else\n        dest = b;\n\n      if(m_matrix.nonZeros()>0) // otherwise L==I\n        derived().matrixL().solveInPlace(dest);\n\n      if(m_diag.size()>0)\n        dest = m_diag.asDiagonal().inverse() * dest;\n\n      if (m_matrix.nonZeros()>0) // otherwise U==I\n        derived().matrixU().solveInPlace(dest);\n\n      if(m_P.size()>0)\n        dest = m_Pinv * dest;\n    }\n    \n    template<typename Rhs,typename Dest>\n    void _solve_impl(const SparseMatrixBase<Rhs> &b, SparseMatrixBase<Dest> &dest) const\n    {\n      internal::solve_sparse_through_dense_panels(derived(), b, dest);\n    }\n\n#endif // EIGEN_PARSED_BY_DOXYGEN\n\n  protected:\n    \n    /** Computes the sparse Cholesky decomposition of \\a matrix */\n    template<bool DoLDLT>\n    void compute(const MatrixType& matrix)\n    {\n      eigen_assert(matrix.rows()==matrix.cols());\n      Index size = matrix.cols();\n      CholMatrixType tmp(size,size);\n      ConstCholMatrixPtr pmat;\n      ordering(matrix, pmat, tmp);\n      analyzePattern_preordered(*pmat, DoLDLT);\n      factorize_preordered<DoLDLT>(*pmat);\n    }\n    \n    template<bool DoLDLT>\n    void factorize(const MatrixType& a)\n    {\n      eigen_assert(a.rows()==a.cols());\n      Index size = a.cols();\n      CholMatrixType tmp(size,size);\n      ConstCholMatrixPtr pmat;\n      \n      if(m_P.size()==0 && (UpLo&Upper)==Upper)\n      {\n        // If there is no ordering, try to directly use the input matrix without any copy\n        internal::simplicial_cholesky_grab_input<CholMatrixType,MatrixType>::run(a, pmat, tmp);\n      }\n      else\n      {\n        tmp.template selfadjointView<Upper>() = a.template selfadjointView<UpLo>().twistedBy(m_P);\n        pmat = &tmp;\n      }\n      \n      factorize_preordered<DoLDLT>(*pmat);\n    }\n\n    template<bool DoLDLT>\n    void factorize_preordered(const CholMatrixType& a);\n\n    void analyzePattern(const MatrixType& a, bool doLDLT)\n    {\n      eigen_assert(a.rows()==a.cols());\n      Index size = a.cols();\n      CholMatrixType tmp(size,size);\n      ConstCholMatrixPtr pmat;\n      ordering(a, pmat, tmp);\n      analyzePattern_preordered(*pmat,doLDLT);\n    }\n    void analyzePattern_preordered(const CholMatrixType& a, bool doLDLT);\n    \n    void ordering(const MatrixType& a, ConstCholMatrixPtr &pmat, CholMatrixType& ap);\n\n    /** keeps off-diagonal entries; drops diagonal entries */\n    struct keep_diag {\n      inline bool operator() (const Index& row, const Index& col, const Scalar&) const\n      {\n        return row!=col;\n      }\n    };\n\n    mutable ComputationInfo m_info;\n    bool m_factorizationIsOk;\n    bool m_analysisIsOk;\n    \n    CholMatrixType m_matrix;\n    VectorType m_diag;                                // the diagonal coefficients (LDLT mode)\n    VectorI m_parent;                                 // elimination tree\n    VectorI m_nonZerosPerCol;\n    PermutationMatrix<Dynamic,Dynamic,StorageIndex> m_P;     // the permutation\n    PermutationMatrix<Dynamic,Dynamic,StorageIndex> m_Pinv;  // the inverse permutation\n\n    RealScalar m_shiftOffset;\n    RealScalar m_shiftScale;\n};\n\ntemplate<typename _MatrixType, int _UpLo = Lower, typename _Ordering = AMDOrdering<typename _MatrixType::StorageIndex> > class SimplicialLLT;\ntemplate<typename _MatrixType, int _UpLo = Lower, typename _Ordering = AMDOrdering<typename _MatrixType::StorageIndex> > class SimplicialLDLT;\ntemplate<typename _MatrixType, int _UpLo = Lower, typename _Ordering = AMDOrdering<typename _MatrixType::StorageIndex> > class SimplicialCholesky;\n\nnamespace internal {\n\ntemplate<typename _MatrixType, int _UpLo, typename _Ordering> struct traits<SimplicialLLT<_MatrixType,_UpLo,_Ordering> >\n{\n  typedef _MatrixType MatrixType;\n  typedef _Ordering OrderingType;\n  enum { UpLo = _UpLo };\n  typedef typename MatrixType::Scalar                         Scalar;\n  typedef typename MatrixType::StorageIndex                   StorageIndex;\n  typedef SparseMatrix<Scalar, ColMajor, StorageIndex>        CholMatrixType;\n  typedef TriangularView<const CholMatrixType, Eigen::Lower>  MatrixL;\n  typedef TriangularView<const typename CholMatrixType::AdjointReturnType, Eigen::Upper>   MatrixU;\n  static inline MatrixL getL(const MatrixType& m) { return MatrixL(m); }\n  static inline MatrixU getU(const MatrixType& m) { return MatrixU(m.adjoint()); }\n};\n\ntemplate<typename _MatrixType,int _UpLo, typename _Ordering> struct traits<SimplicialLDLT<_MatrixType,_UpLo,_Ordering> >\n{\n  typedef _MatrixType MatrixType;\n  typedef _Ordering OrderingType;\n  enum { UpLo = _UpLo };\n  typedef typename MatrixType::Scalar                             Scalar;\n  typedef typename MatrixType::StorageIndex                       StorageIndex;\n  typedef SparseMatrix<Scalar, ColMajor, StorageIndex>            CholMatrixType;\n  typedef TriangularView<const CholMatrixType, Eigen::UnitLower>  MatrixL;\n  typedef TriangularView<const typename CholMatrixType::AdjointReturnType, Eigen::UnitUpper> MatrixU;\n  static inline MatrixL getL(const MatrixType& m) { return MatrixL(m); }\n  static inline MatrixU getU(const MatrixType& m) { return MatrixU(m.adjoint()); }\n};\n\ntemplate<typename _MatrixType, int _UpLo, typename _Ordering> struct traits<SimplicialCholesky<_MatrixType,_UpLo,_Ordering> >\n{\n  typedef _MatrixType MatrixType;\n  typedef _Ordering OrderingType;\n  enum { UpLo = _UpLo };\n};\n\n}\n\n/** \\ingroup SparseCholesky_Module\n  * \\class SimplicialLLT\n  * \\brief A direct sparse LLT Cholesky factorizations\n  *\n  * This class provides a LL^T Cholesky factorizations of sparse matrices that are\n  * selfadjoint and positive definite. The factorization allows for solving A.X = B where\n  * X and B can be either dense or sparse.\n  * \n  * In order to reduce the fill-in, a symmetric permutation P is applied prior to the factorization\n  * such that the factorized matrix is P A P^-1.\n  *\n  * \\tparam _MatrixType the type of the sparse matrix A, it must be a SparseMatrix<>\n  * \\tparam _UpLo the triangular part that will be used for the computations. It can be Lower\n  *               or Upper. Default is Lower.\n  * \\tparam _Ordering The ordering method to use, either AMDOrdering<> or NaturalOrdering<>. Default is AMDOrdering<>\n  *\n  * \\implsparsesolverconcept\n  *\n  * \\sa class SimplicialLDLT, class AMDOrdering, class NaturalOrdering\n  */\ntemplate<typename _MatrixType, int _UpLo, typename _Ordering>\n    class SimplicialLLT : public SimplicialCholeskyBase<SimplicialLLT<_MatrixType,_UpLo,_Ordering> >\n{\npublic:\n    typedef _MatrixType MatrixType;\n    enum { UpLo = _UpLo };\n    typedef SimplicialCholeskyBase<SimplicialLLT> Base;\n    typedef typename MatrixType::Scalar Scalar;\n    typedef typename MatrixType::RealScalar RealScalar;\n    typedef typename MatrixType::StorageIndex StorageIndex;\n    typedef SparseMatrix<Scalar,ColMajor,Index> CholMatrixType;\n    typedef Matrix<Scalar,Dynamic,1> VectorType;\n    typedef internal::traits<SimplicialLLT> Traits;\n    typedef typename Traits::MatrixL  MatrixL;\n    typedef typename Traits::MatrixU  MatrixU;\npublic:\n    /** Default constructor */\n    SimplicialLLT() : Base() {}\n    /** Constructs and performs the LLT factorization of \\a matrix */\n    explicit SimplicialLLT(const MatrixType& matrix)\n        : Base(matrix) {}\n\n    /** \\returns an expression of the factor L */\n    inline const MatrixL matrixL() const {\n        eigen_assert(Base::m_factorizationIsOk && \"Simplicial LLT not factorized\");\n        return Traits::getL(Base::m_matrix);\n    }\n\n    /** \\returns an expression of the factor U (= L^*) */\n    inline const MatrixU matrixU() const {\n        eigen_assert(Base::m_factorizationIsOk && \"Simplicial LLT not factorized\");\n        return Traits::getU(Base::m_matrix);\n    }\n    \n    /** Computes the sparse Cholesky decomposition of \\a matrix */\n    SimplicialLLT& compute(const MatrixType& matrix)\n    {\n      Base::template compute<false>(matrix);\n      return *this;\n    }\n\n    /** Performs a symbolic decomposition on the sparcity of \\a matrix.\n      *\n      * This function is particularly useful when solving for several problems having the same structure.\n      *\n      * \\sa factorize()\n      */\n    void analyzePattern(const MatrixType& a)\n    {\n      Base::analyzePattern(a, false);\n    }\n\n    /** Performs a numeric decomposition of \\a matrix\n      *\n      * The given matrix must has the same sparcity than the matrix on which the symbolic decomposition has been performed.\n      *\n      * \\sa analyzePattern()\n      */\n    void factorize(const MatrixType& a)\n    {\n      Base::template factorize<false>(a);\n    }\n\n    /** \\returns the determinant of the underlying matrix from the current factorization */\n    Scalar determinant() const\n    {\n      Scalar detL = Base::m_matrix.diagonal().prod();\n      return numext::abs2(detL);\n    }\n};\n\n/** \\ingroup SparseCholesky_Module\n  * \\class SimplicialLDLT\n  * \\brief A direct sparse LDLT Cholesky factorizations without square root.\n  *\n  * This class provides a LDL^T Cholesky factorizations without square root of sparse matrices that are\n  * selfadjoint and positive definite. The factorization allows for solving A.X = B where\n  * X and B can be either dense or sparse.\n  * \n  * In order to reduce the fill-in, a symmetric permutation P is applied prior to the factorization\n  * such that the factorized matrix is P A P^-1.\n  *\n  * \\tparam _MatrixType the type of the sparse matrix A, it must be a SparseMatrix<>\n  * \\tparam _UpLo the triangular part that will be used for the computations. It can be Lower\n  *               or Upper. Default is Lower.\n  * \\tparam _Ordering The ordering method to use, either AMDOrdering<> or NaturalOrdering<>. Default is AMDOrdering<>\n  *\n  * \\implsparsesolverconcept\n  *\n  * \\sa class SimplicialLLT, class AMDOrdering, class NaturalOrdering\n  */\ntemplate<typename _MatrixType, int _UpLo, typename _Ordering>\n    class SimplicialLDLT : public SimplicialCholeskyBase<SimplicialLDLT<_MatrixType,_UpLo,_Ordering> >\n{\npublic:\n    typedef _MatrixType MatrixType;\n    enum { UpLo = _UpLo };\n    typedef SimplicialCholeskyBase<SimplicialLDLT> Base;\n    typedef typename MatrixType::Scalar Scalar;\n    typedef typename MatrixType::RealScalar RealScalar;\n    typedef typename MatrixType::StorageIndex StorageIndex;\n    typedef SparseMatrix<Scalar,ColMajor,StorageIndex> CholMatrixType;\n    typedef Matrix<Scalar,Dynamic,1> VectorType;\n    typedef internal::traits<SimplicialLDLT> Traits;\n    typedef typename Traits::MatrixL  MatrixL;\n    typedef typename Traits::MatrixU  MatrixU;\npublic:\n    /** Default constructor */\n    SimplicialLDLT() : Base() {}\n\n    /** Constructs and performs the LLT factorization of \\a matrix */\n    explicit SimplicialLDLT(const MatrixType& matrix)\n        : Base(matrix) {}\n\n    /** \\returns a vector expression of the diagonal D */\n    inline const VectorType vectorD() const {\n        eigen_assert(Base::m_factorizationIsOk && \"Simplicial LDLT not factorized\");\n        return Base::m_diag;\n    }\n    /** \\returns an expression of the factor L */\n    inline const MatrixL matrixL() const {\n        eigen_assert(Base::m_factorizationIsOk && \"Simplicial LDLT not factorized\");\n        return Traits::getL(Base::m_matrix);\n    }\n\n    /** \\returns an expression of the factor U (= L^*) */\n    inline const MatrixU matrixU() const {\n        eigen_assert(Base::m_factorizationIsOk && \"Simplicial LDLT not factorized\");\n        return Traits::getU(Base::m_matrix);\n    }\n\n    /** Computes the sparse Cholesky decomposition of \\a matrix */\n    SimplicialLDLT& compute(const MatrixType& matrix)\n    {\n      Base::template compute<true>(matrix);\n      return *this;\n    }\n    \n    /** Performs a symbolic decomposition on the sparcity of \\a matrix.\n      *\n      * This function is particularly useful when solving for several problems having the same structure.\n      *\n      * \\sa factorize()\n      */\n    void analyzePattern(const MatrixType& a)\n    {\n      Base::analyzePattern(a, true);\n    }\n\n    /** Performs a numeric decomposition of \\a matrix\n      *\n      * The given matrix must has the same sparcity than the matrix on which the symbolic decomposition has been performed.\n      *\n      * \\sa analyzePattern()\n      */\n    void factorize(const MatrixType& a)\n    {\n      Base::template factorize<true>(a);\n    }\n\n    /** \\returns the determinant of the underlying matrix from the current factorization */\n    Scalar determinant() const\n    {\n      return Base::m_diag.prod();\n    }\n};\n\n/** \\deprecated use SimplicialLDLT or class SimplicialLLT\n  * \\ingroup SparseCholesky_Module\n  * \\class SimplicialCholesky\n  *\n  * \\sa class SimplicialLDLT, class SimplicialLLT\n  */\ntemplate<typename _MatrixType, int _UpLo, typename _Ordering>\n    class SimplicialCholesky : public SimplicialCholeskyBase<SimplicialCholesky<_MatrixType,_UpLo,_Ordering> >\n{\npublic:\n    typedef _MatrixType MatrixType;\n    enum { UpLo = _UpLo };\n    typedef SimplicialCholeskyBase<SimplicialCholesky> Base;\n    typedef typename MatrixType::Scalar Scalar;\n    typedef typename MatrixType::RealScalar RealScalar;\n    typedef typename MatrixType::StorageIndex StorageIndex;\n    typedef SparseMatrix<Scalar,ColMajor,StorageIndex> CholMatrixType;\n    typedef Matrix<Scalar,Dynamic,1> VectorType;\n    typedef internal::traits<SimplicialCholesky> Traits;\n    typedef internal::traits<SimplicialLDLT<MatrixType,UpLo> > LDLTTraits;\n    typedef internal::traits<SimplicialLLT<MatrixType,UpLo>  > LLTTraits;\n  public:\n    SimplicialCholesky() : Base(), m_LDLT(true) {}\n\n    explicit SimplicialCholesky(const MatrixType& matrix)\n      : Base(), m_LDLT(true)\n    {\n      compute(matrix);\n    }\n\n    SimplicialCholesky& setMode(SimplicialCholeskyMode mode)\n    {\n      switch(mode)\n      {\n      case SimplicialCholeskyLLT:\n        m_LDLT = false;\n        break;\n      case SimplicialCholeskyLDLT:\n        m_LDLT = true;\n        break;\n      default:\n        break;\n      }\n\n      return *this;\n    }\n\n    inline const VectorType vectorD() const {\n        eigen_assert(Base::m_factorizationIsOk && \"Simplicial Cholesky not factorized\");\n        return Base::m_diag;\n    }\n    inline const CholMatrixType rawMatrix() const {\n        eigen_assert(Base::m_factorizationIsOk && \"Simplicial Cholesky not factorized\");\n        return Base::m_matrix;\n    }\n    \n    /** Computes the sparse Cholesky decomposition of \\a matrix */\n    SimplicialCholesky& compute(const MatrixType& matrix)\n    {\n      if(m_LDLT)\n        Base::template compute<true>(matrix);\n      else\n        Base::template compute<false>(matrix);\n      return *this;\n    }\n\n    /** Performs a symbolic decomposition on the sparcity of \\a matrix.\n      *\n      * This function is particularly useful when solving for several problems having the same structure.\n      *\n      * \\sa factorize()\n      */\n    void analyzePattern(const MatrixType& a)\n    {\n      Base::analyzePattern(a, m_LDLT);\n    }\n\n    /** Performs a numeric decomposition of \\a matrix\n      *\n      * The given matrix must has the same sparcity than the matrix on which the symbolic decomposition has been performed.\n      *\n      * \\sa analyzePattern()\n      */\n    void factorize(const MatrixType& a)\n    {\n      if(m_LDLT)\n        Base::template factorize<true>(a);\n      else\n        Base::template factorize<false>(a);\n    }\n\n    /** \\internal */\n    template<typename Rhs,typename Dest>\n    void _solve_impl(const MatrixBase<Rhs> &b, MatrixBase<Dest> &dest) const\n    {\n      eigen_assert(Base::m_factorizationIsOk && \"The decomposition is not in a valid state for solving, you must first call either compute() or symbolic()/numeric()\");\n      eigen_assert(Base::m_matrix.rows()==b.rows());\n\n      if(Base::m_info!=Success)\n        return;\n\n      if(Base::m_P.size()>0)\n        dest = Base::m_P * b;\n      else\n        dest = b;\n\n      if(Base::m_matrix.nonZeros()>0) // otherwise L==I\n      {\n        if(m_LDLT)\n          LDLTTraits::getL(Base::m_matrix).solveInPlace(dest);\n        else\n          LLTTraits::getL(Base::m_matrix).solveInPlace(dest);\n      }\n\n      if(Base::m_diag.size()>0)\n        dest = Base::m_diag.asDiagonal().inverse() * dest;\n\n      if (Base::m_matrix.nonZeros()>0) // otherwise I==I\n      {\n        if(m_LDLT)\n          LDLTTraits::getU(Base::m_matrix).solveInPlace(dest);\n        else\n          LLTTraits::getU(Base::m_matrix).solveInPlace(dest);\n      }\n\n      if(Base::m_P.size()>0)\n        dest = Base::m_Pinv * dest;\n    }\n    \n    /** \\internal */\n    template<typename Rhs,typename Dest>\n    void _solve_impl(const SparseMatrixBase<Rhs> &b, SparseMatrixBase<Dest> &dest) const\n    {\n      internal::solve_sparse_through_dense_panels(*this, b, dest);\n    }\n    \n    Scalar determinant() const\n    {\n      if(m_LDLT)\n      {\n        return Base::m_diag.prod();\n      }\n      else\n      {\n        Scalar detL = Diagonal<const CholMatrixType>(Base::m_matrix).prod();\n        return numext::abs2(detL);\n      }\n    }\n    \n  protected:\n    bool m_LDLT;\n};\n\ntemplate<typename Derived>\nvoid SimplicialCholeskyBase<Derived>::ordering(const MatrixType& a, ConstCholMatrixPtr &pmat, CholMatrixType& ap)\n{\n  eigen_assert(a.rows()==a.cols());\n  const Index size = a.rows();\n  pmat = &ap;\n  // Note that ordering methods compute the inverse permutation\n  if(!internal::is_same<OrderingType,NaturalOrdering<Index> >::value)\n  {\n    {\n      CholMatrixType C;\n      C = a.template selfadjointView<UpLo>();\n      \n      OrderingType ordering;\n      ordering(C,m_Pinv);\n    }\n\n    if(m_Pinv.size()>0) m_P = m_Pinv.inverse();\n    else                m_P.resize(0);\n    \n    ap.resize(size,size);\n    ap.template selfadjointView<Upper>() = a.template selfadjointView<UpLo>().twistedBy(m_P);\n  }\n  else\n  {\n    m_Pinv.resize(0);\n    m_P.resize(0);\n    if(int(UpLo)==int(Lower) || MatrixType::IsRowMajor)\n    {\n      // we have to transpose the lower part to to the upper one\n      ap.resize(size,size);\n      ap.template selfadjointView<Upper>() = a.template selfadjointView<UpLo>();\n    }\n    else\n      internal::simplicial_cholesky_grab_input<CholMatrixType,MatrixType>::run(a, pmat, ap);\n  }  \n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_SIMPLICIAL_CHOLESKY_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseCholesky/SimplicialCholesky_impl.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2012 Gael Guennebaud <gael.guennebaud@inria.fr>\n\n/*\n\nNOTE: thes functions vave been adapted from the LDL library:\n\nLDL Copyright (c) 2005 by Timothy A. Davis.  All Rights Reserved.\n\nLDL License:\n\n    Your use or distribution of LDL or any modified version of\n    LDL implies that you agree to this License.\n\n    This library is free software; you can redistribute it and/or\n    modify it under the terms of the GNU Lesser General Public\n    License as published by the Free Software Foundation; either\n    version 2.1 of the License, or (at your option) any later version.\n\n    This library is distributed in the hope that it will be useful,\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n    Lesser General Public License for more details.\n\n    You should have received a copy of the GNU Lesser General Public\n    License along with this library; if not, write to the Free Software\n    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301\n    USA\n\n    Permission is hereby granted to use or copy this program under the\n    terms of the GNU LGPL, provided that the Copyright, this License,\n    and the Availability of the original version is retained on all copies.\n    User documentation of any code that uses this code or any modified\n    version of this code must cite the Copyright, this License, the\n    Availability note, and \"Used by permission.\" Permission to modify\n    the code and to distribute modified code is granted, provided the\n    Copyright, this License, and the Availability note are retained,\n    and a notice that the code was modified is included.\n */\n\n#include \"../Core/util/NonMPL2.h\"\n\n#ifndef EIGEN_SIMPLICIAL_CHOLESKY_IMPL_H\n#define EIGEN_SIMPLICIAL_CHOLESKY_IMPL_H\n\nnamespace Eigen {\n\ntemplate<typename Derived>\nvoid SimplicialCholeskyBase<Derived>::analyzePattern_preordered(const CholMatrixType& ap, bool doLDLT)\n{\n  const StorageIndex size = StorageIndex(ap.rows());\n  m_matrix.resize(size, size);\n  m_parent.resize(size);\n  m_nonZerosPerCol.resize(size);\n\n  ei_declare_aligned_stack_constructed_variable(StorageIndex, tags, size, 0);\n\n  for(StorageIndex k = 0; k < size; ++k)\n  {\n    /* L(k,:) pattern: all nodes reachable in etree from nz in A(0:k-1,k) */\n    m_parent[k] = -1;             /* parent of k is not yet known */\n    tags[k] = k;                  /* mark node k as visited */\n    m_nonZerosPerCol[k] = 0;      /* count of nonzeros in column k of L */\n    for(typename CholMatrixType::InnerIterator it(ap,k); it; ++it)\n    {\n      StorageIndex i = it.index();\n      if(i < k)\n      {\n        /* follow path from i to root of etree, stop at flagged node */\n        for(; tags[i] != k; i = m_parent[i])\n        {\n          /* find parent of i if not yet determined */\n          if (m_parent[i] == -1)\n            m_parent[i] = k;\n          m_nonZerosPerCol[i]++;        /* L (k,i) is nonzero */\n          tags[i] = k;                  /* mark i as visited */\n        }\n      }\n    }\n  }\n\n  /* construct Lp index array from m_nonZerosPerCol column counts */\n  StorageIndex* Lp = m_matrix.outerIndexPtr();\n  Lp[0] = 0;\n  for(StorageIndex k = 0; k < size; ++k)\n    Lp[k+1] = Lp[k] + m_nonZerosPerCol[k] + (doLDLT ? 0 : 1);\n\n  m_matrix.resizeNonZeros(Lp[size]);\n\n  m_isInitialized     = true;\n  m_info              = Success;\n  m_analysisIsOk      = true;\n  m_factorizationIsOk = false;\n}\n\n\ntemplate<typename Derived>\ntemplate<bool DoLDLT>\nvoid SimplicialCholeskyBase<Derived>::factorize_preordered(const CholMatrixType& ap)\n{\n  using std::sqrt;\n\n  eigen_assert(m_analysisIsOk && \"You must first call analyzePattern()\");\n  eigen_assert(ap.rows()==ap.cols());\n  eigen_assert(m_parent.size()==ap.rows());\n  eigen_assert(m_nonZerosPerCol.size()==ap.rows());\n\n  const StorageIndex size = StorageIndex(ap.rows());\n  const StorageIndex* Lp = m_matrix.outerIndexPtr();\n  StorageIndex* Li = m_matrix.innerIndexPtr();\n  Scalar* Lx = m_matrix.valuePtr();\n\n  ei_declare_aligned_stack_constructed_variable(Scalar, y, size, 0);\n  ei_declare_aligned_stack_constructed_variable(StorageIndex,  pattern, size, 0);\n  ei_declare_aligned_stack_constructed_variable(StorageIndex,  tags, size, 0);\n\n  bool ok = true;\n  m_diag.resize(DoLDLT ? size : 0);\n\n  for(StorageIndex k = 0; k < size; ++k)\n  {\n    // compute nonzero pattern of kth row of L, in topological order\n    y[k] = 0.0;                     // Y(0:k) is now all zero\n    StorageIndex top = size;               // stack for pattern is empty\n    tags[k] = k;                    // mark node k as visited\n    m_nonZerosPerCol[k] = 0;        // count of nonzeros in column k of L\n    for(typename CholMatrixType::InnerIterator it(ap,k); it; ++it)\n    {\n      StorageIndex i = it.index();\n      if(i <= k)\n      {\n        y[i] += numext::conj(it.value());            /* scatter A(i,k) into Y (sum duplicates) */\n        Index len;\n        for(len = 0; tags[i] != k; i = m_parent[i])\n        {\n          pattern[len++] = i;     /* L(k,i) is nonzero */\n          tags[i] = k;            /* mark i as visited */\n        }\n        while(len > 0)\n          pattern[--top] = pattern[--len];\n      }\n    }\n\n    /* compute numerical values kth row of L (a sparse triangular solve) */\n\n    RealScalar d = numext::real(y[k]) * m_shiftScale + m_shiftOffset;    // get D(k,k), apply the shift function, and clear Y(k)\n    y[k] = 0.0;\n    for(; top < size; ++top)\n    {\n      Index i = pattern[top];       /* pattern[top:n-1] is pattern of L(:,k) */\n      Scalar yi = y[i];             /* get and clear Y(i) */\n      y[i] = 0.0;\n\n      /* the nonzero entry L(k,i) */\n      Scalar l_ki;\n      if(DoLDLT)\n        l_ki = yi / m_diag[i];\n      else\n        yi = l_ki = yi / Lx[Lp[i]];\n\n      Index p2 = Lp[i] + m_nonZerosPerCol[i];\n      Index p;\n      for(p = Lp[i] + (DoLDLT ? 0 : 1); p < p2; ++p)\n        y[Li[p]] -= numext::conj(Lx[p]) * yi;\n      d -= numext::real(l_ki * numext::conj(yi));\n      Li[p] = k;                          /* store L(k,i) in column form of L */\n      Lx[p] = l_ki;\n      ++m_nonZerosPerCol[i];              /* increment count of nonzeros in col i */\n    }\n    if(DoLDLT)\n    {\n      m_diag[k] = d;\n      if(d == RealScalar(0))\n      {\n        ok = false;                         /* failure, D(k,k) is zero */\n        break;\n      }\n    }\n    else\n    {\n      Index p = Lp[k] + m_nonZerosPerCol[k]++;\n      Li[p] = k ;                /* store L(k,k) = sqrt (d) in column k */\n      if(d <= RealScalar(0)) {\n        ok = false;              /* failure, matrix is not positive definite */\n        break;\n      }\n      Lx[p] = sqrt(d) ;\n    }\n  }\n\n  m_info = ok ? Success : NumericalIssue;\n  m_factorizationIsOk = true;\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_SIMPLICIAL_CHOLESKY_IMPL_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseCore/AmbiVector.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_AMBIVECTOR_H\n#define EIGEN_AMBIVECTOR_H\n\nnamespace Eigen { \n\nnamespace internal {\n\n/** \\internal\n  * Hybrid sparse/dense vector class designed for intensive read-write operations.\n  *\n  * See BasicSparseLLT and SparseProduct for usage examples.\n  */\ntemplate<typename _Scalar, typename _StorageIndex>\nclass AmbiVector\n{\n  public:\n    typedef _Scalar Scalar;\n    typedef _StorageIndex StorageIndex;\n    typedef typename NumTraits<Scalar>::Real RealScalar;\n\n    explicit AmbiVector(Index size)\n      : m_buffer(0), m_zero(0), m_size(0), m_allocatedSize(0), m_allocatedElements(0), m_mode(-1)\n    {\n      resize(size);\n    }\n\n    void init(double estimatedDensity);\n    void init(int mode);\n\n    Index nonZeros() const;\n\n    /** Specifies a sub-vector to work on */\n    void setBounds(Index start, Index end) { m_start = convert_index(start); m_end = convert_index(end); }\n\n    void setZero();\n\n    void restart();\n    Scalar& coeffRef(Index i);\n    Scalar& coeff(Index i);\n\n    class Iterator;\n\n    ~AmbiVector() { delete[] m_buffer; }\n\n    void resize(Index size)\n    {\n      if (m_allocatedSize < size)\n        reallocate(size);\n      m_size = convert_index(size);\n    }\n\n    StorageIndex size() const { return m_size; }\n\n  protected:\n    StorageIndex convert_index(Index idx)\n    {\n      return internal::convert_index<StorageIndex>(idx);\n    }\n\n    void reallocate(Index size)\n    {\n      // if the size of the matrix is not too large, let's allocate a bit more than needed such\n      // that we can handle dense vector even in sparse mode.\n      delete[] m_buffer;\n      if (size<1000)\n      {\n        Index allocSize = (size * sizeof(ListEl) + sizeof(Scalar) - 1)/sizeof(Scalar);\n        m_allocatedElements = convert_index((allocSize*sizeof(Scalar))/sizeof(ListEl));\n        m_buffer = new Scalar[allocSize];\n      }\n      else\n      {\n        m_allocatedElements = convert_index((size*sizeof(Scalar))/sizeof(ListEl));\n        m_buffer = new Scalar[size];\n      }\n      m_size = convert_index(size);\n      m_start = 0;\n      m_end = m_size;\n    }\n\n    void reallocateSparse()\n    {\n      Index copyElements = m_allocatedElements;\n      m_allocatedElements = (std::min)(StorageIndex(m_allocatedElements*1.5),m_size);\n      Index allocSize = m_allocatedElements * sizeof(ListEl);\n      allocSize = (allocSize + sizeof(Scalar) - 1)/sizeof(Scalar);\n      Scalar* newBuffer = new Scalar[allocSize];\n      memcpy(newBuffer,  m_buffer,  copyElements * sizeof(ListEl));\n      delete[] m_buffer;\n      m_buffer = newBuffer;\n    }\n\n  protected:\n    // element type of the linked list\n    struct ListEl\n    {\n      StorageIndex next;\n      StorageIndex index;\n      Scalar value;\n    };\n\n    // used to store data in both mode\n    Scalar* m_buffer;\n    Scalar m_zero;\n    StorageIndex m_size;\n    StorageIndex m_start;\n    StorageIndex m_end;\n    StorageIndex m_allocatedSize;\n    StorageIndex m_allocatedElements;\n    StorageIndex m_mode;\n\n    // linked list mode\n    StorageIndex m_llStart;\n    StorageIndex m_llCurrent;\n    StorageIndex m_llSize;\n};\n\n/** \\returns the number of non zeros in the current sub vector */\ntemplate<typename _Scalar,typename _StorageIndex>\nIndex AmbiVector<_Scalar,_StorageIndex>::nonZeros() const\n{\n  if (m_mode==IsSparse)\n    return m_llSize;\n  else\n    return m_end - m_start;\n}\n\ntemplate<typename _Scalar,typename _StorageIndex>\nvoid AmbiVector<_Scalar,_StorageIndex>::init(double estimatedDensity)\n{\n  if (estimatedDensity>0.1)\n    init(IsDense);\n  else\n    init(IsSparse);\n}\n\ntemplate<typename _Scalar,typename _StorageIndex>\nvoid AmbiVector<_Scalar,_StorageIndex>::init(int mode)\n{\n  m_mode = mode;\n  if (m_mode==IsSparse)\n  {\n    m_llSize = 0;\n    m_llStart = -1;\n  }\n}\n\n/** Must be called whenever we might perform a write access\n  * with an index smaller than the previous one.\n  *\n  * Don't worry, this function is extremely cheap.\n  */\ntemplate<typename _Scalar,typename _StorageIndex>\nvoid AmbiVector<_Scalar,_StorageIndex>::restart()\n{\n  m_llCurrent = m_llStart;\n}\n\n/** Set all coefficients of current subvector to zero */\ntemplate<typename _Scalar,typename _StorageIndex>\nvoid AmbiVector<_Scalar,_StorageIndex>::setZero()\n{\n  if (m_mode==IsDense)\n  {\n    for (Index i=m_start; i<m_end; ++i)\n      m_buffer[i] = Scalar(0);\n  }\n  else\n  {\n    eigen_assert(m_mode==IsSparse);\n    m_llSize = 0;\n    m_llStart = -1;\n  }\n}\n\ntemplate<typename _Scalar,typename _StorageIndex>\n_Scalar& AmbiVector<_Scalar,_StorageIndex>::coeffRef(Index i)\n{\n  if (m_mode==IsDense)\n    return m_buffer[i];\n  else\n  {\n    ListEl* EIGEN_RESTRICT llElements = reinterpret_cast<ListEl*>(m_buffer);\n    // TODO factorize the following code to reduce code generation\n    eigen_assert(m_mode==IsSparse);\n    if (m_llSize==0)\n    {\n      // this is the first element\n      m_llStart = 0;\n      m_llCurrent = 0;\n      ++m_llSize;\n      llElements[0].value = Scalar(0);\n      llElements[0].index = convert_index(i);\n      llElements[0].next = -1;\n      return llElements[0].value;\n    }\n    else if (i<llElements[m_llStart].index)\n    {\n      // this is going to be the new first element of the list\n      ListEl& el = llElements[m_llSize];\n      el.value = Scalar(0);\n      el.index = convert_index(i);\n      el.next = m_llStart;\n      m_llStart = m_llSize;\n      ++m_llSize;\n      m_llCurrent = m_llStart;\n      return el.value;\n    }\n    else\n    {\n      StorageIndex nextel = llElements[m_llCurrent].next;\n      eigen_assert(i>=llElements[m_llCurrent].index && \"you must call restart() before inserting an element with lower or equal index\");\n      while (nextel >= 0 && llElements[nextel].index<=i)\n      {\n        m_llCurrent = nextel;\n        nextel = llElements[nextel].next;\n      }\n\n      if (llElements[m_llCurrent].index==i)\n      {\n        // the coefficient already exists and we found it !\n        return llElements[m_llCurrent].value;\n      }\n      else\n      {\n        if (m_llSize>=m_allocatedElements)\n        {\n          reallocateSparse();\n          llElements = reinterpret_cast<ListEl*>(m_buffer);\n        }\n        eigen_internal_assert(m_llSize<m_allocatedElements && \"internal error: overflow in sparse mode\");\n        // let's insert a new coefficient\n        ListEl& el = llElements[m_llSize];\n        el.value = Scalar(0);\n        el.index = convert_index(i);\n        el.next = llElements[m_llCurrent].next;\n        llElements[m_llCurrent].next = m_llSize;\n        ++m_llSize;\n        return el.value;\n      }\n    }\n  }\n}\n\ntemplate<typename _Scalar,typename _StorageIndex>\n_Scalar& AmbiVector<_Scalar,_StorageIndex>::coeff(Index i)\n{\n  if (m_mode==IsDense)\n    return m_buffer[i];\n  else\n  {\n    ListEl* EIGEN_RESTRICT llElements = reinterpret_cast<ListEl*>(m_buffer);\n    eigen_assert(m_mode==IsSparse);\n    if ((m_llSize==0) || (i<llElements[m_llStart].index))\n    {\n      return m_zero;\n    }\n    else\n    {\n      Index elid = m_llStart;\n      while (elid >= 0 && llElements[elid].index<i)\n        elid = llElements[elid].next;\n\n      if (llElements[elid].index==i)\n        return llElements[m_llCurrent].value;\n      else\n        return m_zero;\n    }\n  }\n}\n\n/** Iterator over the nonzero coefficients */\ntemplate<typename _Scalar,typename _StorageIndex>\nclass AmbiVector<_Scalar,_StorageIndex>::Iterator\n{\n  public:\n    typedef _Scalar Scalar;\n    typedef typename NumTraits<Scalar>::Real RealScalar;\n\n    /** Default constructor\n      * \\param vec the vector on which we iterate\n      * \\param epsilon the minimal value used to prune zero coefficients.\n      * In practice, all coefficients having a magnitude smaller than \\a epsilon\n      * are skipped.\n      */\n    explicit Iterator(const AmbiVector& vec, const RealScalar& epsilon = 0)\n      : m_vector(vec)\n    {\n      using std::abs;\n      m_epsilon = epsilon;\n      m_isDense = m_vector.m_mode==IsDense;\n      if (m_isDense)\n      {\n        m_currentEl = 0;   // this is to avoid a compilation warning\n        m_cachedValue = 0; // this is to avoid a compilation warning\n        m_cachedIndex = m_vector.m_start-1;\n        ++(*this);\n      }\n      else\n      {\n        ListEl* EIGEN_RESTRICT llElements = reinterpret_cast<ListEl*>(m_vector.m_buffer);\n        m_currentEl = m_vector.m_llStart;\n        while (m_currentEl>=0 && abs(llElements[m_currentEl].value)<=m_epsilon)\n          m_currentEl = llElements[m_currentEl].next;\n        if (m_currentEl<0)\n        {\n          m_cachedValue = 0; // this is to avoid a compilation warning\n          m_cachedIndex = -1;\n        }\n        else\n        {\n          m_cachedIndex = llElements[m_currentEl].index;\n          m_cachedValue = llElements[m_currentEl].value;\n        }\n      }\n    }\n\n    StorageIndex index() const { return m_cachedIndex; }\n    Scalar value() const { return m_cachedValue; }\n\n    operator bool() const { return m_cachedIndex>=0; }\n\n    Iterator& operator++()\n    {\n      using std::abs;\n      if (m_isDense)\n      {\n        do {\n          ++m_cachedIndex;\n        } while (m_cachedIndex<m_vector.m_end && abs(m_vector.m_buffer[m_cachedIndex])<m_epsilon);\n        if (m_cachedIndex<m_vector.m_end)\n          m_cachedValue = m_vector.m_buffer[m_cachedIndex];\n        else\n          m_cachedIndex=-1;\n      }\n      else\n      {\n        ListEl* EIGEN_RESTRICT llElements = reinterpret_cast<ListEl*>(m_vector.m_buffer);\n        do {\n          m_currentEl = llElements[m_currentEl].next;\n        } while (m_currentEl>=0 && abs(llElements[m_currentEl].value)<m_epsilon);\n        if (m_currentEl<0)\n        {\n          m_cachedIndex = -1;\n        }\n        else\n        {\n          m_cachedIndex = llElements[m_currentEl].index;\n          m_cachedValue = llElements[m_currentEl].value;\n        }\n      }\n      return *this;\n    }\n\n  protected:\n    const AmbiVector& m_vector; // the target vector\n    StorageIndex m_currentEl;            // the current element in sparse/linked-list mode\n    RealScalar m_epsilon;       // epsilon used to prune zero coefficients\n    StorageIndex m_cachedIndex;          // current coordinate\n    Scalar m_cachedValue;       // current value\n    bool m_isDense;             // mode of the vector\n};\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_AMBIVECTOR_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseCore/CompressedStorage.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2014 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_COMPRESSED_STORAGE_H\n#define EIGEN_COMPRESSED_STORAGE_H\n\nnamespace Eigen { \n\nnamespace internal {\n\n/** \\internal\n  * Stores a sparse set of values as a list of values and a list of indices.\n  *\n  */\ntemplate<typename _Scalar,typename _StorageIndex>\nclass CompressedStorage\n{\n  public:\n\n    typedef _Scalar Scalar;\n    typedef _StorageIndex StorageIndex;\n\n  protected:\n\n    typedef typename NumTraits<Scalar>::Real RealScalar;\n\n  public:\n\n    CompressedStorage()\n      : m_values(0), m_indices(0), m_size(0), m_allocatedSize(0)\n    {}\n\n    explicit CompressedStorage(Index size)\n      : m_values(0), m_indices(0), m_size(0), m_allocatedSize(0)\n    {\n      resize(size);\n    }\n\n    CompressedStorage(const CompressedStorage& other)\n      : m_values(0), m_indices(0), m_size(0), m_allocatedSize(0)\n    {\n      *this = other;\n    }\n\n    CompressedStorage& operator=(const CompressedStorage& other)\n    {\n      resize(other.size());\n      if(other.size()>0)\n      {\n        internal::smart_copy(other.m_values,  other.m_values  + m_size, m_values);\n        internal::smart_copy(other.m_indices, other.m_indices + m_size, m_indices);\n      }\n      return *this;\n    }\n\n    void swap(CompressedStorage& other)\n    {\n      std::swap(m_values, other.m_values);\n      std::swap(m_indices, other.m_indices);\n      std::swap(m_size, other.m_size);\n      std::swap(m_allocatedSize, other.m_allocatedSize);\n    }\n\n    ~CompressedStorage()\n    {\n      delete[] m_values;\n      delete[] m_indices;\n    }\n\n    void reserve(Index size)\n    {\n      Index newAllocatedSize = m_size + size;\n      if (newAllocatedSize > m_allocatedSize)\n        reallocate(newAllocatedSize);\n    }\n\n    void squeeze()\n    {\n      if (m_allocatedSize>m_size)\n        reallocate(m_size);\n    }\n\n    void resize(Index size, double reserveSizeFactor = 0)\n    {\n      if (m_allocatedSize<size)\n      {\n        Index realloc_size = (std::min<Index>)(NumTraits<StorageIndex>::highest(),  size + Index(reserveSizeFactor*double(size)));\n        if(realloc_size<size)\n          internal::throw_std_bad_alloc();\n        reallocate(realloc_size);\n      }\n      m_size = size;\n    }\n\n    void append(const Scalar& v, Index i)\n    {\n      Index id = m_size;\n      resize(m_size+1, 1);\n      m_values[id] = v;\n      m_indices[id] = internal::convert_index<StorageIndex>(i);\n    }\n\n    inline Index size() const { return m_size; }\n    inline Index allocatedSize() const { return m_allocatedSize; }\n    inline void clear() { m_size = 0; }\n\n    const Scalar* valuePtr() const { return m_values; }\n    Scalar* valuePtr() { return m_values; }\n    const StorageIndex* indexPtr() const { return m_indices; }\n    StorageIndex* indexPtr() { return m_indices; }\n\n    inline Scalar& value(Index i) { eigen_internal_assert(m_values!=0); return m_values[i]; }\n    inline const Scalar& value(Index i) const { eigen_internal_assert(m_values!=0); return m_values[i]; }\n\n    inline StorageIndex& index(Index i) { eigen_internal_assert(m_indices!=0); return m_indices[i]; }\n    inline const StorageIndex& index(Index i) const { eigen_internal_assert(m_indices!=0); return m_indices[i]; }\n\n    /** \\returns the largest \\c k such that for all \\c j in [0,k) index[\\c j]\\<\\a key */\n    inline Index searchLowerIndex(Index key) const\n    {\n      return searchLowerIndex(0, m_size, key);\n    }\n\n    /** \\returns the largest \\c k in [start,end) such that for all \\c j in [start,k) index[\\c j]\\<\\a key */\n    inline Index searchLowerIndex(Index start, Index end, Index key) const\n    {\n      while(end>start)\n      {\n        Index mid = (end+start)>>1;\n        if (m_indices[mid]<key)\n          start = mid+1;\n        else\n          end = mid;\n      }\n      return start;\n    }\n\n    /** \\returns the stored value at index \\a key\n      * If the value does not exist, then the value \\a defaultValue is returned without any insertion. */\n    inline Scalar at(Index key, const Scalar& defaultValue = Scalar(0)) const\n    {\n      if (m_size==0)\n        return defaultValue;\n      else if (key==m_indices[m_size-1])\n        return m_values[m_size-1];\n      // ^^  optimization: let's first check if it is the last coefficient\n      // (very common in high level algorithms)\n      const Index id = searchLowerIndex(0,m_size-1,key);\n      return ((id<m_size) && (m_indices[id]==key)) ? m_values[id] : defaultValue;\n    }\n\n    /** Like at(), but the search is performed in the range [start,end) */\n    inline Scalar atInRange(Index start, Index end, Index key, const Scalar &defaultValue = Scalar(0)) const\n    {\n      if (start>=end)\n        return defaultValue;\n      else if (end>start && key==m_indices[end-1])\n        return m_values[end-1];\n      // ^^  optimization: let's first check if it is the last coefficient\n      // (very common in high level algorithms)\n      const Index id = searchLowerIndex(start,end-1,key);\n      return ((id<end) && (m_indices[id]==key)) ? m_values[id] : defaultValue;\n    }\n\n    /** \\returns a reference to the value at index \\a key\n      * If the value does not exist, then the value \\a defaultValue is inserted\n      * such that the keys are sorted. */\n    inline Scalar& atWithInsertion(Index key, const Scalar& defaultValue = Scalar(0))\n    {\n      Index id = searchLowerIndex(0,m_size,key);\n      if (id>=m_size || m_indices[id]!=key)\n      {\n        if (m_allocatedSize<m_size+1)\n        {\n          m_allocatedSize = 2*(m_size+1);\n          internal::scoped_array<Scalar> newValues(m_allocatedSize);\n          internal::scoped_array<StorageIndex> newIndices(m_allocatedSize);\n\n          // copy first chunk\n          internal::smart_copy(m_values,  m_values +id, newValues.ptr());\n          internal::smart_copy(m_indices, m_indices+id, newIndices.ptr());\n\n          // copy the rest\n          if(m_size>id)\n          {\n            internal::smart_copy(m_values +id,  m_values +m_size, newValues.ptr() +id+1);\n            internal::smart_copy(m_indices+id,  m_indices+m_size, newIndices.ptr()+id+1);\n          }\n          std::swap(m_values,newValues.ptr());\n          std::swap(m_indices,newIndices.ptr());\n        }\n        else if(m_size>id)\n        {\n          internal::smart_memmove(m_values +id, m_values +m_size, m_values +id+1);\n          internal::smart_memmove(m_indices+id, m_indices+m_size, m_indices+id+1);\n        }\n        m_size++;\n        m_indices[id] = internal::convert_index<StorageIndex>(key);\n        m_values[id] = defaultValue;\n      }\n      return m_values[id];\n    }\n\n    void prune(const Scalar& reference, const RealScalar& epsilon = NumTraits<RealScalar>::dummy_precision())\n    {\n      Index k = 0;\n      Index n = size();\n      for (Index i=0; i<n; ++i)\n      {\n        if (!internal::isMuchSmallerThan(value(i), reference, epsilon))\n        {\n          value(k) = value(i);\n          index(k) = index(i);\n          ++k;\n        }\n      }\n      resize(k,0);\n    }\n\n  protected:\n\n    inline void reallocate(Index size)\n    {\n      #ifdef EIGEN_SPARSE_COMPRESSED_STORAGE_REALLOCATE_PLUGIN\n        EIGEN_SPARSE_COMPRESSED_STORAGE_REALLOCATE_PLUGIN\n      #endif\n      eigen_internal_assert(size!=m_allocatedSize);\n      internal::scoped_array<Scalar> newValues(size);\n      internal::scoped_array<StorageIndex> newIndices(size);\n      Index copySize = (std::min)(size, m_size);\n      if (copySize>0) {\n        internal::smart_copy(m_values, m_values+copySize, newValues.ptr());\n        internal::smart_copy(m_indices, m_indices+copySize, newIndices.ptr());\n      }\n      std::swap(m_values,newValues.ptr());\n      std::swap(m_indices,newIndices.ptr());\n      m_allocatedSize = size;\n    }\n\n  protected:\n    Scalar* m_values;\n    StorageIndex* m_indices;\n    Index m_size;\n    Index m_allocatedSize;\n\n};\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_COMPRESSED_STORAGE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseCore/ConservativeSparseSparseProduct.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2015 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_CONSERVATIVESPARSESPARSEPRODUCT_H\n#define EIGEN_CONSERVATIVESPARSESPARSEPRODUCT_H\n\nnamespace Eigen { \n\nnamespace internal {\n\ntemplate<typename Lhs, typename Rhs, typename ResultType>\nstatic void conservative_sparse_sparse_product_impl(const Lhs& lhs, const Rhs& rhs, ResultType& res, bool sortedInsertion = false)\n{\n  typedef typename remove_all<Lhs>::type::Scalar Scalar;\n\n  // make sure to call innerSize/outerSize since we fake the storage order.\n  Index rows = lhs.innerSize();\n  Index cols = rhs.outerSize();\n  eigen_assert(lhs.outerSize() == rhs.innerSize());\n  \n  ei_declare_aligned_stack_constructed_variable(bool,   mask,     rows, 0);\n  ei_declare_aligned_stack_constructed_variable(Scalar, values,   rows, 0);\n  ei_declare_aligned_stack_constructed_variable(Index,  indices,  rows, 0);\n  \n  std::memset(mask,0,sizeof(bool)*rows);\n\n  evaluator<Lhs> lhsEval(lhs);\n  evaluator<Rhs> rhsEval(rhs);\n  \n  // estimate the number of non zero entries\n  // given a rhs column containing Y non zeros, we assume that the respective Y columns\n  // of the lhs differs in average of one non zeros, thus the number of non zeros for\n  // the product of a rhs column with the lhs is X+Y where X is the average number of non zero\n  // per column of the lhs.\n  // Therefore, we have nnz(lhs*rhs) = nnz(lhs) + nnz(rhs)\n  Index estimated_nnz_prod = lhsEval.nonZerosEstimate() + rhsEval.nonZerosEstimate();\n\n  res.setZero();\n  res.reserve(Index(estimated_nnz_prod));\n  // we compute each column of the result, one after the other\n  for (Index j=0; j<cols; ++j)\n  {\n\n    res.startVec(j);\n    Index nnz = 0;\n    for (typename evaluator<Rhs>::InnerIterator rhsIt(rhsEval, j); rhsIt; ++rhsIt)\n    {\n      Scalar y = rhsIt.value();\n      Index k = rhsIt.index();\n      for (typename evaluator<Lhs>::InnerIterator lhsIt(lhsEval, k); lhsIt; ++lhsIt)\n      {\n        Index i = lhsIt.index();\n        Scalar x = lhsIt.value();\n        if(!mask[i])\n        {\n          mask[i] = true;\n          values[i] = x * y;\n          indices[nnz] = i;\n          ++nnz;\n        }\n        else\n          values[i] += x * y;\n      }\n    }\n    if(!sortedInsertion)\n    {\n      // unordered insertion\n      for(Index k=0; k<nnz; ++k)\n      {\n        Index i = indices[k];\n        res.insertBackByOuterInnerUnordered(j,i) = values[i];\n        mask[i] = false;\n      }\n    }\n    else\n    {\n      // alternative ordered insertion code:\n      const Index t200 = rows/11; // 11 == (log2(200)*1.39)\n      const Index t = (rows*100)/139;\n\n      // FIXME reserve nnz non zeros\n      // FIXME implement faster sorting algorithms for very small nnz\n      // if the result is sparse enough => use a quick sort\n      // otherwise => loop through the entire vector\n      // In order to avoid to perform an expensive log2 when the\n      // result is clearly very sparse we use a linear bound up to 200.\n      if((nnz<200 && nnz<t200) || nnz * numext::log2(int(nnz)) < t)\n      {\n        if(nnz>1) std::sort(indices,indices+nnz);\n        for(Index k=0; k<nnz; ++k)\n        {\n          Index i = indices[k];\n          res.insertBackByOuterInner(j,i) = values[i];\n          mask[i] = false;\n        }\n      }\n      else\n      {\n        // dense path\n        for(Index i=0; i<rows; ++i)\n        {\n          if(mask[i])\n          {\n            mask[i] = false;\n            res.insertBackByOuterInner(j,i) = values[i];\n          }\n        }\n      }\n    }\n  }\n  res.finalize();\n}\n\n\n} // end namespace internal\n\nnamespace internal {\n\ntemplate<typename Lhs, typename Rhs, typename ResultType,\n  int LhsStorageOrder = (traits<Lhs>::Flags&RowMajorBit) ? RowMajor : ColMajor,\n  int RhsStorageOrder = (traits<Rhs>::Flags&RowMajorBit) ? RowMajor : ColMajor,\n  int ResStorageOrder = (traits<ResultType>::Flags&RowMajorBit) ? RowMajor : ColMajor>\nstruct conservative_sparse_sparse_product_selector;\n\ntemplate<typename Lhs, typename Rhs, typename ResultType>\nstruct conservative_sparse_sparse_product_selector<Lhs,Rhs,ResultType,ColMajor,ColMajor,ColMajor>\n{\n  typedef typename remove_all<Lhs>::type LhsCleaned;\n  typedef typename LhsCleaned::Scalar Scalar;\n\n  static void run(const Lhs& lhs, const Rhs& rhs, ResultType& res)\n  {\n    typedef SparseMatrix<typename ResultType::Scalar,RowMajor,typename ResultType::StorageIndex> RowMajorMatrix;\n    typedef SparseMatrix<typename ResultType::Scalar,ColMajor,typename ResultType::StorageIndex> ColMajorMatrixAux;\n    typedef typename sparse_eval<ColMajorMatrixAux,ResultType::RowsAtCompileTime,ResultType::ColsAtCompileTime,ColMajorMatrixAux::Flags>::type ColMajorMatrix;\n    \n    // If the result is tall and thin (in the extreme case a column vector)\n    // then it is faster to sort the coefficients inplace instead of transposing twice.\n    // FIXME, the following heuristic is probably not very good.\n    if(lhs.rows()>rhs.cols())\n    {\n      ColMajorMatrix resCol(lhs.rows(),rhs.cols());\n      // perform sorted insertion\n      internal::conservative_sparse_sparse_product_impl<Lhs,Rhs,ColMajorMatrix>(lhs, rhs, resCol, true);\n      res = resCol.markAsRValue();\n    }\n    else\n    {\n      ColMajorMatrixAux resCol(lhs.rows(),rhs.cols());\n      // ressort to transpose to sort the entries\n      internal::conservative_sparse_sparse_product_impl<Lhs,Rhs,ColMajorMatrixAux>(lhs, rhs, resCol, false);\n      RowMajorMatrix resRow(resCol);\n      res = resRow.markAsRValue();\n    }\n  }\n};\n\ntemplate<typename Lhs, typename Rhs, typename ResultType>\nstruct conservative_sparse_sparse_product_selector<Lhs,Rhs,ResultType,RowMajor,ColMajor,ColMajor>\n{\n  static void run(const Lhs& lhs, const Rhs& rhs, ResultType& res)\n  {\n     typedef SparseMatrix<typename ResultType::Scalar,RowMajor,typename ResultType::StorageIndex> RowMajorMatrix;\n     RowMajorMatrix rhsRow = rhs;\n     RowMajorMatrix resRow(lhs.rows(), rhs.cols());\n     internal::conservative_sparse_sparse_product_impl<RowMajorMatrix,Lhs,RowMajorMatrix>(rhsRow, lhs, resRow);\n     res = resRow;\n  }\n};\n\ntemplate<typename Lhs, typename Rhs, typename ResultType>\nstruct conservative_sparse_sparse_product_selector<Lhs,Rhs,ResultType,ColMajor,RowMajor,ColMajor>\n{\n  static void run(const Lhs& lhs, const Rhs& rhs, ResultType& res)\n  {\n    typedef SparseMatrix<typename ResultType::Scalar,RowMajor,typename ResultType::StorageIndex> RowMajorMatrix;\n    RowMajorMatrix lhsRow = lhs;\n    RowMajorMatrix resRow(lhs.rows(), rhs.cols());\n    internal::conservative_sparse_sparse_product_impl<Rhs,RowMajorMatrix,RowMajorMatrix>(rhs, lhsRow, resRow);\n    res = resRow;\n  }\n};\n\ntemplate<typename Lhs, typename Rhs, typename ResultType>\nstruct conservative_sparse_sparse_product_selector<Lhs,Rhs,ResultType,RowMajor,RowMajor,ColMajor>\n{\n  static void run(const Lhs& lhs, const Rhs& rhs, ResultType& res)\n  {\n    typedef SparseMatrix<typename ResultType::Scalar,RowMajor,typename ResultType::StorageIndex> RowMajorMatrix;\n    RowMajorMatrix resRow(lhs.rows(), rhs.cols());\n    internal::conservative_sparse_sparse_product_impl<Rhs,Lhs,RowMajorMatrix>(rhs, lhs, resRow);\n    res = resRow;\n  }\n};\n\n\ntemplate<typename Lhs, typename Rhs, typename ResultType>\nstruct conservative_sparse_sparse_product_selector<Lhs,Rhs,ResultType,ColMajor,ColMajor,RowMajor>\n{\n  typedef typename traits<typename remove_all<Lhs>::type>::Scalar Scalar;\n\n  static void run(const Lhs& lhs, const Rhs& rhs, ResultType& res)\n  {\n    typedef SparseMatrix<typename ResultType::Scalar,ColMajor,typename ResultType::StorageIndex> ColMajorMatrix;\n    ColMajorMatrix resCol(lhs.rows(), rhs.cols());\n    internal::conservative_sparse_sparse_product_impl<Lhs,Rhs,ColMajorMatrix>(lhs, rhs, resCol);\n    res = resCol;\n  }\n};\n\ntemplate<typename Lhs, typename Rhs, typename ResultType>\nstruct conservative_sparse_sparse_product_selector<Lhs,Rhs,ResultType,RowMajor,ColMajor,RowMajor>\n{\n  static void run(const Lhs& lhs, const Rhs& rhs, ResultType& res)\n  {\n    typedef SparseMatrix<typename ResultType::Scalar,ColMajor,typename ResultType::StorageIndex> ColMajorMatrix;\n    ColMajorMatrix lhsCol = lhs;\n    ColMajorMatrix resCol(lhs.rows(), rhs.cols());\n    internal::conservative_sparse_sparse_product_impl<ColMajorMatrix,Rhs,ColMajorMatrix>(lhsCol, rhs, resCol);\n    res = resCol;\n  }\n};\n\ntemplate<typename Lhs, typename Rhs, typename ResultType>\nstruct conservative_sparse_sparse_product_selector<Lhs,Rhs,ResultType,ColMajor,RowMajor,RowMajor>\n{\n  static void run(const Lhs& lhs, const Rhs& rhs, ResultType& res)\n  {\n    typedef SparseMatrix<typename ResultType::Scalar,ColMajor,typename ResultType::StorageIndex> ColMajorMatrix;\n    ColMajorMatrix rhsCol = rhs;\n    ColMajorMatrix resCol(lhs.rows(), rhs.cols());\n    internal::conservative_sparse_sparse_product_impl<Lhs,ColMajorMatrix,ColMajorMatrix>(lhs, rhsCol, resCol);\n    res = resCol;\n  }\n};\n\ntemplate<typename Lhs, typename Rhs, typename ResultType>\nstruct conservative_sparse_sparse_product_selector<Lhs,Rhs,ResultType,RowMajor,RowMajor,RowMajor>\n{\n  static void run(const Lhs& lhs, const Rhs& rhs, ResultType& res)\n  {\n    typedef SparseMatrix<typename ResultType::Scalar,RowMajor,typename ResultType::StorageIndex> RowMajorMatrix;\n    typedef SparseMatrix<typename ResultType::Scalar,ColMajor,typename ResultType::StorageIndex> ColMajorMatrix;\n    RowMajorMatrix resRow(lhs.rows(),rhs.cols());\n    internal::conservative_sparse_sparse_product_impl<Rhs,Lhs,RowMajorMatrix>(rhs, lhs, resRow);\n    // sort the non zeros:\n    ColMajorMatrix resCol(resRow);\n    res = resCol;\n  }\n};\n\n} // end namespace internal\n\n\nnamespace internal {\n\ntemplate<typename Lhs, typename Rhs, typename ResultType>\nstatic void sparse_sparse_to_dense_product_impl(const Lhs& lhs, const Rhs& rhs, ResultType& res)\n{\n  typedef typename remove_all<Lhs>::type::Scalar Scalar;\n  Index cols = rhs.outerSize();\n  eigen_assert(lhs.outerSize() == rhs.innerSize());\n\n  evaluator<Lhs> lhsEval(lhs);\n  evaluator<Rhs> rhsEval(rhs);\n\n  for (Index j=0; j<cols; ++j)\n  {\n    for (typename evaluator<Rhs>::InnerIterator rhsIt(rhsEval, j); rhsIt; ++rhsIt)\n    {\n      Scalar y = rhsIt.value();\n      Index k = rhsIt.index();\n      for (typename evaluator<Lhs>::InnerIterator lhsIt(lhsEval, k); lhsIt; ++lhsIt)\n      {\n        Index i = lhsIt.index();\n        Scalar x = lhsIt.value();\n        res.coeffRef(i,j) += x * y;\n      }\n    }\n  }\n}\n\n\n} // end namespace internal\n\nnamespace internal {\n\ntemplate<typename Lhs, typename Rhs, typename ResultType,\n  int LhsStorageOrder = (traits<Lhs>::Flags&RowMajorBit) ? RowMajor : ColMajor,\n  int RhsStorageOrder = (traits<Rhs>::Flags&RowMajorBit) ? RowMajor : ColMajor>\nstruct sparse_sparse_to_dense_product_selector;\n\ntemplate<typename Lhs, typename Rhs, typename ResultType>\nstruct sparse_sparse_to_dense_product_selector<Lhs,Rhs,ResultType,ColMajor,ColMajor>\n{\n  static void run(const Lhs& lhs, const Rhs& rhs, ResultType& res)\n  {\n    internal::sparse_sparse_to_dense_product_impl<Lhs,Rhs,ResultType>(lhs, rhs, res);\n  }\n};\n\ntemplate<typename Lhs, typename Rhs, typename ResultType>\nstruct sparse_sparse_to_dense_product_selector<Lhs,Rhs,ResultType,RowMajor,ColMajor>\n{\n  static void run(const Lhs& lhs, const Rhs& rhs, ResultType& res)\n  {\n    typedef SparseMatrix<typename ResultType::Scalar,ColMajor,typename ResultType::StorageIndex> ColMajorMatrix;\n    ColMajorMatrix lhsCol(lhs);\n    internal::sparse_sparse_to_dense_product_impl<ColMajorMatrix,Rhs,ResultType>(lhsCol, rhs, res);\n  }\n};\n\ntemplate<typename Lhs, typename Rhs, typename ResultType>\nstruct sparse_sparse_to_dense_product_selector<Lhs,Rhs,ResultType,ColMajor,RowMajor>\n{\n  static void run(const Lhs& lhs, const Rhs& rhs, ResultType& res)\n  {\n    typedef SparseMatrix<typename ResultType::Scalar,ColMajor,typename ResultType::StorageIndex> ColMajorMatrix;\n    ColMajorMatrix rhsCol(rhs);\n    internal::sparse_sparse_to_dense_product_impl<Lhs,ColMajorMatrix,ResultType>(lhs, rhsCol, res);\n  }\n};\n\ntemplate<typename Lhs, typename Rhs, typename ResultType>\nstruct sparse_sparse_to_dense_product_selector<Lhs,Rhs,ResultType,RowMajor,RowMajor>\n{\n  static void run(const Lhs& lhs, const Rhs& rhs, ResultType& res)\n  {\n    Transpose<ResultType> trRes(res);\n    internal::sparse_sparse_to_dense_product_impl<Rhs,Lhs,Transpose<ResultType> >(rhs, lhs, trRes);\n  }\n};\n\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_CONSERVATIVESPARSESPARSEPRODUCT_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseCore/MappedSparseMatrix.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2014 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_MAPPED_SPARSEMATRIX_H\n#define EIGEN_MAPPED_SPARSEMATRIX_H\n\nnamespace Eigen {\n\n/** \\deprecated Use Map<SparseMatrix<> >\n  * \\class MappedSparseMatrix\n  *\n  * \\brief Sparse matrix\n  *\n  * \\param _Scalar the scalar type, i.e. the type of the coefficients\n  *\n  * See http://www.netlib.org/linalg/html_templates/node91.html for details on the storage scheme.\n  *\n  */\nnamespace internal {\ntemplate<typename _Scalar, int _Flags, typename _StorageIndex>\nstruct traits<MappedSparseMatrix<_Scalar, _Flags, _StorageIndex> > : traits<SparseMatrix<_Scalar, _Flags, _StorageIndex> >\n{};\n} // end namespace internal\n\ntemplate<typename _Scalar, int _Flags, typename _StorageIndex>\nclass MappedSparseMatrix\n  : public Map<SparseMatrix<_Scalar, _Flags, _StorageIndex> >\n{\n    typedef Map<SparseMatrix<_Scalar, _Flags, _StorageIndex> > Base;\n\n  public:\n    \n    typedef typename Base::StorageIndex StorageIndex;\n    typedef typename Base::Scalar Scalar;\n\n    inline MappedSparseMatrix(Index rows, Index cols, Index nnz, StorageIndex* outerIndexPtr, StorageIndex* innerIndexPtr, Scalar* valuePtr, StorageIndex* innerNonZeroPtr = 0)\n      : Base(rows, cols, nnz, outerIndexPtr, innerIndexPtr, valuePtr, innerNonZeroPtr)\n    {}\n\n    /** Empty destructor */\n    inline ~MappedSparseMatrix() {}\n};\n\nnamespace internal {\n\ntemplate<typename _Scalar, int _Options, typename _StorageIndex>\nstruct evaluator<MappedSparseMatrix<_Scalar,_Options,_StorageIndex> >\n  : evaluator<SparseCompressedBase<MappedSparseMatrix<_Scalar,_Options,_StorageIndex> > >\n{\n  typedef MappedSparseMatrix<_Scalar,_Options,_StorageIndex> XprType;\n  typedef evaluator<SparseCompressedBase<XprType> > Base;\n  \n  evaluator() : Base() {}\n  explicit evaluator(const XprType &mat) : Base(mat) {}\n};\n\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_MAPPED_SPARSEMATRIX_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseCore/SparseAssign.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2014 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SPARSEASSIGN_H\n#define EIGEN_SPARSEASSIGN_H\n\nnamespace Eigen { \n\ntemplate<typename Derived>    \ntemplate<typename OtherDerived>\nDerived& SparseMatrixBase<Derived>::operator=(const EigenBase<OtherDerived> &other)\n{\n  internal::call_assignment_no_alias(derived(), other.derived());\n  return derived();\n}\n\ntemplate<typename Derived>\ntemplate<typename OtherDerived>\nDerived& SparseMatrixBase<Derived>::operator=(const ReturnByValue<OtherDerived>& other)\n{\n  // TODO use the evaluator mechanism\n  other.evalTo(derived());\n  return derived();\n}\n\ntemplate<typename Derived>\ntemplate<typename OtherDerived>\ninline Derived& SparseMatrixBase<Derived>::operator=(const SparseMatrixBase<OtherDerived>& other)\n{\n  // by default sparse evaluation do not alias, so we can safely bypass the generic call_assignment routine\n  internal::Assignment<Derived,OtherDerived,internal::assign_op<Scalar,typename OtherDerived::Scalar> >\n          ::run(derived(), other.derived(), internal::assign_op<Scalar,typename OtherDerived::Scalar>());\n  return derived();\n}\n\ntemplate<typename Derived>\ninline Derived& SparseMatrixBase<Derived>::operator=(const Derived& other)\n{\n  internal::call_assignment_no_alias(derived(), other.derived());\n  return derived();\n}\n\nnamespace internal {\n\ntemplate<>\nstruct storage_kind_to_evaluator_kind<Sparse> {\n  typedef IteratorBased Kind;\n};\n\ntemplate<>\nstruct storage_kind_to_shape<Sparse> {\n  typedef SparseShape Shape;\n};\n\nstruct Sparse2Sparse {};\nstruct Sparse2Dense  {};\n\ntemplate<> struct AssignmentKind<SparseShape, SparseShape>           { typedef Sparse2Sparse Kind; };\ntemplate<> struct AssignmentKind<SparseShape, SparseTriangularShape> { typedef Sparse2Sparse Kind; };\ntemplate<> struct AssignmentKind<DenseShape,  SparseShape>           { typedef Sparse2Dense  Kind; };\ntemplate<> struct AssignmentKind<DenseShape,  SparseTriangularShape> { typedef Sparse2Dense  Kind; };\n\n\ntemplate<typename DstXprType, typename SrcXprType>\nvoid assign_sparse_to_sparse(DstXprType &dst, const SrcXprType &src)\n{\n  typedef typename DstXprType::Scalar Scalar;\n  typedef internal::evaluator<DstXprType> DstEvaluatorType;\n  typedef internal::evaluator<SrcXprType> SrcEvaluatorType;\n\n  SrcEvaluatorType srcEvaluator(src);\n\n  const bool transpose = (DstEvaluatorType::Flags & RowMajorBit) != (SrcEvaluatorType::Flags & RowMajorBit);\n  const Index outerEvaluationSize = (SrcEvaluatorType::Flags&RowMajorBit) ? src.rows() : src.cols();\n  if ((!transpose) && src.isRValue())\n  {\n    // eval without temporary\n    dst.resize(src.rows(), src.cols());\n    dst.setZero();\n    dst.reserve((std::max)(src.rows(),src.cols())*2);\n    for (Index j=0; j<outerEvaluationSize; ++j)\n    {\n      dst.startVec(j);\n      for (typename SrcEvaluatorType::InnerIterator it(srcEvaluator, j); it; ++it)\n      {\n        Scalar v = it.value();\n        dst.insertBackByOuterInner(j,it.index()) = v;\n      }\n    }\n    dst.finalize();\n  }\n  else\n  {\n    // eval through a temporary\n    eigen_assert(( ((internal::traits<DstXprType>::SupportedAccessPatterns & OuterRandomAccessPattern)==OuterRandomAccessPattern) ||\n              (!((DstEvaluatorType::Flags & RowMajorBit) != (SrcEvaluatorType::Flags & RowMajorBit)))) &&\n              \"the transpose operation is supposed to be handled in SparseMatrix::operator=\");\n\n    enum { Flip = (DstEvaluatorType::Flags & RowMajorBit) != (SrcEvaluatorType::Flags & RowMajorBit) };\n\n    \n    DstXprType temp(src.rows(), src.cols());\n\n    temp.reserve((std::max)(src.rows(),src.cols())*2);\n    for (Index j=0; j<outerEvaluationSize; ++j)\n    {\n      temp.startVec(j);\n      for (typename SrcEvaluatorType::InnerIterator it(srcEvaluator, j); it; ++it)\n      {\n        Scalar v = it.value();\n        temp.insertBackByOuterInner(Flip?it.index():j,Flip?j:it.index()) = v;\n      }\n    }\n    temp.finalize();\n\n    dst = temp.markAsRValue();\n  }\n}\n\n// Generic Sparse to Sparse assignment\ntemplate< typename DstXprType, typename SrcXprType, typename Functor>\nstruct Assignment<DstXprType, SrcXprType, Functor, Sparse2Sparse>\n{\n  static void run(DstXprType &dst, const SrcXprType &src, const internal::assign_op<typename DstXprType::Scalar,typename SrcXprType::Scalar> &/*func*/)\n  {\n    assign_sparse_to_sparse(dst.derived(), src.derived());\n  }\n};\n\n// Generic Sparse to Dense assignment\ntemplate< typename DstXprType, typename SrcXprType, typename Functor>\nstruct Assignment<DstXprType, SrcXprType, Functor, Sparse2Dense>\n{\n  static void run(DstXprType &dst, const SrcXprType &src, const Functor &func)\n  {\n    if(internal::is_same<Functor,internal::assign_op<typename DstXprType::Scalar,typename SrcXprType::Scalar> >::value)\n      dst.setZero();\n    \n    internal::evaluator<SrcXprType> srcEval(src);\n    Index dstRows = src.rows();\n    Index dstCols = src.cols();\n    if((dst.rows()!=dstRows) || (dst.cols()!=dstCols))\n      dst.resize(dstRows, dstCols);\n    internal::evaluator<DstXprType> dstEval(dst);\n    \n    const Index outerEvaluationSize = (internal::evaluator<SrcXprType>::Flags&RowMajorBit) ? src.rows() : src.cols();\n    for (Index j=0; j<outerEvaluationSize; ++j)\n      for (typename internal::evaluator<SrcXprType>::InnerIterator i(srcEval,j); i; ++i)\n        func.assignCoeff(dstEval.coeffRef(i.row(),i.col()), i.value());\n  }\n};\n\n// Specialization for \"dst = dec.solve(rhs)\"\n// NOTE we need to specialize it for Sparse2Sparse to avoid ambiguous specialization error\ntemplate<typename DstXprType, typename DecType, typename RhsType, typename Scalar>\nstruct Assignment<DstXprType, Solve<DecType,RhsType>, internal::assign_op<Scalar,Scalar>, Sparse2Sparse>\n{\n  typedef Solve<DecType,RhsType> SrcXprType;\n  static void run(DstXprType &dst, const SrcXprType &src, const internal::assign_op<Scalar,Scalar> &)\n  {\n    Index dstRows = src.rows();\n    Index dstCols = src.cols();\n    if((dst.rows()!=dstRows) || (dst.cols()!=dstCols))\n      dst.resize(dstRows, dstCols);\n\n    src.dec()._solve_impl(src.rhs(), dst);\n  }\n};\n\nstruct Diagonal2Sparse {};\n\ntemplate<> struct AssignmentKind<SparseShape,DiagonalShape> { typedef Diagonal2Sparse Kind; };\n\ntemplate< typename DstXprType, typename SrcXprType, typename Functor>\nstruct Assignment<DstXprType, SrcXprType, Functor, Diagonal2Sparse>\n{\n  typedef typename DstXprType::StorageIndex StorageIndex;\n  typedef typename DstXprType::Scalar Scalar;\n  typedef Array<StorageIndex,Dynamic,1> ArrayXI;\n  typedef Array<Scalar,Dynamic,1> ArrayXS;\n  template<int Options>\n  static void run(SparseMatrix<Scalar,Options,StorageIndex> &dst, const SrcXprType &src, const internal::assign_op<typename DstXprType::Scalar,typename SrcXprType::Scalar> &/*func*/)\n  {\n    Index dstRows = src.rows();\n    Index dstCols = src.cols();\n    if((dst.rows()!=dstRows) || (dst.cols()!=dstCols))\n      dst.resize(dstRows, dstCols);\n\n    Index size = src.diagonal().size();\n    dst.makeCompressed();\n    dst.resizeNonZeros(size);\n    Map<ArrayXI>(dst.innerIndexPtr(), size).setLinSpaced(0,StorageIndex(size)-1);\n    Map<ArrayXI>(dst.outerIndexPtr(), size+1).setLinSpaced(0,StorageIndex(size));\n    Map<ArrayXS>(dst.valuePtr(), size) = src.diagonal();\n  }\n  \n  template<typename DstDerived>\n  static void run(SparseMatrixBase<DstDerived> &dst, const SrcXprType &src, const internal::assign_op<typename DstXprType::Scalar,typename SrcXprType::Scalar> &/*func*/)\n  {\n    dst.diagonal() = src.diagonal();\n  }\n  \n  static void run(DstXprType &dst, const SrcXprType &src, const internal::add_assign_op<typename DstXprType::Scalar,typename SrcXprType::Scalar> &/*func*/)\n  { dst.diagonal() += src.diagonal(); }\n  \n  static void run(DstXprType &dst, const SrcXprType &src, const internal::sub_assign_op<typename DstXprType::Scalar,typename SrcXprType::Scalar> &/*func*/)\n  { dst.diagonal() -= src.diagonal(); }\n};\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_SPARSEASSIGN_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseCore/SparseBlock.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\r\n// for linear algebra.\r\n//\r\n// Copyright (C) 2008-2014 Gael Guennebaud <gael.guennebaud@inria.fr>\r\n//\r\n// This Source Code Form is subject to the terms of the Mozilla\r\n// Public License v. 2.0. If a copy of the MPL was not distributed\r\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\r\n\r\n#ifndef EIGEN_SPARSE_BLOCK_H\r\n#define EIGEN_SPARSE_BLOCK_H\r\n\r\nnamespace Eigen { \r\n\r\n// Subset of columns or rows\r\ntemplate<typename XprType, int BlockRows, int BlockCols>\r\nclass BlockImpl<XprType,BlockRows,BlockCols,true,Sparse>\r\n  : public SparseMatrixBase<Block<XprType,BlockRows,BlockCols,true> >\r\n{\r\n    typedef typename internal::remove_all<typename XprType::Nested>::type _MatrixTypeNested;\r\n    typedef Block<XprType, BlockRows, BlockCols, true> BlockType;\r\npublic:\r\n    enum { IsRowMajor = internal::traits<BlockType>::IsRowMajor };\r\nprotected:\r\n    enum { OuterSize = IsRowMajor ? BlockRows : BlockCols };\r\n    typedef SparseMatrixBase<BlockType> Base;\r\n    using Base::convert_index;\r\npublic:\r\n    EIGEN_SPARSE_PUBLIC_INTERFACE(BlockType)\r\n\r\n    inline BlockImpl(XprType& xpr, Index i)\r\n      : m_matrix(xpr), m_outerStart(convert_index(i)), m_outerSize(OuterSize)\r\n    {}\r\n\r\n    inline BlockImpl(XprType& xpr, Index startRow, Index startCol, Index blockRows, Index blockCols)\r\n      : m_matrix(xpr), m_outerStart(convert_index(IsRowMajor ? startRow : startCol)), m_outerSize(convert_index(IsRowMajor ? blockRows : blockCols))\r\n    {}\r\n\r\n    EIGEN_STRONG_INLINE Index rows() const { return IsRowMajor ? m_outerSize.value() : m_matrix.rows(); }\r\n    EIGEN_STRONG_INLINE Index cols() const { return IsRowMajor ? m_matrix.cols() : m_outerSize.value(); }\r\n    \r\n    Index nonZeros() const\r\n    {\r\n      typedef internal::evaluator<XprType> EvaluatorType;\r\n      EvaluatorType matEval(m_matrix);\r\n      Index nnz = 0;\r\n      Index end = m_outerStart + m_outerSize.value();\r\n      for(Index j=m_outerStart; j<end; ++j)\r\n        for(typename EvaluatorType::InnerIterator it(matEval, j); it; ++it)\r\n          ++nnz;\r\n      return nnz;\r\n    }\r\n    \r\n    inline const Scalar coeff(Index row, Index col) const\r\n    {\r\n      return m_matrix.coeff(row + (IsRowMajor ? m_outerStart : 0), col + (IsRowMajor ? 0 :  m_outerStart));\r\n    }\r\n    \r\n    inline const Scalar coeff(Index index) const\r\n    {\r\n      return m_matrix.coeff(IsRowMajor ? m_outerStart : index, IsRowMajor ? index :  m_outerStart);\r\n    }\r\n    \r\n    inline const XprType& nestedExpression() const { return m_matrix; }\r\n    inline XprType& nestedExpression() { return m_matrix; }\r\n    Index startRow() const { return IsRowMajor ? m_outerStart : 0; }\r\n    Index startCol() const { return IsRowMajor ? 0 : m_outerStart; }\r\n    Index blockRows() const { return IsRowMajor ? m_outerSize.value() : m_matrix.rows(); }\r\n    Index blockCols() const { return IsRowMajor ? m_matrix.cols() : m_outerSize.value(); }\r\n\r\n  protected:\r\n\r\n    typename internal::ref_selector<XprType>::non_const_type m_matrix;\r\n    Index m_outerStart;\r\n    const internal::variable_if_dynamic<Index, OuterSize> m_outerSize;\r\n  \r\n  protected:\r\n    // Disable assignment with clear error message.\r\n    // Note that simply removing operator= yields compilation errors with ICC+MSVC\r\n    template<typename T>\r\n    BlockImpl& operator=(const T&)\r\n    {\r\n      EIGEN_STATIC_ASSERT(sizeof(T)==0, THIS_SPARSE_BLOCK_SUBEXPRESSION_IS_READ_ONLY);\r\n      return *this;\r\n    }\r\n};\r\n\r\n\r\n/***************************************************************************\r\n* specialization for SparseMatrix\r\n***************************************************************************/\r\n\r\nnamespace internal {\r\n\r\ntemplate<typename SparseMatrixType, int BlockRows, int BlockCols>\r\nclass sparse_matrix_block_impl\r\n  : public SparseCompressedBase<Block<SparseMatrixType,BlockRows,BlockCols,true> >\r\n{\r\n    typedef typename internal::remove_all<typename SparseMatrixType::Nested>::type _MatrixTypeNested;\r\n    typedef Block<SparseMatrixType, BlockRows, BlockCols, true> BlockType;\r\n    typedef SparseCompressedBase<Block<SparseMatrixType,BlockRows,BlockCols,true> > Base;\r\n    using Base::convert_index;\r\npublic:\r\n    enum { IsRowMajor = internal::traits<BlockType>::IsRowMajor };\r\n    EIGEN_SPARSE_PUBLIC_INTERFACE(BlockType)\r\nprotected:\r\n    typedef typename Base::IndexVector IndexVector;\r\n    enum { OuterSize = IsRowMajor ? BlockRows : BlockCols };\r\npublic:\r\n\r\n    inline sparse_matrix_block_impl(SparseMatrixType& xpr, Index i)\r\n      : m_matrix(xpr), m_outerStart(convert_index(i)), m_outerSize(OuterSize)\r\n    {}\r\n\r\n    inline sparse_matrix_block_impl(SparseMatrixType& xpr, Index startRow, Index startCol, Index blockRows, Index blockCols)\r\n      : m_matrix(xpr), m_outerStart(convert_index(IsRowMajor ? startRow : startCol)), m_outerSize(convert_index(IsRowMajor ? blockRows : blockCols))\r\n    {}\r\n\r\n    template<typename OtherDerived>\r\n    inline BlockType& operator=(const SparseMatrixBase<OtherDerived>& other)\r\n    {\r\n      typedef typename internal::remove_all<typename SparseMatrixType::Nested>::type _NestedMatrixType;\r\n      _NestedMatrixType& matrix = m_matrix;\r\n      // This assignment is slow if this vector set is not empty\r\n      // and/or it is not at the end of the nonzeros of the underlying matrix.\r\n\r\n      // 1 - eval to a temporary to avoid transposition and/or aliasing issues\r\n      Ref<const SparseMatrix<Scalar, IsRowMajor ? RowMajor : ColMajor, StorageIndex> > tmp(other.derived());\r\n      eigen_internal_assert(tmp.outerSize()==m_outerSize.value());\r\n\r\n      // 2 - let's check whether there is enough allocated memory\r\n      Index nnz           = tmp.nonZeros();\r\n      Index start         = m_outerStart==0 ? 0 : m_matrix.outerIndexPtr()[m_outerStart]; // starting position of the current block\r\n      Index end           = m_matrix.outerIndexPtr()[m_outerStart+m_outerSize.value()]; // ending position of the current block\r\n      Index block_size    = end - start;                                                // available room in the current block\r\n      Index tail_size     = m_matrix.outerIndexPtr()[m_matrix.outerSize()] - end;\r\n      \r\n      Index free_size     = m_matrix.isCompressed()\r\n                          ? Index(matrix.data().allocatedSize()) + block_size\r\n                          : block_size;\r\n\r\n      Index tmp_start = tmp.outerIndexPtr()[0];\r\n\r\n      bool update_trailing_pointers = false;\r\n      if(nnz>free_size) \r\n      {\r\n        // realloc manually to reduce copies\r\n        typename SparseMatrixType::Storage newdata(m_matrix.data().allocatedSize() - block_size + nnz);\r\n\r\n        internal::smart_copy(m_matrix.valuePtr(),       m_matrix.valuePtr() + start,      newdata.valuePtr());\r\n        internal::smart_copy(m_matrix.innerIndexPtr(),  m_matrix.innerIndexPtr() + start, newdata.indexPtr());\r\n\r\n        internal::smart_copy(tmp.valuePtr() + tmp_start,      tmp.valuePtr() + tmp_start + nnz,       newdata.valuePtr() + start);\r\n        internal::smart_copy(tmp.innerIndexPtr() + tmp_start, tmp.innerIndexPtr() + tmp_start + nnz,  newdata.indexPtr() + start);\r\n\r\n        internal::smart_copy(matrix.valuePtr()+end,       matrix.valuePtr()+end + tail_size,      newdata.valuePtr()+start+nnz);\r\n        internal::smart_copy(matrix.innerIndexPtr()+end,  matrix.innerIndexPtr()+end + tail_size, newdata.indexPtr()+start+nnz);\r\n        \r\n        newdata.resize(m_matrix.outerIndexPtr()[m_matrix.outerSize()] - block_size + nnz);\r\n\r\n        matrix.data().swap(newdata);\r\n\r\n        update_trailing_pointers = true;\r\n      }\r\n      else\r\n      {\r\n        if(m_matrix.isCompressed())\r\n        {\r\n          // no need to realloc, simply copy the tail at its respective position and insert tmp\r\n          matrix.data().resize(start + nnz + tail_size);\r\n\r\n          internal::smart_memmove(matrix.valuePtr()+end,      matrix.valuePtr() + end+tail_size,      matrix.valuePtr() + start+nnz);\r\n          internal::smart_memmove(matrix.innerIndexPtr()+end, matrix.innerIndexPtr() + end+tail_size, matrix.innerIndexPtr() + start+nnz);\r\n\r\n          update_trailing_pointers = true;\r\n        }\r\n\r\n        internal::smart_copy(tmp.valuePtr() + tmp_start,      tmp.valuePtr() + tmp_start + nnz,       matrix.valuePtr() + start);\r\n        internal::smart_copy(tmp.innerIndexPtr() + tmp_start, tmp.innerIndexPtr() + tmp_start + nnz,  matrix.innerIndexPtr() + start);\r\n      }\r\n\r\n      // update outer index pointers and innerNonZeros\r\n      if(IsVectorAtCompileTime)\r\n      {\r\n        if(!m_matrix.isCompressed())\r\n          matrix.innerNonZeroPtr()[m_outerStart] = StorageIndex(nnz);\r\n        matrix.outerIndexPtr()[m_outerStart] = StorageIndex(start);\r\n      }\r\n      else\r\n      {\r\n        StorageIndex p = StorageIndex(start);\r\n        for(Index k=0; k<m_outerSize.value(); ++k)\r\n        {\r\n          StorageIndex nnz_k = internal::convert_index<StorageIndex>(tmp.innerVector(k).nonZeros());\r\n          if(!m_matrix.isCompressed())\r\n            matrix.innerNonZeroPtr()[m_outerStart+k] = nnz_k;\r\n          matrix.outerIndexPtr()[m_outerStart+k] = p;\r\n          p += nnz_k;\r\n        }\r\n      }\r\n\r\n      if(update_trailing_pointers)\r\n      {\r\n        StorageIndex offset = internal::convert_index<StorageIndex>(nnz - block_size);\r\n        for(Index k = m_outerStart + m_outerSize.value(); k<=matrix.outerSize(); ++k)\r\n        {\r\n          matrix.outerIndexPtr()[k] += offset;\r\n        }\r\n      }\r\n\r\n      return derived();\r\n    }\r\n\r\n    inline BlockType& operator=(const BlockType& other)\r\n    {\r\n      return operator=<BlockType>(other);\r\n    }\r\n\r\n    inline const Scalar* valuePtr() const\r\n    { return m_matrix.valuePtr(); }\r\n    inline Scalar* valuePtr()\r\n    { return m_matrix.valuePtr(); }\r\n\r\n    inline const StorageIndex* innerIndexPtr() const\r\n    { return m_matrix.innerIndexPtr(); }\r\n    inline StorageIndex* innerIndexPtr()\r\n    { return m_matrix.innerIndexPtr(); }\r\n\r\n    inline const StorageIndex* outerIndexPtr() const\r\n    { return m_matrix.outerIndexPtr() + m_outerStart; }\r\n    inline StorageIndex* outerIndexPtr()\r\n    { return m_matrix.outerIndexPtr() + m_outerStart; }\r\n    \r\n    inline const StorageIndex* innerNonZeroPtr() const\r\n    { return isCompressed() ? 0 : (m_matrix.innerNonZeroPtr()+m_outerStart); }\r\n    inline StorageIndex* innerNonZeroPtr()\r\n    { return isCompressed() ? 0 : (m_matrix.innerNonZeroPtr()+m_outerStart); }\r\n    \r\n    bool isCompressed() const { return m_matrix.innerNonZeroPtr()==0; }\r\n    \r\n    inline Scalar& coeffRef(Index row, Index col)\r\n    {\r\n      return m_matrix.coeffRef(row + (IsRowMajor ? m_outerStart : 0), col + (IsRowMajor ? 0 :  m_outerStart));\r\n    }\r\n    \r\n    inline const Scalar coeff(Index row, Index col) const\r\n    {\r\n      return m_matrix.coeff(row + (IsRowMajor ? m_outerStart : 0), col + (IsRowMajor ? 0 :  m_outerStart));\r\n    }\r\n    \r\n    inline const Scalar coeff(Index index) const\r\n    {\r\n      return m_matrix.coeff(IsRowMajor ? m_outerStart : index, IsRowMajor ? index :  m_outerStart);\r\n    }\r\n\r\n    const Scalar& lastCoeff() const\r\n    {\r\n      EIGEN_STATIC_ASSERT_VECTOR_ONLY(sparse_matrix_block_impl);\r\n      eigen_assert(Base::nonZeros()>0);\r\n      if(m_matrix.isCompressed())\r\n        return m_matrix.valuePtr()[m_matrix.outerIndexPtr()[m_outerStart+1]-1];\r\n      else\r\n        return m_matrix.valuePtr()[m_matrix.outerIndexPtr()[m_outerStart]+m_matrix.innerNonZeroPtr()[m_outerStart]-1];\r\n    }\r\n\r\n    EIGEN_STRONG_INLINE Index rows() const { return IsRowMajor ? m_outerSize.value() : m_matrix.rows(); }\r\n    EIGEN_STRONG_INLINE Index cols() const { return IsRowMajor ? m_matrix.cols() : m_outerSize.value(); }\r\n    \r\n    inline const SparseMatrixType& nestedExpression() const { return m_matrix; }\r\n    inline SparseMatrixType& nestedExpression() { return m_matrix; }\r\n    Index startRow() const { return IsRowMajor ? m_outerStart : 0; }\r\n    Index startCol() const { return IsRowMajor ? 0 : m_outerStart; }\r\n    Index blockRows() const { return IsRowMajor ? m_outerSize.value() : m_matrix.rows(); }\r\n    Index blockCols() const { return IsRowMajor ? m_matrix.cols() : m_outerSize.value(); }\r\n\r\n  protected:\r\n\r\n    typename internal::ref_selector<SparseMatrixType>::non_const_type m_matrix;\r\n    Index m_outerStart;\r\n    const internal::variable_if_dynamic<Index, OuterSize> m_outerSize;\r\n\r\n};\r\n\r\n} // namespace internal\r\n\r\ntemplate<typename _Scalar, int _Options, typename _StorageIndex, int BlockRows, int BlockCols>\r\nclass BlockImpl<SparseMatrix<_Scalar, _Options, _StorageIndex>,BlockRows,BlockCols,true,Sparse>\r\n  : public internal::sparse_matrix_block_impl<SparseMatrix<_Scalar, _Options, _StorageIndex>,BlockRows,BlockCols>\r\n{\r\npublic:\r\n  typedef _StorageIndex StorageIndex;\r\n  typedef SparseMatrix<_Scalar, _Options, _StorageIndex> SparseMatrixType;\r\n  typedef internal::sparse_matrix_block_impl<SparseMatrixType,BlockRows,BlockCols> Base;\r\n  inline BlockImpl(SparseMatrixType& xpr, Index i)\r\n    : Base(xpr, i)\r\n  {}\r\n\r\n  inline BlockImpl(SparseMatrixType& xpr, Index startRow, Index startCol, Index blockRows, Index blockCols)\r\n    : Base(xpr, startRow, startCol, blockRows, blockCols)\r\n  {}\r\n  \r\n  using Base::operator=;\r\n};\r\n\r\ntemplate<typename _Scalar, int _Options, typename _StorageIndex, int BlockRows, int BlockCols>\r\nclass BlockImpl<const SparseMatrix<_Scalar, _Options, _StorageIndex>,BlockRows,BlockCols,true,Sparse>\r\n  : public internal::sparse_matrix_block_impl<const SparseMatrix<_Scalar, _Options, _StorageIndex>,BlockRows,BlockCols>\r\n{\r\npublic:\r\n  typedef _StorageIndex StorageIndex;\r\n  typedef const SparseMatrix<_Scalar, _Options, _StorageIndex> SparseMatrixType;\r\n  typedef internal::sparse_matrix_block_impl<SparseMatrixType,BlockRows,BlockCols> Base;\r\n  inline BlockImpl(SparseMatrixType& xpr, Index i)\r\n    : Base(xpr, i)\r\n  {}\r\n\r\n  inline BlockImpl(SparseMatrixType& xpr, Index startRow, Index startCol, Index blockRows, Index blockCols)\r\n    : Base(xpr, startRow, startCol, blockRows, blockCols)\r\n  {}\r\n  \r\n  using Base::operator=;\r\nprivate:\r\n  template<typename Derived> BlockImpl(const SparseMatrixBase<Derived>& xpr, Index i);\r\n  template<typename Derived> BlockImpl(const SparseMatrixBase<Derived>& xpr);\r\n};\r\n\r\n//----------\r\n\r\n/** \\returns the \\a outer -th column (resp. row) of the matrix \\c *this if \\c *this\r\n  * is col-major (resp. row-major).\r\n  */\r\ntemplate<typename Derived>\r\ntypename SparseMatrixBase<Derived>::InnerVectorReturnType SparseMatrixBase<Derived>::innerVector(Index outer)\r\n{ return InnerVectorReturnType(derived(), outer); }\r\n\r\n/** \\returns the \\a outer -th column (resp. row) of the matrix \\c *this if \\c *this\r\n  * is col-major (resp. row-major). Read-only.\r\n  */\r\ntemplate<typename Derived>\r\nconst typename SparseMatrixBase<Derived>::ConstInnerVectorReturnType SparseMatrixBase<Derived>::innerVector(Index outer) const\r\n{ return ConstInnerVectorReturnType(derived(), outer); }\r\n\r\n/** \\returns the \\a outer -th column (resp. row) of the matrix \\c *this if \\c *this\r\n  * is col-major (resp. row-major).\r\n  */\r\ntemplate<typename Derived>\r\ntypename SparseMatrixBase<Derived>::InnerVectorsReturnType\r\nSparseMatrixBase<Derived>::innerVectors(Index outerStart, Index outerSize)\r\n{\r\n  return Block<Derived,Dynamic,Dynamic,true>(derived(),\r\n                                             IsRowMajor ? outerStart : 0, IsRowMajor ? 0 : outerStart,\r\n                                             IsRowMajor ? outerSize : rows(), IsRowMajor ? cols() : outerSize);\r\n  \r\n}\r\n\r\n/** \\returns the \\a outer -th column (resp. row) of the matrix \\c *this if \\c *this\r\n  * is col-major (resp. row-major). Read-only.\r\n  */\r\ntemplate<typename Derived>\r\nconst typename SparseMatrixBase<Derived>::ConstInnerVectorsReturnType\r\nSparseMatrixBase<Derived>::innerVectors(Index outerStart, Index outerSize) const\r\n{\r\n  return Block<const Derived,Dynamic,Dynamic,true>(derived(),\r\n                                                  IsRowMajor ? outerStart : 0, IsRowMajor ? 0 : outerStart,\r\n                                                  IsRowMajor ? outerSize : rows(), IsRowMajor ? cols() : outerSize);\r\n  \r\n}\r\n\r\n/** Generic implementation of sparse Block expression.\r\n  * Real-only. \r\n  */\r\ntemplate<typename XprType, int BlockRows, int BlockCols, bool InnerPanel>\r\nclass BlockImpl<XprType,BlockRows,BlockCols,InnerPanel,Sparse>\r\n  : public SparseMatrixBase<Block<XprType,BlockRows,BlockCols,InnerPanel> >, internal::no_assignment_operator\r\n{\r\n    typedef Block<XprType, BlockRows, BlockCols, InnerPanel> BlockType;\r\n    typedef SparseMatrixBase<BlockType> Base;\r\n    using Base::convert_index;\r\npublic:\r\n    enum { IsRowMajor = internal::traits<BlockType>::IsRowMajor };\r\n    EIGEN_SPARSE_PUBLIC_INTERFACE(BlockType)\r\n    \r\n    typedef typename internal::remove_all<typename XprType::Nested>::type _MatrixTypeNested;\r\n\r\n    /** Column or Row constructor\r\n      */\r\n    inline BlockImpl(XprType& xpr, Index i)\r\n      : m_matrix(xpr),\r\n        m_startRow( (BlockRows==1) && (BlockCols==XprType::ColsAtCompileTime) ? convert_index(i) : 0),\r\n        m_startCol( (BlockRows==XprType::RowsAtCompileTime) && (BlockCols==1) ? convert_index(i) : 0),\r\n        m_blockRows(BlockRows==1 ? 1 : xpr.rows()),\r\n        m_blockCols(BlockCols==1 ? 1 : xpr.cols())\r\n    {}\r\n\r\n    /** Dynamic-size constructor\r\n      */\r\n    inline BlockImpl(XprType& xpr, Index startRow, Index startCol, Index blockRows, Index blockCols)\r\n      : m_matrix(xpr), m_startRow(convert_index(startRow)), m_startCol(convert_index(startCol)), m_blockRows(convert_index(blockRows)), m_blockCols(convert_index(blockCols))\r\n    {}\r\n\r\n    inline Index rows() const { return m_blockRows.value(); }\r\n    inline Index cols() const { return m_blockCols.value(); }\r\n\r\n    inline Scalar& coeffRef(Index row, Index col)\r\n    {\r\n      return m_matrix.coeffRef(row + m_startRow.value(), col + m_startCol.value());\r\n    }\r\n\r\n    inline const Scalar coeff(Index row, Index col) const\r\n    {\r\n      return m_matrix.coeff(row + m_startRow.value(), col + m_startCol.value());\r\n    }\r\n\r\n    inline Scalar& coeffRef(Index index)\r\n    {\r\n      return m_matrix.coeffRef(m_startRow.value() + (RowsAtCompileTime == 1 ? 0 : index),\r\n                               m_startCol.value() + (RowsAtCompileTime == 1 ? index : 0));\r\n    }\r\n\r\n    inline const Scalar coeff(Index index) const\r\n    {\r\n      return m_matrix.coeff(m_startRow.value() + (RowsAtCompileTime == 1 ? 0 : index),\r\n                            m_startCol.value() + (RowsAtCompileTime == 1 ? index : 0));\r\n    }\r\n    \r\n    inline const XprType& nestedExpression() const { return m_matrix; }\r\n    inline XprType& nestedExpression() { return m_matrix; }\r\n    Index startRow() const { return m_startRow.value(); }\r\n    Index startCol() const { return m_startCol.value(); }\r\n    Index blockRows() const { return m_blockRows.value(); }\r\n    Index blockCols() const { return m_blockCols.value(); }\r\n    \r\n  protected:\r\n//     friend class internal::GenericSparseBlockInnerIteratorImpl<XprType,BlockRows,BlockCols,InnerPanel>;\r\n    friend struct internal::unary_evaluator<Block<XprType,BlockRows,BlockCols,InnerPanel>, internal::IteratorBased, Scalar >;\r\n    \r\n    Index nonZeros() const { return Dynamic; }\r\n\r\n    typename internal::ref_selector<XprType>::non_const_type m_matrix;\r\n    const internal::variable_if_dynamic<Index, XprType::RowsAtCompileTime == 1 ? 0 : Dynamic> m_startRow;\r\n    const internal::variable_if_dynamic<Index, XprType::ColsAtCompileTime == 1 ? 0 : Dynamic> m_startCol;\r\n    const internal::variable_if_dynamic<Index, RowsAtCompileTime> m_blockRows;\r\n    const internal::variable_if_dynamic<Index, ColsAtCompileTime> m_blockCols;\r\n\r\n  protected:\r\n    // Disable assignment with clear error message.\r\n    // Note that simply removing operator= yields compilation errors with ICC+MSVC\r\n    template<typename T>\r\n    BlockImpl& operator=(const T&)\r\n    {\r\n      EIGEN_STATIC_ASSERT(sizeof(T)==0, THIS_SPARSE_BLOCK_SUBEXPRESSION_IS_READ_ONLY);\r\n      return *this;\r\n    }\r\n\r\n};\r\n\r\nnamespace internal {\r\n\r\ntemplate<typename ArgType, int BlockRows, int BlockCols, bool InnerPanel>\r\nstruct unary_evaluator<Block<ArgType,BlockRows,BlockCols,InnerPanel>, IteratorBased >\r\n : public evaluator_base<Block<ArgType,BlockRows,BlockCols,InnerPanel> >\r\n{\r\n    class InnerVectorInnerIterator;\r\n    class OuterVectorInnerIterator;\r\n  public:\r\n    typedef Block<ArgType,BlockRows,BlockCols,InnerPanel> XprType;\r\n    typedef typename XprType::StorageIndex StorageIndex;\r\n    typedef typename XprType::Scalar Scalar;\r\n    \r\n    enum {\r\n      IsRowMajor = XprType::IsRowMajor,\r\n      \r\n      OuterVector =  (BlockCols==1 && ArgType::IsRowMajor)\r\n                    | // FIXME | instead of || to please GCC 4.4.0 stupid warning \"suggest parentheses around &&\".\r\n                      // revert to || as soon as not needed anymore. \r\n                     (BlockRows==1 && !ArgType::IsRowMajor),\r\n      \r\n      CoeffReadCost = evaluator<ArgType>::CoeffReadCost,\r\n      Flags = XprType::Flags\r\n    };\r\n    \r\n    typedef typename internal::conditional<OuterVector,OuterVectorInnerIterator,InnerVectorInnerIterator>::type InnerIterator;\r\n    \r\n    explicit unary_evaluator(const XprType& op)\r\n      : m_argImpl(op.nestedExpression()), m_block(op)\r\n    {}\r\n    \r\n    inline Index nonZerosEstimate() const {\r\n      Index nnz = m_block.nonZeros();\r\n      if(nnz<0)\r\n        return m_argImpl.nonZerosEstimate() * m_block.size() / m_block.nestedExpression().size();\r\n      return nnz;\r\n    }\r\n\r\n  protected:\r\n    typedef typename evaluator<ArgType>::InnerIterator EvalIterator;\r\n    \r\n    evaluator<ArgType> m_argImpl;\r\n    const XprType &m_block;\r\n};\r\n\r\ntemplate<typename ArgType, int BlockRows, int BlockCols, bool InnerPanel>\r\nclass unary_evaluator<Block<ArgType,BlockRows,BlockCols,InnerPanel>, IteratorBased>::InnerVectorInnerIterator\r\n : public EvalIterator\r\n{\r\n  enum { IsRowMajor = unary_evaluator::IsRowMajor };\r\n  const XprType& m_block;\r\n  Index m_end;\r\npublic:\r\n  \r\n  EIGEN_STRONG_INLINE InnerVectorInnerIterator(const unary_evaluator& aEval, Index outer)\r\n    : EvalIterator(aEval.m_argImpl, outer + (IsRowMajor ? aEval.m_block.startRow() : aEval.m_block.startCol())),\r\n      m_block(aEval.m_block),\r\n      m_end(IsRowMajor ? aEval.m_block.startCol()+aEval.m_block.blockCols() : aEval.m_block.startRow()+aEval.m_block.blockRows())\r\n  {\r\n    while( (EvalIterator::operator bool()) && (EvalIterator::index() < (IsRowMajor ? m_block.startCol() : m_block.startRow())) )\r\n      EvalIterator::operator++();\r\n  }\r\n  \r\n  inline StorageIndex index() const { return EvalIterator::index() - convert_index<StorageIndex>(IsRowMajor ? m_block.startCol() : m_block.startRow()); }\r\n  inline Index outer()  const { return EvalIterator::outer() - (IsRowMajor ? m_block.startRow() : m_block.startCol()); }\r\n  inline Index row()    const { return EvalIterator::row()   - m_block.startRow(); }\r\n  inline Index col()    const { return EvalIterator::col()   - m_block.startCol(); }\r\n  \r\n  inline operator bool() const { return EvalIterator::operator bool() && EvalIterator::index() < m_end; }\r\n};\r\n\r\ntemplate<typename ArgType, int BlockRows, int BlockCols, bool InnerPanel>\r\nclass unary_evaluator<Block<ArgType,BlockRows,BlockCols,InnerPanel>, IteratorBased>::OuterVectorInnerIterator\r\n{\r\n  enum { IsRowMajor = unary_evaluator::IsRowMajor };\r\n  const unary_evaluator& m_eval;\r\n  Index m_outerPos;\r\n  Index m_innerIndex;\r\n  Scalar m_value;\r\n  Index m_end;\r\npublic:\r\n\r\n  EIGEN_STRONG_INLINE OuterVectorInnerIterator(const unary_evaluator& aEval, Index outer)\r\n    : m_eval(aEval),\r\n      m_outerPos( (IsRowMajor ? aEval.m_block.startCol() : aEval.m_block.startRow()) - 1), // -1 so that operator++ finds the first non-zero entry\r\n      m_innerIndex(IsRowMajor ? aEval.m_block.startRow() : aEval.m_block.startCol()),\r\n      m_value(0),\r\n      m_end(IsRowMajor ? aEval.m_block.startCol()+aEval.m_block.blockCols() : aEval.m_block.startRow()+aEval.m_block.blockRows())\r\n  {\r\n    EIGEN_UNUSED_VARIABLE(outer);\r\n    eigen_assert(outer==0);\r\n    \r\n    ++(*this);\r\n  }\r\n  \r\n  inline StorageIndex index() const { return convert_index<StorageIndex>(m_outerPos - (IsRowMajor ? m_eval.m_block.startCol() : m_eval.m_block.startRow())); }\r\n  inline Index outer()  const { return 0; }\r\n  inline Index row()    const { return IsRowMajor ? 0 : index(); }\r\n  inline Index col()    const { return IsRowMajor ? index() : 0; }\r\n  \r\n  inline Scalar value() const { return m_value; }\r\n  \r\n  inline OuterVectorInnerIterator& operator++()\r\n  {\r\n    // search next non-zero entry\r\n    while(++m_outerPos<m_end)\r\n    {\r\n      EvalIterator it(m_eval.m_argImpl, m_outerPos);\r\n      // search for the key m_innerIndex in the current outer-vector\r\n      while(it && it.index() < m_innerIndex) ++it;\r\n      if(it && it.index()==m_innerIndex)\r\n      {\r\n        m_value = it.value();\r\n        break;\r\n      }\r\n    }\r\n    return *this;\r\n  }\r\n  \r\n  inline operator bool() const { return m_outerPos < m_end; }\r\n};\r\n\r\ntemplate<typename _Scalar, int _Options, typename _StorageIndex, int BlockRows, int BlockCols>\r\nstruct unary_evaluator<Block<SparseMatrix<_Scalar, _Options, _StorageIndex>,BlockRows,BlockCols,true>, IteratorBased>\r\n  : evaluator<SparseCompressedBase<Block<SparseMatrix<_Scalar, _Options, _StorageIndex>,BlockRows,BlockCols,true> > >\r\n{\r\n  typedef Block<SparseMatrix<_Scalar, _Options, _StorageIndex>,BlockRows,BlockCols,true> XprType;\r\n  typedef evaluator<SparseCompressedBase<XprType> > Base;\r\n  explicit unary_evaluator(const XprType &xpr) : Base(xpr) {}\r\n};\r\n\r\ntemplate<typename _Scalar, int _Options, typename _StorageIndex, int BlockRows, int BlockCols>\r\nstruct unary_evaluator<Block<const SparseMatrix<_Scalar, _Options, _StorageIndex>,BlockRows,BlockCols,true>, IteratorBased>\r\n  : evaluator<SparseCompressedBase<Block<const SparseMatrix<_Scalar, _Options, _StorageIndex>,BlockRows,BlockCols,true> > >\r\n{\r\n  typedef Block<const SparseMatrix<_Scalar, _Options, _StorageIndex>,BlockRows,BlockCols,true> XprType;\r\n  typedef evaluator<SparseCompressedBase<XprType> > Base;\r\n  explicit unary_evaluator(const XprType &xpr) : Base(xpr) {}\r\n};\r\n\r\n} // end namespace internal\r\n\r\n\r\n} // end namespace Eigen\r\n\r\n#endif // EIGEN_SPARSE_BLOCK_H\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseCore/SparseColEtree.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2012 Désiré Nuentsa-Wakam <desire.nuentsa_wakam@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n\n/* \n \n * NOTE: This file is the modified version of sp_coletree.c file in SuperLU \n \n * -- SuperLU routine (version 3.1) --\n * Univ. of California Berkeley, Xerox Palo Alto Research Center,\n * and Lawrence Berkeley National Lab.\n * August 1, 2008\n *\n * Copyright (c) 1994 by Xerox Corporation.  All rights reserved.\n *\n * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY\n * EXPRESSED OR IMPLIED.  ANY USE IS AT YOUR OWN RISK.\n *\n * Permission is hereby granted to use or copy this program for any\n * purpose, provided the above notices are retained on all copies.\n * Permission to modify the code and to distribute modified code is\n * granted, provided the above notices are retained, and a notice that\n * the code was modified is included with the above copyright notice.\n */\n#ifndef SPARSE_COLETREE_H\n#define SPARSE_COLETREE_H\n\nnamespace Eigen {\n\nnamespace internal {\n\n/** Find the root of the tree/set containing the vertex i : Use Path halving */ \ntemplate<typename Index, typename IndexVector>\nIndex etree_find (Index i, IndexVector& pp)\n{\n  Index p = pp(i); // Parent \n  Index gp = pp(p); // Grand parent \n  while (gp != p) \n  {\n    pp(i) = gp; // Parent pointer on find path is changed to former grand parent\n    i = gp; \n    p = pp(i);\n    gp = pp(p);\n  }\n  return p; \n}\n\n/** Compute the column elimination tree of a sparse matrix\n  * \\param mat The matrix in column-major format. \n  * \\param parent The elimination tree\n  * \\param firstRowElt The column index of the first element in each row\n  * \\param perm The permutation to apply to the column of \\b mat\n  */\ntemplate <typename MatrixType, typename IndexVector>\nint coletree(const MatrixType& mat, IndexVector& parent, IndexVector& firstRowElt, typename MatrixType::StorageIndex *perm=0)\n{\n  typedef typename MatrixType::StorageIndex StorageIndex;\n  StorageIndex nc = convert_index<StorageIndex>(mat.cols()); // Number of columns\n  StorageIndex m = convert_index<StorageIndex>(mat.rows());\n  StorageIndex diagSize = (std::min)(nc,m);\n  IndexVector root(nc); // root of subtree of etree \n  root.setZero();\n  IndexVector pp(nc); // disjoint sets \n  pp.setZero(); // Initialize disjoint sets \n  parent.resize(mat.cols());\n  //Compute first nonzero column in each row \n  firstRowElt.resize(m);\n  firstRowElt.setConstant(nc);\n  firstRowElt.segment(0, diagSize).setLinSpaced(diagSize, 0, diagSize-1);\n  bool found_diag;\n  for (StorageIndex col = 0; col < nc; col++)\n  {\n    StorageIndex pcol = col;\n    if(perm) pcol  = perm[col];\n    for (typename MatrixType::InnerIterator it(mat, pcol); it; ++it)\n    { \n      Index row = it.row();\n      firstRowElt(row) = (std::min)(firstRowElt(row), col);\n    }\n  }\n  /* Compute etree by Liu's algorithm for symmetric matrices,\n          except use (firstRowElt[r],c) in place of an edge (r,c) of A.\n    Thus each row clique in A'*A is replaced by a star\n    centered at its first vertex, which has the same fill. */\n  StorageIndex rset, cset, rroot;\n  for (StorageIndex col = 0; col < nc; col++) \n  {\n    found_diag = col>=m;\n    pp(col) = col; \n    cset = col; \n    root(cset) = col; \n    parent(col) = nc; \n    /* The diagonal element is treated here even if it does not exist in the matrix\n     * hence the loop is executed once more */ \n    StorageIndex pcol = col;\n    if(perm) pcol  = perm[col];\n    for (typename MatrixType::InnerIterator it(mat, pcol); it||!found_diag; ++it)\n    { //  A sequence of interleaved find and union is performed \n      Index i = col;\n      if(it) i = it.index();\n      if (i == col) found_diag = true;\n      \n      StorageIndex row = firstRowElt(i);\n      if (row >= col) continue; \n      rset = internal::etree_find(row, pp); // Find the name of the set containing row\n      rroot = root(rset);\n      if (rroot != col) \n      {\n        parent(rroot) = col; \n        pp(cset) = rset; \n        cset = rset; \n        root(cset) = col; \n      }\n    }\n  }\n  return 0;  \n}\n\n/** \n  * Depth-first search from vertex n.  No recursion.\n  * This routine was contributed by Cédric Doucet, CEDRAT Group, Meylan, France.\n*/\ntemplate <typename IndexVector>\nvoid nr_etdfs (typename IndexVector::Scalar n, IndexVector& parent, IndexVector& first_kid, IndexVector& next_kid, IndexVector& post, typename IndexVector::Scalar postnum)\n{\n  typedef typename IndexVector::Scalar StorageIndex;\n  StorageIndex current = n, first, next;\n  while (postnum != n) \n  {\n    // No kid for the current node\n    first = first_kid(current);\n    \n    // no kid for the current node\n    if (first == -1) \n    {\n      // Numbering this node because it has no kid \n      post(current) = postnum++;\n      \n      // looking for the next kid \n      next = next_kid(current); \n      while (next == -1) \n      {\n        // No more kids : back to the parent node\n        current = parent(current); \n        // numbering the parent node \n        post(current) = postnum++;\n        \n        // Get the next kid \n        next = next_kid(current); \n      }\n      // stopping criterion \n      if (postnum == n+1) return; \n      \n      // Updating current node \n      current = next; \n    }\n    else \n    {\n      current = first; \n    }\n  }\n}\n\n\n/**\n  * \\brief Post order a tree \n  * \\param n the number of nodes\n  * \\param parent Input tree\n  * \\param post postordered tree\n  */\ntemplate <typename IndexVector>\nvoid treePostorder(typename IndexVector::Scalar n, IndexVector& parent, IndexVector& post)\n{\n  typedef typename IndexVector::Scalar StorageIndex;\n  IndexVector first_kid, next_kid; // Linked list of children \n  StorageIndex postnum; \n  // Allocate storage for working arrays and results \n  first_kid.resize(n+1); \n  next_kid.setZero(n+1);\n  post.setZero(n+1);\n  \n  // Set up structure describing children\n  first_kid.setConstant(-1); \n  for (StorageIndex v = n-1; v >= 0; v--) \n  {\n    StorageIndex dad = parent(v);\n    next_kid(v) = first_kid(dad); \n    first_kid(dad) = v; \n  }\n  \n  // Depth-first search from dummy root vertex #n\n  postnum = 0; \n  internal::nr_etdfs(n, parent, first_kid, next_kid, post, postnum);\n}\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // SPARSE_COLETREE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseCore/SparseCompressedBase.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2015 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SPARSE_COMPRESSED_BASE_H\n#define EIGEN_SPARSE_COMPRESSED_BASE_H\n\nnamespace Eigen { \n\ntemplate<typename Derived> class SparseCompressedBase;\n  \nnamespace internal {\n\ntemplate<typename Derived>\nstruct traits<SparseCompressedBase<Derived> > : traits<Derived>\n{};\n\n} // end namespace internal\n\n/** \\ingroup SparseCore_Module\n  * \\class SparseCompressedBase\n  * \\brief Common base class for sparse [compressed]-{row|column}-storage format.\n  *\n  * This class defines the common interface for all derived classes implementing the compressed sparse storage format, such as:\n  *  - SparseMatrix\n  *  - Ref<SparseMatrixType,Options>\n  *  - Map<SparseMatrixType>\n  *\n  */\ntemplate<typename Derived>\nclass SparseCompressedBase\n  : public SparseMatrixBase<Derived>\n{\n  public:\n    typedef SparseMatrixBase<Derived> Base;\n    EIGEN_SPARSE_PUBLIC_INTERFACE(SparseCompressedBase)\n    using Base::operator=;\n    using Base::IsRowMajor;\n    \n    class InnerIterator;\n    class ReverseInnerIterator;\n    \n  protected:\n    typedef typename Base::IndexVector IndexVector;\n    Eigen::Map<IndexVector> innerNonZeros() { return Eigen::Map<IndexVector>(innerNonZeroPtr(), isCompressed()?0:derived().outerSize()); }\n    const  Eigen::Map<const IndexVector> innerNonZeros() const { return Eigen::Map<const IndexVector>(innerNonZeroPtr(), isCompressed()?0:derived().outerSize()); }\n        \n  public:\n    \n    /** \\returns the number of non zero coefficients */\n    inline Index nonZeros() const\n    {\n      if(Derived::IsVectorAtCompileTime && outerIndexPtr()==0)\n        return derived().nonZeros();\n      else if(isCompressed())\n        return outerIndexPtr()[derived().outerSize()]-outerIndexPtr()[0];\n      else if(derived().outerSize()==0)\n        return 0;\n      else\n        return innerNonZeros().sum();\n    }\n    \n    /** \\returns a const pointer to the array of values.\n      * This function is aimed at interoperability with other libraries.\n      * \\sa innerIndexPtr(), outerIndexPtr() */\n    inline const Scalar* valuePtr() const { return derived().valuePtr(); }\n    /** \\returns a non-const pointer to the array of values.\n      * This function is aimed at interoperability with other libraries.\n      * \\sa innerIndexPtr(), outerIndexPtr() */\n    inline Scalar* valuePtr() { return derived().valuePtr(); }\n\n    /** \\returns a const pointer to the array of inner indices.\n      * This function is aimed at interoperability with other libraries.\n      * \\sa valuePtr(), outerIndexPtr() */\n    inline const StorageIndex* innerIndexPtr() const { return derived().innerIndexPtr(); }\n    /** \\returns a non-const pointer to the array of inner indices.\n      * This function is aimed at interoperability with other libraries.\n      * \\sa valuePtr(), outerIndexPtr() */\n    inline StorageIndex* innerIndexPtr() { return derived().innerIndexPtr(); }\n\n    /** \\returns a const pointer to the array of the starting positions of the inner vectors.\n      * This function is aimed at interoperability with other libraries.\n      * \\warning it returns the null pointer 0 for SparseVector\n      * \\sa valuePtr(), innerIndexPtr() */\n    inline const StorageIndex* outerIndexPtr() const { return derived().outerIndexPtr(); }\n    /** \\returns a non-const pointer to the array of the starting positions of the inner vectors.\n      * This function is aimed at interoperability with other libraries.\n      * \\warning it returns the null pointer 0 for SparseVector\n      * \\sa valuePtr(), innerIndexPtr() */\n    inline StorageIndex* outerIndexPtr() { return derived().outerIndexPtr(); }\n\n    /** \\returns a const pointer to the array of the number of non zeros of the inner vectors.\n      * This function is aimed at interoperability with other libraries.\n      * \\warning it returns the null pointer 0 in compressed mode */\n    inline const StorageIndex* innerNonZeroPtr() const { return derived().innerNonZeroPtr(); }\n    /** \\returns a non-const pointer to the array of the number of non zeros of the inner vectors.\n      * This function is aimed at interoperability with other libraries.\n      * \\warning it returns the null pointer 0 in compressed mode */\n    inline StorageIndex* innerNonZeroPtr() { return derived().innerNonZeroPtr(); }\n    \n    /** \\returns whether \\c *this is in compressed form. */\n    inline bool isCompressed() const { return innerNonZeroPtr()==0; }\n\n    /** \\returns a read-only view of the stored coefficients as a 1D array expression.\n      *\n      * \\warning this method is for \\b compressed \\b storage \\b only, and it will trigger an assertion otherwise.\n      *\n      * \\sa valuePtr(), isCompressed() */\n    const Map<const Array<Scalar,Dynamic,1> > coeffs() const { eigen_assert(isCompressed()); return Array<Scalar,Dynamic,1>::Map(valuePtr(),nonZeros()); }\n\n    /** \\returns a read-write view of the stored coefficients as a 1D array expression\n      *\n      * \\warning this method is for \\b compressed \\b storage \\b only, and it will trigger an assertion otherwise.\n      *\n      * Here is an example:\n      * \\include SparseMatrix_coeffs.cpp\n      * and the output is:\n      * \\include SparseMatrix_coeffs.out\n      *\n      * \\sa valuePtr(), isCompressed() */\n    Map<Array<Scalar,Dynamic,1> > coeffs() { eigen_assert(isCompressed()); return Array<Scalar,Dynamic,1>::Map(valuePtr(),nonZeros()); }\n\n  protected:\n    /** Default constructor. Do nothing. */\n    SparseCompressedBase() {}\n  private:\n    template<typename OtherDerived> explicit SparseCompressedBase(const SparseCompressedBase<OtherDerived>&);\n};\n\ntemplate<typename Derived>\nclass SparseCompressedBase<Derived>::InnerIterator\n{\n  public:\n    InnerIterator()\n      : m_values(0), m_indices(0), m_outer(0), m_id(0), m_end(0)\n    {}\n\n    InnerIterator(const InnerIterator& other)\n      : m_values(other.m_values), m_indices(other.m_indices), m_outer(other.m_outer), m_id(other.m_id), m_end(other.m_end)\n    {}\n\n    InnerIterator& operator=(const InnerIterator& other)\n    {\n      m_values = other.m_values;\n      m_indices = other.m_indices;\n      const_cast<OuterType&>(m_outer).setValue(other.m_outer.value());\n      m_id = other.m_id;\n      m_end = other.m_end;\n      return *this;\n    }\n\n    InnerIterator(const SparseCompressedBase& mat, Index outer)\n      : m_values(mat.valuePtr()), m_indices(mat.innerIndexPtr()), m_outer(outer)\n    {\n      if(Derived::IsVectorAtCompileTime && mat.outerIndexPtr()==0)\n      {\n        m_id = 0;\n        m_end = mat.nonZeros();\n      }\n      else\n      {\n        m_id = mat.outerIndexPtr()[outer];\n        if(mat.isCompressed())\n          m_end = mat.outerIndexPtr()[outer+1];\n        else\n          m_end = m_id + mat.innerNonZeroPtr()[outer];\n      }\n    }\n\n    explicit InnerIterator(const SparseCompressedBase& mat)\n      : m_values(mat.valuePtr()), m_indices(mat.innerIndexPtr()), m_outer(0), m_id(0), m_end(mat.nonZeros())\n    {\n      EIGEN_STATIC_ASSERT_VECTOR_ONLY(Derived);\n    }\n\n    explicit InnerIterator(const internal::CompressedStorage<Scalar,StorageIndex>& data)\n      : m_values(data.valuePtr()), m_indices(data.indexPtr()), m_outer(0), m_id(0), m_end(data.size())\n    {\n      EIGEN_STATIC_ASSERT_VECTOR_ONLY(Derived);\n    }\n\n    inline InnerIterator& operator++() { m_id++; return *this; }\n\n    inline const Scalar& value() const { return m_values[m_id]; }\n    inline Scalar& valueRef() { return const_cast<Scalar&>(m_values[m_id]); }\n\n    inline StorageIndex index() const { return m_indices[m_id]; }\n    inline Index outer() const { return m_outer.value(); }\n    inline Index row() const { return IsRowMajor ? m_outer.value() : index(); }\n    inline Index col() const { return IsRowMajor ? index() : m_outer.value(); }\n\n    inline operator bool() const { return (m_id < m_end); }\n\n  protected:\n    const Scalar* m_values;\n    const StorageIndex* m_indices;\n    typedef internal::variable_if_dynamic<Index,Derived::IsVectorAtCompileTime?0:Dynamic> OuterType;\n    const OuterType m_outer;\n    Index m_id;\n    Index m_end;\n  private:\n    // If you get here, then you're not using the right InnerIterator type, e.g.:\n    //   SparseMatrix<double,RowMajor> A;\n    //   SparseMatrix<double>::InnerIterator it(A,0);\n    template<typename T> InnerIterator(const SparseMatrixBase<T>&, Index outer);\n};\n\ntemplate<typename Derived>\nclass SparseCompressedBase<Derived>::ReverseInnerIterator\n{\n  public:\n    ReverseInnerIterator(const SparseCompressedBase& mat, Index outer)\n      : m_values(mat.valuePtr()), m_indices(mat.innerIndexPtr()), m_outer(outer)\n    {\n      if(Derived::IsVectorAtCompileTime && mat.outerIndexPtr()==0)\n      {\n        m_start = 0;\n        m_id = mat.nonZeros();\n      }\n      else\n      {\n        m_start = mat.outerIndexPtr()[outer];\n        if(mat.isCompressed())\n          m_id = mat.outerIndexPtr()[outer+1];\n        else\n          m_id = m_start + mat.innerNonZeroPtr()[outer];\n      }\n    }\n\n    explicit ReverseInnerIterator(const SparseCompressedBase& mat)\n      : m_values(mat.valuePtr()), m_indices(mat.innerIndexPtr()), m_outer(0), m_start(0), m_id(mat.nonZeros())\n    {\n      EIGEN_STATIC_ASSERT_VECTOR_ONLY(Derived);\n    }\n\n    explicit ReverseInnerIterator(const internal::CompressedStorage<Scalar,StorageIndex>& data)\n      : m_values(data.valuePtr()), m_indices(data.indexPtr()), m_outer(0), m_start(0), m_id(data.size())\n    {\n      EIGEN_STATIC_ASSERT_VECTOR_ONLY(Derived);\n    }\n\n    inline ReverseInnerIterator& operator--() { --m_id; return *this; }\n\n    inline const Scalar& value() const { return m_values[m_id-1]; }\n    inline Scalar& valueRef() { return const_cast<Scalar&>(m_values[m_id-1]); }\n\n    inline StorageIndex index() const { return m_indices[m_id-1]; }\n    inline Index outer() const { return m_outer.value(); }\n    inline Index row() const { return IsRowMajor ? m_outer.value() : index(); }\n    inline Index col() const { return IsRowMajor ? index() : m_outer.value(); }\n\n    inline operator bool() const { return (m_id > m_start); }\n\n  protected:\n    const Scalar* m_values;\n    const StorageIndex* m_indices;\n    typedef internal::variable_if_dynamic<Index,Derived::IsVectorAtCompileTime?0:Dynamic> OuterType;\n    const OuterType m_outer;\n    Index m_start;\n    Index m_id;\n};\n\nnamespace internal {\n\ntemplate<typename Derived>\nstruct evaluator<SparseCompressedBase<Derived> >\n  : evaluator_base<Derived>\n{\n  typedef typename Derived::Scalar Scalar;\n  typedef typename Derived::InnerIterator InnerIterator;\n  \n  enum {\n    CoeffReadCost = NumTraits<Scalar>::ReadCost,\n    Flags = Derived::Flags\n  };\n  \n  evaluator() : m_matrix(0)\n  {\n    EIGEN_INTERNAL_CHECK_COST_VALUE(CoeffReadCost);\n  }\n  explicit evaluator(const Derived &mat) : m_matrix(&mat)\n  {\n    EIGEN_INTERNAL_CHECK_COST_VALUE(CoeffReadCost);\n  }\n  \n  inline Index nonZerosEstimate() const {\n    return m_matrix->nonZeros();\n  }\n  \n  operator Derived&() { return m_matrix->const_cast_derived(); }\n  operator const Derived&() const { return *m_matrix; }\n  \n  typedef typename DenseCoeffsBase<Derived,ReadOnlyAccessors>::CoeffReturnType CoeffReturnType;\n  Scalar coeff(Index row, Index col) const\n  { return m_matrix->coeff(row,col); }\n  \n  Scalar& coeffRef(Index row, Index col)\n  {\n    eigen_internal_assert(row>=0 && row<m_matrix->rows() && col>=0 && col<m_matrix->cols());\n      \n    const Index outer = Derived::IsRowMajor ? row : col;\n    const Index inner = Derived::IsRowMajor ? col : row;\n\n    Index start = m_matrix->outerIndexPtr()[outer];\n    Index end = m_matrix->isCompressed() ? m_matrix->outerIndexPtr()[outer+1] : m_matrix->outerIndexPtr()[outer] + m_matrix->innerNonZeroPtr()[outer];\n    eigen_assert(end>start && \"you are using a non finalized sparse matrix or written coefficient does not exist\");\n    const Index p =   std::lower_bound(m_matrix->innerIndexPtr()+start, m_matrix->innerIndexPtr()+end,inner)\n                    - m_matrix->innerIndexPtr();\n    eigen_assert((p<end) && (m_matrix->innerIndexPtr()[p]==inner) && \"written coefficient does not exist\");\n    return m_matrix->const_cast_derived().valuePtr()[p];\n  }\n\n  const Derived *m_matrix;\n};\n\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_SPARSE_COMPRESSED_BASE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseCore/SparseCwiseBinaryOp.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2014 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SPARSE_CWISE_BINARY_OP_H\n#define EIGEN_SPARSE_CWISE_BINARY_OP_H\n\nnamespace Eigen { \n\n// Here we have to handle 3 cases:\n//  1 - sparse op dense\n//  2 - dense op sparse\n//  3 - sparse op sparse\n// We also need to implement a 4th iterator for:\n//  4 - dense op dense\n// Finally, we also need to distinguish between the product and other operations :\n//                configuration      returned mode\n//  1 - sparse op dense    product      sparse\n//                         generic      dense\n//  2 - dense op sparse    product      sparse\n//                         generic      dense\n//  3 - sparse op sparse   product      sparse\n//                         generic      sparse\n//  4 - dense op dense     product      dense\n//                         generic      dense\n//\n// TODO to ease compiler job, we could specialize product/quotient with a scalar\n//      and fallback to cwise-unary evaluator using bind1st_op and bind2nd_op.\n\ntemplate<typename BinaryOp, typename Lhs, typename Rhs>\nclass CwiseBinaryOpImpl<BinaryOp, Lhs, Rhs, Sparse>\n  : public SparseMatrixBase<CwiseBinaryOp<BinaryOp, Lhs, Rhs> >\n{\n  public:\n    typedef CwiseBinaryOp<BinaryOp, Lhs, Rhs> Derived;\n    typedef SparseMatrixBase<Derived> Base;\n    EIGEN_SPARSE_PUBLIC_INTERFACE(Derived)\n    CwiseBinaryOpImpl()\n    {\n      EIGEN_STATIC_ASSERT((\n                (!internal::is_same<typename internal::traits<Lhs>::StorageKind,\n                                    typename internal::traits<Rhs>::StorageKind>::value)\n            ||  ((Lhs::Flags&RowMajorBit) == (Rhs::Flags&RowMajorBit))),\n            THE_STORAGE_ORDER_OF_BOTH_SIDES_MUST_MATCH);\n    }\n};\n\nnamespace internal {\n\n  \n// Generic \"sparse OP sparse\"\ntemplate<typename XprType> struct binary_sparse_evaluator;\n\ntemplate<typename BinaryOp, typename Lhs, typename Rhs>\nstruct binary_evaluator<CwiseBinaryOp<BinaryOp, Lhs, Rhs>, IteratorBased, IteratorBased>\n  : evaluator_base<CwiseBinaryOp<BinaryOp, Lhs, Rhs> >\n{\nprotected:\n  typedef typename evaluator<Lhs>::InnerIterator  LhsIterator;\n  typedef typename evaluator<Rhs>::InnerIterator  RhsIterator;\n  typedef CwiseBinaryOp<BinaryOp, Lhs, Rhs> XprType;\n  typedef typename traits<XprType>::Scalar Scalar;\n  typedef typename XprType::StorageIndex StorageIndex;\npublic:\n\n  class InnerIterator\n  {\n  public:\n    \n    EIGEN_STRONG_INLINE InnerIterator(const binary_evaluator& aEval, Index outer)\n      : m_lhsIter(aEval.m_lhsImpl,outer), m_rhsIter(aEval.m_rhsImpl,outer), m_functor(aEval.m_functor)\n    {\n      this->operator++();\n    }\n\n    EIGEN_STRONG_INLINE InnerIterator& operator++()\n    {\n      if (m_lhsIter && m_rhsIter && (m_lhsIter.index() == m_rhsIter.index()))\n      {\n        m_id = m_lhsIter.index();\n        m_value = m_functor(m_lhsIter.value(), m_rhsIter.value());\n        ++m_lhsIter;\n        ++m_rhsIter;\n      }\n      else if (m_lhsIter && (!m_rhsIter || (m_lhsIter.index() < m_rhsIter.index())))\n      {\n        m_id = m_lhsIter.index();\n        m_value = m_functor(m_lhsIter.value(), Scalar(0));\n        ++m_lhsIter;\n      }\n      else if (m_rhsIter && (!m_lhsIter || (m_lhsIter.index() > m_rhsIter.index())))\n      {\n        m_id = m_rhsIter.index();\n        m_value = m_functor(Scalar(0), m_rhsIter.value());\n        ++m_rhsIter;\n      }\n      else\n      {\n        m_value = 0; // this is to avoid a compilation warning\n        m_id = -1;\n      }\n      return *this;\n    }\n\n    EIGEN_STRONG_INLINE Scalar value() const { return m_value; }\n\n    EIGEN_STRONG_INLINE StorageIndex index() const { return m_id; }\n    EIGEN_STRONG_INLINE Index row() const { return Lhs::IsRowMajor ? m_lhsIter.row() : index(); }\n    EIGEN_STRONG_INLINE Index col() const { return Lhs::IsRowMajor ? index() : m_lhsIter.col(); }\n\n    EIGEN_STRONG_INLINE operator bool() const { return m_id>=0; }\n\n  protected:\n    LhsIterator m_lhsIter;\n    RhsIterator m_rhsIter;\n    const BinaryOp& m_functor;\n    Scalar m_value;\n    StorageIndex m_id;\n  };\n  \n  \n  enum {\n    CoeffReadCost = evaluator<Lhs>::CoeffReadCost + evaluator<Rhs>::CoeffReadCost + functor_traits<BinaryOp>::Cost,\n    Flags = XprType::Flags\n  };\n  \n  explicit binary_evaluator(const XprType& xpr)\n    : m_functor(xpr.functor()),\n      m_lhsImpl(xpr.lhs()), \n      m_rhsImpl(xpr.rhs())  \n  {\n    EIGEN_INTERNAL_CHECK_COST_VALUE(functor_traits<BinaryOp>::Cost);\n    EIGEN_INTERNAL_CHECK_COST_VALUE(CoeffReadCost);\n  }\n  \n  inline Index nonZerosEstimate() const {\n    return m_lhsImpl.nonZerosEstimate() + m_rhsImpl.nonZerosEstimate();\n  }\n\nprotected:\n  const BinaryOp m_functor;\n  evaluator<Lhs> m_lhsImpl;\n  evaluator<Rhs> m_rhsImpl;\n};\n\n// dense op sparse\ntemplate<typename BinaryOp, typename Lhs, typename Rhs>\nstruct binary_evaluator<CwiseBinaryOp<BinaryOp, Lhs, Rhs>, IndexBased, IteratorBased>\n  : evaluator_base<CwiseBinaryOp<BinaryOp, Lhs, Rhs> >\n{\nprotected:\n  typedef typename evaluator<Rhs>::InnerIterator  RhsIterator;\n  typedef CwiseBinaryOp<BinaryOp, Lhs, Rhs> XprType;\n  typedef typename traits<XprType>::Scalar Scalar;\n  typedef typename XprType::StorageIndex StorageIndex;\npublic:\n\n  class InnerIterator\n  {\n    enum { IsRowMajor = (int(Rhs::Flags)&RowMajorBit)==RowMajorBit };\n  public:\n\n    EIGEN_STRONG_INLINE InnerIterator(const binary_evaluator& aEval, Index outer)\n      : m_lhsEval(aEval.m_lhsImpl), m_rhsIter(aEval.m_rhsImpl,outer), m_functor(aEval.m_functor), m_value(0), m_id(-1), m_innerSize(aEval.m_expr.rhs().innerSize())\n    {\n      this->operator++();\n    }\n\n    EIGEN_STRONG_INLINE InnerIterator& operator++()\n    {\n      ++m_id;\n      if(m_id<m_innerSize)\n      {\n        Scalar lhsVal = m_lhsEval.coeff(IsRowMajor?m_rhsIter.outer():m_id,\n                                        IsRowMajor?m_id:m_rhsIter.outer());\n        if(m_rhsIter && m_rhsIter.index()==m_id)\n        {\n          m_value = m_functor(lhsVal, m_rhsIter.value());\n          ++m_rhsIter;\n        }\n        else\n          m_value = m_functor(lhsVal, Scalar(0));\n      }\n\n      return *this;\n    }\n\n    EIGEN_STRONG_INLINE Scalar value() const { eigen_internal_assert(m_id<m_innerSize); return m_value; }\n\n    EIGEN_STRONG_INLINE StorageIndex index() const { return m_id; }\n    EIGEN_STRONG_INLINE Index row() const { return IsRowMajor ? m_rhsIter.outer() : m_id; }\n    EIGEN_STRONG_INLINE Index col() const { return IsRowMajor ? m_id : m_rhsIter.outer(); }\n\n    EIGEN_STRONG_INLINE operator bool() const { return m_id<m_innerSize; }\n\n  protected:\n    const evaluator<Lhs> &m_lhsEval;\n    RhsIterator m_rhsIter;\n    const BinaryOp& m_functor;\n    Scalar m_value;\n    StorageIndex m_id;\n    StorageIndex m_innerSize;\n  };\n\n\n  enum {\n    CoeffReadCost = evaluator<Lhs>::CoeffReadCost + evaluator<Rhs>::CoeffReadCost + functor_traits<BinaryOp>::Cost,\n    // Expose storage order of the sparse expression\n    Flags = (XprType::Flags & ~RowMajorBit) | (int(Rhs::Flags)&RowMajorBit)\n  };\n\n  explicit binary_evaluator(const XprType& xpr)\n    : m_functor(xpr.functor()),\n      m_lhsImpl(xpr.lhs()),\n      m_rhsImpl(xpr.rhs()),\n      m_expr(xpr)\n  {\n    EIGEN_INTERNAL_CHECK_COST_VALUE(functor_traits<BinaryOp>::Cost);\n    EIGEN_INTERNAL_CHECK_COST_VALUE(CoeffReadCost);\n  }\n\n  inline Index nonZerosEstimate() const {\n    return m_expr.size();\n  }\n\nprotected:\n  const BinaryOp m_functor;\n  evaluator<Lhs> m_lhsImpl;\n  evaluator<Rhs> m_rhsImpl;\n  const XprType &m_expr;\n};\n\n// sparse op dense\ntemplate<typename BinaryOp, typename Lhs, typename Rhs>\nstruct binary_evaluator<CwiseBinaryOp<BinaryOp, Lhs, Rhs>, IteratorBased, IndexBased>\n  : evaluator_base<CwiseBinaryOp<BinaryOp, Lhs, Rhs> >\n{\nprotected:\n  typedef typename evaluator<Lhs>::InnerIterator  LhsIterator;\n  typedef CwiseBinaryOp<BinaryOp, Lhs, Rhs> XprType;\n  typedef typename traits<XprType>::Scalar Scalar;\n  typedef typename XprType::StorageIndex StorageIndex;\npublic:\n\n  class InnerIterator\n  {\n    enum { IsRowMajor = (int(Lhs::Flags)&RowMajorBit)==RowMajorBit };\n  public:\n\n    EIGEN_STRONG_INLINE InnerIterator(const binary_evaluator& aEval, Index outer)\n      : m_lhsIter(aEval.m_lhsImpl,outer), m_rhsEval(aEval.m_rhsImpl), m_functor(aEval.m_functor), m_value(0), m_id(-1), m_innerSize(aEval.m_expr.lhs().innerSize())\n    {\n      this->operator++();\n    }\n\n    EIGEN_STRONG_INLINE InnerIterator& operator++()\n    {\n      ++m_id;\n      if(m_id<m_innerSize)\n      {\n        Scalar rhsVal = m_rhsEval.coeff(IsRowMajor?m_lhsIter.outer():m_id,\n                                        IsRowMajor?m_id:m_lhsIter.outer());\n        if(m_lhsIter && m_lhsIter.index()==m_id)\n        {\n          m_value = m_functor(m_lhsIter.value(), rhsVal);\n          ++m_lhsIter;\n        }\n        else\n          m_value = m_functor(Scalar(0),rhsVal);\n      }\n\n      return *this;\n    }\n\n    EIGEN_STRONG_INLINE Scalar value() const { eigen_internal_assert(m_id<m_innerSize); return m_value; }\n\n    EIGEN_STRONG_INLINE StorageIndex index() const { return m_id; }\n    EIGEN_STRONG_INLINE Index row() const { return IsRowMajor ? m_lhsIter.outer() : m_id; }\n    EIGEN_STRONG_INLINE Index col() const { return IsRowMajor ? m_id : m_lhsIter.outer(); }\n\n    EIGEN_STRONG_INLINE operator bool() const { return m_id<m_innerSize; }\n\n  protected:\n    LhsIterator m_lhsIter;\n    const evaluator<Rhs> &m_rhsEval;\n    const BinaryOp& m_functor;\n    Scalar m_value;\n    StorageIndex m_id;\n    StorageIndex m_innerSize;\n  };\n\n\n  enum {\n    CoeffReadCost = evaluator<Lhs>::CoeffReadCost + evaluator<Rhs>::CoeffReadCost + functor_traits<BinaryOp>::Cost,\n    // Expose storage order of the sparse expression\n    Flags = (XprType::Flags & ~RowMajorBit) | (int(Lhs::Flags)&RowMajorBit)\n  };\n\n  explicit binary_evaluator(const XprType& xpr)\n    : m_functor(xpr.functor()),\n      m_lhsImpl(xpr.lhs()),\n      m_rhsImpl(xpr.rhs()),\n      m_expr(xpr)\n  {\n    EIGEN_INTERNAL_CHECK_COST_VALUE(functor_traits<BinaryOp>::Cost);\n    EIGEN_INTERNAL_CHECK_COST_VALUE(CoeffReadCost);\n  }\n\n  inline Index nonZerosEstimate() const {\n    return m_expr.size();\n  }\n\nprotected:\n  const BinaryOp m_functor;\n  evaluator<Lhs> m_lhsImpl;\n  evaluator<Rhs> m_rhsImpl;\n  const XprType &m_expr;\n};\n\ntemplate<typename T,\n         typename LhsKind   = typename evaluator_traits<typename T::Lhs>::Kind,\n         typename RhsKind   = typename evaluator_traits<typename T::Rhs>::Kind,\n         typename LhsScalar = typename traits<typename T::Lhs>::Scalar,\n         typename RhsScalar = typename traits<typename T::Rhs>::Scalar> struct sparse_conjunction_evaluator;\n\n// \"sparse .* sparse\"\ntemplate<typename T1, typename T2, typename Lhs, typename Rhs>\nstruct binary_evaluator<CwiseBinaryOp<scalar_product_op<T1,T2>, Lhs, Rhs>, IteratorBased, IteratorBased>\n  : sparse_conjunction_evaluator<CwiseBinaryOp<scalar_product_op<T1,T2>, Lhs, Rhs> >\n{\n  typedef CwiseBinaryOp<scalar_product_op<T1,T2>, Lhs, Rhs> XprType;\n  typedef sparse_conjunction_evaluator<XprType> Base;\n  explicit binary_evaluator(const XprType& xpr) : Base(xpr) {}\n};\n// \"dense .* sparse\"\ntemplate<typename T1, typename T2, typename Lhs, typename Rhs>\nstruct binary_evaluator<CwiseBinaryOp<scalar_product_op<T1,T2>, Lhs, Rhs>, IndexBased, IteratorBased>\n  : sparse_conjunction_evaluator<CwiseBinaryOp<scalar_product_op<T1,T2>, Lhs, Rhs> >\n{\n  typedef CwiseBinaryOp<scalar_product_op<T1,T2>, Lhs, Rhs> XprType;\n  typedef sparse_conjunction_evaluator<XprType> Base;\n  explicit binary_evaluator(const XprType& xpr) : Base(xpr) {}\n};\n// \"sparse .* dense\"\ntemplate<typename T1, typename T2, typename Lhs, typename Rhs>\nstruct binary_evaluator<CwiseBinaryOp<scalar_product_op<T1,T2>, Lhs, Rhs>, IteratorBased, IndexBased>\n  : sparse_conjunction_evaluator<CwiseBinaryOp<scalar_product_op<T1,T2>, Lhs, Rhs> >\n{\n  typedef CwiseBinaryOp<scalar_product_op<T1,T2>, Lhs, Rhs> XprType;\n  typedef sparse_conjunction_evaluator<XprType> Base;\n  explicit binary_evaluator(const XprType& xpr) : Base(xpr) {}\n};\n\n// \"sparse && sparse\"\ntemplate<typename Lhs, typename Rhs>\nstruct binary_evaluator<CwiseBinaryOp<scalar_boolean_and_op, Lhs, Rhs>, IteratorBased, IteratorBased>\n  : sparse_conjunction_evaluator<CwiseBinaryOp<scalar_boolean_and_op, Lhs, Rhs> >\n{\n  typedef CwiseBinaryOp<scalar_boolean_and_op, Lhs, Rhs> XprType;\n  typedef sparse_conjunction_evaluator<XprType> Base;\n  explicit binary_evaluator(const XprType& xpr) : Base(xpr) {}\n};\n// \"dense && sparse\"\ntemplate<typename Lhs, typename Rhs>\nstruct binary_evaluator<CwiseBinaryOp<scalar_boolean_and_op, Lhs, Rhs>, IndexBased, IteratorBased>\n  : sparse_conjunction_evaluator<CwiseBinaryOp<scalar_boolean_and_op, Lhs, Rhs> >\n{\n  typedef CwiseBinaryOp<scalar_boolean_and_op, Lhs, Rhs> XprType;\n  typedef sparse_conjunction_evaluator<XprType> Base;\n  explicit binary_evaluator(const XprType& xpr) : Base(xpr) {}\n};\n// \"sparse && dense\"\ntemplate<typename Lhs, typename Rhs>\nstruct binary_evaluator<CwiseBinaryOp<scalar_boolean_and_op, Lhs, Rhs>, IteratorBased, IndexBased>\n  : sparse_conjunction_evaluator<CwiseBinaryOp<scalar_boolean_and_op, Lhs, Rhs> >\n{\n  typedef CwiseBinaryOp<scalar_boolean_and_op, Lhs, Rhs> XprType;\n  typedef sparse_conjunction_evaluator<XprType> Base;\n  explicit binary_evaluator(const XprType& xpr) : Base(xpr) {}\n};\n\n// \"sparse ^ sparse\"\ntemplate<typename XprType>\nstruct sparse_conjunction_evaluator<XprType, IteratorBased, IteratorBased>\n  : evaluator_base<XprType>\n{\nprotected:\n  typedef typename XprType::Functor BinaryOp;\n  typedef typename XprType::Lhs LhsArg;\n  typedef typename XprType::Rhs RhsArg;\n  typedef typename evaluator<LhsArg>::InnerIterator  LhsIterator;\n  typedef typename evaluator<RhsArg>::InnerIterator  RhsIterator;\n  typedef typename XprType::StorageIndex StorageIndex;\n  typedef typename traits<XprType>::Scalar Scalar;\npublic:\n\n  class InnerIterator\n  {\n  public:\n    \n    EIGEN_STRONG_INLINE InnerIterator(const sparse_conjunction_evaluator& aEval, Index outer)\n      : m_lhsIter(aEval.m_lhsImpl,outer), m_rhsIter(aEval.m_rhsImpl,outer), m_functor(aEval.m_functor)\n    {\n      while (m_lhsIter && m_rhsIter && (m_lhsIter.index() != m_rhsIter.index()))\n      {\n        if (m_lhsIter.index() < m_rhsIter.index())\n          ++m_lhsIter;\n        else\n          ++m_rhsIter;\n      }\n    }\n\n    EIGEN_STRONG_INLINE InnerIterator& operator++()\n    {\n      ++m_lhsIter;\n      ++m_rhsIter;\n      while (m_lhsIter && m_rhsIter && (m_lhsIter.index() != m_rhsIter.index()))\n      {\n        if (m_lhsIter.index() < m_rhsIter.index())\n          ++m_lhsIter;\n        else\n          ++m_rhsIter;\n      }\n      return *this;\n    }\n    \n    EIGEN_STRONG_INLINE Scalar value() const { return m_functor(m_lhsIter.value(), m_rhsIter.value()); }\n\n    EIGEN_STRONG_INLINE StorageIndex index() const { return m_lhsIter.index(); }\n    EIGEN_STRONG_INLINE Index row() const { return m_lhsIter.row(); }\n    EIGEN_STRONG_INLINE Index col() const { return m_lhsIter.col(); }\n\n    EIGEN_STRONG_INLINE operator bool() const { return (m_lhsIter && m_rhsIter); }\n\n  protected:\n    LhsIterator m_lhsIter;\n    RhsIterator m_rhsIter;\n    const BinaryOp& m_functor;\n  };\n  \n  \n  enum {\n    CoeffReadCost = evaluator<LhsArg>::CoeffReadCost + evaluator<RhsArg>::CoeffReadCost + functor_traits<BinaryOp>::Cost,\n    Flags = XprType::Flags\n  };\n  \n  explicit sparse_conjunction_evaluator(const XprType& xpr)\n    : m_functor(xpr.functor()),\n      m_lhsImpl(xpr.lhs()), \n      m_rhsImpl(xpr.rhs())  \n  {\n    EIGEN_INTERNAL_CHECK_COST_VALUE(functor_traits<BinaryOp>::Cost);\n    EIGEN_INTERNAL_CHECK_COST_VALUE(CoeffReadCost);\n  }\n  \n  inline Index nonZerosEstimate() const {\n    return (std::min)(m_lhsImpl.nonZerosEstimate(), m_rhsImpl.nonZerosEstimate());\n  }\n\nprotected:\n  const BinaryOp m_functor;\n  evaluator<LhsArg> m_lhsImpl;\n  evaluator<RhsArg> m_rhsImpl;\n};\n\n// \"dense ^ sparse\"\ntemplate<typename XprType>\nstruct sparse_conjunction_evaluator<XprType, IndexBased, IteratorBased>\n  : evaluator_base<XprType>\n{\nprotected:\n  typedef typename XprType::Functor BinaryOp;\n  typedef typename XprType::Lhs LhsArg;\n  typedef typename XprType::Rhs RhsArg;\n  typedef evaluator<LhsArg> LhsEvaluator;\n  typedef typename evaluator<RhsArg>::InnerIterator  RhsIterator;\n  typedef typename XprType::StorageIndex StorageIndex;\n  typedef typename traits<XprType>::Scalar Scalar;\npublic:\n\n  class InnerIterator\n  {\n    enum { IsRowMajor = (int(RhsArg::Flags)&RowMajorBit)==RowMajorBit };\n\n  public:\n    \n    EIGEN_STRONG_INLINE InnerIterator(const sparse_conjunction_evaluator& aEval, Index outer)\n      : m_lhsEval(aEval.m_lhsImpl), m_rhsIter(aEval.m_rhsImpl,outer), m_functor(aEval.m_functor), m_outer(outer)\n    {}\n\n    EIGEN_STRONG_INLINE InnerIterator& operator++()\n    {\n      ++m_rhsIter;\n      return *this;\n    }\n\n    EIGEN_STRONG_INLINE Scalar value() const\n    { return m_functor(m_lhsEval.coeff(IsRowMajor?m_outer:m_rhsIter.index(),IsRowMajor?m_rhsIter.index():m_outer), m_rhsIter.value()); }\n\n    EIGEN_STRONG_INLINE StorageIndex index() const { return m_rhsIter.index(); }\n    EIGEN_STRONG_INLINE Index row() const { return m_rhsIter.row(); }\n    EIGEN_STRONG_INLINE Index col() const { return m_rhsIter.col(); }\n\n    EIGEN_STRONG_INLINE operator bool() const { return m_rhsIter; }\n    \n  protected:\n    const LhsEvaluator &m_lhsEval;\n    RhsIterator m_rhsIter;\n    const BinaryOp& m_functor;\n    const Index m_outer;\n  };\n  \n  \n  enum {\n    CoeffReadCost = evaluator<LhsArg>::CoeffReadCost + evaluator<RhsArg>::CoeffReadCost + functor_traits<BinaryOp>::Cost,\n    // Expose storage order of the sparse expression\n    Flags = (XprType::Flags & ~RowMajorBit) | (int(RhsArg::Flags)&RowMajorBit)\n  };\n  \n  explicit sparse_conjunction_evaluator(const XprType& xpr)\n    : m_functor(xpr.functor()),\n      m_lhsImpl(xpr.lhs()), \n      m_rhsImpl(xpr.rhs())  \n  {\n    EIGEN_INTERNAL_CHECK_COST_VALUE(functor_traits<BinaryOp>::Cost);\n    EIGEN_INTERNAL_CHECK_COST_VALUE(CoeffReadCost);\n  }\n  \n  inline Index nonZerosEstimate() const {\n    return m_rhsImpl.nonZerosEstimate();\n  }\n\nprotected:\n  const BinaryOp m_functor;\n  evaluator<LhsArg> m_lhsImpl;\n  evaluator<RhsArg> m_rhsImpl;\n};\n\n// \"sparse ^ dense\"\ntemplate<typename XprType>\nstruct sparse_conjunction_evaluator<XprType, IteratorBased, IndexBased>\n  : evaluator_base<XprType>\n{\nprotected:\n  typedef typename XprType::Functor BinaryOp;\n  typedef typename XprType::Lhs LhsArg;\n  typedef typename XprType::Rhs RhsArg;\n  typedef typename evaluator<LhsArg>::InnerIterator LhsIterator;\n  typedef evaluator<RhsArg> RhsEvaluator;\n  typedef typename XprType::StorageIndex StorageIndex;\n  typedef typename traits<XprType>::Scalar Scalar;\npublic:\n\n  class InnerIterator\n  {\n    enum { IsRowMajor = (int(LhsArg::Flags)&RowMajorBit)==RowMajorBit };\n\n  public:\n    \n    EIGEN_STRONG_INLINE InnerIterator(const sparse_conjunction_evaluator& aEval, Index outer)\n      : m_lhsIter(aEval.m_lhsImpl,outer), m_rhsEval(aEval.m_rhsImpl), m_functor(aEval.m_functor), m_outer(outer)\n    {}\n\n    EIGEN_STRONG_INLINE InnerIterator& operator++()\n    {\n      ++m_lhsIter;\n      return *this;\n    }\n\n    EIGEN_STRONG_INLINE Scalar value() const\n    { return m_functor(m_lhsIter.value(),\n                       m_rhsEval.coeff(IsRowMajor?m_outer:m_lhsIter.index(),IsRowMajor?m_lhsIter.index():m_outer)); }\n\n    EIGEN_STRONG_INLINE StorageIndex index() const { return m_lhsIter.index(); }\n    EIGEN_STRONG_INLINE Index row() const { return m_lhsIter.row(); }\n    EIGEN_STRONG_INLINE Index col() const { return m_lhsIter.col(); }\n\n    EIGEN_STRONG_INLINE operator bool() const { return m_lhsIter; }\n    \n  protected:\n    LhsIterator m_lhsIter;\n    const evaluator<RhsArg> &m_rhsEval;\n    const BinaryOp& m_functor;\n    const Index m_outer;\n  };\n  \n  \n  enum {\n    CoeffReadCost = evaluator<LhsArg>::CoeffReadCost + evaluator<RhsArg>::CoeffReadCost + functor_traits<BinaryOp>::Cost,\n    // Expose storage order of the sparse expression\n    Flags = (XprType::Flags & ~RowMajorBit) | (int(LhsArg::Flags)&RowMajorBit)\n  };\n  \n  explicit sparse_conjunction_evaluator(const XprType& xpr)\n    : m_functor(xpr.functor()),\n      m_lhsImpl(xpr.lhs()), \n      m_rhsImpl(xpr.rhs())  \n  {\n    EIGEN_INTERNAL_CHECK_COST_VALUE(functor_traits<BinaryOp>::Cost);\n    EIGEN_INTERNAL_CHECK_COST_VALUE(CoeffReadCost);\n  }\n  \n  inline Index nonZerosEstimate() const {\n    return m_lhsImpl.nonZerosEstimate();\n  }\n\nprotected:\n  const BinaryOp m_functor;\n  evaluator<LhsArg> m_lhsImpl;\n  evaluator<RhsArg> m_rhsImpl;\n};\n\n}\n\n/***************************************************************************\n* Implementation of SparseMatrixBase and SparseCwise functions/operators\n***************************************************************************/\n\ntemplate<typename Derived>\ntemplate<typename OtherDerived>\nEIGEN_STRONG_INLINE Derived &\nSparseMatrixBase<Derived>::operator-=(const SparseMatrixBase<OtherDerived> &other)\n{\n  return derived() = derived() - other.derived();\n}\n\ntemplate<typename Derived>\ntemplate<typename OtherDerived>\nEIGEN_STRONG_INLINE Derived &\nSparseMatrixBase<Derived>::operator+=(const SparseMatrixBase<OtherDerived>& other)\n{\n  return derived() = derived() + other.derived();\n}\n\ntemplate<typename Derived>\ntemplate<typename OtherDerived>\nDerived& SparseMatrixBase<Derived>::operator+=(const DiagonalBase<OtherDerived>& other)\n{\n  call_assignment_no_alias(derived(), other.derived(), internal::add_assign_op<Scalar,typename OtherDerived::Scalar>());\n  return derived();\n}\n\ntemplate<typename Derived>\ntemplate<typename OtherDerived>\nDerived& SparseMatrixBase<Derived>::operator-=(const DiagonalBase<OtherDerived>& other)\n{\n  call_assignment_no_alias(derived(), other.derived(), internal::sub_assign_op<Scalar,typename OtherDerived::Scalar>());\n  return derived();\n}\n    \ntemplate<typename Derived>\ntemplate<typename OtherDerived>\nEIGEN_STRONG_INLINE const typename SparseMatrixBase<Derived>::template CwiseProductDenseReturnType<OtherDerived>::Type\nSparseMatrixBase<Derived>::cwiseProduct(const MatrixBase<OtherDerived> &other) const\n{\n  return typename CwiseProductDenseReturnType<OtherDerived>::Type(derived(), other.derived());\n}\n\ntemplate<typename DenseDerived, typename SparseDerived>\nEIGEN_STRONG_INLINE const CwiseBinaryOp<internal::scalar_sum_op<typename DenseDerived::Scalar,typename SparseDerived::Scalar>, const DenseDerived, const SparseDerived>\noperator+(const MatrixBase<DenseDerived> &a, const SparseMatrixBase<SparseDerived> &b)\n{\n  return CwiseBinaryOp<internal::scalar_sum_op<typename DenseDerived::Scalar,typename SparseDerived::Scalar>, const DenseDerived, const SparseDerived>(a.derived(), b.derived());\n}\n\ntemplate<typename SparseDerived, typename DenseDerived>\nEIGEN_STRONG_INLINE const CwiseBinaryOp<internal::scalar_sum_op<typename SparseDerived::Scalar,typename DenseDerived::Scalar>, const SparseDerived, const DenseDerived>\noperator+(const SparseMatrixBase<SparseDerived> &a, const MatrixBase<DenseDerived> &b)\n{\n  return CwiseBinaryOp<internal::scalar_sum_op<typename SparseDerived::Scalar,typename DenseDerived::Scalar>, const SparseDerived, const DenseDerived>(a.derived(), b.derived());\n}\n\ntemplate<typename DenseDerived, typename SparseDerived>\nEIGEN_STRONG_INLINE const CwiseBinaryOp<internal::scalar_difference_op<typename DenseDerived::Scalar,typename SparseDerived::Scalar>, const DenseDerived, const SparseDerived>\noperator-(const MatrixBase<DenseDerived> &a, const SparseMatrixBase<SparseDerived> &b)\n{\n  return CwiseBinaryOp<internal::scalar_difference_op<typename DenseDerived::Scalar,typename SparseDerived::Scalar>, const DenseDerived, const SparseDerived>(a.derived(), b.derived());\n}\n\ntemplate<typename SparseDerived, typename DenseDerived>\nEIGEN_STRONG_INLINE const CwiseBinaryOp<internal::scalar_difference_op<typename SparseDerived::Scalar,typename DenseDerived::Scalar>, const SparseDerived, const DenseDerived>\noperator-(const SparseMatrixBase<SparseDerived> &a, const MatrixBase<DenseDerived> &b)\n{\n  return CwiseBinaryOp<internal::scalar_difference_op<typename SparseDerived::Scalar,typename DenseDerived::Scalar>, const SparseDerived, const DenseDerived>(a.derived(), b.derived());\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_SPARSE_CWISE_BINARY_OP_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseCore/SparseCwiseUnaryOp.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2015 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SPARSE_CWISE_UNARY_OP_H\n#define EIGEN_SPARSE_CWISE_UNARY_OP_H\n\nnamespace Eigen { \n\nnamespace internal {\n  \ntemplate<typename UnaryOp, typename ArgType>\nstruct unary_evaluator<CwiseUnaryOp<UnaryOp,ArgType>, IteratorBased>\n  : public evaluator_base<CwiseUnaryOp<UnaryOp,ArgType> >\n{\n  public:\n    typedef CwiseUnaryOp<UnaryOp, ArgType> XprType;\n\n    class InnerIterator;\n    \n    enum {\n      CoeffReadCost = evaluator<ArgType>::CoeffReadCost + functor_traits<UnaryOp>::Cost,\n      Flags = XprType::Flags\n    };\n    \n    explicit unary_evaluator(const XprType& op) : m_functor(op.functor()), m_argImpl(op.nestedExpression())\n    {\n      EIGEN_INTERNAL_CHECK_COST_VALUE(functor_traits<UnaryOp>::Cost);\n      EIGEN_INTERNAL_CHECK_COST_VALUE(CoeffReadCost);\n    }\n    \n    inline Index nonZerosEstimate() const {\n      return m_argImpl.nonZerosEstimate();\n    }\n\n  protected:\n    typedef typename evaluator<ArgType>::InnerIterator        EvalIterator;\n    \n    const UnaryOp m_functor;\n    evaluator<ArgType> m_argImpl;\n};\n\ntemplate<typename UnaryOp, typename ArgType>\nclass unary_evaluator<CwiseUnaryOp<UnaryOp,ArgType>, IteratorBased>::InnerIterator\n    : public unary_evaluator<CwiseUnaryOp<UnaryOp,ArgType>, IteratorBased>::EvalIterator\n{\n    typedef typename XprType::Scalar Scalar;\n    typedef typename unary_evaluator<CwiseUnaryOp<UnaryOp,ArgType>, IteratorBased>::EvalIterator Base;\n  public:\n\n    EIGEN_STRONG_INLINE InnerIterator(const unary_evaluator& unaryOp, Index outer)\n      : Base(unaryOp.m_argImpl,outer), m_functor(unaryOp.m_functor)\n    {}\n\n    EIGEN_STRONG_INLINE InnerIterator& operator++()\n    { Base::operator++(); return *this; }\n\n    EIGEN_STRONG_INLINE Scalar value() const { return m_functor(Base::value()); }\n\n  protected:\n    const UnaryOp m_functor;\n  private:\n    Scalar& valueRef();\n};\n\ntemplate<typename ViewOp, typename ArgType>\nstruct unary_evaluator<CwiseUnaryView<ViewOp,ArgType>, IteratorBased>\n  : public evaluator_base<CwiseUnaryView<ViewOp,ArgType> >\n{\n  public:\n    typedef CwiseUnaryView<ViewOp, ArgType> XprType;\n\n    class InnerIterator;\n    \n    enum {\n      CoeffReadCost = evaluator<ArgType>::CoeffReadCost + functor_traits<ViewOp>::Cost,\n      Flags = XprType::Flags\n    };\n    \n    explicit unary_evaluator(const XprType& op) : m_functor(op.functor()), m_argImpl(op.nestedExpression())\n    {\n      EIGEN_INTERNAL_CHECK_COST_VALUE(functor_traits<ViewOp>::Cost);\n      EIGEN_INTERNAL_CHECK_COST_VALUE(CoeffReadCost);\n    }\n\n  protected:\n    typedef typename evaluator<ArgType>::InnerIterator        EvalIterator;\n    \n    const ViewOp m_functor;\n    evaluator<ArgType> m_argImpl;\n};\n\ntemplate<typename ViewOp, typename ArgType>\nclass unary_evaluator<CwiseUnaryView<ViewOp,ArgType>, IteratorBased>::InnerIterator\n    : public unary_evaluator<CwiseUnaryView<ViewOp,ArgType>, IteratorBased>::EvalIterator\n{\n    typedef typename XprType::Scalar Scalar;\n    typedef typename unary_evaluator<CwiseUnaryView<ViewOp,ArgType>, IteratorBased>::EvalIterator Base;\n  public:\n\n    EIGEN_STRONG_INLINE InnerIterator(const unary_evaluator& unaryOp, Index outer)\n      : Base(unaryOp.m_argImpl,outer), m_functor(unaryOp.m_functor)\n    {}\n\n    EIGEN_STRONG_INLINE InnerIterator& operator++()\n    { Base::operator++(); return *this; }\n\n    EIGEN_STRONG_INLINE Scalar value() const { return m_functor(Base::value()); }\n    EIGEN_STRONG_INLINE Scalar& valueRef() { return m_functor(Base::valueRef()); }\n\n  protected:\n    const ViewOp m_functor;\n};\n\n} // end namespace internal\n\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE Derived&\nSparseMatrixBase<Derived>::operator*=(const Scalar& other)\n{\n  for (Index j=0; j<outerSize(); ++j)\n    for (typename Derived::InnerIterator i(derived(),j); i; ++i)\n      i.valueRef() *= other;\n  return derived();\n}\n\ntemplate<typename Derived>\nEIGEN_STRONG_INLINE Derived&\nSparseMatrixBase<Derived>::operator/=(const Scalar& other)\n{\n  for (Index j=0; j<outerSize(); ++j)\n    for (typename Derived::InnerIterator i(derived(),j); i; ++i)\n      i.valueRef() /= other;\n  return derived();\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_SPARSE_CWISE_UNARY_OP_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseCore/SparseDenseProduct.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2015 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SPARSEDENSEPRODUCT_H\n#define EIGEN_SPARSEDENSEPRODUCT_H\n\nnamespace Eigen { \n\nnamespace internal {\n\ntemplate <> struct product_promote_storage_type<Sparse,Dense, OuterProduct> { typedef Sparse ret; };\ntemplate <> struct product_promote_storage_type<Dense,Sparse, OuterProduct> { typedef Sparse ret; };\n\ntemplate<typename SparseLhsType, typename DenseRhsType, typename DenseResType,\n         typename AlphaType,\n         int LhsStorageOrder = ((SparseLhsType::Flags&RowMajorBit)==RowMajorBit) ? RowMajor : ColMajor,\n         bool ColPerCol = ((DenseRhsType::Flags&RowMajorBit)==0) || DenseRhsType::ColsAtCompileTime==1>\nstruct sparse_time_dense_product_impl;\n\ntemplate<typename SparseLhsType, typename DenseRhsType, typename DenseResType>\nstruct sparse_time_dense_product_impl<SparseLhsType,DenseRhsType,DenseResType, typename DenseResType::Scalar, RowMajor, true>\n{\n  typedef typename internal::remove_all<SparseLhsType>::type Lhs;\n  typedef typename internal::remove_all<DenseRhsType>::type Rhs;\n  typedef typename internal::remove_all<DenseResType>::type Res;\n  typedef typename evaluator<Lhs>::InnerIterator LhsInnerIterator;\n  typedef evaluator<Lhs> LhsEval;\n  static void run(const SparseLhsType& lhs, const DenseRhsType& rhs, DenseResType& res, const typename Res::Scalar& alpha)\n  {\n    LhsEval lhsEval(lhs);\n    \n    Index n = lhs.outerSize();\n#ifdef EIGEN_HAS_OPENMP\n    Eigen::initParallel();\n    Index threads = Eigen::nbThreads();\n#endif\n    \n    for(Index c=0; c<rhs.cols(); ++c)\n    {\n#ifdef EIGEN_HAS_OPENMP\n      // This 20000 threshold has been found experimentally on 2D and 3D Poisson problems.\n      // It basically represents the minimal amount of work to be done to be worth it.\n      if(threads>1 && lhsEval.nonZerosEstimate() > 20000)\n      {\n        #pragma omp parallel for schedule(dynamic,(n+threads*4-1)/(threads*4)) num_threads(threads)\n        for(Index i=0; i<n; ++i)\n          processRow(lhsEval,rhs,res,alpha,i,c);\n      }\n      else\n#endif\n      {\n        for(Index i=0; i<n; ++i)\n          processRow(lhsEval,rhs,res,alpha,i,c);\n      }\n    }\n  }\n  \n  static void processRow(const LhsEval& lhsEval, const DenseRhsType& rhs, DenseResType& res, const typename Res::Scalar& alpha, Index i, Index col)\n  {\n    typename Res::Scalar tmp(0);\n    for(LhsInnerIterator it(lhsEval,i); it ;++it)\n      tmp += it.value() * rhs.coeff(it.index(),col);\n    res.coeffRef(i,col) += alpha * tmp;\n  }\n  \n};\n\n// FIXME: what is the purpose of the following specialization? Is it for the BlockedSparse format?\n// -> let's disable it for now as it is conflicting with generic scalar*matrix and matrix*scalar operators\n// template<typename T1, typename T2/*, int _Options, typename _StrideType*/>\n// struct ScalarBinaryOpTraits<T1, Ref<T2/*, _Options, _StrideType*/> >\n// {\n//   enum {\n//     Defined = 1\n//   };\n//   typedef typename CwiseUnaryOp<scalar_multiple2_op<T1, typename T2::Scalar>, T2>::PlainObject ReturnType;\n// };\n\ntemplate<typename SparseLhsType, typename DenseRhsType, typename DenseResType, typename AlphaType>\nstruct sparse_time_dense_product_impl<SparseLhsType,DenseRhsType,DenseResType, AlphaType, ColMajor, true>\n{\n  typedef typename internal::remove_all<SparseLhsType>::type Lhs;\n  typedef typename internal::remove_all<DenseRhsType>::type Rhs;\n  typedef typename internal::remove_all<DenseResType>::type Res;\n  typedef typename evaluator<Lhs>::InnerIterator LhsInnerIterator;\n  static void run(const SparseLhsType& lhs, const DenseRhsType& rhs, DenseResType& res, const AlphaType& alpha)\n  {\n    evaluator<Lhs> lhsEval(lhs);\n    for(Index c=0; c<rhs.cols(); ++c)\n    {\n      for(Index j=0; j<lhs.outerSize(); ++j)\n      {\n//        typename Res::Scalar rhs_j = alpha * rhs.coeff(j,c);\n        typename ScalarBinaryOpTraits<AlphaType, typename Rhs::Scalar>::ReturnType rhs_j(alpha * rhs.coeff(j,c));\n        for(LhsInnerIterator it(lhsEval,j); it ;++it)\n          res.coeffRef(it.index(),c) += it.value() * rhs_j;\n      }\n    }\n  }\n};\n\ntemplate<typename SparseLhsType, typename DenseRhsType, typename DenseResType>\nstruct sparse_time_dense_product_impl<SparseLhsType,DenseRhsType,DenseResType, typename DenseResType::Scalar, RowMajor, false>\n{\n  typedef typename internal::remove_all<SparseLhsType>::type Lhs;\n  typedef typename internal::remove_all<DenseRhsType>::type Rhs;\n  typedef typename internal::remove_all<DenseResType>::type Res;\n  typedef typename evaluator<Lhs>::InnerIterator LhsInnerIterator;\n  static void run(const SparseLhsType& lhs, const DenseRhsType& rhs, DenseResType& res, const typename Res::Scalar& alpha)\n  {\n    evaluator<Lhs> lhsEval(lhs);\n    for(Index j=0; j<lhs.outerSize(); ++j)\n    {\n      typename Res::RowXpr res_j(res.row(j));\n      for(LhsInnerIterator it(lhsEval,j); it ;++it)\n        res_j += (alpha*it.value()) * rhs.row(it.index());\n    }\n  }\n};\n\ntemplate<typename SparseLhsType, typename DenseRhsType, typename DenseResType>\nstruct sparse_time_dense_product_impl<SparseLhsType,DenseRhsType,DenseResType, typename DenseResType::Scalar, ColMajor, false>\n{\n  typedef typename internal::remove_all<SparseLhsType>::type Lhs;\n  typedef typename internal::remove_all<DenseRhsType>::type Rhs;\n  typedef typename internal::remove_all<DenseResType>::type Res;\n  typedef typename evaluator<Lhs>::InnerIterator LhsInnerIterator;\n  static void run(const SparseLhsType& lhs, const DenseRhsType& rhs, DenseResType& res, const typename Res::Scalar& alpha)\n  {\n    evaluator<Lhs> lhsEval(lhs);\n    for(Index j=0; j<lhs.outerSize(); ++j)\n    {\n      typename Rhs::ConstRowXpr rhs_j(rhs.row(j));\n      for(LhsInnerIterator it(lhsEval,j); it ;++it)\n        res.row(it.index()) += (alpha*it.value()) * rhs_j;\n    }\n  }\n};\n\ntemplate<typename SparseLhsType, typename DenseRhsType, typename DenseResType,typename AlphaType>\ninline void sparse_time_dense_product(const SparseLhsType& lhs, const DenseRhsType& rhs, DenseResType& res, const AlphaType& alpha)\n{\n  sparse_time_dense_product_impl<SparseLhsType,DenseRhsType,DenseResType, AlphaType>::run(lhs, rhs, res, alpha);\n}\n\n} // end namespace internal\n\nnamespace internal {\n\ntemplate<typename Lhs, typename Rhs, int ProductType>\nstruct generic_product_impl<Lhs, Rhs, SparseShape, DenseShape, ProductType>\n : generic_product_impl_base<Lhs,Rhs,generic_product_impl<Lhs,Rhs,SparseShape,DenseShape,ProductType> >\n{\n  typedef typename Product<Lhs,Rhs>::Scalar Scalar;\n  \n  template<typename Dest>\n  static void scaleAndAddTo(Dest& dst, const Lhs& lhs, const Rhs& rhs, const Scalar& alpha)\n  {\n    typedef typename nested_eval<Lhs,((Rhs::Flags&RowMajorBit)==0) ? 1 : Rhs::ColsAtCompileTime>::type LhsNested;\n    typedef typename nested_eval<Rhs,((Lhs::Flags&RowMajorBit)==0) ? 1 : Dynamic>::type RhsNested;\n    LhsNested lhsNested(lhs);\n    RhsNested rhsNested(rhs);\n    internal::sparse_time_dense_product(lhsNested, rhsNested, dst, alpha);\n  }\n};\n\ntemplate<typename Lhs, typename Rhs, int ProductType>\nstruct generic_product_impl<Lhs, Rhs, SparseTriangularShape, DenseShape, ProductType>\n  : generic_product_impl<Lhs, Rhs, SparseShape, DenseShape, ProductType>\n{};\n\ntemplate<typename Lhs, typename Rhs, int ProductType>\nstruct generic_product_impl<Lhs, Rhs, DenseShape, SparseShape, ProductType>\n  : generic_product_impl_base<Lhs,Rhs,generic_product_impl<Lhs,Rhs,DenseShape,SparseShape,ProductType> >\n{\n  typedef typename Product<Lhs,Rhs>::Scalar Scalar;\n  \n  template<typename Dst>\n  static void scaleAndAddTo(Dst& dst, const Lhs& lhs, const Rhs& rhs, const Scalar& alpha)\n  {\n    typedef typename nested_eval<Lhs,((Rhs::Flags&RowMajorBit)==0) ? Dynamic : 1>::type LhsNested;\n    typedef typename nested_eval<Rhs,((Lhs::Flags&RowMajorBit)==RowMajorBit) ? 1 : Lhs::RowsAtCompileTime>::type RhsNested;\n    LhsNested lhsNested(lhs);\n    RhsNested rhsNested(rhs);\n    \n    // transpose everything\n    Transpose<Dst> dstT(dst);\n    internal::sparse_time_dense_product(rhsNested.transpose(), lhsNested.transpose(), dstT, alpha);\n  }\n};\n\ntemplate<typename Lhs, typename Rhs, int ProductType>\nstruct generic_product_impl<Lhs, Rhs, DenseShape, SparseTriangularShape, ProductType>\n  : generic_product_impl<Lhs, Rhs, DenseShape, SparseShape, ProductType>\n{};\n\ntemplate<typename LhsT, typename RhsT, bool NeedToTranspose>\nstruct sparse_dense_outer_product_evaluator\n{\nprotected:\n  typedef typename conditional<NeedToTranspose,RhsT,LhsT>::type Lhs1;\n  typedef typename conditional<NeedToTranspose,LhsT,RhsT>::type ActualRhs;\n  typedef Product<LhsT,RhsT,DefaultProduct> ProdXprType;\n  \n  // if the actual left-hand side is a dense vector,\n  // then build a sparse-view so that we can seamlessly iterate over it.\n  typedef typename conditional<is_same<typename internal::traits<Lhs1>::StorageKind,Sparse>::value,\n            Lhs1, SparseView<Lhs1> >::type ActualLhs;\n  typedef typename conditional<is_same<typename internal::traits<Lhs1>::StorageKind,Sparse>::value,\n            Lhs1 const&, SparseView<Lhs1> >::type LhsArg;\n            \n  typedef evaluator<ActualLhs> LhsEval;\n  typedef evaluator<ActualRhs> RhsEval;\n  typedef typename evaluator<ActualLhs>::InnerIterator LhsIterator;\n  typedef typename ProdXprType::Scalar Scalar;\n  \npublic:\n  enum {\n    Flags = NeedToTranspose ? RowMajorBit : 0,\n    CoeffReadCost = HugeCost\n  };\n  \n  class InnerIterator : public LhsIterator\n  {\n  public:\n    InnerIterator(const sparse_dense_outer_product_evaluator &xprEval, Index outer)\n      : LhsIterator(xprEval.m_lhsXprImpl, 0),\n        m_outer(outer),\n        m_empty(false),\n        m_factor(get(xprEval.m_rhsXprImpl, outer, typename internal::traits<ActualRhs>::StorageKind() ))\n    {}\n    \n    EIGEN_STRONG_INLINE Index outer() const { return m_outer; }\n    EIGEN_STRONG_INLINE Index row()   const { return NeedToTranspose ? m_outer : LhsIterator::index(); }\n    EIGEN_STRONG_INLINE Index col()   const { return NeedToTranspose ? LhsIterator::index() : m_outer; }\n\n    EIGEN_STRONG_INLINE Scalar value() const { return LhsIterator::value() * m_factor; }\n    EIGEN_STRONG_INLINE operator bool() const { return LhsIterator::operator bool() && (!m_empty); }\n    \n  protected:\n    Scalar get(const RhsEval &rhs, Index outer, Dense = Dense()) const\n    {\n      return rhs.coeff(outer);\n    }\n    \n    Scalar get(const RhsEval &rhs, Index outer, Sparse = Sparse())\n    {\n      typename RhsEval::InnerIterator it(rhs, outer);\n      if (it && it.index()==0 && it.value()!=Scalar(0))\n        return it.value();\n      m_empty = true;\n      return Scalar(0);\n    }\n    \n    Index m_outer;\n    bool m_empty;\n    Scalar m_factor;\n  };\n  \n  sparse_dense_outer_product_evaluator(const Lhs1 &lhs, const ActualRhs &rhs)\n     : m_lhs(lhs), m_lhsXprImpl(m_lhs), m_rhsXprImpl(rhs)\n  {\n    EIGEN_INTERNAL_CHECK_COST_VALUE(CoeffReadCost);\n  }\n  \n  // transpose case\n  sparse_dense_outer_product_evaluator(const ActualRhs &rhs, const Lhs1 &lhs)\n     : m_lhs(lhs), m_lhsXprImpl(m_lhs), m_rhsXprImpl(rhs)\n  {\n    EIGEN_INTERNAL_CHECK_COST_VALUE(CoeffReadCost);\n  }\n    \nprotected:\n  const LhsArg m_lhs;\n  evaluator<ActualLhs> m_lhsXprImpl;\n  evaluator<ActualRhs> m_rhsXprImpl;\n};\n\n// sparse * dense outer product\ntemplate<typename Lhs, typename Rhs>\nstruct product_evaluator<Product<Lhs, Rhs, DefaultProduct>, OuterProduct, SparseShape, DenseShape>\n  : sparse_dense_outer_product_evaluator<Lhs,Rhs, Lhs::IsRowMajor>\n{\n  typedef sparse_dense_outer_product_evaluator<Lhs,Rhs, Lhs::IsRowMajor> Base;\n  \n  typedef Product<Lhs, Rhs> XprType;\n  typedef typename XprType::PlainObject PlainObject;\n\n  explicit product_evaluator(const XprType& xpr)\n    : Base(xpr.lhs(), xpr.rhs())\n  {}\n  \n};\n\ntemplate<typename Lhs, typename Rhs>\nstruct product_evaluator<Product<Lhs, Rhs, DefaultProduct>, OuterProduct, DenseShape, SparseShape>\n  : sparse_dense_outer_product_evaluator<Lhs,Rhs, Rhs::IsRowMajor>\n{\n  typedef sparse_dense_outer_product_evaluator<Lhs,Rhs, Rhs::IsRowMajor> Base;\n  \n  typedef Product<Lhs, Rhs> XprType;\n  typedef typename XprType::PlainObject PlainObject;\n\n  explicit product_evaluator(const XprType& xpr)\n    : Base(xpr.lhs(), xpr.rhs())\n  {}\n  \n};\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_SPARSEDENSEPRODUCT_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseCore/SparseDiagonalProduct.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009-2015 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SPARSE_DIAGONAL_PRODUCT_H\n#define EIGEN_SPARSE_DIAGONAL_PRODUCT_H\n\nnamespace Eigen { \n\n// The product of a diagonal matrix with a sparse matrix can be easily\n// implemented using expression template.\n// We have two consider very different cases:\n// 1 - diag * row-major sparse\n//     => each inner vector <=> scalar * sparse vector product\n//     => so we can reuse CwiseUnaryOp::InnerIterator\n// 2 - diag * col-major sparse\n//     => each inner vector <=> densevector * sparse vector cwise product\n//     => again, we can reuse specialization of CwiseBinaryOp::InnerIterator\n//        for that particular case\n// The two other cases are symmetric.\n\nnamespace internal {\n\nenum {\n  SDP_AsScalarProduct,\n  SDP_AsCwiseProduct\n};\n  \ntemplate<typename SparseXprType, typename DiagonalCoeffType, int SDP_Tag>\nstruct sparse_diagonal_product_evaluator;\n\ntemplate<typename Lhs, typename Rhs, int ProductTag>\nstruct product_evaluator<Product<Lhs, Rhs, DefaultProduct>, ProductTag, DiagonalShape, SparseShape>\n  : public sparse_diagonal_product_evaluator<Rhs, typename Lhs::DiagonalVectorType, Rhs::Flags&RowMajorBit?SDP_AsScalarProduct:SDP_AsCwiseProduct>\n{\n  typedef Product<Lhs, Rhs, DefaultProduct> XprType;\n  enum { CoeffReadCost = HugeCost, Flags = Rhs::Flags&RowMajorBit, Alignment = 0 }; // FIXME CoeffReadCost & Flags\n  \n  typedef sparse_diagonal_product_evaluator<Rhs, typename Lhs::DiagonalVectorType, Rhs::Flags&RowMajorBit?SDP_AsScalarProduct:SDP_AsCwiseProduct> Base;\n  explicit product_evaluator(const XprType& xpr) : Base(xpr.rhs(), xpr.lhs().diagonal()) {}\n};\n\ntemplate<typename Lhs, typename Rhs, int ProductTag>\nstruct product_evaluator<Product<Lhs, Rhs, DefaultProduct>, ProductTag, SparseShape, DiagonalShape>\n  : public sparse_diagonal_product_evaluator<Lhs, Transpose<const typename Rhs::DiagonalVectorType>, Lhs::Flags&RowMajorBit?SDP_AsCwiseProduct:SDP_AsScalarProduct>\n{\n  typedef Product<Lhs, Rhs, DefaultProduct> XprType;\n  enum { CoeffReadCost = HugeCost, Flags = Lhs::Flags&RowMajorBit, Alignment = 0 }; // FIXME CoeffReadCost & Flags\n  \n  typedef sparse_diagonal_product_evaluator<Lhs, Transpose<const typename Rhs::DiagonalVectorType>, Lhs::Flags&RowMajorBit?SDP_AsCwiseProduct:SDP_AsScalarProduct> Base;\n  explicit product_evaluator(const XprType& xpr) : Base(xpr.lhs(), xpr.rhs().diagonal().transpose()) {}\n};\n\ntemplate<typename SparseXprType, typename DiagonalCoeffType>\nstruct sparse_diagonal_product_evaluator<SparseXprType, DiagonalCoeffType, SDP_AsScalarProduct>\n{\nprotected:\n  typedef typename evaluator<SparseXprType>::InnerIterator SparseXprInnerIterator;\n  typedef typename SparseXprType::Scalar Scalar;\n  \npublic:\n  class InnerIterator : public SparseXprInnerIterator\n  {\n  public:\n    InnerIterator(const sparse_diagonal_product_evaluator &xprEval, Index outer)\n      : SparseXprInnerIterator(xprEval.m_sparseXprImpl, outer),\n        m_coeff(xprEval.m_diagCoeffImpl.coeff(outer))\n    {}\n    \n    EIGEN_STRONG_INLINE Scalar value() const { return m_coeff * SparseXprInnerIterator::value(); }\n  protected:\n    typename DiagonalCoeffType::Scalar m_coeff;\n  };\n  \n  sparse_diagonal_product_evaluator(const SparseXprType &sparseXpr, const DiagonalCoeffType &diagCoeff)\n    : m_sparseXprImpl(sparseXpr), m_diagCoeffImpl(diagCoeff)\n  {}\n    \nprotected:\n  evaluator<SparseXprType> m_sparseXprImpl;\n  evaluator<DiagonalCoeffType> m_diagCoeffImpl;\n};\n\n\ntemplate<typename SparseXprType, typename DiagCoeffType>\nstruct sparse_diagonal_product_evaluator<SparseXprType, DiagCoeffType, SDP_AsCwiseProduct>\n{\n  typedef typename SparseXprType::Scalar Scalar;\n  typedef typename SparseXprType::StorageIndex StorageIndex;\n  \n  typedef typename nested_eval<DiagCoeffType,SparseXprType::IsRowMajor ? SparseXprType::RowsAtCompileTime\n                                                                       : SparseXprType::ColsAtCompileTime>::type DiagCoeffNested;\n  \n  class InnerIterator\n  {\n    typedef typename evaluator<SparseXprType>::InnerIterator SparseXprIter;\n  public:\n    InnerIterator(const sparse_diagonal_product_evaluator &xprEval, Index outer)\n      : m_sparseIter(xprEval.m_sparseXprEval, outer), m_diagCoeffNested(xprEval.m_diagCoeffNested)\n    {}\n    \n    inline Scalar value() const { return m_sparseIter.value() * m_diagCoeffNested.coeff(index()); }\n    inline StorageIndex index() const  { return m_sparseIter.index(); }\n    inline Index outer() const  { return m_sparseIter.outer(); }\n    inline Index col() const    { return SparseXprType::IsRowMajor ? m_sparseIter.index() : m_sparseIter.outer(); }\n    inline Index row() const    { return SparseXprType::IsRowMajor ? m_sparseIter.outer() : m_sparseIter.index(); }\n    \n    EIGEN_STRONG_INLINE InnerIterator& operator++() { ++m_sparseIter; return *this; }\n    inline operator bool() const  { return m_sparseIter; }\n    \n  protected:\n    SparseXprIter m_sparseIter;\n    DiagCoeffNested m_diagCoeffNested;\n  };\n  \n  sparse_diagonal_product_evaluator(const SparseXprType &sparseXpr, const DiagCoeffType &diagCoeff)\n    : m_sparseXprEval(sparseXpr), m_diagCoeffNested(diagCoeff)\n  {}\n    \nprotected:\n  evaluator<SparseXprType> m_sparseXprEval;\n  DiagCoeffNested m_diagCoeffNested;\n};\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_SPARSE_DIAGONAL_PRODUCT_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseCore/SparseDot.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SPARSE_DOT_H\n#define EIGEN_SPARSE_DOT_H\n\nnamespace Eigen { \n\ntemplate<typename Derived>\ntemplate<typename OtherDerived>\ntypename internal::traits<Derived>::Scalar\nSparseMatrixBase<Derived>::dot(const MatrixBase<OtherDerived>& other) const\n{\n  EIGEN_STATIC_ASSERT_VECTOR_ONLY(Derived)\n  EIGEN_STATIC_ASSERT_VECTOR_ONLY(OtherDerived)\n  EIGEN_STATIC_ASSERT_SAME_VECTOR_SIZE(Derived,OtherDerived)\n  EIGEN_STATIC_ASSERT((internal::is_same<Scalar, typename OtherDerived::Scalar>::value),\n    YOU_MIXED_DIFFERENT_NUMERIC_TYPES__YOU_NEED_TO_USE_THE_CAST_METHOD_OF_MATRIXBASE_TO_CAST_NUMERIC_TYPES_EXPLICITLY)\n\n  eigen_assert(size() == other.size());\n  eigen_assert(other.size()>0 && \"you are using a non initialized vector\");\n\n  internal::evaluator<Derived> thisEval(derived());\n  typename internal::evaluator<Derived>::InnerIterator i(thisEval, 0);\n  Scalar res(0);\n  while (i)\n  {\n    res += numext::conj(i.value()) * other.coeff(i.index());\n    ++i;\n  }\n  return res;\n}\n\ntemplate<typename Derived>\ntemplate<typename OtherDerived>\ntypename internal::traits<Derived>::Scalar\nSparseMatrixBase<Derived>::dot(const SparseMatrixBase<OtherDerived>& other) const\n{\n  EIGEN_STATIC_ASSERT_VECTOR_ONLY(Derived)\n  EIGEN_STATIC_ASSERT_VECTOR_ONLY(OtherDerived)\n  EIGEN_STATIC_ASSERT_SAME_VECTOR_SIZE(Derived,OtherDerived)\n  EIGEN_STATIC_ASSERT((internal::is_same<Scalar, typename OtherDerived::Scalar>::value),\n    YOU_MIXED_DIFFERENT_NUMERIC_TYPES__YOU_NEED_TO_USE_THE_CAST_METHOD_OF_MATRIXBASE_TO_CAST_NUMERIC_TYPES_EXPLICITLY)\n\n  eigen_assert(size() == other.size());\n\n  internal::evaluator<Derived> thisEval(derived());\n  typename internal::evaluator<Derived>::InnerIterator i(thisEval, 0);\n  \n  internal::evaluator<OtherDerived>  otherEval(other.derived());\n  typename internal::evaluator<OtherDerived>::InnerIterator j(otherEval, 0);\n\n  Scalar res(0);\n  while (i && j)\n  {\n    if (i.index()==j.index())\n    {\n      res += numext::conj(i.value()) * j.value();\n      ++i; ++j;\n    }\n    else if (i.index()<j.index())\n      ++i;\n    else\n      ++j;\n  }\n  return res;\n}\n\ntemplate<typename Derived>\ninline typename NumTraits<typename internal::traits<Derived>::Scalar>::Real\nSparseMatrixBase<Derived>::squaredNorm() const\n{\n  return numext::real((*this).cwiseAbs2().sum());\n}\n\ntemplate<typename Derived>\ninline typename NumTraits<typename internal::traits<Derived>::Scalar>::Real\nSparseMatrixBase<Derived>::norm() const\n{\n  using std::sqrt;\n  return sqrt(squaredNorm());\n}\n\ntemplate<typename Derived>\ninline typename NumTraits<typename internal::traits<Derived>::Scalar>::Real\nSparseMatrixBase<Derived>::blueNorm() const\n{\n  return internal::blueNorm_impl(*this);\n}\n} // end namespace Eigen\n\n#endif // EIGEN_SPARSE_DOT_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseCore/SparseFuzzy.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2014 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SPARSE_FUZZY_H\n#define EIGEN_SPARSE_FUZZY_H\n\nnamespace Eigen {\n  \ntemplate<typename Derived>\ntemplate<typename OtherDerived>\nbool SparseMatrixBase<Derived>::isApprox(const SparseMatrixBase<OtherDerived>& other, const RealScalar &prec) const\n{\n  const typename internal::nested_eval<Derived,2,PlainObject>::type actualA(derived());\n  typename internal::conditional<bool(IsRowMajor)==bool(OtherDerived::IsRowMajor),\n    const typename internal::nested_eval<OtherDerived,2,PlainObject>::type,\n    const PlainObject>::type actualB(other.derived());\n\n  return (actualA - actualB).squaredNorm() <= prec * prec * numext::mini(actualA.squaredNorm(), actualB.squaredNorm());\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_SPARSE_FUZZY_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseCore/SparseMap.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2015 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SPARSE_MAP_H\n#define EIGEN_SPARSE_MAP_H\n\nnamespace Eigen {\n\nnamespace internal {\n\ntemplate<typename MatScalar, int MatOptions, typename MatIndex, int Options, typename StrideType>\nstruct traits<Map<SparseMatrix<MatScalar,MatOptions,MatIndex>, Options, StrideType> >\n  : public traits<SparseMatrix<MatScalar,MatOptions,MatIndex> >\n{\n  typedef SparseMatrix<MatScalar,MatOptions,MatIndex> PlainObjectType;\n  typedef traits<PlainObjectType> TraitsBase;\n  enum {\n    Flags = TraitsBase::Flags & (~NestByRefBit)\n  };\n};\n\ntemplate<typename MatScalar, int MatOptions, typename MatIndex, int Options, typename StrideType>\nstruct traits<Map<const SparseMatrix<MatScalar,MatOptions,MatIndex>, Options, StrideType> >\n  : public traits<SparseMatrix<MatScalar,MatOptions,MatIndex> >\n{\n  typedef SparseMatrix<MatScalar,MatOptions,MatIndex> PlainObjectType;\n  typedef traits<PlainObjectType> TraitsBase;\n  enum {\n    Flags = TraitsBase::Flags & (~ (NestByRefBit | LvalueBit))\n  };\n};\n\n} // end namespace internal\n\ntemplate<typename Derived,\n         int Level = internal::accessors_level<Derived>::has_write_access ? WriteAccessors : ReadOnlyAccessors\n> class SparseMapBase;\n\n/** \\ingroup SparseCore_Module\n  * class SparseMapBase\n  * \\brief Common base class for Map and Ref instance of sparse matrix and vector.\n  */\ntemplate<typename Derived>\nclass SparseMapBase<Derived,ReadOnlyAccessors>\n  : public SparseCompressedBase<Derived>\n{\n  public:\n    typedef SparseCompressedBase<Derived> Base;\n    typedef typename Base::Scalar Scalar;\n    typedef typename Base::StorageIndex StorageIndex;\n    enum { IsRowMajor = Base::IsRowMajor };\n    using Base::operator=;\n  protected:\n    \n    typedef typename internal::conditional<\n                         bool(internal::is_lvalue<Derived>::value),\n                         Scalar *, const Scalar *>::type ScalarPointer;\n    typedef typename internal::conditional<\n                         bool(internal::is_lvalue<Derived>::value),\n                         StorageIndex *, const StorageIndex *>::type IndexPointer;\n\n    Index   m_outerSize;\n    Index   m_innerSize;\n    Array<StorageIndex,2,1>  m_zero_nnz;\n    IndexPointer  m_outerIndex;\n    IndexPointer  m_innerIndices;\n    ScalarPointer m_values;\n    IndexPointer  m_innerNonZeros;\n\n  public:\n\n    /** \\copydoc SparseMatrixBase::rows() */\n    inline Index rows() const { return IsRowMajor ? m_outerSize : m_innerSize; }\n    /** \\copydoc SparseMatrixBase::cols() */\n    inline Index cols() const { return IsRowMajor ? m_innerSize : m_outerSize; }\n    /** \\copydoc SparseMatrixBase::innerSize() */\n    inline Index innerSize() const { return m_innerSize; }\n    /** \\copydoc SparseMatrixBase::outerSize() */\n    inline Index outerSize() const { return m_outerSize; }\n    /** \\copydoc SparseCompressedBase::nonZeros */\n    inline Index nonZeros() const { return m_zero_nnz[1]; }\n    \n    /** \\copydoc SparseCompressedBase::isCompressed */\n    bool isCompressed() const { return m_innerNonZeros==0; }\n\n    //----------------------------------------\n    // direct access interface\n    /** \\copydoc SparseMatrix::valuePtr */\n    inline const Scalar* valuePtr() const { return m_values; }\n    /** \\copydoc SparseMatrix::innerIndexPtr */\n    inline const StorageIndex* innerIndexPtr() const { return m_innerIndices; }\n    /** \\copydoc SparseMatrix::outerIndexPtr */\n    inline const StorageIndex* outerIndexPtr() const { return m_outerIndex; }\n    /** \\copydoc SparseMatrix::innerNonZeroPtr */\n    inline const StorageIndex* innerNonZeroPtr() const { return m_innerNonZeros; }\n    //----------------------------------------\n\n    /** \\copydoc SparseMatrix::coeff */\n    inline Scalar coeff(Index row, Index col) const\n    {\n      const Index outer = IsRowMajor ? row : col;\n      const Index inner = IsRowMajor ? col : row;\n\n      Index start = m_outerIndex[outer];\n      Index end = isCompressed() ? m_outerIndex[outer+1] : start + m_innerNonZeros[outer];\n      if (start==end)\n        return Scalar(0);\n      else if (end>0 && inner==m_innerIndices[end-1])\n        return m_values[end-1];\n      // ^^  optimization: let's first check if it is the last coefficient\n      // (very common in high level algorithms)\n\n      const StorageIndex* r = std::lower_bound(&m_innerIndices[start],&m_innerIndices[end-1],inner);\n      const Index id = r-&m_innerIndices[0];\n      return ((*r==inner) && (id<end)) ? m_values[id] : Scalar(0);\n    }\n\n    inline SparseMapBase(Index rows, Index cols, Index nnz, IndexPointer outerIndexPtr, IndexPointer innerIndexPtr,\n                              ScalarPointer valuePtr, IndexPointer innerNonZerosPtr = 0)\n      : m_outerSize(IsRowMajor?rows:cols), m_innerSize(IsRowMajor?cols:rows), m_zero_nnz(0,internal::convert_index<StorageIndex>(nnz)), m_outerIndex(outerIndexPtr),\n        m_innerIndices(innerIndexPtr), m_values(valuePtr), m_innerNonZeros(innerNonZerosPtr)\n    {}\n\n    // for vectors\n    inline SparseMapBase(Index size, Index nnz, IndexPointer innerIndexPtr, ScalarPointer valuePtr)\n      : m_outerSize(1), m_innerSize(size), m_zero_nnz(0,internal::convert_index<StorageIndex>(nnz)), m_outerIndex(m_zero_nnz.data()),\n        m_innerIndices(innerIndexPtr), m_values(valuePtr), m_innerNonZeros(0)\n    {}\n\n    /** Empty destructor */\n    inline ~SparseMapBase() {}\n\n  protected:\n    inline SparseMapBase() {}\n};\n\n/** \\ingroup SparseCore_Module\n  * class SparseMapBase\n  * \\brief Common base class for writable Map and Ref instance of sparse matrix and vector.\n  */\ntemplate<typename Derived>\nclass SparseMapBase<Derived,WriteAccessors>\n  : public SparseMapBase<Derived,ReadOnlyAccessors>\n{\n    typedef MapBase<Derived, ReadOnlyAccessors> ReadOnlyMapBase;\n    \n  public:\n    typedef SparseMapBase<Derived, ReadOnlyAccessors> Base;\n    typedef typename Base::Scalar Scalar;\n    typedef typename Base::StorageIndex StorageIndex;\n    enum { IsRowMajor = Base::IsRowMajor };\n    \n    using Base::operator=;\n\n  public:\n    \n    //----------------------------------------\n    // direct access interface\n    using Base::valuePtr;\n    using Base::innerIndexPtr;\n    using Base::outerIndexPtr;\n    using Base::innerNonZeroPtr;\n    /** \\copydoc SparseMatrix::valuePtr */\n    inline Scalar* valuePtr()              { return Base::m_values; }\n    /** \\copydoc SparseMatrix::innerIndexPtr */\n    inline StorageIndex* innerIndexPtr()   { return Base::m_innerIndices; }\n    /** \\copydoc SparseMatrix::outerIndexPtr */\n    inline StorageIndex* outerIndexPtr()   { return Base::m_outerIndex; }\n    /** \\copydoc SparseMatrix::innerNonZeroPtr */\n    inline StorageIndex* innerNonZeroPtr() { return Base::m_innerNonZeros; }\n    //----------------------------------------\n\n    /** \\copydoc SparseMatrix::coeffRef */\n    inline Scalar& coeffRef(Index row, Index col)\n    {\n      const Index outer = IsRowMajor ? row : col;\n      const Index inner = IsRowMajor ? col : row;\n\n      Index start = Base::m_outerIndex[outer];\n      Index end = Base::isCompressed() ? Base::m_outerIndex[outer+1] : start + Base::m_innerNonZeros[outer];\n      eigen_assert(end>=start && \"you probably called coeffRef on a non finalized matrix\");\n      eigen_assert(end>start && \"coeffRef cannot be called on a zero coefficient\");\n      StorageIndex* r = std::lower_bound(&Base::m_innerIndices[start],&Base::m_innerIndices[end],inner);\n      const Index id = r - &Base::m_innerIndices[0];\n      eigen_assert((*r==inner) && (id<end) && \"coeffRef cannot be called on a zero coefficient\");\n      return const_cast<Scalar*>(Base::m_values)[id];\n    }\n    \n    inline SparseMapBase(Index rows, Index cols, Index nnz, StorageIndex* outerIndexPtr, StorageIndex* innerIndexPtr,\n                         Scalar* valuePtr, StorageIndex* innerNonZerosPtr = 0)\n      : Base(rows, cols, nnz, outerIndexPtr, innerIndexPtr, valuePtr, innerNonZerosPtr)\n    {}\n\n    // for vectors\n    inline SparseMapBase(Index size, Index nnz, StorageIndex* innerIndexPtr, Scalar* valuePtr)\n      : Base(size, nnz, innerIndexPtr, valuePtr)\n    {}\n\n    /** Empty destructor */\n    inline ~SparseMapBase() {}\n\n  protected:\n    inline SparseMapBase() {}\n};\n\n/** \\ingroup SparseCore_Module\n  *\n  * \\brief Specialization of class Map for SparseMatrix-like storage.\n  *\n  * \\tparam SparseMatrixType the equivalent sparse matrix type of the referenced data, it must be a template instance of class SparseMatrix.\n  *\n  * \\sa class Map, class SparseMatrix, class Ref<SparseMatrixType,Options>\n  */\n#ifndef EIGEN_PARSED_BY_DOXYGEN\ntemplate<typename MatScalar, int MatOptions, typename MatIndex, int Options, typename StrideType>\nclass Map<SparseMatrix<MatScalar,MatOptions,MatIndex>, Options, StrideType>\n  : public SparseMapBase<Map<SparseMatrix<MatScalar,MatOptions,MatIndex>, Options, StrideType> >\n#else\ntemplate<typename SparseMatrixType>\nclass Map<SparseMatrixType>\n  : public SparseMapBase<Derived,WriteAccessors>\n#endif\n{\n  public:\n    typedef SparseMapBase<Map> Base;\n    EIGEN_SPARSE_PUBLIC_INTERFACE(Map)\n    enum { IsRowMajor = Base::IsRowMajor };\n\n  public:\n\n    /** Constructs a read-write Map to a sparse matrix of size \\a rows x \\a cols, containing \\a nnz non-zero coefficients,\n      * stored as a sparse format as defined by the pointers \\a outerIndexPtr, \\a innerIndexPtr, and \\a valuePtr.\n      * If the optional parameter \\a innerNonZerosPtr is the null pointer, then a standard compressed format is assumed.\n      *\n      * This constructor is available only if \\c SparseMatrixType is non-const.\n      *\n      * More details on the expected storage schemes are given in the \\ref TutorialSparse \"manual pages\".\n      */\n    inline Map(Index rows, Index cols, Index nnz, StorageIndex* outerIndexPtr,\n               StorageIndex* innerIndexPtr, Scalar* valuePtr, StorageIndex* innerNonZerosPtr = 0)\n      : Base(rows, cols, nnz, outerIndexPtr, innerIndexPtr, valuePtr, innerNonZerosPtr)\n    {}\n#ifndef EIGEN_PARSED_BY_DOXYGEN\n    /** Empty destructor */\n    inline ~Map() {}\n};\n\ntemplate<typename MatScalar, int MatOptions, typename MatIndex, int Options, typename StrideType>\nclass Map<const SparseMatrix<MatScalar,MatOptions,MatIndex>, Options, StrideType>\n  : public SparseMapBase<Map<const SparseMatrix<MatScalar,MatOptions,MatIndex>, Options, StrideType> >\n{\n  public:\n    typedef SparseMapBase<Map> Base;\n    EIGEN_SPARSE_PUBLIC_INTERFACE(Map)\n    enum { IsRowMajor = Base::IsRowMajor };\n\n  public:\n#endif\n    /** This is the const version of the above constructor.\n      *\n      * This constructor is available only if \\c SparseMatrixType is const, e.g.:\n      * \\code Map<const SparseMatrix<double> >  \\endcode\n      */\n    inline Map(Index rows, Index cols, Index nnz, const StorageIndex* outerIndexPtr,\n               const StorageIndex* innerIndexPtr, const Scalar* valuePtr, const StorageIndex* innerNonZerosPtr = 0)\n      : Base(rows, cols, nnz, outerIndexPtr, innerIndexPtr, valuePtr, innerNonZerosPtr)\n    {}\n\n    /** Empty destructor */\n    inline ~Map() {}\n};\n\nnamespace internal {\n\ntemplate<typename MatScalar, int MatOptions, typename MatIndex, int Options, typename StrideType>\nstruct evaluator<Map<SparseMatrix<MatScalar,MatOptions,MatIndex>, Options, StrideType> >\n  : evaluator<SparseCompressedBase<Map<SparseMatrix<MatScalar,MatOptions,MatIndex>, Options, StrideType> > >\n{\n  typedef evaluator<SparseCompressedBase<Map<SparseMatrix<MatScalar,MatOptions,MatIndex>, Options, StrideType> > > Base;\n  typedef Map<SparseMatrix<MatScalar,MatOptions,MatIndex>, Options, StrideType> XprType;  \n  evaluator() : Base() {}\n  explicit evaluator(const XprType &mat) : Base(mat) {}\n};\n\ntemplate<typename MatScalar, int MatOptions, typename MatIndex, int Options, typename StrideType>\nstruct evaluator<Map<const SparseMatrix<MatScalar,MatOptions,MatIndex>, Options, StrideType> >\n  : evaluator<SparseCompressedBase<Map<const SparseMatrix<MatScalar,MatOptions,MatIndex>, Options, StrideType> > >\n{\n  typedef evaluator<SparseCompressedBase<Map<const SparseMatrix<MatScalar,MatOptions,MatIndex>, Options, StrideType> > > Base;\n  typedef Map<const SparseMatrix<MatScalar,MatOptions,MatIndex>, Options, StrideType> XprType;  \n  evaluator() : Base() {}\n  explicit evaluator(const XprType &mat) : Base(mat) {}\n};\n\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_SPARSE_MAP_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseCore/SparseMatrix.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2014 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SPARSEMATRIX_H\n#define EIGEN_SPARSEMATRIX_H\n\nnamespace Eigen { \n\n/** \\ingroup SparseCore_Module\n  *\n  * \\class SparseMatrix\n  *\n  * \\brief A versatible sparse matrix representation\n  *\n  * This class implements a more versatile variants of the common \\em compressed row/column storage format.\n  * Each colmun's (resp. row) non zeros are stored as a pair of value with associated row (resp. colmiun) index.\n  * All the non zeros are stored in a single large buffer. Unlike the \\em compressed format, there might be extra\n  * space inbetween the nonzeros of two successive colmuns (resp. rows) such that insertion of new non-zero\n  * can be done with limited memory reallocation and copies.\n  *\n  * A call to the function makeCompressed() turns the matrix into the standard \\em compressed format\n  * compatible with many library.\n  *\n  * More details on this storage sceheme are given in the \\ref TutorialSparse \"manual pages\".\n  *\n  * \\tparam _Scalar the scalar type, i.e. the type of the coefficients\n  * \\tparam _Options Union of bit flags controlling the storage scheme. Currently the only possibility\n  *                 is ColMajor or RowMajor. The default is 0 which means column-major.\n  * \\tparam _Index the type of the indices. It has to be a \\b signed type (e.g., short, int, std::ptrdiff_t). Default is \\c int.\n  *\n  * This class can be extended with the help of the plugin mechanism described on the page\n  * \\ref TopicCustomizing_Plugins by defining the preprocessor symbol \\c EIGEN_SPARSEMATRIX_PLUGIN.\n  */\n\nnamespace internal {\ntemplate<typename _Scalar, int _Options, typename _Index>\nstruct traits<SparseMatrix<_Scalar, _Options, _Index> >\n{\n  typedef _Scalar Scalar;\n  typedef _Index StorageIndex;\n  typedef Sparse StorageKind;\n  typedef MatrixXpr XprKind;\n  enum {\n    RowsAtCompileTime = Dynamic,\n    ColsAtCompileTime = Dynamic,\n    MaxRowsAtCompileTime = Dynamic,\n    MaxColsAtCompileTime = Dynamic,\n    Flags = _Options | NestByRefBit | LvalueBit | CompressedAccessBit,\n    SupportedAccessPatterns = InnerRandomAccessPattern\n  };\n};\n\ntemplate<typename _Scalar, int _Options, typename _Index, int DiagIndex>\nstruct traits<Diagonal<SparseMatrix<_Scalar, _Options, _Index>, DiagIndex> >\n{\n  typedef SparseMatrix<_Scalar, _Options, _Index> MatrixType;\n  typedef typename ref_selector<MatrixType>::type MatrixTypeNested;\n  typedef typename remove_reference<MatrixTypeNested>::type _MatrixTypeNested;\n\n  typedef _Scalar Scalar;\n  typedef Dense StorageKind;\n  typedef _Index StorageIndex;\n  typedef MatrixXpr XprKind;\n\n  enum {\n    RowsAtCompileTime = Dynamic,\n    ColsAtCompileTime = 1,\n    MaxRowsAtCompileTime = Dynamic,\n    MaxColsAtCompileTime = 1,\n    Flags = LvalueBit\n  };\n};\n\ntemplate<typename _Scalar, int _Options, typename _Index, int DiagIndex>\nstruct traits<Diagonal<const SparseMatrix<_Scalar, _Options, _Index>, DiagIndex> >\n : public traits<Diagonal<SparseMatrix<_Scalar, _Options, _Index>, DiagIndex> >\n{\n  enum {\n    Flags = 0\n  };\n};\n\n} // end namespace internal\n\ntemplate<typename _Scalar, int _Options, typename _Index>\nclass SparseMatrix\n  : public SparseCompressedBase<SparseMatrix<_Scalar, _Options, _Index> >\n{\n    typedef SparseCompressedBase<SparseMatrix> Base;\n    using Base::convert_index;\n    friend class SparseVector<_Scalar,0,_Index>;\n  public:\n    using Base::isCompressed;\n    using Base::nonZeros;\n    EIGEN_SPARSE_PUBLIC_INTERFACE(SparseMatrix)\n    using Base::operator+=;\n    using Base::operator-=;\n\n    typedef MappedSparseMatrix<Scalar,Flags> Map;\n    typedef Diagonal<SparseMatrix> DiagonalReturnType;\n    typedef Diagonal<const SparseMatrix> ConstDiagonalReturnType;\n    typedef typename Base::InnerIterator InnerIterator;\n    typedef typename Base::ReverseInnerIterator ReverseInnerIterator;\n    \n\n    using Base::IsRowMajor;\n    typedef internal::CompressedStorage<Scalar,StorageIndex> Storage;\n    enum {\n      Options = _Options\n    };\n\n    typedef typename Base::IndexVector IndexVector;\n    typedef typename Base::ScalarVector ScalarVector;\n  protected:\n    typedef SparseMatrix<Scalar,(Flags&~RowMajorBit)|(IsRowMajor?RowMajorBit:0)> TransposedSparseMatrix;\n\n    Index m_outerSize;\n    Index m_innerSize;\n    StorageIndex* m_outerIndex;\n    StorageIndex* m_innerNonZeros;     // optional, if null then the data is compressed\n    Storage m_data;\n\n  public:\n    \n    /** \\returns the number of rows of the matrix */\n    inline Index rows() const { return IsRowMajor ? m_outerSize : m_innerSize; }\n    /** \\returns the number of columns of the matrix */\n    inline Index cols() const { return IsRowMajor ? m_innerSize : m_outerSize; }\n\n    /** \\returns the number of rows (resp. columns) of the matrix if the storage order column major (resp. row major) */\n    inline Index innerSize() const { return m_innerSize; }\n    /** \\returns the number of columns (resp. rows) of the matrix if the storage order column major (resp. row major) */\n    inline Index outerSize() const { return m_outerSize; }\n    \n    /** \\returns a const pointer to the array of values.\n      * This function is aimed at interoperability with other libraries.\n      * \\sa innerIndexPtr(), outerIndexPtr() */\n    inline const Scalar* valuePtr() const { return m_data.valuePtr(); }\n    /** \\returns a non-const pointer to the array of values.\n      * This function is aimed at interoperability with other libraries.\n      * \\sa innerIndexPtr(), outerIndexPtr() */\n    inline Scalar* valuePtr() { return m_data.valuePtr(); }\n\n    /** \\returns a const pointer to the array of inner indices.\n      * This function is aimed at interoperability with other libraries.\n      * \\sa valuePtr(), outerIndexPtr() */\n    inline const StorageIndex* innerIndexPtr() const { return m_data.indexPtr(); }\n    /** \\returns a non-const pointer to the array of inner indices.\n      * This function is aimed at interoperability with other libraries.\n      * \\sa valuePtr(), outerIndexPtr() */\n    inline StorageIndex* innerIndexPtr() { return m_data.indexPtr(); }\n\n    /** \\returns a const pointer to the array of the starting positions of the inner vectors.\n      * This function is aimed at interoperability with other libraries.\n      * \\sa valuePtr(), innerIndexPtr() */\n    inline const StorageIndex* outerIndexPtr() const { return m_outerIndex; }\n    /** \\returns a non-const pointer to the array of the starting positions of the inner vectors.\n      * This function is aimed at interoperability with other libraries.\n      * \\sa valuePtr(), innerIndexPtr() */\n    inline StorageIndex* outerIndexPtr() { return m_outerIndex; }\n\n    /** \\returns a const pointer to the array of the number of non zeros of the inner vectors.\n      * This function is aimed at interoperability with other libraries.\n      * \\warning it returns the null pointer 0 in compressed mode */\n    inline const StorageIndex* innerNonZeroPtr() const { return m_innerNonZeros; }\n    /** \\returns a non-const pointer to the array of the number of non zeros of the inner vectors.\n      * This function is aimed at interoperability with other libraries.\n      * \\warning it returns the null pointer 0 in compressed mode */\n    inline StorageIndex* innerNonZeroPtr() { return m_innerNonZeros; }\n\n    /** \\internal */\n    inline Storage& data() { return m_data; }\n    /** \\internal */\n    inline const Storage& data() const { return m_data; }\n\n    /** \\returns the value of the matrix at position \\a i, \\a j\n      * This function returns Scalar(0) if the element is an explicit \\em zero */\n    inline Scalar coeff(Index row, Index col) const\n    {\n      eigen_assert(row>=0 && row<rows() && col>=0 && col<cols());\n      \n      const Index outer = IsRowMajor ? row : col;\n      const Index inner = IsRowMajor ? col : row;\n      Index end = m_innerNonZeros ? m_outerIndex[outer] + m_innerNonZeros[outer] : m_outerIndex[outer+1];\n      return m_data.atInRange(m_outerIndex[outer], end, StorageIndex(inner));\n    }\n\n    /** \\returns a non-const reference to the value of the matrix at position \\a i, \\a j\n      *\n      * If the element does not exist then it is inserted via the insert(Index,Index) function\n      * which itself turns the matrix into a non compressed form if that was not the case.\n      *\n      * This is a O(log(nnz_j)) operation (binary search) plus the cost of insert(Index,Index)\n      * function if the element does not already exist.\n      */\n    inline Scalar& coeffRef(Index row, Index col)\n    {\n      eigen_assert(row>=0 && row<rows() && col>=0 && col<cols());\n      \n      const Index outer = IsRowMajor ? row : col;\n      const Index inner = IsRowMajor ? col : row;\n\n      Index start = m_outerIndex[outer];\n      Index end = m_innerNonZeros ? m_outerIndex[outer] + m_innerNonZeros[outer] : m_outerIndex[outer+1];\n      eigen_assert(end>=start && \"you probably called coeffRef on a non finalized matrix\");\n      if(end<=start)\n        return insert(row,col);\n      const Index p = m_data.searchLowerIndex(start,end-1,StorageIndex(inner));\n      if((p<end) && (m_data.index(p)==inner))\n        return m_data.value(p);\n      else\n        return insert(row,col);\n    }\n\n    /** \\returns a reference to a novel non zero coefficient with coordinates \\a row x \\a col.\n      * The non zero coefficient must \\b not already exist.\n      *\n      * If the matrix \\c *this is in compressed mode, then \\c *this is turned into uncompressed\n      * mode while reserving room for 2 x this->innerSize() non zeros if reserve(Index) has not been called earlier.\n      * In this case, the insertion procedure is optimized for a \\e sequential insertion mode where elements are assumed to be\n      * inserted by increasing outer-indices.\n      * \n      * If that's not the case, then it is strongly recommended to either use a triplet-list to assemble the matrix, or to first\n      * call reserve(const SizesType &) to reserve the appropriate number of non-zero elements per inner vector.\n      *\n      * Assuming memory has been appropriately reserved, this function performs a sorted insertion in O(1)\n      * if the elements of each inner vector are inserted in increasing inner index order, and in O(nnz_j) for a random insertion.\n      *\n      */\n    Scalar& insert(Index row, Index col);\n\n  public:\n\n    /** Removes all non zeros but keep allocated memory\n      *\n      * This function does not free the currently allocated memory. To release as much as memory as possible,\n      * call \\code mat.data().squeeze(); \\endcode after resizing it.\n      * \n      * \\sa resize(Index,Index), data()\n      */\n    inline void setZero()\n    {\n      m_data.clear();\n      memset(m_outerIndex, 0, (m_outerSize+1)*sizeof(StorageIndex));\n      if(m_innerNonZeros)\n        memset(m_innerNonZeros, 0, (m_outerSize)*sizeof(StorageIndex));\n    }\n\n    /** Preallocates \\a reserveSize non zeros.\n      *\n      * Precondition: the matrix must be in compressed mode. */\n    inline void reserve(Index reserveSize)\n    {\n      eigen_assert(isCompressed() && \"This function does not make sense in non compressed mode.\");\n      m_data.reserve(reserveSize);\n    }\n    \n    #ifdef EIGEN_PARSED_BY_DOXYGEN\n    /** Preallocates \\a reserveSize[\\c j] non zeros for each column (resp. row) \\c j.\n      *\n      * This function turns the matrix in non-compressed mode.\n      * \n      * The type \\c SizesType must expose the following interface:\n        \\code\n        typedef value_type;\n        const value_type& operator[](i) const;\n        \\endcode\n      * for \\c i in the [0,this->outerSize()[ range.\n      * Typical choices include std::vector<int>, Eigen::VectorXi, Eigen::VectorXi::Constant, etc.\n      */\n    template<class SizesType>\n    inline void reserve(const SizesType& reserveSizes);\n    #else\n    template<class SizesType>\n    inline void reserve(const SizesType& reserveSizes, const typename SizesType::value_type& enableif =\n    #if (!EIGEN_COMP_MSVC) || (EIGEN_COMP_MSVC>=1500) // MSVC 2005 fails to compile with this typename\n        typename\n    #endif\n        SizesType::value_type())\n    {\n      EIGEN_UNUSED_VARIABLE(enableif);\n      reserveInnerVectors(reserveSizes);\n    }\n    #endif // EIGEN_PARSED_BY_DOXYGEN\n  protected:\n    template<class SizesType>\n    inline void reserveInnerVectors(const SizesType& reserveSizes)\n    {\n      if(isCompressed())\n      {\n        Index totalReserveSize = 0;\n        // turn the matrix into non-compressed mode\n        m_innerNonZeros = static_cast<StorageIndex*>(std::malloc(m_outerSize * sizeof(StorageIndex)));\n        if (!m_innerNonZeros) internal::throw_std_bad_alloc();\n        \n        // temporarily use m_innerSizes to hold the new starting points.\n        StorageIndex* newOuterIndex = m_innerNonZeros;\n        \n        StorageIndex count = 0;\n        for(Index j=0; j<m_outerSize; ++j)\n        {\n          newOuterIndex[j] = count;\n          count += reserveSizes[j] + (m_outerIndex[j+1]-m_outerIndex[j]);\n          totalReserveSize += reserveSizes[j];\n        }\n        m_data.reserve(totalReserveSize);\n        StorageIndex previousOuterIndex = m_outerIndex[m_outerSize];\n        for(Index j=m_outerSize-1; j>=0; --j)\n        {\n          StorageIndex innerNNZ = previousOuterIndex - m_outerIndex[j];\n          for(Index i=innerNNZ-1; i>=0; --i)\n          {\n            m_data.index(newOuterIndex[j]+i) = m_data.index(m_outerIndex[j]+i);\n            m_data.value(newOuterIndex[j]+i) = m_data.value(m_outerIndex[j]+i);\n          }\n          previousOuterIndex = m_outerIndex[j];\n          m_outerIndex[j] = newOuterIndex[j];\n          m_innerNonZeros[j] = innerNNZ;\n        }\n        m_outerIndex[m_outerSize] = m_outerIndex[m_outerSize-1] + m_innerNonZeros[m_outerSize-1] + reserveSizes[m_outerSize-1];\n        \n        m_data.resize(m_outerIndex[m_outerSize]);\n      }\n      else\n      {\n        StorageIndex* newOuterIndex = static_cast<StorageIndex*>(std::malloc((m_outerSize+1)*sizeof(StorageIndex)));\n        if (!newOuterIndex) internal::throw_std_bad_alloc();\n        \n        StorageIndex count = 0;\n        for(Index j=0; j<m_outerSize; ++j)\n        {\n          newOuterIndex[j] = count;\n          StorageIndex alreadyReserved = (m_outerIndex[j+1]-m_outerIndex[j]) - m_innerNonZeros[j];\n          StorageIndex toReserve = std::max<StorageIndex>(reserveSizes[j], alreadyReserved);\n          count += toReserve + m_innerNonZeros[j];\n        }\n        newOuterIndex[m_outerSize] = count;\n        \n        m_data.resize(count);\n        for(Index j=m_outerSize-1; j>=0; --j)\n        {\n          Index offset = newOuterIndex[j] - m_outerIndex[j];\n          if(offset>0)\n          {\n            StorageIndex innerNNZ = m_innerNonZeros[j];\n            for(Index i=innerNNZ-1; i>=0; --i)\n            {\n              m_data.index(newOuterIndex[j]+i) = m_data.index(m_outerIndex[j]+i);\n              m_data.value(newOuterIndex[j]+i) = m_data.value(m_outerIndex[j]+i);\n            }\n          }\n        }\n        \n        std::swap(m_outerIndex, newOuterIndex);\n        std::free(newOuterIndex);\n      }\n      \n    }\n  public:\n\n    //--- low level purely coherent filling ---\n\n    /** \\internal\n      * \\returns a reference to the non zero coefficient at position \\a row, \\a col assuming that:\n      * - the nonzero does not already exist\n      * - the new coefficient is the last one according to the storage order\n      *\n      * Before filling a given inner vector you must call the statVec(Index) function.\n      *\n      * After an insertion session, you should call the finalize() function.\n      *\n      * \\sa insert, insertBackByOuterInner, startVec */\n    inline Scalar& insertBack(Index row, Index col)\n    {\n      return insertBackByOuterInner(IsRowMajor?row:col, IsRowMajor?col:row);\n    }\n\n    /** \\internal\n      * \\sa insertBack, startVec */\n    inline Scalar& insertBackByOuterInner(Index outer, Index inner)\n    {\n      eigen_assert(Index(m_outerIndex[outer+1]) == m_data.size() && \"Invalid ordered insertion (invalid outer index)\");\n      eigen_assert( (m_outerIndex[outer+1]-m_outerIndex[outer]==0 || m_data.index(m_data.size()-1)<inner) && \"Invalid ordered insertion (invalid inner index)\");\n      Index p = m_outerIndex[outer+1];\n      ++m_outerIndex[outer+1];\n      m_data.append(Scalar(0), inner);\n      return m_data.value(p);\n    }\n\n    /** \\internal\n      * \\warning use it only if you know what you are doing */\n    inline Scalar& insertBackByOuterInnerUnordered(Index outer, Index inner)\n    {\n      Index p = m_outerIndex[outer+1];\n      ++m_outerIndex[outer+1];\n      m_data.append(Scalar(0), inner);\n      return m_data.value(p);\n    }\n\n    /** \\internal\n      * \\sa insertBack, insertBackByOuterInner */\n    inline void startVec(Index outer)\n    {\n      eigen_assert(m_outerIndex[outer]==Index(m_data.size()) && \"You must call startVec for each inner vector sequentially\");\n      eigen_assert(m_outerIndex[outer+1]==0 && \"You must call startVec for each inner vector sequentially\");\n      m_outerIndex[outer+1] = m_outerIndex[outer];\n    }\n\n    /** \\internal\n      * Must be called after inserting a set of non zero entries using the low level compressed API.\n      */\n    inline void finalize()\n    {\n      if(isCompressed())\n      {\n        StorageIndex size = internal::convert_index<StorageIndex>(m_data.size());\n        Index i = m_outerSize;\n        // find the last filled column\n        while (i>=0 && m_outerIndex[i]==0)\n          --i;\n        ++i;\n        while (i<=m_outerSize)\n        {\n          m_outerIndex[i] = size;\n          ++i;\n        }\n      }\n    }\n\n    //---\n\n    template<typename InputIterators>\n    void setFromTriplets(const InputIterators& begin, const InputIterators& end);\n\n    template<typename InputIterators,typename DupFunctor>\n    void setFromTriplets(const InputIterators& begin, const InputIterators& end, DupFunctor dup_func);\n\n    void sumupDuplicates() { collapseDuplicates(internal::scalar_sum_op<Scalar,Scalar>()); }\n\n    template<typename DupFunctor>\n    void collapseDuplicates(DupFunctor dup_func = DupFunctor());\n\n    //---\n    \n    /** \\internal\n      * same as insert(Index,Index) except that the indices are given relative to the storage order */\n    Scalar& insertByOuterInner(Index j, Index i)\n    {\n      return insert(IsRowMajor ? j : i, IsRowMajor ? i : j);\n    }\n\n    /** Turns the matrix into the \\em compressed format.\n      */\n    void makeCompressed()\n    {\n      if(isCompressed())\n        return;\n      \n      eigen_internal_assert(m_outerIndex!=0 && m_outerSize>0);\n      \n      Index oldStart = m_outerIndex[1];\n      m_outerIndex[1] = m_innerNonZeros[0];\n      for(Index j=1; j<m_outerSize; ++j)\n      {\n        Index nextOldStart = m_outerIndex[j+1];\n        Index offset = oldStart - m_outerIndex[j];\n        if(offset>0)\n        {\n          for(Index k=0; k<m_innerNonZeros[j]; ++k)\n          {\n            m_data.index(m_outerIndex[j]+k) = m_data.index(oldStart+k);\n            m_data.value(m_outerIndex[j]+k) = m_data.value(oldStart+k);\n          }\n        }\n        m_outerIndex[j+1] = m_outerIndex[j] + m_innerNonZeros[j];\n        oldStart = nextOldStart;\n      }\n      std::free(m_innerNonZeros);\n      m_innerNonZeros = 0;\n      m_data.resize(m_outerIndex[m_outerSize]);\n      m_data.squeeze();\n    }\n\n    /** Turns the matrix into the uncompressed mode */\n    void uncompress()\n    {\n      if(m_innerNonZeros != 0)\n        return; \n      m_innerNonZeros = static_cast<StorageIndex*>(std::malloc(m_outerSize * sizeof(StorageIndex)));\n      for (Index i = 0; i < m_outerSize; i++)\n      {\n        m_innerNonZeros[i] = m_outerIndex[i+1] - m_outerIndex[i]; \n      }\n    }\n    \n    /** Suppresses all nonzeros which are \\b much \\b smaller \\b than \\a reference under the tolerence \\a epsilon */\n    void prune(const Scalar& reference, const RealScalar& epsilon = NumTraits<RealScalar>::dummy_precision())\n    {\n      prune(default_prunning_func(reference,epsilon));\n    }\n    \n    /** Turns the matrix into compressed format, and suppresses all nonzeros which do not satisfy the predicate \\a keep.\n      * The functor type \\a KeepFunc must implement the following function:\n      * \\code\n      * bool operator() (const Index& row, const Index& col, const Scalar& value) const;\n      * \\endcode\n      * \\sa prune(Scalar,RealScalar)\n      */\n    template<typename KeepFunc>\n    void prune(const KeepFunc& keep = KeepFunc())\n    {\n      // TODO optimize the uncompressed mode to avoid moving and allocating the data twice\n      makeCompressed();\n\n      StorageIndex k = 0;\n      for(Index j=0; j<m_outerSize; ++j)\n      {\n        Index previousStart = m_outerIndex[j];\n        m_outerIndex[j] = k;\n        Index end = m_outerIndex[j+1];\n        for(Index i=previousStart; i<end; ++i)\n        {\n          if(keep(IsRowMajor?j:m_data.index(i), IsRowMajor?m_data.index(i):j, m_data.value(i)))\n          {\n            m_data.value(k) = m_data.value(i);\n            m_data.index(k) = m_data.index(i);\n            ++k;\n          }\n        }\n      }\n      m_outerIndex[m_outerSize] = k;\n      m_data.resize(k,0);\n    }\n\n    /** Resizes the matrix to a \\a rows x \\a cols matrix leaving old values untouched.\n      *\n      * If the sizes of the matrix are decreased, then the matrix is turned to \\b uncompressed-mode\n      * and the storage of the out of bounds coefficients is kept and reserved.\n      * Call makeCompressed() to pack the entries and squeeze extra memory.\n      *\n      * \\sa reserve(), setZero(), makeCompressed()\n      */\n    void conservativeResize(Index rows, Index cols) \n    {\n      // No change\n      if (this->rows() == rows && this->cols() == cols) return;\n      \n      // If one dimension is null, then there is nothing to be preserved\n      if(rows==0 || cols==0) return resize(rows,cols);\n\n      Index innerChange = IsRowMajor ? cols - this->cols() : rows - this->rows();\n      Index outerChange = IsRowMajor ? rows - this->rows() : cols - this->cols();\n      StorageIndex newInnerSize = convert_index(IsRowMajor ? cols : rows);\n\n      // Deals with inner non zeros\n      if (m_innerNonZeros)\n      {\n        // Resize m_innerNonZeros\n        StorageIndex *newInnerNonZeros = static_cast<StorageIndex*>(std::realloc(m_innerNonZeros, (m_outerSize + outerChange) * sizeof(StorageIndex)));\n        if (!newInnerNonZeros) internal::throw_std_bad_alloc();\n        m_innerNonZeros = newInnerNonZeros;\n        \n        for(Index i=m_outerSize; i<m_outerSize+outerChange; i++)          \n          m_innerNonZeros[i] = 0;\n      } \n      else if (innerChange < 0) \n      {\n        // Inner size decreased: allocate a new m_innerNonZeros\n        m_innerNonZeros = static_cast<StorageIndex*>(std::malloc((m_outerSize+outerChange+1) * sizeof(StorageIndex)));\n        if (!m_innerNonZeros) internal::throw_std_bad_alloc();\n        for(Index i = 0; i < m_outerSize; i++)\n          m_innerNonZeros[i] = m_outerIndex[i+1] - m_outerIndex[i];\n      }\n      \n      // Change the m_innerNonZeros in case of a decrease of inner size\n      if (m_innerNonZeros && innerChange < 0)\n      {\n        for(Index i = 0; i < m_outerSize + (std::min)(outerChange, Index(0)); i++)\n        {\n          StorageIndex &n = m_innerNonZeros[i];\n          StorageIndex start = m_outerIndex[i];\n          while (n > 0 && m_data.index(start+n-1) >= newInnerSize) --n; \n        }\n      }\n      \n      m_innerSize = newInnerSize;\n\n      // Re-allocate outer index structure if necessary\n      if (outerChange == 0)\n        return;\n          \n      StorageIndex *newOuterIndex = static_cast<StorageIndex*>(std::realloc(m_outerIndex, (m_outerSize + outerChange + 1) * sizeof(StorageIndex)));\n      if (!newOuterIndex) internal::throw_std_bad_alloc();\n      m_outerIndex = newOuterIndex;\n      if (outerChange > 0)\n      {\n        StorageIndex last = m_outerSize == 0 ? 0 : m_outerIndex[m_outerSize];\n        for(Index i=m_outerSize; i<m_outerSize+outerChange+1; i++)          \n          m_outerIndex[i] = last; \n      }\n      m_outerSize += outerChange;\n    }\n    \n    /** Resizes the matrix to a \\a rows x \\a cols matrix and initializes it to zero.\n      * \n      * This function does not free the currently allocated memory. To release as much as memory as possible,\n      * call \\code mat.data().squeeze(); \\endcode after resizing it.\n      * \n      * \\sa reserve(), setZero()\n      */\n    void resize(Index rows, Index cols)\n    {\n      const Index outerSize = IsRowMajor ? rows : cols;\n      m_innerSize = IsRowMajor ? cols : rows;\n      m_data.clear();\n      if (m_outerSize != outerSize || m_outerSize==0)\n      {\n        std::free(m_outerIndex);\n        m_outerIndex = static_cast<StorageIndex*>(std::malloc((outerSize + 1) * sizeof(StorageIndex)));\n        if (!m_outerIndex) internal::throw_std_bad_alloc();\n        \n        m_outerSize = outerSize;\n      }\n      if(m_innerNonZeros)\n      {\n        std::free(m_innerNonZeros);\n        m_innerNonZeros = 0;\n      }\n      memset(m_outerIndex, 0, (m_outerSize+1)*sizeof(StorageIndex));\n    }\n\n    /** \\internal\n      * Resize the nonzero vector to \\a size */\n    void resizeNonZeros(Index size)\n    {\n      m_data.resize(size);\n    }\n\n    /** \\returns a const expression of the diagonal coefficients. */\n    const ConstDiagonalReturnType diagonal() const { return ConstDiagonalReturnType(*this); }\n    \n    /** \\returns a read-write expression of the diagonal coefficients.\n      * \\warning If the diagonal entries are written, then all diagonal\n      * entries \\b must already exist, otherwise an assertion will be raised.\n      */\n    DiagonalReturnType diagonal() { return DiagonalReturnType(*this); }\n\n    /** Default constructor yielding an empty \\c 0 \\c x \\c 0 matrix */\n    inline SparseMatrix()\n      : m_outerSize(-1), m_innerSize(0), m_outerIndex(0), m_innerNonZeros(0)\n    {\n      check_template_parameters();\n      resize(0, 0);\n    }\n\n    /** Constructs a \\a rows \\c x \\a cols empty matrix */\n    inline SparseMatrix(Index rows, Index cols)\n      : m_outerSize(0), m_innerSize(0), m_outerIndex(0), m_innerNonZeros(0)\n    {\n      check_template_parameters();\n      resize(rows, cols);\n    }\n\n    /** Constructs a sparse matrix from the sparse expression \\a other */\n    template<typename OtherDerived>\n    inline SparseMatrix(const SparseMatrixBase<OtherDerived>& other)\n      : m_outerSize(0), m_innerSize(0), m_outerIndex(0), m_innerNonZeros(0)\n    {\n      EIGEN_STATIC_ASSERT((internal::is_same<Scalar, typename OtherDerived::Scalar>::value),\n        YOU_MIXED_DIFFERENT_NUMERIC_TYPES__YOU_NEED_TO_USE_THE_CAST_METHOD_OF_MATRIXBASE_TO_CAST_NUMERIC_TYPES_EXPLICITLY)\n      check_template_parameters();\n      const bool needToTranspose = (Flags & RowMajorBit) != (internal::evaluator<OtherDerived>::Flags & RowMajorBit);\n      if (needToTranspose)\n        *this = other.derived();\n      else\n      {\n        #ifdef EIGEN_SPARSE_CREATE_TEMPORARY_PLUGIN\n          EIGEN_SPARSE_CREATE_TEMPORARY_PLUGIN\n        #endif\n        internal::call_assignment_no_alias(*this, other.derived());\n      }\n    }\n    \n    /** Constructs a sparse matrix from the sparse selfadjoint view \\a other */\n    template<typename OtherDerived, unsigned int UpLo>\n    inline SparseMatrix(const SparseSelfAdjointView<OtherDerived, UpLo>& other)\n      : m_outerSize(0), m_innerSize(0), m_outerIndex(0), m_innerNonZeros(0)\n    {\n      check_template_parameters();\n      Base::operator=(other);\n    }\n\n    /** Copy constructor (it performs a deep copy) */\n    inline SparseMatrix(const SparseMatrix& other)\n      : Base(), m_outerSize(0), m_innerSize(0), m_outerIndex(0), m_innerNonZeros(0)\n    {\n      check_template_parameters();\n      *this = other.derived();\n    }\n\n    /** \\brief Copy constructor with in-place evaluation */\n    template<typename OtherDerived>\n    SparseMatrix(const ReturnByValue<OtherDerived>& other)\n      : Base(), m_outerSize(0), m_innerSize(0), m_outerIndex(0), m_innerNonZeros(0)\n    {\n      check_template_parameters();\n      initAssignment(other);\n      other.evalTo(*this);\n    }\n    \n    /** \\brief Copy constructor with in-place evaluation */\n    template<typename OtherDerived>\n    explicit SparseMatrix(const DiagonalBase<OtherDerived>& other)\n      : Base(), m_outerSize(0), m_innerSize(0), m_outerIndex(0), m_innerNonZeros(0)\n    {\n      check_template_parameters();\n      *this = other.derived();\n    }\n\n    /** Swaps the content of two sparse matrices of the same type.\n      * This is a fast operation that simply swaps the underlying pointers and parameters. */\n    inline void swap(SparseMatrix& other)\n    {\n      //EIGEN_DBG_SPARSE(std::cout << \"SparseMatrix:: swap\\n\");\n      std::swap(m_outerIndex, other.m_outerIndex);\n      std::swap(m_innerSize, other.m_innerSize);\n      std::swap(m_outerSize, other.m_outerSize);\n      std::swap(m_innerNonZeros, other.m_innerNonZeros);\n      m_data.swap(other.m_data);\n    }\n\n    /** Sets *this to the identity matrix.\n      * This function also turns the matrix into compressed mode, and drop any reserved memory. */\n    inline void setIdentity()\n    {\n      eigen_assert(rows() == cols() && \"ONLY FOR SQUARED MATRICES\");\n      this->m_data.resize(rows());\n      Eigen::Map<IndexVector>(this->m_data.indexPtr(), rows()).setLinSpaced(0, StorageIndex(rows()-1));\n      Eigen::Map<ScalarVector>(this->m_data.valuePtr(), rows()).setOnes();\n      Eigen::Map<IndexVector>(this->m_outerIndex, rows()+1).setLinSpaced(0, StorageIndex(rows()));\n      std::free(m_innerNonZeros);\n      m_innerNonZeros = 0;\n    }\n    inline SparseMatrix& operator=(const SparseMatrix& other)\n    {\n      if (other.isRValue())\n      {\n        swap(other.const_cast_derived());\n      }\n      else if(this!=&other)\n      {\n        #ifdef EIGEN_SPARSE_CREATE_TEMPORARY_PLUGIN\n          EIGEN_SPARSE_CREATE_TEMPORARY_PLUGIN\n        #endif\n        initAssignment(other);\n        if(other.isCompressed())\n        {\n          internal::smart_copy(other.m_outerIndex, other.m_outerIndex + m_outerSize + 1, m_outerIndex);\n          m_data = other.m_data;\n        }\n        else\n        {\n          Base::operator=(other);\n        }\n      }\n      return *this;\n    }\n\n#ifndef EIGEN_PARSED_BY_DOXYGEN\n    template<typename OtherDerived>\n    inline SparseMatrix& operator=(const EigenBase<OtherDerived>& other)\n    { return Base::operator=(other.derived()); }\n#endif // EIGEN_PARSED_BY_DOXYGEN\n\n    template<typename OtherDerived>\n    EIGEN_DONT_INLINE SparseMatrix& operator=(const SparseMatrixBase<OtherDerived>& other);\n\n    friend std::ostream & operator << (std::ostream & s, const SparseMatrix& m)\n    {\n      EIGEN_DBG_SPARSE(\n        s << \"Nonzero entries:\\n\";\n        if(m.isCompressed())\n        {\n          for (Index i=0; i<m.nonZeros(); ++i)\n            s << \"(\" << m.m_data.value(i) << \",\" << m.m_data.index(i) << \") \";\n        }\n        else\n        {\n          for (Index i=0; i<m.outerSize(); ++i)\n          {\n            Index p = m.m_outerIndex[i];\n            Index pe = m.m_outerIndex[i]+m.m_innerNonZeros[i];\n            Index k=p;\n            for (; k<pe; ++k) {\n              s << \"(\" << m.m_data.value(k) << \",\" << m.m_data.index(k) << \") \";\n            }\n            for (; k<m.m_outerIndex[i+1]; ++k) {\n              s << \"(_,_) \";\n            }\n          }\n        }\n        s << std::endl;\n        s << std::endl;\n        s << \"Outer pointers:\\n\";\n        for (Index i=0; i<m.outerSize(); ++i) {\n          s << m.m_outerIndex[i] << \" \";\n        }\n        s << \" $\" << std::endl;\n        if(!m.isCompressed())\n        {\n          s << \"Inner non zeros:\\n\";\n          for (Index i=0; i<m.outerSize(); ++i) {\n            s << m.m_innerNonZeros[i] << \" \";\n          }\n          s << \" $\" << std::endl;\n        }\n        s << std::endl;\n      );\n      s << static_cast<const SparseMatrixBase<SparseMatrix>&>(m);\n      return s;\n    }\n\n    /** Destructor */\n    inline ~SparseMatrix()\n    {\n      std::free(m_outerIndex);\n      std::free(m_innerNonZeros);\n    }\n\n    /** Overloaded for performance */\n    Scalar sum() const;\n    \n#   ifdef EIGEN_SPARSEMATRIX_PLUGIN\n#     include EIGEN_SPARSEMATRIX_PLUGIN\n#   endif\n\nprotected:\n\n    template<typename Other>\n    void initAssignment(const Other& other)\n    {\n      resize(other.rows(), other.cols());\n      if(m_innerNonZeros)\n      {\n        std::free(m_innerNonZeros);\n        m_innerNonZeros = 0;\n      }\n    }\n\n    /** \\internal\n      * \\sa insert(Index,Index) */\n    EIGEN_DONT_INLINE Scalar& insertCompressed(Index row, Index col);\n\n    /** \\internal\n      * A vector object that is equal to 0 everywhere but v at the position i */\n    class SingletonVector\n    {\n        StorageIndex m_index;\n        StorageIndex m_value;\n      public:\n        typedef StorageIndex value_type;\n        SingletonVector(Index i, Index v)\n          : m_index(convert_index(i)), m_value(convert_index(v))\n        {}\n\n        StorageIndex operator[](Index i) const { return i==m_index ? m_value : 0; }\n    };\n\n    /** \\internal\n      * \\sa insert(Index,Index) */\n    EIGEN_DONT_INLINE Scalar& insertUncompressed(Index row, Index col);\n\npublic:\n    /** \\internal\n      * \\sa insert(Index,Index) */\n    EIGEN_STRONG_INLINE Scalar& insertBackUncompressed(Index row, Index col)\n    {\n      const Index outer = IsRowMajor ? row : col;\n      const Index inner = IsRowMajor ? col : row;\n\n      eigen_assert(!isCompressed());\n      eigen_assert(m_innerNonZeros[outer]<=(m_outerIndex[outer+1] - m_outerIndex[outer]));\n\n      Index p = m_outerIndex[outer] + m_innerNonZeros[outer]++;\n      m_data.index(p) = convert_index(inner);\n      return (m_data.value(p) = 0);\n    }\n\nprivate:\n  static void check_template_parameters()\n  {\n    EIGEN_STATIC_ASSERT(NumTraits<StorageIndex>::IsSigned,THE_INDEX_TYPE_MUST_BE_A_SIGNED_TYPE);\n    EIGEN_STATIC_ASSERT((Options&(ColMajor|RowMajor))==Options,INVALID_MATRIX_TEMPLATE_PARAMETERS);\n  }\n\n  struct default_prunning_func {\n    default_prunning_func(const Scalar& ref, const RealScalar& eps) : reference(ref), epsilon(eps) {}\n    inline bool operator() (const Index&, const Index&, const Scalar& value) const\n    {\n      return !internal::isMuchSmallerThan(value, reference, epsilon);\n    }\n    Scalar reference;\n    RealScalar epsilon;\n  };\n};\n\nnamespace internal {\n\ntemplate<typename InputIterator, typename SparseMatrixType, typename DupFunctor>\nvoid set_from_triplets(const InputIterator& begin, const InputIterator& end, SparseMatrixType& mat, DupFunctor dup_func)\n{\n  enum { IsRowMajor = SparseMatrixType::IsRowMajor };\n  typedef typename SparseMatrixType::Scalar Scalar;\n  typedef typename SparseMatrixType::StorageIndex StorageIndex;\n  SparseMatrix<Scalar,IsRowMajor?ColMajor:RowMajor,StorageIndex> trMat(mat.rows(),mat.cols());\n\n  if(begin!=end)\n  {\n    // pass 1: count the nnz per inner-vector\n    typename SparseMatrixType::IndexVector wi(trMat.outerSize());\n    wi.setZero();\n    for(InputIterator it(begin); it!=end; ++it)\n    {\n      eigen_assert(it->row()>=0 && it->row()<mat.rows() && it->col()>=0 && it->col()<mat.cols());\n      wi(IsRowMajor ? it->col() : it->row())++;\n    }\n\n    // pass 2: insert all the elements into trMat\n    trMat.reserve(wi);\n    for(InputIterator it(begin); it!=end; ++it)\n      trMat.insertBackUncompressed(it->row(),it->col()) = it->value();\n\n    // pass 3:\n    trMat.collapseDuplicates(dup_func);\n  }\n\n  // pass 4: transposed copy -> implicit sorting\n  mat = trMat;\n}\n\n}\n\n\n/** Fill the matrix \\c *this with the list of \\em triplets defined by the iterator range \\a begin - \\a end.\n  *\n  * A \\em triplet is a tuple (i,j,value) defining a non-zero element.\n  * The input list of triplets does not have to be sorted, and can contains duplicated elements.\n  * In any case, the result is a \\b sorted and \\b compressed sparse matrix where the duplicates have been summed up.\n  * This is a \\em O(n) operation, with \\em n the number of triplet elements.\n  * The initial contents of \\c *this is destroyed.\n  * The matrix \\c *this must be properly resized beforehand using the SparseMatrix(Index,Index) constructor,\n  * or the resize(Index,Index) method. The sizes are not extracted from the triplet list.\n  *\n  * The \\a InputIterators value_type must provide the following interface:\n  * \\code\n  * Scalar value() const; // the value\n  * Scalar row() const;   // the row index i\n  * Scalar col() const;   // the column index j\n  * \\endcode\n  * See for instance the Eigen::Triplet template class.\n  *\n  * Here is a typical usage example:\n  * \\code\n    typedef Triplet<double> T;\n    std::vector<T> tripletList;\n    triplets.reserve(estimation_of_entries);\n    for(...)\n    {\n      // ...\n      tripletList.push_back(T(i,j,v_ij));\n    }\n    SparseMatrixType m(rows,cols);\n    m.setFromTriplets(tripletList.begin(), tripletList.end());\n    // m is ready to go!\n  * \\endcode\n  *\n  * \\warning The list of triplets is read multiple times (at least twice). Therefore, it is not recommended to define\n  * an abstract iterator over a complex data-structure that would be expensive to evaluate. The triplets should rather\n  * be explicitely stored into a std::vector for instance.\n  */\ntemplate<typename Scalar, int _Options, typename _Index>\ntemplate<typename InputIterators>\nvoid SparseMatrix<Scalar,_Options,_Index>::setFromTriplets(const InputIterators& begin, const InputIterators& end)\n{\n  internal::set_from_triplets<InputIterators, SparseMatrix<Scalar,_Options,_Index> >(begin, end, *this, internal::scalar_sum_op<Scalar,Scalar>());\n}\n\n/** The same as setFromTriplets but when duplicates are met the functor \\a dup_func is applied:\n  * \\code\n  * value = dup_func(OldValue, NewValue)\n  * \\endcode \n  * Here is a C++11 example keeping the latest entry only:\n  * \\code\n  * mat.setFromTriplets(triplets.begin(), triplets.end(), [] (const Scalar&,const Scalar &b) { return b; });\n  * \\endcode\n  */\ntemplate<typename Scalar, int _Options, typename _Index>\ntemplate<typename InputIterators,typename DupFunctor>\nvoid SparseMatrix<Scalar,_Options,_Index>::setFromTriplets(const InputIterators& begin, const InputIterators& end, DupFunctor dup_func)\n{\n  internal::set_from_triplets<InputIterators, SparseMatrix<Scalar,_Options,_Index>, DupFunctor>(begin, end, *this, dup_func);\n}\n\n/** \\internal */\ntemplate<typename Scalar, int _Options, typename _Index>\ntemplate<typename DupFunctor>\nvoid SparseMatrix<Scalar,_Options,_Index>::collapseDuplicates(DupFunctor dup_func)\n{\n  eigen_assert(!isCompressed());\n  // TODO, in practice we should be able to use m_innerNonZeros for that task\n  IndexVector wi(innerSize());\n  wi.fill(-1);\n  StorageIndex count = 0;\n  // for each inner-vector, wi[inner_index] will hold the position of first element into the index/value buffers\n  for(Index j=0; j<outerSize(); ++j)\n  {\n    StorageIndex start   = count;\n    Index oldEnd  = m_outerIndex[j]+m_innerNonZeros[j];\n    for(Index k=m_outerIndex[j]; k<oldEnd; ++k)\n    {\n      Index i = m_data.index(k);\n      if(wi(i)>=start)\n      {\n        // we already meet this entry => accumulate it\n        m_data.value(wi(i)) = dup_func(m_data.value(wi(i)), m_data.value(k));\n      }\n      else\n      {\n        m_data.value(count) = m_data.value(k);\n        m_data.index(count) = m_data.index(k);\n        wi(i) = count;\n        ++count;\n      }\n    }\n    m_outerIndex[j] = start;\n  }\n  m_outerIndex[m_outerSize] = count;\n\n  // turn the matrix into compressed form\n  std::free(m_innerNonZeros);\n  m_innerNonZeros = 0;\n  m_data.resize(m_outerIndex[m_outerSize]);\n}\n\ntemplate<typename Scalar, int _Options, typename _Index>\ntemplate<typename OtherDerived>\nEIGEN_DONT_INLINE SparseMatrix<Scalar,_Options,_Index>& SparseMatrix<Scalar,_Options,_Index>::operator=(const SparseMatrixBase<OtherDerived>& other)\n{\n  EIGEN_STATIC_ASSERT((internal::is_same<Scalar, typename OtherDerived::Scalar>::value),\n        YOU_MIXED_DIFFERENT_NUMERIC_TYPES__YOU_NEED_TO_USE_THE_CAST_METHOD_OF_MATRIXBASE_TO_CAST_NUMERIC_TYPES_EXPLICITLY)\n\n  #ifdef EIGEN_SPARSE_CREATE_TEMPORARY_PLUGIN\n    EIGEN_SPARSE_CREATE_TEMPORARY_PLUGIN\n  #endif\n      \n  const bool needToTranspose = (Flags & RowMajorBit) != (internal::evaluator<OtherDerived>::Flags & RowMajorBit);\n  if (needToTranspose)\n  {\n    #ifdef EIGEN_SPARSE_TRANSPOSED_COPY_PLUGIN\n      EIGEN_SPARSE_TRANSPOSED_COPY_PLUGIN\n    #endif\n    // two passes algorithm:\n    //  1 - compute the number of coeffs per dest inner vector\n    //  2 - do the actual copy/eval\n    // Since each coeff of the rhs has to be evaluated twice, let's evaluate it if needed\n    typedef typename internal::nested_eval<OtherDerived,2,typename internal::plain_matrix_type<OtherDerived>::type >::type OtherCopy;\n    typedef typename internal::remove_all<OtherCopy>::type _OtherCopy;\n    typedef internal::evaluator<_OtherCopy> OtherCopyEval;\n    OtherCopy otherCopy(other.derived());\n    OtherCopyEval otherCopyEval(otherCopy);\n\n    SparseMatrix dest(other.rows(),other.cols());\n    Eigen::Map<IndexVector> (dest.m_outerIndex,dest.outerSize()).setZero();\n\n    // pass 1\n    // FIXME the above copy could be merged with that pass\n    for (Index j=0; j<otherCopy.outerSize(); ++j)\n      for (typename OtherCopyEval::InnerIterator it(otherCopyEval, j); it; ++it)\n        ++dest.m_outerIndex[it.index()];\n\n    // prefix sum\n    StorageIndex count = 0;\n    IndexVector positions(dest.outerSize());\n    for (Index j=0; j<dest.outerSize(); ++j)\n    {\n      StorageIndex tmp = dest.m_outerIndex[j];\n      dest.m_outerIndex[j] = count;\n      positions[j] = count;\n      count += tmp;\n    }\n    dest.m_outerIndex[dest.outerSize()] = count;\n    // alloc\n    dest.m_data.resize(count);\n    // pass 2\n    for (StorageIndex j=0; j<otherCopy.outerSize(); ++j)\n    {\n      for (typename OtherCopyEval::InnerIterator it(otherCopyEval, j); it; ++it)\n      {\n        Index pos = positions[it.index()]++;\n        dest.m_data.index(pos) = j;\n        dest.m_data.value(pos) = it.value();\n      }\n    }\n    this->swap(dest);\n    return *this;\n  }\n  else\n  {\n    if(other.isRValue())\n    {\n      initAssignment(other.derived());\n    }\n    // there is no special optimization\n    return Base::operator=(other.derived());\n  }\n}\n\ntemplate<typename _Scalar, int _Options, typename _Index>\ntypename SparseMatrix<_Scalar,_Options,_Index>::Scalar& SparseMatrix<_Scalar,_Options,_Index>::insert(Index row, Index col)\n{\n  eigen_assert(row>=0 && row<rows() && col>=0 && col<cols());\n  \n  const Index outer = IsRowMajor ? row : col;\n  const Index inner = IsRowMajor ? col : row;\n  \n  if(isCompressed())\n  {\n    if(nonZeros()==0)\n    {\n      // reserve space if not already done\n      if(m_data.allocatedSize()==0)\n        m_data.reserve(2*m_innerSize);\n      \n      // turn the matrix into non-compressed mode\n      m_innerNonZeros = static_cast<StorageIndex*>(std::malloc(m_outerSize * sizeof(StorageIndex)));\n      if(!m_innerNonZeros) internal::throw_std_bad_alloc();\n      \n      memset(m_innerNonZeros, 0, (m_outerSize)*sizeof(StorageIndex));\n      \n      // pack all inner-vectors to the end of the pre-allocated space\n      // and allocate the entire free-space to the first inner-vector\n      StorageIndex end = convert_index(m_data.allocatedSize());\n      for(Index j=1; j<=m_outerSize; ++j)\n        m_outerIndex[j] = end;\n    }\n    else\n    {\n      // turn the matrix into non-compressed mode\n      m_innerNonZeros = static_cast<StorageIndex*>(std::malloc(m_outerSize * sizeof(StorageIndex)));\n      if(!m_innerNonZeros) internal::throw_std_bad_alloc();\n      for(Index j=0; j<m_outerSize; ++j)\n        m_innerNonZeros[j] = m_outerIndex[j+1]-m_outerIndex[j];\n    }\n  }\n  \n  // check whether we can do a fast \"push back\" insertion\n  Index data_end = m_data.allocatedSize();\n  \n  // First case: we are filling a new inner vector which is packed at the end.\n  // We assume that all remaining inner-vectors are also empty and packed to the end.\n  if(m_outerIndex[outer]==data_end)\n  {\n    eigen_internal_assert(m_innerNonZeros[outer]==0);\n    \n    // pack previous empty inner-vectors to end of the used-space\n    // and allocate the entire free-space to the current inner-vector.\n    StorageIndex p = convert_index(m_data.size());\n    Index j = outer;\n    while(j>=0 && m_innerNonZeros[j]==0)\n      m_outerIndex[j--] = p;\n    \n    // push back the new element\n    ++m_innerNonZeros[outer];\n    m_data.append(Scalar(0), inner);\n    \n    // check for reallocation\n    if(data_end != m_data.allocatedSize())\n    {\n      // m_data has been reallocated\n      //  -> move remaining inner-vectors back to the end of the free-space\n      //     so that the entire free-space is allocated to the current inner-vector.\n      eigen_internal_assert(data_end < m_data.allocatedSize());\n      StorageIndex new_end = convert_index(m_data.allocatedSize());\n      for(Index k=outer+1; k<=m_outerSize; ++k)\n        if(m_outerIndex[k]==data_end)\n          m_outerIndex[k] = new_end;\n    }\n    return m_data.value(p);\n  }\n  \n  // Second case: the next inner-vector is packed to the end\n  // and the current inner-vector end match the used-space.\n  if(m_outerIndex[outer+1]==data_end && m_outerIndex[outer]+m_innerNonZeros[outer]==m_data.size())\n  {\n    eigen_internal_assert(outer+1==m_outerSize || m_innerNonZeros[outer+1]==0);\n    \n    // add space for the new element\n    ++m_innerNonZeros[outer];\n    m_data.resize(m_data.size()+1);\n    \n    // check for reallocation\n    if(data_end != m_data.allocatedSize())\n    {\n      // m_data has been reallocated\n      //  -> move remaining inner-vectors back to the end of the free-space\n      //     so that the entire free-space is allocated to the current inner-vector.\n      eigen_internal_assert(data_end < m_data.allocatedSize());\n      StorageIndex new_end = convert_index(m_data.allocatedSize());\n      for(Index k=outer+1; k<=m_outerSize; ++k)\n        if(m_outerIndex[k]==data_end)\n          m_outerIndex[k] = new_end;\n    }\n    \n    // and insert it at the right position (sorted insertion)\n    Index startId = m_outerIndex[outer];\n    Index p = m_outerIndex[outer]+m_innerNonZeros[outer]-1;\n    while ( (p > startId) && (m_data.index(p-1) > inner) )\n    {\n      m_data.index(p) = m_data.index(p-1);\n      m_data.value(p) = m_data.value(p-1);\n      --p;\n    }\n    \n    m_data.index(p) = convert_index(inner);\n    return (m_data.value(p) = 0);\n  }\n  \n  if(m_data.size() != m_data.allocatedSize())\n  {\n    // make sure the matrix is compatible to random un-compressed insertion:\n    m_data.resize(m_data.allocatedSize());\n    this->reserveInnerVectors(Array<StorageIndex,Dynamic,1>::Constant(m_outerSize, 2));\n  }\n  \n  return insertUncompressed(row,col);\n}\n    \ntemplate<typename _Scalar, int _Options, typename _Index>\nEIGEN_DONT_INLINE typename SparseMatrix<_Scalar,_Options,_Index>::Scalar& SparseMatrix<_Scalar,_Options,_Index>::insertUncompressed(Index row, Index col)\n{\n  eigen_assert(!isCompressed());\n\n  const Index outer = IsRowMajor ? row : col;\n  const StorageIndex inner = convert_index(IsRowMajor ? col : row);\n\n  Index room = m_outerIndex[outer+1] - m_outerIndex[outer];\n  StorageIndex innerNNZ = m_innerNonZeros[outer];\n  if(innerNNZ>=room)\n  {\n    // this inner vector is full, we need to reallocate the whole buffer :(\n    reserve(SingletonVector(outer,std::max<StorageIndex>(2,innerNNZ)));\n  }\n\n  Index startId = m_outerIndex[outer];\n  Index p = startId + m_innerNonZeros[outer];\n  while ( (p > startId) && (m_data.index(p-1) > inner) )\n  {\n    m_data.index(p) = m_data.index(p-1);\n    m_data.value(p) = m_data.value(p-1);\n    --p;\n  }\n  eigen_assert((p<=startId || m_data.index(p-1)!=inner) && \"you cannot insert an element that already exists, you must call coeffRef to this end\");\n\n  m_innerNonZeros[outer]++;\n\n  m_data.index(p) = inner;\n  return (m_data.value(p) = 0);\n}\n\ntemplate<typename _Scalar, int _Options, typename _Index>\nEIGEN_DONT_INLINE typename SparseMatrix<_Scalar,_Options,_Index>::Scalar& SparseMatrix<_Scalar,_Options,_Index>::insertCompressed(Index row, Index col)\n{\n  eigen_assert(isCompressed());\n\n  const Index outer = IsRowMajor ? row : col;\n  const Index inner = IsRowMajor ? col : row;\n\n  Index previousOuter = outer;\n  if (m_outerIndex[outer+1]==0)\n  {\n    // we start a new inner vector\n    while (previousOuter>=0 && m_outerIndex[previousOuter]==0)\n    {\n      m_outerIndex[previousOuter] = convert_index(m_data.size());\n      --previousOuter;\n    }\n    m_outerIndex[outer+1] = m_outerIndex[outer];\n  }\n\n  // here we have to handle the tricky case where the outerIndex array\n  // starts with: [ 0 0 0 0 0 1 ...] and we are inserted in, e.g.,\n  // the 2nd inner vector...\n  bool isLastVec = (!(previousOuter==-1 && m_data.size()!=0))\n                && (size_t(m_outerIndex[outer+1]) == m_data.size());\n\n  size_t startId = m_outerIndex[outer];\n  // FIXME let's make sure sizeof(long int) == sizeof(size_t)\n  size_t p = m_outerIndex[outer+1];\n  ++m_outerIndex[outer+1];\n\n  double reallocRatio = 1;\n  if (m_data.allocatedSize()<=m_data.size())\n  {\n    // if there is no preallocated memory, let's reserve a minimum of 32 elements\n    if (m_data.size()==0)\n    {\n      m_data.reserve(32);\n    }\n    else\n    {\n      // we need to reallocate the data, to reduce multiple reallocations\n      // we use a smart resize algorithm based on the current filling ratio\n      // in addition, we use double to avoid integers overflows\n      double nnzEstimate = double(m_outerIndex[outer])*double(m_outerSize)/double(outer+1);\n      reallocRatio = (nnzEstimate-double(m_data.size()))/double(m_data.size());\n      // furthermore we bound the realloc ratio to:\n      //   1) reduce multiple minor realloc when the matrix is almost filled\n      //   2) avoid to allocate too much memory when the matrix is almost empty\n      reallocRatio = (std::min)((std::max)(reallocRatio,1.5),8.);\n    }\n  }\n  m_data.resize(m_data.size()+1,reallocRatio);\n\n  if (!isLastVec)\n  {\n    if (previousOuter==-1)\n    {\n      // oops wrong guess.\n      // let's correct the outer offsets\n      for (Index k=0; k<=(outer+1); ++k)\n        m_outerIndex[k] = 0;\n      Index k=outer+1;\n      while(m_outerIndex[k]==0)\n        m_outerIndex[k++] = 1;\n      while (k<=m_outerSize && m_outerIndex[k]!=0)\n        m_outerIndex[k++]++;\n      p = 0;\n      --k;\n      k = m_outerIndex[k]-1;\n      while (k>0)\n      {\n        m_data.index(k) = m_data.index(k-1);\n        m_data.value(k) = m_data.value(k-1);\n        k--;\n      }\n    }\n    else\n    {\n      // we are not inserting into the last inner vec\n      // update outer indices:\n      Index j = outer+2;\n      while (j<=m_outerSize && m_outerIndex[j]!=0)\n        m_outerIndex[j++]++;\n      --j;\n      // shift data of last vecs:\n      Index k = m_outerIndex[j]-1;\n      while (k>=Index(p))\n      {\n        m_data.index(k) = m_data.index(k-1);\n        m_data.value(k) = m_data.value(k-1);\n        k--;\n      }\n    }\n  }\n\n  while ( (p > startId) && (m_data.index(p-1) > inner) )\n  {\n    m_data.index(p) = m_data.index(p-1);\n    m_data.value(p) = m_data.value(p-1);\n    --p;\n  }\n\n  m_data.index(p) = inner;\n  return (m_data.value(p) = 0);\n}\n\nnamespace internal {\n\ntemplate<typename _Scalar, int _Options, typename _Index>\nstruct evaluator<SparseMatrix<_Scalar,_Options,_Index> >\n  : evaluator<SparseCompressedBase<SparseMatrix<_Scalar,_Options,_Index> > >\n{\n  typedef evaluator<SparseCompressedBase<SparseMatrix<_Scalar,_Options,_Index> > > Base;\n  typedef SparseMatrix<_Scalar,_Options,_Index> SparseMatrixType;\n  evaluator() : Base() {}\n  explicit evaluator(const SparseMatrixType &mat) : Base(mat) {}\n};\n\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_SPARSEMATRIX_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseCore/SparseMatrixBase.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2014 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SPARSEMATRIXBASE_H\n#define EIGEN_SPARSEMATRIXBASE_H\n\nnamespace Eigen { \n\n/** \\ingroup SparseCore_Module\n  *\n  * \\class SparseMatrixBase\n  *\n  * \\brief Base class of any sparse matrices or sparse expressions\n  *\n  * \\tparam Derived is the derived type, e.g. a sparse matrix type, or an expression, etc.\n  *\n  * This class can be extended with the help of the plugin mechanism described on the page\n  * \\ref TopicCustomizing_Plugins by defining the preprocessor symbol \\c EIGEN_SPARSEMATRIXBASE_PLUGIN.\n  */\ntemplate<typename Derived> class SparseMatrixBase\n  : public EigenBase<Derived>\n{\n  public:\n\n    typedef typename internal::traits<Derived>::Scalar Scalar;\n    \n    /** The numeric type of the expression' coefficients, e.g. float, double, int or std::complex<float>, etc.\n      *\n      * It is an alias for the Scalar type */\n    typedef Scalar value_type;\n    \n    typedef typename internal::packet_traits<Scalar>::type PacketScalar;\n    typedef typename internal::traits<Derived>::StorageKind StorageKind;\n    typedef typename internal::traits<Derived>::StorageIndex StorageIndex;\n    typedef typename internal::add_const_on_value_type_if_arithmetic<\n                         typename internal::packet_traits<Scalar>::type\n                     >::type PacketReturnType;\n\n    typedef SparseMatrixBase StorageBaseType;\n\n    typedef Matrix<StorageIndex,Dynamic,1> IndexVector;\n    typedef Matrix<Scalar,Dynamic,1> ScalarVector;\n    \n    template<typename OtherDerived>\n    Derived& operator=(const EigenBase<OtherDerived> &other);\n\n    enum {\n\n      RowsAtCompileTime = internal::traits<Derived>::RowsAtCompileTime,\n        /**< The number of rows at compile-time. This is just a copy of the value provided\n          * by the \\a Derived type. If a value is not known at compile-time,\n          * it is set to the \\a Dynamic constant.\n          * \\sa MatrixBase::rows(), MatrixBase::cols(), ColsAtCompileTime, SizeAtCompileTime */\n\n      ColsAtCompileTime = internal::traits<Derived>::ColsAtCompileTime,\n        /**< The number of columns at compile-time. This is just a copy of the value provided\n          * by the \\a Derived type. If a value is not known at compile-time,\n          * it is set to the \\a Dynamic constant.\n          * \\sa MatrixBase::rows(), MatrixBase::cols(), RowsAtCompileTime, SizeAtCompileTime */\n\n\n      SizeAtCompileTime = (internal::size_at_compile_time<internal::traits<Derived>::RowsAtCompileTime,\n                                                   internal::traits<Derived>::ColsAtCompileTime>::ret),\n        /**< This is equal to the number of coefficients, i.e. the number of\n          * rows times the number of columns, or to \\a Dynamic if this is not\n          * known at compile-time. \\sa RowsAtCompileTime, ColsAtCompileTime */\n\n      MaxRowsAtCompileTime = RowsAtCompileTime,\n      MaxColsAtCompileTime = ColsAtCompileTime,\n\n      MaxSizeAtCompileTime = (internal::size_at_compile_time<MaxRowsAtCompileTime,\n                                                      MaxColsAtCompileTime>::ret),\n\n      IsVectorAtCompileTime = RowsAtCompileTime == 1 || ColsAtCompileTime == 1,\n        /**< This is set to true if either the number of rows or the number of\n          * columns is known at compile-time to be equal to 1. Indeed, in that case,\n          * we are dealing with a column-vector (if there is only one column) or with\n          * a row-vector (if there is only one row). */\n\n      Flags = internal::traits<Derived>::Flags,\n        /**< This stores expression \\ref flags flags which may or may not be inherited by new expressions\n          * constructed from this one. See the \\ref flags \"list of flags\".\n          */\n\n      IsRowMajor = Flags&RowMajorBit ? 1 : 0,\n      \n      InnerSizeAtCompileTime = int(IsVectorAtCompileTime) ? int(SizeAtCompileTime)\n                             : int(IsRowMajor) ? int(ColsAtCompileTime) : int(RowsAtCompileTime),\n\n      #ifndef EIGEN_PARSED_BY_DOXYGEN\n      _HasDirectAccess = (int(Flags)&DirectAccessBit) ? 1 : 0 // workaround sunCC\n      #endif\n    };\n\n    /** \\internal the return type of MatrixBase::adjoint() */\n    typedef typename internal::conditional<NumTraits<Scalar>::IsComplex,\n                        CwiseUnaryOp<internal::scalar_conjugate_op<Scalar>, Eigen::Transpose<const Derived> >,\n                        Transpose<const Derived>\n                     >::type AdjointReturnType;\n    typedef Transpose<Derived> TransposeReturnType;\n    typedef typename internal::add_const<Transpose<const Derived> >::type ConstTransposeReturnType;\n\n    // FIXME storage order do not match evaluator storage order\n    typedef SparseMatrix<Scalar, Flags&RowMajorBit ? RowMajor : ColMajor, StorageIndex> PlainObject;\n\n#ifndef EIGEN_PARSED_BY_DOXYGEN\n    /** This is the \"real scalar\" type; if the \\a Scalar type is already real numbers\n      * (e.g. int, float or double) then \\a RealScalar is just the same as \\a Scalar. If\n      * \\a Scalar is \\a std::complex<T> then RealScalar is \\a T.\n      *\n      * \\sa class NumTraits\n      */\n    typedef typename NumTraits<Scalar>::Real RealScalar;\n\n    /** \\internal the return type of coeff()\n      */\n    typedef typename internal::conditional<_HasDirectAccess, const Scalar&, Scalar>::type CoeffReturnType;\n\n    /** \\internal Represents a matrix with all coefficients equal to one another*/\n    typedef CwiseNullaryOp<internal::scalar_constant_op<Scalar>,Matrix<Scalar,Dynamic,Dynamic> > ConstantReturnType;\n\n    /** type of the equivalent dense matrix */\n    typedef Matrix<Scalar,RowsAtCompileTime,ColsAtCompileTime> DenseMatrixType;\n    /** type of the equivalent square matrix */\n    typedef Matrix<Scalar,EIGEN_SIZE_MAX(RowsAtCompileTime,ColsAtCompileTime),\n                          EIGEN_SIZE_MAX(RowsAtCompileTime,ColsAtCompileTime)> SquareMatrixType;\n\n    inline const Derived& derived() const { return *static_cast<const Derived*>(this); }\n    inline Derived& derived() { return *static_cast<Derived*>(this); }\n    inline Derived& const_cast_derived() const\n    { return *static_cast<Derived*>(const_cast<SparseMatrixBase*>(this)); }\n\n    typedef EigenBase<Derived> Base;\n\n#endif // not EIGEN_PARSED_BY_DOXYGEN\n\n#define EIGEN_CURRENT_STORAGE_BASE_CLASS Eigen::SparseMatrixBase\n#ifdef EIGEN_PARSED_BY_DOXYGEN\n#define EIGEN_DOC_UNARY_ADDONS(METHOD,OP)           /** <p>This method does not change the sparsity of \\c *this: the OP is applied to explicitly stored coefficients only. \\sa SparseCompressedBase::coeffs() </p> */\n#define EIGEN_DOC_BLOCK_ADDONS_NOT_INNER_PANEL      /** <p> \\warning This method returns a read-only expression for any sparse matrices. \\sa \\ref TutorialSparse_SubMatrices \"Sparse block operations\" </p> */\n#define EIGEN_DOC_BLOCK_ADDONS_INNER_PANEL_IF(COND) /** <p> \\warning This method returns a read-write expression for COND sparse matrices only. Otherwise, the returned expression is read-only. \\sa \\ref TutorialSparse_SubMatrices \"Sparse block operations\" </p> */\n#else\n#define EIGEN_DOC_UNARY_ADDONS(X,Y)\n#define EIGEN_DOC_BLOCK_ADDONS_NOT_INNER_PANEL\n#define EIGEN_DOC_BLOCK_ADDONS_INNER_PANEL_IF(COND)\n#endif\n#   include \"../plugins/CommonCwiseUnaryOps.h\"\n#   include \"../plugins/CommonCwiseBinaryOps.h\"\n#   include \"../plugins/MatrixCwiseUnaryOps.h\"\n#   include \"../plugins/MatrixCwiseBinaryOps.h\"\n#   include \"../plugins/BlockMethods.h\"\n#   ifdef EIGEN_SPARSEMATRIXBASE_PLUGIN\n#     include EIGEN_SPARSEMATRIXBASE_PLUGIN\n#   endif\n#undef EIGEN_CURRENT_STORAGE_BASE_CLASS\n#undef EIGEN_DOC_UNARY_ADDONS\n#undef EIGEN_DOC_BLOCK_ADDONS_NOT_INNER_PANEL\n#undef EIGEN_DOC_BLOCK_ADDONS_INNER_PANEL_IF\n\n    /** \\returns the number of rows. \\sa cols() */\n    inline Index rows() const { return derived().rows(); }\n    /** \\returns the number of columns. \\sa rows() */\n    inline Index cols() const { return derived().cols(); }\n    /** \\returns the number of coefficients, which is \\a rows()*cols().\n      * \\sa rows(), cols(). */\n    inline Index size() const { return rows() * cols(); }\n    /** \\returns true if either the number of rows or the number of columns is equal to 1.\n      * In other words, this function returns\n      * \\code rows()==1 || cols()==1 \\endcode\n      * \\sa rows(), cols(), IsVectorAtCompileTime. */\n    inline bool isVector() const { return rows()==1 || cols()==1; }\n    /** \\returns the size of the storage major dimension,\n      * i.e., the number of columns for a columns major matrix, and the number of rows otherwise */\n    Index outerSize() const { return (int(Flags)&RowMajorBit) ? this->rows() : this->cols(); }\n    /** \\returns the size of the inner dimension according to the storage order,\n      * i.e., the number of rows for a columns major matrix, and the number of cols otherwise */\n    Index innerSize() const { return (int(Flags)&RowMajorBit) ? this->cols() : this->rows(); }\n\n    bool isRValue() const { return m_isRValue; }\n    Derived& markAsRValue() { m_isRValue = true; return derived(); }\n\n    SparseMatrixBase() : m_isRValue(false) { /* TODO check flags */ }\n\n    \n    template<typename OtherDerived>\n    Derived& operator=(const ReturnByValue<OtherDerived>& other);\n\n    template<typename OtherDerived>\n    inline Derived& operator=(const SparseMatrixBase<OtherDerived>& other);\n\n    inline Derived& operator=(const Derived& other);\n\n  protected:\n\n    template<typename OtherDerived>\n    inline Derived& assign(const OtherDerived& other);\n\n    template<typename OtherDerived>\n    inline void assignGeneric(const OtherDerived& other);\n\n  public:\n\n    friend std::ostream & operator << (std::ostream & s, const SparseMatrixBase& m)\n    {\n      typedef typename Derived::Nested Nested;\n      typedef typename internal::remove_all<Nested>::type NestedCleaned;\n\n      if (Flags&RowMajorBit)\n      {\n        const Nested nm(m.derived());\n        internal::evaluator<NestedCleaned> thisEval(nm);\n        for (Index row=0; row<nm.outerSize(); ++row)\n        {\n          Index col = 0;\n          for (typename internal::evaluator<NestedCleaned>::InnerIterator it(thisEval, row); it; ++it)\n          {\n            for ( ; col<it.index(); ++col)\n              s << \"0 \";\n            s << it.value() << \" \";\n            ++col;\n          }\n          for ( ; col<m.cols(); ++col)\n            s << \"0 \";\n          s << std::endl;\n        }\n      }\n      else\n      {\n        const Nested nm(m.derived());\n        internal::evaluator<NestedCleaned> thisEval(nm);\n        if (m.cols() == 1) {\n          Index row = 0;\n          for (typename internal::evaluator<NestedCleaned>::InnerIterator it(thisEval, 0); it; ++it)\n          {\n            for ( ; row<it.index(); ++row)\n              s << \"0\" << std::endl;\n            s << it.value() << std::endl;\n            ++row;\n          }\n          for ( ; row<m.rows(); ++row)\n            s << \"0\" << std::endl;\n        }\n        else\n        {\n          SparseMatrix<Scalar, RowMajorBit, StorageIndex> trans = m;\n          s << static_cast<const SparseMatrixBase<SparseMatrix<Scalar, RowMajorBit, StorageIndex> >&>(trans);\n        }\n      }\n      return s;\n    }\n\n    template<typename OtherDerived>\n    Derived& operator+=(const SparseMatrixBase<OtherDerived>& other);\n    template<typename OtherDerived>\n    Derived& operator-=(const SparseMatrixBase<OtherDerived>& other);\n    \n    template<typename OtherDerived>\n    Derived& operator+=(const DiagonalBase<OtherDerived>& other);\n    template<typename OtherDerived>\n    Derived& operator-=(const DiagonalBase<OtherDerived>& other);\n\n    Derived& operator*=(const Scalar& other);\n    Derived& operator/=(const Scalar& other);\n\n    template<typename OtherDerived> struct CwiseProductDenseReturnType {\n      typedef CwiseBinaryOp<internal::scalar_product_op<typename ScalarBinaryOpTraits<\n                                                          typename internal::traits<Derived>::Scalar,\n                                                          typename internal::traits<OtherDerived>::Scalar\n                                                        >::ReturnType>,\n                            const Derived,\n                            const OtherDerived\n                          > Type;\n    };\n\n    template<typename OtherDerived>\n    EIGEN_STRONG_INLINE const typename CwiseProductDenseReturnType<OtherDerived>::Type\n    cwiseProduct(const MatrixBase<OtherDerived> &other) const;\n\n    // sparse * diagonal\n    template<typename OtherDerived>\n    const Product<Derived,OtherDerived>\n    operator*(const DiagonalBase<OtherDerived> &other) const\n    { return Product<Derived,OtherDerived>(derived(), other.derived()); }\n\n    // diagonal * sparse\n    template<typename OtherDerived> friend\n    const Product<OtherDerived,Derived>\n    operator*(const DiagonalBase<OtherDerived> &lhs, const SparseMatrixBase& rhs)\n    { return Product<OtherDerived,Derived>(lhs.derived(), rhs.derived()); }\n    \n    // sparse * sparse\n    template<typename OtherDerived>\n    const Product<Derived,OtherDerived,AliasFreeProduct>\n    operator*(const SparseMatrixBase<OtherDerived> &other) const;\n    \n    // sparse * dense\n    template<typename OtherDerived>\n    const Product<Derived,OtherDerived>\n    operator*(const MatrixBase<OtherDerived> &other) const\n    { return Product<Derived,OtherDerived>(derived(), other.derived()); }\n    \n    // dense * sparse\n    template<typename OtherDerived> friend\n    const Product<OtherDerived,Derived>\n    operator*(const MatrixBase<OtherDerived> &lhs, const SparseMatrixBase& rhs)\n    { return Product<OtherDerived,Derived>(lhs.derived(), rhs.derived()); }\n    \n     /** \\returns an expression of P H P^-1 where H is the matrix represented by \\c *this */\n    SparseSymmetricPermutationProduct<Derived,Upper|Lower> twistedBy(const PermutationMatrix<Dynamic,Dynamic,StorageIndex>& perm) const\n    {\n      return SparseSymmetricPermutationProduct<Derived,Upper|Lower>(derived(), perm);\n    }\n\n    template<typename OtherDerived>\n    Derived& operator*=(const SparseMatrixBase<OtherDerived>& other);\n\n    template<int Mode>\n    inline const TriangularView<const Derived, Mode> triangularView() const;\n    \n    template<unsigned int UpLo> struct SelfAdjointViewReturnType { typedef SparseSelfAdjointView<Derived, UpLo> Type; };\n    template<unsigned int UpLo> struct ConstSelfAdjointViewReturnType { typedef const SparseSelfAdjointView<const Derived, UpLo> Type; };\n\n    template<unsigned int UpLo> inline \n    typename ConstSelfAdjointViewReturnType<UpLo>::Type selfadjointView() const;\n    template<unsigned int UpLo> inline\n    typename SelfAdjointViewReturnType<UpLo>::Type selfadjointView();\n\n    template<typename OtherDerived> Scalar dot(const MatrixBase<OtherDerived>& other) const;\n    template<typename OtherDerived> Scalar dot(const SparseMatrixBase<OtherDerived>& other) const;\n    RealScalar squaredNorm() const;\n    RealScalar norm()  const;\n    RealScalar blueNorm() const;\n\n    TransposeReturnType transpose() { return TransposeReturnType(derived()); }\n    const ConstTransposeReturnType transpose() const { return ConstTransposeReturnType(derived()); }\n    const AdjointReturnType adjoint() const { return AdjointReturnType(transpose()); }\n\n    // inner-vector\n    typedef Block<Derived,IsRowMajor?1:Dynamic,IsRowMajor?Dynamic:1,true>       InnerVectorReturnType;\n    typedef Block<const Derived,IsRowMajor?1:Dynamic,IsRowMajor?Dynamic:1,true> ConstInnerVectorReturnType;\n    InnerVectorReturnType innerVector(Index outer);\n    const ConstInnerVectorReturnType innerVector(Index outer) const;\n\n    // set of inner-vectors\n    typedef Block<Derived,Dynamic,Dynamic,true> InnerVectorsReturnType;\n    typedef Block<const Derived,Dynamic,Dynamic,true> ConstInnerVectorsReturnType;\n    InnerVectorsReturnType innerVectors(Index outerStart, Index outerSize);\n    const ConstInnerVectorsReturnType innerVectors(Index outerStart, Index outerSize) const;\n\n    DenseMatrixType toDense() const\n    {\n      return DenseMatrixType(derived());\n    }\n\n    template<typename OtherDerived>\n    bool isApprox(const SparseMatrixBase<OtherDerived>& other,\n                  const RealScalar& prec = NumTraits<Scalar>::dummy_precision()) const;\n\n    template<typename OtherDerived>\n    bool isApprox(const MatrixBase<OtherDerived>& other,\n                  const RealScalar& prec = NumTraits<Scalar>::dummy_precision()) const\n    { return toDense().isApprox(other,prec); }\n\n    /** \\returns the matrix or vector obtained by evaluating this expression.\n      *\n      * Notice that in the case of a plain matrix or vector (not an expression) this function just returns\n      * a const reference, in order to avoid a useless copy.\n      */\n    inline const typename internal::eval<Derived>::type eval() const\n    { return typename internal::eval<Derived>::type(derived()); }\n\n    Scalar sum() const;\n    \n    inline const SparseView<Derived>\n    pruned(const Scalar& reference = Scalar(0), const RealScalar& epsilon = NumTraits<Scalar>::dummy_precision()) const;\n\n  protected:\n\n    bool m_isRValue;\n\n    static inline StorageIndex convert_index(const Index idx) {\n      return internal::convert_index<StorageIndex>(idx);\n    }\n  private:\n    template<typename Dest> void evalTo(Dest &) const;\n};\n\n} // end namespace Eigen\n\n#endif // EIGEN_SPARSEMATRIXBASE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseCore/SparsePermutation.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2012 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SPARSE_PERMUTATION_H\n#define EIGEN_SPARSE_PERMUTATION_H\n\n// This file implements sparse * permutation products\n\nnamespace Eigen { \n\nnamespace internal {\n\ntemplate<typename ExpressionType, int Side, bool Transposed>\nstruct permutation_matrix_product<ExpressionType, Side, Transposed, SparseShape>\n{\n    typedef typename nested_eval<ExpressionType, 1>::type MatrixType;\n    typedef typename remove_all<MatrixType>::type MatrixTypeCleaned;\n\n    typedef typename MatrixTypeCleaned::Scalar Scalar;\n    typedef typename MatrixTypeCleaned::StorageIndex StorageIndex;\n\n    enum {\n      SrcStorageOrder = MatrixTypeCleaned::Flags&RowMajorBit ? RowMajor : ColMajor,\n      MoveOuter = SrcStorageOrder==RowMajor ? Side==OnTheLeft : Side==OnTheRight\n    };\n    \n    typedef typename internal::conditional<MoveOuter,\n        SparseMatrix<Scalar,SrcStorageOrder,StorageIndex>,\n        SparseMatrix<Scalar,int(SrcStorageOrder)==RowMajor?ColMajor:RowMajor,StorageIndex> >::type ReturnType;\n\n    template<typename Dest,typename PermutationType>\n    static inline void run(Dest& dst, const PermutationType& perm, const ExpressionType& xpr)\n    {\n      MatrixType mat(xpr);\n      if(MoveOuter)\n      {\n        SparseMatrix<Scalar,SrcStorageOrder,StorageIndex> tmp(mat.rows(), mat.cols());\n        Matrix<StorageIndex,Dynamic,1> sizes(mat.outerSize());\n        for(Index j=0; j<mat.outerSize(); ++j)\n        {\n          Index jp = perm.indices().coeff(j);\n          sizes[((Side==OnTheLeft) ^ Transposed) ? jp : j] = StorageIndex(mat.innerVector(((Side==OnTheRight) ^ Transposed) ? jp : j).nonZeros());\n        }\n        tmp.reserve(sizes);\n        for(Index j=0; j<mat.outerSize(); ++j)\n        {\n          Index jp = perm.indices().coeff(j);\n          Index jsrc = ((Side==OnTheRight) ^ Transposed) ? jp : j;\n          Index jdst = ((Side==OnTheLeft) ^ Transposed) ? jp : j;\n          for(typename MatrixTypeCleaned::InnerIterator it(mat,jsrc); it; ++it)\n            tmp.insertByOuterInner(jdst,it.index()) = it.value();\n        }\n        dst = tmp;\n      }\n      else\n      {\n        SparseMatrix<Scalar,int(SrcStorageOrder)==RowMajor?ColMajor:RowMajor,StorageIndex> tmp(mat.rows(), mat.cols());\n        Matrix<StorageIndex,Dynamic,1> sizes(tmp.outerSize());\n        sizes.setZero();\n        PermutationMatrix<Dynamic,Dynamic,StorageIndex> perm_cpy;\n        if((Side==OnTheLeft) ^ Transposed)\n          perm_cpy = perm;\n        else\n          perm_cpy = perm.transpose();\n\n        for(Index j=0; j<mat.outerSize(); ++j)\n          for(typename MatrixTypeCleaned::InnerIterator it(mat,j); it; ++it)\n            sizes[perm_cpy.indices().coeff(it.index())]++;\n        tmp.reserve(sizes);\n        for(Index j=0; j<mat.outerSize(); ++j)\n          for(typename MatrixTypeCleaned::InnerIterator it(mat,j); it; ++it)\n            tmp.insertByOuterInner(perm_cpy.indices().coeff(it.index()),j) = it.value();\n        dst = tmp;\n      }\n    }\n};\n\n}\n\nnamespace internal {\n\ntemplate <int ProductTag> struct product_promote_storage_type<Sparse,             PermutationStorage, ProductTag> { typedef Sparse ret; };\ntemplate <int ProductTag> struct product_promote_storage_type<PermutationStorage, Sparse,             ProductTag> { typedef Sparse ret; };\n\n// TODO, the following two overloads are only needed to define the right temporary type through \n// typename traits<permutation_sparse_matrix_product<Rhs,Lhs,OnTheRight,false> >::ReturnType\n// whereas it should be correctly handled by traits<Product<> >::PlainObject\n\ntemplate<typename Lhs, typename Rhs, int ProductTag>\nstruct product_evaluator<Product<Lhs, Rhs, AliasFreeProduct>, ProductTag, PermutationShape, SparseShape>\n  : public evaluator<typename permutation_matrix_product<Rhs,OnTheLeft,false,SparseShape>::ReturnType>\n{\n  typedef Product<Lhs, Rhs, AliasFreeProduct> XprType;\n  typedef typename permutation_matrix_product<Rhs,OnTheLeft,false,SparseShape>::ReturnType PlainObject;\n  typedef evaluator<PlainObject> Base;\n\n  enum {\n    Flags = Base::Flags | EvalBeforeNestingBit\n  };\n\n  explicit product_evaluator(const XprType& xpr)\n    : m_result(xpr.rows(), xpr.cols())\n  {\n    ::new (static_cast<Base*>(this)) Base(m_result);\n    generic_product_impl<Lhs, Rhs, PermutationShape, SparseShape, ProductTag>::evalTo(m_result, xpr.lhs(), xpr.rhs());\n  }\n\nprotected:\n  PlainObject m_result;\n};\n\ntemplate<typename Lhs, typename Rhs, int ProductTag>\nstruct product_evaluator<Product<Lhs, Rhs, AliasFreeProduct>, ProductTag, SparseShape, PermutationShape >\n  : public evaluator<typename permutation_matrix_product<Lhs,OnTheRight,false,SparseShape>::ReturnType>\n{\n  typedef Product<Lhs, Rhs, AliasFreeProduct> XprType;\n  typedef typename permutation_matrix_product<Lhs,OnTheRight,false,SparseShape>::ReturnType PlainObject;\n  typedef evaluator<PlainObject> Base;\n\n  enum {\n    Flags = Base::Flags | EvalBeforeNestingBit\n  };\n\n  explicit product_evaluator(const XprType& xpr)\n    : m_result(xpr.rows(), xpr.cols())\n  {\n    ::new (static_cast<Base*>(this)) Base(m_result);\n    generic_product_impl<Lhs, Rhs, SparseShape, PermutationShape, ProductTag>::evalTo(m_result, xpr.lhs(), xpr.rhs());\n  }\n\nprotected:\n  PlainObject m_result;\n};\n\n} // end namespace internal\n\n/** \\returns the matrix with the permutation applied to the columns\n  */\ntemplate<typename SparseDerived, typename PermDerived>\ninline const Product<SparseDerived, PermDerived, AliasFreeProduct>\noperator*(const SparseMatrixBase<SparseDerived>& matrix, const PermutationBase<PermDerived>& perm)\n{ return Product<SparseDerived, PermDerived, AliasFreeProduct>(matrix.derived(), perm.derived()); }\n\n/** \\returns the matrix with the permutation applied to the rows\n  */\ntemplate<typename SparseDerived, typename PermDerived>\ninline const Product<PermDerived, SparseDerived, AliasFreeProduct>\noperator*( const PermutationBase<PermDerived>& perm, const SparseMatrixBase<SparseDerived>& matrix)\n{ return  Product<PermDerived, SparseDerived, AliasFreeProduct>(perm.derived(), matrix.derived()); }\n\n\n/** \\returns the matrix with the inverse permutation applied to the columns.\n  */\ntemplate<typename SparseDerived, typename PermutationType>\ninline const Product<SparseDerived, Inverse<PermutationType>, AliasFreeProduct>\noperator*(const SparseMatrixBase<SparseDerived>& matrix, const InverseImpl<PermutationType, PermutationStorage>& tperm)\n{\n  return Product<SparseDerived, Inverse<PermutationType>, AliasFreeProduct>(matrix.derived(), tperm.derived());\n}\n\n/** \\returns the matrix with the inverse permutation applied to the rows.\n  */\ntemplate<typename SparseDerived, typename PermutationType>\ninline const Product<Inverse<PermutationType>, SparseDerived, AliasFreeProduct>\noperator*(const InverseImpl<PermutationType,PermutationStorage>& tperm, const SparseMatrixBase<SparseDerived>& matrix)\n{\n  return Product<Inverse<PermutationType>, SparseDerived, AliasFreeProduct>(tperm.derived(), matrix.derived());\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_SPARSE_SELFADJOINTVIEW_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseCore/SparseProduct.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2015 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SPARSEPRODUCT_H\n#define EIGEN_SPARSEPRODUCT_H\n\nnamespace Eigen { \n\n/** \\returns an expression of the product of two sparse matrices.\n  * By default a conservative product preserving the symbolic non zeros is performed.\n  * The automatic pruning of the small values can be achieved by calling the pruned() function\n  * in which case a totally different product algorithm is employed:\n  * \\code\n  * C = (A*B).pruned();             // supress numerical zeros (exact)\n  * C = (A*B).pruned(ref);\n  * C = (A*B).pruned(ref,epsilon);\n  * \\endcode\n  * where \\c ref is a meaningful non zero reference value.\n  * */\ntemplate<typename Derived>\ntemplate<typename OtherDerived>\ninline const Product<Derived,OtherDerived,AliasFreeProduct>\nSparseMatrixBase<Derived>::operator*(const SparseMatrixBase<OtherDerived> &other) const\n{\n  return Product<Derived,OtherDerived,AliasFreeProduct>(derived(), other.derived());\n}\n\nnamespace internal {\n\n// sparse * sparse\ntemplate<typename Lhs, typename Rhs, int ProductType>\nstruct generic_product_impl<Lhs, Rhs, SparseShape, SparseShape, ProductType>\n{\n  template<typename Dest>\n  static void evalTo(Dest& dst, const Lhs& lhs, const Rhs& rhs)\n  {\n    evalTo(dst, lhs, rhs, typename evaluator_traits<Dest>::Shape());\n  }\n\n  // dense += sparse * sparse\n  template<typename Dest,typename ActualLhs>\n  static void addTo(Dest& dst, const ActualLhs& lhs, const Rhs& rhs, typename enable_if<is_same<typename evaluator_traits<Dest>::Shape,DenseShape>::value,int*>::type* = 0)\n  {\n    typedef typename nested_eval<ActualLhs,Dynamic>::type LhsNested;\n    typedef typename nested_eval<Rhs,Dynamic>::type RhsNested;\n    LhsNested lhsNested(lhs);\n    RhsNested rhsNested(rhs);\n    internal::sparse_sparse_to_dense_product_selector<typename remove_all<LhsNested>::type,\n                                                      typename remove_all<RhsNested>::type, Dest>::run(lhsNested,rhsNested,dst);\n  }\n\n  // dense -= sparse * sparse\n  template<typename Dest>\n  static void subTo(Dest& dst, const Lhs& lhs, const Rhs& rhs, typename enable_if<is_same<typename evaluator_traits<Dest>::Shape,DenseShape>::value,int*>::type* = 0)\n  {\n    addTo(dst, -lhs, rhs);\n  }\n\nprotected:\n\n  // sparse = sparse * sparse\n  template<typename Dest>\n  static void evalTo(Dest& dst, const Lhs& lhs, const Rhs& rhs, SparseShape)\n  {\n    typedef typename nested_eval<Lhs,Dynamic>::type LhsNested;\n    typedef typename nested_eval<Rhs,Dynamic>::type RhsNested;\n    LhsNested lhsNested(lhs);\n    RhsNested rhsNested(rhs);\n    internal::conservative_sparse_sparse_product_selector<typename remove_all<LhsNested>::type,\n                                                          typename remove_all<RhsNested>::type, Dest>::run(lhsNested,rhsNested,dst);\n  }\n\n  // dense = sparse * sparse\n  template<typename Dest>\n  static void evalTo(Dest& dst, const Lhs& lhs, const Rhs& rhs, DenseShape)\n  {\n    dst.setZero();\n    addTo(dst, lhs, rhs);\n  }\n};\n\n// sparse * sparse-triangular\ntemplate<typename Lhs, typename Rhs, int ProductType>\nstruct generic_product_impl<Lhs, Rhs, SparseShape, SparseTriangularShape, ProductType>\n : public generic_product_impl<Lhs, Rhs, SparseShape, SparseShape, ProductType>\n{};\n\n// sparse-triangular * sparse\ntemplate<typename Lhs, typename Rhs, int ProductType>\nstruct generic_product_impl<Lhs, Rhs, SparseTriangularShape, SparseShape, ProductType>\n : public generic_product_impl<Lhs, Rhs, SparseShape, SparseShape, ProductType>\n{};\n\n// dense = sparse-product (can be sparse*sparse, sparse*perm, etc.)\ntemplate< typename DstXprType, typename Lhs, typename Rhs>\nstruct Assignment<DstXprType, Product<Lhs,Rhs,AliasFreeProduct>, internal::assign_op<typename DstXprType::Scalar,typename Product<Lhs,Rhs,AliasFreeProduct>::Scalar>, Sparse2Dense>\n{\n  typedef Product<Lhs,Rhs,AliasFreeProduct> SrcXprType;\n  static void run(DstXprType &dst, const SrcXprType &src, const internal::assign_op<typename DstXprType::Scalar,typename SrcXprType::Scalar> &)\n  {\n    Index dstRows = src.rows();\n    Index dstCols = src.cols();\n    if((dst.rows()!=dstRows) || (dst.cols()!=dstCols))\n      dst.resize(dstRows, dstCols);\n    \n    generic_product_impl<Lhs, Rhs>::evalTo(dst,src.lhs(),src.rhs());\n  }\n};\n\n// dense += sparse-product (can be sparse*sparse, sparse*perm, etc.)\ntemplate< typename DstXprType, typename Lhs, typename Rhs>\nstruct Assignment<DstXprType, Product<Lhs,Rhs,AliasFreeProduct>, internal::add_assign_op<typename DstXprType::Scalar,typename Product<Lhs,Rhs,AliasFreeProduct>::Scalar>, Sparse2Dense>\n{\n  typedef Product<Lhs,Rhs,AliasFreeProduct> SrcXprType;\n  static void run(DstXprType &dst, const SrcXprType &src, const internal::add_assign_op<typename DstXprType::Scalar,typename SrcXprType::Scalar> &)\n  {\n    generic_product_impl<Lhs, Rhs>::addTo(dst,src.lhs(),src.rhs());\n  }\n};\n\n// dense -= sparse-product (can be sparse*sparse, sparse*perm, etc.)\ntemplate< typename DstXprType, typename Lhs, typename Rhs>\nstruct Assignment<DstXprType, Product<Lhs,Rhs,AliasFreeProduct>, internal::sub_assign_op<typename DstXprType::Scalar,typename Product<Lhs,Rhs,AliasFreeProduct>::Scalar>, Sparse2Dense>\n{\n  typedef Product<Lhs,Rhs,AliasFreeProduct> SrcXprType;\n  static void run(DstXprType &dst, const SrcXprType &src, const internal::sub_assign_op<typename DstXprType::Scalar,typename SrcXprType::Scalar> &)\n  {\n    generic_product_impl<Lhs, Rhs>::subTo(dst,src.lhs(),src.rhs());\n  }\n};\n\ntemplate<typename Lhs, typename Rhs, int Options>\nstruct unary_evaluator<SparseView<Product<Lhs, Rhs, Options> >, IteratorBased>\n : public evaluator<typename Product<Lhs, Rhs, DefaultProduct>::PlainObject>\n{\n  typedef SparseView<Product<Lhs, Rhs, Options> > XprType;\n  typedef typename XprType::PlainObject PlainObject;\n  typedef evaluator<PlainObject> Base;\n\n  explicit unary_evaluator(const XprType& xpr)\n    : m_result(xpr.rows(), xpr.cols())\n  {\n    using std::abs;\n    ::new (static_cast<Base*>(this)) Base(m_result);\n    typedef typename nested_eval<Lhs,Dynamic>::type LhsNested;\n    typedef typename nested_eval<Rhs,Dynamic>::type RhsNested;\n    LhsNested lhsNested(xpr.nestedExpression().lhs());\n    RhsNested rhsNested(xpr.nestedExpression().rhs());\n\n    internal::sparse_sparse_product_with_pruning_selector<typename remove_all<LhsNested>::type,\n                                                          typename remove_all<RhsNested>::type, PlainObject>::run(lhsNested,rhsNested,m_result,\n                                                                                                                  abs(xpr.reference())*xpr.epsilon());\n  }\n\nprotected:\n  PlainObject m_result;\n};\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_SPARSEPRODUCT_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseCore/SparseRedux.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2014 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SPARSEREDUX_H\n#define EIGEN_SPARSEREDUX_H\n\nnamespace Eigen { \n\ntemplate<typename Derived>\ntypename internal::traits<Derived>::Scalar\nSparseMatrixBase<Derived>::sum() const\n{\n  eigen_assert(rows()>0 && cols()>0 && \"you are using a non initialized matrix\");\n  Scalar res(0);\n  internal::evaluator<Derived> thisEval(derived());\n  for (Index j=0; j<outerSize(); ++j)\n    for (typename internal::evaluator<Derived>::InnerIterator iter(thisEval,j); iter; ++iter)\n      res += iter.value();\n  return res;\n}\n\ntemplate<typename _Scalar, int _Options, typename _Index>\ntypename internal::traits<SparseMatrix<_Scalar,_Options,_Index> >::Scalar\nSparseMatrix<_Scalar,_Options,_Index>::sum() const\n{\n  eigen_assert(rows()>0 && cols()>0 && \"you are using a non initialized matrix\");\n  if(this->isCompressed())\n    return Matrix<Scalar,1,Dynamic>::Map(m_data.valuePtr(), m_data.size()).sum();\n  else\n    return Base::sum();\n}\n\ntemplate<typename _Scalar, int _Options, typename _Index>\ntypename internal::traits<SparseVector<_Scalar,_Options, _Index> >::Scalar\nSparseVector<_Scalar,_Options,_Index>::sum() const\n{\n  eigen_assert(rows()>0 && cols()>0 && \"you are using a non initialized matrix\");\n  return Matrix<Scalar,1,Dynamic>::Map(m_data.valuePtr(), m_data.size()).sum();\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_SPARSEREDUX_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseCore/SparseRef.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2015 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SPARSE_REF_H\n#define EIGEN_SPARSE_REF_H\n\nnamespace Eigen {\n\nenum {\n  StandardCompressedFormat = 2 /**< used by Ref<SparseMatrix> to specify whether the input storage must be in standard compressed form */\n};\n  \nnamespace internal {\n\ntemplate<typename Derived> class SparseRefBase;\n\ntemplate<typename MatScalar, int MatOptions, typename MatIndex, int _Options, typename _StrideType>\nstruct traits<Ref<SparseMatrix<MatScalar,MatOptions,MatIndex>, _Options, _StrideType> >\n  : public traits<SparseMatrix<MatScalar,MatOptions,MatIndex> >\n{\n  typedef SparseMatrix<MatScalar,MatOptions,MatIndex> PlainObjectType;\n  enum {\n    Options = _Options,\n    Flags = traits<PlainObjectType>::Flags | CompressedAccessBit | NestByRefBit\n  };\n\n  template<typename Derived> struct match {\n    enum {\n      StorageOrderMatch = PlainObjectType::IsVectorAtCompileTime || Derived::IsVectorAtCompileTime || ((PlainObjectType::Flags&RowMajorBit)==(Derived::Flags&RowMajorBit)),\n      MatchAtCompileTime = (Derived::Flags&CompressedAccessBit) && StorageOrderMatch\n    };\n    typedef typename internal::conditional<MatchAtCompileTime,internal::true_type,internal::false_type>::type type;\n  };\n  \n};\n\ntemplate<typename MatScalar, int MatOptions, typename MatIndex, int _Options, typename _StrideType>\nstruct traits<Ref<const SparseMatrix<MatScalar,MatOptions,MatIndex>, _Options, _StrideType> >\n  : public traits<Ref<SparseMatrix<MatScalar,MatOptions,MatIndex>, _Options, _StrideType> >\n{\n  enum {\n    Flags = (traits<SparseMatrix<MatScalar,MatOptions,MatIndex> >::Flags | CompressedAccessBit | NestByRefBit) & ~LvalueBit\n  };\n};\n\ntemplate<typename MatScalar, int MatOptions, typename MatIndex, int _Options, typename _StrideType>\nstruct traits<Ref<SparseVector<MatScalar,MatOptions,MatIndex>, _Options, _StrideType> >\n  : public traits<SparseVector<MatScalar,MatOptions,MatIndex> >\n{\n  typedef SparseVector<MatScalar,MatOptions,MatIndex> PlainObjectType;\n  enum {\n    Options = _Options,\n    Flags = traits<PlainObjectType>::Flags | CompressedAccessBit | NestByRefBit\n  };\n\n  template<typename Derived> struct match {\n    enum {\n      MatchAtCompileTime = (Derived::Flags&CompressedAccessBit) && Derived::IsVectorAtCompileTime\n    };\n    typedef typename internal::conditional<MatchAtCompileTime,internal::true_type,internal::false_type>::type type;\n  };\n\n};\n\ntemplate<typename MatScalar, int MatOptions, typename MatIndex, int _Options, typename _StrideType>\nstruct traits<Ref<const SparseVector<MatScalar,MatOptions,MatIndex>, _Options, _StrideType> >\n  : public traits<Ref<SparseVector<MatScalar,MatOptions,MatIndex>, _Options, _StrideType> >\n{\n  enum {\n    Flags = (traits<SparseVector<MatScalar,MatOptions,MatIndex> >::Flags | CompressedAccessBit | NestByRefBit) & ~LvalueBit\n  };\n};\n\ntemplate<typename Derived>\nstruct traits<SparseRefBase<Derived> > : public traits<Derived> {};\n\ntemplate<typename Derived> class SparseRefBase\n  : public SparseMapBase<Derived>\n{\npublic:\n\n  typedef SparseMapBase<Derived> Base;\n  EIGEN_SPARSE_PUBLIC_INTERFACE(SparseRefBase)\n\n  SparseRefBase()\n    : Base(RowsAtCompileTime==Dynamic?0:RowsAtCompileTime,ColsAtCompileTime==Dynamic?0:ColsAtCompileTime, 0, 0, 0, 0, 0)\n  {}\n  \nprotected:\n\n  template<typename Expression>\n  void construct(Expression& expr)\n  {\n    if(expr.outerIndexPtr()==0)\n      ::new (static_cast<Base*>(this)) Base(expr.size(), expr.nonZeros(), expr.innerIndexPtr(), expr.valuePtr());\n    else\n      ::new (static_cast<Base*>(this)) Base(expr.rows(), expr.cols(), expr.nonZeros(), expr.outerIndexPtr(), expr.innerIndexPtr(), expr.valuePtr(), expr.innerNonZeroPtr());\n  }\n};\n\n} // namespace internal\n\n\n/** \n  * \\ingroup SparseCore_Module\n  *\n  * \\brief A sparse matrix expression referencing an existing sparse expression\n  *\n  * \\tparam SparseMatrixType the equivalent sparse matrix type of the referenced data, it must be a template instance of class SparseMatrix.\n  * \\tparam Options specifies whether the a standard compressed format is required \\c Options is  \\c #StandardCompressedFormat, or \\c 0.\n  *                The default is \\c 0.\n  *\n  * \\sa class Ref\n  */\n#ifndef EIGEN_PARSED_BY_DOXYGEN\ntemplate<typename MatScalar, int MatOptions, typename MatIndex, int Options, typename StrideType>\nclass Ref<SparseMatrix<MatScalar,MatOptions,MatIndex>, Options, StrideType >\n  : public internal::SparseRefBase<Ref<SparseMatrix<MatScalar,MatOptions,MatIndex>, Options, StrideType > >\n#else\ntemplate<typename SparseMatrixType, int Options>\nclass Ref<SparseMatrixType, Options>\n  : public SparseMapBase<Derived,WriteAccessors> // yes, that's weird to use Derived here, but that works!\n#endif\n{\n    typedef SparseMatrix<MatScalar,MatOptions,MatIndex> PlainObjectType;\n    typedef internal::traits<Ref> Traits;\n    template<int OtherOptions>\n    inline Ref(const SparseMatrix<MatScalar,OtherOptions,MatIndex>& expr);\n    template<int OtherOptions>\n    inline Ref(const MappedSparseMatrix<MatScalar,OtherOptions,MatIndex>& expr);\n  public:\n\n    typedef internal::SparseRefBase<Ref> Base;\n    EIGEN_SPARSE_PUBLIC_INTERFACE(Ref)\n\n\n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    template<int OtherOptions>\n    inline Ref(SparseMatrix<MatScalar,OtherOptions,MatIndex>& expr)\n    {\n      EIGEN_STATIC_ASSERT(bool(Traits::template match<SparseMatrix<MatScalar,OtherOptions,MatIndex> >::MatchAtCompileTime), STORAGE_LAYOUT_DOES_NOT_MATCH);\n      eigen_assert( ((Options & int(StandardCompressedFormat))==0) || (expr.isCompressed()) );\n      Base::construct(expr.derived());\n    }\n    \n    template<int OtherOptions>\n    inline Ref(MappedSparseMatrix<MatScalar,OtherOptions,MatIndex>& expr)\n    {\n      EIGEN_STATIC_ASSERT(bool(Traits::template match<SparseMatrix<MatScalar,OtherOptions,MatIndex> >::MatchAtCompileTime), STORAGE_LAYOUT_DOES_NOT_MATCH);\n      eigen_assert( ((Options & int(StandardCompressedFormat))==0) || (expr.isCompressed()) );\n      Base::construct(expr.derived());\n    }\n    \n    template<typename Derived>\n    inline Ref(const SparseCompressedBase<Derived>& expr)\n    #else\n    /** Implicit constructor from any sparse expression (2D matrix or 1D vector) */\n    template<typename Derived>\n    inline Ref(SparseCompressedBase<Derived>& expr)\n    #endif\n    {\n      EIGEN_STATIC_ASSERT(bool(internal::is_lvalue<Derived>::value), THIS_EXPRESSION_IS_NOT_A_LVALUE__IT_IS_READ_ONLY);\n      EIGEN_STATIC_ASSERT(bool(Traits::template match<Derived>::MatchAtCompileTime), STORAGE_LAYOUT_DOES_NOT_MATCH);\n      eigen_assert( ((Options & int(StandardCompressedFormat))==0) || (expr.isCompressed()) );\n      Base::construct(expr.const_cast_derived());\n    }\n};\n\n// this is the const ref version\ntemplate<typename MatScalar, int MatOptions, typename MatIndex, int Options, typename StrideType>\nclass Ref<const SparseMatrix<MatScalar,MatOptions,MatIndex>, Options, StrideType>\n  : public internal::SparseRefBase<Ref<const SparseMatrix<MatScalar,MatOptions,MatIndex>, Options, StrideType> >\n{\n    typedef SparseMatrix<MatScalar,MatOptions,MatIndex> TPlainObjectType;\n    typedef internal::traits<Ref> Traits;\n  public:\n\n    typedef internal::SparseRefBase<Ref> Base;\n    EIGEN_SPARSE_PUBLIC_INTERFACE(Ref)\n\n    template<typename Derived>\n    inline Ref(const SparseMatrixBase<Derived>& expr) : m_hasCopy(false)\n    {\n      construct(expr.derived(), typename Traits::template match<Derived>::type());\n    }\n\n    inline Ref(const Ref& other) : Base(other), m_hasCopy(false) {\n      // copy constructor shall not copy the m_object, to avoid unnecessary malloc and copy\n    }\n\n    template<typename OtherRef>\n    inline Ref(const RefBase<OtherRef>& other) : m_hasCopy(false) {\n      construct(other.derived(), typename Traits::template match<OtherRef>::type());\n    }\n\n    ~Ref() {\n      if(m_hasCopy) {\n        TPlainObjectType* obj = reinterpret_cast<TPlainObjectType*>(m_object_bytes);\n        obj->~TPlainObjectType();\n      }\n    }\n\n  protected:\n\n    template<typename Expression>\n    void construct(const Expression& expr,internal::true_type)\n    {\n      if((Options & int(StandardCompressedFormat)) && (!expr.isCompressed()))\n      {\n        TPlainObjectType* obj = reinterpret_cast<TPlainObjectType*>(m_object_bytes);\n        ::new (obj) TPlainObjectType(expr);\n        m_hasCopy = true;\n        Base::construct(*obj);\n      }\n      else\n      {\n        Base::construct(expr);\n      }\n    }\n\n    template<typename Expression>\n    void construct(const Expression& expr, internal::false_type)\n    {\n      TPlainObjectType* obj = reinterpret_cast<TPlainObjectType*>(m_object_bytes);\n      ::new (obj) TPlainObjectType(expr);\n      m_hasCopy = true;\n      Base::construct(*obj);\n    }\n\n  protected:\n    char m_object_bytes[sizeof(TPlainObjectType)];\n    bool m_hasCopy;\n};\n\n\n\n/**\n  * \\ingroup SparseCore_Module\n  *\n  * \\brief A sparse vector expression referencing an existing sparse vector expression\n  *\n  * \\tparam SparseVectorType the equivalent sparse vector type of the referenced data, it must be a template instance of class SparseVector.\n  *\n  * \\sa class Ref\n  */\n#ifndef EIGEN_PARSED_BY_DOXYGEN\ntemplate<typename MatScalar, int MatOptions, typename MatIndex, int Options, typename StrideType>\nclass Ref<SparseVector<MatScalar,MatOptions,MatIndex>, Options, StrideType >\n  : public internal::SparseRefBase<Ref<SparseVector<MatScalar,MatOptions,MatIndex>, Options, StrideType > >\n#else\ntemplate<typename SparseVectorType>\nclass Ref<SparseVectorType>\n  : public SparseMapBase<Derived,WriteAccessors>\n#endif\n{\n    typedef SparseVector<MatScalar,MatOptions,MatIndex> PlainObjectType;\n    typedef internal::traits<Ref> Traits;\n    template<int OtherOptions>\n    inline Ref(const SparseVector<MatScalar,OtherOptions,MatIndex>& expr);\n  public:\n\n    typedef internal::SparseRefBase<Ref> Base;\n    EIGEN_SPARSE_PUBLIC_INTERFACE(Ref)\n\n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    template<int OtherOptions>\n    inline Ref(SparseVector<MatScalar,OtherOptions,MatIndex>& expr)\n    {\n      EIGEN_STATIC_ASSERT(bool(Traits::template match<SparseVector<MatScalar,OtherOptions,MatIndex> >::MatchAtCompileTime), STORAGE_LAYOUT_DOES_NOT_MATCH);\n      Base::construct(expr.derived());\n    }\n\n    template<typename Derived>\n    inline Ref(const SparseCompressedBase<Derived>& expr)\n    #else\n    /** Implicit constructor from any 1D sparse vector expression */\n    template<typename Derived>\n    inline Ref(SparseCompressedBase<Derived>& expr)\n    #endif\n    {\n      EIGEN_STATIC_ASSERT(bool(internal::is_lvalue<Derived>::value), THIS_EXPRESSION_IS_NOT_A_LVALUE__IT_IS_READ_ONLY);\n      EIGEN_STATIC_ASSERT(bool(Traits::template match<Derived>::MatchAtCompileTime), STORAGE_LAYOUT_DOES_NOT_MATCH);\n      Base::construct(expr.const_cast_derived());\n    }\n};\n\n// this is the const ref version\ntemplate<typename MatScalar, int MatOptions, typename MatIndex, int Options, typename StrideType>\nclass Ref<const SparseVector<MatScalar,MatOptions,MatIndex>, Options, StrideType>\n  : public internal::SparseRefBase<Ref<const SparseVector<MatScalar,MatOptions,MatIndex>, Options, StrideType> >\n{\n    typedef SparseVector<MatScalar,MatOptions,MatIndex> TPlainObjectType;\n    typedef internal::traits<Ref> Traits;\n  public:\n\n    typedef internal::SparseRefBase<Ref> Base;\n    EIGEN_SPARSE_PUBLIC_INTERFACE(Ref)\n\n    template<typename Derived>\n    inline Ref(const SparseMatrixBase<Derived>& expr) : m_hasCopy(false)\n    {\n      construct(expr.derived(), typename Traits::template match<Derived>::type());\n    }\n\n    inline Ref(const Ref& other) : Base(other), m_hasCopy(false) {\n      // copy constructor shall not copy the m_object, to avoid unnecessary malloc and copy\n    }\n\n    template<typename OtherRef>\n    inline Ref(const RefBase<OtherRef>& other) : m_hasCopy(false) {\n      construct(other.derived(), typename Traits::template match<OtherRef>::type());\n    }\n\n    ~Ref() {\n      if(m_hasCopy) {\n        TPlainObjectType* obj = reinterpret_cast<TPlainObjectType*>(m_object_bytes);\n        obj->~TPlainObjectType();\n      }\n    }\n\n  protected:\n\n    template<typename Expression>\n    void construct(const Expression& expr,internal::true_type)\n    {\n      Base::construct(expr);\n    }\n\n    template<typename Expression>\n    void construct(const Expression& expr, internal::false_type)\n    {\n      TPlainObjectType* obj = reinterpret_cast<TPlainObjectType*>(m_object_bytes);\n      ::new (obj) TPlainObjectType(expr);\n      m_hasCopy = true;\n      Base::construct(*obj);\n    }\n\n  protected:\n    char m_object_bytes[sizeof(TPlainObjectType)];\n    bool m_hasCopy;\n};\n\nnamespace internal {\n\n// FIXME shall we introduce a general evaluatior_ref that we can specialize for any sparse object once, and thus remove this copy-pasta thing...\n\ntemplate<typename MatScalar, int MatOptions, typename MatIndex, int Options, typename StrideType>\nstruct evaluator<Ref<SparseMatrix<MatScalar,MatOptions,MatIndex>, Options, StrideType> >\n  : evaluator<SparseCompressedBase<Ref<SparseMatrix<MatScalar,MatOptions,MatIndex>, Options, StrideType> > >\n{\n  typedef evaluator<SparseCompressedBase<Ref<SparseMatrix<MatScalar,MatOptions,MatIndex>, Options, StrideType> > > Base;\n  typedef Ref<SparseMatrix<MatScalar,MatOptions,MatIndex>, Options, StrideType> XprType;  \n  evaluator() : Base() {}\n  explicit evaluator(const XprType &mat) : Base(mat) {}\n};\n\ntemplate<typename MatScalar, int MatOptions, typename MatIndex, int Options, typename StrideType>\nstruct evaluator<Ref<const SparseMatrix<MatScalar,MatOptions,MatIndex>, Options, StrideType> >\n  : evaluator<SparseCompressedBase<Ref<const SparseMatrix<MatScalar,MatOptions,MatIndex>, Options, StrideType> > >\n{\n  typedef evaluator<SparseCompressedBase<Ref<const SparseMatrix<MatScalar,MatOptions,MatIndex>, Options, StrideType> > > Base;\n  typedef Ref<const SparseMatrix<MatScalar,MatOptions,MatIndex>, Options, StrideType> XprType;  \n  evaluator() : Base() {}\n  explicit evaluator(const XprType &mat) : Base(mat) {}\n};\n\ntemplate<typename MatScalar, int MatOptions, typename MatIndex, int Options, typename StrideType>\nstruct evaluator<Ref<SparseVector<MatScalar,MatOptions,MatIndex>, Options, StrideType> >\n  : evaluator<SparseCompressedBase<Ref<SparseVector<MatScalar,MatOptions,MatIndex>, Options, StrideType> > >\n{\n  typedef evaluator<SparseCompressedBase<Ref<SparseVector<MatScalar,MatOptions,MatIndex>, Options, StrideType> > > Base;\n  typedef Ref<SparseVector<MatScalar,MatOptions,MatIndex>, Options, StrideType> XprType;\n  evaluator() : Base() {}\n  explicit evaluator(const XprType &mat) : Base(mat) {}\n};\n\ntemplate<typename MatScalar, int MatOptions, typename MatIndex, int Options, typename StrideType>\nstruct evaluator<Ref<const SparseVector<MatScalar,MatOptions,MatIndex>, Options, StrideType> >\n  : evaluator<SparseCompressedBase<Ref<const SparseVector<MatScalar,MatOptions,MatIndex>, Options, StrideType> > >\n{\n  typedef evaluator<SparseCompressedBase<Ref<const SparseVector<MatScalar,MatOptions,MatIndex>, Options, StrideType> > > Base;\n  typedef Ref<const SparseVector<MatScalar,MatOptions,MatIndex>, Options, StrideType> XprType;\n  evaluator() : Base() {}\n  explicit evaluator(const XprType &mat) : Base(mat) {}\n};\n\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_SPARSE_REF_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseCore/SparseSelfAdjointView.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009-2014 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SPARSE_SELFADJOINTVIEW_H\n#define EIGEN_SPARSE_SELFADJOINTVIEW_H\n\nnamespace Eigen { \n  \n/** \\ingroup SparseCore_Module\n  * \\class SparseSelfAdjointView\n  *\n  * \\brief Pseudo expression to manipulate a triangular sparse matrix as a selfadjoint matrix.\n  *\n  * \\param MatrixType the type of the dense matrix storing the coefficients\n  * \\param Mode can be either \\c #Lower or \\c #Upper\n  *\n  * This class is an expression of a sefladjoint matrix from a triangular part of a matrix\n  * with given dense storage of the coefficients. It is the return type of MatrixBase::selfadjointView()\n  * and most of the time this is the only way that it is used.\n  *\n  * \\sa SparseMatrixBase::selfadjointView()\n  */\nnamespace internal {\n  \ntemplate<typename MatrixType, unsigned int Mode>\nstruct traits<SparseSelfAdjointView<MatrixType,Mode> > : traits<MatrixType> {\n};\n\ntemplate<int SrcMode,int DstMode,typename MatrixType,int DestOrder>\nvoid permute_symm_to_symm(const MatrixType& mat, SparseMatrix<typename MatrixType::Scalar,DestOrder,typename MatrixType::StorageIndex>& _dest, const typename MatrixType::StorageIndex* perm = 0);\n\ntemplate<int Mode,typename MatrixType,int DestOrder>\nvoid permute_symm_to_fullsymm(const MatrixType& mat, SparseMatrix<typename MatrixType::Scalar,DestOrder,typename MatrixType::StorageIndex>& _dest, const typename MatrixType::StorageIndex* perm = 0);\n\n}\n\ntemplate<typename MatrixType, unsigned int _Mode> class SparseSelfAdjointView\n  : public EigenBase<SparseSelfAdjointView<MatrixType,_Mode> >\n{\n  public:\n    \n    enum {\n      Mode = _Mode,\n      RowsAtCompileTime = internal::traits<SparseSelfAdjointView>::RowsAtCompileTime,\n      ColsAtCompileTime = internal::traits<SparseSelfAdjointView>::ColsAtCompileTime\n    };\n\n    typedef EigenBase<SparseSelfAdjointView> Base;\n    typedef typename MatrixType::Scalar Scalar;\n    typedef typename MatrixType::StorageIndex StorageIndex;\n    typedef Matrix<StorageIndex,Dynamic,1> VectorI;\n    typedef typename internal::ref_selector<MatrixType>::non_const_type MatrixTypeNested;\n    typedef typename internal::remove_all<MatrixTypeNested>::type _MatrixTypeNested;\n    \n    explicit inline SparseSelfAdjointView(MatrixType& matrix) : m_matrix(matrix)\n    {\n      eigen_assert(rows()==cols() && \"SelfAdjointView is only for squared matrices\");\n    }\n\n    inline Index rows() const { return m_matrix.rows(); }\n    inline Index cols() const { return m_matrix.cols(); }\n\n    /** \\internal \\returns a reference to the nested matrix */\n    const _MatrixTypeNested& matrix() const { return m_matrix; }\n    typename internal::remove_reference<MatrixTypeNested>::type& matrix() { return m_matrix; }\n\n    /** \\returns an expression of the matrix product between a sparse self-adjoint matrix \\c *this and a sparse matrix \\a rhs.\n      *\n      * Note that there is no algorithmic advantage of performing such a product compared to a general sparse-sparse matrix product.\n      * Indeed, the SparseSelfadjointView operand is first copied into a temporary SparseMatrix before computing the product.\n      */\n    template<typename OtherDerived>\n    Product<SparseSelfAdjointView, OtherDerived>\n    operator*(const SparseMatrixBase<OtherDerived>& rhs) const\n    {\n      return Product<SparseSelfAdjointView, OtherDerived>(*this, rhs.derived());\n    }\n\n    /** \\returns an expression of the matrix product between a sparse matrix \\a lhs and a sparse self-adjoint matrix \\a rhs.\n      *\n      * Note that there is no algorithmic advantage of performing such a product compared to a general sparse-sparse matrix product.\n      * Indeed, the SparseSelfadjointView operand is first copied into a temporary SparseMatrix before computing the product.\n      */\n    template<typename OtherDerived> friend\n    Product<OtherDerived, SparseSelfAdjointView>\n    operator*(const SparseMatrixBase<OtherDerived>& lhs, const SparseSelfAdjointView& rhs)\n    {\n      return Product<OtherDerived, SparseSelfAdjointView>(lhs.derived(), rhs);\n    }\n    \n    /** Efficient sparse self-adjoint matrix times dense vector/matrix product */\n    template<typename OtherDerived>\n    Product<SparseSelfAdjointView,OtherDerived>\n    operator*(const MatrixBase<OtherDerived>& rhs) const\n    {\n      return Product<SparseSelfAdjointView,OtherDerived>(*this, rhs.derived());\n    }\n\n    /** Efficient dense vector/matrix times sparse self-adjoint matrix product */\n    template<typename OtherDerived> friend\n    Product<OtherDerived,SparseSelfAdjointView>\n    operator*(const MatrixBase<OtherDerived>& lhs, const SparseSelfAdjointView& rhs)\n    {\n      return Product<OtherDerived,SparseSelfAdjointView>(lhs.derived(), rhs);\n    }\n\n    /** Perform a symmetric rank K update of the selfadjoint matrix \\c *this:\n      * \\f$ this = this + \\alpha ( u u^* ) \\f$ where \\a u is a vector or matrix.\n      *\n      * \\returns a reference to \\c *this\n      *\n      * To perform \\f$ this = this + \\alpha ( u^* u ) \\f$ you can simply\n      * call this function with u.adjoint().\n      */\n    template<typename DerivedU>\n    SparseSelfAdjointView& rankUpdate(const SparseMatrixBase<DerivedU>& u, const Scalar& alpha = Scalar(1));\n    \n    /** \\returns an expression of P H P^-1 */\n    // TODO implement twists in a more evaluator friendly fashion\n    SparseSymmetricPermutationProduct<_MatrixTypeNested,Mode> twistedBy(const PermutationMatrix<Dynamic,Dynamic,StorageIndex>& perm) const\n    {\n      return SparseSymmetricPermutationProduct<_MatrixTypeNested,Mode>(m_matrix, perm);\n    }\n\n    template<typename SrcMatrixType,int SrcMode>\n    SparseSelfAdjointView& operator=(const SparseSymmetricPermutationProduct<SrcMatrixType,SrcMode>& permutedMatrix)\n    {\n      internal::call_assignment_no_alias_no_transpose(*this, permutedMatrix);\n      return *this;\n    }\n\n    SparseSelfAdjointView& operator=(const SparseSelfAdjointView& src)\n    {\n      PermutationMatrix<Dynamic,Dynamic,StorageIndex> pnull;\n      return *this = src.twistedBy(pnull);\n    }\n\n    template<typename SrcMatrixType,unsigned int SrcMode>\n    SparseSelfAdjointView& operator=(const SparseSelfAdjointView<SrcMatrixType,SrcMode>& src)\n    {\n      PermutationMatrix<Dynamic,Dynamic,StorageIndex> pnull;\n      return *this = src.twistedBy(pnull);\n    }\n    \n    void resize(Index rows, Index cols)\n    {\n      EIGEN_ONLY_USED_FOR_DEBUG(rows);\n      EIGEN_ONLY_USED_FOR_DEBUG(cols);\n      eigen_assert(rows == this->rows() && cols == this->cols()\n                && \"SparseSelfadjointView::resize() does not actually allow to resize.\");\n    }\n    \n  protected:\n\n    MatrixTypeNested m_matrix;\n    //mutable VectorI m_countPerRow;\n    //mutable VectorI m_countPerCol;\n  private:\n    template<typename Dest> void evalTo(Dest &) const;\n};\n\n/***************************************************************************\n* Implementation of SparseMatrixBase methods\n***************************************************************************/\n\ntemplate<typename Derived>\ntemplate<unsigned int UpLo>\ntypename SparseMatrixBase<Derived>::template ConstSelfAdjointViewReturnType<UpLo>::Type SparseMatrixBase<Derived>::selfadjointView() const\n{\n  return SparseSelfAdjointView<const Derived, UpLo>(derived());\n}\n\ntemplate<typename Derived>\ntemplate<unsigned int UpLo>\ntypename SparseMatrixBase<Derived>::template SelfAdjointViewReturnType<UpLo>::Type SparseMatrixBase<Derived>::selfadjointView()\n{\n  return SparseSelfAdjointView<Derived, UpLo>(derived());\n}\n\n/***************************************************************************\n* Implementation of SparseSelfAdjointView methods\n***************************************************************************/\n\ntemplate<typename MatrixType, unsigned int Mode>\ntemplate<typename DerivedU>\nSparseSelfAdjointView<MatrixType,Mode>&\nSparseSelfAdjointView<MatrixType,Mode>::rankUpdate(const SparseMatrixBase<DerivedU>& u, const Scalar& alpha)\n{\n  SparseMatrix<Scalar,(MatrixType::Flags&RowMajorBit)?RowMajor:ColMajor> tmp = u * u.adjoint();\n  if(alpha==Scalar(0))\n    m_matrix = tmp.template triangularView<Mode>();\n  else\n    m_matrix += alpha * tmp.template triangularView<Mode>();\n\n  return *this;\n}\n\nnamespace internal {\n  \n// TODO currently a selfadjoint expression has the form SelfAdjointView<.,.>\n//      in the future selfadjoint-ness should be defined by the expression traits\n//      such that Transpose<SelfAdjointView<.,.> > is valid. (currently TriangularBase::transpose() is overloaded to make it work)\ntemplate<typename MatrixType, unsigned int Mode>\nstruct evaluator_traits<SparseSelfAdjointView<MatrixType,Mode> >\n{\n  typedef typename storage_kind_to_evaluator_kind<typename MatrixType::StorageKind>::Kind Kind;\n  typedef SparseSelfAdjointShape Shape;\n};\n\nstruct SparseSelfAdjoint2Sparse {};\n\ntemplate<> struct AssignmentKind<SparseShape,SparseSelfAdjointShape> { typedef SparseSelfAdjoint2Sparse Kind; };\ntemplate<> struct AssignmentKind<SparseSelfAdjointShape,SparseShape> { typedef Sparse2Sparse Kind; };\n\ntemplate< typename DstXprType, typename SrcXprType, typename Functor>\nstruct Assignment<DstXprType, SrcXprType, Functor, SparseSelfAdjoint2Sparse>\n{\n  typedef typename DstXprType::StorageIndex StorageIndex;\n  template<typename DestScalar,int StorageOrder>\n  static void run(SparseMatrix<DestScalar,StorageOrder,StorageIndex> &dst, const SrcXprType &src, const internal::assign_op<typename DstXprType::Scalar,typename SrcXprType::Scalar> &/*func*/)\n  {\n    internal::permute_symm_to_fullsymm<SrcXprType::Mode>(src.matrix(), dst);\n  }\n  \n  template<typename DestScalar>\n  static void run(DynamicSparseMatrix<DestScalar,ColMajor,StorageIndex>& dst, const SrcXprType &src, const internal::assign_op<typename DstXprType::Scalar,typename SrcXprType::Scalar> &/*func*/)\n  {\n    // TODO directly evaluate into dst;\n    SparseMatrix<DestScalar,ColMajor,StorageIndex> tmp(dst.rows(),dst.cols());\n    internal::permute_symm_to_fullsymm<SrcXprType::Mode>(src.matrix(), tmp);\n    dst = tmp;\n  }\n};\n\n} // end namespace internal\n\n/***************************************************************************\n* Implementation of sparse self-adjoint time dense matrix\n***************************************************************************/\n\nnamespace internal {\n\ntemplate<int Mode, typename SparseLhsType, typename DenseRhsType, typename DenseResType, typename AlphaType>\ninline void sparse_selfadjoint_time_dense_product(const SparseLhsType& lhs, const DenseRhsType& rhs, DenseResType& res, const AlphaType& alpha)\n{\n  EIGEN_ONLY_USED_FOR_DEBUG(alpha);\n  \n  typedef typename internal::nested_eval<SparseLhsType,DenseRhsType::MaxColsAtCompileTime>::type SparseLhsTypeNested;\n  typedef typename internal::remove_all<SparseLhsTypeNested>::type SparseLhsTypeNestedCleaned;\n  typedef evaluator<SparseLhsTypeNestedCleaned> LhsEval;\n  typedef typename LhsEval::InnerIterator LhsIterator;\n  typedef typename SparseLhsType::Scalar LhsScalar;\n  \n  enum {\n    LhsIsRowMajor = (LhsEval::Flags&RowMajorBit)==RowMajorBit,\n    ProcessFirstHalf =\n              ((Mode&(Upper|Lower))==(Upper|Lower))\n          || ( (Mode&Upper) && !LhsIsRowMajor)\n          || ( (Mode&Lower) && LhsIsRowMajor),\n    ProcessSecondHalf = !ProcessFirstHalf\n  };\n  \n  SparseLhsTypeNested lhs_nested(lhs);\n  LhsEval lhsEval(lhs_nested);\n\n  // work on one column at once\n  for (Index k=0; k<rhs.cols(); ++k)\n  {\n    for (Index j=0; j<lhs.outerSize(); ++j)\n    {\n      LhsIterator i(lhsEval,j);\n      // handle diagonal coeff\n      if (ProcessSecondHalf)\n      {\n        while (i && i.index()<j) ++i;\n        if(i && i.index()==j)\n        {\n          res(j,k) += alpha * i.value() * rhs(j,k);\n          ++i;\n        }\n      }\n\n      // premultiplied rhs for scatters\n      typename ScalarBinaryOpTraits<AlphaType, typename DenseRhsType::Scalar>::ReturnType rhs_j(alpha*rhs(j,k));\n      // accumulator for partial scalar product\n      typename DenseResType::Scalar res_j(0);\n      for(; (ProcessFirstHalf ? i && i.index() < j : i) ; ++i)\n      {\n        LhsScalar lhs_ij = i.value();\n        if(!LhsIsRowMajor) lhs_ij = numext::conj(lhs_ij);\n        res_j += lhs_ij * rhs(i.index(),k);\n        res(i.index(),k) += numext::conj(lhs_ij) * rhs_j;\n      }\n      res(j,k) += alpha * res_j;\n\n      // handle diagonal coeff\n      if (ProcessFirstHalf && i && (i.index()==j))\n        res(j,k) += alpha * i.value() * rhs(j,k);\n    }\n  }\n}\n\n\ntemplate<typename LhsView, typename Rhs, int ProductType>\nstruct generic_product_impl<LhsView, Rhs, SparseSelfAdjointShape, DenseShape, ProductType>\n: generic_product_impl_base<LhsView, Rhs, generic_product_impl<LhsView, Rhs, SparseSelfAdjointShape, DenseShape, ProductType> >\n{\n  template<typename Dest>\n  static void scaleAndAddTo(Dest& dst, const LhsView& lhsView, const Rhs& rhs, const typename Dest::Scalar& alpha)\n  {\n    typedef typename LhsView::_MatrixTypeNested Lhs;\n    typedef typename nested_eval<Lhs,Dynamic>::type LhsNested;\n    typedef typename nested_eval<Rhs,Dynamic>::type RhsNested;\n    LhsNested lhsNested(lhsView.matrix());\n    RhsNested rhsNested(rhs);\n    \n    internal::sparse_selfadjoint_time_dense_product<LhsView::Mode>(lhsNested, rhsNested, dst, alpha);\n  }\n};\n\ntemplate<typename Lhs, typename RhsView, int ProductType>\nstruct generic_product_impl<Lhs, RhsView, DenseShape, SparseSelfAdjointShape, ProductType>\n: generic_product_impl_base<Lhs, RhsView, generic_product_impl<Lhs, RhsView, DenseShape, SparseSelfAdjointShape, ProductType> >\n{\n  template<typename Dest>\n  static void scaleAndAddTo(Dest& dst, const Lhs& lhs, const RhsView& rhsView, const typename Dest::Scalar& alpha)\n  {\n    typedef typename RhsView::_MatrixTypeNested Rhs;\n    typedef typename nested_eval<Lhs,Dynamic>::type LhsNested;\n    typedef typename nested_eval<Rhs,Dynamic>::type RhsNested;\n    LhsNested lhsNested(lhs);\n    RhsNested rhsNested(rhsView.matrix());\n    \n    // transpose everything\n    Transpose<Dest> dstT(dst);\n    internal::sparse_selfadjoint_time_dense_product<RhsView::Mode>(rhsNested.transpose(), lhsNested.transpose(), dstT, alpha);\n  }\n};\n\n// NOTE: these two overloads are needed to evaluate the sparse selfadjoint view into a full sparse matrix\n// TODO: maybe the copy could be handled by generic_product_impl so that these overloads would not be needed anymore\n\ntemplate<typename LhsView, typename Rhs, int ProductTag>\nstruct product_evaluator<Product<LhsView, Rhs, DefaultProduct>, ProductTag, SparseSelfAdjointShape, SparseShape>\n  : public evaluator<typename Product<typename Rhs::PlainObject, Rhs, DefaultProduct>::PlainObject>\n{\n  typedef Product<LhsView, Rhs, DefaultProduct> XprType;\n  typedef typename XprType::PlainObject PlainObject;\n  typedef evaluator<PlainObject> Base;\n\n  product_evaluator(const XprType& xpr)\n    : m_lhs(xpr.lhs()), m_result(xpr.rows(), xpr.cols())\n  {\n    ::new (static_cast<Base*>(this)) Base(m_result);\n    generic_product_impl<typename Rhs::PlainObject, Rhs, SparseShape, SparseShape, ProductTag>::evalTo(m_result, m_lhs, xpr.rhs());\n  }\n  \nprotected:\n  typename Rhs::PlainObject m_lhs;\n  PlainObject m_result;\n};\n\ntemplate<typename Lhs, typename RhsView, int ProductTag>\nstruct product_evaluator<Product<Lhs, RhsView, DefaultProduct>, ProductTag, SparseShape, SparseSelfAdjointShape>\n  : public evaluator<typename Product<Lhs, typename Lhs::PlainObject, DefaultProduct>::PlainObject>\n{\n  typedef Product<Lhs, RhsView, DefaultProduct> XprType;\n  typedef typename XprType::PlainObject PlainObject;\n  typedef evaluator<PlainObject> Base;\n\n  product_evaluator(const XprType& xpr)\n    : m_rhs(xpr.rhs()), m_result(xpr.rows(), xpr.cols())\n  {\n    ::new (static_cast<Base*>(this)) Base(m_result);\n    generic_product_impl<Lhs, typename Lhs::PlainObject, SparseShape, SparseShape, ProductTag>::evalTo(m_result, xpr.lhs(), m_rhs);\n  }\n  \nprotected:\n  typename Lhs::PlainObject m_rhs;\n  PlainObject m_result;\n};\n\n} // namespace internal\n\n/***************************************************************************\n* Implementation of symmetric copies and permutations\n***************************************************************************/\nnamespace internal {\n\ntemplate<int Mode,typename MatrixType,int DestOrder>\nvoid permute_symm_to_fullsymm(const MatrixType& mat, SparseMatrix<typename MatrixType::Scalar,DestOrder,typename MatrixType::StorageIndex>& _dest, const typename MatrixType::StorageIndex* perm)\n{\n  typedef typename MatrixType::StorageIndex StorageIndex;\n  typedef typename MatrixType::Scalar Scalar;\n  typedef SparseMatrix<Scalar,DestOrder,StorageIndex> Dest;\n  typedef Matrix<StorageIndex,Dynamic,1> VectorI;\n  typedef evaluator<MatrixType> MatEval;\n  typedef typename evaluator<MatrixType>::InnerIterator MatIterator;\n  \n  MatEval matEval(mat);\n  Dest& dest(_dest.derived());\n  enum {\n    StorageOrderMatch = int(Dest::IsRowMajor) == int(MatrixType::IsRowMajor)\n  };\n  \n  Index size = mat.rows();\n  VectorI count;\n  count.resize(size);\n  count.setZero();\n  dest.resize(size,size);\n  for(Index j = 0; j<size; ++j)\n  {\n    Index jp = perm ? perm[j] : j;\n    for(MatIterator it(matEval,j); it; ++it)\n    {\n      Index i = it.index();\n      Index r = it.row();\n      Index c = it.col();\n      Index ip = perm ? perm[i] : i;\n      if(Mode==(Upper|Lower))\n        count[StorageOrderMatch ? jp : ip]++;\n      else if(r==c)\n        count[ip]++;\n      else if(( Mode==Lower && r>c) || ( Mode==Upper && r<c))\n      {\n        count[ip]++;\n        count[jp]++;\n      }\n    }\n  }\n  Index nnz = count.sum();\n  \n  // reserve space\n  dest.resizeNonZeros(nnz);\n  dest.outerIndexPtr()[0] = 0;\n  for(Index j=0; j<size; ++j)\n    dest.outerIndexPtr()[j+1] = dest.outerIndexPtr()[j] + count[j];\n  for(Index j=0; j<size; ++j)\n    count[j] = dest.outerIndexPtr()[j];\n  \n  // copy data\n  for(StorageIndex j = 0; j<size; ++j)\n  {\n    for(MatIterator it(matEval,j); it; ++it)\n    {\n      StorageIndex i = internal::convert_index<StorageIndex>(it.index());\n      Index r = it.row();\n      Index c = it.col();\n      \n      StorageIndex jp = perm ? perm[j] : j;\n      StorageIndex ip = perm ? perm[i] : i;\n      \n      if(Mode==(Upper|Lower))\n      {\n        Index k = count[StorageOrderMatch ? jp : ip]++;\n        dest.innerIndexPtr()[k] = StorageOrderMatch ? ip : jp;\n        dest.valuePtr()[k] = it.value();\n      }\n      else if(r==c)\n      {\n        Index k = count[ip]++;\n        dest.innerIndexPtr()[k] = ip;\n        dest.valuePtr()[k] = it.value();\n      }\n      else if(( (Mode&Lower)==Lower && r>c) || ( (Mode&Upper)==Upper && r<c))\n      {\n        if(!StorageOrderMatch)\n          std::swap(ip,jp);\n        Index k = count[jp]++;\n        dest.innerIndexPtr()[k] = ip;\n        dest.valuePtr()[k] = it.value();\n        k = count[ip]++;\n        dest.innerIndexPtr()[k] = jp;\n        dest.valuePtr()[k] = numext::conj(it.value());\n      }\n    }\n  }\n}\n\ntemplate<int _SrcMode,int _DstMode,typename MatrixType,int DstOrder>\nvoid permute_symm_to_symm(const MatrixType& mat, SparseMatrix<typename MatrixType::Scalar,DstOrder,typename MatrixType::StorageIndex>& _dest, const typename MatrixType::StorageIndex* perm)\n{\n  typedef typename MatrixType::StorageIndex StorageIndex;\n  typedef typename MatrixType::Scalar Scalar;\n  SparseMatrix<Scalar,DstOrder,StorageIndex>& dest(_dest.derived());\n  typedef Matrix<StorageIndex,Dynamic,1> VectorI;\n  typedef evaluator<MatrixType> MatEval;\n  typedef typename evaluator<MatrixType>::InnerIterator MatIterator;\n\n  enum {\n    SrcOrder = MatrixType::IsRowMajor ? RowMajor : ColMajor,\n    StorageOrderMatch = int(SrcOrder) == int(DstOrder),\n    DstMode = DstOrder==RowMajor ? (_DstMode==Upper ? Lower : Upper) : _DstMode,\n    SrcMode = SrcOrder==RowMajor ? (_SrcMode==Upper ? Lower : Upper) : _SrcMode\n  };\n\n  MatEval matEval(mat);\n  \n  Index size = mat.rows();\n  VectorI count(size);\n  count.setZero();\n  dest.resize(size,size);\n  for(StorageIndex j = 0; j<size; ++j)\n  {\n    StorageIndex jp = perm ? perm[j] : j;\n    for(MatIterator it(matEval,j); it; ++it)\n    {\n      StorageIndex i = it.index();\n      if((int(SrcMode)==int(Lower) && i<j) || (int(SrcMode)==int(Upper) && i>j))\n        continue;\n                  \n      StorageIndex ip = perm ? perm[i] : i;\n      count[int(DstMode)==int(Lower) ? (std::min)(ip,jp) : (std::max)(ip,jp)]++;\n    }\n  }\n  dest.outerIndexPtr()[0] = 0;\n  for(Index j=0; j<size; ++j)\n    dest.outerIndexPtr()[j+1] = dest.outerIndexPtr()[j] + count[j];\n  dest.resizeNonZeros(dest.outerIndexPtr()[size]);\n  for(Index j=0; j<size; ++j)\n    count[j] = dest.outerIndexPtr()[j];\n  \n  for(StorageIndex j = 0; j<size; ++j)\n  {\n    \n    for(MatIterator it(matEval,j); it; ++it)\n    {\n      StorageIndex i = it.index();\n      if((int(SrcMode)==int(Lower) && i<j) || (int(SrcMode)==int(Upper) && i>j))\n        continue;\n                  \n      StorageIndex jp = perm ? perm[j] : j;\n      StorageIndex ip = perm? perm[i] : i;\n      \n      Index k = count[int(DstMode)==int(Lower) ? (std::min)(ip,jp) : (std::max)(ip,jp)]++;\n      dest.innerIndexPtr()[k] = int(DstMode)==int(Lower) ? (std::max)(ip,jp) : (std::min)(ip,jp);\n      \n      if(!StorageOrderMatch) std::swap(ip,jp);\n      if( ((int(DstMode)==int(Lower) && ip<jp) || (int(DstMode)==int(Upper) && ip>jp)))\n        dest.valuePtr()[k] = numext::conj(it.value());\n      else\n        dest.valuePtr()[k] = it.value();\n    }\n  }\n}\n\n}\n\n// TODO implement twists in a more evaluator friendly fashion\n\nnamespace internal {\n\ntemplate<typename MatrixType, int Mode>\nstruct traits<SparseSymmetricPermutationProduct<MatrixType,Mode> > : traits<MatrixType> {\n};\n\n}\n\ntemplate<typename MatrixType,int Mode>\nclass SparseSymmetricPermutationProduct\n  : public EigenBase<SparseSymmetricPermutationProduct<MatrixType,Mode> >\n{\n  public:\n    typedef typename MatrixType::Scalar Scalar;\n    typedef typename MatrixType::StorageIndex StorageIndex;\n    enum {\n      RowsAtCompileTime = internal::traits<SparseSymmetricPermutationProduct>::RowsAtCompileTime,\n      ColsAtCompileTime = internal::traits<SparseSymmetricPermutationProduct>::ColsAtCompileTime\n    };\n  protected:\n    typedef PermutationMatrix<Dynamic,Dynamic,StorageIndex> Perm;\n  public:\n    typedef Matrix<StorageIndex,Dynamic,1> VectorI;\n    typedef typename MatrixType::Nested MatrixTypeNested;\n    typedef typename internal::remove_all<MatrixTypeNested>::type NestedExpression;\n    \n    SparseSymmetricPermutationProduct(const MatrixType& mat, const Perm& perm)\n      : m_matrix(mat), m_perm(perm)\n    {}\n    \n    inline Index rows() const { return m_matrix.rows(); }\n    inline Index cols() const { return m_matrix.cols(); }\n        \n    const NestedExpression& matrix() const { return m_matrix; }\n    const Perm& perm() const { return m_perm; }\n    \n  protected:\n    MatrixTypeNested m_matrix;\n    const Perm& m_perm;\n\n};\n\nnamespace internal {\n  \ntemplate<typename DstXprType, typename MatrixType, int Mode, typename Scalar>\nstruct Assignment<DstXprType, SparseSymmetricPermutationProduct<MatrixType,Mode>, internal::assign_op<Scalar,typename MatrixType::Scalar>, Sparse2Sparse>\n{\n  typedef SparseSymmetricPermutationProduct<MatrixType,Mode> SrcXprType;\n  typedef typename DstXprType::StorageIndex DstIndex;\n  template<int Options>\n  static void run(SparseMatrix<Scalar,Options,DstIndex> &dst, const SrcXprType &src, const internal::assign_op<Scalar,typename MatrixType::Scalar> &)\n  {\n    // internal::permute_symm_to_fullsymm<Mode>(m_matrix,_dest,m_perm.indices().data());\n    SparseMatrix<Scalar,(Options&RowMajor)==RowMajor ? ColMajor : RowMajor, DstIndex> tmp;\n    internal::permute_symm_to_fullsymm<Mode>(src.matrix(),tmp,src.perm().indices().data());\n    dst = tmp;\n  }\n  \n  template<typename DestType,unsigned int DestMode>\n  static void run(SparseSelfAdjointView<DestType,DestMode>& dst, const SrcXprType &src, const internal::assign_op<Scalar,typename MatrixType::Scalar> &)\n  {\n    internal::permute_symm_to_symm<Mode,DestMode>(src.matrix(),dst.matrix(),src.perm().indices().data());\n  }\n};\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_SPARSE_SELFADJOINTVIEW_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseCore/SparseSolverBase.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2014 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SPARSESOLVERBASE_H\n#define EIGEN_SPARSESOLVERBASE_H\n\nnamespace Eigen { \n\nnamespace internal {\n\n  /** \\internal\n  * Helper functions to solve with a sparse right-hand-side and result.\n  * The rhs is decomposed into small vertical panels which are solved through dense temporaries.\n  */\ntemplate<typename Decomposition, typename Rhs, typename Dest>\ntypename enable_if<Rhs::ColsAtCompileTime!=1 && Dest::ColsAtCompileTime!=1>::type\nsolve_sparse_through_dense_panels(const Decomposition &dec, const Rhs& rhs, Dest &dest)\n{\n  EIGEN_STATIC_ASSERT((Dest::Flags&RowMajorBit)==0,THIS_METHOD_IS_ONLY_FOR_COLUMN_MAJOR_MATRICES);\n  typedef typename Dest::Scalar DestScalar;\n  // we process the sparse rhs per block of NbColsAtOnce columns temporarily stored into a dense matrix.\n  static const Index NbColsAtOnce = 4;\n  Index rhsCols = rhs.cols();\n  Index size = rhs.rows();\n  // the temporary matrices do not need more columns than NbColsAtOnce:\n  Index tmpCols = (std::min)(rhsCols, NbColsAtOnce); \n  Eigen::Matrix<DestScalar,Dynamic,Dynamic> tmp(size,tmpCols);\n  Eigen::Matrix<DestScalar,Dynamic,Dynamic> tmpX(size,tmpCols);\n  for(Index k=0; k<rhsCols; k+=NbColsAtOnce)\n  {\n    Index actualCols = std::min<Index>(rhsCols-k, NbColsAtOnce);\n    tmp.leftCols(actualCols) = rhs.middleCols(k,actualCols);\n    tmpX.leftCols(actualCols) = dec.solve(tmp.leftCols(actualCols));\n    dest.middleCols(k,actualCols) = tmpX.leftCols(actualCols).sparseView();\n  }\n}\n\n// Overload for vector as rhs\ntemplate<typename Decomposition, typename Rhs, typename Dest>\ntypename enable_if<Rhs::ColsAtCompileTime==1 || Dest::ColsAtCompileTime==1>::type\nsolve_sparse_through_dense_panels(const Decomposition &dec, const Rhs& rhs, Dest &dest)\n{\n  typedef typename Dest::Scalar DestScalar;\n  Index size = rhs.rows();\n  Eigen::Matrix<DestScalar,Dynamic,1> rhs_dense(rhs);\n  Eigen::Matrix<DestScalar,Dynamic,1> dest_dense(size);\n  dest_dense = dec.solve(rhs_dense);\n  dest = dest_dense.sparseView();\n}\n\n} // end namespace internal\n\n/** \\class SparseSolverBase\n  * \\ingroup SparseCore_Module\n  * \\brief A base class for sparse solvers\n  *\n  * \\tparam Derived the actual type of the solver.\n  *\n  */\ntemplate<typename Derived>\nclass SparseSolverBase : internal::noncopyable\n{\n  public:\n\n    /** Default constructor */\n    SparseSolverBase()\n      : m_isInitialized(false)\n    {}\n\n    ~SparseSolverBase()\n    {}\n\n    Derived& derived() { return *static_cast<Derived*>(this); }\n    const Derived& derived() const { return *static_cast<const Derived*>(this); }\n    \n    /** \\returns an expression of the solution x of \\f$ A x = b \\f$ using the current decomposition of A.\n      *\n      * \\sa compute()\n      */\n    template<typename Rhs>\n    inline const Solve<Derived, Rhs>\n    solve(const MatrixBase<Rhs>& b) const\n    {\n      eigen_assert(m_isInitialized && \"Solver is not initialized.\");\n      eigen_assert(derived().rows()==b.rows() && \"solve(): invalid number of rows of the right hand side matrix b\");\n      return Solve<Derived, Rhs>(derived(), b.derived());\n    }\n    \n    /** \\returns an expression of the solution x of \\f$ A x = b \\f$ using the current decomposition of A.\n      *\n      * \\sa compute()\n      */\n    template<typename Rhs>\n    inline const Solve<Derived, Rhs>\n    solve(const SparseMatrixBase<Rhs>& b) const\n    {\n      eigen_assert(m_isInitialized && \"Solver is not initialized.\");\n      eigen_assert(derived().rows()==b.rows() && \"solve(): invalid number of rows of the right hand side matrix b\");\n      return Solve<Derived, Rhs>(derived(), b.derived());\n    }\n    \n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    /** \\internal default implementation of solving with a sparse rhs */\n    template<typename Rhs,typename Dest>\n    void _solve_impl(const SparseMatrixBase<Rhs> &b, SparseMatrixBase<Dest> &dest) const\n    {\n      internal::solve_sparse_through_dense_panels(derived(), b.derived(), dest.derived());\n    }\n    #endif // EIGEN_PARSED_BY_DOXYGEN\n\n  protected:\n    \n    mutable bool m_isInitialized;\n};\n\n} // end namespace Eigen\n\n#endif // EIGEN_SPARSESOLVERBASE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseCore/SparseSparseProductWithPruning.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2014 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SPARSESPARSEPRODUCTWITHPRUNING_H\n#define EIGEN_SPARSESPARSEPRODUCTWITHPRUNING_H\n\nnamespace Eigen { \n\nnamespace internal {\n\n\n// perform a pseudo in-place sparse * sparse product assuming all matrices are col major\ntemplate<typename Lhs, typename Rhs, typename ResultType>\nstatic void sparse_sparse_product_with_pruning_impl(const Lhs& lhs, const Rhs& rhs, ResultType& res, const typename ResultType::RealScalar& tolerance)\n{\n  // return sparse_sparse_product_with_pruning_impl2(lhs,rhs,res);\n\n  typedef typename remove_all<Lhs>::type::Scalar Scalar;\n  typedef typename remove_all<Lhs>::type::StorageIndex StorageIndex;\n\n  // make sure to call innerSize/outerSize since we fake the storage order.\n  Index rows = lhs.innerSize();\n  Index cols = rhs.outerSize();\n  //Index size = lhs.outerSize();\n  eigen_assert(lhs.outerSize() == rhs.innerSize());\n\n  // allocate a temporary buffer\n  AmbiVector<Scalar,StorageIndex> tempVector(rows);\n\n  // mimics a resizeByInnerOuter:\n  if(ResultType::IsRowMajor)\n    res.resize(cols, rows);\n  else\n    res.resize(rows, cols);\n  \n  evaluator<Lhs> lhsEval(lhs);\n  evaluator<Rhs> rhsEval(rhs);\n  \n  // estimate the number of non zero entries\n  // given a rhs column containing Y non zeros, we assume that the respective Y columns\n  // of the lhs differs in average of one non zeros, thus the number of non zeros for\n  // the product of a rhs column with the lhs is X+Y where X is the average number of non zero\n  // per column of the lhs.\n  // Therefore, we have nnz(lhs*rhs) = nnz(lhs) + nnz(rhs)\n  Index estimated_nnz_prod = lhsEval.nonZerosEstimate() + rhsEval.nonZerosEstimate();\n\n  res.reserve(estimated_nnz_prod);\n  double ratioColRes = double(estimated_nnz_prod)/(double(lhs.rows())*double(rhs.cols()));\n  for (Index j=0; j<cols; ++j)\n  {\n    // FIXME:\n    //double ratioColRes = (double(rhs.innerVector(j).nonZeros()) + double(lhs.nonZeros())/double(lhs.cols()))/double(lhs.rows());\n    // let's do a more accurate determination of the nnz ratio for the current column j of res\n    tempVector.init(ratioColRes);\n    tempVector.setZero();\n    for (typename evaluator<Rhs>::InnerIterator rhsIt(rhsEval, j); rhsIt; ++rhsIt)\n    {\n      // FIXME should be written like this: tmp += rhsIt.value() * lhs.col(rhsIt.index())\n      tempVector.restart();\n      Scalar x = rhsIt.value();\n      for (typename evaluator<Lhs>::InnerIterator lhsIt(lhsEval, rhsIt.index()); lhsIt; ++lhsIt)\n      {\n        tempVector.coeffRef(lhsIt.index()) += lhsIt.value() * x;\n      }\n    }\n    res.startVec(j);\n    for (typename AmbiVector<Scalar,StorageIndex>::Iterator it(tempVector,tolerance); it; ++it)\n      res.insertBackByOuterInner(j,it.index()) = it.value();\n  }\n  res.finalize();\n}\n\ntemplate<typename Lhs, typename Rhs, typename ResultType,\n  int LhsStorageOrder = traits<Lhs>::Flags&RowMajorBit,\n  int RhsStorageOrder = traits<Rhs>::Flags&RowMajorBit,\n  int ResStorageOrder = traits<ResultType>::Flags&RowMajorBit>\nstruct sparse_sparse_product_with_pruning_selector;\n\ntemplate<typename Lhs, typename Rhs, typename ResultType>\nstruct sparse_sparse_product_with_pruning_selector<Lhs,Rhs,ResultType,ColMajor,ColMajor,ColMajor>\n{\n  typedef typename traits<typename remove_all<Lhs>::type>::Scalar Scalar;\n  typedef typename ResultType::RealScalar RealScalar;\n\n  static void run(const Lhs& lhs, const Rhs& rhs, ResultType& res, const RealScalar& tolerance)\n  {\n    typename remove_all<ResultType>::type _res(res.rows(), res.cols());\n    internal::sparse_sparse_product_with_pruning_impl<Lhs,Rhs,ResultType>(lhs, rhs, _res, tolerance);\n    res.swap(_res);\n  }\n};\n\ntemplate<typename Lhs, typename Rhs, typename ResultType>\nstruct sparse_sparse_product_with_pruning_selector<Lhs,Rhs,ResultType,ColMajor,ColMajor,RowMajor>\n{\n  typedef typename ResultType::RealScalar RealScalar;\n  static void run(const Lhs& lhs, const Rhs& rhs, ResultType& res, const RealScalar& tolerance)\n  {\n    // we need a col-major matrix to hold the result\n    typedef SparseMatrix<typename ResultType::Scalar,ColMajor,typename ResultType::StorageIndex> SparseTemporaryType;\n    SparseTemporaryType _res(res.rows(), res.cols());\n    internal::sparse_sparse_product_with_pruning_impl<Lhs,Rhs,SparseTemporaryType>(lhs, rhs, _res, tolerance);\n    res = _res;\n  }\n};\n\ntemplate<typename Lhs, typename Rhs, typename ResultType>\nstruct sparse_sparse_product_with_pruning_selector<Lhs,Rhs,ResultType,RowMajor,RowMajor,RowMajor>\n{\n  typedef typename ResultType::RealScalar RealScalar;\n  static void run(const Lhs& lhs, const Rhs& rhs, ResultType& res, const RealScalar& tolerance)\n  {\n    // let's transpose the product to get a column x column product\n    typename remove_all<ResultType>::type _res(res.rows(), res.cols());\n    internal::sparse_sparse_product_with_pruning_impl<Rhs,Lhs,ResultType>(rhs, lhs, _res, tolerance);\n    res.swap(_res);\n  }\n};\n\ntemplate<typename Lhs, typename Rhs, typename ResultType>\nstruct sparse_sparse_product_with_pruning_selector<Lhs,Rhs,ResultType,RowMajor,RowMajor,ColMajor>\n{\n  typedef typename ResultType::RealScalar RealScalar;\n  static void run(const Lhs& lhs, const Rhs& rhs, ResultType& res, const RealScalar& tolerance)\n  {\n    typedef SparseMatrix<typename ResultType::Scalar,ColMajor,typename Lhs::StorageIndex> ColMajorMatrixLhs;\n    typedef SparseMatrix<typename ResultType::Scalar,ColMajor,typename Lhs::StorageIndex> ColMajorMatrixRhs;\n    ColMajorMatrixLhs colLhs(lhs);\n    ColMajorMatrixRhs colRhs(rhs);\n    internal::sparse_sparse_product_with_pruning_impl<ColMajorMatrixLhs,ColMajorMatrixRhs,ResultType>(colLhs, colRhs, res, tolerance);\n\n    // let's transpose the product to get a column x column product\n//     typedef SparseMatrix<typename ResultType::Scalar> SparseTemporaryType;\n//     SparseTemporaryType _res(res.cols(), res.rows());\n//     sparse_sparse_product_with_pruning_impl<Rhs,Lhs,SparseTemporaryType>(rhs, lhs, _res);\n//     res = _res.transpose();\n  }\n};\n\ntemplate<typename Lhs, typename Rhs, typename ResultType>\nstruct sparse_sparse_product_with_pruning_selector<Lhs,Rhs,ResultType,ColMajor,RowMajor,RowMajor>\n{\n  typedef typename ResultType::RealScalar RealScalar;\n  static void run(const Lhs& lhs, const Rhs& rhs, ResultType& res, const RealScalar& tolerance)\n  {\n    typedef SparseMatrix<typename ResultType::Scalar,RowMajor,typename Lhs::StorageIndex> RowMajorMatrixLhs;\n    RowMajorMatrixLhs rowLhs(lhs);\n    sparse_sparse_product_with_pruning_selector<RowMajorMatrixLhs,Rhs,ResultType,RowMajor,RowMajor>(rowLhs,rhs,res,tolerance);\n  }\n};\n\ntemplate<typename Lhs, typename Rhs, typename ResultType>\nstruct sparse_sparse_product_with_pruning_selector<Lhs,Rhs,ResultType,RowMajor,ColMajor,RowMajor>\n{\n  typedef typename ResultType::RealScalar RealScalar;\n  static void run(const Lhs& lhs, const Rhs& rhs, ResultType& res, const RealScalar& tolerance)\n  {\n    typedef SparseMatrix<typename ResultType::Scalar,RowMajor,typename Lhs::StorageIndex> RowMajorMatrixRhs;\n    RowMajorMatrixRhs rowRhs(rhs);\n    sparse_sparse_product_with_pruning_selector<Lhs,RowMajorMatrixRhs,ResultType,RowMajor,RowMajor,RowMajor>(lhs,rowRhs,res,tolerance);\n  }\n};\n\ntemplate<typename Lhs, typename Rhs, typename ResultType>\nstruct sparse_sparse_product_with_pruning_selector<Lhs,Rhs,ResultType,ColMajor,RowMajor,ColMajor>\n{\n  typedef typename ResultType::RealScalar RealScalar;\n  static void run(const Lhs& lhs, const Rhs& rhs, ResultType& res, const RealScalar& tolerance)\n  {\n    typedef SparseMatrix<typename ResultType::Scalar,ColMajor,typename Lhs::StorageIndex> ColMajorMatrixRhs;\n    ColMajorMatrixRhs colRhs(rhs);\n    internal::sparse_sparse_product_with_pruning_impl<Lhs,ColMajorMatrixRhs,ResultType>(lhs, colRhs, res, tolerance);\n  }\n};\n\ntemplate<typename Lhs, typename Rhs, typename ResultType>\nstruct sparse_sparse_product_with_pruning_selector<Lhs,Rhs,ResultType,RowMajor,ColMajor,ColMajor>\n{\n  typedef typename ResultType::RealScalar RealScalar;\n  static void run(const Lhs& lhs, const Rhs& rhs, ResultType& res, const RealScalar& tolerance)\n  {\n    typedef SparseMatrix<typename ResultType::Scalar,ColMajor,typename Lhs::StorageIndex> ColMajorMatrixLhs;\n    ColMajorMatrixLhs colLhs(lhs);\n    internal::sparse_sparse_product_with_pruning_impl<ColMajorMatrixLhs,Rhs,ResultType>(colLhs, rhs, res, tolerance);\n  }\n};\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_SPARSESPARSEPRODUCTWITHPRUNING_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseCore/SparseTranspose.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2015 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SPARSETRANSPOSE_H\n#define EIGEN_SPARSETRANSPOSE_H\n\nnamespace Eigen { \n\nnamespace internal {\n  template<typename MatrixType,int CompressedAccess=int(MatrixType::Flags&CompressedAccessBit)>\n  class SparseTransposeImpl\n    : public SparseMatrixBase<Transpose<MatrixType> >\n  {};\n  \n  template<typename MatrixType>\n  class SparseTransposeImpl<MatrixType,CompressedAccessBit>\n    : public SparseCompressedBase<Transpose<MatrixType> >\n  {\n    typedef SparseCompressedBase<Transpose<MatrixType> > Base;\n  public:\n    using Base::derived;\n    typedef typename Base::Scalar Scalar;\n    typedef typename Base::StorageIndex StorageIndex;\n\n    inline Index nonZeros() const { return derived().nestedExpression().nonZeros(); }\n    \n    inline const Scalar* valuePtr() const { return derived().nestedExpression().valuePtr(); }\n    inline const StorageIndex* innerIndexPtr() const { return derived().nestedExpression().innerIndexPtr(); }\n    inline const StorageIndex* outerIndexPtr() const { return derived().nestedExpression().outerIndexPtr(); }\n    inline const StorageIndex* innerNonZeroPtr() const { return derived().nestedExpression().innerNonZeroPtr(); }\n\n    inline Scalar* valuePtr() { return derived().nestedExpression().valuePtr(); }\n    inline StorageIndex* innerIndexPtr() { return derived().nestedExpression().innerIndexPtr(); }\n    inline StorageIndex* outerIndexPtr() { return derived().nestedExpression().outerIndexPtr(); }\n    inline StorageIndex* innerNonZeroPtr() { return derived().nestedExpression().innerNonZeroPtr(); }\n  };\n}\n  \ntemplate<typename MatrixType> class TransposeImpl<MatrixType,Sparse>\n  : public internal::SparseTransposeImpl<MatrixType>\n{\n  protected:\n    typedef internal::SparseTransposeImpl<MatrixType> Base;\n};\n\nnamespace internal {\n  \ntemplate<typename ArgType>\nstruct unary_evaluator<Transpose<ArgType>, IteratorBased>\n  : public evaluator_base<Transpose<ArgType> >\n{\n    typedef typename evaluator<ArgType>::InnerIterator        EvalIterator;\n  public:\n    typedef Transpose<ArgType> XprType;\n    \n    inline Index nonZerosEstimate() const {\n      return m_argImpl.nonZerosEstimate();\n    }\n\n    class InnerIterator : public EvalIterator\n    {\n    public:\n      EIGEN_STRONG_INLINE InnerIterator(const unary_evaluator& unaryOp, Index outer)\n        : EvalIterator(unaryOp.m_argImpl,outer)\n      {}\n      \n      Index row() const { return EvalIterator::col(); }\n      Index col() const { return EvalIterator::row(); }\n    };\n    \n    enum {\n      CoeffReadCost = evaluator<ArgType>::CoeffReadCost,\n      Flags = XprType::Flags\n    };\n    \n    explicit unary_evaluator(const XprType& op) :m_argImpl(op.nestedExpression()) {}\n\n  protected:\n    evaluator<ArgType> m_argImpl;\n};\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_SPARSETRANSPOSE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseCore/SparseTriangularView.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009-2015 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2012 Désiré Nuentsa-Wakam <desire.nuentsa_wakam@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SPARSE_TRIANGULARVIEW_H\n#define EIGEN_SPARSE_TRIANGULARVIEW_H\n\nnamespace Eigen {\n\n/** \\ingroup SparseCore_Module\n  *\n  * \\brief Base class for a triangular part in a \\b sparse matrix\n  *\n  * This class is an abstract base class of class TriangularView, and objects of type TriangularViewImpl cannot be instantiated.\n  * It extends class TriangularView with additional methods which are available for sparse expressions only.\n  *\n  * \\sa class TriangularView, SparseMatrixBase::triangularView()\n  */\ntemplate<typename MatrixType, unsigned int Mode> class TriangularViewImpl<MatrixType,Mode,Sparse>\n  : public SparseMatrixBase<TriangularView<MatrixType,Mode> >\n{\n    enum { SkipFirst = ((Mode&Lower) && !(MatrixType::Flags&RowMajorBit))\n                    || ((Mode&Upper) &&  (MatrixType::Flags&RowMajorBit)),\n           SkipLast = !SkipFirst,\n           SkipDiag = (Mode&ZeroDiag) ? 1 : 0,\n           HasUnitDiag = (Mode&UnitDiag) ? 1 : 0\n    };\n    \n    typedef TriangularView<MatrixType,Mode> TriangularViewType;\n    \n  protected:\n    // dummy solve function to make TriangularView happy.\n    void solve() const;\n\n    typedef SparseMatrixBase<TriangularViewType> Base;\n  public:\n    \n    EIGEN_SPARSE_PUBLIC_INTERFACE(TriangularViewType)\n    \n    typedef typename MatrixType::Nested MatrixTypeNested;\n    typedef typename internal::remove_reference<MatrixTypeNested>::type MatrixTypeNestedNonRef;\n    typedef typename internal::remove_all<MatrixTypeNested>::type MatrixTypeNestedCleaned;\n\n    template<typename RhsType, typename DstType>\n    EIGEN_DEVICE_FUNC\n    EIGEN_STRONG_INLINE void _solve_impl(const RhsType &rhs, DstType &dst) const {\n      if(!(internal::is_same<RhsType,DstType>::value && internal::extract_data(dst) == internal::extract_data(rhs)))\n        dst = rhs;\n      this->solveInPlace(dst);\n    }\n\n    template<typename OtherDerived> void solveInPlace(MatrixBase<OtherDerived>& other) const;\n    template<typename OtherDerived> void solveInPlace(SparseMatrixBase<OtherDerived>& other) const;\n  \n};\n\nnamespace internal {\n\ntemplate<typename ArgType, unsigned int Mode>\nstruct unary_evaluator<TriangularView<ArgType,Mode>, IteratorBased>\n : evaluator_base<TriangularView<ArgType,Mode> >\n{\n  typedef TriangularView<ArgType,Mode> XprType;\n  \nprotected:\n  \n  typedef typename XprType::Scalar Scalar;\n  typedef typename XprType::StorageIndex StorageIndex;\n  typedef typename evaluator<ArgType>::InnerIterator EvalIterator;\n  \n  enum { SkipFirst = ((Mode&Lower) && !(ArgType::Flags&RowMajorBit))\n                    || ((Mode&Upper) &&  (ArgType::Flags&RowMajorBit)),\n         SkipLast = !SkipFirst,\n         SkipDiag = (Mode&ZeroDiag) ? 1 : 0,\n         HasUnitDiag = (Mode&UnitDiag) ? 1 : 0\n  };\n  \npublic:\n  \n  enum {\n    CoeffReadCost = evaluator<ArgType>::CoeffReadCost,\n    Flags = XprType::Flags\n  };\n    \n  explicit unary_evaluator(const XprType &xpr) : m_argImpl(xpr.nestedExpression()), m_arg(xpr.nestedExpression()) {}\n  \n  inline Index nonZerosEstimate() const {\n    return m_argImpl.nonZerosEstimate();\n  }\n  \n  class InnerIterator : public EvalIterator\n  {\n      typedef EvalIterator Base;\n    public:\n\n      EIGEN_STRONG_INLINE InnerIterator(const unary_evaluator& xprEval, Index outer)\n        : Base(xprEval.m_argImpl,outer), m_returnOne(false), m_containsDiag(Base::outer()<xprEval.m_arg.innerSize())\n      {\n        if(SkipFirst)\n        {\n          while((*this) && ((HasUnitDiag||SkipDiag)  ? this->index()<=outer : this->index()<outer))\n            Base::operator++();\n          if(HasUnitDiag)\n            m_returnOne = m_containsDiag;\n        }\n        else if(HasUnitDiag && ((!Base::operator bool()) || Base::index()>=Base::outer()))\n        {\n          if((!SkipFirst) && Base::operator bool())\n            Base::operator++();\n          m_returnOne = m_containsDiag;\n        }\n      }\n\n      EIGEN_STRONG_INLINE InnerIterator& operator++()\n      {\n        if(HasUnitDiag && m_returnOne)\n          m_returnOne = false;\n        else\n        {\n          Base::operator++();\n          if(HasUnitDiag && (!SkipFirst) && ((!Base::operator bool()) || Base::index()>=Base::outer()))\n          {\n            if((!SkipFirst) && Base::operator bool())\n              Base::operator++();\n            m_returnOne = m_containsDiag;\n          }\n        }\n        return *this;\n      }\n      \n      EIGEN_STRONG_INLINE operator bool() const\n      {\n        if(HasUnitDiag && m_returnOne)\n          return true;\n        if(SkipFirst) return  Base::operator bool();\n        else\n        {\n          if (SkipDiag) return (Base::operator bool() && this->index() < this->outer());\n          else return (Base::operator bool() && this->index() <= this->outer());\n        }\n      }\n\n//       inline Index row() const { return (ArgType::Flags&RowMajorBit ? Base::outer() : this->index()); }\n//       inline Index col() const { return (ArgType::Flags&RowMajorBit ? this->index() : Base::outer()); }\n      inline StorageIndex index() const\n      {\n        if(HasUnitDiag && m_returnOne)  return internal::convert_index<StorageIndex>(Base::outer());\n        else                            return Base::index();\n      }\n      inline Scalar value() const\n      {\n        if(HasUnitDiag && m_returnOne)  return Scalar(1);\n        else                            return Base::value();\n      }\n\n    protected:\n      bool m_returnOne;\n      bool m_containsDiag;\n    private:\n      Scalar& valueRef();\n  };\n  \nprotected:\n  evaluator<ArgType> m_argImpl;\n  const ArgType& m_arg;\n};\n\n} // end namespace internal\n\ntemplate<typename Derived>\ntemplate<int Mode>\ninline const TriangularView<const Derived, Mode>\nSparseMatrixBase<Derived>::triangularView() const\n{\n  return TriangularView<const Derived, Mode>(derived());\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_SPARSE_TRIANGULARVIEW_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseCore/SparseUtil.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2014 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SPARSEUTIL_H\n#define EIGEN_SPARSEUTIL_H\n\nnamespace Eigen { \n\n#ifdef NDEBUG\n#define EIGEN_DBG_SPARSE(X)\n#else\n#define EIGEN_DBG_SPARSE(X) X\n#endif\n\n#define EIGEN_SPARSE_INHERIT_ASSIGNMENT_OPERATOR(Derived, Op) \\\ntemplate<typename OtherDerived> \\\nEIGEN_STRONG_INLINE Derived& operator Op(const Eigen::SparseMatrixBase<OtherDerived>& other) \\\n{ \\\n  return Base::operator Op(other.derived()); \\\n} \\\nEIGEN_STRONG_INLINE Derived& operator Op(const Derived& other) \\\n{ \\\n  return Base::operator Op(other); \\\n}\n\n#define EIGEN_SPARSE_INHERIT_SCALAR_ASSIGNMENT_OPERATOR(Derived, Op) \\\ntemplate<typename Other> \\\nEIGEN_STRONG_INLINE Derived& operator Op(const Other& scalar) \\\n{ \\\n  return Base::operator Op(scalar); \\\n}\n\n#define EIGEN_SPARSE_INHERIT_ASSIGNMENT_OPERATORS(Derived) \\\nEIGEN_SPARSE_INHERIT_ASSIGNMENT_OPERATOR(Derived, =)\n\n\n#define EIGEN_SPARSE_PUBLIC_INTERFACE(Derived) \\\n  EIGEN_GENERIC_PUBLIC_INTERFACE(Derived)\n\n  \nconst int CoherentAccessPattern     = 0x1;\nconst int InnerRandomAccessPattern  = 0x2 | CoherentAccessPattern;\nconst int OuterRandomAccessPattern  = 0x4 | CoherentAccessPattern;\nconst int RandomAccessPattern       = 0x8 | OuterRandomAccessPattern | InnerRandomAccessPattern;\n\ntemplate<typename _Scalar, int _Flags = 0, typename _StorageIndex = int>  class SparseMatrix;\ntemplate<typename _Scalar, int _Flags = 0, typename _StorageIndex = int>  class DynamicSparseMatrix;\ntemplate<typename _Scalar, int _Flags = 0, typename _StorageIndex = int>  class SparseVector;\ntemplate<typename _Scalar, int _Flags = 0, typename _StorageIndex = int>  class MappedSparseMatrix;\n\ntemplate<typename MatrixType, unsigned int UpLo>  class SparseSelfAdjointView;\ntemplate<typename Lhs, typename Rhs>              class SparseDiagonalProduct;\ntemplate<typename MatrixType> class SparseView;\n\ntemplate<typename Lhs, typename Rhs>        class SparseSparseProduct;\ntemplate<typename Lhs, typename Rhs>        class SparseTimeDenseProduct;\ntemplate<typename Lhs, typename Rhs>        class DenseTimeSparseProduct;\ntemplate<typename Lhs, typename Rhs, bool Transpose> class SparseDenseOuterProduct;\n\ntemplate<typename Lhs, typename Rhs> struct SparseSparseProductReturnType;\ntemplate<typename Lhs, typename Rhs,\n         int InnerSize = EIGEN_SIZE_MIN_PREFER_FIXED(internal::traits<Lhs>::ColsAtCompileTime,internal::traits<Rhs>::RowsAtCompileTime)> struct DenseSparseProductReturnType;\n         \ntemplate<typename Lhs, typename Rhs,\n         int InnerSize = EIGEN_SIZE_MIN_PREFER_FIXED(internal::traits<Lhs>::ColsAtCompileTime,internal::traits<Rhs>::RowsAtCompileTime)> struct SparseDenseProductReturnType;\ntemplate<typename MatrixType,int UpLo> class SparseSymmetricPermutationProduct;\n\nnamespace internal {\n\ntemplate<typename T,int Rows,int Cols,int Flags> struct sparse_eval;\n\ntemplate<typename T> struct eval<T,Sparse>\n  : sparse_eval<T, traits<T>::RowsAtCompileTime,traits<T>::ColsAtCompileTime,traits<T>::Flags>\n{};\n\ntemplate<typename T,int Cols,int Flags> struct sparse_eval<T,1,Cols,Flags> {\n    typedef typename traits<T>::Scalar _Scalar;\n    typedef typename traits<T>::StorageIndex _StorageIndex;\n  public:\n    typedef SparseVector<_Scalar, RowMajor, _StorageIndex> type;\n};\n\ntemplate<typename T,int Rows,int Flags> struct sparse_eval<T,Rows,1,Flags> {\n    typedef typename traits<T>::Scalar _Scalar;\n    typedef typename traits<T>::StorageIndex _StorageIndex;\n  public:\n    typedef SparseVector<_Scalar, ColMajor, _StorageIndex> type;\n};\n\n// TODO this seems almost identical to plain_matrix_type<T, Sparse>\ntemplate<typename T,int Rows,int Cols,int Flags> struct sparse_eval {\n    typedef typename traits<T>::Scalar _Scalar;\n    typedef typename traits<T>::StorageIndex _StorageIndex;\n    enum { _Options = ((Flags&RowMajorBit)==RowMajorBit) ? RowMajor : ColMajor };\n  public:\n    typedef SparseMatrix<_Scalar, _Options, _StorageIndex> type;\n};\n\ntemplate<typename T,int Flags> struct sparse_eval<T,1,1,Flags> {\n    typedef typename traits<T>::Scalar _Scalar;\n  public:\n    typedef Matrix<_Scalar, 1, 1> type;\n};\n\ntemplate<typename T> struct plain_matrix_type<T,Sparse>\n{\n  typedef typename traits<T>::Scalar _Scalar;\n  typedef typename traits<T>::StorageIndex _StorageIndex;\n  enum { _Options = ((evaluator<T>::Flags&RowMajorBit)==RowMajorBit) ? RowMajor : ColMajor };\n  public:\n    typedef SparseMatrix<_Scalar, _Options, _StorageIndex> type;\n};\n\ntemplate<typename T>\nstruct plain_object_eval<T,Sparse>\n  : sparse_eval<T, traits<T>::RowsAtCompileTime,traits<T>::ColsAtCompileTime, evaluator<T>::Flags>\n{};\n\ntemplate<typename Decomposition, typename RhsType>\nstruct solve_traits<Decomposition,RhsType,Sparse>\n{\n  typedef typename sparse_eval<RhsType, RhsType::RowsAtCompileTime, RhsType::ColsAtCompileTime,traits<RhsType>::Flags>::type PlainObject;\n};\n\ntemplate<typename Derived>\nstruct generic_xpr_base<Derived, MatrixXpr, Sparse>\n{\n  typedef SparseMatrixBase<Derived> type;\n};\n\nstruct SparseTriangularShape  { static std::string debugName() { return \"SparseTriangularShape\"; } };\nstruct SparseSelfAdjointShape { static std::string debugName() { return \"SparseSelfAdjointShape\"; } };\n\ntemplate<> struct glue_shapes<SparseShape,SelfAdjointShape> { typedef SparseSelfAdjointShape type;  };\ntemplate<> struct glue_shapes<SparseShape,TriangularShape > { typedef SparseTriangularShape  type;  };\n\n} // end namespace internal\n\n/** \\ingroup SparseCore_Module\n  *\n  * \\class Triplet\n  *\n  * \\brief A small structure to hold a non zero as a triplet (i,j,value).\n  *\n  * \\sa SparseMatrix::setFromTriplets()\n  */\ntemplate<typename Scalar, typename StorageIndex=typename SparseMatrix<Scalar>::StorageIndex >\nclass Triplet\n{\npublic:\n  Triplet() : m_row(0), m_col(0), m_value(0) {}\n\n  Triplet(const StorageIndex& i, const StorageIndex& j, const Scalar& v = Scalar(0))\n    : m_row(i), m_col(j), m_value(v)\n  {}\n\n  /** \\returns the row index of the element */\n  const StorageIndex& row() const { return m_row; }\n\n  /** \\returns the column index of the element */\n  const StorageIndex& col() const { return m_col; }\n\n  /** \\returns the value of the element */\n  const Scalar& value() const { return m_value; }\nprotected:\n  StorageIndex m_row, m_col;\n  Scalar m_value;\n};\n\n} // end namespace Eigen\n\n#endif // EIGEN_SPARSEUTIL_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseCore/SparseVector.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2015 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SPARSEVECTOR_H\n#define EIGEN_SPARSEVECTOR_H\n\nnamespace Eigen { \n\n/** \\ingroup SparseCore_Module\n  * \\class SparseVector\n  *\n  * \\brief a sparse vector class\n  *\n  * \\tparam _Scalar the scalar type, i.e. the type of the coefficients\n  *\n  * See http://www.netlib.org/linalg/html_templates/node91.html for details on the storage scheme.\n  *\n  * This class can be extended with the help of the plugin mechanism described on the page\n  * \\ref TopicCustomizing_Plugins by defining the preprocessor symbol \\c EIGEN_SPARSEVECTOR_PLUGIN.\n  */\n\nnamespace internal {\ntemplate<typename _Scalar, int _Options, typename _StorageIndex>\nstruct traits<SparseVector<_Scalar, _Options, _StorageIndex> >\n{\n  typedef _Scalar Scalar;\n  typedef _StorageIndex StorageIndex;\n  typedef Sparse StorageKind;\n  typedef MatrixXpr XprKind;\n  enum {\n    IsColVector = (_Options & RowMajorBit) ? 0 : 1,\n\n    RowsAtCompileTime = IsColVector ? Dynamic : 1,\n    ColsAtCompileTime = IsColVector ? 1 : Dynamic,\n    MaxRowsAtCompileTime = RowsAtCompileTime,\n    MaxColsAtCompileTime = ColsAtCompileTime,\n    Flags = _Options | NestByRefBit | LvalueBit | (IsColVector ? 0 : RowMajorBit) | CompressedAccessBit,\n    SupportedAccessPatterns = InnerRandomAccessPattern\n  };\n};\n\n// Sparse-Vector-Assignment kinds:\nenum {\n  SVA_RuntimeSwitch,\n  SVA_Inner,\n  SVA_Outer\n};\n\ntemplate< typename Dest, typename Src,\n          int AssignmentKind = !bool(Src::IsVectorAtCompileTime) ? SVA_RuntimeSwitch\n                             : Src::InnerSizeAtCompileTime==1 ? SVA_Outer\n                             : SVA_Inner>\nstruct sparse_vector_assign_selector;\n\n}\n\ntemplate<typename _Scalar, int _Options, typename _StorageIndex>\nclass SparseVector\n  : public SparseCompressedBase<SparseVector<_Scalar, _Options, _StorageIndex> >\n{\n    typedef SparseCompressedBase<SparseVector> Base;\n    using Base::convert_index;\n  public:\n    EIGEN_SPARSE_PUBLIC_INTERFACE(SparseVector)\n    EIGEN_SPARSE_INHERIT_ASSIGNMENT_OPERATOR(SparseVector, +=)\n    EIGEN_SPARSE_INHERIT_ASSIGNMENT_OPERATOR(SparseVector, -=)\n    \n    typedef internal::CompressedStorage<Scalar,StorageIndex> Storage;\n    enum { IsColVector = internal::traits<SparseVector>::IsColVector };\n    \n    enum {\n      Options = _Options\n    };\n    \n    EIGEN_STRONG_INLINE Index rows() const { return IsColVector ? m_size : 1; }\n    EIGEN_STRONG_INLINE Index cols() const { return IsColVector ? 1 : m_size; }\n    EIGEN_STRONG_INLINE Index innerSize() const { return m_size; }\n    EIGEN_STRONG_INLINE Index outerSize() const { return 1; }\n\n    EIGEN_STRONG_INLINE const Scalar* valuePtr() const { return m_data.valuePtr(); }\n    EIGEN_STRONG_INLINE Scalar* valuePtr() { return m_data.valuePtr(); }\n\n    EIGEN_STRONG_INLINE const StorageIndex* innerIndexPtr() const { return m_data.indexPtr(); }\n    EIGEN_STRONG_INLINE StorageIndex* innerIndexPtr() { return m_data.indexPtr(); }\n\n    inline const StorageIndex* outerIndexPtr() const { return 0; }\n    inline StorageIndex* outerIndexPtr() { return 0; }\n    inline const StorageIndex* innerNonZeroPtr() const { return 0; }\n    inline StorageIndex* innerNonZeroPtr() { return 0; }\n    \n    /** \\internal */\n    inline Storage& data() { return m_data; }\n    /** \\internal */\n    inline const Storage& data() const { return m_data; }\n\n    inline Scalar coeff(Index row, Index col) const\n    {\n      eigen_assert(IsColVector ? (col==0 && row>=0 && row<m_size) : (row==0 && col>=0 && col<m_size));\n      return coeff(IsColVector ? row : col);\n    }\n    inline Scalar coeff(Index i) const\n    {\n      eigen_assert(i>=0 && i<m_size);\n      return m_data.at(StorageIndex(i));\n    }\n\n    inline Scalar& coeffRef(Index row, Index col)\n    {\n      eigen_assert(IsColVector ? (col==0 && row>=0 && row<m_size) : (row==0 && col>=0 && col<m_size));\n      return coeffRef(IsColVector ? row : col);\n    }\n\n    /** \\returns a reference to the coefficient value at given index \\a i\n      * This operation involes a log(rho*size) binary search. If the coefficient does not\n      * exist yet, then a sorted insertion into a sequential buffer is performed.\n      *\n      * This insertion might be very costly if the number of nonzeros above \\a i is large.\n      */\n    inline Scalar& coeffRef(Index i)\n    {\n      eigen_assert(i>=0 && i<m_size);\n\n      return m_data.atWithInsertion(StorageIndex(i));\n    }\n\n  public:\n\n    typedef typename Base::InnerIterator InnerIterator;\n    typedef typename Base::ReverseInnerIterator ReverseInnerIterator;\n\n    inline void setZero() { m_data.clear(); }\n\n    /** \\returns the number of non zero coefficients */\n    inline Index nonZeros() const  { return m_data.size(); }\n\n    inline void startVec(Index outer)\n    {\n      EIGEN_UNUSED_VARIABLE(outer);\n      eigen_assert(outer==0);\n    }\n\n    inline Scalar& insertBackByOuterInner(Index outer, Index inner)\n    {\n      EIGEN_UNUSED_VARIABLE(outer);\n      eigen_assert(outer==0);\n      return insertBack(inner);\n    }\n    inline Scalar& insertBack(Index i)\n    {\n      m_data.append(0, i);\n      return m_data.value(m_data.size()-1);\n    }\n    \n    Scalar& insertBackByOuterInnerUnordered(Index outer, Index inner)\n    {\n      EIGEN_UNUSED_VARIABLE(outer);\n      eigen_assert(outer==0);\n      return insertBackUnordered(inner);\n    }\n    inline Scalar& insertBackUnordered(Index i)\n    {\n      m_data.append(0, i);\n      return m_data.value(m_data.size()-1);\n    }\n\n    inline Scalar& insert(Index row, Index col)\n    {\n      eigen_assert(IsColVector ? (col==0 && row>=0 && row<m_size) : (row==0 && col>=0 && col<m_size));\n      \n      Index inner = IsColVector ? row : col;\n      Index outer = IsColVector ? col : row;\n      EIGEN_ONLY_USED_FOR_DEBUG(outer);\n      eigen_assert(outer==0);\n      return insert(inner);\n    }\n    Scalar& insert(Index i)\n    {\n      eigen_assert(i>=0 && i<m_size);\n      \n      Index startId = 0;\n      Index p = Index(m_data.size()) - 1;\n      // TODO smart realloc\n      m_data.resize(p+2,1);\n\n      while ( (p >= startId) && (m_data.index(p) > i) )\n      {\n        m_data.index(p+1) = m_data.index(p);\n        m_data.value(p+1) = m_data.value(p);\n        --p;\n      }\n      m_data.index(p+1) = convert_index(i);\n      m_data.value(p+1) = 0;\n      return m_data.value(p+1);\n    }\n\n    /**\n      */\n    inline void reserve(Index reserveSize) { m_data.reserve(reserveSize); }\n\n\n    inline void finalize() {}\n\n    /** \\copydoc SparseMatrix::prune(const Scalar&,const RealScalar&) */\n    void prune(const Scalar& reference, const RealScalar& epsilon = NumTraits<RealScalar>::dummy_precision())\n    {\n      m_data.prune(reference,epsilon);\n    }\n\n    /** Resizes the sparse vector to \\a rows x \\a cols\n      *\n      * This method is provided for compatibility with matrices.\n      * For a column vector, \\a cols must be equal to 1.\n      * For a row vector, \\a rows must be equal to 1.\n      *\n      * \\sa resize(Index)\n      */\n    void resize(Index rows, Index cols)\n    {\n      eigen_assert((IsColVector ? cols : rows)==1 && \"Outer dimension must equal 1\");\n      resize(IsColVector ? rows : cols);\n    }\n\n    /** Resizes the sparse vector to \\a newSize\n      * This method deletes all entries, thus leaving an empty sparse vector\n      *\n      * \\sa  conservativeResize(), setZero() */\n    void resize(Index newSize)\n    {\n      m_size = newSize;\n      m_data.clear();\n    }\n\n    /** Resizes the sparse vector to \\a newSize, while leaving old values untouched.\n      *\n      * If the size of the vector is decreased, then the storage of the out-of bounds coefficients is kept and reserved.\n      * Call .data().squeeze() to free extra memory.\n      *\n      * \\sa reserve(), setZero()\n      */\n    void conservativeResize(Index newSize)\n    {\n      if (newSize < m_size)\n      {\n        Index i = 0;\n        while (i<m_data.size() && m_data.index(i)<newSize) ++i;\n        m_data.resize(i);\n      }\n      m_size = newSize;\n    }\n\n    void resizeNonZeros(Index size) { m_data.resize(size); }\n\n    inline SparseVector() : m_size(0) { check_template_parameters(); resize(0); }\n\n    explicit inline SparseVector(Index size) : m_size(0) { check_template_parameters(); resize(size); }\n\n    inline SparseVector(Index rows, Index cols) : m_size(0) { check_template_parameters(); resize(rows,cols); }\n\n    template<typename OtherDerived>\n    inline SparseVector(const SparseMatrixBase<OtherDerived>& other)\n      : m_size(0)\n    {\n      #ifdef EIGEN_SPARSE_CREATE_TEMPORARY_PLUGIN\n        EIGEN_SPARSE_CREATE_TEMPORARY_PLUGIN\n      #endif\n      check_template_parameters();\n      *this = other.derived();\n    }\n\n    inline SparseVector(const SparseVector& other)\n      : Base(other), m_size(0)\n    {\n      check_template_parameters();\n      *this = other.derived();\n    }\n\n    /** Swaps the values of \\c *this and \\a other.\n      * Overloaded for performance: this version performs a \\em shallow swap by swaping pointers and attributes only.\n      * \\sa SparseMatrixBase::swap()\n      */\n    inline void swap(SparseVector& other)\n    {\n      std::swap(m_size, other.m_size);\n      m_data.swap(other.m_data);\n    }\n\n    template<int OtherOptions>\n    inline void swap(SparseMatrix<Scalar,OtherOptions,StorageIndex>& other)\n    {\n      eigen_assert(other.outerSize()==1);\n      std::swap(m_size, other.m_innerSize);\n      m_data.swap(other.m_data);\n    }\n\n    inline SparseVector& operator=(const SparseVector& other)\n    {\n      if (other.isRValue())\n      {\n        swap(other.const_cast_derived());\n      }\n      else\n      {\n        resize(other.size());\n        m_data = other.m_data;\n      }\n      return *this;\n    }\n\n    template<typename OtherDerived>\n    inline SparseVector& operator=(const SparseMatrixBase<OtherDerived>& other)\n    {\n      SparseVector tmp(other.size());\n      internal::sparse_vector_assign_selector<SparseVector,OtherDerived>::run(tmp,other.derived());\n      this->swap(tmp);\n      return *this;\n    }\n\n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    template<typename Lhs, typename Rhs>\n    inline SparseVector& operator=(const SparseSparseProduct<Lhs,Rhs>& product)\n    {\n      return Base::operator=(product);\n    }\n    #endif\n\n    friend std::ostream & operator << (std::ostream & s, const SparseVector& m)\n    {\n      for (Index i=0; i<m.nonZeros(); ++i)\n        s << \"(\" << m.m_data.value(i) << \",\" << m.m_data.index(i) << \") \";\n      s << std::endl;\n      return s;\n    }\n\n    /** Destructor */\n    inline ~SparseVector() {}\n\n    /** Overloaded for performance */\n    Scalar sum() const;\n\n  public:\n\n    /** \\internal \\deprecated use setZero() and reserve() */\n    EIGEN_DEPRECATED void startFill(Index reserve)\n    {\n      setZero();\n      m_data.reserve(reserve);\n    }\n\n    /** \\internal \\deprecated use insertBack(Index,Index) */\n    EIGEN_DEPRECATED Scalar& fill(Index r, Index c)\n    {\n      eigen_assert(r==0 || c==0);\n      return fill(IsColVector ? r : c);\n    }\n\n    /** \\internal \\deprecated use insertBack(Index) */\n    EIGEN_DEPRECATED Scalar& fill(Index i)\n    {\n      m_data.append(0, i);\n      return m_data.value(m_data.size()-1);\n    }\n\n    /** \\internal \\deprecated use insert(Index,Index) */\n    EIGEN_DEPRECATED Scalar& fillrand(Index r, Index c)\n    {\n      eigen_assert(r==0 || c==0);\n      return fillrand(IsColVector ? r : c);\n    }\n\n    /** \\internal \\deprecated use insert(Index) */\n    EIGEN_DEPRECATED Scalar& fillrand(Index i)\n    {\n      return insert(i);\n    }\n\n    /** \\internal \\deprecated use finalize() */\n    EIGEN_DEPRECATED void endFill() {}\n    \n    // These two functions were here in the 3.1 release, so let's keep them in case some code rely on them.\n    /** \\internal \\deprecated use data() */\n    EIGEN_DEPRECATED Storage& _data() { return m_data; }\n    /** \\internal \\deprecated use data() */\n    EIGEN_DEPRECATED const Storage& _data() const { return m_data; }\n    \n#   ifdef EIGEN_SPARSEVECTOR_PLUGIN\n#     include EIGEN_SPARSEVECTOR_PLUGIN\n#   endif\n\nprotected:\n  \n    static void check_template_parameters()\n    {\n      EIGEN_STATIC_ASSERT(NumTraits<StorageIndex>::IsSigned,THE_INDEX_TYPE_MUST_BE_A_SIGNED_TYPE);\n      EIGEN_STATIC_ASSERT((_Options&(ColMajor|RowMajor))==Options,INVALID_MATRIX_TEMPLATE_PARAMETERS);\n    }\n    \n    Storage m_data;\n    Index m_size;\n};\n\nnamespace internal {\n\ntemplate<typename _Scalar, int _Options, typename _Index>\nstruct evaluator<SparseVector<_Scalar,_Options,_Index> >\n  : evaluator_base<SparseVector<_Scalar,_Options,_Index> >\n{\n  typedef SparseVector<_Scalar,_Options,_Index> SparseVectorType;\n  typedef evaluator_base<SparseVectorType> Base;\n  typedef typename SparseVectorType::InnerIterator InnerIterator;\n  typedef typename SparseVectorType::ReverseInnerIterator ReverseInnerIterator;\n  \n  enum {\n    CoeffReadCost = NumTraits<_Scalar>::ReadCost,\n    Flags = SparseVectorType::Flags\n  };\n\n  evaluator() : Base() {}\n  \n  explicit evaluator(const SparseVectorType &mat) : m_matrix(&mat)\n  {\n    EIGEN_INTERNAL_CHECK_COST_VALUE(CoeffReadCost);\n  }\n  \n  inline Index nonZerosEstimate() const {\n    return m_matrix->nonZeros();\n  }\n  \n  operator SparseVectorType&() { return m_matrix->const_cast_derived(); }\n  operator const SparseVectorType&() const { return *m_matrix; }\n  \n  const SparseVectorType *m_matrix;\n};\n\ntemplate< typename Dest, typename Src>\nstruct sparse_vector_assign_selector<Dest,Src,SVA_Inner> {\n  static void run(Dest& dst, const Src& src) {\n    eigen_internal_assert(src.innerSize()==src.size());\n    typedef internal::evaluator<Src> SrcEvaluatorType;\n    SrcEvaluatorType srcEval(src);\n    for(typename SrcEvaluatorType::InnerIterator it(srcEval, 0); it; ++it)\n      dst.insert(it.index()) = it.value();\n  }\n};\n\ntemplate< typename Dest, typename Src>\nstruct sparse_vector_assign_selector<Dest,Src,SVA_Outer> {\n  static void run(Dest& dst, const Src& src) {\n    eigen_internal_assert(src.outerSize()==src.size());\n    typedef internal::evaluator<Src> SrcEvaluatorType;\n    SrcEvaluatorType srcEval(src);\n    for(Index i=0; i<src.size(); ++i)\n    {\n      typename SrcEvaluatorType::InnerIterator it(srcEval, i);\n      if(it)\n        dst.insert(i) = it.value();\n    }\n  }\n};\n\ntemplate< typename Dest, typename Src>\nstruct sparse_vector_assign_selector<Dest,Src,SVA_RuntimeSwitch> {\n  static void run(Dest& dst, const Src& src) {\n    if(src.outerSize()==1)  sparse_vector_assign_selector<Dest,Src,SVA_Inner>::run(dst, src);\n    else                    sparse_vector_assign_selector<Dest,Src,SVA_Outer>::run(dst, src);\n  }\n};\n\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_SPARSEVECTOR_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseCore/SparseView.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2011-2014 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2010 Daniel Lowengrub <lowdanie@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SPARSEVIEW_H\n#define EIGEN_SPARSEVIEW_H\n\nnamespace Eigen { \n\nnamespace internal {\n\ntemplate<typename MatrixType>\nstruct traits<SparseView<MatrixType> > : traits<MatrixType>\n{\n  typedef typename MatrixType::StorageIndex StorageIndex;\n  typedef Sparse StorageKind;\n  enum {\n    Flags = int(traits<MatrixType>::Flags) & (RowMajorBit)\n  };\n};\n\n} // end namespace internal\n\ntemplate<typename MatrixType>\nclass SparseView : public SparseMatrixBase<SparseView<MatrixType> >\n{\n  typedef typename MatrixType::Nested MatrixTypeNested;\n  typedef typename internal::remove_all<MatrixTypeNested>::type _MatrixTypeNested;\n  typedef SparseMatrixBase<SparseView > Base;\npublic:\n  EIGEN_SPARSE_PUBLIC_INTERFACE(SparseView)\n  typedef typename internal::remove_all<MatrixType>::type NestedExpression;\n\n  explicit SparseView(const MatrixType& mat, const Scalar& reference = Scalar(0),\n                      const RealScalar &epsilon = NumTraits<Scalar>::dummy_precision())\n    : m_matrix(mat), m_reference(reference), m_epsilon(epsilon) {}\n\n  inline Index rows() const { return m_matrix.rows(); }\n  inline Index cols() const { return m_matrix.cols(); }\n\n  inline Index innerSize() const { return m_matrix.innerSize(); }\n  inline Index outerSize() const { return m_matrix.outerSize(); }\n  \n  /** \\returns the nested expression */\n  const typename internal::remove_all<MatrixTypeNested>::type&\n  nestedExpression() const { return m_matrix; }\n  \n  Scalar reference() const { return m_reference; }\n  RealScalar epsilon() const { return m_epsilon; }\n  \nprotected:\n  MatrixTypeNested m_matrix;\n  Scalar m_reference;\n  RealScalar m_epsilon;\n};\n\nnamespace internal {\n\n// TODO find a way to unify the two following variants\n// This is tricky because implementing an inner iterator on top of an IndexBased evaluator is\n// not easy because the evaluators do not expose the sizes of the underlying expression.\n  \ntemplate<typename ArgType>\nstruct unary_evaluator<SparseView<ArgType>, IteratorBased>\n  : public evaluator_base<SparseView<ArgType> >\n{\n    typedef typename evaluator<ArgType>::InnerIterator EvalIterator;\n  public:\n    typedef SparseView<ArgType> XprType;\n    \n    class InnerIterator : public EvalIterator\n    {\n        typedef typename XprType::Scalar Scalar;\n      public:\n\n        EIGEN_STRONG_INLINE InnerIterator(const unary_evaluator& sve, Index outer)\n          : EvalIterator(sve.m_argImpl,outer), m_view(sve.m_view)\n        {\n          incrementToNonZero();\n        }\n\n        EIGEN_STRONG_INLINE InnerIterator& operator++()\n        {\n          EvalIterator::operator++();\n          incrementToNonZero();\n          return *this;\n        }\n\n        using EvalIterator::value;\n\n      protected:\n        const XprType &m_view;\n\n      private:\n        void incrementToNonZero()\n        {\n          while((bool(*this)) && internal::isMuchSmallerThan(value(), m_view.reference(), m_view.epsilon()))\n          {\n            EvalIterator::operator++();\n          }\n        }\n    };\n    \n    enum {\n      CoeffReadCost = evaluator<ArgType>::CoeffReadCost,\n      Flags = XprType::Flags\n    };\n    \n    explicit unary_evaluator(const XprType& xpr) : m_argImpl(xpr.nestedExpression()), m_view(xpr) {}\n\n  protected:\n    evaluator<ArgType> m_argImpl;\n    const XprType &m_view;\n};\n\ntemplate<typename ArgType>\nstruct unary_evaluator<SparseView<ArgType>, IndexBased>\n  : public evaluator_base<SparseView<ArgType> >\n{\n  public:\n    typedef SparseView<ArgType> XprType;\n  protected:\n    enum { IsRowMajor = (XprType::Flags&RowMajorBit)==RowMajorBit };\n    typedef typename XprType::Scalar Scalar;\n    typedef typename XprType::StorageIndex StorageIndex;\n  public:\n    \n    class InnerIterator\n    {\n      public:\n\n        EIGEN_STRONG_INLINE InnerIterator(const unary_evaluator& sve, Index outer)\n          : m_sve(sve), m_inner(0), m_outer(outer), m_end(sve.m_view.innerSize())\n        {\n          incrementToNonZero();\n        }\n\n        EIGEN_STRONG_INLINE InnerIterator& operator++()\n        {\n          m_inner++;\n          incrementToNonZero();\n          return *this;\n        }\n\n        EIGEN_STRONG_INLINE Scalar value() const\n        {\n          return (IsRowMajor) ? m_sve.m_argImpl.coeff(m_outer, m_inner)\n                              : m_sve.m_argImpl.coeff(m_inner, m_outer);\n        }\n\n        EIGEN_STRONG_INLINE StorageIndex index() const { return m_inner; }\n        inline Index row() const { return IsRowMajor ? m_outer : index(); }\n        inline Index col() const { return IsRowMajor ? index() : m_outer; }\n\n        EIGEN_STRONG_INLINE operator bool() const { return m_inner < m_end && m_inner>=0; }\n\n      protected:\n        const unary_evaluator &m_sve;\n        Index m_inner;\n        const Index m_outer;\n        const Index m_end;\n\n      private:\n        void incrementToNonZero()\n        {\n          while((bool(*this)) && internal::isMuchSmallerThan(value(), m_sve.m_view.reference(), m_sve.m_view.epsilon()))\n          {\n            m_inner++;\n          }\n        }\n    };\n    \n    enum {\n      CoeffReadCost = evaluator<ArgType>::CoeffReadCost,\n      Flags = XprType::Flags\n    };\n    \n    explicit unary_evaluator(const XprType& xpr) : m_argImpl(xpr.nestedExpression()), m_view(xpr) {}\n\n  protected:\n    evaluator<ArgType> m_argImpl;\n    const XprType &m_view;\n};\n\n} // end namespace internal\n\ntemplate<typename Derived>\nconst SparseView<Derived> MatrixBase<Derived>::sparseView(const Scalar& reference,\n                                                          const typename NumTraits<Scalar>::Real& epsilon) const\n{\n  return SparseView<Derived>(derived(), reference, epsilon);\n}\n\n/** \\returns an expression of \\c *this with values smaller than\n  * \\a reference * \\a epsilon are removed.\n  *\n  * This method is typically used in conjunction with the product of two sparse matrices\n  * to automatically prune the smallest values as follows:\n  * \\code\n  * C = (A*B).pruned();             // suppress numerical zeros (exact)\n  * C = (A*B).pruned(ref);\n  * C = (A*B).pruned(ref,epsilon);\n  * \\endcode\n  * where \\c ref is a meaningful non zero reference value.\n  * */\ntemplate<typename Derived>\nconst SparseView<Derived>\nSparseMatrixBase<Derived>::pruned(const Scalar& reference,\n                                  const RealScalar& epsilon) const\n{\n  return SparseView<Derived>(derived(), reference, epsilon);\n}\n\n} // end namespace Eigen\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseCore/TriangularSolver.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SPARSETRIANGULARSOLVER_H\n#define EIGEN_SPARSETRIANGULARSOLVER_H\n\nnamespace Eigen { \n\nnamespace internal {\n\ntemplate<typename Lhs, typename Rhs, int Mode,\n  int UpLo = (Mode & Lower)\n           ? Lower\n           : (Mode & Upper)\n           ? Upper\n           : -1,\n  int StorageOrder = int(traits<Lhs>::Flags) & RowMajorBit>\nstruct sparse_solve_triangular_selector;\n\n// forward substitution, row-major\ntemplate<typename Lhs, typename Rhs, int Mode>\nstruct sparse_solve_triangular_selector<Lhs,Rhs,Mode,Lower,RowMajor>\n{\n  typedef typename Rhs::Scalar Scalar;\n  typedef evaluator<Lhs> LhsEval;\n  typedef typename evaluator<Lhs>::InnerIterator LhsIterator;\n  static void run(const Lhs& lhs, Rhs& other)\n  {\n    LhsEval lhsEval(lhs);\n    for(Index col=0 ; col<other.cols() ; ++col)\n    {\n      for(Index i=0; i<lhs.rows(); ++i)\n      {\n        Scalar tmp = other.coeff(i,col);\n        Scalar lastVal(0);\n        Index lastIndex = 0;\n        for(LhsIterator it(lhsEval, i); it; ++it)\n        {\n          lastVal = it.value();\n          lastIndex = it.index();\n          if(lastIndex==i)\n            break;\n          tmp -= lastVal * other.coeff(lastIndex,col);\n        }\n        if (Mode & UnitDiag)\n          other.coeffRef(i,col) = tmp;\n        else\n        {\n          eigen_assert(lastIndex==i);\n          other.coeffRef(i,col) = tmp/lastVal;\n        }\n      }\n    }\n  }\n};\n\n// backward substitution, row-major\ntemplate<typename Lhs, typename Rhs, int Mode>\nstruct sparse_solve_triangular_selector<Lhs,Rhs,Mode,Upper,RowMajor>\n{\n  typedef typename Rhs::Scalar Scalar;\n  typedef evaluator<Lhs> LhsEval;\n  typedef typename evaluator<Lhs>::InnerIterator LhsIterator;\n  static void run(const Lhs& lhs, Rhs& other)\n  {\n    LhsEval lhsEval(lhs);\n    for(Index col=0 ; col<other.cols() ; ++col)\n    {\n      for(Index i=lhs.rows()-1 ; i>=0 ; --i)\n      {\n        Scalar tmp = other.coeff(i,col);\n        Scalar l_ii(0);\n        LhsIterator it(lhsEval, i);\n        while(it && it.index()<i)\n          ++it;\n        if(!(Mode & UnitDiag))\n        {\n          eigen_assert(it && it.index()==i);\n          l_ii = it.value();\n          ++it;\n        }\n        else if (it && it.index() == i)\n          ++it;\n        for(; it; ++it)\n        {\n          tmp -= it.value() * other.coeff(it.index(),col);\n        }\n\n        if (Mode & UnitDiag)  other.coeffRef(i,col) = tmp;\n        else                  other.coeffRef(i,col) = tmp/l_ii;\n      }\n    }\n  }\n};\n\n// forward substitution, col-major\ntemplate<typename Lhs, typename Rhs, int Mode>\nstruct sparse_solve_triangular_selector<Lhs,Rhs,Mode,Lower,ColMajor>\n{\n  typedef typename Rhs::Scalar Scalar;\n  typedef evaluator<Lhs> LhsEval;\n  typedef typename evaluator<Lhs>::InnerIterator LhsIterator;\n  static void run(const Lhs& lhs, Rhs& other)\n  {\n    LhsEval lhsEval(lhs);\n    for(Index col=0 ; col<other.cols() ; ++col)\n    {\n      for(Index i=0; i<lhs.cols(); ++i)\n      {\n        Scalar& tmp = other.coeffRef(i,col);\n        if (tmp!=Scalar(0)) // optimization when other is actually sparse\n        {\n          LhsIterator it(lhsEval, i);\n          while(it && it.index()<i)\n            ++it;\n          if(!(Mode & UnitDiag))\n          {\n            eigen_assert(it && it.index()==i);\n            tmp /= it.value();\n          }\n          if (it && it.index()==i)\n            ++it;\n          for(; it; ++it)\n            other.coeffRef(it.index(), col) -= tmp * it.value();\n        }\n      }\n    }\n  }\n};\n\n// backward substitution, col-major\ntemplate<typename Lhs, typename Rhs, int Mode>\nstruct sparse_solve_triangular_selector<Lhs,Rhs,Mode,Upper,ColMajor>\n{\n  typedef typename Rhs::Scalar Scalar;\n  typedef evaluator<Lhs> LhsEval;\n  typedef typename evaluator<Lhs>::InnerIterator LhsIterator;\n  static void run(const Lhs& lhs, Rhs& other)\n  {\n    LhsEval lhsEval(lhs);\n    for(Index col=0 ; col<other.cols() ; ++col)\n    {\n      for(Index i=lhs.cols()-1; i>=0; --i)\n      {\n        Scalar& tmp = other.coeffRef(i,col);\n        if (tmp!=Scalar(0)) // optimization when other is actually sparse\n        {\n          if(!(Mode & UnitDiag))\n          {\n            // TODO replace this by a binary search. make sure the binary search is safe for partially sorted elements\n            LhsIterator it(lhsEval, i);\n            while(it && it.index()!=i)\n              ++it;\n            eigen_assert(it && it.index()==i);\n            other.coeffRef(i,col) /= it.value();\n          }\n          LhsIterator it(lhsEval, i);\n          for(; it && it.index()<i; ++it)\n            other.coeffRef(it.index(), col) -= tmp * it.value();\n        }\n      }\n    }\n  }\n};\n\n} // end namespace internal\n\ntemplate<typename ExpressionType,unsigned int Mode>\ntemplate<typename OtherDerived>\nvoid TriangularViewImpl<ExpressionType,Mode,Sparse>::solveInPlace(MatrixBase<OtherDerived>& other) const\n{\n  eigen_assert(derived().cols() == derived().rows() && derived().cols() == other.rows());\n  eigen_assert((!(Mode & ZeroDiag)) && bool(Mode & (Upper|Lower)));\n\n  enum { copy = internal::traits<OtherDerived>::Flags & RowMajorBit };\n\n  typedef typename internal::conditional<copy,\n    typename internal::plain_matrix_type_column_major<OtherDerived>::type, OtherDerived&>::type OtherCopy;\n  OtherCopy otherCopy(other.derived());\n\n  internal::sparse_solve_triangular_selector<ExpressionType, typename internal::remove_reference<OtherCopy>::type, Mode>::run(derived().nestedExpression(), otherCopy);\n\n  if (copy)\n    other = otherCopy;\n}\n\n// pure sparse path\n\nnamespace internal {\n\ntemplate<typename Lhs, typename Rhs, int Mode,\n  int UpLo = (Mode & Lower)\n           ? Lower\n           : (Mode & Upper)\n           ? Upper\n           : -1,\n  int StorageOrder = int(Lhs::Flags) & (RowMajorBit)>\nstruct sparse_solve_triangular_sparse_selector;\n\n// forward substitution, col-major\ntemplate<typename Lhs, typename Rhs, int Mode, int UpLo>\nstruct sparse_solve_triangular_sparse_selector<Lhs,Rhs,Mode,UpLo,ColMajor>\n{\n  typedef typename Rhs::Scalar Scalar;\n  typedef typename promote_index_type<typename traits<Lhs>::StorageIndex,\n                                      typename traits<Rhs>::StorageIndex>::type StorageIndex;\n  static void run(const Lhs& lhs, Rhs& other)\n  {\n    const bool IsLower = (UpLo==Lower);\n    AmbiVector<Scalar,StorageIndex> tempVector(other.rows()*2);\n    tempVector.setBounds(0,other.rows());\n\n    Rhs res(other.rows(), other.cols());\n    res.reserve(other.nonZeros());\n\n    for(Index col=0 ; col<other.cols() ; ++col)\n    {\n      // FIXME estimate number of non zeros\n      tempVector.init(.99/*float(other.col(col).nonZeros())/float(other.rows())*/);\n      tempVector.setZero();\n      tempVector.restart();\n      for (typename Rhs::InnerIterator rhsIt(other, col); rhsIt; ++rhsIt)\n      {\n        tempVector.coeffRef(rhsIt.index()) = rhsIt.value();\n      }\n\n      for(Index i=IsLower?0:lhs.cols()-1;\n          IsLower?i<lhs.cols():i>=0;\n          i+=IsLower?1:-1)\n      {\n        tempVector.restart();\n        Scalar& ci = tempVector.coeffRef(i);\n        if (ci!=Scalar(0))\n        {\n          // find\n          typename Lhs::InnerIterator it(lhs, i);\n          if(!(Mode & UnitDiag))\n          {\n            if (IsLower)\n            {\n              eigen_assert(it.index()==i);\n              ci /= it.value();\n            }\n            else\n              ci /= lhs.coeff(i,i);\n          }\n          tempVector.restart();\n          if (IsLower)\n          {\n            if (it.index()==i)\n              ++it;\n            for(; it; ++it)\n              tempVector.coeffRef(it.index()) -= ci * it.value();\n          }\n          else\n          {\n            for(; it && it.index()<i; ++it)\n              tempVector.coeffRef(it.index()) -= ci * it.value();\n          }\n        }\n      }\n\n\n      Index count = 0;\n      // FIXME compute a reference value to filter zeros\n      for (typename AmbiVector<Scalar,StorageIndex>::Iterator it(tempVector/*,1e-12*/); it; ++it)\n      {\n        ++ count;\n//         std::cerr << \"fill \" << it.index() << \", \" << col << \"\\n\";\n//         std::cout << it.value() << \"  \";\n        // FIXME use insertBack\n        res.insert(it.index(), col) = it.value();\n      }\n//       std::cout << \"tempVector.nonZeros() == \" << int(count) << \" / \" << (other.rows()) << \"\\n\";\n    }\n    res.finalize();\n    other = res.markAsRValue();\n  }\n};\n\n} // end namespace internal\n\ntemplate<typename ExpressionType,unsigned int Mode>\ntemplate<typename OtherDerived>\nvoid TriangularViewImpl<ExpressionType,Mode,Sparse>::solveInPlace(SparseMatrixBase<OtherDerived>& other) const\n{\n  eigen_assert(derived().cols() == derived().rows() && derived().cols() == other.rows());\n  eigen_assert( (!(Mode & ZeroDiag)) && bool(Mode & (Upper|Lower)));\n\n//   enum { copy = internal::traits<OtherDerived>::Flags & RowMajorBit };\n\n//   typedef typename internal::conditional<copy,\n//     typename internal::plain_matrix_type_column_major<OtherDerived>::type, OtherDerived&>::type OtherCopy;\n//   OtherCopy otherCopy(other.derived());\n\n  internal::sparse_solve_triangular_sparse_selector<ExpressionType, OtherDerived, Mode>::run(derived().nestedExpression(), other.derived());\n\n//   if (copy)\n//     other = otherCopy;\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_SPARSETRIANGULARSOLVER_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseLU/SparseLU.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2012 Désiré Nuentsa-Wakam <desire.nuentsa_wakam@inria.fr>\n// Copyright (C) 2012-2014 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n\n#ifndef EIGEN_SPARSE_LU_H\n#define EIGEN_SPARSE_LU_H\n\nnamespace Eigen {\n\ntemplate <typename _MatrixType, typename _OrderingType = COLAMDOrdering<typename _MatrixType::StorageIndex> > class SparseLU;\ntemplate <typename MappedSparseMatrixType> struct SparseLUMatrixLReturnType;\ntemplate <typename MatrixLType, typename MatrixUType> struct SparseLUMatrixUReturnType;\n\n/** \\ingroup SparseLU_Module\n  * \\class SparseLU\n  * \n  * \\brief Sparse supernodal LU factorization for general matrices\n  * \n  * This class implements the supernodal LU factorization for general matrices.\n  * It uses the main techniques from the sequential SuperLU package \n  * (http://crd-legacy.lbl.gov/~xiaoye/SuperLU/). It handles transparently real \n  * and complex arithmetics with single and double precision, depending on the \n  * scalar type of your input matrix. \n  * The code has been optimized to provide BLAS-3 operations during supernode-panel updates. \n  * It benefits directly from the built-in high-performant Eigen BLAS routines. \n  * Moreover, when the size of a supernode is very small, the BLAS calls are avoided to \n  * enable a better optimization from the compiler. For best performance, \n  * you should compile it with NDEBUG flag to avoid the numerous bounds checking on vectors. \n  * \n  * An important parameter of this class is the ordering method. It is used to reorder the columns \n  * (and eventually the rows) of the matrix to reduce the number of new elements that are created during \n  * numerical factorization. The cheapest method available is COLAMD. \n  * See  \\link OrderingMethods_Module the OrderingMethods module \\endlink for the list of \n  * built-in and external ordering methods. \n  *\n  * Simple example with key steps \n  * \\code\n  * VectorXd x(n), b(n);\n  * SparseMatrix<double, ColMajor> A;\n  * SparseLU<SparseMatrix<scalar, ColMajor>, COLAMDOrdering<Index> >   solver;\n  * // fill A and b;\n  * // Compute the ordering permutation vector from the structural pattern of A\n  * solver.analyzePattern(A); \n  * // Compute the numerical factorization \n  * solver.factorize(A); \n  * //Use the factors to solve the linear system \n  * x = solver.solve(b); \n  * \\endcode\n  * \n  * \\warning The input matrix A should be in a \\b compressed and \\b column-major form.\n  * Otherwise an expensive copy will be made. You can call the inexpensive makeCompressed() to get a compressed matrix.\n  * \n  * \\note Unlike the initial SuperLU implementation, there is no step to equilibrate the matrix. \n  * For badly scaled matrices, this step can be useful to reduce the pivoting during factorization. \n  * If this is the case for your matrices, you can try the basic scaling method at\n  *  \"unsupported/Eigen/src/IterativeSolvers/Scaling.h\"\n  * \n  * \\tparam _MatrixType The type of the sparse matrix. It must be a column-major SparseMatrix<>\n  * \\tparam _OrderingType The ordering method to use, either AMD, COLAMD or METIS. Default is COLMAD\n  *\n  * \\implsparsesolverconcept\n  * \n  * \\sa \\ref TutorialSparseSolverConcept\n  * \\sa \\ref OrderingMethods_Module\n  */\ntemplate <typename _MatrixType, typename _OrderingType>\nclass SparseLU : public SparseSolverBase<SparseLU<_MatrixType,_OrderingType> >, public internal::SparseLUImpl<typename _MatrixType::Scalar, typename _MatrixType::StorageIndex>\n{\n  protected:\n    typedef SparseSolverBase<SparseLU<_MatrixType,_OrderingType> > APIBase;\n    using APIBase::m_isInitialized;\n  public:\n    using APIBase::_solve_impl;\n    \n    typedef _MatrixType MatrixType; \n    typedef _OrderingType OrderingType;\n    typedef typename MatrixType::Scalar Scalar; \n    typedef typename MatrixType::RealScalar RealScalar; \n    typedef typename MatrixType::StorageIndex StorageIndex;\n    typedef SparseMatrix<Scalar,ColMajor,StorageIndex> NCMatrix;\n    typedef internal::MappedSuperNodalMatrix<Scalar, StorageIndex> SCMatrix;\n    typedef Matrix<Scalar,Dynamic,1> ScalarVector;\n    typedef Matrix<StorageIndex,Dynamic,1> IndexVector;\n    typedef PermutationMatrix<Dynamic, Dynamic, StorageIndex> PermutationType;\n    typedef internal::SparseLUImpl<Scalar, StorageIndex> Base;\n\n    enum {\n      ColsAtCompileTime = MatrixType::ColsAtCompileTime,\n      MaxColsAtCompileTime = MatrixType::MaxColsAtCompileTime\n    };\n    \n  public:\n    SparseLU():m_lastError(\"\"),m_Ustore(0,0,0,0,0,0),m_symmetricmode(false),m_diagpivotthresh(1.0),m_detPermR(1)\n    {\n      initperfvalues(); \n    }\n    explicit SparseLU(const MatrixType& matrix)\n      : m_lastError(\"\"),m_Ustore(0,0,0,0,0,0),m_symmetricmode(false),m_diagpivotthresh(1.0),m_detPermR(1)\n    {\n      initperfvalues(); \n      compute(matrix);\n    }\n    \n    ~SparseLU()\n    {\n      // Free all explicit dynamic pointers \n    }\n    \n    void analyzePattern (const MatrixType& matrix);\n    void factorize (const MatrixType& matrix);\n    void simplicialfactorize(const MatrixType& matrix);\n    \n    /**\n      * Compute the symbolic and numeric factorization of the input sparse matrix.\n      * The input matrix should be in column-major storage. \n      */\n    void compute (const MatrixType& matrix)\n    {\n      // Analyze \n      analyzePattern(matrix); \n      //Factorize\n      factorize(matrix);\n    } \n    \n    inline Index rows() const { return m_mat.rows(); }\n    inline Index cols() const { return m_mat.cols(); }\n    /** Indicate that the pattern of the input matrix is symmetric */\n    void isSymmetric(bool sym)\n    {\n      m_symmetricmode = sym;\n    }\n    \n    /** \\returns an expression of the matrix L, internally stored as supernodes\n      * The only operation available with this expression is the triangular solve\n      * \\code\n      * y = b; matrixL().solveInPlace(y);\n      * \\endcode\n      */\n    SparseLUMatrixLReturnType<SCMatrix> matrixL() const\n    {\n      return SparseLUMatrixLReturnType<SCMatrix>(m_Lstore);\n    }\n    /** \\returns an expression of the matrix U,\n      * The only operation available with this expression is the triangular solve\n      * \\code\n      * y = b; matrixU().solveInPlace(y);\n      * \\endcode\n      */\n    SparseLUMatrixUReturnType<SCMatrix,MappedSparseMatrix<Scalar,ColMajor,StorageIndex> > matrixU() const\n    {\n      return SparseLUMatrixUReturnType<SCMatrix, MappedSparseMatrix<Scalar,ColMajor,StorageIndex> >(m_Lstore, m_Ustore);\n    }\n\n    /**\n      * \\returns a reference to the row matrix permutation \\f$ P_r \\f$ such that \\f$P_r A P_c^T = L U\\f$\n      * \\sa colsPermutation()\n      */\n    inline const PermutationType& rowsPermutation() const\n    {\n      return m_perm_r;\n    }\n    /**\n      * \\returns a reference to the column matrix permutation\\f$ P_c^T \\f$ such that \\f$P_r A P_c^T = L U\\f$\n      * \\sa rowsPermutation()\n      */\n    inline const PermutationType& colsPermutation() const\n    {\n      return m_perm_c;\n    }\n    /** Set the threshold used for a diagonal entry to be an acceptable pivot. */\n    void setPivotThreshold(const RealScalar& thresh)\n    {\n      m_diagpivotthresh = thresh; \n    }\n\n#ifdef EIGEN_PARSED_BY_DOXYGEN\n    /** \\returns the solution X of \\f$ A X = B \\f$ using the current decomposition of A.\n      *\n      * \\warning the destination matrix X in X = this->solve(B) must be colmun-major.\n      *\n      * \\sa compute()\n      */\n    template<typename Rhs>\n    inline const Solve<SparseLU, Rhs> solve(const MatrixBase<Rhs>& B) const;\n#endif // EIGEN_PARSED_BY_DOXYGEN\n    \n    /** \\brief Reports whether previous computation was successful.\n      *\n      * \\returns \\c Success if computation was succesful,\n      *          \\c NumericalIssue if the LU factorization reports a problem, zero diagonal for instance\n      *          \\c InvalidInput if the input matrix is invalid\n      *\n      * \\sa iparm()          \n      */\n    ComputationInfo info() const\n    {\n      eigen_assert(m_isInitialized && \"Decomposition is not initialized.\");\n      return m_info;\n    }\n    \n    /**\n      * \\returns A string describing the type of error\n      */\n    std::string lastErrorMessage() const\n    {\n      return m_lastError; \n    }\n\n    template<typename Rhs, typename Dest>\n    bool _solve_impl(const MatrixBase<Rhs> &B, MatrixBase<Dest> &X_base) const\n    {\n      Dest& X(X_base.derived());\n      eigen_assert(m_factorizationIsOk && \"The matrix should be factorized first\");\n      EIGEN_STATIC_ASSERT((Dest::Flags&RowMajorBit)==0,\n                        THIS_METHOD_IS_ONLY_FOR_COLUMN_MAJOR_MATRICES);\n      \n      // Permute the right hand side to form X = Pr*B\n      // on return, X is overwritten by the computed solution\n      X.resize(B.rows(),B.cols());\n\n      // this ugly const_cast_derived() helps to detect aliasing when applying the permutations\n      for(Index j = 0; j < B.cols(); ++j)\n        X.col(j) = rowsPermutation() * B.const_cast_derived().col(j);\n      \n      //Forward substitution with L\n      this->matrixL().solveInPlace(X);\n      this->matrixU().solveInPlace(X);\n      \n      // Permute back the solution \n      for (Index j = 0; j < B.cols(); ++j)\n        X.col(j) = colsPermutation().inverse() * X.col(j);\n      \n      return true; \n    }\n    \n    /**\n      * \\returns the absolute value of the determinant of the matrix of which\n      * *this is the QR decomposition.\n      *\n      * \\warning a determinant can be very big or small, so for matrices\n      * of large enough dimension, there is a risk of overflow/underflow.\n      * One way to work around that is to use logAbsDeterminant() instead.\n      *\n      * \\sa logAbsDeterminant(), signDeterminant()\n      */\n    Scalar absDeterminant()\n    {\n      using std::abs;\n      eigen_assert(m_factorizationIsOk && \"The matrix should be factorized first.\");\n      // Initialize with the determinant of the row matrix\n      Scalar det = Scalar(1.);\n      // Note that the diagonal blocks of U are stored in supernodes,\n      // which are available in the  L part :)\n      for (Index j = 0; j < this->cols(); ++j)\n      {\n        for (typename SCMatrix::InnerIterator it(m_Lstore, j); it; ++it)\n        {\n          if(it.index() == j)\n          {\n            det *= abs(it.value());\n            break;\n          }\n        }\n      }\n      return det;\n    }\n\n    /** \\returns the natural log of the absolute value of the determinant of the matrix\n      * of which **this is the QR decomposition\n      *\n      * \\note This method is useful to work around the risk of overflow/underflow that's\n      * inherent to the determinant computation.\n      *\n      * \\sa absDeterminant(), signDeterminant()\n      */\n    Scalar logAbsDeterminant() const\n    {\n      using std::log;\n      using std::abs;\n\n      eigen_assert(m_factorizationIsOk && \"The matrix should be factorized first.\");\n      Scalar det = Scalar(0.);\n      for (Index j = 0; j < this->cols(); ++j)\n      {\n        for (typename SCMatrix::InnerIterator it(m_Lstore, j); it; ++it)\n        {\n          if(it.row() < j) continue;\n          if(it.row() == j)\n          {\n            det += log(abs(it.value()));\n            break;\n          }\n        }\n      }\n      return det;\n    }\n\n    /** \\returns A number representing the sign of the determinant\n      *\n      * \\sa absDeterminant(), logAbsDeterminant()\n      */\n    Scalar signDeterminant()\n    {\n      eigen_assert(m_factorizationIsOk && \"The matrix should be factorized first.\");\n      // Initialize with the determinant of the row matrix\n      Index det = 1;\n      // Note that the diagonal blocks of U are stored in supernodes,\n      // which are available in the  L part :)\n      for (Index j = 0; j < this->cols(); ++j)\n      {\n        for (typename SCMatrix::InnerIterator it(m_Lstore, j); it; ++it)\n        {\n          if(it.index() == j)\n          {\n            if(it.value()<0)\n              det = -det;\n            else if(it.value()==0)\n              return 0;\n            break;\n          }\n        }\n      }\n      return det * m_detPermR * m_detPermC;\n    }\n    \n    /** \\returns The determinant of the matrix.\n      *\n      * \\sa absDeterminant(), logAbsDeterminant()\n      */\n    Scalar determinant()\n    {\n      eigen_assert(m_factorizationIsOk && \"The matrix should be factorized first.\");\n      // Initialize with the determinant of the row matrix\n      Scalar det = Scalar(1.);\n      // Note that the diagonal blocks of U are stored in supernodes,\n      // which are available in the  L part :)\n      for (Index j = 0; j < this->cols(); ++j)\n      {\n        for (typename SCMatrix::InnerIterator it(m_Lstore, j); it; ++it)\n        {\n          if(it.index() == j)\n          {\n            det *= it.value();\n            break;\n          }\n        }\n      }\n      return (m_detPermR * m_detPermC) > 0 ? det : -det;\n    }\n\n  protected:\n    // Functions \n    void initperfvalues()\n    {\n      m_perfv.panel_size = 16;\n      m_perfv.relax = 1; \n      m_perfv.maxsuper = 128; \n      m_perfv.rowblk = 16; \n      m_perfv.colblk = 8; \n      m_perfv.fillfactor = 20;  \n    }\n      \n    // Variables \n    mutable ComputationInfo m_info;\n    bool m_factorizationIsOk;\n    bool m_analysisIsOk;\n    std::string m_lastError;\n    NCMatrix m_mat; // The input (permuted ) matrix \n    SCMatrix m_Lstore; // The lower triangular matrix (supernodal)\n    MappedSparseMatrix<Scalar,ColMajor,StorageIndex> m_Ustore; // The upper triangular matrix\n    PermutationType m_perm_c; // Column permutation \n    PermutationType m_perm_r ; // Row permutation\n    IndexVector m_etree; // Column elimination tree \n    \n    typename Base::GlobalLU_t m_glu; \n                               \n    // SparseLU options \n    bool m_symmetricmode;\n    // values for performance \n    internal::perfvalues m_perfv;\n    RealScalar m_diagpivotthresh; // Specifies the threshold used for a diagonal entry to be an acceptable pivot\n    Index m_nnzL, m_nnzU; // Nonzeros in L and U factors\n    Index m_detPermR, m_detPermC; // Determinants of the permutation matrices\n  private:\n    // Disable copy constructor \n    SparseLU (const SparseLU& );\n  \n}; // End class SparseLU\n\n\n\n// Functions needed by the anaysis phase\n/** \n  * Compute the column permutation to minimize the fill-in\n  * \n  *  - Apply this permutation to the input matrix - \n  * \n  *  - Compute the column elimination tree on the permuted matrix \n  * \n  *  - Postorder the elimination tree and the column permutation\n  * \n  */\ntemplate <typename MatrixType, typename OrderingType>\nvoid SparseLU<MatrixType, OrderingType>::analyzePattern(const MatrixType& mat)\n{\n  \n  //TODO  It is possible as in SuperLU to compute row and columns scaling vectors to equilibrate the matrix mat.\n  \n  // Firstly, copy the whole input matrix. \n  m_mat = mat;\n  \n  // Compute fill-in ordering\n  OrderingType ord; \n  ord(m_mat,m_perm_c);\n  \n  // Apply the permutation to the column of the input  matrix\n  if (m_perm_c.size())\n  {\n    m_mat.uncompress(); //NOTE: The effect of this command is only to create the InnerNonzeros pointers. FIXME : This vector is filled but not subsequently used.  \n    // Then, permute only the column pointers\n    ei_declare_aligned_stack_constructed_variable(StorageIndex,outerIndexPtr,mat.cols()+1,mat.isCompressed()?const_cast<StorageIndex*>(mat.outerIndexPtr()):0);\n    \n    // If the input matrix 'mat' is uncompressed, then the outer-indices do not match the ones of m_mat, and a copy is thus needed.\n    if(!mat.isCompressed()) \n      IndexVector::Map(outerIndexPtr, mat.cols()+1) = IndexVector::Map(m_mat.outerIndexPtr(),mat.cols()+1);\n    \n    // Apply the permutation and compute the nnz per column.\n    for (Index i = 0; i < mat.cols(); i++)\n    {\n      m_mat.outerIndexPtr()[m_perm_c.indices()(i)] = outerIndexPtr[i];\n      m_mat.innerNonZeroPtr()[m_perm_c.indices()(i)] = outerIndexPtr[i+1] - outerIndexPtr[i];\n    }\n  }\n  \n  // Compute the column elimination tree of the permuted matrix \n  IndexVector firstRowElt;\n  internal::coletree(m_mat, m_etree,firstRowElt); \n     \n  // In symmetric mode, do not do postorder here\n  if (!m_symmetricmode) {\n    IndexVector post, iwork; \n    // Post order etree\n    internal::treePostorder(StorageIndex(m_mat.cols()), m_etree, post); \n      \n   \n    // Renumber etree in postorder \n    Index m = m_mat.cols(); \n    iwork.resize(m+1);\n    for (Index i = 0; i < m; ++i) iwork(post(i)) = post(m_etree(i));\n    m_etree = iwork;\n    \n    // Postmultiply A*Pc by post, i.e reorder the matrix according to the postorder of the etree\n    PermutationType post_perm(m); \n    for (Index i = 0; i < m; i++) \n      post_perm.indices()(i) = post(i); \n        \n    // Combine the two permutations : postorder the permutation for future use\n    if(m_perm_c.size()) {\n      m_perm_c = post_perm * m_perm_c;\n    }\n    \n  } // end postordering \n  \n  m_analysisIsOk = true; \n}\n\n// Functions needed by the numerical factorization phase\n\n\n/** \n  *  - Numerical factorization \n  *  - Interleaved with the symbolic factorization \n  * On exit,  info is \n  * \n  *    = 0: successful factorization\n  * \n  *    > 0: if info = i, and i is\n  * \n  *       <= A->ncol: U(i,i) is exactly zero. The factorization has\n  *          been completed, but the factor U is exactly singular,\n  *          and division by zero will occur if it is used to solve a\n  *          system of equations.\n  * \n  *       > A->ncol: number of bytes allocated when memory allocation\n  *         failure occurred, plus A->ncol. If lwork = -1, it is\n  *         the estimated amount of space needed, plus A->ncol.  \n  */\ntemplate <typename MatrixType, typename OrderingType>\nvoid SparseLU<MatrixType, OrderingType>::factorize(const MatrixType& matrix)\n{\n  using internal::emptyIdxLU;\n  eigen_assert(m_analysisIsOk && \"analyzePattern() should be called first\"); \n  eigen_assert((matrix.rows() == matrix.cols()) && \"Only for squared matrices\");\n  \n  typedef typename IndexVector::Scalar StorageIndex; \n  \n  m_isInitialized = true;\n  \n  \n  // Apply the column permutation computed in analyzepattern()\n  //   m_mat = matrix * m_perm_c.inverse(); \n  m_mat = matrix;\n  if (m_perm_c.size()) \n  {\n    m_mat.uncompress(); //NOTE: The effect of this command is only to create the InnerNonzeros pointers.\n    //Then, permute only the column pointers\n    const StorageIndex * outerIndexPtr;\n    if (matrix.isCompressed()) outerIndexPtr = matrix.outerIndexPtr();\n    else\n    {\n      StorageIndex* outerIndexPtr_t = new StorageIndex[matrix.cols()+1];\n      for(Index i = 0; i <= matrix.cols(); i++) outerIndexPtr_t[i] = m_mat.outerIndexPtr()[i];\n      outerIndexPtr = outerIndexPtr_t;\n    }\n    for (Index i = 0; i < matrix.cols(); i++)\n    {\n      m_mat.outerIndexPtr()[m_perm_c.indices()(i)] = outerIndexPtr[i];\n      m_mat.innerNonZeroPtr()[m_perm_c.indices()(i)] = outerIndexPtr[i+1] - outerIndexPtr[i];\n    }\n    if(!matrix.isCompressed()) delete[] outerIndexPtr;\n  } \n  else \n  { //FIXME This should not be needed if the empty permutation is handled transparently\n    m_perm_c.resize(matrix.cols());\n    for(StorageIndex i = 0; i < matrix.cols(); ++i) m_perm_c.indices()(i) = i;\n  }\n  \n  Index m = m_mat.rows();\n  Index n = m_mat.cols();\n  Index nnz = m_mat.nonZeros();\n  Index maxpanel = m_perfv.panel_size * m;\n  // Allocate working storage common to the factor routines\n  Index lwork = 0;\n  Index info = Base::memInit(m, n, nnz, lwork, m_perfv.fillfactor, m_perfv.panel_size, m_glu); \n  if (info) \n  {\n    m_lastError = \"UNABLE TO ALLOCATE WORKING MEMORY\\n\\n\" ;\n    m_factorizationIsOk = false;\n    return ; \n  }\n  \n  // Set up pointers for integer working arrays \n  IndexVector segrep(m); segrep.setZero();\n  IndexVector parent(m); parent.setZero();\n  IndexVector xplore(m); xplore.setZero();\n  IndexVector repfnz(maxpanel);\n  IndexVector panel_lsub(maxpanel);\n  IndexVector xprune(n); xprune.setZero();\n  IndexVector marker(m*internal::LUNoMarker); marker.setZero();\n  \n  repfnz.setConstant(-1); \n  panel_lsub.setConstant(-1);\n  \n  // Set up pointers for scalar working arrays \n  ScalarVector dense; \n  dense.setZero(maxpanel);\n  ScalarVector tempv; \n  tempv.setZero(internal::LUnumTempV(m, m_perfv.panel_size, m_perfv.maxsuper, /*m_perfv.rowblk*/m) );\n  \n  // Compute the inverse of perm_c\n  PermutationType iperm_c(m_perm_c.inverse()); \n  \n  // Identify initial relaxed snodes\n  IndexVector relax_end(n);\n  if ( m_symmetricmode == true ) \n    Base::heap_relax_snode(n, m_etree, m_perfv.relax, marker, relax_end);\n  else\n    Base::relax_snode(n, m_etree, m_perfv.relax, marker, relax_end);\n  \n  \n  m_perm_r.resize(m); \n  m_perm_r.indices().setConstant(-1);\n  marker.setConstant(-1);\n  m_detPermR = 1; // Record the determinant of the row permutation\n  \n  m_glu.supno(0) = emptyIdxLU; m_glu.xsup.setConstant(0);\n  m_glu.xsup(0) = m_glu.xlsub(0) = m_glu.xusub(0) = m_glu.xlusup(0) = Index(0);\n  \n  // Work on one 'panel' at a time. A panel is one of the following :\n  //  (a) a relaxed supernode at the bottom of the etree, or\n  //  (b) panel_size contiguous columns, <panel_size> defined by the user\n  Index jcol; \n  IndexVector panel_histo(n);\n  Index pivrow; // Pivotal row number in the original row matrix\n  Index nseg1; // Number of segments in U-column above panel row jcol\n  Index nseg; // Number of segments in each U-column \n  Index irep; \n  Index i, k, jj; \n  for (jcol = 0; jcol < n; )\n  {\n    // Adjust panel size so that a panel won't overlap with the next relaxed snode. \n    Index panel_size = m_perfv.panel_size; // upper bound on panel width\n    for (k = jcol + 1; k < (std::min)(jcol+panel_size, n); k++)\n    {\n      if (relax_end(k) != emptyIdxLU) \n      {\n        panel_size = k - jcol; \n        break; \n      }\n    }\n    if (k == n) \n      panel_size = n - jcol; \n      \n    // Symbolic outer factorization on a panel of columns \n    Base::panel_dfs(m, panel_size, jcol, m_mat, m_perm_r.indices(), nseg1, dense, panel_lsub, segrep, repfnz, xprune, marker, parent, xplore, m_glu); \n    \n    // Numeric sup-panel updates in topological order \n    Base::panel_bmod(m, panel_size, jcol, nseg1, dense, tempv, segrep, repfnz, m_glu); \n    \n    // Sparse LU within the panel, and below the panel diagonal \n    for ( jj = jcol; jj< jcol + panel_size; jj++) \n    {\n      k = (jj - jcol) * m; // Column index for w-wide arrays \n      \n      nseg = nseg1; // begin after all the panel segments\n      //Depth-first-search for the current column\n      VectorBlock<IndexVector> panel_lsubk(panel_lsub, k, m);\n      VectorBlock<IndexVector> repfnz_k(repfnz, k, m); \n      info = Base::column_dfs(m, jj, m_perm_r.indices(), m_perfv.maxsuper, nseg, panel_lsubk, segrep, repfnz_k, xprune, marker, parent, xplore, m_glu); \n      if ( info ) \n      {\n        m_lastError =  \"UNABLE TO EXPAND MEMORY IN COLUMN_DFS() \";\n        m_info = NumericalIssue; \n        m_factorizationIsOk = false; \n        return; \n      }\n      // Numeric updates to this column \n      VectorBlock<ScalarVector> dense_k(dense, k, m); \n      VectorBlock<IndexVector> segrep_k(segrep, nseg1, m-nseg1); \n      info = Base::column_bmod(jj, (nseg - nseg1), dense_k, tempv, segrep_k, repfnz_k, jcol, m_glu); \n      if ( info ) \n      {\n        m_lastError = \"UNABLE TO EXPAND MEMORY IN COLUMN_BMOD() \";\n        m_info = NumericalIssue; \n        m_factorizationIsOk = false; \n        return; \n      }\n      \n      // Copy the U-segments to ucol(*)\n      info = Base::copy_to_ucol(jj, nseg, segrep, repfnz_k ,m_perm_r.indices(), dense_k, m_glu); \n      if ( info ) \n      {\n        m_lastError = \"UNABLE TO EXPAND MEMORY IN COPY_TO_UCOL() \";\n        m_info = NumericalIssue; \n        m_factorizationIsOk = false; \n        return; \n      }\n      \n      // Form the L-segment \n      info = Base::pivotL(jj, m_diagpivotthresh, m_perm_r.indices(), iperm_c.indices(), pivrow, m_glu);\n      if ( info ) \n      {\n        m_lastError = \"THE MATRIX IS STRUCTURALLY SINGULAR ... ZERO COLUMN AT \";\n        std::ostringstream returnInfo;\n        returnInfo << info; \n        m_lastError += returnInfo.str();\n        m_info = NumericalIssue; \n        m_factorizationIsOk = false; \n        return; \n      }\n      \n      // Update the determinant of the row permutation matrix\n      // FIXME: the following test is not correct, we should probably take iperm_c into account and pivrow is not directly the row pivot.\n      if (pivrow != jj) m_detPermR = -m_detPermR;\n\n      // Prune columns (0:jj-1) using column jj\n      Base::pruneL(jj, m_perm_r.indices(), pivrow, nseg, segrep, repfnz_k, xprune, m_glu); \n      \n      // Reset repfnz for this column \n      for (i = 0; i < nseg; i++)\n      {\n        irep = segrep(i); \n        repfnz_k(irep) = emptyIdxLU; \n      }\n    } // end SparseLU within the panel  \n    jcol += panel_size;  // Move to the next panel\n  } // end for -- end elimination \n  \n  m_detPermR = m_perm_r.determinant();\n  m_detPermC = m_perm_c.determinant();\n  \n  // Count the number of nonzeros in factors \n  Base::countnz(n, m_nnzL, m_nnzU, m_glu); \n  // Apply permutation  to the L subscripts \n  Base::fixupL(n, m_perm_r.indices(), m_glu);\n  \n  // Create supernode matrix L \n  m_Lstore.setInfos(m, n, m_glu.lusup, m_glu.xlusup, m_glu.lsub, m_glu.xlsub, m_glu.supno, m_glu.xsup); \n  // Create the column major upper sparse matrix  U; \n  new (&m_Ustore) MappedSparseMatrix<Scalar, ColMajor, StorageIndex> ( m, n, m_nnzU, m_glu.xusub.data(), m_glu.usub.data(), m_glu.ucol.data() );\n  \n  m_info = Success;\n  m_factorizationIsOk = true;\n}\n\ntemplate<typename MappedSupernodalType>\nstruct SparseLUMatrixLReturnType : internal::no_assignment_operator\n{\n  typedef typename MappedSupernodalType::Scalar Scalar;\n  explicit SparseLUMatrixLReturnType(const MappedSupernodalType& mapL) : m_mapL(mapL)\n  { }\n  Index rows() { return m_mapL.rows(); }\n  Index cols() { return m_mapL.cols(); }\n  template<typename Dest>\n  void solveInPlace( MatrixBase<Dest> &X) const\n  {\n    m_mapL.solveInPlace(X);\n  }\n  const MappedSupernodalType& m_mapL;\n};\n\ntemplate<typename MatrixLType, typename MatrixUType>\nstruct SparseLUMatrixUReturnType : internal::no_assignment_operator\n{\n  typedef typename MatrixLType::Scalar Scalar;\n  SparseLUMatrixUReturnType(const MatrixLType& mapL, const MatrixUType& mapU)\n  : m_mapL(mapL),m_mapU(mapU)\n  { }\n  Index rows() { return m_mapL.rows(); }\n  Index cols() { return m_mapL.cols(); }\n\n  template<typename Dest>   void solveInPlace(MatrixBase<Dest> &X) const\n  {\n    Index nrhs = X.cols();\n    Index n    = X.rows();\n    // Backward solve with U\n    for (Index k = m_mapL.nsuper(); k >= 0; k--)\n    {\n      Index fsupc = m_mapL.supToCol()[k];\n      Index lda = m_mapL.colIndexPtr()[fsupc+1] - m_mapL.colIndexPtr()[fsupc]; // leading dimension\n      Index nsupc = m_mapL.supToCol()[k+1] - fsupc;\n      Index luptr = m_mapL.colIndexPtr()[fsupc];\n\n      if (nsupc == 1)\n      {\n        for (Index j = 0; j < nrhs; j++)\n        {\n          X(fsupc, j) /= m_mapL.valuePtr()[luptr];\n        }\n      }\n      else\n      {\n        Map<const Matrix<Scalar,Dynamic,Dynamic, ColMajor>, 0, OuterStride<> > A( &(m_mapL.valuePtr()[luptr]), nsupc, nsupc, OuterStride<>(lda) );\n        Map< Matrix<Scalar,Dynamic,Dynamic, ColMajor>, 0, OuterStride<> > U (&(X(fsupc,0)), nsupc, nrhs, OuterStride<>(n) );\n        U = A.template triangularView<Upper>().solve(U);\n      }\n\n      for (Index j = 0; j < nrhs; ++j)\n      {\n        for (Index jcol = fsupc; jcol < fsupc + nsupc; jcol++)\n        {\n          typename MatrixUType::InnerIterator it(m_mapU, jcol);\n          for ( ; it; ++it)\n          {\n            Index irow = it.index();\n            X(irow, j) -= X(jcol, j) * it.value();\n          }\n        }\n      }\n    } // End For U-solve\n  }\n  const MatrixLType& m_mapL;\n  const MatrixUType& m_mapU;\n};\n\n} // End namespace Eigen \n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseLU/SparseLUImpl.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2012 Désiré Nuentsa-Wakam <desire.nuentsa_wakam@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n#ifndef SPARSELU_IMPL_H\n#define SPARSELU_IMPL_H\n\nnamespace Eigen {\nnamespace internal {\n  \n/** \\ingroup SparseLU_Module\n  * \\class SparseLUImpl\n  * Base class for sparseLU\n  */\ntemplate <typename Scalar, typename StorageIndex>\nclass SparseLUImpl\n{\n  public:\n    typedef Matrix<Scalar,Dynamic,1> ScalarVector;\n    typedef Matrix<StorageIndex,Dynamic,1> IndexVector; \n    typedef Matrix<Scalar,Dynamic,Dynamic,ColMajor> ScalarMatrix;\n    typedef Map<ScalarMatrix, 0,  OuterStride<> > MappedMatrixBlock;\n    typedef typename ScalarVector::RealScalar RealScalar; \n    typedef Ref<Matrix<Scalar,Dynamic,1> > BlockScalarVector;\n    typedef Ref<Matrix<StorageIndex,Dynamic,1> > BlockIndexVector;\n    typedef LU_GlobalLU_t<IndexVector, ScalarVector> GlobalLU_t; \n    typedef SparseMatrix<Scalar,ColMajor,StorageIndex> MatrixType; \n    \n  protected:\n     template <typename VectorType>\n     Index expand(VectorType& vec, Index& length, Index nbElts, Index keep_prev, Index& num_expansions);\n     Index memInit(Index m, Index n, Index annz, Index lwork, Index fillratio, Index panel_size,  GlobalLU_t& glu); \n     template <typename VectorType>\n     Index memXpand(VectorType& vec, Index& maxlen, Index nbElts, MemType memtype, Index& num_expansions);\n     void heap_relax_snode (const Index n, IndexVector& et, const Index relax_columns, IndexVector& descendants, IndexVector& relax_end); \n     void relax_snode (const Index n, IndexVector& et, const Index relax_columns, IndexVector& descendants, IndexVector& relax_end); \n     Index snode_dfs(const Index jcol, const Index kcol,const MatrixType& mat,  IndexVector& xprune, IndexVector& marker, GlobalLU_t& glu); \n     Index snode_bmod (const Index jcol, const Index fsupc, ScalarVector& dense, GlobalLU_t& glu);\n     Index pivotL(const Index jcol, const RealScalar& diagpivotthresh, IndexVector& perm_r, IndexVector& iperm_c, Index& pivrow, GlobalLU_t& glu);\n     template <typename Traits>\n     void dfs_kernel(const StorageIndex jj, IndexVector& perm_r,\n                    Index& nseg, IndexVector& panel_lsub, IndexVector& segrep,\n                    Ref<IndexVector> repfnz_col, IndexVector& xprune, Ref<IndexVector> marker, IndexVector& parent,\n                    IndexVector& xplore, GlobalLU_t& glu, Index& nextl_col, Index krow, Traits& traits);\n     void panel_dfs(const Index m, const Index w, const Index jcol, MatrixType& A, IndexVector& perm_r, Index& nseg, ScalarVector& dense, IndexVector& panel_lsub, IndexVector& segrep, IndexVector& repfnz, IndexVector& xprune, IndexVector& marker, IndexVector& parent, IndexVector& xplore, GlobalLU_t& glu);\n    \n     void panel_bmod(const Index m, const Index w, const Index jcol, const Index nseg, ScalarVector& dense, ScalarVector& tempv, IndexVector& segrep, IndexVector& repfnz, GlobalLU_t& glu);\n     Index column_dfs(const Index m, const Index jcol, IndexVector& perm_r, Index maxsuper, Index& nseg,  BlockIndexVector lsub_col, IndexVector& segrep, BlockIndexVector repfnz, IndexVector& xprune, IndexVector& marker, IndexVector& parent, IndexVector& xplore, GlobalLU_t& glu);\n     Index column_bmod(const Index jcol, const Index nseg, BlockScalarVector dense, ScalarVector& tempv, BlockIndexVector segrep, BlockIndexVector repfnz, Index fpanelc, GlobalLU_t& glu); \n     Index copy_to_ucol(const Index jcol, const Index nseg, IndexVector& segrep, BlockIndexVector repfnz ,IndexVector& perm_r, BlockScalarVector dense, GlobalLU_t& glu); \n     void pruneL(const Index jcol, const IndexVector& perm_r, const Index pivrow, const Index nseg, const IndexVector& segrep, BlockIndexVector repfnz, IndexVector& xprune, GlobalLU_t& glu);\n     void countnz(const Index n, Index& nnzL, Index& nnzU, GlobalLU_t& glu); \n     void fixupL(const Index n, const IndexVector& perm_r, GlobalLU_t& glu); \n     \n     template<typename , typename >\n     friend struct column_dfs_traits;\n}; \n\n} // end namespace internal\n} // namespace Eigen\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseLU/SparseLU_Memory.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2012 Désiré Nuentsa-Wakam <desire.nuentsa_wakam@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n/* \n \n * NOTE: This file is the modified version of [s,d,c,z]memory.c files in SuperLU \n \n * -- SuperLU routine (version 3.1) --\n * Univ. of California Berkeley, Xerox Palo Alto Research Center,\n * and Lawrence Berkeley National Lab.\n * August 1, 2008\n *\n * Copyright (c) 1994 by Xerox Corporation.  All rights reserved.\n *\n * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY\n * EXPRESSED OR IMPLIED.  ANY USE IS AT YOUR OWN RISK.\n *\n * Permission is hereby granted to use or copy this program for any\n * purpose, provided the above notices are retained on all copies.\n * Permission to modify the code and to distribute modified code is\n * granted, provided the above notices are retained, and a notice that\n * the code was modified is included with the above copyright notice.\n */\n\n#ifndef EIGEN_SPARSELU_MEMORY\n#define EIGEN_SPARSELU_MEMORY\n\nnamespace Eigen {\nnamespace internal {\n  \nenum { LUNoMarker = 3 };\nenum {emptyIdxLU = -1};\ninline Index LUnumTempV(Index& m, Index& w, Index& t, Index& b)\n{\n  return (std::max)(m, (t+b)*w);\n}\n\ntemplate< typename Scalar>\ninline Index LUTempSpace(Index&m, Index& w)\n{\n  return (2*w + 4 + LUNoMarker) * m * sizeof(Index) + (w + 1) * m * sizeof(Scalar);\n}\n\n\n\n\n/** \n  * Expand the existing storage to accomodate more fill-ins\n  * \\param vec Valid pointer to the vector to allocate or expand\n  * \\param[in,out] length  At input, contain the current length of the vector that is to be increased. At output, length of the newly allocated vector\n  * \\param[in] nbElts Current number of elements in the factors\n  * \\param keep_prev  1: use length  and do not expand the vector; 0: compute new_len and expand\n  * \\param[in,out] num_expansions Number of times the memory has been expanded\n  */\ntemplate <typename Scalar, typename StorageIndex>\ntemplate <typename VectorType>\nIndex  SparseLUImpl<Scalar,StorageIndex>::expand(VectorType& vec, Index& length, Index nbElts, Index keep_prev, Index& num_expansions) \n{\n  \n  float alpha = 1.5; // Ratio of the memory increase \n  Index new_len; // New size of the allocated memory\n  \n  if(num_expansions == 0 || keep_prev) \n    new_len = length ; // First time allocate requested\n  else \n    new_len = (std::max)(length+1,Index(alpha * length));\n  \n  VectorType old_vec; // Temporary vector to hold the previous values   \n  if (nbElts > 0 )\n    old_vec = vec.segment(0,nbElts); \n  \n  //Allocate or expand the current vector\n#ifdef EIGEN_EXCEPTIONS\n  try\n#endif\n  {\n    vec.resize(new_len); \n  }\n#ifdef EIGEN_EXCEPTIONS\n  catch(std::bad_alloc& )\n#else\n  if(!vec.size())\n#endif\n  {\n    if (!num_expansions)\n    {\n      // First time to allocate from LUMemInit()\n      // Let LUMemInit() deals with it.\n      return -1;\n    }\n    if (keep_prev)\n    {\n      // In this case, the memory length should not not be reduced\n      return new_len;\n    }\n    else \n    {\n      // Reduce the size and increase again \n      Index tries = 0; // Number of attempts\n      do \n      {\n        alpha = (alpha + 1)/2;\n        new_len = (std::max)(length+1,Index(alpha * length));\n#ifdef EIGEN_EXCEPTIONS\n        try\n#endif\n        {\n          vec.resize(new_len); \n        }\n#ifdef EIGEN_EXCEPTIONS\n        catch(std::bad_alloc& )\n#else\n        if (!vec.size())\n#endif\n        {\n          tries += 1; \n          if ( tries > 10) return new_len; \n        }\n      } while (!vec.size());\n    }\n  }\n  //Copy the previous values to the newly allocated space \n  if (nbElts > 0)\n    vec.segment(0, nbElts) = old_vec;   \n   \n  \n  length  = new_len;\n  if(num_expansions) ++num_expansions;\n  return 0; \n}\n\n/**\n * \\brief  Allocate various working space for the numerical factorization phase.\n * \\param m number of rows of the input matrix \n * \\param n number of columns \n * \\param annz number of initial nonzeros in the matrix \n * \\param lwork  if lwork=-1, this routine returns an estimated size of the required memory\n * \\param glu persistent data to facilitate multiple factors : will be deleted later ??\n * \\param fillratio estimated ratio of fill in the factors\n * \\param panel_size Size of a panel\n * \\return an estimated size of the required memory if lwork = -1; otherwise, return the size of actually allocated memory when allocation failed, and 0 on success\n * \\note Unlike SuperLU, this routine does not support successive factorization with the same pattern and the same row permutation\n */\ntemplate <typename Scalar, typename StorageIndex>\nIndex SparseLUImpl<Scalar,StorageIndex>::memInit(Index m, Index n, Index annz, Index lwork, Index fillratio, Index panel_size,  GlobalLU_t& glu)\n{\n  Index& num_expansions = glu.num_expansions; //No memory expansions so far\n  num_expansions = 0;\n  glu.nzumax = glu.nzlumax = (std::min)(fillratio * (annz+1) / n, m) * n; // estimated number of nonzeros in U \n  glu.nzlmax = (std::max)(Index(4), fillratio) * (annz+1) / 4; // estimated  nnz in L factor\n  // Return the estimated size to the user if necessary\n  Index tempSpace;\n  tempSpace = (2*panel_size + 4 + LUNoMarker) * m * sizeof(Index) + (panel_size + 1) * m * sizeof(Scalar);\n  if (lwork == emptyIdxLU) \n  {\n    Index estimated_size;\n    estimated_size = (5 * n + 5) * sizeof(Index)  + tempSpace\n                    + (glu.nzlmax + glu.nzumax) * sizeof(Index) + (glu.nzlumax+glu.nzumax) *  sizeof(Scalar) + n; \n    return estimated_size;\n  }\n  \n  // Setup the required space \n  \n  // First allocate Integer pointers for L\\U factors\n  glu.xsup.resize(n+1);\n  glu.supno.resize(n+1);\n  glu.xlsub.resize(n+1);\n  glu.xlusup.resize(n+1);\n  glu.xusub.resize(n+1);\n\n  // Reserve memory for L/U factors\n  do \n  {\n    if(     (expand<ScalarVector>(glu.lusup, glu.nzlumax, 0, 0, num_expansions)<0)\n        ||  (expand<ScalarVector>(glu.ucol,  glu.nzumax,  0, 0, num_expansions)<0)\n        ||  (expand<IndexVector> (glu.lsub,  glu.nzlmax,  0, 0, num_expansions)<0)\n        ||  (expand<IndexVector> (glu.usub,  glu.nzumax,  0, 1, num_expansions)<0) )\n    {\n      //Reduce the estimated size and retry\n      glu.nzlumax /= 2;\n      glu.nzumax /= 2;\n      glu.nzlmax /= 2;\n      if (glu.nzlumax < annz ) return glu.nzlumax; \n    }\n  } while (!glu.lusup.size() || !glu.ucol.size() || !glu.lsub.size() || !glu.usub.size());\n  \n  ++num_expansions;\n  return 0;\n  \n} // end LuMemInit\n\n/** \n * \\brief Expand the existing storage \n * \\param vec vector to expand \n * \\param[in,out] maxlen On input, previous size of vec (Number of elements to copy ). on output, new size\n * \\param nbElts current number of elements in the vector.\n * \\param memtype Type of the element to expand\n * \\param num_expansions Number of expansions \n * \\return 0 on success, > 0 size of the memory allocated so far\n */\ntemplate <typename Scalar, typename StorageIndex>\ntemplate <typename VectorType>\nIndex SparseLUImpl<Scalar,StorageIndex>::memXpand(VectorType& vec, Index& maxlen, Index nbElts, MemType memtype, Index& num_expansions)\n{\n  Index failed_size; \n  if (memtype == USUB)\n     failed_size = this->expand<VectorType>(vec, maxlen, nbElts, 1, num_expansions);\n  else\n    failed_size = this->expand<VectorType>(vec, maxlen, nbElts, 0, num_expansions);\n\n  if (failed_size)\n    return failed_size; \n  \n  return 0 ;  \n}\n\n} // end namespace internal\n\n} // end namespace Eigen\n#endif // EIGEN_SPARSELU_MEMORY\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseLU/SparseLU_Structs.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2012 Désiré Nuentsa-Wakam <desire.nuentsa_wakam@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n/* \n * NOTE: This file comes from a partly modified version of files slu_[s,d,c,z]defs.h\n * -- SuperLU routine (version 4.1) --\n * Univ. of California Berkeley, Xerox Palo Alto Research Center,\n * and Lawrence Berkeley National Lab.\n * November, 2010\n * \n * Global data structures used in LU factorization -\n * \n *   nsuper: #supernodes = nsuper + 1, numbered [0, nsuper].\n *   (xsup,supno): supno[i] is the supernode no to which i belongs;\n *  xsup(s) points to the beginning of the s-th supernode.\n *  e.g.   supno 0 1 2 2 3 3 3 4 4 4 4 4   (n=12)\n *          xsup 0 1 2 4 7 12\n *  Note: dfs will be performed on supernode rep. relative to the new \n *        row pivoting ordering\n *\n *   (xlsub,lsub): lsub[*] contains the compressed subscript of\n *  rectangular supernodes; xlsub[j] points to the starting\n *  location of the j-th column in lsub[*]. Note that xlsub \n *  is indexed by column.\n *  Storage: original row subscripts\n *\n *      During the course of sparse LU factorization, we also use\n *  (xlsub,lsub) for the purpose of symmetric pruning. For each\n *  supernode {s,s+1,...,t=s+r} with first column s and last\n *  column t, the subscript set\n *    lsub[j], j=xlsub[s], .., xlsub[s+1]-1\n *  is the structure of column s (i.e. structure of this supernode).\n *  It is used for the storage of numerical values.\n *  Furthermore,\n *    lsub[j], j=xlsub[t], .., xlsub[t+1]-1\n *  is the structure of the last column t of this supernode.\n *  It is for the purpose of symmetric pruning. Therefore, the\n *  structural subscripts can be rearranged without making physical\n *  interchanges among the numerical values.\n *\n *  However, if the supernode has only one column, then we\n *  only keep one set of subscripts. For any subscript interchange\n *  performed, similar interchange must be done on the numerical\n *  values.\n *\n *  The last column structures (for pruning) will be removed\n *  after the numercial LU factorization phase.\n *\n *   (xlusup,lusup): lusup[*] contains the numerical values of the\n *  rectangular supernodes; xlusup[j] points to the starting\n *  location of the j-th column in storage vector lusup[*]\n *  Note: xlusup is indexed by column.\n *  Each rectangular supernode is stored by column-major\n *  scheme, consistent with Fortran 2-dim array storage.\n *\n *   (xusub,ucol,usub): ucol[*] stores the numerical values of\n *  U-columns outside the rectangular supernodes. The row\n *  subscript of nonzero ucol[k] is stored in usub[k].\n *  xusub[i] points to the starting location of column i in ucol.\n *  Storage: new row subscripts; that is subscripts of PA.\n */\n\n#ifndef EIGEN_LU_STRUCTS\n#define EIGEN_LU_STRUCTS\nnamespace Eigen {\nnamespace internal {\n  \ntypedef enum {LUSUP, UCOL, LSUB, USUB, LLVL, ULVL} MemType; \n\ntemplate <typename IndexVector, typename ScalarVector>\nstruct LU_GlobalLU_t {\n  typedef typename IndexVector::Scalar StorageIndex; \n  IndexVector xsup; //First supernode column ... xsup(s) points to the beginning of the s-th supernode\n  IndexVector supno; // Supernode number corresponding to this column (column to supernode mapping)\n  ScalarVector  lusup; // nonzero values of L ordered by columns \n  IndexVector lsub; // Compressed row indices of L rectangular supernodes. \n  IndexVector xlusup; // pointers to the beginning of each column in lusup\n  IndexVector xlsub; // pointers to the beginning of each column in lsub\n  Index   nzlmax; // Current max size of lsub\n  Index   nzlumax; // Current max size of lusup\n  ScalarVector  ucol; // nonzero values of U ordered by columns \n  IndexVector usub; // row indices of U columns in ucol\n  IndexVector xusub; // Pointers to the beginning of each column of U in ucol \n  Index   nzumax; // Current max size of ucol\n  Index   n; // Number of columns in the matrix  \n  Index   num_expansions; \n};\n\n// Values to set for performance\nstruct perfvalues {\n  Index panel_size; // a panel consists of at most <panel_size> consecutive columns\n  Index relax; // To control degree of relaxing supernodes. If the number of nodes (columns) \n                // in a subtree of the elimination tree is less than relax, this subtree is considered \n                // as one supernode regardless of the row structures of those columns\n  Index maxsuper; // The maximum size for a supernode in complete LU\n  Index rowblk; // The minimum row dimension for 2-D blocking to be used;\n  Index colblk; // The minimum column dimension for 2-D blocking to be used;\n  Index fillfactor; // The estimated fills factors for L and U, compared with A\n}; \n\n} // end namespace internal\n\n} // end namespace Eigen\n#endif // EIGEN_LU_STRUCTS\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseLU/SparseLU_SupernodalMatrix.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2012 Désiré Nuentsa-Wakam <desire.nuentsa_wakam@inria.fr>\n// Copyright (C) 2012 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SPARSELU_SUPERNODAL_MATRIX_H\n#define EIGEN_SPARSELU_SUPERNODAL_MATRIX_H\n\nnamespace Eigen {\nnamespace internal {\n\n/** \\ingroup SparseLU_Module\n * \\brief a class to manipulate the L supernodal factor from the SparseLU factorization\n * \n * This class  contain the data to easily store \n * and manipulate the supernodes during the factorization and solution phase of Sparse LU. \n * Only the lower triangular matrix has supernodes.\n * \n * NOTE : This class corresponds to the SCformat structure in SuperLU\n * \n */\n/* TODO\n * InnerIterator as for sparsematrix \n * SuperInnerIterator to iterate through all supernodes \n * Function for triangular solve\n */\ntemplate <typename _Scalar, typename _StorageIndex>\nclass MappedSuperNodalMatrix\n{\n  public:\n    typedef _Scalar Scalar; \n    typedef _StorageIndex StorageIndex;\n    typedef Matrix<StorageIndex,Dynamic,1> IndexVector;\n    typedef Matrix<Scalar,Dynamic,1> ScalarVector;\n  public:\n    MappedSuperNodalMatrix()\n    {\n      \n    }\n    MappedSuperNodalMatrix(Index m, Index n,  ScalarVector& nzval, IndexVector& nzval_colptr, IndexVector& rowind,\n             IndexVector& rowind_colptr, IndexVector& col_to_sup, IndexVector& sup_to_col )\n    {\n      setInfos(m, n, nzval, nzval_colptr, rowind, rowind_colptr, col_to_sup, sup_to_col);\n    }\n    \n    ~MappedSuperNodalMatrix()\n    {\n      \n    }\n    /**\n     * Set appropriate pointers for the lower triangular supernodal matrix\n     * These infos are available at the end of the numerical factorization\n     * FIXME This class will be modified such that it can be use in the course \n     * of the factorization.\n     */\n    void setInfos(Index m, Index n, ScalarVector& nzval, IndexVector& nzval_colptr, IndexVector& rowind,\n             IndexVector& rowind_colptr, IndexVector& col_to_sup, IndexVector& sup_to_col )\n    {\n      m_row = m;\n      m_col = n; \n      m_nzval = nzval.data(); \n      m_nzval_colptr = nzval_colptr.data(); \n      m_rowind = rowind.data(); \n      m_rowind_colptr = rowind_colptr.data(); \n      m_nsuper = col_to_sup(n); \n      m_col_to_sup = col_to_sup.data(); \n      m_sup_to_col = sup_to_col.data(); \n    }\n    \n    /**\n     * Number of rows\n     */\n    Index rows() { return m_row; }\n    \n    /**\n     * Number of columns\n     */\n    Index cols() { return m_col; }\n    \n    /**\n     * Return the array of nonzero values packed by column\n     * \n     * The size is nnz\n     */\n    Scalar* valuePtr() {  return m_nzval; }\n    \n    const Scalar* valuePtr() const \n    {\n      return m_nzval; \n    }\n    /**\n     * Return the pointers to the beginning of each column in \\ref valuePtr()\n     */\n    StorageIndex* colIndexPtr()\n    {\n      return m_nzval_colptr; \n    }\n    \n    const StorageIndex* colIndexPtr() const\n    {\n      return m_nzval_colptr; \n    }\n    \n    /**\n     * Return the array of compressed row indices of all supernodes\n     */\n    StorageIndex* rowIndex()  { return m_rowind; }\n    \n    const StorageIndex* rowIndex() const\n    {\n      return m_rowind; \n    }\n    \n    /**\n     * Return the location in \\em rowvaluePtr() which starts each column\n     */\n    StorageIndex* rowIndexPtr() { return m_rowind_colptr; }\n    \n    const StorageIndex* rowIndexPtr() const\n    {\n      return m_rowind_colptr; \n    }\n    \n    /** \n     * Return the array of column-to-supernode mapping \n     */\n    StorageIndex* colToSup()  { return m_col_to_sup; }\n    \n    const StorageIndex* colToSup() const\n    {\n      return m_col_to_sup;       \n    }\n    /**\n     * Return the array of supernode-to-column mapping\n     */\n    StorageIndex* supToCol() { return m_sup_to_col; }\n    \n    const StorageIndex* supToCol() const\n    {\n      return m_sup_to_col;\n    }\n    \n    /**\n     * Return the number of supernodes\n     */\n    Index nsuper() const\n    {\n      return m_nsuper; \n    }\n    \n    class InnerIterator; \n    template<typename Dest>\n    void solveInPlace( MatrixBase<Dest>&X) const;\n    \n      \n      \n    \n  protected:\n    Index m_row; // Number of rows\n    Index m_col; // Number of columns\n    Index m_nsuper; // Number of supernodes\n    Scalar* m_nzval; //array of nonzero values packed by column\n    StorageIndex* m_nzval_colptr; //nzval_colptr[j] Stores the location in nzval[] which starts column j\n    StorageIndex* m_rowind; // Array of compressed row indices of rectangular supernodes\n    StorageIndex* m_rowind_colptr; //rowind_colptr[j] stores the location in rowind[] which starts column j\n    StorageIndex* m_col_to_sup; // col_to_sup[j] is the supernode number to which column j belongs\n    StorageIndex* m_sup_to_col; //sup_to_col[s] points to the starting column of the s-th supernode\n    \n  private :\n};\n\n/**\n  * \\brief InnerIterator class to iterate over nonzero values of the current column in the supernodal matrix L\n  * \n  */\ntemplate<typename Scalar, typename StorageIndex>\nclass MappedSuperNodalMatrix<Scalar,StorageIndex>::InnerIterator\n{\n  public:\n     InnerIterator(const MappedSuperNodalMatrix& mat, Index outer)\n      : m_matrix(mat),\n        m_outer(outer),\n        m_supno(mat.colToSup()[outer]),\n        m_idval(mat.colIndexPtr()[outer]),\n        m_startidval(m_idval),\n        m_endidval(mat.colIndexPtr()[outer+1]),\n        m_idrow(mat.rowIndexPtr()[mat.supToCol()[mat.colToSup()[outer]]]),\n        m_endidrow(mat.rowIndexPtr()[mat.supToCol()[mat.colToSup()[outer]]+1])\n    {}\n    inline InnerIterator& operator++()\n    { \n      m_idval++; \n      m_idrow++;\n      return *this;\n    }\n    inline Scalar value() const { return m_matrix.valuePtr()[m_idval]; }\n    \n    inline Scalar& valueRef() { return const_cast<Scalar&>(m_matrix.valuePtr()[m_idval]); }\n    \n    inline Index index() const { return m_matrix.rowIndex()[m_idrow]; }\n    inline Index row() const { return index(); }\n    inline Index col() const { return m_outer; }\n    \n    inline Index supIndex() const { return m_supno; }\n    \n    inline operator bool() const \n    { \n      return ( (m_idval < m_endidval) && (m_idval >= m_startidval)\n                && (m_idrow < m_endidrow) );\n    }\n    \n  protected:\n    const MappedSuperNodalMatrix& m_matrix; // Supernodal lower triangular matrix \n    const Index m_outer;                    // Current column \n    const Index m_supno;                    // Current SuperNode number\n    Index m_idval;                          // Index to browse the values in the current column\n    const Index m_startidval;               // Start of the column value\n    const Index m_endidval;                 // End of the column value\n    Index m_idrow;                          // Index to browse the row indices \n    Index m_endidrow;                       // End index of row indices of the current column\n};\n\n/**\n * \\brief Solve with the supernode triangular matrix\n * \n */\ntemplate<typename Scalar, typename Index_>\ntemplate<typename Dest>\nvoid MappedSuperNodalMatrix<Scalar,Index_>::solveInPlace( MatrixBase<Dest>&X) const\n{\n    /* Explicit type conversion as the Index type of MatrixBase<Dest> may be wider than Index */\n//    eigen_assert(X.rows() <= NumTraits<Index>::highest());\n//    eigen_assert(X.cols() <= NumTraits<Index>::highest());\n    Index n    = int(X.rows());\n    Index nrhs = Index(X.cols());\n    const Scalar * Lval = valuePtr();                 // Nonzero values \n    Matrix<Scalar,Dynamic,Dynamic, ColMajor> work(n, nrhs);     // working vector\n    work.setZero();\n    for (Index k = 0; k <= nsuper(); k ++)\n    {\n      Index fsupc = supToCol()[k];                    // First column of the current supernode \n      Index istart = rowIndexPtr()[fsupc];            // Pointer index to the subscript of the current column\n      Index nsupr = rowIndexPtr()[fsupc+1] - istart;  // Number of rows in the current supernode\n      Index nsupc = supToCol()[k+1] - fsupc;          // Number of columns in the current supernode\n      Index nrow = nsupr - nsupc;                     // Number of rows in the non-diagonal part of the supernode\n      Index irow;                                     //Current index row\n      \n      if (nsupc == 1 )\n      {\n        for (Index j = 0; j < nrhs; j++)\n        {\n          InnerIterator it(*this, fsupc);\n          ++it; // Skip the diagonal element\n          for (; it; ++it)\n          {\n            irow = it.row();\n            X(irow, j) -= X(fsupc, j) * it.value();\n          }\n        }\n      }\n      else\n      {\n        // The supernode has more than one column \n        Index luptr = colIndexPtr()[fsupc]; \n        Index lda = colIndexPtr()[fsupc+1] - luptr;\n        \n        // Triangular solve \n        Map<const Matrix<Scalar,Dynamic,Dynamic, ColMajor>, 0, OuterStride<> > A( &(Lval[luptr]), nsupc, nsupc, OuterStride<>(lda) );\n        Map< Matrix<Scalar,Dynamic,Dynamic, ColMajor>, 0, OuterStride<> > U (&(X(fsupc,0)), nsupc, nrhs, OuterStride<>(n) ); \n        U = A.template triangularView<UnitLower>().solve(U); \n        \n        // Matrix-vector product \n        new (&A) Map<const Matrix<Scalar,Dynamic,Dynamic, ColMajor>, 0, OuterStride<> > ( &(Lval[luptr+nsupc]), nrow, nsupc, OuterStride<>(lda) );\n        work.block(0, 0, nrow, nrhs) = A * U; \n        \n        //Begin Scatter \n        for (Index j = 0; j < nrhs; j++)\n        {\n          Index iptr = istart + nsupc; \n          for (Index i = 0; i < nrow; i++)\n          {\n            irow = rowIndex()[iptr]; \n            X(irow, j) -= work(i, j); // Scatter operation\n            work(i, j) = Scalar(0); \n            iptr++;\n          }\n        }\n      }\n    } \n}\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_SPARSELU_MATRIX_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseLU/SparseLU_Utils.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2012 Désiré Nuentsa-Wakam <desire.nuentsa_wakam@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n\n#ifndef EIGEN_SPARSELU_UTILS_H\n#define EIGEN_SPARSELU_UTILS_H\n\nnamespace Eigen {\nnamespace internal {\n\n/**\n * \\brief Count Nonzero elements in the factors\n */\ntemplate <typename Scalar, typename StorageIndex>\nvoid SparseLUImpl<Scalar,StorageIndex>::countnz(const Index n, Index& nnzL, Index& nnzU, GlobalLU_t& glu)\n{\n nnzL = 0; \n nnzU = (glu.xusub)(n); \n Index nsuper = (glu.supno)(n); \n Index jlen; \n Index i, j, fsupc;\n if (n <= 0 ) return; \n // For each supernode\n for (i = 0; i <= nsuper; i++)\n {\n   fsupc = glu.xsup(i); \n   jlen = glu.xlsub(fsupc+1) - glu.xlsub(fsupc); \n   \n   for (j = fsupc; j < glu.xsup(i+1); j++)\n   {\n     nnzL += jlen; \n     nnzU += j - fsupc + 1; \n     jlen--; \n   }\n }\n}\n\n/**\n * \\brief Fix up the data storage lsub for L-subscripts. \n * \n * It removes the subscripts sets for structural pruning, \n * and applies permutation to the remaining subscripts\n * \n */\ntemplate <typename Scalar, typename StorageIndex>\nvoid SparseLUImpl<Scalar,StorageIndex>::fixupL(const Index n, const IndexVector& perm_r, GlobalLU_t& glu)\n{\n  Index fsupc, i, j, k, jstart; \n  \n  StorageIndex nextl = 0; \n  Index nsuper = (glu.supno)(n); \n  \n  // For each supernode \n  for (i = 0; i <= nsuper; i++)\n  {\n    fsupc = glu.xsup(i); \n    jstart = glu.xlsub(fsupc); \n    glu.xlsub(fsupc) = nextl; \n    for (j = jstart; j < glu.xlsub(fsupc + 1); j++)\n    {\n      glu.lsub(nextl) = perm_r(glu.lsub(j)); // Now indexed into P*A\n      nextl++;\n    }\n    for (k = fsupc+1; k < glu.xsup(i+1); k++)\n      glu.xlsub(k) = nextl; // other columns in supernode i\n  }\n  \n  glu.xlsub(n) = nextl; \n}\n\n} // end namespace internal\n\n} // end namespace Eigen\n#endif // EIGEN_SPARSELU_UTILS_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseLU/SparseLU_column_bmod.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2012 Désiré Nuentsa-Wakam <desire.nuentsa_wakam@inria.fr>\n// Copyright (C) 2012 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n/* \n \n * NOTE: This file is the modified version of xcolumn_bmod.c file in SuperLU \n \n * -- SuperLU routine (version 3.0) --\n * Univ. of California Berkeley, Xerox Palo Alto Research Center,\n * and Lawrence Berkeley National Lab.\n * October 15, 2003\n *\n * Copyright (c) 1994 by Xerox Corporation.  All rights reserved.\n *\n * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY\n * EXPRESSED OR IMPLIED.  ANY USE IS AT YOUR OWN RISK.\n *\n * Permission is hereby granted to use or copy this program for any\n * purpose, provided the above notices are retained on all copies.\n * Permission to modify the code and to distribute modified code is\n * granted, provided the above notices are retained, and a notice that\n * the code was modified is included with the above copyright notice.\n */\n#ifndef SPARSELU_COLUMN_BMOD_H\n#define SPARSELU_COLUMN_BMOD_H\n\nnamespace Eigen {\n\nnamespace internal {\n/**\n * \\brief Performs numeric block updates (sup-col) in topological order\n * \n * \\param jcol current column to update\n * \\param nseg Number of segments in the U part\n * \\param dense Store the full representation of the column\n * \\param tempv working array \n * \\param segrep segment representative ...\n * \\param repfnz ??? First nonzero column in each row ???  ...\n * \\param fpanelc First column in the current panel\n * \\param glu Global LU data. \n * \\return 0 - successful return \n *         > 0 - number of bytes allocated when run out of space\n * \n */\ntemplate <typename Scalar, typename StorageIndex>\nIndex SparseLUImpl<Scalar,StorageIndex>::column_bmod(const Index jcol, const Index nseg, BlockScalarVector dense, ScalarVector& tempv,\n                                                     BlockIndexVector segrep, BlockIndexVector repfnz, Index fpanelc, GlobalLU_t& glu)\n{\n  Index  jsupno, k, ksub, krep, ksupno; \n  Index lptr, nrow, isub, irow, nextlu, new_next, ufirst; \n  Index fsupc, nsupc, nsupr, luptr, kfnz, no_zeros; \n  /* krep = representative of current k-th supernode\n    * fsupc =  first supernodal column\n    * nsupc = number of columns in a supernode\n    * nsupr = number of rows in a supernode\n    * luptr = location of supernodal LU-block in storage\n    * kfnz = first nonz in the k-th supernodal segment\n    * no_zeros = no lf leading zeros in a supernodal U-segment\n    */\n  \n  jsupno = glu.supno(jcol);\n  // For each nonzero supernode segment of U[*,j] in topological order \n  k = nseg - 1; \n  Index d_fsupc; // distance between the first column of the current panel and the \n               // first column of the current snode\n  Index fst_col; // First column within small LU update\n  Index segsize; \n  for (ksub = 0; ksub < nseg; ksub++)\n  {\n    krep = segrep(k); k--; \n    ksupno = glu.supno(krep); \n    if (jsupno != ksupno )\n    {\n      // outside the rectangular supernode \n      fsupc = glu.xsup(ksupno); \n      fst_col = (std::max)(fsupc, fpanelc); \n      \n      // Distance from the current supernode to the current panel; \n      // d_fsupc = 0 if fsupc > fpanelc\n      d_fsupc = fst_col - fsupc; \n      \n      luptr = glu.xlusup(fst_col) + d_fsupc; \n      lptr = glu.xlsub(fsupc) + d_fsupc; \n      \n      kfnz = repfnz(krep); \n      kfnz = (std::max)(kfnz, fpanelc); \n      \n      segsize = krep - kfnz + 1; \n      nsupc = krep - fst_col + 1; \n      nsupr = glu.xlsub(fsupc+1) - glu.xlsub(fsupc); \n      nrow = nsupr - d_fsupc - nsupc;\n      Index lda = glu.xlusup(fst_col+1) - glu.xlusup(fst_col);\n      \n      \n      // Perform a triangular solver and block update, \n      // then scatter the result of sup-col update to dense\n      no_zeros = kfnz - fst_col; \n      if(segsize==1)\n        LU_kernel_bmod<1>::run(segsize, dense, tempv, glu.lusup, luptr, lda, nrow, glu.lsub, lptr, no_zeros);\n      else\n        LU_kernel_bmod<Dynamic>::run(segsize, dense, tempv, glu.lusup, luptr, lda, nrow, glu.lsub, lptr, no_zeros);\n    } // end if jsupno \n  } // end for each segment\n  \n  // Process the supernodal portion of  L\\U[*,j]\n  nextlu = glu.xlusup(jcol); \n  fsupc = glu.xsup(jsupno);\n  \n  // copy the SPA dense into L\\U[*,j]\n  Index mem; \n  new_next = nextlu + glu.xlsub(fsupc + 1) - glu.xlsub(fsupc); \n  Index offset = internal::first_multiple<Index>(new_next, internal::packet_traits<Scalar>::size) - new_next;\n  if(offset)\n    new_next += offset;\n  while (new_next > glu.nzlumax )\n  {\n    mem = memXpand<ScalarVector>(glu.lusup, glu.nzlumax, nextlu, LUSUP, glu.num_expansions);  \n    if (mem) return mem; \n  }\n  \n  for (isub = glu.xlsub(fsupc); isub < glu.xlsub(fsupc+1); isub++)\n  {\n    irow = glu.lsub(isub);\n    glu.lusup(nextlu) = dense(irow);\n    dense(irow) = Scalar(0.0); \n    ++nextlu; \n  }\n  \n  if(offset)\n  {\n    glu.lusup.segment(nextlu,offset).setZero();\n    nextlu += offset;\n  }\n  glu.xlusup(jcol + 1) = StorageIndex(nextlu);  // close L\\U(*,jcol); \n  \n  /* For more updates within the panel (also within the current supernode),\n   * should start from the first column of the panel, or the first column\n   * of the supernode, whichever is bigger. There are two cases:\n   *  1) fsupc < fpanelc, then fst_col <-- fpanelc\n   *  2) fsupc >= fpanelc, then fst_col <-- fsupc\n   */\n  fst_col = (std::max)(fsupc, fpanelc); \n  \n  if (fst_col  < jcol)\n  {\n    // Distance between the current supernode and the current panel\n    // d_fsupc = 0 if fsupc >= fpanelc\n    d_fsupc = fst_col - fsupc; \n    \n    lptr = glu.xlsub(fsupc) + d_fsupc; \n    luptr = glu.xlusup(fst_col) + d_fsupc; \n    nsupr = glu.xlsub(fsupc+1) - glu.xlsub(fsupc); // leading dimension\n    nsupc = jcol - fst_col; // excluding jcol \n    nrow = nsupr - d_fsupc - nsupc; \n    \n    // points to the beginning of jcol in snode L\\U(jsupno) \n    ufirst = glu.xlusup(jcol) + d_fsupc; \n    Index lda = glu.xlusup(jcol+1) - glu.xlusup(jcol);\n    MappedMatrixBlock A( &(glu.lusup.data()[luptr]), nsupc, nsupc, OuterStride<>(lda) );\n    VectorBlock<ScalarVector> u(glu.lusup, ufirst, nsupc); \n    u = A.template triangularView<UnitLower>().solve(u); \n    \n    new (&A) MappedMatrixBlock ( &(glu.lusup.data()[luptr+nsupc]), nrow, nsupc, OuterStride<>(lda) );\n    VectorBlock<ScalarVector> l(glu.lusup, ufirst+nsupc, nrow); \n    l.noalias() -= A * u;\n    \n  } // End if fst_col\n  return 0; \n}\n\n} // end namespace internal\n} // end namespace Eigen\n\n#endif // SPARSELU_COLUMN_BMOD_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseLU/SparseLU_column_dfs.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2012 Désiré Nuentsa-Wakam <desire.nuentsa_wakam@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n/* \n \n * NOTE: This file is the modified version of [s,d,c,z]column_dfs.c file in SuperLU \n \n * -- SuperLU routine (version 2.0) --\n * Univ. of California Berkeley, Xerox Palo Alto Research Center,\n * and Lawrence Berkeley National Lab.\n * November 15, 1997\n *\n * Copyright (c) 1994 by Xerox Corporation.  All rights reserved.\n *\n * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY\n * EXPRESSED OR IMPLIED.  ANY USE IS AT YOUR OWN RISK.\n *\n * Permission is hereby granted to use or copy this program for any\n * purpose, provided the above notices are retained on all copies.\n * Permission to modify the code and to distribute modified code is\n * granted, provided the above notices are retained, and a notice that\n * the code was modified is included with the above copyright notice.\n */\n#ifndef SPARSELU_COLUMN_DFS_H\n#define SPARSELU_COLUMN_DFS_H\n\ntemplate <typename Scalar, typename StorageIndex> class SparseLUImpl;\nnamespace Eigen {\n\nnamespace internal {\n\ntemplate<typename IndexVector, typename ScalarVector>\nstruct column_dfs_traits : no_assignment_operator\n{\n  typedef typename ScalarVector::Scalar Scalar;\n  typedef typename IndexVector::Scalar StorageIndex;\n  column_dfs_traits(Index jcol, Index& jsuper, typename SparseLUImpl<Scalar, StorageIndex>::GlobalLU_t& glu, SparseLUImpl<Scalar, StorageIndex>& luImpl)\n   : m_jcol(jcol), m_jsuper_ref(jsuper), m_glu(glu), m_luImpl(luImpl)\n {}\n  bool update_segrep(Index /*krep*/, Index /*jj*/)\n  {\n    return true;\n  }\n  void mem_expand(IndexVector& lsub, Index& nextl, Index chmark)\n  {\n    if (nextl >= m_glu.nzlmax)\n      m_luImpl.memXpand(lsub, m_glu.nzlmax, nextl, LSUB, m_glu.num_expansions); \n    if (chmark != (m_jcol-1)) m_jsuper_ref = emptyIdxLU;\n  }\n  enum { ExpandMem = true };\n  \n  Index m_jcol;\n  Index& m_jsuper_ref;\n  typename SparseLUImpl<Scalar, StorageIndex>::GlobalLU_t& m_glu;\n  SparseLUImpl<Scalar, StorageIndex>& m_luImpl;\n};\n\n\n/**\n * \\brief Performs a symbolic factorization on column jcol and decide the supernode boundary\n * \n * A supernode representative is the last column of a supernode.\n * The nonzeros in U[*,j] are segments that end at supernodes representatives. \n * The routine returns a list of the supernodal representatives \n * in topological order of the dfs that generates them. \n * The location of the first nonzero in each supernodal segment \n * (supernodal entry location) is also returned. \n * \n * \\param m number of rows in the matrix\n * \\param jcol Current column \n * \\param perm_r Row permutation\n * \\param maxsuper  Maximum number of column allowed in a supernode\n * \\param [in,out] nseg Number of segments in current U[*,j] - new segments appended\n * \\param lsub_col defines the rhs vector to start the dfs\n * \\param [in,out] segrep Segment representatives - new segments appended \n * \\param repfnz  First nonzero location in each row\n * \\param xprune \n * \\param marker  marker[i] == jj, if i was visited during dfs of current column jj;\n * \\param parent\n * \\param xplore working array\n * \\param glu global LU data \n * \\return 0 success\n *         > 0 number of bytes allocated when run out of space\n * \n */\ntemplate <typename Scalar, typename StorageIndex>\nIndex SparseLUImpl<Scalar,StorageIndex>::column_dfs(const Index m, const Index jcol, IndexVector& perm_r, Index maxsuper, Index& nseg,\n                                                    BlockIndexVector lsub_col, IndexVector& segrep, BlockIndexVector repfnz, IndexVector& xprune,\n                                                    IndexVector& marker, IndexVector& parent, IndexVector& xplore, GlobalLU_t& glu)\n{\n  \n  Index jsuper = glu.supno(jcol); \n  Index nextl = glu.xlsub(jcol); \n  VectorBlock<IndexVector> marker2(marker, 2*m, m); \n  \n  \n  column_dfs_traits<IndexVector, ScalarVector> traits(jcol, jsuper, glu, *this);\n  \n  // For each nonzero in A(*,jcol) do dfs \n  for (Index k = 0; ((k < m) ? lsub_col[k] != emptyIdxLU : false) ; k++)\n  {\n    Index krow = lsub_col(k); \n    lsub_col(k) = emptyIdxLU; \n    Index kmark = marker2(krow); \n    \n    // krow was visited before, go to the next nonz; \n    if (kmark == jcol) continue;\n    \n    dfs_kernel(StorageIndex(jcol), perm_r, nseg, glu.lsub, segrep, repfnz, xprune, marker2, parent,\n                   xplore, glu, nextl, krow, traits);\n  } // for each nonzero ... \n  \n  Index fsupc;\n  StorageIndex nsuper = glu.supno(jcol);\n  StorageIndex jcolp1 = StorageIndex(jcol) + 1;\n  Index jcolm1 = jcol - 1;\n  \n  // check to see if j belongs in the same supernode as j-1\n  if ( jcol == 0 )\n  { // Do nothing for column 0 \n    nsuper = glu.supno(0) = 0 ;\n  }\n  else \n  {\n    fsupc = glu.xsup(nsuper); \n    StorageIndex jptr = glu.xlsub(jcol); // Not yet compressed\n    StorageIndex jm1ptr = glu.xlsub(jcolm1); \n    \n    // Use supernodes of type T2 : see SuperLU paper\n    if ( (nextl-jptr != jptr-jm1ptr-1) ) jsuper = emptyIdxLU;\n    \n    // Make sure the number of columns in a supernode doesn't\n    // exceed threshold\n    if ( (jcol - fsupc) >= maxsuper) jsuper = emptyIdxLU; \n    \n    /* If jcol starts a new supernode, reclaim storage space in\n     * glu.lsub from previous supernode. Note we only store \n     * the subscript set of the first and last columns of \n     * a supernode. (first for num values, last for pruning)\n     */\n    if (jsuper == emptyIdxLU)\n    { // starts a new supernode \n      if ( (fsupc < jcolm1-1) ) \n      { // >= 3 columns in nsuper\n        StorageIndex ito = glu.xlsub(fsupc+1);\n        glu.xlsub(jcolm1) = ito; \n        StorageIndex istop = ito + jptr - jm1ptr; \n        xprune(jcolm1) = istop; // intialize xprune(jcol-1)\n        glu.xlsub(jcol) = istop; \n        \n        for (StorageIndex ifrom = jm1ptr; ifrom < nextl; ++ifrom, ++ito)\n          glu.lsub(ito) = glu.lsub(ifrom); \n        nextl = ito;  // = istop + length(jcol)\n      }\n      nsuper++; \n      glu.supno(jcol) = nsuper; \n    } // if a new supernode \n  } // end else:  jcol > 0\n  \n  // Tidy up the pointers before exit\n  glu.xsup(nsuper+1) = jcolp1; \n  glu.supno(jcolp1) = nsuper; \n  xprune(jcol) = StorageIndex(nextl);  // Intialize upper bound for pruning\n  glu.xlsub(jcolp1) = StorageIndex(nextl); \n  \n  return 0; \n}\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseLU/SparseLU_copy_to_ucol.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2012 Désiré Nuentsa-Wakam <desire.nuentsa_wakam@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n/* \n \n * NOTE: This file is the modified version of [s,d,c,z]copy_to_ucol.c file in SuperLU \n \n * -- SuperLU routine (version 2.0) --\n * Univ. of California Berkeley, Xerox Palo Alto Research Center,\n * and Lawrence Berkeley National Lab.\n * November 15, 1997\n *\n * Copyright (c) 1994 by Xerox Corporation.  All rights reserved.\n *\n * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY\n * EXPRESSED OR IMPLIED.  ANY USE IS AT YOUR OWN RISK.\n *\n * Permission is hereby granted to use or copy this program for any\n * purpose, provided the above notices are retained on all copies.\n * Permission to modify the code and to distribute modified code is\n * granted, provided the above notices are retained, and a notice that\n * the code was modified is included with the above copyright notice.\n */\n#ifndef SPARSELU_COPY_TO_UCOL_H\n#define SPARSELU_COPY_TO_UCOL_H\n\nnamespace Eigen {\nnamespace internal {\n\n/**\n * \\brief Performs numeric block updates (sup-col) in topological order\n * \n * \\param jcol current column to update\n * \\param nseg Number of segments in the U part\n * \\param segrep segment representative ...\n * \\param repfnz First nonzero column in each row  ...\n * \\param perm_r Row permutation \n * \\param dense Store the full representation of the column\n * \\param glu Global LU data. \n * \\return 0 - successful return \n *         > 0 - number of bytes allocated when run out of space\n * \n */\ntemplate <typename Scalar, typename StorageIndex>\nIndex SparseLUImpl<Scalar,StorageIndex>::copy_to_ucol(const Index jcol, const Index nseg, IndexVector& segrep,\n                                                      BlockIndexVector repfnz ,IndexVector& perm_r, BlockScalarVector dense, GlobalLU_t& glu)\n{  \n  Index ksub, krep, ksupno; \n    \n  Index jsupno = glu.supno(jcol);\n  \n  // For each nonzero supernode segment of U[*,j] in topological order \n  Index k = nseg - 1, i; \n  StorageIndex nextu = glu.xusub(jcol); \n  Index kfnz, isub, segsize; \n  Index new_next,irow; \n  Index fsupc, mem; \n  for (ksub = 0; ksub < nseg; ksub++)\n  {\n    krep = segrep(k); k--; \n    ksupno = glu.supno(krep); \n    if (jsupno != ksupno ) // should go into ucol(); \n    {\n      kfnz = repfnz(krep); \n      if (kfnz != emptyIdxLU)\n      { // Nonzero U-segment \n        fsupc = glu.xsup(ksupno); \n        isub = glu.xlsub(fsupc) + kfnz - fsupc; \n        segsize = krep - kfnz + 1; \n        new_next = nextu + segsize; \n        while (new_next > glu.nzumax) \n        {\n          mem = memXpand<ScalarVector>(glu.ucol, glu.nzumax, nextu, UCOL, glu.num_expansions); \n          if (mem) return mem; \n          mem = memXpand<IndexVector>(glu.usub, glu.nzumax, nextu, USUB, glu.num_expansions); \n          if (mem) return mem; \n          \n        }\n        \n        for (i = 0; i < segsize; i++)\n        {\n          irow = glu.lsub(isub); \n          glu.usub(nextu) = perm_r(irow); // Unlike the L part, the U part is stored in its final order\n          glu.ucol(nextu) = dense(irow); \n          dense(irow) = Scalar(0.0); \n          nextu++;\n          isub++;\n        }\n        \n      } // end nonzero U-segment \n      \n    } // end if jsupno \n    \n  } // end for each segment\n  glu.xusub(jcol + 1) = nextu; // close U(*,jcol)\n  return 0; \n}\n\n} // namespace internal\n} // end namespace Eigen\n\n#endif // SPARSELU_COPY_TO_UCOL_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseLU/SparseLU_gemm_kernel.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2012 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SPARSELU_GEMM_KERNEL_H\n#define EIGEN_SPARSELU_GEMM_KERNEL_H\n\nnamespace Eigen {\n\nnamespace internal {\n\n\n/** \\internal\n  * A general matrix-matrix product kernel optimized for the SparseLU factorization.\n  *  - A, B, and C must be column major\n  *  - lda and ldc must be multiples of the respective packet size\n  *  - C must have the same alignment as A\n  */\ntemplate<typename Scalar>\nEIGEN_DONT_INLINE\nvoid sparselu_gemm(Index m, Index n, Index d, const Scalar* A, Index lda, const Scalar* B, Index ldb, Scalar* C, Index ldc)\n{\n  using namespace Eigen::internal;\n  \n  typedef typename packet_traits<Scalar>::type Packet;\n  enum {\n    NumberOfRegisters = EIGEN_ARCH_DEFAULT_NUMBER_OF_REGISTERS,\n    PacketSize = packet_traits<Scalar>::size,\n    PM = 8,                             // peeling in M\n    RN = 2,                             // register blocking\n    RK = NumberOfRegisters>=16 ? 4 : 2, // register blocking\n    BM = 4096/sizeof(Scalar),           // number of rows of A-C per chunk\n    SM = PM*PacketSize                  // step along M\n  };\n  Index d_end = (d/RK)*RK;    // number of columns of A (rows of B) suitable for full register blocking\n  Index n_end = (n/RN)*RN;    // number of columns of B-C suitable for processing RN columns at once\n  Index i0 = internal::first_default_aligned(A,m);\n  \n  eigen_internal_assert(((lda%PacketSize)==0) && ((ldc%PacketSize)==0) && (i0==internal::first_default_aligned(C,m)));\n  \n  // handle the non aligned rows of A and C without any optimization:\n  for(Index i=0; i<i0; ++i)\n  {\n    for(Index j=0; j<n; ++j)\n    {\n      Scalar c = C[i+j*ldc];\n      for(Index k=0; k<d; ++k)\n        c += B[k+j*ldb] * A[i+k*lda];\n      C[i+j*ldc] = c;\n    }\n  }\n  // process the remaining rows per chunk of BM rows\n  for(Index ib=i0; ib<m; ib+=BM)\n  {\n    Index actual_b = std::min<Index>(BM, m-ib);                 // actual number of rows\n    Index actual_b_end1 = (actual_b/SM)*SM;                   // actual number of rows suitable for peeling\n    Index actual_b_end2 = (actual_b/PacketSize)*PacketSize;   // actual number of rows suitable for vectorization\n    \n    // Let's process two columns of B-C at once\n    for(Index j=0; j<n_end; j+=RN)\n    {\n      const Scalar* Bc0 = B+(j+0)*ldb;\n      const Scalar* Bc1 = B+(j+1)*ldb;\n      \n      for(Index k=0; k<d_end; k+=RK)\n      {\n        \n        // load and expand a RN x RK block of B\n        Packet b00, b10, b20, b30, b01, b11, b21, b31;\n                  { b00 = pset1<Packet>(Bc0[0]); }\n                  { b10 = pset1<Packet>(Bc0[1]); }\n        if(RK==4) { b20 = pset1<Packet>(Bc0[2]); }\n        if(RK==4) { b30 = pset1<Packet>(Bc0[3]); }\n                  { b01 = pset1<Packet>(Bc1[0]); }\n                  { b11 = pset1<Packet>(Bc1[1]); }\n        if(RK==4) { b21 = pset1<Packet>(Bc1[2]); }\n        if(RK==4) { b31 = pset1<Packet>(Bc1[3]); }\n        \n        Packet a0, a1, a2, a3, c0, c1, t0, t1;\n        \n        const Scalar* A0 = A+ib+(k+0)*lda;\n        const Scalar* A1 = A+ib+(k+1)*lda;\n        const Scalar* A2 = A+ib+(k+2)*lda;\n        const Scalar* A3 = A+ib+(k+3)*lda;\n        \n        Scalar* C0 = C+ib+(j+0)*ldc;\n        Scalar* C1 = C+ib+(j+1)*ldc;\n        \n                  a0 = pload<Packet>(A0);\n                  a1 = pload<Packet>(A1);\n        if(RK==4)\n        {\n          a2 = pload<Packet>(A2);\n          a3 = pload<Packet>(A3);\n        }\n        else\n        {\n          // workaround \"may be used uninitialized in this function\" warning\n          a2 = a3 = a0;\n        }\n        \n#define KMADD(c, a, b, tmp) {tmp = b; tmp = pmul(a,tmp); c = padd(c,tmp);}\n#define WORK(I)  \\\n                     c0 = pload<Packet>(C0+i+(I)*PacketSize);    \\\n                     c1 = pload<Packet>(C1+i+(I)*PacketSize);    \\\n                     KMADD(c0, a0, b00, t0)                      \\\n                     KMADD(c1, a0, b01, t1)                      \\\n                     a0 = pload<Packet>(A0+i+(I+1)*PacketSize);  \\\n                     KMADD(c0, a1, b10, t0)                      \\\n                     KMADD(c1, a1, b11, t1)                      \\\n                     a1 = pload<Packet>(A1+i+(I+1)*PacketSize);  \\\n          if(RK==4){ KMADD(c0, a2, b20, t0)                     }\\\n          if(RK==4){ KMADD(c1, a2, b21, t1)                     }\\\n          if(RK==4){ a2 = pload<Packet>(A2+i+(I+1)*PacketSize); }\\\n          if(RK==4){ KMADD(c0, a3, b30, t0)                     }\\\n          if(RK==4){ KMADD(c1, a3, b31, t1)                     }\\\n          if(RK==4){ a3 = pload<Packet>(A3+i+(I+1)*PacketSize); }\\\n                     pstore(C0+i+(I)*PacketSize, c0);            \\\n                     pstore(C1+i+(I)*PacketSize, c1)\n        \n        // process rows of A' - C' with aggressive vectorization and peeling \n        for(Index i=0; i<actual_b_end1; i+=PacketSize*8)\n        {\n          EIGEN_ASM_COMMENT(\"SPARSELU_GEMML_KERNEL1\");\n                    prefetch((A0+i+(5)*PacketSize));\n                    prefetch((A1+i+(5)*PacketSize));\n          if(RK==4) prefetch((A2+i+(5)*PacketSize));\n          if(RK==4) prefetch((A3+i+(5)*PacketSize));\n\n          WORK(0);\n          WORK(1);\n          WORK(2);\n          WORK(3);\n          WORK(4);\n          WORK(5);\n          WORK(6);\n          WORK(7);\n        }\n        // process the remaining rows with vectorization only\n        for(Index i=actual_b_end1; i<actual_b_end2; i+=PacketSize)\n        {\n          WORK(0);\n        }\n#undef WORK\n        // process the remaining rows without vectorization\n        for(Index i=actual_b_end2; i<actual_b; ++i)\n        {\n          if(RK==4)\n          {\n            C0[i] += A0[i]*Bc0[0]+A1[i]*Bc0[1]+A2[i]*Bc0[2]+A3[i]*Bc0[3];\n            C1[i] += A0[i]*Bc1[0]+A1[i]*Bc1[1]+A2[i]*Bc1[2]+A3[i]*Bc1[3];\n          }\n          else\n          {\n            C0[i] += A0[i]*Bc0[0]+A1[i]*Bc0[1];\n            C1[i] += A0[i]*Bc1[0]+A1[i]*Bc1[1];\n          }\n        }\n        \n        Bc0 += RK;\n        Bc1 += RK;\n      } // peeled loop on k\n    } // peeled loop on the columns j\n    // process the last column (we now perform a matrix-vector product)\n    if((n-n_end)>0)\n    {\n      const Scalar* Bc0 = B+(n-1)*ldb;\n      \n      for(Index k=0; k<d_end; k+=RK)\n      {\n        \n        // load and expand a 1 x RK block of B\n        Packet b00, b10, b20, b30;\n                  b00 = pset1<Packet>(Bc0[0]);\n                  b10 = pset1<Packet>(Bc0[1]);\n        if(RK==4) b20 = pset1<Packet>(Bc0[2]);\n        if(RK==4) b30 = pset1<Packet>(Bc0[3]);\n        \n        Packet a0, a1, a2, a3, c0, t0/*, t1*/;\n        \n        const Scalar* A0 = A+ib+(k+0)*lda;\n        const Scalar* A1 = A+ib+(k+1)*lda;\n        const Scalar* A2 = A+ib+(k+2)*lda;\n        const Scalar* A3 = A+ib+(k+3)*lda;\n        \n        Scalar* C0 = C+ib+(n_end)*ldc;\n        \n                  a0 = pload<Packet>(A0);\n                  a1 = pload<Packet>(A1);\n        if(RK==4)\n        {\n          a2 = pload<Packet>(A2);\n          a3 = pload<Packet>(A3);\n        }\n        else\n        {\n          // workaround \"may be used uninitialized in this function\" warning\n          a2 = a3 = a0;\n        }\n        \n#define WORK(I) \\\n                   c0 = pload<Packet>(C0+i+(I)*PacketSize);     \\\n                   KMADD(c0, a0, b00, t0)                       \\\n                   a0 = pload<Packet>(A0+i+(I+1)*PacketSize);   \\\n                   KMADD(c0, a1, b10, t0)                       \\\n                   a1 = pload<Packet>(A1+i+(I+1)*PacketSize);   \\\n        if(RK==4){ KMADD(c0, a2, b20, t0)                      }\\\n        if(RK==4){ a2 = pload<Packet>(A2+i+(I+1)*PacketSize);  }\\\n        if(RK==4){ KMADD(c0, a3, b30, t0)                      }\\\n        if(RK==4){ a3 = pload<Packet>(A3+i+(I+1)*PacketSize);  }\\\n                   pstore(C0+i+(I)*PacketSize, c0);\n        \n        // agressive vectorization and peeling\n        for(Index i=0; i<actual_b_end1; i+=PacketSize*8)\n        {\n          EIGEN_ASM_COMMENT(\"SPARSELU_GEMML_KERNEL2\");\n          WORK(0);\n          WORK(1);\n          WORK(2);\n          WORK(3);\n          WORK(4);\n          WORK(5);\n          WORK(6);\n          WORK(7);\n        }\n        // vectorization only\n        for(Index i=actual_b_end1; i<actual_b_end2; i+=PacketSize)\n        {\n          WORK(0);\n        }\n        // remaining scalars\n        for(Index i=actual_b_end2; i<actual_b; ++i)\n        {\n          if(RK==4) \n            C0[i] += A0[i]*Bc0[0]+A1[i]*Bc0[1]+A2[i]*Bc0[2]+A3[i]*Bc0[3];\n          else\n            C0[i] += A0[i]*Bc0[0]+A1[i]*Bc0[1];\n        }\n        \n        Bc0 += RK;\n#undef WORK\n      }\n    }\n    \n    // process the last columns of A, corresponding to the last rows of B\n    Index rd = d-d_end;\n    if(rd>0)\n    {\n      for(Index j=0; j<n; ++j)\n      {\n        enum {\n          Alignment = PacketSize>1 ? Aligned : 0\n        };\n        typedef Map<Matrix<Scalar,Dynamic,1>, Alignment > MapVector;\n        typedef Map<const Matrix<Scalar,Dynamic,1>, Alignment > ConstMapVector;\n        if(rd==1)       MapVector(C+j*ldc+ib,actual_b) += B[0+d_end+j*ldb] * ConstMapVector(A+(d_end+0)*lda+ib, actual_b);\n        \n        else if(rd==2)  MapVector(C+j*ldc+ib,actual_b) += B[0+d_end+j*ldb] * ConstMapVector(A+(d_end+0)*lda+ib, actual_b)\n                                                        + B[1+d_end+j*ldb] * ConstMapVector(A+(d_end+1)*lda+ib, actual_b);\n        \n        else            MapVector(C+j*ldc+ib,actual_b) += B[0+d_end+j*ldb] * ConstMapVector(A+(d_end+0)*lda+ib, actual_b)\n                                                        + B[1+d_end+j*ldb] * ConstMapVector(A+(d_end+1)*lda+ib, actual_b)\n                                                        + B[2+d_end+j*ldb] * ConstMapVector(A+(d_end+2)*lda+ib, actual_b);\n      }\n    }\n  \n  } // blocking on the rows of A and C\n}\n#undef KMADD\n\n} // namespace internal\n\n} // namespace Eigen\n\n#endif // EIGEN_SPARSELU_GEMM_KERNEL_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseLU/SparseLU_heap_relax_snode.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2012 Désiré Nuentsa-Wakam <desire.nuentsa_wakam@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n/* This file is a modified version of heap_relax_snode.c file in SuperLU\n * -- SuperLU routine (version 3.0) --\n * Univ. of California Berkeley, Xerox Palo Alto Research Center,\n * and Lawrence Berkeley National Lab.\n * October 15, 2003\n *\n * Copyright (c) 1994 by Xerox Corporation.  All rights reserved.\n *\n * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY\n * EXPRESSED OR IMPLIED.  ANY USE IS AT YOUR OWN RISK.\n *\n * Permission is hereby granted to use or copy this program for any\n * purpose, provided the above notices are retained on all copies.\n * Permission to modify the code and to distribute modified code is\n * granted, provided the above notices are retained, and a notice that\n * the code was modified is included with the above copyright notice.\n */\n\n#ifndef SPARSELU_HEAP_RELAX_SNODE_H\n#define SPARSELU_HEAP_RELAX_SNODE_H\n\nnamespace Eigen {\nnamespace internal {\n\n/** \n * \\brief Identify the initial relaxed supernodes\n * \n * This routine applied to a symmetric elimination tree. \n * It assumes that the matrix has been reordered according to the postorder of the etree\n * \\param n The number of columns\n * \\param et elimination tree \n * \\param relax_columns Maximum number of columns allowed in a relaxed snode \n * \\param descendants Number of descendants of each node in the etree\n * \\param relax_end last column in a supernode\n */\ntemplate <typename Scalar, typename StorageIndex>\nvoid SparseLUImpl<Scalar,StorageIndex>::heap_relax_snode (const Index n, IndexVector& et, const Index relax_columns, IndexVector& descendants, IndexVector& relax_end)\n{\n  \n  // The etree may not be postordered, but its heap ordered  \n  IndexVector post;\n  internal::treePostorder(StorageIndex(n), et, post); // Post order etree\n  IndexVector inv_post(n+1); \n  for (StorageIndex i = 0; i < n+1; ++i) inv_post(post(i)) = i; // inv_post = post.inverse()???\n  \n  // Renumber etree in postorder \n  IndexVector iwork(n);\n  IndexVector et_save(n+1);\n  for (Index i = 0; i < n; ++i)\n  {\n    iwork(post(i)) = post(et(i));\n  }\n  et_save = et; // Save the original etree\n  et = iwork; \n  \n  // compute the number of descendants of each node in the etree\n  relax_end.setConstant(emptyIdxLU);\n  Index j, parent; \n  descendants.setZero();\n  for (j = 0; j < n; j++) \n  {\n    parent = et(j);\n    if (parent != n) // not the dummy root\n      descendants(parent) += descendants(j) + 1;\n  }\n  // Identify the relaxed supernodes by postorder traversal of the etree\n  Index snode_start; // beginning of a snode \n  StorageIndex k;\n  Index nsuper_et_post = 0; // Number of relaxed snodes in postordered etree \n  Index nsuper_et = 0; // Number of relaxed snodes in the original etree \n  StorageIndex l; \n  for (j = 0; j < n; )\n  {\n    parent = et(j);\n    snode_start = j; \n    while ( parent != n && descendants(parent) < relax_columns ) \n    {\n      j = parent; \n      parent = et(j);\n    }\n    // Found a supernode in postordered etree, j is the last column \n    ++nsuper_et_post;\n    k = StorageIndex(n);\n    for (Index i = snode_start; i <= j; ++i)\n      k = (std::min)(k, inv_post(i));\n    l = inv_post(j);\n    if ( (l - k) == (j - snode_start) )  // Same number of columns in the snode\n    {\n      // This is also a supernode in the original etree\n      relax_end(k) = l; // Record last column \n      ++nsuper_et; \n    }\n    else \n    {\n      for (Index i = snode_start; i <= j; ++i) \n      {\n        l = inv_post(i);\n        if (descendants(i) == 0) \n        {\n          relax_end(l) = l;\n          ++nsuper_et;\n        }\n      }\n    }\n    j++;\n    // Search for a new leaf\n    while (descendants(j) != 0 && j < n) j++;\n  } // End postorder traversal of the etree\n  \n  // Recover the original etree\n  et = et_save; \n}\n\n} // end namespace internal\n\n} // end namespace Eigen\n#endif // SPARSELU_HEAP_RELAX_SNODE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseLU/SparseLU_kernel_bmod.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2012 Désiré Nuentsa-Wakam <desire.nuentsa_wakam@inria.fr>\n// Copyright (C) 2012 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef SPARSELU_KERNEL_BMOD_H\n#define SPARSELU_KERNEL_BMOD_H\n\nnamespace Eigen {\nnamespace internal {\n  \ntemplate <int SegSizeAtCompileTime> struct LU_kernel_bmod\n{\n  /** \\internal\n    * \\brief Performs numeric block updates from a given supernode to a single column\n    *\n    * \\param segsize Size of the segment (and blocks ) to use for updates\n    * \\param[in,out] dense Packed values of the original matrix\n    * \\param tempv temporary vector to use for updates\n    * \\param lusup array containing the supernodes\n    * \\param lda Leading dimension in the supernode\n    * \\param nrow Number of rows in the rectangular part of the supernode\n    * \\param lsub compressed row subscripts of supernodes\n    * \\param lptr pointer to the first column of the current supernode in lsub\n    * \\param no_zeros Number of nonzeros elements before the diagonal part of the supernode\n    */\n  template <typename BlockScalarVector, typename ScalarVector, typename IndexVector>\n  static EIGEN_DONT_INLINE void run(const Index segsize, BlockScalarVector& dense, ScalarVector& tempv, ScalarVector& lusup, Index& luptr, const Index lda,\n                                    const Index nrow, IndexVector& lsub, const Index lptr, const Index no_zeros);\n};\n\ntemplate <int SegSizeAtCompileTime>\ntemplate <typename BlockScalarVector, typename ScalarVector, typename IndexVector>\nEIGEN_DONT_INLINE void LU_kernel_bmod<SegSizeAtCompileTime>::run(const Index segsize, BlockScalarVector& dense, ScalarVector& tempv, ScalarVector& lusup, Index& luptr, const Index lda,\n                                                                  const Index nrow, IndexVector& lsub, const Index lptr, const Index no_zeros)\n{\n  typedef typename ScalarVector::Scalar Scalar;\n  // First, copy U[*,j] segment from dense(*) to tempv(*)\n  // The result of triangular solve is in tempv[*]; \n    // The result of matric-vector update is in dense[*]\n  Index isub = lptr + no_zeros; \n  Index i;\n  Index irow;\n  for (i = 0; i < ((SegSizeAtCompileTime==Dynamic)?segsize:SegSizeAtCompileTime); i++)\n  {\n    irow = lsub(isub); \n    tempv(i) = dense(irow); \n    ++isub; \n  }\n  // Dense triangular solve -- start effective triangle\n  luptr += lda * no_zeros + no_zeros; \n  // Form Eigen matrix and vector \n  Map<Matrix<Scalar,SegSizeAtCompileTime,SegSizeAtCompileTime, ColMajor>, 0, OuterStride<> > A( &(lusup.data()[luptr]), segsize, segsize, OuterStride<>(lda) );\n  Map<Matrix<Scalar,SegSizeAtCompileTime,1> > u(tempv.data(), segsize);\n  \n  u = A.template triangularView<UnitLower>().solve(u); \n  \n  // Dense matrix-vector product y <-- B*x \n  luptr += segsize;\n  const Index PacketSize = internal::packet_traits<Scalar>::size;\n  Index ldl = internal::first_multiple(nrow, PacketSize);\n  Map<Matrix<Scalar,Dynamic,SegSizeAtCompileTime, ColMajor>, 0, OuterStride<> > B( &(lusup.data()[luptr]), nrow, segsize, OuterStride<>(lda) );\n  Index aligned_offset = internal::first_default_aligned(tempv.data()+segsize, PacketSize);\n  Index aligned_with_B_offset = (PacketSize-internal::first_default_aligned(B.data(), PacketSize))%PacketSize;\n  Map<Matrix<Scalar,Dynamic,1>, 0, OuterStride<> > l(tempv.data()+segsize+aligned_offset+aligned_with_B_offset, nrow, OuterStride<>(ldl) );\n  \n  l.setZero();\n  internal::sparselu_gemm<Scalar>(l.rows(), l.cols(), B.cols(), B.data(), B.outerStride(), u.data(), u.outerStride(), l.data(), l.outerStride());\n  \n  // Scatter tempv[] into SPA dense[] as a temporary storage \n  isub = lptr + no_zeros;\n  for (i = 0; i < ((SegSizeAtCompileTime==Dynamic)?segsize:SegSizeAtCompileTime); i++)\n  {\n    irow = lsub(isub++); \n    dense(irow) = tempv(i);\n  }\n  \n  // Scatter l into SPA dense[]\n  for (i = 0; i < nrow; i++)\n  {\n    irow = lsub(isub++); \n    dense(irow) -= l(i);\n  } \n}\n\ntemplate <> struct LU_kernel_bmod<1>\n{\n  template <typename BlockScalarVector, typename ScalarVector, typename IndexVector>\n  static EIGEN_DONT_INLINE void run(const Index /*segsize*/, BlockScalarVector& dense, ScalarVector& /*tempv*/, ScalarVector& lusup, Index& luptr,\n                                    const Index lda, const Index nrow, IndexVector& lsub, const Index lptr, const Index no_zeros);\n};\n\n\ntemplate <typename BlockScalarVector, typename ScalarVector, typename IndexVector>\nEIGEN_DONT_INLINE void LU_kernel_bmod<1>::run(const Index /*segsize*/, BlockScalarVector& dense, ScalarVector& /*tempv*/, ScalarVector& lusup, Index& luptr,\n                                              const Index lda, const Index nrow, IndexVector& lsub, const Index lptr, const Index no_zeros)\n{\n  typedef typename ScalarVector::Scalar Scalar;\n  typedef typename IndexVector::Scalar StorageIndex;\n  Scalar f = dense(lsub(lptr + no_zeros));\n  luptr += lda * no_zeros + no_zeros + 1;\n  const Scalar* a(lusup.data() + luptr);\n  const StorageIndex*  irow(lsub.data()+lptr + no_zeros + 1);\n  Index i = 0;\n  for (; i+1 < nrow; i+=2)\n  {\n    Index i0 = *(irow++);\n    Index i1 = *(irow++);\n    Scalar a0 = *(a++);\n    Scalar a1 = *(a++);\n    Scalar d0 = dense.coeff(i0);\n    Scalar d1 = dense.coeff(i1);\n    d0 -= f*a0;\n    d1 -= f*a1;\n    dense.coeffRef(i0) = d0;\n    dense.coeffRef(i1) = d1;\n  }\n  if(i<nrow)\n    dense.coeffRef(*(irow++)) -= f * *(a++);\n}\n\n} // end namespace internal\n\n} // end namespace Eigen\n#endif // SPARSELU_KERNEL_BMOD_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseLU/SparseLU_panel_bmod.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2012 Désiré Nuentsa-Wakam <desire.nuentsa_wakam@inria.fr>\n// Copyright (C) 2012 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n/* \n \n * NOTE: This file is the modified version of [s,d,c,z]panel_bmod.c file in SuperLU \n \n * -- SuperLU routine (version 3.0) --\n * Univ. of California Berkeley, Xerox Palo Alto Research Center,\n * and Lawrence Berkeley National Lab.\n * October 15, 2003\n *\n * Copyright (c) 1994 by Xerox Corporation.  All rights reserved.\n *\n * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY\n * EXPRESSED OR IMPLIED.  ANY USE IS AT YOUR OWN RISK.\n *\n * Permission is hereby granted to use or copy this program for any\n * purpose, provided the above notices are retained on all copies.\n * Permission to modify the code and to distribute modified code is\n * granted, provided the above notices are retained, and a notice that\n * the code was modified is included with the above copyright notice.\n */\n#ifndef SPARSELU_PANEL_BMOD_H\n#define SPARSELU_PANEL_BMOD_H\n\nnamespace Eigen {\nnamespace internal {\n\n/**\n * \\brief Performs numeric block updates (sup-panel) in topological order.\n * \n * Before entering this routine, the original nonzeros in the panel\n * were already copied i nto the spa[m,w]\n * \n * \\param m number of rows in the matrix\n * \\param w Panel size\n * \\param jcol Starting  column of the panel\n * \\param nseg Number of segments in the U part\n * \\param dense Store the full representation of the panel \n * \\param tempv working array \n * \\param segrep segment representative... first row in the segment\n * \\param repfnz First nonzero rows\n * \\param glu Global LU data. \n * \n * \n */\ntemplate <typename Scalar, typename StorageIndex>\nvoid SparseLUImpl<Scalar,StorageIndex>::panel_bmod(const Index m, const Index w, const Index jcol, \n                                            const Index nseg, ScalarVector& dense, ScalarVector& tempv,\n                                            IndexVector& segrep, IndexVector& repfnz, GlobalLU_t& glu)\n{\n  \n  Index ksub,jj,nextl_col; \n  Index fsupc, nsupc, nsupr, nrow; \n  Index krep, kfnz; \n  Index lptr; // points to the row subscripts of a supernode \n  Index luptr; // ...\n  Index segsize,no_zeros ; \n  // For each nonz supernode segment of U[*,j] in topological order\n  Index k = nseg - 1; \n  const Index PacketSize = internal::packet_traits<Scalar>::size;\n  \n  for (ksub = 0; ksub < nseg; ksub++)\n  { // For each updating supernode\n    /* krep = representative of current k-th supernode\n     * fsupc =  first supernodal column\n     * nsupc = number of columns in a supernode\n     * nsupr = number of rows in a supernode\n     */\n    krep = segrep(k); k--; \n    fsupc = glu.xsup(glu.supno(krep)); \n    nsupc = krep - fsupc + 1; \n    nsupr = glu.xlsub(fsupc+1) - glu.xlsub(fsupc); \n    nrow = nsupr - nsupc; \n    lptr = glu.xlsub(fsupc); \n    \n    // loop over the panel columns to detect the actual number of columns and rows\n    Index u_rows = 0;\n    Index u_cols = 0;\n    for (jj = jcol; jj < jcol + w; jj++)\n    {\n      nextl_col = (jj-jcol) * m; \n      VectorBlock<IndexVector> repfnz_col(repfnz, nextl_col, m); // First nonzero column index for each row\n      \n      kfnz = repfnz_col(krep); \n      if ( kfnz == emptyIdxLU ) \n        continue; // skip any zero segment\n      \n      segsize = krep - kfnz + 1;\n      u_cols++;\n      u_rows = (std::max)(segsize,u_rows);\n    }\n    \n    if(nsupc >= 2)\n    { \n      Index ldu = internal::first_multiple<Index>(u_rows, PacketSize);\n      Map<ScalarMatrix, Aligned,  OuterStride<> > U(tempv.data(), u_rows, u_cols, OuterStride<>(ldu));\n      \n      // gather U\n      Index u_col = 0;\n      for (jj = jcol; jj < jcol + w; jj++)\n      {\n        nextl_col = (jj-jcol) * m; \n        VectorBlock<IndexVector> repfnz_col(repfnz, nextl_col, m); // First nonzero column index for each row\n        VectorBlock<ScalarVector> dense_col(dense, nextl_col, m); // Scatter/gather entire matrix column from/to here\n        \n        kfnz = repfnz_col(krep); \n        if ( kfnz == emptyIdxLU ) \n          continue; // skip any zero segment\n        \n        segsize = krep - kfnz + 1;\n        luptr = glu.xlusup(fsupc);    \n        no_zeros = kfnz - fsupc; \n        \n        Index isub = lptr + no_zeros;\n        Index off = u_rows-segsize;\n        for (Index i = 0; i < off; i++) U(i,u_col) = 0;\n        for (Index i = 0; i < segsize; i++)\n        {\n          Index irow = glu.lsub(isub); \n          U(i+off,u_col) = dense_col(irow); \n          ++isub; \n        }\n        u_col++;\n      }\n      // solve U = A^-1 U\n      luptr = glu.xlusup(fsupc);\n      Index lda = glu.xlusup(fsupc+1) - glu.xlusup(fsupc);\n      no_zeros = (krep - u_rows + 1) - fsupc;\n      luptr += lda * no_zeros + no_zeros;\n      MappedMatrixBlock A(glu.lusup.data()+luptr, u_rows, u_rows, OuterStride<>(lda) );\n      U = A.template triangularView<UnitLower>().solve(U);\n      \n      // update\n      luptr += u_rows;\n      MappedMatrixBlock B(glu.lusup.data()+luptr, nrow, u_rows, OuterStride<>(lda) );\n      eigen_assert(tempv.size()>w*ldu + nrow*w + 1);\n      \n      Index ldl = internal::first_multiple<Index>(nrow, PacketSize);\n      Index offset = (PacketSize-internal::first_default_aligned(B.data(), PacketSize)) % PacketSize;\n      MappedMatrixBlock L(tempv.data()+w*ldu+offset, nrow, u_cols, OuterStride<>(ldl));\n      \n      L.setZero();\n      internal::sparselu_gemm<Scalar>(L.rows(), L.cols(), B.cols(), B.data(), B.outerStride(), U.data(), U.outerStride(), L.data(), L.outerStride());\n      \n      // scatter U and L\n      u_col = 0;\n      for (jj = jcol; jj < jcol + w; jj++)\n      {\n        nextl_col = (jj-jcol) * m; \n        VectorBlock<IndexVector> repfnz_col(repfnz, nextl_col, m); // First nonzero column index for each row\n        VectorBlock<ScalarVector> dense_col(dense, nextl_col, m); // Scatter/gather entire matrix column from/to here\n        \n        kfnz = repfnz_col(krep); \n        if ( kfnz == emptyIdxLU ) \n          continue; // skip any zero segment\n        \n        segsize = krep - kfnz + 1;\n        no_zeros = kfnz - fsupc; \n        Index isub = lptr + no_zeros;\n        \n        Index off = u_rows-segsize;\n        for (Index i = 0; i < segsize; i++)\n        {\n          Index irow = glu.lsub(isub++); \n          dense_col(irow) = U.coeff(i+off,u_col);\n          U.coeffRef(i+off,u_col) = 0;\n        }\n        \n        // Scatter l into SPA dense[]\n        for (Index i = 0; i < nrow; i++)\n        {\n          Index irow = glu.lsub(isub++); \n          dense_col(irow) -= L.coeff(i,u_col);\n          L.coeffRef(i,u_col) = 0;\n        }\n        u_col++;\n      }\n    }\n    else // level 2 only\n    {\n      // Sequence through each column in the panel\n      for (jj = jcol; jj < jcol + w; jj++)\n      {\n        nextl_col = (jj-jcol) * m; \n        VectorBlock<IndexVector> repfnz_col(repfnz, nextl_col, m); // First nonzero column index for each row\n        VectorBlock<ScalarVector> dense_col(dense, nextl_col, m); // Scatter/gather entire matrix column from/to here\n        \n        kfnz = repfnz_col(krep); \n        if ( kfnz == emptyIdxLU ) \n          continue; // skip any zero segment\n        \n        segsize = krep - kfnz + 1;\n        luptr = glu.xlusup(fsupc);\n        \n        Index lda = glu.xlusup(fsupc+1)-glu.xlusup(fsupc);// nsupr\n        \n        // Perform a trianglar solve and block update, \n        // then scatter the result of sup-col update to dense[]\n        no_zeros = kfnz - fsupc; \n              if(segsize==1)  LU_kernel_bmod<1>::run(segsize, dense_col, tempv, glu.lusup, luptr, lda, nrow, glu.lsub, lptr, no_zeros);\n        else  if(segsize==2)  LU_kernel_bmod<2>::run(segsize, dense_col, tempv, glu.lusup, luptr, lda, nrow, glu.lsub, lptr, no_zeros);\n        else  if(segsize==3)  LU_kernel_bmod<3>::run(segsize, dense_col, tempv, glu.lusup, luptr, lda, nrow, glu.lsub, lptr, no_zeros);\n        else                  LU_kernel_bmod<Dynamic>::run(segsize, dense_col, tempv, glu.lusup, luptr, lda, nrow, glu.lsub, lptr, no_zeros); \n      } // End for each column in the panel \n    }\n    \n  } // End for each updating supernode\n} // end panel bmod\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // SPARSELU_PANEL_BMOD_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseLU/SparseLU_panel_dfs.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2012 Désiré Nuentsa-Wakam <desire.nuentsa_wakam@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n/* \n \n * NOTE: This file is the modified version of [s,d,c,z]panel_dfs.c file in SuperLU \n \n * -- SuperLU routine (version 2.0) --\n * Univ. of California Berkeley, Xerox Palo Alto Research Center,\n * and Lawrence Berkeley National Lab.\n * November 15, 1997\n *\n * Copyright (c) 1994 by Xerox Corporation.  All rights reserved.\n *\n * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY\n * EXPRESSED OR IMPLIED.  ANY USE IS AT YOUR OWN RISK.\n *\n * Permission is hereby granted to use or copy this program for any\n * purpose, provided the above notices are retained on all copies.\n * Permission to modify the code and to distribute modified code is\n * granted, provided the above notices are retained, and a notice that\n * the code was modified is included with the above copyright notice.\n */\n#ifndef SPARSELU_PANEL_DFS_H\n#define SPARSELU_PANEL_DFS_H\n\nnamespace Eigen {\n\nnamespace internal {\n  \ntemplate<typename IndexVector>\nstruct panel_dfs_traits\n{\n  typedef typename IndexVector::Scalar StorageIndex;\n  panel_dfs_traits(Index jcol, StorageIndex* marker)\n    : m_jcol(jcol), m_marker(marker)\n  {}\n  bool update_segrep(Index krep, StorageIndex jj)\n  {\n    if(m_marker[krep]<m_jcol)\n    {\n      m_marker[krep] = jj; \n      return true;\n    }\n    return false;\n  }\n  void mem_expand(IndexVector& /*glu.lsub*/, Index /*nextl*/, Index /*chmark*/) {}\n  enum { ExpandMem = false };\n  Index m_jcol;\n  StorageIndex* m_marker;\n};\n\n\ntemplate <typename Scalar, typename StorageIndex>\ntemplate <typename Traits>\nvoid SparseLUImpl<Scalar,StorageIndex>::dfs_kernel(const StorageIndex jj, IndexVector& perm_r,\n                   Index& nseg, IndexVector& panel_lsub, IndexVector& segrep,\n                   Ref<IndexVector> repfnz_col, IndexVector& xprune, Ref<IndexVector> marker, IndexVector& parent,\n                   IndexVector& xplore, GlobalLU_t& glu,\n                   Index& nextl_col, Index krow, Traits& traits\n                  )\n{\n  \n  StorageIndex kmark = marker(krow);\n      \n  // For each unmarked krow of jj\n  marker(krow) = jj; \n  StorageIndex kperm = perm_r(krow); \n  if (kperm == emptyIdxLU ) {\n    // krow is in L : place it in structure of L(*, jj)\n    panel_lsub(nextl_col++) = StorageIndex(krow);  // krow is indexed into A\n    \n    traits.mem_expand(panel_lsub, nextl_col, kmark);\n  }\n  else \n  {\n    // krow is in U : if its supernode-representative krep\n    // has been explored, update repfnz(*)\n    // krep = supernode representative of the current row\n    StorageIndex krep = glu.xsup(glu.supno(kperm)+1) - 1; \n    // First nonzero element in the current column:\n    StorageIndex myfnz = repfnz_col(krep); \n    \n    if (myfnz != emptyIdxLU )\n    {\n      // Representative visited before\n      if (myfnz > kperm ) repfnz_col(krep) = kperm; \n      \n    }\n    else \n    {\n      // Otherwise, perform dfs starting at krep\n      StorageIndex oldrep = emptyIdxLU; \n      parent(krep) = oldrep; \n      repfnz_col(krep) = kperm; \n      StorageIndex xdfs =  glu.xlsub(krep); \n      Index maxdfs = xprune(krep); \n      \n      StorageIndex kpar;\n      do \n      {\n        // For each unmarked kchild of krep\n        while (xdfs < maxdfs) \n        {\n          StorageIndex kchild = glu.lsub(xdfs); \n          xdfs++; \n          StorageIndex chmark = marker(kchild); \n          \n          if (chmark != jj ) \n          {\n            marker(kchild) = jj; \n            StorageIndex chperm = perm_r(kchild); \n            \n            if (chperm == emptyIdxLU) \n            {\n              // case kchild is in L: place it in L(*, j)\n              panel_lsub(nextl_col++) = kchild;\n              traits.mem_expand(panel_lsub, nextl_col, chmark);\n            }\n            else\n            {\n              // case kchild is in U :\n              // chrep = its supernode-rep. If its rep has been explored, \n              // update its repfnz(*)\n              StorageIndex chrep = glu.xsup(glu.supno(chperm)+1) - 1; \n              myfnz = repfnz_col(chrep); \n              \n              if (myfnz != emptyIdxLU) \n              { // Visited before \n                if (myfnz > chperm) \n                  repfnz_col(chrep) = chperm; \n              }\n              else \n              { // Cont. dfs at snode-rep of kchild\n                xplore(krep) = xdfs; \n                oldrep = krep; \n                krep = chrep; // Go deeper down G(L)\n                parent(krep) = oldrep; \n                repfnz_col(krep) = chperm; \n                xdfs = glu.xlsub(krep); \n                maxdfs = xprune(krep); \n                \n              } // end if myfnz != -1\n            } // end if chperm == -1 \n                \n          } // end if chmark !=jj\n        } // end while xdfs < maxdfs\n        \n        // krow has no more unexplored nbrs :\n        //    Place snode-rep krep in postorder DFS, if this \n        //    segment is seen for the first time. (Note that \n        //    \"repfnz(krep)\" may change later.)\n        //    Baktrack dfs to its parent\n        if(traits.update_segrep(krep,jj))\n        //if (marker1(krep) < jcol )\n        {\n          segrep(nseg) = krep; \n          ++nseg; \n          //marker1(krep) = jj; \n        }\n        \n        kpar = parent(krep); // Pop recursion, mimic recursion \n        if (kpar == emptyIdxLU) \n          break; // dfs done \n        krep = kpar; \n        xdfs = xplore(krep); \n        maxdfs = xprune(krep); \n\n      } while (kpar != emptyIdxLU); // Do until empty stack \n      \n    } // end if (myfnz = -1)\n\n  } // end if (kperm == -1)   \n}\n\n/**\n * \\brief Performs a symbolic factorization on a panel of columns [jcol, jcol+w)\n * \n * A supernode representative is the last column of a supernode.\n * The nonzeros in U[*,j] are segments that end at supernodes representatives\n * \n * The routine returns a list of the supernodal representatives \n * in topological order of the dfs that generates them. This list is \n * a superset of the topological order of each individual column within \n * the panel.\n * The location of the first nonzero in each supernodal segment \n * (supernodal entry location) is also returned. Each column has \n * a separate list for this purpose. \n * \n * Two markers arrays are used for dfs :\n *    marker[i] == jj, if i was visited during dfs of current column jj;\n *    marker1[i] >= jcol, if i was visited by earlier columns in this panel; \n * \n * \\param[in] m number of rows in the matrix\n * \\param[in] w Panel size\n * \\param[in] jcol Starting  column of the panel\n * \\param[in] A Input matrix in column-major storage\n * \\param[in] perm_r Row permutation\n * \\param[out] nseg Number of U segments\n * \\param[out] dense Accumulate the column vectors of the panel\n * \\param[out] panel_lsub Subscripts of the row in the panel \n * \\param[out] segrep Segment representative i.e first nonzero row of each segment\n * \\param[out] repfnz First nonzero location in each row\n * \\param[out] xprune The pruned elimination tree\n * \\param[out] marker work vector\n * \\param  parent The elimination tree\n * \\param xplore work vector\n * \\param glu The global data structure\n * \n */\n\ntemplate <typename Scalar, typename StorageIndex>\nvoid SparseLUImpl<Scalar,StorageIndex>::panel_dfs(const Index m, const Index w, const Index jcol, MatrixType& A, IndexVector& perm_r, Index& nseg, ScalarVector& dense, IndexVector& panel_lsub, IndexVector& segrep, IndexVector& repfnz, IndexVector& xprune, IndexVector& marker, IndexVector& parent, IndexVector& xplore, GlobalLU_t& glu)\n{\n  Index nextl_col; // Next available position in panel_lsub[*,jj] \n  \n  // Initialize pointers \n  VectorBlock<IndexVector> marker1(marker, m, m); \n  nseg = 0; \n  \n  panel_dfs_traits<IndexVector> traits(jcol, marker1.data());\n  \n  // For each column in the panel \n  for (StorageIndex jj = StorageIndex(jcol); jj < jcol + w; jj++) \n  {\n    nextl_col = (jj - jcol) * m; \n    \n    VectorBlock<IndexVector> repfnz_col(repfnz, nextl_col, m); // First nonzero location in each row\n    VectorBlock<ScalarVector> dense_col(dense,nextl_col, m); // Accumulate a column vector here\n    \n    \n    // For each nnz in A[*, jj] do depth first search\n    for (typename MatrixType::InnerIterator it(A, jj); it; ++it)\n    {\n      Index krow = it.row(); \n      dense_col(krow) = it.value();\n      \n      StorageIndex kmark = marker(krow); \n      if (kmark == jj) \n        continue; // krow visited before, go to the next nonzero\n      \n      dfs_kernel(jj, perm_r, nseg, panel_lsub, segrep, repfnz_col, xprune, marker, parent,\n                   xplore, glu, nextl_col, krow, traits);\n    }// end for nonzeros in column jj\n    \n  } // end for column jj\n}\n\n} // end namespace internal\n} // end namespace Eigen\n\n#endif // SPARSELU_PANEL_DFS_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseLU/SparseLU_pivotL.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2012 Désiré Nuentsa-Wakam <desire.nuentsa_wakam@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n/* \n \n * NOTE: This file is the modified version of xpivotL.c file in SuperLU \n \n * -- SuperLU routine (version 3.0) --\n * Univ. of California Berkeley, Xerox Palo Alto Research Center,\n * and Lawrence Berkeley National Lab.\n * October 15, 2003\n *\n * Copyright (c) 1994 by Xerox Corporation.  All rights reserved.\n *\n * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY\n * EXPRESSED OR IMPLIED.  ANY USE IS AT YOUR OWN RISK.\n *\n * Permission is hereby granted to use or copy this program for any\n * purpose, provided the above notices are retained on all copies.\n * Permission to modify the code and to distribute modified code is\n * granted, provided the above notices are retained, and a notice that\n * the code was modified is included with the above copyright notice.\n */\n#ifndef SPARSELU_PIVOTL_H\n#define SPARSELU_PIVOTL_H\n\nnamespace Eigen {\nnamespace internal {\n  \n/**\n * \\brief Performs the numerical pivotin on the current column of L, and the CDIV operation.\n * \n * Pivot policy :\n * (1) Compute thresh = u * max_(i>=j) abs(A_ij);\n * (2) IF user specifies pivot row k and abs(A_kj) >= thresh THEN\n *           pivot row = k;\n *       ELSE IF abs(A_jj) >= thresh THEN\n *           pivot row = j;\n *       ELSE\n *           pivot row = m;\n * \n *   Note: If you absolutely want to use a given pivot order, then set u=0.0.\n * \n * \\param jcol The current column of L\n * \\param diagpivotthresh diagonal pivoting threshold\n * \\param[in,out] perm_r Row permutation (threshold pivoting)\n * \\param[in] iperm_c column permutation - used to finf diagonal of Pc*A*Pc'\n * \\param[out] pivrow  The pivot row\n * \\param glu Global LU data\n * \\return 0 if success, i > 0 if U(i,i) is exactly zero \n * \n */\ntemplate <typename Scalar, typename StorageIndex>\nIndex SparseLUImpl<Scalar,StorageIndex>::pivotL(const Index jcol, const RealScalar& diagpivotthresh, IndexVector& perm_r, IndexVector& iperm_c, Index& pivrow, GlobalLU_t& glu)\n{\n  \n  Index fsupc = (glu.xsup)((glu.supno)(jcol)); // First column in the supernode containing the column jcol\n  Index nsupc = jcol - fsupc; // Number of columns in the supernode portion, excluding jcol; nsupc >=0\n  Index lptr = glu.xlsub(fsupc); // pointer to the starting location of the row subscripts for this supernode portion\n  Index nsupr = glu.xlsub(fsupc+1) - lptr; // Number of rows in the supernode\n  Index lda = glu.xlusup(fsupc+1) - glu.xlusup(fsupc); // leading dimension\n  Scalar* lu_sup_ptr = &(glu.lusup.data()[glu.xlusup(fsupc)]); // Start of the current supernode\n  Scalar* lu_col_ptr = &(glu.lusup.data()[glu.xlusup(jcol)]); // Start of jcol in the supernode\n  StorageIndex* lsub_ptr = &(glu.lsub.data()[lptr]); // Start of row indices of the supernode\n  \n  // Determine the largest abs numerical value for partial pivoting \n  Index diagind = iperm_c(jcol); // diagonal index \n  RealScalar pivmax(-1.0);\n  Index pivptr = nsupc; \n  Index diag = emptyIdxLU; \n  RealScalar rtemp;\n  Index isub, icol, itemp, k; \n  for (isub = nsupc; isub < nsupr; ++isub) {\n    using std::abs;\n    rtemp = abs(lu_col_ptr[isub]);\n    if (rtemp > pivmax) {\n      pivmax = rtemp; \n      pivptr = isub;\n    } \n    if (lsub_ptr[isub] == diagind) diag = isub;\n  }\n  \n  // Test for singularity\n  if ( pivmax <= RealScalar(0.0) ) {\n    // if pivmax == -1, the column is structurally empty, otherwise it is only numerically zero\n    pivrow = pivmax < RealScalar(0.0) ? diagind : lsub_ptr[pivptr];\n    perm_r(pivrow) = StorageIndex(jcol);\n    return (jcol+1);\n  }\n  \n  RealScalar thresh = diagpivotthresh * pivmax; \n  \n  // Choose appropriate pivotal element \n  \n  {\n    // Test if the diagonal element can be used as a pivot (given the threshold value)\n    if (diag >= 0 ) \n    {\n      // Diagonal element exists\n      using std::abs;\n      rtemp = abs(lu_col_ptr[diag]);\n      if (rtemp != RealScalar(0.0) && rtemp >= thresh) pivptr = diag;\n    }\n    pivrow = lsub_ptr[pivptr];\n  }\n  \n  // Record pivot row\n  perm_r(pivrow) = StorageIndex(jcol);\n  // Interchange row subscripts\n  if (pivptr != nsupc )\n  {\n    std::swap( lsub_ptr[pivptr], lsub_ptr[nsupc] );\n    // Interchange numerical values as well, for the two rows in the whole snode\n    // such that L is indexed the same way as A\n    for (icol = 0; icol <= nsupc; icol++)\n    {\n      itemp = pivptr + icol * lda; \n      std::swap(lu_sup_ptr[itemp], lu_sup_ptr[nsupc + icol * lda]);\n    }\n  }\n  // cdiv operations\n  Scalar temp = Scalar(1.0) / lu_col_ptr[nsupc];\n  for (k = nsupc+1; k < nsupr; k++)\n    lu_col_ptr[k] *= temp; \n  return 0;\n}\n\n} // end namespace internal\n} // end namespace Eigen\n\n#endif // SPARSELU_PIVOTL_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseLU/SparseLU_pruneL.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2012 Désiré Nuentsa-Wakam <desire.nuentsa_wakam@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n/* \n \n * NOTE: This file is the modified version of [s,d,c,z]pruneL.c file in SuperLU \n \n * -- SuperLU routine (version 2.0) --\n * Univ. of California Berkeley, Xerox Palo Alto Research Center,\n * and Lawrence Berkeley National Lab.\n * November 15, 1997\n *\n * Copyright (c) 1994 by Xerox Corporation.  All rights reserved.\n *\n * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY\n * EXPRESSED OR IMPLIED.  ANY USE IS AT YOUR OWN RISK.\n *\n * Permission is hereby granted to use or copy this program for any\n * purpose, provided the above notices are retained on all copies.\n * Permission to modify the code and to distribute modified code is\n * granted, provided the above notices are retained, and a notice that\n * the code was modified is included with the above copyright notice.\n */\n#ifndef SPARSELU_PRUNEL_H\n#define SPARSELU_PRUNEL_H\n\nnamespace Eigen {\nnamespace internal {\n\n/**\n * \\brief Prunes the L-structure.\n *\n * It prunes the L-structure  of supernodes whose L-structure contains the current pivot row \"pivrow\"\n * \n * \n * \\param jcol The current column of L\n * \\param[in] perm_r Row permutation\n * \\param[out] pivrow  The pivot row\n * \\param nseg Number of segments\n * \\param segrep \n * \\param repfnz\n * \\param[out] xprune \n * \\param glu Global LU data\n * \n */\ntemplate <typename Scalar, typename StorageIndex>\nvoid SparseLUImpl<Scalar,StorageIndex>::pruneL(const Index jcol, const IndexVector& perm_r, const Index pivrow, const Index nseg,\n                                               const IndexVector& segrep, BlockIndexVector repfnz, IndexVector& xprune, GlobalLU_t& glu)\n{\n  // For each supernode-rep irep in U(*,j]\n  Index jsupno = glu.supno(jcol); \n  Index i,irep,irep1; \n  bool movnum, do_prune = false; \n  Index kmin = 0, kmax = 0, minloc, maxloc,krow; \n  for (i = 0; i < nseg; i++)\n  {\n    irep = segrep(i); \n    irep1 = irep + 1; \n    do_prune = false; \n    \n    // Don't prune with a zero U-segment \n    if (repfnz(irep) == emptyIdxLU) continue; \n    \n    // If a snode overlaps with the next panel, then the U-segment\n    // is fragmented into two parts -- irep and irep1. We should let \n    // pruning occur at the rep-column in irep1s snode. \n    if (glu.supno(irep) == glu.supno(irep1) ) continue; // don't prune \n    \n    // If it has not been pruned & it has a nonz in row L(pivrow,i)\n    if (glu.supno(irep) != jsupno )\n    {\n      if ( xprune (irep) >= glu.xlsub(irep1) )\n      {\n        kmin = glu.xlsub(irep);\n        kmax = glu.xlsub(irep1) - 1; \n        for (krow = kmin; krow <= kmax; krow++)\n        {\n          if (glu.lsub(krow) == pivrow) \n          {\n            do_prune = true; \n            break; \n          }\n        }\n      }\n      \n      if (do_prune) \n      {\n        // do a quicksort-type partition\n        // movnum=true means that the num values have to be exchanged\n        movnum = false; \n        if (irep == glu.xsup(glu.supno(irep)) ) // Snode of size 1 \n          movnum = true; \n        \n        while (kmin <= kmax)\n        {\n          if (perm_r(glu.lsub(kmax)) == emptyIdxLU)\n            kmax--; \n          else if ( perm_r(glu.lsub(kmin)) != emptyIdxLU)\n            kmin++;\n          else \n          {\n            // kmin below pivrow (not yet pivoted), and kmax\n            // above pivrow: interchange the two suscripts\n            std::swap(glu.lsub(kmin), glu.lsub(kmax)); \n            \n            // If the supernode has only one column, then we \n            // only keep one set of subscripts. For any subscript\n            // intercnahge performed, similar interchange must be \n            // done on the numerical values. \n            if (movnum) \n            {\n              minloc = glu.xlusup(irep) + ( kmin - glu.xlsub(irep) ); \n              maxloc = glu.xlusup(irep) + ( kmax - glu.xlsub(irep) ); \n              std::swap(glu.lusup(minloc), glu.lusup(maxloc)); \n            }\n            kmin++;\n            kmax--;\n          }\n        } // end while \n        \n        xprune(irep) = StorageIndex(kmin);  //Pruning \n      } // end if do_prune \n    } // end pruning \n  } // End for each U-segment\n}\n\n} // end namespace internal\n} // end namespace Eigen\n\n#endif // SPARSELU_PRUNEL_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseLU/SparseLU_relax_snode.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2012 Désiré Nuentsa-Wakam <desire.nuentsa_wakam@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n/* This file is a modified version of heap_relax_snode.c file in SuperLU\n * -- SuperLU routine (version 3.0) --\n * Univ. of California Berkeley, Xerox Palo Alto Research Center,\n * and Lawrence Berkeley National Lab.\n * October 15, 2003\n *\n * Copyright (c) 1994 by Xerox Corporation.  All rights reserved.\n *\n * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY\n * EXPRESSED OR IMPLIED.  ANY USE IS AT YOUR OWN RISK.\n *\n * Permission is hereby granted to use or copy this program for any\n * purpose, provided the above notices are retained on all copies.\n * Permission to modify the code and to distribute modified code is\n * granted, provided the above notices are retained, and a notice that\n * the code was modified is included with the above copyright notice.\n */\n\n#ifndef SPARSELU_RELAX_SNODE_H\n#define SPARSELU_RELAX_SNODE_H\n\nnamespace Eigen {\n\nnamespace internal {\n \n/** \n * \\brief Identify the initial relaxed supernodes\n * \n * This routine is applied to a column elimination tree. \n * It assumes that the matrix has been reordered according to the postorder of the etree\n * \\param n  the number of columns\n * \\param et elimination tree \n * \\param relax_columns Maximum number of columns allowed in a relaxed snode \n * \\param descendants Number of descendants of each node in the etree\n * \\param relax_end last column in a supernode\n */\ntemplate <typename Scalar, typename StorageIndex>\nvoid SparseLUImpl<Scalar,StorageIndex>::relax_snode (const Index n, IndexVector& et, const Index relax_columns, IndexVector& descendants, IndexVector& relax_end)\n{\n  \n  // compute the number of descendants of each node in the etree\n  Index parent; \n  relax_end.setConstant(emptyIdxLU);\n  descendants.setZero();\n  for (Index j = 0; j < n; j++) \n  {\n    parent = et(j);\n    if (parent != n) // not the dummy root\n      descendants(parent) += descendants(j) + 1;\n  }\n  // Identify the relaxed supernodes by postorder traversal of the etree\n  Index snode_start; // beginning of a snode \n  for (Index j = 0; j < n; )\n  {\n    parent = et(j);\n    snode_start = j; \n    while ( parent != n && descendants(parent) < relax_columns ) \n    {\n      j = parent; \n      parent = et(j);\n    }\n    // Found a supernode in postordered etree, j is the last column \n    relax_end(snode_start) = StorageIndex(j); // Record last column\n    j++;\n    // Search for a new leaf\n    while (descendants(j) != 0 && j < n) j++;\n  } // End postorder traversal of the etree\n  \n}\n\n} // end namespace internal\n\n} // end namespace Eigen\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SparseQR/SparseQR.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2012-2013 Desire Nuentsa <desire.nuentsa_wakam@inria.fr>\n// Copyright (C) 2012-2014 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SPARSE_QR_H\n#define EIGEN_SPARSE_QR_H\n\nnamespace Eigen {\n\ntemplate<typename MatrixType, typename OrderingType> class SparseQR;\ntemplate<typename SparseQRType> struct SparseQRMatrixQReturnType;\ntemplate<typename SparseQRType> struct SparseQRMatrixQTransposeReturnType;\ntemplate<typename SparseQRType, typename Derived> struct SparseQR_QProduct;\nnamespace internal {\n  template <typename SparseQRType> struct traits<SparseQRMatrixQReturnType<SparseQRType> >\n  {\n    typedef typename SparseQRType::MatrixType ReturnType;\n    typedef typename ReturnType::StorageIndex StorageIndex;\n    typedef typename ReturnType::StorageKind StorageKind;\n    enum {\n      RowsAtCompileTime = Dynamic,\n      ColsAtCompileTime = Dynamic\n    };\n  };\n  template <typename SparseQRType> struct traits<SparseQRMatrixQTransposeReturnType<SparseQRType> >\n  {\n    typedef typename SparseQRType::MatrixType ReturnType;\n  };\n  template <typename SparseQRType, typename Derived> struct traits<SparseQR_QProduct<SparseQRType, Derived> >\n  {\n    typedef typename Derived::PlainObject ReturnType;\n  };\n} // End namespace internal\n\n/**\n  * \\ingroup SparseQR_Module\n  * \\class SparseQR\n  * \\brief Sparse left-looking rank-revealing QR factorization\n  * \n  * This class implements a left-looking rank-revealing QR decomposition \n  * of sparse matrices. When a column has a norm less than a given tolerance\n  * it is implicitly permuted to the end. The QR factorization thus obtained is \n  * given by A*P = Q*R where R is upper triangular or trapezoidal. \n  * \n  * P is the column permutation which is the product of the fill-reducing and the\n  * rank-revealing permutations. Use colsPermutation() to get it.\n  * \n  * Q is the orthogonal matrix represented as products of Householder reflectors. \n  * Use matrixQ() to get an expression and matrixQ().transpose() to get the transpose.\n  * You can then apply it to a vector.\n  * \n  * R is the sparse triangular or trapezoidal matrix. The later occurs when A is rank-deficient.\n  * matrixR().topLeftCorner(rank(), rank()) always returns a triangular factor of full rank.\n  * \n  * \\tparam _MatrixType The type of the sparse matrix A, must be a column-major SparseMatrix<>\n  * \\tparam _OrderingType The fill-reducing ordering method. See the \\link OrderingMethods_Module \n  *  OrderingMethods \\endlink module for the list of built-in and external ordering methods.\n  * \n  * \\implsparsesolverconcept\n  *\n  * \\warning The input sparse matrix A must be in compressed mode (see SparseMatrix::makeCompressed()).\n  * \n  */\ntemplate<typename _MatrixType, typename _OrderingType>\nclass SparseQR : public SparseSolverBase<SparseQR<_MatrixType,_OrderingType> >\n{\n  protected:\n    typedef SparseSolverBase<SparseQR<_MatrixType,_OrderingType> > Base;\n    using Base::m_isInitialized;\n  public:\n    using Base::_solve_impl;\n    typedef _MatrixType MatrixType;\n    typedef _OrderingType OrderingType;\n    typedef typename MatrixType::Scalar Scalar;\n    typedef typename MatrixType::RealScalar RealScalar;\n    typedef typename MatrixType::StorageIndex StorageIndex;\n    typedef SparseMatrix<Scalar,ColMajor,StorageIndex> QRMatrixType;\n    typedef Matrix<StorageIndex, Dynamic, 1> IndexVector;\n    typedef Matrix<Scalar, Dynamic, 1> ScalarVector;\n    typedef PermutationMatrix<Dynamic, Dynamic, StorageIndex> PermutationType;\n\n    enum {\n      ColsAtCompileTime = MatrixType::ColsAtCompileTime,\n      MaxColsAtCompileTime = MatrixType::MaxColsAtCompileTime\n    };\n    \n  public:\n    SparseQR () :  m_analysisIsok(false), m_lastError(\"\"), m_useDefaultThreshold(true),m_isQSorted(false),m_isEtreeOk(false)\n    { }\n    \n    /** Construct a QR factorization of the matrix \\a mat.\n      * \n      * \\warning The matrix \\a mat must be in compressed mode (see SparseMatrix::makeCompressed()).\n      * \n      * \\sa compute()\n      */\n    explicit SparseQR(const MatrixType& mat) : m_analysisIsok(false), m_lastError(\"\"), m_useDefaultThreshold(true),m_isQSorted(false),m_isEtreeOk(false)\n    {\n      compute(mat);\n    }\n    \n    /** Computes the QR factorization of the sparse matrix \\a mat.\n      * \n      * \\warning The matrix \\a mat must be in compressed mode (see SparseMatrix::makeCompressed()).\n      * \n      * \\sa analyzePattern(), factorize()\n      */\n    void compute(const MatrixType& mat)\n    {\n      analyzePattern(mat);\n      factorize(mat);\n    }\n    void analyzePattern(const MatrixType& mat);\n    void factorize(const MatrixType& mat);\n    \n    /** \\returns the number of rows of the represented matrix. \n      */\n    inline Index rows() const { return m_pmat.rows(); }\n    \n    /** \\returns the number of columns of the represented matrix. \n      */\n    inline Index cols() const { return m_pmat.cols();}\n    \n    /** \\returns a const reference to the \\b sparse upper triangular matrix R of the QR factorization.\n      * \\warning The entries of the returned matrix are not sorted. This means that using it in algorithms\n      *          expecting sorted entries will fail. This include random coefficient accesses (SpaseMatrix::coeff()),\n      *          and coefficient-wise operations. Matrix products and triangular solves are fine though.\n      *\n      * To sort the entries, you can assign it to a row-major matrix, and if a column-major matrix\n      * is required, you can copy it again:\n      * \\code\n      * SparseMatrix<double>          R  = qr.matrixR();  // column-major, not sorted!\n      * SparseMatrix<double,RowMajor> Rr = qr.matrixR();  // row-major, sorted\n      * SparseMatrix<double>          Rc = Rr;            // column-major, sorted\n      * \\endcode\n      */\n    const QRMatrixType& matrixR() const { return m_R; }\n    \n    /** \\returns the number of non linearly dependent columns as determined by the pivoting threshold.\n      *\n      * \\sa setPivotThreshold()\n      */\n    Index rank() const\n    {\n      eigen_assert(m_isInitialized && \"The factorization should be called first, use compute()\");\n      return m_nonzeropivots; \n    }\n    \n    /** \\returns an expression of the matrix Q as products of sparse Householder reflectors.\n    * The common usage of this function is to apply it to a dense matrix or vector\n    * \\code\n    * VectorXd B1, B2;\n    * // Initialize B1\n    * B2 = matrixQ() * B1;\n    * \\endcode\n    *\n    * To get a plain SparseMatrix representation of Q:\n    * \\code\n    * SparseMatrix<double> Q;\n    * Q = SparseQR<SparseMatrix<double> >(A).matrixQ();\n    * \\endcode\n    * Internally, this call simply performs a sparse product between the matrix Q\n    * and a sparse identity matrix. However, due to the fact that the sparse\n    * reflectors are stored unsorted, two transpositions are needed to sort\n    * them before performing the product.\n    */\n    SparseQRMatrixQReturnType<SparseQR> matrixQ() const \n    { return SparseQRMatrixQReturnType<SparseQR>(*this); }\n    \n    /** \\returns a const reference to the column permutation P that was applied to A such that A*P = Q*R\n      * It is the combination of the fill-in reducing permutation and numerical column pivoting.\n      */\n    const PermutationType& colsPermutation() const\n    { \n      eigen_assert(m_isInitialized && \"Decomposition is not initialized.\");\n      return m_outputPerm_c;\n    }\n    \n    /** \\returns A string describing the type of error.\n      * This method is provided to ease debugging, not to handle errors.\n      */\n    std::string lastErrorMessage() const { return m_lastError; }\n    \n    /** \\internal */\n    template<typename Rhs, typename Dest>\n    bool _solve_impl(const MatrixBase<Rhs> &B, MatrixBase<Dest> &dest) const\n    {\n      eigen_assert(m_isInitialized && \"The factorization should be called first, use compute()\");\n      eigen_assert(this->rows() == B.rows() && \"SparseQR::solve() : invalid number of rows in the right hand side matrix\");\n\n      Index rank = this->rank();\n      \n      // Compute Q^T * b;\n      typename Dest::PlainObject y, b;\n      y = this->matrixQ().transpose() * B; \n      b = y;\n      \n      // Solve with the triangular matrix R\n      y.resize((std::max<Index>)(cols(),y.rows()),y.cols());\n      y.topRows(rank) = this->matrixR().topLeftCorner(rank, rank).template triangularView<Upper>().solve(b.topRows(rank));\n      y.bottomRows(y.rows()-rank).setZero();\n      \n      // Apply the column permutation\n      if (m_perm_c.size())  dest = colsPermutation() * y.topRows(cols());\n      else                  dest = y.topRows(cols());\n      \n      m_info = Success;\n      return true;\n    }\n\n    /** Sets the threshold that is used to determine linearly dependent columns during the factorization.\n      *\n      * In practice, if during the factorization the norm of the column that has to be eliminated is below\n      * this threshold, then the entire column is treated as zero, and it is moved at the end.\n      */\n    void setPivotThreshold(const RealScalar& threshold)\n    {\n      m_useDefaultThreshold = false;\n      m_threshold = threshold;\n    }\n    \n    /** \\returns the solution X of \\f$ A X = B \\f$ using the current decomposition of A.\n      *\n      * \\sa compute()\n      */\n    template<typename Rhs>\n    inline const Solve<SparseQR, Rhs> solve(const MatrixBase<Rhs>& B) const \n    {\n      eigen_assert(m_isInitialized && \"The factorization should be called first, use compute()\");\n      eigen_assert(this->rows() == B.rows() && \"SparseQR::solve() : invalid number of rows in the right hand side matrix\");\n      return Solve<SparseQR, Rhs>(*this, B.derived());\n    }\n    template<typename Rhs>\n    inline const Solve<SparseQR, Rhs> solve(const SparseMatrixBase<Rhs>& B) const\n    {\n          eigen_assert(m_isInitialized && \"The factorization should be called first, use compute()\");\n          eigen_assert(this->rows() == B.rows() && \"SparseQR::solve() : invalid number of rows in the right hand side matrix\");\n          return Solve<SparseQR, Rhs>(*this, B.derived());\n    }\n    \n    /** \\brief Reports whether previous computation was successful.\n      *\n      * \\returns \\c Success if computation was successful,\n      *          \\c NumericalIssue if the QR factorization reports a numerical problem\n      *          \\c InvalidInput if the input matrix is invalid\n      *\n      * \\sa iparm()          \n      */\n    ComputationInfo info() const\n    {\n      eigen_assert(m_isInitialized && \"Decomposition is not initialized.\");\n      return m_info;\n    }\n\n\n    /** \\internal */\n    inline void _sort_matrix_Q()\n    {\n      if(this->m_isQSorted) return;\n      // The matrix Q is sorted during the transposition\n      SparseMatrix<Scalar, RowMajor, Index> mQrm(this->m_Q);\n      this->m_Q = mQrm;\n      this->m_isQSorted = true;\n    }\n\n    \n  protected:\n    bool m_analysisIsok;\n    bool m_factorizationIsok;\n    mutable ComputationInfo m_info;\n    std::string m_lastError;\n    QRMatrixType m_pmat;            // Temporary matrix\n    QRMatrixType m_R;               // The triangular factor matrix\n    QRMatrixType m_Q;               // The orthogonal reflectors\n    ScalarVector m_hcoeffs;         // The Householder coefficients\n    PermutationType m_perm_c;       // Fill-reducing  Column  permutation\n    PermutationType m_pivotperm;    // The permutation for rank revealing\n    PermutationType m_outputPerm_c; // The final column permutation\n    RealScalar m_threshold;         // Threshold to determine null Householder reflections\n    bool m_useDefaultThreshold;     // Use default threshold\n    Index m_nonzeropivots;          // Number of non zero pivots found\n    IndexVector m_etree;            // Column elimination tree\n    IndexVector m_firstRowElt;      // First element in each row\n    bool m_isQSorted;               // whether Q is sorted or not\n    bool m_isEtreeOk;               // whether the elimination tree match the initial input matrix\n    \n    template <typename, typename > friend struct SparseQR_QProduct;\n    \n};\n\n/** \\brief Preprocessing step of a QR factorization \n  * \n  * \\warning The matrix \\a mat must be in compressed mode (see SparseMatrix::makeCompressed()).\n  * \n  * In this step, the fill-reducing permutation is computed and applied to the columns of A\n  * and the column elimination tree is computed as well. Only the sparsity pattern of \\a mat is exploited.\n  * \n  * \\note In this step it is assumed that there is no empty row in the matrix \\a mat.\n  */\ntemplate <typename MatrixType, typename OrderingType>\nvoid SparseQR<MatrixType,OrderingType>::analyzePattern(const MatrixType& mat)\n{\n  eigen_assert(mat.isCompressed() && \"SparseQR requires a sparse matrix in compressed mode. Call .makeCompressed() before passing it to SparseQR\");\n  // Copy to a column major matrix if the input is rowmajor\n  typename internal::conditional<MatrixType::IsRowMajor,QRMatrixType,const MatrixType&>::type matCpy(mat);\n  // Compute the column fill reducing ordering\n  OrderingType ord; \n  ord(matCpy, m_perm_c); \n  Index n = mat.cols();\n  Index m = mat.rows();\n  Index diagSize = (std::min)(m,n);\n  \n  if (!m_perm_c.size())\n  {\n    m_perm_c.resize(n);\n    m_perm_c.indices().setLinSpaced(n, 0,StorageIndex(n-1));\n  }\n  \n  // Compute the column elimination tree of the permuted matrix\n  m_outputPerm_c = m_perm_c.inverse();\n  internal::coletree(matCpy, m_etree, m_firstRowElt, m_outputPerm_c.indices().data());\n  m_isEtreeOk = true;\n  \n  m_R.resize(m, n);\n  m_Q.resize(m, diagSize);\n  \n  // Allocate space for nonzero elements : rough estimation\n  m_R.reserve(2*mat.nonZeros()); //FIXME Get a more accurate estimation through symbolic factorization with the etree\n  m_Q.reserve(2*mat.nonZeros());\n  m_hcoeffs.resize(diagSize);\n  m_analysisIsok = true;\n}\n\n/** \\brief Performs the numerical QR factorization of the input matrix\n  * \n  * The function SparseQR::analyzePattern(const MatrixType&) must have been called beforehand with\n  * a matrix having the same sparsity pattern than \\a mat.\n  * \n  * \\param mat The sparse column-major matrix\n  */\ntemplate <typename MatrixType, typename OrderingType>\nvoid SparseQR<MatrixType,OrderingType>::factorize(const MatrixType& mat)\n{\n  using std::abs;\n  \n  eigen_assert(m_analysisIsok && \"analyzePattern() should be called before this step\");\n  StorageIndex m = StorageIndex(mat.rows());\n  StorageIndex n = StorageIndex(mat.cols());\n  StorageIndex diagSize = (std::min)(m,n);\n  IndexVector mark((std::max)(m,n)); mark.setConstant(-1);  // Record the visited nodes\n  IndexVector Ridx(n), Qidx(m);                             // Store temporarily the row indexes for the current column of R and Q\n  Index nzcolR, nzcolQ;                                     // Number of nonzero for the current column of R and Q\n  ScalarVector tval(m);                                     // The dense vector used to compute the current column\n  RealScalar pivotThreshold = m_threshold;\n  \n  m_R.setZero();\n  m_Q.setZero();\n  m_pmat = mat;\n  if(!m_isEtreeOk)\n  {\n    m_outputPerm_c = m_perm_c.inverse();\n    internal::coletree(m_pmat, m_etree, m_firstRowElt, m_outputPerm_c.indices().data());\n    m_isEtreeOk = true;\n  }\n\n  m_pmat.uncompress(); // To have the innerNonZeroPtr allocated\n  \n  // Apply the fill-in reducing permutation lazily:\n  {\n    // If the input is row major, copy the original column indices,\n    // otherwise directly use the input matrix\n    // \n    IndexVector originalOuterIndicesCpy;\n    const StorageIndex *originalOuterIndices = mat.outerIndexPtr();\n    if(MatrixType::IsRowMajor)\n    {\n      originalOuterIndicesCpy = IndexVector::Map(m_pmat.outerIndexPtr(),n+1);\n      originalOuterIndices = originalOuterIndicesCpy.data();\n    }\n    \n    for (int i = 0; i < n; i++)\n    {\n      Index p = m_perm_c.size() ? m_perm_c.indices()(i) : i;\n      m_pmat.outerIndexPtr()[p] = originalOuterIndices[i]; \n      m_pmat.innerNonZeroPtr()[p] = originalOuterIndices[i+1] - originalOuterIndices[i]; \n    }\n  }\n  \n  /* Compute the default threshold as in MatLab, see:\n   * Tim Davis, \"Algorithm 915, SuiteSparseQR: Multifrontal Multithreaded Rank-Revealing\n   * Sparse QR Factorization, ACM Trans. on Math. Soft. 38(1), 2011, Page 8:3 \n   */\n  if(m_useDefaultThreshold) \n  {\n    RealScalar max2Norm = 0.0;\n    for (int j = 0; j < n; j++) max2Norm = numext::maxi(max2Norm, m_pmat.col(j).norm());\n    if(max2Norm==RealScalar(0))\n      max2Norm = RealScalar(1);\n    pivotThreshold = 20 * (m + n) * max2Norm * NumTraits<RealScalar>::epsilon();\n  }\n  \n  // Initialize the numerical permutation\n  m_pivotperm.setIdentity(n);\n  \n  StorageIndex nonzeroCol = 0; // Record the number of valid pivots\n  m_Q.startVec(0);\n\n  // Left looking rank-revealing QR factorization: compute a column of R and Q at a time\n  for (StorageIndex col = 0; col < n; ++col)\n  {\n    mark.setConstant(-1);\n    m_R.startVec(col);\n    mark(nonzeroCol) = col;\n    Qidx(0) = nonzeroCol;\n    nzcolR = 0; nzcolQ = 1;\n    bool found_diag = nonzeroCol>=m;\n    tval.setZero(); \n    \n    // Symbolic factorization: find the nonzero locations of the column k of the factors R and Q, i.e.,\n    // all the nodes (with indexes lower than rank) reachable through the column elimination tree (etree) rooted at node k.\n    // Note: if the diagonal entry does not exist, then its contribution must be explicitly added,\n    // thus the trick with found_diag that permits to do one more iteration on the diagonal element if this one has not been found.\n    for (typename QRMatrixType::InnerIterator itp(m_pmat, col); itp || !found_diag; ++itp)\n    {\n      StorageIndex curIdx = nonzeroCol;\n      if(itp) curIdx = StorageIndex(itp.row());\n      if(curIdx == nonzeroCol) found_diag = true;\n      \n      // Get the nonzeros indexes of the current column of R\n      StorageIndex st = m_firstRowElt(curIdx); // The traversal of the etree starts here\n      if (st < 0 )\n      {\n        m_lastError = \"Empty row found during numerical factorization\";\n        m_info = InvalidInput;\n        return;\n      }\n\n      // Traverse the etree \n      Index bi = nzcolR;\n      for (; mark(st) != col; st = m_etree(st))\n      {\n        Ridx(nzcolR) = st;  // Add this row to the list,\n        mark(st) = col;     // and mark this row as visited\n        nzcolR++;\n      }\n\n      // Reverse the list to get the topological ordering\n      Index nt = nzcolR-bi;\n      for(Index i = 0; i < nt/2; i++) std::swap(Ridx(bi+i), Ridx(nzcolR-i-1));\n       \n      // Copy the current (curIdx,pcol) value of the input matrix\n      if(itp) tval(curIdx) = itp.value();\n      else    tval(curIdx) = Scalar(0);\n      \n      // Compute the pattern of Q(:,k)\n      if(curIdx > nonzeroCol && mark(curIdx) != col ) \n      {\n        Qidx(nzcolQ) = curIdx;  // Add this row to the pattern of Q,\n        mark(curIdx) = col;     // and mark it as visited\n        nzcolQ++;\n      }\n    }\n\n    // Browse all the indexes of R(:,col) in reverse order\n    for (Index i = nzcolR-1; i >= 0; i--)\n    {\n      Index curIdx = Ridx(i);\n      \n      // Apply the curIdx-th householder vector to the current column (temporarily stored into tval)\n      Scalar tdot(0);\n      \n      // First compute q' * tval\n      tdot = m_Q.col(curIdx).dot(tval);\n\n      tdot *= m_hcoeffs(curIdx);\n      \n      // Then update tval = tval - q * tau\n      // FIXME: tval -= tdot * m_Q.col(curIdx) should amount to the same (need to check/add support for efficient \"dense ?= sparse\")\n      for (typename QRMatrixType::InnerIterator itq(m_Q, curIdx); itq; ++itq)\n        tval(itq.row()) -= itq.value() * tdot;\n\n      // Detect fill-in for the current column of Q\n      if(m_etree(Ridx(i)) == nonzeroCol)\n      {\n        for (typename QRMatrixType::InnerIterator itq(m_Q, curIdx); itq; ++itq)\n        {\n          StorageIndex iQ = StorageIndex(itq.row());\n          if (mark(iQ) != col)\n          {\n            Qidx(nzcolQ++) = iQ;  // Add this row to the pattern of Q,\n            mark(iQ) = col;       // and mark it as visited\n          }\n        }\n      }\n    } // End update current column\n    \n    Scalar tau = RealScalar(0);\n    RealScalar beta = 0;\n    \n    if(nonzeroCol < diagSize)\n    {\n      // Compute the Householder reflection that eliminate the current column\n      // FIXME this step should call the Householder module.\n      Scalar c0 = nzcolQ ? tval(Qidx(0)) : Scalar(0);\n      \n      // First, the squared norm of Q((col+1):m, col)\n      RealScalar sqrNorm = 0.;\n      for (Index itq = 1; itq < nzcolQ; ++itq) sqrNorm += numext::abs2(tval(Qidx(itq)));\n      if(sqrNorm == RealScalar(0) && numext::imag(c0) == RealScalar(0))\n      {\n        beta = numext::real(c0);\n        tval(Qidx(0)) = 1;\n      }\n      else\n      {\n        using std::sqrt;\n        beta = sqrt(numext::abs2(c0) + sqrNorm);\n        if(numext::real(c0) >= RealScalar(0))\n          beta = -beta;\n        tval(Qidx(0)) = 1;\n        for (Index itq = 1; itq < nzcolQ; ++itq)\n          tval(Qidx(itq)) /= (c0 - beta);\n        tau = numext::conj((beta-c0) / beta);\n          \n      }\n    }\n\n    // Insert values in R\n    for (Index  i = nzcolR-1; i >= 0; i--)\n    {\n      Index curIdx = Ridx(i);\n      if(curIdx < nonzeroCol) \n      {\n        m_R.insertBackByOuterInnerUnordered(col, curIdx) = tval(curIdx);\n        tval(curIdx) = Scalar(0.);\n      }\n    }\n\n    if(nonzeroCol < diagSize && abs(beta) >= pivotThreshold)\n    {\n      m_R.insertBackByOuterInner(col, nonzeroCol) = beta;\n      // The householder coefficient\n      m_hcoeffs(nonzeroCol) = tau;\n      // Record the householder reflections\n      for (Index itq = 0; itq < nzcolQ; ++itq)\n      {\n        Index iQ = Qidx(itq);\n        m_Q.insertBackByOuterInnerUnordered(nonzeroCol,iQ) = tval(iQ);\n        tval(iQ) = Scalar(0.);\n      }\n      nonzeroCol++;\n      if(nonzeroCol<diagSize)\n        m_Q.startVec(nonzeroCol);\n    }\n    else\n    {\n      // Zero pivot found: move implicitly this column to the end\n      for (Index j = nonzeroCol; j < n-1; j++) \n        std::swap(m_pivotperm.indices()(j), m_pivotperm.indices()[j+1]);\n      \n      // Recompute the column elimination tree\n      internal::coletree(m_pmat, m_etree, m_firstRowElt, m_pivotperm.indices().data());\n      m_isEtreeOk = false;\n    }\n  }\n  \n  m_hcoeffs.tail(diagSize-nonzeroCol).setZero();\n  \n  // Finalize the column pointers of the sparse matrices R and Q\n  m_Q.finalize();\n  m_Q.makeCompressed();\n  m_R.finalize();\n  m_R.makeCompressed();\n  m_isQSorted = false;\n\n  m_nonzeropivots = nonzeroCol;\n  \n  if(nonzeroCol<n)\n  {\n    // Permute the triangular factor to put the 'dead' columns to the end\n    QRMatrixType tempR(m_R);\n    m_R = tempR * m_pivotperm;\n    \n    // Update the column permutation\n    m_outputPerm_c = m_outputPerm_c * m_pivotperm;\n  }\n  \n  m_isInitialized = true; \n  m_factorizationIsok = true;\n  m_info = Success;\n}\n\ntemplate <typename SparseQRType, typename Derived>\nstruct SparseQR_QProduct : ReturnByValue<SparseQR_QProduct<SparseQRType, Derived> >\n{\n  typedef typename SparseQRType::QRMatrixType MatrixType;\n  typedef typename SparseQRType::Scalar Scalar;\n  // Get the references \n  SparseQR_QProduct(const SparseQRType& qr, const Derived& other, bool transpose) : \n  m_qr(qr),m_other(other),m_transpose(transpose) {}\n  inline Index rows() const { return m_transpose ? m_qr.rows() : m_qr.cols(); }\n  inline Index cols() const { return m_other.cols(); }\n  \n  // Assign to a vector\n  template<typename DesType>\n  void evalTo(DesType& res) const\n  {\n    Index m = m_qr.rows();\n    Index n = m_qr.cols();\n    Index diagSize = (std::min)(m,n);\n    res = m_other;\n    if (m_transpose)\n    {\n      eigen_assert(m_qr.m_Q.rows() == m_other.rows() && \"Non conforming object sizes\");\n      //Compute res = Q' * other column by column\n      for(Index j = 0; j < res.cols(); j++){\n        for (Index k = 0; k < diagSize; k++)\n        {\n          Scalar tau = Scalar(0);\n          tau = m_qr.m_Q.col(k).dot(res.col(j));\n          if(tau==Scalar(0)) continue;\n          tau = tau * m_qr.m_hcoeffs(k);\n          res.col(j) -= tau * m_qr.m_Q.col(k);\n        }\n      }\n    }\n    else\n    {\n      eigen_assert(m_qr.m_Q.rows() == m_other.rows() && \"Non conforming object sizes\");\n      // Compute res = Q * other column by column\n      for(Index j = 0; j < res.cols(); j++)\n      {\n        for (Index k = diagSize-1; k >=0; k--)\n        {\n          Scalar tau = Scalar(0);\n          tau = m_qr.m_Q.col(k).dot(res.col(j));\n          if(tau==Scalar(0)) continue;\n          tau = tau * m_qr.m_hcoeffs(k);\n          res.col(j) -= tau * m_qr.m_Q.col(k);\n        }\n      }\n    }\n  }\n  \n  const SparseQRType& m_qr;\n  const Derived& m_other;\n  bool m_transpose;\n};\n\ntemplate<typename SparseQRType>\nstruct SparseQRMatrixQReturnType : public EigenBase<SparseQRMatrixQReturnType<SparseQRType> >\n{  \n  typedef typename SparseQRType::Scalar Scalar;\n  typedef Matrix<Scalar,Dynamic,Dynamic> DenseMatrix;\n  enum {\n    RowsAtCompileTime = Dynamic,\n    ColsAtCompileTime = Dynamic\n  };\n  explicit SparseQRMatrixQReturnType(const SparseQRType& qr) : m_qr(qr) {}\n  template<typename Derived>\n  SparseQR_QProduct<SparseQRType, Derived> operator*(const MatrixBase<Derived>& other)\n  {\n    return SparseQR_QProduct<SparseQRType,Derived>(m_qr,other.derived(),false);\n  }\n  SparseQRMatrixQTransposeReturnType<SparseQRType> adjoint() const\n  {\n    return SparseQRMatrixQTransposeReturnType<SparseQRType>(m_qr);\n  }\n  inline Index rows() const { return m_qr.rows(); }\n  inline Index cols() const { return (std::min)(m_qr.rows(),m_qr.cols()); }\n  // To use for operations with the transpose of Q\n  SparseQRMatrixQTransposeReturnType<SparseQRType> transpose() const\n  {\n    return SparseQRMatrixQTransposeReturnType<SparseQRType>(m_qr);\n  }\n  const SparseQRType& m_qr;\n};\n\ntemplate<typename SparseQRType>\nstruct SparseQRMatrixQTransposeReturnType\n{\n  explicit SparseQRMatrixQTransposeReturnType(const SparseQRType& qr) : m_qr(qr) {}\n  template<typename Derived>\n  SparseQR_QProduct<SparseQRType,Derived> operator*(const MatrixBase<Derived>& other)\n  {\n    return SparseQR_QProduct<SparseQRType,Derived>(m_qr,other.derived(), true);\n  }\n  const SparseQRType& m_qr;\n};\n\nnamespace internal {\n  \ntemplate<typename SparseQRType>\nstruct evaluator_traits<SparseQRMatrixQReturnType<SparseQRType> >\n{\n  typedef typename SparseQRType::MatrixType MatrixType;\n  typedef typename storage_kind_to_evaluator_kind<typename MatrixType::StorageKind>::Kind Kind;\n  typedef SparseShape Shape;\n};\n\ntemplate< typename DstXprType, typename SparseQRType>\nstruct Assignment<DstXprType, SparseQRMatrixQReturnType<SparseQRType>, internal::assign_op<typename DstXprType::Scalar,typename DstXprType::Scalar>, Sparse2Sparse>\n{\n  typedef SparseQRMatrixQReturnType<SparseQRType> SrcXprType;\n  typedef typename DstXprType::Scalar Scalar;\n  typedef typename DstXprType::StorageIndex StorageIndex;\n  static void run(DstXprType &dst, const SrcXprType &src, const internal::assign_op<Scalar,Scalar> &/*func*/)\n  {\n    typename DstXprType::PlainObject idMat(src.m_qr.rows(), src.m_qr.rows());\n    idMat.setIdentity();\n    // Sort the sparse householder reflectors if needed\n    const_cast<SparseQRType *>(&src.m_qr)->_sort_matrix_Q();\n    dst = SparseQR_QProduct<SparseQRType, DstXprType>(src.m_qr, idMat, false);\n  }\n};\n\ntemplate< typename DstXprType, typename SparseQRType>\nstruct Assignment<DstXprType, SparseQRMatrixQReturnType<SparseQRType>, internal::assign_op<typename DstXprType::Scalar,typename DstXprType::Scalar>, Sparse2Dense>\n{\n  typedef SparseQRMatrixQReturnType<SparseQRType> SrcXprType;\n  typedef typename DstXprType::Scalar Scalar;\n  typedef typename DstXprType::StorageIndex StorageIndex;\n  static void run(DstXprType &dst, const SrcXprType &src, const internal::assign_op<Scalar,Scalar> &/*func*/)\n  {\n    dst = src.m_qr.matrixQ() * DstXprType::Identity(src.m_qr.rows(), src.m_qr.rows());\n  }\n};\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/StlSupport/StdDeque.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2009 Hauke Heibel <hauke.heibel@googlemail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_STDDEQUE_H\n#define EIGEN_STDDEQUE_H\n\n#include \"details.h\"\n\n/**\n * This section contains a convenience MACRO which allows an easy specialization of\n * std::deque such that for data types with alignment issues the correct allocator\n * is used automatically.\n */\n#define EIGEN_DEFINE_STL_DEQUE_SPECIALIZATION(...) \\\nnamespace std \\\n{ \\\n  template<> \\\n  class deque<__VA_ARGS__, std::allocator<__VA_ARGS__> >           \\\n    : public deque<__VA_ARGS__, EIGEN_ALIGNED_ALLOCATOR<__VA_ARGS__> > \\\n  { \\\n    typedef deque<__VA_ARGS__, EIGEN_ALIGNED_ALLOCATOR<__VA_ARGS__> > deque_base; \\\n  public: \\\n    typedef __VA_ARGS__ value_type; \\\n    typedef deque_base::allocator_type allocator_type; \\\n    typedef deque_base::size_type size_type;  \\\n    typedef deque_base::iterator iterator;  \\\n    explicit deque(const allocator_type& a = allocator_type()) : deque_base(a) {}  \\\n    template<typename InputIterator> \\\n    deque(InputIterator first, InputIterator last, const allocator_type& a = allocator_type()) : deque_base(first, last, a) {} \\\n    deque(const deque& c) : deque_base(c) {}  \\\n    explicit deque(size_type num, const value_type& val = value_type()) : deque_base(num, val) {} \\\n    deque(iterator start, iterator end) : deque_base(start, end) {}  \\\n    deque& operator=(const deque& x) {  \\\n      deque_base::operator=(x);  \\\n      return *this;  \\\n    } \\\n  }; \\\n}\n\n// check whether we really need the std::deque specialization\n#if !EIGEN_HAS_CXX11_CONTAINERS && !(defined(_GLIBCXX_DEQUE) && (!EIGEN_GNUC_AT_LEAST(4,1))) /* Note that before gcc-4.1 we already have: std::deque::resize(size_type,const T&). */\n\nnamespace std {\n\n#define EIGEN_STD_DEQUE_SPECIALIZATION_BODY \\\n  public:  \\\n    typedef T value_type; \\\n    typedef typename deque_base::allocator_type allocator_type; \\\n    typedef typename deque_base::size_type size_type;  \\\n    typedef typename deque_base::iterator iterator;  \\\n    typedef typename deque_base::const_iterator const_iterator;  \\\n    explicit deque(const allocator_type& a = allocator_type()) : deque_base(a) {}  \\\n    template<typename InputIterator> \\\n    deque(InputIterator first, InputIterator last, const allocator_type& a = allocator_type()) \\\n    : deque_base(first, last, a) {} \\\n    deque(const deque& c) : deque_base(c) {}  \\\n    explicit deque(size_type num, const value_type& val = value_type()) : deque_base(num, val) {} \\\n    deque(iterator start, iterator end) : deque_base(start, end) {}  \\\n    deque& operator=(const deque& x) {  \\\n      deque_base::operator=(x);  \\\n      return *this;  \\\n    }\n\n  template<typename T>\n  class deque<T,EIGEN_ALIGNED_ALLOCATOR<T> >\n    : public deque<EIGEN_WORKAROUND_MSVC_STL_SUPPORT(T),\n                   Eigen::aligned_allocator_indirection<EIGEN_WORKAROUND_MSVC_STL_SUPPORT(T)> >\n{\n  typedef deque<EIGEN_WORKAROUND_MSVC_STL_SUPPORT(T),\n                Eigen::aligned_allocator_indirection<EIGEN_WORKAROUND_MSVC_STL_SUPPORT(T)> > deque_base;\n  EIGEN_STD_DEQUE_SPECIALIZATION_BODY\n\n  void resize(size_type new_size)\n  { resize(new_size, T()); }\n\n#if defined(_DEQUE_)\n  // workaround MSVC std::deque implementation\n  void resize(size_type new_size, const value_type& x)\n  {\n    if (deque_base::size() < new_size)\n      deque_base::_Insert_n(deque_base::end(), new_size - deque_base::size(), x);\n    else if (new_size < deque_base::size())\n      deque_base::erase(deque_base::begin() + new_size, deque_base::end());\n  }\n  void push_back(const value_type& x)\n  { deque_base::push_back(x); } \n  void push_front(const value_type& x)\n  { deque_base::push_front(x); }\n  using deque_base::insert;  \n  iterator insert(const_iterator position, const value_type& x)\n  { return deque_base::insert(position,x); }\n  void insert(const_iterator position, size_type new_size, const value_type& x)\n  { deque_base::insert(position, new_size, x); }\n#elif defined(_GLIBCXX_DEQUE) && EIGEN_GNUC_AT_LEAST(4,2)\n  // workaround GCC std::deque implementation\n  void resize(size_type new_size, const value_type& x)\n  {\n    if (new_size < deque_base::size())\n      deque_base::_M_erase_at_end(this->_M_impl._M_start + new_size);\n    else\n      deque_base::insert(deque_base::end(), new_size - deque_base::size(), x);\n  }\n#else\n  // either GCC 4.1 or non-GCC\n  // default implementation which should always work.\n  void resize(size_type new_size, const value_type& x)\n  {\n    if (new_size < deque_base::size())\n      deque_base::erase(deque_base::begin() + new_size, deque_base::end());\n    else if (new_size > deque_base::size())\n      deque_base::insert(deque_base::end(), new_size - deque_base::size(), x);\n  }\n#endif\n  };\n}\n\n#endif // check whether specialization is actually required\n\n#endif // EIGEN_STDDEQUE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/StlSupport/StdList.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009 Hauke Heibel <hauke.heibel@googlemail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_STDLIST_H\n#define EIGEN_STDLIST_H\n\n#include \"details.h\"\n\n/**\n * This section contains a convenience MACRO which allows an easy specialization of\n * std::list such that for data types with alignment issues the correct allocator\n * is used automatically.\n */\n#define EIGEN_DEFINE_STL_LIST_SPECIALIZATION(...) \\\nnamespace std \\\n{ \\\n  template<> \\\n  class list<__VA_ARGS__, std::allocator<__VA_ARGS__> >           \\\n    : public list<__VA_ARGS__, EIGEN_ALIGNED_ALLOCATOR<__VA_ARGS__> > \\\n  { \\\n    typedef list<__VA_ARGS__, EIGEN_ALIGNED_ALLOCATOR<__VA_ARGS__> > list_base; \\\n  public: \\\n    typedef __VA_ARGS__ value_type; \\\n    typedef list_base::allocator_type allocator_type; \\\n    typedef list_base::size_type size_type;  \\\n    typedef list_base::iterator iterator;  \\\n    explicit list(const allocator_type& a = allocator_type()) : list_base(a) {}  \\\n    template<typename InputIterator> \\\n    list(InputIterator first, InputIterator last, const allocator_type& a = allocator_type()) : list_base(first, last, a) {} \\\n    list(const list& c) : list_base(c) {}  \\\n    explicit list(size_type num, const value_type& val = value_type()) : list_base(num, val) {} \\\n    list(iterator start, iterator end) : list_base(start, end) {}  \\\n    list& operator=(const list& x) {  \\\n      list_base::operator=(x);  \\\n      return *this;  \\\n    } \\\n  }; \\\n}\n\n// check whether we really need the std::list specialization\n#if !EIGEN_HAS_CXX11_CONTAINERS && !(defined(_GLIBCXX_LIST) && (!EIGEN_GNUC_AT_LEAST(4,1))) /* Note that before gcc-4.1 we already have: std::list::resize(size_type,const T&). */\n\nnamespace std\n{\n\n#define EIGEN_STD_LIST_SPECIALIZATION_BODY \\\n  public:  \\\n    typedef T value_type; \\\n    typedef typename list_base::allocator_type allocator_type; \\\n    typedef typename list_base::size_type size_type;  \\\n    typedef typename list_base::iterator iterator;  \\\n    typedef typename list_base::const_iterator const_iterator;  \\\n    explicit list(const allocator_type& a = allocator_type()) : list_base(a) {}  \\\n    template<typename InputIterator> \\\n    list(InputIterator first, InputIterator last, const allocator_type& a = allocator_type()) \\\n    : list_base(first, last, a) {} \\\n    list(const list& c) : list_base(c) {}  \\\n    explicit list(size_type num, const value_type& val = value_type()) : list_base(num, val) {} \\\n    list(iterator start, iterator end) : list_base(start, end) {}  \\\n    list& operator=(const list& x) {  \\\n    list_base::operator=(x);  \\\n    return *this; \\\n  }\n\n  template<typename T>\n  class list<T,EIGEN_ALIGNED_ALLOCATOR<T> >\n    : public list<EIGEN_WORKAROUND_MSVC_STL_SUPPORT(T),\n                  Eigen::aligned_allocator_indirection<EIGEN_WORKAROUND_MSVC_STL_SUPPORT(T)> >\n  {\n    typedef list<EIGEN_WORKAROUND_MSVC_STL_SUPPORT(T),\n                 Eigen::aligned_allocator_indirection<EIGEN_WORKAROUND_MSVC_STL_SUPPORT(T)> > list_base;\n    EIGEN_STD_LIST_SPECIALIZATION_BODY\n\n    void resize(size_type new_size)\n    { resize(new_size, T()); }\n\n    void resize(size_type new_size, const value_type& x)\n    {\n      if (list_base::size() < new_size)\n        list_base::insert(list_base::end(), new_size - list_base::size(), x);\n      else\n        while (new_size < list_base::size()) list_base::pop_back();\n    }\n\n#if defined(_LIST_)\n    // workaround MSVC std::list implementation\n    void push_back(const value_type& x)\n    { list_base::push_back(x); } \n    using list_base::insert;  \n    iterator insert(const_iterator position, const value_type& x)\n    { return list_base::insert(position,x); }\n    void insert(const_iterator position, size_type new_size, const value_type& x)\n    { list_base::insert(position, new_size, x); }\n#endif\n  };\n}\n\n#endif // check whether specialization is actually required\n\n#endif // EIGEN_STDLIST_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/StlSupport/StdVector.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2009 Hauke Heibel <hauke.heibel@googlemail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_STDVECTOR_H\n#define EIGEN_STDVECTOR_H\n\n#include \"details.h\"\n\n/**\n * This section contains a convenience MACRO which allows an easy specialization of\n * std::vector such that for data types with alignment issues the correct allocator\n * is used automatically.\n */\n#define EIGEN_DEFINE_STL_VECTOR_SPECIALIZATION(...) \\\nnamespace std \\\n{ \\\n  template<> \\\n  class vector<__VA_ARGS__, std::allocator<__VA_ARGS__> >  \\\n    : public vector<__VA_ARGS__, EIGEN_ALIGNED_ALLOCATOR<__VA_ARGS__> > \\\n  { \\\n    typedef vector<__VA_ARGS__, EIGEN_ALIGNED_ALLOCATOR<__VA_ARGS__> > vector_base; \\\n  public: \\\n    typedef __VA_ARGS__ value_type; \\\n    typedef vector_base::allocator_type allocator_type; \\\n    typedef vector_base::size_type size_type;  \\\n    typedef vector_base::iterator iterator;  \\\n    explicit vector(const allocator_type& a = allocator_type()) : vector_base(a) {}  \\\n    template<typename InputIterator> \\\n    vector(InputIterator first, InputIterator last, const allocator_type& a = allocator_type()) : vector_base(first, last, a) {} \\\n    vector(const vector& c) : vector_base(c) {}  \\\n    explicit vector(size_type num, const value_type& val = value_type()) : vector_base(num, val) {} \\\n    vector(iterator start, iterator end) : vector_base(start, end) {}  \\\n    vector& operator=(const vector& x) {  \\\n      vector_base::operator=(x);  \\\n      return *this;  \\\n    } \\\n  }; \\\n}\n\n// Don't specialize if containers are implemented according to C++11\n#if !EIGEN_HAS_CXX11_CONTAINERS\n\nnamespace std {\n\n#define EIGEN_STD_VECTOR_SPECIALIZATION_BODY \\\n  public:  \\\n    typedef T value_type; \\\n    typedef typename vector_base::allocator_type allocator_type; \\\n    typedef typename vector_base::size_type size_type;  \\\n    typedef typename vector_base::iterator iterator;  \\\n    typedef typename vector_base::const_iterator const_iterator;  \\\n    explicit vector(const allocator_type& a = allocator_type()) : vector_base(a) {}  \\\n    template<typename InputIterator> \\\n    vector(InputIterator first, InputIterator last, const allocator_type& a = allocator_type()) \\\n    : vector_base(first, last, a) {} \\\n    vector(const vector& c) : vector_base(c) {}  \\\n    explicit vector(size_type num, const value_type& val = value_type()) : vector_base(num, val) {} \\\n    vector(iterator start, iterator end) : vector_base(start, end) {}  \\\n    vector& operator=(const vector& x) {  \\\n      vector_base::operator=(x);  \\\n      return *this;  \\\n    }\n\n  template<typename T>\n  class vector<T,EIGEN_ALIGNED_ALLOCATOR<T> >\n    : public vector<EIGEN_WORKAROUND_MSVC_STL_SUPPORT(T),\n                    Eigen::aligned_allocator_indirection<EIGEN_WORKAROUND_MSVC_STL_SUPPORT(T)> >\n{\n  typedef vector<EIGEN_WORKAROUND_MSVC_STL_SUPPORT(T),\n                 Eigen::aligned_allocator_indirection<EIGEN_WORKAROUND_MSVC_STL_SUPPORT(T)> > vector_base;\n  EIGEN_STD_VECTOR_SPECIALIZATION_BODY\n\n  void resize(size_type new_size)\n  { resize(new_size, T()); }\n\n#if defined(_VECTOR_)\n  // workaround MSVC std::vector implementation\n  void resize(size_type new_size, const value_type& x)\n  {\n    if (vector_base::size() < new_size)\n      vector_base::_Insert_n(vector_base::end(), new_size - vector_base::size(), x);\n    else if (new_size < vector_base::size())\n      vector_base::erase(vector_base::begin() + new_size, vector_base::end());\n  }\n  void push_back(const value_type& x)\n  { vector_base::push_back(x); } \n  using vector_base::insert;  \n  iterator insert(const_iterator position, const value_type& x)\n  { return vector_base::insert(position,x); }\n  void insert(const_iterator position, size_type new_size, const value_type& x)\n  { vector_base::insert(position, new_size, x); }\n#elif defined(_GLIBCXX_VECTOR) && (!(EIGEN_GNUC_AT_LEAST(4,1)))\n  /* Note that before gcc-4.1 we already have: std::vector::resize(size_type,const T&).\n   * However, this specialization is still needed to make the above EIGEN_DEFINE_STL_VECTOR_SPECIALIZATION trick to work. */\n  void resize(size_type new_size, const value_type& x)\n  {\n    vector_base::resize(new_size,x);\n  }\n#elif defined(_GLIBCXX_VECTOR) && EIGEN_GNUC_AT_LEAST(4,2)\n  // workaround GCC std::vector implementation\n  void resize(size_type new_size, const value_type& x)\n  {\n    if (new_size < vector_base::size())\n      vector_base::_M_erase_at_end(this->_M_impl._M_start + new_size);\n    else\n      vector_base::insert(vector_base::end(), new_size - vector_base::size(), x);\n  }\n#else\n  // either GCC 4.1 or non-GCC\n  // default implementation which should always work.\n  void resize(size_type new_size, const value_type& x)\n  {\n    if (new_size < vector_base::size())\n      vector_base::erase(vector_base::begin() + new_size, vector_base::end());\n    else if (new_size > vector_base::size())\n      vector_base::insert(vector_base::end(), new_size - vector_base::size(), x);\n  }\n#endif\n  };\n}\n#endif // !EIGEN_HAS_CXX11_CONTAINERS\n\n\n#endif // EIGEN_STDVECTOR_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/StlSupport/details.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2009 Hauke Heibel <hauke.heibel@googlemail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_STL_DETAILS_H\n#define EIGEN_STL_DETAILS_H\n\n#ifndef EIGEN_ALIGNED_ALLOCATOR\n  #define EIGEN_ALIGNED_ALLOCATOR Eigen::aligned_allocator\n#endif\n\nnamespace Eigen {\n\n  // This one is needed to prevent reimplementing the whole std::vector.\n  template <class T>\n  class aligned_allocator_indirection : public EIGEN_ALIGNED_ALLOCATOR<T>\n  {\n  public:\n    typedef size_t    size_type;\n    typedef ptrdiff_t difference_type;\n    typedef T*        pointer;\n    typedef const T*  const_pointer;\n    typedef T&        reference;\n    typedef const T&  const_reference;\n    typedef T         value_type;\n\n    template<class U>\n    struct rebind\n    {\n      typedef aligned_allocator_indirection<U> other;\n    };\n\n    aligned_allocator_indirection() {}\n    aligned_allocator_indirection(const aligned_allocator_indirection& ) : EIGEN_ALIGNED_ALLOCATOR<T>() {}\n    aligned_allocator_indirection(const EIGEN_ALIGNED_ALLOCATOR<T>& ) {}\n    template<class U>\n    aligned_allocator_indirection(const aligned_allocator_indirection<U>& ) {}\n    template<class U>\n    aligned_allocator_indirection(const EIGEN_ALIGNED_ALLOCATOR<U>& ) {}\n    ~aligned_allocator_indirection() {}\n  };\n\n#if EIGEN_COMP_MSVC\n\n  // sometimes, MSVC detects, at compile time, that the argument x\n  // in std::vector::resize(size_t s,T x) won't be aligned and generate an error\n  // even if this function is never called. Whence this little wrapper.\n#define EIGEN_WORKAROUND_MSVC_STL_SUPPORT(T) \\\n  typename Eigen::internal::conditional< \\\n    Eigen::internal::is_arithmetic<T>::value, \\\n    T, \\\n    Eigen::internal::workaround_msvc_stl_support<T> \\\n  >::type\n\n  namespace internal {\n  template<typename T> struct workaround_msvc_stl_support : public T\n  {\n    inline workaround_msvc_stl_support() : T() {}\n    inline workaround_msvc_stl_support(const T& other) : T(other) {}\n    inline operator T& () { return *static_cast<T*>(this); }\n    inline operator const T& () const { return *static_cast<const T*>(this); }\n    template<typename OtherT>\n    inline T& operator=(const OtherT& other)\n    { T::operator=(other); return *this; }\n    inline workaround_msvc_stl_support& operator=(const workaround_msvc_stl_support& other)\n    { T::operator=(other); return *this; }\n  };\n  }\n\n#else\n\n#define EIGEN_WORKAROUND_MSVC_STL_SUPPORT(T) T\n\n#endif\n\n}\n\n#endif // EIGEN_STL_DETAILS_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/SuperLUSupport/SuperLUSupport.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2015 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_SUPERLUSUPPORT_H\n#define EIGEN_SUPERLUSUPPORT_H\n\nnamespace Eigen {\n\n#if defined(SUPERLU_MAJOR_VERSION) && (SUPERLU_MAJOR_VERSION >= 5)\n#define DECL_GSSVX(PREFIX,FLOATTYPE,KEYTYPE)\t\t\\\n    extern \"C\" {                                                                                          \\\n      extern void PREFIX##gssvx(superlu_options_t *, SuperMatrix *, int *, int *, int *,                  \\\n                                char *, FLOATTYPE *, FLOATTYPE *, SuperMatrix *, SuperMatrix *,           \\\n                                void *, int, SuperMatrix *, SuperMatrix *,                                \\\n                                FLOATTYPE *, FLOATTYPE *, FLOATTYPE *, FLOATTYPE *,                       \\\n                                GlobalLU_t *, mem_usage_t *, SuperLUStat_t *, int *);                     \\\n    }                                                                                                     \\\n    inline float SuperLU_gssvx(superlu_options_t *options, SuperMatrix *A,                                \\\n         int *perm_c, int *perm_r, int *etree, char *equed,                                               \\\n         FLOATTYPE *R, FLOATTYPE *C, SuperMatrix *L,                                                      \\\n         SuperMatrix *U, void *work, int lwork,                                                           \\\n         SuperMatrix *B, SuperMatrix *X,                                                                  \\\n         FLOATTYPE *recip_pivot_growth,                                                                   \\\n         FLOATTYPE *rcond, FLOATTYPE *ferr, FLOATTYPE *berr,                                              \\\n         SuperLUStat_t *stats, int *info, KEYTYPE) {                                                      \\\n    mem_usage_t mem_usage;                                                                                \\\n    GlobalLU_t gLU;                                                                                       \\\n    PREFIX##gssvx(options, A, perm_c, perm_r, etree, equed, R, C, L,                                      \\\n         U, work, lwork, B, X, recip_pivot_growth, rcond,                                                 \\\n         ferr, berr, &gLU, &mem_usage, stats, info);                                                      \\\n    return mem_usage.for_lu; /* bytes used by the factor storage */                                       \\\n  }\n#else // version < 5.0\n#define DECL_GSSVX(PREFIX,FLOATTYPE,KEYTYPE)\t\t\\\n    extern \"C\" {                                                                                          \\\n      extern void PREFIX##gssvx(superlu_options_t *, SuperMatrix *, int *, int *, int *,                  \\\n                                char *, FLOATTYPE *, FLOATTYPE *, SuperMatrix *, SuperMatrix *,           \\\n                                void *, int, SuperMatrix *, SuperMatrix *,                                \\\n                                FLOATTYPE *, FLOATTYPE *, FLOATTYPE *, FLOATTYPE *,                       \\\n                                mem_usage_t *, SuperLUStat_t *, int *);                                   \\\n    }                                                                                                     \\\n    inline float SuperLU_gssvx(superlu_options_t *options, SuperMatrix *A,                                \\\n         int *perm_c, int *perm_r, int *etree, char *equed,                                               \\\n         FLOATTYPE *R, FLOATTYPE *C, SuperMatrix *L,                                                      \\\n         SuperMatrix *U, void *work, int lwork,                                                           \\\n         SuperMatrix *B, SuperMatrix *X,                                                                  \\\n         FLOATTYPE *recip_pivot_growth,                                                                   \\\n         FLOATTYPE *rcond, FLOATTYPE *ferr, FLOATTYPE *berr,                                              \\\n         SuperLUStat_t *stats, int *info, KEYTYPE) {                                                      \\\n    mem_usage_t mem_usage;                                                                                \\\n    PREFIX##gssvx(options, A, perm_c, perm_r, etree, equed, R, C, L,                                      \\\n         U, work, lwork, B, X, recip_pivot_growth, rcond,                                                 \\\n         ferr, berr, &mem_usage, stats, info);                                                            \\\n    return mem_usage.for_lu; /* bytes used by the factor storage */                                       \\\n  }\n#endif\n\nDECL_GSSVX(s,float,float)\nDECL_GSSVX(c,float,std::complex<float>)\nDECL_GSSVX(d,double,double)\nDECL_GSSVX(z,double,std::complex<double>)\n\n#ifdef MILU_ALPHA\n#define EIGEN_SUPERLU_HAS_ILU\n#endif\n\n#ifdef EIGEN_SUPERLU_HAS_ILU\n\n// similarly for the incomplete factorization using gsisx\n#define DECL_GSISX(PREFIX,FLOATTYPE,KEYTYPE)                                                    \\\n    extern \"C\" {                                                                                \\\n      extern void PREFIX##gsisx(superlu_options_t *, SuperMatrix *, int *, int *, int *,        \\\n                         char *, FLOATTYPE *, FLOATTYPE *, SuperMatrix *, SuperMatrix *,        \\\n                         void *, int, SuperMatrix *, SuperMatrix *, FLOATTYPE *, FLOATTYPE *,   \\\n                         mem_usage_t *, SuperLUStat_t *, int *);                        \\\n    }                                                                                           \\\n    inline float SuperLU_gsisx(superlu_options_t *options, SuperMatrix *A,                      \\\n         int *perm_c, int *perm_r, int *etree, char *equed,                                     \\\n         FLOATTYPE *R, FLOATTYPE *C, SuperMatrix *L,                                            \\\n         SuperMatrix *U, void *work, int lwork,                                                 \\\n         SuperMatrix *B, SuperMatrix *X,                                                        \\\n         FLOATTYPE *recip_pivot_growth,                                                         \\\n         FLOATTYPE *rcond,                                                                      \\\n         SuperLUStat_t *stats, int *info, KEYTYPE) {                                            \\\n    mem_usage_t mem_usage;                                                              \\\n    PREFIX##gsisx(options, A, perm_c, perm_r, etree, equed, R, C, L,                            \\\n         U, work, lwork, B, X, recip_pivot_growth, rcond,                                       \\\n         &mem_usage, stats, info);                                                              \\\n    return mem_usage.for_lu; /* bytes used by the factor storage */                             \\\n  }\n\nDECL_GSISX(s,float,float)\nDECL_GSISX(c,float,std::complex<float>)\nDECL_GSISX(d,double,double)\nDECL_GSISX(z,double,std::complex<double>)\n\n#endif\n\ntemplate<typename MatrixType>\nstruct SluMatrixMapHelper;\n\n/** \\internal\n  *\n  * A wrapper class for SuperLU matrices. It supports only compressed sparse matrices\n  * and dense matrices. Supernodal and other fancy format are not supported by this wrapper.\n  *\n  * This wrapper class mainly aims to avoids the need of dynamic allocation of the storage structure.\n  */\nstruct SluMatrix : SuperMatrix\n{\n  SluMatrix()\n  {\n    Store = &storage;\n  }\n\n  SluMatrix(const SluMatrix& other)\n    : SuperMatrix(other)\n  {\n    Store = &storage;\n    storage = other.storage;\n  }\n\n  SluMatrix& operator=(const SluMatrix& other)\n  {\n    SuperMatrix::operator=(static_cast<const SuperMatrix&>(other));\n    Store = &storage;\n    storage = other.storage;\n    return *this;\n  }\n\n  struct\n  {\n    union {int nnz;int lda;};\n    void *values;\n    int *innerInd;\n    int *outerInd;\n  } storage;\n\n  void setStorageType(Stype_t t)\n  {\n    Stype = t;\n    if (t==SLU_NC || t==SLU_NR || t==SLU_DN)\n      Store = &storage;\n    else\n    {\n      eigen_assert(false && \"storage type not supported\");\n      Store = 0;\n    }\n  }\n\n  template<typename Scalar>\n  void setScalarType()\n  {\n    if (internal::is_same<Scalar,float>::value)\n      Dtype = SLU_S;\n    else if (internal::is_same<Scalar,double>::value)\n      Dtype = SLU_D;\n    else if (internal::is_same<Scalar,std::complex<float> >::value)\n      Dtype = SLU_C;\n    else if (internal::is_same<Scalar,std::complex<double> >::value)\n      Dtype = SLU_Z;\n    else\n    {\n      eigen_assert(false && \"Scalar type not supported by SuperLU\");\n    }\n  }\n\n  template<typename MatrixType>\n  static SluMatrix Map(MatrixBase<MatrixType>& _mat)\n  {\n    MatrixType& mat(_mat.derived());\n    eigen_assert( ((MatrixType::Flags&RowMajorBit)!=RowMajorBit) && \"row-major dense matrices are not supported by SuperLU\");\n    SluMatrix res;\n    res.setStorageType(SLU_DN);\n    res.setScalarType<typename MatrixType::Scalar>();\n    res.Mtype     = SLU_GE;\n\n    res.nrow      = internal::convert_index<int>(mat.rows());\n    res.ncol      = internal::convert_index<int>(mat.cols());\n\n    res.storage.lda       = internal::convert_index<int>(MatrixType::IsVectorAtCompileTime ? mat.size() : mat.outerStride());\n    res.storage.values    = (void*)(mat.data());\n    return res;\n  }\n\n  template<typename MatrixType>\n  static SluMatrix Map(SparseMatrixBase<MatrixType>& a_mat)\n  {\n    MatrixType &mat(a_mat.derived());\n    SluMatrix res;\n    if ((MatrixType::Flags&RowMajorBit)==RowMajorBit)\n    {\n      res.setStorageType(SLU_NR);\n      res.nrow      = internal::convert_index<int>(mat.cols());\n      res.ncol      = internal::convert_index<int>(mat.rows());\n    }\n    else\n    {\n      res.setStorageType(SLU_NC);\n      res.nrow      = internal::convert_index<int>(mat.rows());\n      res.ncol      = internal::convert_index<int>(mat.cols());\n    }\n\n    res.Mtype       = SLU_GE;\n\n    res.storage.nnz       = internal::convert_index<int>(mat.nonZeros());\n    res.storage.values    = mat.valuePtr();\n    res.storage.innerInd  = mat.innerIndexPtr();\n    res.storage.outerInd  = mat.outerIndexPtr();\n\n    res.setScalarType<typename MatrixType::Scalar>();\n\n    // FIXME the following is not very accurate\n    if (MatrixType::Flags & Upper)\n      res.Mtype = SLU_TRU;\n    if (MatrixType::Flags & Lower)\n      res.Mtype = SLU_TRL;\n\n    eigen_assert(((MatrixType::Flags & SelfAdjoint)==0) && \"SelfAdjoint matrix shape not supported by SuperLU\");\n\n    return res;\n  }\n};\n\ntemplate<typename Scalar, int Rows, int Cols, int Options, int MRows, int MCols>\nstruct SluMatrixMapHelper<Matrix<Scalar,Rows,Cols,Options,MRows,MCols> >\n{\n  typedef Matrix<Scalar,Rows,Cols,Options,MRows,MCols> MatrixType;\n  static void run(MatrixType& mat, SluMatrix& res)\n  {\n    eigen_assert( ((Options&RowMajor)!=RowMajor) && \"row-major dense matrices is not supported by SuperLU\");\n    res.setStorageType(SLU_DN);\n    res.setScalarType<Scalar>();\n    res.Mtype     = SLU_GE;\n\n    res.nrow      = mat.rows();\n    res.ncol      = mat.cols();\n\n    res.storage.lda       = mat.outerStride();\n    res.storage.values    = mat.data();\n  }\n};\n\ntemplate<typename Derived>\nstruct SluMatrixMapHelper<SparseMatrixBase<Derived> >\n{\n  typedef Derived MatrixType;\n  static void run(MatrixType& mat, SluMatrix& res)\n  {\n    if ((MatrixType::Flags&RowMajorBit)==RowMajorBit)\n    {\n      res.setStorageType(SLU_NR);\n      res.nrow      = mat.cols();\n      res.ncol      = mat.rows();\n    }\n    else\n    {\n      res.setStorageType(SLU_NC);\n      res.nrow      = mat.rows();\n      res.ncol      = mat.cols();\n    }\n\n    res.Mtype       = SLU_GE;\n\n    res.storage.nnz       = mat.nonZeros();\n    res.storage.values    = mat.valuePtr();\n    res.storage.innerInd  = mat.innerIndexPtr();\n    res.storage.outerInd  = mat.outerIndexPtr();\n\n    res.setScalarType<typename MatrixType::Scalar>();\n\n    // FIXME the following is not very accurate\n    if (MatrixType::Flags & Upper)\n      res.Mtype = SLU_TRU;\n    if (MatrixType::Flags & Lower)\n      res.Mtype = SLU_TRL;\n\n    eigen_assert(((MatrixType::Flags & SelfAdjoint)==0) && \"SelfAdjoint matrix shape not supported by SuperLU\");\n  }\n};\n\nnamespace internal {\n\ntemplate<typename MatrixType>\nSluMatrix asSluMatrix(MatrixType& mat)\n{\n  return SluMatrix::Map(mat);\n}\n\n/** View a Super LU matrix as an Eigen expression */\ntemplate<typename Scalar, int Flags, typename Index>\nMappedSparseMatrix<Scalar,Flags,Index> map_superlu(SluMatrix& sluMat)\n{\n  eigen_assert((Flags&RowMajor)==RowMajor && sluMat.Stype == SLU_NR\n         || (Flags&ColMajor)==ColMajor && sluMat.Stype == SLU_NC);\n\n  Index outerSize = (Flags&RowMajor)==RowMajor ? sluMat.ncol : sluMat.nrow;\n\n  return MappedSparseMatrix<Scalar,Flags,Index>(\n    sluMat.nrow, sluMat.ncol, sluMat.storage.outerInd[outerSize],\n    sluMat.storage.outerInd, sluMat.storage.innerInd, reinterpret_cast<Scalar*>(sluMat.storage.values) );\n}\n\n} // end namespace internal\n\n/** \\ingroup SuperLUSupport_Module\n  * \\class SuperLUBase\n  * \\brief The base class for the direct and incomplete LU factorization of SuperLU\n  */\ntemplate<typename _MatrixType, typename Derived>\nclass SuperLUBase : public SparseSolverBase<Derived>\n{\n  protected:\n    typedef SparseSolverBase<Derived> Base;\n    using Base::derived;\n    using Base::m_isInitialized;\n  public:\n    typedef _MatrixType MatrixType;\n    typedef typename MatrixType::Scalar Scalar;\n    typedef typename MatrixType::RealScalar RealScalar;\n    typedef typename MatrixType::StorageIndex StorageIndex;\n    typedef Matrix<Scalar,Dynamic,1> Vector;\n    typedef Matrix<int, 1, MatrixType::ColsAtCompileTime> IntRowVectorType;\n    typedef Matrix<int, MatrixType::RowsAtCompileTime, 1> IntColVectorType;    \n    typedef Map<PermutationMatrix<Dynamic,Dynamic,int> > PermutationMap;\n    typedef SparseMatrix<Scalar> LUMatrixType;\n    enum {\n      ColsAtCompileTime = MatrixType::ColsAtCompileTime,\n      MaxColsAtCompileTime = MatrixType::MaxColsAtCompileTime\n    };\n\n  public:\n\n    SuperLUBase() {}\n\n    ~SuperLUBase()\n    {\n      clearFactors();\n    }\n    \n    inline Index rows() const { return m_matrix.rows(); }\n    inline Index cols() const { return m_matrix.cols(); }\n    \n    /** \\returns a reference to the Super LU option object to configure the  Super LU algorithms. */\n    inline superlu_options_t& options() { return m_sluOptions; }\n    \n    /** \\brief Reports whether previous computation was successful.\n      *\n      * \\returns \\c Success if computation was succesful,\n      *          \\c NumericalIssue if the matrix.appears to be negative.\n      */\n    ComputationInfo info() const\n    {\n      eigen_assert(m_isInitialized && \"Decomposition is not initialized.\");\n      return m_info;\n    }\n\n    /** Computes the sparse Cholesky decomposition of \\a matrix */\n    void compute(const MatrixType& matrix)\n    {\n      derived().analyzePattern(matrix);\n      derived().factorize(matrix);\n    }\n\n    /** Performs a symbolic decomposition on the sparcity of \\a matrix.\n      *\n      * This function is particularly useful when solving for several problems having the same structure.\n      * \n      * \\sa factorize()\n      */\n    void analyzePattern(const MatrixType& /*matrix*/)\n    {\n      m_isInitialized = true;\n      m_info = Success;\n      m_analysisIsOk = true;\n      m_factorizationIsOk = false;\n    }\n    \n    template<typename Stream>\n    void dumpMemory(Stream& /*s*/)\n    {}\n    \n  protected:\n    \n    void initFactorization(const MatrixType& a)\n    {\n      set_default_options(&this->m_sluOptions);\n      \n      const Index size = a.rows();\n      m_matrix = a;\n\n      m_sluA = internal::asSluMatrix(m_matrix);\n      clearFactors();\n\n      m_p.resize(size);\n      m_q.resize(size);\n      m_sluRscale.resize(size);\n      m_sluCscale.resize(size);\n      m_sluEtree.resize(size);\n\n      // set empty B and X\n      m_sluB.setStorageType(SLU_DN);\n      m_sluB.setScalarType<Scalar>();\n      m_sluB.Mtype          = SLU_GE;\n      m_sluB.storage.values = 0;\n      m_sluB.nrow           = 0;\n      m_sluB.ncol           = 0;\n      m_sluB.storage.lda    = internal::convert_index<int>(size);\n      m_sluX                = m_sluB;\n      \n      m_extractedDataAreDirty = true;\n    }\n    \n    void init()\n    {\n      m_info = InvalidInput;\n      m_isInitialized = false;\n      m_sluL.Store = 0;\n      m_sluU.Store = 0;\n    }\n    \n    void extractData() const;\n\n    void clearFactors()\n    {\n      if(m_sluL.Store)\n        Destroy_SuperNode_Matrix(&m_sluL);\n      if(m_sluU.Store)\n        Destroy_CompCol_Matrix(&m_sluU);\n\n      m_sluL.Store = 0;\n      m_sluU.Store = 0;\n\n      memset(&m_sluL,0,sizeof m_sluL);\n      memset(&m_sluU,0,sizeof m_sluU);\n    }\n\n    // cached data to reduce reallocation, etc.\n    mutable LUMatrixType m_l;\n    mutable LUMatrixType m_u;\n    mutable IntColVectorType m_p;\n    mutable IntRowVectorType m_q;\n\n    mutable LUMatrixType m_matrix;  // copy of the factorized matrix\n    mutable SluMatrix m_sluA;\n    mutable SuperMatrix m_sluL, m_sluU;\n    mutable SluMatrix m_sluB, m_sluX;\n    mutable SuperLUStat_t m_sluStat;\n    mutable superlu_options_t m_sluOptions;\n    mutable std::vector<int> m_sluEtree;\n    mutable Matrix<RealScalar,Dynamic,1> m_sluRscale, m_sluCscale;\n    mutable Matrix<RealScalar,Dynamic,1> m_sluFerr, m_sluBerr;\n    mutable char m_sluEqued;\n\n    mutable ComputationInfo m_info;\n    int m_factorizationIsOk;\n    int m_analysisIsOk;\n    mutable bool m_extractedDataAreDirty;\n    \n  private:\n    SuperLUBase(SuperLUBase& ) { }\n};\n\n\n/** \\ingroup SuperLUSupport_Module\n  * \\class SuperLU\n  * \\brief A sparse direct LU factorization and solver based on the SuperLU library\n  *\n  * This class allows to solve for A.X = B sparse linear problems via a direct LU factorization\n  * using the SuperLU library. The sparse matrix A must be squared and invertible. The vectors or matrices\n  * X and B can be either dense or sparse.\n  *\n  * \\tparam _MatrixType the type of the sparse matrix A, it must be a SparseMatrix<>\n  *\n  * \\warning This class is only for the 4.x versions of SuperLU. The 3.x and 5.x versions are not supported.\n  *\n  * \\implsparsesolverconcept\n  *\n  * \\sa \\ref TutorialSparseSolverConcept, class SparseLU\n  */\ntemplate<typename _MatrixType>\nclass SuperLU : public SuperLUBase<_MatrixType,SuperLU<_MatrixType> >\n{\n  public:\n    typedef SuperLUBase<_MatrixType,SuperLU> Base;\n    typedef _MatrixType MatrixType;\n    typedef typename Base::Scalar Scalar;\n    typedef typename Base::RealScalar RealScalar;\n    typedef typename Base::StorageIndex StorageIndex;\n    typedef typename Base::IntRowVectorType IntRowVectorType;\n    typedef typename Base::IntColVectorType IntColVectorType;   \n    typedef typename Base::PermutationMap PermutationMap;\n    typedef typename Base::LUMatrixType LUMatrixType;\n    typedef TriangularView<LUMatrixType, Lower|UnitDiag>  LMatrixType;\n    typedef TriangularView<LUMatrixType,  Upper>          UMatrixType;\n\n  public:\n    using Base::_solve_impl;\n\n    SuperLU() : Base() { init(); }\n\n    explicit SuperLU(const MatrixType& matrix) : Base()\n    {\n      init();\n      Base::compute(matrix);\n    }\n\n    ~SuperLU()\n    {\n    }\n    \n    /** Performs a symbolic decomposition on the sparcity of \\a matrix.\n      *\n      * This function is particularly useful when solving for several problems having the same structure.\n      * \n      * \\sa factorize()\n      */\n    void analyzePattern(const MatrixType& matrix)\n    {\n      m_info = InvalidInput;\n      m_isInitialized = false;\n      Base::analyzePattern(matrix);\n    }\n    \n    /** Performs a numeric decomposition of \\a matrix\n      *\n      * The given matrix must has the same sparcity than the matrix on which the symbolic decomposition has been performed.\n      *\n      * \\sa analyzePattern()\n      */\n    void factorize(const MatrixType& matrix);\n    \n    /** \\internal */\n    template<typename Rhs,typename Dest>\n    void _solve_impl(const MatrixBase<Rhs> &b, MatrixBase<Dest> &dest) const;\n    \n    inline const LMatrixType& matrixL() const\n    {\n      if (m_extractedDataAreDirty) this->extractData();\n      return m_l;\n    }\n\n    inline const UMatrixType& matrixU() const\n    {\n      if (m_extractedDataAreDirty) this->extractData();\n      return m_u;\n    }\n\n    inline const IntColVectorType& permutationP() const\n    {\n      if (m_extractedDataAreDirty) this->extractData();\n      return m_p;\n    }\n\n    inline const IntRowVectorType& permutationQ() const\n    {\n      if (m_extractedDataAreDirty) this->extractData();\n      return m_q;\n    }\n    \n    Scalar determinant() const;\n    \n  protected:\n    \n    using Base::m_matrix;\n    using Base::m_sluOptions;\n    using Base::m_sluA;\n    using Base::m_sluB;\n    using Base::m_sluX;\n    using Base::m_p;\n    using Base::m_q;\n    using Base::m_sluEtree;\n    using Base::m_sluEqued;\n    using Base::m_sluRscale;\n    using Base::m_sluCscale;\n    using Base::m_sluL;\n    using Base::m_sluU;\n    using Base::m_sluStat;\n    using Base::m_sluFerr;\n    using Base::m_sluBerr;\n    using Base::m_l;\n    using Base::m_u;\n    \n    using Base::m_analysisIsOk;\n    using Base::m_factorizationIsOk;\n    using Base::m_extractedDataAreDirty;\n    using Base::m_isInitialized;\n    using Base::m_info;\n    \n    void init()\n    {\n      Base::init();\n      \n      set_default_options(&this->m_sluOptions);\n      m_sluOptions.PrintStat        = NO;\n      m_sluOptions.ConditionNumber  = NO;\n      m_sluOptions.Trans            = NOTRANS;\n      m_sluOptions.ColPerm          = COLAMD;\n    }\n    \n    \n  private:\n    SuperLU(SuperLU& ) { }\n};\n\ntemplate<typename MatrixType>\nvoid SuperLU<MatrixType>::factorize(const MatrixType& a)\n{\n  eigen_assert(m_analysisIsOk && \"You must first call analyzePattern()\");\n  if(!m_analysisIsOk)\n  {\n    m_info = InvalidInput;\n    return;\n  }\n  \n  this->initFactorization(a);\n  \n  m_sluOptions.ColPerm = COLAMD;\n  int info = 0;\n  RealScalar recip_pivot_growth, rcond;\n  RealScalar ferr, berr;\n\n  StatInit(&m_sluStat);\n  SuperLU_gssvx(&m_sluOptions, &m_sluA, m_q.data(), m_p.data(), &m_sluEtree[0],\n                &m_sluEqued, &m_sluRscale[0], &m_sluCscale[0],\n                &m_sluL, &m_sluU,\n                NULL, 0,\n                &m_sluB, &m_sluX,\n                &recip_pivot_growth, &rcond,\n                &ferr, &berr,\n                &m_sluStat, &info, Scalar());\n  StatFree(&m_sluStat);\n\n  m_extractedDataAreDirty = true;\n\n  // FIXME how to better check for errors ???\n  m_info = info == 0 ? Success : NumericalIssue;\n  m_factorizationIsOk = true;\n}\n\ntemplate<typename MatrixType>\ntemplate<typename Rhs,typename Dest>\nvoid SuperLU<MatrixType>::_solve_impl(const MatrixBase<Rhs> &b, MatrixBase<Dest>& x) const\n{\n  eigen_assert(m_factorizationIsOk && \"The decomposition is not in a valid state for solving, you must first call either compute() or analyzePattern()/factorize()\");\n\n  const Index size = m_matrix.rows();\n  const Index rhsCols = b.cols();\n  eigen_assert(size==b.rows());\n\n  m_sluOptions.Trans = NOTRANS;\n  m_sluOptions.Fact = FACTORED;\n  m_sluOptions.IterRefine = NOREFINE;\n  \n\n  m_sluFerr.resize(rhsCols);\n  m_sluBerr.resize(rhsCols);\n  \n  Ref<const Matrix<typename Rhs::Scalar,Dynamic,Dynamic,ColMajor> > b_ref(b);\n  Ref<const Matrix<typename Dest::Scalar,Dynamic,Dynamic,ColMajor> > x_ref(x);\n  \n  m_sluB = SluMatrix::Map(b_ref.const_cast_derived());\n  m_sluX = SluMatrix::Map(x_ref.const_cast_derived());\n  \n  typename Rhs::PlainObject b_cpy;\n  if(m_sluEqued!='N')\n  {\n    b_cpy = b;\n    m_sluB = SluMatrix::Map(b_cpy.const_cast_derived());  \n  }\n\n  StatInit(&m_sluStat);\n  int info = 0;\n  RealScalar recip_pivot_growth, rcond;\n  SuperLU_gssvx(&m_sluOptions, &m_sluA,\n                m_q.data(), m_p.data(),\n                &m_sluEtree[0], &m_sluEqued,\n                &m_sluRscale[0], &m_sluCscale[0],\n                &m_sluL, &m_sluU,\n                NULL, 0,\n                &m_sluB, &m_sluX,\n                &recip_pivot_growth, &rcond,\n                &m_sluFerr[0], &m_sluBerr[0],\n                &m_sluStat, &info, Scalar());\n  StatFree(&m_sluStat);\n  \n  if(x.derived().data() != x_ref.data())\n    x = x_ref;\n  \n  m_info = info==0 ? Success : NumericalIssue;\n}\n\n// the code of this extractData() function has been adapted from the SuperLU's Matlab support code,\n//\n//  Copyright (c) 1994 by Xerox Corporation.  All rights reserved.\n//\n//  THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY\n//  EXPRESSED OR IMPLIED.  ANY USE IS AT YOUR OWN RISK.\n//\ntemplate<typename MatrixType, typename Derived>\nvoid SuperLUBase<MatrixType,Derived>::extractData() const\n{\n  eigen_assert(m_factorizationIsOk && \"The decomposition is not in a valid state for extracting factors, you must first call either compute() or analyzePattern()/factorize()\");\n  if (m_extractedDataAreDirty)\n  {\n    int         upper;\n    int         fsupc, istart, nsupr;\n    int         lastl = 0, lastu = 0;\n    SCformat    *Lstore = static_cast<SCformat*>(m_sluL.Store);\n    NCformat    *Ustore = static_cast<NCformat*>(m_sluU.Store);\n    Scalar      *SNptr;\n\n    const Index size = m_matrix.rows();\n    m_l.resize(size,size);\n    m_l.resizeNonZeros(Lstore->nnz);\n    m_u.resize(size,size);\n    m_u.resizeNonZeros(Ustore->nnz);\n\n    int* Lcol = m_l.outerIndexPtr();\n    int* Lrow = m_l.innerIndexPtr();\n    Scalar* Lval = m_l.valuePtr();\n\n    int* Ucol = m_u.outerIndexPtr();\n    int* Urow = m_u.innerIndexPtr();\n    Scalar* Uval = m_u.valuePtr();\n\n    Ucol[0] = 0;\n    Ucol[0] = 0;\n\n    /* for each supernode */\n    for (int k = 0; k <= Lstore->nsuper; ++k)\n    {\n      fsupc   = L_FST_SUPC(k);\n      istart  = L_SUB_START(fsupc);\n      nsupr   = L_SUB_START(fsupc+1) - istart;\n      upper   = 1;\n\n      /* for each column in the supernode */\n      for (int j = fsupc; j < L_FST_SUPC(k+1); ++j)\n      {\n        SNptr = &((Scalar*)Lstore->nzval)[L_NZ_START(j)];\n\n        /* Extract U */\n        for (int i = U_NZ_START(j); i < U_NZ_START(j+1); ++i)\n        {\n          Uval[lastu] = ((Scalar*)Ustore->nzval)[i];\n          /* Matlab doesn't like explicit zero. */\n          if (Uval[lastu] != 0.0)\n            Urow[lastu++] = U_SUB(i);\n        }\n        for (int i = 0; i < upper; ++i)\n        {\n          /* upper triangle in the supernode */\n          Uval[lastu] = SNptr[i];\n          /* Matlab doesn't like explicit zero. */\n          if (Uval[lastu] != 0.0)\n            Urow[lastu++] = L_SUB(istart+i);\n        }\n        Ucol[j+1] = lastu;\n\n        /* Extract L */\n        Lval[lastl] = 1.0; /* unit diagonal */\n        Lrow[lastl++] = L_SUB(istart + upper - 1);\n        for (int i = upper; i < nsupr; ++i)\n        {\n          Lval[lastl] = SNptr[i];\n          /* Matlab doesn't like explicit zero. */\n          if (Lval[lastl] != 0.0)\n            Lrow[lastl++] = L_SUB(istart+i);\n        }\n        Lcol[j+1] = lastl;\n\n        ++upper;\n      } /* for j ... */\n\n    } /* for k ... */\n\n    // squeeze the matrices :\n    m_l.resizeNonZeros(lastl);\n    m_u.resizeNonZeros(lastu);\n\n    m_extractedDataAreDirty = false;\n  }\n}\n\ntemplate<typename MatrixType>\ntypename SuperLU<MatrixType>::Scalar SuperLU<MatrixType>::determinant() const\n{\n  eigen_assert(m_factorizationIsOk && \"The decomposition is not in a valid state for computing the determinant, you must first call either compute() or analyzePattern()/factorize()\");\n  \n  if (m_extractedDataAreDirty)\n    this->extractData();\n\n  Scalar det = Scalar(1);\n  for (int j=0; j<m_u.cols(); ++j)\n  {\n    if (m_u.outerIndexPtr()[j+1]-m_u.outerIndexPtr()[j] > 0)\n    {\n      int lastId = m_u.outerIndexPtr()[j+1]-1;\n      eigen_assert(m_u.innerIndexPtr()[lastId]<=j);\n      if (m_u.innerIndexPtr()[lastId]==j)\n        det *= m_u.valuePtr()[lastId];\n    }\n  }\n  if(PermutationMap(m_p.data(),m_p.size()).determinant()*PermutationMap(m_q.data(),m_q.size()).determinant()<0)\n    det = -det;\n  if(m_sluEqued!='N')\n    return det/m_sluRscale.prod()/m_sluCscale.prod();\n  else\n    return det;\n}\n\n#ifdef EIGEN_PARSED_BY_DOXYGEN\n#define EIGEN_SUPERLU_HAS_ILU\n#endif\n\n#ifdef EIGEN_SUPERLU_HAS_ILU\n\n/** \\ingroup SuperLUSupport_Module\n  * \\class SuperILU\n  * \\brief A sparse direct \\b incomplete LU factorization and solver based on the SuperLU library\n  *\n  * This class allows to solve for an approximate solution of A.X = B sparse linear problems via an incomplete LU factorization\n  * using the SuperLU library. This class is aimed to be used as a preconditioner of the iterative linear solvers.\n  *\n  * \\warning This class is only for the 4.x versions of SuperLU. The 3.x and 5.x versions are not supported.\n  *\n  * \\tparam _MatrixType the type of the sparse matrix A, it must be a SparseMatrix<>\n  *\n  * \\implsparsesolverconcept\n  *\n  * \\sa \\ref TutorialSparseSolverConcept, class IncompleteLUT, class ConjugateGradient, class BiCGSTAB\n  */\n\ntemplate<typename _MatrixType>\nclass SuperILU : public SuperLUBase<_MatrixType,SuperILU<_MatrixType> >\n{\n  public:\n    typedef SuperLUBase<_MatrixType,SuperILU> Base;\n    typedef _MatrixType MatrixType;\n    typedef typename Base::Scalar Scalar;\n    typedef typename Base::RealScalar RealScalar;\n\n  public:\n    using Base::_solve_impl;\n\n    SuperILU() : Base() { init(); }\n\n    SuperILU(const MatrixType& matrix) : Base()\n    {\n      init();\n      Base::compute(matrix);\n    }\n\n    ~SuperILU()\n    {\n    }\n    \n    /** Performs a symbolic decomposition on the sparcity of \\a matrix.\n      *\n      * This function is particularly useful when solving for several problems having the same structure.\n      * \n      * \\sa factorize()\n      */\n    void analyzePattern(const MatrixType& matrix)\n    {\n      Base::analyzePattern(matrix);\n    }\n    \n    /** Performs a numeric decomposition of \\a matrix\n      *\n      * The given matrix must has the same sparcity than the matrix on which the symbolic decomposition has been performed.\n      *\n      * \\sa analyzePattern()\n      */\n    void factorize(const MatrixType& matrix);\n    \n    #ifndef EIGEN_PARSED_BY_DOXYGEN\n    /** \\internal */\n    template<typename Rhs,typename Dest>\n    void _solve_impl(const MatrixBase<Rhs> &b, MatrixBase<Dest> &dest) const;\n    #endif // EIGEN_PARSED_BY_DOXYGEN\n    \n  protected:\n    \n    using Base::m_matrix;\n    using Base::m_sluOptions;\n    using Base::m_sluA;\n    using Base::m_sluB;\n    using Base::m_sluX;\n    using Base::m_p;\n    using Base::m_q;\n    using Base::m_sluEtree;\n    using Base::m_sluEqued;\n    using Base::m_sluRscale;\n    using Base::m_sluCscale;\n    using Base::m_sluL;\n    using Base::m_sluU;\n    using Base::m_sluStat;\n    using Base::m_sluFerr;\n    using Base::m_sluBerr;\n    using Base::m_l;\n    using Base::m_u;\n    \n    using Base::m_analysisIsOk;\n    using Base::m_factorizationIsOk;\n    using Base::m_extractedDataAreDirty;\n    using Base::m_isInitialized;\n    using Base::m_info;\n\n    void init()\n    {\n      Base::init();\n      \n      ilu_set_default_options(&m_sluOptions);\n      m_sluOptions.PrintStat        = NO;\n      m_sluOptions.ConditionNumber  = NO;\n      m_sluOptions.Trans            = NOTRANS;\n      m_sluOptions.ColPerm          = MMD_AT_PLUS_A;\n      \n      // no attempt to preserve column sum\n      m_sluOptions.ILU_MILU = SILU;\n      // only basic ILU(k) support -- no direct control over memory consumption\n      // better to use ILU_DropRule = DROP_BASIC | DROP_AREA\n      // and set ILU_FillFactor to max memory growth\n      m_sluOptions.ILU_DropRule = DROP_BASIC;\n      m_sluOptions.ILU_DropTol = NumTraits<Scalar>::dummy_precision()*10;\n    }\n    \n  private:\n    SuperILU(SuperILU& ) { }\n};\n\ntemplate<typename MatrixType>\nvoid SuperILU<MatrixType>::factorize(const MatrixType& a)\n{\n  eigen_assert(m_analysisIsOk && \"You must first call analyzePattern()\");\n  if(!m_analysisIsOk)\n  {\n    m_info = InvalidInput;\n    return;\n  }\n  \n  this->initFactorization(a);\n\n  int info = 0;\n  RealScalar recip_pivot_growth, rcond;\n\n  StatInit(&m_sluStat);\n  SuperLU_gsisx(&m_sluOptions, &m_sluA, m_q.data(), m_p.data(), &m_sluEtree[0],\n                &m_sluEqued, &m_sluRscale[0], &m_sluCscale[0],\n                &m_sluL, &m_sluU,\n                NULL, 0,\n                &m_sluB, &m_sluX,\n                &recip_pivot_growth, &rcond,\n                &m_sluStat, &info, Scalar());\n  StatFree(&m_sluStat);\n\n  // FIXME how to better check for errors ???\n  m_info = info == 0 ? Success : NumericalIssue;\n  m_factorizationIsOk = true;\n}\n\ntemplate<typename MatrixType>\ntemplate<typename Rhs,typename Dest>\nvoid SuperILU<MatrixType>::_solve_impl(const MatrixBase<Rhs> &b, MatrixBase<Dest>& x) const\n{\n  eigen_assert(m_factorizationIsOk && \"The decomposition is not in a valid state for solving, you must first call either compute() or analyzePattern()/factorize()\");\n\n  const int size = m_matrix.rows();\n  const int rhsCols = b.cols();\n  eigen_assert(size==b.rows());\n\n  m_sluOptions.Trans = NOTRANS;\n  m_sluOptions.Fact = FACTORED;\n  m_sluOptions.IterRefine = NOREFINE;\n\n  m_sluFerr.resize(rhsCols);\n  m_sluBerr.resize(rhsCols);\n  \n  Ref<const Matrix<typename Rhs::Scalar,Dynamic,Dynamic,ColMajor> > b_ref(b);\n  Ref<const Matrix<typename Dest::Scalar,Dynamic,Dynamic,ColMajor> > x_ref(x);\n  \n  m_sluB = SluMatrix::Map(b_ref.const_cast_derived());\n  m_sluX = SluMatrix::Map(x_ref.const_cast_derived());\n\n  typename Rhs::PlainObject b_cpy;\n  if(m_sluEqued!='N')\n  {\n    b_cpy = b;\n    m_sluB = SluMatrix::Map(b_cpy.const_cast_derived());  \n  }\n  \n  int info = 0;\n  RealScalar recip_pivot_growth, rcond;\n\n  StatInit(&m_sluStat);\n  SuperLU_gsisx(&m_sluOptions, &m_sluA,\n                m_q.data(), m_p.data(),\n                &m_sluEtree[0], &m_sluEqued,\n                &m_sluRscale[0], &m_sluCscale[0],\n                &m_sluL, &m_sluU,\n                NULL, 0,\n                &m_sluB, &m_sluX,\n                &recip_pivot_growth, &rcond,\n                &m_sluStat, &info, Scalar());\n  StatFree(&m_sluStat);\n  \n  if(x.derived().data() != x_ref.data())\n    x = x_ref;\n\n  m_info = info==0 ? Success : NumericalIssue;\n}\n#endif\n\n} // end namespace Eigen\n\n#endif // EIGEN_SUPERLUSUPPORT_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/UmfPackSupport/UmfPackSupport.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2011 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_UMFPACKSUPPORT_H\n#define EIGEN_UMFPACKSUPPORT_H\n\nnamespace Eigen { \n\n/* TODO extract L, extract U, compute det, etc... */\n\n// generic double/complex<double> wrapper functions:\n\n\ninline void umfpack_defaults(double control[UMFPACK_CONTROL], double) \n{ umfpack_di_defaults(control); }\n\ninline void umfpack_defaults(double control[UMFPACK_CONTROL], std::complex<double>) \n{ umfpack_zi_defaults(control); }\n\ninline void umfpack_free_numeric(void **Numeric, double)\n{ umfpack_di_free_numeric(Numeric); *Numeric = 0; }\n\ninline void umfpack_free_numeric(void **Numeric, std::complex<double>)\n{ umfpack_zi_free_numeric(Numeric); *Numeric = 0; }\n\ninline void umfpack_free_symbolic(void **Symbolic, double)\n{ umfpack_di_free_symbolic(Symbolic); *Symbolic = 0; }\n\ninline void umfpack_free_symbolic(void **Symbolic, std::complex<double>)\n{ umfpack_zi_free_symbolic(Symbolic); *Symbolic = 0; }\n\ninline int umfpack_symbolic(int n_row,int n_col,\n                            const int Ap[], const int Ai[], const double Ax[], void **Symbolic,\n                            const double Control [UMFPACK_CONTROL], double Info [UMFPACK_INFO])\n{\n  return umfpack_di_symbolic(n_row,n_col,Ap,Ai,Ax,Symbolic,Control,Info);\n}\n\ninline int umfpack_symbolic(int n_row,int n_col,\n                            const int Ap[], const int Ai[], const std::complex<double> Ax[], void **Symbolic,\n                            const double Control [UMFPACK_CONTROL], double Info [UMFPACK_INFO])\n{\n  return umfpack_zi_symbolic(n_row,n_col,Ap,Ai,&numext::real_ref(Ax[0]),0,Symbolic,Control,Info);\n}\n\ninline int umfpack_numeric( const int Ap[], const int Ai[], const double Ax[],\n                            void *Symbolic, void **Numeric,\n                            const double Control[UMFPACK_CONTROL],double Info [UMFPACK_INFO])\n{\n  return umfpack_di_numeric(Ap,Ai,Ax,Symbolic,Numeric,Control,Info);\n}\n\ninline int umfpack_numeric( const int Ap[], const int Ai[], const std::complex<double> Ax[],\n                            void *Symbolic, void **Numeric,\n                            const double Control[UMFPACK_CONTROL],double Info [UMFPACK_INFO])\n{\n  return umfpack_zi_numeric(Ap,Ai,&numext::real_ref(Ax[0]),0,Symbolic,Numeric,Control,Info);\n}\n\ninline int umfpack_solve( int sys, const int Ap[], const int Ai[], const double Ax[],\n                          double X[], const double B[], void *Numeric,\n                          const double Control[UMFPACK_CONTROL], double Info[UMFPACK_INFO])\n{\n  return umfpack_di_solve(sys,Ap,Ai,Ax,X,B,Numeric,Control,Info);\n}\n\ninline int umfpack_solve( int sys, const int Ap[], const int Ai[], const std::complex<double> Ax[],\n                          std::complex<double> X[], const std::complex<double> B[], void *Numeric,\n                          const double Control[UMFPACK_CONTROL], double Info[UMFPACK_INFO])\n{\n  return umfpack_zi_solve(sys,Ap,Ai,&numext::real_ref(Ax[0]),0,&numext::real_ref(X[0]),0,&numext::real_ref(B[0]),0,Numeric,Control,Info);\n}\n\ninline int umfpack_get_lunz(int *lnz, int *unz, int *n_row, int *n_col, int *nz_udiag, void *Numeric, double)\n{\n  return umfpack_di_get_lunz(lnz,unz,n_row,n_col,nz_udiag,Numeric);\n}\n\ninline int umfpack_get_lunz(int *lnz, int *unz, int *n_row, int *n_col, int *nz_udiag, void *Numeric, std::complex<double>)\n{\n  return umfpack_zi_get_lunz(lnz,unz,n_row,n_col,nz_udiag,Numeric);\n}\n\ninline int umfpack_get_numeric(int Lp[], int Lj[], double Lx[], int Up[], int Ui[], double Ux[],\n                               int P[], int Q[], double Dx[], int *do_recip, double Rs[], void *Numeric)\n{\n  return umfpack_di_get_numeric(Lp,Lj,Lx,Up,Ui,Ux,P,Q,Dx,do_recip,Rs,Numeric);\n}\n\ninline int umfpack_get_numeric(int Lp[], int Lj[], std::complex<double> Lx[], int Up[], int Ui[], std::complex<double> Ux[],\n                               int P[], int Q[], std::complex<double> Dx[], int *do_recip, double Rs[], void *Numeric)\n{\n  double& lx0_real = numext::real_ref(Lx[0]);\n  double& ux0_real = numext::real_ref(Ux[0]);\n  double& dx0_real = numext::real_ref(Dx[0]);\n  return umfpack_zi_get_numeric(Lp,Lj,Lx?&lx0_real:0,0,Up,Ui,Ux?&ux0_real:0,0,P,Q,\n                                Dx?&dx0_real:0,0,do_recip,Rs,Numeric);\n}\n\ninline int umfpack_get_determinant(double *Mx, double *Ex, void *NumericHandle, double User_Info [UMFPACK_INFO])\n{\n  return umfpack_di_get_determinant(Mx,Ex,NumericHandle,User_Info);\n}\n\ninline int umfpack_get_determinant(std::complex<double> *Mx, double *Ex, void *NumericHandle, double User_Info [UMFPACK_INFO])\n{\n  double& mx_real = numext::real_ref(*Mx);\n  return umfpack_zi_get_determinant(&mx_real,0,Ex,NumericHandle,User_Info);\n}\n\n\n/** \\ingroup UmfPackSupport_Module\n  * \\brief A sparse LU factorization and solver based on UmfPack\n  *\n  * This class allows to solve for A.X = B sparse linear problems via a LU factorization\n  * using the UmfPack library. The sparse matrix A must be squared and full rank.\n  * The vectors or matrices X and B can be either dense or sparse.\n  *\n  * \\warning The input matrix A should be in a \\b compressed and \\b column-major form.\n  * Otherwise an expensive copy will be made. You can call the inexpensive makeCompressed() to get a compressed matrix.\n  * \\tparam _MatrixType the type of the sparse matrix A, it must be a SparseMatrix<>\n  *\n  * \\implsparsesolverconcept\n  *\n  * \\sa \\ref TutorialSparseSolverConcept, class SparseLU\n  */\ntemplate<typename _MatrixType>\nclass UmfPackLU : public SparseSolverBase<UmfPackLU<_MatrixType> >\n{\n  protected:\n    typedef SparseSolverBase<UmfPackLU<_MatrixType> > Base;\n    using Base::m_isInitialized;\n  public:\n    using Base::_solve_impl;\n    typedef _MatrixType MatrixType;\n    typedef typename MatrixType::Scalar Scalar;\n    typedef typename MatrixType::RealScalar RealScalar;\n    typedef typename MatrixType::StorageIndex StorageIndex;\n    typedef Matrix<Scalar,Dynamic,1> Vector;\n    typedef Matrix<int, 1, MatrixType::ColsAtCompileTime> IntRowVectorType;\n    typedef Matrix<int, MatrixType::RowsAtCompileTime, 1> IntColVectorType;\n    typedef SparseMatrix<Scalar> LUMatrixType;\n    typedef SparseMatrix<Scalar,ColMajor,int> UmfpackMatrixType;\n    typedef Ref<const UmfpackMatrixType, StandardCompressedFormat> UmfpackMatrixRef;\n    enum {\n      ColsAtCompileTime = MatrixType::ColsAtCompileTime,\n      MaxColsAtCompileTime = MatrixType::MaxColsAtCompileTime\n    };\n\n  public:\n\n    typedef Array<double, UMFPACK_CONTROL, 1> UmfpackControl;\n\n    UmfPackLU()\n      : m_dummy(0,0), mp_matrix(m_dummy)\n    {\n      init();\n    }\n\n    template<typename InputMatrixType>\n    explicit UmfPackLU(const InputMatrixType& matrix)\n      : mp_matrix(matrix)\n    {\n      init();\n      compute(matrix);\n    }\n\n    ~UmfPackLU()\n    {\n      if(m_symbolic) umfpack_free_symbolic(&m_symbolic,Scalar());\n      if(m_numeric)  umfpack_free_numeric(&m_numeric,Scalar());\n    }\n\n    inline Index rows() const { return mp_matrix.rows(); }\n    inline Index cols() const { return mp_matrix.cols(); }\n\n    /** \\brief Reports whether previous computation was successful.\n      *\n      * \\returns \\c Success if computation was succesful,\n      *          \\c NumericalIssue if the matrix.appears to be negative.\n      */\n    ComputationInfo info() const\n    {\n      eigen_assert(m_isInitialized && \"Decomposition is not initialized.\");\n      return m_info;\n    }\n\n    inline const LUMatrixType& matrixL() const\n    {\n      if (m_extractedDataAreDirty) extractData();\n      return m_l;\n    }\n\n    inline const LUMatrixType& matrixU() const\n    {\n      if (m_extractedDataAreDirty) extractData();\n      return m_u;\n    }\n\n    inline const IntColVectorType& permutationP() const\n    {\n      if (m_extractedDataAreDirty) extractData();\n      return m_p;\n    }\n\n    inline const IntRowVectorType& permutationQ() const\n    {\n      if (m_extractedDataAreDirty) extractData();\n      return m_q;\n    }\n\n    /** Computes the sparse Cholesky decomposition of \\a matrix \n     *  Note that the matrix should be column-major, and in compressed format for best performance.\n     *  \\sa SparseMatrix::makeCompressed().\n     */\n    template<typename InputMatrixType>\n    void compute(const InputMatrixType& matrix)\n    {\n      if(m_symbolic) umfpack_free_symbolic(&m_symbolic,Scalar());\n      if(m_numeric)  umfpack_free_numeric(&m_numeric,Scalar());\n      grab(matrix.derived());\n      analyzePattern_impl();\n      factorize_impl();\n    }\n\n    /** Performs a symbolic decomposition on the sparcity of \\a matrix.\n      *\n      * This function is particularly useful when solving for several problems having the same structure.\n      *\n      * \\sa factorize(), compute()\n      */\n    template<typename InputMatrixType>\n    void analyzePattern(const InputMatrixType& matrix)\n    {\n      if(m_symbolic) umfpack_free_symbolic(&m_symbolic,Scalar());\n      if(m_numeric)  umfpack_free_numeric(&m_numeric,Scalar());\n      \n      grab(matrix.derived());\n\n      analyzePattern_impl();\n    }\n\n    /** Provides the return status code returned by UmfPack during the numeric\n      * factorization.\n      *\n      * \\sa factorize(), compute()\n      */\n    inline int umfpackFactorizeReturncode() const\n    {\n      eigen_assert(m_numeric && \"UmfPackLU: you must first call factorize()\");\n      return m_fact_errorCode;\n    }\n\n    /** Provides access to the control settings array used by UmfPack.\n      *\n      * If this array contains NaN's, the default values are used.\n      *\n      * See UMFPACK documentation for details.\n      */\n    inline const UmfpackControl& umfpackControl() const\n    {\n      return m_control;\n    }\n    \n    /** Provides access to the control settings array used by UmfPack.\n      *\n      * If this array contains NaN's, the default values are used.\n      *\n      * See UMFPACK documentation for details.\n      */\n    inline UmfpackControl& umfpackControl()\n    {\n      return m_control;\n    }\n    \n    /** Performs a numeric decomposition of \\a matrix\n      *\n      * The given matrix must has the same sparcity than the matrix on which the pattern anylysis has been performed.\n      *\n      * \\sa analyzePattern(), compute()\n      */\n    template<typename InputMatrixType>\n    void factorize(const InputMatrixType& matrix)\n    {\n      eigen_assert(m_analysisIsOk && \"UmfPackLU: you must first call analyzePattern()\");\n      if(m_numeric)\n        umfpack_free_numeric(&m_numeric,Scalar());\n\n      grab(matrix.derived());\n      \n      factorize_impl();\n    }\n\n    /** \\internal */\n    template<typename BDerived,typename XDerived>\n    bool _solve_impl(const MatrixBase<BDerived> &b, MatrixBase<XDerived> &x) const;\n\n    Scalar determinant() const;\n\n    void extractData() const;\n\n  protected:\n\n    void init()\n    {\n      m_info                  = InvalidInput;\n      m_isInitialized         = false;\n      m_numeric               = 0;\n      m_symbolic              = 0;\n      m_extractedDataAreDirty = true;\n    }\n    \n    void analyzePattern_impl()\n    {\n      umfpack_defaults(m_control.data(), Scalar());\n      int errorCode = 0;\n      errorCode = umfpack_symbolic(internal::convert_index<int>(mp_matrix.rows()),\n                                   internal::convert_index<int>(mp_matrix.cols()),\n                                   mp_matrix.outerIndexPtr(), mp_matrix.innerIndexPtr(), mp_matrix.valuePtr(),\n                                   &m_symbolic, m_control.data(), 0);\n\n      m_isInitialized = true;\n      m_info = errorCode ? InvalidInput : Success;\n      m_analysisIsOk = true;\n      m_factorizationIsOk = false;\n      m_extractedDataAreDirty = true;\n    }\n    \n    void factorize_impl()\n    {\n      m_fact_errorCode = umfpack_numeric(mp_matrix.outerIndexPtr(), mp_matrix.innerIndexPtr(), mp_matrix.valuePtr(),\n                                         m_symbolic, &m_numeric, m_control.data(), 0);\n\n      m_info = m_fact_errorCode == UMFPACK_OK ? Success : NumericalIssue;\n      m_factorizationIsOk = true;\n      m_extractedDataAreDirty = true;\n    }\n    \n    template<typename MatrixDerived>\n    void grab(const EigenBase<MatrixDerived> &A)\n    {\n      mp_matrix.~UmfpackMatrixRef();\n      ::new (&mp_matrix) UmfpackMatrixRef(A.derived());\n    }\n    \n    void grab(const UmfpackMatrixRef &A)\n    {\n      if(&(A.derived()) != &mp_matrix)\n      {\n        mp_matrix.~UmfpackMatrixRef();\n        ::new (&mp_matrix) UmfpackMatrixRef(A);\n      }\n    }\n  \n    // cached data to reduce reallocation, etc.\n    mutable LUMatrixType m_l;\n    int m_fact_errorCode;\n    UmfpackControl m_control;\n    \n    mutable LUMatrixType m_u;\n    mutable IntColVectorType m_p;\n    mutable IntRowVectorType m_q;\n\n    UmfpackMatrixType m_dummy;\n    UmfpackMatrixRef mp_matrix;\n  \n    void* m_numeric;\n    void* m_symbolic;\n\n    mutable ComputationInfo m_info;\n    int m_factorizationIsOk;\n    int m_analysisIsOk;\n    mutable bool m_extractedDataAreDirty;\n    \n  private:\n    UmfPackLU(const UmfPackLU& ) { }\n};\n\n\ntemplate<typename MatrixType>\nvoid UmfPackLU<MatrixType>::extractData() const\n{\n  if (m_extractedDataAreDirty)\n  {\n    // get size of the data\n    int lnz, unz, rows, cols, nz_udiag;\n    umfpack_get_lunz(&lnz, &unz, &rows, &cols, &nz_udiag, m_numeric, Scalar());\n\n    // allocate data\n    m_l.resize(rows,(std::min)(rows,cols));\n    m_l.resizeNonZeros(lnz);\n\n    m_u.resize((std::min)(rows,cols),cols);\n    m_u.resizeNonZeros(unz);\n\n    m_p.resize(rows);\n    m_q.resize(cols);\n\n    // extract\n    umfpack_get_numeric(m_l.outerIndexPtr(), m_l.innerIndexPtr(), m_l.valuePtr(),\n                        m_u.outerIndexPtr(), m_u.innerIndexPtr(), m_u.valuePtr(),\n                        m_p.data(), m_q.data(), 0, 0, 0, m_numeric);\n\n    m_extractedDataAreDirty = false;\n  }\n}\n\ntemplate<typename MatrixType>\ntypename UmfPackLU<MatrixType>::Scalar UmfPackLU<MatrixType>::determinant() const\n{\n  Scalar det;\n  umfpack_get_determinant(&det, 0, m_numeric, 0);\n  return det;\n}\n\ntemplate<typename MatrixType>\ntemplate<typename BDerived,typename XDerived>\nbool UmfPackLU<MatrixType>::_solve_impl(const MatrixBase<BDerived> &b, MatrixBase<XDerived> &x) const\n{\n  Index rhsCols = b.cols();\n  eigen_assert((BDerived::Flags&RowMajorBit)==0 && \"UmfPackLU backend does not support non col-major rhs yet\");\n  eigen_assert((XDerived::Flags&RowMajorBit)==0 && \"UmfPackLU backend does not support non col-major result yet\");\n  eigen_assert(b.derived().data() != x.derived().data() && \" Umfpack does not support inplace solve\");\n  \n  int errorCode;\n  Scalar* x_ptr = 0;\n  Matrix<Scalar,Dynamic,1> x_tmp;\n  if(x.innerStride()!=1)\n  {\n    x_tmp.resize(x.rows());\n    x_ptr = x_tmp.data();\n  }\n  for (int j=0; j<rhsCols; ++j)\n  {\n    if(x.innerStride()==1)\n      x_ptr = &x.col(j).coeffRef(0);\n    errorCode = umfpack_solve(UMFPACK_A,\n        mp_matrix.outerIndexPtr(), mp_matrix.innerIndexPtr(), mp_matrix.valuePtr(),\n        x_ptr, &b.const_cast_derived().col(j).coeffRef(0), m_numeric, m_control.data(), 0);\n    if(x.innerStride()!=1)\n      x.col(j) = x_tmp;\n    if (errorCode!=0)\n      return false;\n  }\n\n  return true;\n}\n\n} // end namespace Eigen\n\n#endif // EIGEN_UMFPACKSUPPORT_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/misc/Image.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_MISC_IMAGE_H\n#define EIGEN_MISC_IMAGE_H\n\nnamespace Eigen { \n\nnamespace internal {\n\n/** \\class image_retval_base\n  *\n  */\ntemplate<typename DecompositionType>\nstruct traits<image_retval_base<DecompositionType> >\n{\n  typedef typename DecompositionType::MatrixType MatrixType;\n  typedef Matrix<\n    typename MatrixType::Scalar,\n    MatrixType::RowsAtCompileTime, // the image is a subspace of the destination space, whose\n                                   // dimension is the number of rows of the original matrix\n    Dynamic,                       // we don't know at compile time the dimension of the image (the rank)\n    MatrixType::Options,\n    MatrixType::MaxRowsAtCompileTime, // the image matrix will consist of columns from the original matrix,\n    MatrixType::MaxColsAtCompileTime  // so it has the same number of rows and at most as many columns.\n  > ReturnType;\n};\n\ntemplate<typename _DecompositionType> struct image_retval_base\n : public ReturnByValue<image_retval_base<_DecompositionType> >\n{\n  typedef _DecompositionType DecompositionType;\n  typedef typename DecompositionType::MatrixType MatrixType;\n  typedef ReturnByValue<image_retval_base> Base;\n\n  image_retval_base(const DecompositionType& dec, const MatrixType& originalMatrix)\n    : m_dec(dec), m_rank(dec.rank()),\n      m_cols(m_rank == 0 ? 1 : m_rank),\n      m_originalMatrix(originalMatrix)\n  {}\n\n  inline Index rows() const { return m_dec.rows(); }\n  inline Index cols() const { return m_cols; }\n  inline Index rank() const { return m_rank; }\n  inline const DecompositionType& dec() const { return m_dec; }\n  inline const MatrixType& originalMatrix() const { return m_originalMatrix; }\n\n  template<typename Dest> inline void evalTo(Dest& dst) const\n  {\n    static_cast<const image_retval<DecompositionType>*>(this)->evalTo(dst);\n  }\n\n  protected:\n    const DecompositionType& m_dec;\n    Index m_rank, m_cols;\n    const MatrixType& m_originalMatrix;\n};\n\n} // end namespace internal\n\n#define EIGEN_MAKE_IMAGE_HELPERS(DecompositionType) \\\n  typedef typename DecompositionType::MatrixType MatrixType; \\\n  typedef typename MatrixType::Scalar Scalar; \\\n  typedef typename MatrixType::RealScalar RealScalar; \\\n  typedef Eigen::internal::image_retval_base<DecompositionType> Base; \\\n  using Base::dec; \\\n  using Base::originalMatrix; \\\n  using Base::rank; \\\n  using Base::rows; \\\n  using Base::cols; \\\n  image_retval(const DecompositionType& dec, const MatrixType& originalMatrix) \\\n    : Base(dec, originalMatrix) {}\n\n} // end namespace Eigen\n\n#endif // EIGEN_MISC_IMAGE_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/misc/Kernel.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_MISC_KERNEL_H\n#define EIGEN_MISC_KERNEL_H\n\nnamespace Eigen { \n\nnamespace internal {\n\n/** \\class kernel_retval_base\n  *\n  */\ntemplate<typename DecompositionType>\nstruct traits<kernel_retval_base<DecompositionType> >\n{\n  typedef typename DecompositionType::MatrixType MatrixType;\n  typedef Matrix<\n    typename MatrixType::Scalar,\n    MatrixType::ColsAtCompileTime, // the number of rows in the \"kernel matrix\"\n                                   // is the number of cols of the original matrix\n                                   // so that the product \"matrix * kernel = zero\" makes sense\n    Dynamic,                       // we don't know at compile-time the dimension of the kernel\n    MatrixType::Options,\n    MatrixType::MaxColsAtCompileTime, // see explanation for 2nd template parameter\n    MatrixType::MaxColsAtCompileTime // the kernel is a subspace of the domain space,\n                                     // whose dimension is the number of columns of the original matrix\n  > ReturnType;\n};\n\ntemplate<typename _DecompositionType> struct kernel_retval_base\n : public ReturnByValue<kernel_retval_base<_DecompositionType> >\n{\n  typedef _DecompositionType DecompositionType;\n  typedef ReturnByValue<kernel_retval_base> Base;\n\n  explicit kernel_retval_base(const DecompositionType& dec)\n    : m_dec(dec),\n      m_rank(dec.rank()),\n      m_cols(m_rank==dec.cols() ? 1 : dec.cols() - m_rank)\n  {}\n\n  inline Index rows() const { return m_dec.cols(); }\n  inline Index cols() const { return m_cols; }\n  inline Index rank() const { return m_rank; }\n  inline const DecompositionType& dec() const { return m_dec; }\n\n  template<typename Dest> inline void evalTo(Dest& dst) const\n  {\n    static_cast<const kernel_retval<DecompositionType>*>(this)->evalTo(dst);\n  }\n\n  protected:\n    const DecompositionType& m_dec;\n    Index m_rank, m_cols;\n};\n\n} // end namespace internal\n\n#define EIGEN_MAKE_KERNEL_HELPERS(DecompositionType) \\\n  typedef typename DecompositionType::MatrixType MatrixType; \\\n  typedef typename MatrixType::Scalar Scalar; \\\n  typedef typename MatrixType::RealScalar RealScalar; \\\n  typedef Eigen::internal::kernel_retval_base<DecompositionType> Base; \\\n  using Base::dec; \\\n  using Base::rank; \\\n  using Base::rows; \\\n  using Base::cols; \\\n  kernel_retval(const DecompositionType& dec) : Base(dec) {}\n\n} // end namespace Eigen\n\n#endif // EIGEN_MISC_KERNEL_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/misc/RealSvd2x2.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2009-2010 Benoit Jacob <jacob.benoit.1@gmail.com>\n// Copyright (C) 2013-2016 Gael Guennebaud <gael.guennebaud@inria.fr>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_REALSVD2X2_H\n#define EIGEN_REALSVD2X2_H\n\nnamespace Eigen {\n\nnamespace internal {\n\ntemplate<typename MatrixType, typename RealScalar, typename Index>\nvoid real_2x2_jacobi_svd(const MatrixType& matrix, Index p, Index q,\n                         JacobiRotation<RealScalar> *j_left,\n                         JacobiRotation<RealScalar> *j_right)\n{\n  using std::sqrt;\n  using std::abs;\n  Matrix<RealScalar,2,2> m;\n  m << numext::real(matrix.coeff(p,p)), numext::real(matrix.coeff(p,q)),\n       numext::real(matrix.coeff(q,p)), numext::real(matrix.coeff(q,q));\n  JacobiRotation<RealScalar> rot1;\n  RealScalar t = m.coeff(0,0) + m.coeff(1,1);\n  RealScalar d = m.coeff(1,0) - m.coeff(0,1);\n\n  if(abs(d) < (std::numeric_limits<RealScalar>::min)())\n  {\n    rot1.s() = RealScalar(0);\n    rot1.c() = RealScalar(1);\n  }\n  else\n  {\n    // If d!=0, then t/d cannot overflow because the magnitude of the\n    // entries forming d are not too small compared to the ones forming t.\n    RealScalar u = t / d;\n    RealScalar tmp = sqrt(RealScalar(1) + numext::abs2(u));\n    rot1.s() = RealScalar(1) / tmp;\n    rot1.c() = u / tmp;\n  }\n  m.applyOnTheLeft(0,1,rot1);\n  j_right->makeJacobi(m,0,1);\n  *j_left = rot1 * j_right->transpose();\n}\n\n} // end namespace internal\n\n} // end namespace Eigen\n\n#endif // EIGEN_REALSVD2X2_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/misc/blas.h",
    "content": "#ifndef BLAS_H\n#define BLAS_H\n\n#ifdef __cplusplus\nextern \"C\"\n{\n#endif\n\n#define BLASFUNC(FUNC) FUNC##_\n\n#ifdef __WIN64__\ntypedef long long BLASLONG;\ntypedef unsigned long long BLASULONG;\n#else\ntypedef long BLASLONG;\ntypedef unsigned long BLASULONG;\n#endif\n\nint    BLASFUNC(xerbla)(const char *, int *info, int);\n\nfloat  BLASFUNC(sdot)  (int *, float  *, int *, float  *, int *);\nfloat  BLASFUNC(sdsdot)(int *, float  *,        float  *, int *, float  *, int *);\n\ndouble BLASFUNC(dsdot) (int *, float  *, int *, float  *, int *);\ndouble BLASFUNC(ddot)  (int *, double *, int *, double *, int *);\ndouble BLASFUNC(qdot)  (int *, double *, int *, double *, int *);\n\nint  BLASFUNC(cdotuw)  (int *, float  *, int *, float  *, int *, float*);\nint  BLASFUNC(cdotcw)  (int *, float  *, int *, float  *, int *, float*);\nint  BLASFUNC(zdotuw)  (int *, double  *, int *, double  *, int *, double*);\nint  BLASFUNC(zdotcw)  (int *, double  *, int *, double  *, int *, double*);\n\nint    BLASFUNC(saxpy) (const int *, const float  *, const float  *, const int *, float  *, const int *);\nint    BLASFUNC(daxpy) (const int *, const double *, const double *, const int *, double *, const int *);\nint    BLASFUNC(qaxpy) (const int *, const double *, const double *, const int *, double *, const int *);\nint    BLASFUNC(caxpy) (const int *, const float  *, const float  *, const int *, float  *, const int *);\nint    BLASFUNC(zaxpy) (const int *, const double *, const double *, const int *, double *, const int *);\nint    BLASFUNC(xaxpy) (const int *, const double *, const double *, const int *, double *, const int *);\nint    BLASFUNC(caxpyc)(const int *, const float  *, const float  *, const int *, float  *, const int *);\nint    BLASFUNC(zaxpyc)(const int *, const double *, const double *, const int *, double *, const int *);\nint    BLASFUNC(xaxpyc)(const int *, const double *, const double *, const int *, double *, const int *);\n\nint    BLASFUNC(scopy) (int *, float  *, int *, float  *, int *);\nint    BLASFUNC(dcopy) (int *, double *, int *, double *, int *);\nint    BLASFUNC(qcopy) (int *, double *, int *, double *, int *);\nint    BLASFUNC(ccopy) (int *, float  *, int *, float  *, int *);\nint    BLASFUNC(zcopy) (int *, double *, int *, double *, int *);\nint    BLASFUNC(xcopy) (int *, double *, int *, double *, int *);\n\nint    BLASFUNC(sswap) (int *, float  *, int *, float  *, int *);\nint    BLASFUNC(dswap) (int *, double *, int *, double *, int *);\nint    BLASFUNC(qswap) (int *, double *, int *, double *, int *);\nint    BLASFUNC(cswap) (int *, float  *, int *, float  *, int *);\nint    BLASFUNC(zswap) (int *, double *, int *, double *, int *);\nint    BLASFUNC(xswap) (int *, double *, int *, double *, int *);\n\nfloat  BLASFUNC(sasum) (int *, float  *, int *);\nfloat  BLASFUNC(scasum)(int *, float  *, int *);\ndouble BLASFUNC(dasum) (int *, double *, int *);\ndouble BLASFUNC(qasum) (int *, double *, int *);\ndouble BLASFUNC(dzasum)(int *, double *, int *);\ndouble BLASFUNC(qxasum)(int *, double *, int *);\n\nint    BLASFUNC(isamax)(int *, float  *, int *);\nint    BLASFUNC(idamax)(int *, double *, int *);\nint    BLASFUNC(iqamax)(int *, double *, int *);\nint    BLASFUNC(icamax)(int *, float  *, int *);\nint    BLASFUNC(izamax)(int *, double *, int *);\nint    BLASFUNC(ixamax)(int *, double *, int *);\n\nint    BLASFUNC(ismax) (int *, float  *, int *);\nint    BLASFUNC(idmax) (int *, double *, int *);\nint    BLASFUNC(iqmax) (int *, double *, int *);\nint    BLASFUNC(icmax) (int *, float  *, int *);\nint    BLASFUNC(izmax) (int *, double *, int *);\nint    BLASFUNC(ixmax) (int *, double *, int *);\n\nint    BLASFUNC(isamin)(int *, float  *, int *);\nint    BLASFUNC(idamin)(int *, double *, int *);\nint    BLASFUNC(iqamin)(int *, double *, int *);\nint    BLASFUNC(icamin)(int *, float  *, int *);\nint    BLASFUNC(izamin)(int *, double *, int *);\nint    BLASFUNC(ixamin)(int *, double *, int *);\n\nint    BLASFUNC(ismin)(int *, float  *, int *);\nint    BLASFUNC(idmin)(int *, double *, int *);\nint    BLASFUNC(iqmin)(int *, double *, int *);\nint    BLASFUNC(icmin)(int *, float  *, int *);\nint    BLASFUNC(izmin)(int *, double *, int *);\nint    BLASFUNC(ixmin)(int *, double *, int *);\n\nfloat  BLASFUNC(samax) (int *, float  *, int *);\ndouble BLASFUNC(damax) (int *, double *, int *);\ndouble BLASFUNC(qamax) (int *, double *, int *);\nfloat  BLASFUNC(scamax)(int *, float  *, int *);\ndouble BLASFUNC(dzamax)(int *, double *, int *);\ndouble BLASFUNC(qxamax)(int *, double *, int *);\n\nfloat  BLASFUNC(samin) (int *, float  *, int *);\ndouble BLASFUNC(damin) (int *, double *, int *);\ndouble BLASFUNC(qamin) (int *, double *, int *);\nfloat  BLASFUNC(scamin)(int *, float  *, int *);\ndouble BLASFUNC(dzamin)(int *, double *, int *);\ndouble BLASFUNC(qxamin)(int *, double *, int *);\n\nfloat  BLASFUNC(smax)  (int *, float  *, int *);\ndouble BLASFUNC(dmax)  (int *, double *, int *);\ndouble BLASFUNC(qmax)  (int *, double *, int *);\nfloat  BLASFUNC(scmax) (int *, float  *, int *);\ndouble BLASFUNC(dzmax) (int *, double *, int *);\ndouble BLASFUNC(qxmax) (int *, double *, int *);\n\nfloat  BLASFUNC(smin)  (int *, float  *, int *);\ndouble BLASFUNC(dmin)  (int *, double *, int *);\ndouble BLASFUNC(qmin)  (int *, double *, int *);\nfloat  BLASFUNC(scmin) (int *, float  *, int *);\ndouble BLASFUNC(dzmin) (int *, double *, int *);\ndouble BLASFUNC(qxmin) (int *, double *, int *);\n\nint    BLASFUNC(sscal) (int *,  float  *, float  *, int *);\nint    BLASFUNC(dscal) (int *,  double *, double *, int *);\nint    BLASFUNC(qscal) (int *,  double *, double *, int *);\nint    BLASFUNC(cscal) (int *,  float  *, float  *, int *);\nint    BLASFUNC(zscal) (int *,  double *, double *, int *);\nint    BLASFUNC(xscal) (int *,  double *, double *, int *);\nint    BLASFUNC(csscal)(int *,  float  *, float  *, int *);\nint    BLASFUNC(zdscal)(int *,  double *, double *, int *);\nint    BLASFUNC(xqscal)(int *,  double *, double *, int *);\n\nfloat  BLASFUNC(snrm2) (int *, float  *, int *);\nfloat  BLASFUNC(scnrm2)(int *, float  *, int *);\n\ndouble BLASFUNC(dnrm2) (int *, double *, int *);\ndouble BLASFUNC(qnrm2) (int *, double *, int *);\ndouble BLASFUNC(dznrm2)(int *, double *, int *);\ndouble BLASFUNC(qxnrm2)(int *, double *, int *);\n\nint    BLASFUNC(srot)  (int *, float  *, int *, float  *, int *, float  *, float  *);\nint    BLASFUNC(drot)  (int *, double *, int *, double *, int *, double *, double *);\nint    BLASFUNC(qrot)  (int *, double *, int *, double *, int *, double *, double *);\nint    BLASFUNC(csrot) (int *, float  *, int *, float  *, int *, float  *, float  *);\nint    BLASFUNC(zdrot) (int *, double *, int *, double *, int *, double *, double *);\nint    BLASFUNC(xqrot) (int *, double *, int *, double *, int *, double *, double *);\n\nint    BLASFUNC(srotg) (float  *, float  *, float  *, float  *);\nint    BLASFUNC(drotg) (double *, double *, double *, double *);\nint    BLASFUNC(qrotg) (double *, double *, double *, double *);\nint    BLASFUNC(crotg) (float  *, float  *, float  *, float  *);\nint    BLASFUNC(zrotg) (double *, double *, double *, double *);\nint    BLASFUNC(xrotg) (double *, double *, double *, double *);\n\nint    BLASFUNC(srotmg)(float  *, float  *, float  *, float  *, float  *);\nint    BLASFUNC(drotmg)(double *, double *, double *, double *, double *);\n\nint    BLASFUNC(srotm) (int *, float  *, int *, float  *, int *, float  *);\nint    BLASFUNC(drotm) (int *, double *, int *, double *, int *, double *);\nint    BLASFUNC(qrotm) (int *, double *, int *, double *, int *, double *);\n\n/* Level 2 routines */\n\nint BLASFUNC(sger)(int *,    int *, float *,  float *, int *,\n\t\t   float *,  int *, float *,  int *);\nint BLASFUNC(dger)(int *,    int *, double *, double *, int *,\n\t\t   double *, int *, double *, int *);\nint BLASFUNC(qger)(int *,    int *, double *, double *, int *,\n\t\t   double *, int *, double *, int *);\nint BLASFUNC(cgeru)(int *,    int *, float *,  float *, int *,\n\t\t    float *,  int *, float *,  int *);\nint BLASFUNC(cgerc)(int *,    int *, float *,  float *, int *,\n\t\t    float *,  int *, float *,  int *);\nint BLASFUNC(zgeru)(int *,    int *, double *, double *, int *,\n\t\t    double *, int *, double *, int *);\nint BLASFUNC(zgerc)(int *,    int *, double *, double *, int *,\n\t\t    double *, int *, double *, int *);\nint BLASFUNC(xgeru)(int *,    int *, double *, double *, int *,\n\t\t    double *, int *, double *, int *);\nint BLASFUNC(xgerc)(int *,    int *, double *, double *, int *,\n\t\t    double *, int *, double *, int *);\n\nint BLASFUNC(sgemv)(const char *, const int *, const int *, const float  *, const float  *, const int *, const float  *, const int *, const float  *, float  *, const int *);\nint BLASFUNC(dgemv)(const char *, const int *, const int *, const double *, const double *, const int *, const double *, const int *, const double *, double *, const int *);\nint BLASFUNC(qgemv)(const char *, const int *, const int *, const double *, const double *, const int *, const double *, const int *, const double *, double *, const int *);\nint BLASFUNC(cgemv)(const char *, const int *, const int *, const float  *, const float  *, const int *, const float  *, const int *, const float  *, float  *, const int *);\nint BLASFUNC(zgemv)(const char *, const int *, const int *, const double *, const double *, const int *, const double *, const int *, const double *, double *, const int *);\nint BLASFUNC(xgemv)(const char *, const int *, const int *, const double *, const double *, const int *, const double *, const int *, const double *, double *, const int *);\n\nint BLASFUNC(strsv) (const char *, const char *, const char *, const int *, const float  *, const int *, float  *, const int *);\nint BLASFUNC(dtrsv) (const char *, const char *, const char *, const int *, const double *, const int *, double *, const int *);\nint BLASFUNC(qtrsv) (const char *, const char *, const char *, const int *, const double *, const int *, double *, const int *);\nint BLASFUNC(ctrsv) (const char *, const char *, const char *, const int *, const float  *, const int *, float  *, const int *);\nint BLASFUNC(ztrsv) (const char *, const char *, const char *, const int *, const double *, const int *, double *, const int *);\nint BLASFUNC(xtrsv) (const char *, const char *, const char *, const int *, const double *, const int *, double *, const int *);\n\nint BLASFUNC(stpsv) (char *, char *, char *, int *, float  *, float  *, int *);\nint BLASFUNC(dtpsv) (char *, char *, char *, int *, double *, double *, int *);\nint BLASFUNC(qtpsv) (char *, char *, char *, int *, double *, double *, int *);\nint BLASFUNC(ctpsv) (char *, char *, char *, int *, float  *, float  *, int *);\nint BLASFUNC(ztpsv) (char *, char *, char *, int *, double *, double *, int *);\nint BLASFUNC(xtpsv) (char *, char *, char *, int *, double *, double *, int *);\n\nint BLASFUNC(strmv) (const char *, const char *, const char *, const int *, const float  *, const int *, float  *, const int *);\nint BLASFUNC(dtrmv) (const char *, const char *, const char *, const int *, const double *, const int *, double *, const int *);\nint BLASFUNC(qtrmv) (const char *, const char *, const char *, const int *, const double *, const int *, double *, const int *);\nint BLASFUNC(ctrmv) (const char *, const char *, const char *, const int *, const float  *, const int *, float  *, const int *);\nint BLASFUNC(ztrmv) (const char *, const char *, const char *, const int *, const double *, const int *, double *, const int *);\nint BLASFUNC(xtrmv) (const char *, const char *, const char *, const int *, const double *, const int *, double *, const int *);\n\nint BLASFUNC(stpmv) (char *, char *, char *, int *, float  *, float  *, int *);\nint BLASFUNC(dtpmv) (char *, char *, char *, int *, double *, double *, int *);\nint BLASFUNC(qtpmv) (char *, char *, char *, int *, double *, double *, int *);\nint BLASFUNC(ctpmv) (char *, char *, char *, int *, float  *, float  *, int *);\nint BLASFUNC(ztpmv) (char *, char *, char *, int *, double *, double *, int *);\nint BLASFUNC(xtpmv) (char *, char *, char *, int *, double *, double *, int *);\n\nint BLASFUNC(stbmv) (char *, char *, char *, int *, int *, float  *, int *, float  *, int *);\nint BLASFUNC(dtbmv) (char *, char *, char *, int *, int *, double *, int *, double *, int *);\nint BLASFUNC(qtbmv) (char *, char *, char *, int *, int *, double *, int *, double *, int *);\nint BLASFUNC(ctbmv) (char *, char *, char *, int *, int *, float  *, int *, float  *, int *);\nint BLASFUNC(ztbmv) (char *, char *, char *, int *, int *, double *, int *, double *, int *);\nint BLASFUNC(xtbmv) (char *, char *, char *, int *, int *, double *, int *, double *, int *);\n\nint BLASFUNC(stbsv) (char *, char *, char *, int *, int *, float  *, int *, float  *, int *);\nint BLASFUNC(dtbsv) (char *, char *, char *, int *, int *, double *, int *, double *, int *);\nint BLASFUNC(qtbsv) (char *, char *, char *, int *, int *, double *, int *, double *, int *);\nint BLASFUNC(ctbsv) (char *, char *, char *, int *, int *, float  *, int *, float  *, int *);\nint BLASFUNC(ztbsv) (char *, char *, char *, int *, int *, double *, int *, double *, int *);\nint BLASFUNC(xtbsv) (char *, char *, char *, int *, int *, double *, int *, double *, int *);\n\nint BLASFUNC(ssymv) (const char *, const int *, const float  *, const float  *, const int *, const float  *, const int *, const float  *, float  *, const int *);\nint BLASFUNC(dsymv) (const char *, const int *, const double *, const double *, const int *, const double *, const int *, const double *, double *, const int *);\nint BLASFUNC(qsymv) (const char *, const int *, const double *, const double *, const int *, const double *, const int *, const double *, double *, const int *);\n\nint BLASFUNC(sspmv) (char *, int *, float  *, float *,\n\t\t     float  *, int *, float *, float *, int *);\nint BLASFUNC(dspmv) (char *, int *, double  *, double *,\n\t\t     double  *, int *, double *, double *, int *);\nint BLASFUNC(qspmv) (char *, int *, double  *, double *,\n\t\t     double  *, int *, double *, double *, int *);\n\nint BLASFUNC(ssyr) (const char *, const int *, const float   *, const float  *, const int *, float  *, const int *);\nint BLASFUNC(dsyr) (const char *, const int *, const double  *, const double *, const int *, double *, const int *);\nint BLASFUNC(qsyr) (const char *, const int *, const double  *, const double *, const int *, double *, const int *);\n\nint BLASFUNC(ssyr2) (const char *, const int *, const float   *, const float  *, const int *, const float  *, const int *, float  *, const int *);\nint BLASFUNC(dsyr2) (const char *, const int *, const double  *, const double *, const int *, const double *, const int *, double *, const int *);\nint BLASFUNC(qsyr2) (const char *, const int *, const double  *, const double *, const int *, const double *, const int *, double *, const int *);\nint BLASFUNC(csyr2) (const char *, const int *, const float   *, const float  *, const int *, const float  *, const int *, float  *, const int *);\nint BLASFUNC(zsyr2) (const char *, const int *, const double  *, const double *, const int *, const double *, const int *, double *, const int *);\nint BLASFUNC(xsyr2) (const char *, const int *, const double  *, const double *, const int *, const double *, const int *, double *, const int *);\n\nint BLASFUNC(sspr) (char *, int *, float   *, float  *, int *,\n\t\t    float  *);\nint BLASFUNC(dspr) (char *, int *, double  *, double *, int *,\n\t\t    double *);\nint BLASFUNC(qspr) (char *, int *, double  *, double *, int *,\n\t\t    double *);\n\nint BLASFUNC(sspr2) (char *, int *, float   *,\n\t\t     float  *, int *, float  *, int *, float  *);\nint BLASFUNC(dspr2) (char *, int *, double  *,\n\t\t     double *, int *, double *, int *, double *);\nint BLASFUNC(qspr2) (char *, int *, double  *,\n\t\t     double *, int *, double *, int *, double *);\nint BLASFUNC(cspr2) (char *, int *, float   *,\n\t\t     float  *, int *, float  *, int *, float  *);\nint BLASFUNC(zspr2) (char *, int *, double  *,\n\t\t     double *, int *, double *, int *, double *);\nint BLASFUNC(xspr2) (char *, int *, double  *,\n\t\t     double *, int *, double *, int *, double *);\n\nint BLASFUNC(cher) (char *, int *, float   *, float  *, int *,\n\t\t    float  *, int *);\nint BLASFUNC(zher) (char *, int *, double  *, double *, int *,\n\t\t    double *, int *);\nint BLASFUNC(xher) (char *, int *, double  *, double *, int *,\n\t\t    double *, int *);\n\nint BLASFUNC(chpr) (char *, int *, float   *, float  *, int *, float  *);\nint BLASFUNC(zhpr) (char *, int *, double  *, double *, int *, double *);\nint BLASFUNC(xhpr) (char *, int *, double  *, double *, int *, double *);\n\nint BLASFUNC(cher2) (char *, int *, float   *,\n\t\t     float  *, int *, float  *, int *, float  *, int *);\nint BLASFUNC(zher2) (char *, int *, double  *,\n\t\t     double *, int *, double *, int *, double *, int *);\nint BLASFUNC(xher2) (char *, int *, double  *,\n\t\t     double *, int *, double *, int *, double *, int *);\n\nint BLASFUNC(chpr2) (char *, int *, float   *,\n\t\t     float  *, int *, float  *, int *, float  *);\nint BLASFUNC(zhpr2) (char *, int *, double  *,\n\t\t     double *, int *, double *, int *, double *);\nint BLASFUNC(xhpr2) (char *, int *, double  *,\n\t\t     double *, int *, double *, int *, double *);\n\nint BLASFUNC(chemv) (const char *, const int *, const float  *, const float  *, const int *, const float  *, const int *, const float  *, float  *, const int *);\nint BLASFUNC(zhemv) (const char *, const int *, const double *, const double *, const int *, const double *, const int *, const double *, double *, const int *);\nint BLASFUNC(xhemv) (const char *, const int *, const double *, const double *, const int *, const double *, const int *, const double *, double *, const int *);\n\nint BLASFUNC(chpmv) (char *, int *, float  *, float *,\n\t\t     float  *, int *, float *, float *, int *);\nint BLASFUNC(zhpmv) (char *, int *, double  *, double *,\n\t\t     double  *, int *, double *, double *, int *);\nint BLASFUNC(xhpmv) (char *, int *, double  *, double *,\n\t\t     double  *, int *, double *, double *, int *);\n\nint BLASFUNC(snorm)(char *, int *, int *, float  *, int *);\nint BLASFUNC(dnorm)(char *, int *, int *, double *, int *);\nint BLASFUNC(cnorm)(char *, int *, int *, float  *, int *);\nint BLASFUNC(znorm)(char *, int *, int *, double *, int *);\n\nint BLASFUNC(sgbmv)(char *, int *, int *, int *, int *, float  *, float  *, int *,\n\t\t    float  *, int *, float  *, float  *, int *);\nint BLASFUNC(dgbmv)(char *, int *, int *, int *, int *, double *, double *, int *,\n\t\t    double *, int *, double *, double *, int *);\nint BLASFUNC(qgbmv)(char *, int *, int *, int *, int *, double *, double *, int *,\n\t\t    double *, int *, double *, double *, int *);\nint BLASFUNC(cgbmv)(char *, int *, int *, int *, int *, float  *, float  *, int *,\n\t\t    float  *, int *, float  *, float  *, int *);\nint BLASFUNC(zgbmv)(char *, int *, int *, int *, int *, double *, double *, int *,\n\t\t    double *, int *, double *, double *, int *);\nint BLASFUNC(xgbmv)(char *, int *, int *, int *, int *, double *, double *, int *,\n\t\t    double *, int *, double *, double *, int *);\n\nint BLASFUNC(ssbmv)(char *, int *, int *, float  *, float  *, int *,\n\t\t    float  *, int *, float  *, float  *, int *);\nint BLASFUNC(dsbmv)(char *, int *, int *, double *, double *, int *,\n\t\t    double *, int *, double *, double *, int *);\nint BLASFUNC(qsbmv)(char *, int *, int *, double *, double *, int *,\n\t\t    double *, int *, double *, double *, int *);\nint BLASFUNC(csbmv)(char *, int *, int *, float  *, float  *, int *,\n\t\t    float  *, int *, float  *, float  *, int *);\nint BLASFUNC(zsbmv)(char *, int *, int *, double *, double *, int *,\n\t\t    double *, int *, double *, double *, int *);\nint BLASFUNC(xsbmv)(char *, int *, int *, double *, double *, int *,\n\t\t    double *, int *, double *, double *, int *);\n\nint BLASFUNC(chbmv)(char *, int *, int *, float  *, float  *, int *,\n\t\t    float  *, int *, float  *, float  *, int *);\nint BLASFUNC(zhbmv)(char *, int *, int *, double *, double *, int *,\n\t\t    double *, int *, double *, double *, int *);\nint BLASFUNC(xhbmv)(char *, int *, int *, double *, double *, int *,\n\t\t    double *, int *, double *, double *, int *);\n\n/* Level 3 routines */\n\nint BLASFUNC(sgemm)(const char *, const char *, const int *, const int *, const int *, const float  *, const float  *, const int *, const float  *, const int *, const float  *, float  *, const int *);\nint BLASFUNC(dgemm)(const char *, const char *, const int *, const int *, const int *, const double *, const double *, const int *, const double *, const int *, const double *, double *, const int *);\nint BLASFUNC(qgemm)(const char *, const char *, const int *, const int *, const int *, const double *, const double *, const int *, const double *, const int *, const double *, double *, const int *);\nint BLASFUNC(cgemm)(const char *, const char *, const int *, const int *, const int *, const float  *, const float  *, const int *, const float  *, const int *, const float  *, float  *, const int *);\nint BLASFUNC(zgemm)(const char *, const char *, const int *, const int *, const int *, const double *, const double *, const int *, const double *, const int *, const double *, double *, const int *);\nint BLASFUNC(xgemm)(const char *, const char *, const int *, const int *, const int *, const double *, const double *, const int *, const double *, const int *, const double *, double *, const int *);\n\nint BLASFUNC(cgemm3m)(char *, char *, int *, int *, int *, float *,\n\t   float  *, int *, float  *, int *, float  *, float  *, int *);\nint BLASFUNC(zgemm3m)(char *, char *, int *, int *, int *, double *,\n\t   double *, int *, double *, int *, double *, double *, int *);\nint BLASFUNC(xgemm3m)(char *, char *, int *, int *, int *, double *,\n\t   double *, int *, double *, int *, double *, double *, int *);\n\nint BLASFUNC(sge2mm)(char *, char *, char *, int *, int *,\n\t\t     float *, float  *, int *, float  *, int *,\n\t\t     float *, float  *, int *);\nint BLASFUNC(dge2mm)(char *, char *, char *, int *, int *,\n\t\t     double *, double  *, int *, double  *, int *,\n\t\t     double *, double  *, int *);\nint BLASFUNC(cge2mm)(char *, char *, char *, int *, int *,\n\t\t     float *, float  *, int *, float  *, int *,\n\t\t     float *, float  *, int *);\nint BLASFUNC(zge2mm)(char *, char *, char *, int *, int *,\n\t\t     double *, double  *, int *, double  *, int *,\n\t\t     double *, double  *, int *);\n\nint BLASFUNC(strsm)(const char *, const char *, const char *, const char *, const int *, const int *, const float *,  const float *,  const int *, float *,  const int *);\nint BLASFUNC(dtrsm)(const char *, const char *, const char *, const char *, const int *, const int *, const double *, const double *, const int *, double *, const int *);\nint BLASFUNC(qtrsm)(const char *, const char *, const char *, const char *, const int *, const int *, const double *, const double *, const int *, double *, const int *);\nint BLASFUNC(ctrsm)(const char *, const char *, const char *, const char *, const int *, const int *, const float *,  const float *,  const int *, float *,  const int *);\nint BLASFUNC(ztrsm)(const char *, const char *, const char *, const char *, const int *, const int *, const double *, const double *, const int *, double *, const int *);\nint BLASFUNC(xtrsm)(const char *, const char *, const char *, const char *, const int *, const int *, const double *, const double *, const int *, double *, const int *);\n\nint BLASFUNC(strmm)(const char *, const char *, const char *, const char *, const int *, const int *, const float *,  const float *,  const int *, float *,  const int *);\nint BLASFUNC(dtrmm)(const char *, const char *, const char *, const char *, const int *, const int *, const double *, const double *, const int *, double *, const int *);\nint BLASFUNC(qtrmm)(const char *, const char *, const char *, const char *, const int *, const int *, const double *, const double *, const int *, double *, const int *);\nint BLASFUNC(ctrmm)(const char *, const char *, const char *, const char *, const int *, const int *, const float *,  const float *,  const int *, float *,  const int *);\nint BLASFUNC(ztrmm)(const char *, const char *, const char *, const char *, const int *, const int *, const double *, const double *, const int *, double *, const int *);\nint BLASFUNC(xtrmm)(const char *, const char *, const char *, const char *, const int *, const int *, const double *, const double *, const int *, double *, const int *);\n\nint BLASFUNC(ssymm)(const char *, const char *, const int *, const int *, const float  *, const float  *, const int *, const float  *, const int *, const float  *, float  *, const int *);\nint BLASFUNC(dsymm)(const char *, const char *, const int *, const int *, const double *, const double *, const int *, const double *, const int *, const double *, double *, const int *);\nint BLASFUNC(qsymm)(const char *, const char *, const int *, const int *, const double *, const double *, const int *, const double *, const int *, const double *, double *, const int *);\nint BLASFUNC(csymm)(const char *, const char *, const int *, const int *, const float  *, const float  *, const int *, const float  *, const int *, const float  *, float  *, const int *);\nint BLASFUNC(zsymm)(const char *, const char *, const int *, const int *, const double *, const double *, const int *, const double *, const int *, const double *, double *, const int *);\nint BLASFUNC(xsymm)(const char *, const char *, const int *, const int *, const double *, const double *, const int *, const double *, const int *, const double *, double *, const int *);\n\nint BLASFUNC(csymm3m)(char *, char *, int *, int *, float  *, float  *, int *, float  *, int *, float  *, float  *, int *);\nint BLASFUNC(zsymm3m)(char *, char *, int *, int *, double *, double *, int *, double *, int *, double *, double *, int *);\nint BLASFUNC(xsymm3m)(char *, char *, int *, int *, double *, double *, int *, double *, int *, double *, double *, int *);\n\nint BLASFUNC(ssyrk)(const char *, const char *, const int *, const int *, const float  *, const float  *, const int *, const float  *, float  *, const int *);\nint BLASFUNC(dsyrk)(const char *, const char *, const int *, const int *, const double *, const double *, const int *, const double *, double *, const int *);\nint BLASFUNC(qsyrk)(const char *, const char *, const int *, const int *, const double *, const double *, const int *, const double *, double *, const int *);\nint BLASFUNC(csyrk)(const char *, const char *, const int *, const int *, const float  *, const float  *, const int *, const float  *, float  *, const int *);\nint BLASFUNC(zsyrk)(const char *, const char *, const int *, const int *, const double *, const double *, const int *, const double *, double *, const int *);\nint BLASFUNC(xsyrk)(const char *, const char *, const int *, const int *, const double *, const double *, const int *, const double *, double *, const int *);\n\nint BLASFUNC(ssyr2k)(const char *, const char *, const int *, const int *, const float  *, const float  *, const int *, const float *, const int *, const float  *, float  *, const int *);\nint BLASFUNC(dsyr2k)(const char *, const char *, const int *, const int *, const double *, const double *, const int *, const double*, const int *, const double *, double *, const int *);\nint BLASFUNC(qsyr2k)(const char *, const char *, const int *, const int *, const double *, const double *, const int *, const double*, const int *, const double *, double *, const int *);\nint BLASFUNC(csyr2k)(const char *, const char *, const int *, const int *, const float  *, const float  *, const int *, const float *, const int *, const float  *, float  *, const int *);\nint BLASFUNC(zsyr2k)(const char *, const char *, const int *, const int *, const double *, const double *, const int *, const double*, const int *, const double *, double *, const int *);\nint BLASFUNC(xsyr2k)(const char *, const char *, const int *, const int *, const double *, const double *, const int *, const double*, const int *, const double *, double *, const int *);\n\nint BLASFUNC(chemm)(const char *, const char *, const int *, const int *, const float  *, const float  *, const int *, const float  *, const int *, const float  *, float  *, const int *);\nint BLASFUNC(zhemm)(const char *, const char *, const int *, const int *, const double *, const double *, const int *, const double *, const int *, const double *, double *, const int *);\nint BLASFUNC(xhemm)(const char *, const char *, const int *, const int *, const double *, const double *, const int *, const double *, const int *, const double *, double *, const int *);\n\nint BLASFUNC(chemm3m)(char *, char *, int *, int *, float  *, float  *, int *,\n\t   float  *, int *, float  *, float  *, int *);\nint BLASFUNC(zhemm3m)(char *, char *, int *, int *, double *, double *, int *,\n\t   double *, int *, double *, double *, int *);\nint BLASFUNC(xhemm3m)(char *, char *, int *, int *, double *, double *, int *,\n\t   double *, int *, double *, double *, int *);\n\nint BLASFUNC(cherk)(const char *, const char *, const int *, const int *, const float  *, const float  *, const int *, const float  *, float  *, const int *);\nint BLASFUNC(zherk)(const char *, const char *, const int *, const int *, const double *, const double *, const int *, const double *, double *, const int *);\nint BLASFUNC(xherk)(const char *, const char *, const int *, const int *, const double *, const double *, const int *, const double *, double *, const int *);\n\nint BLASFUNC(cher2k)(const char *, const char *, const int *, const int *, const float  *, const float  *, const int *, const float  *, const int *, const float  *, float  *, const int *);\nint BLASFUNC(zher2k)(const char *, const char *, const int *, const int *, const double *, const double *, const int *, const double *, const int *, const double *, double *, const int *);\nint BLASFUNC(xher2k)(const char *, const char *, const int *, const int *, const double *, const double *, const int *, const double *, const int *, const double *, double *, const int *);\nint BLASFUNC(cher2m)(const char *, const char *, const char *, const int *, const int *, const float  *, const float  *, const int *, const float *, const int *, const float  *, float  *, const int *);\nint BLASFUNC(zher2m)(const char *, const char *, const char *, const int *, const int *, const double *, const double *, const int *, const double*, const int *, const double *, double *, const int *);\nint BLASFUNC(xher2m)(const char *, const char *, const char *, const int *, const int *, const double *, const double *, const int *, const double*, const int *, const double *, double *, const int *);\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/misc/lapack.h",
    "content": "#ifndef LAPACK_H\n#define LAPACK_H\n\n#include \"blas.h\"\n\n#ifdef __cplusplus\nextern \"C\"\n{\n#endif\n\nint BLASFUNC(csymv) (const char *, const int *, const float  *, const float  *, const int *, const float  *, const int *, const float  *, float  *, const int *);\nint BLASFUNC(zsymv) (const char *, const int *, const double *, const double *, const int *, const double *, const int *, const double *, double *, const int *);\nint BLASFUNC(xsymv) (const char *, const int *, const double *, const double *, const int *, const double *, const int *, const double *, double *, const int *);\n\n\nint BLASFUNC(cspmv) (char *, int *, float  *, float *,\n         float  *, int *, float *, float *, int *);\nint BLASFUNC(zspmv) (char *, int *, double  *, double *,\n         double  *, int *, double *, double *, int *);\nint BLASFUNC(xspmv) (char *, int *, double  *, double *,\n         double  *, int *, double *, double *, int *);\n\nint BLASFUNC(csyr) (char *, int *, float   *, float  *, int *,\n        float  *, int *);\nint BLASFUNC(zsyr) (char *, int *, double  *, double *, int *,\n        double *, int *);\nint BLASFUNC(xsyr) (char *, int *, double  *, double *, int *,\n        double *, int *);\n\nint BLASFUNC(cspr) (char *, int *, float   *, float  *, int *,\n        float  *);\nint BLASFUNC(zspr) (char *, int *, double  *, double *, int *,\n        double *);\nint BLASFUNC(xspr) (char *, int *, double  *, double *, int *,\n        double *);\n\nint BLASFUNC(sgemt)(char *, int *, int *, float  *, float  *, int *,\n        float  *, int *);\nint BLASFUNC(dgemt)(char *, int *, int *, double *, double *, int *,\n        double *, int *);\nint BLASFUNC(cgemt)(char *, int *, int *, float  *, float  *, int *,\n        float  *, int *);\nint BLASFUNC(zgemt)(char *, int *, int *, double *, double *, int *,\n        double *, int *);\n\nint BLASFUNC(sgema)(char *, char *, int *, int *, float  *,\n        float  *, int *, float *, float  *, int *, float *, int *);\nint BLASFUNC(dgema)(char *, char *, int *, int *, double *,\n        double *, int *, double*, double *, int *, double*, int *);\nint BLASFUNC(cgema)(char *, char *, int *, int *, float  *,\n        float  *, int *, float *, float  *, int *, float *, int *);\nint BLASFUNC(zgema)(char *, char *, int *, int *, double *,\n        double *, int *, double*, double *, int *, double*, int *);\n\nint BLASFUNC(sgems)(char *, char *, int *, int *, float  *,\n        float  *, int *, float *, float  *, int *, float *, int *);\nint BLASFUNC(dgems)(char *, char *, int *, int *, double *,\n        double *, int *, double*, double *, int *, double*, int *);\nint BLASFUNC(cgems)(char *, char *, int *, int *, float  *,\n        float  *, int *, float *, float  *, int *, float *, int *);\nint BLASFUNC(zgems)(char *, char *, int *, int *, double *,\n        double *, int *, double*, double *, int *, double*, int *);\n\nint BLASFUNC(sgetf2)(int *, int *, float  *, int *, int *, int *);\nint BLASFUNC(dgetf2)(int *, int *, double *, int *, int *, int *);\nint BLASFUNC(qgetf2)(int *, int *, double *, int *, int *, int *);\nint BLASFUNC(cgetf2)(int *, int *, float  *, int *, int *, int *);\nint BLASFUNC(zgetf2)(int *, int *, double *, int *, int *, int *);\nint BLASFUNC(xgetf2)(int *, int *, double *, int *, int *, int *);\n\nint BLASFUNC(sgetrf)(int *, int *, float  *, int *, int *, int *);\nint BLASFUNC(dgetrf)(int *, int *, double *, int *, int *, int *);\nint BLASFUNC(qgetrf)(int *, int *, double *, int *, int *, int *);\nint BLASFUNC(cgetrf)(int *, int *, float  *, int *, int *, int *);\nint BLASFUNC(zgetrf)(int *, int *, double *, int *, int *, int *);\nint BLASFUNC(xgetrf)(int *, int *, double *, int *, int *, int *);\n\nint BLASFUNC(slaswp)(int *, float  *, int *, int *, int *, int *, int *);\nint BLASFUNC(dlaswp)(int *, double *, int *, int *, int *, int *, int *);\nint BLASFUNC(qlaswp)(int *, double *, int *, int *, int *, int *, int *);\nint BLASFUNC(claswp)(int *, float  *, int *, int *, int *, int *, int *);\nint BLASFUNC(zlaswp)(int *, double *, int *, int *, int *, int *, int *);\nint BLASFUNC(xlaswp)(int *, double *, int *, int *, int *, int *, int *);\n\nint BLASFUNC(sgetrs)(char *, int *, int *, float  *, int *, int *, float  *, int *, int *);\nint BLASFUNC(dgetrs)(char *, int *, int *, double *, int *, int *, double *, int *, int *);\nint BLASFUNC(qgetrs)(char *, int *, int *, double *, int *, int *, double *, int *, int *);\nint BLASFUNC(cgetrs)(char *, int *, int *, float  *, int *, int *, float  *, int *, int *);\nint BLASFUNC(zgetrs)(char *, int *, int *, double *, int *, int *, double *, int *, int *);\nint BLASFUNC(xgetrs)(char *, int *, int *, double *, int *, int *, double *, int *, int *);\n\nint BLASFUNC(sgesv)(int *, int *, float  *, int *, int *, float *, int *, int *);\nint BLASFUNC(dgesv)(int *, int *, double *, int *, int *, double*, int *, int *);\nint BLASFUNC(qgesv)(int *, int *, double *, int *, int *, double*, int *, int *);\nint BLASFUNC(cgesv)(int *, int *, float  *, int *, int *, float *, int *, int *);\nint BLASFUNC(zgesv)(int *, int *, double *, int *, int *, double*, int *, int *);\nint BLASFUNC(xgesv)(int *, int *, double *, int *, int *, double*, int *, int *);\n\nint BLASFUNC(spotf2)(char *, int *, float  *, int *, int *);\nint BLASFUNC(dpotf2)(char *, int *, double *, int *, int *);\nint BLASFUNC(qpotf2)(char *, int *, double *, int *, int *);\nint BLASFUNC(cpotf2)(char *, int *, float  *, int *, int *);\nint BLASFUNC(zpotf2)(char *, int *, double *, int *, int *);\nint BLASFUNC(xpotf2)(char *, int *, double *, int *, int *);\n\nint BLASFUNC(spotrf)(char *, int *, float  *, int *, int *);\nint BLASFUNC(dpotrf)(char *, int *, double *, int *, int *);\nint BLASFUNC(qpotrf)(char *, int *, double *, int *, int *);\nint BLASFUNC(cpotrf)(char *, int *, float  *, int *, int *);\nint BLASFUNC(zpotrf)(char *, int *, double *, int *, int *);\nint BLASFUNC(xpotrf)(char *, int *, double *, int *, int *);\n\nint BLASFUNC(slauu2)(char *, int *, float  *, int *, int *);\nint BLASFUNC(dlauu2)(char *, int *, double *, int *, int *);\nint BLASFUNC(qlauu2)(char *, int *, double *, int *, int *);\nint BLASFUNC(clauu2)(char *, int *, float  *, int *, int *);\nint BLASFUNC(zlauu2)(char *, int *, double *, int *, int *);\nint BLASFUNC(xlauu2)(char *, int *, double *, int *, int *);\n\nint BLASFUNC(slauum)(char *, int *, float  *, int *, int *);\nint BLASFUNC(dlauum)(char *, int *, double *, int *, int *);\nint BLASFUNC(qlauum)(char *, int *, double *, int *, int *);\nint BLASFUNC(clauum)(char *, int *, float  *, int *, int *);\nint BLASFUNC(zlauum)(char *, int *, double *, int *, int *);\nint BLASFUNC(xlauum)(char *, int *, double *, int *, int *);\n\nint BLASFUNC(strti2)(char *, char *, int *, float  *, int *, int *);\nint BLASFUNC(dtrti2)(char *, char *, int *, double *, int *, int *);\nint BLASFUNC(qtrti2)(char *, char *, int *, double *, int *, int *);\nint BLASFUNC(ctrti2)(char *, char *, int *, float  *, int *, int *);\nint BLASFUNC(ztrti2)(char *, char *, int *, double *, int *, int *);\nint BLASFUNC(xtrti2)(char *, char *, int *, double *, int *, int *);\n\nint BLASFUNC(strtri)(char *, char *, int *, float  *, int *, int *);\nint BLASFUNC(dtrtri)(char *, char *, int *, double *, int *, int *);\nint BLASFUNC(qtrtri)(char *, char *, int *, double *, int *, int *);\nint BLASFUNC(ctrtri)(char *, char *, int *, float  *, int *, int *);\nint BLASFUNC(ztrtri)(char *, char *, int *, double *, int *, int *);\nint BLASFUNC(xtrtri)(char *, char *, int *, double *, int *, int *);\n\nint BLASFUNC(spotri)(char *, int *, float  *, int *, int *);\nint BLASFUNC(dpotri)(char *, int *, double *, int *, int *);\nint BLASFUNC(qpotri)(char *, int *, double *, int *, int *);\nint BLASFUNC(cpotri)(char *, int *, float  *, int *, int *);\nint BLASFUNC(zpotri)(char *, int *, double *, int *, int *);\nint BLASFUNC(xpotri)(char *, int *, double *, int *, int *);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/misc/lapacke.h",
    "content": "/*****************************************************************************\n  Copyright (c) 2010, Intel Corp.\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without\n  modification, are permitted provided that the following conditions are met:\n\n    * Redistributions of source code must retain the above copyright notice,\n      this list of conditions and the following disclaimer.\n    * Redistributions in binary form must reproduce the above copyright\n      notice, this list of conditions and the following disclaimer in the\n      documentation and/or other materials provided with the distribution.\n    * Neither the name of Intel Corporation nor the names of its contributors\n      may be used to endorse or promote products derived from this software\n      without specific prior written permission.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\n  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF\n  THE POSSIBILITY OF SUCH DAMAGE.\n******************************************************************************\n* Contents: Native C interface to LAPACK\n* Author: Intel Corporation\n* Generated November, 2011\n*****************************************************************************/\n\n#ifndef _MKL_LAPACKE_H_\n\n#ifndef _LAPACKE_H_\n#define _LAPACKE_H_\n\n/*\n*  Turn on HAVE_LAPACK_CONFIG_H to redefine C-LAPACK datatypes\n*/\n#ifdef HAVE_LAPACK_CONFIG_H\n#include \"lapacke_config.h\"\n#endif\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n#include <stdlib.h>\n\n#ifndef lapack_int\n#define lapack_int     int\n#endif\n\n#ifndef lapack_logical\n#define lapack_logical lapack_int\n#endif\n\n/* Complex types are structures equivalent to the\n* Fortran complex types COMPLEX(4) and COMPLEX(8).\n*\n* One can also redefine the types with his own types\n* for example by including in the code definitions like\n*\n* #define lapack_complex_float std::complex<float>\n* #define lapack_complex_double std::complex<double>\n*\n* or define these types in the command line:\n*\n* -Dlapack_complex_float=\"std::complex<float>\"\n* -Dlapack_complex_double=\"std::complex<double>\"\n*/\n\n#ifndef LAPACK_COMPLEX_CUSTOM\n\n/* Complex type (single precision) */\n#ifndef lapack_complex_float\n#include <complex.h>\n#define lapack_complex_float    float _Complex\n#endif\n\n#ifndef lapack_complex_float_real\n#define lapack_complex_float_real(z)       (creal(z))\n#endif\n\n#ifndef lapack_complex_float_imag\n#define lapack_complex_float_imag(z)       (cimag(z))\n#endif\n\nlapack_complex_float lapack_make_complex_float( float re, float im );\n\n/* Complex type (double precision) */\n#ifndef lapack_complex_double\n#include <complex.h>\n#define lapack_complex_double   double _Complex\n#endif\n\n#ifndef lapack_complex_double_real\n#define lapack_complex_double_real(z)      (creal(z))\n#endif\n\n#ifndef lapack_complex_double_imag\n#define lapack_complex_double_imag(z)       (cimag(z))\n#endif\n\nlapack_complex_double lapack_make_complex_double( double re, double im );\n\n#endif\n\n#ifndef LAPACKE_malloc\n#define LAPACKE_malloc( size ) malloc( size )\n#endif\n#ifndef LAPACKE_free\n#define LAPACKE_free( p )      free( p )\n#endif\n\n#define LAPACK_C2INT( x ) (lapack_int)(*((float*)&x ))\n#define LAPACK_Z2INT( x ) (lapack_int)(*((double*)&x ))\n\n#define LAPACK_ROW_MAJOR               101\n#define LAPACK_COL_MAJOR               102\n\n#define LAPACK_WORK_MEMORY_ERROR       -1010\n#define LAPACK_TRANSPOSE_MEMORY_ERROR  -1011\n\n/* Callback logical functions of one, two, or three arguments are used\n*  to select eigenvalues to sort to the top left of the Schur form.\n*  The value is selected if function returns TRUE (non-zero). */\n\ntypedef lapack_logical (*LAPACK_S_SELECT2) ( const float*, const float* );\ntypedef lapack_logical (*LAPACK_S_SELECT3)\n    ( const float*, const float*, const float* );\ntypedef lapack_logical (*LAPACK_D_SELECT2) ( const double*, const double* );\ntypedef lapack_logical (*LAPACK_D_SELECT3)\n    ( const double*, const double*, const double* );\n\ntypedef lapack_logical (*LAPACK_C_SELECT1) ( const lapack_complex_float* );\ntypedef lapack_logical (*LAPACK_C_SELECT2)\n    ( const lapack_complex_float*, const lapack_complex_float* );\ntypedef lapack_logical (*LAPACK_Z_SELECT1) ( const lapack_complex_double* );\ntypedef lapack_logical (*LAPACK_Z_SELECT2)\n    ( const lapack_complex_double*, const lapack_complex_double* );\n\n#include \"lapacke_mangling.h\"\n\n#define LAPACK_lsame LAPACK_GLOBAL(lsame,LSAME)\nlapack_logical LAPACK_lsame( char* ca,  char* cb,\n                              lapack_int lca, lapack_int lcb );\n\n/* C-LAPACK function prototypes */\n\nlapack_int LAPACKE_sbdsdc( int matrix_order, char uplo, char compq,\n                           lapack_int n, float* d, float* e, float* u,\n                           lapack_int ldu, float* vt, lapack_int ldvt, float* q,\n                           lapack_int* iq );\nlapack_int LAPACKE_dbdsdc( int matrix_order, char uplo, char compq,\n                           lapack_int n, double* d, double* e, double* u,\n                           lapack_int ldu, double* vt, lapack_int ldvt,\n                           double* q, lapack_int* iq );\n\nlapack_int LAPACKE_sbdsqr( int matrix_order, char uplo, lapack_int n,\n                           lapack_int ncvt, lapack_int nru, lapack_int ncc,\n                           float* d, float* e, float* vt, lapack_int ldvt,\n                           float* u, lapack_int ldu, float* c, lapack_int ldc );\nlapack_int LAPACKE_dbdsqr( int matrix_order, char uplo, lapack_int n,\n                           lapack_int ncvt, lapack_int nru, lapack_int ncc,\n                           double* d, double* e, double* vt, lapack_int ldvt,\n                           double* u, lapack_int ldu, double* c,\n                           lapack_int ldc );\nlapack_int LAPACKE_cbdsqr( int matrix_order, char uplo, lapack_int n,\n                           lapack_int ncvt, lapack_int nru, lapack_int ncc,\n                           float* d, float* e, lapack_complex_float* vt,\n                           lapack_int ldvt, lapack_complex_float* u,\n                           lapack_int ldu, lapack_complex_float* c,\n                           lapack_int ldc );\nlapack_int LAPACKE_zbdsqr( int matrix_order, char uplo, lapack_int n,\n                           lapack_int ncvt, lapack_int nru, lapack_int ncc,\n                           double* d, double* e, lapack_complex_double* vt,\n                           lapack_int ldvt, lapack_complex_double* u,\n                           lapack_int ldu, lapack_complex_double* c,\n                           lapack_int ldc );\n\nlapack_int LAPACKE_sdisna( char job, lapack_int m, lapack_int n, const float* d,\n                           float* sep );\nlapack_int LAPACKE_ddisna( char job, lapack_int m, lapack_int n,\n                           const double* d, double* sep );\n\nlapack_int LAPACKE_sgbbrd( int matrix_order, char vect, lapack_int m,\n                           lapack_int n, lapack_int ncc, lapack_int kl,\n                           lapack_int ku, float* ab, lapack_int ldab, float* d,\n                           float* e, float* q, lapack_int ldq, float* pt,\n                           lapack_int ldpt, float* c, lapack_int ldc );\nlapack_int LAPACKE_dgbbrd( int matrix_order, char vect, lapack_int m,\n                           lapack_int n, lapack_int ncc, lapack_int kl,\n                           lapack_int ku, double* ab, lapack_int ldab,\n                           double* d, double* e, double* q, lapack_int ldq,\n                           double* pt, lapack_int ldpt, double* c,\n                           lapack_int ldc );\nlapack_int LAPACKE_cgbbrd( int matrix_order, char vect, lapack_int m,\n                           lapack_int n, lapack_int ncc, lapack_int kl,\n                           lapack_int ku, lapack_complex_float* ab,\n                           lapack_int ldab, float* d, float* e,\n                           lapack_complex_float* q, lapack_int ldq,\n                           lapack_complex_float* pt, lapack_int ldpt,\n                           lapack_complex_float* c, lapack_int ldc );\nlapack_int LAPACKE_zgbbrd( int matrix_order, char vect, lapack_int m,\n                           lapack_int n, lapack_int ncc, lapack_int kl,\n                           lapack_int ku, lapack_complex_double* ab,\n                           lapack_int ldab, double* d, double* e,\n                           lapack_complex_double* q, lapack_int ldq,\n                           lapack_complex_double* pt, lapack_int ldpt,\n                           lapack_complex_double* c, lapack_int ldc );\n\nlapack_int LAPACKE_sgbcon( int matrix_order, char norm, lapack_int n,\n                           lapack_int kl, lapack_int ku, const float* ab,\n                           lapack_int ldab, const lapack_int* ipiv, float anorm,\n                           float* rcond );\nlapack_int LAPACKE_dgbcon( int matrix_order, char norm, lapack_int n,\n                           lapack_int kl, lapack_int ku, const double* ab,\n                           lapack_int ldab, const lapack_int* ipiv,\n                           double anorm, double* rcond );\nlapack_int LAPACKE_cgbcon( int matrix_order, char norm, lapack_int n,\n                           lapack_int kl, lapack_int ku,\n                           const lapack_complex_float* ab, lapack_int ldab,\n                           const lapack_int* ipiv, float anorm, float* rcond );\nlapack_int LAPACKE_zgbcon( int matrix_order, char norm, lapack_int n,\n                           lapack_int kl, lapack_int ku,\n                           const lapack_complex_double* ab, lapack_int ldab,\n                           const lapack_int* ipiv, double anorm,\n                           double* rcond );\n\nlapack_int LAPACKE_sgbequ( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int kl, lapack_int ku, const float* ab,\n                           lapack_int ldab, float* r, float* c, float* rowcnd,\n                           float* colcnd, float* amax );\nlapack_int LAPACKE_dgbequ( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int kl, lapack_int ku, const double* ab,\n                           lapack_int ldab, double* r, double* c,\n                           double* rowcnd, double* colcnd, double* amax );\nlapack_int LAPACKE_cgbequ( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int kl, lapack_int ku,\n                           const lapack_complex_float* ab, lapack_int ldab,\n                           float* r, float* c, float* rowcnd, float* colcnd,\n                           float* amax );\nlapack_int LAPACKE_zgbequ( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int kl, lapack_int ku,\n                           const lapack_complex_double* ab, lapack_int ldab,\n                           double* r, double* c, double* rowcnd, double* colcnd,\n                           double* amax );\n\nlapack_int LAPACKE_sgbequb( int matrix_order, lapack_int m, lapack_int n,\n                            lapack_int kl, lapack_int ku, const float* ab,\n                            lapack_int ldab, float* r, float* c, float* rowcnd,\n                            float* colcnd, float* amax );\nlapack_int LAPACKE_dgbequb( int matrix_order, lapack_int m, lapack_int n,\n                            lapack_int kl, lapack_int ku, const double* ab,\n                            lapack_int ldab, double* r, double* c,\n                            double* rowcnd, double* colcnd, double* amax );\nlapack_int LAPACKE_cgbequb( int matrix_order, lapack_int m, lapack_int n,\n                            lapack_int kl, lapack_int ku,\n                            const lapack_complex_float* ab, lapack_int ldab,\n                            float* r, float* c, float* rowcnd, float* colcnd,\n                            float* amax );\nlapack_int LAPACKE_zgbequb( int matrix_order, lapack_int m, lapack_int n,\n                            lapack_int kl, lapack_int ku,\n                            const lapack_complex_double* ab, lapack_int ldab,\n                            double* r, double* c, double* rowcnd,\n                            double* colcnd, double* amax );\n\nlapack_int LAPACKE_sgbrfs( int matrix_order, char trans, lapack_int n,\n                           lapack_int kl, lapack_int ku, lapack_int nrhs,\n                           const float* ab, lapack_int ldab, const float* afb,\n                           lapack_int ldafb, const lapack_int* ipiv,\n                           const float* b, lapack_int ldb, float* x,\n                           lapack_int ldx, float* ferr, float* berr );\nlapack_int LAPACKE_dgbrfs( int matrix_order, char trans, lapack_int n,\n                           lapack_int kl, lapack_int ku, lapack_int nrhs,\n                           const double* ab, lapack_int ldab, const double* afb,\n                           lapack_int ldafb, const lapack_int* ipiv,\n                           const double* b, lapack_int ldb, double* x,\n                           lapack_int ldx, double* ferr, double* berr );\nlapack_int LAPACKE_cgbrfs( int matrix_order, char trans, lapack_int n,\n                           lapack_int kl, lapack_int ku, lapack_int nrhs,\n                           const lapack_complex_float* ab, lapack_int ldab,\n                           const lapack_complex_float* afb, lapack_int ldafb,\n                           const lapack_int* ipiv,\n                           const lapack_complex_float* b, lapack_int ldb,\n                           lapack_complex_float* x, lapack_int ldx, float* ferr,\n                           float* berr );\nlapack_int LAPACKE_zgbrfs( int matrix_order, char trans, lapack_int n,\n                           lapack_int kl, lapack_int ku, lapack_int nrhs,\n                           const lapack_complex_double* ab, lapack_int ldab,\n                           const lapack_complex_double* afb, lapack_int ldafb,\n                           const lapack_int* ipiv,\n                           const lapack_complex_double* b, lapack_int ldb,\n                           lapack_complex_double* x, lapack_int ldx,\n                           double* ferr, double* berr );\n\nlapack_int LAPACKE_sgbrfsx( int matrix_order, char trans, char equed,\n                            lapack_int n, lapack_int kl, lapack_int ku,\n                            lapack_int nrhs, const float* ab, lapack_int ldab,\n                            const float* afb, lapack_int ldafb,\n                            const lapack_int* ipiv, const float* r,\n                            const float* c, const float* b, lapack_int ldb,\n                            float* x, lapack_int ldx, float* rcond, float* berr,\n                            lapack_int n_err_bnds, float* err_bnds_norm,\n                            float* err_bnds_comp, lapack_int nparams,\n                            float* params );\nlapack_int LAPACKE_dgbrfsx( int matrix_order, char trans, char equed,\n                            lapack_int n, lapack_int kl, lapack_int ku,\n                            lapack_int nrhs, const double* ab, lapack_int ldab,\n                            const double* afb, lapack_int ldafb,\n                            const lapack_int* ipiv, const double* r,\n                            const double* c, const double* b, lapack_int ldb,\n                            double* x, lapack_int ldx, double* rcond,\n                            double* berr, lapack_int n_err_bnds,\n                            double* err_bnds_norm, double* err_bnds_comp,\n                            lapack_int nparams, double* params );\nlapack_int LAPACKE_cgbrfsx( int matrix_order, char trans, char equed,\n                            lapack_int n, lapack_int kl, lapack_int ku,\n                            lapack_int nrhs, const lapack_complex_float* ab,\n                            lapack_int ldab, const lapack_complex_float* afb,\n                            lapack_int ldafb, const lapack_int* ipiv,\n                            const float* r, const float* c,\n                            const lapack_complex_float* b, lapack_int ldb,\n                            lapack_complex_float* x, lapack_int ldx,\n                            float* rcond, float* berr, lapack_int n_err_bnds,\n                            float* err_bnds_norm, float* err_bnds_comp,\n                            lapack_int nparams, float* params );\nlapack_int LAPACKE_zgbrfsx( int matrix_order, char trans, char equed,\n                            lapack_int n, lapack_int kl, lapack_int ku,\n                            lapack_int nrhs, const lapack_complex_double* ab,\n                            lapack_int ldab, const lapack_complex_double* afb,\n                            lapack_int ldafb, const lapack_int* ipiv,\n                            const double* r, const double* c,\n                            const lapack_complex_double* b, lapack_int ldb,\n                            lapack_complex_double* x, lapack_int ldx,\n                            double* rcond, double* berr, lapack_int n_err_bnds,\n                            double* err_bnds_norm, double* err_bnds_comp,\n                            lapack_int nparams, double* params );\n\nlapack_int LAPACKE_sgbsv( int matrix_order, lapack_int n, lapack_int kl,\n                          lapack_int ku, lapack_int nrhs, float* ab,\n                          lapack_int ldab, lapack_int* ipiv, float* b,\n                          lapack_int ldb );\nlapack_int LAPACKE_dgbsv( int matrix_order, lapack_int n, lapack_int kl,\n                          lapack_int ku, lapack_int nrhs, double* ab,\n                          lapack_int ldab, lapack_int* ipiv, double* b,\n                          lapack_int ldb );\nlapack_int LAPACKE_cgbsv( int matrix_order, lapack_int n, lapack_int kl,\n                          lapack_int ku, lapack_int nrhs,\n                          lapack_complex_float* ab, lapack_int ldab,\n                          lapack_int* ipiv, lapack_complex_float* b,\n                          lapack_int ldb );\nlapack_int LAPACKE_zgbsv( int matrix_order, lapack_int n, lapack_int kl,\n                          lapack_int ku, lapack_int nrhs,\n                          lapack_complex_double* ab, lapack_int ldab,\n                          lapack_int* ipiv, lapack_complex_double* b,\n                          lapack_int ldb );\n\nlapack_int LAPACKE_sgbsvx( int matrix_order, char fact, char trans,\n                           lapack_int n, lapack_int kl, lapack_int ku,\n                           lapack_int nrhs, float* ab, lapack_int ldab,\n                           float* afb, lapack_int ldafb, lapack_int* ipiv,\n                           char* equed, float* r, float* c, float* b,\n                           lapack_int ldb, float* x, lapack_int ldx,\n                           float* rcond, float* ferr, float* berr,\n                           float* rpivot );\nlapack_int LAPACKE_dgbsvx( int matrix_order, char fact, char trans,\n                           lapack_int n, lapack_int kl, lapack_int ku,\n                           lapack_int nrhs, double* ab, lapack_int ldab,\n                           double* afb, lapack_int ldafb, lapack_int* ipiv,\n                           char* equed, double* r, double* c, double* b,\n                           lapack_int ldb, double* x, lapack_int ldx,\n                           double* rcond, double* ferr, double* berr,\n                           double* rpivot );\nlapack_int LAPACKE_cgbsvx( int matrix_order, char fact, char trans,\n                           lapack_int n, lapack_int kl, lapack_int ku,\n                           lapack_int nrhs, lapack_complex_float* ab,\n                           lapack_int ldab, lapack_complex_float* afb,\n                           lapack_int ldafb, lapack_int* ipiv, char* equed,\n                           float* r, float* c, lapack_complex_float* b,\n                           lapack_int ldb, lapack_complex_float* x,\n                           lapack_int ldx, float* rcond, float* ferr,\n                           float* berr, float* rpivot );\nlapack_int LAPACKE_zgbsvx( int matrix_order, char fact, char trans,\n                           lapack_int n, lapack_int kl, lapack_int ku,\n                           lapack_int nrhs, lapack_complex_double* ab,\n                           lapack_int ldab, lapack_complex_double* afb,\n                           lapack_int ldafb, lapack_int* ipiv, char* equed,\n                           double* r, double* c, lapack_complex_double* b,\n                           lapack_int ldb, lapack_complex_double* x,\n                           lapack_int ldx, double* rcond, double* ferr,\n                           double* berr, double* rpivot );\n\nlapack_int LAPACKE_sgbsvxx( int matrix_order, char fact, char trans,\n                            lapack_int n, lapack_int kl, lapack_int ku,\n                            lapack_int nrhs, float* ab, lapack_int ldab,\n                            float* afb, lapack_int ldafb, lapack_int* ipiv,\n                            char* equed, float* r, float* c, float* b,\n                            lapack_int ldb, float* x, lapack_int ldx,\n                            float* rcond, float* rpvgrw, float* berr,\n                            lapack_int n_err_bnds, float* err_bnds_norm,\n                            float* err_bnds_comp, lapack_int nparams,\n                            float* params );\nlapack_int LAPACKE_dgbsvxx( int matrix_order, char fact, char trans,\n                            lapack_int n, lapack_int kl, lapack_int ku,\n                            lapack_int nrhs, double* ab, lapack_int ldab,\n                            double* afb, lapack_int ldafb, lapack_int* ipiv,\n                            char* equed, double* r, double* c, double* b,\n                            lapack_int ldb, double* x, lapack_int ldx,\n                            double* rcond, double* rpvgrw, double* berr,\n                            lapack_int n_err_bnds, double* err_bnds_norm,\n                            double* err_bnds_comp, lapack_int nparams,\n                            double* params );\nlapack_int LAPACKE_cgbsvxx( int matrix_order, char fact, char trans,\n                            lapack_int n, lapack_int kl, lapack_int ku,\n                            lapack_int nrhs, lapack_complex_float* ab,\n                            lapack_int ldab, lapack_complex_float* afb,\n                            lapack_int ldafb, lapack_int* ipiv, char* equed,\n                            float* r, float* c, lapack_complex_float* b,\n                            lapack_int ldb, lapack_complex_float* x,\n                            lapack_int ldx, float* rcond, float* rpvgrw,\n                            float* berr, lapack_int n_err_bnds,\n                            float* err_bnds_norm, float* err_bnds_comp,\n                            lapack_int nparams, float* params );\nlapack_int LAPACKE_zgbsvxx( int matrix_order, char fact, char trans,\n                            lapack_int n, lapack_int kl, lapack_int ku,\n                            lapack_int nrhs, lapack_complex_double* ab,\n                            lapack_int ldab, lapack_complex_double* afb,\n                            lapack_int ldafb, lapack_int* ipiv, char* equed,\n                            double* r, double* c, lapack_complex_double* b,\n                            lapack_int ldb, lapack_complex_double* x,\n                            lapack_int ldx, double* rcond, double* rpvgrw,\n                            double* berr, lapack_int n_err_bnds,\n                            double* err_bnds_norm, double* err_bnds_comp,\n                            lapack_int nparams, double* params );\n\nlapack_int LAPACKE_sgbtrf( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int kl, lapack_int ku, float* ab,\n                           lapack_int ldab, lapack_int* ipiv );\nlapack_int LAPACKE_dgbtrf( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int kl, lapack_int ku, double* ab,\n                           lapack_int ldab, lapack_int* ipiv );\nlapack_int LAPACKE_cgbtrf( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int kl, lapack_int ku,\n                           lapack_complex_float* ab, lapack_int ldab,\n                           lapack_int* ipiv );\nlapack_int LAPACKE_zgbtrf( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int kl, lapack_int ku,\n                           lapack_complex_double* ab, lapack_int ldab,\n                           lapack_int* ipiv );\n\nlapack_int LAPACKE_sgbtrs( int matrix_order, char trans, lapack_int n,\n                           lapack_int kl, lapack_int ku, lapack_int nrhs,\n                           const float* ab, lapack_int ldab,\n                           const lapack_int* ipiv, float* b, lapack_int ldb );\nlapack_int LAPACKE_dgbtrs( int matrix_order, char trans, lapack_int n,\n                           lapack_int kl, lapack_int ku, lapack_int nrhs,\n                           const double* ab, lapack_int ldab,\n                           const lapack_int* ipiv, double* b, lapack_int ldb );\nlapack_int LAPACKE_cgbtrs( int matrix_order, char trans, lapack_int n,\n                           lapack_int kl, lapack_int ku, lapack_int nrhs,\n                           const lapack_complex_float* ab, lapack_int ldab,\n                           const lapack_int* ipiv, lapack_complex_float* b,\n                           lapack_int ldb );\nlapack_int LAPACKE_zgbtrs( int matrix_order, char trans, lapack_int n,\n                           lapack_int kl, lapack_int ku, lapack_int nrhs,\n                           const lapack_complex_double* ab, lapack_int ldab,\n                           const lapack_int* ipiv, lapack_complex_double* b,\n                           lapack_int ldb );\n\nlapack_int LAPACKE_sgebak( int matrix_order, char job, char side, lapack_int n,\n                           lapack_int ilo, lapack_int ihi, const float* scale,\n                           lapack_int m, float* v, lapack_int ldv );\nlapack_int LAPACKE_dgebak( int matrix_order, char job, char side, lapack_int n,\n                           lapack_int ilo, lapack_int ihi, const double* scale,\n                           lapack_int m, double* v, lapack_int ldv );\nlapack_int LAPACKE_cgebak( int matrix_order, char job, char side, lapack_int n,\n                           lapack_int ilo, lapack_int ihi, const float* scale,\n                           lapack_int m, lapack_complex_float* v,\n                           lapack_int ldv );\nlapack_int LAPACKE_zgebak( int matrix_order, char job, char side, lapack_int n,\n                           lapack_int ilo, lapack_int ihi, const double* scale,\n                           lapack_int m, lapack_complex_double* v,\n                           lapack_int ldv );\n\nlapack_int LAPACKE_sgebal( int matrix_order, char job, lapack_int n, float* a,\n                           lapack_int lda, lapack_int* ilo, lapack_int* ihi,\n                           float* scale );\nlapack_int LAPACKE_dgebal( int matrix_order, char job, lapack_int n, double* a,\n                           lapack_int lda, lapack_int* ilo, lapack_int* ihi,\n                           double* scale );\nlapack_int LAPACKE_cgebal( int matrix_order, char job, lapack_int n,\n                           lapack_complex_float* a, lapack_int lda,\n                           lapack_int* ilo, lapack_int* ihi, float* scale );\nlapack_int LAPACKE_zgebal( int matrix_order, char job, lapack_int n,\n                           lapack_complex_double* a, lapack_int lda,\n                           lapack_int* ilo, lapack_int* ihi, double* scale );\n\nlapack_int LAPACKE_sgebrd( int matrix_order, lapack_int m, lapack_int n,\n                           float* a, lapack_int lda, float* d, float* e,\n                           float* tauq, float* taup );\nlapack_int LAPACKE_dgebrd( int matrix_order, lapack_int m, lapack_int n,\n                           double* a, lapack_int lda, double* d, double* e,\n                           double* tauq, double* taup );\nlapack_int LAPACKE_cgebrd( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_complex_float* a, lapack_int lda, float* d,\n                           float* e, lapack_complex_float* tauq,\n                           lapack_complex_float* taup );\nlapack_int LAPACKE_zgebrd( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_complex_double* a, lapack_int lda, double* d,\n                           double* e, lapack_complex_double* tauq,\n                           lapack_complex_double* taup );\n\nlapack_int LAPACKE_sgecon( int matrix_order, char norm, lapack_int n,\n                           const float* a, lapack_int lda, float anorm,\n                           float* rcond );\nlapack_int LAPACKE_dgecon( int matrix_order, char norm, lapack_int n,\n                           const double* a, lapack_int lda, double anorm,\n                           double* rcond );\nlapack_int LAPACKE_cgecon( int matrix_order, char norm, lapack_int n,\n                           const lapack_complex_float* a, lapack_int lda,\n                           float anorm, float* rcond );\nlapack_int LAPACKE_zgecon( int matrix_order, char norm, lapack_int n,\n                           const lapack_complex_double* a, lapack_int lda,\n                           double anorm, double* rcond );\n\nlapack_int LAPACKE_sgeequ( int matrix_order, lapack_int m, lapack_int n,\n                           const float* a, lapack_int lda, float* r, float* c,\n                           float* rowcnd, float* colcnd, float* amax );\nlapack_int LAPACKE_dgeequ( int matrix_order, lapack_int m, lapack_int n,\n                           const double* a, lapack_int lda, double* r,\n                           double* c, double* rowcnd, double* colcnd,\n                           double* amax );\nlapack_int LAPACKE_cgeequ( int matrix_order, lapack_int m, lapack_int n,\n                           const lapack_complex_float* a, lapack_int lda,\n                           float* r, float* c, float* rowcnd, float* colcnd,\n                           float* amax );\nlapack_int LAPACKE_zgeequ( int matrix_order, lapack_int m, lapack_int n,\n                           const lapack_complex_double* a, lapack_int lda,\n                           double* r, double* c, double* rowcnd, double* colcnd,\n                           double* amax );\n\nlapack_int LAPACKE_sgeequb( int matrix_order, lapack_int m, lapack_int n,\n                            const float* a, lapack_int lda, float* r, float* c,\n                            float* rowcnd, float* colcnd, float* amax );\nlapack_int LAPACKE_dgeequb( int matrix_order, lapack_int m, lapack_int n,\n                            const double* a, lapack_int lda, double* r,\n                            double* c, double* rowcnd, double* colcnd,\n                            double* amax );\nlapack_int LAPACKE_cgeequb( int matrix_order, lapack_int m, lapack_int n,\n                            const lapack_complex_float* a, lapack_int lda,\n                            float* r, float* c, float* rowcnd, float* colcnd,\n                            float* amax );\nlapack_int LAPACKE_zgeequb( int matrix_order, lapack_int m, lapack_int n,\n                            const lapack_complex_double* a, lapack_int lda,\n                            double* r, double* c, double* rowcnd,\n                            double* colcnd, double* amax );\n\nlapack_int LAPACKE_sgees( int matrix_order, char jobvs, char sort,\n                          LAPACK_S_SELECT2 select, lapack_int n, float* a,\n                          lapack_int lda, lapack_int* sdim, float* wr,\n                          float* wi, float* vs, lapack_int ldvs );\nlapack_int LAPACKE_dgees( int matrix_order, char jobvs, char sort,\n                          LAPACK_D_SELECT2 select, lapack_int n, double* a,\n                          lapack_int lda, lapack_int* sdim, double* wr,\n                          double* wi, double* vs, lapack_int ldvs );\nlapack_int LAPACKE_cgees( int matrix_order, char jobvs, char sort,\n                          LAPACK_C_SELECT1 select, lapack_int n,\n                          lapack_complex_float* a, lapack_int lda,\n                          lapack_int* sdim, lapack_complex_float* w,\n                          lapack_complex_float* vs, lapack_int ldvs );\nlapack_int LAPACKE_zgees( int matrix_order, char jobvs, char sort,\n                          LAPACK_Z_SELECT1 select, lapack_int n,\n                          lapack_complex_double* a, lapack_int lda,\n                          lapack_int* sdim, lapack_complex_double* w,\n                          lapack_complex_double* vs, lapack_int ldvs );\n\nlapack_int LAPACKE_sgeesx( int matrix_order, char jobvs, char sort,\n                           LAPACK_S_SELECT2 select, char sense, lapack_int n,\n                           float* a, lapack_int lda, lapack_int* sdim,\n                           float* wr, float* wi, float* vs, lapack_int ldvs,\n                           float* rconde, float* rcondv );\nlapack_int LAPACKE_dgeesx( int matrix_order, char jobvs, char sort,\n                           LAPACK_D_SELECT2 select, char sense, lapack_int n,\n                           double* a, lapack_int lda, lapack_int* sdim,\n                           double* wr, double* wi, double* vs, lapack_int ldvs,\n                           double* rconde, double* rcondv );\nlapack_int LAPACKE_cgeesx( int matrix_order, char jobvs, char sort,\n                           LAPACK_C_SELECT1 select, char sense, lapack_int n,\n                           lapack_complex_float* a, lapack_int lda,\n                           lapack_int* sdim, lapack_complex_float* w,\n                           lapack_complex_float* vs, lapack_int ldvs,\n                           float* rconde, float* rcondv );\nlapack_int LAPACKE_zgeesx( int matrix_order, char jobvs, char sort,\n                           LAPACK_Z_SELECT1 select, char sense, lapack_int n,\n                           lapack_complex_double* a, lapack_int lda,\n                           lapack_int* sdim, lapack_complex_double* w,\n                           lapack_complex_double* vs, lapack_int ldvs,\n                           double* rconde, double* rcondv );\n\nlapack_int LAPACKE_sgeev( int matrix_order, char jobvl, char jobvr,\n                          lapack_int n, float* a, lapack_int lda, float* wr,\n                          float* wi, float* vl, lapack_int ldvl, float* vr,\n                          lapack_int ldvr );\nlapack_int LAPACKE_dgeev( int matrix_order, char jobvl, char jobvr,\n                          lapack_int n, double* a, lapack_int lda, double* wr,\n                          double* wi, double* vl, lapack_int ldvl, double* vr,\n                          lapack_int ldvr );\nlapack_int LAPACKE_cgeev( int matrix_order, char jobvl, char jobvr,\n                          lapack_int n, lapack_complex_float* a, lapack_int lda,\n                          lapack_complex_float* w, lapack_complex_float* vl,\n                          lapack_int ldvl, lapack_complex_float* vr,\n                          lapack_int ldvr );\nlapack_int LAPACKE_zgeev( int matrix_order, char jobvl, char jobvr,\n                          lapack_int n, lapack_complex_double* a,\n                          lapack_int lda, lapack_complex_double* w,\n                          lapack_complex_double* vl, lapack_int ldvl,\n                          lapack_complex_double* vr, lapack_int ldvr );\n\nlapack_int LAPACKE_sgeevx( int matrix_order, char balanc, char jobvl,\n                           char jobvr, char sense, lapack_int n, float* a,\n                           lapack_int lda, float* wr, float* wi, float* vl,\n                           lapack_int ldvl, float* vr, lapack_int ldvr,\n                           lapack_int* ilo, lapack_int* ihi, float* scale,\n                           float* abnrm, float* rconde, float* rcondv );\nlapack_int LAPACKE_dgeevx( int matrix_order, char balanc, char jobvl,\n                           char jobvr, char sense, lapack_int n, double* a,\n                           lapack_int lda, double* wr, double* wi, double* vl,\n                           lapack_int ldvl, double* vr, lapack_int ldvr,\n                           lapack_int* ilo, lapack_int* ihi, double* scale,\n                           double* abnrm, double* rconde, double* rcondv );\nlapack_int LAPACKE_cgeevx( int matrix_order, char balanc, char jobvl,\n                           char jobvr, char sense, lapack_int n,\n                           lapack_complex_float* a, lapack_int lda,\n                           lapack_complex_float* w, lapack_complex_float* vl,\n                           lapack_int ldvl, lapack_complex_float* vr,\n                           lapack_int ldvr, lapack_int* ilo, lapack_int* ihi,\n                           float* scale, float* abnrm, float* rconde,\n                           float* rcondv );\nlapack_int LAPACKE_zgeevx( int matrix_order, char balanc, char jobvl,\n                           char jobvr, char sense, lapack_int n,\n                           lapack_complex_double* a, lapack_int lda,\n                           lapack_complex_double* w, lapack_complex_double* vl,\n                           lapack_int ldvl, lapack_complex_double* vr,\n                           lapack_int ldvr, lapack_int* ilo, lapack_int* ihi,\n                           double* scale, double* abnrm, double* rconde,\n                           double* rcondv );\n\nlapack_int LAPACKE_sgehrd( int matrix_order, lapack_int n, lapack_int ilo,\n                           lapack_int ihi, float* a, lapack_int lda,\n                           float* tau );\nlapack_int LAPACKE_dgehrd( int matrix_order, lapack_int n, lapack_int ilo,\n                           lapack_int ihi, double* a, lapack_int lda,\n                           double* tau );\nlapack_int LAPACKE_cgehrd( int matrix_order, lapack_int n, lapack_int ilo,\n                           lapack_int ihi, lapack_complex_float* a,\n                           lapack_int lda, lapack_complex_float* tau );\nlapack_int LAPACKE_zgehrd( int matrix_order, lapack_int n, lapack_int ilo,\n                           lapack_int ihi, lapack_complex_double* a,\n                           lapack_int lda, lapack_complex_double* tau );\n\nlapack_int LAPACKE_sgejsv( int matrix_order, char joba, char jobu, char jobv,\n                           char jobr, char jobt, char jobp, lapack_int m,\n                           lapack_int n, float* a, lapack_int lda, float* sva,\n                           float* u, lapack_int ldu, float* v, lapack_int ldv,\n                           float* stat, lapack_int* istat );\nlapack_int LAPACKE_dgejsv( int matrix_order, char joba, char jobu, char jobv,\n                           char jobr, char jobt, char jobp, lapack_int m,\n                           lapack_int n, double* a, lapack_int lda, double* sva,\n                           double* u, lapack_int ldu, double* v, lapack_int ldv,\n                           double* stat, lapack_int* istat );\n\nlapack_int LAPACKE_sgelq2( int matrix_order, lapack_int m, lapack_int n,\n                           float* a, lapack_int lda, float* tau );\nlapack_int LAPACKE_dgelq2( int matrix_order, lapack_int m, lapack_int n,\n                           double* a, lapack_int lda, double* tau );\nlapack_int LAPACKE_cgelq2( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_complex_float* a, lapack_int lda,\n                           lapack_complex_float* tau );\nlapack_int LAPACKE_zgelq2( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_complex_double* a, lapack_int lda,\n                           lapack_complex_double* tau );\n\nlapack_int LAPACKE_sgelqf( int matrix_order, lapack_int m, lapack_int n,\n                           float* a, lapack_int lda, float* tau );\nlapack_int LAPACKE_dgelqf( int matrix_order, lapack_int m, lapack_int n,\n                           double* a, lapack_int lda, double* tau );\nlapack_int LAPACKE_cgelqf( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_complex_float* a, lapack_int lda,\n                           lapack_complex_float* tau );\nlapack_int LAPACKE_zgelqf( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_complex_double* a, lapack_int lda,\n                           lapack_complex_double* tau );\n\nlapack_int LAPACKE_sgels( int matrix_order, char trans, lapack_int m,\n                          lapack_int n, lapack_int nrhs, float* a,\n                          lapack_int lda, float* b, lapack_int ldb );\nlapack_int LAPACKE_dgels( int matrix_order, char trans, lapack_int m,\n                          lapack_int n, lapack_int nrhs, double* a,\n                          lapack_int lda, double* b, lapack_int ldb );\nlapack_int LAPACKE_cgels( int matrix_order, char trans, lapack_int m,\n                          lapack_int n, lapack_int nrhs,\n                          lapack_complex_float* a, lapack_int lda,\n                          lapack_complex_float* b, lapack_int ldb );\nlapack_int LAPACKE_zgels( int matrix_order, char trans, lapack_int m,\n                          lapack_int n, lapack_int nrhs,\n                          lapack_complex_double* a, lapack_int lda,\n                          lapack_complex_double* b, lapack_int ldb );\n\nlapack_int LAPACKE_sgelsd( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int nrhs, float* a, lapack_int lda, float* b,\n                           lapack_int ldb, float* s, float rcond,\n                           lapack_int* rank );\nlapack_int LAPACKE_dgelsd( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int nrhs, double* a, lapack_int lda,\n                           double* b, lapack_int ldb, double* s, double rcond,\n                           lapack_int* rank );\nlapack_int LAPACKE_cgelsd( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int nrhs, lapack_complex_float* a,\n                           lapack_int lda, lapack_complex_float* b,\n                           lapack_int ldb, float* s, float rcond,\n                           lapack_int* rank );\nlapack_int LAPACKE_zgelsd( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int nrhs, lapack_complex_double* a,\n                           lapack_int lda, lapack_complex_double* b,\n                           lapack_int ldb, double* s, double rcond,\n                           lapack_int* rank );\n\nlapack_int LAPACKE_sgelss( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int nrhs, float* a, lapack_int lda, float* b,\n                           lapack_int ldb, float* s, float rcond,\n                           lapack_int* rank );\nlapack_int LAPACKE_dgelss( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int nrhs, double* a, lapack_int lda,\n                           double* b, lapack_int ldb, double* s, double rcond,\n                           lapack_int* rank );\nlapack_int LAPACKE_cgelss( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int nrhs, lapack_complex_float* a,\n                           lapack_int lda, lapack_complex_float* b,\n                           lapack_int ldb, float* s, float rcond,\n                           lapack_int* rank );\nlapack_int LAPACKE_zgelss( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int nrhs, lapack_complex_double* a,\n                           lapack_int lda, lapack_complex_double* b,\n                           lapack_int ldb, double* s, double rcond,\n                           lapack_int* rank );\n\nlapack_int LAPACKE_sgelsy( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int nrhs, float* a, lapack_int lda, float* b,\n                           lapack_int ldb, lapack_int* jpvt, float rcond,\n                           lapack_int* rank );\nlapack_int LAPACKE_dgelsy( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int nrhs, double* a, lapack_int lda,\n                           double* b, lapack_int ldb, lapack_int* jpvt,\n                           double rcond, lapack_int* rank );\nlapack_int LAPACKE_cgelsy( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int nrhs, lapack_complex_float* a,\n                           lapack_int lda, lapack_complex_float* b,\n                           lapack_int ldb, lapack_int* jpvt, float rcond,\n                           lapack_int* rank );\nlapack_int LAPACKE_zgelsy( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int nrhs, lapack_complex_double* a,\n                           lapack_int lda, lapack_complex_double* b,\n                           lapack_int ldb, lapack_int* jpvt, double rcond,\n                           lapack_int* rank );\n\nlapack_int LAPACKE_sgeqlf( int matrix_order, lapack_int m, lapack_int n,\n                           float* a, lapack_int lda, float* tau );\nlapack_int LAPACKE_dgeqlf( int matrix_order, lapack_int m, lapack_int n,\n                           double* a, lapack_int lda, double* tau );\nlapack_int LAPACKE_cgeqlf( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_complex_float* a, lapack_int lda,\n                           lapack_complex_float* tau );\nlapack_int LAPACKE_zgeqlf( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_complex_double* a, lapack_int lda,\n                           lapack_complex_double* tau );\n\nlapack_int LAPACKE_sgeqp3( int matrix_order, lapack_int m, lapack_int n,\n                           float* a, lapack_int lda, lapack_int* jpvt,\n                           float* tau );\nlapack_int LAPACKE_dgeqp3( int matrix_order, lapack_int m, lapack_int n,\n                           double* a, lapack_int lda, lapack_int* jpvt,\n                           double* tau );\nlapack_int LAPACKE_cgeqp3( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_complex_float* a, lapack_int lda,\n                           lapack_int* jpvt, lapack_complex_float* tau );\nlapack_int LAPACKE_zgeqp3( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_complex_double* a, lapack_int lda,\n                           lapack_int* jpvt, lapack_complex_double* tau );\n\nlapack_int LAPACKE_sgeqpf( int matrix_order, lapack_int m, lapack_int n,\n                           float* a, lapack_int lda, lapack_int* jpvt,\n                           float* tau );\nlapack_int LAPACKE_dgeqpf( int matrix_order, lapack_int m, lapack_int n,\n                           double* a, lapack_int lda, lapack_int* jpvt,\n                           double* tau );\nlapack_int LAPACKE_cgeqpf( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_complex_float* a, lapack_int lda,\n                           lapack_int* jpvt, lapack_complex_float* tau );\nlapack_int LAPACKE_zgeqpf( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_complex_double* a, lapack_int lda,\n                           lapack_int* jpvt, lapack_complex_double* tau );\n\nlapack_int LAPACKE_sgeqr2( int matrix_order, lapack_int m, lapack_int n,\n                           float* a, lapack_int lda, float* tau );\nlapack_int LAPACKE_dgeqr2( int matrix_order, lapack_int m, lapack_int n,\n                           double* a, lapack_int lda, double* tau );\nlapack_int LAPACKE_cgeqr2( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_complex_float* a, lapack_int lda,\n                           lapack_complex_float* tau );\nlapack_int LAPACKE_zgeqr2( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_complex_double* a, lapack_int lda,\n                           lapack_complex_double* tau );\n\nlapack_int LAPACKE_sgeqrf( int matrix_order, lapack_int m, lapack_int n,\n                           float* a, lapack_int lda, float* tau );\nlapack_int LAPACKE_dgeqrf( int matrix_order, lapack_int m, lapack_int n,\n                           double* a, lapack_int lda, double* tau );\nlapack_int LAPACKE_cgeqrf( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_complex_float* a, lapack_int lda,\n                           lapack_complex_float* tau );\nlapack_int LAPACKE_zgeqrf( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_complex_double* a, lapack_int lda,\n                           lapack_complex_double* tau );\n\nlapack_int LAPACKE_sgeqrfp( int matrix_order, lapack_int m, lapack_int n,\n                            float* a, lapack_int lda, float* tau );\nlapack_int LAPACKE_dgeqrfp( int matrix_order, lapack_int m, lapack_int n,\n                            double* a, lapack_int lda, double* tau );\nlapack_int LAPACKE_cgeqrfp( int matrix_order, lapack_int m, lapack_int n,\n                            lapack_complex_float* a, lapack_int lda,\n                            lapack_complex_float* tau );\nlapack_int LAPACKE_zgeqrfp( int matrix_order, lapack_int m, lapack_int n,\n                            lapack_complex_double* a, lapack_int lda,\n                            lapack_complex_double* tau );\n\nlapack_int LAPACKE_sgerfs( int matrix_order, char trans, lapack_int n,\n                           lapack_int nrhs, const float* a, lapack_int lda,\n                           const float* af, lapack_int ldaf,\n                           const lapack_int* ipiv, const float* b,\n                           lapack_int ldb, float* x, lapack_int ldx,\n                           float* ferr, float* berr );\nlapack_int LAPACKE_dgerfs( int matrix_order, char trans, lapack_int n,\n                           lapack_int nrhs, const double* a, lapack_int lda,\n                           const double* af, lapack_int ldaf,\n                           const lapack_int* ipiv, const double* b,\n                           lapack_int ldb, double* x, lapack_int ldx,\n                           double* ferr, double* berr );\nlapack_int LAPACKE_cgerfs( int matrix_order, char trans, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_float* a,\n                           lapack_int lda, const lapack_complex_float* af,\n                           lapack_int ldaf, const lapack_int* ipiv,\n                           const lapack_complex_float* b, lapack_int ldb,\n                           lapack_complex_float* x, lapack_int ldx, float* ferr,\n                           float* berr );\nlapack_int LAPACKE_zgerfs( int matrix_order, char trans, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_double* a,\n                           lapack_int lda, const lapack_complex_double* af,\n                           lapack_int ldaf, const lapack_int* ipiv,\n                           const lapack_complex_double* b, lapack_int ldb,\n                           lapack_complex_double* x, lapack_int ldx,\n                           double* ferr, double* berr );\n\nlapack_int LAPACKE_sgerfsx( int matrix_order, char trans, char equed,\n                            lapack_int n, lapack_int nrhs, const float* a,\n                            lapack_int lda, const float* af, lapack_int ldaf,\n                            const lapack_int* ipiv, const float* r,\n                            const float* c, const float* b, lapack_int ldb,\n                            float* x, lapack_int ldx, float* rcond, float* berr,\n                            lapack_int n_err_bnds, float* err_bnds_norm,\n                            float* err_bnds_comp, lapack_int nparams,\n                            float* params );\nlapack_int LAPACKE_dgerfsx( int matrix_order, char trans, char equed,\n                            lapack_int n, lapack_int nrhs, const double* a,\n                            lapack_int lda, const double* af, lapack_int ldaf,\n                            const lapack_int* ipiv, const double* r,\n                            const double* c, const double* b, lapack_int ldb,\n                            double* x, lapack_int ldx, double* rcond,\n                            double* berr, lapack_int n_err_bnds,\n                            double* err_bnds_norm, double* err_bnds_comp,\n                            lapack_int nparams, double* params );\nlapack_int LAPACKE_cgerfsx( int matrix_order, char trans, char equed,\n                            lapack_int n, lapack_int nrhs,\n                            const lapack_complex_float* a, lapack_int lda,\n                            const lapack_complex_float* af, lapack_int ldaf,\n                            const lapack_int* ipiv, const float* r,\n                            const float* c, const lapack_complex_float* b,\n                            lapack_int ldb, lapack_complex_float* x,\n                            lapack_int ldx, float* rcond, float* berr,\n                            lapack_int n_err_bnds, float* err_bnds_norm,\n                            float* err_bnds_comp, lapack_int nparams,\n                            float* params );\nlapack_int LAPACKE_zgerfsx( int matrix_order, char trans, char equed,\n                            lapack_int n, lapack_int nrhs,\n                            const lapack_complex_double* a, lapack_int lda,\n                            const lapack_complex_double* af, lapack_int ldaf,\n                            const lapack_int* ipiv, const double* r,\n                            const double* c, const lapack_complex_double* b,\n                            lapack_int ldb, lapack_complex_double* x,\n                            lapack_int ldx, double* rcond, double* berr,\n                            lapack_int n_err_bnds, double* err_bnds_norm,\n                            double* err_bnds_comp, lapack_int nparams,\n                            double* params );\n\nlapack_int LAPACKE_sgerqf( int matrix_order, lapack_int m, lapack_int n,\n                           float* a, lapack_int lda, float* tau );\nlapack_int LAPACKE_dgerqf( int matrix_order, lapack_int m, lapack_int n,\n                           double* a, lapack_int lda, double* tau );\nlapack_int LAPACKE_cgerqf( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_complex_float* a, lapack_int lda,\n                           lapack_complex_float* tau );\nlapack_int LAPACKE_zgerqf( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_complex_double* a, lapack_int lda,\n                           lapack_complex_double* tau );\n\nlapack_int LAPACKE_sgesdd( int matrix_order, char jobz, lapack_int m,\n                           lapack_int n, float* a, lapack_int lda, float* s,\n                           float* u, lapack_int ldu, float* vt,\n                           lapack_int ldvt );\nlapack_int LAPACKE_dgesdd( int matrix_order, char jobz, lapack_int m,\n                           lapack_int n, double* a, lapack_int lda, double* s,\n                           double* u, lapack_int ldu, double* vt,\n                           lapack_int ldvt );\nlapack_int LAPACKE_cgesdd( int matrix_order, char jobz, lapack_int m,\n                           lapack_int n, lapack_complex_float* a,\n                           lapack_int lda, float* s, lapack_complex_float* u,\n                           lapack_int ldu, lapack_complex_float* vt,\n                           lapack_int ldvt );\nlapack_int LAPACKE_zgesdd( int matrix_order, char jobz, lapack_int m,\n                           lapack_int n, lapack_complex_double* a,\n                           lapack_int lda, double* s, lapack_complex_double* u,\n                           lapack_int ldu, lapack_complex_double* vt,\n                           lapack_int ldvt );\n\nlapack_int LAPACKE_sgesv( int matrix_order, lapack_int n, lapack_int nrhs,\n                          float* a, lapack_int lda, lapack_int* ipiv, float* b,\n                          lapack_int ldb );\nlapack_int LAPACKE_dgesv( int matrix_order, lapack_int n, lapack_int nrhs,\n                          double* a, lapack_int lda, lapack_int* ipiv,\n                          double* b, lapack_int ldb );\nlapack_int LAPACKE_cgesv( int matrix_order, lapack_int n, lapack_int nrhs,\n                          lapack_complex_float* a, lapack_int lda,\n                          lapack_int* ipiv, lapack_complex_float* b,\n                          lapack_int ldb );\nlapack_int LAPACKE_zgesv( int matrix_order, lapack_int n, lapack_int nrhs,\n                          lapack_complex_double* a, lapack_int lda,\n                          lapack_int* ipiv, lapack_complex_double* b,\n                          lapack_int ldb );\nlapack_int LAPACKE_dsgesv( int matrix_order, lapack_int n, lapack_int nrhs,\n                           double* a, lapack_int lda, lapack_int* ipiv,\n                           double* b, lapack_int ldb, double* x, lapack_int ldx,\n                           lapack_int* iter );\nlapack_int LAPACKE_zcgesv( int matrix_order, lapack_int n, lapack_int nrhs,\n                           lapack_complex_double* a, lapack_int lda,\n                           lapack_int* ipiv, lapack_complex_double* b,\n                           lapack_int ldb, lapack_complex_double* x,\n                           lapack_int ldx, lapack_int* iter );\n\nlapack_int LAPACKE_sgesvd( int matrix_order, char jobu, char jobvt,\n                           lapack_int m, lapack_int n, float* a, lapack_int lda,\n                           float* s, float* u, lapack_int ldu, float* vt,\n                           lapack_int ldvt, float* superb );\nlapack_int LAPACKE_dgesvd( int matrix_order, char jobu, char jobvt,\n                           lapack_int m, lapack_int n, double* a,\n                           lapack_int lda, double* s, double* u, lapack_int ldu,\n                           double* vt, lapack_int ldvt, double* superb );\nlapack_int LAPACKE_cgesvd( int matrix_order, char jobu, char jobvt,\n                           lapack_int m, lapack_int n, lapack_complex_float* a,\n                           lapack_int lda, float* s, lapack_complex_float* u,\n                           lapack_int ldu, lapack_complex_float* vt,\n                           lapack_int ldvt, float* superb );\nlapack_int LAPACKE_zgesvd( int matrix_order, char jobu, char jobvt,\n                           lapack_int m, lapack_int n, lapack_complex_double* a,\n                           lapack_int lda, double* s, lapack_complex_double* u,\n                           lapack_int ldu, lapack_complex_double* vt,\n                           lapack_int ldvt, double* superb );\n\nlapack_int LAPACKE_sgesvj( int matrix_order, char joba, char jobu, char jobv,\n                           lapack_int m, lapack_int n, float* a, lapack_int lda,\n                           float* sva, lapack_int mv, float* v, lapack_int ldv,\n                           float* stat );\nlapack_int LAPACKE_dgesvj( int matrix_order, char joba, char jobu, char jobv,\n                           lapack_int m, lapack_int n, double* a,\n                           lapack_int lda, double* sva, lapack_int mv,\n                           double* v, lapack_int ldv, double* stat );\n\nlapack_int LAPACKE_sgesvx( int matrix_order, char fact, char trans,\n                           lapack_int n, lapack_int nrhs, float* a,\n                           lapack_int lda, float* af, lapack_int ldaf,\n                           lapack_int* ipiv, char* equed, float* r, float* c,\n                           float* b, lapack_int ldb, float* x, lapack_int ldx,\n                           float* rcond, float* ferr, float* berr,\n                           float* rpivot );\nlapack_int LAPACKE_dgesvx( int matrix_order, char fact, char trans,\n                           lapack_int n, lapack_int nrhs, double* a,\n                           lapack_int lda, double* af, lapack_int ldaf,\n                           lapack_int* ipiv, char* equed, double* r, double* c,\n                           double* b, lapack_int ldb, double* x, lapack_int ldx,\n                           double* rcond, double* ferr, double* berr,\n                           double* rpivot );\nlapack_int LAPACKE_cgesvx( int matrix_order, char fact, char trans,\n                           lapack_int n, lapack_int nrhs,\n                           lapack_complex_float* a, lapack_int lda,\n                           lapack_complex_float* af, lapack_int ldaf,\n                           lapack_int* ipiv, char* equed, float* r, float* c,\n                           lapack_complex_float* b, lapack_int ldb,\n                           lapack_complex_float* x, lapack_int ldx,\n                           float* rcond, float* ferr, float* berr,\n                           float* rpivot );\nlapack_int LAPACKE_zgesvx( int matrix_order, char fact, char trans,\n                           lapack_int n, lapack_int nrhs,\n                           lapack_complex_double* a, lapack_int lda,\n                           lapack_complex_double* af, lapack_int ldaf,\n                           lapack_int* ipiv, char* equed, double* r, double* c,\n                           lapack_complex_double* b, lapack_int ldb,\n                           lapack_complex_double* x, lapack_int ldx,\n                           double* rcond, double* ferr, double* berr,\n                           double* rpivot );\n\nlapack_int LAPACKE_sgesvxx( int matrix_order, char fact, char trans,\n                            lapack_int n, lapack_int nrhs, float* a,\n                            lapack_int lda, float* af, lapack_int ldaf,\n                            lapack_int* ipiv, char* equed, float* r, float* c,\n                            float* b, lapack_int ldb, float* x, lapack_int ldx,\n                            float* rcond, float* rpvgrw, float* berr,\n                            lapack_int n_err_bnds, float* err_bnds_norm,\n                            float* err_bnds_comp, lapack_int nparams,\n                            float* params );\nlapack_int LAPACKE_dgesvxx( int matrix_order, char fact, char trans,\n                            lapack_int n, lapack_int nrhs, double* a,\n                            lapack_int lda, double* af, lapack_int ldaf,\n                            lapack_int* ipiv, char* equed, double* r, double* c,\n                            double* b, lapack_int ldb, double* x,\n                            lapack_int ldx, double* rcond, double* rpvgrw,\n                            double* berr, lapack_int n_err_bnds,\n                            double* err_bnds_norm, double* err_bnds_comp,\n                            lapack_int nparams, double* params );\nlapack_int LAPACKE_cgesvxx( int matrix_order, char fact, char trans,\n                            lapack_int n, lapack_int nrhs,\n                            lapack_complex_float* a, lapack_int lda,\n                            lapack_complex_float* af, lapack_int ldaf,\n                            lapack_int* ipiv, char* equed, float* r, float* c,\n                            lapack_complex_float* b, lapack_int ldb,\n                            lapack_complex_float* x, lapack_int ldx,\n                            float* rcond, float* rpvgrw, float* berr,\n                            lapack_int n_err_bnds, float* err_bnds_norm,\n                            float* err_bnds_comp, lapack_int nparams,\n                            float* params );\nlapack_int LAPACKE_zgesvxx( int matrix_order, char fact, char trans,\n                            lapack_int n, lapack_int nrhs,\n                            lapack_complex_double* a, lapack_int lda,\n                            lapack_complex_double* af, lapack_int ldaf,\n                            lapack_int* ipiv, char* equed, double* r, double* c,\n                            lapack_complex_double* b, lapack_int ldb,\n                            lapack_complex_double* x, lapack_int ldx,\n                            double* rcond, double* rpvgrw, double* berr,\n                            lapack_int n_err_bnds, double* err_bnds_norm,\n                            double* err_bnds_comp, lapack_int nparams,\n                            double* params );\n\nlapack_int LAPACKE_sgetf2( int matrix_order, lapack_int m, lapack_int n,\n                           float* a, lapack_int lda, lapack_int* ipiv );\nlapack_int LAPACKE_dgetf2( int matrix_order, lapack_int m, lapack_int n,\n                           double* a, lapack_int lda, lapack_int* ipiv );\nlapack_int LAPACKE_cgetf2( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_complex_float* a, lapack_int lda,\n                           lapack_int* ipiv );\nlapack_int LAPACKE_zgetf2( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_complex_double* a, lapack_int lda,\n                           lapack_int* ipiv );\n\nlapack_int LAPACKE_sgetrf( int matrix_order, lapack_int m, lapack_int n,\n                           float* a, lapack_int lda, lapack_int* ipiv );\nlapack_int LAPACKE_dgetrf( int matrix_order, lapack_int m, lapack_int n,\n                           double* a, lapack_int lda, lapack_int* ipiv );\nlapack_int LAPACKE_cgetrf( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_complex_float* a, lapack_int lda,\n                           lapack_int* ipiv );\nlapack_int LAPACKE_zgetrf( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_complex_double* a, lapack_int lda,\n                           lapack_int* ipiv );\n\nlapack_int LAPACKE_sgetri( int matrix_order, lapack_int n, float* a,\n                           lapack_int lda, const lapack_int* ipiv );\nlapack_int LAPACKE_dgetri( int matrix_order, lapack_int n, double* a,\n                           lapack_int lda, const lapack_int* ipiv );\nlapack_int LAPACKE_cgetri( int matrix_order, lapack_int n,\n                           lapack_complex_float* a, lapack_int lda,\n                           const lapack_int* ipiv );\nlapack_int LAPACKE_zgetri( int matrix_order, lapack_int n,\n                           lapack_complex_double* a, lapack_int lda,\n                           const lapack_int* ipiv );\n\nlapack_int LAPACKE_sgetrs( int matrix_order, char trans, lapack_int n,\n                           lapack_int nrhs, const float* a, lapack_int lda,\n                           const lapack_int* ipiv, float* b, lapack_int ldb );\nlapack_int LAPACKE_dgetrs( int matrix_order, char trans, lapack_int n,\n                           lapack_int nrhs, const double* a, lapack_int lda,\n                           const lapack_int* ipiv, double* b, lapack_int ldb );\nlapack_int LAPACKE_cgetrs( int matrix_order, char trans, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_float* a,\n                           lapack_int lda, const lapack_int* ipiv,\n                           lapack_complex_float* b, lapack_int ldb );\nlapack_int LAPACKE_zgetrs( int matrix_order, char trans, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_double* a,\n                           lapack_int lda, const lapack_int* ipiv,\n                           lapack_complex_double* b, lapack_int ldb );\n\nlapack_int LAPACKE_sggbak( int matrix_order, char job, char side, lapack_int n,\n                           lapack_int ilo, lapack_int ihi, const float* lscale,\n                           const float* rscale, lapack_int m, float* v,\n                           lapack_int ldv );\nlapack_int LAPACKE_dggbak( int matrix_order, char job, char side, lapack_int n,\n                           lapack_int ilo, lapack_int ihi, const double* lscale,\n                           const double* rscale, lapack_int m, double* v,\n                           lapack_int ldv );\nlapack_int LAPACKE_cggbak( int matrix_order, char job, char side, lapack_int n,\n                           lapack_int ilo, lapack_int ihi, const float* lscale,\n                           const float* rscale, lapack_int m,\n                           lapack_complex_float* v, lapack_int ldv );\nlapack_int LAPACKE_zggbak( int matrix_order, char job, char side, lapack_int n,\n                           lapack_int ilo, lapack_int ihi, const double* lscale,\n                           const double* rscale, lapack_int m,\n                           lapack_complex_double* v, lapack_int ldv );\n\nlapack_int LAPACKE_sggbal( int matrix_order, char job, lapack_int n, float* a,\n                           lapack_int lda, float* b, lapack_int ldb,\n                           lapack_int* ilo, lapack_int* ihi, float* lscale,\n                           float* rscale );\nlapack_int LAPACKE_dggbal( int matrix_order, char job, lapack_int n, double* a,\n                           lapack_int lda, double* b, lapack_int ldb,\n                           lapack_int* ilo, lapack_int* ihi, double* lscale,\n                           double* rscale );\nlapack_int LAPACKE_cggbal( int matrix_order, char job, lapack_int n,\n                           lapack_complex_float* a, lapack_int lda,\n                           lapack_complex_float* b, lapack_int ldb,\n                           lapack_int* ilo, lapack_int* ihi, float* lscale,\n                           float* rscale );\nlapack_int LAPACKE_zggbal( int matrix_order, char job, lapack_int n,\n                           lapack_complex_double* a, lapack_int lda,\n                           lapack_complex_double* b, lapack_int ldb,\n                           lapack_int* ilo, lapack_int* ihi, double* lscale,\n                           double* rscale );\n\nlapack_int LAPACKE_sgges( int matrix_order, char jobvsl, char jobvsr, char sort,\n                          LAPACK_S_SELECT3 selctg, lapack_int n, float* a,\n                          lapack_int lda, float* b, lapack_int ldb,\n                          lapack_int* sdim, float* alphar, float* alphai,\n                          float* beta, float* vsl, lapack_int ldvsl, float* vsr,\n                          lapack_int ldvsr );\nlapack_int LAPACKE_dgges( int matrix_order, char jobvsl, char jobvsr, char sort,\n                          LAPACK_D_SELECT3 selctg, lapack_int n, double* a,\n                          lapack_int lda, double* b, lapack_int ldb,\n                          lapack_int* sdim, double* alphar, double* alphai,\n                          double* beta, double* vsl, lapack_int ldvsl,\n                          double* vsr, lapack_int ldvsr );\nlapack_int LAPACKE_cgges( int matrix_order, char jobvsl, char jobvsr, char sort,\n                          LAPACK_C_SELECT2 selctg, lapack_int n,\n                          lapack_complex_float* a, lapack_int lda,\n                          lapack_complex_float* b, lapack_int ldb,\n                          lapack_int* sdim, lapack_complex_float* alpha,\n                          lapack_complex_float* beta, lapack_complex_float* vsl,\n                          lapack_int ldvsl, lapack_complex_float* vsr,\n                          lapack_int ldvsr );\nlapack_int LAPACKE_zgges( int matrix_order, char jobvsl, char jobvsr, char sort,\n                          LAPACK_Z_SELECT2 selctg, lapack_int n,\n                          lapack_complex_double* a, lapack_int lda,\n                          lapack_complex_double* b, lapack_int ldb,\n                          lapack_int* sdim, lapack_complex_double* alpha,\n                          lapack_complex_double* beta,\n                          lapack_complex_double* vsl, lapack_int ldvsl,\n                          lapack_complex_double* vsr, lapack_int ldvsr );\n\nlapack_int LAPACKE_sggesx( int matrix_order, char jobvsl, char jobvsr,\n                           char sort, LAPACK_S_SELECT3 selctg, char sense,\n                           lapack_int n, float* a, lapack_int lda, float* b,\n                           lapack_int ldb, lapack_int* sdim, float* alphar,\n                           float* alphai, float* beta, float* vsl,\n                           lapack_int ldvsl, float* vsr, lapack_int ldvsr,\n                           float* rconde, float* rcondv );\nlapack_int LAPACKE_dggesx( int matrix_order, char jobvsl, char jobvsr,\n                           char sort, LAPACK_D_SELECT3 selctg, char sense,\n                           lapack_int n, double* a, lapack_int lda, double* b,\n                           lapack_int ldb, lapack_int* sdim, double* alphar,\n                           double* alphai, double* beta, double* vsl,\n                           lapack_int ldvsl, double* vsr, lapack_int ldvsr,\n                           double* rconde, double* rcondv );\nlapack_int LAPACKE_cggesx( int matrix_order, char jobvsl, char jobvsr,\n                           char sort, LAPACK_C_SELECT2 selctg, char sense,\n                           lapack_int n, lapack_complex_float* a,\n                           lapack_int lda, lapack_complex_float* b,\n                           lapack_int ldb, lapack_int* sdim,\n                           lapack_complex_float* alpha,\n                           lapack_complex_float* beta,\n                           lapack_complex_float* vsl, lapack_int ldvsl,\n                           lapack_complex_float* vsr, lapack_int ldvsr,\n                           float* rconde, float* rcondv );\nlapack_int LAPACKE_zggesx( int matrix_order, char jobvsl, char jobvsr,\n                           char sort, LAPACK_Z_SELECT2 selctg, char sense,\n                           lapack_int n, lapack_complex_double* a,\n                           lapack_int lda, lapack_complex_double* b,\n                           lapack_int ldb, lapack_int* sdim,\n                           lapack_complex_double* alpha,\n                           lapack_complex_double* beta,\n                           lapack_complex_double* vsl, lapack_int ldvsl,\n                           lapack_complex_double* vsr, lapack_int ldvsr,\n                           double* rconde, double* rcondv );\n\nlapack_int LAPACKE_sggev( int matrix_order, char jobvl, char jobvr,\n                          lapack_int n, float* a, lapack_int lda, float* b,\n                          lapack_int ldb, float* alphar, float* alphai,\n                          float* beta, float* vl, lapack_int ldvl, float* vr,\n                          lapack_int ldvr );\nlapack_int LAPACKE_dggev( int matrix_order, char jobvl, char jobvr,\n                          lapack_int n, double* a, lapack_int lda, double* b,\n                          lapack_int ldb, double* alphar, double* alphai,\n                          double* beta, double* vl, lapack_int ldvl, double* vr,\n                          lapack_int ldvr );\nlapack_int LAPACKE_cggev( int matrix_order, char jobvl, char jobvr,\n                          lapack_int n, lapack_complex_float* a, lapack_int lda,\n                          lapack_complex_float* b, lapack_int ldb,\n                          lapack_complex_float* alpha,\n                          lapack_complex_float* beta, lapack_complex_float* vl,\n                          lapack_int ldvl, lapack_complex_float* vr,\n                          lapack_int ldvr );\nlapack_int LAPACKE_zggev( int matrix_order, char jobvl, char jobvr,\n                          lapack_int n, lapack_complex_double* a,\n                          lapack_int lda, lapack_complex_double* b,\n                          lapack_int ldb, lapack_complex_double* alpha,\n                          lapack_complex_double* beta,\n                          lapack_complex_double* vl, lapack_int ldvl,\n                          lapack_complex_double* vr, lapack_int ldvr );\n\nlapack_int LAPACKE_sggevx( int matrix_order, char balanc, char jobvl,\n                           char jobvr, char sense, lapack_int n, float* a,\n                           lapack_int lda, float* b, lapack_int ldb,\n                           float* alphar, float* alphai, float* beta, float* vl,\n                           lapack_int ldvl, float* vr, lapack_int ldvr,\n                           lapack_int* ilo, lapack_int* ihi, float* lscale,\n                           float* rscale, float* abnrm, float* bbnrm,\n                           float* rconde, float* rcondv );\nlapack_int LAPACKE_dggevx( int matrix_order, char balanc, char jobvl,\n                           char jobvr, char sense, lapack_int n, double* a,\n                           lapack_int lda, double* b, lapack_int ldb,\n                           double* alphar, double* alphai, double* beta,\n                           double* vl, lapack_int ldvl, double* vr,\n                           lapack_int ldvr, lapack_int* ilo, lapack_int* ihi,\n                           double* lscale, double* rscale, double* abnrm,\n                           double* bbnrm, double* rconde, double* rcondv );\nlapack_int LAPACKE_cggevx( int matrix_order, char balanc, char jobvl,\n                           char jobvr, char sense, lapack_int n,\n                           lapack_complex_float* a, lapack_int lda,\n                           lapack_complex_float* b, lapack_int ldb,\n                           lapack_complex_float* alpha,\n                           lapack_complex_float* beta, lapack_complex_float* vl,\n                           lapack_int ldvl, lapack_complex_float* vr,\n                           lapack_int ldvr, lapack_int* ilo, lapack_int* ihi,\n                           float* lscale, float* rscale, float* abnrm,\n                           float* bbnrm, float* rconde, float* rcondv );\nlapack_int LAPACKE_zggevx( int matrix_order, char balanc, char jobvl,\n                           char jobvr, char sense, lapack_int n,\n                           lapack_complex_double* a, lapack_int lda,\n                           lapack_complex_double* b, lapack_int ldb,\n                           lapack_complex_double* alpha,\n                           lapack_complex_double* beta,\n                           lapack_complex_double* vl, lapack_int ldvl,\n                           lapack_complex_double* vr, lapack_int ldvr,\n                           lapack_int* ilo, lapack_int* ihi, double* lscale,\n                           double* rscale, double* abnrm, double* bbnrm,\n                           double* rconde, double* rcondv );\n\nlapack_int LAPACKE_sggglm( int matrix_order, lapack_int n, lapack_int m,\n                           lapack_int p, float* a, lapack_int lda, float* b,\n                           lapack_int ldb, float* d, float* x, float* y );\nlapack_int LAPACKE_dggglm( int matrix_order, lapack_int n, lapack_int m,\n                           lapack_int p, double* a, lapack_int lda, double* b,\n                           lapack_int ldb, double* d, double* x, double* y );\nlapack_int LAPACKE_cggglm( int matrix_order, lapack_int n, lapack_int m,\n                           lapack_int p, lapack_complex_float* a,\n                           lapack_int lda, lapack_complex_float* b,\n                           lapack_int ldb, lapack_complex_float* d,\n                           lapack_complex_float* x, lapack_complex_float* y );\nlapack_int LAPACKE_zggglm( int matrix_order, lapack_int n, lapack_int m,\n                           lapack_int p, lapack_complex_double* a,\n                           lapack_int lda, lapack_complex_double* b,\n                           lapack_int ldb, lapack_complex_double* d,\n                           lapack_complex_double* x, lapack_complex_double* y );\n\nlapack_int LAPACKE_sgghrd( int matrix_order, char compq, char compz,\n                           lapack_int n, lapack_int ilo, lapack_int ihi,\n                           float* a, lapack_int lda, float* b, lapack_int ldb,\n                           float* q, lapack_int ldq, float* z, lapack_int ldz );\nlapack_int LAPACKE_dgghrd( int matrix_order, char compq, char compz,\n                           lapack_int n, lapack_int ilo, lapack_int ihi,\n                           double* a, lapack_int lda, double* b, lapack_int ldb,\n                           double* q, lapack_int ldq, double* z,\n                           lapack_int ldz );\nlapack_int LAPACKE_cgghrd( int matrix_order, char compq, char compz,\n                           lapack_int n, lapack_int ilo, lapack_int ihi,\n                           lapack_complex_float* a, lapack_int lda,\n                           lapack_complex_float* b, lapack_int ldb,\n                           lapack_complex_float* q, lapack_int ldq,\n                           lapack_complex_float* z, lapack_int ldz );\nlapack_int LAPACKE_zgghrd( int matrix_order, char compq, char compz,\n                           lapack_int n, lapack_int ilo, lapack_int ihi,\n                           lapack_complex_double* a, lapack_int lda,\n                           lapack_complex_double* b, lapack_int ldb,\n                           lapack_complex_double* q, lapack_int ldq,\n                           lapack_complex_double* z, lapack_int ldz );\n\nlapack_int LAPACKE_sgglse( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int p, float* a, lapack_int lda, float* b,\n                           lapack_int ldb, float* c, float* d, float* x );\nlapack_int LAPACKE_dgglse( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int p, double* a, lapack_int lda, double* b,\n                           lapack_int ldb, double* c, double* d, double* x );\nlapack_int LAPACKE_cgglse( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int p, lapack_complex_float* a,\n                           lapack_int lda, lapack_complex_float* b,\n                           lapack_int ldb, lapack_complex_float* c,\n                           lapack_complex_float* d, lapack_complex_float* x );\nlapack_int LAPACKE_zgglse( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int p, lapack_complex_double* a,\n                           lapack_int lda, lapack_complex_double* b,\n                           lapack_int ldb, lapack_complex_double* c,\n                           lapack_complex_double* d, lapack_complex_double* x );\n\nlapack_int LAPACKE_sggqrf( int matrix_order, lapack_int n, lapack_int m,\n                           lapack_int p, float* a, lapack_int lda, float* taua,\n                           float* b, lapack_int ldb, float* taub );\nlapack_int LAPACKE_dggqrf( int matrix_order, lapack_int n, lapack_int m,\n                           lapack_int p, double* a, lapack_int lda,\n                           double* taua, double* b, lapack_int ldb,\n                           double* taub );\nlapack_int LAPACKE_cggqrf( int matrix_order, lapack_int n, lapack_int m,\n                           lapack_int p, lapack_complex_float* a,\n                           lapack_int lda, lapack_complex_float* taua,\n                           lapack_complex_float* b, lapack_int ldb,\n                           lapack_complex_float* taub );\nlapack_int LAPACKE_zggqrf( int matrix_order, lapack_int n, lapack_int m,\n                           lapack_int p, lapack_complex_double* a,\n                           lapack_int lda, lapack_complex_double* taua,\n                           lapack_complex_double* b, lapack_int ldb,\n                           lapack_complex_double* taub );\n\nlapack_int LAPACKE_sggrqf( int matrix_order, lapack_int m, lapack_int p,\n                           lapack_int n, float* a, lapack_int lda, float* taua,\n                           float* b, lapack_int ldb, float* taub );\nlapack_int LAPACKE_dggrqf( int matrix_order, lapack_int m, lapack_int p,\n                           lapack_int n, double* a, lapack_int lda,\n                           double* taua, double* b, lapack_int ldb,\n                           double* taub );\nlapack_int LAPACKE_cggrqf( int matrix_order, lapack_int m, lapack_int p,\n                           lapack_int n, lapack_complex_float* a,\n                           lapack_int lda, lapack_complex_float* taua,\n                           lapack_complex_float* b, lapack_int ldb,\n                           lapack_complex_float* taub );\nlapack_int LAPACKE_zggrqf( int matrix_order, lapack_int m, lapack_int p,\n                           lapack_int n, lapack_complex_double* a,\n                           lapack_int lda, lapack_complex_double* taua,\n                           lapack_complex_double* b, lapack_int ldb,\n                           lapack_complex_double* taub );\n\nlapack_int LAPACKE_sggsvd( int matrix_order, char jobu, char jobv, char jobq,\n                           lapack_int m, lapack_int n, lapack_int p,\n                           lapack_int* k, lapack_int* l, float* a,\n                           lapack_int lda, float* b, lapack_int ldb,\n                           float* alpha, float* beta, float* u, lapack_int ldu,\n                           float* v, lapack_int ldv, float* q, lapack_int ldq,\n                           lapack_int* iwork );\nlapack_int LAPACKE_dggsvd( int matrix_order, char jobu, char jobv, char jobq,\n                           lapack_int m, lapack_int n, lapack_int p,\n                           lapack_int* k, lapack_int* l, double* a,\n                           lapack_int lda, double* b, lapack_int ldb,\n                           double* alpha, double* beta, double* u,\n                           lapack_int ldu, double* v, lapack_int ldv, double* q,\n                           lapack_int ldq, lapack_int* iwork );\nlapack_int LAPACKE_cggsvd( int matrix_order, char jobu, char jobv, char jobq,\n                           lapack_int m, lapack_int n, lapack_int p,\n                           lapack_int* k, lapack_int* l,\n                           lapack_complex_float* a, lapack_int lda,\n                           lapack_complex_float* b, lapack_int ldb,\n                           float* alpha, float* beta, lapack_complex_float* u,\n                           lapack_int ldu, lapack_complex_float* v,\n                           lapack_int ldv, lapack_complex_float* q,\n                           lapack_int ldq, lapack_int* iwork );\nlapack_int LAPACKE_zggsvd( int matrix_order, char jobu, char jobv, char jobq,\n                           lapack_int m, lapack_int n, lapack_int p,\n                           lapack_int* k, lapack_int* l,\n                           lapack_complex_double* a, lapack_int lda,\n                           lapack_complex_double* b, lapack_int ldb,\n                           double* alpha, double* beta,\n                           lapack_complex_double* u, lapack_int ldu,\n                           lapack_complex_double* v, lapack_int ldv,\n                           lapack_complex_double* q, lapack_int ldq,\n                           lapack_int* iwork );\n\nlapack_int LAPACKE_sggsvp( int matrix_order, char jobu, char jobv, char jobq,\n                           lapack_int m, lapack_int p, lapack_int n, float* a,\n                           lapack_int lda, float* b, lapack_int ldb, float tola,\n                           float tolb, lapack_int* k, lapack_int* l, float* u,\n                           lapack_int ldu, float* v, lapack_int ldv, float* q,\n                           lapack_int ldq );\nlapack_int LAPACKE_dggsvp( int matrix_order, char jobu, char jobv, char jobq,\n                           lapack_int m, lapack_int p, lapack_int n, double* a,\n                           lapack_int lda, double* b, lapack_int ldb,\n                           double tola, double tolb, lapack_int* k,\n                           lapack_int* l, double* u, lapack_int ldu, double* v,\n                           lapack_int ldv, double* q, lapack_int ldq );\nlapack_int LAPACKE_cggsvp( int matrix_order, char jobu, char jobv, char jobq,\n                           lapack_int m, lapack_int p, lapack_int n,\n                           lapack_complex_float* a, lapack_int lda,\n                           lapack_complex_float* b, lapack_int ldb, float tola,\n                           float tolb, lapack_int* k, lapack_int* l,\n                           lapack_complex_float* u, lapack_int ldu,\n                           lapack_complex_float* v, lapack_int ldv,\n                           lapack_complex_float* q, lapack_int ldq );\nlapack_int LAPACKE_zggsvp( int matrix_order, char jobu, char jobv, char jobq,\n                           lapack_int m, lapack_int p, lapack_int n,\n                           lapack_complex_double* a, lapack_int lda,\n                           lapack_complex_double* b, lapack_int ldb,\n                           double tola, double tolb, lapack_int* k,\n                           lapack_int* l, lapack_complex_double* u,\n                           lapack_int ldu, lapack_complex_double* v,\n                           lapack_int ldv, lapack_complex_double* q,\n                           lapack_int ldq );\n\nlapack_int LAPACKE_sgtcon( char norm, lapack_int n, const float* dl,\n                           const float* d, const float* du, const float* du2,\n                           const lapack_int* ipiv, float anorm, float* rcond );\nlapack_int LAPACKE_dgtcon( char norm, lapack_int n, const double* dl,\n                           const double* d, const double* du, const double* du2,\n                           const lapack_int* ipiv, double anorm,\n                           double* rcond );\nlapack_int LAPACKE_cgtcon( char norm, lapack_int n,\n                           const lapack_complex_float* dl,\n                           const lapack_complex_float* d,\n                           const lapack_complex_float* du,\n                           const lapack_complex_float* du2,\n                           const lapack_int* ipiv, float anorm, float* rcond );\nlapack_int LAPACKE_zgtcon( char norm, lapack_int n,\n                           const lapack_complex_double* dl,\n                           const lapack_complex_double* d,\n                           const lapack_complex_double* du,\n                           const lapack_complex_double* du2,\n                           const lapack_int* ipiv, double anorm,\n                           double* rcond );\n\nlapack_int LAPACKE_sgtrfs( int matrix_order, char trans, lapack_int n,\n                           lapack_int nrhs, const float* dl, const float* d,\n                           const float* du, const float* dlf, const float* df,\n                           const float* duf, const float* du2,\n                           const lapack_int* ipiv, const float* b,\n                           lapack_int ldb, float* x, lapack_int ldx,\n                           float* ferr, float* berr );\nlapack_int LAPACKE_dgtrfs( int matrix_order, char trans, lapack_int n,\n                           lapack_int nrhs, const double* dl, const double* d,\n                           const double* du, const double* dlf,\n                           const double* df, const double* duf,\n                           const double* du2, const lapack_int* ipiv,\n                           const double* b, lapack_int ldb, double* x,\n                           lapack_int ldx, double* ferr, double* berr );\nlapack_int LAPACKE_cgtrfs( int matrix_order, char trans, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_float* dl,\n                           const lapack_complex_float* d,\n                           const lapack_complex_float* du,\n                           const lapack_complex_float* dlf,\n                           const lapack_complex_float* df,\n                           const lapack_complex_float* duf,\n                           const lapack_complex_float* du2,\n                           const lapack_int* ipiv,\n                           const lapack_complex_float* b, lapack_int ldb,\n                           lapack_complex_float* x, lapack_int ldx, float* ferr,\n                           float* berr );\nlapack_int LAPACKE_zgtrfs( int matrix_order, char trans, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_double* dl,\n                           const lapack_complex_double* d,\n                           const lapack_complex_double* du,\n                           const lapack_complex_double* dlf,\n                           const lapack_complex_double* df,\n                           const lapack_complex_double* duf,\n                           const lapack_complex_double* du2,\n                           const lapack_int* ipiv,\n                           const lapack_complex_double* b, lapack_int ldb,\n                           lapack_complex_double* x, lapack_int ldx,\n                           double* ferr, double* berr );\n\nlapack_int LAPACKE_sgtsv( int matrix_order, lapack_int n, lapack_int nrhs,\n                          float* dl, float* d, float* du, float* b,\n                          lapack_int ldb );\nlapack_int LAPACKE_dgtsv( int matrix_order, lapack_int n, lapack_int nrhs,\n                          double* dl, double* d, double* du, double* b,\n                          lapack_int ldb );\nlapack_int LAPACKE_cgtsv( int matrix_order, lapack_int n, lapack_int nrhs,\n                          lapack_complex_float* dl, lapack_complex_float* d,\n                          lapack_complex_float* du, lapack_complex_float* b,\n                          lapack_int ldb );\nlapack_int LAPACKE_zgtsv( int matrix_order, lapack_int n, lapack_int nrhs,\n                          lapack_complex_double* dl, lapack_complex_double* d,\n                          lapack_complex_double* du, lapack_complex_double* b,\n                          lapack_int ldb );\n\nlapack_int LAPACKE_sgtsvx( int matrix_order, char fact, char trans,\n                           lapack_int n, lapack_int nrhs, const float* dl,\n                           const float* d, const float* du, float* dlf,\n                           float* df, float* duf, float* du2, lapack_int* ipiv,\n                           const float* b, lapack_int ldb, float* x,\n                           lapack_int ldx, float* rcond, float* ferr,\n                           float* berr );\nlapack_int LAPACKE_dgtsvx( int matrix_order, char fact, char trans,\n                           lapack_int n, lapack_int nrhs, const double* dl,\n                           const double* d, const double* du, double* dlf,\n                           double* df, double* duf, double* du2,\n                           lapack_int* ipiv, const double* b, lapack_int ldb,\n                           double* x, lapack_int ldx, double* rcond,\n                           double* ferr, double* berr );\nlapack_int LAPACKE_cgtsvx( int matrix_order, char fact, char trans,\n                           lapack_int n, lapack_int nrhs,\n                           const lapack_complex_float* dl,\n                           const lapack_complex_float* d,\n                           const lapack_complex_float* du,\n                           lapack_complex_float* dlf, lapack_complex_float* df,\n                           lapack_complex_float* duf, lapack_complex_float* du2,\n                           lapack_int* ipiv, const lapack_complex_float* b,\n                           lapack_int ldb, lapack_complex_float* x,\n                           lapack_int ldx, float* rcond, float* ferr,\n                           float* berr );\nlapack_int LAPACKE_zgtsvx( int matrix_order, char fact, char trans,\n                           lapack_int n, lapack_int nrhs,\n                           const lapack_complex_double* dl,\n                           const lapack_complex_double* d,\n                           const lapack_complex_double* du,\n                           lapack_complex_double* dlf,\n                           lapack_complex_double* df,\n                           lapack_complex_double* duf,\n                           lapack_complex_double* du2, lapack_int* ipiv,\n                           const lapack_complex_double* b, lapack_int ldb,\n                           lapack_complex_double* x, lapack_int ldx,\n                           double* rcond, double* ferr, double* berr );\n\nlapack_int LAPACKE_sgttrf( lapack_int n, float* dl, float* d, float* du,\n                           float* du2, lapack_int* ipiv );\nlapack_int LAPACKE_dgttrf( lapack_int n, double* dl, double* d, double* du,\n                           double* du2, lapack_int* ipiv );\nlapack_int LAPACKE_cgttrf( lapack_int n, lapack_complex_float* dl,\n                           lapack_complex_float* d, lapack_complex_float* du,\n                           lapack_complex_float* du2, lapack_int* ipiv );\nlapack_int LAPACKE_zgttrf( lapack_int n, lapack_complex_double* dl,\n                           lapack_complex_double* d, lapack_complex_double* du,\n                           lapack_complex_double* du2, lapack_int* ipiv );\n\nlapack_int LAPACKE_sgttrs( int matrix_order, char trans, lapack_int n,\n                           lapack_int nrhs, const float* dl, const float* d,\n                           const float* du, const float* du2,\n                           const lapack_int* ipiv, float* b, lapack_int ldb );\nlapack_int LAPACKE_dgttrs( int matrix_order, char trans, lapack_int n,\n                           lapack_int nrhs, const double* dl, const double* d,\n                           const double* du, const double* du2,\n                           const lapack_int* ipiv, double* b, lapack_int ldb );\nlapack_int LAPACKE_cgttrs( int matrix_order, char trans, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_float* dl,\n                           const lapack_complex_float* d,\n                           const lapack_complex_float* du,\n                           const lapack_complex_float* du2,\n                           const lapack_int* ipiv, lapack_complex_float* b,\n                           lapack_int ldb );\nlapack_int LAPACKE_zgttrs( int matrix_order, char trans, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_double* dl,\n                           const lapack_complex_double* d,\n                           const lapack_complex_double* du,\n                           const lapack_complex_double* du2,\n                           const lapack_int* ipiv, lapack_complex_double* b,\n                           lapack_int ldb );\n\nlapack_int LAPACKE_chbev( int matrix_order, char jobz, char uplo, lapack_int n,\n                          lapack_int kd, lapack_complex_float* ab,\n                          lapack_int ldab, float* w, lapack_complex_float* z,\n                          lapack_int ldz );\nlapack_int LAPACKE_zhbev( int matrix_order, char jobz, char uplo, lapack_int n,\n                          lapack_int kd, lapack_complex_double* ab,\n                          lapack_int ldab, double* w, lapack_complex_double* z,\n                          lapack_int ldz );\n\nlapack_int LAPACKE_chbevd( int matrix_order, char jobz, char uplo, lapack_int n,\n                           lapack_int kd, lapack_complex_float* ab,\n                           lapack_int ldab, float* w, lapack_complex_float* z,\n                           lapack_int ldz );\nlapack_int LAPACKE_zhbevd( int matrix_order, char jobz, char uplo, lapack_int n,\n                           lapack_int kd, lapack_complex_double* ab,\n                           lapack_int ldab, double* w, lapack_complex_double* z,\n                           lapack_int ldz );\n\nlapack_int LAPACKE_chbevx( int matrix_order, char jobz, char range, char uplo,\n                           lapack_int n, lapack_int kd,\n                           lapack_complex_float* ab, lapack_int ldab,\n                           lapack_complex_float* q, lapack_int ldq, float vl,\n                           float vu, lapack_int il, lapack_int iu, float abstol,\n                           lapack_int* m, float* w, lapack_complex_float* z,\n                           lapack_int ldz, lapack_int* ifail );\nlapack_int LAPACKE_zhbevx( int matrix_order, char jobz, char range, char uplo,\n                           lapack_int n, lapack_int kd,\n                           lapack_complex_double* ab, lapack_int ldab,\n                           lapack_complex_double* q, lapack_int ldq, double vl,\n                           double vu, lapack_int il, lapack_int iu,\n                           double abstol, lapack_int* m, double* w,\n                           lapack_complex_double* z, lapack_int ldz,\n                           lapack_int* ifail );\n\nlapack_int LAPACKE_chbgst( int matrix_order, char vect, char uplo, lapack_int n,\n                           lapack_int ka, lapack_int kb,\n                           lapack_complex_float* ab, lapack_int ldab,\n                           const lapack_complex_float* bb, lapack_int ldbb,\n                           lapack_complex_float* x, lapack_int ldx );\nlapack_int LAPACKE_zhbgst( int matrix_order, char vect, char uplo, lapack_int n,\n                           lapack_int ka, lapack_int kb,\n                           lapack_complex_double* ab, lapack_int ldab,\n                           const lapack_complex_double* bb, lapack_int ldbb,\n                           lapack_complex_double* x, lapack_int ldx );\n\nlapack_int LAPACKE_chbgv( int matrix_order, char jobz, char uplo, lapack_int n,\n                          lapack_int ka, lapack_int kb,\n                          lapack_complex_float* ab, lapack_int ldab,\n                          lapack_complex_float* bb, lapack_int ldbb, float* w,\n                          lapack_complex_float* z, lapack_int ldz );\nlapack_int LAPACKE_zhbgv( int matrix_order, char jobz, char uplo, lapack_int n,\n                          lapack_int ka, lapack_int kb,\n                          lapack_complex_double* ab, lapack_int ldab,\n                          lapack_complex_double* bb, lapack_int ldbb, double* w,\n                          lapack_complex_double* z, lapack_int ldz );\n\nlapack_int LAPACKE_chbgvd( int matrix_order, char jobz, char uplo, lapack_int n,\n                           lapack_int ka, lapack_int kb,\n                           lapack_complex_float* ab, lapack_int ldab,\n                           lapack_complex_float* bb, lapack_int ldbb, float* w,\n                           lapack_complex_float* z, lapack_int ldz );\nlapack_int LAPACKE_zhbgvd( int matrix_order, char jobz, char uplo, lapack_int n,\n                           lapack_int ka, lapack_int kb,\n                           lapack_complex_double* ab, lapack_int ldab,\n                           lapack_complex_double* bb, lapack_int ldbb,\n                           double* w, lapack_complex_double* z,\n                           lapack_int ldz );\n\nlapack_int LAPACKE_chbgvx( int matrix_order, char jobz, char range, char uplo,\n                           lapack_int n, lapack_int ka, lapack_int kb,\n                           lapack_complex_float* ab, lapack_int ldab,\n                           lapack_complex_float* bb, lapack_int ldbb,\n                           lapack_complex_float* q, lapack_int ldq, float vl,\n                           float vu, lapack_int il, lapack_int iu, float abstol,\n                           lapack_int* m, float* w, lapack_complex_float* z,\n                           lapack_int ldz, lapack_int* ifail );\nlapack_int LAPACKE_zhbgvx( int matrix_order, char jobz, char range, char uplo,\n                           lapack_int n, lapack_int ka, lapack_int kb,\n                           lapack_complex_double* ab, lapack_int ldab,\n                           lapack_complex_double* bb, lapack_int ldbb,\n                           lapack_complex_double* q, lapack_int ldq, double vl,\n                           double vu, lapack_int il, lapack_int iu,\n                           double abstol, lapack_int* m, double* w,\n                           lapack_complex_double* z, lapack_int ldz,\n                           lapack_int* ifail );\n\nlapack_int LAPACKE_chbtrd( int matrix_order, char vect, char uplo, lapack_int n,\n                           lapack_int kd, lapack_complex_float* ab,\n                           lapack_int ldab, float* d, float* e,\n                           lapack_complex_float* q, lapack_int ldq );\nlapack_int LAPACKE_zhbtrd( int matrix_order, char vect, char uplo, lapack_int n,\n                           lapack_int kd, lapack_complex_double* ab,\n                           lapack_int ldab, double* d, double* e,\n                           lapack_complex_double* q, lapack_int ldq );\n\nlapack_int LAPACKE_checon( int matrix_order, char uplo, lapack_int n,\n                           const lapack_complex_float* a, lapack_int lda,\n                           const lapack_int* ipiv, float anorm, float* rcond );\nlapack_int LAPACKE_zhecon( int matrix_order, char uplo, lapack_int n,\n                           const lapack_complex_double* a, lapack_int lda,\n                           const lapack_int* ipiv, double anorm,\n                           double* rcond );\n\nlapack_int LAPACKE_cheequb( int matrix_order, char uplo, lapack_int n,\n                            const lapack_complex_float* a, lapack_int lda,\n                            float* s, float* scond, float* amax );\nlapack_int LAPACKE_zheequb( int matrix_order, char uplo, lapack_int n,\n                            const lapack_complex_double* a, lapack_int lda,\n                            double* s, double* scond, double* amax );\n\nlapack_int LAPACKE_cheev( int matrix_order, char jobz, char uplo, lapack_int n,\n                          lapack_complex_float* a, lapack_int lda, float* w );\nlapack_int LAPACKE_zheev( int matrix_order, char jobz, char uplo, lapack_int n,\n                          lapack_complex_double* a, lapack_int lda, double* w );\n\nlapack_int LAPACKE_cheevd( int matrix_order, char jobz, char uplo, lapack_int n,\n                           lapack_complex_float* a, lapack_int lda, float* w );\nlapack_int LAPACKE_zheevd( int matrix_order, char jobz, char uplo, lapack_int n,\n                           lapack_complex_double* a, lapack_int lda,\n                           double* w );\n\nlapack_int LAPACKE_cheevr( int matrix_order, char jobz, char range, char uplo,\n                           lapack_int n, lapack_complex_float* a,\n                           lapack_int lda, float vl, float vu, lapack_int il,\n                           lapack_int iu, float abstol, lapack_int* m, float* w,\n                           lapack_complex_float* z, lapack_int ldz,\n                           lapack_int* isuppz );\nlapack_int LAPACKE_zheevr( int matrix_order, char jobz, char range, char uplo,\n                           lapack_int n, lapack_complex_double* a,\n                           lapack_int lda, double vl, double vu, lapack_int il,\n                           lapack_int iu, double abstol, lapack_int* m,\n                           double* w, lapack_complex_double* z, lapack_int ldz,\n                           lapack_int* isuppz );\n\nlapack_int LAPACKE_cheevx( int matrix_order, char jobz, char range, char uplo,\n                           lapack_int n, lapack_complex_float* a,\n                           lapack_int lda, float vl, float vu, lapack_int il,\n                           lapack_int iu, float abstol, lapack_int* m, float* w,\n                           lapack_complex_float* z, lapack_int ldz,\n                           lapack_int* ifail );\nlapack_int LAPACKE_zheevx( int matrix_order, char jobz, char range, char uplo,\n                           lapack_int n, lapack_complex_double* a,\n                           lapack_int lda, double vl, double vu, lapack_int il,\n                           lapack_int iu, double abstol, lapack_int* m,\n                           double* w, lapack_complex_double* z, lapack_int ldz,\n                           lapack_int* ifail );\n\nlapack_int LAPACKE_chegst( int matrix_order, lapack_int itype, char uplo,\n                           lapack_int n, lapack_complex_float* a,\n                           lapack_int lda, const lapack_complex_float* b,\n                           lapack_int ldb );\nlapack_int LAPACKE_zhegst( int matrix_order, lapack_int itype, char uplo,\n                           lapack_int n, lapack_complex_double* a,\n                           lapack_int lda, const lapack_complex_double* b,\n                           lapack_int ldb );\n\nlapack_int LAPACKE_chegv( int matrix_order, lapack_int itype, char jobz,\n                          char uplo, lapack_int n, lapack_complex_float* a,\n                          lapack_int lda, lapack_complex_float* b,\n                          lapack_int ldb, float* w );\nlapack_int LAPACKE_zhegv( int matrix_order, lapack_int itype, char jobz,\n                          char uplo, lapack_int n, lapack_complex_double* a,\n                          lapack_int lda, lapack_complex_double* b,\n                          lapack_int ldb, double* w );\n\nlapack_int LAPACKE_chegvd( int matrix_order, lapack_int itype, char jobz,\n                           char uplo, lapack_int n, lapack_complex_float* a,\n                           lapack_int lda, lapack_complex_float* b,\n                           lapack_int ldb, float* w );\nlapack_int LAPACKE_zhegvd( int matrix_order, lapack_int itype, char jobz,\n                           char uplo, lapack_int n, lapack_complex_double* a,\n                           lapack_int lda, lapack_complex_double* b,\n                           lapack_int ldb, double* w );\n\nlapack_int LAPACKE_chegvx( int matrix_order, lapack_int itype, char jobz,\n                           char range, char uplo, lapack_int n,\n                           lapack_complex_float* a, lapack_int lda,\n                           lapack_complex_float* b, lapack_int ldb, float vl,\n                           float vu, lapack_int il, lapack_int iu, float abstol,\n                           lapack_int* m, float* w, lapack_complex_float* z,\n                           lapack_int ldz, lapack_int* ifail );\nlapack_int LAPACKE_zhegvx( int matrix_order, lapack_int itype, char jobz,\n                           char range, char uplo, lapack_int n,\n                           lapack_complex_double* a, lapack_int lda,\n                           lapack_complex_double* b, lapack_int ldb, double vl,\n                           double vu, lapack_int il, lapack_int iu,\n                           double abstol, lapack_int* m, double* w,\n                           lapack_complex_double* z, lapack_int ldz,\n                           lapack_int* ifail );\n\nlapack_int LAPACKE_cherfs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_float* a,\n                           lapack_int lda, const lapack_complex_float* af,\n                           lapack_int ldaf, const lapack_int* ipiv,\n                           const lapack_complex_float* b, lapack_int ldb,\n                           lapack_complex_float* x, lapack_int ldx, float* ferr,\n                           float* berr );\nlapack_int LAPACKE_zherfs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_double* a,\n                           lapack_int lda, const lapack_complex_double* af,\n                           lapack_int ldaf, const lapack_int* ipiv,\n                           const lapack_complex_double* b, lapack_int ldb,\n                           lapack_complex_double* x, lapack_int ldx,\n                           double* ferr, double* berr );\n\nlapack_int LAPACKE_cherfsx( int matrix_order, char uplo, char equed,\n                            lapack_int n, lapack_int nrhs,\n                            const lapack_complex_float* a, lapack_int lda,\n                            const lapack_complex_float* af, lapack_int ldaf,\n                            const lapack_int* ipiv, const float* s,\n                            const lapack_complex_float* b, lapack_int ldb,\n                            lapack_complex_float* x, lapack_int ldx,\n                            float* rcond, float* berr, lapack_int n_err_bnds,\n                            float* err_bnds_norm, float* err_bnds_comp,\n                            lapack_int nparams, float* params );\nlapack_int LAPACKE_zherfsx( int matrix_order, char uplo, char equed,\n                            lapack_int n, lapack_int nrhs,\n                            const lapack_complex_double* a, lapack_int lda,\n                            const lapack_complex_double* af, lapack_int ldaf,\n                            const lapack_int* ipiv, const double* s,\n                            const lapack_complex_double* b, lapack_int ldb,\n                            lapack_complex_double* x, lapack_int ldx,\n                            double* rcond, double* berr, lapack_int n_err_bnds,\n                            double* err_bnds_norm, double* err_bnds_comp,\n                            lapack_int nparams, double* params );\n\nlapack_int LAPACKE_chesv( int matrix_order, char uplo, lapack_int n,\n                          lapack_int nrhs, lapack_complex_float* a,\n                          lapack_int lda, lapack_int* ipiv,\n                          lapack_complex_float* b, lapack_int ldb );\nlapack_int LAPACKE_zhesv( int matrix_order, char uplo, lapack_int n,\n                          lapack_int nrhs, lapack_complex_double* a,\n                          lapack_int lda, lapack_int* ipiv,\n                          lapack_complex_double* b, lapack_int ldb );\n\nlapack_int LAPACKE_chesvx( int matrix_order, char fact, char uplo, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_float* a,\n                           lapack_int lda, lapack_complex_float* af,\n                           lapack_int ldaf, lapack_int* ipiv,\n                           const lapack_complex_float* b, lapack_int ldb,\n                           lapack_complex_float* x, lapack_int ldx,\n                           float* rcond, float* ferr, float* berr );\nlapack_int LAPACKE_zhesvx( int matrix_order, char fact, char uplo, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_double* a,\n                           lapack_int lda, lapack_complex_double* af,\n                           lapack_int ldaf, lapack_int* ipiv,\n                           const lapack_complex_double* b, lapack_int ldb,\n                           lapack_complex_double* x, lapack_int ldx,\n                           double* rcond, double* ferr, double* berr );\n\nlapack_int LAPACKE_chesvxx( int matrix_order, char fact, char uplo,\n                            lapack_int n, lapack_int nrhs,\n                            lapack_complex_float* a, lapack_int lda,\n                            lapack_complex_float* af, lapack_int ldaf,\n                            lapack_int* ipiv, char* equed, float* s,\n                            lapack_complex_float* b, lapack_int ldb,\n                            lapack_complex_float* x, lapack_int ldx,\n                            float* rcond, float* rpvgrw, float* berr,\n                            lapack_int n_err_bnds, float* err_bnds_norm,\n                            float* err_bnds_comp, lapack_int nparams,\n                            float* params );\nlapack_int LAPACKE_zhesvxx( int matrix_order, char fact, char uplo,\n                            lapack_int n, lapack_int nrhs,\n                            lapack_complex_double* a, lapack_int lda,\n                            lapack_complex_double* af, lapack_int ldaf,\n                            lapack_int* ipiv, char* equed, double* s,\n                            lapack_complex_double* b, lapack_int ldb,\n                            lapack_complex_double* x, lapack_int ldx,\n                            double* rcond, double* rpvgrw, double* berr,\n                            lapack_int n_err_bnds, double* err_bnds_norm,\n                            double* err_bnds_comp, lapack_int nparams,\n                            double* params );\n\nlapack_int LAPACKE_chetrd( int matrix_order, char uplo, lapack_int n,\n                           lapack_complex_float* a, lapack_int lda, float* d,\n                           float* e, lapack_complex_float* tau );\nlapack_int LAPACKE_zhetrd( int matrix_order, char uplo, lapack_int n,\n                           lapack_complex_double* a, lapack_int lda, double* d,\n                           double* e, lapack_complex_double* tau );\n\nlapack_int LAPACKE_chetrf( int matrix_order, char uplo, lapack_int n,\n                           lapack_complex_float* a, lapack_int lda,\n                           lapack_int* ipiv );\nlapack_int LAPACKE_zhetrf( int matrix_order, char uplo, lapack_int n,\n                           lapack_complex_double* a, lapack_int lda,\n                           lapack_int* ipiv );\n\nlapack_int LAPACKE_chetri( int matrix_order, char uplo, lapack_int n,\n                           lapack_complex_float* a, lapack_int lda,\n                           const lapack_int* ipiv );\nlapack_int LAPACKE_zhetri( int matrix_order, char uplo, lapack_int n,\n                           lapack_complex_double* a, lapack_int lda,\n                           const lapack_int* ipiv );\n\nlapack_int LAPACKE_chetrs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_float* a,\n                           lapack_int lda, const lapack_int* ipiv,\n                           lapack_complex_float* b, lapack_int ldb );\nlapack_int LAPACKE_zhetrs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_double* a,\n                           lapack_int lda, const lapack_int* ipiv,\n                           lapack_complex_double* b, lapack_int ldb );\n\nlapack_int LAPACKE_chfrk( int matrix_order, char transr, char uplo, char trans,\n                          lapack_int n, lapack_int k, float alpha,\n                          const lapack_complex_float* a, lapack_int lda,\n                          float beta, lapack_complex_float* c );\nlapack_int LAPACKE_zhfrk( int matrix_order, char transr, char uplo, char trans,\n                          lapack_int n, lapack_int k, double alpha,\n                          const lapack_complex_double* a, lapack_int lda,\n                          double beta, lapack_complex_double* c );\n\nlapack_int LAPACKE_shgeqz( int matrix_order, char job, char compq, char compz,\n                           lapack_int n, lapack_int ilo, lapack_int ihi,\n                           float* h, lapack_int ldh, float* t, lapack_int ldt,\n                           float* alphar, float* alphai, float* beta, float* q,\n                           lapack_int ldq, float* z, lapack_int ldz );\nlapack_int LAPACKE_dhgeqz( int matrix_order, char job, char compq, char compz,\n                           lapack_int n, lapack_int ilo, lapack_int ihi,\n                           double* h, lapack_int ldh, double* t, lapack_int ldt,\n                           double* alphar, double* alphai, double* beta,\n                           double* q, lapack_int ldq, double* z,\n                           lapack_int ldz );\nlapack_int LAPACKE_chgeqz( int matrix_order, char job, char compq, char compz,\n                           lapack_int n, lapack_int ilo, lapack_int ihi,\n                           lapack_complex_float* h, lapack_int ldh,\n                           lapack_complex_float* t, lapack_int ldt,\n                           lapack_complex_float* alpha,\n                           lapack_complex_float* beta, lapack_complex_float* q,\n                           lapack_int ldq, lapack_complex_float* z,\n                           lapack_int ldz );\nlapack_int LAPACKE_zhgeqz( int matrix_order, char job, char compq, char compz,\n                           lapack_int n, lapack_int ilo, lapack_int ihi,\n                           lapack_complex_double* h, lapack_int ldh,\n                           lapack_complex_double* t, lapack_int ldt,\n                           lapack_complex_double* alpha,\n                           lapack_complex_double* beta,\n                           lapack_complex_double* q, lapack_int ldq,\n                           lapack_complex_double* z, lapack_int ldz );\n\nlapack_int LAPACKE_chpcon( int matrix_order, char uplo, lapack_int n,\n                           const lapack_complex_float* ap,\n                           const lapack_int* ipiv, float anorm, float* rcond );\nlapack_int LAPACKE_zhpcon( int matrix_order, char uplo, lapack_int n,\n                           const lapack_complex_double* ap,\n                           const lapack_int* ipiv, double anorm,\n                           double* rcond );\n\nlapack_int LAPACKE_chpev( int matrix_order, char jobz, char uplo, lapack_int n,\n                          lapack_complex_float* ap, float* w,\n                          lapack_complex_float* z, lapack_int ldz );\nlapack_int LAPACKE_zhpev( int matrix_order, char jobz, char uplo, lapack_int n,\n                          lapack_complex_double* ap, double* w,\n                          lapack_complex_double* z, lapack_int ldz );\n\nlapack_int LAPACKE_chpevd( int matrix_order, char jobz, char uplo, lapack_int n,\n                           lapack_complex_float* ap, float* w,\n                           lapack_complex_float* z, lapack_int ldz );\nlapack_int LAPACKE_zhpevd( int matrix_order, char jobz, char uplo, lapack_int n,\n                           lapack_complex_double* ap, double* w,\n                           lapack_complex_double* z, lapack_int ldz );\n\nlapack_int LAPACKE_chpevx( int matrix_order, char jobz, char range, char uplo,\n                           lapack_int n, lapack_complex_float* ap, float vl,\n                           float vu, lapack_int il, lapack_int iu, float abstol,\n                           lapack_int* m, float* w, lapack_complex_float* z,\n                           lapack_int ldz, lapack_int* ifail );\nlapack_int LAPACKE_zhpevx( int matrix_order, char jobz, char range, char uplo,\n                           lapack_int n, lapack_complex_double* ap, double vl,\n                           double vu, lapack_int il, lapack_int iu,\n                           double abstol, lapack_int* m, double* w,\n                           lapack_complex_double* z, lapack_int ldz,\n                           lapack_int* ifail );\n\nlapack_int LAPACKE_chpgst( int matrix_order, lapack_int itype, char uplo,\n                           lapack_int n, lapack_complex_float* ap,\n                           const lapack_complex_float* bp );\nlapack_int LAPACKE_zhpgst( int matrix_order, lapack_int itype, char uplo,\n                           lapack_int n, lapack_complex_double* ap,\n                           const lapack_complex_double* bp );\n\nlapack_int LAPACKE_chpgv( int matrix_order, lapack_int itype, char jobz,\n                          char uplo, lapack_int n, lapack_complex_float* ap,\n                          lapack_complex_float* bp, float* w,\n                          lapack_complex_float* z, lapack_int ldz );\nlapack_int LAPACKE_zhpgv( int matrix_order, lapack_int itype, char jobz,\n                          char uplo, lapack_int n, lapack_complex_double* ap,\n                          lapack_complex_double* bp, double* w,\n                          lapack_complex_double* z, lapack_int ldz );\n\nlapack_int LAPACKE_chpgvd( int matrix_order, lapack_int itype, char jobz,\n                           char uplo, lapack_int n, lapack_complex_float* ap,\n                           lapack_complex_float* bp, float* w,\n                           lapack_complex_float* z, lapack_int ldz );\nlapack_int LAPACKE_zhpgvd( int matrix_order, lapack_int itype, char jobz,\n                           char uplo, lapack_int n, lapack_complex_double* ap,\n                           lapack_complex_double* bp, double* w,\n                           lapack_complex_double* z, lapack_int ldz );\n\nlapack_int LAPACKE_chpgvx( int matrix_order, lapack_int itype, char jobz,\n                           char range, char uplo, lapack_int n,\n                           lapack_complex_float* ap, lapack_complex_float* bp,\n                           float vl, float vu, lapack_int il, lapack_int iu,\n                           float abstol, lapack_int* m, float* w,\n                           lapack_complex_float* z, lapack_int ldz,\n                           lapack_int* ifail );\nlapack_int LAPACKE_zhpgvx( int matrix_order, lapack_int itype, char jobz,\n                           char range, char uplo, lapack_int n,\n                           lapack_complex_double* ap, lapack_complex_double* bp,\n                           double vl, double vu, lapack_int il, lapack_int iu,\n                           double abstol, lapack_int* m, double* w,\n                           lapack_complex_double* z, lapack_int ldz,\n                           lapack_int* ifail );\n\nlapack_int LAPACKE_chprfs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_float* ap,\n                           const lapack_complex_float* afp,\n                           const lapack_int* ipiv,\n                           const lapack_complex_float* b, lapack_int ldb,\n                           lapack_complex_float* x, lapack_int ldx, float* ferr,\n                           float* berr );\nlapack_int LAPACKE_zhprfs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_double* ap,\n                           const lapack_complex_double* afp,\n                           const lapack_int* ipiv,\n                           const lapack_complex_double* b, lapack_int ldb,\n                           lapack_complex_double* x, lapack_int ldx,\n                           double* ferr, double* berr );\n\nlapack_int LAPACKE_chpsv( int matrix_order, char uplo, lapack_int n,\n                          lapack_int nrhs, lapack_complex_float* ap,\n                          lapack_int* ipiv, lapack_complex_float* b,\n                          lapack_int ldb );\nlapack_int LAPACKE_zhpsv( int matrix_order, char uplo, lapack_int n,\n                          lapack_int nrhs, lapack_complex_double* ap,\n                          lapack_int* ipiv, lapack_complex_double* b,\n                          lapack_int ldb );\n\nlapack_int LAPACKE_chpsvx( int matrix_order, char fact, char uplo, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_float* ap,\n                           lapack_complex_float* afp, lapack_int* ipiv,\n                           const lapack_complex_float* b, lapack_int ldb,\n                           lapack_complex_float* x, lapack_int ldx,\n                           float* rcond, float* ferr, float* berr );\nlapack_int LAPACKE_zhpsvx( int matrix_order, char fact, char uplo, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_double* ap,\n                           lapack_complex_double* afp, lapack_int* ipiv,\n                           const lapack_complex_double* b, lapack_int ldb,\n                           lapack_complex_double* x, lapack_int ldx,\n                           double* rcond, double* ferr, double* berr );\n\nlapack_int LAPACKE_chptrd( int matrix_order, char uplo, lapack_int n,\n                           lapack_complex_float* ap, float* d, float* e,\n                           lapack_complex_float* tau );\nlapack_int LAPACKE_zhptrd( int matrix_order, char uplo, lapack_int n,\n                           lapack_complex_double* ap, double* d, double* e,\n                           lapack_complex_double* tau );\n\nlapack_int LAPACKE_chptrf( int matrix_order, char uplo, lapack_int n,\n                           lapack_complex_float* ap, lapack_int* ipiv );\nlapack_int LAPACKE_zhptrf( int matrix_order, char uplo, lapack_int n,\n                           lapack_complex_double* ap, lapack_int* ipiv );\n\nlapack_int LAPACKE_chptri( int matrix_order, char uplo, lapack_int n,\n                           lapack_complex_float* ap, const lapack_int* ipiv );\nlapack_int LAPACKE_zhptri( int matrix_order, char uplo, lapack_int n,\n                           lapack_complex_double* ap, const lapack_int* ipiv );\n\nlapack_int LAPACKE_chptrs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_float* ap,\n                           const lapack_int* ipiv, lapack_complex_float* b,\n                           lapack_int ldb );\nlapack_int LAPACKE_zhptrs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_double* ap,\n                           const lapack_int* ipiv, lapack_complex_double* b,\n                           lapack_int ldb );\n\nlapack_int LAPACKE_shsein( int matrix_order, char job, char eigsrc, char initv,\n                           lapack_logical* select, lapack_int n, const float* h,\n                           lapack_int ldh, float* wr, const float* wi,\n                           float* vl, lapack_int ldvl, float* vr,\n                           lapack_int ldvr, lapack_int mm, lapack_int* m,\n                           lapack_int* ifaill, lapack_int* ifailr );\nlapack_int LAPACKE_dhsein( int matrix_order, char job, char eigsrc, char initv,\n                           lapack_logical* select, lapack_int n,\n                           const double* h, lapack_int ldh, double* wr,\n                           const double* wi, double* vl, lapack_int ldvl,\n                           double* vr, lapack_int ldvr, lapack_int mm,\n                           lapack_int* m, lapack_int* ifaill,\n                           lapack_int* ifailr );\nlapack_int LAPACKE_chsein( int matrix_order, char job, char eigsrc, char initv,\n                           const lapack_logical* select, lapack_int n,\n                           const lapack_complex_float* h, lapack_int ldh,\n                           lapack_complex_float* w, lapack_complex_float* vl,\n                           lapack_int ldvl, lapack_complex_float* vr,\n                           lapack_int ldvr, lapack_int mm, lapack_int* m,\n                           lapack_int* ifaill, lapack_int* ifailr );\nlapack_int LAPACKE_zhsein( int matrix_order, char job, char eigsrc, char initv,\n                           const lapack_logical* select, lapack_int n,\n                           const lapack_complex_double* h, lapack_int ldh,\n                           lapack_complex_double* w, lapack_complex_double* vl,\n                           lapack_int ldvl, lapack_complex_double* vr,\n                           lapack_int ldvr, lapack_int mm, lapack_int* m,\n                           lapack_int* ifaill, lapack_int* ifailr );\n\nlapack_int LAPACKE_shseqr( int matrix_order, char job, char compz, lapack_int n,\n                           lapack_int ilo, lapack_int ihi, float* h,\n                           lapack_int ldh, float* wr, float* wi, float* z,\n                           lapack_int ldz );\nlapack_int LAPACKE_dhseqr( int matrix_order, char job, char compz, lapack_int n,\n                           lapack_int ilo, lapack_int ihi, double* h,\n                           lapack_int ldh, double* wr, double* wi, double* z,\n                           lapack_int ldz );\nlapack_int LAPACKE_chseqr( int matrix_order, char job, char compz, lapack_int n,\n                           lapack_int ilo, lapack_int ihi,\n                           lapack_complex_float* h, lapack_int ldh,\n                           lapack_complex_float* w, lapack_complex_float* z,\n                           lapack_int ldz );\nlapack_int LAPACKE_zhseqr( int matrix_order, char job, char compz, lapack_int n,\n                           lapack_int ilo, lapack_int ihi,\n                           lapack_complex_double* h, lapack_int ldh,\n                           lapack_complex_double* w, lapack_complex_double* z,\n                           lapack_int ldz );\n\nlapack_int LAPACKE_clacgv( lapack_int n, lapack_complex_float* x,\n                           lapack_int incx );\nlapack_int LAPACKE_zlacgv( lapack_int n, lapack_complex_double* x,\n                           lapack_int incx );\n\nlapack_int LAPACKE_slacpy( int matrix_order, char uplo, lapack_int m,\n                           lapack_int n, const float* a, lapack_int lda, float* b,\n                           lapack_int ldb );\nlapack_int LAPACKE_dlacpy( int matrix_order, char uplo, lapack_int m,\n                           lapack_int n, const double* a, lapack_int lda, double* b,\n                           lapack_int ldb );\nlapack_int LAPACKE_clacpy( int matrix_order, char uplo, lapack_int m,\n                           lapack_int n, const lapack_complex_float* a,\n                           lapack_int lda, lapack_complex_float* b,\n                           lapack_int ldb );\nlapack_int LAPACKE_zlacpy( int matrix_order, char uplo, lapack_int m,\n                           lapack_int n, const lapack_complex_double* a,\n                           lapack_int lda, lapack_complex_double* b,\n                           lapack_int ldb );\n\nlapack_int LAPACKE_zlag2c( int matrix_order, lapack_int m, lapack_int n,\n                           const lapack_complex_double* a, lapack_int lda,\n                           lapack_complex_float* sa, lapack_int ldsa );\n\nlapack_int LAPACKE_slag2d( int matrix_order, lapack_int m, lapack_int n,\n                           const float* sa, lapack_int ldsa, double* a,\n                           lapack_int lda );\n\nlapack_int LAPACKE_dlag2s( int matrix_order, lapack_int m, lapack_int n,\n                           const double* a, lapack_int lda, float* sa,\n                           lapack_int ldsa );\n\nlapack_int LAPACKE_clag2z( int matrix_order, lapack_int m, lapack_int n,\n                           const lapack_complex_float* sa, lapack_int ldsa,\n                           lapack_complex_double* a, lapack_int lda );\n\nlapack_int LAPACKE_slagge( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int kl, lapack_int ku, const float* d,\n                           float* a, lapack_int lda, lapack_int* iseed );\nlapack_int LAPACKE_dlagge( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int kl, lapack_int ku, const double* d,\n                           double* a, lapack_int lda, lapack_int* iseed );\nlapack_int LAPACKE_clagge( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int kl, lapack_int ku, const float* d,\n                           lapack_complex_float* a, lapack_int lda,\n                           lapack_int* iseed );\nlapack_int LAPACKE_zlagge( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int kl, lapack_int ku, const double* d,\n                           lapack_complex_double* a, lapack_int lda,\n                           lapack_int* iseed );\n\nfloat LAPACKE_slamch( char cmach );\ndouble LAPACKE_dlamch( char cmach );\n\nfloat LAPACKE_slange( int matrix_order, char norm, lapack_int m,\n                           lapack_int n, const float* a, lapack_int lda );\ndouble LAPACKE_dlange( int matrix_order, char norm, lapack_int m,\n                           lapack_int n, const double* a, lapack_int lda );\nfloat LAPACKE_clange( int matrix_order, char norm, lapack_int m,\n                           lapack_int n, const lapack_complex_float* a,\n                           lapack_int lda );\ndouble LAPACKE_zlange( int matrix_order, char norm, lapack_int m,\n                           lapack_int n, const lapack_complex_double* a,\n                           lapack_int lda );\n\nfloat LAPACKE_clanhe( int matrix_order, char norm, char uplo, lapack_int n,\n                           const lapack_complex_float* a, lapack_int lda );\ndouble LAPACKE_zlanhe( int matrix_order, char norm, char uplo, lapack_int n,\n                           const lapack_complex_double* a, lapack_int lda );\n\nfloat LAPACKE_slansy( int matrix_order, char norm, char uplo, lapack_int n,\n                           const float* a, lapack_int lda );\ndouble LAPACKE_dlansy( int matrix_order, char norm, char uplo, lapack_int n,\n                           const double* a, lapack_int lda );\nfloat LAPACKE_clansy( int matrix_order, char norm, char uplo, lapack_int n,\n                           const lapack_complex_float* a, lapack_int lda );\ndouble LAPACKE_zlansy( int matrix_order, char norm, char uplo, lapack_int n,\n                           const lapack_complex_double* a, lapack_int lda );\n\nfloat LAPACKE_slantr( int matrix_order, char norm, char uplo, char diag,\n                           lapack_int m, lapack_int n, const float* a,\n                           lapack_int lda );\ndouble LAPACKE_dlantr( int matrix_order, char norm, char uplo, char diag,\n                           lapack_int m, lapack_int n, const double* a,\n                           lapack_int lda );\nfloat LAPACKE_clantr( int matrix_order, char norm, char uplo, char diag,\n                           lapack_int m, lapack_int n, const lapack_complex_float* a,\n                           lapack_int lda );\ndouble LAPACKE_zlantr( int matrix_order, char norm, char uplo, char diag,\n                           lapack_int m, lapack_int n, const lapack_complex_double* a,\n                           lapack_int lda );\n\n\nlapack_int LAPACKE_slarfb( int matrix_order, char side, char trans, char direct,\n                           char storev, lapack_int m, lapack_int n,\n                           lapack_int k, const float* v, lapack_int ldv,\n                           const float* t, lapack_int ldt, float* c,\n                           lapack_int ldc );\nlapack_int LAPACKE_dlarfb( int matrix_order, char side, char trans, char direct,\n                           char storev, lapack_int m, lapack_int n,\n                           lapack_int k, const double* v, lapack_int ldv,\n                           const double* t, lapack_int ldt, double* c,\n                           lapack_int ldc );\nlapack_int LAPACKE_clarfb( int matrix_order, char side, char trans, char direct,\n                           char storev, lapack_int m, lapack_int n,\n                           lapack_int k, const lapack_complex_float* v,\n                           lapack_int ldv, const lapack_complex_float* t,\n                           lapack_int ldt, lapack_complex_float* c,\n                           lapack_int ldc );\nlapack_int LAPACKE_zlarfb( int matrix_order, char side, char trans, char direct,\n                           char storev, lapack_int m, lapack_int n,\n                           lapack_int k, const lapack_complex_double* v,\n                           lapack_int ldv, const lapack_complex_double* t,\n                           lapack_int ldt, lapack_complex_double* c,\n                           lapack_int ldc );\n\nlapack_int LAPACKE_slarfg( lapack_int n, float* alpha, float* x,\n                           lapack_int incx, float* tau );\nlapack_int LAPACKE_dlarfg( lapack_int n, double* alpha, double* x,\n                           lapack_int incx, double* tau );\nlapack_int LAPACKE_clarfg( lapack_int n, lapack_complex_float* alpha,\n                           lapack_complex_float* x, lapack_int incx,\n                           lapack_complex_float* tau );\nlapack_int LAPACKE_zlarfg( lapack_int n, lapack_complex_double* alpha,\n                           lapack_complex_double* x, lapack_int incx,\n                           lapack_complex_double* tau );\n\nlapack_int LAPACKE_slarft( int matrix_order, char direct, char storev,\n                           lapack_int n, lapack_int k, const float* v,\n                           lapack_int ldv, const float* tau, float* t,\n                           lapack_int ldt );\nlapack_int LAPACKE_dlarft( int matrix_order, char direct, char storev,\n                           lapack_int n, lapack_int k, const double* v,\n                           lapack_int ldv, const double* tau, double* t,\n                           lapack_int ldt );\nlapack_int LAPACKE_clarft( int matrix_order, char direct, char storev,\n                           lapack_int n, lapack_int k,\n                           const lapack_complex_float* v, lapack_int ldv,\n                           const lapack_complex_float* tau,\n                           lapack_complex_float* t, lapack_int ldt );\nlapack_int LAPACKE_zlarft( int matrix_order, char direct, char storev,\n                           lapack_int n, lapack_int k,\n                           const lapack_complex_double* v, lapack_int ldv,\n                           const lapack_complex_double* tau,\n                           lapack_complex_double* t, lapack_int ldt );\n\nlapack_int LAPACKE_slarfx( int matrix_order, char side, lapack_int m,\n                           lapack_int n, const float* v, float tau, float* c,\n                           lapack_int ldc, float* work );\nlapack_int LAPACKE_dlarfx( int matrix_order, char side, lapack_int m,\n                           lapack_int n, const double* v, double tau, double* c,\n                           lapack_int ldc, double* work );\nlapack_int LAPACKE_clarfx( int matrix_order, char side, lapack_int m,\n                           lapack_int n, const lapack_complex_float* v,\n                           lapack_complex_float tau, lapack_complex_float* c,\n                           lapack_int ldc, lapack_complex_float* work );\nlapack_int LAPACKE_zlarfx( int matrix_order, char side, lapack_int m,\n                           lapack_int n, const lapack_complex_double* v,\n                           lapack_complex_double tau, lapack_complex_double* c,\n                           lapack_int ldc, lapack_complex_double* work );\n\nlapack_int LAPACKE_slarnv( lapack_int idist, lapack_int* iseed, lapack_int n,\n                           float* x );\nlapack_int LAPACKE_dlarnv( lapack_int idist, lapack_int* iseed, lapack_int n,\n                           double* x );\nlapack_int LAPACKE_clarnv( lapack_int idist, lapack_int* iseed, lapack_int n,\n                           lapack_complex_float* x );\nlapack_int LAPACKE_zlarnv( lapack_int idist, lapack_int* iseed, lapack_int n,\n                           lapack_complex_double* x );\n\nlapack_int LAPACKE_slaset( int matrix_order, char uplo, lapack_int m,\n                           lapack_int n, float alpha, float beta, float* a,\n                           lapack_int lda );\nlapack_int LAPACKE_dlaset( int matrix_order, char uplo, lapack_int m,\n                           lapack_int n, double alpha, double beta, double* a,\n                           lapack_int lda );\nlapack_int LAPACKE_claset( int matrix_order, char uplo, lapack_int m,\n                           lapack_int n, lapack_complex_float alpha,\n                           lapack_complex_float beta, lapack_complex_float* a,\n                           lapack_int lda );\nlapack_int LAPACKE_zlaset( int matrix_order, char uplo, lapack_int m,\n                           lapack_int n, lapack_complex_double alpha,\n                           lapack_complex_double beta, lapack_complex_double* a,\n                           lapack_int lda );\n\nlapack_int LAPACKE_slasrt( char id, lapack_int n, float* d );\nlapack_int LAPACKE_dlasrt( char id, lapack_int n, double* d );\n\nlapack_int LAPACKE_slaswp( int matrix_order, lapack_int n, float* a,\n                           lapack_int lda, lapack_int k1, lapack_int k2,\n                           const lapack_int* ipiv, lapack_int incx );\nlapack_int LAPACKE_dlaswp( int matrix_order, lapack_int n, double* a,\n                           lapack_int lda, lapack_int k1, lapack_int k2,\n                           const lapack_int* ipiv, lapack_int incx );\nlapack_int LAPACKE_claswp( int matrix_order, lapack_int n,\n                           lapack_complex_float* a, lapack_int lda,\n                           lapack_int k1, lapack_int k2, const lapack_int* ipiv,\n                           lapack_int incx );\nlapack_int LAPACKE_zlaswp( int matrix_order, lapack_int n,\n                           lapack_complex_double* a, lapack_int lda,\n                           lapack_int k1, lapack_int k2, const lapack_int* ipiv,\n                           lapack_int incx );\n\nlapack_int LAPACKE_slatms( int matrix_order, lapack_int m, lapack_int n,\n                           char dist, lapack_int* iseed, char sym, float* d,\n                           lapack_int mode, float cond, float dmax,\n                           lapack_int kl, lapack_int ku, char pack, float* a,\n                           lapack_int lda );\nlapack_int LAPACKE_dlatms( int matrix_order, lapack_int m, lapack_int n,\n                           char dist, lapack_int* iseed, char sym, double* d,\n                           lapack_int mode, double cond, double dmax,\n                           lapack_int kl, lapack_int ku, char pack, double* a,\n                           lapack_int lda );\nlapack_int LAPACKE_clatms( int matrix_order, lapack_int m, lapack_int n,\n                           char dist, lapack_int* iseed, char sym, float* d,\n                           lapack_int mode, float cond, float dmax,\n                           lapack_int kl, lapack_int ku, char pack,\n                           lapack_complex_float* a, lapack_int lda );\nlapack_int LAPACKE_zlatms( int matrix_order, lapack_int m, lapack_int n,\n                           char dist, lapack_int* iseed, char sym, double* d,\n                           lapack_int mode, double cond, double dmax,\n                           lapack_int kl, lapack_int ku, char pack,\n                           lapack_complex_double* a, lapack_int lda );\n\nlapack_int LAPACKE_slauum( int matrix_order, char uplo, lapack_int n, float* a,\n                           lapack_int lda );\nlapack_int LAPACKE_dlauum( int matrix_order, char uplo, lapack_int n, double* a,\n                           lapack_int lda );\nlapack_int LAPACKE_clauum( int matrix_order, char uplo, lapack_int n,\n                           lapack_complex_float* a, lapack_int lda );\nlapack_int LAPACKE_zlauum( int matrix_order, char uplo, lapack_int n,\n                           lapack_complex_double* a, lapack_int lda );\n\nlapack_int LAPACKE_sopgtr( int matrix_order, char uplo, lapack_int n,\n                           const float* ap, const float* tau, float* q,\n                           lapack_int ldq );\nlapack_int LAPACKE_dopgtr( int matrix_order, char uplo, lapack_int n,\n                           const double* ap, const double* tau, double* q,\n                           lapack_int ldq );\n\nlapack_int LAPACKE_sopmtr( int matrix_order, char side, char uplo, char trans,\n                           lapack_int m, lapack_int n, const float* ap,\n                           const float* tau, float* c, lapack_int ldc );\nlapack_int LAPACKE_dopmtr( int matrix_order, char side, char uplo, char trans,\n                           lapack_int m, lapack_int n, const double* ap,\n                           const double* tau, double* c, lapack_int ldc );\n\nlapack_int LAPACKE_sorgbr( int matrix_order, char vect, lapack_int m,\n                           lapack_int n, lapack_int k, float* a, lapack_int lda,\n                           const float* tau );\nlapack_int LAPACKE_dorgbr( int matrix_order, char vect, lapack_int m,\n                           lapack_int n, lapack_int k, double* a,\n                           lapack_int lda, const double* tau );\n\nlapack_int LAPACKE_sorghr( int matrix_order, lapack_int n, lapack_int ilo,\n                           lapack_int ihi, float* a, lapack_int lda,\n                           const float* tau );\nlapack_int LAPACKE_dorghr( int matrix_order, lapack_int n, lapack_int ilo,\n                           lapack_int ihi, double* a, lapack_int lda,\n                           const double* tau );\n\nlapack_int LAPACKE_sorglq( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int k, float* a, lapack_int lda,\n                           const float* tau );\nlapack_int LAPACKE_dorglq( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int k, double* a, lapack_int lda,\n                           const double* tau );\n\nlapack_int LAPACKE_sorgql( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int k, float* a, lapack_int lda,\n                           const float* tau );\nlapack_int LAPACKE_dorgql( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int k, double* a, lapack_int lda,\n                           const double* tau );\n\nlapack_int LAPACKE_sorgqr( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int k, float* a, lapack_int lda,\n                           const float* tau );\nlapack_int LAPACKE_dorgqr( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int k, double* a, lapack_int lda,\n                           const double* tau );\n\nlapack_int LAPACKE_sorgrq( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int k, float* a, lapack_int lda,\n                           const float* tau );\nlapack_int LAPACKE_dorgrq( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int k, double* a, lapack_int lda,\n                           const double* tau );\n\nlapack_int LAPACKE_sorgtr( int matrix_order, char uplo, lapack_int n, float* a,\n                           lapack_int lda, const float* tau );\nlapack_int LAPACKE_dorgtr( int matrix_order, char uplo, lapack_int n, double* a,\n                           lapack_int lda, const double* tau );\n\nlapack_int LAPACKE_sormbr( int matrix_order, char vect, char side, char trans,\n                           lapack_int m, lapack_int n, lapack_int k,\n                           const float* a, lapack_int lda, const float* tau,\n                           float* c, lapack_int ldc );\nlapack_int LAPACKE_dormbr( int matrix_order, char vect, char side, char trans,\n                           lapack_int m, lapack_int n, lapack_int k,\n                           const double* a, lapack_int lda, const double* tau,\n                           double* c, lapack_int ldc );\n\nlapack_int LAPACKE_sormhr( int matrix_order, char side, char trans,\n                           lapack_int m, lapack_int n, lapack_int ilo,\n                           lapack_int ihi, const float* a, lapack_int lda,\n                           const float* tau, float* c, lapack_int ldc );\nlapack_int LAPACKE_dormhr( int matrix_order, char side, char trans,\n                           lapack_int m, lapack_int n, lapack_int ilo,\n                           lapack_int ihi, const double* a, lapack_int lda,\n                           const double* tau, double* c, lapack_int ldc );\n\nlapack_int LAPACKE_sormlq( int matrix_order, char side, char trans,\n                           lapack_int m, lapack_int n, lapack_int k,\n                           const float* a, lapack_int lda, const float* tau,\n                           float* c, lapack_int ldc );\nlapack_int LAPACKE_dormlq( int matrix_order, char side, char trans,\n                           lapack_int m, lapack_int n, lapack_int k,\n                           const double* a, lapack_int lda, const double* tau,\n                           double* c, lapack_int ldc );\n\nlapack_int LAPACKE_sormql( int matrix_order, char side, char trans,\n                           lapack_int m, lapack_int n, lapack_int k,\n                           const float* a, lapack_int lda, const float* tau,\n                           float* c, lapack_int ldc );\nlapack_int LAPACKE_dormql( int matrix_order, char side, char trans,\n                           lapack_int m, lapack_int n, lapack_int k,\n                           const double* a, lapack_int lda, const double* tau,\n                           double* c, lapack_int ldc );\n\nlapack_int LAPACKE_sormqr( int matrix_order, char side, char trans,\n                           lapack_int m, lapack_int n, lapack_int k,\n                           const float* a, lapack_int lda, const float* tau,\n                           float* c, lapack_int ldc );\nlapack_int LAPACKE_dormqr( int matrix_order, char side, char trans,\n                           lapack_int m, lapack_int n, lapack_int k,\n                           const double* a, lapack_int lda, const double* tau,\n                           double* c, lapack_int ldc );\n\nlapack_int LAPACKE_sormrq( int matrix_order, char side, char trans,\n                           lapack_int m, lapack_int n, lapack_int k,\n                           const float* a, lapack_int lda, const float* tau,\n                           float* c, lapack_int ldc );\nlapack_int LAPACKE_dormrq( int matrix_order, char side, char trans,\n                           lapack_int m, lapack_int n, lapack_int k,\n                           const double* a, lapack_int lda, const double* tau,\n                           double* c, lapack_int ldc );\n\nlapack_int LAPACKE_sormrz( int matrix_order, char side, char trans,\n                           lapack_int m, lapack_int n, lapack_int k,\n                           lapack_int l, const float* a, lapack_int lda,\n                           const float* tau, float* c, lapack_int ldc );\nlapack_int LAPACKE_dormrz( int matrix_order, char side, char trans,\n                           lapack_int m, lapack_int n, lapack_int k,\n                           lapack_int l, const double* a, lapack_int lda,\n                           const double* tau, double* c, lapack_int ldc );\n\nlapack_int LAPACKE_sormtr( int matrix_order, char side, char uplo, char trans,\n                           lapack_int m, lapack_int n, const float* a,\n                           lapack_int lda, const float* tau, float* c,\n                           lapack_int ldc );\nlapack_int LAPACKE_dormtr( int matrix_order, char side, char uplo, char trans,\n                           lapack_int m, lapack_int n, const double* a,\n                           lapack_int lda, const double* tau, double* c,\n                           lapack_int ldc );\n\nlapack_int LAPACKE_spbcon( int matrix_order, char uplo, lapack_int n,\n                           lapack_int kd, const float* ab, lapack_int ldab,\n                           float anorm, float* rcond );\nlapack_int LAPACKE_dpbcon( int matrix_order, char uplo, lapack_int n,\n                           lapack_int kd, const double* ab, lapack_int ldab,\n                           double anorm, double* rcond );\nlapack_int LAPACKE_cpbcon( int matrix_order, char uplo, lapack_int n,\n                           lapack_int kd, const lapack_complex_float* ab,\n                           lapack_int ldab, float anorm, float* rcond );\nlapack_int LAPACKE_zpbcon( int matrix_order, char uplo, lapack_int n,\n                           lapack_int kd, const lapack_complex_double* ab,\n                           lapack_int ldab, double anorm, double* rcond );\n\nlapack_int LAPACKE_spbequ( int matrix_order, char uplo, lapack_int n,\n                           lapack_int kd, const float* ab, lapack_int ldab,\n                           float* s, float* scond, float* amax );\nlapack_int LAPACKE_dpbequ( int matrix_order, char uplo, lapack_int n,\n                           lapack_int kd, const double* ab, lapack_int ldab,\n                           double* s, double* scond, double* amax );\nlapack_int LAPACKE_cpbequ( int matrix_order, char uplo, lapack_int n,\n                           lapack_int kd, const lapack_complex_float* ab,\n                           lapack_int ldab, float* s, float* scond,\n                           float* amax );\nlapack_int LAPACKE_zpbequ( int matrix_order, char uplo, lapack_int n,\n                           lapack_int kd, const lapack_complex_double* ab,\n                           lapack_int ldab, double* s, double* scond,\n                           double* amax );\n\nlapack_int LAPACKE_spbrfs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int kd, lapack_int nrhs, const float* ab,\n                           lapack_int ldab, const float* afb, lapack_int ldafb,\n                           const float* b, lapack_int ldb, float* x,\n                           lapack_int ldx, float* ferr, float* berr );\nlapack_int LAPACKE_dpbrfs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int kd, lapack_int nrhs, const double* ab,\n                           lapack_int ldab, const double* afb, lapack_int ldafb,\n                           const double* b, lapack_int ldb, double* x,\n                           lapack_int ldx, double* ferr, double* berr );\nlapack_int LAPACKE_cpbrfs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int kd, lapack_int nrhs,\n                           const lapack_complex_float* ab, lapack_int ldab,\n                           const lapack_complex_float* afb, lapack_int ldafb,\n                           const lapack_complex_float* b, lapack_int ldb,\n                           lapack_complex_float* x, lapack_int ldx, float* ferr,\n                           float* berr );\nlapack_int LAPACKE_zpbrfs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int kd, lapack_int nrhs,\n                           const lapack_complex_double* ab, lapack_int ldab,\n                           const lapack_complex_double* afb, lapack_int ldafb,\n                           const lapack_complex_double* b, lapack_int ldb,\n                           lapack_complex_double* x, lapack_int ldx,\n                           double* ferr, double* berr );\n\nlapack_int LAPACKE_spbstf( int matrix_order, char uplo, lapack_int n,\n                           lapack_int kb, float* bb, lapack_int ldbb );\nlapack_int LAPACKE_dpbstf( int matrix_order, char uplo, lapack_int n,\n                           lapack_int kb, double* bb, lapack_int ldbb );\nlapack_int LAPACKE_cpbstf( int matrix_order, char uplo, lapack_int n,\n                           lapack_int kb, lapack_complex_float* bb,\n                           lapack_int ldbb );\nlapack_int LAPACKE_zpbstf( int matrix_order, char uplo, lapack_int n,\n                           lapack_int kb, lapack_complex_double* bb,\n                           lapack_int ldbb );\n\nlapack_int LAPACKE_spbsv( int matrix_order, char uplo, lapack_int n,\n                          lapack_int kd, lapack_int nrhs, float* ab,\n                          lapack_int ldab, float* b, lapack_int ldb );\nlapack_int LAPACKE_dpbsv( int matrix_order, char uplo, lapack_int n,\n                          lapack_int kd, lapack_int nrhs, double* ab,\n                          lapack_int ldab, double* b, lapack_int ldb );\nlapack_int LAPACKE_cpbsv( int matrix_order, char uplo, lapack_int n,\n                          lapack_int kd, lapack_int nrhs,\n                          lapack_complex_float* ab, lapack_int ldab,\n                          lapack_complex_float* b, lapack_int ldb );\nlapack_int LAPACKE_zpbsv( int matrix_order, char uplo, lapack_int n,\n                          lapack_int kd, lapack_int nrhs,\n                          lapack_complex_double* ab, lapack_int ldab,\n                          lapack_complex_double* b, lapack_int ldb );\n\nlapack_int LAPACKE_spbsvx( int matrix_order, char fact, char uplo, lapack_int n,\n                           lapack_int kd, lapack_int nrhs, float* ab,\n                           lapack_int ldab, float* afb, lapack_int ldafb,\n                           char* equed, float* s, float* b, lapack_int ldb,\n                           float* x, lapack_int ldx, float* rcond, float* ferr,\n                           float* berr );\nlapack_int LAPACKE_dpbsvx( int matrix_order, char fact, char uplo, lapack_int n,\n                           lapack_int kd, lapack_int nrhs, double* ab,\n                           lapack_int ldab, double* afb, lapack_int ldafb,\n                           char* equed, double* s, double* b, lapack_int ldb,\n                           double* x, lapack_int ldx, double* rcond,\n                           double* ferr, double* berr );\nlapack_int LAPACKE_cpbsvx( int matrix_order, char fact, char uplo, lapack_int n,\n                           lapack_int kd, lapack_int nrhs,\n                           lapack_complex_float* ab, lapack_int ldab,\n                           lapack_complex_float* afb, lapack_int ldafb,\n                           char* equed, float* s, lapack_complex_float* b,\n                           lapack_int ldb, lapack_complex_float* x,\n                           lapack_int ldx, float* rcond, float* ferr,\n                           float* berr );\nlapack_int LAPACKE_zpbsvx( int matrix_order, char fact, char uplo, lapack_int n,\n                           lapack_int kd, lapack_int nrhs,\n                           lapack_complex_double* ab, lapack_int ldab,\n                           lapack_complex_double* afb, lapack_int ldafb,\n                           char* equed, double* s, lapack_complex_double* b,\n                           lapack_int ldb, lapack_complex_double* x,\n                           lapack_int ldx, double* rcond, double* ferr,\n                           double* berr );\n\nlapack_int LAPACKE_spbtrf( int matrix_order, char uplo, lapack_int n,\n                           lapack_int kd, float* ab, lapack_int ldab );\nlapack_int LAPACKE_dpbtrf( int matrix_order, char uplo, lapack_int n,\n                           lapack_int kd, double* ab, lapack_int ldab );\nlapack_int LAPACKE_cpbtrf( int matrix_order, char uplo, lapack_int n,\n                           lapack_int kd, lapack_complex_float* ab,\n                           lapack_int ldab );\nlapack_int LAPACKE_zpbtrf( int matrix_order, char uplo, lapack_int n,\n                           lapack_int kd, lapack_complex_double* ab,\n                           lapack_int ldab );\n\nlapack_int LAPACKE_spbtrs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int kd, lapack_int nrhs, const float* ab,\n                           lapack_int ldab, float* b, lapack_int ldb );\nlapack_int LAPACKE_dpbtrs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int kd, lapack_int nrhs, const double* ab,\n                           lapack_int ldab, double* b, lapack_int ldb );\nlapack_int LAPACKE_cpbtrs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int kd, lapack_int nrhs,\n                           const lapack_complex_float* ab, lapack_int ldab,\n                           lapack_complex_float* b, lapack_int ldb );\nlapack_int LAPACKE_zpbtrs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int kd, lapack_int nrhs,\n                           const lapack_complex_double* ab, lapack_int ldab,\n                           lapack_complex_double* b, lapack_int ldb );\n\nlapack_int LAPACKE_spftrf( int matrix_order, char transr, char uplo,\n                           lapack_int n, float* a );\nlapack_int LAPACKE_dpftrf( int matrix_order, char transr, char uplo,\n                           lapack_int n, double* a );\nlapack_int LAPACKE_cpftrf( int matrix_order, char transr, char uplo,\n                           lapack_int n, lapack_complex_float* a );\nlapack_int LAPACKE_zpftrf( int matrix_order, char transr, char uplo,\n                           lapack_int n, lapack_complex_double* a );\n\nlapack_int LAPACKE_spftri( int matrix_order, char transr, char uplo,\n                           lapack_int n, float* a );\nlapack_int LAPACKE_dpftri( int matrix_order, char transr, char uplo,\n                           lapack_int n, double* a );\nlapack_int LAPACKE_cpftri( int matrix_order, char transr, char uplo,\n                           lapack_int n, lapack_complex_float* a );\nlapack_int LAPACKE_zpftri( int matrix_order, char transr, char uplo,\n                           lapack_int n, lapack_complex_double* a );\n\nlapack_int LAPACKE_spftrs( int matrix_order, char transr, char uplo,\n                           lapack_int n, lapack_int nrhs, const float* a,\n                           float* b, lapack_int ldb );\nlapack_int LAPACKE_dpftrs( int matrix_order, char transr, char uplo,\n                           lapack_int n, lapack_int nrhs, const double* a,\n                           double* b, lapack_int ldb );\nlapack_int LAPACKE_cpftrs( int matrix_order, char transr, char uplo,\n                           lapack_int n, lapack_int nrhs,\n                           const lapack_complex_float* a,\n                           lapack_complex_float* b, lapack_int ldb );\nlapack_int LAPACKE_zpftrs( int matrix_order, char transr, char uplo,\n                           lapack_int n, lapack_int nrhs,\n                           const lapack_complex_double* a,\n                           lapack_complex_double* b, lapack_int ldb );\n\nlapack_int LAPACKE_spocon( int matrix_order, char uplo, lapack_int n,\n                           const float* a, lapack_int lda, float anorm,\n                           float* rcond );\nlapack_int LAPACKE_dpocon( int matrix_order, char uplo, lapack_int n,\n                           const double* a, lapack_int lda, double anorm,\n                           double* rcond );\nlapack_int LAPACKE_cpocon( int matrix_order, char uplo, lapack_int n,\n                           const lapack_complex_float* a, lapack_int lda,\n                           float anorm, float* rcond );\nlapack_int LAPACKE_zpocon( int matrix_order, char uplo, lapack_int n,\n                           const lapack_complex_double* a, lapack_int lda,\n                           double anorm, double* rcond );\n\nlapack_int LAPACKE_spoequ( int matrix_order, lapack_int n, const float* a,\n                           lapack_int lda, float* s, float* scond,\n                           float* amax );\nlapack_int LAPACKE_dpoequ( int matrix_order, lapack_int n, const double* a,\n                           lapack_int lda, double* s, double* scond,\n                           double* amax );\nlapack_int LAPACKE_cpoequ( int matrix_order, lapack_int n,\n                           const lapack_complex_float* a, lapack_int lda,\n                           float* s, float* scond, float* amax );\nlapack_int LAPACKE_zpoequ( int matrix_order, lapack_int n,\n                           const lapack_complex_double* a, lapack_int lda,\n                           double* s, double* scond, double* amax );\n\nlapack_int LAPACKE_spoequb( int matrix_order, lapack_int n, const float* a,\n                            lapack_int lda, float* s, float* scond,\n                            float* amax );\nlapack_int LAPACKE_dpoequb( int matrix_order, lapack_int n, const double* a,\n                            lapack_int lda, double* s, double* scond,\n                            double* amax );\nlapack_int LAPACKE_cpoequb( int matrix_order, lapack_int n,\n                            const lapack_complex_float* a, lapack_int lda,\n                            float* s, float* scond, float* amax );\nlapack_int LAPACKE_zpoequb( int matrix_order, lapack_int n,\n                            const lapack_complex_double* a, lapack_int lda,\n                            double* s, double* scond, double* amax );\n\nlapack_int LAPACKE_sporfs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const float* a, lapack_int lda,\n                           const float* af, lapack_int ldaf, const float* b,\n                           lapack_int ldb, float* x, lapack_int ldx,\n                           float* ferr, float* berr );\nlapack_int LAPACKE_dporfs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const double* a, lapack_int lda,\n                           const double* af, lapack_int ldaf, const double* b,\n                           lapack_int ldb, double* x, lapack_int ldx,\n                           double* ferr, double* berr );\nlapack_int LAPACKE_cporfs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_float* a,\n                           lapack_int lda, const lapack_complex_float* af,\n                           lapack_int ldaf, const lapack_complex_float* b,\n                           lapack_int ldb, lapack_complex_float* x,\n                           lapack_int ldx, float* ferr, float* berr );\nlapack_int LAPACKE_zporfs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_double* a,\n                           lapack_int lda, const lapack_complex_double* af,\n                           lapack_int ldaf, const lapack_complex_double* b,\n                           lapack_int ldb, lapack_complex_double* x,\n                           lapack_int ldx, double* ferr, double* berr );\n\nlapack_int LAPACKE_sporfsx( int matrix_order, char uplo, char equed,\n                            lapack_int n, lapack_int nrhs, const float* a,\n                            lapack_int lda, const float* af, lapack_int ldaf,\n                            const float* s, const float* b, lapack_int ldb,\n                            float* x, lapack_int ldx, float* rcond, float* berr,\n                            lapack_int n_err_bnds, float* err_bnds_norm,\n                            float* err_bnds_comp, lapack_int nparams,\n                            float* params );\nlapack_int LAPACKE_dporfsx( int matrix_order, char uplo, char equed,\n                            lapack_int n, lapack_int nrhs, const double* a,\n                            lapack_int lda, const double* af, lapack_int ldaf,\n                            const double* s, const double* b, lapack_int ldb,\n                            double* x, lapack_int ldx, double* rcond,\n                            double* berr, lapack_int n_err_bnds,\n                            double* err_bnds_norm, double* err_bnds_comp,\n                            lapack_int nparams, double* params );\nlapack_int LAPACKE_cporfsx( int matrix_order, char uplo, char equed,\n                            lapack_int n, lapack_int nrhs,\n                            const lapack_complex_float* a, lapack_int lda,\n                            const lapack_complex_float* af, lapack_int ldaf,\n                            const float* s, const lapack_complex_float* b,\n                            lapack_int ldb, lapack_complex_float* x,\n                            lapack_int ldx, float* rcond, float* berr,\n                            lapack_int n_err_bnds, float* err_bnds_norm,\n                            float* err_bnds_comp, lapack_int nparams,\n                            float* params );\nlapack_int LAPACKE_zporfsx( int matrix_order, char uplo, char equed,\n                            lapack_int n, lapack_int nrhs,\n                            const lapack_complex_double* a, lapack_int lda,\n                            const lapack_complex_double* af, lapack_int ldaf,\n                            const double* s, const lapack_complex_double* b,\n                            lapack_int ldb, lapack_complex_double* x,\n                            lapack_int ldx, double* rcond, double* berr,\n                            lapack_int n_err_bnds, double* err_bnds_norm,\n                            double* err_bnds_comp, lapack_int nparams,\n                            double* params );\n\nlapack_int LAPACKE_sposv( int matrix_order, char uplo, lapack_int n,\n                          lapack_int nrhs, float* a, lapack_int lda, float* b,\n                          lapack_int ldb );\nlapack_int LAPACKE_dposv( int matrix_order, char uplo, lapack_int n,\n                          lapack_int nrhs, double* a, lapack_int lda, double* b,\n                          lapack_int ldb );\nlapack_int LAPACKE_cposv( int matrix_order, char uplo, lapack_int n,\n                          lapack_int nrhs, lapack_complex_float* a,\n                          lapack_int lda, lapack_complex_float* b,\n                          lapack_int ldb );\nlapack_int LAPACKE_zposv( int matrix_order, char uplo, lapack_int n,\n                          lapack_int nrhs, lapack_complex_double* a,\n                          lapack_int lda, lapack_complex_double* b,\n                          lapack_int ldb );\nlapack_int LAPACKE_dsposv( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, double* a, lapack_int lda,\n                           double* b, lapack_int ldb, double* x, lapack_int ldx,\n                           lapack_int* iter );\nlapack_int LAPACKE_zcposv( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, lapack_complex_double* a,\n                           lapack_int lda, lapack_complex_double* b,\n                           lapack_int ldb, lapack_complex_double* x,\n                           lapack_int ldx, lapack_int* iter );\n\nlapack_int LAPACKE_sposvx( int matrix_order, char fact, char uplo, lapack_int n,\n                           lapack_int nrhs, float* a, lapack_int lda, float* af,\n                           lapack_int ldaf, char* equed, float* s, float* b,\n                           lapack_int ldb, float* x, lapack_int ldx,\n                           float* rcond, float* ferr, float* berr );\nlapack_int LAPACKE_dposvx( int matrix_order, char fact, char uplo, lapack_int n,\n                           lapack_int nrhs, double* a, lapack_int lda,\n                           double* af, lapack_int ldaf, char* equed, double* s,\n                           double* b, lapack_int ldb, double* x, lapack_int ldx,\n                           double* rcond, double* ferr, double* berr );\nlapack_int LAPACKE_cposvx( int matrix_order, char fact, char uplo, lapack_int n,\n                           lapack_int nrhs, lapack_complex_float* a,\n                           lapack_int lda, lapack_complex_float* af,\n                           lapack_int ldaf, char* equed, float* s,\n                           lapack_complex_float* b, lapack_int ldb,\n                           lapack_complex_float* x, lapack_int ldx,\n                           float* rcond, float* ferr, float* berr );\nlapack_int LAPACKE_zposvx( int matrix_order, char fact, char uplo, lapack_int n,\n                           lapack_int nrhs, lapack_complex_double* a,\n                           lapack_int lda, lapack_complex_double* af,\n                           lapack_int ldaf, char* equed, double* s,\n                           lapack_complex_double* b, lapack_int ldb,\n                           lapack_complex_double* x, lapack_int ldx,\n                           double* rcond, double* ferr, double* berr );\n\nlapack_int LAPACKE_sposvxx( int matrix_order, char fact, char uplo,\n                            lapack_int n, lapack_int nrhs, float* a,\n                            lapack_int lda, float* af, lapack_int ldaf,\n                            char* equed, float* s, float* b, lapack_int ldb,\n                            float* x, lapack_int ldx, float* rcond,\n                            float* rpvgrw, float* berr, lapack_int n_err_bnds,\n                            float* err_bnds_norm, float* err_bnds_comp,\n                            lapack_int nparams, float* params );\nlapack_int LAPACKE_dposvxx( int matrix_order, char fact, char uplo,\n                            lapack_int n, lapack_int nrhs, double* a,\n                            lapack_int lda, double* af, lapack_int ldaf,\n                            char* equed, double* s, double* b, lapack_int ldb,\n                            double* x, lapack_int ldx, double* rcond,\n                            double* rpvgrw, double* berr, lapack_int n_err_bnds,\n                            double* err_bnds_norm, double* err_bnds_comp,\n                            lapack_int nparams, double* params );\nlapack_int LAPACKE_cposvxx( int matrix_order, char fact, char uplo,\n                            lapack_int n, lapack_int nrhs,\n                            lapack_complex_float* a, lapack_int lda,\n                            lapack_complex_float* af, lapack_int ldaf,\n                            char* equed, float* s, lapack_complex_float* b,\n                            lapack_int ldb, lapack_complex_float* x,\n                            lapack_int ldx, float* rcond, float* rpvgrw,\n                            float* berr, lapack_int n_err_bnds,\n                            float* err_bnds_norm, float* err_bnds_comp,\n                            lapack_int nparams, float* params );\nlapack_int LAPACKE_zposvxx( int matrix_order, char fact, char uplo,\n                            lapack_int n, lapack_int nrhs,\n                            lapack_complex_double* a, lapack_int lda,\n                            lapack_complex_double* af, lapack_int ldaf,\n                            char* equed, double* s, lapack_complex_double* b,\n                            lapack_int ldb, lapack_complex_double* x,\n                            lapack_int ldx, double* rcond, double* rpvgrw,\n                            double* berr, lapack_int n_err_bnds,\n                            double* err_bnds_norm, double* err_bnds_comp,\n                            lapack_int nparams, double* params );\n\nlapack_int LAPACKE_spotrf( int matrix_order, char uplo, lapack_int n, float* a,\n                           lapack_int lda );\nlapack_int LAPACKE_dpotrf( int matrix_order, char uplo, lapack_int n, double* a,\n                           lapack_int lda );\nlapack_int LAPACKE_cpotrf( int matrix_order, char uplo, lapack_int n,\n                           lapack_complex_float* a, lapack_int lda );\nlapack_int LAPACKE_zpotrf( int matrix_order, char uplo, lapack_int n,\n                           lapack_complex_double* a, lapack_int lda );\n\nlapack_int LAPACKE_spotri( int matrix_order, char uplo, lapack_int n, float* a,\n                           lapack_int lda );\nlapack_int LAPACKE_dpotri( int matrix_order, char uplo, lapack_int n, double* a,\n                           lapack_int lda );\nlapack_int LAPACKE_cpotri( int matrix_order, char uplo, lapack_int n,\n                           lapack_complex_float* a, lapack_int lda );\nlapack_int LAPACKE_zpotri( int matrix_order, char uplo, lapack_int n,\n                           lapack_complex_double* a, lapack_int lda );\n\nlapack_int LAPACKE_spotrs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const float* a, lapack_int lda,\n                           float* b, lapack_int ldb );\nlapack_int LAPACKE_dpotrs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const double* a, lapack_int lda,\n                           double* b, lapack_int ldb );\nlapack_int LAPACKE_cpotrs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_float* a,\n                           lapack_int lda, lapack_complex_float* b,\n                           lapack_int ldb );\nlapack_int LAPACKE_zpotrs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_double* a,\n                           lapack_int lda, lapack_complex_double* b,\n                           lapack_int ldb );\n\nlapack_int LAPACKE_sppcon( int matrix_order, char uplo, lapack_int n,\n                           const float* ap, float anorm, float* rcond );\nlapack_int LAPACKE_dppcon( int matrix_order, char uplo, lapack_int n,\n                           const double* ap, double anorm, double* rcond );\nlapack_int LAPACKE_cppcon( int matrix_order, char uplo, lapack_int n,\n                           const lapack_complex_float* ap, float anorm,\n                           float* rcond );\nlapack_int LAPACKE_zppcon( int matrix_order, char uplo, lapack_int n,\n                           const lapack_complex_double* ap, double anorm,\n                           double* rcond );\n\nlapack_int LAPACKE_sppequ( int matrix_order, char uplo, lapack_int n,\n                           const float* ap, float* s, float* scond,\n                           float* amax );\nlapack_int LAPACKE_dppequ( int matrix_order, char uplo, lapack_int n,\n                           const double* ap, double* s, double* scond,\n                           double* amax );\nlapack_int LAPACKE_cppequ( int matrix_order, char uplo, lapack_int n,\n                           const lapack_complex_float* ap, float* s,\n                           float* scond, float* amax );\nlapack_int LAPACKE_zppequ( int matrix_order, char uplo, lapack_int n,\n                           const lapack_complex_double* ap, double* s,\n                           double* scond, double* amax );\n\nlapack_int LAPACKE_spprfs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const float* ap, const float* afp,\n                           const float* b, lapack_int ldb, float* x,\n                           lapack_int ldx, float* ferr, float* berr );\nlapack_int LAPACKE_dpprfs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const double* ap, const double* afp,\n                           const double* b, lapack_int ldb, double* x,\n                           lapack_int ldx, double* ferr, double* berr );\nlapack_int LAPACKE_cpprfs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_float* ap,\n                           const lapack_complex_float* afp,\n                           const lapack_complex_float* b, lapack_int ldb,\n                           lapack_complex_float* x, lapack_int ldx, float* ferr,\n                           float* berr );\nlapack_int LAPACKE_zpprfs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_double* ap,\n                           const lapack_complex_double* afp,\n                           const lapack_complex_double* b, lapack_int ldb,\n                           lapack_complex_double* x, lapack_int ldx,\n                           double* ferr, double* berr );\n\nlapack_int LAPACKE_sppsv( int matrix_order, char uplo, lapack_int n,\n                          lapack_int nrhs, float* ap, float* b,\n                          lapack_int ldb );\nlapack_int LAPACKE_dppsv( int matrix_order, char uplo, lapack_int n,\n                          lapack_int nrhs, double* ap, double* b,\n                          lapack_int ldb );\nlapack_int LAPACKE_cppsv( int matrix_order, char uplo, lapack_int n,\n                          lapack_int nrhs, lapack_complex_float* ap,\n                          lapack_complex_float* b, lapack_int ldb );\nlapack_int LAPACKE_zppsv( int matrix_order, char uplo, lapack_int n,\n                          lapack_int nrhs, lapack_complex_double* ap,\n                          lapack_complex_double* b, lapack_int ldb );\n\nlapack_int LAPACKE_sppsvx( int matrix_order, char fact, char uplo, lapack_int n,\n                           lapack_int nrhs, float* ap, float* afp, char* equed,\n                           float* s, float* b, lapack_int ldb, float* x,\n                           lapack_int ldx, float* rcond, float* ferr,\n                           float* berr );\nlapack_int LAPACKE_dppsvx( int matrix_order, char fact, char uplo, lapack_int n,\n                           lapack_int nrhs, double* ap, double* afp,\n                           char* equed, double* s, double* b, lapack_int ldb,\n                           double* x, lapack_int ldx, double* rcond,\n                           double* ferr, double* berr );\nlapack_int LAPACKE_cppsvx( int matrix_order, char fact, char uplo, lapack_int n,\n                           lapack_int nrhs, lapack_complex_float* ap,\n                           lapack_complex_float* afp, char* equed, float* s,\n                           lapack_complex_float* b, lapack_int ldb,\n                           lapack_complex_float* x, lapack_int ldx,\n                           float* rcond, float* ferr, float* berr );\nlapack_int LAPACKE_zppsvx( int matrix_order, char fact, char uplo, lapack_int n,\n                           lapack_int nrhs, lapack_complex_double* ap,\n                           lapack_complex_double* afp, char* equed, double* s,\n                           lapack_complex_double* b, lapack_int ldb,\n                           lapack_complex_double* x, lapack_int ldx,\n                           double* rcond, double* ferr, double* berr );\n\nlapack_int LAPACKE_spptrf( int matrix_order, char uplo, lapack_int n,\n                           float* ap );\nlapack_int LAPACKE_dpptrf( int matrix_order, char uplo, lapack_int n,\n                           double* ap );\nlapack_int LAPACKE_cpptrf( int matrix_order, char uplo, lapack_int n,\n                           lapack_complex_float* ap );\nlapack_int LAPACKE_zpptrf( int matrix_order, char uplo, lapack_int n,\n                           lapack_complex_double* ap );\n\nlapack_int LAPACKE_spptri( int matrix_order, char uplo, lapack_int n,\n                           float* ap );\nlapack_int LAPACKE_dpptri( int matrix_order, char uplo, lapack_int n,\n                           double* ap );\nlapack_int LAPACKE_cpptri( int matrix_order, char uplo, lapack_int n,\n                           lapack_complex_float* ap );\nlapack_int LAPACKE_zpptri( int matrix_order, char uplo, lapack_int n,\n                           lapack_complex_double* ap );\n\nlapack_int LAPACKE_spptrs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const float* ap, float* b,\n                           lapack_int ldb );\nlapack_int LAPACKE_dpptrs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const double* ap, double* b,\n                           lapack_int ldb );\nlapack_int LAPACKE_cpptrs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_float* ap,\n                           lapack_complex_float* b, lapack_int ldb );\nlapack_int LAPACKE_zpptrs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_double* ap,\n                           lapack_complex_double* b, lapack_int ldb );\n\nlapack_int LAPACKE_spstrf( int matrix_order, char uplo, lapack_int n, float* a,\n                           lapack_int lda, lapack_int* piv, lapack_int* rank,\n                           float tol );\nlapack_int LAPACKE_dpstrf( int matrix_order, char uplo, lapack_int n, double* a,\n                           lapack_int lda, lapack_int* piv, lapack_int* rank,\n                           double tol );\nlapack_int LAPACKE_cpstrf( int matrix_order, char uplo, lapack_int n,\n                           lapack_complex_float* a, lapack_int lda,\n                           lapack_int* piv, lapack_int* rank, float tol );\nlapack_int LAPACKE_zpstrf( int matrix_order, char uplo, lapack_int n,\n                           lapack_complex_double* a, lapack_int lda,\n                           lapack_int* piv, lapack_int* rank, double tol );\n\nlapack_int LAPACKE_sptcon( lapack_int n, const float* d, const float* e,\n                           float anorm, float* rcond );\nlapack_int LAPACKE_dptcon( lapack_int n, const double* d, const double* e,\n                           double anorm, double* rcond );\nlapack_int LAPACKE_cptcon( lapack_int n, const float* d,\n                           const lapack_complex_float* e, float anorm,\n                           float* rcond );\nlapack_int LAPACKE_zptcon( lapack_int n, const double* d,\n                           const lapack_complex_double* e, double anorm,\n                           double* rcond );\n\nlapack_int LAPACKE_spteqr( int matrix_order, char compz, lapack_int n, float* d,\n                           float* e, float* z, lapack_int ldz );\nlapack_int LAPACKE_dpteqr( int matrix_order, char compz, lapack_int n,\n                           double* d, double* e, double* z, lapack_int ldz );\nlapack_int LAPACKE_cpteqr( int matrix_order, char compz, lapack_int n, float* d,\n                           float* e, lapack_complex_float* z, lapack_int ldz );\nlapack_int LAPACKE_zpteqr( int matrix_order, char compz, lapack_int n,\n                           double* d, double* e, lapack_complex_double* z,\n                           lapack_int ldz );\n\nlapack_int LAPACKE_sptrfs( int matrix_order, lapack_int n, lapack_int nrhs,\n                           const float* d, const float* e, const float* df,\n                           const float* ef, const float* b, lapack_int ldb,\n                           float* x, lapack_int ldx, float* ferr, float* berr );\nlapack_int LAPACKE_dptrfs( int matrix_order, lapack_int n, lapack_int nrhs,\n                           const double* d, const double* e, const double* df,\n                           const double* ef, const double* b, lapack_int ldb,\n                           double* x, lapack_int ldx, double* ferr,\n                           double* berr );\nlapack_int LAPACKE_cptrfs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const float* d,\n                           const lapack_complex_float* e, const float* df,\n                           const lapack_complex_float* ef,\n                           const lapack_complex_float* b, lapack_int ldb,\n                           lapack_complex_float* x, lapack_int ldx, float* ferr,\n                           float* berr );\nlapack_int LAPACKE_zptrfs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const double* d,\n                           const lapack_complex_double* e, const double* df,\n                           const lapack_complex_double* ef,\n                           const lapack_complex_double* b, lapack_int ldb,\n                           lapack_complex_double* x, lapack_int ldx,\n                           double* ferr, double* berr );\n\nlapack_int LAPACKE_sptsv( int matrix_order, lapack_int n, lapack_int nrhs,\n                          float* d, float* e, float* b, lapack_int ldb );\nlapack_int LAPACKE_dptsv( int matrix_order, lapack_int n, lapack_int nrhs,\n                          double* d, double* e, double* b, lapack_int ldb );\nlapack_int LAPACKE_cptsv( int matrix_order, lapack_int n, lapack_int nrhs,\n                          float* d, lapack_complex_float* e,\n                          lapack_complex_float* b, lapack_int ldb );\nlapack_int LAPACKE_zptsv( int matrix_order, lapack_int n, lapack_int nrhs,\n                          double* d, lapack_complex_double* e,\n                          lapack_complex_double* b, lapack_int ldb );\n\nlapack_int LAPACKE_sptsvx( int matrix_order, char fact, lapack_int n,\n                           lapack_int nrhs, const float* d, const float* e,\n                           float* df, float* ef, const float* b, lapack_int ldb,\n                           float* x, lapack_int ldx, float* rcond, float* ferr,\n                           float* berr );\nlapack_int LAPACKE_dptsvx( int matrix_order, char fact, lapack_int n,\n                           lapack_int nrhs, const double* d, const double* e,\n                           double* df, double* ef, const double* b,\n                           lapack_int ldb, double* x, lapack_int ldx,\n                           double* rcond, double* ferr, double* berr );\nlapack_int LAPACKE_cptsvx( int matrix_order, char fact, lapack_int n,\n                           lapack_int nrhs, const float* d,\n                           const lapack_complex_float* e, float* df,\n                           lapack_complex_float* ef,\n                           const lapack_complex_float* b, lapack_int ldb,\n                           lapack_complex_float* x, lapack_int ldx,\n                           float* rcond, float* ferr, float* berr );\nlapack_int LAPACKE_zptsvx( int matrix_order, char fact, lapack_int n,\n                           lapack_int nrhs, const double* d,\n                           const lapack_complex_double* e, double* df,\n                           lapack_complex_double* ef,\n                           const lapack_complex_double* b, lapack_int ldb,\n                           lapack_complex_double* x, lapack_int ldx,\n                           double* rcond, double* ferr, double* berr );\n\nlapack_int LAPACKE_spttrf( lapack_int n, float* d, float* e );\nlapack_int LAPACKE_dpttrf( lapack_int n, double* d, double* e );\nlapack_int LAPACKE_cpttrf( lapack_int n, float* d, lapack_complex_float* e );\nlapack_int LAPACKE_zpttrf( lapack_int n, double* d, lapack_complex_double* e );\n\nlapack_int LAPACKE_spttrs( int matrix_order, lapack_int n, lapack_int nrhs,\n                           const float* d, const float* e, float* b,\n                           lapack_int ldb );\nlapack_int LAPACKE_dpttrs( int matrix_order, lapack_int n, lapack_int nrhs,\n                           const double* d, const double* e, double* b,\n                           lapack_int ldb );\nlapack_int LAPACKE_cpttrs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const float* d,\n                           const lapack_complex_float* e,\n                           lapack_complex_float* b, lapack_int ldb );\nlapack_int LAPACKE_zpttrs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const double* d,\n                           const lapack_complex_double* e,\n                           lapack_complex_double* b, lapack_int ldb );\n\nlapack_int LAPACKE_ssbev( int matrix_order, char jobz, char uplo, lapack_int n,\n                          lapack_int kd, float* ab, lapack_int ldab, float* w,\n                          float* z, lapack_int ldz );\nlapack_int LAPACKE_dsbev( int matrix_order, char jobz, char uplo, lapack_int n,\n                          lapack_int kd, double* ab, lapack_int ldab, double* w,\n                          double* z, lapack_int ldz );\n\nlapack_int LAPACKE_ssbevd( int matrix_order, char jobz, char uplo, lapack_int n,\n                           lapack_int kd, float* ab, lapack_int ldab, float* w,\n                           float* z, lapack_int ldz );\nlapack_int LAPACKE_dsbevd( int matrix_order, char jobz, char uplo, lapack_int n,\n                           lapack_int kd, double* ab, lapack_int ldab,\n                           double* w, double* z, lapack_int ldz );\n\nlapack_int LAPACKE_ssbevx( int matrix_order, char jobz, char range, char uplo,\n                           lapack_int n, lapack_int kd, float* ab,\n                           lapack_int ldab, float* q, lapack_int ldq, float vl,\n                           float vu, lapack_int il, lapack_int iu, float abstol,\n                           lapack_int* m, float* w, float* z, lapack_int ldz,\n                           lapack_int* ifail );\nlapack_int LAPACKE_dsbevx( int matrix_order, char jobz, char range, char uplo,\n                           lapack_int n, lapack_int kd, double* ab,\n                           lapack_int ldab, double* q, lapack_int ldq,\n                           double vl, double vu, lapack_int il, lapack_int iu,\n                           double abstol, lapack_int* m, double* w, double* z,\n                           lapack_int ldz, lapack_int* ifail );\n\nlapack_int LAPACKE_ssbgst( int matrix_order, char vect, char uplo, lapack_int n,\n                           lapack_int ka, lapack_int kb, float* ab,\n                           lapack_int ldab, const float* bb, lapack_int ldbb,\n                           float* x, lapack_int ldx );\nlapack_int LAPACKE_dsbgst( int matrix_order, char vect, char uplo, lapack_int n,\n                           lapack_int ka, lapack_int kb, double* ab,\n                           lapack_int ldab, const double* bb, lapack_int ldbb,\n                           double* x, lapack_int ldx );\n\nlapack_int LAPACKE_ssbgv( int matrix_order, char jobz, char uplo, lapack_int n,\n                          lapack_int ka, lapack_int kb, float* ab,\n                          lapack_int ldab, float* bb, lapack_int ldbb, float* w,\n                          float* z, lapack_int ldz );\nlapack_int LAPACKE_dsbgv( int matrix_order, char jobz, char uplo, lapack_int n,\n                          lapack_int ka, lapack_int kb, double* ab,\n                          lapack_int ldab, double* bb, lapack_int ldbb,\n                          double* w, double* z, lapack_int ldz );\n\nlapack_int LAPACKE_ssbgvd( int matrix_order, char jobz, char uplo, lapack_int n,\n                           lapack_int ka, lapack_int kb, float* ab,\n                           lapack_int ldab, float* bb, lapack_int ldbb,\n                           float* w, float* z, lapack_int ldz );\nlapack_int LAPACKE_dsbgvd( int matrix_order, char jobz, char uplo, lapack_int n,\n                           lapack_int ka, lapack_int kb, double* ab,\n                           lapack_int ldab, double* bb, lapack_int ldbb,\n                           double* w, double* z, lapack_int ldz );\n\nlapack_int LAPACKE_ssbgvx( int matrix_order, char jobz, char range, char uplo,\n                           lapack_int n, lapack_int ka, lapack_int kb,\n                           float* ab, lapack_int ldab, float* bb,\n                           lapack_int ldbb, float* q, lapack_int ldq, float vl,\n                           float vu, lapack_int il, lapack_int iu, float abstol,\n                           lapack_int* m, float* w, float* z, lapack_int ldz,\n                           lapack_int* ifail );\nlapack_int LAPACKE_dsbgvx( int matrix_order, char jobz, char range, char uplo,\n                           lapack_int n, lapack_int ka, lapack_int kb,\n                           double* ab, lapack_int ldab, double* bb,\n                           lapack_int ldbb, double* q, lapack_int ldq,\n                           double vl, double vu, lapack_int il, lapack_int iu,\n                           double abstol, lapack_int* m, double* w, double* z,\n                           lapack_int ldz, lapack_int* ifail );\n\nlapack_int LAPACKE_ssbtrd( int matrix_order, char vect, char uplo, lapack_int n,\n                           lapack_int kd, float* ab, lapack_int ldab, float* d,\n                           float* e, float* q, lapack_int ldq );\nlapack_int LAPACKE_dsbtrd( int matrix_order, char vect, char uplo, lapack_int n,\n                           lapack_int kd, double* ab, lapack_int ldab,\n                           double* d, double* e, double* q, lapack_int ldq );\n\nlapack_int LAPACKE_ssfrk( int matrix_order, char transr, char uplo, char trans,\n                          lapack_int n, lapack_int k, float alpha,\n                          const float* a, lapack_int lda, float beta,\n                          float* c );\nlapack_int LAPACKE_dsfrk( int matrix_order, char transr, char uplo, char trans,\n                          lapack_int n, lapack_int k, double alpha,\n                          const double* a, lapack_int lda, double beta,\n                          double* c );\n\nlapack_int LAPACKE_sspcon( int matrix_order, char uplo, lapack_int n,\n                           const float* ap, const lapack_int* ipiv, float anorm,\n                           float* rcond );\nlapack_int LAPACKE_dspcon( int matrix_order, char uplo, lapack_int n,\n                           const double* ap, const lapack_int* ipiv,\n                           double anorm, double* rcond );\nlapack_int LAPACKE_cspcon( int matrix_order, char uplo, lapack_int n,\n                           const lapack_complex_float* ap,\n                           const lapack_int* ipiv, float anorm, float* rcond );\nlapack_int LAPACKE_zspcon( int matrix_order, char uplo, lapack_int n,\n                           const lapack_complex_double* ap,\n                           const lapack_int* ipiv, double anorm,\n                           double* rcond );\n\nlapack_int LAPACKE_sspev( int matrix_order, char jobz, char uplo, lapack_int n,\n                          float* ap, float* w, float* z, lapack_int ldz );\nlapack_int LAPACKE_dspev( int matrix_order, char jobz, char uplo, lapack_int n,\n                          double* ap, double* w, double* z, lapack_int ldz );\n\nlapack_int LAPACKE_sspevd( int matrix_order, char jobz, char uplo, lapack_int n,\n                           float* ap, float* w, float* z, lapack_int ldz );\nlapack_int LAPACKE_dspevd( int matrix_order, char jobz, char uplo, lapack_int n,\n                           double* ap, double* w, double* z, lapack_int ldz );\n\nlapack_int LAPACKE_sspevx( int matrix_order, char jobz, char range, char uplo,\n                           lapack_int n, float* ap, float vl, float vu,\n                           lapack_int il, lapack_int iu, float abstol,\n                           lapack_int* m, float* w, float* z, lapack_int ldz,\n                           lapack_int* ifail );\nlapack_int LAPACKE_dspevx( int matrix_order, char jobz, char range, char uplo,\n                           lapack_int n, double* ap, double vl, double vu,\n                           lapack_int il, lapack_int iu, double abstol,\n                           lapack_int* m, double* w, double* z, lapack_int ldz,\n                           lapack_int* ifail );\n\nlapack_int LAPACKE_sspgst( int matrix_order, lapack_int itype, char uplo,\n                           lapack_int n, float* ap, const float* bp );\nlapack_int LAPACKE_dspgst( int matrix_order, lapack_int itype, char uplo,\n                           lapack_int n, double* ap, const double* bp );\n\nlapack_int LAPACKE_sspgv( int matrix_order, lapack_int itype, char jobz,\n                          char uplo, lapack_int n, float* ap, float* bp,\n                          float* w, float* z, lapack_int ldz );\nlapack_int LAPACKE_dspgv( int matrix_order, lapack_int itype, char jobz,\n                          char uplo, lapack_int n, double* ap, double* bp,\n                          double* w, double* z, lapack_int ldz );\n\nlapack_int LAPACKE_sspgvd( int matrix_order, lapack_int itype, char jobz,\n                           char uplo, lapack_int n, float* ap, float* bp,\n                           float* w, float* z, lapack_int ldz );\nlapack_int LAPACKE_dspgvd( int matrix_order, lapack_int itype, char jobz,\n                           char uplo, lapack_int n, double* ap, double* bp,\n                           double* w, double* z, lapack_int ldz );\n\nlapack_int LAPACKE_sspgvx( int matrix_order, lapack_int itype, char jobz,\n                           char range, char uplo, lapack_int n, float* ap,\n                           float* bp, float vl, float vu, lapack_int il,\n                           lapack_int iu, float abstol, lapack_int* m, float* w,\n                           float* z, lapack_int ldz, lapack_int* ifail );\nlapack_int LAPACKE_dspgvx( int matrix_order, lapack_int itype, char jobz,\n                           char range, char uplo, lapack_int n, double* ap,\n                           double* bp, double vl, double vu, lapack_int il,\n                           lapack_int iu, double abstol, lapack_int* m,\n                           double* w, double* z, lapack_int ldz,\n                           lapack_int* ifail );\n\nlapack_int LAPACKE_ssprfs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const float* ap, const float* afp,\n                           const lapack_int* ipiv, const float* b,\n                           lapack_int ldb, float* x, lapack_int ldx,\n                           float* ferr, float* berr );\nlapack_int LAPACKE_dsprfs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const double* ap, const double* afp,\n                           const lapack_int* ipiv, const double* b,\n                           lapack_int ldb, double* x, lapack_int ldx,\n                           double* ferr, double* berr );\nlapack_int LAPACKE_csprfs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_float* ap,\n                           const lapack_complex_float* afp,\n                           const lapack_int* ipiv,\n                           const lapack_complex_float* b, lapack_int ldb,\n                           lapack_complex_float* x, lapack_int ldx, float* ferr,\n                           float* berr );\nlapack_int LAPACKE_zsprfs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_double* ap,\n                           const lapack_complex_double* afp,\n                           const lapack_int* ipiv,\n                           const lapack_complex_double* b, lapack_int ldb,\n                           lapack_complex_double* x, lapack_int ldx,\n                           double* ferr, double* berr );\n\nlapack_int LAPACKE_sspsv( int matrix_order, char uplo, lapack_int n,\n                          lapack_int nrhs, float* ap, lapack_int* ipiv,\n                          float* b, lapack_int ldb );\nlapack_int LAPACKE_dspsv( int matrix_order, char uplo, lapack_int n,\n                          lapack_int nrhs, double* ap, lapack_int* ipiv,\n                          double* b, lapack_int ldb );\nlapack_int LAPACKE_cspsv( int matrix_order, char uplo, lapack_int n,\n                          lapack_int nrhs, lapack_complex_float* ap,\n                          lapack_int* ipiv, lapack_complex_float* b,\n                          lapack_int ldb );\nlapack_int LAPACKE_zspsv( int matrix_order, char uplo, lapack_int n,\n                          lapack_int nrhs, lapack_complex_double* ap,\n                          lapack_int* ipiv, lapack_complex_double* b,\n                          lapack_int ldb );\n\nlapack_int LAPACKE_sspsvx( int matrix_order, char fact, char uplo, lapack_int n,\n                           lapack_int nrhs, const float* ap, float* afp,\n                           lapack_int* ipiv, const float* b, lapack_int ldb,\n                           float* x, lapack_int ldx, float* rcond, float* ferr,\n                           float* berr );\nlapack_int LAPACKE_dspsvx( int matrix_order, char fact, char uplo, lapack_int n,\n                           lapack_int nrhs, const double* ap, double* afp,\n                           lapack_int* ipiv, const double* b, lapack_int ldb,\n                           double* x, lapack_int ldx, double* rcond,\n                           double* ferr, double* berr );\nlapack_int LAPACKE_cspsvx( int matrix_order, char fact, char uplo, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_float* ap,\n                           lapack_complex_float* afp, lapack_int* ipiv,\n                           const lapack_complex_float* b, lapack_int ldb,\n                           lapack_complex_float* x, lapack_int ldx,\n                           float* rcond, float* ferr, float* berr );\nlapack_int LAPACKE_zspsvx( int matrix_order, char fact, char uplo, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_double* ap,\n                           lapack_complex_double* afp, lapack_int* ipiv,\n                           const lapack_complex_double* b, lapack_int ldb,\n                           lapack_complex_double* x, lapack_int ldx,\n                           double* rcond, double* ferr, double* berr );\n\nlapack_int LAPACKE_ssptrd( int matrix_order, char uplo, lapack_int n, float* ap,\n                           float* d, float* e, float* tau );\nlapack_int LAPACKE_dsptrd( int matrix_order, char uplo, lapack_int n,\n                           double* ap, double* d, double* e, double* tau );\n\nlapack_int LAPACKE_ssptrf( int matrix_order, char uplo, lapack_int n, float* ap,\n                           lapack_int* ipiv );\nlapack_int LAPACKE_dsptrf( int matrix_order, char uplo, lapack_int n,\n                           double* ap, lapack_int* ipiv );\nlapack_int LAPACKE_csptrf( int matrix_order, char uplo, lapack_int n,\n                           lapack_complex_float* ap, lapack_int* ipiv );\nlapack_int LAPACKE_zsptrf( int matrix_order, char uplo, lapack_int n,\n                           lapack_complex_double* ap, lapack_int* ipiv );\n\nlapack_int LAPACKE_ssptri( int matrix_order, char uplo, lapack_int n, float* ap,\n                           const lapack_int* ipiv );\nlapack_int LAPACKE_dsptri( int matrix_order, char uplo, lapack_int n,\n                           double* ap, const lapack_int* ipiv );\nlapack_int LAPACKE_csptri( int matrix_order, char uplo, lapack_int n,\n                           lapack_complex_float* ap, const lapack_int* ipiv );\nlapack_int LAPACKE_zsptri( int matrix_order, char uplo, lapack_int n,\n                           lapack_complex_double* ap, const lapack_int* ipiv );\n\nlapack_int LAPACKE_ssptrs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const float* ap,\n                           const lapack_int* ipiv, float* b, lapack_int ldb );\nlapack_int LAPACKE_dsptrs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const double* ap,\n                           const lapack_int* ipiv, double* b, lapack_int ldb );\nlapack_int LAPACKE_csptrs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_float* ap,\n                           const lapack_int* ipiv, lapack_complex_float* b,\n                           lapack_int ldb );\nlapack_int LAPACKE_zsptrs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_double* ap,\n                           const lapack_int* ipiv, lapack_complex_double* b,\n                           lapack_int ldb );\n\nlapack_int LAPACKE_sstebz( char range, char order, lapack_int n, float vl,\n                           float vu, lapack_int il, lapack_int iu, float abstol,\n                           const float* d, const float* e, lapack_int* m,\n                           lapack_int* nsplit, float* w, lapack_int* iblock,\n                           lapack_int* isplit );\nlapack_int LAPACKE_dstebz( char range, char order, lapack_int n, double vl,\n                           double vu, lapack_int il, lapack_int iu,\n                           double abstol, const double* d, const double* e,\n                           lapack_int* m, lapack_int* nsplit, double* w,\n                           lapack_int* iblock, lapack_int* isplit );\n\nlapack_int LAPACKE_sstedc( int matrix_order, char compz, lapack_int n, float* d,\n                           float* e, float* z, lapack_int ldz );\nlapack_int LAPACKE_dstedc( int matrix_order, char compz, lapack_int n,\n                           double* d, double* e, double* z, lapack_int ldz );\nlapack_int LAPACKE_cstedc( int matrix_order, char compz, lapack_int n, float* d,\n                           float* e, lapack_complex_float* z, lapack_int ldz );\nlapack_int LAPACKE_zstedc( int matrix_order, char compz, lapack_int n,\n                           double* d, double* e, lapack_complex_double* z,\n                           lapack_int ldz );\n\nlapack_int LAPACKE_sstegr( int matrix_order, char jobz, char range,\n                           lapack_int n, float* d, float* e, float vl, float vu,\n                           lapack_int il, lapack_int iu, float abstol,\n                           lapack_int* m, float* w, float* z, lapack_int ldz,\n                           lapack_int* isuppz );\nlapack_int LAPACKE_dstegr( int matrix_order, char jobz, char range,\n                           lapack_int n, double* d, double* e, double vl,\n                           double vu, lapack_int il, lapack_int iu,\n                           double abstol, lapack_int* m, double* w, double* z,\n                           lapack_int ldz, lapack_int* isuppz );\nlapack_int LAPACKE_cstegr( int matrix_order, char jobz, char range,\n                           lapack_int n, float* d, float* e, float vl, float vu,\n                           lapack_int il, lapack_int iu, float abstol,\n                           lapack_int* m, float* w, lapack_complex_float* z,\n                           lapack_int ldz, lapack_int* isuppz );\nlapack_int LAPACKE_zstegr( int matrix_order, char jobz, char range,\n                           lapack_int n, double* d, double* e, double vl,\n                           double vu, lapack_int il, lapack_int iu,\n                           double abstol, lapack_int* m, double* w,\n                           lapack_complex_double* z, lapack_int ldz,\n                           lapack_int* isuppz );\n\nlapack_int LAPACKE_sstein( int matrix_order, lapack_int n, const float* d,\n                           const float* e, lapack_int m, const float* w,\n                           const lapack_int* iblock, const lapack_int* isplit,\n                           float* z, lapack_int ldz, lapack_int* ifailv );\nlapack_int LAPACKE_dstein( int matrix_order, lapack_int n, const double* d,\n                           const double* e, lapack_int m, const double* w,\n                           const lapack_int* iblock, const lapack_int* isplit,\n                           double* z, lapack_int ldz, lapack_int* ifailv );\nlapack_int LAPACKE_cstein( int matrix_order, lapack_int n, const float* d,\n                           const float* e, lapack_int m, const float* w,\n                           const lapack_int* iblock, const lapack_int* isplit,\n                           lapack_complex_float* z, lapack_int ldz,\n                           lapack_int* ifailv );\nlapack_int LAPACKE_zstein( int matrix_order, lapack_int n, const double* d,\n                           const double* e, lapack_int m, const double* w,\n                           const lapack_int* iblock, const lapack_int* isplit,\n                           lapack_complex_double* z, lapack_int ldz,\n                           lapack_int* ifailv );\n\nlapack_int LAPACKE_sstemr( int matrix_order, char jobz, char range,\n                           lapack_int n, float* d, float* e, float vl, float vu,\n                           lapack_int il, lapack_int iu, lapack_int* m,\n                           float* w, float* z, lapack_int ldz, lapack_int nzc,\n                           lapack_int* isuppz, lapack_logical* tryrac );\nlapack_int LAPACKE_dstemr( int matrix_order, char jobz, char range,\n                           lapack_int n, double* d, double* e, double vl,\n                           double vu, lapack_int il, lapack_int iu,\n                           lapack_int* m, double* w, double* z, lapack_int ldz,\n                           lapack_int nzc, lapack_int* isuppz,\n                           lapack_logical* tryrac );\nlapack_int LAPACKE_cstemr( int matrix_order, char jobz, char range,\n                           lapack_int n, float* d, float* e, float vl, float vu,\n                           lapack_int il, lapack_int iu, lapack_int* m,\n                           float* w, lapack_complex_float* z, lapack_int ldz,\n                           lapack_int nzc, lapack_int* isuppz,\n                           lapack_logical* tryrac );\nlapack_int LAPACKE_zstemr( int matrix_order, char jobz, char range,\n                           lapack_int n, double* d, double* e, double vl,\n                           double vu, lapack_int il, lapack_int iu,\n                           lapack_int* m, double* w, lapack_complex_double* z,\n                           lapack_int ldz, lapack_int nzc, lapack_int* isuppz,\n                           lapack_logical* tryrac );\n\nlapack_int LAPACKE_ssteqr( int matrix_order, char compz, lapack_int n, float* d,\n                           float* e, float* z, lapack_int ldz );\nlapack_int LAPACKE_dsteqr( int matrix_order, char compz, lapack_int n,\n                           double* d, double* e, double* z, lapack_int ldz );\nlapack_int LAPACKE_csteqr( int matrix_order, char compz, lapack_int n, float* d,\n                           float* e, lapack_complex_float* z, lapack_int ldz );\nlapack_int LAPACKE_zsteqr( int matrix_order, char compz, lapack_int n,\n                           double* d, double* e, lapack_complex_double* z,\n                           lapack_int ldz );\n\nlapack_int LAPACKE_ssterf( lapack_int n, float* d, float* e );\nlapack_int LAPACKE_dsterf( lapack_int n, double* d, double* e );\n\nlapack_int LAPACKE_sstev( int matrix_order, char jobz, lapack_int n, float* d,\n                          float* e, float* z, lapack_int ldz );\nlapack_int LAPACKE_dstev( int matrix_order, char jobz, lapack_int n, double* d,\n                          double* e, double* z, lapack_int ldz );\n\nlapack_int LAPACKE_sstevd( int matrix_order, char jobz, lapack_int n, float* d,\n                           float* e, float* z, lapack_int ldz );\nlapack_int LAPACKE_dstevd( int matrix_order, char jobz, lapack_int n, double* d,\n                           double* e, double* z, lapack_int ldz );\n\nlapack_int LAPACKE_sstevr( int matrix_order, char jobz, char range,\n                           lapack_int n, float* d, float* e, float vl, float vu,\n                           lapack_int il, lapack_int iu, float abstol,\n                           lapack_int* m, float* w, float* z, lapack_int ldz,\n                           lapack_int* isuppz );\nlapack_int LAPACKE_dstevr( int matrix_order, char jobz, char range,\n                           lapack_int n, double* d, double* e, double vl,\n                           double vu, lapack_int il, lapack_int iu,\n                           double abstol, lapack_int* m, double* w, double* z,\n                           lapack_int ldz, lapack_int* isuppz );\n\nlapack_int LAPACKE_sstevx( int matrix_order, char jobz, char range,\n                           lapack_int n, float* d, float* e, float vl, float vu,\n                           lapack_int il, lapack_int iu, float abstol,\n                           lapack_int* m, float* w, float* z, lapack_int ldz,\n                           lapack_int* ifail );\nlapack_int LAPACKE_dstevx( int matrix_order, char jobz, char range,\n                           lapack_int n, double* d, double* e, double vl,\n                           double vu, lapack_int il, lapack_int iu,\n                           double abstol, lapack_int* m, double* w, double* z,\n                           lapack_int ldz, lapack_int* ifail );\n\nlapack_int LAPACKE_ssycon( int matrix_order, char uplo, lapack_int n,\n                           const float* a, lapack_int lda,\n                           const lapack_int* ipiv, float anorm, float* rcond );\nlapack_int LAPACKE_dsycon( int matrix_order, char uplo, lapack_int n,\n                           const double* a, lapack_int lda,\n                           const lapack_int* ipiv, double anorm,\n                           double* rcond );\nlapack_int LAPACKE_csycon( int matrix_order, char uplo, lapack_int n,\n                           const lapack_complex_float* a, lapack_int lda,\n                           const lapack_int* ipiv, float anorm, float* rcond );\nlapack_int LAPACKE_zsycon( int matrix_order, char uplo, lapack_int n,\n                           const lapack_complex_double* a, lapack_int lda,\n                           const lapack_int* ipiv, double anorm,\n                           double* rcond );\n\nlapack_int LAPACKE_ssyequb( int matrix_order, char uplo, lapack_int n,\n                            const float* a, lapack_int lda, float* s,\n                            float* scond, float* amax );\nlapack_int LAPACKE_dsyequb( int matrix_order, char uplo, lapack_int n,\n                            const double* a, lapack_int lda, double* s,\n                            double* scond, double* amax );\nlapack_int LAPACKE_csyequb( int matrix_order, char uplo, lapack_int n,\n                            const lapack_complex_float* a, lapack_int lda,\n                            float* s, float* scond, float* amax );\nlapack_int LAPACKE_zsyequb( int matrix_order, char uplo, lapack_int n,\n                            const lapack_complex_double* a, lapack_int lda,\n                            double* s, double* scond, double* amax );\n\nlapack_int LAPACKE_ssyev( int matrix_order, char jobz, char uplo, lapack_int n,\n                          float* a, lapack_int lda, float* w );\nlapack_int LAPACKE_dsyev( int matrix_order, char jobz, char uplo, lapack_int n,\n                          double* a, lapack_int lda, double* w );\n\nlapack_int LAPACKE_ssyevd( int matrix_order, char jobz, char uplo, lapack_int n,\n                           float* a, lapack_int lda, float* w );\nlapack_int LAPACKE_dsyevd( int matrix_order, char jobz, char uplo, lapack_int n,\n                           double* a, lapack_int lda, double* w );\n\nlapack_int LAPACKE_ssyevr( int matrix_order, char jobz, char range, char uplo,\n                           lapack_int n, float* a, lapack_int lda, float vl,\n                           float vu, lapack_int il, lapack_int iu, float abstol,\n                           lapack_int* m, float* w, float* z, lapack_int ldz,\n                           lapack_int* isuppz );\nlapack_int LAPACKE_dsyevr( int matrix_order, char jobz, char range, char uplo,\n                           lapack_int n, double* a, lapack_int lda, double vl,\n                           double vu, lapack_int il, lapack_int iu,\n                           double abstol, lapack_int* m, double* w, double* z,\n                           lapack_int ldz, lapack_int* isuppz );\n\nlapack_int LAPACKE_ssyevx( int matrix_order, char jobz, char range, char uplo,\n                           lapack_int n, float* a, lapack_int lda, float vl,\n                           float vu, lapack_int il, lapack_int iu, float abstol,\n                           lapack_int* m, float* w, float* z, lapack_int ldz,\n                           lapack_int* ifail );\nlapack_int LAPACKE_dsyevx( int matrix_order, char jobz, char range, char uplo,\n                           lapack_int n, double* a, lapack_int lda, double vl,\n                           double vu, lapack_int il, lapack_int iu,\n                           double abstol, lapack_int* m, double* w, double* z,\n                           lapack_int ldz, lapack_int* ifail );\n\nlapack_int LAPACKE_ssygst( int matrix_order, lapack_int itype, char uplo,\n                           lapack_int n, float* a, lapack_int lda,\n                           const float* b, lapack_int ldb );\nlapack_int LAPACKE_dsygst( int matrix_order, lapack_int itype, char uplo,\n                           lapack_int n, double* a, lapack_int lda,\n                           const double* b, lapack_int ldb );\n\nlapack_int LAPACKE_ssygv( int matrix_order, lapack_int itype, char jobz,\n                          char uplo, lapack_int n, float* a, lapack_int lda,\n                          float* b, lapack_int ldb, float* w );\nlapack_int LAPACKE_dsygv( int matrix_order, lapack_int itype, char jobz,\n                          char uplo, lapack_int n, double* a, lapack_int lda,\n                          double* b, lapack_int ldb, double* w );\n\nlapack_int LAPACKE_ssygvd( int matrix_order, lapack_int itype, char jobz,\n                           char uplo, lapack_int n, float* a, lapack_int lda,\n                           float* b, lapack_int ldb, float* w );\nlapack_int LAPACKE_dsygvd( int matrix_order, lapack_int itype, char jobz,\n                           char uplo, lapack_int n, double* a, lapack_int lda,\n                           double* b, lapack_int ldb, double* w );\n\nlapack_int LAPACKE_ssygvx( int matrix_order, lapack_int itype, char jobz,\n                           char range, char uplo, lapack_int n, float* a,\n                           lapack_int lda, float* b, lapack_int ldb, float vl,\n                           float vu, lapack_int il, lapack_int iu, float abstol,\n                           lapack_int* m, float* w, float* z, lapack_int ldz,\n                           lapack_int* ifail );\nlapack_int LAPACKE_dsygvx( int matrix_order, lapack_int itype, char jobz,\n                           char range, char uplo, lapack_int n, double* a,\n                           lapack_int lda, double* b, lapack_int ldb, double vl,\n                           double vu, lapack_int il, lapack_int iu,\n                           double abstol, lapack_int* m, double* w, double* z,\n                           lapack_int ldz, lapack_int* ifail );\n\nlapack_int LAPACKE_ssyrfs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const float* a, lapack_int lda,\n                           const float* af, lapack_int ldaf,\n                           const lapack_int* ipiv, const float* b,\n                           lapack_int ldb, float* x, lapack_int ldx,\n                           float* ferr, float* berr );\nlapack_int LAPACKE_dsyrfs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const double* a, lapack_int lda,\n                           const double* af, lapack_int ldaf,\n                           const lapack_int* ipiv, const double* b,\n                           lapack_int ldb, double* x, lapack_int ldx,\n                           double* ferr, double* berr );\nlapack_int LAPACKE_csyrfs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_float* a,\n                           lapack_int lda, const lapack_complex_float* af,\n                           lapack_int ldaf, const lapack_int* ipiv,\n                           const lapack_complex_float* b, lapack_int ldb,\n                           lapack_complex_float* x, lapack_int ldx, float* ferr,\n                           float* berr );\nlapack_int LAPACKE_zsyrfs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_double* a,\n                           lapack_int lda, const lapack_complex_double* af,\n                           lapack_int ldaf, const lapack_int* ipiv,\n                           const lapack_complex_double* b, lapack_int ldb,\n                           lapack_complex_double* x, lapack_int ldx,\n                           double* ferr, double* berr );\n\nlapack_int LAPACKE_ssyrfsx( int matrix_order, char uplo, char equed,\n                            lapack_int n, lapack_int nrhs, const float* a,\n                            lapack_int lda, const float* af, lapack_int ldaf,\n                            const lapack_int* ipiv, const float* s,\n                            const float* b, lapack_int ldb, float* x,\n                            lapack_int ldx, float* rcond, float* berr,\n                            lapack_int n_err_bnds, float* err_bnds_norm,\n                            float* err_bnds_comp, lapack_int nparams,\n                            float* params );\nlapack_int LAPACKE_dsyrfsx( int matrix_order, char uplo, char equed,\n                            lapack_int n, lapack_int nrhs, const double* a,\n                            lapack_int lda, const double* af, lapack_int ldaf,\n                            const lapack_int* ipiv, const double* s,\n                            const double* b, lapack_int ldb, double* x,\n                            lapack_int ldx, double* rcond, double* berr,\n                            lapack_int n_err_bnds, double* err_bnds_norm,\n                            double* err_bnds_comp, lapack_int nparams,\n                            double* params );\nlapack_int LAPACKE_csyrfsx( int matrix_order, char uplo, char equed,\n                            lapack_int n, lapack_int nrhs,\n                            const lapack_complex_float* a, lapack_int lda,\n                            const lapack_complex_float* af, lapack_int ldaf,\n                            const lapack_int* ipiv, const float* s,\n                            const lapack_complex_float* b, lapack_int ldb,\n                            lapack_complex_float* x, lapack_int ldx,\n                            float* rcond, float* berr, lapack_int n_err_bnds,\n                            float* err_bnds_norm, float* err_bnds_comp,\n                            lapack_int nparams, float* params );\nlapack_int LAPACKE_zsyrfsx( int matrix_order, char uplo, char equed,\n                            lapack_int n, lapack_int nrhs,\n                            const lapack_complex_double* a, lapack_int lda,\n                            const lapack_complex_double* af, lapack_int ldaf,\n                            const lapack_int* ipiv, const double* s,\n                            const lapack_complex_double* b, lapack_int ldb,\n                            lapack_complex_double* x, lapack_int ldx,\n                            double* rcond, double* berr, lapack_int n_err_bnds,\n                            double* err_bnds_norm, double* err_bnds_comp,\n                            lapack_int nparams, double* params );\n\nlapack_int LAPACKE_ssysv( int matrix_order, char uplo, lapack_int n,\n                          lapack_int nrhs, float* a, lapack_int lda,\n                          lapack_int* ipiv, float* b, lapack_int ldb );\nlapack_int LAPACKE_dsysv( int matrix_order, char uplo, lapack_int n,\n                          lapack_int nrhs, double* a, lapack_int lda,\n                          lapack_int* ipiv, double* b, lapack_int ldb );\nlapack_int LAPACKE_csysv( int matrix_order, char uplo, lapack_int n,\n                          lapack_int nrhs, lapack_complex_float* a,\n                          lapack_int lda, lapack_int* ipiv,\n                          lapack_complex_float* b, lapack_int ldb );\nlapack_int LAPACKE_zsysv( int matrix_order, char uplo, lapack_int n,\n                          lapack_int nrhs, lapack_complex_double* a,\n                          lapack_int lda, lapack_int* ipiv,\n                          lapack_complex_double* b, lapack_int ldb );\n\nlapack_int LAPACKE_ssysvx( int matrix_order, char fact, char uplo, lapack_int n,\n                           lapack_int nrhs, const float* a, lapack_int lda,\n                           float* af, lapack_int ldaf, lapack_int* ipiv,\n                           const float* b, lapack_int ldb, float* x,\n                           lapack_int ldx, float* rcond, float* ferr,\n                           float* berr );\nlapack_int LAPACKE_dsysvx( int matrix_order, char fact, char uplo, lapack_int n,\n                           lapack_int nrhs, const double* a, lapack_int lda,\n                           double* af, lapack_int ldaf, lapack_int* ipiv,\n                           const double* b, lapack_int ldb, double* x,\n                           lapack_int ldx, double* rcond, double* ferr,\n                           double* berr );\nlapack_int LAPACKE_csysvx( int matrix_order, char fact, char uplo, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_float* a,\n                           lapack_int lda, lapack_complex_float* af,\n                           lapack_int ldaf, lapack_int* ipiv,\n                           const lapack_complex_float* b, lapack_int ldb,\n                           lapack_complex_float* x, lapack_int ldx,\n                           float* rcond, float* ferr, float* berr );\nlapack_int LAPACKE_zsysvx( int matrix_order, char fact, char uplo, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_double* a,\n                           lapack_int lda, lapack_complex_double* af,\n                           lapack_int ldaf, lapack_int* ipiv,\n                           const lapack_complex_double* b, lapack_int ldb,\n                           lapack_complex_double* x, lapack_int ldx,\n                           double* rcond, double* ferr, double* berr );\n\nlapack_int LAPACKE_ssysvxx( int matrix_order, char fact, char uplo,\n                            lapack_int n, lapack_int nrhs, float* a,\n                            lapack_int lda, float* af, lapack_int ldaf,\n                            lapack_int* ipiv, char* equed, float* s, float* b,\n                            lapack_int ldb, float* x, lapack_int ldx,\n                            float* rcond, float* rpvgrw, float* berr,\n                            lapack_int n_err_bnds, float* err_bnds_norm,\n                            float* err_bnds_comp, lapack_int nparams,\n                            float* params );\nlapack_int LAPACKE_dsysvxx( int matrix_order, char fact, char uplo,\n                            lapack_int n, lapack_int nrhs, double* a,\n                            lapack_int lda, double* af, lapack_int ldaf,\n                            lapack_int* ipiv, char* equed, double* s, double* b,\n                            lapack_int ldb, double* x, lapack_int ldx,\n                            double* rcond, double* rpvgrw, double* berr,\n                            lapack_int n_err_bnds, double* err_bnds_norm,\n                            double* err_bnds_comp, lapack_int nparams,\n                            double* params );\nlapack_int LAPACKE_csysvxx( int matrix_order, char fact, char uplo,\n                            lapack_int n, lapack_int nrhs,\n                            lapack_complex_float* a, lapack_int lda,\n                            lapack_complex_float* af, lapack_int ldaf,\n                            lapack_int* ipiv, char* equed, float* s,\n                            lapack_complex_float* b, lapack_int ldb,\n                            lapack_complex_float* x, lapack_int ldx,\n                            float* rcond, float* rpvgrw, float* berr,\n                            lapack_int n_err_bnds, float* err_bnds_norm,\n                            float* err_bnds_comp, lapack_int nparams,\n                            float* params );\nlapack_int LAPACKE_zsysvxx( int matrix_order, char fact, char uplo,\n                            lapack_int n, lapack_int nrhs,\n                            lapack_complex_double* a, lapack_int lda,\n                            lapack_complex_double* af, lapack_int ldaf,\n                            lapack_int* ipiv, char* equed, double* s,\n                            lapack_complex_double* b, lapack_int ldb,\n                            lapack_complex_double* x, lapack_int ldx,\n                            double* rcond, double* rpvgrw, double* berr,\n                            lapack_int n_err_bnds, double* err_bnds_norm,\n                            double* err_bnds_comp, lapack_int nparams,\n                            double* params );\n\nlapack_int LAPACKE_ssytrd( int matrix_order, char uplo, lapack_int n, float* a,\n                           lapack_int lda, float* d, float* e, float* tau );\nlapack_int LAPACKE_dsytrd( int matrix_order, char uplo, lapack_int n, double* a,\n                           lapack_int lda, double* d, double* e, double* tau );\n\nlapack_int LAPACKE_ssytrf( int matrix_order, char uplo, lapack_int n, float* a,\n                           lapack_int lda, lapack_int* ipiv );\nlapack_int LAPACKE_dsytrf( int matrix_order, char uplo, lapack_int n, double* a,\n                           lapack_int lda, lapack_int* ipiv );\nlapack_int LAPACKE_csytrf( int matrix_order, char uplo, lapack_int n,\n                           lapack_complex_float* a, lapack_int lda,\n                           lapack_int* ipiv );\nlapack_int LAPACKE_zsytrf( int matrix_order, char uplo, lapack_int n,\n                           lapack_complex_double* a, lapack_int lda,\n                           lapack_int* ipiv );\n\nlapack_int LAPACKE_ssytri( int matrix_order, char uplo, lapack_int n, float* a,\n                           lapack_int lda, const lapack_int* ipiv );\nlapack_int LAPACKE_dsytri( int matrix_order, char uplo, lapack_int n, double* a,\n                           lapack_int lda, const lapack_int* ipiv );\nlapack_int LAPACKE_csytri( int matrix_order, char uplo, lapack_int n,\n                           lapack_complex_float* a, lapack_int lda,\n                           const lapack_int* ipiv );\nlapack_int LAPACKE_zsytri( int matrix_order, char uplo, lapack_int n,\n                           lapack_complex_double* a, lapack_int lda,\n                           const lapack_int* ipiv );\n\nlapack_int LAPACKE_ssytrs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const float* a, lapack_int lda,\n                           const lapack_int* ipiv, float* b, lapack_int ldb );\nlapack_int LAPACKE_dsytrs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const double* a, lapack_int lda,\n                           const lapack_int* ipiv, double* b, lapack_int ldb );\nlapack_int LAPACKE_csytrs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_float* a,\n                           lapack_int lda, const lapack_int* ipiv,\n                           lapack_complex_float* b, lapack_int ldb );\nlapack_int LAPACKE_zsytrs( int matrix_order, char uplo, lapack_int n,\n                           lapack_int nrhs, const lapack_complex_double* a,\n                           lapack_int lda, const lapack_int* ipiv,\n                           lapack_complex_double* b, lapack_int ldb );\n\nlapack_int LAPACKE_stbcon( int matrix_order, char norm, char uplo, char diag,\n                           lapack_int n, lapack_int kd, const float* ab,\n                           lapack_int ldab, float* rcond );\nlapack_int LAPACKE_dtbcon( int matrix_order, char norm, char uplo, char diag,\n                           lapack_int n, lapack_int kd, const double* ab,\n                           lapack_int ldab, double* rcond );\nlapack_int LAPACKE_ctbcon( int matrix_order, char norm, char uplo, char diag,\n                           lapack_int n, lapack_int kd,\n                           const lapack_complex_float* ab, lapack_int ldab,\n                           float* rcond );\nlapack_int LAPACKE_ztbcon( int matrix_order, char norm, char uplo, char diag,\n                           lapack_int n, lapack_int kd,\n                           const lapack_complex_double* ab, lapack_int ldab,\n                           double* rcond );\n\nlapack_int LAPACKE_stbrfs( int matrix_order, char uplo, char trans, char diag,\n                           lapack_int n, lapack_int kd, lapack_int nrhs,\n                           const float* ab, lapack_int ldab, const float* b,\n                           lapack_int ldb, const float* x, lapack_int ldx,\n                           float* ferr, float* berr );\nlapack_int LAPACKE_dtbrfs( int matrix_order, char uplo, char trans, char diag,\n                           lapack_int n, lapack_int kd, lapack_int nrhs,\n                           const double* ab, lapack_int ldab, const double* b,\n                           lapack_int ldb, const double* x, lapack_int ldx,\n                           double* ferr, double* berr );\nlapack_int LAPACKE_ctbrfs( int matrix_order, char uplo, char trans, char diag,\n                           lapack_int n, lapack_int kd, lapack_int nrhs,\n                           const lapack_complex_float* ab, lapack_int ldab,\n                           const lapack_complex_float* b, lapack_int ldb,\n                           const lapack_complex_float* x, lapack_int ldx,\n                           float* ferr, float* berr );\nlapack_int LAPACKE_ztbrfs( int matrix_order, char uplo, char trans, char diag,\n                           lapack_int n, lapack_int kd, lapack_int nrhs,\n                           const lapack_complex_double* ab, lapack_int ldab,\n                           const lapack_complex_double* b, lapack_int ldb,\n                           const lapack_complex_double* x, lapack_int ldx,\n                           double* ferr, double* berr );\n\nlapack_int LAPACKE_stbtrs( int matrix_order, char uplo, char trans, char diag,\n                           lapack_int n, lapack_int kd, lapack_int nrhs,\n                           const float* ab, lapack_int ldab, float* b,\n                           lapack_int ldb );\nlapack_int LAPACKE_dtbtrs( int matrix_order, char uplo, char trans, char diag,\n                           lapack_int n, lapack_int kd, lapack_int nrhs,\n                           const double* ab, lapack_int ldab, double* b,\n                           lapack_int ldb );\nlapack_int LAPACKE_ctbtrs( int matrix_order, char uplo, char trans, char diag,\n                           lapack_int n, lapack_int kd, lapack_int nrhs,\n                           const lapack_complex_float* ab, lapack_int ldab,\n                           lapack_complex_float* b, lapack_int ldb );\nlapack_int LAPACKE_ztbtrs( int matrix_order, char uplo, char trans, char diag,\n                           lapack_int n, lapack_int kd, lapack_int nrhs,\n                           const lapack_complex_double* ab, lapack_int ldab,\n                           lapack_complex_double* b, lapack_int ldb );\n\nlapack_int LAPACKE_stfsm( int matrix_order, char transr, char side, char uplo,\n                          char trans, char diag, lapack_int m, lapack_int n,\n                          float alpha, const float* a, float* b,\n                          lapack_int ldb );\nlapack_int LAPACKE_dtfsm( int matrix_order, char transr, char side, char uplo,\n                          char trans, char diag, lapack_int m, lapack_int n,\n                          double alpha, const double* a, double* b,\n                          lapack_int ldb );\nlapack_int LAPACKE_ctfsm( int matrix_order, char transr, char side, char uplo,\n                          char trans, char diag, lapack_int m, lapack_int n,\n                          lapack_complex_float alpha,\n                          const lapack_complex_float* a,\n                          lapack_complex_float* b, lapack_int ldb );\nlapack_int LAPACKE_ztfsm( int matrix_order, char transr, char side, char uplo,\n                          char trans, char diag, lapack_int m, lapack_int n,\n                          lapack_complex_double alpha,\n                          const lapack_complex_double* a,\n                          lapack_complex_double* b, lapack_int ldb );\n\nlapack_int LAPACKE_stftri( int matrix_order, char transr, char uplo, char diag,\n                           lapack_int n, float* a );\nlapack_int LAPACKE_dtftri( int matrix_order, char transr, char uplo, char diag,\n                           lapack_int n, double* a );\nlapack_int LAPACKE_ctftri( int matrix_order, char transr, char uplo, char diag,\n                           lapack_int n, lapack_complex_float* a );\nlapack_int LAPACKE_ztftri( int matrix_order, char transr, char uplo, char diag,\n                           lapack_int n, lapack_complex_double* a );\n\nlapack_int LAPACKE_stfttp( int matrix_order, char transr, char uplo,\n                           lapack_int n, const float* arf, float* ap );\nlapack_int LAPACKE_dtfttp( int matrix_order, char transr, char uplo,\n                           lapack_int n, const double* arf, double* ap );\nlapack_int LAPACKE_ctfttp( int matrix_order, char transr, char uplo,\n                           lapack_int n, const lapack_complex_float* arf,\n                           lapack_complex_float* ap );\nlapack_int LAPACKE_ztfttp( int matrix_order, char transr, char uplo,\n                           lapack_int n, const lapack_complex_double* arf,\n                           lapack_complex_double* ap );\n\nlapack_int LAPACKE_stfttr( int matrix_order, char transr, char uplo,\n                           lapack_int n, const float* arf, float* a,\n                           lapack_int lda );\nlapack_int LAPACKE_dtfttr( int matrix_order, char transr, char uplo,\n                           lapack_int n, const double* arf, double* a,\n                           lapack_int lda );\nlapack_int LAPACKE_ctfttr( int matrix_order, char transr, char uplo,\n                           lapack_int n, const lapack_complex_float* arf,\n                           lapack_complex_float* a, lapack_int lda );\nlapack_int LAPACKE_ztfttr( int matrix_order, char transr, char uplo,\n                           lapack_int n, const lapack_complex_double* arf,\n                           lapack_complex_double* a, lapack_int lda );\n\nlapack_int LAPACKE_stgevc( int matrix_order, char side, char howmny,\n                           const lapack_logical* select, lapack_int n,\n                           const float* s, lapack_int lds, const float* p,\n                           lapack_int ldp, float* vl, lapack_int ldvl,\n                           float* vr, lapack_int ldvr, lapack_int mm,\n                           lapack_int* m );\nlapack_int LAPACKE_dtgevc( int matrix_order, char side, char howmny,\n                           const lapack_logical* select, lapack_int n,\n                           const double* s, lapack_int lds, const double* p,\n                           lapack_int ldp, double* vl, lapack_int ldvl,\n                           double* vr, lapack_int ldvr, lapack_int mm,\n                           lapack_int* m );\nlapack_int LAPACKE_ctgevc( int matrix_order, char side, char howmny,\n                           const lapack_logical* select, lapack_int n,\n                           const lapack_complex_float* s, lapack_int lds,\n                           const lapack_complex_float* p, lapack_int ldp,\n                           lapack_complex_float* vl, lapack_int ldvl,\n                           lapack_complex_float* vr, lapack_int ldvr,\n                           lapack_int mm, lapack_int* m );\nlapack_int LAPACKE_ztgevc( int matrix_order, char side, char howmny,\n                           const lapack_logical* select, lapack_int n,\n                           const lapack_complex_double* s, lapack_int lds,\n                           const lapack_complex_double* p, lapack_int ldp,\n                           lapack_complex_double* vl, lapack_int ldvl,\n                           lapack_complex_double* vr, lapack_int ldvr,\n                           lapack_int mm, lapack_int* m );\n\nlapack_int LAPACKE_stgexc( int matrix_order, lapack_logical wantq,\n                           lapack_logical wantz, lapack_int n, float* a,\n                           lapack_int lda, float* b, lapack_int ldb, float* q,\n                           lapack_int ldq, float* z, lapack_int ldz,\n                           lapack_int* ifst, lapack_int* ilst );\nlapack_int LAPACKE_dtgexc( int matrix_order, lapack_logical wantq,\n                           lapack_logical wantz, lapack_int n, double* a,\n                           lapack_int lda, double* b, lapack_int ldb, double* q,\n                           lapack_int ldq, double* z, lapack_int ldz,\n                           lapack_int* ifst, lapack_int* ilst );\nlapack_int LAPACKE_ctgexc( int matrix_order, lapack_logical wantq,\n                           lapack_logical wantz, lapack_int n,\n                           lapack_complex_float* a, lapack_int lda,\n                           lapack_complex_float* b, lapack_int ldb,\n                           lapack_complex_float* q, lapack_int ldq,\n                           lapack_complex_float* z, lapack_int ldz,\n                           lapack_int ifst, lapack_int ilst );\nlapack_int LAPACKE_ztgexc( int matrix_order, lapack_logical wantq,\n                           lapack_logical wantz, lapack_int n,\n                           lapack_complex_double* a, lapack_int lda,\n                           lapack_complex_double* b, lapack_int ldb,\n                           lapack_complex_double* q, lapack_int ldq,\n                           lapack_complex_double* z, lapack_int ldz,\n                           lapack_int ifst, lapack_int ilst );\n\nlapack_int LAPACKE_stgsen( int matrix_order, lapack_int ijob,\n                           lapack_logical wantq, lapack_logical wantz,\n                           const lapack_logical* select, lapack_int n, float* a,\n                           lapack_int lda, float* b, lapack_int ldb,\n                           float* alphar, float* alphai, float* beta, float* q,\n                           lapack_int ldq, float* z, lapack_int ldz,\n                           lapack_int* m, float* pl, float* pr, float* dif );\nlapack_int LAPACKE_dtgsen( int matrix_order, lapack_int ijob,\n                           lapack_logical wantq, lapack_logical wantz,\n                           const lapack_logical* select, lapack_int n,\n                           double* a, lapack_int lda, double* b, lapack_int ldb,\n                           double* alphar, double* alphai, double* beta,\n                           double* q, lapack_int ldq, double* z, lapack_int ldz,\n                           lapack_int* m, double* pl, double* pr, double* dif );\nlapack_int LAPACKE_ctgsen( int matrix_order, lapack_int ijob,\n                           lapack_logical wantq, lapack_logical wantz,\n                           const lapack_logical* select, lapack_int n,\n                           lapack_complex_float* a, lapack_int lda,\n                           lapack_complex_float* b, lapack_int ldb,\n                           lapack_complex_float* alpha,\n                           lapack_complex_float* beta, lapack_complex_float* q,\n                           lapack_int ldq, lapack_complex_float* z,\n                           lapack_int ldz, lapack_int* m, float* pl, float* pr,\n                           float* dif );\nlapack_int LAPACKE_ztgsen( int matrix_order, lapack_int ijob,\n                           lapack_logical wantq, lapack_logical wantz,\n                           const lapack_logical* select, lapack_int n,\n                           lapack_complex_double* a, lapack_int lda,\n                           lapack_complex_double* b, lapack_int ldb,\n                           lapack_complex_double* alpha,\n                           lapack_complex_double* beta,\n                           lapack_complex_double* q, lapack_int ldq,\n                           lapack_complex_double* z, lapack_int ldz,\n                           lapack_int* m, double* pl, double* pr, double* dif );\n\nlapack_int LAPACKE_stgsja( int matrix_order, char jobu, char jobv, char jobq,\n                           lapack_int m, lapack_int p, lapack_int n,\n                           lapack_int k, lapack_int l, float* a, lapack_int lda,\n                           float* b, lapack_int ldb, float tola, float tolb,\n                           float* alpha, float* beta, float* u, lapack_int ldu,\n                           float* v, lapack_int ldv, float* q, lapack_int ldq,\n                           lapack_int* ncycle );\nlapack_int LAPACKE_dtgsja( int matrix_order, char jobu, char jobv, char jobq,\n                           lapack_int m, lapack_int p, lapack_int n,\n                           lapack_int k, lapack_int l, double* a,\n                           lapack_int lda, double* b, lapack_int ldb,\n                           double tola, double tolb, double* alpha,\n                           double* beta, double* u, lapack_int ldu, double* v,\n                           lapack_int ldv, double* q, lapack_int ldq,\n                           lapack_int* ncycle );\nlapack_int LAPACKE_ctgsja( int matrix_order, char jobu, char jobv, char jobq,\n                           lapack_int m, lapack_int p, lapack_int n,\n                           lapack_int k, lapack_int l, lapack_complex_float* a,\n                           lapack_int lda, lapack_complex_float* b,\n                           lapack_int ldb, float tola, float tolb, float* alpha,\n                           float* beta, lapack_complex_float* u, lapack_int ldu,\n                           lapack_complex_float* v, lapack_int ldv,\n                           lapack_complex_float* q, lapack_int ldq,\n                           lapack_int* ncycle );\nlapack_int LAPACKE_ztgsja( int matrix_order, char jobu, char jobv, char jobq,\n                           lapack_int m, lapack_int p, lapack_int n,\n                           lapack_int k, lapack_int l, lapack_complex_double* a,\n                           lapack_int lda, lapack_complex_double* b,\n                           lapack_int ldb, double tola, double tolb,\n                           double* alpha, double* beta,\n                           lapack_complex_double* u, lapack_int ldu,\n                           lapack_complex_double* v, lapack_int ldv,\n                           lapack_complex_double* q, lapack_int ldq,\n                           lapack_int* ncycle );\n\nlapack_int LAPACKE_stgsna( int matrix_order, char job, char howmny,\n                           const lapack_logical* select, lapack_int n,\n                           const float* a, lapack_int lda, const float* b,\n                           lapack_int ldb, const float* vl, lapack_int ldvl,\n                           const float* vr, lapack_int ldvr, float* s,\n                           float* dif, lapack_int mm, lapack_int* m );\nlapack_int LAPACKE_dtgsna( int matrix_order, char job, char howmny,\n                           const lapack_logical* select, lapack_int n,\n                           const double* a, lapack_int lda, const double* b,\n                           lapack_int ldb, const double* vl, lapack_int ldvl,\n                           const double* vr, lapack_int ldvr, double* s,\n                           double* dif, lapack_int mm, lapack_int* m );\nlapack_int LAPACKE_ctgsna( int matrix_order, char job, char howmny,\n                           const lapack_logical* select, lapack_int n,\n                           const lapack_complex_float* a, lapack_int lda,\n                           const lapack_complex_float* b, lapack_int ldb,\n                           const lapack_complex_float* vl, lapack_int ldvl,\n                           const lapack_complex_float* vr, lapack_int ldvr,\n                           float* s, float* dif, lapack_int mm, lapack_int* m );\nlapack_int LAPACKE_ztgsna( int matrix_order, char job, char howmny,\n                           const lapack_logical* select, lapack_int n,\n                           const lapack_complex_double* a, lapack_int lda,\n                           const lapack_complex_double* b, lapack_int ldb,\n                           const lapack_complex_double* vl, lapack_int ldvl,\n                           const lapack_complex_double* vr, lapack_int ldvr,\n                           double* s, double* dif, lapack_int mm,\n                           lapack_int* m );\n\nlapack_int LAPACKE_stgsyl( int matrix_order, char trans, lapack_int ijob,\n                           lapack_int m, lapack_int n, const float* a,\n                           lapack_int lda, const float* b, lapack_int ldb,\n                           float* c, lapack_int ldc, const float* d,\n                           lapack_int ldd, const float* e, lapack_int lde,\n                           float* f, lapack_int ldf, float* scale, float* dif );\nlapack_int LAPACKE_dtgsyl( int matrix_order, char trans, lapack_int ijob,\n                           lapack_int m, lapack_int n, const double* a,\n                           lapack_int lda, const double* b, lapack_int ldb,\n                           double* c, lapack_int ldc, const double* d,\n                           lapack_int ldd, const double* e, lapack_int lde,\n                           double* f, lapack_int ldf, double* scale,\n                           double* dif );\nlapack_int LAPACKE_ctgsyl( int matrix_order, char trans, lapack_int ijob,\n                           lapack_int m, lapack_int n,\n                           const lapack_complex_float* a, lapack_int lda,\n                           const lapack_complex_float* b, lapack_int ldb,\n                           lapack_complex_float* c, lapack_int ldc,\n                           const lapack_complex_float* d, lapack_int ldd,\n                           const lapack_complex_float* e, lapack_int lde,\n                           lapack_complex_float* f, lapack_int ldf,\n                           float* scale, float* dif );\nlapack_int LAPACKE_ztgsyl( int matrix_order, char trans, lapack_int ijob,\n                           lapack_int m, lapack_int n,\n                           const lapack_complex_double* a, lapack_int lda,\n                           const lapack_complex_double* b, lapack_int ldb,\n                           lapack_complex_double* c, lapack_int ldc,\n                           const lapack_complex_double* d, lapack_int ldd,\n                           const lapack_complex_double* e, lapack_int lde,\n                           lapack_complex_double* f, lapack_int ldf,\n                           double* scale, double* dif );\n\nlapack_int LAPACKE_stpcon( int matrix_order, char norm, char uplo, char diag,\n                           lapack_int n, const float* ap, float* rcond );\nlapack_int LAPACKE_dtpcon( int matrix_order, char norm, char uplo, char diag,\n                           lapack_int n, const double* ap, double* rcond );\nlapack_int LAPACKE_ctpcon( int matrix_order, char norm, char uplo, char diag,\n                           lapack_int n, const lapack_complex_float* ap,\n                           float* rcond );\nlapack_int LAPACKE_ztpcon( int matrix_order, char norm, char uplo, char diag,\n                           lapack_int n, const lapack_complex_double* ap,\n                           double* rcond );\n\nlapack_int LAPACKE_stprfs( int matrix_order, char uplo, char trans, char diag,\n                           lapack_int n, lapack_int nrhs, const float* ap,\n                           const float* b, lapack_int ldb, const float* x,\n                           lapack_int ldx, float* ferr, float* berr );\nlapack_int LAPACKE_dtprfs( int matrix_order, char uplo, char trans, char diag,\n                           lapack_int n, lapack_int nrhs, const double* ap,\n                           const double* b, lapack_int ldb, const double* x,\n                           lapack_int ldx, double* ferr, double* berr );\nlapack_int LAPACKE_ctprfs( int matrix_order, char uplo, char trans, char diag,\n                           lapack_int n, lapack_int nrhs,\n                           const lapack_complex_float* ap,\n                           const lapack_complex_float* b, lapack_int ldb,\n                           const lapack_complex_float* x, lapack_int ldx,\n                           float* ferr, float* berr );\nlapack_int LAPACKE_ztprfs( int matrix_order, char uplo, char trans, char diag,\n                           lapack_int n, lapack_int nrhs,\n                           const lapack_complex_double* ap,\n                           const lapack_complex_double* b, lapack_int ldb,\n                           const lapack_complex_double* x, lapack_int ldx,\n                           double* ferr, double* berr );\n\nlapack_int LAPACKE_stptri( int matrix_order, char uplo, char diag, lapack_int n,\n                           float* ap );\nlapack_int LAPACKE_dtptri( int matrix_order, char uplo, char diag, lapack_int n,\n                           double* ap );\nlapack_int LAPACKE_ctptri( int matrix_order, char uplo, char diag, lapack_int n,\n                           lapack_complex_float* ap );\nlapack_int LAPACKE_ztptri( int matrix_order, char uplo, char diag, lapack_int n,\n                           lapack_complex_double* ap );\n\nlapack_int LAPACKE_stptrs( int matrix_order, char uplo, char trans, char diag,\n                           lapack_int n, lapack_int nrhs, const float* ap,\n                           float* b, lapack_int ldb );\nlapack_int LAPACKE_dtptrs( int matrix_order, char uplo, char trans, char diag,\n                           lapack_int n, lapack_int nrhs, const double* ap,\n                           double* b, lapack_int ldb );\nlapack_int LAPACKE_ctptrs( int matrix_order, char uplo, char trans, char diag,\n                           lapack_int n, lapack_int nrhs,\n                           const lapack_complex_float* ap,\n                           lapack_complex_float* b, lapack_int ldb );\nlapack_int LAPACKE_ztptrs( int matrix_order, char uplo, char trans, char diag,\n                           lapack_int n, lapack_int nrhs,\n                           const lapack_complex_double* ap,\n                           lapack_complex_double* b, lapack_int ldb );\n\nlapack_int LAPACKE_stpttf( int matrix_order, char transr, char uplo,\n                           lapack_int n, const float* ap, float* arf );\nlapack_int LAPACKE_dtpttf( int matrix_order, char transr, char uplo,\n                           lapack_int n, const double* ap, double* arf );\nlapack_int LAPACKE_ctpttf( int matrix_order, char transr, char uplo,\n                           lapack_int n, const lapack_complex_float* ap,\n                           lapack_complex_float* arf );\nlapack_int LAPACKE_ztpttf( int matrix_order, char transr, char uplo,\n                           lapack_int n, const lapack_complex_double* ap,\n                           lapack_complex_double* arf );\n\nlapack_int LAPACKE_stpttr( int matrix_order, char uplo, lapack_int n,\n                           const float* ap, float* a, lapack_int lda );\nlapack_int LAPACKE_dtpttr( int matrix_order, char uplo, lapack_int n,\n                           const double* ap, double* a, lapack_int lda );\nlapack_int LAPACKE_ctpttr( int matrix_order, char uplo, lapack_int n,\n                           const lapack_complex_float* ap,\n                           lapack_complex_float* a, lapack_int lda );\nlapack_int LAPACKE_ztpttr( int matrix_order, char uplo, lapack_int n,\n                           const lapack_complex_double* ap,\n                           lapack_complex_double* a, lapack_int lda );\n\nlapack_int LAPACKE_strcon( int matrix_order, char norm, char uplo, char diag,\n                           lapack_int n, const float* a, lapack_int lda,\n                           float* rcond );\nlapack_int LAPACKE_dtrcon( int matrix_order, char norm, char uplo, char diag,\n                           lapack_int n, const double* a, lapack_int lda,\n                           double* rcond );\nlapack_int LAPACKE_ctrcon( int matrix_order, char norm, char uplo, char diag,\n                           lapack_int n, const lapack_complex_float* a,\n                           lapack_int lda, float* rcond );\nlapack_int LAPACKE_ztrcon( int matrix_order, char norm, char uplo, char diag,\n                           lapack_int n, const lapack_complex_double* a,\n                           lapack_int lda, double* rcond );\n\nlapack_int LAPACKE_strevc( int matrix_order, char side, char howmny,\n                           lapack_logical* select, lapack_int n, const float* t,\n                           lapack_int ldt, float* vl, lapack_int ldvl,\n                           float* vr, lapack_int ldvr, lapack_int mm,\n                           lapack_int* m );\nlapack_int LAPACKE_dtrevc( int matrix_order, char side, char howmny,\n                           lapack_logical* select, lapack_int n,\n                           const double* t, lapack_int ldt, double* vl,\n                           lapack_int ldvl, double* vr, lapack_int ldvr,\n                           lapack_int mm, lapack_int* m );\nlapack_int LAPACKE_ctrevc( int matrix_order, char side, char howmny,\n                           const lapack_logical* select, lapack_int n,\n                           lapack_complex_float* t, lapack_int ldt,\n                           lapack_complex_float* vl, lapack_int ldvl,\n                           lapack_complex_float* vr, lapack_int ldvr,\n                           lapack_int mm, lapack_int* m );\nlapack_int LAPACKE_ztrevc( int matrix_order, char side, char howmny,\n                           const lapack_logical* select, lapack_int n,\n                           lapack_complex_double* t, lapack_int ldt,\n                           lapack_complex_double* vl, lapack_int ldvl,\n                           lapack_complex_double* vr, lapack_int ldvr,\n                           lapack_int mm, lapack_int* m );\n\nlapack_int LAPACKE_strexc( int matrix_order, char compq, lapack_int n, float* t,\n                           lapack_int ldt, float* q, lapack_int ldq,\n                           lapack_int* ifst, lapack_int* ilst );\nlapack_int LAPACKE_dtrexc( int matrix_order, char compq, lapack_int n,\n                           double* t, lapack_int ldt, double* q, lapack_int ldq,\n                           lapack_int* ifst, lapack_int* ilst );\nlapack_int LAPACKE_ctrexc( int matrix_order, char compq, lapack_int n,\n                           lapack_complex_float* t, lapack_int ldt,\n                           lapack_complex_float* q, lapack_int ldq,\n                           lapack_int ifst, lapack_int ilst );\nlapack_int LAPACKE_ztrexc( int matrix_order, char compq, lapack_int n,\n                           lapack_complex_double* t, lapack_int ldt,\n                           lapack_complex_double* q, lapack_int ldq,\n                           lapack_int ifst, lapack_int ilst );\n\nlapack_int LAPACKE_strrfs( int matrix_order, char uplo, char trans, char diag,\n                           lapack_int n, lapack_int nrhs, const float* a,\n                           lapack_int lda, const float* b, lapack_int ldb,\n                           const float* x, lapack_int ldx, float* ferr,\n                           float* berr );\nlapack_int LAPACKE_dtrrfs( int matrix_order, char uplo, char trans, char diag,\n                           lapack_int n, lapack_int nrhs, const double* a,\n                           lapack_int lda, const double* b, lapack_int ldb,\n                           const double* x, lapack_int ldx, double* ferr,\n                           double* berr );\nlapack_int LAPACKE_ctrrfs( int matrix_order, char uplo, char trans, char diag,\n                           lapack_int n, lapack_int nrhs,\n                           const lapack_complex_float* a, lapack_int lda,\n                           const lapack_complex_float* b, lapack_int ldb,\n                           const lapack_complex_float* x, lapack_int ldx,\n                           float* ferr, float* berr );\nlapack_int LAPACKE_ztrrfs( int matrix_order, char uplo, char trans, char diag,\n                           lapack_int n, lapack_int nrhs,\n                           const lapack_complex_double* a, lapack_int lda,\n                           const lapack_complex_double* b, lapack_int ldb,\n                           const lapack_complex_double* x, lapack_int ldx,\n                           double* ferr, double* berr );\n\nlapack_int LAPACKE_strsen( int matrix_order, char job, char compq,\n                           const lapack_logical* select, lapack_int n, float* t,\n                           lapack_int ldt, float* q, lapack_int ldq, float* wr,\n                           float* wi, lapack_int* m, float* s, float* sep );\nlapack_int LAPACKE_dtrsen( int matrix_order, char job, char compq,\n                           const lapack_logical* select, lapack_int n,\n                           double* t, lapack_int ldt, double* q, lapack_int ldq,\n                           double* wr, double* wi, lapack_int* m, double* s,\n                           double* sep );\nlapack_int LAPACKE_ctrsen( int matrix_order, char job, char compq,\n                           const lapack_logical* select, lapack_int n,\n                           lapack_complex_float* t, lapack_int ldt,\n                           lapack_complex_float* q, lapack_int ldq,\n                           lapack_complex_float* w, lapack_int* m, float* s,\n                           float* sep );\nlapack_int LAPACKE_ztrsen( int matrix_order, char job, char compq,\n                           const lapack_logical* select, lapack_int n,\n                           lapack_complex_double* t, lapack_int ldt,\n                           lapack_complex_double* q, lapack_int ldq,\n                           lapack_complex_double* w, lapack_int* m, double* s,\n                           double* sep );\n\nlapack_int LAPACKE_strsna( int matrix_order, char job, char howmny,\n                           const lapack_logical* select, lapack_int n,\n                           const float* t, lapack_int ldt, const float* vl,\n                           lapack_int ldvl, const float* vr, lapack_int ldvr,\n                           float* s, float* sep, lapack_int mm, lapack_int* m );\nlapack_int LAPACKE_dtrsna( int matrix_order, char job, char howmny,\n                           const lapack_logical* select, lapack_int n,\n                           const double* t, lapack_int ldt, const double* vl,\n                           lapack_int ldvl, const double* vr, lapack_int ldvr,\n                           double* s, double* sep, lapack_int mm,\n                           lapack_int* m );\nlapack_int LAPACKE_ctrsna( int matrix_order, char job, char howmny,\n                           const lapack_logical* select, lapack_int n,\n                           const lapack_complex_float* t, lapack_int ldt,\n                           const lapack_complex_float* vl, lapack_int ldvl,\n                           const lapack_complex_float* vr, lapack_int ldvr,\n                           float* s, float* sep, lapack_int mm, lapack_int* m );\nlapack_int LAPACKE_ztrsna( int matrix_order, char job, char howmny,\n                           const lapack_logical* select, lapack_int n,\n                           const lapack_complex_double* t, lapack_int ldt,\n                           const lapack_complex_double* vl, lapack_int ldvl,\n                           const lapack_complex_double* vr, lapack_int ldvr,\n                           double* s, double* sep, lapack_int mm,\n                           lapack_int* m );\n\nlapack_int LAPACKE_strsyl( int matrix_order, char trana, char tranb,\n                           lapack_int isgn, lapack_int m, lapack_int n,\n                           const float* a, lapack_int lda, const float* b,\n                           lapack_int ldb, float* c, lapack_int ldc,\n                           float* scale );\nlapack_int LAPACKE_dtrsyl( int matrix_order, char trana, char tranb,\n                           lapack_int isgn, lapack_int m, lapack_int n,\n                           const double* a, lapack_int lda, const double* b,\n                           lapack_int ldb, double* c, lapack_int ldc,\n                           double* scale );\nlapack_int LAPACKE_ctrsyl( int matrix_order, char trana, char tranb,\n                           lapack_int isgn, lapack_int m, lapack_int n,\n                           const lapack_complex_float* a, lapack_int lda,\n                           const lapack_complex_float* b, lapack_int ldb,\n                           lapack_complex_float* c, lapack_int ldc,\n                           float* scale );\nlapack_int LAPACKE_ztrsyl( int matrix_order, char trana, char tranb,\n                           lapack_int isgn, lapack_int m, lapack_int n,\n                           const lapack_complex_double* a, lapack_int lda,\n                           const lapack_complex_double* b, lapack_int ldb,\n                           lapack_complex_double* c, lapack_int ldc,\n                           double* scale );\n\nlapack_int LAPACKE_strtri( int matrix_order, char uplo, char diag, lapack_int n,\n                           float* a, lapack_int lda );\nlapack_int LAPACKE_dtrtri( int matrix_order, char uplo, char diag, lapack_int n,\n                           double* a, lapack_int lda );\nlapack_int LAPACKE_ctrtri( int matrix_order, char uplo, char diag, lapack_int n,\n                           lapack_complex_float* a, lapack_int lda );\nlapack_int LAPACKE_ztrtri( int matrix_order, char uplo, char diag, lapack_int n,\n                           lapack_complex_double* a, lapack_int lda );\n\nlapack_int LAPACKE_strtrs( int matrix_order, char uplo, char trans, char diag,\n                           lapack_int n, lapack_int nrhs, const float* a,\n                           lapack_int lda, float* b, lapack_int ldb );\nlapack_int LAPACKE_dtrtrs( int matrix_order, char uplo, char trans, char diag,\n                           lapack_int n, lapack_int nrhs, const double* a,\n                           lapack_int lda, double* b, lapack_int ldb );\nlapack_int LAPACKE_ctrtrs( int matrix_order, char uplo, char trans, char diag,\n                           lapack_int n, lapack_int nrhs,\n                           const lapack_complex_float* a, lapack_int lda,\n                           lapack_complex_float* b, lapack_int ldb );\nlapack_int LAPACKE_ztrtrs( int matrix_order, char uplo, char trans, char diag,\n                           lapack_int n, lapack_int nrhs,\n                           const lapack_complex_double* a, lapack_int lda,\n                           lapack_complex_double* b, lapack_int ldb );\n\nlapack_int LAPACKE_strttf( int matrix_order, char transr, char uplo,\n                           lapack_int n, const float* a, lapack_int lda,\n                           float* arf );\nlapack_int LAPACKE_dtrttf( int matrix_order, char transr, char uplo,\n                           lapack_int n, const double* a, lapack_int lda,\n                           double* arf );\nlapack_int LAPACKE_ctrttf( int matrix_order, char transr, char uplo,\n                           lapack_int n, const lapack_complex_float* a,\n                           lapack_int lda, lapack_complex_float* arf );\nlapack_int LAPACKE_ztrttf( int matrix_order, char transr, char uplo,\n                           lapack_int n, const lapack_complex_double* a,\n                           lapack_int lda, lapack_complex_double* arf );\n\nlapack_int LAPACKE_strttp( int matrix_order, char uplo, lapack_int n,\n                           const float* a, lapack_int lda, float* ap );\nlapack_int LAPACKE_dtrttp( int matrix_order, char uplo, lapack_int n,\n                           const double* a, lapack_int lda, double* ap );\nlapack_int LAPACKE_ctrttp( int matrix_order, char uplo, lapack_int n,\n                           const lapack_complex_float* a, lapack_int lda,\n                           lapack_complex_float* ap );\nlapack_int LAPACKE_ztrttp( int matrix_order, char uplo, lapack_int n,\n                           const lapack_complex_double* a, lapack_int lda,\n                           lapack_complex_double* ap );\n\nlapack_int LAPACKE_stzrzf( int matrix_order, lapack_int m, lapack_int n,\n                           float* a, lapack_int lda, float* tau );\nlapack_int LAPACKE_dtzrzf( int matrix_order, lapack_int m, lapack_int n,\n                           double* a, lapack_int lda, double* tau );\nlapack_int LAPACKE_ctzrzf( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_complex_float* a, lapack_int lda,\n                           lapack_complex_float* tau );\nlapack_int LAPACKE_ztzrzf( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_complex_double* a, lapack_int lda,\n                           lapack_complex_double* tau );\n\nlapack_int LAPACKE_cungbr( int matrix_order, char vect, lapack_int m,\n                           lapack_int n, lapack_int k, lapack_complex_float* a,\n                           lapack_int lda, const lapack_complex_float* tau );\nlapack_int LAPACKE_zungbr( int matrix_order, char vect, lapack_int m,\n                           lapack_int n, lapack_int k, lapack_complex_double* a,\n                           lapack_int lda, const lapack_complex_double* tau );\n\nlapack_int LAPACKE_cunghr( int matrix_order, lapack_int n, lapack_int ilo,\n                           lapack_int ihi, lapack_complex_float* a,\n                           lapack_int lda, const lapack_complex_float* tau );\nlapack_int LAPACKE_zunghr( int matrix_order, lapack_int n, lapack_int ilo,\n                           lapack_int ihi, lapack_complex_double* a,\n                           lapack_int lda, const lapack_complex_double* tau );\n\nlapack_int LAPACKE_cunglq( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int k, lapack_complex_float* a,\n                           lapack_int lda, const lapack_complex_float* tau );\nlapack_int LAPACKE_zunglq( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int k, lapack_complex_double* a,\n                           lapack_int lda, const lapack_complex_double* tau );\n\nlapack_int LAPACKE_cungql( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int k, lapack_complex_float* a,\n                           lapack_int lda, const lapack_complex_float* tau );\nlapack_int LAPACKE_zungql( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int k, lapack_complex_double* a,\n                           lapack_int lda, const lapack_complex_double* tau );\n\nlapack_int LAPACKE_cungqr( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int k, lapack_complex_float* a,\n                           lapack_int lda, const lapack_complex_float* tau );\nlapack_int LAPACKE_zungqr( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int k, lapack_complex_double* a,\n                           lapack_int lda, const lapack_complex_double* tau );\n\nlapack_int LAPACKE_cungrq( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int k, lapack_complex_float* a,\n                           lapack_int lda, const lapack_complex_float* tau );\nlapack_int LAPACKE_zungrq( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int k, lapack_complex_double* a,\n                           lapack_int lda, const lapack_complex_double* tau );\n\nlapack_int LAPACKE_cungtr( int matrix_order, char uplo, lapack_int n,\n                           lapack_complex_float* a, lapack_int lda,\n                           const lapack_complex_float* tau );\nlapack_int LAPACKE_zungtr( int matrix_order, char uplo, lapack_int n,\n                           lapack_complex_double* a, lapack_int lda,\n                           const lapack_complex_double* tau );\n\nlapack_int LAPACKE_cunmbr( int matrix_order, char vect, char side, char trans,\n                           lapack_int m, lapack_int n, lapack_int k,\n                           const lapack_complex_float* a, lapack_int lda,\n                           const lapack_complex_float* tau,\n                           lapack_complex_float* c, lapack_int ldc );\nlapack_int LAPACKE_zunmbr( int matrix_order, char vect, char side, char trans,\n                           lapack_int m, lapack_int n, lapack_int k,\n                           const lapack_complex_double* a, lapack_int lda,\n                           const lapack_complex_double* tau,\n                           lapack_complex_double* c, lapack_int ldc );\n\nlapack_int LAPACKE_cunmhr( int matrix_order, char side, char trans,\n                           lapack_int m, lapack_int n, lapack_int ilo,\n                           lapack_int ihi, const lapack_complex_float* a,\n                           lapack_int lda, const lapack_complex_float* tau,\n                           lapack_complex_float* c, lapack_int ldc );\nlapack_int LAPACKE_zunmhr( int matrix_order, char side, char trans,\n                           lapack_int m, lapack_int n, lapack_int ilo,\n                           lapack_int ihi, const lapack_complex_double* a,\n                           lapack_int lda, const lapack_complex_double* tau,\n                           lapack_complex_double* c, lapack_int ldc );\n\nlapack_int LAPACKE_cunmlq( int matrix_order, char side, char trans,\n                           lapack_int m, lapack_int n, lapack_int k,\n                           const lapack_complex_float* a, lapack_int lda,\n                           const lapack_complex_float* tau,\n                           lapack_complex_float* c, lapack_int ldc );\nlapack_int LAPACKE_zunmlq( int matrix_order, char side, char trans,\n                           lapack_int m, lapack_int n, lapack_int k,\n                           const lapack_complex_double* a, lapack_int lda,\n                           const lapack_complex_double* tau,\n                           lapack_complex_double* c, lapack_int ldc );\n\nlapack_int LAPACKE_cunmql( int matrix_order, char side, char trans,\n                           lapack_int m, lapack_int n, lapack_int k,\n                           const lapack_complex_float* a, lapack_int lda,\n                           const lapack_complex_float* tau,\n                           lapack_complex_float* c, lapack_int ldc );\nlapack_int LAPACKE_zunmql( int matrix_order, char side, char trans,\n                           lapack_int m, lapack_int n, lapack_int k,\n                           const lapack_complex_double* a, lapack_int lda,\n                           const lapack_complex_double* tau,\n                           lapack_complex_double* c, lapack_int ldc );\n\nlapack_int LAPACKE_cunmqr( int matrix_order, char side, char trans,\n                           lapack_int m, lapack_int n, lapack_int k,\n                           const lapack_complex_float* a, lapack_int lda,\n                           const lapack_complex_float* tau,\n                           lapack_complex_float* c, lapack_int ldc );\nlapack_int LAPACKE_zunmqr( int matrix_order, char side, char trans,\n                           lapack_int m, lapack_int n, lapack_int k,\n                           const lapack_complex_double* a, lapack_int lda,\n                           const lapack_complex_double* tau,\n                           lapack_complex_double* c, lapack_int ldc );\n\nlapack_int LAPACKE_cunmrq( int matrix_order, char side, char trans,\n                           lapack_int m, lapack_int n, lapack_int k,\n                           const lapack_complex_float* a, lapack_int lda,\n                           const lapack_complex_float* tau,\n                           lapack_complex_float* c, lapack_int ldc );\nlapack_int LAPACKE_zunmrq( int matrix_order, char side, char trans,\n                           lapack_int m, lapack_int n, lapack_int k,\n                           const lapack_complex_double* a, lapack_int lda,\n                           const lapack_complex_double* tau,\n                           lapack_complex_double* c, lapack_int ldc );\n\nlapack_int LAPACKE_cunmrz( int matrix_order, char side, char trans,\n                           lapack_int m, lapack_int n, lapack_int k,\n                           lapack_int l, const lapack_complex_float* a,\n                           lapack_int lda, const lapack_complex_float* tau,\n                           lapack_complex_float* c, lapack_int ldc );\nlapack_int LAPACKE_zunmrz( int matrix_order, char side, char trans,\n                           lapack_int m, lapack_int n, lapack_int k,\n                           lapack_int l, const lapack_complex_double* a,\n                           lapack_int lda, const lapack_complex_double* tau,\n                           lapack_complex_double* c, lapack_int ldc );\n\nlapack_int LAPACKE_cunmtr( int matrix_order, char side, char uplo, char trans,\n                           lapack_int m, lapack_int n,\n                           const lapack_complex_float* a, lapack_int lda,\n                           const lapack_complex_float* tau,\n                           lapack_complex_float* c, lapack_int ldc );\nlapack_int LAPACKE_zunmtr( int matrix_order, char side, char uplo, char trans,\n                           lapack_int m, lapack_int n,\n                           const lapack_complex_double* a, lapack_int lda,\n                           const lapack_complex_double* tau,\n                           lapack_complex_double* c, lapack_int ldc );\n\nlapack_int LAPACKE_cupgtr( int matrix_order, char uplo, lapack_int n,\n                           const lapack_complex_float* ap,\n                           const lapack_complex_float* tau,\n                           lapack_complex_float* q, lapack_int ldq );\nlapack_int LAPACKE_zupgtr( int matrix_order, char uplo, lapack_int n,\n                           const lapack_complex_double* ap,\n                           const lapack_complex_double* tau,\n                           lapack_complex_double* q, lapack_int ldq );\n\nlapack_int LAPACKE_cupmtr( int matrix_order, char side, char uplo, char trans,\n                           lapack_int m, lapack_int n,\n                           const lapack_complex_float* ap,\n                           const lapack_complex_float* tau,\n                           lapack_complex_float* c, lapack_int ldc );\nlapack_int LAPACKE_zupmtr( int matrix_order, char side, char uplo, char trans,\n                           lapack_int m, lapack_int n,\n                           const lapack_complex_double* ap,\n                           const lapack_complex_double* tau,\n                           lapack_complex_double* c, lapack_int ldc );\n\nlapack_int LAPACKE_sbdsdc_work( int matrix_order, char uplo, char compq,\n                                lapack_int n, float* d, float* e, float* u,\n                                lapack_int ldu, float* vt, lapack_int ldvt,\n                                float* q, lapack_int* iq, float* work,\n                                lapack_int* iwork );\nlapack_int LAPACKE_dbdsdc_work( int matrix_order, char uplo, char compq,\n                                lapack_int n, double* d, double* e, double* u,\n                                lapack_int ldu, double* vt, lapack_int ldvt,\n                                double* q, lapack_int* iq, double* work,\n                                lapack_int* iwork );\n\nlapack_int LAPACKE_sbdsqr_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int ncvt, lapack_int nru, lapack_int ncc,\n                                float* d, float* e, float* vt, lapack_int ldvt,\n                                float* u, lapack_int ldu, float* c,\n                                lapack_int ldc, float* work );\nlapack_int LAPACKE_dbdsqr_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int ncvt, lapack_int nru, lapack_int ncc,\n                                double* d, double* e, double* vt,\n                                lapack_int ldvt, double* u, lapack_int ldu,\n                                double* c, lapack_int ldc, double* work );\nlapack_int LAPACKE_cbdsqr_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int ncvt, lapack_int nru, lapack_int ncc,\n                                float* d, float* e, lapack_complex_float* vt,\n                                lapack_int ldvt, lapack_complex_float* u,\n                                lapack_int ldu, lapack_complex_float* c,\n                                lapack_int ldc, float* work );\nlapack_int LAPACKE_zbdsqr_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int ncvt, lapack_int nru, lapack_int ncc,\n                                double* d, double* e, lapack_complex_double* vt,\n                                lapack_int ldvt, lapack_complex_double* u,\n                                lapack_int ldu, lapack_complex_double* c,\n                                lapack_int ldc, double* work );\n\nlapack_int LAPACKE_sdisna_work( char job, lapack_int m, lapack_int n,\n                                const float* d, float* sep );\nlapack_int LAPACKE_ddisna_work( char job, lapack_int m, lapack_int n,\n                                const double* d, double* sep );\n\nlapack_int LAPACKE_sgbbrd_work( int matrix_order, char vect, lapack_int m,\n                                lapack_int n, lapack_int ncc, lapack_int kl,\n                                lapack_int ku, float* ab, lapack_int ldab,\n                                float* d, float* e, float* q, lapack_int ldq,\n                                float* pt, lapack_int ldpt, float* c,\n                                lapack_int ldc, float* work );\nlapack_int LAPACKE_dgbbrd_work( int matrix_order, char vect, lapack_int m,\n                                lapack_int n, lapack_int ncc, lapack_int kl,\n                                lapack_int ku, double* ab, lapack_int ldab,\n                                double* d, double* e, double* q, lapack_int ldq,\n                                double* pt, lapack_int ldpt, double* c,\n                                lapack_int ldc, double* work );\nlapack_int LAPACKE_cgbbrd_work( int matrix_order, char vect, lapack_int m,\n                                lapack_int n, lapack_int ncc, lapack_int kl,\n                                lapack_int ku, lapack_complex_float* ab,\n                                lapack_int ldab, float* d, float* e,\n                                lapack_complex_float* q, lapack_int ldq,\n                                lapack_complex_float* pt, lapack_int ldpt,\n                                lapack_complex_float* c, lapack_int ldc,\n                                lapack_complex_float* work, float* rwork );\nlapack_int LAPACKE_zgbbrd_work( int matrix_order, char vect, lapack_int m,\n                                lapack_int n, lapack_int ncc, lapack_int kl,\n                                lapack_int ku, lapack_complex_double* ab,\n                                lapack_int ldab, double* d, double* e,\n                                lapack_complex_double* q, lapack_int ldq,\n                                lapack_complex_double* pt, lapack_int ldpt,\n                                lapack_complex_double* c, lapack_int ldc,\n                                lapack_complex_double* work, double* rwork );\n\nlapack_int LAPACKE_sgbcon_work( int matrix_order, char norm, lapack_int n,\n                                lapack_int kl, lapack_int ku, const float* ab,\n                                lapack_int ldab, const lapack_int* ipiv,\n                                float anorm, float* rcond, float* work,\n                                lapack_int* iwork );\nlapack_int LAPACKE_dgbcon_work( int matrix_order, char norm, lapack_int n,\n                                lapack_int kl, lapack_int ku, const double* ab,\n                                lapack_int ldab, const lapack_int* ipiv,\n                                double anorm, double* rcond, double* work,\n                                lapack_int* iwork );\nlapack_int LAPACKE_cgbcon_work( int matrix_order, char norm, lapack_int n,\n                                lapack_int kl, lapack_int ku,\n                                const lapack_complex_float* ab, lapack_int ldab,\n                                const lapack_int* ipiv, float anorm,\n                                float* rcond, lapack_complex_float* work,\n                                float* rwork );\nlapack_int LAPACKE_zgbcon_work( int matrix_order, char norm, lapack_int n,\n                                lapack_int kl, lapack_int ku,\n                                const lapack_complex_double* ab,\n                                lapack_int ldab, const lapack_int* ipiv,\n                                double anorm, double* rcond,\n                                lapack_complex_double* work, double* rwork );\n\nlapack_int LAPACKE_sgbequ_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int kl, lapack_int ku, const float* ab,\n                                lapack_int ldab, float* r, float* c,\n                                float* rowcnd, float* colcnd, float* amax );\nlapack_int LAPACKE_dgbequ_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int kl, lapack_int ku, const double* ab,\n                                lapack_int ldab, double* r, double* c,\n                                double* rowcnd, double* colcnd, double* amax );\nlapack_int LAPACKE_cgbequ_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int kl, lapack_int ku,\n                                const lapack_complex_float* ab, lapack_int ldab,\n                                float* r, float* c, float* rowcnd,\n                                float* colcnd, float* amax );\nlapack_int LAPACKE_zgbequ_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int kl, lapack_int ku,\n                                const lapack_complex_double* ab,\n                                lapack_int ldab, double* r, double* c,\n                                double* rowcnd, double* colcnd, double* amax );\n\nlapack_int LAPACKE_sgbequb_work( int matrix_order, lapack_int m, lapack_int n,\n                                 lapack_int kl, lapack_int ku, const float* ab,\n                                 lapack_int ldab, float* r, float* c,\n                                 float* rowcnd, float* colcnd, float* amax );\nlapack_int LAPACKE_dgbequb_work( int matrix_order, lapack_int m, lapack_int n,\n                                 lapack_int kl, lapack_int ku, const double* ab,\n                                 lapack_int ldab, double* r, double* c,\n                                 double* rowcnd, double* colcnd, double* amax );\nlapack_int LAPACKE_cgbequb_work( int matrix_order, lapack_int m, lapack_int n,\n                                 lapack_int kl, lapack_int ku,\n                                 const lapack_complex_float* ab,\n                                 lapack_int ldab, float* r, float* c,\n                                 float* rowcnd, float* colcnd, float* amax );\nlapack_int LAPACKE_zgbequb_work( int matrix_order, lapack_int m, lapack_int n,\n                                 lapack_int kl, lapack_int ku,\n                                 const lapack_complex_double* ab,\n                                 lapack_int ldab, double* r, double* c,\n                                 double* rowcnd, double* colcnd, double* amax );\n\nlapack_int LAPACKE_sgbrfs_work( int matrix_order, char trans, lapack_int n,\n                                lapack_int kl, lapack_int ku, lapack_int nrhs,\n                                const float* ab, lapack_int ldab,\n                                const float* afb, lapack_int ldafb,\n                                const lapack_int* ipiv, const float* b,\n                                lapack_int ldb, float* x, lapack_int ldx,\n                                float* ferr, float* berr, float* work,\n                                lapack_int* iwork );\nlapack_int LAPACKE_dgbrfs_work( int matrix_order, char trans, lapack_int n,\n                                lapack_int kl, lapack_int ku, lapack_int nrhs,\n                                const double* ab, lapack_int ldab,\n                                const double* afb, lapack_int ldafb,\n                                const lapack_int* ipiv, const double* b,\n                                lapack_int ldb, double* x, lapack_int ldx,\n                                double* ferr, double* berr, double* work,\n                                lapack_int* iwork );\nlapack_int LAPACKE_cgbrfs_work( int matrix_order, char trans, lapack_int n,\n                                lapack_int kl, lapack_int ku, lapack_int nrhs,\n                                const lapack_complex_float* ab, lapack_int ldab,\n                                const lapack_complex_float* afb,\n                                lapack_int ldafb, const lapack_int* ipiv,\n                                const lapack_complex_float* b, lapack_int ldb,\n                                lapack_complex_float* x, lapack_int ldx,\n                                float* ferr, float* berr,\n                                lapack_complex_float* work, float* rwork );\nlapack_int LAPACKE_zgbrfs_work( int matrix_order, char trans, lapack_int n,\n                                lapack_int kl, lapack_int ku, lapack_int nrhs,\n                                const lapack_complex_double* ab,\n                                lapack_int ldab,\n                                const lapack_complex_double* afb,\n                                lapack_int ldafb, const lapack_int* ipiv,\n                                const lapack_complex_double* b, lapack_int ldb,\n                                lapack_complex_double* x, lapack_int ldx,\n                                double* ferr, double* berr,\n                                lapack_complex_double* work, double* rwork );\n\nlapack_int LAPACKE_sgbrfsx_work( int matrix_order, char trans, char equed,\n                                 lapack_int n, lapack_int kl, lapack_int ku,\n                                 lapack_int nrhs, const float* ab,\n                                 lapack_int ldab, const float* afb,\n                                 lapack_int ldafb, const lapack_int* ipiv,\n                                 const float* r, const float* c, const float* b,\n                                 lapack_int ldb, float* x, lapack_int ldx,\n                                 float* rcond, float* berr,\n                                 lapack_int n_err_bnds, float* err_bnds_norm,\n                                 float* err_bnds_comp, lapack_int nparams,\n                                 float* params, float* work,\n                                 lapack_int* iwork );\nlapack_int LAPACKE_dgbrfsx_work( int matrix_order, char trans, char equed,\n                                 lapack_int n, lapack_int kl, lapack_int ku,\n                                 lapack_int nrhs, const double* ab,\n                                 lapack_int ldab, const double* afb,\n                                 lapack_int ldafb, const lapack_int* ipiv,\n                                 const double* r, const double* c,\n                                 const double* b, lapack_int ldb, double* x,\n                                 lapack_int ldx, double* rcond, double* berr,\n                                 lapack_int n_err_bnds, double* err_bnds_norm,\n                                 double* err_bnds_comp, lapack_int nparams,\n                                 double* params, double* work,\n                                 lapack_int* iwork );\nlapack_int LAPACKE_cgbrfsx_work( int matrix_order, char trans, char equed,\n                                 lapack_int n, lapack_int kl, lapack_int ku,\n                                 lapack_int nrhs,\n                                 const lapack_complex_float* ab,\n                                 lapack_int ldab,\n                                 const lapack_complex_float* afb,\n                                 lapack_int ldafb, const lapack_int* ipiv,\n                                 const float* r, const float* c,\n                                 const lapack_complex_float* b, lapack_int ldb,\n                                 lapack_complex_float* x, lapack_int ldx,\n                                 float* rcond, float* berr,\n                                 lapack_int n_err_bnds, float* err_bnds_norm,\n                                 float* err_bnds_comp, lapack_int nparams,\n                                 float* params, lapack_complex_float* work,\n                                 float* rwork );\nlapack_int LAPACKE_zgbrfsx_work( int matrix_order, char trans, char equed,\n                                 lapack_int n, lapack_int kl, lapack_int ku,\n                                 lapack_int nrhs,\n                                 const lapack_complex_double* ab,\n                                 lapack_int ldab,\n                                 const lapack_complex_double* afb,\n                                 lapack_int ldafb, const lapack_int* ipiv,\n                                 const double* r, const double* c,\n                                 const lapack_complex_double* b, lapack_int ldb,\n                                 lapack_complex_double* x, lapack_int ldx,\n                                 double* rcond, double* berr,\n                                 lapack_int n_err_bnds, double* err_bnds_norm,\n                                 double* err_bnds_comp, lapack_int nparams,\n                                 double* params, lapack_complex_double* work,\n                                 double* rwork );\n\nlapack_int LAPACKE_sgbsv_work( int matrix_order, lapack_int n, lapack_int kl,\n                               lapack_int ku, lapack_int nrhs, float* ab,\n                               lapack_int ldab, lapack_int* ipiv, float* b,\n                               lapack_int ldb );\nlapack_int LAPACKE_dgbsv_work( int matrix_order, lapack_int n, lapack_int kl,\n                               lapack_int ku, lapack_int nrhs, double* ab,\n                               lapack_int ldab, lapack_int* ipiv, double* b,\n                               lapack_int ldb );\nlapack_int LAPACKE_cgbsv_work( int matrix_order, lapack_int n, lapack_int kl,\n                               lapack_int ku, lapack_int nrhs,\n                               lapack_complex_float* ab, lapack_int ldab,\n                               lapack_int* ipiv, lapack_complex_float* b,\n                               lapack_int ldb );\nlapack_int LAPACKE_zgbsv_work( int matrix_order, lapack_int n, lapack_int kl,\n                               lapack_int ku, lapack_int nrhs,\n                               lapack_complex_double* ab, lapack_int ldab,\n                               lapack_int* ipiv, lapack_complex_double* b,\n                               lapack_int ldb );\n\nlapack_int LAPACKE_sgbsvx_work( int matrix_order, char fact, char trans,\n                                lapack_int n, lapack_int kl, lapack_int ku,\n                                lapack_int nrhs, float* ab, lapack_int ldab,\n                                float* afb, lapack_int ldafb, lapack_int* ipiv,\n                                char* equed, float* r, float* c, float* b,\n                                lapack_int ldb, float* x, lapack_int ldx,\n                                float* rcond, float* ferr, float* berr,\n                                float* work, lapack_int* iwork );\nlapack_int LAPACKE_dgbsvx_work( int matrix_order, char fact, char trans,\n                                lapack_int n, lapack_int kl, lapack_int ku,\n                                lapack_int nrhs, double* ab, lapack_int ldab,\n                                double* afb, lapack_int ldafb, lapack_int* ipiv,\n                                char* equed, double* r, double* c, double* b,\n                                lapack_int ldb, double* x, lapack_int ldx,\n                                double* rcond, double* ferr, double* berr,\n                                double* work, lapack_int* iwork );\nlapack_int LAPACKE_cgbsvx_work( int matrix_order, char fact, char trans,\n                                lapack_int n, lapack_int kl, lapack_int ku,\n                                lapack_int nrhs, lapack_complex_float* ab,\n                                lapack_int ldab, lapack_complex_float* afb,\n                                lapack_int ldafb, lapack_int* ipiv, char* equed,\n                                float* r, float* c, lapack_complex_float* b,\n                                lapack_int ldb, lapack_complex_float* x,\n                                lapack_int ldx, float* rcond, float* ferr,\n                                float* berr, lapack_complex_float* work,\n                                float* rwork );\nlapack_int LAPACKE_zgbsvx_work( int matrix_order, char fact, char trans,\n                                lapack_int n, lapack_int kl, lapack_int ku,\n                                lapack_int nrhs, lapack_complex_double* ab,\n                                lapack_int ldab, lapack_complex_double* afb,\n                                lapack_int ldafb, lapack_int* ipiv, char* equed,\n                                double* r, double* c, lapack_complex_double* b,\n                                lapack_int ldb, lapack_complex_double* x,\n                                lapack_int ldx, double* rcond, double* ferr,\n                                double* berr, lapack_complex_double* work,\n                                double* rwork );\n\nlapack_int LAPACKE_sgbsvxx_work( int matrix_order, char fact, char trans,\n                                 lapack_int n, lapack_int kl, lapack_int ku,\n                                 lapack_int nrhs, float* ab, lapack_int ldab,\n                                 float* afb, lapack_int ldafb, lapack_int* ipiv,\n                                 char* equed, float* r, float* c, float* b,\n                                 lapack_int ldb, float* x, lapack_int ldx,\n                                 float* rcond, float* rpvgrw, float* berr,\n                                 lapack_int n_err_bnds, float* err_bnds_norm,\n                                 float* err_bnds_comp, lapack_int nparams,\n                                 float* params, float* work,\n                                 lapack_int* iwork );\nlapack_int LAPACKE_dgbsvxx_work( int matrix_order, char fact, char trans,\n                                 lapack_int n, lapack_int kl, lapack_int ku,\n                                 lapack_int nrhs, double* ab, lapack_int ldab,\n                                 double* afb, lapack_int ldafb,\n                                 lapack_int* ipiv, char* equed, double* r,\n                                 double* c, double* b, lapack_int ldb,\n                                 double* x, lapack_int ldx, double* rcond,\n                                 double* rpvgrw, double* berr,\n                                 lapack_int n_err_bnds, double* err_bnds_norm,\n                                 double* err_bnds_comp, lapack_int nparams,\n                                 double* params, double* work,\n                                 lapack_int* iwork );\nlapack_int LAPACKE_cgbsvxx_work( int matrix_order, char fact, char trans,\n                                 lapack_int n, lapack_int kl, lapack_int ku,\n                                 lapack_int nrhs, lapack_complex_float* ab,\n                                 lapack_int ldab, lapack_complex_float* afb,\n                                 lapack_int ldafb, lapack_int* ipiv,\n                                 char* equed, float* r, float* c,\n                                 lapack_complex_float* b, lapack_int ldb,\n                                 lapack_complex_float* x, lapack_int ldx,\n                                 float* rcond, float* rpvgrw, float* berr,\n                                 lapack_int n_err_bnds, float* err_bnds_norm,\n                                 float* err_bnds_comp, lapack_int nparams,\n                                 float* params, lapack_complex_float* work,\n                                 float* rwork );\nlapack_int LAPACKE_zgbsvxx_work( int matrix_order, char fact, char trans,\n                                 lapack_int n, lapack_int kl, lapack_int ku,\n                                 lapack_int nrhs, lapack_complex_double* ab,\n                                 lapack_int ldab, lapack_complex_double* afb,\n                                 lapack_int ldafb, lapack_int* ipiv,\n                                 char* equed, double* r, double* c,\n                                 lapack_complex_double* b, lapack_int ldb,\n                                 lapack_complex_double* x, lapack_int ldx,\n                                 double* rcond, double* rpvgrw, double* berr,\n                                 lapack_int n_err_bnds, double* err_bnds_norm,\n                                 double* err_bnds_comp, lapack_int nparams,\n                                 double* params, lapack_complex_double* work,\n                                 double* rwork );\n\nlapack_int LAPACKE_sgbtrf_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int kl, lapack_int ku, float* ab,\n                                lapack_int ldab, lapack_int* ipiv );\nlapack_int LAPACKE_dgbtrf_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int kl, lapack_int ku, double* ab,\n                                lapack_int ldab, lapack_int* ipiv );\nlapack_int LAPACKE_cgbtrf_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int kl, lapack_int ku,\n                                lapack_complex_float* ab, lapack_int ldab,\n                                lapack_int* ipiv );\nlapack_int LAPACKE_zgbtrf_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int kl, lapack_int ku,\n                                lapack_complex_double* ab, lapack_int ldab,\n                                lapack_int* ipiv );\n\nlapack_int LAPACKE_sgbtrs_work( int matrix_order, char trans, lapack_int n,\n                                lapack_int kl, lapack_int ku, lapack_int nrhs,\n                                const float* ab, lapack_int ldab,\n                                const lapack_int* ipiv, float* b,\n                                lapack_int ldb );\nlapack_int LAPACKE_dgbtrs_work( int matrix_order, char trans, lapack_int n,\n                                lapack_int kl, lapack_int ku, lapack_int nrhs,\n                                const double* ab, lapack_int ldab,\n                                const lapack_int* ipiv, double* b,\n                                lapack_int ldb );\nlapack_int LAPACKE_cgbtrs_work( int matrix_order, char trans, lapack_int n,\n                                lapack_int kl, lapack_int ku, lapack_int nrhs,\n                                const lapack_complex_float* ab, lapack_int ldab,\n                                const lapack_int* ipiv, lapack_complex_float* b,\n                                lapack_int ldb );\nlapack_int LAPACKE_zgbtrs_work( int matrix_order, char trans, lapack_int n,\n                                lapack_int kl, lapack_int ku, lapack_int nrhs,\n                                const lapack_complex_double* ab,\n                                lapack_int ldab, const lapack_int* ipiv,\n                                lapack_complex_double* b, lapack_int ldb );\n\nlapack_int LAPACKE_sgebak_work( int matrix_order, char job, char side,\n                                lapack_int n, lapack_int ilo, lapack_int ihi,\n                                const float* scale, lapack_int m, float* v,\n                                lapack_int ldv );\nlapack_int LAPACKE_dgebak_work( int matrix_order, char job, char side,\n                                lapack_int n, lapack_int ilo, lapack_int ihi,\n                                const double* scale, lapack_int m, double* v,\n                                lapack_int ldv );\nlapack_int LAPACKE_cgebak_work( int matrix_order, char job, char side,\n                                lapack_int n, lapack_int ilo, lapack_int ihi,\n                                const float* scale, lapack_int m,\n                                lapack_complex_float* v, lapack_int ldv );\nlapack_int LAPACKE_zgebak_work( int matrix_order, char job, char side,\n                                lapack_int n, lapack_int ilo, lapack_int ihi,\n                                const double* scale, lapack_int m,\n                                lapack_complex_double* v, lapack_int ldv );\n\nlapack_int LAPACKE_sgebal_work( int matrix_order, char job, lapack_int n,\n                                float* a, lapack_int lda, lapack_int* ilo,\n                                lapack_int* ihi, float* scale );\nlapack_int LAPACKE_dgebal_work( int matrix_order, char job, lapack_int n,\n                                double* a, lapack_int lda, lapack_int* ilo,\n                                lapack_int* ihi, double* scale );\nlapack_int LAPACKE_cgebal_work( int matrix_order, char job, lapack_int n,\n                                lapack_complex_float* a, lapack_int lda,\n                                lapack_int* ilo, lapack_int* ihi,\n                                float* scale );\nlapack_int LAPACKE_zgebal_work( int matrix_order, char job, lapack_int n,\n                                lapack_complex_double* a, lapack_int lda,\n                                lapack_int* ilo, lapack_int* ihi,\n                                double* scale );\n\nlapack_int LAPACKE_sgebrd_work( int matrix_order, lapack_int m, lapack_int n,\n                                float* a, lapack_int lda, float* d, float* e,\n                                float* tauq, float* taup, float* work,\n                                lapack_int lwork );\nlapack_int LAPACKE_dgebrd_work( int matrix_order, lapack_int m, lapack_int n,\n                                double* a, lapack_int lda, double* d, double* e,\n                                double* tauq, double* taup, double* work,\n                                lapack_int lwork );\nlapack_int LAPACKE_cgebrd_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_complex_float* a, lapack_int lda,\n                                float* d, float* e, lapack_complex_float* tauq,\n                                lapack_complex_float* taup,\n                                lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_zgebrd_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_complex_double* a, lapack_int lda,\n                                double* d, double* e,\n                                lapack_complex_double* tauq,\n                                lapack_complex_double* taup,\n                                lapack_complex_double* work, lapack_int lwork );\n\nlapack_int LAPACKE_sgecon_work( int matrix_order, char norm, lapack_int n,\n                                const float* a, lapack_int lda, float anorm,\n                                float* rcond, float* work, lapack_int* iwork );\nlapack_int LAPACKE_dgecon_work( int matrix_order, char norm, lapack_int n,\n                                const double* a, lapack_int lda, double anorm,\n                                double* rcond, double* work,\n                                lapack_int* iwork );\nlapack_int LAPACKE_cgecon_work( int matrix_order, char norm, lapack_int n,\n                                const lapack_complex_float* a, lapack_int lda,\n                                float anorm, float* rcond,\n                                lapack_complex_float* work, float* rwork );\nlapack_int LAPACKE_zgecon_work( int matrix_order, char norm, lapack_int n,\n                                const lapack_complex_double* a, lapack_int lda,\n                                double anorm, double* rcond,\n                                lapack_complex_double* work, double* rwork );\n\nlapack_int LAPACKE_sgeequ_work( int matrix_order, lapack_int m, lapack_int n,\n                                const float* a, lapack_int lda, float* r,\n                                float* c, float* rowcnd, float* colcnd,\n                                float* amax );\nlapack_int LAPACKE_dgeequ_work( int matrix_order, lapack_int m, lapack_int n,\n                                const double* a, lapack_int lda, double* r,\n                                double* c, double* rowcnd, double* colcnd,\n                                double* amax );\nlapack_int LAPACKE_cgeequ_work( int matrix_order, lapack_int m, lapack_int n,\n                                const lapack_complex_float* a, lapack_int lda,\n                                float* r, float* c, float* rowcnd,\n                                float* colcnd, float* amax );\nlapack_int LAPACKE_zgeequ_work( int matrix_order, lapack_int m, lapack_int n,\n                                const lapack_complex_double* a, lapack_int lda,\n                                double* r, double* c, double* rowcnd,\n                                double* colcnd, double* amax );\n\nlapack_int LAPACKE_sgeequb_work( int matrix_order, lapack_int m, lapack_int n,\n                                 const float* a, lapack_int lda, float* r,\n                                 float* c, float* rowcnd, float* colcnd,\n                                 float* amax );\nlapack_int LAPACKE_dgeequb_work( int matrix_order, lapack_int m, lapack_int n,\n                                 const double* a, lapack_int lda, double* r,\n                                 double* c, double* rowcnd, double* colcnd,\n                                 double* amax );\nlapack_int LAPACKE_cgeequb_work( int matrix_order, lapack_int m, lapack_int n,\n                                 const lapack_complex_float* a, lapack_int lda,\n                                 float* r, float* c, float* rowcnd,\n                                 float* colcnd, float* amax );\nlapack_int LAPACKE_zgeequb_work( int matrix_order, lapack_int m, lapack_int n,\n                                 const lapack_complex_double* a, lapack_int lda,\n                                 double* r, double* c, double* rowcnd,\n                                 double* colcnd, double* amax );\n\nlapack_int LAPACKE_sgees_work( int matrix_order, char jobvs, char sort,\n                               LAPACK_S_SELECT2 select, lapack_int n, float* a,\n                               lapack_int lda, lapack_int* sdim, float* wr,\n                               float* wi, float* vs, lapack_int ldvs,\n                               float* work, lapack_int lwork,\n                               lapack_logical* bwork );\nlapack_int LAPACKE_dgees_work( int matrix_order, char jobvs, char sort,\n                               LAPACK_D_SELECT2 select, lapack_int n, double* a,\n                               lapack_int lda, lapack_int* sdim, double* wr,\n                               double* wi, double* vs, lapack_int ldvs,\n                               double* work, lapack_int lwork,\n                               lapack_logical* bwork );\nlapack_int LAPACKE_cgees_work( int matrix_order, char jobvs, char sort,\n                               LAPACK_C_SELECT1 select, lapack_int n,\n                               lapack_complex_float* a, lapack_int lda,\n                               lapack_int* sdim, lapack_complex_float* w,\n                               lapack_complex_float* vs, lapack_int ldvs,\n                               lapack_complex_float* work, lapack_int lwork,\n                               float* rwork, lapack_logical* bwork );\nlapack_int LAPACKE_zgees_work( int matrix_order, char jobvs, char sort,\n                               LAPACK_Z_SELECT1 select, lapack_int n,\n                               lapack_complex_double* a, lapack_int lda,\n                               lapack_int* sdim, lapack_complex_double* w,\n                               lapack_complex_double* vs, lapack_int ldvs,\n                               lapack_complex_double* work, lapack_int lwork,\n                               double* rwork, lapack_logical* bwork );\n\nlapack_int LAPACKE_sgeesx_work( int matrix_order, char jobvs, char sort,\n                                LAPACK_S_SELECT2 select, char sense,\n                                lapack_int n, float* a, lapack_int lda,\n                                lapack_int* sdim, float* wr, float* wi,\n                                float* vs, lapack_int ldvs, float* rconde,\n                                float* rcondv, float* work, lapack_int lwork,\n                                lapack_int* iwork, lapack_int liwork,\n                                lapack_logical* bwork );\nlapack_int LAPACKE_dgeesx_work( int matrix_order, char jobvs, char sort,\n                                LAPACK_D_SELECT2 select, char sense,\n                                lapack_int n, double* a, lapack_int lda,\n                                lapack_int* sdim, double* wr, double* wi,\n                                double* vs, lapack_int ldvs, double* rconde,\n                                double* rcondv, double* work, lapack_int lwork,\n                                lapack_int* iwork, lapack_int liwork,\n                                lapack_logical* bwork );\nlapack_int LAPACKE_cgeesx_work( int matrix_order, char jobvs, char sort,\n                                LAPACK_C_SELECT1 select, char sense,\n                                lapack_int n, lapack_complex_float* a,\n                                lapack_int lda, lapack_int* sdim,\n                                lapack_complex_float* w,\n                                lapack_complex_float* vs, lapack_int ldvs,\n                                float* rconde, float* rcondv,\n                                lapack_complex_float* work, lapack_int lwork,\n                                float* rwork, lapack_logical* bwork );\nlapack_int LAPACKE_zgeesx_work( int matrix_order, char jobvs, char sort,\n                                LAPACK_Z_SELECT1 select, char sense,\n                                lapack_int n, lapack_complex_double* a,\n                                lapack_int lda, lapack_int* sdim,\n                                lapack_complex_double* w,\n                                lapack_complex_double* vs, lapack_int ldvs,\n                                double* rconde, double* rcondv,\n                                lapack_complex_double* work, lapack_int lwork,\n                                double* rwork, lapack_logical* bwork );\n\nlapack_int LAPACKE_sgeev_work( int matrix_order, char jobvl, char jobvr,\n                               lapack_int n, float* a, lapack_int lda,\n                               float* wr, float* wi, float* vl, lapack_int ldvl,\n                               float* vr, lapack_int ldvr, float* work,\n                               lapack_int lwork );\nlapack_int LAPACKE_dgeev_work( int matrix_order, char jobvl, char jobvr,\n                               lapack_int n, double* a, lapack_int lda,\n                               double* wr, double* wi, double* vl,\n                               lapack_int ldvl, double* vr, lapack_int ldvr,\n                               double* work, lapack_int lwork );\nlapack_int LAPACKE_cgeev_work( int matrix_order, char jobvl, char jobvr,\n                               lapack_int n, lapack_complex_float* a,\n                               lapack_int lda, lapack_complex_float* w,\n                               lapack_complex_float* vl, lapack_int ldvl,\n                               lapack_complex_float* vr, lapack_int ldvr,\n                               lapack_complex_float* work, lapack_int lwork,\n                               float* rwork );\nlapack_int LAPACKE_zgeev_work( int matrix_order, char jobvl, char jobvr,\n                               lapack_int n, lapack_complex_double* a,\n                               lapack_int lda, lapack_complex_double* w,\n                               lapack_complex_double* vl, lapack_int ldvl,\n                               lapack_complex_double* vr, lapack_int ldvr,\n                               lapack_complex_double* work, lapack_int lwork,\n                               double* rwork );\n\nlapack_int LAPACKE_sgeevx_work( int matrix_order, char balanc, char jobvl,\n                                char jobvr, char sense, lapack_int n, float* a,\n                                lapack_int lda, float* wr, float* wi, float* vl,\n                                lapack_int ldvl, float* vr, lapack_int ldvr,\n                                lapack_int* ilo, lapack_int* ihi, float* scale,\n                                float* abnrm, float* rconde, float* rcondv,\n                                float* work, lapack_int lwork,\n                                lapack_int* iwork );\nlapack_int LAPACKE_dgeevx_work( int matrix_order, char balanc, char jobvl,\n                                char jobvr, char sense, lapack_int n, double* a,\n                                lapack_int lda, double* wr, double* wi,\n                                double* vl, lapack_int ldvl, double* vr,\n                                lapack_int ldvr, lapack_int* ilo,\n                                lapack_int* ihi, double* scale, double* abnrm,\n                                double* rconde, double* rcondv, double* work,\n                                lapack_int lwork, lapack_int* iwork );\nlapack_int LAPACKE_cgeevx_work( int matrix_order, char balanc, char jobvl,\n                                char jobvr, char sense, lapack_int n,\n                                lapack_complex_float* a, lapack_int lda,\n                                lapack_complex_float* w,\n                                lapack_complex_float* vl, lapack_int ldvl,\n                                lapack_complex_float* vr, lapack_int ldvr,\n                                lapack_int* ilo, lapack_int* ihi, float* scale,\n                                float* abnrm, float* rconde, float* rcondv,\n                                lapack_complex_float* work, lapack_int lwork,\n                                float* rwork );\nlapack_int LAPACKE_zgeevx_work( int matrix_order, char balanc, char jobvl,\n                                char jobvr, char sense, lapack_int n,\n                                lapack_complex_double* a, lapack_int lda,\n                                lapack_complex_double* w,\n                                lapack_complex_double* vl, lapack_int ldvl,\n                                lapack_complex_double* vr, lapack_int ldvr,\n                                lapack_int* ilo, lapack_int* ihi, double* scale,\n                                double* abnrm, double* rconde, double* rcondv,\n                                lapack_complex_double* work, lapack_int lwork,\n                                double* rwork );\n\nlapack_int LAPACKE_sgehrd_work( int matrix_order, lapack_int n, lapack_int ilo,\n                                lapack_int ihi, float* a, lapack_int lda,\n                                float* tau, float* work, lapack_int lwork );\nlapack_int LAPACKE_dgehrd_work( int matrix_order, lapack_int n, lapack_int ilo,\n                                lapack_int ihi, double* a, lapack_int lda,\n                                double* tau, double* work, lapack_int lwork );\nlapack_int LAPACKE_cgehrd_work( int matrix_order, lapack_int n, lapack_int ilo,\n                                lapack_int ihi, lapack_complex_float* a,\n                                lapack_int lda, lapack_complex_float* tau,\n                                lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_zgehrd_work( int matrix_order, lapack_int n, lapack_int ilo,\n                                lapack_int ihi, lapack_complex_double* a,\n                                lapack_int lda, lapack_complex_double* tau,\n                                lapack_complex_double* work, lapack_int lwork );\n\nlapack_int LAPACKE_sgejsv_work( int matrix_order, char joba, char jobu,\n                                char jobv, char jobr, char jobt, char jobp,\n                                lapack_int m, lapack_int n, float* a,\n                                lapack_int lda, float* sva, float* u,\n                                lapack_int ldu, float* v, lapack_int ldv,\n                                float* work, lapack_int lwork,\n                                lapack_int* iwork );\nlapack_int LAPACKE_dgejsv_work( int matrix_order, char joba, char jobu,\n                                char jobv, char jobr, char jobt, char jobp,\n                                lapack_int m, lapack_int n, double* a,\n                                lapack_int lda, double* sva, double* u,\n                                lapack_int ldu, double* v, lapack_int ldv,\n                                double* work, lapack_int lwork,\n                                lapack_int* iwork );\n\nlapack_int LAPACKE_sgelq2_work( int matrix_order, lapack_int m, lapack_int n,\n                                float* a, lapack_int lda, float* tau,\n                                float* work );\nlapack_int LAPACKE_dgelq2_work( int matrix_order, lapack_int m, lapack_int n,\n                                double* a, lapack_int lda, double* tau,\n                                double* work );\nlapack_int LAPACKE_cgelq2_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_complex_float* a, lapack_int lda,\n                                lapack_complex_float* tau,\n                                lapack_complex_float* work );\nlapack_int LAPACKE_zgelq2_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_complex_double* a, lapack_int lda,\n                                lapack_complex_double* tau,\n                                lapack_complex_double* work );\n\nlapack_int LAPACKE_sgelqf_work( int matrix_order, lapack_int m, lapack_int n,\n                                float* a, lapack_int lda, float* tau,\n                                float* work, lapack_int lwork );\nlapack_int LAPACKE_dgelqf_work( int matrix_order, lapack_int m, lapack_int n,\n                                double* a, lapack_int lda, double* tau,\n                                double* work, lapack_int lwork );\nlapack_int LAPACKE_cgelqf_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_complex_float* a, lapack_int lda,\n                                lapack_complex_float* tau,\n                                lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_zgelqf_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_complex_double* a, lapack_int lda,\n                                lapack_complex_double* tau,\n                                lapack_complex_double* work, lapack_int lwork );\n\nlapack_int LAPACKE_sgels_work( int matrix_order, char trans, lapack_int m,\n                               lapack_int n, lapack_int nrhs, float* a,\n                               lapack_int lda, float* b, lapack_int ldb,\n                               float* work, lapack_int lwork );\nlapack_int LAPACKE_dgels_work( int matrix_order, char trans, lapack_int m,\n                               lapack_int n, lapack_int nrhs, double* a,\n                               lapack_int lda, double* b, lapack_int ldb,\n                               double* work, lapack_int lwork );\nlapack_int LAPACKE_cgels_work( int matrix_order, char trans, lapack_int m,\n                               lapack_int n, lapack_int nrhs,\n                               lapack_complex_float* a, lapack_int lda,\n                               lapack_complex_float* b, lapack_int ldb,\n                               lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_zgels_work( int matrix_order, char trans, lapack_int m,\n                               lapack_int n, lapack_int nrhs,\n                               lapack_complex_double* a, lapack_int lda,\n                               lapack_complex_double* b, lapack_int ldb,\n                               lapack_complex_double* work, lapack_int lwork );\n\nlapack_int LAPACKE_sgelsd_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int nrhs, float* a, lapack_int lda,\n                                float* b, lapack_int ldb, float* s, float rcond,\n                                lapack_int* rank, float* work, lapack_int lwork,\n                                lapack_int* iwork );\nlapack_int LAPACKE_dgelsd_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int nrhs, double* a, lapack_int lda,\n                                double* b, lapack_int ldb, double* s,\n                                double rcond, lapack_int* rank, double* work,\n                                lapack_int lwork, lapack_int* iwork );\nlapack_int LAPACKE_cgelsd_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int nrhs, lapack_complex_float* a,\n                                lapack_int lda, lapack_complex_float* b,\n                                lapack_int ldb, float* s, float rcond,\n                                lapack_int* rank, lapack_complex_float* work,\n                                lapack_int lwork, float* rwork,\n                                lapack_int* iwork );\nlapack_int LAPACKE_zgelsd_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int nrhs, lapack_complex_double* a,\n                                lapack_int lda, lapack_complex_double* b,\n                                lapack_int ldb, double* s, double rcond,\n                                lapack_int* rank, lapack_complex_double* work,\n                                lapack_int lwork, double* rwork,\n                                lapack_int* iwork );\n\nlapack_int LAPACKE_sgelss_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int nrhs, float* a, lapack_int lda,\n                                float* b, lapack_int ldb, float* s, float rcond,\n                                lapack_int* rank, float* work,\n                                lapack_int lwork );\nlapack_int LAPACKE_dgelss_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int nrhs, double* a, lapack_int lda,\n                                double* b, lapack_int ldb, double* s,\n                                double rcond, lapack_int* rank, double* work,\n                                lapack_int lwork );\nlapack_int LAPACKE_cgelss_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int nrhs, lapack_complex_float* a,\n                                lapack_int lda, lapack_complex_float* b,\n                                lapack_int ldb, float* s, float rcond,\n                                lapack_int* rank, lapack_complex_float* work,\n                                lapack_int lwork, float* rwork );\nlapack_int LAPACKE_zgelss_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int nrhs, lapack_complex_double* a,\n                                lapack_int lda, lapack_complex_double* b,\n                                lapack_int ldb, double* s, double rcond,\n                                lapack_int* rank, lapack_complex_double* work,\n                                lapack_int lwork, double* rwork );\n\nlapack_int LAPACKE_sgelsy_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int nrhs, float* a, lapack_int lda,\n                                float* b, lapack_int ldb, lapack_int* jpvt,\n                                float rcond, lapack_int* rank, float* work,\n                                lapack_int lwork );\nlapack_int LAPACKE_dgelsy_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int nrhs, double* a, lapack_int lda,\n                                double* b, lapack_int ldb, lapack_int* jpvt,\n                                double rcond, lapack_int* rank, double* work,\n                                lapack_int lwork );\nlapack_int LAPACKE_cgelsy_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int nrhs, lapack_complex_float* a,\n                                lapack_int lda, lapack_complex_float* b,\n                                lapack_int ldb, lapack_int* jpvt, float rcond,\n                                lapack_int* rank, lapack_complex_float* work,\n                                lapack_int lwork, float* rwork );\nlapack_int LAPACKE_zgelsy_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int nrhs, lapack_complex_double* a,\n                                lapack_int lda, lapack_complex_double* b,\n                                lapack_int ldb, lapack_int* jpvt, double rcond,\n                                lapack_int* rank, lapack_complex_double* work,\n                                lapack_int lwork, double* rwork );\n\nlapack_int LAPACKE_sgeqlf_work( int matrix_order, lapack_int m, lapack_int n,\n                                float* a, lapack_int lda, float* tau,\n                                float* work, lapack_int lwork );\nlapack_int LAPACKE_dgeqlf_work( int matrix_order, lapack_int m, lapack_int n,\n                                double* a, lapack_int lda, double* tau,\n                                double* work, lapack_int lwork );\nlapack_int LAPACKE_cgeqlf_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_complex_float* a, lapack_int lda,\n                                lapack_complex_float* tau,\n                                lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_zgeqlf_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_complex_double* a, lapack_int lda,\n                                lapack_complex_double* tau,\n                                lapack_complex_double* work, lapack_int lwork );\n\nlapack_int LAPACKE_sgeqp3_work( int matrix_order, lapack_int m, lapack_int n,\n                                float* a, lapack_int lda, lapack_int* jpvt,\n                                float* tau, float* work, lapack_int lwork );\nlapack_int LAPACKE_dgeqp3_work( int matrix_order, lapack_int m, lapack_int n,\n                                double* a, lapack_int lda, lapack_int* jpvt,\n                                double* tau, double* work, lapack_int lwork );\nlapack_int LAPACKE_cgeqp3_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_complex_float* a, lapack_int lda,\n                                lapack_int* jpvt, lapack_complex_float* tau,\n                                lapack_complex_float* work, lapack_int lwork,\n                                float* rwork );\nlapack_int LAPACKE_zgeqp3_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_complex_double* a, lapack_int lda,\n                                lapack_int* jpvt, lapack_complex_double* tau,\n                                lapack_complex_double* work, lapack_int lwork,\n                                double* rwork );\n\nlapack_int LAPACKE_sgeqpf_work( int matrix_order, lapack_int m, lapack_int n,\n                                float* a, lapack_int lda, lapack_int* jpvt,\n                                float* tau, float* work );\nlapack_int LAPACKE_dgeqpf_work( int matrix_order, lapack_int m, lapack_int n,\n                                double* a, lapack_int lda, lapack_int* jpvt,\n                                double* tau, double* work );\nlapack_int LAPACKE_cgeqpf_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_complex_float* a, lapack_int lda,\n                                lapack_int* jpvt, lapack_complex_float* tau,\n                                lapack_complex_float* work, float* rwork );\nlapack_int LAPACKE_zgeqpf_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_complex_double* a, lapack_int lda,\n                                lapack_int* jpvt, lapack_complex_double* tau,\n                                lapack_complex_double* work, double* rwork );\n\nlapack_int LAPACKE_sgeqr2_work( int matrix_order, lapack_int m, lapack_int n,\n                                float* a, lapack_int lda, float* tau,\n                                float* work );\nlapack_int LAPACKE_dgeqr2_work( int matrix_order, lapack_int m, lapack_int n,\n                                double* a, lapack_int lda, double* tau,\n                                double* work );\nlapack_int LAPACKE_cgeqr2_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_complex_float* a, lapack_int lda,\n                                lapack_complex_float* tau,\n                                lapack_complex_float* work );\nlapack_int LAPACKE_zgeqr2_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_complex_double* a, lapack_int lda,\n                                lapack_complex_double* tau,\n                                lapack_complex_double* work );\n\nlapack_int LAPACKE_sgeqrf_work( int matrix_order, lapack_int m, lapack_int n,\n                                float* a, lapack_int lda, float* tau,\n                                float* work, lapack_int lwork );\nlapack_int LAPACKE_dgeqrf_work( int matrix_order, lapack_int m, lapack_int n,\n                                double* a, lapack_int lda, double* tau,\n                                double* work, lapack_int lwork );\nlapack_int LAPACKE_cgeqrf_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_complex_float* a, lapack_int lda,\n                                lapack_complex_float* tau,\n                                lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_zgeqrf_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_complex_double* a, lapack_int lda,\n                                lapack_complex_double* tau,\n                                lapack_complex_double* work, lapack_int lwork );\n\nlapack_int LAPACKE_sgeqrfp_work( int matrix_order, lapack_int m, lapack_int n,\n                                 float* a, lapack_int lda, float* tau,\n                                 float* work, lapack_int lwork );\nlapack_int LAPACKE_dgeqrfp_work( int matrix_order, lapack_int m, lapack_int n,\n                                 double* a, lapack_int lda, double* tau,\n                                 double* work, lapack_int lwork );\nlapack_int LAPACKE_cgeqrfp_work( int matrix_order, lapack_int m, lapack_int n,\n                                 lapack_complex_float* a, lapack_int lda,\n                                 lapack_complex_float* tau,\n                                 lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_zgeqrfp_work( int matrix_order, lapack_int m, lapack_int n,\n                                 lapack_complex_double* a, lapack_int lda,\n                                 lapack_complex_double* tau,\n                                 lapack_complex_double* work,\n                                 lapack_int lwork );\n\nlapack_int LAPACKE_sgerfs_work( int matrix_order, char trans, lapack_int n,\n                                lapack_int nrhs, const float* a, lapack_int lda,\n                                const float* af, lapack_int ldaf,\n                                const lapack_int* ipiv, const float* b,\n                                lapack_int ldb, float* x, lapack_int ldx,\n                                float* ferr, float* berr, float* work,\n                                lapack_int* iwork );\nlapack_int LAPACKE_dgerfs_work( int matrix_order, char trans, lapack_int n,\n                                lapack_int nrhs, const double* a,\n                                lapack_int lda, const double* af,\n                                lapack_int ldaf, const lapack_int* ipiv,\n                                const double* b, lapack_int ldb, double* x,\n                                lapack_int ldx, double* ferr, double* berr,\n                                double* work, lapack_int* iwork );\nlapack_int LAPACKE_cgerfs_work( int matrix_order, char trans, lapack_int n,\n                                lapack_int nrhs, const lapack_complex_float* a,\n                                lapack_int lda, const lapack_complex_float* af,\n                                lapack_int ldaf, const lapack_int* ipiv,\n                                const lapack_complex_float* b, lapack_int ldb,\n                                lapack_complex_float* x, lapack_int ldx,\n                                float* ferr, float* berr,\n                                lapack_complex_float* work, float* rwork );\nlapack_int LAPACKE_zgerfs_work( int matrix_order, char trans, lapack_int n,\n                                lapack_int nrhs, const lapack_complex_double* a,\n                                lapack_int lda, const lapack_complex_double* af,\n                                lapack_int ldaf, const lapack_int* ipiv,\n                                const lapack_complex_double* b, lapack_int ldb,\n                                lapack_complex_double* x, lapack_int ldx,\n                                double* ferr, double* berr,\n                                lapack_complex_double* work, double* rwork );\n\nlapack_int LAPACKE_sgerfsx_work( int matrix_order, char trans, char equed,\n                                 lapack_int n, lapack_int nrhs, const float* a,\n                                 lapack_int lda, const float* af,\n                                 lapack_int ldaf, const lapack_int* ipiv,\n                                 const float* r, const float* c, const float* b,\n                                 lapack_int ldb, float* x, lapack_int ldx,\n                                 float* rcond, float* berr,\n                                 lapack_int n_err_bnds, float* err_bnds_norm,\n                                 float* err_bnds_comp, lapack_int nparams,\n                                 float* params, float* work,\n                                 lapack_int* iwork );\nlapack_int LAPACKE_dgerfsx_work( int matrix_order, char trans, char equed,\n                                 lapack_int n, lapack_int nrhs, const double* a,\n                                 lapack_int lda, const double* af,\n                                 lapack_int ldaf, const lapack_int* ipiv,\n                                 const double* r, const double* c,\n                                 const double* b, lapack_int ldb, double* x,\n                                 lapack_int ldx, double* rcond, double* berr,\n                                 lapack_int n_err_bnds, double* err_bnds_norm,\n                                 double* err_bnds_comp, lapack_int nparams,\n                                 double* params, double* work,\n                                 lapack_int* iwork );\nlapack_int LAPACKE_cgerfsx_work( int matrix_order, char trans, char equed,\n                                 lapack_int n, lapack_int nrhs,\n                                 const lapack_complex_float* a, lapack_int lda,\n                                 const lapack_complex_float* af,\n                                 lapack_int ldaf, const lapack_int* ipiv,\n                                 const float* r, const float* c,\n                                 const lapack_complex_float* b, lapack_int ldb,\n                                 lapack_complex_float* x, lapack_int ldx,\n                                 float* rcond, float* berr,\n                                 lapack_int n_err_bnds, float* err_bnds_norm,\n                                 float* err_bnds_comp, lapack_int nparams,\n                                 float* params, lapack_complex_float* work,\n                                 float* rwork );\nlapack_int LAPACKE_zgerfsx_work( int matrix_order, char trans, char equed,\n                                 lapack_int n, lapack_int nrhs,\n                                 const lapack_complex_double* a, lapack_int lda,\n                                 const lapack_complex_double* af,\n                                 lapack_int ldaf, const lapack_int* ipiv,\n                                 const double* r, const double* c,\n                                 const lapack_complex_double* b, lapack_int ldb,\n                                 lapack_complex_double* x, lapack_int ldx,\n                                 double* rcond, double* berr,\n                                 lapack_int n_err_bnds, double* err_bnds_norm,\n                                 double* err_bnds_comp, lapack_int nparams,\n                                 double* params, lapack_complex_double* work,\n                                 double* rwork );\n\nlapack_int LAPACKE_sgerqf_work( int matrix_order, lapack_int m, lapack_int n,\n                                float* a, lapack_int lda, float* tau,\n                                float* work, lapack_int lwork );\nlapack_int LAPACKE_dgerqf_work( int matrix_order, lapack_int m, lapack_int n,\n                                double* a, lapack_int lda, double* tau,\n                                double* work, lapack_int lwork );\nlapack_int LAPACKE_cgerqf_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_complex_float* a, lapack_int lda,\n                                lapack_complex_float* tau,\n                                lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_zgerqf_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_complex_double* a, lapack_int lda,\n                                lapack_complex_double* tau,\n                                lapack_complex_double* work, lapack_int lwork );\n\nlapack_int LAPACKE_sgesdd_work( int matrix_order, char jobz, lapack_int m,\n                                lapack_int n, float* a, lapack_int lda,\n                                float* s, float* u, lapack_int ldu, float* vt,\n                                lapack_int ldvt, float* work, lapack_int lwork,\n                                lapack_int* iwork );\nlapack_int LAPACKE_dgesdd_work( int matrix_order, char jobz, lapack_int m,\n                                lapack_int n, double* a, lapack_int lda,\n                                double* s, double* u, lapack_int ldu,\n                                double* vt, lapack_int ldvt, double* work,\n                                lapack_int lwork, lapack_int* iwork );\nlapack_int LAPACKE_cgesdd_work( int matrix_order, char jobz, lapack_int m,\n                                lapack_int n, lapack_complex_float* a,\n                                lapack_int lda, float* s,\n                                lapack_complex_float* u, lapack_int ldu,\n                                lapack_complex_float* vt, lapack_int ldvt,\n                                lapack_complex_float* work, lapack_int lwork,\n                                float* rwork, lapack_int* iwork );\nlapack_int LAPACKE_zgesdd_work( int matrix_order, char jobz, lapack_int m,\n                                lapack_int n, lapack_complex_double* a,\n                                lapack_int lda, double* s,\n                                lapack_complex_double* u, lapack_int ldu,\n                                lapack_complex_double* vt, lapack_int ldvt,\n                                lapack_complex_double* work, lapack_int lwork,\n                                double* rwork, lapack_int* iwork );\n\nlapack_int LAPACKE_sgesv_work( int matrix_order, lapack_int n, lapack_int nrhs,\n                               float* a, lapack_int lda, lapack_int* ipiv,\n                               float* b, lapack_int ldb );\nlapack_int LAPACKE_dgesv_work( int matrix_order, lapack_int n, lapack_int nrhs,\n                               double* a, lapack_int lda, lapack_int* ipiv,\n                               double* b, lapack_int ldb );\nlapack_int LAPACKE_cgesv_work( int matrix_order, lapack_int n, lapack_int nrhs,\n                               lapack_complex_float* a, lapack_int lda,\n                               lapack_int* ipiv, lapack_complex_float* b,\n                               lapack_int ldb );\nlapack_int LAPACKE_zgesv_work( int matrix_order, lapack_int n, lapack_int nrhs,\n                               lapack_complex_double* a, lapack_int lda,\n                               lapack_int* ipiv, lapack_complex_double* b,\n                               lapack_int ldb );\nlapack_int LAPACKE_dsgesv_work( int matrix_order, lapack_int n, lapack_int nrhs,\n                                double* a, lapack_int lda, lapack_int* ipiv,\n                                double* b, lapack_int ldb, double* x,\n                                lapack_int ldx, double* work, float* swork,\n                                lapack_int* iter );\nlapack_int LAPACKE_zcgesv_work( int matrix_order, lapack_int n, lapack_int nrhs,\n                                lapack_complex_double* a, lapack_int lda,\n                                lapack_int* ipiv, lapack_complex_double* b,\n                                lapack_int ldb, lapack_complex_double* x,\n                                lapack_int ldx, lapack_complex_double* work,\n                                lapack_complex_float* swork, double* rwork,\n                                lapack_int* iter );\n\nlapack_int LAPACKE_sgesvd_work( int matrix_order, char jobu, char jobvt,\n                                lapack_int m, lapack_int n, float* a,\n                                lapack_int lda, float* s, float* u,\n                                lapack_int ldu, float* vt, lapack_int ldvt,\n                                float* work, lapack_int lwork );\nlapack_int LAPACKE_dgesvd_work( int matrix_order, char jobu, char jobvt,\n                                lapack_int m, lapack_int n, double* a,\n                                lapack_int lda, double* s, double* u,\n                                lapack_int ldu, double* vt, lapack_int ldvt,\n                                double* work, lapack_int lwork );\nlapack_int LAPACKE_cgesvd_work( int matrix_order, char jobu, char jobvt,\n                                lapack_int m, lapack_int n,\n                                lapack_complex_float* a, lapack_int lda,\n                                float* s, lapack_complex_float* u,\n                                lapack_int ldu, lapack_complex_float* vt,\n                                lapack_int ldvt, lapack_complex_float* work,\n                                lapack_int lwork, float* rwork );\nlapack_int LAPACKE_zgesvd_work( int matrix_order, char jobu, char jobvt,\n                                lapack_int m, lapack_int n,\n                                lapack_complex_double* a, lapack_int lda,\n                                double* s, lapack_complex_double* u,\n                                lapack_int ldu, lapack_complex_double* vt,\n                                lapack_int ldvt, lapack_complex_double* work,\n                                lapack_int lwork, double* rwork );\n\nlapack_int LAPACKE_sgesvj_work( int matrix_order, char joba, char jobu,\n                                char jobv, lapack_int m, lapack_int n, float* a,\n                                lapack_int lda, float* sva, lapack_int mv,\n                                float* v, lapack_int ldv, float* work,\n                                lapack_int lwork );\nlapack_int LAPACKE_dgesvj_work( int matrix_order, char joba, char jobu,\n                                char jobv, lapack_int m, lapack_int n,\n                                double* a, lapack_int lda, double* sva,\n                                lapack_int mv, double* v, lapack_int ldv,\n                                double* work, lapack_int lwork );\n\nlapack_int LAPACKE_sgesvx_work( int matrix_order, char fact, char trans,\n                                lapack_int n, lapack_int nrhs, float* a,\n                                lapack_int lda, float* af, lapack_int ldaf,\n                                lapack_int* ipiv, char* equed, float* r,\n                                float* c, float* b, lapack_int ldb, float* x,\n                                lapack_int ldx, float* rcond, float* ferr,\n                                float* berr, float* work, lapack_int* iwork );\nlapack_int LAPACKE_dgesvx_work( int matrix_order, char fact, char trans,\n                                lapack_int n, lapack_int nrhs, double* a,\n                                lapack_int lda, double* af, lapack_int ldaf,\n                                lapack_int* ipiv, char* equed, double* r,\n                                double* c, double* b, lapack_int ldb, double* x,\n                                lapack_int ldx, double* rcond, double* ferr,\n                                double* berr, double* work, lapack_int* iwork );\nlapack_int LAPACKE_cgesvx_work( int matrix_order, char fact, char trans,\n                                lapack_int n, lapack_int nrhs,\n                                lapack_complex_float* a, lapack_int lda,\n                                lapack_complex_float* af, lapack_int ldaf,\n                                lapack_int* ipiv, char* equed, float* r,\n                                float* c, lapack_complex_float* b,\n                                lapack_int ldb, lapack_complex_float* x,\n                                lapack_int ldx, float* rcond, float* ferr,\n                                float* berr, lapack_complex_float* work,\n                                float* rwork );\nlapack_int LAPACKE_zgesvx_work( int matrix_order, char fact, char trans,\n                                lapack_int n, lapack_int nrhs,\n                                lapack_complex_double* a, lapack_int lda,\n                                lapack_complex_double* af, lapack_int ldaf,\n                                lapack_int* ipiv, char* equed, double* r,\n                                double* c, lapack_complex_double* b,\n                                lapack_int ldb, lapack_complex_double* x,\n                                lapack_int ldx, double* rcond, double* ferr,\n                                double* berr, lapack_complex_double* work,\n                                double* rwork );\n\nlapack_int LAPACKE_sgesvxx_work( int matrix_order, char fact, char trans,\n                                 lapack_int n, lapack_int nrhs, float* a,\n                                 lapack_int lda, float* af, lapack_int ldaf,\n                                 lapack_int* ipiv, char* equed, float* r,\n                                 float* c, float* b, lapack_int ldb, float* x,\n                                 lapack_int ldx, float* rcond, float* rpvgrw,\n                                 float* berr, lapack_int n_err_bnds,\n                                 float* err_bnds_norm, float* err_bnds_comp,\n                                 lapack_int nparams, float* params, float* work,\n                                 lapack_int* iwork );\nlapack_int LAPACKE_dgesvxx_work( int matrix_order, char fact, char trans,\n                                 lapack_int n, lapack_int nrhs, double* a,\n                                 lapack_int lda, double* af, lapack_int ldaf,\n                                 lapack_int* ipiv, char* equed, double* r,\n                                 double* c, double* b, lapack_int ldb,\n                                 double* x, lapack_int ldx, double* rcond,\n                                 double* rpvgrw, double* berr,\n                                 lapack_int n_err_bnds, double* err_bnds_norm,\n                                 double* err_bnds_comp, lapack_int nparams,\n                                 double* params, double* work,\n                                 lapack_int* iwork );\nlapack_int LAPACKE_cgesvxx_work( int matrix_order, char fact, char trans,\n                                 lapack_int n, lapack_int nrhs,\n                                 lapack_complex_float* a, lapack_int lda,\n                                 lapack_complex_float* af, lapack_int ldaf,\n                                 lapack_int* ipiv, char* equed, float* r,\n                                 float* c, lapack_complex_float* b,\n                                 lapack_int ldb, lapack_complex_float* x,\n                                 lapack_int ldx, float* rcond, float* rpvgrw,\n                                 float* berr, lapack_int n_err_bnds,\n                                 float* err_bnds_norm, float* err_bnds_comp,\n                                 lapack_int nparams, float* params,\n                                 lapack_complex_float* work, float* rwork );\nlapack_int LAPACKE_zgesvxx_work( int matrix_order, char fact, char trans,\n                                 lapack_int n, lapack_int nrhs,\n                                 lapack_complex_double* a, lapack_int lda,\n                                 lapack_complex_double* af, lapack_int ldaf,\n                                 lapack_int* ipiv, char* equed, double* r,\n                                 double* c, lapack_complex_double* b,\n                                 lapack_int ldb, lapack_complex_double* x,\n                                 lapack_int ldx, double* rcond, double* rpvgrw,\n                                 double* berr, lapack_int n_err_bnds,\n                                 double* err_bnds_norm, double* err_bnds_comp,\n                                 lapack_int nparams, double* params,\n                                 lapack_complex_double* work, double* rwork );\n\nlapack_int LAPACKE_sgetf2_work( int matrix_order, lapack_int m, lapack_int n,\n                                float* a, lapack_int lda, lapack_int* ipiv );\nlapack_int LAPACKE_dgetf2_work( int matrix_order, lapack_int m, lapack_int n,\n                                double* a, lapack_int lda, lapack_int* ipiv );\nlapack_int LAPACKE_cgetf2_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_complex_float* a, lapack_int lda,\n                                lapack_int* ipiv );\nlapack_int LAPACKE_zgetf2_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_complex_double* a, lapack_int lda,\n                                lapack_int* ipiv );\n\nlapack_int LAPACKE_sgetrf_work( int matrix_order, lapack_int m, lapack_int n,\n                                float* a, lapack_int lda, lapack_int* ipiv );\nlapack_int LAPACKE_dgetrf_work( int matrix_order, lapack_int m, lapack_int n,\n                                double* a, lapack_int lda, lapack_int* ipiv );\nlapack_int LAPACKE_cgetrf_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_complex_float* a, lapack_int lda,\n                                lapack_int* ipiv );\nlapack_int LAPACKE_zgetrf_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_complex_double* a, lapack_int lda,\n                                lapack_int* ipiv );\n\nlapack_int LAPACKE_sgetri_work( int matrix_order, lapack_int n, float* a,\n                                lapack_int lda, const lapack_int* ipiv,\n                                float* work, lapack_int lwork );\nlapack_int LAPACKE_dgetri_work( int matrix_order, lapack_int n, double* a,\n                                lapack_int lda, const lapack_int* ipiv,\n                                double* work, lapack_int lwork );\nlapack_int LAPACKE_cgetri_work( int matrix_order, lapack_int n,\n                                lapack_complex_float* a, lapack_int lda,\n                                const lapack_int* ipiv,\n                                lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_zgetri_work( int matrix_order, lapack_int n,\n                                lapack_complex_double* a, lapack_int lda,\n                                const lapack_int* ipiv,\n                                lapack_complex_double* work, lapack_int lwork );\n\nlapack_int LAPACKE_sgetrs_work( int matrix_order, char trans, lapack_int n,\n                                lapack_int nrhs, const float* a, lapack_int lda,\n                                const lapack_int* ipiv, float* b,\n                                lapack_int ldb );\nlapack_int LAPACKE_dgetrs_work( int matrix_order, char trans, lapack_int n,\n                                lapack_int nrhs, const double* a,\n                                lapack_int lda, const lapack_int* ipiv,\n                                double* b, lapack_int ldb );\nlapack_int LAPACKE_cgetrs_work( int matrix_order, char trans, lapack_int n,\n                                lapack_int nrhs, const lapack_complex_float* a,\n                                lapack_int lda, const lapack_int* ipiv,\n                                lapack_complex_float* b, lapack_int ldb );\nlapack_int LAPACKE_zgetrs_work( int matrix_order, char trans, lapack_int n,\n                                lapack_int nrhs, const lapack_complex_double* a,\n                                lapack_int lda, const lapack_int* ipiv,\n                                lapack_complex_double* b, lapack_int ldb );\n\nlapack_int LAPACKE_sggbak_work( int matrix_order, char job, char side,\n                                lapack_int n, lapack_int ilo, lapack_int ihi,\n                                const float* lscale, const float* rscale,\n                                lapack_int m, float* v, lapack_int ldv );\nlapack_int LAPACKE_dggbak_work( int matrix_order, char job, char side,\n                                lapack_int n, lapack_int ilo, lapack_int ihi,\n                                const double* lscale, const double* rscale,\n                                lapack_int m, double* v, lapack_int ldv );\nlapack_int LAPACKE_cggbak_work( int matrix_order, char job, char side,\n                                lapack_int n, lapack_int ilo, lapack_int ihi,\n                                const float* lscale, const float* rscale,\n                                lapack_int m, lapack_complex_float* v,\n                                lapack_int ldv );\nlapack_int LAPACKE_zggbak_work( int matrix_order, char job, char side,\n                                lapack_int n, lapack_int ilo, lapack_int ihi,\n                                const double* lscale, const double* rscale,\n                                lapack_int m, lapack_complex_double* v,\n                                lapack_int ldv );\n\nlapack_int LAPACKE_sggbal_work( int matrix_order, char job, lapack_int n,\n                                float* a, lapack_int lda, float* b,\n                                lapack_int ldb, lapack_int* ilo,\n                                lapack_int* ihi, float* lscale, float* rscale,\n                                float* work );\nlapack_int LAPACKE_dggbal_work( int matrix_order, char job, lapack_int n,\n                                double* a, lapack_int lda, double* b,\n                                lapack_int ldb, lapack_int* ilo,\n                                lapack_int* ihi, double* lscale, double* rscale,\n                                double* work );\nlapack_int LAPACKE_cggbal_work( int matrix_order, char job, lapack_int n,\n                                lapack_complex_float* a, lapack_int lda,\n                                lapack_complex_float* b, lapack_int ldb,\n                                lapack_int* ilo, lapack_int* ihi, float* lscale,\n                                float* rscale, float* work );\nlapack_int LAPACKE_zggbal_work( int matrix_order, char job, lapack_int n,\n                                lapack_complex_double* a, lapack_int lda,\n                                lapack_complex_double* b, lapack_int ldb,\n                                lapack_int* ilo, lapack_int* ihi,\n                                double* lscale, double* rscale, double* work );\n\nlapack_int LAPACKE_sgges_work( int matrix_order, char jobvsl, char jobvsr,\n                               char sort, LAPACK_S_SELECT3 selctg, lapack_int n,\n                               float* a, lapack_int lda, float* b,\n                               lapack_int ldb, lapack_int* sdim, float* alphar,\n                               float* alphai, float* beta, float* vsl,\n                               lapack_int ldvsl, float* vsr, lapack_int ldvsr,\n                               float* work, lapack_int lwork,\n                               lapack_logical* bwork );\nlapack_int LAPACKE_dgges_work( int matrix_order, char jobvsl, char jobvsr,\n                               char sort, LAPACK_D_SELECT3 selctg, lapack_int n,\n                               double* a, lapack_int lda, double* b,\n                               lapack_int ldb, lapack_int* sdim, double* alphar,\n                               double* alphai, double* beta, double* vsl,\n                               lapack_int ldvsl, double* vsr, lapack_int ldvsr,\n                               double* work, lapack_int lwork,\n                               lapack_logical* bwork );\nlapack_int LAPACKE_cgges_work( int matrix_order, char jobvsl, char jobvsr,\n                               char sort, LAPACK_C_SELECT2 selctg, lapack_int n,\n                               lapack_complex_float* a, lapack_int lda,\n                               lapack_complex_float* b, lapack_int ldb,\n                               lapack_int* sdim, lapack_complex_float* alpha,\n                               lapack_complex_float* beta,\n                               lapack_complex_float* vsl, lapack_int ldvsl,\n                               lapack_complex_float* vsr, lapack_int ldvsr,\n                               lapack_complex_float* work, lapack_int lwork,\n                               float* rwork, lapack_logical* bwork );\nlapack_int LAPACKE_zgges_work( int matrix_order, char jobvsl, char jobvsr,\n                               char sort, LAPACK_Z_SELECT2 selctg, lapack_int n,\n                               lapack_complex_double* a, lapack_int lda,\n                               lapack_complex_double* b, lapack_int ldb,\n                               lapack_int* sdim, lapack_complex_double* alpha,\n                               lapack_complex_double* beta,\n                               lapack_complex_double* vsl, lapack_int ldvsl,\n                               lapack_complex_double* vsr, lapack_int ldvsr,\n                               lapack_complex_double* work, lapack_int lwork,\n                               double* rwork, lapack_logical* bwork );\n\nlapack_int LAPACKE_sggesx_work( int matrix_order, char jobvsl, char jobvsr,\n                                char sort, LAPACK_S_SELECT3 selctg, char sense,\n                                lapack_int n, float* a, lapack_int lda,\n                                float* b, lapack_int ldb, lapack_int* sdim,\n                                float* alphar, float* alphai, float* beta,\n                                float* vsl, lapack_int ldvsl, float* vsr,\n                                lapack_int ldvsr, float* rconde, float* rcondv,\n                                float* work, lapack_int lwork,\n                                lapack_int* iwork, lapack_int liwork,\n                                lapack_logical* bwork );\nlapack_int LAPACKE_dggesx_work( int matrix_order, char jobvsl, char jobvsr,\n                                char sort, LAPACK_D_SELECT3 selctg, char sense,\n                                lapack_int n, double* a, lapack_int lda,\n                                double* b, lapack_int ldb, lapack_int* sdim,\n                                double* alphar, double* alphai, double* beta,\n                                double* vsl, lapack_int ldvsl, double* vsr,\n                                lapack_int ldvsr, double* rconde,\n                                double* rcondv, double* work, lapack_int lwork,\n                                lapack_int* iwork, lapack_int liwork,\n                                lapack_logical* bwork );\nlapack_int LAPACKE_cggesx_work( int matrix_order, char jobvsl, char jobvsr,\n                                char sort, LAPACK_C_SELECT2 selctg, char sense,\n                                lapack_int n, lapack_complex_float* a,\n                                lapack_int lda, lapack_complex_float* b,\n                                lapack_int ldb, lapack_int* sdim,\n                                lapack_complex_float* alpha,\n                                lapack_complex_float* beta,\n                                lapack_complex_float* vsl, lapack_int ldvsl,\n                                lapack_complex_float* vsr, lapack_int ldvsr,\n                                float* rconde, float* rcondv,\n                                lapack_complex_float* work, lapack_int lwork,\n                                float* rwork, lapack_int* iwork,\n                                lapack_int liwork, lapack_logical* bwork );\nlapack_int LAPACKE_zggesx_work( int matrix_order, char jobvsl, char jobvsr,\n                                char sort, LAPACK_Z_SELECT2 selctg, char sense,\n                                lapack_int n, lapack_complex_double* a,\n                                lapack_int lda, lapack_complex_double* b,\n                                lapack_int ldb, lapack_int* sdim,\n                                lapack_complex_double* alpha,\n                                lapack_complex_double* beta,\n                                lapack_complex_double* vsl, lapack_int ldvsl,\n                                lapack_complex_double* vsr, lapack_int ldvsr,\n                                double* rconde, double* rcondv,\n                                lapack_complex_double* work, lapack_int lwork,\n                                double* rwork, lapack_int* iwork,\n                                lapack_int liwork, lapack_logical* bwork );\n\nlapack_int LAPACKE_sggev_work( int matrix_order, char jobvl, char jobvr,\n                               lapack_int n, float* a, lapack_int lda, float* b,\n                               lapack_int ldb, float* alphar, float* alphai,\n                               float* beta, float* vl, lapack_int ldvl,\n                               float* vr, lapack_int ldvr, float* work,\n                               lapack_int lwork );\nlapack_int LAPACKE_dggev_work( int matrix_order, char jobvl, char jobvr,\n                               lapack_int n, double* a, lapack_int lda,\n                               double* b, lapack_int ldb, double* alphar,\n                               double* alphai, double* beta, double* vl,\n                               lapack_int ldvl, double* vr, lapack_int ldvr,\n                               double* work, lapack_int lwork );\nlapack_int LAPACKE_cggev_work( int matrix_order, char jobvl, char jobvr,\n                               lapack_int n, lapack_complex_float* a,\n                               lapack_int lda, lapack_complex_float* b,\n                               lapack_int ldb, lapack_complex_float* alpha,\n                               lapack_complex_float* beta,\n                               lapack_complex_float* vl, lapack_int ldvl,\n                               lapack_complex_float* vr, lapack_int ldvr,\n                               lapack_complex_float* work, lapack_int lwork,\n                               float* rwork );\nlapack_int LAPACKE_zggev_work( int matrix_order, char jobvl, char jobvr,\n                               lapack_int n, lapack_complex_double* a,\n                               lapack_int lda, lapack_complex_double* b,\n                               lapack_int ldb, lapack_complex_double* alpha,\n                               lapack_complex_double* beta,\n                               lapack_complex_double* vl, lapack_int ldvl,\n                               lapack_complex_double* vr, lapack_int ldvr,\n                               lapack_complex_double* work, lapack_int lwork,\n                               double* rwork );\n\nlapack_int LAPACKE_sggevx_work( int matrix_order, char balanc, char jobvl,\n                                char jobvr, char sense, lapack_int n, float* a,\n                                lapack_int lda, float* b, lapack_int ldb,\n                                float* alphar, float* alphai, float* beta,\n                                float* vl, lapack_int ldvl, float* vr,\n                                lapack_int ldvr, lapack_int* ilo,\n                                lapack_int* ihi, float* lscale, float* rscale,\n                                float* abnrm, float* bbnrm, float* rconde,\n                                float* rcondv, float* work, lapack_int lwork,\n                                lapack_int* iwork, lapack_logical* bwork );\nlapack_int LAPACKE_dggevx_work( int matrix_order, char balanc, char jobvl,\n                                char jobvr, char sense, lapack_int n, double* a,\n                                lapack_int lda, double* b, lapack_int ldb,\n                                double* alphar, double* alphai, double* beta,\n                                double* vl, lapack_int ldvl, double* vr,\n                                lapack_int ldvr, lapack_int* ilo,\n                                lapack_int* ihi, double* lscale, double* rscale,\n                                double* abnrm, double* bbnrm, double* rconde,\n                                double* rcondv, double* work, lapack_int lwork,\n                                lapack_int* iwork, lapack_logical* bwork );\nlapack_int LAPACKE_cggevx_work( int matrix_order, char balanc, char jobvl,\n                                char jobvr, char sense, lapack_int n,\n                                lapack_complex_float* a, lapack_int lda,\n                                lapack_complex_float* b, lapack_int ldb,\n                                lapack_complex_float* alpha,\n                                lapack_complex_float* beta,\n                                lapack_complex_float* vl, lapack_int ldvl,\n                                lapack_complex_float* vr, lapack_int ldvr,\n                                lapack_int* ilo, lapack_int* ihi, float* lscale,\n                                float* rscale, float* abnrm, float* bbnrm,\n                                float* rconde, float* rcondv,\n                                lapack_complex_float* work, lapack_int lwork,\n                                float* rwork, lapack_int* iwork,\n                                lapack_logical* bwork );\nlapack_int LAPACKE_zggevx_work( int matrix_order, char balanc, char jobvl,\n                                char jobvr, char sense, lapack_int n,\n                                lapack_complex_double* a, lapack_int lda,\n                                lapack_complex_double* b, lapack_int ldb,\n                                lapack_complex_double* alpha,\n                                lapack_complex_double* beta,\n                                lapack_complex_double* vl, lapack_int ldvl,\n                                lapack_complex_double* vr, lapack_int ldvr,\n                                lapack_int* ilo, lapack_int* ihi,\n                                double* lscale, double* rscale, double* abnrm,\n                                double* bbnrm, double* rconde, double* rcondv,\n                                lapack_complex_double* work, lapack_int lwork,\n                                double* rwork, lapack_int* iwork,\n                                lapack_logical* bwork );\n\nlapack_int LAPACKE_sggglm_work( int matrix_order, lapack_int n, lapack_int m,\n                                lapack_int p, float* a, lapack_int lda,\n                                float* b, lapack_int ldb, float* d, float* x,\n                                float* y, float* work, lapack_int lwork );\nlapack_int LAPACKE_dggglm_work( int matrix_order, lapack_int n, lapack_int m,\n                                lapack_int p, double* a, lapack_int lda,\n                                double* b, lapack_int ldb, double* d, double* x,\n                                double* y, double* work, lapack_int lwork );\nlapack_int LAPACKE_cggglm_work( int matrix_order, lapack_int n, lapack_int m,\n                                lapack_int p, lapack_complex_float* a,\n                                lapack_int lda, lapack_complex_float* b,\n                                lapack_int ldb, lapack_complex_float* d,\n                                lapack_complex_float* x,\n                                lapack_complex_float* y,\n                                lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_zggglm_work( int matrix_order, lapack_int n, lapack_int m,\n                                lapack_int p, lapack_complex_double* a,\n                                lapack_int lda, lapack_complex_double* b,\n                                lapack_int ldb, lapack_complex_double* d,\n                                lapack_complex_double* x,\n                                lapack_complex_double* y,\n                                lapack_complex_double* work, lapack_int lwork );\n\nlapack_int LAPACKE_sgghrd_work( int matrix_order, char compq, char compz,\n                                lapack_int n, lapack_int ilo, lapack_int ihi,\n                                float* a, lapack_int lda, float* b,\n                                lapack_int ldb, float* q, lapack_int ldq,\n                                float* z, lapack_int ldz );\nlapack_int LAPACKE_dgghrd_work( int matrix_order, char compq, char compz,\n                                lapack_int n, lapack_int ilo, lapack_int ihi,\n                                double* a, lapack_int lda, double* b,\n                                lapack_int ldb, double* q, lapack_int ldq,\n                                double* z, lapack_int ldz );\nlapack_int LAPACKE_cgghrd_work( int matrix_order, char compq, char compz,\n                                lapack_int n, lapack_int ilo, lapack_int ihi,\n                                lapack_complex_float* a, lapack_int lda,\n                                lapack_complex_float* b, lapack_int ldb,\n                                lapack_complex_float* q, lapack_int ldq,\n                                lapack_complex_float* z, lapack_int ldz );\nlapack_int LAPACKE_zgghrd_work( int matrix_order, char compq, char compz,\n                                lapack_int n, lapack_int ilo, lapack_int ihi,\n                                lapack_complex_double* a, lapack_int lda,\n                                lapack_complex_double* b, lapack_int ldb,\n                                lapack_complex_double* q, lapack_int ldq,\n                                lapack_complex_double* z, lapack_int ldz );\n\nlapack_int LAPACKE_sgglse_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int p, float* a, lapack_int lda,\n                                float* b, lapack_int ldb, float* c, float* d,\n                                float* x, float* work, lapack_int lwork );\nlapack_int LAPACKE_dgglse_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int p, double* a, lapack_int lda,\n                                double* b, lapack_int ldb, double* c, double* d,\n                                double* x, double* work, lapack_int lwork );\nlapack_int LAPACKE_cgglse_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int p, lapack_complex_float* a,\n                                lapack_int lda, lapack_complex_float* b,\n                                lapack_int ldb, lapack_complex_float* c,\n                                lapack_complex_float* d,\n                                lapack_complex_float* x,\n                                lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_zgglse_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int p, lapack_complex_double* a,\n                                lapack_int lda, lapack_complex_double* b,\n                                lapack_int ldb, lapack_complex_double* c,\n                                lapack_complex_double* d,\n                                lapack_complex_double* x,\n                                lapack_complex_double* work, lapack_int lwork );\n\nlapack_int LAPACKE_sggqrf_work( int matrix_order, lapack_int n, lapack_int m,\n                                lapack_int p, float* a, lapack_int lda,\n                                float* taua, float* b, lapack_int ldb,\n                                float* taub, float* work, lapack_int lwork );\nlapack_int LAPACKE_dggqrf_work( int matrix_order, lapack_int n, lapack_int m,\n                                lapack_int p, double* a, lapack_int lda,\n                                double* taua, double* b, lapack_int ldb,\n                                double* taub, double* work, lapack_int lwork );\nlapack_int LAPACKE_cggqrf_work( int matrix_order, lapack_int n, lapack_int m,\n                                lapack_int p, lapack_complex_float* a,\n                                lapack_int lda, lapack_complex_float* taua,\n                                lapack_complex_float* b, lapack_int ldb,\n                                lapack_complex_float* taub,\n                                lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_zggqrf_work( int matrix_order, lapack_int n, lapack_int m,\n                                lapack_int p, lapack_complex_double* a,\n                                lapack_int lda, lapack_complex_double* taua,\n                                lapack_complex_double* b, lapack_int ldb,\n                                lapack_complex_double* taub,\n                                lapack_complex_double* work, lapack_int lwork );\n\nlapack_int LAPACKE_sggrqf_work( int matrix_order, lapack_int m, lapack_int p,\n                                lapack_int n, float* a, lapack_int lda,\n                                float* taua, float* b, lapack_int ldb,\n                                float* taub, float* work, lapack_int lwork );\nlapack_int LAPACKE_dggrqf_work( int matrix_order, lapack_int m, lapack_int p,\n                                lapack_int n, double* a, lapack_int lda,\n                                double* taua, double* b, lapack_int ldb,\n                                double* taub, double* work, lapack_int lwork );\nlapack_int LAPACKE_cggrqf_work( int matrix_order, lapack_int m, lapack_int p,\n                                lapack_int n, lapack_complex_float* a,\n                                lapack_int lda, lapack_complex_float* taua,\n                                lapack_complex_float* b, lapack_int ldb,\n                                lapack_complex_float* taub,\n                                lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_zggrqf_work( int matrix_order, lapack_int m, lapack_int p,\n                                lapack_int n, lapack_complex_double* a,\n                                lapack_int lda, lapack_complex_double* taua,\n                                lapack_complex_double* b, lapack_int ldb,\n                                lapack_complex_double* taub,\n                                lapack_complex_double* work, lapack_int lwork );\n\nlapack_int LAPACKE_sggsvd_work( int matrix_order, char jobu, char jobv,\n                                char jobq, lapack_int m, lapack_int n,\n                                lapack_int p, lapack_int* k, lapack_int* l,\n                                float* a, lapack_int lda, float* b,\n                                lapack_int ldb, float* alpha, float* beta,\n                                float* u, lapack_int ldu, float* v,\n                                lapack_int ldv, float* q, lapack_int ldq,\n                                float* work, lapack_int* iwork );\nlapack_int LAPACKE_dggsvd_work( int matrix_order, char jobu, char jobv,\n                                char jobq, lapack_int m, lapack_int n,\n                                lapack_int p, lapack_int* k, lapack_int* l,\n                                double* a, lapack_int lda, double* b,\n                                lapack_int ldb, double* alpha, double* beta,\n                                double* u, lapack_int ldu, double* v,\n                                lapack_int ldv, double* q, lapack_int ldq,\n                                double* work, lapack_int* iwork );\nlapack_int LAPACKE_cggsvd_work( int matrix_order, char jobu, char jobv,\n                                char jobq, lapack_int m, lapack_int n,\n                                lapack_int p, lapack_int* k, lapack_int* l,\n                                lapack_complex_float* a, lapack_int lda,\n                                lapack_complex_float* b, lapack_int ldb,\n                                float* alpha, float* beta,\n                                lapack_complex_float* u, lapack_int ldu,\n                                lapack_complex_float* v, lapack_int ldv,\n                                lapack_complex_float* q, lapack_int ldq,\n                                lapack_complex_float* work, float* rwork,\n                                lapack_int* iwork );\nlapack_int LAPACKE_zggsvd_work( int matrix_order, char jobu, char jobv,\n                                char jobq, lapack_int m, lapack_int n,\n                                lapack_int p, lapack_int* k, lapack_int* l,\n                                lapack_complex_double* a, lapack_int lda,\n                                lapack_complex_double* b, lapack_int ldb,\n                                double* alpha, double* beta,\n                                lapack_complex_double* u, lapack_int ldu,\n                                lapack_complex_double* v, lapack_int ldv,\n                                lapack_complex_double* q, lapack_int ldq,\n                                lapack_complex_double* work, double* rwork,\n                                lapack_int* iwork );\n\nlapack_int LAPACKE_sggsvp_work( int matrix_order, char jobu, char jobv,\n                                char jobq, lapack_int m, lapack_int p,\n                                lapack_int n, float* a, lapack_int lda,\n                                float* b, lapack_int ldb, float tola,\n                                float tolb, lapack_int* k, lapack_int* l,\n                                float* u, lapack_int ldu, float* v,\n                                lapack_int ldv, float* q, lapack_int ldq,\n                                lapack_int* iwork, float* tau, float* work );\nlapack_int LAPACKE_dggsvp_work( int matrix_order, char jobu, char jobv,\n                                char jobq, lapack_int m, lapack_int p,\n                                lapack_int n, double* a, lapack_int lda,\n                                double* b, lapack_int ldb, double tola,\n                                double tolb, lapack_int* k, lapack_int* l,\n                                double* u, lapack_int ldu, double* v,\n                                lapack_int ldv, double* q, lapack_int ldq,\n                                lapack_int* iwork, double* tau, double* work );\nlapack_int LAPACKE_cggsvp_work( int matrix_order, char jobu, char jobv,\n                                char jobq, lapack_int m, lapack_int p,\n                                lapack_int n, lapack_complex_float* a,\n                                lapack_int lda, lapack_complex_float* b,\n                                lapack_int ldb, float tola, float tolb,\n                                lapack_int* k, lapack_int* l,\n                                lapack_complex_float* u, lapack_int ldu,\n                                lapack_complex_float* v, lapack_int ldv,\n                                lapack_complex_float* q, lapack_int ldq,\n                                lapack_int* iwork, float* rwork,\n                                lapack_complex_float* tau,\n                                lapack_complex_float* work );\nlapack_int LAPACKE_zggsvp_work( int matrix_order, char jobu, char jobv,\n                                char jobq, lapack_int m, lapack_int p,\n                                lapack_int n, lapack_complex_double* a,\n                                lapack_int lda, lapack_complex_double* b,\n                                lapack_int ldb, double tola, double tolb,\n                                lapack_int* k, lapack_int* l,\n                                lapack_complex_double* u, lapack_int ldu,\n                                lapack_complex_double* v, lapack_int ldv,\n                                lapack_complex_double* q, lapack_int ldq,\n                                lapack_int* iwork, double* rwork,\n                                lapack_complex_double* tau,\n                                lapack_complex_double* work );\n\nlapack_int LAPACKE_sgtcon_work( char norm, lapack_int n, const float* dl,\n                                const float* d, const float* du,\n                                const float* du2, const lapack_int* ipiv,\n                                float anorm, float* rcond, float* work,\n                                lapack_int* iwork );\nlapack_int LAPACKE_dgtcon_work( char norm, lapack_int n, const double* dl,\n                                const double* d, const double* du,\n                                const double* du2, const lapack_int* ipiv,\n                                double anorm, double* rcond, double* work,\n                                lapack_int* iwork );\nlapack_int LAPACKE_cgtcon_work( char norm, lapack_int n,\n                                const lapack_complex_float* dl,\n                                const lapack_complex_float* d,\n                                const lapack_complex_float* du,\n                                const lapack_complex_float* du2,\n                                const lapack_int* ipiv, float anorm,\n                                float* rcond, lapack_complex_float* work );\nlapack_int LAPACKE_zgtcon_work( char norm, lapack_int n,\n                                const lapack_complex_double* dl,\n                                const lapack_complex_double* d,\n                                const lapack_complex_double* du,\n                                const lapack_complex_double* du2,\n                                const lapack_int* ipiv, double anorm,\n                                double* rcond, lapack_complex_double* work );\n\nlapack_int LAPACKE_sgtrfs_work( int matrix_order, char trans, lapack_int n,\n                                lapack_int nrhs, const float* dl,\n                                const float* d, const float* du,\n                                const float* dlf, const float* df,\n                                const float* duf, const float* du2,\n                                const lapack_int* ipiv, const float* b,\n                                lapack_int ldb, float* x, lapack_int ldx,\n                                float* ferr, float* berr, float* work,\n                                lapack_int* iwork );\nlapack_int LAPACKE_dgtrfs_work( int matrix_order, char trans, lapack_int n,\n                                lapack_int nrhs, const double* dl,\n                                const double* d, const double* du,\n                                const double* dlf, const double* df,\n                                const double* duf, const double* du2,\n                                const lapack_int* ipiv, const double* b,\n                                lapack_int ldb, double* x, lapack_int ldx,\n                                double* ferr, double* berr, double* work,\n                                lapack_int* iwork );\nlapack_int LAPACKE_cgtrfs_work( int matrix_order, char trans, lapack_int n,\n                                lapack_int nrhs, const lapack_complex_float* dl,\n                                const lapack_complex_float* d,\n                                const lapack_complex_float* du,\n                                const lapack_complex_float* dlf,\n                                const lapack_complex_float* df,\n                                const lapack_complex_float* duf,\n                                const lapack_complex_float* du2,\n                                const lapack_int* ipiv,\n                                const lapack_complex_float* b, lapack_int ldb,\n                                lapack_complex_float* x, lapack_int ldx,\n                                float* ferr, float* berr,\n                                lapack_complex_float* work, float* rwork );\nlapack_int LAPACKE_zgtrfs_work( int matrix_order, char trans, lapack_int n,\n                                lapack_int nrhs,\n                                const lapack_complex_double* dl,\n                                const lapack_complex_double* d,\n                                const lapack_complex_double* du,\n                                const lapack_complex_double* dlf,\n                                const lapack_complex_double* df,\n                                const lapack_complex_double* duf,\n                                const lapack_complex_double* du2,\n                                const lapack_int* ipiv,\n                                const lapack_complex_double* b, lapack_int ldb,\n                                lapack_complex_double* x, lapack_int ldx,\n                                double* ferr, double* berr,\n                                lapack_complex_double* work, double* rwork );\n\nlapack_int LAPACKE_sgtsv_work( int matrix_order, lapack_int n, lapack_int nrhs,\n                               float* dl, float* d, float* du, float* b,\n                               lapack_int ldb );\nlapack_int LAPACKE_dgtsv_work( int matrix_order, lapack_int n, lapack_int nrhs,\n                               double* dl, double* d, double* du, double* b,\n                               lapack_int ldb );\nlapack_int LAPACKE_cgtsv_work( int matrix_order, lapack_int n, lapack_int nrhs,\n                               lapack_complex_float* dl,\n                               lapack_complex_float* d,\n                               lapack_complex_float* du,\n                               lapack_complex_float* b, lapack_int ldb );\nlapack_int LAPACKE_zgtsv_work( int matrix_order, lapack_int n, lapack_int nrhs,\n                               lapack_complex_double* dl,\n                               lapack_complex_double* d,\n                               lapack_complex_double* du,\n                               lapack_complex_double* b, lapack_int ldb );\n\nlapack_int LAPACKE_sgtsvx_work( int matrix_order, char fact, char trans,\n                                lapack_int n, lapack_int nrhs, const float* dl,\n                                const float* d, const float* du, float* dlf,\n                                float* df, float* duf, float* du2,\n                                lapack_int* ipiv, const float* b,\n                                lapack_int ldb, float* x, lapack_int ldx,\n                                float* rcond, float* ferr, float* berr,\n                                float* work, lapack_int* iwork );\nlapack_int LAPACKE_dgtsvx_work( int matrix_order, char fact, char trans,\n                                lapack_int n, lapack_int nrhs, const double* dl,\n                                const double* d, const double* du, double* dlf,\n                                double* df, double* duf, double* du2,\n                                lapack_int* ipiv, const double* b,\n                                lapack_int ldb, double* x, lapack_int ldx,\n                                double* rcond, double* ferr, double* berr,\n                                double* work, lapack_int* iwork );\nlapack_int LAPACKE_cgtsvx_work( int matrix_order, char fact, char trans,\n                                lapack_int n, lapack_int nrhs,\n                                const lapack_complex_float* dl,\n                                const lapack_complex_float* d,\n                                const lapack_complex_float* du,\n                                lapack_complex_float* dlf,\n                                lapack_complex_float* df,\n                                lapack_complex_float* duf,\n                                lapack_complex_float* du2, lapack_int* ipiv,\n                                const lapack_complex_float* b, lapack_int ldb,\n                                lapack_complex_float* x, lapack_int ldx,\n                                float* rcond, float* ferr, float* berr,\n                                lapack_complex_float* work, float* rwork );\nlapack_int LAPACKE_zgtsvx_work( int matrix_order, char fact, char trans,\n                                lapack_int n, lapack_int nrhs,\n                                const lapack_complex_double* dl,\n                                const lapack_complex_double* d,\n                                const lapack_complex_double* du,\n                                lapack_complex_double* dlf,\n                                lapack_complex_double* df,\n                                lapack_complex_double* duf,\n                                lapack_complex_double* du2, lapack_int* ipiv,\n                                const lapack_complex_double* b, lapack_int ldb,\n                                lapack_complex_double* x, lapack_int ldx,\n                                double* rcond, double* ferr, double* berr,\n                                lapack_complex_double* work, double* rwork );\n\nlapack_int LAPACKE_sgttrf_work( lapack_int n, float* dl, float* d, float* du,\n                                float* du2, lapack_int* ipiv );\nlapack_int LAPACKE_dgttrf_work( lapack_int n, double* dl, double* d, double* du,\n                                double* du2, lapack_int* ipiv );\nlapack_int LAPACKE_cgttrf_work( lapack_int n, lapack_complex_float* dl,\n                                lapack_complex_float* d,\n                                lapack_complex_float* du,\n                                lapack_complex_float* du2, lapack_int* ipiv );\nlapack_int LAPACKE_zgttrf_work( lapack_int n, lapack_complex_double* dl,\n                                lapack_complex_double* d,\n                                lapack_complex_double* du,\n                                lapack_complex_double* du2, lapack_int* ipiv );\n\nlapack_int LAPACKE_sgttrs_work( int matrix_order, char trans, lapack_int n,\n                                lapack_int nrhs, const float* dl,\n                                const float* d, const float* du,\n                                const float* du2, const lapack_int* ipiv,\n                                float* b, lapack_int ldb );\nlapack_int LAPACKE_dgttrs_work( int matrix_order, char trans, lapack_int n,\n                                lapack_int nrhs, const double* dl,\n                                const double* d, const double* du,\n                                const double* du2, const lapack_int* ipiv,\n                                double* b, lapack_int ldb );\nlapack_int LAPACKE_cgttrs_work( int matrix_order, char trans, lapack_int n,\n                                lapack_int nrhs, const lapack_complex_float* dl,\n                                const lapack_complex_float* d,\n                                const lapack_complex_float* du,\n                                const lapack_complex_float* du2,\n                                const lapack_int* ipiv, lapack_complex_float* b,\n                                lapack_int ldb );\nlapack_int LAPACKE_zgttrs_work( int matrix_order, char trans, lapack_int n,\n                                lapack_int nrhs,\n                                const lapack_complex_double* dl,\n                                const lapack_complex_double* d,\n                                const lapack_complex_double* du,\n                                const lapack_complex_double* du2,\n                                const lapack_int* ipiv,\n                                lapack_complex_double* b, lapack_int ldb );\n\nlapack_int LAPACKE_chbev_work( int matrix_order, char jobz, char uplo,\n                               lapack_int n, lapack_int kd,\n                               lapack_complex_float* ab, lapack_int ldab,\n                               float* w, lapack_complex_float* z,\n                               lapack_int ldz, lapack_complex_float* work,\n                               float* rwork );\nlapack_int LAPACKE_zhbev_work( int matrix_order, char jobz, char uplo,\n                               lapack_int n, lapack_int kd,\n                               lapack_complex_double* ab, lapack_int ldab,\n                               double* w, lapack_complex_double* z,\n                               lapack_int ldz, lapack_complex_double* work,\n                               double* rwork );\n\nlapack_int LAPACKE_chbevd_work( int matrix_order, char jobz, char uplo,\n                                lapack_int n, lapack_int kd,\n                                lapack_complex_float* ab, lapack_int ldab,\n                                float* w, lapack_complex_float* z,\n                                lapack_int ldz, lapack_complex_float* work,\n                                lapack_int lwork, float* rwork,\n                                lapack_int lrwork, lapack_int* iwork,\n                                lapack_int liwork );\nlapack_int LAPACKE_zhbevd_work( int matrix_order, char jobz, char uplo,\n                                lapack_int n, lapack_int kd,\n                                lapack_complex_double* ab, lapack_int ldab,\n                                double* w, lapack_complex_double* z,\n                                lapack_int ldz, lapack_complex_double* work,\n                                lapack_int lwork, double* rwork,\n                                lapack_int lrwork, lapack_int* iwork,\n                                lapack_int liwork );\n\nlapack_int LAPACKE_chbevx_work( int matrix_order, char jobz, char range,\n                                char uplo, lapack_int n, lapack_int kd,\n                                lapack_complex_float* ab, lapack_int ldab,\n                                lapack_complex_float* q, lapack_int ldq,\n                                float vl, float vu, lapack_int il,\n                                lapack_int iu, float abstol, lapack_int* m,\n                                float* w, lapack_complex_float* z,\n                                lapack_int ldz, lapack_complex_float* work,\n                                float* rwork, lapack_int* iwork,\n                                lapack_int* ifail );\nlapack_int LAPACKE_zhbevx_work( int matrix_order, char jobz, char range,\n                                char uplo, lapack_int n, lapack_int kd,\n                                lapack_complex_double* ab, lapack_int ldab,\n                                lapack_complex_double* q, lapack_int ldq,\n                                double vl, double vu, lapack_int il,\n                                lapack_int iu, double abstol, lapack_int* m,\n                                double* w, lapack_complex_double* z,\n                                lapack_int ldz, lapack_complex_double* work,\n                                double* rwork, lapack_int* iwork,\n                                lapack_int* ifail );\n\nlapack_int LAPACKE_chbgst_work( int matrix_order, char vect, char uplo,\n                                lapack_int n, lapack_int ka, lapack_int kb,\n                                lapack_complex_float* ab, lapack_int ldab,\n                                const lapack_complex_float* bb, lapack_int ldbb,\n                                lapack_complex_float* x, lapack_int ldx,\n                                lapack_complex_float* work, float* rwork );\nlapack_int LAPACKE_zhbgst_work( int matrix_order, char vect, char uplo,\n                                lapack_int n, lapack_int ka, lapack_int kb,\n                                lapack_complex_double* ab, lapack_int ldab,\n                                const lapack_complex_double* bb,\n                                lapack_int ldbb, lapack_complex_double* x,\n                                lapack_int ldx, lapack_complex_double* work,\n                                double* rwork );\n\nlapack_int LAPACKE_chbgv_work( int matrix_order, char jobz, char uplo,\n                               lapack_int n, lapack_int ka, lapack_int kb,\n                               lapack_complex_float* ab, lapack_int ldab,\n                               lapack_complex_float* bb, lapack_int ldbb,\n                               float* w, lapack_complex_float* z,\n                               lapack_int ldz, lapack_complex_float* work,\n                               float* rwork );\nlapack_int LAPACKE_zhbgv_work( int matrix_order, char jobz, char uplo,\n                               lapack_int n, lapack_int ka, lapack_int kb,\n                               lapack_complex_double* ab, lapack_int ldab,\n                               lapack_complex_double* bb, lapack_int ldbb,\n                               double* w, lapack_complex_double* z,\n                               lapack_int ldz, lapack_complex_double* work,\n                               double* rwork );\n\nlapack_int LAPACKE_chbgvd_work( int matrix_order, char jobz, char uplo,\n                                lapack_int n, lapack_int ka, lapack_int kb,\n                                lapack_complex_float* ab, lapack_int ldab,\n                                lapack_complex_float* bb, lapack_int ldbb,\n                                float* w, lapack_complex_float* z,\n                                lapack_int ldz, lapack_complex_float* work,\n                                lapack_int lwork, float* rwork,\n                                lapack_int lrwork, lapack_int* iwork,\n                                lapack_int liwork );\nlapack_int LAPACKE_zhbgvd_work( int matrix_order, char jobz, char uplo,\n                                lapack_int n, lapack_int ka, lapack_int kb,\n                                lapack_complex_double* ab, lapack_int ldab,\n                                lapack_complex_double* bb, lapack_int ldbb,\n                                double* w, lapack_complex_double* z,\n                                lapack_int ldz, lapack_complex_double* work,\n                                lapack_int lwork, double* rwork,\n                                lapack_int lrwork, lapack_int* iwork,\n                                lapack_int liwork );\n\nlapack_int LAPACKE_chbgvx_work( int matrix_order, char jobz, char range,\n                                char uplo, lapack_int n, lapack_int ka,\n                                lapack_int kb, lapack_complex_float* ab,\n                                lapack_int ldab, lapack_complex_float* bb,\n                                lapack_int ldbb, lapack_complex_float* q,\n                                lapack_int ldq, float vl, float vu,\n                                lapack_int il, lapack_int iu, float abstol,\n                                lapack_int* m, float* w,\n                                lapack_complex_float* z, lapack_int ldz,\n                                lapack_complex_float* work, float* rwork,\n                                lapack_int* iwork, lapack_int* ifail );\nlapack_int LAPACKE_zhbgvx_work( int matrix_order, char jobz, char range,\n                                char uplo, lapack_int n, lapack_int ka,\n                                lapack_int kb, lapack_complex_double* ab,\n                                lapack_int ldab, lapack_complex_double* bb,\n                                lapack_int ldbb, lapack_complex_double* q,\n                                lapack_int ldq, double vl, double vu,\n                                lapack_int il, lapack_int iu, double abstol,\n                                lapack_int* m, double* w,\n                                lapack_complex_double* z, lapack_int ldz,\n                                lapack_complex_double* work, double* rwork,\n                                lapack_int* iwork, lapack_int* ifail );\n\nlapack_int LAPACKE_chbtrd_work( int matrix_order, char vect, char uplo,\n                                lapack_int n, lapack_int kd,\n                                lapack_complex_float* ab, lapack_int ldab,\n                                float* d, float* e, lapack_complex_float* q,\n                                lapack_int ldq, lapack_complex_float* work );\nlapack_int LAPACKE_zhbtrd_work( int matrix_order, char vect, char uplo,\n                                lapack_int n, lapack_int kd,\n                                lapack_complex_double* ab, lapack_int ldab,\n                                double* d, double* e, lapack_complex_double* q,\n                                lapack_int ldq, lapack_complex_double* work );\n\nlapack_int LAPACKE_checon_work( int matrix_order, char uplo, lapack_int n,\n                                const lapack_complex_float* a, lapack_int lda,\n                                const lapack_int* ipiv, float anorm,\n                                float* rcond, lapack_complex_float* work );\nlapack_int LAPACKE_zhecon_work( int matrix_order, char uplo, lapack_int n,\n                                const lapack_complex_double* a, lapack_int lda,\n                                const lapack_int* ipiv, double anorm,\n                                double* rcond, lapack_complex_double* work );\n\nlapack_int LAPACKE_cheequb_work( int matrix_order, char uplo, lapack_int n,\n                                 const lapack_complex_float* a, lapack_int lda,\n                                 float* s, float* scond, float* amax,\n                                 lapack_complex_float* work );\nlapack_int LAPACKE_zheequb_work( int matrix_order, char uplo, lapack_int n,\n                                 const lapack_complex_double* a, lapack_int lda,\n                                 double* s, double* scond, double* amax,\n                                 lapack_complex_double* work );\n\nlapack_int LAPACKE_cheev_work( int matrix_order, char jobz, char uplo,\n                               lapack_int n, lapack_complex_float* a,\n                               lapack_int lda, float* w,\n                               lapack_complex_float* work, lapack_int lwork,\n                               float* rwork );\nlapack_int LAPACKE_zheev_work( int matrix_order, char jobz, char uplo,\n                               lapack_int n, lapack_complex_double* a,\n                               lapack_int lda, double* w,\n                               lapack_complex_double* work, lapack_int lwork,\n                               double* rwork );\n\nlapack_int LAPACKE_cheevd_work( int matrix_order, char jobz, char uplo,\n                                lapack_int n, lapack_complex_float* a,\n                                lapack_int lda, float* w,\n                                lapack_complex_float* work, lapack_int lwork,\n                                float* rwork, lapack_int lrwork,\n                                lapack_int* iwork, lapack_int liwork );\nlapack_int LAPACKE_zheevd_work( int matrix_order, char jobz, char uplo,\n                                lapack_int n, lapack_complex_double* a,\n                                lapack_int lda, double* w,\n                                lapack_complex_double* work, lapack_int lwork,\n                                double* rwork, lapack_int lrwork,\n                                lapack_int* iwork, lapack_int liwork );\n\nlapack_int LAPACKE_cheevr_work( int matrix_order, char jobz, char range,\n                                char uplo, lapack_int n,\n                                lapack_complex_float* a, lapack_int lda,\n                                float vl, float vu, lapack_int il,\n                                lapack_int iu, float abstol, lapack_int* m,\n                                float* w, lapack_complex_float* z,\n                                lapack_int ldz, lapack_int* isuppz,\n                                lapack_complex_float* work, lapack_int lwork,\n                                float* rwork, lapack_int lrwork,\n                                lapack_int* iwork, lapack_int liwork );\nlapack_int LAPACKE_zheevr_work( int matrix_order, char jobz, char range,\n                                char uplo, lapack_int n,\n                                lapack_complex_double* a, lapack_int lda,\n                                double vl, double vu, lapack_int il,\n                                lapack_int iu, double abstol, lapack_int* m,\n                                double* w, lapack_complex_double* z,\n                                lapack_int ldz, lapack_int* isuppz,\n                                lapack_complex_double* work, lapack_int lwork,\n                                double* rwork, lapack_int lrwork,\n                                lapack_int* iwork, lapack_int liwork );\n\nlapack_int LAPACKE_cheevx_work( int matrix_order, char jobz, char range,\n                                char uplo, lapack_int n,\n                                lapack_complex_float* a, lapack_int lda,\n                                float vl, float vu, lapack_int il,\n                                lapack_int iu, float abstol, lapack_int* m,\n                                float* w, lapack_complex_float* z,\n                                lapack_int ldz, lapack_complex_float* work,\n                                lapack_int lwork, float* rwork,\n                                lapack_int* iwork, lapack_int* ifail );\nlapack_int LAPACKE_zheevx_work( int matrix_order, char jobz, char range,\n                                char uplo, lapack_int n,\n                                lapack_complex_double* a, lapack_int lda,\n                                double vl, double vu, lapack_int il,\n                                lapack_int iu, double abstol, lapack_int* m,\n                                double* w, lapack_complex_double* z,\n                                lapack_int ldz, lapack_complex_double* work,\n                                lapack_int lwork, double* rwork,\n                                lapack_int* iwork, lapack_int* ifail );\n\nlapack_int LAPACKE_chegst_work( int matrix_order, lapack_int itype, char uplo,\n                                lapack_int n, lapack_complex_float* a,\n                                lapack_int lda, const lapack_complex_float* b,\n                                lapack_int ldb );\nlapack_int LAPACKE_zhegst_work( int matrix_order, lapack_int itype, char uplo,\n                                lapack_int n, lapack_complex_double* a,\n                                lapack_int lda, const lapack_complex_double* b,\n                                lapack_int ldb );\n\nlapack_int LAPACKE_chegv_work( int matrix_order, lapack_int itype, char jobz,\n                               char uplo, lapack_int n, lapack_complex_float* a,\n                               lapack_int lda, lapack_complex_float* b,\n                               lapack_int ldb, float* w,\n                               lapack_complex_float* work, lapack_int lwork,\n                               float* rwork );\nlapack_int LAPACKE_zhegv_work( int matrix_order, lapack_int itype, char jobz,\n                               char uplo, lapack_int n,\n                               lapack_complex_double* a, lapack_int lda,\n                               lapack_complex_double* b, lapack_int ldb,\n                               double* w, lapack_complex_double* work,\n                               lapack_int lwork, double* rwork );\n\nlapack_int LAPACKE_chegvd_work( int matrix_order, lapack_int itype, char jobz,\n                                char uplo, lapack_int n,\n                                lapack_complex_float* a, lapack_int lda,\n                                lapack_complex_float* b, lapack_int ldb,\n                                float* w, lapack_complex_float* work,\n                                lapack_int lwork, float* rwork,\n                                lapack_int lrwork, lapack_int* iwork,\n                                lapack_int liwork );\nlapack_int LAPACKE_zhegvd_work( int matrix_order, lapack_int itype, char jobz,\n                                char uplo, lapack_int n,\n                                lapack_complex_double* a, lapack_int lda,\n                                lapack_complex_double* b, lapack_int ldb,\n                                double* w, lapack_complex_double* work,\n                                lapack_int lwork, double* rwork,\n                                lapack_int lrwork, lapack_int* iwork,\n                                lapack_int liwork );\n\nlapack_int LAPACKE_chegvx_work( int matrix_order, lapack_int itype, char jobz,\n                                char range, char uplo, lapack_int n,\n                                lapack_complex_float* a, lapack_int lda,\n                                lapack_complex_float* b, lapack_int ldb,\n                                float vl, float vu, lapack_int il,\n                                lapack_int iu, float abstol, lapack_int* m,\n                                float* w, lapack_complex_float* z,\n                                lapack_int ldz, lapack_complex_float* work,\n                                lapack_int lwork, float* rwork,\n                                lapack_int* iwork, lapack_int* ifail );\nlapack_int LAPACKE_zhegvx_work( int matrix_order, lapack_int itype, char jobz,\n                                char range, char uplo, lapack_int n,\n                                lapack_complex_double* a, lapack_int lda,\n                                lapack_complex_double* b, lapack_int ldb,\n                                double vl, double vu, lapack_int il,\n                                lapack_int iu, double abstol, lapack_int* m,\n                                double* w, lapack_complex_double* z,\n                                lapack_int ldz, lapack_complex_double* work,\n                                lapack_int lwork, double* rwork,\n                                lapack_int* iwork, lapack_int* ifail );\n\nlapack_int LAPACKE_cherfs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const lapack_complex_float* a,\n                                lapack_int lda, const lapack_complex_float* af,\n                                lapack_int ldaf, const lapack_int* ipiv,\n                                const lapack_complex_float* b, lapack_int ldb,\n                                lapack_complex_float* x, lapack_int ldx,\n                                float* ferr, float* berr,\n                                lapack_complex_float* work, float* rwork );\nlapack_int LAPACKE_zherfs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const lapack_complex_double* a,\n                                lapack_int lda, const lapack_complex_double* af,\n                                lapack_int ldaf, const lapack_int* ipiv,\n                                const lapack_complex_double* b, lapack_int ldb,\n                                lapack_complex_double* x, lapack_int ldx,\n                                double* ferr, double* berr,\n                                lapack_complex_double* work, double* rwork );\n\nlapack_int LAPACKE_cherfsx_work( int matrix_order, char uplo, char equed,\n                                 lapack_int n, lapack_int nrhs,\n                                 const lapack_complex_float* a, lapack_int lda,\n                                 const lapack_complex_float* af,\n                                 lapack_int ldaf, const lapack_int* ipiv,\n                                 const float* s, const lapack_complex_float* b,\n                                 lapack_int ldb, lapack_complex_float* x,\n                                 lapack_int ldx, float* rcond, float* berr,\n                                 lapack_int n_err_bnds, float* err_bnds_norm,\n                                 float* err_bnds_comp, lapack_int nparams,\n                                 float* params, lapack_complex_float* work,\n                                 float* rwork );\nlapack_int LAPACKE_zherfsx_work( int matrix_order, char uplo, char equed,\n                                 lapack_int n, lapack_int nrhs,\n                                 const lapack_complex_double* a, lapack_int lda,\n                                 const lapack_complex_double* af,\n                                 lapack_int ldaf, const lapack_int* ipiv,\n                                 const double* s,\n                                 const lapack_complex_double* b, lapack_int ldb,\n                                 lapack_complex_double* x, lapack_int ldx,\n                                 double* rcond, double* berr,\n                                 lapack_int n_err_bnds, double* err_bnds_norm,\n                                 double* err_bnds_comp, lapack_int nparams,\n                                 double* params, lapack_complex_double* work,\n                                 double* rwork );\n\nlapack_int LAPACKE_chesv_work( int matrix_order, char uplo, lapack_int n,\n                               lapack_int nrhs, lapack_complex_float* a,\n                               lapack_int lda, lapack_int* ipiv,\n                               lapack_complex_float* b, lapack_int ldb,\n                               lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_zhesv_work( int matrix_order, char uplo, lapack_int n,\n                               lapack_int nrhs, lapack_complex_double* a,\n                               lapack_int lda, lapack_int* ipiv,\n                               lapack_complex_double* b, lapack_int ldb,\n                               lapack_complex_double* work, lapack_int lwork );\n\nlapack_int LAPACKE_chesvx_work( int matrix_order, char fact, char uplo,\n                                lapack_int n, lapack_int nrhs,\n                                const lapack_complex_float* a, lapack_int lda,\n                                lapack_complex_float* af, lapack_int ldaf,\n                                lapack_int* ipiv, const lapack_complex_float* b,\n                                lapack_int ldb, lapack_complex_float* x,\n                                lapack_int ldx, float* rcond, float* ferr,\n                                float* berr, lapack_complex_float* work,\n                                lapack_int lwork, float* rwork );\nlapack_int LAPACKE_zhesvx_work( int matrix_order, char fact, char uplo,\n                                lapack_int n, lapack_int nrhs,\n                                const lapack_complex_double* a, lapack_int lda,\n                                lapack_complex_double* af, lapack_int ldaf,\n                                lapack_int* ipiv,\n                                const lapack_complex_double* b, lapack_int ldb,\n                                lapack_complex_double* x, lapack_int ldx,\n                                double* rcond, double* ferr, double* berr,\n                                lapack_complex_double* work, lapack_int lwork,\n                                double* rwork );\n\nlapack_int LAPACKE_chesvxx_work( int matrix_order, char fact, char uplo,\n                                 lapack_int n, lapack_int nrhs,\n                                 lapack_complex_float* a, lapack_int lda,\n                                 lapack_complex_float* af, lapack_int ldaf,\n                                 lapack_int* ipiv, char* equed, float* s,\n                                 lapack_complex_float* b, lapack_int ldb,\n                                 lapack_complex_float* x, lapack_int ldx,\n                                 float* rcond, float* rpvgrw, float* berr,\n                                 lapack_int n_err_bnds, float* err_bnds_norm,\n                                 float* err_bnds_comp, lapack_int nparams,\n                                 float* params, lapack_complex_float* work,\n                                 float* rwork );\nlapack_int LAPACKE_zhesvxx_work( int matrix_order, char fact, char uplo,\n                                 lapack_int n, lapack_int nrhs,\n                                 lapack_complex_double* a, lapack_int lda,\n                                 lapack_complex_double* af, lapack_int ldaf,\n                                 lapack_int* ipiv, char* equed, double* s,\n                                 lapack_complex_double* b, lapack_int ldb,\n                                 lapack_complex_double* x, lapack_int ldx,\n                                 double* rcond, double* rpvgrw, double* berr,\n                                 lapack_int n_err_bnds, double* err_bnds_norm,\n                                 double* err_bnds_comp, lapack_int nparams,\n                                 double* params, lapack_complex_double* work,\n                                 double* rwork );\n\nlapack_int LAPACKE_chetrd_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_complex_float* a, lapack_int lda,\n                                float* d, float* e, lapack_complex_float* tau,\n                                lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_zhetrd_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_complex_double* a, lapack_int lda,\n                                double* d, double* e,\n                                lapack_complex_double* tau,\n                                lapack_complex_double* work, lapack_int lwork );\n\nlapack_int LAPACKE_chetrf_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_complex_float* a, lapack_int lda,\n                                lapack_int* ipiv, lapack_complex_float* work,\n                                lapack_int lwork );\nlapack_int LAPACKE_zhetrf_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_complex_double* a, lapack_int lda,\n                                lapack_int* ipiv, lapack_complex_double* work,\n                                lapack_int lwork );\n\nlapack_int LAPACKE_chetri_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_complex_float* a, lapack_int lda,\n                                const lapack_int* ipiv,\n                                lapack_complex_float* work );\nlapack_int LAPACKE_zhetri_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_complex_double* a, lapack_int lda,\n                                const lapack_int* ipiv,\n                                lapack_complex_double* work );\n\nlapack_int LAPACKE_chetrs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const lapack_complex_float* a,\n                                lapack_int lda, const lapack_int* ipiv,\n                                lapack_complex_float* b, lapack_int ldb );\nlapack_int LAPACKE_zhetrs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const lapack_complex_double* a,\n                                lapack_int lda, const lapack_int* ipiv,\n                                lapack_complex_double* b, lapack_int ldb );\n\nlapack_int LAPACKE_chfrk_work( int matrix_order, char transr, char uplo,\n                               char trans, lapack_int n, lapack_int k,\n                               float alpha, const lapack_complex_float* a,\n                               lapack_int lda, float beta,\n                               lapack_complex_float* c );\nlapack_int LAPACKE_zhfrk_work( int matrix_order, char transr, char uplo,\n                               char trans, lapack_int n, lapack_int k,\n                               double alpha, const lapack_complex_double* a,\n                               lapack_int lda, double beta,\n                               lapack_complex_double* c );\n\nlapack_int LAPACKE_shgeqz_work( int matrix_order, char job, char compq,\n                                char compz, lapack_int n, lapack_int ilo,\n                                lapack_int ihi, float* h, lapack_int ldh,\n                                float* t, lapack_int ldt, float* alphar,\n                                float* alphai, float* beta, float* q,\n                                lapack_int ldq, float* z, lapack_int ldz,\n                                float* work, lapack_int lwork );\nlapack_int LAPACKE_dhgeqz_work( int matrix_order, char job, char compq,\n                                char compz, lapack_int n, lapack_int ilo,\n                                lapack_int ihi, double* h, lapack_int ldh,\n                                double* t, lapack_int ldt, double* alphar,\n                                double* alphai, double* beta, double* q,\n                                lapack_int ldq, double* z, lapack_int ldz,\n                                double* work, lapack_int lwork );\nlapack_int LAPACKE_chgeqz_work( int matrix_order, char job, char compq,\n                                char compz, lapack_int n, lapack_int ilo,\n                                lapack_int ihi, lapack_complex_float* h,\n                                lapack_int ldh, lapack_complex_float* t,\n                                lapack_int ldt, lapack_complex_float* alpha,\n                                lapack_complex_float* beta,\n                                lapack_complex_float* q, lapack_int ldq,\n                                lapack_complex_float* z, lapack_int ldz,\n                                lapack_complex_float* work, lapack_int lwork,\n                                float* rwork );\nlapack_int LAPACKE_zhgeqz_work( int matrix_order, char job, char compq,\n                                char compz, lapack_int n, lapack_int ilo,\n                                lapack_int ihi, lapack_complex_double* h,\n                                lapack_int ldh, lapack_complex_double* t,\n                                lapack_int ldt, lapack_complex_double* alpha,\n                                lapack_complex_double* beta,\n                                lapack_complex_double* q, lapack_int ldq,\n                                lapack_complex_double* z, lapack_int ldz,\n                                lapack_complex_double* work, lapack_int lwork,\n                                double* rwork );\n\nlapack_int LAPACKE_chpcon_work( int matrix_order, char uplo, lapack_int n,\n                                const lapack_complex_float* ap,\n                                const lapack_int* ipiv, float anorm,\n                                float* rcond, lapack_complex_float* work );\nlapack_int LAPACKE_zhpcon_work( int matrix_order, char uplo, lapack_int n,\n                                const lapack_complex_double* ap,\n                                const lapack_int* ipiv, double anorm,\n                                double* rcond, lapack_complex_double* work );\n\nlapack_int LAPACKE_chpev_work( int matrix_order, char jobz, char uplo,\n                               lapack_int n, lapack_complex_float* ap, float* w,\n                               lapack_complex_float* z, lapack_int ldz,\n                               lapack_complex_float* work, float* rwork );\nlapack_int LAPACKE_zhpev_work( int matrix_order, char jobz, char uplo,\n                               lapack_int n, lapack_complex_double* ap,\n                               double* w, lapack_complex_double* z,\n                               lapack_int ldz, lapack_complex_double* work,\n                               double* rwork );\n\nlapack_int LAPACKE_chpevd_work( int matrix_order, char jobz, char uplo,\n                                lapack_int n, lapack_complex_float* ap,\n                                float* w, lapack_complex_float* z,\n                                lapack_int ldz, lapack_complex_float* work,\n                                lapack_int lwork, float* rwork,\n                                lapack_int lrwork, lapack_int* iwork,\n                                lapack_int liwork );\nlapack_int LAPACKE_zhpevd_work( int matrix_order, char jobz, char uplo,\n                                lapack_int n, lapack_complex_double* ap,\n                                double* w, lapack_complex_double* z,\n                                lapack_int ldz, lapack_complex_double* work,\n                                lapack_int lwork, double* rwork,\n                                lapack_int lrwork, lapack_int* iwork,\n                                lapack_int liwork );\n\nlapack_int LAPACKE_chpevx_work( int matrix_order, char jobz, char range,\n                                char uplo, lapack_int n,\n                                lapack_complex_float* ap, float vl, float vu,\n                                lapack_int il, lapack_int iu, float abstol,\n                                lapack_int* m, float* w,\n                                lapack_complex_float* z, lapack_int ldz,\n                                lapack_complex_float* work, float* rwork,\n                                lapack_int* iwork, lapack_int* ifail );\nlapack_int LAPACKE_zhpevx_work( int matrix_order, char jobz, char range,\n                                char uplo, lapack_int n,\n                                lapack_complex_double* ap, double vl, double vu,\n                                lapack_int il, lapack_int iu, double abstol,\n                                lapack_int* m, double* w,\n                                lapack_complex_double* z, lapack_int ldz,\n                                lapack_complex_double* work, double* rwork,\n                                lapack_int* iwork, lapack_int* ifail );\n\nlapack_int LAPACKE_chpgst_work( int matrix_order, lapack_int itype, char uplo,\n                                lapack_int n, lapack_complex_float* ap,\n                                const lapack_complex_float* bp );\nlapack_int LAPACKE_zhpgst_work( int matrix_order, lapack_int itype, char uplo,\n                                lapack_int n, lapack_complex_double* ap,\n                                const lapack_complex_double* bp );\n\nlapack_int LAPACKE_chpgv_work( int matrix_order, lapack_int itype, char jobz,\n                               char uplo, lapack_int n,\n                               lapack_complex_float* ap,\n                               lapack_complex_float* bp, float* w,\n                               lapack_complex_float* z, lapack_int ldz,\n                               lapack_complex_float* work, float* rwork );\nlapack_int LAPACKE_zhpgv_work( int matrix_order, lapack_int itype, char jobz,\n                               char uplo, lapack_int n,\n                               lapack_complex_double* ap,\n                               lapack_complex_double* bp, double* w,\n                               lapack_complex_double* z, lapack_int ldz,\n                               lapack_complex_double* work, double* rwork );\n\nlapack_int LAPACKE_chpgvd_work( int matrix_order, lapack_int itype, char jobz,\n                                char uplo, lapack_int n,\n                                lapack_complex_float* ap,\n                                lapack_complex_float* bp, float* w,\n                                lapack_complex_float* z, lapack_int ldz,\n                                lapack_complex_float* work, lapack_int lwork,\n                                float* rwork, lapack_int lrwork,\n                                lapack_int* iwork, lapack_int liwork );\nlapack_int LAPACKE_zhpgvd_work( int matrix_order, lapack_int itype, char jobz,\n                                char uplo, lapack_int n,\n                                lapack_complex_double* ap,\n                                lapack_complex_double* bp, double* w,\n                                lapack_complex_double* z, lapack_int ldz,\n                                lapack_complex_double* work, lapack_int lwork,\n                                double* rwork, lapack_int lrwork,\n                                lapack_int* iwork, lapack_int liwork );\n\nlapack_int LAPACKE_chpgvx_work( int matrix_order, lapack_int itype, char jobz,\n                                char range, char uplo, lapack_int n,\n                                lapack_complex_float* ap,\n                                lapack_complex_float* bp, float vl, float vu,\n                                lapack_int il, lapack_int iu, float abstol,\n                                lapack_int* m, float* w,\n                                lapack_complex_float* z, lapack_int ldz,\n                                lapack_complex_float* work, float* rwork,\n                                lapack_int* iwork, lapack_int* ifail );\nlapack_int LAPACKE_zhpgvx_work( int matrix_order, lapack_int itype, char jobz,\n                                char range, char uplo, lapack_int n,\n                                lapack_complex_double* ap,\n                                lapack_complex_double* bp, double vl, double vu,\n                                lapack_int il, lapack_int iu, double abstol,\n                                lapack_int* m, double* w,\n                                lapack_complex_double* z, lapack_int ldz,\n                                lapack_complex_double* work, double* rwork,\n                                lapack_int* iwork, lapack_int* ifail );\n\nlapack_int LAPACKE_chprfs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const lapack_complex_float* ap,\n                                const lapack_complex_float* afp,\n                                const lapack_int* ipiv,\n                                const lapack_complex_float* b, lapack_int ldb,\n                                lapack_complex_float* x, lapack_int ldx,\n                                float* ferr, float* berr,\n                                lapack_complex_float* work, float* rwork );\nlapack_int LAPACKE_zhprfs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs,\n                                const lapack_complex_double* ap,\n                                const lapack_complex_double* afp,\n                                const lapack_int* ipiv,\n                                const lapack_complex_double* b, lapack_int ldb,\n                                lapack_complex_double* x, lapack_int ldx,\n                                double* ferr, double* berr,\n                                lapack_complex_double* work, double* rwork );\n\nlapack_int LAPACKE_chpsv_work( int matrix_order, char uplo, lapack_int n,\n                               lapack_int nrhs, lapack_complex_float* ap,\n                               lapack_int* ipiv, lapack_complex_float* b,\n                               lapack_int ldb );\nlapack_int LAPACKE_zhpsv_work( int matrix_order, char uplo, lapack_int n,\n                               lapack_int nrhs, lapack_complex_double* ap,\n                               lapack_int* ipiv, lapack_complex_double* b,\n                               lapack_int ldb );\n\nlapack_int LAPACKE_chpsvx_work( int matrix_order, char fact, char uplo,\n                                lapack_int n, lapack_int nrhs,\n                                const lapack_complex_float* ap,\n                                lapack_complex_float* afp, lapack_int* ipiv,\n                                const lapack_complex_float* b, lapack_int ldb,\n                                lapack_complex_float* x, lapack_int ldx,\n                                float* rcond, float* ferr, float* berr,\n                                lapack_complex_float* work, float* rwork );\nlapack_int LAPACKE_zhpsvx_work( int matrix_order, char fact, char uplo,\n                                lapack_int n, lapack_int nrhs,\n                                const lapack_complex_double* ap,\n                                lapack_complex_double* afp, lapack_int* ipiv,\n                                const lapack_complex_double* b, lapack_int ldb,\n                                lapack_complex_double* x, lapack_int ldx,\n                                double* rcond, double* ferr, double* berr,\n                                lapack_complex_double* work, double* rwork );\n\nlapack_int LAPACKE_chptrd_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_complex_float* ap, float* d, float* e,\n                                lapack_complex_float* tau );\nlapack_int LAPACKE_zhptrd_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_complex_double* ap, double* d, double* e,\n                                lapack_complex_double* tau );\n\nlapack_int LAPACKE_chptrf_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_complex_float* ap, lapack_int* ipiv );\nlapack_int LAPACKE_zhptrf_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_complex_double* ap, lapack_int* ipiv );\n\nlapack_int LAPACKE_chptri_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_complex_float* ap,\n                                const lapack_int* ipiv,\n                                lapack_complex_float* work );\nlapack_int LAPACKE_zhptri_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_complex_double* ap,\n                                const lapack_int* ipiv,\n                                lapack_complex_double* work );\n\nlapack_int LAPACKE_chptrs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const lapack_complex_float* ap,\n                                const lapack_int* ipiv, lapack_complex_float* b,\n                                lapack_int ldb );\nlapack_int LAPACKE_zhptrs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs,\n                                const lapack_complex_double* ap,\n                                const lapack_int* ipiv,\n                                lapack_complex_double* b, lapack_int ldb );\n\nlapack_int LAPACKE_shsein_work( int matrix_order, char job, char eigsrc,\n                                char initv, lapack_logical* select,\n                                lapack_int n, const float* h, lapack_int ldh,\n                                float* wr, const float* wi, float* vl,\n                                lapack_int ldvl, float* vr, lapack_int ldvr,\n                                lapack_int mm, lapack_int* m, float* work,\n                                lapack_int* ifaill, lapack_int* ifailr );\nlapack_int LAPACKE_dhsein_work( int matrix_order, char job, char eigsrc,\n                                char initv, lapack_logical* select,\n                                lapack_int n, const double* h, lapack_int ldh,\n                                double* wr, const double* wi, double* vl,\n                                lapack_int ldvl, double* vr, lapack_int ldvr,\n                                lapack_int mm, lapack_int* m, double* work,\n                                lapack_int* ifaill, lapack_int* ifailr );\nlapack_int LAPACKE_chsein_work( int matrix_order, char job, char eigsrc,\n                                char initv, const lapack_logical* select,\n                                lapack_int n, const lapack_complex_float* h,\n                                lapack_int ldh, lapack_complex_float* w,\n                                lapack_complex_float* vl, lapack_int ldvl,\n                                lapack_complex_float* vr, lapack_int ldvr,\n                                lapack_int mm, lapack_int* m,\n                                lapack_complex_float* work, float* rwork,\n                                lapack_int* ifaill, lapack_int* ifailr );\nlapack_int LAPACKE_zhsein_work( int matrix_order, char job, char eigsrc,\n                                char initv, const lapack_logical* select,\n                                lapack_int n, const lapack_complex_double* h,\n                                lapack_int ldh, lapack_complex_double* w,\n                                lapack_complex_double* vl, lapack_int ldvl,\n                                lapack_complex_double* vr, lapack_int ldvr,\n                                lapack_int mm, lapack_int* m,\n                                lapack_complex_double* work, double* rwork,\n                                lapack_int* ifaill, lapack_int* ifailr );\n\nlapack_int LAPACKE_shseqr_work( int matrix_order, char job, char compz,\n                                lapack_int n, lapack_int ilo, lapack_int ihi,\n                                float* h, lapack_int ldh, float* wr, float* wi,\n                                float* z, lapack_int ldz, float* work,\n                                lapack_int lwork );\nlapack_int LAPACKE_dhseqr_work( int matrix_order, char job, char compz,\n                                lapack_int n, lapack_int ilo, lapack_int ihi,\n                                double* h, lapack_int ldh, double* wr,\n                                double* wi, double* z, lapack_int ldz,\n                                double* work, lapack_int lwork );\nlapack_int LAPACKE_chseqr_work( int matrix_order, char job, char compz,\n                                lapack_int n, lapack_int ilo, lapack_int ihi,\n                                lapack_complex_float* h, lapack_int ldh,\n                                lapack_complex_float* w,\n                                lapack_complex_float* z, lapack_int ldz,\n                                lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_zhseqr_work( int matrix_order, char job, char compz,\n                                lapack_int n, lapack_int ilo, lapack_int ihi,\n                                lapack_complex_double* h, lapack_int ldh,\n                                lapack_complex_double* w,\n                                lapack_complex_double* z, lapack_int ldz,\n                                lapack_complex_double* work, lapack_int lwork );\n\nlapack_int LAPACKE_clacgv_work( lapack_int n, lapack_complex_float* x,\n                                lapack_int incx );\nlapack_int LAPACKE_zlacgv_work( lapack_int n, lapack_complex_double* x,\n                                lapack_int incx );\n\nlapack_int LAPACKE_slacpy_work( int matrix_order, char uplo, lapack_int m,\n                                lapack_int n, const float* a, lapack_int lda,\n                                float* b, lapack_int ldb );\nlapack_int LAPACKE_dlacpy_work( int matrix_order, char uplo, lapack_int m,\n                                lapack_int n, const double* a, lapack_int lda,\n                                double* b, lapack_int ldb );\nlapack_int LAPACKE_clacpy_work( int matrix_order, char uplo, lapack_int m,\n                                lapack_int n, const lapack_complex_float* a,\n                                lapack_int lda, lapack_complex_float* b,\n                                lapack_int ldb );\nlapack_int LAPACKE_zlacpy_work( int matrix_order, char uplo, lapack_int m,\n                                lapack_int n, const lapack_complex_double* a,\n                                lapack_int lda, lapack_complex_double* b,\n                                lapack_int ldb );\n\nlapack_int LAPACKE_zlag2c_work( int matrix_order, lapack_int m, lapack_int n,\n                                const lapack_complex_double* a, lapack_int lda,\n                                lapack_complex_float* sa, lapack_int ldsa );\n\nlapack_int LAPACKE_slag2d_work( int matrix_order, lapack_int m, lapack_int n,\n                                const float* sa, lapack_int ldsa, double* a,\n                                lapack_int lda );\n\nlapack_int LAPACKE_dlag2s_work( int matrix_order, lapack_int m, lapack_int n,\n                                const double* a, lapack_int lda, float* sa,\n                                lapack_int ldsa );\n\nlapack_int LAPACKE_clag2z_work( int matrix_order, lapack_int m, lapack_int n,\n                                const lapack_complex_float* sa, lapack_int ldsa,\n                                lapack_complex_double* a, lapack_int lda );\n\nlapack_int LAPACKE_slagge_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int kl, lapack_int ku, const float* d,\n                                float* a, lapack_int lda, lapack_int* iseed,\n                                float* work );\nlapack_int LAPACKE_dlagge_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int kl, lapack_int ku, const double* d,\n                                double* a, lapack_int lda, lapack_int* iseed,\n                                double* work );\nlapack_int LAPACKE_clagge_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int kl, lapack_int ku, const float* d,\n                                lapack_complex_float* a, lapack_int lda,\n                                lapack_int* iseed, lapack_complex_float* work );\nlapack_int LAPACKE_zlagge_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int kl, lapack_int ku, const double* d,\n                                lapack_complex_double* a, lapack_int lda,\n                                lapack_int* iseed,\n                                lapack_complex_double* work );\n                                \nlapack_int LAPACKE_claghe_work( int matrix_order, lapack_int n, lapack_int k,\n                                const float* d, lapack_complex_float* a,\n                                lapack_int lda, lapack_int* iseed,\n                                lapack_complex_float* work );\nlapack_int LAPACKE_zlaghe_work( int matrix_order, lapack_int n, lapack_int k,\n                                const double* d, lapack_complex_double* a,\n                                lapack_int lda, lapack_int* iseed,\n                                lapack_complex_double* work );\n\nlapack_int LAPACKE_slagsy_work( int matrix_order, lapack_int n, lapack_int k,\n                                const float* d, float* a, lapack_int lda,\n                                lapack_int* iseed, float* work );\nlapack_int LAPACKE_dlagsy_work( int matrix_order, lapack_int n, lapack_int k,\n                                const double* d, double* a, lapack_int lda,\n                                lapack_int* iseed, double* work );\nlapack_int LAPACKE_clagsy_work( int matrix_order, lapack_int n, lapack_int k,\n                                const float* d, lapack_complex_float* a,\n                                lapack_int lda, lapack_int* iseed,\n                                lapack_complex_float* work );\nlapack_int LAPACKE_zlagsy_work( int matrix_order, lapack_int n, lapack_int k,\n                                const double* d, lapack_complex_double* a,\n                                lapack_int lda, lapack_int* iseed,\n                                lapack_complex_double* work );\n\nlapack_int LAPACKE_slapmr_work( int matrix_order, lapack_logical forwrd,\n                                lapack_int m, lapack_int n, float* x,\n                                lapack_int ldx, lapack_int* k );\nlapack_int LAPACKE_dlapmr_work( int matrix_order, lapack_logical forwrd,\n                                lapack_int m, lapack_int n, double* x,\n                                lapack_int ldx, lapack_int* k );\nlapack_int LAPACKE_clapmr_work( int matrix_order, lapack_logical forwrd,\n                                lapack_int m, lapack_int n,\n                                lapack_complex_float* x, lapack_int ldx,\n                                lapack_int* k );\nlapack_int LAPACKE_zlapmr_work( int matrix_order, lapack_logical forwrd,\n                                lapack_int m, lapack_int n,\n                                lapack_complex_double* x, lapack_int ldx,\n                                lapack_int* k );\n\nlapack_int LAPACKE_slartgp_work( float f, float g, float* cs, float* sn,\n                                 float* r );\nlapack_int LAPACKE_dlartgp_work( double f, double g, double* cs, double* sn,\n                                 double* r );\n\nlapack_int LAPACKE_slartgs_work( float x, float y, float sigma, float* cs,\n                                 float* sn );\nlapack_int LAPACKE_dlartgs_work( double x, double y, double sigma, double* cs,\n                                 double* sn );\n                                \nfloat LAPACKE_slapy2_work( float x, float y );\ndouble LAPACKE_dlapy2_work( double x, double y );\n\nfloat LAPACKE_slapy3_work( float x, float y, float z );\ndouble LAPACKE_dlapy3_work( double x, double y, double z );\n\nfloat LAPACKE_slamch_work( char cmach );\ndouble LAPACKE_dlamch_work( char cmach );\n\nfloat LAPACKE_slange_work( int matrix_order, char norm, lapack_int m,\n                                lapack_int n, const float* a, lapack_int lda,\n                                float* work );\ndouble LAPACKE_dlange_work( int matrix_order, char norm, lapack_int m,\n                                lapack_int n, const double* a, lapack_int lda,\n                                double* work );\nfloat LAPACKE_clange_work( int matrix_order, char norm, lapack_int m,\n                                lapack_int n, const lapack_complex_float* a,\n                                lapack_int lda, float* work );\ndouble LAPACKE_zlange_work( int matrix_order, char norm, lapack_int m,\n                                lapack_int n, const lapack_complex_double* a,\n                                lapack_int lda, double* work );\n\nfloat LAPACKE_clanhe_work( int matrix_order, char norm, char uplo,\n                                lapack_int n, const lapack_complex_float* a,\n                                lapack_int lda, float* work );\ndouble LAPACKE_zlanhe_work( int matrix_order, char norm, char uplo,\n                                lapack_int n, const lapack_complex_double* a,\n                                lapack_int lda, double* work );\n\nfloat LAPACKE_slansy_work( int matrix_order, char norm, char uplo,\n                                lapack_int n, const float* a, lapack_int lda,\n                                float* work );\ndouble LAPACKE_dlansy_work( int matrix_order, char norm, char uplo,\n                                lapack_int n, const double* a, lapack_int lda,\n                                double* work );\nfloat LAPACKE_clansy_work( int matrix_order, char norm, char uplo,\n                                lapack_int n, const lapack_complex_float* a,\n                                lapack_int lda, float* work );\ndouble LAPACKE_zlansy_work( int matrix_order, char norm, char uplo,\n                                lapack_int n, const lapack_complex_double* a,\n                                lapack_int lda, double* work );\n\nfloat LAPACKE_slantr_work( int matrix_order, char norm, char uplo,\n                                char diag, lapack_int m, lapack_int n, const float* a,\n                                lapack_int lda, float* work );\ndouble LAPACKE_dlantr_work( int matrix_order, char norm, char uplo,\n                                char diag, lapack_int m, lapack_int n,\n                                const double* a, lapack_int lda, double* work );\nfloat LAPACKE_clantr_work( int matrix_order, char norm, char uplo,\n                                char diag, lapack_int m, lapack_int n,\n                                const lapack_complex_float* a, lapack_int lda,\n                                float* work );\ndouble LAPACKE_zlantr_work( int matrix_order, char norm, char uplo,\n                                char diag, lapack_int m, lapack_int n,\n                                const lapack_complex_double* a, lapack_int lda,\n                                double* work );\n\nlapack_int LAPACKE_slarfb_work( int matrix_order, char side, char trans,\n                                char direct, char storev, lapack_int m,\n                                lapack_int n, lapack_int k, const float* v,\n                                lapack_int ldv, const float* t, lapack_int ldt,\n                                float* c, lapack_int ldc, float* work,\n                                lapack_int ldwork );\nlapack_int LAPACKE_dlarfb_work( int matrix_order, char side, char trans,\n                                char direct, char storev, lapack_int m,\n                                lapack_int n, lapack_int k, const double* v,\n                                lapack_int ldv, const double* t, lapack_int ldt,\n                                double* c, lapack_int ldc, double* work,\n                                lapack_int ldwork );\nlapack_int LAPACKE_clarfb_work( int matrix_order, char side, char trans,\n                                char direct, char storev, lapack_int m,\n                                lapack_int n, lapack_int k,\n                                const lapack_complex_float* v, lapack_int ldv,\n                                const lapack_complex_float* t, lapack_int ldt,\n                                lapack_complex_float* c, lapack_int ldc,\n                                lapack_complex_float* work, lapack_int ldwork );\nlapack_int LAPACKE_zlarfb_work( int matrix_order, char side, char trans,\n                                char direct, char storev, lapack_int m,\n                                lapack_int n, lapack_int k,\n                                const lapack_complex_double* v, lapack_int ldv,\n                                const lapack_complex_double* t, lapack_int ldt,\n                                lapack_complex_double* c, lapack_int ldc,\n                                lapack_complex_double* work,\n                                lapack_int ldwork );\n\nlapack_int LAPACKE_slarfg_work( lapack_int n, float* alpha, float* x,\n                                lapack_int incx, float* tau );\nlapack_int LAPACKE_dlarfg_work( lapack_int n, double* alpha, double* x,\n                                lapack_int incx, double* tau );\nlapack_int LAPACKE_clarfg_work( lapack_int n, lapack_complex_float* alpha,\n                                lapack_complex_float* x, lapack_int incx,\n                                lapack_complex_float* tau );\nlapack_int LAPACKE_zlarfg_work( lapack_int n, lapack_complex_double* alpha,\n                                lapack_complex_double* x, lapack_int incx,\n                                lapack_complex_double* tau );\n\nlapack_int LAPACKE_slarft_work( int matrix_order, char direct, char storev,\n                                lapack_int n, lapack_int k, const float* v,\n                                lapack_int ldv, const float* tau, float* t,\n                                lapack_int ldt );\nlapack_int LAPACKE_dlarft_work( int matrix_order, char direct, char storev,\n                                lapack_int n, lapack_int k, const double* v,\n                                lapack_int ldv, const double* tau, double* t,\n                                lapack_int ldt );\nlapack_int LAPACKE_clarft_work( int matrix_order, char direct, char storev,\n                                lapack_int n, lapack_int k,\n                                const lapack_complex_float* v, lapack_int ldv,\n                                const lapack_complex_float* tau,\n                                lapack_complex_float* t, lapack_int ldt );\nlapack_int LAPACKE_zlarft_work( int matrix_order, char direct, char storev,\n                                lapack_int n, lapack_int k,\n                                const lapack_complex_double* v, lapack_int ldv,\n                                const lapack_complex_double* tau,\n                                lapack_complex_double* t, lapack_int ldt );\n\nlapack_int LAPACKE_slarfx_work( int matrix_order, char side, lapack_int m,\n                                lapack_int n, const float* v, float tau,\n                                float* c, lapack_int ldc, float* work );\nlapack_int LAPACKE_dlarfx_work( int matrix_order, char side, lapack_int m,\n                                lapack_int n, const double* v, double tau,\n                                double* c, lapack_int ldc, double* work );\nlapack_int LAPACKE_clarfx_work( int matrix_order, char side, lapack_int m,\n                                lapack_int n, const lapack_complex_float* v,\n                                lapack_complex_float tau,\n                                lapack_complex_float* c, lapack_int ldc,\n                                lapack_complex_float* work );\nlapack_int LAPACKE_zlarfx_work( int matrix_order, char side, lapack_int m,\n                                lapack_int n, const lapack_complex_double* v,\n                                lapack_complex_double tau,\n                                lapack_complex_double* c, lapack_int ldc,\n                                lapack_complex_double* work );\n\nlapack_int LAPACKE_slarnv_work( lapack_int idist, lapack_int* iseed,\n                                lapack_int n, float* x );\nlapack_int LAPACKE_dlarnv_work( lapack_int idist, lapack_int* iseed,\n                                lapack_int n, double* x );\nlapack_int LAPACKE_clarnv_work( lapack_int idist, lapack_int* iseed,\n                                lapack_int n, lapack_complex_float* x );\nlapack_int LAPACKE_zlarnv_work( lapack_int idist, lapack_int* iseed,\n                                lapack_int n, lapack_complex_double* x );\n\nlapack_int LAPACKE_slaset_work( int matrix_order, char uplo, lapack_int m,\n                                lapack_int n, float alpha, float beta, float* a,\n                                lapack_int lda );\nlapack_int LAPACKE_dlaset_work( int matrix_order, char uplo, lapack_int m,\n                                lapack_int n, double alpha, double beta,\n                                double* a, lapack_int lda );\nlapack_int LAPACKE_claset_work( int matrix_order, char uplo, lapack_int m,\n                                lapack_int n, lapack_complex_float alpha,\n                                lapack_complex_float beta,\n                                lapack_complex_float* a, lapack_int lda );\nlapack_int LAPACKE_zlaset_work( int matrix_order, char uplo, lapack_int m,\n                                lapack_int n, lapack_complex_double alpha,\n                                lapack_complex_double beta,\n                                lapack_complex_double* a, lapack_int lda );\n\nlapack_int LAPACKE_slasrt_work( char id, lapack_int n, float* d );\nlapack_int LAPACKE_dlasrt_work( char id, lapack_int n, double* d );\n\nlapack_int LAPACKE_slaswp_work( int matrix_order, lapack_int n, float* a,\n                                lapack_int lda, lapack_int k1, lapack_int k2,\n                                const lapack_int* ipiv, lapack_int incx );\nlapack_int LAPACKE_dlaswp_work( int matrix_order, lapack_int n, double* a,\n                                lapack_int lda, lapack_int k1, lapack_int k2,\n                                const lapack_int* ipiv, lapack_int incx );\nlapack_int LAPACKE_claswp_work( int matrix_order, lapack_int n,\n                                lapack_complex_float* a, lapack_int lda,\n                                lapack_int k1, lapack_int k2,\n                                const lapack_int* ipiv, lapack_int incx );\nlapack_int LAPACKE_zlaswp_work( int matrix_order, lapack_int n,\n                                lapack_complex_double* a, lapack_int lda,\n                                lapack_int k1, lapack_int k2,\n                                const lapack_int* ipiv, lapack_int incx );\n\nlapack_int LAPACKE_slatms_work( int matrix_order, lapack_int m, lapack_int n,\n                                char dist, lapack_int* iseed, char sym,\n                                float* d, lapack_int mode, float cond,\n                                float dmax, lapack_int kl, lapack_int ku,\n                                char pack, float* a, lapack_int lda,\n                                float* work );\nlapack_int LAPACKE_dlatms_work( int matrix_order, lapack_int m, lapack_int n,\n                                char dist, lapack_int* iseed, char sym,\n                                double* d, lapack_int mode, double cond,\n                                double dmax, lapack_int kl, lapack_int ku,\n                                char pack, double* a, lapack_int lda,\n                                double* work );\nlapack_int LAPACKE_clatms_work( int matrix_order, lapack_int m, lapack_int n,\n                                char dist, lapack_int* iseed, char sym,\n                                float* d, lapack_int mode, float cond,\n                                float dmax, lapack_int kl, lapack_int ku,\n                                char pack, lapack_complex_float* a,\n                                lapack_int lda, lapack_complex_float* work );\nlapack_int LAPACKE_zlatms_work( int matrix_order, lapack_int m, lapack_int n,\n                                char dist, lapack_int* iseed, char sym,\n                                double* d, lapack_int mode, double cond,\n                                double dmax, lapack_int kl, lapack_int ku,\n                                char pack, lapack_complex_double* a,\n                                lapack_int lda, lapack_complex_double* work );\n\nlapack_int LAPACKE_slauum_work( int matrix_order, char uplo, lapack_int n,\n                                float* a, lapack_int lda );\nlapack_int LAPACKE_dlauum_work( int matrix_order, char uplo, lapack_int n,\n                                double* a, lapack_int lda );\nlapack_int LAPACKE_clauum_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_complex_float* a, lapack_int lda );\nlapack_int LAPACKE_zlauum_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_complex_double* a, lapack_int lda );\n\nlapack_int LAPACKE_sopgtr_work( int matrix_order, char uplo, lapack_int n,\n                                const float* ap, const float* tau, float* q,\n                                lapack_int ldq, float* work );\nlapack_int LAPACKE_dopgtr_work( int matrix_order, char uplo, lapack_int n,\n                                const double* ap, const double* tau, double* q,\n                                lapack_int ldq, double* work );\n\nlapack_int LAPACKE_sopmtr_work( int matrix_order, char side, char uplo,\n                                char trans, lapack_int m, lapack_int n,\n                                const float* ap, const float* tau, float* c,\n                                lapack_int ldc, float* work );\nlapack_int LAPACKE_dopmtr_work( int matrix_order, char side, char uplo,\n                                char trans, lapack_int m, lapack_int n,\n                                const double* ap, const double* tau, double* c,\n                                lapack_int ldc, double* work );\n\nlapack_int LAPACKE_sorgbr_work( int matrix_order, char vect, lapack_int m,\n                                lapack_int n, lapack_int k, float* a,\n                                lapack_int lda, const float* tau, float* work,\n                                lapack_int lwork );\nlapack_int LAPACKE_dorgbr_work( int matrix_order, char vect, lapack_int m,\n                                lapack_int n, lapack_int k, double* a,\n                                lapack_int lda, const double* tau, double* work,\n                                lapack_int lwork );\n\nlapack_int LAPACKE_sorghr_work( int matrix_order, lapack_int n, lapack_int ilo,\n                                lapack_int ihi, float* a, lapack_int lda,\n                                const float* tau, float* work,\n                                lapack_int lwork );\nlapack_int LAPACKE_dorghr_work( int matrix_order, lapack_int n, lapack_int ilo,\n                                lapack_int ihi, double* a, lapack_int lda,\n                                const double* tau, double* work,\n                                lapack_int lwork );\n\nlapack_int LAPACKE_sorglq_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int k, float* a, lapack_int lda,\n                                const float* tau, float* work,\n                                lapack_int lwork );\nlapack_int LAPACKE_dorglq_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int k, double* a, lapack_int lda,\n                                const double* tau, double* work,\n                                lapack_int lwork );\n\nlapack_int LAPACKE_sorgql_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int k, float* a, lapack_int lda,\n                                const float* tau, float* work,\n                                lapack_int lwork );\nlapack_int LAPACKE_dorgql_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int k, double* a, lapack_int lda,\n                                const double* tau, double* work,\n                                lapack_int lwork );\n\nlapack_int LAPACKE_sorgqr_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int k, float* a, lapack_int lda,\n                                const float* tau, float* work,\n                                lapack_int lwork );\nlapack_int LAPACKE_dorgqr_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int k, double* a, lapack_int lda,\n                                const double* tau, double* work,\n                                lapack_int lwork );\n\nlapack_int LAPACKE_sorgrq_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int k, float* a, lapack_int lda,\n                                const float* tau, float* work,\n                                lapack_int lwork );\nlapack_int LAPACKE_dorgrq_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int k, double* a, lapack_int lda,\n                                const double* tau, double* work,\n                                lapack_int lwork );\n\nlapack_int LAPACKE_sorgtr_work( int matrix_order, char uplo, lapack_int n,\n                                float* a, lapack_int lda, const float* tau,\n                                float* work, lapack_int lwork );\nlapack_int LAPACKE_dorgtr_work( int matrix_order, char uplo, lapack_int n,\n                                double* a, lapack_int lda, const double* tau,\n                                double* work, lapack_int lwork );\n\nlapack_int LAPACKE_sormbr_work( int matrix_order, char vect, char side,\n                                char trans, lapack_int m, lapack_int n,\n                                lapack_int k, const float* a, lapack_int lda,\n                                const float* tau, float* c, lapack_int ldc,\n                                float* work, lapack_int lwork );\nlapack_int LAPACKE_dormbr_work( int matrix_order, char vect, char side,\n                                char trans, lapack_int m, lapack_int n,\n                                lapack_int k, const double* a, lapack_int lda,\n                                const double* tau, double* c, lapack_int ldc,\n                                double* work, lapack_int lwork );\n\nlapack_int LAPACKE_sormhr_work( int matrix_order, char side, char trans,\n                                lapack_int m, lapack_int n, lapack_int ilo,\n                                lapack_int ihi, const float* a, lapack_int lda,\n                                const float* tau, float* c, lapack_int ldc,\n                                float* work, lapack_int lwork );\nlapack_int LAPACKE_dormhr_work( int matrix_order, char side, char trans,\n                                lapack_int m, lapack_int n, lapack_int ilo,\n                                lapack_int ihi, const double* a, lapack_int lda,\n                                const double* tau, double* c, lapack_int ldc,\n                                double* work, lapack_int lwork );\n\nlapack_int LAPACKE_sormlq_work( int matrix_order, char side, char trans,\n                                lapack_int m, lapack_int n, lapack_int k,\n                                const float* a, lapack_int lda,\n                                const float* tau, float* c, lapack_int ldc,\n                                float* work, lapack_int lwork );\nlapack_int LAPACKE_dormlq_work( int matrix_order, char side, char trans,\n                                lapack_int m, lapack_int n, lapack_int k,\n                                const double* a, lapack_int lda,\n                                const double* tau, double* c, lapack_int ldc,\n                                double* work, lapack_int lwork );\n\nlapack_int LAPACKE_sormql_work( int matrix_order, char side, char trans,\n                                lapack_int m, lapack_int n, lapack_int k,\n                                const float* a, lapack_int lda,\n                                const float* tau, float* c, lapack_int ldc,\n                                float* work, lapack_int lwork );\nlapack_int LAPACKE_dormql_work( int matrix_order, char side, char trans,\n                                lapack_int m, lapack_int n, lapack_int k,\n                                const double* a, lapack_int lda,\n                                const double* tau, double* c, lapack_int ldc,\n                                double* work, lapack_int lwork );\n\nlapack_int LAPACKE_sormqr_work( int matrix_order, char side, char trans,\n                                lapack_int m, lapack_int n, lapack_int k,\n                                const float* a, lapack_int lda,\n                                const float* tau, float* c, lapack_int ldc,\n                                float* work, lapack_int lwork );\nlapack_int LAPACKE_dormqr_work( int matrix_order, char side, char trans,\n                                lapack_int m, lapack_int n, lapack_int k,\n                                const double* a, lapack_int lda,\n                                const double* tau, double* c, lapack_int ldc,\n                                double* work, lapack_int lwork );\n\nlapack_int LAPACKE_sormrq_work( int matrix_order, char side, char trans,\n                                lapack_int m, lapack_int n, lapack_int k,\n                                const float* a, lapack_int lda,\n                                const float* tau, float* c, lapack_int ldc,\n                                float* work, lapack_int lwork );\nlapack_int LAPACKE_dormrq_work( int matrix_order, char side, char trans,\n                                lapack_int m, lapack_int n, lapack_int k,\n                                const double* a, lapack_int lda,\n                                const double* tau, double* c, lapack_int ldc,\n                                double* work, lapack_int lwork );\n\nlapack_int LAPACKE_sormrz_work( int matrix_order, char side, char trans,\n                                lapack_int m, lapack_int n, lapack_int k,\n                                lapack_int l, const float* a, lapack_int lda,\n                                const float* tau, float* c, lapack_int ldc,\n                                float* work, lapack_int lwork );\nlapack_int LAPACKE_dormrz_work( int matrix_order, char side, char trans,\n                                lapack_int m, lapack_int n, lapack_int k,\n                                lapack_int l, const double* a, lapack_int lda,\n                                const double* tau, double* c, lapack_int ldc,\n                                double* work, lapack_int lwork );\n\nlapack_int LAPACKE_sormtr_work( int matrix_order, char side, char uplo,\n                                char trans, lapack_int m, lapack_int n,\n                                const float* a, lapack_int lda,\n                                const float* tau, float* c, lapack_int ldc,\n                                float* work, lapack_int lwork );\nlapack_int LAPACKE_dormtr_work( int matrix_order, char side, char uplo,\n                                char trans, lapack_int m, lapack_int n,\n                                const double* a, lapack_int lda,\n                                const double* tau, double* c, lapack_int ldc,\n                                double* work, lapack_int lwork );\n\nlapack_int LAPACKE_spbcon_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int kd, const float* ab, lapack_int ldab,\n                                float anorm, float* rcond, float* work,\n                                lapack_int* iwork );\nlapack_int LAPACKE_dpbcon_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int kd, const double* ab,\n                                lapack_int ldab, double anorm, double* rcond,\n                                double* work, lapack_int* iwork );\nlapack_int LAPACKE_cpbcon_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int kd, const lapack_complex_float* ab,\n                                lapack_int ldab, float anorm, float* rcond,\n                                lapack_complex_float* work, float* rwork );\nlapack_int LAPACKE_zpbcon_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int kd, const lapack_complex_double* ab,\n                                lapack_int ldab, double anorm, double* rcond,\n                                lapack_complex_double* work, double* rwork );\n\nlapack_int LAPACKE_spbequ_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int kd, const float* ab, lapack_int ldab,\n                                float* s, float* scond, float* amax );\nlapack_int LAPACKE_dpbequ_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int kd, const double* ab,\n                                lapack_int ldab, double* s, double* scond,\n                                double* amax );\nlapack_int LAPACKE_cpbequ_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int kd, const lapack_complex_float* ab,\n                                lapack_int ldab, float* s, float* scond,\n                                float* amax );\nlapack_int LAPACKE_zpbequ_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int kd, const lapack_complex_double* ab,\n                                lapack_int ldab, double* s, double* scond,\n                                double* amax );\n\nlapack_int LAPACKE_spbrfs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int kd, lapack_int nrhs, const float* ab,\n                                lapack_int ldab, const float* afb,\n                                lapack_int ldafb, const float* b,\n                                lapack_int ldb, float* x, lapack_int ldx,\n                                float* ferr, float* berr, float* work,\n                                lapack_int* iwork );\nlapack_int LAPACKE_dpbrfs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int kd, lapack_int nrhs,\n                                const double* ab, lapack_int ldab,\n                                const double* afb, lapack_int ldafb,\n                                const double* b, lapack_int ldb, double* x,\n                                lapack_int ldx, double* ferr, double* berr,\n                                double* work, lapack_int* iwork );\nlapack_int LAPACKE_cpbrfs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int kd, lapack_int nrhs,\n                                const lapack_complex_float* ab, lapack_int ldab,\n                                const lapack_complex_float* afb,\n                                lapack_int ldafb, const lapack_complex_float* b,\n                                lapack_int ldb, lapack_complex_float* x,\n                                lapack_int ldx, float* ferr, float* berr,\n                                lapack_complex_float* work, float* rwork );\nlapack_int LAPACKE_zpbrfs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int kd, lapack_int nrhs,\n                                const lapack_complex_double* ab,\n                                lapack_int ldab,\n                                const lapack_complex_double* afb,\n                                lapack_int ldafb,\n                                const lapack_complex_double* b, lapack_int ldb,\n                                lapack_complex_double* x, lapack_int ldx,\n                                double* ferr, double* berr,\n                                lapack_complex_double* work, double* rwork );\n\nlapack_int LAPACKE_spbstf_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int kb, float* bb, lapack_int ldbb );\nlapack_int LAPACKE_dpbstf_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int kb, double* bb, lapack_int ldbb );\nlapack_int LAPACKE_cpbstf_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int kb, lapack_complex_float* bb,\n                                lapack_int ldbb );\nlapack_int LAPACKE_zpbstf_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int kb, lapack_complex_double* bb,\n                                lapack_int ldbb );\n\nlapack_int LAPACKE_spbsv_work( int matrix_order, char uplo, lapack_int n,\n                               lapack_int kd, lapack_int nrhs, float* ab,\n                               lapack_int ldab, float* b, lapack_int ldb );\nlapack_int LAPACKE_dpbsv_work( int matrix_order, char uplo, lapack_int n,\n                               lapack_int kd, lapack_int nrhs, double* ab,\n                               lapack_int ldab, double* b, lapack_int ldb );\nlapack_int LAPACKE_cpbsv_work( int matrix_order, char uplo, lapack_int n,\n                               lapack_int kd, lapack_int nrhs,\n                               lapack_complex_float* ab, lapack_int ldab,\n                               lapack_complex_float* b, lapack_int ldb );\nlapack_int LAPACKE_zpbsv_work( int matrix_order, char uplo, lapack_int n,\n                               lapack_int kd, lapack_int nrhs,\n                               lapack_complex_double* ab, lapack_int ldab,\n                               lapack_complex_double* b, lapack_int ldb );\n\nlapack_int LAPACKE_spbsvx_work( int matrix_order, char fact, char uplo,\n                                lapack_int n, lapack_int kd, lapack_int nrhs,\n                                float* ab, lapack_int ldab, float* afb,\n                                lapack_int ldafb, char* equed, float* s,\n                                float* b, lapack_int ldb, float* x,\n                                lapack_int ldx, float* rcond, float* ferr,\n                                float* berr, float* work, lapack_int* iwork );\nlapack_int LAPACKE_dpbsvx_work( int matrix_order, char fact, char uplo,\n                                lapack_int n, lapack_int kd, lapack_int nrhs,\n                                double* ab, lapack_int ldab, double* afb,\n                                lapack_int ldafb, char* equed, double* s,\n                                double* b, lapack_int ldb, double* x,\n                                lapack_int ldx, double* rcond, double* ferr,\n                                double* berr, double* work, lapack_int* iwork );\nlapack_int LAPACKE_cpbsvx_work( int matrix_order, char fact, char uplo,\n                                lapack_int n, lapack_int kd, lapack_int nrhs,\n                                lapack_complex_float* ab, lapack_int ldab,\n                                lapack_complex_float* afb, lapack_int ldafb,\n                                char* equed, float* s, lapack_complex_float* b,\n                                lapack_int ldb, lapack_complex_float* x,\n                                lapack_int ldx, float* rcond, float* ferr,\n                                float* berr, lapack_complex_float* work,\n                                float* rwork );\nlapack_int LAPACKE_zpbsvx_work( int matrix_order, char fact, char uplo,\n                                lapack_int n, lapack_int kd, lapack_int nrhs,\n                                lapack_complex_double* ab, lapack_int ldab,\n                                lapack_complex_double* afb, lapack_int ldafb,\n                                char* equed, double* s,\n                                lapack_complex_double* b, lapack_int ldb,\n                                lapack_complex_double* x, lapack_int ldx,\n                                double* rcond, double* ferr, double* berr,\n                                lapack_complex_double* work, double* rwork );\n\nlapack_int LAPACKE_spbtrf_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int kd, float* ab, lapack_int ldab );\nlapack_int LAPACKE_dpbtrf_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int kd, double* ab, lapack_int ldab );\nlapack_int LAPACKE_cpbtrf_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int kd, lapack_complex_float* ab,\n                                lapack_int ldab );\nlapack_int LAPACKE_zpbtrf_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int kd, lapack_complex_double* ab,\n                                lapack_int ldab );\n\nlapack_int LAPACKE_spbtrs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int kd, lapack_int nrhs, const float* ab,\n                                lapack_int ldab, float* b, lapack_int ldb );\nlapack_int LAPACKE_dpbtrs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int kd, lapack_int nrhs,\n                                const double* ab, lapack_int ldab, double* b,\n                                lapack_int ldb );\nlapack_int LAPACKE_cpbtrs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int kd, lapack_int nrhs,\n                                const lapack_complex_float* ab, lapack_int ldab,\n                                lapack_complex_float* b, lapack_int ldb );\nlapack_int LAPACKE_zpbtrs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int kd, lapack_int nrhs,\n                                const lapack_complex_double* ab,\n                                lapack_int ldab, lapack_complex_double* b,\n                                lapack_int ldb );\n\nlapack_int LAPACKE_spftrf_work( int matrix_order, char transr, char uplo,\n                                lapack_int n, float* a );\nlapack_int LAPACKE_dpftrf_work( int matrix_order, char transr, char uplo,\n                                lapack_int n, double* a );\nlapack_int LAPACKE_cpftrf_work( int matrix_order, char transr, char uplo,\n                                lapack_int n, lapack_complex_float* a );\nlapack_int LAPACKE_zpftrf_work( int matrix_order, char transr, char uplo,\n                                lapack_int n, lapack_complex_double* a );\n\nlapack_int LAPACKE_spftri_work( int matrix_order, char transr, char uplo,\n                                lapack_int n, float* a );\nlapack_int LAPACKE_dpftri_work( int matrix_order, char transr, char uplo,\n                                lapack_int n, double* a );\nlapack_int LAPACKE_cpftri_work( int matrix_order, char transr, char uplo,\n                                lapack_int n, lapack_complex_float* a );\nlapack_int LAPACKE_zpftri_work( int matrix_order, char transr, char uplo,\n                                lapack_int n, lapack_complex_double* a );\n\nlapack_int LAPACKE_spftrs_work( int matrix_order, char transr, char uplo,\n                                lapack_int n, lapack_int nrhs, const float* a,\n                                float* b, lapack_int ldb );\nlapack_int LAPACKE_dpftrs_work( int matrix_order, char transr, char uplo,\n                                lapack_int n, lapack_int nrhs, const double* a,\n                                double* b, lapack_int ldb );\nlapack_int LAPACKE_cpftrs_work( int matrix_order, char transr, char uplo,\n                                lapack_int n, lapack_int nrhs,\n                                const lapack_complex_float* a,\n                                lapack_complex_float* b, lapack_int ldb );\nlapack_int LAPACKE_zpftrs_work( int matrix_order, char transr, char uplo,\n                                lapack_int n, lapack_int nrhs,\n                                const lapack_complex_double* a,\n                                lapack_complex_double* b, lapack_int ldb );\n\nlapack_int LAPACKE_spocon_work( int matrix_order, char uplo, lapack_int n,\n                                const float* a, lapack_int lda, float anorm,\n                                float* rcond, float* work, lapack_int* iwork );\nlapack_int LAPACKE_dpocon_work( int matrix_order, char uplo, lapack_int n,\n                                const double* a, lapack_int lda, double anorm,\n                                double* rcond, double* work,\n                                lapack_int* iwork );\nlapack_int LAPACKE_cpocon_work( int matrix_order, char uplo, lapack_int n,\n                                const lapack_complex_float* a, lapack_int lda,\n                                float anorm, float* rcond,\n                                lapack_complex_float* work, float* rwork );\nlapack_int LAPACKE_zpocon_work( int matrix_order, char uplo, lapack_int n,\n                                const lapack_complex_double* a, lapack_int lda,\n                                double anorm, double* rcond,\n                                lapack_complex_double* work, double* rwork );\n\nlapack_int LAPACKE_spoequ_work( int matrix_order, lapack_int n, const float* a,\n                                lapack_int lda, float* s, float* scond,\n                                float* amax );\nlapack_int LAPACKE_dpoequ_work( int matrix_order, lapack_int n, const double* a,\n                                lapack_int lda, double* s, double* scond,\n                                double* amax );\nlapack_int LAPACKE_cpoequ_work( int matrix_order, lapack_int n,\n                                const lapack_complex_float* a, lapack_int lda,\n                                float* s, float* scond, float* amax );\nlapack_int LAPACKE_zpoequ_work( int matrix_order, lapack_int n,\n                                const lapack_complex_double* a, lapack_int lda,\n                                double* s, double* scond, double* amax );\n\nlapack_int LAPACKE_spoequb_work( int matrix_order, lapack_int n, const float* a,\n                                 lapack_int lda, float* s, float* scond,\n                                 float* amax );\nlapack_int LAPACKE_dpoequb_work( int matrix_order, lapack_int n,\n                                 const double* a, lapack_int lda, double* s,\n                                 double* scond, double* amax );\nlapack_int LAPACKE_cpoequb_work( int matrix_order, lapack_int n,\n                                 const lapack_complex_float* a, lapack_int lda,\n                                 float* s, float* scond, float* amax );\nlapack_int LAPACKE_zpoequb_work( int matrix_order, lapack_int n,\n                                 const lapack_complex_double* a, lapack_int lda,\n                                 double* s, double* scond, double* amax );\n\nlapack_int LAPACKE_sporfs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const float* a, lapack_int lda,\n                                const float* af, lapack_int ldaf,\n                                const float* b, lapack_int ldb, float* x,\n                                lapack_int ldx, float* ferr, float* berr,\n                                float* work, lapack_int* iwork );\nlapack_int LAPACKE_dporfs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const double* a,\n                                lapack_int lda, const double* af,\n                                lapack_int ldaf, const double* b,\n                                lapack_int ldb, double* x, lapack_int ldx,\n                                double* ferr, double* berr, double* work,\n                                lapack_int* iwork );\nlapack_int LAPACKE_cporfs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const lapack_complex_float* a,\n                                lapack_int lda, const lapack_complex_float* af,\n                                lapack_int ldaf, const lapack_complex_float* b,\n                                lapack_int ldb, lapack_complex_float* x,\n                                lapack_int ldx, float* ferr, float* berr,\n                                lapack_complex_float* work, float* rwork );\nlapack_int LAPACKE_zporfs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const lapack_complex_double* a,\n                                lapack_int lda, const lapack_complex_double* af,\n                                lapack_int ldaf, const lapack_complex_double* b,\n                                lapack_int ldb, lapack_complex_double* x,\n                                lapack_int ldx, double* ferr, double* berr,\n                                lapack_complex_double* work, double* rwork );\n\nlapack_int LAPACKE_sporfsx_work( int matrix_order, char uplo, char equed,\n                                 lapack_int n, lapack_int nrhs, const float* a,\n                                 lapack_int lda, const float* af,\n                                 lapack_int ldaf, const float* s,\n                                 const float* b, lapack_int ldb, float* x,\n                                 lapack_int ldx, float* rcond, float* berr,\n                                 lapack_int n_err_bnds, float* err_bnds_norm,\n                                 float* err_bnds_comp, lapack_int nparams,\n                                 float* params, float* work,\n                                 lapack_int* iwork );\nlapack_int LAPACKE_dporfsx_work( int matrix_order, char uplo, char equed,\n                                 lapack_int n, lapack_int nrhs, const double* a,\n                                 lapack_int lda, const double* af,\n                                 lapack_int ldaf, const double* s,\n                                 const double* b, lapack_int ldb, double* x,\n                                 lapack_int ldx, double* rcond, double* berr,\n                                 lapack_int n_err_bnds, double* err_bnds_norm,\n                                 double* err_bnds_comp, lapack_int nparams,\n                                 double* params, double* work,\n                                 lapack_int* iwork );\nlapack_int LAPACKE_cporfsx_work( int matrix_order, char uplo, char equed,\n                                 lapack_int n, lapack_int nrhs,\n                                 const lapack_complex_float* a, lapack_int lda,\n                                 const lapack_complex_float* af,\n                                 lapack_int ldaf, const float* s,\n                                 const lapack_complex_float* b, lapack_int ldb,\n                                 lapack_complex_float* x, lapack_int ldx,\n                                 float* rcond, float* berr,\n                                 lapack_int n_err_bnds, float* err_bnds_norm,\n                                 float* err_bnds_comp, lapack_int nparams,\n                                 float* params, lapack_complex_float* work,\n                                 float* rwork );\nlapack_int LAPACKE_zporfsx_work( int matrix_order, char uplo, char equed,\n                                 lapack_int n, lapack_int nrhs,\n                                 const lapack_complex_double* a, lapack_int lda,\n                                 const lapack_complex_double* af,\n                                 lapack_int ldaf, const double* s,\n                                 const lapack_complex_double* b, lapack_int ldb,\n                                 lapack_complex_double* x, lapack_int ldx,\n                                 double* rcond, double* berr,\n                                 lapack_int n_err_bnds, double* err_bnds_norm,\n                                 double* err_bnds_comp, lapack_int nparams,\n                                 double* params, lapack_complex_double* work,\n                                 double* rwork );\n\nlapack_int LAPACKE_sposv_work( int matrix_order, char uplo, lapack_int n,\n                               lapack_int nrhs, float* a, lapack_int lda,\n                               float* b, lapack_int ldb );\nlapack_int LAPACKE_dposv_work( int matrix_order, char uplo, lapack_int n,\n                               lapack_int nrhs, double* a, lapack_int lda,\n                               double* b, lapack_int ldb );\nlapack_int LAPACKE_cposv_work( int matrix_order, char uplo, lapack_int n,\n                               lapack_int nrhs, lapack_complex_float* a,\n                               lapack_int lda, lapack_complex_float* b,\n                               lapack_int ldb );\nlapack_int LAPACKE_zposv_work( int matrix_order, char uplo, lapack_int n,\n                               lapack_int nrhs, lapack_complex_double* a,\n                               lapack_int lda, lapack_complex_double* b,\n                               lapack_int ldb );\nlapack_int LAPACKE_dsposv_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, double* a, lapack_int lda,\n                                double* b, lapack_int ldb, double* x,\n                                lapack_int ldx, double* work, float* swork,\n                                lapack_int* iter );\nlapack_int LAPACKE_zcposv_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, lapack_complex_double* a,\n                                lapack_int lda, lapack_complex_double* b,\n                                lapack_int ldb, lapack_complex_double* x,\n                                lapack_int ldx, lapack_complex_double* work,\n                                lapack_complex_float* swork, double* rwork,\n                                lapack_int* iter );\n\nlapack_int LAPACKE_sposvx_work( int matrix_order, char fact, char uplo,\n                                lapack_int n, lapack_int nrhs, float* a,\n                                lapack_int lda, float* af, lapack_int ldaf,\n                                char* equed, float* s, float* b, lapack_int ldb,\n                                float* x, lapack_int ldx, float* rcond,\n                                float* ferr, float* berr, float* work,\n                                lapack_int* iwork );\nlapack_int LAPACKE_dposvx_work( int matrix_order, char fact, char uplo,\n                                lapack_int n, lapack_int nrhs, double* a,\n                                lapack_int lda, double* af, lapack_int ldaf,\n                                char* equed, double* s, double* b,\n                                lapack_int ldb, double* x, lapack_int ldx,\n                                double* rcond, double* ferr, double* berr,\n                                double* work, lapack_int* iwork );\nlapack_int LAPACKE_cposvx_work( int matrix_order, char fact, char uplo,\n                                lapack_int n, lapack_int nrhs,\n                                lapack_complex_float* a, lapack_int lda,\n                                lapack_complex_float* af, lapack_int ldaf,\n                                char* equed, float* s, lapack_complex_float* b,\n                                lapack_int ldb, lapack_complex_float* x,\n                                lapack_int ldx, float* rcond, float* ferr,\n                                float* berr, lapack_complex_float* work,\n                                float* rwork );\nlapack_int LAPACKE_zposvx_work( int matrix_order, char fact, char uplo,\n                                lapack_int n, lapack_int nrhs,\n                                lapack_complex_double* a, lapack_int lda,\n                                lapack_complex_double* af, lapack_int ldaf,\n                                char* equed, double* s,\n                                lapack_complex_double* b, lapack_int ldb,\n                                lapack_complex_double* x, lapack_int ldx,\n                                double* rcond, double* ferr, double* berr,\n                                lapack_complex_double* work, double* rwork );\n\nlapack_int LAPACKE_sposvxx_work( int matrix_order, char fact, char uplo,\n                                 lapack_int n, lapack_int nrhs, float* a,\n                                 lapack_int lda, float* af, lapack_int ldaf,\n                                 char* equed, float* s, float* b,\n                                 lapack_int ldb, float* x, lapack_int ldx,\n                                 float* rcond, float* rpvgrw, float* berr,\n                                 lapack_int n_err_bnds, float* err_bnds_norm,\n                                 float* err_bnds_comp, lapack_int nparams,\n                                 float* params, float* work,\n                                 lapack_int* iwork );\nlapack_int LAPACKE_dposvxx_work( int matrix_order, char fact, char uplo,\n                                 lapack_int n, lapack_int nrhs, double* a,\n                                 lapack_int lda, double* af, lapack_int ldaf,\n                                 char* equed, double* s, double* b,\n                                 lapack_int ldb, double* x, lapack_int ldx,\n                                 double* rcond, double* rpvgrw, double* berr,\n                                 lapack_int n_err_bnds, double* err_bnds_norm,\n                                 double* err_bnds_comp, lapack_int nparams,\n                                 double* params, double* work,\n                                 lapack_int* iwork );\nlapack_int LAPACKE_cposvxx_work( int matrix_order, char fact, char uplo,\n                                 lapack_int n, lapack_int nrhs,\n                                 lapack_complex_float* a, lapack_int lda,\n                                 lapack_complex_float* af, lapack_int ldaf,\n                                 char* equed, float* s, lapack_complex_float* b,\n                                 lapack_int ldb, lapack_complex_float* x,\n                                 lapack_int ldx, float* rcond, float* rpvgrw,\n                                 float* berr, lapack_int n_err_bnds,\n                                 float* err_bnds_norm, float* err_bnds_comp,\n                                 lapack_int nparams, float* params,\n                                 lapack_complex_float* work, float* rwork );\nlapack_int LAPACKE_zposvxx_work( int matrix_order, char fact, char uplo,\n                                 lapack_int n, lapack_int nrhs,\n                                 lapack_complex_double* a, lapack_int lda,\n                                 lapack_complex_double* af, lapack_int ldaf,\n                                 char* equed, double* s,\n                                 lapack_complex_double* b, lapack_int ldb,\n                                 lapack_complex_double* x, lapack_int ldx,\n                                 double* rcond, double* rpvgrw, double* berr,\n                                 lapack_int n_err_bnds, double* err_bnds_norm,\n                                 double* err_bnds_comp, lapack_int nparams,\n                                 double* params, lapack_complex_double* work,\n                                 double* rwork );\n\nlapack_int LAPACKE_spotrf_work( int matrix_order, char uplo, lapack_int n,\n                                float* a, lapack_int lda );\nlapack_int LAPACKE_dpotrf_work( int matrix_order, char uplo, lapack_int n,\n                                double* a, lapack_int lda );\nlapack_int LAPACKE_cpotrf_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_complex_float* a, lapack_int lda );\nlapack_int LAPACKE_zpotrf_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_complex_double* a, lapack_int lda );\n\nlapack_int LAPACKE_spotri_work( int matrix_order, char uplo, lapack_int n,\n                                float* a, lapack_int lda );\nlapack_int LAPACKE_dpotri_work( int matrix_order, char uplo, lapack_int n,\n                                double* a, lapack_int lda );\nlapack_int LAPACKE_cpotri_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_complex_float* a, lapack_int lda );\nlapack_int LAPACKE_zpotri_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_complex_double* a, lapack_int lda );\n\nlapack_int LAPACKE_spotrs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const float* a, lapack_int lda,\n                                float* b, lapack_int ldb );\nlapack_int LAPACKE_dpotrs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const double* a,\n                                lapack_int lda, double* b, lapack_int ldb );\nlapack_int LAPACKE_cpotrs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const lapack_complex_float* a,\n                                lapack_int lda, lapack_complex_float* b,\n                                lapack_int ldb );\nlapack_int LAPACKE_zpotrs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const lapack_complex_double* a,\n                                lapack_int lda, lapack_complex_double* b,\n                                lapack_int ldb );\n\nlapack_int LAPACKE_sppcon_work( int matrix_order, char uplo, lapack_int n,\n                                const float* ap, float anorm, float* rcond,\n                                float* work, lapack_int* iwork );\nlapack_int LAPACKE_dppcon_work( int matrix_order, char uplo, lapack_int n,\n                                const double* ap, double anorm, double* rcond,\n                                double* work, lapack_int* iwork );\nlapack_int LAPACKE_cppcon_work( int matrix_order, char uplo, lapack_int n,\n                                const lapack_complex_float* ap, float anorm,\n                                float* rcond, lapack_complex_float* work,\n                                float* rwork );\nlapack_int LAPACKE_zppcon_work( int matrix_order, char uplo, lapack_int n,\n                                const lapack_complex_double* ap, double anorm,\n                                double* rcond, lapack_complex_double* work,\n                                double* rwork );\n\nlapack_int LAPACKE_sppequ_work( int matrix_order, char uplo, lapack_int n,\n                                const float* ap, float* s, float* scond,\n                                float* amax );\nlapack_int LAPACKE_dppequ_work( int matrix_order, char uplo, lapack_int n,\n                                const double* ap, double* s, double* scond,\n                                double* amax );\nlapack_int LAPACKE_cppequ_work( int matrix_order, char uplo, lapack_int n,\n                                const lapack_complex_float* ap, float* s,\n                                float* scond, float* amax );\nlapack_int LAPACKE_zppequ_work( int matrix_order, char uplo, lapack_int n,\n                                const lapack_complex_double* ap, double* s,\n                                double* scond, double* amax );\n\nlapack_int LAPACKE_spprfs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const float* ap,\n                                const float* afp, const float* b,\n                                lapack_int ldb, float* x, lapack_int ldx,\n                                float* ferr, float* berr, float* work,\n                                lapack_int* iwork );\nlapack_int LAPACKE_dpprfs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const double* ap,\n                                const double* afp, const double* b,\n                                lapack_int ldb, double* x, lapack_int ldx,\n                                double* ferr, double* berr, double* work,\n                                lapack_int* iwork );\nlapack_int LAPACKE_cpprfs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const lapack_complex_float* ap,\n                                const lapack_complex_float* afp,\n                                const lapack_complex_float* b, lapack_int ldb,\n                                lapack_complex_float* x, lapack_int ldx,\n                                float* ferr, float* berr,\n                                lapack_complex_float* work, float* rwork );\nlapack_int LAPACKE_zpprfs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs,\n                                const lapack_complex_double* ap,\n                                const lapack_complex_double* afp,\n                                const lapack_complex_double* b, lapack_int ldb,\n                                lapack_complex_double* x, lapack_int ldx,\n                                double* ferr, double* berr,\n                                lapack_complex_double* work, double* rwork );\n\nlapack_int LAPACKE_sppsv_work( int matrix_order, char uplo, lapack_int n,\n                               lapack_int nrhs, float* ap, float* b,\n                               lapack_int ldb );\nlapack_int LAPACKE_dppsv_work( int matrix_order, char uplo, lapack_int n,\n                               lapack_int nrhs, double* ap, double* b,\n                               lapack_int ldb );\nlapack_int LAPACKE_cppsv_work( int matrix_order, char uplo, lapack_int n,\n                               lapack_int nrhs, lapack_complex_float* ap,\n                               lapack_complex_float* b, lapack_int ldb );\nlapack_int LAPACKE_zppsv_work( int matrix_order, char uplo, lapack_int n,\n                               lapack_int nrhs, lapack_complex_double* ap,\n                               lapack_complex_double* b, lapack_int ldb );\n\nlapack_int LAPACKE_sppsvx_work( int matrix_order, char fact, char uplo,\n                                lapack_int n, lapack_int nrhs, float* ap,\n                                float* afp, char* equed, float* s, float* b,\n                                lapack_int ldb, float* x, lapack_int ldx,\n                                float* rcond, float* ferr, float* berr,\n                                float* work, lapack_int* iwork );\nlapack_int LAPACKE_dppsvx_work( int matrix_order, char fact, char uplo,\n                                lapack_int n, lapack_int nrhs, double* ap,\n                                double* afp, char* equed, double* s, double* b,\n                                lapack_int ldb, double* x, lapack_int ldx,\n                                double* rcond, double* ferr, double* berr,\n                                double* work, lapack_int* iwork );\nlapack_int LAPACKE_cppsvx_work( int matrix_order, char fact, char uplo,\n                                lapack_int n, lapack_int nrhs,\n                                lapack_complex_float* ap,\n                                lapack_complex_float* afp, char* equed,\n                                float* s, lapack_complex_float* b,\n                                lapack_int ldb, lapack_complex_float* x,\n                                lapack_int ldx, float* rcond, float* ferr,\n                                float* berr, lapack_complex_float* work,\n                                float* rwork );\nlapack_int LAPACKE_zppsvx_work( int matrix_order, char fact, char uplo,\n                                lapack_int n, lapack_int nrhs,\n                                lapack_complex_double* ap,\n                                lapack_complex_double* afp, char* equed,\n                                double* s, lapack_complex_double* b,\n                                lapack_int ldb, lapack_complex_double* x,\n                                lapack_int ldx, double* rcond, double* ferr,\n                                double* berr, lapack_complex_double* work,\n                                double* rwork );\n\nlapack_int LAPACKE_spptrf_work( int matrix_order, char uplo, lapack_int n,\n                                float* ap );\nlapack_int LAPACKE_dpptrf_work( int matrix_order, char uplo, lapack_int n,\n                                double* ap );\nlapack_int LAPACKE_cpptrf_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_complex_float* ap );\nlapack_int LAPACKE_zpptrf_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_complex_double* ap );\n\nlapack_int LAPACKE_spptri_work( int matrix_order, char uplo, lapack_int n,\n                                float* ap );\nlapack_int LAPACKE_dpptri_work( int matrix_order, char uplo, lapack_int n,\n                                double* ap );\nlapack_int LAPACKE_cpptri_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_complex_float* ap );\nlapack_int LAPACKE_zpptri_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_complex_double* ap );\n\nlapack_int LAPACKE_spptrs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const float* ap, float* b,\n                                lapack_int ldb );\nlapack_int LAPACKE_dpptrs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const double* ap, double* b,\n                                lapack_int ldb );\nlapack_int LAPACKE_cpptrs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const lapack_complex_float* ap,\n                                lapack_complex_float* b, lapack_int ldb );\nlapack_int LAPACKE_zpptrs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs,\n                                const lapack_complex_double* ap,\n                                lapack_complex_double* b, lapack_int ldb );\n\nlapack_int LAPACKE_spstrf_work( int matrix_order, char uplo, lapack_int n,\n                                float* a, lapack_int lda, lapack_int* piv,\n                                lapack_int* rank, float tol, float* work );\nlapack_int LAPACKE_dpstrf_work( int matrix_order, char uplo, lapack_int n,\n                                double* a, lapack_int lda, lapack_int* piv,\n                                lapack_int* rank, double tol, double* work );\nlapack_int LAPACKE_cpstrf_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_complex_float* a, lapack_int lda,\n                                lapack_int* piv, lapack_int* rank, float tol,\n                                float* work );\nlapack_int LAPACKE_zpstrf_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_complex_double* a, lapack_int lda,\n                                lapack_int* piv, lapack_int* rank, double tol,\n                                double* work );\n\nlapack_int LAPACKE_sptcon_work( lapack_int n, const float* d, const float* e,\n                                float anorm, float* rcond, float* work );\nlapack_int LAPACKE_dptcon_work( lapack_int n, const double* d, const double* e,\n                                double anorm, double* rcond, double* work );\nlapack_int LAPACKE_cptcon_work( lapack_int n, const float* d,\n                                const lapack_complex_float* e, float anorm,\n                                float* rcond, float* work );\nlapack_int LAPACKE_zptcon_work( lapack_int n, const double* d,\n                                const lapack_complex_double* e, double anorm,\n                                double* rcond, double* work );\n\nlapack_int LAPACKE_spteqr_work( int matrix_order, char compz, lapack_int n,\n                                float* d, float* e, float* z, lapack_int ldz,\n                                float* work );\nlapack_int LAPACKE_dpteqr_work( int matrix_order, char compz, lapack_int n,\n                                double* d, double* e, double* z, lapack_int ldz,\n                                double* work );\nlapack_int LAPACKE_cpteqr_work( int matrix_order, char compz, lapack_int n,\n                                float* d, float* e, lapack_complex_float* z,\n                                lapack_int ldz, float* work );\nlapack_int LAPACKE_zpteqr_work( int matrix_order, char compz, lapack_int n,\n                                double* d, double* e, lapack_complex_double* z,\n                                lapack_int ldz, double* work );\n\nlapack_int LAPACKE_sptrfs_work( int matrix_order, lapack_int n, lapack_int nrhs,\n                                const float* d, const float* e, const float* df,\n                                const float* ef, const float* b, lapack_int ldb,\n                                float* x, lapack_int ldx, float* ferr,\n                                float* berr, float* work );\nlapack_int LAPACKE_dptrfs_work( int matrix_order, lapack_int n, lapack_int nrhs,\n                                const double* d, const double* e,\n                                const double* df, const double* ef,\n                                const double* b, lapack_int ldb, double* x,\n                                lapack_int ldx, double* ferr, double* berr,\n                                double* work );\nlapack_int LAPACKE_cptrfs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const float* d,\n                                const lapack_complex_float* e, const float* df,\n                                const lapack_complex_float* ef,\n                                const lapack_complex_float* b, lapack_int ldb,\n                                lapack_complex_float* x, lapack_int ldx,\n                                float* ferr, float* berr,\n                                lapack_complex_float* work, float* rwork );\nlapack_int LAPACKE_zptrfs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const double* d,\n                                const lapack_complex_double* e,\n                                const double* df,\n                                const lapack_complex_double* ef,\n                                const lapack_complex_double* b, lapack_int ldb,\n                                lapack_complex_double* x, lapack_int ldx,\n                                double* ferr, double* berr,\n                                lapack_complex_double* work, double* rwork );\n\nlapack_int LAPACKE_sptsv_work( int matrix_order, lapack_int n, lapack_int nrhs,\n                               float* d, float* e, float* b, lapack_int ldb );\nlapack_int LAPACKE_dptsv_work( int matrix_order, lapack_int n, lapack_int nrhs,\n                               double* d, double* e, double* b,\n                               lapack_int ldb );\nlapack_int LAPACKE_cptsv_work( int matrix_order, lapack_int n, lapack_int nrhs,\n                               float* d, lapack_complex_float* e,\n                               lapack_complex_float* b, lapack_int ldb );\nlapack_int LAPACKE_zptsv_work( int matrix_order, lapack_int n, lapack_int nrhs,\n                               double* d, lapack_complex_double* e,\n                               lapack_complex_double* b, lapack_int ldb );\n\nlapack_int LAPACKE_sptsvx_work( int matrix_order, char fact, lapack_int n,\n                                lapack_int nrhs, const float* d, const float* e,\n                                float* df, float* ef, const float* b,\n                                lapack_int ldb, float* x, lapack_int ldx,\n                                float* rcond, float* ferr, float* berr,\n                                float* work );\nlapack_int LAPACKE_dptsvx_work( int matrix_order, char fact, lapack_int n,\n                                lapack_int nrhs, const double* d,\n                                const double* e, double* df, double* ef,\n                                const double* b, lapack_int ldb, double* x,\n                                lapack_int ldx, double* rcond, double* ferr,\n                                double* berr, double* work );\nlapack_int LAPACKE_cptsvx_work( int matrix_order, char fact, lapack_int n,\n                                lapack_int nrhs, const float* d,\n                                const lapack_complex_float* e, float* df,\n                                lapack_complex_float* ef,\n                                const lapack_complex_float* b, lapack_int ldb,\n                                lapack_complex_float* x, lapack_int ldx,\n                                float* rcond, float* ferr, float* berr,\n                                lapack_complex_float* work, float* rwork );\nlapack_int LAPACKE_zptsvx_work( int matrix_order, char fact, lapack_int n,\n                                lapack_int nrhs, const double* d,\n                                const lapack_complex_double* e, double* df,\n                                lapack_complex_double* ef,\n                                const lapack_complex_double* b, lapack_int ldb,\n                                lapack_complex_double* x, lapack_int ldx,\n                                double* rcond, double* ferr, double* berr,\n                                lapack_complex_double* work, double* rwork );\n\nlapack_int LAPACKE_spttrf_work( lapack_int n, float* d, float* e );\nlapack_int LAPACKE_dpttrf_work( lapack_int n, double* d, double* e );\nlapack_int LAPACKE_cpttrf_work( lapack_int n, float* d,\n                                lapack_complex_float* e );\nlapack_int LAPACKE_zpttrf_work( lapack_int n, double* d,\n                                lapack_complex_double* e );\n\nlapack_int LAPACKE_spttrs_work( int matrix_order, lapack_int n, lapack_int nrhs,\n                                const float* d, const float* e, float* b,\n                                lapack_int ldb );\nlapack_int LAPACKE_dpttrs_work( int matrix_order, lapack_int n, lapack_int nrhs,\n                                const double* d, const double* e, double* b,\n                                lapack_int ldb );\nlapack_int LAPACKE_cpttrs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const float* d,\n                                const lapack_complex_float* e,\n                                lapack_complex_float* b, lapack_int ldb );\nlapack_int LAPACKE_zpttrs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const double* d,\n                                const lapack_complex_double* e,\n                                lapack_complex_double* b, lapack_int ldb );\n\nlapack_int LAPACKE_ssbev_work( int matrix_order, char jobz, char uplo,\n                               lapack_int n, lapack_int kd, float* ab,\n                               lapack_int ldab, float* w, float* z,\n                               lapack_int ldz, float* work );\nlapack_int LAPACKE_dsbev_work( int matrix_order, char jobz, char uplo,\n                               lapack_int n, lapack_int kd, double* ab,\n                               lapack_int ldab, double* w, double* z,\n                               lapack_int ldz, double* work );\n\nlapack_int LAPACKE_ssbevd_work( int matrix_order, char jobz, char uplo,\n                                lapack_int n, lapack_int kd, float* ab,\n                                lapack_int ldab, float* w, float* z,\n                                lapack_int ldz, float* work, lapack_int lwork,\n                                lapack_int* iwork, lapack_int liwork );\nlapack_int LAPACKE_dsbevd_work( int matrix_order, char jobz, char uplo,\n                                lapack_int n, lapack_int kd, double* ab,\n                                lapack_int ldab, double* w, double* z,\n                                lapack_int ldz, double* work, lapack_int lwork,\n                                lapack_int* iwork, lapack_int liwork );\n\nlapack_int LAPACKE_ssbevx_work( int matrix_order, char jobz, char range,\n                                char uplo, lapack_int n, lapack_int kd,\n                                float* ab, lapack_int ldab, float* q,\n                                lapack_int ldq, float vl, float vu,\n                                lapack_int il, lapack_int iu, float abstol,\n                                lapack_int* m, float* w, float* z,\n                                lapack_int ldz, float* work, lapack_int* iwork,\n                                lapack_int* ifail );\nlapack_int LAPACKE_dsbevx_work( int matrix_order, char jobz, char range,\n                                char uplo, lapack_int n, lapack_int kd,\n                                double* ab, lapack_int ldab, double* q,\n                                lapack_int ldq, double vl, double vu,\n                                lapack_int il, lapack_int iu, double abstol,\n                                lapack_int* m, double* w, double* z,\n                                lapack_int ldz, double* work, lapack_int* iwork,\n                                lapack_int* ifail );\n\nlapack_int LAPACKE_ssbgst_work( int matrix_order, char vect, char uplo,\n                                lapack_int n, lapack_int ka, lapack_int kb,\n                                float* ab, lapack_int ldab, const float* bb,\n                                lapack_int ldbb, float* x, lapack_int ldx,\n                                float* work );\nlapack_int LAPACKE_dsbgst_work( int matrix_order, char vect, char uplo,\n                                lapack_int n, lapack_int ka, lapack_int kb,\n                                double* ab, lapack_int ldab, const double* bb,\n                                lapack_int ldbb, double* x, lapack_int ldx,\n                                double* work );\n\nlapack_int LAPACKE_ssbgv_work( int matrix_order, char jobz, char uplo,\n                               lapack_int n, lapack_int ka, lapack_int kb,\n                               float* ab, lapack_int ldab, float* bb,\n                               lapack_int ldbb, float* w, float* z,\n                               lapack_int ldz, float* work );\nlapack_int LAPACKE_dsbgv_work( int matrix_order, char jobz, char uplo,\n                               lapack_int n, lapack_int ka, lapack_int kb,\n                               double* ab, lapack_int ldab, double* bb,\n                               lapack_int ldbb, double* w, double* z,\n                               lapack_int ldz, double* work );\n\nlapack_int LAPACKE_ssbgvd_work( int matrix_order, char jobz, char uplo,\n                                lapack_int n, lapack_int ka, lapack_int kb,\n                                float* ab, lapack_int ldab, float* bb,\n                                lapack_int ldbb, float* w, float* z,\n                                lapack_int ldz, float* work, lapack_int lwork,\n                                lapack_int* iwork, lapack_int liwork );\nlapack_int LAPACKE_dsbgvd_work( int matrix_order, char jobz, char uplo,\n                                lapack_int n, lapack_int ka, lapack_int kb,\n                                double* ab, lapack_int ldab, double* bb,\n                                lapack_int ldbb, double* w, double* z,\n                                lapack_int ldz, double* work, lapack_int lwork,\n                                lapack_int* iwork, lapack_int liwork );\n\nlapack_int LAPACKE_ssbgvx_work( int matrix_order, char jobz, char range,\n                                char uplo, lapack_int n, lapack_int ka,\n                                lapack_int kb, float* ab, lapack_int ldab,\n                                float* bb, lapack_int ldbb, float* q,\n                                lapack_int ldq, float vl, float vu,\n                                lapack_int il, lapack_int iu, float abstol,\n                                lapack_int* m, float* w, float* z,\n                                lapack_int ldz, float* work, lapack_int* iwork,\n                                lapack_int* ifail );\nlapack_int LAPACKE_dsbgvx_work( int matrix_order, char jobz, char range,\n                                char uplo, lapack_int n, lapack_int ka,\n                                lapack_int kb, double* ab, lapack_int ldab,\n                                double* bb, lapack_int ldbb, double* q,\n                                lapack_int ldq, double vl, double vu,\n                                lapack_int il, lapack_int iu, double abstol,\n                                lapack_int* m, double* w, double* z,\n                                lapack_int ldz, double* work, lapack_int* iwork,\n                                lapack_int* ifail );\n\nlapack_int LAPACKE_ssbtrd_work( int matrix_order, char vect, char uplo,\n                                lapack_int n, lapack_int kd, float* ab,\n                                lapack_int ldab, float* d, float* e, float* q,\n                                lapack_int ldq, float* work );\nlapack_int LAPACKE_dsbtrd_work( int matrix_order, char vect, char uplo,\n                                lapack_int n, lapack_int kd, double* ab,\n                                lapack_int ldab, double* d, double* e,\n                                double* q, lapack_int ldq, double* work );\n\nlapack_int LAPACKE_ssfrk_work( int matrix_order, char transr, char uplo,\n                               char trans, lapack_int n, lapack_int k,\n                               float alpha, const float* a, lapack_int lda,\n                               float beta, float* c );\nlapack_int LAPACKE_dsfrk_work( int matrix_order, char transr, char uplo,\n                               char trans, lapack_int n, lapack_int k,\n                               double alpha, const double* a, lapack_int lda,\n                               double beta, double* c );\n\nlapack_int LAPACKE_sspcon_work( int matrix_order, char uplo, lapack_int n,\n                                const float* ap, const lapack_int* ipiv,\n                                float anorm, float* rcond, float* work,\n                                lapack_int* iwork );\nlapack_int LAPACKE_dspcon_work( int matrix_order, char uplo, lapack_int n,\n                                const double* ap, const lapack_int* ipiv,\n                                double anorm, double* rcond, double* work,\n                                lapack_int* iwork );\nlapack_int LAPACKE_cspcon_work( int matrix_order, char uplo, lapack_int n,\n                                const lapack_complex_float* ap,\n                                const lapack_int* ipiv, float anorm,\n                                float* rcond, lapack_complex_float* work );\nlapack_int LAPACKE_zspcon_work( int matrix_order, char uplo, lapack_int n,\n                                const lapack_complex_double* ap,\n                                const lapack_int* ipiv, double anorm,\n                                double* rcond, lapack_complex_double* work );\n\nlapack_int LAPACKE_sspev_work( int matrix_order, char jobz, char uplo,\n                               lapack_int n, float* ap, float* w, float* z,\n                               lapack_int ldz, float* work );\nlapack_int LAPACKE_dspev_work( int matrix_order, char jobz, char uplo,\n                               lapack_int n, double* ap, double* w, double* z,\n                               lapack_int ldz, double* work );\n\nlapack_int LAPACKE_sspevd_work( int matrix_order, char jobz, char uplo,\n                                lapack_int n, float* ap, float* w, float* z,\n                                lapack_int ldz, float* work, lapack_int lwork,\n                                lapack_int* iwork, lapack_int liwork );\nlapack_int LAPACKE_dspevd_work( int matrix_order, char jobz, char uplo,\n                                lapack_int n, double* ap, double* w, double* z,\n                                lapack_int ldz, double* work, lapack_int lwork,\n                                lapack_int* iwork, lapack_int liwork );\n\nlapack_int LAPACKE_sspevx_work( int matrix_order, char jobz, char range,\n                                char uplo, lapack_int n, float* ap, float vl,\n                                float vu, lapack_int il, lapack_int iu,\n                                float abstol, lapack_int* m, float* w, float* z,\n                                lapack_int ldz, float* work, lapack_int* iwork,\n                                lapack_int* ifail );\nlapack_int LAPACKE_dspevx_work( int matrix_order, char jobz, char range,\n                                char uplo, lapack_int n, double* ap, double vl,\n                                double vu, lapack_int il, lapack_int iu,\n                                double abstol, lapack_int* m, double* w,\n                                double* z, lapack_int ldz, double* work,\n                                lapack_int* iwork, lapack_int* ifail );\n\nlapack_int LAPACKE_sspgst_work( int matrix_order, lapack_int itype, char uplo,\n                                lapack_int n, float* ap, const float* bp );\nlapack_int LAPACKE_dspgst_work( int matrix_order, lapack_int itype, char uplo,\n                                lapack_int n, double* ap, const double* bp );\n\nlapack_int LAPACKE_sspgv_work( int matrix_order, lapack_int itype, char jobz,\n                               char uplo, lapack_int n, float* ap, float* bp,\n                               float* w, float* z, lapack_int ldz,\n                               float* work );\nlapack_int LAPACKE_dspgv_work( int matrix_order, lapack_int itype, char jobz,\n                               char uplo, lapack_int n, double* ap, double* bp,\n                               double* w, double* z, lapack_int ldz,\n                               double* work );\n\nlapack_int LAPACKE_sspgvd_work( int matrix_order, lapack_int itype, char jobz,\n                                char uplo, lapack_int n, float* ap, float* bp,\n                                float* w, float* z, lapack_int ldz, float* work,\n                                lapack_int lwork, lapack_int* iwork,\n                                lapack_int liwork );\nlapack_int LAPACKE_dspgvd_work( int matrix_order, lapack_int itype, char jobz,\n                                char uplo, lapack_int n, double* ap, double* bp,\n                                double* w, double* z, lapack_int ldz,\n                                double* work, lapack_int lwork,\n                                lapack_int* iwork, lapack_int liwork );\n\nlapack_int LAPACKE_sspgvx_work( int matrix_order, lapack_int itype, char jobz,\n                                char range, char uplo, lapack_int n, float* ap,\n                                float* bp, float vl, float vu, lapack_int il,\n                                lapack_int iu, float abstol, lapack_int* m,\n                                float* w, float* z, lapack_int ldz, float* work,\n                                lapack_int* iwork, lapack_int* ifail );\nlapack_int LAPACKE_dspgvx_work( int matrix_order, lapack_int itype, char jobz,\n                                char range, char uplo, lapack_int n, double* ap,\n                                double* bp, double vl, double vu, lapack_int il,\n                                lapack_int iu, double abstol, lapack_int* m,\n                                double* w, double* z, lapack_int ldz,\n                                double* work, lapack_int* iwork,\n                                lapack_int* ifail );\n\nlapack_int LAPACKE_ssprfs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const float* ap,\n                                const float* afp, const lapack_int* ipiv,\n                                const float* b, lapack_int ldb, float* x,\n                                lapack_int ldx, float* ferr, float* berr,\n                                float* work, lapack_int* iwork );\nlapack_int LAPACKE_dsprfs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const double* ap,\n                                const double* afp, const lapack_int* ipiv,\n                                const double* b, lapack_int ldb, double* x,\n                                lapack_int ldx, double* ferr, double* berr,\n                                double* work, lapack_int* iwork );\nlapack_int LAPACKE_csprfs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const lapack_complex_float* ap,\n                                const lapack_complex_float* afp,\n                                const lapack_int* ipiv,\n                                const lapack_complex_float* b, lapack_int ldb,\n                                lapack_complex_float* x, lapack_int ldx,\n                                float* ferr, float* berr,\n                                lapack_complex_float* work, float* rwork );\nlapack_int LAPACKE_zsprfs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs,\n                                const lapack_complex_double* ap,\n                                const lapack_complex_double* afp,\n                                const lapack_int* ipiv,\n                                const lapack_complex_double* b, lapack_int ldb,\n                                lapack_complex_double* x, lapack_int ldx,\n                                double* ferr, double* berr,\n                                lapack_complex_double* work, double* rwork );\n\nlapack_int LAPACKE_sspsv_work( int matrix_order, char uplo, lapack_int n,\n                               lapack_int nrhs, float* ap, lapack_int* ipiv,\n                               float* b, lapack_int ldb );\nlapack_int LAPACKE_dspsv_work( int matrix_order, char uplo, lapack_int n,\n                               lapack_int nrhs, double* ap, lapack_int* ipiv,\n                               double* b, lapack_int ldb );\nlapack_int LAPACKE_cspsv_work( int matrix_order, char uplo, lapack_int n,\n                               lapack_int nrhs, lapack_complex_float* ap,\n                               lapack_int* ipiv, lapack_complex_float* b,\n                               lapack_int ldb );\nlapack_int LAPACKE_zspsv_work( int matrix_order, char uplo, lapack_int n,\n                               lapack_int nrhs, lapack_complex_double* ap,\n                               lapack_int* ipiv, lapack_complex_double* b,\n                               lapack_int ldb );\n\nlapack_int LAPACKE_sspsvx_work( int matrix_order, char fact, char uplo,\n                                lapack_int n, lapack_int nrhs, const float* ap,\n                                float* afp, lapack_int* ipiv, const float* b,\n                                lapack_int ldb, float* x, lapack_int ldx,\n                                float* rcond, float* ferr, float* berr,\n                                float* work, lapack_int* iwork );\nlapack_int LAPACKE_dspsvx_work( int matrix_order, char fact, char uplo,\n                                lapack_int n, lapack_int nrhs, const double* ap,\n                                double* afp, lapack_int* ipiv, const double* b,\n                                lapack_int ldb, double* x, lapack_int ldx,\n                                double* rcond, double* ferr, double* berr,\n                                double* work, lapack_int* iwork );\nlapack_int LAPACKE_cspsvx_work( int matrix_order, char fact, char uplo,\n                                lapack_int n, lapack_int nrhs,\n                                const lapack_complex_float* ap,\n                                lapack_complex_float* afp, lapack_int* ipiv,\n                                const lapack_complex_float* b, lapack_int ldb,\n                                lapack_complex_float* x, lapack_int ldx,\n                                float* rcond, float* ferr, float* berr,\n                                lapack_complex_float* work, float* rwork );\nlapack_int LAPACKE_zspsvx_work( int matrix_order, char fact, char uplo,\n                                lapack_int n, lapack_int nrhs,\n                                const lapack_complex_double* ap,\n                                lapack_complex_double* afp, lapack_int* ipiv,\n                                const lapack_complex_double* b, lapack_int ldb,\n                                lapack_complex_double* x, lapack_int ldx,\n                                double* rcond, double* ferr, double* berr,\n                                lapack_complex_double* work, double* rwork );\n\nlapack_int LAPACKE_ssptrd_work( int matrix_order, char uplo, lapack_int n,\n                                float* ap, float* d, float* e, float* tau );\nlapack_int LAPACKE_dsptrd_work( int matrix_order, char uplo, lapack_int n,\n                                double* ap, double* d, double* e, double* tau );\n\nlapack_int LAPACKE_ssptrf_work( int matrix_order, char uplo, lapack_int n,\n                                float* ap, lapack_int* ipiv );\nlapack_int LAPACKE_dsptrf_work( int matrix_order, char uplo, lapack_int n,\n                                double* ap, lapack_int* ipiv );\nlapack_int LAPACKE_csptrf_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_complex_float* ap, lapack_int* ipiv );\nlapack_int LAPACKE_zsptrf_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_complex_double* ap, lapack_int* ipiv );\n\nlapack_int LAPACKE_ssptri_work( int matrix_order, char uplo, lapack_int n,\n                                float* ap, const lapack_int* ipiv,\n                                float* work );\nlapack_int LAPACKE_dsptri_work( int matrix_order, char uplo, lapack_int n,\n                                double* ap, const lapack_int* ipiv,\n                                double* work );\nlapack_int LAPACKE_csptri_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_complex_float* ap,\n                                const lapack_int* ipiv,\n                                lapack_complex_float* work );\nlapack_int LAPACKE_zsptri_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_complex_double* ap,\n                                const lapack_int* ipiv,\n                                lapack_complex_double* work );\n\nlapack_int LAPACKE_ssptrs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const float* ap,\n                                const lapack_int* ipiv, float* b,\n                                lapack_int ldb );\nlapack_int LAPACKE_dsptrs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const double* ap,\n                                const lapack_int* ipiv, double* b,\n                                lapack_int ldb );\nlapack_int LAPACKE_csptrs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const lapack_complex_float* ap,\n                                const lapack_int* ipiv, lapack_complex_float* b,\n                                lapack_int ldb );\nlapack_int LAPACKE_zsptrs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs,\n                                const lapack_complex_double* ap,\n                                const lapack_int* ipiv,\n                                lapack_complex_double* b, lapack_int ldb );\n\nlapack_int LAPACKE_sstebz_work( char range, char order, lapack_int n, float vl,\n                                float vu, lapack_int il, lapack_int iu,\n                                float abstol, const float* d, const float* e,\n                                lapack_int* m, lapack_int* nsplit, float* w,\n                                lapack_int* iblock, lapack_int* isplit,\n                                float* work, lapack_int* iwork );\nlapack_int LAPACKE_dstebz_work( char range, char order, lapack_int n, double vl,\n                                double vu, lapack_int il, lapack_int iu,\n                                double abstol, const double* d, const double* e,\n                                lapack_int* m, lapack_int* nsplit, double* w,\n                                lapack_int* iblock, lapack_int* isplit,\n                                double* work, lapack_int* iwork );\n\nlapack_int LAPACKE_sstedc_work( int matrix_order, char compz, lapack_int n,\n                                float* d, float* e, float* z, lapack_int ldz,\n                                float* work, lapack_int lwork,\n                                lapack_int* iwork, lapack_int liwork );\nlapack_int LAPACKE_dstedc_work( int matrix_order, char compz, lapack_int n,\n                                double* d, double* e, double* z, lapack_int ldz,\n                                double* work, lapack_int lwork,\n                                lapack_int* iwork, lapack_int liwork );\nlapack_int LAPACKE_cstedc_work( int matrix_order, char compz, lapack_int n,\n                                float* d, float* e, lapack_complex_float* z,\n                                lapack_int ldz, lapack_complex_float* work,\n                                lapack_int lwork, float* rwork,\n                                lapack_int lrwork, lapack_int* iwork,\n                                lapack_int liwork );\nlapack_int LAPACKE_zstedc_work( int matrix_order, char compz, lapack_int n,\n                                double* d, double* e, lapack_complex_double* z,\n                                lapack_int ldz, lapack_complex_double* work,\n                                lapack_int lwork, double* rwork,\n                                lapack_int lrwork, lapack_int* iwork,\n                                lapack_int liwork );\n\nlapack_int LAPACKE_sstegr_work( int matrix_order, char jobz, char range,\n                                lapack_int n, float* d, float* e, float vl,\n                                float vu, lapack_int il, lapack_int iu,\n                                float abstol, lapack_int* m, float* w, float* z,\n                                lapack_int ldz, lapack_int* isuppz, float* work,\n                                lapack_int lwork, lapack_int* iwork,\n                                lapack_int liwork );\nlapack_int LAPACKE_dstegr_work( int matrix_order, char jobz, char range,\n                                lapack_int n, double* d, double* e, double vl,\n                                double vu, lapack_int il, lapack_int iu,\n                                double abstol, lapack_int* m, double* w,\n                                double* z, lapack_int ldz, lapack_int* isuppz,\n                                double* work, lapack_int lwork,\n                                lapack_int* iwork, lapack_int liwork );\nlapack_int LAPACKE_cstegr_work( int matrix_order, char jobz, char range,\n                                lapack_int n, float* d, float* e, float vl,\n                                float vu, lapack_int il, lapack_int iu,\n                                float abstol, lapack_int* m, float* w,\n                                lapack_complex_float* z, lapack_int ldz,\n                                lapack_int* isuppz, float* work,\n                                lapack_int lwork, lapack_int* iwork,\n                                lapack_int liwork );\nlapack_int LAPACKE_zstegr_work( int matrix_order, char jobz, char range,\n                                lapack_int n, double* d, double* e, double vl,\n                                double vu, lapack_int il, lapack_int iu,\n                                double abstol, lapack_int* m, double* w,\n                                lapack_complex_double* z, lapack_int ldz,\n                                lapack_int* isuppz, double* work,\n                                lapack_int lwork, lapack_int* iwork,\n                                lapack_int liwork );\n\nlapack_int LAPACKE_sstein_work( int matrix_order, lapack_int n, const float* d,\n                                const float* e, lapack_int m, const float* w,\n                                const lapack_int* iblock,\n                                const lapack_int* isplit, float* z,\n                                lapack_int ldz, float* work, lapack_int* iwork,\n                                lapack_int* ifailv );\nlapack_int LAPACKE_dstein_work( int matrix_order, lapack_int n, const double* d,\n                                const double* e, lapack_int m, const double* w,\n                                const lapack_int* iblock,\n                                const lapack_int* isplit, double* z,\n                                lapack_int ldz, double* work, lapack_int* iwork,\n                                lapack_int* ifailv );\nlapack_int LAPACKE_cstein_work( int matrix_order, lapack_int n, const float* d,\n                                const float* e, lapack_int m, const float* w,\n                                const lapack_int* iblock,\n                                const lapack_int* isplit,\n                                lapack_complex_float* z, lapack_int ldz,\n                                float* work, lapack_int* iwork,\n                                lapack_int* ifailv );\nlapack_int LAPACKE_zstein_work( int matrix_order, lapack_int n, const double* d,\n                                const double* e, lapack_int m, const double* w,\n                                const lapack_int* iblock,\n                                const lapack_int* isplit,\n                                lapack_complex_double* z, lapack_int ldz,\n                                double* work, lapack_int* iwork,\n                                lapack_int* ifailv );\n\nlapack_int LAPACKE_sstemr_work( int matrix_order, char jobz, char range,\n                                lapack_int n, float* d, float* e, float vl,\n                                float vu, lapack_int il, lapack_int iu,\n                                lapack_int* m, float* w, float* z,\n                                lapack_int ldz, lapack_int nzc,\n                                lapack_int* isuppz, lapack_logical* tryrac,\n                                float* work, lapack_int lwork,\n                                lapack_int* iwork, lapack_int liwork );\nlapack_int LAPACKE_dstemr_work( int matrix_order, char jobz, char range,\n                                lapack_int n, double* d, double* e, double vl,\n                                double vu, lapack_int il, lapack_int iu,\n                                lapack_int* m, double* w, double* z,\n                                lapack_int ldz, lapack_int nzc,\n                                lapack_int* isuppz, lapack_logical* tryrac,\n                                double* work, lapack_int lwork,\n                                lapack_int* iwork, lapack_int liwork );\nlapack_int LAPACKE_cstemr_work( int matrix_order, char jobz, char range,\n                                lapack_int n, float* d, float* e, float vl,\n                                float vu, lapack_int il, lapack_int iu,\n                                lapack_int* m, float* w,\n                                lapack_complex_float* z, lapack_int ldz,\n                                lapack_int nzc, lapack_int* isuppz,\n                                lapack_logical* tryrac, float* work,\n                                lapack_int lwork, lapack_int* iwork,\n                                lapack_int liwork );\nlapack_int LAPACKE_zstemr_work( int matrix_order, char jobz, char range,\n                                lapack_int n, double* d, double* e, double vl,\n                                double vu, lapack_int il, lapack_int iu,\n                                lapack_int* m, double* w,\n                                lapack_complex_double* z, lapack_int ldz,\n                                lapack_int nzc, lapack_int* isuppz,\n                                lapack_logical* tryrac, double* work,\n                                lapack_int lwork, lapack_int* iwork,\n                                lapack_int liwork );\n\nlapack_int LAPACKE_ssteqr_work( int matrix_order, char compz, lapack_int n,\n                                float* d, float* e, float* z, lapack_int ldz,\n                                float* work );\nlapack_int LAPACKE_dsteqr_work( int matrix_order, char compz, lapack_int n,\n                                double* d, double* e, double* z, lapack_int ldz,\n                                double* work );\nlapack_int LAPACKE_csteqr_work( int matrix_order, char compz, lapack_int n,\n                                float* d, float* e, lapack_complex_float* z,\n                                lapack_int ldz, float* work );\nlapack_int LAPACKE_zsteqr_work( int matrix_order, char compz, lapack_int n,\n                                double* d, double* e, lapack_complex_double* z,\n                                lapack_int ldz, double* work );\n\nlapack_int LAPACKE_ssterf_work( lapack_int n, float* d, float* e );\nlapack_int LAPACKE_dsterf_work( lapack_int n, double* d, double* e );\n\nlapack_int LAPACKE_sstev_work( int matrix_order, char jobz, lapack_int n,\n                               float* d, float* e, float* z, lapack_int ldz,\n                               float* work );\nlapack_int LAPACKE_dstev_work( int matrix_order, char jobz, lapack_int n,\n                               double* d, double* e, double* z, lapack_int ldz,\n                               double* work );\n\nlapack_int LAPACKE_sstevd_work( int matrix_order, char jobz, lapack_int n,\n                                float* d, float* e, float* z, lapack_int ldz,\n                                float* work, lapack_int lwork,\n                                lapack_int* iwork, lapack_int liwork );\nlapack_int LAPACKE_dstevd_work( int matrix_order, char jobz, lapack_int n,\n                                double* d, double* e, double* z, lapack_int ldz,\n                                double* work, lapack_int lwork,\n                                lapack_int* iwork, lapack_int liwork );\n\nlapack_int LAPACKE_sstevr_work( int matrix_order, char jobz, char range,\n                                lapack_int n, float* d, float* e, float vl,\n                                float vu, lapack_int il, lapack_int iu,\n                                float abstol, lapack_int* m, float* w, float* z,\n                                lapack_int ldz, lapack_int* isuppz, float* work,\n                                lapack_int lwork, lapack_int* iwork,\n                                lapack_int liwork );\nlapack_int LAPACKE_dstevr_work( int matrix_order, char jobz, char range,\n                                lapack_int n, double* d, double* e, double vl,\n                                double vu, lapack_int il, lapack_int iu,\n                                double abstol, lapack_int* m, double* w,\n                                double* z, lapack_int ldz, lapack_int* isuppz,\n                                double* work, lapack_int lwork,\n                                lapack_int* iwork, lapack_int liwork );\n\nlapack_int LAPACKE_sstevx_work( int matrix_order, char jobz, char range,\n                                lapack_int n, float* d, float* e, float vl,\n                                float vu, lapack_int il, lapack_int iu,\n                                float abstol, lapack_int* m, float* w, float* z,\n                                lapack_int ldz, float* work, lapack_int* iwork,\n                                lapack_int* ifail );\nlapack_int LAPACKE_dstevx_work( int matrix_order, char jobz, char range,\n                                lapack_int n, double* d, double* e, double vl,\n                                double vu, lapack_int il, lapack_int iu,\n                                double abstol, lapack_int* m, double* w,\n                                double* z, lapack_int ldz, double* work,\n                                lapack_int* iwork, lapack_int* ifail );\n\nlapack_int LAPACKE_ssycon_work( int matrix_order, char uplo, lapack_int n,\n                                const float* a, lapack_int lda,\n                                const lapack_int* ipiv, float anorm,\n                                float* rcond, float* work, lapack_int* iwork );\nlapack_int LAPACKE_dsycon_work( int matrix_order, char uplo, lapack_int n,\n                                const double* a, lapack_int lda,\n                                const lapack_int* ipiv, double anorm,\n                                double* rcond, double* work,\n                                lapack_int* iwork );\nlapack_int LAPACKE_csycon_work( int matrix_order, char uplo, lapack_int n,\n                                const lapack_complex_float* a, lapack_int lda,\n                                const lapack_int* ipiv, float anorm,\n                                float* rcond, lapack_complex_float* work );\nlapack_int LAPACKE_zsycon_work( int matrix_order, char uplo, lapack_int n,\n                                const lapack_complex_double* a, lapack_int lda,\n                                const lapack_int* ipiv, double anorm,\n                                double* rcond, lapack_complex_double* work );\n\nlapack_int LAPACKE_ssyequb_work( int matrix_order, char uplo, lapack_int n,\n                                 const float* a, lapack_int lda, float* s,\n                                 float* scond, float* amax, float* work );\nlapack_int LAPACKE_dsyequb_work( int matrix_order, char uplo, lapack_int n,\n                                 const double* a, lapack_int lda, double* s,\n                                 double* scond, double* amax, double* work );\nlapack_int LAPACKE_csyequb_work( int matrix_order, char uplo, lapack_int n,\n                                 const lapack_complex_float* a, lapack_int lda,\n                                 float* s, float* scond, float* amax,\n                                 lapack_complex_float* work );\nlapack_int LAPACKE_zsyequb_work( int matrix_order, char uplo, lapack_int n,\n                                 const lapack_complex_double* a, lapack_int lda,\n                                 double* s, double* scond, double* amax,\n                                 lapack_complex_double* work );\n\nlapack_int LAPACKE_ssyev_work( int matrix_order, char jobz, char uplo,\n                               lapack_int n, float* a, lapack_int lda, float* w,\n                               float* work, lapack_int lwork );\nlapack_int LAPACKE_dsyev_work( int matrix_order, char jobz, char uplo,\n                               lapack_int n, double* a, lapack_int lda,\n                               double* w, double* work, lapack_int lwork );\n\nlapack_int LAPACKE_ssyevd_work( int matrix_order, char jobz, char uplo,\n                                lapack_int n, float* a, lapack_int lda,\n                                float* w, float* work, lapack_int lwork,\n                                lapack_int* iwork, lapack_int liwork );\nlapack_int LAPACKE_dsyevd_work( int matrix_order, char jobz, char uplo,\n                                lapack_int n, double* a, lapack_int lda,\n                                double* w, double* work, lapack_int lwork,\n                                lapack_int* iwork, lapack_int liwork );\n\nlapack_int LAPACKE_ssyevr_work( int matrix_order, char jobz, char range,\n                                char uplo, lapack_int n, float* a,\n                                lapack_int lda, float vl, float vu,\n                                lapack_int il, lapack_int iu, float abstol,\n                                lapack_int* m, float* w, float* z,\n                                lapack_int ldz, lapack_int* isuppz, float* work,\n                                lapack_int lwork, lapack_int* iwork,\n                                lapack_int liwork );\nlapack_int LAPACKE_dsyevr_work( int matrix_order, char jobz, char range,\n                                char uplo, lapack_int n, double* a,\n                                lapack_int lda, double vl, double vu,\n                                lapack_int il, lapack_int iu, double abstol,\n                                lapack_int* m, double* w, double* z,\n                                lapack_int ldz, lapack_int* isuppz,\n                                double* work, lapack_int lwork,\n                                lapack_int* iwork, lapack_int liwork );\n\nlapack_int LAPACKE_ssyevx_work( int matrix_order, char jobz, char range,\n                                char uplo, lapack_int n, float* a,\n                                lapack_int lda, float vl, float vu,\n                                lapack_int il, lapack_int iu, float abstol,\n                                lapack_int* m, float* w, float* z,\n                                lapack_int ldz, float* work, lapack_int lwork,\n                                lapack_int* iwork, lapack_int* ifail );\nlapack_int LAPACKE_dsyevx_work( int matrix_order, char jobz, char range,\n                                char uplo, lapack_int n, double* a,\n                                lapack_int lda, double vl, double vu,\n                                lapack_int il, lapack_int iu, double abstol,\n                                lapack_int* m, double* w, double* z,\n                                lapack_int ldz, double* work, lapack_int lwork,\n                                lapack_int* iwork, lapack_int* ifail );\n\nlapack_int LAPACKE_ssygst_work( int matrix_order, lapack_int itype, char uplo,\n                                lapack_int n, float* a, lapack_int lda,\n                                const float* b, lapack_int ldb );\nlapack_int LAPACKE_dsygst_work( int matrix_order, lapack_int itype, char uplo,\n                                lapack_int n, double* a, lapack_int lda,\n                                const double* b, lapack_int ldb );\n\nlapack_int LAPACKE_ssygv_work( int matrix_order, lapack_int itype, char jobz,\n                               char uplo, lapack_int n, float* a,\n                               lapack_int lda, float* b, lapack_int ldb,\n                               float* w, float* work, lapack_int lwork );\nlapack_int LAPACKE_dsygv_work( int matrix_order, lapack_int itype, char jobz,\n                               char uplo, lapack_int n, double* a,\n                               lapack_int lda, double* b, lapack_int ldb,\n                               double* w, double* work, lapack_int lwork );\n\nlapack_int LAPACKE_ssygvd_work( int matrix_order, lapack_int itype, char jobz,\n                                char uplo, lapack_int n, float* a,\n                                lapack_int lda, float* b, lapack_int ldb,\n                                float* w, float* work, lapack_int lwork,\n                                lapack_int* iwork, lapack_int liwork );\nlapack_int LAPACKE_dsygvd_work( int matrix_order, lapack_int itype, char jobz,\n                                char uplo, lapack_int n, double* a,\n                                lapack_int lda, double* b, lapack_int ldb,\n                                double* w, double* work, lapack_int lwork,\n                                lapack_int* iwork, lapack_int liwork );\n\nlapack_int LAPACKE_ssygvx_work( int matrix_order, lapack_int itype, char jobz,\n                                char range, char uplo, lapack_int n, float* a,\n                                lapack_int lda, float* b, lapack_int ldb,\n                                float vl, float vu, lapack_int il,\n                                lapack_int iu, float abstol, lapack_int* m,\n                                float* w, float* z, lapack_int ldz, float* work,\n                                lapack_int lwork, lapack_int* iwork,\n                                lapack_int* ifail );\nlapack_int LAPACKE_dsygvx_work( int matrix_order, lapack_int itype, char jobz,\n                                char range, char uplo, lapack_int n, double* a,\n                                lapack_int lda, double* b, lapack_int ldb,\n                                double vl, double vu, lapack_int il,\n                                lapack_int iu, double abstol, lapack_int* m,\n                                double* w, double* z, lapack_int ldz,\n                                double* work, lapack_int lwork,\n                                lapack_int* iwork, lapack_int* ifail );\n\nlapack_int LAPACKE_ssyrfs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const float* a, lapack_int lda,\n                                const float* af, lapack_int ldaf,\n                                const lapack_int* ipiv, const float* b,\n                                lapack_int ldb, float* x, lapack_int ldx,\n                                float* ferr, float* berr, float* work,\n                                lapack_int* iwork );\nlapack_int LAPACKE_dsyrfs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const double* a,\n                                lapack_int lda, const double* af,\n                                lapack_int ldaf, const lapack_int* ipiv,\n                                const double* b, lapack_int ldb, double* x,\n                                lapack_int ldx, double* ferr, double* berr,\n                                double* work, lapack_int* iwork );\nlapack_int LAPACKE_csyrfs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const lapack_complex_float* a,\n                                lapack_int lda, const lapack_complex_float* af,\n                                lapack_int ldaf, const lapack_int* ipiv,\n                                const lapack_complex_float* b, lapack_int ldb,\n                                lapack_complex_float* x, lapack_int ldx,\n                                float* ferr, float* berr,\n                                lapack_complex_float* work, float* rwork );\nlapack_int LAPACKE_zsyrfs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const lapack_complex_double* a,\n                                lapack_int lda, const lapack_complex_double* af,\n                                lapack_int ldaf, const lapack_int* ipiv,\n                                const lapack_complex_double* b, lapack_int ldb,\n                                lapack_complex_double* x, lapack_int ldx,\n                                double* ferr, double* berr,\n                                lapack_complex_double* work, double* rwork );\n\nlapack_int LAPACKE_ssyrfsx_work( int matrix_order, char uplo, char equed,\n                                 lapack_int n, lapack_int nrhs, const float* a,\n                                 lapack_int lda, const float* af,\n                                 lapack_int ldaf, const lapack_int* ipiv,\n                                 const float* s, const float* b, lapack_int ldb,\n                                 float* x, lapack_int ldx, float* rcond,\n                                 float* berr, lapack_int n_err_bnds,\n                                 float* err_bnds_norm, float* err_bnds_comp,\n                                 lapack_int nparams, float* params, float* work,\n                                 lapack_int* iwork );\nlapack_int LAPACKE_dsyrfsx_work( int matrix_order, char uplo, char equed,\n                                 lapack_int n, lapack_int nrhs, const double* a,\n                                 lapack_int lda, const double* af,\n                                 lapack_int ldaf, const lapack_int* ipiv,\n                                 const double* s, const double* b,\n                                 lapack_int ldb, double* x, lapack_int ldx,\n                                 double* rcond, double* berr,\n                                 lapack_int n_err_bnds, double* err_bnds_norm,\n                                 double* err_bnds_comp, lapack_int nparams,\n                                 double* params, double* work,\n                                 lapack_int* iwork );\nlapack_int LAPACKE_csyrfsx_work( int matrix_order, char uplo, char equed,\n                                 lapack_int n, lapack_int nrhs,\n                                 const lapack_complex_float* a, lapack_int lda,\n                                 const lapack_complex_float* af,\n                                 lapack_int ldaf, const lapack_int* ipiv,\n                                 const float* s, const lapack_complex_float* b,\n                                 lapack_int ldb, lapack_complex_float* x,\n                                 lapack_int ldx, float* rcond, float* berr,\n                                 lapack_int n_err_bnds, float* err_bnds_norm,\n                                 float* err_bnds_comp, lapack_int nparams,\n                                 float* params, lapack_complex_float* work,\n                                 float* rwork );\nlapack_int LAPACKE_zsyrfsx_work( int matrix_order, char uplo, char equed,\n                                 lapack_int n, lapack_int nrhs,\n                                 const lapack_complex_double* a, lapack_int lda,\n                                 const lapack_complex_double* af,\n                                 lapack_int ldaf, const lapack_int* ipiv,\n                                 const double* s,\n                                 const lapack_complex_double* b, lapack_int ldb,\n                                 lapack_complex_double* x, lapack_int ldx,\n                                 double* rcond, double* berr,\n                                 lapack_int n_err_bnds, double* err_bnds_norm,\n                                 double* err_bnds_comp, lapack_int nparams,\n                                 double* params, lapack_complex_double* work,\n                                 double* rwork );\n\nlapack_int LAPACKE_ssysv_work( int matrix_order, char uplo, lapack_int n,\n                               lapack_int nrhs, float* a, lapack_int lda,\n                               lapack_int* ipiv, float* b, lapack_int ldb,\n                               float* work, lapack_int lwork );\nlapack_int LAPACKE_dsysv_work( int matrix_order, char uplo, lapack_int n,\n                               lapack_int nrhs, double* a, lapack_int lda,\n                               lapack_int* ipiv, double* b, lapack_int ldb,\n                               double* work, lapack_int lwork );\nlapack_int LAPACKE_csysv_work( int matrix_order, char uplo, lapack_int n,\n                               lapack_int nrhs, lapack_complex_float* a,\n                               lapack_int lda, lapack_int* ipiv,\n                               lapack_complex_float* b, lapack_int ldb,\n                               lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_zsysv_work( int matrix_order, char uplo, lapack_int n,\n                               lapack_int nrhs, lapack_complex_double* a,\n                               lapack_int lda, lapack_int* ipiv,\n                               lapack_complex_double* b, lapack_int ldb,\n                               lapack_complex_double* work, lapack_int lwork );\n\nlapack_int LAPACKE_ssysvx_work( int matrix_order, char fact, char uplo,\n                                lapack_int n, lapack_int nrhs, const float* a,\n                                lapack_int lda, float* af, lapack_int ldaf,\n                                lapack_int* ipiv, const float* b,\n                                lapack_int ldb, float* x, lapack_int ldx,\n                                float* rcond, float* ferr, float* berr,\n                                float* work, lapack_int lwork,\n                                lapack_int* iwork );\nlapack_int LAPACKE_dsysvx_work( int matrix_order, char fact, char uplo,\n                                lapack_int n, lapack_int nrhs, const double* a,\n                                lapack_int lda, double* af, lapack_int ldaf,\n                                lapack_int* ipiv, const double* b,\n                                lapack_int ldb, double* x, lapack_int ldx,\n                                double* rcond, double* ferr, double* berr,\n                                double* work, lapack_int lwork,\n                                lapack_int* iwork );\nlapack_int LAPACKE_csysvx_work( int matrix_order, char fact, char uplo,\n                                lapack_int n, lapack_int nrhs,\n                                const lapack_complex_float* a, lapack_int lda,\n                                lapack_complex_float* af, lapack_int ldaf,\n                                lapack_int* ipiv, const lapack_complex_float* b,\n                                lapack_int ldb, lapack_complex_float* x,\n                                lapack_int ldx, float* rcond, float* ferr,\n                                float* berr, lapack_complex_float* work,\n                                lapack_int lwork, float* rwork );\nlapack_int LAPACKE_zsysvx_work( int matrix_order, char fact, char uplo,\n                                lapack_int n, lapack_int nrhs,\n                                const lapack_complex_double* a, lapack_int lda,\n                                lapack_complex_double* af, lapack_int ldaf,\n                                lapack_int* ipiv,\n                                const lapack_complex_double* b, lapack_int ldb,\n                                lapack_complex_double* x, lapack_int ldx,\n                                double* rcond, double* ferr, double* berr,\n                                lapack_complex_double* work, lapack_int lwork,\n                                double* rwork );\n\nlapack_int LAPACKE_ssysvxx_work( int matrix_order, char fact, char uplo,\n                                 lapack_int n, lapack_int nrhs, float* a,\n                                 lapack_int lda, float* af, lapack_int ldaf,\n                                 lapack_int* ipiv, char* equed, float* s,\n                                 float* b, lapack_int ldb, float* x,\n                                 lapack_int ldx, float* rcond, float* rpvgrw,\n                                 float* berr, lapack_int n_err_bnds,\n                                 float* err_bnds_norm, float* err_bnds_comp,\n                                 lapack_int nparams, float* params, float* work,\n                                 lapack_int* iwork );\nlapack_int LAPACKE_dsysvxx_work( int matrix_order, char fact, char uplo,\n                                 lapack_int n, lapack_int nrhs, double* a,\n                                 lapack_int lda, double* af, lapack_int ldaf,\n                                 lapack_int* ipiv, char* equed, double* s,\n                                 double* b, lapack_int ldb, double* x,\n                                 lapack_int ldx, double* rcond, double* rpvgrw,\n                                 double* berr, lapack_int n_err_bnds,\n                                 double* err_bnds_norm, double* err_bnds_comp,\n                                 lapack_int nparams, double* params,\n                                 double* work, lapack_int* iwork );\nlapack_int LAPACKE_csysvxx_work( int matrix_order, char fact, char uplo,\n                                 lapack_int n, lapack_int nrhs,\n                                 lapack_complex_float* a, lapack_int lda,\n                                 lapack_complex_float* af, lapack_int ldaf,\n                                 lapack_int* ipiv, char* equed, float* s,\n                                 lapack_complex_float* b, lapack_int ldb,\n                                 lapack_complex_float* x, lapack_int ldx,\n                                 float* rcond, float* rpvgrw, float* berr,\n                                 lapack_int n_err_bnds, float* err_bnds_norm,\n                                 float* err_bnds_comp, lapack_int nparams,\n                                 float* params, lapack_complex_float* work,\n                                 float* rwork );\nlapack_int LAPACKE_zsysvxx_work( int matrix_order, char fact, char uplo,\n                                 lapack_int n, lapack_int nrhs,\n                                 lapack_complex_double* a, lapack_int lda,\n                                 lapack_complex_double* af, lapack_int ldaf,\n                                 lapack_int* ipiv, char* equed, double* s,\n                                 lapack_complex_double* b, lapack_int ldb,\n                                 lapack_complex_double* x, lapack_int ldx,\n                                 double* rcond, double* rpvgrw, double* berr,\n                                 lapack_int n_err_bnds, double* err_bnds_norm,\n                                 double* err_bnds_comp, lapack_int nparams,\n                                 double* params, lapack_complex_double* work,\n                                 double* rwork );\n\nlapack_int LAPACKE_ssytrd_work( int matrix_order, char uplo, lapack_int n,\n                                float* a, lapack_int lda, float* d, float* e,\n                                float* tau, float* work, lapack_int lwork );\nlapack_int LAPACKE_dsytrd_work( int matrix_order, char uplo, lapack_int n,\n                                double* a, lapack_int lda, double* d, double* e,\n                                double* tau, double* work, lapack_int lwork );\n\nlapack_int LAPACKE_ssytrf_work( int matrix_order, char uplo, lapack_int n,\n                                float* a, lapack_int lda, lapack_int* ipiv,\n                                float* work, lapack_int lwork );\nlapack_int LAPACKE_dsytrf_work( int matrix_order, char uplo, lapack_int n,\n                                double* a, lapack_int lda, lapack_int* ipiv,\n                                double* work, lapack_int lwork );\nlapack_int LAPACKE_csytrf_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_complex_float* a, lapack_int lda,\n                                lapack_int* ipiv, lapack_complex_float* work,\n                                lapack_int lwork );\nlapack_int LAPACKE_zsytrf_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_complex_double* a, lapack_int lda,\n                                lapack_int* ipiv, lapack_complex_double* work,\n                                lapack_int lwork );\n\nlapack_int LAPACKE_ssytri_work( int matrix_order, char uplo, lapack_int n,\n                                float* a, lapack_int lda,\n                                const lapack_int* ipiv, float* work );\nlapack_int LAPACKE_dsytri_work( int matrix_order, char uplo, lapack_int n,\n                                double* a, lapack_int lda,\n                                const lapack_int* ipiv, double* work );\nlapack_int LAPACKE_csytri_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_complex_float* a, lapack_int lda,\n                                const lapack_int* ipiv,\n                                lapack_complex_float* work );\nlapack_int LAPACKE_zsytri_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_complex_double* a, lapack_int lda,\n                                const lapack_int* ipiv,\n                                lapack_complex_double* work );\n\nlapack_int LAPACKE_ssytrs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const float* a, lapack_int lda,\n                                const lapack_int* ipiv, float* b,\n                                lapack_int ldb );\nlapack_int LAPACKE_dsytrs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const double* a,\n                                lapack_int lda, const lapack_int* ipiv,\n                                double* b, lapack_int ldb );\nlapack_int LAPACKE_csytrs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const lapack_complex_float* a,\n                                lapack_int lda, const lapack_int* ipiv,\n                                lapack_complex_float* b, lapack_int ldb );\nlapack_int LAPACKE_zsytrs_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_int nrhs, const lapack_complex_double* a,\n                                lapack_int lda, const lapack_int* ipiv,\n                                lapack_complex_double* b, lapack_int ldb );\n\nlapack_int LAPACKE_stbcon_work( int matrix_order, char norm, char uplo,\n                                char diag, lapack_int n, lapack_int kd,\n                                const float* ab, lapack_int ldab, float* rcond,\n                                float* work, lapack_int* iwork );\nlapack_int LAPACKE_dtbcon_work( int matrix_order, char norm, char uplo,\n                                char diag, lapack_int n, lapack_int kd,\n                                const double* ab, lapack_int ldab,\n                                double* rcond, double* work,\n                                lapack_int* iwork );\nlapack_int LAPACKE_ctbcon_work( int matrix_order, char norm, char uplo,\n                                char diag, lapack_int n, lapack_int kd,\n                                const lapack_complex_float* ab, lapack_int ldab,\n                                float* rcond, lapack_complex_float* work,\n                                float* rwork );\nlapack_int LAPACKE_ztbcon_work( int matrix_order, char norm, char uplo,\n                                char diag, lapack_int n, lapack_int kd,\n                                const lapack_complex_double* ab,\n                                lapack_int ldab, double* rcond,\n                                lapack_complex_double* work, double* rwork );\n\nlapack_int LAPACKE_stbrfs_work( int matrix_order, char uplo, char trans,\n                                char diag, lapack_int n, lapack_int kd,\n                                lapack_int nrhs, const float* ab,\n                                lapack_int ldab, const float* b, lapack_int ldb,\n                                const float* x, lapack_int ldx, float* ferr,\n                                float* berr, float* work, lapack_int* iwork );\nlapack_int LAPACKE_dtbrfs_work( int matrix_order, char uplo, char trans,\n                                char diag, lapack_int n, lapack_int kd,\n                                lapack_int nrhs, const double* ab,\n                                lapack_int ldab, const double* b,\n                                lapack_int ldb, const double* x, lapack_int ldx,\n                                double* ferr, double* berr, double* work,\n                                lapack_int* iwork );\nlapack_int LAPACKE_ctbrfs_work( int matrix_order, char uplo, char trans,\n                                char diag, lapack_int n, lapack_int kd,\n                                lapack_int nrhs, const lapack_complex_float* ab,\n                                lapack_int ldab, const lapack_complex_float* b,\n                                lapack_int ldb, const lapack_complex_float* x,\n                                lapack_int ldx, float* ferr, float* berr,\n                                lapack_complex_float* work, float* rwork );\nlapack_int LAPACKE_ztbrfs_work( int matrix_order, char uplo, char trans,\n                                char diag, lapack_int n, lapack_int kd,\n                                lapack_int nrhs,\n                                const lapack_complex_double* ab,\n                                lapack_int ldab, const lapack_complex_double* b,\n                                lapack_int ldb, const lapack_complex_double* x,\n                                lapack_int ldx, double* ferr, double* berr,\n                                lapack_complex_double* work, double* rwork );\n\nlapack_int LAPACKE_stbtrs_work( int matrix_order, char uplo, char trans,\n                                char diag, lapack_int n, lapack_int kd,\n                                lapack_int nrhs, const float* ab,\n                                lapack_int ldab, float* b, lapack_int ldb );\nlapack_int LAPACKE_dtbtrs_work( int matrix_order, char uplo, char trans,\n                                char diag, lapack_int n, lapack_int kd,\n                                lapack_int nrhs, const double* ab,\n                                lapack_int ldab, double* b, lapack_int ldb );\nlapack_int LAPACKE_ctbtrs_work( int matrix_order, char uplo, char trans,\n                                char diag, lapack_int n, lapack_int kd,\n                                lapack_int nrhs, const lapack_complex_float* ab,\n                                lapack_int ldab, lapack_complex_float* b,\n                                lapack_int ldb );\nlapack_int LAPACKE_ztbtrs_work( int matrix_order, char uplo, char trans,\n                                char diag, lapack_int n, lapack_int kd,\n                                lapack_int nrhs,\n                                const lapack_complex_double* ab,\n                                lapack_int ldab, lapack_complex_double* b,\n                                lapack_int ldb );\n\nlapack_int LAPACKE_stfsm_work( int matrix_order, char transr, char side,\n                               char uplo, char trans, char diag, lapack_int m,\n                               lapack_int n, float alpha, const float* a,\n                               float* b, lapack_int ldb );\nlapack_int LAPACKE_dtfsm_work( int matrix_order, char transr, char side,\n                               char uplo, char trans, char diag, lapack_int m,\n                               lapack_int n, double alpha, const double* a,\n                               double* b, lapack_int ldb );\nlapack_int LAPACKE_ctfsm_work( int matrix_order, char transr, char side,\n                               char uplo, char trans, char diag, lapack_int m,\n                               lapack_int n, lapack_complex_float alpha,\n                               const lapack_complex_float* a,\n                               lapack_complex_float* b, lapack_int ldb );\nlapack_int LAPACKE_ztfsm_work( int matrix_order, char transr, char side,\n                               char uplo, char trans, char diag, lapack_int m,\n                               lapack_int n, lapack_complex_double alpha,\n                               const lapack_complex_double* a,\n                               lapack_complex_double* b, lapack_int ldb );\n\nlapack_int LAPACKE_stftri_work( int matrix_order, char transr, char uplo,\n                                char diag, lapack_int n, float* a );\nlapack_int LAPACKE_dtftri_work( int matrix_order, char transr, char uplo,\n                                char diag, lapack_int n, double* a );\nlapack_int LAPACKE_ctftri_work( int matrix_order, char transr, char uplo,\n                                char diag, lapack_int n,\n                                lapack_complex_float* a );\nlapack_int LAPACKE_ztftri_work( int matrix_order, char transr, char uplo,\n                                char diag, lapack_int n,\n                                lapack_complex_double* a );\n\nlapack_int LAPACKE_stfttp_work( int matrix_order, char transr, char uplo,\n                                lapack_int n, const float* arf, float* ap );\nlapack_int LAPACKE_dtfttp_work( int matrix_order, char transr, char uplo,\n                                lapack_int n, const double* arf, double* ap );\nlapack_int LAPACKE_ctfttp_work( int matrix_order, char transr, char uplo,\n                                lapack_int n, const lapack_complex_float* arf,\n                                lapack_complex_float* ap );\nlapack_int LAPACKE_ztfttp_work( int matrix_order, char transr, char uplo,\n                                lapack_int n, const lapack_complex_double* arf,\n                                lapack_complex_double* ap );\n\nlapack_int LAPACKE_stfttr_work( int matrix_order, char transr, char uplo,\n                                lapack_int n, const float* arf, float* a,\n                                lapack_int lda );\nlapack_int LAPACKE_dtfttr_work( int matrix_order, char transr, char uplo,\n                                lapack_int n, const double* arf, double* a,\n                                lapack_int lda );\nlapack_int LAPACKE_ctfttr_work( int matrix_order, char transr, char uplo,\n                                lapack_int n, const lapack_complex_float* arf,\n                                lapack_complex_float* a, lapack_int lda );\nlapack_int LAPACKE_ztfttr_work( int matrix_order, char transr, char uplo,\n                                lapack_int n, const lapack_complex_double* arf,\n                                lapack_complex_double* a, lapack_int lda );\n\nlapack_int LAPACKE_stgevc_work( int matrix_order, char side, char howmny,\n                                const lapack_logical* select, lapack_int n,\n                                const float* s, lapack_int lds, const float* p,\n                                lapack_int ldp, float* vl, lapack_int ldvl,\n                                float* vr, lapack_int ldvr, lapack_int mm,\n                                lapack_int* m, float* work );\nlapack_int LAPACKE_dtgevc_work( int matrix_order, char side, char howmny,\n                                const lapack_logical* select, lapack_int n,\n                                const double* s, lapack_int lds,\n                                const double* p, lapack_int ldp, double* vl,\n                                lapack_int ldvl, double* vr, lapack_int ldvr,\n                                lapack_int mm, lapack_int* m, double* work );\nlapack_int LAPACKE_ctgevc_work( int matrix_order, char side, char howmny,\n                                const lapack_logical* select, lapack_int n,\n                                const lapack_complex_float* s, lapack_int lds,\n                                const lapack_complex_float* p, lapack_int ldp,\n                                lapack_complex_float* vl, lapack_int ldvl,\n                                lapack_complex_float* vr, lapack_int ldvr,\n                                lapack_int mm, lapack_int* m,\n                                lapack_complex_float* work, float* rwork );\nlapack_int LAPACKE_ztgevc_work( int matrix_order, char side, char howmny,\n                                const lapack_logical* select, lapack_int n,\n                                const lapack_complex_double* s, lapack_int lds,\n                                const lapack_complex_double* p, lapack_int ldp,\n                                lapack_complex_double* vl, lapack_int ldvl,\n                                lapack_complex_double* vr, lapack_int ldvr,\n                                lapack_int mm, lapack_int* m,\n                                lapack_complex_double* work, double* rwork );\n\nlapack_int LAPACKE_stgexc_work( int matrix_order, lapack_logical wantq,\n                                lapack_logical wantz, lapack_int n, float* a,\n                                lapack_int lda, float* b, lapack_int ldb,\n                                float* q, lapack_int ldq, float* z,\n                                lapack_int ldz, lapack_int* ifst,\n                                lapack_int* ilst, float* work,\n                                lapack_int lwork );\nlapack_int LAPACKE_dtgexc_work( int matrix_order, lapack_logical wantq,\n                                lapack_logical wantz, lapack_int n, double* a,\n                                lapack_int lda, double* b, lapack_int ldb,\n                                double* q, lapack_int ldq, double* z,\n                                lapack_int ldz, lapack_int* ifst,\n                                lapack_int* ilst, double* work,\n                                lapack_int lwork );\nlapack_int LAPACKE_ctgexc_work( int matrix_order, lapack_logical wantq,\n                                lapack_logical wantz, lapack_int n,\n                                lapack_complex_float* a, lapack_int lda,\n                                lapack_complex_float* b, lapack_int ldb,\n                                lapack_complex_float* q, lapack_int ldq,\n                                lapack_complex_float* z, lapack_int ldz,\n                                lapack_int ifst, lapack_int ilst );\nlapack_int LAPACKE_ztgexc_work( int matrix_order, lapack_logical wantq,\n                                lapack_logical wantz, lapack_int n,\n                                lapack_complex_double* a, lapack_int lda,\n                                lapack_complex_double* b, lapack_int ldb,\n                                lapack_complex_double* q, lapack_int ldq,\n                                lapack_complex_double* z, lapack_int ldz,\n                                lapack_int ifst, lapack_int ilst );\n\nlapack_int LAPACKE_stgsen_work( int matrix_order, lapack_int ijob,\n                                lapack_logical wantq, lapack_logical wantz,\n                                const lapack_logical* select, lapack_int n,\n                                float* a, lapack_int lda, float* b,\n                                lapack_int ldb, float* alphar, float* alphai,\n                                float* beta, float* q, lapack_int ldq, float* z,\n                                lapack_int ldz, lapack_int* m, float* pl,\n                                float* pr, float* dif, float* work,\n                                lapack_int lwork, lapack_int* iwork,\n                                lapack_int liwork );\nlapack_int LAPACKE_dtgsen_work( int matrix_order, lapack_int ijob,\n                                lapack_logical wantq, lapack_logical wantz,\n                                const lapack_logical* select, lapack_int n,\n                                double* a, lapack_int lda, double* b,\n                                lapack_int ldb, double* alphar, double* alphai,\n                                double* beta, double* q, lapack_int ldq,\n                                double* z, lapack_int ldz, lapack_int* m,\n                                double* pl, double* pr, double* dif,\n                                double* work, lapack_int lwork,\n                                lapack_int* iwork, lapack_int liwork );\nlapack_int LAPACKE_ctgsen_work( int matrix_order, lapack_int ijob,\n                                lapack_logical wantq, lapack_logical wantz,\n                                const lapack_logical* select, lapack_int n,\n                                lapack_complex_float* a, lapack_int lda,\n                                lapack_complex_float* b, lapack_int ldb,\n                                lapack_complex_float* alpha,\n                                lapack_complex_float* beta,\n                                lapack_complex_float* q, lapack_int ldq,\n                                lapack_complex_float* z, lapack_int ldz,\n                                lapack_int* m, float* pl, float* pr, float* dif,\n                                lapack_complex_float* work, lapack_int lwork,\n                                lapack_int* iwork, lapack_int liwork );\nlapack_int LAPACKE_ztgsen_work( int matrix_order, lapack_int ijob,\n                                lapack_logical wantq, lapack_logical wantz,\n                                const lapack_logical* select, lapack_int n,\n                                lapack_complex_double* a, lapack_int lda,\n                                lapack_complex_double* b, lapack_int ldb,\n                                lapack_complex_double* alpha,\n                                lapack_complex_double* beta,\n                                lapack_complex_double* q, lapack_int ldq,\n                                lapack_complex_double* z, lapack_int ldz,\n                                lapack_int* m, double* pl, double* pr,\n                                double* dif, lapack_complex_double* work,\n                                lapack_int lwork, lapack_int* iwork,\n                                lapack_int liwork );\n\nlapack_int LAPACKE_stgsja_work( int matrix_order, char jobu, char jobv,\n                                char jobq, lapack_int m, lapack_int p,\n                                lapack_int n, lapack_int k, lapack_int l,\n                                float* a, lapack_int lda, float* b,\n                                lapack_int ldb, float tola, float tolb,\n                                float* alpha, float* beta, float* u,\n                                lapack_int ldu, float* v, lapack_int ldv,\n                                float* q, lapack_int ldq, float* work,\n                                lapack_int* ncycle );\nlapack_int LAPACKE_dtgsja_work( int matrix_order, char jobu, char jobv,\n                                char jobq, lapack_int m, lapack_int p,\n                                lapack_int n, lapack_int k, lapack_int l,\n                                double* a, lapack_int lda, double* b,\n                                lapack_int ldb, double tola, double tolb,\n                                double* alpha, double* beta, double* u,\n                                lapack_int ldu, double* v, lapack_int ldv,\n                                double* q, lapack_int ldq, double* work,\n                                lapack_int* ncycle );\nlapack_int LAPACKE_ctgsja_work( int matrix_order, char jobu, char jobv,\n                                char jobq, lapack_int m, lapack_int p,\n                                lapack_int n, lapack_int k, lapack_int l,\n                                lapack_complex_float* a, lapack_int lda,\n                                lapack_complex_float* b, lapack_int ldb,\n                                float tola, float tolb, float* alpha,\n                                float* beta, lapack_complex_float* u,\n                                lapack_int ldu, lapack_complex_float* v,\n                                lapack_int ldv, lapack_complex_float* q,\n                                lapack_int ldq, lapack_complex_float* work,\n                                lapack_int* ncycle );\nlapack_int LAPACKE_ztgsja_work( int matrix_order, char jobu, char jobv,\n                                char jobq, lapack_int m, lapack_int p,\n                                lapack_int n, lapack_int k, lapack_int l,\n                                lapack_complex_double* a, lapack_int lda,\n                                lapack_complex_double* b, lapack_int ldb,\n                                double tola, double tolb, double* alpha,\n                                double* beta, lapack_complex_double* u,\n                                lapack_int ldu, lapack_complex_double* v,\n                                lapack_int ldv, lapack_complex_double* q,\n                                lapack_int ldq, lapack_complex_double* work,\n                                lapack_int* ncycle );\n\nlapack_int LAPACKE_stgsna_work( int matrix_order, char job, char howmny,\n                                const lapack_logical* select, lapack_int n,\n                                const float* a, lapack_int lda, const float* b,\n                                lapack_int ldb, const float* vl,\n                                lapack_int ldvl, const float* vr,\n                                lapack_int ldvr, float* s, float* dif,\n                                lapack_int mm, lapack_int* m, float* work,\n                                lapack_int lwork, lapack_int* iwork );\nlapack_int LAPACKE_dtgsna_work( int matrix_order, char job, char howmny,\n                                const lapack_logical* select, lapack_int n,\n                                const double* a, lapack_int lda,\n                                const double* b, lapack_int ldb,\n                                const double* vl, lapack_int ldvl,\n                                const double* vr, lapack_int ldvr, double* s,\n                                double* dif, lapack_int mm, lapack_int* m,\n                                double* work, lapack_int lwork,\n                                lapack_int* iwork );\nlapack_int LAPACKE_ctgsna_work( int matrix_order, char job, char howmny,\n                                const lapack_logical* select, lapack_int n,\n                                const lapack_complex_float* a, lapack_int lda,\n                                const lapack_complex_float* b, lapack_int ldb,\n                                const lapack_complex_float* vl, lapack_int ldvl,\n                                const lapack_complex_float* vr, lapack_int ldvr,\n                                float* s, float* dif, lapack_int mm,\n                                lapack_int* m, lapack_complex_float* work,\n                                lapack_int lwork, lapack_int* iwork );\nlapack_int LAPACKE_ztgsna_work( int matrix_order, char job, char howmny,\n                                const lapack_logical* select, lapack_int n,\n                                const lapack_complex_double* a, lapack_int lda,\n                                const lapack_complex_double* b, lapack_int ldb,\n                                const lapack_complex_double* vl,\n                                lapack_int ldvl,\n                                const lapack_complex_double* vr,\n                                lapack_int ldvr, double* s, double* dif,\n                                lapack_int mm, lapack_int* m,\n                                lapack_complex_double* work, lapack_int lwork,\n                                lapack_int* iwork );\n\nlapack_int LAPACKE_stgsyl_work( int matrix_order, char trans, lapack_int ijob,\n                                lapack_int m, lapack_int n, const float* a,\n                                lapack_int lda, const float* b, lapack_int ldb,\n                                float* c, lapack_int ldc, const float* d,\n                                lapack_int ldd, const float* e, lapack_int lde,\n                                float* f, lapack_int ldf, float* scale,\n                                float* dif, float* work, lapack_int lwork,\n                                lapack_int* iwork );\nlapack_int LAPACKE_dtgsyl_work( int matrix_order, char trans, lapack_int ijob,\n                                lapack_int m, lapack_int n, const double* a,\n                                lapack_int lda, const double* b, lapack_int ldb,\n                                double* c, lapack_int ldc, const double* d,\n                                lapack_int ldd, const double* e, lapack_int lde,\n                                double* f, lapack_int ldf, double* scale,\n                                double* dif, double* work, lapack_int lwork,\n                                lapack_int* iwork );\nlapack_int LAPACKE_ctgsyl_work( int matrix_order, char trans, lapack_int ijob,\n                                lapack_int m, lapack_int n,\n                                const lapack_complex_float* a, lapack_int lda,\n                                const lapack_complex_float* b, lapack_int ldb,\n                                lapack_complex_float* c, lapack_int ldc,\n                                const lapack_complex_float* d, lapack_int ldd,\n                                const lapack_complex_float* e, lapack_int lde,\n                                lapack_complex_float* f, lapack_int ldf,\n                                float* scale, float* dif,\n                                lapack_complex_float* work, lapack_int lwork,\n                                lapack_int* iwork );\nlapack_int LAPACKE_ztgsyl_work( int matrix_order, char trans, lapack_int ijob,\n                                lapack_int m, lapack_int n,\n                                const lapack_complex_double* a, lapack_int lda,\n                                const lapack_complex_double* b, lapack_int ldb,\n                                lapack_complex_double* c, lapack_int ldc,\n                                const lapack_complex_double* d, lapack_int ldd,\n                                const lapack_complex_double* e, lapack_int lde,\n                                lapack_complex_double* f, lapack_int ldf,\n                                double* scale, double* dif,\n                                lapack_complex_double* work, lapack_int lwork,\n                                lapack_int* iwork );\n\nlapack_int LAPACKE_stpcon_work( int matrix_order, char norm, char uplo,\n                                char diag, lapack_int n, const float* ap,\n                                float* rcond, float* work, lapack_int* iwork );\nlapack_int LAPACKE_dtpcon_work( int matrix_order, char norm, char uplo,\n                                char diag, lapack_int n, const double* ap,\n                                double* rcond, double* work,\n                                lapack_int* iwork );\nlapack_int LAPACKE_ctpcon_work( int matrix_order, char norm, char uplo,\n                                char diag, lapack_int n,\n                                const lapack_complex_float* ap, float* rcond,\n                                lapack_complex_float* work, float* rwork );\nlapack_int LAPACKE_ztpcon_work( int matrix_order, char norm, char uplo,\n                                char diag, lapack_int n,\n                                const lapack_complex_double* ap, double* rcond,\n                                lapack_complex_double* work, double* rwork );\n\nlapack_int LAPACKE_stprfs_work( int matrix_order, char uplo, char trans,\n                                char diag, lapack_int n, lapack_int nrhs,\n                                const float* ap, const float* b, lapack_int ldb,\n                                const float* x, lapack_int ldx, float* ferr,\n                                float* berr, float* work, lapack_int* iwork );\nlapack_int LAPACKE_dtprfs_work( int matrix_order, char uplo, char trans,\n                                char diag, lapack_int n, lapack_int nrhs,\n                                const double* ap, const double* b,\n                                lapack_int ldb, const double* x, lapack_int ldx,\n                                double* ferr, double* berr, double* work,\n                                lapack_int* iwork );\nlapack_int LAPACKE_ctprfs_work( int matrix_order, char uplo, char trans,\n                                char diag, lapack_int n, lapack_int nrhs,\n                                const lapack_complex_float* ap,\n                                const lapack_complex_float* b, lapack_int ldb,\n                                const lapack_complex_float* x, lapack_int ldx,\n                                float* ferr, float* berr,\n                                lapack_complex_float* work, float* rwork );\nlapack_int LAPACKE_ztprfs_work( int matrix_order, char uplo, char trans,\n                                char diag, lapack_int n, lapack_int nrhs,\n                                const lapack_complex_double* ap,\n                                const lapack_complex_double* b, lapack_int ldb,\n                                const lapack_complex_double* x, lapack_int ldx,\n                                double* ferr, double* berr,\n                                lapack_complex_double* work, double* rwork );\n\nlapack_int LAPACKE_stptri_work( int matrix_order, char uplo, char diag,\n                                lapack_int n, float* ap );\nlapack_int LAPACKE_dtptri_work( int matrix_order, char uplo, char diag,\n                                lapack_int n, double* ap );\nlapack_int LAPACKE_ctptri_work( int matrix_order, char uplo, char diag,\n                                lapack_int n, lapack_complex_float* ap );\nlapack_int LAPACKE_ztptri_work( int matrix_order, char uplo, char diag,\n                                lapack_int n, lapack_complex_double* ap );\n\nlapack_int LAPACKE_stptrs_work( int matrix_order, char uplo, char trans,\n                                char diag, lapack_int n, lapack_int nrhs,\n                                const float* ap, float* b, lapack_int ldb );\nlapack_int LAPACKE_dtptrs_work( int matrix_order, char uplo, char trans,\n                                char diag, lapack_int n, lapack_int nrhs,\n                                const double* ap, double* b, lapack_int ldb );\nlapack_int LAPACKE_ctptrs_work( int matrix_order, char uplo, char trans,\n                                char diag, lapack_int n, lapack_int nrhs,\n                                const lapack_complex_float* ap,\n                                lapack_complex_float* b, lapack_int ldb );\nlapack_int LAPACKE_ztptrs_work( int matrix_order, char uplo, char trans,\n                                char diag, lapack_int n, lapack_int nrhs,\n                                const lapack_complex_double* ap,\n                                lapack_complex_double* b, lapack_int ldb );\n\nlapack_int LAPACKE_stpttf_work( int matrix_order, char transr, char uplo,\n                                lapack_int n, const float* ap, float* arf );\nlapack_int LAPACKE_dtpttf_work( int matrix_order, char transr, char uplo,\n                                lapack_int n, const double* ap, double* arf );\nlapack_int LAPACKE_ctpttf_work( int matrix_order, char transr, char uplo,\n                                lapack_int n, const lapack_complex_float* ap,\n                                lapack_complex_float* arf );\nlapack_int LAPACKE_ztpttf_work( int matrix_order, char transr, char uplo,\n                                lapack_int n, const lapack_complex_double* ap,\n                                lapack_complex_double* arf );\n\nlapack_int LAPACKE_stpttr_work( int matrix_order, char uplo, lapack_int n,\n                                const float* ap, float* a, lapack_int lda );\nlapack_int LAPACKE_dtpttr_work( int matrix_order, char uplo, lapack_int n,\n                                const double* ap, double* a, lapack_int lda );\nlapack_int LAPACKE_ctpttr_work( int matrix_order, char uplo, lapack_int n,\n                                const lapack_complex_float* ap,\n                                lapack_complex_float* a, lapack_int lda );\nlapack_int LAPACKE_ztpttr_work( int matrix_order, char uplo, lapack_int n,\n                                const lapack_complex_double* ap,\n                                lapack_complex_double* a, lapack_int lda );\n\nlapack_int LAPACKE_strcon_work( int matrix_order, char norm, char uplo,\n                                char diag, lapack_int n, const float* a,\n                                lapack_int lda, float* rcond, float* work,\n                                lapack_int* iwork );\nlapack_int LAPACKE_dtrcon_work( int matrix_order, char norm, char uplo,\n                                char diag, lapack_int n, const double* a,\n                                lapack_int lda, double* rcond, double* work,\n                                lapack_int* iwork );\nlapack_int LAPACKE_ctrcon_work( int matrix_order, char norm, char uplo,\n                                char diag, lapack_int n,\n                                const lapack_complex_float* a, lapack_int lda,\n                                float* rcond, lapack_complex_float* work,\n                                float* rwork );\nlapack_int LAPACKE_ztrcon_work( int matrix_order, char norm, char uplo,\n                                char diag, lapack_int n,\n                                const lapack_complex_double* a, lapack_int lda,\n                                double* rcond, lapack_complex_double* work,\n                                double* rwork );\n\nlapack_int LAPACKE_strevc_work( int matrix_order, char side, char howmny,\n                                lapack_logical* select, lapack_int n,\n                                const float* t, lapack_int ldt, float* vl,\n                                lapack_int ldvl, float* vr, lapack_int ldvr,\n                                lapack_int mm, lapack_int* m, float* work );\nlapack_int LAPACKE_dtrevc_work( int matrix_order, char side, char howmny,\n                                lapack_logical* select, lapack_int n,\n                                const double* t, lapack_int ldt, double* vl,\n                                lapack_int ldvl, double* vr, lapack_int ldvr,\n                                lapack_int mm, lapack_int* m, double* work );\nlapack_int LAPACKE_ctrevc_work( int matrix_order, char side, char howmny,\n                                const lapack_logical* select, lapack_int n,\n                                lapack_complex_float* t, lapack_int ldt,\n                                lapack_complex_float* vl, lapack_int ldvl,\n                                lapack_complex_float* vr, lapack_int ldvr,\n                                lapack_int mm, lapack_int* m,\n                                lapack_complex_float* work, float* rwork );\nlapack_int LAPACKE_ztrevc_work( int matrix_order, char side, char howmny,\n                                const lapack_logical* select, lapack_int n,\n                                lapack_complex_double* t, lapack_int ldt,\n                                lapack_complex_double* vl, lapack_int ldvl,\n                                lapack_complex_double* vr, lapack_int ldvr,\n                                lapack_int mm, lapack_int* m,\n                                lapack_complex_double* work, double* rwork );\n\nlapack_int LAPACKE_strexc_work( int matrix_order, char compq, lapack_int n,\n                                float* t, lapack_int ldt, float* q,\n                                lapack_int ldq, lapack_int* ifst,\n                                lapack_int* ilst, float* work );\nlapack_int LAPACKE_dtrexc_work( int matrix_order, char compq, lapack_int n,\n                                double* t, lapack_int ldt, double* q,\n                                lapack_int ldq, lapack_int* ifst,\n                                lapack_int* ilst, double* work );\nlapack_int LAPACKE_ctrexc_work( int matrix_order, char compq, lapack_int n,\n                                lapack_complex_float* t, lapack_int ldt,\n                                lapack_complex_float* q, lapack_int ldq,\n                                lapack_int ifst, lapack_int ilst );\nlapack_int LAPACKE_ztrexc_work( int matrix_order, char compq, lapack_int n,\n                                lapack_complex_double* t, lapack_int ldt,\n                                lapack_complex_double* q, lapack_int ldq,\n                                lapack_int ifst, lapack_int ilst );\n\nlapack_int LAPACKE_strrfs_work( int matrix_order, char uplo, char trans,\n                                char diag, lapack_int n, lapack_int nrhs,\n                                const float* a, lapack_int lda, const float* b,\n                                lapack_int ldb, const float* x, lapack_int ldx,\n                                float* ferr, float* berr, float* work,\n                                lapack_int* iwork );\nlapack_int LAPACKE_dtrrfs_work( int matrix_order, char uplo, char trans,\n                                char diag, lapack_int n, lapack_int nrhs,\n                                const double* a, lapack_int lda,\n                                const double* b, lapack_int ldb,\n                                const double* x, lapack_int ldx, double* ferr,\n                                double* berr, double* work, lapack_int* iwork );\nlapack_int LAPACKE_ctrrfs_work( int matrix_order, char uplo, char trans,\n                                char diag, lapack_int n, lapack_int nrhs,\n                                const lapack_complex_float* a, lapack_int lda,\n                                const lapack_complex_float* b, lapack_int ldb,\n                                const lapack_complex_float* x, lapack_int ldx,\n                                float* ferr, float* berr,\n                                lapack_complex_float* work, float* rwork );\nlapack_int LAPACKE_ztrrfs_work( int matrix_order, char uplo, char trans,\n                                char diag, lapack_int n, lapack_int nrhs,\n                                const lapack_complex_double* a, lapack_int lda,\n                                const lapack_complex_double* b, lapack_int ldb,\n                                const lapack_complex_double* x, lapack_int ldx,\n                                double* ferr, double* berr,\n                                lapack_complex_double* work, double* rwork );\n\nlapack_int LAPACKE_strsen_work( int matrix_order, char job, char compq,\n                                const lapack_logical* select, lapack_int n,\n                                float* t, lapack_int ldt, float* q,\n                                lapack_int ldq, float* wr, float* wi,\n                                lapack_int* m, float* s, float* sep,\n                                float* work, lapack_int lwork,\n                                lapack_int* iwork, lapack_int liwork );\nlapack_int LAPACKE_dtrsen_work( int matrix_order, char job, char compq,\n                                const lapack_logical* select, lapack_int n,\n                                double* t, lapack_int ldt, double* q,\n                                lapack_int ldq, double* wr, double* wi,\n                                lapack_int* m, double* s, double* sep,\n                                double* work, lapack_int lwork,\n                                lapack_int* iwork, lapack_int liwork );\nlapack_int LAPACKE_ctrsen_work( int matrix_order, char job, char compq,\n                                const lapack_logical* select, lapack_int n,\n                                lapack_complex_float* t, lapack_int ldt,\n                                lapack_complex_float* q, lapack_int ldq,\n                                lapack_complex_float* w, lapack_int* m,\n                                float* s, float* sep,\n                                lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_ztrsen_work( int matrix_order, char job, char compq,\n                                const lapack_logical* select, lapack_int n,\n                                lapack_complex_double* t, lapack_int ldt,\n                                lapack_complex_double* q, lapack_int ldq,\n                                lapack_complex_double* w, lapack_int* m,\n                                double* s, double* sep,\n                                lapack_complex_double* work, lapack_int lwork );\n\nlapack_int LAPACKE_strsna_work( int matrix_order, char job, char howmny,\n                                const lapack_logical* select, lapack_int n,\n                                const float* t, lapack_int ldt, const float* vl,\n                                lapack_int ldvl, const float* vr,\n                                lapack_int ldvr, float* s, float* sep,\n                                lapack_int mm, lapack_int* m, float* work,\n                                lapack_int ldwork, lapack_int* iwork );\nlapack_int LAPACKE_dtrsna_work( int matrix_order, char job, char howmny,\n                                const lapack_logical* select, lapack_int n,\n                                const double* t, lapack_int ldt,\n                                const double* vl, lapack_int ldvl,\n                                const double* vr, lapack_int ldvr, double* s,\n                                double* sep, lapack_int mm, lapack_int* m,\n                                double* work, lapack_int ldwork,\n                                lapack_int* iwork );\nlapack_int LAPACKE_ctrsna_work( int matrix_order, char job, char howmny,\n                                const lapack_logical* select, lapack_int n,\n                                const lapack_complex_float* t, lapack_int ldt,\n                                const lapack_complex_float* vl, lapack_int ldvl,\n                                const lapack_complex_float* vr, lapack_int ldvr,\n                                float* s, float* sep, lapack_int mm,\n                                lapack_int* m, lapack_complex_float* work,\n                                lapack_int ldwork, float* rwork );\nlapack_int LAPACKE_ztrsna_work( int matrix_order, char job, char howmny,\n                                const lapack_logical* select, lapack_int n,\n                                const lapack_complex_double* t, lapack_int ldt,\n                                const lapack_complex_double* vl,\n                                lapack_int ldvl,\n                                const lapack_complex_double* vr,\n                                lapack_int ldvr, double* s, double* sep,\n                                lapack_int mm, lapack_int* m,\n                                lapack_complex_double* work, lapack_int ldwork,\n                                double* rwork );\n\nlapack_int LAPACKE_strsyl_work( int matrix_order, char trana, char tranb,\n                                lapack_int isgn, lapack_int m, lapack_int n,\n                                const float* a, lapack_int lda, const float* b,\n                                lapack_int ldb, float* c, lapack_int ldc,\n                                float* scale );\nlapack_int LAPACKE_dtrsyl_work( int matrix_order, char trana, char tranb,\n                                lapack_int isgn, lapack_int m, lapack_int n,\n                                const double* a, lapack_int lda,\n                                const double* b, lapack_int ldb, double* c,\n                                lapack_int ldc, double* scale );\nlapack_int LAPACKE_ctrsyl_work( int matrix_order, char trana, char tranb,\n                                lapack_int isgn, lapack_int m, lapack_int n,\n                                const lapack_complex_float* a, lapack_int lda,\n                                const lapack_complex_float* b, lapack_int ldb,\n                                lapack_complex_float* c, lapack_int ldc,\n                                float* scale );\nlapack_int LAPACKE_ztrsyl_work( int matrix_order, char trana, char tranb,\n                                lapack_int isgn, lapack_int m, lapack_int n,\n                                const lapack_complex_double* a, lapack_int lda,\n                                const lapack_complex_double* b, lapack_int ldb,\n                                lapack_complex_double* c, lapack_int ldc,\n                                double* scale );\n\nlapack_int LAPACKE_strtri_work( int matrix_order, char uplo, char diag,\n                                lapack_int n, float* a, lapack_int lda );\nlapack_int LAPACKE_dtrtri_work( int matrix_order, char uplo, char diag,\n                                lapack_int n, double* a, lapack_int lda );\nlapack_int LAPACKE_ctrtri_work( int matrix_order, char uplo, char diag,\n                                lapack_int n, lapack_complex_float* a,\n                                lapack_int lda );\nlapack_int LAPACKE_ztrtri_work( int matrix_order, char uplo, char diag,\n                                lapack_int n, lapack_complex_double* a,\n                                lapack_int lda );\n\nlapack_int LAPACKE_strtrs_work( int matrix_order, char uplo, char trans,\n                                char diag, lapack_int n, lapack_int nrhs,\n                                const float* a, lapack_int lda, float* b,\n                                lapack_int ldb );\nlapack_int LAPACKE_dtrtrs_work( int matrix_order, char uplo, char trans,\n                                char diag, lapack_int n, lapack_int nrhs,\n                                const double* a, lapack_int lda, double* b,\n                                lapack_int ldb );\nlapack_int LAPACKE_ctrtrs_work( int matrix_order, char uplo, char trans,\n                                char diag, lapack_int n, lapack_int nrhs,\n                                const lapack_complex_float* a, lapack_int lda,\n                                lapack_complex_float* b, lapack_int ldb );\nlapack_int LAPACKE_ztrtrs_work( int matrix_order, char uplo, char trans,\n                                char diag, lapack_int n, lapack_int nrhs,\n                                const lapack_complex_double* a, lapack_int lda,\n                                lapack_complex_double* b, lapack_int ldb );\n\nlapack_int LAPACKE_strttf_work( int matrix_order, char transr, char uplo,\n                                lapack_int n, const float* a, lapack_int lda,\n                                float* arf );\nlapack_int LAPACKE_dtrttf_work( int matrix_order, char transr, char uplo,\n                                lapack_int n, const double* a, lapack_int lda,\n                                double* arf );\nlapack_int LAPACKE_ctrttf_work( int matrix_order, char transr, char uplo,\n                                lapack_int n, const lapack_complex_float* a,\n                                lapack_int lda, lapack_complex_float* arf );\nlapack_int LAPACKE_ztrttf_work( int matrix_order, char transr, char uplo,\n                                lapack_int n, const lapack_complex_double* a,\n                                lapack_int lda, lapack_complex_double* arf );\n\nlapack_int LAPACKE_strttp_work( int matrix_order, char uplo, lapack_int n,\n                                const float* a, lapack_int lda, float* ap );\nlapack_int LAPACKE_dtrttp_work( int matrix_order, char uplo, lapack_int n,\n                                const double* a, lapack_int lda, double* ap );\nlapack_int LAPACKE_ctrttp_work( int matrix_order, char uplo, lapack_int n,\n                                const lapack_complex_float* a, lapack_int lda,\n                                lapack_complex_float* ap );\nlapack_int LAPACKE_ztrttp_work( int matrix_order, char uplo, lapack_int n,\n                                const lapack_complex_double* a, lapack_int lda,\n                                lapack_complex_double* ap );\n\nlapack_int LAPACKE_stzrzf_work( int matrix_order, lapack_int m, lapack_int n,\n                                float* a, lapack_int lda, float* tau,\n                                float* work, lapack_int lwork );\nlapack_int LAPACKE_dtzrzf_work( int matrix_order, lapack_int m, lapack_int n,\n                                double* a, lapack_int lda, double* tau,\n                                double* work, lapack_int lwork );\nlapack_int LAPACKE_ctzrzf_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_complex_float* a, lapack_int lda,\n                                lapack_complex_float* tau,\n                                lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_ztzrzf_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_complex_double* a, lapack_int lda,\n                                lapack_complex_double* tau,\n                                lapack_complex_double* work, lapack_int lwork );\n\nlapack_int LAPACKE_cungbr_work( int matrix_order, char vect, lapack_int m,\n                                lapack_int n, lapack_int k,\n                                lapack_complex_float* a, lapack_int lda,\n                                const lapack_complex_float* tau,\n                                lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_zungbr_work( int matrix_order, char vect, lapack_int m,\n                                lapack_int n, lapack_int k,\n                                lapack_complex_double* a, lapack_int lda,\n                                const lapack_complex_double* tau,\n                                lapack_complex_double* work, lapack_int lwork );\n\nlapack_int LAPACKE_cunghr_work( int matrix_order, lapack_int n, lapack_int ilo,\n                                lapack_int ihi, lapack_complex_float* a,\n                                lapack_int lda, const lapack_complex_float* tau,\n                                lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_zunghr_work( int matrix_order, lapack_int n, lapack_int ilo,\n                                lapack_int ihi, lapack_complex_double* a,\n                                lapack_int lda,\n                                const lapack_complex_double* tau,\n                                lapack_complex_double* work, lapack_int lwork );\n\nlapack_int LAPACKE_cunglq_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int k, lapack_complex_float* a,\n                                lapack_int lda, const lapack_complex_float* tau,\n                                lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_zunglq_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int k, lapack_complex_double* a,\n                                lapack_int lda,\n                                const lapack_complex_double* tau,\n                                lapack_complex_double* work, lapack_int lwork );\n\nlapack_int LAPACKE_cungql_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int k, lapack_complex_float* a,\n                                lapack_int lda, const lapack_complex_float* tau,\n                                lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_zungql_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int k, lapack_complex_double* a,\n                                lapack_int lda,\n                                const lapack_complex_double* tau,\n                                lapack_complex_double* work, lapack_int lwork );\n\nlapack_int LAPACKE_cungqr_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int k, lapack_complex_float* a,\n                                lapack_int lda, const lapack_complex_float* tau,\n                                lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_zungqr_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int k, lapack_complex_double* a,\n                                lapack_int lda,\n                                const lapack_complex_double* tau,\n                                lapack_complex_double* work, lapack_int lwork );\n\nlapack_int LAPACKE_cungrq_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int k, lapack_complex_float* a,\n                                lapack_int lda, const lapack_complex_float* tau,\n                                lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_zungrq_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int k, lapack_complex_double* a,\n                                lapack_int lda,\n                                const lapack_complex_double* tau,\n                                lapack_complex_double* work, lapack_int lwork );\n\nlapack_int LAPACKE_cungtr_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_complex_float* a, lapack_int lda,\n                                const lapack_complex_float* tau,\n                                lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_zungtr_work( int matrix_order, char uplo, lapack_int n,\n                                lapack_complex_double* a, lapack_int lda,\n                                const lapack_complex_double* tau,\n                                lapack_complex_double* work, lapack_int lwork );\n\nlapack_int LAPACKE_cunmbr_work( int matrix_order, char vect, char side,\n                                char trans, lapack_int m, lapack_int n,\n                                lapack_int k, const lapack_complex_float* a,\n                                lapack_int lda, const lapack_complex_float* tau,\n                                lapack_complex_float* c, lapack_int ldc,\n                                lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_zunmbr_work( int matrix_order, char vect, char side,\n                                char trans, lapack_int m, lapack_int n,\n                                lapack_int k, const lapack_complex_double* a,\n                                lapack_int lda,\n                                const lapack_complex_double* tau,\n                                lapack_complex_double* c, lapack_int ldc,\n                                lapack_complex_double* work, lapack_int lwork );\n\nlapack_int LAPACKE_cunmhr_work( int matrix_order, char side, char trans,\n                                lapack_int m, lapack_int n, lapack_int ilo,\n                                lapack_int ihi, const lapack_complex_float* a,\n                                lapack_int lda, const lapack_complex_float* tau,\n                                lapack_complex_float* c, lapack_int ldc,\n                                lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_zunmhr_work( int matrix_order, char side, char trans,\n                                lapack_int m, lapack_int n, lapack_int ilo,\n                                lapack_int ihi, const lapack_complex_double* a,\n                                lapack_int lda,\n                                const lapack_complex_double* tau,\n                                lapack_complex_double* c, lapack_int ldc,\n                                lapack_complex_double* work, lapack_int lwork );\n\nlapack_int LAPACKE_cunmlq_work( int matrix_order, char side, char trans,\n                                lapack_int m, lapack_int n, lapack_int k,\n                                const lapack_complex_float* a, lapack_int lda,\n                                const lapack_complex_float* tau,\n                                lapack_complex_float* c, lapack_int ldc,\n                                lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_zunmlq_work( int matrix_order, char side, char trans,\n                                lapack_int m, lapack_int n, lapack_int k,\n                                const lapack_complex_double* a, lapack_int lda,\n                                const lapack_complex_double* tau,\n                                lapack_complex_double* c, lapack_int ldc,\n                                lapack_complex_double* work, lapack_int lwork );\n\nlapack_int LAPACKE_cunmql_work( int matrix_order, char side, char trans,\n                                lapack_int m, lapack_int n, lapack_int k,\n                                const lapack_complex_float* a, lapack_int lda,\n                                const lapack_complex_float* tau,\n                                lapack_complex_float* c, lapack_int ldc,\n                                lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_zunmql_work( int matrix_order, char side, char trans,\n                                lapack_int m, lapack_int n, lapack_int k,\n                                const lapack_complex_double* a, lapack_int lda,\n                                const lapack_complex_double* tau,\n                                lapack_complex_double* c, lapack_int ldc,\n                                lapack_complex_double* work, lapack_int lwork );\n\nlapack_int LAPACKE_cunmqr_work( int matrix_order, char side, char trans,\n                                lapack_int m, lapack_int n, lapack_int k,\n                                const lapack_complex_float* a, lapack_int lda,\n                                const lapack_complex_float* tau,\n                                lapack_complex_float* c, lapack_int ldc,\n                                lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_zunmqr_work( int matrix_order, char side, char trans,\n                                lapack_int m, lapack_int n, lapack_int k,\n                                const lapack_complex_double* a, lapack_int lda,\n                                const lapack_complex_double* tau,\n                                lapack_complex_double* c, lapack_int ldc,\n                                lapack_complex_double* work, lapack_int lwork );\n\nlapack_int LAPACKE_cunmrq_work( int matrix_order, char side, char trans,\n                                lapack_int m, lapack_int n, lapack_int k,\n                                const lapack_complex_float* a, lapack_int lda,\n                                const lapack_complex_float* tau,\n                                lapack_complex_float* c, lapack_int ldc,\n                                lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_zunmrq_work( int matrix_order, char side, char trans,\n                                lapack_int m, lapack_int n, lapack_int k,\n                                const lapack_complex_double* a, lapack_int lda,\n                                const lapack_complex_double* tau,\n                                lapack_complex_double* c, lapack_int ldc,\n                                lapack_complex_double* work, lapack_int lwork );\n\nlapack_int LAPACKE_cunmrz_work( int matrix_order, char side, char trans,\n                                lapack_int m, lapack_int n, lapack_int k,\n                                lapack_int l, const lapack_complex_float* a,\n                                lapack_int lda, const lapack_complex_float* tau,\n                                lapack_complex_float* c, lapack_int ldc,\n                                lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_zunmrz_work( int matrix_order, char side, char trans,\n                                lapack_int m, lapack_int n, lapack_int k,\n                                lapack_int l, const lapack_complex_double* a,\n                                lapack_int lda,\n                                const lapack_complex_double* tau,\n                                lapack_complex_double* c, lapack_int ldc,\n                                lapack_complex_double* work, lapack_int lwork );\n\nlapack_int LAPACKE_cunmtr_work( int matrix_order, char side, char uplo,\n                                char trans, lapack_int m, lapack_int n,\n                                const lapack_complex_float* a, lapack_int lda,\n                                const lapack_complex_float* tau,\n                                lapack_complex_float* c, lapack_int ldc,\n                                lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_zunmtr_work( int matrix_order, char side, char uplo,\n                                char trans, lapack_int m, lapack_int n,\n                                const lapack_complex_double* a, lapack_int lda,\n                                const lapack_complex_double* tau,\n                                lapack_complex_double* c, lapack_int ldc,\n                                lapack_complex_double* work, lapack_int lwork );\n\nlapack_int LAPACKE_cupgtr_work( int matrix_order, char uplo, lapack_int n,\n                                const lapack_complex_float* ap,\n                                const lapack_complex_float* tau,\n                                lapack_complex_float* q, lapack_int ldq,\n                                lapack_complex_float* work );\nlapack_int LAPACKE_zupgtr_work( int matrix_order, char uplo, lapack_int n,\n                                const lapack_complex_double* ap,\n                                const lapack_complex_double* tau,\n                                lapack_complex_double* q, lapack_int ldq,\n                                lapack_complex_double* work );\n\nlapack_int LAPACKE_cupmtr_work( int matrix_order, char side, char uplo,\n                                char trans, lapack_int m, lapack_int n,\n                                const lapack_complex_float* ap,\n                                const lapack_complex_float* tau,\n                                lapack_complex_float* c, lapack_int ldc,\n                                lapack_complex_float* work );\nlapack_int LAPACKE_zupmtr_work( int matrix_order, char side, char uplo,\n                                char trans, lapack_int m, lapack_int n,\n                                const lapack_complex_double* ap,\n                                const lapack_complex_double* tau,\n                                lapack_complex_double* c, lapack_int ldc,\n                                lapack_complex_double* work );\n\nlapack_int LAPACKE_claghe( int matrix_order, lapack_int n, lapack_int k,\n                           const float* d, lapack_complex_float* a,\n                           lapack_int lda, lapack_int* iseed );\nlapack_int LAPACKE_zlaghe( int matrix_order, lapack_int n, lapack_int k,\n                           const double* d, lapack_complex_double* a,\n                           lapack_int lda, lapack_int* iseed );\n\nlapack_int LAPACKE_slagsy( int matrix_order, lapack_int n, lapack_int k,\n                           const float* d, float* a, lapack_int lda,\n                           lapack_int* iseed );\nlapack_int LAPACKE_dlagsy( int matrix_order, lapack_int n, lapack_int k,\n                           const double* d, double* a, lapack_int lda,\n                           lapack_int* iseed );\nlapack_int LAPACKE_clagsy( int matrix_order, lapack_int n, lapack_int k,\n                           const float* d, lapack_complex_float* a,\n                           lapack_int lda, lapack_int* iseed );\nlapack_int LAPACKE_zlagsy( int matrix_order, lapack_int n, lapack_int k,\n                           const double* d, lapack_complex_double* a,\n                           lapack_int lda, lapack_int* iseed );\n\nlapack_int LAPACKE_slapmr( int matrix_order, lapack_logical forwrd,\n                           lapack_int m, lapack_int n, float* x, lapack_int ldx,\n                           lapack_int* k );\nlapack_int LAPACKE_dlapmr( int matrix_order, lapack_logical forwrd,\n                           lapack_int m, lapack_int n, double* x,\n                           lapack_int ldx, lapack_int* k );\nlapack_int LAPACKE_clapmr( int matrix_order, lapack_logical forwrd,\n                           lapack_int m, lapack_int n, lapack_complex_float* x,\n                           lapack_int ldx, lapack_int* k );\nlapack_int LAPACKE_zlapmr( int matrix_order, lapack_logical forwrd,\n                           lapack_int m, lapack_int n, lapack_complex_double* x,\n                           lapack_int ldx, lapack_int* k );\n\n\nfloat LAPACKE_slapy2( float x, float y );\ndouble LAPACKE_dlapy2( double x, double y );\n\nfloat LAPACKE_slapy3( float x, float y, float z );\ndouble LAPACKE_dlapy3( double x, double y, double z );\n\nlapack_int LAPACKE_slartgp( float f, float g, float* cs, float* sn, float* r );\nlapack_int LAPACKE_dlartgp( double f, double g, double* cs, double* sn,\n                            double* r );\n\nlapack_int LAPACKE_slartgs( float x, float y, float sigma, float* cs,\n                            float* sn );\nlapack_int LAPACKE_dlartgs( double x, double y, double sigma, double* cs,\n                            double* sn );\n\n\n//LAPACK 3.3.0\nlapack_int LAPACKE_cbbcsd( int matrix_order, char jobu1, char jobu2,\n                           char jobv1t, char jobv2t, char trans, lapack_int m,\n                           lapack_int p, lapack_int q, float* theta, float* phi,\n                           lapack_complex_float* u1, lapack_int ldu1,\n                           lapack_complex_float* u2, lapack_int ldu2,\n                           lapack_complex_float* v1t, lapack_int ldv1t,\n                           lapack_complex_float* v2t, lapack_int ldv2t,\n                           float* b11d, float* b11e, float* b12d, float* b12e,\n                           float* b21d, float* b21e, float* b22d, float* b22e );\nlapack_int LAPACKE_cbbcsd_work( int matrix_order, char jobu1, char jobu2,\n                                char jobv1t, char jobv2t, char trans,\n                                lapack_int m, lapack_int p, lapack_int q,\n                                float* theta, float* phi,\n                                lapack_complex_float* u1, lapack_int ldu1,\n                                lapack_complex_float* u2, lapack_int ldu2,\n                                lapack_complex_float* v1t, lapack_int ldv1t,\n                                lapack_complex_float* v2t, lapack_int ldv2t,\n                                float* b11d, float* b11e, float* b12d,\n                                float* b12e, float* b21d, float* b21e,\n                                float* b22d, float* b22e, float* rwork,\n                                lapack_int lrwork );\nlapack_int LAPACKE_cheswapr( int matrix_order, char uplo, lapack_int n,\n                             lapack_complex_float* a, lapack_int i1,\n                             lapack_int i2 );\nlapack_int LAPACKE_cheswapr_work( int matrix_order, char uplo, lapack_int n,\n                                  lapack_complex_float* a, lapack_int i1,\n                                  lapack_int i2 );\nlapack_int LAPACKE_chetri2( int matrix_order, char uplo, lapack_int n,\n                            lapack_complex_float* a, lapack_int lda,\n                            const lapack_int* ipiv );\nlapack_int LAPACKE_chetri2_work( int matrix_order, char uplo, lapack_int n,\n                                 lapack_complex_float* a, lapack_int lda,\n                                 const lapack_int* ipiv,\n                                 lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_chetri2x( int matrix_order, char uplo, lapack_int n,\n                             lapack_complex_float* a, lapack_int lda,\n                             const lapack_int* ipiv, lapack_int nb );\nlapack_int LAPACKE_chetri2x_work( int matrix_order, char uplo, lapack_int n,\n                                  lapack_complex_float* a, lapack_int lda,\n                                  const lapack_int* ipiv,\n                                  lapack_complex_float* work, lapack_int nb );\nlapack_int LAPACKE_chetrs2( int matrix_order, char uplo, lapack_int n,\n                            lapack_int nrhs, const lapack_complex_float* a,\n                            lapack_int lda, const lapack_int* ipiv,\n                            lapack_complex_float* b, lapack_int ldb );\nlapack_int LAPACKE_chetrs2_work( int matrix_order, char uplo, lapack_int n,\n                                 lapack_int nrhs, const lapack_complex_float* a,\n                                 lapack_int lda, const lapack_int* ipiv,\n                                 lapack_complex_float* b, lapack_int ldb,\n                                 lapack_complex_float* work );\nlapack_int LAPACKE_csyconv( int matrix_order, char uplo, char way, lapack_int n,\n                            lapack_complex_float* a, lapack_int lda,\n                            const lapack_int* ipiv );\nlapack_int LAPACKE_csyconv_work( int matrix_order, char uplo, char way,\n                                 lapack_int n, lapack_complex_float* a,\n                                 lapack_int lda, const lapack_int* ipiv,\n                                 lapack_complex_float* work );\nlapack_int LAPACKE_csyswapr( int matrix_order, char uplo, lapack_int n,\n                             lapack_complex_float* a, lapack_int i1,\n                             lapack_int i2 );\nlapack_int LAPACKE_csyswapr_work( int matrix_order, char uplo, lapack_int n,\n                                  lapack_complex_float* a, lapack_int i1,\n                                  lapack_int i2 );\nlapack_int LAPACKE_csytri2( int matrix_order, char uplo, lapack_int n,\n                            lapack_complex_float* a, lapack_int lda,\n                            const lapack_int* ipiv );\nlapack_int LAPACKE_csytri2_work( int matrix_order, char uplo, lapack_int n,\n                                 lapack_complex_float* a, lapack_int lda,\n                                 const lapack_int* ipiv,\n                                 lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_csytri2x( int matrix_order, char uplo, lapack_int n,\n                             lapack_complex_float* a, lapack_int lda,\n                             const lapack_int* ipiv, lapack_int nb );\nlapack_int LAPACKE_csytri2x_work( int matrix_order, char uplo, lapack_int n,\n                                  lapack_complex_float* a, lapack_int lda,\n                                  const lapack_int* ipiv,\n                                  lapack_complex_float* work, lapack_int nb );\nlapack_int LAPACKE_csytrs2( int matrix_order, char uplo, lapack_int n,\n                            lapack_int nrhs, const lapack_complex_float* a,\n                            lapack_int lda, const lapack_int* ipiv,\n                            lapack_complex_float* b, lapack_int ldb );\nlapack_int LAPACKE_csytrs2_work( int matrix_order, char uplo, lapack_int n,\n                                 lapack_int nrhs, const lapack_complex_float* a,\n                                 lapack_int lda, const lapack_int* ipiv,\n                                 lapack_complex_float* b, lapack_int ldb,\n                                 lapack_complex_float* work );\nlapack_int LAPACKE_cunbdb( int matrix_order, char trans, char signs,\n                           lapack_int m, lapack_int p, lapack_int q,\n                           lapack_complex_float* x11, lapack_int ldx11,\n                           lapack_complex_float* x12, lapack_int ldx12,\n                           lapack_complex_float* x21, lapack_int ldx21,\n                           lapack_complex_float* x22, lapack_int ldx22,\n                           float* theta, float* phi,\n                           lapack_complex_float* taup1,\n                           lapack_complex_float* taup2,\n                           lapack_complex_float* tauq1,\n                           lapack_complex_float* tauq2 );\nlapack_int LAPACKE_cunbdb_work( int matrix_order, char trans, char signs,\n                                lapack_int m, lapack_int p, lapack_int q,\n                                lapack_complex_float* x11, lapack_int ldx11,\n                                lapack_complex_float* x12, lapack_int ldx12,\n                                lapack_complex_float* x21, lapack_int ldx21,\n                                lapack_complex_float* x22, lapack_int ldx22,\n                                float* theta, float* phi,\n                                lapack_complex_float* taup1,\n                                lapack_complex_float* taup2,\n                                lapack_complex_float* tauq1,\n                                lapack_complex_float* tauq2,\n                                lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_cuncsd( int matrix_order, char jobu1, char jobu2,\n                           char jobv1t, char jobv2t, char trans, char signs,\n                           lapack_int m, lapack_int p, lapack_int q,\n                           lapack_complex_float* x11, lapack_int ldx11,\n                           lapack_complex_float* x12, lapack_int ldx12,\n                           lapack_complex_float* x21, lapack_int ldx21,\n                           lapack_complex_float* x22, lapack_int ldx22,\n                           float* theta, lapack_complex_float* u1,\n                           lapack_int ldu1, lapack_complex_float* u2,\n                           lapack_int ldu2, lapack_complex_float* v1t,\n                           lapack_int ldv1t, lapack_complex_float* v2t,\n                           lapack_int ldv2t );\nlapack_int LAPACKE_cuncsd_work( int matrix_order, char jobu1, char jobu2,\n                                char jobv1t, char jobv2t, char trans,\n                                char signs, lapack_int m, lapack_int p,\n                                lapack_int q, lapack_complex_float* x11,\n                                lapack_int ldx11, lapack_complex_float* x12,\n                                lapack_int ldx12, lapack_complex_float* x21,\n                                lapack_int ldx21, lapack_complex_float* x22,\n                                lapack_int ldx22, float* theta,\n                                lapack_complex_float* u1, lapack_int ldu1,\n                                lapack_complex_float* u2, lapack_int ldu2,\n                                lapack_complex_float* v1t, lapack_int ldv1t,\n                                lapack_complex_float* v2t, lapack_int ldv2t,\n                                lapack_complex_float* work, lapack_int lwork,\n                                float* rwork, lapack_int lrwork,\n                                lapack_int* iwork );\nlapack_int LAPACKE_dbbcsd( int matrix_order, char jobu1, char jobu2,\n                           char jobv1t, char jobv2t, char trans, lapack_int m,\n                           lapack_int p, lapack_int q, double* theta,\n                           double* phi, double* u1, lapack_int ldu1, double* u2,\n                           lapack_int ldu2, double* v1t, lapack_int ldv1t,\n                           double* v2t, lapack_int ldv2t, double* b11d,\n                           double* b11e, double* b12d, double* b12e,\n                           double* b21d, double* b21e, double* b22d,\n                           double* b22e );\nlapack_int LAPACKE_dbbcsd_work( int matrix_order, char jobu1, char jobu2,\n                                char jobv1t, char jobv2t, char trans,\n                                lapack_int m, lapack_int p, lapack_int q,\n                                double* theta, double* phi, double* u1,\n                                lapack_int ldu1, double* u2, lapack_int ldu2,\n                                double* v1t, lapack_int ldv1t, double* v2t,\n                                lapack_int ldv2t, double* b11d, double* b11e,\n                                double* b12d, double* b12e, double* b21d,\n                                double* b21e, double* b22d, double* b22e,\n                                double* work, lapack_int lwork );\nlapack_int LAPACKE_dorbdb( int matrix_order, char trans, char signs,\n                           lapack_int m, lapack_int p, lapack_int q,\n                           double* x11, lapack_int ldx11, double* x12,\n                           lapack_int ldx12, double* x21, lapack_int ldx21,\n                           double* x22, lapack_int ldx22, double* theta,\n                           double* phi, double* taup1, double* taup2,\n                           double* tauq1, double* tauq2 );\nlapack_int LAPACKE_dorbdb_work( int matrix_order, char trans, char signs,\n                                lapack_int m, lapack_int p, lapack_int q,\n                                double* x11, lapack_int ldx11, double* x12,\n                                lapack_int ldx12, double* x21, lapack_int ldx21,\n                                double* x22, lapack_int ldx22, double* theta,\n                                double* phi, double* taup1, double* taup2,\n                                double* tauq1, double* tauq2, double* work,\n                                lapack_int lwork );\nlapack_int LAPACKE_dorcsd( int matrix_order, char jobu1, char jobu2,\n                           char jobv1t, char jobv2t, char trans, char signs,\n                           lapack_int m, lapack_int p, lapack_int q,\n                           double* x11, lapack_int ldx11, double* x12,\n                           lapack_int ldx12, double* x21, lapack_int ldx21,\n                           double* x22, lapack_int ldx22, double* theta,\n                           double* u1, lapack_int ldu1, double* u2,\n                           lapack_int ldu2, double* v1t, lapack_int ldv1t,\n                           double* v2t, lapack_int ldv2t );\nlapack_int LAPACKE_dorcsd_work( int matrix_order, char jobu1, char jobu2,\n                                char jobv1t, char jobv2t, char trans,\n                                char signs, lapack_int m, lapack_int p,\n                                lapack_int q, double* x11, lapack_int ldx11,\n                                double* x12, lapack_int ldx12, double* x21,\n                                lapack_int ldx21, double* x22, lapack_int ldx22,\n                                double* theta, double* u1, lapack_int ldu1,\n                                double* u2, lapack_int ldu2, double* v1t,\n                                lapack_int ldv1t, double* v2t, lapack_int ldv2t,\n                                double* work, lapack_int lwork,\n                                lapack_int* iwork );\nlapack_int LAPACKE_dsyconv( int matrix_order, char uplo, char way, lapack_int n,\n                            double* a, lapack_int lda, const lapack_int* ipiv );\nlapack_int LAPACKE_dsyconv_work( int matrix_order, char uplo, char way,\n                                 lapack_int n, double* a, lapack_int lda,\n                                 const lapack_int* ipiv, double* work );\nlapack_int LAPACKE_dsyswapr( int matrix_order, char uplo, lapack_int n,\n                             double* a, lapack_int i1, lapack_int i2 );\nlapack_int LAPACKE_dsyswapr_work( int matrix_order, char uplo, lapack_int n,\n                                  double* a, lapack_int i1, lapack_int i2 );\nlapack_int LAPACKE_dsytri2( int matrix_order, char uplo, lapack_int n,\n                            double* a, lapack_int lda, const lapack_int* ipiv );\nlapack_int LAPACKE_dsytri2_work( int matrix_order, char uplo, lapack_int n,\n                                 double* a, lapack_int lda,\n                                 const lapack_int* ipiv,\n                                 lapack_complex_double* work, lapack_int lwork );\nlapack_int LAPACKE_dsytri2x( int matrix_order, char uplo, lapack_int n,\n                             double* a, lapack_int lda, const lapack_int* ipiv,\n                             lapack_int nb );\nlapack_int LAPACKE_dsytri2x_work( int matrix_order, char uplo, lapack_int n,\n                                  double* a, lapack_int lda,\n                                  const lapack_int* ipiv, double* work,\n                                  lapack_int nb );\nlapack_int LAPACKE_dsytrs2( int matrix_order, char uplo, lapack_int n,\n                            lapack_int nrhs, const double* a, lapack_int lda,\n                            const lapack_int* ipiv, double* b, lapack_int ldb );\nlapack_int LAPACKE_dsytrs2_work( int matrix_order, char uplo, lapack_int n,\n                                 lapack_int nrhs, const double* a,\n                                 lapack_int lda, const lapack_int* ipiv,\n                                 double* b, lapack_int ldb, double* work );\nlapack_int LAPACKE_sbbcsd( int matrix_order, char jobu1, char jobu2,\n                           char jobv1t, char jobv2t, char trans, lapack_int m,\n                           lapack_int p, lapack_int q, float* theta, float* phi,\n                           float* u1, lapack_int ldu1, float* u2,\n                           lapack_int ldu2, float* v1t, lapack_int ldv1t,\n                           float* v2t, lapack_int ldv2t, float* b11d,\n                           float* b11e, float* b12d, float* b12e, float* b21d,\n                           float* b21e, float* b22d, float* b22e );\nlapack_int LAPACKE_sbbcsd_work( int matrix_order, char jobu1, char jobu2,\n                                char jobv1t, char jobv2t, char trans,\n                                lapack_int m, lapack_int p, lapack_int q,\n                                float* theta, float* phi, float* u1,\n                                lapack_int ldu1, float* u2, lapack_int ldu2,\n                                float* v1t, lapack_int ldv1t, float* v2t,\n                                lapack_int ldv2t, float* b11d, float* b11e,\n                                float* b12d, float* b12e, float* b21d,\n                                float* b21e, float* b22d, float* b22e,\n                                float* work, lapack_int lwork );\nlapack_int LAPACKE_sorbdb( int matrix_order, char trans, char signs,\n                           lapack_int m, lapack_int p, lapack_int q, float* x11,\n                           lapack_int ldx11, float* x12, lapack_int ldx12,\n                           float* x21, lapack_int ldx21, float* x22,\n                           lapack_int ldx22, float* theta, float* phi,\n                           float* taup1, float* taup2, float* tauq1,\n                           float* tauq2 );\nlapack_int LAPACKE_sorbdb_work( int matrix_order, char trans, char signs,\n                                lapack_int m, lapack_int p, lapack_int q,\n                                float* x11, lapack_int ldx11, float* x12,\n                                lapack_int ldx12, float* x21, lapack_int ldx21,\n                                float* x22, lapack_int ldx22, float* theta,\n                                float* phi, float* taup1, float* taup2,\n                                float* tauq1, float* tauq2, float* work,\n                                lapack_int lwork );\nlapack_int LAPACKE_sorcsd( int matrix_order, char jobu1, char jobu2,\n                           char jobv1t, char jobv2t, char trans, char signs,\n                           lapack_int m, lapack_int p, lapack_int q, float* x11,\n                           lapack_int ldx11, float* x12, lapack_int ldx12,\n                           float* x21, lapack_int ldx21, float* x22,\n                           lapack_int ldx22, float* theta, float* u1,\n                           lapack_int ldu1, float* u2, lapack_int ldu2,\n                           float* v1t, lapack_int ldv1t, float* v2t,\n                           lapack_int ldv2t );\nlapack_int LAPACKE_sorcsd_work( int matrix_order, char jobu1, char jobu2,\n                                char jobv1t, char jobv2t, char trans,\n                                char signs, lapack_int m, lapack_int p,\n                                lapack_int q, float* x11, lapack_int ldx11,\n                                float* x12, lapack_int ldx12, float* x21,\n                                lapack_int ldx21, float* x22, lapack_int ldx22,\n                                float* theta, float* u1, lapack_int ldu1,\n                                float* u2, lapack_int ldu2, float* v1t,\n                                lapack_int ldv1t, float* v2t, lapack_int ldv2t,\n                                float* work, lapack_int lwork,\n                                lapack_int* iwork );\nlapack_int LAPACKE_ssyconv( int matrix_order, char uplo, char way, lapack_int n,\n                            float* a, lapack_int lda, const lapack_int* ipiv );\nlapack_int LAPACKE_ssyconv_work( int matrix_order, char uplo, char way,\n                                 lapack_int n, float* a, lapack_int lda,\n                                 const lapack_int* ipiv, float* work );\nlapack_int LAPACKE_ssyswapr( int matrix_order, char uplo, lapack_int n,\n                             float* a, lapack_int i1, lapack_int i2 );\nlapack_int LAPACKE_ssyswapr_work( int matrix_order, char uplo, lapack_int n,\n                                  float* a, lapack_int i1, lapack_int i2 );\nlapack_int LAPACKE_ssytri2( int matrix_order, char uplo, lapack_int n, float* a,\n                            lapack_int lda, const lapack_int* ipiv );\nlapack_int LAPACKE_ssytri2_work( int matrix_order, char uplo, lapack_int n,\n                                 float* a, lapack_int lda,\n                                 const lapack_int* ipiv,\n                                 lapack_complex_float* work, lapack_int lwork );\nlapack_int LAPACKE_ssytri2x( int matrix_order, char uplo, lapack_int n,\n                             float* a, lapack_int lda, const lapack_int* ipiv,\n                             lapack_int nb );\nlapack_int LAPACKE_ssytri2x_work( int matrix_order, char uplo, lapack_int n,\n                                  float* a, lapack_int lda,\n                                  const lapack_int* ipiv, float* work,\n                                  lapack_int nb );\nlapack_int LAPACKE_ssytrs2( int matrix_order, char uplo, lapack_int n,\n                            lapack_int nrhs, const float* a, lapack_int lda,\n                            const lapack_int* ipiv, float* b, lapack_int ldb );\nlapack_int LAPACKE_ssytrs2_work( int matrix_order, char uplo, lapack_int n,\n                                 lapack_int nrhs, const float* a,\n                                 lapack_int lda, const lapack_int* ipiv,\n                                 float* b, lapack_int ldb, float* work );\nlapack_int LAPACKE_zbbcsd( int matrix_order, char jobu1, char jobu2,\n                           char jobv1t, char jobv2t, char trans, lapack_int m,\n                           lapack_int p, lapack_int q, double* theta,\n                           double* phi, lapack_complex_double* u1,\n                           lapack_int ldu1, lapack_complex_double* u2,\n                           lapack_int ldu2, lapack_complex_double* v1t,\n                           lapack_int ldv1t, lapack_complex_double* v2t,\n                           lapack_int ldv2t, double* b11d, double* b11e,\n                           double* b12d, double* b12e, double* b21d,\n                           double* b21e, double* b22d, double* b22e );\nlapack_int LAPACKE_zbbcsd_work( int matrix_order, char jobu1, char jobu2,\n                                char jobv1t, char jobv2t, char trans,\n                                lapack_int m, lapack_int p, lapack_int q,\n                                double* theta, double* phi,\n                                lapack_complex_double* u1, lapack_int ldu1,\n                                lapack_complex_double* u2, lapack_int ldu2,\n                                lapack_complex_double* v1t, lapack_int ldv1t,\n                                lapack_complex_double* v2t, lapack_int ldv2t,\n                                double* b11d, double* b11e, double* b12d,\n                                double* b12e, double* b21d, double* b21e,\n                                double* b22d, double* b22e, double* rwork,\n                                lapack_int lrwork );\nlapack_int LAPACKE_zheswapr( int matrix_order, char uplo, lapack_int n,\n                             lapack_complex_double* a, lapack_int i1,\n                             lapack_int i2 );\nlapack_int LAPACKE_zheswapr_work( int matrix_order, char uplo, lapack_int n,\n                                  lapack_complex_double* a, lapack_int i1,\n                                  lapack_int i2 );\nlapack_int LAPACKE_zhetri2( int matrix_order, char uplo, lapack_int n,\n                            lapack_complex_double* a, lapack_int lda,\n                            const lapack_int* ipiv );\nlapack_int LAPACKE_zhetri2_work( int matrix_order, char uplo, lapack_int n,\n                                 lapack_complex_double* a, lapack_int lda,\n                                 const lapack_int* ipiv,\n                                 lapack_complex_double* work, lapack_int lwork );\nlapack_int LAPACKE_zhetri2x( int matrix_order, char uplo, lapack_int n,\n                             lapack_complex_double* a, lapack_int lda,\n                             const lapack_int* ipiv, lapack_int nb );\nlapack_int LAPACKE_zhetri2x_work( int matrix_order, char uplo, lapack_int n,\n                                  lapack_complex_double* a, lapack_int lda,\n                                  const lapack_int* ipiv,\n                                  lapack_complex_double* work, lapack_int nb );\nlapack_int LAPACKE_zhetrs2( int matrix_order, char uplo, lapack_int n,\n                            lapack_int nrhs, const lapack_complex_double* a,\n                            lapack_int lda, const lapack_int* ipiv,\n                            lapack_complex_double* b, lapack_int ldb );\nlapack_int LAPACKE_zhetrs2_work( int matrix_order, char uplo, lapack_int n,\n                                 lapack_int nrhs, const lapack_complex_double* a,\n                                 lapack_int lda, const lapack_int* ipiv,\n                                 lapack_complex_double* b, lapack_int ldb,\n                                 lapack_complex_double* work );\nlapack_int LAPACKE_zsyconv( int matrix_order, char uplo, char way, lapack_int n,\n                            lapack_complex_double* a, lapack_int lda,\n                            const lapack_int* ipiv );\nlapack_int LAPACKE_zsyconv_work( int matrix_order, char uplo, char way,\n                                 lapack_int n, lapack_complex_double* a,\n                                 lapack_int lda, const lapack_int* ipiv,\n                                 lapack_complex_double* work );\nlapack_int LAPACKE_zsyswapr( int matrix_order, char uplo, lapack_int n,\n                             lapack_complex_double* a, lapack_int i1,\n                             lapack_int i2 );\nlapack_int LAPACKE_zsyswapr_work( int matrix_order, char uplo, lapack_int n,\n                                  lapack_complex_double* a, lapack_int i1,\n                                  lapack_int i2 );\nlapack_int LAPACKE_zsytri2( int matrix_order, char uplo, lapack_int n,\n                            lapack_complex_double* a, lapack_int lda,\n                            const lapack_int* ipiv );\nlapack_int LAPACKE_zsytri2_work( int matrix_order, char uplo, lapack_int n,\n                                 lapack_complex_double* a, lapack_int lda,\n                                 const lapack_int* ipiv,\n                                 lapack_complex_double* work, lapack_int lwork );\nlapack_int LAPACKE_zsytri2x( int matrix_order, char uplo, lapack_int n,\n                             lapack_complex_double* a, lapack_int lda,\n                             const lapack_int* ipiv, lapack_int nb );\nlapack_int LAPACKE_zsytri2x_work( int matrix_order, char uplo, lapack_int n,\n                                  lapack_complex_double* a, lapack_int lda,\n                                  const lapack_int* ipiv,\n                                  lapack_complex_double* work, lapack_int nb );\nlapack_int LAPACKE_zsytrs2( int matrix_order, char uplo, lapack_int n,\n                            lapack_int nrhs, const lapack_complex_double* a,\n                            lapack_int lda, const lapack_int* ipiv,\n                            lapack_complex_double* b, lapack_int ldb );\nlapack_int LAPACKE_zsytrs2_work( int matrix_order, char uplo, lapack_int n,\n                                 lapack_int nrhs, const lapack_complex_double* a,\n                                 lapack_int lda, const lapack_int* ipiv,\n                                 lapack_complex_double* b, lapack_int ldb,\n                                 lapack_complex_double* work );\nlapack_int LAPACKE_zunbdb( int matrix_order, char trans, char signs,\n                           lapack_int m, lapack_int p, lapack_int q,\n                           lapack_complex_double* x11, lapack_int ldx11,\n                           lapack_complex_double* x12, lapack_int ldx12,\n                           lapack_complex_double* x21, lapack_int ldx21,\n                           lapack_complex_double* x22, lapack_int ldx22,\n                           double* theta, double* phi,\n                           lapack_complex_double* taup1,\n                           lapack_complex_double* taup2,\n                           lapack_complex_double* tauq1,\n                           lapack_complex_double* tauq2 );\nlapack_int LAPACKE_zunbdb_work( int matrix_order, char trans, char signs,\n                                lapack_int m, lapack_int p, lapack_int q,\n                                lapack_complex_double* x11, lapack_int ldx11,\n                                lapack_complex_double* x12, lapack_int ldx12,\n                                lapack_complex_double* x21, lapack_int ldx21,\n                                lapack_complex_double* x22, lapack_int ldx22,\n                                double* theta, double* phi,\n                                lapack_complex_double* taup1,\n                                lapack_complex_double* taup2,\n                                lapack_complex_double* tauq1,\n                                lapack_complex_double* tauq2,\n                                lapack_complex_double* work, lapack_int lwork );\nlapack_int LAPACKE_zuncsd( int matrix_order, char jobu1, char jobu2,\n                           char jobv1t, char jobv2t, char trans, char signs,\n                           lapack_int m, lapack_int p, lapack_int q,\n                           lapack_complex_double* x11, lapack_int ldx11,\n                           lapack_complex_double* x12, lapack_int ldx12,\n                           lapack_complex_double* x21, lapack_int ldx21,\n                           lapack_complex_double* x22, lapack_int ldx22,\n                           double* theta, lapack_complex_double* u1,\n                           lapack_int ldu1, lapack_complex_double* u2,\n                           lapack_int ldu2, lapack_complex_double* v1t,\n                           lapack_int ldv1t, lapack_complex_double* v2t,\n                           lapack_int ldv2t );\nlapack_int LAPACKE_zuncsd_work( int matrix_order, char jobu1, char jobu2,\n                                char jobv1t, char jobv2t, char trans,\n                                char signs, lapack_int m, lapack_int p,\n                                lapack_int q, lapack_complex_double* x11,\n                                lapack_int ldx11, lapack_complex_double* x12,\n                                lapack_int ldx12, lapack_complex_double* x21,\n                                lapack_int ldx21, lapack_complex_double* x22,\n                                lapack_int ldx22, double* theta,\n                                lapack_complex_double* u1, lapack_int ldu1,\n                                lapack_complex_double* u2, lapack_int ldu2,\n                                lapack_complex_double* v1t, lapack_int ldv1t,\n                                lapack_complex_double* v2t, lapack_int ldv2t,\n                                lapack_complex_double* work, lapack_int lwork,\n                                double* rwork, lapack_int lrwork,\n                                lapack_int* iwork );\n//LAPACK 3.4.0\nlapack_int LAPACKE_sgemqrt( int matrix_order, char side, char trans,\n                            lapack_int m, lapack_int n, lapack_int k,\n                            lapack_int nb, const float* v, lapack_int ldv,\n                            const float* t, lapack_int ldt, float* c,\n                            lapack_int ldc );\nlapack_int LAPACKE_dgemqrt( int matrix_order, char side, char trans,\n                            lapack_int m, lapack_int n, lapack_int k,\n                            lapack_int nb, const double* v, lapack_int ldv,\n                            const double* t, lapack_int ldt, double* c,\n                            lapack_int ldc );\nlapack_int LAPACKE_cgemqrt( int matrix_order, char side, char trans,\n                            lapack_int m, lapack_int n, lapack_int k,\n                            lapack_int nb, const lapack_complex_float* v,\n                            lapack_int ldv, const lapack_complex_float* t,\n                            lapack_int ldt, lapack_complex_float* c,\n                            lapack_int ldc );\nlapack_int LAPACKE_zgemqrt( int matrix_order, char side, char trans,\n                            lapack_int m, lapack_int n, lapack_int k,\n                            lapack_int nb, const lapack_complex_double* v,\n                            lapack_int ldv, const lapack_complex_double* t,\n                            lapack_int ldt, lapack_complex_double* c,\n                            lapack_int ldc );\n\nlapack_int LAPACKE_sgeqrt( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int nb, float* a, lapack_int lda, float* t,\n                           lapack_int ldt );\nlapack_int LAPACKE_dgeqrt( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int nb, double* a, lapack_int lda, double* t,\n                           lapack_int ldt );\nlapack_int LAPACKE_cgeqrt( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int nb, lapack_complex_float* a,\n                           lapack_int lda, lapack_complex_float* t,\n                           lapack_int ldt );\nlapack_int LAPACKE_zgeqrt( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int nb, lapack_complex_double* a,\n                           lapack_int lda, lapack_complex_double* t,\n                           lapack_int ldt );\n\nlapack_int LAPACKE_sgeqrt2( int matrix_order, lapack_int m, lapack_int n,\n                            float* a, lapack_int lda, float* t,\n                            lapack_int ldt );\nlapack_int LAPACKE_dgeqrt2( int matrix_order, lapack_int m, lapack_int n,\n                            double* a, lapack_int lda, double* t,\n                            lapack_int ldt );\nlapack_int LAPACKE_cgeqrt2( int matrix_order, lapack_int m, lapack_int n,\n                            lapack_complex_float* a, lapack_int lda,\n                            lapack_complex_float* t, lapack_int ldt );\nlapack_int LAPACKE_zgeqrt2( int matrix_order, lapack_int m, lapack_int n,\n                            lapack_complex_double* a, lapack_int lda,\n                            lapack_complex_double* t, lapack_int ldt );\n\nlapack_int LAPACKE_sgeqrt3( int matrix_order, lapack_int m, lapack_int n,\n                            float* a, lapack_int lda, float* t,\n                            lapack_int ldt );\nlapack_int LAPACKE_dgeqrt3( int matrix_order, lapack_int m, lapack_int n,\n                            double* a, lapack_int lda, double* t,\n                            lapack_int ldt );\nlapack_int LAPACKE_cgeqrt3( int matrix_order, lapack_int m, lapack_int n,\n                            lapack_complex_float* a, lapack_int lda,\n                            lapack_complex_float* t, lapack_int ldt );\nlapack_int LAPACKE_zgeqrt3( int matrix_order, lapack_int m, lapack_int n,\n                            lapack_complex_double* a, lapack_int lda,\n                            lapack_complex_double* t, lapack_int ldt );\n\nlapack_int LAPACKE_stpmqrt( int matrix_order, char side, char trans,\n                            lapack_int m, lapack_int n, lapack_int k,\n                            lapack_int l, lapack_int nb, const float* v,\n                            lapack_int ldv, const float* t, lapack_int ldt,\n                            float* a, lapack_int lda, float* b,\n                            lapack_int ldb );\nlapack_int LAPACKE_dtpmqrt( int matrix_order, char side, char trans,\n                            lapack_int m, lapack_int n, lapack_int k,\n                            lapack_int l, lapack_int nb, const double* v,\n                            lapack_int ldv, const double* t, lapack_int ldt,\n                            double* a, lapack_int lda, double* b,\n                            lapack_int ldb );\nlapack_int LAPACKE_ctpmqrt( int matrix_order, char side, char trans,\n                            lapack_int m, lapack_int n, lapack_int k,\n                            lapack_int l, lapack_int nb,\n                            const lapack_complex_float* v, lapack_int ldv,\n                            const lapack_complex_float* t, lapack_int ldt,\n                            lapack_complex_float* a, lapack_int lda,\n                            lapack_complex_float* b, lapack_int ldb );\nlapack_int LAPACKE_ztpmqrt( int matrix_order, char side, char trans,\n                            lapack_int m, lapack_int n, lapack_int k,\n                            lapack_int l, lapack_int nb,\n                            const lapack_complex_double* v, lapack_int ldv,\n                            const lapack_complex_double* t, lapack_int ldt,\n                            lapack_complex_double* a, lapack_int lda,\n                            lapack_complex_double* b, lapack_int ldb );\n\nlapack_int LAPACKE_dtpqrt( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int l, lapack_int nb, double* a,\n                           lapack_int lda, double* b, lapack_int ldb, double* t,\n                           lapack_int ldt );\nlapack_int LAPACKE_ctpqrt( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int l, lapack_int nb, lapack_complex_float* a,\n                           lapack_int lda, lapack_complex_float* t,\n                           lapack_complex_float* b, lapack_int ldb,\n                           lapack_int ldt );\nlapack_int LAPACKE_ztpqrt( int matrix_order, lapack_int m, lapack_int n,\n                           lapack_int l, lapack_int nb,\n                           lapack_complex_double* a, lapack_int lda,\n                           lapack_complex_double* b, lapack_int ldb,\n                           lapack_complex_double* t, lapack_int ldt );\n\nlapack_int LAPACKE_stpqrt2( int matrix_order, lapack_int m, lapack_int n,\n                            float* a, lapack_int lda, float* b, lapack_int ldb,\n                            float* t, lapack_int ldt );\nlapack_int LAPACKE_dtpqrt2( int matrix_order, lapack_int m, lapack_int n,\n                            double* a, lapack_int lda, double* b,\n                            lapack_int ldb, double* t, lapack_int ldt );\nlapack_int LAPACKE_ctpqrt2( int matrix_order, lapack_int m, lapack_int n,\n                            lapack_complex_float* a, lapack_int lda,\n                            lapack_complex_float* b, lapack_int ldb,\n                            lapack_complex_float* t, lapack_int ldt );\nlapack_int LAPACKE_ztpqrt2( int matrix_order, lapack_int m, lapack_int n,\n                            lapack_complex_double* a, lapack_int lda,\n                            lapack_complex_double* b, lapack_int ldb,\n                            lapack_complex_double* t, lapack_int ldt );\n\nlapack_int LAPACKE_stprfb( int matrix_order, char side, char trans, char direct,\n                           char storev, lapack_int m, lapack_int n,\n                           lapack_int k, lapack_int l, const float* v,\n                           lapack_int ldv, const float* t, lapack_int ldt,\n                           float* a, lapack_int lda, float* b, lapack_int ldb,\n                           lapack_int myldwork );\nlapack_int LAPACKE_dtprfb( int matrix_order, char side, char trans, char direct,\n                           char storev, lapack_int m, lapack_int n,\n                           lapack_int k, lapack_int l, const double* v,\n                           lapack_int ldv, const double* t, lapack_int ldt,\n                           double* a, lapack_int lda, double* b, lapack_int ldb,\n                           lapack_int myldwork );\nlapack_int LAPACKE_ctprfb( int matrix_order, char side, char trans, char direct,\n                           char storev, lapack_int m, lapack_int n,\n                           lapack_int k, lapack_int l,\n                           const lapack_complex_float* v, lapack_int ldv,\n                           const lapack_complex_float* t, lapack_int ldt,\n                           lapack_complex_float* a, lapack_int lda,\n                           lapack_complex_float* b, lapack_int ldb,\n                           lapack_int myldwork );\nlapack_int LAPACKE_ztprfb( int matrix_order, char side, char trans, char direct,\n                           char storev, lapack_int m, lapack_int n,\n                           lapack_int k, lapack_int l,\n                           const lapack_complex_double* v, lapack_int ldv,\n                           const lapack_complex_double* t, lapack_int ldt,\n                           lapack_complex_double* a, lapack_int lda,\n                           lapack_complex_double* b, lapack_int ldb,\n                           lapack_int myldwork );\n\nlapack_int LAPACKE_sgemqrt_work( int matrix_order, char side, char trans,\n                                 lapack_int m, lapack_int n, lapack_int k,\n                                 lapack_int nb, const float* v, lapack_int ldv,\n                                 const float* t, lapack_int ldt, float* c,\n                                 lapack_int ldc, float* work );\nlapack_int LAPACKE_dgemqrt_work( int matrix_order, char side, char trans,\n                                 lapack_int m, lapack_int n, lapack_int k,\n                                 lapack_int nb, const double* v, lapack_int ldv,\n                                 const double* t, lapack_int ldt, double* c,\n                                 lapack_int ldc, double* work );\nlapack_int LAPACKE_cgemqrt_work( int matrix_order, char side, char trans,\n                                 lapack_int m, lapack_int n, lapack_int k,\n                                 lapack_int nb, const lapack_complex_float* v,\n                                 lapack_int ldv, const lapack_complex_float* t,\n                                 lapack_int ldt, lapack_complex_float* c,\n                                 lapack_int ldc, lapack_complex_float* work );\nlapack_int LAPACKE_zgemqrt_work( int matrix_order, char side, char trans,\n                                 lapack_int m, lapack_int n, lapack_int k,\n                                 lapack_int nb, const lapack_complex_double* v,\n                                 lapack_int ldv, const lapack_complex_double* t,\n                                 lapack_int ldt, lapack_complex_double* c,\n                                 lapack_int ldc, lapack_complex_double* work );\n\nlapack_int LAPACKE_sgeqrt_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int nb, float* a, lapack_int lda,\n                                float* t, lapack_int ldt, float* work );\nlapack_int LAPACKE_dgeqrt_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int nb, double* a, lapack_int lda,\n                                double* t, lapack_int ldt, double* work );\nlapack_int LAPACKE_cgeqrt_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int nb, lapack_complex_float* a,\n                                lapack_int lda, lapack_complex_float* t,\n                                lapack_int ldt, lapack_complex_float* work );\nlapack_int LAPACKE_zgeqrt_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int nb, lapack_complex_double* a,\n                                lapack_int lda, lapack_complex_double* t,\n                                lapack_int ldt, lapack_complex_double* work );\n\nlapack_int LAPACKE_sgeqrt2_work( int matrix_order, lapack_int m, lapack_int n,\n                                 float* a, lapack_int lda, float* t,\n                                 lapack_int ldt );\nlapack_int LAPACKE_dgeqrt2_work( int matrix_order, lapack_int m, lapack_int n,\n                                 double* a, lapack_int lda, double* t,\n                                 lapack_int ldt );\nlapack_int LAPACKE_cgeqrt2_work( int matrix_order, lapack_int m, lapack_int n,\n                                 lapack_complex_float* a, lapack_int lda,\n                                 lapack_complex_float* t, lapack_int ldt );\nlapack_int LAPACKE_zgeqrt2_work( int matrix_order, lapack_int m, lapack_int n,\n                                 lapack_complex_double* a, lapack_int lda,\n                                 lapack_complex_double* t, lapack_int ldt );\n\nlapack_int LAPACKE_sgeqrt3_work( int matrix_order, lapack_int m, lapack_int n,\n                                 float* a, lapack_int lda, float* t,\n                                 lapack_int ldt );\nlapack_int LAPACKE_dgeqrt3_work( int matrix_order, lapack_int m, lapack_int n,\n                                 double* a, lapack_int lda, double* t,\n                                 lapack_int ldt );\nlapack_int LAPACKE_cgeqrt3_work( int matrix_order, lapack_int m, lapack_int n,\n                                 lapack_complex_float* a, lapack_int lda,\n                                 lapack_complex_float* t, lapack_int ldt );\nlapack_int LAPACKE_zgeqrt3_work( int matrix_order, lapack_int m, lapack_int n,\n                                 lapack_complex_double* a, lapack_int lda,\n                                 lapack_complex_double* t, lapack_int ldt );\n\nlapack_int LAPACKE_stpmqrt_work( int matrix_order, char side, char trans,\n                                 lapack_int m, lapack_int n, lapack_int k,\n                                 lapack_int l, lapack_int nb, const float* v,\n                                 lapack_int ldv, const float* t, lapack_int ldt,\n                                 float* a, lapack_int lda, float* b,\n                                 lapack_int ldb, float* work );\nlapack_int LAPACKE_dtpmqrt_work( int matrix_order, char side, char trans,\n                                 lapack_int m, lapack_int n, lapack_int k,\n                                 lapack_int l, lapack_int nb, const double* v,\n                                 lapack_int ldv, const double* t,\n                                 lapack_int ldt, double* a, lapack_int lda,\n                                 double* b, lapack_int ldb, double* work );\nlapack_int LAPACKE_ctpmqrt_work( int matrix_order, char side, char trans,\n                                 lapack_int m, lapack_int n, lapack_int k,\n                                 lapack_int l, lapack_int nb,\n                                 const lapack_complex_float* v, lapack_int ldv,\n                                 const lapack_complex_float* t, lapack_int ldt,\n                                 lapack_complex_float* a, lapack_int lda,\n                                 lapack_complex_float* b, lapack_int ldb,\n                                 lapack_complex_float* work );\nlapack_int LAPACKE_ztpmqrt_work( int matrix_order, char side, char trans,\n                                 lapack_int m, lapack_int n, lapack_int k,\n                                 lapack_int l, lapack_int nb,\n                                 const lapack_complex_double* v, lapack_int ldv,\n                                 const lapack_complex_double* t, lapack_int ldt,\n                                 lapack_complex_double* a, lapack_int lda,\n                                 lapack_complex_double* b, lapack_int ldb,\n                                 lapack_complex_double* work );\n\nlapack_int LAPACKE_dtpqrt_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int l, lapack_int nb, double* a,\n                                lapack_int lda, double* b, lapack_int ldb,\n                                double* t, lapack_int ldt, double* work );\nlapack_int LAPACKE_ctpqrt_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int l, lapack_int nb,\n                                lapack_complex_float* a, lapack_int lda,\n                                lapack_complex_float* t,\n                                lapack_complex_float* b, lapack_int ldb,\n                                lapack_int ldt, lapack_complex_float* work );\nlapack_int LAPACKE_ztpqrt_work( int matrix_order, lapack_int m, lapack_int n,\n                                lapack_int l, lapack_int nb,\n                                lapack_complex_double* a, lapack_int lda,\n                                lapack_complex_double* b, lapack_int ldb,\n                                lapack_complex_double* t, lapack_int ldt,\n                                lapack_complex_double* work );\n\nlapack_int LAPACKE_stpqrt2_work( int matrix_order, lapack_int m, lapack_int n,\n                                 float* a, lapack_int lda, float* b,\n                                 lapack_int ldb, float* t, lapack_int ldt );\nlapack_int LAPACKE_dtpqrt2_work( int matrix_order, lapack_int m, lapack_int n,\n                                 double* a, lapack_int lda, double* b,\n                                 lapack_int ldb, double* t, lapack_int ldt );\nlapack_int LAPACKE_ctpqrt2_work( int matrix_order, lapack_int m, lapack_int n,\n                                 lapack_complex_float* a, lapack_int lda,\n                                 lapack_complex_float* b, lapack_int ldb,\n                                 lapack_complex_float* t, lapack_int ldt );\nlapack_int LAPACKE_ztpqrt2_work( int matrix_order, lapack_int m, lapack_int n,\n                                 lapack_complex_double* a, lapack_int lda,\n                                 lapack_complex_double* b, lapack_int ldb,\n                                 lapack_complex_double* t, lapack_int ldt );\n\nlapack_int LAPACKE_stprfb_work( int matrix_order, char side, char trans,\n                                char direct, char storev, lapack_int m,\n                                lapack_int n, lapack_int k, lapack_int l,\n                                const float* v, lapack_int ldv, const float* t,\n                                lapack_int ldt, float* a, lapack_int lda,\n                                float* b, lapack_int ldb, const float* mywork,\n                                lapack_int myldwork );\nlapack_int LAPACKE_dtprfb_work( int matrix_order, char side, char trans,\n                                char direct, char storev, lapack_int m,\n                                lapack_int n, lapack_int k, lapack_int l,\n                                const double* v, lapack_int ldv,\n                                const double* t, lapack_int ldt, double* a,\n                                lapack_int lda, double* b, lapack_int ldb,\n                                const double* mywork, lapack_int myldwork );\nlapack_int LAPACKE_ctprfb_work( int matrix_order, char side, char trans,\n                                char direct, char storev, lapack_int m,\n                                lapack_int n, lapack_int k, lapack_int l,\n                                const lapack_complex_float* v, lapack_int ldv,\n                                const lapack_complex_float* t, lapack_int ldt,\n                                lapack_complex_float* a, lapack_int lda,\n                                lapack_complex_float* b, lapack_int ldb,\n                                const float* mywork, lapack_int myldwork );\nlapack_int LAPACKE_ztprfb_work( int matrix_order, char side, char trans,\n                                char direct, char storev, lapack_int m,\n                                lapack_int n, lapack_int k, lapack_int l,\n                                const lapack_complex_double* v, lapack_int ldv,\n                                const lapack_complex_double* t, lapack_int ldt,\n                                lapack_complex_double* a, lapack_int lda,\n                                lapack_complex_double* b, lapack_int ldb,\n                                const double* mywork, lapack_int myldwork );\n//LAPACK 3.X.X\nlapack_int LAPACKE_csyr( int matrix_order, char uplo, lapack_int n,\n                             lapack_complex_float alpha,\n                             const lapack_complex_float* x, lapack_int incx,\n                             lapack_complex_float* a, lapack_int lda );\nlapack_int LAPACKE_zsyr( int matrix_order, char uplo, lapack_int n,\n                             lapack_complex_double alpha,\n                             const lapack_complex_double* x, lapack_int incx,\n                             lapack_complex_double* a, lapack_int lda );\n\nlapack_int LAPACKE_csyr_work( int matrix_order, char uplo, lapack_int n,\n                                  lapack_complex_float alpha,\n                                  const lapack_complex_float* x,\n                                  lapack_int incx, lapack_complex_float* a,\n                                  lapack_int lda );\nlapack_int LAPACKE_zsyr_work( int matrix_order, char uplo, lapack_int n,\n                                  lapack_complex_double alpha,\n                                  const lapack_complex_double* x,\n                                  lapack_int incx, lapack_complex_double* a,\n                                  lapack_int lda );\n\n\n\n#define LAPACK_sgetrf LAPACK_GLOBAL(sgetrf,SGETRF)\n#define LAPACK_dgetrf LAPACK_GLOBAL(dgetrf,DGETRF)\n#define LAPACK_cgetrf LAPACK_GLOBAL(cgetrf,CGETRF)\n#define LAPACK_zgetrf LAPACK_GLOBAL(zgetrf,ZGETRF)\n#define LAPACK_sgbtrf LAPACK_GLOBAL(sgbtrf,SGBTRF)\n#define LAPACK_dgbtrf LAPACK_GLOBAL(dgbtrf,DGBTRF)\n#define LAPACK_cgbtrf LAPACK_GLOBAL(cgbtrf,CGBTRF)\n#define LAPACK_zgbtrf LAPACK_GLOBAL(zgbtrf,ZGBTRF)\n#define LAPACK_sgttrf LAPACK_GLOBAL(sgttrf,SGTTRF)\n#define LAPACK_dgttrf LAPACK_GLOBAL(dgttrf,DGTTRF)\n#define LAPACK_cgttrf LAPACK_GLOBAL(cgttrf,CGTTRF)\n#define LAPACK_zgttrf LAPACK_GLOBAL(zgttrf,ZGTTRF)\n#define LAPACK_spotrf LAPACK_GLOBAL(spotrf,SPOTRF)\n#define LAPACK_dpotrf LAPACK_GLOBAL(dpotrf,DPOTRF)\n#define LAPACK_cpotrf LAPACK_GLOBAL(cpotrf,CPOTRF)\n#define LAPACK_zpotrf LAPACK_GLOBAL(zpotrf,ZPOTRF)\n#define LAPACK_dpstrf LAPACK_GLOBAL(dpstrf,DPSTRF)\n#define LAPACK_spstrf LAPACK_GLOBAL(spstrf,SPSTRF)\n#define LAPACK_zpstrf LAPACK_GLOBAL(zpstrf,ZPSTRF)\n#define LAPACK_cpstrf LAPACK_GLOBAL(cpstrf,CPSTRF)\n#define LAPACK_dpftrf LAPACK_GLOBAL(dpftrf,DPFTRF)\n#define LAPACK_spftrf LAPACK_GLOBAL(spftrf,SPFTRF)\n#define LAPACK_zpftrf LAPACK_GLOBAL(zpftrf,ZPFTRF)\n#define LAPACK_cpftrf LAPACK_GLOBAL(cpftrf,CPFTRF)\n#define LAPACK_spptrf LAPACK_GLOBAL(spptrf,SPPTRF)\n#define LAPACK_dpptrf LAPACK_GLOBAL(dpptrf,DPPTRF)\n#define LAPACK_cpptrf LAPACK_GLOBAL(cpptrf,CPPTRF)\n#define LAPACK_zpptrf LAPACK_GLOBAL(zpptrf,ZPPTRF)\n#define LAPACK_spbtrf LAPACK_GLOBAL(spbtrf,SPBTRF)\n#define LAPACK_dpbtrf LAPACK_GLOBAL(dpbtrf,DPBTRF)\n#define LAPACK_cpbtrf LAPACK_GLOBAL(cpbtrf,CPBTRF)\n#define LAPACK_zpbtrf LAPACK_GLOBAL(zpbtrf,ZPBTRF)\n#define LAPACK_spttrf LAPACK_GLOBAL(spttrf,SPTTRF)\n#define LAPACK_dpttrf LAPACK_GLOBAL(dpttrf,DPTTRF)\n#define LAPACK_cpttrf LAPACK_GLOBAL(cpttrf,CPTTRF)\n#define LAPACK_zpttrf LAPACK_GLOBAL(zpttrf,ZPTTRF)\n#define LAPACK_ssytrf LAPACK_GLOBAL(ssytrf,SSYTRF)\n#define LAPACK_dsytrf LAPACK_GLOBAL(dsytrf,DSYTRF)\n#define LAPACK_csytrf LAPACK_GLOBAL(csytrf,CSYTRF)\n#define LAPACK_zsytrf LAPACK_GLOBAL(zsytrf,ZSYTRF)\n#define LAPACK_chetrf LAPACK_GLOBAL(chetrf,CHETRF)\n#define LAPACK_zhetrf LAPACK_GLOBAL(zhetrf,ZHETRF)\n#define LAPACK_ssptrf LAPACK_GLOBAL(ssptrf,SSPTRF)\n#define LAPACK_dsptrf LAPACK_GLOBAL(dsptrf,DSPTRF)\n#define LAPACK_csptrf LAPACK_GLOBAL(csptrf,CSPTRF)\n#define LAPACK_zsptrf LAPACK_GLOBAL(zsptrf,ZSPTRF)\n#define LAPACK_chptrf LAPACK_GLOBAL(chptrf,CHPTRF)\n#define LAPACK_zhptrf LAPACK_GLOBAL(zhptrf,ZHPTRF)\n#define LAPACK_sgetrs LAPACK_GLOBAL(sgetrs,SGETRS)\n#define LAPACK_dgetrs LAPACK_GLOBAL(dgetrs,DGETRS)\n#define LAPACK_cgetrs LAPACK_GLOBAL(cgetrs,CGETRS)\n#define LAPACK_zgetrs LAPACK_GLOBAL(zgetrs,ZGETRS)\n#define LAPACK_sgbtrs LAPACK_GLOBAL(sgbtrs,SGBTRS)\n#define LAPACK_dgbtrs LAPACK_GLOBAL(dgbtrs,DGBTRS)\n#define LAPACK_cgbtrs LAPACK_GLOBAL(cgbtrs,CGBTRS)\n#define LAPACK_zgbtrs LAPACK_GLOBAL(zgbtrs,ZGBTRS)\n#define LAPACK_sgttrs LAPACK_GLOBAL(sgttrs,SGTTRS)\n#define LAPACK_dgttrs LAPACK_GLOBAL(dgttrs,DGTTRS)\n#define LAPACK_cgttrs LAPACK_GLOBAL(cgttrs,CGTTRS)\n#define LAPACK_zgttrs LAPACK_GLOBAL(zgttrs,ZGTTRS)\n#define LAPACK_spotrs LAPACK_GLOBAL(spotrs,SPOTRS)\n#define LAPACK_dpotrs LAPACK_GLOBAL(dpotrs,DPOTRS)\n#define LAPACK_cpotrs LAPACK_GLOBAL(cpotrs,CPOTRS)\n#define LAPACK_zpotrs LAPACK_GLOBAL(zpotrs,ZPOTRS)\n#define LAPACK_dpftrs LAPACK_GLOBAL(dpftrs,DPFTRS)\n#define LAPACK_spftrs LAPACK_GLOBAL(spftrs,SPFTRS)\n#define LAPACK_zpftrs LAPACK_GLOBAL(zpftrs,ZPFTRS)\n#define LAPACK_cpftrs LAPACK_GLOBAL(cpftrs,CPFTRS)\n#define LAPACK_spptrs LAPACK_GLOBAL(spptrs,SPPTRS)\n#define LAPACK_dpptrs LAPACK_GLOBAL(dpptrs,DPPTRS)\n#define LAPACK_cpptrs LAPACK_GLOBAL(cpptrs,CPPTRS)\n#define LAPACK_zpptrs LAPACK_GLOBAL(zpptrs,ZPPTRS)\n#define LAPACK_spbtrs LAPACK_GLOBAL(spbtrs,SPBTRS)\n#define LAPACK_dpbtrs LAPACK_GLOBAL(dpbtrs,DPBTRS)\n#define LAPACK_cpbtrs LAPACK_GLOBAL(cpbtrs,CPBTRS)\n#define LAPACK_zpbtrs LAPACK_GLOBAL(zpbtrs,ZPBTRS)\n#define LAPACK_spttrs LAPACK_GLOBAL(spttrs,SPTTRS)\n#define LAPACK_dpttrs LAPACK_GLOBAL(dpttrs,DPTTRS)\n#define LAPACK_cpttrs LAPACK_GLOBAL(cpttrs,CPTTRS)\n#define LAPACK_zpttrs LAPACK_GLOBAL(zpttrs,ZPTTRS)\n#define LAPACK_ssytrs LAPACK_GLOBAL(ssytrs,SSYTRS)\n#define LAPACK_dsytrs LAPACK_GLOBAL(dsytrs,DSYTRS)\n#define LAPACK_csytrs LAPACK_GLOBAL(csytrs,CSYTRS)\n#define LAPACK_zsytrs LAPACK_GLOBAL(zsytrs,ZSYTRS)\n#define LAPACK_chetrs LAPACK_GLOBAL(chetrs,CHETRS)\n#define LAPACK_zhetrs LAPACK_GLOBAL(zhetrs,ZHETRS)\n#define LAPACK_ssptrs LAPACK_GLOBAL(ssptrs,SSPTRS)\n#define LAPACK_dsptrs LAPACK_GLOBAL(dsptrs,DSPTRS)\n#define LAPACK_csptrs LAPACK_GLOBAL(csptrs,CSPTRS)\n#define LAPACK_zsptrs LAPACK_GLOBAL(zsptrs,ZSPTRS)\n#define LAPACK_chptrs LAPACK_GLOBAL(chptrs,CHPTRS)\n#define LAPACK_zhptrs LAPACK_GLOBAL(zhptrs,ZHPTRS)\n#define LAPACK_strtrs LAPACK_GLOBAL(strtrs,STRTRS)\n#define LAPACK_dtrtrs LAPACK_GLOBAL(dtrtrs,DTRTRS)\n#define LAPACK_ctrtrs LAPACK_GLOBAL(ctrtrs,CTRTRS)\n#define LAPACK_ztrtrs LAPACK_GLOBAL(ztrtrs,ZTRTRS)\n#define LAPACK_stptrs LAPACK_GLOBAL(stptrs,STPTRS)\n#define LAPACK_dtptrs LAPACK_GLOBAL(dtptrs,DTPTRS)\n#define LAPACK_ctptrs LAPACK_GLOBAL(ctptrs,CTPTRS)\n#define LAPACK_ztptrs LAPACK_GLOBAL(ztptrs,ZTPTRS)\n#define LAPACK_stbtrs LAPACK_GLOBAL(stbtrs,STBTRS)\n#define LAPACK_dtbtrs LAPACK_GLOBAL(dtbtrs,DTBTRS)\n#define LAPACK_ctbtrs LAPACK_GLOBAL(ctbtrs,CTBTRS)\n#define LAPACK_ztbtrs LAPACK_GLOBAL(ztbtrs,ZTBTRS)\n#define LAPACK_sgecon LAPACK_GLOBAL(sgecon,SGECON)\n#define LAPACK_dgecon LAPACK_GLOBAL(dgecon,DGECON)\n#define LAPACK_cgecon LAPACK_GLOBAL(cgecon,CGECON)\n#define LAPACK_zgecon LAPACK_GLOBAL(zgecon,ZGECON)\n#define LAPACK_sgbcon LAPACK_GLOBAL(sgbcon,SGBCON)\n#define LAPACK_dgbcon LAPACK_GLOBAL(dgbcon,DGBCON)\n#define LAPACK_cgbcon LAPACK_GLOBAL(cgbcon,CGBCON)\n#define LAPACK_zgbcon LAPACK_GLOBAL(zgbcon,ZGBCON)\n#define LAPACK_sgtcon LAPACK_GLOBAL(sgtcon,SGTCON)\n#define LAPACK_dgtcon LAPACK_GLOBAL(dgtcon,DGTCON)\n#define LAPACK_cgtcon LAPACK_GLOBAL(cgtcon,CGTCON)\n#define LAPACK_zgtcon LAPACK_GLOBAL(zgtcon,ZGTCON)\n#define LAPACK_spocon LAPACK_GLOBAL(spocon,SPOCON)\n#define LAPACK_dpocon LAPACK_GLOBAL(dpocon,DPOCON)\n#define LAPACK_cpocon LAPACK_GLOBAL(cpocon,CPOCON)\n#define LAPACK_zpocon LAPACK_GLOBAL(zpocon,ZPOCON)\n#define LAPACK_sppcon LAPACK_GLOBAL(sppcon,SPPCON)\n#define LAPACK_dppcon LAPACK_GLOBAL(dppcon,DPPCON)\n#define LAPACK_cppcon LAPACK_GLOBAL(cppcon,CPPCON)\n#define LAPACK_zppcon LAPACK_GLOBAL(zppcon,ZPPCON)\n#define LAPACK_spbcon LAPACK_GLOBAL(spbcon,SPBCON)\n#define LAPACK_dpbcon LAPACK_GLOBAL(dpbcon,DPBCON)\n#define LAPACK_cpbcon LAPACK_GLOBAL(cpbcon,CPBCON)\n#define LAPACK_zpbcon LAPACK_GLOBAL(zpbcon,ZPBCON)\n#define LAPACK_sptcon LAPACK_GLOBAL(sptcon,SPTCON)\n#define LAPACK_dptcon LAPACK_GLOBAL(dptcon,DPTCON)\n#define LAPACK_cptcon LAPACK_GLOBAL(cptcon,CPTCON)\n#define LAPACK_zptcon LAPACK_GLOBAL(zptcon,ZPTCON)\n#define LAPACK_ssycon LAPACK_GLOBAL(ssycon,SSYCON)\n#define LAPACK_dsycon LAPACK_GLOBAL(dsycon,DSYCON)\n#define LAPACK_csycon LAPACK_GLOBAL(csycon,CSYCON)\n#define LAPACK_zsycon LAPACK_GLOBAL(zsycon,ZSYCON)\n#define LAPACK_checon LAPACK_GLOBAL(checon,CHECON)\n#define LAPACK_zhecon LAPACK_GLOBAL(zhecon,ZHECON)\n#define LAPACK_sspcon LAPACK_GLOBAL(sspcon,SSPCON)\n#define LAPACK_dspcon LAPACK_GLOBAL(dspcon,DSPCON)\n#define LAPACK_cspcon LAPACK_GLOBAL(cspcon,CSPCON)\n#define LAPACK_zspcon LAPACK_GLOBAL(zspcon,ZSPCON)\n#define LAPACK_chpcon LAPACK_GLOBAL(chpcon,CHPCON)\n#define LAPACK_zhpcon LAPACK_GLOBAL(zhpcon,ZHPCON)\n#define LAPACK_strcon LAPACK_GLOBAL(strcon,STRCON)\n#define LAPACK_dtrcon LAPACK_GLOBAL(dtrcon,DTRCON)\n#define LAPACK_ctrcon LAPACK_GLOBAL(ctrcon,CTRCON)\n#define LAPACK_ztrcon LAPACK_GLOBAL(ztrcon,ZTRCON)\n#define LAPACK_stpcon LAPACK_GLOBAL(stpcon,STPCON)\n#define LAPACK_dtpcon LAPACK_GLOBAL(dtpcon,DTPCON)\n#define LAPACK_ctpcon LAPACK_GLOBAL(ctpcon,CTPCON)\n#define LAPACK_ztpcon LAPACK_GLOBAL(ztpcon,ZTPCON)\n#define LAPACK_stbcon LAPACK_GLOBAL(stbcon,STBCON)\n#define LAPACK_dtbcon LAPACK_GLOBAL(dtbcon,DTBCON)\n#define LAPACK_ctbcon LAPACK_GLOBAL(ctbcon,CTBCON)\n#define LAPACK_ztbcon LAPACK_GLOBAL(ztbcon,ZTBCON)\n#define LAPACK_sgerfs LAPACK_GLOBAL(sgerfs,SGERFS)\n#define LAPACK_dgerfs LAPACK_GLOBAL(dgerfs,DGERFS)\n#define LAPACK_cgerfs LAPACK_GLOBAL(cgerfs,CGERFS)\n#define LAPACK_zgerfs LAPACK_GLOBAL(zgerfs,ZGERFS)\n#define LAPACK_dgerfsx LAPACK_GLOBAL(dgerfsx,DGERFSX)\n#define LAPACK_sgerfsx LAPACK_GLOBAL(sgerfsx,SGERFSX)\n#define LAPACK_zgerfsx LAPACK_GLOBAL(zgerfsx,ZGERFSX)\n#define LAPACK_cgerfsx LAPACK_GLOBAL(cgerfsx,CGERFSX)\n#define LAPACK_sgbrfs LAPACK_GLOBAL(sgbrfs,SGBRFS)\n#define LAPACK_dgbrfs LAPACK_GLOBAL(dgbrfs,DGBRFS)\n#define LAPACK_cgbrfs LAPACK_GLOBAL(cgbrfs,CGBRFS)\n#define LAPACK_zgbrfs LAPACK_GLOBAL(zgbrfs,ZGBRFS)\n#define LAPACK_dgbrfsx LAPACK_GLOBAL(dgbrfsx,DGBRFSX)\n#define LAPACK_sgbrfsx LAPACK_GLOBAL(sgbrfsx,SGBRFSX)\n#define LAPACK_zgbrfsx LAPACK_GLOBAL(zgbrfsx,ZGBRFSX)\n#define LAPACK_cgbrfsx LAPACK_GLOBAL(cgbrfsx,CGBRFSX)\n#define LAPACK_sgtrfs LAPACK_GLOBAL(sgtrfs,SGTRFS)\n#define LAPACK_dgtrfs LAPACK_GLOBAL(dgtrfs,DGTRFS)\n#define LAPACK_cgtrfs LAPACK_GLOBAL(cgtrfs,CGTRFS)\n#define LAPACK_zgtrfs LAPACK_GLOBAL(zgtrfs,ZGTRFS)\n#define LAPACK_sporfs LAPACK_GLOBAL(sporfs,SPORFS)\n#define LAPACK_dporfs LAPACK_GLOBAL(dporfs,DPORFS)\n#define LAPACK_cporfs LAPACK_GLOBAL(cporfs,CPORFS)\n#define LAPACK_zporfs LAPACK_GLOBAL(zporfs,ZPORFS)\n#define LAPACK_dporfsx LAPACK_GLOBAL(dporfsx,DPORFSX)\n#define LAPACK_sporfsx LAPACK_GLOBAL(sporfsx,SPORFSX)\n#define LAPACK_zporfsx LAPACK_GLOBAL(zporfsx,ZPORFSX)\n#define LAPACK_cporfsx LAPACK_GLOBAL(cporfsx,CPORFSX)\n#define LAPACK_spprfs LAPACK_GLOBAL(spprfs,SPPRFS)\n#define LAPACK_dpprfs LAPACK_GLOBAL(dpprfs,DPPRFS)\n#define LAPACK_cpprfs LAPACK_GLOBAL(cpprfs,CPPRFS)\n#define LAPACK_zpprfs LAPACK_GLOBAL(zpprfs,ZPPRFS)\n#define LAPACK_spbrfs LAPACK_GLOBAL(spbrfs,SPBRFS)\n#define LAPACK_dpbrfs LAPACK_GLOBAL(dpbrfs,DPBRFS)\n#define LAPACK_cpbrfs LAPACK_GLOBAL(cpbrfs,CPBRFS)\n#define LAPACK_zpbrfs LAPACK_GLOBAL(zpbrfs,ZPBRFS)\n#define LAPACK_sptrfs LAPACK_GLOBAL(sptrfs,SPTRFS)\n#define LAPACK_dptrfs LAPACK_GLOBAL(dptrfs,DPTRFS)\n#define LAPACK_cptrfs LAPACK_GLOBAL(cptrfs,CPTRFS)\n#define LAPACK_zptrfs LAPACK_GLOBAL(zptrfs,ZPTRFS)\n#define LAPACK_ssyrfs LAPACK_GLOBAL(ssyrfs,SSYRFS)\n#define LAPACK_dsyrfs LAPACK_GLOBAL(dsyrfs,DSYRFS)\n#define LAPACK_csyrfs LAPACK_GLOBAL(csyrfs,CSYRFS)\n#define LAPACK_zsyrfs LAPACK_GLOBAL(zsyrfs,ZSYRFS)\n#define LAPACK_dsyrfsx LAPACK_GLOBAL(dsyrfsx,DSYRFSX)\n#define LAPACK_ssyrfsx LAPACK_GLOBAL(ssyrfsx,SSYRFSX)\n#define LAPACK_zsyrfsx LAPACK_GLOBAL(zsyrfsx,ZSYRFSX)\n#define LAPACK_csyrfsx LAPACK_GLOBAL(csyrfsx,CSYRFSX)\n#define LAPACK_cherfs LAPACK_GLOBAL(cherfs,CHERFS)\n#define LAPACK_zherfs LAPACK_GLOBAL(zherfs,ZHERFS)\n#define LAPACK_zherfsx LAPACK_GLOBAL(zherfsx,ZHERFSX)\n#define LAPACK_cherfsx LAPACK_GLOBAL(cherfsx,CHERFSX)\n#define LAPACK_ssprfs LAPACK_GLOBAL(ssprfs,SSPRFS)\n#define LAPACK_dsprfs LAPACK_GLOBAL(dsprfs,DSPRFS)\n#define LAPACK_csprfs LAPACK_GLOBAL(csprfs,CSPRFS)\n#define LAPACK_zsprfs LAPACK_GLOBAL(zsprfs,ZSPRFS)\n#define LAPACK_chprfs LAPACK_GLOBAL(chprfs,CHPRFS)\n#define LAPACK_zhprfs LAPACK_GLOBAL(zhprfs,ZHPRFS)\n#define LAPACK_strrfs LAPACK_GLOBAL(strrfs,STRRFS)\n#define LAPACK_dtrrfs LAPACK_GLOBAL(dtrrfs,DTRRFS)\n#define LAPACK_ctrrfs LAPACK_GLOBAL(ctrrfs,CTRRFS)\n#define LAPACK_ztrrfs LAPACK_GLOBAL(ztrrfs,ZTRRFS)\n#define LAPACK_stprfs LAPACK_GLOBAL(stprfs,STPRFS)\n#define LAPACK_dtprfs LAPACK_GLOBAL(dtprfs,DTPRFS)\n#define LAPACK_ctprfs LAPACK_GLOBAL(ctprfs,CTPRFS)\n#define LAPACK_ztprfs LAPACK_GLOBAL(ztprfs,ZTPRFS)\n#define LAPACK_stbrfs LAPACK_GLOBAL(stbrfs,STBRFS)\n#define LAPACK_dtbrfs LAPACK_GLOBAL(dtbrfs,DTBRFS)\n#define LAPACK_ctbrfs LAPACK_GLOBAL(ctbrfs,CTBRFS)\n#define LAPACK_ztbrfs LAPACK_GLOBAL(ztbrfs,ZTBRFS)\n#define LAPACK_sgetri LAPACK_GLOBAL(sgetri,SGETRI)\n#define LAPACK_dgetri LAPACK_GLOBAL(dgetri,DGETRI)\n#define LAPACK_cgetri LAPACK_GLOBAL(cgetri,CGETRI)\n#define LAPACK_zgetri LAPACK_GLOBAL(zgetri,ZGETRI)\n#define LAPACK_spotri LAPACK_GLOBAL(spotri,SPOTRI)\n#define LAPACK_dpotri LAPACK_GLOBAL(dpotri,DPOTRI)\n#define LAPACK_cpotri LAPACK_GLOBAL(cpotri,CPOTRI)\n#define LAPACK_zpotri LAPACK_GLOBAL(zpotri,ZPOTRI)\n#define LAPACK_dpftri LAPACK_GLOBAL(dpftri,DPFTRI)\n#define LAPACK_spftri LAPACK_GLOBAL(spftri,SPFTRI)\n#define LAPACK_zpftri LAPACK_GLOBAL(zpftri,ZPFTRI)\n#define LAPACK_cpftri LAPACK_GLOBAL(cpftri,CPFTRI)\n#define LAPACK_spptri LAPACK_GLOBAL(spptri,SPPTRI)\n#define LAPACK_dpptri LAPACK_GLOBAL(dpptri,DPPTRI)\n#define LAPACK_cpptri LAPACK_GLOBAL(cpptri,CPPTRI)\n#define LAPACK_zpptri LAPACK_GLOBAL(zpptri,ZPPTRI)\n#define LAPACK_ssytri LAPACK_GLOBAL(ssytri,SSYTRI)\n#define LAPACK_dsytri LAPACK_GLOBAL(dsytri,DSYTRI)\n#define LAPACK_csytri LAPACK_GLOBAL(csytri,CSYTRI)\n#define LAPACK_zsytri LAPACK_GLOBAL(zsytri,ZSYTRI)\n#define LAPACK_chetri LAPACK_GLOBAL(chetri,CHETRI)\n#define LAPACK_zhetri LAPACK_GLOBAL(zhetri,ZHETRI)\n#define LAPACK_ssptri LAPACK_GLOBAL(ssptri,SSPTRI)\n#define LAPACK_dsptri LAPACK_GLOBAL(dsptri,DSPTRI)\n#define LAPACK_csptri LAPACK_GLOBAL(csptri,CSPTRI)\n#define LAPACK_zsptri LAPACK_GLOBAL(zsptri,ZSPTRI)\n#define LAPACK_chptri LAPACK_GLOBAL(chptri,CHPTRI)\n#define LAPACK_zhptri LAPACK_GLOBAL(zhptri,ZHPTRI)\n#define LAPACK_strtri LAPACK_GLOBAL(strtri,STRTRI)\n#define LAPACK_dtrtri LAPACK_GLOBAL(dtrtri,DTRTRI)\n#define LAPACK_ctrtri LAPACK_GLOBAL(ctrtri,CTRTRI)\n#define LAPACK_ztrtri LAPACK_GLOBAL(ztrtri,ZTRTRI)\n#define LAPACK_dtftri LAPACK_GLOBAL(dtftri,DTFTRI)\n#define LAPACK_stftri LAPACK_GLOBAL(stftri,STFTRI)\n#define LAPACK_ztftri LAPACK_GLOBAL(ztftri,ZTFTRI)\n#define LAPACK_ctftri LAPACK_GLOBAL(ctftri,CTFTRI)\n#define LAPACK_stptri LAPACK_GLOBAL(stptri,STPTRI)\n#define LAPACK_dtptri LAPACK_GLOBAL(dtptri,DTPTRI)\n#define LAPACK_ctptri LAPACK_GLOBAL(ctptri,CTPTRI)\n#define LAPACK_ztptri LAPACK_GLOBAL(ztptri,ZTPTRI)\n#define LAPACK_sgeequ LAPACK_GLOBAL(sgeequ,SGEEQU)\n#define LAPACK_dgeequ LAPACK_GLOBAL(dgeequ,DGEEQU)\n#define LAPACK_cgeequ LAPACK_GLOBAL(cgeequ,CGEEQU)\n#define LAPACK_zgeequ LAPACK_GLOBAL(zgeequ,ZGEEQU)\n#define LAPACK_dgeequb LAPACK_GLOBAL(dgeequb,DGEEQUB)\n#define LAPACK_sgeequb LAPACK_GLOBAL(sgeequb,SGEEQUB)\n#define LAPACK_zgeequb LAPACK_GLOBAL(zgeequb,ZGEEQUB)\n#define LAPACK_cgeequb LAPACK_GLOBAL(cgeequb,CGEEQUB)\n#define LAPACK_sgbequ LAPACK_GLOBAL(sgbequ,SGBEQU)\n#define LAPACK_dgbequ LAPACK_GLOBAL(dgbequ,DGBEQU)\n#define LAPACK_cgbequ LAPACK_GLOBAL(cgbequ,CGBEQU)\n#define LAPACK_zgbequ LAPACK_GLOBAL(zgbequ,ZGBEQU)\n#define LAPACK_dgbequb LAPACK_GLOBAL(dgbequb,DGBEQUB)\n#define LAPACK_sgbequb LAPACK_GLOBAL(sgbequb,SGBEQUB)\n#define LAPACK_zgbequb LAPACK_GLOBAL(zgbequb,ZGBEQUB)\n#define LAPACK_cgbequb LAPACK_GLOBAL(cgbequb,CGBEQUB)\n#define LAPACK_spoequ LAPACK_GLOBAL(spoequ,SPOEQU)\n#define LAPACK_dpoequ LAPACK_GLOBAL(dpoequ,DPOEQU)\n#define LAPACK_cpoequ LAPACK_GLOBAL(cpoequ,CPOEQU)\n#define LAPACK_zpoequ LAPACK_GLOBAL(zpoequ,ZPOEQU)\n#define LAPACK_dpoequb LAPACK_GLOBAL(dpoequb,DPOEQUB)\n#define LAPACK_spoequb LAPACK_GLOBAL(spoequb,SPOEQUB)\n#define LAPACK_zpoequb LAPACK_GLOBAL(zpoequb,ZPOEQUB)\n#define LAPACK_cpoequb LAPACK_GLOBAL(cpoequb,CPOEQUB)\n#define LAPACK_sppequ LAPACK_GLOBAL(sppequ,SPPEQU)\n#define LAPACK_dppequ LAPACK_GLOBAL(dppequ,DPPEQU)\n#define LAPACK_cppequ LAPACK_GLOBAL(cppequ,CPPEQU)\n#define LAPACK_zppequ LAPACK_GLOBAL(zppequ,ZPPEQU)\n#define LAPACK_spbequ LAPACK_GLOBAL(spbequ,SPBEQU)\n#define LAPACK_dpbequ LAPACK_GLOBAL(dpbequ,DPBEQU)\n#define LAPACK_cpbequ LAPACK_GLOBAL(cpbequ,CPBEQU)\n#define LAPACK_zpbequ LAPACK_GLOBAL(zpbequ,ZPBEQU)\n#define LAPACK_dsyequb LAPACK_GLOBAL(dsyequb,DSYEQUB)\n#define LAPACK_ssyequb LAPACK_GLOBAL(ssyequb,SSYEQUB)\n#define LAPACK_zsyequb LAPACK_GLOBAL(zsyequb,ZSYEQUB)\n#define LAPACK_csyequb LAPACK_GLOBAL(csyequb,CSYEQUB)\n#define LAPACK_zheequb LAPACK_GLOBAL(zheequb,ZHEEQUB)\n#define LAPACK_cheequb LAPACK_GLOBAL(cheequb,CHEEQUB)\n#define LAPACK_sgesv LAPACK_GLOBAL(sgesv,SGESV)\n#define LAPACK_dgesv LAPACK_GLOBAL(dgesv,DGESV)\n#define LAPACK_cgesv LAPACK_GLOBAL(cgesv,CGESV)\n#define LAPACK_zgesv LAPACK_GLOBAL(zgesv,ZGESV)\n#define LAPACK_dsgesv LAPACK_GLOBAL(dsgesv,DSGESV)\n#define LAPACK_zcgesv LAPACK_GLOBAL(zcgesv,ZCGESV)\n#define LAPACK_sgesvx LAPACK_GLOBAL(sgesvx,SGESVX)\n#define LAPACK_dgesvx LAPACK_GLOBAL(dgesvx,DGESVX)\n#define LAPACK_cgesvx LAPACK_GLOBAL(cgesvx,CGESVX)\n#define LAPACK_zgesvx LAPACK_GLOBAL(zgesvx,ZGESVX)\n#define LAPACK_dgesvxx LAPACK_GLOBAL(dgesvxx,DGESVXX)\n#define LAPACK_sgesvxx LAPACK_GLOBAL(sgesvxx,SGESVXX)\n#define LAPACK_zgesvxx LAPACK_GLOBAL(zgesvxx,ZGESVXX)\n#define LAPACK_cgesvxx LAPACK_GLOBAL(cgesvxx,CGESVXX)\n#define LAPACK_sgbsv LAPACK_GLOBAL(sgbsv,SGBSV)\n#define LAPACK_dgbsv LAPACK_GLOBAL(dgbsv,DGBSV)\n#define LAPACK_cgbsv LAPACK_GLOBAL(cgbsv,CGBSV)\n#define LAPACK_zgbsv LAPACK_GLOBAL(zgbsv,ZGBSV)\n#define LAPACK_sgbsvx LAPACK_GLOBAL(sgbsvx,SGBSVX)\n#define LAPACK_dgbsvx LAPACK_GLOBAL(dgbsvx,DGBSVX)\n#define LAPACK_cgbsvx LAPACK_GLOBAL(cgbsvx,CGBSVX)\n#define LAPACK_zgbsvx LAPACK_GLOBAL(zgbsvx,ZGBSVX)\n#define LAPACK_dgbsvxx LAPACK_GLOBAL(dgbsvxx,DGBSVXX)\n#define LAPACK_sgbsvxx LAPACK_GLOBAL(sgbsvxx,SGBSVXX)\n#define LAPACK_zgbsvxx LAPACK_GLOBAL(zgbsvxx,ZGBSVXX)\n#define LAPACK_cgbsvxx LAPACK_GLOBAL(cgbsvxx,CGBSVXX)\n#define LAPACK_sgtsv LAPACK_GLOBAL(sgtsv,SGTSV)\n#define LAPACK_dgtsv LAPACK_GLOBAL(dgtsv,DGTSV)\n#define LAPACK_cgtsv LAPACK_GLOBAL(cgtsv,CGTSV)\n#define LAPACK_zgtsv LAPACK_GLOBAL(zgtsv,ZGTSV)\n#define LAPACK_sgtsvx LAPACK_GLOBAL(sgtsvx,SGTSVX)\n#define LAPACK_dgtsvx LAPACK_GLOBAL(dgtsvx,DGTSVX)\n#define LAPACK_cgtsvx LAPACK_GLOBAL(cgtsvx,CGTSVX)\n#define LAPACK_zgtsvx LAPACK_GLOBAL(zgtsvx,ZGTSVX)\n#define LAPACK_sposv LAPACK_GLOBAL(sposv,SPOSV)\n#define LAPACK_dposv LAPACK_GLOBAL(dposv,DPOSV)\n#define LAPACK_cposv LAPACK_GLOBAL(cposv,CPOSV)\n#define LAPACK_zposv LAPACK_GLOBAL(zposv,ZPOSV)\n#define LAPACK_dsposv LAPACK_GLOBAL(dsposv,DSPOSV)\n#define LAPACK_zcposv LAPACK_GLOBAL(zcposv,ZCPOSV)\n#define LAPACK_sposvx LAPACK_GLOBAL(sposvx,SPOSVX)\n#define LAPACK_dposvx LAPACK_GLOBAL(dposvx,DPOSVX)\n#define LAPACK_cposvx LAPACK_GLOBAL(cposvx,CPOSVX)\n#define LAPACK_zposvx LAPACK_GLOBAL(zposvx,ZPOSVX)\n#define LAPACK_dposvxx LAPACK_GLOBAL(dposvxx,DPOSVXX)\n#define LAPACK_sposvxx LAPACK_GLOBAL(sposvxx,SPOSVXX)\n#define LAPACK_zposvxx LAPACK_GLOBAL(zposvxx,ZPOSVXX)\n#define LAPACK_cposvxx LAPACK_GLOBAL(cposvxx,CPOSVXX)\n#define LAPACK_sppsv LAPACK_GLOBAL(sppsv,SPPSV)\n#define LAPACK_dppsv LAPACK_GLOBAL(dppsv,DPPSV)\n#define LAPACK_cppsv LAPACK_GLOBAL(cppsv,CPPSV)\n#define LAPACK_zppsv LAPACK_GLOBAL(zppsv,ZPPSV)\n#define LAPACK_sppsvx LAPACK_GLOBAL(sppsvx,SPPSVX)\n#define LAPACK_dppsvx LAPACK_GLOBAL(dppsvx,DPPSVX)\n#define LAPACK_cppsvx LAPACK_GLOBAL(cppsvx,CPPSVX)\n#define LAPACK_zppsvx LAPACK_GLOBAL(zppsvx,ZPPSVX)\n#define LAPACK_spbsv LAPACK_GLOBAL(spbsv,SPBSV)\n#define LAPACK_dpbsv LAPACK_GLOBAL(dpbsv,DPBSV)\n#define LAPACK_cpbsv LAPACK_GLOBAL(cpbsv,CPBSV)\n#define LAPACK_zpbsv LAPACK_GLOBAL(zpbsv,ZPBSV)\n#define LAPACK_spbsvx LAPACK_GLOBAL(spbsvx,SPBSVX)\n#define LAPACK_dpbsvx LAPACK_GLOBAL(dpbsvx,DPBSVX)\n#define LAPACK_cpbsvx LAPACK_GLOBAL(cpbsvx,CPBSVX)\n#define LAPACK_zpbsvx LAPACK_GLOBAL(zpbsvx,ZPBSVX)\n#define LAPACK_sptsv LAPACK_GLOBAL(sptsv,SPTSV)\n#define LAPACK_dptsv LAPACK_GLOBAL(dptsv,DPTSV)\n#define LAPACK_cptsv LAPACK_GLOBAL(cptsv,CPTSV)\n#define LAPACK_zptsv LAPACK_GLOBAL(zptsv,ZPTSV)\n#define LAPACK_sptsvx LAPACK_GLOBAL(sptsvx,SPTSVX)\n#define LAPACK_dptsvx LAPACK_GLOBAL(dptsvx,DPTSVX)\n#define LAPACK_cptsvx LAPACK_GLOBAL(cptsvx,CPTSVX)\n#define LAPACK_zptsvx LAPACK_GLOBAL(zptsvx,ZPTSVX)\n#define LAPACK_ssysv LAPACK_GLOBAL(ssysv,SSYSV)\n#define LAPACK_dsysv LAPACK_GLOBAL(dsysv,DSYSV)\n#define LAPACK_csysv LAPACK_GLOBAL(csysv,CSYSV)\n#define LAPACK_zsysv LAPACK_GLOBAL(zsysv,ZSYSV)\n#define LAPACK_ssysvx LAPACK_GLOBAL(ssysvx,SSYSVX)\n#define LAPACK_dsysvx LAPACK_GLOBAL(dsysvx,DSYSVX)\n#define LAPACK_csysvx LAPACK_GLOBAL(csysvx,CSYSVX)\n#define LAPACK_zsysvx LAPACK_GLOBAL(zsysvx,ZSYSVX)\n#define LAPACK_dsysvxx LAPACK_GLOBAL(dsysvxx,DSYSVXX)\n#define LAPACK_ssysvxx LAPACK_GLOBAL(ssysvxx,SSYSVXX)\n#define LAPACK_zsysvxx LAPACK_GLOBAL(zsysvxx,ZSYSVXX)\n#define LAPACK_csysvxx LAPACK_GLOBAL(csysvxx,CSYSVXX)\n#define LAPACK_chesv LAPACK_GLOBAL(chesv,CHESV)\n#define LAPACK_zhesv LAPACK_GLOBAL(zhesv,ZHESV)\n#define LAPACK_chesvx LAPACK_GLOBAL(chesvx,CHESVX)\n#define LAPACK_zhesvx LAPACK_GLOBAL(zhesvx,ZHESVX)\n#define LAPACK_zhesvxx LAPACK_GLOBAL(zhesvxx,ZHESVXX)\n#define LAPACK_chesvxx LAPACK_GLOBAL(chesvxx,CHESVXX)\n#define LAPACK_sspsv LAPACK_GLOBAL(sspsv,SSPSV)\n#define LAPACK_dspsv LAPACK_GLOBAL(dspsv,DSPSV)\n#define LAPACK_cspsv LAPACK_GLOBAL(cspsv,CSPSV)\n#define LAPACK_zspsv LAPACK_GLOBAL(zspsv,ZSPSV)\n#define LAPACK_sspsvx LAPACK_GLOBAL(sspsvx,SSPSVX)\n#define LAPACK_dspsvx LAPACK_GLOBAL(dspsvx,DSPSVX)\n#define LAPACK_cspsvx LAPACK_GLOBAL(cspsvx,CSPSVX)\n#define LAPACK_zspsvx LAPACK_GLOBAL(zspsvx,ZSPSVX)\n#define LAPACK_chpsv LAPACK_GLOBAL(chpsv,CHPSV)\n#define LAPACK_zhpsv LAPACK_GLOBAL(zhpsv,ZHPSV)\n#define LAPACK_chpsvx LAPACK_GLOBAL(chpsvx,CHPSVX)\n#define LAPACK_zhpsvx LAPACK_GLOBAL(zhpsvx,ZHPSVX)\n#define LAPACK_sgeqrf LAPACK_GLOBAL(sgeqrf,SGEQRF)\n#define LAPACK_dgeqrf LAPACK_GLOBAL(dgeqrf,DGEQRF)\n#define LAPACK_cgeqrf LAPACK_GLOBAL(cgeqrf,CGEQRF)\n#define LAPACK_zgeqrf LAPACK_GLOBAL(zgeqrf,ZGEQRF)\n#define LAPACK_sgeqpf LAPACK_GLOBAL(sgeqpf,SGEQPF)\n#define LAPACK_dgeqpf LAPACK_GLOBAL(dgeqpf,DGEQPF)\n#define LAPACK_cgeqpf LAPACK_GLOBAL(cgeqpf,CGEQPF)\n#define LAPACK_zgeqpf LAPACK_GLOBAL(zgeqpf,ZGEQPF)\n#define LAPACK_sgeqp3 LAPACK_GLOBAL(sgeqp3,SGEQP3)\n#define LAPACK_dgeqp3 LAPACK_GLOBAL(dgeqp3,DGEQP3)\n#define LAPACK_cgeqp3 LAPACK_GLOBAL(cgeqp3,CGEQP3)\n#define LAPACK_zgeqp3 LAPACK_GLOBAL(zgeqp3,ZGEQP3)\n#define LAPACK_sorgqr LAPACK_GLOBAL(sorgqr,SORGQR)\n#define LAPACK_dorgqr LAPACK_GLOBAL(dorgqr,DORGQR)\n#define LAPACK_sormqr LAPACK_GLOBAL(sormqr,SORMQR)\n#define LAPACK_dormqr LAPACK_GLOBAL(dormqr,DORMQR)\n#define LAPACK_cungqr LAPACK_GLOBAL(cungqr,CUNGQR)\n#define LAPACK_zungqr LAPACK_GLOBAL(zungqr,ZUNGQR)\n#define LAPACK_cunmqr LAPACK_GLOBAL(cunmqr,CUNMQR)\n#define LAPACK_zunmqr LAPACK_GLOBAL(zunmqr,ZUNMQR)\n#define LAPACK_sgelqf LAPACK_GLOBAL(sgelqf,SGELQF)\n#define LAPACK_dgelqf LAPACK_GLOBAL(dgelqf,DGELQF)\n#define LAPACK_cgelqf LAPACK_GLOBAL(cgelqf,CGELQF)\n#define LAPACK_zgelqf LAPACK_GLOBAL(zgelqf,ZGELQF)\n#define LAPACK_sorglq LAPACK_GLOBAL(sorglq,SORGLQ)\n#define LAPACK_dorglq LAPACK_GLOBAL(dorglq,DORGLQ)\n#define LAPACK_sormlq LAPACK_GLOBAL(sormlq,SORMLQ)\n#define LAPACK_dormlq LAPACK_GLOBAL(dormlq,DORMLQ)\n#define LAPACK_cunglq LAPACK_GLOBAL(cunglq,CUNGLQ)\n#define LAPACK_zunglq LAPACK_GLOBAL(zunglq,ZUNGLQ)\n#define LAPACK_cunmlq LAPACK_GLOBAL(cunmlq,CUNMLQ)\n#define LAPACK_zunmlq LAPACK_GLOBAL(zunmlq,ZUNMLQ)\n#define LAPACK_sgeqlf LAPACK_GLOBAL(sgeqlf,SGEQLF)\n#define LAPACK_dgeqlf LAPACK_GLOBAL(dgeqlf,DGEQLF)\n#define LAPACK_cgeqlf LAPACK_GLOBAL(cgeqlf,CGEQLF)\n#define LAPACK_zgeqlf LAPACK_GLOBAL(zgeqlf,ZGEQLF)\n#define LAPACK_sorgql LAPACK_GLOBAL(sorgql,SORGQL)\n#define LAPACK_dorgql LAPACK_GLOBAL(dorgql,DORGQL)\n#define LAPACK_cungql LAPACK_GLOBAL(cungql,CUNGQL)\n#define LAPACK_zungql LAPACK_GLOBAL(zungql,ZUNGQL)\n#define LAPACK_sormql LAPACK_GLOBAL(sormql,SORMQL)\n#define LAPACK_dormql LAPACK_GLOBAL(dormql,DORMQL)\n#define LAPACK_cunmql LAPACK_GLOBAL(cunmql,CUNMQL)\n#define LAPACK_zunmql LAPACK_GLOBAL(zunmql,ZUNMQL)\n#define LAPACK_sgerqf LAPACK_GLOBAL(sgerqf,SGERQF)\n#define LAPACK_dgerqf LAPACK_GLOBAL(dgerqf,DGERQF)\n#define LAPACK_cgerqf LAPACK_GLOBAL(cgerqf,CGERQF)\n#define LAPACK_zgerqf LAPACK_GLOBAL(zgerqf,ZGERQF)\n#define LAPACK_sorgrq LAPACK_GLOBAL(sorgrq,SORGRQ)\n#define LAPACK_dorgrq LAPACK_GLOBAL(dorgrq,DORGRQ)\n#define LAPACK_cungrq LAPACK_GLOBAL(cungrq,CUNGRQ)\n#define LAPACK_zungrq LAPACK_GLOBAL(zungrq,ZUNGRQ)\n#define LAPACK_sormrq LAPACK_GLOBAL(sormrq,SORMRQ)\n#define LAPACK_dormrq LAPACK_GLOBAL(dormrq,DORMRQ)\n#define LAPACK_cunmrq LAPACK_GLOBAL(cunmrq,CUNMRQ)\n#define LAPACK_zunmrq LAPACK_GLOBAL(zunmrq,ZUNMRQ)\n#define LAPACK_stzrzf LAPACK_GLOBAL(stzrzf,STZRZF)\n#define LAPACK_dtzrzf LAPACK_GLOBAL(dtzrzf,DTZRZF)\n#define LAPACK_ctzrzf LAPACK_GLOBAL(ctzrzf,CTZRZF)\n#define LAPACK_ztzrzf LAPACK_GLOBAL(ztzrzf,ZTZRZF)\n#define LAPACK_sormrz LAPACK_GLOBAL(sormrz,SORMRZ)\n#define LAPACK_dormrz LAPACK_GLOBAL(dormrz,DORMRZ)\n#define LAPACK_cunmrz LAPACK_GLOBAL(cunmrz,CUNMRZ)\n#define LAPACK_zunmrz LAPACK_GLOBAL(zunmrz,ZUNMRZ)\n#define LAPACK_sggqrf LAPACK_GLOBAL(sggqrf,SGGQRF)\n#define LAPACK_dggqrf LAPACK_GLOBAL(dggqrf,DGGQRF)\n#define LAPACK_cggqrf LAPACK_GLOBAL(cggqrf,CGGQRF)\n#define LAPACK_zggqrf LAPACK_GLOBAL(zggqrf,ZGGQRF)\n#define LAPACK_sggrqf LAPACK_GLOBAL(sggrqf,SGGRQF)\n#define LAPACK_dggrqf LAPACK_GLOBAL(dggrqf,DGGRQF)\n#define LAPACK_cggrqf LAPACK_GLOBAL(cggrqf,CGGRQF)\n#define LAPACK_zggrqf LAPACK_GLOBAL(zggrqf,ZGGRQF)\n#define LAPACK_sgebrd LAPACK_GLOBAL(sgebrd,SGEBRD)\n#define LAPACK_dgebrd LAPACK_GLOBAL(dgebrd,DGEBRD)\n#define LAPACK_cgebrd LAPACK_GLOBAL(cgebrd,CGEBRD)\n#define LAPACK_zgebrd LAPACK_GLOBAL(zgebrd,ZGEBRD)\n#define LAPACK_sgbbrd LAPACK_GLOBAL(sgbbrd,SGBBRD)\n#define LAPACK_dgbbrd LAPACK_GLOBAL(dgbbrd,DGBBRD)\n#define LAPACK_cgbbrd LAPACK_GLOBAL(cgbbrd,CGBBRD)\n#define LAPACK_zgbbrd LAPACK_GLOBAL(zgbbrd,ZGBBRD)\n#define LAPACK_sorgbr LAPACK_GLOBAL(sorgbr,SORGBR)\n#define LAPACK_dorgbr LAPACK_GLOBAL(dorgbr,DORGBR)\n#define LAPACK_sormbr LAPACK_GLOBAL(sormbr,SORMBR)\n#define LAPACK_dormbr LAPACK_GLOBAL(dormbr,DORMBR)\n#define LAPACK_cungbr LAPACK_GLOBAL(cungbr,CUNGBR)\n#define LAPACK_zungbr LAPACK_GLOBAL(zungbr,ZUNGBR)\n#define LAPACK_cunmbr LAPACK_GLOBAL(cunmbr,CUNMBR)\n#define LAPACK_zunmbr LAPACK_GLOBAL(zunmbr,ZUNMBR)\n#define LAPACK_sbdsqr LAPACK_GLOBAL(sbdsqr,SBDSQR)\n#define LAPACK_dbdsqr LAPACK_GLOBAL(dbdsqr,DBDSQR)\n#define LAPACK_cbdsqr LAPACK_GLOBAL(cbdsqr,CBDSQR)\n#define LAPACK_zbdsqr LAPACK_GLOBAL(zbdsqr,ZBDSQR)\n#define LAPACK_sbdsdc LAPACK_GLOBAL(sbdsdc,SBDSDC)\n#define LAPACK_dbdsdc LAPACK_GLOBAL(dbdsdc,DBDSDC)\n#define LAPACK_ssytrd LAPACK_GLOBAL(ssytrd,SSYTRD)\n#define LAPACK_dsytrd LAPACK_GLOBAL(dsytrd,DSYTRD)\n#define LAPACK_sorgtr LAPACK_GLOBAL(sorgtr,SORGTR)\n#define LAPACK_dorgtr LAPACK_GLOBAL(dorgtr,DORGTR)\n#define LAPACK_sormtr LAPACK_GLOBAL(sormtr,SORMTR)\n#define LAPACK_dormtr LAPACK_GLOBAL(dormtr,DORMTR)\n#define LAPACK_chetrd LAPACK_GLOBAL(chetrd,CHETRD)\n#define LAPACK_zhetrd LAPACK_GLOBAL(zhetrd,ZHETRD)\n#define LAPACK_cungtr LAPACK_GLOBAL(cungtr,CUNGTR)\n#define LAPACK_zungtr LAPACK_GLOBAL(zungtr,ZUNGTR)\n#define LAPACK_cunmtr LAPACK_GLOBAL(cunmtr,CUNMTR)\n#define LAPACK_zunmtr LAPACK_GLOBAL(zunmtr,ZUNMTR)\n#define LAPACK_ssptrd LAPACK_GLOBAL(ssptrd,SSPTRD)\n#define LAPACK_dsptrd LAPACK_GLOBAL(dsptrd,DSPTRD)\n#define LAPACK_sopgtr LAPACK_GLOBAL(sopgtr,SOPGTR)\n#define LAPACK_dopgtr LAPACK_GLOBAL(dopgtr,DOPGTR)\n#define LAPACK_sopmtr LAPACK_GLOBAL(sopmtr,SOPMTR)\n#define LAPACK_dopmtr LAPACK_GLOBAL(dopmtr,DOPMTR)\n#define LAPACK_chptrd LAPACK_GLOBAL(chptrd,CHPTRD)\n#define LAPACK_zhptrd LAPACK_GLOBAL(zhptrd,ZHPTRD)\n#define LAPACK_cupgtr LAPACK_GLOBAL(cupgtr,CUPGTR)\n#define LAPACK_zupgtr LAPACK_GLOBAL(zupgtr,ZUPGTR)\n#define LAPACK_cupmtr LAPACK_GLOBAL(cupmtr,CUPMTR)\n#define LAPACK_zupmtr LAPACK_GLOBAL(zupmtr,ZUPMTR)\n#define LAPACK_ssbtrd LAPACK_GLOBAL(ssbtrd,SSBTRD)\n#define LAPACK_dsbtrd LAPACK_GLOBAL(dsbtrd,DSBTRD)\n#define LAPACK_chbtrd LAPACK_GLOBAL(chbtrd,CHBTRD)\n#define LAPACK_zhbtrd LAPACK_GLOBAL(zhbtrd,ZHBTRD)\n#define LAPACK_ssterf LAPACK_GLOBAL(ssterf,SSTERF)\n#define LAPACK_dsterf LAPACK_GLOBAL(dsterf,DSTERF)\n#define LAPACK_ssteqr LAPACK_GLOBAL(ssteqr,SSTEQR)\n#define LAPACK_dsteqr LAPACK_GLOBAL(dsteqr,DSTEQR)\n#define LAPACK_csteqr LAPACK_GLOBAL(csteqr,CSTEQR)\n#define LAPACK_zsteqr LAPACK_GLOBAL(zsteqr,ZSTEQR)\n#define LAPACK_sstemr LAPACK_GLOBAL(sstemr,SSTEMR)\n#define LAPACK_dstemr LAPACK_GLOBAL(dstemr,DSTEMR)\n#define LAPACK_cstemr LAPACK_GLOBAL(cstemr,CSTEMR)\n#define LAPACK_zstemr LAPACK_GLOBAL(zstemr,ZSTEMR)\n#define LAPACK_sstedc LAPACK_GLOBAL(sstedc,SSTEDC)\n#define LAPACK_dstedc LAPACK_GLOBAL(dstedc,DSTEDC)\n#define LAPACK_cstedc LAPACK_GLOBAL(cstedc,CSTEDC)\n#define LAPACK_zstedc LAPACK_GLOBAL(zstedc,ZSTEDC)\n#define LAPACK_sstegr LAPACK_GLOBAL(sstegr,SSTEGR)\n#define LAPACK_dstegr LAPACK_GLOBAL(dstegr,DSTEGR)\n#define LAPACK_cstegr LAPACK_GLOBAL(cstegr,CSTEGR)\n#define LAPACK_zstegr LAPACK_GLOBAL(zstegr,ZSTEGR)\n#define LAPACK_spteqr LAPACK_GLOBAL(spteqr,SPTEQR)\n#define LAPACK_dpteqr LAPACK_GLOBAL(dpteqr,DPTEQR)\n#define LAPACK_cpteqr LAPACK_GLOBAL(cpteqr,CPTEQR)\n#define LAPACK_zpteqr LAPACK_GLOBAL(zpteqr,ZPTEQR)\n#define LAPACK_sstebz LAPACK_GLOBAL(sstebz,SSTEBZ)\n#define LAPACK_dstebz LAPACK_GLOBAL(dstebz,DSTEBZ)\n#define LAPACK_sstein LAPACK_GLOBAL(sstein,SSTEIN)\n#define LAPACK_dstein LAPACK_GLOBAL(dstein,DSTEIN)\n#define LAPACK_cstein LAPACK_GLOBAL(cstein,CSTEIN)\n#define LAPACK_zstein LAPACK_GLOBAL(zstein,ZSTEIN)\n#define LAPACK_sdisna LAPACK_GLOBAL(sdisna,SDISNA)\n#define LAPACK_ddisna LAPACK_GLOBAL(ddisna,DDISNA)\n#define LAPACK_ssygst LAPACK_GLOBAL(ssygst,SSYGST)\n#define LAPACK_dsygst LAPACK_GLOBAL(dsygst,DSYGST)\n#define LAPACK_chegst LAPACK_GLOBAL(chegst,CHEGST)\n#define LAPACK_zhegst LAPACK_GLOBAL(zhegst,ZHEGST)\n#define LAPACK_sspgst LAPACK_GLOBAL(sspgst,SSPGST)\n#define LAPACK_dspgst LAPACK_GLOBAL(dspgst,DSPGST)\n#define LAPACK_chpgst LAPACK_GLOBAL(chpgst,CHPGST)\n#define LAPACK_zhpgst LAPACK_GLOBAL(zhpgst,ZHPGST)\n#define LAPACK_ssbgst LAPACK_GLOBAL(ssbgst,SSBGST)\n#define LAPACK_dsbgst LAPACK_GLOBAL(dsbgst,DSBGST)\n#define LAPACK_chbgst LAPACK_GLOBAL(chbgst,CHBGST)\n#define LAPACK_zhbgst LAPACK_GLOBAL(zhbgst,ZHBGST)\n#define LAPACK_spbstf LAPACK_GLOBAL(spbstf,SPBSTF)\n#define LAPACK_dpbstf LAPACK_GLOBAL(dpbstf,DPBSTF)\n#define LAPACK_cpbstf LAPACK_GLOBAL(cpbstf,CPBSTF)\n#define LAPACK_zpbstf LAPACK_GLOBAL(zpbstf,ZPBSTF)\n#define LAPACK_sgehrd LAPACK_GLOBAL(sgehrd,SGEHRD)\n#define LAPACK_dgehrd LAPACK_GLOBAL(dgehrd,DGEHRD)\n#define LAPACK_cgehrd LAPACK_GLOBAL(cgehrd,CGEHRD)\n#define LAPACK_zgehrd LAPACK_GLOBAL(zgehrd,ZGEHRD)\n#define LAPACK_sorghr LAPACK_GLOBAL(sorghr,SORGHR)\n#define LAPACK_dorghr LAPACK_GLOBAL(dorghr,DORGHR)\n#define LAPACK_sormhr LAPACK_GLOBAL(sormhr,SORMHR)\n#define LAPACK_dormhr LAPACK_GLOBAL(dormhr,DORMHR)\n#define LAPACK_cunghr LAPACK_GLOBAL(cunghr,CUNGHR)\n#define LAPACK_zunghr LAPACK_GLOBAL(zunghr,ZUNGHR)\n#define LAPACK_cunmhr LAPACK_GLOBAL(cunmhr,CUNMHR)\n#define LAPACK_zunmhr LAPACK_GLOBAL(zunmhr,ZUNMHR)\n#define LAPACK_sgebal LAPACK_GLOBAL(sgebal,SGEBAL)\n#define LAPACK_dgebal LAPACK_GLOBAL(dgebal,DGEBAL)\n#define LAPACK_cgebal LAPACK_GLOBAL(cgebal,CGEBAL)\n#define LAPACK_zgebal LAPACK_GLOBAL(zgebal,ZGEBAL)\n#define LAPACK_sgebak LAPACK_GLOBAL(sgebak,SGEBAK)\n#define LAPACK_dgebak LAPACK_GLOBAL(dgebak,DGEBAK)\n#define LAPACK_cgebak LAPACK_GLOBAL(cgebak,CGEBAK)\n#define LAPACK_zgebak LAPACK_GLOBAL(zgebak,ZGEBAK)\n#define LAPACK_shseqr LAPACK_GLOBAL(shseqr,SHSEQR)\n#define LAPACK_dhseqr LAPACK_GLOBAL(dhseqr,DHSEQR)\n#define LAPACK_chseqr LAPACK_GLOBAL(chseqr,CHSEQR)\n#define LAPACK_zhseqr LAPACK_GLOBAL(zhseqr,ZHSEQR)\n#define LAPACK_shsein LAPACK_GLOBAL(shsein,SHSEIN)\n#define LAPACK_dhsein LAPACK_GLOBAL(dhsein,DHSEIN)\n#define LAPACK_chsein LAPACK_GLOBAL(chsein,CHSEIN)\n#define LAPACK_zhsein LAPACK_GLOBAL(zhsein,ZHSEIN)\n#define LAPACK_strevc LAPACK_GLOBAL(strevc,STREVC)\n#define LAPACK_dtrevc LAPACK_GLOBAL(dtrevc,DTREVC)\n#define LAPACK_ctrevc LAPACK_GLOBAL(ctrevc,CTREVC)\n#define LAPACK_ztrevc LAPACK_GLOBAL(ztrevc,ZTREVC)\n#define LAPACK_strsna LAPACK_GLOBAL(strsna,STRSNA)\n#define LAPACK_dtrsna LAPACK_GLOBAL(dtrsna,DTRSNA)\n#define LAPACK_ctrsna LAPACK_GLOBAL(ctrsna,CTRSNA)\n#define LAPACK_ztrsna LAPACK_GLOBAL(ztrsna,ZTRSNA)\n#define LAPACK_strexc LAPACK_GLOBAL(strexc,STREXC)\n#define LAPACK_dtrexc LAPACK_GLOBAL(dtrexc,DTREXC)\n#define LAPACK_ctrexc LAPACK_GLOBAL(ctrexc,CTREXC)\n#define LAPACK_ztrexc LAPACK_GLOBAL(ztrexc,ZTREXC)\n#define LAPACK_strsen LAPACK_GLOBAL(strsen,STRSEN)\n#define LAPACK_dtrsen LAPACK_GLOBAL(dtrsen,DTRSEN)\n#define LAPACK_ctrsen LAPACK_GLOBAL(ctrsen,CTRSEN)\n#define LAPACK_ztrsen LAPACK_GLOBAL(ztrsen,ZTRSEN)\n#define LAPACK_strsyl LAPACK_GLOBAL(strsyl,STRSYL)\n#define LAPACK_dtrsyl LAPACK_GLOBAL(dtrsyl,DTRSYL)\n#define LAPACK_ctrsyl LAPACK_GLOBAL(ctrsyl,CTRSYL)\n#define LAPACK_ztrsyl LAPACK_GLOBAL(ztrsyl,ZTRSYL)\n#define LAPACK_sgghrd LAPACK_GLOBAL(sgghrd,SGGHRD)\n#define LAPACK_dgghrd LAPACK_GLOBAL(dgghrd,DGGHRD)\n#define LAPACK_cgghrd LAPACK_GLOBAL(cgghrd,CGGHRD)\n#define LAPACK_zgghrd LAPACK_GLOBAL(zgghrd,ZGGHRD)\n#define LAPACK_sggbal LAPACK_GLOBAL(sggbal,SGGBAL)\n#define LAPACK_dggbal LAPACK_GLOBAL(dggbal,DGGBAL)\n#define LAPACK_cggbal LAPACK_GLOBAL(cggbal,CGGBAL)\n#define LAPACK_zggbal LAPACK_GLOBAL(zggbal,ZGGBAL)\n#define LAPACK_sggbak LAPACK_GLOBAL(sggbak,SGGBAK)\n#define LAPACK_dggbak LAPACK_GLOBAL(dggbak,DGGBAK)\n#define LAPACK_cggbak LAPACK_GLOBAL(cggbak,CGGBAK)\n#define LAPACK_zggbak LAPACK_GLOBAL(zggbak,ZGGBAK)\n#define LAPACK_shgeqz LAPACK_GLOBAL(shgeqz,SHGEQZ)\n#define LAPACK_dhgeqz LAPACK_GLOBAL(dhgeqz,DHGEQZ)\n#define LAPACK_chgeqz LAPACK_GLOBAL(chgeqz,CHGEQZ)\n#define LAPACK_zhgeqz LAPACK_GLOBAL(zhgeqz,ZHGEQZ)\n#define LAPACK_stgevc LAPACK_GLOBAL(stgevc,STGEVC)\n#define LAPACK_dtgevc LAPACK_GLOBAL(dtgevc,DTGEVC)\n#define LAPACK_ctgevc LAPACK_GLOBAL(ctgevc,CTGEVC)\n#define LAPACK_ztgevc LAPACK_GLOBAL(ztgevc,ZTGEVC)\n#define LAPACK_stgexc LAPACK_GLOBAL(stgexc,STGEXC)\n#define LAPACK_dtgexc LAPACK_GLOBAL(dtgexc,DTGEXC)\n#define LAPACK_ctgexc LAPACK_GLOBAL(ctgexc,CTGEXC)\n#define LAPACK_ztgexc LAPACK_GLOBAL(ztgexc,ZTGEXC)\n#define LAPACK_stgsen LAPACK_GLOBAL(stgsen,STGSEN)\n#define LAPACK_dtgsen LAPACK_GLOBAL(dtgsen,DTGSEN)\n#define LAPACK_ctgsen LAPACK_GLOBAL(ctgsen,CTGSEN)\n#define LAPACK_ztgsen LAPACK_GLOBAL(ztgsen,ZTGSEN)\n#define LAPACK_stgsyl LAPACK_GLOBAL(stgsyl,STGSYL)\n#define LAPACK_dtgsyl LAPACK_GLOBAL(dtgsyl,DTGSYL)\n#define LAPACK_ctgsyl LAPACK_GLOBAL(ctgsyl,CTGSYL)\n#define LAPACK_ztgsyl LAPACK_GLOBAL(ztgsyl,ZTGSYL)\n#define LAPACK_stgsna LAPACK_GLOBAL(stgsna,STGSNA)\n#define LAPACK_dtgsna LAPACK_GLOBAL(dtgsna,DTGSNA)\n#define LAPACK_ctgsna LAPACK_GLOBAL(ctgsna,CTGSNA)\n#define LAPACK_ztgsna LAPACK_GLOBAL(ztgsna,ZTGSNA)\n#define LAPACK_sggsvp LAPACK_GLOBAL(sggsvp,SGGSVP)\n#define LAPACK_dggsvp LAPACK_GLOBAL(dggsvp,DGGSVP)\n#define LAPACK_cggsvp LAPACK_GLOBAL(cggsvp,CGGSVP)\n#define LAPACK_zggsvp LAPACK_GLOBAL(zggsvp,ZGGSVP)\n#define LAPACK_stgsja LAPACK_GLOBAL(stgsja,STGSJA)\n#define LAPACK_dtgsja LAPACK_GLOBAL(dtgsja,DTGSJA)\n#define LAPACK_ctgsja LAPACK_GLOBAL(ctgsja,CTGSJA)\n#define LAPACK_ztgsja LAPACK_GLOBAL(ztgsja,ZTGSJA)\n#define LAPACK_sgels LAPACK_GLOBAL(sgels,SGELS)\n#define LAPACK_dgels LAPACK_GLOBAL(dgels,DGELS)\n#define LAPACK_cgels LAPACK_GLOBAL(cgels,CGELS)\n#define LAPACK_zgels LAPACK_GLOBAL(zgels,ZGELS)\n#define LAPACK_sgelsy LAPACK_GLOBAL(sgelsy,SGELSY)\n#define LAPACK_dgelsy LAPACK_GLOBAL(dgelsy,DGELSY)\n#define LAPACK_cgelsy LAPACK_GLOBAL(cgelsy,CGELSY)\n#define LAPACK_zgelsy LAPACK_GLOBAL(zgelsy,ZGELSY)\n#define LAPACK_sgelss LAPACK_GLOBAL(sgelss,SGELSS)\n#define LAPACK_dgelss LAPACK_GLOBAL(dgelss,DGELSS)\n#define LAPACK_cgelss LAPACK_GLOBAL(cgelss,CGELSS)\n#define LAPACK_zgelss LAPACK_GLOBAL(zgelss,ZGELSS)\n#define LAPACK_sgelsd LAPACK_GLOBAL(sgelsd,SGELSD)\n#define LAPACK_dgelsd LAPACK_GLOBAL(dgelsd,DGELSD)\n#define LAPACK_cgelsd LAPACK_GLOBAL(cgelsd,CGELSD)\n#define LAPACK_zgelsd LAPACK_GLOBAL(zgelsd,ZGELSD)\n#define LAPACK_sgglse LAPACK_GLOBAL(sgglse,SGGLSE)\n#define LAPACK_dgglse LAPACK_GLOBAL(dgglse,DGGLSE)\n#define LAPACK_cgglse LAPACK_GLOBAL(cgglse,CGGLSE)\n#define LAPACK_zgglse LAPACK_GLOBAL(zgglse,ZGGLSE)\n#define LAPACK_sggglm LAPACK_GLOBAL(sggglm,SGGGLM)\n#define LAPACK_dggglm LAPACK_GLOBAL(dggglm,DGGGLM)\n#define LAPACK_cggglm LAPACK_GLOBAL(cggglm,CGGGLM)\n#define LAPACK_zggglm LAPACK_GLOBAL(zggglm,ZGGGLM)\n#define LAPACK_ssyev LAPACK_GLOBAL(ssyev,SSYEV)\n#define LAPACK_dsyev LAPACK_GLOBAL(dsyev,DSYEV)\n#define LAPACK_cheev LAPACK_GLOBAL(cheev,CHEEV)\n#define LAPACK_zheev LAPACK_GLOBAL(zheev,ZHEEV)\n#define LAPACK_ssyevd LAPACK_GLOBAL(ssyevd,SSYEVD)\n#define LAPACK_dsyevd LAPACK_GLOBAL(dsyevd,DSYEVD)\n#define LAPACK_cheevd LAPACK_GLOBAL(cheevd,CHEEVD)\n#define LAPACK_zheevd LAPACK_GLOBAL(zheevd,ZHEEVD)\n#define LAPACK_ssyevx LAPACK_GLOBAL(ssyevx,SSYEVX)\n#define LAPACK_dsyevx LAPACK_GLOBAL(dsyevx,DSYEVX)\n#define LAPACK_cheevx LAPACK_GLOBAL(cheevx,CHEEVX)\n#define LAPACK_zheevx LAPACK_GLOBAL(zheevx,ZHEEVX)\n#define LAPACK_ssyevr LAPACK_GLOBAL(ssyevr,SSYEVR)\n#define LAPACK_dsyevr LAPACK_GLOBAL(dsyevr,DSYEVR)\n#define LAPACK_cheevr LAPACK_GLOBAL(cheevr,CHEEVR)\n#define LAPACK_zheevr LAPACK_GLOBAL(zheevr,ZHEEVR)\n#define LAPACK_sspev LAPACK_GLOBAL(sspev,SSPEV)\n#define LAPACK_dspev LAPACK_GLOBAL(dspev,DSPEV)\n#define LAPACK_chpev LAPACK_GLOBAL(chpev,CHPEV)\n#define LAPACK_zhpev LAPACK_GLOBAL(zhpev,ZHPEV)\n#define LAPACK_sspevd LAPACK_GLOBAL(sspevd,SSPEVD)\n#define LAPACK_dspevd LAPACK_GLOBAL(dspevd,DSPEVD)\n#define LAPACK_chpevd LAPACK_GLOBAL(chpevd,CHPEVD)\n#define LAPACK_zhpevd LAPACK_GLOBAL(zhpevd,ZHPEVD)\n#define LAPACK_sspevx LAPACK_GLOBAL(sspevx,SSPEVX)\n#define LAPACK_dspevx LAPACK_GLOBAL(dspevx,DSPEVX)\n#define LAPACK_chpevx LAPACK_GLOBAL(chpevx,CHPEVX)\n#define LAPACK_zhpevx LAPACK_GLOBAL(zhpevx,ZHPEVX)\n#define LAPACK_ssbev LAPACK_GLOBAL(ssbev,SSBEV)\n#define LAPACK_dsbev LAPACK_GLOBAL(dsbev,DSBEV)\n#define LAPACK_chbev LAPACK_GLOBAL(chbev,CHBEV)\n#define LAPACK_zhbev LAPACK_GLOBAL(zhbev,ZHBEV)\n#define LAPACK_ssbevd LAPACK_GLOBAL(ssbevd,SSBEVD)\n#define LAPACK_dsbevd LAPACK_GLOBAL(dsbevd,DSBEVD)\n#define LAPACK_chbevd LAPACK_GLOBAL(chbevd,CHBEVD)\n#define LAPACK_zhbevd LAPACK_GLOBAL(zhbevd,ZHBEVD)\n#define LAPACK_ssbevx LAPACK_GLOBAL(ssbevx,SSBEVX)\n#define LAPACK_dsbevx LAPACK_GLOBAL(dsbevx,DSBEVX)\n#define LAPACK_chbevx LAPACK_GLOBAL(chbevx,CHBEVX)\n#define LAPACK_zhbevx LAPACK_GLOBAL(zhbevx,ZHBEVX)\n#define LAPACK_sstev LAPACK_GLOBAL(sstev,SSTEV)\n#define LAPACK_dstev LAPACK_GLOBAL(dstev,DSTEV)\n#define LAPACK_sstevd LAPACK_GLOBAL(sstevd,SSTEVD)\n#define LAPACK_dstevd LAPACK_GLOBAL(dstevd,DSTEVD)\n#define LAPACK_sstevx LAPACK_GLOBAL(sstevx,SSTEVX)\n#define LAPACK_dstevx LAPACK_GLOBAL(dstevx,DSTEVX)\n#define LAPACK_sstevr LAPACK_GLOBAL(sstevr,SSTEVR)\n#define LAPACK_dstevr LAPACK_GLOBAL(dstevr,DSTEVR)\n#define LAPACK_sgees LAPACK_GLOBAL(sgees,SGEES)\n#define LAPACK_dgees LAPACK_GLOBAL(dgees,DGEES)\n#define LAPACK_cgees LAPACK_GLOBAL(cgees,CGEES)\n#define LAPACK_zgees LAPACK_GLOBAL(zgees,ZGEES)\n#define LAPACK_sgeesx LAPACK_GLOBAL(sgeesx,SGEESX)\n#define LAPACK_dgeesx LAPACK_GLOBAL(dgeesx,DGEESX)\n#define LAPACK_cgeesx LAPACK_GLOBAL(cgeesx,CGEESX)\n#define LAPACK_zgeesx LAPACK_GLOBAL(zgeesx,ZGEESX)\n#define LAPACK_sgeev LAPACK_GLOBAL(sgeev,SGEEV)\n#define LAPACK_dgeev LAPACK_GLOBAL(dgeev,DGEEV)\n#define LAPACK_cgeev LAPACK_GLOBAL(cgeev,CGEEV)\n#define LAPACK_zgeev LAPACK_GLOBAL(zgeev,ZGEEV)\n#define LAPACK_sgeevx LAPACK_GLOBAL(sgeevx,SGEEVX)\n#define LAPACK_dgeevx LAPACK_GLOBAL(dgeevx,DGEEVX)\n#define LAPACK_cgeevx LAPACK_GLOBAL(cgeevx,CGEEVX)\n#define LAPACK_zgeevx LAPACK_GLOBAL(zgeevx,ZGEEVX)\n#define LAPACK_sgesvd LAPACK_GLOBAL(sgesvd,SGESVD)\n#define LAPACK_dgesvd LAPACK_GLOBAL(dgesvd,DGESVD)\n#define LAPACK_cgesvd LAPACK_GLOBAL(cgesvd,CGESVD)\n#define LAPACK_zgesvd LAPACK_GLOBAL(zgesvd,ZGESVD)\n#define LAPACK_sgesdd LAPACK_GLOBAL(sgesdd,SGESDD)\n#define LAPACK_dgesdd LAPACK_GLOBAL(dgesdd,DGESDD)\n#define LAPACK_cgesdd LAPACK_GLOBAL(cgesdd,CGESDD)\n#define LAPACK_zgesdd LAPACK_GLOBAL(zgesdd,ZGESDD)\n#define LAPACK_dgejsv LAPACK_GLOBAL(dgejsv,DGEJSV)\n#define LAPACK_sgejsv LAPACK_GLOBAL(sgejsv,SGEJSV)\n#define LAPACK_dgesvj LAPACK_GLOBAL(dgesvj,DGESVJ)\n#define LAPACK_sgesvj LAPACK_GLOBAL(sgesvj,SGESVJ)\n#define LAPACK_sggsvd LAPACK_GLOBAL(sggsvd,SGGSVD)\n#define LAPACK_dggsvd LAPACK_GLOBAL(dggsvd,DGGSVD)\n#define LAPACK_cggsvd LAPACK_GLOBAL(cggsvd,CGGSVD)\n#define LAPACK_zggsvd LAPACK_GLOBAL(zggsvd,ZGGSVD)\n#define LAPACK_ssygv LAPACK_GLOBAL(ssygv,SSYGV)\n#define LAPACK_dsygv LAPACK_GLOBAL(dsygv,DSYGV)\n#define LAPACK_chegv LAPACK_GLOBAL(chegv,CHEGV)\n#define LAPACK_zhegv LAPACK_GLOBAL(zhegv,ZHEGV)\n#define LAPACK_ssygvd LAPACK_GLOBAL(ssygvd,SSYGVD)\n#define LAPACK_dsygvd LAPACK_GLOBAL(dsygvd,DSYGVD)\n#define LAPACK_chegvd LAPACK_GLOBAL(chegvd,CHEGVD)\n#define LAPACK_zhegvd LAPACK_GLOBAL(zhegvd,ZHEGVD)\n#define LAPACK_ssygvx LAPACK_GLOBAL(ssygvx,SSYGVX)\n#define LAPACK_dsygvx LAPACK_GLOBAL(dsygvx,DSYGVX)\n#define LAPACK_chegvx LAPACK_GLOBAL(chegvx,CHEGVX)\n#define LAPACK_zhegvx LAPACK_GLOBAL(zhegvx,ZHEGVX)\n#define LAPACK_sspgv LAPACK_GLOBAL(sspgv,SSPGV)\n#define LAPACK_dspgv LAPACK_GLOBAL(dspgv,DSPGV)\n#define LAPACK_chpgv LAPACK_GLOBAL(chpgv,CHPGV)\n#define LAPACK_zhpgv LAPACK_GLOBAL(zhpgv,ZHPGV)\n#define LAPACK_sspgvd LAPACK_GLOBAL(sspgvd,SSPGVD)\n#define LAPACK_dspgvd LAPACK_GLOBAL(dspgvd,DSPGVD)\n#define LAPACK_chpgvd LAPACK_GLOBAL(chpgvd,CHPGVD)\n#define LAPACK_zhpgvd LAPACK_GLOBAL(zhpgvd,ZHPGVD)\n#define LAPACK_sspgvx LAPACK_GLOBAL(sspgvx,SSPGVX)\n#define LAPACK_dspgvx LAPACK_GLOBAL(dspgvx,DSPGVX)\n#define LAPACK_chpgvx LAPACK_GLOBAL(chpgvx,CHPGVX)\n#define LAPACK_zhpgvx LAPACK_GLOBAL(zhpgvx,ZHPGVX)\n#define LAPACK_ssbgv LAPACK_GLOBAL(ssbgv,SSBGV)\n#define LAPACK_dsbgv LAPACK_GLOBAL(dsbgv,DSBGV)\n#define LAPACK_chbgv LAPACK_GLOBAL(chbgv,CHBGV)\n#define LAPACK_zhbgv LAPACK_GLOBAL(zhbgv,ZHBGV)\n#define LAPACK_ssbgvd LAPACK_GLOBAL(ssbgvd,SSBGVD)\n#define LAPACK_dsbgvd LAPACK_GLOBAL(dsbgvd,DSBGVD)\n#define LAPACK_chbgvd LAPACK_GLOBAL(chbgvd,CHBGVD)\n#define LAPACK_zhbgvd LAPACK_GLOBAL(zhbgvd,ZHBGVD)\n#define LAPACK_ssbgvx LAPACK_GLOBAL(ssbgvx,SSBGVX)\n#define LAPACK_dsbgvx LAPACK_GLOBAL(dsbgvx,DSBGVX)\n#define LAPACK_chbgvx LAPACK_GLOBAL(chbgvx,CHBGVX)\n#define LAPACK_zhbgvx LAPACK_GLOBAL(zhbgvx,ZHBGVX)\n#define LAPACK_sgges LAPACK_GLOBAL(sgges,SGGES)\n#define LAPACK_dgges LAPACK_GLOBAL(dgges,DGGES)\n#define LAPACK_cgges LAPACK_GLOBAL(cgges,CGGES)\n#define LAPACK_zgges LAPACK_GLOBAL(zgges,ZGGES)\n#define LAPACK_sggesx LAPACK_GLOBAL(sggesx,SGGESX)\n#define LAPACK_dggesx LAPACK_GLOBAL(dggesx,DGGESX)\n#define LAPACK_cggesx LAPACK_GLOBAL(cggesx,CGGESX)\n#define LAPACK_zggesx LAPACK_GLOBAL(zggesx,ZGGESX)\n#define LAPACK_sggev LAPACK_GLOBAL(sggev,SGGEV)\n#define LAPACK_dggev LAPACK_GLOBAL(dggev,DGGEV)\n#define LAPACK_cggev LAPACK_GLOBAL(cggev,CGGEV)\n#define LAPACK_zggev LAPACK_GLOBAL(zggev,ZGGEV)\n#define LAPACK_sggevx LAPACK_GLOBAL(sggevx,SGGEVX)\n#define LAPACK_dggevx LAPACK_GLOBAL(dggevx,DGGEVX)\n#define LAPACK_cggevx LAPACK_GLOBAL(cggevx,CGGEVX)\n#define LAPACK_zggevx LAPACK_GLOBAL(zggevx,ZGGEVX)\n#define LAPACK_dsfrk LAPACK_GLOBAL(dsfrk,DSFRK)\n#define LAPACK_ssfrk LAPACK_GLOBAL(ssfrk,SSFRK)\n#define LAPACK_zhfrk LAPACK_GLOBAL(zhfrk,ZHFRK)\n#define LAPACK_chfrk LAPACK_GLOBAL(chfrk,CHFRK)\n#define LAPACK_dtfsm LAPACK_GLOBAL(dtfsm,DTFSM)\n#define LAPACK_stfsm LAPACK_GLOBAL(stfsm,STFSM)\n#define LAPACK_ztfsm LAPACK_GLOBAL(ztfsm,ZTFSM)\n#define LAPACK_ctfsm LAPACK_GLOBAL(ctfsm,CTFSM)\n#define LAPACK_dtfttp LAPACK_GLOBAL(dtfttp,DTFTTP)\n#define LAPACK_stfttp LAPACK_GLOBAL(stfttp,STFTTP)\n#define LAPACK_ztfttp LAPACK_GLOBAL(ztfttp,ZTFTTP)\n#define LAPACK_ctfttp LAPACK_GLOBAL(ctfttp,CTFTTP)\n#define LAPACK_dtfttr LAPACK_GLOBAL(dtfttr,DTFTTR)\n#define LAPACK_stfttr LAPACK_GLOBAL(stfttr,STFTTR)\n#define LAPACK_ztfttr LAPACK_GLOBAL(ztfttr,ZTFTTR)\n#define LAPACK_ctfttr LAPACK_GLOBAL(ctfttr,CTFTTR)\n#define LAPACK_dtpttf LAPACK_GLOBAL(dtpttf,DTPTTF)\n#define LAPACK_stpttf LAPACK_GLOBAL(stpttf,STPTTF)\n#define LAPACK_ztpttf LAPACK_GLOBAL(ztpttf,ZTPTTF)\n#define LAPACK_ctpttf LAPACK_GLOBAL(ctpttf,CTPTTF)\n#define LAPACK_dtpttr LAPACK_GLOBAL(dtpttr,DTPTTR)\n#define LAPACK_stpttr LAPACK_GLOBAL(stpttr,STPTTR)\n#define LAPACK_ztpttr LAPACK_GLOBAL(ztpttr,ZTPTTR)\n#define LAPACK_ctpttr LAPACK_GLOBAL(ctpttr,CTPTTR)\n#define LAPACK_dtrttf LAPACK_GLOBAL(dtrttf,DTRTTF)\n#define LAPACK_strttf LAPACK_GLOBAL(strttf,STRTTF)\n#define LAPACK_ztrttf LAPACK_GLOBAL(ztrttf,ZTRTTF)\n#define LAPACK_ctrttf LAPACK_GLOBAL(ctrttf,CTRTTF)\n#define LAPACK_dtrttp LAPACK_GLOBAL(dtrttp,DTRTTP)\n#define LAPACK_strttp LAPACK_GLOBAL(strttp,STRTTP)\n#define LAPACK_ztrttp LAPACK_GLOBAL(ztrttp,ZTRTTP)\n#define LAPACK_ctrttp LAPACK_GLOBAL(ctrttp,CTRTTP)\n#define LAPACK_sgeqrfp LAPACK_GLOBAL(sgeqrfp,SGEQRFP)\n#define LAPACK_dgeqrfp LAPACK_GLOBAL(dgeqrfp,DGEQRFP)\n#define LAPACK_cgeqrfp LAPACK_GLOBAL(cgeqrfp,CGEQRFP)\n#define LAPACK_zgeqrfp LAPACK_GLOBAL(zgeqrfp,ZGEQRFP)\n#define LAPACK_clacgv LAPACK_GLOBAL(clacgv,CLACGV)\n#define LAPACK_zlacgv LAPACK_GLOBAL(zlacgv,ZLACGV)\n#define LAPACK_slarnv LAPACK_GLOBAL(slarnv,SLARNV)\n#define LAPACK_dlarnv LAPACK_GLOBAL(dlarnv,DLARNV)\n#define LAPACK_clarnv LAPACK_GLOBAL(clarnv,CLARNV)\n#define LAPACK_zlarnv LAPACK_GLOBAL(zlarnv,ZLARNV)\n#define LAPACK_sgeqr2 LAPACK_GLOBAL(sgeqr2,SGEQR2)\n#define LAPACK_dgeqr2 LAPACK_GLOBAL(dgeqr2,DGEQR2)\n#define LAPACK_cgeqr2 LAPACK_GLOBAL(cgeqr2,CGEQR2)\n#define LAPACK_zgeqr2 LAPACK_GLOBAL(zgeqr2,ZGEQR2)\n#define LAPACK_slacpy LAPACK_GLOBAL(slacpy,SLACPY)\n#define LAPACK_dlacpy LAPACK_GLOBAL(dlacpy,DLACPY)\n#define LAPACK_clacpy LAPACK_GLOBAL(clacpy,CLACPY)\n#define LAPACK_zlacpy LAPACK_GLOBAL(zlacpy,ZLACPY)\n#define LAPACK_sgetf2 LAPACK_GLOBAL(sgetf2,SGETF2)\n#define LAPACK_dgetf2 LAPACK_GLOBAL(dgetf2,DGETF2)\n#define LAPACK_cgetf2 LAPACK_GLOBAL(cgetf2,CGETF2)\n#define LAPACK_zgetf2 LAPACK_GLOBAL(zgetf2,ZGETF2)\n#define LAPACK_slaswp LAPACK_GLOBAL(slaswp,SLASWP)\n#define LAPACK_dlaswp LAPACK_GLOBAL(dlaswp,DLASWP)\n#define LAPACK_claswp LAPACK_GLOBAL(claswp,CLASWP)\n#define LAPACK_zlaswp LAPACK_GLOBAL(zlaswp,ZLASWP)\n#define LAPACK_slange LAPACK_GLOBAL(slange,SLANGE)\n#define LAPACK_dlange LAPACK_GLOBAL(dlange,DLANGE)\n#define LAPACK_clange LAPACK_GLOBAL(clange,CLANGE)\n#define LAPACK_zlange LAPACK_GLOBAL(zlange,ZLANGE)\n#define LAPACK_clanhe LAPACK_GLOBAL(clanhe,CLANHE)\n#define LAPACK_zlanhe LAPACK_GLOBAL(zlanhe,ZLANHE)\n#define LAPACK_slansy LAPACK_GLOBAL(slansy,SLANSY)\n#define LAPACK_dlansy LAPACK_GLOBAL(dlansy,DLANSY)\n#define LAPACK_clansy LAPACK_GLOBAL(clansy,CLANSY)\n#define LAPACK_zlansy LAPACK_GLOBAL(zlansy,ZLANSY)\n#define LAPACK_slantr LAPACK_GLOBAL(slantr,SLANTR)\n#define LAPACK_dlantr LAPACK_GLOBAL(dlantr,DLANTR)\n#define LAPACK_clantr LAPACK_GLOBAL(clantr,CLANTR)\n#define LAPACK_zlantr LAPACK_GLOBAL(zlantr,ZLANTR)\n#define LAPACK_slamch LAPACK_GLOBAL(slamch,SLAMCH)\n#define LAPACK_dlamch LAPACK_GLOBAL(dlamch,DLAMCH)\n#define LAPACK_sgelq2 LAPACK_GLOBAL(sgelq2,SGELQ2)\n#define LAPACK_dgelq2 LAPACK_GLOBAL(dgelq2,DGELQ2)\n#define LAPACK_cgelq2 LAPACK_GLOBAL(cgelq2,CGELQ2)\n#define LAPACK_zgelq2 LAPACK_GLOBAL(zgelq2,ZGELQ2)\n#define LAPACK_slarfb LAPACK_GLOBAL(slarfb,SLARFB)\n#define LAPACK_dlarfb LAPACK_GLOBAL(dlarfb,DLARFB)\n#define LAPACK_clarfb LAPACK_GLOBAL(clarfb,CLARFB)\n#define LAPACK_zlarfb LAPACK_GLOBAL(zlarfb,ZLARFB)\n#define LAPACK_slarfg LAPACK_GLOBAL(slarfg,SLARFG)\n#define LAPACK_dlarfg LAPACK_GLOBAL(dlarfg,DLARFG)\n#define LAPACK_clarfg LAPACK_GLOBAL(clarfg,CLARFG)\n#define LAPACK_zlarfg LAPACK_GLOBAL(zlarfg,ZLARFG)\n#define LAPACK_slarft LAPACK_GLOBAL(slarft,SLARFT)\n#define LAPACK_dlarft LAPACK_GLOBAL(dlarft,DLARFT)\n#define LAPACK_clarft LAPACK_GLOBAL(clarft,CLARFT)\n#define LAPACK_zlarft LAPACK_GLOBAL(zlarft,ZLARFT)\n#define LAPACK_slarfx LAPACK_GLOBAL(slarfx,SLARFX)\n#define LAPACK_dlarfx LAPACK_GLOBAL(dlarfx,DLARFX)\n#define LAPACK_clarfx LAPACK_GLOBAL(clarfx,CLARFX)\n#define LAPACK_zlarfx LAPACK_GLOBAL(zlarfx,ZLARFX)\n#define LAPACK_slatms LAPACK_GLOBAL(slatms,SLATMS)\n#define LAPACK_dlatms LAPACK_GLOBAL(dlatms,DLATMS)\n#define LAPACK_clatms LAPACK_GLOBAL(clatms,CLATMS)\n#define LAPACK_zlatms LAPACK_GLOBAL(zlatms,ZLATMS)\n#define LAPACK_slag2d LAPACK_GLOBAL(slag2d,SLAG2D)\n#define LAPACK_dlag2s LAPACK_GLOBAL(dlag2s,DLAG2S)\n#define LAPACK_clag2z LAPACK_GLOBAL(clag2z,CLAG2Z)\n#define LAPACK_zlag2c LAPACK_GLOBAL(zlag2c,ZLAG2C)\n#define LAPACK_slauum LAPACK_GLOBAL(slauum,SLAUUM)\n#define LAPACK_dlauum LAPACK_GLOBAL(dlauum,DLAUUM)\n#define LAPACK_clauum LAPACK_GLOBAL(clauum,CLAUUM)\n#define LAPACK_zlauum LAPACK_GLOBAL(zlauum,ZLAUUM)\n#define LAPACK_slagge LAPACK_GLOBAL(slagge,SLAGGE)\n#define LAPACK_dlagge LAPACK_GLOBAL(dlagge,DLAGGE)\n#define LAPACK_clagge LAPACK_GLOBAL(clagge,CLAGGE)\n#define LAPACK_zlagge LAPACK_GLOBAL(zlagge,ZLAGGE)\n#define LAPACK_slaset LAPACK_GLOBAL(slaset,SLASET)\n#define LAPACK_dlaset LAPACK_GLOBAL(dlaset,DLASET)\n#define LAPACK_claset LAPACK_GLOBAL(claset,CLASET)\n#define LAPACK_zlaset LAPACK_GLOBAL(zlaset,ZLASET)\n#define LAPACK_slasrt LAPACK_GLOBAL(slasrt,SLASRT)\n#define LAPACK_dlasrt LAPACK_GLOBAL(dlasrt,DLASRT)\n#define LAPACK_slagsy LAPACK_GLOBAL(slagsy,SLAGSY)\n#define LAPACK_dlagsy LAPACK_GLOBAL(dlagsy,DLAGSY)\n#define LAPACK_clagsy LAPACK_GLOBAL(clagsy,CLAGSY)\n#define LAPACK_zlagsy LAPACK_GLOBAL(zlagsy,ZLAGSY)\n#define LAPACK_claghe LAPACK_GLOBAL(claghe,CLAGHE)\n#define LAPACK_zlaghe LAPACK_GLOBAL(zlaghe,ZLAGHE)\n#define LAPACK_slapmr LAPACK_GLOBAL(slapmr,SLAPMR)\n#define LAPACK_dlapmr LAPACK_GLOBAL(dlapmr,DLAPMR)\n#define LAPACK_clapmr LAPACK_GLOBAL(clapmr,CLAPMR)\n#define LAPACK_zlapmr LAPACK_GLOBAL(zlapmr,ZLAPMR)\n#define LAPACK_slapy2 LAPACK_GLOBAL(slapy2,SLAPY2)\n#define LAPACK_dlapy2 LAPACK_GLOBAL(dlapy2,DLAPY2)\n#define LAPACK_slapy3 LAPACK_GLOBAL(slapy3,SLAPY3)\n#define LAPACK_dlapy3 LAPACK_GLOBAL(dlapy3,DLAPY3)\n#define LAPACK_slartgp LAPACK_GLOBAL(slartgp,SLARTGP)\n#define LAPACK_dlartgp LAPACK_GLOBAL(dlartgp,DLARTGP)\n#define LAPACK_slartgs LAPACK_GLOBAL(slartgs,SLARTGS)\n#define LAPACK_dlartgs LAPACK_GLOBAL(dlartgs,DLARTGS)\n// LAPACK 3.3.0\n#define LAPACK_cbbcsd LAPACK_GLOBAL(cbbcsd,CBBCSD)\n#define LAPACK_cheswapr LAPACK_GLOBAL(cheswapr,CHESWAPR)\n#define LAPACK_chetri2 LAPACK_GLOBAL(chetri2,CHETRI2)\n#define LAPACK_chetri2x LAPACK_GLOBAL(chetri2x,CHETRI2X)\n#define LAPACK_chetrs2 LAPACK_GLOBAL(chetrs2,CHETRS2)\n#define LAPACK_csyconv LAPACK_GLOBAL(csyconv,CSYCONV)\n#define LAPACK_csyswapr LAPACK_GLOBAL(csyswapr,CSYSWAPR)\n#define LAPACK_csytri2 LAPACK_GLOBAL(csytri2,CSYTRI2)\n#define LAPACK_csytri2x LAPACK_GLOBAL(csytri2x,CSYTRI2X)\n#define LAPACK_csytrs2 LAPACK_GLOBAL(csytrs2,CSYTRS2)\n#define LAPACK_cunbdb LAPACK_GLOBAL(cunbdb,CUNBDB)\n#define LAPACK_cuncsd LAPACK_GLOBAL(cuncsd,CUNCSD)\n#define LAPACK_dbbcsd LAPACK_GLOBAL(dbbcsd,DBBCSD)\n#define LAPACK_dorbdb LAPACK_GLOBAL(dorbdb,DORBDB)\n#define LAPACK_dorcsd LAPACK_GLOBAL(dorcsd,DORCSD)\n#define LAPACK_dsyconv LAPACK_GLOBAL(dsyconv,DSYCONV)\n#define LAPACK_dsyswapr LAPACK_GLOBAL(dsyswapr,DSYSWAPR)\n#define LAPACK_dsytri2 LAPACK_GLOBAL(dsytri2,DSYTRI2)\n#define LAPACK_dsytri2x LAPACK_GLOBAL(dsytri2x,DSYTRI2X)\n#define LAPACK_dsytrs2 LAPACK_GLOBAL(dsytrs2,DSYTRS2)\n#define LAPACK_sbbcsd LAPACK_GLOBAL(sbbcsd,SBBCSD)\n#define LAPACK_sorbdb LAPACK_GLOBAL(sorbdb,SORBDB)\n#define LAPACK_sorcsd LAPACK_GLOBAL(sorcsd,SORCSD)\n#define LAPACK_ssyconv LAPACK_GLOBAL(ssyconv,SSYCONV)\n#define LAPACK_ssyswapr LAPACK_GLOBAL(ssyswapr,SSYSWAPR)\n#define LAPACK_ssytri2 LAPACK_GLOBAL(ssytri2,SSYTRI2)\n#define LAPACK_ssytri2x LAPACK_GLOBAL(ssytri2x,SSYTRI2X)\n#define LAPACK_ssytrs2 LAPACK_GLOBAL(ssytrs2,SSYTRS2)\n#define LAPACK_zbbcsd LAPACK_GLOBAL(zbbcsd,ZBBCSD)\n#define LAPACK_zheswapr LAPACK_GLOBAL(zheswapr,ZHESWAPR)\n#define LAPACK_zhetri2 LAPACK_GLOBAL(zhetri2,ZHETRI2)\n#define LAPACK_zhetri2x LAPACK_GLOBAL(zhetri2x,ZHETRI2X)\n#define LAPACK_zhetrs2 LAPACK_GLOBAL(zhetrs2,ZHETRS2)\n#define LAPACK_zsyconv LAPACK_GLOBAL(zsyconv,ZSYCONV)\n#define LAPACK_zsyswapr LAPACK_GLOBAL(zsyswapr,ZSYSWAPR)\n#define LAPACK_zsytri2 LAPACK_GLOBAL(zsytri2,ZSYTRI2)\n#define LAPACK_zsytri2x LAPACK_GLOBAL(zsytri2x,ZSYTRI2X)\n#define LAPACK_zsytrs2 LAPACK_GLOBAL(zsytrs2,ZSYTRS2)\n#define LAPACK_zunbdb LAPACK_GLOBAL(zunbdb,ZUNBDB)\n#define LAPACK_zuncsd LAPACK_GLOBAL(zuncsd,ZUNCSD)\n// LAPACK 3.4.0\n#define LAPACK_sgemqrt LAPACK_GLOBAL(sgemqrt,SGEMQRT)\n#define LAPACK_dgemqrt LAPACK_GLOBAL(dgemqrt,DGEMQRT)\n#define LAPACK_cgemqrt LAPACK_GLOBAL(cgemqrt,CGEMQRT)\n#define LAPACK_zgemqrt LAPACK_GLOBAL(zgemqrt,ZGEMQRT)\n#define LAPACK_sgeqrt LAPACK_GLOBAL(sgeqrt,SGEQRT)\n#define LAPACK_dgeqrt LAPACK_GLOBAL(dgeqrt,DGEQRT)\n#define LAPACK_cgeqrt LAPACK_GLOBAL(cgeqrt,CGEQRT)\n#define LAPACK_zgeqrt LAPACK_GLOBAL(zgeqrt,ZGEQRT)\n#define LAPACK_sgeqrt2 LAPACK_GLOBAL(sgeqrt2,SGEQRT2)\n#define LAPACK_dgeqrt2 LAPACK_GLOBAL(dgeqrt2,DGEQRT2)\n#define LAPACK_cgeqrt2 LAPACK_GLOBAL(cgeqrt2,CGEQRT2)\n#define LAPACK_zgeqrt2 LAPACK_GLOBAL(zgeqrt2,ZGEQRT2)\n#define LAPACK_sgeqrt3 LAPACK_GLOBAL(sgeqrt3,SGEQRT3)\n#define LAPACK_dgeqrt3 LAPACK_GLOBAL(dgeqrt3,DGEQRT3)\n#define LAPACK_cgeqrt3 LAPACK_GLOBAL(cgeqrt3,CGEQRT3)\n#define LAPACK_zgeqrt3 LAPACK_GLOBAL(zgeqrt3,ZGEQRT3)\n#define LAPACK_stpmqrt LAPACK_GLOBAL(stpmqrt,STPMQRT)\n#define LAPACK_dtpmqrt LAPACK_GLOBAL(dtpmqrt,DTPMQRT)\n#define LAPACK_ctpmqrt LAPACK_GLOBAL(ctpmqrt,CTPMQRT)\n#define LAPACK_ztpmqrt LAPACK_GLOBAL(ztpmqrt,ZTPMQRT)\n#define LAPACK_dtpqrt LAPACK_GLOBAL(dtpqrt,DTPQRT)\n#define LAPACK_ctpqrt LAPACK_GLOBAL(ctpqrt,CTPQRT)\n#define LAPACK_ztpqrt LAPACK_GLOBAL(ztpqrt,ZTPQRT)\n#define LAPACK_stpqrt2 LAPACK_GLOBAL(stpqrt2,STPQRT2)\n#define LAPACK_dtpqrt2 LAPACK_GLOBAL(dtpqrt2,DTPQRT2)\n#define LAPACK_ctpqrt2 LAPACK_GLOBAL(ctpqrt2,CTPQRT2)\n#define LAPACK_ztpqrt2 LAPACK_GLOBAL(ztpqrt2,ZTPQRT2)\n#define LAPACK_stprfb LAPACK_GLOBAL(stprfb,STPRFB)\n#define LAPACK_dtprfb LAPACK_GLOBAL(dtprfb,DTPRFB)\n#define LAPACK_ctprfb LAPACK_GLOBAL(ctprfb,CTPRFB)\n#define LAPACK_ztprfb LAPACK_GLOBAL(ztprfb,ZTPRFB)\n// LAPACK 3.X.X\n#define LAPACK_csyr LAPACK_GLOBAL(csyr,CSYR)\n#define LAPACK_zsyr LAPACK_GLOBAL(zsyr,ZSYR)\n\n\nvoid LAPACK_sgetrf( lapack_int* m, lapack_int* n, float* a, lapack_int* lda,\n                    lapack_int* ipiv, lapack_int *info );\nvoid LAPACK_dgetrf( lapack_int* m, lapack_int* n, double* a, lapack_int* lda,\n                    lapack_int* ipiv, lapack_int *info );\nvoid LAPACK_cgetrf( lapack_int* m, lapack_int* n, lapack_complex_float* a,\n                    lapack_int* lda, lapack_int* ipiv, lapack_int *info );\nvoid LAPACK_zgetrf( lapack_int* m, lapack_int* n, lapack_complex_double* a,\n                    lapack_int* lda, lapack_int* ipiv, lapack_int *info );\nvoid LAPACK_sgbtrf( lapack_int* m, lapack_int* n, lapack_int* kl,\n                    lapack_int* ku, float* ab, lapack_int* ldab,\n                    lapack_int* ipiv, lapack_int *info );\nvoid LAPACK_dgbtrf( lapack_int* m, lapack_int* n, lapack_int* kl,\n                    lapack_int* ku, double* ab, lapack_int* ldab,\n                    lapack_int* ipiv, lapack_int *info );\nvoid LAPACK_cgbtrf( lapack_int* m, lapack_int* n, lapack_int* kl,\n                    lapack_int* ku, lapack_complex_float* ab, lapack_int* ldab,\n                    lapack_int* ipiv, lapack_int *info );\nvoid LAPACK_zgbtrf( lapack_int* m, lapack_int* n, lapack_int* kl,\n                    lapack_int* ku, lapack_complex_double* ab, lapack_int* ldab,\n                    lapack_int* ipiv, lapack_int *info );\nvoid LAPACK_sgttrf( lapack_int* n, float* dl, float* d, float* du, float* du2,\n                    lapack_int* ipiv, lapack_int *info );\nvoid LAPACK_dgttrf( lapack_int* n, double* dl, double* d, double* du,\n                    double* du2, lapack_int* ipiv, lapack_int *info );\nvoid LAPACK_cgttrf( lapack_int* n, lapack_complex_float* dl,\n                    lapack_complex_float* d, lapack_complex_float* du,\n                    lapack_complex_float* du2, lapack_int* ipiv,\n                    lapack_int *info );\nvoid LAPACK_zgttrf( lapack_int* n, lapack_complex_double* dl,\n                    lapack_complex_double* d, lapack_complex_double* du,\n                    lapack_complex_double* du2, lapack_int* ipiv,\n                    lapack_int *info );\nvoid LAPACK_spotrf( char* uplo, lapack_int* n, float* a, lapack_int* lda,\n                    lapack_int *info );\nvoid LAPACK_dpotrf( char* uplo, lapack_int* n, double* a, lapack_int* lda,\n                    lapack_int *info );\nvoid LAPACK_cpotrf( char* uplo, lapack_int* n, lapack_complex_float* a,\n                    lapack_int* lda, lapack_int *info );\nvoid LAPACK_zpotrf( char* uplo, lapack_int* n, lapack_complex_double* a,\n                    lapack_int* lda, lapack_int *info );\nvoid LAPACK_dpstrf( char* uplo, lapack_int* n, double* a, lapack_int* lda,\n                    lapack_int* piv, lapack_int* rank, double* tol,\n                    double* work, lapack_int *info );\nvoid LAPACK_spstrf( char* uplo, lapack_int* n, float* a, lapack_int* lda,\n                    lapack_int* piv, lapack_int* rank, float* tol, float* work,\n                    lapack_int *info );\nvoid LAPACK_zpstrf( char* uplo, lapack_int* n, lapack_complex_double* a,\n                    lapack_int* lda, lapack_int* piv, lapack_int* rank,\n                    double* tol, double* work, lapack_int *info );\nvoid LAPACK_cpstrf( char* uplo, lapack_int* n, lapack_complex_float* a,\n                    lapack_int* lda, lapack_int* piv, lapack_int* rank,\n                    float* tol, float* work, lapack_int *info );\nvoid LAPACK_dpftrf( char* transr, char* uplo, lapack_int* n, double* a,\n                    lapack_int *info );\nvoid LAPACK_spftrf( char* transr, char* uplo, lapack_int* n, float* a,\n                    lapack_int *info );\nvoid LAPACK_zpftrf( char* transr, char* uplo, lapack_int* n,\n                    lapack_complex_double* a, lapack_int *info );\nvoid LAPACK_cpftrf( char* transr, char* uplo, lapack_int* n,\n                    lapack_complex_float* a, lapack_int *info );\nvoid LAPACK_spptrf( char* uplo, lapack_int* n, float* ap, lapack_int *info );\nvoid LAPACK_dpptrf( char* uplo, lapack_int* n, double* ap, lapack_int *info );\nvoid LAPACK_cpptrf( char* uplo, lapack_int* n, lapack_complex_float* ap,\n                    lapack_int *info );\nvoid LAPACK_zpptrf( char* uplo, lapack_int* n, lapack_complex_double* ap,\n                    lapack_int *info );\nvoid LAPACK_spbtrf( char* uplo, lapack_int* n, lapack_int* kd, float* ab,\n                    lapack_int* ldab, lapack_int *info );\nvoid LAPACK_dpbtrf( char* uplo, lapack_int* n, lapack_int* kd, double* ab,\n                    lapack_int* ldab, lapack_int *info );\nvoid LAPACK_cpbtrf( char* uplo, lapack_int* n, lapack_int* kd,\n                    lapack_complex_float* ab, lapack_int* ldab,\n                    lapack_int *info );\nvoid LAPACK_zpbtrf( char* uplo, lapack_int* n, lapack_int* kd,\n                    lapack_complex_double* ab, lapack_int* ldab,\n                    lapack_int *info );\nvoid LAPACK_spttrf( lapack_int* n, float* d, float* e, lapack_int *info );\nvoid LAPACK_dpttrf( lapack_int* n, double* d, double* e, lapack_int *info );\nvoid LAPACK_cpttrf( lapack_int* n, float* d, lapack_complex_float* e,\n                    lapack_int *info );\nvoid LAPACK_zpttrf( lapack_int* n, double* d, lapack_complex_double* e,\n                    lapack_int *info );\nvoid LAPACK_ssytrf( char* uplo, lapack_int* n, float* a, lapack_int* lda,\n                    lapack_int* ipiv, float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_dsytrf( char* uplo, lapack_int* n, double* a, lapack_int* lda,\n                    lapack_int* ipiv, double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_csytrf( char* uplo, lapack_int* n, lapack_complex_float* a,\n                    lapack_int* lda, lapack_int* ipiv,\n                    lapack_complex_float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_zsytrf( char* uplo, lapack_int* n, lapack_complex_double* a,\n                    lapack_int* lda, lapack_int* ipiv,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_chetrf( char* uplo, lapack_int* n, lapack_complex_float* a,\n                    lapack_int* lda, lapack_int* ipiv,\n                    lapack_complex_float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_zhetrf( char* uplo, lapack_int* n, lapack_complex_double* a,\n                    lapack_int* lda, lapack_int* ipiv,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_ssptrf( char* uplo, lapack_int* n, float* ap, lapack_int* ipiv,\n                    lapack_int *info );\nvoid LAPACK_dsptrf( char* uplo, lapack_int* n, double* ap, lapack_int* ipiv,\n                    lapack_int *info );\nvoid LAPACK_csptrf( char* uplo, lapack_int* n, lapack_complex_float* ap,\n                    lapack_int* ipiv, lapack_int *info );\nvoid LAPACK_zsptrf( char* uplo, lapack_int* n, lapack_complex_double* ap,\n                    lapack_int* ipiv, lapack_int *info );\nvoid LAPACK_chptrf( char* uplo, lapack_int* n, lapack_complex_float* ap,\n                    lapack_int* ipiv, lapack_int *info );\nvoid LAPACK_zhptrf( char* uplo, lapack_int* n, lapack_complex_double* ap,\n                    lapack_int* ipiv, lapack_int *info );\nvoid LAPACK_sgetrs( char* trans, lapack_int* n, lapack_int* nrhs,\n                    const float* a, lapack_int* lda, const lapack_int* ipiv,\n                    float* b, lapack_int* ldb, lapack_int *info );\nvoid LAPACK_dgetrs( char* trans, lapack_int* n, lapack_int* nrhs,\n                    const double* a, lapack_int* lda, const lapack_int* ipiv,\n                    double* b, lapack_int* ldb, lapack_int *info );\nvoid LAPACK_cgetrs( char* trans, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_float* a, lapack_int* lda,\n                    const lapack_int* ipiv, lapack_complex_float* b,\n                    lapack_int* ldb, lapack_int *info );\nvoid LAPACK_zgetrs( char* trans, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_double* a, lapack_int* lda,\n                    const lapack_int* ipiv, lapack_complex_double* b,\n                    lapack_int* ldb, lapack_int *info );\nvoid LAPACK_sgbtrs( char* trans, lapack_int* n, lapack_int* kl, lapack_int* ku,\n                    lapack_int* nrhs, const float* ab, lapack_int* ldab,\n                    const lapack_int* ipiv, float* b, lapack_int* ldb,\n                    lapack_int *info );\nvoid LAPACK_dgbtrs( char* trans, lapack_int* n, lapack_int* kl, lapack_int* ku,\n                    lapack_int* nrhs, const double* ab, lapack_int* ldab,\n                    const lapack_int* ipiv, double* b, lapack_int* ldb,\n                    lapack_int *info );\nvoid LAPACK_cgbtrs( char* trans, lapack_int* n, lapack_int* kl, lapack_int* ku,\n                    lapack_int* nrhs, const lapack_complex_float* ab,\n                    lapack_int* ldab, const lapack_int* ipiv,\n                    lapack_complex_float* b, lapack_int* ldb,\n                    lapack_int *info );\nvoid LAPACK_zgbtrs( char* trans, lapack_int* n, lapack_int* kl, lapack_int* ku,\n                    lapack_int* nrhs, const lapack_complex_double* ab,\n                    lapack_int* ldab, const lapack_int* ipiv,\n                    lapack_complex_double* b, lapack_int* ldb,\n                    lapack_int *info );\nvoid LAPACK_sgttrs( char* trans, lapack_int* n, lapack_int* nrhs,\n                    const float* dl, const float* d, const float* du,\n                    const float* du2, const lapack_int* ipiv, float* b,\n                    lapack_int* ldb, lapack_int *info );\nvoid LAPACK_dgttrs( char* trans, lapack_int* n, lapack_int* nrhs,\n                    const double* dl, const double* d, const double* du,\n                    const double* du2, const lapack_int* ipiv, double* b,\n                    lapack_int* ldb, lapack_int *info );\nvoid LAPACK_cgttrs( char* trans, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_float* dl,\n                    const lapack_complex_float* d,\n                    const lapack_complex_float* du,\n                    const lapack_complex_float* du2, const lapack_int* ipiv,\n                    lapack_complex_float* b, lapack_int* ldb,\n                    lapack_int *info );\nvoid LAPACK_zgttrs( char* trans, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_double* dl,\n                    const lapack_complex_double* d,\n                    const lapack_complex_double* du,\n                    const lapack_complex_double* du2, const lapack_int* ipiv,\n                    lapack_complex_double* b, lapack_int* ldb,\n                    lapack_int *info );\nvoid LAPACK_spotrs( char* uplo, lapack_int* n, lapack_int* nrhs, const float* a,\n                    lapack_int* lda, float* b, lapack_int* ldb,\n                    lapack_int *info );\nvoid LAPACK_dpotrs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const double* a, lapack_int* lda, double* b,\n                    lapack_int* ldb, lapack_int *info );\nvoid LAPACK_cpotrs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_float* a, lapack_int* lda,\n                    lapack_complex_float* b, lapack_int* ldb,\n                    lapack_int *info );\nvoid LAPACK_zpotrs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_double* a, lapack_int* lda,\n                    lapack_complex_double* b, lapack_int* ldb,\n                    lapack_int *info );\nvoid LAPACK_dpftrs( char* transr, char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const double* a, double* b, lapack_int* ldb,\n                    lapack_int *info );\nvoid LAPACK_spftrs( char* transr, char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const float* a, float* b, lapack_int* ldb,\n                    lapack_int *info );\nvoid LAPACK_zpftrs( char* transr, char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_double* a, lapack_complex_double* b,\n                    lapack_int* ldb, lapack_int *info );\nvoid LAPACK_cpftrs( char* transr, char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_float* a, lapack_complex_float* b,\n                    lapack_int* ldb, lapack_int *info );\nvoid LAPACK_spptrs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const float* ap, float* b, lapack_int* ldb,\n                    lapack_int *info );\nvoid LAPACK_dpptrs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const double* ap, double* b, lapack_int* ldb,\n                    lapack_int *info );\nvoid LAPACK_cpptrs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_float* ap, lapack_complex_float* b,\n                    lapack_int* ldb, lapack_int *info );\nvoid LAPACK_zpptrs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_double* ap, lapack_complex_double* b,\n                    lapack_int* ldb, lapack_int *info );\nvoid LAPACK_spbtrs( char* uplo, lapack_int* n, lapack_int* kd, lapack_int* nrhs,\n                    const float* ab, lapack_int* ldab, float* b,\n                    lapack_int* ldb, lapack_int *info );\nvoid LAPACK_dpbtrs( char* uplo, lapack_int* n, lapack_int* kd, lapack_int* nrhs,\n                    const double* ab, lapack_int* ldab, double* b,\n                    lapack_int* ldb, lapack_int *info );\nvoid LAPACK_cpbtrs( char* uplo, lapack_int* n, lapack_int* kd, lapack_int* nrhs,\n                    const lapack_complex_float* ab, lapack_int* ldab,\n                    lapack_complex_float* b, lapack_int* ldb,\n                    lapack_int *info );\nvoid LAPACK_zpbtrs( char* uplo, lapack_int* n, lapack_int* kd, lapack_int* nrhs,\n                    const lapack_complex_double* ab, lapack_int* ldab,\n                    lapack_complex_double* b, lapack_int* ldb,\n                    lapack_int *info );\nvoid LAPACK_spttrs( lapack_int* n, lapack_int* nrhs, const float* d,\n                    const float* e, float* b, lapack_int* ldb,\n                    lapack_int *info );\nvoid LAPACK_dpttrs( lapack_int* n, lapack_int* nrhs, const double* d,\n                    const double* e, double* b, lapack_int* ldb,\n                    lapack_int *info );\nvoid LAPACK_cpttrs( char* uplo, lapack_int* n, lapack_int* nrhs, const float* d,\n                    const lapack_complex_float* e, lapack_complex_float* b,\n                    lapack_int* ldb, lapack_int *info );\nvoid LAPACK_zpttrs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const double* d, const lapack_complex_double* e,\n                    lapack_complex_double* b, lapack_int* ldb,\n                    lapack_int *info );\nvoid LAPACK_ssytrs( char* uplo, lapack_int* n, lapack_int* nrhs, const float* a,\n                    lapack_int* lda, const lapack_int* ipiv, float* b,\n                    lapack_int* ldb, lapack_int *info );\nvoid LAPACK_dsytrs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const double* a, lapack_int* lda, const lapack_int* ipiv,\n                    double* b, lapack_int* ldb, lapack_int *info );\nvoid LAPACK_csytrs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_float* a, lapack_int* lda,\n                    const lapack_int* ipiv, lapack_complex_float* b,\n                    lapack_int* ldb, lapack_int *info );\nvoid LAPACK_zsytrs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_double* a, lapack_int* lda,\n                    const lapack_int* ipiv, lapack_complex_double* b,\n                    lapack_int* ldb, lapack_int *info );\nvoid LAPACK_chetrs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_float* a, lapack_int* lda,\n                    const lapack_int* ipiv, lapack_complex_float* b,\n                    lapack_int* ldb, lapack_int *info );\nvoid LAPACK_zhetrs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_double* a, lapack_int* lda,\n                    const lapack_int* ipiv, lapack_complex_double* b,\n                    lapack_int* ldb, lapack_int *info );\nvoid LAPACK_ssptrs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const float* ap, const lapack_int* ipiv, float* b,\n                    lapack_int* ldb, lapack_int *info );\nvoid LAPACK_dsptrs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const double* ap, const lapack_int* ipiv, double* b,\n                    lapack_int* ldb, lapack_int *info );\nvoid LAPACK_csptrs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_float* ap, const lapack_int* ipiv,\n                    lapack_complex_float* b, lapack_int* ldb,\n                    lapack_int *info );\nvoid LAPACK_zsptrs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_double* ap, const lapack_int* ipiv,\n                    lapack_complex_double* b, lapack_int* ldb,\n                    lapack_int *info );\nvoid LAPACK_chptrs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_float* ap, const lapack_int* ipiv,\n                    lapack_complex_float* b, lapack_int* ldb,\n                    lapack_int *info );\nvoid LAPACK_zhptrs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_double* ap, const lapack_int* ipiv,\n                    lapack_complex_double* b, lapack_int* ldb,\n                    lapack_int *info );\nvoid LAPACK_strtrs( char* uplo, char* trans, char* diag, lapack_int* n,\n                    lapack_int* nrhs, const float* a, lapack_int* lda, float* b,\n                    lapack_int* ldb, lapack_int *info );\nvoid LAPACK_dtrtrs( char* uplo, char* trans, char* diag, lapack_int* n,\n                    lapack_int* nrhs, const double* a, lapack_int* lda,\n                    double* b, lapack_int* ldb, lapack_int *info );\nvoid LAPACK_ctrtrs( char* uplo, char* trans, char* diag, lapack_int* n,\n                    lapack_int* nrhs, const lapack_complex_float* a,\n                    lapack_int* lda, lapack_complex_float* b, lapack_int* ldb,\n                    lapack_int *info );\nvoid LAPACK_ztrtrs( char* uplo, char* trans, char* diag, lapack_int* n,\n                    lapack_int* nrhs, const lapack_complex_double* a,\n                    lapack_int* lda, lapack_complex_double* b, lapack_int* ldb,\n                    lapack_int *info );\nvoid LAPACK_stptrs( char* uplo, char* trans, char* diag, lapack_int* n,\n                    lapack_int* nrhs, const float* ap, float* b,\n                    lapack_int* ldb, lapack_int *info );\nvoid LAPACK_dtptrs( char* uplo, char* trans, char* diag, lapack_int* n,\n                    lapack_int* nrhs, const double* ap, double* b,\n                    lapack_int* ldb, lapack_int *info );\nvoid LAPACK_ctptrs( char* uplo, char* trans, char* diag, lapack_int* n,\n                    lapack_int* nrhs, const lapack_complex_float* ap,\n                    lapack_complex_float* b, lapack_int* ldb,\n                    lapack_int *info );\nvoid LAPACK_ztptrs( char* uplo, char* trans, char* diag, lapack_int* n,\n                    lapack_int* nrhs, const lapack_complex_double* ap,\n                    lapack_complex_double* b, lapack_int* ldb,\n                    lapack_int *info );\nvoid LAPACK_stbtrs( char* uplo, char* trans, char* diag, lapack_int* n,\n                    lapack_int* kd, lapack_int* nrhs, const float* ab,\n                    lapack_int* ldab, float* b, lapack_int* ldb,\n                    lapack_int *info );\nvoid LAPACK_dtbtrs( char* uplo, char* trans, char* diag, lapack_int* n,\n                    lapack_int* kd, lapack_int* nrhs, const double* ab,\n                    lapack_int* ldab, double* b, lapack_int* ldb,\n                    lapack_int *info );\nvoid LAPACK_ctbtrs( char* uplo, char* trans, char* diag, lapack_int* n,\n                    lapack_int* kd, lapack_int* nrhs,\n                    const lapack_complex_float* ab, lapack_int* ldab,\n                    lapack_complex_float* b, lapack_int* ldb,\n                    lapack_int *info );\nvoid LAPACK_ztbtrs( char* uplo, char* trans, char* diag, lapack_int* n,\n                    lapack_int* kd, lapack_int* nrhs,\n                    const lapack_complex_double* ab, lapack_int* ldab,\n                    lapack_complex_double* b, lapack_int* ldb,\n                    lapack_int *info );\nvoid LAPACK_sgecon( char* norm, lapack_int* n, const float* a, lapack_int* lda,\n                    float* anorm, float* rcond, float* work, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_dgecon( char* norm, lapack_int* n, const double* a, lapack_int* lda,\n                    double* anorm, double* rcond, double* work,\n                    lapack_int* iwork, lapack_int *info );\nvoid LAPACK_cgecon( char* norm, lapack_int* n, const lapack_complex_float* a,\n                    lapack_int* lda, float* anorm, float* rcond,\n                    lapack_complex_float* work, float* rwork,\n                    lapack_int *info );\nvoid LAPACK_zgecon( char* norm, lapack_int* n, const lapack_complex_double* a,\n                    lapack_int* lda, double* anorm, double* rcond,\n                    lapack_complex_double* work, double* rwork,\n                    lapack_int *info );\nvoid LAPACK_sgbcon( char* norm, lapack_int* n, lapack_int* kl, lapack_int* ku,\n                    const float* ab, lapack_int* ldab, const lapack_int* ipiv,\n                    float* anorm, float* rcond, float* work, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_dgbcon( char* norm, lapack_int* n, lapack_int* kl, lapack_int* ku,\n                    const double* ab, lapack_int* ldab, const lapack_int* ipiv,\n                    double* anorm, double* rcond, double* work,\n                    lapack_int* iwork, lapack_int *info );\nvoid LAPACK_cgbcon( char* norm, lapack_int* n, lapack_int* kl, lapack_int* ku,\n                    const lapack_complex_float* ab, lapack_int* ldab,\n                    const lapack_int* ipiv, float* anorm, float* rcond,\n                    lapack_complex_float* work, float* rwork,\n                    lapack_int *info );\nvoid LAPACK_zgbcon( char* norm, lapack_int* n, lapack_int* kl, lapack_int* ku,\n                    const lapack_complex_double* ab, lapack_int* ldab,\n                    const lapack_int* ipiv, double* anorm, double* rcond,\n                    lapack_complex_double* work, double* rwork,\n                    lapack_int *info );\nvoid LAPACK_sgtcon( char* norm, lapack_int* n, const float* dl, const float* d,\n                    const float* du, const float* du2, const lapack_int* ipiv,\n                    float* anorm, float* rcond, float* work, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_dgtcon( char* norm, lapack_int* n, const double* dl,\n                    const double* d, const double* du, const double* du2,\n                    const lapack_int* ipiv, double* anorm, double* rcond,\n                    double* work, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_cgtcon( char* norm, lapack_int* n, const lapack_complex_float* dl,\n                    const lapack_complex_float* d,\n                    const lapack_complex_float* du,\n                    const lapack_complex_float* du2, const lapack_int* ipiv,\n                    float* anorm, float* rcond, lapack_complex_float* work,\n                    lapack_int *info );\nvoid LAPACK_zgtcon( char* norm, lapack_int* n, const lapack_complex_double* dl,\n                    const lapack_complex_double* d,\n                    const lapack_complex_double* du,\n                    const lapack_complex_double* du2, const lapack_int* ipiv,\n                    double* anorm, double* rcond, lapack_complex_double* work,\n                    lapack_int *info );\nvoid LAPACK_spocon( char* uplo, lapack_int* n, const float* a, lapack_int* lda,\n                    float* anorm, float* rcond, float* work, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_dpocon( char* uplo, lapack_int* n, const double* a, lapack_int* lda,\n                    double* anorm, double* rcond, double* work,\n                    lapack_int* iwork, lapack_int *info );\nvoid LAPACK_cpocon( char* uplo, lapack_int* n, const lapack_complex_float* a,\n                    lapack_int* lda, float* anorm, float* rcond,\n                    lapack_complex_float* work, float* rwork,\n                    lapack_int *info );\nvoid LAPACK_zpocon( char* uplo, lapack_int* n, const lapack_complex_double* a,\n                    lapack_int* lda, double* anorm, double* rcond,\n                    lapack_complex_double* work, double* rwork,\n                    lapack_int *info );\nvoid LAPACK_sppcon( char* uplo, lapack_int* n, const float* ap, float* anorm,\n                    float* rcond, float* work, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_dppcon( char* uplo, lapack_int* n, const double* ap, double* anorm,\n                    double* rcond, double* work, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_cppcon( char* uplo, lapack_int* n, const lapack_complex_float* ap,\n                    float* anorm, float* rcond, lapack_complex_float* work,\n                    float* rwork, lapack_int *info );\nvoid LAPACK_zppcon( char* uplo, lapack_int* n, const lapack_complex_double* ap,\n                    double* anorm, double* rcond, lapack_complex_double* work,\n                    double* rwork, lapack_int *info );\nvoid LAPACK_spbcon( char* uplo, lapack_int* n, lapack_int* kd, const float* ab,\n                    lapack_int* ldab, float* anorm, float* rcond, float* work,\n                    lapack_int* iwork, lapack_int *info );\nvoid LAPACK_dpbcon( char* uplo, lapack_int* n, lapack_int* kd, const double* ab,\n                    lapack_int* ldab, double* anorm, double* rcond,\n                    double* work, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_cpbcon( char* uplo, lapack_int* n, lapack_int* kd,\n                    const lapack_complex_float* ab, lapack_int* ldab,\n                    float* anorm, float* rcond, lapack_complex_float* work,\n                    float* rwork, lapack_int *info );\nvoid LAPACK_zpbcon( char* uplo, lapack_int* n, lapack_int* kd,\n                    const lapack_complex_double* ab, lapack_int* ldab,\n                    double* anorm, double* rcond, lapack_complex_double* work,\n                    double* rwork, lapack_int *info );\nvoid LAPACK_sptcon( lapack_int* n, const float* d, const float* e, float* anorm,\n                    float* rcond, float* work, lapack_int *info );\nvoid LAPACK_dptcon( lapack_int* n, const double* d, const double* e,\n                    double* anorm, double* rcond, double* work,\n                    lapack_int *info );\nvoid LAPACK_cptcon( lapack_int* n, const float* d,\n                    const lapack_complex_float* e, float* anorm, float* rcond,\n                    float* work, lapack_int *info );\nvoid LAPACK_zptcon( lapack_int* n, const double* d,\n                    const lapack_complex_double* e, double* anorm,\n                    double* rcond, double* work, lapack_int *info );\nvoid LAPACK_ssycon( char* uplo, lapack_int* n, const float* a, lapack_int* lda,\n                    const lapack_int* ipiv, float* anorm, float* rcond,\n                    float* work, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_dsycon( char* uplo, lapack_int* n, const double* a, lapack_int* lda,\n                    const lapack_int* ipiv, double* anorm, double* rcond,\n                    double* work, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_csycon( char* uplo, lapack_int* n, const lapack_complex_float* a,\n                    lapack_int* lda, const lapack_int* ipiv, float* anorm,\n                    float* rcond, lapack_complex_float* work,\n                    lapack_int *info );\nvoid LAPACK_zsycon( char* uplo, lapack_int* n, const lapack_complex_double* a,\n                    lapack_int* lda, const lapack_int* ipiv, double* anorm,\n                    double* rcond, lapack_complex_double* work,\n                    lapack_int *info );\nvoid LAPACK_checon( char* uplo, lapack_int* n, const lapack_complex_float* a,\n                    lapack_int* lda, const lapack_int* ipiv, float* anorm,\n                    float* rcond, lapack_complex_float* work,\n                    lapack_int *info );\nvoid LAPACK_zhecon( char* uplo, lapack_int* n, const lapack_complex_double* a,\n                    lapack_int* lda, const lapack_int* ipiv, double* anorm,\n                    double* rcond, lapack_complex_double* work,\n                    lapack_int *info );\nvoid LAPACK_sspcon( char* uplo, lapack_int* n, const float* ap,\n                    const lapack_int* ipiv, float* anorm, float* rcond,\n                    float* work, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_dspcon( char* uplo, lapack_int* n, const double* ap,\n                    const lapack_int* ipiv, double* anorm, double* rcond,\n                    double* work, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_cspcon( char* uplo, lapack_int* n, const lapack_complex_float* ap,\n                    const lapack_int* ipiv, float* anorm, float* rcond,\n                    lapack_complex_float* work, lapack_int *info );\nvoid LAPACK_zspcon( char* uplo, lapack_int* n, const lapack_complex_double* ap,\n                    const lapack_int* ipiv, double* anorm, double* rcond,\n                    lapack_complex_double* work, lapack_int *info );\nvoid LAPACK_chpcon( char* uplo, lapack_int* n, const lapack_complex_float* ap,\n                    const lapack_int* ipiv, float* anorm, float* rcond,\n                    lapack_complex_float* work, lapack_int *info );\nvoid LAPACK_zhpcon( char* uplo, lapack_int* n, const lapack_complex_double* ap,\n                    const lapack_int* ipiv, double* anorm, double* rcond,\n                    lapack_complex_double* work, lapack_int *info );\nvoid LAPACK_strcon( char* norm, char* uplo, char* diag, lapack_int* n,\n                    const float* a, lapack_int* lda, float* rcond, float* work,\n                    lapack_int* iwork, lapack_int *info );\nvoid LAPACK_dtrcon( char* norm, char* uplo, char* diag, lapack_int* n,\n                    const double* a, lapack_int* lda, double* rcond,\n                    double* work, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_ctrcon( char* norm, char* uplo, char* diag, lapack_int* n,\n                    const lapack_complex_float* a, lapack_int* lda,\n                    float* rcond, lapack_complex_float* work, float* rwork,\n                    lapack_int *info );\nvoid LAPACK_ztrcon( char* norm, char* uplo, char* diag, lapack_int* n,\n                    const lapack_complex_double* a, lapack_int* lda,\n                    double* rcond, lapack_complex_double* work, double* rwork,\n                    lapack_int *info );\nvoid LAPACK_stpcon( char* norm, char* uplo, char* diag, lapack_int* n,\n                    const float* ap, float* rcond, float* work,\n                    lapack_int* iwork, lapack_int *info );\nvoid LAPACK_dtpcon( char* norm, char* uplo, char* diag, lapack_int* n,\n                    const double* ap, double* rcond, double* work,\n                    lapack_int* iwork, lapack_int *info );\nvoid LAPACK_ctpcon( char* norm, char* uplo, char* diag, lapack_int* n,\n                    const lapack_complex_float* ap, float* rcond,\n                    lapack_complex_float* work, float* rwork,\n                    lapack_int *info );\nvoid LAPACK_ztpcon( char* norm, char* uplo, char* diag, lapack_int* n,\n                    const lapack_complex_double* ap, double* rcond,\n                    lapack_complex_double* work, double* rwork,\n                    lapack_int *info );\nvoid LAPACK_stbcon( char* norm, char* uplo, char* diag, lapack_int* n,\n                    lapack_int* kd, const float* ab, lapack_int* ldab,\n                    float* rcond, float* work, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_dtbcon( char* norm, char* uplo, char* diag, lapack_int* n,\n                    lapack_int* kd, const double* ab, lapack_int* ldab,\n                    double* rcond, double* work, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_ctbcon( char* norm, char* uplo, char* diag, lapack_int* n,\n                    lapack_int* kd, const lapack_complex_float* ab,\n                    lapack_int* ldab, float* rcond, lapack_complex_float* work,\n                    float* rwork, lapack_int *info );\nvoid LAPACK_ztbcon( char* norm, char* uplo, char* diag, lapack_int* n,\n                    lapack_int* kd, const lapack_complex_double* ab,\n                    lapack_int* ldab, double* rcond,\n                    lapack_complex_double* work, double* rwork,\n                    lapack_int *info );\nvoid LAPACK_sgerfs( char* trans, lapack_int* n, lapack_int* nrhs,\n                    const float* a, lapack_int* lda, const float* af,\n                    lapack_int* ldaf, const lapack_int* ipiv, const float* b,\n                    lapack_int* ldb, float* x, lapack_int* ldx, float* ferr,\n                    float* berr, float* work, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_dgerfs( char* trans, lapack_int* n, lapack_int* nrhs,\n                    const double* a, lapack_int* lda, const double* af,\n                    lapack_int* ldaf, const lapack_int* ipiv, const double* b,\n                    lapack_int* ldb, double* x, lapack_int* ldx, double* ferr,\n                    double* berr, double* work, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_cgerfs( char* trans, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_float* a, lapack_int* lda,\n                    const lapack_complex_float* af, lapack_int* ldaf,\n                    const lapack_int* ipiv, const lapack_complex_float* b,\n                    lapack_int* ldb, lapack_complex_float* x, lapack_int* ldx,\n                    float* ferr, float* berr, lapack_complex_float* work,\n                    float* rwork, lapack_int *info );\nvoid LAPACK_zgerfs( char* trans, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_double* a, lapack_int* lda,\n                    const lapack_complex_double* af, lapack_int* ldaf,\n                    const lapack_int* ipiv, const lapack_complex_double* b,\n                    lapack_int* ldb, lapack_complex_double* x, lapack_int* ldx,\n                    double* ferr, double* berr, lapack_complex_double* work,\n                    double* rwork, lapack_int *info );\nvoid LAPACK_dgerfsx( char* trans, char* equed, lapack_int* n, lapack_int* nrhs,\n                     const double* a, lapack_int* lda, const double* af,\n                     lapack_int* ldaf, const lapack_int* ipiv, const double* r,\n                     const double* c, const double* b, lapack_int* ldb,\n                     double* x, lapack_int* ldx, double* rcond, double* berr,\n                     lapack_int* n_err_bnds, double* err_bnds_norm,\n                     double* err_bnds_comp, lapack_int* nparams, double* params,\n                     double* work, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_sgerfsx( char* trans, char* equed, lapack_int* n, lapack_int* nrhs,\n                     const float* a, lapack_int* lda, const float* af,\n                     lapack_int* ldaf, const lapack_int* ipiv, const float* r,\n                     const float* c, const float* b, lapack_int* ldb, float* x,\n                     lapack_int* ldx, float* rcond, float* berr,\n                     lapack_int* n_err_bnds, float* err_bnds_norm,\n                     float* err_bnds_comp, lapack_int* nparams, float* params,\n                     float* work, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_zgerfsx( char* trans, char* equed, lapack_int* n, lapack_int* nrhs,\n                     const lapack_complex_double* a, lapack_int* lda,\n                     const lapack_complex_double* af, lapack_int* ldaf,\n                     const lapack_int* ipiv, const double* r, const double* c,\n                     const lapack_complex_double* b, lapack_int* ldb,\n                     lapack_complex_double* x, lapack_int* ldx, double* rcond,\n                     double* berr, lapack_int* n_err_bnds,\n                     double* err_bnds_norm, double* err_bnds_comp,\n                     lapack_int* nparams, double* params,\n                     lapack_complex_double* work, double* rwork,\n                     lapack_int *info );\nvoid LAPACK_cgerfsx( char* trans, char* equed, lapack_int* n, lapack_int* nrhs,\n                     const lapack_complex_float* a, lapack_int* lda,\n                     const lapack_complex_float* af, lapack_int* ldaf,\n                     const lapack_int* ipiv, const float* r, const float* c,\n                     const lapack_complex_float* b, lapack_int* ldb,\n                     lapack_complex_float* x, lapack_int* ldx, float* rcond,\n                     float* berr, lapack_int* n_err_bnds, float* err_bnds_norm,\n                     float* err_bnds_comp, lapack_int* nparams, float* params,\n                     lapack_complex_float* work, float* rwork,\n                     lapack_int *info );\nvoid LAPACK_sgbrfs( char* trans, lapack_int* n, lapack_int* kl, lapack_int* ku,\n                    lapack_int* nrhs, const float* ab, lapack_int* ldab,\n                    const float* afb, lapack_int* ldafb, const lapack_int* ipiv,\n                    const float* b, lapack_int* ldb, float* x, lapack_int* ldx,\n                    float* ferr, float* berr, float* work, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_dgbrfs( char* trans, lapack_int* n, lapack_int* kl, lapack_int* ku,\n                    lapack_int* nrhs, const double* ab, lapack_int* ldab,\n                    const double* afb, lapack_int* ldafb,\n                    const lapack_int* ipiv, const double* b, lapack_int* ldb,\n                    double* x, lapack_int* ldx, double* ferr, double* berr,\n                    double* work, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_cgbrfs( char* trans, lapack_int* n, lapack_int* kl, lapack_int* ku,\n                    lapack_int* nrhs, const lapack_complex_float* ab,\n                    lapack_int* ldab, const lapack_complex_float* afb,\n                    lapack_int* ldafb, const lapack_int* ipiv,\n                    const lapack_complex_float* b, lapack_int* ldb,\n                    lapack_complex_float* x, lapack_int* ldx, float* ferr,\n                    float* berr, lapack_complex_float* work, float* rwork,\n                    lapack_int *info );\nvoid LAPACK_zgbrfs( char* trans, lapack_int* n, lapack_int* kl, lapack_int* ku,\n                    lapack_int* nrhs, const lapack_complex_double* ab,\n                    lapack_int* ldab, const lapack_complex_double* afb,\n                    lapack_int* ldafb, const lapack_int* ipiv,\n                    const lapack_complex_double* b, lapack_int* ldb,\n                    lapack_complex_double* x, lapack_int* ldx, double* ferr,\n                    double* berr, lapack_complex_double* work, double* rwork,\n                    lapack_int *info );\nvoid LAPACK_dgbrfsx( char* trans, char* equed, lapack_int* n, lapack_int* kl,\n                     lapack_int* ku, lapack_int* nrhs, const double* ab,\n                     lapack_int* ldab, const double* afb, lapack_int* ldafb,\n                     const lapack_int* ipiv, const double* r, const double* c,\n                     const double* b, lapack_int* ldb, double* x,\n                     lapack_int* ldx, double* rcond, double* berr,\n                     lapack_int* n_err_bnds, double* err_bnds_norm,\n                     double* err_bnds_comp, lapack_int* nparams, double* params,\n                     double* work, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_sgbrfsx( char* trans, char* equed, lapack_int* n, lapack_int* kl,\n                     lapack_int* ku, lapack_int* nrhs, const float* ab,\n                     lapack_int* ldab, const float* afb, lapack_int* ldafb,\n                     const lapack_int* ipiv, const float* r, const float* c,\n                     const float* b, lapack_int* ldb, float* x, lapack_int* ldx,\n                     float* rcond, float* berr, lapack_int* n_err_bnds,\n                     float* err_bnds_norm, float* err_bnds_comp,\n                     lapack_int* nparams, float* params, float* work,\n                     lapack_int* iwork, lapack_int *info );\nvoid LAPACK_zgbrfsx( char* trans, char* equed, lapack_int* n, lapack_int* kl,\n                     lapack_int* ku, lapack_int* nrhs,\n                     const lapack_complex_double* ab, lapack_int* ldab,\n                     const lapack_complex_double* afb, lapack_int* ldafb,\n                     const lapack_int* ipiv, const double* r, const double* c,\n                     const lapack_complex_double* b, lapack_int* ldb,\n                     lapack_complex_double* x, lapack_int* ldx, double* rcond,\n                     double* berr, lapack_int* n_err_bnds,\n                     double* err_bnds_norm, double* err_bnds_comp,\n                     lapack_int* nparams, double* params,\n                     lapack_complex_double* work, double* rwork,\n                     lapack_int *info );\nvoid LAPACK_cgbrfsx( char* trans, char* equed, lapack_int* n, lapack_int* kl,\n                     lapack_int* ku, lapack_int* nrhs,\n                     const lapack_complex_float* ab, lapack_int* ldab,\n                     const lapack_complex_float* afb, lapack_int* ldafb,\n                     const lapack_int* ipiv, const float* r, const float* c,\n                     const lapack_complex_float* b, lapack_int* ldb,\n                     lapack_complex_float* x, lapack_int* ldx, float* rcond,\n                     float* berr, lapack_int* n_err_bnds, float* err_bnds_norm,\n                     float* err_bnds_comp, lapack_int* nparams, float* params,\n                     lapack_complex_float* work, float* rwork,\n                     lapack_int *info );\nvoid LAPACK_sgtrfs( char* trans, lapack_int* n, lapack_int* nrhs,\n                    const float* dl, const float* d, const float* du,\n                    const float* dlf, const float* df, const float* duf,\n                    const float* du2, const lapack_int* ipiv, const float* b,\n                    lapack_int* ldb, float* x, lapack_int* ldx, float* ferr,\n                    float* berr, float* work, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_dgtrfs( char* trans, lapack_int* n, lapack_int* nrhs,\n                    const double* dl, const double* d, const double* du,\n                    const double* dlf, const double* df, const double* duf,\n                    const double* du2, const lapack_int* ipiv, const double* b,\n                    lapack_int* ldb, double* x, lapack_int* ldx, double* ferr,\n                    double* berr, double* work, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_cgtrfs( char* trans, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_float* dl,\n                    const lapack_complex_float* d,\n                    const lapack_complex_float* du,\n                    const lapack_complex_float* dlf,\n                    const lapack_complex_float* df,\n                    const lapack_complex_float* duf,\n                    const lapack_complex_float* du2, const lapack_int* ipiv,\n                    const lapack_complex_float* b, lapack_int* ldb,\n                    lapack_complex_float* x, lapack_int* ldx, float* ferr,\n                    float* berr, lapack_complex_float* work, float* rwork,\n                    lapack_int *info );\nvoid LAPACK_zgtrfs( char* trans, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_double* dl,\n                    const lapack_complex_double* d,\n                    const lapack_complex_double* du,\n                    const lapack_complex_double* dlf,\n                    const lapack_complex_double* df,\n                    const lapack_complex_double* duf,\n                    const lapack_complex_double* du2, const lapack_int* ipiv,\n                    const lapack_complex_double* b, lapack_int* ldb,\n                    lapack_complex_double* x, lapack_int* ldx, double* ferr,\n                    double* berr, lapack_complex_double* work, double* rwork,\n                    lapack_int *info );\nvoid LAPACK_sporfs( char* uplo, lapack_int* n, lapack_int* nrhs, const float* a,\n                    lapack_int* lda, const float* af, lapack_int* ldaf,\n                    const float* b, lapack_int* ldb, float* x, lapack_int* ldx,\n                    float* ferr, float* berr, float* work, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_dporfs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const double* a, lapack_int* lda, const double* af,\n                    lapack_int* ldaf, const double* b, lapack_int* ldb,\n                    double* x, lapack_int* ldx, double* ferr, double* berr,\n                    double* work, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_cporfs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_float* a, lapack_int* lda,\n                    const lapack_complex_float* af, lapack_int* ldaf,\n                    const lapack_complex_float* b, lapack_int* ldb,\n                    lapack_complex_float* x, lapack_int* ldx, float* ferr,\n                    float* berr, lapack_complex_float* work, float* rwork,\n                    lapack_int *info );\nvoid LAPACK_zporfs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_double* a, lapack_int* lda,\n                    const lapack_complex_double* af, lapack_int* ldaf,\n                    const lapack_complex_double* b, lapack_int* ldb,\n                    lapack_complex_double* x, lapack_int* ldx, double* ferr,\n                    double* berr, lapack_complex_double* work, double* rwork,\n                    lapack_int *info );\nvoid LAPACK_dporfsx( char* uplo, char* equed, lapack_int* n, lapack_int* nrhs,\n                     const double* a, lapack_int* lda, const double* af,\n                     lapack_int* ldaf, const double* s, const double* b,\n                     lapack_int* ldb, double* x, lapack_int* ldx, double* rcond,\n                     double* berr, lapack_int* n_err_bnds,\n                     double* err_bnds_norm, double* err_bnds_comp,\n                     lapack_int* nparams, double* params, double* work,\n                     lapack_int* iwork, lapack_int *info );\nvoid LAPACK_sporfsx( char* uplo, char* equed, lapack_int* n, lapack_int* nrhs,\n                     const float* a, lapack_int* lda, const float* af,\n                     lapack_int* ldaf, const float* s, const float* b,\n                     lapack_int* ldb, float* x, lapack_int* ldx, float* rcond,\n                     float* berr, lapack_int* n_err_bnds, float* err_bnds_norm,\n                     float* err_bnds_comp, lapack_int* nparams, float* params,\n                     float* work, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_zporfsx( char* uplo, char* equed, lapack_int* n, lapack_int* nrhs,\n                     const lapack_complex_double* a, lapack_int* lda,\n                     const lapack_complex_double* af, lapack_int* ldaf,\n                     const double* s, const lapack_complex_double* b,\n                     lapack_int* ldb, lapack_complex_double* x, lapack_int* ldx,\n                     double* rcond, double* berr, lapack_int* n_err_bnds,\n                     double* err_bnds_norm, double* err_bnds_comp,\n                     lapack_int* nparams, double* params,\n                     lapack_complex_double* work, double* rwork,\n                     lapack_int *info );\nvoid LAPACK_cporfsx( char* uplo, char* equed, lapack_int* n, lapack_int* nrhs,\n                     const lapack_complex_float* a, lapack_int* lda,\n                     const lapack_complex_float* af, lapack_int* ldaf,\n                     const float* s, const lapack_complex_float* b,\n                     lapack_int* ldb, lapack_complex_float* x, lapack_int* ldx,\n                     float* rcond, float* berr, lapack_int* n_err_bnds,\n                     float* err_bnds_norm, float* err_bnds_comp,\n                     lapack_int* nparams, float* params,\n                     lapack_complex_float* work, float* rwork,\n                     lapack_int *info );\nvoid LAPACK_spprfs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const float* ap, const float* afp, const float* b,\n                    lapack_int* ldb, float* x, lapack_int* ldx, float* ferr,\n                    float* berr, float* work, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_dpprfs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const double* ap, const double* afp, const double* b,\n                    lapack_int* ldb, double* x, lapack_int* ldx, double* ferr,\n                    double* berr, double* work, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_cpprfs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_float* ap,\n                    const lapack_complex_float* afp,\n                    const lapack_complex_float* b, lapack_int* ldb,\n                    lapack_complex_float* x, lapack_int* ldx, float* ferr,\n                    float* berr, lapack_complex_float* work, float* rwork,\n                    lapack_int *info );\nvoid LAPACK_zpprfs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_double* ap,\n                    const lapack_complex_double* afp,\n                    const lapack_complex_double* b, lapack_int* ldb,\n                    lapack_complex_double* x, lapack_int* ldx, double* ferr,\n                    double* berr, lapack_complex_double* work, double* rwork,\n                    lapack_int *info );\nvoid LAPACK_spbrfs( char* uplo, lapack_int* n, lapack_int* kd, lapack_int* nrhs,\n                    const float* ab, lapack_int* ldab, const float* afb,\n                    lapack_int* ldafb, const float* b, lapack_int* ldb,\n                    float* x, lapack_int* ldx, float* ferr, float* berr,\n                    float* work, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_dpbrfs( char* uplo, lapack_int* n, lapack_int* kd, lapack_int* nrhs,\n                    const double* ab, lapack_int* ldab, const double* afb,\n                    lapack_int* ldafb, const double* b, lapack_int* ldb,\n                    double* x, lapack_int* ldx, double* ferr, double* berr,\n                    double* work, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_cpbrfs( char* uplo, lapack_int* n, lapack_int* kd, lapack_int* nrhs,\n                    const lapack_complex_float* ab, lapack_int* ldab,\n                    const lapack_complex_float* afb, lapack_int* ldafb,\n                    const lapack_complex_float* b, lapack_int* ldb,\n                    lapack_complex_float* x, lapack_int* ldx, float* ferr,\n                    float* berr, lapack_complex_float* work, float* rwork,\n                    lapack_int *info );\nvoid LAPACK_zpbrfs( char* uplo, lapack_int* n, lapack_int* kd, lapack_int* nrhs,\n                    const lapack_complex_double* ab, lapack_int* ldab,\n                    const lapack_complex_double* afb, lapack_int* ldafb,\n                    const lapack_complex_double* b, lapack_int* ldb,\n                    lapack_complex_double* x, lapack_int* ldx, double* ferr,\n                    double* berr, lapack_complex_double* work, double* rwork,\n                    lapack_int *info );\nvoid LAPACK_sptrfs( lapack_int* n, lapack_int* nrhs, const float* d,\n                    const float* e, const float* df, const float* ef,\n                    const float* b, lapack_int* ldb, float* x, lapack_int* ldx,\n                    float* ferr, float* berr, float* work, lapack_int *info );\nvoid LAPACK_dptrfs( lapack_int* n, lapack_int* nrhs, const double* d,\n                    const double* e, const double* df, const double* ef,\n                    const double* b, lapack_int* ldb, double* x,\n                    lapack_int* ldx, double* ferr, double* berr, double* work,\n                    lapack_int *info );\nvoid LAPACK_cptrfs( char* uplo, lapack_int* n, lapack_int* nrhs, const float* d,\n                    const lapack_complex_float* e, const float* df,\n                    const lapack_complex_float* ef,\n                    const lapack_complex_float* b, lapack_int* ldb,\n                    lapack_complex_float* x, lapack_int* ldx, float* ferr,\n                    float* berr, lapack_complex_float* work, float* rwork,\n                    lapack_int *info );\nvoid LAPACK_zptrfs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const double* d, const lapack_complex_double* e,\n                    const double* df, const lapack_complex_double* ef,\n                    const lapack_complex_double* b, lapack_int* ldb,\n                    lapack_complex_double* x, lapack_int* ldx, double* ferr,\n                    double* berr, lapack_complex_double* work, double* rwork,\n                    lapack_int *info );\nvoid LAPACK_ssyrfs( char* uplo, lapack_int* n, lapack_int* nrhs, const float* a,\n                    lapack_int* lda, const float* af, lapack_int* ldaf,\n                    const lapack_int* ipiv, const float* b, lapack_int* ldb,\n                    float* x, lapack_int* ldx, float* ferr, float* berr,\n                    float* work, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_dsyrfs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const double* a, lapack_int* lda, const double* af,\n                    lapack_int* ldaf, const lapack_int* ipiv, const double* b,\n                    lapack_int* ldb, double* x, lapack_int* ldx, double* ferr,\n                    double* berr, double* work, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_csyrfs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_float* a, lapack_int* lda,\n                    const lapack_complex_float* af, lapack_int* ldaf,\n                    const lapack_int* ipiv, const lapack_complex_float* b,\n                    lapack_int* ldb, lapack_complex_float* x, lapack_int* ldx,\n                    float* ferr, float* berr, lapack_complex_float* work,\n                    float* rwork, lapack_int *info );\nvoid LAPACK_zsyrfs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_double* a, lapack_int* lda,\n                    const lapack_complex_double* af, lapack_int* ldaf,\n                    const lapack_int* ipiv, const lapack_complex_double* b,\n                    lapack_int* ldb, lapack_complex_double* x, lapack_int* ldx,\n                    double* ferr, double* berr, lapack_complex_double* work,\n                    double* rwork, lapack_int *info );\nvoid LAPACK_dsyrfsx( char* uplo, char* equed, lapack_int* n, lapack_int* nrhs,\n                     const double* a, lapack_int* lda, const double* af,\n                     lapack_int* ldaf, const lapack_int* ipiv, const double* s,\n                     const double* b, lapack_int* ldb, double* x,\n                     lapack_int* ldx, double* rcond, double* berr,\n                     lapack_int* n_err_bnds, double* err_bnds_norm,\n                     double* err_bnds_comp, lapack_int* nparams, double* params,\n                     double* work, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_ssyrfsx( char* uplo, char* equed, lapack_int* n, lapack_int* nrhs,\n                     const float* a, lapack_int* lda, const float* af,\n                     lapack_int* ldaf, const lapack_int* ipiv, const float* s,\n                     const float* b, lapack_int* ldb, float* x, lapack_int* ldx,\n                     float* rcond, float* berr, lapack_int* n_err_bnds,\n                     float* err_bnds_norm, float* err_bnds_comp,\n                     lapack_int* nparams, float* params, float* work,\n                     lapack_int* iwork, lapack_int *info );\nvoid LAPACK_zsyrfsx( char* uplo, char* equed, lapack_int* n, lapack_int* nrhs,\n                     const lapack_complex_double* a, lapack_int* lda,\n                     const lapack_complex_double* af, lapack_int* ldaf,\n                     const lapack_int* ipiv, const double* s,\n                     const lapack_complex_double* b, lapack_int* ldb,\n                     lapack_complex_double* x, lapack_int* ldx, double* rcond,\n                     double* berr, lapack_int* n_err_bnds,\n                     double* err_bnds_norm, double* err_bnds_comp,\n                     lapack_int* nparams, double* params,\n                     lapack_complex_double* work, double* rwork,\n                     lapack_int *info );\nvoid LAPACK_csyrfsx( char* uplo, char* equed, lapack_int* n, lapack_int* nrhs,\n                     const lapack_complex_float* a, lapack_int* lda,\n                     const lapack_complex_float* af, lapack_int* ldaf,\n                     const lapack_int* ipiv, const float* s,\n                     const lapack_complex_float* b, lapack_int* ldb,\n                     lapack_complex_float* x, lapack_int* ldx, float* rcond,\n                     float* berr, lapack_int* n_err_bnds, float* err_bnds_norm,\n                     float* err_bnds_comp, lapack_int* nparams, float* params,\n                     lapack_complex_float* work, float* rwork,\n                     lapack_int *info );\nvoid LAPACK_cherfs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_float* a, lapack_int* lda,\n                    const lapack_complex_float* af, lapack_int* ldaf,\n                    const lapack_int* ipiv, const lapack_complex_float* b,\n                    lapack_int* ldb, lapack_complex_float* x, lapack_int* ldx,\n                    float* ferr, float* berr, lapack_complex_float* work,\n                    float* rwork, lapack_int *info );\nvoid LAPACK_zherfs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_double* a, lapack_int* lda,\n                    const lapack_complex_double* af, lapack_int* ldaf,\n                    const lapack_int* ipiv, const lapack_complex_double* b,\n                    lapack_int* ldb, lapack_complex_double* x, lapack_int* ldx,\n                    double* ferr, double* berr, lapack_complex_double* work,\n                    double* rwork, lapack_int *info );\nvoid LAPACK_zherfsx( char* uplo, char* equed, lapack_int* n, lapack_int* nrhs,\n                     const lapack_complex_double* a, lapack_int* lda,\n                     const lapack_complex_double* af, lapack_int* ldaf,\n                     const lapack_int* ipiv, const double* s,\n                     const lapack_complex_double* b, lapack_int* ldb,\n                     lapack_complex_double* x, lapack_int* ldx, double* rcond,\n                     double* berr, lapack_int* n_err_bnds,\n                     double* err_bnds_norm, double* err_bnds_comp,\n                     lapack_int* nparams, double* params,\n                     lapack_complex_double* work, double* rwork,\n                     lapack_int *info );\nvoid LAPACK_cherfsx( char* uplo, char* equed, lapack_int* n, lapack_int* nrhs,\n                     const lapack_complex_float* a, lapack_int* lda,\n                     const lapack_complex_float* af, lapack_int* ldaf,\n                     const lapack_int* ipiv, const float* s,\n                     const lapack_complex_float* b, lapack_int* ldb,\n                     lapack_complex_float* x, lapack_int* ldx, float* rcond,\n                     float* berr, lapack_int* n_err_bnds, float* err_bnds_norm,\n                     float* err_bnds_comp, lapack_int* nparams, float* params,\n                     lapack_complex_float* work, float* rwork,\n                     lapack_int *info );\nvoid LAPACK_ssprfs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const float* ap, const float* afp, const lapack_int* ipiv,\n                    const float* b, lapack_int* ldb, float* x, lapack_int* ldx,\n                    float* ferr, float* berr, float* work, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_dsprfs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const double* ap, const double* afp, const lapack_int* ipiv,\n                    const double* b, lapack_int* ldb, double* x,\n                    lapack_int* ldx, double* ferr, double* berr, double* work,\n                    lapack_int* iwork, lapack_int *info );\nvoid LAPACK_csprfs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_float* ap,\n                    const lapack_complex_float* afp, const lapack_int* ipiv,\n                    const lapack_complex_float* b, lapack_int* ldb,\n                    lapack_complex_float* x, lapack_int* ldx, float* ferr,\n                    float* berr, lapack_complex_float* work, float* rwork,\n                    lapack_int *info );\nvoid LAPACK_zsprfs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_double* ap,\n                    const lapack_complex_double* afp, const lapack_int* ipiv,\n                    const lapack_complex_double* b, lapack_int* ldb,\n                    lapack_complex_double* x, lapack_int* ldx, double* ferr,\n                    double* berr, lapack_complex_double* work, double* rwork,\n                    lapack_int *info );\nvoid LAPACK_chprfs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_float* ap,\n                    const lapack_complex_float* afp, const lapack_int* ipiv,\n                    const lapack_complex_float* b, lapack_int* ldb,\n                    lapack_complex_float* x, lapack_int* ldx, float* ferr,\n                    float* berr, lapack_complex_float* work, float* rwork,\n                    lapack_int *info );\nvoid LAPACK_zhprfs( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_double* ap,\n                    const lapack_complex_double* afp, const lapack_int* ipiv,\n                    const lapack_complex_double* b, lapack_int* ldb,\n                    lapack_complex_double* x, lapack_int* ldx, double* ferr,\n                    double* berr, lapack_complex_double* work, double* rwork,\n                    lapack_int *info );\nvoid LAPACK_strrfs( char* uplo, char* trans, char* diag, lapack_int* n,\n                    lapack_int* nrhs, const float* a, lapack_int* lda,\n                    const float* b, lapack_int* ldb, const float* x,\n                    lapack_int* ldx, float* ferr, float* berr, float* work,\n                    lapack_int* iwork, lapack_int *info );\nvoid LAPACK_dtrrfs( char* uplo, char* trans, char* diag, lapack_int* n,\n                    lapack_int* nrhs, const double* a, lapack_int* lda,\n                    const double* b, lapack_int* ldb, const double* x,\n                    lapack_int* ldx, double* ferr, double* berr, double* work,\n                    lapack_int* iwork, lapack_int *info );\nvoid LAPACK_ctrrfs( char* uplo, char* trans, char* diag, lapack_int* n,\n                    lapack_int* nrhs, const lapack_complex_float* a,\n                    lapack_int* lda, const lapack_complex_float* b,\n                    lapack_int* ldb, const lapack_complex_float* x,\n                    lapack_int* ldx, float* ferr, float* berr,\n                    lapack_complex_float* work, float* rwork,\n                    lapack_int *info );\nvoid LAPACK_ztrrfs( char* uplo, char* trans, char* diag, lapack_int* n,\n                    lapack_int* nrhs, const lapack_complex_double* a,\n                    lapack_int* lda, const lapack_complex_double* b,\n                    lapack_int* ldb, const lapack_complex_double* x,\n                    lapack_int* ldx, double* ferr, double* berr,\n                    lapack_complex_double* work, double* rwork,\n                    lapack_int *info );\nvoid LAPACK_stprfs( char* uplo, char* trans, char* diag, lapack_int* n,\n                    lapack_int* nrhs, const float* ap, const float* b,\n                    lapack_int* ldb, const float* x, lapack_int* ldx,\n                    float* ferr, float* berr, float* work, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_dtprfs( char* uplo, char* trans, char* diag, lapack_int* n,\n                    lapack_int* nrhs, const double* ap, const double* b,\n                    lapack_int* ldb, const double* x, lapack_int* ldx,\n                    double* ferr, double* berr, double* work, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_ctprfs( char* uplo, char* trans, char* diag, lapack_int* n,\n                    lapack_int* nrhs, const lapack_complex_float* ap,\n                    const lapack_complex_float* b, lapack_int* ldb,\n                    const lapack_complex_float* x, lapack_int* ldx, float* ferr,\n                    float* berr, lapack_complex_float* work, float* rwork,\n                    lapack_int *info );\nvoid LAPACK_ztprfs( char* uplo, char* trans, char* diag, lapack_int* n,\n                    lapack_int* nrhs, const lapack_complex_double* ap,\n                    const lapack_complex_double* b, lapack_int* ldb,\n                    const lapack_complex_double* x, lapack_int* ldx,\n                    double* ferr, double* berr, lapack_complex_double* work,\n                    double* rwork, lapack_int *info );\nvoid LAPACK_stbrfs( char* uplo, char* trans, char* diag, lapack_int* n,\n                    lapack_int* kd, lapack_int* nrhs, const float* ab,\n                    lapack_int* ldab, const float* b, lapack_int* ldb,\n                    const float* x, lapack_int* ldx, float* ferr, float* berr,\n                    float* work, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_dtbrfs( char* uplo, char* trans, char* diag, lapack_int* n,\n                    lapack_int* kd, lapack_int* nrhs, const double* ab,\n                    lapack_int* ldab, const double* b, lapack_int* ldb,\n                    const double* x, lapack_int* ldx, double* ferr,\n                    double* berr, double* work, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_ctbrfs( char* uplo, char* trans, char* diag, lapack_int* n,\n                    lapack_int* kd, lapack_int* nrhs,\n                    const lapack_complex_float* ab, lapack_int* ldab,\n                    const lapack_complex_float* b, lapack_int* ldb,\n                    const lapack_complex_float* x, lapack_int* ldx, float* ferr,\n                    float* berr, lapack_complex_float* work, float* rwork,\n                    lapack_int *info );\nvoid LAPACK_ztbrfs( char* uplo, char* trans, char* diag, lapack_int* n,\n                    lapack_int* kd, lapack_int* nrhs,\n                    const lapack_complex_double* ab, lapack_int* ldab,\n                    const lapack_complex_double* b, lapack_int* ldb,\n                    const lapack_complex_double* x, lapack_int* ldx,\n                    double* ferr, double* berr, lapack_complex_double* work,\n                    double* rwork, lapack_int *info );\nvoid LAPACK_sgetri( lapack_int* n, float* a, lapack_int* lda,\n                    const lapack_int* ipiv, float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_dgetri( lapack_int* n, double* a, lapack_int* lda,\n                    const lapack_int* ipiv, double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_cgetri( lapack_int* n, lapack_complex_float* a, lapack_int* lda,\n                    const lapack_int* ipiv, lapack_complex_float* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_zgetri( lapack_int* n, lapack_complex_double* a, lapack_int* lda,\n                    const lapack_int* ipiv, lapack_complex_double* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_spotri( char* uplo, lapack_int* n, float* a, lapack_int* lda,\n                    lapack_int *info );\nvoid LAPACK_dpotri( char* uplo, lapack_int* n, double* a, lapack_int* lda,\n                    lapack_int *info );\nvoid LAPACK_cpotri( char* uplo, lapack_int* n, lapack_complex_float* a,\n                    lapack_int* lda, lapack_int *info );\nvoid LAPACK_zpotri( char* uplo, lapack_int* n, lapack_complex_double* a,\n                    lapack_int* lda, lapack_int *info );\nvoid LAPACK_dpftri( char* transr, char* uplo, lapack_int* n, double* a,\n                    lapack_int *info );\nvoid LAPACK_spftri( char* transr, char* uplo, lapack_int* n, float* a,\n                    lapack_int *info );\nvoid LAPACK_zpftri( char* transr, char* uplo, lapack_int* n,\n                    lapack_complex_double* a, lapack_int *info );\nvoid LAPACK_cpftri( char* transr, char* uplo, lapack_int* n,\n                    lapack_complex_float* a, lapack_int *info );\nvoid LAPACK_spptri( char* uplo, lapack_int* n, float* ap, lapack_int *info );\nvoid LAPACK_dpptri( char* uplo, lapack_int* n, double* ap, lapack_int *info );\nvoid LAPACK_cpptri( char* uplo, lapack_int* n, lapack_complex_float* ap,\n                    lapack_int *info );\nvoid LAPACK_zpptri( char* uplo, lapack_int* n, lapack_complex_double* ap,\n                    lapack_int *info );\nvoid LAPACK_ssytri( char* uplo, lapack_int* n, float* a, lapack_int* lda,\n                    const lapack_int* ipiv, float* work, lapack_int *info );\nvoid LAPACK_dsytri( char* uplo, lapack_int* n, double* a, lapack_int* lda,\n                    const lapack_int* ipiv, double* work, lapack_int *info );\nvoid LAPACK_csytri( char* uplo, lapack_int* n, lapack_complex_float* a,\n                    lapack_int* lda, const lapack_int* ipiv,\n                    lapack_complex_float* work, lapack_int *info );\nvoid LAPACK_zsytri( char* uplo, lapack_int* n, lapack_complex_double* a,\n                    lapack_int* lda, const lapack_int* ipiv,\n                    lapack_complex_double* work, lapack_int *info );\nvoid LAPACK_chetri( char* uplo, lapack_int* n, lapack_complex_float* a,\n                    lapack_int* lda, const lapack_int* ipiv,\n                    lapack_complex_float* work, lapack_int *info );\nvoid LAPACK_zhetri( char* uplo, lapack_int* n, lapack_complex_double* a,\n                    lapack_int* lda, const lapack_int* ipiv,\n                    lapack_complex_double* work, lapack_int *info );\nvoid LAPACK_ssptri( char* uplo, lapack_int* n, float* ap,\n                    const lapack_int* ipiv, float* work, lapack_int *info );\nvoid LAPACK_dsptri( char* uplo, lapack_int* n, double* ap,\n                    const lapack_int* ipiv, double* work, lapack_int *info );\nvoid LAPACK_csptri( char* uplo, lapack_int* n, lapack_complex_float* ap,\n                    const lapack_int* ipiv, lapack_complex_float* work,\n                    lapack_int *info );\nvoid LAPACK_zsptri( char* uplo, lapack_int* n, lapack_complex_double* ap,\n                    const lapack_int* ipiv, lapack_complex_double* work,\n                    lapack_int *info );\nvoid LAPACK_chptri( char* uplo, lapack_int* n, lapack_complex_float* ap,\n                    const lapack_int* ipiv, lapack_complex_float* work,\n                    lapack_int *info );\nvoid LAPACK_zhptri( char* uplo, lapack_int* n, lapack_complex_double* ap,\n                    const lapack_int* ipiv, lapack_complex_double* work,\n                    lapack_int *info );\nvoid LAPACK_strtri( char* uplo, char* diag, lapack_int* n, float* a,\n                    lapack_int* lda, lapack_int *info );\nvoid LAPACK_dtrtri( char* uplo, char* diag, lapack_int* n, double* a,\n                    lapack_int* lda, lapack_int *info );\nvoid LAPACK_ctrtri( char* uplo, char* diag, lapack_int* n,\n                    lapack_complex_float* a, lapack_int* lda,\n                    lapack_int *info );\nvoid LAPACK_ztrtri( char* uplo, char* diag, lapack_int* n,\n                    lapack_complex_double* a, lapack_int* lda,\n                    lapack_int *info );\nvoid LAPACK_dtftri( char* transr, char* uplo, char* diag, lapack_int* n,\n                    double* a, lapack_int *info );\nvoid LAPACK_stftri( char* transr, char* uplo, char* diag, lapack_int* n,\n                    float* a, lapack_int *info );\nvoid LAPACK_ztftri( char* transr, char* uplo, char* diag, lapack_int* n,\n                    lapack_complex_double* a, lapack_int *info );\nvoid LAPACK_ctftri( char* transr, char* uplo, char* diag, lapack_int* n,\n                    lapack_complex_float* a, lapack_int *info );\nvoid LAPACK_stptri( char* uplo, char* diag, lapack_int* n, float* ap,\n                    lapack_int *info );\nvoid LAPACK_dtptri( char* uplo, char* diag, lapack_int* n, double* ap,\n                    lapack_int *info );\nvoid LAPACK_ctptri( char* uplo, char* diag, lapack_int* n,\n                    lapack_complex_float* ap, lapack_int *info );\nvoid LAPACK_ztptri( char* uplo, char* diag, lapack_int* n,\n                    lapack_complex_double* ap, lapack_int *info );\nvoid LAPACK_sgeequ( lapack_int* m, lapack_int* n, const float* a,\n                    lapack_int* lda, float* r, float* c, float* rowcnd,\n                    float* colcnd, float* amax, lapack_int *info );\nvoid LAPACK_dgeequ( lapack_int* m, lapack_int* n, const double* a,\n                    lapack_int* lda, double* r, double* c, double* rowcnd,\n                    double* colcnd, double* amax, lapack_int *info );\nvoid LAPACK_cgeequ( lapack_int* m, lapack_int* n, const lapack_complex_float* a,\n                    lapack_int* lda, float* r, float* c, float* rowcnd,\n                    float* colcnd, float* amax, lapack_int *info );\nvoid LAPACK_zgeequ( lapack_int* m, lapack_int* n,\n                    const lapack_complex_double* a, lapack_int* lda, double* r,\n                    double* c, double* rowcnd, double* colcnd, double* amax,\n                    lapack_int *info );\nvoid LAPACK_dgeequb( lapack_int* m, lapack_int* n, const double* a,\n                     lapack_int* lda, double* r, double* c, double* rowcnd,\n                     double* colcnd, double* amax, lapack_int *info );\nvoid LAPACK_sgeequb( lapack_int* m, lapack_int* n, const float* a,\n                     lapack_int* lda, float* r, float* c, float* rowcnd,\n                     float* colcnd, float* amax, lapack_int *info );\nvoid LAPACK_zgeequb( lapack_int* m, lapack_int* n,\n                     const lapack_complex_double* a, lapack_int* lda, double* r,\n                     double* c, double* rowcnd, double* colcnd, double* amax,\n                     lapack_int *info );\nvoid LAPACK_cgeequb( lapack_int* m, lapack_int* n,\n                     const lapack_complex_float* a, lapack_int* lda, float* r,\n                     float* c, float* rowcnd, float* colcnd, float* amax,\n                     lapack_int *info );\nvoid LAPACK_sgbequ( lapack_int* m, lapack_int* n, lapack_int* kl,\n                    lapack_int* ku, const float* ab, lapack_int* ldab, float* r,\n                    float* c, float* rowcnd, float* colcnd, float* amax,\n                    lapack_int *info );\nvoid LAPACK_dgbequ( lapack_int* m, lapack_int* n, lapack_int* kl,\n                    lapack_int* ku, const double* ab, lapack_int* ldab,\n                    double* r, double* c, double* rowcnd, double* colcnd,\n                    double* amax, lapack_int *info );\nvoid LAPACK_cgbequ( lapack_int* m, lapack_int* n, lapack_int* kl,\n                    lapack_int* ku, const lapack_complex_float* ab,\n                    lapack_int* ldab, float* r, float* c, float* rowcnd,\n                    float* colcnd, float* amax, lapack_int *info );\nvoid LAPACK_zgbequ( lapack_int* m, lapack_int* n, lapack_int* kl,\n                    lapack_int* ku, const lapack_complex_double* ab,\n                    lapack_int* ldab, double* r, double* c, double* rowcnd,\n                    double* colcnd, double* amax, lapack_int *info );\nvoid LAPACK_dgbequb( lapack_int* m, lapack_int* n, lapack_int* kl,\n                     lapack_int* ku, const double* ab, lapack_int* ldab,\n                     double* r, double* c, double* rowcnd, double* colcnd,\n                     double* amax, lapack_int *info );\nvoid LAPACK_sgbequb( lapack_int* m, lapack_int* n, lapack_int* kl,\n                     lapack_int* ku, const float* ab, lapack_int* ldab,\n                     float* r, float* c, float* rowcnd, float* colcnd,\n                     float* amax, lapack_int *info );\nvoid LAPACK_zgbequb( lapack_int* m, lapack_int* n, lapack_int* kl,\n                     lapack_int* ku, const lapack_complex_double* ab,\n                     lapack_int* ldab, double* r, double* c, double* rowcnd,\n                     double* colcnd, double* amax, lapack_int *info );\nvoid LAPACK_cgbequb( lapack_int* m, lapack_int* n, lapack_int* kl,\n                     lapack_int* ku, const lapack_complex_float* ab,\n                     lapack_int* ldab, float* r, float* c, float* rowcnd,\n                     float* colcnd, float* amax, lapack_int *info );\nvoid LAPACK_spoequ( lapack_int* n, const float* a, lapack_int* lda, float* s,\n                    float* scond, float* amax, lapack_int *info );\nvoid LAPACK_dpoequ( lapack_int* n, const double* a, lapack_int* lda, double* s,\n                    double* scond, double* amax, lapack_int *info );\nvoid LAPACK_cpoequ( lapack_int* n, const lapack_complex_float* a,\n                    lapack_int* lda, float* s, float* scond, float* amax,\n                    lapack_int *info );\nvoid LAPACK_zpoequ( lapack_int* n, const lapack_complex_double* a,\n                    lapack_int* lda, double* s, double* scond, double* amax,\n                    lapack_int *info );\nvoid LAPACK_dpoequb( lapack_int* n, const double* a, lapack_int* lda, double* s,\n                     double* scond, double* amax, lapack_int *info );\nvoid LAPACK_spoequb( lapack_int* n, const float* a, lapack_int* lda, float* s,\n                     float* scond, float* amax, lapack_int *info );\nvoid LAPACK_zpoequb( lapack_int* n, const lapack_complex_double* a,\n                     lapack_int* lda, double* s, double* scond, double* amax,\n                     lapack_int *info );\nvoid LAPACK_cpoequb( lapack_int* n, const lapack_complex_float* a,\n                     lapack_int* lda, float* s, float* scond, float* amax,\n                     lapack_int *info );\nvoid LAPACK_sppequ( char* uplo, lapack_int* n, const float* ap, float* s,\n                    float* scond, float* amax, lapack_int *info );\nvoid LAPACK_dppequ( char* uplo, lapack_int* n, const double* ap, double* s,\n                    double* scond, double* amax, lapack_int *info );\nvoid LAPACK_cppequ( char* uplo, lapack_int* n, const lapack_complex_float* ap,\n                    float* s, float* scond, float* amax, lapack_int *info );\nvoid LAPACK_zppequ( char* uplo, lapack_int* n, const lapack_complex_double* ap,\n                    double* s, double* scond, double* amax, lapack_int *info );\nvoid LAPACK_spbequ( char* uplo, lapack_int* n, lapack_int* kd, const float* ab,\n                    lapack_int* ldab, float* s, float* scond, float* amax,\n                    lapack_int *info );\nvoid LAPACK_dpbequ( char* uplo, lapack_int* n, lapack_int* kd, const double* ab,\n                    lapack_int* ldab, double* s, double* scond, double* amax,\n                    lapack_int *info );\nvoid LAPACK_cpbequ( char* uplo, lapack_int* n, lapack_int* kd,\n                    const lapack_complex_float* ab, lapack_int* ldab, float* s,\n                    float* scond, float* amax, lapack_int *info );\nvoid LAPACK_zpbequ( char* uplo, lapack_int* n, lapack_int* kd,\n                    const lapack_complex_double* ab, lapack_int* ldab,\n                    double* s, double* scond, double* amax, lapack_int *info );\nvoid LAPACK_dsyequb( char* uplo, lapack_int* n, const double* a,\n                     lapack_int* lda, double* s, double* scond, double* amax,\n                     double* work, lapack_int *info );\nvoid LAPACK_ssyequb( char* uplo, lapack_int* n, const float* a, lapack_int* lda,\n                     float* s, float* scond, float* amax, float* work,\n                     lapack_int *info );\nvoid LAPACK_zsyequb( char* uplo, lapack_int* n, const lapack_complex_double* a,\n                     lapack_int* lda, double* s, double* scond, double* amax,\n                     lapack_complex_double* work, lapack_int *info );\nvoid LAPACK_csyequb( char* uplo, lapack_int* n, const lapack_complex_float* a,\n                     lapack_int* lda, float* s, float* scond, float* amax,\n                     lapack_complex_float* work, lapack_int *info );\nvoid LAPACK_zheequb( char* uplo, lapack_int* n, const lapack_complex_double* a,\n                     lapack_int* lda, double* s, double* scond, double* amax,\n                     lapack_complex_double* work, lapack_int *info );\nvoid LAPACK_cheequb( char* uplo, lapack_int* n, const lapack_complex_float* a,\n                     lapack_int* lda, float* s, float* scond, float* amax,\n                     lapack_complex_float* work, lapack_int *info );\nvoid LAPACK_sgesv( lapack_int* n, lapack_int* nrhs, float* a, lapack_int* lda,\n                   lapack_int* ipiv, float* b, lapack_int* ldb,\n                   lapack_int *info );\nvoid LAPACK_dgesv( lapack_int* n, lapack_int* nrhs, double* a, lapack_int* lda,\n                   lapack_int* ipiv, double* b, lapack_int* ldb,\n                   lapack_int *info );\nvoid LAPACK_cgesv( lapack_int* n, lapack_int* nrhs, lapack_complex_float* a,\n                   lapack_int* lda, lapack_int* ipiv, lapack_complex_float* b,\n                   lapack_int* ldb, lapack_int *info );\nvoid LAPACK_zgesv( lapack_int* n, lapack_int* nrhs, lapack_complex_double* a,\n                   lapack_int* lda, lapack_int* ipiv, lapack_complex_double* b,\n                   lapack_int* ldb, lapack_int *info );\nvoid LAPACK_dsgesv( lapack_int* n, lapack_int* nrhs, double* a, lapack_int* lda,\n                    lapack_int* ipiv, double* b, lapack_int* ldb, double* x,\n                    lapack_int* ldx, double* work, float* swork,\n                    lapack_int* iter, lapack_int *info );\nvoid LAPACK_zcgesv( lapack_int* n, lapack_int* nrhs, lapack_complex_double* a,\n                    lapack_int* lda, lapack_int* ipiv, lapack_complex_double* b,\n                    lapack_int* ldb, lapack_complex_double* x, lapack_int* ldx,\n                    lapack_complex_double* work, lapack_complex_float* swork,\n                    double* rwork, lapack_int* iter, lapack_int *info );\nvoid LAPACK_sgesvx( char* fact, char* trans, lapack_int* n, lapack_int* nrhs,\n                    float* a, lapack_int* lda, float* af, lapack_int* ldaf,\n                    lapack_int* ipiv, char* equed, float* r, float* c, float* b,\n                    lapack_int* ldb, float* x, lapack_int* ldx, float* rcond,\n                    float* ferr, float* berr, float* work, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_dgesvx( char* fact, char* trans, lapack_int* n, lapack_int* nrhs,\n                    double* a, lapack_int* lda, double* af, lapack_int* ldaf,\n                    lapack_int* ipiv, char* equed, double* r, double* c,\n                    double* b, lapack_int* ldb, double* x, lapack_int* ldx,\n                    double* rcond, double* ferr, double* berr, double* work,\n                    lapack_int* iwork, lapack_int *info );\nvoid LAPACK_cgesvx( char* fact, char* trans, lapack_int* n, lapack_int* nrhs,\n                    lapack_complex_float* a, lapack_int* lda,\n                    lapack_complex_float* af, lapack_int* ldaf,\n                    lapack_int* ipiv, char* equed, float* r, float* c,\n                    lapack_complex_float* b, lapack_int* ldb,\n                    lapack_complex_float* x, lapack_int* ldx, float* rcond,\n                    float* ferr, float* berr, lapack_complex_float* work,\n                    float* rwork, lapack_int *info );\nvoid LAPACK_zgesvx( char* fact, char* trans, lapack_int* n, lapack_int* nrhs,\n                    lapack_complex_double* a, lapack_int* lda,\n                    lapack_complex_double* af, lapack_int* ldaf,\n                    lapack_int* ipiv, char* equed, double* r, double* c,\n                    lapack_complex_double* b, lapack_int* ldb,\n                    lapack_complex_double* x, lapack_int* ldx, double* rcond,\n                    double* ferr, double* berr, lapack_complex_double* work,\n                    double* rwork, lapack_int *info );\nvoid LAPACK_dgesvxx( char* fact, char* trans, lapack_int* n, lapack_int* nrhs,\n                     double* a, lapack_int* lda, double* af, lapack_int* ldaf,\n                     lapack_int* ipiv, char* equed, double* r, double* c,\n                     double* b, lapack_int* ldb, double* x, lapack_int* ldx,\n                     double* rcond, double* rpvgrw, double* berr,\n                     lapack_int* n_err_bnds, double* err_bnds_norm,\n                     double* err_bnds_comp, lapack_int* nparams, double* params,\n                     double* work, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_sgesvxx( char* fact, char* trans, lapack_int* n, lapack_int* nrhs,\n                     float* a, lapack_int* lda, float* af, lapack_int* ldaf,\n                     lapack_int* ipiv, char* equed, float* r, float* c,\n                     float* b, lapack_int* ldb, float* x, lapack_int* ldx,\n                     float* rcond, float* rpvgrw, float* berr,\n                     lapack_int* n_err_bnds, float* err_bnds_norm,\n                     float* err_bnds_comp, lapack_int* nparams, float* params,\n                     float* work, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_zgesvxx( char* fact, char* trans, lapack_int* n, lapack_int* nrhs,\n                     lapack_complex_double* a, lapack_int* lda,\n                     lapack_complex_double* af, lapack_int* ldaf,\n                     lapack_int* ipiv, char* equed, double* r, double* c,\n                     lapack_complex_double* b, lapack_int* ldb,\n                     lapack_complex_double* x, lapack_int* ldx, double* rcond,\n                     double* rpvgrw, double* berr, lapack_int* n_err_bnds,\n                     double* err_bnds_norm, double* err_bnds_comp,\n                     lapack_int* nparams, double* params,\n                     lapack_complex_double* work, double* rwork,\n                     lapack_int *info );\nvoid LAPACK_cgesvxx( char* fact, char* trans, lapack_int* n, lapack_int* nrhs,\n                     lapack_complex_float* a, lapack_int* lda,\n                     lapack_complex_float* af, lapack_int* ldaf,\n                     lapack_int* ipiv, char* equed, float* r, float* c,\n                     lapack_complex_float* b, lapack_int* ldb,\n                     lapack_complex_float* x, lapack_int* ldx, float* rcond,\n                     float* rpvgrw, float* berr, lapack_int* n_err_bnds,\n                     float* err_bnds_norm, float* err_bnds_comp,\n                     lapack_int* nparams, float* params,\n                     lapack_complex_float* work, float* rwork,\n                     lapack_int *info );\nvoid LAPACK_sgbsv( lapack_int* n, lapack_int* kl, lapack_int* ku,\n                   lapack_int* nrhs, float* ab, lapack_int* ldab,\n                   lapack_int* ipiv, float* b, lapack_int* ldb,\n                   lapack_int *info );\nvoid LAPACK_dgbsv( lapack_int* n, lapack_int* kl, lapack_int* ku,\n                   lapack_int* nrhs, double* ab, lapack_int* ldab,\n                   lapack_int* ipiv, double* b, lapack_int* ldb,\n                   lapack_int *info );\nvoid LAPACK_cgbsv( lapack_int* n, lapack_int* kl, lapack_int* ku,\n                   lapack_int* nrhs, lapack_complex_float* ab, lapack_int* ldab,\n                   lapack_int* ipiv, lapack_complex_float* b, lapack_int* ldb,\n                   lapack_int *info );\nvoid LAPACK_zgbsv( lapack_int* n, lapack_int* kl, lapack_int* ku,\n                   lapack_int* nrhs, lapack_complex_double* ab,\n                   lapack_int* ldab, lapack_int* ipiv, lapack_complex_double* b,\n                   lapack_int* ldb, lapack_int *info );\nvoid LAPACK_sgbsvx( char* fact, char* trans, lapack_int* n, lapack_int* kl,\n                    lapack_int* ku, lapack_int* nrhs, float* ab,\n                    lapack_int* ldab, float* afb, lapack_int* ldafb,\n                    lapack_int* ipiv, char* equed, float* r, float* c, float* b,\n                    lapack_int* ldb, float* x, lapack_int* ldx, float* rcond,\n                    float* ferr, float* berr, float* work, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_dgbsvx( char* fact, char* trans, lapack_int* n, lapack_int* kl,\n                    lapack_int* ku, lapack_int* nrhs, double* ab,\n                    lapack_int* ldab, double* afb, lapack_int* ldafb,\n                    lapack_int* ipiv, char* equed, double* r, double* c,\n                    double* b, lapack_int* ldb, double* x, lapack_int* ldx,\n                    double* rcond, double* ferr, double* berr, double* work,\n                    lapack_int* iwork, lapack_int *info );\nvoid LAPACK_cgbsvx( char* fact, char* trans, lapack_int* n, lapack_int* kl,\n                    lapack_int* ku, lapack_int* nrhs, lapack_complex_float* ab,\n                    lapack_int* ldab, lapack_complex_float* afb,\n                    lapack_int* ldafb, lapack_int* ipiv, char* equed, float* r,\n                    float* c, lapack_complex_float* b, lapack_int* ldb,\n                    lapack_complex_float* x, lapack_int* ldx, float* rcond,\n                    float* ferr, float* berr, lapack_complex_float* work,\n                    float* rwork, lapack_int *info );\nvoid LAPACK_zgbsvx( char* fact, char* trans, lapack_int* n, lapack_int* kl,\n                    lapack_int* ku, lapack_int* nrhs, lapack_complex_double* ab,\n                    lapack_int* ldab, lapack_complex_double* afb,\n                    lapack_int* ldafb, lapack_int* ipiv, char* equed, double* r,\n                    double* c, lapack_complex_double* b, lapack_int* ldb,\n                    lapack_complex_double* x, lapack_int* ldx, double* rcond,\n                    double* ferr, double* berr, lapack_complex_double* work,\n                    double* rwork, lapack_int *info );\nvoid LAPACK_dgbsvxx( char* fact, char* trans, lapack_int* n, lapack_int* kl,\n                     lapack_int* ku, lapack_int* nrhs, double* ab,\n                     lapack_int* ldab, double* afb, lapack_int* ldafb,\n                     lapack_int* ipiv, char* equed, double* r, double* c,\n                     double* b, lapack_int* ldb, double* x, lapack_int* ldx,\n                     double* rcond, double* rpvgrw, double* berr,\n                     lapack_int* n_err_bnds, double* err_bnds_norm,\n                     double* err_bnds_comp, lapack_int* nparams, double* params,\n                     double* work, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_sgbsvxx( char* fact, char* trans, lapack_int* n, lapack_int* kl,\n                     lapack_int* ku, lapack_int* nrhs, float* ab,\n                     lapack_int* ldab, float* afb, lapack_int* ldafb,\n                     lapack_int* ipiv, char* equed, float* r, float* c,\n                     float* b, lapack_int* ldb, float* x, lapack_int* ldx,\n                     float* rcond, float* rpvgrw, float* berr,\n                     lapack_int* n_err_bnds, float* err_bnds_norm,\n                     float* err_bnds_comp, lapack_int* nparams, float* params,\n                     float* work, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_zgbsvxx( char* fact, char* trans, lapack_int* n, lapack_int* kl,\n                     lapack_int* ku, lapack_int* nrhs,\n                     lapack_complex_double* ab, lapack_int* ldab,\n                     lapack_complex_double* afb, lapack_int* ldafb,\n                     lapack_int* ipiv, char* equed, double* r, double* c,\n                     lapack_complex_double* b, lapack_int* ldb,\n                     lapack_complex_double* x, lapack_int* ldx, double* rcond,\n                     double* rpvgrw, double* berr, lapack_int* n_err_bnds,\n                     double* err_bnds_norm, double* err_bnds_comp,\n                     lapack_int* nparams, double* params,\n                     lapack_complex_double* work, double* rwork,\n                     lapack_int *info );\nvoid LAPACK_cgbsvxx( char* fact, char* trans, lapack_int* n, lapack_int* kl,\n                     lapack_int* ku, lapack_int* nrhs, lapack_complex_float* ab,\n                     lapack_int* ldab, lapack_complex_float* afb,\n                     lapack_int* ldafb, lapack_int* ipiv, char* equed, float* r,\n                     float* c, lapack_complex_float* b, lapack_int* ldb,\n                     lapack_complex_float* x, lapack_int* ldx, float* rcond,\n                     float* rpvgrw, float* berr, lapack_int* n_err_bnds,\n                     float* err_bnds_norm, float* err_bnds_comp,\n                     lapack_int* nparams, float* params,\n                     lapack_complex_float* work, float* rwork,\n                     lapack_int *info );\nvoid LAPACK_sgtsv( lapack_int* n, lapack_int* nrhs, float* dl, float* d,\n                   float* du, float* b, lapack_int* ldb, lapack_int *info );\nvoid LAPACK_dgtsv( lapack_int* n, lapack_int* nrhs, double* dl, double* d,\n                   double* du, double* b, lapack_int* ldb, lapack_int *info );\nvoid LAPACK_cgtsv( lapack_int* n, lapack_int* nrhs, lapack_complex_float* dl,\n                   lapack_complex_float* d, lapack_complex_float* du,\n                   lapack_complex_float* b, lapack_int* ldb, lapack_int *info );\nvoid LAPACK_zgtsv( lapack_int* n, lapack_int* nrhs, lapack_complex_double* dl,\n                   lapack_complex_double* d, lapack_complex_double* du,\n                   lapack_complex_double* b, lapack_int* ldb,\n                   lapack_int *info );\nvoid LAPACK_sgtsvx( char* fact, char* trans, lapack_int* n, lapack_int* nrhs,\n                    const float* dl, const float* d, const float* du,\n                    float* dlf, float* df, float* duf, float* du2,\n                    lapack_int* ipiv, const float* b, lapack_int* ldb, float* x,\n                    lapack_int* ldx, float* rcond, float* ferr, float* berr,\n                    float* work, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_dgtsvx( char* fact, char* trans, lapack_int* n, lapack_int* nrhs,\n                    const double* dl, const double* d, const double* du,\n                    double* dlf, double* df, double* duf, double* du2,\n                    lapack_int* ipiv, const double* b, lapack_int* ldb,\n                    double* x, lapack_int* ldx, double* rcond, double* ferr,\n                    double* berr, double* work, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_cgtsvx( char* fact, char* trans, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_float* dl,\n                    const lapack_complex_float* d,\n                    const lapack_complex_float* du, lapack_complex_float* dlf,\n                    lapack_complex_float* df, lapack_complex_float* duf,\n                    lapack_complex_float* du2, lapack_int* ipiv,\n                    const lapack_complex_float* b, lapack_int* ldb,\n                    lapack_complex_float* x, lapack_int* ldx, float* rcond,\n                    float* ferr, float* berr, lapack_complex_float* work,\n                    float* rwork, lapack_int *info );\nvoid LAPACK_zgtsvx( char* fact, char* trans, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_double* dl,\n                    const lapack_complex_double* d,\n                    const lapack_complex_double* du, lapack_complex_double* dlf,\n                    lapack_complex_double* df, lapack_complex_double* duf,\n                    lapack_complex_double* du2, lapack_int* ipiv,\n                    const lapack_complex_double* b, lapack_int* ldb,\n                    lapack_complex_double* x, lapack_int* ldx, double* rcond,\n                    double* ferr, double* berr, lapack_complex_double* work,\n                    double* rwork, lapack_int *info );\nvoid LAPACK_sposv( char* uplo, lapack_int* n, lapack_int* nrhs, float* a,\n                   lapack_int* lda, float* b, lapack_int* ldb,\n                   lapack_int *info );\nvoid LAPACK_dposv( char* uplo, lapack_int* n, lapack_int* nrhs, double* a,\n                   lapack_int* lda, double* b, lapack_int* ldb,\n                   lapack_int *info );\nvoid LAPACK_cposv( char* uplo, lapack_int* n, lapack_int* nrhs,\n                   lapack_complex_float* a, lapack_int* lda,\n                   lapack_complex_float* b, lapack_int* ldb, lapack_int *info );\nvoid LAPACK_zposv( char* uplo, lapack_int* n, lapack_int* nrhs,\n                   lapack_complex_double* a, lapack_int* lda,\n                   lapack_complex_double* b, lapack_int* ldb,\n                   lapack_int *info );\nvoid LAPACK_dsposv( char* uplo, lapack_int* n, lapack_int* nrhs, double* a,\n                    lapack_int* lda, double* b, lapack_int* ldb, double* x,\n                    lapack_int* ldx, double* work, float* swork,\n                    lapack_int* iter, lapack_int *info );\nvoid LAPACK_zcposv( char* uplo, lapack_int* n, lapack_int* nrhs,\n                    lapack_complex_double* a, lapack_int* lda,\n                    lapack_complex_double* b, lapack_int* ldb,\n                    lapack_complex_double* x, lapack_int* ldx,\n                    lapack_complex_double* work, lapack_complex_float* swork,\n                    double* rwork, lapack_int* iter, lapack_int *info );\nvoid LAPACK_sposvx( char* fact, char* uplo, lapack_int* n, lapack_int* nrhs,\n                    float* a, lapack_int* lda, float* af, lapack_int* ldaf,\n                    char* equed, float* s, float* b, lapack_int* ldb, float* x,\n                    lapack_int* ldx, float* rcond, float* ferr, float* berr,\n                    float* work, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_dposvx( char* fact, char* uplo, lapack_int* n, lapack_int* nrhs,\n                    double* a, lapack_int* lda, double* af, lapack_int* ldaf,\n                    char* equed, double* s, double* b, lapack_int* ldb,\n                    double* x, lapack_int* ldx, double* rcond, double* ferr,\n                    double* berr, double* work, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_cposvx( char* fact, char* uplo, lapack_int* n, lapack_int* nrhs,\n                    lapack_complex_float* a, lapack_int* lda,\n                    lapack_complex_float* af, lapack_int* ldaf, char* equed,\n                    float* s, lapack_complex_float* b, lapack_int* ldb,\n                    lapack_complex_float* x, lapack_int* ldx, float* rcond,\n                    float* ferr, float* berr, lapack_complex_float* work,\n                    float* rwork, lapack_int *info );\nvoid LAPACK_zposvx( char* fact, char* uplo, lapack_int* n, lapack_int* nrhs,\n                    lapack_complex_double* a, lapack_int* lda,\n                    lapack_complex_double* af, lapack_int* ldaf, char* equed,\n                    double* s, lapack_complex_double* b, lapack_int* ldb,\n                    lapack_complex_double* x, lapack_int* ldx, double* rcond,\n                    double* ferr, double* berr, lapack_complex_double* work,\n                    double* rwork, lapack_int *info );\nvoid LAPACK_dposvxx( char* fact, char* uplo, lapack_int* n, lapack_int* nrhs,\n                     double* a, lapack_int* lda, double* af, lapack_int* ldaf,\n                     char* equed, double* s, double* b, lapack_int* ldb,\n                     double* x, lapack_int* ldx, double* rcond, double* rpvgrw,\n                     double* berr, lapack_int* n_err_bnds,\n                     double* err_bnds_norm, double* err_bnds_comp,\n                     lapack_int* nparams, double* params, double* work,\n                     lapack_int* iwork, lapack_int *info );\nvoid LAPACK_sposvxx( char* fact, char* uplo, lapack_int* n, lapack_int* nrhs,\n                     float* a, lapack_int* lda, float* af, lapack_int* ldaf,\n                     char* equed, float* s, float* b, lapack_int* ldb, float* x,\n                     lapack_int* ldx, float* rcond, float* rpvgrw, float* berr,\n                     lapack_int* n_err_bnds, float* err_bnds_norm,\n                     float* err_bnds_comp, lapack_int* nparams, float* params,\n                     float* work, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_zposvxx( char* fact, char* uplo, lapack_int* n, lapack_int* nrhs,\n                     lapack_complex_double* a, lapack_int* lda,\n                     lapack_complex_double* af, lapack_int* ldaf, char* equed,\n                     double* s, lapack_complex_double* b, lapack_int* ldb,\n                     lapack_complex_double* x, lapack_int* ldx, double* rcond,\n                     double* rpvgrw, double* berr, lapack_int* n_err_bnds,\n                     double* err_bnds_norm, double* err_bnds_comp,\n                     lapack_int* nparams, double* params,\n                     lapack_complex_double* work, double* rwork,\n                     lapack_int *info );\nvoid LAPACK_cposvxx( char* fact, char* uplo, lapack_int* n, lapack_int* nrhs,\n                     lapack_complex_float* a, lapack_int* lda,\n                     lapack_complex_float* af, lapack_int* ldaf, char* equed,\n                     float* s, lapack_complex_float* b, lapack_int* ldb,\n                     lapack_complex_float* x, lapack_int* ldx, float* rcond,\n                     float* rpvgrw, float* berr, lapack_int* n_err_bnds,\n                     float* err_bnds_norm, float* err_bnds_comp,\n                     lapack_int* nparams, float* params,\n                     lapack_complex_float* work, float* rwork,\n                     lapack_int *info );\nvoid LAPACK_sppsv( char* uplo, lapack_int* n, lapack_int* nrhs, float* ap,\n                   float* b, lapack_int* ldb, lapack_int *info );\nvoid LAPACK_dppsv( char* uplo, lapack_int* n, lapack_int* nrhs, double* ap,\n                   double* b, lapack_int* ldb, lapack_int *info );\nvoid LAPACK_cppsv( char* uplo, lapack_int* n, lapack_int* nrhs,\n                   lapack_complex_float* ap, lapack_complex_float* b,\n                   lapack_int* ldb, lapack_int *info );\nvoid LAPACK_zppsv( char* uplo, lapack_int* n, lapack_int* nrhs,\n                   lapack_complex_double* ap, lapack_complex_double* b,\n                   lapack_int* ldb, lapack_int *info );\nvoid LAPACK_sppsvx( char* fact, char* uplo, lapack_int* n, lapack_int* nrhs,\n                    float* ap, float* afp, char* equed, float* s, float* b,\n                    lapack_int* ldb, float* x, lapack_int* ldx, float* rcond,\n                    float* ferr, float* berr, float* work, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_dppsvx( char* fact, char* uplo, lapack_int* n, lapack_int* nrhs,\n                    double* ap, double* afp, char* equed, double* s, double* b,\n                    lapack_int* ldb, double* x, lapack_int* ldx, double* rcond,\n                    double* ferr, double* berr, double* work, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_cppsvx( char* fact, char* uplo, lapack_int* n, lapack_int* nrhs,\n                    lapack_complex_float* ap, lapack_complex_float* afp,\n                    char* equed, float* s, lapack_complex_float* b,\n                    lapack_int* ldb, lapack_complex_float* x, lapack_int* ldx,\n                    float* rcond, float* ferr, float* berr,\n                    lapack_complex_float* work, float* rwork,\n                    lapack_int *info );\nvoid LAPACK_zppsvx( char* fact, char* uplo, lapack_int* n, lapack_int* nrhs,\n                    lapack_complex_double* ap, lapack_complex_double* afp,\n                    char* equed, double* s, lapack_complex_double* b,\n                    lapack_int* ldb, lapack_complex_double* x, lapack_int* ldx,\n                    double* rcond, double* ferr, double* berr,\n                    lapack_complex_double* work, double* rwork,\n                    lapack_int *info );\nvoid LAPACK_spbsv( char* uplo, lapack_int* n, lapack_int* kd, lapack_int* nrhs,\n                   float* ab, lapack_int* ldab, float* b, lapack_int* ldb,\n                   lapack_int *info );\nvoid LAPACK_dpbsv( char* uplo, lapack_int* n, lapack_int* kd, lapack_int* nrhs,\n                   double* ab, lapack_int* ldab, double* b, lapack_int* ldb,\n                   lapack_int *info );\nvoid LAPACK_cpbsv( char* uplo, lapack_int* n, lapack_int* kd, lapack_int* nrhs,\n                   lapack_complex_float* ab, lapack_int* ldab,\n                   lapack_complex_float* b, lapack_int* ldb, lapack_int *info );\nvoid LAPACK_zpbsv( char* uplo, lapack_int* n, lapack_int* kd, lapack_int* nrhs,\n                   lapack_complex_double* ab, lapack_int* ldab,\n                   lapack_complex_double* b, lapack_int* ldb,\n                   lapack_int *info );\nvoid LAPACK_spbsvx( char* fact, char* uplo, lapack_int* n, lapack_int* kd,\n                    lapack_int* nrhs, float* ab, lapack_int* ldab, float* afb,\n                    lapack_int* ldafb, char* equed, float* s, float* b,\n                    lapack_int* ldb, float* x, lapack_int* ldx, float* rcond,\n                    float* ferr, float* berr, float* work, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_dpbsvx( char* fact, char* uplo, lapack_int* n, lapack_int* kd,\n                    lapack_int* nrhs, double* ab, lapack_int* ldab, double* afb,\n                    lapack_int* ldafb, char* equed, double* s, double* b,\n                    lapack_int* ldb, double* x, lapack_int* ldx, double* rcond,\n                    double* ferr, double* berr, double* work, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_cpbsvx( char* fact, char* uplo, lapack_int* n, lapack_int* kd,\n                    lapack_int* nrhs, lapack_complex_float* ab,\n                    lapack_int* ldab, lapack_complex_float* afb,\n                    lapack_int* ldafb, char* equed, float* s,\n                    lapack_complex_float* b, lapack_int* ldb,\n                    lapack_complex_float* x, lapack_int* ldx, float* rcond,\n                    float* ferr, float* berr, lapack_complex_float* work,\n                    float* rwork, lapack_int *info );\nvoid LAPACK_zpbsvx( char* fact, char* uplo, lapack_int* n, lapack_int* kd,\n                    lapack_int* nrhs, lapack_complex_double* ab,\n                    lapack_int* ldab, lapack_complex_double* afb,\n                    lapack_int* ldafb, char* equed, double* s,\n                    lapack_complex_double* b, lapack_int* ldb,\n                    lapack_complex_double* x, lapack_int* ldx, double* rcond,\n                    double* ferr, double* berr, lapack_complex_double* work,\n                    double* rwork, lapack_int *info );\nvoid LAPACK_sptsv( lapack_int* n, lapack_int* nrhs, float* d, float* e,\n                   float* b, lapack_int* ldb, lapack_int *info );\nvoid LAPACK_dptsv( lapack_int* n, lapack_int* nrhs, double* d, double* e,\n                   double* b, lapack_int* ldb, lapack_int *info );\nvoid LAPACK_cptsv( lapack_int* n, lapack_int* nrhs, float* d,\n                   lapack_complex_float* e, lapack_complex_float* b,\n                   lapack_int* ldb, lapack_int *info );\nvoid LAPACK_zptsv( lapack_int* n, lapack_int* nrhs, double* d,\n                   lapack_complex_double* e, lapack_complex_double* b,\n                   lapack_int* ldb, lapack_int *info );\nvoid LAPACK_sptsvx( char* fact, lapack_int* n, lapack_int* nrhs, const float* d,\n                    const float* e, float* df, float* ef, const float* b,\n                    lapack_int* ldb, float* x, lapack_int* ldx, float* rcond,\n                    float* ferr, float* berr, float* work, lapack_int *info );\nvoid LAPACK_dptsvx( char* fact, lapack_int* n, lapack_int* nrhs,\n                    const double* d, const double* e, double* df, double* ef,\n                    const double* b, lapack_int* ldb, double* x,\n                    lapack_int* ldx, double* rcond, double* ferr, double* berr,\n                    double* work, lapack_int *info );\nvoid LAPACK_cptsvx( char* fact, lapack_int* n, lapack_int* nrhs, const float* d,\n                    const lapack_complex_float* e, float* df,\n                    lapack_complex_float* ef, const lapack_complex_float* b,\n                    lapack_int* ldb, lapack_complex_float* x, lapack_int* ldx,\n                    float* rcond, float* ferr, float* berr,\n                    lapack_complex_float* work, float* rwork,\n                    lapack_int *info );\nvoid LAPACK_zptsvx( char* fact, lapack_int* n, lapack_int* nrhs,\n                    const double* d, const lapack_complex_double* e, double* df,\n                    lapack_complex_double* ef, const lapack_complex_double* b,\n                    lapack_int* ldb, lapack_complex_double* x, lapack_int* ldx,\n                    double* rcond, double* ferr, double* berr,\n                    lapack_complex_double* work, double* rwork,\n                    lapack_int *info );\nvoid LAPACK_ssysv( char* uplo, lapack_int* n, lapack_int* nrhs, float* a,\n                   lapack_int* lda, lapack_int* ipiv, float* b, lapack_int* ldb,\n                   float* work, lapack_int* lwork, lapack_int *info );\nvoid LAPACK_dsysv( char* uplo, lapack_int* n, lapack_int* nrhs, double* a,\n                   lapack_int* lda, lapack_int* ipiv, double* b,\n                   lapack_int* ldb, double* work, lapack_int* lwork,\n                   lapack_int *info );\nvoid LAPACK_csysv( char* uplo, lapack_int* n, lapack_int* nrhs,\n                   lapack_complex_float* a, lapack_int* lda, lapack_int* ipiv,\n                   lapack_complex_float* b, lapack_int* ldb,\n                   lapack_complex_float* work, lapack_int* lwork,\n                   lapack_int *info );\nvoid LAPACK_zsysv( char* uplo, lapack_int* n, lapack_int* nrhs,\n                   lapack_complex_double* a, lapack_int* lda, lapack_int* ipiv,\n                   lapack_complex_double* b, lapack_int* ldb,\n                   lapack_complex_double* work, lapack_int* lwork,\n                   lapack_int *info );\nvoid LAPACK_ssysvx( char* fact, char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const float* a, lapack_int* lda, float* af,\n                    lapack_int* ldaf, lapack_int* ipiv, const float* b,\n                    lapack_int* ldb, float* x, lapack_int* ldx, float* rcond,\n                    float* ferr, float* berr, float* work, lapack_int* lwork,\n                    lapack_int* iwork, lapack_int *info );\nvoid LAPACK_dsysvx( char* fact, char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const double* a, lapack_int* lda, double* af,\n                    lapack_int* ldaf, lapack_int* ipiv, const double* b,\n                    lapack_int* ldb, double* x, lapack_int* ldx, double* rcond,\n                    double* ferr, double* berr, double* work, lapack_int* lwork,\n                    lapack_int* iwork, lapack_int *info );\nvoid LAPACK_csysvx( char* fact, char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_float* a, lapack_int* lda,\n                    lapack_complex_float* af, lapack_int* ldaf,\n                    lapack_int* ipiv, const lapack_complex_float* b,\n                    lapack_int* ldb, lapack_complex_float* x, lapack_int* ldx,\n                    float* rcond, float* ferr, float* berr,\n                    lapack_complex_float* work, lapack_int* lwork, float* rwork,\n                    lapack_int *info );\nvoid LAPACK_zsysvx( char* fact, char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_double* a, lapack_int* lda,\n                    lapack_complex_double* af, lapack_int* ldaf,\n                    lapack_int* ipiv, const lapack_complex_double* b,\n                    lapack_int* ldb, lapack_complex_double* x, lapack_int* ldx,\n                    double* rcond, double* ferr, double* berr,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    double* rwork, lapack_int *info );\nvoid LAPACK_dsysvxx( char* fact, char* uplo, lapack_int* n, lapack_int* nrhs,\n                     double* a, lapack_int* lda, double* af, lapack_int* ldaf,\n                     lapack_int* ipiv, char* equed, double* s, double* b,\n                     lapack_int* ldb, double* x, lapack_int* ldx, double* rcond,\n                     double* rpvgrw, double* berr, lapack_int* n_err_bnds,\n                     double* err_bnds_norm, double* err_bnds_comp,\n                     lapack_int* nparams, double* params, double* work,\n                     lapack_int* iwork, lapack_int *info );\nvoid LAPACK_ssysvxx( char* fact, char* uplo, lapack_int* n, lapack_int* nrhs,\n                     float* a, lapack_int* lda, float* af, lapack_int* ldaf,\n                     lapack_int* ipiv, char* equed, float* s, float* b,\n                     lapack_int* ldb, float* x, lapack_int* ldx, float* rcond,\n                     float* rpvgrw, float* berr, lapack_int* n_err_bnds,\n                     float* err_bnds_norm, float* err_bnds_comp,\n                     lapack_int* nparams, float* params, float* work,\n                     lapack_int* iwork, lapack_int *info );\nvoid LAPACK_zsysvxx( char* fact, char* uplo, lapack_int* n, lapack_int* nrhs,\n                     lapack_complex_double* a, lapack_int* lda,\n                     lapack_complex_double* af, lapack_int* ldaf,\n                     lapack_int* ipiv, char* equed, double* s,\n                     lapack_complex_double* b, lapack_int* ldb,\n                     lapack_complex_double* x, lapack_int* ldx, double* rcond,\n                     double* rpvgrw, double* berr, lapack_int* n_err_bnds,\n                     double* err_bnds_norm, double* err_bnds_comp,\n                     lapack_int* nparams, double* params,\n                     lapack_complex_double* work, double* rwork,\n                     lapack_int *info );\nvoid LAPACK_csysvxx( char* fact, char* uplo, lapack_int* n, lapack_int* nrhs,\n                     lapack_complex_float* a, lapack_int* lda,\n                     lapack_complex_float* af, lapack_int* ldaf,\n                     lapack_int* ipiv, char* equed, float* s,\n                     lapack_complex_float* b, lapack_int* ldb,\n                     lapack_complex_float* x, lapack_int* ldx, float* rcond,\n                     float* rpvgrw, float* berr, lapack_int* n_err_bnds,\n                     float* err_bnds_norm, float* err_bnds_comp,\n                     lapack_int* nparams, float* params,\n                     lapack_complex_float* work, float* rwork,\n                     lapack_int *info );\nvoid LAPACK_chesv( char* uplo, lapack_int* n, lapack_int* nrhs,\n                   lapack_complex_float* a, lapack_int* lda, lapack_int* ipiv,\n                   lapack_complex_float* b, lapack_int* ldb,\n                   lapack_complex_float* work, lapack_int* lwork,\n                   lapack_int *info );\nvoid LAPACK_zhesv( char* uplo, lapack_int* n, lapack_int* nrhs,\n                   lapack_complex_double* a, lapack_int* lda, lapack_int* ipiv,\n                   lapack_complex_double* b, lapack_int* ldb,\n                   lapack_complex_double* work, lapack_int* lwork,\n                   lapack_int *info );\nvoid LAPACK_chesvx( char* fact, char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_float* a, lapack_int* lda,\n                    lapack_complex_float* af, lapack_int* ldaf,\n                    lapack_int* ipiv, const lapack_complex_float* b,\n                    lapack_int* ldb, lapack_complex_float* x, lapack_int* ldx,\n                    float* rcond, float* ferr, float* berr,\n                    lapack_complex_float* work, lapack_int* lwork, float* rwork,\n                    lapack_int *info );\nvoid LAPACK_zhesvx( char* fact, char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_double* a, lapack_int* lda,\n                    lapack_complex_double* af, lapack_int* ldaf,\n                    lapack_int* ipiv, const lapack_complex_double* b,\n                    lapack_int* ldb, lapack_complex_double* x, lapack_int* ldx,\n                    double* rcond, double* ferr, double* berr,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    double* rwork, lapack_int *info );\nvoid LAPACK_zhesvxx( char* fact, char* uplo, lapack_int* n, lapack_int* nrhs,\n                     lapack_complex_double* a, lapack_int* lda,\n                     lapack_complex_double* af, lapack_int* ldaf,\n                     lapack_int* ipiv, char* equed, double* s,\n                     lapack_complex_double* b, lapack_int* ldb,\n                     lapack_complex_double* x, lapack_int* ldx, double* rcond,\n                     double* rpvgrw, double* berr, lapack_int* n_err_bnds,\n                     double* err_bnds_norm, double* err_bnds_comp,\n                     lapack_int* nparams, double* params,\n                     lapack_complex_double* work, double* rwork,\n                     lapack_int *info );\nvoid LAPACK_chesvxx( char* fact, char* uplo, lapack_int* n, lapack_int* nrhs,\n                     lapack_complex_float* a, lapack_int* lda,\n                     lapack_complex_float* af, lapack_int* ldaf,\n                     lapack_int* ipiv, char* equed, float* s,\n                     lapack_complex_float* b, lapack_int* ldb,\n                     lapack_complex_float* x, lapack_int* ldx, float* rcond,\n                     float* rpvgrw, float* berr, lapack_int* n_err_bnds,\n                     float* err_bnds_norm, float* err_bnds_comp,\n                     lapack_int* nparams, float* params,\n                     lapack_complex_float* work, float* rwork,\n                     lapack_int *info );\nvoid LAPACK_sspsv( char* uplo, lapack_int* n, lapack_int* nrhs, float* ap,\n                   lapack_int* ipiv, float* b, lapack_int* ldb,\n                   lapack_int *info );\nvoid LAPACK_dspsv( char* uplo, lapack_int* n, lapack_int* nrhs, double* ap,\n                   lapack_int* ipiv, double* b, lapack_int* ldb,\n                   lapack_int *info );\nvoid LAPACK_cspsv( char* uplo, lapack_int* n, lapack_int* nrhs,\n                   lapack_complex_float* ap, lapack_int* ipiv,\n                   lapack_complex_float* b, lapack_int* ldb, lapack_int *info );\nvoid LAPACK_zspsv( char* uplo, lapack_int* n, lapack_int* nrhs,\n                   lapack_complex_double* ap, lapack_int* ipiv,\n                   lapack_complex_double* b, lapack_int* ldb,\n                   lapack_int *info );\nvoid LAPACK_sspsvx( char* fact, char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const float* ap, float* afp, lapack_int* ipiv,\n                    const float* b, lapack_int* ldb, float* x, lapack_int* ldx,\n                    float* rcond, float* ferr, float* berr, float* work,\n                    lapack_int* iwork, lapack_int *info );\nvoid LAPACK_dspsvx( char* fact, char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const double* ap, double* afp, lapack_int* ipiv,\n                    const double* b, lapack_int* ldb, double* x,\n                    lapack_int* ldx, double* rcond, double* ferr, double* berr,\n                    double* work, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_cspsvx( char* fact, char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_float* ap, lapack_complex_float* afp,\n                    lapack_int* ipiv, const lapack_complex_float* b,\n                    lapack_int* ldb, lapack_complex_float* x, lapack_int* ldx,\n                    float* rcond, float* ferr, float* berr,\n                    lapack_complex_float* work, float* rwork,\n                    lapack_int *info );\nvoid LAPACK_zspsvx( char* fact, char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_double* ap, lapack_complex_double* afp,\n                    lapack_int* ipiv, const lapack_complex_double* b,\n                    lapack_int* ldb, lapack_complex_double* x, lapack_int* ldx,\n                    double* rcond, double* ferr, double* berr,\n                    lapack_complex_double* work, double* rwork,\n                    lapack_int *info );\nvoid LAPACK_chpsv( char* uplo, lapack_int* n, lapack_int* nrhs,\n                   lapack_complex_float* ap, lapack_int* ipiv,\n                   lapack_complex_float* b, lapack_int* ldb, lapack_int *info );\nvoid LAPACK_zhpsv( char* uplo, lapack_int* n, lapack_int* nrhs,\n                   lapack_complex_double* ap, lapack_int* ipiv,\n                   lapack_complex_double* b, lapack_int* ldb,\n                   lapack_int *info );\nvoid LAPACK_chpsvx( char* fact, char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_float* ap, lapack_complex_float* afp,\n                    lapack_int* ipiv, const lapack_complex_float* b,\n                    lapack_int* ldb, lapack_complex_float* x, lapack_int* ldx,\n                    float* rcond, float* ferr, float* berr,\n                    lapack_complex_float* work, float* rwork,\n                    lapack_int *info );\nvoid LAPACK_zhpsvx( char* fact, char* uplo, lapack_int* n, lapack_int* nrhs,\n                    const lapack_complex_double* ap, lapack_complex_double* afp,\n                    lapack_int* ipiv, const lapack_complex_double* b,\n                    lapack_int* ldb, lapack_complex_double* x, lapack_int* ldx,\n                    double* rcond, double* ferr, double* berr,\n                    lapack_complex_double* work, double* rwork,\n                    lapack_int *info );\nvoid LAPACK_sgeqrf( lapack_int* m, lapack_int* n, float* a, lapack_int* lda,\n                    float* tau, float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_dgeqrf( lapack_int* m, lapack_int* n, double* a, lapack_int* lda,\n                    double* tau, double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_cgeqrf( lapack_int* m, lapack_int* n, lapack_complex_float* a,\n                    lapack_int* lda, lapack_complex_float* tau,\n                    lapack_complex_float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_zgeqrf( lapack_int* m, lapack_int* n, lapack_complex_double* a,\n                    lapack_int* lda, lapack_complex_double* tau,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_sgeqpf( lapack_int* m, lapack_int* n, float* a, lapack_int* lda,\n                    lapack_int* jpvt, float* tau, float* work,\n                    lapack_int *info );\nvoid LAPACK_dgeqpf( lapack_int* m, lapack_int* n, double* a, lapack_int* lda,\n                    lapack_int* jpvt, double* tau, double* work,\n                    lapack_int *info );\nvoid LAPACK_cgeqpf( lapack_int* m, lapack_int* n, lapack_complex_float* a,\n                    lapack_int* lda, lapack_int* jpvt,\n                    lapack_complex_float* tau, lapack_complex_float* work,\n                    float* rwork, lapack_int *info );\nvoid LAPACK_zgeqpf( lapack_int* m, lapack_int* n, lapack_complex_double* a,\n                    lapack_int* lda, lapack_int* jpvt,\n                    lapack_complex_double* tau, lapack_complex_double* work,\n                    double* rwork, lapack_int *info );\nvoid LAPACK_sgeqp3( lapack_int* m, lapack_int* n, float* a, lapack_int* lda,\n                    lapack_int* jpvt, float* tau, float* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_dgeqp3( lapack_int* m, lapack_int* n, double* a, lapack_int* lda,\n                    lapack_int* jpvt, double* tau, double* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_cgeqp3( lapack_int* m, lapack_int* n, lapack_complex_float* a,\n                    lapack_int* lda, lapack_int* jpvt,\n                    lapack_complex_float* tau, lapack_complex_float* work,\n                    lapack_int* lwork, float* rwork, lapack_int *info );\nvoid LAPACK_zgeqp3( lapack_int* m, lapack_int* n, lapack_complex_double* a,\n                    lapack_int* lda, lapack_int* jpvt,\n                    lapack_complex_double* tau, lapack_complex_double* work,\n                    lapack_int* lwork, double* rwork, lapack_int *info );\nvoid LAPACK_sorgqr( lapack_int* m, lapack_int* n, lapack_int* k, float* a,\n                    lapack_int* lda, const float* tau, float* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_dorgqr( lapack_int* m, lapack_int* n, lapack_int* k, double* a,\n                    lapack_int* lda, const double* tau, double* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_sormqr( char* side, char* trans, lapack_int* m, lapack_int* n,\n                    lapack_int* k, const float* a, lapack_int* lda,\n                    const float* tau, float* c, lapack_int* ldc, float* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_dormqr( char* side, char* trans, lapack_int* m, lapack_int* n,\n                    lapack_int* k, const double* a, lapack_int* lda,\n                    const double* tau, double* c, lapack_int* ldc, double* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_cungqr( lapack_int* m, lapack_int* n, lapack_int* k,\n                    lapack_complex_float* a, lapack_int* lda,\n                    const lapack_complex_float* tau, lapack_complex_float* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_zungqr( lapack_int* m, lapack_int* n, lapack_int* k,\n                    lapack_complex_double* a, lapack_int* lda,\n                    const lapack_complex_double* tau,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_cunmqr( char* side, char* trans, lapack_int* m, lapack_int* n,\n                    lapack_int* k, const lapack_complex_float* a,\n                    lapack_int* lda, const lapack_complex_float* tau,\n                    lapack_complex_float* c, lapack_int* ldc,\n                    lapack_complex_float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_zunmqr( char* side, char* trans, lapack_int* m, lapack_int* n,\n                    lapack_int* k, const lapack_complex_double* a,\n                    lapack_int* lda, const lapack_complex_double* tau,\n                    lapack_complex_double* c, lapack_int* ldc,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_sgelqf( lapack_int* m, lapack_int* n, float* a, lapack_int* lda,\n                    float* tau, float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_dgelqf( lapack_int* m, lapack_int* n, double* a, lapack_int* lda,\n                    double* tau, double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_cgelqf( lapack_int* m, lapack_int* n, lapack_complex_float* a,\n                    lapack_int* lda, lapack_complex_float* tau,\n                    lapack_complex_float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_zgelqf( lapack_int* m, lapack_int* n, lapack_complex_double* a,\n                    lapack_int* lda, lapack_complex_double* tau,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_sorglq( lapack_int* m, lapack_int* n, lapack_int* k, float* a,\n                    lapack_int* lda, const float* tau, float* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_dorglq( lapack_int* m, lapack_int* n, lapack_int* k, double* a,\n                    lapack_int* lda, const double* tau, double* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_sormlq( char* side, char* trans, lapack_int* m, lapack_int* n,\n                    lapack_int* k, const float* a, lapack_int* lda,\n                    const float* tau, float* c, lapack_int* ldc, float* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_dormlq( char* side, char* trans, lapack_int* m, lapack_int* n,\n                    lapack_int* k, const double* a, lapack_int* lda,\n                    const double* tau, double* c, lapack_int* ldc, double* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_cunglq( lapack_int* m, lapack_int* n, lapack_int* k,\n                    lapack_complex_float* a, lapack_int* lda,\n                    const lapack_complex_float* tau, lapack_complex_float* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_zunglq( lapack_int* m, lapack_int* n, lapack_int* k,\n                    lapack_complex_double* a, lapack_int* lda,\n                    const lapack_complex_double* tau,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_cunmlq( char* side, char* trans, lapack_int* m, lapack_int* n,\n                    lapack_int* k, const lapack_complex_float* a,\n                    lapack_int* lda, const lapack_complex_float* tau,\n                    lapack_complex_float* c, lapack_int* ldc,\n                    lapack_complex_float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_zunmlq( char* side, char* trans, lapack_int* m, lapack_int* n,\n                    lapack_int* k, const lapack_complex_double* a,\n                    lapack_int* lda, const lapack_complex_double* tau,\n                    lapack_complex_double* c, lapack_int* ldc,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_sgeqlf( lapack_int* m, lapack_int* n, float* a, lapack_int* lda,\n                    float* tau, float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_dgeqlf( lapack_int* m, lapack_int* n, double* a, lapack_int* lda,\n                    double* tau, double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_cgeqlf( lapack_int* m, lapack_int* n, lapack_complex_float* a,\n                    lapack_int* lda, lapack_complex_float* tau,\n                    lapack_complex_float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_zgeqlf( lapack_int* m, lapack_int* n, lapack_complex_double* a,\n                    lapack_int* lda, lapack_complex_double* tau,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_sorgql( lapack_int* m, lapack_int* n, lapack_int* k, float* a,\n                    lapack_int* lda, const float* tau, float* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_dorgql( lapack_int* m, lapack_int* n, lapack_int* k, double* a,\n                    lapack_int* lda, const double* tau, double* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_cungql( lapack_int* m, lapack_int* n, lapack_int* k,\n                    lapack_complex_float* a, lapack_int* lda,\n                    const lapack_complex_float* tau, lapack_complex_float* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_zungql( lapack_int* m, lapack_int* n, lapack_int* k,\n                    lapack_complex_double* a, lapack_int* lda,\n                    const lapack_complex_double* tau,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_sormql( char* side, char* trans, lapack_int* m, lapack_int* n,\n                    lapack_int* k, const float* a, lapack_int* lda,\n                    const float* tau, float* c, lapack_int* ldc, float* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_dormql( char* side, char* trans, lapack_int* m, lapack_int* n,\n                    lapack_int* k, const double* a, lapack_int* lda,\n                    const double* tau, double* c, lapack_int* ldc, double* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_cunmql( char* side, char* trans, lapack_int* m, lapack_int* n,\n                    lapack_int* k, const lapack_complex_float* a,\n                    lapack_int* lda, const lapack_complex_float* tau,\n                    lapack_complex_float* c, lapack_int* ldc,\n                    lapack_complex_float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_zunmql( char* side, char* trans, lapack_int* m, lapack_int* n,\n                    lapack_int* k, const lapack_complex_double* a,\n                    lapack_int* lda, const lapack_complex_double* tau,\n                    lapack_complex_double* c, lapack_int* ldc,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_sgerqf( lapack_int* m, lapack_int* n, float* a, lapack_int* lda,\n                    float* tau, float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_dgerqf( lapack_int* m, lapack_int* n, double* a, lapack_int* lda,\n                    double* tau, double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_cgerqf( lapack_int* m, lapack_int* n, lapack_complex_float* a,\n                    lapack_int* lda, lapack_complex_float* tau,\n                    lapack_complex_float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_zgerqf( lapack_int* m, lapack_int* n, lapack_complex_double* a,\n                    lapack_int* lda, lapack_complex_double* tau,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_sorgrq( lapack_int* m, lapack_int* n, lapack_int* k, float* a,\n                    lapack_int* lda, const float* tau, float* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_dorgrq( lapack_int* m, lapack_int* n, lapack_int* k, double* a,\n                    lapack_int* lda, const double* tau, double* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_cungrq( lapack_int* m, lapack_int* n, lapack_int* k,\n                    lapack_complex_float* a, lapack_int* lda,\n                    const lapack_complex_float* tau, lapack_complex_float* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_zungrq( lapack_int* m, lapack_int* n, lapack_int* k,\n                    lapack_complex_double* a, lapack_int* lda,\n                    const lapack_complex_double* tau,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_sormrq( char* side, char* trans, lapack_int* m, lapack_int* n,\n                    lapack_int* k, const float* a, lapack_int* lda,\n                    const float* tau, float* c, lapack_int* ldc, float* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_dormrq( char* side, char* trans, lapack_int* m, lapack_int* n,\n                    lapack_int* k, const double* a, lapack_int* lda,\n                    const double* tau, double* c, lapack_int* ldc, double* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_cunmrq( char* side, char* trans, lapack_int* m, lapack_int* n,\n                    lapack_int* k, const lapack_complex_float* a,\n                    lapack_int* lda, const lapack_complex_float* tau,\n                    lapack_complex_float* c, lapack_int* ldc,\n                    lapack_complex_float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_zunmrq( char* side, char* trans, lapack_int* m, lapack_int* n,\n                    lapack_int* k, const lapack_complex_double* a,\n                    lapack_int* lda, const lapack_complex_double* tau,\n                    lapack_complex_double* c, lapack_int* ldc,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_stzrzf( lapack_int* m, lapack_int* n, float* a, lapack_int* lda,\n                    float* tau, float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_dtzrzf( lapack_int* m, lapack_int* n, double* a, lapack_int* lda,\n                    double* tau, double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_ctzrzf( lapack_int* m, lapack_int* n, lapack_complex_float* a,\n                    lapack_int* lda, lapack_complex_float* tau,\n                    lapack_complex_float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_ztzrzf( lapack_int* m, lapack_int* n, lapack_complex_double* a,\n                    lapack_int* lda, lapack_complex_double* tau,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_sormrz( char* side, char* trans, lapack_int* m, lapack_int* n,\n                    lapack_int* k, lapack_int* l, const float* a,\n                    lapack_int* lda, const float* tau, float* c,\n                    lapack_int* ldc, float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_dormrz( char* side, char* trans, lapack_int* m, lapack_int* n,\n                    lapack_int* k, lapack_int* l, const double* a,\n                    lapack_int* lda, const double* tau, double* c,\n                    lapack_int* ldc, double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_cunmrz( char* side, char* trans, lapack_int* m, lapack_int* n,\n                    lapack_int* k, lapack_int* l, const lapack_complex_float* a,\n                    lapack_int* lda, const lapack_complex_float* tau,\n                    lapack_complex_float* c, lapack_int* ldc,\n                    lapack_complex_float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_zunmrz( char* side, char* trans, lapack_int* m, lapack_int* n,\n                    lapack_int* k, lapack_int* l,\n                    const lapack_complex_double* a, lapack_int* lda,\n                    const lapack_complex_double* tau, lapack_complex_double* c,\n                    lapack_int* ldc, lapack_complex_double* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_sggqrf( lapack_int* n, lapack_int* m, lapack_int* p, float* a,\n                    lapack_int* lda, float* taua, float* b, lapack_int* ldb,\n                    float* taub, float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_dggqrf( lapack_int* n, lapack_int* m, lapack_int* p, double* a,\n                    lapack_int* lda, double* taua, double* b, lapack_int* ldb,\n                    double* taub, double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_cggqrf( lapack_int* n, lapack_int* m, lapack_int* p,\n                    lapack_complex_float* a, lapack_int* lda,\n                    lapack_complex_float* taua, lapack_complex_float* b,\n                    lapack_int* ldb, lapack_complex_float* taub,\n                    lapack_complex_float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_zggqrf( lapack_int* n, lapack_int* m, lapack_int* p,\n                    lapack_complex_double* a, lapack_int* lda,\n                    lapack_complex_double* taua, lapack_complex_double* b,\n                    lapack_int* ldb, lapack_complex_double* taub,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_sggrqf( lapack_int* m, lapack_int* p, lapack_int* n, float* a,\n                    lapack_int* lda, float* taua, float* b, lapack_int* ldb,\n                    float* taub, float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_dggrqf( lapack_int* m, lapack_int* p, lapack_int* n, double* a,\n                    lapack_int* lda, double* taua, double* b, lapack_int* ldb,\n                    double* taub, double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_cggrqf( lapack_int* m, lapack_int* p, lapack_int* n,\n                    lapack_complex_float* a, lapack_int* lda,\n                    lapack_complex_float* taua, lapack_complex_float* b,\n                    lapack_int* ldb, lapack_complex_float* taub,\n                    lapack_complex_float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_zggrqf( lapack_int* m, lapack_int* p, lapack_int* n,\n                    lapack_complex_double* a, lapack_int* lda,\n                    lapack_complex_double* taua, lapack_complex_double* b,\n                    lapack_int* ldb, lapack_complex_double* taub,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_sgebrd( lapack_int* m, lapack_int* n, float* a, lapack_int* lda,\n                    float* d, float* e, float* tauq, float* taup, float* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_dgebrd( lapack_int* m, lapack_int* n, double* a, lapack_int* lda,\n                    double* d, double* e, double* tauq, double* taup,\n                    double* work, lapack_int* lwork, lapack_int *info );\nvoid LAPACK_cgebrd( lapack_int* m, lapack_int* n, lapack_complex_float* a,\n                    lapack_int* lda, float* d, float* e,\n                    lapack_complex_float* tauq, lapack_complex_float* taup,\n                    lapack_complex_float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_zgebrd( lapack_int* m, lapack_int* n, lapack_complex_double* a,\n                    lapack_int* lda, double* d, double* e,\n                    lapack_complex_double* tauq, lapack_complex_double* taup,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_sgbbrd( char* vect, lapack_int* m, lapack_int* n, lapack_int* ncc,\n                    lapack_int* kl, lapack_int* ku, float* ab, lapack_int* ldab,\n                    float* d, float* e, float* q, lapack_int* ldq, float* pt,\n                    lapack_int* ldpt, float* c, lapack_int* ldc, float* work,\n                    lapack_int *info );\nvoid LAPACK_dgbbrd( char* vect, lapack_int* m, lapack_int* n, lapack_int* ncc,\n                    lapack_int* kl, lapack_int* ku, double* ab,\n                    lapack_int* ldab, double* d, double* e, double* q,\n                    lapack_int* ldq, double* pt, lapack_int* ldpt, double* c,\n                    lapack_int* ldc, double* work, lapack_int *info );\nvoid LAPACK_cgbbrd( char* vect, lapack_int* m, lapack_int* n, lapack_int* ncc,\n                    lapack_int* kl, lapack_int* ku, lapack_complex_float* ab,\n                    lapack_int* ldab, float* d, float* e,\n                    lapack_complex_float* q, lapack_int* ldq,\n                    lapack_complex_float* pt, lapack_int* ldpt,\n                    lapack_complex_float* c, lapack_int* ldc,\n                    lapack_complex_float* work, float* rwork,\n                    lapack_int *info );\nvoid LAPACK_zgbbrd( char* vect, lapack_int* m, lapack_int* n, lapack_int* ncc,\n                    lapack_int* kl, lapack_int* ku, lapack_complex_double* ab,\n                    lapack_int* ldab, double* d, double* e,\n                    lapack_complex_double* q, lapack_int* ldq,\n                    lapack_complex_double* pt, lapack_int* ldpt,\n                    lapack_complex_double* c, lapack_int* ldc,\n                    lapack_complex_double* work, double* rwork,\n                    lapack_int *info );\nvoid LAPACK_sorgbr( char* vect, lapack_int* m, lapack_int* n, lapack_int* k,\n                    float* a, lapack_int* lda, const float* tau, float* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_dorgbr( char* vect, lapack_int* m, lapack_int* n, lapack_int* k,\n                    double* a, lapack_int* lda, const double* tau, double* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_sormbr( char* vect, char* side, char* trans, lapack_int* m,\n                    lapack_int* n, lapack_int* k, const float* a,\n                    lapack_int* lda, const float* tau, float* c,\n                    lapack_int* ldc, float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_dormbr( char* vect, char* side, char* trans, lapack_int* m,\n                    lapack_int* n, lapack_int* k, const double* a,\n                    lapack_int* lda, const double* tau, double* c,\n                    lapack_int* ldc, double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_cungbr( char* vect, lapack_int* m, lapack_int* n, lapack_int* k,\n                    lapack_complex_float* a, lapack_int* lda,\n                    const lapack_complex_float* tau, lapack_complex_float* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_zungbr( char* vect, lapack_int* m, lapack_int* n, lapack_int* k,\n                    lapack_complex_double* a, lapack_int* lda,\n                    const lapack_complex_double* tau,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_cunmbr( char* vect, char* side, char* trans, lapack_int* m,\n                    lapack_int* n, lapack_int* k, const lapack_complex_float* a,\n                    lapack_int* lda, const lapack_complex_float* tau,\n                    lapack_complex_float* c, lapack_int* ldc,\n                    lapack_complex_float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_zunmbr( char* vect, char* side, char* trans, lapack_int* m,\n                    lapack_int* n, lapack_int* k,\n                    const lapack_complex_double* a, lapack_int* lda,\n                    const lapack_complex_double* tau, lapack_complex_double* c,\n                    lapack_int* ldc, lapack_complex_double* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_sbdsqr( char* uplo, lapack_int* n, lapack_int* ncvt,\n                    lapack_int* nru, lapack_int* ncc, float* d, float* e,\n                    float* vt, lapack_int* ldvt, float* u, lapack_int* ldu,\n                    float* c, lapack_int* ldc, float* work, lapack_int *info );\nvoid LAPACK_dbdsqr( char* uplo, lapack_int* n, lapack_int* ncvt,\n                    lapack_int* nru, lapack_int* ncc, double* d, double* e,\n                    double* vt, lapack_int* ldvt, double* u, lapack_int* ldu,\n                    double* c, lapack_int* ldc, double* work,\n                    lapack_int *info );\nvoid LAPACK_cbdsqr( char* uplo, lapack_int* n, lapack_int* ncvt,\n                    lapack_int* nru, lapack_int* ncc, float* d, float* e,\n                    lapack_complex_float* vt, lapack_int* ldvt,\n                    lapack_complex_float* u, lapack_int* ldu,\n                    lapack_complex_float* c, lapack_int* ldc, float* work,\n                    lapack_int *info );\nvoid LAPACK_zbdsqr( char* uplo, lapack_int* n, lapack_int* ncvt,\n                    lapack_int* nru, lapack_int* ncc, double* d, double* e,\n                    lapack_complex_double* vt, lapack_int* ldvt,\n                    lapack_complex_double* u, lapack_int* ldu,\n                    lapack_complex_double* c, lapack_int* ldc, double* work,\n                    lapack_int *info );\nvoid LAPACK_sbdsdc( char* uplo, char* compq, lapack_int* n, float* d, float* e,\n                    float* u, lapack_int* ldu, float* vt, lapack_int* ldvt,\n                    float* q, lapack_int* iq, float* work, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_dbdsdc( char* uplo, char* compq, lapack_int* n, double* d,\n                    double* e, double* u, lapack_int* ldu, double* vt,\n                    lapack_int* ldvt, double* q, lapack_int* iq, double* work,\n                    lapack_int* iwork, lapack_int *info );\nvoid LAPACK_ssytrd( char* uplo, lapack_int* n, float* a, lapack_int* lda,\n                    float* d, float* e, float* tau, float* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_dsytrd( char* uplo, lapack_int* n, double* a, lapack_int* lda,\n                    double* d, double* e, double* tau, double* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_sorgtr( char* uplo, lapack_int* n, float* a, lapack_int* lda,\n                    const float* tau, float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_dorgtr( char* uplo, lapack_int* n, double* a, lapack_int* lda,\n                    const double* tau, double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_sormtr( char* side, char* uplo, char* trans, lapack_int* m,\n                    lapack_int* n, const float* a, lapack_int* lda,\n                    const float* tau, float* c, lapack_int* ldc, float* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_dormtr( char* side, char* uplo, char* trans, lapack_int* m,\n                    lapack_int* n, const double* a, lapack_int* lda,\n                    const double* tau, double* c, lapack_int* ldc, double* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_chetrd( char* uplo, lapack_int* n, lapack_complex_float* a,\n                    lapack_int* lda, float* d, float* e,\n                    lapack_complex_float* tau, lapack_complex_float* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_zhetrd( char* uplo, lapack_int* n, lapack_complex_double* a,\n                    lapack_int* lda, double* d, double* e,\n                    lapack_complex_double* tau, lapack_complex_double* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_cungtr( char* uplo, lapack_int* n, lapack_complex_float* a,\n                    lapack_int* lda, const lapack_complex_float* tau,\n                    lapack_complex_float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_zungtr( char* uplo, lapack_int* n, lapack_complex_double* a,\n                    lapack_int* lda, const lapack_complex_double* tau,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_cunmtr( char* side, char* uplo, char* trans, lapack_int* m,\n                    lapack_int* n, const lapack_complex_float* a,\n                    lapack_int* lda, const lapack_complex_float* tau,\n                    lapack_complex_float* c, lapack_int* ldc,\n                    lapack_complex_float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_zunmtr( char* side, char* uplo, char* trans, lapack_int* m,\n                    lapack_int* n, const lapack_complex_double* a,\n                    lapack_int* lda, const lapack_complex_double* tau,\n                    lapack_complex_double* c, lapack_int* ldc,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_ssptrd( char* uplo, lapack_int* n, float* ap, float* d, float* e,\n                    float* tau, lapack_int *info );\nvoid LAPACK_dsptrd( char* uplo, lapack_int* n, double* ap, double* d, double* e,\n                    double* tau, lapack_int *info );\nvoid LAPACK_sopgtr( char* uplo, lapack_int* n, const float* ap,\n                    const float* tau, float* q, lapack_int* ldq, float* work,\n                    lapack_int *info );\nvoid LAPACK_dopgtr( char* uplo, lapack_int* n, const double* ap,\n                    const double* tau, double* q, lapack_int* ldq, double* work,\n                    lapack_int *info );\nvoid LAPACK_sopmtr( char* side, char* uplo, char* trans, lapack_int* m,\n                    lapack_int* n, const float* ap, const float* tau, float* c,\n                    lapack_int* ldc, float* work, lapack_int *info );\nvoid LAPACK_dopmtr( char* side, char* uplo, char* trans, lapack_int* m,\n                    lapack_int* n, const double* ap, const double* tau,\n                    double* c, lapack_int* ldc, double* work,\n                    lapack_int *info );\nvoid LAPACK_chptrd( char* uplo, lapack_int* n, lapack_complex_float* ap,\n                    float* d, float* e, lapack_complex_float* tau,\n                    lapack_int *info );\nvoid LAPACK_zhptrd( char* uplo, lapack_int* n, lapack_complex_double* ap,\n                    double* d, double* e, lapack_complex_double* tau,\n                    lapack_int *info );\nvoid LAPACK_cupgtr( char* uplo, lapack_int* n, const lapack_complex_float* ap,\n                    const lapack_complex_float* tau, lapack_complex_float* q,\n                    lapack_int* ldq, lapack_complex_float* work,\n                    lapack_int *info );\nvoid LAPACK_zupgtr( char* uplo, lapack_int* n, const lapack_complex_double* ap,\n                    const lapack_complex_double* tau, lapack_complex_double* q,\n                    lapack_int* ldq, lapack_complex_double* work,\n                    lapack_int *info );\nvoid LAPACK_cupmtr( char* side, char* uplo, char* trans, lapack_int* m,\n                    lapack_int* n, const lapack_complex_float* ap,\n                    const lapack_complex_float* tau, lapack_complex_float* c,\n                    lapack_int* ldc, lapack_complex_float* work,\n                    lapack_int *info );\nvoid LAPACK_zupmtr( char* side, char* uplo, char* trans, lapack_int* m,\n                    lapack_int* n, const lapack_complex_double* ap,\n                    const lapack_complex_double* tau, lapack_complex_double* c,\n                    lapack_int* ldc, lapack_complex_double* work,\n                    lapack_int *info );\nvoid LAPACK_ssbtrd( char* vect, char* uplo, lapack_int* n, lapack_int* kd,\n                    float* ab, lapack_int* ldab, float* d, float* e, float* q,\n                    lapack_int* ldq, float* work, lapack_int *info );\nvoid LAPACK_dsbtrd( char* vect, char* uplo, lapack_int* n, lapack_int* kd,\n                    double* ab, lapack_int* ldab, double* d, double* e,\n                    double* q, lapack_int* ldq, double* work,\n                    lapack_int *info );\nvoid LAPACK_chbtrd( char* vect, char* uplo, lapack_int* n, lapack_int* kd,\n                    lapack_complex_float* ab, lapack_int* ldab, float* d,\n                    float* e, lapack_complex_float* q, lapack_int* ldq,\n                    lapack_complex_float* work, lapack_int *info );\nvoid LAPACK_zhbtrd( char* vect, char* uplo, lapack_int* n, lapack_int* kd,\n                    lapack_complex_double* ab, lapack_int* ldab, double* d,\n                    double* e, lapack_complex_double* q, lapack_int* ldq,\n                    lapack_complex_double* work, lapack_int *info );\nvoid LAPACK_ssterf( lapack_int* n, float* d, float* e, lapack_int *info );\nvoid LAPACK_dsterf( lapack_int* n, double* d, double* e, lapack_int *info );\nvoid LAPACK_ssteqr( char* compz, lapack_int* n, float* d, float* e, float* z,\n                    lapack_int* ldz, float* work, lapack_int *info );\nvoid LAPACK_dsteqr( char* compz, lapack_int* n, double* d, double* e, double* z,\n                    lapack_int* ldz, double* work, lapack_int *info );\nvoid LAPACK_csteqr( char* compz, lapack_int* n, float* d, float* e,\n                    lapack_complex_float* z, lapack_int* ldz, float* work,\n                    lapack_int *info );\nvoid LAPACK_zsteqr( char* compz, lapack_int* n, double* d, double* e,\n                    lapack_complex_double* z, lapack_int* ldz, double* work,\n                    lapack_int *info );\nvoid LAPACK_sstemr( char* jobz, char* range, lapack_int* n, float* d, float* e,\n                    float* vl, float* vu, lapack_int* il, lapack_int* iu,\n                    lapack_int* m, float* w, float* z, lapack_int* ldz,\n                    lapack_int* nzc, lapack_int* isuppz, lapack_logical* tryrac,\n                    float* work, lapack_int* lwork, lapack_int* iwork,\n                    lapack_int* liwork, lapack_int *info );\nvoid LAPACK_dstemr( char* jobz, char* range, lapack_int* n, double* d,\n                    double* e, double* vl, double* vu, lapack_int* il,\n                    lapack_int* iu, lapack_int* m, double* w, double* z,\n                    lapack_int* ldz, lapack_int* nzc, lapack_int* isuppz,\n                    lapack_logical* tryrac, double* work, lapack_int* lwork,\n                    lapack_int* iwork, lapack_int* liwork, lapack_int *info );\nvoid LAPACK_cstemr( char* jobz, char* range, lapack_int* n, float* d, float* e,\n                    float* vl, float* vu, lapack_int* il, lapack_int* iu,\n                    lapack_int* m, float* w, lapack_complex_float* z,\n                    lapack_int* ldz, lapack_int* nzc, lapack_int* isuppz,\n                    lapack_logical* tryrac, float* work, lapack_int* lwork,\n                    lapack_int* iwork, lapack_int* liwork, lapack_int *info );\nvoid LAPACK_zstemr( char* jobz, char* range, lapack_int* n, double* d,\n                    double* e, double* vl, double* vu, lapack_int* il,\n                    lapack_int* iu, lapack_int* m, double* w,\n                    lapack_complex_double* z, lapack_int* ldz, lapack_int* nzc,\n                    lapack_int* isuppz, lapack_logical* tryrac, double* work,\n                    lapack_int* lwork, lapack_int* iwork, lapack_int* liwork,\n                    lapack_int *info );\nvoid LAPACK_sstedc( char* compz, lapack_int* n, float* d, float* e, float* z,\n                    lapack_int* ldz, float* work, lapack_int* lwork,\n                    lapack_int* iwork, lapack_int* liwork, lapack_int *info );\nvoid LAPACK_dstedc( char* compz, lapack_int* n, double* d, double* e, double* z,\n                    lapack_int* ldz, double* work, lapack_int* lwork,\n                    lapack_int* iwork, lapack_int* liwork, lapack_int *info );\nvoid LAPACK_cstedc( char* compz, lapack_int* n, float* d, float* e,\n                    lapack_complex_float* z, lapack_int* ldz,\n                    lapack_complex_float* work, lapack_int* lwork, float* rwork,\n                    lapack_int* lrwork, lapack_int* iwork, lapack_int* liwork,\n                    lapack_int *info );\nvoid LAPACK_zstedc( char* compz, lapack_int* n, double* d, double* e,\n                    lapack_complex_double* z, lapack_int* ldz,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    double* rwork, lapack_int* lrwork, lapack_int* iwork,\n                    lapack_int* liwork, lapack_int *info );\nvoid LAPACK_sstegr( char* jobz, char* range, lapack_int* n, float* d, float* e,\n                    float* vl, float* vu, lapack_int* il, lapack_int* iu,\n                    float* abstol, lapack_int* m, float* w, float* z,\n                    lapack_int* ldz, lapack_int* isuppz, float* work,\n                    lapack_int* lwork, lapack_int* iwork, lapack_int* liwork,\n                    lapack_int *info );\nvoid LAPACK_dstegr( char* jobz, char* range, lapack_int* n, double* d,\n                    double* e, double* vl, double* vu, lapack_int* il,\n                    lapack_int* iu, double* abstol, lapack_int* m, double* w,\n                    double* z, lapack_int* ldz, lapack_int* isuppz,\n                    double* work, lapack_int* lwork, lapack_int* iwork,\n                    lapack_int* liwork, lapack_int *info );\nvoid LAPACK_cstegr( char* jobz, char* range, lapack_int* n, float* d, float* e,\n                    float* vl, float* vu, lapack_int* il, lapack_int* iu,\n                    float* abstol, lapack_int* m, float* w,\n                    lapack_complex_float* z, lapack_int* ldz,\n                    lapack_int* isuppz, float* work, lapack_int* lwork,\n                    lapack_int* iwork, lapack_int* liwork, lapack_int *info );\nvoid LAPACK_zstegr( char* jobz, char* range, lapack_int* n, double* d,\n                    double* e, double* vl, double* vu, lapack_int* il,\n                    lapack_int* iu, double* abstol, lapack_int* m, double* w,\n                    lapack_complex_double* z, lapack_int* ldz,\n                    lapack_int* isuppz, double* work, lapack_int* lwork,\n                    lapack_int* iwork, lapack_int* liwork, lapack_int *info );\nvoid LAPACK_spteqr( char* compz, lapack_int* n, float* d, float* e, float* z,\n                    lapack_int* ldz, float* work, lapack_int *info );\nvoid LAPACK_dpteqr( char* compz, lapack_int* n, double* d, double* e, double* z,\n                    lapack_int* ldz, double* work, lapack_int *info );\nvoid LAPACK_cpteqr( char* compz, lapack_int* n, float* d, float* e,\n                    lapack_complex_float* z, lapack_int* ldz, float* work,\n                    lapack_int *info );\nvoid LAPACK_zpteqr( char* compz, lapack_int* n, double* d, double* e,\n                    lapack_complex_double* z, lapack_int* ldz, double* work,\n                    lapack_int *info );\nvoid LAPACK_sstebz( char* range, char* order, lapack_int* n, float* vl,\n                    float* vu, lapack_int* il, lapack_int* iu, float* abstol,\n                    const float* d, const float* e, lapack_int* m,\n                    lapack_int* nsplit, float* w, lapack_int* iblock,\n                    lapack_int* isplit, float* work, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_dstebz( char* range, char* order, lapack_int* n, double* vl,\n                    double* vu, lapack_int* il, lapack_int* iu, double* abstol,\n                    const double* d, const double* e, lapack_int* m,\n                    lapack_int* nsplit, double* w, lapack_int* iblock,\n                    lapack_int* isplit, double* work, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_sstein( lapack_int* n, const float* d, const float* e,\n                    lapack_int* m, const float* w, const lapack_int* iblock,\n                    const lapack_int* isplit, float* z, lapack_int* ldz,\n                    float* work, lapack_int* iwork, lapack_int* ifailv,\n                    lapack_int *info );\nvoid LAPACK_dstein( lapack_int* n, const double* d, const double* e,\n                    lapack_int* m, const double* w, const lapack_int* iblock,\n                    const lapack_int* isplit, double* z, lapack_int* ldz,\n                    double* work, lapack_int* iwork, lapack_int* ifailv,\n                    lapack_int *info );\nvoid LAPACK_cstein( lapack_int* n, const float* d, const float* e,\n                    lapack_int* m, const float* w, const lapack_int* iblock,\n                    const lapack_int* isplit, lapack_complex_float* z,\n                    lapack_int* ldz, float* work, lapack_int* iwork,\n                    lapack_int* ifailv, lapack_int *info );\nvoid LAPACK_zstein( lapack_int* n, const double* d, const double* e,\n                    lapack_int* m, const double* w, const lapack_int* iblock,\n                    const lapack_int* isplit, lapack_complex_double* z,\n                    lapack_int* ldz, double* work, lapack_int* iwork,\n                    lapack_int* ifailv, lapack_int *info );\nvoid LAPACK_sdisna( char* job, lapack_int* m, lapack_int* n, const float* d,\n                    float* sep, lapack_int *info );\nvoid LAPACK_ddisna( char* job, lapack_int* m, lapack_int* n, const double* d,\n                    double* sep, lapack_int *info );\nvoid LAPACK_ssygst( lapack_int* itype, char* uplo, lapack_int* n, float* a,\n                    lapack_int* lda, const float* b, lapack_int* ldb,\n                    lapack_int *info );\nvoid LAPACK_dsygst( lapack_int* itype, char* uplo, lapack_int* n, double* a,\n                    lapack_int* lda, const double* b, lapack_int* ldb,\n                    lapack_int *info );\nvoid LAPACK_chegst( lapack_int* itype, char* uplo, lapack_int* n,\n                    lapack_complex_float* a, lapack_int* lda,\n                    const lapack_complex_float* b, lapack_int* ldb,\n                    lapack_int *info );\nvoid LAPACK_zhegst( lapack_int* itype, char* uplo, lapack_int* n,\n                    lapack_complex_double* a, lapack_int* lda,\n                    const lapack_complex_double* b, lapack_int* ldb,\n                    lapack_int *info );\nvoid LAPACK_sspgst( lapack_int* itype, char* uplo, lapack_int* n, float* ap,\n                    const float* bp, lapack_int *info );\nvoid LAPACK_dspgst( lapack_int* itype, char* uplo, lapack_int* n, double* ap,\n                    const double* bp, lapack_int *info );\nvoid LAPACK_chpgst( lapack_int* itype, char* uplo, lapack_int* n,\n                    lapack_complex_float* ap, const lapack_complex_float* bp,\n                    lapack_int *info );\nvoid LAPACK_zhpgst( lapack_int* itype, char* uplo, lapack_int* n,\n                    lapack_complex_double* ap, const lapack_complex_double* bp,\n                    lapack_int *info );\nvoid LAPACK_ssbgst( char* vect, char* uplo, lapack_int* n, lapack_int* ka,\n                    lapack_int* kb, float* ab, lapack_int* ldab,\n                    const float* bb, lapack_int* ldbb, float* x,\n                    lapack_int* ldx, float* work, lapack_int *info );\nvoid LAPACK_dsbgst( char* vect, char* uplo, lapack_int* n, lapack_int* ka,\n                    lapack_int* kb, double* ab, lapack_int* ldab,\n                    const double* bb, lapack_int* ldbb, double* x,\n                    lapack_int* ldx, double* work, lapack_int *info );\nvoid LAPACK_chbgst( char* vect, char* uplo, lapack_int* n, lapack_int* ka,\n                    lapack_int* kb, lapack_complex_float* ab, lapack_int* ldab,\n                    const lapack_complex_float* bb, lapack_int* ldbb,\n                    lapack_complex_float* x, lapack_int* ldx,\n                    lapack_complex_float* work, float* rwork,\n                    lapack_int *info );\nvoid LAPACK_zhbgst( char* vect, char* uplo, lapack_int* n, lapack_int* ka,\n                    lapack_int* kb, lapack_complex_double* ab, lapack_int* ldab,\n                    const lapack_complex_double* bb, lapack_int* ldbb,\n                    lapack_complex_double* x, lapack_int* ldx,\n                    lapack_complex_double* work, double* rwork,\n                    lapack_int *info );\nvoid LAPACK_spbstf( char* uplo, lapack_int* n, lapack_int* kb, float* bb,\n                    lapack_int* ldbb, lapack_int *info );\nvoid LAPACK_dpbstf( char* uplo, lapack_int* n, lapack_int* kb, double* bb,\n                    lapack_int* ldbb, lapack_int *info );\nvoid LAPACK_cpbstf( char* uplo, lapack_int* n, lapack_int* kb,\n                    lapack_complex_float* bb, lapack_int* ldbb,\n                    lapack_int *info );\nvoid LAPACK_zpbstf( char* uplo, lapack_int* n, lapack_int* kb,\n                    lapack_complex_double* bb, lapack_int* ldbb,\n                    lapack_int *info );\nvoid LAPACK_sgehrd( lapack_int* n, lapack_int* ilo, lapack_int* ihi, float* a,\n                    lapack_int* lda, float* tau, float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_dgehrd( lapack_int* n, lapack_int* ilo, lapack_int* ihi, double* a,\n                    lapack_int* lda, double* tau, double* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_cgehrd( lapack_int* n, lapack_int* ilo, lapack_int* ihi,\n                    lapack_complex_float* a, lapack_int* lda,\n                    lapack_complex_float* tau, lapack_complex_float* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_zgehrd( lapack_int* n, lapack_int* ilo, lapack_int* ihi,\n                    lapack_complex_double* a, lapack_int* lda,\n                    lapack_complex_double* tau, lapack_complex_double* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_sorghr( lapack_int* n, lapack_int* ilo, lapack_int* ihi, float* a,\n                    lapack_int* lda, const float* tau, float* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_dorghr( lapack_int* n, lapack_int* ilo, lapack_int* ihi, double* a,\n                    lapack_int* lda, const double* tau, double* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_sormhr( char* side, char* trans, lapack_int* m, lapack_int* n,\n                    lapack_int* ilo, lapack_int* ihi, const float* a,\n                    lapack_int* lda, const float* tau, float* c,\n                    lapack_int* ldc, float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_dormhr( char* side, char* trans, lapack_int* m, lapack_int* n,\n                    lapack_int* ilo, lapack_int* ihi, const double* a,\n                    lapack_int* lda, const double* tau, double* c,\n                    lapack_int* ldc, double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_cunghr( lapack_int* n, lapack_int* ilo, lapack_int* ihi,\n                    lapack_complex_float* a, lapack_int* lda,\n                    const lapack_complex_float* tau, lapack_complex_float* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_zunghr( lapack_int* n, lapack_int* ilo, lapack_int* ihi,\n                    lapack_complex_double* a, lapack_int* lda,\n                    const lapack_complex_double* tau,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_cunmhr( char* side, char* trans, lapack_int* m, lapack_int* n,\n                    lapack_int* ilo, lapack_int* ihi,\n                    const lapack_complex_float* a, lapack_int* lda,\n                    const lapack_complex_float* tau, lapack_complex_float* c,\n                    lapack_int* ldc, lapack_complex_float* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_zunmhr( char* side, char* trans, lapack_int* m, lapack_int* n,\n                    lapack_int* ilo, lapack_int* ihi,\n                    const lapack_complex_double* a, lapack_int* lda,\n                    const lapack_complex_double* tau, lapack_complex_double* c,\n                    lapack_int* ldc, lapack_complex_double* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_sgebal( char* job, lapack_int* n, float* a, lapack_int* lda,\n                    lapack_int* ilo, lapack_int* ihi, float* scale,\n                    lapack_int *info );\nvoid LAPACK_dgebal( char* job, lapack_int* n, double* a, lapack_int* lda,\n                    lapack_int* ilo, lapack_int* ihi, double* scale,\n                    lapack_int *info );\nvoid LAPACK_cgebal( char* job, lapack_int* n, lapack_complex_float* a,\n                    lapack_int* lda, lapack_int* ilo, lapack_int* ihi,\n                    float* scale, lapack_int *info );\nvoid LAPACK_zgebal( char* job, lapack_int* n, lapack_complex_double* a,\n                    lapack_int* lda, lapack_int* ilo, lapack_int* ihi,\n                    double* scale, lapack_int *info );\nvoid LAPACK_sgebak( char* job, char* side, lapack_int* n, lapack_int* ilo,\n                    lapack_int* ihi, const float* scale, lapack_int* m,\n                    float* v, lapack_int* ldv, lapack_int *info );\nvoid LAPACK_dgebak( char* job, char* side, lapack_int* n, lapack_int* ilo,\n                    lapack_int* ihi, const double* scale, lapack_int* m,\n                    double* v, lapack_int* ldv, lapack_int *info );\nvoid LAPACK_cgebak( char* job, char* side, lapack_int* n, lapack_int* ilo,\n                    lapack_int* ihi, const float* scale, lapack_int* m,\n                    lapack_complex_float* v, lapack_int* ldv,\n                    lapack_int *info );\nvoid LAPACK_zgebak( char* job, char* side, lapack_int* n, lapack_int* ilo,\n                    lapack_int* ihi, const double* scale, lapack_int* m,\n                    lapack_complex_double* v, lapack_int* ldv,\n                    lapack_int *info );\nvoid LAPACK_shseqr( char* job, char* compz, lapack_int* n, lapack_int* ilo,\n                    lapack_int* ihi, float* h, lapack_int* ldh, float* wr,\n                    float* wi, float* z, lapack_int* ldz, float* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_dhseqr( char* job, char* compz, lapack_int* n, lapack_int* ilo,\n                    lapack_int* ihi, double* h, lapack_int* ldh, double* wr,\n                    double* wi, double* z, lapack_int* ldz, double* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_chseqr( char* job, char* compz, lapack_int* n, lapack_int* ilo,\n                    lapack_int* ihi, lapack_complex_float* h, lapack_int* ldh,\n                    lapack_complex_float* w, lapack_complex_float* z,\n                    lapack_int* ldz, lapack_complex_float* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_zhseqr( char* job, char* compz, lapack_int* n, lapack_int* ilo,\n                    lapack_int* ihi, lapack_complex_double* h, lapack_int* ldh,\n                    lapack_complex_double* w, lapack_complex_double* z,\n                    lapack_int* ldz, lapack_complex_double* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_shsein( char* job, char* eigsrc, char* initv,\n                    lapack_logical* select, lapack_int* n, const float* h,\n                    lapack_int* ldh, float* wr, const float* wi, float* vl,\n                    lapack_int* ldvl, float* vr, lapack_int* ldvr,\n                    lapack_int* mm, lapack_int* m, float* work,\n                    lapack_int* ifaill, lapack_int* ifailr, lapack_int *info );\nvoid LAPACK_dhsein( char* job, char* eigsrc, char* initv,\n                    lapack_logical* select, lapack_int* n, const double* h,\n                    lapack_int* ldh, double* wr, const double* wi, double* vl,\n                    lapack_int* ldvl, double* vr, lapack_int* ldvr,\n                    lapack_int* mm, lapack_int* m, double* work,\n                    lapack_int* ifaill, lapack_int* ifailr, lapack_int *info );\nvoid LAPACK_chsein( char* job, char* eigsrc, char* initv,\n                    const lapack_logical* select, lapack_int* n,\n                    const lapack_complex_float* h, lapack_int* ldh,\n                    lapack_complex_float* w, lapack_complex_float* vl,\n                    lapack_int* ldvl, lapack_complex_float* vr,\n                    lapack_int* ldvr, lapack_int* mm, lapack_int* m,\n                    lapack_complex_float* work, float* rwork,\n                    lapack_int* ifaill, lapack_int* ifailr, lapack_int *info );\nvoid LAPACK_zhsein( char* job, char* eigsrc, char* initv,\n                    const lapack_logical* select, lapack_int* n,\n                    const lapack_complex_double* h, lapack_int* ldh,\n                    lapack_complex_double* w, lapack_complex_double* vl,\n                    lapack_int* ldvl, lapack_complex_double* vr,\n                    lapack_int* ldvr, lapack_int* mm, lapack_int* m,\n                    lapack_complex_double* work, double* rwork,\n                    lapack_int* ifaill, lapack_int* ifailr, lapack_int *info );\nvoid LAPACK_strevc( char* side, char* howmny, lapack_logical* select,\n                    lapack_int* n, const float* t, lapack_int* ldt, float* vl,\n                    lapack_int* ldvl, float* vr, lapack_int* ldvr,\n                    lapack_int* mm, lapack_int* m, float* work,\n                    lapack_int *info );\nvoid LAPACK_dtrevc( char* side, char* howmny, lapack_logical* select,\n                    lapack_int* n, const double* t, lapack_int* ldt, double* vl,\n                    lapack_int* ldvl, double* vr, lapack_int* ldvr,\n                    lapack_int* mm, lapack_int* m, double* work,\n                    lapack_int *info );\nvoid LAPACK_ctrevc( char* side, char* howmny, const lapack_logical* select,\n                    lapack_int* n, lapack_complex_float* t, lapack_int* ldt,\n                    lapack_complex_float* vl, lapack_int* ldvl,\n                    lapack_complex_float* vr, lapack_int* ldvr, lapack_int* mm,\n                    lapack_int* m, lapack_complex_float* work, float* rwork,\n                    lapack_int *info );\nvoid LAPACK_ztrevc( char* side, char* howmny, const lapack_logical* select,\n                    lapack_int* n, lapack_complex_double* t, lapack_int* ldt,\n                    lapack_complex_double* vl, lapack_int* ldvl,\n                    lapack_complex_double* vr, lapack_int* ldvr, lapack_int* mm,\n                    lapack_int* m, lapack_complex_double* work, double* rwork,\n                    lapack_int *info );\nvoid LAPACK_strsna( char* job, char* howmny, const lapack_logical* select,\n                    lapack_int* n, const float* t, lapack_int* ldt,\n                    const float* vl, lapack_int* ldvl, const float* vr,\n                    lapack_int* ldvr, float* s, float* sep, lapack_int* mm,\n                    lapack_int* m, float* work, lapack_int* ldwork,\n                    lapack_int* iwork, lapack_int *info );\nvoid LAPACK_dtrsna( char* job, char* howmny, const lapack_logical* select,\n                    lapack_int* n, const double* t, lapack_int* ldt,\n                    const double* vl, lapack_int* ldvl, const double* vr,\n                    lapack_int* ldvr, double* s, double* sep, lapack_int* mm,\n                    lapack_int* m, double* work, lapack_int* ldwork,\n                    lapack_int* iwork, lapack_int *info );\nvoid LAPACK_ctrsna( char* job, char* howmny, const lapack_logical* select,\n                    lapack_int* n, const lapack_complex_float* t,\n                    lapack_int* ldt, const lapack_complex_float* vl,\n                    lapack_int* ldvl, const lapack_complex_float* vr,\n                    lapack_int* ldvr, float* s, float* sep, lapack_int* mm,\n                    lapack_int* m, lapack_complex_float* work,\n                    lapack_int* ldwork, float* rwork, lapack_int *info );\nvoid LAPACK_ztrsna( char* job, char* howmny, const lapack_logical* select,\n                    lapack_int* n, const lapack_complex_double* t,\n                    lapack_int* ldt, const lapack_complex_double* vl,\n                    lapack_int* ldvl, const lapack_complex_double* vr,\n                    lapack_int* ldvr, double* s, double* sep, lapack_int* mm,\n                    lapack_int* m, lapack_complex_double* work,\n                    lapack_int* ldwork, double* rwork, lapack_int *info );\nvoid LAPACK_strexc( char* compq, lapack_int* n, float* t, lapack_int* ldt,\n                    float* q, lapack_int* ldq, lapack_int* ifst,\n                    lapack_int* ilst, float* work, lapack_int *info );\nvoid LAPACK_dtrexc( char* compq, lapack_int* n, double* t, lapack_int* ldt,\n                    double* q, lapack_int* ldq, lapack_int* ifst,\n                    lapack_int* ilst, double* work, lapack_int *info );\nvoid LAPACK_ctrexc( char* compq, lapack_int* n, lapack_complex_float* t,\n                    lapack_int* ldt, lapack_complex_float* q, lapack_int* ldq,\n                    lapack_int* ifst, lapack_int* ilst, lapack_int *info );\nvoid LAPACK_ztrexc( char* compq, lapack_int* n, lapack_complex_double* t,\n                    lapack_int* ldt, lapack_complex_double* q, lapack_int* ldq,\n                    lapack_int* ifst, lapack_int* ilst, lapack_int *info );\nvoid LAPACK_strsen( char* job, char* compq, const lapack_logical* select,\n                    lapack_int* n, float* t, lapack_int* ldt, float* q,\n                    lapack_int* ldq, float* wr, float* wi, lapack_int* m,\n                    float* s, float* sep, float* work, lapack_int* lwork,\n                    lapack_int* iwork, lapack_int* liwork, lapack_int *info );\nvoid LAPACK_dtrsen( char* job, char* compq, const lapack_logical* select,\n                    lapack_int* n, double* t, lapack_int* ldt, double* q,\n                    lapack_int* ldq, double* wr, double* wi, lapack_int* m,\n                    double* s, double* sep, double* work, lapack_int* lwork,\n                    lapack_int* iwork, lapack_int* liwork, lapack_int *info );\nvoid LAPACK_ctrsen( char* job, char* compq, const lapack_logical* select,\n                    lapack_int* n, lapack_complex_float* t, lapack_int* ldt,\n                    lapack_complex_float* q, lapack_int* ldq,\n                    lapack_complex_float* w, lapack_int* m, float* s,\n                    float* sep, lapack_complex_float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_ztrsen( char* job, char* compq, const lapack_logical* select,\n                    lapack_int* n, lapack_complex_double* t, lapack_int* ldt,\n                    lapack_complex_double* q, lapack_int* ldq,\n                    lapack_complex_double* w, lapack_int* m, double* s,\n                    double* sep, lapack_complex_double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_strsyl( char* trana, char* tranb, lapack_int* isgn, lapack_int* m,\n                    lapack_int* n, const float* a, lapack_int* lda,\n                    const float* b, lapack_int* ldb, float* c, lapack_int* ldc,\n                    float* scale, lapack_int *info );\nvoid LAPACK_dtrsyl( char* trana, char* tranb, lapack_int* isgn, lapack_int* m,\n                    lapack_int* n, const double* a, lapack_int* lda,\n                    const double* b, lapack_int* ldb, double* c,\n                    lapack_int* ldc, double* scale, lapack_int *info );\nvoid LAPACK_ctrsyl( char* trana, char* tranb, lapack_int* isgn, lapack_int* m,\n                    lapack_int* n, const lapack_complex_float* a,\n                    lapack_int* lda, const lapack_complex_float* b,\n                    lapack_int* ldb, lapack_complex_float* c, lapack_int* ldc,\n                    float* scale, lapack_int *info );\nvoid LAPACK_ztrsyl( char* trana, char* tranb, lapack_int* isgn, lapack_int* m,\n                    lapack_int* n, const lapack_complex_double* a,\n                    lapack_int* lda, const lapack_complex_double* b,\n                    lapack_int* ldb, lapack_complex_double* c, lapack_int* ldc,\n                    double* scale, lapack_int *info );\nvoid LAPACK_sgghrd( char* compq, char* compz, lapack_int* n, lapack_int* ilo,\n                    lapack_int* ihi, float* a, lapack_int* lda, float* b,\n                    lapack_int* ldb, float* q, lapack_int* ldq, float* z,\n                    lapack_int* ldz, lapack_int *info );\nvoid LAPACK_dgghrd( char* compq, char* compz, lapack_int* n, lapack_int* ilo,\n                    lapack_int* ihi, double* a, lapack_int* lda, double* b,\n                    lapack_int* ldb, double* q, lapack_int* ldq, double* z,\n                    lapack_int* ldz, lapack_int *info );\nvoid LAPACK_cgghrd( char* compq, char* compz, lapack_int* n, lapack_int* ilo,\n                    lapack_int* ihi, lapack_complex_float* a, lapack_int* lda,\n                    lapack_complex_float* b, lapack_int* ldb,\n                    lapack_complex_float* q, lapack_int* ldq,\n                    lapack_complex_float* z, lapack_int* ldz,\n                    lapack_int *info );\nvoid LAPACK_zgghrd( char* compq, char* compz, lapack_int* n, lapack_int* ilo,\n                    lapack_int* ihi, lapack_complex_double* a, lapack_int* lda,\n                    lapack_complex_double* b, lapack_int* ldb,\n                    lapack_complex_double* q, lapack_int* ldq,\n                    lapack_complex_double* z, lapack_int* ldz,\n                    lapack_int *info );\nvoid LAPACK_sggbal( char* job, lapack_int* n, float* a, lapack_int* lda,\n                    float* b, lapack_int* ldb, lapack_int* ilo, lapack_int* ihi,\n                    float* lscale, float* rscale, float* work,\n                    lapack_int *info );\nvoid LAPACK_dggbal( char* job, lapack_int* n, double* a, lapack_int* lda,\n                    double* b, lapack_int* ldb, lapack_int* ilo,\n                    lapack_int* ihi, double* lscale, double* rscale,\n                    double* work, lapack_int *info );\nvoid LAPACK_cggbal( char* job, lapack_int* n, lapack_complex_float* a,\n                    lapack_int* lda, lapack_complex_float* b, lapack_int* ldb,\n                    lapack_int* ilo, lapack_int* ihi, float* lscale,\n                    float* rscale, float* work, lapack_int *info );\nvoid LAPACK_zggbal( char* job, lapack_int* n, lapack_complex_double* a,\n                    lapack_int* lda, lapack_complex_double* b, lapack_int* ldb,\n                    lapack_int* ilo, lapack_int* ihi, double* lscale,\n                    double* rscale, double* work, lapack_int *info );\nvoid LAPACK_sggbak( char* job, char* side, lapack_int* n, lapack_int* ilo,\n                    lapack_int* ihi, const float* lscale, const float* rscale,\n                    lapack_int* m, float* v, lapack_int* ldv,\n                    lapack_int *info );\nvoid LAPACK_dggbak( char* job, char* side, lapack_int* n, lapack_int* ilo,\n                    lapack_int* ihi, const double* lscale, const double* rscale,\n                    lapack_int* m, double* v, lapack_int* ldv,\n                    lapack_int *info );\nvoid LAPACK_cggbak( char* job, char* side, lapack_int* n, lapack_int* ilo,\n                    lapack_int* ihi, const float* lscale, const float* rscale,\n                    lapack_int* m, lapack_complex_float* v, lapack_int* ldv,\n                    lapack_int *info );\nvoid LAPACK_zggbak( char* job, char* side, lapack_int* n, lapack_int* ilo,\n                    lapack_int* ihi, const double* lscale, const double* rscale,\n                    lapack_int* m, lapack_complex_double* v, lapack_int* ldv,\n                    lapack_int *info );\nvoid LAPACK_shgeqz( char* job, char* compq, char* compz, lapack_int* n,\n                    lapack_int* ilo, lapack_int* ihi, float* h, lapack_int* ldh,\n                    float* t, lapack_int* ldt, float* alphar, float* alphai,\n                    float* beta, float* q, lapack_int* ldq, float* z,\n                    lapack_int* ldz, float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_dhgeqz( char* job, char* compq, char* compz, lapack_int* n,\n                    lapack_int* ilo, lapack_int* ihi, double* h,\n                    lapack_int* ldh, double* t, lapack_int* ldt, double* alphar,\n                    double* alphai, double* beta, double* q, lapack_int* ldq,\n                    double* z, lapack_int* ldz, double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_chgeqz( char* job, char* compq, char* compz, lapack_int* n,\n                    lapack_int* ilo, lapack_int* ihi, lapack_complex_float* h,\n                    lapack_int* ldh, lapack_complex_float* t, lapack_int* ldt,\n                    lapack_complex_float* alpha, lapack_complex_float* beta,\n                    lapack_complex_float* q, lapack_int* ldq,\n                    lapack_complex_float* z, lapack_int* ldz,\n                    lapack_complex_float* work, lapack_int* lwork, float* rwork,\n                    lapack_int *info );\nvoid LAPACK_zhgeqz( char* job, char* compq, char* compz, lapack_int* n,\n                    lapack_int* ilo, lapack_int* ihi, lapack_complex_double* h,\n                    lapack_int* ldh, lapack_complex_double* t, lapack_int* ldt,\n                    lapack_complex_double* alpha, lapack_complex_double* beta,\n                    lapack_complex_double* q, lapack_int* ldq,\n                    lapack_complex_double* z, lapack_int* ldz,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    double* rwork, lapack_int *info );\nvoid LAPACK_stgevc( char* side, char* howmny, const lapack_logical* select,\n                    lapack_int* n, const float* s, lapack_int* lds,\n                    const float* p, lapack_int* ldp, float* vl,\n                    lapack_int* ldvl, float* vr, lapack_int* ldvr,\n                    lapack_int* mm, lapack_int* m, float* work,\n                    lapack_int *info );\nvoid LAPACK_dtgevc( char* side, char* howmny, const lapack_logical* select,\n                    lapack_int* n, const double* s, lapack_int* lds,\n                    const double* p, lapack_int* ldp, double* vl,\n                    lapack_int* ldvl, double* vr, lapack_int* ldvr,\n                    lapack_int* mm, lapack_int* m, double* work,\n                    lapack_int *info );\nvoid LAPACK_ctgevc( char* side, char* howmny, const lapack_logical* select,\n                    lapack_int* n, const lapack_complex_float* s,\n                    lapack_int* lds, const lapack_complex_float* p,\n                    lapack_int* ldp, lapack_complex_float* vl, lapack_int* ldvl,\n                    lapack_complex_float* vr, lapack_int* ldvr, lapack_int* mm,\n                    lapack_int* m, lapack_complex_float* work, float* rwork,\n                    lapack_int *info );\nvoid LAPACK_ztgevc( char* side, char* howmny, const lapack_logical* select,\n                    lapack_int* n, const lapack_complex_double* s,\n                    lapack_int* lds, const lapack_complex_double* p,\n                    lapack_int* ldp, lapack_complex_double* vl,\n                    lapack_int* ldvl, lapack_complex_double* vr,\n                    lapack_int* ldvr, lapack_int* mm, lapack_int* m,\n                    lapack_complex_double* work, double* rwork,\n                    lapack_int *info );\nvoid LAPACK_stgexc( lapack_logical* wantq, lapack_logical* wantz, lapack_int* n,\n                    float* a, lapack_int* lda, float* b, lapack_int* ldb,\n                    float* q, lapack_int* ldq, float* z, lapack_int* ldz,\n                    lapack_int* ifst, lapack_int* ilst, float* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_dtgexc( lapack_logical* wantq, lapack_logical* wantz, lapack_int* n,\n                    double* a, lapack_int* lda, double* b, lapack_int* ldb,\n                    double* q, lapack_int* ldq, double* z, lapack_int* ldz,\n                    lapack_int* ifst, lapack_int* ilst, double* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_ctgexc( lapack_logical* wantq, lapack_logical* wantz, lapack_int* n,\n                    lapack_complex_float* a, lapack_int* lda,\n                    lapack_complex_float* b, lapack_int* ldb,\n                    lapack_complex_float* q, lapack_int* ldq,\n                    lapack_complex_float* z, lapack_int* ldz, lapack_int* ifst,\n                    lapack_int* ilst, lapack_int *info );\nvoid LAPACK_ztgexc( lapack_logical* wantq, lapack_logical* wantz, lapack_int* n,\n                    lapack_complex_double* a, lapack_int* lda,\n                    lapack_complex_double* b, lapack_int* ldb,\n                    lapack_complex_double* q, lapack_int* ldq,\n                    lapack_complex_double* z, lapack_int* ldz, lapack_int* ifst,\n                    lapack_int* ilst, lapack_int *info );\nvoid LAPACK_stgsen( lapack_int* ijob, lapack_logical* wantq,\n                    lapack_logical* wantz, const lapack_logical* select,\n                    lapack_int* n, float* a, lapack_int* lda, float* b,\n                    lapack_int* ldb, float* alphar, float* alphai, float* beta,\n                    float* q, lapack_int* ldq, float* z, lapack_int* ldz,\n                    lapack_int* m, float* pl, float* pr, float* dif,\n                    float* work, lapack_int* lwork, lapack_int* iwork,\n                    lapack_int* liwork, lapack_int *info );\nvoid LAPACK_dtgsen( lapack_int* ijob, lapack_logical* wantq,\n                    lapack_logical* wantz, const lapack_logical* select,\n                    lapack_int* n, double* a, lapack_int* lda, double* b,\n                    lapack_int* ldb, double* alphar, double* alphai,\n                    double* beta, double* q, lapack_int* ldq, double* z,\n                    lapack_int* ldz, lapack_int* m, double* pl, double* pr,\n                    double* dif, double* work, lapack_int* lwork,\n                    lapack_int* iwork, lapack_int* liwork, lapack_int *info );\nvoid LAPACK_ctgsen( lapack_int* ijob, lapack_logical* wantq,\n                    lapack_logical* wantz, const lapack_logical* select,\n                    lapack_int* n, lapack_complex_float* a, lapack_int* lda,\n                    lapack_complex_float* b, lapack_int* ldb,\n                    lapack_complex_float* alpha, lapack_complex_float* beta,\n                    lapack_complex_float* q, lapack_int* ldq,\n                    lapack_complex_float* z, lapack_int* ldz, lapack_int* m,\n                    float* pl, float* pr, float* dif,\n                    lapack_complex_float* work, lapack_int* lwork,\n                    lapack_int* iwork, lapack_int* liwork, lapack_int *info );\nvoid LAPACK_ztgsen( lapack_int* ijob, lapack_logical* wantq,\n                    lapack_logical* wantz, const lapack_logical* select,\n                    lapack_int* n, lapack_complex_double* a, lapack_int* lda,\n                    lapack_complex_double* b, lapack_int* ldb,\n                    lapack_complex_double* alpha, lapack_complex_double* beta,\n                    lapack_complex_double* q, lapack_int* ldq,\n                    lapack_complex_double* z, lapack_int* ldz, lapack_int* m,\n                    double* pl, double* pr, double* dif,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    lapack_int* iwork, lapack_int* liwork, lapack_int *info );\nvoid LAPACK_stgsyl( char* trans, lapack_int* ijob, lapack_int* m, lapack_int* n,\n                    const float* a, lapack_int* lda, const float* b,\n                    lapack_int* ldb, float* c, lapack_int* ldc, const float* d,\n                    lapack_int* ldd, const float* e, lapack_int* lde, float* f,\n                    lapack_int* ldf, float* scale, float* dif, float* work,\n                    lapack_int* lwork, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_dtgsyl( char* trans, lapack_int* ijob, lapack_int* m, lapack_int* n,\n                    const double* a, lapack_int* lda, const double* b,\n                    lapack_int* ldb, double* c, lapack_int* ldc,\n                    const double* d, lapack_int* ldd, const double* e,\n                    lapack_int* lde, double* f, lapack_int* ldf, double* scale,\n                    double* dif, double* work, lapack_int* lwork,\n                    lapack_int* iwork, lapack_int *info );\nvoid LAPACK_ctgsyl( char* trans, lapack_int* ijob, lapack_int* m, lapack_int* n,\n                    const lapack_complex_float* a, lapack_int* lda,\n                    const lapack_complex_float* b, lapack_int* ldb,\n                    lapack_complex_float* c, lapack_int* ldc,\n                    const lapack_complex_float* d, lapack_int* ldd,\n                    const lapack_complex_float* e, lapack_int* lde,\n                    lapack_complex_float* f, lapack_int* ldf, float* scale,\n                    float* dif, lapack_complex_float* work, lapack_int* lwork,\n                    lapack_int* iwork, lapack_int *info );\nvoid LAPACK_ztgsyl( char* trans, lapack_int* ijob, lapack_int* m, lapack_int* n,\n                    const lapack_complex_double* a, lapack_int* lda,\n                    const lapack_complex_double* b, lapack_int* ldb,\n                    lapack_complex_double* c, lapack_int* ldc,\n                    const lapack_complex_double* d, lapack_int* ldd,\n                    const lapack_complex_double* e, lapack_int* lde,\n                    lapack_complex_double* f, lapack_int* ldf, double* scale,\n                    double* dif, lapack_complex_double* work, lapack_int* lwork,\n                    lapack_int* iwork, lapack_int *info );\nvoid LAPACK_stgsna( char* job, char* howmny, const lapack_logical* select,\n                    lapack_int* n, const float* a, lapack_int* lda,\n                    const float* b, lapack_int* ldb, const float* vl,\n                    lapack_int* ldvl, const float* vr, lapack_int* ldvr,\n                    float* s, float* dif, lapack_int* mm, lapack_int* m,\n                    float* work, lapack_int* lwork, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_dtgsna( char* job, char* howmny, const lapack_logical* select,\n                    lapack_int* n, const double* a, lapack_int* lda,\n                    const double* b, lapack_int* ldb, const double* vl,\n                    lapack_int* ldvl, const double* vr, lapack_int* ldvr,\n                    double* s, double* dif, lapack_int* mm, lapack_int* m,\n                    double* work, lapack_int* lwork, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_ctgsna( char* job, char* howmny, const lapack_logical* select,\n                    lapack_int* n, const lapack_complex_float* a,\n                    lapack_int* lda, const lapack_complex_float* b,\n                    lapack_int* ldb, const lapack_complex_float* vl,\n                    lapack_int* ldvl, const lapack_complex_float* vr,\n                    lapack_int* ldvr, float* s, float* dif, lapack_int* mm,\n                    lapack_int* m, lapack_complex_float* work,\n                    lapack_int* lwork, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_ztgsna( char* job, char* howmny, const lapack_logical* select,\n                    lapack_int* n, const lapack_complex_double* a,\n                    lapack_int* lda, const lapack_complex_double* b,\n                    lapack_int* ldb, const lapack_complex_double* vl,\n                    lapack_int* ldvl, const lapack_complex_double* vr,\n                    lapack_int* ldvr, double* s, double* dif, lapack_int* mm,\n                    lapack_int* m, lapack_complex_double* work,\n                    lapack_int* lwork, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_sggsvp( char* jobu, char* jobv, char* jobq, lapack_int* m,\n                    lapack_int* p, lapack_int* n, float* a, lapack_int* lda,\n                    float* b, lapack_int* ldb, float* tola, float* tolb,\n                    lapack_int* k, lapack_int* l, float* u, lapack_int* ldu,\n                    float* v, lapack_int* ldv, float* q, lapack_int* ldq,\n                    lapack_int* iwork, float* tau, float* work,\n                    lapack_int *info );\nvoid LAPACK_dggsvp( char* jobu, char* jobv, char* jobq, lapack_int* m,\n                    lapack_int* p, lapack_int* n, double* a, lapack_int* lda,\n                    double* b, lapack_int* ldb, double* tola, double* tolb,\n                    lapack_int* k, lapack_int* l, double* u, lapack_int* ldu,\n                    double* v, lapack_int* ldv, double* q, lapack_int* ldq,\n                    lapack_int* iwork, double* tau, double* work,\n                    lapack_int *info );\nvoid LAPACK_cggsvp( char* jobu, char* jobv, char* jobq, lapack_int* m,\n                    lapack_int* p, lapack_int* n, lapack_complex_float* a,\n                    lapack_int* lda, lapack_complex_float* b, lapack_int* ldb,\n                    float* tola, float* tolb, lapack_int* k, lapack_int* l,\n                    lapack_complex_float* u, lapack_int* ldu,\n                    lapack_complex_float* v, lapack_int* ldv,\n                    lapack_complex_float* q, lapack_int* ldq, lapack_int* iwork,\n                    float* rwork, lapack_complex_float* tau,\n                    lapack_complex_float* work, lapack_int *info );\nvoid LAPACK_zggsvp( char* jobu, char* jobv, char* jobq, lapack_int* m,\n                    lapack_int* p, lapack_int* n, lapack_complex_double* a,\n                    lapack_int* lda, lapack_complex_double* b, lapack_int* ldb,\n                    double* tola, double* tolb, lapack_int* k, lapack_int* l,\n                    lapack_complex_double* u, lapack_int* ldu,\n                    lapack_complex_double* v, lapack_int* ldv,\n                    lapack_complex_double* q, lapack_int* ldq,\n                    lapack_int* iwork, double* rwork,\n                    lapack_complex_double* tau, lapack_complex_double* work,\n                    lapack_int *info );\nvoid LAPACK_stgsja( char* jobu, char* jobv, char* jobq, lapack_int* m,\n                    lapack_int* p, lapack_int* n, lapack_int* k, lapack_int* l,\n                    float* a, lapack_int* lda, float* b, lapack_int* ldb,\n                    float* tola, float* tolb, float* alpha, float* beta,\n                    float* u, lapack_int* ldu, float* v, lapack_int* ldv,\n                    float* q, lapack_int* ldq, float* work, lapack_int* ncycle,\n                    lapack_int *info );\nvoid LAPACK_dtgsja( char* jobu, char* jobv, char* jobq, lapack_int* m,\n                    lapack_int* p, lapack_int* n, lapack_int* k, lapack_int* l,\n                    double* a, lapack_int* lda, double* b, lapack_int* ldb,\n                    double* tola, double* tolb, double* alpha, double* beta,\n                    double* u, lapack_int* ldu, double* v, lapack_int* ldv,\n                    double* q, lapack_int* ldq, double* work,\n                    lapack_int* ncycle, lapack_int *info );\nvoid LAPACK_ctgsja( char* jobu, char* jobv, char* jobq, lapack_int* m,\n                    lapack_int* p, lapack_int* n, lapack_int* k, lapack_int* l,\n                    lapack_complex_float* a, lapack_int* lda,\n                    lapack_complex_float* b, lapack_int* ldb, float* tola,\n                    float* tolb, float* alpha, float* beta,\n                    lapack_complex_float* u, lapack_int* ldu,\n                    lapack_complex_float* v, lapack_int* ldv,\n                    lapack_complex_float* q, lapack_int* ldq,\n                    lapack_complex_float* work, lapack_int* ncycle,\n                    lapack_int *info );\nvoid LAPACK_ztgsja( char* jobu, char* jobv, char* jobq, lapack_int* m,\n                    lapack_int* p, lapack_int* n, lapack_int* k, lapack_int* l,\n                    lapack_complex_double* a, lapack_int* lda,\n                    lapack_complex_double* b, lapack_int* ldb, double* tola,\n                    double* tolb, double* alpha, double* beta,\n                    lapack_complex_double* u, lapack_int* ldu,\n                    lapack_complex_double* v, lapack_int* ldv,\n                    lapack_complex_double* q, lapack_int* ldq,\n                    lapack_complex_double* work, lapack_int* ncycle,\n                    lapack_int *info );\nvoid LAPACK_sgels( char* trans, lapack_int* m, lapack_int* n, lapack_int* nrhs,\n                   float* a, lapack_int* lda, float* b, lapack_int* ldb,\n                   float* work, lapack_int* lwork, lapack_int *info );\nvoid LAPACK_dgels( char* trans, lapack_int* m, lapack_int* n, lapack_int* nrhs,\n                   double* a, lapack_int* lda, double* b, lapack_int* ldb,\n                   double* work, lapack_int* lwork, lapack_int *info );\nvoid LAPACK_cgels( char* trans, lapack_int* m, lapack_int* n, lapack_int* nrhs,\n                   lapack_complex_float* a, lapack_int* lda,\n                   lapack_complex_float* b, lapack_int* ldb,\n                   lapack_complex_float* work, lapack_int* lwork,\n                   lapack_int *info );\nvoid LAPACK_zgels( char* trans, lapack_int* m, lapack_int* n, lapack_int* nrhs,\n                   lapack_complex_double* a, lapack_int* lda,\n                   lapack_complex_double* b, lapack_int* ldb,\n                   lapack_complex_double* work, lapack_int* lwork,\n                   lapack_int *info );\nvoid LAPACK_sgelsy( lapack_int* m, lapack_int* n, lapack_int* nrhs, float* a,\n                    lapack_int* lda, float* b, lapack_int* ldb,\n                    lapack_int* jpvt, float* rcond, lapack_int* rank,\n                    float* work, lapack_int* lwork, lapack_int *info );\nvoid LAPACK_dgelsy( lapack_int* m, lapack_int* n, lapack_int* nrhs, double* a,\n                    lapack_int* lda, double* b, lapack_int* ldb,\n                    lapack_int* jpvt, double* rcond, lapack_int* rank,\n                    double* work, lapack_int* lwork, lapack_int *info );\nvoid LAPACK_cgelsy( lapack_int* m, lapack_int* n, lapack_int* nrhs,\n                    lapack_complex_float* a, lapack_int* lda,\n                    lapack_complex_float* b, lapack_int* ldb, lapack_int* jpvt,\n                    float* rcond, lapack_int* rank, lapack_complex_float* work,\n                    lapack_int* lwork, float* rwork, lapack_int *info );\nvoid LAPACK_zgelsy( lapack_int* m, lapack_int* n, lapack_int* nrhs,\n                    lapack_complex_double* a, lapack_int* lda,\n                    lapack_complex_double* b, lapack_int* ldb, lapack_int* jpvt,\n                    double* rcond, lapack_int* rank,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    double* rwork, lapack_int *info );\nvoid LAPACK_sgelss( lapack_int* m, lapack_int* n, lapack_int* nrhs, float* a,\n                    lapack_int* lda, float* b, lapack_int* ldb, float* s,\n                    float* rcond, lapack_int* rank, float* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_dgelss( lapack_int* m, lapack_int* n, lapack_int* nrhs, double* a,\n                    lapack_int* lda, double* b, lapack_int* ldb, double* s,\n                    double* rcond, lapack_int* rank, double* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_cgelss( lapack_int* m, lapack_int* n, lapack_int* nrhs,\n                    lapack_complex_float* a, lapack_int* lda,\n                    lapack_complex_float* b, lapack_int* ldb, float* s,\n                    float* rcond, lapack_int* rank, lapack_complex_float* work,\n                    lapack_int* lwork, float* rwork, lapack_int *info );\nvoid LAPACK_zgelss( lapack_int* m, lapack_int* n, lapack_int* nrhs,\n                    lapack_complex_double* a, lapack_int* lda,\n                    lapack_complex_double* b, lapack_int* ldb, double* s,\n                    double* rcond, lapack_int* rank,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    double* rwork, lapack_int *info );\nvoid LAPACK_sgelsd( lapack_int* m, lapack_int* n, lapack_int* nrhs, float* a,\n                    lapack_int* lda, float* b, lapack_int* ldb, float* s,\n                    float* rcond, lapack_int* rank, float* work,\n                    lapack_int* lwork, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_dgelsd( lapack_int* m, lapack_int* n, lapack_int* nrhs, double* a,\n                    lapack_int* lda, double* b, lapack_int* ldb, double* s,\n                    double* rcond, lapack_int* rank, double* work,\n                    lapack_int* lwork, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_cgelsd( lapack_int* m, lapack_int* n, lapack_int* nrhs,\n                    lapack_complex_float* a, lapack_int* lda,\n                    lapack_complex_float* b, lapack_int* ldb, float* s,\n                    float* rcond, lapack_int* rank, lapack_complex_float* work,\n                    lapack_int* lwork, float* rwork, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_zgelsd( lapack_int* m, lapack_int* n, lapack_int* nrhs,\n                    lapack_complex_double* a, lapack_int* lda,\n                    lapack_complex_double* b, lapack_int* ldb, double* s,\n                    double* rcond, lapack_int* rank,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    double* rwork, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_sgglse( lapack_int* m, lapack_int* n, lapack_int* p, float* a,\n                    lapack_int* lda, float* b, lapack_int* ldb, float* c,\n                    float* d, float* x, float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_dgglse( lapack_int* m, lapack_int* n, lapack_int* p, double* a,\n                    lapack_int* lda, double* b, lapack_int* ldb, double* c,\n                    double* d, double* x, double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_cgglse( lapack_int* m, lapack_int* n, lapack_int* p,\n                    lapack_complex_float* a, lapack_int* lda,\n                    lapack_complex_float* b, lapack_int* ldb,\n                    lapack_complex_float* c, lapack_complex_float* d,\n                    lapack_complex_float* x, lapack_complex_float* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_zgglse( lapack_int* m, lapack_int* n, lapack_int* p,\n                    lapack_complex_double* a, lapack_int* lda,\n                    lapack_complex_double* b, lapack_int* ldb,\n                    lapack_complex_double* c, lapack_complex_double* d,\n                    lapack_complex_double* x, lapack_complex_double* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_sggglm( lapack_int* n, lapack_int* m, lapack_int* p, float* a,\n                    lapack_int* lda, float* b, lapack_int* ldb, float* d,\n                    float* x, float* y, float* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_dggglm( lapack_int* n, lapack_int* m, lapack_int* p, double* a,\n                    lapack_int* lda, double* b, lapack_int* ldb, double* d,\n                    double* x, double* y, double* work, lapack_int* lwork,\n                    lapack_int *info );\nvoid LAPACK_cggglm( lapack_int* n, lapack_int* m, lapack_int* p,\n                    lapack_complex_float* a, lapack_int* lda,\n                    lapack_complex_float* b, lapack_int* ldb,\n                    lapack_complex_float* d, lapack_complex_float* x,\n                    lapack_complex_float* y, lapack_complex_float* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_zggglm( lapack_int* n, lapack_int* m, lapack_int* p,\n                    lapack_complex_double* a, lapack_int* lda,\n                    lapack_complex_double* b, lapack_int* ldb,\n                    lapack_complex_double* d, lapack_complex_double* x,\n                    lapack_complex_double* y, lapack_complex_double* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_ssyev( char* jobz, char* uplo, lapack_int* n, float* a,\n                   lapack_int* lda, float* w, float* work, lapack_int* lwork,\n                   lapack_int *info );\nvoid LAPACK_dsyev( char* jobz, char* uplo, lapack_int* n, double* a,\n                   lapack_int* lda, double* w, double* work, lapack_int* lwork,\n                   lapack_int *info );\nvoid LAPACK_cheev( char* jobz, char* uplo, lapack_int* n,\n                   lapack_complex_float* a, lapack_int* lda, float* w,\n                   lapack_complex_float* work, lapack_int* lwork, float* rwork,\n                   lapack_int *info );\nvoid LAPACK_zheev( char* jobz, char* uplo, lapack_int* n,\n                   lapack_complex_double* a, lapack_int* lda, double* w,\n                   lapack_complex_double* work, lapack_int* lwork,\n                   double* rwork, lapack_int *info );\nvoid LAPACK_ssyevd( char* jobz, char* uplo, lapack_int* n, float* a,\n                    lapack_int* lda, float* w, float* work, lapack_int* lwork,\n                    lapack_int* iwork, lapack_int* liwork, lapack_int *info );\nvoid LAPACK_dsyevd( char* jobz, char* uplo, lapack_int* n, double* a,\n                    lapack_int* lda, double* w, double* work, lapack_int* lwork,\n                    lapack_int* iwork, lapack_int* liwork, lapack_int *info );\nvoid LAPACK_cheevd( char* jobz, char* uplo, lapack_int* n,\n                    lapack_complex_float* a, lapack_int* lda, float* w,\n                    lapack_complex_float* work, lapack_int* lwork, float* rwork,\n                    lapack_int* lrwork, lapack_int* iwork, lapack_int* liwork,\n                    lapack_int *info );\nvoid LAPACK_zheevd( char* jobz, char* uplo, lapack_int* n,\n                    lapack_complex_double* a, lapack_int* lda, double* w,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    double* rwork, lapack_int* lrwork, lapack_int* iwork,\n                    lapack_int* liwork, lapack_int *info );\nvoid LAPACK_ssyevx( char* jobz, char* range, char* uplo, lapack_int* n,\n                    float* a, lapack_int* lda, float* vl, float* vu,\n                    lapack_int* il, lapack_int* iu, float* abstol,\n                    lapack_int* m, float* w, float* z, lapack_int* ldz,\n                    float* work, lapack_int* lwork, lapack_int* iwork,\n                    lapack_int* ifail, lapack_int *info );\nvoid LAPACK_dsyevx( char* jobz, char* range, char* uplo, lapack_int* n,\n                    double* a, lapack_int* lda, double* vl, double* vu,\n                    lapack_int* il, lapack_int* iu, double* abstol,\n                    lapack_int* m, double* w, double* z, lapack_int* ldz,\n                    double* work, lapack_int* lwork, lapack_int* iwork,\n                    lapack_int* ifail, lapack_int *info );\nvoid LAPACK_cheevx( char* jobz, char* range, char* uplo, lapack_int* n,\n                    lapack_complex_float* a, lapack_int* lda, float* vl,\n                    float* vu, lapack_int* il, lapack_int* iu, float* abstol,\n                    lapack_int* m, float* w, lapack_complex_float* z,\n                    lapack_int* ldz, lapack_complex_float* work,\n                    lapack_int* lwork, float* rwork, lapack_int* iwork,\n                    lapack_int* ifail, lapack_int *info );\nvoid LAPACK_zheevx( char* jobz, char* range, char* uplo, lapack_int* n,\n                    lapack_complex_double* a, lapack_int* lda, double* vl,\n                    double* vu, lapack_int* il, lapack_int* iu, double* abstol,\n                    lapack_int* m, double* w, lapack_complex_double* z,\n                    lapack_int* ldz, lapack_complex_double* work,\n                    lapack_int* lwork, double* rwork, lapack_int* iwork,\n                    lapack_int* ifail, lapack_int *info );\nvoid LAPACK_ssyevr( char* jobz, char* range, char* uplo, lapack_int* n,\n                    float* a, lapack_int* lda, float* vl, float* vu,\n                    lapack_int* il, lapack_int* iu, float* abstol,\n                    lapack_int* m, float* w, float* z, lapack_int* ldz,\n                    lapack_int* isuppz, float* work, lapack_int* lwork,\n                    lapack_int* iwork, lapack_int* liwork, lapack_int *info );\nvoid LAPACK_dsyevr( char* jobz, char* range, char* uplo, lapack_int* n,\n                    double* a, lapack_int* lda, double* vl, double* vu,\n                    lapack_int* il, lapack_int* iu, double* abstol,\n                    lapack_int* m, double* w, double* z, lapack_int* ldz,\n                    lapack_int* isuppz, double* work, lapack_int* lwork,\n                    lapack_int* iwork, lapack_int* liwork, lapack_int *info );\nvoid LAPACK_cheevr( char* jobz, char* range, char* uplo, lapack_int* n,\n                    lapack_complex_float* a, lapack_int* lda, float* vl,\n                    float* vu, lapack_int* il, lapack_int* iu, float* abstol,\n                    lapack_int* m, float* w, lapack_complex_float* z,\n                    lapack_int* ldz, lapack_int* isuppz,\n                    lapack_complex_float* work, lapack_int* lwork, float* rwork,\n                    lapack_int* lrwork, lapack_int* iwork, lapack_int* liwork,\n                    lapack_int *info );\nvoid LAPACK_zheevr( char* jobz, char* range, char* uplo, lapack_int* n,\n                    lapack_complex_double* a, lapack_int* lda, double* vl,\n                    double* vu, lapack_int* il, lapack_int* iu, double* abstol,\n                    lapack_int* m, double* w, lapack_complex_double* z,\n                    lapack_int* ldz, lapack_int* isuppz,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    double* rwork, lapack_int* lrwork, lapack_int* iwork,\n                    lapack_int* liwork, lapack_int *info );\nvoid LAPACK_sspev( char* jobz, char* uplo, lapack_int* n, float* ap, float* w,\n                   float* z, lapack_int* ldz, float* work, lapack_int *info );\nvoid LAPACK_dspev( char* jobz, char* uplo, lapack_int* n, double* ap, double* w,\n                   double* z, lapack_int* ldz, double* work, lapack_int *info );\nvoid LAPACK_chpev( char* jobz, char* uplo, lapack_int* n,\n                   lapack_complex_float* ap, float* w, lapack_complex_float* z,\n                   lapack_int* ldz, lapack_complex_float* work, float* rwork,\n                   lapack_int *info );\nvoid LAPACK_zhpev( char* jobz, char* uplo, lapack_int* n,\n                   lapack_complex_double* ap, double* w,\n                   lapack_complex_double* z, lapack_int* ldz,\n                   lapack_complex_double* work, double* rwork,\n                   lapack_int *info );\nvoid LAPACK_sspevd( char* jobz, char* uplo, lapack_int* n, float* ap, float* w,\n                    float* z, lapack_int* ldz, float* work, lapack_int* lwork,\n                    lapack_int* iwork, lapack_int* liwork, lapack_int *info );\nvoid LAPACK_dspevd( char* jobz, char* uplo, lapack_int* n, double* ap,\n                    double* w, double* z, lapack_int* ldz, double* work,\n                    lapack_int* lwork, lapack_int* iwork, lapack_int* liwork,\n                    lapack_int *info );\nvoid LAPACK_chpevd( char* jobz, char* uplo, lapack_int* n,\n                    lapack_complex_float* ap, float* w, lapack_complex_float* z,\n                    lapack_int* ldz, lapack_complex_float* work,\n                    lapack_int* lwork, float* rwork, lapack_int* lrwork,\n                    lapack_int* iwork, lapack_int* liwork, lapack_int *info );\nvoid LAPACK_zhpevd( char* jobz, char* uplo, lapack_int* n,\n                    lapack_complex_double* ap, double* w,\n                    lapack_complex_double* z, lapack_int* ldz,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    double* rwork, lapack_int* lrwork, lapack_int* iwork,\n                    lapack_int* liwork, lapack_int *info );\nvoid LAPACK_sspevx( char* jobz, char* range, char* uplo, lapack_int* n,\n                    float* ap, float* vl, float* vu, lapack_int* il,\n                    lapack_int* iu, float* abstol, lapack_int* m, float* w,\n                    float* z, lapack_int* ldz, float* work, lapack_int* iwork,\n                    lapack_int* ifail, lapack_int *info );\nvoid LAPACK_dspevx( char* jobz, char* range, char* uplo, lapack_int* n,\n                    double* ap, double* vl, double* vu, lapack_int* il,\n                    lapack_int* iu, double* abstol, lapack_int* m, double* w,\n                    double* z, lapack_int* ldz, double* work, lapack_int* iwork,\n                    lapack_int* ifail, lapack_int *info );\nvoid LAPACK_chpevx( char* jobz, char* range, char* uplo, lapack_int* n,\n                    lapack_complex_float* ap, float* vl, float* vu,\n                    lapack_int* il, lapack_int* iu, float* abstol,\n                    lapack_int* m, float* w, lapack_complex_float* z,\n                    lapack_int* ldz, lapack_complex_float* work, float* rwork,\n                    lapack_int* iwork, lapack_int* ifail, lapack_int *info );\nvoid LAPACK_zhpevx( char* jobz, char* range, char* uplo, lapack_int* n,\n                    lapack_complex_double* ap, double* vl, double* vu,\n                    lapack_int* il, lapack_int* iu, double* abstol,\n                    lapack_int* m, double* w, lapack_complex_double* z,\n                    lapack_int* ldz, lapack_complex_double* work, double* rwork,\n                    lapack_int* iwork, lapack_int* ifail, lapack_int *info );\nvoid LAPACK_ssbev( char* jobz, char* uplo, lapack_int* n, lapack_int* kd,\n                   float* ab, lapack_int* ldab, float* w, float* z,\n                   lapack_int* ldz, float* work, lapack_int *info );\nvoid LAPACK_dsbev( char* jobz, char* uplo, lapack_int* n, lapack_int* kd,\n                   double* ab, lapack_int* ldab, double* w, double* z,\n                   lapack_int* ldz, double* work, lapack_int *info );\nvoid LAPACK_chbev( char* jobz, char* uplo, lapack_int* n, lapack_int* kd,\n                   lapack_complex_float* ab, lapack_int* ldab, float* w,\n                   lapack_complex_float* z, lapack_int* ldz,\n                   lapack_complex_float* work, float* rwork, lapack_int *info );\nvoid LAPACK_zhbev( char* jobz, char* uplo, lapack_int* n, lapack_int* kd,\n                   lapack_complex_double* ab, lapack_int* ldab, double* w,\n                   lapack_complex_double* z, lapack_int* ldz,\n                   lapack_complex_double* work, double* rwork,\n                   lapack_int *info );\nvoid LAPACK_ssbevd( char* jobz, char* uplo, lapack_int* n, lapack_int* kd,\n                    float* ab, lapack_int* ldab, float* w, float* z,\n                    lapack_int* ldz, float* work, lapack_int* lwork,\n                    lapack_int* iwork, lapack_int* liwork, lapack_int *info );\nvoid LAPACK_dsbevd( char* jobz, char* uplo, lapack_int* n, lapack_int* kd,\n                    double* ab, lapack_int* ldab, double* w, double* z,\n                    lapack_int* ldz, double* work, lapack_int* lwork,\n                    lapack_int* iwork, lapack_int* liwork, lapack_int *info );\nvoid LAPACK_chbevd( char* jobz, char* uplo, lapack_int* n, lapack_int* kd,\n                    lapack_complex_float* ab, lapack_int* ldab, float* w,\n                    lapack_complex_float* z, lapack_int* ldz,\n                    lapack_complex_float* work, lapack_int* lwork, float* rwork,\n                    lapack_int* lrwork, lapack_int* iwork, lapack_int* liwork,\n                    lapack_int *info );\nvoid LAPACK_zhbevd( char* jobz, char* uplo, lapack_int* n, lapack_int* kd,\n                    lapack_complex_double* ab, lapack_int* ldab, double* w,\n                    lapack_complex_double* z, lapack_int* ldz,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    double* rwork, lapack_int* lrwork, lapack_int* iwork,\n                    lapack_int* liwork, lapack_int *info );\nvoid LAPACK_ssbevx( char* jobz, char* range, char* uplo, lapack_int* n,\n                    lapack_int* kd, float* ab, lapack_int* ldab, float* q,\n                    lapack_int* ldq, float* vl, float* vu, lapack_int* il,\n                    lapack_int* iu, float* abstol, lapack_int* m, float* w,\n                    float* z, lapack_int* ldz, float* work, lapack_int* iwork,\n                    lapack_int* ifail, lapack_int *info );\nvoid LAPACK_dsbevx( char* jobz, char* range, char* uplo, lapack_int* n,\n                    lapack_int* kd, double* ab, lapack_int* ldab, double* q,\n                    lapack_int* ldq, double* vl, double* vu, lapack_int* il,\n                    lapack_int* iu, double* abstol, lapack_int* m, double* w,\n                    double* z, lapack_int* ldz, double* work, lapack_int* iwork,\n                    lapack_int* ifail, lapack_int *info );\nvoid LAPACK_chbevx( char* jobz, char* range, char* uplo, lapack_int* n,\n                    lapack_int* kd, lapack_complex_float* ab, lapack_int* ldab,\n                    lapack_complex_float* q, lapack_int* ldq, float* vl,\n                    float* vu, lapack_int* il, lapack_int* iu, float* abstol,\n                    lapack_int* m, float* w, lapack_complex_float* z,\n                    lapack_int* ldz, lapack_complex_float* work, float* rwork,\n                    lapack_int* iwork, lapack_int* ifail, lapack_int *info );\nvoid LAPACK_zhbevx( char* jobz, char* range, char* uplo, lapack_int* n,\n                    lapack_int* kd, lapack_complex_double* ab, lapack_int* ldab,\n                    lapack_complex_double* q, lapack_int* ldq, double* vl,\n                    double* vu, lapack_int* il, lapack_int* iu, double* abstol,\n                    lapack_int* m, double* w, lapack_complex_double* z,\n                    lapack_int* ldz, lapack_complex_double* work, double* rwork,\n                    lapack_int* iwork, lapack_int* ifail, lapack_int *info );\nvoid LAPACK_sstev( char* jobz, lapack_int* n, float* d, float* e, float* z,\n                   lapack_int* ldz, float* work, lapack_int *info );\nvoid LAPACK_dstev( char* jobz, lapack_int* n, double* d, double* e, double* z,\n                   lapack_int* ldz, double* work, lapack_int *info );\nvoid LAPACK_sstevd( char* jobz, lapack_int* n, float* d, float* e, float* z,\n                    lapack_int* ldz, float* work, lapack_int* lwork,\n                    lapack_int* iwork, lapack_int* liwork, lapack_int *info );\nvoid LAPACK_dstevd( char* jobz, lapack_int* n, double* d, double* e, double* z,\n                    lapack_int* ldz, double* work, lapack_int* lwork,\n                    lapack_int* iwork, lapack_int* liwork, lapack_int *info );\nvoid LAPACK_sstevx( char* jobz, char* range, lapack_int* n, float* d, float* e,\n                    float* vl, float* vu, lapack_int* il, lapack_int* iu,\n                    float* abstol, lapack_int* m, float* w, float* z,\n                    lapack_int* ldz, float* work, lapack_int* iwork,\n                    lapack_int* ifail, lapack_int *info );\nvoid LAPACK_dstevx( char* jobz, char* range, lapack_int* n, double* d,\n                    double* e, double* vl, double* vu, lapack_int* il,\n                    lapack_int* iu, double* abstol, lapack_int* m, double* w,\n                    double* z, lapack_int* ldz, double* work, lapack_int* iwork,\n                    lapack_int* ifail, lapack_int *info );\nvoid LAPACK_sstevr( char* jobz, char* range, lapack_int* n, float* d, float* e,\n                    float* vl, float* vu, lapack_int* il, lapack_int* iu,\n                    float* abstol, lapack_int* m, float* w, float* z,\n                    lapack_int* ldz, lapack_int* isuppz, float* work,\n                    lapack_int* lwork, lapack_int* iwork, lapack_int* liwork,\n                    lapack_int *info );\nvoid LAPACK_dstevr( char* jobz, char* range, lapack_int* n, double* d,\n                    double* e, double* vl, double* vu, lapack_int* il,\n                    lapack_int* iu, double* abstol, lapack_int* m, double* w,\n                    double* z, lapack_int* ldz, lapack_int* isuppz,\n                    double* work, lapack_int* lwork, lapack_int* iwork,\n                    lapack_int* liwork, lapack_int *info );\nvoid LAPACK_sgees( char* jobvs, char* sort, LAPACK_S_SELECT2 select,\n                   lapack_int* n, float* a, lapack_int* lda, lapack_int* sdim,\n                   float* wr, float* wi, float* vs, lapack_int* ldvs,\n                   float* work, lapack_int* lwork, lapack_logical* bwork,\n                   lapack_int *info );\nvoid LAPACK_dgees( char* jobvs, char* sort, LAPACK_D_SELECT2 select,\n                   lapack_int* n, double* a, lapack_int* lda, lapack_int* sdim,\n                   double* wr, double* wi, double* vs, lapack_int* ldvs,\n                   double* work, lapack_int* lwork, lapack_logical* bwork,\n                   lapack_int *info );\nvoid LAPACK_cgees( char* jobvs, char* sort, LAPACK_C_SELECT1 select,\n                   lapack_int* n, lapack_complex_float* a, lapack_int* lda,\n                   lapack_int* sdim, lapack_complex_float* w,\n                   lapack_complex_float* vs, lapack_int* ldvs,\n                   lapack_complex_float* work, lapack_int* lwork, float* rwork,\n                   lapack_logical* bwork, lapack_int *info );\nvoid LAPACK_zgees( char* jobvs, char* sort, LAPACK_Z_SELECT1 select,\n                   lapack_int* n, lapack_complex_double* a, lapack_int* lda,\n                   lapack_int* sdim, lapack_complex_double* w,\n                   lapack_complex_double* vs, lapack_int* ldvs,\n                   lapack_complex_double* work, lapack_int* lwork,\n                   double* rwork, lapack_logical* bwork, lapack_int *info );\nvoid LAPACK_sgeesx( char* jobvs, char* sort, LAPACK_S_SELECT2 select,\n                    char* sense, lapack_int* n, float* a, lapack_int* lda,\n                    lapack_int* sdim, float* wr, float* wi, float* vs,\n                    lapack_int* ldvs, float* rconde, float* rcondv, float* work,\n                    lapack_int* lwork, lapack_int* iwork, lapack_int* liwork,\n                    lapack_logical* bwork, lapack_int *info );\nvoid LAPACK_dgeesx( char* jobvs, char* sort, LAPACK_D_SELECT2 select,\n                    char* sense, lapack_int* n, double* a, lapack_int* lda,\n                    lapack_int* sdim, double* wr, double* wi, double* vs,\n                    lapack_int* ldvs, double* rconde, double* rcondv,\n                    double* work, lapack_int* lwork, lapack_int* iwork,\n                    lapack_int* liwork, lapack_logical* bwork,\n                    lapack_int *info );\nvoid LAPACK_cgeesx( char* jobvs, char* sort, LAPACK_C_SELECT1 select,\n                    char* sense, lapack_int* n, lapack_complex_float* a,\n                    lapack_int* lda, lapack_int* sdim, lapack_complex_float* w,\n                    lapack_complex_float* vs, lapack_int* ldvs, float* rconde,\n                    float* rcondv, lapack_complex_float* work,\n                    lapack_int* lwork, float* rwork, lapack_logical* bwork,\n                    lapack_int *info );\nvoid LAPACK_zgeesx( char* jobvs, char* sort, LAPACK_Z_SELECT1 select,\n                    char* sense, lapack_int* n, lapack_complex_double* a,\n                    lapack_int* lda, lapack_int* sdim, lapack_complex_double* w,\n                    lapack_complex_double* vs, lapack_int* ldvs, double* rconde,\n                    double* rcondv, lapack_complex_double* work,\n                    lapack_int* lwork, double* rwork, lapack_logical* bwork,\n                    lapack_int *info );\nvoid LAPACK_sgeev( char* jobvl, char* jobvr, lapack_int* n, float* a,\n                   lapack_int* lda, float* wr, float* wi, float* vl,\n                   lapack_int* ldvl, float* vr, lapack_int* ldvr, float* work,\n                   lapack_int* lwork, lapack_int *info );\nvoid LAPACK_dgeev( char* jobvl, char* jobvr, lapack_int* n, double* a,\n                   lapack_int* lda, double* wr, double* wi, double* vl,\n                   lapack_int* ldvl, double* vr, lapack_int* ldvr, double* work,\n                   lapack_int* lwork, lapack_int *info );\nvoid LAPACK_cgeev( char* jobvl, char* jobvr, lapack_int* n,\n                   lapack_complex_float* a, lapack_int* lda,\n                   lapack_complex_float* w, lapack_complex_float* vl,\n                   lapack_int* ldvl, lapack_complex_float* vr, lapack_int* ldvr,\n                   lapack_complex_float* work, lapack_int* lwork, float* rwork,\n                   lapack_int *info );\nvoid LAPACK_zgeev( char* jobvl, char* jobvr, lapack_int* n,\n                   lapack_complex_double* a, lapack_int* lda,\n                   lapack_complex_double* w, lapack_complex_double* vl,\n                   lapack_int* ldvl, lapack_complex_double* vr,\n                   lapack_int* ldvr, lapack_complex_double* work,\n                   lapack_int* lwork, double* rwork, lapack_int *info );\nvoid LAPACK_sgeevx( char* balanc, char* jobvl, char* jobvr, char* sense,\n                    lapack_int* n, float* a, lapack_int* lda, float* wr,\n                    float* wi, float* vl, lapack_int* ldvl, float* vr,\n                    lapack_int* ldvr, lapack_int* ilo, lapack_int* ihi,\n                    float* scale, float* abnrm, float* rconde, float* rcondv,\n                    float* work, lapack_int* lwork, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_dgeevx( char* balanc, char* jobvl, char* jobvr, char* sense,\n                    lapack_int* n, double* a, lapack_int* lda, double* wr,\n                    double* wi, double* vl, lapack_int* ldvl, double* vr,\n                    lapack_int* ldvr, lapack_int* ilo, lapack_int* ihi,\n                    double* scale, double* abnrm, double* rconde,\n                    double* rcondv, double* work, lapack_int* lwork,\n                    lapack_int* iwork, lapack_int *info );\nvoid LAPACK_cgeevx( char* balanc, char* jobvl, char* jobvr, char* sense,\n                    lapack_int* n, lapack_complex_float* a, lapack_int* lda,\n                    lapack_complex_float* w, lapack_complex_float* vl,\n                    lapack_int* ldvl, lapack_complex_float* vr,\n                    lapack_int* ldvr, lapack_int* ilo, lapack_int* ihi,\n                    float* scale, float* abnrm, float* rconde, float* rcondv,\n                    lapack_complex_float* work, lapack_int* lwork, float* rwork,\n                    lapack_int *info );\nvoid LAPACK_zgeevx( char* balanc, char* jobvl, char* jobvr, char* sense,\n                    lapack_int* n, lapack_complex_double* a, lapack_int* lda,\n                    lapack_complex_double* w, lapack_complex_double* vl,\n                    lapack_int* ldvl, lapack_complex_double* vr,\n                    lapack_int* ldvr, lapack_int* ilo, lapack_int* ihi,\n                    double* scale, double* abnrm, double* rconde,\n                    double* rcondv, lapack_complex_double* work,\n                    lapack_int* lwork, double* rwork, lapack_int *info );\nvoid LAPACK_sgesvd( char* jobu, char* jobvt, lapack_int* m, lapack_int* n,\n                    float* a, lapack_int* lda, float* s, float* u,\n                    lapack_int* ldu, float* vt, lapack_int* ldvt, float* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_dgesvd( char* jobu, char* jobvt, lapack_int* m, lapack_int* n,\n                    double* a, lapack_int* lda, double* s, double* u,\n                    lapack_int* ldu, double* vt, lapack_int* ldvt, double* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_cgesvd( char* jobu, char* jobvt, lapack_int* m, lapack_int* n,\n                    lapack_complex_float* a, lapack_int* lda, float* s,\n                    lapack_complex_float* u, lapack_int* ldu,\n                    lapack_complex_float* vt, lapack_int* ldvt,\n                    lapack_complex_float* work, lapack_int* lwork, float* rwork,\n                    lapack_int *info );\nvoid LAPACK_zgesvd( char* jobu, char* jobvt, lapack_int* m, lapack_int* n,\n                    lapack_complex_double* a, lapack_int* lda, double* s,\n                    lapack_complex_double* u, lapack_int* ldu,\n                    lapack_complex_double* vt, lapack_int* ldvt,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    double* rwork, lapack_int *info );\nvoid LAPACK_sgesdd( char* jobz, lapack_int* m, lapack_int* n, float* a,\n                    lapack_int* lda, float* s, float* u, lapack_int* ldu,\n                    float* vt, lapack_int* ldvt, float* work, lapack_int* lwork,\n                    lapack_int* iwork, lapack_int *info );\nvoid LAPACK_dgesdd( char* jobz, lapack_int* m, lapack_int* n, double* a,\n                    lapack_int* lda, double* s, double* u, lapack_int* ldu,\n                    double* vt, lapack_int* ldvt, double* work,\n                    lapack_int* lwork, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_cgesdd( char* jobz, lapack_int* m, lapack_int* n,\n                    lapack_complex_float* a, lapack_int* lda, float* s,\n                    lapack_complex_float* u, lapack_int* ldu,\n                    lapack_complex_float* vt, lapack_int* ldvt,\n                    lapack_complex_float* work, lapack_int* lwork, float* rwork,\n                    lapack_int* iwork, lapack_int *info );\nvoid LAPACK_zgesdd( char* jobz, lapack_int* m, lapack_int* n,\n                    lapack_complex_double* a, lapack_int* lda, double* s,\n                    lapack_complex_double* u, lapack_int* ldu,\n                    lapack_complex_double* vt, lapack_int* ldvt,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    double* rwork, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_dgejsv( char* joba, char* jobu, char* jobv, char* jobr, char* jobt,\n                    char* jobp, lapack_int* m, lapack_int* n, double* a,\n                    lapack_int* lda, double* sva, double* u, lapack_int* ldu,\n                    double* v, lapack_int* ldv, double* work, lapack_int* lwork,\n                    lapack_int* iwork, lapack_int *info );\nvoid LAPACK_sgejsv( char* joba, char* jobu, char* jobv, char* jobr, char* jobt,\n                    char* jobp, lapack_int* m, lapack_int* n, float* a,\n                    lapack_int* lda, float* sva, float* u, lapack_int* ldu,\n                    float* v, lapack_int* ldv, float* work, lapack_int* lwork,\n                    lapack_int* iwork, lapack_int *info );\nvoid LAPACK_dgesvj( char* joba, char* jobu, char* jobv, lapack_int* m,\n                    lapack_int* n, double* a, lapack_int* lda, double* sva,\n                    lapack_int* mv, double* v, lapack_int* ldv, double* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_sgesvj( char* joba, char* jobu, char* jobv, lapack_int* m,\n                    lapack_int* n, float* a, lapack_int* lda, float* sva,\n                    lapack_int* mv, float* v, lapack_int* ldv, float* work,\n                    lapack_int* lwork, lapack_int *info );\nvoid LAPACK_sggsvd( char* jobu, char* jobv, char* jobq, lapack_int* m,\n                    lapack_int* n, lapack_int* p, lapack_int* k, lapack_int* l,\n                    float* a, lapack_int* lda, float* b, lapack_int* ldb,\n                    float* alpha, float* beta, float* u, lapack_int* ldu,\n                    float* v, lapack_int* ldv, float* q, lapack_int* ldq,\n                    float* work, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_dggsvd( char* jobu, char* jobv, char* jobq, lapack_int* m,\n                    lapack_int* n, lapack_int* p, lapack_int* k, lapack_int* l,\n                    double* a, lapack_int* lda, double* b, lapack_int* ldb,\n                    double* alpha, double* beta, double* u, lapack_int* ldu,\n                    double* v, lapack_int* ldv, double* q, lapack_int* ldq,\n                    double* work, lapack_int* iwork, lapack_int *info );\nvoid LAPACK_cggsvd( char* jobu, char* jobv, char* jobq, lapack_int* m,\n                    lapack_int* n, lapack_int* p, lapack_int* k, lapack_int* l,\n                    lapack_complex_float* a, lapack_int* lda,\n                    lapack_complex_float* b, lapack_int* ldb, float* alpha,\n                    float* beta, lapack_complex_float* u, lapack_int* ldu,\n                    lapack_complex_float* v, lapack_int* ldv,\n                    lapack_complex_float* q, lapack_int* ldq,\n                    lapack_complex_float* work, float* rwork, lapack_int* iwork,\n                    lapack_int *info );\nvoid LAPACK_zggsvd( char* jobu, char* jobv, char* jobq, lapack_int* m,\n                    lapack_int* n, lapack_int* p, lapack_int* k, lapack_int* l,\n                    lapack_complex_double* a, lapack_int* lda,\n                    lapack_complex_double* b, lapack_int* ldb, double* alpha,\n                    double* beta, lapack_complex_double* u, lapack_int* ldu,\n                    lapack_complex_double* v, lapack_int* ldv,\n                    lapack_complex_double* q, lapack_int* ldq,\n                    lapack_complex_double* work, double* rwork,\n                    lapack_int* iwork, lapack_int *info );\nvoid LAPACK_ssygv( lapack_int* itype, char* jobz, char* uplo, lapack_int* n,\n                   float* a, lapack_int* lda, float* b, lapack_int* ldb,\n                   float* w, float* work, lapack_int* lwork, lapack_int *info );\nvoid LAPACK_dsygv( lapack_int* itype, char* jobz, char* uplo, lapack_int* n,\n                   double* a, lapack_int* lda, double* b, lapack_int* ldb,\n                   double* w, double* work, lapack_int* lwork,\n                   lapack_int *info );\nvoid LAPACK_chegv( lapack_int* itype, char* jobz, char* uplo, lapack_int* n,\n                   lapack_complex_float* a, lapack_int* lda,\n                   lapack_complex_float* b, lapack_int* ldb, float* w,\n                   lapack_complex_float* work, lapack_int* lwork, float* rwork,\n                   lapack_int *info );\nvoid LAPACK_zhegv( lapack_int* itype, char* jobz, char* uplo, lapack_int* n,\n                   lapack_complex_double* a, lapack_int* lda,\n                   lapack_complex_double* b, lapack_int* ldb, double* w,\n                   lapack_complex_double* work, lapack_int* lwork,\n                   double* rwork, lapack_int *info );\nvoid LAPACK_ssygvd( lapack_int* itype, char* jobz, char* uplo, lapack_int* n,\n                    float* a, lapack_int* lda, float* b, lapack_int* ldb,\n                    float* w, float* work, lapack_int* lwork, lapack_int* iwork,\n                    lapack_int* liwork, lapack_int *info );\nvoid LAPACK_dsygvd( lapack_int* itype, char* jobz, char* uplo, lapack_int* n,\n                    double* a, lapack_int* lda, double* b, lapack_int* ldb,\n                    double* w, double* work, lapack_int* lwork,\n                    lapack_int* iwork, lapack_int* liwork, lapack_int *info );\nvoid LAPACK_chegvd( lapack_int* itype, char* jobz, char* uplo, lapack_int* n,\n                    lapack_complex_float* a, lapack_int* lda,\n                    lapack_complex_float* b, lapack_int* ldb, float* w,\n                    lapack_complex_float* work, lapack_int* lwork, float* rwork,\n                    lapack_int* lrwork, lapack_int* iwork, lapack_int* liwork,\n                    lapack_int *info );\nvoid LAPACK_zhegvd( lapack_int* itype, char* jobz, char* uplo, lapack_int* n,\n                    lapack_complex_double* a, lapack_int* lda,\n                    lapack_complex_double* b, lapack_int* ldb, double* w,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    double* rwork, lapack_int* lrwork, lapack_int* iwork,\n                    lapack_int* liwork, lapack_int *info );\nvoid LAPACK_ssygvx( lapack_int* itype, char* jobz, char* range, char* uplo,\n                    lapack_int* n, float* a, lapack_int* lda, float* b,\n                    lapack_int* ldb, float* vl, float* vu, lapack_int* il,\n                    lapack_int* iu, float* abstol, lapack_int* m, float* w,\n                    float* z, lapack_int* ldz, float* work, lapack_int* lwork,\n                    lapack_int* iwork, lapack_int* ifail, lapack_int *info );\nvoid LAPACK_dsygvx( lapack_int* itype, char* jobz, char* range, char* uplo,\n                    lapack_int* n, double* a, lapack_int* lda, double* b,\n                    lapack_int* ldb, double* vl, double* vu, lapack_int* il,\n                    lapack_int* iu, double* abstol, lapack_int* m, double* w,\n                    double* z, lapack_int* ldz, double* work, lapack_int* lwork,\n                    lapack_int* iwork, lapack_int* ifail, lapack_int *info );\nvoid LAPACK_chegvx( lapack_int* itype, char* jobz, char* range, char* uplo,\n                    lapack_int* n, lapack_complex_float* a, lapack_int* lda,\n                    lapack_complex_float* b, lapack_int* ldb, float* vl,\n                    float* vu, lapack_int* il, lapack_int* iu, float* abstol,\n                    lapack_int* m, float* w, lapack_complex_float* z,\n                    lapack_int* ldz, lapack_complex_float* work,\n                    lapack_int* lwork, float* rwork, lapack_int* iwork,\n                    lapack_int* ifail, lapack_int *info );\nvoid LAPACK_zhegvx( lapack_int* itype, char* jobz, char* range, char* uplo,\n                    lapack_int* n, lapack_complex_double* a, lapack_int* lda,\n                    lapack_complex_double* b, lapack_int* ldb, double* vl,\n                    double* vu, lapack_int* il, lapack_int* iu, double* abstol,\n                    lapack_int* m, double* w, lapack_complex_double* z,\n                    lapack_int* ldz, lapack_complex_double* work,\n                    lapack_int* lwork, double* rwork, lapack_int* iwork,\n                    lapack_int* ifail, lapack_int *info );\nvoid LAPACK_sspgv( lapack_int* itype, char* jobz, char* uplo, lapack_int* n,\n                   float* ap, float* bp, float* w, float* z, lapack_int* ldz,\n                   float* work, lapack_int *info );\nvoid LAPACK_dspgv( lapack_int* itype, char* jobz, char* uplo, lapack_int* n,\n                   double* ap, double* bp, double* w, double* z,\n                   lapack_int* ldz, double* work, lapack_int *info );\nvoid LAPACK_chpgv( lapack_int* itype, char* jobz, char* uplo, lapack_int* n,\n                   lapack_complex_float* ap, lapack_complex_float* bp, float* w,\n                   lapack_complex_float* z, lapack_int* ldz,\n                   lapack_complex_float* work, float* rwork, lapack_int *info );\nvoid LAPACK_zhpgv( lapack_int* itype, char* jobz, char* uplo, lapack_int* n,\n                   lapack_complex_double* ap, lapack_complex_double* bp,\n                   double* w, lapack_complex_double* z, lapack_int* ldz,\n                   lapack_complex_double* work, double* rwork,\n                   lapack_int *info );\nvoid LAPACK_sspgvd( lapack_int* itype, char* jobz, char* uplo, lapack_int* n,\n                    float* ap, float* bp, float* w, float* z, lapack_int* ldz,\n                    float* work, lapack_int* lwork, lapack_int* iwork,\n                    lapack_int* liwork, lapack_int *info );\nvoid LAPACK_dspgvd( lapack_int* itype, char* jobz, char* uplo, lapack_int* n,\n                    double* ap, double* bp, double* w, double* z,\n                    lapack_int* ldz, double* work, lapack_int* lwork,\n                    lapack_int* iwork, lapack_int* liwork, lapack_int *info );\nvoid LAPACK_chpgvd( lapack_int* itype, char* jobz, char* uplo, lapack_int* n,\n                    lapack_complex_float* ap, lapack_complex_float* bp,\n                    float* w, lapack_complex_float* z, lapack_int* ldz,\n                    lapack_complex_float* work, lapack_int* lwork, float* rwork,\n                    lapack_int* lrwork, lapack_int* iwork, lapack_int* liwork,\n                    lapack_int *info );\nvoid LAPACK_zhpgvd( lapack_int* itype, char* jobz, char* uplo, lapack_int* n,\n                    lapack_complex_double* ap, lapack_complex_double* bp,\n                    double* w, lapack_complex_double* z, lapack_int* ldz,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    double* rwork, lapack_int* lrwork, lapack_int* iwork,\n                    lapack_int* liwork, lapack_int *info );\nvoid LAPACK_sspgvx( lapack_int* itype, char* jobz, char* range, char* uplo,\n                    lapack_int* n, float* ap, float* bp, float* vl, float* vu,\n                    lapack_int* il, lapack_int* iu, float* abstol,\n                    lapack_int* m, float* w, float* z, lapack_int* ldz,\n                    float* work, lapack_int* iwork, lapack_int* ifail,\n                    lapack_int *info );\nvoid LAPACK_dspgvx( lapack_int* itype, char* jobz, char* range, char* uplo,\n                    lapack_int* n, double* ap, double* bp, double* vl,\n                    double* vu, lapack_int* il, lapack_int* iu, double* abstol,\n                    lapack_int* m, double* w, double* z, lapack_int* ldz,\n                    double* work, lapack_int* iwork, lapack_int* ifail,\n                    lapack_int *info );\nvoid LAPACK_chpgvx( lapack_int* itype, char* jobz, char* range, char* uplo,\n                    lapack_int* n, lapack_complex_float* ap,\n                    lapack_complex_float* bp, float* vl, float* vu,\n                    lapack_int* il, lapack_int* iu, float* abstol,\n                    lapack_int* m, float* w, lapack_complex_float* z,\n                    lapack_int* ldz, lapack_complex_float* work, float* rwork,\n                    lapack_int* iwork, lapack_int* ifail, lapack_int *info );\nvoid LAPACK_zhpgvx( lapack_int* itype, char* jobz, char* range, char* uplo,\n                    lapack_int* n, lapack_complex_double* ap,\n                    lapack_complex_double* bp, double* vl, double* vu,\n                    lapack_int* il, lapack_int* iu, double* abstol,\n                    lapack_int* m, double* w, lapack_complex_double* z,\n                    lapack_int* ldz, lapack_complex_double* work, double* rwork,\n                    lapack_int* iwork, lapack_int* ifail, lapack_int *info );\nvoid LAPACK_ssbgv( char* jobz, char* uplo, lapack_int* n, lapack_int* ka,\n                   lapack_int* kb, float* ab, lapack_int* ldab, float* bb,\n                   lapack_int* ldbb, float* w, float* z, lapack_int* ldz,\n                   float* work, lapack_int *info );\nvoid LAPACK_dsbgv( char* jobz, char* uplo, lapack_int* n, lapack_int* ka,\n                   lapack_int* kb, double* ab, lapack_int* ldab, double* bb,\n                   lapack_int* ldbb, double* w, double* z, lapack_int* ldz,\n                   double* work, lapack_int *info );\nvoid LAPACK_chbgv( char* jobz, char* uplo, lapack_int* n, lapack_int* ka,\n                   lapack_int* kb, lapack_complex_float* ab, lapack_int* ldab,\n                   lapack_complex_float* bb, lapack_int* ldbb, float* w,\n                   lapack_complex_float* z, lapack_int* ldz,\n                   lapack_complex_float* work, float* rwork, lapack_int *info );\nvoid LAPACK_zhbgv( char* jobz, char* uplo, lapack_int* n, lapack_int* ka,\n                   lapack_int* kb, lapack_complex_double* ab, lapack_int* ldab,\n                   lapack_complex_double* bb, lapack_int* ldbb, double* w,\n                   lapack_complex_double* z, lapack_int* ldz,\n                   lapack_complex_double* work, double* rwork,\n                   lapack_int *info );\nvoid LAPACK_ssbgvd( char* jobz, char* uplo, lapack_int* n, lapack_int* ka,\n                    lapack_int* kb, float* ab, lapack_int* ldab, float* bb,\n                    lapack_int* ldbb, float* w, float* z, lapack_int* ldz,\n                    float* work, lapack_int* lwork, lapack_int* iwork,\n                    lapack_int* liwork, lapack_int *info );\nvoid LAPACK_dsbgvd( char* jobz, char* uplo, lapack_int* n, lapack_int* ka,\n                    lapack_int* kb, double* ab, lapack_int* ldab, double* bb,\n                    lapack_int* ldbb, double* w, double* z, lapack_int* ldz,\n                    double* work, lapack_int* lwork, lapack_int* iwork,\n                    lapack_int* liwork, lapack_int *info );\nvoid LAPACK_chbgvd( char* jobz, char* uplo, lapack_int* n, lapack_int* ka,\n                    lapack_int* kb, lapack_complex_float* ab, lapack_int* ldab,\n                    lapack_complex_float* bb, lapack_int* ldbb, float* w,\n                    lapack_complex_float* z, lapack_int* ldz,\n                    lapack_complex_float* work, lapack_int* lwork, float* rwork,\n                    lapack_int* lrwork, lapack_int* iwork, lapack_int* liwork,\n                    lapack_int *info );\nvoid LAPACK_zhbgvd( char* jobz, char* uplo, lapack_int* n, lapack_int* ka,\n                    lapack_int* kb, lapack_complex_double* ab, lapack_int* ldab,\n                    lapack_complex_double* bb, lapack_int* ldbb, double* w,\n                    lapack_complex_double* z, lapack_int* ldz,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    double* rwork, lapack_int* lrwork, lapack_int* iwork,\n                    lapack_int* liwork, lapack_int *info );\nvoid LAPACK_ssbgvx( char* jobz, char* range, char* uplo, lapack_int* n,\n                    lapack_int* ka, lapack_int* kb, float* ab, lapack_int* ldab,\n                    float* bb, lapack_int* ldbb, float* q, lapack_int* ldq,\n                    float* vl, float* vu, lapack_int* il, lapack_int* iu,\n                    float* abstol, lapack_int* m, float* w, float* z,\n                    lapack_int* ldz, float* work, lapack_int* iwork,\n                    lapack_int* ifail, lapack_int *info );\nvoid LAPACK_dsbgvx( char* jobz, char* range, char* uplo, lapack_int* n,\n                    lapack_int* ka, lapack_int* kb, double* ab,\n                    lapack_int* ldab, double* bb, lapack_int* ldbb, double* q,\n                    lapack_int* ldq, double* vl, double* vu, lapack_int* il,\n                    lapack_int* iu, double* abstol, lapack_int* m, double* w,\n                    double* z, lapack_int* ldz, double* work, lapack_int* iwork,\n                    lapack_int* ifail, lapack_int *info );\nvoid LAPACK_chbgvx( char* jobz, char* range, char* uplo, lapack_int* n,\n                    lapack_int* ka, lapack_int* kb, lapack_complex_float* ab,\n                    lapack_int* ldab, lapack_complex_float* bb,\n                    lapack_int* ldbb, lapack_complex_float* q, lapack_int* ldq,\n                    float* vl, float* vu, lapack_int* il, lapack_int* iu,\n                    float* abstol, lapack_int* m, float* w,\n                    lapack_complex_float* z, lapack_int* ldz,\n                    lapack_complex_float* work, float* rwork, lapack_int* iwork,\n                    lapack_int* ifail, lapack_int *info );\nvoid LAPACK_zhbgvx( char* jobz, char* range, char* uplo, lapack_int* n,\n                    lapack_int* ka, lapack_int* kb, lapack_complex_double* ab,\n                    lapack_int* ldab, lapack_complex_double* bb,\n                    lapack_int* ldbb, lapack_complex_double* q, lapack_int* ldq,\n                    double* vl, double* vu, lapack_int* il, lapack_int* iu,\n                    double* abstol, lapack_int* m, double* w,\n                    lapack_complex_double* z, lapack_int* ldz,\n                    lapack_complex_double* work, double* rwork,\n                    lapack_int* iwork, lapack_int* ifail, lapack_int *info );\nvoid LAPACK_sgges( char* jobvsl, char* jobvsr, char* sort,\n                   LAPACK_S_SELECT3 selctg, lapack_int* n, float* a,\n                   lapack_int* lda, float* b, lapack_int* ldb, lapack_int* sdim,\n                   float* alphar, float* alphai, float* beta, float* vsl,\n                   lapack_int* ldvsl, float* vsr, lapack_int* ldvsr,\n                   float* work, lapack_int* lwork, lapack_logical* bwork,\n                   lapack_int *info );\nvoid LAPACK_dgges( char* jobvsl, char* jobvsr, char* sort,\n                   LAPACK_D_SELECT3 selctg, lapack_int* n, double* a,\n                   lapack_int* lda, double* b, lapack_int* ldb,\n                   lapack_int* sdim, double* alphar, double* alphai,\n                   double* beta, double* vsl, lapack_int* ldvsl, double* vsr,\n                   lapack_int* ldvsr, double* work, lapack_int* lwork,\n                   lapack_logical* bwork, lapack_int *info );\nvoid LAPACK_cgges( char* jobvsl, char* jobvsr, char* sort,\n                   LAPACK_C_SELECT2 selctg, lapack_int* n,\n                   lapack_complex_float* a, lapack_int* lda,\n                   lapack_complex_float* b, lapack_int* ldb, lapack_int* sdim,\n                   lapack_complex_float* alpha, lapack_complex_float* beta,\n                   lapack_complex_float* vsl, lapack_int* ldvsl,\n                   lapack_complex_float* vsr, lapack_int* ldvsr,\n                   lapack_complex_float* work, lapack_int* lwork, float* rwork,\n                   lapack_logical* bwork, lapack_int *info );\nvoid LAPACK_zgges( char* jobvsl, char* jobvsr, char* sort,\n                   LAPACK_Z_SELECT2 selctg, lapack_int* n,\n                   lapack_complex_double* a, lapack_int* lda,\n                   lapack_complex_double* b, lapack_int* ldb, lapack_int* sdim,\n                   lapack_complex_double* alpha, lapack_complex_double* beta,\n                   lapack_complex_double* vsl, lapack_int* ldvsl,\n                   lapack_complex_double* vsr, lapack_int* ldvsr,\n                   lapack_complex_double* work, lapack_int* lwork,\n                   double* rwork, lapack_logical* bwork, lapack_int *info );\nvoid LAPACK_sggesx( char* jobvsl, char* jobvsr, char* sort,\n                    LAPACK_S_SELECT3 selctg, char* sense, lapack_int* n,\n                    float* a, lapack_int* lda, float* b, lapack_int* ldb,\n                    lapack_int* sdim, float* alphar, float* alphai, float* beta,\n                    float* vsl, lapack_int* ldvsl, float* vsr,\n                    lapack_int* ldvsr, float* rconde, float* rcondv,\n                    float* work, lapack_int* lwork, lapack_int* iwork,\n                    lapack_int* liwork, lapack_logical* bwork,\n                    lapack_int *info );\nvoid LAPACK_dggesx( char* jobvsl, char* jobvsr, char* sort,\n                    LAPACK_D_SELECT3 selctg, char* sense, lapack_int* n,\n                    double* a, lapack_int* lda, double* b, lapack_int* ldb,\n                    lapack_int* sdim, double* alphar, double* alphai,\n                    double* beta, double* vsl, lapack_int* ldvsl, double* vsr,\n                    lapack_int* ldvsr, double* rconde, double* rcondv,\n                    double* work, lapack_int* lwork, lapack_int* iwork,\n                    lapack_int* liwork, lapack_logical* bwork,\n                    lapack_int *info );\nvoid LAPACK_cggesx( char* jobvsl, char* jobvsr, char* sort,\n                    LAPACK_C_SELECT2 selctg, char* sense, lapack_int* n,\n                    lapack_complex_float* a, lapack_int* lda,\n                    lapack_complex_float* b, lapack_int* ldb, lapack_int* sdim,\n                    lapack_complex_float* alpha, lapack_complex_float* beta,\n                    lapack_complex_float* vsl, lapack_int* ldvsl,\n                    lapack_complex_float* vsr, lapack_int* ldvsr, float* rconde,\n                    float* rcondv, lapack_complex_float* work,\n                    lapack_int* lwork, float* rwork, lapack_int* iwork,\n                    lapack_int* liwork, lapack_logical* bwork,\n                    lapack_int *info );\nvoid LAPACK_zggesx( char* jobvsl, char* jobvsr, char* sort,\n                    LAPACK_Z_SELECT2 selctg, char* sense, lapack_int* n,\n                    lapack_complex_double* a, lapack_int* lda,\n                    lapack_complex_double* b, lapack_int* ldb, lapack_int* sdim,\n                    lapack_complex_double* alpha, lapack_complex_double* beta,\n                    lapack_complex_double* vsl, lapack_int* ldvsl,\n                    lapack_complex_double* vsr, lapack_int* ldvsr,\n                    double* rconde, double* rcondv, lapack_complex_double* work,\n                    lapack_int* lwork, double* rwork, lapack_int* iwork,\n                    lapack_int* liwork, lapack_logical* bwork,\n                    lapack_int *info );\nvoid LAPACK_sggev( char* jobvl, char* jobvr, lapack_int* n, float* a,\n                   lapack_int* lda, float* b, lapack_int* ldb, float* alphar,\n                   float* alphai, float* beta, float* vl, lapack_int* ldvl,\n                   float* vr, lapack_int* ldvr, float* work, lapack_int* lwork,\n                   lapack_int *info );\nvoid LAPACK_dggev( char* jobvl, char* jobvr, lapack_int* n, double* a,\n                   lapack_int* lda, double* b, lapack_int* ldb, double* alphar,\n                   double* alphai, double* beta, double* vl, lapack_int* ldvl,\n                   double* vr, lapack_int* ldvr, double* work,\n                   lapack_int* lwork, lapack_int *info );\nvoid LAPACK_cggev( char* jobvl, char* jobvr, lapack_int* n,\n                   lapack_complex_float* a, lapack_int* lda,\n                   lapack_complex_float* b, lapack_int* ldb,\n                   lapack_complex_float* alpha, lapack_complex_float* beta,\n                   lapack_complex_float* vl, lapack_int* ldvl,\n                   lapack_complex_float* vr, lapack_int* ldvr,\n                   lapack_complex_float* work, lapack_int* lwork, float* rwork,\n                   lapack_int *info );\nvoid LAPACK_zggev( char* jobvl, char* jobvr, lapack_int* n,\n                   lapack_complex_double* a, lapack_int* lda,\n                   lapack_complex_double* b, lapack_int* ldb,\n                   lapack_complex_double* alpha, lapack_complex_double* beta,\n                   lapack_complex_double* vl, lapack_int* ldvl,\n                   lapack_complex_double* vr, lapack_int* ldvr,\n                   lapack_complex_double* work, lapack_int* lwork,\n                   double* rwork, lapack_int *info );\nvoid LAPACK_sggevx( char* balanc, char* jobvl, char* jobvr, char* sense,\n                    lapack_int* n, float* a, lapack_int* lda, float* b,\n                    lapack_int* ldb, float* alphar, float* alphai, float* beta,\n                    float* vl, lapack_int* ldvl, float* vr, lapack_int* ldvr,\n                    lapack_int* ilo, lapack_int* ihi, float* lscale,\n                    float* rscale, float* abnrm, float* bbnrm, float* rconde,\n                    float* rcondv, float* work, lapack_int* lwork,\n                    lapack_int* iwork, lapack_logical* bwork,\n                    lapack_int *info );\nvoid LAPACK_dggevx( char* balanc, char* jobvl, char* jobvr, char* sense,\n                    lapack_int* n, double* a, lapack_int* lda, double* b,\n                    lapack_int* ldb, double* alphar, double* alphai,\n                    double* beta, double* vl, lapack_int* ldvl, double* vr,\n                    lapack_int* ldvr, lapack_int* ilo, lapack_int* ihi,\n                    double* lscale, double* rscale, double* abnrm,\n                    double* bbnrm, double* rconde, double* rcondv, double* work,\n                    lapack_int* lwork, lapack_int* iwork, lapack_logical* bwork,\n                    lapack_int *info );\nvoid LAPACK_cggevx( char* balanc, char* jobvl, char* jobvr, char* sense,\n                    lapack_int* n, lapack_complex_float* a, lapack_int* lda,\n                    lapack_complex_float* b, lapack_int* ldb,\n                    lapack_complex_float* alpha, lapack_complex_float* beta,\n                    lapack_complex_float* vl, lapack_int* ldvl,\n                    lapack_complex_float* vr, lapack_int* ldvr, lapack_int* ilo,\n                    lapack_int* ihi, float* lscale, float* rscale, float* abnrm,\n                    float* bbnrm, float* rconde, float* rcondv,\n                    lapack_complex_float* work, lapack_int* lwork, float* rwork,\n                    lapack_int* iwork, lapack_logical* bwork,\n                    lapack_int *info );\nvoid LAPACK_zggevx( char* balanc, char* jobvl, char* jobvr, char* sense,\n                    lapack_int* n, lapack_complex_double* a, lapack_int* lda,\n                    lapack_complex_double* b, lapack_int* ldb,\n                    lapack_complex_double* alpha, lapack_complex_double* beta,\n                    lapack_complex_double* vl, lapack_int* ldvl,\n                    lapack_complex_double* vr, lapack_int* ldvr,\n                    lapack_int* ilo, lapack_int* ihi, double* lscale,\n                    double* rscale, double* abnrm, double* bbnrm,\n                    double* rconde, double* rcondv, lapack_complex_double* work,\n                    lapack_int* lwork, double* rwork, lapack_int* iwork,\n                    lapack_logical* bwork, lapack_int *info );\nvoid LAPACK_dsfrk( char* transr, char* uplo, char* trans, lapack_int* n,\n                   lapack_int* k, double* alpha, const double* a,\n                   lapack_int* lda, double* beta, double* c );\nvoid LAPACK_ssfrk( char* transr, char* uplo, char* trans, lapack_int* n,\n                   lapack_int* k, float* alpha, const float* a, lapack_int* lda,\n                   float* beta, float* c );\nvoid LAPACK_zhfrk( char* transr, char* uplo, char* trans, lapack_int* n,\n                   lapack_int* k, double* alpha, const lapack_complex_double* a,\n                   lapack_int* lda, double* beta, lapack_complex_double* c );\nvoid LAPACK_chfrk( char* transr, char* uplo, char* trans, lapack_int* n,\n                   lapack_int* k, float* alpha, const lapack_complex_float* a,\n                   lapack_int* lda, float* beta, lapack_complex_float* c );\nvoid LAPACK_dtfsm( char* transr, char* side, char* uplo, char* trans,\n                   char* diag, lapack_int* m, lapack_int* n, double* alpha,\n                   const double* a, double* b, lapack_int* ldb );\nvoid LAPACK_stfsm( char* transr, char* side, char* uplo, char* trans,\n                   char* diag, lapack_int* m, lapack_int* n, float* alpha,\n                   const float* a, float* b, lapack_int* ldb );\nvoid LAPACK_ztfsm( char* transr, char* side, char* uplo, char* trans,\n                   char* diag, lapack_int* m, lapack_int* n,\n                   lapack_complex_double* alpha, const lapack_complex_double* a,\n                   lapack_complex_double* b, lapack_int* ldb );\nvoid LAPACK_ctfsm( char* transr, char* side, char* uplo, char* trans,\n                   char* diag, lapack_int* m, lapack_int* n,\n                   lapack_complex_float* alpha, const lapack_complex_float* a,\n                   lapack_complex_float* b, lapack_int* ldb );\nvoid LAPACK_dtfttp( char* transr, char* uplo, lapack_int* n, const double* arf,\n                    double* ap, lapack_int *info );\nvoid LAPACK_stfttp( char* transr, char* uplo, lapack_int* n, const float* arf,\n                    float* ap, lapack_int *info );\nvoid LAPACK_ztfttp( char* transr, char* uplo, lapack_int* n,\n                    const lapack_complex_double* arf, lapack_complex_double* ap,\n                    lapack_int *info );\nvoid LAPACK_ctfttp( char* transr, char* uplo, lapack_int* n,\n                    const lapack_complex_float* arf, lapack_complex_float* ap,\n                    lapack_int *info );\nvoid LAPACK_dtfttr( char* transr, char* uplo, lapack_int* n, const double* arf,\n                    double* a, lapack_int* lda, lapack_int *info );\nvoid LAPACK_stfttr( char* transr, char* uplo, lapack_int* n, const float* arf,\n                    float* a, lapack_int* lda, lapack_int *info );\nvoid LAPACK_ztfttr( char* transr, char* uplo, lapack_int* n,\n                    const lapack_complex_double* arf, lapack_complex_double* a,\n                    lapack_int* lda, lapack_int *info );\nvoid LAPACK_ctfttr( char* transr, char* uplo, lapack_int* n,\n                    const lapack_complex_float* arf, lapack_complex_float* a,\n                    lapack_int* lda, lapack_int *info );\nvoid LAPACK_dtpttf( char* transr, char* uplo, lapack_int* n, const double* ap,\n                    double* arf, lapack_int *info );\nvoid LAPACK_stpttf( char* transr, char* uplo, lapack_int* n, const float* ap,\n                    float* arf, lapack_int *info );\nvoid LAPACK_ztpttf( char* transr, char* uplo, lapack_int* n,\n                    const lapack_complex_double* ap, lapack_complex_double* arf,\n                    lapack_int *info );\nvoid LAPACK_ctpttf( char* transr, char* uplo, lapack_int* n,\n                    const lapack_complex_float* ap, lapack_complex_float* arf,\n                    lapack_int *info );\nvoid LAPACK_dtpttr( char* uplo, lapack_int* n, const double* ap, double* a,\n                    lapack_int* lda, lapack_int *info );\nvoid LAPACK_stpttr( char* uplo, lapack_int* n, const float* ap, float* a,\n                    lapack_int* lda, lapack_int *info );\nvoid LAPACK_ztpttr( char* uplo, lapack_int* n, const lapack_complex_double* ap,\n                    lapack_complex_double* a, lapack_int* lda,\n                    lapack_int *info );\nvoid LAPACK_ctpttr( char* uplo, lapack_int* n, const lapack_complex_float* ap,\n                    lapack_complex_float* a, lapack_int* lda,\n                    lapack_int *info );\nvoid LAPACK_dtrttf( char* transr, char* uplo, lapack_int* n, const double* a,\n                    lapack_int* lda, double* arf, lapack_int *info );\nvoid LAPACK_strttf( char* transr, char* uplo, lapack_int* n, const float* a,\n                    lapack_int* lda, float* arf, lapack_int *info );\nvoid LAPACK_ztrttf( char* transr, char* uplo, lapack_int* n,\n                    const lapack_complex_double* a, lapack_int* lda,\n                    lapack_complex_double* arf, lapack_int *info );\nvoid LAPACK_ctrttf( char* transr, char* uplo, lapack_int* n,\n                    const lapack_complex_float* a, lapack_int* lda,\n                    lapack_complex_float* arf, lapack_int *info );\nvoid LAPACK_dtrttp( char* uplo, lapack_int* n, const double* a, lapack_int* lda,\n                    double* ap, lapack_int *info );\nvoid LAPACK_strttp( char* uplo, lapack_int* n, const float* a, lapack_int* lda,\n                    float* ap, lapack_int *info );\nvoid LAPACK_ztrttp( char* uplo, lapack_int* n, const lapack_complex_double* a,\n                    lapack_int* lda, lapack_complex_double* ap,\n                    lapack_int *info );\nvoid LAPACK_ctrttp( char* uplo, lapack_int* n, const lapack_complex_float* a,\n                    lapack_int* lda, lapack_complex_float* ap,\n                    lapack_int *info );\nvoid LAPACK_sgeqrfp( lapack_int* m, lapack_int* n, float* a, lapack_int* lda,\n                     float* tau, float* work, lapack_int* lwork,\n                     lapack_int *info );\nvoid LAPACK_dgeqrfp( lapack_int* m, lapack_int* n, double* a, lapack_int* lda,\n                     double* tau, double* work, lapack_int* lwork,\n                     lapack_int *info );\nvoid LAPACK_cgeqrfp( lapack_int* m, lapack_int* n, lapack_complex_float* a,\n                     lapack_int* lda, lapack_complex_float* tau,\n                     lapack_complex_float* work, lapack_int* lwork,\n                     lapack_int *info );\nvoid LAPACK_zgeqrfp( lapack_int* m, lapack_int* n, lapack_complex_double* a,\n                     lapack_int* lda, lapack_complex_double* tau,\n                     lapack_complex_double* work, lapack_int* lwork,\n                     lapack_int *info );\nvoid LAPACK_clacgv( lapack_int* n, lapack_complex_float* x, lapack_int* incx );\nvoid LAPACK_zlacgv( lapack_int* n, lapack_complex_double* x, lapack_int* incx );\nvoid LAPACK_slarnv( lapack_int* idist, lapack_int* iseed, lapack_int* n,\n                    float* x );\nvoid LAPACK_dlarnv( lapack_int* idist, lapack_int* iseed, lapack_int* n,\n                    double* x );\nvoid LAPACK_clarnv( lapack_int* idist, lapack_int* iseed, lapack_int* n,\n                    lapack_complex_float* x );\nvoid LAPACK_zlarnv( lapack_int* idist, lapack_int* iseed, lapack_int* n,\n                    lapack_complex_double* x );\nvoid LAPACK_sgeqr2( lapack_int* m, lapack_int* n, float* a, lapack_int* lda,\n                    float* tau, float* work, lapack_int *info );\nvoid LAPACK_dgeqr2( lapack_int* m, lapack_int* n, double* a, lapack_int* lda,\n                    double* tau, double* work, lapack_int *info );\nvoid LAPACK_cgeqr2( lapack_int* m, lapack_int* n, lapack_complex_float* a,\n                    lapack_int* lda, lapack_complex_float* tau,\n                    lapack_complex_float* work, lapack_int *info );\nvoid LAPACK_zgeqr2( lapack_int* m, lapack_int* n, lapack_complex_double* a,\n                    lapack_int* lda, lapack_complex_double* tau,\n                    lapack_complex_double* work, lapack_int *info );\nvoid LAPACK_slacpy( char* uplo, lapack_int* m, lapack_int* n, const float* a,\n                    lapack_int* lda, float* b, lapack_int* ldb );\nvoid LAPACK_dlacpy( char* uplo, lapack_int* m, lapack_int* n, const double* a,\n                    lapack_int* lda, double* b, lapack_int* ldb );\nvoid LAPACK_clacpy( char* uplo, lapack_int* m, lapack_int* n,\n                    const lapack_complex_float* a, lapack_int* lda,\n                    lapack_complex_float* b, lapack_int* ldb );\nvoid LAPACK_zlacpy( char* uplo, lapack_int* m, lapack_int* n,\n                    const lapack_complex_double* a, lapack_int* lda,\n                    lapack_complex_double* b, lapack_int* ldb );\nvoid LAPACK_sgetf2( lapack_int* m, lapack_int* n, float* a, lapack_int* lda,\n                    lapack_int* ipiv, lapack_int *info );\nvoid LAPACK_dgetf2( lapack_int* m, lapack_int* n, double* a, lapack_int* lda,\n                    lapack_int* ipiv, lapack_int *info );\nvoid LAPACK_cgetf2( lapack_int* m, lapack_int* n, lapack_complex_float* a,\n                    lapack_int* lda, lapack_int* ipiv, lapack_int *info );\nvoid LAPACK_zgetf2( lapack_int* m, lapack_int* n, lapack_complex_double* a,\n                    lapack_int* lda, lapack_int* ipiv, lapack_int *info );\nvoid LAPACK_slaswp( lapack_int* n, float* a, lapack_int* lda, lapack_int* k1,\n                    lapack_int* k2, const lapack_int* ipiv, lapack_int* incx );\nvoid LAPACK_dlaswp( lapack_int* n, double* a, lapack_int* lda, lapack_int* k1,\n                    lapack_int* k2, const lapack_int* ipiv, lapack_int* incx );\nvoid LAPACK_claswp( lapack_int* n, lapack_complex_float* a, lapack_int* lda,\n                    lapack_int* k1, lapack_int* k2, const lapack_int* ipiv,\n                    lapack_int* incx );\nvoid LAPACK_zlaswp( lapack_int* n, lapack_complex_double* a, lapack_int* lda,\n                    lapack_int* k1, lapack_int* k2, const lapack_int* ipiv,\n                    lapack_int* incx );\nfloat LAPACK_slange( char* norm, lapack_int* m, lapack_int* n, const float* a,\n                    lapack_int* lda, float* work );\ndouble LAPACK_dlange( char* norm, lapack_int* m, lapack_int* n, const double* a,\n                    lapack_int* lda, double* work );\nfloat LAPACK_clange( char* norm, lapack_int* m, lapack_int* n,\n                    const lapack_complex_float* a, lapack_int* lda, float* work );\ndouble LAPACK_zlange( char* norm, lapack_int* m, lapack_int* n,\n                    const lapack_complex_double* a, lapack_int* lda, double* work );\nfloat LAPACK_clanhe( char* norm, char* uplo, lapack_int* n,\n                    const lapack_complex_float* a, lapack_int* lda, float* work );\ndouble LAPACK_zlanhe( char* norm, char* uplo, lapack_int* n,\n                    const lapack_complex_double* a, lapack_int* lda, double* work );\nfloat LAPACK_slansy( char* norm, char* uplo, lapack_int* n, const float* a,\n                    lapack_int* lda, float* work );\ndouble LAPACK_dlansy( char* norm, char* uplo, lapack_int* n, const double* a,\n                    lapack_int* lda, double* work );\nfloat LAPACK_clansy( char* norm, char* uplo, lapack_int* n,\n                    const lapack_complex_float* a, lapack_int* lda, float* work );\ndouble LAPACK_zlansy( char* norm, char* uplo, lapack_int* n,\n                    const lapack_complex_double* a, lapack_int* lda, double* work );\nfloat LAPACK_slantr( char* norm, char* uplo, char* diag, lapack_int* m,\n                    lapack_int* n, const float* a, lapack_int* lda, float* work );\ndouble LAPACK_dlantr( char* norm, char* uplo, char* diag, lapack_int* m,\n                    lapack_int* n, const double* a, lapack_int* lda, double* work );\nfloat LAPACK_clantr( char* norm, char* uplo, char* diag, lapack_int* m,\n                    lapack_int* n, const lapack_complex_float* a, lapack_int* lda,\n                    float* work );\ndouble LAPACK_zlantr( char* norm, char* uplo, char* diag, lapack_int* m,\n                    lapack_int* n, const lapack_complex_double* a, lapack_int* lda,\n                    double* work );\nfloat LAPACK_slamch( char* cmach );\ndouble LAPACK_dlamch( char* cmach );\nvoid LAPACK_sgelq2( lapack_int* m, lapack_int* n, float* a, lapack_int* lda,\n                    float* tau, float* work, lapack_int *info );\nvoid LAPACK_dgelq2( lapack_int* m, lapack_int* n, double* a, lapack_int* lda,\n                    double* tau, double* work, lapack_int *info );\nvoid LAPACK_cgelq2( lapack_int* m, lapack_int* n, lapack_complex_float* a,\n                    lapack_int* lda, lapack_complex_float* tau,\n                    lapack_complex_float* work, lapack_int *info );\nvoid LAPACK_zgelq2( lapack_int* m, lapack_int* n, lapack_complex_double* a,\n                    lapack_int* lda, lapack_complex_double* tau,\n                    lapack_complex_double* work, lapack_int *info );\nvoid LAPACK_slarfb( char* side, char* trans, char* direct, char* storev,\n                    lapack_int* m, lapack_int* n, lapack_int* k, const float* v,\n                    lapack_int* ldv, const float* t, lapack_int* ldt, float* c,\n                    lapack_int* ldc, float* work, lapack_int* ldwork );\nvoid LAPACK_dlarfb( char* side, char* trans, char* direct, char* storev,\n                    lapack_int* m, lapack_int* n, lapack_int* k,\n                    const double* v, lapack_int* ldv, const double* t,\n                    lapack_int* ldt, double* c, lapack_int* ldc, double* work,\n                    lapack_int* ldwork );\nvoid LAPACK_clarfb( char* side, char* trans, char* direct, char* storev,\n                    lapack_int* m, lapack_int* n, lapack_int* k,\n                    const lapack_complex_float* v, lapack_int* ldv,\n                    const lapack_complex_float* t, lapack_int* ldt,\n                    lapack_complex_float* c, lapack_int* ldc,\n                    lapack_complex_float* work, lapack_int* ldwork );\nvoid LAPACK_zlarfb( char* side, char* trans, char* direct, char* storev,\n                    lapack_int* m, lapack_int* n, lapack_int* k,\n                    const lapack_complex_double* v, lapack_int* ldv,\n                    const lapack_complex_double* t, lapack_int* ldt,\n                    lapack_complex_double* c, lapack_int* ldc,\n                    lapack_complex_double* work, lapack_int* ldwork );\nvoid LAPACK_slarfg( lapack_int* n, float* alpha, float* x, lapack_int* incx,\n                    float* tau );\nvoid LAPACK_dlarfg( lapack_int* n, double* alpha, double* x, lapack_int* incx,\n                    double* tau );\nvoid LAPACK_clarfg( lapack_int* n, lapack_complex_float* alpha,\n                    lapack_complex_float* x, lapack_int* incx,\n                    lapack_complex_float* tau );\nvoid LAPACK_zlarfg( lapack_int* n, lapack_complex_double* alpha,\n                    lapack_complex_double* x, lapack_int* incx,\n                    lapack_complex_double* tau );\nvoid LAPACK_slarft( char* direct, char* storev, lapack_int* n, lapack_int* k,\n                    const float* v, lapack_int* ldv, const float* tau, float* t,\n                    lapack_int* ldt );\nvoid LAPACK_dlarft( char* direct, char* storev, lapack_int* n, lapack_int* k,\n                    const double* v, lapack_int* ldv, const double* tau,\n                    double* t, lapack_int* ldt );\nvoid LAPACK_clarft( char* direct, char* storev, lapack_int* n, lapack_int* k,\n                    const lapack_complex_float* v, lapack_int* ldv,\n                    const lapack_complex_float* tau, lapack_complex_float* t,\n                    lapack_int* ldt );\nvoid LAPACK_zlarft( char* direct, char* storev, lapack_int* n, lapack_int* k,\n                    const lapack_complex_double* v, lapack_int* ldv,\n                    const lapack_complex_double* tau, lapack_complex_double* t,\n                    lapack_int* ldt );\nvoid LAPACK_slarfx( char* side, lapack_int* m, lapack_int* n, const float* v,\n                    float* tau, float* c, lapack_int* ldc, float* work );\nvoid LAPACK_dlarfx( char* side, lapack_int* m, lapack_int* n, const double* v,\n                    double* tau, double* c, lapack_int* ldc, double* work );\nvoid LAPACK_clarfx( char* side, lapack_int* m, lapack_int* n,\n                    const lapack_complex_float* v, lapack_complex_float* tau,\n                    lapack_complex_float* c, lapack_int* ldc,\n                    lapack_complex_float* work );\nvoid LAPACK_zlarfx( char* side, lapack_int* m, lapack_int* n,\n                    const lapack_complex_double* v, lapack_complex_double* tau,\n                    lapack_complex_double* c, lapack_int* ldc,\n                    lapack_complex_double* work );\nvoid LAPACK_slatms( lapack_int* m, lapack_int* n, char* dist, lapack_int* iseed,\n                    char* sym, float* d, lapack_int* mode, float* cond,\n                    float* dmax, lapack_int* kl, lapack_int* ku, char* pack,\n                    float* a, lapack_int* lda, float* work, lapack_int *info );\nvoid LAPACK_dlatms( lapack_int* m, lapack_int* n, char* dist, lapack_int* iseed,\n                    char* sym, double* d, lapack_int* mode, double* cond,\n                    double* dmax, lapack_int* kl, lapack_int* ku, char* pack,\n                    double* a, lapack_int* lda, double* work,\n                    lapack_int *info );\nvoid LAPACK_clatms( lapack_int* m, lapack_int* n, char* dist, lapack_int* iseed,\n                    char* sym, float* d, lapack_int* mode, float* cond,\n                    float* dmax, lapack_int* kl, lapack_int* ku, char* pack,\n                    lapack_complex_float* a, lapack_int* lda,\n                    lapack_complex_float* work, lapack_int *info );\nvoid LAPACK_zlatms( lapack_int* m, lapack_int* n, char* dist, lapack_int* iseed,\n                    char* sym, double* d, lapack_int* mode, double* cond,\n                    double* dmax, lapack_int* kl, lapack_int* ku, char* pack,\n                    lapack_complex_double* a, lapack_int* lda,\n                    lapack_complex_double* work, lapack_int *info );\nvoid LAPACK_slag2d( lapack_int* m, lapack_int* n, const float* sa,\n                    lapack_int* ldsa, double* a, lapack_int* lda,\n                    lapack_int *info );\nvoid LAPACK_dlag2s( lapack_int* m, lapack_int* n, const double* a,\n                    lapack_int* lda, float* sa, lapack_int* ldsa,\n                    lapack_int *info );\nvoid LAPACK_clag2z( lapack_int* m, lapack_int* n,\n                    const lapack_complex_float* sa, lapack_int* ldsa,\n                    lapack_complex_double* a, lapack_int* lda,\n                    lapack_int *info );\nvoid LAPACK_zlag2c( lapack_int* m, lapack_int* n,\n                    const lapack_complex_double* a, lapack_int* lda,\n                    lapack_complex_float* sa, lapack_int* ldsa,\n                    lapack_int *info );\nvoid LAPACK_slauum( char* uplo, lapack_int* n, float* a, lapack_int* lda,\n                    lapack_int *info );\nvoid LAPACK_dlauum( char* uplo, lapack_int* n, double* a, lapack_int* lda,\n                    lapack_int *info );\nvoid LAPACK_clauum( char* uplo, lapack_int* n, lapack_complex_float* a,\n                    lapack_int* lda, lapack_int *info );\nvoid LAPACK_zlauum( char* uplo, lapack_int* n, lapack_complex_double* a,\n                    lapack_int* lda, lapack_int *info );\nvoid LAPACK_slagge( lapack_int* m, lapack_int* n, lapack_int* kl,\n                    lapack_int* ku, const float* d, float* a, lapack_int* lda,\n                    lapack_int* iseed, float* work, lapack_int *info );\nvoid LAPACK_dlagge( lapack_int* m, lapack_int* n, lapack_int* kl,\n                    lapack_int* ku, const double* d, double* a, lapack_int* lda,\n                    lapack_int* iseed, double* work, lapack_int *info );\nvoid LAPACK_clagge( lapack_int* m, lapack_int* n, lapack_int* kl,\n                    lapack_int* ku, const float* d, lapack_complex_float* a,\n                    lapack_int* lda, lapack_int* iseed,\n                    lapack_complex_float* work, lapack_int *info );\nvoid LAPACK_zlagge( lapack_int* m, lapack_int* n, lapack_int* kl,\n                    lapack_int* ku, const double* d, lapack_complex_double* a,\n                    lapack_int* lda, lapack_int* iseed,\n                    lapack_complex_double* work, lapack_int *info );\nvoid LAPACK_slaset( char* uplo, lapack_int* m, lapack_int* n, float* alpha,\n                    float* beta, float* a, lapack_int* lda );\nvoid LAPACK_dlaset( char* uplo, lapack_int* m, lapack_int* n, double* alpha,\n                    double* beta, double* a, lapack_int* lda );\nvoid LAPACK_claset( char* uplo, lapack_int* m, lapack_int* n,\n                    lapack_complex_float* alpha, lapack_complex_float* beta,\n                    lapack_complex_float* a, lapack_int* lda );\nvoid LAPACK_zlaset( char* uplo, lapack_int* m, lapack_int* n,\n                    lapack_complex_double* alpha, lapack_complex_double* beta,\n                    lapack_complex_double* a, lapack_int* lda );\nvoid LAPACK_slasrt( char* id, lapack_int* n, float* d, lapack_int *info );\nvoid LAPACK_dlasrt( char* id, lapack_int* n, double* d, lapack_int *info );\nvoid LAPACK_claghe( lapack_int* n, lapack_int* k, const float* d,\n                    lapack_complex_float* a, lapack_int* lda, lapack_int* iseed,\n                    lapack_complex_float* work, lapack_int *info );\nvoid LAPACK_zlaghe( lapack_int* n, lapack_int* k, const double* d,\n                    lapack_complex_double* a, lapack_int* lda,\n                    lapack_int* iseed, lapack_complex_double* work,\n                    lapack_int *info );\nvoid LAPACK_slagsy( lapack_int* n, lapack_int* k, const float* d, float* a,\n                    lapack_int* lda, lapack_int* iseed, float* work,\n                    lapack_int *info );\nvoid LAPACK_dlagsy( lapack_int* n, lapack_int* k, const double* d, double* a,\n                    lapack_int* lda, lapack_int* iseed, double* work,\n                    lapack_int *info );\nvoid LAPACK_clagsy( lapack_int* n, lapack_int* k, const float* d,\n                    lapack_complex_float* a, lapack_int* lda, lapack_int* iseed,\n                    lapack_complex_float* work, lapack_int *info );\nvoid LAPACK_zlagsy( lapack_int* n, lapack_int* k, const double* d,\n                    lapack_complex_double* a, lapack_int* lda,\n                    lapack_int* iseed, lapack_complex_double* work,\n                    lapack_int *info );\nvoid LAPACK_slapmr( lapack_logical* forwrd, lapack_int* m, lapack_int* n,\n                    float* x, lapack_int* ldx, lapack_int* k );\nvoid LAPACK_dlapmr( lapack_logical* forwrd, lapack_int* m, lapack_int* n,\n                    double* x, lapack_int* ldx, lapack_int* k );\nvoid LAPACK_clapmr( lapack_logical* forwrd, lapack_int* m, lapack_int* n,\n                    lapack_complex_float* x, lapack_int* ldx, lapack_int* k );\nvoid LAPACK_zlapmr( lapack_logical* forwrd, lapack_int* m, lapack_int* n,\n                    lapack_complex_double* x, lapack_int* ldx, lapack_int* k );\nfloat LAPACK_slapy2( float* x, float* y );\ndouble LAPACK_dlapy2( double* x, double* y );\nfloat LAPACK_slapy3( float* x, float* y, float* z );\ndouble LAPACK_dlapy3( double* x, double* y, double* z );\nvoid LAPACK_slartgp( float* f, float* g, float* cs, float* sn, float* r );\nvoid LAPACK_dlartgp( double* f, double* g, double* cs, double* sn, double* r );\nvoid LAPACK_slartgs( float* x, float* y, float* sigma, float* cs, float* sn );\nvoid LAPACK_dlartgs( double* x, double* y, double* sigma, double* cs,\n                     double* sn );\n// LAPACK 3.3.0\nvoid LAPACK_cbbcsd( char* jobu1, char* jobu2,\n                    char* jobv1t, char* jobv2t, char* trans,\n                    lapack_int* m, lapack_int* p, lapack_int* q,\n                    float* theta, float* phi,\n                    lapack_complex_float* u1, lapack_int* ldu1,\n                    lapack_complex_float* u2, lapack_int* ldu2,\n                    lapack_complex_float* v1t, lapack_int* ldv1t,\n                    lapack_complex_float* v2t, lapack_int* ldv2t,\n                    float* b11d, float* b11e, float* b12d,\n                    float* b12e, float* b21d, float* b21e,\n                    float* b22d, float* b22e, float* rwork,\n                    lapack_int* lrwork , lapack_int *info );\nvoid LAPACK_cheswapr( char* uplo, lapack_int* n,\n                      lapack_complex_float* a, lapack_int* i1,\n                      lapack_int* i2 );\nvoid LAPACK_chetri2( char* uplo, lapack_int* n,\n                     lapack_complex_float* a, lapack_int* lda,\n                     const lapack_int* ipiv,\n                     lapack_complex_float* work, lapack_int* lwork , lapack_int *info );\nvoid LAPACK_chetri2x( char* uplo, lapack_int* n,\n                      lapack_complex_float* a, lapack_int* lda,\n                      const lapack_int* ipiv,\n                      lapack_complex_float* work, lapack_int* nb , lapack_int *info );\nvoid LAPACK_chetrs2( char* uplo, lapack_int* n,\n                     lapack_int* nrhs, const lapack_complex_float* a,\n                     lapack_int* lda, const lapack_int* ipiv,\n                     lapack_complex_float* b, lapack_int* ldb,\n                     lapack_complex_float* work , lapack_int *info );\nvoid LAPACK_csyconv( char* uplo, char* way,\n                     lapack_int* n, lapack_complex_float* a,\n                     lapack_int* lda, const lapack_int* ipiv,\n                     lapack_complex_float* work , lapack_int *info );\nvoid LAPACK_csyswapr( char* uplo, lapack_int* n,\n                      lapack_complex_float* a, lapack_int* i1,\n                      lapack_int* i2 );\nvoid LAPACK_csytri2( char* uplo, lapack_int* n,\n                     lapack_complex_float* a, lapack_int* lda,\n                     const lapack_int* ipiv,\n                     lapack_complex_float* work, lapack_int* lwork , lapack_int *info );\nvoid LAPACK_csytri2x( char* uplo, lapack_int* n,\n                      lapack_complex_float* a, lapack_int* lda,\n                      const lapack_int* ipiv,\n                      lapack_complex_float* work, lapack_int* nb , lapack_int *info );\nvoid LAPACK_csytrs2( char* uplo, lapack_int* n,\n                     lapack_int* nrhs, const lapack_complex_float* a,\n                     lapack_int* lda, const lapack_int* ipiv,\n                     lapack_complex_float* b, lapack_int* ldb,\n                     lapack_complex_float* work , lapack_int *info );\nvoid LAPACK_cunbdb( char* trans, char* signs,\n                    lapack_int* m, lapack_int* p, lapack_int* q,\n                    lapack_complex_float* x11, lapack_int* ldx11,\n                    lapack_complex_float* x12, lapack_int* ldx12,\n                    lapack_complex_float* x21, lapack_int* ldx21,\n                    lapack_complex_float* x22, lapack_int* ldx22,\n                    float* theta, float* phi,\n                    lapack_complex_float* taup1,\n                    lapack_complex_float* taup2,\n                    lapack_complex_float* tauq1,\n                    lapack_complex_float* tauq2,\n                    lapack_complex_float* work, lapack_int* lwork , lapack_int *info );\nvoid LAPACK_cuncsd( char* jobu1, char* jobu2,\n                    char* jobv1t, char* jobv2t, char* trans,\n                    char* signs, lapack_int* m, lapack_int* p,\n                    lapack_int* q, lapack_complex_float* x11,\n                    lapack_int* ldx11, lapack_complex_float* x12,\n                    lapack_int* ldx12, lapack_complex_float* x21,\n                    lapack_int* ldx21, lapack_complex_float* x22,\n                    lapack_int* ldx22, float* theta,\n                    lapack_complex_float* u1, lapack_int* ldu1,\n                    lapack_complex_float* u2, lapack_int* ldu2,\n                    lapack_complex_float* v1t, lapack_int* ldv1t,\n                    lapack_complex_float* v2t, lapack_int* ldv2t,\n                    lapack_complex_float* work, lapack_int* lwork,\n                    float* rwork, lapack_int* lrwork,\n                    lapack_int* iwork , lapack_int *info );\nvoid LAPACK_dbbcsd( char* jobu1, char* jobu2,\n                    char* jobv1t, char* jobv2t, char* trans,\n                    lapack_int* m, lapack_int* p, lapack_int* q,\n                    double* theta, double* phi, double* u1,\n                    lapack_int* ldu1, double* u2, lapack_int* ldu2,\n                    double* v1t, lapack_int* ldv1t, double* v2t,\n                    lapack_int* ldv2t, double* b11d, double* b11e,\n                    double* b12d, double* b12e, double* b21d,\n                    double* b21e, double* b22d, double* b22e,\n                    double* work, lapack_int* lwork , lapack_int *info );\nvoid LAPACK_dorbdb( char* trans, char* signs,\n                    lapack_int* m, lapack_int* p, lapack_int* q,\n                    double* x11, lapack_int* ldx11, double* x12,\n                    lapack_int* ldx12, double* x21, lapack_int* ldx21,\n                    double* x22, lapack_int* ldx22, double* theta,\n                    double* phi, double* taup1, double* taup2,\n                    double* tauq1, double* tauq2, double* work,\n                    lapack_int* lwork , lapack_int *info );\nvoid LAPACK_dorcsd( char* jobu1, char* jobu2,\n                    char* jobv1t, char* jobv2t, char* trans,\n                    char* signs, lapack_int* m, lapack_int* p,\n                    lapack_int* q, double* x11, lapack_int* ldx11,\n                    double* x12, lapack_int* ldx12, double* x21,\n                    lapack_int* ldx21, double* x22, lapack_int* ldx22,\n                    double* theta, double* u1, lapack_int* ldu1,\n                    double* u2, lapack_int* ldu2, double* v1t,\n                    lapack_int* ldv1t, double* v2t, lapack_int* ldv2t,\n                    double* work, lapack_int* lwork,\n                    lapack_int* iwork , lapack_int *info );\nvoid LAPACK_dsyconv( char* uplo, char* way,\n                     lapack_int* n, double* a, lapack_int* lda,\n                     const lapack_int* ipiv, double* work , lapack_int *info );\nvoid LAPACK_dsyswapr( char* uplo, lapack_int* n,\n                      double* a, lapack_int* i1, lapack_int* i2 );\nvoid LAPACK_dsytri2( char* uplo, lapack_int* n,\n                     double* a, lapack_int* lda,\n                     const lapack_int* ipiv,\n                     lapack_complex_double* work, lapack_int* lwork , lapack_int *info );\nvoid LAPACK_dsytri2x( char* uplo, lapack_int* n,\n                      double* a, lapack_int* lda,\n                      const lapack_int* ipiv, double* work,\n                      lapack_int* nb , lapack_int *info );\nvoid LAPACK_dsytrs2( char* uplo, lapack_int* n,\n                     lapack_int* nrhs, const double* a,\n                     lapack_int* lda, const lapack_int* ipiv,\n                     double* b, lapack_int* ldb, double* work , lapack_int *info );\nvoid LAPACK_sbbcsd( char* jobu1, char* jobu2,\n                    char* jobv1t, char* jobv2t, char* trans,\n                    lapack_int* m, lapack_int* p, lapack_int* q,\n                    float* theta, float* phi, float* u1,\n                    lapack_int* ldu1, float* u2, lapack_int* ldu2,\n                    float* v1t, lapack_int* ldv1t, float* v2t,\n                    lapack_int* ldv2t, float* b11d, float* b11e,\n                    float* b12d, float* b12e, float* b21d,\n                    float* b21e, float* b22d, float* b22e,\n                    float* work, lapack_int* lwork , lapack_int *info );\nvoid LAPACK_sorbdb( char* trans, char* signs,\n                    lapack_int* m, lapack_int* p, lapack_int* q,\n                    float* x11, lapack_int* ldx11, float* x12,\n                    lapack_int* ldx12, float* x21, lapack_int* ldx21,\n                    float* x22, lapack_int* ldx22, float* theta,\n                    float* phi, float* taup1, float* taup2,\n                    float* tauq1, float* tauq2, float* work,\n                    lapack_int* lwork , lapack_int *info );\nvoid LAPACK_sorcsd( char* jobu1, char* jobu2,\n                    char* jobv1t, char* jobv2t, char* trans,\n                    char* signs, lapack_int* m, lapack_int* p,\n                    lapack_int* q, float* x11, lapack_int* ldx11,\n                    float* x12, lapack_int* ldx12, float* x21,\n                    lapack_int* ldx21, float* x22, lapack_int* ldx22,\n                    float* theta, float* u1, lapack_int* ldu1,\n                    float* u2, lapack_int* ldu2, float* v1t,\n                    lapack_int* ldv1t, float* v2t, lapack_int* ldv2t,\n                    float* work, lapack_int* lwork,\n                    lapack_int* iwork , lapack_int *info );\nvoid LAPACK_ssyconv( char* uplo, char* way,\n                     lapack_int* n, float* a, lapack_int* lda,\n                     const lapack_int* ipiv, float* work , lapack_int *info );\nvoid LAPACK_ssyswapr( char* uplo, lapack_int* n,\n                      float* a, lapack_int* i1, lapack_int* i2 );\nvoid LAPACK_ssytri2( char* uplo, lapack_int* n,\n                     float* a, lapack_int* lda,\n                     const lapack_int* ipiv,\n                     lapack_complex_float* work, lapack_int* lwork , lapack_int *info );\nvoid LAPACK_ssytri2x( char* uplo, lapack_int* n,\n                      float* a, lapack_int* lda,\n                      const lapack_int* ipiv, float* work,\n                      lapack_int* nb , lapack_int *info );\nvoid LAPACK_ssytrs2( char* uplo, lapack_int* n,\n                     lapack_int* nrhs, const float* a,\n                     lapack_int* lda, const lapack_int* ipiv,\n                     float* b, lapack_int* ldb, float* work , lapack_int *info );\nvoid LAPACK_zbbcsd( char* jobu1, char* jobu2,\n                    char* jobv1t, char* jobv2t, char* trans,\n                    lapack_int* m, lapack_int* p, lapack_int* q,\n                    double* theta, double* phi,\n                    lapack_complex_double* u1, lapack_int* ldu1,\n                    lapack_complex_double* u2, lapack_int* ldu2,\n                    lapack_complex_double* v1t, lapack_int* ldv1t,\n                    lapack_complex_double* v2t, lapack_int* ldv2t,\n                    double* b11d, double* b11e, double* b12d,\n                    double* b12e, double* b21d, double* b21e,\n                    double* b22d, double* b22e, double* rwork,\n                    lapack_int* lrwork , lapack_int *info );\nvoid LAPACK_zheswapr( char* uplo, lapack_int* n,\n                      lapack_complex_double* a, lapack_int* i1,\n                      lapack_int* i2 );\nvoid LAPACK_zhetri2( char* uplo, lapack_int* n,\n                     lapack_complex_double* a, lapack_int* lda,\n                     const lapack_int* ipiv,\n                     lapack_complex_double* work, lapack_int* lwork , lapack_int *info );\nvoid LAPACK_zhetri2x( char* uplo, lapack_int* n,\n                      lapack_complex_double* a, lapack_int* lda,\n                      const lapack_int* ipiv,\n                      lapack_complex_double* work, lapack_int* nb , lapack_int *info );\nvoid LAPACK_zhetrs2( char* uplo, lapack_int* n,\n                     lapack_int* nrhs,\n                     const lapack_complex_double* a, lapack_int* lda,\n                     const lapack_int* ipiv,\n                     lapack_complex_double* b, lapack_int* ldb,\n                     lapack_complex_double* work , lapack_int *info );\nvoid LAPACK_zsyconv( char* uplo, char* way,\n                     lapack_int* n, lapack_complex_double* a,\n                     lapack_int* lda, const lapack_int* ipiv,\n                     lapack_complex_double* work , lapack_int *info );\nvoid LAPACK_zsyswapr( char* uplo, lapack_int* n,\n                      lapack_complex_double* a, lapack_int* i1,\n                      lapack_int* i2 );\nvoid LAPACK_zsytri2( char* uplo, lapack_int* n,\n                     lapack_complex_double* a, lapack_int* lda,\n                     const lapack_int* ipiv,\n                     lapack_complex_double* work, lapack_int* lwork , lapack_int *info );\nvoid LAPACK_zsytri2x( char* uplo, lapack_int* n,\n                      lapack_complex_double* a, lapack_int* lda,\n                      const lapack_int* ipiv,\n                      lapack_complex_double* work, lapack_int* nb , lapack_int *info );\nvoid LAPACK_zsytrs2( char* uplo, lapack_int* n,\n                     lapack_int* nrhs,\n                     const lapack_complex_double* a, lapack_int* lda,\n                     const lapack_int* ipiv,\n                     lapack_complex_double* b, lapack_int* ldb,\n                     lapack_complex_double* work , lapack_int *info );\nvoid LAPACK_zunbdb( char* trans, char* signs,\n                    lapack_int* m, lapack_int* p, lapack_int* q,\n                    lapack_complex_double* x11, lapack_int* ldx11,\n                    lapack_complex_double* x12, lapack_int* ldx12,\n                    lapack_complex_double* x21, lapack_int* ldx21,\n                    lapack_complex_double* x22, lapack_int* ldx22,\n                    double* theta, double* phi,\n                    lapack_complex_double* taup1,\n                    lapack_complex_double* taup2,\n                    lapack_complex_double* tauq1,\n                    lapack_complex_double* tauq2,\n                    lapack_complex_double* work, lapack_int* lwork , lapack_int *info );\nvoid LAPACK_zuncsd( char* jobu1, char* jobu2,\n                    char* jobv1t, char* jobv2t, char* trans,\n                    char* signs, lapack_int* m, lapack_int* p,\n                    lapack_int* q, lapack_complex_double* x11,\n                    lapack_int* ldx11, lapack_complex_double* x12,\n                    lapack_int* ldx12, lapack_complex_double* x21,\n                    lapack_int* ldx21, lapack_complex_double* x22,\n                    lapack_int* ldx22, double* theta,\n                    lapack_complex_double* u1, lapack_int* ldu1,\n                    lapack_complex_double* u2, lapack_int* ldu2,\n                    lapack_complex_double* v1t, lapack_int* ldv1t,\n                    lapack_complex_double* v2t, lapack_int* ldv2t,\n                    lapack_complex_double* work, lapack_int* lwork,\n                    double* rwork, lapack_int* lrwork,\n                    lapack_int* iwork , lapack_int *info );\n// LAPACK 3.4.0\nvoid LAPACK_sgemqrt( char* side, char* trans, lapack_int* m, lapack_int* n,\n                     lapack_int* k, lapack_int* nb, const float* v,\n                     lapack_int* ldv, const float* t, lapack_int* ldt, float* c,\n                     lapack_int* ldc, float* work, lapack_int *info );\nvoid LAPACK_dgemqrt( char* side, char* trans, lapack_int* m, lapack_int* n,\n                     lapack_int* k, lapack_int* nb, const double* v,\n                     lapack_int* ldv, const double* t, lapack_int* ldt,\n                     double* c, lapack_int* ldc, double* work,\n                     lapack_int *info );\nvoid LAPACK_cgemqrt( char* side, char* trans, lapack_int* m, lapack_int* n,\n                     lapack_int* k, lapack_int* nb,\n                     const lapack_complex_float* v, lapack_int* ldv,\n                     const lapack_complex_float* t, lapack_int* ldt,\n                     lapack_complex_float* c, lapack_int* ldc,\n                     lapack_complex_float* work, lapack_int *info );\nvoid LAPACK_zgemqrt( char* side, char* trans, lapack_int* m, lapack_int* n,\n                     lapack_int* k, lapack_int* nb,\n                     const lapack_complex_double* v, lapack_int* ldv,\n                     const lapack_complex_double* t, lapack_int* ldt,\n                     lapack_complex_double* c, lapack_int* ldc,\n                     lapack_complex_double* work, lapack_int *info );\nvoid LAPACK_sgeqrt( lapack_int* m, lapack_int* n, lapack_int* nb, float* a,\n                    lapack_int* lda, float* t, lapack_int* ldt, float* work,\n                    lapack_int *info );\nvoid LAPACK_dgeqrt( lapack_int* m, lapack_int* n, lapack_int* nb, double* a,\n                    lapack_int* lda, double* t, lapack_int* ldt, double* work,\n                    lapack_int *info );\nvoid LAPACK_cgeqrt( lapack_int* m, lapack_int* n, lapack_int* nb,\n                    lapack_complex_float* a, lapack_int* lda,\n                    lapack_complex_float* t, lapack_int* ldt,\n                    lapack_complex_float* work, lapack_int *info );\nvoid LAPACK_zgeqrt( lapack_int* m, lapack_int* n, lapack_int* nb,\n                    lapack_complex_double* a, lapack_int* lda,\n                    lapack_complex_double* t, lapack_int* ldt,\n                    lapack_complex_double* work, lapack_int *info );\nvoid LAPACK_sgeqrt2( lapack_int* m, lapack_int* n, float* a, lapack_int* lda,\n                     float* t, lapack_int* ldt, lapack_int *info );\nvoid LAPACK_dgeqrt2( lapack_int* m, lapack_int* n, double* a, lapack_int* lda,\n                     double* t, lapack_int* ldt, lapack_int *info );\nvoid LAPACK_cgeqrt2( lapack_int* m, lapack_int* n, lapack_complex_float* a,\n                     lapack_int* lda, lapack_complex_float* t, lapack_int* ldt,\n                     lapack_int *info );\nvoid LAPACK_zgeqrt2( lapack_int* m, lapack_int* n, lapack_complex_double* a,\n                     lapack_int* lda, lapack_complex_double* t, lapack_int* ldt,\n                     lapack_int *info );\nvoid LAPACK_sgeqrt3( lapack_int* m, lapack_int* n, float* a, lapack_int* lda,\n                     float* t, lapack_int* ldt, lapack_int *info );\nvoid LAPACK_dgeqrt3( lapack_int* m, lapack_int* n, double* a, lapack_int* lda,\n                     double* t, lapack_int* ldt, lapack_int *info );\nvoid LAPACK_cgeqrt3( lapack_int* m, lapack_int* n, lapack_complex_float* a,\n                     lapack_int* lda, lapack_complex_float* t, lapack_int* ldt,\n                     lapack_int *info );\nvoid LAPACK_zgeqrt3( lapack_int* m, lapack_int* n, lapack_complex_double* a,\n                     lapack_int* lda, lapack_complex_double* t, lapack_int* ldt,\n                     lapack_int *info );\nvoid LAPACK_stpmqrt( char* side, char* trans, lapack_int* m, lapack_int* n,\n                     lapack_int* k, lapack_int* l, lapack_int* nb,\n                     const float* v, lapack_int* ldv, const float* t,\n                     lapack_int* ldt, float* a, lapack_int* lda, float* b,\n                     lapack_int* ldb, float* work, lapack_int *info );\nvoid LAPACK_dtpmqrt( char* side, char* trans, lapack_int* m, lapack_int* n,\n                     lapack_int* k, lapack_int* l, lapack_int* nb,\n                     const double* v, lapack_int* ldv, const double* t,\n                     lapack_int* ldt, double* a, lapack_int* lda, double* b,\n                     lapack_int* ldb, double* work, lapack_int *info );\nvoid LAPACK_ctpmqrt( char* side, char* trans, lapack_int* m, lapack_int* n,\n                     lapack_int* k, lapack_int* l, lapack_int* nb,\n                     const lapack_complex_float* v, lapack_int* ldv,\n                     const lapack_complex_float* t, lapack_int* ldt,\n                     lapack_complex_float* a, lapack_int* lda,\n                     lapack_complex_float* b, lapack_int* ldb,\n                     lapack_complex_float* work, lapack_int *info );\nvoid LAPACK_ztpmqrt( char* side, char* trans, lapack_int* m, lapack_int* n,\n                     lapack_int* k, lapack_int* l, lapack_int* nb,\n                     const lapack_complex_double* v, lapack_int* ldv,\n                     const lapack_complex_double* t, lapack_int* ldt,\n                     lapack_complex_double* a, lapack_int* lda,\n                     lapack_complex_double* b, lapack_int* ldb,\n                     lapack_complex_double* work, lapack_int *info );\nvoid LAPACK_dtpqrt( lapack_int* m, lapack_int* n, lapack_int* l, lapack_int* nb,\n                    double* a, lapack_int* lda, double* b, lapack_int* ldb,\n                    double* t, lapack_int* ldt, double* work,\n                    lapack_int *info );\nvoid LAPACK_ctpqrt( lapack_int* m, lapack_int* n, lapack_int* l, lapack_int* nb,\n                    lapack_complex_float* a, lapack_int* lda,\n                    lapack_complex_float* t, lapack_complex_float* b,\n                    lapack_int* ldb, lapack_int* ldt,\n                    lapack_complex_float* work, lapack_int *info );\nvoid LAPACK_ztpqrt( lapack_int* m, lapack_int* n, lapack_int* l, lapack_int* nb,\n                    lapack_complex_double* a, lapack_int* lda,\n                    lapack_complex_double* b, lapack_int* ldb,\n                    lapack_complex_double* t, lapack_int* ldt,\n                    lapack_complex_double* work, lapack_int *info );\nvoid LAPACK_stpqrt2( lapack_int* m, lapack_int* n, float* a, lapack_int* lda,\n                     float* b, lapack_int* ldb, float* t, lapack_int* ldt,\n                     lapack_int *info );\nvoid LAPACK_dtpqrt2( lapack_int* m, lapack_int* n, double* a, lapack_int* lda,\n                     double* b, lapack_int* ldb, double* t, lapack_int* ldt,\n                     lapack_int *info );\nvoid LAPACK_ctpqrt2( lapack_int* m, lapack_int* n, lapack_complex_float* a,\n                     lapack_int* lda, lapack_complex_float* b, lapack_int* ldb,\n                     lapack_complex_float* t, lapack_int* ldt,\n                     lapack_int *info );\nvoid LAPACK_ztpqrt2( lapack_int* m, lapack_int* n, lapack_complex_double* a,\n                     lapack_int* lda, lapack_complex_double* b, lapack_int* ldb,\n                     lapack_complex_double* t, lapack_int* ldt,\n                     lapack_int *info );\nvoid LAPACK_stprfb( char* side, char* trans, char* direct, char* storev,\n                    lapack_int* m, lapack_int* n, lapack_int* k, lapack_int* l,\n                    const float* v, lapack_int* ldv, const float* t,\n                    lapack_int* ldt, float* a, lapack_int* lda, float* b,\n                    lapack_int* ldb, const float* mywork,\n                    lapack_int* myldwork );\nvoid LAPACK_dtprfb( char* side, char* trans, char* direct, char* storev,\n                    lapack_int* m, lapack_int* n, lapack_int* k, lapack_int* l,\n                    const double* v, lapack_int* ldv, const double* t,\n                    lapack_int* ldt, double* a, lapack_int* lda, double* b,\n                    lapack_int* ldb, const double* mywork,\n                    lapack_int* myldwork );\nvoid LAPACK_ctprfb( char* side, char* trans, char* direct, char* storev,\n                    lapack_int* m, lapack_int* n, lapack_int* k, lapack_int* l,\n                    const lapack_complex_float* v, lapack_int* ldv,\n                    const lapack_complex_float* t, lapack_int* ldt,\n                    lapack_complex_float* a, lapack_int* lda,\n                    lapack_complex_float* b, lapack_int* ldb,\n                    const float* mywork, lapack_int* myldwork );\nvoid LAPACK_ztprfb( char* side, char* trans, char* direct, char* storev,\n                    lapack_int* m, lapack_int* n, lapack_int* k, lapack_int* l,\n                    const lapack_complex_double* v, lapack_int* ldv,\n                    const lapack_complex_double* t, lapack_int* ldt,\n                    lapack_complex_double* a, lapack_int* lda,\n                    lapack_complex_double* b, lapack_int* ldb,\n                    const double* mywork, lapack_int* myldwork );\n// LAPACK 3.X.X\nvoid LAPACK_csyr( char* uplo, lapack_int* n, lapack_complex_float* alpha,\n                      const lapack_complex_float* x, lapack_int* incx,\n                      lapack_complex_float* a, lapack_int* lda );\nvoid LAPACK_zsyr( char* uplo, lapack_int* n, lapack_complex_double* alpha,\n                      const lapack_complex_double* x, lapack_int* incx,\n                      lapack_complex_double* a, lapack_int* lda );\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* _LAPACKE_H_ */\n\n#endif /* _MKL_LAPACKE_H_ */\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/misc/lapacke_mangling.h",
    "content": "#ifndef LAPACK_HEADER_INCLUDED\n#define LAPACK_HEADER_INCLUDED\n\n#ifndef LAPACK_GLOBAL\n#if defined(LAPACK_GLOBAL_PATTERN_LC) || defined(ADD_)\n#define LAPACK_GLOBAL(lcname,UCNAME)  lcname##_\n#elif defined(LAPACK_GLOBAL_PATTERN_UC) || defined(UPPER)\n#define LAPACK_GLOBAL(lcname,UCNAME)  UCNAME\n#elif defined(LAPACK_GLOBAL_PATTERN_MC) || defined(NOCHANGE)\n#define LAPACK_GLOBAL(lcname,UCNAME)  lcname\n#else\n#define LAPACK_GLOBAL(lcname,UCNAME)  lcname##_\n#endif\n#endif\n\n#endif\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/plugins/ArrayCwiseBinaryOps.h",
    "content": "\n/** \\returns an expression of the coefficient wise product of \\c *this and \\a other\n  *\n  * \\sa MatrixBase::cwiseProduct\n  */\ntemplate<typename OtherDerived>\nEIGEN_DEVICE_FUNC\nEIGEN_STRONG_INLINE const EIGEN_CWISE_BINARY_RETURN_TYPE(Derived,OtherDerived,product)\noperator*(const EIGEN_CURRENT_STORAGE_BASE_CLASS<OtherDerived> &other) const\n{\n  return EIGEN_CWISE_BINARY_RETURN_TYPE(Derived,OtherDerived,product)(derived(), other.derived());\n}\n\n/** \\returns an expression of the coefficient wise quotient of \\c *this and \\a other\n  *\n  * \\sa MatrixBase::cwiseQuotient\n  */\ntemplate<typename OtherDerived>\nEIGEN_DEVICE_FUNC\nEIGEN_STRONG_INLINE const CwiseBinaryOp<internal::scalar_quotient_op<Scalar,typename OtherDerived::Scalar>, const Derived, const OtherDerived>\noperator/(const EIGEN_CURRENT_STORAGE_BASE_CLASS<OtherDerived> &other) const\n{\n  return CwiseBinaryOp<internal::scalar_quotient_op<Scalar,typename OtherDerived::Scalar>, const Derived, const OtherDerived>(derived(), other.derived());\n}\n\n/** \\returns an expression of the coefficient-wise min of \\c *this and \\a other\n  *\n  * Example: \\include Cwise_min.cpp\n  * Output: \\verbinclude Cwise_min.out\n  *\n  * \\sa max()\n  */\nEIGEN_MAKE_CWISE_BINARY_OP(min,min)\n\n/** \\returns an expression of the coefficient-wise min of \\c *this and scalar \\a other\n  *\n  * \\sa max()\n  */\nEIGEN_DEVICE_FUNC\nEIGEN_STRONG_INLINE const CwiseBinaryOp<internal::scalar_min_op<Scalar,Scalar>, const Derived,\n                                        const CwiseNullaryOp<internal::scalar_constant_op<Scalar>, PlainObject> >\n#ifdef EIGEN_PARSED_BY_DOXYGEN\nmin\n#else\n(min)\n#endif\n(const Scalar &other) const\n{\n  return (min)(Derived::PlainObject::Constant(rows(), cols(), other));\n}\n\n/** \\returns an expression of the coefficient-wise max of \\c *this and \\a other\n  *\n  * Example: \\include Cwise_max.cpp\n  * Output: \\verbinclude Cwise_max.out\n  *\n  * \\sa min()\n  */\nEIGEN_MAKE_CWISE_BINARY_OP(max,max)\n\n/** \\returns an expression of the coefficient-wise max of \\c *this and scalar \\a other\n  *\n  * \\sa min()\n  */\nEIGEN_DEVICE_FUNC\nEIGEN_STRONG_INLINE const CwiseBinaryOp<internal::scalar_max_op<Scalar,Scalar>, const Derived,\n                                        const CwiseNullaryOp<internal::scalar_constant_op<Scalar>, PlainObject> >\n#ifdef EIGEN_PARSED_BY_DOXYGEN\nmax\n#else\n(max)\n#endif\n(const Scalar &other) const\n{\n  return (max)(Derived::PlainObject::Constant(rows(), cols(), other));\n}\n\n/** \\returns an expression of the coefficient-wise power of \\c *this to the given array of \\a exponents.\n  *\n  * This function computes the coefficient-wise power.\n  *\n  * Example: \\include Cwise_array_power_array.cpp\n  * Output: \\verbinclude Cwise_array_power_array.out\n  */\nEIGEN_MAKE_CWISE_BINARY_OP(pow,pow)\n\n#ifndef EIGEN_PARSED_BY_DOXYGEN\nEIGEN_MAKE_SCALAR_BINARY_OP_ONTHERIGHT(pow,pow)\n#else\n/** \\returns an expression of the coefficients of \\c *this rasied to the constant power \\a exponent\n  *\n  * \\tparam T is the scalar type of \\a exponent. It must be compatible with the scalar type of the given expression.\n  *\n  * This function computes the coefficient-wise power. The function MatrixBase::pow() in the\n  * unsupported module MatrixFunctions computes the matrix power.\n  *\n  * Example: \\include Cwise_pow.cpp\n  * Output: \\verbinclude Cwise_pow.out\n  *\n  * \\sa ArrayBase::pow(ArrayBase), square(), cube(), exp(), log()\n  */\ntemplate<typename T>\nconst CwiseBinaryOp<internal::scalar_pow_op<Scalar,T>,Derived,Constant<T> > pow(const T& exponent) const;\n#endif\n\n\n// TODO code generating macros could be moved to Macros.h and could include generation of documentation\n#define EIGEN_MAKE_CWISE_COMP_OP(OP, COMPARATOR) \\\ntemplate<typename OtherDerived> \\\nEIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const CwiseBinaryOp<internal::scalar_cmp_op<Scalar, typename OtherDerived::Scalar, internal::cmp_ ## COMPARATOR>, const Derived, const OtherDerived> \\\nOP(const EIGEN_CURRENT_STORAGE_BASE_CLASS<OtherDerived> &other) const \\\n{ \\\n  return CwiseBinaryOp<internal::scalar_cmp_op<Scalar, typename OtherDerived::Scalar, internal::cmp_ ## COMPARATOR>, const Derived, const OtherDerived>(derived(), other.derived()); \\\n}\\\ntypedef CwiseBinaryOp<internal::scalar_cmp_op<Scalar,Scalar, internal::cmp_ ## COMPARATOR>, const Derived, const CwiseNullaryOp<internal::scalar_constant_op<Scalar>, PlainObject> > Cmp ## COMPARATOR ## ReturnType; \\\ntypedef CwiseBinaryOp<internal::scalar_cmp_op<Scalar,Scalar, internal::cmp_ ## COMPARATOR>, const CwiseNullaryOp<internal::scalar_constant_op<Scalar>, PlainObject>, const Derived > RCmp ## COMPARATOR ## ReturnType; \\\nEIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const Cmp ## COMPARATOR ## ReturnType \\\nOP(const Scalar& s) const { \\\n  return this->OP(Derived::PlainObject::Constant(rows(), cols(), s)); \\\n} \\\nEIGEN_DEVICE_FUNC friend EIGEN_STRONG_INLINE const RCmp ## COMPARATOR ## ReturnType \\\nOP(const Scalar& s, const Derived& d) { \\\n  return Derived::PlainObject::Constant(d.rows(), d.cols(), s).OP(d); \\\n}\n\n#define EIGEN_MAKE_CWISE_COMP_R_OP(OP, R_OP, RCOMPARATOR) \\\ntemplate<typename OtherDerived> \\\nEIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const CwiseBinaryOp<internal::scalar_cmp_op<typename OtherDerived::Scalar, Scalar, internal::cmp_##RCOMPARATOR>, const OtherDerived, const Derived> \\\nOP(const EIGEN_CURRENT_STORAGE_BASE_CLASS<OtherDerived> &other) const \\\n{ \\\n  return CwiseBinaryOp<internal::scalar_cmp_op<typename OtherDerived::Scalar, Scalar, internal::cmp_##RCOMPARATOR>, const OtherDerived, const Derived>(other.derived(), derived()); \\\n} \\\nEIGEN_DEVICE_FUNC \\\ninline const RCmp ## RCOMPARATOR ## ReturnType \\\nOP(const Scalar& s) const { \\\n  return Derived::PlainObject::Constant(rows(), cols(), s).R_OP(*this); \\\n} \\\nfriend inline const Cmp ## RCOMPARATOR ## ReturnType \\\nOP(const Scalar& s, const Derived& d) { \\\n  return d.R_OP(Derived::PlainObject::Constant(d.rows(), d.cols(), s)); \\\n}\n\n\n\n/** \\returns an expression of the coefficient-wise \\< operator of *this and \\a other\n  *\n  * Example: \\include Cwise_less.cpp\n  * Output: \\verbinclude Cwise_less.out\n  *\n  * \\sa all(), any(), operator>(), operator<=()\n  */\nEIGEN_MAKE_CWISE_COMP_OP(operator<, LT)\n\n/** \\returns an expression of the coefficient-wise \\<= operator of *this and \\a other\n  *\n  * Example: \\include Cwise_less_equal.cpp\n  * Output: \\verbinclude Cwise_less_equal.out\n  *\n  * \\sa all(), any(), operator>=(), operator<()\n  */\nEIGEN_MAKE_CWISE_COMP_OP(operator<=, LE)\n\n/** \\returns an expression of the coefficient-wise \\> operator of *this and \\a other\n  *\n  * Example: \\include Cwise_greater.cpp\n  * Output: \\verbinclude Cwise_greater.out\n  *\n  * \\sa all(), any(), operator>=(), operator<()\n  */\nEIGEN_MAKE_CWISE_COMP_R_OP(operator>, operator<, LT)\n\n/** \\returns an expression of the coefficient-wise \\>= operator of *this and \\a other\n  *\n  * Example: \\include Cwise_greater_equal.cpp\n  * Output: \\verbinclude Cwise_greater_equal.out\n  *\n  * \\sa all(), any(), operator>(), operator<=()\n  */\nEIGEN_MAKE_CWISE_COMP_R_OP(operator>=, operator<=, LE)\n\n/** \\returns an expression of the coefficient-wise == operator of *this and \\a other\n  *\n  * \\warning this performs an exact comparison, which is generally a bad idea with floating-point types.\n  * In order to check for equality between two vectors or matrices with floating-point coefficients, it is\n  * generally a far better idea to use a fuzzy comparison as provided by isApprox() and\n  * isMuchSmallerThan().\n  *\n  * Example: \\include Cwise_equal_equal.cpp\n  * Output: \\verbinclude Cwise_equal_equal.out\n  *\n  * \\sa all(), any(), isApprox(), isMuchSmallerThan()\n  */\nEIGEN_MAKE_CWISE_COMP_OP(operator==, EQ)\n\n/** \\returns an expression of the coefficient-wise != operator of *this and \\a other\n  *\n  * \\warning this performs an exact comparison, which is generally a bad idea with floating-point types.\n  * In order to check for equality between two vectors or matrices with floating-point coefficients, it is\n  * generally a far better idea to use a fuzzy comparison as provided by isApprox() and\n  * isMuchSmallerThan().\n  *\n  * Example: \\include Cwise_not_equal.cpp\n  * Output: \\verbinclude Cwise_not_equal.out\n  *\n  * \\sa all(), any(), isApprox(), isMuchSmallerThan()\n  */\nEIGEN_MAKE_CWISE_COMP_OP(operator!=, NEQ)\n\n\n#undef EIGEN_MAKE_CWISE_COMP_OP\n#undef EIGEN_MAKE_CWISE_COMP_R_OP\n\n// scalar addition\n#ifndef EIGEN_PARSED_BY_DOXYGEN\nEIGEN_MAKE_SCALAR_BINARY_OP(operator+,sum)\n#else\n/** \\returns an expression of \\c *this with each coeff incremented by the constant \\a scalar\n  *\n  * \\tparam T is the scalar type of \\a scalar. It must be compatible with the scalar type of the given expression.\n  *\n  * Example: \\include Cwise_plus.cpp\n  * Output: \\verbinclude Cwise_plus.out\n  *\n  * \\sa operator+=(), operator-()\n  */\ntemplate<typename T>\nconst CwiseBinaryOp<internal::scalar_sum_op<Scalar,T>,Derived,Constant<T> > operator+(const T& scalar) const;\n/** \\returns an expression of \\a expr with each coeff incremented by the constant \\a scalar\n  *\n  * \\tparam T is the scalar type of \\a scalar. It must be compatible with the scalar type of the given expression.\n  */\ntemplate<typename T> friend\nconst CwiseBinaryOp<internal::scalar_sum_op<T,Scalar>,Constant<T>,Derived> operator+(const T& scalar, const StorageBaseType& expr);\n#endif\n\n#ifndef EIGEN_PARSED_BY_DOXYGEN\nEIGEN_MAKE_SCALAR_BINARY_OP(operator-,difference)\n#else\n/** \\returns an expression of \\c *this with each coeff decremented by the constant \\a scalar\n  *\n  * \\tparam T is the scalar type of \\a scalar. It must be compatible with the scalar type of the given expression.\n  *\n  * Example: \\include Cwise_minus.cpp\n  * Output: \\verbinclude Cwise_minus.out\n  *\n  * \\sa operator+=(), operator-()\n  */\ntemplate<typename T>\nconst CwiseBinaryOp<internal::scalar_difference_op<Scalar,T>,Derived,Constant<T> > operator-(const T& scalar) const;\n/** \\returns an expression of the constant matrix of value \\a scalar decremented by the coefficients of \\a expr\n  *\n  * \\tparam T is the scalar type of \\a scalar. It must be compatible with the scalar type of the given expression.\n  */\ntemplate<typename T> friend\nconst CwiseBinaryOp<internal::scalar_difference_op<T,Scalar>,Constant<T>,Derived> operator-(const T& scalar, const StorageBaseType& expr);\n#endif\n\n\n#ifndef EIGEN_PARSED_BY_DOXYGEN\n  EIGEN_MAKE_SCALAR_BINARY_OP_ONTHELEFT(operator/,quotient)\n#else\n  /**\n    * \\brief Component-wise division of the scalar \\a s by array elements of \\a a.\n    *\n    * \\tparam Scalar is the scalar type of \\a x. It must be compatible with the scalar type of the given array expression (\\c Derived::Scalar).\n    */\n  template<typename T> friend\n  inline const CwiseBinaryOp<internal::scalar_quotient_op<T,Scalar>,Constant<T>,Derived>\n  operator/(const T& s,const StorageBaseType& a);\n#endif\n\n/** \\returns an expression of the coefficient-wise ^ operator of *this and \\a other\n *\n * \\warning this operator is for expression of bool only.\n *\n * Example: \\include Cwise_boolean_xor.cpp\n * Output: \\verbinclude Cwise_boolean_xor.out\n *\n * \\sa operator&&(), select()\n */\ntemplate<typename OtherDerived>\nEIGEN_DEVICE_FUNC\ninline const CwiseBinaryOp<internal::scalar_boolean_xor_op, const Derived, const OtherDerived>\noperator^(const EIGEN_CURRENT_STORAGE_BASE_CLASS<OtherDerived> &other) const\n{\n  EIGEN_STATIC_ASSERT((internal::is_same<bool,Scalar>::value && internal::is_same<bool,typename OtherDerived::Scalar>::value),\n                      THIS_METHOD_IS_ONLY_FOR_EXPRESSIONS_OF_BOOL);\n  return CwiseBinaryOp<internal::scalar_boolean_xor_op, const Derived, const OtherDerived>(derived(),other.derived());\n}\n\n// NOTE disabled until we agree on argument order\n#if 0\n/** \\cpp11 \\returns an expression of the coefficient-wise polygamma function.\n  *\n  * \\specialfunctions_module\n  *\n  * It returns the \\a n -th derivative of the digamma(psi) evaluated at \\c *this.\n  *\n  * \\warning Be careful with the order of the parameters: x.polygamma(n) is equivalent to polygamma(n,x)\n  *\n  * \\sa Eigen::polygamma()\n  */\ntemplate<typename DerivedN>\ninline const CwiseBinaryOp<internal::scalar_polygamma_op<Scalar>, const DerivedN, const Derived>\npolygamma(const EIGEN_CURRENT_STORAGE_BASE_CLASS<DerivedN> &n) const\n{\n  return CwiseBinaryOp<internal::scalar_polygamma_op<Scalar>, const DerivedN, const Derived>(n.derived(), this->derived());\n}\n#endif\n\n/** \\returns an expression of the coefficient-wise zeta function.\n  *\n  * \\specialfunctions_module\n  *\n  * It returns the Riemann zeta function of two arguments \\c *this and \\a q:\n  *\n  * \\param *this is the exposent, it must be > 1\n  * \\param q is the shift, it must be > 0\n  *\n  * \\note This function supports only float and double scalar types. To support other scalar types, the user has\n  * to provide implementations of zeta(T,T) for any scalar type T to be supported.\n  *\n  * This method is an alias for zeta(*this,q);\n  *\n  * \\sa Eigen::zeta()\n  */\ntemplate<typename DerivedQ>\ninline const CwiseBinaryOp<internal::scalar_zeta_op<Scalar>, const Derived, const DerivedQ>\nzeta(const EIGEN_CURRENT_STORAGE_BASE_CLASS<DerivedQ> &q) const\n{\n  return CwiseBinaryOp<internal::scalar_zeta_op<Scalar>, const Derived, const DerivedQ>(this->derived(), q.derived());\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/plugins/ArrayCwiseUnaryOps.h",
    "content": "\n\ntypedef CwiseUnaryOp<internal::scalar_abs_op<Scalar>, const Derived> AbsReturnType;\ntypedef CwiseUnaryOp<internal::scalar_arg_op<Scalar>, const Derived> ArgReturnType;\ntypedef CwiseUnaryOp<internal::scalar_abs2_op<Scalar>, const Derived> Abs2ReturnType;\ntypedef CwiseUnaryOp<internal::scalar_sqrt_op<Scalar>, const Derived> SqrtReturnType;\ntypedef CwiseUnaryOp<internal::scalar_rsqrt_op<Scalar>, const Derived> RsqrtReturnType;\ntypedef CwiseUnaryOp<internal::scalar_sign_op<Scalar>, const Derived> SignReturnType;\ntypedef CwiseUnaryOp<internal::scalar_inverse_op<Scalar>, const Derived> InverseReturnType;\ntypedef CwiseUnaryOp<internal::scalar_boolean_not_op<Scalar>, const Derived> BooleanNotReturnType;\n\ntypedef CwiseUnaryOp<internal::scalar_exp_op<Scalar>, const Derived> ExpReturnType;\ntypedef CwiseUnaryOp<internal::scalar_log_op<Scalar>, const Derived> LogReturnType;\ntypedef CwiseUnaryOp<internal::scalar_log1p_op<Scalar>, const Derived> Log1pReturnType;\ntypedef CwiseUnaryOp<internal::scalar_log10_op<Scalar>, const Derived> Log10ReturnType;\ntypedef CwiseUnaryOp<internal::scalar_cos_op<Scalar>, const Derived> CosReturnType;\ntypedef CwiseUnaryOp<internal::scalar_sin_op<Scalar>, const Derived> SinReturnType;\ntypedef CwiseUnaryOp<internal::scalar_tan_op<Scalar>, const Derived> TanReturnType;\ntypedef CwiseUnaryOp<internal::scalar_acos_op<Scalar>, const Derived> AcosReturnType;\ntypedef CwiseUnaryOp<internal::scalar_asin_op<Scalar>, const Derived> AsinReturnType;\ntypedef CwiseUnaryOp<internal::scalar_atan_op<Scalar>, const Derived> AtanReturnType;\ntypedef CwiseUnaryOp<internal::scalar_tanh_op<Scalar>, const Derived> TanhReturnType;\ntypedef CwiseUnaryOp<internal::scalar_sinh_op<Scalar>, const Derived> SinhReturnType;\ntypedef CwiseUnaryOp<internal::scalar_cosh_op<Scalar>, const Derived> CoshReturnType;\ntypedef CwiseUnaryOp<internal::scalar_square_op<Scalar>, const Derived> SquareReturnType;\ntypedef CwiseUnaryOp<internal::scalar_cube_op<Scalar>, const Derived> CubeReturnType;\ntypedef CwiseUnaryOp<internal::scalar_round_op<Scalar>, const Derived> RoundReturnType;\ntypedef CwiseUnaryOp<internal::scalar_floor_op<Scalar>, const Derived> FloorReturnType;\ntypedef CwiseUnaryOp<internal::scalar_ceil_op<Scalar>, const Derived> CeilReturnType;\ntypedef CwiseUnaryOp<internal::scalar_isnan_op<Scalar>, const Derived> IsNaNReturnType;\ntypedef CwiseUnaryOp<internal::scalar_isinf_op<Scalar>, const Derived> IsInfReturnType;\ntypedef CwiseUnaryOp<internal::scalar_isfinite_op<Scalar>, const Derived> IsFiniteReturnType;\n\n/** \\returns an expression of the coefficient-wise absolute value of \\c *this\n  *\n  * Example: \\include Cwise_abs.cpp\n  * Output: \\verbinclude Cwise_abs.out\n  *\n  * \\sa <a href=\"group__CoeffwiseMathFunctions.html#cwisetable_abs\">Math functions</a>, abs2()\n  */\nEIGEN_DEVICE_FUNC\nEIGEN_STRONG_INLINE const AbsReturnType\nabs() const\n{\n  return AbsReturnType(derived());\n}\n\n/** \\returns an expression of the coefficient-wise phase angle of \\c *this\n  *\n  * Example: \\include Cwise_arg.cpp\n  * Output: \\verbinclude Cwise_arg.out\n  *\n  * \\sa abs()\n  */\nEIGEN_DEVICE_FUNC\nEIGEN_STRONG_INLINE const ArgReturnType\narg() const\n{\n  return ArgReturnType(derived());\n}\n\n/** \\returns an expression of the coefficient-wise squared absolute value of \\c *this\n  *\n  * Example: \\include Cwise_abs2.cpp\n  * Output: \\verbinclude Cwise_abs2.out\n  *\n  * \\sa <a href=\"group__CoeffwiseMathFunctions.html#cwisetable_abs2\">Math functions</a>, abs(), square()\n  */\nEIGEN_DEVICE_FUNC\nEIGEN_STRONG_INLINE const Abs2ReturnType\nabs2() const\n{\n  return Abs2ReturnType(derived());\n}\n\n/** \\returns an expression of the coefficient-wise exponential of *this.\n  *\n  * This function computes the coefficient-wise exponential. The function MatrixBase::exp() in the\n  * unsupported module MatrixFunctions computes the matrix exponential.\n  *\n  * Example: \\include Cwise_exp.cpp\n  * Output: \\verbinclude Cwise_exp.out\n  *\n  * \\sa <a href=\"group__CoeffwiseMathFunctions.html#cwisetable_exp\">Math functions</a>, pow(), log(), sin(), cos()\n  */\nEIGEN_DEVICE_FUNC\ninline const ExpReturnType\nexp() const\n{\n  return ExpReturnType(derived());\n}\n\n/** \\returns an expression of the coefficient-wise logarithm of *this.\n  *\n  * This function computes the coefficient-wise logarithm. The function MatrixBase::log() in the\n  * unsupported module MatrixFunctions computes the matrix logarithm.\n  *\n  * Example: \\include Cwise_log.cpp\n  * Output: \\verbinclude Cwise_log.out\n  *\n  * \\sa <a href=\"group__CoeffwiseMathFunctions.html#cwisetable_log\">Math functions</a>, exp()\n  */\nEIGEN_DEVICE_FUNC\ninline const LogReturnType\nlog() const\n{\n  return LogReturnType(derived());\n}\n\n/** \\returns an expression of the coefficient-wise logarithm of 1 plus \\c *this.\n  *\n  * In exact arithmetic, \\c x.log() is equivalent to \\c (x+1).log(),\n  * however, with finite precision, this function is much more accurate when \\c x is close to zero.\n  *\n  * \\sa <a href=\"group__CoeffwiseMathFunctions.html#cwisetable_log1p\">Math functions</a>, log()\n  */\nEIGEN_DEVICE_FUNC\ninline const Log1pReturnType\nlog1p() const\n{\n  return Log1pReturnType(derived());\n}\n\n/** \\returns an expression of the coefficient-wise base-10 logarithm of *this.\n  *\n  * This function computes the coefficient-wise base-10 logarithm.\n  *\n  * Example: \\include Cwise_log10.cpp\n  * Output: \\verbinclude Cwise_log10.out\n  *\n  * \\sa <a href=\"group__CoeffwiseMathFunctions.html#cwisetable_log10\">Math functions</a>, log()\n  */\nEIGEN_DEVICE_FUNC\ninline const Log10ReturnType\nlog10() const\n{\n  return Log10ReturnType(derived());\n}\n\n/** \\returns an expression of the coefficient-wise square root of *this.\n  *\n  * This function computes the coefficient-wise square root. The function MatrixBase::sqrt() in the\n  * unsupported module MatrixFunctions computes the matrix square root.\n  *\n  * Example: \\include Cwise_sqrt.cpp\n  * Output: \\verbinclude Cwise_sqrt.out\n  *\n  * \\sa <a href=\"group__CoeffwiseMathFunctions.html#cwisetable_sqrt\">Math functions</a>, pow(), square()\n  */\nEIGEN_DEVICE_FUNC\ninline const SqrtReturnType\nsqrt() const\n{\n  return SqrtReturnType(derived());\n}\n\n/** \\returns an expression of the coefficient-wise inverse square root of *this.\n  *\n  * This function computes the coefficient-wise inverse square root.\n  *\n  * Example: \\include Cwise_sqrt.cpp\n  * Output: \\verbinclude Cwise_sqrt.out\n  *\n  * \\sa pow(), square()\n  */\nEIGEN_DEVICE_FUNC\ninline const RsqrtReturnType\nrsqrt() const\n{\n  return RsqrtReturnType(derived());\n}\n\n/** \\returns an expression of the coefficient-wise signum of *this.\n  *\n  * This function computes the coefficient-wise signum.\n  *\n  * Example: \\include Cwise_sign.cpp\n  * Output: \\verbinclude Cwise_sign.out\n  *\n  * \\sa pow(), square()\n  */\nEIGEN_DEVICE_FUNC\ninline const SignReturnType\nsign() const\n{\n  return SignReturnType(derived());\n}\n\n\n/** \\returns an expression of the coefficient-wise cosine of *this.\n  *\n  * This function computes the coefficient-wise cosine. The function MatrixBase::cos() in the\n  * unsupported module MatrixFunctions computes the matrix cosine.\n  *\n  * Example: \\include Cwise_cos.cpp\n  * Output: \\verbinclude Cwise_cos.out\n  *\n  * \\sa <a href=\"group__CoeffwiseMathFunctions.html#cwisetable_cos\">Math functions</a>, sin(), acos()\n  */\nEIGEN_DEVICE_FUNC\ninline const CosReturnType\ncos() const\n{\n  return CosReturnType(derived());\n}\n\n\n/** \\returns an expression of the coefficient-wise sine of *this.\n  *\n  * This function computes the coefficient-wise sine. The function MatrixBase::sin() in the\n  * unsupported module MatrixFunctions computes the matrix sine.\n  *\n  * Example: \\include Cwise_sin.cpp\n  * Output: \\verbinclude Cwise_sin.out\n  *\n  * \\sa <a href=\"group__CoeffwiseMathFunctions.html#cwisetable_sin\">Math functions</a>, cos(), asin()\n  */\nEIGEN_DEVICE_FUNC\ninline const SinReturnType\nsin() const\n{\n  return SinReturnType(derived());\n}\n\n/** \\returns an expression of the coefficient-wise tan of *this.\n  *\n  * Example: \\include Cwise_tan.cpp\n  * Output: \\verbinclude Cwise_tan.out\n  *\n  * \\sa <a href=\"group__CoeffwiseMathFunctions.html#cwisetable_tan\">Math functions</a>, cos(), sin()\n  */\nEIGEN_DEVICE_FUNC\ninline const TanReturnType\ntan() const\n{\n  return TanReturnType(derived());\n}\n\n/** \\returns an expression of the coefficient-wise arc tan of *this.\n  *\n  * Example: \\include Cwise_atan.cpp\n  * Output: \\verbinclude Cwise_atan.out\n  *\n  * \\sa <a href=\"group__CoeffwiseMathFunctions.html#cwisetable_atan\">Math functions</a>, tan(), asin(), acos()\n  */\nEIGEN_DEVICE_FUNC\ninline const AtanReturnType\natan() const\n{\n  return AtanReturnType(derived());\n}\n\n/** \\returns an expression of the coefficient-wise arc cosine of *this.\n  *\n  * Example: \\include Cwise_acos.cpp\n  * Output: \\verbinclude Cwise_acos.out\n  *\n  * \\sa <a href=\"group__CoeffwiseMathFunctions.html#cwisetable_acos\">Math functions</a>, cos(), asin()\n  */\nEIGEN_DEVICE_FUNC\ninline const AcosReturnType\nacos() const\n{\n  return AcosReturnType(derived());\n}\n\n/** \\returns an expression of the coefficient-wise arc sine of *this.\n  *\n  * Example: \\include Cwise_asin.cpp\n  * Output: \\verbinclude Cwise_asin.out\n  *\n  * \\sa <a href=\"group__CoeffwiseMathFunctions.html#cwisetable_asin\">Math functions</a>, sin(), acos()\n  */\nEIGEN_DEVICE_FUNC\ninline const AsinReturnType\nasin() const\n{\n  return AsinReturnType(derived());\n}\n\n/** \\returns an expression of the coefficient-wise hyperbolic tan of *this.\n  *\n  * Example: \\include Cwise_tanh.cpp\n  * Output: \\verbinclude Cwise_tanh.out\n  *\n  * \\sa <a href=\"group__CoeffwiseMathFunctions.html#cwisetable_tanh\">Math functions</a>, tan(), sinh(), cosh()\n  */\nEIGEN_DEVICE_FUNC\ninline const TanhReturnType\ntanh() const\n{\n  return TanhReturnType(derived());\n}\n\n/** \\returns an expression of the coefficient-wise hyperbolic sin of *this.\n  *\n  * Example: \\include Cwise_sinh.cpp\n  * Output: \\verbinclude Cwise_sinh.out\n  *\n  * \\sa <a href=\"group__CoeffwiseMathFunctions.html#cwisetable_sinh\">Math functions</a>, sin(), tanh(), cosh()\n  */\nEIGEN_DEVICE_FUNC\ninline const SinhReturnType\nsinh() const\n{\n  return SinhReturnType(derived());\n}\n\n/** \\returns an expression of the coefficient-wise hyperbolic cos of *this.\n  *\n  * Example: \\include Cwise_cosh.cpp\n  * Output: \\verbinclude Cwise_cosh.out\n  *\n  * \\sa <a href=\"group__CoeffwiseMathFunctions.html#cwisetable_cosh\">Math functions</a>, tan(), sinh(), cosh()\n  */\nEIGEN_DEVICE_FUNC\ninline const CoshReturnType\ncosh() const\n{\n  return CoshReturnType(derived());\n}\n\n/** \\returns an expression of the coefficient-wise inverse of *this.\n  *\n  * Example: \\include Cwise_inverse.cpp\n  * Output: \\verbinclude Cwise_inverse.out\n  *\n  * \\sa operator/(), operator*()\n  */\nEIGEN_DEVICE_FUNC\ninline const InverseReturnType\ninverse() const\n{\n  return InverseReturnType(derived());\n}\n\n/** \\returns an expression of the coefficient-wise square of *this.\n  *\n  * Example: \\include Cwise_square.cpp\n  * Output: \\verbinclude Cwise_square.out\n  *\n  * \\sa <a href=\"group__CoeffwiseMathFunctions.html#cwisetable_squareE\">Math functions</a>, abs2(), cube(), pow()\n  */\nEIGEN_DEVICE_FUNC\ninline const SquareReturnType\nsquare() const\n{\n  return SquareReturnType(derived());\n}\n\n/** \\returns an expression of the coefficient-wise cube of *this.\n  *\n  * Example: \\include Cwise_cube.cpp\n  * Output: \\verbinclude Cwise_cube.out\n  *\n  * \\sa <a href=\"group__CoeffwiseMathFunctions.html#cwisetable_cube\">Math functions</a>, square(), pow()\n  */\nEIGEN_DEVICE_FUNC\ninline const CubeReturnType\ncube() const\n{\n  return CubeReturnType(derived());\n}\n\n/** \\returns an expression of the coefficient-wise round of *this.\n  *\n  * Example: \\include Cwise_round.cpp\n  * Output: \\verbinclude Cwise_round.out\n  *\n  * \\sa <a href=\"group__CoeffwiseMathFunctions.html#cwisetable_round\">Math functions</a>, ceil(), floor()\n  */\nEIGEN_DEVICE_FUNC\ninline const RoundReturnType\nround() const\n{\n  return RoundReturnType(derived());\n}\n\n/** \\returns an expression of the coefficient-wise floor of *this.\n  *\n  * Example: \\include Cwise_floor.cpp\n  * Output: \\verbinclude Cwise_floor.out\n  *\n  * \\sa <a href=\"group__CoeffwiseMathFunctions.html#cwisetable_floor\">Math functions</a>, ceil(), round()\n  */\nEIGEN_DEVICE_FUNC\ninline const FloorReturnType\nfloor() const\n{\n  return FloorReturnType(derived());\n}\n\n/** \\returns an expression of the coefficient-wise ceil of *this.\n  *\n  * Example: \\include Cwise_ceil.cpp\n  * Output: \\verbinclude Cwise_ceil.out\n  *\n  * \\sa <a href=\"group__CoeffwiseMathFunctions.html#cwisetable_ceil\">Math functions</a>, floor(), round()\n  */\nEIGEN_DEVICE_FUNC\ninline const CeilReturnType\nceil() const\n{\n  return CeilReturnType(derived());\n}\n\n/** \\returns an expression of the coefficient-wise isnan of *this.\n  *\n  * Example: \\include Cwise_isNaN.cpp\n  * Output: \\verbinclude Cwise_isNaN.out\n  *\n  * \\sa isfinite(), isinf()\n  */\nEIGEN_DEVICE_FUNC\ninline const IsNaNReturnType\nisNaN() const\n{\n  return IsNaNReturnType(derived());\n}\n\n/** \\returns an expression of the coefficient-wise isinf of *this.\n  *\n  * Example: \\include Cwise_isInf.cpp\n  * Output: \\verbinclude Cwise_isInf.out\n  *\n  * \\sa isnan(), isfinite()\n  */\nEIGEN_DEVICE_FUNC\ninline const IsInfReturnType\nisInf() const\n{\n  return IsInfReturnType(derived());\n}\n\n/** \\returns an expression of the coefficient-wise isfinite of *this.\n  *\n  * Example: \\include Cwise_isFinite.cpp\n  * Output: \\verbinclude Cwise_isFinite.out\n  *\n  * \\sa isnan(), isinf()\n  */\nEIGEN_DEVICE_FUNC\ninline const IsFiniteReturnType\nisFinite() const\n{\n  return IsFiniteReturnType(derived());\n}\n\n/** \\returns an expression of the coefficient-wise ! operator of *this\n  *\n  * \\warning this operator is for expression of bool only.\n  *\n  * Example: \\include Cwise_boolean_not.cpp\n  * Output: \\verbinclude Cwise_boolean_not.out\n  *\n  * \\sa operator!=()\n  */\nEIGEN_DEVICE_FUNC\ninline const BooleanNotReturnType\noperator!() const\n{\n  EIGEN_STATIC_ASSERT((internal::is_same<bool,Scalar>::value),\n                      THIS_METHOD_IS_ONLY_FOR_EXPRESSIONS_OF_BOOL);\n  return BooleanNotReturnType(derived());\n}\n\n\n// --- SpecialFunctions module ---\n\ntypedef CwiseUnaryOp<internal::scalar_lgamma_op<Scalar>, const Derived> LgammaReturnType;\ntypedef CwiseUnaryOp<internal::scalar_digamma_op<Scalar>, const Derived> DigammaReturnType;\ntypedef CwiseUnaryOp<internal::scalar_erf_op<Scalar>, const Derived> ErfReturnType;\ntypedef CwiseUnaryOp<internal::scalar_erfc_op<Scalar>, const Derived> ErfcReturnType;\n\n/** \\cpp11 \\returns an expression of the coefficient-wise ln(|gamma(*this)|).\n  *\n  * \\specialfunctions_module\n  *\n  * Example: \\include Cwise_lgamma.cpp\n  * Output: \\verbinclude Cwise_lgamma.out\n  *\n  * \\note This function supports only float and double scalar types in c++11 mode. To support other scalar types,\n  * or float/double in non c++11 mode, the user has to provide implementations of lgamma(T) for any scalar\n  * type T to be supported.\n  *\n  * \\sa <a href=\"group__CoeffwiseMathFunctions.html#cwisetable_lgamma\">Math functions</a>, digamma()\n  */\nEIGEN_DEVICE_FUNC\ninline const LgammaReturnType\nlgamma() const\n{\n  return LgammaReturnType(derived());\n}\n\n/** \\returns an expression of the coefficient-wise digamma (psi, derivative of lgamma).\n  *\n  * \\specialfunctions_module\n  *\n  * \\note This function supports only float and double scalar types. To support other scalar types,\n  * the user has to provide implementations of digamma(T) for any scalar\n  * type T to be supported.\n  *\n  * \\sa <a href=\"group__CoeffwiseMathFunctions.html#cwisetable_digamma\">Math functions</a>, Eigen::digamma(), Eigen::polygamma(), lgamma()\n  */\nEIGEN_DEVICE_FUNC\ninline const DigammaReturnType\ndigamma() const\n{\n  return DigammaReturnType(derived());\n}\n\n/** \\cpp11 \\returns an expression of the coefficient-wise Gauss error\n  * function of *this.\n  *\n  * \\specialfunctions_module\n  *\n  * Example: \\include Cwise_erf.cpp\n  * Output: \\verbinclude Cwise_erf.out\n  *\n  * \\note This function supports only float and double scalar types in c++11 mode. To support other scalar types,\n  * or float/double in non c++11 mode, the user has to provide implementations of erf(T) for any scalar\n  * type T to be supported.\n  *\n  * \\sa <a href=\"group__CoeffwiseMathFunctions.html#cwisetable_erf\">Math functions</a>, erfc()\n  */\nEIGEN_DEVICE_FUNC\ninline const ErfReturnType\nerf() const\n{\n  return ErfReturnType(derived());\n}\n\n/** \\cpp11 \\returns an expression of the coefficient-wise Complementary error\n  * function of *this.\n  *\n  * \\specialfunctions_module\n  *\n  * Example: \\include Cwise_erfc.cpp\n  * Output: \\verbinclude Cwise_erfc.out\n  *\n  * \\note This function supports only float and double scalar types in c++11 mode. To support other scalar types,\n  * or float/double in non c++11 mode, the user has to provide implementations of erfc(T) for any scalar\n  * type T to be supported.\n  *\n  * \\sa <a href=\"group__CoeffwiseMathFunctions.html#cwisetable_erfc\">Math functions</a>, erf()\n  */\nEIGEN_DEVICE_FUNC\ninline const ErfcReturnType\nerfc() const\n{\n  return ErfcReturnType(derived());\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/plugins/BlockMethods.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2010 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2006-2010 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n#ifndef EIGEN_PARSED_BY_DOXYGEN\n\n/// \\internal expression type of a column */\ntypedef Block<Derived, internal::traits<Derived>::RowsAtCompileTime, 1, !IsRowMajor> ColXpr;\ntypedef const Block<const Derived, internal::traits<Derived>::RowsAtCompileTime, 1, !IsRowMajor> ConstColXpr;\n/// \\internal expression type of a row */\ntypedef Block<Derived, 1, internal::traits<Derived>::ColsAtCompileTime, IsRowMajor> RowXpr;\ntypedef const Block<const Derived, 1, internal::traits<Derived>::ColsAtCompileTime, IsRowMajor> ConstRowXpr;\n/// \\internal expression type of a block of whole columns */\ntypedef Block<Derived, internal::traits<Derived>::RowsAtCompileTime, Dynamic, !IsRowMajor> ColsBlockXpr;\ntypedef const Block<const Derived, internal::traits<Derived>::RowsAtCompileTime, Dynamic, !IsRowMajor> ConstColsBlockXpr;\n/// \\internal expression type of a block of whole rows */\ntypedef Block<Derived, Dynamic, internal::traits<Derived>::ColsAtCompileTime, IsRowMajor> RowsBlockXpr;\ntypedef const Block<const Derived, Dynamic, internal::traits<Derived>::ColsAtCompileTime, IsRowMajor> ConstRowsBlockXpr;\n/// \\internal expression type of a block of whole columns */\ntemplate<int N> struct NColsBlockXpr { typedef Block<Derived, internal::traits<Derived>::RowsAtCompileTime, N, !IsRowMajor> Type; };\ntemplate<int N> struct ConstNColsBlockXpr { typedef const Block<const Derived, internal::traits<Derived>::RowsAtCompileTime, N, !IsRowMajor> Type; };\n/// \\internal expression type of a block of whole rows */\ntemplate<int N> struct NRowsBlockXpr { typedef Block<Derived, N, internal::traits<Derived>::ColsAtCompileTime, IsRowMajor> Type; };\ntemplate<int N> struct ConstNRowsBlockXpr { typedef const Block<const Derived, N, internal::traits<Derived>::ColsAtCompileTime, IsRowMajor> Type; };\n/// \\internal expression of a block */\ntypedef Block<Derived> BlockXpr;\ntypedef const Block<const Derived> ConstBlockXpr;\n/// \\internal expression of a block of fixed sizes */\ntemplate<int Rows, int Cols> struct FixedBlockXpr { typedef Block<Derived,Rows,Cols> Type; };\ntemplate<int Rows, int Cols> struct ConstFixedBlockXpr { typedef Block<const Derived,Rows,Cols> Type; };\n\ntypedef VectorBlock<Derived> SegmentReturnType;\ntypedef const VectorBlock<const Derived> ConstSegmentReturnType;\ntemplate<int Size> struct FixedSegmentReturnType { typedef VectorBlock<Derived, Size> Type; };\ntemplate<int Size> struct ConstFixedSegmentReturnType { typedef const VectorBlock<const Derived, Size> Type; };\n\n#endif // not EIGEN_PARSED_BY_DOXYGEN\n\n/// \\returns a dynamic-size expression of a block in *this.\n///\n/// \\param startRow the first row in the block\n/// \\param startCol the first column in the block\n/// \\param blockRows the number of rows in the block\n/// \\param blockCols the number of columns in the block\n///\n/// Example: \\include MatrixBase_block_int_int_int_int.cpp\n/// Output: \\verbinclude MatrixBase_block_int_int_int_int.out\n///\n/// \\note Even though the returned expression has dynamic size, in the case\n/// when it is applied to a fixed-size matrix, it inherits a fixed maximal size,\n/// which means that evaluating it does not cause a dynamic memory allocation.\n///\nEIGEN_DOC_BLOCK_ADDONS_NOT_INNER_PANEL\n///\n/// \\sa class Block, block(Index,Index)\n///\nEIGEN_DEVICE_FUNC\ninline BlockXpr block(Index startRow, Index startCol, Index blockRows, Index blockCols)\n{\n  return BlockXpr(derived(), startRow, startCol, blockRows, blockCols);\n}\n\n/// This is the const version of block(Index,Index,Index,Index). */\nEIGEN_DEVICE_FUNC\ninline const ConstBlockXpr block(Index startRow, Index startCol, Index blockRows, Index blockCols) const\n{\n  return ConstBlockXpr(derived(), startRow, startCol, blockRows, blockCols);\n}\n\n\n\n\n/// \\returns a dynamic-size expression of a top-right corner of *this.\n///\n/// \\param cRows the number of rows in the corner\n/// \\param cCols the number of columns in the corner\n///\n/// Example: \\include MatrixBase_topRightCorner_int_int.cpp\n/// Output: \\verbinclude MatrixBase_topRightCorner_int_int.out\n///\nEIGEN_DOC_BLOCK_ADDONS_NOT_INNER_PANEL\n///\n/// \\sa class Block, block(Index,Index,Index,Index)\n///\nEIGEN_DEVICE_FUNC\ninline BlockXpr topRightCorner(Index cRows, Index cCols)\n{\n  return BlockXpr(derived(), 0, cols() - cCols, cRows, cCols);\n}\n\n/// This is the const version of topRightCorner(Index, Index).\nEIGEN_DEVICE_FUNC\ninline const ConstBlockXpr topRightCorner(Index cRows, Index cCols) const\n{\n  return ConstBlockXpr(derived(), 0, cols() - cCols, cRows, cCols);\n}\n\n/// \\returns an expression of a fixed-size top-right corner of *this.\n///\n/// \\tparam CRows the number of rows in the corner\n/// \\tparam CCols the number of columns in the corner\n///\n/// Example: \\include MatrixBase_template_int_int_topRightCorner.cpp\n/// Output: \\verbinclude MatrixBase_template_int_int_topRightCorner.out\n///\nEIGEN_DOC_BLOCK_ADDONS_NOT_INNER_PANEL\n///\n/// \\sa class Block, block<int,int>(Index,Index)\n///\ntemplate<int CRows, int CCols>\nEIGEN_DEVICE_FUNC\ninline typename FixedBlockXpr<CRows,CCols>::Type topRightCorner()\n{\n  return typename FixedBlockXpr<CRows,CCols>::Type(derived(), 0, cols() - CCols);\n}\n\n/// This is the const version of topRightCorner<int, int>().\ntemplate<int CRows, int CCols>\nEIGEN_DEVICE_FUNC\ninline const typename ConstFixedBlockXpr<CRows,CCols>::Type topRightCorner() const\n{\n  return typename ConstFixedBlockXpr<CRows,CCols>::Type(derived(), 0, cols() - CCols);\n}\n\n/// \\returns an expression of a top-right corner of *this.\n///\n/// \\tparam CRows number of rows in corner as specified at compile-time\n/// \\tparam CCols number of columns in corner as specified at compile-time\n/// \\param  cRows number of rows in corner as specified at run-time\n/// \\param  cCols number of columns in corner as specified at run-time\n///\n/// This function is mainly useful for corners where the number of rows is specified at compile-time\n/// and the number of columns is specified at run-time, or vice versa. The compile-time and run-time\n/// information should not contradict. In other words, \\a cRows should equal \\a CRows unless\n/// \\a CRows is \\a Dynamic, and the same for the number of columns.\n///\n/// Example: \\include MatrixBase_template_int_int_topRightCorner_int_int.cpp\n/// Output: \\verbinclude MatrixBase_template_int_int_topRightCorner_int_int.out\n///\nEIGEN_DOC_BLOCK_ADDONS_NOT_INNER_PANEL\n///\n/// \\sa class Block\n///\ntemplate<int CRows, int CCols>\ninline typename FixedBlockXpr<CRows,CCols>::Type topRightCorner(Index cRows, Index cCols)\n{\n  return typename FixedBlockXpr<CRows,CCols>::Type(derived(), 0, cols() - cCols, cRows, cCols);\n}\n\n/// This is the const version of topRightCorner<int, int>(Index, Index).\ntemplate<int CRows, int CCols>\ninline const typename ConstFixedBlockXpr<CRows,CCols>::Type topRightCorner(Index cRows, Index cCols) const\n{\n  return typename ConstFixedBlockXpr<CRows,CCols>::Type(derived(), 0, cols() - cCols, cRows, cCols);\n}\n\n\n\n/// \\returns a dynamic-size expression of a top-left corner of *this.\n///\n/// \\param cRows the number of rows in the corner\n/// \\param cCols the number of columns in the corner\n///\n/// Example: \\include MatrixBase_topLeftCorner_int_int.cpp\n/// Output: \\verbinclude MatrixBase_topLeftCorner_int_int.out\n///\nEIGEN_DOC_BLOCK_ADDONS_NOT_INNER_PANEL\n///\n/// \\sa class Block, block(Index,Index,Index,Index)\n///\nEIGEN_DEVICE_FUNC\ninline BlockXpr topLeftCorner(Index cRows, Index cCols)\n{\n  return BlockXpr(derived(), 0, 0, cRows, cCols);\n}\n\n/// This is the const version of topLeftCorner(Index, Index).\nEIGEN_DEVICE_FUNC\ninline const ConstBlockXpr topLeftCorner(Index cRows, Index cCols) const\n{\n  return ConstBlockXpr(derived(), 0, 0, cRows, cCols);\n}\n\n/// \\returns an expression of a fixed-size top-left corner of *this.\n///\n/// The template parameters CRows and CCols are the number of rows and columns in the corner.\n///\n/// Example: \\include MatrixBase_template_int_int_topLeftCorner.cpp\n/// Output: \\verbinclude MatrixBase_template_int_int_topLeftCorner.out\n///\nEIGEN_DOC_BLOCK_ADDONS_NOT_INNER_PANEL\n///\n/// \\sa class Block, block(Index,Index,Index,Index)\n///\ntemplate<int CRows, int CCols>\nEIGEN_DEVICE_FUNC\ninline typename FixedBlockXpr<CRows,CCols>::Type topLeftCorner()\n{\n  return typename FixedBlockXpr<CRows,CCols>::Type(derived(), 0, 0);\n}\n\n/// This is the const version of topLeftCorner<int, int>().\ntemplate<int CRows, int CCols>\nEIGEN_DEVICE_FUNC\ninline const typename ConstFixedBlockXpr<CRows,CCols>::Type topLeftCorner() const\n{\n  return typename ConstFixedBlockXpr<CRows,CCols>::Type(derived(), 0, 0);\n}\n\n/// \\returns an expression of a top-left corner of *this.\n///\n/// \\tparam CRows number of rows in corner as specified at compile-time\n/// \\tparam CCols number of columns in corner as specified at compile-time\n/// \\param  cRows number of rows in corner as specified at run-time\n/// \\param  cCols number of columns in corner as specified at run-time\n///\n/// This function is mainly useful for corners where the number of rows is specified at compile-time\n/// and the number of columns is specified at run-time, or vice versa. The compile-time and run-time\n/// information should not contradict. In other words, \\a cRows should equal \\a CRows unless\n/// \\a CRows is \\a Dynamic, and the same for the number of columns.\n///\n/// Example: \\include MatrixBase_template_int_int_topLeftCorner_int_int.cpp\n/// Output: \\verbinclude MatrixBase_template_int_int_topLeftCorner_int_int.out\n///\nEIGEN_DOC_BLOCK_ADDONS_NOT_INNER_PANEL\n///\n/// \\sa class Block\n///\ntemplate<int CRows, int CCols>\ninline typename FixedBlockXpr<CRows,CCols>::Type topLeftCorner(Index cRows, Index cCols)\n{\n  return typename FixedBlockXpr<CRows,CCols>::Type(derived(), 0, 0, cRows, cCols);\n}\n\n/// This is the const version of topLeftCorner<int, int>(Index, Index).\ntemplate<int CRows, int CCols>\ninline const typename ConstFixedBlockXpr<CRows,CCols>::Type topLeftCorner(Index cRows, Index cCols) const\n{\n  return typename ConstFixedBlockXpr<CRows,CCols>::Type(derived(), 0, 0, cRows, cCols);\n}\n\n\n\n/// \\returns a dynamic-size expression of a bottom-right corner of *this.\n///\n/// \\param cRows the number of rows in the corner\n/// \\param cCols the number of columns in the corner\n///\n/// Example: \\include MatrixBase_bottomRightCorner_int_int.cpp\n/// Output: \\verbinclude MatrixBase_bottomRightCorner_int_int.out\n///\nEIGEN_DOC_BLOCK_ADDONS_NOT_INNER_PANEL\n///\n/// \\sa class Block, block(Index,Index,Index,Index)\n///\nEIGEN_DEVICE_FUNC\ninline BlockXpr bottomRightCorner(Index cRows, Index cCols)\n{\n  return BlockXpr(derived(), rows() - cRows, cols() - cCols, cRows, cCols);\n}\n\n/// This is the const version of bottomRightCorner(Index, Index).\nEIGEN_DEVICE_FUNC\ninline const ConstBlockXpr bottomRightCorner(Index cRows, Index cCols) const\n{\n  return ConstBlockXpr(derived(), rows() - cRows, cols() - cCols, cRows, cCols);\n}\n\n/// \\returns an expression of a fixed-size bottom-right corner of *this.\n///\n/// The template parameters CRows and CCols are the number of rows and columns in the corner.\n///\n/// Example: \\include MatrixBase_template_int_int_bottomRightCorner.cpp\n/// Output: \\verbinclude MatrixBase_template_int_int_bottomRightCorner.out\n///\nEIGEN_DOC_BLOCK_ADDONS_NOT_INNER_PANEL\n///\n/// \\sa class Block, block(Index,Index,Index,Index)\n///\ntemplate<int CRows, int CCols>\nEIGEN_DEVICE_FUNC\ninline typename FixedBlockXpr<CRows,CCols>::Type bottomRightCorner()\n{\n  return typename FixedBlockXpr<CRows,CCols>::Type(derived(), rows() - CRows, cols() - CCols);\n}\n\n/// This is the const version of bottomRightCorner<int, int>().\ntemplate<int CRows, int CCols>\nEIGEN_DEVICE_FUNC\ninline const typename ConstFixedBlockXpr<CRows,CCols>::Type bottomRightCorner() const\n{\n  return typename ConstFixedBlockXpr<CRows,CCols>::Type(derived(), rows() - CRows, cols() - CCols);\n}\n\n/// \\returns an expression of a bottom-right corner of *this.\n///\n/// \\tparam CRows number of rows in corner as specified at compile-time\n/// \\tparam CCols number of columns in corner as specified at compile-time\n/// \\param  cRows number of rows in corner as specified at run-time\n/// \\param  cCols number of columns in corner as specified at run-time\n///\n/// This function is mainly useful for corners where the number of rows is specified at compile-time\n/// and the number of columns is specified at run-time, or vice versa. The compile-time and run-time\n/// information should not contradict. In other words, \\a cRows should equal \\a CRows unless\n/// \\a CRows is \\a Dynamic, and the same for the number of columns.\n///\n/// Example: \\include MatrixBase_template_int_int_bottomRightCorner_int_int.cpp\n/// Output: \\verbinclude MatrixBase_template_int_int_bottomRightCorner_int_int.out\n///\nEIGEN_DOC_BLOCK_ADDONS_NOT_INNER_PANEL\n///\n/// \\sa class Block\n///\ntemplate<int CRows, int CCols>\ninline typename FixedBlockXpr<CRows,CCols>::Type bottomRightCorner(Index cRows, Index cCols)\n{\n  return typename FixedBlockXpr<CRows,CCols>::Type(derived(), rows() - cRows, cols() - cCols, cRows, cCols);\n}\n\n/// This is the const version of bottomRightCorner<int, int>(Index, Index).\ntemplate<int CRows, int CCols>\ninline const typename ConstFixedBlockXpr<CRows,CCols>::Type bottomRightCorner(Index cRows, Index cCols) const\n{\n  return typename ConstFixedBlockXpr<CRows,CCols>::Type(derived(), rows() - cRows, cols() - cCols, cRows, cCols);\n}\n\n\n\n/// \\returns a dynamic-size expression of a bottom-left corner of *this.\n///\n/// \\param cRows the number of rows in the corner\n/// \\param cCols the number of columns in the corner\n///\n/// Example: \\include MatrixBase_bottomLeftCorner_int_int.cpp\n/// Output: \\verbinclude MatrixBase_bottomLeftCorner_int_int.out\n///\nEIGEN_DOC_BLOCK_ADDONS_NOT_INNER_PANEL\n///\n/// \\sa class Block, block(Index,Index,Index,Index)\n///\nEIGEN_DEVICE_FUNC\ninline BlockXpr bottomLeftCorner(Index cRows, Index cCols)\n{\n  return BlockXpr(derived(), rows() - cRows, 0, cRows, cCols);\n}\n\n/// This is the const version of bottomLeftCorner(Index, Index).\nEIGEN_DEVICE_FUNC\ninline const ConstBlockXpr bottomLeftCorner(Index cRows, Index cCols) const\n{\n  return ConstBlockXpr(derived(), rows() - cRows, 0, cRows, cCols);\n}\n\n/// \\returns an expression of a fixed-size bottom-left corner of *this.\n///\n/// The template parameters CRows and CCols are the number of rows and columns in the corner.\n///\n/// Example: \\include MatrixBase_template_int_int_bottomLeftCorner.cpp\n/// Output: \\verbinclude MatrixBase_template_int_int_bottomLeftCorner.out\n///\nEIGEN_DOC_BLOCK_ADDONS_NOT_INNER_PANEL\n///\n/// \\sa class Block, block(Index,Index,Index,Index)\n///\ntemplate<int CRows, int CCols>\nEIGEN_DEVICE_FUNC\ninline typename FixedBlockXpr<CRows,CCols>::Type bottomLeftCorner()\n{\n  return typename FixedBlockXpr<CRows,CCols>::Type(derived(), rows() - CRows, 0);\n}\n\n/// This is the const version of bottomLeftCorner<int, int>().\ntemplate<int CRows, int CCols>\nEIGEN_DEVICE_FUNC\ninline const typename ConstFixedBlockXpr<CRows,CCols>::Type bottomLeftCorner() const\n{\n  return typename ConstFixedBlockXpr<CRows,CCols>::Type(derived(), rows() - CRows, 0);\n}\n\n/// \\returns an expression of a bottom-left corner of *this.\n///\n/// \\tparam CRows number of rows in corner as specified at compile-time\n/// \\tparam CCols number of columns in corner as specified at compile-time\n/// \\param  cRows number of rows in corner as specified at run-time\n/// \\param  cCols number of columns in corner as specified at run-time\n///\n/// This function is mainly useful for corners where the number of rows is specified at compile-time\n/// and the number of columns is specified at run-time, or vice versa. The compile-time and run-time\n/// information should not contradict. In other words, \\a cRows should equal \\a CRows unless\n/// \\a CRows is \\a Dynamic, and the same for the number of columns.\n///\n/// Example: \\include MatrixBase_template_int_int_bottomLeftCorner_int_int.cpp\n/// Output: \\verbinclude MatrixBase_template_int_int_bottomLeftCorner_int_int.out\n///\nEIGEN_DOC_BLOCK_ADDONS_NOT_INNER_PANEL\n///\n/// \\sa class Block\n///\ntemplate<int CRows, int CCols>\ninline typename FixedBlockXpr<CRows,CCols>::Type bottomLeftCorner(Index cRows, Index cCols)\n{\n  return typename FixedBlockXpr<CRows,CCols>::Type(derived(), rows() - cRows, 0, cRows, cCols);\n}\n\n/// This is the const version of bottomLeftCorner<int, int>(Index, Index).\ntemplate<int CRows, int CCols>\ninline const typename ConstFixedBlockXpr<CRows,CCols>::Type bottomLeftCorner(Index cRows, Index cCols) const\n{\n  return typename ConstFixedBlockXpr<CRows,CCols>::Type(derived(), rows() - cRows, 0, cRows, cCols);\n}\n\n\n\n/// \\returns a block consisting of the top rows of *this.\n///\n/// \\param n the number of rows in the block\n///\n/// Example: \\include MatrixBase_topRows_int.cpp\n/// Output: \\verbinclude MatrixBase_topRows_int.out\n///\nEIGEN_DOC_BLOCK_ADDONS_INNER_PANEL_IF(row-major)\n///\n/// \\sa class Block, block(Index,Index,Index,Index)\n///\nEIGEN_DEVICE_FUNC\ninline RowsBlockXpr topRows(Index n)\n{\n  return RowsBlockXpr(derived(), 0, 0, n, cols());\n}\n\n/// This is the const version of topRows(Index).\nEIGEN_DEVICE_FUNC\ninline ConstRowsBlockXpr topRows(Index n) const\n{\n  return ConstRowsBlockXpr(derived(), 0, 0, n, cols());\n}\n\n/// \\returns a block consisting of the top rows of *this.\n///\n/// \\tparam N the number of rows in the block as specified at compile-time\n/// \\param n the number of rows in the block as specified at run-time\n///\n/// The compile-time and run-time information should not contradict. In other words,\n/// \\a n should equal \\a N unless \\a N is \\a Dynamic.\n///\n/// Example: \\include MatrixBase_template_int_topRows.cpp\n/// Output: \\verbinclude MatrixBase_template_int_topRows.out\n///\nEIGEN_DOC_BLOCK_ADDONS_INNER_PANEL_IF(row-major)\n///\n/// \\sa class Block, block(Index,Index,Index,Index)\n///\ntemplate<int N>\nEIGEN_DEVICE_FUNC\ninline typename NRowsBlockXpr<N>::Type topRows(Index n = N)\n{\n  return typename NRowsBlockXpr<N>::Type(derived(), 0, 0, n, cols());\n}\n\n/// This is the const version of topRows<int>().\ntemplate<int N>\nEIGEN_DEVICE_FUNC\ninline typename ConstNRowsBlockXpr<N>::Type topRows(Index n = N) const\n{\n  return typename ConstNRowsBlockXpr<N>::Type(derived(), 0, 0, n, cols());\n}\n\n\n\n/// \\returns a block consisting of the bottom rows of *this.\n///\n/// \\param n the number of rows in the block\n///\n/// Example: \\include MatrixBase_bottomRows_int.cpp\n/// Output: \\verbinclude MatrixBase_bottomRows_int.out\n///\nEIGEN_DOC_BLOCK_ADDONS_INNER_PANEL_IF(row-major)\n///\n/// \\sa class Block, block(Index,Index,Index,Index)\n///\nEIGEN_DEVICE_FUNC\ninline RowsBlockXpr bottomRows(Index n)\n{\n  return RowsBlockXpr(derived(), rows() - n, 0, n, cols());\n}\n\n/// This is the const version of bottomRows(Index).\nEIGEN_DEVICE_FUNC\ninline ConstRowsBlockXpr bottomRows(Index n) const\n{\n  return ConstRowsBlockXpr(derived(), rows() - n, 0, n, cols());\n}\n\n/// \\returns a block consisting of the bottom rows of *this.\n///\n/// \\tparam N the number of rows in the block as specified at compile-time\n/// \\param n the number of rows in the block as specified at run-time\n///\n/// The compile-time and run-time information should not contradict. In other words,\n/// \\a n should equal \\a N unless \\a N is \\a Dynamic.\n///\n/// Example: \\include MatrixBase_template_int_bottomRows.cpp\n/// Output: \\verbinclude MatrixBase_template_int_bottomRows.out\n///\nEIGEN_DOC_BLOCK_ADDONS_INNER_PANEL_IF(row-major)\n///\n/// \\sa class Block, block(Index,Index,Index,Index)\n///\ntemplate<int N>\nEIGEN_DEVICE_FUNC\ninline typename NRowsBlockXpr<N>::Type bottomRows(Index n = N)\n{\n  return typename NRowsBlockXpr<N>::Type(derived(), rows() - n, 0, n, cols());\n}\n\n/// This is the const version of bottomRows<int>().\ntemplate<int N>\nEIGEN_DEVICE_FUNC\ninline typename ConstNRowsBlockXpr<N>::Type bottomRows(Index n = N) const\n{\n  return typename ConstNRowsBlockXpr<N>::Type(derived(), rows() - n, 0, n, cols());\n}\n\n\n\n/// \\returns a block consisting of a range of rows of *this.\n///\n/// \\param startRow the index of the first row in the block\n/// \\param n the number of rows in the block\n///\n/// Example: \\include DenseBase_middleRows_int.cpp\n/// Output: \\verbinclude DenseBase_middleRows_int.out\n///\nEIGEN_DOC_BLOCK_ADDONS_INNER_PANEL_IF(row-major)\n///\n/// \\sa class Block, block(Index,Index,Index,Index)\n///\nEIGEN_DEVICE_FUNC\ninline RowsBlockXpr middleRows(Index startRow, Index n)\n{\n  return RowsBlockXpr(derived(), startRow, 0, n, cols());\n}\n\n/// This is the const version of middleRows(Index,Index).\nEIGEN_DEVICE_FUNC\ninline ConstRowsBlockXpr middleRows(Index startRow, Index n) const\n{\n  return ConstRowsBlockXpr(derived(), startRow, 0, n, cols());\n}\n\n/// \\returns a block consisting of a range of rows of *this.\n///\n/// \\tparam N the number of rows in the block as specified at compile-time\n/// \\param startRow the index of the first row in the block\n/// \\param n the number of rows in the block as specified at run-time\n///\n/// The compile-time and run-time information should not contradict. In other words,\n/// \\a n should equal \\a N unless \\a N is \\a Dynamic.\n///\n/// Example: \\include DenseBase_template_int_middleRows.cpp\n/// Output: \\verbinclude DenseBase_template_int_middleRows.out\n///\nEIGEN_DOC_BLOCK_ADDONS_INNER_PANEL_IF(row-major)\n///\n/// \\sa class Block, block(Index,Index,Index,Index)\n///\ntemplate<int N>\nEIGEN_DEVICE_FUNC\ninline typename NRowsBlockXpr<N>::Type middleRows(Index startRow, Index n = N)\n{\n  return typename NRowsBlockXpr<N>::Type(derived(), startRow, 0, n, cols());\n}\n\n/// This is the const version of middleRows<int>().\ntemplate<int N>\nEIGEN_DEVICE_FUNC\ninline typename ConstNRowsBlockXpr<N>::Type middleRows(Index startRow, Index n = N) const\n{\n  return typename ConstNRowsBlockXpr<N>::Type(derived(), startRow, 0, n, cols());\n}\n\n\n\n/// \\returns a block consisting of the left columns of *this.\n///\n/// \\param n the number of columns in the block\n///\n/// Example: \\include MatrixBase_leftCols_int.cpp\n/// Output: \\verbinclude MatrixBase_leftCols_int.out\n///\nEIGEN_DOC_BLOCK_ADDONS_INNER_PANEL_IF(column-major)\n///\n/// \\sa class Block, block(Index,Index,Index,Index)\n///\nEIGEN_DEVICE_FUNC\ninline ColsBlockXpr leftCols(Index n)\n{\n  return ColsBlockXpr(derived(), 0, 0, rows(), n);\n}\n\n/// This is the const version of leftCols(Index).\nEIGEN_DEVICE_FUNC\ninline ConstColsBlockXpr leftCols(Index n) const\n{\n  return ConstColsBlockXpr(derived(), 0, 0, rows(), n);\n}\n\n/// \\returns a block consisting of the left columns of *this.\n///\n/// \\tparam N the number of columns in the block as specified at compile-time\n/// \\param n the number of columns in the block as specified at run-time\n///\n/// The compile-time and run-time information should not contradict. In other words,\n/// \\a n should equal \\a N unless \\a N is \\a Dynamic.\n///\n/// Example: \\include MatrixBase_template_int_leftCols.cpp\n/// Output: \\verbinclude MatrixBase_template_int_leftCols.out\n///\nEIGEN_DOC_BLOCK_ADDONS_INNER_PANEL_IF(column-major)\n///\n/// \\sa class Block, block(Index,Index,Index,Index)\n///\ntemplate<int N>\nEIGEN_DEVICE_FUNC\ninline typename NColsBlockXpr<N>::Type leftCols(Index n = N)\n{\n  return typename NColsBlockXpr<N>::Type(derived(), 0, 0, rows(), n);\n}\n\n/// This is the const version of leftCols<int>().\ntemplate<int N>\nEIGEN_DEVICE_FUNC\ninline typename ConstNColsBlockXpr<N>::Type leftCols(Index n = N) const\n{\n  return typename ConstNColsBlockXpr<N>::Type(derived(), 0, 0, rows(), n);\n}\n\n\n\n/// \\returns a block consisting of the right columns of *this.\n///\n/// \\param n the number of columns in the block\n///\n/// Example: \\include MatrixBase_rightCols_int.cpp\n/// Output: \\verbinclude MatrixBase_rightCols_int.out\n///\nEIGEN_DOC_BLOCK_ADDONS_INNER_PANEL_IF(column-major)\n///\n/// \\sa class Block, block(Index,Index,Index,Index)\n///\nEIGEN_DEVICE_FUNC\ninline ColsBlockXpr rightCols(Index n)\n{\n  return ColsBlockXpr(derived(), 0, cols() - n, rows(), n);\n}\n\n/// This is the const version of rightCols(Index).\nEIGEN_DEVICE_FUNC\ninline ConstColsBlockXpr rightCols(Index n) const\n{\n  return ConstColsBlockXpr(derived(), 0, cols() - n, rows(), n);\n}\n\n/// \\returns a block consisting of the right columns of *this.\n///\n/// \\tparam N the number of columns in the block as specified at compile-time\n/// \\param n the number of columns in the block as specified at run-time\n///\n/// The compile-time and run-time information should not contradict. In other words,\n/// \\a n should equal \\a N unless \\a N is \\a Dynamic.\n///\n/// Example: \\include MatrixBase_template_int_rightCols.cpp\n/// Output: \\verbinclude MatrixBase_template_int_rightCols.out\n///\nEIGEN_DOC_BLOCK_ADDONS_INNER_PANEL_IF(column-major)\n///\n/// \\sa class Block, block(Index,Index,Index,Index)\n///\ntemplate<int N>\nEIGEN_DEVICE_FUNC\ninline typename NColsBlockXpr<N>::Type rightCols(Index n = N)\n{\n  return typename NColsBlockXpr<N>::Type(derived(), 0, cols() - n, rows(), n);\n}\n\n/// This is the const version of rightCols<int>().\ntemplate<int N>\nEIGEN_DEVICE_FUNC\ninline typename ConstNColsBlockXpr<N>::Type rightCols(Index n = N) const\n{\n  return typename ConstNColsBlockXpr<N>::Type(derived(), 0, cols() - n, rows(), n);\n}\n\n\n\n/// \\returns a block consisting of a range of columns of *this.\n///\n/// \\param startCol the index of the first column in the block\n/// \\param numCols the number of columns in the block\n///\n/// Example: \\include DenseBase_middleCols_int.cpp\n/// Output: \\verbinclude DenseBase_middleCols_int.out\n///\nEIGEN_DOC_BLOCK_ADDONS_INNER_PANEL_IF(column-major)\n///\n/// \\sa class Block, block(Index,Index,Index,Index)\n///\nEIGEN_DEVICE_FUNC\ninline ColsBlockXpr middleCols(Index startCol, Index numCols)\n{\n  return ColsBlockXpr(derived(), 0, startCol, rows(), numCols);\n}\n\n/// This is the const version of middleCols(Index,Index).\nEIGEN_DEVICE_FUNC\ninline ConstColsBlockXpr middleCols(Index startCol, Index numCols) const\n{\n  return ConstColsBlockXpr(derived(), 0, startCol, rows(), numCols);\n}\n\n/// \\returns a block consisting of a range of columns of *this.\n///\n/// \\tparam N the number of columns in the block as specified at compile-time\n/// \\param startCol the index of the first column in the block\n/// \\param n the number of columns in the block as specified at run-time\n///\n/// The compile-time and run-time information should not contradict. In other words,\n/// \\a n should equal \\a N unless \\a N is \\a Dynamic.\n///\n/// Example: \\include DenseBase_template_int_middleCols.cpp\n/// Output: \\verbinclude DenseBase_template_int_middleCols.out\n///\nEIGEN_DOC_BLOCK_ADDONS_INNER_PANEL_IF(column-major)\n///\n/// \\sa class Block, block(Index,Index,Index,Index)\n///\ntemplate<int N>\nEIGEN_DEVICE_FUNC\ninline typename NColsBlockXpr<N>::Type middleCols(Index startCol, Index n = N)\n{\n  return typename NColsBlockXpr<N>::Type(derived(), 0, startCol, rows(), n);\n}\n\n/// This is the const version of middleCols<int>().\ntemplate<int N>\nEIGEN_DEVICE_FUNC\ninline typename ConstNColsBlockXpr<N>::Type middleCols(Index startCol, Index n = N) const\n{\n  return typename ConstNColsBlockXpr<N>::Type(derived(), 0, startCol, rows(), n);\n}\n\n\n\n/// \\returns a fixed-size expression of a block in *this.\n///\n/// The template parameters \\a NRows and \\a NCols are the number of\n/// rows and columns in the block.\n///\n/// \\param startRow the first row in the block\n/// \\param startCol the first column in the block\n///\n/// Example: \\include MatrixBase_block_int_int.cpp\n/// Output: \\verbinclude MatrixBase_block_int_int.out\n///\n/// \\note since block is a templated member, the keyword template has to be used\n/// if the matrix type is also a template parameter: \\code m.template block<3,3>(1,1); \\endcode\n///\nEIGEN_DOC_BLOCK_ADDONS_NOT_INNER_PANEL\n///\n/// \\sa class Block, block(Index,Index,Index,Index)\n///\ntemplate<int NRows, int NCols>\nEIGEN_DEVICE_FUNC\ninline typename FixedBlockXpr<NRows,NCols>::Type block(Index startRow, Index startCol)\n{\n  return typename FixedBlockXpr<NRows,NCols>::Type(derived(), startRow, startCol);\n}\n\n/// This is the const version of block<>(Index, Index). */\ntemplate<int NRows, int NCols>\nEIGEN_DEVICE_FUNC\ninline const typename ConstFixedBlockXpr<NRows,NCols>::Type block(Index startRow, Index startCol) const\n{\n  return typename ConstFixedBlockXpr<NRows,NCols>::Type(derived(), startRow, startCol);\n}\n\n/// \\returns an expression of a block in *this.\n///\n/// \\tparam NRows number of rows in block as specified at compile-time\n/// \\tparam NCols number of columns in block as specified at compile-time\n/// \\param  startRow  the first row in the block\n/// \\param  startCol  the first column in the block\n/// \\param  blockRows number of rows in block as specified at run-time\n/// \\param  blockCols number of columns in block as specified at run-time\n///\n/// This function is mainly useful for blocks where the number of rows is specified at compile-time\n/// and the number of columns is specified at run-time, or vice versa. The compile-time and run-time\n/// information should not contradict. In other words, \\a blockRows should equal \\a NRows unless\n/// \\a NRows is \\a Dynamic, and the same for the number of columns.\n///\n/// Example: \\include MatrixBase_template_int_int_block_int_int_int_int.cpp\n/// Output: \\verbinclude MatrixBase_template_int_int_block_int_int_int_int.cpp\n///\nEIGEN_DOC_BLOCK_ADDONS_NOT_INNER_PANEL\n///\n/// \\sa class Block, block(Index,Index,Index,Index)\n///\ntemplate<int NRows, int NCols>\ninline typename FixedBlockXpr<NRows,NCols>::Type block(Index startRow, Index startCol,\n                                                  Index blockRows, Index blockCols)\n{\n  return typename FixedBlockXpr<NRows,NCols>::Type(derived(), startRow, startCol, blockRows, blockCols);\n}\n\n/// This is the const version of block<>(Index, Index, Index, Index). */\ntemplate<int NRows, int NCols>\ninline const typename ConstFixedBlockXpr<NRows,NCols>::Type block(Index startRow, Index startCol,\n                                                              Index blockRows, Index blockCols) const\n{\n  return typename ConstFixedBlockXpr<NRows,NCols>::Type(derived(), startRow, startCol, blockRows, blockCols);\n}\n\n/// \\returns an expression of the \\a i-th column of *this. Note that the numbering starts at 0.\n///\n/// Example: \\include MatrixBase_col.cpp\n/// Output: \\verbinclude MatrixBase_col.out\n///\nEIGEN_DOC_BLOCK_ADDONS_INNER_PANEL_IF(column-major)\n///\n/// \\sa row(), class Block */\nEIGEN_DEVICE_FUNC\ninline ColXpr col(Index i)\n{\n  return ColXpr(derived(), i);\n}\n\n/// This is the const version of col(). */\nEIGEN_DEVICE_FUNC\ninline ConstColXpr col(Index i) const\n{\n  return ConstColXpr(derived(), i);\n}\n\n/// \\returns an expression of the \\a i-th row of *this. Note that the numbering starts at 0.\n///\n/// Example: \\include MatrixBase_row.cpp\n/// Output: \\verbinclude MatrixBase_row.out\n///\nEIGEN_DOC_BLOCK_ADDONS_INNER_PANEL_IF(row-major)\n///\n/// \\sa col(), class Block */\nEIGEN_DEVICE_FUNC\ninline RowXpr row(Index i)\n{\n  return RowXpr(derived(), i);\n}\n\n/// This is the const version of row(). */\nEIGEN_DEVICE_FUNC\ninline ConstRowXpr row(Index i) const\n{\n  return ConstRowXpr(derived(), i);\n}\n\n/// \\returns a dynamic-size expression of a segment (i.e. a vector block) in *this.\n///\n/// \\only_for_vectors\n///\n/// \\param start the first coefficient in the segment\n/// \\param n the number of coefficients in the segment\n///\n/// Example: \\include MatrixBase_segment_int_int.cpp\n/// Output: \\verbinclude MatrixBase_segment_int_int.out\n///\n/// \\note Even though the returned expression has dynamic size, in the case\n/// when it is applied to a fixed-size vector, it inherits a fixed maximal size,\n/// which means that evaluating it does not cause a dynamic memory allocation.\n///\n/// \\sa class Block, segment(Index)\n///\nEIGEN_DEVICE_FUNC\ninline SegmentReturnType segment(Index start, Index n)\n{\n  EIGEN_STATIC_ASSERT_VECTOR_ONLY(Derived)\n  return SegmentReturnType(derived(), start, n);\n}\n\n\n/// This is the const version of segment(Index,Index).\nEIGEN_DEVICE_FUNC\ninline ConstSegmentReturnType segment(Index start, Index n) const\n{\n  EIGEN_STATIC_ASSERT_VECTOR_ONLY(Derived)\n  return ConstSegmentReturnType(derived(), start, n);\n}\n\n/// \\returns a dynamic-size expression of the first coefficients of *this.\n///\n/// \\only_for_vectors\n///\n/// \\param n the number of coefficients in the segment\n///\n/// Example: \\include MatrixBase_start_int.cpp\n/// Output: \\verbinclude MatrixBase_start_int.out\n///\n/// \\note Even though the returned expression has dynamic size, in the case\n/// when it is applied to a fixed-size vector, it inherits a fixed maximal size,\n/// which means that evaluating it does not cause a dynamic memory allocation.\n///\n/// \\sa class Block, block(Index,Index)\n///\nEIGEN_DEVICE_FUNC\ninline SegmentReturnType head(Index n)\n{\n  EIGEN_STATIC_ASSERT_VECTOR_ONLY(Derived)\n  return SegmentReturnType(derived(), 0, n);\n}\n\n/// This is the const version of head(Index).\nEIGEN_DEVICE_FUNC\ninline ConstSegmentReturnType head(Index n) const\n{\n  EIGEN_STATIC_ASSERT_VECTOR_ONLY(Derived)\n  return ConstSegmentReturnType(derived(), 0, n);\n}\n\n/// \\returns a dynamic-size expression of the last coefficients of *this.\n///\n/// \\only_for_vectors\n///\n/// \\param n the number of coefficients in the segment\n///\n/// Example: \\include MatrixBase_end_int.cpp\n/// Output: \\verbinclude MatrixBase_end_int.out\n///\n/// \\note Even though the returned expression has dynamic size, in the case\n/// when it is applied to a fixed-size vector, it inherits a fixed maximal size,\n/// which means that evaluating it does not cause a dynamic memory allocation.\n///\n/// \\sa class Block, block(Index,Index)\n///\nEIGEN_DEVICE_FUNC\ninline SegmentReturnType tail(Index n)\n{\n  EIGEN_STATIC_ASSERT_VECTOR_ONLY(Derived)\n  return SegmentReturnType(derived(), this->size() - n, n);\n}\n\n/// This is the const version of tail(Index).\nEIGEN_DEVICE_FUNC\ninline ConstSegmentReturnType tail(Index n) const\n{\n  EIGEN_STATIC_ASSERT_VECTOR_ONLY(Derived)\n  return ConstSegmentReturnType(derived(), this->size() - n, n);\n}\n\n/// \\returns a fixed-size expression of a segment (i.e. a vector block) in \\c *this\n///\n/// \\only_for_vectors\n///\n/// \\tparam N the number of coefficients in the segment as specified at compile-time\n/// \\param start the index of the first element in the segment\n/// \\param n the number of coefficients in the segment as specified at compile-time\n///\n/// The compile-time and run-time information should not contradict. In other words,\n/// \\a n should equal \\a N unless \\a N is \\a Dynamic.\n///\n/// Example: \\include MatrixBase_template_int_segment.cpp\n/// Output: \\verbinclude MatrixBase_template_int_segment.out\n///\n/// \\sa class Block\n///\ntemplate<int N>\nEIGEN_DEVICE_FUNC\ninline typename FixedSegmentReturnType<N>::Type segment(Index start, Index n = N)\n{\n  EIGEN_STATIC_ASSERT_VECTOR_ONLY(Derived)\n  return typename FixedSegmentReturnType<N>::Type(derived(), start, n);\n}\n\n/// This is the const version of segment<int>(Index).\ntemplate<int N>\nEIGEN_DEVICE_FUNC\ninline typename ConstFixedSegmentReturnType<N>::Type segment(Index start, Index n = N) const\n{\n  EIGEN_STATIC_ASSERT_VECTOR_ONLY(Derived)\n  return typename ConstFixedSegmentReturnType<N>::Type(derived(), start, n);\n}\n\n/// \\returns a fixed-size expression of the first coefficients of *this.\n///\n/// \\only_for_vectors\n///\n/// \\tparam N the number of coefficients in the segment as specified at compile-time\n/// \\param  n the number of coefficients in the segment as specified at run-time\n///\n/// The compile-time and run-time information should not contradict. In other words,\n/// \\a n should equal \\a N unless \\a N is \\a Dynamic.\n///\n/// Example: \\include MatrixBase_template_int_start.cpp\n/// Output: \\verbinclude MatrixBase_template_int_start.out\n///\n/// \\sa class Block\n///\ntemplate<int N>\nEIGEN_DEVICE_FUNC\ninline typename FixedSegmentReturnType<N>::Type head(Index n = N)\n{\n  EIGEN_STATIC_ASSERT_VECTOR_ONLY(Derived)\n  return typename FixedSegmentReturnType<N>::Type(derived(), 0, n);\n}\n\n/// This is the const version of head<int>().\ntemplate<int N>\nEIGEN_DEVICE_FUNC\ninline typename ConstFixedSegmentReturnType<N>::Type head(Index n = N) const\n{\n  EIGEN_STATIC_ASSERT_VECTOR_ONLY(Derived)\n  return typename ConstFixedSegmentReturnType<N>::Type(derived(), 0, n);\n}\n\n/// \\returns a fixed-size expression of the last coefficients of *this.\n///\n/// \\only_for_vectors\n///\n/// \\tparam N the number of coefficients in the segment as specified at compile-time\n/// \\param  n the number of coefficients in the segment as specified at run-time\n///\n/// The compile-time and run-time information should not contradict. In other words,\n/// \\a n should equal \\a N unless \\a N is \\a Dynamic.\n///\n/// Example: \\include MatrixBase_template_int_end.cpp\n/// Output: \\verbinclude MatrixBase_template_int_end.out\n///\n/// \\sa class Block\n///\ntemplate<int N>\nEIGEN_DEVICE_FUNC\ninline typename FixedSegmentReturnType<N>::Type tail(Index n = N)\n{\n  EIGEN_STATIC_ASSERT_VECTOR_ONLY(Derived)\n  return typename FixedSegmentReturnType<N>::Type(derived(), size() - n);\n}\n\n/// This is the const version of tail<int>.\ntemplate<int N>\nEIGEN_DEVICE_FUNC\ninline typename ConstFixedSegmentReturnType<N>::Type tail(Index n = N) const\n{\n  EIGEN_STATIC_ASSERT_VECTOR_ONLY(Derived)\n  return typename ConstFixedSegmentReturnType<N>::Type(derived(), size() - n);\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/plugins/CommonCwiseBinaryOps.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2016 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2006-2008 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n// This file is a base class plugin containing common coefficient wise functions.\n\n/** \\returns an expression of the difference of \\c *this and \\a other\n  *\n  * \\note If you want to substract a given scalar from all coefficients, see Cwise::operator-().\n  *\n  * \\sa class CwiseBinaryOp, operator-=()\n  */\nEIGEN_MAKE_CWISE_BINARY_OP(operator-,difference)\n\n/** \\returns an expression of the sum of \\c *this and \\a other\n  *\n  * \\note If you want to add a given scalar to all coefficients, see Cwise::operator+().\n  *\n  * \\sa class CwiseBinaryOp, operator+=()\n  */\nEIGEN_MAKE_CWISE_BINARY_OP(operator+,sum)\n\n/** \\returns an expression of a custom coefficient-wise operator \\a func of *this and \\a other\n  *\n  * The template parameter \\a CustomBinaryOp is the type of the functor\n  * of the custom operator (see class CwiseBinaryOp for an example)\n  *\n  * Here is an example illustrating the use of custom functors:\n  * \\include class_CwiseBinaryOp.cpp\n  * Output: \\verbinclude class_CwiseBinaryOp.out\n  *\n  * \\sa class CwiseBinaryOp, operator+(), operator-(), cwiseProduct()\n  */\ntemplate<typename CustomBinaryOp, typename OtherDerived>\nEIGEN_DEVICE_FUNC\nEIGEN_STRONG_INLINE const CwiseBinaryOp<CustomBinaryOp, const Derived, const OtherDerived>\nbinaryExpr(const EIGEN_CURRENT_STORAGE_BASE_CLASS<OtherDerived> &other, const CustomBinaryOp& func = CustomBinaryOp()) const\n{\n  return CwiseBinaryOp<CustomBinaryOp, const Derived, const OtherDerived>(derived(), other.derived(), func);\n}\n\n\n#ifndef EIGEN_PARSED_BY_DOXYGEN\nEIGEN_MAKE_SCALAR_BINARY_OP(operator*,product)\n#else\n/** \\returns an expression of \\c *this scaled by the scalar factor \\a scalar\n  *\n  * \\tparam T is the scalar type of \\a scalar. It must be compatible with the scalar type of the given expression.\n  */\ntemplate<typename T>\nconst CwiseBinaryOp<internal::scalar_product_op<Scalar,T>,Derived,Constant<T> > operator*(const T& scalar) const;\n/** \\returns an expression of \\a expr scaled by the scalar factor \\a scalar\n  *\n  * \\tparam T is the scalar type of \\a scalar. It must be compatible with the scalar type of the given expression.\n  */\ntemplate<typename T> friend\nconst CwiseBinaryOp<internal::scalar_product_op<T,Scalar>,Constant<T>,Derived> operator*(const T& scalar, const StorageBaseType& expr);\n#endif\n\n\n\n#ifndef EIGEN_PARSED_BY_DOXYGEN\nEIGEN_MAKE_SCALAR_BINARY_OP_ONTHERIGHT(operator/,quotient)\n#else\n/** \\returns an expression of \\c *this divided by the scalar value \\a scalar\n  *\n  * \\tparam T is the scalar type of \\a scalar. It must be compatible with the scalar type of the given expression.\n  */\ntemplate<typename T>\nconst CwiseBinaryOp<internal::scalar_quotient_op<Scalar,T>,Derived,Constant<T> > operator/(const T& scalar) const;\n#endif\n\n/** \\returns an expression of the coefficient-wise boolean \\b and operator of \\c *this and \\a other\n  *\n  * \\warning this operator is for expression of bool only.\n  *\n  * Example: \\include Cwise_boolean_and.cpp\n  * Output: \\verbinclude Cwise_boolean_and.out\n  *\n  * \\sa operator||(), select()\n  */\ntemplate<typename OtherDerived>\nEIGEN_DEVICE_FUNC\ninline const CwiseBinaryOp<internal::scalar_boolean_and_op, const Derived, const OtherDerived>\noperator&&(const EIGEN_CURRENT_STORAGE_BASE_CLASS<OtherDerived> &other) const\n{\n  EIGEN_STATIC_ASSERT((internal::is_same<bool,Scalar>::value && internal::is_same<bool,typename OtherDerived::Scalar>::value),\n                      THIS_METHOD_IS_ONLY_FOR_EXPRESSIONS_OF_BOOL);\n  return CwiseBinaryOp<internal::scalar_boolean_and_op, const Derived, const OtherDerived>(derived(),other.derived());\n}\n\n/** \\returns an expression of the coefficient-wise boolean \\b or operator of \\c *this and \\a other\n  *\n  * \\warning this operator is for expression of bool only.\n  *\n  * Example: \\include Cwise_boolean_or.cpp\n  * Output: \\verbinclude Cwise_boolean_or.out\n  *\n  * \\sa operator&&(), select()\n  */\ntemplate<typename OtherDerived>\nEIGEN_DEVICE_FUNC\ninline const CwiseBinaryOp<internal::scalar_boolean_or_op, const Derived, const OtherDerived>\noperator||(const EIGEN_CURRENT_STORAGE_BASE_CLASS<OtherDerived> &other) const\n{\n  EIGEN_STATIC_ASSERT((internal::is_same<bool,Scalar>::value && internal::is_same<bool,typename OtherDerived::Scalar>::value),\n                      THIS_METHOD_IS_ONLY_FOR_EXPRESSIONS_OF_BOOL);\n  return CwiseBinaryOp<internal::scalar_boolean_or_op, const Derived, const OtherDerived>(derived(),other.derived());\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/plugins/CommonCwiseUnaryOps.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2006-2008 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n// This file is a base class plugin containing common coefficient wise functions.\n\n#ifndef EIGEN_PARSED_BY_DOXYGEN\n\n/** \\internal the return type of conjugate() */\ntypedef typename internal::conditional<NumTraits<Scalar>::IsComplex,\n                    const CwiseUnaryOp<internal::scalar_conjugate_op<Scalar>, const Derived>,\n                    const Derived&\n                  >::type ConjugateReturnType;\n/** \\internal the return type of real() const */\ntypedef typename internal::conditional<NumTraits<Scalar>::IsComplex,\n                    const CwiseUnaryOp<internal::scalar_real_op<Scalar>, const Derived>,\n                    const Derived&\n                  >::type RealReturnType;\n/** \\internal the return type of real() */\ntypedef typename internal::conditional<NumTraits<Scalar>::IsComplex,\n                    CwiseUnaryView<internal::scalar_real_ref_op<Scalar>, Derived>,\n                    Derived&\n                  >::type NonConstRealReturnType;\n/** \\internal the return type of imag() const */\ntypedef CwiseUnaryOp<internal::scalar_imag_op<Scalar>, const Derived> ImagReturnType;\n/** \\internal the return type of imag() */\ntypedef CwiseUnaryView<internal::scalar_imag_ref_op<Scalar>, Derived> NonConstImagReturnType;\n\ntypedef CwiseUnaryOp<internal::scalar_opposite_op<Scalar>, const Derived> NegativeReturnType;\n\n#endif // not EIGEN_PARSED_BY_DOXYGEN\n\n/// \\returns an expression of the opposite of \\c *this\n///\nEIGEN_DOC_UNARY_ADDONS(operator-,opposite)\n///\nEIGEN_DEVICE_FUNC\ninline const NegativeReturnType\noperator-() const { return NegativeReturnType(derived()); }\n\n\ntemplate<class NewType> struct CastXpr { typedef typename internal::cast_return_type<Derived,const CwiseUnaryOp<internal::scalar_cast_op<Scalar, NewType>, const Derived> >::type Type; };\n\n/// \\returns an expression of \\c *this with the \\a Scalar type casted to\n/// \\a NewScalar.\n///\n/// The template parameter \\a NewScalar is the type we are casting the scalars to.\n///\nEIGEN_DOC_UNARY_ADDONS(cast,conversion function)\n///\n/// \\sa class CwiseUnaryOp\n///\ntemplate<typename NewType>\nEIGEN_DEVICE_FUNC\ntypename CastXpr<NewType>::Type\ncast() const\n{\n  return typename CastXpr<NewType>::Type(derived());\n}\n\n/// \\returns an expression of the complex conjugate of \\c *this.\n///\nEIGEN_DOC_UNARY_ADDONS(conjugate,complex conjugate)\n///\n/// \\sa <a href=\"group__CoeffwiseMathFunctions.html#cwisetable_conj\">Math functions</a>, MatrixBase::adjoint()\nEIGEN_DEVICE_FUNC\ninline ConjugateReturnType\nconjugate() const\n{\n  return ConjugateReturnType(derived());\n}\n\n/// \\returns a read-only expression of the real part of \\c *this.\n///\nEIGEN_DOC_UNARY_ADDONS(real,real part function)\n///\n/// \\sa imag()\nEIGEN_DEVICE_FUNC\ninline RealReturnType\nreal() const { return RealReturnType(derived()); }\n\n/// \\returns an read-only expression of the imaginary part of \\c *this.\n///\nEIGEN_DOC_UNARY_ADDONS(imag,imaginary part function)\n///\n/// \\sa real()\nEIGEN_DEVICE_FUNC\ninline const ImagReturnType\nimag() const { return ImagReturnType(derived()); }\n\n/// \\brief Apply a unary operator coefficient-wise\n/// \\param[in]  func  Functor implementing the unary operator\n/// \\tparam  CustomUnaryOp Type of \\a func\n/// \\returns An expression of a custom coefficient-wise unary operator \\a func of *this\n///\n/// The function \\c ptr_fun() from the C++ standard library can be used to make functors out of normal functions.\n///\n/// Example:\n/// \\include class_CwiseUnaryOp_ptrfun.cpp\n/// Output: \\verbinclude class_CwiseUnaryOp_ptrfun.out\n///\n/// Genuine functors allow for more possibilities, for instance it may contain a state.\n///\n/// Example:\n/// \\include class_CwiseUnaryOp.cpp\n/// Output: \\verbinclude class_CwiseUnaryOp.out\n///\nEIGEN_DOC_UNARY_ADDONS(unaryExpr,unary function)\n///\n/// \\sa unaryViewExpr, binaryExpr, class CwiseUnaryOp\n///\ntemplate<typename CustomUnaryOp>\nEIGEN_DEVICE_FUNC\ninline const CwiseUnaryOp<CustomUnaryOp, const Derived>\nunaryExpr(const CustomUnaryOp& func = CustomUnaryOp()) const\n{\n  return CwiseUnaryOp<CustomUnaryOp, const Derived>(derived(), func);\n}\n\n/// \\returns an expression of a custom coefficient-wise unary operator \\a func of *this\n///\n/// The template parameter \\a CustomUnaryOp is the type of the functor\n/// of the custom unary operator.\n///\n/// Example:\n/// \\include class_CwiseUnaryOp.cpp\n/// Output: \\verbinclude class_CwiseUnaryOp.out\n///\nEIGEN_DOC_UNARY_ADDONS(unaryViewExpr,unary function)\n///\n/// \\sa unaryExpr, binaryExpr class CwiseUnaryOp\n///\ntemplate<typename CustomViewOp>\nEIGEN_DEVICE_FUNC\ninline const CwiseUnaryView<CustomViewOp, const Derived>\nunaryViewExpr(const CustomViewOp& func = CustomViewOp()) const\n{\n  return CwiseUnaryView<CustomViewOp, const Derived>(derived(), func);\n}\n\n/// \\returns a non const expression of the real part of \\c *this.\n///\nEIGEN_DOC_UNARY_ADDONS(real,real part function)\n///\n/// \\sa imag()\nEIGEN_DEVICE_FUNC\ninline NonConstRealReturnType\nreal() { return NonConstRealReturnType(derived()); }\n\n/// \\returns a non const expression of the imaginary part of \\c *this.\n///\nEIGEN_DOC_UNARY_ADDONS(imag,imaginary part function)\n///\n/// \\sa real()\nEIGEN_DEVICE_FUNC\ninline NonConstImagReturnType\nimag() { return NonConstImagReturnType(derived()); }\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/plugins/MatrixCwiseBinaryOps.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2006-2008 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n// This file is a base class plugin containing matrix specifics coefficient wise functions.\n\n/** \\returns an expression of the Schur product (coefficient wise product) of *this and \\a other\n  *\n  * Example: \\include MatrixBase_cwiseProduct.cpp\n  * Output: \\verbinclude MatrixBase_cwiseProduct.out\n  *\n  * \\sa class CwiseBinaryOp, cwiseAbs2\n  */\ntemplate<typename OtherDerived>\nEIGEN_DEVICE_FUNC\nEIGEN_STRONG_INLINE const EIGEN_CWISE_BINARY_RETURN_TYPE(Derived,OtherDerived,product)\ncwiseProduct(const EIGEN_CURRENT_STORAGE_BASE_CLASS<OtherDerived> &other) const\n{\n  return EIGEN_CWISE_BINARY_RETURN_TYPE(Derived,OtherDerived,product)(derived(), other.derived());\n}\n\n/** \\returns an expression of the coefficient-wise == operator of *this and \\a other\n  *\n  * \\warning this performs an exact comparison, which is generally a bad idea with floating-point types.\n  * In order to check for equality between two vectors or matrices with floating-point coefficients, it is\n  * generally a far better idea to use a fuzzy comparison as provided by isApprox() and\n  * isMuchSmallerThan().\n  *\n  * Example: \\include MatrixBase_cwiseEqual.cpp\n  * Output: \\verbinclude MatrixBase_cwiseEqual.out\n  *\n  * \\sa cwiseNotEqual(), isApprox(), isMuchSmallerThan()\n  */\ntemplate<typename OtherDerived>\nEIGEN_DEVICE_FUNC\ninline const CwiseBinaryOp<std::equal_to<Scalar>, const Derived, const OtherDerived>\ncwiseEqual(const EIGEN_CURRENT_STORAGE_BASE_CLASS<OtherDerived> &other) const\n{\n  return CwiseBinaryOp<std::equal_to<Scalar>, const Derived, const OtherDerived>(derived(), other.derived());\n}\n\n/** \\returns an expression of the coefficient-wise != operator of *this and \\a other\n  *\n  * \\warning this performs an exact comparison, which is generally a bad idea with floating-point types.\n  * In order to check for equality between two vectors or matrices with floating-point coefficients, it is\n  * generally a far better idea to use a fuzzy comparison as provided by isApprox() and\n  * isMuchSmallerThan().\n  *\n  * Example: \\include MatrixBase_cwiseNotEqual.cpp\n  * Output: \\verbinclude MatrixBase_cwiseNotEqual.out\n  *\n  * \\sa cwiseEqual(), isApprox(), isMuchSmallerThan()\n  */\ntemplate<typename OtherDerived>\nEIGEN_DEVICE_FUNC\ninline const CwiseBinaryOp<std::not_equal_to<Scalar>, const Derived, const OtherDerived>\ncwiseNotEqual(const EIGEN_CURRENT_STORAGE_BASE_CLASS<OtherDerived> &other) const\n{\n  return CwiseBinaryOp<std::not_equal_to<Scalar>, const Derived, const OtherDerived>(derived(), other.derived());\n}\n\n/** \\returns an expression of the coefficient-wise min of *this and \\a other\n  *\n  * Example: \\include MatrixBase_cwiseMin.cpp\n  * Output: \\verbinclude MatrixBase_cwiseMin.out\n  *\n  * \\sa class CwiseBinaryOp, max()\n  */\ntemplate<typename OtherDerived>\nEIGEN_DEVICE_FUNC\nEIGEN_STRONG_INLINE const CwiseBinaryOp<internal::scalar_min_op<Scalar,Scalar>, const Derived, const OtherDerived>\ncwiseMin(const EIGEN_CURRENT_STORAGE_BASE_CLASS<OtherDerived> &other) const\n{\n  return CwiseBinaryOp<internal::scalar_min_op<Scalar,Scalar>, const Derived, const OtherDerived>(derived(), other.derived());\n}\n\n/** \\returns an expression of the coefficient-wise min of *this and scalar \\a other\n  *\n  * \\sa class CwiseBinaryOp, min()\n  */\nEIGEN_DEVICE_FUNC\nEIGEN_STRONG_INLINE const CwiseBinaryOp<internal::scalar_min_op<Scalar,Scalar>, const Derived, const ConstantReturnType>\ncwiseMin(const Scalar &other) const\n{\n  return cwiseMin(Derived::Constant(rows(), cols(), other));\n}\n\n/** \\returns an expression of the coefficient-wise max of *this and \\a other\n  *\n  * Example: \\include MatrixBase_cwiseMax.cpp\n  * Output: \\verbinclude MatrixBase_cwiseMax.out\n  *\n  * \\sa class CwiseBinaryOp, min()\n  */\ntemplate<typename OtherDerived>\nEIGEN_DEVICE_FUNC\nEIGEN_STRONG_INLINE const CwiseBinaryOp<internal::scalar_max_op<Scalar,Scalar>, const Derived, const OtherDerived>\ncwiseMax(const EIGEN_CURRENT_STORAGE_BASE_CLASS<OtherDerived> &other) const\n{\n  return CwiseBinaryOp<internal::scalar_max_op<Scalar,Scalar>, const Derived, const OtherDerived>(derived(), other.derived());\n}\n\n/** \\returns an expression of the coefficient-wise max of *this and scalar \\a other\n  *\n  * \\sa class CwiseBinaryOp, min()\n  */\nEIGEN_DEVICE_FUNC\nEIGEN_STRONG_INLINE const CwiseBinaryOp<internal::scalar_max_op<Scalar,Scalar>, const Derived, const ConstantReturnType>\ncwiseMax(const Scalar &other) const\n{\n  return cwiseMax(Derived::Constant(rows(), cols(), other));\n}\n\n\n/** \\returns an expression of the coefficient-wise quotient of *this and \\a other\n  *\n  * Example: \\include MatrixBase_cwiseQuotient.cpp\n  * Output: \\verbinclude MatrixBase_cwiseQuotient.out\n  *\n  * \\sa class CwiseBinaryOp, cwiseProduct(), cwiseInverse()\n  */\ntemplate<typename OtherDerived>\nEIGEN_DEVICE_FUNC\nEIGEN_STRONG_INLINE const CwiseBinaryOp<internal::scalar_quotient_op<Scalar>, const Derived, const OtherDerived>\ncwiseQuotient(const EIGEN_CURRENT_STORAGE_BASE_CLASS<OtherDerived> &other) const\n{\n  return CwiseBinaryOp<internal::scalar_quotient_op<Scalar>, const Derived, const OtherDerived>(derived(), other.derived());\n}\n\ntypedef CwiseBinaryOp<internal::scalar_cmp_op<Scalar,Scalar,internal::cmp_EQ>, const Derived, const ConstantReturnType> CwiseScalarEqualReturnType;\n\n/** \\returns an expression of the coefficient-wise == operator of \\c *this and a scalar \\a s\n  *\n  * \\warning this performs an exact comparison, which is generally a bad idea with floating-point types.\n  * In order to check for equality between two vectors or matrices with floating-point coefficients, it is\n  * generally a far better idea to use a fuzzy comparison as provided by isApprox() and\n  * isMuchSmallerThan().\n  *\n  * \\sa cwiseEqual(const MatrixBase<OtherDerived> &) const\n  */\nEIGEN_DEVICE_FUNC\ninline const CwiseScalarEqualReturnType\ncwiseEqual(const Scalar& s) const\n{\n  return CwiseScalarEqualReturnType(derived(), Derived::Constant(rows(), cols(), s), internal::scalar_cmp_op<Scalar,Scalar,internal::cmp_EQ>());\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen/src/plugins/MatrixCwiseUnaryOps.h",
    "content": "// This file is part of Eigen, a lightweight C++ template library\n// for linear algebra.\n//\n// Copyright (C) 2008-2009 Gael Guennebaud <gael.guennebaud@inria.fr>\n// Copyright (C) 2006-2008 Benoit Jacob <jacob.benoit.1@gmail.com>\n//\n// This Source Code Form is subject to the terms of the Mozilla\n// Public License v. 2.0. If a copy of the MPL was not distributed\n// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.\n\n// This file is included into the body of the base classes supporting matrix specific coefficient-wise functions.\n// This include MatrixBase and SparseMatrixBase.\n\n\ntypedef CwiseUnaryOp<internal::scalar_abs_op<Scalar>, const Derived> CwiseAbsReturnType;\ntypedef CwiseUnaryOp<internal::scalar_abs2_op<Scalar>, const Derived> CwiseAbs2ReturnType;\ntypedef CwiseUnaryOp<internal::scalar_sqrt_op<Scalar>, const Derived> CwiseSqrtReturnType;\ntypedef CwiseUnaryOp<internal::scalar_sign_op<Scalar>, const Derived> CwiseSignReturnType;\ntypedef CwiseUnaryOp<internal::scalar_inverse_op<Scalar>, const Derived> CwiseInverseReturnType;\n\n/// \\returns an expression of the coefficient-wise absolute value of \\c *this\n///\n/// Example: \\include MatrixBase_cwiseAbs.cpp\n/// Output: \\verbinclude MatrixBase_cwiseAbs.out\n///\nEIGEN_DOC_UNARY_ADDONS(cwiseAbs,absolute value)\n///\n/// \\sa cwiseAbs2()\n///\nEIGEN_DEVICE_FUNC\nEIGEN_STRONG_INLINE const CwiseAbsReturnType\ncwiseAbs() const { return CwiseAbsReturnType(derived()); }\n\n/// \\returns an expression of the coefficient-wise squared absolute value of \\c *this\n///\n/// Example: \\include MatrixBase_cwiseAbs2.cpp\n/// Output: \\verbinclude MatrixBase_cwiseAbs2.out\n///\nEIGEN_DOC_UNARY_ADDONS(cwiseAbs2,squared absolute value)\n///\n/// \\sa cwiseAbs()\n///\nEIGEN_DEVICE_FUNC\nEIGEN_STRONG_INLINE const CwiseAbs2ReturnType\ncwiseAbs2() const { return CwiseAbs2ReturnType(derived()); }\n\n/// \\returns an expression of the coefficient-wise square root of *this.\n///\n/// Example: \\include MatrixBase_cwiseSqrt.cpp\n/// Output: \\verbinclude MatrixBase_cwiseSqrt.out\n///\nEIGEN_DOC_UNARY_ADDONS(cwiseSqrt,square-root)\n///\n/// \\sa cwisePow(), cwiseSquare()\n///\nEIGEN_DEVICE_FUNC\ninline const CwiseSqrtReturnType\ncwiseSqrt() const { return CwiseSqrtReturnType(derived()); }\n\n/// \\returns an expression of the coefficient-wise signum of *this.\n///\n/// Example: \\include MatrixBase_cwiseSign.cpp\n/// Output: \\verbinclude MatrixBase_cwiseSign.out\n///\nEIGEN_DOC_UNARY_ADDONS(cwiseSign,sign function)\n///\nEIGEN_DEVICE_FUNC\ninline const CwiseSignReturnType\ncwiseSign() const { return CwiseSignReturnType(derived()); }\n\n\n/// \\returns an expression of the coefficient-wise inverse of *this.\n///\n/// Example: \\include MatrixBase_cwiseInverse.cpp\n/// Output: \\verbinclude MatrixBase_cwiseInverse.out\n///\nEIGEN_DOC_UNARY_ADDONS(cwiseInverse,inverse)\n///\n/// \\sa cwiseProduct()\n///\nEIGEN_DEVICE_FUNC\ninline const CwiseInverseReturnType\ncwiseInverse() const { return CwiseInverseReturnType(derived()); }\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Eigen331/src/Eigen.h",
    "content": "// Credits:   @rpavlik for writing this header.\r\n// Note:  \"Importantly, it includes a header to both indicate to the Arduino IDE\r\n//         that this library should be used, and set up the preprocessor environment\r\n//         so the ample #define lines in the Arduino and AVR libraries don't wreak havoc with Eigen.\r\n\n// Disable debug asserts.\n#define EIGEN_NO_DEBUG 1\n\n// Hint to number of registers\n#define EIGEN_ARCH_DEFAULT_NUMBER_OF_REGISTERS 16\n\n#ifdef A0\n# define NEED_A0_RESTORED A0\n# undef A0\n#endif\n#ifdef A1\n# define NEED_A1_RESTORED A1\n# undef A1\n#endif\n#ifdef B0\n# define NEED_B0_RESTORED B0\n# undef B0\n#endif\n#ifdef B1\n# define NEED_B1_RESTORED B1\n# undef B1\n#endif\n\nnamespace std {\n\tstruct nothrow_t;\n}\n\n\r\n// Include main EIGEN Core header\n#include <Eigen/Core>\n\r\n\n#ifdef NEED_A0_RESTORED\n# define A0 NEED_A0_RESTORED\n# undef NEED_A0_RESTORED\n#endif\n#ifdef NEED_A1_RESTORED\n# define A1 NEED_A1_RESTORED\n# undef NEED_A1_RESTORED\n#endif\n#ifdef NEED_B0_RESTORED\n# define B0 NEED_B0_RESTORED\n# undef NEED_B0_RESTORED\n#endif\n#ifdef NEED_B1_RESTORED\n# define B1 NEED_B1_RESTORED\n# undef NEED_B1_RESTORED\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/HX8347D/LCD.cpp",
    "content": "\r\n\r\n#include <LCD.h>\r\n#include <SPI.h>\r\n\r\n#define USE_FRAME_BUFFER     1\r\n\r\n\r\n#if USE_FRAME_BUFFER == 1\r\nuint16_t frame_buf[320*240];\r\n#endif\r\n\r\nvoid TFT::lcd_init()\r\n{\r\n\t__LCD_DC_OUT();\r\n\t__LCD_DC_SET();\r\n\r\n\t__LCD_CS_OUT();\r\n    __LCD_CS_SET();\r\n\r\n\t__LCD_BKL_OUT();\r\n    __LCD_BKL_OFF();\r\n\r\n\t//Driving ability Setting\r\n\tlcd_write_register(0xEA,0x00); //PTBA[15:8]\r\n\tlcd_write_register(0xEB,0x20); //PTBA[7:0]\r\n\tlcd_write_register(0xEC,0x0C); //STBA[15:8]\r\n\tlcd_write_register(0xED,0xC4); //STBA[7:0]\r\n\tlcd_write_register(0xE8,0x38); //OPON[7:0]\r\n\tlcd_write_register(0xE9,0x10); //OPON1[7:0]\r\n\tlcd_write_register(0xF1,0x01); //OTPS1B\r\n\tlcd_write_register(0xF2,0x10); //GEN\r\n\t//Gamma 2.2 Setting\r\n\tlcd_write_register(0x40,0x01); //\r\n\tlcd_write_register(0x41,0x00); //\r\n\tlcd_write_register(0x42,0x00); //\r\n\tlcd_write_register(0x43,0x10); //\r\n\tlcd_write_register(0x44,0x0E); //\r\n\tlcd_write_register(0x45,0x24); //\r\n\tlcd_write_register(0x46,0x04); //\r\n\tlcd_write_register(0x47,0x50); //\r\n\tlcd_write_register(0x48,0x02); //\r\n\tlcd_write_register(0x49,0x13); //\r\n\tlcd_write_register(0x4A,0x19); //\r\n\tlcd_write_register(0x4B,0x19); //\r\n\tlcd_write_register(0x4C,0x16); //\r\n\tlcd_write_register(0x50,0x1B); //\r\n\tlcd_write_register(0x51,0x31); //\r\n\tlcd_write_register(0x52,0x2F); //\r\n\tlcd_write_register(0x53,0x3F); //\r\n\tlcd_write_register(0x54,0x3F); //\r\n\tlcd_write_register(0x55,0x3E); //\r\n\tlcd_write_register(0x56,0x2F); //\r\n\tlcd_write_register(0x57,0x7B); //\r\n\tlcd_write_register(0x58,0x09); //\r\n\tlcd_write_register(0x59,0x06); //\r\n\tlcd_write_register(0x5A,0x06); //\r\n\tlcd_write_register(0x5B,0x0C); //\r\n\tlcd_write_register(0x5C,0x1D); //\r\n\tlcd_write_register(0x5D,0xCC); //\r\n\t//Power Voltage Setting\r\n\tlcd_write_register(0x1B,0x1B); //VRH=4.65V\r\n\tlcd_write_register(0x1A,0x01); //BT (VGH~15V,VGL~-10V,DDVDH~5V)\r\n\tlcd_write_register(0x24,0x2F); //VMH(VCOM High voltage ~3.2V)\r\n\tlcd_write_register(0x25,0x57); //VML(VCOM Low voltage -1.2V)\r\n\t//****VCOM offset**///\r\n\tlcd_write_register(0x23,0x88); //for Flicker adjust //can reload from OTP\r\n\t//Power on Setting\r\n\tlcd_write_register(0x18,0x34); //I/P_RADJ,N/P_RADJ, Normal mode 60Hz\r\n\tlcd_write_register(0x19,0x01); //OSC_EN='1', start Osc\r\n\tlcd_write_register(0x01,0x00); //DP_STB='0', out deep sleep\r\n\tlcd_write_register(0x1F,0x88);// GAS=1, VOMG=00, PON=0, DK=1, XDK=0, DVDH_TRI=0, STB=0\r\n\tdelay(5);\r\n\tlcd_write_register(0x1F,0x80);// GAS=1, VOMG=00, PON=0, DK=0, XDK=0, DVDH_TRI=0, STB=0\r\n\tdelay(5);\r\n\tlcd_write_register(0x1F,0x90);// GAS=1, VOMG=00, PON=1, DK=0, XDK=0, DVDH_TRI=0, STB=0\r\n\tdelay(5);\r\n\tlcd_write_register(0x1F,0xD0);// GAS=1, VOMG=10, PON=1, DK=0, XDK=0, DDVDH_TRI=0, STB=0\r\n\tdelay(5);\r\n\t//262k/65k color selection\r\n\tlcd_write_register(0x17,0x05); //default 0x06 262k color // 0x05 65k color\r\n\t//SET PANEL\r\n\tlcd_write_register(0x36,0x00); //SS_P, GS_P,REV_P,BGR_P\r\n\t//Display ON Setting\r\n\tlcd_write_register(0x28,0x38); //GON=1, DTE=1, D=1000\r\n\tdelay(40);\r\n\tlcd_write_register(0x28,0x3F); //GON=1, DTE=1, D=1100\r\n\r\n\tlcd_write_register(0x16,0x18);\r\n\t//Set GRAM Area\r\n\tlcd_write_register(0x02,0x00);\r\n\tlcd_write_register(0x03,0x00); //Column Start\r\n\tlcd_write_register(0x04,0x00);\r\n\tlcd_write_register(0x05,0xEF); //Column End\r\n\tlcd_write_register(0x06,0x00);\r\n\tlcd_write_register(0x07,0x00); //Row Start\r\n\tlcd_write_register(0x08,0x01);\r\n\tlcd_write_register(0x09,0x3F); //Row End\r\n\r\n    lcd_clear_screen(WHITE);\r\n\t__LCD_BKL_ON();\r\n}\r\n\r\n//draw a point on the lcd with the specified color.\r\n//hwXpos specify x position.\r\n//hwYpos specify y position.\r\n//hwColor color of the point.\r\n#if 1\r\nvoid TFT::lcd_draw_point(uint16_t hwXpos, uint16_t hwYpos, uint16_t hwColor)\r\n{\r\n\tif (hwXpos >= LCD_WIDTH || hwYpos >= LCD_HEIGHT) {\r\n\t\treturn;\r\n\t}\r\n\r\n  frame_buf[hwYpos*LCD_WIDTH+hwXpos] = hwColor>>8 | hwColor<<8;\r\n}\r\n\r\n#else\r\nvoid TFT::lcd_draw_point(uint16_t hwXpos, uint16_t hwYpos, uint16_t hwColor)\r\n{\r\n\tif (hwXpos >= LCD_WIDTH || hwYpos >= LCD_HEIGHT) {\r\n\t\treturn;\r\n\t}\r\n\r\n\tlcd_set_cursor(hwXpos, hwYpos);\r\n\tlcd_write_byte(0x22, LCD_CMD);\r\n  lcd_write_word(hwColor);\r\n}\r\n#endif\r\n\r\n\r\n\r\nvoid TFT::drawFrame(void)\r\n{\r\n\r\n#if USE_FRAME_BUFFER == 1\r\n  lcd_set_cursor(0, 0);\r\n\tlcd_write_byte(0x22, LCD_CMD);\r\n\r\n  __LCD_DC_SET();\r\n  __LCD_CS_CLR();\r\n\r\n/*\r\n  for (int i=0; i<LCD_WIDTH*LCD_HEIGHT; i++)\r\n  {\r\n    __LCD_WRITE_BYTE(frame_buf[i] >> 8);\r\n    __LCD_WRITE_BYTE(frame_buf[i] & 0xFF);\r\n  }\r\n  */\r\n  SPI.writeFast(frame_buf, LCD_WIDTH*LCD_HEIGHT*2);\r\n\r\n  __LCD_CS_SET();\r\n\r\n#endif\r\n}\r\n\r\n//display a char at the specified position on lcd.\r\nvoid TFT::lcd_display_char(uint16_t hwXpos, //specify x position.\r\n                         uint16_t hwYpos, //specify y position.\r\n                         uint8_t chChr,   //a char is display.\r\n                         uint8_t chSize,  //specify the size of the char\r\n                         uint16_t hwColor) //specify the color of the char\r\n{\r\n\tuint8_t i, j, chTemp;\r\n\tuint16_t hwYpos0 = hwYpos, hwColorVal = 0;\r\n\r\n\tif (hwXpos >= LCD_WIDTH || hwYpos >= LCD_HEIGHT) {\r\n\t\treturn;\r\n\t}\r\n\r\n\r\n    for (i = 0; i < chSize; i ++) {\r\n\t\tif (FONT_1206 == chSize) {\r\n\t\t\tchTemp = pgm_read_byte(&c_chFont1206[chChr - 0x20][i]);\r\n\t\t} else if (FONT_1608 == chSize) {\r\n\t\t\tchTemp = pgm_read_byte(&c_chFont1608[chChr - 0x20][i]);\r\n\t\t}\r\n\r\n        for (j = 0; j < 8; j ++) {\r\n    \t\tif (chTemp & 0x80) {\r\n\t\t\t\thwColorVal = hwColor;\r\n\t\t\t\tlcd_draw_point(hwXpos, hwYpos, hwColorVal);\r\n    \t\t}\r\n\t\t\tchTemp <<= 1;\r\n\t\t\thwYpos ++;\r\n\t\t\tif ((hwYpos - hwYpos0) == chSize) {\r\n\t\t\t\thwYpos = hwYpos0;\r\n\t\t\t\thwXpos ++;\r\n\t\t\t\tbreak;\r\n\t\t\t}\r\n\t\t}\r\n    }\r\n}\r\n\r\n\r\n//_pow\r\nstatic uint32_t _pow(uint8_t m, uint8_t n)\r\n{\r\n\tuint32_t result = 1;\r\n\r\n\twhile(n --) result *= m;\r\n\treturn result;\r\n}\r\n\r\n//display a number at the specified position on lcd.\r\nvoid TFT::lcd_display_num(uint16_t hwXpos,  //specify x position.\r\n                          uint16_t hwYpos, //specify y position.\r\n                          uint32_t chNum,  //a number is display.\r\n                          uint8_t chLen,   //length ot the number\r\n                          uint8_t chSize,  //specify the size of the number\r\n                          uint16_t hwColor) //specify the color of the number\r\n{\r\n\tuint8_t i;\r\n\tuint8_t chTemp, chShow = 0;\r\n\r\n\tif (hwXpos >= LCD_WIDTH || hwYpos >= LCD_HEIGHT) {\r\n\t\treturn;\r\n\t}\r\n\r\n\tfor(i = 0; i < chLen; i ++) {\r\n\t\tchTemp = (chNum / _pow(10, chLen - i - 1)) % 10;\r\n\t\tif(chShow == 0 && i < (chLen - 1)) {\r\n\t\t\tif(chTemp == 0) {\r\n\t\t\t\tlcd_display_char(hwXpos + (chSize / 2) * i, hwYpos, ' ', chSize, hwColor);\r\n\t\t\t\tcontinue;\r\n\t\t\t} else {\r\n\t\t\t\tchShow = 1;\r\n\t\t\t}\r\n\t\t}\r\n\t \tlcd_display_char(hwXpos + (chSize / 2) * i, hwYpos, chTemp + '0', chSize, hwColor);\r\n\t}\r\n}\r\n\r\n//display a string at the specified position on lcd.\r\nvoid TFT::lcd_display_string(uint16_t hwXpos, //specify x position.\r\n                         uint16_t hwYpos,   //specify y position.\r\n                         const uint8_t *pchString,  //a pointer to string\r\n                         uint8_t chSize,    // the size of the string\r\n                         uint16_t hwColor)  // specify the color of the string\r\n{\r\n\r\n\tif (hwXpos >= LCD_WIDTH || hwYpos >= LCD_HEIGHT) {\r\n\t\treturn;\r\n\t}\r\n\r\n    while (*pchString != '\\0') {\r\n        if (hwXpos > (LCD_WIDTH - chSize / 2)) {\r\n\t\t\thwXpos = 0;\r\n\t\t\thwYpos += chSize;\r\n\t\t\tif (hwYpos > (LCD_HEIGHT - chSize)) {\r\n\t\t\t\thwYpos = hwXpos = 0;\r\n\t\t\t\tlcd_clear_screen(0x00);\r\n\t\t\t}\r\n\t\t}\r\n\r\n        lcd_display_char(hwXpos, hwYpos, (uint8_t)*pchString, chSize, hwColor);\r\n        hwXpos += chSize / 2;\r\n        pchString ++;\r\n    }\r\n}\r\n\r\n//draw a line at the specified position on lcd.\r\nvoid TFT::lcd_draw_line(uint16_t hwXpos0, //specify x0 position.\r\n                      uint16_t hwYpos0, //specify y0 position.\r\n                      uint16_t hwXpos1, //specify x1 position.\r\n                      uint16_t hwYpos1, //specify y1 position.\r\n                      uint16_t hwColor) //specify the color of the line\r\n{\r\n\tint x = hwXpos1 - hwXpos0;\r\n    int y = hwYpos1 - hwYpos0;\r\n    int dx = abs(x), sx = hwXpos0 < hwXpos1 ? 1 : -1;\r\n    int dy = -abs(y), sy = hwYpos0 < hwYpos1 ? 1 : -1;\r\n    int err = dx + dy, e2;\r\n\r\n\tif (hwXpos0 >= LCD_WIDTH || hwYpos0 >= LCD_HEIGHT || hwXpos1 >= LCD_WIDTH || hwYpos1 >= LCD_HEIGHT) {\r\n\t\treturn;\r\n\t}\r\n\r\n    for (;;){\r\n        lcd_draw_point(hwXpos0, hwYpos0 , hwColor);\r\n        e2 = 2 * err;\r\n        if (e2 >= dy) {\r\n            if (hwXpos0 == hwXpos1) break;\r\n            err += dy; hwXpos0 += sx;\r\n        }\r\n        if (e2 <= dx) {\r\n            if (hwYpos0 == hwYpos1) break;\r\n            err += dx; hwYpos0 += sy;\r\n        }\r\n    }\r\n}\r\n\r\n//draw a circle at the specified position on lcd.\r\nvoid TFT::lcd_draw_circle(uint16_t hwXpos,  //specify x position.\r\n                        uint16_t hwYpos,  //specify y position.\r\n                        uint16_t hwRadius, //specify the radius of the circle.\r\n                        uint16_t hwColor)  //specify the color of the circle.\r\n{\r\n\tint x = -hwRadius, y = 0, err = 2 - 2 * hwRadius, e2;\r\n\r\n\tif (hwXpos >= LCD_WIDTH || hwYpos >= LCD_HEIGHT) {\r\n\t\treturn;\r\n\t}\r\n\r\n    do {\r\n        lcd_draw_point(hwXpos - x, hwYpos + y, hwColor);\r\n        lcd_draw_point(hwXpos + x, hwYpos + y, hwColor);\r\n        lcd_draw_point(hwXpos + x, hwYpos - y, hwColor);\r\n        lcd_draw_point(hwXpos - x, hwYpos - y, hwColor);\r\n        e2 = err;\r\n        if (e2 <= y) {\r\n            err += ++ y * 2 + 1;\r\n            if(-x == y && e2 <= x) e2 = 0;\r\n        }\r\n        if(e2 > x) err += ++ x * 2 + 1;\r\n    } while(x <= 0);\r\n}\r\n\r\n//fill a rectangle out at the specified position on lcd.\r\nvoid TFT::lcd_fill_rect(uint16_t hwXpos,  //specify x position.\r\n                   uint16_t hwYpos,  //specify y position.\r\n                   uint16_t hwWidth, //specify the width of the rectangle.\r\n                   uint16_t hwHeight, //specify the height of the rectangle.\r\n                   uint16_t hwColor)  //specify the color of rectangle.\r\n{\r\n\tuint16_t i, j;\r\n\r\n\tif (hwXpos >= LCD_WIDTH || hwYpos >= LCD_HEIGHT) {\r\n\t\treturn;\r\n\t}\r\n\r\n\tfor(i = 0; i < hwHeight; i ++){\r\n\t\tfor(j = 0; j < hwWidth; j ++){\r\n\t\t\tlcd_draw_point(hwXpos + j, hwYpos + i, hwColor);\r\n\t\t}\r\n\t}\r\n}\r\n\r\n//draw a vertical line at the specified position on lcd.\r\nvoid TFT::lcd_draw_v_line(uint16_t hwXpos, //specify x position.\r\n                        uint16_t hwYpos, //specify y position.\r\n                        uint16_t hwHeight, //specify the height of the vertical line.\r\n                        uint16_t hwColor)  //specify the color of the vertical line.\r\n{\r\n\tuint16_t i, y1 = min(hwYpos + hwHeight, LCD_HEIGHT - 1);\r\n\r\n\tif (hwXpos >= LCD_WIDTH || hwYpos >= LCD_HEIGHT) {\r\n\t\treturn;\r\n\t}\r\n\r\n    for (i = hwYpos; i < y1; i ++) {\r\n        lcd_draw_point(hwXpos, i, hwColor);\r\n    }\r\n}\r\n\r\n//draw a horizonal line at the specified position on lcd.\r\nvoid TFT::lcd_draw_h_line(uint16_t hwXpos, //specify x position.\r\n                        uint16_t hwYpos,  //specify y position.\r\n                        uint16_t hwWidth, //specify the width of the horizonal line.\r\n                        uint16_t hwColor) //specify the color of the horizonal line.\r\n{\r\n\tuint16_t i, x1 = min(hwXpos + hwWidth, LCD_WIDTH - 1);\r\n\r\n\tif (hwXpos >= LCD_WIDTH || hwYpos >= LCD_HEIGHT) {\r\n\t\treturn;\r\n\t}\r\n\r\n    for (i = hwXpos; i < x1; i ++) {\r\n        lcd_draw_point(i, hwYpos, hwColor);\r\n    }\r\n}\r\n\r\nvoid TFT::lcd_draw_rect(uint16_t hwXpos,  //specify x position.\r\n                      uint16_t hwYpos,  //specify y position.\r\n                      uint16_t hwWidth, //specify the width of the rectangle.\r\n                      uint16_t hwHeight, //specify the height of the rectangle.\r\n                      uint16_t hwColor)  //specify the color of rectangle.\r\n{\r\n\tif (hwXpos >= LCD_WIDTH || hwYpos >= LCD_HEIGHT) {\r\n\t\treturn;\r\n\t}\r\n\r\n\tlcd_draw_h_line(hwXpos, hwYpos, hwWidth, hwColor);\r\n\tlcd_draw_h_line(hwXpos, hwYpos + hwHeight, hwWidth, hwColor);\r\n\tlcd_draw_v_line(hwXpos, hwYpos, hwHeight, hwColor);\r\n\tlcd_draw_v_line(hwXpos + hwWidth, hwYpos, hwHeight + 1, hwColor);\r\n}\r\n\r\n\r\nTFT Tft = TFT();\r\n/*********************************************************************************************************\r\n  END FILE\r\n*********************************************************************************************************/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/HX8347D/LCD.h",
    "content": "#ifndef LCD_h\r\n#define LCD_h\r\n\r\n#include <Arduino.h>\r\n#include <avr/pgmspace.h>\r\n#include <SPI.h>\r\n\r\n#include \"font.h\"\r\n\r\n//Basic Colors\r\n#define WHITE          0xFFFF\r\n#define BLACK          0x0000\r\n#define BLUE           0x001F\r\n#define BRED           0XF81F\r\n#define GRED \t\t   0XFFE0\r\n#define GBLUE\t\t   0X07FF\r\n#define RED            0xF800\r\n#define MAGENTA        0xF81F\r\n#define GREEN          0x07E0\r\n#define CYAN           0x7FFF\r\n#define YELLOW         0xFFE0\r\n#define BROWN \t\t   0XBC40\r\n#define BRRED \t\t   0XFC07\r\n#define GRAY  \t\t   0X8430\r\n\r\n#define LCD_CMD      0\r\n#define LCD_DATA     1\r\n\r\n#define FONT_1206    12\r\n#define FONT_1608    16\r\n\r\n#define LCD_WIDTH    240\r\n#define LCD_HEIGHT   320\r\n\r\n\r\n#if  defined(__AVR_ATmega32U4__)\r\n\r\n#define __LCD_CS_OUT()    DDRB |= 0x40\r\n#define __LCD_CS_CLR()    PORTB &=~ 0x40\r\n#define __LCD_CS_SET()    PORTB |=  0x40\r\n\r\n#define __LCD_DC_OUT()    DDRE |= 0x40\r\n#define __LCD_DC_CLR()    PORTE &=~ 0x40\r\n#define __LCD_DC_SET()    PORTE |=  0x40\r\n\r\n#define __LCD_BKL_OUT()   DDRB |= 0x20\r\n#define __LCD_BKL_OFF()   PORTB &=~ 0x20\r\n#define __LCD_BKL_ON()    PORTB |=  0x20\r\n\r\n#elif defined(__AVR_ATmega328__)\r\n\r\n#define __LCD_CS_OUT()    DDRB |= 0x04\r\n#define __LCD_CS_CLR()    PORTB &=~ 0x04\r\n#define __LCD_CS_SET()    PORTB |=  0x04\r\n\r\n#define __LCD_DC_OUT()    DDRD |= 0x80\r\n#define __LCD_DC_CLR()    PORTD &=~ 0x80\r\n#define __LCD_DC_SET()    PORTD |=  0x80\r\n\r\n#define __LCD_BKL_OUT()   DDRB |= 0x02\r\n#define __LCD_BKL_OFF()   PORTB &=~ 0x02\r\n#define __LCD_BKL_ON()    PORTB |=  0x02\r\n\r\n#else\r\n\r\n#define LCD_DC_PIN         7\r\n#define LCD_BKL_PIN        9\r\n#define LCD_CS_PIN        10\r\n\r\n#define __LCD_CS_OUT()    pinMode(LCD_CS_PIN, OUTPUT)\r\n#define __LCD_CS_CLR()    digitalWrite(LCD_CS_PIN, LOW)\r\n#define __LCD_CS_SET()    digitalWrite(LCD_CS_PIN, HIGH)\r\n\r\n#define __LCD_DC_OUT()    pinMode(LCD_DC_PIN, OUTPUT)\r\n#define __LCD_DC_CLR()    digitalWrite(LCD_DC_PIN, LOW)\r\n#define __LCD_DC_SET()    digitalWrite(LCD_DC_PIN, HIGH)\r\n\r\n#define __LCD_BKL_OUT()   pinMode(LCD_BKL_PIN, OUTPUT)\r\n#define __LCD_BKL_OFF()   digitalWrite(LCD_BKL_PIN, LOW)\r\n#define __LCD_BKL_ON()    digitalWrite(LCD_BKL_PIN, HIGH)\r\n\r\n#endif\r\n\r\n#define __LCD_WRITE_BYTE(__DATA)       SPI.transfer(__DATA)\r\n\r\n\r\n\r\n\r\nclass TFT\r\n{\r\n\r\npublic:\r\n\r\n  void drawFrame(void);\r\n\r\n\tvoid lcd_write_byte(uint8_t chByte, uint8_t chCmd)\r\n\t{\r\n\t    if (chCmd) {\r\n\t        __LCD_DC_SET();\r\n\t    } else {\r\n\t        __LCD_DC_CLR();\r\n\t    }\r\n\r\n\t    __LCD_CS_CLR();\r\n\t    __LCD_WRITE_BYTE(chByte);\r\n\t    __LCD_CS_SET();\r\n\t}\r\n\r\n\tinline void lcd_write_word(uint16_t hwData)\r\n\t{\r\n\t\t__LCD_DC_SET();\r\n\t    __LCD_CS_CLR();\r\n\t    __LCD_WRITE_BYTE(hwData >> 8);\r\n\t    __LCD_WRITE_BYTE(hwData & 0xFF);\r\n\t    __LCD_CS_SET();\r\n\t}\r\n\r\n\r\n\t//write a word(two bytes) to the specified register of lcd.\r\n\t//chRegister address of the register of lcd.\r\n\t//hwValue value is written to the specified register.\r\n\tvoid lcd_write_register(uint8_t chRegister, uint8_t chValue)\r\n\t{\r\n\t\tlcd_write_byte(chRegister, LCD_CMD);\r\n\t\tlcd_write_byte(chValue, LCD_DATA);\r\n\t}\r\n\r\n\t//set the specified position of cursor on lcd.\r\n\t//hwXpos specify x position\r\n\t//hwYpos specify y position\r\n\tvoid lcd_set_cursor(uint16_t hwXpos, uint16_t hwYpos)\r\n\t{\r\n\t\tif (hwXpos >= LCD_WIDTH|| hwYpos >= LCD_HEIGHT) {\r\n\t\t\treturn;\r\n\t\t}\r\n\r\n\t\tlcd_write_register(0x02, hwXpos >> 8);\r\n\t\tlcd_write_register(0x03, hwXpos & 0xFF); //Column Start\r\n\t\tlcd_write_register(0x06, hwYpos >> 8);\r\n\t\tlcd_write_register(0x07, hwYpos & 0xFF); //Row Start\r\n\t}\r\n\r\n    //clear the lcd with the specified color.\r\n\tvoid lcd_clear_screen(uint16_t hwColor)\r\n\t{\r\n\t\tuint32_t i, wCount = LCD_WIDTH;\r\n\r\n\t\twCount *= LCD_HEIGHT;\r\n\r\n\t\tlcd_set_cursor(0, 0);\r\n\t\tlcd_write_byte(0x22, LCD_CMD);\r\n\r\n\t    __LCD_DC_SET();\r\n\t\t__LCD_CS_CLR();\r\n\t\tfor (i = 0; i < wCount; i ++) {\r\n\t\t\t__LCD_WRITE_BYTE(hwColor >> 8);\r\n\t\t\t__LCD_WRITE_BYTE(hwColor & 0xFF);\r\n\t\t}\r\n\t\t__LCD_CS_SET();\r\n\t}\r\n\r\n\tvoid lcd_init ();\r\n\tvoid lcd_draw_point(uint16_t hwXpos, uint16_t hwYpos, uint16_t hwColor);\r\n\tvoid lcd_display_char(uint16_t hwXpos, //specify x position.\r\n                         uint16_t hwYpos, //specify y position.\r\n                         uint8_t chChr,   //a char is display.\r\n                         uint8_t chSize,  //specify the size of the char\r\n                         uint16_t hwColor); //specify the color of the char\r\n\t//display a number at the specified position on lcd.\r\n\tvoid lcd_display_num(uint16_t hwXpos,  //specify x position.\r\n\t                          uint16_t hwYpos, //specify y position.\r\n\t                          uint32_t chNum,  //a number is display.\r\n\t                          uint8_t chLen,   //length ot the number\r\n\t                          uint8_t chSize,  //specify the size of the number\r\n\t                          uint16_t hwColor); //specify the color of the number\r\n\t//display a string at the specified position on lcd.\r\n\tvoid lcd_display_string(uint16_t hwXpos, //specify x position.\r\n\t                         uint16_t hwYpos,   //specify y position.\r\n\t                         const uint8_t *pchString,  //a pointer to string\r\n\t                         uint8_t chSize,    // the size of the string\r\n\t                         uint16_t hwColor);  // specify the color of the string\r\n    void lcd_draw_line(uint16_t hwXpos0, //specify x0 position.\r\n                      uint16_t hwYpos0, //specify y0 position.\r\n                      uint16_t hwXpos1, //specify x1 position.\r\n                      uint16_t hwYpos1, //specify y1 position.\r\n                      uint16_t hwColor); //specify the color of the line\r\n    void lcd_draw_circle(uint16_t hwXpos,  //specify x position.\r\n                        uint16_t hwYpos,  //specify y position.\r\n                        uint16_t hwRadius, //specify the radius of the circle.\r\n                        uint16_t hwColor);  //specify the color of the circle.\r\n    void lcd_fill_rect(uint16_t hwXpos,  //specify x position.\r\n                   uint16_t hwYpos,  //specify y position.\r\n                   uint16_t hwWidth, //specify the width of the rectangle.\r\n                   uint16_t hwHeight, //specify the height of the rectangle.\r\n                   uint16_t hwColor);  //specify the color of rectangle.\r\n    void lcd_draw_v_line(uint16_t hwXpos, //specify x position.\r\n                        uint16_t hwYpos, //specify y position.\r\n                        uint16_t hwHeight, //specify the height of the vertical line.\r\n                        uint16_t hwColor);  //specify the color of the vertical line.\r\n    void lcd_draw_h_line(uint16_t hwXpos, //specify x position.\r\n                        uint16_t hwYpos,  //specify y position.\r\n                        uint16_t hwWidth, //specify the width of the horizonal line.\r\n                        uint16_t hwColor); //specify the color of the horizonal line.\r\n\tvoid lcd_draw_rect(uint16_t hwXpos,  //specify x position.\r\n                      uint16_t hwYpos,  //specify y position.\r\n                      uint16_t hwWidth, //specify the width of the rectangle.\r\n                      uint16_t hwHeight, //specify the height of the rectangle.\r\n                      uint16_t hwColor);  //specify the color of rectangle.\r\n\r\n};\r\n\r\nextern TFT Tft;\r\n\r\n#endif\r\n\r\n/*********************************************************************************************************\r\n  END FILE\r\n*********************************************************************************************************/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/HX8347D/font.c",
    "content": "#include <avr/pgmspace.h>\n\nconst uint8_t c_chFont1206[95][12] PROGMEM =\n{\n\t{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*\" \",0*/\n\t{0x00,0x00,0x00,0x00,0x3F,0x40,0x00,0x00,0x00,0x00,0x00,0x00},/*\"!\",1*/\n\t{0x00,0x00,0x30,0x00,0x40,0x00,0x30,0x00,0x40,0x00,0x00,0x00},/*\"\"\",2*/\n\t{0x09,0x00,0x0B,0xC0,0x3D,0x00,0x0B,0xC0,0x3D,0x00,0x09,0x00},/*\"#\",3*/\n\t{0x18,0xC0,0x24,0x40,0x7F,0xE0,0x22,0x40,0x31,0x80,0x00,0x00},/*\"$\",4*/\n\t{0x18,0x00,0x24,0xC0,0x1B,0x00,0x0D,0x80,0x32,0x40,0x01,0x80},/*\"%\",5*/\n\t{0x03,0x80,0x1C,0x40,0x27,0x40,0x1C,0x80,0x07,0x40,0x00,0x40},/*\"&\",6*/\n\t{0x10,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*\"'\",7*/\n\t{0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0x80,0x20,0x40,0x40,0x20},/*\"(\",8*/\n\t{0x00,0x00,0x40,0x20,0x20,0x40,0x1F,0x80,0x00,0x00,0x00,0x00},/*\")\",9*/\n\t{0x09,0x00,0x06,0x00,0x1F,0x80,0x06,0x00,0x09,0x00,0x00,0x00},/*\"*\",10*/\n\t{0x04,0x00,0x04,0x00,0x3F,0x80,0x04,0x00,0x04,0x00,0x00,0x00},/*\"+\",11*/\n\t{0x00,0x10,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*\",\",12*/\n\t{0x04,0x00,0x04,0x00,0x04,0x00,0x04,0x00,0x04,0x00,0x00,0x00},/*\"-\",13*/\n\t{0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*\".\",14*/\n\t{0x00,0x20,0x01,0xC0,0x06,0x00,0x38,0x00,0x40,0x00,0x00,0x00},/*\"/\",15*/\n\t{0x1F,0x80,0x20,0x40,0x20,0x40,0x20,0x40,0x1F,0x80,0x00,0x00},/*\"0\",16*/\n\t{0x00,0x00,0x10,0x40,0x3F,0xC0,0x00,0x40,0x00,0x00,0x00,0x00},/*\"1\",17*/\n\t{0x18,0xC0,0x21,0x40,0x22,0x40,0x24,0x40,0x18,0x40,0x00,0x00},/*\"2\",18*/\n\t{0x10,0x80,0x20,0x40,0x24,0x40,0x24,0x40,0x1B,0x80,0x00,0x00},/*\"3\",19*/\n\t{0x02,0x00,0x0D,0x00,0x11,0x00,0x3F,0xC0,0x01,0x40,0x00,0x00},/*\"4\",20*/\n\t{0x3C,0x80,0x24,0x40,0x24,0x40,0x24,0x40,0x23,0x80,0x00,0x00},/*\"5\",21*/\n\t{0x1F,0x80,0x24,0x40,0x24,0x40,0x34,0x40,0x03,0x80,0x00,0x00},/*\"6\",22*/\n\t{0x30,0x00,0x20,0x00,0x27,0xC0,0x38,0x00,0x20,0x00,0x00,0x00},/*\"7\",23*/\n\t{0x1B,0x80,0x24,0x40,0x24,0x40,0x24,0x40,0x1B,0x80,0x00,0x00},/*\"8\",24*/\n\t{0x1C,0x00,0x22,0xC0,0x22,0x40,0x22,0x40,0x1F,0x80,0x00,0x00},/*\"9\",25*/\n\t{0x00,0x00,0x00,0x00,0x08,0x40,0x00,0x00,0x00,0x00,0x00,0x00},/*\":\",26*/\n\t{0x00,0x00,0x00,0x00,0x04,0x60,0x00,0x00,0x00,0x00,0x00,0x00},/*\";\",27*/\n\t{0x00,0x00,0x04,0x00,0x0A,0x00,0x11,0x00,0x20,0x80,0x40,0x40},/*\"<\",28*/\n\t{0x09,0x00,0x09,0x00,0x09,0x00,0x09,0x00,0x09,0x00,0x00,0x00},/*\"=\",29*/\n\t{0x00,0x00,0x40,0x40,0x20,0x80,0x11,0x00,0x0A,0x00,0x04,0x00},/*\">\",30*/\n\t{0x18,0x00,0x20,0x00,0x23,0x40,0x24,0x00,0x18,0x00,0x00,0x00},/*\"?\",31*/\n\t{0x1F,0x80,0x20,0x40,0x27,0x40,0x29,0x40,0x1F,0x40,0x00,0x00},/*\"@\",32*/\n\t{0x00,0x40,0x07,0xC0,0x39,0x00,0x0F,0x00,0x01,0xC0,0x00,0x40},/*\"A\",33*/\n\t{0x20,0x40,0x3F,0xC0,0x24,0x40,0x24,0x40,0x1B,0x80,0x00,0x00},/*\"B\",34*/\n\t{0x1F,0x80,0x20,0x40,0x20,0x40,0x20,0x40,0x30,0x80,0x00,0x00},/*\"C\",35*/\n\t{0x20,0x40,0x3F,0xC0,0x20,0x40,0x20,0x40,0x1F,0x80,0x00,0x00},/*\"D\",36*/\n\t{0x20,0x40,0x3F,0xC0,0x24,0x40,0x2E,0x40,0x30,0xC0,0x00,0x00},/*\"E\",37*/\n\t{0x20,0x40,0x3F,0xC0,0x24,0x40,0x2E,0x00,0x30,0x00,0x00,0x00},/*\"F\",38*/\n\t{0x0F,0x00,0x10,0x80,0x20,0x40,0x22,0x40,0x33,0x80,0x02,0x00},/*\"G\",39*/\n\t{0x20,0x40,0x3F,0xC0,0x04,0x00,0x04,0x00,0x3F,0xC0,0x20,0x40},/*\"H\",40*/\n\t{0x20,0x40,0x20,0x40,0x3F,0xC0,0x20,0x40,0x20,0x40,0x00,0x00},/*\"I\",41*/\n\t{0x00,0x60,0x20,0x20,0x20,0x20,0x3F,0xC0,0x20,0x00,0x20,0x00},/*\"J\",42*/\n\t{0x20,0x40,0x3F,0xC0,0x24,0x40,0x0B,0x00,0x30,0xC0,0x20,0x40},/*\"K\",43*/\n\t{0x20,0x40,0x3F,0xC0,0x20,0x40,0x00,0x40,0x00,0x40,0x00,0xC0},/*\"L\",44*/\n\t{0x3F,0xC0,0x3C,0x00,0x03,0xC0,0x3C,0x00,0x3F,0xC0,0x00,0x00},/*\"M\",45*/\n\t{0x20,0x40,0x3F,0xC0,0x0C,0x40,0x23,0x00,0x3F,0xC0,0x20,0x00},/*\"N\",46*/\n\t{0x1F,0x80,0x20,0x40,0x20,0x40,0x20,0x40,0x1F,0x80,0x00,0x00},/*\"O\",47*/\n\t{0x20,0x40,0x3F,0xC0,0x24,0x40,0x24,0x00,0x18,0x00,0x00,0x00},/*\"P\",48*/\n\t{0x1F,0x80,0x21,0x40,0x21,0x40,0x20,0xE0,0x1F,0xA0,0x00,0x00},/*\"Q\",49*/\n\t{0x20,0x40,0x3F,0xC0,0x24,0x40,0x26,0x00,0x19,0xC0,0x00,0x40},/*\"R\",50*/\n\t{0x18,0xC0,0x24,0x40,0x24,0x40,0x22,0x40,0x31,0x80,0x00,0x00},/*\"S\",51*/\n\t{0x30,0x00,0x20,0x40,0x3F,0xC0,0x20,0x40,0x30,0x00,0x00,0x00},/*\"T\",52*/\n\t{0x20,0x00,0x3F,0x80,0x00,0x40,0x00,0x40,0x3F,0x80,0x20,0x00},/*\"U\",53*/\n\t{0x20,0x00,0x3E,0x00,0x01,0xC0,0x07,0x00,0x38,0x00,0x20,0x00},/*\"V\",54*/\n\t{0x38,0x00,0x07,0xC0,0x3C,0x00,0x07,0xC0,0x38,0x00,0x00,0x00},/*\"W\",55*/\n\t{0x20,0x40,0x39,0xC0,0x06,0x00,0x39,0xC0,0x20,0x40,0x00,0x00},/*\"X\",56*/\n\t{0x20,0x00,0x38,0x40,0x07,0xC0,0x38,0x40,0x20,0x00,0x00,0x00},/*\"Y\",57*/\n\t{0x30,0x40,0x21,0xC0,0x26,0x40,0x38,0x40,0x20,0xC0,0x00,0x00},/*\"Z\",58*/\n\t{0x00,0x00,0x00,0x00,0x7F,0xE0,0x40,0x20,0x40,0x20,0x00,0x00},/*\"[\",59*/\n\t{0x00,0x00,0x70,0x00,0x0C,0x00,0x03,0x80,0x00,0x40,0x00,0x00},/*\"\\\",60*/\n\t{0x00,0x00,0x40,0x20,0x40,0x20,0x7F,0xE0,0x00,0x00,0x00,0x00},/*\"]\",61*/\n\t{0x00,0x00,0x20,0x00,0x40,0x00,0x20,0x00,0x00,0x00,0x00,0x00},/*\"^\",62*/\n\t{0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10},/*\"_\",63*/\n\t{0x00,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*\"`\",64*/\n\t{0x00,0x00,0x02,0x80,0x05,0x40,0x05,0x40,0x03,0xC0,0x00,0x40},/*\"a\",65*/\n\t{0x20,0x00,0x3F,0xC0,0x04,0x40,0x04,0x40,0x03,0x80,0x00,0x00},/*\"b\",66*/\n\t{0x00,0x00,0x03,0x80,0x04,0x40,0x04,0x40,0x06,0x40,0x00,0x00},/*\"c\",67*/\n\t{0x00,0x00,0x03,0x80,0x04,0x40,0x24,0x40,0x3F,0xC0,0x00,0x40},/*\"d\",68*/\n\t{0x00,0x00,0x03,0x80,0x05,0x40,0x05,0x40,0x03,0x40,0x00,0x00},/*\"e\",69*/\n\t{0x00,0x00,0x04,0x40,0x1F,0xC0,0x24,0x40,0x24,0x40,0x20,0x00},/*\"f\",70*/\n\t{0x00,0x00,0x02,0xE0,0x05,0x50,0x05,0x50,0x06,0x50,0x04,0x20},/*\"g\",71*/\n\t{0x20,0x40,0x3F,0xC0,0x04,0x40,0x04,0x00,0x03,0xC0,0x00,0x40},/*\"h\",72*/\n\t{0x00,0x00,0x04,0x40,0x27,0xC0,0x00,0x40,0x00,0x00,0x00,0x00},/*\"i\",73*/\n\t{0x00,0x10,0x00,0x10,0x04,0x10,0x27,0xE0,0x00,0x00,0x00,0x00},/*\"j\",74*/\n\t{0x20,0x40,0x3F,0xC0,0x01,0x40,0x07,0x00,0x04,0xC0,0x04,0x40},/*\"k\",75*/\n\t{0x20,0x40,0x20,0x40,0x3F,0xC0,0x00,0x40,0x00,0x40,0x00,0x00},/*\"l\",76*/\n\t{0x07,0xC0,0x04,0x00,0x07,0xC0,0x04,0x00,0x03,0xC0,0x00,0x00},/*\"m\",77*/\n\t{0x04,0x40,0x07,0xC0,0x04,0x40,0x04,0x00,0x03,0xC0,0x00,0x40},/*\"n\",78*/\n\t{0x00,0x00,0x03,0x80,0x04,0x40,0x04,0x40,0x03,0x80,0x00,0x00},/*\"o\",79*/\n\t{0x04,0x10,0x07,0xF0,0x04,0x50,0x04,0x40,0x03,0x80,0x00,0x00},/*\"p\",80*/\n\t{0x00,0x00,0x03,0x80,0x04,0x40,0x04,0x50,0x07,0xF0,0x00,0x10},/*\"q\",81*/\n\t{0x04,0x40,0x07,0xC0,0x02,0x40,0x04,0x00,0x04,0x00,0x00,0x00},/*\"r\",82*/\n\t{0x00,0x00,0x06,0x40,0x05,0x40,0x05,0x40,0x04,0xC0,0x00,0x00},/*\"s\",83*/\n\t{0x00,0x00,0x04,0x00,0x1F,0x80,0x04,0x40,0x00,0x40,0x00,0x00},/*\"t\",84*/\n\t{0x04,0x00,0x07,0x80,0x00,0x40,0x04,0x40,0x07,0xC0,0x00,0x40},/*\"u\",85*/\n\t{0x04,0x00,0x07,0x00,0x04,0xC0,0x01,0x80,0x06,0x00,0x04,0x00},/*\"v\",86*/\n\t{0x06,0x00,0x01,0xC0,0x07,0x00,0x01,0xC0,0x06,0x00,0x00,0x00},/*\"w\",87*/\n\t{0x04,0x40,0x06,0xC0,0x01,0x00,0x06,0xC0,0x04,0x40,0x00,0x00},/*\"x\",88*/\n\t{0x04,0x10,0x07,0x10,0x04,0xE0,0x01,0x80,0x06,0x00,0x04,0x00},/*\"y\",89*/\n\t{0x00,0x00,0x04,0x40,0x05,0xC0,0x06,0x40,0x04,0x40,0x00,0x00},/*\"z\",90*/\n\t{0x00,0x00,0x00,0x00,0x04,0x00,0x7B,0xE0,0x40,0x20,0x00,0x00},/*\"{\",91*/\n\t{0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xF0,0x00,0x00,0x00,0x00},/*\"|\",92*/\n\t{0x00,0x00,0x40,0x20,0x7B,0xE0,0x04,0x00,0x00,0x00,0x00,0x00},/*\"}\",93*/\n\t{0x40,0x00,0x80,0x00,0x40,0x00,0x20,0x00,0x20,0x00,0x40,0x00},/*\"~\",94*/\n\n};\n\nconst uint8_t c_chFont1608[95][16] PROGMEM = {\t  \n{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*\" \",0*/\n{0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xCC,0x00,0x0C,0x00,0x00,0x00,0x00,0x00,0x00},/*\"!\",1*/\n{0x00,0x00,0x08,0x00,0x30,0x00,0x60,0x00,0x08,0x00,0x30,0x00,0x60,0x00,0x00,0x00},/*\"\"\",2*/\n{0x02,0x20,0x03,0xFC,0x1E,0x20,0x02,0x20,0x03,0xFC,0x1E,0x20,0x02,0x20,0x00,0x00},/*\"#\",3*/\n{0x00,0x00,0x0E,0x18,0x11,0x04,0x3F,0xFF,0x10,0x84,0x0C,0x78,0x00,0x00,0x00,0x00},/*\"$\",4*/\n{0x0F,0x00,0x10,0x84,0x0F,0x38,0x00,0xC0,0x07,0x78,0x18,0x84,0x00,0x78,0x00,0x00},/*\"%\",5*/\n{0x00,0x78,0x0F,0x84,0x10,0xC4,0x11,0x24,0x0E,0x98,0x00,0xE4,0x00,0x84,0x00,0x08},/*\"&\",6*/\n{0x08,0x00,0x68,0x00,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*\"'\",7*/\n{0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xE0,0x18,0x18,0x20,0x04,0x40,0x02,0x00,0x00},/*\"(\",8*/\n{0x00,0x00,0x40,0x02,0x20,0x04,0x18,0x18,0x07,0xE0,0x00,0x00,0x00,0x00,0x00,0x00},/*\")\",9*/\n{0x02,0x40,0x02,0x40,0x01,0x80,0x0F,0xF0,0x01,0x80,0x02,0x40,0x02,0x40,0x00,0x00},/*\"*\",10*/\n{0x00,0x80,0x00,0x80,0x00,0x80,0x0F,0xF8,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x00},/*\"+\",11*/\n{0x00,0x01,0x00,0x0D,0x00,0x0E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*\",\",12*/\n{0x00,0x00,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80},/*\"-\",13*/\n{0x00,0x00,0x00,0x0C,0x00,0x0C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*\".\",14*/\n{0x00,0x00,0x00,0x06,0x00,0x18,0x00,0x60,0x01,0x80,0x06,0x00,0x18,0x00,0x20,0x00},/*\"/\",15*/\n{0x00,0x00,0x07,0xF0,0x08,0x08,0x10,0x04,0x10,0x04,0x08,0x08,0x07,0xF0,0x00,0x00},/*\"0\",16*/\n{0x00,0x00,0x08,0x04,0x08,0x04,0x1F,0xFC,0x00,0x04,0x00,0x04,0x00,0x00,0x00,0x00},/*\"1\",17*/\n{0x00,0x00,0x0E,0x0C,0x10,0x14,0x10,0x24,0x10,0x44,0x11,0x84,0x0E,0x0C,0x00,0x00},/*\"2\",18*/\n{0x00,0x00,0x0C,0x18,0x10,0x04,0x11,0x04,0x11,0x04,0x12,0x88,0x0C,0x70,0x00,0x00},/*\"3\",19*/\n{0x00,0x00,0x00,0xE0,0x03,0x20,0x04,0x24,0x08,0x24,0x1F,0xFC,0x00,0x24,0x00,0x00},/*\"4\",20*/\n{0x00,0x00,0x1F,0x98,0x10,0x84,0x11,0x04,0x11,0x04,0x10,0x88,0x10,0x70,0x00,0x00},/*\"5\",21*/\n{0x00,0x00,0x07,0xF0,0x08,0x88,0x11,0x04,0x11,0x04,0x18,0x88,0x00,0x70,0x00,0x00},/*\"6\",22*/\n{0x00,0x00,0x1C,0x00,0x10,0x00,0x10,0xFC,0x13,0x00,0x1C,0x00,0x10,0x00,0x00,0x00},/*\"7\",23*/\n{0x00,0x00,0x0E,0x38,0x11,0x44,0x10,0x84,0x10,0x84,0x11,0x44,0x0E,0x38,0x00,0x00},/*\"8\",24*/\n{0x00,0x00,0x07,0x00,0x08,0x8C,0x10,0x44,0x10,0x44,0x08,0x88,0x07,0xF0,0x00,0x00},/*\"9\",25*/\n{0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x0C,0x03,0x0C,0x00,0x00,0x00,0x00,0x00,0x00},/*\":\",26*/\n{0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*\";\",27*/\n{0x00,0x00,0x00,0x80,0x01,0x40,0x02,0x20,0x04,0x10,0x08,0x08,0x10,0x04,0x00,0x00},/*\"<\",28*/\n{0x02,0x20,0x02,0x20,0x02,0x20,0x02,0x20,0x02,0x20,0x02,0x20,0x02,0x20,0x00,0x00},/*\"=\",29*/\n{0x00,0x00,0x10,0x04,0x08,0x08,0x04,0x10,0x02,0x20,0x01,0x40,0x00,0x80,0x00,0x00},/*\">\",30*/\n{0x00,0x00,0x0E,0x00,0x12,0x00,0x10,0x0C,0x10,0x6C,0x10,0x80,0x0F,0x00,0x00,0x00},/*\"?\",31*/\n{0x03,0xE0,0x0C,0x18,0x13,0xE4,0x14,0x24,0x17,0xC4,0x08,0x28,0x07,0xD0,0x00,0x00},/*\"@\",32*/\n{0x00,0x04,0x00,0x3C,0x03,0xC4,0x1C,0x40,0x07,0x40,0x00,0xE4,0x00,0x1C,0x00,0x04},/*\"A\",33*/\n{0x10,0x04,0x1F,0xFC,0x11,0x04,0x11,0x04,0x11,0x04,0x0E,0x88,0x00,0x70,0x00,0x00},/*\"B\",34*/\n{0x03,0xE0,0x0C,0x18,0x10,0x04,0x10,0x04,0x10,0x04,0x10,0x08,0x1C,0x10,0x00,0x00},/*\"C\",35*/\n{0x10,0x04,0x1F,0xFC,0x10,0x04,0x10,0x04,0x10,0x04,0x08,0x08,0x07,0xF0,0x00,0x00},/*\"D\",36*/\n{0x10,0x04,0x1F,0xFC,0x11,0x04,0x11,0x04,0x17,0xC4,0x10,0x04,0x08,0x18,0x00,0x00},/*\"E\",37*/\n{0x10,0x04,0x1F,0xFC,0x11,0x04,0x11,0x00,0x17,0xC0,0x10,0x00,0x08,0x00,0x00,0x00},/*\"F\",38*/\n{0x03,0xE0,0x0C,0x18,0x10,0x04,0x10,0x04,0x10,0x44,0x1C,0x78,0x00,0x40,0x00,0x00},/*\"G\",39*/\n{0x10,0x04,0x1F,0xFC,0x10,0x84,0x00,0x80,0x00,0x80,0x10,0x84,0x1F,0xFC,0x10,0x04},/*\"H\",40*/\n{0x00,0x00,0x10,0x04,0x10,0x04,0x1F,0xFC,0x10,0x04,0x10,0x04,0x00,0x00,0x00,0x00},/*\"I\",41*/\n{0x00,0x03,0x00,0x01,0x10,0x01,0x10,0x01,0x1F,0xFE,0x10,0x00,0x10,0x00,0x00,0x00},/*\"J\",42*/\n{0x10,0x04,0x1F,0xFC,0x11,0x04,0x03,0x80,0x14,0x64,0x18,0x1C,0x10,0x04,0x00,0x00},/*\"K\",43*/\n{0x10,0x04,0x1F,0xFC,0x10,0x04,0x00,0x04,0x00,0x04,0x00,0x04,0x00,0x0C,0x00,0x00},/*\"L\",44*/\n{0x10,0x04,0x1F,0xFC,0x1F,0x00,0x00,0xFC,0x1F,0x00,0x1F,0xFC,0x10,0x04,0x00,0x00},/*\"M\",45*/\n{0x10,0x04,0x1F,0xFC,0x0C,0x04,0x03,0x00,0x00,0xE0,0x10,0x18,0x1F,0xFC,0x10,0x00},/*\"N\",46*/\n{0x07,0xF0,0x08,0x08,0x10,0x04,0x10,0x04,0x10,0x04,0x08,0x08,0x07,0xF0,0x00,0x00},/*\"O\",47*/\n{0x10,0x04,0x1F,0xFC,0x10,0x84,0x10,0x80,0x10,0x80,0x10,0x80,0x0F,0x00,0x00,0x00},/*\"P\",48*/\n{0x07,0xF0,0x08,0x18,0x10,0x24,0x10,0x24,0x10,0x1C,0x08,0x0A,0x07,0xF2,0x00,0x00},/*\"Q\",49*/\n{0x10,0x04,0x1F,0xFC,0x11,0x04,0x11,0x00,0x11,0xC0,0x11,0x30,0x0E,0x0C,0x00,0x04},/*\"R\",50*/\n{0x00,0x00,0x0E,0x1C,0x11,0x04,0x10,0x84,0x10,0x84,0x10,0x44,0x1C,0x38,0x00,0x00},/*\"S\",51*/\n{0x18,0x00,0x10,0x00,0x10,0x04,0x1F,0xFC,0x10,0x04,0x10,0x00,0x18,0x00,0x00,0x00},/*\"T\",52*/\n{0x10,0x00,0x1F,0xF8,0x10,0x04,0x00,0x04,0x00,0x04,0x10,0x04,0x1F,0xF8,0x10,0x00},/*\"U\",53*/\n{0x10,0x00,0x1E,0x00,0x11,0xE0,0x00,0x1C,0x00,0x70,0x13,0x80,0x1C,0x00,0x10,0x00},/*\"V\",54*/\n{0x1F,0xC0,0x10,0x3C,0x00,0xE0,0x1F,0x00,0x00,0xE0,0x10,0x3C,0x1F,0xC0,0x00,0x00},/*\"W\",55*/\n{0x10,0x04,0x18,0x0C,0x16,0x34,0x01,0xC0,0x01,0xC0,0x16,0x34,0x18,0x0C,0x10,0x04},/*\"X\",56*/\n{0x10,0x00,0x1C,0x00,0x13,0x04,0x00,0xFC,0x13,0x04,0x1C,0x00,0x10,0x00,0x00,0x00},/*\"Y\",57*/\n{0x08,0x04,0x10,0x1C,0x10,0x64,0x10,0x84,0x13,0x04,0x1C,0x04,0x10,0x18,0x00,0x00},/*\"Z\",58*/\n{0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFE,0x40,0x02,0x40,0x02,0x40,0x02,0x00,0x00},/*\"[\",59*/\n{0x00,0x00,0x30,0x00,0x0C,0x00,0x03,0x80,0x00,0x60,0x00,0x1C,0x00,0x03,0x00,0x00},/*\"\\\",60*/\n{0x00,0x00,0x40,0x02,0x40,0x02,0x40,0x02,0x7F,0xFE,0x00,0x00,0x00,0x00,0x00,0x00},/*\"]\",61*/\n{0x00,0x00,0x00,0x00,0x20,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x20,0x00,0x00,0x00},/*\"^\",62*/\n{0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01},/*\"_\",63*/\n{0x00,0x00,0x40,0x00,0x40,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*\"`\",64*/\n{0x00,0x00,0x00,0x98,0x01,0x24,0x01,0x44,0x01,0x44,0x01,0x44,0x00,0xFC,0x00,0x04},/*\"a\",65*/\n{0x10,0x00,0x1F,0xFC,0x00,0x88,0x01,0x04,0x01,0x04,0x00,0x88,0x00,0x70,0x00,0x00},/*\"b\",66*/\n{0x00,0x00,0x00,0x70,0x00,0x88,0x01,0x04,0x01,0x04,0x01,0x04,0x00,0x88,0x00,0x00},/*\"c\",67*/\n{0x00,0x00,0x00,0x70,0x00,0x88,0x01,0x04,0x01,0x04,0x11,0x08,0x1F,0xFC,0x00,0x04},/*\"d\",68*/\n{0x00,0x00,0x00,0xF8,0x01,0x44,0x01,0x44,0x01,0x44,0x01,0x44,0x00,0xC8,0x00,0x00},/*\"e\",69*/\n{0x00,0x00,0x01,0x04,0x01,0x04,0x0F,0xFC,0x11,0x04,0x11,0x04,0x11,0x00,0x18,0x00},/*\"f\",70*/\n{0x00,0x00,0x00,0xD6,0x01,0x29,0x01,0x29,0x01,0x29,0x01,0xC9,0x01,0x06,0x00,0x00},/*\"g\",71*/\n{0x10,0x04,0x1F,0xFC,0x00,0x84,0x01,0x00,0x01,0x00,0x01,0x04,0x00,0xFC,0x00,0x04},/*\"h\",72*/\n{0x00,0x00,0x01,0x04,0x19,0x04,0x19,0xFC,0x00,0x04,0x00,0x04,0x00,0x00,0x00,0x00},/*\"i\",73*/\n{0x00,0x00,0x00,0x03,0x00,0x01,0x01,0x01,0x19,0x01,0x19,0xFE,0x00,0x00,0x00,0x00},/*\"j\",74*/\n{0x10,0x04,0x1F,0xFC,0x00,0x24,0x00,0x40,0x01,0xB4,0x01,0x0C,0x01,0x04,0x00,0x00},/*\"k\",75*/\n{0x00,0x00,0x10,0x04,0x10,0x04,0x1F,0xFC,0x00,0x04,0x00,0x04,0x00,0x00,0x00,0x00},/*\"l\",76*/\n{0x01,0x04,0x01,0xFC,0x01,0x04,0x01,0x00,0x01,0xFC,0x01,0x04,0x01,0x00,0x00,0xFC},/*\"m\",77*/\n{0x01,0x04,0x01,0xFC,0x00,0x84,0x01,0x00,0x01,0x00,0x01,0x04,0x00,0xFC,0x00,0x04},/*\"n\",78*/\n{0x00,0x00,0x00,0xF8,0x01,0x04,0x01,0x04,0x01,0x04,0x01,0x04,0x00,0xF8,0x00,0x00},/*\"o\",79*/\n{0x01,0x01,0x01,0xFF,0x00,0x85,0x01,0x04,0x01,0x04,0x00,0x88,0x00,0x70,0x00,0x00},/*\"p\",80*/\n{0x00,0x00,0x00,0x70,0x00,0x88,0x01,0x04,0x01,0x04,0x01,0x05,0x01,0xFF,0x00,0x01},/*\"q\",81*/\n{0x01,0x04,0x01,0x04,0x01,0xFC,0x00,0x84,0x01,0x04,0x01,0x00,0x01,0x80,0x00,0x00},/*\"r\",82*/\n{0x00,0x00,0x00,0xCC,0x01,0x24,0x01,0x24,0x01,0x24,0x01,0x24,0x01,0x98,0x00,0x00},/*\"s\",83*/\n{0x00,0x00,0x01,0x00,0x01,0x00,0x07,0xF8,0x01,0x04,0x01,0x04,0x00,0x00,0x00,0x00},/*\"t\",84*/\n{0x01,0x00,0x01,0xF8,0x00,0x04,0x00,0x04,0x00,0x04,0x01,0x08,0x01,0xFC,0x00,0x04},/*\"u\",85*/\n{0x01,0x00,0x01,0x80,0x01,0x70,0x00,0x0C,0x00,0x10,0x01,0x60,0x01,0x80,0x01,0x00},/*\"v\",86*/\n{0x01,0xF0,0x01,0x0C,0x00,0x30,0x01,0xC0,0x00,0x30,0x01,0x0C,0x01,0xF0,0x01,0x00},/*\"w\",87*/\n{0x00,0x00,0x01,0x04,0x01,0x8C,0x00,0x74,0x01,0x70,0x01,0x8C,0x01,0x04,0x00,0x00},/*\"x\",88*/\n{0x01,0x01,0x01,0x81,0x01,0x71,0x00,0x0E,0x00,0x18,0x01,0x60,0x01,0x80,0x01,0x00},/*\"y\",89*/\n{0x00,0x00,0x01,0x84,0x01,0x0C,0x01,0x34,0x01,0x44,0x01,0x84,0x01,0x0C,0x00,0x00},/*\"z\",90*/\n{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x3E,0xFC,0x40,0x02,0x40,0x02},/*\"{\",91*/\n{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00},/*\"|\",92*/\n{0x00,0x00,0x40,0x02,0x40,0x02,0x3E,0xFC,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*\"}\",93*/\n{0x00,0x00,0x60,0x00,0x80,0x00,0x80,0x00,0x40,0x00,0x40,0x00,0x20,0x00,0x20,0x00},/*\"~\",94*/\n};\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/HX8347D/font.h",
    "content": "extern const uint8_t c_chFont1206[95][12];\nextern const uint8_t c_chFont1608[95][16];\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/I2Cdev/I2Cdev.cpp",
    "content": "// I2Cdev library collection - Main I2C device class\n// Abstracts bit and byte I2C R/W functions into a convenient class\n// 2013-06-05 by Jeff Rowberg <jeff@rowberg.net>\n//\n// Changelog:\n//      2013-05-06 - add Francesco Ferrara's Fastwire v0.24 implementation with small modifications\n//      2013-05-05 - fix issue with writing bit values to words (Sasquatch/Farzanegan)\n//      2012-06-09 - fix major issue with reading > 32 bytes at a time with Arduino Wire\n//                 - add compiler warnings when using outdated or IDE or limited I2Cdev implementation\n//      2011-11-01 - fix write*Bits mask calculation (thanks sasquatch @ Arduino forums)\n//      2011-10-03 - added automatic Arduino version detection for ease of use\n//      2011-10-02 - added Gene Knight's NBWire TwoWire class implementation with small modifications\n//      2011-08-31 - added support for Arduino 1.0 Wire library (methods are different from 0.x)\n//      2011-08-03 - added optional timeout parameter to read* methods to easily change from default\n//      2011-08-02 - added support for 16-bit registers\n//                 - fixed incorrect Doxygen comments on some methods\n//                 - added timeout value for read operations (thanks mem @ Arduino forums)\n//      2011-07-30 - changed read/write function structures to return success or byte counts\n//                 - made all methods static for multi-device memory savings\n//      2011-07-28 - initial release\n\n/* ============================================\nI2Cdev device library code is placed under the MIT license\nCopyright (c) 2013 Jeff Rowberg\n\nPermission is hereby granted, free of charge, to any person obtaining a copy\nof this software and associated documentation files (the \"Software\"), to deal\nin the Software without restriction, including without limitation the rights\nto use, copy, modify, merge, publish, distribute, sublicense, and/or sell\ncopies of the Software, and to permit persons to whom the Software is\nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in\nall copies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\nTHE SOFTWARE.\n===============================================\n*/\n\n\n\n#include \"I2Cdev.h\"\n\n#if I2CDEV_IMPLEMENTATION == I2CDEV_ARDUINO_WIRE\n#include <Wire.h>\n#endif\n\n#if I2CDEV_IMPLEMENTATION == I2CDEV_ARDUINO_WIRE\n\n\n#elif I2CDEV_IMPLEMENTATION == I2CDEV_BUILTIN_FASTWIRE\nI2C_HandleTypeDef I2cHandle;\n\n#endif\n\n\n/** Default constructor.\n */\nI2Cdev::I2Cdev() {\n}\n\nvoid I2Cdev::begin( uint32_t freq )\n{\n  #if I2CDEV_IMPLEMENTATION == I2CDEV_BUILTIN_FASTWIRE\n  I2cHandle.Instance             = I2C1;\n\n  if     ( freq == 400 ) I2cHandle.Init.Timing = 0x6000030D; //0x4 0 9 1 27 32;\n  else if( freq == 100 ) I2cHandle.Init.Timing = 0x20404768;\n  else                   I2cHandle.Init.Timing = 0x6000030D; //0x4 0 9 1 27 32;\n\n\n  I2cHandle.Init.OwnAddress1     = 0x00;\n  I2cHandle.Init.AddressingMode  = I2C_ADDRESSINGMODE_7BIT;\n  I2cHandle.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;\n  I2cHandle.Init.OwnAddress2     = 0xFF;\n  I2cHandle.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;\n  I2cHandle.Init.NoStretchMode   = I2C_NOSTRETCH_DISABLE;\n\n  if(HAL_I2C_Init(&I2cHandle) != HAL_OK)\n  {\n  }\n\n  /* Enable the Analog I2C Filter */\n  HAL_I2CEx_ConfigAnalogFilter(&I2cHandle,I2C_ANALOGFILTER_ENABLE);\n  #endif\n}\n\n\n/** Read a single bit from an 8-bit device register.\n * @param devAddr I2C slave device address\n * @param regAddr Register regAddr to read from\n * @param bitNum Bit position to read (0-7)\n * @param data Container for single bit value\n * @param timeout Optional read timeout in milliseconds (0 to disable, leave off to use default class value in I2Cdev::readTimeout)\n * @return Status of read operation (true = success)\n */\nint8_t I2Cdev::readBit(uint8_t devAddr, uint8_t regAddr, uint8_t bitNum, uint8_t *data, uint16_t timeout) {\n    uint8_t b;\n    uint8_t count = readByte(devAddr, regAddr, &b, timeout);\n    *data = b & (1 << bitNum);\n    return count;\n}\n\n/** Read a single bit from a 16-bit device register.\n * @param devAddr I2C slave device address\n * @param regAddr Register regAddr to read from\n * @param bitNum Bit position to read (0-15)\n * @param data Container for single bit value\n * @param timeout Optional read timeout in milliseconds (0 to disable, leave off to use default class value in I2Cdev::readTimeout)\n * @return Status of read operation (true = success)\n */\nint8_t I2Cdev::readBitW(uint8_t devAddr, uint8_t regAddr, uint8_t bitNum, uint16_t *data, uint16_t timeout) {\n    uint16_t b;\n    uint8_t count = readWord(devAddr, regAddr, &b, timeout);\n    *data = b & (1 << bitNum);\n    return count;\n}\n\n/** Read multiple bits from an 8-bit device register.\n * @param devAddr I2C slave device address\n * @param regAddr Register regAddr to read from\n * @param bitStart First bit position to read (0-7)\n * @param length Number of bits to read (not more than 8)\n * @param data Container for right-aligned value (i.e. '101' read from any bitStart position will equal 0x05)\n * @param timeout Optional read timeout in milliseconds (0 to disable, leave off to use default class value in I2Cdev::readTimeout)\n * @return Status of read operation (true = success)\n */\nint8_t I2Cdev::readBits(uint8_t devAddr, uint8_t regAddr, uint8_t bitStart, uint8_t length, uint8_t *data, uint16_t timeout) {\n    // 01101001 read byte\n    // 76543210 bit numbers\n    //    xxx   args: bitStart=4, length=3\n    //    010   masked\n    //   -> 010 shifted\n    uint8_t count, b;\n    if ((count = readByte(devAddr, regAddr, &b, timeout)) != 0) {\n        uint8_t mask = ((1 << length) - 1) << (bitStart - length + 1);\n        b &= mask;\n        b >>= (bitStart - length + 1);\n        *data = b;\n    }\n    return count;\n}\n\n/** Read multiple bits from a 16-bit device register.\n * @param devAddr I2C slave device address\n * @param regAddr Register regAddr to read from\n * @param bitStart First bit position to read (0-15)\n * @param length Number of bits to read (not more than 16)\n * @param data Container for right-aligned value (i.e. '101' read from any bitStart position will equal 0x05)\n * @param timeout Optional read timeout in milliseconds (0 to disable, leave off to use default class value in I2Cdev::readTimeout)\n * @return Status of read operation (1 = success, 0 = failure, -1 = timeout)\n */\nint8_t I2Cdev::readBitsW(uint8_t devAddr, uint8_t regAddr, uint8_t bitStart, uint8_t length, uint16_t *data, uint16_t timeout) {\n    // 1101011001101001 read byte\n    // fedcba9876543210 bit numbers\n    //    xxx           args: bitStart=12, length=3\n    //    010           masked\n    //           -> 010 shifted\n    uint8_t count;\n    uint16_t w;\n    if ((count = readWord(devAddr, regAddr, &w, timeout)) != 0) {\n        uint16_t mask = ((1 << length) - 1) << (bitStart - length + 1);\n        w &= mask;\n        w >>= (bitStart - length + 1);\n        *data = w;\n    }\n    return count;\n}\n\n/** Read single byte from an 8-bit device register.\n * @param devAddr I2C slave device address\n * @param regAddr Register regAddr to read from\n * @param data Container for byte value read from device\n * @param timeout Optional read timeout in milliseconds (0 to disable, leave off to use default class value in I2Cdev::readTimeout)\n * @return Status of read operation (true = success)\n */\nint8_t I2Cdev::readByte(uint8_t devAddr, uint8_t regAddr, uint8_t *data, uint16_t timeout) {\n    return readBytes(devAddr, regAddr, 1, data, timeout);\n}\n\n/** Read single word from a 16-bit device register.\n * @param devAddr I2C slave device address\n * @param regAddr Register regAddr to read from\n * @param data Container for word value read from device\n * @param timeout Optional read timeout in milliseconds (0 to disable, leave off to use default class value in I2Cdev::readTimeout)\n * @return Status of read operation (true = success)\n */\nint8_t I2Cdev::readWord(uint8_t devAddr, uint8_t regAddr, uint16_t *data, uint16_t timeout) {\n    return readWords(devAddr, regAddr, 1, data, timeout);\n}\n\n/** Read multiple bytes from an 8-bit device register.\n * @param devAddr I2C slave device address\n * @param regAddr First register regAddr to read from\n * @param length Number of bytes to read\n * @param data Buffer to store read data in\n * @param timeout Optional read timeout in milliseconds (0 to disable, leave off to use default class value in I2Cdev::readTimeout)\n * @return Number of bytes read (-1 indicates failure)\n */\nint8_t I2Cdev::readBytes(uint8_t devAddr, uint8_t regAddr, uint8_t length, uint8_t *data, uint16_t timeout) {\n    #ifdef I2CDEV_SERIAL_DEBUG\n        Serial.print(\"I2C (0x\");\n        Serial.print(devAddr, HEX);\n        Serial.print(\") reading \");\n        Serial.print(length, DEC);\n        Serial.print(\" bytes from 0x\");\n        Serial.print(regAddr, HEX);\n        Serial.print(\"...\");\n    #endif\n\n    int8_t count = 0;\n    uint32_t t1 = millis();\n\n    #if (I2CDEV_IMPLEMENTATION == I2CDEV_ARDUINO_WIRE)\n\n            // Arduino v1.0.1+, Wire library\n            // Adds official support for repeated start condition, yay!\n\n            // I2C/TWI subsystem uses internal buffer that breaks with large data requests\n            // so if user requests more than BUFFER_LENGTH bytes, we have to do it in\n            // smaller chunks instead of all at once\n            for (uint8_t k = 0; k < length; k += min(length, BUFFER_LENGTH)) {\n                Wire.beginTransmission(devAddr);\n                Wire.write(regAddr);\n                Wire.endTransmission();\n                Wire.beginTransmission(devAddr);\n                Wire.requestFrom(devAddr, (uint8_t)min(length - k, BUFFER_LENGTH));\n        \n                for (; Wire.available() && (timeout == 0 || millis() - t1 < timeout); count++) {\n                    data[count] = Wire.read();\n                    #ifdef I2CDEV_SERIAL_DEBUG\n                        Serial.print(data[count], HEX);\n                        if (count + 1 < length) Serial.print(\" \");\n                    #endif\n                }\n            }\n\n    #elif (I2CDEV_IMPLEMENTATION == I2CDEV_BUILTIN_FASTWIRE)\n\n            HAL_StatusTypeDef ret;\n\n            ret = HAL_I2C_Mem_Read(&I2cHandle, (uint16_t)(devAddr << 1), regAddr, I2C_MEMADD_SIZE_8BIT, data, length, timeout);\n\n            if( ret == HAL_OK )\n            {\n              count = length;\n            }\n            else\n            {\n                count = -1;\n            }\n    #endif\n\n    // check for timeout\n    if (timeout > 0 && millis() - t1 >= timeout && count < length) count = -1; // timeout\n\n    #ifdef I2CDEV_SERIAL_DEBUG\n        Serial.print(\". Done (\");\n        Serial.print(count, DEC);\n        Serial.println(\" read).\");\n    #endif\n\n    return count;\n}\n\n/** Read multiple words from a 16-bit device register.\n * @param devAddr I2C slave device address\n * @param regAddr First register regAddr to read from\n * @param length Number of words to read\n * @param data Buffer to store read data in\n * @param timeout Optional read timeout in milliseconds (0 to disable, leave off to use default class value in I2Cdev::readTimeout)\n * @return Number of words read (-1 indicates failure)\n */\nint8_t I2Cdev::readWords(uint8_t devAddr, uint8_t regAddr, uint8_t length, uint16_t *data, uint16_t timeout) {\n    #ifdef I2CDEV_SERIAL_DEBUG\n        Serial.print(\"I2C (0x\");\n        Serial.print(devAddr, HEX);\n        Serial.print(\") reading \");\n        Serial.print(length, DEC);\n        Serial.print(\" words from 0x\");\n        Serial.print(regAddr, HEX);\n        Serial.print(\"...\");\n    #endif\n\n    int8_t count = 0;\n    uint32_t t1 = millis();\n\n    #if (I2CDEV_IMPLEMENTATION == I2CDEV_ARDUINO_WIRE)\n\n            // Arduino v1.0.1+, Wire library\n            // Adds official support for repeated start condition, yay!\n\n            // I2C/TWI subsystem uses internal buffer that breaks with large data requests\n            // so if user requests more than BUFFER_LENGTH bytes, we have to do it in\n            // smaller chunks instead of all at once\n            for (uint8_t k = 0; k < length * 2; k += min(length * 2, BUFFER_LENGTH)) {\n                Wire.beginTransmission(devAddr);\n                Wire.write(regAddr);\n                Wire.endTransmission();\n                Wire.beginTransmission(devAddr);\n                Wire.requestFrom(devAddr, (uint8_t)(length * 2)); // length=words, this wants bytes\n        \n                bool msb = true; // starts with MSB, then LSB\n                for (; Wire.available() && count < length && (timeout == 0 || millis() - t1 < timeout);) {\n                    if (msb) {\n                        // first byte is bits 15-8 (MSb=15)\n                        data[count] = Wire.read() << 8;\n                    } else {\n                        // second byte is bits 7-0 (LSb=0)\n                        data[count] |= Wire.read();\n                        #ifdef I2CDEV_SERIAL_DEBUG\n                            Serial.print(data[count], HEX);\n                            if (count + 1 < length) Serial.print(\" \");\n                        #endif\n                        count++;\n                    }\n                    msb = !msb;\n                }\n        \n                Wire.endTransmission();\n            }\n    #elif (I2CDEV_IMPLEMENTATION == I2CDEV_BUILTIN_FASTWIRE)\n\n            HAL_StatusTypeDef ret;\n\n            ret = HAL_I2C_Mem_Read(&I2cHandle, (uint16_t)(devAddr << 1), regAddr, I2C_MEMADD_SIZE_16BIT, (uint8_t *)data, length, timeout);\n\n            if( ret == HAL_OK )\n            {\n              count = length;\n            }\n            else\n            {\n                count = -1;\n            }\n\n    #endif\n\n    if (timeout > 0 && millis() - t1 >= timeout && count < length) count = -1; // timeout\n\n    #ifdef I2CDEV_SERIAL_DEBUG\n        Serial.print(\". Done (\");\n        Serial.print(count, DEC);\n        Serial.println(\" read).\");\n    #endif\n    \n    return count;\n}\n\n/** write a single bit in an 8-bit device register.\n * @param devAddr I2C slave device address\n * @param regAddr Register regAddr to write to\n * @param bitNum Bit position to write (0-7)\n * @param value New bit value to write\n * @return Status of operation (true = success)\n */\nbool I2Cdev::writeBit(uint8_t devAddr, uint8_t regAddr, uint8_t bitNum, uint8_t data) {\n    uint8_t b;\n    readByte(devAddr, regAddr, &b);\n    b = (data != 0) ? (b | (1 << bitNum)) : (b & ~(1 << bitNum));\n    return writeByte(devAddr, regAddr, b);\n}\n\n/** write a single bit in a 16-bit device register.\n * @param devAddr I2C slave device address\n * @param regAddr Register regAddr to write to\n * @param bitNum Bit position to write (0-15)\n * @param value New bit value to write\n * @return Status of operation (true = success)\n */\nbool I2Cdev::writeBitW(uint8_t devAddr, uint8_t regAddr, uint8_t bitNum, uint16_t data) {\n    uint16_t w;\n    readWord(devAddr, regAddr, &w);\n    w = (data != 0) ? (w | (1 << bitNum)) : (w & ~(1 << bitNum));\n    return writeWord(devAddr, regAddr, w);\n}\n\n/** Write multiple bits in an 8-bit device register.\n * @param devAddr I2C slave device address\n * @param regAddr Register regAddr to write to\n * @param bitStart First bit position to write (0-7)\n * @param length Number of bits to write (not more than 8)\n * @param data Right-aligned value to write\n * @return Status of operation (true = success)\n */\nbool I2Cdev::writeBits(uint8_t devAddr, uint8_t regAddr, uint8_t bitStart, uint8_t length, uint8_t data) {\n    //      010 value to write\n    // 76543210 bit numbers\n    //    xxx   args: bitStart=4, length=3\n    // 00011100 mask byte\n    // 10101111 original value (sample)\n    // 10100011 original & ~mask\n    // 10101011 masked | value\n    uint8_t b;\n    if (readByte(devAddr, regAddr, &b) != 0) {\n        uint8_t mask = ((1 << length) - 1) << (bitStart - length + 1);\n        data <<= (bitStart - length + 1); // shift data into correct position\n        data &= mask; // zero all non-important bits in data\n        b &= ~(mask); // zero all important bits in existing byte\n        b |= data; // combine data with existing byte\n        return writeByte(devAddr, regAddr, b);\n    } else {\n        return false;\n    }\n}\n\n/** Write multiple bits in a 16-bit device register.\n * @param devAddr I2C slave device address\n * @param regAddr Register regAddr to write to\n * @param bitStart First bit position to write (0-15)\n * @param length Number of bits to write (not more than 16)\n * @param data Right-aligned value to write\n * @return Status of operation (true = success)\n */\nbool I2Cdev::writeBitsW(uint8_t devAddr, uint8_t regAddr, uint8_t bitStart, uint8_t length, uint16_t data) {\n    //              010 value to write\n    // fedcba9876543210 bit numbers\n    //    xxx           args: bitStart=12, length=3\n    // 0001110000000000 mask word\n    // 1010111110010110 original value (sample)\n    // 1010001110010110 original & ~mask\n    // 1010101110010110 masked | value\n    uint16_t w;\n    if (readWord(devAddr, regAddr, &w) != 0) {\n        uint16_t mask = ((1 << length) - 1) << (bitStart - length + 1);\n        data <<= (bitStart - length + 1); // shift data into correct position\n        data &= mask; // zero all non-important bits in data\n        w &= ~(mask); // zero all important bits in existing word\n        w |= data; // combine data with existing word\n        return writeWord(devAddr, regAddr, w);\n    } else {\n        return false;\n    }\n}\n\n/** Write single byte to an 8-bit device register.\n * @param devAddr I2C slave device address\n * @param regAddr Register address to write to\n * @param data New byte value to write\n * @return Status of operation (true = success)\n */\nbool I2Cdev::writeByte(uint8_t devAddr, uint8_t regAddr, uint8_t data) {\n    return writeBytes(devAddr, regAddr, 1, &data);\n}\n\n/** Write single word to a 16-bit device register.\n * @param devAddr I2C slave device address\n * @param regAddr Register address to write to\n * @param data New word value to write\n * @return Status of operation (true = success)\n */\nbool I2Cdev::writeWord(uint8_t devAddr, uint8_t regAddr, uint16_t data) {\n    return writeWords(devAddr, regAddr, 1, &data);\n}\n\n/** Write multiple bytes to an 8-bit device register.\n * @param devAddr I2C slave device address\n * @param regAddr First register address to write to\n * @param length Number of bytes to write\n * @param data Buffer to copy new data from\n * @return Status of operation (true = success)\n */\nbool I2Cdev::writeBytes(uint8_t devAddr, uint8_t regAddr, uint8_t length, uint8_t* data) {\n    #ifdef I2CDEV_SERIAL_DEBUG\n        Serial.print(\"I2C (0x\");\n        Serial.print(devAddr, HEX);\n        Serial.print(\") writing \");\n        Serial.print(length, DEC);\n        Serial.print(\" bytes to 0x\");\n        Serial.print(regAddr, HEX);\n        Serial.print(\"...\");\n    #endif\n    uint8_t status = 0;\n    #if (I2CDEV_IMPLEMENTATION == I2CDEV_ARDUINO_WIRE)\n        Wire.beginTransmission(devAddr);\n        Wire.write((uint8_t) regAddr); // send address\n\n    for (uint8_t i = 0; i < length; i++) {\n        #ifdef I2CDEV_SERIAL_DEBUG\n            Serial.print(data[i], HEX);\n            if (i + 1 < length) Serial.print(\" \");\n        #endif\n            Wire.write((uint8_t) data[i]);\n    }\n    status = Wire.endTransmission();\n\n    #ifdef I2CDEV_SERIAL_DEBUG\n        Serial.println(\". Done.\");\n    #endif\n  #else\n        HAL_StatusTypeDef ret;\n\n        ret = HAL_I2C_Mem_Write(&I2cHandle, (uint16_t)(devAddr << 1), regAddr, I2C_MEMADD_SIZE_8BIT, data, length, 100);\n\n        if( ret == HAL_OK )\n        {\n          status = 0;\n        }\n        else\n        {\n          status = 1;\n        }\n  #endif\n  return status == 0;\n}\n\n/** Write multiple words to a 16-bit device register.\n * @param devAddr I2C slave device address\n * @param regAddr First register address to write to\n * @param length Number of words to write\n * @param data Buffer to copy new data from\n * @return Status of operation (true = success)\n */\nbool I2Cdev::writeWords(uint8_t devAddr, uint8_t regAddr, uint8_t length, uint16_t* data) {\n    #ifdef I2CDEV_SERIAL_DEBUG\n        Serial.print(\"I2C (0x\");\n        Serial.print(devAddr, HEX);\n        Serial.print(\") writing \");\n        Serial.print(length, DEC);\n        Serial.print(\" words to 0x\");\n        Serial.print(regAddr, HEX);\n        Serial.print(\"...\");\n    #endif\n    uint8_t status = 0;\n    #if (I2CDEV_IMPLEMENTATION == I2CDEV_ARDUINO_WIRE)\n        Wire.beginTransmission(devAddr);\n        Wire.write(regAddr); // send address\n\n        for (uint8_t i = 0; i < length * 2; i++) {\n        #ifdef I2CDEV_SERIAL_DEBUG\n            Serial.print(data[i], HEX);\n            if (i + 1 < length) Serial.print(\" \");\n        #endif\n        Wire.write((uint8_t)(data[i] >> 8));    // send MSB\n        Wire.write((uint8_t)data[i++]);         // send LSB\n        }\n        status = Wire.endTransmission();\n        #ifdef I2CDEV_SERIAL_DEBUG\n        Serial.println(\". Done.\");\n        #endif\n    #else\n        HAL_StatusTypeDef ret;\n\n        ret = HAL_I2C_Mem_Write(&I2cHandle, (uint16_t)(devAddr << 1), regAddr, I2C_MEMADD_SIZE_16BIT, (uint8_t *)data, length, 100);\n\n        if( ret == HAL_OK )\n        {\n          status = 0;\n        }\n        else\n        {\n          status = 1;\n        }\n    #endif\n    return status == 0;\n}\n\n/** Default timeout value for read operations.\n * Set this to 0 to disable timeout detection.\n */\nuint16_t I2Cdev::readTimeout = I2CDEV_DEFAULT_READ_TIMEOUT;\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/I2Cdev/I2Cdev.h",
    "content": "// I2Cdev library collection - Main I2C device class header file\n// Abstracts bit and byte I2C R/W functions into a convenient class\n// 2013-06-05 by Jeff Rowberg <jeff@rowberg.net>\n//\n// Changelog:\n//      2015-10-30 - simondlevy : support i2c_t3 for Teensy3.1\n//      2013-05-06 - add Francesco Ferrara's Fastwire v0.24 implementation with small modifications\n//      2013-05-05 - fix issue with writing bit values to words (Sasquatch/Farzanegan)\n//      2012-06-09 - fix major issue with reading > 32 bytes at a time with Arduino Wire\n//                 - add compiler warnings when using outdated or IDE or limited I2Cdev implementation\n//      2011-11-01 - fix write*Bits mask calculation (thanks sasquatch @ Arduino forums)\n//      2011-10-03 - added automatic Arduino version detection for ease of use\n//      2011-10-02 - added Gene Knight's NBWire TwoWire class implementation with small modifications\n//      2011-08-31 - added support for Arduino 1.0 Wire library (methods are different from 0.x)\n//      2011-08-03 - added optional timeout parameter to read* methods to easily change from default\n//      2011-08-02 - added support for 16-bit registers\n//                 - fixed incorrect Doxygen comments on some methods\n//                 - added timeout value for read operations (thanks mem @ Arduino forums)\n//      2011-07-30 - changed read/write function structures to return success or byte counts\n//                 - made all methods static for multi-device memory savings\n//      2011-07-28 - initial release\n\n/* ============================================\nI2Cdev device library code is placed under the MIT license\nCopyright (c) 2013 Jeff Rowberg\n\nPermission is hereby granted, free of charge, to any person obtaining a copy\nof this software and associated documentation files (the \"Software\"), to deal\nin the Software without restriction, including without limitation the rights\nto use, copy, modify, merge, publish, distribute, sublicense, and/or sell\ncopies of the Software, and to permit persons to whom the Software is\nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in\nall copies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\nTHE SOFTWARE.\n===============================================\n*/\n\n#ifndef _I2CDEV_H_\n#define _I2CDEV_H_\n\n// -----------------------------------------------------------------------------\n// I2C interface implementation setting\n// -----------------------------------------------------------------------------\n#ifndef I2CDEV_IMPLEMENTATION\n//#define I2CDEV_IMPLEMENTATION       I2CDEV_ARDUINO_WIRE\n#define I2CDEV_IMPLEMENTATION       I2CDEV_BUILTIN_FASTWIRE\n#endif\n\n// comment this out if you are using a non-optimal IDE/implementation setting\n// but want the compiler to shut up about it\n#define I2CDEV_IMPLEMENTATION_WARNINGS\n\n// -----------------------------------------------------------------------------\n// I2C interface implementation options\n// -----------------------------------------------------------------------------\n#define I2CDEV_ARDUINO_WIRE         1 // Wire object from Arduino\n#define I2CDEV_BUILTIN_NBWIRE       2 // Tweaked Wire object from Gene Knight's NBWire project\n                                      // ^^^ NBWire implementation is still buggy w/some interrupts!\n#define I2CDEV_BUILTIN_FASTWIRE     3 // FastWire object from Francesco Ferrara's project\n#define I2CDEV_I2CMASTER_LIBRARY    4 // I2C object from DSSCircuits I2C-Master Library at https://github.com/DSSCircuits/I2C-Master-Library\n\n// -----------------------------------------------------------------------------\n// Arduino-style \"Serial.print\" debug constant (uncomment to enable)\n// -----------------------------------------------------------------------------\n//#define I2CDEV_SERIAL_DEBUG\n\n#ifdef ARDUINO\n    #include \"Arduino.h\"\n    #if I2CDEV_IMPLEMENTATION == I2CDEV_ARDUINO_WIRE\n    #include <Wire.h>\n    #endif\n#endif\n\n\n\n// 1000ms default read timeout (modify with \"I2Cdev::readTimeout = [ms];\")\n#define I2CDEV_DEFAULT_READ_TIMEOUT     1000\n\nclass I2Cdev {\n    public:\n        I2Cdev();\n        static void begin( uint32_t freq );\n\n        static int8_t readBit(uint8_t devAddr, uint8_t regAddr, uint8_t bitNum, uint8_t *data, uint16_t timeout=I2Cdev::readTimeout);\n        static int8_t readBitW(uint8_t devAddr, uint8_t regAddr, uint8_t bitNum, uint16_t *data, uint16_t timeout=I2Cdev::readTimeout);\n        static int8_t readBits(uint8_t devAddr, uint8_t regAddr, uint8_t bitStart, uint8_t length, uint8_t *data, uint16_t timeout=I2Cdev::readTimeout);\n        static int8_t readBitsW(uint8_t devAddr, uint8_t regAddr, uint8_t bitStart, uint8_t length, uint16_t *data, uint16_t timeout=I2Cdev::readTimeout);\n        static int8_t readByte(uint8_t devAddr, uint8_t regAddr, uint8_t *data, uint16_t timeout=I2Cdev::readTimeout);\n        static int8_t readWord(uint8_t devAddr, uint8_t regAddr, uint16_t *data, uint16_t timeout=I2Cdev::readTimeout);\n        static int8_t readBytes(uint8_t devAddr, uint8_t regAddr, uint8_t length, uint8_t *data, uint16_t timeout=I2Cdev::readTimeout);\n        static int8_t readWords(uint8_t devAddr, uint8_t regAddr, uint8_t length, uint16_t *data, uint16_t timeout=I2Cdev::readTimeout);\n\n        static bool writeBit(uint8_t devAddr, uint8_t regAddr, uint8_t bitNum, uint8_t data);\n        static bool writeBitW(uint8_t devAddr, uint8_t regAddr, uint8_t bitNum, uint16_t data);\n        static bool writeBits(uint8_t devAddr, uint8_t regAddr, uint8_t bitStart, uint8_t length, uint8_t data);\n        static bool writeBitsW(uint8_t devAddr, uint8_t regAddr, uint8_t bitStart, uint8_t length, uint16_t data);\n        static bool writeByte(uint8_t devAddr, uint8_t regAddr, uint8_t data);\n        static bool writeWord(uint8_t devAddr, uint8_t regAddr, uint16_t data);\n        static bool writeBytes(uint8_t devAddr, uint8_t regAddr, uint8_t length, uint8_t *data);\n        static bool writeWords(uint8_t devAddr, uint8_t regAddr, uint8_t length, uint16_t *data);\n\n        static uint16_t readTimeout;\n};\n\n#if I2CDEV_IMPLEMENTATION == I2CDEV_BUILTIN_FASTWIRE\n\n#endif\n\n#endif /* _I2CDEV_H_ */\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/I2Cdev/keywords.txt",
    "content": "#######################################\n# Syntax Coloring Map For I2Cdev\n#######################################\n\n#######################################\n# Datatypes (KEYWORD1)\n#######################################\nI2Cdev\tKEYWORD1\n\n#######################################\n# Methods and Functions (KEYWORD2)\n#######################################\n\nreadBit\tKEYWORD2\nreadBitW\tKEYWORD2\nreadBits\tKEYWORD2\nreadBitsW\tKEYWORD2\nreadByte\tKEYWORD2\nreadBytes\tKEYWORD2\nreadWord\tKEYWORD2\nreadWords\tKEYWORD2\nwriteBit\tKEYWORD2\nwriteBitW\tKEYWORD2\nwriteBits\tKEYWORD2\nwriteBitsW\tKEYWORD2\nwriteByte\tKEYWORD2\nwriteBytes\tKEYWORD2\nwriteWord\tKEYWORD2\nwriteWords\tKEYWORD2\n\n#######################################\n# Instances (KEYWORD2)\n#######################################\n\n#######################################\n# Constants (LITERAL1)\n#######################################\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/I2Cdev/library.json",
    "content": "{\n  \"name\": \"I2Cdevlib-Core\",\n  \"keywords\": \"i2cdevlib, i2c\",\n  \"description\": \"The I2C Device Library (I2Cdevlib) is a collection of uniform and well-documented classes to provide simple and intuitive interfaces to I2C devices.\",\n  \"include\": \"Arduino/I2Cdev\",\n  \"repository\":\n  {\n    \"type\": \"git\",\n    \"url\": \"https://github.com/jrowberg/i2cdevlib.git\"\n  },\n  \"frameworks\": \"arduino\",\n  \"platforms\": \"atmelavr\"\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/IMU/Define.h",
    "content": "//----------------------------------------------------------------------------\r\n//    프로그램명 \t: DEFINE\r\n//\r\n//    만든이     \t: Made by Baram ( chcbaram@paran.com )\r\n//\r\n//    날  짜     : \r\n//    \r\n//    최종 수정  \t: \r\n//\r\n//    MPU_Type\t: \r\n//\r\n//    파일명     \t: DEFINE.h\r\n//----------------------------------------------------------------------------\r\n#ifndef _DEFINE_H_\r\n#define _DEFINE_H_\r\n\r\n#include <inttypes.h>\r\n#include <Arduino.h> \r\n\r\n\r\n\r\n#define ROLL\t\t0\r\n#define PITCH\t\t1\r\n#define YAW\t\t\t2\r\n\r\n\r\n\r\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/IMU/ICM20648.cpp",
    "content": "#include <Arduino.h>\n#include <SPI.h>\n#include \"ICM20648.h\"\n\n\n\n\n//#define SPI_CS_PIN          BDPIN_SPI_CS_IMU\n                            \n#define ICM20648_ADDRESS    0x68\n#define MPU_CALI_COUNT      512\n\n\n#define ACC_ORIENTATION(X, Y, Z)  {accADC[PITCH]  =  Y; accADC[ROLL]  =  X; accADC[YAW]  =   Z;}\n#define GYRO_ORIENTATION(X, Y, Z) {gyroADC[PITCH] =  Y; gyroADC[ROLL] =  X; gyroADC[YAW] =   Z;}\n\n\n\n\n\n\n\ncICM20648::cICM20648()\n{\n\tcalibratingG = 0;\n\tcalibratingA = 0;\n  calibratingM = 0;\n  bConnected   = false;\n}\n\nvoid cICM20648::selectBank(uint8_t bank)\n{\n  digitalWrite( BDPIN_SPI_CS_IMU, LOW);\n\n  /* clear R/W bit - write, send the address */\n  MPU_SPI.write((uint8_t)ICM20648_REG_BANK_SEL);\n  MPU_SPI.write((uint8_t)(bank << 4));\n \n  digitalWrite( BDPIN_SPI_CS_IMU, HIGH);\n}\n\nvoid cICM20648::spiRead(uint16_t addr, uint8_t *p_data, uint32_t length)\n{\n  uint8_t reg_addr;\n  uint8_t bank;\n \n  reg_addr = (uint8_t) (addr & 0x7F);\n  bank = (uint8_t) (addr >> 7);\n\n  selectBank(bank);\n\n  digitalWrite( BDPIN_SPI_CS_IMU, LOW);\n \n  MPU_SPI.transfer(0x80 | reg_addr);\n  MPU_SPI.transfer(NULL, (void *)p_data, (size_t)length);\n \n  digitalWrite( BDPIN_SPI_CS_IMU, HIGH);\n}\n\nuint8_t cICM20648::spiReadByte(uint16_t addr)\n{\n  uint8_t data;\n\n  spiRead(addr, &data, 1);\n\n\treturn data;\n}\n\nvoid cICM20648::spiWriteByte(uint16_t addr, uint8_t data)\n{\n  uint8_t reg_addr;\n  uint8_t bank;\n \n  reg_addr = (uint8_t) (addr & 0x7F);\n  bank = (uint8_t) (addr >> 7);\n \n  selectBank(bank);\n \n  digitalWrite( BDPIN_SPI_CS_IMU, LOW); \n\n  MPU_SPI.transfer(reg_addr & 0x7F);\n  MPU_SPI.transfer(data);\n \n  digitalWrite( BDPIN_SPI_CS_IMU, HIGH); \n}\n\nbool cICM20648::begin()\n{\n  uint8_t data;\n\n  pinMode( BDPIN_SPI_CS_IMU, OUTPUT );\n\n  MPU_SPI.begin();\n  MPU_SPI.setDataMode( SPI_MODE3 );\n  MPU_SPI.setBitOrder( MSBFIRST );\n  MPU_SPI.setClockDivider( SPI_CLOCK_DIV128 ); // 108Mhz/128 = 0.8MHz\n  digitalWrite(BDPIN_SPI_CS_IMU, HIGH);\n  delay( 100 );\n\n  // Disable I2C interface, use SPI\n  spiWriteByte(ICM20648_REG_USER_CTRL, ICM20648_BIT_I2C_IF_DIS);\n\n  data = spiReadByte(ICM20648_REG_WHO_AM_I);\n\n  if(data == ICM20648_DEVICE_ID)\n  {\n    bConnected = true;\n    init();\n    gyro_init();\n    acc_init();\n    mag_init();\n\n    MPU_SPI.setClockDivider( SPI_CLOCK_DIV4 ); // 6.5MHz\n  }\n\n\n\n  return bConnected;\n}\n\nvoid cICM20648::init( void )\n{\n  uint8_t state;\n  uint8_t data;\n  uint8_t response[3] = {0, 0, 0};\n\n\n  //ICM20648 Reset\n  spiWriteByte(ICM20648_REG_PWR_MGMT_1, ICM20648_BIT_H_RESET);\n\tdelay(100);\n\n\t//ICM20648 Set Clock Source\n  // Auto selects the best available clock source  PLL if ready, else use the Internal oscillator\n  spiWriteByte(ICM20648_REG_PWR_MGMT_1, ICM20648_BIT_CLK_PLL); \n  // PLL startup time - maybe it is too long but better be on the safe side, no spec in the datasheet */\n  delay(30);  \n\n\t//ICM20648 Set Interrupt\n  spiWriteByte(ICM20648_REG_INT_PIN_CFG, ICM20648_BIT_INT_ACTL | ICM20648_BIT_INT_OPEN);\n\tdelay(1);\n\n\t//ICM20648 Set Sensors\n  spiWriteByte(ICM20648_REG_PWR_MGMT_2, 0x00); // Acc/Gyro Enable\n\tdelay(1);\n\n\t//ICM20648 Set SampleRate\n\t//SAMPLE_RATE = Internal_Sample_Rate / (1 + SMPLRT_DIV)\n  spiWriteByte(ICM20648_REG_GYRO_SMPLRT_DIV, 0x00); // \n\tdelay(1);\n\n\t//ICM20648 Gyro \n\n\t// Set Full Scale Gyro Range\n  data = ICM20648_GYRO_FULLSCALE_2000DPS;\n  // Set Gyro DLPF\n  data |= ICM20648_GYRO_BW_51HZ;\n  spiWriteByte(ICM20648_REG_GYRO_CONFIG_1, data);\n\tdelay(1);\n\n\t//ICM20648 Accel\n\t\n  // Set Full Scale Accel Range\n  data = ICM20648_ACCEL_FULLSCALE_2G;\n  // Set Accel DLPF\n  data |= ICM20648_ACCEL_BW_50HZ;\n  spiWriteByte(ICM20648_REG_ACCEL_CONFIG, data);\n\tdelay(1);\n}\n\nvoid cICM20648::gyro_init( void )\n{\n\tuint8_t i;\n\n\n\tfor( i=0; i<3; i++ )\n\t{\n    gyroADC[i]  = 0;\n\t\tgyroZero[i] = 0;\n\t\tgyroRAW[i]  = 0;\n\t}\n\n\tcalibratingG = MPU_CALI_COUNT;\n}\n\nvoid cICM20648::gyro_get_adc( void )\n{\n\tint16_t x = 0;\n\tint16_t y = 0;\n\tint16_t z = 0;\n\n  uint8_t rawADC[6];\n\n  if( bConnected == true )\n  {\n    spiRead(ICM20648_REG_GYRO_XOUT_H_SH, &rawADC[0], 6);\n\n \t\tx = (((int16_t)rawADC[0]) << 8) | rawADC[1];\n  \ty = (((int16_t)rawADC[2]) << 8) | rawADC[3];\n  \tz = (((int16_t)rawADC[4]) << 8) | rawADC[5];\n\n  \tgyroRAW[0] = x;\n  \tgyroRAW[1] = y;\n  \tgyroRAW[2] = z;\n\n  \tGYRO_ORIENTATION( x, y,z );\n  }\n\n  gyro_common();\n}\n\nvoid cICM20648::gyro_cali_start()\n{\n\tcalibratingG = MPU_CALI_COUNT;\n}\n\nvoid cICM20648::acc_init( void )\n{\n  uint8_t i;\n\n\n  for( i=0; i<3; i++ )\n  {\n    accADC[i]   = 0;\n\t\taccZero[i]  = 0;\n    accRAW[i]   = 0;\n  }\n}\n\nvoid cICM20648::acc_get_adc( void )\n{\n\tint16_t x = 0;\n\tint16_t y = 0;\n\tint16_t z = 0;\n  uint8_t rawADC[6];\n\n  if( bConnected == true )\n  {    \n    spiRead(ICM20648_REG_ACCEL_XOUT_H_SH, &rawADC[0], 6);\n\n    x = (((int16_t)rawADC[0]) << 8) | rawADC[1];\n    y = (((int16_t)rawADC[2]) << 8) | rawADC[3];\n    z = (((int16_t)rawADC[4]) << 8) | rawADC[5];\n\n    accRAW[0] = x;\n    accRAW[1] = y;\n    accRAW[2] = z;\n    \n\t\tACC_ORIENTATION( x,\ty, z );\n\t}\n\n\tacc_common();\n}\n\nvoid cICM20648::gyro_common()\n{\n\tstatic int16_t previousGyroADC[3];\n\tstatic int32_t g[3];\n\tuint8_t axis, tilt=0;\n\n\tmemset(previousGyroADC, 0, 3);\n\n\tif (calibratingG>0)\n\t{\n\t\tfor (axis = 0; axis < 3; axis++)\n\t\t{\n\t\t\tif (calibratingG == MPU_CALI_COUNT)\n\t\t\t{ // Reset g[axis] at start of calibration\n\t\t\t\tg[axis]=0;\n\t\t\t\tpreviousGyroADC[axis] = gyroADC[axis];\n\t\t\t}\n\t\t\tif (calibratingG % 10 == 0)\n\t\t\t{\n\t\t\t\t//if(abs(gyroADC[axis] - previousGyroADC[axis]) > 8) tilt=1;\n\n\t\t\t\tpreviousGyroADC[axis] = gyroADC[axis];\n\t\t\t}\n\t\t\tg[axis] += gyroADC[axis]; // Sum up 512 readings\n\t\t\tgyroZero[axis]=g[axis]>>9;\n\n\t\t\tif (calibratingG == 1)\n\t\t\t{\n\t\t\t\t//SET_ALARM_BUZZER(ALRM_FAC_CONFIRM, ALRM_LVL_CONFIRM_ELSE);\n\t\t\t}\n\t\t}\n\n\t\tif(tilt)\n\t\t{\n\t\t\tcalibratingG=1000;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tcalibratingG--;\n\t\t}\n\t\treturn;\n\t}\n\n\n  for (axis = 0; axis < 3; axis++)\n  {\n    gyroADC[axis] -= gyroZero[axis];\n\n    //anti gyro glitch, limit the variation between two consecutive readings\n    //gyroADC[axis] = constrain(gyroADC[axis],previousGyroADC[axis]-800,previousGyroADC[axis]+800);\n    previousGyroADC[axis] = gyroADC[axis];\n  }\n}\n\nvoid cICM20648::acc_common()\n{\n\tstatic int32_t a[3];\n\n\tif (calibratingA>0)\n\t{\n\t\tcalibratingA--;\n\t\tfor (uint8_t axis = 0; axis < 3; axis++)\n\t\t{\n\t\t\tif (calibratingA ==(MPU_CALI_COUNT-1)) a[axis]=0;  // Reset a[axis] at start of calibration\n\t\t\ta[axis] += accADC[axis];             // Sum up 512 readings\n\t\t\taccZero[axis] = a[axis]>>9;          // Calculate average, only the last itteration where (calibratingA == 0) is relevant\n\t\t}\n\t\tif (calibratingA == 0)\n\t\t{\n\t\t\t//accZero[YAW] -= ACC_1G;\n      accZero[YAW] = 0;\n\t\t}\n\t}\n\n  accADC[ROLL]  -=  accZero[ROLL] ;\n  accADC[PITCH] -=  accZero[PITCH];\n  accADC[YAW]   -=  accZero[YAW] ;\n}\n\nvoid cICM20648::mag_init( void )\n{\n  uint8_t i;\n\n  for( i=0; i<3; i++ )\n  {\n    magADC[i]   = 0;\n\t\tmagZero[i]  = 0;\n    magRAW[i]   = 0;\n  }\n}\n\nvoid cICM20648::mag_get_adc( void )\n{\n  return;\n}\n\nvoid cICM20648::mag_common()\n{\n  magADC[0] = magRAW[0];\n  magADC[1] = magRAW[1];\n  magADC[2] = magRAW[2];\n}\n\nvoid cICM20648::acc_cali_start()\n{\n\tcalibratingA = MPU_CALI_COUNT;\n}\n\nbool cICM20648::acc_cali_get_done()\n{\n\tif( calibratingA == 0 ) return true;\n\telse                    return false;\n}\n\nbool cICM20648::gyro_cali_get_done()\n{\n\tif( calibratingG == 0 ) return true;\n\telse                    return false;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/IMU/ICM20648.h",
    "content": "#ifndef _ICM20648_H_\n#define _ICM20648_H_\n\n#include <inttypes.h>\n#include <Arduino.h>\n\n#include \"Define.h\"\n#include \"ICM20648_REGS.h\"\n\n\n\n\n#define MPU_SPI   SPI_IMU\n\n\n\nclass cICM20648\n{\n\npublic:\n  bool     bConnected;\n\n\tint16_t  gyroADC[3];\n\tint16_t  gyroRAW[3];\n\tint16_t  gyroZero[3];\n\n\tint16_t  accADC[3];\n\tint16_t  accRAW[3];\n\tint16_t  accZero[3];\n\n  int16_t  magADC[3];\n\tint16_t  magRAW[3];\n\tint16_t  magZero[3];\n\n\tint16_t  gyroData[3];\n\tint16_t  accSmooth[3];\n\n\tuint16_t calibratingG;\n\tuint16_t calibratingA;\n  uint16_t calibratingM;\n\n\n  int16_t AK8963_ASA[3];\n\n\npublic:\n\tcICM20648();\n\n  bool begin( void );\n  void init( void );\n\tvoid gyro_init( void );\n\tvoid gyro_get_adc( void );\n\tvoid gyro_common();\n\tvoid gyro_cali_start();\n\tbool gyro_cali_get_done();\n\n\tvoid acc_init( void );\n\tvoid acc_get_adc( void );\n\tvoid acc_common();\n\tvoid acc_cali_start();\n\tbool acc_cali_get_done();\n\n  void mag_init( void );\n\tvoid mag_get_adc( void );\n\tvoid mag_common();\n\tvoid mag_cali_start();\n\tbool mag_cali_get_done();\n\n\nprivate:\n  void selectBank(uint8_t bank);\n  void spiRead(uint16_t addr, uint8_t *p_data, uint32_t length);\n  uint8_t spiReadByte(uint16_t addr);\n  void spiWriteByte(uint16_t addr, uint8_t data);\n\n};\n\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/IMU/ICM20648_REGS.h",
    "content": "/***************************************************************************//**\n * @file ICM20648.cpp\n *******************************************************************************\n * @section License\n * <b>(C) Copyright 2017 Silicon Labs, http://www.silabs.com</b>\n *******************************************************************************\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\"); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n ******************************************************************************/\n\n\n#ifndef _ICM20648_REGS_H\n#define _ICM20648_REGS_H\n\n\n/**************************************************************************//**\n* @name Error Codes\n* @{\n******************************************************************************/\n#define ICM20648_OK                                 0x0000   /**< No errors         */\n#define ICM20648_ERROR_INVALID_DEVICE_ID            0x0001   /**< Invalid device ID */\n/**@}*/\n \n/**************************************************************************//**\n* @name ICM20648 register banks\n* @{\n******************************************************************************/\n#define ICM20648_BANK_0                  (0 << 7)     /**< Register bank 0 */\n#define ICM20648_BANK_1                  (1 << 7)     /**< Register bank 1 */\n#define ICM20648_BANK_2                  (2 << 7)     /**< Register bank 2 */\n#define ICM20648_BANK_3                  (3 << 7)     /**< Register bank 3 */\n/**@}*/\n \n/**************************************************************************//**\n* @name Register and associated bit definitions\n* @{\n******************************************************************************/\n/***********************/\n/* Bank 0 register map */\n/***********************/\n#define ICM20648_REG_WHO_AM_I            (ICM20648_BANK_0 | 0x00)    /**< Device ID register                                     */\n \n#define ICM20648_REG_USER_CTRL           (ICM20648_BANK_0 | 0x03)    /**< User control register                                  */\n#define ICM20648_BIT_DMP_EN              0x80                        /**< DMP enable bit                                         */\n#define ICM20648_BIT_FIFO_EN             0x40                        /**< FIFO enable bit                                        */\n#define ICM20648_BIT_I2C_MST_EN          0x20                        /**< I2C master I/F enable bit                              */\n#define ICM20648_BIT_I2C_IF_DIS          0x10                        /**< Disable I2C, enable SPI bit                            */\n#define ICM20648_BIT_DMP_RST             0x08                        /**< DMP module reset bit                                   */\n#define ICM20648_BIT_DIAMOND_DMP_RST     0x04                        /**< SRAM module reset bit                                  */\n \n#define ICM20648_REG_LP_CONFIG           (ICM20648_BANK_0 | 0x05)    /**< Low Power mode config register                         */\n#define ICM20648_BIT_I2C_MST_CYCLE       0x40                        /**< I2C master cycle mode enable                           */\n#define ICM20648_BIT_ACCEL_CYCLE         0x20                        /**< Accelerometer cycle mode enable                        */\n#define ICM20648_BIT_GYRO_CYCLE          0x10                        /**< Gyroscope cycle mode enable                            */\n \n#define ICM20648_REG_PWR_MGMT_1          (ICM20648_BANK_0 | 0x06)    /**< Power Management 1 register                            */\n#define ICM20648_BIT_H_RESET             0x80                        /**< Device reset bit                                       */\n#define ICM20648_BIT_SLEEP               0x40                        /**< Sleep mode enable bit                                  */\n#define ICM20648_BIT_LP_EN               0x20                        /**< Low Power feature enable bit                           */\n#define ICM20648_BIT_TEMP_DIS            0x08                        /**< Temperature sensor disable bit                         */\n#define ICM20648_BIT_CLK_PLL             0x01                        /**< Auto clock source selection setting                    */\n \n#define ICM20648_REG_PWR_MGMT_2          (ICM20648_BANK_0 | 0x07)    /**< Power Management 2 register                            */\n#define ICM20648_BIT_PWR_ACCEL_STBY      0x38                        /**< Disable accelerometer                                  */\n#define ICM20648_BIT_PWR_GYRO_STBY       0x07                        /**< Disable gyroscope                                      */\n#define ICM20648_BIT_PWR_ALL_OFF         0x7F                        /**< Disable both accel and gyro                            */\n \n#define ICM20648_REG_INT_PIN_CFG         (ICM20648_BANK_0 | 0x0F)    /**< Interrupt Pin Configuration register                   */\n#define ICM20648_BIT_INT_ACTL            0x80                        /**< Active low setting bit                                 */\n#define ICM20648_BIT_INT_OPEN            0x40                        /**< Open collector onfiguration bit                        */\n#define ICM20648_BIT_INT_LATCH_EN        0x20                        /**< Latch enable bit                                       */\n \n#define ICM20648_REG_INT_ENABLE          (ICM20648_BANK_0 | 0x10)    /**< Interrupt Enable register                              */\n#define ICM20648_BIT_WOM_INT_EN          0x08                        /**< Wake-up On Motion enable bit                           */\n \n#define ICM20648_REG_INT_ENABLE_1        (ICM20648_BANK_0 | 0x11)    /**< Interrupt Enable 1 register                            */\n#define ICM20648_BIT_RAW_DATA_0_RDY_EN   0x01                        /**< Raw data ready interrupt enable bit                    */\n \n#define ICM20648_REG_INT_ENABLE_2        (ICM20648_BANK_0 | 0x12)    /**< Interrupt Enable 2 register                            */\n#define ICM20648_BIT_FIFO_OVERFLOW_EN_0  0x01                        /**< FIFO overflow interrupt enable bit                     */\n \n#define ICM20648_REG_INT_ENABLE_3        (ICM20648_BANK_0 | 0x13)    /**< Interrupt Enable 2 register                            */\n \n#define ICM20648_REG_INT_STATUS          (ICM20648_BANK_0 | 0x19)    /**< Interrupt Status register                              */\n#define ICM20648_BIT_WOM_INT             0x08                        /**< Wake-up on motion interrupt occured bit                */\n#define ICM20648_BIT_PLL_RDY             0x04                        /**< PLL ready interrupt occured bit                        */\n \n#define ICM20648_REG_INT_STATUS_1        (ICM20648_BANK_0 | 0x1A)    /**< Interrupt Status 1 register                            */\n#define ICM20648_BIT_RAW_DATA_0_RDY_INT  0x01                        /**< Raw data ready interrupt occured bit                   */\n \n#define ICM20648_REG_INT_STATUS_2        (ICM20648_BANK_0 | 0x1B)    /**< Interrupt Status 2 register                            */\n \n#define ICM20648_REG_ACCEL_XOUT_H_SH     (ICM20648_BANK_0 | 0x2D)    /**< Accelerometer X-axis data high byte                    */\n#define ICM20648_REG_ACCEL_XOUT_L_SH     (ICM20648_BANK_0 | 0x2E)    /**< Accelerometer X-axis data low byte                     */\n#define ICM20648_REG_ACCEL_YOUT_H_SH     (ICM20648_BANK_0 | 0x2F)    /**< Accelerometer Y-axis data high byte                    */\n#define ICM20648_REG_ACCEL_YOUT_L_SH     (ICM20648_BANK_0 | 0x30)    /**< Accelerometer Y-axis data low byte                     */\n#define ICM20648_REG_ACCEL_ZOUT_H_SH     (ICM20648_BANK_0 | 0x31)    /**< Accelerometer Z-axis data high byte                    */\n#define ICM20648_REG_ACCEL_ZOUT_L_SH     (ICM20648_BANK_0 | 0x32)    /**< Accelerometer Z-axis data low byte                     */\n \n#define ICM20648_REG_GYRO_XOUT_H_SH      (ICM20648_BANK_0 | 0x33)    /**< Gyroscope X-axis data high byte                        */\n#define ICM20648_REG_GYRO_XOUT_L_SH      (ICM20648_BANK_0 | 0x34)    /**< Gyroscope X-axis data low byte                         */\n#define ICM20648_REG_GYRO_YOUT_H_SH      (ICM20648_BANK_0 | 0x35)    /**< Gyroscope Y-axis data high byte                        */\n#define ICM20648_REG_GYRO_YOUT_L_SH      (ICM20648_BANK_0 | 0x36)    /**< Gyroscope Y-axis data low byte                         */\n#define ICM20648_REG_GYRO_ZOUT_H_SH      (ICM20648_BANK_0 | 0x37)    /**< Gyroscope Z-axis data high byte                        */\n#define ICM20648_REG_GYRO_ZOUT_L_SH      (ICM20648_BANK_0 | 0x38)    /**< Gyroscope Z-axis data low byte                         */\n \n#define ICM20648_REG_TEMPERATURE_H       (ICM20648_BANK_0 | 0x39)    /**< Temperature data high byte                             */\n#define ICM20648_REG_TEMPERATURE_L       (ICM20648_BANK_0 | 0x3A)    /**< Temperature data low byte                              */\n#define ICM20648_REG_TEMP_CONFIG         (ICM20648_BANK_0 | 0x53)    /**< Temperature Configuration register                     */\n \n#define ICM20648_REG_FIFO_EN_1           (ICM20648_BANK_0 | 0x66)    /**< FIFO Enable 1 register                                 */\n \n#define ICM20648_REG_FIFO_EN_2           (ICM20648_BANK_0 | 0x67)    /**< FIFO Enable 2 register                                 */\n#define ICM20648_BIT_ACCEL_FIFO_EN       0x10                        /**< Enable writing acceleration data to FIFO bit           */\n#define ICM20648_BITS_GYRO_FIFO_EN       0x0E                        /**< Enable writing gyroscope data to FIFO bit              */\n \n#define ICM20648_REG_FIFO_RST            (ICM20648_BANK_0 | 0x68)    /**< FIFO Reset register                                    */\n#define ICM20648_REG_FIFO_MODE           (ICM20648_BANK_0 | 0x69)    /**< FIFO Mode register                                     */\n \n#define ICM20648_REG_FIFO_COUNT_H        (ICM20648_BANK_0 | 0x70)    /**< FIFO data count high byte                              */\n#define ICM20648_REG_FIFO_COUNT_L        (ICM20648_BANK_0 | 0x71)    /**< FIFO data count low byte                               */\n#define ICM20648_REG_FIFO_R_W            (ICM20648_BANK_0 | 0x72)    /**< FIFO Read/Write register                               */\n \n#define ICM20648_REG_DATA_RDY_STATUS     (ICM20648_BANK_0 | 0x74)    /**< Data Ready Status register                             */\n#define ICM20648_BIT_RAW_DATA_0_RDY      0x01                        /**< Raw Data Ready bit                                     */\n \n#define ICM20648_REG_FIFO_CFG            (ICM20648_BANK_0 | 0x76)    /**< FIFO Configuration register                            */\n#define ICM20648_BIT_MULTI_FIFO_CFG      0x01                        /**< Interrupt status for each sensor is required           */\n#define ICM20648_BIT_SINGLE_FIFO_CFG     0x00                        /**< Interrupt status for only a single sensor is required  */\n \n/***********************/\n/* Bank 1 register map */\n/***********************/\n#define ICM20648_REG_XA_OFFSET_H         (ICM20648_BANK_1 | 0x14)    /**< Acceleration sensor X-axis offset cancellation high byte  */\n#define ICM20648_REG_XA_OFFSET_L         (ICM20648_BANK_1 | 0x15)    /**< Acceleration sensor X-axis offset cancellation low byte   */\n#define ICM20648_REG_YA_OFFSET_H         (ICM20648_BANK_1 | 0x17)    /**< Acceleration sensor Y-axis offset cancellation high byte  */\n#define ICM20648_REG_YA_OFFSET_L         (ICM20648_BANK_1 | 0x18)    /**< Acceleration sensor Y-axis offset cancellation low byte   */\n#define ICM20648_REG_ZA_OFFSET_H         (ICM20648_BANK_1 | 0x1A)    /**< Acceleration sensor Z-axis offset cancellation high byte  */\n#define ICM20648_REG_ZA_OFFSET_L         (ICM20648_BANK_1 | 0x1B)    /**< Acceleration sensor Z-axis offset cancellation low byte   */\n \n#define ICM20648_REG_TIMEBASE_CORR_PLL   (ICM20648_BANK_1 | 0x28)    /**< PLL Timebase Correction register                          */\n \n/***********************/\n/* Bank 2 register map */\n/***********************/\n#define ICM20648_REG_GYRO_SMPLRT_DIV     (ICM20648_BANK_2 | 0x00)    /**< Gyroscope Sample Rate Divider regiser      */\n \n#define ICM20648_REG_GYRO_CONFIG_1       (ICM20648_BANK_2 | 0x01)    /**< Gyroscope Configuration 1 register         */\n#define ICM20648_BIT_GYRO_FCHOICE        0x01                        /**< Gyro Digital Low-Pass Filter enable bit    */\n#define ICM20648_SHIFT_GYRO_FS_SEL       1                           /**< Gyro Full Scale Select bit shift           */\n#define ICM20648_SHIFT_GYRO_DLPCFG       3                           /**< Gyro DLPF Config bit shift                 */\n#define ICM20648_MASK_GYRO_FULLSCALE     0x06                        /**< Gyro Full Scale Select bitmask             */\n#define ICM20648_MASK_GYRO_BW            0x39                        /**< Gyro Bandwidth Select bitmask              */\n#define ICM20648_GYRO_FULLSCALE_250DPS   (0x00 << ICM20648_SHIFT_GYRO_FS_SEL)    /**< Gyro Full Scale = 250 deg/sec  */\n#define ICM20648_GYRO_FULLSCALE_500DPS   (0x01 << ICM20648_SHIFT_GYRO_FS_SEL)    /**< Gyro Full Scale = 500 deg/sec  */\n#define ICM20648_GYRO_FULLSCALE_1000DPS  (0x02 << ICM20648_SHIFT_GYRO_FS_SEL)    /**< Gyro Full Scale = 1000 deg/sec */\n#define ICM20648_GYRO_FULLSCALE_2000DPS  (0x03 << ICM20648_SHIFT_GYRO_FS_SEL)    /**< Gyro Full Scale = 2000 deg/sec */\n#define ICM20648_GYRO_BW_12100HZ         (0x00 << ICM20648_SHIFT_GYRO_DLPCFG)                                     /**< Gyro Bandwidth = 12100 Hz */\n#define ICM20648_GYRO_BW_360HZ           ( (0x07 << ICM20648_SHIFT_GYRO_DLPCFG) | ICM20648_BIT_GYRO_FCHOICE)      /**< Gyro Bandwidth = 360 Hz   */\n#define ICM20648_GYRO_BW_200HZ           ( (0x00 << ICM20648_SHIFT_GYRO_DLPCFG) | ICM20648_BIT_GYRO_FCHOICE)      /**< Gyro Bandwidth = 200 Hz   */\n#define ICM20648_GYRO_BW_150HZ           ( (0x01 << ICM20648_SHIFT_GYRO_DLPCFG) | ICM20648_BIT_GYRO_FCHOICE)      /**< Gyro Bandwidth = 150 Hz   */\n#define ICM20648_GYRO_BW_120HZ           ( (0x02 << ICM20648_SHIFT_GYRO_DLPCFG) | ICM20648_BIT_GYRO_FCHOICE)      /**< Gyro Bandwidth = 120 Hz   */\n#define ICM20648_GYRO_BW_51HZ            ( (0x03 << ICM20648_SHIFT_GYRO_DLPCFG) | ICM20648_BIT_GYRO_FCHOICE)      /**< Gyro Bandwidth = 51 Hz    */\n#define ICM20648_GYRO_BW_24HZ            ( (0x04 << ICM20648_SHIFT_GYRO_DLPCFG) | ICM20648_BIT_GYRO_FCHOICE)      /**< Gyro Bandwidth = 24 Hz    */\n#define ICM20648_GYRO_BW_12HZ            ( (0x05 << ICM20648_SHIFT_GYRO_DLPCFG) | ICM20648_BIT_GYRO_FCHOICE)      /**< Gyro Bandwidth = 12 Hz    */\n#define ICM20648_GYRO_BW_6HZ             ( (0x06 << ICM20648_SHIFT_GYRO_DLPCFG) | ICM20648_BIT_GYRO_FCHOICE)      /**< Gyro Bandwidth = 6 Hz     */\n \n#define ICM20648_REG_GYRO_CONFIG_2       (ICM20648_BANK_2 | 0x02)    /**< Gyroscope Configuration 2 register                     */\n#define ICM20648_BIT_GYRO_CTEN           0x38                        /**< Gyroscope Self-Test Enable bits                        */\n \n#define ICM20648_REG_XG_OFFS_USRH        (ICM20648_BANK_2 | 0x03)    /**< Gyroscope sensor X-axis offset cancellation high byte  */\n#define ICM20648_REG_XG_OFFS_USRL        (ICM20648_BANK_2 | 0x04)    /**< Gyroscope sensor X-axis offset cancellation low byte   */\n#define ICM20648_REG_YG_OFFS_USRH        (ICM20648_BANK_2 | 0x05)    /**< Gyroscope sensor Y-axis offset cancellation high byte  */\n#define ICM20648_REG_YG_OFFS_USRL        (ICM20648_BANK_2 | 0x06)    /**< Gyroscope sensor Y-axis offset cancellation low byte   */\n#define ICM20648_REG_ZG_OFFS_USRH        (ICM20648_BANK_2 | 0x07)    /**< Gyroscope sensor Z-axis offset cancellation high byte  */\n#define ICM20648_REG_ZG_OFFS_USRL        (ICM20648_BANK_2 | 0x08)    /**< Gyroscope sensor Z-axis offset cancellation low byte   */\n \n#define ICM20648_REG_ODR_ALIGN_EN        (ICM20648_BANK_2 | 0x09)    /**< Output Data Rate start time alignment                  */\n \n#define ICM20648_REG_ACCEL_SMPLRT_DIV_1  (ICM20648_BANK_2 | 0x10)    /**< Acceleration Sensor Sample Rate Divider 1 register     */\n#define ICM20648_REG_ACCEL_SMPLRT_DIV_2  (ICM20648_BANK_2 | 0x11)    /**< Acceleration Sensor Sample Rate Divider 2 register     */\n \n#define ICM20648_REG_ACCEL_INTEL_CTRL    (ICM20648_BANK_2 | 0x12)    /**< Accelerometer Hardware Intelligence Control register   */\n#define ICM20648_BIT_ACCEL_INTEL_EN      0x02                        /**< Wake-up On Motion enable bit                           */\n#define ICM20648_BIT_ACCEL_INTEL_MODE    0x01                        /**< WOM algorithm selection bit                            */\n \n#define ICM20648_REG_ACCEL_WOM_THR       (ICM20648_BANK_2 | 0x13)    /**< Wake-up On Motion Threshold register                   */\n \n#define ICM20648_REG_ACCEL_CONFIG        (ICM20648_BANK_2 | 0x14)    /**< Accelerometer Configuration register                   */\n#define ICM20648_BIT_ACCEL_FCHOICE       0x01                        /**< Accel Digital Low-Pass Filter enable bit               */\n#define ICM20648_SHIFT_ACCEL_FS          1                           /**< Accel Full Scale Select bit shift                      */\n#define ICM20648_SHIFT_ACCEL_DLPCFG      3                           /**< Accel DLPF Config bit shift                            */\n#define ICM20648_MASK_ACCEL_FULLSCALE    0x06                        /**< Accel Full Scale Select bitmask                        */\n#define ICM20648_MASK_ACCEL_BW           0x39                        /**< Accel Bandwidth Select bitmask                         */\n#define ICM20648_ACCEL_FULLSCALE_2G      (0x00 << ICM20648_SHIFT_ACCEL_FS)    /**< Accel Full Scale = 2 g  */\n#define ICM20648_ACCEL_FULLSCALE_4G      (0x01 << ICM20648_SHIFT_ACCEL_FS)    /**< Accel Full Scale = 4 g  */\n#define ICM20648_ACCEL_FULLSCALE_8G      (0x02 << ICM20648_SHIFT_ACCEL_FS)    /**< Accel Full Scale = 8 g  */\n#define ICM20648_ACCEL_FULLSCALE_16G     (0x03 << ICM20648_SHIFT_ACCEL_FS)    /**< Accel Full Scale = 16 g */\n#define ICM20648_ACCEL_BW_1210HZ         (0x00 << ICM20648_SHIFT_ACCEL_DLPCFG)                                    /**< Accel Bandwidth = 1210 Hz  */\n#define ICM20648_ACCEL_BW_470HZ          ( (0x07 << ICM20648_SHIFT_ACCEL_DLPCFG) | ICM20648_BIT_ACCEL_FCHOICE)    /**< Accel Bandwidth = 470 Hz   */\n#define ICM20648_ACCEL_BW_246HZ          ( (0x00 << ICM20648_SHIFT_ACCEL_DLPCFG) | ICM20648_BIT_ACCEL_FCHOICE)    /**< Accel Bandwidth = 246 Hz   */\n#define ICM20648_ACCEL_BW_111HZ          ( (0x02 << ICM20648_SHIFT_ACCEL_DLPCFG) | ICM20648_BIT_ACCEL_FCHOICE)    /**< Accel Bandwidth = 111 Hz   */\n#define ICM20648_ACCEL_BW_50HZ           ( (0x03 << ICM20648_SHIFT_ACCEL_DLPCFG) | ICM20648_BIT_ACCEL_FCHOICE)    /**< Accel Bandwidth = 50 Hz    */\n#define ICM20648_ACCEL_BW_24HZ           ( (0x04 << ICM20648_SHIFT_ACCEL_DLPCFG) | ICM20648_BIT_ACCEL_FCHOICE)    /**< Accel Bandwidth = 24 Hz    */\n#define ICM20648_ACCEL_BW_12HZ           ( (0x05 << ICM20648_SHIFT_ACCEL_DLPCFG) | ICM20648_BIT_ACCEL_FCHOICE)    /**< Accel Bandwidth = 12 Hz    */\n#define ICM20648_ACCEL_BW_6HZ            ( (0x06 << ICM20648_SHIFT_ACCEL_DLPCFG) | ICM20648_BIT_ACCEL_FCHOICE)    /**< Accel Bandwidth = 6 Hz     */\n \n#define ICM20648_REG_ACCEL_CONFIG_2      (ICM20648_BANK_2 | 0x15)    /**< Accelerometer Configuration 2 register              */\n#define ICM20648_BIT_ACCEL_CTEN          0x1C                        /**< Accelerometer Self-Test Enable bits                 */\n \n/***********************/\n/* Bank 3 register map */\n/***********************/\n#define ICM20648_REG_I2C_MST_ODR_CONFIG  (ICM20648_BANK_3 | 0x00)    /**< I2C Master Output Data Rate Configuration register  */\n \n#define ICM20648_REG_I2C_MST_CTRL        (ICM20648_BANK_3 | 0x01)    /**< I2C Master Control register                         */\n#define ICM20648_BIT_I2C_MST_P_NSR       0x10                        /**< Stop between reads enabling bit                     */\n \n#define ICM20648_REG_I2C_MST_DELAY_CTRL  (ICM20648_BANK_3 | 0x02)    /**< I2C Master Delay Control register                   */\n#define ICM20648_BIT_SLV0_DLY_EN         0x01                        /**< I2C Slave0 Delay Enable bit                         */\n#define ICM20648_BIT_SLV1_DLY_EN         0x02                        /**< I2C Slave1 Delay Enable bit                         */\n#define ICM20648_BIT_SLV2_DLY_EN         0x04                        /**< I2C Slave2 Delay Enable bit                         */\n#define ICM20648_BIT_SLV3_DLY_EN         0x08                        /**< I2C Slave3 Delay Enable bit                         */\n \n#define ICM20648_REG_I2C_SLV0_ADDR       (ICM20648_BANK_3 | 0x03)    /**< I2C Slave0 Physical Address register                */\n#define ICM20648_REG_I2C_SLV0_REG        (ICM20648_BANK_3 | 0x04)    /**< I2C Slave0 Register Address register                */\n#define ICM20648_REG_I2C_SLV0_CTRL       (ICM20648_BANK_3 | 0x05)    /**< I2C Slave0 Control register                         */\n#define ICM20648_REG_I2C_SLV0_DO         (ICM20648_BANK_3 | 0x06)    /**< I2C Slave0 Data Out register                        */\n \n#define ICM20648_REG_I2C_SLV1_ADDR       (ICM20648_BANK_3 | 0x07)    /**< I2C Slave1 Physical Address register                */\n#define ICM20648_REG_I2C_SLV1_REG        (ICM20648_BANK_3 | 0x08)    /**< I2C Slave1 Register Address register                */\n#define ICM20648_REG_I2C_SLV1_CTRL       (ICM20648_BANK_3 | 0x09)    /**< I2C Slave1 Control register                         */\n#define ICM20648_REG_I2C_SLV1_DO         (ICM20648_BANK_3 | 0x0A)    /**< I2C Slave1 Data Out register                        */\n \n#define ICM20648_REG_I2C_SLV2_ADDR       (ICM20648_BANK_3 | 0x0B)    /**< I2C Slave2 Physical Address register                */\n#define ICM20648_REG_I2C_SLV2_REG        (ICM20648_BANK_3 | 0x0C)    /**< I2C Slave2 Register Address register                */\n#define ICM20648_REG_I2C_SLV2_CTRL       (ICM20648_BANK_3 | 0x0D)    /**< I2C Slave2 Control register                         */\n#define ICM20648_REG_I2C_SLV2_DO         (ICM20648_BANK_3 | 0x0E)    /**< I2C Slave2 Data Out register                        */\n \n#define ICM20648_REG_I2C_SLV3_ADDR       (ICM20648_BANK_3 | 0x0F)    /**< I2C Slave3 Physical Address register                */\n#define ICM20648_REG_I2C_SLV3_REG        (ICM20648_BANK_3 | 0x10)    /**< I2C Slave3 Register Address register                */\n#define ICM20648_REG_I2C_SLV3_CTRL       (ICM20648_BANK_3 | 0x11)    /**< I2C Slave3 Control register                         */\n#define ICM20648_REG_I2C_SLV3_DO         (ICM20648_BANK_3 | 0x12)    /**< I2C Slave3 Data Out register                        */\n \n#define ICM20648_REG_I2C_SLV4_ADDR       (ICM20648_BANK_3 | 0x13)    /**< I2C Slave4 Physical Address register                */\n#define ICM20648_REG_I2C_SLV4_REG        (ICM20648_BANK_3 | 0x14)    /**< I2C Slave4 Register Address register                */\n#define ICM20648_REG_I2C_SLV4_CTRL       (ICM20648_BANK_3 | 0x15)    /**< I2C Slave4 Control register                         */\n#define ICM20648_REG_I2C_SLV4_DO         (ICM20648_BANK_3 | 0x16)    /**< I2C Slave4 Data Out register                        */\n#define ICM20648_REG_I2C_SLV4_DI         (ICM20648_BANK_3 | 0x17)    /**< I2C Slave4 Data In register                         */\n \n#define ICM20648_BIT_I2C_SLV_EN          0x80                        /**< I2C Slave Enable bit                                */\n#define ICM20648_BIT_I2C_BYTE_SW         0x40                        /**< I2C Slave Byte Swap enable bit                      */\n#define ICM20648_BIT_I2C_REG_DIS         0x20                        /**< I2C Slave Do Not Write Register Value bit           */\n#define ICM20648_BIT_I2C_GRP             0x10                        /**< I2C Slave Group bit                                 */\n#define ICM20648_BIT_I2C_READ            0x80                        /**< I2C Slave R/W bit                                   */\n \n/* Register common for all banks */\n#define ICM20648_REG_BANK_SEL            0x7F                        /**< Bank Select register                                */\n \n#define ICM20648_DEVICE_ID               0xE0                        /**< ICM20648 Device ID value                            */\n#define ICM20948_DEVICE_ID               0xEA                        /**< ICM20948 Device ID value                            */\n\n\n\n\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/IMU/IMU.cpp",
    "content": "//----------------------------------------------------------------------------\r\n//    프로그램명 \t:\r\n//\r\n//    만든이     \t: Made by Baram ( chcbaram@paran.com )\r\n//\r\n//    날  짜     :\r\n//\r\n//    최종 수정  \t:\r\n//\r\n//    MPU_Type\t:\r\n//\r\n//    파일명     \t: IMU.ino\r\n//----------------------------------------------------------------------------\r\n#include <Arduino.h>\r\n#include \"IMU.h\"\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : BLE\r\n     WORK    :\r\n     ARG     : void\r\n     RET     : void\r\n---------------------------------------------------------------------------*/\r\ncIMU::cIMU()\r\n{\r\n  uint8_t i;\r\n\r\n  for( i=0; i<3; i++ )\r\n  {\r\n    rpy[i] = 0.;\r\n\r\n  }\r\n\r\n\tbConnected = false;\r\n}\r\n\r\n\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : begin\r\n     WORK    :\r\n     ARG     : void\r\n     RET     : void\r\n---------------------------------------------------------------------------*/\r\nuint8_t cIMU::begin( uint32_t hz )\r\n{\r\n\tuint8_t err_code = IMU_OK;\r\n  uint32_t i;\r\n  uint32_t pre_time;\r\n\r\n  update_hz = hz;\r\n  update_us = 1000000/hz;\r\n\r\n  aRes = 8.0/32768.0;      // 8g\r\n  \r\n  gRes = 2000.0/32768.0;   // 2000dps\r\n  //mRes = 10.*4912./8190.;  // 14BIT\r\n  mRes = 10.*4912./32760.; // 16BIT\r\n\r\n  bConnected = SEN.begin();\r\n  \r\n  \r\n  if( bConnected == true )\r\n  {\r\n    filter.begin(update_hz);\r\n\r\n    for (i=0; i<32; i++)\r\n    {\r\n      update();\r\n    }\r\n\r\n    pre_time = millis();\r\n    while(!SEN.gyro_cali_get_done())\r\n    {\r\n      update();\r\n\r\n      if (millis()-pre_time > 5000)\r\n      {\r\n        break;\r\n      }\r\n    }\r\n  }\r\n  \r\n  \r\n\r\n\treturn err_code;\r\n}\r\n\r\n\r\n\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : update\r\n     WORK    :\r\n     ARG     : void\r\n     RET     : void\r\n---------------------------------------------------------------------------*/\r\nuint16_t cIMU::update( uint32_t option )\r\n{\r\n  UNUSED(option);\r\n\r\n\tuint16_t ret_time = 0;\r\n\r\n\tstatic uint32_t tTime;\r\n\r\n\r\n\tif( (micros()-tTime) >= update_us )\r\n\t{\r\n\t\tret_time = micros()-tTime;\r\n    tTime = micros();\r\n\r\n\t\tcomputeIMU();\r\n\r\n\t\tgyroData[0] = SEN.gyroADC[0];\r\n\t\tgyroData[1] = SEN.gyroADC[1];\r\n\t\tgyroData[2] = SEN.gyroADC[2];\r\n\r\n    gyroRaw[0]  = SEN.gyroRAW[0];\r\n    gyroRaw[1]  = SEN.gyroRAW[1];\r\n    gyroRaw[2]  = SEN.gyroRAW[2];\r\n\r\n    accData[0]  = SEN.accADC[0];\r\n    accData[1]  = SEN.accADC[1];\r\n    accData[2]  = SEN.accADC[2];\r\n\r\n    accRaw[0]   = SEN.accRAW[0];\r\n    accRaw[1]   = SEN.accRAW[1];\r\n    accRaw[2]   = SEN.accRAW[2];\r\n\r\n    magData[0]  = SEN.magADC[0];\r\n    magData[1]  = SEN.magADC[1];\r\n    magData[2]  = SEN.magADC[2];\r\n\r\n    magRaw[0]   = SEN.magRAW[0];\r\n    magRaw[1]   = SEN.magRAW[1];\r\n    magRaw[2]   = SEN.magRAW[2];\r\n\t}\r\n\r\n\treturn ret_time;\r\n}\r\n\r\n\r\n#define FILTER_NUM    3\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : compute\r\n     WORK    :\r\n     ARG     : void\r\n     RET     : void\r\n---------------------------------------------------------------------------*/\r\nvoid cIMU::computeIMU( void )\r\n{\r\n  static uint32_t prev_process_time = micros();\r\n  static uint32_t cur_process_time = 0;\r\n  static uint32_t process_time = 0;\r\n  uint32_t i;\r\n  static int32_t gyroADC[3][FILTER_NUM] = {0,};\r\n  int32_t gyroAdcSum;\r\n\r\n  uint32_t axis;\r\n\r\n\tSEN.acc_get_adc();\r\n\tSEN.gyro_get_adc();\r\n  SEN.mag_get_adc();\r\n\r\n  for (axis = 0; axis < 3; axis++)\r\n  {\r\n    gyroADC[axis][0] = SEN.gyroADC[axis];\r\n\r\n\r\n    gyroAdcSum = 0;\r\n    for (i=0; i<FILTER_NUM; i++)\r\n    {\r\n      gyroAdcSum += gyroADC[axis][i];\r\n    }\r\n    SEN.gyroADC[axis] = gyroAdcSum/FILTER_NUM;\r\n    for (i=FILTER_NUM-1; i>0; i--)\r\n    {\r\n      gyroADC[axis][i] = gyroADC[axis][i-1];\r\n    }\r\n\r\n    if (abs(SEN.gyroADC[axis]) <= 3)\r\n    {\r\n      SEN.gyroADC[axis] = 0;\r\n    }\r\n  }\r\n\r\n\r\n  for( i=0; i<3; i++ )\r\n  {\r\n    accRaw[i]   = SEN.accRAW[i];\r\n    accData[i]  = SEN.accADC[i];\r\n    gyroRaw[i]  = SEN.gyroRAW[i];\r\n    gyroData[i] = SEN.gyroADC[i];\r\n    magRaw[i]   = SEN.magRAW[i];\r\n    magData[i]  = SEN.magADC[i];\r\n  }\r\n\r\n  ax = (float)SEN.accADC[0]*aRes;\r\n  ay = (float)SEN.accADC[1]*aRes;\r\n  az = (float)SEN.accADC[2]*aRes;\r\n\r\n  gx = (float)SEN.gyroADC[0]*gRes;\r\n  gy = (float)SEN.gyroADC[1]*gRes;\r\n  gz = (float)SEN.gyroADC[2]*gRes;\r\n\r\n  mx = (float)SEN.magADC[0]*mRes;\r\n  my = (float)SEN.magADC[1]*mRes;\r\n  mz = (float)SEN.magADC[2]*mRes;\r\n\r\n\r\n  cur_process_time  = micros();\r\n  process_time      = cur_process_time-prev_process_time;\r\n  prev_process_time = cur_process_time;\r\n\r\n  if (SEN.calibratingG == 0 && SEN.calibratingA == 0)\r\n  {\r\n    filter.invSampleFreq = (float)process_time/1000000.0f;\r\n    filter.updateIMU(gx, gy, gz, ax, ay, az);\r\n    //filter.update(gx, gy, gz, ax, ay, az, mx, my, mz);\r\n  }\r\n\r\n\r\n  rpy[0] = filter.getRoll();\r\n  rpy[1] = filter.getPitch();\r\n  rpy[2] = filter.getYaw()-180.;\r\n\r\n  quat[0] = filter.q0;\r\n  quat[1] = filter.q1;\r\n  quat[2] = filter.q2;\r\n  quat[3] = filter.q3;\r\n\r\n  angle[0] = (int16_t)(rpy[0] * 10.);\r\n  angle[1] = (int16_t)(rpy[1] * 10.);\r\n  angle[2] = (int16_t)(rpy[1] * 1.);\r\n\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/IMU/IMU.h",
    "content": "//----------------------------------------------------------------------------\r\n//    프로그램명 \t: IMU\r\n//\r\n//    만든이     \t: Made by Baram ( chcbaram@paran.com )\r\n//\r\n//    날  짜     :\r\n//\r\n//    최종 수정  \t:\r\n//\r\n//    MPU_Type\t:\r\n//\r\n//    파일명     \t: IMU.h\r\n//----------------------------------------------------------------------------\r\n#ifndef _IMU_H_\r\n#define _IMU_H_\r\n\r\n#include <inttypes.h>\r\n#include <Arduino.h>\r\n\r\n#include <SPI.h>\r\n// #include \"MPU9250.h\"\r\n#include \"MadgwickAHRS.h\"\r\n\r\n#include \"imu_selector.h\"\r\n\r\n#define IMU_OK\t\t\t  0x00\r\n#define IMU_ERR_I2C\t\t0x01\r\n\r\n\r\n\r\nclass cIMU\r\n{\r\npublic:\r\n\t//cMPU9250 SEN;\r\n  cIMUDevice SEN;\r\n  //cICM20648 SEN;\r\n  \r\n  \r\n\tint16_t angle[3];\r\n  float   rpy[3];\r\n  float   quat[4];\r\n  int16_t gyroData[3];\r\n  int16_t gyroRaw[3];\r\n  int16_t accData[3];\r\n  int16_t accRaw[3];\r\n  int16_t magData[3];\r\n  int16_t magRaw[3];\r\n\r\n  float ax, ay, az;\r\n  float gx, gy, gz;\r\n  float mx, my, mz;\r\n\r\n\tbool bConnected;\r\n\r\n  float aRes;\r\n  float gRes;\r\n  float mRes;\r\n\r\npublic:\r\n\tcIMU();\r\n\r\n\tuint8_t  begin( uint32_t hz = 200 );\r\n\tuint16_t update( uint32_t option = 0 );\r\n\r\nprivate:\r\n  Madgwick filter;\r\n  uint32_t update_hz;\r\n  uint32_t update_us;\r\n\r\n\tvoid computeIMU( void );\r\n\r\n};\r\n\r\n\r\n#endif\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/IMU/MPU9250.cpp",
    "content": "//----------------------------------------------------------------------------\r\n//    프로그램명 \t: MPU6050\r\n//\r\n//    만든이     \t: Baram ( chcbaram@paran.com )\r\n//\r\n//    날  짜     :\r\n//\r\n//    최종 수정  \t:\r\n//\r\n//    MPU_Type\t:\r\n//\r\n//    파일명     \t: MPU6050.cpp\r\n//----------------------------------------------------------------------------\r\n\r\n\r\n\r\n#include <Arduino.h>\r\n#include <SPI.h>\r\n#include \"MPU9250.h\"\r\n#include \"imu_spi.h\"\r\n\r\n\r\n#define MPU_CS_PIN          BDPIN_SPI_CS_IMU\r\n#define MPU9250_ADDRESS     0x68\r\n#define MPU_CALI_COUNT      512\r\n\r\n\r\n//#define ACC_ORIENTATION(X, Y, Z)  {accADC[PITCH]  = -X; accADC[ROLL]  =  Y; accADC[YAW]  =   Z;}\r\n//#define GYRO_ORIENTATION(X, Y, Z) {gyroADC[PITCH] =  Y; gyroADC[ROLL] =  X; gyroADC[YAW] =   Z;}\r\n\r\n#define ACC_ORIENTATION(X, Y, Z)  {accADC[PITCH]  =  Y; accADC[ROLL]  =  X; accADC[YAW]  =   Z;}\r\n#define GYRO_ORIENTATION(X, Y, Z) {gyroADC[PITCH] =  Y; gyroADC[ROLL] =  X; gyroADC[YAW] =   Z;}\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : cMPU9250\r\n     WORK    :\r\n     ARG     : void\r\n     RET     : void\r\n---------------------------------------------------------------------------*/\r\ncMPU9250::cMPU9250()\r\n{\r\n\tcalibratingG = 0;\r\n\tcalibratingA = 0;\r\n  calibratingM = 0;\r\n  bConnected   = false;\r\n}\r\n\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : cMPU9250\r\n     WORK    :\r\n     ARG     : void\r\n     RET     : void\r\n---------------------------------------------------------------------------*/\r\nbool cMPU9250::begin()\r\n{\r\n\r\n  pinMode( MPU_CS_PIN, OUTPUT );\r\n\r\n  MPU_SPI.begin();\r\n  MPU_SPI.setDataMode( SPI_MODE3 );\r\n  MPU_SPI.setBitOrder( MSBFIRST );\r\n  MPU_SPI.setClockDivider( SPI_CLOCK_DIV128 ); // 108Mhz/128 = 0.8MHz\r\n  digitalWrite(MPU_CS_PIN, HIGH);\r\n  delay( 100 );\r\n\r\n\r\n  if( imu_spi_read(MPU9250_ADDRESS, 0x75) == 0x71 )\r\n  {\r\n    bConnected = true;\r\n    init();\r\n    gyro_init();\r\n    acc_init();\r\n    mag_init();\r\n\r\n    MPU_SPI.setClockDivider( SPI_CLOCK_DIV8 ); // 13MHz\r\n  }\r\n\r\n\r\n\r\n  return bConnected;\r\n}\r\n\r\n\r\nvoid cMPU9250::init( void )\r\n{\r\n  uint8_t state;\r\n  uint8_t data;\r\n  uint8_t response[3] = {0, 0, 0};\r\n\r\n\r\n  //MPU9250 Reset\r\n\timu_spi_write(MPU9250_SPIx_ADDR, MPU9250_PWR_MGMT_1, MPU9250_RESET);\r\n\tdelay(100);\r\n\t//MPU9250 Set Clock Source\r\n\timu_spi_write(MPU9250_SPIx_ADDR, MPU9250_PWR_MGMT_1,  MPU9250_CLOCK_PLLGYROZ);\r\n\tdelay(1);\r\n\r\n\r\n\t//MPU9250 Set Interrupt\r\n\timu_spi_write(MPU9250_SPIx_ADDR, MPU9250_INT_PIN_CFG,  MPU9250_INT_ANYRD_2CLEAR);\r\n\tdelay(1);\r\n\timu_spi_write(MPU9250_SPIx_ADDR, MPU9250_INT_ENABLE, ENABLE);\r\n\tdelay(1);\r\n\t//MPU9250 Set Sensors\r\n\timu_spi_write(MPU9250_SPIx_ADDR, MPU9250_PWR_MGMT_2, MPU9250_XYZ_GYRO & MPU9250_XYZ_ACCEL);\r\n\tdelay(1);\r\n\t//MPU9250 Set SampleRate\r\n\t//SAMPLE_RATE = Internal_Sample_Rate / (1 + SMPLRT_DIV)\r\n\timu_spi_write(MPU9250_SPIx_ADDR, MPU9250_SMPLRT_DIV, SMPLRT_DIV);\r\n\tdelay(1);\r\n\t//MPU9250 Set Full Scale Gyro Range\r\n\t//Fchoice_b[1:0] = [00] enable DLPF\r\n\timu_spi_write(MPU9250_SPIx_ADDR, MPU9250_GYRO_CONFIG, (MPU9250_FSR_2000DPS << 3));\r\n\tdelay(1);\r\n\t//MPU9250 Set Full Scale Accel Range PS:2G\r\n\timu_spi_write(MPU9250_SPIx_ADDR, MPU9250_ACCEL_CONFIG, (MPU9250_FSR_2G << 3));\r\n\tdelay(1);\r\n\t//MPU9250 Set Accel DLPF\r\n\tdata = imu_spi_read(MPU9250_SPIx_ADDR, MPU9250_ACCEL_CONFIG2);\r\n\tdata |= MPU9250_ACCEL_DLPF_41HZ;\r\n\tdelay(1);\r\n\timu_spi_write(MPU9250_SPIx_ADDR, MPU9250_ACCEL_CONFIG2, data);\r\n\tdelay(1);\r\n\t//MPU9250 Set Gyro DLPF\r\n\timu_spi_write(MPU9250_SPIx_ADDR, MPU9250_CONFIG, MPU9250_GYRO_DLPF_41HZ);\r\n\tdelay(1);\r\n\r\n\r\n\r\n  //MPU9250 Set SPI Mode\r\n\tstate = imu_spi_read(MPU9250_ADDRESS, MPU9250_USER_CTRL);\r\n\tdelay(1);\r\n\timu_spi_write(MPU9250_ADDRESS, MPU9250_USER_CTRL, state | MPU9250_I2C_IF_DIS);\r\n\tdelay(1);\r\n\tstate = imu_spi_read(MPU9250_ADDRESS, MPU9250_USER_CTRL);\r\n\tdelay(1);\r\n\timu_spi_write(MPU9250_ADDRESS, MPU9250_USER_CTRL, state | MPU9250_I2C_MST_EN);\r\n\tdelay(1);\r\n\t//////////////////////////////////////////////////////////////////////////\r\n\t//AK8963 Setup\r\n\t//reset AK8963\r\n\timu_spi_ak8963_write(MPU9250_AK8963_I2C_ADDR, MPU9250_AK8963_CNTL2, MPU9250_AK8963_CNTL2_SRST);\r\n\tdelay(1);\r\n\r\n\timu_spi_ak8963_write(MPU9250_AK8963_I2C_ADDR, MPU9250_AK8963_CNTL, MPU9250_AK8963_POWER_DOWN);\r\n\tdelay(1);\r\n\timu_spi_ak8963_write(MPU9250_AK8963_I2C_ADDR, MPU9250_AK8963_CNTL, MPU9250_AK8963_FUSE_ROM_ACCESS);\r\n\tdelay(1);\r\n\r\n\r\n  imu_spi_ak8963_reads(MPU9250_AK8963_I2C_ADDR, MPU9250_AK8963_WIA, 3, response);\r\n\t//\r\n\t//AK8963 get calibration data\r\n\timu_spi_ak8963_reads(MPU9250_AK8963_I2C_ADDR, MPU9250_AK8963_ASAX, 3, response);\r\n\tAK8963_ASA[0] = (int16_t)(response[0]) + 128;\r\n\tAK8963_ASA[1] = (int16_t)(response[1]) + 128;\r\n\tAK8963_ASA[2] = (int16_t)(response[2]) + 128;\r\n\tdelay(1);\r\n\r\n\timu_spi_ak8963_write(MPU9250_AK8963_I2C_ADDR, MPU9250_AK8963_CNTL, MPU9250_AK8963_POWER_DOWN);\r\n\tdelay(1);\r\n\t//\r\n\timu_spi_write(MPU9250_SPIx_ADDR, MPU9250_I2C_MST_CTRL, 0x5D);\r\n\tdelay(1);\r\n\timu_spi_write(MPU9250_SPIx_ADDR, MPU9250_I2C_SLV0_ADDR, MPU9250_AK8963_I2C_ADDR | MPU9250_I2C_READ);\r\n\tdelay(1);\r\n\timu_spi_write(MPU9250_SPIx_ADDR, MPU9250_I2C_SLV0_REG, MPU9250_AK8963_ST1);\r\n\tdelay(1);\r\n\timu_spi_write(MPU9250_SPIx_ADDR, MPU9250_I2C_SLV0_CTRL, 0x88);\r\n\tdelay(1);\r\n\t//\r\n\timu_spi_ak8963_write(MPU9250_AK8963_I2C_ADDR, MPU9250_AK8963_CNTL, MPU9250_AK8963_CONTINUOUS_MEASUREMENT);\r\n\tdelay(1);\r\n\r\n\t//\r\n\timu_spi_write(MPU9250_SPIx_ADDR, MPU9250_I2C_SLV4_CTRL, 0x09);\r\n\tdelay(1);\r\n\t//\r\n\timu_spi_write(MPU9250_SPIx_ADDR, MPU9250_I2C_MST_DELAY_CTRL, 0x81);\r\n\tdelay(100);\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : gyro_init\r\n     WORK    :\r\n     ARG     : void\r\n     RET     : void\r\n---------------------------------------------------------------------------*/\r\nvoid cMPU9250::gyro_init( void )\r\n{\r\n  uint8_t i;\r\n\r\n  for( i=0; i<3; i++ )\r\n  {\r\n    gyroADC[i]  = 0;\r\n\tgyroZero[i] = 0;\r\n\tgyroRAW[i]  = 0;\r\n  }\r\n\r\n  calibratingG = MPU_CALI_COUNT;\r\n}\r\n\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : gyro_get_adc\r\n     WORK    :\r\n     ARG     : void\r\n     RET     : void\r\n---------------------------------------------------------------------------*/\r\nvoid cMPU9250::gyro_get_adc( void )\r\n{\r\n  int16_t x = 0;\r\n  int16_t y = 0;\r\n  int16_t z = 0;\r\n\r\n  uint8_t rawADC[6];\r\n\r\n  if( bConnected == true )\r\n  {\r\n    imu_spi_reads( MPU9250_ADDRESS, MPU9250_GYRO_XOUT_H, 6, rawADC );\r\n\r\n \tx = (((int16_t)rawADC[0]) << 8) | rawADC[1];\r\n  \ty = (((int16_t)rawADC[2]) << 8) | rawADC[3];\r\n  \tz = (((int16_t)rawADC[4]) << 8) | rawADC[5];\r\n\r\n  \tgyroRAW[0] = x;\r\n  \tgyroRAW[1] = y;\r\n  \tgyroRAW[2] = z;\r\n\r\n  \tGYRO_ORIENTATION( x, y,z );\r\n  }\r\n\r\n  gyro_common();\r\n}\r\n\r\n\r\n\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : gyro_cali_start\r\n     WORK    :\r\n     ARG     : void\r\n     RET     : void\r\n---------------------------------------------------------------------------*/\r\nvoid cMPU9250::gyro_cali_start()\r\n{\r\n  calibratingG = MPU_CALI_COUNT;\r\n}\r\n\r\n\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : acc_init\r\n     WORK    :\r\n     ARG     : void\r\n     RET     : void\r\n---------------------------------------------------------------------------*/\r\nvoid cMPU9250::acc_init( void )\r\n{\r\n  uint8_t i;\r\n\r\n  for( i=0; i<3; i++ )\r\n  {\r\n    accADC[i]   = 0;\r\n    accZero[i]  = 0;\r\n    accRAW[i]   = 0;\r\n  }\r\n}\r\n\r\n\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : acc_get_adc\r\n     WORK    :\r\n     ARG     : void\r\n     RET     : void\r\n---------------------------------------------------------------------------*/\r\nvoid cMPU9250::acc_get_adc( void )\r\n{\r\n  int16_t x = 0;\r\n  int16_t y = 0;\r\n  int16_t z = 0;\r\n  uint8_t rawADC[6];\r\n\r\n  if( bConnected == true )\r\n  {\r\n    imu_spi_reads( MPU9250_ADDRESS, MPU9250_ACCEL_XOUT_H, 6, rawADC );\r\n\r\n    x = (((int16_t)rawADC[0]) << 8) | rawADC[1];\r\n    y = (((int16_t)rawADC[2]) << 8) | rawADC[3];\r\n    z = (((int16_t)rawADC[4]) << 8) | rawADC[5];\r\n\r\n    accRAW[0] = x;\r\n    accRAW[1] = y;\r\n    accRAW[2] = z;\r\n\t\r\n\tACC_ORIENTATION( x,\ty, z );\r\n  }\r\n\r\n\tacc_common();\r\n}\r\n\r\n\r\n\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : gyro_common\r\n     WORK    :\r\n     ARG     : void\r\n     RET     : void\r\n---------------------------------------------------------------------------*/\r\nvoid cMPU9250::gyro_common()\r\n{\r\n\tstatic int16_t previousGyroADC[3];\r\n\tstatic int32_t g[3];\r\n\tuint8_t axis, tilt=0;\r\n\r\n\tmemset(previousGyroADC, 0, 3);\r\n\r\n\tif (calibratingG>0)\r\n\t{\r\n\t\tfor (axis = 0; axis < 3; axis++)\r\n\t\t{\r\n\t\t\tif (calibratingG == MPU_CALI_COUNT)\r\n\t\t\t{ // Reset g[axis] at start of calibration\r\n\t\t\t\tg[axis]=0;\r\n\t\t\t\tpreviousGyroADC[axis] = gyroADC[axis];\r\n\t\t\t}\r\n\t\t\tif (calibratingG % 10 == 0)\r\n\t\t\t{\r\n\t\t\t\t//if(abs(gyroADC[axis] - previousGyroADC[axis]) > 8) tilt=1;\r\n\r\n\t\t\t\tpreviousGyroADC[axis] = gyroADC[axis];\r\n\t\t\t}\r\n\t\t\tg[axis] += gyroADC[axis]; // Sum up 512 readings\r\n\t\t\tgyroZero[axis]=g[axis]>>9;\r\n\r\n\t\t\tif (calibratingG == 1)\r\n\t\t\t{\r\n\t\t\t\t//SET_ALARM_BUZZER(ALRM_FAC_CONFIRM, ALRM_LVL_CONFIRM_ELSE);\r\n\t\t\t}\r\n\t\t}\r\n\r\n\t\tif(tilt)\r\n\t\t{\r\n\t\t\tcalibratingG=1000;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tcalibratingG--;\r\n\t\t}\r\n\t\treturn;\r\n\t}\r\n\r\n\r\n  for (axis = 0; axis < 3; axis++)\r\n  {\r\n    gyroADC[axis] -= gyroZero[axis];\r\n\r\n    //anti gyro glitch, limit the variation between two consecutive readings\r\n    //gyroADC[axis] = constrain(gyroADC[axis],previousGyroADC[axis]-800,previousGyroADC[axis]+800);\r\n    previousGyroADC[axis] = gyroADC[axis];\r\n  }\r\n}\r\n\r\n\r\n\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : acc_common\r\n     WORK    :\r\n     ARG     : void\r\n     RET     : void\r\n---------------------------------------------------------------------------*/\r\nvoid cMPU9250::acc_common()\r\n{\r\n\tstatic int32_t a[3];\r\n\r\n\tif (calibratingA>0)\r\n\t{\r\n\t\tcalibratingA--;\r\n\t\tfor (uint8_t axis = 0; axis < 3; axis++)\r\n\t\t{\r\n\t\t\tif (calibratingA ==(MPU_CALI_COUNT-1)) a[axis]=0;  // Reset a[axis] at start of calibration\r\n\t\t\ta[axis] += accADC[axis];             // Sum up 512 readings\r\n\t\t\taccZero[axis] = a[axis]>>9;          // Calculate average, only the last itteration where (calibratingA == 0) is relevant\r\n\t\t}\r\n\t\tif (calibratingA == 0)\r\n\t\t{\r\n\t\t\t//accZero[YAW] -= ACC_1G;\r\n      accZero[YAW] = 0;\r\n\t\t}\r\n\t}\r\n\r\n  accADC[ROLL]  -=  accZero[ROLL] ;\r\n  accADC[PITCH] -=  accZero[PITCH];\r\n  accADC[YAW]   -=  accZero[YAW] ;\r\n}\r\n\r\n\r\n\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : acc_init\r\n     WORK    :\r\n     ARG     : void\r\n     RET     : void\r\n---------------------------------------------------------------------------*/\r\nvoid cMPU9250::mag_init( void )\r\n{\r\n  uint8_t i;\r\n\r\n  for( i=0; i<3; i++ )\r\n  {\r\n    magADC[i]   = 0;\r\n\t\tmagZero[i]  = 0;\r\n    magRAW[i]   = 0;\r\n  }\r\n}\r\n\r\n\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : mag_get_adc\r\n     WORK    :\r\n     ARG     : void\r\n     RET     : void\r\n---------------------------------------------------------------------------*/\r\nvoid cMPU9250::mag_get_adc( void )\r\n{\r\n\t// int16_t x = 0;\r\n\t// int16_t y = 0;\r\n\t// int16_t z = 0;\r\n\r\n  uint8_t data[8];\r\n\r\n\r\n\r\n  if( bConnected == true )\r\n  {\r\n  \timu_spi_reads(MPU9250_ADDRESS, MPU9250_EXT_SENS_DATA_00, 8, data);\r\n\r\n  \tif (!(data[0] & MPU9250_AK8963_DATA_READY) || (data[0] & MPU9250_AK8963_DATA_OVERRUN))\r\n    {\r\n  \t\treturn;\r\n  \t}\r\n  \tif (data[7] & MPU9250_AK8963_OVERFLOW)\r\n    {\r\n  \t\treturn;\r\n  \t}\r\n  \tmagRAW[0] = (data[2] << 8) | data[1];\r\n  \tmagRAW[1] = (data[4] << 8) | data[3];\r\n  \tmagRAW[2] = (data[6] << 8) | data[5];\r\n\r\n  \tmagRAW[0] = ((long)magRAW[0] * AK8963_ASA[0]) >> 8;\r\n  \tmagRAW[1] = ((long)magRAW[1] * AK8963_ASA[1]) >> 8;\r\n  \tmagRAW[2] = ((long)magRAW[2] * AK8963_ASA[2]) >> 8;\r\n\t}\r\n\r\n\tmag_common();\r\n}\r\n\r\n\r\n\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : mag_common\r\n     WORK    :\r\n     ARG     : void\r\n     RET     : void\r\n---------------------------------------------------------------------------*/\r\nvoid cMPU9250::mag_common()\r\n{\r\n  magADC[0] = magRAW[0];\r\n  magADC[1] = magRAW[1];\r\n  magADC[2] = magRAW[2];\r\n}\r\n\r\n\r\n\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : acc_cali_start\r\n     WORK    :\r\n     ARG     : void\r\n     RET     : void\r\n---------------------------------------------------------------------------*/\r\nvoid cMPU9250::acc_cali_start()\r\n{\r\n\tcalibratingA = MPU_CALI_COUNT;\r\n}\r\n\r\n\r\n\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : acc_cali_get_done\r\n     WORK    :\r\n     ARG     : void\r\n     RET     : void\r\n---------------------------------------------------------------------------*/\r\nbool cMPU9250::acc_cali_get_done()\r\n{\r\n\tif( calibratingA == 0 ) return true;\r\n\telse                    return false;\r\n}\r\n\r\n\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : gyro_cali_get_done\r\n     WORK    :\r\n     ARG     : void\r\n     RET     : void\r\n---------------------------------------------------------------------------*/\r\nbool cMPU9250::gyro_cali_get_done()\r\n{\r\n\tif( calibratingG == 0 ) return true;\r\n\telse                    return false;\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/IMU/MPU9250.h",
    "content": "//----------------------------------------------------------------------------\r\n//    프로그램명 \t: MPU6050\r\n//\r\n//    만든이     \t: Baram ( chcbaram@paran.com )\r\n//\r\n//    날  짜     :\r\n//\r\n//    최종 수정  \t:\r\n//\r\n//    MPU_Type\t:\r\n//\r\n//    파일명     \t: MPU6050.h\r\n//----------------------------------------------------------------------------\r\n#ifndef _MPU9250_H_\r\n#define _MPU9250_H_\r\n\r\n#include <inttypes.h>\r\n#include <Arduino.h>\r\n\r\n#include \"Define.h\"\r\n#include \"MPU9250_REGS.h\"\r\n\r\n\r\n#define ACC_1G     512\r\n#define GYRO_SCALE (4 / 16.4 * PI / 180.0 / 1000000.0) //16.4 LSB = 1 deg/s\r\n\r\n\r\n#define MPU_SPI   SPI_IMU\r\n\r\n\r\nvoid read_regs( uint8_t addr, uint8_t reg, uint8_t *p_data, uint32_t length );\r\n\r\n\r\nclass cMPU9250\r\n{\r\n public:\r\n  bool     bConnected;\r\n\r\n    int16_t  gyroADC[3];\r\n    int16_t  gyroRAW[3];\r\n    int16_t  gyroZero[3];\r\n\r\n    int16_t  accADC[3];\r\n    int16_t  accRAW[3];\r\n    int16_t  accZero[3];\r\n\r\n    int16_t  magADC[3];\r\n    int16_t  magRAW[3];\r\n    int16_t  magZero[3];\r\n\r\n    int16_t  gyroData[3];\r\n    int16_t  accSmooth[3];\r\n\r\n\tuint16_t calibratingG;\r\n\tuint16_t calibratingA;\r\n    uint16_t calibratingM;\r\n\r\n    int16_t AK8963_ASA[3];\r\n\r\n public:\r\n\tcMPU9250();\r\n\r\n    bool begin( void );\r\n    void init( void );\r\n\tvoid gyro_init( void );\r\n\tvoid gyro_get_adc( void );\r\n\tvoid gyro_common();\r\n\tvoid gyro_cali_start();\r\n\tbool gyro_cali_get_done();\r\n\r\n\tvoid acc_init( void );\r\n\tvoid acc_get_adc( void );\r\n\tvoid acc_common();\r\n\tvoid acc_cali_start();\r\n\tbool acc_cali_get_done();\r\n\r\n    void mag_init( void );\r\n\tvoid mag_get_adc( void );\r\n\tvoid mag_common();\r\n\tvoid mag_cali_start();\r\n\tbool mag_cali_get_done();\r\n\r\n};\r\n\r\n\r\n#endif\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/IMU/MPU9250_REGS.h",
    "content": "/*\r\nThe MIT License (MIT)\r\n\r\nCopyright (c) 2015-? suhetao\r\n\r\nPermission is hereby granted, free of charge, to any person obtaining a copy of\r\nthis software and associated documentation files (the \"Software\"), to deal in\r\nthe Software without restriction, including without limitation the rights to\r\nuse, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r\nthe Software, and to permit persons to whom the Software is furnished to do so,\r\nsubject to the following conditions:\r\n\r\nThe above copyright notice and this permission notice shall be included in all\r\ncopies or substantial portions of the Software.\r\n\r\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r\nFOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r\nCOPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r\nIN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r\nCONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r\n*/\r\n\r\n#ifndef _MPU9250_REGS_H\r\n#define _MPU9250_REGS_H\r\n\r\n\r\n//////////////////////////////////////////////////////////////////////////\r\n//Register Map for Gyroscope and Accelerometer\r\n#define MPU9250_SELF_TEST_X_GYRO        0x00\r\n#define MPU9250_SELF_TEST_Y_GYRO        0x01\r\n#define MPU9250_SELF_TEST_Z_GYRO        0x02\r\n\r\n#define MPU9250_SELF_TEST_X_ACCEL       0x0D\r\n#define MPU9250_SELF_TEST_Y_ACCEL       0x0E\r\n#define MPU9250_SELF_TEST_Z_ACCEL       0x0F\r\n\r\n#define MPU9250_XG_OFFSET_H             0x13\r\n#define MPU9250_XG_OFFSET_L             0x14\r\n#define MPU9250_YG_OFFSET_H             0x15\r\n#define MPU9250_YG_OFFSET_L             0x16\r\n#define MPU9250_ZG_OFFSET_H             0x17\r\n#define MPU9250_ZG_OFFSET_L             0x18\r\n#define MPU9250_SMPLRT_DIV              0x19\r\n#define MPU9250_CONFIG                  0x1A\r\n#define MPU9250_GYRO_CONFIG             0x1B\r\n#define MPU9250_ACCEL_CONFIG            0x1C\r\n#define MPU9250_ACCEL_CONFIG2           0x1D\r\n#define MPU9250_LP_ACCEL_ODR            0x1E\r\n#define MPU9250_WOM_THR                 0x1F\r\n\r\n#define MPU9250_FIFO_EN                 0x23\r\n#define MPU9250_I2C_MST_CTRL            0x24\r\n#define MPU9250_I2C_SLV0_ADDR           0x25\r\n#define MPU9250_I2C_SLV0_REG            0x26\r\n#define MPU9250_I2C_SLV0_CTRL           0x27\r\n#define MPU9250_I2C_SLV1_ADDR           0x28\r\n#define MPU9250_I2C_SLV1_REG            0x29\r\n#define MPU9250_I2C_SLV1_CTRL           0x2A\r\n#define MPU9250_I2C_SLV2_ADDR           0x2B\r\n#define MPU9250_I2C_SLV2_REG            0x2C\r\n#define MPU9250_I2C_SLV2_CTRL           0x2D\r\n#define MPU9250_I2C_SLV3_ADDR           0x2E\r\n#define MPU9250_I2C_SLV3_REG            0x2F\r\n#define MPU9250_I2C_SLV3_CTRL           0x30\r\n#define MPU9250_I2C_SLV4_ADDR           0x31\r\n#define MPU9250_I2C_SLV4_REG            0x32\r\n#define MPU9250_I2C_SLV4_DO             0x33\r\n#define MPU9250_I2C_SLV4_CTRL           0x34\r\n#define MPU9250_I2C_SLV4_DI             0x35\r\n#define MPU9250_I2C_MST_STATUS          0x36\r\n#define MPU9250_INT_PIN_CFG             0x37\r\n#define MPU9250_INT_ENABLE              0x38\r\n\r\n#define MPU9250_INT_STATUS              0x3A\r\n#define MPU9250_ACCEL_XOUT_H            0x3B\r\n#define MPU9250_ACCEL_XOUT_L            0x3C\r\n#define MPU9250_ACCEL_YOUT_H            0x3D\r\n#define MPU9250_ACCEL_YOUT_L            0x3E\r\n#define MPU9250_ACCEL_ZOUT_H            0x3F\r\n#define MPU9250_ACCEL_ZOUT_L            0x40\r\n#define MPU9250_TEMP_OUT_H              0x41\r\n#define MPU9250_TEMP_OUT_L              0x42\r\n#define MPU9250_GYRO_XOUT_H             0x43\r\n#define MPU9250_GYRO_XOUT_L             0x44\r\n#define MPU9250_GYRO_YOUT_H             0x45\r\n#define MPU9250_GYRO_YOUT_L             0x46\r\n#define MPU9250_GYRO_ZOUT_H             0x47\r\n#define MPU9250_GYRO_ZOUT_L             0x48\r\n#define MPU9250_EXT_SENS_DATA_00        0x49\r\n#define MPU9250_EXT_SENS_DATA_01        0x4A\r\n#define MPU9250_EXT_SENS_DATA_02        0x4B\r\n#define MPU9250_EXT_SENS_DATA_03        0x4C\r\n#define MPU9250_EXT_SENS_DATA_04        0x4D\r\n#define MPU9250_EXT_SENS_DATA_05        0x4E\r\n#define MPU9250_EXT_SENS_DATA_06        0x4F\r\n#define MPU9250_EXT_SENS_DATA_07        0x50\r\n#define MPU9250_EXT_SENS_DATA_08        0x51\r\n#define MPU9250_EXT_SENS_DATA_09        0x52\r\n#define MPU9250_EXT_SENS_DATA_10        0x53\r\n#define MPU9250_EXT_SENS_DATA_11        0x54\r\n#define MPU9250_EXT_SENS_DATA_12        0x55\r\n#define MPU9250_EXT_SENS_DATA_13        0x56\r\n#define MPU9250_EXT_SENS_DATA_14        0x57\r\n#define MPU9250_EXT_SENS_DATA_15        0x58\r\n#define MPU9250_EXT_SENS_DATA_16        0x59\r\n#define MPU9250_EXT_SENS_DATA_17        0x5A\r\n#define MPU9250_EXT_SENS_DATA_18        0x5B\r\n#define MPU9250_EXT_SENS_DATA_19        0x5C\r\n#define MPU9250_EXT_SENS_DATA_20        0x5D\r\n#define MPU9250_EXT_SENS_DATA_21        0x5E\r\n#define MPU9250_EXT_SENS_DATA_22        0x5F\r\n#define MPU9250_EXT_SENS_DATA_23        0x60\r\n\r\n#define MPU9250_I2C_SLV0_DO             0x63\r\n#define MPU9250_I2C_SLV1_DO             0x64\r\n#define MPU9250_I2C_SLV2_DO             0x65\r\n#define MPU9250_I2C_SLV3_DO             0x66\r\n#define MPU9250_I2C_MST_DELAY_CTRL      0x67\r\n#define MPU9250_SIGNAL_PATH_RESET       0x68\r\n#define MPU9250_MOT_DETECT_CTRL         0x69\r\n#define MPU9250_USER_CTRL               0x6A\r\n#define MPU9250_PWR_MGMT_1              0x6B\r\n#define MPU9250_PWR_MGMT_2              0x6C\r\n\r\n#define MPU9250_FIFO_COUNTH             0x72\r\n#define MPU9250_FIFO_COUNTL             0x73\r\n#define MPU9250_FIFO_R_W                0x74\r\n#define MPU9250_WHO_AM_I                0x75\r\n#define MPU9250_XA_OFFSET_H             0x77\r\n#define MPU9250_XA_OFFSET_L             0x78\r\n\r\n#define MPU9250_YA_OFFSET_H             0x7A\r\n#define MPU9250_YA_OFFSET_L             0x7B\r\n\r\n#define MPU9250_ZA_OFFSET_H             0x7D\r\n#define MPU9250_ZA_OFFSET_L             0x7E\r\n//\r\n#define MPU9250_I2C_READ 0x80\r\n\r\n//Magnetometer register maps\r\n#define MPU9250_AK8963_WIA                 0x00\r\n#define MPU9250_AK8963_INFO                0x01\r\n#define MPU9250_AK8963_ST1                 0x02\r\n#define MPU9250_AK8963_XOUT_L              0x03\r\n#define MPU9250_AK8963_XOUT_H              0x04\r\n#define MPU9250_AK8963_YOUT_L              0x05\r\n#define MPU9250_AK8963_YOUT_H              0x06\r\n#define MPU9250_AK8963_ZOUT_L              0x07\r\n#define MPU9250_AK8963_ZOUT_H              0x08\r\n#define MPU9250_AK8963_ST2                 0x09\r\n#define MPU9250_AK8963_CNTL                0x0A\r\n#define MPU9250_AK8963_CNTL2               0x0B\r\n#define MPU9250_AK8963_RSV                 0x0B //DO NOT ACCESS <MPU9250_AK8963_CNTL2>\r\n#define MPU9250_AK8963_ASTC                0x0C\r\n#define MPU9250_AK8963_TS1                 0x0D //DO NOT ACCESS\r\n#define MPU9250_AK8963_TS2                 0x0E //DO NOT ACCESS\r\n#define MPU9250_AK8963_I2CDIS              0x0F\r\n#define MPU9250_AK8963_ASAX                0x10\r\n#define MPU9250_AK8963_ASAY                0x11\r\n#define MPU9250_AK8963_ASAZ                0x12\r\n\r\n#define MPU9250_AK8963_I2C_ADDR 0x0C\r\n#define MPU9250_AK8963_POWER_DOWN 0x10\r\n#define MPU9250_AK8963_FUSE_ROM_ACCESS 0x1F\r\n#define MPU9250_AK8963_SINGLE_MEASUREMENT 0x11\r\n#define MPU9250_AK8963_CONTINUOUS_MEASUREMENT 0x16 //MODE 2\r\n#define MPU9250_AK8963_DATA_READY      (0x01)\r\n#define MPU9250_AK8963_DATA_OVERRUN    (0x02)\r\n#define MPU9250_AK8963_OVERFLOW        (0x80)\r\n#define MPU9250_AK8963_DATA_ERROR      (0x40)\r\n#define MPU9250_AK8963_CNTL2_SRST 0x01\r\n\r\n//\r\n#define MPU9250_I2C_SLV4_EN 0x80\r\n#define MPU9250_I2C_SLV4_DONE 0x40\r\n#define MPU9250_I2C_SLV4_NACK 0x10\r\n//\r\n#define MPU9250_I2C_IF_DIS (0x10)\r\n#define MPU9250_I2C_MST_EN (0x20)\r\n#define MPU9250_FIFO_RST (0x04)\r\n#define MPU9250_FIFO_ENABLE (0x40)\r\n//\r\n#define MPU9250_RESET 0x80\r\n#define MPU9250_CLOCK_MASK 0xF8\r\n#define MPU9250_CLOCK_INTERNAL 0x00\r\n#define MPU9250_CLOCK_PLL 0x01\r\n#define MPU9250_CLOCK_PLLGYROZ 0x03\r\n#define MPU9250_FS_SEL_MASK 0xE7\r\n#define MPU9250_SLEEP_MASK 0x40\r\n//\r\n#define MPU9250_XYZ_GYRO 0xC7\r\n#define MPU9250_XYZ_ACCEL 0xF8\r\n//\r\n#define MPU9250_RAW_RDY_EN (0x01)\r\n#define MPU9250_RAW_DATA_RDY_INT (0x01)\r\n#define MPU9250_FIFO_OVERFLOW (0x10)\r\n//\r\n#define MPU9250_INT_ANYRD_2CLEAR (0x10)\r\n#define MPU9250_LATCH_INT_EN (0x20)\r\n//\r\n#define MPU9250_MAX_FIFO (1024)\r\n#define MPU9250_FIFO_SIZE_1024  (0x40)\r\n#define MPU9250_FIFO_SIZE_2048  (0x80)\r\n#define MPU9250_FIFO_SIZE_4096  (0xC0)\r\n\r\n#define MPU9250_TEMP_OUT (0x80)\r\n#define MPU9250_GYRO_XOUT (0x40)\r\n#define MPU9250_GYRO_YOUT (0x20)\r\n#define MPU9250_GYRO_ZOUT (0x10)\r\n#define MPU9250_ACCEL (0x08)\r\n\r\n//\r\n#define SMPLRT_DIV 0\r\n#define MPU9250_SPIx_ADDR 0x00\r\n//////////////////////////////////////////////////////////////////////////\r\n//\r\nenum MPU9250_GYRO_DLPF {\r\n    MPU9250_GYRO_DLPF_250HZ = 0,\r\n    MPU9250_GYRO_DLPF_184HZ,\r\n    MPU9250_GYRO_DLPF_92HZ,\r\n    MPU9250_GYRO_DLPF_41HZ,\r\n    MPU9250_GYRO_DLPF_20HZ,\r\n    MPU9250_GYRO_DLPF_10HZ,\r\n    MPU9250_GYRO_DLPF_5HZ,\r\n    MPU9250_GYRO_DLPF_3600HZ,\r\n    NUM_GYRO_DLPF\r\n};\r\n\r\nenum MPU9250_GYRO_FSR {\r\n    MPU9250_FSR_250DPS = 0,\r\n    MPU9250_FSR_500DPS,\r\n    MPU9250_FSR_1000DPS,\r\n    MPU9250_FSR_2000DPS,\r\n    MPU9250_NUM_GYRO_FSR\r\n};\r\n\r\nenum MPU9250_ACCEL_DLPF {\r\n    MPU9250_ACCEL_DLPF_460HZ = 0,\r\n    MPU9250_ACCEL_DLPF_184HZ,\r\n    MPU9250_ACCEL_DLPF_92HZ,\r\n    MPU9250_ACCEL_DLPF_41HZ,\r\n    MPU9250_ACCEL_DLPF_20HZ,\r\n    MPU9250_ACCEL_DLPF_10HZ,\r\n    MPU9250_ACCEL_DLPF_5HZ,\r\n    MPU9250_ACCEL_DLPF_460HZ2,\r\n    MPU9250_NUM_ACCEL_DLPF\r\n};\r\n\r\nenum MPU9250_ACCEL_FSR {\r\n    MPU9250_FSR_2G = 0,\r\n    MPU9250_FSR_4G,\r\n    MPU9250_FSR_8G,\r\n    MPU9250_FSR_16G,\r\n    MPU9250_NUM_ACCEL_FSR\r\n};\r\n\r\nenum MPU9250_CLK {\r\n    MPU9250_CLK_INTERNAL = 0,\r\n    MPU9250_CLK_PLL,\r\n    MPU9250_NUM_CLK\r\n};\r\n\r\n\r\n#endif\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/IMU/MadgwickAHRS.cpp",
    "content": "//=============================================================================================\r\n// MadgwickAHRS.c\r\n//=============================================================================================\r\n//\r\n// Implementation of Madgwick's IMU and AHRS algorithms.\r\n// See: http://www.x-io.co.uk/open-source-imu-and-ahrs-algorithms/\r\n//\r\n// From the x-io website \"Open-source resources available on this website are\r\n// provided under the GNU General Public Licence unless an alternative licence\r\n// is provided in source.\"\r\n//\r\n// Date\t\t\tAuthor          Notes\r\n// 29/09/2011\tSOH Madgwick    Initial release\r\n// 02/10/2011\tSOH Madgwick\tOptimised for reduced CPU load\r\n// 19/02/2012\tSOH Madgwick\tMagnetometer measurement is normalised\r\n//\r\n//=============================================================================================\r\n\r\n//-------------------------------------------------------------------------------------------\r\n// Header files\r\n\r\n#include \"MadgwickAHRS.h\"\r\n#include <math.h>\r\n\r\n//-------------------------------------------------------------------------------------------\r\n// Definitions\r\n\r\n#define sampleFreqDef   512.0f          // sample frequency in Hz\r\n#define betaDef         0.1f            // 2 * proportional gain\r\n\r\n\r\n\r\n//============================================================================================\r\n// Functions\r\n\r\n//-------------------------------------------------------------------------------------------\r\n// AHRS algorithm update\r\n\r\nMadgwick::Madgwick() {\r\n\tbeta = betaDef;\r\n\tq0 = 1.0f;\r\n\tq1 = 0.0f;\r\n\tq2 = 0.0f;\r\n\tq3 = 0.0f;\r\n\tinvSampleFreq = 1.0f / sampleFreqDef;\r\n\tanglesComputed = 0;\r\n}\r\n\r\nvoid Madgwick::update(float gx, float gy, float gz, float ax, float ay, float az, float mx, float my, float mz) {\r\n\tfloat recipNorm;\r\n\tfloat s0, s1, s2, s3;\r\n\tfloat qDot1, qDot2, qDot3, qDot4;\r\n\tfloat hx, hy;\r\n\tfloat _2q0mx, _2q0my, _2q0mz, _2q1mx, _2bx, _2bz, _4bx, _4bz, _2q0, _2q1, _2q2, _2q3, _2q0q2, _2q2q3, q0q0, q0q1, q0q2, q0q3, q1q1, q1q2, q1q3, q2q2, q2q3, q3q3;\r\n\r\n\t// Use IMU algorithm if magnetometer measurement invalid (avoids NaN in magnetometer normalisation)\r\n\tif((mx == 0.0f) && (my == 0.0f) && (mz == 0.0f)) {\r\n\t\tupdateIMU(gx, gy, gz, ax, ay, az);\r\n\t\treturn;\r\n\t}\r\n\r\n\t// Convert gyroscope degrees/sec to radians/sec\r\n\tgx *= 0.0174533f;\r\n\tgy *= 0.0174533f;\r\n\tgz *= 0.0174533f;\r\n\r\n\t// Rate of change of quaternion from gyroscope\r\n\tqDot1 = 0.5f * (-q1 * gx - q2 * gy - q3 * gz);\r\n\tqDot2 = 0.5f * (q0 * gx + q2 * gz - q3 * gy);\r\n\tqDot3 = 0.5f * (q0 * gy - q1 * gz + q3 * gx);\r\n\tqDot4 = 0.5f * (q0 * gz + q1 * gy - q2 * gx);\r\n\r\n\t// Compute feedback only if accelerometer measurement valid (avoids NaN in accelerometer normalisation)\r\n\tif(!((ax == 0.0f) && (ay == 0.0f) && (az == 0.0f))) {\r\n\r\n\t\t// Normalise accelerometer measurement\r\n\t\trecipNorm = invSqrt(ax * ax + ay * ay + az * az);\r\n\t\tax *= recipNorm;\r\n\t\tay *= recipNorm;\r\n\t\taz *= recipNorm;\r\n\r\n\t\t// Normalise magnetometer measurement\r\n\t\trecipNorm = invSqrt(mx * mx + my * my + mz * mz);\r\n\t\tmx *= recipNorm;\r\n\t\tmy *= recipNorm;\r\n\t\tmz *= recipNorm;\r\n\r\n\t\t// Auxiliary variables to avoid repeated arithmetic\r\n\t\t_2q0mx = 2.0f * q0 * mx;\r\n\t\t_2q0my = 2.0f * q0 * my;\r\n\t\t_2q0mz = 2.0f * q0 * mz;\r\n\t\t_2q1mx = 2.0f * q1 * mx;\r\n\t\t_2q0 = 2.0f * q0;\r\n\t\t_2q1 = 2.0f * q1;\r\n\t\t_2q2 = 2.0f * q2;\r\n\t\t_2q3 = 2.0f * q3;\r\n\t\t_2q0q2 = 2.0f * q0 * q2;\r\n\t\t_2q2q3 = 2.0f * q2 * q3;\r\n\t\tq0q0 = q0 * q0;\r\n\t\tq0q1 = q0 * q1;\r\n\t\tq0q2 = q0 * q2;\r\n\t\tq0q3 = q0 * q3;\r\n\t\tq1q1 = q1 * q1;\r\n\t\tq1q2 = q1 * q2;\r\n\t\tq1q3 = q1 * q3;\r\n\t\tq2q2 = q2 * q2;\r\n\t\tq2q3 = q2 * q3;\r\n\t\tq3q3 = q3 * q3;\r\n\r\n\t\t// Reference direction of Earth's magnetic field\r\n\t\thx = mx * q0q0 - _2q0my * q3 + _2q0mz * q2 + mx * q1q1 + _2q1 * my * q2 + _2q1 * mz * q3 - mx * q2q2 - mx * q3q3;\r\n\t\thy = _2q0mx * q3 + my * q0q0 - _2q0mz * q1 + _2q1mx * q2 - my * q1q1 + my * q2q2 + _2q2 * mz * q3 - my * q3q3;\r\n\t\t_2bx = sqrtf(hx * hx + hy * hy);\r\n\t\t_2bz = -_2q0mx * q2 + _2q0my * q1 + mz * q0q0 + _2q1mx * q3 - mz * q1q1 + _2q2 * my * q3 - mz * q2q2 + mz * q3q3;\r\n\t\t_4bx = 2.0f * _2bx;\r\n\t\t_4bz = 2.0f * _2bz;\r\n\r\n\t\t// Gradient decent algorithm corrective step\r\n\t\ts0 = -_2q2 * (2.0f * q1q3 - _2q0q2 - ax) + _2q1 * (2.0f * q0q1 + _2q2q3 - ay) - _2bz * q2 * (_2bx * (0.5f - q2q2 - q3q3) + _2bz * (q1q3 - q0q2) - mx) + (-_2bx * q3 + _2bz * q1) * (_2bx * (q1q2 - q0q3) + _2bz * (q0q1 + q2q3) - my) + _2bx * q2 * (_2bx * (q0q2 + q1q3) + _2bz * (0.5f - q1q1 - q2q2) - mz);\r\n\t\ts1 = _2q3 * (2.0f * q1q3 - _2q0q2 - ax) + _2q0 * (2.0f * q0q1 + _2q2q3 - ay) - 4.0f * q1 * (1 - 2.0f * q1q1 - 2.0f * q2q2 - az) + _2bz * q3 * (_2bx * (0.5f - q2q2 - q3q3) + _2bz * (q1q3 - q0q2) - mx) + (_2bx * q2 + _2bz * q0) * (_2bx * (q1q2 - q0q3) + _2bz * (q0q1 + q2q3) - my) + (_2bx * q3 - _4bz * q1) * (_2bx * (q0q2 + q1q3) + _2bz * (0.5f - q1q1 - q2q2) - mz);\r\n\t\ts2 = -_2q0 * (2.0f * q1q3 - _2q0q2 - ax) + _2q3 * (2.0f * q0q1 + _2q2q3 - ay) - 4.0f * q2 * (1 - 2.0f * q1q1 - 2.0f * q2q2 - az) + (-_4bx * q2 - _2bz * q0) * (_2bx * (0.5f - q2q2 - q3q3) + _2bz * (q1q3 - q0q2) - mx) + (_2bx * q1 + _2bz * q3) * (_2bx * (q1q2 - q0q3) + _2bz * (q0q1 + q2q3) - my) + (_2bx * q0 - _4bz * q2) * (_2bx * (q0q2 + q1q3) + _2bz * (0.5f - q1q1 - q2q2) - mz);\r\n\t\ts3 = _2q1 * (2.0f * q1q3 - _2q0q2 - ax) + _2q2 * (2.0f * q0q1 + _2q2q3 - ay) + (-_4bx * q3 + _2bz * q1) * (_2bx * (0.5f - q2q2 - q3q3) + _2bz * (q1q3 - q0q2) - mx) + (-_2bx * q0 + _2bz * q2) * (_2bx * (q1q2 - q0q3) + _2bz * (q0q1 + q2q3) - my) + _2bx * q1 * (_2bx * (q0q2 + q1q3) + _2bz * (0.5f - q1q1 - q2q2) - mz);\r\n\t\trecipNorm = invSqrt(s0 * s0 + s1 * s1 + s2 * s2 + s3 * s3); // normalise step magnitude\r\n\t\ts0 *= recipNorm;\r\n\t\ts1 *= recipNorm;\r\n\t\ts2 *= recipNorm;\r\n\t\ts3 *= recipNorm;\r\n\r\n\t\t// Apply feedback step\r\n\t\tqDot1 -= beta * s0;\r\n\t\tqDot2 -= beta * s1;\r\n\t\tqDot3 -= beta * s2;\r\n\t\tqDot4 -= beta * s3;\r\n\t}\r\n\r\n\t// Integrate rate of change of quaternion to yield quaternion\r\n\tq0 += qDot1 * invSampleFreq;\r\n\tq1 += qDot2 * invSampleFreq;\r\n\tq2 += qDot3 * invSampleFreq;\r\n\tq3 += qDot4 * invSampleFreq;\r\n\r\n\t// Normalise quaternion\r\n\trecipNorm = invSqrt(q0 * q0 + q1 * q1 + q2 * q2 + q3 * q3);\r\n\tq0 *= recipNorm;\r\n\tq1 *= recipNorm;\r\n\tq2 *= recipNorm;\r\n\tq3 *= recipNorm;\r\n\tanglesComputed = 0;\r\n}\r\n\r\n//-------------------------------------------------------------------------------------------\r\n// IMU algorithm update\r\n\r\nvoid Madgwick::updateIMU(float gx, float gy, float gz, float ax, float ay, float az) {\r\n\tfloat recipNorm;\r\n\tfloat s0, s1, s2, s3;\r\n\tfloat qDot1, qDot2, qDot3, qDot4;\r\n\tfloat _2q0, _2q1, _2q2, _2q3, _4q0, _4q1, _4q2 ,_8q1, _8q2, q0q0, q1q1, q2q2, q3q3;\r\n\r\n\t// Convert gyroscope degrees/sec to radians/sec\r\n\tgx *= 0.0174533f;\r\n\tgy *= 0.0174533f;\r\n\tgz *= 0.0174533f;\r\n\r\n\t// Rate of change of quaternion from gyroscope\r\n\tqDot1 = 0.5f * (-q1 * gx - q2 * gy - q3 * gz);\r\n\tqDot2 = 0.5f * (q0 * gx + q2 * gz - q3 * gy);\r\n\tqDot3 = 0.5f * (q0 * gy - q1 * gz + q3 * gx);\r\n\tqDot4 = 0.5f * (q0 * gz + q1 * gy - q2 * gx);\r\n\r\n\t// Compute feedback only if accelerometer measurement valid (avoids NaN in accelerometer normalisation)\r\n\tif(!((ax == 0.0f) && (ay == 0.0f) && (az == 0.0f))) {\r\n\r\n\t\t// Normalise accelerometer measurement\r\n\t\trecipNorm = invSqrt(ax * ax + ay * ay + az * az);\r\n\t\tax *= recipNorm;\r\n\t\tay *= recipNorm;\r\n\t\taz *= recipNorm;\r\n\r\n\t\t// Auxiliary variables to avoid repeated arithmetic\r\n\t\t_2q0 = 2.0f * q0;\r\n\t\t_2q1 = 2.0f * q1;\r\n\t\t_2q2 = 2.0f * q2;\r\n\t\t_2q3 = 2.0f * q3;\r\n\t\t_4q0 = 4.0f * q0;\r\n\t\t_4q1 = 4.0f * q1;\r\n\t\t_4q2 = 4.0f * q2;\r\n\t\t_8q1 = 8.0f * q1;\r\n\t\t_8q2 = 8.0f * q2;\r\n\t\tq0q0 = q0 * q0;\r\n\t\tq1q1 = q1 * q1;\r\n\t\tq2q2 = q2 * q2;\r\n\t\tq3q3 = q3 * q3;\r\n\r\n\t\t// Gradient decent algorithm corrective step\r\n\t\ts0 = _4q0 * q2q2 + _2q2 * ax + _4q0 * q1q1 - _2q1 * ay;\r\n\t\ts1 = _4q1 * q3q3 - _2q3 * ax + 4.0f * q0q0 * q1 - _2q0 * ay - _4q1 + _8q1 * q1q1 + _8q1 * q2q2 + _4q1 * az;\r\n\t\ts2 = 4.0f * q0q0 * q2 + _2q0 * ax + _4q2 * q3q3 - _2q3 * ay - _4q2 + _8q2 * q1q1 + _8q2 * q2q2 + _4q2 * az;\r\n\t\ts3 = 4.0f * q1q1 * q3 - _2q1 * ax + 4.0f * q2q2 * q3 - _2q2 * ay;\r\n\t\trecipNorm = invSqrt(s0 * s0 + s1 * s1 + s2 * s2 + s3 * s3); // normalise step magnitude\r\n\t\ts0 *= recipNorm;\r\n\t\ts1 *= recipNorm;\r\n\t\ts2 *= recipNorm;\r\n\t\ts3 *= recipNorm;\r\n\r\n\t\t// Apply feedback step\r\n\t\tqDot1 -= beta * s0;\r\n\t\tqDot2 -= beta * s1;\r\n\t\tqDot3 -= beta * s2;\r\n\t\tqDot4 -= beta * s3;\r\n\t}\r\n\r\n\t// Integrate rate of change of quaternion to yield quaternion\r\n\tq0 += qDot1 * invSampleFreq;\r\n\tq1 += qDot2 * invSampleFreq;\r\n\tq2 += qDot3 * invSampleFreq;\r\n\tq3 += qDot4 * invSampleFreq;\r\n\r\n\t// Normalise quaternion\r\n\trecipNorm = invSqrt(q0 * q0 + q1 * q1 + q2 * q2 + q3 * q3);\r\n\tq0 *= recipNorm;\r\n\tq1 *= recipNorm;\r\n\tq2 *= recipNorm;\r\n\tq3 *= recipNorm;\r\n\tanglesComputed = 0;\r\n}\r\n\r\n//-------------------------------------------------------------------------------------------\r\n// Fast inverse square-root\r\n// See: http://en.wikipedia.org/wiki/Fast_inverse_square_root\r\n\r\nfloat Madgwick::invSqrt(float x) {\r\n\tfloat halfx = 0.5f * x;\r\n\tfloat y = x;\r\n\tlong i = *(long*)&y;\r\n\ti = 0x5f3759df - (i>>1);\r\n\ty = *(float*)&i;\r\n\ty = y * (1.5f - (halfx * y * y));\r\n\ty = y * (1.5f - (halfx * y * y));\r\n\treturn y;\r\n}\r\n\r\n//-------------------------------------------------------------------------------------------\r\n\r\nvoid Madgwick::computeAngles()\r\n{\r\n\troll = atan2f(q0*q1 + q2*q3, 0.5f - q1*q1 - q2*q2);\r\n\tpitch = asinf(-2.0f * (q1*q3 - q0*q2));\r\n\tyaw = atan2f(q1*q2 + q0*q3, 0.5f - q2*q2 - q3*q3);\r\n\tanglesComputed = 1;\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/IMU/MadgwickAHRS.h",
    "content": "//=============================================================================================\r\n// MadgwickAHRS.h\r\n//=============================================================================================\r\n//\r\n// Implementation of Madgwick's IMU and AHRS algorithms.\r\n// See: http://www.x-io.co.uk/open-source-imu-and-ahrs-algorithms/\r\n//\r\n// From the x-io website \"Open-source resources available on this website are\r\n// provided under the GNU General Public Licence unless an alternative licence\r\n// is provided in source.\"\r\n//\r\n// Date\t\t\tAuthor          Notes\r\n// 29/09/2011\tSOH Madgwick    Initial release\r\n// 02/10/2011\tSOH Madgwick\tOptimised for reduced CPU load\r\n//\r\n//=============================================================================================\r\n#ifndef MadgwickAHRS_h\r\n#define MadgwickAHRS_h\r\n#include <math.h>\r\n\r\n//--------------------------------------------------------------------------------------------\r\n// Variable declaration\r\nclass Madgwick{\r\nprivate:\r\n    static float invSqrt(float x);\r\n    float beta;\t\t\t\t// algorithm gain\r\n    float roll;\r\n    float pitch;\r\n    float yaw;\r\n    char anglesComputed;\r\n    void computeAngles();\r\n\r\n//-------------------------------------------------------------------------------------------\r\n// Function declarations\r\npublic:\r\n    float invSampleFreq;\r\n\r\n    float q0;\r\n    float q1;\r\n    float q2;\r\n    float q3;\t// quaternion of sensor frame relative to auxiliary frame\r\n\r\n    Madgwick(void);\r\n    void begin(float sampleFrequency) { invSampleFreq = 1.0f / sampleFrequency; }\r\n    void update(float gx, float gy, float gz, float ax, float ay, float az, float mx, float my, float mz);\r\n    void updateIMU(float gx, float gy, float gz, float ax, float ay, float az);\r\n    //float getPitch(){return atan2f(2.0f * q2 * q3 - 2.0f * q0 * q1, 2.0f * q0 * q0 + 2.0f * q3 * q3 - 1.0f);};\r\n    //float getRoll(){return -1.0f * asinf(2.0f * q1 * q3 + 2.0f * q0 * q2);};\r\n    //float getYaw(){return atan2f(2.0f * q1 * q2 - 2.0f * q0 * q3, 2.0f * q0 * q0 + 2.0f * q1 * q1 - 1.0f);};\r\n    float getRoll() {\r\n        if (!anglesComputed) computeAngles();\r\n        return roll * 57.29578f;\r\n    }\r\n    float getPitch() {\r\n        if (!anglesComputed) computeAngles();\r\n        return pitch * 57.29578f;\r\n    }\r\n    float getYaw() {\r\n        if (!anglesComputed) computeAngles();\r\n        return yaw * 57.29578f + 180.0f;\r\n    }\r\n    float getRollRadians() {\r\n        if (!anglesComputed) computeAngles();\r\n        return roll;\r\n    }\r\n    float getPitchRadians() {\r\n        if (!anglesComputed) computeAngles();\r\n        return pitch;\r\n    }\r\n    float getYawRadians() {\r\n        if (!anglesComputed) computeAngles();\r\n        return yaw;\r\n    }\r\n};\r\n#endif\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/IMU/imu_selector.cpp",
    "content": "#include \"imu_selector.h\"\n\nbool cIMUDevice::begin( void )\n{\n  bool result = false;\n\n  if(DEV1.begin() == true)\n  {\n    device_model = MPU9250;\n    result = true;\n  }\n  else if (DEV2.begin() == true)\n  {\n    device_model = ICM20468;\n    result = true;\n  }\n  \n  return result;\n}\n\nvoid cIMUDevice::init( void )\n{\n  switch(device_model)\n  {\n    case MPU9250:\n      DEV1.init();\n      break;\n    case ICM20468:\n      DEV2.init();\n      break;\n    default : break;\n  }\n}\n\nvoid cIMUDevice::gyro_init( void )\n{\n  switch(device_model)\n  {\n    case MPU9250:\n      DEV1.gyro_init();\n      break;\n    case ICM20468:\n      DEV2.gyro_init();\n      break;\n    default : break;\n  }\n}\n\nvoid cIMUDevice::gyro_get_adc( void )\n{\n  switch(device_model)\n  {\n    case MPU9250:\n      DEV1.gyro_get_adc();\n      memcpy(gyroRAW,DEV1.gyroRAW,3*sizeof(int16_t));\n      memcpy(gyroADC,DEV1.gyroADC,3*sizeof(int16_t));\n      break;\n    case ICM20468:\n      DEV2.gyro_get_adc();\n      memcpy(gyroRAW,DEV2.gyroRAW,3*sizeof(int16_t));\n      memcpy(gyroADC,DEV2.gyroADC,3*sizeof(int16_t));\n      break;\n    default : break;\n  }\n}\n\nvoid cIMUDevice::gyro_common()\n{\n  switch(device_model)\n  {\n    case MPU9250:\n      DEV1.gyro_common();\n      break;\n    case ICM20468:\n      DEV2.gyro_common();\n      break;\n    default : break;\n  }\n}\n\nvoid cIMUDevice::gyro_cali_start()\n{\n  switch(device_model)\n  {\n    case MPU9250:\n      DEV1.gyro_cali_start();\n      break;\n    case ICM20468:\n      DEV2.gyro_cali_start();\n      break;\n    default : break; \n  }\n}\n\nbool cIMUDevice::gyro_cali_get_done()\n{\n  bool result = false;\n\n  switch(device_model)\n  {\n    case MPU9250:\n      result = DEV1.gyro_cali_get_done();\n      break;\n    case ICM20468:\n      result = DEV2.gyro_cali_get_done();\n      break;\n    default : break;\n  }\n\n  return result;\n}\n\nvoid cIMUDevice::acc_init( void )\n{\n  switch(device_model)\n  {\n    case MPU9250:\n      DEV1.acc_init();\n      break;\n    case ICM20468:\n      DEV2.acc_init();\n      break;\n    default : break;\n  }\n}\n\nvoid cIMUDevice::acc_get_adc( void )\n{\n  switch(device_model)\n  {\n    case MPU9250:\n      DEV1.acc_get_adc();\n      memcpy(accRAW,DEV1.accRAW,3*sizeof(int16_t));\n      memcpy(accADC,DEV1.accADC,3*sizeof(int16_t));\n      break;\n    case ICM20468:\n      DEV2.acc_get_adc();\n      memcpy(accRAW,DEV2.accRAW,3*sizeof(int16_t));\n      memcpy(accADC,DEV2.accADC,3*sizeof(int16_t));\n      break;\n    default : break;\n  }\n}\n\nvoid cIMUDevice::acc_common( void )\n{\n  switch(device_model)\n  {\n    case MPU9250:\n      DEV1.acc_common();\n      break;\n    case ICM20468:\n      DEV2.acc_common();\n      break;\n    default : break;\n  }\n}\n\nvoid cIMUDevice::acc_cali_start()\n{\n  switch(device_model)\n  {\n    case MPU9250:\n      DEV1.acc_cali_start();\n      break;\n    case ICM20468:\n      DEV2.acc_cali_start();\n      break;\n    default : break;\n  }\n}\n\nbool cIMUDevice::acc_cali_get_done()\n{\n  bool result = false;\n\n  switch(device_model)\n  {\n    case MPU9250:\n    result = DEV1.acc_cali_get_done();\n    break;\n    case ICM20468:\n    result = DEV2.acc_cali_get_done();\n    break;\n    default : break;\n  }\n  return result;\n}\n\nvoid cIMUDevice::mag_init( void )\n{\n  switch(device_model)\n  {\n    case MPU9250:\n      DEV1.mag_init();\n      break;\n    case ICM20468:\n      DEV2.mag_init();\n      break;\n    default : break;\n  }\n}\n\nvoid cIMUDevice::mag_get_adc( void )\n{\n  switch(device_model)\n  {\n    case MPU9250:\n      DEV1.mag_get_adc();\n      memcpy(magRAW,DEV1.magRAW,3*sizeof(int16_t));\n      memcpy(magADC,DEV1.magADC,3*sizeof(int16_t));\n      break;\n    case ICM20468:\n      DEV2.mag_get_adc();\n      memcpy(magRAW,DEV2.magRAW,3*sizeof(int16_t));\n      memcpy(magADC,DEV2.magADC,3*sizeof(int16_t));\n      break;\n    default : break;\n  }\n}\nvoid cIMUDevice::mag_common()\n{\n  switch(device_model)\n  {\n    case MPU9250:\n      DEV1.mag_common();\n      break;\n    case ICM20468:\n      DEV2.mag_common();\n      break;\n    default : break;\n  }\n}\nvoid cIMUDevice::mag_cali_start()\n{\n  switch(device_model)\n  {\n    case MPU9250:\n      DEV1.mag_cali_start();\n      break;\n    case ICM20468:\n      DEV2.mag_cali_start();\n      break;\n    default : break;\n  }\n}\n\nbool cIMUDevice::mag_cali_get_done()\n{\n  bool result = false;\n\n  switch(device_model)\n  {\n    case MPU9250:\n      result = DEV1.mag_cali_get_done();\n      break;\n    case ICM20468:\n      result = DEV2.mag_cali_get_done();\n      break;\n    default : break;\n  }\n\n  return result;\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/IMU/imu_selector.h",
    "content": "#ifndef __IMU_SELECTOR_H__\n#define __IMU_SELECTOR_H__\n\n\n#include \"ICM20648.h\"\n#include \"MPU9250.h\"\n\n\nclass cIMUDevice\n{\n public:  \n  bool begin( void );\n  void init( void );\n  void gyro_init( void );\n  void gyro_get_adc( void );\n  void gyro_common();\n  void gyro_cali_start();\n  bool gyro_cali_get_done();\n  void acc_init( void );\n  void acc_get_adc( void );\n  void acc_common( void );\n  void acc_cali_start();\n  bool acc_cali_get_done();\n  void mag_init( void );\n  void mag_get_adc( void );\n  void mag_common();\n  void mag_cali_start();\n  bool mag_cali_get_done();\n\n public : \n  bool     bConnected;\n  \n  int16_t  gyroADC[3];\n  int16_t  gyroRAW[3];\n  int16_t  gyroZero[3];\n\n  int16_t  accADC[3];\n  int16_t  accRAW[3];\n  int16_t  accZero[3];\n\n  int16_t  magADC[3];\n  int16_t  magRAW[3];\n  int16_t  magZero[3];\n\n  int16_t  gyroData[3];\n  int16_t  accSmooth[3];\n\n  uint16_t calibratingG;\n  uint16_t calibratingA;\n  uint16_t calibratingM;\n\n  int16_t AK8963_ASA[3];\n\n private:\n  cMPU9250 DEV1;\n  cICM20648 DEV2;\n\n  uint8_t device_model;\n\n  enum DeviceModel\n  {\n    MPU9250=1,\n    ICM20468\n  };\n};\n\n#endif\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/IMU/imu_spi.cpp",
    "content": "#include <Arduino.h>\r\n#include <SPI.h>\r\n#include \"imu_spi.h\"\r\n#include \"MPU9250_REGS.h\"\r\n\r\n\r\n\r\n\r\n\r\nvoid imu_spi_init(void)\r\n{\r\n  pinMode( BDPIN_SPI_CS_IMU, OUTPUT );\r\n\r\n  SPI_IMU.begin();\r\n  SPI_IMU.setDataMode( SPI_MODE0 );\r\n  SPI_IMU.setBitOrder( MSBFIRST );\r\n  SPI_IMU.setClockDivider( SPI_CLOCK_DIV128 ); // 1MHz\r\n  digitalWrite(BDPIN_SPI_CS_IMU, HIGH);\r\n  delay(100);\r\n}\r\n\r\nvoid imu_spi_initFast(void)\r\n{\r\n  SPI_IMU.begin();\r\n  SPI_IMU.setDataMode( SPI_MODE3 );\r\n  SPI_IMU.setBitOrder( MSBFIRST );\r\n  SPI_IMU.setClockDivider( SPI_CLOCK_DIV8 ); // 1MHz\r\n  digitalWrite(BDPIN_SPI_CS_IMU, HIGH);\r\n  delay(200);\r\n}\r\n\r\nint  imu_spi_writes(uint8_t slave_addr, uint8_t reg_addr, uint8_t length, uint8_t *data)\r\n{\r\n  uint32_t i;\r\n\r\n\tUNUSED(slave_addr);\r\n\r\n  digitalWrite( BDPIN_SPI_CS_IMU, LOW);\r\n  SPI_IMU.transfer( reg_addr );\r\n\r\n  for( i=0; i<length; i++ )\r\n  {\r\n    SPI_IMU.transfer( data[i] );\r\n  }\r\n  digitalWrite( BDPIN_SPI_CS_IMU, HIGH);\r\n  delay_ms(1);\r\n\treturn 0;\r\n}\r\n\r\nint imu_spi_reads(uint8_t slave_addr, uint8_t reg_addr, uint8_t length, uint8_t *data)\r\n{\r\n  uint32_t i;\r\n  //uint8_t read_value;\r\n\r\n\tUNUSED(slave_addr);\r\n\r\n  digitalWrite( BDPIN_SPI_CS_IMU, LOW);\r\n  SPI_IMU.transfer( reg_addr | 0x80 );  // reg | 0x80 to denote read\r\n  for( i=0; i<length; i++ )\r\n  {\r\n    data[i] = SPI_IMU.transfer( 0xFF );\r\n  }\r\n  digitalWrite( BDPIN_SPI_CS_IMU, HIGH);\r\n\treturn 0;\r\n}\r\n\r\nint imu_spi_ak8963_reads(uint8_t akm_addr, uint8_t reg_addr, uint8_t len, uint8_t *data)\r\n{\r\n\tuint8_t index = 0;\r\n\tuint8_t status = 0;\r\n\tuint32_t timeout = 0;\r\n\tuint8_t tmp = 0;\r\n\r\n\ttmp = akm_addr | MPU9250_I2C_READ;\r\n\timu_spi_writes(MPU9250_SPIx_ADDR, MPU9250_I2C_SLV4_ADDR, 1, &tmp);\r\n\tdelay(1);\r\n\twhile(index < len){\r\n\t\ttmp = reg_addr + index;\r\n\t\timu_spi_writes(MPU9250_SPIx_ADDR, MPU9250_I2C_SLV4_REG, 1, &tmp);\r\n\t\tdelay(1);\r\n\t\ttmp = MPU9250_I2C_SLV4_EN;\r\n\t\timu_spi_writes(MPU9250_SPIx_ADDR, MPU9250_I2C_SLV4_CTRL, 1, &tmp);\r\n\t\tdelay(1);\r\n\r\n\t\tdo {\r\n\t\t\tif (timeout++ > 50){\r\n\t\t\t\treturn -2;\r\n\t\t\t}\r\n\t\t\timu_spi_reads(MPU9250_SPIx_ADDR, MPU9250_I2C_MST_STATUS, 1, &status);\r\n\t\t\tdelay_ms(2);\r\n\t\t} while ((status & MPU9250_I2C_SLV4_DONE) == 0);\r\n\t\timu_spi_reads(MPU9250_SPIx_ADDR, MPU9250_I2C_SLV4_DI, 1, data + index);\r\n\t\tdelay_ms(1);\r\n\t\tindex++;\r\n\t}\r\n\treturn 0;\r\n}\r\n\r\nint imu_spi_ak8963_writes(uint8_t akm_addr, uint8_t reg_addr, uint8_t len, uint8_t *data)\r\n{\r\n  uint32_t timeout = 0;\r\n\tuint8_t status = 0;\r\n\tuint8_t tmp = 0;\r\n\tuint8_t index = 0;\r\n\r\n\ttmp = akm_addr;\r\n\timu_spi_writes(MPU9250_SPIx_ADDR, MPU9250_I2C_SLV4_ADDR, 1, &tmp);\r\n\tdelay_ms(2);\r\n\r\n\twhile(index < len){\r\n\t\ttmp = reg_addr + index;\r\n\t\timu_spi_writes(MPU9250_SPIx_ADDR, MPU9250_I2C_SLV4_REG, 1, &tmp);\r\n\t\tdelay_ms(2);\r\n\t\timu_spi_writes(MPU9250_SPIx_ADDR, MPU9250_I2C_SLV4_DO, 1, data + index);\r\n\t\tdelay_ms(2);\r\n\t\ttmp = MPU9250_I2C_SLV4_EN;\r\n\t\timu_spi_writes(MPU9250_SPIx_ADDR, MPU9250_I2C_SLV4_CTRL, 1, &tmp);\r\n\t\tdelay_ms(2);\r\n\r\n\t\tdo {\r\n\t\t\tif (timeout++ > 50)\r\n\t\t\t\treturn -2;\r\n\t\t\timu_spi_reads(MPU9250_SPIx_ADDR, MPU9250_I2C_MST_STATUS, 1, &status);\r\n\t\t\tdelay_ms(2);\r\n\t\t} while ((status & MPU9250_I2C_SLV4_DONE) == 0);\r\n\t\tif (status & MPU9250_I2C_SLV4_NACK)\r\n\t\t\treturn -3;\r\n\t\tindex++;\r\n\t}\r\n\treturn 0;\r\n}\r\n\r\nint imu_spi_write(uint8_t addr, uint8_t reg_addr, uint8_t data)\r\n{\r\n\tUNUSED(addr);\r\n\r\n\tdigitalWrite( BDPIN_SPI_CS_IMU, LOW);\r\n\tSPI_IMU.transfer(reg_addr);\r\n\tSPI_IMU.transfer(data);\r\n\tdigitalWrite( BDPIN_SPI_CS_IMU, HIGH);\r\n\treturn 0;\r\n}\r\n\r\nuint8_t imu_spi_read(uint8_t addr, uint8_t reg_addr)\r\n{\r\n\tUNUSED(addr);\r\n\r\n\tuint8_t dummy = 0;\r\n\tuint8_t data = 0;\r\n\r\n\tdigitalWrite( BDPIN_SPI_CS_IMU, LOW);\r\n\tSPI_IMU.transfer(0x80 | reg_addr);\r\n\tdata = SPI_IMU.transfer(dummy);\r\n\tdigitalWrite( BDPIN_SPI_CS_IMU, HIGH);\r\n\treturn data;\r\n}\r\n\r\nint imu_spi_ak8963_write(uint8_t akm_addr, uint8_t reg_addr, uint8_t data)\r\n{\r\n  uint8_t param[1];\r\n\r\n  param[0] = data;\r\n\r\n  return imu_spi_ak8963_writes(akm_addr,reg_addr, 1, param);\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/IMU/imu_spi.h",
    "content": "#ifndef _IMU_SPI_H_\r\n#define _IMU_SPI_H_\r\n\r\n#if defined(__cplusplus)\r\nextern \"C\" {\r\n#endif\r\n\r\n#include <inttypes.h>\r\n\r\nvoid imu_spi_init(void);\r\nvoid imu_spi_initFast(void);\r\nint  imu_spi_reads(uint8_t slave_addr, uint8_t reg_addr, uint8_t length, uint8_t *data);\r\nint  imu_spi_writes(uint8_t slave_addr, uint8_t reg_addr, uint8_t length, uint8_t *data);\r\nint  imu_spi_ak8963_reads(uint8_t akm_addr, uint8_t reg_addr, uint8_t len, uint8_t *data);\r\nint  imu_spi_ak8963_writes(uint8_t akm_addr, uint8_t reg_addr, uint8_t len, uint8_t *data);\r\n\r\nint imu_spi_ak8963_write(uint8_t akm_addr, uint8_t reg_addr, uint8_t data);\r\n\r\nuint8_t imu_spi_read(uint8_t addr, uint8_t reg_addr);\r\nint     imu_spi_write(uint8_t addr, uint8_t reg_addr, uint8_t data);\r\n\r\n\r\n#if defined(__cplusplus)\r\n}\r\n#endif\r\n\r\n#endif\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/IMU/keywords.txt",
    "content": "#######################################\n# Syntax Coloring Map For IMU\n#######################################\n\n#######################################\n# Datatypes (KEYWORD1)\n#######################################\ncIMU\tKEYWORD1\ncICM20648 KEYWORD1\ncIMUDevice KEYWORD1\nMadgwick KEYWORD1\ncMPU9250 KEYWORD1\n#######################################\n# Methods and Functions (KEYWORD2)\n#######################################\ngyro_init KEYWORD2\ngyro_get_adc KEYWORD2\ngyro_cali_start KEYWORD2\ngyro_common KEYWORD2\ngyro_cali_get_done KEYWORD2\nacc_init KEYWORD2\nacc_get_adc KEYWORD2\nacc_cali_start KEYWORD2\nacc_common KEYWORD2\nacc_cali_get_done KEYWORD2\nmag_init KEYWORD2\nmag_get_adc KEYWORD2\nmag_cali_start KEYWORD2\nmag_common KEYWORD2\nmag_cali_get_done KEYWORD2\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/LcdTouchPanel/LcdTouchPanel.cpp",
    "content": "#include <LcdTouchPanel.h>\n\nvoid tftInit()\n{\n\n    __SD_CS_DISABLE();\n    SPI.beginFast();\n    SPI.setDataMode(SPI_MODE3);\n    SPI.setBitOrder(MSBFIRST);\n    SPI.setClockDivider(SPI_CLOCK_DIV4);\n\n    Tft.lcd_init();\n    Tp.tp_init();\n}\n\nvoid getSingleTouchPoint(uint16_t* touch_list)\n{\n\n    //Make sure, that before reading the touch info, you must decrease the SPI speed under 2MHz. After finish this process, return to SPI_CLOCK_DIV4.\n    SPI.setClockDivider(SPI_CLOCK_DIV32);\n    Tp.tp_show_single_info(touch_list);\n    touch_list[XPOS] = constrain(touch_list[XPOS], TOUCH_MIN, TOUCH_MAX);\n    touch_list[YPOS] = constrain(touch_list[YPOS], TOUCH_MIN, TOUCH_MAX);\n    SPI.setClockDivider(SPI_CLOCK_DIV4);\n}\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/LcdTouchPanel/LcdTouchPanel.h",
    "content": "#include <SPI.h>\n#include \"Adafruit_GFX.h\"\n#include \"LCD.h\"\n#include \"XPT2046.h\"\n#include \"Touch.h\"\n#include <Fonts/FreeMonoBold12pt7b.h>\n#include <Fonts/FreeMonoBold9pt7b.h>\n\n#define XPOS 0\n#define YPOS 1\n\n#define TOUCH_MIN 127\n#define TOUCH_MAX 1950\n#define TOUCH_RANGE (TOUCH_MAX-TOUCH_MIN)\n\n#define LCD_MAX_X 240\n#define LCD_MAX_Y 320\n\nenum shape_list {CIRCLE, SQUARE};\n\nvoid getSingleTouchPoint(uint16_t* touch_list);\nvoid tftInit(void);\n    "
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/LcdTouchPanel/library.properties",
    "content": "name=LcdTouchPanel\nversion=0.1.0\nauthor=Daniel Seon\nmaintainer=Baram(chc@robotis.com)\nsentence=library for LcdTouchPanel\nparagraph=\ncategory=Data Processing\nurl=https://github.com/ROBOTIS-GIT/OpenCR\narchitectures=OpenCR\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OLLO/OLLO.cpp",
    "content": "/*\r\n * OLLO.cpp\r\n *\r\n *  Created on: 2013. 5. 30.\r\n *      Author: ROBOTIS CO,.LTD.\r\n */\r\n\r\n#include \"OLLO.h\"\r\n\r\n\r\nuint8_t before_color_num =0;\r\nuint8_t before_color_cnt =0;\r\nuint8_t after_color_value = 0;\r\nuint8_t bColorResult =0;\r\n\r\nOLLO::OLLO() {\r\n\t// TODO Auto-generated constructor stub\r\n\r\n}\r\n\r\nOLLO::~OLLO() {\r\n\t// TODO Auto-generated destructor stub\r\n}\r\nint average_cnt = 0;\r\nword long gwTheRmistor[108] = {\r\n  67747,64577,61571,58721,\r\n  56017,53452,51018,48707,\r\n  46513,44430,42450,40569,\r\n  38781,37081,35465,33927,\r\n  32464,31072,29747,28485,\r\n  27283,26138,25048,24008, 23017,\r\n  22072,21171,20311,19491,\r\n  18708,17960,17246,16565,\r\n  15913,15291,14696,14128,\r\n  13584,13064,12567,12091,\r\n  11636,11200,10782,10383,\r\n  10000, 9633, 9282,  8945,\r\n  8622, 8313, 8016, 7731,\r\n  7458, 7195, 6944, 6702,\r\n  6470, 6247, 6033, 5828,\r\n  5630, 5440, 5258, 5082,\r\n  4914, 4751, 4595, 4445,\r\n  4300, 4161, 4027, 3898,\r\n  3774, 3654, 3539, 3427,\r\n  3320, 3217, 3118, 3022,\r\n  2929, 2840, 2754, 2671,\r\n  2590, 2513, 2438, 2366,\r\n  2296, 2229, 2164, 2101,\r\n};\r\n\r\n\r\nvoid OLLO::begin(int devNum){\r\n\tif( devNum == 0 ){\r\n\t\t\treturn;\r\n\t}\r\n\tmMot_plus = 0;\r\n\tmMot_minus = 0;\r\n\r\n\r\n  pinMode(OLLO_SLEEP, OUTPUT);\r\n  digitalWrite(OLLO_SLEEP, HIGH);\r\n\r\n\tswitch(devNum){\r\n\tcase 1:\r\n\t\tpinMode(PORT1_SIG1, OUTPUT); //RED  (right)\r\n\t\tpinMode(PORT1_SIG2, OUTPUT); //BLUE (left)\r\n\t\tpinMode(PORT1_ADC, INPUT_ANALOG); //ADC input\r\n\t\tbreak;\r\n\tcase 2:\r\n\t\tpinMode(PORT2_SIG1, OUTPUT); //RED  (right)\r\n\t\tpinMode(PORT2_SIG2, OUTPUT); //BLUE (left)\r\n\t\tpinMode(PORT2_ADC, INPUT_ANALOG);//ADC input\r\n\t\tbreak;\r\n\tcase 3:\r\n\t\tpinMode(PORT3_SIG1, OUTPUT); //RED  (right)\r\n\t\tpinMode(PORT3_SIG2, OUTPUT); //BLUE (left)\r\n\t\tpinMode(PORT3_ADC, INPUT_ANALOG);//ADC input\r\n\t\tbreak;\r\n\tcase 4:\r\n\t\tpinMode(PORT4_SIG1, OUTPUT); //RED  (right)\r\n\t\tpinMode(PORT4_SIG2, OUTPUT); //BLUE (left)\r\n\t\tpinMode(PORT4_ADC, INPUT_ANALOG);//ADC input\r\n\t\tbreak;\r\n\tdefault:\r\n\t\tbreak;\r\n\t}\r\n}\r\nvoid OLLO::begin(int devNum, OlloDeviceIndex device_index){ //MAGNETIC SENSOR, Button, IR Sensor, and etc...\r\n\tif( devNum == 0 ){\r\n\t\t\treturn;\r\n\t}\r\n\tmMot_plus = 0;\r\n\tmMot_minus = 0;\r\n\r\n  pinMode(OLLO_SLEEP, OUTPUT);\r\n  digitalWrite(OLLO_SLEEP, HIGH);\r\n    \r\n\tswitch(devNum){\r\n\tcase 1:\r\n\t\tif(device_index == TOUCH_SENSOR || device_index == PIR_SENSOR || device_index == MAGNETIC_SENSOR){\r\n\t\t\tpinMode(PORT1_ADC, INPUT_PULLUP);\r\n\t\t}else if(device_index == ULTRASONIC_SENSOR || device_index == COLOR_SENSOR || device_index == TEMPERATURE_SENSOR ){\r\n\t\t\tpinMode(PORT1_ADC, INPUT_ANALOG);\r\n\t\t}\r\n\t\telse{\r\n\t\t\tpinMode(PORT1_ADC, INPUT_ANALOG); //ADC input\r\n\t\t}\r\n\r\n\t\tpinMode(PORT1_SIG1, OUTPUT); //SIG1\r\n\t\tpinMode(PORT1_SIG2, OUTPUT); //SIG2\r\n\t\tif(device_index == IR_SENSOR ){\r\n\t\t\tdigitalWrite(PORT1_SIG1,LOW); //SIG1 set to LOW\r\n\t\t\tdigitalWrite(PORT1_SIG2,LOW); //SIG2 set to LOW\r\n\t\t}\r\n\t\tbreak;\r\n\tcase 2:\r\n\t\tif(device_index == TOUCH_SENSOR || device_index == PIR_SENSOR || device_index == MAGNETIC_SENSOR){\r\n\t\t\tpinMode(PORT2_ADC, INPUT_PULLUP);\r\n\t\t}else if(device_index == ULTRASONIC_SENSOR || device_index == COLOR_SENSOR || device_index == TEMPERATURE_SENSOR ){\r\n\t\t\tpinMode(PORT2_ADC, INPUT_ANALOG);//ADC input\r\n\t\t}else{\r\n\t\t\tpinMode(PORT2_ADC, INPUT_ANALOG);//ADC input\r\n\t\t}\r\n\r\n\t\tpinMode(PORT2_SIG1, OUTPUT); //SIG1\r\n\t\tpinMode(PORT2_SIG2, OUTPUT); //SIG2\r\n\t\tif(device_index == IR_SENSOR ){\r\n\t\t\tdigitalWrite(PORT2_SIG1,LOW); //set to LOW\r\n\t\t\tdigitalWrite(PORT2_SIG2,LOW); //set to LOW\r\n\t\t}\r\n\t\tbreak;\r\n\tcase 3:\r\n\t\tif(device_index == TOUCH_SENSOR || device_index == PIR_SENSOR || device_index == MAGNETIC_SENSOR){\r\n\t\t\tpinMode(PORT3_ADC, INPUT_PULLUP);\r\n\t\t}else if(device_index == ULTRASONIC_SENSOR || device_index == COLOR_SENSOR || device_index == TEMPERATURE_SENSOR ){\r\n\t\t\tpinMode(PORT3_ADC, INPUT_ANALOG);//ADC input\r\n\t\t}else{\r\n\t\t\tpinMode(PORT3_ADC, INPUT_ANALOG);//ADC input\r\n\t\t}\r\n\r\n\t\tpinMode(PORT3_SIG1, OUTPUT); //SIG1\r\n\t\tpinMode(PORT3_SIG2, OUTPUT); //SIG2\r\n\t\tif(device_index == IR_SENSOR ){\r\n\t\t\tdigitalWrite(PORT3_SIG1,LOW); //set SIG1 to LOW\r\n\t\t\tdigitalWrite(PORT3_SIG2,LOW); //set SIG2 to LOW\r\n\t\t}\r\n\t\tbreak;\r\n\tcase 4:\r\n\t\tif(device_index == TOUCH_SENSOR || device_index == PIR_SENSOR || device_index == MAGNETIC_SENSOR ){\r\n\t\t\tpinMode(PORT4_ADC, INPUT_PULLUP);\r\n\t\t}else if(device_index == ULTRASONIC_SENSOR || device_index == COLOR_SENSOR || device_index == TEMPERATURE_SENSOR ){\r\n\t\t\tpinMode(PORT4_ADC, INPUT_ANALOG);//ADC input\r\n\t\t}else{\r\n\t\t\tpinMode(PORT4_ADC, INPUT_ANALOG);//ADC input\r\n\t\t}\r\n\r\n\t\tpinMode(PORT4_SIG1, OUTPUT); //SIG1\r\n\t\tpinMode(PORT4_SIG2, OUTPUT); //SIG2\r\n\t\tif(device_index == IR_SENSOR ){\r\n\t\t\tdigitalWrite(PORT4_SIG1,LOW); //set SIG1 to LOW\r\n\t\t\tdigitalWrite(PORT4_SIG2,LOW); //set SIG2 to LOW\r\n\t\t}\r\n\t\tbreak;\r\n\tdefault:\r\n\t\tbreak;\r\n\t}\r\n}\r\n\r\nvoid OLLO::begin(int devNum, OlloDeviceIndex device_index, voidFuncPtr handler){ //Button with handler function.\r\n\tif( devNum == 0 ){\r\n\t\treturn;\r\n\t}\r\n\tswitch(devNum){\r\n\tcase 1:\r\n\t\tif(device_index == TOUCH_SENSOR){\r\n\t\t\tpinMode(PORT1_ADC, INPUT_PULLUP);\r\n\t\t\tattachInterrupt(PORT1_ADC,handler, RISING);\r\n\t\t}\r\n\t\tbreak;\r\n\tcase 2:\r\n\t\tif(device_index == TOUCH_SENSOR){\r\n\t\t\tpinMode(PORT2_ADC, INPUT_PULLUP);\r\n\t\t\tattachInterrupt(PORT2_ADC,handler, RISING);\r\n\t\t}\r\n\t\tbreak;\r\n\tcase 3:\r\n\t\tif(device_index == TOUCH_SENSOR){\r\n\t\t\tpinMode(PORT3_ADC, INPUT_PULLUP);\r\n\t\t\tattachInterrupt(PORT3_ADC,handler, RISING);\r\n\t\t}\r\n\t\tbreak;\r\n\tcase 4:\r\n\t\tif(device_index == TOUCH_SENSOR){\r\n\t\t\tpinMode(PORT4_ADC, INPUT_PULLUP);\r\n\t\t\tattachInterrupt(PORT4_ADC,handler, RISING);\r\n\t\t}\r\n\t\tbreak;\r\n\tdefault:\r\n\t\tbreak;\r\n\t}\r\n}\r\n\r\n\r\nint OLLO::read(int devNum){ // general sensor reading method\r\n\tif( devNum == 0 ){\r\n\t\t\treturn 0;\r\n\t}\r\n\tswitch(devNum){\r\n\tcase 1:\r\n\t\treturn (int)analogRead(PORT1_ADC);\r\n\tcase 2:\r\n\t\treturn (int)analogRead(PORT2_ADC);\r\n\tcase 3:\r\n\t\treturn (int)analogRead(PORT3_ADC);\r\n\tcase 4:\r\n\t\treturn (int)analogRead(PORT4_ADC);\r\n\tdefault:\r\n\t\treturn 0;\r\n\t}\r\n\r\n}\r\nint OLLO::read(int devNum, OlloDeviceIndex device_index){ // IR SENSOR, Button, MAGNETIC SENSOR, and etc...\r\n\tint adcValue = 0;\r\n\r\n\tsigned int scount;\r\n\tword long vvalue = 0;\r\n\tuint32_t analogValue;\r\n\tint distance_value = 0;\r\n\tint dis_value = 0;\r\n\r\n\tsigned int average_value = 0;\r\n\tif( devNum == 0 ){\r\n\t\treturn 0;\r\n\t}\r\n\tswitch(devNum){\r\n\tcase 1:\r\n\t\tif(device_index == IR_SENSOR){\r\n\t\t\tdigitalWrite(PORT1_SIG2, HIGH);\r\n\t\t\tdelayMicroseconds(15);\r\n\t\t\tadcValue = analogRead(PORT1_ADC);\r\n\t\t\tdigitalWrite(PORT1_SIG2, LOW);\r\n\t\t\treturn adcValue;\r\n\t\t}else if(device_index == MAGNETIC_SENSOR || device_index == TOUCH_SENSOR  || device_index == PIR_SENSOR){\r\n\t\t\treturn digitalRead(PORT1_ADC);\r\n\t\t}else if(device_index == ULTRASONIC_SENSOR){\r\n\t\t\tdistance_value = (int)analogRead(PORT1_ADC);\r\n\t\t\tdis_value = (((distance_value * 0.24)/4) - 3);\r\n\t\t\taverage_cnt++;\r\n\t\t\taverage_value+=dis_value;\r\n\t\t\tif(average_cnt >= 100){\r\n\t\t\t\taverage_value/=100;\r\n\t\t\t\taverage_cnt = 0;\r\n\t\t\t}\r\n\t\t\t  return average_value;\r\n\t\t}else if(device_index == TEMPERATURE_SENSOR){\r\n\t\t\tanalogValue = analogRead(PORT1_ADC);\r\n\t\t\tvvalue = (1023 - analogValue) * 10000 /analogValue;\r\n\t\t\tfor(scount = -20; scount < 140; scount++){\r\n\t\t\t\tif(vvalue > gwTheRmistor[scount +20]){\r\n\t\t\t\t      return scount;\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t}\r\n\t\telse if(device_index == COLOR_SENSOR){\r\n\t\t\treturn this->detectColor(1);\r\n\t\t}else{\r\n\t\t\treturn (int)analogRead(PORT1_ADC);\r\n\t\t}\r\n\t\tbreak;\r\n\tcase 2:\r\n\t\tif(device_index == IR_SENSOR){\r\n\t\t\tdigitalWrite(PORT2_SIG2, HIGH);//digitalWrite(PORT1_SIG2, HIGH); -> digitalWrite(PORT2_SIG2, HIGH); 140324\r\n\t\t\tdelayMicroseconds(15);\r\n\t\t\tadcValue = analogRead(PORT2_ADC);//adcValue = analogRead(PORT1_ADC); -> adcValue = analogRead(PORT2_ADC); 140324\r\n\t\t\tdigitalWrite(PORT2_SIG2, LOW);//digitalWrite(PORT1_SIG2, LOW); -> digitalWrite(PORT2_SIG2, LOW);\r\n\t\t\treturn adcValue;\r\n\t\t}else if(device_index == MAGNETIC_SENSOR || device_index == TOUCH_SENSOR || device_index == PIR_SENSOR){\r\n\t\t\treturn digitalRead(PORT2_ADC);\r\n\t\t}else if(device_index == ULTRASONIC_SENSOR){\r\n\t\t\tdistance_value = (int)analogRead(PORT2_ADC); //analogRead(PORT1_ADC); -> analogRead(PORT2_ADC); 140324\r\n\t\t\tdis_value = (((distance_value * 0.24)/4) - 3);\r\n\t\t\taverage_cnt++;\r\n\t\t\taverage_value+=dis_value;\r\n\t\t\tif(average_cnt >= 100){\r\n\t\t\t\taverage_value/=100;\r\n\t\t\t\taverage_cnt = 0;\r\n\t\t\t}\r\n\t\t\t  return average_value;\r\n\t\t}else if(device_index == COLOR_SENSOR){\r\n\t\t\treturn this->detectColor(2);\r\n\t\t}\r\n\t\telse if(device_index == TEMPERATURE_SENSOR){\r\n\t\t\tanalogValue = analogRead(PORT2_ADC);\r\n\t\t\tvvalue = (1023 - analogValue) * 10000 /analogValue;\r\n\t\t\tfor(scount = -20; scount < 140; scount++){\r\n\t\t\t\tif(vvalue > gwTheRmistor[scount +20]){\r\n\t\t\t\t      return scount;\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t}\r\n\t\telse{\r\n\t\t\treturn (int)analogRead(PORT2_ADC);\r\n\t\t}\r\n\t\tbreak;\r\n\tcase 3:\r\n\t\tif(device_index == IR_SENSOR){\r\n\t\t\tdigitalWrite(PORT3_SIG2, HIGH);////digitalWrite(PORT1_SIG2, HIGH); -> digitalWrite(PORT3_SIG2, HIGH); 140324\r\n\t\t\tdelayMicroseconds(15);\r\n\t\t\tadcValue = analogRead(PORT3_ADC);//adcValue = analogRead(PORT1_ADC); -> adcValue = analogRead(PORT3_ADC); 140324\r\n\t\t\tdigitalWrite(PORT3_SIG2, LOW);//digitalWrite(PORT1_SIG2, LOW); -> digitalWrite(PORT3_SIG2, LOW);\r\n\t\t\treturn adcValue;\r\n\t\t}else if(device_index == MAGNETIC_SENSOR || device_index == TOUCH_SENSOR || device_index == PIR_SENSOR){\r\n\t\t\treturn digitalRead(PORT3_ADC);\r\n\t\t}else if(device_index == ULTRASONIC_SENSOR){\r\n\t\t\tdistance_value = (int)analogRead(PORT3_ADC); //analogRead(PORT1_ADC); -> analogRead(PORT3_ADC); 140324\r\n\t\t\tdis_value = (((distance_value * 0.24)/4) - 3);\r\n\t\t\taverage_cnt++;\r\n\t\t\taverage_value+=dis_value;\r\n\t\t\tif(average_cnt >= 100){\r\n\t\t\t\taverage_value/=100;\r\n\t\t\t\taverage_cnt = 0;\r\n\t\t\t}\r\n\t\t\t  return average_value;\r\n\t\t}else if(device_index == TEMPERATURE_SENSOR){\r\n\t\t\tanalogValue = analogRead(PORT3_ADC);\r\n\t\t\tvvalue = (1023 - analogValue) * 10000 /analogValue;\r\n\t\t\tfor(scount = -20; scount < 140; scount++){\r\n\t\t\t\tif(vvalue > gwTheRmistor[scount +20]){\r\n\t\t\t\t      return scount;\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t}else if(device_index == COLOR_SENSOR){\r\n\t\t\treturn OLLO::detectColor(3);\r\n\t\t}else{\r\n\t\t\treturn (int)analogRead(PORT3_ADC);\r\n\t\t}\r\n\t\tbreak;\r\n\tcase 4:\r\n\t\tif(device_index == IR_SENSOR){\r\n\t\t\tdigitalWrite(PORT4_SIG2, HIGH); //digitalWrite(PORT1_SIG2, HIGH); -> digitalWrite(PORT4_SIG2, HIGH); 140324\r\n\t\t\tdelayMicroseconds(15);\r\n\t\t\tadcValue = analogRead(PORT4_ADC); //adcValue = analogRead(PORT1_ADC); -> adcValue = analogRead(PORT4_ADC); 140324\r\n\t\t\tdigitalWrite(PORT4_SIG2, LOW);//digitalWrite(PORT1_SIG2, LOW); -> digitalWrite(PORT4_SIG2, LOW);\r\n\t\t\treturn adcValue;\r\n\t\t}else if(device_index == MAGNETIC_SENSOR || device_index == TOUCH_SENSOR || device_index == PIR_SENSOR ){\r\n\t\t\treturn digitalRead(PORT4_ADC);\r\n\t\t}else if(device_index == ULTRASONIC_SENSOR){\r\n\t\t\tdistance_value = (int)analogRead(PORT4_ADC); //analogRead(PORT1_ADC); -> analogRead(PORT4_ADC); 140324\r\n\t\t\tdis_value = (((distance_value * 0.24)/4) - 3);\r\n\t\t\taverage_cnt++;\r\n\t\t\taverage_value+=dis_value;\r\n\t\t\tif(average_cnt >= 100){\r\n\t\t\t\taverage_value/=100;\r\n\t\t\t\taverage_cnt = 0;\r\n\t\t\t}\r\n\t\t\t  return average_value;\r\n\t\t}else if(device_index == TEMPERATURE_SENSOR){\r\n\t\t\tanalogValue = analogRead(PORT4_ADC);// 2014-04-17 shin\r\n\t\t\tvvalue = (1023 - analogValue) * 10000 /analogValue;\r\n\t\t\tfor(scount = -20; scount < 140; scount++){\r\n\t\t\t\tif(vvalue > gwTheRmistor[scount +20]){\r\n\t\t\t\t      return scount;\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t}else if(device_index == COLOR_SENSOR){\r\n\t\t\treturn OLLO::detectColor(4);\r\n\t\t}else{\r\n\t\t\treturn (int)analogRead(PORT4_ADC);\r\n\t\t}\r\n\t\tbreak;\r\n\tdefault:\r\n\t\treturn 0;\r\n\t}\r\n\treturn 0;\r\n}\r\n\r\nint OLLO::read(int devNum, OlloDeviceIndex device_index, ColorIndex sub_index){ //COLOR SENSOR\r\n\t//int adcValue = 0;\r\n\tif( devNum == 0 ){\r\n\t\treturn 0;\r\n\t}\r\n\tif(device_index == COLOR_SENSOR){\r\n\t\tsetColor(sub_index);\r\n\t}else{\r\n\t\treturn 0;\r\n\t}\r\n\r\n\tswitch(devNum){\r\n\tcase 1:\r\n\t\t digitalWrite(PORT1_SIG1, mMot_minus);\r\n\t\t digitalWrite(PORT1_SIG2, mMot_plus);\r\n\t\t delay(5); // after 20ms, read analog\r\n\t\t return (((int)analogRead(PORT1_ADC)));\r\n\r\n\tcase 2:\r\n\t\tdigitalWrite(PORT2_SIG1, mMot_minus);\r\n\t\tdigitalWrite(PORT2_SIG2, mMot_plus);\r\n\t\tdelay(5);\r\n\t\treturn ((int)analogRead(PORT2_ADC));\r\n\r\n\tcase 3:\r\n\t\tdigitalWrite(PORT3_SIG1, mMot_minus);\r\n\t\tdigitalWrite(PORT3_SIG2, mMot_plus);\r\n\t\tdelay(5);\r\n\t\treturn ((int)analogRead(PORT3_ADC));\r\n\r\n\tcase 4:\r\n\t\tdigitalWrite(PORT4_SIG1, mMot_minus);\r\n\t\tdigitalWrite(PORT4_SIG2, mMot_plus);\r\n\t\tdelay(5);\r\n\t\treturn ((int)analogRead(PORT4_ADC));\r\n\r\n\tdefault:\r\n\t\treturn 0;\r\n\t}\r\n}\r\nvoid OLLO::writeLED(int devNum, uint8_t leftVal, uint8_t rightVal ){\r\n\tif( leftVal >1 || rightVal >1 || devNum == 0 ){\r\n\t\treturn;\r\n\t}\r\n\r\n\tswitch(devNum){\r\n\t\tcase 1:\r\n\t\t\t digitalWrite(PORT1_SIG1,rightVal);\r\n\t\t\t digitalWrite(PORT1_SIG2,leftVal);\r\n\t\t\tbreak;\r\n\t\tcase 2:\r\n\t\t\tdigitalWrite(PORT2_SIG1,rightVal);\r\n\t\t\tdigitalWrite(PORT2_SIG2,leftVal);\r\n\t\t\tbreak;\r\n\t\tcase 3:\r\n\t\t\tdigitalWrite(PORT3_SIG1,rightVal);\r\n\t\t\tdigitalWrite(PORT3_SIG2,leftVal);\r\n\t\t\tbreak;\r\n\t\tcase 4:\r\n\t\t\tdigitalWrite(PORT4_SIG1,rightVal);\r\n\t\t\tdigitalWrite(PORT4_SIG2,leftVal);\r\n\t\t\tbreak;\r\n\t\tdefault:\r\n\t\t\tbreak;\r\n\t\t}\r\n\r\n}\r\nvoid OLLO::write(int devNum, uint8_t leftVal, uint8_t rightVal ){\r\n\tif( leftVal >1 || rightVal >1 || devNum == 0 ){\r\n\t\treturn;\r\n\t}\r\n\r\n\tswitch(devNum){\r\n\t\tcase 1:\r\n\t\t\t digitalWrite(6,rightVal);\r\n\t\t\t digitalWrite(7,leftVal);\r\n\t\t\tbreak;\r\n\t\tcase 2:\r\n\t\t\tdigitalWrite(8,rightVal);\r\n\t\t\tdigitalWrite(9,leftVal);\r\n\t\t\tbreak;\r\n\t\tcase 3:\r\n\t\t\tdigitalWrite(10,rightVal);\r\n\t\t\tdigitalWrite(11,leftVal);\r\n\t\t\tbreak;\r\n\t\tcase 4:\r\n\t\t\tdigitalWrite(12,rightVal);\r\n\t\t\tdigitalWrite(13,leftVal);\r\n\t\t\tbreak;\r\n\t\tdefault:\r\n\t\t\tbreak;\r\n\t\t}\r\n\r\n}\r\nvoid OLLO::write(int devNum, uint8_t leftVal, uint8_t centerVal, uint8_t rightVal){\r\n\r\n\tif( leftVal >1 || rightVal >1 || centerVal > 1 || devNum == 0){\r\n\t\treturn;\r\n\t}\r\n\r\n\tswitch(devNum){\r\n\t\tcase 1:\r\n\t\t\t digitalWrite(6,rightVal);\r\n\t\t\t digitalWrite(2,centerVal);\r\n\t\t\t digitalWrite(7,leftVal);\r\n\t\t\tbreak;\r\n\t\tcase 2:\r\n\t\t\tdigitalWrite(8,rightVal);\r\n\t\t\tdigitalWrite(3,centerVal);\r\n\t\t\tdigitalWrite(9,leftVal);\r\n\t\t\tbreak;\r\n\t\tcase 3:\r\n\t\t\tdigitalWrite(10,rightVal);\r\n\t\t\tdigitalWrite(0,centerVal);\r\n\t\t\tdigitalWrite(11,leftVal);\r\n\t\t\tbreak;\r\n\t\tcase 4:\r\n\t\t\tdigitalWrite(12,rightVal);\r\n\t\t\tdigitalWrite(1,centerVal);\r\n\t\t\tdigitalWrite(13,leftVal);\r\n\t\t\tbreak;\r\n\t\tdefault:\r\n\t\t\tbreak;\r\n\t}\r\n\r\n}\r\n\r\nvoid OLLO::setColor(ColorIndex colorIndex) {\r\n\tswitch(colorIndex){\r\n\t\tcase RED: //Red\r\n\t\t\tmMot_minus = HIGH;\r\n\t\t\tmMot_plus = HIGH;\r\n\t\t\tbreak;\r\n\t\tcase GREEN://Green\r\n\t\t\tmMot_minus = LOW;\r\n\t\t\tmMot_plus = HIGH;\r\n\t\t\tbreak;\r\n\t\tcase BLUE://Blue\r\n\t\t\tmMot_minus = HIGH;\r\n\t\t\tmMot_plus = LOW;\r\n\t\t\tbreak;\r\n\t\tdefault:\r\n\t\t\tbreak;\r\n\t}\r\n}\r\n\r\nint OLLO::detectColor(uint8_t port) {\r\n\tint lColor[3]= {0,0,0};\r\n\tint lRed,lGreen,lBlue;\r\n\tbColorResult=0;\r\n\r\n\tfloat\tfRawY, fRawCb, fRawCr, fR, fG, fB, fGR, fGB, fRB;\r\n\tuint8_t\t\tuY, uCb, uCr;\r\n\r\n\tlRed = this->read(port, COLOR_SENSOR, RED);\r\n\tlGreen = (this->read(port, COLOR_SENSOR, GREEN));\r\n\tlBlue = this->read(port, COLOR_SENSOR, BLUE);\r\n \r\n\tfGR = (float)lGreen / (float)lRed;\r\n\tfGB = (float)lGreen / (float)lBlue;\r\n\tfRB = (float)lRed / (float)lBlue;\r\n\tfR = (float)lRed * 255 / 1023;\r\n\tfG = (float)lGreen * 255 / 1023;\r\n\tfB = (float)lBlue * 255 / 1023;\r\n\r\n\tfRawY  = (299 * fR + 587 * fG + 114 * fB) / 1000;\r\n\tfRawCb = 0.5643 * (fB - fRawY) + 128;\r\n\tfRawCr = 0.7132 * (fR - fRawY) + 128;\r\n\r\n\tuY  = constrain((int)fRawY , 0 , 255);\r\n\tuCb = constrain((int)fRawCb, 0 , 255);\r\n\tuCr = constrain((int)fRawCr, 0 , 255);\r\n\t\r\n\t// Color detecting algorithm changed from RGB to YCbCr, 2018-10-18 Will\r\n\tif (uCb >= 105 && uCb <= 125 && uCr >= 130 && uCr < 200 && uY <= 100)\r\n\t{\r\n\t\tif ((fGR < 0.60) && ((fRB > 2.5) || (fRB <= 2.5 && fGB < 1.15))) {\r\n\t\t\tbColorResult = 3;  // red\r\n\t\t} else if ((uCb / uY) < 1.50) {\r\n\t\t\tbColorResult = 6;  // yellow\r\n\t\t} else {\r\n\t\t\tbColorResult = 0;  // unknown\r\n\t\t}\r\n\t} else if (uCb >= 110 && uCb <= 135 && uCr >= 105 && uCr < 140 && uY > 40 && uY < 100) {\r\n\t\tif (fGR > 0.90) {\r\n\t\t\tif (fGB > 0.80) {\r\n\t\t\t\tbColorResult = 4;\t // green\r\n\t\t\t} else {\r\n\t\t\t\tbColorResult = 0;\r\n\t\t\t}\r\n\t\t} else {\r\n\t\t\tbColorResult = 6;\t // yellow\r\n\t\t}\r\n\t} else if (uCb >= 130 && uCb <= 160 && uCr >= 110 && uCr < 130 && uY > 20 && uY < 80) {\r\n\t\tif (fGR > 1.00 && fGB < 0.80) {\r\n\t\t\tbColorResult = 5;\t // blue\r\n\t\t}\telse if (fRB > 0.90) {\r\n\t\t\tbColorResult = 2;  // black\r\n\t\t} else {\r\n\t\t\tbColorResult = 0;\r\n\t\t}\r\n\t}\telse if (uCb >= 70 && uCb <= 115 && uCr >= 130 && uCr < 185 && uY > 80) {\r\n\t\tif ((float)(uCb / uY) < 1.50) {\r\n\t\t\tbColorResult = 6;\t // yellow\r\n\t\t} else if ((float)(uCb / uY) > 2.00) {\r\n\t\t\tbColorResult = 2;  // black\r\n\t\t} else {\r\n\t\t\tbColorResult = 0;  // unknown\r\n\t\t}\r\n\t}\telse if (uCb >= 110 && uCb <= 130 && uCr >= 110 && uCr < 140 && uY < 100) {\r\n\t\tif (fGR < 1.10 || (fGR >=1.10 && lRed < 90 && lGreen < 100 && lBlue < 90)) {\r\n\t\t\tbColorResult = 2;\t // black\r\n\t\t} else if (lGreen >= 100) {\r\n\t\t\tbColorResult = 4;  // Green\r\n\t\t} else {\r\n\t\t\tbColorResult = 0;  // unknown\r\n\t\t}\r\n\t} else if (uCb >= 105 && uCb <= 150 && uCr >= 110 && uCr < 165 && uY > 100) {\r\n\t\tif (fRB < 1.30) {\r\n\t\t\tbColorResult = 1;\t // white\r\n\t\t}\telse if (fRB > 1.30) {\r\n\t\t\tbColorResult = 6;  // yellow\r\n\t\t} else {\r\n\t\t\tbColorResult = 0;  // unknown\r\n\t\t}\r\n\t} else {\r\n\t\tbColorResult = 0;  // unknown\r\n\t}\r\n\r\n\tif (bColorResult == before_color_num) {\r\n\t\tbefore_color_cnt++;\r\n\t\tif (before_color_cnt >= 10) {\r\n\t\t\treturn bColorResult;\r\n\t\t}\r\n\t}\telse {\r\n\t\tbefore_color_cnt = 0;\r\n\t}\r\n\r\n\tbefore_color_num = bColorResult;\r\n\treturn 0;\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OLLO/OLLO.h",
    "content": "/*\r\n * OLLO.h For OpenCR\r\n *\r\n *  Created on: 2013. 5. 30.\r\n *      Author: ROBOTIS CO,.LTD.\r\n */\r\n\r\n#ifndef OLLO_H_\r\n#define OLLO_H_\r\n#include <Arduino.h>\r\n\r\n\r\n\r\n\r\n\r\ntypedef enum OLLO_DEVICE_INDEX {\r\n    IR_SENSOR,\r\n    TOUCH_SENSOR,\r\n    GYRO_SENOSR,\r\n    DMS_SENSOR,\r\n    PIR_SENSOR,\r\n    MAGNETIC_SENSOR,\r\n    COLOR_SENSOR,\r\n    ULTRASONIC_SENSOR,\r\n    LED_DISPLAY,\r\n    TEMPERATURE_SENSOR\r\n}OlloDeviceIndex;\r\n\r\ntypedef enum COLOR_INDEX {\r\n    RED =1 ,\r\n    GREEN,\r\n    BLUE,\r\n    YELLOW,\r\n    ORANGE,\r\n    BLACK,\r\n    WHITE\r\n}ColorIndex;\r\n\r\n\r\n#define COLOR_RED   1\r\n#define COLOR_GREEN 2\r\n#define COLOR_BLUE  3\r\n\r\n\r\n#define PORT1_SIG1  40\r\n#define PORT1_SIG2  41\r\n#define PORT1_ADC   42\r\n\r\n#define PORT2_SIG1  43\r\n#define PORT2_SIG2  44\r\n#define PORT2_ADC   45\r\n\r\n#define PORT3_SIG1  70\r\n#define PORT3_SIG2  71\r\n#define PORT3_ADC   72\r\n\r\n#define PORT4_SIG1  73\r\n#define PORT4_SIG2  74\r\n#define PORT4_ADC   75\r\n\r\n#define OLLO_SLEEP  46\r\n\r\n\r\nclass OLLO {\r\nprivate:\r\n\tuint8_t mportNumber;\r\n\tuint8_t mMot_plus;\r\n\tuint8_t mMot_minus;\r\n\tint detectColor(uint8_t port);\r\n\t\t//int color_chk();\r\n\tvoid setColor(ColorIndex colorIndex);\r\n\tint read(int devNum, OlloDeviceIndex device_index, ColorIndex sub_index);\r\npublic:\r\n\tOLLO();\r\n\tvirtual ~OLLO();\r\n\t//General 3PIN sensors\r\n\tvoid begin(int devNum);\r\n\tvoid begin(int devNum, OlloDeviceIndex device_index);\r\n\tvoid begin(int devNum, OlloDeviceIndex device_index, voidFuncPtr handler);\r\n\r\n\tint read(int devNum);\r\n\tint read(int devNum, OlloDeviceIndex device_index);\r\n\r\n//\tuint8_t isGreen(uint8_t port);\r\n//\tuint8_t isWhite(uint8_t port);\r\n//\tuint8_t isBlue(uint8_t port);\r\n//\tuint8_t isBlack(uint8_t port);\r\n//\tuint8_t isRed(uint8_t port);\r\n//\tuint8_t isYellow(uint8_t port);\r\n//\tuint8_t detectColor(uint8_t port);\r\n\r\n\tvoid write(int devNum, uint8_t leftVal,  uint8_t rightVal);\r\n\tvoid write(int devNum, uint8_t leftVal, uint8_t centerVal, uint8_t rightVal);\r\n\r\n\t//IR Sensor Module\r\n\t//void beginIR(int devNum);\r\n\t//LED Module\r\n\tvoid writeLED(int devNum,uint8_t leftVal, uint8_t rightVal );\r\n\t//Button Module\r\n\t//void beginButton(int devNum,voidFuncPtr handler);\r\n\t//int readColor(int devNum, int colorIndex);\r\n\r\n\r\n};\r\n\r\n#endif /* OLLO_H_ */\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OLLO/keywords.txt",
    "content": "#######################################\n# Datatypes (KEYWORD1)\n#######################################\n\n#######################################\n# Methods and Functions (KEYWORD2)\n#######################################\nread\tKEYWORD2\nwrite\tKEYWORD2\nwriteLED\tKEYWORD2\nbeginIR\tKEYWORD2\nbeginButton\tKEYWORD2\nreadColor\tKEYWORD2\n#######################################\n# Class (KEYWORD3)\n#######################################\nOLLO\tKEYWORD3\nmyOLLO\tKEYWORD3\n#######################################\n# Constants (LITERAL1)\n#######################################\nTOUCH_SENSOR\tLITERAL1\nGYRO_SENOSR\tLITERAL1\nDMS_SENSOR\tLITERAL1\nIR_SENSOR\tLITERAL1\nPIR_SENSOR\t\tLITERAL1\nMAGNETIC_SENSOR\tLITERAL1\nCOLOR_SENSOR\tLITERAL1\nULTRASONIC_SENSOR\t\tLITERAL1\nLED_DISPLAY\tLITERAL1\nRED\tLITERAL1\nGREEN\tLITERAL1\nBLUE\tLITERAL1\nYELLOW\tLITERAL1\nORANGE\tLITERAL1\nBLACK\tLITERAL1\nWHITE\tLITERAL1\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OP3/OP3.cpp",
    "content": ""
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OP3/OP3.h",
    "content": ""
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OP3/examples/opencr_op3/dxl.cpp",
    "content": "/*\n * dxl.c\n *\n *  Created on: 2017. 4. 11.\n *      Author: Baram\n */\n#include <stdlib.h>\n\n#include \"dxl_def.h\"\n#include \"dxl.h\"\n#include \"dxl_hw.h\"\n\n\n#define PACKET_STATE_IDLE           0\n#define PACKET_STATE_RESERVED       1\n#define PACKET_STATE_ID             2\n#define PACKET_STATE_LENGTH_L       3\n#define PACKET_STATE_LENGTH_H       4\n#define PACKET_STATE_DATA           5\n#define PACKET_STATE_CRC_L          6\n#define PACKET_STATE_CRC_H          7\n\n\n\n\n\n//-- Internal Variables\n//\n\n\n//-- External Variables\n//\n\n//-- Internal Functions\n//\nstatic dxl_error_t dxlRxPacketVer2_0(dxl_t *p_packet, uint8_t data_in);\nstatic void dxlUpdateCrc(uint16_t *p_crc_cur, uint8_t data_in);\nstatic uint16_t dxlAddStuffing(uint8_t *p_data, uint16_t length);\nstatic uint16_t dxlRemoveStuffing(uint8_t *p_data, uint16_t length);\n\n\n//-- External Functions\n//\n\n\n\n\n\nbool dxlInit(dxl_t *p_packet, uint8_t protocol_ver)\n{\n  p_packet->header_cnt = 0;\n  p_packet->packet_ver = protocol_ver;\n  p_packet->dxlport_ch = -1;\n  p_packet->rx_state   = PACKET_STATE_IDLE;\n\n  p_packet->id         = 200;\n\n  p_packet->rx.header[0] = 0;\n  p_packet->rx.header[1] = 0;\n  p_packet->rx.header[2] = 0;\n\n  p_packet->inst_func.ping          = NULL;\n  p_packet->inst_func.read          = NULL;\n  p_packet->inst_func.write         = NULL;\n  p_packet->inst_func.reg_write     = NULL;\n  p_packet->inst_func.action        = NULL;\n  p_packet->inst_func.factory_reset = NULL;\n  p_packet->inst_func.reboot        = NULL;\n  p_packet->inst_func.status        = NULL;\n  p_packet->inst_func.sync_read     = NULL;\n  p_packet->inst_func.sync_write    = NULL;\n  p_packet->inst_func.bulk_read     = NULL;\n  p_packet->inst_func.bulk_write    = NULL;\n\n\n  return true;\n}\n\nbool dxlSetId(dxl_t *p_packet, uint8_t id)\n{\n  p_packet->id = id;\n\n  return true;\n}\n\nuint8_t dxlGetId(dxl_t *p_packet)\n{\n  return p_packet->id;\n}\n\nvoid dxlAddInstFunc(dxl_t *p_packet, uint8_t inst, dxl_error_t (*func)(dxl_t *p_dxl))\n{\n\n\n  switch(inst)\n  {\n    case INST_PING:\n      p_packet->inst_func.ping = (dxl_error_t (*)(void *))func;\n      break;\n\n    case INST_READ:\n      p_packet->inst_func.read = (dxl_error_t (*)(void *))func;\n      break;\n\n    case INST_WRITE:\n      p_packet->inst_func.write = (dxl_error_t (*)(void *))func;\n      break;\n\n    case INST_REG_WRITE:\n      p_packet->inst_func.reg_write = (dxl_error_t (*)(void *))func;\n      break;\n\n    case INST_ACTION:\n      p_packet->inst_func.action = (dxl_error_t (*)(void *))func;\n      break;\n\n    case INST_RESET:\n      p_packet->inst_func.factory_reset = (dxl_error_t (*)(void *))func;\n      break;\n\n    case INST_REBOOT:\n      p_packet->inst_func.reboot = (dxl_error_t (*)(void *))func;\n      break;\n\n    case INST_STATUS:\n      p_packet->inst_func.status = (dxl_error_t (*)(void *))func;\n      break;\n\n    case INST_SYNC_READ:\n      p_packet->inst_func.sync_read = (dxl_error_t (*)(void *))func;\n      break;\n\n    case INST_SYNC_WRITE:\n      p_packet->inst_func.sync_write = (dxl_error_t (*)(void *))func;\n      break;\n\n    case INST_BULK_READ:\n      p_packet->inst_func.bulk_read = (dxl_error_t (*)(void *))func;\n      break;\n\n    case INST_BULK_WRITE:\n      p_packet->inst_func.bulk_write = (dxl_error_t (*)(void *))func;\n      break;\n  }\n}\n\ndxl_error_t dxlProcessInst(dxl_t *p_packet)\n{\n  dxl_error_t ret = DXL_RET_OK;\n  uint8_t inst;\n  dxl_error_t (*func)(dxl_t *p_dxl);\n\n\n  inst = p_packet->rx.cmd;\n  func = NULL;\n\n  switch(inst)\n  {\n    case INST_PING:\n      func = (dxl_error_t (*)(dxl_t *))p_packet->inst_func.ping;\n      break;\n\n    case INST_READ:\n      func = (dxl_error_t (*)(dxl_t *))p_packet->inst_func.read;\n      break;\n\n    case INST_WRITE:\n      func = (dxl_error_t (*)(dxl_t *))p_packet->inst_func.write;\n      break;\n\n    case INST_REG_WRITE:\n      func = (dxl_error_t (*)(dxl_t *))p_packet->inst_func.reg_write;\n      break;\n\n    case INST_ACTION:\n      func = (dxl_error_t (*)(dxl_t *))p_packet->inst_func.action;\n      break;\n\n    case INST_RESET:\n      func = (dxl_error_t (*)(dxl_t *))p_packet->inst_func.factory_reset;\n      break;\n\n    case INST_REBOOT:\n      func = (dxl_error_t (*)(dxl_t *))p_packet->inst_func.reboot;\n      break;\n\n    case INST_STATUS:\n      func = (dxl_error_t (*)(dxl_t *))p_packet->inst_func.status;\n      break;\n\n    case INST_SYNC_READ:\n      func = (dxl_error_t (*)(dxl_t *))p_packet->inst_func.sync_read;\n      break;\n\n    case INST_SYNC_WRITE:\n      func = (dxl_error_t (*)(dxl_t *))p_packet->inst_func.sync_write;\n      break;\n\n    case INST_BULK_READ:\n      func = (dxl_error_t (*)(dxl_t *))p_packet->inst_func.bulk_read;\n      break;\n\n    case INST_BULK_WRITE:\n      func = (dxl_error_t (*)(dxl_t *))p_packet->inst_func.bulk_write;\n      break;\n  }\n\n\n  if (func != NULL)\n  {\n    if (p_packet->rx.id != dxlGetId(p_packet) &&  p_packet->rx.id != DXL_GLOBAL_ID)\n    {\n      ret = DXL_RET_ERROR_NO_ID;\n    }\n    else\n    {\n      ret = func(p_packet);\n    }\n  }\n\n  return ret;\n}\n\n\nbool dxlOpenPort(dxl_t *p_packet, uint8_t ch, uint32_t baud)\n{\n  bool ret = true;\n\n\n  p_packet->dxlport_ch   = ch;\n  p_packet->dxlport_baud = baud;\n\n  dxl_hw_begin(baud);\n\n  return ret;\n}\n\nuint32_t dxlRxAvailable(dxl_t *p_packet)\n{\n  (void)(p_packet);\n\n  return dxl_hw_available();\n}\n\nuint8_t dxlRxRead(dxl_t *p_packet)\n{\n  (void)(p_packet);\n\n  return dxl_hw_read();\n}\n\ndxl_error_t dxlRxPacket(dxl_t *p_packet)\n{\n  uint8_t data;\n  dxl_error_t ret = DXL_RET_EMPTY;\n\n\n\n  if (p_packet->packet_ver == DXL_PACKET_VER_1_0)\n  {\n    //ret = dxlRxPacketVer1_0(p_packet, data);\n  }\n  else\n  {\n    while(dxlRxAvailable(p_packet))\n    {\n      data = dxlRxRead(p_packet);\n      ret  = dxlRxPacketVer2_0(p_packet, data);\n\n      //Serial.print(\"rx data : \");\n      //Serial.println(data);\n      if (ret != DXL_RET_EMPTY)\n      {\n        break;\n      }\n    }\n  }\n\n  return ret;\n}\n\ndxl_error_t dxlRxPacketDataIn(dxl_t *p_packet, uint8_t data_in)\n{\n  dxl_error_t ret = DXL_RET_EMPTY;\n\n\n\n  if (p_packet->packet_ver == DXL_PACKET_VER_1_0)\n  {\n    //ret = dxlRxPacketVer1_0(p_packet, data);\n  }\n  else\n  {\n    ret  = dxlRxPacketVer2_0(p_packet, data_in);\n  }\n\n  return ret;\n}\n\ndxl_error_t dxlRxPacketVer2_0(dxl_t *p_packet, uint8_t data_in)\n{\n  dxl_error_t ret = DXL_RET_EMPTY;\n  uint16_t stuff_length;\n\n\n\n  //-- time out(100ms)\n  //\n  if( (micros() - p_packet->prev_time) > 100000 )\n  {\n    p_packet->rx_state   = PACKET_STATE_IDLE;\n    p_packet->prev_time  = micros();\n    p_packet->header_cnt = 0;\n  }\n\n  switch(p_packet->rx_state)\n  {\n    case PACKET_STATE_IDLE:\n      p_packet->prev_time = micros();\n\n      if( p_packet->header_cnt >= 2 )\n      {\n        p_packet->rx.header[2] = data_in;\n\n        if(    p_packet->rx.header[0] == 0xFF\n            && p_packet->rx.header[1] == 0xFF\n            && p_packet->rx.header[2] == 0xFD )\n        {\n          p_packet->header_cnt = 0;\n          p_packet->rx.crc     = 0;\n          dxlUpdateCrc(&p_packet->rx.crc, 0xFF);\n          dxlUpdateCrc(&p_packet->rx.crc, 0xFF);\n          dxlUpdateCrc(&p_packet->rx.crc, 0xFD);\n          p_packet->rx_state = PACKET_STATE_RESERVED;\n        }\n        else\n        {\n          p_packet->rx.header[0] = p_packet->rx.header[1];\n          p_packet->rx.header[1] = p_packet->rx.header[2];\n          p_packet->rx.header[2] = 0;\n        }\n      }\n      else\n      {\n        p_packet->rx.header[p_packet->header_cnt] = data_in;\n        p_packet->header_cnt++;\n      }\n      break;\n\n    case PACKET_STATE_RESERVED:\n      if( data_in == 0xFD )\n      {\n        p_packet->rx_state  = PACKET_STATE_IDLE;\n      }\n      else\n      {\n        p_packet->rx.reserved = data_in;\n        p_packet->rx_state    = PACKET_STATE_ID;\n      }\n      dxlUpdateCrc(&p_packet->rx.crc, data_in);\n      break;\n\n    case PACKET_STATE_ID:\n      p_packet->rx.id       = data_in;\n      p_packet->rx_state    = PACKET_STATE_LENGTH_L;\n      dxlUpdateCrc(&p_packet->rx.crc, data_in);\n      break;\n\n    case PACKET_STATE_LENGTH_L:\n      p_packet->rx.packet_length = data_in;\n      p_packet->rx_state         = PACKET_STATE_LENGTH_H;\n      dxlUpdateCrc(&p_packet->rx.crc, data_in);\n      break;\n\n    case PACKET_STATE_LENGTH_H:\n      p_packet->rx.packet_length |= data_in<<8;\n      p_packet->rx_state          = PACKET_STATE_DATA;\n      p_packet->rx.index          = 0;\n      dxlUpdateCrc(&p_packet->rx.crc, data_in);\n\n      if (p_packet->rx.packet_length > DXL_MAX_BUFFER)\n      {\n        p_packet->rx_state = PACKET_STATE_IDLE;\n      }\n      if (p_packet->rx.packet_length < 3)\n      {\n        p_packet->rx_state = PACKET_STATE_IDLE;\n      }\n\n      break;\n\n    case PACKET_STATE_DATA:\n      p_packet->rx.data[p_packet->rx.index] = data_in;\n      dxlUpdateCrc(&p_packet->rx.crc, data_in);\n\n      p_packet->rx.index++;\n\n      if (p_packet->rx.index >= p_packet->rx.packet_length-2)\n      {\n        p_packet->rx_state = PACKET_STATE_CRC_L;\n      }\n      break;\n\n    case PACKET_STATE_CRC_L:\n      p_packet->rx.crc_received = data_in;\n      p_packet->rx_state        = PACKET_STATE_CRC_H;\n      break;\n\n    case PACKET_STATE_CRC_H:\n      p_packet->rx.crc_received |= data_in<<8;\n\n\n      stuff_length = dxlRemoveStuffing(p_packet->rx.data, p_packet->rx.packet_length);\n      p_packet->rx.packet_length -= stuff_length;\n\n      if (p_packet->rx.crc_received == p_packet->rx.crc)\n      {\n        p_packet->rx.cmd   = p_packet->rx.data[0];\n        p_packet->rx.error = p_packet->rx.data[1];\n\n        if (p_packet->rx.data[0] == DXL_INST_STATUS)\n        {\n          p_packet->rx.p_param      = &p_packet->rx.data[2];\n          p_packet->rx.param_length = p_packet->rx.packet_length - 4;\n          ret = DXL_RET_RX_STATUS;\n        }\n        else\n        {\n          p_packet->rx.p_param      = &p_packet->rx.data[1];\n          p_packet->rx.param_length = p_packet->rx.packet_length - 3;\n          ret = DXL_RET_RX_INST;\n        }\n      }\n      else\n      {\n        ret = DXL_RET_ERROR_CRC;\n      }\n\n      p_packet->rx_state = PACKET_STATE_IDLE;\n      break;\n\n    default:\n      p_packet->rx_state = PACKET_STATE_IDLE;\n      break;\n  }\n\n  return ret;\n}\n\nuint16_t dxlRemoveStuffing(uint8_t *p_data, uint16_t length)\n{\n  uint16_t i;\n  uint16_t stuff_length;\n\n\n\n  stuff_length = 0;\n  for( i=0; i<length; i++ )\n  {\n    if( i >= 2 )\n    {\n      if( p_data[i-2] == 0xFF && p_data[i-1] == 0xFF  && p_data[i] == 0xFD )\n      {\n        i++;\n        p_data[i] = p_data[i+1];\n        stuff_length++;\n      }\n    }\n  }\n\n  return stuff_length;\n}\n\nuint16_t dxlAddStuffing(uint8_t *p_data, uint16_t length)\n{\n  uint8_t stuff_buf[DXL_MAX_BUFFER];\n  uint16_t i;\n  uint16_t index;\n  uint16_t stuff_length = 0;\n\n\n  index = 0;\n  stuff_length = 0;\n  for( i=0; i<length-2; i++ )\n  {\n    stuff_buf[index++] = p_data[i];\n\n    if( i >= 2 )\n    {\n      if( p_data[i-2] == 0xFF && p_data[i-1] == 0xFF  && p_data[i] == 0xFD )\n      {\n        stuff_buf[index++] = 0xFD;\n        stuff_length++;\n      }\n    }\n  }\n\n  if( stuff_length > 0 )\n  {\n    for( i=0; i<index; i++ )\n    {\n      p_data[i] = stuff_buf[i];\n    }\n  }\n\n  return stuff_length;\n}\n\ndxl_error_t dxlMakePacketStatus(dxl_t *p_packet, uint8_t id, uint8_t error, uint8_t *p_data, uint16_t length )\n{\n  dxl_error_t ret = DXL_RET_OK;\n  uint16_t i = 0;\n  uint16_t packet_length;\n  uint16_t stuff_length;\n  uint16_t crc;\n\n\n  if (length > DXL_MAX_BUFFER-7)\n  {\n    return DXL_RET_ERROR_LENGTH;\n  }\n\n  packet_length = length + 4;\n\n  p_packet->tx.data[PKT_HDR_1_IDX] = 0xFF;\n  p_packet->tx.data[PKT_HDR_2_IDX] = 0xFF;\n  p_packet->tx.data[PKT_HDR_3_IDX] = 0xFD;\n  p_packet->tx.data[PKT_RSV_IDX]   = 0x00;\n  p_packet->tx.data[PKT_ID_IDX]    = id;\n  p_packet->tx.data[PKT_INST_IDX]  = DXL_INST_STATUS;\n  p_packet->tx.data[PKT_ERROR_IDX] = error;\n\n\n  for (i=0; i<length; i++)\n  {\n    p_packet->tx.data[PKT_STATUS_PARAM_IDX + i] = p_data[i];\n  }\n\n  // stuff 추가\n  stuff_length = dxlAddStuffing(&p_packet->tx.data[PKT_INST_IDX], length + 2);\n  packet_length += stuff_length;\n\n  p_packet->tx.data[PKT_LEN_L_IDX] = packet_length >> 0;\n  p_packet->tx.data[PKT_LEN_H_IDX] = packet_length >> 8;\n\n\n  // crc 계산\n  crc = 0;\n  for (i=0; i<packet_length+7-2; i++)\n  {\n    dxlUpdateCrc(&crc, p_packet->tx.data[i]);\n  }\n\n\n  p_packet->tx.data[PKT_INST_IDX + packet_length - 2] = crc >> 0;\n  p_packet->tx.data[PKT_INST_IDX + packet_length - 1] = crc >> 8;\n\n  p_packet->tx.packet_length = packet_length + 7;\n\n  return ret;\n}\n\n\ndxl_error_t dxlTxPacketStatus(dxl_t *p_packet, uint8_t id, uint8_t error, uint8_t *p_data, uint16_t length )\n{\n  dxl_error_t ret = DXL_RET_OK;\n\n\n\n  ret = dxlMakePacketStatus(p_packet, id, error, p_data, length );\n\n  if (ret == DXL_RET_OK)\n  {\n    // 데이터 전송\n    dxl_hw_write(p_packet->tx.data, p_packet->tx.packet_length);\n  }\n\n  return ret;\n}\n\ndxl_error_t dxlTxPacket(dxl_t *p_packet)\n{\n  dxl_error_t ret = DXL_RET_OK;\n\n  dxl_hw_write(p_packet->tx.data, p_packet->tx.packet_length);\n\n/*\n  for(int i=0; i<p_packet->tx.packet_length; i++)\n  {\n\n    Serial.printf(\"%02X \", p_packet->tx.data[i]);\n\n    //Serial.println(p_packet->tx.data[i], HEX);\n  }\n  Serial.println(\" \");\n*/\n\n  return ret;\n}\n\n\nvoid dxlUpdateCrc(uint16_t *p_crc_cur, uint8_t data_in)\n{\n  uint16_t crc;\n  uint16_t i;\n  unsigned short crc_table[256] = {0x0000,\n                                  0x8005, 0x800F, 0x000A, 0x801B, 0x001E, 0x0014, 0x8011,\n                                  0x8033, 0x0036, 0x003C, 0x8039, 0x0028, 0x802D, 0x8027,\n                                  0x0022, 0x8063, 0x0066, 0x006C, 0x8069, 0x0078, 0x807D,\n                                  0x8077, 0x0072, 0x0050, 0x8055, 0x805F, 0x005A, 0x804B,\n                                  0x004E, 0x0044, 0x8041, 0x80C3, 0x00C6, 0x00CC, 0x80C9,\n                                  0x00D8, 0x80DD, 0x80D7, 0x00D2, 0x00F0, 0x80F5, 0x80FF,\n                                  0x00FA, 0x80EB, 0x00EE, 0x00E4, 0x80E1, 0x00A0, 0x80A5,\n                                  0x80AF, 0x00AA, 0x80BB, 0x00BE, 0x00B4, 0x80B1, 0x8093,\n                                  0x0096, 0x009C, 0x8099, 0x0088, 0x808D, 0x8087, 0x0082,\n                                  0x8183, 0x0186, 0x018C, 0x8189, 0x0198, 0x819D, 0x8197,\n                                  0x0192, 0x01B0, 0x81B5, 0x81BF, 0x01BA, 0x81AB, 0x01AE,\n                                  0x01A4, 0x81A1, 0x01E0, 0x81E5, 0x81EF, 0x01EA, 0x81FB,\n                                  0x01FE, 0x01F4, 0x81F1, 0x81D3, 0x01D6, 0x01DC, 0x81D9,\n                                  0x01C8, 0x81CD, 0x81C7, 0x01C2, 0x0140, 0x8145, 0x814F,\n                                  0x014A, 0x815B, 0x015E, 0x0154, 0x8151, 0x8173, 0x0176,\n                                  0x017C, 0x8179, 0x0168, 0x816D, 0x8167, 0x0162, 0x8123,\n                                  0x0126, 0x012C, 0x8129, 0x0138, 0x813D, 0x8137, 0x0132,\n                                  0x0110, 0x8115, 0x811F, 0x011A, 0x810B, 0x010E, 0x0104,\n                                  0x8101, 0x8303, 0x0306, 0x030C, 0x8309, 0x0318, 0x831D,\n                                  0x8317, 0x0312, 0x0330, 0x8335, 0x833F, 0x033A, 0x832B,\n                                  0x032E, 0x0324, 0x8321, 0x0360, 0x8365, 0x836F, 0x036A,\n                                  0x837B, 0x037E, 0x0374, 0x8371, 0x8353, 0x0356, 0x035C,\n                                  0x8359, 0x0348, 0x834D, 0x8347, 0x0342, 0x03C0, 0x83C5,\n                                  0x83CF, 0x03CA, 0x83DB, 0x03DE, 0x03D4, 0x83D1, 0x83F3,\n                                  0x03F6, 0x03FC, 0x83F9, 0x03E8, 0x83ED, 0x83E7, 0x03E2,\n                                  0x83A3, 0x03A6, 0x03AC, 0x83A9, 0x03B8, 0x83BD, 0x83B7,\n                                  0x03B2, 0x0390, 0x8395, 0x839F, 0x039A, 0x838B, 0x038E,\n                                  0x0384, 0x8381, 0x0280, 0x8285, 0x828F, 0x028A, 0x829B,\n                                  0x029E, 0x0294, 0x8291, 0x82B3, 0x02B6, 0x02BC, 0x82B9,\n                                  0x02A8, 0x82AD, 0x82A7, 0x02A2, 0x82E3, 0x02E6, 0x02EC,\n                                  0x82E9, 0x02F8, 0x82FD, 0x82F7, 0x02F2, 0x02D0, 0x82D5,\n                                  0x82DF, 0x02DA, 0x82CB, 0x02CE, 0x02C4, 0x82C1, 0x8243,\n                                  0x0246, 0x024C, 0x8249, 0x0258, 0x825D, 0x8257, 0x0252,\n                                  0x0270, 0x8275, 0x827F, 0x027A, 0x826B, 0x026E, 0x0264,\n                                  0x8261, 0x0220, 0x8225, 0x822F, 0x022A, 0x823B, 0x023E,\n                                  0x0234, 0x8231, 0x8213, 0x0216, 0x021C, 0x8219, 0x0208,\n                                  0x820D, 0x8207, 0x0202 };\n\n  crc = *p_crc_cur;\n\n  i = ((unsigned short)(crc >> 8) ^ data_in) & 0xFF;\n  *p_crc_cur = (crc << 8) ^ crc_table[i];\n}\n\n\n\n\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OP3/examples/opencr_op3/dxl.h",
    "content": "/*\n * dxl.h\n *\n *  Created on: 2017. 4. 11.\n *      Author: Baram\n */\n\n#ifndef DXL_H_\n#define DXL_H_\n\n\n#include \"dxl_def.h\"\n\n\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n\n#define DXL_PACKET_VER_1_0      0\n#define DXL_PACKET_VER_2_0      1\n\n\n#define DXL_STATE_WAIT_INST     0\n#define DXL_STATE_WAIT_STATUS   1\n\n\n#define DXL_TYPE_INST           0\n#define DXL_TYPE_STATUS         1\n\n\n#define DXL_INST_STATUS         0x55\n\n#define DXL_GLOBAL_ID           0xFE\n\n\n#define DXL_MAX_BUFFER          2048\n\n\n\n#define PKT_HDR_1_IDX           0\n#define PKT_HDR_2_IDX           1\n#define PKT_HDR_3_IDX           2\n#define PKT_RSV_IDX             3\n#define PKT_ID_IDX              4\n#define PKT_LEN_L_IDX           5\n#define PKT_LEN_H_IDX           6\n#define PKT_INST_IDX            7\n#define PKT_ERROR_IDX           8\n\n#define PKT_STATUS_PARAM_IDX    9\n\n\n\n#define INST_PING               0x01\n#define INST_READ               0x02\n#define INST_WRITE              0x03\n#define INST_REG_WRITE          0x04\n#define INST_ACTION             0x05\n#define INST_RESET              0x06\n#define INST_REBOOT             0x08\n#define INST_STATUS             0x55\n#define INST_SYNC_READ          0x82\n#define INST_SYNC_WRITE         0x83\n#define INST_BULK_READ          0x92\n#define INST_BULK_WRITE         0x93\n\n#define DXL_ERR_NONE            0x00\n#define DXL_ERR_RESULT_FAIL     0x01\n#define DXL_ERR_INST_ERROR      0x02\n#define DXL_ERR_CRC_ERROR       0x03\n#define DXL_ERR_DATA_RANGE      0x04\n#define DXL_ERR_DATA_LENGTH     0x05\n#define DXL_ERR_DATA_LIMIT      0x06\n#define DXL_ERR_ACCESS          0x07\n\n\n\n#define DXL_PROCESS_INST        0\n#define DXL_PROCESS_BROAD_PING  1\n#define DXL_PROCESS_BROAD_READ  2\n#define DXL_PROCESS_BROAD_WRITE 3\n\n\ntypedef enum\n{\n  DXL_RET_OK,\n  DXL_RET_RX_INST,\n  DXL_RET_RX_STATUS,\n  DXL_RET_EMPTY,\n  DXL_RET_PROCESS_BROAD_PING,\n  DXL_RET_PROCESS_BROAD_READ,\n  DXL_RET_PROCESS_BROAD_WRITE,\n  DXL_RET_ERROR_CRC,\n  DXL_RET_ERROR_LENGTH,\n  DXL_RET_ERROR_NO_ID,\n  DXL_RET_ERROR\n} dxl_error_t;\n\n\n\n\ntypedef struct\n{\n  uint8_t   header[3];\n  uint8_t   reserved;\n  uint8_t   id;\n  uint8_t   cmd;\n  uint8_t   error;\n  uint8_t   type;\n  uint16_t  index;\n  uint16_t  packet_length;\n  uint16_t  param_length;\n  uint16_t  crc;\n  uint16_t  crc_received;\n  uint8_t   *p_param;\n  uint8_t   data[DXL_MAX_BUFFER];\n} dxl_packet_t;\n\n\ntypedef struct\n{\n  dxl_error_t (*ping         )(void *p_arg);\n  dxl_error_t (*read         )(void *p_arg);\n  dxl_error_t (*write        )(void *p_arg);\n  dxl_error_t (*reg_write    )(void *p_arg);\n  dxl_error_t (*action       )(void *p_arg);\n  dxl_error_t (*factory_reset)(void *p_arg);\n  dxl_error_t (*reboot       )(void *p_arg);\n  dxl_error_t (*status       )(void *p_arg);\n  dxl_error_t (*sync_read    )(void *p_arg);\n  dxl_error_t (*sync_write   )(void *p_arg);\n  dxl_error_t (*bulk_read    )(void *p_arg);\n  dxl_error_t (*bulk_write   )(void *p_arg);\n} dxl_inst_func_t;\n\n\ntypedef struct\n{\n  uint8_t  packet_ver;\n   int8_t  dxlport_ch;\n  uint32_t dxlport_baud;\n  uint8_t  rx_state;\n  uint8_t  id;\n  uint8_t  current_id;\n  uint8_t  pre_id;\n\n  uint32_t prev_time;\n  uint8_t  header_cnt;\n\n  dxl_inst_func_t inst_func;\n  dxl_packet_t    rx;\n  dxl_packet_t    tx;\n} dxl_t;\n\n\n\nbool dxlInit(dxl_t *p_packet, uint8_t protocol_ver);\nbool dxlOpenPort(dxl_t *p_packet, uint8_t ch, uint32_t baud);\nvoid dxlAddInstFunc(dxl_t *p_packet, uint8_t inst, dxl_error_t (*func)(dxl_t *p_dxl));\nbool dxlSetId(dxl_t *p_packet, uint8_t id);\nuint8_t dxlGetId(dxl_t *p_packet);\n\nuint32_t dxlRxAvailable(dxl_t *p_packet);\nuint8_t  dxlRxRead(dxl_t *p_packet);\n\n\ndxl_error_t dxlProcessInst(dxl_t *p_packet);\ndxl_error_t dxlRxPacket(dxl_t *p_packet);\ndxl_error_t dxlRxPacketDataIn(dxl_t *p_packet, uint8_t data_in);\n\ndxl_error_t dxlTxPacketInst(dxl_t *p_packet);\ndxl_error_t dxlTxPacketStatus(dxl_t *p_packet, uint8_t id, uint8_t error, uint8_t *p_data, uint16_t length );\ndxl_error_t dxlTxPacket(dxl_t *p_packet);\ndxl_error_t dxlMakePacketStatus(dxl_t *p_packet, uint8_t id, uint8_t error, uint8_t *p_data, uint16_t length );\n\n#ifdef __cplusplus\n}\n#endif\n\n\n\n#endif /* DXL_H_ */\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OP3/examples/opencr_op3/dxl_debug.cpp",
    "content": "/*\n *  dxl_node_op3.cpp\n *\n *  debug node op3\n *\n *  Created on: 2017. 2. 2.\n *      Author: Baram\n */\n\n#include \"dxl_hw.h\"\n#include \"dxl_hw_op3.h\"\n#include \"dxl_node_op3.h\"\n#include \"dxl_debug.h\"\n#include <EEPROM.h>\n\n\n\n#define DEBUG_SERIAL    Serial\n\n\n\n\nextern dxl_mem_op3_t *p_dxl_mem;\n\nstatic uint8_t debug_state = 0;\n\n\n\nstatic void dxl_debug_menu_show_list(void);\nstatic bool dxl_debug_menu_loop(uint8_t ch);\nstatic void dxl_debug_menu_show_cmdline(void);\nstatic bool dxl_debug_menu_shwo_ctrltbl();\n\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_debug_init\n     WORK    :\n---------------------------------------------------------------------------*/\nvoid dxl_debug_init(void)\n{\n  DEBUG_SERIAL.begin(57600);\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_debug_loop\n     WORK    :\n---------------------------------------------------------------------------*/\nvoid dxl_debug_loop(void)\n{\n  static uint32_t tTime[16];\n  uint8_t ch;\n\n\n  if(Serial.available())\n  {\n    ch = Serial.read();\n\n\n    switch(debug_state)\n    {\n      case 0:\n        if(ch == 'm')\n        {\n          debug_state = 1;\n          dxl_debug_menu_show_list();\n          dxl_debug_menu_show_cmdline();\n        }\n        break;\n\n      case 1:\n        dxl_debug_menu_loop(ch);\n        break;\n\n      default:\n        break;\n    }\n  }\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_debug_menu_show_list\n     WORK    :\n---------------------------------------------------------------------------*/\nvoid dxl_debug_menu_show_list(void)\n{\n  DEBUG_SERIAL.println(\"---------------------------\");\n  DEBUG_SERIAL.println(\"m - show menu\");\n  DEBUG_SERIAL.println(\"d - show step\");\n  DEBUG_SERIAL.println(\"l - show control table\");\n  DEBUG_SERIAL.println(\"q - exit menu\");\n  DEBUG_SERIAL.println(\"---------------------------\");\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_debug_menu_show_cmdline\n     WORK    :\n---------------------------------------------------------------------------*/\nvoid dxl_debug_menu_show_cmdline(void)\n{\n  DEBUG_SERIAL.print(\">>\");\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_debug_menu_show_list\n     WORK    :\n---------------------------------------------------------------------------*/\nbool dxl_debug_menu_loop(uint8_t ch)\n{\n  bool exit_menu = false;\n\n\n  switch(ch)\n  {\n    case 'm':\n      dxl_debug_menu_show_list();\n      break;\n\n\n    case 'q':\n      exit_menu = true;\n      DEBUG_SERIAL.println(\" \");\n      DEBUG_SERIAL.println(\"exit menu...\");\n      break;\n\n    case 'd':\n      break;\n\n    case 'l':\n      DEBUG_SERIAL.println(\" \");\n      dxl_debug_menu_shwo_ctrltbl();\n      break;\n\n    default:\n      exit_menu = true;\n      break;\n  }\n\n\n  if(exit_menu == false)\n  {\n    dxl_debug_menu_show_cmdline();\n  }\n\n  return exit_menu;\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_debug_menu_shwo_ctrltbl\n     WORK    :\n---------------------------------------------------------------------------*/\nbool dxl_debug_menu_shwo_ctrltbl()\n{\n  uint32_t addr;\n\n\n  addr = (uint32_t)&p_dxl_mem->Model_Number - (uint32_t)p_dxl_mem;\n  DEBUG_SERIAL.print(addr);\n  DEBUG_SERIAL.print(\"\\t Model_Number    \\t \"); DEBUG_SERIAL.print  (p_dxl_mem->Model_Number);\n  DEBUG_SERIAL.print(\"\\t 0x\");              DEBUG_SERIAL.println(p_dxl_mem->Model_Number,HEX);\n\n  addr = (uint32_t)&p_dxl_mem->Firmware_Version - (uint32_t)p_dxl_mem;\n  DEBUG_SERIAL.print(addr);\n  DEBUG_SERIAL.print(\"\\t Firmware_Version\\t \"); DEBUG_SERIAL.print  (p_dxl_mem->Firmware_Version);\n  DEBUG_SERIAL.print(\"\\t 0x\");                  DEBUG_SERIAL.println(p_dxl_mem->Firmware_Version,HEX);\n\n  addr = (uint32_t)&p_dxl_mem->ID - (uint32_t)p_dxl_mem;\n  DEBUG_SERIAL.print(addr);\n  DEBUG_SERIAL.print(\"\\t ID              \\t \"); DEBUG_SERIAL.print  (p_dxl_mem->ID);\n  DEBUG_SERIAL.print(\"\\t 0x\");                  DEBUG_SERIAL.println(p_dxl_mem->ID,HEX);\n\n  addr = (uint32_t)&p_dxl_mem->Baud - (uint32_t)p_dxl_mem;\n  DEBUG_SERIAL.print(addr);\n  DEBUG_SERIAL.print(\"\\t Baud            \\t \"); DEBUG_SERIAL.print  (p_dxl_mem->Baud);\n  DEBUG_SERIAL.print(\"\\t 0x\");                  DEBUG_SERIAL.println(p_dxl_mem->Baud,HEX);\n\n  addr = (uint32_t)&p_dxl_mem->Return_Delay_Time - (uint32_t)p_dxl_mem;\n  DEBUG_SERIAL.print(addr);\n  DEBUG_SERIAL.print(\"\\t Return_Delay_Time \\t \"); DEBUG_SERIAL.print  (p_dxl_mem->Return_Delay_Time);\n  DEBUG_SERIAL.print(\"\\t 0x\");                  DEBUG_SERIAL.println(p_dxl_mem->Return_Delay_Time,HEX);\n\n  addr = (uint32_t)&p_dxl_mem->Status_Return_Level - (uint32_t)p_dxl_mem;\n  DEBUG_SERIAL.print(addr);\n  DEBUG_SERIAL.print(\"\\t Status_Return_Level \\t \"); DEBUG_SERIAL.print  (p_dxl_mem->Status_Return_Level);\n  DEBUG_SERIAL.print(\"\\t 0x\");                  DEBUG_SERIAL.println(p_dxl_mem->Status_Return_Level,HEX);\n\n  addr = (uint32_t)&p_dxl_mem->Roll_Offset - (uint32_t)p_dxl_mem;\n  DEBUG_SERIAL.print(addr);\n  DEBUG_SERIAL.print(\"\\t Roll_Offset     \\t \"); DEBUG_SERIAL.print  (p_dxl_mem->Roll_Offset);\n  DEBUG_SERIAL.print(\"\\t 0x\");                  DEBUG_SERIAL.println(p_dxl_mem->Roll_Offset,HEX);\n\n  addr = (uint32_t)&p_dxl_mem->Pitch_Offset - (uint32_t)p_dxl_mem;\n  DEBUG_SERIAL.print(addr);\n  DEBUG_SERIAL.print(\"\\t Pitch_Offset    \\t \"); DEBUG_SERIAL.print  (p_dxl_mem->Pitch_Offset);\n  DEBUG_SERIAL.print(\"\\t 0x\");                  DEBUG_SERIAL.println(p_dxl_mem->Pitch_Offset,HEX);\n\n  addr = (uint32_t)&p_dxl_mem->Yaw_Offset - (uint32_t)p_dxl_mem;\n  DEBUG_SERIAL.print(addr);\n  DEBUG_SERIAL.print(\"\\t Yaw_Offset      \\t \"); DEBUG_SERIAL.print  (p_dxl_mem->Yaw_Offset);\n  DEBUG_SERIAL.print(\"\\t 0x\");                  DEBUG_SERIAL.println(p_dxl_mem->Yaw_Offset,HEX);\n\n  addr = (uint32_t)&p_dxl_mem->Dynamixel_Power - (uint32_t)p_dxl_mem;\n  DEBUG_SERIAL.print(addr);\n  DEBUG_SERIAL.print(\"\\t Dynamixel_Power \\t \"); DEBUG_SERIAL.print  (p_dxl_mem->Dynamixel_Power);\n  DEBUG_SERIAL.print(\"\\t 0x\");                  DEBUG_SERIAL.println(p_dxl_mem->Dynamixel_Power,HEX);\n\n  addr = (uint32_t)&p_dxl_mem->LED - (uint32_t)p_dxl_mem;\n  DEBUG_SERIAL.print(addr);\n  DEBUG_SERIAL.print(\"\\t LED             \\t \"); DEBUG_SERIAL.print  (p_dxl_mem->LED);\n  DEBUG_SERIAL.print(\"\\t 0x\");                  DEBUG_SERIAL.println(p_dxl_mem->LED,HEX);\n\n  addr = (uint32_t)&p_dxl_mem->LED_RGB - (uint32_t)p_dxl_mem;\n  DEBUG_SERIAL.print(addr);\n  DEBUG_SERIAL.print(\"\\t LED_RGB         \\t \"); DEBUG_SERIAL.print  (p_dxl_mem->LED_RGB);\n  DEBUG_SERIAL.print(\"\\t 0x\");                  DEBUG_SERIAL.println(p_dxl_mem->LED_RGB,HEX);\n\n  addr = (uint32_t)&p_dxl_mem->Buzzer - (uint32_t)p_dxl_mem;\n  DEBUG_SERIAL.print(addr);\n  DEBUG_SERIAL.print(\"\\t Buzzer          \\t \"); DEBUG_SERIAL.print  (p_dxl_mem->Buzzer);\n  DEBUG_SERIAL.print(\"\\t 0x\");                  DEBUG_SERIAL.println(p_dxl_mem->Buzzer,HEX);\n\n  addr = (uint32_t)&p_dxl_mem->Button - (uint32_t)p_dxl_mem;\n  DEBUG_SERIAL.print(addr);\n  DEBUG_SERIAL.print(\"\\t Button          \\t \"); DEBUG_SERIAL.print  (p_dxl_mem->Button);\n  DEBUG_SERIAL.print(\"\\t 0x\");                  DEBUG_SERIAL.println(p_dxl_mem->Button,HEX);\n\n  addr = (uint32_t)&p_dxl_mem->Voltage - (uint32_t)p_dxl_mem;\n  DEBUG_SERIAL.print(addr);\n  DEBUG_SERIAL.print(\"\\t Voltage         \\t \"); DEBUG_SERIAL.print  (p_dxl_mem->Voltage);\n  DEBUG_SERIAL.print(\"\\t 0x\");                  DEBUG_SERIAL.println(p_dxl_mem->Voltage,HEX);\n\n  addr = (uint32_t)&p_dxl_mem->Gyro_X - (uint32_t)p_dxl_mem;\n  DEBUG_SERIAL.print(addr);\n  DEBUG_SERIAL.print(\"\\t Gyro_X          \\t \"); DEBUG_SERIAL.print  (p_dxl_mem->Gyro_X);\n  DEBUG_SERIAL.print(\"\\t 0x\");                  DEBUG_SERIAL.println(p_dxl_mem->Gyro_X,HEX);\n\n  addr = (uint32_t)&p_dxl_mem->Gyro_Y - (uint32_t)p_dxl_mem;\n  DEBUG_SERIAL.print(addr);\n  DEBUG_SERIAL.print(\"\\t Gyro_Y          \\t \"); DEBUG_SERIAL.print  (p_dxl_mem->Gyro_Y);\n  DEBUG_SERIAL.print(\"\\t 0x\");                  DEBUG_SERIAL.println(p_dxl_mem->Gyro_Y,HEX);\n\n  addr = (uint32_t)&p_dxl_mem->Gyro_Z - (uint32_t)p_dxl_mem;\n  DEBUG_SERIAL.print(addr);\n  DEBUG_SERIAL.print(\"\\t Gyro_Z          \\t \"); DEBUG_SERIAL.print  (p_dxl_mem->Gyro_Z);\n  DEBUG_SERIAL.print(\"\\t 0x\");                  DEBUG_SERIAL.println(p_dxl_mem->Gyro_Z,HEX);\n\n  addr = (uint32_t)&p_dxl_mem->Acc_X - (uint32_t)p_dxl_mem;\n  DEBUG_SERIAL.print(addr);\n  DEBUG_SERIAL.print(\"\\t Acc_X           \\t \"); DEBUG_SERIAL.print  (p_dxl_mem->Acc_X);\n  DEBUG_SERIAL.print(\"\\t 0x\");                  DEBUG_SERIAL.println(p_dxl_mem->Acc_X,HEX);\n\n  addr = (uint32_t)&p_dxl_mem->Acc_Y - (uint32_t)p_dxl_mem;\n  DEBUG_SERIAL.print(addr);\n  DEBUG_SERIAL.print(\"\\t Acc_Y           \\t \"); DEBUG_SERIAL.print  (p_dxl_mem->Acc_Y);\n  DEBUG_SERIAL.print(\"\\t 0x\");                  DEBUG_SERIAL.println(p_dxl_mem->Acc_Y,HEX);\n\n  addr = (uint32_t)&p_dxl_mem->Acc_Z - (uint32_t)p_dxl_mem;\n  DEBUG_SERIAL.print(addr);\n  DEBUG_SERIAL.print(\"\\t Acc_Z           \\t \"); DEBUG_SERIAL.print  (p_dxl_mem->Acc_Z);\n  DEBUG_SERIAL.print(\"\\t 0x\");                  DEBUG_SERIAL.println(p_dxl_mem->Acc_Z,HEX);\n\n  addr = (uint32_t)&p_dxl_mem->Roll - (uint32_t)p_dxl_mem;\n  DEBUG_SERIAL.print(addr);\n  DEBUG_SERIAL.print(\"\\t Roll            \\t \"); DEBUG_SERIAL.print  (p_dxl_mem->Roll);\n  DEBUG_SERIAL.print(\"\\t 0x\");                  DEBUG_SERIAL.println(p_dxl_mem->Roll,HEX);\n\n  addr = (uint32_t)&p_dxl_mem->Pitch - (uint32_t)p_dxl_mem;\n  DEBUG_SERIAL.print(addr);\n  DEBUG_SERIAL.print(\"\\t Pitch           \\t \"); DEBUG_SERIAL.print  (p_dxl_mem->Pitch);\n  DEBUG_SERIAL.print(\"\\t 0x\");                  DEBUG_SERIAL.println(p_dxl_mem->Pitch,HEX);\n\n  addr = (uint32_t)&p_dxl_mem->Yaw - (uint32_t)p_dxl_mem;\n  DEBUG_SERIAL.print(addr);\n  DEBUG_SERIAL.print(\"\\t Yaw             \\t \"); DEBUG_SERIAL.print  (p_dxl_mem->Yaw);\n  DEBUG_SERIAL.print(\"\\t 0x\");                  DEBUG_SERIAL.println(p_dxl_mem->Yaw,HEX);\n\n  addr = (uint32_t)&p_dxl_mem->IMU_Control - (uint32_t)p_dxl_mem;\n  DEBUG_SERIAL.print(addr);\n  DEBUG_SERIAL.print(\"\\t IMU_Control     \\t \"); DEBUG_SERIAL.print  (p_dxl_mem->IMU_Control);\n  DEBUG_SERIAL.print(\"\\t 0x\");                  DEBUG_SERIAL.println(p_dxl_mem->IMU_Control,HEX);\n\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OP3/examples/opencr_op3/dxl_debug.h",
    "content": "/*\n *  dxl_debug.h\n *\n *  debug node op3\n *\n *  Created on: 2017. 2. 2.\n *      Author: Baram\n */\n\n#ifndef DXL_DEBUG_H\n#define DXL_DEBUG_H\n\n\n#include \"dxl.h\"\n#include \"dxl_def.h\"\n\n\n\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n\n\n\n\n\nvoid dxl_debug_init(void);\nvoid dxl_debug_loop(void);\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OP3/examples/opencr_op3/dxl_def.h",
    "content": "/*\n *  dxl_def.h\n *\n *  dynamixel define\n *\n *  Created on: 2016. 10. 21.\n *      Author: Baram\n */\n\n#ifndef DXL_DEF_H\n#define DXL_DEF_H\n\n#include <Arduino.h>\n#include <math.h>\n#include <string.h>\n#include <stdarg.h>\n#include <stdio.h>\n\n\n\n#define DXL_PORT                  Serial3\n\n\n#define DXL_ID_BROADCAST_ID       0xFE\n\n#define DXL_BUF_LENGTH            1024\n\n\n#define DXL_INST_PING             0x01\n#define DXL_INST_READ             0x02\n#define DXL_INST_WRITE            0x03\n#define DXL_INST_REG_WRITE        0x04\n#define DXL_INST_ACTION           0x05\n#define DXL_INST_FACTORY_RESET    0x06\n#define DXL_INST_REBOOT           0x08\n#define DXL_INST_STATUS           0x55\n#define DXL_INST_SYNC_READ        0x82\n#define DXL_INST_SYNC_WRITE       0x83\n#define DXL_INST_BULK_READ        0x92\n#define DXL_INST_BULK_WRITE       0x93\n\n\n#define DXL_ERR_RESULT_FAIL       0x01\n#define DXL_ERR_INST              0x02\n#define DXL_ERR_CRC               0x03\n#define DXL_ERR_DATA_RANGE        0x04\n#define DXL_ERR_DATA_LENGTH       0x05\n#define DXL_ERR_DATA_LIMIT        0x06\n#define DXL_ERR_ACCESS            0x07\n\n\n\n#define _USE_DEBUG_LOG_RX_INST    (0)\n#define _USE_DEBUG_LOG_RX_STATUS  (0)\n#define _USE_DEBUG_LOG_RX_RAW     (0)\n#define _USE_DEBUG_LOG_TX_INST    (0)\n#define _USE_DEBUG_LOG_TX_STATUS  (0)\n#define _USE_DEBUG_LOG_INST_FUNC  (0)\n\n\n\n#define DXL_MEM_ATTR_NONE         0\n#define DXL_MEM_ATTR_EEPROM       (1<<1)\n#define DXL_MEM_ATTR_RAM          (1<<2)\n#define DXL_MEM_ATTR_RO           (1<<3)\n#define DXL_MEM_ATTR_WO           (1<<4)\n#define DXL_MEM_ATTR_RW           (1<<5)\n#define DXL_MEM_ATTR_REG          (1<<6)\n\n\n\ntypedef struct\n{\n  uint8_t data    [DXL_BUF_LENGTH];\n  uint8_t data_reg[DXL_BUF_LENGTH];\n  uint8_t attr    [DXL_BUF_LENGTH];\n} dxl_mem_t;\n\n\ntypedef struct\n{\n  uint8_t addr;\n  uint8_t length;\n  uint8_t attr;\n  uint8_t init_data;\n} dxl_mem_attr_t;\n\n\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OP3/examples/opencr_op3/dxl_hw.cpp",
    "content": "/*\n *  dxl_hw.cpp\n *\n *  dynamixel hardware\n *\n *  Created on: 2016. 10. 21.\n *      Author: Baram\n */\n\n#include \"dxl_hw.h\"\n\n/* For debug */\nuint32_t tx_led_count, rx_led_count;\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_hw_begin\n     WORK    :\n---------------------------------------------------------------------------*/\nuint32_t dxl_hw_begin(uint8_t baud)\n{\n  uint32_t Baudrate = 0;\n\n  pinMode( DXL_LED_RX, OUTPUT);\n  pinMode( DXL_LED_TX, OUTPUT);\n\n  pinMode( BDPIN_DXL_PWR_EN, OUTPUT );\n  dxl_hw_power_disable();\n\n\n  switch(baud)\n  {\n    case 0:\n      Baudrate = 9600;        // 9600 BPS\n      break;\n\n    case 1:\n      Baudrate = 57600;       // 57,600 BPS\n      break;\n\n    case 2:\n      Baudrate = 115200;      // 115,200 BPS\n      break;\n\n    case 3:\n      Baudrate = 1000000;     // 1M BPS\n      break;\n\n    case 4:\n      Baudrate = 2000000;     // 2M BPS\n      break;\n\n    case 5:\n      Baudrate = 3000000;     // 3M BPS\n      break;\n\n    case 6:\n      Baudrate = 4000000;     // 4M BPS\n      break;\n\n    case 7:\n      Baudrate = 4500000;     // 4.5M BPS\n      break;\n\n    default:\n      Baudrate = 1000000;     // 1M BPS\n      break;\n  }\n\n\n  DXL_PORT.begin(Baudrate);\n\n  return Baudrate;\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_hw_tx_enable\n     WORK    :\n---------------------------------------------------------------------------*/\nvoid dxl_hw_tx_enable(void)\n{\n  drv_dxl_tx_enable(TRUE);\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_hw_tx_disable\n     WORK    :\n---------------------------------------------------------------------------*/\nvoid dxl_hw_tx_disable(void)\n{\n  drv_dxl_tx_enable(FALSE);\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_hw_power_enable\n     WORK    :\n---------------------------------------------------------------------------*/\nvoid dxl_hw_power_enable(void)\n{\n  digitalWrite(BDPIN_DXL_PWR_EN, HIGH);\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_hw_power_enable\n     WORK    :\n---------------------------------------------------------------------------*/\nvoid dxl_hw_power_disable(void)\n{\n  digitalWrite(BDPIN_DXL_PWR_EN, LOW);\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_hw_read\n     WORK    :\n---------------------------------------------------------------------------*/\nuint8_t dxl_hw_read(void)\n{\n  rx_led_count = 3;\n\n  return DXL_PORT.read();\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_hw_write\n     WORK    :\n---------------------------------------------------------------------------*/\nvoid dxl_hw_write(uint8_t value)\n{\n\tDXL_PORT.write(value);\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_hw_write\n     WORK    :\n---------------------------------------------------------------------------*/\nvoid dxl_hw_write(uint8_t *p_data, uint32_t length)\n{\n  uint32_t i;\n\n\n  dxl_hw_tx_enable();\n\n  for (i=0; i<length; i++)\n  {\n    DXL_PORT.write(p_data[i]);\n  }\n  DXL_PORT.flush();\n  tx_led_count = 3;\n\n  dxl_hw_tx_disable();\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_hw_available\n     WORK    :\n---------------------------------------------------------------------------*/\nuint32_t dxl_hw_available(void)\n{\n  return DXL_PORT.available();\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OP3/examples/opencr_op3/dxl_hw.h",
    "content": "/*\n *  dxl_hw.h\n *\n *  dynamixel hardware\n *\n *  Created on: 2016. 10. 21.\n *      Author: Baram\n */\n\n#ifndef DXL_HW_H\n#define DXL_HW_H\n\n\n#include \"dxl_def.h\"\n\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n\n#define DXL_LED_RX            BDPIN_LED_USER_1\n#define DXL_LED_TX            BDPIN_LED_USER_2\n\n\nuint32_t dxl_hw_begin(uint8_t baud);\n\nvoid dxl_hw_tx_enable(void);\nvoid dxl_hw_tx_disable(void);\n\nvoid dxl_hw_power_enable(void);\nvoid dxl_hw_power_disable(void);\n\nuint8_t dxl_hw_read(void);\nvoid    dxl_hw_write(uint8_t value);\nvoid    dxl_hw_write(uint8_t *p_data, uint32_t length);\n\nuint32_t dxl_hw_available(void);\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OP3/examples/opencr_op3/dxl_hw_op3.cpp",
    "content": "/*\n *  dxl_hw_op3.cpp\n *\n *  dynamixel hardware op3\n *\n *  Created on: 2016. 10. 21.\n *      Author: Baram\n */\n\n#include \"dxl_hw_op3.h\"\n#include <IMU.h>\n\n\n#define LED_PWM_PIN_MAX     3\n#define LED_PWM_PWM_MAX     31\n\n#define BUTTON_PIN_MAX      4\n\n#define IMU_CALI_MAX_COUNT  512\n\n\nstatic uint8_t led_pwm_pins[LED_PWM_PIN_MAX] = {PIN_LED_R, PIN_LED_G, PIN_LED_B};\nstatic uint8_t led_pwm_value[LED_PWM_PIN_MAX];\n\nstatic float   imu_offset[3];\nstatic int16_t imu_cali_count[3];\nstatic float   imu_cali_sum[3];\n\nstatic uint8_t  button_value[BUTTON_PIN_MAX];\nstatic uint32_t button_pin_num[BUTTON_PIN_MAX] = {\n  PIN_BUTTON_S1,\n  PIN_BUTTON_S2,\n  PIN_BUTTON_S3,\n  PIN_BUTTON_S4 };\n\n\n\n#define BATTERY_POWER_OFF             0\n#define BATTERY_POWER_STARTUP         1\n#define BATTERY_POWER_NORMAL          2\n#define BATTERY_POWER_CHECK           3\n#define BATTERY_POWER_WARNNING        4\n\n\nstatic uint8_t battery_voltage = 0;\nstatic float   battery_valtage_raw = 0;\nstatic uint8_t battery_state   = BATTERY_POWER_STARTUP;\n\n\n\ncIMU          IMU;\nHardwareTimer Timer(TIMER_CH1);\n\n\n\n\nint16_t dxl_hw_op3_acc_conv(int16_t value);\nint16_t dxl_hw_op3_gyro_conv(int16_t value);\nvoid    dxl_hw_op3_button_update();\nvoid    dxl_hw_op3_voltage_update();\n\nvoid handler_led(void)\n{\n  uint32_t i;\n  static uint8_t led_counter = 0;\n\n\n  for( i=0; i<LED_PWM_PIN_MAX; i++ )\n  {\n    if( led_counter < led_pwm_value[i] && led_pwm_value[i] > 0 )\n    {\n      dxl_hw_op3_led_set(led_pwm_pins[i], 0); // LED ON\n    }\n    else\n    {\n      dxl_hw_op3_led_set(led_pwm_pins[i], 1); // LED OFF\n    }\n  }\n\n  led_counter++;\n  if( led_counter > LED_PWM_PWM_MAX ) led_counter = 0;\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_hw_op3_init\n     WORK    :\n---------------------------------------------------------------------------*/\nvoid dxl_hw_op3_init(void)\n{\n  uint16_t i;\n\n\n  IMU.begin();\n\n\n  for(i=0; i<3; i++)\n  {\n    imu_offset[i]     = 0.0;\n    imu_cali_count[i] = 0;\n  }\n\n  for(i=0; i<BUTTON_PIN_MAX; i++)\n  {\n    button_value[i] = 0;\n  }\n\n  pinMode(PIN_LED_R, OUTPUT);\n  pinMode(PIN_LED_G, OUTPUT);\n  pinMode(PIN_LED_B, OUTPUT);\n\n  pinMode(PIN_LED_1, OUTPUT);\n  pinMode(PIN_LED_2, OUTPUT);\n  pinMode(PIN_LED_3, OUTPUT);\n\n  pinMode(PIN_BUTTON_S1, INPUT_PULLUP);\n  pinMode(PIN_BUTTON_S2, INPUT_PULLUP);\n  pinMode(PIN_BUTTON_S3, INPUT_PULLUP);\n  pinMode(PIN_BUTTON_S4, INPUT_PULLUP);\n\n\n  dxl_hw_op3_led_set(PIN_LED_1, 1); // R\n  dxl_hw_op3_led_set(PIN_LED_2, 1); // G\n  dxl_hw_op3_led_set(PIN_LED_3, 1); // B\n\n\n  dxl_hw_op3_led_pwm(PIN_LED_R, 0);\n  dxl_hw_op3_led_pwm(PIN_LED_G, 0);\n  dxl_hw_op3_led_pwm(PIN_LED_B, 0);\n\n  Timer.pause();\n  Timer.setPeriod(500);              // 500us\n  Timer.attachInterrupt(handler_led);\n  Timer.refresh();\n  Timer.resume();\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_hw_op3_update\n     WORK    :\n---------------------------------------------------------------------------*/\nvoid dxl_hw_op3_update(void)\n{\n  uint8_t i;\n\n\n  if(IMU.update())\n  {\n    for(i=0; i<3; i++)\n    {\n      if(imu_cali_count[i] > 0)\n      {\n        imu_cali_sum[i] += IMU.rpy[i];\n        imu_cali_count[i]--;\n\n        if(imu_cali_count[i] == 0)\n        {\n          imu_offset[i] = imu_cali_sum[i]/IMU_CALI_MAX_COUNT;\n          imu_cali_count[i] = -1;\n        }\n      }\n    }\n  }\n\n  dxl_hw_op3_button_update();\n  dxl_hw_op3_voltage_update();\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_hw_op3_acc_conv\n     WORK    :\n---------------------------------------------------------------------------*/\nint16_t dxl_hw_op3_acc_conv(int16_t value)\n{\n  int16_t  data;\n\n  #if 0\n  data = constrain(value, -2048, 2048); // 8g->4g\n  data = data/4 + 512;\n  data = constrain(data, 0, 1023);\n  #else\n  data = value;\n  #endif\n\n  return (int16_t)data;\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_hw_op3_button_update\n     WORK    :\n---------------------------------------------------------------------------*/\nvoid dxl_hw_op3_button_update()\n{\n  static uint8_t pin_state[BUTTON_PIN_MAX] = {0,};\n  uint8_t pin_in = 0;\n  uint32_t i;\n  static uint32_t pin_time[BUTTON_PIN_MAX] = {0,};\n\n\n  for(i=0; i<BUTTON_PIN_MAX; i++)\n  {\n    pin_in = !digitalRead(button_pin_num[i]);\n\n    switch(pin_state[i])\n    {\n      case 0:\n        if(button_value[i] != pin_in)\n        {\n          pin_state[i] = 1;\n          pin_time[i] = millis();\n        }\n        break;\n\n      case 1:\n        if((millis()-pin_time[i]) > 30)\n        {\n          if(button_value[i] != pin_in)\n          {\n            button_value[i] = pin_in;\n          }\n          pin_state[i] = 0;\n        }\n        break;\n\n      default:\n\n        break;\n    }\n  }\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_hw_op3_button_read\n     WORK    :\n---------------------------------------------------------------------------*/\nuint8_t dxl_hw_op3_button_read(uint8_t pin_num)\n{\n  uint8_t pin_in = 0;\n  uint8_t i;\n\n  for(i=0; i<BUTTON_PIN_MAX; i++)\n  {\n    if(button_pin_num[i] == pin_num)\n    {\n      break;\n    }\n  }\n\n  if(i == BUTTON_PIN_MAX) return 0;\n\n  pin_in = button_value[i];\n\n  return pin_in;\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_hw_op3_led_set\n     WORK    :\n---------------------------------------------------------------------------*/\nvoid dxl_hw_op3_led_set(uint8_t pin_num, uint8_t value)\n{\n  digitalWrite(pin_num, value);\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_hw_op3_led_pwm\n     WORK    :\n---------------------------------------------------------------------------*/\nvoid dxl_hw_op3_led_pwm(uint8_t pin_num, uint8_t value)\n{\n  switch(pin_num)\n  {\n    case PIN_LED_R:\n      led_pwm_value[0] = constrain(value, 0, LED_PWM_PWM_MAX);\n      break;\n\n    case PIN_LED_G:\n      led_pwm_value[1] = constrain(value, 0, LED_PWM_PWM_MAX);\n      break;\n\n    case PIN_LED_B:\n      led_pwm_value[2] = constrain(value, 0, LED_PWM_PWM_MAX);\n      break;\n  }\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_hw_op3_voltage_update\n     WORK    :\n---------------------------------------------------------------------------*/\nvoid dxl_hw_op3_voltage_update(void)\n{\n  static bool startup = false;\n  static int adc_index = 0;\n  static int prev_state = 0;\n  static int alram_state = 0;\n  static int check_index = 0;\n\n  int i;\n  int adc_value;\n  int adc_sum;\n  float vol_value;\n\n  static uint32_t process_time[8] = {0,};\n  static uint16_t adc_value_tbl[10] = {0,};\n\n  float voltage_ref = 11.1;\n\n\n  if(millis()-process_time[0] > 100)\n  {\n    process_time[0] = millis();\n    adc_value = analogRead(BDPIN_BAT_PWR_ADC);\n\n    adc_value_tbl[adc_index] = adc_value;\n\n    adc_index++;\n    adc_index %= 10;\n\n    adc_sum = 0;\n    for(i=0; i<10; i++)\n    {\n        adc_sum += adc_value_tbl[i];\n    }\n    adc_value = adc_sum/10;\n    vol_value = map(adc_value, 0, 1023, 0, 331*57/10);\n    battery_valtage_raw = vol_value/100;\n\n    battery_valtage_raw += 0.5;\n\n    //Serial.println(vol_value);\n\n    vol_value = battery_valtage_raw * 10;\n    vol_value = constrain(vol_value, 0, 255);\n    battery_voltage = vol_value;\n  }\n\n\n  if(millis()-process_time[1] > 1000)\n  {\n    process_time[1] = millis();\n\n\n    switch(battery_state)\n    {\n      case BATTERY_POWER_OFF:\n        alram_state = 0;\n        if(battery_valtage_raw > voltage_ref*0.20)\n        {\n          prev_state    = battery_state;\n          battery_state = BATTERY_POWER_STARTUP;\n        }\n        else\n        {\n          noTone(BDPIN_BUZZER);\n        }\n        break;\n\n      case BATTERY_POWER_STARTUP:\n        if(battery_valtage_raw > voltage_ref)\n        {\n          prev_state    = battery_state;\n          battery_state = BATTERY_POWER_NORMAL;\n        }\n        else\n        {\n          prev_state    = battery_state;\n          battery_state = BATTERY_POWER_CHECK;\n        }\n        break;\n\n      case BATTERY_POWER_NORMAL:\n        alram_state = 0;\n        if(battery_valtage_raw < voltage_ref)\n        {\n          prev_state    = battery_state;\n          battery_state = BATTERY_POWER_CHECK;\n          check_index   = 0;\n        }\n        break;\n\n      case BATTERY_POWER_CHECK:\n        if(check_index < 5)\n        {\n          check_index++;\n        }\n        else\n        {\n          if(battery_valtage_raw < voltage_ref)\n          {\n            prev_state    = battery_state;\n            battery_state = BATTERY_POWER_WARNNING;\n          }\n        }\n        if(battery_valtage_raw >= voltage_ref)\n        {\n          prev_state    = battery_state;\n          battery_state = BATTERY_POWER_NORMAL;\n        }\n        break;\n\n      case BATTERY_POWER_WARNNING:\n        //alram_state ^= 1;\n        //if(alram_state)\n        //{\n        //  tone(BDPIN_BUZZER, 1000, 500);\n        //}\n\n        if(battery_valtage_raw > voltage_ref)\n        {\n          prev_state    = battery_state;\n          battery_state = BATTERY_POWER_NORMAL;\n        }\n        if(battery_valtage_raw < voltage_ref*0.20)\n        {\n          prev_state    = battery_state;\n          battery_state = BATTERY_POWER_OFF;\n        }\n        break;\n\n      default:\n        break;\n    }\n  }\n\n  if (battery_state == BATTERY_POWER_WARNNING)\n  {\n    if(millis()-process_time[2] >= 200)\n    {\n      process_time[2] = millis();\n\n      tone(BDPIN_BUZZER, 1000, 100);\n    }\n  }\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_hw_op3_voltage_read\n     WORK    :\n---------------------------------------------------------------------------*/\nuint8_t dxl_hw_op3_voltage_read(void)\n{\n  /*\n  int adc_value;\n  float vol_value;\n\n  adc_value = analogRead(BDPIN_BAT_PWR_ADC);\n\n  vol_value = map(adc_value, 0, 1023, 0, 330*57/10);\n  vol_value = vol_value/10;\n  vol_value = constrain(vol_value, 0, 255);\n  */\n\n  return (uint8_t)battery_voltage;\n}\n\n\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_hw_op3_gyro_conv\n     WORK    :\n---------------------------------------------------------------------------*/\nint16_t dxl_hw_op3_gyro_conv(int16_t value)\n{\n  int16_t  data;\n\n  #if 0\n  data = constrain(value, -8200, 8200); // 2000deg->500deg\n  data = map(data, -8200, 8200, 0, 1023);\n  #else\n  data = value;\n  #endif\n\n  return (int16_t)data;\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_hw_op3_acc_get_x\n     WORK    :\n---------------------------------------------------------------------------*/\nint16_t dxl_hw_op3_acc_get_x(void)\n{\n  return dxl_hw_op3_acc_conv(IMU.SEN.accRAW[0]);\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_hw_op3_acc_get_y\n     WORK    :\n---------------------------------------------------------------------------*/\nint16_t dxl_hw_op3_acc_get_y(void)\n{\n  int16_t ret;\n\n  ret = dxl_hw_op3_acc_conv(IMU.SEN.accRAW[1]);\n\n  return ret;\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_hw_op3_acc_get_z\n     WORK    :\n---------------------------------------------------------------------------*/\nint16_t dxl_hw_op3_acc_get_z(void)\n{\n  return dxl_hw_op3_acc_conv(IMU.SEN.accRAW[2]);\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_hw_op3_acc_get_x\n     WORK    :\n---------------------------------------------------------------------------*/\nint16_t dxl_hw_op3_gyro_get_x(void)\n{\n  return dxl_hw_op3_gyro_conv(IMU.SEN.gyroADC[0]);\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_hw_op3_acc_get_y\n     WORK    :\n---------------------------------------------------------------------------*/\nint16_t dxl_hw_op3_gyro_get_y(void)\n{\n  int16_t ret;\n\n  ret = dxl_hw_op3_gyro_conv(IMU.SEN.gyroADC[1]);\n\n  return ret;\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_hw_op3_acc_get_z\n     WORK    :\n---------------------------------------------------------------------------*/\nint16_t dxl_hw_op3_gyro_get_z(void)\n{\n  return dxl_hw_op3_gyro_conv(IMU.SEN.gyroADC[2]);\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_hw_op3_get_rpy\n     WORK    :\n---------------------------------------------------------------------------*/\nint16_t dxl_hw_op3_get_rpy(uint8_t rpy)\n{\n  int16_t ret;\n\n\n  switch(rpy)\n  {\n    case 0:\n      ret = (int16_t)((IMU.rpy[0]-imu_offset[0]) * 10.);\n      break;\n\n    case 1:\n      ret = (int16_t)((IMU.rpy[1]-imu_offset[1]) * 10.);\n      break;\n\n    case 2:\n      ret = (int16_t)((IMU.rpy[2]-imu_offset[2]) * 10.);\n      break;\n\n    default:\n      ret = (int16_t)((IMU.rpy[0]-imu_offset[0]) * 10.);\n      break;\n  }\n\n  return ret;\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_hw_op3_start_cali\n     WORK    :\n---------------------------------------------------------------------------*/\nvoid dxl_hw_op3_start_cali(uint8_t index)\n{\n  imu_cali_count[index]  = IMU_CALI_MAX_COUNT;\n  imu_cali_sum[index] = 0;\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_hw_op3_clear_cali\n     WORK    :\n---------------------------------------------------------------------------*/\nvoid dxl_hw_op3_clear_cali(uint8_t index)\n{\n  imu_cali_count[index] = 0;\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_hw_op3_get_cali\n     WORK    :\n---------------------------------------------------------------------------*/\nint16_t dxl_hw_op3_get_cali(uint8_t index)\n{\n  return imu_cali_count[index];\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_hw_op3_set_offset\n     WORK    :\n---------------------------------------------------------------------------*/\nvoid dxl_hw_op3_set_offset(uint8_t index, float offset_data)\n{\n  imu_offset[index] = offset_data;\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_hw_op3_get_offset\n     WORK    :\n---------------------------------------------------------------------------*/\nfloat dxl_hw_op3_get_offset(uint8_t index)\n{\n  return imu_offset[index];\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_hw_op3_start_gyro_cali\n     WORK    :\n---------------------------------------------------------------------------*/\nvoid dxl_hw_op3_start_gyro_cali(void)\n{\n  IMU.SEN.gyro_cali_start();\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_hw_op3_get_gyro_cali_done\n     WORK    :\n---------------------------------------------------------------------------*/\nbool dxl_hw_op3_get_gyro_cali_done(void)\n{\n  return IMU.SEN.gyro_cali_get_done();\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OP3/examples/opencr_op3/dxl_hw_op3.h",
    "content": "/*\n *  dxl_hw_op3.h\n *\n *  dynamixel hardware op3\n *\n *  Created on: 2016. 10. 21.\n *      Author: Baram\n */\n\n#ifndef DXL_HW_OP3_H\n#define DXL_HW_OP3_H\n\n\n#include \"dxl_def.h\"\n\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n\n#define PIN_LED_R         50\n#define PIN_LED_G         51\n#define PIN_LED_B         52\n\n#define PIN_LED_1         53\n#define PIN_LED_2         54\n#define PIN_LED_3         55\n\n#define PIN_BUTTON_S1     56\n#define PIN_BUTTON_S2     57\n#define PIN_BUTTON_S3     58\n#define PIN_BUTTON_S4     59\n\n\n\n\n\nvoid dxl_hw_op3_init(void);\nvoid dxl_hw_op3_update(void);\n\n// button\nuint8_t dxl_hw_op3_button_read(uint8_t pin_num);\n\n// led\nvoid dxl_hw_op3_led_set(uint8_t pin_num, uint8_t value);\nvoid dxl_hw_op3_led_pwm(uint8_t pin_num, uint8_t value);\n\n// voltage\nuint8_t dxl_hw_op3_voltage_read(void);\n\n// acc\nint16_t dxl_hw_op3_gyro_get_x(void);\nint16_t dxl_hw_op3_gyro_get_y(void);\nint16_t dxl_hw_op3_gyro_get_z(void);\n\nint16_t dxl_hw_op3_acc_get_x(void);\nint16_t dxl_hw_op3_acc_get_y(void);\nint16_t dxl_hw_op3_acc_get_z(void);\n\nint16_t dxl_hw_op3_get_rpy(uint8_t rpy);\nvoid    dxl_hw_op3_start_cali(uint8_t index);\nint16_t dxl_hw_op3_get_cali(uint8_t index);\nvoid    dxl_hw_op3_clear_cali(uint8_t index);\n\n\nvoid  dxl_hw_op3_set_offset(uint8_t index, float offset_data);\nfloat dxl_hw_op3_get_offset(uint8_t index);\n\nvoid dxl_hw_op3_start_gyro_cali(void);\nbool dxl_hw_op3_get_gyro_cali_done(void);\n\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OP3/examples/opencr_op3/dxl_node_op3.cpp",
    "content": "/*\n *  dxl_node_op3.cpp\n *\n *  dynamixel node op3\n *\n *  Created on: 2016. 10. 21.\n *      Author: Baram\n */\n\n#include \"dxl.h\"\n#include \"dxl_hw.h\"\n#include \"dxl_hw_op3.h\"\n#include \"dxl_node_op3.h\"\n#include \"dxl_debug.h\"\n#include <EEPROM.h>\n\n\n\n#define RANGE_CHECK(addr,x)            dxl_node_check_range(addr, (uint32_t)&(x), sizeof(x))\n\n\n\nstatic dxl_t dxl_sp;\n\n\ndxl_mem_op3_t *p_dxl_mem;\ndxl_mem_t      mem;\n\n\n\nvoid dxl_node_op3_reset(void);\nvoid dxl_node_op3_factory_reset(void);\nvoid dxl_node_op3_btn_loop(void);\n\n\n//-- dxl sp driver function\n//\ndxl_error_t ping(dxl_t *p_dxl);\ndxl_error_t read(dxl_t *p_dxl);\ndxl_error_t write(dxl_t *p_dxl);\ndxl_error_t sync_read(dxl_t *p_dxl);\ndxl_error_t sync_write(dxl_t *p_dxl);\ndxl_error_t bulk_read(dxl_t *p_dxl);\ndxl_error_t bulk_write(dxl_t *p_dxl);\n\n\nvoid dxl_process_packet();\n\n\nstatic uint8_t dxl_node_read_byte(uint16_t addr);\nstatic void    dxl_node_write_byte(uint16_t addr, uint8_t data);\n\nstatic BOOL dxl_node_check_range(uint16_t addr, uint32_t addr_ptr, uint8_t length);\nvoid dxl_node_op3_change_baud(void);\n\nstatic void dxl_node_update_tx_rx_led();\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_node_op3_init\n     WORK    :\n---------------------------------------------------------------------------*/\nvoid dxl_node_op3_init(void)\n{\n  p_dxl_mem = (dxl_mem_op3_t *)&mem.data;\n\n\n  dxlInit(&dxl_sp, DXL_PACKET_VER_2_0);\n\n\n  dxl_hw_op3_init();\n  dxl_node_op3_reset();\n\n  if( p_dxl_mem->Model_Number != DXL_NODE_OP3_MODLE_NUMBER )\n  {\n    dxl_node_op3_factory_reset();\n    dxl_node_op3_reset();\n  }\n\n  if( p_dxl_mem->Firmware_Version != DXL_NODE_OP3_FW_VER )\n  {\n    p_dxl_mem->Firmware_Version = DXL_NODE_OP3_FW_VER;\n    EEPROM[2] = mem.data[2];\n  }\n\n\n  p_dxl_mem->IMU_Control = 0;\n\n  dxl_node_write_byte(26, (0x1F<<0));\n  dxl_node_write_byte(27, (0x00<<0));\n\n\n\n  dxlSetId(&dxl_sp, p_dxl_mem->ID);\n  dxlOpenPort(&dxl_sp, 0, p_dxl_mem->Baud);\n\n\n  dxlAddInstFunc(&dxl_sp, INST_PING,  ping);\n  dxlAddInstFunc(&dxl_sp, INST_READ,  read);\n  dxlAddInstFunc(&dxl_sp, INST_WRITE, write);\n  dxlAddInstFunc(&dxl_sp, INST_SYNC_READ, sync_read);\n  dxlAddInstFunc(&dxl_sp, INST_SYNC_WRITE, sync_write);\n  dxlAddInstFunc(&dxl_sp, INST_BULK_READ, bulk_read);\n  dxlAddInstFunc(&dxl_sp, INST_BULK_WRITE, bulk_write);\n\n  dxl_debug_init();\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_node_op3_loop\n     WORK    :\n---------------------------------------------------------------------------*/\nvoid dxl_node_op3_loop(void)\n{\n  static uint8_t  gyro_cali_state = 0;\n  uint8_t i;\n\n  dxl_process_packet();\n  dxl_node_update_tx_rx_led();\n\n\n  dxl_hw_op3_update();\n\n\n  p_dxl_mem->Acc_X  = dxl_hw_op3_acc_get_x();\n  p_dxl_mem->Acc_Y  = dxl_hw_op3_acc_get_y();\n  p_dxl_mem->Acc_Z  = dxl_hw_op3_acc_get_z();\n\n  p_dxl_mem->Gyro_X = dxl_hw_op3_gyro_get_x();\n  p_dxl_mem->Gyro_Y = dxl_hw_op3_gyro_get_y();\n  p_dxl_mem->Gyro_Z = dxl_hw_op3_gyro_get_z();\n\n  p_dxl_mem->Roll   = dxl_hw_op3_get_rpy(0);\n  p_dxl_mem->Pitch  = dxl_hw_op3_get_rpy(1);\n  p_dxl_mem->Yaw    = dxl_hw_op3_get_rpy(2);\n\n\n  for(i=0; i<3; i++)\n  {\n    if(p_dxl_mem->IMU_Control & (1<<i))\n    {\n      if(dxl_hw_op3_get_cali(i) == 0)\n      {\n        dxl_hw_op3_start_cali(i);\n      }\n      if(dxl_hw_op3_get_cali(i) < 0)\n      {\n        p_dxl_mem->IMU_Control &= ~(1<<i);\n        dxl_hw_op3_clear_cali(i);\n\n        p_dxl_mem->Roll_Offset  = dxl_hw_op3_get_offset(0) * 10.;\n        p_dxl_mem->Pitch_Offset = dxl_hw_op3_get_offset(1) * 10.;\n        p_dxl_mem->Yaw_Offset   = dxl_hw_op3_get_offset(2) * 10.;\n\n\n        EEPROM[18] = mem.data[18];\n        EEPROM[19] = mem.data[19];\n        EEPROM[20] = mem.data[20];\n        EEPROM[21] = mem.data[21];\n      }\n    }\n  }\n\n  if(p_dxl_mem->IMU_Control & (1<<3))\n  {\n    if(gyro_cali_state == 0)\n    {\n      dxl_hw_op3_start_gyro_cali();\n      gyro_cali_state = 1;\n    }\n    else\n    {\n      if(dxl_hw_op3_get_gyro_cali_done() == true)\n      {\n        p_dxl_mem->IMU_Control &= ~(1<<3);\n        gyro_cali_state = 0;\n      }\n    }\n\n  }\n\n\n  dxl_node_op3_btn_loop();\n\n  dxl_debug_loop();\n}\n\n\nvoid dxl_process_packet()\n{\n  static uint8_t process_state = 0;\n  dxl_error_t dxl_ret;\n  static uint32_t pre_time;\n\n\n  switch (process_state)\n  {\n    //-- INST\n    //\n    case DXL_PROCESS_INST:\n      dxl_ret = dxlRxPacket(&dxl_sp);\n\n      if (dxl_ret == DXL_RET_RX_INST)\n      {\n        dxl_ret = dxlProcessInst(&dxl_sp);\n\n        if (dxl_ret == DXL_RET_PROCESS_BROAD_PING)\n        {\n          dxl_sp.current_id = 1;\n          pre_time = micros();\n          process_state = DXL_PROCESS_BROAD_PING;\n        }\n\n        if (dxl_ret == DXL_RET_PROCESS_BROAD_READ)\n        {\n          pre_time = micros();\n          process_state = DXL_PROCESS_BROAD_READ;\n        }\n      }\n      break;\n\n\n    //-- BROAD_PING\n    //\n    case DXL_PROCESS_BROAD_PING:\n      dxl_ret = dxlRxPacket(&dxl_sp);\n\n      if (dxl_ret == DXL_RET_RX_STATUS)\n      {\n        dxl_sp.current_id = dxl_sp.rx.id + 1;\n      }\n      else\n      {\n        if (micros()-pre_time >= 3000)\n        {\n          pre_time = micros();\n          dxl_sp.current_id++;\n        }\n      }\n\n      if (dxl_sp.current_id == dxl_sp.id)\n      {\n        dxlTxPacket(&dxl_sp);\n        process_state = DXL_PROCESS_INST;\n      }\n      break;\n\n    //-- BROAD_READ\n    //\n    case DXL_PROCESS_BROAD_READ:\n      dxl_ret = dxlRxPacket(&dxl_sp);\n\n      if (dxl_ret == DXL_RET_RX_STATUS)\n      {\n        pre_time = micros();\n        if (dxl_sp.pre_id == dxl_sp.rx.id)\n        {\n          dxlTxPacket(&dxl_sp);\n          process_state = DXL_PROCESS_INST;\n          //Serial.println(\" Bulk Read out\");\n        }\n        else\n        {\n          //Serial.print(\" in \");\n          //Serial.println(dxl_sp.rx.id, HEX);\n        }\n      }\n      else\n      {\n        if (micros()-pre_time >= 50000)\n        {\n          process_state = DXL_PROCESS_INST;\n          //Serial.println(\" Bulk Read timeout\");\n        }\n      }\n      break;\n\n\n    default:\n      process_state = DXL_PROCESS_INST;\n      break;\n  }\n\n}\n\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_node_op3_btn_loop\n     WORK    :\n---------------------------------------------------------------------------*/\nvoid dxl_node_op3_btn_loop(void)\n{\n  static uint8_t  btn_state = 0;\n  static uint32_t btn_time  = 0;\n\n\n  switch( btn_state )\n  {\n    case 0:\n      if( dxl_hw_op3_button_read(PIN_BUTTON_S4) )\n      {\n        btn_time  = millis();\n        btn_state = 1;\n      }\n      break;\n\n    case 1:\n      if( !dxl_hw_op3_button_read(PIN_BUTTON_S4) ) btn_state = 0;\n      if( (millis()-btn_time) > 100 )\n      {\n        dxl_node_write_byte(24, 0);\n        btn_time  = millis();\n        btn_state = 2;\n      }\n      break;\n\n    case 2:\n      if( !dxl_hw_op3_button_read(PIN_BUTTON_S4) ) btn_state = 0;\n      break;\n\n    default:\n      break;\n  }\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_node_op3_reset\n     WORK    :\n---------------------------------------------------------------------------*/\nvoid dxl_node_op3_reset(void)\n{\n  uint16_t i;\n\n\n  memset(&mem, 0x00, sizeof(dxl_mem_t));\n\n  mem.attr[0]   = DXL_MEM_ATTR_EEPROM | DXL_MEM_ATTR_RO;\n  mem.attr[1]   = DXL_MEM_ATTR_EEPROM | DXL_MEM_ATTR_RO;\n  mem.attr[2]   = DXL_MEM_ATTR_EEPROM | DXL_MEM_ATTR_RO;\n  mem.attr[3]   = DXL_MEM_ATTR_EEPROM | DXL_MEM_ATTR_RW;\n  mem.attr[4]   = DXL_MEM_ATTR_EEPROM | DXL_MEM_ATTR_RW;\n  mem.attr[5]   = DXL_MEM_ATTR_EEPROM | DXL_MEM_ATTR_RW;\n  mem.attr[16]  = DXL_MEM_ATTR_EEPROM | DXL_MEM_ATTR_RW;\n  mem.attr[18]  = DXL_MEM_ATTR_EEPROM | DXL_MEM_ATTR_RW;\n  mem.attr[19]  = DXL_MEM_ATTR_EEPROM | DXL_MEM_ATTR_RW;\n  mem.attr[20]  = DXL_MEM_ATTR_EEPROM | DXL_MEM_ATTR_RW;\n  mem.attr[21]  = DXL_MEM_ATTR_EEPROM | DXL_MEM_ATTR_RW;\n  mem.attr[22]  = DXL_MEM_ATTR_EEPROM | DXL_MEM_ATTR_RW;\n  mem.attr[23]  = DXL_MEM_ATTR_EEPROM | DXL_MEM_ATTR_RW;\n\n  mem.attr[24]  = DXL_MEM_ATTR_RAM    | DXL_MEM_ATTR_RW;\n  mem.attr[25]  = DXL_MEM_ATTR_RAM    | DXL_MEM_ATTR_RW;\n  mem.attr[26]  = DXL_MEM_ATTR_RAM    | DXL_MEM_ATTR_RW;\n  mem.attr[27]  = DXL_MEM_ATTR_RAM    | DXL_MEM_ATTR_RW;\n  mem.attr[28]  = DXL_MEM_ATTR_RAM    | DXL_MEM_ATTR_RW;\n  mem.attr[29]  = DXL_MEM_ATTR_RAM    | DXL_MEM_ATTR_RW;\n  mem.attr[30]  = DXL_MEM_ATTR_RAM    | DXL_MEM_ATTR_RO;\n  mem.attr[31]  = DXL_MEM_ATTR_RAM    | DXL_MEM_ATTR_RO;\n  mem.attr[32]  = DXL_MEM_ATTR_RAM    | DXL_MEM_ATTR_RO;\n  mem.attr[33]  = DXL_MEM_ATTR_RAM    | DXL_MEM_ATTR_RO;\n  mem.attr[34]  = DXL_MEM_ATTR_RAM    | DXL_MEM_ATTR_RO;\n  mem.attr[35]  = DXL_MEM_ATTR_RAM    | DXL_MEM_ATTR_RO;\n  mem.attr[36]  = DXL_MEM_ATTR_RAM    | DXL_MEM_ATTR_RO;\n  mem.attr[37]  = DXL_MEM_ATTR_RAM    | DXL_MEM_ATTR_RO;\n  mem.attr[38]  = DXL_MEM_ATTR_RAM    | DXL_MEM_ATTR_RO;\n  mem.attr[39]  = DXL_MEM_ATTR_RAM    | DXL_MEM_ATTR_RO;\n  mem.attr[40]  = DXL_MEM_ATTR_RAM    | DXL_MEM_ATTR_RO;\n  mem.attr[41]  = DXL_MEM_ATTR_RAM    | DXL_MEM_ATTR_RO;\n  mem.attr[42]  = DXL_MEM_ATTR_RAM    | DXL_MEM_ATTR_RO;\n  mem.attr[43]  = DXL_MEM_ATTR_RAM    | DXL_MEM_ATTR_RO;\n  mem.attr[44]  = DXL_MEM_ATTR_RAM    | DXL_MEM_ATTR_RO;\n  mem.attr[45]  = DXL_MEM_ATTR_RAM    | DXL_MEM_ATTR_RO;\n  mem.attr[46]  = DXL_MEM_ATTR_RAM    | DXL_MEM_ATTR_RO;\n  mem.attr[47]  = DXL_MEM_ATTR_RAM    | DXL_MEM_ATTR_RO;\n  mem.attr[48]  = DXL_MEM_ATTR_RAM    | DXL_MEM_ATTR_RO;\n  mem.attr[49]  = DXL_MEM_ATTR_RAM    | DXL_MEM_ATTR_RO;\n  mem.attr[50]  = DXL_MEM_ATTR_RAM    | DXL_MEM_ATTR_RW;\n\n\n  // EEPROM Load\n  for( i=0; i<sizeof(dxl_mem_op3_t); i++ )\n  {\n    if( mem.attr[i]&DXL_MEM_ATTR_EEPROM )\n    {\n      mem.data[i] = EEPROM[i];\n    }\n  }\n\n  dxl_hw_op3_set_offset(0, (float)p_dxl_mem->Roll_Offset/10.);\n  dxl_hw_op3_set_offset(1, (float)p_dxl_mem->Pitch_Offset/10.);\n  //dxl_hw_op3_set_offset(2, (float)p_dxl_mem->Yaw_Offset/10.);\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_node_op3_factory_reset\n     WORK    :\n---------------------------------------------------------------------------*/\nvoid dxl_node_op3_factory_reset(void)\n{\n  uint16_t i;\n\n\n  p_dxl_mem->Model_Number         = DXL_NODE_OP3_MODLE_NUMBER;\n  p_dxl_mem->Firmware_Version     = DXL_NODE_OP3_FW_VER;\n  p_dxl_mem->ID                   = DXL_NODE_OP3_ID;\n  p_dxl_mem->Baud                 = DXL_NODE_OP3_BAUD;\n  p_dxl_mem->Return_Delay_Time    = 0;\n  p_dxl_mem->Status_Return_Level  = 2;\n  p_dxl_mem->Roll_Offset          = 0;\n  p_dxl_mem->Pitch_Offset         = 0;\n  p_dxl_mem->Yaw_Offset           = 0;\n\n  // EEPROM Save\n  for( i=0; i<sizeof(dxl_mem_op3_t); i++ )\n  {\n    if( mem.attr[i]&DXL_MEM_ATTR_EEPROM )\n    {\n      EEPROM[i] = mem.data[i];\n    }\n  }\n\n  dxl_node_op3_reset();\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_node_op3_change_baud\n     WORK    :\n---------------------------------------------------------------------------*/\nvoid dxl_node_op3_change_baud(void)\n{\n  dxlOpenPort(&dxl_sp, 0, p_dxl_mem->Baud);\n}\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_node_read_byte\n     WORK    :\n---------------------------------------------------------------------------*/\nuint8_t dxl_node_read_byte(uint16_t addr)\n{\n  if( RANGE_CHECK(addr, p_dxl_mem->Button) )\n  {\n    p_dxl_mem->Button  = dxl_hw_op3_button_read(PIN_BUTTON_S1)<<0;\n    p_dxl_mem->Button |= dxl_hw_op3_button_read(PIN_BUTTON_S2)<<1;\n    p_dxl_mem->Button |= dxl_hw_op3_button_read(PIN_BUTTON_S3)<<2;\n    p_dxl_mem->Button |= dxl_hw_op3_button_read(PIN_BUTTON_S4)<<3;\n  }\n\n  if( RANGE_CHECK(addr, p_dxl_mem->Voltage) )\n  {\n    p_dxl_mem->Voltage  = dxl_hw_op3_voltage_read();\n  }\n\n\n  return mem.data[addr];\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_node_write_byte\n     WORK    :\n---------------------------------------------------------------------------*/\nvoid dxl_node_write_byte(uint16_t addr, uint8_t data)\n{\n  uint8_t pwm_value[3];\n\n\n  mem.data[addr] = data;\n\n\n\n  if( RANGE_CHECK(addr, p_dxl_mem->Dynamixel_Power) )\n  {\n    if( p_dxl_mem->Dynamixel_Power == 1 ) dxl_hw_power_enable();\n    else                                  dxl_hw_power_disable();\n  }\n\n  if( RANGE_CHECK(addr, p_dxl_mem->LED) )\n  {\n    if( data & (1<<0) ) dxl_hw_op3_led_set(PIN_LED_1, 0);\n    else                dxl_hw_op3_led_set(PIN_LED_1, 1);\n    if( data & (1<<1) ) dxl_hw_op3_led_set(PIN_LED_2, 0);\n    else                dxl_hw_op3_led_set(PIN_LED_2, 1);\n    if( data & (1<<2) ) dxl_hw_op3_led_set(PIN_LED_3, 0);\n    else                dxl_hw_op3_led_set(PIN_LED_3, 1);\n  }\n\n  if( RANGE_CHECK(addr, p_dxl_mem->LED_RGB) )\n  {\n    pwm_value[0] = (p_dxl_mem->LED_RGB>> 0) & 0x1F;\n    pwm_value[1] = (p_dxl_mem->LED_RGB>> 5) & 0x1F;\n    pwm_value[2] = (p_dxl_mem->LED_RGB>>10) & 0x1F;\n\n    dxl_hw_op3_led_pwm(PIN_LED_R, pwm_value[0]);\n    dxl_hw_op3_led_pwm(PIN_LED_G, pwm_value[1]);\n    dxl_hw_op3_led_pwm(PIN_LED_B, pwm_value[2]);\n  }\n\n  if( RANGE_CHECK(addr, p_dxl_mem->Baud) )\n  {\n    dxl_node_op3_change_baud();\n  }\n\n  if( RANGE_CHECK(addr, p_dxl_mem->Buzzer) )\n  {\n    if( p_dxl_mem->Buzzer > 0 ) tone(BDPIN_BUZZER, p_dxl_mem->Buzzer);\n    else                        noTone(BDPIN_BUZZER);\n  }\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : dxl_node_check_range\n     WORK    :\n---------------------------------------------------------------------------*/\nBOOL dxl_node_check_range(uint16_t addr, uint32_t addr_ptr, uint8_t length)\n{\n  BOOL ret = FALSE;\n  uint32_t addr_offset;\n\n  addr_offset = addr_ptr - (uint32_t)p_dxl_mem;\n\n  if( addr >= (addr_offset+length-1) && addr < (addr_offset+length) )\n  {\n    ret = TRUE;\n  }\n\n\n  return ret;\n}\n\n\n/*---------------------------------------------------------------------------\n     dxl sp driver\n---------------------------------------------------------------------------*/\nvoid processRead(uint16_t addr, uint8_t *p_data, uint16_t length)\n{\n  uint32_t i;\n\n\n  for( i=0; i<length; i++ )\n  {\n    p_data[i] = dxl_node_read_byte(addr);\n    addr++;\n  }\n}\n\nvoid processWrite(uint16_t addr, uint8_t *p_data, uint16_t length)\n{\n  uint32_t i;\n\n\n  for( i=0; i<length; i++ )\n  {\n    if( mem.attr[addr]&DXL_MEM_ATTR_WO || mem.attr[addr]&DXL_MEM_ATTR_RW )\n    {\n      dxl_node_write_byte(addr, p_data[i]);\n      if( mem.attr[addr]&DXL_MEM_ATTR_EEPROM )\n      {\n        EEPROM[addr] = mem.data[addr];\n      }\n    }\n    addr++;\n  }\n}\n\n\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : ping\n     WORK    :\n---------------------------------------------------------------------------*/\ndxl_error_t ping(dxl_t *p_dxl)\n{\n  dxl_error_t ret = DXL_RET_OK;\n  uint8_t data[3];\n\n\n\n  data[0] = (p_dxl_mem->Model_Number>>0) & 0xFF;\n  data[1] = (p_dxl_mem->Model_Number>>8) & 0xFF;\n  data[2] = p_dxl_mem->Firmware_Version;\n\n  if (p_dxl->rx.id == DXL_GLOBAL_ID)\n  {\n    ret = dxlMakePacketStatus(p_dxl, p_dxl->id, 0, data, 3);\n\n    if (ret == DXL_RET_OK)\n    {\n      ret = DXL_RET_PROCESS_BROAD_PING;\n    }\n  }\n  else\n  {\n    ret = dxlTxPacketStatus(p_dxl, p_dxl->id, 0, data, 3);\n  }\n\n\n  return ret;\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : read\n     WORK    :\n---------------------------------------------------------------------------*/\ndxl_error_t read(dxl_t *p_dxl)\n{\n  dxl_error_t ret = DXL_RET_OK;\n  uint16_t addr;\n  uint16_t length;\n  uint8_t data[DXL_MAX_BUFFER];\n\n\n  if (p_dxl->rx.id == DXL_GLOBAL_ID || p_dxl->rx.param_length != 4)\n  {\n    return DXL_RET_EMPTY;\n  }\n\n\n  addr   = (p_dxl->rx.p_param[1]<<8) | p_dxl->rx.p_param[0];\n  length = (p_dxl->rx.p_param[3]<<8) | p_dxl->rx.p_param[2];\n\n\n  if (addr >= sizeof(dxl_mem_op3_t))\n  {\n    dxlTxPacketStatus(p_dxl, p_dxl->id, DXL_ERR_DATA_LENGTH, NULL, 0);\n    return DXL_RET_ERROR_LENGTH;\n  }\n  if( length > DXL_MAX_BUFFER - 10 )\n  {\n    dxlTxPacketStatus(p_dxl, p_dxl->id, DXL_ERR_DATA_LENGTH, NULL, 0);\n    return DXL_RET_ERROR_LENGTH;\n  }\n\n  processRead(addr, data, length);\n\n\n  ret = dxlTxPacketStatus(p_dxl, p_dxl->id, 0, data, length);\n\n  //Serial.println(\" Read\");\n\n  return ret;\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : write\n     WORK    :\n---------------------------------------------------------------------------*/\ndxl_error_t write(dxl_t *p_dxl)\n{\n  dxl_error_t ret = DXL_RET_OK;\n  uint16_t addr;\n  uint16_t length;\n  uint8_t  *p_data;\n\n\n  if (p_dxl->rx.id == DXL_GLOBAL_ID)\n  {\n    return DXL_RET_EMPTY;\n  }\n\n  addr   = (p_dxl->rx.p_param[1]<<8) | p_dxl->rx.p_param[0];\n  p_data = &p_dxl->rx.p_param[2];\n\n  if (p_dxl->rx.param_length > 2 )\n  {\n    length = p_dxl->rx.param_length - 2;\n  }\n  else\n  {\n    dxlTxPacketStatus(p_dxl, p_dxl->id, DXL_ERR_DATA_LENGTH, NULL, 0);\n    return DXL_RET_ERROR_LENGTH;\n  }\n\n  if (addr >= sizeof(dxl_mem_op3_t))\n  {\n    dxlTxPacketStatus(p_dxl, p_dxl->id, DXL_ERR_DATA_LENGTH, NULL, 0);\n    return DXL_RET_ERROR_LENGTH;\n  }\n  if( length > DXL_MAX_BUFFER - 10 )\n  {\n    dxlTxPacketStatus(p_dxl, p_dxl->id, DXL_ERR_DATA_LENGTH, NULL, 0);\n    return DXL_RET_ERROR_LENGTH;\n  }\n\n\n  dxlTxPacketStatus(p_dxl, p_dxl->id, DXL_ERR_NONE, NULL, 0);\n\n\n  processWrite(addr, p_data, length);\n\n  //Serial.println(\" write\");\n  return ret;\n}\n\n\ndxl_error_t sync_read(dxl_t *p_dxl)\n{\n  dxl_error_t ret = DXL_RET_OK;\n  uint16_t addr;\n  uint16_t length;\n  uint8_t  *p_data;\n  uint16_t i;\n  uint16_t rx_id_cnt;\n  uint8_t data[DXL_MAX_BUFFER];\n\n\n  if (p_dxl->rx.id != DXL_GLOBAL_ID)\n  {\n    return DXL_RET_EMPTY;\n  }\n\n  addr      = (p_dxl->rx.p_param[1]<<8) | p_dxl->rx.p_param[0];\n  length    = (p_dxl->rx.p_param[3]<<8) | p_dxl->rx.p_param[2];\n  p_data    = &p_dxl->rx.p_param[4];\n  rx_id_cnt = p_dxl->rx.param_length - 4;\n\n\n  if (p_dxl->rx.param_length < (5) || rx_id_cnt > 255)\n  {\n    //dxlTxPacketStatus(p_dxl, p_dxl->id, DXL_ERR_DATA_LENGTH, NULL, 0);\n    return DXL_RET_ERROR_LENGTH;\n  }\n  if (addr >= sizeof(dxl_mem_op3_t) || (addr+length) > sizeof(dxl_mem_op3_t))\n  {\n    //dxlTxPacketStatus(p_dxl, p_dxl->id, DXL_ERR_DATA_LENGTH, NULL, 0);\n    return DXL_RET_ERROR_LENGTH;\n  }\n\n\n\n\n  p_dxl->pre_id     = 0xFF;\n  p_dxl->current_id = 0xFF;\n\n  for (i=0; i<rx_id_cnt; i++)\n  {\n    if (p_data[i] == p_dxl->id)\n    {\n      p_dxl->current_id = p_dxl->id;\n      break;\n    }\n\n    p_dxl->pre_id = p_data[i];\n  }\n\n\n  if (p_dxl->current_id == p_dxl->id)\n  {\n    processRead(addr, data, length);\n\n\n    if (p_dxl->pre_id == 0xFF)\n    {\n      ret = dxlTxPacketStatus(p_dxl, p_dxl->id, 0, data, length);\n    }\n    else\n    {\n      ret = dxlMakePacketStatus(p_dxl, p_dxl->id, 0, data, length);\n      if (ret == DXL_RET_OK)\n      {\n        ret = DXL_RET_PROCESS_BROAD_READ;\n      }\n    }\n  }\n\n  //Serial.println(\" Sync Read\");\n\n  return ret;\n}\n\n\ndxl_error_t sync_write(dxl_t *p_dxl)\n{\n  dxl_error_t ret = DXL_RET_OK;\n  uint16_t addr;\n  uint16_t length;\n  uint8_t  *p_data;\n  uint16_t remain_length;\n  uint16_t index;\n\n  if (p_dxl->rx.id != DXL_GLOBAL_ID)\n  {\n    //Serial.println(\" Sync Write Err 0\");\n    return DXL_RET_EMPTY;\n  }\n\n  addr   = (p_dxl->rx.p_param[1]<<8) | p_dxl->rx.p_param[0];\n  length = (p_dxl->rx.p_param[3]<<8) | p_dxl->rx.p_param[2];\n\n\n\n  //Serial.print(\" Sync Write in : \");\n  //Serial.print(addr);\n  //Serial.print(\" \");\n  //Serial.println(length);\n\n  if (p_dxl->rx.param_length < (4+length+1))\n  {\n    //dxlTxPacketStatus(p_dxl, p_dxl->id, DXL_ERR_DATA_LENGTH, NULL, 0);\n    //Serial.println(\" Sync Write Err 1\");\n    return DXL_RET_ERROR_LENGTH;\n  }\n  if (addr >= sizeof(dxl_mem_op3_t) || (addr+length) > sizeof(dxl_mem_op3_t))\n  {\n    //dxlTxPacketStatus(p_dxl, p_dxl->id, DXL_ERR_DATA_LENGTH, NULL, 0);\n    //Serial.println(\" Sync Write Err 2\");\n    return DXL_RET_ERROR_LENGTH;\n  }\n\n\n\n\n  index = 4;\n  while(1)\n  {\n    p_data = &p_dxl->rx.p_param[index];\n    remain_length = p_dxl->rx.param_length - index;\n\n\n    if (remain_length < (length+1))\n    {\n      break;\n    }\n    else\n    {\n      if (p_data[0] == p_dxl->id)\n      {\n        processWrite(addr, &p_data[1], length);\n        //Serial.println(\" Sync Write out\");\n        break;\n      }\n\n      index += length + 1;\n    }\n  }\n\n  return ret;\n}\n\n\ndxl_error_t bulk_read(dxl_t *p_dxl)\n{\n  dxl_error_t ret = DXL_RET_OK;\n  uint16_t addr;\n  uint16_t length;\n  uint8_t  *p_data;\n  uint16_t i;\n  uint16_t rx_id_cnt;\n  uint8_t data[DXL_MAX_BUFFER];\n\n\n\n  if (p_dxl->rx.id != DXL_GLOBAL_ID)\n  {\n    return DXL_RET_EMPTY;\n  }\n\n\n  rx_id_cnt = p_dxl->rx.param_length / 5;\n\n\n  if (p_dxl->rx.param_length < 5 || (p_dxl->rx.param_length%5) != 0)\n  {\n    //Serial.print(\" DXL_RET_ERROR_LENGTH \");\n    return DXL_RET_ERROR_LENGTH;\n  }\n\n\n  p_dxl->pre_id     = 0xFF;\n  p_dxl->current_id = 0xFF;\n\n  for (i=0; i<rx_id_cnt; i++)\n  {\n    p_data = &p_dxl->rx.p_param[i*5];\n    addr   = (p_data[2]<<8) | p_data[1];\n    length = (p_data[4]<<8) | p_data[3];\n\n\n    //Serial.print(\" bulk in id \");\n    //Serial.println(p_data[0], HEX);\n\n    if (p_data[0] == p_dxl->id)\n    {\n      p_dxl->current_id = p_dxl->id;\n      break;\n    }\n    p_dxl->pre_id = p_data[0];\n  }\n\n\n  if (p_dxl->current_id == p_dxl->id)\n  {\n    if (addr >= sizeof(dxl_mem_op3_t) || (addr+length) > sizeof(dxl_mem_op3_t))\n    {\n      return DXL_RET_ERROR_LENGTH;\n    }\n\n\n    processRead(addr, data, length);\n\n\n    if (p_dxl->pre_id == 0xFF)\n    {\n      ret = dxlTxPacketStatus(p_dxl, p_dxl->id, 0, data, length);\n    }\n    else\n    {\n      ret = dxlMakePacketStatus(p_dxl, p_dxl->id, 0, data, length);\n      if (ret == DXL_RET_OK)\n      {\n        ret = DXL_RET_PROCESS_BROAD_READ;\n      }\n    }\n  }\n\n  return ret;\n}\n\n\ndxl_error_t bulk_write(dxl_t *p_dxl)\n{\n  dxl_error_t ret = DXL_RET_OK;\n  uint16_t addr;\n  uint16_t length;\n  uint8_t  *p_data;\n  uint16_t index;\n\n  if (p_dxl->rx.id != DXL_GLOBAL_ID)\n  {\n    return DXL_RET_EMPTY;\n  }\n\n\n  index = 0;\n  while(1)\n  {\n    p_data = &p_dxl->rx.p_param[index];\n    addr   = (p_data[2]<<8) | p_data[1];\n    length = (p_data[4]<<8) | p_data[3];\n\n    index += 5;\n\n    if (p_dxl->rx.param_length < (index + length))\n    {\n      break;\n    }\n\n    if (p_data[0] == p_dxl->id)\n    {\n      if (addr >= sizeof(dxl_mem_op3_t) || (addr+length) > sizeof(dxl_mem_op3_t))\n      {\n        return DXL_RET_ERROR_LENGTH;\n      }\n      processWrite(addr, &p_dxl->rx.p_param[index], length);\n\n      //Serial.print(addr);\n      //Serial.print(\" \");\n      //Serial.print(length);\n      //Serial.print(\" \");\n      //Serial.println(\" bulk write \");\n      break;\n    }\n    index += length;\n  }\n\n  return ret;\n}\n\n\nextern uint32_t tx_led_count, rx_led_count;\n\nstatic void dxl_node_update_tx_rx_led()\n{\n  static uint32_t tx_led_update_time = millis();\n  static uint32_t rx_led_update_time = millis();\n\n  if( (millis()-tx_led_update_time) > 50 )\n  {\n    tx_led_update_time = millis();\n\n    if( tx_led_count )\n    {\n      digitalWriteFast(DXL_LED_TX, !digitalReadFast(DXL_LED_TX));\n      tx_led_count--;\n    }\n    else\n    {\n      digitalWriteFast(DXL_LED_TX, HIGH);\n    }\n  }\n\n  if( (millis()-rx_led_update_time) > 50 )\n  {\n    rx_led_update_time = millis();\n\n    if( rx_led_count )\n    {\n      digitalWriteFast(DXL_LED_RX, !digitalReadFast(DXL_LED_RX));\n      rx_led_count--;\n    }\n    else\n    {\n      digitalWriteFast(DXL_LED_RX, HIGH);\n    }\n  }\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OP3/examples/opencr_op3/dxl_node_op3.h",
    "content": "/*\n *  dxl_node_op3.h\n *\n *  dynamixel node op3\n *\n *  Created on: 2016. 10. 21.\n *      Author: Baram\n */\n\n#ifndef DXL_NODE_OP3_H\n#define DXL_NODE_OP3_H\n\n\n#include \"dxl.h\"\n#include \"dxl_def.h\"\n\n\n\n#define DXL_NODE_OP3_ID                   200         // 0xC8\n#define DXL_NODE_OP3_MODLE_NUMBER         0x7400\n#define DXL_NODE_OP3_FW_VER               0x02\n#define DXL_NODE_OP3_BAUD                 4\n\n\n\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n\n\ntypedef struct\n{\n  uint16_t Model_Number;                  // 0\n  uint8_t  Firmware_Version;              // 2\n  uint8_t  ID;                            // 3\n  uint8_t  Baud;                          // 4\n  uint8_t  Return_Delay_Time;             // 5\n  uint8_t  Dummy1[10];                    // 6\n  uint8_t  Status_Return_Level;           // 16\n  uint8_t  Dummy2[1];                     // 17\n  int16_t  Roll_Offset;                   // 18\n  int16_t  Pitch_Offset;                  // 20\n  int16_t  Yaw_Offset;                    // 22\n\n  uint8_t  Dynamixel_Power;               // 24\n  uint8_t  LED;                           // 25\n  uint16_t LED_RGB;                       // 26\n  uint16_t Buzzer;                        // 28\n  uint8_t  Button;                        // 30\n  uint8_t  Voltage;                       // 31\n  int16_t  Gyro_X;                        // 32\n  int16_t  Gyro_Y;                        // 34\n  int16_t  Gyro_Z;                        // 36\n  int16_t  Acc_X;                         // 38\n  int16_t  Acc_Y;                         // 40\n  int16_t  Acc_Z;                         // 42\n  int16_t  Roll;                          // 44\n  int16_t  Pitch;                         // 46\n  int16_t  Yaw;                           // 48\n  uint8_t  IMU_Control;                   // 50\n\n} __attribute__((packed)) dxl_mem_op3_t;\n\n\n\n\n\n\nvoid dxl_node_op3_init(void);\nvoid dxl_node_op3_loop(void);\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OP3/examples/opencr_op3/opencr_op3.ino",
    "content": "/*\n *  opencr_op3\n *\n *\n *  Created on: 2016. 10. 21.\n *      Author: Baram\n */\n#include \"dxl_node_op3.h\"\n\n\n\nextern void dxl_hw_tx_enable(void);\n\nvoid setup()\n{\n  Serial.begin(115200);\n  Serial.println(\"op3 start\");\n  dxl_node_op3_init();\n}\n\nvoid loop()\n{\n  dxl_node_op3_loop();\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/OpenCR.cpp",
    "content": ""
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/OpenCR.h",
    "content": ""
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/01. Basics/a_Bare_Minimum/a_Bare_Minimum.ino",
    "content": "/* Minimum_Source*/\n\nvoid setup() {\n  // put your setup code here, to run once:\n\n}\n\nvoid loop() {\n  // put your main code here, to run repeatedly: \n\n}\n\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/01. Basics/b_Blink_LED/b_Blink_LED.ino",
    "content": "/*\n * Blink(LED)\n */\n\n/*\n#define BDPIN_LED_USER_1        22\n#define BDPIN_LED_USER_2        23\n#define BDPIN_LED_USER_3        24\n#define BDPIN_LED_USER_4        25\n */\n\nint led_pin = 13;\nint led_pin_user[4] = { BDPIN_LED_USER_1, BDPIN_LED_USER_2, BDPIN_LED_USER_3, BDPIN_LED_USER_4 };\n\nvoid setup() {\n  // Set up the built-in LED pin as an output:\n  pinMode(led_pin, OUTPUT);\n  pinMode(led_pin_user[0], OUTPUT);\n  pinMode(led_pin_user[1], OUTPUT);\n  pinMode(led_pin_user[2], OUTPUT);\n  pinMode(led_pin_user[3], OUTPUT);\n\n  Serial.begin(115200);\n\n}\n\nvoid loop() {\n  int i;\n\n  digitalWrite(led_pin, HIGH);  // set to as HIGH LED is turn-off\n  delay(100);                   // Wait for 0.1 second\n  digitalWrite(led_pin, LOW);   // set to as LOW LED is turn-on\n  delay(100);                   // Wait for 0.1 second\n\n\n  for( i=0; i<4; i++ )\n  {\n    digitalWrite(led_pin_user[i], HIGH);\n    delay(100);\n  }\n  for( i=0; i<4; i++ )\n  {\n    digitalWrite(led_pin_user[i], LOW);\n    delay(100);\n  }\n\n  Serial.println( String(10) );\n}\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/01. Basics/c_Digital_Read_Serial/c_Digital_Read_Serial.ino",
    "content": "/*\n * DigitalReadSerial\n */\n\n/*\n#define BDPIN_DIP_SW_1          26\n#define BDPIN_DIP_SW_2          27\n#define BDPIN_PUSH_SW_1         34\n#define BDPIN_PUSH_SW_2         35\n */\n\nvoid setup(){\n  Serial.begin(115200);\n\n  pinMode(BDPIN_DIP_SW_1, INPUT);\n  pinMode(BDPIN_DIP_SW_2, INPUT);\n  pinMode(BDPIN_PUSH_SW_1, INPUT);\n  pinMode(BDPIN_PUSH_SW_2, INPUT);\n\n}\nvoid loop(){\n  int dip_state;\n  int push_state;\n\n  dip_state  = digitalRead(BDPIN_DIP_SW_1)<<0;\n  dip_state |= digitalRead(BDPIN_DIP_SW_2)<<1;\n\n  push_state  = digitalRead(BDPIN_PUSH_SW_1)<<0;\n  push_state |= digitalRead(BDPIN_PUSH_SW_2)<<1;\n\n  Serial.print(\"dip_state = \");\n  Serial.print(dip_state, BIN);\n\n  Serial.print(\"\\tpush_state = \");\n  Serial.println(push_state, BIN);\n\n\n  delay(100);\n}\n\n\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/01. Basics/d_Analog_Read_Serial/d_Analog_Read_Serial.ino",
    "content": "/*\r\n * AnalogReadSerial\r\n */\r\n\r\n\r\n\r\nvoid setup(){\r\n  Serial.begin(115200);\r\n}\r\n\r\nvoid loop(){\r\n  Serial.print(\"A0 = \");\r\n  Serial.print(analogRead(A0));\r\n  Serial.print(\"\\t\");\r\n\r\n  Serial.print(\"A1 = \");\r\n  Serial.print(analogRead(A1));\r\n  Serial.print(\"\\t\");\r\n\r\n  Serial.print(\"A2 = \");\r\n  Serial.print(analogRead(A2));\r\n  Serial.print(\"\\t\");\r\n\r\n  Serial.print(\"A3 = \");\r\n  Serial.print(analogRead(A3));\r\n  Serial.print(\"\\t\");\r\n\r\n  Serial.print(\"A4 = \");\r\n  Serial.print(analogRead(A4));\r\n  Serial.print(\"\\t\");\r\n\r\n  Serial.print(\"A5 = \");\r\n  Serial.print(analogRead(A5));\r\n  Serial.println(\" \");\r\n\r\n  delay(100);\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/01. Basics/e_Read_Analog_Voltage/e_Read_Analog_Voltage.ino",
    "content": "/*\n * ReadAnalogVoltage\n */\n\nvoid setup() {\n  Serial.begin(115200);\n}\n\nvoid loop() {\n  int adc_value;\n  float vol_value;\n\n  // put your main code here, to run repeatedly:\n\n  adc_value = analogRead(BDPIN_BAT_PWR_ADC);\n\n  Serial.print(\"BAT_PWR = \");\n  Serial.print(adc_value);\n  Serial.print(\"\\t\");\n  vol_value = map(adc_value, 0, 1023, 0, 330*57/10);\n  vol_value = vol_value/100;\n  Serial.print(vol_value);\n  Serial.println(\"V\\t\");\n\n  delay(100);\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/01. Basics/f_Gpio_Write_Speed_Test/f_Gpio_Write_Speed_Test.ino",
    "content": "/* Author: KurtE\n * Modified by : Kei\n */\n\nGPIO_TypeDef *pin0_port;\nuint32_t  pin0_set_mask;\nuint32_t  pin0_clear_mask;\n\nvoid setup() {\n  pinMode (0, OUTPUT);\n  \n  // For register access directly\n  pin0_port = g_Pin2PortMapArray[0].GPIOx_Port;\n  pin0_set_mask = g_Pin2PortMapArray[0].Pin_abstraction;\n  pin0_clear_mask = (uint32_t)g_Pin2PortMapArray[0].Pin_abstraction << 16;\n}\n\nvoid loop() {\n  // Write Method1 : digitalWrite\n  digitalWrite(0, HIGH);\n  digitalWrite(0, LOW);\n  digitalWrite(0, HIGH);\n  digitalWrite(0, LOW);\n  digitalWrite(0, HIGH);\n  digitalWrite(0, LOW);\n\n  // Write Method2 : Access register directly\n  pin0_port->BSRR = pin0_set_mask;\n  pin0_port->BSRR = pin0_clear_mask;\n  pin0_port->BSRR = pin0_set_mask;\n  pin0_port->BSRR = pin0_clear_mask;\n  pin0_port->BSRR = pin0_set_mask;\n  pin0_port->BSRR = pin0_clear_mask;\n\n  // Write Method3 : digitalWriteFast\n  digitalWriteFast(0, HIGH);\n  digitalWriteFast(0, LOW);\n  digitalWriteFast(0, HIGH);\n  digitalWriteFast(0, LOW);\n  digitalWriteFast(0, HIGH);\n  digitalWriteFast(0, LOW);\n\n  delayMicroseconds(100);\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/02. Digital/a_toneMelody/a_toneMelody.ino",
    "content": "/*\n  Melody\n\n Plays a melody\n\n circuit:\n * 8-ohm speaker on digital pin 8\n\n created 21 Jan 2010\n modified 30 Aug 2011\n by Tom Igoe\n\nThis example code is in the public domain.\n\n http://www.arduino.cc/en/Tutorial/Tone\n\n */\n#include \"pitches.h\"\n\n// notes in the melody:\nint melody[] = {\n  NOTE_C4, NOTE_G3, NOTE_G3, NOTE_A3, NOTE_G3, 0, NOTE_B3, NOTE_C4\n};\n\n// note durations: 4 = quarter note, 8 = eighth note, etc.:\nint noteDurations[] = {\n  4, 8, 8, 4, 4, 4, 4, 4\n};\n\nvoid setup() {\n  // iterate over the notes of the melody:\n  for (int thisNote = 0; thisNote < 8; thisNote++) {\n\n    // to calculate the note duration, take one second\n    // divided by the note type.\n    //e.g. quarter note = 1000 / 4, eighth note = 1000/8, etc.\n    int noteDuration = 1000 / noteDurations[thisNote];\n    tone(BDPIN_BUZZER, melody[thisNote], noteDuration);\n\n    // to distinguish the notes, set a minimum time between them.\n    // the note's duration + 30% seems to work well:\n    int pauseBetweenNotes = noteDuration * 1.30;\n    delay(pauseBetweenNotes);\n    // stop the tone playing:\n    noTone(BDPIN_BUZZER);\n  }\n}\n\nvoid loop() {\n  // no need to repeat the melody.\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/02. Digital/a_toneMelody/pitches.h",
    "content": "/*************************************************\n * Public Constants\n *************************************************/\n\n#define NOTE_B0  31\n#define NOTE_C1  33\n#define NOTE_CS1 35\n#define NOTE_D1  37\n#define NOTE_DS1 39\n#define NOTE_E1  41\n#define NOTE_F1  44\n#define NOTE_FS1 46\n#define NOTE_G1  49\n#define NOTE_GS1 52\n#define NOTE_A1  55\n#define NOTE_AS1 58\n#define NOTE_B1  62\n#define NOTE_C2  65\n#define NOTE_CS2 69\n#define NOTE_D2  73\n#define NOTE_DS2 78\n#define NOTE_E2  82\n#define NOTE_F2  87\n#define NOTE_FS2 93\n#define NOTE_G2  98\n#define NOTE_GS2 104\n#define NOTE_A2  110\n#define NOTE_AS2 117\n#define NOTE_B2  123\n#define NOTE_C3  131\n#define NOTE_CS3 139\n#define NOTE_D3  147\n#define NOTE_DS3 156\n#define NOTE_E3  165\n#define NOTE_F3  175\n#define NOTE_FS3 185\n#define NOTE_G3  196\n#define NOTE_GS3 208\n#define NOTE_A3  220\n#define NOTE_AS3 233\n#define NOTE_B3  247\n#define NOTE_C4  262\n#define NOTE_CS4 277\n#define NOTE_D4  294\n#define NOTE_DS4 311\n#define NOTE_E4  330\n#define NOTE_F4  349\n#define NOTE_FS4 370\n#define NOTE_G4  392\n#define NOTE_GS4 415\n#define NOTE_A4  440\n#define NOTE_AS4 466\n#define NOTE_B4  494\n#define NOTE_C5  523\n#define NOTE_CS5 554\n#define NOTE_D5  587\n#define NOTE_DS5 622\n#define NOTE_E5  659\n#define NOTE_F5  698\n#define NOTE_FS5 740\n#define NOTE_G5  784\n#define NOTE_GS5 831\n#define NOTE_A5  880\n#define NOTE_AS5 932\n#define NOTE_B5  988\n#define NOTE_C6  1047\n#define NOTE_CS6 1109\n#define NOTE_D6  1175\n#define NOTE_DS6 1245\n#define NOTE_E6  1319\n#define NOTE_F6  1397\n#define NOTE_FS6 1480\n#define NOTE_G6  1568\n#define NOTE_GS6 1661\n#define NOTE_A6  1760\n#define NOTE_AS6 1865\n#define NOTE_B6  1976\n#define NOTE_C7  2093\n#define NOTE_CS7 2217\n#define NOTE_D7  2349\n#define NOTE_DS7 2489\n#define NOTE_E7  2637\n#define NOTE_F7  2794\n#define NOTE_FS7 2960\n#define NOTE_G7  3136\n#define NOTE_GS7 3322\n#define NOTE_A7  3520\n#define NOTE_AS7 3729\n#define NOTE_B7  3951\n#define NOTE_C8  4186\n#define NOTE_CS8 4435\n#define NOTE_D8  4699\n#define NOTE_DS8 4978\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/02. Digital/b_PWM/b_PWM.ino",
    "content": "/*\n * PWM\n */\n\n/*\n * PWM Pins : 3, 5, 6, 9, 10, 11\n */\n\nint pwm_pins[6] = { 3, 5, 6, 9, 10, 11 };\n\nvoid setup() {\n  // put your setup code here, to run once:\n}\n\nvoid loop() {\n  // put your main code here, to run repeatedly:\n  int i;\n  static uint8_t pwm_out = 0;\n\n  for( i=0; i<6; i++ )\n  {\n    analogWrite(pwm_pins[i], pwm_out++);\n  }\n  delay(100);\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/03. Communication/a_Serial_HelloWorld/a_Serial_HelloWorld.ino",
    "content": "/*\n * Serial_HelloWorld\n*/\nvolatile int nCount=0;\n\nvoid setup() {\n  Serial.begin(115200);\n}\n\nvoid loop() {\n  //print \"Hello World!!\" to PC though USB Virtual COM port\n  Serial.println(\"Hello World!!\");\n  Serial.print(\"nCount : \"); // display nCount variable and increase nCount.\n  Serial.println(nCount++);\n  \n  delay(1000);\n}\n\n\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/04. Interrupt/a_EXIT_Interrupt_Serial/a_EXIT_Interrupt_Serial.ino",
    "content": "/*\n * EXIT_Interrupt_Serial\n*/\n\n/*\n    0: PIN 2,   EXTI_0\n    1: PIN 3,   EXTI_1\n    2: PIN 4,   EXTI_2\n    3: PIN 7,   EXTI_3\n    4: PIN 8,   EXTI_4\n */\n\n\nvoid setup(){\n  Serial.begin(115200);\n\n  pinMode(9, OUTPUT);\n\n  pinMode(2, INPUT_PULLDOWN);\n  pinMode(3, INPUT_PULLDOWN);\n  pinMode(4, INPUT_PULLDOWN);\n  pinMode(7, INPUT_PULLDOWN);\n  pinMode(8, INPUT_PULLDOWN);\n\n  /*It can be choose as CHANGE, RISING or FALLING*/\n  attachInterrupt(0, changeDirection_EXIT_0, RISING);\n  attachInterrupt(1, changeDirection_EXIT_1, RISING);\n  attachInterrupt(2, changeDirection_EXIT_2, RISING);\n  attachInterrupt(3, changeDirection_EXIT_3, RISING);\n  attachInterrupt(4, changeDirection_EXIT_4, RISING);\n}\n\nvoid changeDirection_EXIT_0(void){\n  Serial.println(\"EXIT_Interrupt! 0\");\n}\n\nvoid changeDirection_EXIT_1(void){\n  Serial.println(\"EXIT_Interrupt! 1\");\n}\n\nvoid changeDirection_EXIT_2(void){\n  Serial.println(\"EXIT_Interrupt! 2\");\n}\n\nvoid changeDirection_EXIT_3(void){\n  Serial.println(\"EXIT_Interrupt! 3\");\n}\n\nvoid changeDirection_EXIT_4(void){\n  Serial.println(\"EXIT_Interrupt! 4\");\n}\n\nvoid loop(){\n  digitalWrite(9, HIGH);\n  delay(500);\n  digitalWrite(9, LOW);\n  delay(500);\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/04. Interrupt/d_Timer_Interrupt_LED/d_Timer_Interrupt_LED.ino",
    "content": "#define BOARD_LED_PIN 13\n#define LED_RATE 1000000                // in microseconds; should give 1Hz toggles\n\nHardwareTimer Timer(TIMER_CH1);\n\nvoid setup() {\n  pinMode(BOARD_LED_PIN, OUTPUT);\n\n  Timer.stop();\n  Timer.setPeriod(LED_RATE);           // in microseconds\n  Timer.attachInterrupt(handler_led);\n  Timer.start();\n}\n\nvoid loop() {\n  // Nothing! It's all in the handler_led() interrupt:\n}\n\nvoid handler_led(void) {\n  static uint8_t flag = 0;\n\n  digitalWrite(BOARD_LED_PIN, flag);\n  flag ^= 1;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/05. Sensors/OLLO_COLOR_Read/OLLO_COLOR_Read.ino",
    "content": "// OLLO Color Sensor(CS-10) example\n// \n// Connect Color Sensor Module(CS-10) to OLLO port 1 in the OpenCR.\n// \n// You can buy Color Sensor in ROBOTIS-SHOP\n// http://www.robotis-shop-en.com/shop/step1.php?number=750&b_code=B20070914051413&c_code=C20100528062452\n// You can also find all information \n// http://support.robotis.com/\n//                \n// This example is tested with the following device\n// Controller : OpenCR\n// Sensor : CS-10\n// \n// Created : 13 July 2023\n// by YKW. ROBOTIS Co., LTD.\n\n#include <OLLO.h>\nOLLO myOLLO;\n\nvoid setup() {\n  myOLLO.begin(1, COLOR_SENSOR); // OLLO Color Module must be connected at port 1.\n  Serial.begin(115200);\n}\n\nvoid loop() {\n  int colorValue = myOLLO.read(1, COLOR_SENSOR);\n\n  Serial.print(\"COLOR Sensor Read = \");\n  switch (colorValue) {\n    case 0:\n      Serial.println(\"Unknown color\");\n      break;\n    case 1:\n      Serial.println(\"White\");\n      break;\n    case 2:\n      Serial.println(\"Black\");\n      break;\n    case 3:\n      Serial.println(\"Red\");\n      break;\n    case 4:\n      Serial.println(\"Green\");\n      break;\n    case 5:\n      Serial.println(\"Blue\");\n      break;\n    case 6:\n      Serial.println(\"Yellow\");\n      break;\n    default:\n      Serial.println(\"Unknown color\");\n      break;\n  }\n\n  delay(100);\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/05. Sensors/OLLO_DMS_Read/OLLO_DMS_Read.ino",
    "content": "/* OLLO DMS Sensor Read \n \n connect DMS Sensor Module(DMS-80) to port 1.\n \n You can buy DMS Sensor DYNAMIXEL in ROBOTIS-SHOP\n http://www.robotis-shop-en.com/shop/step1.php?number=834&b_code=B20070914051413&c_code=C20100528062452\n You can also find all information \n http://support.robotis.com/\n \n                 Compatibility\n CM900                  X\n OpenCM9.04             O\n \n created 16 Nov 2012\n by ROBOTIS CO,.LTD.\n */\n\n#include <OLLO.h>\nOLLO myOLLO;\n\nvoid setup(){\n  myOLLO.begin(1);//DMS Module must be connected at port 1.\n}\nvoid loop(){\n  Serial.print(\"DMS Sensor ADC Value = \");\n  Serial.println(myOLLO.read(1)); //read ADC value from OLLO port 1\n  delay(60);\n}\n\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/05. Sensors/OLLO_IR_Read/OLLO_IR_Read.ino",
    "content": "/*\n OLLO IR Sensor Read example\n \n connect IR Sensor Module(OIS-10) to port 1.\n \n You can buy IR Sensor DYNAMIXEL in ROBOTIS-SHOP\n http://www.robotis-shop-en.com/shop/step1.php?number=750&b_code=B20070914051413&c_code=C20100528062452\n You can also find all information \n http://support.robotis.com/\n                \n                  Compatibility\n CM900                  X\n OpenCM9.04             O\n \n created 16 Nov 2012\n by ROBOTIS CO,.LTD.\n */\n\n#include <OLLO.h>\nOLLO myOLLO;\n\nvoid setup(){\n  Serial.begin(115200);\n  myOLLO.begin(1, IR_SENSOR);//IR Module must be connected at port 1.\n}\nvoid loop(){\n  Serial.print(\"IR Sensor ADC = \");\n  Serial.println(myOLLO.read(1, IR_SENSOR)); //read ADC value from OLLO port 1  \n  delay(60);\n}\n\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/05. Sensors/OLLO_TOUCH_Read/OLLO_TOUCH_Read.ino",
    "content": "/* OLLO Touch sensor interrupt\n \n connect Touch Sensor Module to port 2.\n \n  You can buy Touch Sensor DYNAMIXEL in ROBOTIS-SHOP\n http://www.robotis-shop-en.com/shop/step1.php?number=750&b_code=B20070914051413&c_code=C20100528062452\n //위 링크 수정\n \n You can also find all information \n http://support.robotis.com/\n \n                  Compatibility\n CM900                  X\n OpenCM9.04             O\n \n created 16 Nov 2012\n by ROBOTIS CO,.LTD.\n */\n\n#include <OLLO.h>\nOLLO myOLLO;\n\nvoid setup(){\n  myOLLO.begin(1,TOUCH_SENSOR);//OLLO Touch Module must be connected at port 2.\n  \n}\nvoid loop(){\n  Serial.print(\"Touch Read = \");\n  Serial.println(myOLLO.read(1, TOUCH_SENSOR));\n  delay(100); \n}\n\n\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/05. Sensors/OLLO_TPS_READ/OLLO_TPS_READ.ino",
    "content": "/* OLLO TPS Sensor Read\n \n connect Temperature Sensor to OLLO ports \n\n                 Compatibility\n CM900                  X\n OpenCM9.04             O\n \n created 16 Nov 2012\n by ROBOTIS CO,.LTD.\n */\n\n#include <OLLO.h>\nOLLO myOLLO;\n\n#define YOUR_OLLO_PORT 3\n\nvoid setup(){\n  myOLLO.begin(YOUR_OLLO_PORT);// A Module needs to be connected to proper port (PORT 1 to 4)\n}\nvoid loop(){\n  Serial.print(\"RAW Temperature = \");\n  Serial.print(myOLLO.read(YOUR_OLLO_PORT)); //read ADC value from YOUR_OLLO-PORT\n  Serial.print(\"\\t Converted Temperature = \");\n  Serial.println(myOLLO.read(YOUR_OLLO_PORT, TEMPERATURE_SENSOR)); //read ADC value from YOUR_OLLO-PORT\n  delay(100);\n}\n\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/06. RC100/RC100/RC100.ino",
    "content": "/*******************************************************************************\r\n* Copyright (c) 2016, ROBOTIS CO., LTD.\r\n* All rights reserved.\r\n*\r\n* Redistribution and use in source and binary forms, with or without\r\n* modification, are permitted provided that the following conditions are met:\r\n*\r\n* * Redistributions of source code must retain the above copyright notice, this\r\n*   list of conditions and the following disclaimer.\r\n*\r\n* * Redistributions in binary form must reproduce the above copyright notice,\r\n*   this list of conditions and the following disclaimer in the documentation\r\n*   and/or other materials provided with the distribution.\r\n*\r\n* * Neither the name of ROBOTIS nor the names of its\r\n*   contributors may be used to endorse or promote products derived from\r\n*   this software without specific prior written permission.\r\n*\r\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n*******************************************************************************/\r\n\r\n/* Author: Taehoon Lim (Darby), Ashe Kim */\r\n\r\n#include <RC100.h>\r\n#include <DynamixelSDK.h>\r\n\r\n#define LEFT_DXL  1\r\n#define RIGHT_DXL 2\r\n\r\n#define BAUDRATE 1000000\r\n#define DEVICENAME \"\"\r\n#define PROTOCOL_VERSION 2.0\r\n\r\n#define ADDR_TORQUE_ENABLE 64\r\n#define ADDR_GOAL_VELOCITY 104\r\n\r\n#define LEN_TORQUE_ENABLE 1\r\n#define LEN_GOAL_VELOCITY 4\r\n\r\n#define ON  1\r\n#define OFF 0\r\n\r\n#define VELOCITY 10\r\n\r\ndynamixel::PortHandler *portHandler;\r\ndynamixel::PacketHandler *packetHandler;\r\n\r\ndynamixel::GroupSyncWrite *groupSyncWrite;\r\n\r\nbool dxl_addparam_result = false;\r\nint dxl_comm_result = COMM_TX_FAIL;\r\nuint8_t dxl_error = 0;\r\n\r\nint vel[2] = {0, 0};\r\nint const_vel = 200;\r\n\r\nRC100 Controller;\r\nint RcvData = 0;\r\n\r\nvoid setup() \r\n{\r\n  Serial.begin(57600);\r\n\r\n  Controller.begin(1);\r\n\r\n  portHandler = dynamixel::PortHandler::getPortHandler(DEVICENAME);\r\n  packetHandler = dynamixel::PacketHandler::getPacketHandler(PROTOCOL_VERSION);\r\n  groupSyncWrite = new dynamixel::GroupSyncWrite(portHandler, packetHandler, ADDR_GOAL_VELOCITY, LEN_GOAL_VELOCITY);\r\n\r\n  portHandler -> openPort();\r\n  portHandler->setBaudRate(BAUDRATE);\r\n\r\n  dxl_comm_result = packetHandler->write1ByteTxRx(portHandler, LEFT_DXL, ADDR_TORQUE_ENABLE, ON, &dxl_error);\r\n  packetHandler->getTxRxResult(dxl_comm_result);\r\n\r\n  dxl_comm_result = packetHandler->write1ByteTxRx(portHandler, RIGHT_DXL, ADDR_TORQUE_ENABLE, ON, &dxl_error);\r\n  packetHandler->getTxRxResult(dxl_comm_result);\r\n}\r\n\r\nvoid loop() \r\n{\r\n  if (Controller.available())\r\n  {\r\n    RcvData = Controller.readData();\r\n    Serial.print(\"RcvData = \");\r\n    Serial.print(RcvData);\r\n    Serial.print(\" LEFT_VEL = \");\r\n    Serial.print(vel[0]);\r\n    Serial.print(\" RIGHT_VEL = \");\r\n    Serial.println(vel[1]);\r\n\r\n    if (RcvData & RC100_BTN_U)\r\n    {\r\n      vel[0] += VELOCITY;\r\n      vel[1] -= VELOCITY;\r\n    }\r\n    else if (RcvData & RC100_BTN_D)\r\n    {\r\n      vel[0] -= VELOCITY;\r\n      vel[1] += VELOCITY;\r\n    }\r\n    else if (RcvData & RC100_BTN_L)\r\n    {\r\n      vel[0] -= VELOCITY;\r\n      vel[1] -= VELOCITY;\r\n    }\r\n    else if (RcvData & RC100_BTN_R)\r\n    {\r\n      vel[0] += VELOCITY;\r\n      vel[1] += VELOCITY;\r\n    }\r\n    else if (RcvData & RC100_BTN_1)\r\n    {\r\n      vel[0] = (const_vel + 10);\r\n      vel[1] = (const_vel + 10);\r\n    }\r\n    else if (RcvData & RC100_BTN_2)\r\n    {\r\n      vel[0] = (const_vel - 10);\r\n      vel[1] = (const_vel - 10);\r\n    }\r\n    else if (RcvData & RC100_BTN_3)\r\n    {\r\n      vel[0] = -const_vel;\r\n      vel[1] = const_vel;\r\n    }\r\n    else if (RcvData & RC100_BTN_4)\r\n    {\r\n      vel[0] = const_vel;\r\n      vel[1] = -const_vel;\r\n    }\r\n    else if (RcvData & RC100_BTN_5)\r\n    {\r\n      vel[0] = 0;\r\n      vel[1] = 0;\r\n    }\r\n\r\n    controlMotor( vel[0], vel[1]);\r\n    return;\r\n  }\r\n}\r\n\r\nvoid controlMotor( int64_t left_wheel_value, int64_t right_wheel_value)\r\n{\r\n  //bool dxl_addparam_result;\r\n  //int dxl_comm_result;\r\n\r\n  groupSyncWrite->addParam(LEFT_DXL, (uint8_t*)&left_wheel_value);\r\n  groupSyncWrite->addParam(RIGHT_DXL, (uint8_t*)&right_wheel_value);\r\n\r\n  groupSyncWrite->txPacket();\r\n\r\n  groupSyncWrite->clearParam();\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/07. DynamixelSDK/dxl_monitor/dxl_monitor.ino",
    "content": "#include <DynamixelSDK.h>\r\n#include <stdarg.h>\r\n\r\n\r\n// Protocol version\r\n#define PROTOCOL_VERSION1               1.0                 // See which protocol version is used in the Dynamixel\r\n#define PROTOCOL_VERSION2               2.0\r\n\r\n// Default setting\r\n#define DEVICENAME                      \"OpenCR_DXL_Port\"   // This definition only has a symbolic meaning and does not affect to any functionality\r\n\r\n\r\n#define CMD_SERIAL    Serial                                // USB Serial\r\n//#define CMD_SERIAL    Serial2                               // Bluetooth Serial\r\n\r\n\r\n\r\n\r\n\r\nvoid setup()\r\n{\r\n  CMD_SERIAL.begin(57600);\r\n}\r\n\r\nvoid loop()\r\n{\r\n  dxl_monitor_main();\r\n}\r\n\r\n\r\nstatic void _printf(char *fmt, ... )\r\n{\r\n  char buf[128]; // resulting string limited to 128 chars\r\n  char buf_out[128];\r\n  va_list args;\r\n  size_t i;\r\n  int i_out;\r\n\r\n\r\n  va_start (args, fmt );\r\n  vsnprintf(buf, 128, fmt, args);\r\n  va_end (args);\r\n\r\n  i_out = 0;\r\n  for( i=0; i<strlen(buf); i++ )\r\n  {\r\n    if( buf[i] == '\\n' )\r\n    {\r\n      buf_out[i_out++] = '\\r';\r\n      buf_out[i_out++] = '\\n';\r\n    }\r\n    else\r\n    {\r\n      buf_out[i_out++] = buf[i];\r\n    }\r\n  }\r\n  buf_out[i_out] = 0;\r\n\r\n  CMD_SERIAL.print(buf_out);\r\n}\r\n\r\nstatic void _fprintf(FILE * stream, char *fmt, ... )\r\n{\r\n  UNUSED(stream);\r\n\r\n  char buf[128]; // resulting string limited to 128 chars\r\n  char buf_out[128];\r\n  va_list args;\r\n  size_t i;\r\n  int i_out;\r\n\r\n  va_start (args, fmt );\r\n  vsnprintf(buf, 128, fmt, args);\r\n  va_end (args);\r\n\r\n  i_out = 0;\r\n  for( i=0; i<strlen(buf); i++ )\r\n  {\r\n    if( buf[i] == '\\n' )\r\n    {\r\n      buf_out[i_out++] = '\\r';\r\n      buf_out[i_out++] = '\\n';\r\n    }\r\n    else\r\n    {\r\n      buf_out[i_out++] = buf[i];\r\n    }\r\n  }\r\n  buf_out[i_out] = 0;\r\n\r\n  CMD_SERIAL.print(buf_out);\r\n}\r\n\r\nint getch()\r\n{\r\n  while(1)\r\n  {\r\n    if( CMD_SERIAL.available() > 0 )\r\n    {\r\n      break;\r\n    }\r\n  }\r\n\r\n  return CMD_SERIAL.read();\r\n}\r\n\r\nint kbhit(void)\r\n{\r\n  return CMD_SERIAL.available();\r\n}\r\n\r\nchar * fgets ( char * str, int num, FILE * stream )\r\n{\r\n  UNUSED(stream);\r\n\r\n  char ch;\r\n  int  index;\r\n\r\n  index = 0;\r\n\r\n  while(1)\r\n  {\r\n    if( CMD_SERIAL.available() > 0 )\r\n    {\r\n      ch = CMD_SERIAL.read();\r\n\r\n      CMD_SERIAL.write(ch);\r\n\r\n      if( index < num-1 && ch != 0x0D )\r\n      {\r\n        if ( ch != 0X0A )  // Ignore line feeds\r\n        {\r\n          str[index++] = ch;\r\n        }\r\n      }\r\n      if( ch == 0x0D)\r\n      {\r\n        str[index] = 0;\r\n        break;\r\n      }\r\n    }\r\n  }\r\n\r\n  return str;\r\n}\r\n\r\nvoid usage(char *progname)\r\n{\r\n  _printf((char*) \"-----------------------------------------------------------------------\\n\");\r\n  _printf((char*) \"Usage: %s\\n\");\r\n  _printf((char*) \" [-h | --help]........: display this help\\n\");\r\n  _printf((char*) \"[-d | --device]......: port to open\\n\", progname);\r\n  _printf((char*) \"-----------------------------------------------------------------------\\n\");\r\n}\r\n\r\nvoid help()\r\n{\r\n  _printf((char*) \"\\n\");\r\n  _printf((char*) \"                    .----------------------------.\\n\");\r\n  _printf((char*) \"                    |  DXL Monitor Command List  |\\n\");\r\n  _printf((char*) \"                    '----------------------------'\\n\");\r\n  _printf((char*) \" =========================== Common Commands ===========================\\n\");\r\n  _printf((char*) \" \\n\");\r\n  _printf((char*) \" help|h|?                    :Displays help information\\n\");\r\n  _printf((char*) \" baud [BAUD_RATE]            :Changes baudrate to [BAUD_RATE] \\n\");\r\n  _printf((char*) \"                               ex) baud 2400 (2400 bps) \\n\");\r\n  _printf((char*) \"                               ex) baud 1000000 (1 Mbps)  \\n\");\r\n  _printf((char*) \" exit                        :Exit this program\\n\");\r\n  _printf((char*) \" scan                        :Outputs the current status of all Dynamixels\\n\");\r\n  _printf((char*) \" ping [ID] [ID] ...          :Outputs the current status of [ID]s \\n\");\r\n  _printf((char*) \" bp                          :Broadcast ping (Dynamixel Protocol 2.0 only)\\n\");\r\n  _printf((char*) \" \\n\");\r\n  _printf((char*) \" ==================== Commands for Dynamixel Protocol 1.0 ====================\\n\");\r\n  _printf((char*) \" \\n\");\r\n  _printf((char*) \" wrb1|w1 [ID] [ADDR] [VALUE] :Write byte [VALUE] to [ADDR] of [ID]\\n\");\r\n  _printf((char*) \" wrw1 [ID] [ADDR] [VALUE]    :Write word [VALUE] to [ADDR] of [ID]\\n\");\r\n  _printf((char*) \" rdb1 [ID] [ADDR]            :Read byte value from [ADDR] of [ID]\\n\");\r\n  _printf((char*) \" rdw1 [ID] [ADDR]            :Read word value from [ADDR] of [ID]\\n\");\r\n  _printf((char*) \" r1 [ID] [ADDR] [LENGTH]     :Dumps the control table of [ID]\\n\");\r\n  _printf((char*) \"                               ([LENGTH] bytes from [ADDR])\\n\");\r\n  _printf((char*) \" reset1|rst1 [ID]            :Factory reset the Dynamixel of [ID]\\n\");\r\n  _printf((char*) \" \\n\");\r\n  _printf((char*) \" ==================== Commands for Dynamixel Protocol 2.0 ====================\\n\");\r\n  _printf((char*) \" \\n\");\r\n  _printf((char*) \" wrb2|w2 [ID] [ADDR] [VALUE] :Write byte [VALUE] to [ADDR] of [ID]\\n\");\r\n  _printf((char*) \" wrw2 [ID] [ADDR] [VALUE]    :Write word [VALUE] to [ADDR] of [ID]\\n\");\r\n  _printf((char*) \" wrd2 [ID] [ADDR] [VALUE]    :Write dword [VALUE] to [ADDR] of [ID]\\n\");\r\n  _printf((char*) \" rdb2 [ID] [ADDR]            :Read byte value from [ADDR] of [ID]\\n\");\r\n  _printf((char*) \" rdw2 [ID] [ADDR]            :Read word value from [ADDR] of [ID]\\n\");\r\n  _printf((char*) \" rdd2 [ID] [ADDR]            :Read dword value from [ADDR] of [ID]\\n\");\r\n  _printf((char*) \" r2 [ID] [ADDR] [LENGTH]     :Dumps the control table of [ID]\\n\");\r\n  _printf((char*) \"                               ([LENGTH] bytes from [ADDR])\\n\");\r\n  _printf((char*) \" reboot2|rbt2 [ID]           :reboot the Dynamixel of [ID]\\n\");\r\n  _printf((char*) \" reset2|rst2 [ID] [OPTION]   :Factory reset the Dynamixel of [ID]\\n\");\r\n  _printf((char*) \"                               OPTION: 255(All), 1(Except ID), 2(Except ID&Baud)\\n\");\r\n\r\n  _printf((char*) \"\\n\");\r\n}\r\n\r\nvoid scan(dynamixel::PortHandler *portHandler, dynamixel::PacketHandler *packetHandler1, dynamixel::PacketHandler *packetHandler2)\r\n{\r\n  uint8_t dxl_error;\r\n  uint16_t dxl_model_num;\r\n\r\n  _fprintf(stderr, (char*) \"\\n\");\r\n  _fprintf(stderr, (char*) \"Scan Dynamixel Using Protocol 1.0\\n\");\r\n  for (int id = 1; id < 253; id++)\r\n  {\r\n    if (packetHandler1-> ping(portHandler, id, &dxl_model_num, &dxl_error)== COMM_SUCCESS)\r\n    {\r\n      _fprintf(stderr, (char*) \"\\n                                          ... SUCCESS \\r\");\r\n      _fprintf(stderr, (char*) \" [ID:%.3d] Model No : %.5d \\n\", id, dxl_model_num);\r\n    }\r\n    else\r\n        _fprintf(stderr, (char*) \".\");\r\n\r\n    if (kbhit())\r\n    {\r\n        char c = getch();\r\n        if (c == 0x1b)\r\n        break;\r\n    }\r\n  }\r\n  _fprintf(stderr, (char*) \"\\n\\n\");\r\n\r\n  _fprintf(stderr, (char*) \"Scan Dynamixel Using Protocol 2.0\\n\");\r\n  for (int id = 1; id < 253; id++)\r\n  {\r\n    if (packetHandler2-> ping(portHandler, id, &dxl_model_num, &dxl_error)== COMM_SUCCESS)\r\n    {\r\n      _fprintf(stderr, (char*) \"\\n                                          ... SUCCESS \\r\");\r\n      _fprintf(stderr, (char*) \" [ID:%.3d] Model No : %.5d \\n\", id, dxl_model_num);\r\n    }\r\n    else\r\n    {\r\n      _fprintf(stderr, (char*) \".\");\r\n    }\r\n\r\n    if (kbhit())\r\n    {\r\n      char c = getch();\r\n      if (c == 0x1b) break;\r\n    }\r\n  }\r\n  _fprintf(stderr, (char*) \"\\n\\n\");\r\n}\r\n\r\nvoid write(dynamixel::PortHandler *portHandler, dynamixel::PacketHandler *packetHandler, uint8_t id, uint16_t addr, uint16_t length, uint32_t value)\r\n{\r\n  uint8_t dxl_error = 0;\r\n  int dxl_comm_result = COMM_TX_FAIL;\r\n\r\n  if (length == 1)\r\n  {\r\n    dxl_comm_result = packetHandler->write1ByteTxRx(portHandler, id, addr, (uint8_t)value, &dxl_error);\r\n  }\r\n  else if (length == 2)\r\n  {\r\n    dxl_comm_result = packetHandler->write2ByteTxRx(portHandler, id, addr, (uint16_t)value, &dxl_error);\r\n  }\r\n  else if (length == 4)\r\n  {\r\n    dxl_comm_result = packetHandler->write4ByteTxRx(portHandler, id, addr, (uint32_t)value, &dxl_error);\r\n  }\r\n\r\n  if (dxl_comm_result == COMM_SUCCESS)\r\n  {\r\n    if (dxl_error != 0) Serial.print(packetHandler->getRxPacketError(dxl_error));\r\n    _fprintf(stderr, (char*) \"\\n Success to write\\n\\n\");\r\n  }\r\n  else\r\n  {\r\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n    _fprintf(stderr, (char*) \"\\n Fail to write! \\n\\n\");\r\n  }\r\n}\r\n\r\nvoid read(dynamixel::PortHandler *portHandler, dynamixel::PacketHandler *packetHandler, uint8_t id, uint16_t addr, uint16_t length)\r\n{\r\n  uint8_t dxl_error = 0;\r\n  int     dxl_comm_result = COMM_TX_FAIL;\r\n\r\n  int8_t  value8    = 0;\r\n  int16_t value16   = 0;\r\n  int32_t value32   = 0;\r\n\r\n\r\n  if (length == 1)\r\n  {\r\n    dxl_comm_result = packetHandler->read1ByteTxRx(portHandler, id, addr, (uint8_t*)&value8, &dxl_error);\r\n  }\r\n  else if (length == 2)\r\n  {\r\n    dxl_comm_result = packetHandler->read2ByteTxRx(portHandler, id, addr, (uint16_t*)&value16, &dxl_error);\r\n  }\r\n  else if (length == 4)\r\n  {\r\n    dxl_comm_result = packetHandler->read4ByteTxRx(portHandler, id, addr, (uint32_t*)&value32, &dxl_error);\r\n  }\r\n\r\n  if (dxl_comm_result == COMM_SUCCESS)\r\n  {\r\n    if (dxl_error != 0) Serial.print(packetHandler->getRxPacketError(dxl_error));\r\n\r\n    if (length == 1)\r\n    {\r\n      _fprintf(stderr, (char*) \"\\n READ VALUE : (UNSIGNED) %u , (SIGNED) %d \\n\\n\", (uint8_t)value8, value8);\r\n    }\r\n    else if (length == 2)\r\n    {\r\n      _fprintf(stderr, (char*) \"\\n READ VALUE : (UNSIGNED) %u , (SIGNED) %d \\n\\n\", (uint16_t)value16, value16);\r\n    }\r\n    else if (length == 4)\r\n    {\r\n      _fprintf(stderr, (char*) \"\\n READ VALUE : (UNSIGNED) %u , (SIGNED) %d \\n\\n\", (uint32_t)value32, value32);\r\n    }\r\n  }\r\n  else\r\n  {\r\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n    _fprintf(stderr, (char*) \"\\n Fail to read! \\n\\n\");\r\n  }\r\n}\r\n\r\nvoid dump(dynamixel::PortHandler *portHandler, dynamixel::PacketHandler *packetHandler, uint8_t id, uint16_t addr, uint16_t len)\r\n{\r\n  uint8_t  dxl_error       = 0;\r\n  int      dxl_comm_result = COMM_TX_FAIL;\r\n  uint8_t *data            = (uint8_t*)calloc(len, sizeof(uint8_t));\r\n\r\n  dxl_comm_result = packetHandler->readTxRx(portHandler, id, addr, len, data, &dxl_error);\r\n  if (dxl_comm_result == COMM_SUCCESS)\r\n  {\r\n    if (dxl_error != 0)\r\n      Serial.print(packetHandler->getRxPacketError(dxl_error));\r\n\r\n    if (id != BROADCAST_ID)\r\n    {\r\n      _fprintf(stderr, (char*) \"\\n\");\r\n      for (int i = addr; i < addr+len; i++)\r\n      _fprintf(stderr, (char*) \"ADDR %.3d [0x%.4X] :     %.3d [0x%.2X] \\n\", i, i, data[i-addr], data[i-addr]);\r\n      _fprintf(stderr, (char*) \"\\n\");\r\n    }\r\n  }\r\n  else\r\n  {\r\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n    _fprintf(stderr, (char*) \"\\n Fail to read! \\n\\n\");\r\n  }\r\n\r\n  free(data);\r\n}\r\n\r\nvoid dxl_monitor_main(void)\r\n{\r\n  // Initialize Packethandler1 instance\r\n  dynamixel::PacketHandler *packetHandler1 = dynamixel::PacketHandler::getPacketHandler(PROTOCOL_VERSION1);\r\n\r\n  // Initialize Packethandler2 instance\r\n  dynamixel::PacketHandler *packetHandler2 = dynamixel::PacketHandler::getPacketHandler(PROTOCOL_VERSION2);\r\n\r\n  _fprintf(stderr, (char*) \"\\n***********************************************************************\\n\");\r\n  _fprintf(stderr, (char*)   \"*                            DXL Monitor                              *\\n\");\r\n  _fprintf(stderr, (char*)   \"***********************************************************************\\n\\n\");\r\n\r\n  char *dev_name = (char*)DEVICENAME;\r\n\r\n  // Initialize PortHandler instance\r\n  // Set the port path\r\n  // Get methods and members of PortHandlerLinux or PortHandlerWindows\r\n  dynamixel::PortHandler *portHandler = dynamixel::PortHandler::getPortHandler(dev_name);\r\n\r\n\r\n  // Open port\r\n  if (portHandler->openPort())\r\n  {\r\n    _printf((char*) \"Succeeded to open the port!\\r\\n\");\r\n    _printf((char*) \" - Device Name : %s\\r\\n\", dev_name);\r\n    _printf((char*) \" - Baudrate    : %d\\r\\n\", portHandler->getBaudRate());\r\n  }\r\n  else\r\n  {\r\n    _printf((char*) \"Failed to open the port! [%s]\\n\", dev_name);\r\n  }\r\n\r\n  char    input[128];\r\n  char    cmd[80];\r\n  char    param[20][30];\r\n  int     num_param;\r\n  char    *token;\r\n  uint8_t dxl_error;\r\n\r\n  while(1)\r\n  {\r\n    _printf((char*) \"[CMD] \");\r\n    fgets(input, sizeof(input), stdin);\r\n    char *p;\r\n    if ((p = strchr(input, '\\n'))!= NULL) *p = '\\0';\r\n\r\n    if (strlen(input) == 0) continue;\r\n\r\n    token = strtok(input, \" \");\r\n\r\n    if (token == 0) continue;\r\n\r\n    strcpy(cmd, token);\r\n    token = strtok(0, \" \");\r\n    num_param = 0;\r\n    while(token != 0)\r\n    {\r\n      strcpy(param[num_param++], token);\r\n      token = strtok(0, \" \");\r\n    }\r\n\r\n    if (strcmp(cmd, \"help\") == 0 || strcmp(cmd, \"h\") == 0 || strcmp(cmd, \"?\") == 0)\r\n    {\r\n      help();\r\n    }\r\n    else if (strcmp(cmd, \"baud\") == 0)\r\n    {\r\n      if (num_param == 1)\r\n      {\r\n        if (portHandler->setBaudRate(atoi(param[0])) == false)\r\n          _fprintf(stderr, (char*) \" Failed to change baudrate! \\n\");\r\n        else\r\n          _fprintf(stderr, (char*) \" Success to change baudrate! [ BAUD RATE: %d ]\\n\", atoi(param[0]));\r\n      }\r\n      else\r\n      {\r\n        _fprintf(stderr, (char*) \" Invalid parameters! \\n\");\r\n        continue;\r\n      }\r\n    }\r\n    else if (strcmp(cmd, \"exit\") == 0)\r\n    {\r\n      portHandler->closePort();\r\n      return;\r\n    }\r\n    else if (strcmp(cmd, \"scan\") == 0)\r\n    {\r\n      scan(portHandler, packetHandler1, packetHandler2);\r\n    }\r\n    else if (strcmp(cmd, \"ping\") == 0)\r\n    {\r\n      uint16_t dxl_model_num;\r\n\r\n      if (num_param == 0)\r\n      {\r\n        _fprintf(stderr, (char*) \" Invalid parameters! \\n\");\r\n        continue;\r\n      }\r\n\r\n      _fprintf(stderr, (char*) \"\\n\");\r\n      _fprintf(stderr, (char*) \"ping Using Protocol 1.0\\n\");\r\n      for (int i = 0; i < num_param; i++)\r\n      {\r\n        if (packetHandler1->ping(portHandler, atoi(param[i]), &dxl_model_num, &dxl_error) == COMM_SUCCESS)\r\n        {\r\n          _fprintf(stderr, (char*) \"\\n                                          ... SUCCESS \\r\");\r\n          _fprintf(stderr, (char*) \" [ID:%.3d] Model No : %.5d \\n\", atoi(param[i]), dxl_model_num);\r\n        }\r\n        else\r\n        {\r\n          _fprintf(stderr, (char*) \"\\n                                          ... FAIL \\r\");\r\n          _fprintf(stderr, (char*) \" [ID:%.3d] \\n\", atoi(param[i]));\r\n        }\r\n      }\r\n      _fprintf(stderr, (char*) \"\\n\");\r\n\r\n      _fprintf(stderr, (char*) \"\\n\");\r\n      _fprintf(stderr, (char*) \"ping Using Protocol 2.0\\n\");\r\n      for (int i = 0; i < num_param; i++)\r\n      {\r\n        if (packetHandler2->ping(portHandler, atoi(param[i]), &dxl_model_num, &dxl_error) == COMM_SUCCESS)\r\n        {\r\n          _fprintf(stderr, (char*) \"\\n                                          ... SUCCESS \\r\");\r\n          _fprintf(stderr, (char*) \" [ID:%.3d] Model No : %.5d \\n\", atoi(param[i]), dxl_model_num);\r\n        }\r\n        else\r\n        {\r\n          _fprintf(stderr, (char*) \"\\n                                          ... FAIL \\r\");\r\n          _fprintf(stderr, (char*) \" [ID:%.3d] \\n\", atoi(param[i]));\r\n        }\r\n      }\r\n      _fprintf(stderr, (char*) \"\\n\");\r\n    }\r\n    else if (strcmp(cmd, \"bp\") == 0)\r\n    {\r\n      if (num_param == 0)\r\n      {\r\n        std::vector<unsigned char> vec;\r\n\r\n        int dxl_comm_result = packetHandler2->broadcastPing(portHandler, vec);\r\n        if (dxl_comm_result != COMM_SUCCESS) _fprintf(stderr, (char*) \"%s\\n\", packetHandler2->getTxRxResult(dxl_comm_result));\r\n\r\n        for (unsigned int i = 0; i < vec.size(); i++)\r\n        {\r\n          _fprintf(stderr, (char*) \"\\n                                          ... SUCCESS \\r\");\r\n          _fprintf(stderr, (char*) \" [ID:%.3d] \\n\", vec.at(i));\r\n        }\r\n        _printf((char*) \"\\n\");\r\n      }\r\n      else\r\n      {\r\n        _fprintf(stderr, (char*) \" Invalid parameters! \\n\");\r\n      }\r\n    }\r\n    else if (strcmp(cmd, \"wrb1\") == 0 || strcmp(cmd, \"w1\") == 0)\r\n    {\r\n      if (num_param == 3)\r\n      {\r\n        write(portHandler, packetHandler1, atoi(param[0]), atoi(param[1]), 1, atoi(param[2]));\r\n      }\r\n      else\r\n      {\r\n        _fprintf(stderr, (char*) \" Invalid parameters! \\n\");\r\n      }\r\n    }\r\n    else if (strcmp(cmd, \"wrb2\") == 0 || strcmp(cmd, \"w2\") == 0)\r\n    {\r\n      if (num_param == 3)\r\n      {\r\n        write(portHandler, packetHandler2, atoi(param[0]), atoi(param[1]), 1, atoi(param[2]));\r\n      }\r\n      else\r\n      {\r\n        _fprintf(stderr, (char*) \" Invalid parameters! \\n\");\r\n      }\r\n    }\r\n    else if (strcmp(cmd, \"wrw1\") == 0)\r\n    {\r\n      if (num_param == 3)\r\n      {\r\n        write(portHandler, packetHandler1, atoi(param[0]), atoi(param[1]), 2, atoi(param[2]));\r\n      }\r\n      else\r\n      {\r\n        _fprintf(stderr, (char*) \" Invalid parameters! \\n\");\r\n      }\r\n    }\r\n    else if (strcmp(cmd, \"wrw2\") == 0)\r\n    {\r\n      if (num_param == 3)\r\n      {\r\n        write(portHandler, packetHandler2, atoi(param[0]), atoi(param[1]), 2, atoi(param[2]));\r\n      }\r\n      else\r\n      {\r\n        _fprintf(stderr, (char*) \" Invalid parameters! \\n\");\r\n      }\r\n    }\r\n    else if (strcmp(cmd, \"wrd2\") == 0)\r\n    {\r\n      if (num_param == 3)\r\n      {\r\n        write(portHandler, packetHandler2, atoi(param[0]), atoi(param[1]), 4, atoi(param[2]));\r\n      }\r\n      else\r\n      {\r\n        _fprintf(stderr, (char*) \" Invalid parameters! \\n\");\r\n      }\r\n    }\r\n    else if (strcmp(cmd, \"rdb1\") == 0)\r\n    {\r\n      if (num_param == 2)\r\n      {\r\n        read(portHandler, packetHandler1, atoi(param[0]), atoi(param[1]), 1);\r\n      }\r\n      else\r\n      {\r\n        _fprintf(stderr, (char*) \" Invalid parameters! \\n\");\r\n      }\r\n    }\r\n    else if (strcmp(cmd, \"rdb2\") == 0)\r\n    {\r\n      if (num_param == 2)\r\n      {\r\n        read(portHandler, packetHandler2, atoi(param[0]), atoi(param[1]), 1);\r\n      }\r\n      else\r\n      {\r\n        _fprintf(stderr, (char*) \" Invalid parameters! \\n\");\r\n      }\r\n    }\r\n    else if (strcmp(cmd, \"rdw1\") == 0)\r\n    {\r\n      if (num_param == 2)\r\n      {\r\n        read(portHandler, packetHandler1, atoi(param[0]), atoi(param[1]), 2);\r\n      }\r\n      else\r\n      {\r\n        _fprintf(stderr, (char*) \" Invalid parameters! \\n\");\r\n      }\r\n    }\r\n    else if (strcmp(cmd, \"rdw2\") == 0)\r\n    {\r\n      if (num_param == 2)\r\n      {\r\n        read(portHandler, packetHandler2, atoi(param[0]), atoi(param[1]), 2);\r\n      }\r\n      else\r\n      {\r\n        _fprintf(stderr, (char*) \" Invalid parameters! \\n\");\r\n      }\r\n    }\r\n    else if (strcmp(cmd, \"rdd2\") == 0)\r\n    {\r\n      if (num_param == 2)\r\n      {\r\n        read(portHandler, packetHandler2, atoi(param[0]), atoi(param[1]), 4);\r\n      }\r\n      else\r\n      {\r\n        _fprintf(stderr, (char*) \" Invalid parameters! \\n\");\r\n      }\r\n    }\r\n    else if (strcmp(cmd, \"r1\") == 0)\r\n    {\r\n      if (num_param == 3)\r\n      {\r\n        dump(portHandler, packetHandler1, atoi(param[0]), atoi(param[1]), atoi(param[2]));\r\n      }\r\n      else{\r\n        _fprintf(stderr, (char*) \" Invalid parameters! \\n\");}\r\n    }\r\n    else if (strcmp(cmd, \"r2\") == 0)\r\n    {\r\n      if (num_param == 3)\r\n      {\r\n        dump(portHandler, packetHandler2, atoi(param[0]), atoi(param[1]), atoi(param[2]));\r\n      }\r\n      else\r\n      {\r\n        _fprintf(stderr, (char*) \" Invalid parameters! \\n\");\r\n      }\r\n    }\r\n    else if (strcmp(cmd, \"reboot2\") == 0 || strcmp(cmd, \"rbt2\") == 0)\r\n    {\r\n      if (num_param == 1)\r\n      {\r\n        int dxl_comm_result = packetHandler2->reboot(portHandler, atoi(param[0]), &dxl_error);\r\n        if (dxl_comm_result == COMM_SUCCESS)\r\n        {\r\n          if (dxl_error != 0) packetHandler2->getRxPacketError(dxl_error);\r\n          _fprintf(stderr, (char*) \"\\n Success to reboot! \\n\\n\");\r\n        }\r\n        else\r\n        {\r\n          _fprintf(stderr, (char*) \"%s\\n\", packetHandler2->getTxRxResult(dxl_comm_result));\r\n          _fprintf(stderr, (char*) \"\\n Fail to reboot! \\n\\n\");\r\n        }\r\n      }\r\n      else\r\n      {\r\n          _fprintf(stderr, (char*) \" Invalid parameters! \\n\");\r\n      }\r\n    }\r\n    else if (strcmp(cmd, \"reset1\") == 0 || strcmp(cmd, \"rst1\") == 0)\r\n    {\r\n      if (num_param == 1)\r\n      {\r\n        int dxl_comm_result = packetHandler1->factoryReset(portHandler, atoi(param[0]), 0x00, &dxl_error);\r\n        if (dxl_comm_result == COMM_SUCCESS)\r\n        {\r\n          if (dxl_error != 0)\r\n            packetHandler1->getRxPacketError(dxl_error);\r\n          _fprintf(stderr, (char*) \"\\n Success to reset! \\n\\n\");\r\n        }\r\n        else\r\n        {\r\n          _fprintf(stderr, (char*) \"%s\\n\", packetHandler1->getTxRxResult(dxl_comm_result));\r\n          _fprintf(stderr, (char*) \"\\n Fail to reset! \\n\\n\");\r\n        }\r\n      }\r\n      else\r\n      {\r\n        _fprintf(stderr, (char*) \" Invalid parameters! \\n\");\r\n      }\r\n    }\r\n    else if (strcmp(cmd, \"reset2\") == 0 || strcmp(cmd, \"rst2\") == 0)\r\n    {\r\n      if (num_param == 2)\r\n      {\r\n        int dxl_comm_result = packetHandler2->factoryReset(portHandler, atoi(param[0]), atoi(param[1]), &dxl_error);\r\n        if (dxl_comm_result == COMM_SUCCESS)\r\n        {\r\n          if (dxl_error != 0) packetHandler2->getRxPacketError(dxl_error);\r\n          _fprintf(stderr, (char*) \"\\n Success to reset! \\n\\n\");\r\n        }\r\n        else\r\n        {\r\n          _fprintf(stderr, (char*) \"%s\\n\", packetHandler2->getTxRxResult(dxl_comm_result));\r\n          _fprintf(stderr, (char*) \"\\n Fail to reset! \\n\\n\");\r\n        }\r\n      }\r\n      else\r\n      {\r\n        _fprintf(stderr, (char*) \" Invalid parameters! \\n\");\r\n      }\r\n    }\r\n    else\r\n    {\r\n      _printf((char*) \" Bad command! Please input 'help'.\\n\");\r\n    }\r\n  }\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/07. DynamixelSDK/protocol1.0/bulk_read/bulk_read.ino",
    "content": "/*******************************************************************************\r\n* Copyright (c) 2016, ROBOTIS CO., LTD.\r\n* All rights reserved.\r\n*\r\n* Redistribution and use in source and binary forms, with or without\r\n* modification, are permitted provided that the following conditions are met:\r\n*\r\n* * Redistributions of source code must retain the above copyright notice, this\r\n*   list of conditions and the following disclaimer.\r\n*\r\n* * Redistributions in binary form must reproduce the above copyright notice,\r\n*   this list of conditions and the following disclaimer in the documentation\r\n*   and/or other materials provided with the distribution.\r\n*\r\n* * Neither the name of ROBOTIS nor the names of its\r\n*   contributors may be used to endorse or promote products derived from\r\n*   this software without specific prior written permission.\r\n*\r\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n*******************************************************************************/\r\n\r\n/* Author: Ryu Woon Jung (Leon) */\r\n\r\n//\r\n// *********     Bulk Read Example      *********\r\n//\r\n//\r\n// Available Dynamixel model on this example : MX or X series set to Protocol 1.0\r\n// This example is tested with two Dynamixel MX-28, and an USB2DYNAMIXEL\r\n// Be sure that Dynamixel MX properties are already set as %% ID : 1 / Baudnum : 34 (Baudrate : 57600)\r\n//\r\n\r\n#include <DynamixelSDK.h>\r\n\r\n\r\n// Control table address\r\n#define ADDR_MX_TORQUE_ENABLE           24                  // Control table address is different in Dynamixel model\r\n#define ADDR_MX_GOAL_POSITION           30\r\n#define ADDR_MX_PRESENT_POSITION        36\r\n#define ADDR_MX_MOVING                  46\r\n\r\n// Data Byte Length\r\n#define LEN_MX_GOAL_POSITION            2\r\n#define LEN_MX_PRESENT_POSITION         2\r\n#define LEN_MX_MOVING                   1\r\n\r\n// Protocol version\r\n#define PROTOCOL_VERSION                1.0                 // See which protocol version is used in the Dynamixel\r\n\r\n// Default setting\r\n#define DXL1_ID                         1                   // Dynamixel#1 ID: 1\r\n#define DXL2_ID                         2                   // Dynamixel#2 ID: 2\r\n#define BAUDRATE                        57600\r\n#define DEVICENAME                      \"OpenCR_DXL_Port\"   // This definition only has a symbolic meaning and does not affect to any functionality\r\n\r\n#define TORQUE_ENABLE                   1                   // Value for enabling the torque\r\n#define TORQUE_DISABLE                  0                   // Value for disabling the torque\r\n#define DXL_MINIMUM_POSITION_VALUE      100                 // Dynamixel will rotate between this value\r\n#define DXL_MAXIMUM_POSITION_VALUE      4000                // and this value (note that the Dynamixel would not move when the position value is out of movable range. Check e-manual about the range of the Dynamixel you use.)\r\n#define DXL_MOVING_STATUS_THRESHOLD     10                  // Dynamixel moving status threshold\r\n\r\n#define ESC_ASCII_VALUE                 0x1b\r\n\r\n#define CMD_SERIAL                      Serial\r\n\r\nint getch()\r\n{\r\n  while(1)\r\n  {\r\n    if( CMD_SERIAL.available() > 0 )\r\n    {\r\n      break;\r\n    }\r\n  }\r\n\r\n  return CMD_SERIAL.read();\r\n}\r\n\r\nint kbhit(void)\r\n{\r\n  return CMD_SERIAL.available();\r\n}\r\n\r\nvoid setup()\r\n{\r\n  Serial.begin(115200);\r\n  while(!Serial);\r\n\r\n  Serial.println(\"Start..\");\r\n\r\n  // Initialize PortHandler instance\r\n  // Set the port path\r\n  // Get methods and members of PortHandlerLinux or PortHandlerWindows\r\n  dynamixel::PortHandler *portHandler = dynamixel::PortHandler::getPortHandler(DEVICENAME);\r\n\r\n  // Initialize PacketHandler instance\r\n  // Set the protocol version\r\n  // Get methods and members of Protocol1PacketHandler or Protocol2PacketHandler\r\n  dynamixel::PacketHandler *packetHandler = dynamixel::PacketHandler::getPacketHandler(PROTOCOL_VERSION);\r\n\r\n  // Initialize GroupBulkRead instance\r\n  dynamixel::GroupBulkRead groupBulkRead(portHandler, packetHandler);\r\n\r\n  int index = 0;\r\n  int dxl_comm_result = COMM_TX_FAIL;             // Communication result\r\n  bool dxl_addparam_result = false;               // addParam result\r\n  //bool dxl_getdata_result = false;                // GetParam result\r\n  int dxl_goal_position[2] = {DXL_MINIMUM_POSITION_VALUE, DXL_MAXIMUM_POSITION_VALUE};  // Goal position\r\n\r\n  uint8_t dxl_error = 0;                          // Dynamixel error\r\n  uint16_t dxl1_present_position = 0;             // Present position\r\n  uint8_t dxl2_moving = 0;                        // Dynamixel moving status\r\n\r\n  // Open port\r\n  if (portHandler->openPort())\r\n  {\r\n    Serial.print(\"Succeeded to open the port!\\n\");\r\n  }\r\n  else\r\n  {\r\n    Serial.print(\"Failed to open the port!\\n\");\r\n    return;\r\n  }\r\n\r\n  // Set port baudrate\r\n  if (portHandler->setBaudRate(BAUDRATE))\r\n  {\r\n    Serial.print(\"Succeeded to change the baudrate!\\n\");\r\n  }\r\n  else\r\n  {\r\n    Serial.print(\"Failed to change the baudrate!\\n\");\r\n    return;\r\n  }\r\n\r\n  // Enable Dynamixel#1 Torque\r\n  dxl_comm_result = packetHandler->write1ByteTxRx(portHandler, DXL1_ID, ADDR_MX_TORQUE_ENABLE, TORQUE_ENABLE, &dxl_error);\r\n  if (dxl_comm_result != COMM_SUCCESS)\r\n  {\r\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n  }\r\n  else if (dxl_error != 0)\r\n  {\r\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\r\n  }\r\n  else\r\n  {\r\n    Serial.print(\"Dynamixel#1 has been successfully connected \\n\");\r\n  }\r\n\r\n  // Enable Dynamixel#2 Torque\r\n  dxl_comm_result = packetHandler->write1ByteTxRx(portHandler, DXL2_ID, ADDR_MX_TORQUE_ENABLE, TORQUE_ENABLE, &dxl_error);\r\n  if (dxl_comm_result != COMM_SUCCESS)\r\n  {\r\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n  }\r\n  else if (dxl_error != 0)\r\n  {\r\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\r\n  }\r\n  else\r\n  {\r\n    Serial.print(\"Dynamixel#2 has been successfully connected \\n\");\r\n  }\r\n\r\n  // Add parameter storage for Dynamixel#1 present position value\r\n  dxl_addparam_result = groupBulkRead.addParam(DXL1_ID, ADDR_MX_PRESENT_POSITION, LEN_MX_PRESENT_POSITION);\r\n  if (dxl_addparam_result != true)\r\n  {\r\n    Serial.print(\"[ID:\"); Serial.print(DXL1_ID); Serial.println(\"groupBulkRead addparam failed\");\r\n    return;\r\n  }\r\n\r\n  // Add parameter storage for Dynamixel#2 present moving value\r\n  dxl_addparam_result = groupBulkRead.addParam(DXL2_ID, ADDR_MX_MOVING, LEN_MX_MOVING);\r\n  if (dxl_addparam_result != true)\r\n  {\r\n    Serial.print(\"[ID:\"); Serial.print(DXL2_ID); Serial.println(\"groupBulkRead addparam failed\");\r\n    return;\r\n  }\r\n\r\n  while(1)\r\n  {\r\n    Serial.print(\"Press any key to continue! (or press q to quit!)\\n\");\r\n    if (getch() == 'q')\r\n      break;\r\n\r\n    // Write Dynamixel#1 goal position\r\n    dxl_comm_result = packetHandler->write2ByteTxRx(portHandler, DXL1_ID, ADDR_MX_GOAL_POSITION, dxl_goal_position[index], &dxl_error);\r\n    if (dxl_comm_result != COMM_SUCCESS)\r\n    {\r\n      Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n    }\r\n    else if (dxl_error != 0)\r\n    {\r\n      Serial.print(packetHandler->getRxPacketError(dxl_error));\r\n    }\r\n\r\n    // Write Dynamixel#2 goal position\r\n    dxl_comm_result = packetHandler->write2ByteTxRx(portHandler, DXL2_ID, ADDR_MX_GOAL_POSITION, dxl_goal_position[index], &dxl_error);\r\n    if (dxl_comm_result != COMM_SUCCESS)\r\n    {\r\n      Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n    }\r\n    else if (dxl_error != 0)\r\n    {\r\n      Serial.print(packetHandler->getRxPacketError(dxl_error));\r\n    }\r\n\r\n    do\r\n    {\r\n      // Bulkread present position and moving status\r\n      dxl_comm_result = groupBulkRead.txRxPacket();\r\n      if (dxl_comm_result != COMM_SUCCESS) printf(\"%s\\n\", packetHandler->getTxRxResult(dxl_comm_result));\r\n\r\n      groupBulkRead.isAvailable(DXL1_ID, ADDR_MX_PRESENT_POSITION, LEN_MX_PRESENT_POSITION);\r\n      if (dxl_addparam_result != true)\r\n      {\r\n        Serial.print(\"[ID:\"); Serial.print(DXL1_ID); Serial.println(\"groupBulkRead getdata failed\");\r\n        return;\r\n      }\r\n\r\n      groupBulkRead.isAvailable(DXL2_ID, ADDR_MX_MOVING, LEN_MX_MOVING);\r\n      if (dxl_addparam_result != true)\r\n      {\r\n        Serial.print(\"[ID:\"); Serial.print(DXL2_ID); Serial.println(\"groupBulkRead getdata failed\");\r\n        return;\r\n      }\r\n\r\n      // Get Dynamixel#1 present position value\r\n      dxl1_present_position = groupBulkRead.getData(DXL1_ID, ADDR_MX_PRESENT_POSITION, LEN_MX_PRESENT_POSITION);\r\n\r\n      // Get Dynamixel#2 moving status value\r\n      dxl2_moving = groupBulkRead.getData(DXL2_ID, ADDR_MX_MOVING, LEN_MX_MOVING);\r\n\r\n      Serial.print(\"[ID:\"); Serial.print(DXL1_ID);\r\n      Serial.print(\"] Present Position : \"); Serial.print(dxl1_present_position);\r\n      Serial.print(\"  [ID:\"); Serial.print(DXL2_ID);\r\n      Serial.print(\"] Is Moving : \"); Serial.print(dxl2_moving);\r\n\r\n    }while(abs(dxl_goal_position[index] - dxl1_present_position) > DXL_MOVING_STATUS_THRESHOLD);\r\n\r\n    // Change goal position\r\n    if (index == 0)\r\n    {\r\n      index = 1;\r\n    }\r\n    else\r\n    {\r\n      index = 0;\r\n    }\r\n  }\r\n\r\n  // Disable Dynamixel#1 Torque\r\n  dxl_comm_result = packetHandler->write1ByteTxRx(portHandler, DXL1_ID, ADDR_MX_TORQUE_ENABLE, TORQUE_DISABLE, &dxl_error);\r\n  if (dxl_comm_result != COMM_SUCCESS)\r\n  {\r\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n  }\r\n  else if (dxl_error != 0)\r\n  {\r\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\r\n  }\r\n\r\n  // Disable Dynamixel#2 Torque\r\n  dxl_comm_result = packetHandler->write1ByteTxRx(portHandler, DXL2_ID, ADDR_MX_TORQUE_ENABLE, TORQUE_DISABLE, &dxl_error);\r\n  if (dxl_comm_result != COMM_SUCCESS)\r\n  {\r\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n  }\r\n  else if (dxl_error != 0)\r\n  {\r\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\r\n  }\r\n\r\n  // Close port\r\n  portHandler->closePort();\r\n}\r\n\r\nvoid loop()\r\n{\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/07. DynamixelSDK/protocol1.0/ping/ping.ino",
    "content": "/*******************************************************************************\n* Copyright (c) 2016, ROBOTIS CO., LTD.\n* All rights reserved.\n*\n* Redistribution and use in source and binary forms, with or without\n* modification, are permitted provided that the following conditions are met:\n*\n* * Redistributions of source code must retain the above copyright notice, this\n*   list of conditions and the following disclaimer.\n*\n* * Redistributions in binary form must reproduce the above copyright notice,\n*   this list of conditions and the following disclaimer in the documentation\n*   and/or other materials provided with the distribution.\n*\n* * Neither the name of ROBOTIS nor the names of its\n*   contributors may be used to endorse or promote products derived from\n*   this software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*******************************************************************************/\n\n/* Author: Ryu Woon Jung (Leon) */\n\n//\n// *********     ping Example      *********\n//\n//\n// Available Dynamixel model on this example : All models using Protocol 1.0\n// This example is tested with a Dynamixel MX-28, and an USB2DYNAMIXEL\n// Be sure that Dynamixel MX properties are already set as %% ID : 1 / Baudnum : 34 (Baudrate : 57600)\n//\n\n#include <DynamixelSDK.h>\n\n\n// Protocol version\n#define PROTOCOL_VERSION                1.0                 // See which protocol version is used in the Dynamixel\n\n// Default setting\n#define DXL_ID                          1                   // Dynamixel ID: 1\n#define BAUDRATE                        57600\n#define DEVICENAME                      \"OpenCR_DXL_Port\"   // This definition only has a symbolic meaning and does not affect to any functionality\n\n#define CMD_SERIAL                      Serial\n\nint getch()\n{\n  while(1)\n  {\n    if( CMD_SERIAL.available() > 0 )\n    {\n      break;\n    }\n  }\n\n  return CMD_SERIAL.read();\n}\n\nint kbhit(void)\n{\n  return CMD_SERIAL.available();\n}\n\nvoid setup()\n{\n  Serial.begin(115200);\n  while(!Serial);\n\n  Serial.println(\"Start..\");\n\n  // Initialize PortHandler instance\n  // Set the port path\n  // Get methods and members of PortHandlerLinux or PortHandlerWindows\n  dynamixel::PortHandler *portHandler = dynamixel::PortHandler::getPortHandler(DEVICENAME);\n\n  // Initialize PacketHandler instance\n  // Set the protocol version\n  // Get methods and members of Protocol1PacketHandler or Protocol2PacketHandler\n  dynamixel::PacketHandler *packetHandler = dynamixel::PacketHandler::getPacketHandler(PROTOCOL_VERSION);\n\n  int dxl_comm_result = COMM_TX_FAIL;             // Communication result\n\n  uint8_t dxl_error = 0;                          // Dynamixel error\n  uint16_t dxl_model_number;                      // Dynamixel model number\n\n  // Open port\n  if (portHandler->openPort())\n  {\n    Serial.print(\"Succeeded to open the port!\\n\");\n  }\n  else\n  {\n    Serial.print(\"Failed to open the port!\\n\");\n    return;\n  }\n\n  // Set port baudrate\n  if (portHandler->setBaudRate(BAUDRATE))\n  {\n    Serial.print(\"Succeeded to change the baudrate!\\n\");\n  }\n  else\n  {\n    Serial.print(\"Failed to change the baudrate!\\n\");\n    return;\n  }\n\n  // Try to ping the Dynamixel\n  // Get Dynamixel model number\n  dxl_comm_result = packetHandler->ping(portHandler, DXL_ID, &dxl_model_number, &dxl_error);\n  if (dxl_comm_result != COMM_SUCCESS)\n  {\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\n  }\n  else if (dxl_error != 0)\n  {\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\n  }\n\n  Serial.print(\"[ID:\"); Serial.print(DXL_ID);\n  Serial.print(\"] ping Succeeded. Dynamixel model number : \");\n  Serial.println(dxl_model_number);\n\n  // Close port\n  portHandler->closePort();\n}\n\nvoid loop()\n{\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/07. DynamixelSDK/protocol1.0/read_write/read_write.ino",
    "content": "/*******************************************************************************\n* Copyright (c) 2016, ROBOTIS CO., LTD.\n* All rights reserved.\n*\n* Redistribution and use in source and binary forms, with or without\n* modification, are permitted provided that the following conditions are met:\n*\n* * Redistributions of source code must retain the above copyright notice, this\n*   list of conditions and the following disclaimer.\n*\n* * Redistributions in binary form must reproduce the above copyright notice,\n*   this list of conditions and the following disclaimer in the documentation\n*   and/or other materials provided with the distribution.\n*\n* * Neither the name of ROBOTIS nor the names of its\n*   contributors may be used to endorse or promote products derived from\n*   this software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*******************************************************************************/\n\n/* Author: Ryu Woon Jung (Leon) */\n\n//\n// *********     Read and Write Example      *********\n//\n//\n// Available DXL model on this example : All models using Protocol 1.0\n// This example is tested with a DXL MX-28, and an USB2DYNAMIXEL\n// Be sure that DXL MX properties are already set as %% ID : 1 / Baudnum : 34 (Baudrate : 57600)\n//\n\n#include <DynamixelSDK.h>\n\n\n// Control table address\n#define ADDR_MX_TORQUE_ENABLE           24                  // Control table address is different in Dynamixel model\n#define ADDR_MX_GOAL_POSITION           30\n#define ADDR_MX_PRESENT_POSITION        36\n\n// Protocol version\n#define PROTOCOL_VERSION                1.0                 // See which protocol version is used in the Dynamixel\n\n// Default setting\n#define DXL_ID                          1                   // Dynamixel ID: 1\n#define BAUDRATE                        57600\n#define DEVICENAME                      \"OpenCR_DXL_Port\"   // This definition only has a symbolic meaning and does not affect to any functionality\n\n\n#define TORQUE_ENABLE                   1                   // Value for enabling the torque\n#define TORQUE_DISABLE                  0                   // Value for disabling the torque\n#define DXL_MINIMUM_POSITION_VALUE      100                 // Dynamixel will rotate between this value\n#define DXL_MAXIMUM_POSITION_VALUE      4000                // and this value (note that the Dynamixel would not move when the position value is out of movable range. Check e-manual about the range of the Dynamixel you use.)\n#define DXL_MOVING_STATUS_THRESHOLD     10                  // Dynamixel moving status threshold\n\n#define ESC_ASCII_VALUE                 0x1b\n\n#define CMD_SERIAL                      Serial\n\nint getch()\n{\n  while(1)\n  {\n    if( CMD_SERIAL.available() > 0 )\n    {\n      break;\n    }\n  }\n\n  return CMD_SERIAL.read();\n}\n\nint kbhit(void)\n{\n  return CMD_SERIAL.available();\n}\n\nvoid setup()\n{\n  Serial.begin(115200);\n  while(!Serial);\n\n  Serial.println(\"Start..\");\n\n  // Initialize PortHandler instance\n  // Set the port path\n  // Get methods and members of PortHandlerLinux or PortHandlerWindows\n  dynamixel::PortHandler *portHandler = dynamixel::PortHandler::getPortHandler(DEVICENAME);\n\n  // Initialize PacketHandler instance\n  // Set the protocol version\n  // Get methods and members of Protocol1PacketHandler or Protocol2PacketHandler\n  dynamixel::PacketHandler *packetHandler = dynamixel::PacketHandler::getPacketHandler(PROTOCOL_VERSION);\n\n  int index = 0;\n  int dxl_comm_result = COMM_TX_FAIL;             // Communication result\n  int dxl_goal_position[2] = {DXL_MINIMUM_POSITION_VALUE, DXL_MAXIMUM_POSITION_VALUE};         // Goal position\n\n  uint8_t dxl_error = 0;                          // Dynamixel error\n  uint16_t dxl_present_position = 0;              // Present position\n\n  // Open port\n  if (portHandler->openPort())\n  {\n    Serial.print(\"Succeeded to open the port!\\n\");\n  }\n  else\n  {\n    Serial.print(\"Failed to open the port!\\n\");\n    return;\n  }\n\n  // Set port baudrate\n  if (portHandler->setBaudRate(BAUDRATE))\n  {\n    Serial.print(\"Succeeded to change the baudrate!\\n\");\n  }\n  else\n  {\n    Serial.print(\"Failed to change the baudrate!\\n\");\n    return;\n  }\n\n  // Enable Dynamixel Torque\n  dxl_comm_result = packetHandler->write1ByteTxRx(portHandler, DXL_ID, ADDR_MX_TORQUE_ENABLE, TORQUE_ENABLE, &dxl_error);\n  if (dxl_comm_result != COMM_SUCCESS)\n  {\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\n  }\n  else if (dxl_error != 0)\n  {\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\n  }\n  else\n  {\n    Serial.print(\"Dynamixel has been successfully connected \\n\");\n  }\n\n  while(1)\n  {\n    Serial.print(\"Press any key to continue! (or press q to quit!)\\n\");\n    if (getch() == 'q')\n      break;\n\n    // Write goal position\n    dxl_comm_result = packetHandler->write2ByteTxRx(portHandler, DXL_ID, ADDR_MX_GOAL_POSITION, dxl_goal_position[index], &dxl_error);\n    if (dxl_comm_result != COMM_SUCCESS)\n    {\n      Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\n    }\n    else if (dxl_error != 0)\n    {\n      Serial.print(packetHandler->getRxPacketError(dxl_error));\n    }\n\n    do\n    {\n      // Read present position\n      dxl_comm_result = packetHandler->read2ByteTxRx(portHandler, DXL_ID, ADDR_MX_PRESENT_POSITION, &dxl_present_position, &dxl_error);\n      if (dxl_comm_result != COMM_SUCCESS)\n      {\n        Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\n      }\n      else if (dxl_error != 0)\n      {\n        Serial.print(packetHandler->getRxPacketError(dxl_error));\n      }\n\n      Serial.print(\"[ID:\"); Serial.print(DXL_ID);\n      Serial.print(\"] GoalPos:\"); Serial.print(dxl_goal_position[index]);\n      Serial.print(\"  PresPos:\"); Serial.print(dxl_present_position);\n      Serial.println(\" \");\n\n    }while((abs(dxl_goal_position[index] - dxl_present_position) > DXL_MOVING_STATUS_THRESHOLD));\n\n    // Change goal position\n    if (index == 0)\n    {\n      index = 1;\n    }\n    else\n    {\n      index = 0;\n    }\n  }\n\n  // Disable Dynamixel Torque\n  dxl_comm_result = packetHandler->write1ByteTxRx(portHandler, DXL_ID, ADDR_MX_TORQUE_ENABLE, TORQUE_DISABLE, &dxl_error);\n  if (dxl_comm_result != COMM_SUCCESS)\n  {\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\n  }\n  else if (dxl_error != 0)\n  {\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\n  }\n\n  // Close port\n  portHandler->closePort();\n}\n\nvoid loop()\n{\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/07. DynamixelSDK/protocol1.0/reset/reset.ino",
    "content": "/*******************************************************************************\n* Copyright (c) 2016, ROBOTIS CO., LTD.\n* All rights reserved.\n*\n* Redistribution and use in source and binary forms, with or without\n* modification, are permitted provided that the following conditions are met:\n*\n* * Redistributions of source code must retain the above copyright notice, this\n*   list of conditions and the following disclaimer.\n*\n* * Redistributions in binary form must reproduce the above copyright notice,\n*   this list of conditions and the following disclaimer in the documentation\n*   and/or other materials provided with the distribution.\n*\n* * Neither the name of ROBOTIS nor the names of its\n*   contributors may be used to endorse or promote products derived from\n*   this software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*******************************************************************************/\n\n/* Author: Ryu Woon Jung (Leon) */\n\n//\n// *********     Factory Reset Example      *********\n//\n//\n// Available Dynamixel model on this example : All models using Protocol 1.0\n// This example is tested with a Dynamixel MX-28, and an USB2DYNAMIXEL\n// Be sure that Dynamixel PRO properties are already set as %% ID : 1 / Baudnum : 34 (Baudrate : 57600)\n//\n\n// Be aware that:\n// This example resets all properties of Dynamixel to default values, such as %% ID : 1 / Baudnum : 34 (Baudrate : 57600)\n//\n\n#include <DynamixelSDK.h>\n\n// Control table address\n#define ADDR_MX_BAUDRATE                4                   // Control table address is different in Dynamixel model\n\n// Protocol version\n#define PROTOCOL_VERSION                1.0                 // See which protocol version is used in the Dynamixel\n\n// Default setting\n#define DXL_ID                          1                   // Dynamixel ID: 1\n#define BAUDRATE                        57600\n#define DEVICENAME                      \"OpenCR_DXL_Port\"   // This definition only has a symbolic meaning and does not affect to any functionality\n\n#define FACTORYRST_DEFAULTBAUDRATE      57600               // Dynamixel baudrate set by factoryreset\n#define NEW_BAUDNUM                     1                   // New baudnum to recover Dynamixel baudrate as it was\n#define OPERATION_MODE                  0x00                // Mode is unavailable in Protocol 1.0 Reset\n\n#define TORQUE_ENABLE                   1                   // Value for enabling the torque\n#define TORQUE_DISABLE                  0                   // Value for disabling the torque\n\n#define CMD_SERIAL                      Serial\n\nint getch()\n{\n  while(1)\n  {\n    if( CMD_SERIAL.available() > 0 )\n    {\n      break;\n    }\n  }\n\n  return CMD_SERIAL.read();\n}\n\nint kbhit(void)\n{\n  return CMD_SERIAL.available();\n}\n\nvoid setup()\n{\n  Serial.begin(115200);\n  while(!Serial);\n\n  Serial.println(\"Start..\");\n\n  // Initialize PortHandler instance\n  // Set the port path\n  // Get methods and members of PortHandlerLinux or PortHandlerWindows\n  dynamixel::PortHandler *portHandler = dynamixel::PortHandler::getPortHandler(DEVICENAME);\n\n  // Initialize PacketHandler instance\n  // Set the protocol version\n  // Get methods and members of Protocol1PacketHandler or Protocol2PacketHandler\n  dynamixel::PacketHandler *packetHandler = dynamixel::PacketHandler::getPacketHandler(PROTOCOL_VERSION);\n\n  int dxl_comm_result = COMM_TX_FAIL;             // Communication result\n\n  uint8_t dxl_error = 0;                          // Dynamixel error\n  uint8_t dxl_baudnum_read;                       // Read baudnum\n\n  // Open port\n  if (portHandler->openPort())\n  {\n    Serial.print(\"Succeeded to open the port!\\n\");\n  }\n  else\n  {\n    Serial.print(\"Failed to open the port!\\n\");\n    return;\n  }\n\n  // Set port baudrate\n  if (portHandler->setBaudRate(BAUDRATE))\n  {\n    Serial.print(\"Succeeded to change the baudrate!\\n\");\n  }\n  else\n  {\n    Serial.print(\"Failed to change the baudrate!\\n\");\n    return;\n  }\n\n  // Read present baudrate of the controller\n  Serial.print(\"Now the controller baudrate is :\");\n  Serial.print(portHandler->getBaudRate());\n\n  // Try factoryreset\n  Serial.print(\"[ID:\"); Serial.print(DXL_ID);\n  Serial.print(\"] Try factoryreset : \");\n\n  dxl_comm_result = packetHandler->factoryReset(portHandler, DXL_ID, OPERATION_MODE, &dxl_error);\n  if (dxl_comm_result != COMM_SUCCESS)\n  {\n    Serial.print(\"Aborted\\n\");\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\n    return;\n  }\n  else if (dxl_error != 0)\n  {\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\n  }\n\n  // Wait for reset\n  Serial.print(\"Wait for reset...\\n\");\n  delay(2000);\n\n  Serial.print(\"[ID:\"); Serial.print(DXL_ID);\n  Serial.print(\"] factoryReset Success!\\n\");\n\n  // Set controller baudrate to Dynamixel default baudrate\n  if (portHandler->setBaudRate(FACTORYRST_DEFAULTBAUDRATE))\n  {\n    Serial.print(\"Succeed to change the controller baudrate to : \");\n    Serial.print(FACTORYRST_DEFAULTBAUDRATE);\n  }\n  else\n  {\n    Serial.print(\"Failed to change the controller baudrate\\n\");\n    return;\n  }\n\n  // Read Dynamixel baudnum\n  dxl_comm_result = packetHandler->read1ByteTxRx(portHandler, DXL_ID, ADDR_MX_BAUDRATE, &dxl_baudnum_read, &dxl_error);\n  if (dxl_comm_result != COMM_SUCCESS)\n  {\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\n  }\n  else if (dxl_error != 0)\n  {\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\n  }\n  else\n  {\n    Serial.print(\"[ID:\"); Serial.print(DXL_ID);\n    Serial.print(\"] DXL baudnum is now : \");\n    Serial.println(dxl_baudnum_read);\n  }\n\n  // Write new baudnum\n  dxl_comm_result = packetHandler->write1ByteTxRx(portHandler, DXL_ID, ADDR_MX_BAUDRATE, NEW_BAUDNUM, &dxl_error);\n  if (dxl_comm_result != COMM_SUCCESS)\n  {\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\n  }\n  else if (dxl_error != 0)\n  {\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\n  }\n  else\n  {\n    Serial.print(\"[ID:\"); Serial.print(DXL_ID);\n    Serial.print(\"] Set Dynamixel baudnum to : \");\n    Serial.println(NEW_BAUDNUM);\n  }\n\n  // Set port baudrate to BAUDRATE\n  if (portHandler->setBaudRate(BAUDRATE))\n  {\n    Serial.print(\"Succeed to change the controller baudrate to : \");\n    Serial.print(BAUDRATE);\n  }\n  else\n  {\n    Serial.print(\"Failed to change the controller baudrate\\n\");\n    return;\n  }\n\n  delay(200);\n\n  // Read Dynamixel baudnum\n  dxl_comm_result = packetHandler->read1ByteTxRx(portHandler, DXL_ID, ADDR_MX_BAUDRATE, &dxl_baudnum_read, &dxl_error);\n  if (dxl_comm_result != COMM_SUCCESS)\n  {\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\n  }\n  else if (dxl_error != 0)\n  {\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\n  }\n  else\n  {\n    Serial.print(\"[ID:\"); Serial.print(DXL_ID);\n    Serial.print(\"] Dynamixel Baudnum is now : \");\n    Serial.print(dxl_baudnum_read);\n  }\n\n  // Close port\n  portHandler->closePort();\n}\n\nvoid loop()\n{\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/07. DynamixelSDK/protocol1.0/sync_write/sync_write.ino",
    "content": "/*******************************************************************************\n* Copyright (c) 2016, ROBOTIS CO., LTD.\n* All rights reserved.\n*\n* Redistribution and use in source and binary forms, with or without\n* modification, are permitted provided that the following conditions are met:\n*\n* * Redistributions of source code must retain the above copyright notice, this\n*   list of conditions and the following disclaimer.\n*\n* * Redistributions in binary form must reproduce the above copyright notice,\n*   this list of conditions and the following disclaimer in the documentation\n*   and/or other materials provided with the distribution.\n*\n* * Neither the name of ROBOTIS nor the names of its\n*   contributors may be used to endorse or promote products derived from\n*   this software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*******************************************************************************/\n\n/* Author: Ryu Woon Jung (Leon) */\n\n//\n// *********     Sync Write Example      *********\n//\n//\n// Available Dynamixel model on this example : All models using Protocol 1.0\n// This example is tested with two Dynamixel MX-28, and an USB2DYNAMIXEL\n// Be sure that Dynamixel MX properties are already set as %% ID : 1 / Baudnum : 34 (Baudrate : 57600)\n//\n\n#include <DynamixelSDK.h>\n\n// Control table address\n#define ADDR_MX_TORQUE_ENABLE           24                  // Control table address is different in Dynamixel model\n#define ADDR_MX_GOAL_POSITION           30\n#define ADDR_MX_PRESENT_POSITION        36\n\n// Data Byte Length\n#define LEN_MX_GOAL_POSITION            2\n#define LEN_MX_PRESENT_POSITION         2\n\n// Protocol version\n#define PROTOCOL_VERSION                1.0                 // See which protocol version is used in the Dynamixel\n\n// Default setting\n#define DXL1_ID                         1                   // Dynamixel#1 ID: 1\n#define DXL2_ID                         2                   // Dynamixel#2 ID: 2\n#define BAUDRATE                        57600\n#define DEVICENAME                      \"OpenCR_DXL_Port\"   // This definition only has a symbolic meaning and does not affect to any functionality\n\n#define TORQUE_ENABLE                   1                   // Value for enabling the torque\n#define TORQUE_DISABLE                  0                   // Value for disabling the torque\n#define DXL_MINIMUM_POSITION_VALUE      100                 // Dynamixel will rotate between this value\n#define DXL_MAXIMUM_POSITION_VALUE      1000                // and this value (note that the Dynamixel would not move when the position value is out of movable range. Check e-manual about the range of the Dynamixel you use.)\n#define DXL_MOVING_STATUS_THRESHOLD     10                  // Dynamixel moving status threshold\n\n#define ESC_ASCII_VALUE                 0x1b\n\n#define CMD_SERIAL                      Serial\n\nint getch()\n{\n  while(1)\n  {\n    if( CMD_SERIAL.available() > 0 )\n    {\n      break;\n    }\n  }\n\n  return CMD_SERIAL.read();\n}\n\nint kbhit(void)\n{\n  return CMD_SERIAL.available();\n}\n\nvoid setup()\n{\n  Serial.begin(115200);\n  while(!Serial);\n\n  Serial.println(\"Start..\");\n\n  // Initialize PortHandler instance\n  // Set the port path\n  // Get methods and members of PortHandlerLinux or PortHandlerWindows\n  dynamixel::PortHandler *portHandler = dynamixel::PortHandler::getPortHandler(DEVICENAME);\n\n  // Initialize PacketHandler instance\n  // Set the protocol version\n  // Get methods and members of Protocol1PacketHandler or Protocol2PacketHandler\n  dynamixel::PacketHandler *packetHandler = dynamixel::PacketHandler::getPacketHandler(PROTOCOL_VERSION);\n\n  // Initialize GroupSyncWrite instance\n  dynamixel::GroupSyncWrite groupSyncWrite(portHandler, packetHandler, ADDR_MX_GOAL_POSITION, LEN_MX_GOAL_POSITION);\n\n  int index = 0;\n  int dxl_comm_result = COMM_TX_FAIL;             // Communication result\n  bool dxl_addparam_result = false;               // addParam result\n  int dxl_goal_position[2] = {DXL_MINIMUM_POSITION_VALUE, DXL_MAXIMUM_POSITION_VALUE};  // Goal position\n\n  uint8_t dxl_error = 0;                          // Dynamixel error\n  uint8_t param_goal_position[2];\n  uint16_t dxl1_present_position = 0, dxl2_present_position = 0;                        // Present position\n\n  // Open port\n  if (portHandler->openPort())\n  {\n    Serial.print(\"Succeeded to open the port!\\n\");\n  }\n  else\n  {\n    Serial.print(\"Failed to open the port!\\n\");\n    return;\n  }\n\n  // Set port baudrate\n  if (portHandler->setBaudRate(BAUDRATE))\n  {\n    Serial.print(\"Succeeded to change the baudrate!\\n\");\n  }\n  else\n  {\n    Serial.print(\"Failed to change the baudrate!\\n\");\n    return;\n  }\n\n  // Enable Dynamixel#1 Torque\n  dxl_comm_result = packetHandler->write1ByteTxRx(portHandler, DXL1_ID, ADDR_MX_TORQUE_ENABLE, TORQUE_ENABLE, &dxl_error);\n  if (dxl_comm_result != COMM_SUCCESS)\n  {\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\n  }\n  else if (dxl_error != 0)\n  {\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\n  }\n  else\n  {\n    Serial.print(\"Dynamixel#1 has been successfully connected \\n\");\n  }\n\n  // Enable Dynamixel#2 Torque\n  dxl_comm_result = packetHandler->write1ByteTxRx(portHandler, DXL2_ID, ADDR_MX_TORQUE_ENABLE, TORQUE_ENABLE, &dxl_error);\n  if (dxl_comm_result != COMM_SUCCESS)\n  {\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\n  }\n  else if (dxl_error != 0)\n  {\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\n  }\n  else\n  {\n    Serial.print(\"Dynamixel#2 has been successfully connected \\n\");\n  }\n\n  while(1)\n  {\n    Serial.print(\"Press any key to continue! (or press q to quit!)\\n\");\n    if (getch() == 'q')\n      break;\n\n    // Allocate goal position value into byte array\n    param_goal_position[0] = DXL_LOBYTE(dxl_goal_position[index]);\n    param_goal_position[1] = DXL_HIBYTE(dxl_goal_position[index]);\n\n    // Add Dynamixel#1 goal position value to the Syncwrite storage\n    dxl_addparam_result = groupSyncWrite.addParam(DXL1_ID, param_goal_position);\n    if (dxl_addparam_result != true)\n    {\n      Serial.print(\"[ID:\"); Serial.print(DXL1_ID); Serial.println(\"groupSyncWrite addparam failed\");\n      return;\n    }\n\n    // Add Dynamixel#2 goal position value to the Syncwrite parameter storage\n    dxl_addparam_result = groupSyncWrite.addParam(DXL2_ID, param_goal_position);\n    if (dxl_addparam_result != true)\n    {\n      Serial.print(\"[ID:\"); Serial.print(DXL2_ID); Serial.println(\"groupSyncWrite addparam failed\");\n      return;\n    }\n\n    // Syncwrite goal position\n    dxl_comm_result = groupSyncWrite.txPacket();\n    if (dxl_comm_result != COMM_SUCCESS) Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\n\n    // Clear syncwrite parameter storage\n    groupSyncWrite.clearParam();\n\n    do\n    {\n      // Read Dynamixel#1 present position\n      dxl_comm_result = packetHandler->read2ByteTxRx(portHandler, DXL1_ID, ADDR_MX_PRESENT_POSITION, &dxl1_present_position, &dxl_error);\n      if (dxl_comm_result != COMM_SUCCESS)\n      {\n        Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\n      }\n      else if (dxl_error != 0)\n      {\n        Serial.print(packetHandler->getRxPacketError(dxl_error));\n      }\n\n      // Read Dynamixel#2 present position\n      dxl_comm_result = packetHandler->read2ByteTxRx(portHandler, DXL2_ID, ADDR_MX_PRESENT_POSITION, &dxl2_present_position, &dxl_error);\n      if (dxl_comm_result != COMM_SUCCESS)\n      {\n        Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\n      }\n      else if (dxl_error != 0)\n      {\n        Serial.print(packetHandler->getRxPacketError(dxl_error));\n      }\n\n      Serial.print(\"[ID:\"); Serial.print(DXL1_ID);\n      Serial.print(\"] GoalPos:\"); Serial.print(dxl_goal_position[index]);\n      Serial.print(\"  PresPos:\"); Serial.print(dxl1_present_position);\n      Serial.print(\" [ID:\"); Serial.print(DXL2_ID);\n      Serial.print(\"] GoalPos:\"); Serial.print(dxl_goal_position[index]);\n      Serial.print(\"  PresPos:\"); Serial.print(dxl2_present_position);\n      Serial.println(\" \");\n\n    }while((abs(dxl_goal_position[index] - dxl1_present_position) > DXL_MOVING_STATUS_THRESHOLD) || (abs(dxl_goal_position[index] - dxl2_present_position) > DXL_MOVING_STATUS_THRESHOLD));\n\n    // Change goal position\n    if (index == 0)\n    {\n      index = 1;\n    }\n    else\n    {\n      index = 0;\n    }\n  }\n\n  // Disable Dynamixel#1 Torque\n  dxl_comm_result = packetHandler->write1ByteTxRx(portHandler, DXL1_ID, ADDR_MX_TORQUE_ENABLE, TORQUE_DISABLE, &dxl_error);\n  if (dxl_comm_result != COMM_SUCCESS)\n  {\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\n  }\n  else if (dxl_error != 0)\n  {\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\n  }\n\n  // Disable Dynamixel#2 Torque\n  dxl_comm_result = packetHandler->write1ByteTxRx(portHandler, DXL2_ID, ADDR_MX_TORQUE_ENABLE, TORQUE_DISABLE, &dxl_error);\n  if (dxl_comm_result != COMM_SUCCESS)\n  {\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\n  }\n  else if (dxl_error != 0)\n  {\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\n  }\n\n  // Close port\n  portHandler->closePort();\n}\n\nvoid loop()\n{\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/07. DynamixelSDK/protocol2.0/broadcast_ping/broadcast_ping.ino",
    "content": "/*******************************************************************************\r\n* Copyright (c) 2016, ROBOTIS CO., LTD.\r\n* All rights reserved.\r\n*\r\n* Redistribution and use in source and binary forms, with or without\r\n* modification, are permitted provided that the following conditions are met:\r\n*\r\n* * Redistributions of source code must retain the above copyright notice, this\r\n*   list of conditions and the following disclaimer.\r\n*\r\n* * Redistributions in binary form must reproduce the above copyright notice,\r\n*   this list of conditions and the following disclaimer in the documentation\r\n*   and/or other materials provided with the distribution.\r\n*\r\n* * Neither the name of ROBOTIS nor the names of its\r\n*   contributors may be used to endorse or promote products derived from\r\n*   this software without specific prior written permission.\r\n*\r\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n*******************************************************************************/\r\n\r\n/* Author: Ryu Woon Jung (Leon) */\r\n\r\n//\r\n// *********     broadcastPing Example      *********\r\n//\r\n//\r\n// Available Dynamixel model on this example : All models using Protocol 2.0\r\n// This example is tested with two Dynamixel PRO 54-200, and an USB2DYNAMIXEL\r\n// Be sure that Dynamixel PRO properties are already set as %% ID : 1 / Baudnum : 1 (Baudrate : 57600)\r\n//\r\n\r\n#include <DynamixelSDK.h>\r\n\r\n\r\n// Protocol version\r\n#define PROTOCOL_VERSION                2.0                 // See which protocol version is used in the Dynamixel\r\n\r\n// Default setting\r\n#define BAUDRATE                        57600\r\n#define DEVICENAME                      \"OpenCR_DXL_Port\"   // This definition only has a symbolic meaning and does not affect to any functionality\r\n\r\n\r\nvoid setup()\r\n{\r\n  Serial.begin(115200);\r\n  while(!Serial);\r\n\r\n  Serial.println(\"Start..\");\r\n\r\n  // Initialize PortHandler instance\r\n  // Set the port path\r\n  // Get methods and members of PortHandlerLinux or PortHandlerWindows\r\n  dynamixel::PortHandler *portHandler = dynamixel::PortHandler::getPortHandler(DEVICENAME);\r\n\r\n  // Initialize PacketHandler instance\r\n  // Set the protocol version\r\n  // Get methods and members of Protocol1PacketHandler or Protocol2PacketHandler\r\n  dynamixel::PacketHandler *packetHandler = dynamixel::PacketHandler::getPacketHandler(PROTOCOL_VERSION);\r\n\r\n  int dxl_comm_result = COMM_TX_FAIL;             // Communication result\r\n\r\n  //uint8_t dxl_error = 0;                          // Dynamixel error\r\n  //uint16_t dxl_model_number;                      // Dynamixel model number\r\n\r\n  std::vector<uint8_t> vec;                       // Dynamixel data storages\r\n\r\n  // Open port\r\n  if (portHandler->openPort())\r\n  {\r\n    Serial.print(\"Succeeded to open the port!\\n\");\r\n  }\r\n  else\r\n  {\r\n    Serial.print(\"Failed to open the port!\\n\");\r\n    return;\r\n  }\r\n\r\n  // Set port baudrate\r\n  if (portHandler->setBaudRate(BAUDRATE))\r\n  {\r\n    Serial.print(\"Succeeded to change the baudrate!\\n\");\r\n  }\r\n  else\r\n  {\r\n    Serial.print(\"Failed to change the baudrate!\\n\");\r\n    return;\r\n  }\r\n\r\n  // Try to broadcast ping the Dynamixel\r\n  dxl_comm_result = packetHandler->broadcastPing(portHandler, vec);\r\n  if (dxl_comm_result != COMM_SUCCESS) Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n\r\n  Serial.print(\"Detected Dynamixel : \\n\");\r\n  for (int i = 0; i < (int)vec.size(); i++)\r\n  {\r\n    Serial.print(\"[ID:\"); Serial.print(vec.at(i));\r\n    Serial.println(\"]\");\r\n  }\r\n\r\n  // Close port\r\n  portHandler->closePort();\r\n}\r\n\r\nvoid loop()\r\n{\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/07. DynamixelSDK/protocol2.0/bulk_read_write/bulk_read_write.ino",
    "content": "/*******************************************************************************\r\n* Copyright (c) 2016, ROBOTIS CO., LTD.\r\n* All rights reserved.\r\n*\r\n* Redistribution and use in source and binary forms, with or without\r\n* modification, are permitted provided that the following conditions are met:\r\n*\r\n* * Redistributions of source code must retain the above copyright notice, this\r\n*   list of conditions and the following disclaimer.\r\n*\r\n* * Redistributions in binary form must reproduce the above copyright notice,\r\n*   this list of conditions and the following disclaimer in the documentation\r\n*   and/or other materials provided with the distribution.\r\n*\r\n* * Neither the name of ROBOTIS nor the names of its\r\n*   contributors may be used to endorse or promote products derived from\r\n*   this software without specific prior written permission.\r\n*\r\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n*******************************************************************************/\r\n\r\n/* Author: Ryu Woon Jung (Leon) */\r\n\r\n//\r\n// *********     Bulk Read and Bulk Write Example      *********\r\n//\r\n//\r\n// Available Dynamixel model on this example : All models using Protocol 2.0\r\n// This example is tested with two Dynamixel PRO 54-200, and an USB2DYNAMIXEL\r\n// Be sure that Dynamixel PRO properties are already set as %% ID : 1 and 2 / Baudnum : 1 (Baudrate : 57600)\r\n//\r\n\r\n#include <DynamixelSDK.h>\r\n\r\n// Control table address\r\n#define ADDR_PRO_TORQUE_ENABLE          562                 // Control table address is different in Dynamixel model\r\n#define ADDR_PRO_LED_RED                563\r\n#define ADDR_PRO_GOAL_POSITION          596\r\n#define ADDR_PRO_PRESENT_POSITION       611\r\n\r\n// Data Byte Length\r\n#define LEN_PRO_LED_RED                 1\r\n#define LEN_PRO_GOAL_POSITION           4\r\n#define LEN_PRO_PRESENT_POSITION        4\r\n\r\n// Protocol version\r\n#define PROTOCOL_VERSION                2.0                 // See which protocol version is used in the Dynamixel\r\n\r\n// Default setting\r\n#define DXL1_ID                         1                   // Dynamixel#1 ID: 1\r\n#define DXL2_ID                         2                   // Dynamixel#2 ID: 2\r\n#define BAUDRATE                        57600\r\n#define DEVICENAME                      \"OpenCR_DXL_Port\"   // This definition only has a symbolic meaning and does not affect to any functionality\r\n\r\n#define TORQUE_ENABLE                   1                   // Value for enabling the torque\r\n#define TORQUE_DISABLE                  0                   // Value for disabling the torque\r\n#define DXL_MINIMUM_POSITION_VALUE     -150000              // Dynamixel will rotate between this value\r\n#define DXL_MAXIMUM_POSITION_VALUE      150000              // and this value (note that the Dynamixel would not move when the position value is out of movable range. Check e-manual about the range of the Dynamixel you use.)\r\n#define DXL_MOVING_STATUS_THRESHOLD     20                  // Dynamixel moving status threshold\r\n\r\n#define ESC_ASCII_VALUE                 0x1b\r\n\r\n#define CMD_SERIAL                      Serial\r\n\r\nint getch()\r\n{\r\n  while(1)\r\n  {\r\n    if( CMD_SERIAL.available() > 0 )\r\n    {\r\n      break;\r\n    }\r\n  }\r\n\r\n  return CMD_SERIAL.read();\r\n}\r\n\r\nint kbhit(void)\r\n{\r\n  return CMD_SERIAL.available();\r\n}\r\n\r\nvoid setup()\r\n{\r\n  CMD_SERIAL.begin(115200);\r\n  while(!CMD_SERIAL);\r\n\r\n  CMD_SERIAL.println(\"Start..\");\r\n\r\n  // Initialize PortHandler instance\r\n  // Set the port path\r\n  // Get methods and members of PortHandlerLinux or PortHandlerWindows\r\n  dynamixel::PortHandler *portHandler = dynamixel::PortHandler::getPortHandler(DEVICENAME);\r\n\r\n  // Initialize PacketHandler instance\r\n  // Set the protocol version\r\n  // Get methods and members of Protocol1PacketHandler or Protocol2PacketHandler\r\n  dynamixel::PacketHandler *packetHandler = dynamixel::PacketHandler::getPacketHandler(PROTOCOL_VERSION);\r\n\r\n  // Initialize GroupBulkWrite instance\r\n  dynamixel::GroupBulkWrite groupBulkWrite(portHandler, packetHandler);\r\n\r\n  // Initialize GroupBulkRead instance\r\n  dynamixel::GroupBulkRead groupBulkRead(portHandler, packetHandler);\r\n\r\n  int index = 0;\r\n  int dxl_comm_result = COMM_TX_FAIL;             // Communication result\r\n  bool dxl_addparam_result = false;                // addParam result\r\n  //bool dxl_getdata_result = false;                 // GetParam result\r\n  int dxl_goal_position[2] = {DXL_MINIMUM_POSITION_VALUE, DXL_MAXIMUM_POSITION_VALUE};         // Goal position\r\n\r\n  uint8_t dxl_error = 0;                          // Dynamixel error\r\n  uint8_t dxl_led_value[2] = {0x00, 0xFF};        // Dynamixel LED value for write\r\n  uint8_t param_goal_position[4];\r\n  int32_t dxl1_present_position = 0;              // Present position\r\n  uint8_t dxl2_led_value_read;                    // Dynamixel LED value for read\r\n\r\n  // Open port\r\n  if (portHandler->openPort())\r\n  {\r\n    CMD_SERIAL.print(\"Succeeded to open the port!\\n\");\r\n  }\r\n  else\r\n  {\r\n    CMD_SERIAL.print(\"Failed to open the port!\\n\");\r\n    return;\r\n  }\r\n\r\n  // Set port baudrate\r\n  if (portHandler->setBaudRate(BAUDRATE))\r\n  {\r\n    CMD_SERIAL.print(\"Succeeded to change the baudrate!\\n\");\r\n  }\r\n  else\r\n  {\r\n    CMD_SERIAL.print(\"Failed to change the baudrate!\\n\");\r\n    return;\r\n  }\r\n\r\n  // Enable Dynamixel#1 Torque\r\n  dxl_comm_result = packetHandler->write1ByteTxRx(portHandler, DXL1_ID, ADDR_PRO_TORQUE_ENABLE, TORQUE_ENABLE, &dxl_error);\r\n  if (dxl_comm_result != COMM_SUCCESS)\r\n  {\r\n    CMD_SERIAL.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n  }\r\n  else if (dxl_error != 0)\r\n  {\r\n    CMD_SERIAL.print(packetHandler->getRxPacketError(dxl_error));\r\n  }\r\n  else\r\n  {\r\n    CMD_SERIAL.print(\"Dynamixel#1 has been successfully connected \\n\");\r\n  }\r\n\r\n  // Enable Dynamixel#2 Torque\r\n  dxl_comm_result = packetHandler->write1ByteTxRx(portHandler, DXL2_ID, ADDR_PRO_TORQUE_ENABLE, TORQUE_ENABLE, &dxl_error);\r\n  if (dxl_comm_result != COMM_SUCCESS)\r\n  {\r\n    CMD_SERIAL.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n  }\r\n  else if (dxl_error != 0)\r\n  {\r\n    CMD_SERIAL.print(packetHandler->getRxPacketError(dxl_error));\r\n  }\r\n  else\r\n  {\r\n    CMD_SERIAL.print(\"Dynamixel#2 has been successfully connected \\n\");\r\n  }\r\n\r\n  // Add parameter storage for Dynamixel#1 present position\r\n  dxl_addparam_result = groupBulkRead.addParam(DXL1_ID, ADDR_PRO_PRESENT_POSITION, LEN_PRO_PRESENT_POSITION);\r\n  if (dxl_addparam_result != true)\r\n  {\r\n    CMD_SERIAL.print(\"[ID:\"); CMD_SERIAL.print(DXL1_ID); CMD_SERIAL.println(\"groupBulkRead addparam failed\");\r\n    return;\r\n  }\r\n\r\n  // Add parameter storage for Dynamixel#2 LED value\r\n  dxl_addparam_result = groupBulkRead.addParam(DXL2_ID, ADDR_PRO_LED_RED, LEN_PRO_LED_RED);\r\n  if (dxl_addparam_result != true)\r\n  {\r\n    CMD_SERIAL.print(\"[ID:\"); CMD_SERIAL.print(DXL2_ID); CMD_SERIAL.println(\"groupBulkRead addparam failed\");\r\n    return;\r\n  }\r\n\r\n  while(1)\r\n  {\r\n    CMD_SERIAL.print(\"Press any key to continue! (or press q to quit!)\\n\");\r\n    if (getch() == 'q')\r\n      break;\r\n\r\n    // Allocate goal position value into byte array\r\n    param_goal_position[0] = DXL_LOBYTE(DXL_LOWORD(dxl_goal_position[index]));\r\n    param_goal_position[1] = DXL_HIBYTE(DXL_LOWORD(dxl_goal_position[index]));\r\n    param_goal_position[2] = DXL_LOBYTE(DXL_HIWORD(dxl_goal_position[index]));\r\n    param_goal_position[3] = DXL_HIBYTE(DXL_HIWORD(dxl_goal_position[index]));\r\n\r\n    // Add parameter storage for Dynamixel#1 goal position\r\n    dxl_addparam_result = groupBulkWrite.addParam(DXL1_ID, ADDR_PRO_GOAL_POSITION, LEN_PRO_GOAL_POSITION, param_goal_position);\r\n    if (dxl_addparam_result != true)\r\n    {\r\n      CMD_SERIAL.print(\"[ID:\"); CMD_SERIAL.print(DXL1_ID); CMD_SERIAL.println(\"groupBulkWrite addparam failed\");\r\n      return;\r\n    }\r\n\r\n    // Add parameter storage for Dynamixel#2 LED value\r\n    dxl_addparam_result = groupBulkWrite.addParam(DXL2_ID, ADDR_PRO_LED_RED, LEN_PRO_LED_RED, &dxl_led_value[index]);\r\n    if (dxl_addparam_result != true)\r\n    {\r\n      CMD_SERIAL.print(\"[ID:\"); CMD_SERIAL.print(DXL2_ID); CMD_SERIAL.println(\"groupBulkWrite addparam failed\");\r\n      return;\r\n    }\r\n\r\n    // Bulkwrite goal position and LED value\r\n    dxl_comm_result = groupBulkWrite.txPacket();\r\n    if (dxl_comm_result != COMM_SUCCESS) CMD_SERIAL.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n\r\n    // Clear bulkwrite parameter storage\r\n    groupBulkWrite.clearParam();\r\n\r\n    do\r\n    {\r\n      // Bulkread present position and LED status\r\n      dxl_comm_result = groupBulkRead.txRxPacket();\r\n      if (dxl_comm_result != COMM_SUCCESS) CMD_SERIAL.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n\r\n      // Check if groupbulkread data of Dynamixel#1 is available\r\n      groupBulkRead.isAvailable(DXL1_ID, ADDR_PRO_PRESENT_POSITION, LEN_PRO_PRESENT_POSITION);\r\n      if (dxl_addparam_result != true)\r\n      {\r\n        CMD_SERIAL.print(\"[ID:\"); CMD_SERIAL.print(DXL1_ID); CMD_SERIAL.println(\"groupBulkRead getdata failed\");\r\n        return;\r\n      }\r\n\r\n      // Check if groupbulkread data of Dynamixel#2 is available\r\n      groupBulkRead.isAvailable(DXL2_ID, ADDR_PRO_LED_RED, LEN_PRO_LED_RED);\r\n      if (dxl_addparam_result != true)\r\n      {\r\n        CMD_SERIAL.print(\"[ID:\"); CMD_SERIAL.print(DXL2_ID); CMD_SERIAL.println(\"groupBulkRead getdata failed\");\r\n        return;\r\n      }\r\n\r\n      // Get present position value\r\n      dxl1_present_position = groupBulkRead.getData(DXL1_ID, ADDR_PRO_PRESENT_POSITION, LEN_PRO_PRESENT_POSITION);\r\n\r\n      // Get LED value\r\n      dxl2_led_value_read = groupBulkRead.getData(DXL2_ID, ADDR_PRO_LED_RED, LEN_PRO_LED_RED);\r\n\r\n      CMD_SERIAL.print(\"[ID:\"); CMD_SERIAL.print(DXL1_ID);\r\n      CMD_SERIAL.print(\"] Present Position : \"); CMD_SERIAL.print(dxl1_present_position);\r\n      CMD_SERIAL.print(\"  [ID:\"); CMD_SERIAL.print(DXL2_ID);\r\n      CMD_SERIAL.print(\"] LED Value:\"); CMD_SERIAL.print(dxl2_led_value_read);\r\n      CMD_SERIAL.println(\" \");\r\n\r\n    }while(abs(dxl_goal_position[index] - dxl1_present_position) > DXL_MOVING_STATUS_THRESHOLD);\r\n\r\n    // Change goal position\r\n    if (index == 0)\r\n    {\r\n      index = 1;\r\n    }\r\n    else\r\n    {\r\n      index = 0;\r\n    }\r\n  }\r\n\r\n  // Disable Dynamixel#1 Torque\r\n  dxl_comm_result = packetHandler->write1ByteTxRx(portHandler, DXL1_ID, ADDR_PRO_TORQUE_ENABLE, TORQUE_DISABLE, &dxl_error);\r\n  if (dxl_comm_result != COMM_SUCCESS)\r\n  {\r\n    CMD_SERIAL.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n  }\r\n  else if (dxl_error != 0)\r\n  {\r\n    CMD_SERIAL.print(packetHandler->getRxPacketError(dxl_error));\r\n  }\r\n\r\n  // Disable Dynamixel#2 Torque\r\n  dxl_comm_result = packetHandler->write1ByteTxRx(portHandler, DXL2_ID, ADDR_PRO_TORQUE_ENABLE, TORQUE_DISABLE, &dxl_error);\r\n  if (dxl_comm_result != COMM_SUCCESS)\r\n  {\r\n    CMD_SERIAL.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n  }\r\n  else if (dxl_error != 0)\r\n  {\r\n    CMD_SERIAL.print(packetHandler->getRxPacketError(dxl_error));\r\n  }\r\n\r\n  // Close port\r\n  portHandler->closePort();\r\n}\r\n\r\nvoid loop()\r\n{\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/07. DynamixelSDK/protocol2.0/factory_reset/factory_reset.ino",
    "content": "/*******************************************************************************\r\n* Copyright (c) 2016, ROBOTIS CO., LTD.\r\n* All rights reserved.\r\n*\r\n* Redistribution and use in source and binary forms, with or without\r\n* modification, are permitted provided that the following conditions are met:\r\n*\r\n* * Redistributions of source code must retain the above copyright notice, this\r\n*   list of conditions and the following disclaimer.\r\n*\r\n* * Redistributions in binary form must reproduce the above copyright notice,\r\n*   this list of conditions and the following disclaimer in the documentation\r\n*   and/or other materials provided with the distribution.\r\n*\r\n* * Neither the name of ROBOTIS nor the names of its\r\n*   contributors may be used to endorse or promote products derived from\r\n*   this software without specific prior written permission.\r\n*\r\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n*******************************************************************************/\r\n\r\n/* Author: Ryu Woon Jung (Leon) */\r\n\r\n//\r\n// *********     Factory Reset Example      *********\r\n//\r\n//\r\n// Available Dynamixel model on this example : All models using Protocol 2.0\r\n// This example is tested with a Dynamixel PRO 54-200, and an USB2DYNAMIXEL\r\n// Be sure that Dynamixel PRO properties are already set as %% ID : 1 / Baudnum : 1 (Baudrate : 57600)\r\n//\r\n\r\n// Be aware that:\r\n// This example resets all properties of Dynamixel to default values, such as %% ID : 1 / Baudnum : 1 (Baudrate : 57600)\r\n//\r\n\r\n#include <DynamixelSDK.h>                            // Uses Dynamixel SDK library\r\n\r\n// Control table address\r\n#define ADDR_PRO_BAUDRATE               8                   // Control table address is different in Dynamixel model\r\n\r\n// Protocol version\r\n#define PROTOCOL_VERSION                2.0                 // See which protocol version is used in the Dynamixel\r\n\r\n// Default setting\r\n#define DXL_ID                          1                   // Dynamixel ID: 1\r\n#define BAUDRATE                        57600\r\n#define DEVICENAME                      \"OpenCR_DXL_Port\"   // This definition only has a symbolic meaning and does not affect to any functionality\r\n\r\n#define FACTORYRST_DEFAULTBAUDRATE      57600               // Dynamixel baudrate set by factoryreset\r\n#define NEW_BAUDNUM                     3                   // New baudnum to recover Dynamixel baudrate as it was\r\n#define OPERATION_MODE                  0x01                // 0xFF : reset all values\r\n                                                            // 0x01 : reset all values except ID\r\n                                                            // 0x02 : reset all values except ID and baudrate\r\n\r\n#define CMD_SERIAL                      Serial\r\n\r\nint getch()\r\n{\r\n  while(1)\r\n  {\r\n    if( CMD_SERIAL.available() > 0 )\r\n    {\r\n      break;\r\n    }\r\n  }\r\n\r\n  return CMD_SERIAL.read();\r\n}\r\n\r\nint kbhit(void)\r\n{\r\n  return CMD_SERIAL.available();\r\n}\r\n\r\nvoid setup()\r\n{\r\n  CMD_SERIAL.begin(115200);\r\n  while(!CMD_SERIAL);\r\n\r\n  CMD_SERIAL.println(\"Start..\");\r\n\r\n  // Initialize PortHandler instance\r\n  // Set the port path\r\n  // Get methods and members of PortHandlerLinux or PortHandlerWindows\r\n  dynamixel::PortHandler *portHandler = dynamixel::PortHandler::getPortHandler(DEVICENAME);\r\n\r\n  // Initialize PacketHandler instance\r\n  // Set the protocol version\r\n  // Get methods and members of Protocol1PacketHandler or Protocol2PacketHandler\r\n  dynamixel::PacketHandler *packetHandler = dynamixel::PacketHandler::getPacketHandler(PROTOCOL_VERSION);\r\n\r\n  int dxl_comm_result = COMM_TX_FAIL;             // Communication result\r\n\r\n  uint8_t dxl_error = 0;                          // Dynamixel error\r\n  uint8_t dxl_baudnum_read;                       // Read baudnum\r\n\r\n  // Open port\r\n  if (portHandler->openPort())\r\n  {\r\n    CMD_SERIAL.print(\"Succeeded to open the port!\\n\");\r\n  }\r\n  else\r\n  {\r\n    CMD_SERIAL.print(\"Failed to open the port!\\n\");\r\n    return;\r\n  }\r\n\r\n  // Set port baudrate\r\n  if (portHandler->setBaudRate(BAUDRATE))\r\n  {\r\n    CMD_SERIAL.print(\"Succeeded to change the baudrate!\\n\");\r\n  }\r\n  else\r\n  {\r\n    CMD_SERIAL.print(\"Failed to change the baudrate!\\n\");\r\n    return;\r\n  }\r\n\r\n  // Read present baudrate of the controller\r\n  CMD_SERIAL.print(\"Now the controller baudrate is :\");\r\n  CMD_SERIAL.print(portHandler->getBaudRate());\r\n\r\n  // Try factoryreset\r\n  CMD_SERIAL.print(\"[ID:\"); CMD_SERIAL.print(DXL_ID);\r\n  CMD_SERIAL.print(\"] Try factoryreset : \");\r\n\r\n  dxl_comm_result = packetHandler->factoryReset(portHandler, DXL_ID, OPERATION_MODE, &dxl_error);\r\n  if (dxl_comm_result != COMM_SUCCESS)\r\n  {\r\n    CMD_SERIAL.print(\"Aborted\\n\");\r\n    CMD_SERIAL.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n    return;\r\n  }\r\n  else if (dxl_error != 0)\r\n  {\r\n    CMD_SERIAL.print(packetHandler->getRxPacketError(dxl_error));\r\n  }\r\n\r\n  // Wait for reset\r\n  CMD_SERIAL.print(\"Wait for reset...\\n\");\r\n  delay(2000);\r\n\r\n  CMD_SERIAL.print(\"[ID:\"); CMD_SERIAL.print(DXL_ID);\r\n  CMD_SERIAL.print(\"] factoryReset Success!\\n\");\r\n\r\n  // Set controller baudrate to Dynamixel default baudrate\r\n  if (portHandler->setBaudRate(FACTORYRST_DEFAULTBAUDRATE))\r\n  {\r\n    CMD_SERIAL.print(\"Succeed to change the controller baudrate to : \");\r\n    CMD_SERIAL.println(FACTORYRST_DEFAULTBAUDRATE);\r\n  }\r\n  else\r\n  {\r\n    CMD_SERIAL.print(\"Failed to change the controller baudrate\\n\");\r\n    return;\r\n  }\r\n\r\n  // Read Dynamixel baudnum\r\n  dxl_comm_result = packetHandler->read1ByteTxRx(portHandler, DXL_ID, ADDR_PRO_BAUDRATE, &dxl_baudnum_read, &dxl_error);\r\n  if (dxl_comm_result != COMM_SUCCESS)\r\n  {\r\n    CMD_SERIAL.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n  }\r\n  else if (dxl_error != 0)\r\n  {\r\n    CMD_SERIAL.print(packetHandler->getRxPacketError(dxl_error));\r\n  }\r\n  else\r\n  {\r\n    CMD_SERIAL.print(\"[ID:\"); CMD_SERIAL.print(DXL_ID);\r\n    CMD_SERIAL.print(\"] DXL baudnum is now : \");\r\n    CMD_SERIAL.println(dxl_baudnum_read);\r\n  }\r\n\r\n  // Write new baudnum\r\n  dxl_comm_result = packetHandler->write1ByteTxRx(portHandler, DXL_ID, ADDR_PRO_BAUDRATE, NEW_BAUDNUM, &dxl_error);\r\n  if (dxl_comm_result != COMM_SUCCESS)\r\n  {\r\n    CMD_SERIAL.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n  }\r\n  else if (dxl_error != 0)\r\n  {\r\n    CMD_SERIAL.print(packetHandler->getRxPacketError(dxl_error));\r\n  }\r\n  else\r\n  {\r\n    CMD_SERIAL.print(\"[ID:\"); CMD_SERIAL.print(DXL_ID);\r\n    CMD_SERIAL.print(\"] Set Dynamixel baudnum to : \");\r\n    CMD_SERIAL.println(NEW_BAUDNUM);\r\n  }\r\n\r\n  // Set port baudrate to BAUDRATE\r\n  if (portHandler->setBaudRate(BAUDRATE))\r\n  {\r\n    CMD_SERIAL.print(\"Succeed to change the controller baudrate to : \");\r\n    CMD_SERIAL.println(BAUDRATE);\r\n  }\r\n  else\r\n  {\r\n    CMD_SERIAL.print(\"Failed to change the controller baudrate\\n\");\r\n    return;\r\n  }\r\n\r\n  delay(200);\r\n\r\n  // Read Dynamixel baudnum\r\n  dxl_comm_result = packetHandler->read1ByteTxRx(portHandler, DXL_ID, ADDR_PRO_BAUDRATE, &dxl_baudnum_read, &dxl_error);\r\n  if (dxl_comm_result != COMM_SUCCESS)\r\n  {\r\n    CMD_SERIAL.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n  }\r\n  else if (dxl_error != 0)\r\n  {\r\n    CMD_SERIAL.print(packetHandler->getRxPacketError(dxl_error));\r\n  }\r\n  else\r\n  {\r\n    CMD_SERIAL.print(\"[ID:\"); CMD_SERIAL.print(DXL_ID);\r\n    CMD_SERIAL.print(\"] Dynamixel Baudnum is now : \");\r\n    CMD_SERIAL.print(dxl_baudnum_read);\r\n  }\r\n\r\n  // Close port\r\n  portHandler->closePort();\r\n\r\n  return;\r\n}\r\n\r\nvoid loop()\r\n{\r\n  \r\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/07. DynamixelSDK/protocol2.0/indirect_address/indirect_address.ino",
    "content": "/*******************************************************************************\r\n* Copyright (c) 2016, ROBOTIS CO., LTD.\r\n* All rights reserved.\r\n*\r\n* Redistribution and use in source and binary forms, with or without\r\n* modification, are permitted provided that the following conditions are met:\r\n*\r\n* * Redistributions of source code must retain the above copyright notice, this\r\n*   list of conditions and the following disclaimer.\r\n*\r\n* * Redistributions in binary form must reproduce the above copyright notice,\r\n*   this list of conditions and the following disclaimer in the documentation\r\n*   and/or other materials provided with the distribution.\r\n*\r\n* * Neither the name of ROBOTIS nor the names of its\r\n*   contributors may be used to endorse or promote products derived from\r\n*   this software without specific prior written permission.\r\n*\r\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n*******************************************************************************/\r\n\r\n/* Author: Ryu Woon Jung (Leon) */\r\n\r\n//\r\n// *********     Indirect Address Example      *********\r\n//\r\n//\r\n// Available Dynamixel model on this example : All models using Protocol 2.0\r\n// This example is tested with a Dynamixel PRO 54-200, and an USB2DYNAMIXEL\r\n// Be sure that Dynamixel PRO properties are already set as %% ID : 1 / Baudnum : 1 (Baudrate : 57600)\r\n//\r\n\r\n#include <DynamixelSDK.h>\r\n\r\n\r\n// Control table address\r\n// Control table address is different in Dynamixel model\r\n#define ADDR_PRO_INDIRECTADDRESS_FOR_WRITE      49                  // EEPROM region\r\n#define ADDR_PRO_INDIRECTADDRESS_FOR_READ       59                  // EEPROM region\r\n#define ADDR_PRO_TORQUE_ENABLE                  562\r\n#define ADDR_PRO_LED_RED                        563\r\n#define ADDR_PRO_GOAL_POSITION                  596\r\n#define ADDR_PRO_MOVING                         610\r\n#define ADDR_PRO_PRESENT_POSITION               611\r\n#define ADDR_PRO_INDIRECTDATA_FOR_WRITE         634\r\n#define ADDR_PRO_INDIRECTDATA_FOR_READ          639\r\n\r\n// Data Byte Length\r\n#define LEN_PRO_LED_RED                         1\r\n#define LEN_PRO_GOAL_POSITION                   4\r\n#define LEN_PRO_MOVING                          1\r\n#define LEN_PRO_PRESENT_POSITION                4\r\n#define LEN_PRO_INDIRECTDATA_FOR_WRITE          5\r\n#define LEN_PRO_INDIRECTDATA_FOR_READ           5\r\n\r\n// Protocol version\r\n#define PROTOCOL_VERSION                        2.0                 // See which protocol version is used in the Dynamixel\r\n\r\n// Default setting\r\n#define DXL_ID                                  1                   // Dynamixel ID: 1\r\n#define BAUDRATE                                57600\r\n#define DEVICENAME                              \"OpenCR_DXL_Port\"   // This definition only has a symbolic meaning and does not affect to any functionality\r\n\r\n#define TORQUE_ENABLE                           1                   // Value for enabling the torque\r\n#define TORQUE_DISABLE                          0                   // Value for disabling the torque\r\n#define DXL_MINIMUM_POSITION_VALUE             -150000              // Dynamixel will rotate between this value\r\n#define DXL_MAXIMUM_POSITION_VALUE              150000              // and this value (note that the Dynamixel would not move when the position value is out of movable range. Check e-manual about the range of the Dynamixel you use.)\r\n#define DXL_MINIMUM_LED_VALUE                   0                   // Dynamixel LED will light between this value\r\n#define DXL_MAXIMUM_LED_VALUE                   255                 // and this value\r\n#define DXL_MOVING_STATUS_THRESHOLD             20                  // Dynamixel moving status threshold\r\n\r\n#define ESC_ASCII_VALUE                         0x1b\r\n\r\n#define CMD_SERIAL                              Serial\r\n\r\nint getch()\r\n{\r\n  while(1)\r\n  {\r\n    if( CMD_SERIAL.available() > 0 )\r\n    {\r\n      break;\r\n    }\r\n  }\r\n\r\n  return CMD_SERIAL.read();\r\n}\r\n\r\nint kbhit(void)\r\n{\r\n  return CMD_SERIAL.available();\r\n}\r\n\r\nvoid setup()\r\n{\r\n  Serial.begin(115200);\r\n  while(!Serial);\r\n\r\n  Serial.println(\"Start..\");\r\n\r\n  // Initialize PortHandler instance\r\n  // Set the port path\r\n  // Get methods and members of PortHandlerLinux or PortHandlerWindows\r\n  dynamixel::PortHandler *portHandler = dynamixel::PortHandler::getPortHandler(DEVICENAME);\r\n\r\n  // Initialize PacketHandler instance\r\n  // Set the protocol version\r\n  // Get methods and members of Protocol1PacketHandler or Protocol2PacketHandler\r\n  dynamixel::PacketHandler *packetHandler = dynamixel::PacketHandler::getPacketHandler(PROTOCOL_VERSION);\r\n\r\n  // Initialize GroupSyncWrite instance\r\n  dynamixel::GroupSyncWrite groupSyncWrite(portHandler, packetHandler, ADDR_PRO_INDIRECTDATA_FOR_WRITE, LEN_PRO_INDIRECTDATA_FOR_WRITE);\r\n\r\n  // Initialize Groupsyncread instance\r\n  dynamixel::GroupSyncRead groupSyncRead(portHandler, packetHandler, ADDR_PRO_INDIRECTDATA_FOR_READ, LEN_PRO_INDIRECTDATA_FOR_READ);\r\n\r\n  int index = 0;\r\n  int dxl_comm_result = COMM_TX_FAIL;             // Communication result\r\n  bool dxl_addparam_result = false;               // addParam result\r\n  bool dxl_getdata_result = false;                // GetParam result\r\n  int dxl_goal_position[2] = {DXL_MINIMUM_POSITION_VALUE, DXL_MAXIMUM_POSITION_VALUE};  // Goal position\r\n\r\n  uint8_t dxl_error = 0;                          // Dynamixel error\r\n  uint8_t dxl_moving = 0;                         // Dynamixel moving status\r\n  uint8_t param_indirect_data_for_write[LEN_PRO_INDIRECTDATA_FOR_WRITE];\r\n  uint8_t dxl_led_value[2] = {0x00, 0xFF};        // Dynamixel LED value\r\n  int32_t dxl_present_position = 0;               // Present position\r\n\r\n  // Open port\r\n  if (portHandler->openPort())\r\n  {\r\n    Serial.print(\"Succeeded to open the port!\\n\");\r\n  }\r\n  else\r\n  {\r\n    Serial.print(\"Failed to open the port!\\n\");\r\n    return;\r\n  }\r\n\r\n  // Set port baudrate\r\n  if (portHandler->setBaudRate(BAUDRATE))\r\n  {\r\n    Serial.print(\"Succeeded to change the baudrate!\\n\");\r\n  }\r\n  else\r\n  {\r\n    Serial.print(\"Failed to change the baudrate!\\n\");\r\n    return;\r\n  }\r\n\r\n  // Disable Dynamixel Torque :\r\n  // Indirect address would not accessible when the torque is already enabled\r\n  dxl_comm_result = packetHandler->write1ByteTxRx(portHandler, DXL_ID, ADDR_PRO_TORQUE_ENABLE, TORQUE_DISABLE, &dxl_error);\r\n  if (dxl_comm_result != COMM_SUCCESS)\r\n  {\r\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n  }\r\n  else if (dxl_error != 0)\r\n  {\r\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\r\n  }\r\n  else\r\n  {\r\n    Serial.print(\"Dynamixel has been successfully connected \\n\");\r\n  }\r\n\r\n  // INDIRECTDATA parameter storages replace LED, goal position, present position and moving status storages\r\n  dxl_comm_result = packetHandler->write2ByteTxRx(portHandler, DXL_ID, ADDR_PRO_INDIRECTADDRESS_FOR_WRITE + 0, ADDR_PRO_GOAL_POSITION + 0, &dxl_error);\r\n  if (dxl_comm_result != COMM_SUCCESS)\r\n  {\r\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n  }\r\n  else if (dxl_error != 0)\r\n  {\r\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\r\n  }\r\n\r\n  dxl_comm_result = packetHandler->write2ByteTxRx(portHandler, DXL_ID, ADDR_PRO_INDIRECTADDRESS_FOR_WRITE + 2, ADDR_PRO_GOAL_POSITION + 1, &dxl_error);\r\n  if (dxl_comm_result != COMM_SUCCESS)\r\n  {\r\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n  }\r\n  else if (dxl_error != 0)\r\n  {\r\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\r\n  }\r\n\r\n  dxl_comm_result = packetHandler->write2ByteTxRx(portHandler, DXL_ID, ADDR_PRO_INDIRECTADDRESS_FOR_WRITE + 4, ADDR_PRO_GOAL_POSITION + 2, &dxl_error);\r\n  if (dxl_comm_result != COMM_SUCCESS)\r\n  {\r\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n  }\r\n  else if (dxl_error != 0)\r\n  {\r\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\r\n  }\r\n\r\n  dxl_comm_result = packetHandler->write2ByteTxRx(portHandler, DXL_ID, ADDR_PRO_INDIRECTADDRESS_FOR_WRITE + 6, ADDR_PRO_GOAL_POSITION + 3, &dxl_error);\r\n  if (dxl_comm_result != COMM_SUCCESS)\r\n  {\r\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n  }\r\n  else if (dxl_error != 0)\r\n  {\r\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\r\n  }\r\n\r\n  dxl_comm_result = packetHandler->write2ByteTxRx(portHandler, DXL_ID, ADDR_PRO_INDIRECTADDRESS_FOR_WRITE + 8, ADDR_PRO_LED_RED, &dxl_error);\r\n  if (dxl_comm_result != COMM_SUCCESS)\r\n  {\r\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n  }\r\n  else if (dxl_error != 0)\r\n  {\r\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\r\n  }\r\n\r\n  dxl_comm_result = packetHandler->write2ByteTxRx(portHandler, DXL_ID, ADDR_PRO_INDIRECTADDRESS_FOR_READ + 0, ADDR_PRO_PRESENT_POSITION + 0, &dxl_error);\r\n  if (dxl_comm_result != COMM_SUCCESS)\r\n  {\r\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n  }\r\n  else if (dxl_error != 0)\r\n  {\r\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\r\n  }\r\n\r\n  dxl_comm_result = packetHandler->write2ByteTxRx(portHandler, DXL_ID, ADDR_PRO_INDIRECTADDRESS_FOR_READ + 2, ADDR_PRO_PRESENT_POSITION + 1, &dxl_error);\r\n  if (dxl_comm_result != COMM_SUCCESS)\r\n  {\r\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n  }\r\n  else if (dxl_error != 0)\r\n  {\r\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\r\n  }\r\n\r\n  dxl_comm_result = packetHandler->write2ByteTxRx(portHandler, DXL_ID, ADDR_PRO_INDIRECTADDRESS_FOR_READ + 4, ADDR_PRO_PRESENT_POSITION + 2, &dxl_error);\r\n  if (dxl_comm_result != COMM_SUCCESS)\r\n  {\r\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n  }\r\n  else if (dxl_error != 0)\r\n  {\r\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\r\n  }\r\n\r\n  dxl_comm_result = packetHandler->write2ByteTxRx(portHandler, DXL_ID, ADDR_PRO_INDIRECTADDRESS_FOR_READ + 6, ADDR_PRO_PRESENT_POSITION + 3, &dxl_error);\r\n  if (dxl_comm_result != COMM_SUCCESS)\r\n  {\r\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n  }\r\n  else if (dxl_error != 0)\r\n  {\r\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\r\n  }\r\n\r\n  dxl_comm_result = packetHandler->write2ByteTxRx(portHandler, DXL_ID, ADDR_PRO_INDIRECTADDRESS_FOR_READ + 8, ADDR_PRO_MOVING, &dxl_error);\r\n  if (dxl_comm_result != COMM_SUCCESS)\r\n  {\r\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n  }\r\n  else if (dxl_error != 0)\r\n  {\r\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\r\n  }\r\n\r\n  // Enable Dynamixel Torque\r\n  dxl_comm_result = packetHandler->write1ByteTxRx(portHandler, DXL_ID, ADDR_PRO_TORQUE_ENABLE, TORQUE_ENABLE, &dxl_error);\r\n  if (dxl_comm_result != COMM_SUCCESS)\r\n  {\r\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n  }\r\n  else if (dxl_error != 0)\r\n  {\r\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\r\n  }\r\n\r\n  // Add parameter storage for the present position value\r\n  dxl_addparam_result = groupSyncRead.addParam(DXL_ID);\r\n  if (dxl_addparam_result != true)\r\n  {\r\n    Serial.print(\"[ID:\"); Serial.print(DXL_ID); Serial.println(\"groupSyncRead addparam failed\");\r\n    return;\r\n  }\r\n\r\n  while(1)\r\n  {\r\n    Serial.print(\"Press any key to continue! (or press q to quit!)\\n\");\r\n    if (getch() == 'q')\r\n      break;\r\n\r\n    // Allocate LED and goal position value into byte array\r\n    param_indirect_data_for_write[0] = DXL_LOBYTE(DXL_LOWORD(dxl_goal_position[index]));\r\n    param_indirect_data_for_write[1] = DXL_HIBYTE(DXL_LOWORD(dxl_goal_position[index]));\r\n    param_indirect_data_for_write[2] = DXL_LOBYTE(DXL_HIWORD(dxl_goal_position[index]));\r\n    param_indirect_data_for_write[3] = DXL_HIBYTE(DXL_HIWORD(dxl_goal_position[index]));\r\n    param_indirect_data_for_write[4] = dxl_led_value[index];\r\n\r\n    // Add values to the Syncwrite storage\r\n    dxl_addparam_result = groupSyncWrite.addParam(DXL_ID, param_indirect_data_for_write);\r\n    if (dxl_addparam_result != true)\r\n    {\r\n      Serial.print(\"[ID:\"); Serial.print(DXL_ID); Serial.println(\"groupSyncWrite addparam failed\");\r\n      return;\r\n    }\r\n\r\n    // Syncwrite all\r\n    dxl_comm_result = groupSyncWrite.txPacket();\r\n    if (dxl_comm_result != COMM_SUCCESS) Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n\r\n    // Clear syncwrite parameter storage\r\n    groupSyncWrite.clearParam();\r\n\r\n    do\r\n    {\r\n      // Syncread present position from indirectdata2\r\n      dxl_comm_result = groupSyncRead.txRxPacket();\r\n      if (dxl_comm_result != COMM_SUCCESS) Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n\r\n      // Check if groupsyncread data of Dyanamixel is available\r\n      dxl_getdata_result = groupSyncRead.isAvailable(DXL_ID, ADDR_PRO_INDIRECTDATA_FOR_READ, LEN_PRO_PRESENT_POSITION);\r\n      if (dxl_getdata_result != true)\r\n      {\r\n        Serial.print(\"[ID:\"); Serial.print(DXL_ID); Serial.println(\"groupSyncRead getdata failed\");\r\n        return;\r\n      }\r\n\r\n      // Check if groupsyncread data of Dyanamixel is available\r\n      dxl_getdata_result = groupSyncRead.isAvailable(DXL_ID, ADDR_PRO_INDIRECTDATA_FOR_READ + LEN_PRO_PRESENT_POSITION, LEN_PRO_MOVING);\r\n      if (dxl_getdata_result != true)\r\n      {\r\n        Serial.print(\"[ID:\"); Serial.print(DXL_ID); Serial.println(\"groupSyncRead getdata failed\");\r\n        return;\r\n      }\r\n\r\n      // Get Dynamixel present position value\r\n      dxl_present_position = groupSyncRead.getData(DXL_ID, ADDR_PRO_INDIRECTDATA_FOR_READ, LEN_PRO_PRESENT_POSITION);\r\n\r\n      // Get Dynamixel moving status value\r\n      dxl_moving = groupSyncRead.getData(DXL_ID, ADDR_PRO_INDIRECTDATA_FOR_READ + LEN_PRO_PRESENT_POSITION, LEN_PRO_MOVING);\r\n\r\n      Serial.print(\"[ID:\"); Serial.print(DXL_ID);\r\n      Serial.print(\"] GoalPos:\"); Serial.print(dxl_goal_position[index]);\r\n      Serial.print(\"  PresPos:\"); Serial.print(dxl_present_position);\r\n      Serial.print(\"  IsMoving:\"); Serial.print(dxl_moving);\r\n      Serial.println(\" \");\r\n\r\n    }while(abs(dxl_goal_position[index] - dxl_present_position) > DXL_MOVING_STATUS_THRESHOLD);\r\n\r\n    // Change goal position\r\n    if (index == 0)\r\n    {\r\n      index = 1;\r\n    }\r\n    else\r\n    {\r\n      index = 0;\r\n    }\r\n  }\r\n\r\n  // Disable Dynamixel Torque\r\n  dxl_comm_result = packetHandler->write1ByteTxRx(portHandler, DXL_ID, ADDR_PRO_TORQUE_ENABLE, TORQUE_DISABLE, &dxl_error);\r\n  if (dxl_comm_result != COMM_SUCCESS)\r\n  {\r\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n  }\r\n  else if (dxl_error != 0)\r\n  {\r\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\r\n  }\r\n\r\n  // Close port\r\n  portHandler->closePort();\r\n\r\n  return;\r\n}\r\n\r\nvoid loop()\r\n{\r\n  \r\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/07. DynamixelSDK/protocol2.0/ping/ping.ino",
    "content": "/*******************************************************************************\n* Copyright (c) 2016, ROBOTIS CO., LTD.\n* All rights reserved.\n*\n* Redistribution and use in source and binary forms, with or without\n* modification, are permitted provided that the following conditions are met:\n*\n* * Redistributions of source code must retain the above copyright notice, this\n*   list of conditions and the following disclaimer.\n*\n* * Redistributions in binary form must reproduce the above copyright notice,\n*   this list of conditions and the following disclaimer in the documentation\n*   and/or other materials provided with the distribution.\n*\n* * Neither the name of ROBOTIS nor the names of its\n*   contributors may be used to endorse or promote products derived from\n*   this software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*******************************************************************************/\n\n/* Author: Ryu Woon Jung (Leon) */\n\n//\n// *********     ping Example      *********\n//\n//\n// Available Dynamixel model on this example : All models using Protocol 2.0\n// This example is tested with a Dynamixel PRO 54-200, and an USB2DYNAMIXEL\n// Be sure that Dynamixel PRO properties are already set as %% ID : 1 / Baudnum : 1 (Baudrate : 57600)\n//\n\n#include <DynamixelSDK.h>\n\n\n// Protocol version\n#define PROTOCOL_VERSION                2.0                 // See which protocol version is used in the Dynamixel\n\n// Default setting\n#define DXL_ID                          1                   // Dynamixel ID: 1\n#define BAUDRATE                        57600\n#define DEVICENAME                      \"OpenCR_DXL_Port\"   // This definition only has a symbolic meaning and does not affect to any functionality\n\n\n\nvoid setup()\n{\n  Serial.begin(115200);\n  while(!Serial);\n\n  Serial.println(\"Start..\");\n\n  // Initialize PortHandler instance\n  // Set the port path\n  // Get methods and members of PortHandlerLinux or PortHandlerWindows\n  dynamixel::PortHandler *portHandler = dynamixel::PortHandler::getPortHandler(DEVICENAME);\n\n  // Initialize PacketHandler instance\n  // Set the protocol version\n  // Get methods and members of Protocol1PacketHandler or Protocol2PacketHandler\n  dynamixel::PacketHandler *packetHandler = dynamixel::PacketHandler::getPacketHandler(PROTOCOL_VERSION);\n\n  int dxl_comm_result = COMM_TX_FAIL;             // Communication result\n\n  uint8_t dxl_error = 0;                          // Dynamixel error\n  uint16_t dxl_model_number;                      // Dynamixel model number\n\n  // Open port\n  if (portHandler->openPort())\n  {\n    Serial.print(\"Succeeded to open the port!\\n\");\n  }\n  else\n  {\n    Serial.print(\"Failed to open the port!\\n\");\n    return;\n  }\n\n  // Set port baudrate\n  if (portHandler->setBaudRate(BAUDRATE))\n  {\n    Serial.print(\"Succeeded to change the baudrate!\\n\");\n  }\n  else\n  {\n    Serial.print(\"Failed to change the baudrate!\\n\");\n    return;\n  }\n\n  // Try to ping the Dynamixel\n  // Get Dynamixel model number\n  dxl_comm_result = packetHandler->ping(portHandler, DXL_ID, &dxl_model_number, &dxl_error);\n  if (dxl_comm_result != COMM_SUCCESS)\n  {\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\n  }\n  else if (dxl_error != 0)\n  {\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\n  }\n\n  Serial.print(\"[ID:\"); Serial.print(DXL_ID);\n  Serial.print(\"] ping Succeeded. Dynamixel model number : \");\n  Serial.println(dxl_model_number);\n\n  // Close port\n  portHandler->closePort();\n}\n\nvoid loop()\n{\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/07. DynamixelSDK/protocol2.0/read_write/read_write.ino",
    "content": "/*******************************************************************************\n* Copyright (c) 2016, ROBOTIS CO., LTD.\n* All rights reserved.\n*\n* Redistribution and use in source and binary forms, with or without\n* modification, are permitted provided that the following conditions are met:\n*\n* * Redistributions of source code must retain the above copyright notice, this\n*   list of conditions and the following disclaimer.\n*\n* * Redistributions in binary form must reproduce the above copyright notice,\n*   this list of conditions and the following disclaimer in the documentation\n*   and/or other materials provided with the distribution.\n*\n* * Neither the name of ROBOTIS nor the names of its\n*   contributors may be used to endorse or promote products derived from\n*   this software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*******************************************************************************/\n\n/* Author: Ryu Woon Jung (Leon) */\n\n//\n// *********     Read and Write Example      *********\n//\n//\n// Available Dynamixel model on this example : All models using Protocol 2.0\n// This example is tested with a Dynamixel PRO 54-200, and an USB2DYNAMIXEL\n// Be sure that Dynamixel PRO properties are already set as %% ID : 1 / Baudnum : 1 (Baudrate : 57600)\n//\n\n#include <DynamixelSDK.h>\n\n\n// Control table address\n#define ADDR_PRO_TORQUE_ENABLE          562                 // Control table address is different in Dynamixel model\n#define ADDR_PRO_GOAL_POSITION          596\n#define ADDR_PRO_PRESENT_POSITION       611\n\n// Protocol version\n#define PROTOCOL_VERSION                2.0                 // See which protocol version is used in the Dynamixel\n\n// Default setting\n#define DXL_ID                          1                   // Dynamixel ID: 1\n#define BAUDRATE                        57600\n#define DEVICENAME                      \"OpenCR_DXL_Port\"   // This definition only has a symbolic meaning and does not affect to any functionality\n\n#define TORQUE_ENABLE                   1                   // Value for enabling the torque\n#define TORQUE_DISABLE                  0                   // Value for disabling the torque\n#define DXL_MINIMUM_POSITION_VALUE     -150000              // Dynamixel will rotate between this value\n#define DXL_MAXIMUM_POSITION_VALUE      150000              // and this value (note that the Dynamixel would not move when the position value is out of movable range. Check e-manual about the range of the Dynamixel you use.)\n#define DXL_MOVING_STATUS_THRESHOLD     20                  // Dynamixel moving status threshold\n\n#define ESC_ASCII_VALUE                 0x1b\n\n#define CMD_SERIAL                      Serial\n\nint getch()\n{\n  while(1)\n  {\n    if( CMD_SERIAL.available() > 0 )\n    {\n      break;\n    }\n  }\n\n  return CMD_SERIAL.read();\n}\n\nint kbhit(void)\n{\n  return CMD_SERIAL.available();\n}\n\nvoid setup()\n{\n  Serial.begin(115200);\n  while(!Serial);\n\n  Serial.println(\"Start..\");\n\n  // Initialize PortHandler instance\n  // Set the port path\n  // Get methods and members of PortHandlerLinux or PortHandlerWindows\n  dynamixel::PortHandler *portHandler = dynamixel::PortHandler::getPortHandler(DEVICENAME);\n\n  // Initialize PacketHandler instance\n  // Set the protocol version\n  // Get methods and members of Protocol1PacketHandler or Protocol2PacketHandler\n  dynamixel::PacketHandler *packetHandler = dynamixel::PacketHandler::getPacketHandler(PROTOCOL_VERSION);\n\n  int index = 0;\n  int dxl_comm_result = COMM_TX_FAIL;             // Communication result\n  int dxl_goal_position[2] = {DXL_MINIMUM_POSITION_VALUE, DXL_MAXIMUM_POSITION_VALUE};         // Goal position\n\n  uint8_t dxl_error = 0;                          // Dynamixel error\n  int32_t dxl_present_position = 0;               // Present position\n\n  // Open port\n  if (portHandler->openPort())\n  {\n    Serial.print(\"Succeeded to open the port!\\n\");\n  }\n  else\n  {\n    Serial.print(\"Failed to open the port!\\n\");\n    return;\n  }\n\n  // Set port baudrate\n  if (portHandler->setBaudRate(BAUDRATE))\n  {\n    Serial.print(\"Succeeded to change the baudrate!\\n\");\n  }\n  else\n  {\n    Serial.print(\"Failed to change the baudrate!\\n\");\n    return;\n  }\n\n  // Enable Dynamixel Torque\n  dxl_comm_result = packetHandler->write1ByteTxRx(portHandler, DXL_ID, ADDR_PRO_TORQUE_ENABLE, TORQUE_ENABLE, &dxl_error);\n  if (dxl_comm_result != COMM_SUCCESS)\n  {\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\n  }\n  else if (dxl_error != 0)\n  {\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\n  }\n  else\n  {\n    Serial.print(\"Dynamixel has been successfully connected \\n\");\n  }\n\n  while(1)\n  {\n    Serial.print(\"Press any key to continue! (or press q to quit!)\\n\");\n    if (getch() == 'q')\n      break;\n\n    // Write goal position\n    dxl_comm_result = packetHandler->write4ByteTxRx(portHandler, DXL_ID, ADDR_PRO_GOAL_POSITION, dxl_goal_position[index], &dxl_error);\n    if (dxl_comm_result != COMM_SUCCESS)\n    {\n      Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\n    }\n    else if (dxl_error != 0)\n    {\n      Serial.print(packetHandler->getRxPacketError(dxl_error));\n    }\n\n    do\n    {\n      // Read present position\n      dxl_comm_result = packetHandler->read4ByteTxRx(portHandler, DXL_ID, ADDR_PRO_PRESENT_POSITION, (uint32_t*)&dxl_present_position, &dxl_error);\n      if (dxl_comm_result != COMM_SUCCESS)\n      {\n        Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\n      }\n      else if (dxl_error != 0)\n      {\n        Serial.print(packetHandler->getRxPacketError(dxl_error));\n      }\n\n      Serial.print(\"[ID:\"); Serial.print(DXL_ID);\n      Serial.print(\"] GoalPos:\"); Serial.print(dxl_goal_position[index]);\n      Serial.print(\"  PresPos:\"); Serial.print(dxl_present_position);\n      Serial.println(\" \");\n\n    }while((abs(dxl_goal_position[index] - dxl_present_position) > DXL_MOVING_STATUS_THRESHOLD));\n\n    // Change goal position\n    if (index == 0)\n    {\n      index = 1;\n    }\n    else\n    {\n      index = 0;\n    }\n  }\n\n  // Disable Dynamixel Torque\n  dxl_comm_result = packetHandler->write1ByteTxRx(portHandler, DXL_ID, ADDR_PRO_TORQUE_ENABLE, TORQUE_DISABLE, &dxl_error);\n  if (dxl_comm_result != COMM_SUCCESS)\n  {\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\n  }\n  else if (dxl_error != 0)\n  {\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\n  }\n\n  // Close port\n  portHandler->closePort();\n}\n\nvoid loop()\n{\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/07. DynamixelSDK/protocol2.0/reboot/reboot.ino",
    "content": "/*******************************************************************************\r\n* Copyright (c) 2016, ROBOTIS CO., LTD.\r\n* All rights reserved.\r\n*\r\n* Redistribution and use in source and binary forms, with or without\r\n* modification, are permitted provided that the following conditions are met:\r\n*\r\n* * Redistributions of source code must retain the above copyright notice, this\r\n*   list of conditions and the following disclaimer.\r\n*\r\n* * Redistributions in binary form must reproduce the above copyright notice,\r\n*   this list of conditions and the following disclaimer in the documentation\r\n*   and/or other materials provided with the distribution.\r\n*\r\n* * Neither the name of ROBOTIS nor the names of its\r\n*   contributors may be used to endorse or promote products derived from\r\n*   this software without specific prior written permission.\r\n*\r\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n*******************************************************************************/\r\n\r\n/* Author: Ryu Woon Jung (Leon) */\r\n\r\n//\r\n// *********     reboot Example      *********\r\n//\r\n//\r\n// Available Dynamixel model on this example : All models using Protocol 2.0\r\n// This example is tested with a Dynamixel PRO 54-200, and USB2DYNAMIXEL\r\n// Be sure that Dynamixel PRO properties are already set as %% ID : 1 / Baudnum : 1 (Baudrate : 57600)\r\n//\r\n\r\n#include <DynamixelSDK.h>\r\n\r\n\r\n// Protocol version\r\n#define PROTOCOL_VERSION                2.0                 // See which protocol version is used in the Dynamixel\r\n\r\n// Default setting\r\n#define DXL_ID                          1                   // Dynamixel ID: 1\r\n#define BAUDRATE                        57600\r\n#define DEVICENAME                      \"OpenCR_DXL_Port\"   // This definition only has a symbolic meaning and does not affect to any functionality\r\n\r\n#define CMD_SERIAL                      Serial\r\n\r\nint getch()\r\n{\r\n  while(1)\r\n  {\r\n    if( CMD_SERIAL.available() > 0 )\r\n    {\r\n      break;\r\n    }\r\n  }\r\n\r\n  return CMD_SERIAL.read();\r\n}\r\n\r\nint kbhit(void)\r\n{\r\n  return CMD_SERIAL.available();\r\n}\r\n\r\nvoid setup()\r\n{\r\n  Serial.begin(115200);\r\n  while(!Serial);\r\n\r\n  Serial.println(\"Start..\");\r\n\r\n  // Initialize PortHandler instance\r\n  // Set the port path\r\n  // Get methods and members of PortHandlerLinux or PortHandlerWindows\r\n  dynamixel::PortHandler *portHandler = dynamixel::PortHandler::getPortHandler(DEVICENAME);\r\n\r\n  // Initialize PacketHandler instance\r\n  // Set the protocol version\r\n  // Get methods and members of Protocol1PacketHandler or Protocol2PacketHandler\r\n  dynamixel::PacketHandler *packetHandler = dynamixel::PacketHandler::getPacketHandler(PROTOCOL_VERSION);\r\n\r\n  int dxl_comm_result = COMM_TX_FAIL;             // Communication result\r\n\r\n  uint8_t dxl_error = 0;                          // Dynamixel error\r\n\r\n  // Open port\r\n  if (portHandler->openPort())\r\n  {\r\n    Serial.print(\"Succeeded to open the port!\\n\");\r\n  }\r\n  else\r\n  {\r\n    Serial.print(\"Failed to open the port!\\n\");\r\n    return;\r\n  }\r\n\r\n  // Set port baudrate\r\n  if (portHandler->setBaudRate(BAUDRATE))\r\n  {\r\n    Serial.print(\"Succeeded to change the baudrate!\\n\");\r\n  }\r\n  else\r\n  {\r\n    Serial.print(\"Failed to change the baudrate!\\n\");\r\n    return;\r\n  }\r\n\r\n  // Trigger\r\n  Serial.print(\"Press any key to reboot\\n\");\r\n  getch();\r\n\r\n  Serial.print(\"See the Dynamixel LED flickering\\n\");\r\n  // Try reboot\r\n  // Dynamixel LED will flicker while it reboots\r\n  dxl_comm_result = packetHandler->reboot(portHandler, DXL_ID, &dxl_error);\r\n  if (dxl_comm_result != COMM_SUCCESS)\r\n  {\r\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n  }\r\n  else if (dxl_error != 0)\r\n  {\r\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\r\n  }\r\n\r\n  Serial.print(\"[ID:\"); Serial.print(DXL_ID);\r\n  Serial.print(\"] reboot Succeeded\\n\");\r\n\r\n  // Close port\r\n  portHandler->closePort();\r\n\r\n  return;\r\n}\r\n\r\nvoid loop()\r\n{\r\n  \r\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/07. DynamixelSDK/protocol2.0/sync_read_write/sync_read_write.ino",
    "content": "/*******************************************************************************\r\n* Copyright (c) 2016, ROBOTIS CO., LTD.\r\n* All rights reserved.\r\n*\r\n* Redistribution and use in source and binary forms, with or without\r\n* modification, are permitted provided that the following conditions are met:\r\n*\r\n* * Redistributions of source code must retain the above copyright notice, this\r\n*   list of conditions and the following disclaimer.\r\n*\r\n* * Redistributions in binary form must reproduce the above copyright notice,\r\n*   this list of conditions and the following disclaimer in the documentation\r\n*   and/or other materials provided with the distribution.\r\n*\r\n* * Neither the name of ROBOTIS nor the names of its\r\n*   contributors may be used to endorse or promote products derived from\r\n*   this software without specific prior written permission.\r\n*\r\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n*******************************************************************************/\r\n\r\n/* Author: Ryu Woon Jung (Leon) */\r\n\r\n//\r\n// *********     Sync Read and Sync Write Example      *********\r\n//\r\n//\r\n// Available Dynamixel model on this example : All models using Protocol 2.0\r\n// This example is tested with two Dynamixel PRO 54-200, and an USB2DYNAMIXEL\r\n// Be sure that Dynamixel PRO properties are already set as %% ID : 1 / Baudnum : 1 (Baudrate : 57600)\r\n//\r\n\r\n#include <DynamixelSDK.h>\r\n\r\n// Control table address\r\n#define ADDR_PRO_TORQUE_ENABLE          562                 // Control table address is different in Dynamixel model\r\n#define ADDR_PRO_GOAL_POSITION          596\r\n#define ADDR_PRO_PRESENT_POSITION       611\r\n\r\n// Data Byte Length\r\n#define LEN_PRO_GOAL_POSITION           4\r\n#define LEN_PRO_PRESENT_POSITION        4\r\n\r\n// Protocol version\r\n#define PROTOCOL_VERSION                2.0                 // See which protocol version is used in the Dynamixel\r\n\r\n// Default setting\r\n#define DXL1_ID                         1                   // Dynamixel#1 ID: 1\r\n#define DXL2_ID                         2                   // Dynamixel#2 ID: 2\r\n#define BAUDRATE                        57600\r\n#define DEVICENAME                      \"OpenCR_DXL_Port\"   // This definition only has a symbolic meaning and does not affect to any functionality\r\n\r\n#define TORQUE_ENABLE                   1                   // Value for enabling the torque\r\n#define TORQUE_DISABLE                  0                   // Value for disabling the torque\r\n#define DXL_MINIMUM_POSITION_VALUE     -150000              // Dynamixel will rotate between this value\r\n#define DXL_MAXIMUM_POSITION_VALUE      150000              // and this value (note that the Dynamixel would not move when the position value is out of movable range. Check e-manual about the range of the Dynamixel you use.)\r\n#define DXL_MOVING_STATUS_THRESHOLD     20                  // Dynamixel moving status threshold\r\n\r\n#define ESC_ASCII_VALUE                 0x1b\r\n\r\n#define CMD_SERIAL                      Serial\r\n\r\nint getch()\r\n{\r\n  while(1)\r\n  {\r\n    if( CMD_SERIAL.available() > 0 )\r\n    {\r\n      break;\r\n    }\r\n  }\r\n\r\n  return CMD_SERIAL.read();\r\n}\r\n\r\nint kbhit(void)\r\n{\r\n  return CMD_SERIAL.available();\r\n}\r\n\r\nvoid setup()\r\n{\r\n  Serial.begin(115200);\r\n  while(!Serial);\r\n\r\n  Serial.println(\"Start..\");\r\n\r\n   // Initialize PortHandler instance\r\n  // Set the port path\r\n  // Get methods and members of PortHandlerLinux or PortHandlerWindows\r\n  dynamixel::PortHandler *portHandler = dynamixel::PortHandler::getPortHandler(DEVICENAME);\r\n\r\n  // Initialize PacketHandler instance\r\n  // Set the protocol version\r\n  // Get methods and members of Protocol1PacketHandler or Protocol2PacketHandler\r\n  dynamixel::PacketHandler *packetHandler = dynamixel::PacketHandler::getPacketHandler(PROTOCOL_VERSION);\r\n\r\n  // Initialize GroupSyncWrite instance\r\n  dynamixel::GroupSyncWrite groupSyncWrite(portHandler, packetHandler, ADDR_PRO_GOAL_POSITION, LEN_PRO_GOAL_POSITION);\r\n\r\n  // Initialize Groupsyncread instance for Present Position\r\n  dynamixel::GroupSyncRead groupSyncRead(portHandler, packetHandler, ADDR_PRO_PRESENT_POSITION, LEN_PRO_PRESENT_POSITION);\r\n\r\n  int index = 0;\r\n  int dxl_comm_result = COMM_TX_FAIL;             // Communication result\r\n  bool dxl_addparam_result = false;                // addParam result\r\n  //bool dxl_getdata_result = false;                 // GetParam result\r\n  int dxl_goal_position[2] = {DXL_MINIMUM_POSITION_VALUE, DXL_MAXIMUM_POSITION_VALUE};         // Goal position\r\n\r\n  uint8_t dxl_error = 0;                          // Dynamixel error\r\n  uint8_t param_goal_position[4];\r\n  int32_t dxl1_present_position = 0, dxl2_present_position = 0;              // Present position\r\n\r\n  // Open port\r\n  if (portHandler->openPort())\r\n  {\r\n    Serial.print(\"Succeeded to open the port!\\n\");\r\n  }\r\n  else\r\n  {\r\n    Serial.print(\"Failed to open the port!\\n\");\r\n    return;\r\n  }\r\n\r\n  // Set port baudrate\r\n  if (portHandler->setBaudRate(BAUDRATE))\r\n  {\r\n    Serial.print(\"Succeeded to change the baudrate!\\n\");\r\n  }\r\n  else\r\n  {\r\n    Serial.print(\"Failed to change the baudrate!\\n\");\r\n    return;\r\n  }\r\n\r\n  // Enable Dynamixel#1 Torque\r\n  dxl_comm_result = packetHandler->write1ByteTxRx(portHandler, DXL1_ID, ADDR_PRO_TORQUE_ENABLE, TORQUE_ENABLE, &dxl_error);\r\n  if (dxl_comm_result != COMM_SUCCESS)\r\n  {\r\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n  }\r\n  else if (dxl_error != 0)\r\n  {\r\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\r\n  }\r\n  else\r\n  {\r\n    Serial.print(\"Dynamixel#1 has been successfully connected \\n\");\r\n  }\r\n\r\n  // Enable Dynamixel#2 Torque\r\n  dxl_comm_result = packetHandler->write1ByteTxRx(portHandler, DXL2_ID, ADDR_PRO_TORQUE_ENABLE, TORQUE_ENABLE, &dxl_error);\r\n  if (dxl_comm_result != COMM_SUCCESS)\r\n  {\r\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n  }\r\n  else if (dxl_error != 0)\r\n  {\r\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\r\n  }\r\n  else\r\n  {\r\n    Serial.print(\"Dynamixel#2 has been successfully connected \\n\");\r\n  }\r\n\r\n  // Add parameter storage for Dynamixel#1 present position value\r\n  dxl_addparam_result = groupSyncRead.addParam(DXL1_ID);\r\n  if (dxl_addparam_result != true)\r\n  {\r\n    Serial.print(\"[ID:\"); Serial.print(DXL1_ID); Serial.println(\"groupSyncRead addparam failed\");\r\n    return;\r\n  }\r\n\r\n  // Add parameter storage for Dynamixel#2 present position value\r\n  dxl_addparam_result = groupSyncRead.addParam(DXL2_ID);\r\n  if (dxl_addparam_result != true)\r\n  {\r\n    Serial.print(\"[ID:\"); Serial.print(DXL2_ID); Serial.println(\"groupSyncRead addparam failed\");\r\n    return;\r\n  }\r\n\r\n  while(1)\r\n  {\r\n    Serial.print(\"Press any key to continue! (or press q to quit!)\\n\");\r\n    if (getch() == 'q')\r\n      break;\r\n\r\n    // Allocate goal position value into byte array\r\n    param_goal_position[0] = DXL_LOBYTE(DXL_LOWORD(dxl_goal_position[index]));\r\n    param_goal_position[1] = DXL_HIBYTE(DXL_LOWORD(dxl_goal_position[index]));\r\n    param_goal_position[2] = DXL_LOBYTE(DXL_HIWORD(dxl_goal_position[index]));\r\n    param_goal_position[3] = DXL_HIBYTE(DXL_HIWORD(dxl_goal_position[index]));\r\n\r\n    // Add Dynamixel#1 goal position value to the Syncwrite storage\r\n    dxl_addparam_result = groupSyncWrite.addParam(DXL1_ID, param_goal_position);\r\n    if (dxl_addparam_result != true)\r\n    {\r\n      Serial.print(\"[ID:\"); Serial.print(DXL1_ID); Serial.println(\"groupSyncWrite addparam failed\");\r\n      return;\r\n    }\r\n\r\n    // Add Dynamixel#2 goal position value to the Syncwrite parameter storage\r\n    dxl_addparam_result = groupSyncWrite.addParam(DXL2_ID, param_goal_position);\r\n    if (dxl_addparam_result != true)\r\n    {\r\n      Serial.print(\"[ID:\"); Serial.print(DXL2_ID); Serial.println(\"groupSyncWrite addparam failed\");\r\n      return;\r\n    }\r\n\r\n    // Syncwrite goal position\r\n    dxl_comm_result = groupSyncWrite.txPacket();\r\n    if (dxl_comm_result != COMM_SUCCESS) Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n\r\n    // Clear syncwrite parameter storage\r\n    groupSyncWrite.clearParam();\r\n\r\n    do\r\n    {\r\n      // Syncread present position\r\n      dxl_comm_result = groupSyncRead.txRxPacket();\r\n      if (dxl_comm_result != COMM_SUCCESS) Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n\r\n      // Check if groupsyncread data of Dynamixel#1 is available\r\n      groupSyncRead.isAvailable(DXL1_ID, ADDR_PRO_PRESENT_POSITION, LEN_PRO_PRESENT_POSITION);\r\n      if (dxl_addparam_result != true)\r\n      {\r\n        Serial.print(\"[ID:\"); Serial.print(DXL1_ID); Serial.println(\"groupSyncRead getdata failed\");\r\n        return;\r\n      }\r\n\r\n      // Check if groupsyncread data of Dynamixel#2 is available\r\n      groupSyncRead.isAvailable(DXL2_ID, ADDR_PRO_PRESENT_POSITION, LEN_PRO_PRESENT_POSITION);\r\n      if (dxl_addparam_result != true)\r\n      {\r\n        Serial.print(\"[ID:\"); Serial.print(DXL2_ID); Serial.println(\"groupSyncRead getdata failed\");\r\n        return;\r\n      }\r\n\r\n      // Get Dynamixel#1 present position value\r\n      dxl1_present_position = groupSyncRead.getData(DXL1_ID, ADDR_PRO_PRESENT_POSITION, LEN_PRO_PRESENT_POSITION);\r\n\r\n      // Get Dynamixel#2 present position value\r\n      dxl2_present_position = groupSyncRead.getData(DXL2_ID, ADDR_PRO_PRESENT_POSITION, LEN_PRO_PRESENT_POSITION);\r\n\r\n      Serial.print(\"[ID:\"); Serial.print(DXL1_ID);\r\n      Serial.print(\"] GoalPos:\"); Serial.print(dxl_goal_position[index]);\r\n      Serial.print(\"  PresPos:\"); Serial.print(dxl1_present_position);\r\n      Serial.print(\" [ID:\"); Serial.print(DXL2_ID);\r\n      Serial.print(\"] GoalPos:\"); Serial.print(dxl_goal_position[index]);\r\n      Serial.print(\"  PresPos:\"); Serial.print(dxl2_present_position);\r\n      Serial.println(\" \");\r\n\r\n    }while((abs(dxl_goal_position[index] - dxl1_present_position) > DXL_MOVING_STATUS_THRESHOLD) || (abs(dxl_goal_position[index] - dxl2_present_position) > DXL_MOVING_STATUS_THRESHOLD));\r\n\r\n    // Change goal position\r\n    if (index == 0)\r\n    {\r\n      index = 1;\r\n    }\r\n    else\r\n    {\r\n      index = 0;\r\n    }\r\n  }\r\n\r\n  // Disable Dynamixel#1 Torque\r\n  dxl_comm_result = packetHandler->write1ByteTxRx(portHandler, DXL1_ID, ADDR_PRO_TORQUE_ENABLE, TORQUE_DISABLE, &dxl_error);\r\n  if (dxl_comm_result != COMM_SUCCESS)\r\n  {\r\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n  }\r\n  else if (dxl_error != 0)\r\n  {\r\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\r\n  }\r\n\r\n  // Disable Dynamixel#2 Torque\r\n  dxl_comm_result = packetHandler->write1ByteTxRx(portHandler, DXL2_ID, ADDR_PRO_TORQUE_ENABLE, TORQUE_DISABLE, &dxl_error);\r\n  if (dxl_comm_result != COMM_SUCCESS)\r\n  {\r\n    Serial.print(packetHandler->getTxRxResult(dxl_comm_result));\r\n  }\r\n  else if (dxl_error != 0)\r\n  {\r\n    Serial.print(packetHandler->getRxPacketError(dxl_error));\r\n  }\r\n\r\n  // Close port\r\n  portHandler->closePort();\r\n}\r\n\r\nvoid loop()\r\n{\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/07. DynamixelSDK/protocol_combined/protocol_combined.ino",
    "content": "/*******************************************************************************\n* Copyright (c) 2016, ROBOTIS CO., LTD.\n* All rights reserved.\n*\n* Redistribution and use in source and binary forms, with or without\n* modification, are permitted provided that the following conditions are met:\n*\n* * Redistributions of source code must retain the above copyright notice, this\n*   list of conditions and the following disclaimer.\n*\n* * Redistributions in binary form must reproduce the above copyright notice,\n*   this list of conditions and the following disclaimer in the documentation\n*   and/or other materials provided with the distribution.\n*\n* * Neither the name of ROBOTIS nor the names of its\n*   contributors may be used to endorse or promote products derived from\n*   this software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*******************************************************************************/\n\n/* Author: Ryu Woon Jung (Leon) */\n\n//\n// *********     Protocol Combined Example      *********\n//\n//\n// Available Dynamixel model on this example : All models using Protocol 1.0 and 2.0\n// This example is tested with a Dynamixel MX-28, a Dynamixel PRO 54-200 and an USB2DYNAMIXEL\n// Be sure that properties of Dynamixel MX and PRO are already set as %% MX - ID : 1 / Baudnum : 34 (Baudrate : 57600) , PRO - ID : 1 / Baudnum : 1 (Baudrate : 57600)\n//\n\n// Be aware that:\n// This example configures two different control tables (especially, if it uses Dynamixel and Dynamixel PRO). It may modify critical Dynamixel parameter on the control table, if Dynamixels have wrong ID.\n//\n\n#include <DynamixelSDK.h>\n\n// Control table address for Dynamixel MX\n#define ADDR_MX_TORQUE_ENABLE           24                  // Control table address is different in Dynamixel model\n#define ADDR_MX_GOAL_POSITION           30\n#define ADDR_MX_PRESENT_POSITION        36\n\n// Control table address for Dynamixel PRO\n#define ADDR_PRO_TORQUE_ENABLE          562\n#define ADDR_PRO_GOAL_POSITION          596\n#define ADDR_PRO_PRESENT_POSITION       611\n\n// Protocol version\n#define PROTOCOL_VERSION1               1.0                 // See which protocol version is used in the Dynamixel\n#define PROTOCOL_VERSION2               2.0\n\n// Default setting\n#define DXL1_ID                         1                   // Dynamixel#1 ID: 1\n#define DXL2_ID                         2                   // Dynamixel#2 ID: 2\n#define BAUDRATE                        57600\n#define DEVICENAME                      \"OpenCR_DXL_Port\"   // This definition only has a symbolic meaning and does not affect to any functionality\n\n#define TORQUE_ENABLE                   1                   // Value for enabling the torque\n#define TORQUE_DISABLE                  0                   // Value for disabling the torque\n#define DXL1_MINIMUM_POSITION_VALUE     100                 // Dynamixel will rotate between this value\n#define DXL1_MAXIMUM_POSITION_VALUE     4000                // and this value (note that the Dynamixel would not move when the position value is out of movable range. Check e-manual about the range of the Dynamixel you use.)\n#define DXL2_MINIMUM_POSITION_VALUE     -150000\n#define DXL2_MAXIMUM_POSITION_VALUE     150000\n#define DXL1_MOVING_STATUS_THRESHOLD    10                  // Dynamixel MX moving status threshold\n#define DXL2_MOVING_STATUS_THRESHOLD    20                  // Dynamixel PRO moving status threshold\n\n#define ESC_ASCII_VALUE                 0x1b\n\n#define CMD_SERIAL                      Serial\n\nint getch()\n{\n  while(1)\n  {\n    if( CMD_SERIAL.available() > 0 )\n    {\n      break;\n    }\n  }\n\n  return CMD_SERIAL.read();\n}\n\nint kbhit(void)\n{\n  return CMD_SERIAL.available();\n}\n\nvoid setup()\n{\n  Serial.begin(115200);\n  while(!Serial);\n\n  Serial.println(\"Start..\");\n\n  // Initialize PortHandler instance\n  // Set the port path\n  // Get methods and members of PortHandlerLinux or PortHandlerWindows\n  dynamixel::PortHandler *portHandler = dynamixel::PortHandler::getPortHandler(DEVICENAME);\n\n  // Initialize PacketHandler instance\n  // Set the protocol version\n  // Get methods and members of Protocol1PacketHandler or Protocol2PacketHandler\n  dynamixel::PacketHandler *packetHandler1 = dynamixel::PacketHandler::getPacketHandler(PROTOCOL_VERSION1);\n  dynamixel::PacketHandler *packetHandler2 = dynamixel::PacketHandler::getPacketHandler(PROTOCOL_VERSION2);\n\n  int index = 0;\n  int dxl_comm_result = COMM_TX_FAIL;       // Communication result\n  int dxl1_goal_position[2] = {DXL1_MINIMUM_POSITION_VALUE, DXL1_MAXIMUM_POSITION_VALUE};     // Goal position of Dynamixel MX\n  int dxl2_goal_position[2] = {DXL2_MINIMUM_POSITION_VALUE, DXL2_MAXIMUM_POSITION_VALUE};     // Goal position of Dynamixel PRO\n\n  uint8_t dxl_error = 0;                    // Dynamixel error\n  uint16_t dxl1_present_position = 0;       // Present position of Dynamixel MX\n  int32_t dxl2_present_position = 0;        // Present position of Dynamixel PRO\n\n  // Open port\n  if (portHandler->openPort())\n  {\n    Serial.print(\"Succeeded to open the port!\\n\");\n  }\n  else\n  {\n    Serial.print(\"Failed to open the port!\\n\");\n    return;\n  }\n\n  // Set port baudrate\n  if (portHandler->setBaudRate(BAUDRATE))\n  {\n    Serial.print(\"Succeeded to change the baudrate!\\n\");\n  }\n  else\n  {\n    Serial.print(\"Failed to change the baudrate!\\n\");\n    return;\n  }\n\n  // Enable Dynamixel#1 torque\n  dxl_comm_result = packetHandler1->write1ByteTxRx(portHandler, DXL1_ID, ADDR_MX_TORQUE_ENABLE, TORQUE_ENABLE, &dxl_error);\n  if (dxl_comm_result != COMM_SUCCESS)\n  {\n    Serial.print(packetHandler1->getTxRxResult(dxl_comm_result));\n  }\n  else if (dxl_error != 0)\n  {\n    Serial.print(packetHandler1->getRxPacketError(dxl_error));\n  }\n  else\n  {\n    Serial.print(\"Dynamixel#1 has been successfully connected \\n\");\n  }\n  // Enable Dynamixel#2 torque\n  dxl_comm_result = packetHandler2->write1ByteTxRx(portHandler, DXL2_ID, ADDR_PRO_TORQUE_ENABLE, TORQUE_ENABLE, &dxl_error);\n  if (dxl_comm_result != COMM_SUCCESS)\n  {\n    Serial.print(packetHandler2->getTxRxResult(dxl_comm_result));\n  }\n  else if (dxl_error != 0)\n  {\n    Serial.print(packetHandler2->getRxPacketError(dxl_error));\n  }\n  else\n  {\n    Serial.print(\"Dynamixel#2 has been successfully connected \\n\");\n  }\n\n  while(1)\n  {\n    Serial.print(\"Press any key to continue! (or press q to quit!)\\n\");\n    if (getch() == 'q')\n      break;\n\n    // Write Dynamixel#1 goal position\n    dxl_comm_result = packetHandler1->write2ByteTxRx(portHandler, DXL1_ID, ADDR_MX_GOAL_POSITION, dxl1_goal_position[index], &dxl_error);\n    if (dxl_comm_result != COMM_SUCCESS)\n    {\n      Serial.print(packetHandler1->getTxRxResult(dxl_comm_result));\n    }\n    else if (dxl_error != 0)\n    {\n      Serial.print(packetHandler1->getRxPacketError(dxl_error));\n    }\n\n    // Write Dynamixel#2 goal position\n    dxl_comm_result = packetHandler2->write4ByteTxRx(portHandler, DXL2_ID, ADDR_PRO_GOAL_POSITION, dxl2_goal_position[index], &dxl_error);\n    if (dxl_comm_result != COMM_SUCCESS)\n    {\n      Serial.print(packetHandler2->getTxRxResult(dxl_comm_result));\n    }\n    else if (dxl_error != 0)\n    {\n      Serial.print(packetHandler2->getRxPacketError(dxl_error));\n    }\n\n    do\n    {\n      // Read Dynamixel#1 present position\n      dxl_comm_result = packetHandler1->read2ByteTxRx(portHandler, DXL1_ID, ADDR_MX_PRESENT_POSITION, &dxl1_present_position, &dxl_error);\n      if (dxl_comm_result != COMM_SUCCESS)\n      {\n        Serial.print(packetHandler1->getTxRxResult(dxl_comm_result));\n      }\n      else if (dxl_error != 0)\n      {\n        Serial.print(packetHandler1->getRxPacketError(dxl_error));\n      }\n\n      // Read Dynamixel#2 present position\n      dxl_comm_result = packetHandler2->read4ByteTxRx(portHandler, DXL2_ID, ADDR_PRO_PRESENT_POSITION, (uint32_t*)&dxl2_present_position, &dxl_error);\n      if (dxl_comm_result != COMM_SUCCESS)\n      {\n        Serial.print(packetHandler2->getTxRxResult(dxl_comm_result));\n      }\n      else if (dxl_error != 0)\n      {\n        Serial.print(packetHandler2->getRxPacketError(dxl_error));\n      }\n\n      Serial.print(\"[ID:\"); Serial.print(DXL1_ID);\n      Serial.print(\"] GoalPos:\"); Serial.print(dxl1_goal_position[index]);\n      Serial.print(\"  PresPos:\"); Serial.print(dxl1_present_position);\n      Serial.print(\"  [ID:\"); Serial.print(DXL2_ID);\n      Serial.print(\"] GoalPos:\"); Serial.print(dxl2_goal_position[index]);\n      Serial.print(\"  PresPos:\"); Serial.print(dxl2_present_position);\n\n    }while((abs(dxl1_goal_position[index] - dxl1_present_position) > DXL1_MOVING_STATUS_THRESHOLD) || (abs(dxl2_goal_position[index] - dxl2_present_position) > DXL2_MOVING_STATUS_THRESHOLD));\n\n    // Change goal position\n    if (index == 0)\n    {\n      index = 1;\n    }\n    else\n    {\n      index = 0;\n    }\n  }\n\n  // Disable Dynamixel#1 Torque\n  dxl_comm_result = packetHandler1->write1ByteTxRx(portHandler, DXL1_ID, ADDR_MX_TORQUE_ENABLE, TORQUE_DISABLE, &dxl_error);\n  if (dxl_comm_result != COMM_SUCCESS)\n  {\n    Serial.print(packetHandler1->getTxRxResult(dxl_comm_result));\n  }\n  else if (dxl_error != 0)\n  {\n    Serial.print(packetHandler1->getRxPacketError(dxl_error));\n  }\n\n  // Disable Dynamixel#2 Torque\n  dxl_comm_result = packetHandler2->write1ByteTxRx(portHandler, DXL2_ID, ADDR_PRO_TORQUE_ENABLE, TORQUE_DISABLE, &dxl_error);\n  if (dxl_comm_result != COMM_SUCCESS)\n  {\n    Serial.print(packetHandler2->getTxRxResult(dxl_comm_result));\n  }\n  else if (dxl_error != 0)\n  {\n    Serial.print(packetHandler2->getRxPacketError(dxl_error));\n  }\n\n  // Close port\n  portHandler->closePort();\n}\n\nvoid loop()\n{\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/08. DynamixelWorkbench/a_Model_Scan/a_Model_Scan.ino",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Taehun Lim (Darby) */\n\n#include <DynamixelWorkbench.h>\n\n#if defined(__OPENCM904__)\n  #define DEVICE_NAME \"3\" //Dynamixel on Serial3(USART3)  <-OpenCM 485EXP\n#elif defined(__OPENCR__)\n  #define DEVICE_NAME \"\"\n#endif          \n\n#define BAUDRATE  1000000\n\nDynamixelWorkbench dxl_wb;\n\nvoid setup() \n{\n  Serial.begin(57600);\n  while(!Serial); // Wait for Opening Serial Monitor\n\n  const char *log = NULL;\n  bool result = false;\n\n  uint8_t scanned_id[16];\n  uint8_t dxl_cnt = 0;\n  uint8_t range = 100;\n\n  result = dxl_wb.init(DEVICE_NAME, BAUDRATE, &log);\n  if (result == false)\n  {\n    Serial.println(log);\n    Serial.println(\"Failed to init\");\n  }\n  else\n  {\n    Serial.print(\"Succeeded to init : \");\n    Serial.println(BAUDRATE);  \n  }\n\n  Serial.println(\"Wait for scan...\");\n  result = dxl_wb.scan(scanned_id, &dxl_cnt, range, &log);\n  if (result == false)\n  {\n    Serial.println(log);\n    Serial.println(\"Failed to scan\");\n  }\n  else\n  {\n    Serial.print(\"Find \");\n    Serial.print(dxl_cnt);\n    Serial.println(\" Dynamixels\");\n\n    for (int cnt = 0; cnt < dxl_cnt; cnt++)\n    {\n      Serial.print(\"id : \");\n      Serial.print(scanned_id[cnt]);\n      Serial.print(\" model name : \");\n      Serial.println(dxl_wb.getModelName(scanned_id[cnt]));\n    }\n  }  \n}\n\nvoid loop() \n{\n\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/08. DynamixelWorkbench/b_Ping/b_Ping.ino",
    "content": "/*******************************************************************************\r\n* Copyright 2016 ROBOTIS CO., LTD.\r\n*\r\n* Licensed under the Apache License, Version 2.0 (the \"License\");\r\n* you may not use this file except in compliance with the License.\r\n* You may obtain a copy of the License at\r\n*\r\n*     http://www.apache.org/licenses/LICENSE-2.0\r\n*\r\n* Unless required by applicable law or agreed to in writing, software\r\n* distributed under the License is distributed on an \"AS IS\" BASIS,\r\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n* See the License for the specific language governing permissions and\r\n* limitations under the License.\r\n*******************************************************************************/\r\n\r\n/* Authors: Taehun Lim (Darby) */\r\n\r\n#include <DynamixelWorkbench.h>\r\n\r\n#if defined(__OPENCM904__)\r\n  #define DEVICE_NAME \"3\" //Dynamixel on Serial3(USART3)  <-OpenCM 485EXP\r\n#elif defined(__OPENCR__)\r\n  #define DEVICE_NAME \"\"\r\n#endif  \r\n\r\n#define BAUDRATE  57600\r\n#define DXL_ID    1\r\n\r\nDynamixelWorkbench dxl_wb;\r\n\r\nvoid setup() \r\n{\r\n  Serial.begin(57600);\r\n  while(!Serial); // Wait for Opening Serial Monitor\r\n\r\n  const char *log;\r\n  bool result = false;\r\n\r\n  uint8_t dxl_id = DXL_ID;\r\n  uint16_t model_number = 0;\r\n\r\n  result = dxl_wb.init(DEVICE_NAME, BAUDRATE, &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to init\");\r\n  }\r\n  else\r\n  {\r\n    Serial.print(\"Succeeded to init : \");\r\n    Serial.println(BAUDRATE);  \r\n  }\r\n\r\n  result = dxl_wb.ping(dxl_id, &model_number, &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to ping\");\r\n  }\r\n  else\r\n  {\r\n    Serial.println(\"Succeeded to ping\");\r\n    Serial.print(\"id : \");\r\n    Serial.print(dxl_id);\r\n    Serial.print(\" model_number : \");\r\n    Serial.println(model_number);\r\n  }\r\n}\r\n\r\nvoid loop() \r\n{\r\n\r\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/08. DynamixelWorkbench/c_ID_Change/c_ID_Change.ino",
    "content": "/*******************************************************************************\r\n* Copyright 2016 ROBOTIS CO., LTD.\r\n*\r\n* Licensed under the Apache License, Version 2.0 (the \"License\");\r\n* you may not use this file except in compliance with the License.\r\n* You may obtain a copy of the License at\r\n*\r\n*     http://www.apache.org/licenses/LICENSE-2.0\r\n*\r\n* Unless required by applicable law or agreed to in writing, software\r\n* distributed under the License is distributed on an \"AS IS\" BASIS,\r\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n* See the License for the specific language governing permissions and\r\n* limitations under the License.\r\n*******************************************************************************/\r\n\r\n/* Authors: Taehun Lim (Darby) */\r\n\r\n#include <DynamixelWorkbench.h>\r\n\r\n#if defined(__OPENCM904__)\r\n  #define DEVICE_NAME \"3\" //Dynamixel on Serial3(USART3)  <-OpenCM 485EXP\r\n#elif defined(__OPENCR__)\r\n  #define DEVICE_NAME \"\"\r\n#endif  \r\n\r\n#define BAUDRATE  57600\r\n#define DXL_ID  1\r\n#define NEW_DXL_ID  2\r\n\r\nDynamixelWorkbench dxl_wb;\r\n\r\nvoid setup() \r\n{\r\n  Serial.begin(57600);\r\n  while(!Serial); // Wait for Opening Serial Monitor\r\n\r\n  const char *log;\r\n  bool result = false;\r\n\r\n  uint8_t dxl_id = DXL_ID;\r\n  uint8_t dxl_new_id = NEW_DXL_ID;\r\n  uint16_t model_number = 0;\r\n\r\n  result = dxl_wb.init(DEVICE_NAME, BAUDRATE, &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to init\");\r\n  }\r\n  else\r\n  {\r\n    Serial.print(\"Succeeded to init : \");\r\n    Serial.println(BAUDRATE);  \r\n  }\r\n\r\n  result = dxl_wb.ping(dxl_id, &model_number, &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to ping\");\r\n  }\r\n  else\r\n  {\r\n    Serial.println(\"Succeeded to ping\");\r\n    Serial.print(\"id : \");\r\n    Serial.print(dxl_id);\r\n    Serial.print(\" model_number : \");\r\n    Serial.println(model_number);\r\n  }\r\n\r\n  result = dxl_wb.changeID(dxl_id, dxl_new_id, &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    return;\r\n  }\r\n  else\r\n  {\r\n    Serial.println(log);\r\n  }\r\n\r\n  uint8_t scanned_id[16];\r\n  uint8_t dxl_cnt = 0;\r\n  uint8_t range = 100;\r\n\r\n  result = dxl_wb.scan(scanned_id, &dxl_cnt, range, &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to scan\");\r\n  }\r\n  else\r\n  {\r\n    Serial.print(\"Find \");\r\n    Serial.print(dxl_cnt);\r\n    Serial.println(\" Dynamixels\");\r\n\r\n    for (int cnt = 0; cnt < dxl_cnt; cnt++)\r\n    {\r\n      Serial.print(\"id : \");\r\n      Serial.print(scanned_id[cnt]);\r\n      Serial.print(\" model name : \");\r\n      Serial.println(dxl_wb.getModelName(scanned_id[cnt]));\r\n    }\r\n  }\r\n}\r\n\r\nvoid loop() \r\n{\r\n\r\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/08. DynamixelWorkbench/d_BPS_Change/d_BPS_Change.ino",
    "content": "/*******************************************************************************\r\n* Copyright 2016 ROBOTIS CO., LTD.\r\n*\r\n* Licensed under the Apache License, Version 2.0 (the \"License\");\r\n* you may not use this file except in compliance with the License.\r\n* You may obtain a copy of the License at\r\n*\r\n*     http://www.apache.org/licenses/LICENSE-2.0\r\n*\r\n* Unless required by applicable law or agreed to in writing, software\r\n* distributed under the License is distributed on an \"AS IS\" BASIS,\r\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n* See the License for the specific language governing permissions and\r\n* limitations under the License.\r\n*******************************************************************************/\r\n\r\n/* Authors: Taehun Lim (Darby) */\r\n\r\n#include <DynamixelWorkbench.h>\r\n\r\n#if defined(__OPENCM904__)\r\n  #define DEVICE_NAME \"3\" //Dynamixel on Serial3(USART3)  <-OpenCM 485EXP\r\n#elif defined(__OPENCR__)\r\n  #define DEVICE_NAME \"\"\r\n#endif   \r\n\r\n#define BAUDRATE  1000000\r\n#define DXL_ID 1\r\n#define NEW_BAUDRATE 57600\r\n\r\nDynamixelWorkbench dxl_wb;\r\n\r\nvoid setup() \r\n{\r\n  Serial.begin(57600);\r\n  while(!Serial); // Wait for Opening Serial Monitor\r\n\r\n  const char *log;\r\n  bool result = false;\r\n\r\n  uint8_t dxl_id = DXL_ID;\r\n  uint32_t new_baud_rate = NEW_BAUDRATE;\r\n  uint16_t model_number = 0;\r\n\r\n  result = dxl_wb.init(DEVICE_NAME, BAUDRATE, &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to init\");\r\n  }\r\n  else\r\n  {\r\n    Serial.print(\"Succeeded to init : \");\r\n    Serial.println(BAUDRATE);  \r\n  }\r\n\r\n  result = dxl_wb.ping(dxl_id, &model_number, &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to ping\");\r\n  }\r\n  else\r\n  {\r\n    Serial.println(\"Succeeded to ping\");\r\n    Serial.print(\"id : \");\r\n    Serial.print(dxl_id);\r\n    Serial.print(\" model_number : \");\r\n    Serial.println(model_number);\r\n  }\r\n\r\n  result = dxl_wb.changeBaudrate(dxl_id, new_baud_rate, &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    return;\r\n  }\r\n  else\r\n  {\r\n    Serial.println(log);\r\n  }\r\n\r\n  return;\r\n}\r\n\r\nvoid loop() \r\n{\r\n\r\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/08. DynamixelWorkbench/e_Mode_Change/e_Mode_Change.ino",
    "content": "/*******************************************************************************\r\n* Copyright 2016 ROBOTIS CO., LTD.\r\n*\r\n* Licensed under the Apache License, Version 2.0 (the \"License\");\r\n* you may not use this file except in compliance with the License.\r\n* You may obtain a copy of the License at\r\n*\r\n*     http://www.apache.org/licenses/LICENSE-2.0\r\n*\r\n* Unless required by applicable law or agreed to in writing, software\r\n* distributed under the License is distributed on an \"AS IS\" BASIS,\r\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n* See the License for the specific language governing permissions and\r\n* limitations under the License.\r\n*******************************************************************************/\r\n\r\n/* Authors: Taehun Lim (Darby) */\r\n\r\n#include <DynamixelWorkbench.h>\r\n\r\n#if defined(__OPENCM904__)\r\n  #define DEVICE_NAME \"3\" //Dynamixel on Serial3(USART3)  <-OpenCM 485EXP\r\n#elif defined(__OPENCR__)\r\n  #define DEVICE_NAME \"\"\r\n#endif    \r\n\r\n#define BAUDRATE  57600\r\n#define DXL_ID    1\r\n#define MODE 0\r\n\r\n// \"Please insert the right number from 0 to 6 to set constrol mode \r\n// \"0 - current control mode\r\n// \"1 - velocity control mode\r\n// \"2 - position control mode\r\n// \"3 - extended position control mode\r\n// \"4 - current based position control mode\r\n// \"5 - pwm control mode\r\n\r\nDynamixelWorkbench dxl_wb;\r\n\r\nvoid setup() \r\n{\r\n  Serial.begin(57600);\r\n  while(!Serial); // Wait for Opening Serial Monitor\r\n\r\n  const char *log;\r\n  bool result = false;\r\n\r\n  uint8_t dxl_id = DXL_ID;\r\n  uint8_t mode = MODE;\r\n  uint16_t model_number = 0;\r\n\r\n  result = dxl_wb.init(DEVICE_NAME, BAUDRATE, &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to init\");\r\n  }\r\n  else\r\n  {\r\n    Serial.print(\"Succeeded to init : \");\r\n    Serial.println(BAUDRATE);  \r\n  }\r\n\r\n  result = dxl_wb.ping(dxl_id, &model_number, &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to ping\");\r\n  }\r\n  else\r\n  {\r\n    Serial.println(\"Succeeded to ping\");\r\n    Serial.print(\"id : \");\r\n    Serial.print(dxl_id);\r\n    Serial.print(\" model_number : \");\r\n    Serial.println(model_number);\r\n  }\r\n\r\n  switch (mode)\r\n  {\r\n    case 0:\r\n      result = dxl_wb.setCurrentControlMode(dxl_id, &log);\r\n      if (result == false)\r\n      {\r\n        Serial.println(log);\r\n        Serial.println(\"Failed to set mode\");\r\n      }\r\n      else\r\n      {\r\n        Serial.println(\"Succeeded to set mode\");\r\n      }\r\n     break;\r\n\r\n    case 1:\r\n      result = dxl_wb.setVelocityControlMode(dxl_id, &log);\r\n      if (result == false)\r\n      {\r\n        Serial.println(log);\r\n        Serial.println(\"Failed to set mode\");\r\n      }\r\n      else\r\n      {\r\n        Serial.println(\"Succeeded to set mode\");\r\n      }\r\n     break;\r\n\r\n    case 2:\r\n      result = dxl_wb.setPositionControlMode(dxl_id, &log);\r\n      if (result == false)\r\n      {\r\n        Serial.println(log);\r\n        Serial.println(\"Failed to set mode\");\r\n      }\r\n      else\r\n      {\r\n        Serial.println(\"Succeeded to set mode\");\r\n      }\r\n     break;\r\n\r\n    case 3:\r\n      result = dxl_wb.setExtendedPositionControlMode(dxl_id, &log);\r\n      if (result == false)\r\n      {\r\n        Serial.println(log);\r\n        Serial.println(\"Failed to set mode\");\r\n      }\r\n      else\r\n      {\r\n        Serial.println(\"Succeeded to set mode\");\r\n      }\r\n     break;\r\n\r\n    case 4:\r\n      result = dxl_wb.setCurrentBasedPositionControlMode(dxl_id, &log);\r\n      if (result == false)\r\n      {\r\n        Serial.println(log);\r\n        Serial.println(\"Failed to set mode\");\r\n      }\r\n      else\r\n      {\r\n        Serial.println(\"Succeeded to set mode\");\r\n      }\r\n     break;\r\n\r\n    case 5:\r\n      result = dxl_wb.setPWMControlMode(dxl_id, &log);\r\n      if (result == false)\r\n      {\r\n        Serial.println(log);\r\n        Serial.println(\"Failed to set mode\");\r\n      }\r\n      else\r\n      {\r\n        Serial.println(\"Succeeded to set mode\");\r\n      }\r\n     break;\r\n\r\n    default:\r\n      result = dxl_wb.setPositionControlMode(dxl_id, &log);\r\n      if (result == false)\r\n      {\r\n        Serial.println(log);\r\n        Serial.println(\"Failed to set mode\");\r\n      }\r\n      else\r\n      {\r\n        Serial.println(\"Succeeded to set mode\");\r\n      }\r\n     break;\r\n  }\r\n}\r\n\r\nvoid loop() \r\n{\r\n\r\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/08. DynamixelWorkbench/f_Reboot/f_Reboot.ino",
    "content": "/*******************************************************************************\r\n* Copyright 2016 ROBOTIS CO., LTD.\r\n*\r\n* Licensed under the Apache License, Version 2.0 (the \"License\");\r\n* you may not use this file except in compliance with the License.\r\n* You may obtain a copy of the License at\r\n*\r\n*     http://www.apache.org/licenses/LICENSE-2.0\r\n*\r\n* Unless required by applicable law or agreed to in writing, software\r\n* distributed under the License is distributed on an \"AS IS\" BASIS,\r\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n* See the License for the specific language governing permissions and\r\n* limitations under the License.\r\n*******************************************************************************/\r\n\r\n/* Authors: Taehun Lim (Darby) */\r\n\r\n#include <DynamixelWorkbench.h>\r\n\r\n#if defined(__OPENCM904__)\r\n  #define DEVICE_NAME \"3\" //Dynamixel on Serial3(USART3)  <-OpenCM 485EXP\r\n#elif defined(__OPENCR__)\r\n  #define DEVICE_NAME \"\"\r\n#endif   \r\n\r\n#define BAUDRATE  57600\r\n#define DXL_ID    1\r\n\r\nDynamixelWorkbench dxl_wb;\r\n\r\nvoid setup() \r\n{\r\n  Serial.begin(57600);\r\n  while(!Serial); // Wait for Opening Serial Monitor\r\n\r\n  const char *log;\r\n  bool result = false;\r\n\r\n  uint8_t dxl_id = DXL_ID;\r\n  uint16_t model_number = 0;\r\n\r\n  result = dxl_wb.init(DEVICE_NAME, BAUDRATE, &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to init\");\r\n  }\r\n  else\r\n  {\r\n    Serial.print(\"Succeeded to init : \");\r\n    Serial.println(BAUDRATE);  \r\n  }\r\n\r\n  result = dxl_wb.ping(dxl_id, &model_number, &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to ping\");\r\n  }\r\n  else\r\n  {\r\n    Serial.println(\"Succeeded to ping\");\r\n    Serial.print(\"id : \");\r\n    Serial.print(dxl_id);\r\n    Serial.print(\" model_number : \");\r\n    Serial.println(model_number);\r\n  }\r\n\r\n  result = dxl_wb.reboot(dxl_id, &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to reboot\");\r\n  }\r\n  else\r\n  {\r\n    Serial.println(\"Succeed to reboot\");\r\n  }\r\n}\r\n\r\nvoid loop() \r\n{\r\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/08. DynamixelWorkbench/g_Reset/g_Reset.ino",
    "content": "/*******************************************************************************\r\n* Copyright 2016 ROBOTIS CO., LTD.\r\n*\r\n* Licensed under the Apache License, Version 2.0 (the \"License\");\r\n* you may not use this file except in compliance with the License.\r\n* You may obtain a copy of the License at\r\n*\r\n*     http://www.apache.org/licenses/LICENSE-2.0\r\n*\r\n* Unless required by applicable law or agreed to in writing, software\r\n* distributed under the License is distributed on an \"AS IS\" BASIS,\r\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n* See the License for the specific language governing permissions and\r\n* limitations under the License.\r\n*******************************************************************************/\r\n\r\n/* Authors: Taehun Lim (Darby) */\r\n\r\n#include <DynamixelWorkbench.h>\r\n\r\n#if defined(__OPENCM904__)\r\n  #define DEVICE_NAME \"3\" //Dynamixel on Serial3(USART3)  <-OpenCM 485EXP\r\n#elif defined(__OPENCR__)\r\n  #define DEVICE_NAME \"\"\r\n#endif   \r\n\r\n#define BAUDRATE  57600\r\n#define DXL_ID    2\r\n\r\nDynamixelWorkbench dxl_wb;\r\n\r\nvoid setup() \r\n{\r\n  Serial.begin(57600);\r\n  while(!Serial); // Wait for Opening Serial Monitor\r\n\r\n  const char *log;\r\n  bool result = false;\r\n\r\n  uint8_t dxl_id = DXL_ID;\r\n  uint16_t model_number = 0;\r\n\r\n  result = dxl_wb.init(DEVICE_NAME, BAUDRATE, &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to init\");\r\n  }\r\n  else\r\n  {\r\n    Serial.print(\"Succeeded to init : \");\r\n    Serial.println(BAUDRATE);  \r\n  }\r\n\r\n  result = dxl_wb.ping(dxl_id, &model_number, &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to ping\");\r\n  }\r\n  else\r\n  {\r\n    Serial.println(\"Succeeded to ping\");\r\n    Serial.print(\"id : \");\r\n    Serial.print(dxl_id);\r\n    Serial.print(\" model_number : \");\r\n    Serial.println(model_number);\r\n  }\r\n\r\n  result = dxl_wb.reset(dxl_id, &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to reset\");\r\n  }\r\n  else\r\n  {\r\n    Serial.println(\"Succeed to reset\");\r\n  }\r\n}\r\n\r\nvoid loop() \r\n{\r\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/08. DynamixelWorkbench/h_Position/h_Position.ino",
    "content": "/*******************************************************************************\r\n* Copyright 2016 ROBOTIS CO., LTD.\r\n*\r\n* Licensed under the Apache License, Version 2.0 (the \"License\");\r\n* you may not use this file except in compliance with the License.\r\n* You may obtain a copy of the License at\r\n*\r\n*     http://www.apache.org/licenses/LICENSE-2.0\r\n*\r\n* Unless required by applicable law or agreed to in writing, software\r\n* distributed under the License is distributed on an \"AS IS\" BASIS,\r\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n* See the License for the specific language governing permissions and\r\n* limitations under the License.\r\n*******************************************************************************/\r\n\r\n/* Authors: Taehun Lim (Darby) */\r\n\r\n#include <DynamixelWorkbench.h>\r\n\r\n#if defined(__OPENCM904__)\r\n  #define DEVICE_NAME \"3\" //Dynamixel on Serial3(USART3)  <-OpenCM 485EXP\r\n#elif defined(__OPENCR__)\r\n  #define DEVICE_NAME \"\"\r\n#endif   \r\n\r\n#define BAUDRATE  57600\r\n#define DXL_ID    1\r\n\r\nDynamixelWorkbench dxl_wb;\r\n\r\nvoid setup() \r\n{\r\n  Serial.begin(57600);\r\n  // while(!Serial); // Wait for Opening Serial Monitor\r\n\r\n  const char *log;\r\n  bool result = false;\r\n\r\n  uint8_t dxl_id = DXL_ID;\r\n  uint16_t model_number = 0;\r\n\r\n  result = dxl_wb.init(DEVICE_NAME, BAUDRATE, &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to init\");\r\n  }\r\n  else\r\n  {\r\n    Serial.print(\"Succeeded to init : \");\r\n    Serial.println(BAUDRATE);  \r\n  }\r\n\r\n  result = dxl_wb.ping(dxl_id, &model_number, &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to ping\");\r\n  }\r\n  else\r\n  {\r\n    Serial.println(\"Succeeded to ping\");\r\n    Serial.print(\"id : \");\r\n    Serial.print(dxl_id);\r\n    Serial.print(\" model_number : \");\r\n    Serial.println(model_number);\r\n  }\r\n\r\n  result = dxl_wb.jointMode(dxl_id, 0, 0, &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to change joint mode\");\r\n  }\r\n  else\r\n  {\r\n    Serial.println(\"Succeed to change joint mode\");\r\n    Serial.println(\"Dynamixel is moving...\");\r\n\r\n    for (int count = 0; count < 3; count++)\r\n    {\r\n      dxl_wb.goalPosition(dxl_id, (int32_t)0);\r\n      delay(3000);\r\n\r\n      dxl_wb.goalPosition(dxl_id, (int32_t)1023);\r\n      delay(3000);\r\n    }\r\n  }\r\n}\r\n\r\nvoid loop() \r\n{\r\n\r\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/08. DynamixelWorkbench/i_Velocity/i_Velocity.ino",
    "content": "/*******************************************************************************\r\n* Copyright 2016 ROBOTIS CO., LTD.\r\n*\r\n* Licensed under the Apache License, Version 2.0 (the \"License\");\r\n* you may not use this file except in compliance with the License.\r\n* You may obtain a copy of the License at\r\n*\r\n*     http://www.apache.org/licenses/LICENSE-2.0\r\n*\r\n* Unless required by applicable law or agreed to in writing, software\r\n* distributed under the License is distributed on an \"AS IS\" BASIS,\r\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n* See the License for the specific language governing permissions and\r\n* limitations under the License.\r\n*******************************************************************************/\r\n\r\n/* Authors: Taehun Lim (Darby) */\r\n\r\n#include <DynamixelWorkbench.h>\r\n\r\n#if defined(__OPENCM904__)\r\n  #define DEVICE_NAME \"3\" //Dynamixel on Serial3(USART3)  <-OpenCM 485EXP\r\n#elif defined(__OPENCR__)\r\n  #define DEVICE_NAME \"\"\r\n#endif   \r\n\r\n#define BAUDRATE  57600\r\n#define DXL_ID    1\r\n\r\nDynamixelWorkbench dxl_wb;\r\n\r\nvoid setup() \r\n{\r\n  Serial.begin(57600);\r\n  // while(!Serial); // Wait for Opening Serial Monitor\r\n\r\n  const char *log;\r\n  bool result = false;\r\n\r\n  uint8_t dxl_id = DXL_ID;\r\n  uint16_t model_number = 0;\r\n\r\n  result = dxl_wb.init(DEVICE_NAME, BAUDRATE, &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to init\");\r\n  }\r\n  else\r\n  {\r\n    Serial.print(\"Succeeded to init : \");\r\n    Serial.println(BAUDRATE);  \r\n  }\r\n\r\n  result = dxl_wb.ping(dxl_id, &model_number, &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to ping\");\r\n  }\r\n  else\r\n  {\r\n    Serial.println(\"Succeeded to ping\");\r\n    Serial.print(\"id : \");\r\n    Serial.print(dxl_id);\r\n    Serial.print(\" model_number : \");\r\n    Serial.println(model_number);\r\n  }\r\n\r\n  result = dxl_wb.wheelMode(dxl_id, 0, &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to change wheel mode\");\r\n  }\r\n  else\r\n  {\r\n    Serial.println(\"Succeed to change wheel mode\");\r\n    Serial.println(\"Dynamixel is moving...\");\r\n\r\n    for (int count = 0; count < 3; count++)\r\n    {\r\n      dxl_wb.goalVelocity(dxl_id, (int32_t)-100);\r\n      delay(3000);\r\n\r\n      dxl_wb.goalVelocity(dxl_id, (int32_t)100);\r\n      delay(3000);\r\n    }\r\n\r\n    dxl_wb.goalVelocity(dxl_id, (int32_t)0);\r\n  }\r\n}\r\n\r\nvoid loop() \r\n{\r\n\r\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/08. DynamixelWorkbench/j_Current_Based_Position/j_Current_Based_Position.ino",
    "content": "/*******************************************************************************\r\n* Copyright 2016 ROBOTIS CO., LTD.\r\n*\r\n* Licensed under the Apache License, Version 2.0 (the \"License\");\r\n* you may not use this file except in compliance with the License.\r\n* You may obtain a copy of the License at\r\n*\r\n*     http://www.apache.org/licenses/LICENSE-2.0\r\n*\r\n* Unless required by applicable law or agreed to in writing, software\r\n* distributed under the License is distributed on an \"AS IS\" BASIS,\r\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n* See the License for the specific language governing permissions and\r\n* limitations under the License.\r\n*******************************************************************************/\r\n\r\n/* Authors: Taehun Lim (Darby) */\r\n\r\n#include <DynamixelWorkbench.h>\r\n\r\n#if defined(__OPENCM904__)\r\n  #define DEVICE_NAME \"3\" //Dynamixel on Serial3(USART3)  <-OpenCM 485EXP\r\n#elif defined(__OPENCR__)\r\n  #define DEVICE_NAME \"\"\r\n#endif   \r\n\r\n#define BAUDRATE  57600\r\n#define DXL_ID    1\r\n\r\nDynamixelWorkbench dxl_wb;\r\n\r\nvoid setup() \r\n{\r\n  Serial.begin(57600);\r\n  while(!Serial); // Wait for Opening Serial Monitor\r\n\r\n  const char *log;\r\n  bool result = false;\r\n\r\n  uint8_t dxl_id = DXL_ID;\r\n  uint16_t model_number = 0;\r\n\r\n  result = dxl_wb.init(DEVICE_NAME, BAUDRATE, &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to init\");\r\n  }\r\n  else\r\n  {\r\n    Serial.print(\"Succeeded to init : \");\r\n    Serial.println(BAUDRATE);  \r\n  }\r\n\r\n  result = dxl_wb.ping(dxl_id, &model_number, &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to ping\");\r\n  }\r\n  else\r\n  {\r\n    Serial.println(\"Succeeded to ping\");\r\n    Serial.print(\"id : \");\r\n    Serial.print(dxl_id);\r\n    Serial.print(\" model_number : \");\r\n    Serial.println(model_number);\r\n  }\r\n\r\n  result = dxl_wb.currentBasedPositionMode(dxl_id, 30, &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to change current based position mode\");\r\n  }\r\n  else\r\n  {\r\n    Serial.println(\"Succeed to change current based position mode\");\r\n    Serial.println(\"Dynamixel is moving...\");\r\n\r\n    for (int count = 0; count < 3; count++)\r\n    {\r\n      dxl_wb.goalPosition(dxl_id, (int32_t)0);\r\n      delay(3000);\r\n\r\n      dxl_wb.goalPosition(dxl_id, (int32_t)2048);\r\n      delay(3000);\r\n    }\r\n  }\r\n}\r\n\r\nvoid loop() \r\n{\r\n\r\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/08. DynamixelWorkbench/k_Read_Write/k_Read_Write.ino",
    "content": "/*******************************************************************************\r\n* Copyright 2016 ROBOTIS CO., LTD.\r\n*\r\n* Licensed under the Apache License, Version 2.0 (the \"License\");\r\n* you may not use this file except in compliance with the License.\r\n* You may obtain a copy of the License at\r\n*\r\n*     http://www.apache.org/licenses/LICENSE-2.0\r\n*\r\n* Unless required by applicable law or agreed to in writing, software\r\n* distributed under the License is distributed on an \"AS IS\" BASIS,\r\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n* See the License for the specific language governing permissions and\r\n* limitations under the License.\r\n*******************************************************************************/\r\n\r\n/* Authors: Taehun Lim (Darby) */\r\n\r\n#include <DynamixelWorkbench.h>\r\n\r\n#if defined(__OPENCM904__)\r\n  #define DEVICE_NAME \"3\" //Dynamixel on Serial3(USART3)  <-OpenCM 485EXP\r\n#elif defined(__OPENCR__)\r\n  #define DEVICE_NAME \"\"\r\n#endif   \r\n\r\n#define BAUDRATE  57600\r\n#define DXL_ID    1\r\n\r\nDynamixelWorkbench dxl_wb;\r\n\r\nvoid setup() \r\n{\r\n  Serial.begin(57600);\r\n  while(!Serial); // Wait for Opening Serial Monitor\r\n\r\n  const char *log;\r\n  bool result = false;\r\n\r\n  uint8_t dxl_id = DXL_ID;\r\n  uint16_t model_number = 0;\r\n\r\n  result = dxl_wb.init(DEVICE_NAME, BAUDRATE, &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to init\");\r\n  }\r\n  else\r\n  {\r\n    Serial.print(\"Succeeded to init : \");\r\n    Serial.println(BAUDRATE);  \r\n  }\r\n\r\n  result = dxl_wb.ping(dxl_id, &model_number, &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to ping\");\r\n  }\r\n  else\r\n  {\r\n    Serial.println(\"Succeeded to ping\");\r\n    Serial.print(\"id : \");\r\n    Serial.print(dxl_id);\r\n    Serial.print(\" model_number : \");\r\n    Serial.println(model_number);\r\n  }\r\n\r\n  result = dxl_wb.itemWrite(dxl_id, \"LED\", 1, &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to LED On\");\r\n  }\r\n  else\r\n  {\r\n    Serial.println(\"Succeed to LED On\");\r\n  }\r\n\r\n  int32_t get_data = 0;\r\n  result = dxl_wb.itemRead(dxl_id, \"Present_Position\", &get_data, &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to get present position\");\r\n  }\r\n  else\r\n  {\r\n    Serial.print(\"Succeed to get present position(value : \");\r\n    Serial.print(get_data);\r\n    Serial.println(\")\");\r\n  }\r\n}\r\n\r\nvoid loop() \r\n{\r\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/08. DynamixelWorkbench/l_Sync_Write/l_Sync_Write.ino",
    "content": "/*******************************************************************************\r\n* Copyright 2016 ROBOTIS CO., LTD.\r\n*\r\n* Licensed under the Apache License, Version 2.0 (the \"License\");\r\n* you may not use this file except in compliance with the License.\r\n* You may obtain a copy of the License at\r\n*\r\n*     http://www.apache.org/licenses/LICENSE-2.0\r\n*\r\n* Unless required by applicable law or agreed to in writing, software\r\n* distributed under the License is distributed on an \"AS IS\" BASIS,\r\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n* See the License for the specific language governing permissions and\r\n* limitations under the License.\r\n*******************************************************************************/\r\n\r\n/* Authors: Taehun Lim (Darby) */\r\n\r\n#include <DynamixelWorkbench.h>\r\n\r\n#if defined(__OPENCM904__)\r\n  #define DEVICE_NAME \"3\" //Dynamixel on Serial3(USART3)  <-OpenCM 485EXP\r\n#elif defined(__OPENCR__)\r\n  #define DEVICE_NAME \"\"\r\n#endif   \r\n\r\n#define BAUDRATE  57600\r\n#define DXL_ID_1  1\r\n#define DXL_ID_2  2\r\n\r\nDynamixelWorkbench dxl_wb;\r\n\r\nint32_t goal_position[2] = {0, 1023};\r\n\r\nconst uint8_t handler_index = 0;\r\n\r\nvoid setup() \r\n{\r\n  Serial.begin(57600);\r\n  // while(!Serial); // Wait for Opening Serial Monitor\r\n\r\n  const char *log;\r\n  bool result = false;\r\n\r\n  uint16_t model_number = 0;\r\n  uint8_t dxl_id[2] = {DXL_ID_1, DXL_ID_2};\r\n\r\n  result = dxl_wb.init(DEVICE_NAME, BAUDRATE, &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to init\");\r\n  }\r\n  else\r\n  {\r\n    Serial.print(\"Succeeded to init : \");\r\n    Serial.println(BAUDRATE);  \r\n  }\r\n\r\n  for (int cnt = 0; cnt < 2; cnt++)\r\n  {\r\n    result = dxl_wb.ping(dxl_id[cnt], &model_number, &log);\r\n    if (result == false)\r\n    {\r\n      Serial.println(log);\r\n      Serial.println(\"Failed to ping\");\r\n    }\r\n    else\r\n    {\r\n      Serial.println(\"Succeeded to ping\");\r\n      Serial.print(\"id : \");\r\n      Serial.print(dxl_id[cnt]);\r\n      Serial.print(\" model_number : \");\r\n      Serial.println(model_number);\r\n    }\r\n\r\n    result = dxl_wb.jointMode(dxl_id[cnt], 0, 0, &log);\r\n    if (result == false)\r\n    {\r\n      Serial.println(log);\r\n      Serial.println(\"Failed to change joint mode\");\r\n    }\r\n    else\r\n    {\r\n      Serial.println(\"Succeed to change joint mode\");\r\n    }\r\n  } \r\n\r\n  result = dxl_wb.addSyncWriteHandler(dxl_id[0], \"Goal_Position\", &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to add sync write handler\");\r\n  }\r\n}\r\n\r\nvoid loop() \r\n{  \r\n  const char *log;\r\n  bool result = false;\r\n  result = dxl_wb.syncWrite(handler_index, &goal_position[0], &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to sync write position\");\r\n  }\r\n\r\n  delay(3000);\r\n\r\n  swap(goal_position);\r\n}\r\n\r\nvoid swap(int32_t *array)\r\n{\r\n  int32_t tmp = array[0];\r\n  array[0] = array[1];\r\n  array[1] = tmp;\r\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/08. DynamixelWorkbench/m_Sync_Read_Write/m_Sync_Read_Write.ino",
    "content": "/*******************************************************************************\r\n* Copyright 2016 ROBOTIS CO., LTD.\r\n*\r\n* Licensed under the Apache License, Version 2.0 (the \"License\");\r\n* you may not use this file except in compliance with the License.\r\n* You may obtain a copy of the License at\r\n*\r\n*     http://www.apache.org/licenses/LICENSE-2.0\r\n*\r\n* Unless required by applicable law or agreed to in writing, software\r\n* distributed under the License is distributed on an \"AS IS\" BASIS,\r\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n* See the License for the specific language governing permissions and\r\n* limitations under the License.\r\n*******************************************************************************/\r\n\r\n/* Authors: Taehun Lim (Darby) */\r\n\r\n#include <DynamixelWorkbench.h>\r\n\r\n#if defined(__OPENCM904__)\r\n  #define DEVICE_NAME \"3\" //Dynamixel on Serial3(USART3)  <-OpenCM 485EXP\r\n#elif defined(__OPENCR__)\r\n  #define DEVICE_NAME \"\"\r\n#endif   \r\n\r\n#define BAUDRATE  57600\r\n#define DXL_ID_1  1\r\n#define DXL_ID_2  2\r\n\r\nDynamixelWorkbench dxl_wb;\r\n\r\nuint8_t dxl_id[2] = {DXL_ID_1, DXL_ID_2};\r\nint32_t goal_position[2] = {0, 1023};\r\n\r\nconst uint8_t handler_index = 0;\r\n\r\nvoid setup() \r\n{\r\n  Serial.begin(57600);\r\n  // while(!Serial); // Wait for Opening Serial Monitor\r\n\r\n  const char *log;\r\n  bool result = false;\r\n\r\n  uint16_t model_number = 0;\r\n\r\n  result = dxl_wb.init(DEVICE_NAME, BAUDRATE, &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to init\");\r\n  }\r\n  else\r\n  {\r\n    Serial.print(\"Succeeded to init : \");\r\n    Serial.println(BAUDRATE);  \r\n  }\r\n\r\n  for (int cnt = 0; cnt < 2; cnt++)\r\n  {\r\n    result = dxl_wb.ping(dxl_id[cnt], &model_number, &log);\r\n    if (result == false)\r\n    {\r\n      Serial.println(log);\r\n      Serial.println(\"Failed to ping\");\r\n    }\r\n    else\r\n    {\r\n      Serial.println(\"Succeeded to ping\");\r\n      Serial.print(\"id : \");\r\n      Serial.print(dxl_id[cnt]);\r\n      Serial.print(\" model_number : \");\r\n      Serial.println(model_number);\r\n    }\r\n\r\n    result = dxl_wb.jointMode(dxl_id[cnt], 0, 0, &log);\r\n    if (result == false)\r\n    {\r\n      Serial.println(log);\r\n      Serial.println(\"Failed to change joint mode\");\r\n    }\r\n    else\r\n    {\r\n      Serial.println(\"Succeed to change joint mode\");\r\n    }\r\n  } \r\n\r\n  result = dxl_wb.addSyncWriteHandler(dxl_id[0], \"Goal_Position\", &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to add sync write handler\");\r\n  }\r\n\r\n  result = dxl_wb.addSyncReadHandler(dxl_id[0], \"Present_Position\", &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to add sync read handler\");\r\n  }\r\n}\r\n\r\nvoid loop() \r\n{  \r\n  const char *log;\r\n  bool result = false;\r\n\r\n  int32_t present_position[2] = {0, 0};\r\n\r\n  result = dxl_wb.syncWrite(handler_index, &goal_position[0], &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to sync write position\");\r\n  }\r\n\r\n  do\r\n  {\r\n    result = dxl_wb.syncRead(handler_index, &log);\r\n    if (result == false)\r\n    {\r\n      Serial.println(log);\r\n      Serial.println(\"Failed to sync read position\");\r\n    }\r\n\r\n    result = dxl_wb.getSyncReadData(handler_index, &present_position[0], &log);\r\n    if (result == false)\r\n    {\r\n      Serial.println(log);\r\n    }\r\n    else\r\n    {\r\n      Serial.print(\"[ID \");\r\n      Serial.print(dxl_id[0]);\r\n      Serial.print(\" ]\");\r\n      Serial.print(\" Goal Position : \");\r\n      Serial.print(goal_position[0]);\r\n      Serial.print(\" Present Position : \");\r\n      Serial.print(present_position[0]);\r\n      Serial.print(\" [ID \");\r\n      Serial.print(dxl_id[1]);\r\n      Serial.print(\" ]\");\r\n      Serial.print(\" Goal Position : \");\r\n      Serial.print(goal_position[1]);\r\n      Serial.print(\" Present Position : \");\r\n      Serial.println(present_position[1]);\r\n    }\r\n\r\n  }while(abs(goal_position[0] - present_position[0]) > 15 && \r\n        abs(goal_position[1] - present_position[1]) > 15);\r\n\r\n  swap(goal_position);\r\n}\r\n\r\nvoid swap(int32_t *array)\r\n{\r\n  int32_t tmp = array[0];\r\n  array[0] = array[1];\r\n  array[1] = tmp;\r\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/08. DynamixelWorkbench/n_Bulk_Read_Write/n_Bulk_Read_Write.ino",
    "content": "/*******************************************************************************\r\n* Copyright 2016 ROBOTIS CO., LTD.\r\n*\r\n* Licensed under the Apache License, Version 2.0 (the \"License\");\r\n* you may not use this file except in compliance with the License.\r\n* You may obtain a copy of the License at\r\n*\r\n*     http://www.apache.org/licenses/LICENSE-2.0\r\n*\r\n* Unless required by applicable law or agreed to in writing, software\r\n* distributed under the License is distributed on an \"AS IS\" BASIS,\r\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n* See the License for the specific language governing permissions and\r\n* limitations under the License.\r\n*******************************************************************************/\r\n\r\n/* Authors: Taehun Lim (Darby) */\r\n\r\n#include <DynamixelWorkbench.h>\r\n\r\n#if defined(__OPENCM904__)\r\n  #define DEVICE_NAME \"3\" //Dynamixel on Serial3(USART3)  <-OpenCM 485EXP\r\n#elif defined(__OPENCR__)\r\n  #define DEVICE_NAME \"\"\r\n#endif   \r\n\r\n#define BAUDRATE  57600\r\n#define DXL_ID_1  1\r\n#define DXL_ID_2  2\r\n\r\nDynamixelWorkbench dxl_wb;\r\n\r\nuint8_t dxl_id[2] = {DXL_ID_1, DXL_ID_2};\r\nint32_t goal_position[2] = {0, 1023};\r\nint32_t led[2] = {0, 1};\r\n\r\nconst uint8_t handler_index = 0;\r\n\r\nvoid setup() \r\n{\r\n  Serial.begin(57600);\r\n  // while(!Serial); // Wait for Opening Serial Monitor\r\n\r\n  const char *log;\r\n  bool result = false;\r\n\r\n  uint16_t model_number = 0;\r\n\r\n  result = dxl_wb.init(DEVICE_NAME, BAUDRATE, &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to init\");\r\n  }\r\n  else\r\n  {\r\n    Serial.print(\"Succeeded to init : \");\r\n    Serial.println(BAUDRATE);  \r\n  }\r\n\r\n  for (int cnt = 0; cnt < 2; cnt++)\r\n  {\r\n    result = dxl_wb.ping(dxl_id[cnt], &model_number, &log);\r\n    if (result == false)\r\n    {\r\n      Serial.println(log);\r\n      Serial.println(\"Failed to ping\");\r\n    }\r\n    else\r\n    {\r\n      Serial.println(\"Succeeded to ping\");\r\n      Serial.print(\"id : \");\r\n      Serial.print(dxl_id[cnt]);\r\n      Serial.print(\" model_number : \");\r\n      Serial.println(model_number);\r\n    }\r\n\r\n    result = dxl_wb.jointMode(dxl_id[cnt], 0, 0, &log);\r\n    if (result == false)\r\n    {\r\n      Serial.println(log);\r\n      Serial.println(\"Failed to change joint mode\");\r\n    }\r\n    else\r\n    {\r\n      Serial.println(\"Succeed to change joint mode\");\r\n    }\r\n  } \r\n\r\n  result = dxl_wb.initBulkWrite(&log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n  }\r\n  else\r\n  {\r\n    Serial.println(log);\r\n  }\r\n\r\n  result = dxl_wb.initBulkRead(&log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n  }\r\n  else\r\n  {\r\n    Serial.println(log);\r\n  }\r\n\r\n  result = dxl_wb.addBulkReadParam(dxl_id[0], \"Present_Position\", &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to add bulk read position param\");\r\n  }\r\n  else\r\n  {\r\n    Serial.println(log);\r\n  }\r\n\r\n  result = dxl_wb.addBulkReadParam(dxl_id[1], \"LED\", &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to add bulk read led param\");\r\n  }\r\n  else\r\n  {\r\n    Serial.println(log);\r\n  }\r\n}\r\n\r\nvoid loop() \r\n{  \r\n  const char *log;\r\n  bool result = false;\r\n  \r\n  int32_t get_data[2] = {0, 0};\r\n\r\n  result = dxl_wb.addBulkWriteParam(dxl_id[0], \"Goal_Position\", goal_position[0], &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to add bulk write position param\");\r\n  }\r\n  else\r\n  {\r\n    Serial.println(log);\r\n  }\r\n\r\n  result = dxl_wb.addBulkWriteParam(dxl_id[1], \"LED\", led[0], &log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to add bulk write led param\");\r\n  }\r\n  else\r\n  {\r\n    Serial.println(log);\r\n  }\r\n\r\n  result = dxl_wb.bulkWrite(&log);\r\n  if (result == false)\r\n  {\r\n    Serial.println(log);\r\n    Serial.println(\"Failed to bulk write\");\r\n  }\r\n\r\n  do\r\n  {\r\n    result = dxl_wb.bulkRead(&log);\r\n    if (result == false)\r\n    {\r\n      Serial.println(log);\r\n      Serial.println(\"Failed to bulk read\");\r\n    }\r\n\r\n    result = dxl_wb.getBulkReadData(&get_data[0], &log);\r\n    if (result == false)\r\n    {\r\n      Serial.println(log);\r\n    }\r\n    else\r\n    {\r\n      Serial.print(\"[ID \");\r\n      Serial.print(dxl_id[0]);\r\n      Serial.print(\" ]\");\r\n      Serial.print(\" Goal Position : \");\r\n      Serial.print(goal_position[0]);\r\n      Serial.print(\" Present Position : \");\r\n      Serial.print(get_data[0]);\r\n      Serial.print(\" [ID \");\r\n      Serial.print(dxl_id[1]);\r\n      Serial.print(\" ]\");\r\n      Serial.print(\" Goal LED : \");\r\n      Serial.println(get_data[1]);\r\n    }\r\n\r\n  }while(abs(goal_position[0] - get_data[0]) > 15);\r\n\r\n  swap(goal_position);\r\n  swap(led);\r\n}\r\n\r\nvoid swap(int32_t *array)\r\n{\r\n  int32_t tmp = array[0];\r\n  array[0] = array[1];\r\n  array[1] = tmp;\r\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/08. DynamixelWorkbench/o_Find_Dynamixel/o_Find_Dynamixel.ino",
    "content": "/*******************************************************************************\r\n* Copyright 2016 ROBOTIS CO., LTD.\r\n*\r\n* Licensed under the Apache License, Version 2.0 (the \"License\");\r\n* you may not use this file except in compliance with the License.\r\n* You may obtain a copy of the License at\r\n*\r\n*     http://www.apache.org/licenses/LICENSE-2.0\r\n*\r\n* Unless required by applicable law or agreed to in writing, software\r\n* distributed under the License is distributed on an \"AS IS\" BASIS,\r\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n* See the License for the specific language governing permissions and\r\n* limitations under the License.\r\n*******************************************************************************/\r\n\r\n/* Authors: Taehun Lim (Darby) */\r\n\r\n#include <DynamixelWorkbench.h>\r\n\r\n#if defined(__OPENCM904__)\r\n  #define DEVICE_NAME \"3\" //Dynamixel on Serial3(USART3)  <-OpenCM 485EXP\r\n#elif defined(__OPENCR__)\r\n  #define DEVICE_NAME \"\"\r\n#endif   \r\n\r\n#define BAUDRATE_NUM 7\r\n\r\nDynamixelWorkbench dxl_wb;\r\n\r\nvoid setup() \r\n{\r\n  Serial.begin(57600);\r\n  while(!Serial); // Wait for Opening Serial Monitor\r\n\r\n  const char *log;\r\n  bool result = false;\r\n\r\n  uint8_t scanned_id[100];\r\n  uint8_t dxl_cnt = 0;\r\n\r\n  uint32_t baudrate[BAUDRATE_NUM] = {9600, 57600, 115200, 1000000, 2000000, 3000000, 4000000};\r\n  uint8_t range = 253;\r\n\r\n  uint8_t index = 0;\r\n\r\n  while (index < BAUDRATE_NUM)\r\n  {\r\n    result = dxl_wb.init(DEVICE_NAME, baudrate[index], &log);\r\n    if (result == false)\r\n    {\r\n      Serial.println(log);\r\n      Serial.println(\"Failed to init\");\r\n    }\r\n    else\r\n    {\r\n      Serial.print(\"Succeed to init : \");\r\n      Serial.println(baudrate[index]);  \r\n    }\r\n\r\n    dxl_cnt = 0;\r\n    for (uint8_t num = 0; num < 100; num++) scanned_id[num] = 0;\r\n\r\n    result = dxl_wb.scan(scanned_id, &dxl_cnt, range, &log);\r\n    if (result == false)\r\n    {\r\n      Serial.println(log);\r\n      Serial.println(\"Failed to scan\");\r\n    }\r\n    else\r\n    {\r\n      Serial.print(\"Find \");\r\n      Serial.print(dxl_cnt);\r\n      Serial.println(\" Dynamixels\");\r\n\r\n      for (int cnt = 0; cnt < dxl_cnt; cnt++)\r\n      {\r\n        Serial.print(\"id : \");\r\n        Serial.print(scanned_id[cnt]);\r\n        Serial.print(\" model name : \");\r\n        Serial.println(dxl_wb.getModelName(scanned_id[cnt]));\r\n      }\r\n    } \r\n\r\n    index++;\r\n  }\r\n}\r\n\r\nvoid loop() \r\n{\r\n\r\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/08. DynamixelWorkbench/p_Monitor/p_Monitor.ino",
    "content": "/*******************************************************************************\r\n* Copyright 2016 ROBOTIS CO., LTD.\r\n*\r\n* Licensed under the Apache License, Version 2.0 (the \"License\");\r\n* you may not use this file except in compliance with the License.\r\n* You may obtain a copy of the License at\r\n*\r\n*     http://www.apache.org/licenses/LICENSE-2.0\r\n*\r\n* Unless required by applicable law or agreed to in writing, software\r\n* distributed under the License is distributed on an \"AS IS\" BASIS,\r\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n* See the License for the specific language governing permissions and\r\n* limitations under the License.\r\n*******************************************************************************/\r\n\r\n/* Authors: Taehun Lim (Darby) */\r\n\r\n#include <DynamixelWorkbench.h>\r\n\r\n#if defined(__OPENCM904__)\r\n  #define DEVICE_NAME \"3\" //Dynamixel on Serial3(USART3)  <-OpenCM 485EXP\r\n#elif defined(__OPENCR__)\r\n  #define DEVICE_NAME \"\"\r\n#endif   \r\n\r\n#define STRING_BUF_NUM 64\r\nString cmd[STRING_BUF_NUM];\r\n\r\nDynamixelWorkbench dxl_wb;\r\nuint8_t get_id[16];\r\nuint8_t scan_cnt = 0;\r\nuint8_t ping_cnt = 0;\r\n\r\nbool isAvailableID(uint8_t id);\r\nvoid split(String data, char separator, String* temp);\r\nvoid printInst();\r\n\r\nvoid setup() \r\n{\r\n  Serial.begin(57600);\r\n  while(!Serial); // Open a Serial Monitor  \r\n\r\n  printInst();\r\n}\r\n\r\nvoid loop() \r\n{\r\n  const char *log = NULL;\r\n  bool result = false;\r\n\r\n  if (Serial.available())\r\n  {\r\n    String read_string = Serial.readStringUntil('\\n');\r\n    Serial.println(\"[CMD] : \" + String(read_string));\r\n\r\n    read_string.trim();\r\n\r\n    split(read_string, ' ', cmd);\r\n\r\n    if (cmd[0] == \"help\")\r\n    {\r\n      printInst();\r\n    }\r\n    else if (cmd[0] == \"begin\")\r\n    {\r\n      if (cmd[1] == '\\0')\r\n        cmd[1] = String(\"57600\");\r\n\r\n      uint32_t baud = cmd[1].toInt();\r\n      result = dxl_wb.init(DEVICE_NAME, baud);\r\n      if (result == false)\r\n      {\r\n        Serial.println(log);\r\n        Serial.println(\"Failed to init\");\r\n      }\r\n      else\r\n      {\r\n        Serial.print(\"Succeed to init : \");\r\n        Serial.println(baud);  \r\n      }\r\n    }\r\n    else if (cmd[0] == \"end\")\r\n    {        \r\n      return;\r\n    }\r\n    else if (cmd[0] == \"scan\")\r\n    { \r\n      if (cmd[1] == '\\0')\r\n        cmd[1] = String(\"253\");\r\n\r\n      uint8_t range = cmd[1].toInt();\r\n      result = dxl_wb.scan(get_id, &scan_cnt, range);\r\n      if (result == false)\r\n      {\r\n        Serial.println(log);\r\n        Serial.println(\"Failed to scan\");\r\n      }\r\n      else\r\n      {\r\n        Serial.print(\"Find \");\r\n        Serial.print(scan_cnt);\r\n        Serial.println(\" Dynamixels\");\r\n\r\n        for (int cnt = 0; cnt < scan_cnt; cnt++)\r\n        {\r\n          Serial.print(\"id : \");\r\n          Serial.print(get_id[cnt]);\r\n          Serial.print(\" model name : \");\r\n          Serial.println(dxl_wb.getModelName(get_id[cnt]));\r\n        }\r\n      }  \r\n    }\r\n    else if (cmd[0] == \"ping\")\r\n    {\r\n      if (cmd[1] == '\\0')\r\n        cmd[1] = String(\"1\");\r\n\r\n      get_id[ping_cnt] = cmd[1].toInt();\r\n      uint16_t model_number = 0;\r\n\r\n      result = dxl_wb.ping(get_id[ping_cnt], &model_number, &log);\r\n      if (result == false)\r\n      {\r\n        Serial.println(log);\r\n        Serial.println(\"Failed to ping\");\r\n      }\r\n      else\r\n      {\r\n        ping_cnt++;\r\n\r\n        Serial.println(\"Succeed to ping\");\r\n        Serial.print(\"id : \");\r\n        Serial.print(get_id[ping_cnt]);\r\n        Serial.print(\" model_number : \");\r\n        Serial.println(model_number);\r\n      }\r\n    }\r\n    else if (isAvailableID(cmd[1].toInt()))\r\n    {\r\n      if (cmd[0] == \"control_table\")\r\n      {\r\n        uint8_t id = cmd[1].toInt();\r\n\r\n        const ControlItem *control_item =  dxl_wb.getControlTable(id);\r\n        uint8_t the_number_of_control_item = dxl_wb.getTheNumberOfControlItem(id);\r\n\r\n        uint16_t last_register_addr = control_item[the_number_of_control_item-1].address;\r\n        uint16_t last_register_addr_length = control_item[the_number_of_control_item-1].data_length;\r\n\r\n        uint32_t getAllRegisteredData[last_register_addr+last_register_addr_length];\r\n\r\n        if (control_item != NULL)\r\n        {\r\n          result = dxl_wb.readRegister(id, (uint16_t)0, last_register_addr+last_register_addr_length, getAllRegisteredData, &log);\r\n          if (result == false)\r\n          {\r\n            Serial.println(log);\r\n            return;\r\n          }\r\n          else\r\n          {\r\n            for (int index = 0; index < the_number_of_control_item; index++)\r\n            {\r\n              uint32_t data = 0;\r\n\r\n              if (dxl_wb.getProtocolVersion() == 2.0f)\r\n              {\r\n                data = getAllRegisteredData[control_item[index].address];\r\n                Serial.print(\"\\t\");\r\n                Serial.print(control_item[index].item_name);\r\n                Serial.print(\" : \");\r\n                Serial.println(data);\r\n              }\r\n              else if (dxl_wb.getProtocolVersion() == 1.0f)\r\n              {\r\n                switch (control_item[index].data_length)\r\n                {\r\n                  case BYTE:\r\n                    data = getAllRegisteredData[control_item[index].address];\r\n                    Serial.print(\"\\t\");\r\n                    Serial.print(control_item[index].item_name);\r\n                    Serial.print(\" : \");\r\n                    Serial.println(data);\r\n                    break;\r\n\r\n                  case WORD:\r\n                    data = DXL_MAKEWORD(getAllRegisteredData[control_item[index].address], getAllRegisteredData[control_item[index].address+1]);\r\n                    Serial.print(\"\\t\");\r\n                    Serial.print(control_item[index].item_name);\r\n                    Serial.print(\" : \");\r\n                    Serial.println(data);\r\n                    break;\r\n\r\n                  case DWORD:\r\n                    data = DXL_MAKEDWORD(DXL_MAKEWORD(getAllRegisteredData[control_item[index].address],   getAllRegisteredData[control_item[index].address+1]),\r\n                                          DXL_MAKEWORD(getAllRegisteredData[control_item[index].address+2], getAllRegisteredData[control_item[index].address+3]));\r\n                    Serial.print(\"\\t\");\r\n                    Serial.print(control_item[index].item_name);\r\n                    Serial.print(\" : \");\r\n                    Serial.println(data);\r\n                    break;\r\n\r\n                  default:\r\n                    data = getAllRegisteredData[control_item[index].address];\r\n                    break;\r\n                } \r\n              }\r\n            }\r\n          }\r\n        }\r\n      }\r\n      else if (cmd[0] == \"sync_write_handler\")\r\n      {\r\n        static uint8_t sync_write_handler_index = 0;\r\n        uint8_t id = cmd[1].toInt();\r\n\r\n        result = dxl_wb.addSyncWriteHandler(id, cmd[2].c_str(), &log);\r\n        if (result == false)\r\n        {\r\n          Serial.println(log);\r\n          Serial.print(\"Failed to add sync write handler\\n\");\r\n          return;\r\n        }\r\n        else\r\n        {\r\n          Serial.println(log);\r\n          Serial.print(\"sync_write_handler_index = \");\r\n          Serial.println(sync_write_handler_index);\r\n        }\r\n      }\r\n      else if (cmd[0] == \"sync_read_handler\")\r\n      {\r\n        static uint8_t sync_read_handler_index = 0;\r\n        uint8_t id = cmd[1].toInt();        \r\n\r\n        result = dxl_wb.addSyncReadHandler(id, cmd[2].c_str(), &log);\r\n        if (result == false)\r\n        {\r\n          Serial.println(log);\r\n          Serial.print(\"Failed to add sync write handler\\n\");\r\n          return;\r\n        }\r\n        else\r\n        {\r\n          Serial.println(log);\r\n          Serial.print(\"sync_read_handler_index = \");\r\n          Serial.println(sync_read_handler_index);\r\n        }\r\n      }\r\n      else if (cmd[0] == \"bulk_write_handler\")\r\n      {\r\n        result = dxl_wb.initBulkWrite(&log);\r\n        if (result == false)\r\n        {\r\n          Serial.println(log);\r\n          Serial.print(\"Failed to init bulk write handler\\n\");\r\n          return;\r\n        }\r\n        else\r\n          Serial.println(log);\r\n      }\r\n      else if (cmd[0] == \"bulk_write_param\")\r\n      {\r\n        uint8_t id = cmd[1].toInt();\r\n\r\n        result = dxl_wb.addBulkWriteParam(id, cmd[2].c_str(), cmd[3].toInt(), &log);\r\n        if (result == false)\r\n        {\r\n          Serial.println(log);\r\n          Serial.print(\"Failed to add param for bulk write\\n\");\r\n          return;\r\n        }\r\n        else\r\n          Serial.println(log);\r\n      }\r\n      else if (cmd[0] == \"bulk_write\")\r\n      {\r\n        result = dxl_wb.bulkWrite(&log);\r\n        if (result == false)\r\n        {\r\n          Serial.println(log);\r\n          Serial.print(\"Failed to bulk write\\n\");\r\n          return;\r\n        }\r\n        else\r\n          Serial.println(log);\r\n      }\r\n      else if (cmd[0] == \"bulk_read_handler\")\r\n      {\r\n        result = dxl_wb.initBulkRead(&log);\r\n        if (result == false)\r\n        {\r\n          Serial.println(log);\r\n          Serial.print(\"Failed to init bulk read handler\\n\");\r\n          return;\r\n        }\r\n        else\r\n          Serial.println(log);\r\n      }\r\n      else if (cmd[0] == \"bulk_read_param\")\r\n      {\r\n        uint8_t id = cmd[1].toInt();\r\n        result = dxl_wb.addBulkReadParam(id, cmd[2].c_str(), &log);\r\n        if (result == false)\r\n        {\r\n          Serial.println(log);\r\n          Serial.print(\"Failed to add param for bulk read\\n\");\r\n          return;\r\n        }\r\n        else\r\n          Serial.println(log);\r\n      }\r\n      else if (cmd[0] == \"bulk_read\")\r\n      {\r\n        result = dxl_wb.bulkRead(&log);\r\n        if (result == false)\r\n        {\r\n          Serial.println(log);\r\n          Serial.println(\"Failed to bulk read\");\r\n          return;\r\n        }\r\n        else\r\n          printf(\"%s\\n\", log);\r\n\r\n        int32_t get_data[dxl_wb.getTheNumberOfBulkReadParam()];\r\n        result = dxl_wb.getBulkReadData(&get_data[0], &log);\r\n        if (result == false)\r\n        {\r\n          Serial.println(log);\r\n          Serial.println(\"Failed to get bulk read data\");\r\n          return;\r\n        }\r\n        else\r\n        {\r\n          Serial.println(log);\r\n          for (uint8_t index = 0; index < dxl_wb.getTheNumberOfBulkReadParam(); index++)\r\n          {\r\n            Serial.print(\"data[\");\r\n            Serial.print(index);\r\n            Serial.print(\"] : \");\r\n            Serial.print(get_data[index]);\r\n          }\r\n          Serial.println(\"\");\r\n        }\r\n\r\n        dxl_wb.clearBulkReadParam();\r\n      }\r\n      else if (isAvailableID(cmd[1].toInt()) && isAvailableID(cmd[2].toInt()))\r\n      {\r\n        if (cmd[0] == \"sync_write\")\r\n        {\r\n          uint8_t id_1 = cmd[1].toInt();\r\n          uint8_t id_2 = cmd[2].toInt();\r\n          uint8_t id[2] = {id_1, id_2};\r\n          uint8_t id_num = 2;\r\n\r\n          int32_t data[2] = {0, 0};\r\n          data[0] = cmd[4].toInt();\r\n          data[1] = cmd[5].toInt();\r\n\r\n          uint8_t handler_index = cmd[3].toInt();\r\n\r\n          result = dxl_wb.syncWrite(handler_index, id, id_num, (int32_t *)data, 1, &log);\r\n          if (result == false)\r\n          {\r\n            Serial.println(log);\r\n            return;\r\n          }\r\n          else\r\n            Serial.println(log);\r\n        }\r\n        else if (cmd[0] == \"sync_read\")\r\n        {\r\n          uint8_t id_1 = cmd[1].toInt();\r\n          uint8_t id_2 = cmd[2].toInt();\r\n          uint8_t id[2] = {id_1, id_2};\r\n          uint8_t id_num = 2;\r\n\r\n          int32_t data[2] = {0, 0};\r\n          uint8_t handler_index = cmd[3].toInt();\r\n\r\n          result = dxl_wb.syncRead(handler_index, id, id_num, &log);\r\n          if (result == false)\r\n          {\r\n            Serial.println(log);\r\n            return;\r\n          }\r\n          else\r\n          {\r\n            Serial.println(log);\r\n          }\r\n\r\n          result = dxl_wb.getSyncReadData(handler_index, id, id_num, data, &log);\r\n          if (result == false)\r\n          {\r\n            Serial.println(log);\r\n            return;\r\n          }\r\n          else\r\n          {\r\n            Serial.println(log);\r\n            Serial.print(\"[ID \");\r\n            Serial.print(cmd[1].toInt());\r\n            Serial.print(\" ]\");\r\n            Serial.print(\" data : \");\r\n            Serial.println(data[0]);\r\n            Serial.print(\"[ID \");\r\n            Serial.print(cmd[2].toInt());\r\n            Serial.print(\" ]\");\r\n            Serial.print(\" data : \");\r\n            Serial.println(data[0]);\r\n          }\r\n        }\r\n      }\r\n      else if (cmd[0] == \"id\")\r\n      {\r\n        uint8_t id     = cmd[1].toInt();\r\n        uint8_t new_id = cmd[2].toInt();\r\n\r\n        result = dxl_wb.changeID(id, new_id, &log);\r\n        if (result == false)\r\n        {\r\n          Serial.println(log);\r\n          return;\r\n        }\r\n        else\r\n        {\r\n          Serial.println(log);\r\n        }\r\n      }\r\n      else if (cmd[0] == \"baud\")\r\n      {\r\n        uint8_t  id       = cmd[1].toInt();\r\n        uint32_t  new_baud  = cmd[2].toInt();\r\n\r\n        result = dxl_wb.changeBaudrate(id, new_baud, &log);\r\n        if (result == false)\r\n        {\r\n          Serial.println(log);\r\n          return ;\r\n        }\r\n        else\r\n        {\r\n          result = dxl_wb.setBaudrate(new_baud, &log);\r\n          Serial.println(log);\r\n        }\r\n      }\r\n      else if (cmd[0] == \"torque_on\")\r\n      {\r\n        uint8_t id       = cmd[1].toInt();\r\n\r\n        result = dxl_wb.torqueOn(id, &log);\r\n        if (result == false)\r\n        {\r\n          Serial.println(log);\r\n          return;\r\n        }\r\n        else\r\n        {\r\n          Serial.println(log);\r\n        }\r\n      }\r\n      else if (cmd[0] == \"torque_off\")\r\n      {\r\n        uint8_t id       = cmd[1].toInt();\r\n\r\n        result = dxl_wb.torqueOff(id, &log);\r\n        if (result == false)\r\n        {\r\n          Serial.println(log);\r\n          return;\r\n        }\r\n        else\r\n        {\r\n          Serial.println(log);\r\n        }\r\n      }\r\n      else if (cmd[0] == \"joint\")\r\n      {\r\n        uint8_t id    = cmd[1].toInt();\r\n        uint16_t goal = cmd[2].toInt();\r\n\r\n        result = dxl_wb.jointMode(id, 0, 0, &log);\r\n        if (result == false)\r\n        {\r\n          Serial.println(log);\r\n          return;\r\n        }\r\n        else\r\n        {\r\n          Serial.println(log);\r\n        }\r\n\r\n        result = dxl_wb.goalPosition(id, (int32_t)goal, &log);\r\n        if (result == false)\r\n        {\r\n          Serial.println(log);\r\n          return;\r\n        }\r\n        else\r\n        {\r\n          Serial.println(log);\r\n        }\r\n      }\r\n      else if (cmd[0] == \"wheel\")\r\n      {\r\n        uint8_t id    = cmd[1].toInt();\r\n        int32_t goal  = cmd[2].toInt();\r\n\r\n        result = dxl_wb.wheelMode(id, 0, &log);\r\n        if (result == false)\r\n        {\r\n          Serial.println(log);\r\n          return;\r\n        }\r\n        else\r\n        {\r\n          Serial.println(log);\r\n        }\r\n\r\n        result = dxl_wb.goalVelocity(id, (int32_t)goal, &log);\r\n        if (result == false)\r\n        {\r\n          Serial.println(log);\r\n          return;\r\n        }\r\n        else\r\n        {\r\n          Serial.println(log);\r\n        }\r\n      }\r\n      else if (cmd[0] == \"write\")\r\n      {\r\n        uint8_t id = cmd[1].toInt();      \r\n        uint32_t value = cmd[3].toInt(); \r\n\r\n        result = dxl_wb.writeRegister(id, cmd[2].c_str(), value, &log);\r\n        if (result == false)\r\n        {\r\n          Serial.println(log);\r\n          Serial.println(\"Failed to write\");\r\n          return;\r\n        }\r\n        else\r\n        {\r\n          Serial.println(log);\r\n        }\r\n      }\r\n      else if (cmd[0] == \"read\")\r\n      {\r\n        uint8_t id = cmd[1].toInt();\r\n\r\n        int32_t data = 0;\r\n        \r\n        result = dxl_wb.readRegister(id, cmd[2].c_str(), &data, &log);\r\n        if (result == false)\r\n        {\r\n          Serial.println(log);\r\n          Serial.println(\"Failed to read\");\r\n          return;\r\n        }\r\n        else\r\n        {\r\n          Serial.println(log);\r\n          Serial.print(\"read data : \");\r\n          Serial.println(data);\r\n        }\r\n      }\r\n      else if (cmd[0] == \"reboot\")\r\n      {\r\n        uint8_t id = cmd[1].toInt();\r\n\r\n        result = dxl_wb.reboot(id, &log);\r\n        if (result == false)\r\n        {\r\n          Serial.println(log);\r\n          Serial.println(\"Failed to reboot\");\r\n          return;\r\n        }\r\n        else\r\n        {\r\n          Serial.println(log);\r\n        }\r\n      }\r\n      else if (cmd[0] == \"reset\")\r\n      {\r\n        uint8_t id = cmd[1].toInt();\r\n\r\n        result = dxl_wb.reset(id, &log);\r\n        if (result == false)\r\n        {\r\n          Serial.println(log);\r\n          Serial.println(\"Failed to reset\");\r\n          return;\r\n        }\r\n        else\r\n        {\r\n          Serial.println(log);\r\n        }\r\n      }\r\n      else \r\n      {\r\n        Serial.println(\"Wrong command\");\r\n      }\r\n    }\r\n    else \r\n    {\r\n      Serial.println(\"Please check ID\");\r\n    }\r\n  }\r\n}\r\n\r\nvoid split(String data, char separator, String* temp)\r\n{\r\n\tint cnt = 0;\r\n\tint get_index = 0;\r\n\r\n  String copy = data;\r\n  \r\n\twhile(true)\r\n\t{\r\n\t\tget_index = copy.indexOf(separator);\r\n\r\n\t\tif(-1 != get_index)\r\n\t\t{\r\n\t\t\ttemp[cnt] = copy.substring(0, get_index);\r\n\r\n\t\t\tcopy = copy.substring(get_index + 1);\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n      temp[cnt] = copy.substring(0, copy.length());\r\n\t\t\tbreak;\r\n\t\t}\r\n\t\t++cnt;\r\n\t}\r\n}\r\n\r\nbool isAvailableID(uint8_t id)\r\n{\r\n  for (int dxl_cnt = 0; dxl_cnt < (scan_cnt + ping_cnt); dxl_cnt++)\r\n  {\r\n    if (get_id[dxl_cnt] == id)\r\n      return true;\r\n  }\r\n\r\n  return false;\r\n}\r\n\r\nvoid printInst(void)\r\n{\r\n  Serial.print(\"-------------------------------------\\n\");\r\n  Serial.print(\"Set begin before scan or ping\\n\");\r\n  Serial.print(\"-------------------------------------\\n\");\r\n  Serial.print(\"help\\n\");\r\n  Serial.print(\"begin  (BAUD)\\n\");\r\n  Serial.print(\"scan   (RANGE)\\n\");\r\n  Serial.print(\"ping   (ID)\\n\");\r\n  Serial.print(\"control_table (ID)\\n\");\r\n  Serial.print(\"id     (ID) (NEW_ID)\\n\");\r\n  Serial.print(\"baud   (ID) (NEW_BAUD)\\n\");\r\n  Serial.print(\"torque_on (ID)\\n\");\r\n  Serial.print(\"torque_off (ID)\\n\");\r\n  Serial.print(\"joint  (ID) (GOAL_POSITION)\\n\");\r\n  Serial.print(\"wheel  (ID) (GOAL_VELOCITY)\\n\");\r\n  Serial.print(\"write  (ID) (ADDRESS_NAME) (DATA)\\n\");\r\n  Serial.print(\"read   (ID) (ADDRESS_NAME)\\n\");\r\n  Serial.print(\"sync_write_handler (Ref_ID) (ADDRESS_NAME)\\n\");\r\n  Serial.print(\"sync_write (ID_1) (ID_2) (HANDLER_INDEX) (PARAM_1) (PARAM_2)\\n\");\r\n  Serial.print(\"sync_read_handler (Ref_ID) (ADDRESS_NAME)\\n\");\r\n  Serial.print(\"sync_read (ID_1) (ID_2) (HANDLER_INDEX)\\n\");\r\n  Serial.print(\"bulk_write_handler\\n\");\r\n  Serial.print(\"bulk_write_param (ID) (ADDRESS_NAME) (PARAM)\\n\");\r\n  Serial.print(\"bulk_write\\n\");\r\n  Serial.print(\"bulk_read_handler\\n\");\r\n  Serial.print(\"bulk_read_param (ID) (ADDRESS_NAME)\\n\");\r\n  Serial.print(\"bulk_read\\n\");\r\n  Serial.print(\"reboot (ID) \\n\");\r\n  Serial.print(\"reset  (ID) \\n\");\r\n  Serial.print(\"end\\n\");\r\n  Serial.print(\"-------------------------------------\\n\");\r\n  Serial.print(\"Press Enter Key\\n\");\r\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/09. IMU/IMU_Read_AccRAW/IMU_Read_AccRAW.ino",
    "content": "/*\n  Range   : +/- 2 g\n  Scale   : 16384 = 1 g\n */\n\n#include <IMU.h>\n\n\ncIMU    IMU;\n\n\n\nuint8_t   led_tog = 0;\nuint8_t   led_pin = 13;\n\nvoid setup()\n{\n  Serial.begin(115200);\n\n  IMU.begin();\n\n  pinMode( led_pin, OUTPUT );\n}\n\n\n\n\n\nvoid loop()\n{\n  static uint32_t tTime[3];\n  static uint32_t imu_time = 0;\n\n\n  if( (millis()-tTime[0]) >= 500 )\n  {\n    tTime[0] = millis();\n\n    digitalWrite( led_pin, led_tog );\n    led_tog ^= 1;\n  }\n\n  tTime[2] = micros();\n  if( IMU.update() > 0 ) imu_time = micros()-tTime[2];\n\n\n\n  if( (millis()-tTime[1]) >= 50 )\n  {\n    tTime[1] = millis();\n\n    Serial.print(imu_time);\n    Serial.print(\" \\t\");\n    Serial.print(IMU.accRaw[0]);    // ACC X\n    Serial.print(\" \\t\");\n    Serial.print(IMU.accRaw[1]);    // ACC Y\n    Serial.print(\" \\t\");\n    Serial.print(IMU.accRaw[2]);    // ACC Z\n    Serial.println(\" \");\n  }\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/09. IMU/IMU_Read_GyroRAW/IMU_Read_GyroRAW.ino",
    "content": "/*\n  Range   : +/- 2000 deg/sec\n  Scale   : 16.4 = 1 deg/sec\n */\n\n#include <IMU.h>\n\n\ncIMU    IMU;\n\n\nuint8_t   led_tog = 0;\nuint8_t   led_pin = 13;\n\nvoid setup()\n{\n  Serial.begin(115200);\n\n  IMU.begin();\n\n  pinMode( led_pin, OUTPUT );\n}\n\n\n\n\n\nvoid loop()\n{\n  static uint32_t tTime[3];\n  static uint32_t imu_time = 0;\n\n\n  if( (millis()-tTime[0]) >= 500 )\n  {\n    tTime[0] = millis();\n\n    digitalWrite( led_pin, led_tog );\n    led_tog ^= 1;\n  }\n\n  tTime[2] = micros();\n  if( IMU.update() > 0 ) imu_time = micros()-tTime[2];\n\n\n\n  if( (millis()-tTime[1]) >= 50 )\n  {\n    tTime[1] = millis();\n\n    Serial.print(imu_time);\n    Serial.print(\" \\t\");\n    Serial.print(IMU.gyroRaw[0]);    // GYRO X\n    Serial.print(\" \\t\");\n    Serial.print(IMU.gyroRaw[1]);    // GYRO Y\n    Serial.print(\" \\t\");\n    Serial.print(IMU.gyroRaw[2]);    // GYRO Z\n    Serial.println(\" \");\n  }\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/09. IMU/IMU_Read_RollPitchYaw/IMU_Read_RollPitchYaw.ino",
    "content": "/*\n  Range   : Roll  : +/- 180 deg/sec\n            Pitch : +/- 180 deg/sec\n            Yaw   : +/- 180 deg/sec\n  Scale   : Roll  : 1 = 1 deg/sec\n            Pitch : 1 = 1 deg/sec\n            Yaw   : 1 = 1 deg/sec\n */\n\n#include <IMU.h>\n\n\ncIMU    IMU;\n\n\n\nuint8_t   err_code;\nuint8_t   led_tog = 0;\nuint8_t   led_pin = 13;\n\nvoid setup()\n{\n  Serial.begin(115200);\n\n  IMU.begin();\n\n  pinMode( led_pin, OUTPUT );\n}\n\n\n\n\n\nvoid loop()\n{\n  static uint32_t tTime[3];\n  static uint32_t imu_time = 0;\n\n\n  if( (millis()-tTime[0]) >= 500 )\n  {\n    tTime[0] = millis();\n\n    digitalWrite( led_pin, led_tog );\n    led_tog ^= 1;\n  }\n\n  tTime[2] = micros();\n  if( IMU.update() > 0 ) imu_time = micros()-tTime[2];\n\n\n\n  if( (millis()-tTime[1]) >= 50 )\n  {\n    tTime[1] = millis();\n\n    Serial.print(imu_time);\n    Serial.print(\" \");\n    Serial.print(IMU.rpy[0]);\n    Serial.print(\" \");\n    Serial.print(IMU.rpy[1]);\n    Serial.print(\" \");\n    Serial.println(IMU.rpy[2]);\n  }\n\n\n  if( Serial.available() )\n  {\n    char Ch = Serial.read();\n\n    if( Ch == '1' )\n    {\n      Serial.println(\"ACC Cali Start\");\n\n      IMU.SEN.acc_cali_start();\n      while( IMU.SEN.acc_cali_get_done() == false )\n      {\n        IMU.update();\n      }\n\n      Serial.print(\"ACC Cali End \");\n    }\n  }\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/CAMERA/ov7725_al422b/ov7725_al422b.cpp",
    "content": "#include <Touch.h>\n#include <XPT2046.h>\n#include \"ov7725_al422b.h\"\n#include \"settings.h\"\n\nobject_info_t detected_object[MAX_OBJECT];\nuint16_t img_width = LCD_WIDTH;\nuint16_t img_height = LCD_HEIGHT;\nuint8_t  detectCount = 0;\nuint8_t  target = 0;\nchar detectCounter[3];\nchar coordinateX[4];\nchar coordinateY[4];\nchar fpsString[3];\n\n#if _USE_FULLSCREEN == true\n  uint16_t image_buf[LCD_WIDTH*LCD_HEIGHT];\n  //use bit for each pixel info or else : RAM overflow\n  uint16_t __attribute__((section(\".NoneCacheableMem\"))) masked_image_buf[(LCD_WIDTH*LCD_HEIGHT)/16];\n#else\n  uint16_t image_buf[(LCD_WIDTH/2)*(LCD_HEIGHT/2)];\n  uint16_t masked_image_buf[(LCD_WIDTH/2)*(LCD_HEIGHT/2)];\n#endif\n\nvoid lcdInit()\n{\n    __SD_CS_DISABLE();\n    SPI.beginFast();\n\n    TFTLCD.lcd_init();\n    Tp.tp_init();\n}\n\nvoid getSingleTouchPoint(uint16_t* touch_list)\n{\n    //Make sure, that before reading the touch info, you must decrease the SPI speed under 2MHz. After finish this process, return to SPI_CLOCK_DIV4.\n    SPI.setClockDivider(SPI_CLOCK_DIV32);\n    Tp.tp_show_single_info(touch_list);\n    touch_list[XPOS] = constrain(touch_list[XPOS], TOUCH_MIN, TOUCH_MAX);\n    touch_list[YPOS] = constrain(touch_list[YPOS], TOUCH_MIN, TOUCH_MAX);\n    SPI.setClockDivider(SPI_CLOCK_DIV4);\n}\n\nvoid drawScreen()\n{\n  TFTLCD.drawFrame();\n}\n\nvoid clearScreen(uint16_t color)\n{\n  TFTLCD.lcd_clear_screen(color);\n}\n\nvoid lcdRotation(uint8_t rotation)\n{\n  TFTLCD.LCDRotation(rotation);\n}\n\nvoid drawText(uint16_t x_pos, uint16_t y_pos, const uint8_t *string, uint8_t ch_size, uint16_t color)\n{\n  TFTLCD.lcd_display_string(x_pos, y_pos, string, ch_size, color);\n}\n\nvoid setGRamArea(uint8_t size)\n{\n  TFTLCD.setLcdMemoryArea(size);\n}\n\n/********************\n * Image Processing\n * Pixel : GGGBBBBB RRRRRGGG\n ********************/\nvoid colorFilter(uint16_t *image, uint8_t size)\n{\n  uint32_t pixelCount = 0;\n  img_width = LCD_WIDTH;\n  img_height = LCD_HEIGHT;\n  uint16_t u_quotient = 0;\n  uint8_t  u_remainder = 0;\n  \n  if((size == QUARTERVIEW) || (size == QQVGA))\n  {\n    img_width = LCD_WIDTH / 2;\n    img_height = LCD_HEIGHT / 2;\n  }\n\n  for(pixelCount = 0; pixelCount < img_width*img_height; pixelCount++)\n  {\n    if(colorFinder(image, pixelCount))\n    {\n      #if _USE_FULLSCREEN == true\n        u_quotient = pixelCount / 16;\n        u_remainder = pixelCount % 16;\n        masked_image_buf[u_quotient] |= (0x8000 >> u_remainder);  // 1000 0000\n      #else\n        //change the detected color to BLUE\n        masked_image_buf[pixelCount] = BLUE;\n      #endif\n    }\n    else\n    {\n      #if _USE_FULLSCREEN == true\n        u_quotient = pixelCount / 16;\n        u_remainder = pixelCount % 16;\n        masked_image_buf[u_quotient] &= ~(0x8000 >> u_remainder);  // 0111 1111\n      #else\n        masked_image_buf[pixelCount] = BLACK;\n      #endif\n    }\n  }\n}\n\nbool colorFinder(const uint16_t *image, uint32_t pixelLocation)\n{\n  const color_range_t* target_color = &selected_color[SELECTED_COLOR];\t//select color to detect\n  uint16_t pixelColor;\n  float propRed;\n  float propGreen;\n  float propBlue;\n  uint8_t rgbSUM;\n\n  pixelColor = image[pixelLocation] >> 8 | image[pixelLocation] << 8;\n  rgbSUM = ((pixelColor >> 11) & 0x1F) + ((pixelColor >> 5) & 0x3F) + (pixelColor & 0x1F);\n  propRed = (float)((pixelColor >> 11) & 0x1F) / rgbSUM;\n  propGreen = (float)((pixelColor >> 5) & 0x3F) / rgbSUM;\n  propBlue = (float)(pixelColor & 0x001F) / rgbSUM;\n\n  //compare Red range\n  if ((propRed > target_color->minRed) && (propRed < target_color->maxRed))\n  {\n\t//compare Green range\n\tif ((propGreen > target_color->minGreen) && (propGreen < target_color->maxGreen))\n\t{\n\t  //compare Blue ranges\n\t  if ((propBlue > target_color->minBlue) && (propBlue < target_color->maxBlue))\n\t  {\n\t    //if RGB is within TARGET_COLOR range, leave the color or else erase pixel to BLACK.\n\t\t  return true;\n\t  }\n\t  return false;\n\t}\n\treturn false;\n  }\n  return false;\n}\n\n/**\n * This function is copied and modified from \n * https://github.com/ratkins/RGBConverter/blob/master/RGBConverter.cpp\n * \n * Converts an RGB565 color value to HSL. Conversion formula\n * adapted from http://en.wikipedia.org/wiki/HSL_color_space.\n * ----Assumes r, g, and b are contained in the set [0, 255]---- and\n * returns h, s, and l in the set [0, 1].\n *\n * @param   Number  r       The red color value\n * @param   Number  g       The green color value\n * @param   Number  b       The blue color value\n * @return  Array           The HSL representation\n**/\n// void rgbToHsl(byte r, byte g, byte b, double hsl[])\n// {\n//   double rd = (double) r/31;\n//   double gd = (double) g/63;\n//   double bd = (double) b/31;\n//   double max = MAX(MAX(rd,gd),bd);\n//   double min = MIN(MIN(rd,gd),bd);\n//   double h = 0;\n//   double s = 0;\n//   double l = 0;\n//   h = s = l = (max + min) / 2;\n\n//   if (max == min)\n//   {\n//     h = s = 0; // achromatic\n//   }\n//   else\n//   {\n//     double d = max - min;\n//     s = l > 0.5 ? d / (2 - max - min) : d / (max + min);\n//     if (max == rd)\n//     {\n//       h = (gd - bd) / d + (gd < bd ? 6 : 0);\n//     }\n//     else if (max == gd)\n//     {\n//       h = (bd - rd) / d + 2;\n//     }\n//     else if (max == bd)\n//     {\n//       h = (rd - gd) / d + 4;\n//     }\n//     h = h / 6;\n//   }\n//   hsl[0] = h;\n//   hsl[1] = s;\n//   hsl[2] = l;\n// }\n\n//find the most attracting detection and mark around it\nvoid objectFinder(const uint16_t *masked_image)\n{\n  detectCount = 0;\n  uint8_t  xCount = 0;\n  uint8_t  yCount = 0;\n  uint16_t cellValue = 0;\n  uint16_t cellColumnCount;\n  uint32_t cellRawCount = 0;\n  uint32_t pixeltoCheck = 0;\n  uint16_t u_quotient = 0;\n  uint8_t  u_remainder = 0;\n\n  for(; cellRawCount < img_width*img_height; )\n  {\n    cellColumnCount = 0;\n    for(; cellColumnCount < img_height; )\n    {\n      cellValue = 0;\n      for(yCount = 0; yCount < MIN_OBJECT_PIXEL; yCount++)\n      {\n        pixeltoCheck = cellRawCount + cellColumnCount + img_height*yCount;\n        for(xCount = 0; xCount < MIN_OBJECT_PIXEL; xCount++)\n        {\n          #if _USE_FULLSCREEN == true\n            u_quotient = pixeltoCheck / 16;\n            u_remainder = pixeltoCheck % 16;\n            cellValue = cellValue + (uint16_t)((masked_image[u_quotient] >> (15 - u_remainder)) & 0x0001);\n            pixeltoCheck++;\n          #else\n            cellValue = cellValue + (masked_image[pixeltoCheck] >> 8 | masked_image[pixeltoCheck] << 8);\n            pixeltoCheck++;\n          #endif\n        }\n      }\n      #if _USE_FULLSCREEN == true\n        if(cellValue > ((MIN_OBJECT_PIXEL * MIN_OBJECT_PIXEL) / 2))\n      #else\n        if(cellValue > (15 * MIN_OBJECT_PIXEL * MIN_OBJECT_PIXEL))\n      #endif\n      {\n        detected_object[detectCount].coordX = cellColumnCount;\t\t\t\t\t  //X coordinate\n        detected_object[detectCount].coordY = cellRawCount / img_height;\t\t//Y coordinate\n        detected_object[detectCount].object_width = MIN_OBJECT_PIXEL;\n        detected_object[detectCount++].object_height = MIN_OBJECT_PIXEL;\n\n        if(detectCount > MAX_OBJECT) { detectCount = MAX_OBJECT; }\n      }\n      cellColumnCount = cellColumnCount + MIN_OBJECT_PIXEL;\n    }\n    cellRawCount = cellRawCount + img_height*MIN_OBJECT_PIXEL;\n  }\n}\n\n//calculate weight for each cell\nvoid cellWeight(void)\n{\n  uint8_t cellWeightCounter = 0;\n  uint8_t i = 0;\n  int16_t x = 0;\n  int16_t y = 0;\n  uint8_t distance = 0;\n\n  for(cellWeightCounter = 0; cellWeightCounter < detectCount; cellWeightCounter++)\n  {\n    detected_object[cellWeightCounter].object_weight = 0;\n    for(i = 0; i < detectCount; i++)\n    {\n      x = (detected_object[cellWeightCounter].coordX - detected_object[i].coordX) / MIN_OBJECT_PIXEL;\n      y = (detected_object[cellWeightCounter].coordY - detected_object[i].coordY) / MIN_OBJECT_PIXEL;\n      distance = x*x + y*y;\n      switch(distance)\n      {\n        case 1:\n          detected_object[cellWeightCounter].object_weight += 1.0;\n          break;\n        case 2:\n          detected_object[cellWeightCounter].object_weight += 0.5;\n          break;\n        case 4:\n          detected_object[cellWeightCounter].object_weight += 0.25;\n          break;\n        case 5:\n          detected_object[cellWeightCounter].object_weight += 0.2;\n          break;\n        default:\n          break;\n      }\n    }\n  }\n}\n\nvoid findCenterCell(void)\n{\n  float fWeight = 0.0;\n  for(uint8_t i = 0; i < detectCount; i++)\n  {\n    if(detected_object[i].object_weight > fWeight)\n    {\n      fWeight = detected_object[i].object_weight;\n      target = i;\n    }\n    TFTLCD.lcd_draw_rect(detected_object[i].coordX, detected_object[i].coordY, detected_object[i].object_width, detected_object[i].object_height, WHITE);\n  }\n  if ((detected_object[target].object_weight < 4) || (detectCount < MIN_OBJECT_PIXEL))\n  {\n    detected_object[target].coordX = img_height / 2;\n    detected_object[target].coordY = img_width / 2;\n    detected_object[target].track = false;\n  }\n  else\n  {\n    detected_object[target].track = true;\n  }\n  TFTLCD.lcd_draw_rect(detected_object[target].coordX, detected_object[target].coordY, detected_object[target].object_width, detected_object[target].object_height, RED);\n}\n\nvoid displayInfo(uint8_t fps)\n{\n  itoa(fps, fpsString, 10);\n  itoa(detectCount, detectCounter, 10);\n  itoa(detected_object[target].coordX, coordinateX, 10);\n  itoa(detected_object[target].coordY, coordinateY, 10);\n\n  drawText(20, 5, (const uint8_t *)\"fps\", 12, RED);\n  drawText(5, 5, (const uint8_t *)fpsString, 12, RED);\n  drawText(5, 15, (const uint8_t *)detectCounter, 12, WHITE);\n  drawText(5, 25, (const uint8_t *)coordinateX, 12, WHITE);\n  drawText(5, 35, (const uint8_t *)coordinateY, 12, WHITE);\n}\n\n/********************************************\n * Dynamixel Initialization for Object tracking\n********************************************/\nvoid initDynamixel(dynamixel::PortHandler *hPort, dynamixel::PacketHandler *hPacket)\n{\n  if(hPort->openPort()) {Serial.print(\"Succeeded to open the port!\\n\");}\n  else                  {Serial.print(\"Failed to open the port!\\n\");}\n\n  if(hPort->setBaudRate(BAUDRATE))  {Serial.print(\"Succeeded to set the baudrate!\\n\");}\n  else                              {Serial.print(\"Failed to set the baudrate!\\n\");}\n\n  dxlCommResult = hPacket->write1ByteTxRx(hPort, PAN_ID, ADD_TORQUE_ENABLE, TORQUE_OFF, &dxlError);\n  if (dxlCommResult != COMM_SUCCESS)  {Serial.print(hPacket->getTxRxResult(dxlCommResult));}\n  else if (dxlError != 0)             {Serial.print(hPacket->getRxPacketError(dxlError));}\n  else                                {Serial.print(\"Pan Dynamixel On \\n\");}\n\n  dxlCommResult = hPacket->write1ByteTxRx(hPort, TILT_ID, ADD_TORQUE_ENABLE, TORQUE_OFF, &dxlError);\n  if (dxlCommResult != COMM_SUCCESS)  {Serial.print(hPacket->getTxRxResult(dxlCommResult));}\n  else if (dxlError != 0)             {Serial.print(hPacket->getRxPacketError(dxlError));}\n  else                                {Serial.print(\"Tilt Dynamixel On \\n\");}\n\n  delay_ms(10);\n\n  dxlCommResult = hPacket->write4ByteTxRx(hPort, PAN_ID, ADD_PROF_ACCEL, PROF_ACCEL, &dxlError);\n  if (dxlCommResult != COMM_SUCCESS)  {Serial.print(hPacket->getTxRxResult(dxlCommResult));}\n  else if (dxlError != 0)             {Serial.print(hPacket->getRxPacketError(dxlError));}\n  else                                {Serial.print(\"Pan Profile Accel Set \\n\");}\n  \n  dxlCommResult = hPacket->write4ByteTxRx(hPort, TILT_ID, ADD_PROF_ACCEL, PROF_ACCEL, &dxlError);\n  if (dxlCommResult != COMM_SUCCESS)  {Serial.print(hPacket->getTxRxResult(dxlCommResult));}\n  else if (dxlError != 0)             {Serial.print(hPacket->getRxPacketError(dxlError));}\n  else                                {Serial.print(\"Tilt Profile Accel Set \\n\");}\n\n  delay_ms(10);\n\n  dxlCommResult = hPacket->write4ByteTxRx(hPort, PAN_ID, ADD_PROF_VEL, PROF_VEL, &dxlError);\n  if (dxlCommResult != COMM_SUCCESS)  {Serial.print(hPacket->getTxRxResult(dxlCommResult));}\n  else if (dxlError != 0)             {Serial.print(hPacket->getRxPacketError(dxlError));}\n  else                                {Serial.print(\"Pan Profile Velocity Set \\n\");}\n  \n  dxlCommResult = hPacket->write4ByteTxRx(hPort, TILT_ID, ADD_PROF_VEL, PROF_VEL, &dxlError);\n  if (dxlCommResult != COMM_SUCCESS)  {Serial.print(hPacket->getTxRxResult(dxlCommResult));}\n  else if (dxlError != 0)             {Serial.print(hPacket->getRxPacketError(dxlError));}\n  else                                {Serial.print(\"Tilt Profile Velocity Set \\n\");}\n\n  delay_ms(10);\n\n  dxlCommResult = hPacket->write1ByteTxRx(hPort, PAN_ID, ADD_TORQUE_ENABLE, TORQUE_ON, &dxlError);\n  if (dxlCommResult != COMM_SUCCESS)  {Serial.print(hPacket->getTxRxResult(dxlCommResult));}\n  else if (dxlError != 0)             {Serial.print(hPacket->getRxPacketError(dxlError));}\n  else                                {Serial.print(\"Pan Dynamixel On \\n\");}\n\n  dxlCommResult = hPacket->write1ByteTxRx(hPort, TILT_ID, ADD_TORQUE_ENABLE, TORQUE_ON, &dxlError);\n  if (dxlCommResult != COMM_SUCCESS)  {Serial.print(hPacket->getTxRxResult(dxlCommResult));}\n  else if (dxlError != 0)             {Serial.print(hPacket->getRxPacketError(dxlError));}\n  else                                {Serial.print(\"Tilt Dynamixel On \\n\");}\n\n  delay_ms(10);\n\n  // Pan Initial Center Position\n  dxlCommResult = hPacket->write4ByteTxRx(hPort, PAN_ID, ADD_GOAL_POSITION, 2048, &dxlError);\n  if (dxlCommResult != COMM_SUCCESS)  {Serial.print(hPacket->getTxRxResult(dxlCommResult));}\n  else if (dxlError != 0)             {Serial.print(hPacket->getRxPacketError(dxlError));}\n  else                                {Serial.print(\"Pan Dynamixel Init Completed \\n\");}\n\n  // Tilt Initial Center Position\n  dxlCommResult = hPacket->write4ByteTxRx(hPort, TILT_ID, ADD_GOAL_POSITION, 2048, &dxlError);\n  if (dxlCommResult != COMM_SUCCESS)  {Serial.print(hPacket->getTxRxResult(dxlCommResult));}\n  else if (dxlError != 0)             {Serial.print(hPacket->getRxPacketError(dxlError));}\n  else                                {Serial.print(\"Tilt Dynamixel Init Completed \\n\");}\n  \n  delay_ms(1000);\n\n  // Read Pan present position\n  dxlCommResult = hPacket->read4ByteTxRx(hPort, PAN_ID, ADD_PRESENT_POSITION, (uint32_t*)&panPresentPosition, &dxlError);\n  // Read Tilt present position\n  dxlCommResult = hPacket->read4ByteTxRx(hPort, TILT_ID, ADD_PRESENT_POSITION, (uint32_t*)&tiltPresentPosition, &dxlError);\n}\n\n\n/********************************************\n * Dynamixel Control for Object tracking\n********************************************/\nvoid trackObject(dynamixel::PortHandler *hPort, dynamixel::PacketHandler *hPacket)\n{\n  // Read Pan present position\n  dxlCommResult = hPacket->read4ByteTxRx(hPort, PAN_ID, ADD_PRESENT_POSITION, (uint32_t*)&panPresentPosition, &dxlError);\n  // Read Tilt present position\n  dxlCommResult = hPacket->read4ByteTxRx(hPort, TILT_ID, ADD_PRESENT_POSITION, (uint32_t*)&tiltPresentPosition, &dxlError);\n\n  if(detected_object[target].track == true)\n  {\n    //Track the object\n    //find the angle between target x, y and image center\n    if (detected_object[target].coordX > (img_height / 2) + MOVING_THRESHOLD)       {panGoalPosition = panPresentPosition - (detected_object[target].coordX - (img_height / 2));}\n    else if (detected_object[target].coordX < (img_height / 2) - MOVING_THRESHOLD)  {panGoalPosition = panPresentPosition + ((img_height / 2) - detected_object[target].coordX);}\n    else                                                              {panGoalPosition = panPresentPosition;}\n\n    if(panGoalPosition > PAN_MAX_POSITION)    {panGoalPosition = PAN_MAX_POSITION;}\n    if(panGoalPosition < PAN_MIN_POSITION)    {panGoalPosition = PAN_MIN_POSITION;}\n\n    dxlCommResult = hPacket->write4ByteTxRx(hPort, PAN_ID, ADD_GOAL_POSITION, panGoalPosition, &dxlError);\n    if (dxlCommResult != COMM_SUCCESS)  {Serial.print(hPacket->getTxRxResult(dxlCommResult));}\n    else if (dxlError != 0)             {Serial.print(hPacket->getRxPacketError(dxlError));}\n    else {}\n\n    if (detected_object[target].coordY > ((img_width / 2) + MOVING_THRESHOLD))       {tiltGoalPosition = tiltPresentPosition - (detected_object[target].coordY - (img_width / 2));}\n    else if (detected_object[target].coordY < ((img_width / 2) - MOVING_THRESHOLD))  {tiltGoalPosition = tiltPresentPosition + ((img_width / 2) - detected_object[target].coordY);}\n    else                                                                {tiltGoalPosition = tiltPresentPosition;}\n\n    if(tiltGoalPosition > TILT_MAX_POSITION)   {tiltGoalPosition = TILT_MAX_POSITION;}\n    if(tiltGoalPosition < TILT_MIN_POSITION)   {tiltGoalPosition = TILT_MIN_POSITION;}\n\n    dxlCommResult = hPacket->write4ByteTxOnly(hPort, TILT_ID, ADD_GOAL_POSITION, tiltGoalPosition);\n    if (dxlCommResult != COMM_SUCCESS)  {Serial.print(hPacket->getTxRxResult(dxlCommResult));}\n    else if (dxlError != 0)             {Serial.print(hPacket->getRxPacketError(dxlError));}\n  }\n  else\n  {\n    // Serial.print(\"The object is too small or too large!\\n\");\n  }\n}\n\n/********************************************\n * Dynamixel Control for Operating Platform\n * Left : Positive -> Forward, Right : Negative -> Forward\n * Velocity Control Mode\n********************************************/\nvoid movePlatform(dynamixel::PortHandler *hPort, dynamixel::PacketHandler *hPacket)\n{\n  //to do\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/CAMERA/ov7725_al422b/ov7725_al422b.h",
    "content": "#ifndef _OV7725_AL422B_H_\n#define _OV7725_AL422B_H_\n\n#include <Arduino.h>\n#include <DynamixelSDK.h>\n#include \"XPT2046.h\"\n#include \"./src/OV7725/OV7725.h\"\n#include \"./src/sccb/sccb.h\"\n#include \"./src/tftLcd.h\"\n\nextern  uint32_t panGoalPosition;\nextern  uint32_t tiltGoalPosition;\nextern  uint32_t panPresentPosition;\nextern  uint32_t tiltPresentPosition;\nextern  uint8_t  dxlError;\nextern  int      dxlCommResult;\n\ntypedef struct {\n  uint16_t coordX;\n  uint16_t coordY;\n  uint16_t object_width;\n  uint16_t object_height;\n  float object_weight;\n  bool track;\n} object_info_t;\n\ntypedef struct {\n  float maxRed;\n  float maxGreen;\n  float maxBlue;\n  float minRed;\n  float minGreen;\n  float minBlue;\n} color_range_t;\n\nconst color_range_t selected_color[] = {\n  {1.0, 0.5, 0.5, 0.4, 0.0, 0.0},\t//red\n  {0.6, 0.6, 1.0, 0.0, 0.0, 0.4},\t//blue\n};\n\nvoid lcdInit(void);\nvoid getSingleTouchPoint(uint16_t* touch_list);\nvoid drawScreen();\nvoid clearScreen(uint16_t color);\nvoid lcdRotation(uint8_t rotation);\nvoid drawText(uint16_t x_pos, uint16_t y_pos, const uint8_t *string, uint8_t ch_size, uint16_t color);\nvoid setGRamArea(uint8_t size);\n\nvoid colorFilter(uint16_t *image, uint8_t size);\nbool colorFinder(const uint16_t *image, uint32_t pixelLocation);\nvoid objectFinder(const uint16_t *masked_image);\nvoid cellWeight(void);\nvoid findCenterCell(void);\nvoid displayInfo(uint8_t fps);\n\nvoid initDynamixel(dynamixel::PortHandler *hPort, dynamixel::PacketHandler *hPacket);\nvoid trackObject(dynamixel::PortHandler *hPort, dynamixel::PacketHandler *hPacket);\nvoid movePlatform(dynamixel::PortHandler *hPort, dynamixel::PacketHandler *hPacket);\n\n\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/CAMERA/ov7725_al422b/ov7725_al422b.ino",
    "content": "#include \"ov7725_al422b.h\"\n#include \"settings.h\"\n\nHardwareTimer Timer(TIMER_CH1);\nuint8_t fps = 0;\nuint8_t frameCount = 0;\nuint8_t size = QVGA;\n\nuint32_t panGoalPosition = 2048;\nuint32_t tiltGoalPosition = 2048;\nuint32_t panPresentPosition = 0;\nuint32_t tiltPresentPosition = 0;\nuint8_t  dxlError = 0;\nint      dxlCommResult = COMM_TX_FAIL;\n\nvoid setup() {\n  uint8_t ov7725Vsync = 0;\n  \n  Serial.begin(115200);\n  \n  dynamixel::PortHandler *hPort = dynamixel::PortHandler::getPortHandler(DXL_PORT);\n  dynamixel::PacketHandler *hPacket = dynamixel::PacketHandler::getPacketHandler(PROTOCOL_VERSION);\n\n  initDynamixel(hPort, hPacket);\n\n  if(_USE_FULLSCREEN == true)\n  {\n    size = QVGA;\n  }\n  else\n  {\n    size = QUARTERVIEW;\n  }\n\n  pinMode(BOARD_LED_PIN, OUTPUT);\n  pinMode(BDPIN_LED_USER_1, OUTPUT);\n  pinMode(BDPIN_LED_USER_4, OUTPUT);\n  pinMode(BDPIN_LED_USER_2, OUTPUT);\n  pinMode(BDPIN_LED_USER_3, OUTPUT);\n  pinMode(BDPIN_PUSH_SW_1, INPUT);\n      \n  Timer.stop();\n  Timer.setPeriod(LED_RATE);\n  Timer.attachInterrupt(status_led);\n  Timer.start();\n\n  // put your setup code here, to run once:\n  Serial.begin(115200);\n  \n  lcdInit();\n  \n  lcdRotation(3);\n  setGRamArea(size);\n\n  OV7725_Init();\n\n  while(1)\n  {\n    ov7725Vsync = getVsync();\n    if(ov7725Vsync == 2)\n    {\n      readIMG(size);\n      colorFilter(image_buf, size);\n      objectFinder(masked_image_buf);\n      cellWeight();\n      findCenterCell();\n      displayInfo(fps);\n      drawScreen();\n      trackObject(hPort, hPacket);\n      setVsync(0);\n      frameCount++;\n    }\n  }\n}\n\n\nvoid status_led(void) {\n  static uint8_t flag = 0;\n  digitalWrite(BOARD_LED_PIN, flag);\n  flag ^= 1;\n  if(flag == 0)\n  {\n    fps = frameCount;\n    frameCount = 0;\n  }\n}\n\nvoid loop() {\n  \n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/CAMERA/ov7725_al422b/settings.h",
    "content": "#ifndef __SETTINGS_H\n#define __SETTINGS_H\n\n#define BOARD_LED_PIN           BDPIN_LED_STATUS    //Status LED\n#define LED_RATE                500000              // in microseconds; should toggle every 0.5sec\n\n#define _USE_FULLSCREEN         true                // true : use 320x240, false : use 160x120\n\n#if _USE_FULLSCREEN == true\n  #define MIN_OBJECT_PIXEL\t\t5\t//Set the object size to detect\n#else\n  #define MIN_OBJECT_PIXEL\t\t3\t//Set the object size to detect\n#endif\n\n#define MAX_OBJECT\t\t\t\t  200\t//maximum number of object to detect\n#define SELECTED_COLOR      0   //0:Red, 1:Blue\n\n//Dynamixel Definition\n#define PROTOCOL_VERSION        2.0\n#define BAUDRATE                1000000\n#define DXL_PORT                \"1\"\n#define LEFT_WHEEL              1\n#define RIGHT_WHEEL             2\n#define PAN_ID                  3\n#define TILT_ID                 4\n\n#define ADD_TORQUE_ENABLE       64\n#define ADD_GOAL_POSITION       116\n#define ADD_PRESENT_POSITION    132\n#define ADD_PROF_ACCEL          112\n#define ADD_PROF_VEL            108\n\n#define TORQUE_ON               1\n#define TORQUE_OFF              0\n#define PAN_MIN_POSITION        1024    //+90\n#define PAN_MAX_POSITION        3072    //-90\n#define TILT_MIN_POSITION       1024    //+90\n#define TILT_MAX_POSITION       3072    //-90\n#define PROF_ACCEL              25\n#define PROF_VEL                200\n#define MOVING_THRESHOLD        5       //11.38 = 1degree\n#define TRACK_THRESHOLD         50\n#define MOVING_STEP             15\n\n#define ESC_ASCII_VALUE         0x1b\n\nextern  uint16_t image_buf[];\nextern  uint16_t masked_image_buf[];\n\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/CAMERA/ov7725_al422b/src/OV7725/OV7725.cpp",
    "content": "/****************************************Copyright (c)****************************************************\n**                                      \n**                                 http://www.powermcu.com\n**\n**--------------File Info---------------------------------------------------------------------------------\n** File name:               OV7725.c\n** Descriptions:            OV7725 application function\n**\n**--------------------------------------------------------------------------------------------------------\n** Created by:              AVRman\n** Created date:            2011-2-13\n** Version:                 v1.0\n** Descriptions:            The original version\n**\n**--------------------------------------------------------------------------------------------------------\n** Modified by:             Will Son\n** Modified date:           2018-5-2\n** Version:                 v1.0\n** Descriptions:            OV7725 for OpenCR1.0\n**\n*********************************************************************************************************/\n\n/* Includes ------------------------------------------------------------------*/\n#include \"OV7725.h\"\n#include \"../sccb/sccb.h\"\n#include \"../../settings.h\"\n\nvolatile uint8_t Vsync = 0;\nuint8_t rawImgSize = QVGA;\nuint16_t firstHData = 0;\nuint16_t secondHData = 0;\nuint16_t thirdHData = 0;\nuint16_t firstLData = 0;\nuint16_t secondLData = 0;\nuint16_t thirdLData = 0;\nuint16_t cmosData = 0;\nuint8_t  camAddress = 0;\n\nstatic uint8_t toggle = 0;\n\nGPIO_TypeDef *first;\nGPIO_TypeDef *second;\nGPIO_TypeDef *third;\n\nstatic void vsync_interrupt(void)\n{\n  if(Vsync == 0)\n  {\n    //FIFO Write Reset\n    FIFO_WRST_L();\n    FIFO_WE_H();\n    Vsync = 1;\n    FIFO_WE_H();\n    FIFO_WRST_H();\n  }\n  else if(Vsync == 1)\n  {\n    FIFO_WE_L();\n    Vsync = 2;\n  }\n  __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_13);\n}\n\n/*******************************************************************************\n* Function Name  : OV7725_XCLK_Init\n* Description    : Set general GPIO pin as PWM output and use for clock as MCOx is not available\n* Input          : GPIO pin, Resolution, Duty\n* Output         : None\n* Return         : None\n* Attention\t\t : None\n*******************************************************************************/\nstatic void OV7725_XCLK_Init(void)\n{\n  if(drv_pwm_get_init(XCLK_PIN) == false)\n  {\n    drv_pwm_set_freq(XCLK_PIN, ov7725_xclk);\n    drv_pwm_setup(XCLK_PIN);\n  }\n  drv_pwm_set_duty(XCLK_PIN, 6, 32);\n}\n\n/*******************************************************************************\n* Function Name  : GPIO_Configuration\n* Description    : OV7725 VSYNC GPIO Configuration\n* Input          : None\n* Output         : None\n* Return         : None\n* Attention\t\t : None\n*******************************************************************************/            \nstatic void GPIO_Configuration(void)\n{\n  pinMode(CAM_VSYNC, INPUT_PULLDOWN);\n  attachInterrupt(9, vsync_interrupt, RISING);  //attach rising edge detection interrupt on VSYNC\n}\n\n/*******************************************************************************\n* Function Name  : FIFO_GPIO_Configuration\n* Description    : AL422B FIFO control GPIO Configuration \n* Input          : None\n* Output         : None\n* Return         : None\n* Attention\t\t : None\n*******************************************************************************/  \nstatic void FIFO_GPIO_Configuration(void)\n{\n  /* FIFO_RCLK : PE1 */\n  pinMode(CAM_RCLK, OUTPUT);\n\n  /* FIFO_RRST : PE0 */\n  pinMode(CAM_RRST, OUTPUT);\n\n  /* FIFO_CS or REN : PD6 */\n  pinMode(CAM_REN, OUTPUT);\n\n  /* FIFO_WEN : PD3 */\n  pinMode(CAM_WEN, OUTPUT);\n\n  /* FIFO_WRST : PB7 */\n  pinMode(CAM_WRST, OUTPUT);\n\n  /* FIFO D[0-7] */\n  pinMode(FIFO0, INPUT_PULLUP);\n  pinMode(FIFO1, INPUT_PULLUP);\n  pinMode(FIFO2, INPUT_PULLUP);\n  pinMode(FIFO3, INPUT_PULLUP);\n  pinMode(FIFO4, INPUT_PULLUP);\n  pinMode(FIFO5, INPUT_PULLUP);\n  pinMode(FIFO6, INPUT_PULLUP);\n  pinMode(FIFO7, INPUT_PULLUP);\n\n  first = g_Pin2PortMapArray[FIFO0].GPIOx_Port;\n  second = g_Pin2PortMapArray[FIFO3].GPIOx_Port;\n  third = g_Pin2PortMapArray[FIFO6].GPIOx_Port;\n}\n\n/*******************************************************************************\n* Function Name  : OV7725_Init\n* Description    : OV7725��ʼ��\n* Input          : None\n* Output         : None\n* Return         : None\n* Attention\t\t : ����1�ɹ�������0ʧ��\n*******************************************************************************/ \nint OV7725_Init(void)\n{\n  int16_t i=0;\n\n  OV7725_XCLK_Init();\n  GPIO_Configuration();\n  FIFO_GPIO_Configuration();\n\n  if(cambus_init() != 0)\n  {\n\t  return 1;\t//init error\n  }\n\n  camAddress = cambus_scan();\t//OV7725 Address = 0x42\n\n  // Reset SCCB\n  if(camAddress == ADDR_OV7725)\n  {\n    if(cambus_writeb(ADDR_OV7725, 0x12, 0x80) != 0)\n    {\n      return 1;\n    }\n  }\n  delay_ms(10);\n\n  //Setting OV7725 Register\n  for( i=0 ; i < (REG_NUM - 2) ; i++ )\n  {\n\t  if( cambus_writeb(ADDR_OV7725, OV7725_Reg[i][0], OV7725_Reg[i][1]) != 0 )\n\t  {\n\t\t  return 1;\n\t  }\n\t  delay_ms(10);\n  }\n\n  if(rawImgSize == QQVGA)\n  {\n    cambus_writeb(ADDR_OV7725, 0x29, 0x28);\n    delay_ms(10);\n    cambus_writeb(ADDR_OV7725, 0x2c, 0x3c);\n  }\n\n  return 0;\n}\n\nuint8_t getVsync(void)\n{\n  return Vsync;\n}\n\nvoid setVsync(uint8_t value)\n{\n  Vsync = value;\n}\n\nvoid setRawImgSize(uint8_t value)\n{\n  if (value == QVGA)\n    rawImgSize = QVGA;\n  else if (value == QQVGA)\n    rawImgSize = QQVGA;\n}\n\n// Read Image from FIFO\nvoid readIMG(uint8_t size) \n{\n  uint32_t pixelCount = 0;\n  uint32_t qtPixelCount = 0;\n  float    fWeight = 0;\n\n  FIFO_WE_L();\n\n  FIFO_RRST_L();\n\n  FIFO_RCLK_H();  //Read Reset\n  FIFO_RCLK_L();\n  \n  FIFO_RCLK_H();  //Read Reset\n  FIFO_RCLK_L();\n\n  FIFO_RRST_H();\n\n  if(size == QUARTERVIEW)\n  {\n    for(pixelCount = 0; pixelCount < (LCD_WIDTH*LCD_HEIGHT) ;pixelCount++)\n    {\n      if((pixelCount % 2 == 0) && ((pixelCount / 320) % 2 == 0))\n      {\n        FIFO_RCLK_H();\n\n        //High Byte\n        FIFO_RCLK_L();\n        firstHData = first->IDR; \t  //XXX0 0000 0000 0000\n        secondHData = second->IDR; \t//0000 0000 000X 0XXX\n        thirdHData = third->IDR;\t\t//0000 000X 0000 0000\n        FIFO_RCLK_H();\n\n        //Low Byte\n        FIFO_RCLK_L();\n        firstLData = first->IDR; \t  //XXX0 0000 0000 0000\n        secondLData = second->IDR; \t//0000 0000 000X 0XXX\n        thirdLData = third->IDR;\t  //0000 000X 0000 0000\n        FIFO_RCLK_H();\n\n        //1st and 2nd byte is inverted. therefore, GGGBBBBB RRRRRGGG\n        cmosData = (((firstLData >> 5) & 0x0700) | ((secondLData << 11) & 0xB800) | ((thirdLData << 6) & 0x4000) | ((firstHData >> 13) & 0x0007) | ((secondHData << 3) & 0x00B8) | ((thirdHData >> 2) & 0x0040));\n        image_buf[qtPixelCount++] = cmosData;\n      }\n      //read and waste unnecessary data\n      else\n      {\n        FIFO_RCLK_H();\n\n        //High Byte\n        FIFO_RCLK_L();\n        firstHData = first->IDR; \t  //XXX0 0000 0000 0000\n        secondHData = second->IDR; \t//0000 0000 000X 0XXX\n        thirdHData = third->IDR;\t\t//0000 000X 0000 0000\n        FIFO_RCLK_H();\n\n        //Low Byte\n        FIFO_RCLK_L();\n        firstLData = first->IDR; \t  //XXX0 0000 0000 0000\n        secondLData = second->IDR; \t//0000 0000 000X 0XXX\n        thirdLData = third->IDR;\t  //0000 000X 0000 0000\n        FIFO_RCLK_H();\n      }\n    }\n  }\n  else if(size == QVGA)\n  {\n    for(pixelCount = 0; pixelCount < (LCD_WIDTH*LCD_HEIGHT) ;pixelCount++)\n    {\n      FIFO_RCLK_H();\n\n      //High Byte\n      FIFO_RCLK_L();\n      firstHData = first->IDR; \t  //XXX0 0000 0000 0000\n      secondHData = second->IDR; \t//0000 0000 000X 0XXX\n      thirdHData = third->IDR;\t\t//0000 000X 0000 0000\n      FIFO_RCLK_H();\n\n      //Low Byte\n      FIFO_RCLK_L();\n      firstLData = first->IDR; \t  //XXX0 0000 0000 0000\n      secondLData = second->IDR; \t//0000 0000 000X 0XXX\n      thirdLData = third->IDR;\t  //0000 000X 0000 0000\n      FIFO_RCLK_H();\n\n      //1st and 2nd byte is inverted. therefore, GGGBBBBB RRRRRGGG\n      cmosData = (((firstLData >> 5) & 0x0700) | ((secondLData << 11) & 0xB800) | ((thirdLData << 6) & 0x4000) | ((firstHData >> 13) & 0x0007) | ((secondHData << 3) & 0x00B8) | ((thirdHData >> 2) & 0x0040));\n      image_buf[pixelCount] = cmosData;\n    }\n  }\n}\n\n/*********************************************************************************************************\n      END FILE\n*********************************************************************************************************/\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/CAMERA/ov7725_al422b/src/OV7725/OV7725.h",
    "content": "/****************************************Copyright (c)****************************************************\n**                                      \n**                                 http://www.powermcu.com\n**\n**--------------File Info---------------------------------------------------------------------------------\n** File name:               OV7725.h\n** Descriptions:            None\n**\n**--------------------------------------------------------------------------------------------------------\n** Created by:              AVRman\n** Created date:            2011-2-13\n** Version:                 v1.0\n** Descriptions:            The original version\n**\n**--------------------------------------------------------------------------------------------------------\n** Modified by:             Will Son\n** Modified date:           2018-5-2\n** Version:                 v1.0\n** Descriptions:            OV7725 for OpenCR1.0\n**\n*********************************************************************************************************/\n\n#ifndef __OV7725_H\n#define __OV7725_H \n\n/* Includes ------------------------------------------------------------------*/\t   \n\n#include \"../tftLcd.h\"\n\n#define ov7725_xclk\t\t20000000  //20Mhz\n#define XCLK_PIN  BDPIN_GPIO_8  //GPIO #10(GPIOE PIN11)\n#define CAM_VSYNC BDPIN_GPIO_3\n#define CAM_WRST  BDPIN_GPIO_4\n#define CAM_WEN   BDPIN_GPIO_5\n#define CAM_RRST  BDPIN_GPIO_7\n#define CAM_REN   BDPIN_GPIO_6\n#define CAM_RCLK  BDPIN_GPIO_9\n#define FIFO0     BDPIN_GPIO_10\n#define FIFO1     BDPIN_GPIO_11\n#define FIFO2     BDPIN_GPIO_12\n#define FIFO3     BDPIN_GPIO_13\n#define FIFO4     BDPIN_GPIO_14\n#define FIFO5     BDPIN_GPIO_15\n#define FIFO6     BDPIN_GPIO_16\n#define FIFO7     BDPIN_GPIO_17\n\n/*------------------------------------------------------\n  ģ���������� | ����            |     STM32���������� |\n  ------------------------------------------------------\n  SCCB_SCL     : SCCB SCL             : PB10    I2C2_SCL\n  SCCB_SDA     : SCCB SDA             : PB11    I2C2_SDA\n  CAM_VSYNC    : VSYNC                : PC13    GPIO #5\n  CAM_WRST     : FIFO Write Reset     : PD2     GPIO #6\n  CAM_WEN      : FIFO Write Enable    : PE3     GPIO #7\n  XCLK         : CMOS Clock           : PE11    GPIO #10\n  CAM_RRST     : FIFO Read Reset      : PE10    GPIO #9\n  CAM_REN      : FIFO Write Enable    : PG2     GPIO #8\n  CAM_RCLK     : FIFO Read Clock      : PE12    GPIO #11\n  FIFO D0~D7   : FIFO Data Out        : PE13/14/15,PF0/1/2,PD8,PF4   GPIO #12,13,14,15,16,17,18,19\n  -----------------------------------------------------*/\n\n/* Private define ------------------------------------------------------------*/\n\n#define FIFO_CS_PIN     GPIO_PIN_6\n#define FIFO_WRST_PIN   GPIO_PIN_7\n#define FIFO_RRST_PIN   GPIO_PIN_0\n#define FIFO_RCLK_PIN   GPIO_PIN_1\n#define FIFO_WE_PIN     GPIO_PIN_3\n\n#define FIFO_CS_H()     GPIOG->BSRR |= 0x00000004U\n#define FIFO_CS_L()     GPIOG->BSRR |= 0x00040000U\n\n#define FIFO_WRST_H()   GPIOD->BSRR |= 0x00000004U\n#define FIFO_WRST_L()   GPIOD->BSRR |= 0x00040000U\n\n#define FIFO_RRST_H()   GPIOE->BSRR |= 0x00000400U\n#define FIFO_RRST_L()   GPIOE->BSRR |= 0x04000000U\n\n#define FIFO_RCLK_H()   GPIOE->BSRR |= 0x00001000U\n#define FIFO_RCLK_L()   GPIOE->BSRR |= 0x10000000U\n\n#define FIFO_WE_H()     GPIOE->BSRR |= 0x00000008U\n#define FIFO_WE_L()     GPIOE->BSRR |= 0x00080000U\n\n#define FIFO_OE_H()\t\tGPIOG->BSRR |= 0x00000004U\n#define FIFO_OE_L()\t\tGPIOG->BSRR |= 0x00040000U\n\n#define REG_NUM                            79\n#define PORT_VSYNC_CMOS                    GPIOA\n#define RCC_APB2Periph_PORT_VSYNC_CMOS     RCC_APB2Periph_GPIOA\n#define PIN_VSYNC_CMOS                     GPIO_Pin_0\n#define EXTI_LINE_VSYNC_CMOS               EXTI_Line0\n#define PORT_SOURCE_VSYNC_CMOS             GPIO_PortSourceGPIOA\n#define PIN_SOURCE_VSYNC_CMOS              GPIO_PinSource0\n\nconst uint8_t OV7725_Reg[REG_NUM][2] =\n{\n  /* Setting OV7725QVGA RGB565 */\n\t{0x2a,0x00}, //QVGA : {0x2a,0x00} , QQVGA : {0x2a,0x00}\n\t{0x11,0x00}, // 00/01/03/07 for 60/30/15/7.5fps  - set to 15fps for QVGA\n\t{0x0D,0xF1},\n\t{0x12,0x46}, /* QVGA RGB565 {0x12,0x46}, QQVGA RGB565 {0x12,0x46}*/\n\t{0x17,0x3F},\n\t{0x18,0x50},\n\t{0x19,0x03},\n\t{0x1A,0x78},\n\t{0x32,0x80},\n\n\t{0xAC,0xff}, //auto scaling\n\t{0x42,0x7f},\n\t{0x4d,0x00}, /* 0x09 */\n\t{0x63,0xf0},\n\t{0x64,0xff},\n\t{0x65,0x00}, //0x20\n\t{0x66,0x10}, //0x00\n\t{0x67,0x00},\n\t{0x69,0x5C},\n\t{0x13,0x8F},  //{0x13,0xff},\n\t{0x0d,0x41}, /* PLL, 0xc1*/\n\t{0x0f,0x43}, //0xc5\n\t{0x14,0x4A}, //{0x14,0x11},\n\t{0x22,0xFF}, // ff/7f/3f/1f for 60/30/15/7.5fps\n\t{0x23,0x01}, // 01/03/07/0f for 60/30/15/7.5fps\n\t{0x24,0x34},\n\t{0x25,0x3c},\n\t{0x26,0xa1},\n\t{0x2b,0x00},\n\t{0x6b,0xaa},\n\n\t{0x90,0x0a},\n\t{0x91,0x01}, //{0x91,0x01}\n\t{0x92,0x01}, //{0x92,0x01}\n\t{0x93,0x01},\n\n\t{0x94,0x5f}, //{0x94,0x5f}\n\t{0x95,0x53}, //{0x95,0x53}\n\t{0x96,0x11}, //{0x96,0x11}\n\t{0x97,0x1a}, //{0x97,0x1a}\n\t{0x98,0x3d}, //{0x98,0x3d}\n\t{0x99,0x5a}, //{0x99,0x5a}\n\t{0x9a,0x1e}, //{0x9a,0x1e}\n\n\t{0x9b,0x00}, /* set luma */\n\t{0x9c,0x25}, /* set contrast */\n\t{0xa7,0x40}, /* set saturation {0xa7,0x65}*/\n\t{0xa8,0x40}, /* set saturation {0xa8,0x65}*/\n\t{0xa9,0x80}, /* set hue */\n\t{0xaa,0x80}, /* set hue */\n\n\t{0x9e,0x81},\n\t{0xa6,0x00},\n\t{0x7e,0x0c},\n\t{0x7f,0x16},\n\t{0x80,0x2a},\n\t{0x81,0x4e},\n\t{0x82,0x61},\n\t{0x83,0x6f},\n\t{0x84,0x7b},\n\t{0x85,0x86},\n\t{0x86,0x8e},\n\t{0x87,0x97},\n\t{0x88,0xa4},\n\t{0x89,0xaf},\n\t{0x8a,0xc5},\n\t{0x8b,0xd7},\n\t{0x8c,0xe8},\n\t{0x8d,0x20},\n\t{0x33,0x00},\n\t{0x22,0x99},\n\t{0x23,0x03},\n\t{0x4a,0x00},\n\t{0x49,0x50}, //{0x49,0x13}\n\t{0x47,0x08}, //{0x47,0x08}\n\t{0x4b,0x14}, //{0x4b,0x14}\n\t{0x4c,0x17}, //{0x4c,0x17}\n\t{0x46,0x00}, //{0x46,0x05}\n\t{0x0e,0x01}, //{0x0e,0xf5}1111,0101\n\t{0x0c,0xD0}, //bit6 : Horizontal Mirror, bit0 : test pattern enable\n\t\n\t{0x29,0x50},\t//_USE_QVGA\n\t{0x2c,0x78},\t//_USE_QVGA\n\n\t{0x29,0x28},\t//_USE_QQVGA\n\t{0x2c,0x3C},\t//_USE_QQVGA\n};\n/* Private variables ---------------------------------------------------------*/\t\n\n/* Private function prototypes -----------------------------------------------*/\nint  OV7725_Init(void);\nuint8_t getVsync(void);\nvoid setVsync(uint8_t value);\nvoid readIMG(uint8_t size);\nvoid setRawImgSize(uint8_t value);\n\n#endif\n/*********************************************************************************************************\n      END FILE\n*********************************************************************************************************/\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/CAMERA/ov7725_al422b/src/sccb/sccb.c",
    "content": "/****************************************Copyright (c)**************************************************\n**\n**                                 http://www.powermcu.com\n**\n**--------------File Info-------------------------------------------------------------------------------\n** File name:\t\t\tSCCB.c\n** Descriptions:\t\tSCCB ����������\n**\n**------------------------------------------------------------------------------------------------------\n** Created by:\t\t\tAVRman\n** Created date:\t\t2011-2-13\n** Version:\t\t\t\t1.0\n** Descriptions:\t\tThe original version\n**\n**------------------------------------------------------------------------------------------------------\n** Modified by:\n** Modified date:\n** Version:\n** Descriptions:\n********************************************************************************************************/\n\n/* Includes ------------------------------------------------------------------*/\n#include \"sccb.h\"\n\n#define I2C_FREQUENCY   (100000)\n#define I2C_TIMEOUT     (1000)\n\nstatic I2C_HandleTypeDef I2CHandle;\n\n\n\nint cambus_init()\n{\n    /* Configure I2C */\n    I2CHandle.Instance             = I2C2;\n    I2CHandle.Init.AddressingMode  = I2C_ADDRESSINGMODE_7BIT;\n    I2CHandle.Init.Timing          = 0x40912732; // 100KHz\n    I2CHandle.Init.DualAddressMode = I2C_DUALADDRESS_DISABLED;\n\tI2CHandle.Init.GeneralCallMode = I2C_GENERALCALL_DISABLED;\n\tI2CHandle.Init.NoStretchMode   = I2C_NOSTRETCH_DISABLED;\n\tI2CHandle.Init.OwnAddress1     = 0xFE;\n\tI2CHandle.Init.OwnAddress2     = 0xFE;\n\n    if (HAL_I2C_Init(&I2CHandle) != HAL_OK) {\n        /* Initialization Error */\n        return -1;\n    }\n    return 0;\n}\n\nint cambus_scan()\n{\n    for (uint8_t addr=0x08; addr<=0x77; addr++) {\n        __disable_irq();\n        if (HAL_I2C_IsDeviceReady(&I2CHandle, addr << 1, 10, I2C_TIMEOUT) == HAL_OK) {\n            __enable_irq();\n            return (addr << 1);\n        }\n        __enable_irq();\n    }\n\n    return 0;\n}\n\nint cambus_readb(uint8_t slv_addr, uint8_t reg_addr, uint8_t *reg_data)\n{\n    int ret = 0;\n\n    __disable_irq();\n    if((HAL_I2C_Master_Transmit(&I2CHandle, slv_addr, &reg_addr, 1, I2C_TIMEOUT) != HAL_OK)\n    || (HAL_I2C_Master_Receive(&I2CHandle, slv_addr, reg_data, 1, I2C_TIMEOUT) != HAL_OK)) {\n        ret = -1;\n    }\n    __enable_irq();\n    return ret;\n}\n\nint cambus_writeb(uint8_t slv_addr, uint8_t reg_addr, uint8_t reg_data)\n{\n    int ret=0;\n    uint8_t buf[] = {reg_addr, reg_data};\n\n    __disable_irq();\n    if(HAL_I2C_Master_Transmit(&I2CHandle, slv_addr, buf, 2, I2C_TIMEOUT) != HAL_OK) {\n    \tret = -1;\n    }\n    __enable_irq();\n    return ret;\n}\n\nint cambus_readw(uint8_t slv_addr, uint8_t reg_addr, uint16_t *reg_data)\n{\n    int ret=0;\n    __disable_irq();\n    if (HAL_I2C_Mem_Read(&I2CHandle, slv_addr, reg_addr,\n                I2C_MEMADD_SIZE_8BIT, (uint8_t*) reg_data, 2, I2C_TIMEOUT) != HAL_OK) {\n        ret = -1;\n    }\n    __enable_irq();\n    *reg_data = (*reg_data >> 8) | (*reg_data << 8);\n    return ret;\n}\n\nint cambus_writew(uint8_t slv_addr, uint8_t reg_addr, uint16_t reg_data)\n{\n    int ret=0;\n    reg_data = (reg_data >> 8) | (reg_data << 8);\n    __disable_irq();\n    if (HAL_I2C_Mem_Write(&I2CHandle, slv_addr, reg_addr,\n                I2C_MEMADD_SIZE_8BIT, (uint8_t*) &reg_data, 2, I2C_TIMEOUT) != HAL_OK) {\n        ret = -1;\n    }\n    __enable_irq();\n    return ret;\n}\n\n/*********************************************************************************************************\n      END FILE\n*********************************************************************************************************/"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/CAMERA/ov7725_al422b/src/sccb/sccb.h",
    "content": "/****************************************Copyright (c)**************************************************\n**\n**                                 http://www.powermcu.com\n**\n**--------------File Info-------------------------------------------------------------------------------\n** File name:\t\t\tSCCB.h\n** Descriptions:\t\tSCCB ����������\n**\n**------------------------------------------------------------------------------------------------------\n** Created by:\t\t\tAVRman\n** Created date:\t\t2011-2-13\n** Version:\t\t\t\t1.0\n** Descriptions:\t\tThe original version\n**\n**------------------------------------------------------------------------------------------------------\n** Modified by:\n** Modified date:\n** Version:\n** Descriptions:\n********************************************************************************************************/\n#ifndef __SCCB_H\n#define __SCCB_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f7xx.h\"\n#include <hw.h>\n\n/* Private define ------------------------------------------------------------*/\n// #define SCL_H         GPIOB->BSRR = 0x00000400U\t//gpioPinWrite(_DEF_I2C2_SCL, GPIO_PIN_SET) \t//GPIOB->BSRR = GPIO_PIN_10\t /* GPIO_SetBits(GPIOB , GPIO_Pin_10)   */\n// #define SCL_L         GPIOB->BSRR = 0x04000000U\t//gpioPinWrite(_DEF_I2C2_SCL, GPIO_PIN_RESET)\t//GPIOB->BRR  = GPIO_PIN_10  /* GPIO_ResetBits(GPIOB , GPIO_Pin_10) */\n\n// #define SDA_H         GPIOB->BSRR = 0x00000800U\t//gpioPinWrite(_DEF_I2C2_SDA, GPIO_PIN_SET)\t\t//GPIOB->BSRR = GPIO_PIN_11\t /* GPIO_SetBits(GPIOB , GPIO_Pin_11)   */\n// #define SDA_L         GPIOB->BSRR = 0x08000000U\t//gpioPinWrite(_DEF_I2C2_SDA, GPIO_PIN_RESET)\t//GPIOB->BRR  = GPIO_PIN_11\t /* GPIO_ResetBits(GPIOB , GPIO_Pin_11) */\n\n// #define SCL_read      digitalReadFast(BDPIN_GPIO_1)\t//(GPIOB->IDR) & GPIO_PIN_10\t//GPIOB->IDR  & GPIO_PIN_10\t /* GPIO_ReadInputDataBit(GPIOB , GPIO_Pin_10) */\n// #define SDA_read      digitalReadFast(BDPIN_GPIO_2)\t//(GPIOB->IDR) & GPIO_PIN_11\t//GPIOB->IDR  & GPIO_PIN_11\t /* GPIO_ReadInputDataBit(GPIOB , GPIO_Pin_11) */\n\n#define ADDR_OV7725   0x42\n\n/* Private function prototypes -----------------------------------------------*/\n// void I2C_Configuration(void);\n// int I2C_WriteByte( uint16_t WriteAddress , uint8_t SendByte , uint8_t DeviceAddress);\n// int I2C_ReadByte(uint8_t* pBuffer,   uint16_t length,   uint16_t ReadAddress,  uint8_t DeviceAddress);\n// void SDA_input(void);\n// void SDA_output(void);\n\nint cambus_init(void);\nint cambus_scan(void);\nint cambus_readb(uint8_t slv_addr, uint8_t reg_addr, uint8_t *reg_data);\nint cambus_writeb(uint8_t slv_addr, uint8_t reg_addr, uint8_t reg_data);\n\n// void I2C_delay(void);\n\n#ifdef __cplusplus\n }\n#endif\n\n#endif /* __SCCB_H */\n\n/*********************************************************************************************************\n      END FILE\n*********************************************************************************************************/\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/CAMERA/ov7725_al422b/src/tftLcd.cpp",
    "content": "#include \"tftLcd.h\"\n#include \"../settings.h\"\n\n#define USE_image_bufFER     1\n\nuint16_t IMG_WIDTH = LCD_WIDTH;\nuint16_t IMG_HEIGHT = LCD_HEIGHT;\nuint16_t rotation = 2;\n\nvoid TFT_LCD::lcd_init()\n{\n  lcd_width = LCD_WIDTH;\n  lcd_height = LCD_HEIGHT;\n  setLcdMemoryArea(QVGA);\n\n  __LCD_DC_OUT();\n  __LCD_DC_SET();\n\n  __LCD_CS_OUT();\n  __LCD_CS_SET();\n\n  __LCD_BKL_OUT();\n  __LCD_BKL_OFF();\n\n  //Driving ability Setting\n  lcd_write_register(0xEA,0x00); //PTBA[15:8]\n  lcd_write_register(0xEB,0x20); //PTBA[7:0]\n  lcd_write_register(0xEC,0x0C); //STBA[15:8]\n  lcd_write_register(0xED,0xC4); //STBA[7:0]\n  lcd_write_register(0xE8,0x38); //OPON[7:0]\n  lcd_write_register(0xE9,0x10); //OPON1[7:0]\n  lcd_write_register(0xF1,0x01); //OTPS1B\n  lcd_write_register(0xF2,0x10); //GEN\n  //Gamma 2.2 Setting\n  lcd_write_register(0x40,0x01); //\n  lcd_write_register(0x41,0x00); //\n  lcd_write_register(0x42,0x00); //\n  lcd_write_register(0x43,0x10); //\n  lcd_write_register(0x44,0x0E); //\n  lcd_write_register(0x45,0x24); //\n  lcd_write_register(0x46,0x04); //\n  lcd_write_register(0x47,0x50); //\n  lcd_write_register(0x48,0x02); //\n  lcd_write_register(0x49,0x13); //\n  lcd_write_register(0x4A,0x19); //\n  lcd_write_register(0x4B,0x19); //\n  lcd_write_register(0x4C,0x16); //\n  lcd_write_register(0x50,0x1B); //\n  lcd_write_register(0x51,0x31); //\n  lcd_write_register(0x52,0x2F); //\n  lcd_write_register(0x53,0x3F); //\n  lcd_write_register(0x54,0x3F); //\n  lcd_write_register(0x55,0x3E); //\n  lcd_write_register(0x56,0x2F); //\n  lcd_write_register(0x57,0x7B); //\n  lcd_write_register(0x58,0x09); //\n  lcd_write_register(0x59,0x06); //\n  lcd_write_register(0x5A,0x06); //\n  lcd_write_register(0x5B,0x0C); //\n  lcd_write_register(0x5C,0x1D); //\n  lcd_write_register(0x5D,0xCC); //\n  //Power Voltage Setting\n  lcd_write_register(0x1B,0x1B); //VRH=4.65V\n  lcd_write_register(0x1A,0x01); //BT (VGH~15V,VGL~-10V,DDVDH~5V)\n  lcd_write_register(0x24,0x2F); //VMH(VCOM High voltage ~3.2V)\n  lcd_write_register(0x25,0x57); //VML(VCOM Low voltage -1.2V)\n  //****VCOM offset**///\n  lcd_write_register(0x23,0x88); //for Flicker adjust //can reload from OTP\n  //Power on Setting\n  lcd_write_register(0x18,0x34); //I/P_RADJ,N/P_RADJ, Normal mode 60Hz\n  lcd_write_register(0x19,0x01); //OSC_EN='1', start Osc\n  lcd_write_register(0x01,0x00); //DP_STB='0', out deep sleep\n  lcd_write_register(0x1F,0x88);// GAS=1, VOMG=00, PON=0, DK=1, XDK=0, DVDH_TRI=0, STB=0\n  delay(5);\n  lcd_write_register(0x1F,0x80);// GAS=1, VOMG=00, PON=0, DK=0, XDK=0, DVDH_TRI=0, STB=0\n  delay(5);\n  lcd_write_register(0x1F,0x90);// GAS=1, VOMG=00, PON=1, DK=0, XDK=0, DVDH_TRI=0, STB=0\n  delay(5);\n  lcd_write_register(0x1F,0xD0);// GAS=1, VOMG=10, PON=1, DK=0, XDK=0, DDVDH_TRI=0, STB=0\n  delay(5);\n  //262k/65k color selection\n  lcd_write_register(0x17,0x05); //default 0x06 262k color // 0x05 65k color\n  //SET PANEL\n  lcd_write_register(0x36,0x00); //SS_P, GS_P,REV_P,BGR_P\n  //Display ON Setting\n  lcd_write_register(0x28,0x38); //GON=1, DTE=1, D=1000\n  delay(40);\n  lcd_write_register(0x28,0x3F); //GON=1, DTE=1, D=1100\n\n  lcd_write_register(0x16,0x18); //MY,MX,MV,ML,BGR,x,x,x\n\n  //Set GRAM Area\n  lcd_write_register(0x02,0x00);\n  lcd_write_register(0x03,0x00); //Column Start\n  lcd_write_register(0x04,0x00);\n  lcd_write_register(0x05,0xEF); //Column End\n  lcd_write_register(0x06,0x00);\n  lcd_write_register(0x07,0x00); //Row Start\n  lcd_write_register(0x08,0x01);\n  lcd_write_register(0x09,0x3F); //Row End\n\n  lcd_clear_screen(BLACK);\n  __LCD_BKL_ON();\n}\n\n//draw a point on the lcd with the specified color.\n//hwXpos specify x position.\n//hwYpos specify y position.\n//hwColor color of the point.\n#if USE_image_bufFER == 1\nvoid TFT_LCD::lcd_draw_point(uint16_t hwXpos, uint16_t hwYpos, uint16_t hwColor)\n{\n    if (hwXpos >= IMG_WIDTH || hwYpos >= IMG_HEIGHT) {\n      return;\n    }\n\n  image_buf[hwYpos*IMG_WIDTH+hwXpos] = hwColor;\n}\n\n#else\nvoid TFT_LCD::lcd_draw_point(uint16_t hwXpos, uint16_t hwYpos, uint16_t hwColor)\n{\n    if (hwXpos >= lcd_width || hwYpos >= lcd_height) {\n      return;\n    }\n\n    lcd_set_cursor(hwXpos, hwYpos);\n    lcd_write_byte(0x22, LCD_CMD);\n    lcd_write_word(hwColor);\n}\n#endif\n\nvoid TFT_LCD::setAddrWindow(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1)\n{\n  lcd_write_register(0x03,(x0>>0)); //Column Start\n  lcd_write_register(0x02,(x0>>8));\n  lcd_write_register(0x05,(x1>>0)); //Column End\n  lcd_write_register(0x04,(x1>>8));\n  lcd_write_register(0x07,(y0>>0)); //Row Start\n  lcd_write_register(0x06,(y0>>8));\n  lcd_write_register(0x09,(y1>>0)); //Row End\n  lcd_write_register(0x08,(y1>>8));\n}\n\nvoid TFT_LCD::LCDRotation(uint8_t rotation)\n{\n//   lcd_write_register(0x16,0x28);\n  uint8_t setting = 0;\n  switch(rotation)\n  {\n    case 0:\n      setting = MACR_MX | MACR_MY | MACR_BGR;\n      lcd_width = LCD_WIDTH;\n      lcd_height = LCD_HEIGHT;\n      break;\n    case 1:\n      setting = MACR_MY | MACR_MV | MACR_BGR;\n      lcd_width = LCD_HEIGHT;\n      lcd_height = LCD_WIDTH;\n      break;\n    case 2:\n      setting = MACR_BGR;\n      lcd_width = LCD_WIDTH;\n      lcd_height = LCD_HEIGHT;\n      break;\n    case 3:\n      setting = MACR_MX | MACR_MV | MACR_BGR;\n      lcd_width = LCD_HEIGHT;\n      lcd_height = LCD_WIDTH;\n      break;\n  }\n  IMG_WIDTH = lcd_width;\n  IMG_HEIGHT = lcd_height;\n  lcd_write_register(0x16, setting);\n  setAddrWindow(0, 0, lcd_width-1, lcd_height-1);\n}\n\nvoid TFT_LCD::setLcdMemoryArea(uint8_t size)\n{\n  switch(size)\n  {\n    //QVGA\n    case 0:\n      IMG_WIDTH = lcd_width;\n      IMG_HEIGHT = lcd_height;\n      setAddrWindow(0, 0, IMG_WIDTH-1, IMG_HEIGHT-1);\n      break;\n    \n    //QQVGA\n    case 1:\n    //QUARTERVIEW of QVGA\n    case 2:\n      IMG_WIDTH = lcd_width / 2;\n      IMG_HEIGHT = lcd_height / 2;\n      setAddrWindow(0, 0, IMG_WIDTH-1, IMG_HEIGHT-1);\n      break;\n    \n    default:\n      IMG_WIDTH = lcd_width;\n      IMG_HEIGHT = lcd_height;\n      setAddrWindow(0, 0, IMG_WIDTH-1, IMG_HEIGHT-1);\n      break;\n  }\n}\n\n\nvoid TFT_LCD::drawFrame(void)\n{\n  lcd_set_cursor(0, 0);\n  lcd_write_byte(0x22, LCD_CMD);\n  SPI.beginTransaction(SPISettings(25000000, MSBFIRST, SPI_MODE0));\n  __LCD_DC_SET();\n  __LCD_CS_CLR();\n  SPI.transfer(image_buf, NULL, IMG_WIDTH*IMG_HEIGHT*2);\n  __LCD_CS_SET();\n}\n\n//display a char at the specified position on lcd.\nvoid TFT_LCD::lcd_display_char(uint16_t hwXpos, //specify x position.\n                         uint16_t hwYpos, //specify y position.\n                         uint8_t chChr,   //a char is display.\n                         uint8_t chSize,  //specify the size of the char\n                         uint16_t hwColor) //specify the color of the char\n{\n  uint8_t i, j, chTemp;\n  uint16_t hwYpos0 = hwYpos, hwColorVal = 0;\n\n  if (hwXpos >= lcd_width || hwYpos >= lcd_height) {\n    return;\n  }\n\n  for (i = 0; i < chSize; i ++) {\n    if (FONT_1206 == chSize) {\n      chTemp = pgm_read_byte(&c_chFont1206[chChr - 0x20][i]);\n    } else if (FONT_1608 == chSize) {\n      chTemp = pgm_read_byte(&c_chFont1608[chChr - 0x20][i]);\n    }\n\n    for (j = 0; j < 8; j ++) {\n      if (chTemp & 0x80) {\n        hwColorVal = hwColor;\n        lcd_draw_point(hwXpos, hwYpos, hwColorVal);\n      }\n      chTemp <<= 1;\n      hwYpos ++;\n      if ((hwYpos - hwYpos0) == chSize) {\n        hwYpos = hwYpos0;\n        hwXpos ++;\n        break;\n      }\n    }\n  }\n}\n\n\n//_pow\nstatic uint32_t _pow(uint8_t m, uint8_t n)\n{\n    uint32_t result = 1;\n\n    while(n --) result *= m;\n    return result;\n}\n\n//display a number at the specified position on lcd.\nvoid TFT_LCD::lcd_display_num(uint16_t hwXpos,  //specify x position.\n                          uint16_t hwYpos, //specify y position.\n                          uint32_t chNum,  //a number is display.\n                          uint8_t chLen,   //length ot the number\n                          uint8_t chSize,  //specify the size of the number\n                          uint16_t hwColor) //specify the color of the number\n{\n    uint8_t i;\n    uint8_t chTemp, chShow = 0;\n\n    if (hwXpos >= lcd_width || hwYpos >= lcd_height) {\n        return;\n    }\n\n    for(i = 0; i < chLen; i ++) {\n        chTemp = (chNum / _pow(10, chLen - i - 1)) % 10;\n        if(chShow == 0 && i < (chLen - 1)) {\n            if(chTemp == 0) {\n                lcd_display_char(hwXpos + (chSize / 2) * i, hwYpos, ' ', chSize, hwColor);\n                continue;\n            } else {\n                chShow = 1;\n            }\n        }\n         lcd_display_char(hwXpos + (chSize / 2) * i, hwYpos, chTemp + '0', chSize, hwColor);\n    }\n}\n\n//display a string at the specified position on lcd.\nvoid TFT_LCD::lcd_display_string(uint16_t hwXpos, //specify x position.\n                         uint16_t hwYpos,   //specify y position.\n                         const uint8_t *pchString,  //a pointer to string\n                         uint8_t chSize,    // the size of the string\n                         uint16_t hwColor)  // specify the color of the string\n{\n\n    if (hwXpos >= lcd_width || hwYpos >= lcd_height) {\n        return;\n    }\n\n    while (*pchString != '\\0') {\n        if (hwXpos > (lcd_width - chSize / 2)) {\n            hwXpos = 0;\n            hwYpos += chSize;\n            if (hwYpos > (lcd_height - chSize)) {\n                hwYpos = hwXpos = 0;\n                lcd_clear_screen(0x00);\n            }\n        }\n\n        lcd_display_char(hwXpos, hwYpos, (uint8_t)*pchString, chSize, hwColor);\n        hwXpos += chSize / 2;\n        pchString ++;\n    }\n}\n\n//draw a line at the specified position on lcd.\nvoid TFT_LCD::lcd_draw_line(uint16_t hwXpos0, //specify x0 position.\n                      uint16_t hwYpos0, //specify y0 position.\n                      uint16_t hwXpos1, //specify x1 position.\n                      uint16_t hwYpos1, //specify y1 position.\n                      uint16_t hwColor) //specify the color of the line\n{\n    int x = hwXpos1 - hwXpos0;\n    int y = hwYpos1 - hwYpos0;\n    int dx = abs(x), sx = hwXpos0 < hwXpos1 ? 1 : -1;\n    int dy = -abs(y), sy = hwYpos0 < hwYpos1 ? 1 : -1;\n    int err = dx + dy, e2;\n\n    if (hwXpos0 >= lcd_width || hwYpos0 >= lcd_height || hwXpos1 >= lcd_width || hwYpos1 >= lcd_height) {\n        return;\n    }\n\n    for (;;){\n        lcd_draw_point(hwXpos0, hwYpos0 , hwColor);\n        e2 = 2 * err;\n        if (e2 >= dy) {\n            if (hwXpos0 == hwXpos1) break;\n            err += dy; hwXpos0 += sx;\n        }\n        if (e2 <= dx) {\n            if (hwYpos0 == hwYpos1) break;\n            err += dx; hwYpos0 += sy;\n        }\n    }\n}\n\n//draw a circle at the specified position on lcd.\nvoid TFT_LCD::lcd_draw_circle(uint16_t hwXpos,  //specify x position.\n                        uint16_t hwYpos,  //specify y position.\n                        uint16_t hwRadius, //specify the radius of the circle.\n                        uint16_t hwColor)  //specify the color of the circle.\n{\n    int x = -hwRadius, y = 0, err = 2 - 2 * hwRadius, e2;\n\n    if (hwXpos >= lcd_width || hwYpos >= lcd_height) {\n        return;\n    }\n\n    do {\n        lcd_draw_point(hwXpos - x, hwYpos + y, hwColor);\n        lcd_draw_point(hwXpos + x, hwYpos + y, hwColor);\n        lcd_draw_point(hwXpos + x, hwYpos - y, hwColor);\n        lcd_draw_point(hwXpos - x, hwYpos - y, hwColor);\n        e2 = err;\n        if (e2 <= y) {\n            err += ++ y * 2 + 1;\n            if(-x == y && e2 <= x) e2 = 0;\n        }\n        if(e2 > x) err += ++ x * 2 + 1;\n    } while(x <= 0);\n}\n\n//fill a rectangle out at the specified position on lcd.\nvoid TFT_LCD::lcd_fill_rect(uint16_t hwXpos,  //specify x position.\n                   uint16_t hwYpos,  //specify y position.\n                   uint16_t hwWidth, //specify the width of the rectangle.\n                   uint16_t hwHeight, //specify the height of the rectangle.\n                   uint16_t hwColor)  //specify the color of rectangle.\n{\n    uint16_t i, j;\n\n    if (hwXpos >= lcd_width || hwYpos >= lcd_height) {\n        return;\n    }\n\n    for(i = 0; i < hwHeight; i ++){\n        for(j = 0; j < hwWidth; j ++){\n            lcd_draw_point(hwXpos + j, hwYpos + i, hwColor);\n        }\n    }\n}\n\n//draw a vertical line at the specified position on lcd.\nvoid TFT_LCD::lcd_draw_v_line(uint16_t hwXpos, //specify x position.\n                        uint16_t hwYpos, //specify y position.\n                        uint16_t hwHeight, //specify the height of the vertical line.\n                        uint16_t hwColor)  //specify the color of the vertical line.\n{\n    uint16_t i, y1 = min(hwYpos + hwHeight, lcd_height - 1);\n\n    if (hwXpos >= lcd_width || hwYpos >= lcd_height) {\n        return;\n    }\n\n    for (i = hwYpos; i < y1; i ++) {\n        lcd_draw_point(hwXpos, i, hwColor);\n    }\n}\n\n//draw a horizonal line at the specified position on lcd.\nvoid TFT_LCD::lcd_draw_h_line(uint16_t hwXpos, //specify x position.\n                        uint16_t hwYpos,  //specify y position.\n                        uint16_t hwWidth, //specify the width of the horizonal line.\n                        uint16_t hwColor) //specify the color of the horizonal line.\n{\n    uint16_t i, x1 = min(hwXpos + hwWidth, lcd_width - 1);\n\n    if (hwXpos >= lcd_width || hwYpos >= lcd_height) {\n        return;\n    }\n\n    for (i = hwXpos; i < x1; i ++) {\n        lcd_draw_point(i, hwYpos, hwColor);\n    }\n}\n\nvoid TFT_LCD::lcd_draw_rect(uint16_t hwXpos,  //specify x position.\n                      uint16_t hwYpos,  //specify y position.\n                      uint16_t hwWidth, //specify the width of the rectangle.\n                      uint16_t hwHeight, //specify the height of the rectangle.\n                      uint16_t hwColor)  //specify the color of rectangle.\n{\n    if (hwXpos >= lcd_width || hwYpos >= lcd_height) {\n        return;\n    }\n\n    lcd_draw_h_line(hwXpos, hwYpos, hwWidth, hwColor);\n    lcd_draw_h_line(hwXpos, hwYpos + hwHeight, hwWidth, hwColor);\n    lcd_draw_v_line(hwXpos, hwYpos, hwHeight, hwColor);\n    lcd_draw_v_line(hwXpos + hwWidth, hwYpos, hwHeight + 1, hwColor);\n}\n\nuint16_t TFT_LCD::get_lcd_width(void)\n{\n    return lcd_width;\n}\n\nuint16_t TFT_LCD::get_lcd_height(void)\n{\n    return lcd_height;\n}\n\n\nTFT_LCD TFTLCD = TFT_LCD();\n/*********************************************************************************************************\n  END FILE\n*********************************************************************************************************/\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/CAMERA/ov7725_al422b/src/tftLcd.h",
    "content": "#ifndef __TFT_LCD_h\n#define __TFT_LCD_h\n\n#include <avr/pgmspace.h>\n#include <SPI.h>\n#include <digitalWriteFast.h>\n\n#include \"font.h\"\n\n//Basic Colors for RGB565\n// #define WHITE          0xFFFF\n// #define BLACK          0x0000\n// #define BLUE           0x001F\n// #define BRED           0XF81F\n// #define GRED \t\t   0XFFE0\n// #define GBLUE\t\t   0X07FF\n// #define RED            0xF800\n// #define MAGENTA        0xF81F\n// #define GREEN          0x07E0\n// #define CYAN           0x7FFF\n// #define YELLOW         0xFFE0\n// #define BROWN \t\t   0XBC40\n// #define BRRED \t\t   0XFC07\n// #define GRAY  \t\t   0X8430\n\n//Colors for SPI DMA\n#define WHITE          0xFFFF\n#define BLACK          0x0000\n#define BLUE           0x1F00\n#define BRED           0x1FF8\n#define GRED \t\t   0xE0FF\n#define GBLUE\t\t   0xFF07\n#define RED            0x00F8\n#define MAGENTA        0x1FF8\n#define GREEN          0xE007\n#define CYAN           0xFF7F\n#define YELLOW         0xE0FF\n#define BROWN \t\t   0x40BC\n#define BRRED \t\t   0x07FC\n#define GRAY  \t\t   0x3084\n\n#define MACR_MY\t\t0x80\n#define MACR_MX\t\t0x40\n#define MACR_MV\t\t0x20\n#define MACR_ML\t\t0x10\n#define MACR_BGR\t0x08\n\n#define LCD_CMD      0\n#define LCD_DATA     1\n\n#define FONT_1206    12\n#define FONT_1608    16\n\n#define QVGA         0\n#define QQVGA        1\n#define QUARTERVIEW  2\n\n#define LCD_WIDTH    240\n#define LCD_HEIGHT   320\n\n\n#if  defined(__AVR_ATmega32U4__)\n\n#define __LCD_CS_OUT()    DDRB |= 0x40\n#define __LCD_CS_CLR()    PORTB &=~ 0x40\n#define __LCD_CS_SET()    PORTB |=  0x40\n\n#define __LCD_DC_OUT()    DDRE |= 0x40\n#define __LCD_DC_CLR()    PORTE &=~ 0x40\n#define __LCD_DC_SET()    PORTE |=  0x40\n\n#define __LCD_BKL_OUT()   DDRB |= 0x20\n#define __LCD_BKL_OFF()   PORTB &=~ 0x20\n#define __LCD_BKL_ON()    PORTB |=  0x20\n\n#elif defined(__AVR_ATmega328__)\n\n#define __LCD_CS_OUT()    DDRB |= 0x04\n#define __LCD_CS_CLR()    PORTB &=~ 0x04\n#define __LCD_CS_SET()    PORTB |=  0x04\n\n#define __LCD_DC_OUT()    DDRD |= 0x80\n#define __LCD_DC_CLR()    PORTD &=~ 0x80\n#define __LCD_DC_SET()    PORTD |=  0x80\n\n#define __LCD_BKL_OUT()   DDRB |= 0x02\n#define __LCD_BKL_OFF()   PORTB &=~ 0x02\n#define __LCD_BKL_ON()    PORTB |=  0x02\n\n#else\n\n#define LCD_DC_PIN         7\n#define LCD_BKL_PIN        9\n#define LCD_CS_PIN        10\n\n#define TP_PRESS_DOWN           0x80\n#define TP_PRESSED              0x40\n\n#define XPOS 0\n#define YPOS 1\n\n#define TOUCH_MIN 127\n#define TOUCH_MAX 1950\n#define TOUCH_RANGE (TOUCH_MAX-TOUCH_MIN)\n\n#define LCD_MAX_X 240\n#define LCD_MAX_Y 320\n\n#define __LCD_CS_OUT()    pinMode(LCD_CS_PIN, OUTPUT)\n#define __LCD_CS_CLR()    digitalWriteFast(LCD_CS_PIN, LOW)\n#define __LCD_CS_SET()    digitalWriteFast(LCD_CS_PIN, HIGH)\n\n#define __LCD_DC_OUT()    pinMode(LCD_DC_PIN, OUTPUT)\n#define __LCD_DC_CLR()    digitalWriteFast(LCD_DC_PIN, LOW)\n#define __LCD_DC_SET()    digitalWriteFast(LCD_DC_PIN, HIGH)\n\n#define __LCD_BKL_OUT()   pinMode(LCD_BKL_PIN, OUTPUT)\n#define __LCD_BKL_OFF()   digitalWriteFast(LCD_BKL_PIN, LOW)\n#define __LCD_BKL_ON()    digitalWriteFast(LCD_BKL_PIN, HIGH)\n\n#endif\n\n#define __LCD_WRITE_BYTE(__DATA)       SPI.transfer(__DATA)\n\n\nclass TFT_LCD\n{\n\npublic:\n\n    void drawFrame();\n\tvoid setAddrWindow(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1);\n\tvoid LCDRotation(uint8_t direction);\n\tvoid setLcdMemoryArea(uint8_t size);\n\tvoid swapLCDWH(bool swapXY)\n\t{\n\t\tif(swapXY == true)\n\t\t{\n\t\t\tlcd_width = LCD_HEIGHT;\n\t\t\tlcd_height = LCD_WIDTH;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tlcd_width = LCD_WIDTH;\n\t\t\tlcd_height = LCD_HEIGHT;\n\t\t}\n\t}\n\n\tvoid lcd_write_byte(uint8_t chByte, uint8_t chCmd)\n\t{\n\t    if (chCmd) {\n\t        __LCD_DC_SET();\n\t    } else {\n\t        __LCD_DC_CLR();\n\t    }\n\n\t    __LCD_CS_CLR();\n\t    __LCD_WRITE_BYTE(chByte);\n\t    __LCD_CS_SET();\n\t}\n\n\tinline void lcd_write_word(uint16_t hwData)\n\t{\n\t\t__LCD_DC_SET();\n\t    __LCD_CS_CLR();\n\t    __LCD_WRITE_BYTE(hwData >> 8);\n\t    __LCD_WRITE_BYTE(hwData & 0xFF);\n\t    __LCD_CS_SET();\n\t}\n\n\n\t//write a word(two bytes) to the specified register of lcd.\n\t//chRegister address of the register of lcd.\n\t//hwValue value is written to the specified register.\n\tvoid lcd_write_register(uint8_t chRegister, uint8_t chValue)\n\t{\n\t\tlcd_write_byte(chRegister, LCD_CMD);\n\t\tlcd_write_byte(chValue, LCD_DATA);\n\t}\n\n\t//set the specified position of cursor on lcd.\n\t//hwXpos specify x position\n\t//hwYpos specify y position\n\tvoid lcd_set_cursor(uint16_t hwXpos, uint16_t hwYpos)\n\t{\n\t\tif (hwXpos >= lcd_width|| hwYpos >= lcd_height) {\n\t\t\treturn;\n\t\t}\n\n\t\tlcd_write_register(0x02, hwXpos >> 8);\n\t\tlcd_write_register(0x03, hwXpos & 0xFF); //Column Start\n\t\tlcd_write_register(0x06, hwYpos >> 8);\n\t\tlcd_write_register(0x07, hwYpos & 0xFF); //Row Start\n\t}\n\n    //clear the lcd with the specified color.\n\tvoid lcd_clear_screen(uint16_t hwColor)\n\t{\n\t\tuint32_t i, wCount = lcd_width;\n\n\t\twCount *= lcd_height;\n\n\t\tlcd_set_cursor(0, 0);\n\t\tlcd_write_byte(0x22, LCD_CMD);\n\n\t    __LCD_DC_SET();\n\t\t__LCD_CS_CLR();\n\t\tfor (i = 0; i < wCount; i ++) {\n\t\t\t__LCD_WRITE_BYTE(hwColor >> 8);\n\t\t\t__LCD_WRITE_BYTE(hwColor & 0xFF);\n\t\t}\n\t\t__LCD_CS_SET();\n\t}\n\n\tvoid lcd_init ();\n\tvoid lcd_draw_point(uint16_t hwXpos, uint16_t hwYpos, uint16_t hwColor);\n\tvoid lcd_display_char(uint16_t hwXpos, //specify x position.\n                         uint16_t hwYpos, //specify y position.\n                         uint8_t chChr,   //a char is display.\n                         uint8_t chSize,  //specify the size of the char\n                         uint16_t hwColor); //specify the color of the char\n\t//display a number at the specified position on lcd.\n\tvoid lcd_display_num(uint16_t hwXpos,  //specify x position.\n\t                          uint16_t hwYpos, //specify y position.\n\t                          uint32_t chNum,  //a number is display.\n\t                          uint8_t chLen,   //length ot the number\n\t                          uint8_t chSize,  //specify the size of the number\n\t                          uint16_t hwColor); //specify the color of the number\n\t//display a string at the specified position on lcd.\n\tvoid lcd_display_string(uint16_t hwXpos, //specify x position.\n\t                         uint16_t hwYpos,   //specify y position.\n\t                         const uint8_t *pchString,  //a pointer to string\n\t                         uint8_t chSize,    // the size of the string\n\t                         uint16_t hwColor);  // specify the color of the string\n  \tvoid lcd_draw_line(uint16_t hwXpos0, //specify x0 position.\n                    uint16_t hwYpos0, //specify y0 position.\n                    uint16_t hwXpos1, //specify x1 position.\n                    uint16_t hwYpos1, //specify y1 position.\n                    uint16_t hwColor); //specify the color of the line\n  \tvoid lcd_draw_circle(uint16_t hwXpos,  //specify x position.\n                      uint16_t hwYpos,  //specify y position.\n                      uint16_t hwRadius, //specify the radius of the circle.\n                      uint16_t hwColor);  //specify the color of the circle.\n  \tvoid lcd_fill_rect(uint16_t hwXpos,  //specify x position.\n                  uint16_t hwYpos,  //specify y position.\n                  uint16_t hwWidth, //specify the width of the rectangle.\n                  uint16_t hwHeight, //specify the height of the rectangle.\n                  uint16_t hwColor);  //specify the color of rectangle.\n  \tvoid lcd_draw_v_line(uint16_t hwXpos, //specify x position.\n                      uint16_t hwYpos, //specify y position.\n                      uint16_t hwHeight, //specify the height of the vertical line.\n                      uint16_t hwColor);  //specify the color of the vertical line.\n  \tvoid lcd_draw_h_line(uint16_t hwXpos, //specify x position.\n                      uint16_t hwYpos,  //specify y position.\n                      uint16_t hwWidth, //specify the width of the horizonal line.\n                      uint16_t hwColor); //specify the color of the horizonal line.\n\tvoid lcd_draw_rect(uint16_t hwXpos,  //specify x position.\n\t\t\t\t\tuint16_t hwYpos,  //specify y position.\n\t\t\t\t\tuint16_t hwWidth, //specify the width of the rectangle.\n\t\t\t\t\tuint16_t hwHeight, //specify the height of the rectangle.\n\t\t\t\t\tuint16_t hwColor);  //specify the color of rectangle.\n\tuint16_t get_lcd_width(void);\n\tuint16_t get_lcd_height(void);\n\nprivate:\nuint16_t lcd_width;\nuint16_t lcd_height;\n\n};\n\nextern TFT_LCD TFTLCD;\n\n#endif\n\n/*********************************************************************************************************\n  END FILE\n*********************************************************************************************************/\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/CAN/canMaskFilter/canMaskFilter.ino",
    "content": "/*******************************************************************************\n* Copyright (c) 2016, ROBOTIS CO., LTD.\n* All rights reserved.\n*\n* Redistribution and use in source and binary forms, with or without\n* modification, are permitted provided that the following conditions are met:\n*\n* * Redistributions of source code must retain the above copyright notice, this\n*   list of conditions and the following disclaimer.\n*\n* * Redistributions in binary form must reproduce the above copyright notice,\n*   this list of conditions and the following disclaimer in the documentation\n*   and/or other materials provided with the distribution.\n*\n* * Neither the name of ROBOTIS nor the names of its\n*   contributors may be used to endorse or promote products derived from\n*   this software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*******************************************************************************/\n\n/* Author: Kei */\n\n#include <CAN.h>\n\nuint32_t id, mask, i;\ncan_message_t rx_msg;\n/*\n *  typedef struct \n *  {\n *    uint32_t id      : Identifier of received message\n *    uint32_t length  : Length of received message data\n *    uint8_t  data[8] : Data of received message\n *    uint8_t  format  : Type of ID\n *  } can_message_t;\n * \n * BAUDRATE :\n *   CAN_BAUD_125K\n *   CAN_BAUD_250K\n *   CAN_BAUD_500K\n *   CAN_BAUD_1000K\n * \n * FORMAT :\n *   CAN_STD_FORMAT\n *   CAN_EXT_FORMAT\n*/\n\nvoid setup()\n{\n  Serial.begin(115200);\n\n  Serial.println(\"=================================\");\n  Serial.println(\"=== CAN RX Interrupt Example! ===\");\n\n  if (CanBus.begin(CAN_BAUD_125K, CAN_STD_FORMAT) == false)\n  {\n    Serial.println(\"CAN open fail!!\");\n  }\n  else\n  {\n    id = 0x123;\n    mask = 0x1FFFFFFF; // Extended ID all bit mask (must match!)\n    CanBus.configFilter(id, mask, CAN_EXT_FORMAT);\n    CanBus.attachRxInterrupt(canRxHandlerTemplate);\n  }\n}\n\nvoid loop()\n{\n}\n\nvoid canRxHandlerTemplate(can_message_t *arg)\n{\n  if(CanBus.readMessage(&rx_msg))\n  {\n    Serial.print(\"ID : \");\n    Serial.print(arg->id, HEX);\n    Serial.print(\", Length : \");\n    Serial.print(arg->length);\n    Serial.print(\", Data : \");\n    for (i = 0; i < arg->length; i++)\n    {\n      Serial.print(arg->data[i], HEX);\n      Serial.print(\" \");\n    }\n    Serial.println();\n  }\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/CAN/canRxInterrupt/canRxInterrupt.ino",
    "content": "/*******************************************************************************\n* Copyright (c) 2016, ROBOTIS CO., LTD.\n* All rights reserved.\n*\n* Redistribution and use in source and binary forms, with or without\n* modification, are permitted provided that the following conditions are met:\n*\n* * Redistributions of source code must retain the above copyright notice, this\n*   list of conditions and the following disclaimer.\n*\n* * Redistributions in binary form must reproduce the above copyright notice,\n*   this list of conditions and the following disclaimer in the documentation\n*   and/or other materials provided with the distribution.\n*\n* * Neither the name of ROBOTIS nor the names of its\n*   contributors may be used to endorse or promote products derived from\n*   this software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*******************************************************************************/\n\n/* Author: Kei */\n\n#include <CAN.h>\n\nuint32_t id, i;\ncan_message_t rx_msg;\n/*\n *  typedef struct \n *  {\n *    uint32_t id      : Identifier of received message\n *    uint32_t length  : Length of received message data\n *    uint8_t  data[8] : Data of received message\n *    uint8_t  format  : Type of ID\n *  } can_message_t;\n * \n * BAUDRATE :\n *   CAN_BAUD_125K\n *   CAN_BAUD_250K\n *   CAN_BAUD_500K\n *   CAN_BAUD_1000K\n * \n * FORMAT :\n *   CAN_STD_FORMAT\n *   CAN_EXT_FORMAT\n*/\n\n\nvoid setup()\n{\n  Serial.begin(115200);\n\n  Serial.println(\"=================================\");\n  Serial.println(\"=== CAN RX Interrupt Example! ===\");\n\n  if (CanBus.begin() == false)\n  {\n    Serial.println(\"CAN open fail!!\");\n  }\n  else\n  {\n    id = 0x123;\n    CanBus.configFilter(id, 0);\n    CanBus.attachRxInterrupt(canRxHandlerTemplate);\n  }\n}\n\nvoid loop()\n{\n}\n\nvoid canRxHandlerTemplate(can_message_t *arg)\n{\n  if(CanBus.readMessage(&rx_msg))\n  {\n    Serial.print(\"ID : \");\n    Serial.print(arg->id, HEX);\n    Serial.print(\", Length : \");\n    Serial.print(arg->length);\n    Serial.print(\", Data : \");\n    for (i = 0; i < arg->length; i++)\n    {\n      Serial.print(arg->data[i], HEX);\n      Serial.print(\" \");\n    }\n    Serial.println();\n  }\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/CAN/canTxRxByte/canTxRxByte.ino",
    "content": "/*******************************************************************************\n* Copyright (c) 2016, ROBOTIS CO., LTD.\n* All rights reserved.\n*\n* Redistribution and use in source and binary forms, with or without\n* modification, are permitted provided that the following conditions are met:\n*\n* * Redistributions of source code must retain the above copyright notice, this\n*   list of conditions and the following disclaimer.\n*\n* * Redistributions in binary form must reproduce the above copyright notice,\n*   this list of conditions and the following disclaimer in the documentation\n*   and/or other materials provided with the distribution.\n*\n* * Neither the name of ROBOTIS nor the names of its\n*   contributors may be used to endorse or promote products derived from\n*   this software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*******************************************************************************/\n\n/* Author: Kei */\n\n#include <CAN.h>\n\nuint32_t id;\nuint8_t data;\n/*\n *  typedef struct \n *  {\n *    uint32_t id      : Identifier of received message\n *    uint32_t length  : Length of received message data\n *    uint8_t  data[8] : Data of received message\n *    uint8_t  format  : Type of ID\n *  } can_message_t;\n * \n * BAUDRATE :\n *   CAN_BAUD_125K\n *   CAN_BAUD_250K\n *   CAN_BAUD_500K\n *   CAN_BAUD_1000K\n * \n * FORMAT :\n *   CAN_STD_FORMAT\n *   CAN_EXT_FORMAT\n*/\n\nvoid setup() \n{\n  Serial.begin(115200);\n\n  Serial.println(\"===============================\");\n  Serial.println(\"=== CAN Chat Example(Char)! ===\");\n\n  if(CanBus.begin(_DEF_CAN_BAUD_125K, CAN_STD_FORMAT) == false)\n  {\n    Serial.println(\"CAN open fail!!\");\n  }\n  else\n  {\n    id = 0x123;\n    CanBus.configFilter(id, 0); // It(mask = 0) can receive message from all ID. \n  }\n}\n\nvoid loop() \n{\n  if(CanBus.availableMessage())\n  {\n    Serial.print((char)CanBus.read());\n  }\n\n  if(Serial.available())\n  {\n    data = Serial.read();\n    CanBus.write(id, &data, 1);\n  }\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/CAN/canTxRxMessage/canTxRxMessage.ino",
    "content": "/*******************************************************************************\n* Copyright (c) 2016, ROBOTIS CO., LTD.\n* All rights reserved.\n*\n* Redistribution and use in source and binary forms, with or without\n* modification, are permitted provided that the following conditions are met:\n*\n* * Redistributions of source code must retain the above copyright notice, this\n*   list of conditions and the following disclaimer.\n*\n* * Redistributions in binary form must reproduce the above copyright notice,\n*   this list of conditions and the following disclaimer in the documentation\n*   and/or other materials provided with the distribution.\n*\n* * Neither the name of ROBOTIS nor the names of its\n*   contributors may be used to endorse or promote products derived from\n*   this software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*******************************************************************************/\n\n/* Author: Kei */\n\n#include <CAN.h>\n\n#define SEND_INTERVAL_MS 1000\n\nuint32_t t_time, id, i;\ncan_message_t tx_msg, rx_msg;\n/*\n *  typedef struct \n *  {\n *    uint32_t id      : Identifier of received message\n *    uint32_t length  : Length of received message data\n *    uint8_t  data[8] : Data of received message\n *    uint8_t  format  : Type of ID\n *  } can_message_t;\n * \n * BAUDRATE :\n *   CAN_BAUD_125K\n *   CAN_BAUD_250K\n *   CAN_BAUD_500K\n *   CAN_BAUD_1000K\n * \n * FORMAT :\n *   CAN_STD_FORMAT\n *   CAN_EXT_FORMAT\n*/\n\nvoid setup()\n{\n  Serial.begin(115200);\n\n  Serial.println(\"============================\");\n  Serial.println(\"=== CAN Message Example! ===\");\n\n  if (CanBus.begin(CAN_BAUD_1000K, CAN_STD_FORMAT) == false)\n  {\n    Serial.println(\"CAN open fail!!\");\n  }\n  else\n  {\n    id = 0x123;\n    \n    CanBus.configFilter(id, 0, CAN_EXT_FORMAT);\n  }\n}\n\nvoid loop()\n{\n  if (CanBus.availableMessage())\n  {\n    if(CanBus.readMessage(&rx_msg))\n    {\n      Serial.print(\"ID : \");\n      Serial.print(rx_msg.id, HEX);\n      Serial.print(\", Length : \");\n      Serial.print(rx_msg.length);\n      Serial.print(\", Data : \");\n      for (i = 0; i < rx_msg.length; i++)\n      {\n        Serial.print(rx_msg.data[i], HEX);\n        Serial.print(\" \");\n      }\n      Serial.println();\n    }\n  }\n\n  if (millis() - t_time >= SEND_INTERVAL_MS)\n  {\n    t_time = millis();\n\n    tx_msg.id = 0x123;\n    tx_msg.format = CAN_EXT_FORMAT;\n    for(i = 0; i < 8; i++)\n    {\n      tx_msg.data[i] = (uint8_t)micros() + i;\n    }\n    tx_msg.length = i;\n\n    CanBus.writeMessage(&tx_msg);\n  }\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/EEPROM/eeprom_clear/eeprom_clear.ino",
    "content": "/*\n * EEPROM Clear\n *\n * Sets all of the bytes of the EEPROM to 0.\n * Please see eeprom_iteration for a more in depth\n * look at how to traverse the EEPROM.\n *\n * This example code is in the public domain.\n */\n\n#include <EEPROM.h>\n\nvoid setup() {\n  // initialize the LED pin as an output.\n  pinMode(13, OUTPUT);\n  \n  /***\n    Iterate through each byte of the EEPROM storage.\n\n    Larger AVR processors have larger EEPROM sizes, E.g:\n    - Arduno Duemilanove: 512b EEPROM storage.\n    - Arduino Uno:        1kb EEPROM storage.\n    - Arduino Mega:       4kb EEPROM storage.\n\n    Rather than hard-coding the length, you should use the pre-provided length function.\n    This will make your code portable to all AVR processors.\n  ***/\n\n  for (int i = 0 ; i < EEPROM.length() ; i++) {\n    EEPROM.write(i, 0);\n  }\n\n  // turn the LED on when we're done\n  digitalWrite(13, HIGH);\n}\n\nvoid loop() {\n  /** Empty loop. **/\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/EEPROM/eeprom_crc/eeprom_crc.ino",
    "content": "/***\n    Written by Christopher Andrews.\n    CRC algorithm generated by pycrc, MIT licence ( https://github.com/tpircher/pycrc ).\n\n\tA CRC is a simple way of checking whether data has changed or become corrupted.\n\tThis example calculates a CRC value directly on the EEPROM values.\n\tThe purpose of this example is to highlight how the EEPROM object can be used just like an array.\n***/\n\n#include <Arduino.h>\n#include <EEPROM.h>\n\nvoid setup() {\n\n  //Start serial\n  Serial.begin(9600);\n  while (!Serial) {\n    ; // wait for serial port to connect. Needed for native USB port only\n  }\n\n  //Print length of data to run CRC on.\n  Serial.print(\"EEPROM length: \");\n  Serial.println(EEPROM.length());\n\n  //Print the result of calling eeprom_crc()\n  Serial.print(\"CRC32 of EEPROM data: 0x\");\n  Serial.println(eeprom_crc(), HEX);\n  Serial.print(\"\\n\\nDone!\");\n}\n\nvoid loop() {\n  /* Empty loop */\n}\n\nunsigned long eeprom_crc(void) {\n\n  const unsigned long crc_table[16] = {\n    0x00000000, 0x1db71064, 0x3b6e20c8, 0x26d930ac,\n    0x76dc4190, 0x6b6b51f4, 0x4db26158, 0x5005713c,\n    0xedb88320, 0xf00f9344, 0xd6d6a3e8, 0xcb61b38c,\n    0x9b64c2b0, 0x86d3d2d4, 0xa00ae278, 0xbdbdf21c\n  };\n\n  unsigned long crc = ~0L;\n\n  for (int index = 0 ; index < EEPROM.length()  ; ++index) {\n    crc = crc_table[(crc ^ EEPROM[index]) & 0x0f] ^ (crc >> 4);\n    crc = crc_table[(crc ^ (EEPROM[index] >> 4)) & 0x0f] ^ (crc >> 4);\n    crc = ~crc;\n  }\n  return crc;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/EEPROM/eeprom_get/eeprom_get.ino",
    "content": "/***\n    eeprom_get example.\n\n    This shows how to use the EEPROM.get() method.\n\n    To pre-set the EEPROM data, run the example sketch eeprom_put.\n    This sketch will run without it, however, the values shown\n    will be shown from what ever is already on the EEPROM.\n\n    This may cause the serial object to print out a large string\n    of garbage if there is no null character inside one of the strings\n    loaded.\n\n    Written by Christopher Andrews 2015\n    Released under MIT licence.\n***/\n\n#include <EEPROM.h>\n\nvoid setup() {\n\n  float f = 0.00f;   //Variable to store data read from EEPROM.\n  int eeAddress = 0; //EEPROM address to start reading from\n\n  Serial.begin(9600);\n  while (!Serial) {\n    ; // wait for serial port to connect. Needed for native USB port only\n  }\n  Serial.print(\"Read float from EEPROM: \");\n\n  //Get the float data from the EEPROM at position 'eeAddress'\n  EEPROM.get(eeAddress, f);\n  Serial.println(f, 3);    //This may print 'ovf, nan' if the data inside the EEPROM is not a valid float.\n\n  /***\n    As get also returns a reference to 'f', you can use it inline.\n    E.g: Serial.print( EEPROM.get( eeAddress, f ) );\n  ***/\n\n  /***\n    Get can be used with custom structures too.\n    I have separated this into an extra function.\n  ***/\n\n  secondTest(); //Run the next test.\n}\n\nstruct MyObject {\n  float field1;\n  byte field2;\n  char name[10];\n};\n\nvoid secondTest() {\n  int eeAddress = sizeof(float); //Move address to the next byte after float 'f'.\n\n  MyObject customVar; //Variable to store custom object read from EEPROM.\n  EEPROM.get(eeAddress, customVar);\n\n  Serial.println(\"Read custom object from EEPROM: \");\n  Serial.println(customVar.field1);\n  Serial.println(customVar.field2);\n  Serial.println(customVar.name);\n}\n\nvoid loop() {\n  /* Empty loop */\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/EEPROM/eeprom_iteration/eeprom_iteration.ino",
    "content": "/***\n    eeprom_iteration example.\n\n    A set of example snippets highlighting the\n    simplest methods for traversing the EEPROM.\n\n    Running this sketch is not necessary, this is\n    simply highlighting certain programming methods.\n\n    Written by Christopher Andrews 2015\n    Released under MIT licence.\n***/\n\n#include <EEPROM.h>\n\nvoid setup() {\n\n  /***\n    Iterate the EEPROM using a for loop.\n  ***/\n\n  for (int index = 0 ; index < EEPROM.length() ; index++) {\n\n    //Add one to each cell in the EEPROM\n    EEPROM[ index ] += 1;\n  }\n\n  /***\n    Iterate the EEPROM using a while loop.\n  ***/\n\n  int index = 0;\n\n  while (index < EEPROM.length()) {\n\n    //Add one to each cell in the EEPROM\n    EEPROM[ index ] += 1;\n    index++;\n  }\n\n  /***\n    Iterate the EEPROM using a do-while loop.\n  ***/\n\n  int idx = 0;  //Used 'idx' to avoid name conflict with 'index' above.\n\n  do {\n\n    //Add one to each cell in the EEPROM\n    EEPROM[ idx ] += 1;\n    idx++;\n  } while (idx < EEPROM.length());\n\n\n} //End of setup function.\n\nvoid loop() {}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/EEPROM/eeprom_put/eeprom_put.ino",
    "content": "/***\n    eeprom_put example.\n\n    This shows how to use the EEPROM.put() method.\n    Also, this sketch will pre-set the EEPROM data for the\n    example sketch eeprom_get.\n\n    Note, unlike the single byte version EEPROM.write(),\n    the put method will use update semantics. As in a byte\n    will only be written to the EEPROM if the data is actually\n    different.\n\n    Written by Christopher Andrews 2015\n    Released under MIT licence.\n***/\n\n#include <EEPROM.h>\n\nstruct MyObject {\n  float field1;\n  byte field2;\n  char name[10];\n};\n\nvoid setup() {\n\n  Serial.begin(9600);\n  while (!Serial) {\n    ; // wait for serial port to connect. Needed for native USB port only\n  }\n\n  float f = 123.456f;  //Variable to store in EEPROM.\n  int eeAddress = 0;   //Location we want the data to be put.\n\n\n  //One simple call, with the address first and the object second.\n  EEPROM.put(eeAddress, f);\n\n  Serial.println(\"Written float data type!\");\n\n  /** Put is designed for use with custom structures also. **/\n\n  //Data to store.\n  MyObject customVar = {\n    3.14f,\n    65,\n    \"Working!\"\n  };\n\n  eeAddress += sizeof(float); //Move address to the next byte after float 'f'.\n\n  EEPROM.put(eeAddress, customVar);\n  Serial.print(\"Written custom data type! \\n\\nView the example sketch eeprom_get to see how you can retrieve the values!\");\n}\n\nvoid loop() {\n  /* Empty loop */\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/EEPROM/eeprom_read/eeprom_read.ino",
    "content": "/*\n * EEPROM Read\n *\n * Reads the value of each byte of the EEPROM and prints it\n * to the computer.\n * This example code is in the public domain.\n */\n\n#include <EEPROM.h>\n\n// start reading from the first byte (address 0) of the EEPROM\nint address = 0;\nbyte value;\n\nvoid setup() {\n  // initialize serial and wait for port to open:\n  Serial.begin(9600);\n  while (!Serial) {\n    ; // wait for serial port to connect. Needed for native USB port only\n  }\n}\n\nvoid loop() {\n  // read a byte from the current address of the EEPROM\n  value = EEPROM.read(address);\n\n  Serial.print(address);\n  Serial.print(\"\\t\");\n  Serial.print(value, DEC);\n  Serial.println();\n\n  /***\n    Advance to the next address, when at the end restart at the beginning.\n\n    Larger AVR processors have larger EEPROM sizes, E.g:\n    - Arduno Duemilanove: 512b EEPROM storage.\n    - Arduino Uno:        1kb EEPROM storage.\n    - Arduino Mega:       4kb EEPROM storage.\n\n    Rather than hard-coding the length, you should use the pre-provided length function.\n    This will make your code portable to all AVR processors.\n  ***/\n  address = address + 1;\n  if (address == EEPROM.length()) {\n    address = 0;\n  }\n\n  /***\n    As the EEPROM sizes are powers of two, wrapping (preventing overflow) of an\n    EEPROM address is also doable by a bitwise and of the length - 1.\n\n    ++address &= EEPROM.length() - 1;\n  ***/\n\n  delay(500);\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/EEPROM/eeprom_update/eeprom_update.ino",
    "content": "/***\n   EEPROM Update method\n\n   Stores values read from analog input 0 into the EEPROM.\n   These values will stay in the EEPROM when the board is\n   turned off and may be retrieved later by another sketch.\n\n   If a value has not changed in the EEPROM, it is not overwritten\n   which would reduce the life span of the EEPROM unnecessarily.\n\n   Released using MIT licence.\n ***/\n\n#include <EEPROM.h>\n\n/** the current address in the EEPROM (i.e. which byte we're going to write to next) **/\nint address = 0;\n\nvoid setup() {\n  /** EMpty setup **/\n}\n\nvoid loop() {\n  /***\n    need to divide by 4 because analog inputs range from\n    0 to 1023 and each byte of the EEPROM can only hold a\n    value from 0 to 255.\n  ***/\n  int val = analogRead(0) / 4;\n\n  /***\n    Update the particular EEPROM cell.\n    these values will remain there when the board is\n    turned off.\n  ***/\n  EEPROM.update(address, val);\n\n  /***\n    The function EEPROM.update(address, val) is equivalent to the following:\n\n    if( EEPROM.read(address) != val ){\n      EEPROM.write(address, val);\n    }\n  ***/\n\n\n  /***\n    Advance to the next address, when at the end restart at the beginning.\n\n    Larger AVR processors have larger EEPROM sizes, E.g:\n    - Arduno Duemilanove: 512b EEPROM storage.\n    - Arduino Uno:        1kb EEPROM storage.\n    - Arduino Mega:       4kb EEPROM storage.\n\n    Rather than hard-coding the length, you should use the pre-provided length function.\n    This will make your code portable to all AVR processors.\n  ***/\n  address = address + 1;\n  if (address == EEPROM.length()) {\n    address = 0;\n  }\n\n  /***\n    As the EEPROM sizes are powers of two, wrapping (preventing overflow) of an\n    EEPROM address is also doable by a bitwise and of the length - 1.\n\n    ++address &= EEPROM.length() - 1;\n  ***/\n\n  delay(100);\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/EEPROM/eeprom_write/eeprom_write.ino",
    "content": "/*\n * EEPROM Write\n *\n * Stores values read from analog input 0 into the EEPROM.\n * These values will stay in the EEPROM when the board is\n * turned off and may be retrieved later by another sketch.\n */\n\n#include <EEPROM.h>\n\n/** the current address in the EEPROM (i.e. which byte we're going to write to next) **/\nint addr = 0;\n\nvoid setup() {\n  /** Empty setup. **/\n}\n\nvoid loop() {\n  /***\n    Need to divide by 4 because analog inputs range from\n    0 to 1023 and each byte of the EEPROM can only hold a\n    value from 0 to 255.\n  ***/\n\n  int val = analogRead(0) / 4;\n\n  /***\n    Write the value to the appropriate byte of the EEPROM.\n    these values will remain there when the board is\n    turned off.\n  ***/\n\n  EEPROM.write(addr, val);\n\n  /***\n    Advance to the next address, when at the end restart at the beginning.\n\n    Larger AVR processors have larger EEPROM sizes, E.g:\n    - Arduno Duemilanove: 512b EEPROM storage.\n    - Arduino Uno:        1kb EEPROM storage.\n    - Arduino Mega:       4kb EEPROM storage.\n\n    Rather than hard-coding the length, you should use the pre-provided length function.\n    This will make your code portable to all AVR processors.\n  ***/\n  addr = addr + 1;\n  if (addr == EEPROM.length()) {\n    addr = 0;\n  }\n\n  /***\n    As the EEPROM sizes are powers of two, wrapping (preventing overflow) of an\n    EEPROM address is also doable by a bitwise and of the length - 1.\n\n    ++addr &= EEPROM.length() - 1;\n  ***/\n\n\n  delay(100);\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/Eigen/eigen_test/eigen_test.ino",
    "content": "// Example By: RandomVibe\r\n// Eigen Doc: http://eigen.tuxfamily.org/dox/\r\n// Quick Reference: http://eigen.tuxfamily.org/dox/QuickRefPage.html\r\n\r\n#include <Eigen.h>        // Calls main Eigen matrix class library\r\n#include <Eigen/LU>       // Calls inverse, determinant, LU decomp., etc.\r\nusing namespace Eigen;    // Eigen related statement; simplifies syntax for declaration of matrices\r\n\r\n\r\nvoid print_mtxf(const Eigen::MatrixXf& K);\r\n\r\nextern \"C\"\r\n{\r\n  extern int __io_putchar(int ch);\r\n}\r\n\r\n\r\nint __io_putchar(int ch)\r\n{\r\n  return Serial.write(ch);\r\n}\r\n\r\n\r\nvoid setup() {\r\n  uint32_t process_time;\r\n\r\n   Serial.begin(115200);\r\n   while(!Serial);\r\n\r\n   process_time = micros();\r\n   // DECLARE MATRICES\r\n   //--------------------\r\n   MatrixXf Pp(6,6);   // Produces 6x6 float matrix class\r\n   MatrixXf H(6,6);    // Note: without \"using namespace Eigen\", declaration would be: Eigen::MatrixXf H(6,6);\r\n   MatrixXf R(6,6);\r\n   MatrixXf X(6,6);\r\n   MatrixXf K(6,6);\r\n   MatrixXf Z(6,6);\r\n\r\n   // INPUT MATRICES (so-called comma-initialize syntax)\r\n   //---------------------------------------------------------\r\n   Pp << 0.3252,  0.3192,  1.0933, -0.0068, -1.0891, -1.4916,\r\n        -0.7549,  0.3129,  1.1093,  1.5326,  0.0326, -0.7423,\r\n         1.3703, -0.8649, -0.8637, -0.7697,  0.5525, -1.0616,\r\n        -1.7115, -0.0301,  0.0774,  0.3714,  1.1006,  2.3505,\r\n        -0.1022, -0.1649, -1.2141, -0.2256,  1.5442, -0.6156,\r\n        -0.2414,  0.6277, -1.1135,  1.1174,  0.0859,  0.7481 ;\r\n\r\n   H << 0.8147, 0.2785, 0.9572, 0.7922, 0.6787, 0.7060,\r\n        0.9058, 0.5469, 0.4854, 0.9595, 0.7577, 0.0318,\r\n        0.1270, 0.9575, 0.8003, 0.6557, 0.7431, 0.2769,\r\n        0.9134, 0.9649, 0.1419, 0.0357, 0.3922, 0.0462,\r\n        0.6324, 0.1576, 0.4218, 0.8491, 0.6555, 0.0971,\r\n        0.0975, 0.9706, 0.9157, 0.9340, 0.1712, 0.8235;\r\n\r\n   R << 0.3252,  0.3192,  1.0933, -0.0068, -1.0891, -1.4916,\r\n       -0.7549,  0.3129,  1.1093,  1.5326,  0.0326, -0.7423,\r\n        1.3703, -0.8649, -0.8637, -0.7697,  0.5525, -1.0616,\r\n       -1.7115, -0.0301,  0.0774,  0.3714,  1.1006,  2.3505,\r\n       -0.1022, -0.1649, -1.2141, -0.2256,  1.5442, -0.6156,\r\n       -0.2414,  0.6277, -1.1135,  1.1174,  0.0859,  0.7481;\r\n\r\n\r\n   // Kalman Gain Example; Matlab form:  K = Pp * H' * inv(H * Pp * H' + R)\r\n   //-----------------------------------\r\n   X  = H * Pp * H.transpose() + R;\r\n   K  = Pp * H.transpose() * X.inverse();\r\n\r\n   Serial.print(\"us : \");\r\n   Serial.println(micros()-process_time);\r\n   // Print Result\r\n   //----------------------------\r\n   print_mtxf(K);      // Print Matrix Result (passed by reference)\r\n\r\n\r\n   Serial.println(\"end\");\r\n}\r\n\r\n\r\n\r\n\r\nvoid loop() {\r\n // put your main code here, to run repeatedly:\r\n\r\n}\r\n\r\n\r\n\r\n\r\n// PRINT MATRIX (float type)\r\n// By: randomvibe\r\n//-----------------------------\r\nvoid print_mtxf(const Eigen::MatrixXf& X)\r\n{\r\n   int i, j, nrow, ncol;\r\n\r\n   nrow = X.rows();\r\n   ncol = X.cols();\r\n\r\n   Serial.print(\"nrow: \"); Serial.println(nrow);\r\n   Serial.print(\"ncol: \"); Serial.println(ncol);\r\n   Serial.println();\r\n\r\n   for (i=0; i<nrow; i++)\r\n   {\r\n       for (j=0; j<ncol; j++)\r\n       {\r\n           Serial.print(X(i,j), 6);   // print 6 decimal places\r\n           Serial.print(\", \");\r\n       }\r\n       Serial.println();\r\n   }\r\n   Serial.println();\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/FreeRTOS/thread_led/thread_led.ino",
    "content": "#include <RTOS.h>\n\n\nosThreadId thread_id_loop;\nosThreadId thread_id_led;\n\n\n\nstatic void Thread_Loop(void const *argument)\n{\n  (void) argument;\n\n\n  for(;;)\n  {\n    loop();\n  }\n}\n\n\nvoid setup() \n{\n  Serial.begin(115200);\n\n  // define thread\n  osThreadDef(THREAD_NAME_LOOP, Thread_Loop, osPriorityNormal, 0, 1024);\n  osThreadDef(THREAD_NAME_LED,  Thread_Led,  osPriorityNormal, 0, 1024);\n\n  // create thread\n  thread_id_loop = osThreadCreate(osThread(THREAD_NAME_LOOP), NULL);\n  thread_id_led  = osThreadCreate(osThread(THREAD_NAME_LED), NULL);\n\n  // start kernel\n  osKernelStart();\n\n}\n\nvoid loop() \n{\n  static uint32_t cnt = 0;\n  \n  Serial.print(\"RTOS Cnt : \");\n  Serial.println(cnt++);\n  osDelay(100);  \n}\n\nstatic void Thread_Led(void const *argument)\n{\n  (void) argument;\n\n\n  pinMode(13, OUTPUT);\n\n  for(;;)\n  {\n    digitalWrite(13, !digitalRead(13));\n    osDelay(300);\n  }\n}\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/LDS/drawLDS/drawLDS.ino",
    "content": "/*******************************************************************************\r\n* Copyright (c) 2018, ROBOTIS CO., LTD.\r\n* All rights reserved.\r\n*\r\n* Redistribution and use in source and binary forms, with or without\r\n* modification, are permitted provided that the following conditions are met:\r\n*\r\n* * Redistributions of source code must retain the above copyright notice, this\r\n*   list of conditions and the following disclaimer.\r\n*\r\n* * Redistributions in binary form must reproduce the above copyright notice,\r\n*   this list of conditions and the following disclaimer in the documentation\r\n*   and/or other materials provided with the distribution.\r\n*\r\n* * Neither the name of ROBOTIS nor the names of its\r\n*   contributors may be used to endorse or promote products derived from\r\n*   this software without specific prior written permission.\r\n*\r\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n*******************************************************************************/\r\n\r\n/* Author: Baram */\r\n\r\n#include <LcdTouchPanel.h>\r\n#include \"lds.h\"\r\n\r\n\r\n\r\n#define DISTANCE_MAX    1000      // 100.0 cm \r\n\r\n\r\n\r\nlds_scan_t lds_scan;\r\n\r\n\r\n\r\n\r\nvoid setup() {\r\n  // put your setup code here, to run once:\r\n  Serial.begin(115760);\r\n  Serial2.begin(230400);\r\n\r\n  ldsInit(&lds_scan);\r\n  tftInit();\r\n\r\n  delay(100);\r\n  Serial2.print(\"b\");\r\n\r\n  pinMode(BDPIN_PUSH_SW_1, INPUT);\r\n  pinMode(BDPIN_PUSH_SW_2, INPUT);  \r\n}\r\n\r\nvoid loop() {\r\n  // put your main code here, to run repeatedly:\r\n  static uint32_t pre_time;\r\n\r\n\r\n  if (Serial.available())\r\n  {\r\n    Serial2.write(Serial.read());\r\n  }\r\n\r\n  while(Serial2.available() > 0)\r\n  {\r\n    if (ldsUpdate(&lds_scan, Serial2.read()) == true)\r\n    {\r\n      drawPoint();\r\n    }\r\n  }\r\n  \r\n  if (millis()-pre_time >= 50)\r\n  {\r\n    pre_time = millis();\r\n\r\n    /*\r\n    Serial.print(lds_scan.data[1].range);\r\n    Serial.print(\" \");\r\n    Serial.print(lds_scan.data[1].intensity);\r\n    Serial.print(\" \");\r\n    Serial.print(lds_scan.scan_time);\r\n    Serial.println(\" \");    \r\n    */\r\n  }\r\n\r\n}\r\n\r\nvoid drawPoint(void)\r\n{\r\n  int16_t cx = 240/2;\r\n  int16_t cy = 320/2;\r\n  int16_t x;\r\n  int16_t y;\r\n  int32_t d;\r\n\r\n  // double fx;\r\n  // double fy;\r\n  double r;\r\n  double offset_r = 90. * M_PI / 180.;\r\n  static uint8_t mode = 0;\r\n  float  h;\r\n  uint16_t color;\r\n  uint8_t rgb[3];\r\n\r\n  //uint32_t pre_time = millis();\r\n\r\n  Tft.lcd_fill_rect(0, 0, LCD_WIDTH, LCD_HEIGHT, BLACK);\r\n\r\n\r\n  if (mode == 0)\r\n  {\r\n    for (int i=0; i<360; i++)\r\n    {\r\n      // range normalize\r\n      d = constrain(lds_scan.data[i].range, 0, 3500);\r\n      d = map(d, 0, DISTANCE_MAX, 0, 120);\r\n\r\n      r = i * 2.0 * M_PI / 360.;\r\n      x = cx + cos(r+offset_r) * d;\r\n      y = cy - sin(r+offset_r) * d;\r\n\r\n      x = constrain(x, 0, 237);\r\n      y = constrain(y, 0, 319-11);\r\n\r\n      // intensity normalize\r\n      h = map(constrain(lds_scan.data[i].intensity, 0, 5000), 0, 5000, 0, 1000) / 1000.;\r\n      hslToRgb(h, 0.5, 0.5, rgb);\r\n      color = color565(rgb[0], rgb[1], rgb[2]);\r\n\r\n      Tft.lcd_fill_rect(x, y, 3, 3, color);\r\n\r\n      if (i == 0)\r\n      {\r\n        x = cx + cos(r+offset_r) * 118;\r\n        y = cy - sin(r+offset_r) * 118;      \r\n        Tft.lcd_draw_line(cx, cy, x, y, WHITE);\r\n      }\r\n    }\r\n\r\n    drawPalletBar();\r\n  }\r\n\r\n  if (mode == 1)\r\n  {\r\n    for (int i=0; i<320; i+=2)\r\n    {\r\n      d = constrain(lds_scan.data[i].range, 0, 2000);\r\n      d = map(d, 0, 2000, 0, 200);\r\n      Tft.lcd_draw_line(0, i, d, i, GREEN);\r\n    }\r\n    for (int i=1; i<320; i+=2)\r\n    {\r\n      d = constrain(lds_scan.data[i-1].intensity, 0, 5000);\r\n      d = map(d, 0, 5000, 0, 200);\r\n      Tft.lcd_draw_line(0, i, d, i, WHITE);\r\n    }    \r\n  }\r\n  \r\n  Tft.drawFrame();\r\n\r\n\r\n  if (digitalRead(BDPIN_PUSH_SW_1) == HIGH)\r\n  {\r\n    mode = 0;\r\n  }\r\n  if (digitalRead(BDPIN_PUSH_SW_2) == HIGH)\r\n  {\r\n    mode = 1;\r\n  }\r\n}\r\n\r\nvoid drawPallet(void)\r\n{\r\n  uint8_t rgb[3];\r\n  float h;\r\n\r\n  for (int y=0; y<320; y++)\r\n  {\r\n    h = (float)y / 320.;\r\n    hslToRgb(h, 0.5, 0.5, rgb);\r\n    Tft.lcd_draw_line(0, 319-y, 240-1, 319-y, color565(rgb[0], rgb[1], rgb[2]));    \r\n  }  \r\n  Tft.drawFrame();  \r\n}\r\n\r\nvoid drawPalletBar(void)\r\n{\r\n  uint8_t rgb[3];\r\n  float h;\r\n\r\n  for (int x=0; x<240; x++)\r\n  {\r\n    h = (float)x / 240.;\r\n    hslToRgb(h, 0.5, 0.5, rgb);\r\n    Tft.lcd_draw_line(x, 319-10, x, 319, color565(rgb[0], rgb[1], rgb[2]));    \r\n  }  \r\n}\r\n\r\n\r\n// Pass 8-bit (each) R,G,B, get back 16-bit packed color\r\nuint16_t color565(uint8_t r, uint8_t g, uint8_t b) \r\n{\r\n  return ((r & 0xF8) << 8) | ((g & 0xFC) << 3) | (b >> 3);\r\n}\r\n/**\r\n* Adapted from http://stackoverflow.com/questions/2353211/hsl-to-rgb-color-conversion\r\n* Converts an HSL color value to RGB. Conversion formula\r\n * adapted from http://en.wikipedia.org/wiki/HSL_color_space.\r\n* Assumes h, s, and l are contained in the set [0, 1] and\r\n* returns r, g, and b in the set [0, 255].\r\n*\r\n* @param   Number  h       The hue\r\n* @param   Number  s       The saturation\r\n* @param   Number  l       The lightness\r\n* @return  Array           The RGB representation\r\n*/\r\nvoid hslToRgb(float h, float s, float l, byte * rgbIn) {\r\n  float r, g, b;\r\n\r\n  if (s == 0) {\r\n    r = g = b = l; // achromatic\r\n  } else {\r\n    float q = l < 0.5 ? l * (1 + s) : l + s - l * s;\r\n    float p = 2 * l - q;\r\n    r = hue2rgb(p, q, h + 1.0 / 3);\r\n    g = hue2rgb(p, q, h);\r\n    b = hue2rgb(p, q, h - 1.0 / 3);\r\n  }\r\n  rgbIn[0] = min(r * 255, 255);\r\n  rgbIn[1] = min(g * 255, 255);\r\n  rgbIn[2] = min(b * 255, 255);\r\n}\r\n\r\nfloat hue2rgb (float p, float q, float t) {\r\n  if (t < 0) t += 1;\r\n  if (t > 1) t -= 1;\r\n  if (t < 1.0 / 6) return p + (q - p) * 6 * t;\r\n  if (t < 1.0 / 2) return q;\r\n  if (t < 2.0 / 3) return p + (q - p) * (2.0 / 3 - t) * 6;\r\n  return p;\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/LDS/drawLDS/lds.cpp",
    "content": "#include \"lds.h\"\n\n\n\n#define LDS_PACKET_FIND_HEADER      0\n#define LDS_PACKET_PARSING          1\n\n\n\n\n\n\nvoid ldsInit(lds_scan_t *p_scan)\n{\n  uint32_t i;\n\n\n  p_scan->angle_min = 0.0;\n  p_scan->angle_max = 2.0*M_PI;\n  p_scan->angle_increment = (2.0*M_PI/360.0);\n  p_scan->range_min = 0.12;\n  p_scan->range_max = 3.5;\n\n  p_scan->state = LDS_PACKET_FIND_HEADER;\n  p_scan->index = 0;\n  p_scan->packet_index = 0;\n  p_scan->motor_speed = 0;\n  p_scan->scan_time = 0;\n\n  for (i=0; i<360; i++)\n  {\n    p_scan->data[i].range = 0;\n    p_scan->data[i].intensity = 0;\n  }\n\n  p_scan->buffer_index = 0;\n  for (i=0; i<42; i++)\n  {\n    p_scan->buffer[i] = 0;\n  }\n}\n\nbool ldsUpdate(lds_scan_t *p_scan, uint8_t data_in)\n{\n  static uint32_t pre_time = 0;\n  static uint32_t pre_scan_time = 0;\n  bool ret = false;\n\n  // time out : 1000ms\n  if (millis()-pre_time >= 1000)\n  {\n    pre_time = millis();\n    p_scan->state = LDS_PACKET_FIND_HEADER;\n    p_scan->index = 0;\n    p_scan->buffer_index = 0;\n    p_scan->packet_index = 0;\n    p_scan->buffer[0] = 0;\n    p_scan->buffer[1] = 0;\n  }\n\n  switch(p_scan->state)\n  {\n    case LDS_PACKET_FIND_HEADER:    \n      if (p_scan->buffer_index >= 1)\n      {\n        p_scan->buffer[1] = data_in;\n\n        if(    p_scan->buffer[0] == 0xFA\n            && p_scan->buffer[1] == (0xA0 + p_scan->packet_index))\n        {\n          p_scan->index = p_scan->packet_index * 6;\n          p_scan->buffer_index++;\n          p_scan->state = LDS_PACKET_PARSING;\n          if (p_scan->buffer[1] == 0xA0)\n          {\n            p_scan->motor_speed_sum = 0;\n            p_scan->scan_time = millis() - pre_scan_time;\n            pre_scan_time = millis();\n          }\n        }\n        else\n        {\n          p_scan->buffer[0] = p_scan->buffer[1];\n          p_scan->buffer[1] = 0;\n        }        \n      }\n      else\n      {\n        p_scan->buffer[p_scan->buffer_index] = data_in;\n        p_scan->buffer_index++;\n      }\n      break;\n\n    case LDS_PACKET_PARSING:\n      p_scan->buffer[p_scan->buffer_index++] = data_in;\n\n      if (p_scan->buffer_index >= 42)\n      {\n        p_scan->motor_speed_sum += (p_scan->buffer[3]<<8) | p_scan->buffer[2];\n\n        for (uint16_t i=0; i<6; i++)\n        {\n          uint16_t index;\n          uint8_t  *p_data;\n\n          index  = 359 - (p_scan->index + i); \n          p_data = &p_scan->buffer[4 + 6*i];\n          p_scan->data[index].intensity = (p_data[1]<<8) | p_data[0];\n          p_scan->data[index].range     = (p_data[3]<<8) | p_data[2];\n          p_scan->data[index].reserved  = (p_data[5]<<8) | p_data[4];\n        }\n\n        if (p_scan->packet_index == 60-1)\n        {\n          p_scan->motor_speed = p_scan->motor_speed_sum / 60; \n          ret = true;\n        }\n        p_scan->packet_index = (p_scan->packet_index + 1) % 60;\n        p_scan->state = LDS_PACKET_FIND_HEADER;\n        p_scan->buffer_index = 0;\n        p_scan->buffer[0] = 0;\n        p_scan->buffer[1] = 0;\n      }\n      break;    \n  }\n\n\n  return ret;\n}\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/LDS/drawLDS/lds.h",
    "content": "#ifndef _LDS_H_\n#define _LDS_H_\n\n\n#include <Arduino.h>\n\n\ntypedef struct\n{\n  uint16_t range;\n  uint16_t intensity;\n  uint16_t reserved;\n} lds_packet_t;\n\n\ntypedef struct\n{\n  uint8_t state;\n  uint8_t buffer_index;\n  uint8_t buffer[42];\n  uint16_t index;\n  uint16_t packet_index;\n  uint32_t motor_speed;\n  uint32_t motor_speed_sum;\n  uint32_t scan_time;\n  \n  float angle_min;\n  float angle_max;\n  float angle_increment;\n  float range_min;\n  float range_max;\n\n  lds_packet_t data[360];\n} lds_scan_t;\n\n\n\n\nvoid ldsInit(lds_scan_t *p_scan);\nbool ldsUpdate(lds_scan_t *p_scan, uint8_t data_in);\n\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/SPI/using_SPI_ports/using_SPI_ports.ino",
    "content": "/*\r\n * SPI Examble\r\n */\r\n\r\n\r\n\r\n#include <SPI.h>\r\n\r\n\r\n#define SPI_NSS_PIN  10\r\n\r\n\r\n\r\nvoid setup() {\r\n\r\n  SPI.begin();                          // Initialize the SPI port.\r\n  SPI.setBitOrder(MSBFIRST);            // Set the SPI bit order\r\n  SPI.setDataMode(SPI_MODE0);           //Set the  SPI data mode 0\r\n  SPI.setClockDivider(SPI_CLOCK_DIV16); // Slow speed (108 / 16 = 6.75 MHz SPI speed)\r\n  pinMode(SPI_NSS_PIN, OUTPUT);\r\n}\r\n\r\nvoid loop() {\r\n\r\n  sendSPI();\r\n\r\n  delayMicroseconds(10);\r\n}\r\n\r\nvoid sendSPI()\r\n{\r\n  digitalWrite(SPI_NSS_PIN, LOW);\r\n  SPI.transfer(0x55);\r\n  digitalWrite(SPI_NSS_PIN, HIGH);\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/Servo/Knob/Knob.ino",
    "content": "/*\n Controlling a servo position using a potentiometer (variable resistor)\n by Michal Rinott <http://people.interaction-ivrea.it/m.rinott>\n\n modified on 8 Nov 2013\n by Scott Fitzgerald\n http://www.arduino.cc/en/Tutorial/Knob\n*/\n\n#include <Servo.h>\n\nServo myservo;  // create servo object to control a servo\n\nint potpin = 0;  // analog pin used to connect the potentiometer\nint val;    // variable to read the value from the analog pin\n\nvoid setup() {\n  myservo.attach(9);  // attaches the servo on pin 9 to the servo object\n}\n\nvoid loop() {\n  val = analogRead(potpin);            // reads the value of the potentiometer (value between 0 and 1023)\n  val = map(val, 0, 1023, 0, 180);     // scale it to use it with the servo (value between 0 and 180)\n  myservo.write(val);                  // sets the servo position according to the scaled value\n  delay(15);                           // waits for the servo to get there\n}\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/Servo/Sweep/Sweep.ino",
    "content": "/* Sweep\n by BARRAGAN <http://barraganstudio.com>\n This example code is in the public domain.\n\n modified 8 Nov 2013\n by Scott Fitzgerald\n http://www.arduino.cc/en/Tutorial/Sweep\n*/\n\n#include <Servo.h>\n\nServo myservo;  // create servo object to control a servo\n// twelve servo objects can be created on most boards\n\nint pos = 0;    // variable to store the servo position\n\nvoid setup() {\n  myservo.attach(9);  // attaches the servo on pin 9 to the servo object\n}\n\nvoid loop() {\n  for (pos = 0; pos <= 180; pos += 1) { // goes from 0 degrees to 180 degrees\n    // in steps of 1 degree\n    myservo.write(pos);              // tell servo to go to position in variable 'pos'\n    delay(15);                       // waits 15ms for the servo to reach the position\n  }\n  for (pos = 180; pos >= 0; pos -= 1) { // goes from 180 degrees to 0 degrees\n    myservo.write(pos);              // tell servo to go to position in variable 'pos'\n    delay(15);                       // waits 15ms for the servo to reach the position\n  }\n}\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/TFT/tft_shape/tft_shape/tft_shape.ino",
    "content": "#include <LcdTouchPanel.h>\r\n\r\n\r\nvoid drawShape(shape_list shape, uint16_t x_pos, uint16_t y_pos, uint16_t radius, uint16_t color){\r\n  switch(shape)\r\n  {\r\n    case CIRCLE:\r\n     Tft.lcd_draw_circle(x_pos, y_pos, radius, color);\r\n     break;\r\n     \r\n    case SQUARE:\r\n     Tft.lcd_fill_rect(x_pos, y_pos, radius, radius, color);\r\n     break;\r\n  }\r\n}\r\n\r\nvoid drawFrame(){\r\n  Tft.drawFrame();\r\n}\r\n\r\n////////////////////////////////////\r\nvoid setup() {\r\n  // put your setup code here, to run once:\r\n  Serial.begin(115200);\r\n  tftInit();\r\n\r\n}\r\n\r\nvoid loop() {\r\n  static uint32_t pre_time;\r\n\r\n  if(millis() - pre_time >= 50)\r\n  {\r\n    drawShape(CIRCLE, 120, 80, 50, RED);\r\n    drawShape(SQUARE, 120, 160, 50, RED);\r\n    drawFrame();\r\n  }\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/TFT/tft_text/tft_text/tft_text.ino",
    "content": "#include <LcdTouchPanel.h>\n\nvoid drawText(uint16_t x_pos, uint16_t y_pos, const uint8_t *string, uint8_t ch_size, uint16_t color){\n  Tft.lcd_display_string(x_pos, y_pos, string, ch_size, color) ;\n}\nvoid drawFrame(){\n  Tft.drawFrame();\n}\n\n////////////////////////////////////\nvoid setup() {\n  // put your setup code here, to run once:\n  Serial.begin(115200);\n  tftInit();\n}\n\nvoid loop() {\n  static uint32_t pre_time;\n\n  if(millis() - pre_time >= 50)\n  {\n    drawText(40,40, (const uint8_t *)\"Hello, World!!!\",16, RED);\n    drawFrame();\n  }\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/TFT/tft_touch/tft_touch/tft_touch.ino",
    "content": "//Before, running this project. you have to know that the coordinate of LCD and Touch is different. \n//The relationship between LCD and touch is,\n//LCD   x : 0 ~ 240,    y : 0 ~ 320   (origin : when you set the OpenCR direction with the usb port facing downside, left-upper point is (0,0))\n//Touch x : 1950 ~ 127, y : 1950 ~ 127\n//So, I'am gonna support you by using convCoordinateTouch2LCD function\n\n#include <LcdTouchPanel.h>\n\nuint16_t lcd_list[2];\nuint16_t* convCoordinateTouch2LCD(uint16_t* touch_list)\n{\n   lcd_list[XPOS] = LCD_MAX_X*(TOUCH_MAX-touch_list[XPOS])/TOUCH_RANGE;\n   lcd_list[YPOS] = LCD_MAX_Y*(TOUCH_MAX-touch_list[YPOS])/TOUCH_RANGE;\n   return lcd_list;\n}\n\n\nvoid drawText(uint16_t x_pos, uint16_t y_pos, const uint8_t *string, uint8_t ch_size, uint16_t color)\n{\n  Tft.lcd_display_string(x_pos, y_pos, string, ch_size, color) ;\n}\n\nvoid drawTouch(uint16_t x_pos, uint16_t y_pos, uint16_t color)\n{\n  Tft.lcd_draw_circle(x_pos, y_pos, 5, color);\n}\n\nvoid drawFrame()\n{\n  Tft.drawFrame();\n}\n\n////////////////////////////////////\nuint16_t touch_pos[2];\n\n\nvoid setup()\n{\n  // put your setup code here, to run once:\n  Serial.begin(115200);\n  tftInit();    \n}\n\nvoid loop()\n{\n  // put your main code here, to run repeatedly:\n  static uint32_t pre_time;\n  uint16_t *lcd_pos;\n \n  getSingleTouchPoint(touch_pos);\n  lcd_pos = convCoordinateTouch2LCD(touch_pos);\n\n  if(millis() - pre_time >= 50)\n  {\n    pre_time = millis();\n    Serial.print(\"touch : \");\n    Serial.print(touch_pos[XPOS]);\n    Serial.print(\" , \");\n    Serial.println(touch_pos[YPOS]);\n    Serial.print(\"lcd : \");\n    Serial.print(lcd_pos[XPOS]);\n    Serial.print(\" , \");\n    Serial.println(lcd_pos[YPOS]);\n    Serial.println();\n\n    drawText(40,40, (const uint8_t *)\"Touch The Screen !!\",16, RED);\n    drawTouch(lcd_pos[XPOS], lcd_pos[YPOS], RED);\n    drawFrame();\n  }\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/Waveshare/breakouttouchpaint/breakouttouchpaint.ino",
    "content": "/***************************************************\n  This is our touchscreen painting example for the Adafruit HX8357 Breakout\n  ----> http://www.adafruit.com/products/2050\n\n  Check out the links above for our tutorials and wiring diagrams\n  These displays use SPI to communicate, 4 or 5 pins are required to\n  interface (RST is optional)\n  Adafruit invests time and resources providing this open source code,\n  please support Adafruit and open-source hardware by purchasing\n  products from Adafruit!\n\n  Written by Limor Fried/Ladyada for Adafruit Industries.\n  MIT license, all text above must be included in any redistribution\n ****************************************************/\n\n/** NOT FOR USE WITH THE TOUCH SHIELD, ONLY FOR THE 3.5\" BREAKOUT! **/\n\n#include <Adafruit_GFX.h>    // Core graphics library\n#include <SPI.h>\n#include \"Adafruit_HX8357.h\"\n#include \"TouchScreen.h\"\n\n// These are the four touchscreen analog pins\n#define YP A2  // must be an analog pin, use \"An\" notation!\n#define XM A3  // must be an analog pin, use \"An\" notation!\n#define YM 7   // can be a digital pin\n#define XP 8   // can be a digital pin\n\n// This is calibration data for the raw touch data to the screen coordinates\n#define TS_MINX 110\n#define TS_MINY 80\n#define TS_MAXX 900\n#define TS_MAXY 940\n\n#define MINPRESSURE 10\n#define MAXPRESSURE 1000\n\n// The display uses hardware SPI, plus #9 & #10\n#define TFT_RST -1  // dont use a reset pin, tie to arduino RST if you like\n#define TFT_DC 9\n#define TFT_CS 10\n\nAdafruit_HX8357 tft = Adafruit_HX8357(TFT_CS, TFT_DC, TFT_RST);\n\n// For better pressure precision, we need to know the resistance\n// between X+ and X- Use any multimeter to read it\n// For the one we're using, its 300 ohms across the X plate\nTouchScreen ts = TouchScreen(XP, YP, XM, YM, 300);\n\n// Size of the color selection boxes and the paintbrush size\n#define BOXSIZE 40\n#define PENRADIUS 3\nint oldcolor, currentcolor;\n\nvoid setup(void) {\n  while (!Serial);     // used for leonardo debugging\n \n  Serial.begin(115200);\n  Serial.println(F(\"Touch Paint!\"));\n  \n  tft.begin(HX8357D);\n  tft.fillScreen(HX8357_BLACK);\n  \n  // make the color selection boxes\n  tft.fillRect(0, 0, BOXSIZE, BOXSIZE, HX8357_RED);\n  tft.fillRect(BOXSIZE, 0, BOXSIZE, BOXSIZE, HX8357_YELLOW);\n  tft.fillRect(BOXSIZE*2, 0, BOXSIZE, BOXSIZE, HX8357_GREEN);\n  tft.fillRect(BOXSIZE*3, 0, BOXSIZE, BOXSIZE, HX8357_CYAN);\n  tft.fillRect(BOXSIZE*4, 0, BOXSIZE, BOXSIZE, HX8357_BLUE);\n  tft.fillRect(BOXSIZE*5, 0, BOXSIZE, BOXSIZE, HX8357_MAGENTA);\n  tft.fillRect(BOXSIZE*6, 0, BOXSIZE, BOXSIZE, HX8357_BLACK);\n  tft.fillRect(BOXSIZE*6, 0, BOXSIZE, BOXSIZE, HX8357_WHITE);\n \n  // select the current color 'red'\n  tft.drawRect(0, 0, BOXSIZE, BOXSIZE, HX8357_WHITE);\n  currentcolor = HX8357_RED;\n}\n\n\nvoid loop()\n{\n  // Retrieve a point  \n  TSPoint p = ts.getPoint();\n \n  // we have some minimum pressure we consider 'valid'\n  // pressure of 0 means no pressing!\n  if (p.z < MINPRESSURE || p.z > MAXPRESSURE) {\n     return;\n  }\n\n  Serial.print(\"X = \"); Serial.print(p.x);\n  Serial.print(\"\\tY = \"); Serial.print(p.y);\n  Serial.print(\"\\tPressure = \"); Serial.println(p.z);  \n   \n  // Scale from ~0->1000 to tft.width using the calibration #'s\n  p.x = map(p.x, TS_MINX, TS_MAXX, 0, tft.width());\n  p.y = map(p.y, TS_MINY, TS_MAXY, 0, tft.height());\n\n\n  /*\n  Serial.print(\"(\"); Serial.print(p.x);\n  Serial.print(\", \"); Serial.print(p.y);\n  Serial.println(\")\");\n*/\n    \n  if (p.y < BOXSIZE) {\n     oldcolor = currentcolor;\n\n     if (p.x < BOXSIZE) { \n       currentcolor = HX8357_RED; \n       tft.drawRect(0, 0, BOXSIZE, BOXSIZE, HX8357_WHITE);\n     } else if (p.x < BOXSIZE*2) {\n       currentcolor = HX8357_YELLOW;\n       tft.drawRect(BOXSIZE, 0, BOXSIZE, BOXSIZE, HX8357_WHITE);\n     } else if (p.x < BOXSIZE*3) {\n       currentcolor = HX8357_GREEN;\n       tft.drawRect(BOXSIZE*2, 0, BOXSIZE, BOXSIZE, HX8357_WHITE);\n     } else if (p.x < BOXSIZE*4) {\n       currentcolor = HX8357_CYAN;\n       tft.drawRect(BOXSIZE*3, 0, BOXSIZE, BOXSIZE, HX8357_WHITE);\n     } else if (p.x < BOXSIZE*5) {\n       currentcolor = HX8357_BLUE;\n       tft.drawRect(BOXSIZE*4, 0, BOXSIZE, BOXSIZE, HX8357_WHITE);\n     } else if (p.x < BOXSIZE*6) {\n       currentcolor = HX8357_MAGENTA;\n       tft.drawRect(BOXSIZE*5, 0, BOXSIZE, BOXSIZE, HX8357_WHITE);\n     } else if (p.x < BOXSIZE*7) {\n       currentcolor = HX8357_WHITE;\n       tft.drawRect(BOXSIZE*6, 0, BOXSIZE, BOXSIZE, HX8357_RED);\n     } else if (p.x < BOXSIZE*8) {\n       currentcolor = HX8357_BLACK;\n       tft.drawRect(BOXSIZE*7, 0, BOXSIZE, BOXSIZE, HX8357_WHITE);\n     }\n\n     if (oldcolor != currentcolor) {\n        if (oldcolor == HX8357_RED) \n          tft.fillRect(0, 0, BOXSIZE, BOXSIZE, HX8357_RED);\n        if (oldcolor == HX8357_YELLOW) \n          tft.fillRect(BOXSIZE, 0, BOXSIZE, BOXSIZE, HX8357_YELLOW);\n        if (oldcolor == HX8357_GREEN) \n          tft.fillRect(BOXSIZE*2, 0, BOXSIZE, BOXSIZE, HX8357_GREEN);\n        if (oldcolor == HX8357_CYAN) \n          tft.fillRect(BOXSIZE*3, 0, BOXSIZE, BOXSIZE, HX8357_CYAN);\n        if (oldcolor == HX8357_BLUE) \n          tft.fillRect(BOXSIZE*4, 0, BOXSIZE, BOXSIZE, HX8357_BLUE);\n        if (oldcolor == HX8357_MAGENTA) \n          tft.fillRect(BOXSIZE*5, 0, BOXSIZE, BOXSIZE, HX8357_MAGENTA);\n        if (oldcolor == HX8357_WHITE) \n          tft.fillRect(BOXSIZE*6, 0, BOXSIZE, BOXSIZE, HX8357_WHITE);\n        if (oldcolor == HX8357_BLACK) \n          tft.fillRect(BOXSIZE*7, 0, BOXSIZE, BOXSIZE, HX8357_BLACK);\n     }\n  }\n  if (((p.y-PENRADIUS) > BOXSIZE) && ((p.y+PENRADIUS) < tft.height())) {\n    tft.fillCircle(p.x, p.y, PENRADIUS, currentcolor);\n  }\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/Waveshare/graphicstest/graphicstest.ino",
    "content": "/***************************************************\n  This is our library for the Adafruit HX8357D Breakout\n  ----> http://www.adafruit.com/products/2050\n\n  Check out the links above for our tutorials and wiring diagrams\n  These displays use SPI to communicate, 4 or 5 pins are required to\n  interface (RST is optional)\n  Adafruit invests time and resources providing this open source code,\n  please support Adafruit and open-source hardware by purchasing\n  products from Adafruit!\n\n  Written by Limor Fried/Ladyada for Adafruit Industries.\n  MIT license, all text above must be included in any redistribution\n ****************************************************/\n\n#include <SPI.h>\n#include \"Adafruit_GFX.h\"\n#include \"Waveshare_HX8347D.h\"\n\n\n\n\nWaveshare_HX8347D tft = Waveshare_HX8347D();\n\n\n\n\nvoid setup() {\n  uint32_t t_time;\n\n  Serial.begin(9600);\n  while(!Serial);\n  Serial.println(\"HX8347D Test!\");\n\n  tft.begin();\n\n\n\n  Serial.println(F(\"Benchmark                Time (microseconds)\"));\n\n  tft.setRotation(1);\n\n  t_time = micros();\n  tft.fillScreen(HX8347D_RED);\n  tft.drawFrame();\n  Serial.println(micros()-t_time);\n\n\n  delay(500);\n  tft.fillScreen(HX8347D_GREEN);\n  tft.drawFrame();\n  delay(500);\n  tft.fillScreen(HX8347D_BLUE);\n  tft.drawFrame();\n  delay(500);\n  tft.fillScreen(HX8347D_BLACK);\n  tft.drawFrame();\n  delay(500);\n\n\n  Serial.print(F(\"Text                     \"));\n  Serial.println(testText());\n  delay(500);\n\n  Serial.print(F(\"Lines                    \"));\n  Serial.println(testLines(HX8347D_CYAN));\n  delay(500);\n\n  Serial.print(F(\"Rectangles (outline)     \"));\n  Serial.println(testRects(HX8347D_GREEN));\n  delay(500);\n\n  tft.fillScreen(HX8347D_BLACK);\n  Serial.print(F(\"Circles (outline)        \"));\n  Serial.println(testCircles(10, HX8347D_RED));\n  delay(500);\n\n\n  Serial.print(F(\"Triangles (outline)      \"));\n  Serial.println(testTriangles());\n  delay(500);\n\n  Serial.print(F(\"Triangles (filled)       \"));\n  Serial.println(testFilledTriangles());\n  delay(500);\n\n\n  Serial.print(F(\"Rounded rects (outline)  \"));\n  Serial.println(testRoundRects());\n  delay(500);\n\n  Serial.print(F(\"Rounded rects (filled)   \"));\n  Serial.println(testFilledRoundRects());\n  delay(500);\n\n  Serial.println(F(\"Done!\"));\n}\n\n\nvoid loop(void) {\n  for(uint8_t rotation=0; rotation<4; rotation++) {\n    tft.setRotation(rotation);\n    testText();\n    delay(1000);\n  }\n}\n\nunsigned long testFillScreen() {\n  unsigned long start = micros();\n  tft.fillScreen(HX8347D_RED);\n  tft.drawFrame();\n  tft.fillScreen(HX8347D_GREEN);\n  tft.drawFrame();\n  tft.fillScreen(HX8347D_BLUE);\n  tft.drawFrame();\n  tft.fillScreen(HX8347D_WHITE);\n  tft.drawFrame();\n  return micros() - start;\n}\n\n\nunsigned long testText() {\n  tft.fillScreen(HX8347D_BLACK);\n  unsigned long start = micros();\n  tft.setCursor(0, 0);\n  tft.setTextColor(HX8347D_WHITE);  tft.setTextSize(1);\n  tft.println(\"Hello World!\");\n  tft.setTextColor(HX8347D_YELLOW); tft.setTextSize(2);\n  tft.println(1234.56);\n  tft.setTextColor(HX8347D_RED);    tft.setTextSize(3);\n  tft.println(0xDEADBEEF, HEX);\n  tft.println();\n  tft.setTextColor(HX8347D_GREEN);\n  tft.setTextSize(5);\n  tft.println(\"Groop\");\n  tft.setTextSize(2);\n  tft.println(\"I implore thee,\");\n  tft.setTextSize(1);\n  tft.println(\"my foonting turlingdromes.\");\n  tft.println(\"And hooptiously drangle me\");\n  tft.println(\"with crinkly bindlewurdles,\");\n  tft.println(\"Or I will rend thee\");\n  tft.println(\"in the gobberwarts\");\n  tft.println(\"with my blurglecruncheon,\");\n  tft.println(\"see if I don't!\");\n\n  tft.setTextColor(HX8347D_WHITE);\n  tft.println(F(\"Alice was beginning to get very tired of sitting by her sister on the bank, and of having nothing to do: once or twice she had peeped into the book her sister was reading, but it had no pictures or conversations in it, 'and what is the use of a book,' thought Alice 'without pictures or conversations?'\"));\n\ntft.println(F(\"So she was considering in her own mind (as well as she could, for the hot day made her feel very sleepy and stupid), whether the pleasure of making a daisy-chain would be worth the trouble of getting up and picking the daisies, when suddenly a White Rabbit with pink eyes ran close by her.\"));\n\ntft.println(F(\"There was nothing so very remarkable in that; nor did Alice think it so very much out of the way to hear the Rabbit say to itself, 'Oh dear! Oh dear! I shall be late!' (when she thought it over afterwards, it occurred to her that she ought to have wondered at this, but at the time it all seemed quite natural); but when the Rabbit actually took a watch out of its waistcoat-pocket, and looked at it, and then hurried on, Alice started to her feet, for it flashed across her mind that she had never before seen a rabbit with either a waistcoat-pocket, or a watch to take out of it, and burning with curiosity, she ran across the field after it, and fortunately was just in time to see it pop down a large rabbit-hole under the hedge.\"));\n\ntft.println(F(\"In another moment down went Alice after it, never once considering how in the world she was to get out again.\"));\n\ntft.println(F(\"The rabbit-hole went straight on like a tunnel for some way, and then dipped suddenly down, so suddenly that Alice had not a moment to think about stopping herself before she found herself falling down a very deep well.\"));\n\ntft.println(F(\"Either the well was very deep, or she fell very slowly, for she had plenty of time as she went down to look about her and to wonder what was going to happen next. First, she tried to look down and make out what she was coming to, but it was too dark to see anything; then she looked at the sides of the well, and noticed that they were filled with cupboards and book-shelves; here and there she saw maps and pictures hung upon pegs. She took down a jar from one of the shelves as she passed; it was labelled 'ORANGE MARMALADE', but to her great disappointment it was empty: she did not like to drop the jar for fear of killing somebody, so managed to put it into one of the cupboards as she fell past it.\"));\n\n  tft.drawFrame();\n  return micros() - start;\n}\n\nunsigned long testLines(uint16_t color) {\n  unsigned long start, t;\n  int           x1, y1, x2, y2,\n                w = tft.width(),\n                h = tft.height();\n\n  tft.fillScreen(HX8347D_BLACK);\n\n  x1 = y1 = 0;\n  y2    = h - 1;\n  start = micros();\n  for(x2=0; x2<w; x2+=6) tft.drawLine(x1, y1, x2, y2, color);\n  x2    = w - 1;\n  for(y2=0; y2<h; y2+=6) tft.drawLine(x1, y1, x2, y2, color);\n  t     = micros() - start; // fillScreen doesn't count against timing\n\n\n  tft.drawFrame();\n  return micros() - start;\n}\n\nunsigned long testFastLines(uint16_t color1, uint16_t color2) {\n  unsigned long start;\n  int           x, y, w = tft.width(), h = tft.height();\n\n  tft.fillScreen(HX8347D_BLACK);\n  start = micros();\n  for(y=0; y<h; y+=5) tft.drawFastHLine(0, y, w, color1);\n  for(x=0; x<w; x+=5) tft.drawFastVLine(x, 0, h, color2);\n\n  tft.drawFrame();\n  return micros() - start;\n}\n\nunsigned long testRects(uint16_t color) {\n  unsigned long start;\n  int           n, i, i2,\n                cx = tft.width()  / 2,\n                cy = tft.height() / 2;\n\n  tft.fillScreen(HX8347D_BLACK);\n  n     = min(tft.width(), tft.height());\n  start = micros();\n  for(i=2; i<n; i+=6) {\n    i2 = i / 2;\n    tft.drawRect(cx-i2, cy-i2, i, i, color);\n  }\n\n  tft.drawFrame();\n  return micros() - start;\n}\n\nunsigned long testFilledRects(uint16_t color1, uint16_t color2) {\n  unsigned long start, t = 0;\n  int           n, i, i2,\n                cx = tft.width()  / 2 - 1,\n                cy = tft.height() / 2 - 1;\n\n  tft.fillScreen(HX8347D_BLACK);\n  n = min(tft.width(), tft.height());\n  for(i=n; i>0; i-=6) {\n    i2    = i / 2;\n    start = micros();\n    tft.fillRect(cx-i2, cy-i2, i, i, color1);\n    t    += micros() - start;\n    // Outlines are not included in timing results\n    tft.drawRect(cx-i2, cy-i2, i, i, color2);\n  }\n\n  tft.drawFrame();\n  return t;\n}\n\nunsigned long testFilledCircles(uint8_t radius, uint16_t color) {\n  unsigned long start;\n  int x, y, w = tft.width(), h = tft.height(), r2 = radius * 2;\n\n  tft.fillScreen(HX8347D_BLACK);\n  start = micros();\n  for(x=radius; x<w; x+=r2) {\n    for(y=radius; y<h; y+=r2) {\n      tft.fillCircle(x, y, radius, color);\n    }\n  }\n\n  tft.drawFrame();\n  return micros() - start;\n}\n\nunsigned long testCircles(uint8_t radius, uint16_t color) {\n  unsigned long start;\n  int           x, y, r2 = radius * 2,\n                w = tft.width()  + radius,\n                h = tft.height() + radius;\n\n  // Screen is not cleared for this one -- this is\n  // intentional and does not affect the reported time.\n  start = micros();\n  for(x=0; x<w; x+=r2) {\n    for(y=0; y<h; y+=r2) {\n      tft.drawCircle(x, y, radius, color);\n    }\n  }\n\n  tft.drawFrame();\n  return micros() - start;\n}\n\nunsigned long testTriangles() {\n  unsigned long start;\n  int           n, i, cx = tft.width()  / 2 - 1,\n                      cy = tft.height() / 2 - 1;\n\n  tft.fillScreen(HX8347D_BLACK);\n  n     = min(cx, cy);\n  start = micros();\n  for(i=0; i<n; i+=5) {\n    tft.drawTriangle(\n      cx    , cy - i, // peak\n      cx - i, cy + i, // bottom left\n      cx + i, cy + i, // bottom right\n      tft.color565(200, 20, i));\n  }\n\n  tft.drawFrame();\n  return micros() - start;\n}\n\nunsigned long testFilledTriangles() {\n  unsigned long start, t = 0;\n  int           i, cx = tft.width()  / 2 - 1,\n                   cy = tft.height() / 2 - 1;\n\n  tft.fillScreen(HX8347D_BLACK);\n  start = micros();\n  for(i=min(cx,cy); i>10; i-=5) {\n    start = micros();\n    tft.fillTriangle(cx, cy - i, cx - i, cy + i, cx + i, cy + i,\n      tft.color565(0, i, i));\n    t += micros() - start;\n    tft.drawTriangle(cx, cy - i, cx - i, cy + i, cx + i, cy + i,\n      tft.color565(i, i, 0));\n  }\n\n  tft.drawFrame();\n  return t;\n}\n\nunsigned long testRoundRects() {\n  unsigned long start;\n  int           w, i, i2,\n                cx = tft.width()  / 2 ,\n                cy = tft.height() / 2 ;\n\n  tft.fillScreen(HX8347D_BLACK);\n  w     = min(tft.width(), tft.height());\n  start = micros();\n  for(i=0; i<w; i+=8) {\n    i2 = i / 2 - 2;\n    tft.drawRoundRect(cx-i2, cy-i2, i, i, i/8, tft.color565(i, 100, 100));\n  }\n\n  tft.drawFrame();\n  return micros() - start;\n}\n\nunsigned long testFilledRoundRects() {\n  unsigned long start;\n  int           i, i2,\n                cx = tft.width()  / 2 + 10,\n                cy = tft.height() / 2 + 10;\n\n  tft.fillScreen(HX8347D_BLACK);\n  start = micros();\n  for(i=min(tft.width(), tft.height()) - 20; i>20; i-=6) {\n    i2 = i / 2;\n    tft.fillRoundRect(cx-i2, cy-i2, i-20, i-20, i/8, tft.color565(100, i/2, 100));\n  }\n\n  tft.drawFrame();\n  return micros() - start;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/Waveshare/lcd_logo/lcd_logo.ino",
    "content": "#include \"logo.h\"\n#include <RTOS.h>\n\nvoid setup(void) \n{\n  Serial.begin(115200);\n  while(!Serial);  \n  logo_drawLogo();  \n\n\n  pinMode(13, OUTPUT);\n}\n\nvoid loop() \n{\n  digitalWrite(13, !digitalRead(13));\n  Serial.println(\"test\");\n  delay(100);\n}\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/Waveshare/lcd_logo/logo.cpp",
    "content": "#include \"Adafruit_GFX.h\"\n#include \"Waveshare_HX8347D.h\"\n#include <SPI.h>\n#include <SD.h>\n#include <RTOS.h>\n\n\n\nWaveshare_HX8347D tft = Waveshare_HX8347D();\n\n#define SD_CS 5\n\n\n\nvoid bmpDraw(char *filename, uint8_t x, uint16_t y);\nuint16_t read16(File &f);\nuint32_t read32(File &f);\n\n\n\n\nvoid logo_drawLogo(void) \n{  \n  tft.begin();\n  tft.setRotation(1);\n  \n  tft.setLedPower(0);\n  tft.fillScreen(HX8347D_WHITE);  \n  \n  \n  \n  Serial.print(\"Initializing SD card...\");\n  if (!SD.begin(SD_CS)) {\n    Serial.println(\"failed!\");\n  }\n  Serial.println(\"OK!\");\n  \n\n  bmpDraw(\"logot.bmp\", 0, 0);\n\n  //pinMode(13, OUTPUT);\n\n  for( int i=0; i<=100; i++ )\n  {\n    tft.setLedPower(i);\n    delay(10);\n  }\n}\n\n\n// This function opens a Windows Bitmap (BMP) file and\n// displays it at the given coordinates.  It's sped up\n// by reading many pixels worth of data at a time\n// (rather than pixel by pixel).  Increasing the buffer\n// size takes more of the Arduino's precious RAM but\n// makes loading a little faster.  20 pixels seems a\n// good balance.\n\n#define BUFFPIXEL 20\n\nvoid bmpDraw(char *filename, uint8_t x, uint16_t y) {\n\n  File     bmpFile;\n  int      bmpWidth, bmpHeight;   // W+H in pixels\n  uint8_t  bmpDepth;              // Bit depth (currently must be 24)\n  uint32_t bmpImageoffset;        // Start of image data in file\n  uint32_t rowSize;               // Not always = bmpWidth; may have padding\n  uint8_t  sdbuffer[3*BUFFPIXEL]; // pixel buffer (R+G+B per pixel)\n  uint8_t  buffidx = sizeof(sdbuffer); // Current position in sdbuffer\n  boolean  goodBmp = false;       // Set to true on valid header parse\n  boolean  flip    = true;        // BMP is stored bottom-to-top\n  int      w, h, row, col;\n  uint8_t  r, g, b;\n  uint32_t pos = 0, startTime = millis();\n\n  if((x >= tft.width()) || (y >= tft.height())) return;\n\n  Serial.println();\n  Serial.print(F(\"Loading image '\"));\n  Serial.print(filename);\n  Serial.println('\\'');\n\n  // Open requested file on SD card\n  if ((bmpFile = SD.open(filename)) == NULL) {\n    Serial.print(F(\"File not found\"));\n    return;\n  }\n\n  // Parse BMP header\n  if(read16(bmpFile) == 0x4D42) { // BMP signature\n    Serial.print(F(\"File size: \")); Serial.println(read32(bmpFile));\n    (void)read32(bmpFile); // Read & ignore creator bytes\n    bmpImageoffset = read32(bmpFile); // Start of image data\n    Serial.print(F(\"Image Offset: \")); Serial.println(bmpImageoffset, DEC);\n    // Read DIB header\n    Serial.print(F(\"Header size: \")); Serial.println(read32(bmpFile));\n    bmpWidth  = read32(bmpFile);\n    bmpHeight = read32(bmpFile);\n\n    x += (tft.width()-bmpWidth)/2;\n    y += (tft.height()-bmpHeight)/2;\n    \n    if(read16(bmpFile) == 1) { // # planes -- must be '1'\n      bmpDepth = read16(bmpFile); // bits per pixel\n      Serial.print(F(\"Bit Depth: \")); Serial.println(bmpDepth);\n      if((bmpDepth == 24) && (read32(bmpFile) == 0)) { // 0 = uncompressed\n\n        goodBmp = true; // Supported BMP format -- proceed!\n        Serial.print(F(\"Image size: \"));\n        Serial.print(bmpWidth);\n        Serial.print('x');\n        Serial.println(bmpHeight);\n\n        // BMP rows are padded (if needed) to 4-byte boundary\n        rowSize = (bmpWidth * 3 + 3) & ~3;\n\n        // If bmpHeight is negative, image is in top-down order.\n        // This is not canon but has been observed in the wild.\n        if(bmpHeight < 0) {\n          bmpHeight = -bmpHeight;\n          flip      = false;\n        }\n\n        // Crop area to be loaded\n        w = bmpWidth;\n        h = bmpHeight;\n        if((x+w-1) >= tft.width())  w = tft.width()  - x;\n        if((y+h-1) >= tft.height()) h = tft.height() - y;\n\n        // Set TFT address window to clipped image bounds\n        tft.setAddrWindow(x, y, x+w-1, y+h-1);\n\n        \n        for (row=0; row<h; row++) { // For each scanline...\n\n          // Seek to start of scan line.  It might seem labor-\n          // intensive to be doing this on every line, but this\n          // method covers a lot of gritty details like cropping\n          // and scanline padding.  Also, the seek only takes\n          // place if the file position actually needs to change\n          // (avoids a lot of cluster math in SD library).\n          if(flip) // Bitmap is stored bottom-to-top order (normal BMP)\n            pos = bmpImageoffset + (bmpHeight - 1 - row) * rowSize; \n          else     // Bitmap is stored top-to-bottom\n            pos = bmpImageoffset + row * rowSize;\n          if(bmpFile.position() != pos) { // Need seek?\n            bmpFile.seek(pos);\n            buffidx = sizeof(sdbuffer); // Force buffer reload\n          }\n\n          for (col=0; col<w; col++) { // For each pixel...\n            // Time to read more pixel data?\n            if (buffidx >= sizeof(sdbuffer)) { // Indeed\n              bmpFile.read(sdbuffer, sizeof(sdbuffer));\n              buffidx = 0; // Set index to beginning\n            }\n\n            // Convert pixel from BMP to TFT format, push to display\n            b = sdbuffer[buffidx++];\n            g = sdbuffer[buffidx++];\n            r = sdbuffer[buffidx++];\n            tft.pushColor(tft.color565(r,g,b));\n          } // end pixel\n        } // end scanline\n        Serial.print(F(\"Loaded in \"));\n        Serial.print(millis() - startTime);\n        Serial.println(\" ms\");\n      } // end goodBmp\n    }\n  }\n\n  bmpFile.close();\n  if(!goodBmp) Serial.println(F(\"BMP format not recognized.\"));\n}\n\n// These read 16- and 32-bit types from the SD card file.\n// BMP data is stored little-endian, Arduino is little-endian too.\n// May need to reverse subscript order if porting elsewhere.\n\nuint16_t read16(File &f) {\n  uint16_t result;\n  ((uint8_t *)&result)[0] = f.read(); // LSB\n  ((uint8_t *)&result)[1] = f.read(); // MSB\n  return result;\n}\n\nuint32_t read32(File &f) {\n  uint32_t result;\n  ((uint8_t *)&result)[0] = f.read(); // LSB\n  ((uint8_t *)&result)[1] = f.read();\n  ((uint8_t *)&result)[2] = f.read();\n  ((uint8_t *)&result)[3] = f.read(); // MSB\n  return result;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/Waveshare/lcd_logo/logo.h",
    "content": "\n\n\n\nvoid logo_drawLogo(void);\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/Waveshare/spitftbitmap/spitftbitmap.ino",
    "content": "/***************************************************\n  This is our Bitmap drawing example for the Adafruit HX8357 Breakout\n  ----> http://www.adafruit.com/products/2050\n\n  Check out the links above for our tutorials and wiring diagrams\n  These displays use SPI to communicate, 4 or 5 pins are required to\n  interface (RST is optional)\n  Adafruit invests time and resources providing this open source code,\n  please support Adafruit and open-source hardware by purchasing\n  products from Adafruit!\n\n  Written by Limor Fried/Ladyada for Adafruit Industries.\n  MIT license, all text above must be included in any redistribution\n ****************************************************/\n\n\n#include <Adafruit_GFX.h>    // Core graphics library\n#include \"Adafruit_HX8357.h\"\n#include <SPI.h>\n#include <SD.h>\n\n// TFT display and SD card will share the hardware SPI interface.\n// Hardware SPI pins are specific to the Arduino board type and\n// cannot be remapped to alternate pins.  For Arduino Uno,\n// Duemilanove, etc., pin 11 = MOSI, pin 12 = MISO, pin 13 = SCK.\n\n#define TFT_DC 9\n#define TFT_CS 10\n// Use hardware SPI (on Uno, #13, #12, #11) and the above for CS/DC\nAdafruit_HX8357 tft = Adafruit_HX8357(TFT_CS, TFT_DC);\n\n#define SD_CS 4\n\nvoid setup(void) {\n  Serial.begin(9600);\n\n  tft.begin(HX8357D);\n  tft.fillScreen(HX8357_BLUE);\n  \n  Serial.print(\"Initializing SD card...\");\n  if (!SD.begin(SD_CS)) {\n    Serial.println(\"failed!\");\n  }\n  Serial.println(\"OK!\");\n\n  bmpDraw(\"jumpers.bmp\", 0, 0);\n}\n\nvoid loop() {\n}\n\n// This function opens a Windows Bitmap (BMP) file and\n// displays it at the given coordinates.  It's sped up\n// by reading many pixels worth of data at a time\n// (rather than pixel by pixel).  Increasing the buffer\n// size takes more of the Arduino's precious RAM but\n// makes loading a little faster.  20 pixels seems a\n// good balance.\n\n#define BUFFPIXEL 20\n\nvoid bmpDraw(char *filename, uint8_t x, uint16_t y) {\n\n  File     bmpFile;\n  int      bmpWidth, bmpHeight;   // W+H in pixels\n  uint8_t  bmpDepth;              // Bit depth (currently must be 24)\n  uint32_t bmpImageoffset;        // Start of image data in file\n  uint32_t rowSize;               // Not always = bmpWidth; may have padding\n  uint8_t  sdbuffer[3*BUFFPIXEL]; // pixel buffer (R+G+B per pixel)\n  uint8_t  buffidx = sizeof(sdbuffer); // Current position in sdbuffer\n  boolean  goodBmp = false;       // Set to true on valid header parse\n  boolean  flip    = true;        // BMP is stored bottom-to-top\n  int      w, h, row, col;\n  uint8_t  r, g, b;\n  uint32_t pos = 0, startTime = millis();\n\n  if((x >= tft.width()) || (y >= tft.height())) return;\n\n  Serial.println();\n  Serial.print(F(\"Loading image '\"));\n  Serial.print(filename);\n  Serial.println('\\'');\n\n  // Open requested file on SD card\n  if ((bmpFile = SD.open(filename)) == NULL) {\n    Serial.print(F(\"File not found\"));\n    return;\n  }\n\n  // Parse BMP header\n  if(read16(bmpFile) == 0x4D42) { // BMP signature\n    Serial.print(F(\"File size: \")); Serial.println(read32(bmpFile));\n    (void)read32(bmpFile); // Read & ignore creator bytes\n    bmpImageoffset = read32(bmpFile); // Start of image data\n    Serial.print(F(\"Image Offset: \")); Serial.println(bmpImageoffset, DEC);\n    // Read DIB header\n    Serial.print(F(\"Header size: \")); Serial.println(read32(bmpFile));\n    bmpWidth  = read32(bmpFile);\n    bmpHeight = read32(bmpFile);\n    if(read16(bmpFile) == 1) { // # planes -- must be '1'\n      bmpDepth = read16(bmpFile); // bits per pixel\n      Serial.print(F(\"Bit Depth: \")); Serial.println(bmpDepth);\n      if((bmpDepth == 24) && (read32(bmpFile) == 0)) { // 0 = uncompressed\n\n        goodBmp = true; // Supported BMP format -- proceed!\n        Serial.print(F(\"Image size: \"));\n        Serial.print(bmpWidth);\n        Serial.print('x');\n        Serial.println(bmpHeight);\n\n        // BMP rows are padded (if needed) to 4-byte boundary\n        rowSize = (bmpWidth * 3 + 3) & ~3;\n\n        // If bmpHeight is negative, image is in top-down order.\n        // This is not canon but has been observed in the wild.\n        if(bmpHeight < 0) {\n          bmpHeight = -bmpHeight;\n          flip      = false;\n        }\n\n        // Crop area to be loaded\n        w = bmpWidth;\n        h = bmpHeight;\n        if((x+w-1) >= tft.width())  w = tft.width()  - x;\n        if((y+h-1) >= tft.height()) h = tft.height() - y;\n\n        // Set TFT address window to clipped image bounds\n        tft.setAddrWindow(x, y, x+w-1, y+h-1);\n\n        for (row=0; row<h; row++) { // For each scanline...\n\n          // Seek to start of scan line.  It might seem labor-\n          // intensive to be doing this on every line, but this\n          // method covers a lot of gritty details like cropping\n          // and scanline padding.  Also, the seek only takes\n          // place if the file position actually needs to change\n          // (avoids a lot of cluster math in SD library).\n          if(flip) // Bitmap is stored bottom-to-top order (normal BMP)\n            pos = bmpImageoffset + (bmpHeight - 1 - row) * rowSize;\n          else     // Bitmap is stored top-to-bottom\n            pos = bmpImageoffset + row * rowSize;\n          if(bmpFile.position() != pos) { // Need seek?\n            bmpFile.seek(pos);\n            buffidx = sizeof(sdbuffer); // Force buffer reload\n          }\n\n          for (col=0; col<w; col++) { // For each pixel...\n            // Time to read more pixel data?\n            if (buffidx >= sizeof(sdbuffer)) { // Indeed\n              bmpFile.read(sdbuffer, sizeof(sdbuffer));\n              buffidx = 0; // Set index to beginning\n            }\n\n            // Convert pixel from BMP to TFT format, push to display\n            b = sdbuffer[buffidx++];\n            g = sdbuffer[buffidx++];\n            r = sdbuffer[buffidx++];\n            tft.pushColor(tft.color565(r,g,b));\n          } // end pixel\n        } // end scanline\n        Serial.print(F(\"Loaded in \"));\n        Serial.print(millis() - startTime);\n        Serial.println(\" ms\");\n      } // end goodBmp\n    }\n  }\n\n  bmpFile.close();\n  if(!goodBmp) Serial.println(F(\"BMP format not recognized.\"));\n}\n\n// These read 16- and 32-bit types from the SD card file.\n// BMP data is stored little-endian, Arduino is little-endian too.\n// May need to reverse subscript order if porting elsewhere.\n\nuint16_t read16(File &f) {\n  uint16_t result;\n  ((uint8_t *)&result)[0] = f.read(); // LSB\n  ((uint8_t *)&result)[1] = f.read(); // MSB\n  return result;\n}\n\nuint32_t read32(File &f) {\n  uint32_t result;\n  ((uint8_t *)&result)[0] = f.read(); // LSB\n  ((uint8_t *)&result)[1] = f.read();\n  ((uint8_t *)&result)[2] = f.read();\n  ((uint8_t *)&result)[3] = f.read(); // MSB\n  return result;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/Waveshare/tft_box/tft_box.ino",
    "content": "/***************************************************\n  This is our library for the Adafruit HX8357D Breakout\n  ----> http://www.adafruit.com/products/2050\n\n  Check out the links above for our tutorials and wiring diagrams\n  These displays use SPI to communicate, 4 or 5 pins are required to\n  interface (RST is optional)\n  Adafruit invests time and resources providing this open source code,\n  please support Adafruit and open-source hardware by purchasing\n  products from Adafruit!\n\n  Written by Limor Fried/Ladyada for Adafruit Industries.\n  MIT license, all text above must be included in any redistribution\n ****************************************************/\n\n#include <SPI.h>\n#include \"Adafruit_GFX.h\"\n#include \"Waveshare_HX8347D.h\"\n\n\n\n\nWaveshare_HX8347D tft = Waveshare_HX8347D();\n\n\n\n\nvoid setup() {\n  uint32_t t_time;\n  \n  Serial.begin(9600);\n\n  tft.begin();\n\n\n  \n\n  tft.setRotation(1);  \n  \n  tft.fillScreen(HX8347D_BLACK);\n}\n\n\nvoid loop(void) {\n  static int x[8], y[8];\n  static int x_dir[8] = {0,};\n  static int x_width[8];\n  static int x_step[8];\n  static int x_color[8];\n\n  uint32_t t_time;\n  int i;\n\n  \n  x_width[0] = 30;  y[0] =       0;  x_step[0] = 1; x_color[0] = HX8347D_RED;\n  x_width[1] = 30;  y[1] =      32;  x_step[1] = 2; x_color[1] = HX8347D_BLUE;\n  x_width[2] = 30;  y[2] = y[1]+32;  x_step[2] = 3; x_color[2] = HX8347D_GREEN;\n  x_width[3] = 30;  y[3] = y[2]+32;  x_step[3] = 4; x_color[3] = HX8347D_CYAN;\n  x_width[4] = 30;  y[4] = y[3]+32;  x_step[4] = 5; x_color[4] = HX8347D_MAGENTA;\n  x_width[5] = 30;  y[5] = y[4]+32;  x_step[5] = 6; x_color[5] = HX8347D_YELLOW;\n  x_width[6] = 30;  y[6] = y[5]+32;  x_step[6] = 7; x_color[6] = HX8347D_WHITE;\n\n\n  t_time = micros();\n\n\n  for(i=0; i<7; i++)\n  {\n    tft.fillRect(x[i], y[i], x_width[i], x_width[i], x_color[i]);    \n  }\n  tft.drawFrame();\n  \n  for(i=0; i<7; i++)\n  {  \n    tft.fillRect(x[i], y[i], x_width[i], x_width[i], HX8347D_BLACK);      \n    \n    if( x_dir[i] == 0 )\n      x[i] += x_step[i];\n    else\n      x[i] -= x_step[i];\n  \n    if(x[i]>240-x_width[i])\n    {\n      x_dir[i] ^= 1;\n      x[i] = 240-x_width[i];\n    }\n  \n    if(x[i]<0)\n    {\n      x_dir[i] ^= 1;\n      x[i] = 0;\n    }\n  }\n  \n  uint32_t process_time;\n\n  process_time = micros() - t_time;\n\n\n  tft.setCursor(0, 260);\n  tft.setTextColor(HX8347D_GREEN, HX8347D_BLACK);\n  tft.setTextSize(3);\n  tft.println((process_time/1000) + String(\" ms \"));    \n  \n  tft.setCursor(0, 300);\n  tft.println(1000/(process_time/1000) + String(\" FPS  \"));\n}\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/rtc_time/rtc_time.ino",
    "content": "\ntypedef struct\n{\n  uint32_t time_year;\n  uint32_t time_mon;\n  uint32_t time_day;\n  uint32_t time_hour;\n  uint32_t time_min;\n  uint32_t time_sec;\n} rtc_time_t;\n\n\n\nbool setRtcTime(uint32_t _year, uint32_t _mon, uint32_t _day, uint32_t _hour, uint32_t _min, uint32_t _sec);\nrtc_time_t getRtcTime(void);\n\n\n\n\nvoid setup() {\n  // put your setup code here, to run once:\n  Serial.begin(115200);\n\n\n  // if you want to change the time, uncommnet line below.\n  //setRtcTime(2018, 3, 5, 13, 22, 1);\n\n\n}\n\nvoid loop() {  \n  rtc_time_t rtc_time;\n\n  rtc_time = getRtcTime();\n\n\n  Serial.print(String(rtc_time.time_year));\n  Serial.print(String(\"/\") + String(rtc_time.time_mon));\n  Serial.print(String(\"/\") + String(rtc_time.time_day));\n  Serial.print(String(\" \") + String(rtc_time.time_hour));\n  Serial.print(String(\":\") + String(rtc_time.time_min));\n  Serial.println(String(\":\") + String(rtc_time.time_sec));\n\n  delay(1000);\n}\n\n\n\n\nrtc_time_t getRtcTime(void)\n{\n  rtc_time_t ret;\n  time_t now;\n  struct tm *t;\n\n  now = rtcGetTime();    \n  t   = localtime(&now); \n\n  ret.time_year = t->tm_year + 1900;\n  ret.time_mon  = t->tm_mon;\n  ret.time_day  = t->tm_mday;\n  ret.time_hour = t->tm_hour;\n  ret.time_min  = t->tm_min;\n  ret.time_sec  = t->tm_sec;  \n\n  return ret;\n}\n\n\nbool setRtcTime(uint32_t _year, uint32_t _mon, uint32_t _day, uint32_t _hour, uint32_t _min, uint32_t _sec)\n{\n  struct tm time_str;\n  time_t time_data;\n  \n  time_str.tm_year = _year - 1900;\n  time_str.tm_mon = _mon;\n  time_str.tm_mday = _day;\n  time_str.tm_hour = _hour;\n  time_str.tm_min = _min;\n  time_str.tm_sec = _sec;\n  time_str.tm_isdst = -1;\n\n  time_data = mktime(&time_str);\n  \n  if ( time_data == -1)\n  {\n    return false;\n  }\n\n  rtcSetTime(time_data);\n  \n  return true;\n}\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenCR/examples/10. Etc/usb_to_dxl/usb_to_dxl.ino",
    "content": "#include <DynamixelSDK.h>\r\n#include <stdarg.h>\r\n\r\n\r\n#define DXL_USB_VER           20170915\r\n\r\n#define CMD_PORT              Serial      // USB\r\n#define DBG_PORT              Serial2     // UART1\r\n#define DXL_PORT              Serial3\r\n#define DXL_BAUD              1000000\r\n\r\n\r\n#define DXL_LED_RX            BDPIN_LED_USER_1\r\n#define DXL_LED_TX            BDPIN_LED_USER_2\r\n\r\n\r\n#define DXL_POWER_DISABLE()   digitalWrite(BDPIN_DXL_PWR_EN, LOW);\r\n#define DXL_POWER_ENABLE()    digitalWrite(BDPIN_DXL_PWR_EN, HIGH);\r\n\r\n#define DXL_TX_BUFFER_LENGTH  1024\r\n\r\n\r\nuint8_t tx_buffer[DXL_TX_BUFFER_LENGTH];\r\n\r\n\r\nstatic int rx_led_count = 0;\r\nstatic int tx_led_count = 0;\r\n\r\nstatic int rx_led_update_time;\r\nstatic int tx_led_update_time;\r\n\r\nstatic uint32_t update_time[8];\r\n\r\n\r\nstatic uint32_t rx_data_cnt = 0;\r\nstatic uint32_t tx_data_cnt = 0;\r\n\r\nstatic uint32_t rx_bandwidth = 0;\r\nstatic uint32_t tx_bandwidth = 0;\r\n\r\nuint32_t usb_baud;\r\n\r\n\r\nvoid setup()\r\n{\r\n  CMD_PORT.begin(115200);\r\n  DBG_PORT.begin(57600);\r\n  DXL_PORT.begin(DXL_BAUD);\r\n\r\n  pinMode( BDPIN_DXL_PWR_EN, OUTPUT );\r\n  pinMode( DXL_LED_RX, OUTPUT );\r\n  pinMode( DXL_LED_TX, OUTPUT );\r\n\r\n  digitalWrite(DXL_LED_TX, HIGH);\r\n  digitalWrite(DXL_LED_RX, HIGH);\r\n\r\n  drv_dxl_tx_enable(FALSE);\r\n\r\n  DXL_POWER_ENABLE();\r\n}\r\n\r\nvoid loop()\r\n{\r\n  update_dxl();\r\n  update_led();\r\n\r\n  if( CMD_PORT.getBaudRate() != DXL_PORT.getBaudRate() )\r\n  {\r\n    DXL_PORT.begin(CMD_PORT.getBaudRate());\r\n  }\r\n\r\n  if( (millis()-update_time[1]) > 1000 )\r\n  {\r\n    update_time[1] = millis();\r\n\r\n    tx_bandwidth = tx_data_cnt;\r\n    rx_bandwidth = rx_data_cnt;\r\n\r\n    tx_data_cnt = 0;\r\n    rx_data_cnt = 0;\r\n  }\r\n}\r\n\r\n\r\nvoid update_dxl()\r\n{\r\n  int length;\r\n  int i;\r\n\r\n\r\n  //-- USB -> DXL\r\n  length = CMD_PORT.available();\r\n  if( length > 0 )\r\n  {\r\n    drv_dxl_tx_enable(TRUE);\r\n    for(i=0; i<length; i++ )\r\n    {\r\n      DXL_PORT.write(CMD_PORT.read());\r\n      DXL_PORT.flush();\r\n    }\r\n    drv_dxl_tx_enable(FALSE);\r\n\r\n    tx_led_count = 3;\r\n\r\n    tx_data_cnt += length;\r\n  }\r\n\r\n  //-- DXL -> USB\r\n  length = DXL_PORT.available();\r\n  if( length > 0 )\r\n  {\r\n    if( length > DXL_TX_BUFFER_LENGTH )\r\n    {\r\n      length = DXL_TX_BUFFER_LENGTH;\r\n    }\r\n    for(i=0; i<length; i++ )\r\n    {\r\n      tx_buffer[i] = DXL_PORT.read();\r\n    }\r\n    CMD_PORT.write(tx_buffer, length);\r\n\r\n    rx_led_count = 3;\r\n    rx_data_cnt += length;\r\n  }\r\n}\r\n\r\n\r\nvoid update_led()\r\n{\r\n  if( (millis()-tx_led_update_time) > 50 )\r\n  {\r\n    tx_led_update_time = millis();\r\n\r\n    if( tx_led_count )\r\n    {\r\n      digitalWrite(DXL_LED_TX, !digitalRead(DXL_LED_TX));\r\n      tx_led_count--;\r\n    }\r\n    else\r\n    {\r\n      digitalWrite(DXL_LED_TX, HIGH);\r\n    }\r\n  }\r\n\r\n  if( (millis()-rx_led_update_time) > 50 )\r\n  {\r\n    rx_led_update_time = millis();\r\n\r\n    if( rx_led_count )\r\n    {\r\n      digitalWrite(DXL_LED_RX, !digitalRead(DXL_LED_RX));\r\n      rx_led_count--;\r\n    }\r\n    else\r\n    {\r\n      digitalWrite(DXL_LED_RX, HIGH);\r\n    }\r\n  }\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Chain/open_manipulator_chain/demo.h",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef DEMO_H_\n#define DEMO_H_\n\n#include <open_manipulator_libs.h>\n\nbool start_demo_flag;\nbool erasing_flag;\nuint8_t motion_cnt[] = {0};\nuint8_t sub_motion_cnt[] = {0};\n\n/*****************************************************************************\n** Functions used in runDemo()\n*****************************************************************************/\n// Move in Joint Space \nvoid moveJS(OpenManipulator *open_manipulator, double j1, double j2, double j3, double j4, double t)\n{\n  static std::vector <double> target_angle;\n  target_angle.clear();\n  target_angle.push_back(j1);\n  target_angle.push_back(j2);\n  target_angle.push_back(j3);\n  target_angle.push_back(j4);\n  open_manipulator->makeJointTrajectory(target_angle,t);\n}\n\n/*****************************************************************************\n** Start or Stop Demo\n*****************************************************************************/\nvoid startDemo()\n{\n  // Start the demo\n  start_demo_flag = true;\n}\n\nvoid stopDemo(OpenManipulator *open_manipulator)\n{\n  // Stop the demo\n  start_demo_flag = false;\n\n  // Move to the default pose.\n  moveJS(open_manipulator, 0.0, 0.0, 0.0, 0.0, 1.0); \n  open_manipulator->makeToolTrajectory(\"tool\", 0.0);\n\n  // Reset the count variables\n  motion_cnt[0] = 0;\n  sub_motion_cnt[0] = 0;\n  erasing_flag = false;\n}\n\n/*****************************************************************************\n** Initialize Demo\n*****************************************************************************/\nvoid initDemo()\n{\n  start_demo_flag = false;\n  motion_cnt[0] = 0;\n  sub_motion_cnt[0] = 0;\n  erasing_flag = false;\n\n  pinMode(BDPIN_PUSH_SW_1, INPUT);\n  pinMode(BDPIN_PUSH_SW_2, INPUT);\n}\n\n/*****************************************************************************\n** Run Demo\n*****************************************************************************/\nvoid runDemo(OpenManipulator *open_manipulator)\n{\n  if(digitalRead(BDPIN_PUSH_SW_1))\n  {\n    startDemo();\n  }\n  if(digitalRead(BDPIN_PUSH_SW_2))\n  {\n    stopDemo(open_manipulator);\n  }\n\n  if (open_manipulator->getMovingState())\n  {\n    return;\n  }\n  else \n  {\n    if (start_demo_flag)\n    // if (1)\n    {\n      // Draw Objects\n      if (!erasing_flag)\n      {\n        switch(motion_cnt[0])\n        {\n\n          case 0:\n            moveJS(open_manipulator, 0.0, -1.0, 0.2, 0.8, 2.0); \n            motion_cnt[0] ++; \n          break;\n          case 1:\n            moveJS(open_manipulator, -0.5, 0.0, 1.0, -1.0, 2.0); \n            motion_cnt[0] ++; \n          break;\n          case 2:\n            moveJS(open_manipulator, -0.5, 0.1, 0.75, -0.85, 2.0); \n            motion_cnt[0] ++; \n          break;\n          case 3:\n            open_manipulator->sleepTrajectory(2.0);\n            motion_cnt[0] ++; \n          break;\n          case 4:\n            moveJS(open_manipulator, -0.5, -0.05, 1.05, -1.0, 2.0); \n            motion_cnt[0] = 0; \n          break;\n        }\n      }\n    }\n  }\n}\n\n#endif // DEMO_H_\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Chain/open_manipulator_chain/open_manipulator_chain.ino",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include <open_manipulator_libs.h>\n#include \"processing.h\"\n#include \"remote_controller.h\"\n#include \"demo.h\"\n\nOpenManipulator open_manipulator;\ndouble control_time = 0.010;\ndouble present_time = 0.0;\ndouble previous_time = 0.0;\nbool platform_state = true;\n\nvoid setup()\n{\n  Serial.begin(57600);\n  DEBUG.begin(57600);\n  // while (!Serial)\n  // ;\n\n  connectProcessing(platform_state);\n  connectRC100();\n\n\n  open_manipulator.initOpenManipulator(platform_state);\n  log::println(\"OpenManipulator Debugging Port\");\n\n\n  initDemo();\n}\n\nvoid loop()\n{\n  present_time = millis()/1000.0;\n  getData(100);\n  playProcessingMotion(&open_manipulator);\n\n  if(present_time-previous_time >= control_time)\n  {\n    open_manipulator.processOpenManipulator(millis()/1000.0);\n    previous_time = millis()/1000.0;\n    sendValueToProcessing(&open_manipulator);\n  }\n\n  runDemo(&open_manipulator);\n}\n\n\n\nvoid getData(uint32_t wait_time)\n{\n  static uint8_t state = 0;\n  static uint32_t tick = 0;\n\n  bool rc100_state = false;\n  bool processing_state = false;\n\n  uint16_t get_rc100_data = 0;\n  String get_processing_data = \"\";\n\n  if (availableRC100())\n  {\n    get_rc100_data = readRC100Data();\n    rc100_state = true;\n  }\n\n  if (availableProcessing())\n  {\n    get_processing_data = readProcessingData();\n    processing_state = true;\n  }\n\n  \n  switch (state)\n  {\n    case 0:\n      if (rc100_state)\n      {\n        fromRC100(&open_manipulator, get_rc100_data);\n        tick = millis();\n        state = 1;\n      }\n      else if (processing_state)\n      {\n        fromProcessing(&open_manipulator, get_processing_data);\n        tick = millis();\n        state = 1;\n      }\n     break;\n\n    case 1:\n      if ((millis() - tick) >= wait_time)\n      {\n        state = 0;\n      }\n     break;\n\n    default:\n      state = 0;\n     break;\n  }\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Chain/open_manipulator_chain/processing.h",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef PROCESSING_H_\n#define PROCESSING_H_\n\n#include <open_manipulator_libs.h>\n\n#define DXL_SIZE 5\n\ntypedef struct _MotionWaypoint\n{\n  std::vector<double> angle;\n  double path_time;\n  double gripper_value;\n} MotionWaypoint;\n\nstd::vector<MotionWaypoint> motion_way_point_buf;\nbool processing_motion_state = false;\nchar hand_motion_cnt = 0;\nbool hand_motion_repeat_state = false;\nbool platform_state_processing = false;\nString global_cmd[50];\n\nvoid connectProcessing(bool platform)\n{ \n  platform_state_processing = platform;\n  for (int i = 0; i < DXL_SIZE; i++)\n  {\n    Serial.print(0.0);\n    Serial.print(\",\");\n  }\n\n  Serial.println(0.0);\n  delay(300);\n\n  Serial.println(\"Init Processing\");\n}\n\nint availableProcessing()\n{\n  return Serial.available();\n}\n\nString readProcessingData()\n{\n  return Serial.readStringUntil('\\n');\n}\n\nvoid split(String data, char separator, String* temp)\n{\n  int cnt = 0;\n  int get_index = 0;\n\n  String copy = data;\n  \n  while(true)\n  {\n    get_index = copy.indexOf(separator);\n\n    if(-1 != get_index)\n    {\n      temp[cnt] = copy.substring(0, get_index);\n      copy = copy.substring(get_index + 1);\n    }\n    else\n    {\n      temp[cnt] = copy.substring(0, copy.length());\n      break;\n    }\n\t  ++cnt;\n  }\n}\n\nString* parseDataFromProcessing(String get)\n{\n  get.trim();\n  split(get, ',', global_cmd);\n  \n  return global_cmd;\n}\n\nvoid sendAngleToProcessing(JointWaypoint joint_states_vector)\n{\n  Serial.print(\"angle\");\n  for (int i = 0; i < (int)joint_states_vector.size(); i++)\n  {\n    Serial.print(\",\");\n    Serial.print(joint_states_vector.at(i).position, 3);\n  }\n  Serial.print(\"\\n\");\n}\n\nvoid sendToolDataToProcessing(ToolValue value)\n{\n  Serial.print(\"tool\");\n  Serial.print(\",\");\n  Serial.print(value.position * 10);\n  Serial.print(\"\\n\");\n}\n\nvoid sendValueToProcessing(OpenManipulator *open_manipulator)\n{\n  sendAngleToProcessing(open_manipulator->getAllActiveJointValue());\n  sendToolDataToProcessing(open_manipulator->getToolValue(\"gripper\"));\n}\n\nvoid fromProcessing(OpenManipulator *open_manipulator, String data)\n{\n  String *cmd = parseDataFromProcessing(data);\n\n  if (cmd[0] == \"opm\")\n  {\n    if (cmd[1] == \"ready\")\n    {\n      if(platform_state_processing)\n      {\n        open_manipulator->enableAllActuator();\n        sendValueToProcessing(open_manipulator);\n      }\n    }\n    else if (cmd[1] == \"end\")\n    {\n      if(platform_state_processing)\n      {\n        open_manipulator->disableAllActuator();\n      }\n    }\n  }\n  ////////// joint space control tab\n  else if (cmd[0] == \"joint\")\n  {\n    std::vector<double> goal_position;\n    for (uint8_t index = 0; index < DXL_SIZE; index++)\n    {\n      goal_position.push_back((double)cmd[index + 1].toFloat());\n    }\n    open_manipulator->makeJointTrajectory(goal_position, 1.0); // FIX TIME PARAM\n  }\n  else if (cmd[0] == \"gripper\")\n  {\n    open_manipulator->makeToolTrajectory(\"gripper\", (double)cmd[1].toFloat());\n  }\n  else if (cmd[0] == \"grip\")\n  {\n    if (cmd[1] == \"on\")\n      open_manipulator->makeToolTrajectory(\"gripper\", -0.009);\n    else if (cmd[1] == \"off\")\n      open_manipulator->makeToolTrajectory(\"gripper\", 0.009);\n  }\n  ////////// task space control tab\n  else if (cmd[0] == \"task\")\n  {\n    if (cmd[1] == \"forward\")\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"gripper\", math::vector3(0.010, 0.0, 0.0), 0.2);\n    else if (cmd[1] == \"back\")\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"gripper\", math::vector3(-0.010, 0.0, 0.0), 0.2);\n    else if (cmd[1] == \"left\")\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"gripper\", math::vector3(0.0, 0.010, 0.0), 0.2);\n    else if (cmd[1] == \"right\")\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"gripper\", math::vector3(0.0, -0.010, 0.0), 0.2);\n    else if (cmd[1] == \"up\")\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"gripper\", math::vector3(0.0, 0.0, 0.010), 0.2);\n    else if (cmd[1] == \"down\")\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"gripper\", math::vector3(0.0, 0.0, -0.010), 0.2);\n    else\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"gripper\", math::vector3(0.0, 0.0, 0.0), 0.2);\n  }\n  else if (cmd[0] == \"torque\")\n  {\n    if(platform_state_processing)\n    {\n      if (cmd[1] == \"on\")\n        open_manipulator->enableAllJointActuator();\n      else if (cmd[1] == \"off\")\n        open_manipulator->disableAllJointActuator();\n    }\n  }\n  ////////// hand teaching tab\n  else if (cmd[0] == \"get\")\n  {\n    if (cmd[1] == \"clear\")  // motion clear\n    {\n      processing_motion_state = false;\n      motion_way_point_buf.clear();\n      hand_motion_cnt = 0;\n    }\n    else if (cmd[1] == \"pose\")  // save pose\n    {\n      MotionWaypoint read_value;\n      JointWaypoint present_states = open_manipulator->getAllActiveJointValue();\n      for(uint32_t i = 0; i < present_states.size(); i ++)\n        read_value.angle.push_back(present_states.at(i).position);  \n      read_value.path_time = 2.0; // FIX TIME PARAM\n      read_value.gripper_value = open_manipulator->getToolValue(\"gripper\").position;\n      motion_way_point_buf.push_back(read_value);  \n      hand_motion_cnt = 0;\n    }\n    else if (cmd[1] == \"on\")  // save gripper on\n    {\n      open_manipulator->makeToolTrajectory(\"gripper\", -0.009);\n    }\n    else if (cmd[1] == \"off\")  // save gripper off\n    {\n      open_manipulator->makeToolTrajectory(\"gripper\", 0.009);\n    }\n  }\n  else if (cmd[0] == \"hand\")\n  {\n    if (cmd[1] == \"once\") // play motion (once)\n    {\n      processing_motion_state = true;\n    }\n    else if (cmd[1] == \"repeat\") // play motion (repeat)\n    {\n      hand_motion_repeat_state = true;\n    }\n    else if (cmd[1] == \"stop\") // play motion (stop)\n    {\n      hand_motion_repeat_state = false;\n      processing_motion_state = false;\n      hand_motion_cnt = 0;\n    }\n  }\n  ////////// motion tab\n  else if (cmd[0] == \"motion\")\n  {\n    if (cmd[1] == \"1\")\n    {\n      TaskWaypoint draw_line_arg;\n      draw_line_arg.kinematic.position(0) = 0.02;\n      draw_line_arg.kinematic.position(1) = 0.02;\n      draw_line_arg.kinematic.position(2) = -0.02;\n      void *p_draw_line_arg = &draw_line_arg;\n      open_manipulator->makeCustomTrajectory(CUSTOM_TRAJECTORY_LINE, \"gripper\", p_draw_line_arg, 1.0);\n    }\n    else if (cmd[1] == \"2\")\n    {\n      double draw_circle_arg[3];\n      draw_circle_arg[0] = 0.03; // radius (m)\n      draw_circle_arg[1] = 2;    // revolution\n      draw_circle_arg[2] = 0.0;  // start angle position (rad)\n      void* p_draw_circle_arg = &draw_circle_arg;\n      open_manipulator->makeCustomTrajectory(CUSTOM_TRAJECTORY_CIRCLE, \"gripper\", p_draw_circle_arg, 4.0);\n    }\n  }\n}\n\nvoid playProcessingMotion(OpenManipulator *open_manipulator)\n{\n  if(!open_manipulator->getMovingState() && processing_motion_state)\n  {\n    if(motion_way_point_buf.size() == 0)\n      return;\n\n    open_manipulator->makeToolTrajectory(\"gripper\", motion_way_point_buf.at(hand_motion_cnt).gripper_value);\n    open_manipulator->makeJointTrajectory(motion_way_point_buf.at(hand_motion_cnt).angle, motion_way_point_buf.at(hand_motion_cnt).path_time); \n    hand_motion_cnt ++;\n    if(hand_motion_cnt >= motion_way_point_buf.size())\n    {\n      hand_motion_cnt = 0;\n      if(!hand_motion_repeat_state)\n        processing_motion_state = false;\n    }\n  }\n}\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Chain/open_manipulator_chain/remote_controller.h",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef REMOTE_CONTROLLER_H_\n#define REMOTE_CONTROLLER_H_\n\n#include <open_manipulator_libs.h>\n#include <RC100.h>\n\nRC100 rc100;\ndouble grip_value = 0.0;\n\nvoid connectRC100()\n{\n  rc100.begin(1);\n}\n\nint availableRC100()\n{\n  return rc100.available();\n}\n\nuint16_t readRC100Data()\n{\n  return rc100.readData();\n}\n\nvoid fromRC100(OpenManipulator* open_manipulator, uint16_t data)\n{\n  if (data & RC100_BTN_U) \n    open_manipulator->makeTaskTrajectoryFromPresentPose(\"gripper\", math::vector3(0.007, 0.0, 0.0), 0.16);\n  else if (data & RC100_BTN_D)\n    open_manipulator->makeTaskTrajectoryFromPresentPose(\"gripper\", math::vector3(-0.007, 0.0, 0.0), 0.16);\n  else if (data & RC100_BTN_L)\n    open_manipulator->makeTaskTrajectoryFromPresentPose(\"gripper\", math::vector3(0.0, 0.007, 0.0), 0.16);\n  else if (data & RC100_BTN_R)\n    open_manipulator->makeTaskTrajectoryFromPresentPose(\"gripper\", math::vector3(0.0, -0.007, 0.0), 0.16);\n  else if (data & RC100_BTN_1)\n    open_manipulator->makeTaskTrajectoryFromPresentPose(\"gripper\", math::vector3(0.0, 0.0, 0.007), 0.16);\n  else if (data & RC100_BTN_3)\n    open_manipulator->makeTaskTrajectoryFromPresentPose(\"gripper\", math::vector3(0.0, 0.0, -0.007), 0.16);\n  else if (data & RC100_BTN_2)\n  {\n    grip_value += 0.0020;\n    if (grip_value > 0.01f)\n      grip_value = 0.01f;\n\n    open_manipulator->makeToolTrajectory(\"gripper\", grip_value);\n  }\n  else if (data & RC100_BTN_4)\n  {\n    grip_value -= 0.002;\n    if (grip_value < -0.01f)\n      grip_value = -0.01f;\n\n    open_manipulator->makeToolTrajectory(\"gripper\", grip_value);\n  }\n  else if (data & RC100_BTN_5)\n  {\n    std::vector<double> goal_position;\n    goal_position.push_back(0.0);\n    goal_position.push_back(-60.0 * DEG2RAD);\n    goal_position.push_back(20.0 * DEG2RAD);\n    goal_position.push_back(40.0 * DEG2RAD);\n    open_manipulator->makeJointTrajectory(goal_position, 1.5);\n  }\n  else if (data & RC100_BTN_6)\n  {\n    std::vector<double> goal_position;\n    goal_position.push_back(0.0);\n    goal_position.push_back(0.0);\n    goal_position.push_back(0.0);\n    goal_position.push_back(0.0);\n    open_manipulator->makeJointTrajectory(goal_position, 1.0);\n  }\n}\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Chain/open_manipulator_chain_ROS/open_manipulator_chain_ROS.h",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef OPEN_MANIPULATOR_CHAIN_ROS_H_\n#define OPEN_MANIPULATOR_CHAIN_ROS_H_\n\n#include <ros.h>\n#include <ros/time.h>\n\n#include <open_manipulator_libs.h>\n\n#include <sensor_msgs/JointState.h>\n#include <open_manipulator_msgs/KinematicsPose.h>\n#include <open_manipulator_msgs/OpenManipulatorState.h>\n\n#include <open_manipulator_msgs/SetJointPosition.h>\n#include <open_manipulator_msgs/SetKinematicsPose.h>\n#include <open_manipulator_msgs/SetActuatorState.h>\n#include <open_manipulator_msgs/SetDrawingTrajectory.h>\n\nusing open_manipulator_msgs::SetJointPosition;\nusing open_manipulator_msgs::SetKinematicsPose;\nusing open_manipulator_msgs::SetActuatorState;\nusing open_manipulator_msgs::SetDrawingTrajectory;\n\nOpenManipulator open_manipulator;\ndouble present_time = 0.0;\ndouble previous_time = 0.0;\ndouble previous_time_pub = 0.0;\n\n/*******************************************************************************\n* ROS NodeHandle\n*******************************************************************************/\nros::NodeHandle nh;\n\n/*******************************************************************************\n* Service Server\n*******************************************************************************/\nvoid goalJointSpacePathCallback(const SetJointPosition::Request & req, SetJointPosition::Response & res);\nros::ServiceServer<SetJointPosition::Request, SetJointPosition::Response> goal_joint_space_path_server(\n  \"open_manipulator/goal_joint_space_path\", &goalJointSpacePathCallback);\n\nvoid goalJointSpacePathToKinematicsPoseCallback(const SetKinematicsPose::Request & req, SetKinematicsPose::Response & res);\nros::ServiceServer<SetKinematicsPose::Request, SetKinematicsPose::Response> goal_joint_space_path_to_kinematics_pose_server(\n  \"open_manipulator/goal_joint_space_path_to_kinematics_pose\", &goalJointSpacePathToKinematicsPoseCallback);\n\nvoid goalJointSpacePathToKinematicsPositionCallback(const SetKinematicsPose::Request & req, SetKinematicsPose::Response & res);\nros::ServiceServer<SetKinematicsPose::Request, SetKinematicsPose::Response> goal_joint_space_path_to_kinematics_position_server(\n  \"open_manipulator/goal_joint_space_path_to_kinematics_position\", &goalJointSpacePathToKinematicsPositionCallback);\n\nvoid goalJointSpacePathToKinematicsOrientationCallback(const SetKinematicsPose::Request & req, SetKinematicsPose::Response & res);\nros::ServiceServer<SetKinematicsPose::Request, SetKinematicsPose::Response> goal_joint_space_path_to_kinematics_orientation_server(\n  \"open_manipulator/goal_joint_space_path_to_kinematics_orientation\", &goalJointSpacePathToKinematicsOrientationCallback);\n\nvoid goalTaskSpacePathCallback(const SetKinematicsPose::Request & req, SetKinematicsPose::Response & res);\nros::ServiceServer<SetKinematicsPose::Request, SetKinematicsPose::Response> goal_task_space_path_server(\n  \"open_manipulator/goal_task_space_path\", &goalTaskSpacePathCallback);\n\nvoid goalTaskSpacePathPositionOnlyCallback(const SetKinematicsPose::Request & req, SetKinematicsPose::Response & res);\nros::ServiceServer<SetKinematicsPose::Request, SetKinematicsPose::Response> goal_task_space_path_position_only_server(\n  \"open_manipulator/goal_task_space_path_position_only\", &goalTaskSpacePathPositionOnlyCallback);\n\nvoid goalTaskSpacePathOrientationOnlyCallback(const SetKinematicsPose::Request & req, SetKinematicsPose::Response & res);\nros::ServiceServer<SetKinematicsPose::Request, SetKinematicsPose::Response> goal_task_space_path_orientation_only_server(\n  \"open_manipulator/goal_task_space_path_orientation_only\", &goalTaskSpacePathOrientationOnlyCallback);\n\nvoid goalJointSpacePathFromPresentCallback(const SetJointPosition::Request & req, SetJointPosition::Response & res);\nros::ServiceServer<SetJointPosition::Request, SetJointPosition::Response> goal_joint_space_path_from_present_server(\n  \"open_manipulator/goal_joint_space_path_from_present\", &goalJointSpacePathFromPresentCallback);\n\nvoid goalTaskSpacePathFromPresentCallback(const SetKinematicsPose::Request & req, SetKinematicsPose::Response & res);\nros::ServiceServer<SetKinematicsPose::Request, SetKinematicsPose::Response> goal_task_space_path_from_present_server(\n  \"open_manipulator/goal_task_space_path_from_present\", &goalTaskSpacePathFromPresentCallback);\n\nvoid goalTaskSpacePathFromPresentPositionOnlyCallback(const SetKinematicsPose::Request & req, SetKinematicsPose::Response & res);\nros::ServiceServer<SetKinematicsPose::Request, SetKinematicsPose::Response> goal_task_space_path_from_present_position_only_server(\n  \"open_manipulator/goal_task_space_path_from_present_position_only\", &goalTaskSpacePathFromPresentPositionOnlyCallback);\n\nvoid goalTaskSpacePathFromPresentOrientationOnlyCallback(const SetKinematicsPose::Request & req, SetKinematicsPose::Response & res);\nros::ServiceServer<SetKinematicsPose::Request, SetKinematicsPose::Response> goal_task_space_path_from_present_orientation_only_server(\n  \"open_manipulator/goal_task_space_path_from_present_orientation_only\", &goalTaskSpacePathFromPresentOrientationOnlyCallback);\n\nvoid goalToolControlCallback(const SetJointPosition::Request & req, SetJointPosition::Response & res);\nros::ServiceServer<SetJointPosition::Request, SetJointPosition::Response> goal_tool_control_server(\n  \"open_manipulator/goal_tool_control\", &goalToolControlCallback);\n\nvoid setActuatorStateCallback(const SetActuatorState::Request & req, SetActuatorState::Response & res);\nros::ServiceServer<SetActuatorState::Request, SetActuatorState::Response> set_actuator_state_server(\n  \"open_manipulator/set_actuator_state\", &setActuatorStateCallback);\n\nvoid goalDrawingTrajectoryCallBack(const SetDrawingTrajectory::Request & req, SetDrawingTrajectory::Response & res);\nros::ServiceServer<SetDrawingTrajectory::Request, SetDrawingTrajectory::Response> goal_drawing_trajectory_server(\n  \"open_manipulator/goal_drawing_trajectory\", &goalDrawingTrajectoryCallBack);\n\n/*******************************************************************************\n* Publisher\n*******************************************************************************/\nvoid publishJointStates(void);\nsensor_msgs::JointState joint_states_msg;\nros::Publisher joint_states_pub(\"open_manipulator/joint_states\", &joint_states_msg);\n\nvoid publishKinematicPose(void);\nopen_manipulator_msgs::KinematicsPose kinematic_pose_msg;\nros::Publisher kinematic_pose_pub(\"open_manipulator/gripper/kinematics_pose\", &kinematic_pose_msg);\n\nvoid publishOpenManipulatorStates(void);\nopen_manipulator_msgs::OpenManipulatorState open_manipulator_states_msg; \nros::Publisher open_manipulator_states_pub(\"open_manipulator/states\", &open_manipulator_states_msg);\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Chain/open_manipulator_chain_ROS/open_manipulator_chain_ROS.ino",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include \"open_manipulator_chain_ROS.h\"\n\ndouble control_time = 0.010f;\n\nvoid setup()\n{\n  DEBUG.begin(57600);\n\n  // Initialize ROS node handle, advertise and subscribe the topics\n  nh.initNode();\n  nh.getHardware()->setBaud(115200);\n\n  nh.advertise(joint_states_pub);  \n  nh.advertise(kinematic_pose_pub);  \n  nh.advertise(open_manipulator_states_pub);  \n\n  nh.advertiseService(goal_joint_space_path_server);\n  nh.advertiseService(goal_joint_space_path_to_kinematics_pose_server);\n  nh.advertiseService(goal_joint_space_path_to_kinematics_position_server);\n  nh.advertiseService(goal_joint_space_path_to_kinematics_orientation_server);\n  nh.advertiseService(goal_task_space_path_server);\n  nh.advertiseService(goal_task_space_path_position_only_server);\n  nh.advertiseService(goal_task_space_path_orientation_only_server);\n  nh.advertiseService(goal_joint_space_path_from_present_server);\n  nh.advertiseService(goal_task_space_path_from_present_server);\n  nh.advertiseService(goal_task_space_path_from_present_position_only_server);\n  nh.advertiseService(goal_task_space_path_from_present_orientation_only_server);\n  nh.advertiseService(goal_tool_control_server);\n  nh.advertiseService(set_actuator_state_server);\n  nh.advertiseService(goal_drawing_trajectory_server);\n\n  // Initialize Open Manipulator.  \n  open_manipulator.initOpenManipulator(true);\n\n  log::println(\"OpenManipulator Debugging Port\");\n}\n\nvoid loop()\n{\n  present_time = (float)(millis()/1000.0f);\n  nh.spinOnce();\n\n  if(present_time-previous_time >= control_time)\n  {\n    open_manipulator.processOpenManipulator(millis()/1000.0);\n    previous_time = (float)(millis()/1000.0f);\n  }\n  if(present_time - previous_time_pub >= control_time*10)\n  {\n    publishJointStates();\n    publishKinematicPose();\n    publishOpenManipulatorStates();\n    previous_time_pub = (float)(millis()/1000.0f);\n  }\n}\n\n/*******************************************************************************\n* Service server (set trajectory using joint angle values)\n*******************************************************************************/\nvoid goalJointSpacePathCallback(const SetJointPosition::Request & req, SetJointPosition::Response & res)\n{\n  std::vector <double> target_angle;\n  for(int i = 0; i < req.joint_position.joint_name_length; i ++)\n    target_angle.push_back(req.joint_position.position[i]);\n\n  open_manipulator.makeJointTrajectory(target_angle, req.path_time);\n\n  res.is_planned = true;\n}\n\n/*******************************************************************************\n* Service server (set trajectory using kinematic pose value)\n*******************************************************************************/\nvoid goalJointSpacePathToKinematicsPoseCallback(const SetKinematicsPose::Request & req, SetKinematicsPose::Response & res)\n{\n  KinematicPose target_pose;\n  target_pose.position[0] = req.kinematics_pose.pose.position.x;\n  target_pose.position[1] = req.kinematics_pose.pose.position.y;\n  target_pose.position[2] = req.kinematics_pose.pose.position.z;\n\n  Eigen::Quaterniond q(req.kinematics_pose.pose.orientation.w,\n                       req.kinematics_pose.pose.orientation.x,\n                       req.kinematics_pose.pose.orientation.y,\n                       req.kinematics_pose.pose.orientation.z);\n  target_pose.orientation = math::convertQuaternionToRotationMatrix(q);\n\n  open_manipulator.makeJointTrajectory(req.end_effector_name, target_pose, req.path_time);\n\n  res.is_planned = true;\n}\n\n/*******************************************************************************\n* Service server (set trajectory using kinematic position value)\n*******************************************************************************/\nvoid goalJointSpacePathToKinematicsPositionCallback(const SetKinematicsPose::Request & req, SetKinematicsPose::Response & res)\n{\n  KinematicPose target_pose;\n  target_pose.position[0] = req.kinematics_pose.pose.position.x;\n  target_pose.position[1] = req.kinematics_pose.pose.position.y;\n  target_pose.position[2] = req.kinematics_pose.pose.position.z;\n\n  open_manipulator.makeJointTrajectory(req.end_effector_name, target_pose, req.path_time);\n\n  res.is_planned = true;\n}\n\n/*******************************************************************************\n* Service server (set trajectory using kinematic orientation value)\n*******************************************************************************/\nvoid goalJointSpacePathToKinematicsOrientationCallback(const SetKinematicsPose::Request & req, SetKinematicsPose::Response & res)\n{\n  KinematicPose target_pose;\n\n  Eigen::Quaterniond q(req.kinematics_pose.pose.orientation.w,\n                       req.kinematics_pose.pose.orientation.x,\n                       req.kinematics_pose.pose.orientation.y,\n                       req.kinematics_pose.pose.orientation.z);\n  target_pose.orientation = math::convertQuaternionToRotationMatrix(q);\n\n  open_manipulator.makeJointTrajectory(req.end_effector_name, target_pose, req.path_time);\n\n  res.is_planned = true;\n}\n\n/*******************************************************************************\n* Service server (set trajectory using kinematic pose value)\n*******************************************************************************/\nvoid goalTaskSpacePathCallback(const SetKinematicsPose::Request & req, SetKinematicsPose::Response & res)\n{\n  KinematicPose target_pose;\n  target_pose.position[0] = req.kinematics_pose.pose.position.x;\n  target_pose.position[1] = req.kinematics_pose.pose.position.y;\n  target_pose.position[2] = req.kinematics_pose.pose.position.z;\n\n  Eigen::Quaterniond q(req.kinematics_pose.pose.orientation.w,\n                       req.kinematics_pose.pose.orientation.x,\n                       req.kinematics_pose.pose.orientation.y,\n                       req.kinematics_pose.pose.orientation.z);\n  target_pose.orientation = math::convertQuaternionToRotationMatrix(q);\n\n  open_manipulator.makeTaskTrajectory(req.end_effector_name, target_pose, req.path_time);\n\n  res.is_planned = true;\n}\n\n/*******************************************************************************\n* Service server (set trajectory using kinematic position value)\n*******************************************************************************/\nvoid goalTaskSpacePathPositionOnlyCallback(const SetKinematicsPose::Request & req, SetKinematicsPose::Response & res)\n{\n  Eigen::Vector3d position;\n  position[0] = req.kinematics_pose.pose.position.x;\n  position[1] = req.kinematics_pose.pose.position.y;\n  position[2] = req.kinematics_pose.pose.position.z;\n\n  open_manipulator.makeTaskTrajectory(req.end_effector_name, position, req.path_time);\n\n  res.is_planned = true;\n}\n\n/*******************************************************************************\n* Service server (set trajectory using kinematic orientation value)\n*******************************************************************************/\nvoid goalTaskSpacePathOrientationOnlyCallback(const SetKinematicsPose::Request & req, SetKinematicsPose::Response & res)\n{\n  Eigen::Quaterniond q(req.kinematics_pose.pose.orientation.w,\n                        req.kinematics_pose.pose.orientation.x,\n                        req.kinematics_pose.pose.orientation.y,\n                        req.kinematics_pose.pose.orientation.z);\n  Eigen::Matrix3d orientation = math::convertQuaternionToRotationMatrix(q);\n\n  open_manipulator.makeTaskTrajectory(req.end_effector_name, orientation, req.path_time);\n\n  res.is_planned = true;\n}\n\n/*******************************************************************************\n* Service server (set trajectory using joint angle values form present values)\n*******************************************************************************/\nvoid goalJointSpacePathFromPresentCallback(const SetJointPosition::Request & req, SetJointPosition::Response & res)\n{\n  std::vector <double> target_angle;\n  for(int i = 0; i < req.joint_position.joint_name_length; i ++)\n    target_angle.push_back(req.joint_position.position[i]);\n\n  open_manipulator.makeJointTrajectoryFromPresentPosition(target_angle, req.path_time);\n\n  res.is_planned = true;\n}\n\n/*******************************************************************************\n* Service server (set trajectory using kinematic pose value from present value)\n*******************************************************************************/\nvoid goalTaskSpacePathFromPresentCallback(const SetKinematicsPose::Request & req, SetKinematicsPose::Response & res)\n{\n  KinematicPose target_pose;\n  target_pose.position[0] = req.kinematics_pose.pose.position.x;\n  target_pose.position[1] = req.kinematics_pose.pose.position.y;\n  target_pose.position[2] = req.kinematics_pose.pose.position.z;\n\n  Eigen::Quaterniond q(req.kinematics_pose.pose.orientation.w,\n                       req.kinematics_pose.pose.orientation.x,\n                       req.kinematics_pose.pose.orientation.y,\n                       req.kinematics_pose.pose.orientation.z);\n  target_pose.orientation = math::convertQuaternionToRotationMatrix(q);\n\n  open_manipulator.makeTaskTrajectoryFromPresentPose(req.planning_group, target_pose, req.path_time);\n\n  res.is_planned = true;\n}\n\n/*******************************************************************************\n* Service server (set trajectory using kinematic position value from present value)\n*******************************************************************************/\nvoid goalTaskSpacePathFromPresentPositionOnlyCallback(const SetKinematicsPose::Request & req, SetKinematicsPose::Response & res)\n{\n  Eigen::Vector3d position;\n  position[0] = req.kinematics_pose.pose.position.x;\n  position[1] = req.kinematics_pose.pose.position.y;\n  position[2] = req.kinematics_pose.pose.position.z;\n\n  open_manipulator.makeTaskTrajectoryFromPresentPose(req.planning_group, position, req.path_time);\n\n  res.is_planned = true;\n}\n\n/*******************************************************************************\n* Service server (set trajectory using kinematic oreintation value from present value)\n*******************************************************************************/\nvoid goalTaskSpacePathFromPresentOrientationOnlyCallback(const SetKinematicsPose::Request & req, SetKinematicsPose::Response & res)\n{\n  Eigen::Quaterniond q(req.kinematics_pose.pose.orientation.w,\n                        req.kinematics_pose.pose.orientation.x,\n                        req.kinematics_pose.pose.orientation.y,\n                        req.kinematics_pose.pose.orientation.z);\n  Eigen::Matrix3d orientation = math::convertQuaternionToRotationMatrix(q);\n\n  open_manipulator.makeTaskTrajectoryFromPresentPose(req.planning_group, orientation, req.path_time);\n\n  res.is_planned = true;\n}\n\n/*******************************************************************************\n* Service server (set tool control)\n*******************************************************************************/\nvoid goalToolControlCallback(const SetJointPosition::Request & req, SetJointPosition::Response & res)\n{\n  for(int i = 0; i < req.joint_position.joint_name_length; i ++)\n  {\n    open_manipulator.makeToolTrajectory(req.joint_position.joint_name[i], req.joint_position.position[i]);\n  }\n\n  res.is_planned = true;\n}\n\n/*******************************************************************************\n* Service server (set actuator state)\n*******************************************************************************/\nvoid setActuatorStateCallback(const SetActuatorState::Request & req, SetActuatorState::Response & res)\n{\n  if(req.set_actuator_state == true) // torque on\n    open_manipulator.enableAllActuator();\n  else // torque off\n    open_manipulator.disableAllActuator();\n\n  res.is_planned = true;\n}\n\n/*******************************************************************************\n* Service server (set drawing trajectory)\n*******************************************************************************/\nvoid goalDrawingTrajectoryCallBack(const SetDrawingTrajectory::Request & req, SetDrawingTrajectory::Response & res)\n{\n  STRING trajectory_name (req.drawing_trajectory_name);\n\n  if(trajectory_name == \"circle\")\n  {\n    double draw_circle_arg[3];\n    draw_circle_arg[0] = req.param[0];  // radius (m)\n    draw_circle_arg[1] = req.param[1];  // revolution (rev)\n    draw_circle_arg[2] = req.param[2];  // start angle position (rad)\n    void* p_draw_circle_arg = &draw_circle_arg;\n\n    open_manipulator.makeCustomTrajectory(CUSTOM_TRAJECTORY_CIRCLE, req.end_effector_name, p_draw_circle_arg, req.path_time);\n  }\n  else if(trajectory_name == \"line\")\n  {\n    TaskWaypoint draw_line_arg;\n    draw_line_arg.kinematic.position(0) = req.param[0]; // x axis (m)\n    draw_line_arg.kinematic.position(1) = req.param[1]; // y axis (m)\n    draw_line_arg.kinematic.position(2) = req.param[2]; // z axis (m)\n    void *p_draw_line_arg = &draw_line_arg;\n\n    open_manipulator.makeCustomTrajectory(CUSTOM_TRAJECTORY_LINE, req.end_effector_name, p_draw_line_arg, req.path_time);\n  }\n  else if(trajectory_name == \"rhombus\")\n  {\n    double draw_rhombus_arg[3];\n    draw_rhombus_arg[0] = req.param[0];  // radius (m)\n    draw_rhombus_arg[1] = req.param[1];  // revolution (rev)\n    draw_rhombus_arg[2] = req.param[2];  // start angle position (rad)\n    void* p_draw_rhombus_arg = &draw_rhombus_arg;\n\n    open_manipulator.makeCustomTrajectory(CUSTOM_TRAJECTORY_RHOMBUS, req.end_effector_name, p_draw_rhombus_arg, req.path_time);\n  }\n  else if(trajectory_name == \"heart\")\n  {\n    double draw_heart_arg[3];\n    draw_heart_arg[0] = req.param[0];  // radius (m)\n    draw_heart_arg[1] = req.param[1];  // revolution (rev)\n    draw_heart_arg[2] = req.param[2];  // start angle position (rad)\n    void* p_draw_heart_arg = &draw_heart_arg;\n\n    open_manipulator.makeCustomTrajectory(CUSTOM_TRAJECTORY_HEART, req.end_effector_name, p_draw_heart_arg, req.path_time);\n  }\n  res.is_planned = true;\n}\n\n/*******************************************************************************\n* Publish msgs (joint states)\n*******************************************************************************/\nvoid publishJointStates(void)\n{\n  auto joints_name = open_manipulator.getManipulator()->getAllActiveJointComponentName();\n  auto tool_name = open_manipulator.getManipulator()->getAllToolComponentName();\n\n  auto joint_value = open_manipulator.getAllActiveJointValue();\n  auto tool_value = open_manipulator.getAllToolValue();\n\n  joint_states_msg.name_length = joints_name.size()+tool_name.size();\n  joint_states_msg.position_length = joints_name.size()+tool_name.size();\n  joint_states_msg.velocity_length = joints_name.size()+tool_name.size();\n  joint_states_msg.effort_length = joints_name.size()+tool_name.size();\n\n  char* pub_joint_name[joints_name.size()+tool_name.size()];\n  float pub_joint_position[joints_name.size()+tool_name.size()] = {0.0, };\n  float pub_joint_velocity[joints_name.size()+tool_name.size()] = {0.0, };\n  float pub_joint_effort[joints_name.size()+tool_name.size()] = {0.0, };\n  \n  for(uint8_t i = 0; i < joints_name.size(); i ++)\n  {\n    pub_joint_name[i] = const_cast<char*>(joints_name[i].c_str());\n    pub_joint_position[i] = (float)joint_value[i].position;\n    pub_joint_velocity[i] = (float)joint_value[i].velocity;\n    pub_joint_effort[i] = (float)joint_value[i].effort;\n  }\n\n  for(uint8_t i = joints_name.size(); i < joints_name.size()+tool_name.size(); i ++)\n  {\n    pub_joint_name[i] = const_cast<char*>(tool_name[i-joints_name.size()].c_str());\n    pub_joint_position[i] = tool_value[i-joints_name.size()].position;\n    pub_joint_velocity[i] = 0.0f;\n    pub_joint_effort[i] = 0.0f;\n  }\n\n  joint_states_msg.header.stamp = nh.now();\n  joint_states_msg.name = pub_joint_name;\n  joint_states_msg.position = pub_joint_position;\n  joint_states_msg.velocity = pub_joint_velocity;\n  joint_states_msg.effort = pub_joint_effort;\n\n  joint_states_pub.publish(&joint_states_msg);\n}\n\n/*******************************************************************************\n* Publish msgs (kinematic pose)\n*******************************************************************************/\nvoid publishKinematicPose(void)\n{\n  auto opm_tools_name = open_manipulator.getManipulator()->getAllToolComponentName();\n\n  KinematicPose pose = open_manipulator.getKinematicPose(\"gripper\");\n  kinematic_pose_msg.pose.position.x = pose.position[0];\n  kinematic_pose_msg.pose.position.y = pose.position[1];\n  kinematic_pose_msg.pose.position.z = pose.position[2];\n  Eigen::Quaterniond orientation = math::convertRotationMatrixToQuaternion(pose.orientation);\n  kinematic_pose_msg.pose.orientation.w = orientation.w();\n  kinematic_pose_msg.pose.orientation.x = orientation.x();\n  kinematic_pose_msg.pose.orientation.y = orientation.y();\n  kinematic_pose_msg.pose.orientation.z = orientation.z();\n\n  kinematic_pose_pub.publish(&kinematic_pose_msg);\n}\n/*******************************************************************************\n* Publish msgs (openmanipulator states)\n*******************************************************************************/\nvoid publishOpenManipulatorStates(void)\n{\n  if(open_manipulator.getMovingState())\n    open_manipulator_states_msg.open_manipulator_moving_state = open_manipulator_states_msg.IS_MOVING;\n  else\n    open_manipulator_states_msg.open_manipulator_moving_state = open_manipulator_states_msg.STOPPED;\n\n  if(open_manipulator.getActuatorEnabledState(JOINT_DYNAMIXEL))\n    open_manipulator_states_msg.open_manipulator_actuator_state = open_manipulator_states_msg.ACTUATOR_ENABLED;\n  else\n    open_manipulator_states_msg.open_manipulator_actuator_state = open_manipulator_states_msg.ACTUATOR_DISABLED;\n\n  open_manipulator_states_pub.publish(&open_manipulator_states_msg);\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Chain/open_manipulator_chain_pen/open_manipulator_chain_pen.ino",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include \"open_manipulator_pen.h\"\n#include \"open_manipulator_pen_motion.h\"\n#include \"processing.h\"\n\nOpenManipulatorPen open_manipulator;\ndouble control_time = 0.010f;\ndouble present_time = 0.0;\ndouble previous_time = 0.0;\nbool platform_state = true;\n\nvoid setup()\n{\n  Serial.begin(57600);\n  DEBUG.begin(57600);\n\n  connectProcessing(platform_state);\n  switchInit();\n\n  open_manipulator.initOpenManipulator(platform_state);\n  log::println(\"OpenManipulatorPen Debugging Port\");\n}\n\nvoid loop()\n{\n  present_time = (float)(millis()/1000.0f);\n  getData(100);\n  switchRead(&open_manipulator);\n  playMotion(&open_manipulator);  \n  playProcessingMotion(&open_manipulator);\n\n  if(present_time-previous_time >= control_time)\n  {\n    open_manipulator.processOpenManipulator(millis()/1000.0);\n    previous_time = (float)(millis()/1000.0f);\n    sendValueToProcessing(&open_manipulator);\n  }\n}\n\nvoid getData(uint32_t wait_time)\n{\n  static uint8_t state = 0;\n  static uint32_t tick = 0;\n\n  bool processing_state = false;\n  String get_processing_data = \"\";\n\n  if (availableProcessing())\n  {\n    get_processing_data = readProcessingData();\n    processing_state = true;\n  }\n\n  switch (state)\n  {\n    case 0:\n      if (processing_state)\n      {\n        fromProcessing(&open_manipulator, get_processing_data);\n        tick = millis();\n        state = 1;\n      }\n     break;\n    case 1:\n      if ((millis() - tick) >= wait_time)\n      {\n        state = 0;\n      }\n     break;\n\n    default:\n      state = 0;\n     break;\n  }\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Chain/open_manipulator_chain_pen/open_manipulator_pen.h",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef OPEN_MANIPULATOR_PEN_H_\n#define OPEN_MANIPULATOR_PEN_H_\n\n#include <open_manipulator_libs.h>\n#include \"open_manipulator_pen_drawing.h\"\n\n#define CUSTOM_TRAJECTORY_SIZE 5\n#define CUSTOM_TRAJECTORY_LINE    \"custom_trajectory_line\"\n#define CUSTOM_TRAJECTORY_CIRCLE  \"custom_trajectory_circle\"\n#define CUSTOM_TRAJECTORY_RHOMBUS \"custom_trajectory_rhombus\"\n#define CUSTOM_TRAJECTORY_HEART   \"custom_trajectory_heart\"\n#define DRAWING_ALPHABET          \"drawing_alphabet\"\n\n#define JOINT_DYNAMIXEL \"joint_dxl\"\n\n#define X_AXIS robotis_manipulator::math::vector3(1.0, 0.0, 0.0)\n#define Y_AXIS robotis_manipulator::math::vector3(0.0, 1.0, 0.0)\n#define Z_AXIS robotis_manipulator::math::vector3(0.0, 0.0, 1.0)\n\nclass OpenManipulatorPen : public robotis_manipulator::RobotisManipulator\n{\nprivate:\n  robotis_manipulator::Kinematics *kinematics_;\n  robotis_manipulator::JointActuator *actuator_;\n  robotis_manipulator::ToolActuator *tool_;\n  robotis_manipulator::CustomTaskTrajectory *custom_trajectory_[CUSTOM_TRAJECTORY_SIZE];\n\n public:\n  OpenManipulatorPen() {}\n  virtual ~OpenManipulatorPen() {\n    delete kinematics_;\n    delete actuator_;\n    delete tool_;\n    for(uint8_t index = 0; index < CUSTOM_TRAJECTORY_SIZE; index++)\n      delete custom_trajectory_[index];\n  }\n\n  void initOpenManipulator(bool using_actual_robot_state, STRING usb_port = \"/dev/ttyUSB0\", STRING baud_rate = \"1000000\", float control_loop_time = 0.010)\n  {\n\t/*****************************************************************************\n\t ** Initialize Manipulator Parameter \n\t*****************************************************************************/\n\taddWorld(\"world\",   // world name\n\t\t\t\t\t\"joint1\"); // child name\n\n\taddJoint(\"joint1\",  // my name\n\t\t\t\t\t\"world\",   // parent name\n\t\t\t\t\t\"joint2\",  // child name\n\t\t\t\t\tmath::vector3(0.012, 0.0, 0.017),               // relative position\n\t\t\t\t\tmath::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // relative orientation\n\t\t\t\t\tZ_AXIS,    // axis of rotation\n\t\t\t\t\t11,        // actuator id\n\t\t\t\t\tM_PI,      // max joint limit (3.14 rad)\n\t\t\t\t\t-M_PI);    // min joint limit (-3.14 rad)\n\n\taddJoint(\"joint2\",  // my name\n\t\t\t\t\t\"joint1\",  // parent name\n\t\t\t\t\t\"joint3\",  // child name\n\t\t\t\t\tmath::vector3(0.0, 0.0, 0.0595),                // relative position\n\t\t\t\t\tmath::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // relative orientation\n\t\t\t\t\tY_AXIS,    // axis of rotation\n\t\t\t\t\t12,        // actuator id\n\t\t\t\t\tM_PI_2,    // max joint limit (1.67 rad)\n\t\t\t\t\t-2.05);    // min joint limit (-2.05 rad)\n\n\taddJoint(\"joint3\",  // my name\n\t\t\t\t\t\"joint2\",  // parent name\n\t\t\t\t\t\"joint4\",  // child name\n\t\t\t\t\tmath::vector3(0.024, 0.0, 0.128),               // relative position\n\t\t\t\t\tmath::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // relative orientation\n\t\t\t\t\tY_AXIS,    // axis of rotation\n\t\t\t\t\t13,        // actuator id\n\t\t\t\t\t1.53,      // max joint limit (1.53 rad)\n\t\t\t\t\t-M_PI_2);  // min joint limit (-1.67 rad)\n\n\taddJoint(\"joint4\",  // my name\n\t\t\t\t\t\"joint3\",  // parent name\n\t\t\t\t\t\"pen\", // child name\n\t\t\t\t\tmath::vector3(0.124, 0.0, 0.0),                 // relative position\n\t\t\t\t\tmath::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // relative orientation\n\t\t\t\t\tY_AXIS,    // axis of rotation\n\t\t\t\t\t14,        // actuator id\n\t\t\t\t\t2.0,       // max joint limit (2.0 rad)\n\t\t\t\t\t-1.8);     // min joint limit (-1.8 rad)\n            \n\taddTool(\"pen\",   // my name\n\t\t\t\t\t\"joint4\", // parent name\n\t\t\t\t\tmath::vector3(0.043, 0.0, 0.0), // relative position\n\t\t\t\t\tmath::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // relative orientation\n\t\t\t\t\t-1); // actuator id\n\n  /*****************************************************************************\n  ** Initialize Kinematics \n  *****************************************************************************/\n  kinematics_ = new kinematics::SolverCustomizedforOMChain();\n//  kinematics_ = new kinematics::SolverUsingCRAndSRPositionOnlyJacobian();\n  addKinematics(kinematics_);\n\n    if(using_actual_robot_state)\n    {\n\t\t\t/*****************************************************************************\n\t\t\t** Initialize joint Actuator\n\t\t\t*****************************************************************************/\n\t\t\t// actuator_ = new dynamixel::JointDynamixel();\n\t\t\tactuator_ = new dynamixel::JointDynamixelProfileControl(control_loop_time);\n\n      // communication setting argument\n      STRING dxl_comm_arg[2] = {usb_port, baud_rate};\n      void *p_dxl_comm_arg = &dxl_comm_arg;\n\n      // set joint actuator id\n      std::vector<uint8_t> jointDxlId;\n      jointDxlId.push_back(11);\n      jointDxlId.push_back(12);\n      jointDxlId.push_back(13);\n      jointDxlId.push_back(14);\n      addJointActuator(JOINT_DYNAMIXEL, actuator_, jointDxlId, p_dxl_comm_arg);\n\n      // set joint actuator control mode\n      STRING joint_dxl_mode_arg = \"position_mode\";\n      void *p_joint_dxl_mode_arg = &joint_dxl_mode_arg;\n      setJointActuatorMode(JOINT_DYNAMIXEL, jointDxlId, p_joint_dxl_mode_arg);\n\n      // set joint actuator parameter\n      STRING joint_dxl_opt_arg[2] = {\"Position_P_Gain\", \"1200\"};\n      void *p_joint_dxl_opt_arg = &joint_dxl_opt_arg;\n      setJointActuatorMode(JOINT_DYNAMIXEL, jointDxlId, p_joint_dxl_opt_arg);\n\n      // all actuator enable\n      enableAllActuator();\n      receiveAllJointActuatorValue();\n    }\n\n\t\t/*****************************************************************************\n\t\t** Initialize Custom Trajectory\n\t\t*****************************************************************************/\n\t\tcustom_trajectory_[0] = new custom_trajectory::Line();\n\t\tcustom_trajectory_[1] = new custom_trajectory::Circle();\n\t\tcustom_trajectory_[2] = new custom_trajectory::Rhombus();\n\t\tcustom_trajectory_[3] = new custom_trajectory::Heart();\n\t\tcustom_trajectory_[4] = new open_manipulator_pen_drawing::Alphabet();\n\n\t\taddCustomTrajectory(CUSTOM_TRAJECTORY_LINE, custom_trajectory_[0]);\n\t\taddCustomTrajectory(CUSTOM_TRAJECTORY_CIRCLE, custom_trajectory_[1]);\n\t\taddCustomTrajectory(CUSTOM_TRAJECTORY_RHOMBUS, custom_trajectory_[2]);\n\t\taddCustomTrajectory(CUSTOM_TRAJECTORY_HEART, custom_trajectory_[3]);\n\t\taddCustomTrajectory(DRAWING_ALPHABET, custom_trajectory_[4]);\n\t\t\n  }\n\n  void processOpenManipulator(double present_time)\n  {\n    JointWaypoint goal_joint_value  = getJointGoalValueFromTrajectory(present_time);\n\n    receiveAllJointActuatorValue();\n    if(goal_joint_value.size() != 0) sendAllJointActuatorValue(goal_joint_value);\n    solveForwardKinematics();\n  }\n};\n\n#endif // OPEN_MANIPULATOR_PEN_H_\n\n\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Chain/open_manipulator_chain_pen/open_manipulator_pen_drawing.cpp",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include \"open_manipulator_pen_drawing.h\"\n\nusing namespace open_manipulator_pen_drawing;\n\nAlphabet::Alphabet() {}\nAlphabet::~Alphabet() {}\n\nvoid Alphabet::initAlphabet(double move_time, TaskWaypoint start, char alphabet, char scale)\n{\n  start_pose_ = start;\n  alphabet_ = alphabet;\n  move_time_ = move_time;\n  scale_ = (double)scale * 0.001 *0.5;\n\n  Point drawingStart, drawingGoal;\n\n  drawingStart.position = 0.0;\n  drawingStart.velocity = 0.0;\n  drawingStart.acceleration = 0.0;\n  drawingStart.effort = 0.0;\n\n  if(alphabet_ == 'B')  drawingGoal.position = 10.0; \n  else if(alphabet_ == 'R')  drawingGoal.position = 7.5; \n  else if(alphabet_ == 'O')  drawingGoal.position = 2.0; \n  else if(alphabet_ == 'T')  drawingGoal.position = 5.0; \n  else if(alphabet_ == 'I')  drawingGoal.position = 8.0; \n  else if(alphabet_ == 'S')  drawingGoal.position = 7.0; \n  else if(alphabet_ == 'C')  drawingGoal.position = 3.0; \n  else if(alphabet_ == '!')  \n  {\n    drawingGoal.position = 55.75; \n    scale_ *= 0.2;\n  }\n  else                      drawingGoal.position = 2.0; \n\n  drawingGoal.velocity = 0.0;\n  drawingGoal.acceleration = 0.0;\n  drawingGoal.effort = 0.0;\n\n  path_generator_.calcCoefficient(drawingStart, drawingGoal, move_time);\n  coefficient_ = path_generator_.getCoefficient();\n}\n\nTaskWaypoint Alphabet::drawAlphabet(double time_var)\n{\n  // get time variable\n  double get_time_var = 0.0;\n\n  get_time_var = coefficient_(0) +\n                 coefficient_(1) * pow(time_var, 1) +\n                 coefficient_(2) * pow(time_var, 2) +\n                 coefficient_(3) * pow(time_var, 3) +\n                 coefficient_(4) * pow(time_var, 4) +\n                 coefficient_(5) * pow(time_var, 5);\n\n  if(alphabet_ == 'B')      return drawing_B(get_time_var);\n  else if(alphabet_ == 'R') return drawing_R(get_time_var);\n  else if(alphabet_ == 'O') return drawing_O(get_time_var);\n  else if(alphabet_ == 'T') return drawing_T(get_time_var);\n  else if(alphabet_ == 'I') return drawing_I(get_time_var);\n  else if(alphabet_ == 'S') return drawing_S(get_time_var);\n  else if(alphabet_ == 'C') return drawing_C(get_time_var);\n  else if(alphabet_ == '!') return drawing_MM(get_time_var);\n  else return {};\n}\n\nvoid Alphabet::setOption(const void *arg){}\nvoid Alphabet::makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg)\n{\n  char *c_arg = (char *)arg;\n  initAlphabet(move_time, start, c_arg[0], c_arg[1]);\n}\nTaskWaypoint Alphabet::getTaskWaypoint(double tick){  return drawAlphabet(tick); }\n\nTaskWaypoint Alphabet::drawing_B(double t)\n{\n  // set drawing trajectory\n  TaskWaypoint pose;\n  double diff_pose[2] = {0.0, 0.0};\n  \n  if(t <= 2.0)\n  {\n    double x = t;         \n    diff_pose[0] = 0; // x\n    diff_pose[1] = x; // y\n  }\n  else if(t <= 3.5)\n  {\n    double x = t-2.0;\n    diff_pose[0] = x; // x\n    diff_pose[1] = 2.0; // y\n  }\n  else if(t <= 5.0) // up half circle\n  {\n    double x = (t - 3.5) * (3.14/1.5);\n    diff_pose[0] = 1.5 + 0.5 * sin(x);// x\n    diff_pose[1] = 1.5 + 0.5 * cos(x);// y\n  }\n  else if(t <= 6.0)\n  {\n    double x = 1.5 - (t-5.0);\n    diff_pose[0] = x; // x\n    diff_pose[1] = 1.0; // y\n  }\n  else if(t <= 7.0)\n  {\n    double x = (t-6.0) + 0.5;\n    diff_pose[0] = x; // x\n    diff_pose[1] = 1.0; // y\n  }\n  else if(t <= 8.5) // up half circle\n  {\n    double x = (t - 7.0) * (3.14/1.5);\n    diff_pose[0] = 1.5 + 0.5 * sin(x);// x\n    diff_pose[1] = 0.5 + 0.5 * cos(x);// y\n  }\n  else// if(t <= 10.0)\n  {\n    double x = 1.5 - (t-8.5);\n    diff_pose[0] = x; // x\n    diff_pose[1] = 0.0; // y\n  }\n\n  pose.kinematic.position[0] = start_pose_.kinematic.position[0] - diff_pose[1]*scale_;\n  pose.kinematic.position[1] = start_pose_.kinematic.position[1] + diff_pose[0]*scale_;\n  pose.kinematic.position[2] = start_pose_.kinematic.position[2];\n  pose.kinematic.orientation = start_pose_.kinematic.orientation;\n\n  return pose;\n}\n\nTaskWaypoint Alphabet::drawing_R(double t)\n{\n  // set drawing trajectory\n  TaskWaypoint pose;\n  double diff_pose[2] = {0.0, 0.0};\n\n  if(t <= 2.0)\n  {\n    double x = t;         \n    diff_pose[0] = 0; // x\n    diff_pose[1] = x; // y\n  }\n  else if(t <= 3.5)\n  {\n    double x = t-2.0;\n    diff_pose[0] = x; // x\n    diff_pose[1] = 2.0; // y\n  }\n  else if(t <= 5.0) // up half circle\n  {\n    double x = (t - 3.5) * (3.14/1.5);\n    diff_pose[0] = 1.5 + 0.5 * sin(x);// x\n    diff_pose[1] = 1.5 + 0.5 * cos(x);// y\n  }\n  else if(t <= 6.0)\n  {\n    double x = 1.5 - (t-5.0);\n    diff_pose[0] = x; // x\n    diff_pose[1] = 1.0; // y\n  }\n  else //if(t <= 7.5)\n  {\n    double x = (t-6.0) + 0.5;\n    diff_pose[0] = x; // x\n    diff_pose[1] = -(2.0/3.0)*x + 4.0/3.0; // y\n  }\n\n  pose.kinematic.position[0] = start_pose_.kinematic.position[0] - diff_pose[1]*scale_;\n  pose.kinematic.position[1] = start_pose_.kinematic.position[1] + diff_pose[0]*scale_;\n  pose.kinematic.position[2] = start_pose_.kinematic.position[2];\n  pose.kinematic.orientation = start_pose_.kinematic.orientation;\n\n  return pose;\n}\n\nTaskWaypoint Alphabet::drawing_C(double t)\n{\n  // set drawing trajectory\n  TaskWaypoint pose;\n  double diff_pose[2] = {0.0, 0.0};\n\n  double x = (t) * (9.0/4.0*PI/3.0);\n\n  if(x <= 3.0/4.0 * PI)\n  {\n    diff_pose[0] = 1.0 + cos(x + PI); // x\n    diff_pose[1] = sin(x); // y\n  }\n  else //if(t <= 3.0)\n  {\n    diff_pose[0] = 1.0 +sin(x); // x\n    diff_pose[1] = cos(x+PI); // y\n  }\n\n  pose.kinematic.position[0] = start_pose_.kinematic.position[0] - diff_pose[1]*scale_;\n  pose.kinematic.position[1] = start_pose_.kinematic.position[1] + diff_pose[0]*scale_;\n  pose.kinematic.position[2] = start_pose_.kinematic.position[2];\n  pose.kinematic.orientation = start_pose_.kinematic.orientation;\n\n  return pose;\n}\nTaskWaypoint Alphabet::drawing_O(double t)\n{\n  // set drawing trajectory\n  TaskWaypoint pose;\n  double diff_pose[2] = {0.0, 0.0};\n\n  double x = (t) * (6.28/2.0);\n  diff_pose[0] = 1.0 + 1.0 * cos(x+3.14);// y\n  diff_pose[1] = 1.0 * sin(x);// x\n\n  pose.kinematic.position[0] = start_pose_.kinematic.position[0] - diff_pose[1]*scale_;\n  pose.kinematic.position[1] = start_pose_.kinematic.position[1] + diff_pose[0]*scale_;\n  pose.kinematic.position[2] = start_pose_.kinematic.position[2];\n  pose.kinematic.orientation = start_pose_.kinematic.orientation;\n\n  return pose;\n}\n\nTaskWaypoint Alphabet::drawing_T(double t)\n{\n  // set drawing trajectory\n  TaskWaypoint pose;\n  double diff_pose[2] = {0.0, 0.0};\n\n  if(t <= 2.0)\n  {\n    double x = t;         \n    diff_pose[0] = 0; // x\n    diff_pose[1] = x; // y\n  }\n  else if(t <= 3.0)\n  {\n    double x = -(t-2.0);         \n    diff_pose[0] = x+0.1; // x\n    diff_pose[1] = 2.0; // y\n  }\n  else// if(t <= 4.0)\n  {\n    double x = -1.0 + (t-3.0);         \n    diff_pose[0] = x; // x\n    diff_pose[1] = 2.0; // y\n  }\n\n  pose.kinematic.position[0] = start_pose_.kinematic.position[0] - diff_pose[1]*scale_;\n  pose.kinematic.position[1] = start_pose_.kinematic.position[1] + diff_pose[0]*scale_;\n  pose.kinematic.position[2] = start_pose_.kinematic.position[2];\n  pose.kinematic.orientation = start_pose_.kinematic.orientation;\n  \n  return pose;\n}\n\nTaskWaypoint Alphabet::drawing_I(double t)\n{\n  // set drawing trajectory\n  TaskWaypoint pose;\n  double diff_pose[2] = {0.0, 0.0};\n\n  if(t <= 2.0)\n  {\n    double x = (t);         \n    diff_pose[0] = x; // x\n    diff_pose[1] = 0; // y\n  }\n  else if(t <= 3.0)\n  {\n    double x = 2.0 - (t-2.0);         \n    diff_pose[0] = x-0.2; // x\n    diff_pose[1] = 0; // y\n  }\n  else if(t <= 5.0)\n  {\n    double x = (t-3.0);         \n    diff_pose[0] = 1.0; // x\n    diff_pose[1] = x; // y\n  }\n  else if(t <= 6.0)\n  {\n    double x = 1.0 - (t-5.0);         \n    diff_pose[0] = x; // x\n    diff_pose[1] = 2.0; // y\n  }\n  else //if(t <= 8.0)\n  {\n    double x = (t-6.0);         \n    diff_pose[0] = x; // x\n    diff_pose[1] = 2.0; // y\n  }\n\n  pose.kinematic.position[0] = start_pose_.kinematic.position[0] - diff_pose[1]*scale_;\n  pose.kinematic.position[1] = start_pose_.kinematic.position[1] + diff_pose[0]*scale_;\n  pose.kinematic.position[2] = start_pose_.kinematic.position[2];\n  pose.kinematic.orientation = start_pose_.kinematic.orientation;\n\n  return pose;\n}\n\nTaskWaypoint Alphabet::drawing_S(double t)\n{\n  // set drawing trajectory\n  TaskWaypoint pose;\n  double diff_pose[2] = {0.0, 0.0};\n\n  if(t <= 1.5)\n  {\n    double x = t;         \n    diff_pose[0] = x; // x\n    diff_pose[1] = 0; // y\n  }\n  else if(t <= 3.0)\n  {\n    double x = (t - 1.5) * (3.14/1.5);\n    diff_pose[0] = 1.5 + 0.5 * sin(x);// x\n    diff_pose[1] = 0.5 + 0.5 * cos(x + PI);// y\n  }\n  else if(t <= 4.0) \n  {\n    double x = 1.5 - (t - 3.0);\n    diff_pose[0] = x;// x\n    diff_pose[1] = 1.0;// y\n  }\n  else if(t <= 5.5)\n  {\n    double x = (t - 4.0) * (3.14/1.5);\n    diff_pose[0] = 0.5 + 0.5 * sin(x+ PI);// x\n    diff_pose[1] = 1.5 + 0.5 * cos(x+ PI);// y\n  }\n  else// if(t <= 7.0)\n  {\n    double x = 0.5 + (t-5.5);\n    diff_pose[0] = x; // x\n    diff_pose[1] = 2.0; // y\n  }\n\n  pose.kinematic.position[0] = start_pose_.kinematic.position[0] - diff_pose[1]*scale_;\n  pose.kinematic.position[1] = start_pose_.kinematic.position[1] + diff_pose[0]*scale_;\n  pose.kinematic.position[2] = start_pose_.kinematic.position[2];\n  pose.kinematic.orientation = start_pose_.kinematic.orientation;\n  \n  return pose;\n}\n\nTaskWaypoint Alphabet::drawing_MM(double t)\n{\n  // set drawing trajectory\n  TaskWaypoint pose;\n  double diff_pose[2] = {0.0, 0.0};\n  \n  if(t <= 1.134)\n  {\n    double x = t;         \n    diff_pose[0] = x; // x\n    diff_pose[1] = 0; // y\n  }\n  else if(t <= 5.0)\n  {\n    double x = (t - 1.134) * ((8.0/3.0)*PI/3.866);\n    diff_pose[0] = 2.0 + 1 * sin(-x - 2.0/3.0*PI);// x\n    diff_pose[1] = 0.5 + 1 * cos(-x - 2.0/3.0*PI);// y\n  }\n  else if(t <= 10.634)\n  {\n    double x = 2.866 + (t-5.0);\n    diff_pose[0] = x; // x\n    diff_pose[1] = 0; // y\n  }\n  else if(t <= 12.0)\n  {\n    double x = (t - 10.634) * ((PI)/1.366);\n    diff_pose[0] = 9.0 + 0.5 * cos(x+PI);// x\n    diff_pose[1] = 0.0 + 0.5 * sin(x+PI);// y\n  }\n  else if(t <= 12.5) \n  {\n    double x = 9.5 + (t-12.0);\n    diff_pose[0] = x; // x\n    diff_pose[1] = 0; // y\n  }\n  else if(t <= 15.5) \n  {\n    double x = (t-12.5);\n    diff_pose[0] = 10.0; // x\n    diff_pose[1] = x; // y\n  }\n  else if(t <= 18.5) \n  {\n    double x = 10.0 - (t-15.5);\n    diff_pose[0] = x; // x\n    diff_pose[1] = 3.0; // y\n  }\n  else if(t <= 19.5) \n  {\n    double x = (t-18.5);\n    diff_pose[0] = 7.0; // x\n    diff_pose[1] = x + 3.0; // y\n  }\n  else if(t <= 20.5) \n  {\n    double x = 7.0 - (t-19.5);\n    diff_pose[0] = x; // x\n    diff_pose[1] = 4.0; // y\n  }\n  else if(t <= 21.0) \n  {\n    double x = (t-20.5) + 4.0;\n    diff_pose[0] = 6.0; // x\n    diff_pose[1] = x; // y\n  }\n  else if(t <= 23.5) // 2.5 \n  {\n    double x = (t-21.0) + 6.0;\n    diff_pose[0] = x; // x\n    diff_pose[1] = x - 1.5; // y\n  }\n  else if(t <= 24.25) // 0.75 \n  {\n    double x = 8.5 - (t-23.5);\n    diff_pose[0] = x; // x\n    diff_pose[1] = -x+15.5 ; // y\n  }\n  else if(t <= 24.5) // 0.25 \n  {\n    double x = 7.75 - (t-24.25);\n    diff_pose[0] = x; // x\n    diff_pose[1] = x; // y\n  }\n  else if(t <= 27.5) // 3.0\n  {\n    double x = 7.5 - (t-24.5);\n    diff_pose[0] = x; // x\n    diff_pose[1] = -0.5*x+11.25 ; // y\n  }\n  else if(t <= 28.25) // 0.75 \n  {\n    double x = (t-27.5)+9.0; \n    diff_pose[0] = 4.5; // x\n    diff_pose[1] = x ; // y\n  }\n  else if(t <= 28.75) // 0.5\n  {\n    double x = 4.5 - (t-28.25); \n    diff_pose[0] = x; // x\n    diff_pose[1] = 9.75 ; // y\n  }\n  else if(t <= 29.0) // 0.25 \n  {\n    double x = (t-28.75)+9.75; \n    diff_pose[0] = 4.0; // x\n    diff_pose[1] = x ; // y\n  }\n  else if(t <= 30.0) // 1.0 top\n  {\n    double x = 4.0 - (t-29.0); \n    diff_pose[0] = x; // x\n    diff_pose[1] = 10.0; // y\n  }\n  else if(t <= 30.5) // 0.5 \n  {\n    double x = 10.0 - (t-30.0); \n    diff_pose[0] = 3.0; // x\n    diff_pose[1] = x ; // y\n  }\n  else if(t <= 31.0) // 0.5 \n  {\n    double x = 3.0 - (t-30.5); \n    diff_pose[0] = x; // x\n    diff_pose[1] = 9.5 ; // y\n  }\n  else if(t <= 31.25) // 0.25 \n  {\n    double x = 9.5 - (t-31.0); \n    diff_pose[0] = 2.5; // x\n    diff_pose[1] = x ; // y\n  }\n  else if(t <= 31.75) // 0.5 \n  {\n    double x = 2.5 - (t-31.25); \n    diff_pose[0] = x; // x\n    diff_pose[1] = 9.25 ; // y\n  }\n  else if(t <= 33.25) // 1.5 \n  {\n    double x = 2.0 - (t-31.75); \n    diff_pose[0] = x; // x\n    diff_pose[1] = 0.25/1.5*x + (9-(0.25*0.5/1.5)); // y\n  }\n  else if(t <= 34.0) // 0.75 gripper\n  {\n    double x = 9.0 - (t-33.25); \n    diff_pose[0] = 0.5; // x\n    diff_pose[1] = x; // y\n  }\n  else if(t <= 35.5) // 1.5\n  {\n    double x = (t-34.0) + 0.5; \n    diff_pose[0] = x; // x\n    diff_pose[1] = -0.25/1.5*x + (8.25 + (0.25*0.5/1.5)); // y\n  }\n  else if(t <= 36.0) // 0.5\n  {\n    double x = (t-35.5) + 2.0; \n    diff_pose[0] = x; // x\n    diff_pose[1] = 8.0; // y\n  }\n  else if(t <= 36.25) // 0.25\n  {\n    double x = 8.0 - (t-36.0); \n    diff_pose[0] = 2.5; // x\n    diff_pose[1] = x; // y\n  }\n  else if(t <= 36.75) // 0.5\n  {\n    double x = 2.5 + (t-36.25); \n    diff_pose[0] = x; // x\n    diff_pose[1] = 7.75; // y\n  }\n  else if(t <= 37.75) // 1.0\n  {\n    double x = (t-36.75) + 3.0; \n    diff_pose[0] = x; // x\n    diff_pose[1] = 0.25*x + (7.0); // y\n  }\n  else if(t <= 38.25) // 0.5\n  {\n    double x = (t-37.75) + 4.0; \n    diff_pose[0] = x; // x\n    diff_pose[1] = 8.0; // y\n  }\n  else if(t <= 40.75) // 1.5\n  {\n    double x = (t-38.25) + 4.5; \n    diff_pose[0] = x; // x\n    diff_pose[1] = -0.5*x + (8.0 + (0.5*4.5)); // y\n  }\n  else if(t <= 41.0) // 0.25\n  {\n    double x = 6.75 - (t-40.75); \n    diff_pose[0] = 7.0; // x\n    diff_pose[1] = x; // y\n  }\n  else if(t <= 42.75) // 1.75\n  {\n    double x = 7.0 - (t-41.0); \n    diff_pose[0] = x; // x\n    diff_pose[1] = x-0.5; // y\n  }\n  else if(t <= 43.0) // 0.25\n  {\n    double x = 5.25 - (t-42.75); \n    diff_pose[0] = x; // x\n    diff_pose[1] = 4.75; // y\n  }\n  else if(t <= 44.75) // 1.75\n  {\n    double x = 4.75 - (t-43.00); \n    diff_pose[0] = 5.0; // x\n    diff_pose[1] = x; // y\n  }\n  else if(t <= 45.25) // 0.5\n  {\n    double x = 5.0 - (t-44.75); \n    diff_pose[0] = x; // x\n    diff_pose[1] = 3.0; // y\n  }\n  else if(t <= 46.25) // 1.0\n  {\n    double x = (t-45.25) + 3.0; \n    diff_pose[0] = 4.5; // x\n    diff_pose[1] = x; // y\n  }\n  else if(t <= 48.25) // 2.0\n  {\n    double x = 4.5 - (t-46.25); \n    diff_pose[0] = x; // x\n    diff_pose[1] = 4.0; // y\n  }\n  else if(t <= 48.75) // 0.5\n  {\n    double x = 4.0 - (t-48.25); \n    diff_pose[0] = 2.5; // x\n    diff_pose[1] = x; // y\n  }\n  else if(t <= 49.75) // 1.0\n  {\n    double x = 2.5 - (t-48.75); \n    diff_pose[0] = x; // x\n    diff_pose[1] = 3.5; // y\n  }\n  else if(t <= 50.25) // 0.5\n  {\n    double x = 3.5 - (t-49.75); \n    diff_pose[0] = 1.5; // x\n    diff_pose[1] = x; // y\n  }\n  else if(t <= 51.5) // 1.25\n  {\n    double x = 1.5 - (t-50.25); \n    diff_pose[0] = x; // x\n    diff_pose[1] = 3.0; // y\n  }\n  else if(t <= 52.0) // 0.5\n  {\n    double x = (t-51.5) + 3.0; \n    diff_pose[0] = 0.25; // x\n    diff_pose[1] = x; // y\n  }\n  else if(t <= 52.25) // 0.25\n  {\n    double x = 0.25 - (t-52.0); \n    diff_pose[0] = x; // x\n    diff_pose[1] = 3.5; // y\n  }\n  else// if(t <= 55.75) // 3.5\n  {\n    double x = 3.5 - (t-52.25); \n    diff_pose[0] = 0.0; // x\n    diff_pose[1] = x; // y\n  }\n\n  pose.kinematic.position[0] = start_pose_.kinematic.position[0] - diff_pose[1]*scale_;\n  pose.kinematic.position[1] = start_pose_.kinematic.position[1] + diff_pose[0]*scale_;\n  pose.kinematic.position[2] = start_pose_.kinematic.position[2];\n  pose.kinematic.orientation = start_pose_.kinematic.orientation;\n  \n  return pose;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Chain/open_manipulator_chain_pen/open_manipulator_pen_drawing.h",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef OPEN_MANIPULATOR_PEN_DRAWING_H_\n#define OPEN_MANIPULATOR_PEN_DRAWING_H_\n\n#include <RobotisManipulator.h>\n\nusing namespace robotis_manipulator;\nusing namespace Eigen;\n\nnamespace open_manipulator_pen_drawing\n{\n//-------------------- Alphabet --------------------//\n\nclass Alphabet : public CustomTaskTrajectory\n{\nprivate:\n  MinimumJerk path_generator_;\n  VectorXd coefficient_;\n\n  TaskWaypoint start_pose_;\n  TaskWaypoint goal_pose_;\n\n  char alphabet_;\n  double move_time_;\n  double scale_;\n\npublic:\n  Alphabet();\n  virtual ~Alphabet();\n\n  void initAlphabet(double move_time, TaskWaypoint start, char alphabet, char scale);\n  TaskWaypoint drawAlphabet(double time_var);\n  TaskWaypoint drawing_B(double t);\n  TaskWaypoint drawing_R(double t);\n  TaskWaypoint drawing_C(double t);\n  TaskWaypoint drawing_O(double t);\n  TaskWaypoint drawing_T(double t);\n  TaskWaypoint drawing_I(double t);\n  TaskWaypoint drawing_S(double t);\n  TaskWaypoint drawing_MM(double t);\n  \n  virtual void setOption(const void *arg);\n  virtual void makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg);\n  virtual TaskWaypoint getTaskWaypoint(double tick);\n};\n\n} // namespace open_manipulator_pen_drawing\n#endif // OPEN_MANIPULATOR_PEN_DRAWING_H_\n\n\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Chain/open_manipulator_chain_pen/open_manipulator_pen_motion.h",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef OPEN_MANIPULATOR_PEN_MOTION_H_\n#define OPEN_MANIPULATOR_PEN_MOTION_H_\n\n#include <RobotisManipulator.h>\n#include \"open_manipulator_pen.h\"\n\n#define BDPIN_PUSH_SW_1         34\n#define BDPIN_PUSH_SW_2         35\n\n#define PEN_DEPTH  0.0436\n\nbool demo_motion_state = false;\nint  demo_motion_type = 0;\nchar demo_motion_cnt = 0;\n\nvoid demo_motion_robotis_mm(OpenManipulatorPen *open_manipulator, int cnt)\n{\n  std::vector<double> goal_joint_position;\n  char draw_alphabet_arg[1];\n  void* p_draw_alphabet_arg = &draw_alphabet_arg;\n  Eigen::Vector3d goal_pose;\n\n  Eigen::Vector3d robotis_start_position(0.147, -0.07, PEN_DEPTH);\n  Eigen::Vector3d mm_start_position(0.280, -0.06, PEN_DEPTH);\n  Eigen::Vector3d ict_start_position(0.220, -0.06, PEN_DEPTH);\n  \n  switch(cnt) \n  {\n    case 0: // home\n      goal_joint_position.push_back( 0.00);\n      goal_joint_position.push_back(-1.05);\n      goal_joint_position.push_back( 0.35);\n      goal_joint_position.push_back( 0.69);\n      open_manipulator->makeJointTrajectory(goal_joint_position, 1.0); \n    break;\n    case 1: // init\n      goal_joint_position.push_back( 0.00);\n      goal_joint_position.push_back( 0.00);\n      goal_joint_position.push_back( 0.00);\n      goal_joint_position.push_back( 0.00);\n      open_manipulator->makeJointTrajectory(goal_joint_position, 1.0); \n    break;\n\n    case 2: // R start pose 0, 0\n      goal_pose = robotis_start_position;\n      goal_pose(2) += 0.01;\n      open_manipulator->makeTaskTrajectory(\"pen\", goal_pose, 1.0);\n    break;\n    case 3: // z down\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, -0.010), 0.5);\n    break;\n    case 4: // drawing R\n      draw_alphabet_arg[0] = 'R'; // drawing alphabet\n      draw_alphabet_arg[1] = 20; // drawing scale 2cm\n      open_manipulator->makeCustomTrajectory(DRAWING_ALPHABET, \"pen\", p_draw_alphabet_arg, 5.0);\n    break;\n    case 5: // z up\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, 0.010), 0.5);\n    break;\n\n    case 6: // O start pose 0, 1\n      goal_pose = robotis_start_position;\n      goal_pose(0) -=0.010;\n      goal_pose(1) +=0.02; \n      goal_pose(2) +=0.01;\n      open_manipulator->makeTaskTrajectory(\"pen\", goal_pose, 1.0);\n    break;\n    case 7: // z down\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, -0.010), 0.5);\n    break;\n    case 8: // drawing O\n      draw_alphabet_arg[0] = 'O'; // drawing alphabet\n      draw_alphabet_arg[1] = 20; // drawing scale 2cm\n      open_manipulator->makeCustomTrajectory(DRAWING_ALPHABET, \"pen\", p_draw_alphabet_arg, 5.0);\n    break;\n    case 9: // z up\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, 0.010), 0.5);\n    break;\n\n    case 10: // B start pose 0, 0\n      goal_pose = robotis_start_position;\n      goal_pose(0) -=0.00;\n      goal_pose(1) +=0.04; \n      goal_pose(2) +=0.01;\n      open_manipulator->makeTaskTrajectory(\"pen\", goal_pose, 1.0);\n    break;\n    case 11: // z down\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, -0.010), 0.5);\n    break;\n    case 12: // drawing O\n      draw_alphabet_arg[0] = 'B'; // drawing alphabet\n      draw_alphabet_arg[1] = 20; // drawing scale 2cm\n      open_manipulator->makeCustomTrajectory(DRAWING_ALPHABET, \"pen\", p_draw_alphabet_arg, 5.0);\n    break;\n    case 13: // z up\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, 0.010), 0.5);\n    break;\n\n    case 14: // O start pose 0, 1\n      goal_pose = robotis_start_position;\n      goal_pose(0) -=0.01;\n      goal_pose(1) +=0.06; \n      goal_pose(2) +=0.01;\n      open_manipulator->makeTaskTrajectory(\"pen\", goal_pose, 1.0);\n    break;\n    case 15: // z down\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, -0.010), 0.5);\n    break;\n    case 16: // drawing O\n      draw_alphabet_arg[0] = 'O'; // drawing alphabet\n      draw_alphabet_arg[1] = 20; // drawing scale 2cm\n      open_manipulator->makeCustomTrajectory(DRAWING_ALPHABET, \"pen\", p_draw_alphabet_arg, 5.0);\n    break;\n    case 17: // z up\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, 0.010), 0.5);\n    break;\n\n    case 18: // T start pose 1, 0\n      goal_pose = robotis_start_position;\n      goal_pose(0) -=0.0;\n      goal_pose(1) +=0.09 - 0.001; \n      goal_pose(2) +=0.01;\n      open_manipulator->makeTaskTrajectory(\"pen\", goal_pose, 1.0);\n    break;\n    case 19: // z down\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, -0.010), 0.5);\n    break;\n    case 20: // drawing O\n      draw_alphabet_arg[0] = 'T'; // drawing alphabet\n      draw_alphabet_arg[1] = 20; // drawing scale 2cm\n      open_manipulator->makeCustomTrajectory(DRAWING_ALPHABET, \"pen\", p_draw_alphabet_arg, 5.0);\n    break;\n    case 21: // z up\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, 0.010), 0.5);\n    break;\n\n    case 22: // I start pose 0, 0\n      goal_pose = robotis_start_position;\n      goal_pose(0) -=0.0;\n      goal_pose(1) +=0.10 - 0.001;  \n      goal_pose(2) +=0.01;\n      open_manipulator->makeTaskTrajectory(\"pen\", goal_pose, 1.0);\n    break;\n    case 23: // z down\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, -0.010), 0.5);\n    break;\n    case 24: // drawing O\n      draw_alphabet_arg[0] = 'I'; // drawing alphabet\n      draw_alphabet_arg[1] = 20; // drawing scale 2cm\n      open_manipulator->makeCustomTrajectory(DRAWING_ALPHABET, \"pen\", p_draw_alphabet_arg, 5.0);\n    break;\n    case 25: // z up\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, 0.010), 0.5);\n    break;\n    \n    case 26: // S start pose 0, 0\n      goal_pose = robotis_start_position;\n      goal_pose(0) -=0.0;\n      goal_pose(1) +=0.12 - 0.001; \n      goal_pose(2) +=0.01;\n      open_manipulator->makeTaskTrajectory(\"pen\", goal_pose, 1.0);\n    break;\n    case 27: // z down\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, -0.010), 0.5);\n    break;\n    case 28: // drawing O\n      draw_alphabet_arg[0] = 'S'; // drawing alphabet\n      draw_alphabet_arg[1] = 20; // drawing scale 2cm\n      open_manipulator->makeCustomTrajectory(DRAWING_ALPHABET, \"pen\", p_draw_alphabet_arg, 5.0);\n    break;\n    case 29: // z up\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, 0.010), 0.5);\n    break;\n\n    case 30: // mobile manipulator start pose 0, 0\n      goal_pose = mm_start_position;\n      goal_pose(2) += 0.01;\n      open_manipulator->makeTaskTrajectory(\"pen\", goal_pose, 1.5);\n    break;\n    case 31: // z down\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, -0.010), 0.5);\n    break;\n    case 32: // drawing mm\n      draw_alphabet_arg[0] = '!'; // drawing alphabet\n      draw_alphabet_arg[1] = 120; // drawing scale 12cm\n      open_manipulator->makeCustomTrajectory(DRAWING_ALPHABET, \"pen\", p_draw_alphabet_arg,10.0);\n    break;\n    case 33: // z up\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, 0.020), 0.5);\n    break;\n\n    case 34: // I start pose 0, 0\n      goal_pose = ict_start_position;\n      goal_pose(2) += 0.01;\n      open_manipulator->makeTaskTrajectory(\"pen\", goal_pose, 1.5);\n    break;\n    case 35: // z down\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, -0.010), 0.5);\n    break;\n    case 36: // drawing mm\n      draw_alphabet_arg[0] = 'I'; // drawing alphabet\n      draw_alphabet_arg[1] = 15; // drawing scale 1.5cm\n      open_manipulator->makeCustomTrajectory(DRAWING_ALPHABET, \"pen\", p_draw_alphabet_arg, 5.0);\n    break;\n    case 37: // z up\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, 0.010), 0.5);\n    break;\n\n    case 38: // C start pose 0, 1\n      goal_pose = ict_start_position;\n      goal_pose(0) -= 0.0075;\n      goal_pose(1) += 0.015; \n      goal_pose(2) += 0.01;\n      open_manipulator->makeTaskTrajectory(\"pen\", goal_pose, 1.5);\n    break;\n    case 39: // z down\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, -0.010), 0.5);\n    break;\n    case 40: // drawing mm\n      draw_alphabet_arg[0] = 'C'; // drawing alphabet\n      draw_alphabet_arg[1] = 15; // drawing scale 1.5cm\n      open_manipulator->makeCustomTrajectory(DRAWING_ALPHABET, \"pen\", p_draw_alphabet_arg, 5.0);\n    break;\n    case 41: // z up\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, 0.010), 0.5);\n    break;\n\n    case 42: // T start pose 0, 0\n      goal_pose = ict_start_position;\n      goal_pose(0) -= 0.0;\n      goal_pose(1) += 0.0375; \n      goal_pose(2) += 0.01;\n      open_manipulator->makeTaskTrajectory(\"pen\", goal_pose, 1.5);\n    break;\n    case 43: // z down\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, -0.010), 0.5);\n    break;\n    case 44: // drawing mm\n      draw_alphabet_arg[0] = 'T'; // drawing alphabet\n      draw_alphabet_arg[1] = 15; // drawing scale 1.5cm\n      open_manipulator->makeCustomTrajectory(DRAWING_ALPHABET, \"pen\", p_draw_alphabet_arg, 5.0);\n    break;\n    case 45: // z up\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, 0.010), 0.5);\n    break;\n    \n    case 46: // home\n      goal_joint_position.push_back( 0.00);\n      goal_joint_position.push_back(-1.05);\n      goal_joint_position.push_back( 0.35);\n      goal_joint_position.push_back( 0.69);\n      open_manipulator->makeJointTrajectory(goal_joint_position, 1.5); \n    break;\n  }\n}\n\nvoid demo_motion_mm(OpenManipulatorPen *open_manipulator, int cnt)\n{\n  std::vector<double> goal_joint_position;\n  char draw_alphabet_arg[1];\n  void* p_draw_alphabet_arg = &draw_alphabet_arg;\n  Eigen::Vector3d goal_pose;\n  \n  Eigen::Vector3d mm_start_position(0.260, -0.075, PEN_DEPTH);\n  \n  switch(cnt) \n  {\n    case 0: // home\n      goal_joint_position.push_back( 0.00);\n      goal_joint_position.push_back(-1.05);\n      goal_joint_position.push_back( 0.35);\n      goal_joint_position.push_back( 0.69);\n      open_manipulator->makeJointTrajectory(goal_joint_position, 1.0); \n    break;\n    case 1: // init\n      goal_joint_position.push_back( 0.00);\n      goal_joint_position.push_back( 0.00);\n      goal_joint_position.push_back( 0.00);\n      goal_joint_position.push_back( 0.00);\n      open_manipulator->makeJointTrajectory(goal_joint_position, 1.0); \n    break;\n\n    case 2: // mobile manipulator start pose 0, 0\n      goal_pose = mm_start_position;\n      goal_pose(2) += 0.01;\n      open_manipulator->makeTaskTrajectory(\"pen\", goal_pose, 1.5);\n    break;\n    case 3: // z down\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, -0.010), 0.5);\n    break;\n    case 4: // drawing mm\n      draw_alphabet_arg[0] = '!'; // drawing alphabet\n      draw_alphabet_arg[1] = 120; // drawing scale 12cm\n      open_manipulator->makeCustomTrajectory(DRAWING_ALPHABET, \"pen\", p_draw_alphabet_arg,25.0);\n    break;\n    case 5: // z up\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, 0.020), 0.5);\n    break;\n\n    case 6: // home\n      goal_joint_position.push_back( 0.00);\n      goal_joint_position.push_back(-1.05);\n      goal_joint_position.push_back( 0.35);\n      goal_joint_position.push_back( 0.69);\n      open_manipulator->makeJointTrajectory(goal_joint_position, 1.5); \n    break;\n  }\n}\n\nvoid demo_motion_robotis(OpenManipulatorPen *open_manipulator, int cnt)\n{\n  std::vector<double> goal_joint_position;\n  char draw_alphabet_arg[1];\n  void* p_draw_alphabet_arg = &draw_alphabet_arg;\n  Eigen::Vector3d goal_pose;\n\n  Eigen::Vector3d robotis_start_position(0.190, -0.105, PEN_DEPTH);\n  \n  switch(cnt) \n  {\n    case 0: // home\n      goal_joint_position.push_back( 0.00);\n      goal_joint_position.push_back(-1.05);\n      goal_joint_position.push_back( 0.35);\n      goal_joint_position.push_back( 0.69);\n      open_manipulator->makeJointTrajectory(goal_joint_position, 1.0); \n    break;\n    case 1: // init\n      goal_joint_position.push_back( 0.00);\n      goal_joint_position.push_back( 0.00);\n      goal_joint_position.push_back( 0.00);\n      goal_joint_position.push_back( 0.00);\n      open_manipulator->makeJointTrajectory(goal_joint_position, 1.0); \n    break;\n\n    case 2: // R start pose 0, 0\n      goal_pose = robotis_start_position;\n      goal_pose(2) += 0.01;\n      open_manipulator->makeTaskTrajectory(\"pen\", goal_pose, 1.0);\n    break;\n    case 3: // z down\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, -0.010), 0.5);\n    break;\n    case 4: // drawing R\n      draw_alphabet_arg[0] = 'R'; // drawing alphabet\n      draw_alphabet_arg[1] = 30; // drawing scale 3cm\n      open_manipulator->makeCustomTrajectory(DRAWING_ALPHABET, \"pen\", p_draw_alphabet_arg, 5.0);\n    break;\n    case 5: // z up\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, 0.010), 0.5);\n    break;\n\n    case 6: // O start pose 0, 1\n      goal_pose = robotis_start_position;\n      goal_pose(0) -=0.015;\n      goal_pose(1) +=0.03; \n      goal_pose(2) +=0.01;\n      open_manipulator->makeTaskTrajectory(\"pen\", goal_pose, 1.0);\n    break;\n    case 7: // z down\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, -0.010), 0.5);\n    break;\n    case 8: // drawing O\n      draw_alphabet_arg[0] = 'O'; // drawing alphabet\n      draw_alphabet_arg[1] = 30; // drawing scale 3cm\n      open_manipulator->makeCustomTrajectory(DRAWING_ALPHABET, \"pen\", p_draw_alphabet_arg, 5.0);\n    break;\n    case 9: // z up\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, 0.010), 0.5);\n    break;\n\n    case 10: // B start pose 0, 0\n      goal_pose = robotis_start_position;\n      goal_pose(0) -=0.00;\n      goal_pose(1) +=0.06; \n      goal_pose(2) +=0.01;\n      open_manipulator->makeTaskTrajectory(\"pen\", goal_pose, 1.0);\n    break;\n    case 11: // z down\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, -0.010), 0.5);\n    break;\n    case 12: // drawing O\n      draw_alphabet_arg[0] = 'B'; // drawing alphabet\n      draw_alphabet_arg[1] = 30; // drawing scale 3cm\n      open_manipulator->makeCustomTrajectory(DRAWING_ALPHABET, \"pen\", p_draw_alphabet_arg, 5.0);\n    break;\n    case 13: // z up\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, 0.010), 0.5);\n    break;\n\n    case 14: // O start pose 0, 1\n      goal_pose = robotis_start_position;\n      goal_pose(0) -=0.015;\n      goal_pose(1) +=0.09; \n      goal_pose(2) +=0.01;\n      open_manipulator->makeTaskTrajectory(\"pen\", goal_pose, 1.0);\n    break;\n    case 15: // z down\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, -0.010), 0.5);\n    break;\n    case 16: // drawing O\n      draw_alphabet_arg[0] = 'O'; // drawing alphabet\n      draw_alphabet_arg[1] = 30; // drawing scale 3cm\n      open_manipulator->makeCustomTrajectory(DRAWING_ALPHABET, \"pen\", p_draw_alphabet_arg, 5.0);\n    break;\n    case 17: // z up\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, 0.010), 0.5);\n    break;\n\n    case 18: // T start pose 1, 0\n      goal_pose = robotis_start_position;\n      goal_pose(0) -=0.0;\n      goal_pose(1) +=0.12 + 0.015 - 0.003; \n      goal_pose(2) +=0.01;\n      open_manipulator->makeTaskTrajectory(\"pen\", goal_pose, 1.0);\n    break;\n    case 19: // z down\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, -0.010), 0.5);\n    break;\n    case 20: // drawing O\n      draw_alphabet_arg[0] = 'T'; // drawing alphabet\n      draw_alphabet_arg[1] = 30; // drawing scale 3cm\n      open_manipulator->makeCustomTrajectory(DRAWING_ALPHABET, \"pen\", p_draw_alphabet_arg, 5.0);\n    break;\n    case 21: // z up\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, 0.010), 0.5);\n    break;\n\n    case 22: // I start pose 0, 0\n      goal_pose = robotis_start_position;\n      goal_pose(0) -=0.0;\n      goal_pose(1) +=0.15 - 0.003;  \n      goal_pose(2) +=0.01;\n      open_manipulator->makeTaskTrajectory(\"pen\", goal_pose, 1.0);\n    break;\n    case 23: // z down\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, -0.010), 0.5);\n    break;\n    case 24: // drawing O\n      draw_alphabet_arg[0] = 'I'; // drawing alphabet\n      draw_alphabet_arg[1] = 30; // drawing scale 3cm\n      open_manipulator->makeCustomTrajectory(DRAWING_ALPHABET, \"pen\", p_draw_alphabet_arg, 5.0);\n    break;\n    case 25: // z up\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, 0.010), 0.5);\n    break;\n    \n    case 26: // S start pose 0, 0\n      goal_pose = robotis_start_position;\n      goal_pose(0) -=0.0;\n      goal_pose(1) +=0.18 - 0.003; \n      goal_pose(2) +=0.01;\n      open_manipulator->makeTaskTrajectory(\"pen\", goal_pose, 1.0);\n    break;\n    case 27: // z down\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, -0.010), 0.5);\n    break;\n    case 28: // drawing O\n      draw_alphabet_arg[0] = 'S'; // drawing alphabet\n      draw_alphabet_arg[1] = 30; // drawing scale 3cm\n      open_manipulator->makeCustomTrajectory(DRAWING_ALPHABET, \"pen\", p_draw_alphabet_arg, 5.0);\n    break;\n    case 29: // z up\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, 0.010), 0.5);\n    break;\n\n    case 30: // home\n      goal_joint_position.push_back( 0.00);\n      goal_joint_position.push_back(-1.05);\n      goal_joint_position.push_back( 0.35);\n      goal_joint_position.push_back( 0.69);\n      open_manipulator->makeJointTrajectory(goal_joint_position, 1.5); \n    break;\n  }\n}\n\nvoid playMotion(OpenManipulatorPen *open_manipulator)\n{\n  if(!open_manipulator->getMovingState() && demo_motion_state)\n  {\n    log::println(\"Demo cnt \", demo_motion_cnt);\n    if(demo_motion_type == 1) // robotis\n      demo_motion_robotis(open_manipulator, demo_motion_cnt);\n    else if(demo_motion_type == 2) // mobile manipulator\n      demo_motion_mm(open_manipulator, demo_motion_cnt);\n    else if(demo_motion_type == 3) // robotis + mobile manipulator  \n      demo_motion_robotis_mm(open_manipulator, demo_motion_cnt);\n    demo_motion_cnt ++;\n    if(demo_motion_cnt > 46)\n    {\n      demo_motion_cnt = 0;\n      demo_motion_state = false;\n    }\n  }\n}\n\nvoid switchInit()\n{\n  pinMode(BDPIN_PUSH_SW_1, INPUT);\n  pinMode(BDPIN_PUSH_SW_2, INPUT);\n}\n\nvoid switchRead(OpenManipulatorPen *open_manipulator)\n{\n  if(digitalRead(BDPIN_PUSH_SW_1))\n  {\n    demo_motion_state = true;\n    demo_motion_type = 1; // ROBOTIS\n  }\n  else if(digitalRead(BDPIN_PUSH_SW_2))\n  {\n    demo_motion_state = true;\n    demo_motion_type = 2; // mobile manipulator\n  }\n}\n#endif // OPEN_MANIPULATOR_PEN_MOTION_H_\n\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Chain/open_manipulator_chain_pen/processing.h",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef PROCESSING_H_\n#define PROCESSING_H_\n\n#include \"open_manipulator_pen.h\"\n\n#define DXL_SIZE 5\n\ntypedef struct _MotionWaypoint\n{\n  std::vector<double> angle;\n  double path_time;\n  double gripper_value;\n} MotionWaypoint;\n\nstd::vector<MotionWaypoint> motion_way_point_buf;\nbool processing_motion_state = false;\nchar hand_motion_cnt = 0;\nbool hand_motion_repeat_state = false;\nbool platform_state_processing = false;\nString global_cmd[50];\n\nvoid connectProcessing(bool platform)\n{ \n  platform_state_processing = platform;\n  for (int i = 0; i < DXL_SIZE; i++)\n  {\n    Serial.print(0.0);\n    Serial.print(\",\");\n  }\n\n  Serial.println(0.0);\n  delay(300);\n\n  Serial.println(\"Init Processing\");\n}\n\nint availableProcessing()\n{\n  return Serial.available();\n}\n\nString readProcessingData()\n{\n  return Serial.readStringUntil('\\n');\n}\n\nvoid split(String data, char separator, String* temp)\n{\n  int cnt = 0;\n  int get_index = 0;\n\n  String copy = data;\n  \n  while(true)\n  {\n    get_index = copy.indexOf(separator);\n    if(-1 != get_index)\n    {\n      temp[cnt] = copy.substring(0, get_index);\n      copy = copy.substring(get_index + 1);\n    }\n    else\n    {\n      temp[cnt] = copy.substring(0, copy.length());\n      break;\n    }\n\t  ++cnt;\n  }\n}\n\nString* parseDataFromProcessing(String get)\n{\n  get.trim();\n  split(get, ',', global_cmd);\n  \n  return global_cmd;\n}\n\nvoid sendAngleToProcessing(JointWaypoint joint_states_vector)\n{\n  Serial.print(\"angle\");\n\n  for (int i = 0; i < (int)joint_states_vector.size(); i++)\n  {\n    Serial.print(\",\");\n    Serial.print(joint_states_vector.at(i).position, 3);\n  }\n  Serial.print(\"\\n\");\n}\n\nvoid sendValueToProcessing(OpenManipulatorPen *open_manipulator)\n{\n  sendAngleToProcessing(open_manipulator->getAllActiveJointValue());\n}\n\nvoid fromProcessing(OpenManipulatorPen *open_manipulator, String data)\n{\n  String *cmd = parseDataFromProcessing(data);\n\n  if (cmd[0] == \"opm\")\n  {\n    if (cmd[1] == \"ready\")\n    {\n      if(platform_state_processing)\n      {\n        open_manipulator->enableAllActuator();\n        sendValueToProcessing(open_manipulator);\n      }\n    }\n    else if (cmd[1] == \"end\")\n    {\n      if(platform_state_processing)\n      {\n        open_manipulator->disableAllActuator();\n      }\n    }\n  }\n  ////////// joint space control tab\n  else if (cmd[0] == \"joint\")\n  {\n    std::vector<double> goal_position;\n    for (uint8_t index = 0; index < DXL_SIZE; index++)\n    {\n      goal_position.push_back((double)cmd[index + 1].toFloat());\n    }\n    open_manipulator->makeJointTrajectory(goal_position, 1.0); // FIX TIME PARAM\n  }\n  ////////// task space control tab\n  else if (cmd[0] == \"task\")\n  {\n    if (cmd[1] == \"forward\")\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.010, 0.0, 0.0), 0.2);\n    else if (cmd[1] == \"back\")\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(-0.010, 0.0, 0.0), 0.2);\n    else if (cmd[1] == \"left\")\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.010, 0.0), 0.2);\n    else if (cmd[1] == \"right\")\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, -0.010, 0.0), 0.2);\n    else if (cmd[1] == \"up\")\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, 0.010), 0.2);\n    else if (cmd[1] == \"down\")\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, -0.010), 0.2);\n    else\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"pen\", math::vector3(0.0, 0.0, 0.0), 0.2);\n  }\n  else if (cmd[0] == \"torque\")\n  {\n    if(platform_state_processing)\n    {\n      if (cmd[1] == \"on\")\n        open_manipulator->enableAllActuator();\n      else if (cmd[1] == \"off\")\n        open_manipulator->disableAllActuator();\n    }\n  }\n  ////////// hand teaching tab\n  else if (cmd[0] == \"get\")\n  {\n    if (cmd[1] == \"clear\")  // motion clear\n    {\n      processing_motion_state = false;\n      motion_way_point_buf.clear();\n      hand_motion_cnt = 0;\n    }\n    else if (cmd[1] == \"pose\")  // save pose\n    {\n      MotionWaypoint read_value;\n      JointWaypoint present_states = open_manipulator->getAllActiveJointValue();\n      for(uint32_t i = 0; i < present_states.size(); i ++)\n        read_value.angle.push_back(present_states.at(i).position);  \n      read_value.path_time = 2.0; // FIX TIME PARAM\n      motion_way_point_buf.push_back(read_value);  \n      hand_motion_cnt = 0;\n    }\n  }\n  else if (cmd[0] == \"hand\")\n  {\n    if (cmd[1] == \"once\") // play motion (once)\n    {\n      processing_motion_state = true;//\n    }\n    else if (cmd[1] == \"repeat\") // play motion (repeat)\n    {\n      hand_motion_repeat_state = true;\n    }\n    else if (cmd[1] == \"stop\") // play motion (stop)\n    {\n      hand_motion_repeat_state = false;\n      processing_motion_state = false;\n      hand_motion_cnt = 0;\n    }\n  }\n  ////////// motion tab\n  else if (cmd[0] == \"motion\")\n  {\n    if (cmd[1] == \"1\")\n    {\n      TaskWaypoint draw_line_arg;\n      draw_line_arg.kinematic.position(0) = 0.02;\n      draw_line_arg.kinematic.position(1) = 0.02;\n      draw_line_arg.kinematic.position(2) = -0.02;\n      void *p_draw_line_arg = &draw_line_arg;\n      open_manipulator->makeCustomTrajectory(CUSTOM_TRAJECTORY_LINE, \"pen\", p_draw_line_arg, 1.0);\n    }\n    else if (cmd[1] == \"2\")\n    {\n      double draw_circle_arg[3];\n      draw_circle_arg[0] = 0.03; // radius (m)\n      draw_circle_arg[1] = 2;    // revolution\n      draw_circle_arg[2] = 0.0;  // start angle position (rad)\n      void* p_draw_circle_arg = &draw_circle_arg;\n      open_manipulator->makeCustomTrajectory(CUSTOM_TRAJECTORY_CIRCLE, \"pen\", p_draw_circle_arg, 4.0);\n    }\n  }\n}\n\nvoid playProcessingMotion(OpenManipulatorPen *open_manipulator)\n{\n  if(!open_manipulator->getMovingState() && processing_motion_state)\n  {\n    if(motion_way_point_buf.size() == 0)\n      return;\n\n    open_manipulator->makeJointTrajectory(motion_way_point_buf.at(hand_motion_cnt).angle, motion_way_point_buf.at(hand_motion_cnt).path_time); \n    hand_motion_cnt ++;\n    if(hand_motion_cnt >= motion_way_point_buf.size())\n    {\n      hand_motion_cnt = 0;\n      if(!hand_motion_repeat_state)\n        processing_motion_state = false;\n    }\n  }\n}\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Chain/open_manipulator_chain_teaching/open_manipulator_chain_teaching.ino",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Will Son */\n\n#include <open_manipulator_libs.h>\n#include \"Arduino.h\"\n\nOpenManipulator open_manipulator;\ndouble control_time = 0.010;  //default control frequency (100Hz)\ndouble present_time = 0.0;\ndouble previous_time = 0.0;\nbool platform_state = true;\nbool start_motion_flag = false;\nbool stop_motion_flag = false;\nbool teaching_mode_flag = false;\nuint8_t motion_cnt[] = {0};\nuint8_t motion_index = 0;\nuint8_t motion_number = 0;\n\nstd::vector<JointValue> present_position;\nstd::vector<JointValue> gripper_position;\nstd::vector<JointValue> saved_teaching_pose;\n\nvoid setup()\n{\n  Serial.begin(57600);\n  while (!Serial);  // Wait until Serial is Opened\n\n  open_manipulator.setOpenManipulatorCustomJointId(11, 12, 13, 14, 15); // ID 11, 12, 13, 14, 15 is default\n  open_manipulator.initOpenManipulator(platform_state);\n  Serial.println(\"OpenManipulator Init Begin\");\n\n  initDemo();\n  \n  Serial.println(\"Press [SW1] to start programmed motion. Press [SW2] to start teaching mode.\");\n  while (true)\n  {\n    digitalWrite(BDPIN_LED_USER_1, LOW);\n    if(digitalRead(BDPIN_PUSH_SW_1))\n    {\n      Serial.println(\"Programmed motion mode begin.\");\n      teaching_mode_flag = false;\n      warning();\n      break;\n    }\n    else if(digitalRead(BDPIN_PUSH_SW_2))\n    {\n      Serial.println(\"Teaching mode begin.\");\n      teaching_mode_flag = true;\n      break;\n    }\n  }\n  digitalWrite(BDPIN_LED_USER_1, HIGH);\n}\n\nvoid loop()\n{\n  if (teaching_mode_flag)\n  {\n    open_manipulator.disableAllActuator();\n    delay_ms(1000);\n    Serial.println(\"Press [SW2] to append Current Pose. Press [SW1] to finish appending pose and play taught pose\");\n\n    while (true)\n    {\n      digitalWrite(BDPIN_LED_USER_2, LOW);\n      if (digitalRead(BDPIN_PUSH_SW_2))\n      {\n        // Append(Teach) the current Pose to the present_position data\n        uint8_t pos_vector_index = motion_index;\n        present_position = open_manipulator.receiveAllJointActuatorValue();\n        gripper_position = open_manipulator.receiveAllToolActuatorValue();\n        for(uint8_t joint_index = 0; joint_index < 4; joint_index++ )\n        {\n          saved_teaching_pose.push_back(present_position.at(joint_index));\n        }\n        saved_teaching_pose.push_back(gripper_position.at(0));\n\n        // Display saved Pose Joint angles in Radian\n        Serial.print(\"[Pose \");\n        Serial.print(motion_index/5 + 1);\n        Serial.print(\"] : \");\n        Serial.print(saved_teaching_pose[pos_vector_index++].position, 3);\n        Serial.print(\", \");\n        Serial.print(saved_teaching_pose[pos_vector_index++].position, 3);\n        Serial.print(\", \");\n        Serial.print(saved_teaching_pose[pos_vector_index++].position, 3);\n        Serial.print(\", \");\n        Serial.print(saved_teaching_pose[pos_vector_index++].position, 3);\n        Serial.print(\", \");\n        Serial.println(saved_teaching_pose[pos_vector_index++].position, 3);\n        motion_index = motion_index + 5;\n        break;\n      }\n      if (digitalRead(BDPIN_PUSH_SW_1))\n      {\n        digitalWrite(BDPIN_LED_USER_3, LOW);\n        teaching_mode_flag = false;\n\n        // Display the list of saved(taught) Pose\n        for(uint8_t index = 0; index < motion_index ; index++)\n        {\n          if(index % 5 == 0)\n          {\n            Serial.println();\n          }\n          else\n          {\n            Serial.print(\", \");\n          }\n          Serial.print(saved_teaching_pose[index].position, 3);\n        }\n\n        warning();\n        break;\n      }\n    }\n    digitalWrite(BDPIN_LED_USER_2, HIGH);\n  }\n  else\n  {\n    present_time = millis()/1000.0;\n\n    // Trajectory following movement occurs here\n    if(present_time-previous_time >= control_time)\n    {\n      open_manipulator.processOpenManipulator(millis()/1000.0);\n      previous_time = millis()/1000.0;\n    }\n\n    // Read the next Pose to move\n    if(!saved_teaching_pose.empty())\n    {\n      runTeachingMotion(&open_manipulator);\n    }\n    else\n    {\n      runDemo(&open_manipulator);\n    }\n  }\n}\n\n// Output warning before starting motion\nvoid warning()\n{\n  Serial.println();\n  Serial.println(\"WARNING!!! OpenMANIPULATOR-X operates in 5 seconds.\");\n  delay_ms(1000);\n  Serial.println(\"WARNING!!! OpenMANIPULATOR-X operates in 4 seconds.\");\n  delay_ms(1000);\n  Serial.println(\"WARNING!!! OpenMANIPULATOR-X operates in 3 seconds.\");\n  delay_ms(1000);\n  Serial.println(\"WARNING!!! OpenMANIPULATOR-X operates in 2 seconds.\");\n  delay_ms(1000);\n  Serial.println(\"WARNING!!! OpenMANIPULATOR-X operates in 1 seconds.\");\n  open_manipulator.receiveAllJointActuatorValue();\n  open_manipulator.receiveAllToolActuatorValue();\n  open_manipulator.enableAllActuator();\n  delay_ms(1000);\n}\n\n// Move in Joint Space \nvoid moveJS(OpenManipulator *open_manipulator, double j1, double j2, double j3, double j4, double gripper_pos, double time)\n{\n  static std::vector <double> target_angle;\n  target_angle.clear();\n  target_angle.push_back(j1);\n  target_angle.push_back(j2);\n  target_angle.push_back(j3);\n  target_angle.push_back(j4);\n  open_manipulator->makeJointTrajectory(target_angle, time);\n  open_manipulator->makeToolTrajectory(\"gripper\", gripper_pos);\n}\n\n/*****************************************************************************\n** Initialize Demo\n*****************************************************************************/\nvoid initDemo()\n{\n  start_motion_flag = false;\n  motion_cnt[0] = 0;\n\n  pinMode(BDPIN_PUSH_SW_1, INPUT);\n  pinMode(BDPIN_PUSH_SW_2, INPUT);\n  pinMode(BDPIN_GPIO_1, OUTPUT);\n  digitalWrite(BDPIN_GPIO_1, LOW);\n  Serial.println(\"OpenManipulator Init Completed\");\n}\n\n/*****************************************************************************\n** Play Demo Motion\n*****************************************************************************/\nvoid runDemo(OpenManipulator *open_manipulator)\n{\n  if(!start_motion_flag && !stop_motion_flag)\n  {\n    startMotion();\n  }\n  if(!start_motion_flag && stop_motion_flag)  // Restart DEMO\n  {\n    if(digitalRead(BDPIN_PUSH_SW_1))\n    {\n      startMotion();\n    }\n  }\n  if(digitalRead(BDPIN_PUSH_SW_2) && !stop_motion_flag)  // Stop DEMO\n  {\n    stopMotion(open_manipulator);\n  }\n\n  if (open_manipulator->getMovingState())\n  {\n    return;\n  }\n  else \n  {\n    if (start_motion_flag)\n    {\n      switch(motion_cnt[0])\n      {\n        case 0:\n          moveJS(open_manipulator, 0.0, -1.0, 0.2, 0.8, 0.0, 2.0); \n          motion_cnt[0] ++; \n          break;\n        case 1:\n          moveJS(open_manipulator, -0.5, 0.0, 1.0, -1.0, 0.01, 2.0); \n          motion_cnt[0] ++; \n          break;\n        case 2:\n          moveJS(open_manipulator, -0.5, 0.1, 0.75, -0.85, 0.01, 2.0); \n          motion_cnt[0] ++; \n          break;\n        case 3:\n          open_manipulator->sleepTrajectory(2.0);\n          motion_cnt[0] ++; \n          break;\n        case 4:\n          moveJS(open_manipulator, -0.5, -0.05, 1.05, -1.0, 0.0, 2.0); \n          motion_cnt[0] = 0; \n          break;\n        default:\n          motion_cnt[0] = 0;\n          break;\n      }\n    }\n  }\n}\n\n/*****************************************************************************\n** Play Teaching Motion\n*****************************************************************************/\nvoid runTeachingMotion(OpenManipulator *open_manipulator)\n{\n  if(!start_motion_flag && !stop_motion_flag) // Start Teach Motion\n  {\n    startMotion();\n  }\n  if(!start_motion_flag && stop_motion_flag)  // Restart Teach Motion\n  {\n    if(digitalRead(BDPIN_PUSH_SW_1))\n    {\n      startMotion();\n    }\n  }\n  if(digitalRead(BDPIN_PUSH_SW_2) && !stop_motion_flag)  // Stop Teach Motion\n  {\n    stopMotion(open_manipulator);\n    digitalWrite(BDPIN_LED_USER_1, HIGH); // Turn off USER1 LED\n    digitalWrite(BDPIN_LED_USER_2, HIGH); // Turn off USER2 LED\n    digitalWrite(BDPIN_LED_USER_3, HIGH); // Turn off USER3 LED\n    digitalWrite(BDPIN_LED_USER_4, HIGH); // Turn off USER4 LED\n  }\n\n  if (open_manipulator->getMovingState()) // Check if OpenMANIPULATOR is moving along the trajectory\n  {\n    // If OpenMANIPULATOR is still moving along the trajectory, then do not get the next Pose and return to main loop\n    // Digital Output HIGH(3.3V) on OpenCR GPIO pin #3 (http://emanual.robotis.com/docs/en/parts/controller/opencr10/#gpio)\n    digitalWrite(BDPIN_GPIO_1, HIGH);\n    return;\n  }\n  else\n  {\n    // Digital Output LOW(0V) on OpenCR GPIO pin #3 (http://emanual.robotis.com/docs/en/parts/controller/opencr10/#gpio)\n    digitalWrite(BDPIN_GPIO_1, LOW);\n    if (start_motion_flag)\n    {\n      if (motion_cnt[0] < motion_index)\n      {\n        uint8_t joint1_index = motion_cnt[0]++;\n        uint8_t joint2_index = motion_cnt[0]++;\n        uint8_t joint3_index = motion_cnt[0]++;\n        uint8_t joint4_index = motion_cnt[0]++;\n        uint8_t gripper_index = motion_cnt[0]++;\n        \n        // Play each motion during 3.0 seconds\n        moveJS(open_manipulator, saved_teaching_pose[joint1_index].position, saved_teaching_pose[joint2_index].position, saved_teaching_pose[joint3_index].position, saved_teaching_pose[joint4_index].position, saved_teaching_pose[gripper_index].position, 3.0);\n      }\n      else\n      {\n        motion_cnt[0] = 0;\n      }\n    }\n  }\n}\n\n/*****************************************************************************\n** Start Motion\n*****************************************************************************/\nvoid startMotion()\n{\n  Serial.println(\"Press [SW2] to Stop Motion\");\n  // Start the motion\n  start_motion_flag = true;\n  stop_motion_flag = false;\n  \n  motion_cnt[0] = 0;\n}\n\n/*****************************************************************************\n** Stop Motion\n*****************************************************************************/\nvoid stopMotion(OpenManipulator *open_manipulator)\n{\n  Serial.println(\"Press [SW1] to Start Motion\");\n  // Stop the motion\n  start_motion_flag = false;\n  stop_motion_flag = true;\n\n  // Go to the Init Pose(Right angle pose).\n  moveJS(open_manipulator, 0.0, 0.0, 0.0, 0.0, 0.0, 1.0); \n  motion_cnt[0] = 0;\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Chain/open_manipulator_chain_vacuum/actuator.h",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef ACTUATOR_H_\n#define ACTUATOR_H_\n\n#include <RobotisManipulator.h>\n\n#define BDPIN_RELAY         8\n#define BDPIN_PUMP_MOTOR    12\n\nnamespace actuator\n{\nclass GripperVacuum : public robotis_manipulator::ToolActuator\n{\n private:\n  int8_t actuator_id_;\n  ActuatorValue tool_value_;\n\n public:\n  GripperVacuum() {}\n  virtual ~GripperVacuum() {}\n\n  virtual void init(uint8_t actuator_id, const void *arg)\n  {\n    actuator_id_ = actuator_id;\n    tool_value_.position = 0.0;\n    pinMode(BDPIN_RELAY, OUTPUT);\n    pinMode(BDPIN_PUMP_MOTOR, OUTPUT);\n  }\n  virtual void setMode(const void *arg){}\n  virtual uint8_t getId()\n  {\n    return actuator_id_;\n  }\n\n  virtual void enable(){}\n  virtual void disable(){}\n\n  virtual bool sendToolActuatorValue(ActuatorValue value)\n  {\n    if(value.position == 0.0)\n    {\n      tool_value_.position = 0.0;\n      digitalWrite(BDPIN_RELAY, LOW);\n      digitalWrite(BDPIN_PUMP_MOTOR, LOW);\n    }\n    else if(value.position == 1.0)\n    {\n      tool_value_.position = 1.0;\n      digitalWrite(BDPIN_RELAY, HIGH);\n      digitalWrite(BDPIN_PUMP_MOTOR, HIGH);\n    }\n    return true;\n  }\n  virtual ActuatorValue receiveToolActuatorValue()\n  {\n    return tool_value_;\n  }\n\n////////////////////////////////////////////////////////////////\n};\n\n} // namespace actuator\n#endif // ACTUATOR_H_\n\n\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Chain/open_manipulator_chain_vacuum/open_manipulator_chain_vacuum.ino",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include \"open_manipulator_vacuum.h\"\n#include \"open_manipulator_vacuum_motion.h\"\n#include \"processing.h\"\n\nOpenManipulatorVacuum open_manipulator;\ndouble control_time = 0.010f;\ndouble present_time = 0.0;\ndouble previous_time = 0.0;\nbool platform_state = true;\n\nvoid setup()\n{\n  Serial.begin(57600);\n  DEBUG.begin(57600);\n\n  connectProcessing(platform_state);\n  switchInit();\n  \n  open_manipulator.initOpenManipulator(platform_state);\n  log::println(\"OpenManipulatorVacuum Debugging Port\");\n}\n\nvoid loop()\n{\n  present_time = (float)(millis()/1000.0f);\n  getData(100);\n  switchRead();\n  playMotion(&open_manipulator);\n  playProcessingMotion(&open_manipulator);\n\n  if(present_time-previous_time >= control_time)\n  {\n    open_manipulator.processOpenManipulator(millis()/1000.0);\n    previous_time = (float)(millis()/1000.0f);\n    sendValueToProcessing(&open_manipulator);\n  }\n}\n\nvoid getData(uint32_t wait_time)\n{\n  static uint8_t state = 0;\n  static uint32_t tick = 0;\n\n  bool processing_state = false;\n  String get_processing_data = \"\";\n\n  if (availableProcessing())\n  {\n    get_processing_data = readProcessingData();\n    processing_state = true;\n  }\n\n  switch (state)\n  {\n    case 0:\n      if (processing_state)\n      {\n        fromProcessing(&open_manipulator, get_processing_data);\n        tick = millis();\n        state = 1;\n      }\n     break;\n\n    case 1:\n      if ((millis() - tick) >= wait_time)\n      {\n        state = 0;\n      }\n     break;\n\n    default:\n      state = 0;\n     break;\n  }\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Chain/open_manipulator_chain_vacuum/open_manipulator_vacuum.h",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef OPEN_MANIPULATOR_VACUUM_H_\n#define OPEN_MANIPULATOR_VACUUM_H_\n\n#include <open_manipulator_libs.h>\n#include \"actuator.h\"\n\n#define CUSTOM_TRAJECTORY_SIZE 4\n#define CUSTOM_TRAJECTORY_LINE    \"custom_trajectory_line\"\n#define CUSTOM_TRAJECTORY_CIRCLE  \"custom_trajectory_circle\"\n#define CUSTOM_TRAJECTORY_RHOMBUS \"custom_trajectory_rhombus\"\n#define CUSTOM_TRAJECTORY_HEART   \"custom_trajectory_heart\"\n\n#define JOINT_DYNAMIXEL \"joint_dxl\"\n#define TOOL_VACUUM \"tool_vacuum\"\n\n#define X_AXIS robotis_manipulator::math::vector3(1.0, 0.0, 0.0)\n#define Y_AXIS robotis_manipulator::math::vector3(0.0, 1.0, 0.0)\n#define Z_AXIS robotis_manipulator::math::vector3(0.0, 0.0, 1.0)\n\nclass OpenManipulatorVacuum : public robotis_manipulator::RobotisManipulator\n{\nprivate:\n  robotis_manipulator::Kinematics *kinematics_;\n  robotis_manipulator::JointActuator *actuator_;\n  robotis_manipulator::ToolActuator *tool_;\n  robotis_manipulator::CustomTaskTrajectory *custom_trajectory_[CUSTOM_TRAJECTORY_SIZE];\n\n public:\n  OpenManipulatorVacuum() {}\n  virtual ~OpenManipulatorVacuum() {}\n\n  void initOpenManipulator(bool using_actual_robot_state, STRING usb_port = \"/dev/ttyUSB0\", STRING baud_rate = \"1000000\", float control_loop_time = 0.010)\n  {\n\t\t/*****************************************************************************\n\t\t ** Initialize Manipulator Parameter \n\t\t*****************************************************************************/\n\t\taddWorld(\"world\",   // world name\n\t\t\t\t\t\t\"joint1\"); // child name\n\n\t\taddJoint(\"joint1\",  // my name\n\t\t\t\t\t\t\"world\",   // parent name\n\t\t\t\t\t\t\"joint2\",  // child name\n\t\t\t\t\t\tmath::vector3(0.012, 0.0, 0.017),               // relative position\n\t\t\t\t\t\tmath::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // relative orientation\n\t\t\t\t\t\tZ_AXIS,    // axis of rotation\n\t\t\t\t\t\t11,        // actuator id\n\t\t\t\t\t\tM_PI,      // max joint limit (3.14 rad)\n\t\t\t\t\t\t-M_PI);    // min joint limit (-3.14 rad)\n\n\t\taddJoint(\"joint2\",  // my name\n\t\t\t\t\t\t\"joint1\",  // parent name\n\t\t\t\t\t\t\"joint3\",  // child name\n\t\t\t\t\t\tmath::vector3(0.0, 0.0, 0.0595),                // relative position\n\t\t\t\t\t\tmath::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // relative orientation\n\t\t\t\t\t\tY_AXIS,    // axis of rotation\n\t\t\t\t\t\t12,        // actuator id\n\t\t\t\t\t\tM_PI_2,    // max joint limit (1.67 rad)\n\t\t\t\t\t\t-2.05);    // min joint limit (-2.05 rad)\n\n\t\taddJoint(\"joint3\",  // my name\n\t\t\t\t\t\t\"joint2\",  // parent name\n\t\t\t\t\t\t\"joint4\",  // child name\n\t\t\t\t\t\tmath::vector3(0.024, 0.0, 0.128),               // relative position\n\t\t\t\t\t\tmath::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // relative orientation\n\t\t\t\t\t\tY_AXIS,    // axis of rotation\n\t\t\t\t\t\t13,        // actuator id\n\t\t\t\t\t\t1.53,      // max joint limit (1.53 rad)\n\t\t\t\t\t\t-M_PI_2);  // min joint limit (-1.67 rad)\n\n\t\taddJoint(\"joint4\",  // my name\n\t\t\t\t\t\t\"joint3\",  // parent name\n\t\t\t\t\t\t\"vacuum\", // child name\n\t\t\t\t\t\tmath::vector3(0.124, 0.0, 0.0),                 // relative position\n\t\t\t\t\t\tmath::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // relative orientation\n\t\t\t\t\t\tY_AXIS,    // axis of rotation\n\t\t\t\t\t\t14,        // actuator id\n\t\t\t\t\t\t2.0,       // max joint limit (2.0 rad)\n\t\t\t\t\t\t-1.8);     // min joint limit (-1.8 rad)\n\t\t\t\t\t\t\t\n    addTool(\"vacuum\",   // my name\n            \"joint4\", // parent name\n            math::vector3(0.043, 0.0, 0.0), // relative position\n            math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // relative orientation\n            15); // actuator id\n\n\t\t/*****************************************************************************\n\t\t** Initialize Kinematics \n\t\t*****************************************************************************/\n\t\tkinematics_ = new kinematics::SolverCustomizedforOMChain();\n\t//  kinematics_ = new kinematics::SolverUsingCRAndSRPositionOnlyJacobian();\n\t\taddKinematics(kinematics_);\n\n\t\tif(using_actual_robot_state)\n\t\t{\n\t\t\t/*****************************************************************************\n\t\t\t** Initialize joint Actuator\n\t\t\t*****************************************************************************/\n\t\t\t// actuator_ = new dynamixel::JointDynamixel();\n\t\t\tactuator_ = new dynamixel::JointDynamixelProfileControl(control_loop_time);\n\n      // communication setting argument\n      STRING dxl_comm_arg[2] = {usb_port, baud_rate};\n      void *p_dxl_comm_arg = &dxl_comm_arg;\n\n      // set joint actuator id\n      std::vector<uint8_t> jointDxlId;\n      jointDxlId.push_back(11);\n      jointDxlId.push_back(12);\n      jointDxlId.push_back(13);\n      jointDxlId.push_back(14);\n      addJointActuator(JOINT_DYNAMIXEL, actuator_, jointDxlId, p_dxl_comm_arg);\n\n      // set joint actuator control mode\n      STRING joint_dxl_mode_arg = \"position_mode\";\n      void *p_joint_dxl_mode_arg = &joint_dxl_mode_arg;\n      setJointActuatorMode(JOINT_DYNAMIXEL, jointDxlId, p_joint_dxl_mode_arg);\n\n\t\t\t/*****************************************************************************\n\t\t\t** Initialize Tool Actuator\n\t\t\t*****************************************************************************/\n\t\t\ttool_ = new actuator::GripperVacuum();\n\n\t\t\tuint8_t toolId = 15;\n\t\t\taddToolActuator(TOOL_VACUUM, tool_, toolId, NULL);\n\t\t\t\t\n\t\t\t// Enable All Actuators \n\t\t\tenableAllActuator();\n\n\t\t\t// Receive current angles from all actuators \n\t\t\treceiveAllJointActuatorValue();\n\t\t\treceiveAllToolActuatorValue();\n\t\t}\n\n\t\t/*****************************************************************************\n\t\t** Initialize Custom Trajectory\n\t\t*****************************************************************************/\n\t\tcustom_trajectory_[0] = new custom_trajectory::Line();\n\t\tcustom_trajectory_[1] = new custom_trajectory::Circle();\n\t\tcustom_trajectory_[2] = new custom_trajectory::Rhombus();\n\t\tcustom_trajectory_[3] = new custom_trajectory::Heart();\n\n\t\taddCustomTrajectory(CUSTOM_TRAJECTORY_LINE, custom_trajectory_[0]);\n\t\taddCustomTrajectory(CUSTOM_TRAJECTORY_CIRCLE, custom_trajectory_[1]);\n\t\taddCustomTrajectory(CUSTOM_TRAJECTORY_RHOMBUS, custom_trajectory_[2]);\n\t\taddCustomTrajectory(CUSTOM_TRAJECTORY_HEART, custom_trajectory_[3]);\n\t}\n\n  void processOpenManipulator(double present_time)\n  {\n\t\tJointWaypoint goal_joint_value = getJointGoalValueFromTrajectory(present_time);\n\t\tJointWaypoint goal_tool_value  = getToolGoalValue();\n\n\t\treceiveAllJointActuatorValue();\n\t\treceiveAllToolActuatorValue();\n\t\tif(goal_joint_value.size() != 0) sendAllJointActuatorValue(goal_joint_value);\n\t\tif(goal_tool_value.size() != 0) sendAllToolActuatorValue(goal_tool_value);\n\t\tsolveForwardKinematics();\n  }\n};\n\n#endif // OPEN_MANIPULATOR_VACUUM_H_\n\n\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Chain/open_manipulator_chain_vacuum/open_manipulator_vacuum_motion.h",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef OPEN_MANIPULATOR_VACUUM_MOTION_H_\n#define OPEN_MANIPULATOR_VACUUM_MOTION_H_\n\n#include <RobotisManipulator.h>\n#include \"open_manipulator_vacuum.h\"\n\n#define BDPIN_PUSH_SW_1         34\n#define BDPIN_PUSH_SW_2         35\n\nbool demo_motion_state = false;\nchar demo_motion_cnt = 0;\n\n#define NUM_OF_MOTION 42\n#define NUM_OF_JOINT 4\ndouble demo_motion_way_point_buf[NUM_OF_MOTION][6] = \n{\n // j1       j2       j3       j4       time    tool \n    0.000,   0.000,   0.000,   0.000,   1.5,    0.0, // init\n    0.000,  -1.050,   0.350,   0.690,   1.0,    0.0, // home\n\n    0.433,   0.827,   0.031,  -0.827,   1.5,    0.0, // pose 1 up\n    0.433,   1.019,  -0.018,  -1.045,   0.5,    0.0, // pose 1\n    0.433,   1.019,  -0.018,  -1.045,   0.5,    1.0, // pick\n    0.433,   0.827,   0.031,  -0.827,   0.5,    1.0, // pose 1 up\n   -1.557,  -0.110,   0.360,   1.318,   1.5,    1.0, // save up\n   -1.557,   0.029,   0.594,   0.919,   1.0,    1.0, // save pose\n   -1.557,   0.029,   0.594,   0.919,   0.5,    0.0, // place\n    0.000,  -1.050,   0.350,   0.690,   1.0,    0.0, // home\n\n    0.540,   0.721,   0.804,  -1.522,   1.5,    0.0, // pose 2 up\n    0.540,   0.844,   0.752,  -1.598,   0.5,    0.0, // pose 2\n    0.540,   0.844,   0.752,  -1.598,   0.5,    1.0, // pick\n    0.540,   0.721,   0.804,  -1.522,   0.5,    1.0, // pose 2 up\n   -1.557,  -0.110,   0.360,   1.318,   1.5,    1.0, // save up\n   -1.557,   0.029,   0.594,   0.919,   1.0,    1.0, // save pose\n   -1.557,   0.029,   0.594,   0.919,   0.5,    0.0, // place\n    0.000,  -1.050,   0.350,   0.690,   1.0,    0.0, // home\n\n    0.249,   0.755,   0.575,  -1.328,   1.5,    0.0, // pose 3 up\n    0.249,   0.857,   0.537,  -1.385,   0.5,    0.0, // pose 3\n    0.249,   0.857,   0.537,  -1.385,   0.5,    1.0, // pick\n    0.249,   0.755,   0.575,  -1.328,   0.5,    1.0, // pose 3 up\n   -1.557,  -0.110,   0.360,   1.318,   1.5,    1.0, // save up\n   -1.557,   0.029,   0.594,   0.919,   1.0,    1.0, // save pose\n   -1.557,   0.029,   0.594,   0.919,   0.5,    0.0, // place\n    0.000,  -1.050,   0.350,   0.690,   1.0,    0.0, // home\n\n    0.046,   0.851,   0.138,  -1.000,   1.5,    0.0, // pose 4 up\n    0.046,   0.966,   0.090,  -1.022,   0.5,    0.0, // pose 4\n    0.046,   0.966,   0.090,  -1.022,   0.5,    1.0, // pick\n    0.046,   0.851,   0.138,  -1.000,   0.5,    1.0, // pose 4 up\n   -1.557,  -0.110,   0.360,   1.318,   1.5,    1.0, // save up\n   -1.557,   0.029,   0.594,   0.919,   1.0,    1.0, // save pose\n   -1.557,   0.029,   0.594,   0.919,   0.5,    0.0, // place\n    0.000,  -1.050,   0.350,   0.690,   1.0,    0.0, // home\n\n   -0.229,   0.724,   0.555,  -1.335,   1.5,    0.0, // pose 5 up\n   -0.229,   0.879,   0.509,  -1.437,   0.5,    0.0, // pose 5\n   -0.229,   0.879,   0.509,  -1.437,   0.5,    1.0, // pick\n   -0.229,   0.724,   0.555,  -1.335,   0.5,    1.0, // pose 5 up\n   -1.557,  -0.110,   0.360,   1.318,   1.5,    1.0, // save up\n   -1.557,   0.029,   0.594,   0.919,   1.0,    1.0, // save pose\n   -1.557,   0.029,   0.594,   0.919,   0.5,    0.0, // place\n    0.000,  -0.077,   0.538,  -0.446,   1.0,    0.0  // ceremony\n  \n};\n\n\nvoid playMotion(OpenManipulatorVacuum *open_manipulator)\n{\n  if(!open_manipulator->getMovingState() && demo_motion_state)\n  {\n    std::vector<double> joint_angle;\n    for(int i = 0; i < NUM_OF_JOINT; i ++)\n      joint_angle.push_back(demo_motion_way_point_buf[demo_motion_cnt][i]);\n    open_manipulator->makeJointTrajectory(joint_angle, demo_motion_way_point_buf[demo_motion_cnt][4]); \n    open_manipulator->makeToolTrajectory(\"vacuum\", demo_motion_way_point_buf[demo_motion_cnt][5]);\n    \n    demo_motion_cnt ++;\n    if(demo_motion_cnt > NUM_OF_MOTION)\n    {\n      double draw_circle_arg[3];\n      draw_circle_arg[0] = 0.2; // radius (m)\n      draw_circle_arg[1] = 2;    // revolution\n      draw_circle_arg[2] = 0.0;  // start angle position (rad)\n      void* p_draw_circle_arg = &draw_circle_arg;\n      open_manipulator->makeCustomTrajectory(CUSTOM_TRAJECTORY_HEART, \"vacuum\", p_draw_circle_arg, 4.0);\n\n      demo_motion_cnt = 0;\n      demo_motion_state = false;\n    }\n  }\n}\n\nvoid switchInit()\n{\n  pinMode(BDPIN_PUSH_SW_1, INPUT);\n  pinMode(BDPIN_PUSH_SW_2, INPUT);\n}\n\nvoid switchRead()\n{\n  if(digitalRead(BDPIN_PUSH_SW_1))\n    demo_motion_state = true;\n  else if(digitalRead(BDPIN_PUSH_SW_2))\n    demo_motion_state = false;\n}\n#endif // OPEN_MANIPULATOR_VACUUM_MOTION_H_\n\n\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Chain/open_manipulator_chain_vacuum/processing.h",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef PROCESSING_H_\n#define PROCESSING_H_\n\n#include \"open_manipulator_vacuum.h\"\n\n#define DXL_SIZE 5\n\ntypedef struct _MotionWaypoint\n{\n  std::vector<double> angle;\n  double path_time;\n  double gripper_value;\n} MotionWaypoint;\n\nstd::vector<MotionWaypoint> motion_way_point_buf;\nbool processing_motion_state = false;\nchar hand_motion_cnt = 0;\nbool hand_motion_repeat_state = false;\nbool platform_state_processing = false;\nString global_cmd[50];\n\nvoid connectProcessing(bool platform)\n{ \n  platform_state_processing = platform;\n  for (int i = 0; i < DXL_SIZE; i++)\n  {\n    Serial.print(0.0);\n    Serial.print(\",\");\n  }\n\n  Serial.println(0.0);\n  delay(300);\n\n  Serial.println(\"Init Processing\");\n}\n\nint availableProcessing()\n{\n  return Serial.available();\n}\n\nString readProcessingData()\n{\n  return Serial.readStringUntil('\\n');\n}\n\nvoid split(String data, char separator, String* temp)\n{\n  int cnt = 0;\n  int get_index = 0;\n\n  String copy = data;\n  \n  while(true)\n  {\n    get_index = copy.indexOf(separator);\n    if(-1 != get_index)\n    {\n      temp[cnt] = copy.substring(0, get_index);\n      copy = copy.substring(get_index + 1);\n    }\n    else\n    {\n      temp[cnt] = copy.substring(0, copy.length());\n      break;\n    }\n\t  ++cnt;\n  }\n}\n\nString* parseDataFromProcessing(String get)\n{\n  get.trim();\n  split(get, ',', global_cmd);\n  \n  return global_cmd;\n}\n\nvoid sendAngleToProcessing(JointWaypoint joint_states_vector)\n{\n  Serial.print(\"angle\");\n\n  for (int i = 0; i < (int)joint_states_vector.size(); i++)\n  {\n    Serial.print(\",\");\n    Serial.print(joint_states_vector.at(i).position, 3);\n  }\n  Serial.print(\"\\n\");\n}\n\nvoid sendValueToProcessing(OpenManipulatorVacuum *open_manipulator)\n{\n  sendAngleToProcessing(open_manipulator->getAllActiveJointValue());\n}\n\nvoid fromProcessing(OpenManipulatorVacuum *open_manipulator, String data)\n{\n  String *cmd = parseDataFromProcessing(data);\n\n  if (cmd[0] == \"opm\")\n  {\n    if (cmd[1] == \"ready\")\n    {\n      if(platform_state_processing)\n      {\n        open_manipulator->enableAllActuator();\n        sendValueToProcessing(open_manipulator);\n      }\n    }\n    else if (cmd[1] == \"end\")\n    {\n      if(platform_state_processing)\n      {\n        open_manipulator->disableAllActuator();\n      }\n    }\n  }\n  ////////// joint space control tab\n  else if (cmd[0] == \"joint\")\n  {\n    std::vector<double> goal_position;\n    for (uint8_t index = 0; index < DXL_SIZE; index++)\n    {\n      goal_position.push_back((double)cmd[index + 1].toFloat());\n    }\n    open_manipulator->makeJointTrajectory(goal_position, 1.0); // FIX TIME PARAM\n  }\n  else if (cmd[0] == \"gripper\")\n  {\n    open_manipulator->makeToolTrajectory(\"vacuum\", (double)cmd[1].toFloat());\n  }\n  else if (cmd[0] == \"grip\")\n  {\n    if (cmd[1] == \"on\")\n      open_manipulator->makeToolTrajectory(\"vacuum\", 1.0);\n    else if (cmd[1] == \"off\")\n      open_manipulator->makeToolTrajectory(\"vacuum\", 0.0);\n  }\n  ////////// task space control tab\n  else if (cmd[0] == \"task\")\n  {\n    if (cmd[1] == \"forward\")\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"vacuum\", math::vector3(0.010, 0.0, 0.0), 0.2);\n    else if (cmd[1] == \"back\")\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"vacuum\", math::vector3(-0.010, 0.0, 0.0), 0.2);\n    else if (cmd[1] == \"left\")\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"vacuum\", math::vector3(0.0, 0.010, 0.0), 0.2);\n    else if (cmd[1] == \"right\")\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"vacuum\", math::vector3(0.0, -0.010, 0.0), 0.2);\n    else if (cmd[1] == \"up\")\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"vacuum\", math::vector3(0.0, 0.0, 0.010), 0.2);\n    else if (cmd[1] == \"down\")\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"vacuum\", math::vector3(0.0, 0.0, -0.010), 0.2);\n    else\n      open_manipulator->makeTaskTrajectoryFromPresentPose(\"vacuum\", math::vector3(0.0, 0.0, 0.0), 0.2);\n  }\n  else if (cmd[0] == \"torque\")\n  {\n    if(platform_state_processing)\n    {\n      if (cmd[1] == \"on\")\n        open_manipulator->enableAllJointActuator();\n      else if (cmd[1] == \"off\")\n        open_manipulator->disableAllJointActuator();\n    }\n  }\n  ////////// hand teaching tab\n  else if (cmd[0] == \"get\")\n  {\n    if (cmd[1] == \"clear\")  // motion clear\n    {\n      processing_motion_state = false;\n      motion_way_point_buf.clear();\n      hand_motion_cnt = 0;\n    }\n    else if (cmd[1] == \"pose\")  // save pose\n    {\n      MotionWaypoint read_value;\n      JointWaypoint present_states = open_manipulator->getAllActiveJointValue();\n      for(int i = 0; i < present_states.size(); i ++)\n        read_value.angle.push_back(present_states.at(i).position);  \n      read_value.path_time = 2.0;\n      read_value.gripper_value = open_manipulator->getToolValue(\"vacuum\").position;\n      motion_way_point_buf.push_back(read_value);  \n      hand_motion_cnt = 0;\n    }\n    else if (cmd[1] == \"on\")  // save gripper on\n    {\n      open_manipulator->makeToolTrajectory(\"vacuum\", 1.0);\n    }\n    else if (cmd[1] == \"off\")  // save gripper off\n    {\n      open_manipulator->makeToolTrajectory(\"vacuum\", 0.0);\n    }\n  }\n  else if (cmd[0] == \"hand\")\n  {\n    if (cmd[1] == \"once\") // play motion (once)\n    {\n      processing_motion_state = true;//processing_motion_state;\n    }\n    else if (cmd[1] == \"repeat\") // play motion (repeat)\n    {\n      hand_motion_repeat_state = true;\n    }\n    else if (cmd[1] == \"stop\") // play motion (stop)\n    {\n      hand_motion_repeat_state = false;\n      processing_motion_state = false;\n      hand_motion_cnt = 0;\n    }\n  }\n  ////////// motion tab\n  else if (cmd[0] == \"motion\")\n  {\n    if (cmd[1] == \"1\")\n    {\n      TaskWaypoint draw_line_arg;\n      draw_line_arg.kinematic.position(0) = 0.02;\n      draw_line_arg.kinematic.position(1) = 0.02;\n      draw_line_arg.kinematic.position(2) = -0.02;\n      void *p_draw_line_arg = &draw_line_arg;\n            \n      open_manipulator->makeCustomTrajectory(CUSTOM_TRAJECTORY_LINE, \"vacuum\", p_draw_line_arg, 1.0);\n    }\n    else if (cmd[1] == \"2\")\n    {\n      double draw_circle_arg[3];\n      draw_circle_arg[0] = 0.03; // radius (m)\n      draw_circle_arg[1] = 2;    // revolution\n      draw_circle_arg[2] = 0.0;  // start angle position (rad)\n      void* p_draw_circle_arg = &draw_circle_arg;\n\n      open_manipulator->makeCustomTrajectory(CUSTOM_TRAJECTORY_CIRCLE, \"vacuum\", p_draw_circle_arg, 4.0);\n    }\n  }\n}\n\nvoid playProcessingMotion(OpenManipulatorVacuum *open_manipulator)\n{\n  if(!open_manipulator->getMovingState() && processing_motion_state)\n  {\n    if(motion_way_point_buf.size() == 0)\n      return;\n\n    open_manipulator->makeToolTrajectory(\"vacuum\", motion_way_point_buf.at(hand_motion_cnt).gripper_value);\n    open_manipulator->makeJointTrajectory(motion_way_point_buf.at(hand_motion_cnt).angle, motion_way_point_buf.at(hand_motion_cnt).path_time); \n    hand_motion_cnt ++;\n    if(hand_motion_cnt >= motion_way_point_buf.size())\n    {\n      hand_motion_cnt = 0;\n      if(!hand_motion_repeat_state)\n        processing_motion_state = false;\n    }\n  }\n}\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Delta/open_manipulator_delta/demo.h",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef DEMO_H_\n#define DEMO_H_\n\n#include <delta_libs.h>\n\nbool start_demo_flag;\nuint8_t motion_cnt[] = {0};\nuint8_t sub_motion_cnt[] = {0};\n\nconst double hole[10][3] = {{ 0.0580, -0.0340, 0.023},  // Ball 1 \n                            { 0.0000, -0.0690, 0.023},  // Ball 2\n                            {-0.0563, -0.0360, 0.023},  // Ball 3\n                            {-0.0570,  0.0315, 0.023},  // Ball 4\n                            {-0.0000,  0.0660, 0.023},  // Ball 5\n                            { 0.0580,  0.0335, 0.023},  // Ball 6\n                            { 0.0000,  0.0173, 0.023},  // Ball 7\n                            {-0.0150, -0.0087, 0.023},  // Ball 8\n                            { 0.0150, -0.0087, 0.023},  // Ball 9\n                            { 0.0000,  0.0000, 0.042}}; // Centre\n                                  \n/*****************************************************************************\n** Functions used in runDemo()\n*****************************************************************************/\n// Move in Joint Space \nbool touchBall(Delta *delta, int num, double t, int index)\n{\n  switch(sub_motion_cnt[index])\n  {\n  case 0: delta->makeTaskTrajectory(\"tool\", math::vector3(hole[num-1][0], hole[num-1][1], hole[num-1][2]+0.015), t); break;\n  case 1: delta->makeTaskTrajectory(\"tool\", math::vector3(hole[num-1][0], hole[num-1][1], hole[num-1][2]), t); break;\n  case 2: delta->makeTaskTrajectory(\"tool\", math::vector3(hole[num-1][0], hole[num-1][1], hole[num-1][2]+0.015), t); return 1; \n  }\n  return 0;\n}\n\nvoid suctionOnOff(bool onoff)\n{\n  if (onoff)\n  {\n    pinMode(4, OUTPUT);\n    pinMode(7, OUTPUT);\n    pinMode(8, OUTPUT);\n    pinMode(12, OUTPUT);\n    digitalWrite(8, HIGH);      //suction on\n    digitalWrite(12, HIGH);     //suction on\n  } \n  else \n  {\n    pinMode(4, OUTPUT);\n    pinMode(7, OUTPUT);\n    pinMode(8, OUTPUT);\n    pinMode(12, OUTPUT);\n    digitalWrite(8, LOW);      //suction off\n    digitalWrite(12, LOW);     //suction off\n  }\n}\n\nbool moveBall(Delta *delta, int num1, int num2, double t, int index)\n{\n  switch(sub_motion_cnt[index])\n  {\n  case 0: delta->makeTaskTrajectory(\"tool\", math::vector3(hole[num1-1][0], hole[num1-1][1], hole[num2-1][2]+0.015), t); break;\n  case 1: delta->makeTaskTrajectory(\"tool\", math::vector3(hole[num1-1][0], hole[num1-1][1], hole[num1-1][2]), t); suctionOnOff(true); break;\n  case 2: delta->sleepTrajectory(1.0); break;\n  case 3: delta->makeTaskTrajectory(\"tool\", math::vector3(hole[num1-1][0], hole[num1-1][1], hole[num2-1][2]+0.015), t); break;\n  case 4: delta->makeTaskTrajectory(\"tool\", math::vector3(hole[num2-1][0], hole[num2-1][1], hole[num2-1][2]+0.015), t); break;\n  case 5: delta->makeTaskTrajectory(\"tool\", math::vector3(hole[num2-1][0], hole[num2-1][1], hole[num2-1][2]), t); break;\n  case 6: delta->sleepTrajectory(1.0); suctionOnOff(false); break;\n  case 7: delta->makeTaskTrajectory(\"tool\", math::vector3(hole[num2-1][0], hole[num2-1][1], hole[num2-1][2]+0.015), t); return 1;\n  }\n  return 0;\n}\n\n// Draw an Object \nvoid drawObj(Delta *delta, STRING object, double radius, int num_revolution, double start_angular_position, double move_time)\n{\n  double draw_arg[3]; \n  draw_arg[0] = radius;                 // Radius (m)\n  draw_arg[1] = num_revolution;         // Number of revolution\n  draw_arg[2] = start_angular_position; // Starting angular position (rad)\n  void *p_draw_arg = &draw_arg;\n\n  delta->makeCustomTrajectory(object, \"tool\", p_draw_arg, move_time);\n}\n\n/*****************************************************************************\n** Start or Stop Demo\n*****************************************************************************/\nvoid startDemo()\n{\n  // Start the demo\n  start_demo_flag = true;\n}\n\nvoid stopDemo(Delta *delta)\n{\n  // Stop the demo\n  start_demo_flag = false;\n\n  // Move to the default pose.\n  delta->makeTaskTrajectory(\"tool\", math::vector3(0.0, 0.0, 0.0), 2.0);\n\n  // Reset the count variables\n  motion_cnt[0] = 0;\n  sub_motion_cnt[0] = 0;\n}\n\n/*****************************************************************************\n** Initialize Demo\n*****************************************************************************/\nvoid initDemo()\n{\n  start_demo_flag = false;\n  motion_cnt[0] = 0;\n  sub_motion_cnt[0] = 0;\n}\n\n/*****************************************************************************\n** Run Demo\n*****************************************************************************/\nvoid runDemo(Delta *delta)\n{\n  if(digitalRead(BDPIN_PUSH_SW_1))\n  {\n    startDemo();\n  }\n  if(digitalRead(BDPIN_PUSH_SW_2))\n  {\n    stopDemo(delta);    \n  }\n\n  if (delta->getMovingState()) \n  {\n    return;\n  }\n  else \n  {\n    if (start_demo_flag)\n    {\n      switch(motion_cnt[0])\n      {\n        case 0:\n          if(touchBall(delta, 1, 0.07, 0)) \n          { sub_motion_cnt[0] = 0; motion_cnt[0] ++; }\n          else \n            sub_motion_cnt[0] ++;\n        break;\n        case 1:\n          if(touchBall(delta, 2, 0.07, 0)) \n          { sub_motion_cnt[0] = 0; motion_cnt[0] ++; }\n          else \n            sub_motion_cnt[0] ++;\n        break;\n        case 2:\n          if(touchBall(delta, 3, 0.07, 0)) \n          { sub_motion_cnt[0] = 0; motion_cnt[0] ++; }\n          else \n            sub_motion_cnt[0] ++;\n        break;\n        case 3:\n          if(touchBall(delta, 4, 0.07, 0)) \n          { sub_motion_cnt[0] = 0; motion_cnt[0] ++; }\n          else \n            sub_motion_cnt[0] ++;\n        break;\n        case 4:\n          if(touchBall(delta, 5, 0.07, 0))\n          { sub_motion_cnt[0] = 0; motion_cnt[0] ++; }\n          else \n            sub_motion_cnt[0] ++;\n        break;\n        case 5:\n          if(touchBall(delta, 6, 0.07, 0)) \n          { sub_motion_cnt[0] = 0; motion_cnt[0] ++; }\n          else \n            sub_motion_cnt[0] ++;\n        break;\n        case 6:\n          if(touchBall(delta, 5, 0.07, 0))\n          { sub_motion_cnt[0] = 0; motion_cnt[0] ++; }\n          else \n            sub_motion_cnt[0] ++;\n        break;\n        case 7:\n          if(touchBall(delta, 4, 0.07, 0)) \n          { sub_motion_cnt[0] = 0; motion_cnt[0] ++; }\n          else \n            sub_motion_cnt[0] ++;\n        break;\n        case 8:\n          if(touchBall(delta, 3, 0.07, 0)) \n          { sub_motion_cnt[0] = 0; motion_cnt[0] ++; }\n          else \n            sub_motion_cnt[0] ++;\n        break;\n        case 9:\n          if(touchBall(delta, 2, 0.07, 0)) \n          { sub_motion_cnt[0] = 0; motion_cnt[0] ++; }\n          else \n            sub_motion_cnt[0] ++;\n        break;\n        case 10:\n          if(touchBall(delta, 1, 0.07, 0)) \n          { sub_motion_cnt[0] = 0; motion_cnt[0] ++; }\n          else \n            sub_motion_cnt[0] ++;\n        break;\n        case 11:\n          if(moveBall(delta, 1, 9, 0.15, 0)) \n          { sub_motion_cnt[0] = 0; motion_cnt[0] ++; }\n          else \n            sub_motion_cnt[0] ++;\n        break;\n        case 12:\n          if(moveBall(delta, 3, 8, 0.15, 0)) \n          { sub_motion_cnt[0] = 0; motion_cnt[0] ++; }\n          else \n            sub_motion_cnt[0] ++;\n        break;\n        case 13:\n          if(moveBall(delta, 5, 7, 0.15, 0)) \n          { sub_motion_cnt[0] = 0; motion_cnt[0] ++; }\n          else \n            sub_motion_cnt[0] ++;\n        break;\n        case 14:\n          if(moveBall(delta, 6, 10, 0.15, 0)) \n          { sub_motion_cnt[0] = 0; motion_cnt[0] ++; }\n          else \n            sub_motion_cnt[0] ++;\n        break;\n        case 15:\n          if(moveBall(delta, 10, 6, 0.15, 0))\n          { sub_motion_cnt[0] = 0; motion_cnt[0] ++; }\n          else \n            sub_motion_cnt[0] ++;\n        break;\n        case 16:\n          if(moveBall(delta, 7, 5, 0.15, 0)) \n          { sub_motion_cnt[0] = 0; motion_cnt[0] ++; }\n          else \n            sub_motion_cnt[0] ++;\n        break;\n        case 17:\n          if(moveBall(delta, 8, 3, 0.15, 0)) \n          { sub_motion_cnt[0] = 0; motion_cnt[0] ++; }\n          else \n            sub_motion_cnt[0] ++;\n        break;\n        case 18:\n          if(moveBall(delta, 9, 1, 0.15, 0)) \n          { sub_motion_cnt[0] = 0; motion_cnt[0] ++; }\n          else \n            sub_motion_cnt[0] ++;\n        break;\n        case 19:\n          delta->makeTaskTrajectory(\"tool\", math::vector3(0,0,0), 1.0);\n        break;        \n      }\n    }\n  }\n}\n\n#endif // DEMO_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Delta/open_manipulator_delta/open_manipulator_delta.ino",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include <delta_libs.h>\n#include \"remotecontroller100.h\"\n#include \"processing.h\"\n#include \"demo.h\"\n\nDelta delta;\n\nvoid setup()\n{\n  delta.initDebug();\n\n  initRC100();\n\n  initProcessing();\n\n  initDemo();\n\n  delta.initOpenManipulator(true); // true:  using actual hardware\n                                   // false: using only visualization tool\n}\n\nvoid loop()\n{\n  receiveDataFromRC100(&delta);\n\n  receiveDataFromProcessing(&delta); \n  sendDataToProcessing(&delta);\n\n  delta.processOpenManipulator(millis()/1000.0);\n\n  runDemo(&delta);\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Delta/open_manipulator_delta/processing.h",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef PROCESSING_H_\n#define PROCESSING_H_\n\n#include <delta_libs.h>\n#include \"demo.h\"\n\n/*****************************************************************************\n** Initialize baudrate for using Processing\n*****************************************************************************/\nvoid initProcessing()\n{ \n  Serial.begin(57600);\n  \n  Serial.print(\"Initial actuator angles: \");\n  for (int i = 0; i < DXL_SIZE; i++)\n  {\n    Serial.print(0.0);\n    Serial.print(\",\");\n  }\n  Serial.println(\"\");\n  delay(300);             \n}\n\n/*****************************************************************************\n** Send data from Processing\n*****************************************************************************/\n// Send joint data to Processing \nvoid sendJointDataToProcessing(JointWaypoint joint_angle_vector) \n{\n  Serial.print(\"joint\");\n\n  for (int i = 0; i < (int)joint_angle_vector.size(); i++)\n  {\n    Serial.print(\",\");\n    Serial.print(joint_angle_vector.at(i).position,3);\n  }\n  Serial.print(\"\\n\");\n}\n\n// Send tool data(on or off) to Processing \nvoid sendToolDataToProcessing(bool onoff)\n{\n  Serial.print(\"tool\");\n  Serial.print(\",\");\n  Serial.print(onoff);\n  Serial.print(\"\\n\");\n}\n\n// Send tool data(values) to Processing \nvoid sendToolDataToProcessing(JointValue value)\n{\n  Serial.print(\"tool\");\n  Serial.print(\",\");\n  Serial.print(value.position);\n  Serial.print(\"\\n\");\n}\n\n// Send joint and tool data(values) to Processing \nvoid sendDataToProcessing(Delta *delta)\n{\n  sendJointDataToProcessing(delta->getTrajectory()->getManipulator()->getAllJointValue());\n}\n\n/*****************************************************************************\n** Receive data from Processing\n*****************************************************************************/\n// Split data by separator \nvoid split(String data, char separator, String* temp)\n{\n  int cnt = 0;\n  int get_index = 0;\n\n  String copy = data;\n  \n  while(true)\n  {\n    get_index = copy.indexOf(separator);\n\n    if(-1 != get_index)\n    {\n      temp[cnt] = copy.substring(0, get_index);\n      copy = copy.substring(get_index + 1);\n    }\n    else\n    {\n      temp[cnt] = copy.substring(0, copy.length());\n      break;\n    }\n    ++cnt;\n  }\n}\n\n// Parse data received from Processing \nString cmd[50];\nString* parseProcessingData(String get) \n{\n  get.trim();\n  split(get, ',', cmd);\n  \n  return cmd;\n}\n\n// Receive data from Processing \nvoid receiveDataFromProcessing(Delta *delta) \n{\n  if (!delta->getReceiveDataFlag())\n  {\n    if (Serial.available())\n    {\n      String serialInput = Serial.readStringUntil('\\n');\n      String *cmd = parseProcessingData(serialInput);\n\n      // Actuator Control Tab \n      if (cmd[0] == \"actuator\")\n      {\n        // Torque On/Off\n        if (cmd[1] == \"on\")\n        {\n          if(delta->getUsingActualRobotState())\n          {\n            delta->enableAllActuator();\n            sendDataToProcessing(delta);\n          }\n        }\n        else if (cmd[1] == \"off\")\n        {\n          if(delta->getUsingActualRobotState())\n          {\n            delta->disableAllActuator();\n          }\n        }\n      }\n\n      // Joint space control tab \n      else if (cmd[0] == \"joint\")\n      {\n        // Joint Torque on/off\n        if (cmd[1] == \"on\")\n        {\n          if (delta->getUsingActualRobotState())    \n          {\n            delta->enableAllJointActuator();\n            sendJointDataToProcessing(delta->getAllActiveJointValue());\n          }\n        }\n        else if (cmd[1] == \"off\")\n        {\n          if (delta->getUsingActualRobotState())    \n            delta->disableAllJointActuator();\n        }\n\n        // Joint Position Control\n        // else\n        // {\n        //   std::vector<double> goal_position;\n        //   for (uint8_t index = 0; index < DXL_SIZE; index++)\n        //   {\n        //     goal_position.push_back((double)cmd[index + 1].toFloat());\n        //   }\n        //   delta->makeJointTrajectory(goal_position, 1.0); \n        // }\n      }\n\n      // Tool control tab \n      else if (cmd[0] == \"tool\")\n      {\n        if (cmd[1] == \"y\")\n          suctionOnOff(true);\n        else if (cmd[1] == \"n\")\n          suctionOnOff(false);\n      }\n\n      // Task space control tab \n      else if (cmd[0] == \"task\")\n      {\n        // if (cmd[1] == \"f\")\n        //   delta->makeTaskTrajectory(\"tool\", math::vector3(0.020, 0.0, 0.0), 0.1);\n        // else if (cmd[1] == \"b\")\n        //   delta->makeTaskTrajectory(\"tool\", math::vector3(-0.020, 0.0, 0.0), 0.1);\n        // else if (cmd[1] == \"l\")\n        //   delta->makeTaskTrajectory(\"tool\", math::vector3(0.0, 0.020, 0.0), 0.1);\n        // else if (cmd[1] == \"r\")\n        //   delta->makeTaskTrajectory(\"tool\", math::vector3(0.0, -0.020, 0.0), 0.1);\n        // else if (cmd[1] == \"u\")\n        //   delta->makeTaskTrajectory(\"tool\", math::vector3(0.0, 0.0, 0.015), 0.1);\n        // else if (cmd[1] == \"d\")\n        //   delta->makeTaskTrajectory(\"tool\", math::vector3(0.0, 0.0, -0.010), 0.1);\n        // else\n        //   delta->makeTaskTrajectory(\"tool\", math::vector3(0.0, 0.0, 0.0), 0.1);\n        if (cmd[1] == \"f\")\n          delta->makeTaskTrajectory(\"tool\", math::vector3(0.040, 0.0, 0.02), 0.1);\n        else if (cmd[1] == \"b\")\n          delta->makeTaskTrajectory(\"tool\", math::vector3(-0.040, 0.0, 0.02), 0.1);\n        else if (cmd[1] == \"l\")\n          delta->makeTaskTrajectory(\"tool\", math::vector3(0.0, 0.040, 0.02), 0.1);\n        else if (cmd[1] == \"r\")\n          delta->makeTaskTrajectory(\"tool\", math::vector3(0.0, -0.040, 0.02), 0.1);\n        else if (cmd[1] == \"u\")\n          delta->makeTaskTrajectory(\"tool\", math::vector3(0.0, 0.0, 0.05), 0.1);\n        else if (cmd[1] == \"d\")\n          delta->makeTaskTrajectory(\"tool\", math::vector3(0.0, 0.0, -0.010), 0.1);\n        else\n          delta->makeTaskTrajectory(\"tool\", math::vector3(0.0, 0.0, 0.0), 0.1);\n      }\n\n      // Demo Control tab \n      else if (cmd[0] == \"demo\")\n      {\n        if (cmd[1] == \"start\")\n          startDemo();\n        else if (cmd[1] == \"stop\")\n          stopDemo(delta);\n      }\n\n//----------------------------------------------//\n//         DO NOT MODIFY THE BELOW CODE         //\n//----------------------------------------------//\n      delta->setReceiveDataFlag(true);\n      delta->setPrevReceiveTime(millis()/1000.0); \n    }\n  }\n  else\n  {\n    if (millis()/1000.0 - delta->getPrevReceiveTime() >= RECEIVE_RATE)\n    {\n      delta->setReceiveDataFlag(false); \n      initRC100();\n    }\n  }\n}\n\n#endif  //PROCESSING_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Delta/open_manipulator_delta/remotecontroller100.h",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef REMOTECONTROLLER100_H_\n#define REMOTECONTROLLER100_H_\n\n#include <delta_libs.h>\n#include <RC100.h>\n#include \"demo.h\"\n\nRC100 rc100;\ndouble grip_value = 0.0;\n\n/*****************************************************************************\n** Initialize baudrate for using RC100\n*****************************************************************************/\nvoid initRC100()\n{\n  rc100.begin(1); // Using Serial2(=SerialBT1)\n}\n\n/*****************************************************************************\n** Receive data from RC100\n*****************************************************************************/\nvoid receiveDataFromRC100(Delta* delta)\n{\n  if (!delta->getReceiveDataFlag())\n  {\n    if (rc100.available())\n    {\n      delta->setReceiveDataFlag(true);\n\n      uint16_t data = rc100.readData();\n\n      // Task space control tab \n      if (data & RC100_BTN_U) \n        delta->makeTaskTrajectory(\"tool\", math::vector3(0.020, 0.0, 0.0), 0.1);\n      else if (data & RC100_BTN_L) \n        delta->makeTaskTrajectory(\"tool\", math::vector3(-0.020, 0.0, 0.0), 0.1);\n      else if (data & RC100_BTN_D)\n        delta->makeTaskTrajectory(\"tool\", math::vector3(0.0, 0.020, 0.0), 0.1);\n      else if (data & RC100_BTN_R) \n        delta->makeTaskTrajectory(\"tool\", math::vector3(0.0, -0.020, 0.0), 0.1);\n      else if (data & RC100_BTN_1)\n        delta->makeTaskTrajectory(\"tool\", math::vector3(0.0, 0.0, 0.015), 0.1);\n      else if (data & RC100_BTN_2)\n        delta->makeTaskTrajectory(\"tool\", math::vector3(0.0, 0.0, -0.015), 0.1);\n      else if (data & RC100_BTN_3) \n        startDemo();\n      else if (data & RC100_BTN_4)         \n        stopDemo(delta);\n      else if (data & RC100_BTN_5) {}\n      else if (data & RC100_BTN_6)\n      {\n        std::vector<double> goal_position;\n        goal_position.push_back(0.0);\n        goal_position.push_back(0.0);\n        goal_position.push_back(0.0);\n        delta->makeJointTrajectory(goal_position, 1.0);\n      }\n      \n//----------------------------------------------//\n//         DO NOT MODIFY THE BELOW CODE         //\n//----------------------------------------------//\n      delta->setReceiveDataFlag(true);\n      delta->setPrevReceiveTime(millis()/1000.0); \n    }\n  }\n  else \n  {\n    if (millis()/1000.0 - delta->getPrevReceiveTime() >= RECEIVE_RATE)\n    {\n      delta->setReceiveDataFlag(false);   \n      initRC100();\n    }\n  }\n}\n\n#endif // REMOTECONTROLLER100_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Linear/open_manipulator_linear/demo.h",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef DEMO_H_\n#define DEMO_H_\n\n#include <linear_libs.h>\n\nbool start_demo_flag;\nuint8_t motion_cnt[] = {0};\nuint8_t sub_motion_cnt[] = {0};\n\n/*****************************************************************************\n** Start or Stop Demo\n*****************************************************************************/\nvoid startDemo()\n{\n  // Start the demo\n  start_demo_flag = true;\n}\n\nvoid stopDemo(Linear *linear)\n{\n  // Stop the demo\n  start_demo_flag = false;\n\n  // Move to the default pose.\n  std::vector<double> target_angle;\n  target_angle.push_back(0.0);\n  target_angle.push_back(0.0);\n  target_angle.push_back(0.0);\n  linear->makeJointTrajectory(target_angle, 1);\n  linear->makeToolTrajectory(\"tool\", -0.007);\n\n  // Reset the count variables\n  motion_cnt[0] = 0;\n  sub_motion_cnt[0] = 0;\n}\n\n/*****************************************************************************\n** Initialize Demo\n*****************************************************************************/\nvoid initDemo()\n{\n  start_demo_flag = false;\n  motion_cnt[0] = 0;\n  sub_motion_cnt[0] = 0;  \n}\n\n/*****************************************************************************\n** Run Demo\n*****************************************************************************/\nvoid runDemo(Linear *linear)\n{\n  if(digitalRead(BDPIN_PUSH_SW_1))\n  {\n    startDemo();\n  }\n  if(digitalRead(BDPIN_PUSH_SW_2))\n  {\n    stopDemo(linear);    \n  }\n\n  if (linear->getMovingState())\n  {\n    return;\n  }\n  else\n  {\n    if (start_demo_flag)\n    {\n      switch(motion_cnt[0])\n      {\n        case 0:\n          linear->makeToolTrajectory(\"tool\", -0.49);\n          linear->sleepTrajectory(2.0);\n          motion_cnt[0] ++;\n        break;\n        case 1:\n          {\n          double joint_angle[2];\n          joint_angle[0] = linear->getJointValue(\"joint1\").position;\n          joint_angle[1] = linear->getJointValue(\"joint2\").position;\n          std::vector<double> target_angle;\n          target_angle.push_back(joint_angle[0]);\n          target_angle.push_back(joint_angle[1]);\n          target_angle.push_back(0.0);\n          linear->makeJointTrajectory(target_angle, 1.0);\n          motion_cnt[0] ++;\n          }\n        break;\n        case 2:\n          linear->makeToolTrajectory(\"tool\", 0.49);        \n          linear->sleepTrajectory(2.0); \n          motion_cnt[0] ++;\n        break;\n        case 3:\n          {\n          double joint_angle[2];\n          joint_angle[0] = linear->getJointValue(\"joint1\").position;\n          joint_angle[1] = linear->getJointValue(\"joint2\").position;\n          std::vector<double> target_angle;\n          target_angle.push_back(joint_angle[0]);\n          target_angle.push_back(joint_angle[1]);\n          target_angle.push_back(-2*PI);\n          linear->makeJointTrajectory(target_angle, 1.0);\n          motion_cnt[0] ++;\n          }\n        break;\n        case 4:\n          {\n          std::vector<double> target_angle;\n          target_angle.push_back(-4.899);\n          target_angle.push_back(-4.5);\n          target_angle.push_back(-2*PI);\n          linear->makeJointTrajectory(target_angle, 0.3);\n          motion_cnt[0] ++;\n          }\n        break;\n        case 5:\n          linear->sleepTrajectory(1.0); \n          motion_cnt[0] ++;\n        break;\n        case 6:\n          linear->makeToolTrajectory(\"tool\", -0.49);        \n          linear->sleepTrajectory(2.0); \n          motion_cnt[0] ++;\n        break;\n        case 7:\n          linear->makeToolTrajectory(\"tool\", 0.49);        \n          linear->sleepTrajectory(2.0); \n          motion_cnt[0] ++;\n        break;\n        case 8:\n          {\n          std::vector<double> target_angle;\n          target_angle.push_back(0.0);\n          target_angle.push_back(0.0);\n          target_angle.push_back(-2*PI);\n          linear->makeJointTrajectory(target_angle, 0.3);\n          motion_cnt[0] ++;\n          }\n        break;\n      }\n    }\n  }\n}\n\n#endif // DEMO_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Linear/open_manipulator_linear/open_manipulator_linear.ino",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include <linear_libs.h>\n#include \"remotecontroller100.h\"\n#include \"processing.h\"\n#include \"demo.h\"\n\nLinear linear;\n\nvoid setup()\n{\n  linear.initDebug();\n\n  initRC100();\n\n  initProcessing();\n\n  initDemo();\n\n  linear.initOpenManipulator(true); // true:  using actual hardware\n                                    // false: using only visualization tool\n}\n\nvoid loop()\n{\n  receiveDataFromRC100(&linear);\n\n  receiveDataFromProcessing(&linear);\n  sendDataToProcessing(&linear);\n\n  linear.processOpenManipulator(millis()/1000.0);\n\n  runDemo(&linear);\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Linear/open_manipulator_linear/processing.h",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef PROCESSING_H_\n#define PROCESSING_H_\n\n#include <linear_libs.h>\n#include \"demo.h\"\n\n/*****************************************************************************\n** Initialize baudrate for using Processing\n*****************************************************************************/\nvoid initProcessing()\n{ \n  Serial.begin(57600);\n\n  Serial.print(\"Initial actuator angles: \");\n  for (int i = 0; i < DXL_SIZE; i++)\n  {\n    Serial.print(0.0);\n    Serial.print(\",\");\n  }\n  Serial.println(\"\");\n  delay(300);             \n}\n\n/*****************************************************************************\n** Send data from Processing\n*****************************************************************************/\n// Send joint data to Processing \nvoid sendJointDataToProcessing(JointWaypoint joint_angle_vector) \n{\n  Serial.print(\"joint\");\n\n  for (int i = 0; i < (int)joint_angle_vector.size(); i++)\n  {\n    Serial.print(\",\");\n    Serial.print(joint_angle_vector.at(i).position,3);\n  }\n  Serial.print(\"\\n\");\n}\n\n// Send tool data(on or off) to Processing \nvoid sendToolDataToProcessing(bool onoff)\n{\n  Serial.print(\"tool\");\n  Serial.print(\",\");\n  Serial.print(onoff);\n  Serial.print(\"\\n\");\n}\n\n// Send tool data(values) to Processing \nvoid sendToolDataToProcessing(JointWaypoint tool_angle_vector)\n{\n  Serial.print(\"tool\");\n\n  for (int i = 0; i < (int)tool_angle_vector.size(); i++)\n  {\n    Serial.print(\",\");\n    Serial.print(tool_angle_vector.at(i).position,3);\n  }\n  Serial.print(\"\\n\");\n}\n\n// Send joint and tool data(values) to Processing \nvoid sendDataToProcessing(Linear *linear)\n{\n  sendJointDataToProcessing(linear->getTrajectory()->getManipulator()->getAllJointValue());\n  sendToolDataToProcessing(linear->getTrajectory()->getManipulator()->getAllToolValue());\n}\n\n/*****************************************************************************\n** Receive data from Processing\n*****************************************************************************/\n// Split data by separator \nvoid split(String data, char separator, String* temp)\n{\n  int cnt = 0;\n  int get_index = 0;\n\n  String copy = data;\n  \n  while(true)\n  {\n    get_index = copy.indexOf(separator);\n\n    if(-1 != get_index)\n    {\n      temp[cnt] = copy.substring(0, get_index);\n      copy = copy.substring(get_index + 1);\n    }\n    else\n    {\n      temp[cnt] = copy.substring(0, copy.length());\n      break;\n    }\n    ++cnt;\n  }\n}\n\n// Parse data received from Processing \nString cmd[50];\nString* parseProcessingData(String get) \n{\n  get.trim();\n  split(get, ',', cmd);\n  \n  return cmd;\n}\n\n// Receive data from Processing \nvoid receiveDataFromProcessing(Linear *linear) \n{\n  if (!linear->getReceiveDataFlag())\n  {\n    if (Serial.available())\n    {\n      String serialInput = Serial.readStringUntil('\\n');\n      String *cmd = parseProcessingData(serialInput);\n\n      // Actuator Control Tab \n      if (cmd[0] == \"actuator\")\n      {\n        // Torque On/Off\n        if (cmd[1] == \"on\")\n        {\n          if(linear->getUsingActualRobotState())\n          {\n            linear->enableAllActuator();\n            sendDataToProcessing(linear);\n          }\n        }\n        else if (cmd[1] == \"off\")\n        {\n          if(linear->getUsingActualRobotState())\n          {\n            linear->disableAllActuator();\n          }\n        }\n      }\n\n      // Joint space control tab \n      else if (cmd[0] == \"joint\")\n      {\n        // Joint Torque on/off\n        if (cmd[1] == \"on\")\n        {\n          if (linear->getUsingActualRobotState())    \n          {\n            linear->enableAllJointActuator();\n            sendJointDataToProcessing(linear->getAllActiveJointValue());\n          }\n        }\n        else if (cmd[1] == \"off\")\n        {\n          if (linear->getUsingActualRobotState())    \n            linear->disableAllJointActuator();\n        }\n\n        // Joint Position Control\n        else\n        {\n          std::vector<double> goal_position;\n          for (uint8_t index = 0; index < DXL_SIZE; index++)\n          {\n            goal_position.push_back((double)cmd[index + 1].toFloat());\n          }\n          linear->makeJointTrajectory(goal_position, 1.0); \n        }\n      }\n\n      // Tool control tab \n      else if (cmd[0] == \"tool\")\n      {\n        // Tool Torque on/off\n        if (cmd[1] == \"y\")\n          linear->makeToolTrajectory(\"tool\", -0.49);\n        else if (cmd[1] == \"n\")\n          linear->makeToolTrajectory(\"tool\", 0.49);\n\n        // Torque On/Off\n        else if (cmd[1] == \"on\")\n        {\n          if (linear->getUsingActualRobotState())    \n            linear->enableAllToolActuator();\n        }\n        else if (cmd[1] == \"off\")\n        {\n          if (linear->getUsingActualRobotState())    \n            linear->disableAllToolActuator();\n        }\n\n        // Tool Position Control\n        else\n          linear->makeToolTrajectory(\"tool\", (double)cmd[1].toFloat());\n      }\n\n      // Task space control tab \n      else if (cmd[0] == \"task\")\n      {\n        if (cmd[1] == \"f\")\n          linear->makeTaskTrajectoryFromPresentPose(\"tool\", math::vector3(0.006, 0.0, 0.0), 0.2);\n        else if (cmd[1] == \"b\")\n          linear->makeTaskTrajectoryFromPresentPose(\"tool\", math::vector3(-0.006, 0.0, 0.0), 0.2);\n        else if (cmd[1] == \"l\")\n          linear->makeTaskTrajectoryFromPresentPose(\"tool\", math::vector3(0.0, 0.006, 0.0), 0.2);\n        else if (cmd[1] == \"r\")\n          linear->makeTaskTrajectoryFromPresentPose(\"tool\", math::vector3(0.0, -0.006, 0.0), 0.2);\n        else\n          linear->makeTaskTrajectory(\"tool\", math::vector3(0.0, 0.0, 0.0), 0.2);\n      }\n\n      // Demo Control tab \n      else if (cmd[0] == \"demo\")\n      {\n        if (cmd[1] == \"start\")\n          startDemo();\n        else if (cmd[1] == \"stop\")\n          stopDemo(linear);\n      }\n\n//----------------------------------------------//\n//         DO NOT MODIFY THE BELOW CODE         //\n//----------------------------------------------//\n      linear->setReceiveDataFlag(true);\n      linear->setPrevReceiveTime(millis()/1000.0); \n    }\n  }\n  else\n  {\n    if (millis()/1000.0 - linear->getPrevReceiveTime() >= RECEIVE_RATE)\n    {\n      linear->setReceiveDataFlag(false); \n      initRC100();\n    }\n  }\n}\n\n#endif //PROCESSING_H"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Linear/open_manipulator_linear/remotecontroller100.h",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef REMOTECONTROLLER100_H_\n#define REMOTECONTROLLER100_H_\n\n#include <linear_libs.h>\n#include <RC100.h>\n#include \"demo.h\"\n\nRC100 rc100;\n\n/*****************************************************************************\n** Initialize baudrate for using RC100\n*****************************************************************************/\nvoid initRC100()\n{\n  rc100.begin(1); // Using Serial2(=SerialBT1)\n}\n\n/*****************************************************************************\n** Receive data from RC100\n*****************************************************************************/\nvoid receiveDataFromRC100(Linear* linear)\n{\n  if (!linear->getReceiveDataFlag())\n  {\n    if (rc100.available())\n    {\n      // Read data received from RC100\n      uint16_t data = rc100.readData();\n      if (data & RC100_BTN_U)\n        linear->makeTaskTrajectory(\"tool\", math::vector3(0.006, 0.0, 0.0), 0.2);\n      else if (data & RC100_BTN_D)\n        linear->makeTaskTrajectory(\"tool\", math::vector3(-0.006, 0.0, 0.0), 0.2);\n      else if (data & RC100_BTN_L)\n        linear->makeTaskTrajectory(\"tool\", math::vector3(0.0, 0.006, 0.0), 0.2);\n      else if (data & RC100_BTN_R)\n        linear->makeTaskTrajectory(\"tool\", math::vector3(0.0, -0.006, 0.0), 0.2);\n      else if (data & RC100_BTN_1)\n        linear->makeToolTrajectory(\"tool\", -0.007);\n      else if (data & RC100_BTN_2)\n        linear->makeToolTrajectory(\"tool\", 0.007);\n      else if (data & RC100_BTN_3)\n        startDemo();\n      else if (data & RC100_BTN_4)\n        stopDemo(linear);\n      else if (data & RC100_BTN_5) {}\n      else if (data & RC100_BTN_6)\n      {\n        std::vector<double> target_angle;\n        target_angle.push_back(0.0);\n        target_angle.push_back(0.0);\n        target_angle.push_back(0.0);\n        linear->makeJointTrajectory(target_angle, 1.0);\n      }\n      \n//----------------------------------------------//\n//         DO NOT MODIFY THE BELOW CODE         //\n//----------------------------------------------//\n      linear->setReceiveDataFlag(true);\n      linear->setPrevReceiveTime(millis()/1000.0);\n    }\n  }\n  else\n  {\n    if (millis()/1000.0 - linear->getPrevReceiveTime() >= RECEIVE_RATE)\n    {\n      linear->setReceiveDataFlag(false);\n      initRC100();\n    }\n  }\n}\n#endif // REMOTECONTROLLER100_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Link/open_manipulator_link/link.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Hye-Jong KIM */\n\n#ifndef LINK_H_\n#define LINK_H_\n\n// Necessary library\n#include <open_manipulator_libs.h>\n\n// User-defined library\n#include \"link_kinematics.h\"\n#include \"vacuum_actuator.h\"\n\n/////////////custom trajectory///////////////\n#define CUSTOM_TRAJECTORY_SIZE 4\n#define CUSTOM_TRAJECTORY_LINE    \"custom_trajectory_line\"\n#define CUSTOM_TRAJECTORY_CIRCLE  \"custom_trajectory_circle\"\n#define CUSTOM_TRAJECTORY_RHOMBUS \"custom_trajectory_rhombus\"\n#define CUSTOM_TRAJECTORY_HEART   \"custom_trajectory_heart\"\n////////////////////////////////////////////\n\n/////////////control time set////////////////\n#define ACTUATOR_CONTROL_TIME 0.010\n////////////////////////////////////////////\n\n//////////////Vacuum Pin Num////////////////\n#define RELAY_PIN 8\n////////////////////////////////////////////\n\n////////////////////////////////////////////\n#define X_AXIS robotis_manipulator::math::vector3(1.0, 0.0, 0.0)\n#define Y_AXIS robotis_manipulator::math::vector3(0.0, 1.0, 0.0)\n#define Z_AXIS robotis_manipulator::math::vector3(0.0, 0.0, 1.0)\n////////////////////////////////////////////\n\nclass OpenManipulatorLink : public robotis_manipulator::RobotisManipulator\n{\n private:\n  robotis_manipulator::Kinematics *kinematics_;\n  robotis_manipulator::JointActuator *joint_actuator_;\n  robotis_manipulator::ToolActuator *tool_actuator_;\n  robotis_manipulator::CustomTaskTrajectory *custom_trajectory_[CUSTOM_TRAJECTORY_SIZE];\n\n  // bool processing_;\n  std::vector<uint8_t> jointDxlId;\n\n public:\n  OpenManipulatorLink(){}\n  virtual ~OpenManipulatorLink(){}\n\n  void initManipulator(bool using_platform, STRING usb_port = \"/dev/ttyACM0\", STRING baud_rate = \"1000000\", float control_loop_time = 0.010)\n  {\n    /*****************************************************************************\n    ** Initialize Manipulator Parameter \n    *****************************************************************************/\n    addWorld(\"world\", \"joint01\");\n    addJoint(\"joint01\", \"world\", \"joint02\",\n                            math::vector3(-0.23867882, 0, 0),\n                            math::convertRPYToRotationMatrix(0.0, 0.0, 0.0),\n                            Z_AXIS,\n                            1,\n                            M_PI,\n                            -M_PI,\n                            1.0);\n    addComponentChild(\"joint01\", \"joint03\");\n    addComponentChild(\"joint01\", \"joint08\");\n    addJoint(\"joint02\", \"joint01\", \"joint06\", \n                            math::vector3(0, 0.022, 0.052),\n                            math::convertRPYToRotationMatrix(0.0, 0.0, 0.0),\n                            Y_AXIS,\n                            2,\n                            0.0,\n                            -M_PI,\n                            -1.0\n                            );\n    addJoint(\"joint03\", \"joint01\", \"joint04\",\n                            math::vector3(0, -0.022, 0.052),\n                            math::convertRPYToRotationMatrix(0.0, 0.0, 0.0),\n                            Y_AXIS,\n                            3,\n                            -M_PI/4,\n                            -M_PI,\n                            1.0);\n    addJoint(\"joint04\", \"joint03\", \"joint05\",\n                            math::vector3(0.050, 0.007, 0),\n                            math::convertRPYToRotationMatrix(0.0, 0.0, 0.0),\n                            Y_AXIS);\n    addJoint(\"joint05\", \"joint04\", \"joint06\",\n                            math::vector3(0.200, 0.006, 0),\n                            math::convertRPYToRotationMatrix(0.0, 0.0, 0.0),\n                            Y_AXIS);\n    addJoint(\"joint06\", \"joint02\", \"joint07\",\n                            math::vector3(0.200, -0.016, 0),\n                            math::convertRPYToRotationMatrix(0.0, 0.0, 0.0),\n                            Y_AXIS);\n    addJoint(\"joint07\", \"joint06\", \"vacuum\",\n                            math::vector3(0.200, -0.009, 0),\n                            math::convertRPYToRotationMatrix(0.0, 0.0, 0.0),\n                            Y_AXIS);\n    addJoint(\"joint08\", \"joint01\", \"joint09\",\n                            math::vector3(-0.04531539, 0.006, 0.07313091),\n                            math::convertRPYToRotationMatrix(0.0, 0.0, 0.0),\n                            Y_AXIS);\n    addJoint(\"joint09\", \"joint08\", \"joint10\",\n                            math::vector3(0.200, 0.009, 0),\n                            math::convertRPYToRotationMatrix(0.0, 0.0, 0.0),\n                            Y_AXIS);\n    addJoint(\"joint10\", \"joint09\", \"joint11\",\n                            math::vector3(0.07660444, -0.006, 0),\n                            math::convertRPYToRotationMatrix(0.0, 0.0, 0.0),\n                            Y_AXIS);\n    addJoint(\"joint11\", \"joint10\", \"vacuum\",\n                            math::vector3(0.200, -0.006, 0),\n                            math::convertRPYToRotationMatrix(0.0, 0.0, 0.0),\n                            Y_AXIS);\n    addTool(\"vacuum\", \"joint07\",\n                        math::vector3(0.03867882, 0.003, -0.01337315-0.01),\n                        math::convertRPYToRotationMatrix(0.0, 0.0, 0.0),\n                        4,\n                        1.0);\n\n    /*****************************************************************************\n    ** Initialize Kinematics \n    *****************************************************************************/\n    kinematics_ = new kinematics::Link();\n    addKinematics(kinematics_);\n\n    if(using_platform)\n    {\n      /*****************************************************************************\n      ** Initialize ㅓoint Actuator\n      *****************************************************************************/\n      // actuator_ = new dynamixel::JointDynamixel();\n      joint_actuator_ = new dynamixel::JointDynamixelProfileControl(control_loop_time);\n      \n      // Set communication arguments\n      STRING dxl_comm_arg[2] = {usb_port, baud_rate};\n      void *p_dxl_comm_arg = &dxl_comm_arg;\n\n      // Set joint actuator id\n      std::vector<uint8_t> jointDxlId;\n      jointDxlId.push_back(1);\n      jointDxlId.push_back(2);\n      jointDxlId.push_back(3);\n      addJointActuator(\"joint_dxl\", joint_actuator_, jointDxlId, p_dxl_comm_arg);\n\n      // Set joint actuator control mode\n      STRING joint_dxl_mode_arg = \"position_mode\";\n      void *p_joint_dxl_mode_arg = &joint_dxl_mode_arg;\n      setJointActuatorMode(\"joint_dxl\", jointDxlId, p_joint_dxl_mode_arg);\n\n\n    /*****************************************************************************\n    ** Initialize Tool Actuator\n    *****************************************************************************/\n      tool_actuator_ = new VacuumModule();\n      uint8_t suc_pin_arg = RELAY_PIN;\n      void *p_suc_pin_arg = &suc_pin_arg;\n      addToolActuator(\"vacuum_module\", tool_actuator_, getManipulator()->getId(\"vacuum\"), p_suc_pin_arg);\n    \n      // Enable All Actuators \n      enableAllActuator();\n\n      // Receive current angles from all actuators \n      receiveAllJointActuatorValue();\n      receiveAllToolActuatorValue();\n    }\n\n    /*****************************************************************************\n    ** Initialize Custom Trajectory\n    *****************************************************************************/\n    custom_trajectory_[0] = new custom_trajectory::Line();\n    custom_trajectory_[1] = new custom_trajectory::Circle();\n    custom_trajectory_[2] = new custom_trajectory::Rhombus();\n    custom_trajectory_[3] = new custom_trajectory::Heart();\n\n    addCustomTrajectory(CUSTOM_TRAJECTORY_LINE, custom_trajectory_[0]);\n    addCustomTrajectory(CUSTOM_TRAJECTORY_CIRCLE, custom_trajectory_[1]);\n    addCustomTrajectory(CUSTOM_TRAJECTORY_RHOMBUS, custom_trajectory_[2]);\n    addCustomTrajectory(CUSTOM_TRAJECTORY_HEART, custom_trajectory_[3]);\n  }\n\n  void Process(double present_time)\n  {\n    JointWaypoint goal_joint_value = getJointGoalValueFromTrajectory(present_time);\n    JointWaypoint goal_tool_value  = getToolGoalValue();\n\n    receiveAllJointActuatorValue();\n    receiveAllToolActuatorValue();\n    if(goal_joint_value.size() != 0) sendAllJointActuatorValue(goal_joint_value);\n    if(goal_tool_value.size() != 0) sendAllToolActuatorValue(goal_tool_value);\n    solveForwardKinematics();\n  } \n};\n\n#endif //LINK_H_"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Link/open_manipulator_link/link_kinematics.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Hye-Jong KIM */\n\n#ifndef LINKKINEMATICS_H_\n#define LINKKINEMATICS_H_\n\n#if defined(__OPENCR__)\n  #include <RobotisManipulator.h>\n#else\n  #include <robotis_manipulator/robotis_manipulator.h>\n#endif\n\n\nusing namespace robotis_manipulator;\n\nnamespace kinematics\n{\n\n/*****************************************************************************\n** Kinematics Solver Using Chain Rule and Geometric Inverse For OpenManipulator Link\n*****************************************************************************/\nclass Link : public robotis_manipulator::Kinematics\n{\npublic:\n  Link(){}\n  virtual ~Link(){}\n\n  virtual void setOption(const void *arg){}\n\n  virtual Eigen::MatrixXd jacobian(Manipulator *manipulator, Name tool_name)\n  {\n    return {};\n  }\n\n  virtual void solveForwardKinematics(Manipulator *manipulator)\n  {\n    updatePassiveJointValue(manipulator);\n    forwardSolverUsingChainRule(manipulator, manipulator->getWorldChildName());\n  }\n\n  virtual bool solveInverseKinematics(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue>* goal_joint_value)\n  {\n    *goal_joint_value = geometricInverse(manipulator, tool_name, target_pose);\n    return true;\n  }\n\n  //private\n  void forwardSolverUsingChainRule(Manipulator *manipulator, Name component_name)\n  {\n    Name my_name = component_name;\n    Name parent_name = manipulator->getComponentParentName(my_name);\n    int8_t number_of_child = manipulator->getComponentChildName(my_name).size();\n\n    Pose parent_pose_value;\n    Pose my_pose_value;\n\n    //Get Parent Pose\n    if (parent_name == manipulator->getWorldName())\n    {\n      parent_pose_value = manipulator->getWorldPose();\n    }\n    else\n    {\n      parent_pose_value = manipulator->getComponentPoseFromWorld(parent_name);\n    }\n\n    //position\n    my_pose_value.kinematic.position = parent_pose_value.kinematic.position\n                                    + (parent_pose_value.kinematic.orientation * manipulator->getComponentRelativePositionFromParent(my_name));\n    //orientation\n    my_pose_value.kinematic.orientation = parent_pose_value.kinematic.orientation * math::rodriguesRotationMatrix(manipulator->getAxis(my_name), manipulator->getJointPosition(my_name));\n    //linear velocity\n    my_pose_value.dynamic.linear.velocity = math::vector3(0.0, 0.0, 0.0);\n    //angular velocity\n    my_pose_value.dynamic.angular.velocity = math::vector3(0.0, 0.0, 0.0);\n    //linear acceleration\n    my_pose_value.dynamic.linear.acceleration = math::vector3(0.0, 0.0, 0.0);\n    //angular acceleration\n    my_pose_value.dynamic.angular.acceleration = math::vector3(0.0, 0.0, 0.0);\n\n    manipulator->setComponentPoseFromWorld(my_name, my_pose_value);\n\n    for (int8_t index = 0; index < number_of_child; index++)\n    {\n      Name child_name = manipulator->getComponentChildName(my_name).at(index);\n      forwardSolverUsingChainRule(manipulator, child_name);\n    }\n  }\n\n  std::vector<JointValue> geometricInverse(Manipulator *manipulator, Name tool_name, Pose target_pose) //for basic model);\n  {\n    std::vector<JointValue> target_angle_vector;\n    Eigen::Vector3d control_position; //joint6-joint1\n    Eigen::Vector3d tool_relative_position = manipulator->getComponentRelativePositionFromParent(tool_name);\n    Eigen::Vector3d base_position = manipulator->getComponentPositionFromWorld(manipulator->getWorldChildName());\n    Eigen::Vector3d temp_vector;\n\n    JointValue target_angle[3];\n    double link[3];\n    double temp_x;\n    double temp_y;\n\n    temp_x = target_pose.kinematic.position(0) - base_position(0);\n    temp_y = target_pose.kinematic.position(1) - base_position(1);\n    target_angle[0].position = atan2(temp_y, temp_x);\n\n    control_position(0) = target_pose.kinematic.position(0) - tool_relative_position(0) * cos(target_angle[0].position);\n    control_position(1) = target_pose.kinematic.position(1) - tool_relative_position(0) * sin(target_angle[0].position);\n    control_position(2) = target_pose.kinematic.position(2) - tool_relative_position(2);\n\n    temp_vector = manipulator->getComponentRelativePositionFromParent(manipulator->getComponentParentName(manipulator->getComponentParentName(manipulator->getComponentParentName(tool_name))));\n    link[0] = temp_vector(2);\n    temp_vector = manipulator->getComponentRelativePositionFromParent(manipulator->getComponentParentName(manipulator->getComponentParentName(tool_name)));\n    link[1] = temp_vector(0);\n    temp_vector = manipulator->getComponentRelativePositionFromParent(manipulator->getComponentParentName(tool_name));\n    link[2] = temp_vector(0);\n\n    temp_y = control_position(2) - base_position(2) - link[0];\n    temp_x = (control_position(0) - base_position(0)) / cos(target_angle[0].position);\n\n    target_angle[1].position = -(acos(((temp_x * temp_x + temp_y * temp_y + link[1] * link[1] - link[2] * link[2])) / (2 * link[1] * sqrt(temp_x * temp_x + temp_y * temp_y))) + atan2(temp_y, temp_x));\n    target_angle[2].position = -acos((link[1] * link[1] + link[2] * link[2] - (temp_x * temp_x + temp_y * temp_y)) / (2 * link[1] * link[2])) + target_angle[1].position;\n\n    target_angle[0].velocity = 0.0;\n    target_angle[1].velocity = 0.0;\n    target_angle[2].velocity = 0.0;\n    target_angle[0].acceleration = 0.0;\n    target_angle[1].acceleration = 0.0;\n    target_angle[2].acceleration = 0.0;\n\n    target_angle_vector.push_back(target_angle[0]);\n    target_angle_vector.push_back(target_angle[1]);\n    target_angle_vector.push_back(target_angle[2]);\n    \n    return target_angle_vector;\n  }\n\n  void updatePassiveJointValue(Manipulator *manipulator)\n  {\n    std::vector<double> joint_angle;\n    joint_angle = manipulator->getAllActiveJointPosition();\n\n    joint_angle.push_back(joint_angle[1] - joint_angle[2]);\n    joint_angle.push_back(-M_PI - (joint_angle[1] - joint_angle[2]));\n    joint_angle.push_back(-M_PI - (joint_angle[1] - joint_angle[2]));\n    joint_angle.push_back(-M_PI - joint_angle[2]);\n    joint_angle.push_back(joint_angle[1]);\n    joint_angle.push_back(-(15 * DEG2RAD) - joint_angle[1]);\n    joint_angle.push_back(joint_angle[2] - (195 * DEG2RAD));\n    joint_angle.push_back((90 * DEG2RAD) - joint_angle[2]);\n\n    manipulator->setAllJointPosition(joint_angle);\n  }\n};\n}\n\n#endif // LINK_KINEMATICS_H_"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Link/open_manipulator_link/motion.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Hye-Jong KIM */\n\n#ifndef MOTION_H_\n#define MOTION_H_\n\n#include \"link.h\"\n\n//////////////////Motion num////////////////\n#define MAX_MOTION_NUM 102\n////////////////////////////////////////////\n\n//////////////////////fleg///////////////////\nbool motion    = false;\nbool repeat    = true;\nbool IK_motion = true;\n////////////////////////////////////////////\n\n///////////////////storage//////////////////\ndouble motion_storage[MAX_MOTION_NUM][5] = {0.0, };\nconst double initial_motion_set[56][5] = { // time, joint1, joint2, joint3, grip\n////////////////////////////////////STEP1///////////////////////////////////////////\n                                                { 2.0,  1.04, -1.99, -2.87,  0.0},    //move\n                                                { 1.0,  1.04, -1.74, -2.39,  0.0},    //down\n                                                { 0.5,  0.00,  0.00,  0.00,  1.0},    //pick\n                                                { 1.0,  1.04, -1.99, -2.87,  0.0},    //up\n                                                { 2.0,  0.20, -2.04, -3.10,  0.0},    //move\n                                                { 1.0,  0.20, -1.55, -2.13,  0.0},    //down\n                                                { 2.0,  0.00,  0.00,  0.00, -1.0},    //place\n                                                { 1.0,  0.20, -2.04, -3.10,  0.0},    //up\n/////////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////STEP2///////////////////////////////////////////\n                                                { 2.0,  1.04, -1.99, -2.87,  0.0},    //move\n                                                { 1.0,  1.04, -1.74, -2.39,  0.0},    //down\n                                                { 0.5,  0.00,  0.00,  0.00,  1.0},    //pick\n                                                { 1.0,  1.04, -1.99, -2.87,  0.0},    //up\n                                                { 2.0, -0.20, -2.04, -3.10,  0.0},    //move\n                                                { 1.0, -0.20, -1.55, -2.13,  0.0},    //down\n                                                { 2.0,  0.00,  0.00,  0.00, -1.0},    //place\n                                                { 1.0, -0.20, -2.04, -3.10,  0.0},    //up\n/////////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////STEP3///////////////////////////////////////////\n                                                { 2.0,  1.04, -1.99, -2.87,  0.0},    //move\n                                                { 1.0,  1.03, -1.69, -2.31,  0.0},    //down\n                                                { 0.5,  0.00,  0.00,  0.00,  1.0},    //pick\n                                                { 1.0,  1.04, -1.99, -2.87,  0.0},    //up\n                                                { 2.0,  0.15, -1.71, -2.79,  0.0},    //move\n                                                { 1.0,  0.14, -1.34, -2.18,  0.0},    //down\n                                                { 2.0,  0.00,  0.00,  0.00, -1.0},    //place\n                                                { 1.0,  0.15, -1.71, -2.79,  0.0},    //up\n/////////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////STEP4///////////////////////////////////////////\n                                                { 2.0,  1.04, -1.99, -2.87,  0.0},    //move\n                                                { 1.0,  1.03, -1.62, -2.22,  0.0},    //down\n                                                { 0.5,  0.00,  0.00,  0.00,  1.0},    //pick\n                                                { 1.0,  1.04, -1.99, -2.87,  0.0},    //up\n                                                { 2.0, -0.15, -1.71, -2.80,  0.0},    //move\n                                                { 1.0, -0.15, -1.34, -2.19,  0.0},    //down\n                                                { 2.0,  0.00,  0.00,  0.00, -1.0},    //place\n                                                { 1.0, -0.15, -1.71, -2.80,  0.0},    //up\n/////////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////STEP5///////////////////////////////////////////\n                                                { 2.0,  1.04, -1.99, -2.87,  0.0},    //move\n                                                { 1.0,  1.03, -1.62, -2.22,  0.0},    //down\n                                                { 0.5,  0.00,  0.00,  0.00,  1.0},    //pick\n                                                { 1.0,  1.04, -1.99, -2.87,  0.0},    //up\n                                                { 2.0, -0.15, -1.71, -2.80,  0.0},    //move\n                                                { 1.0, -0.15, -1.34, -2.19,  0.0},    //down\n                                                { 2.0,  0.00,  0.00,  0.00, -1.0},    //place\n                                                { 1.0, -0.15, -1.71, -2.80,  0.0},    //up\n/////////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////STEP6///////////////////////////////////////////\n                                                { 2.0,  1.04, -1.99, -2.87,  0.0},    //move\n                                                { 1.0,  1.03, -1.62, -2.22,  0.0},    //down\n                                                { 0.5,  0.00,  0.00,  0.00,  1.0},    //pick\n                                                { 1.0,  1.04, -1.99, -2.87,  0.0},    //up\n                                                { 2.0, -0.15, -1.71, -2.80,  0.0},    //move\n                                                { 1.0, -0.15, -1.34, -2.19,  0.0},    //down\n                                                { 2.0,  0.00,  0.00,  0.00, -1.0},    //place\n                                                { 1.0, -0.15, -1.71, -2.80,  0.0},    //up\n/////////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////STEP7///////////////////////////////////////////\n                                                { 2.0,  1.04, -1.99, -2.87,  0.0},    //move\n                                                { 1.0,  1.03, -1.62, -2.22,  0.0},    //down\n                                                { 0.5,  0.00,  0.00,  0.00,  1.0},    //pick\n                                                { 1.0,  1.04, -1.99, -2.87,  0.0},    //up\n                                                { 2.0, -0.15, -1.71, -2.80,  0.0},    //move\n                                                { 1.0, -0.15, -1.34, -2.19,  0.0},    //down\n                                                { 2.0,  0.00,  0.00,  0.00, -1.0},    //place\n                                                { 1.0, -0.15, -1.71, -2.80,  0.0}  \n/////////////////////////////////////////////////////////////////////////////////////\n                                                };\nconst double initial_IKmotion_set[MAX_MOTION_NUM][5] = { // time, x, y, z, VACUUM\n////////////////////////////////////STEP1///////////////////////////////////////////\n                                                { 1.0, -0.165,  0.125,  0.180,  0.000},    //move\n                                                { 1.0, -0.165,  0.125,  0.090,  0.000},    //down\n                                                { 1.0,  0.000,  0.000,  0.000,  1.000},    //pick\n                                                { 1.0, -0.165,  0.125,  0.180,  0.000},    //up\n                                                { 1.0,  0.000, -0.060,  0.180,  0.000},    //move\n                                                { 1.0,  0.000, -0.060,  0.055,  0.000},    //down\n                                                { 1.0,  0.000,  0.000,  0.000, -1.000},    //place\n                                                { 1.0,  0.000, -0.060,  0.180,  0.000},    //up\n/////////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////STEP2///////////////////////////////////////////\n                                                { 1.0, -0.165,  0.125,  0.180,  0.000},    //move\n                                                { 1.0, -0.165,  0.125,  0.085,  0.000},    //down\n                                                { 1.0,  0.000,  0.000,  0.000,  1.000},    //pick\n                                                { 1.0, -0.165,  0.125,  0.180,  0.000},    //up\n                                                { 1.0,  0.000,  0.000,  0.180,  0.000},    //move\n                                                { 1.0,  0.000,  0.000,  0.055,  0.000},    //down\n                                                { 1.0,  0.000,  0.000,  0.000, -1.000},    //place\n                                                { 1.0,  0.000,  0.000,  0.180,  0.000},    //up\n/////////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////STEP3///////////////////////////////////////////\n                                                { 1.0, -0.165,  0.125,  0.180,  0.000},    //move\n                                                { 1.0, -0.165,  0.125,  0.080,  0.000},    //down\n                                                { 1.0,  0.000,  0.000,  0.000,  1.000},    //pick\n                                                { 1.0, -0.165,  0.125,  0.180,  0.000},    //up\n                                                { 1.0,  0.000,  0.060,  0.180,  0.000},    //move\n                                                { 1.0,  0.000,  0.060,  0.055,  0.000},    //down\n                                                { 1.0,  0.000,  0.000,  0.000, -1.000},    //place\n                                                { 1.0,  0.000,  0.060,  0.180,  0.000},    //up\n/////////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////STEP4///////////////////////////////////////////\n                                                { 1.0, -0.165,  0.125,  0.180,  0.000},    //move\n                                                { 1.0, -0.165,  0.125,  0.075,  0.000},    //down\n                                                { 1.0,  0.000,  0.000,  0.000,  1.000},    //pick\n                                                { 1.0, -0.165,  0.125,  0.180,  0.000},    //up\n                                                { 1.0,  0.000, -0.026,  0.180,  0.000},    //move\n                                                { 1.0,  0.000, -0.026,  0.105,  0.000},    //down\n                                                { 1.0,  0.000,  0.000,  0.000, -1.000},    //place\n                                                { 1.0,  0.000, -0.026,  0.180,  0.000},    //up\n/////////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////STEP5///////////////////////////////////////////\n                                                { 1.0, -0.165,  0.125,  0.180,  0.000},    //move\n                                                { 1.0, -0.165,  0.125,  0.070,  0.000},    //down\n                                                { 1.0,  0.000,  0.000,  0.000,  1.000},    //pick\n                                                { 1.0, -0.165,  0.125,  0.180,  0.000},    //up\n                                                { 1.0,  0.000,  0.026,  0.180,  0.000},    //move\n                                                { 1.0,  0.000,  0.026,  0.105,  0.000},    //down\n                                                { 1.0,  0.000,  0.000,  0.000, -1.000},    //place\n                                                { 1.0,  0.000,  0.026,  0.180,  0.000},    //up\n/////////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////STEP6///////////////////////////////////////////\n                                                { 1.0, -0.165,  0.125,  0.180,  0.000},    //move\n                                                { 1.0, -0.165,  0.125,  0.065,  0.000},    //down\n                                                { 1.0,  0.000,  0.000,  0.000,  1.000},    //pick\n                                                { 1.0, -0.165,  0.125,  0.180,  0.000},    //up\n                                                { 1.0,  0.000,  0.000,  0.180,  0.000},    //move\n                                                { 1.0,  0.000,  0.000,  0.155,  0.000},    //down\n                                                { 1.0,  0.000,  0.000,  0.000, -1.000},    //place\n                                                { 1.0,  0.000,  0.000,  0.180,  0.000},    //up\n/////////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////STEP7///////////////////////////////////////////\n                                                { 3.0, -0.075,  0.075,  0.180,  0.000},    \n                                                { 0.5, -0.075,  0.075,  0.100,  0.000},    \n                                                { 0.5, -0.075,  0.075,  0.180,  0.000},    \n                                                { 0.5, -0.075,  0.075,  0.100,  0.000},    \n                                                { 0.5, -0.075,  0.075,  0.180,  0.000},    \n                                                { 3.0, -0.075,  0.075,  0.180,  0.000},     \n/////////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////STEP6///////////////////////////////////////////\n                                                { 1.0, -0.005,  0.000,  0.180,  0.000},    //move\n                                                { 1.0, -0.005,  0.000,  0.145,  0.000},    //down\n                                                { 1.0,  0.000,  0.000,  0.000,  1.000},    //pick\n                                                { 1.0, -0.005,  0.000,  0.180,  0.000},    //up\n                                                { 1.0, -0.165,  0.127,  0.180,  0.000},    //move\n                                                { 1.0, -0.165,  0.127,  0.075,  0.000},    //down\n                                                { 1.0,  0.000,  0.000,  0.000, -1.000},    //place\n                                                { 1.0, -0.165,  0.127,  0.180,  0.000},    //up\n/////////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////STEP5///////////////////////////////////////////\n                                                { 1.0, -0.005,  0.026,  0.180,  0.000},    //move\n                                                { 1.0, -0.005,  0.026,  0.095,  0.000},    //down\n                                                { 1.0,  0.000,  0.000,  0.000,  1.000},    //place\n                                                { 1.0, -0.005,  0.026,  0.180,  0.000},    //up\n                                                { 1.0, -0.165,  0.127,  0.180,  0.000},    //move\n                                                { 1.0, -0.165,  0.127,  0.080,  0.000},    //down\n                                                { 1.0,  0.000,  0.000,  0.000, -1.000},    //pick\n                                                { 1.0, -0.165,  0.127,  0.180,  0.000},    //up\n/////////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////STEP4///////////////////////////////////////////\n                                                { 1.0, -0.005, -0.026,  0.180,  0.000},    //move\n                                                { 1.0,  0.000, -0.026,  0.095,  0.000},    //down\n                                                { 1.0, -0.005,  0.000,  0.000,  1.000},    //place\n                                                { 1.0, -0.005, -0.026,  0.180,  0.000},    //up\n                                                { 1.0, -0.165,  0.127,  0.180,  0.000},    //move\n                                                { 1.0, -0.165,  0.127,  0.085,  0.000},    //down\n                                                { 1.0,  0.000,  0.000,  0.000, -1.000},    //pick\n                                                { 1.0, -0.165,  0.127,  0.180,  0.000},    //up\n/////////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////STEP3///////////////////////////////////////////\n                                                { 1.0, -0.005,  0.060,  0.180,  0.000},    //move\n                                                { 1.0, -0.005,  0.060,  0.045,  0.000},    //down\n                                                { 1.0,  0.000,  0.000,  0.000,  1.000},    //place\n                                                { 1.0, -0.005,  0.060,  0.180,  0.000},    //up\n                                                { 1.0, -0.165,  0.127,  0.180,  0.000},    //move\n                                                { 1.0, -0.165,  0.127,  0.090,  0.000},    //down\n                                                { 1.0,  0.000,  0.000,  0.000, -1.000},    //pick\n                                                { 1.0, -0.165,  0.127,  0.180,  0.000},    //up\n/////////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////STEP2///////////////////////////////////////////\n                                                { 1.0, -0.005,  0.000,  0.180,  0.000},    //move\n                                                { 1.0, -0.005,  0.000,  0.045,  0.000},    //down\n                                                { 1.0,  0.000,  0.000,  0.000,  1.000},    //place\n                                                { 1.0, -0.005,  0.000,  0.180,  0.000},    //up\n                                                { 1.0, -0.165,  0.127,  0.180,  0.000},    //move\n                                                { 1.0, -0.165,  0.127,  0.095,  0.000},    //down\n                                                { 1.0,  0.000,  0.000,  0.000, -1.000},    //pick\n                                                { 1.0, -0.165,  0.127,  0.180,  0.000},    //up\n/////////////////////////////////////////////////////////////////////////////////////\n////////////////////////////////////STEP1///////////////////////////////////////////\n                                                { 1.0, -0.005, -0.060,  0.180,  0.000},    //move\n                                                { 1.0, -0.005, -0.060,  0.045,  0.000},    //down\n                                                { 1.0,  0.000,  0.000,  0.000,  1.000},    //place\n                                                { 1.0, -0.005, -0.060,  0.180,  0.000},    //up\n                                                { 1.0, -0.165,  0.127,  0.180,  0.000},    //move\n                                                { 1.0, -0.165,  0.127,  0.100,  0.000},    //down\n                                                { 1.0,  0.000,  0.000,  0.000, -1.000},    //pick\n                                                { 1.0, -0.165,  0.127,  0.180,  0.000},    //up\n/////////////////////////////////////////////////////////////////////////////////////\n                                                };\n// ////////////////////////////////////////////\n\n//////////////////motion cnt////////////////\nuint8_t motion_cnt = 0;\nuint8_t filled_motion_num = MAX_MOTION_NUM;\n////////////////////////////////////////////\n\nvoid setMotion(OpenManipulatorLink* open_manipulator_link)\n{\n  if (motion)\n  {\n    if (open_manipulator_link->getMovingState())///////////////////////////\n    {\n      return;\n    }\n    else\n    {\n////////////////////////MOTION SETTING//////////////////////////////        \n      //repeat check\n      if (motion_cnt >= filled_motion_num)\n      {\n        if (repeat)\n        {\n          motion_cnt = 0;\n        }\n        else\n        {\n          motion_cnt = 0;\n          motion     = false;     \n        }\n      }\n      \n      static std::vector<double> target_angle;\n      if (motion_storage[motion_cnt][4] == 1.0)\n      {\n        open_manipulator_link->makeToolTrajectory(\"vacuum\", 1.0);   //VACUUM on\n        open_manipulator_link->makeJointTrajectory(target_angle, motion_storage[motion_cnt][0]);         \n      }\n      else if (motion_storage[motion_cnt][4] == -1.0)\n      {\n        open_manipulator_link->makeToolTrajectory(\"vacuum\", -1.0);     //VACUUM off\n        open_manipulator_link->makeJointTrajectory(target_angle, motion_storage[motion_cnt][0]);   \n      }\n      else\n      {\n        target_angle.clear();\n        for (int8_t i = 1; i < 4; i++)\n        {\n          target_angle.push_back(motion_storage[motion_cnt][i]);\n        }\n        open_manipulator_link->makeJointTrajectory(target_angle, motion_storage[motion_cnt][0]);   \n      }\n      motion_cnt++;\n////////////////////////MOTION SETTING////////////////////////////// \n    }\n  }\n  else\n  {\n    motion_cnt = 0;\n  }\n}\n\nvoid motionStart(OpenManipulatorLink* open_manipulator_link)\n{\n  if(IK_motion)\n  {\n    Pose target_pose;\n    std::vector <JointValue> target_motion_angle;\n\n    for (uint8_t i = 0; i < uint8_t(MAX_MOTION_NUM); i++)\n    {\n      motion_storage[i][0] = initial_IKmotion_set[i][0];     //time set\n      motion_storage[i][4] = initial_IKmotion_set[i][4];     //VACUUM set\n        \n      for(uint8_t j = 0; j < 3; j++)\n        target_pose.kinematic.position(j) = initial_IKmotion_set[i][j+1];\n\n      open_manipulator_link->solveInverseKinematics(\"vacuum\", target_pose, &target_motion_angle);\n\n      for(uint8_t j = 0; j < 3; j++)\n      {\n        motion_storage[i][j+1] = target_motion_angle.at(j).position;\n      }\n    }\n    filled_motion_num = MAX_MOTION_NUM;  \n    motion_cnt = 0;          \n    motion = true;\n  }\n  else\n  {\n    for (uint8_t i = 0; i < uint8_t(MAX_MOTION_NUM); i++)\n    {\n        for (uint8_t j = 0; j < 5; j++)\n        {\n        motion_storage[i][j] = initial_motion_set[i][j];\n        }\n    }\n    filled_motion_num = MAX_MOTION_NUM;  \n    motion_cnt = 0;          \n    motion = true;\n  }\n}\n\nvoid motionStop()\n{\n  for (uint8_t i = 0; i < uint8_t(MAX_MOTION_NUM); i++)\n  {\n    for (uint8_t j = 0; j < 5; j++)\n    {\n      motion_storage[i][j] = 0.0;\n    }\n  }\n  motion_cnt = 0;\n  motion     = false;\n  repeat     = false;\n}\n\nvoid AddMotionStorage()\n{\n\n}\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Link/open_manipulator_link/open_manipulator_link.ino",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Hye-Jong KIM */\n\n#include \"link.h\"\n#include \"processing.h\"\n#include \"motion.h\"\n#include \"remote_controller.h\"\n\n#define BDPIN_PUSH_SW_1         34\n#define BDPIN_PUSH_SW_2         35\n\ndouble present_time = 0.0;\ndouble previous_time = 0.0;\n\nOpenManipulatorLink open_manipulator_link;\n\nvoid setup()\n{\n  Serial.begin(57600);\n  DEBUG.begin(57600);\n  while (!Serial)\n    ;\n\n  connectProcessing();\n  connectRC100();\n  switchInit();\n\n  open_manipulator_link.initManipulator(true, \"/dev/ttyACM0\", \"1000000\", 0.010f);\n  log::println(\"OpenManipulator Debugging Port\");\n}\n\nvoid loop()\n{\n  present_time = (double)(millis()/1000.0);\n\n  //get Date \n  getData(10);\n  switchRead();\n  setMotion(&open_manipulator_link);\n\n  //Control\n  if(present_time-previous_time>= ACTUATOR_CONTROL_TIME)\n  {\n    open_manipulator_link.Process((double)(millis()/1000.0));\n    sendAngle2Processing(open_manipulator_link.getManipulator()->getAllActiveJointValue());\n    previous_time= (double)(millis()/1000.0);\n  }\n  \n  //osDelay(LOOP_TIME * 1000);\n}\n\n\n////////////////////////getData/////////////////////////////////\nvoid getData(uint32_t wait_time)\n{\n  static uint8_t state = 0;\n  static uint32_t tick = 0;\n\n  bool rc100_flag = false;\n  bool processing_flag = false;\n\n  uint16_t get_rc100_data = 0;\n  String get_processing_data = \"\";\n\n  if (availableRC100())\n  {\n    get_rc100_data = readRC100Data();\n    rc100_flag = true;\n  }\n  if (availableProcessing())\n  {\n    get_processing_data = readProcessingData();\n    processing_flag = true;\n  }\n\n  switch (state)\n  {\n    case 0:\n      if (processing_flag)\n      {\n        fromProcessing(&open_manipulator_link, get_processing_data);\n\n        tick = millis();\n        state = 1;\n      }\n      else if (rc100_flag)\n      {\n        fromRC100(&open_manipulator_link, get_rc100_data);\n\n        tick = millis();\n        state = 1;\n      }\n     break;\n\n    case 1:\n      if ((millis() - tick) >= wait_time)\n      {\n        state = 0;\n      }\n     break;\n\n    default:\n      state = 0;\n     break;\n  }\n}\n///////////////////////////////////////////////////////////////\n////////////////////////switch/////////////////////////////////\nvoid switchInit()\n{\n  pinMode(BDPIN_PUSH_SW_1, INPUT);\n  pinMode(BDPIN_PUSH_SW_2, INPUT);\n}\n\nvoid switchRead()\n{\n  if(digitalRead(BDPIN_PUSH_SW_1))\n  {\n    motionStart(&open_manipulator_link);\n  }\n  if(digitalRead(BDPIN_PUSH_SW_2))\n  {\n    motionStop();\n  }\n}\n///////////////////////////////////////////////////////////////"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Link/open_manipulator_link/processing.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Hye-Jong KIM */\n\n#ifndef PROCESSING_H_\n#define PROCESSING_H_\n\n#include \"link.h\"\n#include \"motion.h\"\n\n//////////////////Move step/////////////////\n#define MOVESTEP 0.01\n////////////////////////////////////////////\n//////////////////Move time/////////////////\n#define MOVETIME 1.0\n////////////////////////////////////////////\n//////////////////cmd param/////////////////\nString global_cmd[50];\n////////////////////////////////////////////\n\n\n////////////////////////////send////////////////////////////////////\nvoid sendAngle2Processing(std::vector<JointValue> joint_angle_vector)\n{\n  Serial.print(\"angle\");\n\n  for (uint32_t i = 0; i < joint_angle_vector.size(); i++)\n  {\n    Serial.print(\",\");\n    Serial.print(joint_angle_vector.at(i).position);\n  }\n  Serial.print(\"\\n\");\n}\n\nvoid sendToolData2Processing(bool onoff)\n{\n  Serial.print(\"tool\");\n  Serial.print(\",\");\n  Serial.print(onoff);\n  Serial.print(\"\\n\");\n}\n\nvoid sendToolData2Processing(ToolValue value)\n{\n  Serial.print(\"tool\");\n  Serial.print(\",\");\n  Serial.print(value.position);\n  Serial.print(\"\\n\");\n}\n////////////////////////////////////////////////////////////////////\n\nvoid connectProcessing()\n{\n  for (int i = 0; i < 5; i++)\n  {\n    Serial.print(0.0);\n    Serial.print(\",\");\n  }\n\n  Serial.println(0.0);\n  delay(300);\n\n  Serial.println(\"Init Processing\");\n}\n\nint availableProcessing()\n{\n  return Serial.available();\n}\n\nString readProcessingData()\n{\n  return Serial.readStringUntil('\\n');\n}\n\nvoid split(String data, char separator, String* temp)\n{\n  int cnt = 0;\n  int get_index = 0;\n\n  String copy = data;\n  \n  while(true)\n  {\n    get_index = copy.indexOf(separator);\n\n\tif(-1 != get_index)\n\t{\n\t  temp[cnt] = copy.substring(0, get_index);\n  \t  copy = copy.substring(get_index + 1);\n\t}\n\telse\n\t{\n      temp[cnt] = copy.substring(0, copy.length());\n\t  break;\n\t}\n\t  ++cnt;\n  }\n}\n\nString* parseDataFromProcessing(String get)\n{\n  get.trim();\n  split(get, ',', global_cmd);\n  \n  return global_cmd;\n}\n\nvoid fromProcessing(OpenManipulatorLink *open_manipulator_link, String data)\n{\n  String *cmd = parseDataFromProcessing(data);\n\n////////////////////////Manipulator OnOff//////////////////////////\n  if (cmd[0] == \"om\")\n  {\n    if (cmd[1] == \"ready\")\n    {\n      open_manipulator_link->enableAllActuator();\n      sendAngle2Processing(open_manipulator_link->getAllActiveJointValue());\n      sendToolData2Processing(open_manipulator_link->getToolValue(\"vacuum\"));\n    }\n    else if (cmd[1] == \"end\")\n    {\n      open_manipulator_link->disableAllActuator();\n    }\n  }\n////////////////////////////////////////////////////////////////////\n/////////////////////////////Joint Move/////////////////////////////\n  else if (cmd[0] == \"joint\")\n  {\n    std::vector<double> goal_position;\n\n    for (int8_t index = 0; index < open_manipulator_link->getManipulator()->getDOF(); index++)\n    {\n      goal_position.push_back((double)cmd[index + 1].toFloat());\n    }\n    open_manipulator_link->makeJointTrajectory(goal_position, MOVETIME); // FIX TIME PARAM\n  }\n////////////////////////////////////////////////////////////////////\n////////////////////////////Vacuum OnOff///////////////////////////\n  else if (cmd[0] == \"suction\")\n  {\n    if (cmd[1] == \"on\")\n    {\n      open_manipulator_link->makeToolTrajectory(\"vacuum\", 1.0);\n    }\n    else if (cmd[1] == \"off\")\n    {\n      open_manipulator_link->makeToolTrajectory(\"vacuum\", -1.0);\n    }\n  }\n////////////////////////////////////////////////////////////////////\n/////////////////////////////Task move//////////////////////////////\n  else if (cmd[0] == \"task\")\n  {\n    Pose target_pose;\n    std::vector<double> target_angle;\n\n    if (cmd[1] == \"forward\")\n    {\n      open_manipulator_link->makeTaskTrajectoryFromPresentPose(\"vacuum\", math::vector3(MOVESTEP, 0.0, 0.0), MOVETIME);\n    }  \n    else if (cmd[1] == \"back\")\n    {\n      open_manipulator_link->makeTaskTrajectoryFromPresentPose(\"vacuum\", math::vector3(-MOVESTEP, 0.0, 0.0), MOVETIME);\n    }\n    else if (cmd[1] == \"left\")\n    {\n      open_manipulator_link->makeTaskTrajectoryFromPresentPose(\"vacuum\", math::vector3(0.0, MOVESTEP, 0.0), MOVETIME);\n    }\n    else if (cmd[1] == \"right\")\n    {\n      open_manipulator_link->makeTaskTrajectoryFromPresentPose(\"vacuum\", math::vector3(0.0, -MOVESTEP, 0.0), MOVETIME);\n    }\n    else if (cmd[1] == \"up\")\n    {\n      open_manipulator_link->makeTaskTrajectoryFromPresentPose(\"vacuum\", math::vector3(0.0, 0.0, MOVESTEP), MOVETIME);\n    }\n    else if (cmd[1] == \"down\")\n    {\n      open_manipulator_link->makeTaskTrajectoryFromPresentPose(\"vacuum\", math::vector3(0.0, 0.0, -MOVESTEP), MOVETIME);\n    }\n    else\n    {\n      open_manipulator_link->makeTaskTrajectoryFromPresentPose(\"vacuum\", math::vector3(0.0, 0.0, 0.0), MOVETIME);\n    }\n  }\n////////////////////////////////////////////////////////////////////\n////////////////////////////Motor onOff/////////////////////////////\n  else if (cmd[0] == \"motor\")\n  {\n    if (cmd[1] == \"enable\")\n    {\n      open_manipulator_link->enableAllActuator();\n    }\n    else if (cmd[1] == \"disable\")\n    {\n      open_manipulator_link->disableAllActuator();\n    }\n  }\n////////////////////////////////////////////////////////////////////\n///////////////////////////motion move//////////////////////////////\n  else if (cmd[0] == \"motion\")\n  {\n    if (cmd[1] == \"start\")\n    {\n      motionStart(open_manipulator_link);\n    }\n    else if (cmd[1] == \"stop\")\n    {\n      motionStop();\n    }\n  }\n////////////////////////////////////////////////////////////////////\n///////////////////////////check setting////////////////////////////\n  else if (cmd[0] == \"check\")\n  {\n    open_manipulator_link->printManipulatorSetting();\n  }\n////////////////////////////////////////////////////////////////////\n}\n\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Link/open_manipulator_link/remote_controller.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim */\n\n#ifndef REMOTE_CONTROLLER_H_\n#define REMOTE_CONTROLLER_H_\n\n#include \"link.h\"\n#include <RC100.h>\n#include \"motion.h\"\n\nRC100 rc100;\n\nvoid connectRC100()\n{\n  rc100.begin(1);\n}\n\nint availableRC100()\n{\n  return rc100.available();\n}\n\nuint16_t readRC100Data()\n{\n  return rc100.readData();\n}\n\nvoid fromRC100(OpenManipulatorLink* open_manipulator_link, int16_t data)\n{\n  if (data & RC100_BTN_U)\n    open_manipulator_link->makeTaskTrajectoryFromPresentPose(\"vacuum\", math::vector3(MOVESTEP, 0.0, 0.0), MOVETIME);\n  else if (data & RC100_BTN_D)\n    open_manipulator_link->makeTaskTrajectoryFromPresentPose(\"vacuum\", math::vector3(-MOVESTEP, 0.0, 0.0), MOVETIME);\n  else if (data & RC100_BTN_L)\n    open_manipulator_link->makeTaskTrajectoryFromPresentPose(\"vacuum\", math::vector3(0.0, MOVESTEP, 0.0), MOVETIME);\n  else if (data & RC100_BTN_R)\n    open_manipulator_link->makeTaskTrajectoryFromPresentPose(\"vacuum\", math::vector3(0.0, -MOVESTEP, 0.0), MOVETIME);\n  else if (data & RC100_BTN_1)\n    open_manipulator_link->makeTaskTrajectoryFromPresentPose(\"vacuum\", math::vector3(0.0, 0.0, MOVESTEP), MOVETIME);\n  else if (data & RC100_BTN_3)\n    open_manipulator_link->makeTaskTrajectoryFromPresentPose(\"vacuum\", math::vector3(0.0, 0.0, -MOVESTEP), MOVETIME);\n  else if (data & RC100_BTN_2)\n  {\n    open_manipulator_link->makeToolTrajectory(\"vacuum\", 1.0);\n  }\n  else if (data & RC100_BTN_4)\n  {\n    open_manipulator_link->makeToolTrajectory(\"vacuum\", -1.0);\n  }\n  else if (data & RC100_BTN_5)\n  {\n    motionStart(open_manipulator_link);\n  }\n  else if (data & RC100_BTN_6)\n  {\n    motionStop();\n  }\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Link/open_manipulator_link/vacuum_actuator.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Hye-Jong KIM */\n\n#ifndef VACUUM_ACTUATOR_H_\n#define VACUUM_ACTUATOR_H_\n\n#if defined(__OPENCR__)\n  #include <RobotisManipulator.h>\n#else\n  #include <robotis_manipulator/robotis_manipulator.h>\n#endif\n#include \"Arduino.h\"\n\n\nclass VacuumModule : public robotis_manipulator::ToolActuator\n{\n private:\n  uint8_t relay_pin_;\n  int8_t id_;\n  bool suction_flag_;\n\n public:\n  VacuumModule(){}\n  virtual ~VacuumModule(){}\n\n  virtual void init(uint8_t actuator_id, const void *arg)\n  {\n    id_ = actuator_id;\n   \n    uint8_t *get_arg = (uint8_t *)arg;\n    relay_pin_ = get_arg[0];\n\n    vacuumInit();\n  }\n\n  virtual void setMode(const void *arg){}\n\n  virtual uint8_t getId()\n  {\n    return id_;\n  }\n\n  virtual void enable(){}\n  virtual void disable(){}\n\n  virtual bool sendToolActuatorValue(ActuatorValue value)\n  {\n    if(value.position > 0)\n    {\n      suction_flag_ = true;\n      vacuumOn();\n      return true;\n    }  \n    else\n    {\n      suction_flag_ = false;\n      vacuumOff();\n      return true;\n    }\n    return false;\n  }\n\n  virtual ActuatorValue receiveToolActuatorValue()\n  { \n    ActuatorValue result;\n\n    if(suction_flag_)\n    { \n      result.position = 1.0;\n      result.velocity = 0.0;\n      result.acceleration = 0.0;\n      return result;\n    }\n    else\n    {\n      result.position = -1.0;\n      result.velocity = 0.0;\n      result.acceleration = 0.0;\n      return result;\n    }\n  }\n\n  void vacuumInit()\n  {\n    pinMode(relay_pin_, OUTPUT);\n  }\n\n  void vacuumOn()\n  {\n    digitalWrite(relay_pin_, HIGH);\n  }\n\n  void vacuumOff()\n  {\n    digitalWrite(relay_pin_, LOW);\n  }\n};\n\n\n\n\n#endif //LINK_VACUUM_H_"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Planar/open_manipulator_planar/demo.h",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef DEMO_H_\n#define DEMO_H_\n\n#include <planar_libs.h>\n\nbool start_demo_flag;\nuint8_t motion_cnt[] = {0};\nuint8_t sub_motion_cnt[] = {0};\n\n/*****************************************************************************\n** Functions used in runDemo()\n*****************************************************************************/\n// Draw an Object \nvoid drawObj(Planar* planar, STRING object, double radius, int num_revolution, double start_angular_position, double move_time)\n{\n  double draw_arg[3]; \n  draw_arg[0] = radius;                 // Radius (m)\n  draw_arg[1] = num_revolution;         // Number of revolution\n  draw_arg[2] = start_angular_position; // Starting angular position (rad)\n  void* p_draw_arg = &draw_arg;\n\n  planar->makeCustomTrajectory(object, \"tool\", draw_arg, move_time);\n}\n\n/*****************************************************************************\n** Start or Stop Demo\n*****************************************************************************/\nvoid startDemo()\n{\n  // Start the demo\n  start_demo_flag = true;\n}\n\nvoid stopDemo(Planar *planar)\n{\n  // Stop the demo\n  start_demo_flag = false;\n\n  // Move to the default pose.\n  planar->makeTaskTrajectory(\"tool\", math::vector3(0.0, 0.0, 0.0), 2.0);\n\n  // Reset the count variables\n  motion_cnt[0] = 0;\n  sub_motion_cnt[0] = 0;\n}\n\n/*****************************************************************************\n** Initialize Demo\n*****************************************************************************/\nvoid initDemo()\n{\n  start_demo_flag = false;\n  motion_cnt[0] = 0;\n  sub_motion_cnt[0] = 0;\n}\n\n/*****************************************************************************\n** Run Demo\n*****************************************************************************/\nvoid runDemo(Planar *planar)\n{\n  if(digitalRead(BDPIN_PUSH_SW_1))\n  {\n    startDemo();\n  }\n  if(digitalRead(BDPIN_PUSH_SW_2))\n  {\n    stopDemo(planar);    \n  }\n\n  if (planar->getMovingState()) \n  {\n    return;\n  }\n  else \n  {\n    if (start_demo_flag)\n    {\n      switch(motion_cnt[0])\n      {\n        case 0:\n          planar->makeTaskTrajectory(\"tool\", math::vector3( 0.045, 0.0, 0.0), 1.0);\n          motion_cnt[0] ++; \n        break;\n        case 1:\n          planar->makeTaskTrajectory(\"tool\", math::vector3( 0.0, 0.045, 0.0), 1.0);\n          motion_cnt[0] ++; \n        break;\n        case 2:\n          planar->makeTaskTrajectory(\"tool\", math::vector3(-0.045, 0.0, 0.0), 1.0);\n          motion_cnt[0] ++; \n        break;\n        case 3:\n          planar->makeTaskTrajectory(\"tool\", math::vector3( 0.0,-0.045, 0.0), 1.0);\n          motion_cnt[0] ++; \n        break;\n        case 4:\n          planar->makeTaskTrajectory(\"tool\", math::vector3( 0.045, 0.0, 0.0), 1.0);\n          motion_cnt[0] ++; \n        break;\n        case 5:\n          drawObj(planar, CUSTOM_TRAJECTORY_CIRCLE, 0.045, 1, 0.0, 2.0); \n          motion_cnt[0] ++; \n        break;\n        case 6:\n          planar->makeTaskTrajectory(\"tool\", math::vector3( 0.0, 0.0, 0.0), 0.5);\n          motion_cnt[0] ++; \n        break;\n      }\n    }\n  }\n}\n\n#endif // DEMO_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Planar/open_manipulator_planar/open_manipulator_planar.ino",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include <planar_libs.h>\n#include \"remotecontroller100.h\"\n#include \"processing.h\"\n#include \"demo.h\"\n\nPlanar planar;\n\nvoid setup()\n{\n  planar.initDebug();\n\n  initRC100();       \n\n  initProcessing();  \n\n  initDemo();\n\n  planar.initOpenManipulator(true); // true:  using actual hardware\n                                    // false: using only visualization tool \n}\n\nvoid loop()\n{\n  receiveDataFromRC100(&planar);\n\n  receiveDataFromProcessing(&planar);\n  sendDataToProcessing(&planar);\n\n  planar.processOpenManipulator(millis()/1000.0);\n\n  runDemo(&planar);\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Planar/open_manipulator_planar/processing.h",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef PROCESSING_H_\n#define PROCESSING_H_\n\n#include <planar_libs.h>\n#include \"demo.h\"\n\n/*****************************************************************************\n** Initialize baudrate for using Processing\n*****************************************************************************/\nvoid initProcessing()\n{\n  Serial.begin(57600);\n\n  Serial.print(\"Initial actuator angles: \");\n  for (int i = 0; i < DXL_SIZE; i++)\n  {\n    Serial.print(0.0);\n    Serial.print(\",\");\n  }\n  Serial.println(\"\");\n  delay(300);\n}\n\n/*****************************************************************************\n** Send data to Processing\n*****************************************************************************/\n// Send joint data to Processing \nvoid sendJointDataToProcessing(JointWaypoint joint_angle_vector) \n{\n  Serial.print(\"joint\");\n\n  for (int i = 0; i < (int)joint_angle_vector.size(); i++)\n  {\n    Serial.print(\",\");\n    Serial.print(joint_angle_vector.at(i).position,3);\n  }\n  Serial.print(\"\\n\");\n}\n\n// Send joint and tool values to Processing \nvoid sendDataToProcessing(Planar *planar)\n{\n  sendJointDataToProcessing(planar->getTrajectory()->getManipulator()->getAllJointValue());\n}\n\n/*****************************************************************************\n** Receive data from Processing\n*****************************************************************************/\n// Split data by separator \nvoid split(String data, char separator, String* temp)\n{\n  int cnt = 0;\n  int get_index = 0;\n\n  String copy = data;\n  \n  while(true)\n  {\n    get_index = copy.indexOf(separator);\n\n    if(-1 != get_index)\n    {\n      temp[cnt] = copy.substring(0, get_index);\n      copy = copy.substring(get_index + 1);\n    }\n    else\n    {\n      temp[cnt] = copy.substring(0, copy.length());\n      break;\n    }\n    ++cnt;\n  }\n}\n\n// Parse data received from Processing \nString cmd[50];\nString* parseProcessingData(String get) \n{\n  get.trim();\n  split(get, ',', cmd);\n  \n  return cmd;\n}\n\n// Receive data from Processing \nvoid receiveDataFromProcessing(Planar *planar) \n{\n  if (!planar->getReceiveDataFlag())\n  {\n    if (Serial.available())\n    {\n      String serialInput = Serial.readStringUntil('\\n');\n      String *cmd = parseProcessingData(serialInput);\n\n      // Actuator Control Tab \n      if (cmd[0] == \"actuator\")\n      {\n        // Torque On/Off\n        if (cmd[1] == \"on\")\n        {\n          if(planar->getUsingActualRobotState())\n          {\n            planar->enableAllActuator();\n            sendDataToProcessing(planar);\n          }\n        }\n        else if (cmd[1] == \"off\")\n        {\n          if(planar->getUsingActualRobotState())\n          {\n            planar->disableAllActuator();\n          }\n        }\n      }\n\n      // Joint space control tab \n      else if (cmd[0] == \"joint\")\n      {\n        // Joint Torque on/off\n        if (cmd[1] == \"on\")\n        {\n          if (planar->getUsingActualRobotState())    \n          {\n            planar->enableAllJointActuator();\n            sendJointDataToProcessing(planar->getTrajectory()->getManipulator()->getAllJointValue());\n          }\n        }\n        else if (cmd[1] == \"off\")\n        {\n          if (planar->getUsingActualRobotState())    \n            planar->disableAllJointActuator();\n        }\n\n        // Joint Position Control\n        // else\n        // {\n        //   std::vector<double> goal_position;\n        //   for (uint8_t index = 0; index < DXL_SIZE; index++)\n        //   {\n        //     goal_position.push_back((double)cmd[index + 1].toFloat());\n        //   }\n        //   planar->makeJointTrajectory(goal_position, 1.0); \n        // }\n      }\n\n      // Task space control tab \n      else if (cmd[0] == \"task\")\n      {\n        if (cmd[1] == \"f\")\n          planar->makeTaskTrajectory(\"tool\", math::vector3( 0.020, 0.0, 0.0), 0.15);\n        else if (cmd[1] == \"b\")\n          planar->makeTaskTrajectory(\"tool\", math::vector3(-0.020, 0.0, 0.0), 0.15);\n        else if (cmd[1] == \"l\")\n          planar->makeTaskTrajectory(\"tool\", math::vector3(0.0,  0.020, 0.0), 0.15);\n        else if (cmd[1] == \"r\")\n          planar->makeTaskTrajectory(\"tool\", math::vector3(0.0, -0.020, 0.0), 0.15);\n        else\n          planar->makeTaskTrajectory(\"tool\", math::vector3(0.0, 0.0, 0.0), 0.15);\n      }\n\n      // Demo Control tab\n      else if (cmd[0] == \"demo\")\n      {\n        if (cmd[1] == \"start\")\n          startDemo();\n        else if (cmd[1] == \"stop\")\n          stopDemo(planar);\n      }\n\n//----------------------------------------------//\n//         DO NOT MODIFY THE BELOW CODE         //\n//----------------------------------------------//\n      planar->setReceiveDataFlag(true);\n      planar->setPrevReceiveTime(millis()/1000.0); \n    }\n  }\n  else \n  {\n    if (millis()/1000.0 - planar->getPrevReceiveTime() >= RECEIVE_RATE)\n    {\n      planar->setReceiveDataFlag(false); \n      initRC100();\n    }\n  }\n}\n\n#endif //PROCESSING_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Planar/open_manipulator_planar/remotecontroller100.h",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef REMOTECONTROLLER100_H_\n#define REMOTECONTROLLER100_H_\n\n#include <planar_libs.h>\n#include <RC100.h>\n#include \"demo.h\"\n\nRC100 rc100;\ndouble grip_value = 0.0;\n\n/*****************************************************************************\n** Initialize baudrate for using RC100\n*****************************************************************************/\nvoid initRC100()\n{\n  rc100.begin(1); // Using Serial2(=SerialBT1)\n}\n\n/*****************************************************************************\n** Receive data from RC100\n*****************************************************************************/\nvoid receiveDataFromRC100(Planar* planar)\n{\n  if (!planar->getReceiveDataFlag())\n  {\n    if (rc100.available())\n    {\n      planar->setReceiveDataFlag(true);\n\n      uint16_t data = rc100.readData();\n\n      // Task space control tab \n      if (data & RC100_BTN_U)\n        planar->makeTaskTrajectory(\"tool\", math::vector3(0.020, 0.0, 0.0), 0.15);\n      else if (data & RC100_BTN_D)\n        planar->makeTaskTrajectory(\"tool\", math::vector3(-0.020, 0.0, 0.0), 0.15);\n      else if (data & RC100_BTN_L)\n        planar->makeTaskTrajectory(\"tool\", math::vector3(0.0,  0.020, 0.0), 0.15);\n      else if (data & RC100_BTN_R)\n        planar->makeTaskTrajectory(\"tool\", math::vector3(0.0, -0.020, 0.0), 0.15);\n      else if (data & RC100_BTN_1) {}\n      else if (data & RC100_BTN_2) {}\n      else if (data & RC100_BTN_3)\n        startDemo();\n      else if (data & RC100_BTN_4)\n        stopDemo(planar);\n      else if (data & RC100_BTN_5) {}\n      else if (data & RC100_BTN_6)\n      {\n        std::vector<double> goal_position;\n        goal_position.push_back(0.0);\n        goal_position.push_back(0.0);\n        goal_position.push_back(0.0);\n        planar->makeJointTrajectory(goal_position, 0.5);\n      }\n\n//----------------------------------------------//\n//         DO NOT MODIFY THE BELOW CODE         //\n//----------------------------------------------//\n      planar->setReceiveDataFlag(true);\n      planar->setPrevReceiveTime(millis()/1000.0); \n    }\n  }\n  else \n  {\n    if (millis()/1000.0 - planar->getPrevReceiveTime() >= RECEIVE_RATE)\n    {\n      planar->setReceiveDataFlag(false);   \n      initRC100();\n    }\n  }\n}\n\n#endif // REMOTECONTROLLER100_H_"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Scara/open_manipulator_scara/demo.h",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef DEMO_H_\n#define DEMO_H_\n\n#include <scara_libs.h>\n\nbool start_demo_flag;\nbool erasing_flag;\nuint8_t motion_cnt[] = {0};\nuint8_t sub_motion_cnt[] = {0};\n\n/*****************************************************************************\n** Functions used in runDemo()\n*****************************************************************************/\n// Move in Joint Space \nvoid moveJS(Scara* scara, double j1, double j2, double j3, double t) \n{\n  static std::vector <double> target_angle;\n  target_angle.clear();\n  target_angle.push_back(j1);\n  target_angle.push_back(j2);\n  target_angle.push_back(j3);\n  scara->makeJointTrajectory(target_angle,t);     \n}\n\n// Draw an Object \nvoid drawObj(Scara* scara, STRING object, double radius, int num_revolution, double start_angular_position, double move_time)\n{\n  double draw_arg[3]; \n  draw_arg[0] = radius;                 // Radius (m)\n  draw_arg[1] = num_revolution;         // Number of revolution\n  draw_arg[2] = start_angular_position; // Starting angular position (rad)\n  void* p_draw_arg = &draw_arg;\n\n  scara->makeCustomTrajectory(object, \"tool\", p_draw_arg, move_time);\n}\n\n// Erase an Object\nbool eraseObj(Scara *scara, int index)\n{\n  switch(sub_motion_cnt[index])\n  {\n  case 0: scara->makeToolTrajectory(\"tool\", -0.5); break;\n  case 1: moveJS(scara, -2.17, 0.82, 2.05, 3.0); break;\n  case 2: scara->sleepTrajectory(2.0); scara->makeToolTrajectory(\"tool\", -0.0); break;\n  case 3: scara->sleepTrajectory(2.0); scara->makeToolTrajectory(\"tool\", -0.5); return 1; \n  }\n  return 0;\n}\n\nbool drawCircle(Scara *scara, int index)\n{\n  switch(sub_motion_cnt[index])\n  {\n  case 0: scara->makeToolTrajectory(\"tool\", -0.5); break;\n  case 1: moveJS(scara, -1.05, 0.9, 0.9, 2.0); break;\n  case 2: scara->makeToolTrajectory(\"tool\", -0.0); break;\n  case 3: drawObj(scara, CUSTOM_TRAJECTORY_CIRCLE, 0.030, 1, 0.0, 10.0); return 1;\n  }\n  return 0;\n}\n\nbool drawCircle2(Scara *scara, int index)\n{\n  switch(sub_motion_cnt[index])\n  {\n  case 0: scara->makeToolTrajectory(\"tool\", -0.5); break;\n  case 1: moveJS(scara, -1.45, 1.2, 1.2, 2.0); break;\n  case 2: scara->makeToolTrajectory(\"tool\", -0.0); break;\n  case 3: drawObj(scara, CUSTOM_TRAJECTORY_CIRCLE, 0.020, 1, 0, 10.0); break; \n  case 4: drawObj(scara, CUSTOM_TRAJECTORY_CIRCLE, 0.020, 1, PI/3, 10.0); break; \n  case 5: drawObj(scara, CUSTOM_TRAJECTORY_CIRCLE, 0.020, 1, PI*2/3, 10.0); break; \n  case 6: drawObj(scara, CUSTOM_TRAJECTORY_CIRCLE, 0.020, 1, PI, 10.0); break; \n  case 7: drawObj(scara, CUSTOM_TRAJECTORY_CIRCLE, 0.020, 1, PI*4/3, 10.0); break; \n  case 8: drawObj(scara, CUSTOM_TRAJECTORY_CIRCLE, 0.020, 1, PI*5/3, 10.0); return 1;\n  }\n  return 0;\n}\n\nbool drawRhombus(Scara *scara, int index)\n{\n  switch(sub_motion_cnt[index])\n  {\n  case 0: scara->makeToolTrajectory(\"tool\", -0.5); break;\n  case 1: moveJS(scara, -1.8, 1.43, 1.43, 2.0); break;\n  case 2: scara->makeToolTrajectory(\"tool\", -0.0); break;\n  case 3: drawObj(scara, CUSTOM_TRAJECTORY_RHOMBUS, 0.035, 1, PI, 10.0); return 1;\n  }\n  return 0;\n}\n\nbool drawRhombus2(Scara *scara, int index)\n{\n  switch(sub_motion_cnt[index])\n  {\n  case 0: scara->makeToolTrajectory(\"tool\", -0.5); break;\n  case 1: moveJS(scara, -1.80, 1.43, 1.43, 2.0); break;\n  case 2: scara->makeToolTrajectory(\"tool\", -0.0); break;\n  case 3: drawObj(scara, CUSTOM_TRAJECTORY_RHOMBUS, 0.020, 1, PI, 10.0); break;\n  case 4: drawObj(scara, CUSTOM_TRAJECTORY_RHOMBUS, 0.027, 1, PI, 10.0); break;\n  case 5: drawObj(scara, CUSTOM_TRAJECTORY_RHOMBUS, 0.034, 1, PI, 10.0); break;\n  case 6: drawObj(scara, CUSTOM_TRAJECTORY_RHOMBUS, 0.041, 1, PI, 10.0); return 1;\n  }\n  return 0;\n}\n\nbool drawHeart(Scara *scara, int index)\n{\n  switch(sub_motion_cnt[index])\n  {\n  case 0: scara->makeToolTrajectory(\"tool\", -0.5); break;\n  case 1: moveJS(scara, -1.6, 1.3, 1.3, 2.0); break;\n  case 2: scara->makeToolTrajectory(\"tool\", -0.0); break;\n  case 3: drawObj(scara, CUSTOM_TRAJECTORY_HEART, 0.045, 1, PI, 10.0); return 1;\n  }\n  return 0;\n}\n\n/*****************************************************************************\n** Start or Stop Demo\n*****************************************************************************/\nvoid startDemo()\n{\n  // Start the demo\n  start_demo_flag = true;\n}\n\nvoid stopDemo(Scara *scara)\n{\n  // Stop the demo\n  start_demo_flag = false;\n\n  // Move to the default pose.\n  moveJS(scara, 0.0, 0.0, 0.0, 2.0); \n  scara->makeToolTrajectory(\"tool\", -0.5);\n\n  // Reset the count variables\n  motion_cnt[0] = 0;\n  sub_motion_cnt[0] = 0;\n  erasing_flag = false;\n}\n\n/*****************************************************************************\n** Initialize Demo\n*****************************************************************************/\nvoid initDemo()\n{\n  start_demo_flag = false;\n  motion_cnt[0] = 0;\n  sub_motion_cnt[0] = 0;\n  erasing_flag = false;\n\n  pinMode(BDPIN_PUSH_SW_1, INPUT);\n  pinMode(BDPIN_PUSH_SW_2, INPUT);\n}\n\n/*****************************************************************************\n** Run Demo\n*****************************************************************************/\nvoid runDemo(Scara *scara)\n{\n  if(digitalRead(BDPIN_PUSH_SW_1))\n  {\n    startDemo();\n  }\n  if(digitalRead(BDPIN_PUSH_SW_2))\n  {\n    stopDemo(scara);\n  }\n\n  if (scara->getMovingState())\n  {\n    return;\n  }\n  else \n  {\n    if (start_demo_flag)\n    {\n      // Draw Objects\n      if (!erasing_flag)\n      {\n        switch(motion_cnt[0])\n        {\n          case 0:\n            if(drawCircle(scara, 0))\n            { sub_motion_cnt[0] = 0; motion_cnt[0] ++; erasing_flag = true; }\n            else\n              sub_motion_cnt[0] ++;\n          break;\n          case 1:\n            if(drawCircle2(scara, 0))\n            { sub_motion_cnt[0] = 0; motion_cnt[0] ++; erasing_flag = true; }\n            else \n              sub_motion_cnt[0] ++;\n          break;\n          case 2:\n            if(drawRhombus(scara, 0))\n            { sub_motion_cnt[0] = 0; motion_cnt[0] ++; erasing_flag = true; }\n            else \n              sub_motion_cnt[0] ++;\n          break;\n          case 3:\n            if(drawRhombus2(scara, 0))\n            { sub_motion_cnt[0] = 0; motion_cnt[0] ++; erasing_flag = true; }\n            else\n              sub_motion_cnt[0] ++;\n          break;\n          case 4:\n            if(drawHeart(scara, 0))\n            { sub_motion_cnt[0] = 0; motion_cnt[0] = 0; erasing_flag = true; }\n            else \n              sub_motion_cnt[0] ++;\n          break;\n        }\n      }\n\n      // Erase Objects\n      else\n      {\n        if(eraseObj(scara, 0))\n        { sub_motion_cnt[0] = 0; erasing_flag = false; }\n        else \n          sub_motion_cnt[0] ++;\n      }\n    }\n  }\n}\n\n#endif // DEMO_H_\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Scara/open_manipulator_scara/open_manipulator_scara.ino",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include <scara_libs.h>\n#include \"remotecontroller100.h\"\n#include \"processing.h\"\n#include \"demo.h\"\n\nScara scara;\n\nvoid setup()\n{\n  scara.initDebug();\n\n  initRC100();\n\n  initProcessing();  \n\n  initDemo();\n\n  scara.initOpenManipulator(true); // true:  using actual hardware\n                                   // false: using only visualization tool \n}\n\nvoid loop()\n{ \n  receiveDataFromRC100(&scara);      \n\n  receiveDataFromProcessing(&scara); \n  sendDataToProcessing(&scara); \n\n  scara.processOpenManipulator(millis()/1000.0);    \n\n  runDemo(&scara); \n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Scara/open_manipulator_scara/processing.h",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef PROCESSING_H_\n#define PROCESSING_H_\n\n#include <scara_libs.h>\n#include \"demo.h\"\n\n/*****************************************************************************\n** Initialize baudrate for using Processing\n*****************************************************************************/\nvoid initProcessing()\n{ \n  Serial.begin(57600);\n\n  Serial.print(\"Initial actuator angles: \");\n  for (int i = 0; i < DXL_SIZE; i++)\n  {\n    Serial.print(0.0);\n    Serial.print(\",\");\n  }\n  Serial.println(\"\");\n  delay(300);             \n}\n\n/*****************************************************************************\n** Send data from Processing\n*****************************************************************************/\n// Send joint data to Processing \nvoid sendJointDataToProcessing(JointWaypoint joint_angle_vector) \n{\n  Serial.print(\"joint\");\n\n  for (int i = 0; i < (int)joint_angle_vector.size(); i++)\n  {\n    Serial.print(\",\");\n    Serial.print(joint_angle_vector.at(i).position,3);\n  }\n  Serial.print(\"\\n\");\n}\n\n// Send tool data(on or off) to Processing \nvoid sendToolDataToProcessing(bool onoff)\n{\n  Serial.print(\"tool\");\n  Serial.print(\",\");\n  Serial.print(onoff);\n  Serial.print(\"\\n\");\n}\n\n// Send tool data(values) to Processing \nvoid sendToolDataToProcessing(JointWaypoint tool_angle_vector)\n{\n  Serial.print(\"tool\");\n  \n  for (int i = 0; i < (int)tool_angle_vector.size(); i++)\n  {\n    Serial.print(\",\");\n    Serial.print(tool_angle_vector.at(i).position,3);\n  }\n  Serial.print(\"\\n\");\n}\n\n// Send joint and tool data(values) to Processing \nvoid sendDataToProcessing(Scara *scara)\n{\n  sendJointDataToProcessing(scara->getTrajectory()->getManipulator()->getAllJointValue());\n  sendToolDataToProcessing(scara->getTrajectory()->getManipulator()->getAllToolValue());\n}\n\n/*****************************************************************************\n** Receive data from Processing\n*****************************************************************************/\n// Split data by separator \nvoid split(String data, char separator, String* temp)\n{\n  int cnt = 0;\n  int get_index = 0;\n\n  String copy = data;\n  \n  while(true)\n  {\n    get_index = copy.indexOf(separator);\n\n    if(-1 != get_index)\n    {\n      temp[cnt] = copy.substring(0, get_index);\n      copy = copy.substring(get_index + 1);\n    }\n    else\n    {\n      temp[cnt] = copy.substring(0, copy.length());\n      break;\n    }\n    ++cnt;\n  }\n}\n\n// Parse data received from Processing \nString cmd[50];\nString* parseProcessingData(String get) \n{\n  get.trim();\n  split(get, ',', cmd);\n  \n  return cmd;\n}\n\n// Receive data from Processing \nvoid receiveDataFromProcessing(Scara *scara) \n{\n  if (!scara->getReceiveDataFlag())\n  {\n    if (Serial.available())\n    {\n      String serialInput = Serial.readStringUntil('\\n');\n      String *cmd = parseProcessingData(serialInput);\n\n      // Actuator Control Tab \n      if (cmd[0] == \"actuator\")\n      {\n        // Torque On/Off\n        if (cmd[1] == \"on\")\n        {\n          if(scara->getUsingActualRobotState())\n          {\n            scara->enableAllActuator();\n            sendDataToProcessing(scara);\n          }\n        }\n        else if (cmd[1] == \"off\")\n        {\n          if(scara->getUsingActualRobotState())\n          {\n            scara->disableAllActuator();\n          }\n        }\n      }\n\n      // Joint space control tab \n      else if (cmd[0] == \"joint\")\n      {\n        // Joint Torque on/off\n        if (cmd[1] == \"on\")\n        {\n          if (scara->getUsingActualRobotState())    \n          {\n            scara->enableAllJointActuator();\n            sendJointDataToProcessing(scara->getAllActiveJointValue());\n          }\n        }\n        else if (cmd[1] == \"off\")\n        {\n          if (scara->getUsingActualRobotState())    \n            scara->disableAllJointActuator();\n        }\n\n        // Joint Position Control\n        else\n        {\n          std::vector<double> goal_position;\n          for (uint8_t index = 0; index < DXL_SIZE; index++)\n          {\n            goal_position.push_back((double)cmd[index + 1].toFloat());\n          }\n          scara->makeJointTrajectory(goal_position, 1.0); \n        }\n      }\n\n      // Tool control tab \n      else if (cmd[0] == \"tool\")\n      {\n        // Tool Torque on/off\n        if (cmd[1] == \"y\")\n          scara->makeToolTrajectory(\"tool\", 0.0);\n        else if (cmd[1] == \"n\")\n          scara->makeToolTrajectory(\"tool\", -0.5);\n\n        // Torque On/Off\n        else if (cmd[1] == \"on\")\n        {\n          if (scara->getUsingActualRobotState())    \n            scara->enableAllToolActuator();\n        }\n        else if (cmd[1] == \"off\")\n        {\n          if (scara->getUsingActualRobotState())    \n            scara->disableAllToolActuator();\n        }\n\n        // Tool Position Control\n        else\n          scara->makeToolTrajectory(\"tool\", (double)cmd[1].toFloat());\n      }\n\n      // Task space control tab \n      else if (cmd[0] == \"task\")\n      {\n        if (cmd[1] == \"f\")\n          scara->makeTaskTrajectoryFromPresentPose(\"tool\", math::vector3( 0.010, 0.0, 0.0), 1.0);\n        else if (cmd[1] == \"b\")\n          scara->makeTaskTrajectoryFromPresentPose(\"tool\", math::vector3(-0.010, 0.0, 0.0), 1.0);\n        else if (cmd[1] == \"l\")\n          scara->makeTaskTrajectoryFromPresentPose(\"tool\", math::vector3(0.0,  0.010, 0.0), 1.0);\n        else if (cmd[1] == \"r\")\n          scara->makeTaskTrajectoryFromPresentPose(\"tool\", math::vector3(0.0, -0.010, 0.0), 1.0);\n        else\n          scara->makeTaskTrajectoryFromPresentPose(\"tool\", math::vector3(0.0, 0.0, 0.0), 1.0);\n      }\n\n      // Demo Control tab \n      else if (cmd[0] == \"demo\")\n      {\n        if (cmd[1] == \"start\")\n          startDemo();\n        else if (cmd[1] == \"stop\")\n          stopDemo(scara);\n      }\n\n//----------------------------------------------//\n//         DO NOT MODIFY THE BELOW CODE         //\n//----------------------------------------------//\n      scara->setReceiveDataFlag(true);\n      scara->setPrevReceiveTime(millis()/1000.0); \n    }\n  }\n  else \n  {\n    if (millis()/1000.0 - scara->getPrevReceiveTime() >= RECEIVE_RATE)\n    {\n      scara->setReceiveDataFlag(false); \n      initRC100();\n    }\n  }\n}\n\n#endif //PROCESSING_H\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Scara/open_manipulator_scara/remotecontroller100.h",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef REMOTECONTROLLER100_H_\n#define REMOTECONTROLLER100_H_\n\n#include <scara_libs.h>\n#include <RC100.h>\n#include \"demo.h\"\n\nRC100 rc100;\n\n/*****************************************************************************\n** Initialize baudrate for using RC100\n*****************************************************************************/\nvoid initRC100()\n{\n  rc100.begin(1); // using Serial2(=SerialBT1)\n}\n\n/*****************************************************************************\n** Receive data from RC100\n*****************************************************************************/\nvoid receiveDataFromRC100(Scara* scara)\n{\n  if (!scara->getReceiveDataFlag())\n  {\n    if (rc100.available())\n    {\n      scara->setReceiveDataFlag(true);\n\n      uint16_t data = rc100.readData();\n\n      // Task space control tab \n      if (data & RC100_BTN_U)\n        scara->makeTaskTrajectoryFromPresentPose(\"tool\", math::vector3(0.006, 0.0, 0.0), 0.16);\n      else if (data & RC100_BTN_D)\n        scara->makeTaskTrajectoryFromPresentPose(\"tool\", math::vector3(-0.006, 0.0, 0.0), 0.16);\n      else if (data & RC100_BTN_L)\n        scara->makeTaskTrajectoryFromPresentPose(\"tool\", math::vector3(0.0, 0.006, 0.0), 0.16);\n      else if (data & RC100_BTN_R)\n        scara->makeTaskTrajectoryFromPresentPose(\"tool\", math::vector3(0.0, -0.006, 0.0), 0.16);\n      else if (data & RC100_BTN_1)\n        scara->makeToolTrajectory(\"tool\", 0.0);\n      else if (data & RC100_BTN_2)\n        scara->makeToolTrajectory(\"tool\", 1.0);\n      else if (data & RC100_BTN_3)\n        startDemo();\n      else if (data & RC100_BTN_4)\n        stopDemo(scara);\n      else if (data & RC100_BTN_5)\n      {\n        std::vector<double> goal_position;\n        goal_position.push_back(-60.0 * DEG2RAD);\n        goal_position.push_back(20.0 * DEG2RAD);\n        goal_position.push_back(40.0 * DEG2RAD);\n        scara->makeJointTrajectory(goal_position, 1.0);\n      }\n      else if (data & RC100_BTN_6)\n      {\n        std::vector<double> goal_position;\n        goal_position.push_back(0.0);\n        goal_position.push_back(0.0);\n        goal_position.push_back(0.0);\n        scara->makeJointTrajectory(goal_position, 0.5);\n      }\n\n//----------------------------------------------//\n//         DO NOT MODIFY THE BELOW CODE         //\n//----------------------------------------------//\n      scara->setReceiveDataFlag(true);\n      scara->setPrevReceiveTime(millis()/1000.0); \n    }\n  }\n  else \n  {\n    if (millis()/1000.0 - scara->getPrevReceiveTime() >= RECEIVE_RATE)\n    {\n      scara->setReceiveDataFlag(false);   \n      initRC100();\n    }\n  }\n}\n\n#endif // REMOTECONTROLLER100_H_"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Stewart/open_manipulator_stewart/demo.h",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef DEMO_H_\n#define DEMO_H_\n\n#include <stewart_libs.h>\n\nbool start_demo_flag;\nuint8_t motion_cnt[] = {0};\n\n/*****************************************************************************\n** Start or Stop Demo\n*****************************************************************************/\nvoid startDemo()\n{\n  // Start the demo\n  start_demo_flag = true;\n}\n\nvoid stopDemo(Stewart *stewart)\n{\n  // Stop the demo\n  start_demo_flag = false;\n\n  // Move to the default pose.\n  stewart->makeTaskTrajectory(\"tool\", math::vector3(0.0, 0.0, 0.0), 2.0);\n\n  // Reset the count variables\n  motion_cnt[0] = 0;\n}\n\n/*****************************************************************************\n** Initialize Demo\n*****************************************************************************/\nvoid initDemo()\n{\n  start_demo_flag = false;\n  motion_cnt[0] = 0;\n}\n\n/*****************************************************************************\n** Run Demo\n*****************************************************************************/\nvoid runDemo(Stewart *stewart)\n{\n  if(digitalRead(BDPIN_PUSH_SW_1))\n  {\n    startDemo();\n  }\n  if(digitalRead(BDPIN_PUSH_SW_2))\n  {\n    stopDemo(stewart);    \n  }\n\n  if (stewart->getMovingState()) \n  {\n    return;\n  }\n  else \n  {\n    if (start_demo_flag)\n    {\n      switch(motion_cnt[0])\n      {\n        case 0:\n          stewart->makeTaskTrajectory(\"tool\", math::vector3( 0.025, 0.0, 0.0), 1.0);\n          motion_cnt[0] ++; \n        break;\n        case 1:\n          stewart->makeTaskTrajectory(\"tool\", math::vector3(-0.025, 0.0, 0.0), 1.0/2);\n          motion_cnt[0] ++; \n        break;\n        case 2:\n          stewart->makeTaskTrajectory(\"tool\", math::vector3( 0.025, 0.0, 0.0), 1.0/2);\n          motion_cnt[0] ++; \n        break;\n        case 3:\n          stewart->makeTaskTrajectory(\"tool\", math::vector3(-0.025, 0.0, 0.0), 1.0/2);\n          motion_cnt[0] ++; \n        break;\n        case 4:\n          stewart->makeTaskTrajectory(\"tool\", math::vector3(0.0, 0.025, 0.0), 1.0/2);\n          motion_cnt[0] ++; \n        break;\n        case 5:\n          stewart->makeTaskTrajectory(\"tool\", math::vector3(0.0, -0.025, 0.0), 1.0/2);\n          motion_cnt[0] ++; \n        break;\n        case 6:\n          stewart->makeTaskTrajectory(\"tool\", math::vector3(0.0,  0.025, 0.0), 1.0/2);\n          motion_cnt[0] ++; \n        break;\n        case 7:\n          stewart->makeTaskTrajectory(\"tool\", math::vector3(0.0, -0.025, 0.0), 1.0/2);\n          motion_cnt[0] ++; \n        break;\n        case 8:\n          stewart->makeTaskTrajectory(\"tool\", math::vector3(0.0, 0.0, 0.020), 1.0/2);\n          motion_cnt[0] ++; \n        break;\n        case 9:\n          stewart->makeTaskTrajectory(\"tool\", math::vector3(0.0, 0.0, -0.0), 1.0/2);\n          motion_cnt[0] ++; \n        break;\n        case 10:\n          stewart->makeTaskTrajectory(\"tool\", math::vector3(0.0, 0.0, 0.020), 1.0/2);\n          motion_cnt[0] ++; \n        break;\n        case 11:\n          stewart->makeTaskTrajectory(\"tool\", math::vector3(0.0, 0.0, -0.0), 1.0/2);\n          motion_cnt[0] ++; \n        break;\n        case 12:\n        {\n          Pose goal_pose;\n          goal_pose.kinematic.position = math::vector3(0.0, 0.0, 0.0);\n          goal_pose.kinematic.orientation = math::convertRollAngleToRotationMatrix(PI/18.0);\n          stewart->makeTaskTrajectory(\"tool\", goal_pose.kinematic, 1.0);\n          motion_cnt[0] ++; \n        }\n        break;\n        case 13:\n        {\n          Pose goal_pose;\n          goal_pose.kinematic.position = math::vector3(0.0, 0.0, 0.0);\n          goal_pose.kinematic.orientation = math::convertRollAngleToRotationMatrix(-PI/18.0);\n          stewart->makeTaskTrajectory(\"tool\", goal_pose.kinematic, 1.0/2);\n          motion_cnt[0] ++; \n        }\n        break;\n        case 14:\n        {\n          Pose goal_pose;\n          goal_pose.kinematic.position = math::vector3(0.0, 0.0, 0.0);\n          goal_pose.kinematic.orientation = math::convertPitchAngleToRotationMatrix(PI/18.0);\n          stewart->makeTaskTrajectory(\"tool\", goal_pose.kinematic, 1.0/2);\n          motion_cnt[0] ++; \n        }\n        break;\n        case 15:\n        {\n          Pose goal_pose;\n          goal_pose.kinematic.position = math::vector3(0.0, 0.0, 0.0);\n          goal_pose.kinematic.orientation = math::convertPitchAngleToRotationMatrix(-PI/18.0);\n          stewart->makeTaskTrajectory(\"tool\", goal_pose.kinematic, 1.0/2);\n          motion_cnt[0] ++; \n        }\n        break;\n        case 16:\n        {\n          Pose goal_pose;\n          goal_pose.kinematic.position = math::vector3(0.0, 0.0, 0.0);\n          goal_pose.kinematic.orientation = math::convertYawAngleToRotationMatrix(PI/6.0);\n          stewart->makeTaskTrajectory(\"tool\", goal_pose.kinematic, 1.0/2);\n          motion_cnt[0] ++; \n        }\n        break;\n        case 17:\n        {\n          Pose goal_pose;\n          goal_pose.kinematic.position = math::vector3(0.0, 0.0, 0.0);\n          goal_pose.kinematic.orientation = math::convertYawAngleToRotationMatrix(-PI/6.0);\n          stewart->makeTaskTrajectory(\"tool\", goal_pose.kinematic, 1.0/2);\n          motion_cnt[0] ++; \n        }\n        break;\n        case 18:\n        {\n          Pose goal_pose;\n          goal_pose.kinematic.position = math::vector3(0.0, 0.0, 0.0);\n          goal_pose.kinematic.orientation = math::convertRollAngleToRotationMatrix(0.0);\n          stewart->makeTaskTrajectory(\"tool\", goal_pose.kinematic, 1.0/2);\n          motion_cnt[0] ++; \n        }\n        break;\n        case 19:\n          // stewart->sleepTrajectory(10.0);\n          // motion_cnt[0] = 0; \n        break;\n      }\n    }\n  }\n}\n\n#endif // DEMO_H_\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Stewart/open_manipulator_stewart/demo2.h",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef DEMO2_H_\n#define DEMO2_H_\n\n#include <stewart_libs.h>\n\n/*****************************************************************************\n** Touch panel stuff for detecting ball position\n*****************************************************************************/\n#define PIN_LR      8\n#define PIN_LL      9\n#define PIN_UR      10\n#define PIN_UL      11\n#define PIN_COM     A0\n\nbool touch = 0;\ndouble touch_position[2];\n\nvoid touchPanelInit()\n{\n  pinMode(PIN_LR, OUTPUT);\n  pinMode(PIN_LL, OUTPUT);  \n  pinMode(PIN_UR, OUTPUT);\n  pinMode(PIN_UL, OUTPUT);\n\n  digitalWrite(PIN_LR, LOW);\n  digitalWrite(PIN_LL, LOW);\n  digitalWrite(PIN_UR, LOW);\n  digitalWrite(PIN_UL, LOW);\n}\n\nint touchAvailable(void)\n{\n  int pin_data;\n  \n  digitalWrite(PIN_UL, LOW);\n  digitalWrite(PIN_UR, LOW);\n  digitalWrite(PIN_LL, LOW);\n  digitalWrite(PIN_LR, LOW);\n  \n  pinMode(PIN_COM, INPUT_PULLUP);\n  delay(2);  \n  pin_data = digitalRead(PIN_COM);\n  pinMode(PIN_COM, INPUT_ANALOG);\n  \n  return pin_data; \n}\n\nint touchX(void)\n{\n  digitalWrite(PIN_UL, LOW);\n  digitalWrite(PIN_UR, HIGH);\n  digitalWrite(PIN_LL, HIGH);\n  digitalWrite(PIN_LR, LOW);\n\n  delay(2);\n  return analogRead(PIN_COM); \n}\n\nint touchY(void)\n{\n  digitalWrite(PIN_UL, LOW);\n  digitalWrite(PIN_UR, LOW);\n  digitalWrite(PIN_LL, HIGH);\n  digitalWrite(PIN_LR, HIGH);\n\n  delay(2);\n  return analogRead(PIN_COM); \n}\n\n/*****************************************************************************\n** PID stuff for ball position\n*****************************************************************************/\nint16_t ball_x_pos, ball_y_pos;\nint16_t measured_x_pos, measured_y_pos;\ndouble corrected_x_pos, corrected_y_pos;\n\nint16_t set_x_pos = 0, set_y_pos = 0;\nint16_t x_pos_array [79], y_pos_array [79];\ndouble x_avg [16], y_avg [16];\n\ndouble FPGA_x_angle = 0, FPGA_y_angle = 0;\ndouble testxangle = 0, testyangle = 0;\n\ndouble p_gain = 0.28, i_gain = 0.01, d_gain = 1.5;//550\n\ndouble x_offset = -10, y_offset = 0;\ndouble error_x = 0, error_y = 0;\n\ndouble i_x = 0, i_y = 0;\n\ndouble d_x = 0, d_y = 0;\n\ndouble d_x_avg = 0, d_y_avg = 0;\ndouble d_x_pos = 0, d_y_pos = 0;\ndouble d_x_neg = 0, d_y_neg = 0;\n\nstatic int count_for_round = 0;\n\nint i, j;\n\nvoid ball_PID(Stewart *stewart)\n{\n  // Raw Ball Position\n  touch_position[0] = double(touchX()-520) / 520.0 * 310.0;\n  touch_position[1] = double(touchY()-520) / 520.0 * 230.0;\n\n  if (touchAvailable()==1) {\n    touch_position[0] = 0;\n    touch_position[1] = 0;\n  }\n\n  corrected_x_pos = touch_position[0];\n  corrected_y_pos = touch_position[1];\n\n  Serial.print(\"T : \");\n  Serial.print(touchAvailable());\n    \n  // Serial.print(\"\\t X : \");\n  // Serial.print(touch_position[0]);\n  // Serial.print(\"\\tY : \");\n  // Serial.print(touch_position[1]);\n  // Serial.println(); \n\n\n  if (stewart->getOffsetPositionNum() == 0) \n  {\n    set_x_pos = 0;\n    set_y_pos = 0;\n    count_for_round = 0;\n  }\n  else if (stewart->getOffsetPositionNum() == 1) \n  {\n    set_x_pos = -20;\n    set_y_pos = 15;\n    count_for_round = 0;\n  }\n  else if (stewart->getOffsetPositionNum() == 2) \n  {\n    set_x_pos = -20;\n    set_y_pos = -15;\n    count_for_round = 0;\n  }\n  else if (stewart->getOffsetPositionNum() == 3) \n  {\n    set_x_pos = 20;\n    set_y_pos = -15;\n    count_for_round = 0;\n  }\n  else if (stewart->getOffsetPositionNum() == 4) \n  {\n    set_x_pos = 20;\n    set_y_pos = 15;\n    count_for_round = 0;\n  }\n  else if (stewart->getOffsetPositionNum() == 5) \n  {\n    set_x_pos = 75*cos((double)count_for_round/10.0);\n    set_y_pos = 75*sin((double)count_for_round/10.0);\n    count_for_round++;\n    if (count_for_round == 6280) count_for_round = 0;\n  }\n  else if (stewart->getOffsetPositionNum() == 6) \n  {\n    set_x_pos = 75*cos((double)count_for_round/10.0);\n    set_y_pos =-75*sin((double)count_for_round/10.0);\n    count_for_round++;\n    if (count_for_round == 6280) count_for_round = 0;\n  }\n\n  // P value\n  error_x = (set_x_pos - corrected_x_pos) ;\n  error_y = (set_y_pos - corrected_y_pos) ;\n\n  // D value\n  //fill ball history array\n  for (i = 0; i < 79; i ++)\n  {\n    x_pos_array [i + 1] = x_pos_array [i];\n    y_pos_array [i + 1] = y_pos_array [i];\n  }\n  x_pos_array [0] = corrected_x_pos;\n  y_pos_array [0] = corrected_y_pos;\n\n  for (i = 0; i < 16; i ++)\n  {\n    x_avg[i] = x_pos_array [i * 5]; //5\n    y_avg[i] = y_pos_array [i * 5]; //5\n  }\n\n  d_x_pos = 322.0 * x_avg[0] + 217.0 * x_avg[1] + 110.0 * x_avg[2] + 35.0 * x_avg[3] + 25.0 * x_avg[13] + 98.0 * x_avg[14] + 203.0 * x_avg[15]; //\n  d_y_pos = 322.0 * y_avg[0] + 217.0 * y_avg[1] + 110.0 * y_avg[2] + 35.0 * y_avg[3] + 25.0 * y_avg[13] + 98.0 * y_avg[14] + 203.0 * y_avg[15];\n\n  d_x_neg = -42.0 * x_avg[4] - 87.0 * x_avg[5] - 134.0 * x_avg[6] - 149.0 * x_avg[7] - 166.0 * x_avg[8] - 151.0 * x_avg[9] - 138.0 * x_avg[10] - 93.0 * x_avg[11] - 50.0 * x_avg[12];\n  d_y_neg = -42.0 * y_avg[4] - 87.0 * y_avg[5] - 134.0 * y_avg[6] - 149.0 * y_avg[7] - 166.0 * y_avg[8] - 151.0 * y_avg[9] - 138.0 * y_avg[10] - 93.0 * y_avg[11] - 50.0 * y_avg[12];\n\n  d_x = (d_x_pos + d_x_neg) * d_gain / 28.56;\n  d_y = (d_y_pos + d_y_neg) * d_gain / 28.56;\n\n  d_x_avg = .5 * d_x + .5 * d_x_avg;\n  d_y_avg = .5 * d_y + .5 * d_y_avg;\n\n  // I value\n  if (error_x < 200 && error_x > -200) i_x += i_gain * error_x / 10.0;\n  else i_x = 0;\n  if (error_y < 200 && error_y > -200) i_y += i_gain * error_y / 10.0;\n  else i_y = 0;\n\n  if (i_gain == 0)\n  {\n    i_x = 0;\n    i_y = 0;\n  }\n\n  if (i_x > 400.0) i_x = 400.0;\n  else if (i_x < -400.0) i_x = -400.0;\n\n  if (i_y > 400.0) i_y = 400.0;\n  else if (i_y < -400.0) i_y = -400.0;\n\n\n  FPGA_x_angle = error_x * p_gain + i_x - d_x_avg + x_offset;\n  FPGA_y_angle = error_y * p_gain + i_y - d_y_avg + y_offset;\n  testxangle = error_x * p_gain;\n  testyangle = error_y * p_gain;\n\n  Serial.print(\"\\t OffsetNum : \");\n  Serial.print(stewart->getOffsetPositionNum());\n  Serial.print(\"\\t set_X : \");\n  Serial.print(set_x_pos,2);\n  Serial.print(\"\\t set_Y : \");\n  Serial.print(set_y_pos,2);\n  Serial.print(\"\\t curr_x : \");\n  Serial.print(corrected_x_pos,2);\n  Serial.print(\"\\t curr_Y : \");\n  Serial.print(corrected_y_pos,2);\n  Serial.println(); \n  Serial.print(\"\\t Ent_X : \");\n  Serial.print(FPGA_x_angle,2);\n  Serial.print(\"\\t Ent_Y : \");\n  Serial.print(FPGA_y_angle,2);\n  Serial.print(\"\\t Prop_X : \");\n  Serial.print(testxangle,2);\n  Serial.print(\"\\t Prop_Y : \");\n  Serial.print(testyangle,2);\n  Serial.print(\"\\t Dete_X : \");\n  Serial.print(d_x / d_gain,2);\n  Serial.print(\"\\t Dete_Y : \");\n  Serial.print(d_y / d_gain,2);\n  Serial.println(); \n}\n\n/*****************************************************************************\n** For calculating Median and Average\n*****************************************************************************/\nstd::vector<double> sample_angle_x_for_median;\nstd::vector<double> sample_angle_y_for_median;\nstd::vector<double> sample_angle_1_for_average;\nstd::vector<double> sample_angle_2_for_average;\nstd::vector<double> sample_angle_3_for_average;\nstd::vector<double> sample_angle_4_for_average;\nstd::vector<double> sample_angle_5_for_average;\nstd::vector<double> sample_angle_6_for_average;\n\ndouble calcMedian(std::vector<double> *sample_angle_vector, double new_sample) \n{\n  std::vector<double> _sample_angle_vector;\n  double result;\n\n  // Add new sample\n  if (sample_angle_vector->size() < 10)\n  {\n    sample_angle_vector->push_back(new_sample);\n  }\n  else \n  {\n    for (int8_t i=0; i<9; i++)\n    {\n      sample_angle_vector->at(i) = sample_angle_vector->at(i+1);\n    }\n    sample_angle_vector->at(9) = new_sample;\n  }\n\n  \n  _sample_angle_vector = *sample_angle_vector;\n\n  // Sort values\n  std::sort(_sample_angle_vector.begin(),_sample_angle_vector.end());\n\n  // Compute Median \n  if(_sample_angle_vector.size()%2==1) //Number of elements are odd\n  {\n    result = _sample_angle_vector[_sample_angle_vector.size()/2];\n  }\n  else // Number of elements are even\n  {\n    int index = _sample_angle_vector.size()/2;\n    result = (_sample_angle_vector[index-1] + _sample_angle_vector[index])/2;\n  }\n\n  return result;\n}\n\ndouble calcAverage(std::vector<double> *sample_angle_vector, double new_sample) \n{\n  std::vector<double> _sample_angle_vector;\n  double result;\n\n  // Add new sample\n  if (sample_angle_vector->size() < 10) \n  {\n    sample_angle_vector->push_back(new_sample);\n  }\n  else \n  {\n    for (int8_t i=0; i<9; i++)\n    {\n      sample_angle_vector->at(i) = sample_angle_vector->at(i+1);\n    }\n    sample_angle_vector->at(9) = new_sample;\n  }\n\n\n  _sample_angle_vector = *sample_angle_vector;\n\n  // Compute Average\n  double sum;\n  for (int8_t i=0; i<_sample_angle_vector.size(); i++)\n  {\n    sum += _sample_angle_vector.at(i);\n  }\n\n  result = sum / _sample_angle_vector.size();\n\n  return result;\n}\n\n/*****************************************************************************\n** Start or Stop Demo\n*****************************************************************************/\nbool start_demo_flag;\n\nvoid startDemo()\n{\n  // Start the demo\n  start_demo_flag = true;\n}\n\nvoid stopDemo(Stewart *stewart)\n{\n  // Stop the demo\n  start_demo_flag = false;\n\n  // Move to the default pose.\n  stewart->makeTaskTrajectory(\"tool\", math::vector3(0.0, 0.0, 0.0), 2.0);\n}\n\n/*****************************************************************************\n** Initialize Demo\n*****************************************************************************/\nvoid initDemo()\n{\n  touchPanelInit();\n}\n\n/*****************************************************************************\n** Run Demo\n*****************************************************************************/\nvoid runDemo(Stewart *stewart)\n{\n  if(digitalRead(BDPIN_PUSH_SW_1))\n  {\n    startDemo();\n  }\n  if(digitalRead(BDPIN_PUSH_SW_2))\n  {\n    stopDemo(stewart);    \n  }\n\n  if (stewart->getMovingState()) \n  {\n    return;\n  }\n  else\n  {\n    if (start_demo_flag)\n    {\n      ball_PID(stewart);\n\n      // Compute X, Y Position\n      double x_input;\n      double y_input;\n\n      x_input = calcMedian(&sample_angle_x_for_median, double(FPGA_x_angle)) /10*DEG2RAD;\n      y_input = calcMedian(&sample_angle_y_for_median, double(FPGA_y_angle)) /10*DEG2RAD;\n\n      if (x_input >  10*DEG2RAD) x_input =  10*DEG2RAD;\n      if (x_input < -10*DEG2RAD) x_input = -10*DEG2RAD;\n      if (y_input >  10*DEG2RAD) y_input =  10*DEG2RAD;\n      if (y_input < -10*DEG2RAD) y_input = -10*DEG2RAD;\n\n\n      Eigen::Matrix4d robot_balancing;\n      robot_balancing = RM_MATH::getRotation4d(x_input, y_input, 0);\n      // robot_balancing = RM_MATH::getRotation4d((-touch_position[0]/10)*DEG2RAD, (-touch_position[1]/10)*DEG2RAD, 0);\n\n      Pose goal_pose;\n      goal_pose.position = RM_MATH::makeVector3(0.0, 0.0, 0.0);\n      goal_pose.orientation = RM_MATH::makeMatrix3(robot_balancing(0,0), robot_balancing(0,1), robot_balancing(0,2),\n                                                  robot_balancing(1,0), robot_balancing(1,1), robot_balancing(1,2),\n                                                  robot_balancing(2,0), robot_balancing(2,1), robot_balancing(2,2));\n\n      // Compute Joint Angular Position\n      std::vector<double> goal_joint_values;\n\n      stewart->inverseKinematics(\"tool\", goal_pose, &goal_joint_values);\n\n      std::vector<double> angle_input;\n\n      double curr_motor_angle[6];\n\n      //add deadbamd that the motors do nothing\n      curr_motor_angle[0] = stewart->getJointValue(\"joint1\").value;\n      curr_motor_angle[1] = stewart->getJointValue(\"joint2\").value;\n      curr_motor_angle[2] = stewart->getJointValue(\"joint3\").value;\n      curr_motor_angle[3] = stewart->getJointValue(\"joint4\").value;\n      curr_motor_angle[4] = stewart->getJointValue(\"joint5\").value;\n      curr_motor_angle[5] = stewart->getJointValue(\"joint6\").value;\n\n      double set_speed[6];\n\n      angle_input.push_back(calcAverage(&sample_angle_1_for_average, goal_joint_values.at(0)));\n      angle_input.push_back(calcAverage(&sample_angle_2_for_average, goal_joint_values.at(1)));\n      angle_input.push_back(calcAverage(&sample_angle_3_for_average, goal_joint_values.at(2)));\n      angle_input.push_back(calcAverage(&sample_angle_4_for_average, goal_joint_values.at(3)));\n      angle_input.push_back(calcAverage(&sample_angle_5_for_average, goal_joint_values.at(4)));\n      angle_input.push_back(calcAverage(&sample_angle_6_for_average, goal_joint_values.at(5)));\n\n      for (int8_t i=0; i<6; i++)\n      {\n        angle_input.push_back(goal_joint_values.at(i));\n      }\n\n      double deadband = 2*DEG2RAD;\n      for (int8_t i=0; i<6; i++)\n      {\n        if (curr_motor_angle[i] - angle_input.at(i) < deadband && curr_motor_angle[i] - angle_input.at(i) > -deadband) \n          angle_input.at(i) = curr_motor_angle[i];\n      }\n\n      stewart->jointTrajectoryMove(angle_input, 0.05);\n      // stewart->jointTrajectoryMove(angle_input, 0.1);\n    }\n  }\n}\n\n#endif // DEMO2_H_\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Stewart/open_manipulator_stewart/open_manipulator_stewart.ino",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include <stewart_libs.h>\n#include \"remotecontroller100.h\"\n#include \"processing.h\"\n#include \"demo.h\"\n\nStewart stewart;\n\nvoid setup()\n{\n  stewart.initDebug();\n\n  initRC100();       \n\n  initProcessing();  \n\n  initDemo();\n\n  stewart.initOpenManipulator(true); // true:  using actual hardware \n                                     // false: using only visualization tool \n}\n\nvoid loop()\n{\n  receiveDataFromRC100(&stewart);      \n\n  receiveDataFromProcessing(&stewart); \n  sendDataToProcessing(&stewart); \n\n  stewart.processOpenManipulator(millis()/1000.0);     \n\n  runDemo(&stewart); \n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Stewart/open_manipulator_stewart/processing.h",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef PROCESSING_H_\n#define PROCESSING_H_\n\n#include <stewart_libs.h>\n#include \"demo.h\"\n\n/*****************************************************************************\n** Initialize baudrate for using Processing\n*****************************************************************************/\nvoid initProcessing()\n{ \n  Serial.begin(57600);\n\n  Serial.print(\"Initial actuator angles: \");\n  for (int i = 0; i < DXL_SIZE; i++)\n  {\n    Serial.print(0.0);\n    Serial.print(\",\");\n  }\n  Serial.println(\"\");\n  delay(300);\n}\n\n/*****************************************************************************\n** Send data from Processing\n*****************************************************************************/\n// Send joint data to Processing \nvoid sendJointDataToProcessing(JointWaypoint joint_angle_vector) \n{\n  Serial.print(\"joint\");\n\n  for (int i = 0; i < (int)joint_angle_vector.size(); i++)\n  {\n    Serial.print(\",\");\n    Serial.print(joint_angle_vector.at(i).position,3);\n  }\n  Serial.print(\"\\n\");\n}\n\n// Send joint and tool data(values) to Processing \nvoid sendDataToProcessing(Stewart *stewart)\n{\n  sendJointDataToProcessing(stewart->getTrajectory()->getManipulator()->getAllJointValue());\n}\n\n/*****************************************************************************\n** Receive data from Processing\n*****************************************************************************/\n// Split data by separator \nvoid split(String data, char separator, String* temp)\n{\n  int cnt = 0;\n  int get_index = 0;\n\n  String copy = data;\n  \n  while(true)\n  {\n    get_index = copy.indexOf(separator);\n\n\tif(-1 != get_index)\n\t{\n\t  temp[cnt] = copy.substring(0, get_index);\n  \tcopy = copy.substring(get_index + 1);\n\t}\n\telse\n\t{\n    temp[cnt] = copy.substring(0, copy.length());\n\t  break;\n\t}\n\t  ++cnt;\n  }\n}\n\n// Parse data received from Processing \nString cmd[50];\nString* parseProcessingData(String get) \n{\n  get.trim();\n  split(get, ',', cmd);\n  \n  return cmd;\n}\n\n// Receive data from Processing \nvoid receiveDataFromProcessing(Stewart *stewart) \n{\n  if (!stewart->getReceiveDataFlag())\n  {\n    if (Serial.available())\n    {\n      String serialInput = Serial.readStringUntil('\\n');\n      String *cmd = parseProcessingData(serialInput);\n\n      // Actuator Control Tab \n      if (cmd[0] == \"actuator\")\n      {\n        // Torque On/Off\n        if (cmd[1] == \"on\")\n        {\n          if(stewart->getUsingActualRobotState())\n          {\n            stewart->enableAllActuator();\n            sendDataToProcessing(stewart);\n          }\n        }\n        else if (cmd[1] == \"off\")\n        {\n          if(stewart->getUsingActualRobotState())\n          {\n            stewart->disableAllActuator();\n          }\n        }\n      }\n\n      // Joint space control tab \n      else if (cmd[0] == \"joint\")\n      {\n        // Joint Torque on/off\n        if (cmd[1] == \"on\")\n        {\n          if (stewart->getUsingActualRobotState())    \n          {\n            stewart->enableAllJointActuator();\n            sendJointDataToProcessing(stewart->getAllActiveJointValue());\n          }\n        }\n        else if (cmd[1] == \"off\")\n        {\n          if (stewart->getUsingActualRobotState())    \n            stewart->disableAllJointActuator();\n        }\n\n        // Joint Position Control\n        else\n        {\n          std::vector<double> goal_position;\n          for (uint8_t index = 0; index < DXL_SIZE; index++)\n          {\n            goal_position.push_back((double)cmd[index + 1].toFloat());\n          }\n          stewart->makeJointTrajectory(goal_position, 1.0); \n        }\n      }\n\n      // Task space control tab \n      else if (cmd[0] == \"task\")\n      {\n        if (cmd[1] == \"f\")\n          stewart->makeTaskTrajectory(\"tool\", math::vector3( 0.020, 0.0, 0.0), 1.0);\n        else if (cmd[1] == \"b\")\n          stewart->makeTaskTrajectory(\"tool\", math::vector3(-0.020, 0.0, 0.0), 1.0);\n        else if (cmd[1] == \"l\")\n          stewart->makeTaskTrajectory(\"tool\", math::vector3(0.0,  0.020, 0.0), 1.0);\n        else if (cmd[1] == \"r\")\n          stewart->makeTaskTrajectory(\"tool\", math::vector3(0.0, -0.020, 0.0), 1.0);\n        else if (cmd[1] == \"u\")\n          stewart->makeTaskTrajectory(\"tool\", math::vector3(0.0, 0.0, 0.015), 1.0);\n        else if (cmd[1] == \"d\")\n          stewart->makeTaskTrajectory(\"tool\", math::vector3(0.0, 0.0, -0.015), 1.0);\n        else if (cmd[1] == \"rotx\")\n        {\n          Pose goal_pose;\n          goal_pose.kinematic.position = math::vector3(0.0, 0.0, 0.0);\n          goal_pose.kinematic.orientation = math::convertRollAngleToRotationMatrix(PI/18.0);\n          stewart->makeTaskTrajectory(\"tool\", goal_pose.kinematic, 1.0);\n        }\n        else if (cmd[1] == \"rotxi\")\n        {\n          Pose goal_pose;\n          goal_pose.kinematic.position = math::vector3(0.0, 0.0, 0.0);\n          goal_pose.kinematic.orientation = math::convertRollAngleToRotationMatrix(-PI/18.0);\n          stewart->makeTaskTrajectory(\"tool\", goal_pose.kinematic, 1.0);\n        }\n        else if (cmd[1] == \"roty\")\n        {\n          Pose goal_pose;\n          goal_pose.kinematic.position = math::vector3(0.0, 0.0, 0.0);\n          goal_pose.kinematic.orientation = math::convertPitchAngleToRotationMatrix(PI/18.0);\n          stewart->makeTaskTrajectory(\"tool\", goal_pose.kinematic, 1.0);\n        }\n        else if (cmd[1] == \"rotyi\")\n        {\n          Pose goal_pose;\n          goal_pose.kinematic.position = math::vector3(0.0, 0.0, 0.0);\n          goal_pose.kinematic.orientation = math::convertPitchAngleToRotationMatrix(-PI/18.0);\n          stewart->makeTaskTrajectory(\"tool\", goal_pose.kinematic, 1.0);\n        }\n        else if (cmd[1] == \"rotz\")\n        {\n          Pose goal_pose;\n          goal_pose.kinematic.position = math::vector3(0.0, 0.0, 0.0);\n          goal_pose.kinematic.orientation = math::convertYawAngleToRotationMatrix(PI/6.0);\n          stewart->makeTaskTrajectory(\"tool\", goal_pose.kinematic, 1.0);\n        }\n        else if (cmd[1] == \"rotzi\")\n        {\n          Pose goal_pose;\n          goal_pose.kinematic.position = math::vector3(0.0, 0.0, 0.0);\n          goal_pose.kinematic.orientation = math::convertYawAngleToRotationMatrix(-PI/6.0);\n          stewart->makeTaskTrajectory(\"tool\", goal_pose.kinematic, 1.0);\n        }\n        else\n        {\n          Pose goal_pose;\n          goal_pose.kinematic.position = math::vector3(0.0, 0.0, 0.0);\n          goal_pose.kinematic.orientation = math::convertRollAngleToRotationMatrix(0.0);\n          stewart->makeTaskTrajectory(\"tool\", goal_pose.kinematic, 1.0);\n        }\n      }\n\n      // Demo Control tab \n      else if (cmd[0] == \"demo\")\n      {\n        if (cmd[1] == \"start\")\n          startDemo();\n        else if (cmd[1] == \"stop\")\n          stopDemo(stewart);\n      }\n\n//----------------------------------------------//\n//         DO NOT MODIFY THE BELOW CODE         //\n//----------------------------------------------//\n      stewart->setReceiveDataFlag(true);  \n      stewart->setPrevReceiveTime(millis()/1000.0);\n    }\n  }\n  else\n  {\n    if (millis()/1000.0 - stewart->getPrevReceiveTime() >= RECEIVE_RATE)\n    {\n      stewart->setReceiveDataFlag(false); \n      initRC100();\n    }\n  }\n}\n\n#endif  //PROCESSING_H"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/example/Stewart/open_manipulator_stewart/remotecontroller100.h",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef REMOTECONTROLLER100_H_\n#define REMOTECONTROLLER100_H_\n\n#include <stewart_libs.h>\n#include <RC100.h>\n#include \"demo.h\"\n\nRC100 rc100;\n\n/*****************************************************************************\n** Initialize baudrate for using RC100\n*****************************************************************************/\nvoid initRC100()\n{\n  rc100.begin(1); // using Serial2(=SerialBT1)\n}\n\n/*****************************************************************************\n** Receive data from RC100\n*****************************************************************************/\nvoid receiveDataFromRC100(Stewart* stewart)\n{\n  if (!stewart->getReceiveDataFlag())\n  {\n    if (rc100.available())\n    {\n      stewart->setReceiveDataFlag(true);\n\n      uint16_t data = rc100.readData();\n\n      // Task space control tab \n      if (data & RC100_BTN_U) \n        stewart->makeTaskTrajectory(\"tool\", math::vector3(0.020, 0.0, 0.0), 1.0);\n      else if (data & RC100_BTN_L) \n        stewart->makeTaskTrajectory(\"tool\", math::vector3(-0.020, 0.0, 0.0), 1.0);\n      else if (data & RC100_BTN_D)\n        stewart->makeTaskTrajectory(\"tool\", math::vector3(0.0, 0.020, 0.0), 1.0);\n      else if (data & RC100_BTN_R) \n        stewart->makeTaskTrajectory(\"tool\", math::vector3(0.0, -0.020, 0.0), 1.0);\n      else if (data & RC100_BTN_1)\n        stewart->makeTaskTrajectory(\"tool\", math::vector3(0.0, 0.0, 0.015), 1.0);\n      else if (data & RC100_BTN_2)\n        stewart->makeTaskTrajectory(\"tool\", math::vector3(0.0, 0.0, -0.015), 1.0);\n      else if (data & RC100_BTN_3)\n        startDemo();      \n      else if (data & RC100_BTN_4)\n        stopDemo(stewart);\n      else if (data & RC100_BTN_5) {}\n      else if (data & RC100_BTN_6)\n      {\n        std::vector<double> goal_position;\n        goal_position.push_back(0.0);\n        goal_position.push_back(0.0);\n        goal_position.push_back(0.0);\n        goal_position.push_back(0.0);\n        goal_position.push_back(0.0);\n        goal_position.push_back(0.0);\n        stewart->makeJointTrajectory(goal_position, 0.5);        \n      }\n      \n//----------------------------------------------//\n//         DO NOT MODIFY THE BELOW CODE         //\n//----------------------------------------------//\n      stewart->setReceiveDataFlag(true);\n      stewart->setPrevReceiveTime(millis()/1000.0);\n    }\n  }\n  else \n  {\n    if (millis()/1000.0 - stewart->getPrevReceiveTime() >= RECEIVE_RATE)\n    {\n      stewart->setReceiveDataFlag(false);   \n      initRC100();\n    }\n  }\n}\n\n#endif // REMOTECONTROLLER100_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/library.properties",
    "content": "name=OpenManipulator\nversion=0.2.0\nauthor=Darby Lim (thlim@robotis.com), Hye-Jong KIM (hjkim@robotis.com), Ryan Shim (jhshim@robotis.com), Yong-Ho Na (yhna@robotis.com)\nmaintainer=Pyo(pyo@robotis.com), Baram(chc@robotis.com)\nsentence=Kinematics and Dynamics library and example of OpenManipulator\nparagraph=\ncategory=Data Processing\nurl=https://github.com/ROBOTIS-GIT/OpenCR\narchitectures=OpenCR\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/delta_libs/include/delta_libs/delta.h",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef DELTA_H_\n#define DELTA_H_\n\n#include \"delta_custom_trajectory.h\"\n#include \"delta_dynamixel.h\"\n#include \"delta_kinematics.h\"\n\n#define CUSTOM_TRAJECTORY_SIZE 4\n#define CUSTOM_TRAJECTORY_LINE    \"custom_trajectory_line\"\n#define CUSTOM_TRAJECTORY_CIRCLE  \"custom_trajectory_circle\"\n#define CUSTOM_TRAJECTORY_RHOMBUS \"custom_trajectory_rhombus\"\n#define CUSTOM_TRAJECTORY_HEART   \"custom_trajectory_heart\"\n\n#define DXL_SIZE 3\n#define JOINT_DYNAMIXEL \"joint_dxl\"\n\n#define RECEIVE_RATE 0.100 // unit: s\n#define CONTROL_RATE 0.010 // unit: s\n\n#define X_AXIS robotis_manipulator::math::vector3(1.0, 0.0, 0.0)\n#define Y_AXIS robotis_manipulator::math::vector3(0.0, 1.0, 0.0)\n#define Z_AXIS robotis_manipulator::math::vector3(0.0, 0.0, 1.0)\n\nclass Delta : public robotis_manipulator::RobotisManipulator\n{\nprivate:\n  robotis_manipulator::Kinematics *kinematics_;\n  robotis_manipulator::JointActuator *joint_;\n  robotis_manipulator::ToolActuator *tool_;\n  robotis_manipulator::CustomTaskTrajectory *custom_trajectory_[CUSTOM_TRAJECTORY_SIZE];\n\n  bool using_actual_robot_state_;\n  bool receive_data_flag_ = false;\n  double prev_receive_time_ = 0.0;\n  double prev_control_time_ = 0.0;\n\npublic:\n  Delta();\n  virtual ~Delta();\n\n  void initDebug();\n  void initOpenManipulator(bool using_actual_robot_state, \n                           STRING usb_port = \"/dev/ttyUSB0\", \n                           STRING baud_rate = \"1000000\", \n                           float control_rate = CONTROL_RATE);\n  void processOpenManipulator(double present_time);\n\n  bool getUsingActualRobotState();\n  bool getReceiveDataFlag();\n  double getPrevReceiveTime();\n\n  void setReceiveDataFlag(bool receive_data_flag);\n  void setPrevReceiveTime(double prev_receive_time);\n};\n\n#endif // Delta_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/delta_libs/include/delta_libs/delta_custom_trajectory.h",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef SCARA_CUSTOM_TRAJECTORY_H_\n#define SCARA_CUSTOM_TRAJECTORY_H_\n\n#if defined(__OPENCR__)\n  #include <RobotisManipulator.h>\n#else\n  #include <robotis_manipulator/robotis_manipulator.h>\n#endif\n\nusing namespace robotis_manipulator;\nusing namespace Eigen;\n\nnamespace delta_custom_trajectory\n{\n  \nenum AXIS{\n\tX_AXIS,\n\tY_AXIS,\n\tZ_AXIS,\n};\n\n/*****************************************************************************\n** Line\n*****************************************************************************/\nclass Line : public robotis_manipulator::CustomTaskTrajectory\n{\nprivate:\n  TaskWaypoint start_pose_;\n  TaskWaypoint goal_pose_;\n\n  double acc_dec_time_;\n  double move_time_;\n  std::vector<double> vel_max_;\n\npublic:\n\tLine() {}\n\tvirtual ~Line() {}\n\n  void initLine(double move_time, TaskWaypoint start, TaskWaypoint delta);\n  TaskWaypoint drawLine(double time_var);\n\n  virtual void setOption(const void *arg);\n  virtual void makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg);\n  virtual TaskWaypoint getTaskWaypoint(double tick);\n};\n\n\n/*****************************************************************************\n** Circle\n*****************************************************************************/\nclass Circle : public robotis_manipulator::CustomTaskTrajectory\n{\nprivate:\n  robotis_manipulator::MinimumJerk path_generator_;\n  VectorXd coefficient_;\n\n  TaskWaypoint start_pose_;\n  TaskWaypoint goal_pose_;\n\n  double radius_;\n  double start_angular_position_;\n  double revolution_;\n\npublic:\n\tCircle() {}\n\tvirtual ~Circle() {}\n\n  void initCircle(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position);\n  TaskWaypoint drawCircle(double time_var);\n\n  virtual void setOption(const void *arg);\n  virtual void makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg);\n  virtual TaskWaypoint getTaskWaypoint(double tick);\n};\n\n\n/*****************************************************************************\n** Rhombus\n*****************************************************************************/\nclass Rhombus : public robotis_manipulator::CustomTaskTrajectory\n{\nprivate:\n  robotis_manipulator::MinimumJerk path_generator_;\n  VectorXd coefficient_;\n\n  TaskWaypoint start_pose_;\n  TaskWaypoint goal_pose_;\n\n  double radius_;\n  double start_angular_position_;\n  double revolution_;\n\npublic:\n\tRhombus() {}\n\tvirtual ~Rhombus() {}\n\n  void initRhombus(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position);\n  TaskWaypoint drawRhombus(double time_var);\n\n  virtual void setOption(const void *arg);\n  virtual void makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg);\n  virtual TaskWaypoint getTaskWaypoint(double tick);\n};\n\n\n/*****************************************************************************\n** Heart\n*****************************************************************************/\nclass Heart : public robotis_manipulator::CustomTaskTrajectory\n{\nprivate:\n  robotis_manipulator::MinimumJerk path_generator_;\n  VectorXd coefficient_;\n\n  TaskWaypoint start_pose_;\n  TaskWaypoint goal_pose_;\n\n  double radius_;\n  double start_angular_position_;\n  double revolution_;\n\npublic:\n\tHeart() {}\n\tvirtual ~Heart() {}\n\n  void initHeart(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position);\n  TaskWaypoint drawHeart(double tick);\n\n  virtual void setOption(const void *arg);\n  virtual void makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg);\n  virtual TaskWaypoint getTaskWaypoint(double tick);\n};\n\n\n} // namespace delta_custom_trajectory\n#endif // DELTA_CUSTOM_TRAJECTORY_H_\n\n\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/delta_libs/include/delta_libs/delta_dynamixel.h",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef DELTA_DYNAMIXEL_H_\n#define DELTA_DYNAMIXEL_H_\n\n#if defined(__OPENCR__)\n  #include <RobotisManipulator.h>\n  #include <DynamixelWorkbench.h>\n#else\n  #include <robotis_manipulator/robotis_manipulator.h>\n  #include <dynamixel_workbench_toolbox/dynamixel_workbench.h>\n#endif\n\nnamespace delta_dynamixel\n{\n\n#define SYNC_WRITE_HANDLER 0\n#define SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT 0\n\n//#define CONTROL_LOOP_TIME 10;    //ms\n\n// Protocol 2.0\n#define ADDR_PRESENT_CURRENT_2 126\n#define ADDR_PRESENT_VELOCITY_2 128\n#define ADDR_PRESENT_POSITION_2 132\n#define ADDR_VELOCITY_TRAJECTORY_2 136\n#define ADDR_POSITION_TRAJECTORY_2 140\n#define ADDR_PROFILE_ACCELERATION_2 108\n#define ADDR_PROFILE_VELOCITY_2 112\n#define ADDR_GOAL_POSITION_2 116\n\n\n#define LENGTH_PRESENT_CURRENT_2 2\n#define LENGTH_PRESENT_VELOCITY_2 4\n#define LENGTH_PRESENT_POSITION_2 4\n#define LENGTH_VELOCITY_TRAJECTORY_2 4\n#define LENGTH_POSITION_TRAJECTORY_2 4\n#define LENGTH_PROFILE_ACCELERATION_2 4\n#define LENGTH_PROFILE_VELOCITY_2 4\n#define LENGTH_GOAL_POSITION_2 4\n\n\n// Protocol 1.0\n#define ADDR_PRESENT_CURRENT_1 = 40;\n#define ADDR_PRESENT_VELOCITY_1 = 38;\n#define ADDR_PRESENT_POSITION_1 = 36;\n\n#define LENGTH_PRESENT_CURRENT_1 = 2;\n#define LENGTH_PRESENT_VELOCITY_1 = 2;\n#define LENGTH_PRESENT_POSITION_1 = 2;\n\ntypedef struct\n{\n  std::vector<uint8_t> id;\n  uint8_t num;\n} Joint;\n\nclass JointDynamixel : public robotis_manipulator::JointActuator\n{\nprivate:\n  DynamixelWorkbench *dynamixel_workbench_;\n  Joint dynamixel_;\n\npublic:\n  JointDynamixel(){}\n  virtual ~JointDynamixel(){}\n\n\n  /*****************************************************************************\n  ** Joint Dynamixel Control Functions\n  *****************************************************************************/\n  virtual void init(std::vector<uint8_t> actuator_id, const void *arg);\n  virtual void setMode(std::vector<uint8_t> actuator_id, const void *arg);\n  virtual std::vector<uint8_t> getId();\n\n  virtual void enable();\n  virtual void disable();\n\n  virtual bool sendJointActuatorValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector);\n  virtual std::vector<robotis_manipulator::ActuatorValue> receiveJointActuatorValue(std::vector<uint8_t> actuator_id);\n\n\n  /*****************************************************************************\n  ** Functions called in Joint Dynamixel Control Functions\n  *****************************************************************************/\n  bool initialize(std::vector<uint8_t> actuator_id, STRING dxl_device_name, STRING dxl_baud_rate);\n  bool setOperatingMode(std::vector<uint8_t> actuator_id, STRING dynamixel_mode = \"position_mode\");\n  bool setSDKHandler(uint8_t actuator_id);\n  bool writeProfileValue(std::vector<uint8_t> actuator_id, STRING profile_mode, uint32_t value);\n  bool writeGoalPosition(std::vector<uint8_t> actuator_id, std::vector<double> radian_vector);\n  std::vector<robotis_manipulator::ActuatorValue> receiveAllDynamixelValue(std::vector<uint8_t> actuator_id);\n};\n\nclass JointDynamixelProfileControl : public robotis_manipulator::JointActuator\n{\nprivate:\n  DynamixelWorkbench *dynamixel_workbench_;\n  Joint dynamixel_;\n  float control_loop_time_; // unit: ms\n  std::map<uint8_t, robotis_manipulator::ActuatorValue> previous_goal_value_;\n\npublic:\n  JointDynamixelProfileControl(float control_loop_time = 0.010);\n  virtual ~JointDynamixelProfileControl(){}\n\n\n  /*****************************************************************************\n  ** Joint Dynamixel Profile Control Functions\n  *****************************************************************************/\n  virtual void init(std::vector<uint8_t> actuator_id, const void *arg);\n  virtual void setMode(std::vector<uint8_t> actuator_id, const void *arg);\n  virtual std::vector<uint8_t> getId();\n\n  virtual void enable();\n  virtual void disable();\n\n  virtual bool sendJointActuatorValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector);\n  virtual std::vector<robotis_manipulator::ActuatorValue> receiveJointActuatorValue(std::vector<uint8_t> actuator_id);\n\n\n  /*****************************************************************************\n  ** Functions called in Joint Dynamixel Profile Control Functions\n  *****************************************************************************/\n  bool initialize(std::vector<uint8_t> actuator_id, STRING dxl_device_name, STRING dxl_baud_rate);\n  bool setOperatingMode(std::vector<uint8_t> actuator_id, STRING dynamixel_mode = \"position_mode\");\n  bool setSDKHandler(uint8_t actuator_id);\n  bool writeProfileValue(std::vector<uint8_t> actuator_id, STRING profile_mode, uint32_t value);\n  bool writeGoalProfilingControlValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector);\n  std::vector<robotis_manipulator::ActuatorValue> receiveAllDynamixelValue(std::vector<uint8_t> actuator_id);\n};\n\nclass ToolDynamixel : public robotis_manipulator::ToolActuator\n{\n private:\n  DynamixelWorkbench *dynamixel_workbench_;\n  Joint dynamixel_;\n\n public:\n  ToolDynamixel() {}\n  virtual ~ToolDynamixel() {}\n\n\n  /*****************************************************************************\n  ** Tool Dynamixel Control Functions\n  *****************************************************************************/\n  virtual void init(uint8_t actuator_id, const void *arg);\n  virtual void setMode(const void *arg);\n  virtual uint8_t getId();\n\n  virtual void enable();\n  virtual void disable();\n\n  virtual bool sendToolActuatorValue(robotis_manipulator::ActuatorValue value);\n  virtual robotis_manipulator::ActuatorValue receiveToolActuatorValue();\n\n\n  /*****************************************************************************\n  ** Functions called in Tool Dynamixel Profile Control Functions\n  *****************************************************************************/\n  bool initialize(uint8_t actuator_id, STRING dxl_device_name, STRING dxl_baud_rate);\n  bool setOperatingMode(STRING dynamixel_mode = \"position_mode\");\n  bool writeProfileValue(STRING profile_mode, uint32_t value);\n  bool setSDKHandler();\n  bool writeGoalPosition(double radian);\n  double receiveDynamixelValue();\n};\n\n} // namespace delta_dynamixel\n#endif // DELTA_DYNAMIXEL_H_\n\n\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/delta_libs/include/delta_libs/delta_kinematics.h",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef DELTA_KINEMATICS_H_\n#define DELTA_KINEMATICS_H_\n\n#if defined(__OPENCR__)\n  #include <RobotisManipulator.h>\n#else\n  #include <robotis_manipulator/robotis_manipulator.h>\n#endif\n\nusing namespace Eigen;\nusing namespace robotis_manipulator;\n\nnamespace delta_kinematics\n{\n\n/*****************************************************************************\n** Kinematics Solver Using Geometry\n*****************************************************************************/\nclass SolverUsingGeometry : public robotis_manipulator::Kinematics\n{\nprivate:\n  bool inverseKinematicsSolverUsingGeometry(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue>* goal_joint_value);\n\npublic:\n  SolverUsingGeometry() {}\n  virtual ~SolverUsingGeometry() {}\n\n  virtual void setOption(const void *arg);\n  virtual MatrixXd jacobian(Manipulator *manipulator, Name tool_name);\n  virtual void solveForwardKinematics(Manipulator *manipulator);\n  virtual bool solveInverseKinematics(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue>* goal_joint_value);\n};\n\n} // namespace delta_kinematics\n\n#endif // DELTA_KINEMATICS_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/delta_libs/src/delta.cpp",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include \"../include/delta_libs/delta.h\"\n\nDelta::Delta() {}\nDelta::~Delta()\n{\n  delete kinematics_;\n  delete joint_;\n  delete tool_;\n  for(uint8_t index = 0; index < CUSTOM_TRAJECTORY_SIZE; index++)\n    delete custom_trajectory_[index];\n}\n\nvoid Delta::initDebug()\n{\n  DEBUG.begin(57600); // Using Serial4(=SerialBT2)\n  log::print(\"OpenManipulator Debugging Port\"); \n}\n\nvoid Delta::initOpenManipulator(bool using_actual_robot_state, STRING usb_port, STRING baud_rate, float control_rate)\n{\n  /*****************************************************************************\n  ** Set if using actual robot\n  *****************************************************************************/\n  using_actual_robot_state_ = using_actual_robot_state;\n  \n  /*****************************************************************************\n  ** Initialize Manipulator Parameters\n  *****************************************************************************/\n  addWorld(\"world\",   // world name\n           \"joint1\"); // child name\n\n  addJoint(\"joint1\",  // my name\n           \"world\",   // parent name\n           \"joint4\",  // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Z_AXIS,    // axis of rotation\n           1);        // actuator id\n\n  addJoint(\"joint2\",  // my name\n           \"world\",   // parent name\n           \"joint5\",  // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // relative orientation\n           Z_AXIS,    // axis of rotation\n           2);        // actuator id\n\n  addJoint(\"joint3\",  // my name\n           \"world\",   // parent name\n           \"joint6\",  // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Z_AXIS,    // axis of rotation\n           3);        // actuator id\n\n  addJoint(\"joint4\",  // my name\n           \"joint1\",  // parent name\n           \"joint7\",  // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Z_AXIS,    // axis of rotation\n           -1);       // actuator id\n\n  addJoint(\"joint4_2\",  // my name\n           \"joint1\",  // parent name\n           \"joint7\",  // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Z_AXIS,    // axis of rotation\n           -1);       // actuator id\n\n  addJoint(\"joint5\",  // my name\n           \"joint2\",  // parent name\n           \"joint8\",  // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Z_AXIS,    // axis of rotation\n           -1);       // actuator id\n\n  addJoint(\"joint5_2\",  // my name\n           \"joint2\",  // parent name\n           \"joint8\",  // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Z_AXIS,    // axis of rotation\n           -1);       // actuator id\n\n  addJoint(\"joint6\",  // my name\n           \"joint3\",   // parent name\n           \"joint9\",  // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Z_AXIS,    // axis of rotation\n           -1);        // actuator id\n\n  addJoint(\"joint6_2\",  // my name\n           \"joint3\",   // parent name\n           \"joint9\",  // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Z_AXIS,    // axis of rotation\n           -1);        // actuator id\n\n  addJoint(\"joint7\",  // my name\n           \"joint4\",   // parent name\n           \"tool\",  // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Z_AXIS,    // axis of rotation\n           -1);        // actuator id\n\n  addJoint(\"joint7_2\",  // my name\n           \"joint4\",   // parent name\n           \"tool\",  // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Z_AXIS,    // axis of rotation\n           -1);        // actuator id\n\n  addTool(\"tool\",     // my name\n          \"joint7\",   // Not used\n          math::vector3(0.0, 0.0, 0.0),                    // Not used\n          math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n          -1);        // actuator id\n\n  /*****************************************************************************\n  ** Initialize Kinematics \n  *****************************************************************************/\n  kinematics_ = new delta_kinematics::SolverUsingGeometry();\n  addKinematics(kinematics_);\n\n  /*****************************************************************************\n  ** Initialize Custom Trajectory\n  *****************************************************************************/\n  custom_trajectory_[0] = new delta_custom_trajectory::Line();\n  custom_trajectory_[1] = new delta_custom_trajectory::Circle();\n  custom_trajectory_[2] = new delta_custom_trajectory::Rhombus();\n  custom_trajectory_[3] = new delta_custom_trajectory::Heart();\n\n  addCustomTrajectory(CUSTOM_TRAJECTORY_LINE, custom_trajectory_[0]);\n  addCustomTrajectory(CUSTOM_TRAJECTORY_CIRCLE, custom_trajectory_[1]);\n  addCustomTrajectory(CUSTOM_TRAJECTORY_RHOMBUS, custom_trajectory_[2]);\n  addCustomTrajectory(CUSTOM_TRAJECTORY_HEART, custom_trajectory_[3]);\n\n  if (using_actual_robot_state_)\n  {\n    /*****************************************************************************\n    ** Initialize Joint Actuator\n    *****************************************************************************/\n    joint_ = new delta_dynamixel::JointDynamixelProfileControl(control_rate);\n\n    // Set communication arguments\n    STRING dxl_comm_arg[2] = {usb_port, baud_rate};\n    void *p_dxl_comm_arg = &dxl_comm_arg;\n\n    // Set joint actuator id\n    std::vector<uint8_t> jointDxlId;\n    jointDxlId.push_back(1);\n    jointDxlId.push_back(2);\n    jointDxlId.push_back(3);\n    addJointActuator(JOINT_DYNAMIXEL, joint_, jointDxlId, p_dxl_comm_arg);\n\n    // Set joint actuator control mode\n    STRING joint_dxl_mode_arg = \"position_mode\";\n    void *p_joint_dxl_mode_arg = &joint_dxl_mode_arg;\n    setJointActuatorMode(JOINT_DYNAMIXEL, jointDxlId, p_joint_dxl_mode_arg);\n\n    /*****************************************************************************\n    ** Enable actuators and Receive actuator values \n    *****************************************************************************/\n    // Enable All Actuators\n    enableAllActuator();\n\n    // Receive current angles from all actuators \n    receiveAllJointActuatorValue();\n  }\n}\n\n/*****************************************************************************\n** Process actuator values received from external controllers\n*****************************************************************************/\nvoid Delta::processOpenManipulator(double present_time)\n{\n  if (present_time - prev_control_time_ >= CONTROL_RATE)\n  {\n    JointWaypoint goal_joint_value = getJointGoalValueFromTrajectory(present_time);\n    if(goal_joint_value.size() != 0) sendAllJointActuatorValue(goal_joint_value);\n\n    // Set previous control time\n    prev_control_time_ = millis()/1000.0;\n  }\n}\n\n/*****************************************************************************\n** State Functions\n*****************************************************************************/\n// Check if using acutal robot \nbool Delta::getUsingActualRobotState() \n{\n  return using_actual_robot_state_;\n}\n\n/* Check if the program read data within control rate) */\nbool Delta::getReceiveDataFlag()  \n{\n  return receive_data_flag_;\n}\n\n/* Get the previous time when data were received */\ndouble Delta::getPrevReceiveTime() \n{\n  return prev_receive_time_;\n}\n\n/* Set whether data were received or not */\nvoid Delta::setReceiveDataFlag(bool receive_data_flag) \n{\n  receive_data_flag_ = receive_data_flag;\n}\n\n/* Set the previous time when data were received */\nvoid Delta::setPrevReceiveTime(double prev_receive_time)  \n{\n  prev_receive_time_ = prev_receive_time;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/delta_libs/src/delta_custom_trajectory.cpp",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include \"../include/delta_libs/delta_custom_trajectory.h\"\n\nusing namespace delta_custom_trajectory;\nusing namespace Eigen;\n\n\n/*****************************************************************************\n** Line\n*****************************************************************************/\nvoid Line::initLine(double move_time, TaskWaypoint start, TaskWaypoint delta)\n{\n  move_time_ = move_time;\n  acc_dec_time_ = move_time_ * 0.2;\n  vel_max_.resize(3);\n\n  TaskWaypoint start_to_goal;\n\n  start_pose_ = start;\n\n  goal_pose_ .kinematic.orientation = start_pose_.kinematic.orientation;\n  goal_pose_ .kinematic.position = start.kinematic.position + delta.kinematic.position;\n\n  vel_max_.at(X_AXIS) = delta.kinematic.position(X_AXIS)/(move_time_ - acc_dec_time_);\n  vel_max_.at(Y_AXIS) = delta.kinematic.position(Y_AXIS)/(move_time_ - acc_dec_time_);\n  vel_max_.at(Z_AXIS) = delta.kinematic.position(Z_AXIS)/(move_time_ - acc_dec_time_);\n}\n\nTaskWaypoint Line::drawLine(double time_var)\n{\n  TaskWaypoint pose;\n\n  if(acc_dec_time_ >= time_var)\n  {\n    pose.kinematic.position(X_AXIS) = 0.5*vel_max_.at(X_AXIS)*pow(time_var, 2)/acc_dec_time_ + start_pose_.kinematic.position(X_AXIS);\n    pose.kinematic.position(Y_AXIS) = 0.5*vel_max_.at(Y_AXIS)*pow(time_var, 2)/acc_dec_time_ + start_pose_.kinematic.position(Y_AXIS);\n    pose.kinematic.position(Z_AXIS) = 0.5*vel_max_.at(Z_AXIS)*pow(time_var, 2)/acc_dec_time_ + start_pose_.kinematic.position(Z_AXIS);\n  }\n  else if(time_var > acc_dec_time_ && (move_time_ - acc_dec_time_) >= time_var )\n  {\n    pose.kinematic.position(X_AXIS) = vel_max_.at(X_AXIS)*(time_var-(acc_dec_time_*0.5)) + start_pose_.kinematic.position(X_AXIS);\n    pose.kinematic.position(Y_AXIS) = vel_max_.at(Y_AXIS)*(time_var-(acc_dec_time_*0.5)) + start_pose_.kinematic.position(Y_AXIS);\n    pose.kinematic.position(Z_AXIS) = vel_max_.at(Z_AXIS)*(time_var-(acc_dec_time_*0.5)) + start_pose_.kinematic.position(Z_AXIS);\n  }\n  else if(time_var > (move_time_ - acc_dec_time_) && (time_var < move_time_))\n  {\n    pose.kinematic.position(X_AXIS) = goal_pose_.kinematic.position(X_AXIS) - vel_max_.at(X_AXIS)*0.5/acc_dec_time_*(pow((move_time_-time_var),2));\n    pose.kinematic.position(Y_AXIS) = goal_pose_.kinematic.position(Y_AXIS) - vel_max_.at(Y_AXIS)*0.5/acc_dec_time_*(pow((move_time_-time_var),2));\n    pose.kinematic.position(Z_AXIS) = goal_pose_.kinematic.position(Z_AXIS) - vel_max_.at(Z_AXIS)*0.5/acc_dec_time_*(pow((move_time_-time_var),2));\n  }\n  else if(time_var <= move_time_)\n  {\n    pose.kinematic.position(X_AXIS) = goal_pose_.kinematic.position(X_AXIS);\n    pose.kinematic.position(Y_AXIS) = goal_pose_.kinematic.position(Y_AXIS);\n    pose.kinematic.position(Z_AXIS) = goal_pose_.kinematic.position(Z_AXIS);\n  }\n\n  pose.kinematic.orientation = start_pose_.kinematic.orientation;\n  pose.dynamic.linear.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.linear.acceleration = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.acceleration = Eigen::Vector3d::Zero(3);\n\n  return pose;\n}\n\nTaskWaypoint Line::getTaskWaypoint(double tick)\n{\n  return drawLine(tick);\n}\n\n\nvoid Line::makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg)\n{\n  TaskWaypoint *c_arg = (TaskWaypoint *)arg;\n  initLine(move_time, start, c_arg[0]);\n}\nvoid Line::setOption(const void *arg) {}\n\n\n/*****************************************************************************\n** Circle\n*****************************************************************************/\nvoid Circle::initCircle(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position)\n{\n  start_pose_ = start;\n\n  radius_ = radius;\n  revolution_ = revolution;\n  start_angular_position_ = start_angular_position;\n\n  Point drawingStart, drawingGoal;\n\n  drawingStart.position = 0.0;\n  drawingStart.velocity = 0.0;\n  drawingStart.acceleration = 0.0;\n  drawingStart.effort = 0.0;\n\n  drawingGoal.position = revolution_ * 2*M_PI;\n  drawingGoal.velocity = 0.0;\n  drawingGoal.acceleration = 0.0;\n  drawingGoal.effort = 0.0;\n\n  path_generator_.calcCoefficient(drawingStart, drawingGoal, move_time);\n  coefficient_ = path_generator_.getCoefficient();\n}\n\nTaskWaypoint Circle::drawCircle(double tick)\n{\n  // get time variable\n  double get_time_var = 0.0;\n\n  get_time_var = coefficient_(0) +\n                 coefficient_(1) * pow(tick, 1) +\n                 coefficient_(2) * pow(tick, 2) +\n                 coefficient_(3) * pow(tick, 3) +\n                 coefficient_(4) * pow(tick, 4) +\n                 coefficient_(5) * pow(tick, 5);\n\n  // set drawing trajectory\n  TaskWaypoint pose;\n\n  double diff_pose[2];\n\n  diff_pose[0] = (cos(get_time_var)-1)*cos(start_angular_position_) - sin(get_time_var)*sin(start_angular_position_);\n  diff_pose[1] = (cos(get_time_var)-1)*sin(start_angular_position_) + sin(get_time_var)*cos(start_angular_position_);\n\n  pose.kinematic.position(X_AXIS) = start_pose_.kinematic.position(X_AXIS) + radius_ * diff_pose[0];\n  pose.kinematic.position(Y_AXIS) = start_pose_.kinematic.position(Y_AXIS) + radius_ * diff_pose[1];\n  pose.kinematic.position(Z_AXIS) = start_pose_.kinematic.position(Z_AXIS);\n\n  pose.kinematic.orientation = start_pose_.kinematic.orientation;\n\n  pose.dynamic.linear.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.linear.acceleration = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.acceleration = Eigen::Vector3d::Zero(3);\n\n  return pose;\n}\n\nTaskWaypoint Circle::getTaskWaypoint(double tick)\n{\n  return drawCircle(tick);\n}\n\nvoid Circle::makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg)\n{\n  double *get_arg_ = (double *)arg;\n  initCircle(move_time, start, get_arg_[0], get_arg_[1], get_arg_[2]);\n}\n\nvoid Circle::setOption(const void *arg){}\n\n\n/*****************************************************************************\n** Rhombus\n*****************************************************************************/\nvoid Rhombus::initRhombus(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position)\n{\n  start_pose_ = start;\n\n  radius_ = radius;\n  revolution_ = revolution;\n  start_angular_position_ = start_angular_position;\n\n  Point drawingStart, drawingGoal;\n\n  drawingStart.position = 0.0;\n  drawingStart.velocity = 0.0;\n  drawingStart.acceleration = 0.0;\n  drawingStart.effort = 0.0;\n\n  drawingGoal.position = revolution_ * 2*M_PI;\n  drawingGoal.velocity = 0.0;\n  drawingGoal.acceleration = 0.0;\n  drawingGoal.effort = 0.0;\n\n  path_generator_.calcCoefficient(drawingStart, drawingGoal, move_time);\n  coefficient_ = path_generator_.getCoefficient();\n}\n\n\nTaskWaypoint Rhombus::drawRhombus(double tick)\n{\n  // get time variable\n  double get_time_var = 0.0;\n\n  get_time_var = coefficient_(0) +\n                 coefficient_(1) * pow(tick, 1) +\n                 coefficient_(2) * pow(tick, 2) +\n                 coefficient_(3) * pow(tick, 3) +\n                 coefficient_(4) * pow(tick, 4) +\n                 coefficient_(5) * pow(tick, 5); \n\n  // set drawing trajectory\n  TaskWaypoint pose;\n  double diff_pose[2];\n  double traj[2];\n\n  while(true)\n  {\n    if (get_time_var < PI*2) break;\n    get_time_var = get_time_var - PI*2;\n  }\n\n  if (get_time_var >= 0 && get_time_var < PI/2){\n    traj[0] = - get_time_var / (PI/2);\n    traj[1] = - get_time_var / (PI/2);\n  } else if (get_time_var >= PI/2 && get_time_var < PI){\n    traj[0] = - get_time_var / (PI/2);\n    traj[1] = get_time_var / (PI/2) - 2;\n  } else if (get_time_var >= PI && get_time_var < PI*3/2){\n    traj[0] = get_time_var / (PI/2) - 4;\n    traj[1] = get_time_var / (PI/2) - 2;\n  } else {\n    traj[0] = get_time_var / (PI/2) - 4;\n    traj[1] = - get_time_var / (PI/2) + 4;\n  }\n  \n\n  diff_pose[0] = traj[0]*cos(start_angular_position_) - traj[1]*sin(start_angular_position_);\n  diff_pose[1] = traj[0]*sin(start_angular_position_) + traj[1]*cos(start_angular_position_);\n\n  pose.kinematic.position(X_AXIS) = start_pose_.kinematic.position(X_AXIS) + radius_ * diff_pose[0];\n  pose.kinematic.position(Y_AXIS) = start_pose_.kinematic.position(Y_AXIS) + radius_ * diff_pose[1];\n  pose.kinematic.position(Z_AXIS) = start_pose_.kinematic.position(Z_AXIS);\n\n  pose.kinematic.orientation = start_pose_.kinematic.orientation;\n\n  pose.dynamic.linear.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.linear.acceleration = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.acceleration = Eigen::Vector3d::Zero(3);\n\n  return pose;\n}\n\n\nvoid Rhombus::makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg)\n{\n  double *get_arg_ = (double *)arg;\n  initRhombus(move_time, start, get_arg_[0], get_arg_[1], get_arg_[2]);\n}\n\nTaskWaypoint Rhombus::getTaskWaypoint(double tick)\n{\n  return drawRhombus(tick);\n}\nvoid Rhombus::setOption(const void *arg){}\n\n\n/*****************************************************************************\n** Heart\n*****************************************************************************/\nvoid Heart::initHeart(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position)\n{\n  start_pose_ = start;\n\n  radius_ = radius;\n  revolution_ = revolution;\n  start_angular_position_ = start_angular_position;\n\n  Point drawingStart, drawingGoal;\n\n  drawingStart.position = 0.0;\n  drawingStart.velocity = 0.0;\n  drawingStart.acceleration = 0.0;\n  drawingStart.effort = 0.0;\n\n  drawingGoal.position = revolution_ * 2*M_PI;\n  drawingGoal.velocity = 0.0;\n  drawingGoal.acceleration = 0.0;\n  drawingGoal.effort = 0.0;\n\n  path_generator_.calcCoefficient(drawingStart, drawingGoal, move_time);\n  coefficient_ = path_generator_.getCoefficient();\n}\n\nTaskWaypoint Heart::drawHeart(double tick)\n{\n  // get time variable\n  double get_time_var = 0.0;\n\n  get_time_var = coefficient_(0) +\n                 coefficient_(1) * pow(tick, 1) +\n                 coefficient_(2) * pow(tick, 2) +\n                 coefficient_(3) * pow(tick, 3) +\n                 coefficient_(4) * pow(tick, 4) +\n                 coefficient_(5) * pow(tick, 5);\n\n  // set drawing trajectory\n  TaskWaypoint pose;\n  double diff_pose[2];\n  double traj[2];\n\n\tdouble shift_offset = - 5.0;\n\n  traj[0] = (shift_offset + (13*cos(get_time_var) - 5*cos(2*get_time_var) - 2*cos(3*get_time_var) - cos(4*get_time_var))) / 16;\n  traj[1] = (16*sin(get_time_var)*sin(get_time_var)*sin(get_time_var)) / 16;\n\n  diff_pose[0] = traj[0]*cos(start_angular_position_) - traj[1]*sin(start_angular_position_);\n  diff_pose[1] = traj[0]*sin(start_angular_position_) + traj[1]*cos(start_angular_position_);\n\n  pose.kinematic.position(X_AXIS) = start_pose_.kinematic.position(X_AXIS) + radius_ * diff_pose[0];\n  pose.kinematic.position(Y_AXIS) = start_pose_.kinematic.position(Y_AXIS) + radius_ * diff_pose[1];\n  pose.kinematic.position(Z_AXIS) = start_pose_.kinematic.position(Z_AXIS);\n\n  pose.kinematic.orientation = start_pose_.kinematic.orientation;\n\n  pose.dynamic.linear.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.linear.acceleration = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.acceleration = Eigen::Vector3d::Zero(3);\n\n  return pose;\n}\n\nvoid Heart::makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg)\n{\n  double *get_arg_ = (double *)arg;\n  initHeart(move_time, start, get_arg_[0], get_arg_[1], get_arg_[2]);\n}\nvoid Heart::setOption(const void *arg){}\n\nTaskWaypoint Heart::getTaskWaypoint(double tick)\n{\n  return drawHeart(tick);\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/delta_libs/src/delta_dynamixel.cpp",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include \"../include/delta_libs/delta_dynamixel.h\"\n\nusing namespace delta_dynamixel;\nusing namespace robotis_manipulator;\n\n/*****************************************************************************\n** Joint Dynamixel Control Functions\n*****************************************************************************/\nvoid JointDynamixel::init(std::vector<uint8_t> actuator_id, const void *arg)\n{\n  STRING *get_arg_ = (STRING *)arg;\n\n  bool result = JointDynamixel::initialize(actuator_id ,get_arg_[0], get_arg_[1]);\n\n  if (result == false)\n    return;\n}\n\nvoid JointDynamixel::setMode(std::vector<uint8_t> actuator_id, const void *arg)\n{\n  bool result = false;\n  // const char* log = NULL;\n\n  STRING *get_arg_ = (STRING *)arg;\n\n  if (get_arg_[0] == \"position_mode\" || get_arg_[0] == \"current_based_position_mode\")\n  {\n    result = JointDynamixel::setOperatingMode(actuator_id, get_arg_[0]);\n    if (result == false)\n      return;\n\n    result = JointDynamixel::setSDKHandler(actuator_id.at(0));\n    if (result == false)\n      return;\n  }\n  else\n  {\n    result = JointDynamixel::writeProfileValue(actuator_id, get_arg_[0], std::atoi(get_arg_[1].c_str()));\n    if (result == false)\n      return;\n  }\n  return;\n}\n\nstd::vector<uint8_t> JointDynamixel::getId()\n{\n  return dynamixel_.id;\n}\n\nvoid JointDynamixel::enable()\n{\n  const char* log = NULL;\n  bool result = false;\n  \n  for (uint32_t index = 0; index < dynamixel_.num; index++)\n  {\n    result = dynamixel_workbench_->torqueOn(dynamixel_.id.at(index), &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  enabled_state_ = true;\n}\n\nvoid JointDynamixel::disable()\n{\n  const char* log = NULL;\n  bool result = false;\n  \n  for (uint32_t index = 0; index < dynamixel_.num; index++)\n  {\n    result = dynamixel_workbench_->torqueOff(dynamixel_.id.at(index), &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  enabled_state_ = false;\n}\n\nbool JointDynamixel::sendJointActuatorValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector)\n{\n  bool result = false;\n\n  std::vector<double> radian_vector;\n  for(uint32_t index = 0; index < value_vector.size(); index++)\n  {\n    radian_vector.push_back(value_vector.at(index).position);\n  }\n  result = JointDynamixel::writeGoalPosition(actuator_id, radian_vector);\n  if (result == false)\n    return false;\n\n  return true;\n}\n\nstd::vector<robotis_manipulator::ActuatorValue> JointDynamixel::receiveJointActuatorValue(std::vector<uint8_t> actuator_id)\n{\n  return JointDynamixel::receiveAllDynamixelValue(actuator_id);\n}\n\n\n/*****************************************************************************\n** Functions called in Joint Dynamixel Control Functions\n*****************************************************************************/\nbool JointDynamixel::initialize(std::vector<uint8_t> actuator_id, STRING dxl_device_name, STRING dxl_baud_rate)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  STRING return_delay_time_st = \"Return_Delay_Time\";\n  const char * return_delay_time_char = return_delay_time_st.c_str();\n\n  dynamixel_.id = actuator_id;\n  dynamixel_.num = actuator_id.size();\n\n  dynamixel_workbench_ = new DynamixelWorkbench;\n\n  result = dynamixel_workbench_->init(dxl_device_name.c_str(), std::atoi(dxl_baud_rate.c_str()), &log);\n  if (result == false)\n  {\n    log::error(log);\n  }    \n\n  uint16_t get_model_number;\n  for (uint8_t index = 0; index < dynamixel_.num; index++)\n  {\n    uint8_t id = dynamixel_.id.at(index);\n    result = dynamixel_workbench_->ping(id, &get_model_number, &log);\n\n    if (result == false)\n    {\n      log::error(log);\n      log::error(\"Please check your Dynamixel ID\");\n    }\n    else\n    {\n      char str[100];\n      sprintf(str, \"Joint Dynamixel ID : %d, Model Name : %s\", id, dynamixel_workbench_->getModelName(id));\n      log::println(str);\n\n      result = dynamixel_workbench_->setVelocityBasedProfile(id, &log);\n      if(result == false)\n      {\n        log::error(log);\n        log::error(\"Please check your Dynamixel firmware version (v38~)\");\n      }\n\n      result = dynamixel_workbench_->writeRegister(id, return_delay_time_char, 0, &log);\n      if (result == false)\n      {\n        log::error(log);\n        log::error(\"Please check your Dynamixel firmware version\");\n      }\n    }\n  }\n  return true;\n}\n\nbool JointDynamixel::setOperatingMode(std::vector<uint8_t> actuator_id, STRING dynamixel_mode)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const uint32_t velocity = 0;\n  const uint32_t acceleration = 0;\n  const uint32_t current = 0;\n\n  if (dynamixel_mode == \"position_mode\")\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->jointMode(actuator_id.at(num), velocity, acceleration, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n  else if (dynamixel_mode == \"current_based_position_mode\")\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->currentBasedPositionMode(actuator_id.at(num), current, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n  else\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->jointMode(actuator_id.at(num), velocity, acceleration, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n\n  return true;\n}\n\nbool JointDynamixel::setSDKHandler(uint8_t actuator_id)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  result = dynamixel_workbench_->addSyncWriteHandler(actuator_id, \"Goal_Position\", &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->addSyncReadHandler(ADDR_PRESENT_CURRENT_2, \n                                                    (LENGTH_PRESENT_CURRENT_2 + LENGTH_PRESENT_VELOCITY_2 + LENGTH_PRESENT_POSITION_2), \n                                                    &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\nbool JointDynamixel::writeProfileValue(std::vector<uint8_t> actuator_id, STRING profile_mode, uint32_t value)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const char * char_profile_mode = profile_mode.c_str();\n\n  for (uint8_t num = 0; num < actuator_id.size(); num++)\n  {\n    result = dynamixel_workbench_->writeRegister(actuator_id.at(num), char_profile_mode, value, &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n\n  return true;\n}\n\nbool JointDynamixel::writeGoalPosition(std::vector<uint8_t> actuator_id, std::vector<double> radian_vector)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  uint8_t id_array[actuator_id.size()];\n  int32_t goal_position[actuator_id.size()];\n\n  for (uint8_t index = 0; index < actuator_id.size(); index++)\n  {\n    id_array[index] = actuator_id.at(index);\n    goal_position[index] = dynamixel_workbench_->convertRadian2Value(actuator_id.at(index), radian_vector.at(index));\n  }\n\n  result = dynamixel_workbench_->syncWrite(SYNC_WRITE_HANDLER, id_array, actuator_id.size(), goal_position, 1, &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\nstd::vector<robotis_manipulator::ActuatorValue> JointDynamixel::receiveAllDynamixelValue(std::vector<uint8_t> actuator_id)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  std::vector<robotis_manipulator::ActuatorValue> all_actuator;\n\n  uint8_t id_array[actuator_id.size()];\n  for (uint8_t index = 0; index < actuator_id.size(); index++)\n    id_array[index] = actuator_id.at(index);\n\n  int32_t get_current[actuator_id.size()];\n  int32_t get_velocity[actuator_id.size()];\n  int32_t get_position[actuator_id.size()];\n\n  result = dynamixel_workbench_->syncRead(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                          id_array,\n                                          actuator_id.size(),\n                                          &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                id_array,\n                                                actuator_id.size(),\n                                                ADDR_PRESENT_CURRENT_2,\n                                                LENGTH_PRESENT_CURRENT_2,\n                                                get_current,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                 id_array,\n                                                 actuator_id.size(),\n                                                ADDR_PRESENT_VELOCITY_2,\n                                                LENGTH_PRESENT_VELOCITY_2,\n                                                get_velocity,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                 id_array,\n                                                 actuator_id.size(),\n                                                ADDR_PRESENT_POSITION_2,\n                                                LENGTH_PRESENT_POSITION_2,\n                                                get_position,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  for (uint8_t index = 0; index < actuator_id.size(); index++)\n  {\n    robotis_manipulator::ActuatorValue actuator;\n    actuator.effort = dynamixel_workbench_->convertValue2Current(get_current[index]);\n    actuator.velocity = dynamixel_workbench_->convertValue2Velocity(actuator_id.at(index), get_velocity[index]);\n    actuator.position = dynamixel_workbench_->convertValue2Radian(actuator_id.at(index), get_position[index]);\n\n    all_actuator.push_back(actuator);\n  }\n\n  return all_actuator;\n}\n\n\n/*****************************************************************************\n** Joint Dynamixel Profile Control Functions\n*****************************************************************************/\nJointDynamixelProfileControl::JointDynamixelProfileControl(float control_loop_time)\n{\n  control_loop_time_ = control_loop_time;\n}\n\nvoid JointDynamixelProfileControl::init(std::vector<uint8_t> actuator_id, const void *arg)\n{\n  STRING *get_arg_ = (STRING *)arg;\n\n  bool result = JointDynamixelProfileControl::initialize(actuator_id ,get_arg_[0], get_arg_[1]);\n\n  if (result == false)\n    return;\n}\n\nvoid JointDynamixelProfileControl::setMode(std::vector<uint8_t> actuator_id, const void *arg)\n{\n  bool result = false;\n  // const char* log = NULL;\n\n  STRING *get_arg_ = (STRING *)arg;\n\n  if (get_arg_[0] == \"position_mode\" || get_arg_[0] == \"current_based_position_mode\")\n  {\n    result = JointDynamixelProfileControl::setOperatingMode(actuator_id, get_arg_[0]);\n    if (result == false)\n      return;\n\n    result = JointDynamixelProfileControl::setSDKHandler(actuator_id.at(0));\n    if (result == false)\n      return;\n  }\n  else\n  {\n    result = JointDynamixelProfileControl::writeProfileValue(actuator_id, get_arg_[0], std::atoi(get_arg_[1].c_str()));\n    if (result == false)\n      return;\n  }\n  return;\n}\n\nstd::vector<uint8_t> JointDynamixelProfileControl::getId()\n{\n  return dynamixel_.id;\n}\n\nvoid JointDynamixelProfileControl::enable()\n{\n  const char* log = NULL;\n  bool result = false;\n\n  for (uint32_t index = 0; index < dynamixel_.num; index++)\n  {\n    result = dynamixel_workbench_->torqueOn(dynamixel_.id.at(index), &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  enabled_state_ = true;\n}\n\nvoid JointDynamixelProfileControl::disable()\n{\n  const char* log = NULL;\n  bool result = false;\n\n  for (uint32_t index = 0; index < dynamixel_.num; index++)\n  {\n    result = dynamixel_workbench_->torqueOff(dynamixel_.id.at(index), &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  enabled_state_ = false;\n}\n\nbool JointDynamixelProfileControl::sendJointActuatorValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector)\n{\n  bool result = false;\n\n  result = JointDynamixelProfileControl::writeGoalProfilingControlValue(actuator_id, value_vector);\n  if (result == false)\n    return false;\n\n  return true;\n}\n\nstd::vector<robotis_manipulator::ActuatorValue> JointDynamixelProfileControl::receiveJointActuatorValue(std::vector<uint8_t> actuator_id)\n{\n  return JointDynamixelProfileControl::receiveAllDynamixelValue(actuator_id);\n}\n\n\n/*****************************************************************************\n** Functions called in Joint Dynamixel Profile Control Functions\n*****************************************************************************/\nbool JointDynamixelProfileControl::initialize(std::vector<uint8_t> actuator_id, STRING dxl_device_name, STRING dxl_baud_rate)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  STRING return_delay_time_st = \"Return_Delay_Time\";\n  const char * return_delay_time_char = return_delay_time_st.c_str();\n\n  dynamixel_.id = actuator_id;\n  dynamixel_.num = actuator_id.size();\n\n  dynamixel_workbench_ = new DynamixelWorkbench;\n\n  result = dynamixel_workbench_->init(dxl_device_name.c_str(), std::atoi(dxl_baud_rate.c_str()), &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  uint16_t get_model_number;\n  for (uint8_t index = 0; index < dynamixel_.num; index++)\n  {\n    uint8_t id = dynamixel_.id.at(index);\n    result = dynamixel_workbench_->ping(id, &get_model_number, &log);\n\n    if (result == false)\n    {\n      log::error(log);\n      log::error(\"Please check your Dynamixel ID\");\n    }\n    else\n    {\n      char str[100];\n      sprintf(str, \"Joint Dynamixel ID : %d, Model Name : %s\", id, dynamixel_workbench_->getModelName(id));\n      log::println(str);\n\n      result = dynamixel_workbench_->setTimeBasedProfile(id, &log);\n      if(result == false)\n      {\n        log::error(log);\n        log::error(\"Please check your Dynamixel firmware version (v38~)\");\n      }\n\n      result = dynamixel_workbench_->writeRegister(id, return_delay_time_char, 0, &log);\n      if (result == false)\n      {\n        log::error(log);\n        log::error(\"Please check your Dynamixel firmware version\");\n      }\n    }\n  }\n  return true;\n}\n\nbool JointDynamixelProfileControl::setOperatingMode(std::vector<uint8_t> actuator_id, STRING dynamixel_mode)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const uint32_t velocity = uint32_t(control_loop_time_*1000) * 3;\n  const uint32_t acceleration = uint32_t(control_loop_time_*1000);\n  const uint32_t current = 0;\n\n  if (dynamixel_mode == \"position_mode\")\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->jointMode(actuator_id.at(num), velocity, acceleration, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n  else if (dynamixel_mode == \"current_based_position_mode\")\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->currentBasedPositionMode(actuator_id.at(num), current, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n  else\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->jointMode(actuator_id.at(num), velocity, acceleration, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n\n  return true;\n}\n\nbool JointDynamixelProfileControl::setSDKHandler(uint8_t actuator_id)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  result = dynamixel_workbench_->addSyncWriteHandler(actuator_id, \"Goal_Position\", &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->addSyncReadHandler(ADDR_PRESENT_CURRENT_2,\n                                                    (LENGTH_PRESENT_CURRENT_2 + LENGTH_PRESENT_VELOCITY_2 + LENGTH_PRESENT_POSITION_2),\n                                                    &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\nbool JointDynamixelProfileControl::writeProfileValue(std::vector<uint8_t> actuator_id, STRING profile_mode, uint32_t value)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const char * char_profile_mode = profile_mode.c_str();\n\n  for (uint8_t num = 0; num < actuator_id.size(); num++)\n  {\n    result = dynamixel_workbench_->writeRegister(actuator_id.at(num), char_profile_mode, value, &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  return true;\n}\n\nbool JointDynamixelProfileControl::writeGoalProfilingControlValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  uint8_t id_array[actuator_id.size()];\n  int32_t goal_value[actuator_id.size()];\n\n  //add tarajectory eq.\n  for(uint8_t index = 0; index < actuator_id.size(); index++)\n  {\n    float result_position;\n    float time_control = control_loop_time_;       //ms\n\n    if(previous_goal_value_.find(actuator_id.at(index)) == previous_goal_value_.end())\n    {\n      previous_goal_value_.insert(std::make_pair(actuator_id.at(index), value_vector.at(index)));\n    }\n\n    result_position = value_vector.at(index).position + 3*(value_vector.at(index).velocity * (time_control))/2;\n\n    id_array[index] = actuator_id.at(index);\n    goal_value[index] = dynamixel_workbench_->convertRadian2Value(actuator_id.at(index), result_position);\n\n    previous_goal_value_[actuator_id.at(index)] = value_vector.at(index);\n  }\n\n  result = dynamixel_workbench_->syncWrite(SYNC_WRITE_HANDLER, id_array, actuator_id.size(), goal_value, 1, &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n  return true;\n}\n\nstd::vector<robotis_manipulator::ActuatorValue> JointDynamixelProfileControl::receiveAllDynamixelValue(std::vector<uint8_t> actuator_id)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  std::vector<robotis_manipulator::ActuatorValue> all_actuator;\n\n  uint8_t id_array[actuator_id.size()];\n  for (uint8_t index = 0; index < actuator_id.size(); index++)\n    id_array[index] = actuator_id.at(index);\n\n  int32_t get_current[actuator_id.size()];\n  int32_t get_velocity[actuator_id.size()];\n  int32_t get_position[actuator_id.size()];\n\n  result = dynamixel_workbench_->syncRead(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                          id_array,\n                                          actuator_id.size(),\n                                          &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                id_array,\n                                                actuator_id.size(),\n                                                ADDR_PRESENT_CURRENT_2,\n                                                LENGTH_PRESENT_CURRENT_2,\n                                                get_current,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                 id_array,\n                                                 actuator_id.size(),\n                                                ADDR_PRESENT_VELOCITY_2,\n                                                LENGTH_PRESENT_VELOCITY_2,\n                                                get_velocity,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                 id_array,\n                                                 actuator_id.size(),\n                                                ADDR_PRESENT_POSITION_2,\n                                                LENGTH_PRESENT_POSITION_2,\n                                                get_position,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  for (uint8_t index = 0; index < actuator_id.size(); index++)\n  {\n    robotis_manipulator::ActuatorValue actuator;\n    actuator.effort = dynamixel_workbench_->convertValue2Current(get_current[index]);\n    actuator.velocity = dynamixel_workbench_->convertValue2Velocity(actuator_id.at(index), get_velocity[index]);\n    actuator.position = dynamixel_workbench_->convertValue2Radian(actuator_id.at(index), get_position[index]);\n\n    all_actuator.push_back(actuator);\n  }\n\n  return all_actuator;\n}\n\n\n/*****************************************************************************\n** Tool Dynamixel Control Functions\n*****************************************************************************/\nvoid ToolDynamixel::init(uint8_t actuator_id, const void *arg)\n{\n  STRING *get_arg_ = (STRING *)arg;\n\n  bool result = ToolDynamixel::initialize(actuator_id ,get_arg_[0], get_arg_[1]);\n\n  if (result == false)\n    return;\n}\n\nvoid ToolDynamixel::setMode(const void *arg)\n{\n  bool result = false;\n// const char* log = NULL;\n\n  STRING *get_arg_ = (STRING *)arg;\n\n  if (get_arg_[0] == \"position_mode\" || get_arg_[0] == \"current_based_position_mode\")\n  {\n    result = ToolDynamixel::setOperatingMode(get_arg_[0]);\n    if (result == false)\n      return;\n  }\n  else\n  {\n    result = ToolDynamixel::writeProfileValue(get_arg_[0], std::atoi(get_arg_[1].c_str()));\n    if (result == false)\n      return;\n  }\n\n  result = ToolDynamixel::setSDKHandler();\n  if (result == false)\n    return;\n}\n\nuint8_t ToolDynamixel::getId()\n{\n  return dynamixel_.id.at(0);\n}\n\nvoid ToolDynamixel::enable()\n{\n  const char* log = NULL;\n  bool result = false;\n  \n  result = dynamixel_workbench_->torqueOn(dynamixel_.id.at(0), &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n  enabled_state_ = true;\n}\n\nvoid ToolDynamixel::disable()\n{\n  const char* log = NULL;\n  bool result = false;\n  \n  result = dynamixel_workbench_->torqueOff(dynamixel_.id.at(0), &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n  enabled_state_ = false;\n}\n\nbool ToolDynamixel::sendToolActuatorValue(robotis_manipulator::ActuatorValue value)\n{\n  return ToolDynamixel::writeGoalPosition(value.position);\n}\n\nrobotis_manipulator::ActuatorValue ToolDynamixel::receiveToolActuatorValue()\n{\n  robotis_manipulator::ActuatorValue result;\n  result.position = ToolDynamixel::receiveDynamixelValue();\n  result.velocity = 0.0;\n  result.acceleration = 0.0;\n  result.effort = 0.0;\n  return result;\n}\n\n\n/*****************************************************************************\n** Functions called in Tool Dynamixel Profile Control Functions\n*****************************************************************************/\nbool ToolDynamixel::initialize(uint8_t actuator_id, STRING dxl_device_name, STRING dxl_baud_rate)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  STRING return_delay_time_st = \"Return_Delay_Time\";\n  const char * return_delay_time_char = return_delay_time_st.c_str();\n\n  dynamixel_.id.push_back(actuator_id);\n  dynamixel_.num = 1;\n\n  dynamixel_workbench_ = new DynamixelWorkbench;\n\n  result = dynamixel_workbench_->init(dxl_device_name.c_str(), std::atoi(dxl_baud_rate.c_str()), &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  uint16_t get_model_number;\n  result = dynamixel_workbench_->ping(dynamixel_.id.at(0), &get_model_number, &log);\n  if (result == false)\n  {\n    log::error(log);\n    log::error(\"Please check your Dynamixel ID\");\n  }\n  else\n  {\n    char str[100];\n    sprintf(str, \"Tool Dynamixel ID : %d, Model Name :\", dynamixel_.id.at(0));\n    strcat(str, dynamixel_workbench_->getModelName(dynamixel_.id.at(0)));\n    log::println(str);\n\n    result = dynamixel_workbench_->setVelocityBasedProfile(dynamixel_.id.at(0), &log);\n    if(result == false)\n    {\n      log::error(log);\n      log::error(\"Please check your Dynamixel firmware version (v38~)\");\n    }\n\n    result = dynamixel_workbench_->writeRegister(dynamixel_.id.at(0), return_delay_time_char, 0, &log);\n    if (result == false)\n    {\n      log::error(log);\n      log::error(\"Please check your Dynamixel firmware version\");\n    }\n  }\n\n  return true;\n}\n\nbool ToolDynamixel::setOperatingMode(STRING dynamixel_mode)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const uint32_t velocity = 0;\n  const uint32_t acceleration = 0;\n  const uint32_t current = 200;\n\n  if (dynamixel_mode == \"position_mode\")\n  {\n    result = dynamixel_workbench_->jointMode(dynamixel_.id.at(0), velocity, acceleration, &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  else if (dynamixel_mode == \"current_based_position_mode\")\n  {\n    result = dynamixel_workbench_->currentBasedPositionMode(dynamixel_.id.at(0), current, &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  else\n  {\n    result = dynamixel_workbench_->jointMode(dynamixel_.id.at(0), velocity, acceleration, &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n\n  return true;\n}\n\nbool ToolDynamixel::writeProfileValue(STRING profile_mode, uint32_t value)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const char * char_profile_mode = profile_mode.c_str();\n\n  result = dynamixel_workbench_->writeRegister(dynamixel_.id.at(0), char_profile_mode, value, &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\nbool ToolDynamixel::setSDKHandler()\n{\n  bool result = false;\n  const char* log = NULL;\n\n  result = dynamixel_workbench_->addSyncWriteHandler(dynamixel_.id.at(0), \"Goal_Position\", &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->addSyncReadHandler(dynamixel_.id.at(0),\n                                                    \"Present_Position\", \n                                                    &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\nbool ToolDynamixel::writeGoalPosition(double radian)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  int32_t goal_position = 0;\n\n  goal_position = dynamixel_workbench_->convertRadian2Value(dynamixel_.id.at(0), radian);\n\n  result = dynamixel_workbench_->syncWrite(SYNC_WRITE_HANDLER, &goal_position, &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\ndouble ToolDynamixel::receiveDynamixelValue()\n{\n  bool result = false;\n  const char* log = NULL;\n\n  int32_t get_value = 0;\n  uint8_t id_array[1] = {dynamixel_.id.at(0)};\n\n  result = dynamixel_workbench_->syncRead(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT, \n                                          id_array,\n                                          (uint8_t)1,\n                                          &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT, \n                                            id_array,\n                                            (uint8_t)1,\n                                            &get_value, \n                                            &log);\n  if (result == false)\n  {\n    log::error(log);\n  } \n\n  return dynamixel_workbench_->convertValue2Radian(dynamixel_.id.at(0), get_value);\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/delta_libs/src/delta_kinematics.cpp",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include \"../include/delta_libs/delta_kinematics.h\"\n\nusing namespace robotis_manipulator; \nusing namespace delta_kinematics;\n\n/*****************************************************************************\n** Kinematics Solver \n*****************************************************************************/\nvoid SolverUsingGeometry::setOption(const void *arg) {}\n\nEigen::MatrixXd SolverUsingGeometry::jacobian(Manipulator *manipulator, Name tool_name)\n{\n  return Eigen::MatrixXd::Identity(6, manipulator->getDOF());\n}\n\nvoid SolverUsingGeometry::solveForwardKinematics(Manipulator *manipulator) {}\n\nbool SolverUsingGeometry::solveInverseKinematics(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue> *goal_joint_value)\n{\n  return inverseKinematicsSolverUsingGeometry(manipulator, tool_name, target_pose, goal_joint_value);\n}\n\n/*****************************************************************************\n** Private\n*****************************************************************************/\nbool SolverUsingGeometry::inverseKinematicsSolverUsingGeometry(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue> *goal_joint_value)\n{\n  std::vector<JointValue> target_angle_vector;\n\n  double temp_angle[3];\n  double temp_angle2[3];\n  JointValue target_angle[12];\n  JointValue target_angle2[3];\n  const double link[3] = {0.100, 0.224, 0.020};\n  double start_x[3], start_y[3], start_z[3];\n  double goal_x[3], goal_y[3], goal_z[3];\n  double diff_x[3], diff_y[3], diff_z[3];\n  double temp[3], temp2[3], temp3[3], temp4[3], temp5[3] , temp6[3];\n  double a[3], b[3], c[3];\n  double target_pose_length[3];\n  double elbow_x[3], elbow_y[3], elbow_z[3];\n  double diff_x2[3], diff_y2[3], diff_z2[3];\n\n  // Start pose for each set of two joints\n  for (int i=0; i<3; i++)\n  {\n    start_x[i] = cos(PI*2.0/3.0*i)*(-0.055);\n    start_y[i] = sin(PI*2.0/3.0*i)*(-0.055);\n    start_z[i] = 0.17875;\n  }\n  \n  // Goal pose for each set of two joints\n  for (int i=0; i<3; i++)\n  {\n    goal_x[i] = target_pose.kinematic.position(0) + cos(PI*2.0/3.0*i)*(-link[2]);\n    goal_y[i] = target_pose.kinematic.position(1) + sin(PI*2.0/3.0*i)*(-link[2]);\n    goal_z[i] = target_pose.kinematic.position(2);\n  }\n\n  // Pose difference for each set of two joints\n  for (int i=0; i<3; i++)\n  {\n    diff_x[i] = goal_x[i] - start_x[i];\n    diff_y[i] = goal_y[i] - start_y[i];\n    diff_z[i] = goal_z[i] - start_z[i];\n  }\n\n  for (int i=0; i<3; i++)\n  {\n    temp[i] = diff_x[i]*cos(-PI*2.0/3.0*i) - diff_y[i]*sin(-PI*2.0/3.0*i);\n    temp2[i] = diff_x[i]*sin(-PI*2.0/3.0*i) + diff_y[i]*cos(-PI*2.0/3.0*i);\n    temp3[i] = sqrt(pow(link[1],2) - pow(temp2[i],2));\n    temp4[i] = sqrt(pow(temp[i],2) + pow(diff_z[i],2));\n    temp5[i] = pow(temp3[i],2) - pow(temp4[i],2) - pow(link[0],2);\n    target_angle[i].position = asin(temp5[i] / (2*temp4[i]*link[0])) - acos(-diff_z[i]/temp4[i]);    \n  }\n\n  target_angle_vector.push_back(target_angle[0]);\n  target_angle_vector.push_back(target_angle[1]);\n  target_angle_vector.push_back(target_angle[2]);\n\n  for (int i=0; i<3; i++){\n    elbow_x[i] = start_x[i] + cos(PI*2.0/3.0*i)*link[0]*(-cos(target_angle[i].position));\n    elbow_y[i] = start_y[i] + sin(PI*2.0/3.0*i)*link[0]*(-cos(target_angle[i].position));\n    elbow_z[i] = start_z[i] + link[0]*sin(target_angle[i].position);\n  }\n\n  // Pose difference for each set of two joints\n  for (int i=0; i<3; i++){\n    diff_x2[i] = goal_x[i] - elbow_x[i];\n    diff_y2[i] = goal_y[i] - elbow_y[i];\n    diff_z2[i] = goal_z[i] - elbow_z[i];\n  }\n\n  for (int i=0; i<3; i++){\n    temp6[i] = diff_x2[i]*sin(-PI*2.0/3.0*i) + diff_y2[i]*cos(-PI*2.0/3.0*i);\n    target_angle[2*i+4].position = asin(temp6[i] / link[1]);\n    target_angle[2*i+3].position = -PI + asin(-diff_z2[i] / cos(target_angle[2*i+4].position) / link[1]) - target_angle[i].position;\n    target_angle[2*i+3].position += PI*127.0/180.0;\n  }\n\n  target_angle_vector.push_back(target_angle[3]);\n  target_angle_vector.push_back(target_angle[4]);\n  target_angle_vector.push_back(target_angle[5]);\n  target_angle_vector.push_back(target_angle[6]);\n  target_angle_vector.push_back(target_angle[7]);\n  target_angle_vector.push_back(target_angle[8]);\n\n  target_angle[3].position -= PI*127.0/180.0;\n\n  target_angle[9].position = -target_angle[4].position;\n  target_angle[10].position = -PI - target_angle[0].position - target_angle[3].position;\n  target_angle[10].position += PI*53.0/180.0;\n\n  target_angle_vector.push_back(target_angle[9]);\n  target_angle_vector.push_back(target_angle[10]);\n  \n  *goal_joint_value = target_angle_vector;\n  manipulator->setAllJointValue(target_angle_vector);\n\n  return true;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/delta_libs.h",
    "content": "#include \"delta_libs/include/delta_libs/delta.h\"\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/linear_libs/include/linear_libs/linear.h",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef LINEAR_H_\n#define LINEAR_H_\n\n#include \"linear_custom_trajectory.h\"\n#include \"linear_dynamixel.h\"\n#include \"linear_kinematics.h\"\n\n#define CUSTOM_TRAJECTORY_SIZE 4\n#define CUSTOM_TRAJECTORY_LINE    \"custom_trajectory_line\"\n#define CUSTOM_TRAJECTORY_CIRCLE  \"custom_trajectory_circle\"\n#define CUSTOM_TRAJECTORY_RHOMBUS \"custom_trajectory_rhombus\"\n#define CUSTOM_TRAJECTORY_HEART   \"custom_trajectory_heart\"\n\n#define DXL_SIZE 4\n#define JOINT_DYNAMIXEL \"joint_dxl\"\n#define TOOL_DYNAMIXEL \"tool_dxl\"\n\n#define RECEIVE_RATE 0.100 // unit: s\n#define CONTROL_RATE 0.010 // unit: s\n\n#define X_AXIS robotis_manipulator::math::vector3(1.0, 0.0, 0.0)\n#define Y_AXIS robotis_manipulator::math::vector3(0.0, 1.0, 0.0)\n#define Z_AXIS robotis_manipulator::math::vector3(0.0, 0.0, 1.0)\n\nclass Linear : public robotis_manipulator::RobotisManipulator\n{\nprivate:\n  robotis_manipulator::Kinematics *kinematics_;\n  robotis_manipulator::JointActuator *joint_;  \n  robotis_manipulator::ToolActuator *tool_;    \n  robotis_manipulator::CustomTaskTrajectory *custom_trajectory_[CUSTOM_TRAJECTORY_SIZE];\n\n  bool using_actual_robot_state_;\n  bool receive_data_flag_ = false;\n  double prev_receive_time_ = 0.0;\n  double prev_control_time_ = 0.0;\n\npublic:\n  Linear();\n  virtual ~Linear();\n\n  void initDebug();\n  void initOpenManipulator(bool using_actual_robot_state, \n                           STRING usb_port = \"/dev/ttyUSB0\", \n                           STRING baud_rate = \"1000000\", \n                           float control_rate = CONTROL_RATE);\n  void processOpenManipulator(double present_time);\n\n  bool getUsingActualRobotState();\n  bool getReceiveDataFlag();\n  double getPrevReceiveTime();\n\n  void setReceiveDataFlag(bool receive_data_flag);\n  void setPrevReceiveTime(double prev_receive_time);\n};\n\n#endif // LINEAR_H_\n\n\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/linear_libs/include/linear_libs/linear_custom_trajectory.h",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef LINEAR_CUSTOM_TRAJECTORY_H_\n#define LINEAR_CUSTOM_TRAJECTORY_H_\n\n#if defined(__OPENCR__)\n  #include <RobotisManipulator.h>\n#else\n  #include <robotis_manipulator/robotis_manipulator.h>\n#endif\n\nusing namespace robotis_manipulator;\nusing namespace Eigen;\n\nnamespace linear_custom_trajectory\n{\n  \nenum AXIS{\n\tX_AXIS,\n\tY_AXIS,\n\tZ_AXIS,\n};\n\n/*****************************************************************************\n** Line\n*****************************************************************************/\nclass Line : public robotis_manipulator::CustomTaskTrajectory\n{\nprivate:\n  TaskWaypoint start_pose_;\n  TaskWaypoint goal_pose_;\n\n  double acc_dec_time_;\n  double move_time_;\n  std::vector<double> vel_max_;\n\npublic:\n\tLine() {}\n\tvirtual ~Line() {}\n\n  void initLine(double move_time, TaskWaypoint start, TaskWaypoint delta);\n  TaskWaypoint drawLine(double time_var);\n\n  virtual void setOption(const void *arg);\n  virtual void makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg);\n  virtual TaskWaypoint getTaskWaypoint(double tick);\n};\n\n\n/*****************************************************************************\n** Circle\n*****************************************************************************/\nclass Circle : public robotis_manipulator::CustomTaskTrajectory\n{\nprivate:\n  robotis_manipulator::MinimumJerk path_generator_;\n  VectorXd coefficient_;\n\n  TaskWaypoint start_pose_;\n  TaskWaypoint goal_pose_;\n\n  double radius_;\n  double start_angular_position_;\n  double revolution_;\n\npublic:\n\tCircle() {}\n\tvirtual ~Circle() {}\n\n  void initCircle(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position);\n  TaskWaypoint drawCircle(double time_var);\n\n  virtual void setOption(const void *arg);\n  virtual void makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg);\n  virtual TaskWaypoint getTaskWaypoint(double tick);\n};\n\n\n/*****************************************************************************\n** Rhombus\n*****************************************************************************/\nclass Rhombus : public robotis_manipulator::CustomTaskTrajectory\n{\nprivate:\n  robotis_manipulator::MinimumJerk path_generator_;\n  VectorXd coefficient_;\n\n  TaskWaypoint start_pose_;\n  TaskWaypoint goal_pose_;\n\n  double radius_;\n  double start_angular_position_;\n  double revolution_;\n\npublic:\n\tRhombus() {}\n\tvirtual ~Rhombus() {}\n\n  void initRhombus(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position);\n  TaskWaypoint drawRhombus(double time_var);\n\n  virtual void setOption(const void *arg);\n  virtual void makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg);\n  virtual TaskWaypoint getTaskWaypoint(double tick);\n};\n\n\n/*****************************************************************************\n** Heart\n*****************************************************************************/\nclass Heart : public robotis_manipulator::CustomTaskTrajectory\n{\nprivate:\n  robotis_manipulator::MinimumJerk path_generator_;\n  VectorXd coefficient_;\n\n  TaskWaypoint start_pose_;\n  TaskWaypoint goal_pose_;\n\n  double radius_;\n  double start_angular_position_;\n  double revolution_;\n\npublic:\n\tHeart() {}\n\tvirtual ~Heart() {}\n\n  void initHeart(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position);\n  TaskWaypoint drawHeart(double tick);\n\n  virtual void setOption(const void *arg);\n  virtual void makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg);\n  virtual TaskWaypoint getTaskWaypoint(double tick);\n};\n\n\n} // namespace linear_custom_trajectory\n#endif // LINEAR_CUSTOM_TRAJECTORY_H_\n\n\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/linear_libs/include/linear_libs/linear_dynamixel.h",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef LINEAR_DYNAMIXEL_H_\n#define LINEAR_DYNAMIXEL_H_\n\n#if defined(__OPENCR__)\n  #include <RobotisManipulator.h>\n  #include <DynamixelWorkbench.h>\n#else\n  #include <robotis_manipulator/robotis_manipulator.h>\n  #include <dynamixel_workbench_toolbox/dynamixel_workbench.h>\n#endif\n\nnamespace linear_dynamixel\n{\n\n#define SYNC_WRITE_HANDLER 0\n#define SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT 0\n\n//#define CONTROL_LOOP_TIME 10;    //ms\n\n// Protocol 2.0\n#define ADDR_PRESENT_CURRENT_2 126\n#define ADDR_PRESENT_VELOCITY_2 128\n#define ADDR_PRESENT_POSITION_2 132\n#define ADDR_VELOCITY_TRAJECTORY_2 136\n#define ADDR_POSITION_TRAJECTORY_2 140\n#define ADDR_PROFILE_ACCELERATION_2 108\n#define ADDR_PROFILE_VELOCITY_2 112\n#define ADDR_GOAL_POSITION_2 116\n\n\n#define LENGTH_PRESENT_CURRENT_2 2\n#define LENGTH_PRESENT_VELOCITY_2 4\n#define LENGTH_PRESENT_POSITION_2 4\n#define LENGTH_VELOCITY_TRAJECTORY_2 4\n#define LENGTH_POSITION_TRAJECTORY_2 4\n#define LENGTH_PROFILE_ACCELERATION_2 4\n#define LENGTH_PROFILE_VELOCITY_2 4\n#define LENGTH_GOAL_POSITION_2 4\n\n\n// Protocol 1.0\n#define ADDR_PRESENT_CURRENT_1 = 40;\n#define ADDR_PRESENT_VELOCITY_1 = 38;\n#define ADDR_PRESENT_POSITION_1 = 36;\n\n#define LENGTH_PRESENT_CURRENT_1 = 2;\n#define LENGTH_PRESENT_VELOCITY_1 = 2;\n#define LENGTH_PRESENT_POSITION_1 = 2;\n\ntypedef struct\n{\n  std::vector<uint8_t> id;\n  uint8_t num;\n} Joint;\n\nclass JointDynamixel : public robotis_manipulator::JointActuator\n{\nprivate:\n  DynamixelWorkbench *dynamixel_workbench_;\n  Joint dynamixel_;\n\npublic:\n  JointDynamixel(){}\n  virtual ~JointDynamixel(){}\n\n\n  /*****************************************************************************\n  ** Joint Dynamixel Control Functions\n  *****************************************************************************/\n  virtual void init(std::vector<uint8_t> actuator_id, const void *arg);\n  virtual void setMode(std::vector<uint8_t> actuator_id, const void *arg);\n  virtual std::vector<uint8_t> getId();\n\n  virtual void enable();\n  virtual void disable();\n\n  virtual bool sendJointActuatorValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector);\n  virtual std::vector<robotis_manipulator::ActuatorValue> receiveJointActuatorValue(std::vector<uint8_t> actuator_id);\n\n\n  /*****************************************************************************\n  ** Functions called in Joint Dynamixel Control Functions\n  *****************************************************************************/\n  bool initialize(std::vector<uint8_t> actuator_id, STRING dxl_device_name, STRING dxl_baud_rate);\n  bool setOperatingMode(std::vector<uint8_t> actuator_id, STRING dynamixel_mode = \"position_mode\");\n  bool setSDKHandler(uint8_t actuator_id);\n  bool writeProfileValue(std::vector<uint8_t> actuator_id, STRING profile_mode, uint32_t value);\n  bool writeGoalPosition(std::vector<uint8_t> actuator_id, std::vector<double> radian_vector);\n  std::vector<robotis_manipulator::ActuatorValue> receiveAllDynamixelValue(std::vector<uint8_t> actuator_id);\n};\n\nclass JointDynamixelProfileControl : public robotis_manipulator::JointActuator\n{\nprivate:\n  DynamixelWorkbench *dynamixel_workbench_;\n  Joint dynamixel_;\n  float control_loop_time_; // unit: ms\n  std::map<uint8_t, robotis_manipulator::ActuatorValue> previous_goal_value_;\n\npublic:\n  JointDynamixelProfileControl(float control_loop_time = 0.010);\n  virtual ~JointDynamixelProfileControl(){}\n\n\n  /*****************************************************************************\n  ** Joint Dynamixel Profile Control Functions\n  *****************************************************************************/\n  virtual void init(std::vector<uint8_t> actuator_id, const void *arg);\n  virtual void setMode(std::vector<uint8_t> actuator_id, const void *arg);\n  virtual std::vector<uint8_t> getId();\n\n  virtual void enable();\n  virtual void disable();\n\n  virtual bool sendJointActuatorValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector);\n  virtual std::vector<robotis_manipulator::ActuatorValue> receiveJointActuatorValue(std::vector<uint8_t> actuator_id);\n\n\n  /*****************************************************************************\n  ** Functions called in Joint Dynamixel Profile Control Functions\n  *****************************************************************************/\n  bool initialize(std::vector<uint8_t> actuator_id, STRING dxl_device_name, STRING dxl_baud_rate);\n  bool setOperatingMode(std::vector<uint8_t> actuator_id, STRING dynamixel_mode = \"position_mode\");\n  bool setSDKHandler(uint8_t actuator_id);\n  bool writeProfileValue(std::vector<uint8_t> actuator_id, STRING profile_mode, uint32_t value);\n  bool writeGoalProfilingControlValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector);\n  std::vector<robotis_manipulator::ActuatorValue> receiveAllDynamixelValue(std::vector<uint8_t> actuator_id);\n};\n\nclass ToolDynamixel : public robotis_manipulator::ToolActuator\n{\n private:\n  DynamixelWorkbench *dynamixel_workbench_;\n  Joint dynamixel_;\n\n public:\n  ToolDynamixel() {}\n  virtual ~ToolDynamixel() {}\n\n\n  /*****************************************************************************\n  ** Tool Dynamixel Control Functions\n  *****************************************************************************/\n  virtual void init(uint8_t actuator_id, const void *arg);\n  virtual void setMode(const void *arg);\n  virtual uint8_t getId();\n\n  virtual void enable();\n  virtual void disable();\n\n  virtual bool sendToolActuatorValue(robotis_manipulator::ActuatorValue value);\n  virtual robotis_manipulator::ActuatorValue receiveToolActuatorValue();\n\n\n  /*****************************************************************************\n  ** Functions called in Tool Dynamixel Profile Control Functions\n  *****************************************************************************/\n  bool initialize(uint8_t actuator_id, STRING dxl_device_name, STRING dxl_baud_rate);\n  bool setOperatingMode(STRING dynamixel_mode = \"position_mode\");\n  bool writeProfileValue(STRING profile_mode, uint32_t value);\n  bool setSDKHandler();\n  bool writeGoalPosition(double radian);\n  double receiveDynamixelValue();\n};\n\n} // namespace linear_dynamixel\n#endif // LINEAR_DYNAMIXEL_H_\n\n\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/linear_libs/include/linear_libs/linear_kinematics.h",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef LINEAR_KINEMATICS_H_\n#define LINEAR_KINEMATICS_H_\n\n#if defined(__OPENCR__)\n  #include <RobotisManipulator.h>\n#else\n  #include <robotis_manipulator/robotis_manipulator.h>\n#endif\n\nusing namespace Eigen;\nusing namespace robotis_manipulator;\n\nnamespace linear_kinematics\n{\n\n/*****************************************************************************\n** Kinematics Solver Using CHain Rule and Geometry\n*****************************************************************************/\nclass SolverUsingGeometry : public robotis_manipulator::Kinematics\n{\nprivate:\n  void forwardKinematicsSolverUsingGeometry(Manipulator *manipulator, Name component_name);\n  bool inverseKinematicsSolverUsingGeometry(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue>* goal_joint_value);\n  \npublic:\n  SolverUsingGeometry() {}\n  virtual ~SolverUsingGeometry() {}\n\n  virtual void setOption(const void *arg);\n  virtual MatrixXd jacobian(Manipulator *manipulator, Name tool_name);\n  virtual void solveForwardKinematics(Manipulator *manipulator);\n  virtual bool solveInverseKinematics(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue>* goal_joint_value);\n};\n\n} // namespace linear_kinematics\n\n#endif // LINEAR_KINEMATICS_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/linear_libs/src/linear.cpp",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include \"../include/linear_libs/linear.h\"\n\nLinear::Linear() {}\nLinear::~Linear()\n{\n  delete kinematics_;\n  delete joint_;\n  delete tool_;\n  for(uint8_t index = 0; index < CUSTOM_TRAJECTORY_SIZE; index++)\n    delete custom_trajectory_[index];\n}\n\nvoid Linear::initDebug()\n{\n  DEBUG.begin(57600); // Using Serial4(=SerialBT2)\n  log::print(\"OpenManipulator Debugging Port\"); \n}\n\nvoid Linear::initOpenManipulator(bool using_actual_robot_state, STRING usb_port, STRING baud_rate, float control_rate)\n{\n  /*****************************************************************************\n  ** Set if using actual robot\n  *****************************************************************************/\n  using_actual_robot_state_ = using_actual_robot_state;  \n\n  /*****************************************************************************\n  ** Initialize Manipulator Parameters\n  *****************************************************************************/\n  addWorld(\"world\",   // world name\n           \"joint1\"); // child name\n\n  addJoint(\"joint1\",  // my name\n           \"world\",   // parent name\n           \"joint2\",  // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Z_AXIS,    // axis of rotation\n           1,         // actuator id\n           5.0/3.0*M_PI,   // max_limit\n           -5.0/3.0*M_PI); // min_limit\n                 \n\n  addJoint(\"joint2\",  // my name\n           \"joint1\",  // parent name\n           \"joint3\",  // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Z_AXIS,    // axis of rotation\n           2,         // actuator id\n           5.0/3.0*M_PI,   // max_limit\n           -5.0/3.0*M_PI); // min_limit\n                  \n\n  addJoint(\"joint3\",  // my name\n           \"joint2\",  // parent name\n           \"tool\",    // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Z_AXIS,    // axis of rotation\n           3,         // actuator id\n           2.1*M_PI,  // max_limit\n           -2.1*M_PI);// min_limit\n\n  addTool(\"tool\",     // my name\n          \"joint3\",   // parent name\n          math::vector3(0.0, 0.0, 0.0),                    // Not used\n          math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n          4,          // actuator id\n          0.500,      // max gripper limit \n          -0.500);    // min gripper limit \n\n  /*****************************************************************************\n  ** Initialize Kinematics \n  *****************************************************************************/\n  kinematics_ = new linear_kinematics::SolverUsingGeometry();\n  addKinematics(kinematics_);\n\n  /*****************************************************************************\n  ** Initialize Custom Trajectory\n  *****************************************************************************/\n  custom_trajectory_[0] = new linear_custom_trajectory::Line();\n  custom_trajectory_[1] = new linear_custom_trajectory::Circle();\n  custom_trajectory_[2] = new linear_custom_trajectory::Rhombus();\n  custom_trajectory_[3] = new linear_custom_trajectory::Heart();\n\n  addCustomTrajectory(CUSTOM_TRAJECTORY_LINE, custom_trajectory_[0]);\n  addCustomTrajectory(CUSTOM_TRAJECTORY_CIRCLE, custom_trajectory_[1]);\n  addCustomTrajectory(CUSTOM_TRAJECTORY_RHOMBUS, custom_trajectory_[2]);\n  addCustomTrajectory(CUSTOM_TRAJECTORY_HEART, custom_trajectory_[3]);\n\n  if (using_actual_robot_state_)\n  {\n    /*****************************************************************************\n    ** Initialize ㅓoint Actuator\n    *****************************************************************************/\n    joint_ = new linear_dynamixel::JointDynamixelProfileControl(control_rate);\n\n    // Set communication arguments \n    STRING dxl_comm_arg[2] = {usb_port, baud_rate};\n    void *p_dxl_comm_arg = &dxl_comm_arg; \n\n    // Set joint actuator id \n    std::vector<uint8_t> jointDxlId;\n    jointDxlId.push_back(1);\n    jointDxlId.push_back(2);\n    jointDxlId.push_back(3);\n    addJointActuator(JOINT_DYNAMIXEL, joint_, jointDxlId, p_dxl_comm_arg);\n\n    // Set joint actuator control mode\n    STRING joint_dxl_mode_arg = \"position_mode\";\n    void *p_joint_dxl_mode_arg = &joint_dxl_mode_arg;\n    setJointActuatorMode(JOINT_DYNAMIXEL, jointDxlId, p_joint_dxl_mode_arg);\n\n    /*****************************************************************************\n    ** Initialize Tool Actuator\n    *****************************************************************************/\n    tool_ = new linear_dynamixel::ToolDynamixel();\n\n    // Set tool actuator id \n    uint8_t toolDxlId = 4;\n    addToolActuator(TOOL_DYNAMIXEL, tool_, toolDxlId, p_dxl_comm_arg);\n\n    // Set tool actuator control mode \n    STRING tool_dxl_mode_arg = \"position_mode\";\n    void *p_tool_dxl_mode_arg = &tool_dxl_mode_arg;\n    setToolActuatorMode(TOOL_DYNAMIXEL, p_tool_dxl_mode_arg);\n\n    /*****************************************************************************\n    ** Enable actuators and Receive actuator values \n    *****************************************************************************/\n    // Enable All Actuators \n    enableAllActuator();\n\n    // Receive current angles from all actuators \n    receiveAllJointActuatorValue();\n    receiveAllToolActuatorValue();\n  }\n}\n\n/*****************************************************************************\n** Process actuator values received from external controllers\n*****************************************************************************/\nvoid Linear::processOpenManipulator(double present_time)  \n{\n  if (present_time - prev_control_time_ >= CONTROL_RATE)  \n  {\n    JointWaypoint goal_joint_value = getJointGoalValueFromTrajectory(present_time);\n    JointWaypoint goal_tool_value  = getToolGoalValue();\n\n    if (using_actual_robot_state_)\n    {\n      receiveAllJointActuatorValue();   \n      receiveAllToolActuatorValue();    \n    }\n\n    if(goal_joint_value.size() != 0) sendAllJointActuatorValue(goal_joint_value);   \n    if(goal_tool_value.size() != 0) sendAllToolActuatorValue(goal_tool_value);\n    solveForwardKinematics(); \n\n    // Set previous control time\n    prev_control_time_ = millis()/1000.0;\n  }\n}\n\n/*****************************************************************************\n** State Functions\n*****************************************************************************/\n// Check if using acutal robot \nbool Linear::getUsingActualRobotState() \n{\n  return using_actual_robot_state_;\n}\n\n/* Check if the program read data within control rate) */\nbool Linear::getReceiveDataFlag()  \n{\n  return receive_data_flag_;\n}\n\n/* Get the previous time when data were received */\ndouble Linear::getPrevReceiveTime() \n{\n  return prev_receive_time_;\n}\n\n/* Set whether data were received or not */\nvoid Linear::setReceiveDataFlag(bool receive_data_flag) \n{\n  receive_data_flag_ = receive_data_flag;\n}\n\n/* Set the previous time when data were received */\nvoid Linear::setPrevReceiveTime(double prev_receive_time)  \n{\n  prev_receive_time_ = prev_receive_time;\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/linear_libs/src/linear_custom_trajectory.cpp",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include \"../include/linear_libs/linear_custom_trajectory.h\"\n\nusing namespace linear_custom_trajectory;\nusing namespace Eigen;\n\n\n/*****************************************************************************\n** Line\n*****************************************************************************/\nvoid Line::initLine(double move_time, TaskWaypoint start, TaskWaypoint delta)\n{\n  move_time_ = move_time;\n  acc_dec_time_ = move_time_ * 0.2;\n  vel_max_.resize(3);\n\n  TaskWaypoint start_to_goal;\n\n  start_pose_ = start;\n\n  goal_pose_ .kinematic.orientation = start_pose_.kinematic.orientation;\n  goal_pose_ .kinematic.position = start.kinematic.position + delta.kinematic.position;\n\n  vel_max_.at(X_AXIS) = delta.kinematic.position(X_AXIS)/(move_time_ - acc_dec_time_);\n  vel_max_.at(Y_AXIS) = delta.kinematic.position(Y_AXIS)/(move_time_ - acc_dec_time_);\n  vel_max_.at(Z_AXIS) = delta.kinematic.position(Z_AXIS)/(move_time_ - acc_dec_time_);\n}\n\nTaskWaypoint Line::drawLine(double time_var)\n{\n  TaskWaypoint pose;\n\n  if(acc_dec_time_ >= time_var)\n  {\n    pose.kinematic.position(X_AXIS) = 0.5*vel_max_.at(X_AXIS)*pow(time_var, 2)/acc_dec_time_ + start_pose_.kinematic.position(X_AXIS);\n    pose.kinematic.position(Y_AXIS) = 0.5*vel_max_.at(Y_AXIS)*pow(time_var, 2)/acc_dec_time_ + start_pose_.kinematic.position(Y_AXIS);\n    pose.kinematic.position(Z_AXIS) = 0.5*vel_max_.at(Z_AXIS)*pow(time_var, 2)/acc_dec_time_ + start_pose_.kinematic.position(Z_AXIS);\n  }\n  else if(time_var > acc_dec_time_ && (move_time_ - acc_dec_time_) >= time_var )\n  {\n    pose.kinematic.position(X_AXIS) = vel_max_.at(X_AXIS)*(time_var-(acc_dec_time_*0.5)) + start_pose_.kinematic.position(X_AXIS);\n    pose.kinematic.position(Y_AXIS) = vel_max_.at(Y_AXIS)*(time_var-(acc_dec_time_*0.5)) + start_pose_.kinematic.position(Y_AXIS);\n    pose.kinematic.position(Z_AXIS) = vel_max_.at(Z_AXIS)*(time_var-(acc_dec_time_*0.5)) + start_pose_.kinematic.position(Z_AXIS);\n  }\n  else if(time_var > (move_time_ - acc_dec_time_) && (time_var < move_time_))\n  {\n    pose.kinematic.position(X_AXIS) = goal_pose_.kinematic.position(X_AXIS) - vel_max_.at(X_AXIS)*0.5/acc_dec_time_*(pow((move_time_-time_var),2));\n    pose.kinematic.position(Y_AXIS) = goal_pose_.kinematic.position(Y_AXIS) - vel_max_.at(Y_AXIS)*0.5/acc_dec_time_*(pow((move_time_-time_var),2));\n    pose.kinematic.position(Z_AXIS) = goal_pose_.kinematic.position(Z_AXIS) - vel_max_.at(Z_AXIS)*0.5/acc_dec_time_*(pow((move_time_-time_var),2));\n  }\n  else if(time_var <= move_time_)\n  {\n    pose.kinematic.position(X_AXIS) = goal_pose_.kinematic.position(X_AXIS);\n    pose.kinematic.position(Y_AXIS) = goal_pose_.kinematic.position(Y_AXIS);\n    pose.kinematic.position(Z_AXIS) = goal_pose_.kinematic.position(Z_AXIS);\n  }\n\n  pose.kinematic.orientation = start_pose_.kinematic.orientation;\n  pose.dynamic.linear.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.linear.acceleration = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.acceleration = Eigen::Vector3d::Zero(3);\n\n  return pose;\n}\n\nTaskWaypoint Line::getTaskWaypoint(double tick)\n{\n  return drawLine(tick);\n}\n\n\nvoid Line::makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg)\n{\n  TaskWaypoint *c_arg = (TaskWaypoint *)arg;\n  initLine(move_time, start, c_arg[0]);\n}\nvoid Line::setOption(const void *arg) {}\n\n\n/*****************************************************************************\n** Circle\n*****************************************************************************/\nvoid Circle::initCircle(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position)\n{\n  start_pose_ = start;\n\n  radius_ = radius;\n  revolution_ = revolution;\n  start_angular_position_ = start_angular_position;\n\n  Point drawingStart, drawingGoal;\n\n  drawingStart.position = 0.0;\n  drawingStart.velocity = 0.0;\n  drawingStart.acceleration = 0.0;\n  drawingStart.effort = 0.0;\n\n  drawingGoal.position = revolution_ * 2*M_PI;\n  drawingGoal.velocity = 0.0;\n  drawingGoal.acceleration = 0.0;\n  drawingGoal.effort = 0.0;\n\n  path_generator_.calcCoefficient(drawingStart, drawingGoal, move_time);\n  coefficient_ = path_generator_.getCoefficient();\n}\n\nTaskWaypoint Circle::drawCircle(double tick)\n{\n  // get time variable\n  double get_time_var = 0.0;\n\n  get_time_var = coefficient_(0) +\n                 coefficient_(1) * pow(tick, 1) +\n                 coefficient_(2) * pow(tick, 2) +\n                 coefficient_(3) * pow(tick, 3) +\n                 coefficient_(4) * pow(tick, 4) +\n                 coefficient_(5) * pow(tick, 5);\n\n  // set drawing trajectory\n  TaskWaypoint pose;\n\n  double diff_pose[2];\n\n  diff_pose[0] = (cos(get_time_var)-1)*cos(start_angular_position_) - sin(get_time_var)*sin(start_angular_position_);\n  diff_pose[1] = (cos(get_time_var)-1)*sin(start_angular_position_) + sin(get_time_var)*cos(start_angular_position_);\n\n  pose.kinematic.position(X_AXIS) = start_pose_.kinematic.position(X_AXIS) + radius_ * diff_pose[0];\n  pose.kinematic.position(Y_AXIS) = start_pose_.kinematic.position(Y_AXIS) + radius_ * diff_pose[1];\n  pose.kinematic.position(Z_AXIS) = start_pose_.kinematic.position(Z_AXIS);\n\n  pose.kinematic.orientation = start_pose_.kinematic.orientation;\n\n  pose.dynamic.linear.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.linear.acceleration = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.acceleration = Eigen::Vector3d::Zero(3);\n\n  return pose;\n}\n\nTaskWaypoint Circle::getTaskWaypoint(double tick)\n{\n  return drawCircle(tick);\n}\n\nvoid Circle::makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg)\n{\n  double *get_arg_ = (double *)arg;\n  initCircle(move_time, start, get_arg_[0], get_arg_[1], get_arg_[2]);\n}\n\nvoid Circle::setOption(const void *arg){}\n\n\n/*****************************************************************************\n** Rhombus\n*****************************************************************************/\nvoid Rhombus::initRhombus(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position)\n{\n  start_pose_ = start;\n\n  radius_ = radius;\n  revolution_ = revolution;\n  start_angular_position_ = start_angular_position;\n\n  Point drawingStart, drawingGoal;\n\n  drawingStart.position = 0.0;\n  drawingStart.velocity = 0.0;\n  drawingStart.acceleration = 0.0;\n  drawingStart.effort = 0.0;\n\n  drawingGoal.position = revolution_ * 2*M_PI;\n  drawingGoal.velocity = 0.0;\n  drawingGoal.acceleration = 0.0;\n  drawingGoal.effort = 0.0;\n\n  path_generator_.calcCoefficient(drawingStart, drawingGoal, move_time);\n  coefficient_ = path_generator_.getCoefficient();\n}\n\n\nTaskWaypoint Rhombus::drawRhombus(double tick)\n{\n  // get time variable\n  double get_time_var = 0.0;\n\n  get_time_var = coefficient_(0) +\n                 coefficient_(1) * pow(tick, 1) +\n                 coefficient_(2) * pow(tick, 2) +\n                 coefficient_(3) * pow(tick, 3) +\n                 coefficient_(4) * pow(tick, 4) +\n                 coefficient_(5) * pow(tick, 5); \n\n  // set drawing trajectory\n  TaskWaypoint pose;\n  double diff_pose[2];\n  double traj[2];\n\n  while(true)\n  {\n    if (get_time_var < PI*2) break;\n    get_time_var = get_time_var - PI*2;\n  }\n\n  if (get_time_var >= 0 && get_time_var < PI/2){\n    traj[0] = - get_time_var / (PI/2);\n    traj[1] = - get_time_var / (PI/2);\n  } else if (get_time_var >= PI/2 && get_time_var < PI){\n    traj[0] = - get_time_var / (PI/2);\n    traj[1] = get_time_var / (PI/2) - 2;\n  } else if (get_time_var >= PI && get_time_var < PI*3/2){\n    traj[0] = get_time_var / (PI/2) - 4;\n    traj[1] = get_time_var / (PI/2) - 2;\n  } else {\n    traj[0] = get_time_var / (PI/2) - 4;\n    traj[1] = - get_time_var / (PI/2) + 4;\n  }\n  \n\n  diff_pose[0] = traj[0]*cos(start_angular_position_) - traj[1]*sin(start_angular_position_);\n  diff_pose[1] = traj[0]*sin(start_angular_position_) + traj[1]*cos(start_angular_position_);\n\n  pose.kinematic.position(X_AXIS) = start_pose_.kinematic.position(X_AXIS) + radius_ * diff_pose[0];\n  pose.kinematic.position(Y_AXIS) = start_pose_.kinematic.position(Y_AXIS) + radius_ * diff_pose[1];\n  pose.kinematic.position(Z_AXIS) = start_pose_.kinematic.position(Z_AXIS);\n\n  pose.kinematic.orientation = start_pose_.kinematic.orientation;\n\n  pose.dynamic.linear.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.linear.acceleration = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.acceleration = Eigen::Vector3d::Zero(3);\n\n  return pose;\n}\n\n\nvoid Rhombus::makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg)\n{\n  double *get_arg_ = (double *)arg;\n  initRhombus(move_time, start, get_arg_[0], get_arg_[1], get_arg_[2]);\n}\n\nTaskWaypoint Rhombus::getTaskWaypoint(double tick)\n{\n  return drawRhombus(tick);\n}\nvoid Rhombus::setOption(const void *arg){}\n\n\n/*****************************************************************************\n** Heart\n*****************************************************************************/\nvoid Heart::initHeart(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position)\n{\n  start_pose_ = start;\n\n  radius_ = radius;\n  revolution_ = revolution;\n  start_angular_position_ = start_angular_position;\n\n  Point drawingStart, drawingGoal;\n\n  drawingStart.position = 0.0;\n  drawingStart.velocity = 0.0;\n  drawingStart.acceleration = 0.0;\n  drawingStart.effort = 0.0;\n\n  drawingGoal.position = revolution_ * 2*M_PI;\n  drawingGoal.velocity = 0.0;\n  drawingGoal.acceleration = 0.0;\n  drawingGoal.effort = 0.0;\n\n  path_generator_.calcCoefficient(drawingStart, drawingGoal, move_time);\n  coefficient_ = path_generator_.getCoefficient();\n}\n\nTaskWaypoint Heart::drawHeart(double tick)\n{\n  // get time variable\n  double get_time_var = 0.0;\n\n  get_time_var = coefficient_(0) +\n                 coefficient_(1) * pow(tick, 1) +\n                 coefficient_(2) * pow(tick, 2) +\n                 coefficient_(3) * pow(tick, 3) +\n                 coefficient_(4) * pow(tick, 4) +\n                 coefficient_(5) * pow(tick, 5);\n\n  // set drawing trajectory\n  TaskWaypoint pose;\n  double diff_pose[2];\n  double traj[2];\n\n\tdouble shift_offset = - 5.0;\n\n  traj[0] = (shift_offset + (13*cos(get_time_var) - 5*cos(2*get_time_var) - 2*cos(3*get_time_var) - cos(4*get_time_var))) / 16;\n  traj[1] = (16*sin(get_time_var)*sin(get_time_var)*sin(get_time_var)) / 16;\n\n  diff_pose[0] = traj[0]*cos(start_angular_position_) - traj[1]*sin(start_angular_position_);\n  diff_pose[1] = traj[0]*sin(start_angular_position_) + traj[1]*cos(start_angular_position_);\n\n  pose.kinematic.position(X_AXIS) = start_pose_.kinematic.position(X_AXIS) + radius_ * diff_pose[0];\n  pose.kinematic.position(Y_AXIS) = start_pose_.kinematic.position(Y_AXIS) + radius_ * diff_pose[1];\n  pose.kinematic.position(Z_AXIS) = start_pose_.kinematic.position(Z_AXIS);\n\n  pose.kinematic.orientation = start_pose_.kinematic.orientation;\n\n  pose.dynamic.linear.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.linear.acceleration = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.acceleration = Eigen::Vector3d::Zero(3);\n\n  return pose;\n}\n\nvoid Heart::makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg)\n{\n  double *get_arg_ = (double *)arg;\n  initHeart(move_time, start, get_arg_[0], get_arg_[1], get_arg_[2]);\n}\nvoid Heart::setOption(const void *arg){}\n\nTaskWaypoint Heart::getTaskWaypoint(double tick)\n{\n  return drawHeart(tick);\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/linear_libs/src/linear_dynamixel.cpp",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include \"../include/linear_libs/linear_dynamixel.h\"\n\nusing namespace linear_dynamixel;\nusing namespace robotis_manipulator;\n\n/*****************************************************************************\n** Joint Dynamixel Control Functions\n*****************************************************************************/\nvoid JointDynamixel::init(std::vector<uint8_t> actuator_id, const void *arg)\n{\n  STRING *get_arg_ = (STRING *)arg;\n\n  bool result = JointDynamixel::initialize(actuator_id ,get_arg_[0], get_arg_[1]);\n\n  if (result == false)\n    return;\n}\n\nvoid JointDynamixel::setMode(std::vector<uint8_t> actuator_id, const void *arg)\n{\n  bool result = false;\n  // const char* log = NULL;\n\n  STRING *get_arg_ = (STRING *)arg;\n\n  if (get_arg_[0] == \"position_mode\" || get_arg_[0] == \"current_based_position_mode\")\n  {\n    result = JointDynamixel::setOperatingMode(actuator_id, get_arg_[0]);\n    if (result == false)\n      return;\n\n    result = JointDynamixel::setSDKHandler(actuator_id.at(0));\n    if (result == false)\n      return;\n  }\n  else\n  {\n    result = JointDynamixel::writeProfileValue(actuator_id, get_arg_[0], std::atoi(get_arg_[1].c_str()));\n    if (result == false)\n      return;\n  }\n  return;\n}\n\nstd::vector<uint8_t> JointDynamixel::getId()\n{\n  return dynamixel_.id;\n}\n\nvoid JointDynamixel::enable()\n{\n  const char* log = NULL;\n  bool result = false;\n  \n  for (uint32_t index = 0; index < dynamixel_.num; index++)\n  {\n    result = dynamixel_workbench_->torqueOn(dynamixel_.id.at(index), &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  enabled_state_ = true;\n}\n\nvoid JointDynamixel::disable()\n{\n  const char* log = NULL;\n  bool result = false;\n  \n  for (uint32_t index = 0; index < dynamixel_.num; index++)\n  {\n    result = dynamixel_workbench_->torqueOff(dynamixel_.id.at(index), &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  enabled_state_ = false;\n}\n\nbool JointDynamixel::sendJointActuatorValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector)\n{\n  bool result = false;\n\n  std::vector<double> radian_vector;\n  for(uint32_t index = 0; index < value_vector.size(); index++)\n  {\n    radian_vector.push_back(value_vector.at(index).position);\n  }\n  result = JointDynamixel::writeGoalPosition(actuator_id, radian_vector);\n  if (result == false)\n    return false;\n\n  return true;\n}\n\nstd::vector<robotis_manipulator::ActuatorValue> JointDynamixel::receiveJointActuatorValue(std::vector<uint8_t> actuator_id)\n{\n  return JointDynamixel::receiveAllDynamixelValue(actuator_id);\n}\n\n\n/*****************************************************************************\n** Functions called in Joint Dynamixel Control Functions\n*****************************************************************************/\nbool JointDynamixel::initialize(std::vector<uint8_t> actuator_id, STRING dxl_device_name, STRING dxl_baud_rate)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  STRING return_delay_time_st = \"Return_Delay_Time\";\n  const char * return_delay_time_char = return_delay_time_st.c_str();\n\n  dynamixel_.id = actuator_id;\n  dynamixel_.num = actuator_id.size();\n\n  dynamixel_workbench_ = new DynamixelWorkbench;\n\n  result = dynamixel_workbench_->init(dxl_device_name.c_str(), std::atoi(dxl_baud_rate.c_str()), &log);\n  if (result == false)\n  {\n    log::error(log);\n  }    \n\n  uint16_t get_model_number;\n  for (uint8_t index = 0; index < dynamixel_.num; index++)\n  {\n    uint8_t id = dynamixel_.id.at(index);\n    result = dynamixel_workbench_->ping(id, &get_model_number, &log);\n\n    if (result == false)\n    {\n      log::error(log);\n      log::error(\"Please check your Dynamixel ID\");\n    }\n    else\n    {\n      char str[100];\n      sprintf(str, \"Joint Dynamixel ID : %d, Model Name : %s\", id, dynamixel_workbench_->getModelName(id));\n      log::println(str);\n\n      result = dynamixel_workbench_->setVelocityBasedProfile(id, &log);\n      if(result == false)\n      {\n        log::error(log);\n        log::error(\"Please check your Dynamixel firmware version (v38~)\");\n      }\n\n      result = dynamixel_workbench_->writeRegister(id, return_delay_time_char, 0, &log);\n      if (result == false)\n      {\n        log::error(log);\n        log::error(\"Please check your Dynamixel firmware version\");\n      }\n    }\n  }\n  return true;\n}\n\nbool JointDynamixel::setOperatingMode(std::vector<uint8_t> actuator_id, STRING dynamixel_mode)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const uint32_t velocity = 0;\n  const uint32_t acceleration = 0;\n  const uint32_t current = 0;\n\n  if (dynamixel_mode == \"position_mode\")\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->jointMode(actuator_id.at(num), velocity, acceleration, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n  else if (dynamixel_mode == \"current_based_position_mode\")\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->currentBasedPositionMode(actuator_id.at(num), current, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n  else\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->jointMode(actuator_id.at(num), velocity, acceleration, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n\n  return true;\n}\n\nbool JointDynamixel::setSDKHandler(uint8_t actuator_id)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  result = dynamixel_workbench_->addSyncWriteHandler(actuator_id, \"Goal_Position\", &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->addSyncReadHandler(ADDR_PRESENT_CURRENT_2, \n                                                    (LENGTH_PRESENT_CURRENT_2 + LENGTH_PRESENT_VELOCITY_2 + LENGTH_PRESENT_POSITION_2), \n                                                    &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\nbool JointDynamixel::writeProfileValue(std::vector<uint8_t> actuator_id, STRING profile_mode, uint32_t value)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const char * char_profile_mode = profile_mode.c_str();\n\n  for (uint8_t num = 0; num < actuator_id.size(); num++)\n  {\n    result = dynamixel_workbench_->writeRegister(actuator_id.at(num), char_profile_mode, value, &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n\n  return true;\n}\n\nbool JointDynamixel::writeGoalPosition(std::vector<uint8_t> actuator_id, std::vector<double> radian_vector)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  uint8_t id_array[actuator_id.size()];\n  int32_t goal_position[actuator_id.size()];\n\n  for (uint8_t index = 0; index < actuator_id.size(); index++)\n  {\n    id_array[index] = actuator_id.at(index);\n    goal_position[index] = dynamixel_workbench_->convertRadian2Value(actuator_id.at(index), radian_vector.at(index));\n  }\n\n  result = dynamixel_workbench_->syncWrite(SYNC_WRITE_HANDLER, id_array, actuator_id.size(), goal_position, 1, &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\nstd::vector<robotis_manipulator::ActuatorValue> JointDynamixel::receiveAllDynamixelValue(std::vector<uint8_t> actuator_id)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  std::vector<robotis_manipulator::ActuatorValue> all_actuator;\n\n  uint8_t id_array[actuator_id.size()];\n  for (uint8_t index = 0; index < actuator_id.size(); index++)\n    id_array[index] = actuator_id.at(index);\n\n  int32_t get_current[actuator_id.size()];\n  int32_t get_velocity[actuator_id.size()];\n  int32_t get_position[actuator_id.size()];\n\n  result = dynamixel_workbench_->syncRead(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                          id_array,\n                                          actuator_id.size(),\n                                          &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                id_array,\n                                                actuator_id.size(),\n                                                ADDR_PRESENT_CURRENT_2,\n                                                LENGTH_PRESENT_CURRENT_2,\n                                                get_current,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                 id_array,\n                                                 actuator_id.size(),\n                                                ADDR_PRESENT_VELOCITY_2,\n                                                LENGTH_PRESENT_VELOCITY_2,\n                                                get_velocity,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                 id_array,\n                                                 actuator_id.size(),\n                                                ADDR_PRESENT_POSITION_2,\n                                                LENGTH_PRESENT_POSITION_2,\n                                                get_position,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  for (uint8_t index = 0; index < actuator_id.size(); index++)\n  {\n    robotis_manipulator::ActuatorValue actuator;\n    actuator.effort = dynamixel_workbench_->convertValue2Current(get_current[index]);\n    actuator.velocity = dynamixel_workbench_->convertValue2Velocity(actuator_id.at(index), get_velocity[index]);\n    actuator.position = dynamixel_workbench_->convertValue2Radian(actuator_id.at(index), get_position[index]);\n\n    all_actuator.push_back(actuator);\n  }\n\n  return all_actuator;\n}\n\n\n/*****************************************************************************\n** Joint Dynamixel Profile Control Functions\n*****************************************************************************/\nJointDynamixelProfileControl::JointDynamixelProfileControl(float control_loop_time)\n{\n  control_loop_time_ = control_loop_time;\n}\n\nvoid JointDynamixelProfileControl::init(std::vector<uint8_t> actuator_id, const void *arg)\n{\n  STRING *get_arg_ = (STRING *)arg;\n\n  bool result = JointDynamixelProfileControl::initialize(actuator_id ,get_arg_[0], get_arg_[1]);\n\n  if (result == false)\n    return;\n}\n\nvoid JointDynamixelProfileControl::setMode(std::vector<uint8_t> actuator_id, const void *arg)\n{\n  bool result = false;\n  // const char* log = NULL;\n\n  STRING *get_arg_ = (STRING *)arg;\n\n  if (get_arg_[0] == \"position_mode\" || get_arg_[0] == \"current_based_position_mode\")\n  {\n    result = JointDynamixelProfileControl::setOperatingMode(actuator_id, get_arg_[0]);\n    if (result == false)\n      return;\n\n    result = JointDynamixelProfileControl::setSDKHandler(actuator_id.at(0));\n    if (result == false)\n      return;\n  }\n  else\n  {\n    result = JointDynamixelProfileControl::writeProfileValue(actuator_id, get_arg_[0], std::atoi(get_arg_[1].c_str()));\n    if (result == false)\n      return;\n  }\n  return;\n}\n\nstd::vector<uint8_t> JointDynamixelProfileControl::getId()\n{\n  return dynamixel_.id;\n}\n\nvoid JointDynamixelProfileControl::enable()\n{\n  const char* log = NULL;\n  bool result = false;\n\n  for (uint32_t index = 0; index < dynamixel_.num; index++)\n  {\n    result = dynamixel_workbench_->torqueOn(dynamixel_.id.at(index), &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  enabled_state_ = true;\n}\n\nvoid JointDynamixelProfileControl::disable()\n{\n  const char* log = NULL;\n  bool result = false;\n\n  for (uint32_t index = 0; index < dynamixel_.num; index++)\n  {\n    result = dynamixel_workbench_->torqueOff(dynamixel_.id.at(index), &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  enabled_state_ = false;\n}\n\nbool JointDynamixelProfileControl::sendJointActuatorValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector)\n{\n  bool result = false;\n\n  result = JointDynamixelProfileControl::writeGoalProfilingControlValue(actuator_id, value_vector);\n  if (result == false)\n    return false;\n\n  return true;\n}\n\nstd::vector<robotis_manipulator::ActuatorValue> JointDynamixelProfileControl::receiveJointActuatorValue(std::vector<uint8_t> actuator_id)\n{\n  return JointDynamixelProfileControl::receiveAllDynamixelValue(actuator_id);\n}\n\n\n/*****************************************************************************\n** Functions called in Joint Dynamixel Profile Control Functions\n*****************************************************************************/\nbool JointDynamixelProfileControl::initialize(std::vector<uint8_t> actuator_id, STRING dxl_device_name, STRING dxl_baud_rate)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  STRING return_delay_time_st = \"Return_Delay_Time\";\n  const char * return_delay_time_char = return_delay_time_st.c_str();\n\n  dynamixel_.id = actuator_id;\n  dynamixel_.num = actuator_id.size();\n\n  dynamixel_workbench_ = new DynamixelWorkbench;\n\n  result = dynamixel_workbench_->init(dxl_device_name.c_str(), std::atoi(dxl_baud_rate.c_str()), &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  uint16_t get_model_number;\n  for (uint8_t index = 0; index < dynamixel_.num; index++)\n  {\n    uint8_t id = dynamixel_.id.at(index);\n    result = dynamixel_workbench_->ping(id, &get_model_number, &log);\n\n    if (result == false)\n    {\n      log::error(log);\n      log::error(\"Please check your Dynamixel ID\");\n    }\n    else\n    {\n      char str[100];\n      sprintf(str, \"Joint Dynamixel ID : %d, Model Name : %s\", id, dynamixel_workbench_->getModelName(id));\n      log::println(str);\n\n      result = dynamixel_workbench_->setTimeBasedProfile(id, &log);\n      if(result == false)\n      {\n        log::error(log);\n        log::error(\"Please check your Dynamixel firmware version (v38~)\");\n      }\n\n      result = dynamixel_workbench_->writeRegister(id, return_delay_time_char, 0, &log);\n      if (result == false)\n      {\n        log::error(log);\n        log::error(\"Please check your Dynamixel firmware version\");\n      }\n    }\n  }\n  return true;\n}\n\nbool JointDynamixelProfileControl::setOperatingMode(std::vector<uint8_t> actuator_id, STRING dynamixel_mode)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const uint32_t velocity = uint32_t(control_loop_time_*1000) * 3;\n  const uint32_t acceleration = uint32_t(control_loop_time_*1000);\n  const uint32_t current = 0;\n\n  if (dynamixel_mode == \"position_mode\")\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->jointMode(actuator_id.at(num), velocity, acceleration, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n  else if (dynamixel_mode == \"current_based_position_mode\")\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->currentBasedPositionMode(actuator_id.at(num), current, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n  else\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->jointMode(actuator_id.at(num), velocity, acceleration, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n\n  return true;\n}\n\nbool JointDynamixelProfileControl::setSDKHandler(uint8_t actuator_id)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  result = dynamixel_workbench_->addSyncWriteHandler(actuator_id, \"Goal_Position\", &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->addSyncReadHandler(ADDR_PRESENT_CURRENT_2,\n                                                    (LENGTH_PRESENT_CURRENT_2 + LENGTH_PRESENT_VELOCITY_2 + LENGTH_PRESENT_POSITION_2),\n                                                    &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\nbool JointDynamixelProfileControl::writeProfileValue(std::vector<uint8_t> actuator_id, STRING profile_mode, uint32_t value)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const char * char_profile_mode = profile_mode.c_str();\n\n  for (uint8_t num = 0; num < actuator_id.size(); num++)\n  {\n    result = dynamixel_workbench_->writeRegister(actuator_id.at(num), char_profile_mode, value, &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  return true;\n}\n\nbool JointDynamixelProfileControl::writeGoalProfilingControlValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  uint8_t id_array[actuator_id.size()];\n  int32_t goal_value[actuator_id.size()];\n\n  //add tarajectory eq.\n  for(uint8_t index = 0; index < actuator_id.size(); index++)\n  {\n    float result_position;\n    float time_control = control_loop_time_;       //ms\n\n    if(previous_goal_value_.find(actuator_id.at(index)) == previous_goal_value_.end())\n    {\n      previous_goal_value_.insert(std::make_pair(actuator_id.at(index), value_vector.at(index)));\n    }\n\n    result_position = value_vector.at(index).position + 3*(value_vector.at(index).velocity * (time_control))/2;\n\n    id_array[index] = actuator_id.at(index);\n    goal_value[index] = dynamixel_workbench_->convertRadian2Value(actuator_id.at(index), result_position);\n\n    previous_goal_value_[actuator_id.at(index)] = value_vector.at(index);\n  }\n\n  result = dynamixel_workbench_->syncWrite(SYNC_WRITE_HANDLER, id_array, actuator_id.size(), goal_value, 1, &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n  return true;\n}\n\nstd::vector<robotis_manipulator::ActuatorValue> JointDynamixelProfileControl::receiveAllDynamixelValue(std::vector<uint8_t> actuator_id)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  std::vector<robotis_manipulator::ActuatorValue> all_actuator;\n\n  uint8_t id_array[actuator_id.size()];\n  for (uint8_t index = 0; index < actuator_id.size(); index++)\n    id_array[index] = actuator_id.at(index);\n\n  int32_t get_current[actuator_id.size()];\n  int32_t get_velocity[actuator_id.size()];\n  int32_t get_position[actuator_id.size()];\n\n  result = dynamixel_workbench_->syncRead(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                          id_array,\n                                          actuator_id.size(),\n                                          &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                id_array,\n                                                actuator_id.size(),\n                                                ADDR_PRESENT_CURRENT_2,\n                                                LENGTH_PRESENT_CURRENT_2,\n                                                get_current,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                 id_array,\n                                                 actuator_id.size(),\n                                                ADDR_PRESENT_VELOCITY_2,\n                                                LENGTH_PRESENT_VELOCITY_2,\n                                                get_velocity,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                 id_array,\n                                                 actuator_id.size(),\n                                                ADDR_PRESENT_POSITION_2,\n                                                LENGTH_PRESENT_POSITION_2,\n                                                get_position,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  for (uint8_t index = 0; index < actuator_id.size(); index++)\n  {\n    robotis_manipulator::ActuatorValue actuator;\n    actuator.effort = dynamixel_workbench_->convertValue2Current(get_current[index]);\n    actuator.velocity = dynamixel_workbench_->convertValue2Velocity(actuator_id.at(index), get_velocity[index]);\n    actuator.position = dynamixel_workbench_->convertValue2Radian(actuator_id.at(index), get_position[index]);\n\n    all_actuator.push_back(actuator);\n  }\n\n  return all_actuator;\n}\n\n\n/*****************************************************************************\n** Tool Dynamixel Control Functions\n*****************************************************************************/\nvoid ToolDynamixel::init(uint8_t actuator_id, const void *arg)\n{\n  STRING *get_arg_ = (STRING *)arg;\n\n  bool result = ToolDynamixel::initialize(actuator_id ,get_arg_[0], get_arg_[1]);\n\n  if (result == false)\n    return;\n}\n\nvoid ToolDynamixel::setMode(const void *arg)\n{\n  bool result = false;\n// const char* log = NULL;\n\n  STRING *get_arg_ = (STRING *)arg;\n\n  if (get_arg_[0] == \"position_mode\" || get_arg_[0] == \"current_based_position_mode\")\n  {\n    result = ToolDynamixel::setOperatingMode(get_arg_[0]);\n    if (result == false)\n      return;\n  }\n  else\n  {\n    result = ToolDynamixel::writeProfileValue(get_arg_[0], std::atoi(get_arg_[1].c_str()));\n    if (result == false)\n      return;\n  }\n\n  result = ToolDynamixel::setSDKHandler();\n  if (result == false)\n    return;\n}\n\nuint8_t ToolDynamixel::getId()\n{\n  return dynamixel_.id.at(0);\n}\n\nvoid ToolDynamixel::enable()\n{\n  const char* log = NULL;\n  bool result = false;\n  \n  result = dynamixel_workbench_->torqueOn(dynamixel_.id.at(0), &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n  enabled_state_ = true;\n}\n\nvoid ToolDynamixel::disable()\n{\n  const char* log = NULL;\n  bool result = false;\n  \n  result = dynamixel_workbench_->torqueOff(dynamixel_.id.at(0), &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n  enabled_state_ = false;\n}\n\nbool ToolDynamixel::sendToolActuatorValue(robotis_manipulator::ActuatorValue value)\n{\n  return ToolDynamixel::writeGoalPosition(value.position);\n}\n\nrobotis_manipulator::ActuatorValue ToolDynamixel::receiveToolActuatorValue()\n{\n  robotis_manipulator::ActuatorValue result;\n  result.position = ToolDynamixel::receiveDynamixelValue();\n  result.velocity = 0.0;\n  result.acceleration = 0.0;\n  result.effort = 0.0;\n  return result;\n}\n\n\n/*****************************************************************************\n** Functions called in Tool Dynamixel Profile Control Functions\n*****************************************************************************/\nbool ToolDynamixel::initialize(uint8_t actuator_id, STRING dxl_device_name, STRING dxl_baud_rate)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  STRING return_delay_time_st = \"Return_Delay_Time\";\n  const char * return_delay_time_char = return_delay_time_st.c_str();\n\n  dynamixel_.id.push_back(actuator_id);\n  dynamixel_.num = 1;\n\n  dynamixel_workbench_ = new DynamixelWorkbench;\n\n  result = dynamixel_workbench_->init(dxl_device_name.c_str(), std::atoi(dxl_baud_rate.c_str()), &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  uint16_t get_model_number;\n  result = dynamixel_workbench_->ping(dynamixel_.id.at(0), &get_model_number, &log);\n  if (result == false)\n  {\n    log::error(log);\n    log::error(\"Please check your Dynamixel ID\");\n  }\n  else\n  {\n    char str[100];\n    sprintf(str, \"Tool Dynamixel ID : %d, Model Name :\", dynamixel_.id.at(0));\n    strcat(str, dynamixel_workbench_->getModelName(dynamixel_.id.at(0)));\n    log::println(str);\n\n    result = dynamixel_workbench_->setVelocityBasedProfile(dynamixel_.id.at(0), &log);\n    if(result == false)\n    {\n      log::error(log);\n      log::error(\"Please check your Dynamixel firmware version (v38~)\");\n    }\n\n    result = dynamixel_workbench_->writeRegister(dynamixel_.id.at(0), return_delay_time_char, 0, &log);\n    if (result == false)\n    {\n      log::error(log);\n      log::error(\"Please check your Dynamixel firmware version\");\n    }\n  }\n\n  return true;\n}\n\nbool ToolDynamixel::setOperatingMode(STRING dynamixel_mode)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const uint32_t velocity = 0;\n  const uint32_t acceleration = 0;\n  const uint32_t current = 200;\n\n  if (dynamixel_mode == \"position_mode\")\n  {\n    result = dynamixel_workbench_->jointMode(dynamixel_.id.at(0), velocity, acceleration, &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  else if (dynamixel_mode == \"current_based_position_mode\")\n  {\n    result = dynamixel_workbench_->currentBasedPositionMode(dynamixel_.id.at(0), current, &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  else\n  {\n    result = dynamixel_workbench_->jointMode(dynamixel_.id.at(0), velocity, acceleration, &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n\n  return true;\n}\n\nbool ToolDynamixel::writeProfileValue(STRING profile_mode, uint32_t value)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const char * char_profile_mode = profile_mode.c_str();\n\n  result = dynamixel_workbench_->writeRegister(dynamixel_.id.at(0), char_profile_mode, value, &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\nbool ToolDynamixel::setSDKHandler()\n{\n  bool result = false;\n  const char* log = NULL;\n\n  result = dynamixel_workbench_->addSyncWriteHandler(dynamixel_.id.at(0), \"Goal_Position\", &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->addSyncReadHandler(dynamixel_.id.at(0),\n                                                    \"Present_Position\", \n                                                    &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\nbool ToolDynamixel::writeGoalPosition(double radian)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  int32_t goal_position = 0;\n\n  goal_position = dynamixel_workbench_->convertRadian2Value(dynamixel_.id.at(0), radian);\n\n  result = dynamixel_workbench_->syncWrite(SYNC_WRITE_HANDLER, &goal_position, &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\ndouble ToolDynamixel::receiveDynamixelValue()\n{\n  bool result = false;\n  const char* log = NULL;\n\n  int32_t get_value = 0;\n  uint8_t id_array[1] = {dynamixel_.id.at(0)};\n\n  result = dynamixel_workbench_->syncRead(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT, \n                                          id_array,\n                                          (uint8_t)1,\n                                          &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT, \n                                            id_array,\n                                            (uint8_t)1,\n                                            &get_value, \n                                            &log);\n  if (result == false)\n  {\n    log::error(log);\n  } \n\n  return dynamixel_workbench_->convertValue2Radian(dynamixel_.id.at(0), get_value);\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/linear_libs/src/linear_kinematics.cpp",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include \"../include/linear_libs/linear_kinematics.h\"\n\nusing namespace robotis_manipulator;\nusing namespace linear_kinematics;\n\n/*****************************************************************************\n** Kinematics Solver \n*****************************************************************************/\nvoid SolverUsingGeometry::setOption(const void *arg) {}\n\nEigen::MatrixXd SolverUsingGeometry::jacobian(Manipulator *manipulator, Name tool_name)\n{\n  return Eigen::MatrixXd::Identity(6, manipulator->getDOF());\n}\n\nvoid SolverUsingGeometry::solveForwardKinematics(Manipulator *manipulator)\n{\n  forwardKinematicsSolverUsingGeometry(manipulator, manipulator->getWorldChildName());\n}\n\nbool SolverUsingGeometry::solveInverseKinematics(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue> *goal_joint_value)\n{\n  return inverseKinematicsSolverUsingGeometry(manipulator, tool_name, target_pose, goal_joint_value);\n}\n\n/*****************************************************************************\n** Private\n*****************************************************************************/\nvoid SolverUsingGeometry::forwardKinematicsSolverUsingGeometry(Manipulator *manipulator, Name component_name)  \n{\n  // // Get my name, parent name and number of children \n  // Name my_name = component_name;\n  // Name parent_name = manipulator->getComponentParentName(my_name);\n  // int8_t number_of_child = manipulator->getComponentChildName(my_name).size();\n\n  // // Define my & parent position and orientation \n  // Eigen::Vector3d parent_position_from_world;\n  // Eigen::Matrix3d parent_orientation_from_world; \n  // Eigen::Vector3d my_position_from_world;\n  // Eigen::Matrix3d my_orientation_from_world; \n\n \n  // // Get parent position and orientation \n  // // when parent is world\n  // if (parent_name == manipulator->getWorldName())\n  // {\n  //   parent_position_from_world = manipulator->getWorldPosition();                 \n  //   parent_orientation_from_world = manipulator->getWorldOrientation();\n  // }\n  // // when parent is not world\n  // else\n  // {\n  //   parent_position_from_world = manipulator->getComponentPositionFromWorld(parent_name); \n  //   parent_orientation_from_world = manipulator->getComponentOrientationFromWorld(parent_name);\n  // }\n\n  // Calculate my position and orientation \n  double wheel_radius = 0.02818;\n  double motor_angle[4];\n  // std::vector<Name> child_name = manipulator->getComponentChildName(my_name);\n\n  // for (int8_t index=0; index<2; index++) \n  // {\n  motor_angle[0] = manipulator->getJointValue(\"joint1\").position;\n  motor_angle[1] = manipulator->getJointValue(\"joint2\").position;\n  motor_angle[2] = manipulator->getJointValue(\"joint3\").position;\n  motor_angle[3] = manipulator->getJointValue(\"tool\").position;\n  // }\n\n  Eigen::Vector3d pos_joint1;\n  Eigen::Vector3d pos_joint2;\n  Eigen::Vector3d pos_joint3;\n  Eigen::Vector3d pos_joint4;\n\n  pos_joint1 << wheel_radius * motor_angle[0], 0                            , 0;\n  pos_joint2 << wheel_radius * motor_angle[0], wheel_radius * motor_angle[1], 0;\n  pos_joint3 << wheel_radius * motor_angle[0], wheel_radius * motor_angle[1], -0,01;\n  pos_joint4 << wheel_radius * motor_angle[0], wheel_radius * motor_angle[1], wheel_radius * motor_angle[2];\n\n  // Set my position and orientation \n  manipulator->setComponentPositionFromWorld(\"joint1\", pos_joint1);\n  manipulator->setComponentPositionFromWorld(\"joint2\", pos_joint2);\n  manipulator->setComponentPositionFromWorld(\"joint3\", pos_joint3);\n  manipulator->setComponentPositionFromWorld(\"tool\", pos_joint4);\n\n  Eigen::Vector3d pos_joint11, pos_joint22, pos_joint33;\n  pos_joint11 = manipulator->getComponentPositionFromWorld(\"joint1\");\n  pos_joint22 = manipulator->getComponentPositionFromWorld(\"joint2\");\n  pos_joint33 = manipulator->getComponentPositionFromWorld(\"joint3\");\n\n  // Serial.print(pos_joint11(0));\n  // Serial.print(pos_joint11(1));\n  // Serial.print(pos_joint11(2));\n  // Serial.print(pos_joint22(0));\n  // Serial.print(pos_joint22(1));\n  // Serial.print(pos_joint22(2));\n  // Serial.print(pos_joint33(0));\n  // Serial.print(pos_joint33(1));\n  // Serial.println(pos_joint33(2));\n  // Serial.flush();\n\n}\n\nbool SolverUsingGeometry::inverseKinematicsSolverUsingGeometry(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue> *goal_joint_value)\n{\n  JointValue target_angle[3];       \n  std::vector<JointValue> target_joint_value;\n  double x_limit = 0.300;\n  double y_limit = 0.300;\n  double z_limit = 0.300;\n  double wheel_radius = 0.02818;\n\n  Manipulator _manipulator = *manipulator;\n\n  // // Set x, y, z limits \n  // if (target_pose.position(0) >  x_limit) target_pose.position(0) = x_limit;\n  // if (target_pose.position(0) < -x_limit) target_pose.position(0) = -x_limit;\n  // if (target_pose.position(1) >  y_limit) target_pose.position(1) = y_limit;\n  // if (target_pose.position(1) < -y_limit) target_pose.position(1) = -y_limit;\n  // if (target_pose.position(2) >  z_limit) target_pose.position(1) = z_limit;\n  // if (target_pose.position(2) <  0      ) target_pose.position(1) = 0;\n\n  for (int8_t index=0; index<3; index++) \n  {\n    // Calculate the target pose of each joint.\n    target_angle[index].position = target_pose.kinematic.position(index) / wheel_radius;\n\n    // Calculate the target pose of each joint.\n    target_joint_value.push_back(target_angle[index]);\n    // *goal_joint_value.push_back(target_angle[index]);    <-- can be like this???\n  }\n  *goal_joint_value = target_joint_value;\n\n  return true;\n}\n\n\n\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/linear_libs.h",
    "content": "#include \"linear_libs/include/linear_libs/linear.h\""
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/open_manipulator_libs/include/open_manipulator_libs/custom_trajectory.h",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef CUSTOM_TRAJECTORY_H_\n#define CUSTOM_TRAJECTORY_H_\n\n#if defined(__OPENCR__)\n  #include <RobotisManipulator.h>\n#else\n  #include <robotis_manipulator/robotis_manipulator.h>\n#endif\n\nusing namespace robotis_manipulator;\nusing namespace Eigen;\n\nnamespace custom_trajectory\n{\n  \nenum AXIS{\n\tX_AXIS,\n\tY_AXIS,\n\tZ_AXIS,\n};\n\n\n/*****************************************************************************\n** Line\n*****************************************************************************/\nclass Line : public robotis_manipulator::CustomTaskTrajectory\n{\nprivate:\n  TaskWaypoint start_pose_;\n  TaskWaypoint goal_pose_;\n\n  double acc_dec_time_;\n  double move_time_;\n  std::vector<double> vel_max_;\n\npublic:\n\tLine() {}\n\tvirtual ~Line() {}\n\n  void initLine(double move_time, TaskWaypoint start, TaskWaypoint delta);\n  TaskWaypoint drawLine(double time_var);\n\n  virtual void setOption(const void *arg);\n  virtual void makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg);\n  virtual TaskWaypoint getTaskWaypoint(double tick);\n};\n\n\n/*****************************************************************************\n** Circle\n*****************************************************************************/\nclass Circle : public robotis_manipulator::CustomTaskTrajectory\n{\nprivate:\n  robotis_manipulator::MinimumJerk path_generator_;\n  VectorXd coefficient_;\n\n  TaskWaypoint start_pose_;\n  TaskWaypoint goal_pose_;\n\n  double radius_;\n  double start_angular_position_;\n  double revolution_;\n\npublic:\n\tCircle() {}\n\tvirtual ~Circle() {}\n\n  void initCircle(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position);\n  TaskWaypoint drawCircle(double time_var);\n\n  virtual void setOption(const void *arg);\n  virtual void makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg);\n  virtual TaskWaypoint getTaskWaypoint(double tick);\n};\n\n\n/*****************************************************************************\n** Rhombus\n*****************************************************************************/\nclass Rhombus : public robotis_manipulator::CustomTaskTrajectory\n{\nprivate:\n  robotis_manipulator::MinimumJerk path_generator_;\n  VectorXd coefficient_;\n\n  TaskWaypoint start_pose_;\n  TaskWaypoint goal_pose_;\n\n  double radius_;\n  double start_angular_position_;\n  double revolution_;\n\npublic:\n\tRhombus() {}\n\tvirtual ~Rhombus() {}\n\n  void initRhombus(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position);\n  TaskWaypoint drawRhombus(double time_var);\n\n  virtual void setOption(const void *arg);\n  virtual void makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg);\n  virtual TaskWaypoint getTaskWaypoint(double tick);\n};\n\n\n/*****************************************************************************\n** Heart\n*****************************************************************************/\nclass Heart : public robotis_manipulator::CustomTaskTrajectory\n{\nprivate:\n  robotis_manipulator::MinimumJerk path_generator_;\n  VectorXd coefficient_;\n\n  TaskWaypoint start_pose_;\n  TaskWaypoint goal_pose_;\n\n  double radius_;\n  double start_angular_position_;\n  double revolution_;\n\npublic:\n\tHeart() {}\n\tvirtual ~Heart() {}\n\n  void initHeart(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position);\n  TaskWaypoint drawHeart(double tick);\n\n  virtual void setOption(const void *arg);\n  virtual void makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg);\n  virtual TaskWaypoint getTaskWaypoint(double tick);\n};\n\n\n} // namespace CUSTOM_TRAJECTORY\n#endif // CUSTOM_TRAJECTORY_H_\n\n\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/open_manipulator_libs/include/open_manipulator_libs/dynamixel.h",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef DYNAMIXEL_H_\n#define DYNAMIXEL_H_\n\n#if defined(__OPENCR__)\n  #include <RobotisManipulator.h>\n  #include <DynamixelWorkbench.h>\n#else\n  #include <robotis_manipulator/robotis_manipulator.h>\n  #include <dynamixel_workbench_toolbox/dynamixel_workbench.h>\n#endif\n\nnamespace dynamixel\n{\n\n#define SYNC_WRITE_HANDLER 0\n#define SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT 0\n\n//#define CONTROL_LOOP_TIME 10;    //ms\n\n// Protocol 2.0\n#define ADDR_PRESENT_CURRENT_2 126\n#define ADDR_PRESENT_VELOCITY_2 128\n#define ADDR_PRESENT_POSITION_2 132\n#define ADDR_VELOCITY_TRAJECTORY_2 136\n#define ADDR_POSITION_TRAJECTORY_2 140\n#define ADDR_PROFILE_ACCELERATION_2 108\n#define ADDR_PROFILE_VELOCITY_2 112\n#define ADDR_GOAL_POSITION_2 116\n\n\n#define LENGTH_PRESENT_CURRENT_2 2\n#define LENGTH_PRESENT_VELOCITY_2 4\n#define LENGTH_PRESENT_POSITION_2 4\n#define LENGTH_VELOCITY_TRAJECTORY_2 4\n#define LENGTH_POSITION_TRAJECTORY_2 4\n#define LENGTH_PROFILE_ACCELERATION_2 4\n#define LENGTH_PROFILE_VELOCITY_2 4\n#define LENGTH_GOAL_POSITION_2 4\n\n\n// Protocol 1.0\n#define ADDR_PRESENT_CURRENT_1 = 40;\n#define ADDR_PRESENT_VELOCITY_1 = 38;\n#define ADDR_PRESENT_POSITION_1 = 36;\n\n#define LENGTH_PRESENT_CURRENT_1 = 2;\n#define LENGTH_PRESENT_VELOCITY_1 = 2;\n#define LENGTH_PRESENT_POSITION_1 = 2;\n\ntypedef struct\n{\n  std::vector<uint8_t> id;\n  uint8_t num;\n} Joint;\n\nclass JointDynamixel : public robotis_manipulator::JointActuator\n{\nprivate:\n  DynamixelWorkbench *dynamixel_workbench_;\n  Joint dynamixel_;\n\npublic:\n  JointDynamixel(){}\n  virtual ~JointDynamixel(){}\n\n\n  /*****************************************************************************\n  ** Joint Dynamixel Control Functions\n  *****************************************************************************/\n  virtual void init(std::vector<uint8_t> actuator_id, const void *arg);\n  virtual void setMode(std::vector<uint8_t> actuator_id, const void *arg);\n  virtual std::vector<uint8_t> getId();\n\n  virtual void enable();\n  virtual void disable();\n\n  virtual bool sendJointActuatorValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector);\n  virtual std::vector<robotis_manipulator::ActuatorValue> receiveJointActuatorValue(std::vector<uint8_t> actuator_id);\n\n\n  /*****************************************************************************\n  ** Functions called in Joint Dynamixel Control Functions\n  *****************************************************************************/\n  bool initialize(std::vector<uint8_t> actuator_id, STRING dxl_device_name, STRING dxl_baud_rate);\n  bool setOperatingMode(std::vector<uint8_t> actuator_id, STRING dynamixel_mode = \"position_mode\");\n  bool setSDKHandler(uint8_t actuator_id);\n  bool writeProfileValue(std::vector<uint8_t> actuator_id, STRING profile_mode, uint32_t value);\n  bool writeGoalPosition(std::vector<uint8_t> actuator_id, std::vector<double> radian_vector);\n  std::vector<robotis_manipulator::ActuatorValue> receiveAllDynamixelValue(std::vector<uint8_t> actuator_id);\n};\n\nclass JointDynamixelProfileControl : public robotis_manipulator::JointActuator\n{\nprivate:\n  DynamixelWorkbench *dynamixel_workbench_;\n  Joint dynamixel_;\n  float control_loop_time_; // unit: ms\n  std::map<uint8_t, robotis_manipulator::ActuatorValue> previous_goal_value_;\n\npublic:\n  JointDynamixelProfileControl(float control_loop_time = 0.010);\n  virtual ~JointDynamixelProfileControl(){}\n\n\n  /*****************************************************************************\n  ** Joint Dynamixel Profile Control Functions\n  *****************************************************************************/\n  virtual void init(std::vector<uint8_t> actuator_id, const void *arg);\n  virtual void setMode(std::vector<uint8_t> actuator_id, const void *arg);\n  virtual std::vector<uint8_t> getId();\n\n  virtual void enable();\n  virtual void disable();\n\n  virtual bool sendJointActuatorValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector);\n  virtual std::vector<robotis_manipulator::ActuatorValue> receiveJointActuatorValue(std::vector<uint8_t> actuator_id);\n\n\n  /*****************************************************************************\n  ** Functions called in Joint Dynamixel Profile Control Functions\n  *****************************************************************************/\n  bool initialize(std::vector<uint8_t> actuator_id, STRING dxl_device_name, STRING dxl_baud_rate);\n  bool setOperatingMode(std::vector<uint8_t> actuator_id, STRING dynamixel_mode = \"position_mode\");\n  bool setSDKHandler(uint8_t actuator_id);\n  bool writeProfileValue(std::vector<uint8_t> actuator_id, STRING profile_mode, uint32_t value);\n  bool writeGoalProfilingControlValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector);\n  std::vector<robotis_manipulator::ActuatorValue> receiveAllDynamixelValue(std::vector<uint8_t> actuator_id);\n};\n\nclass GripperDynamixel : public robotis_manipulator::ToolActuator\n{\n private:\n  DynamixelWorkbench *dynamixel_workbench_;\n  Joint dynamixel_;\n\n public:\n  GripperDynamixel() {}\n  virtual ~GripperDynamixel() {}\n\n\n  /*****************************************************************************\n  ** Tool Dynamixel Control Functions\n  *****************************************************************************/\n  virtual void init(uint8_t actuator_id, const void *arg);\n  virtual void setMode(const void *arg);\n  virtual uint8_t getId();\n\n  virtual void enable();\n  virtual void disable();\n\n  virtual bool sendToolActuatorValue(robotis_manipulator::ActuatorValue value);\n  virtual robotis_manipulator::ActuatorValue receiveToolActuatorValue();\n\n\n  /*****************************************************************************\n  ** Functions called in Tool Dynamixel Profile Control Functions\n  *****************************************************************************/\n  bool initialize(uint8_t actuator_id, STRING dxl_device_name, STRING dxl_baud_rate);\n  bool setOperatingMode(STRING dynamixel_mode = \"position_mode\");\n  bool writeProfileValue(STRING profile_mode, uint32_t value);\n  bool setSDKHandler();\n  bool writeGoalPosition(double radian);\n  double receiveDynamixelValue();\n};\n\n} // namespace DYNAMIXEL\n#endif // DYNAMIXEL_H_\n\n\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/open_manipulator_libs/include/open_manipulator_libs/kinematics.h",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef KINEMATICS_H_\n#define KINEMATICS_H_\n\n#if defined(__OPENCR__)\n  #include <RobotisManipulator.h>\n#else\n  #include <robotis_manipulator/robotis_manipulator.h>\n#endif\n\n//#define KINEMATICS_DEBUG\n\nusing namespace Eigen;\nusing namespace robotis_manipulator;\n\nnamespace kinematics\n{\n  \n/*****************************************************************************\n** Kinematics Solver Using Chain Rule and Jacobian\n*****************************************************************************/\nclass SolverUsingCRAndJacobian : public robotis_manipulator::Kinematics\n{\nprivate:\n  void forwardSolverUsingChainRule(Manipulator *manipulator, Name component_name);\n  bool inverseSolverUsingJacobian(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue>* goal_joint_value);\n\npublic:\n  SolverUsingCRAndJacobian(){}\n  virtual ~SolverUsingCRAndJacobian(){}\n\n  virtual void setOption(const void *arg);\n  virtual MatrixXd jacobian(Manipulator *manipulator, Name tool_name);\n  virtual void solveForwardKinematics(Manipulator *manipulator);\n  virtual bool solveInverseKinematics(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue>* goal_joint_value);\n};\n\n\n/*****************************************************************************\n** Kinematics Solver Using Chain Rule and Singularity Robust Jacobian\n*****************************************************************************/\nclass SolverUsingCRAndSRJacobian : public robotis_manipulator::Kinematics\n{\nprivate:\n  void forwardSolverUsingChainRule(Manipulator *manipulator, Name component_name);\n  bool inverseSolverUsingSRJacobian(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue>* goal_joint_value);\n\npublic:\n  SolverUsingCRAndSRJacobian(){}\n  virtual ~SolverUsingCRAndSRJacobian(){}\n\n  virtual void setOption(const void *arg);\n  virtual MatrixXd jacobian(Manipulator *manipulator, Name tool_name);\n  virtual void solveForwardKinematics(Manipulator *manipulator);\n  virtual bool solveInverseKinematics(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue>* goal_joint_value);\n};\n\n\n/*****************************************************************************\n** Kinematics Solver Using Chain Rule and Singularity Robust Position Only Jacobian\n*****************************************************************************/\nclass SolverUsingCRAndSRPositionOnlyJacobian : public robotis_manipulator::Kinematics\n{\nprivate:\n  void forwardSolverUsingChainRule(Manipulator *manipulator, Name component_name);\n  bool inverseSolverUsingPositionOnlySRJacobian(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue>* goal_joint_value);\n\npublic:\n  SolverUsingCRAndSRPositionOnlyJacobian(){}\n  virtual ~SolverUsingCRAndSRPositionOnlyJacobian(){}\n\n  virtual void setOption(const void *arg);\n  virtual MatrixXd jacobian(Manipulator *manipulator, Name tool_name);\n  virtual void solveForwardKinematics(Manipulator *manipulator);\n  virtual bool solveInverseKinematics(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue>* goal_joint_value);\n};\n\n\n/*****************************************************************************\n** Kinematics Solver Customized for OpenManipulator Chain\n*****************************************************************************/\nclass SolverCustomizedforOMChain : public robotis_manipulator::Kinematics\n{\nprivate:\n  void forwardSolverUsingChainRule(Manipulator *manipulator, Name component_name);\n  bool chainCustomInverseKinematics(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue>* goal_joint_value);\n\npublic:\n  SolverCustomizedforOMChain(){}\n  virtual ~SolverCustomizedforOMChain(){}\n\n  virtual void setOption(const void *arg);\n  virtual MatrixXd jacobian(Manipulator *manipulator, Name tool_name);\n  virtual void solveForwardKinematics(Manipulator *manipulator);\n  virtual bool solveInverseKinematics(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue>* goal_joint_value);\n};\n\n} // namespace KINEMATICS\n\n\n#endif // KINEMATICS_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/open_manipulator_libs/include/open_manipulator_libs/open_manipulator.h",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef OPEN_MANIPULTOR_H_\n#define OPEN_MANIPULTOR_H_\n\n#include \"custom_trajectory.h\"\n#include \"dynamixel.h\"\n#include \"kinematics.h\"\n\n#define CUSTOM_TRAJECTORY_SIZE 4\n#define CUSTOM_TRAJECTORY_LINE    \"custom_trajectory_line\"\n#define CUSTOM_TRAJECTORY_CIRCLE  \"custom_trajectory_circle\"\n#define CUSTOM_TRAJECTORY_RHOMBUS \"custom_trajectory_rhombus\"\n#define CUSTOM_TRAJECTORY_HEART   \"custom_trajectory_heart\"\n\n#define JOINT_DYNAMIXEL \"joint_dxl\"\n#define TOOL_DYNAMIXEL  \"tool_dxl\"\n\n#define X_AXIS robotis_manipulator::math::vector3(1.0, 0.0, 0.0)\n#define Y_AXIS robotis_manipulator::math::vector3(0.0, 1.0, 0.0)\n#define Z_AXIS robotis_manipulator::math::vector3(0.0, 0.0, 1.0)\n\nclass OpenManipulator : public robotis_manipulator::RobotisManipulator\n{\n  \nprivate:\n  robotis_manipulator::Kinematics *kinematics_;\n  robotis_manipulator::JointActuator *joint_;\n  robotis_manipulator::ToolActuator *tool_;\n  robotis_manipulator::CustomTaskTrajectory *custom_trajectory_[CUSTOM_TRAJECTORY_SIZE];\n  uint8_t joint1_id, joint2_id, joint3_id, joint4_id, gripper_id;\n\npublic:\n  OpenManipulator();\n  virtual ~OpenManipulator();\n\n  void initOpenManipulator(bool using_actual_robot_state, \n                           STRING usb_port = \"/dev/ttyUSB0\", \n                           STRING baud_rate = \"1000000\", \n                           float control_loop_time = 0.010);\n  void processOpenManipulator(double present_time);\n  \n  // Allow to use a custom joint ID for OpenMANIPULATOR-X\n  void setOpenManipulatorCustomJointId(uint8_t joint1, uint8_t joint2, uint8_t joint3, uint8_t joint4, uint8_t gripper);\n};\n\n#endif // OPEN_MANIPULTOR_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/open_manipulator_libs/src/custom_trajectory.cpp",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include \"../include/open_manipulator_libs/custom_trajectory.h\"\n\nusing namespace custom_trajectory;\nusing namespace Eigen;\n\n\n/*****************************************************************************\n** Line\n*****************************************************************************/\nvoid Line::initLine(double move_time, TaskWaypoint start, TaskWaypoint delta)\n{\n  move_time_ = move_time;\n  acc_dec_time_ = move_time_ * 0.2;\n  vel_max_.resize(3);\n\n  TaskWaypoint start_to_goal;\n\n  start_pose_ = start;\n\n  goal_pose_ .kinematic.orientation = start_pose_.kinematic.orientation;\n  goal_pose_ .kinematic.position = start.kinematic.position + delta.kinematic.position;\n\n  vel_max_.at(X_AXIS) = delta.kinematic.position(X_AXIS)/(move_time_ - acc_dec_time_);\n  vel_max_.at(Y_AXIS) = delta.kinematic.position(Y_AXIS)/(move_time_ - acc_dec_time_);\n  vel_max_.at(Z_AXIS) = delta.kinematic.position(Z_AXIS)/(move_time_ - acc_dec_time_);\n}\n\nTaskWaypoint Line::drawLine(double time_var)\n{\n  TaskWaypoint pose;\n\n  if(acc_dec_time_ >= time_var)\n  {\n    pose.kinematic.position(X_AXIS) = 0.5*vel_max_.at(X_AXIS)*pow(time_var, 2)/acc_dec_time_ + start_pose_.kinematic.position(X_AXIS);\n    pose.kinematic.position(Y_AXIS) = 0.5*vel_max_.at(Y_AXIS)*pow(time_var, 2)/acc_dec_time_ + start_pose_.kinematic.position(Y_AXIS);\n    pose.kinematic.position(Z_AXIS) = 0.5*vel_max_.at(Z_AXIS)*pow(time_var, 2)/acc_dec_time_ + start_pose_.kinematic.position(Z_AXIS);\n  }\n  else if(time_var > acc_dec_time_ && (move_time_ - acc_dec_time_) >= time_var )\n  {\n    pose.kinematic.position(X_AXIS) = vel_max_.at(X_AXIS)*(time_var-(acc_dec_time_*0.5)) + start_pose_.kinematic.position(X_AXIS);\n    pose.kinematic.position(Y_AXIS) = vel_max_.at(Y_AXIS)*(time_var-(acc_dec_time_*0.5)) + start_pose_.kinematic.position(Y_AXIS);\n    pose.kinematic.position(Z_AXIS) = vel_max_.at(Z_AXIS)*(time_var-(acc_dec_time_*0.5)) + start_pose_.kinematic.position(Z_AXIS);\n  }\n  else if(time_var > (move_time_ - acc_dec_time_) && (time_var < move_time_))\n  {\n    pose.kinematic.position(X_AXIS) = goal_pose_.kinematic.position(X_AXIS) - vel_max_.at(X_AXIS)*0.5/acc_dec_time_*(pow((move_time_-time_var),2));\n    pose.kinematic.position(Y_AXIS) = goal_pose_.kinematic.position(Y_AXIS) - vel_max_.at(Y_AXIS)*0.5/acc_dec_time_*(pow((move_time_-time_var),2));\n    pose.kinematic.position(Z_AXIS) = goal_pose_.kinematic.position(Z_AXIS) - vel_max_.at(Z_AXIS)*0.5/acc_dec_time_*(pow((move_time_-time_var),2));\n  }\n  else if(time_var <= move_time_)\n  {\n    pose.kinematic.position(X_AXIS) = goal_pose_.kinematic.position(X_AXIS);\n    pose.kinematic.position(Y_AXIS) = goal_pose_.kinematic.position(Y_AXIS);\n    pose.kinematic.position(Z_AXIS) = goal_pose_.kinematic.position(Z_AXIS);\n  }\n\n  pose.kinematic.orientation = start_pose_.kinematic.orientation;\n  pose.dynamic.linear.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.linear.acceleration = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.acceleration = Eigen::Vector3d::Zero(3);\n\n  return pose;\n}\n\nTaskWaypoint Line::getTaskWaypoint(double tick)\n{\n  return drawLine(tick);\n}\n\n\nvoid Line::makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg)\n{\n  TaskWaypoint *c_arg = (TaskWaypoint *)arg;\n  initLine(move_time, start, c_arg[0]);\n}\nvoid Line::setOption(const void *arg) {}\n\n\n/*****************************************************************************\n** Circle\n*****************************************************************************/\nvoid Circle::initCircle(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position)\n{\n  start_pose_ = start;\n\n  radius_ = radius;\n  revolution_ = revolution;\n  start_angular_position_ = start_angular_position;\n\n  Point drawingStart, drawingGoal;\n\n  drawingStart.position = 0.0;\n  drawingStart.velocity = 0.0;\n  drawingStart.acceleration = 0.0;\n  drawingStart.effort = 0.0;\n\n  drawingGoal.position = revolution_ * 2*M_PI;\n  drawingGoal.velocity = 0.0;\n  drawingGoal.acceleration = 0.0;\n  drawingGoal.effort = 0.0;\n\n  path_generator_.calcCoefficient(drawingStart, drawingGoal, move_time);\n  coefficient_ = path_generator_.getCoefficient();\n}\n\nTaskWaypoint Circle::drawCircle(double tick)\n{\n  // get time variable\n  double get_time_var = 0.0;\n\n  get_time_var = coefficient_(0) +\n                 coefficient_(1) * pow(tick, 1) +\n                 coefficient_(2) * pow(tick, 2) +\n                 coefficient_(3) * pow(tick, 3) +\n                 coefficient_(4) * pow(tick, 4) +\n                 coefficient_(5) * pow(tick, 5);\n\n  // set drawing trajectory\n  TaskWaypoint pose;\n\n  double diff_pose[2];\n\n  diff_pose[0] = (cos(get_time_var)-1)*cos(start_angular_position_) - sin(get_time_var)*sin(start_angular_position_);\n  diff_pose[1] = (cos(get_time_var)-1)*sin(start_angular_position_) + sin(get_time_var)*cos(start_angular_position_);\n\n  pose.kinematic.position(X_AXIS) = start_pose_.kinematic.position(X_AXIS) + radius_ * diff_pose[0];\n  pose.kinematic.position(Y_AXIS) = start_pose_.kinematic.position(Y_AXIS) + radius_ * diff_pose[1];\n  pose.kinematic.position(Z_AXIS) = start_pose_.kinematic.position(Z_AXIS);\n\n  pose.kinematic.orientation = start_pose_.kinematic.orientation;\n\n  pose.dynamic.linear.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.linear.acceleration = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.acceleration = Eigen::Vector3d::Zero(3);\n\n  return pose;\n}\n\nTaskWaypoint Circle::getTaskWaypoint(double tick)\n{\n  return drawCircle(tick);\n}\n\nvoid Circle::makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg)\n{\n  double *get_arg_ = (double *)arg;\n  initCircle(move_time, start, get_arg_[0], get_arg_[1], get_arg_[2]);\n}\n\nvoid Circle::setOption(const void *arg){}\n\n\n/*****************************************************************************\n** Rhombus\n*****************************************************************************/\nvoid Rhombus::initRhombus(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position)\n{\n  start_pose_ = start;\n\n  radius_ = radius;\n  revolution_ = revolution;\n  start_angular_position_ = start_angular_position;\n\n  Point drawingStart, drawingGoal;\n\n  drawingStart.position = 0.0;\n  drawingStart.velocity = 0.0;\n  drawingStart.acceleration = 0.0;\n  drawingStart.effort = 0.0;\n\n  drawingGoal.position = revolution_ * 2*M_PI;\n  drawingGoal.velocity = 0.0;\n  drawingGoal.acceleration = 0.0;\n  drawingGoal.effort = 0.0;\n\n  path_generator_.calcCoefficient(drawingStart, drawingGoal, move_time);\n  coefficient_ = path_generator_.getCoefficient();\n}\n\n\nTaskWaypoint Rhombus::drawRhombus(double tick)\n{\n  // get time variable\n  double get_time_var = 0.0;\n\n  get_time_var = coefficient_(0) +\n                 coefficient_(1) * pow(tick, 1) +\n                 coefficient_(2) * pow(tick, 2) +\n                 coefficient_(3) * pow(tick, 3) +\n                 coefficient_(4) * pow(tick, 4) +\n                 coefficient_(5) * pow(tick, 5); \n\n  // set drawing trajectory\n  TaskWaypoint pose;\n  double diff_pose[2];\n  double traj[2];\n\n  while(true)\n  {\n    if (get_time_var < PI*2) break;\n    get_time_var = get_time_var - PI*2;\n  }\n\n  if (get_time_var >= 0 && get_time_var < PI/2){\n    traj[0] = - get_time_var / (PI/2);\n    traj[1] = - get_time_var / (PI/2);\n  } else if (get_time_var >= PI/2 && get_time_var < PI){\n    traj[0] = - get_time_var / (PI/2);\n    traj[1] = get_time_var / (PI/2) - 2;\n  } else if (get_time_var >= PI && get_time_var < PI*3/2){\n    traj[0] = get_time_var / (PI/2) - 4;\n    traj[1] = get_time_var / (PI/2) - 2;\n  } else {\n    traj[0] = get_time_var / (PI/2) - 4;\n    traj[1] = - get_time_var / (PI/2) + 4;\n  }\n  \n\n  diff_pose[0] = traj[0]*cos(start_angular_position_) - traj[1]*sin(start_angular_position_);\n  diff_pose[1] = traj[0]*sin(start_angular_position_) + traj[1]*cos(start_angular_position_);\n\n  pose.kinematic.position(X_AXIS) = start_pose_.kinematic.position(X_AXIS) + radius_ * diff_pose[0];\n  pose.kinematic.position(Y_AXIS) = start_pose_.kinematic.position(Y_AXIS) + radius_ * diff_pose[1];\n  pose.kinematic.position(Z_AXIS) = start_pose_.kinematic.position(Z_AXIS);\n\n  pose.kinematic.orientation = start_pose_.kinematic.orientation;\n\n  pose.dynamic.linear.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.linear.acceleration = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.acceleration = Eigen::Vector3d::Zero(3);\n\n  return pose;\n}\n\n\nvoid Rhombus::makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg)\n{\n  double *get_arg_ = (double *)arg;\n  initRhombus(move_time, start, get_arg_[0], get_arg_[1], get_arg_[2]);\n}\n\nTaskWaypoint Rhombus::getTaskWaypoint(double tick)\n{\n  return drawRhombus(tick);\n}\nvoid Rhombus::setOption(const void *arg){}\n\n\n/*****************************************************************************\n** Heart\n*****************************************************************************/\nvoid Heart::initHeart(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position)\n{\n  start_pose_ = start;\n\n  radius_ = radius;\n  revolution_ = revolution;\n  start_angular_position_ = start_angular_position;\n\n  Point drawingStart, drawingGoal;\n\n  drawingStart.position = 0.0;\n  drawingStart.velocity = 0.0;\n  drawingStart.acceleration = 0.0;\n  drawingStart.effort = 0.0;\n\n  drawingGoal.position = revolution_ * 2*M_PI;\n  drawingGoal.velocity = 0.0;\n  drawingGoal.acceleration = 0.0;\n  drawingGoal.effort = 0.0;\n\n  path_generator_.calcCoefficient(drawingStart, drawingGoal, move_time);\n  coefficient_ = path_generator_.getCoefficient();\n}\n\nTaskWaypoint Heart::drawHeart(double tick)\n{\n  // get time variable\n  double get_time_var = 0.0;\n\n  get_time_var = coefficient_(0) +\n                 coefficient_(1) * pow(tick, 1) +\n                 coefficient_(2) * pow(tick, 2) +\n                 coefficient_(3) * pow(tick, 3) +\n                 coefficient_(4) * pow(tick, 4) +\n                 coefficient_(5) * pow(tick, 5);\n\n  // set drawing trajectory\n  TaskWaypoint pose;\n  double diff_pose[2];\n  double traj[2];\n\n\tdouble shift_offset = - 5.0;\n\n  traj[0] = (shift_offset + (13*cos(get_time_var) - 5*cos(2*get_time_var) - 2*cos(3*get_time_var) - cos(4*get_time_var))) / 16;\n  traj[1] = (16*sin(get_time_var)*sin(get_time_var)*sin(get_time_var)) / 16;\n\n  diff_pose[0] = traj[0]*cos(start_angular_position_) - traj[1]*sin(start_angular_position_);\n  diff_pose[1] = traj[0]*sin(start_angular_position_) + traj[1]*cos(start_angular_position_);\n\n  pose.kinematic.position(X_AXIS) = start_pose_.kinematic.position(X_AXIS) + radius_ * diff_pose[0];\n  pose.kinematic.position(Y_AXIS) = start_pose_.kinematic.position(Y_AXIS) + radius_ * diff_pose[1];\n  pose.kinematic.position(Z_AXIS) = start_pose_.kinematic.position(Z_AXIS);\n\n  pose.kinematic.orientation = start_pose_.kinematic.orientation;\n\n  pose.dynamic.linear.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.linear.acceleration = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.acceleration = Eigen::Vector3d::Zero(3);\n\n  return pose;\n}\n\nvoid Heart::makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg)\n{\n  double *get_arg_ = (double *)arg;\n  initHeart(move_time, start, get_arg_[0], get_arg_[1], get_arg_[2]);\n}\nvoid Heart::setOption(const void *arg){}\n\nTaskWaypoint Heart::getTaskWaypoint(double tick)\n{\n  return drawHeart(tick);\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/open_manipulator_libs/src/dynamixel.cpp",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include \"../include/open_manipulator_libs/dynamixel.h\"\n\nusing namespace dynamixel;\nusing namespace robotis_manipulator;\n\n/*****************************************************************************\n** Joint Dynamixel Control Functions\n*****************************************************************************/\nvoid JointDynamixel::init(std::vector<uint8_t> actuator_id, const void *arg)\n{\n  STRING *get_arg_ = (STRING *)arg;\n\n  bool result = JointDynamixel::initialize(actuator_id ,get_arg_[0], get_arg_[1]);\n\n  if (result == false)\n    return;\n}\n\nvoid JointDynamixel::setMode(std::vector<uint8_t> actuator_id, const void *arg)\n{\n  bool result = false;\n  // const char* log = NULL;\n\n  STRING *get_arg_ = (STRING *)arg;\n\n  if (get_arg_[0] == \"position_mode\" || get_arg_[0] == \"current_based_position_mode\")\n  {\n    result = JointDynamixel::setOperatingMode(actuator_id, get_arg_[0]);\n    if (result == false)\n      return;\n\n    result = JointDynamixel::setSDKHandler(actuator_id.at(0));\n    if (result == false)\n      return;\n  }\n  else\n  {\n    result = JointDynamixel::writeProfileValue(actuator_id, get_arg_[0], std::atoi(get_arg_[1].c_str()));\n    if (result == false)\n      return;\n  }\n  return;\n}\n\nstd::vector<uint8_t> JointDynamixel::getId()\n{\n  return dynamixel_.id;\n}\n\nvoid JointDynamixel::enable()\n{\n  const char* log = NULL;\n  bool result = false;\n  \n  for (uint32_t index = 0; index < dynamixel_.num; index++)\n  {\n    result = dynamixel_workbench_->torqueOn(dynamixel_.id.at(index), &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  enabled_state_ = true;\n}\n\nvoid JointDynamixel::disable()\n{\n  const char* log = NULL;\n  bool result = false;\n  \n  for (uint32_t index = 0; index < dynamixel_.num; index++)\n  {\n    result = dynamixel_workbench_->torqueOff(dynamixel_.id.at(index), &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  enabled_state_ = false;\n}\n\nbool JointDynamixel::sendJointActuatorValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector)\n{\n  bool result = false;\n\n  std::vector<double> radian_vector;\n  for(uint32_t index = 0; index < value_vector.size(); index++)\n  {\n    radian_vector.push_back(value_vector.at(index).position);\n  }\n  result = JointDynamixel::writeGoalPosition(actuator_id, radian_vector);\n  if (result == false)\n    return false;\n\n  return true;\n}\n\nstd::vector<robotis_manipulator::ActuatorValue> JointDynamixel::receiveJointActuatorValue(std::vector<uint8_t> actuator_id)\n{\n  return JointDynamixel::receiveAllDynamixelValue(actuator_id);\n}\n\n\n/*****************************************************************************\n** Functions called in Joint Dynamixel Control Functions\n*****************************************************************************/\nbool JointDynamixel::initialize(std::vector<uint8_t> actuator_id, STRING dxl_device_name, STRING dxl_baud_rate)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  STRING return_delay_time_st = \"Return_Delay_Time\";\n  const char * return_delay_time_char = return_delay_time_st.c_str();\n\n  dynamixel_.id = actuator_id;\n  dynamixel_.num = actuator_id.size();\n\n  dynamixel_workbench_ = new DynamixelWorkbench;\n\n  result = dynamixel_workbench_->init(dxl_device_name.c_str(), std::atoi(dxl_baud_rate.c_str()), &log);\n  if (result == false)\n  {\n    log::error(log);\n  }    \n\n  uint16_t get_model_number;\n  for (uint8_t index = 0; index < dynamixel_.num; index++)\n  {\n    uint8_t id = dynamixel_.id.at(index);\n    result = dynamixel_workbench_->ping(id, &get_model_number, &log);\n\n    if (result == false)\n    {\n      log::error(log);\n      log::error(\"Please check your Dynamixel ID\");\n    }\n    else\n    {\n      char str[100];\n      sprintf(str, \"Joint Dynamixel ID : %d, Model Name : %s\", id, dynamixel_workbench_->getModelName(id));\n      log::println(str);\n\n      result = dynamixel_workbench_->setVelocityBasedProfile(id, &log);\n      if(result == false)\n      {\n        log::error(log);\n        log::error(\"Please check your Dynamixel firmware version (v38~)\");\n      }\n\n      result = dynamixel_workbench_->writeRegister(id, return_delay_time_char, 0, &log);\n      if (result == false)\n      {\n        log::error(log);\n        log::error(\"Please check your Dynamixel firmware version\");\n      }\n    }\n  }\n  return true;\n}\n\nbool JointDynamixel::setOperatingMode(std::vector<uint8_t> actuator_id, STRING dynamixel_mode)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const uint32_t velocity = 0;\n  const uint32_t acceleration = 0;\n  const uint32_t current = 0;\n\n  if (dynamixel_mode == \"position_mode\")\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->jointMode(actuator_id.at(num), velocity, acceleration, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n  else if (dynamixel_mode == \"current_based_position_mode\")\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->currentBasedPositionMode(actuator_id.at(num), current, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n  else\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->jointMode(actuator_id.at(num), velocity, acceleration, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n\n  return true;\n}\n\nbool JointDynamixel::setSDKHandler(uint8_t actuator_id)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  result = dynamixel_workbench_->addSyncWriteHandler(actuator_id, \"Goal_Position\", &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->addSyncReadHandler(ADDR_PRESENT_CURRENT_2, \n                                                    (LENGTH_PRESENT_CURRENT_2 + LENGTH_PRESENT_VELOCITY_2 + LENGTH_PRESENT_POSITION_2), \n                                                    &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\nbool JointDynamixel::writeProfileValue(std::vector<uint8_t> actuator_id, STRING profile_mode, uint32_t value)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const char * char_profile_mode = profile_mode.c_str();\n\n  for (uint8_t num = 0; num < actuator_id.size(); num++)\n  {\n    result = dynamixel_workbench_->writeRegister(actuator_id.at(num), char_profile_mode, value, &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n\n  return true;\n}\n\nbool JointDynamixel::writeGoalPosition(std::vector<uint8_t> actuator_id, std::vector<double> radian_vector)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  uint8_t id_array[actuator_id.size()];\n  int32_t goal_position[actuator_id.size()];\n\n  for (uint8_t index = 0; index < actuator_id.size(); index++)\n  {\n    id_array[index] = actuator_id.at(index);\n    goal_position[index] = dynamixel_workbench_->convertRadian2Value(actuator_id.at(index), radian_vector.at(index));\n  }\n\n  result = dynamixel_workbench_->syncWrite(SYNC_WRITE_HANDLER, id_array, actuator_id.size(), goal_position, 1, &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\nstd::vector<robotis_manipulator::ActuatorValue> JointDynamixel::receiveAllDynamixelValue(std::vector<uint8_t> actuator_id)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  std::vector<robotis_manipulator::ActuatorValue> all_actuator;\n\n  uint8_t id_array[actuator_id.size()];\n  for (uint8_t index = 0; index < actuator_id.size(); index++)\n    id_array[index] = actuator_id.at(index);\n\n  int32_t get_current[actuator_id.size()];\n  int32_t get_velocity[actuator_id.size()];\n  int32_t get_position[actuator_id.size()];\n\n  result = dynamixel_workbench_->syncRead(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                          id_array,\n                                          actuator_id.size(),\n                                          &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                id_array,\n                                                actuator_id.size(),\n                                                ADDR_PRESENT_CURRENT_2,\n                                                LENGTH_PRESENT_CURRENT_2,\n                                                get_current,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                 id_array,\n                                                 actuator_id.size(),\n                                                ADDR_PRESENT_VELOCITY_2,\n                                                LENGTH_PRESENT_VELOCITY_2,\n                                                get_velocity,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                 id_array,\n                                                 actuator_id.size(),\n                                                ADDR_PRESENT_POSITION_2,\n                                                LENGTH_PRESENT_POSITION_2,\n                                                get_position,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  for (uint8_t index = 0; index < actuator_id.size(); index++)\n  {\n    robotis_manipulator::ActuatorValue actuator;\n    actuator.effort = dynamixel_workbench_->convertValue2Current(get_current[index]);\n    actuator.velocity = dynamixel_workbench_->convertValue2Velocity(actuator_id.at(index), get_velocity[index]);\n    actuator.position = dynamixel_workbench_->convertValue2Radian(actuator_id.at(index), get_position[index]);\n\n    all_actuator.push_back(actuator);\n  }\n\n  return all_actuator;\n}\n\n\n/*****************************************************************************\n** Joint Dynamixel Profile Control Functions\n*****************************************************************************/\nJointDynamixelProfileControl::JointDynamixelProfileControl(float control_loop_time)\n{\n  control_loop_time_ = control_loop_time;\n}\n\nvoid JointDynamixelProfileControl::init(std::vector<uint8_t> actuator_id, const void *arg)\n{\n  STRING *get_arg_ = (STRING *)arg;\n\n  bool result = JointDynamixelProfileControl::initialize(actuator_id ,get_arg_[0], get_arg_[1]);\n\n  if (result == false)\n    return;\n}\n\nvoid JointDynamixelProfileControl::setMode(std::vector<uint8_t> actuator_id, const void *arg)\n{\n  bool result = false;\n  // const char* log = NULL;\n\n  STRING *get_arg_ = (STRING *)arg;\n\n  if (get_arg_[0] == \"position_mode\" || get_arg_[0] == \"current_based_position_mode\")\n  {\n    result = JointDynamixelProfileControl::setOperatingMode(actuator_id, get_arg_[0]);\n    if (result == false)\n      return;\n\n    result = JointDynamixelProfileControl::setSDKHandler(actuator_id.at(0));\n    if (result == false)\n      return;\n  }\n  else\n  {\n    result = JointDynamixelProfileControl::writeProfileValue(actuator_id, get_arg_[0], std::atoi(get_arg_[1].c_str()));\n    if (result == false)\n      return;\n  }\n  return;\n}\n\nstd::vector<uint8_t> JointDynamixelProfileControl::getId()\n{\n  return dynamixel_.id;\n}\n\nvoid JointDynamixelProfileControl::enable()\n{\n  const char* log = NULL;\n  bool result = false;\n\n  for (uint32_t index = 0; index < dynamixel_.num; index++)\n  {\n    result = dynamixel_workbench_->torqueOn(dynamixel_.id.at(index), &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  enabled_state_ = true;\n}\n\nvoid JointDynamixelProfileControl::disable()\n{\n  const char* log = NULL;\n  bool result = false;\n\n  for (uint32_t index = 0; index < dynamixel_.num; index++)\n  {\n    result = dynamixel_workbench_->torqueOff(dynamixel_.id.at(index), &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  enabled_state_ = false;\n}\n\nbool JointDynamixelProfileControl::sendJointActuatorValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector)\n{\n  bool result = false;\n\n  result = JointDynamixelProfileControl::writeGoalProfilingControlValue(actuator_id, value_vector);\n  if (result == false)\n    return false;\n\n  return true;\n}\n\nstd::vector<robotis_manipulator::ActuatorValue> JointDynamixelProfileControl::receiveJointActuatorValue(std::vector<uint8_t> actuator_id)\n{\n  return JointDynamixelProfileControl::receiveAllDynamixelValue(actuator_id);\n}\n\n\n/*****************************************************************************\n** Functions called in Joint Dynamixel Profile Control Functions\n*****************************************************************************/\nbool JointDynamixelProfileControl::initialize(std::vector<uint8_t> actuator_id, STRING dxl_device_name, STRING dxl_baud_rate)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  STRING return_delay_time_st = \"Return_Delay_Time\";\n  const char * return_delay_time_char = return_delay_time_st.c_str();\n\n  dynamixel_.id = actuator_id;\n  dynamixel_.num = actuator_id.size();\n\n  dynamixel_workbench_ = new DynamixelWorkbench;\n\n  result = dynamixel_workbench_->init(dxl_device_name.c_str(), std::atoi(dxl_baud_rate.c_str()), &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  uint16_t get_model_number;\n  for (uint8_t index = 0; index < dynamixel_.num; index++)\n  {\n    uint8_t id = dynamixel_.id.at(index);\n    result = dynamixel_workbench_->ping(id, &get_model_number, &log);\n\n    if (result == false)\n    {\n      log::error(log);\n      log::error(\"Please check your Dynamixel ID\");\n    }\n    else\n    {\n      char str[100];\n      sprintf(str, \"Joint Dynamixel ID : %d, Model Name : %s\", id, dynamixel_workbench_->getModelName(id));\n      log::println(str);\n\n      result = dynamixel_workbench_->setTimeBasedProfile(id, &log);\n      if(result == false)\n      {\n        log::error(log);\n        log::error(\"Please check your Dynamixel firmware version (v38~)\");\n      }\n\n      result = dynamixel_workbench_->writeRegister(id, return_delay_time_char, 0, &log);\n      if (result == false)\n      {\n        log::error(log);\n        log::error(\"Please check your Dynamixel firmware version\");\n      }\n    }\n  }\n  return true;\n}\n\nbool JointDynamixelProfileControl::setOperatingMode(std::vector<uint8_t> actuator_id, STRING dynamixel_mode)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const uint32_t velocity = uint32_t(control_loop_time_*1000) * 3;\n  const uint32_t acceleration = uint32_t(control_loop_time_*1000);\n  const uint32_t current = 0;\n\n  if (dynamixel_mode == \"position_mode\")\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->jointMode(actuator_id.at(num), velocity, acceleration, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n  else if (dynamixel_mode == \"current_based_position_mode\")\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->currentBasedPositionMode(actuator_id.at(num), current, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n  else\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->jointMode(actuator_id.at(num), velocity, acceleration, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n\n  return true;\n}\n\nbool JointDynamixelProfileControl::setSDKHandler(uint8_t actuator_id)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  result = dynamixel_workbench_->addSyncWriteHandler(actuator_id, \"Goal_Position\", &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->addSyncReadHandler(ADDR_PRESENT_CURRENT_2,\n                                                    (LENGTH_PRESENT_CURRENT_2 + LENGTH_PRESENT_VELOCITY_2 + LENGTH_PRESENT_POSITION_2),\n                                                    &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\nbool JointDynamixelProfileControl::writeProfileValue(std::vector<uint8_t> actuator_id, STRING profile_mode, uint32_t value)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const char * char_profile_mode = profile_mode.c_str();\n\n  for (uint8_t num = 0; num < actuator_id.size(); num++)\n  {\n    result = dynamixel_workbench_->writeRegister(actuator_id.at(num), char_profile_mode, value, &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  return true;\n}\n\nbool JointDynamixelProfileControl::writeGoalProfilingControlValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  uint8_t id_array[actuator_id.size()];\n  int32_t goal_value[actuator_id.size()];\n\n  //add tarajectory eq.\n  for(uint8_t index = 0; index < actuator_id.size(); index++)\n  {\n    float result_position;\n    float time_control = control_loop_time_;       //ms\n\n    if(previous_goal_value_.find(actuator_id.at(index)) == previous_goal_value_.end())\n    {\n      previous_goal_value_.insert(std::make_pair(actuator_id.at(index), value_vector.at(index)));\n    }\n\n    result_position = value_vector.at(index).position + 3*(value_vector.at(index).velocity * (time_control))/2;\n\n    id_array[index] = actuator_id.at(index);\n    goal_value[index] = dynamixel_workbench_->convertRadian2Value(actuator_id.at(index), result_position);\n\n    previous_goal_value_[actuator_id.at(index)] = value_vector.at(index);\n  }\n\n  result = dynamixel_workbench_->syncWrite(SYNC_WRITE_HANDLER, id_array, actuator_id.size(), goal_value, 1, &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n  return true;\n}\n\nstd::vector<robotis_manipulator::ActuatorValue> JointDynamixelProfileControl::receiveAllDynamixelValue(std::vector<uint8_t> actuator_id)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  std::vector<robotis_manipulator::ActuatorValue> all_actuator;\n\n  uint8_t id_array[actuator_id.size()];\n  for (uint8_t index = 0; index < actuator_id.size(); index++)\n    id_array[index] = actuator_id.at(index);\n\n  int32_t get_current[actuator_id.size()];\n  int32_t get_velocity[actuator_id.size()];\n  int32_t get_position[actuator_id.size()];\n\n  result = dynamixel_workbench_->syncRead(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                          id_array,\n                                          actuator_id.size(),\n                                          &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                id_array,\n                                                actuator_id.size(),\n                                                ADDR_PRESENT_CURRENT_2,\n                                                LENGTH_PRESENT_CURRENT_2,\n                                                get_current,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                 id_array,\n                                                 actuator_id.size(),\n                                                ADDR_PRESENT_VELOCITY_2,\n                                                LENGTH_PRESENT_VELOCITY_2,\n                                                get_velocity,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                 id_array,\n                                                 actuator_id.size(),\n                                                ADDR_PRESENT_POSITION_2,\n                                                LENGTH_PRESENT_POSITION_2,\n                                                get_position,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  for (uint8_t index = 0; index < actuator_id.size(); index++)\n  {\n    robotis_manipulator::ActuatorValue actuator;\n    actuator.effort = dynamixel_workbench_->convertValue2Current(get_current[index]);\n    actuator.velocity = dynamixel_workbench_->convertValue2Velocity(actuator_id.at(index), get_velocity[index]);\n    actuator.position = dynamixel_workbench_->convertValue2Radian(actuator_id.at(index), get_position[index]);\n\n    all_actuator.push_back(actuator);\n  }\n\n  return all_actuator;\n}\n\n\n/*****************************************************************************\n** Tool Dynamixel Control Functions\n*****************************************************************************/\nvoid GripperDynamixel::init(uint8_t actuator_id, const void *arg)\n{\n  STRING *get_arg_ = (STRING *)arg;\n\n  bool result = GripperDynamixel::initialize(actuator_id ,get_arg_[0], get_arg_[1]);\n\n  if (result == false)\n    return;\n}\n\nvoid GripperDynamixel::setMode(const void *arg)\n{\n  bool result = false;\n// const char* log = NULL;\n\n  STRING *get_arg_ = (STRING *)arg;\n\n  if (get_arg_[0] == \"position_mode\" || get_arg_[0] == \"current_based_position_mode\")\n  {\n    result = GripperDynamixel::setOperatingMode(get_arg_[0]);\n    if (result == false)\n      return;\n  }\n  else\n  {\n    result = GripperDynamixel::writeProfileValue(get_arg_[0], std::atoi(get_arg_[1].c_str()));\n    if (result == false)\n      return;\n  }\n\n  result = GripperDynamixel::setSDKHandler();\n  if (result == false)\n    return;\n}\n\nuint8_t GripperDynamixel::getId()\n{\n  return dynamixel_.id.at(0);\n}\n\nvoid GripperDynamixel::enable()\n{\n  const char* log = NULL;\n  bool result = false;\n  \n  result = dynamixel_workbench_->torqueOn(dynamixel_.id.at(0), &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n  enabled_state_ = true;\n}\n\nvoid GripperDynamixel::disable()\n{\n  const char* log = NULL;\n  bool result = false;\n  \n  result = dynamixel_workbench_->torqueOff(dynamixel_.id.at(0), &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n  enabled_state_ = false;\n}\n\nbool GripperDynamixel::sendToolActuatorValue(robotis_manipulator::ActuatorValue value)\n{\n  return GripperDynamixel::writeGoalPosition(value.position);\n}\n\nrobotis_manipulator::ActuatorValue GripperDynamixel::receiveToolActuatorValue()\n{\n  robotis_manipulator::ActuatorValue result;\n  result.position = GripperDynamixel::receiveDynamixelValue();\n  result.velocity = 0.0;\n  result.acceleration = 0.0;\n  result.effort = 0.0;\n  return result;\n}\n\n\n/*****************************************************************************\n** Functions called in Tool Dynamixel Profile Control Functions\n*****************************************************************************/\nbool GripperDynamixel::initialize(uint8_t actuator_id, STRING dxl_device_name, STRING dxl_baud_rate)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  STRING return_delay_time_st = \"Return_Delay_Time\";\n  const char * return_delay_time_char = return_delay_time_st.c_str();\n\n  dynamixel_.id.push_back(actuator_id);\n  dynamixel_.num = 1;\n\n  dynamixel_workbench_ = new DynamixelWorkbench;\n\n  result = dynamixel_workbench_->init(dxl_device_name.c_str(), std::atoi(dxl_baud_rate.c_str()), &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  uint16_t get_model_number;\n  result = dynamixel_workbench_->ping(dynamixel_.id.at(0), &get_model_number, &log);\n  if (result == false)\n  {\n    log::error(log);\n    log::error(\"Please check your Dynamixel ID\");\n  }\n  else\n  {\n    char str[100];\n    sprintf(str, \"Gripper Dynamixel ID : %d, Model Name :\", dynamixel_.id.at(0));\n    strcat(str, dynamixel_workbench_->getModelName(dynamixel_.id.at(0)));\n    log::println(str);\n\n    result = dynamixel_workbench_->setVelocityBasedProfile(dynamixel_.id.at(0), &log);\n    if(result == false)\n    {\n      log::error(log);\n      log::error(\"Please check your Dynamixel firmware version (v38~)\");\n    }\n\n    result = dynamixel_workbench_->writeRegister(dynamixel_.id.at(0), return_delay_time_char, 0, &log);\n    if (result == false)\n    {\n      log::error(log);\n      log::error(\"Please check your Dynamixel firmware version\");\n    }\n  }\n\n  return true;\n}\n\nbool GripperDynamixel::setOperatingMode(STRING dynamixel_mode)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const uint32_t velocity = 0;\n  const uint32_t acceleration = 0;\n  const uint32_t current = 200;\n\n  if (dynamixel_mode == \"position_mode\")\n  {\n    result = dynamixel_workbench_->jointMode(dynamixel_.id.at(0), velocity, acceleration, &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  else if (dynamixel_mode == \"current_based_position_mode\")\n  {\n    result = dynamixel_workbench_->currentBasedPositionMode(dynamixel_.id.at(0), current, &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  else\n  {\n    result = dynamixel_workbench_->jointMode(dynamixel_.id.at(0), velocity, acceleration, &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n\n  return true;\n}\n\nbool GripperDynamixel::writeProfileValue(STRING profile_mode, uint32_t value)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const char * char_profile_mode = profile_mode.c_str();\n\n  result = dynamixel_workbench_->writeRegister(dynamixel_.id.at(0), char_profile_mode, value, &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\nbool GripperDynamixel::setSDKHandler()\n{\n  bool result = false;\n  const char* log = NULL;\n\n  result = dynamixel_workbench_->addSyncWriteHandler(dynamixel_.id.at(0), \"Goal_Position\", &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->addSyncReadHandler(dynamixel_.id.at(0),\n                                                    \"Present_Position\", \n                                                    &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\nbool GripperDynamixel::writeGoalPosition(double radian)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  int32_t goal_position = 0;\n\n  goal_position = dynamixel_workbench_->convertRadian2Value(dynamixel_.id.at(0), radian);\n\n  result = dynamixel_workbench_->syncWrite(SYNC_WRITE_HANDLER, &goal_position, &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\ndouble GripperDynamixel::receiveDynamixelValue()\n{\n  bool result = false;\n  const char* log = NULL;\n\n  int32_t get_value = 0;\n  uint8_t id_array[1] = {dynamixel_.id.at(0)};\n\n  result = dynamixel_workbench_->syncRead(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT, \n                                          id_array,\n                                          (uint8_t)1,\n                                          &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT, \n                                            id_array,\n                                            (uint8_t)1,\n                                            &get_value, \n                                            &log);\n  if (result == false)\n  {\n    log::error(log);\n  } \n\n  return dynamixel_workbench_->convertValue2Radian(dynamixel_.id.at(0), get_value);\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/open_manipulator_libs/src/kinematics.cpp",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include \"../include/open_manipulator_libs/kinematics.h\"\n\nusing namespace robotis_manipulator;\nusing namespace kinematics;\n\n\n/*****************************************************************************\n** Kinematics Solver Using Chain Rule and Jacobian\n*****************************************************************************/\nvoid SolverUsingCRAndJacobian::setOption(const void *arg){}\n\nEigen::MatrixXd SolverUsingCRAndJacobian::jacobian(Manipulator *manipulator, Name tool_name)\n{\n  Eigen::MatrixXd jacobian = Eigen::MatrixXd::Identity(6, manipulator->getDOF());\n\n  Eigen::Vector3d joint_axis = Eigen::Vector3d::Zero(3);\n\n  Eigen::Vector3d position_changed = Eigen::Vector3d::Zero(3);\n  Eigen::Vector3d orientation_changed = Eigen::Vector3d::Zero(3);\n  Eigen::VectorXd pose_changed = Eigen::VectorXd::Zero(6);\n\n  //////////////////////////////////////////////////////////////////////////////////\n\n  int8_t index = 0;\n  Name my_name =  manipulator->getWorldChildName();\n\n  for (int8_t size = 0; size < manipulator->getDOF(); size++)\n  {\n    Name parent_name = manipulator->getComponentParentName(my_name);\n    if (parent_name == manipulator->getWorldName())\n    {\n      joint_axis = manipulator->getWorldOrientation() * manipulator->getAxis(my_name);\n    }\n    else\n    {\n      joint_axis = manipulator->getComponentOrientationFromWorld(parent_name) * manipulator->getAxis(my_name);\n    }\n\n    position_changed = math::skewSymmetricMatrix(joint_axis) *\n                       (manipulator->getComponentPositionFromWorld(tool_name) - manipulator->getComponentPositionFromWorld(my_name));\n    orientation_changed = joint_axis;\n\n    pose_changed << position_changed(0),\n        position_changed(1),\n        position_changed(2),\n        orientation_changed(0),\n        orientation_changed(1),\n        orientation_changed(2);\n\n    jacobian.col(index) = pose_changed;\n    index++;\n    my_name = manipulator->getComponentChildName(my_name).at(0); // Get Child name which has active joint\n  }\n  return jacobian;\n}\n\nvoid SolverUsingCRAndJacobian::solveForwardKinematics(Manipulator *manipulator)\n{\n  forwardSolverUsingChainRule(manipulator, manipulator->getWorldChildName());\n}\n\nbool SolverUsingCRAndJacobian::solveInverseKinematics(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue> *goal_joint_value)\n{\n  return inverseSolverUsingJacobian(manipulator, tool_name, target_pose, goal_joint_value);\n}\n\n\n//private\nvoid SolverUsingCRAndJacobian::forwardSolverUsingChainRule(Manipulator *manipulator, Name component_name)\n{\n  Name my_name = component_name;\n  Name parent_name = manipulator->getComponentParentName(my_name);\n  int8_t number_of_child = manipulator->getComponentChildName(my_name).size();\n\n  Pose parent_pose_value;\n  Pose my_pose_value;\n\n  //Get Parent Pose\n  if (parent_name == manipulator->getWorldName())\n  {\n    parent_pose_value = manipulator->getWorldPose();\n  }\n  else\n  {\n    parent_pose_value = manipulator->getComponentPoseFromWorld(parent_name);\n  }\n\n  //position\n  my_pose_value.kinematic.position = parent_pose_value.kinematic.position\n                                   + (parent_pose_value.kinematic.orientation * manipulator->getComponentRelativePositionFromParent(my_name));\n  //orientation\n  my_pose_value.kinematic.orientation = parent_pose_value.kinematic.orientation * math::rodriguesRotationMatrix(manipulator->getAxis(my_name), manipulator->getJointPosition(my_name));\n  //linear velocity\n  my_pose_value.dynamic.linear.velocity = math::vector3(0.0, 0.0, 0.0);\n  //angular velocity\n  my_pose_value.dynamic.angular.velocity = math::vector3(0.0, 0.0, 0.0);\n  //linear acceleration\n  my_pose_value.dynamic.linear.acceleration = math::vector3(0.0, 0.0, 0.0);\n  //angular acceleration\n  my_pose_value.dynamic.angular.acceleration = math::vector3(0.0, 0.0, 0.0);\n\n  manipulator->setComponentPoseFromWorld(my_name, my_pose_value);\n\n  for (int8_t index = 0; index < number_of_child; index++)\n  {\n    Name child_name = manipulator->getComponentChildName(my_name).at(index);\n    forwardSolverUsingChainRule(manipulator, child_name);\n  }\n}\n\nbool SolverUsingCRAndJacobian::inverseSolverUsingJacobian(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue> *goal_joint_value)\n{\n  const double lambda = 0.7;\n  const int8_t iteration = 10;\n\n  Manipulator _manipulator = *manipulator;\n\n  Eigen::MatrixXd jacobian = Eigen::MatrixXd::Identity(6, _manipulator.getDOF());\n\n  Eigen::VectorXd pose_changed = Eigen::VectorXd::Zero(6);\n  Eigen::VectorXd delta_angle = Eigen::VectorXd::Zero(_manipulator.getDOF());\n\n  for (int8_t count = 0; count < iteration; count++)\n  {\n    //Forward kinematics solve\n    solveForwardKinematics(&_manipulator);\n    //Get jacobian\n    jacobian = this->jacobian(&_manipulator, tool_name);\n\n    //Pose Difference\n    pose_changed = math::poseDifference(target_pose.kinematic.position, _manipulator.getComponentPositionFromWorld(tool_name),\n                                           target_pose.kinematic.orientation, _manipulator.getComponentOrientationFromWorld(tool_name));\n\n    //pose sovler success\n    if (pose_changed.norm() < 1E-6)\n    {\n      *goal_joint_value = _manipulator.getAllActiveJointValue();\n      for(int8_t index = 0; index < _manipulator.getDOF(); index++)\n      {\n        goal_joint_value->at(index).velocity = 0.0;\n        goal_joint_value->at(index).acceleration = 0.0;\n        goal_joint_value->at(index).effort = 0.0;\n      }\n      return true;\n    }\n\n    //get delta angle\n    ColPivHouseholderQR<MatrixXd> dec(jacobian);\n    delta_angle = lambda * dec.solve(pose_changed);\n\n    //set changed angle\n    std::vector<double> changed_angle;\n    for(int8_t index = 0; index < _manipulator.getDOF(); index++)\n      changed_angle.push_back(_manipulator.getAllActiveJointPosition().at(index) + delta_angle(index));\n    _manipulator.setAllActiveJointPosition(changed_angle);\n  }\n  *goal_joint_value = {};\n  return false;\n}\n\n\n/*****************************************************************************\n** Kinematics Solver Using Chain Rule and Singularity Robust Jacobian\n*****************************************************************************/\nvoid SolverUsingCRAndSRJacobian::setOption(const void *arg){}\n\nEigen::MatrixXd SolverUsingCRAndSRJacobian::jacobian(Manipulator *manipulator, Name tool_name)\n{\n  Eigen::MatrixXd jacobian = Eigen::MatrixXd::Identity(6, manipulator->getDOF());\n\n  Eigen::Vector3d joint_axis = Eigen::Vector3d::Zero(3);\n\n  Eigen::Vector3d position_changed = Eigen::Vector3d::Zero(3);\n  Eigen::Vector3d orientation_changed = Eigen::Vector3d::Zero(3);\n  Eigen::VectorXd pose_changed = Eigen::VectorXd::Zero(6);\n\n  //////////////////////////////////////////////////////////////////////////////////\n\n  int8_t index = 0;\n  Name my_name =  manipulator->getWorldChildName();\n\n  for (int8_t size = 0; size < manipulator->getDOF(); size++)\n  {\n    Name parent_name = manipulator->getComponentParentName(my_name);\n    if (parent_name == manipulator->getWorldName())\n    {\n      joint_axis = manipulator->getWorldOrientation() * manipulator->getAxis(my_name);\n    }\n    else\n    {\n      joint_axis = manipulator->getComponentOrientationFromWorld(parent_name) * manipulator->getAxis(my_name);\n    }\n\n    position_changed = math::skewSymmetricMatrix(joint_axis) *\n                       (manipulator->getComponentPositionFromWorld(tool_name) - manipulator->getComponentPositionFromWorld(my_name));\n    orientation_changed = joint_axis;\n\n    pose_changed << position_changed(0),\n        position_changed(1),\n        position_changed(2),\n        orientation_changed(0),\n        orientation_changed(1),\n        orientation_changed(2);\n\n    jacobian.col(index) = pose_changed;\n    index++;\n    my_name = manipulator->getComponentChildName(my_name).at(0); // Get Child name which has active joint\n  }\n  return jacobian;\n}\n\nvoid SolverUsingCRAndSRJacobian::solveForwardKinematics(Manipulator *manipulator)\n{\n  forwardSolverUsingChainRule(manipulator, manipulator->getWorldChildName());\n}\n\nbool SolverUsingCRAndSRJacobian::solveInverseKinematics(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue> *goal_joint_value)\n{\n  return inverseSolverUsingSRJacobian(manipulator, tool_name, target_pose, goal_joint_value);\n}\n\n\n//private\nvoid SolverUsingCRAndSRJacobian::forwardSolverUsingChainRule(Manipulator *manipulator, Name component_name)\n{\n  Name my_name = component_name;\n  Name parent_name = manipulator->getComponentParentName(my_name);\n  int8_t number_of_child = manipulator->getComponentChildName(my_name).size();\n\n  Pose parent_pose_value;\n  Pose my_pose_value;\n\n  //Get Parent Pose\n  if (parent_name == manipulator->getWorldName())\n  {\n    parent_pose_value = manipulator->getWorldPose();\n  }\n  else\n  {\n    parent_pose_value = manipulator->getComponentPoseFromWorld(parent_name);\n  }\n\n  //position\n  my_pose_value.kinematic.position = parent_pose_value.kinematic.position\n                                   + (parent_pose_value.kinematic.orientation * manipulator->getComponentRelativePositionFromParent(my_name));\n  //orientation\n  my_pose_value.kinematic.orientation = parent_pose_value.kinematic.orientation * math::rodriguesRotationMatrix(manipulator->getAxis(my_name), manipulator->getJointPosition(my_name));\n  //linear velocity\n  my_pose_value.dynamic.linear.velocity = math::vector3(0.0, 0.0, 0.0);\n  //angular velocity\n  my_pose_value.dynamic.angular.velocity = math::vector3(0.0, 0.0, 0.0);\n  //linear acceleration\n  my_pose_value.dynamic.linear.acceleration = math::vector3(0.0, 0.0, 0.0);\n  //angular acceleration\n  my_pose_value.dynamic.angular.acceleration = math::vector3(0.0, 0.0, 0.0);\n\n  manipulator->setComponentPoseFromWorld(my_name, my_pose_value);\n\n  for (int8_t index = 0; index < number_of_child; index++)\n  {\n    Name child_name = manipulator->getComponentChildName(my_name).at(index);\n    forwardSolverUsingChainRule(manipulator, child_name);\n  }\n}\n\nbool SolverUsingCRAndSRJacobian::inverseSolverUsingSRJacobian(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue> *goal_joint_value)\n{\n  //manipulator\n  Manipulator _manipulator = *manipulator;\n\n  //solver parameter\n  double lambda = 0.0;\n  const double param = 0.002;\n  const int8_t iteration = 10;\n\n  const double gamma = 0.5;             //rollback delta\n\n  //sr sovler parameter\n  double wn_pos = 1 / 0.3;\n  double wn_ang = 1 / (2 * M_PI);\n  double pre_Ek = 0.0;\n  double new_Ek = 0.0;\n\n  Eigen::MatrixXd We(6, 6);\n  We << wn_pos, 0, 0, 0, 0, 0,\n      0, wn_pos, 0, 0, 0, 0,\n      0, 0, wn_pos, 0, 0, 0,\n      0, 0, 0, wn_ang, 0, 0,\n      0, 0, 0, 0, wn_ang, 0,\n      0, 0, 0, 0, 0, wn_ang;\n\n  Eigen::MatrixXd Wn = Eigen::MatrixXd::Identity(_manipulator.getDOF(), _manipulator.getDOF());\n\n  //jacobian\n  Eigen::MatrixXd jacobian = Eigen::MatrixXd::Identity(6, _manipulator.getDOF());\n  Eigen::MatrixXd sr_jacobian = Eigen::MatrixXd::Identity(_manipulator.getDOF(), _manipulator.getDOF());\n\n  //delta parameter\n  Eigen::VectorXd pose_changed = Eigen::VectorXd::Zero(6);\n  Eigen::VectorXd angle_changed = Eigen::VectorXd::Zero(_manipulator.getDOF());    //delta angle (dq)\n  Eigen::VectorXd gerr(_manipulator.getDOF());\n\n  //angle parameter\n  std::vector<double> present_angle;                                               //angle (q)\n  std::vector<double> set_angle;                                                   //set angle (q + dq)\n\n  ////////////////////////////solving//////////////////////////////////\n\n  solveForwardKinematics(&_manipulator);\n  //////////////checking dx///////////////\n  pose_changed = math::poseDifference(target_pose.kinematic.position, _manipulator.getComponentPositionFromWorld(tool_name), target_pose.kinematic.orientation, _manipulator.getComponentOrientationFromWorld(tool_name));\n  pre_Ek = pose_changed.transpose() * We * pose_changed;\n  ///////////////////////////////////////\n\n  /////////////////////////////debug/////////////////////////////////\n  #if defined(KINEMATICS_DEBUG)\n  Eigen::Vector3d target_orientation_rpy = math::convertRotationToRPY(target_pose.orientation);\n  Eigen::VectorXd debug_target_pose(6);\n  for(int t=0; t<3; t++)\n    debug_target_pose(t) = target_pose.position(t);\n  for(int t=0; t<3; t++)\n    debug_target_pose(t+3) = target_orientation_rpy(t);\n\n  Eigen::Vector3d present_position = _manipulator.getComponentPositionFromWorld(tool_name);\n  Eigen::MatrixXd present_orientation = _manipulator.getComponentOrientationFromWorld(tool_name);\n  Eigen::Vector3d present_orientation_rpy = math::convertRotationToRPY(present_orientation);\n  Eigen::VectorXd debug_present_pose(6);\n  for(int t=0; t<3; t++)\n    debug_present_pose(t) = present_position(t);\n  for(int t=0; t<3; t++)\n    debug_present_pose(t+3) = present_orientation_rpy(t);\n\n  log::println(\"------------------------------------\");\n  log::warn(\"iter : first\");\n  log::warn(\"Ek : \", pre_Ek*1000000000000);\n  log::println(\"tar_pose\");\n  log::println_VECTOR(debug_target_pose,16);\n  log::println(\"pre_pose\");\n  log::println_VECTOR(debug_present_pose,16);\n  log::println(\"delta_pose\");\n  log::println_VECTOR(debug_target_pose-debug_present_pose,16);\n  #endif\n  ////////////////////////////debug//////////////////////////////////\n\n  //////////////////////////solving loop///////////////////////////////\n  for (int8_t count = 0; count < iteration; count++)\n  {\n    //////////solve using jacobian//////////\n    jacobian = this->jacobian(&_manipulator, tool_name);\n    lambda = pre_Ek + param;\n\n    sr_jacobian = (jacobian.transpose() * We * jacobian) + (lambda * Wn);     //calculate sr_jacobian (J^T*we*J + lamda*Wn)\n    gerr = jacobian.transpose() * We * pose_changed;                          //calculate gerr (J^T*we) dx\n\n    ColPivHouseholderQR<Eigen::MatrixXd> dec(sr_jacobian);                    //solving (get dq)\n    angle_changed = dec.solve(gerr);                                          //(J^T*we) * dx = (J^T*we*J + lamda*Wn) * dq\n\n    present_angle = _manipulator.getAllActiveJointPosition();\n    set_angle.clear();\n    for (int8_t index = 0; index < _manipulator.getDOF(); index++)\n      set_angle.push_back(present_angle.at(index) + angle_changed(index));\n    _manipulator.setAllActiveJointPosition(set_angle);\n    solveForwardKinematics(&_manipulator);\n    ////////////////////////////////////////\n\n    //////////////checking dx///////////////\n    pose_changed = math::poseDifference(target_pose.kinematic.position, _manipulator.getComponentPositionFromWorld(tool_name), target_pose.kinematic.orientation, _manipulator.getComponentOrientationFromWorld(tool_name));\n    new_Ek = pose_changed.transpose() * We * pose_changed;\n    ////////////////////////////////////////\n\n    /////////////////////////////debug/////////////////////////////////\n    #if defined(KINEMATICS_DEBUG)\n    present_position = _manipulator.getComponentPositionFromWorld(tool_name);\n    present_orientation = _manipulator.getComponentOrientationFromWorld(tool_name);\n    present_orientation_rpy = math::convertRotationToRPY(present_orientation);\n    for(int t=0; t<3; t++)\n      debug_present_pose(t) = present_position(t);\n    for(int t=0; t<3; t++)\n      debug_present_pose(t+3) = present_orientation_rpy(t);\n    log::warn(\"iter : \", count,0);\n    log::warn(\"Ek : \", new_Ek*1000000000000);\n    log::println(\"tar_pose\");\n    log::println_VECTOR(debug_target_pose,16);\n    log::println(\"pre_pose\");\n    log::println_VECTOR(debug_present_pose,16);\n    log::println(\"delta_pose\");\n    log::println_VECTOR(debug_target_pose-debug_present_pose,16);\n    #endif\n    ////////////////////////////debug//////////////////////////////////\n\n    if (new_Ek < 1E-12)\n    {\n      /////////////////////////////debug/////////////////////////////////\n      #if defined(KINEMATICS_DEBUG)\n      log::warn(\"iter : \", count,0);\n      log::warn(\"Ek : \", new_Ek*1000000000000);\n      log::error(\"Success\");\n      log::println(\"------------------------------------\");\n      #endif\n      //////////////////////////debug//////////////////////////////////\n      *goal_joint_value = _manipulator.getAllActiveJointValue();\n      for(int8_t index = 0; index < _manipulator.getDOF(); index++)\n      {\n        goal_joint_value->at(index).velocity = 0.0;\n        goal_joint_value->at(index).acceleration = 0.0;\n        goal_joint_value->at(index).effort = 0.0;\n      }\n      return true;\n    }\n    else if (new_Ek < pre_Ek)\n    {\n      pre_Ek = new_Ek;\n    }\n    else\n    {\n      present_angle = _manipulator.getAllActiveJointPosition();\n      for (int8_t index = 0; index < _manipulator.getDOF(); index++)\n        set_angle.push_back(present_angle.at(index) - (gamma * angle_changed(index)));\n      _manipulator.setAllActiveJointPosition(set_angle);\n\n      solveForwardKinematics(&_manipulator);\n    }\n  }\n  log::error(\"[sr]fail to solve inverse kinematics (please change the solver)\");\n  *goal_joint_value = {};\n  return false;\n}\n\n\n/*****************************************************************************\n** Kinematics Solver Using Chain Rule and Singularity Robust Position Only Jacobian\n*****************************************************************************/\nvoid SolverUsingCRAndSRPositionOnlyJacobian::setOption(const void *arg){}\n\nEigen::MatrixXd SolverUsingCRAndSRPositionOnlyJacobian::jacobian(Manipulator *manipulator, Name tool_name)\n{\n  Eigen::MatrixXd jacobian = Eigen::MatrixXd::Identity(6, manipulator->getDOF());\n\n  Eigen::Vector3d joint_axis = Eigen::Vector3d::Zero(3);\n\n  Eigen::Vector3d position_changed = Eigen::Vector3d::Zero(3);\n  Eigen::Vector3d orientation_changed = Eigen::Vector3d::Zero(3);\n  Eigen::VectorXd pose_changed = Eigen::VectorXd::Zero(6);\n\n  //////////////////////////////////////////////////////////////////////////////////\n\n  int8_t index = 0;\n  Name my_name =  manipulator->getWorldChildName();\n\n  for (int8_t size = 0; size < manipulator->getDOF(); size++)\n  {\n    Name parent_name = manipulator->getComponentParentName(my_name);\n    if (parent_name == manipulator->getWorldName())\n    {\n      joint_axis = manipulator->getWorldOrientation() * manipulator->getAxis(my_name);\n    }\n    else\n    {\n      joint_axis = manipulator->getComponentOrientationFromWorld(parent_name) * manipulator->getAxis(my_name);\n    }\n\n    position_changed = math::skewSymmetricMatrix(joint_axis) *\n                       (manipulator->getComponentPositionFromWorld(tool_name) - manipulator->getComponentPositionFromWorld(my_name));\n    orientation_changed = joint_axis;\n\n    pose_changed << position_changed(0),\n        position_changed(1),\n        position_changed(2),\n        orientation_changed(0),\n        orientation_changed(1),\n        orientation_changed(2);\n\n    jacobian.col(index) = pose_changed;\n    index++;\n    my_name = manipulator->getComponentChildName(my_name).at(0); // Get Child name which has active joint\n  }\n  return jacobian;\n}\n\nvoid SolverUsingCRAndSRPositionOnlyJacobian::solveForwardKinematics(Manipulator *manipulator)\n{\n  forwardSolverUsingChainRule(manipulator, manipulator->getWorldChildName());\n}\n\nbool SolverUsingCRAndSRPositionOnlyJacobian::solveInverseKinematics(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue> *goal_joint_value)\n{\n  return inverseSolverUsingPositionOnlySRJacobian(manipulator, tool_name, target_pose, goal_joint_value);\n}\n\n\n//private\nvoid SolverUsingCRAndSRPositionOnlyJacobian::forwardSolverUsingChainRule(Manipulator *manipulator, Name component_name)\n{\n  Name my_name = component_name;\n  Name parent_name = manipulator->getComponentParentName(my_name);\n  int8_t number_of_child = manipulator->getComponentChildName(my_name).size();\n\n  Pose parent_pose_value;\n  Pose my_pose_value;\n\n  //Get Parent Pose\n  if (parent_name == manipulator->getWorldName())\n  {\n    parent_pose_value = manipulator->getWorldPose();\n  }\n  else\n  {\n    parent_pose_value = manipulator->getComponentPoseFromWorld(parent_name);\n  }\n\n  //position\n  my_pose_value.kinematic.position = parent_pose_value.kinematic.position\n                                   + (parent_pose_value.kinematic.orientation * manipulator->getComponentRelativePositionFromParent(my_name));\n  //orientation\n  my_pose_value.kinematic.orientation = parent_pose_value.kinematic.orientation * math::rodriguesRotationMatrix(manipulator->getAxis(my_name), manipulator->getJointPosition(my_name));\n  //linear velocity\n  my_pose_value.dynamic.linear.velocity = math::vector3(0.0, 0.0, 0.0);\n  //angular velocity\n  my_pose_value.dynamic.angular.velocity = math::vector3(0.0, 0.0, 0.0);\n  //linear acceleration\n  my_pose_value.dynamic.linear.acceleration = math::vector3(0.0, 0.0, 0.0);\n  //angular acceleration\n  my_pose_value.dynamic.angular.acceleration = math::vector3(0.0, 0.0, 0.0);\n\n  manipulator->setComponentPoseFromWorld(my_name, my_pose_value);\n\n  for (int8_t index = 0; index < number_of_child; index++)\n  {\n    Name child_name = manipulator->getComponentChildName(my_name).at(index);\n    forwardSolverUsingChainRule(manipulator, child_name);\n  }\n}\n\nbool SolverUsingCRAndSRPositionOnlyJacobian::inverseSolverUsingPositionOnlySRJacobian(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue> *goal_joint_value)\n{\n  //manipulator\n  Manipulator _manipulator = *manipulator;\n\n  //solver parameter\n  double lambda = 0.0;\n  const double param = 0.002;\n  const int8_t iteration = 10;\n\n  const double gamma = 0.5;             //rollback delta\n\n  //jacobian\n  Eigen::MatrixXd jacobian = Eigen::MatrixXd::Identity(6, _manipulator.getDOF());\n  Eigen::MatrixXd position_jacobian = Eigen::MatrixXd::Identity(3, _manipulator.getDOF());\n  Eigen::MatrixXd sr_jacobian = Eigen::MatrixXd::Identity(_manipulator.getDOF(), _manipulator.getDOF());\n\n  //delta parameter\n  Eigen::Vector3d position_changed = Eigen::VectorXd::Zero(3);\n  Eigen::VectorXd angle_changed = Eigen::VectorXd::Zero(_manipulator.getDOF());    //delta angle (dq)\n  Eigen::VectorXd gerr(_manipulator.getDOF());\n\n  //sr sovler parameter\n  double wn_pos = 1 / 0.3;\n  double pre_Ek = 0.0;\n  double new_Ek = 0.0;\n\n  Eigen::MatrixXd We(3, 3);\n  We << wn_pos, 0, 0,\n      0, wn_pos, 0,\n      0, 0, wn_pos;\n\n  Eigen::MatrixXd Wn = Eigen::MatrixXd::Identity(_manipulator.getDOF(), _manipulator.getDOF());\n\n  //angle parameter\n  std::vector<double> present_angle;                                               //angle (q)\n  std::vector<double> set_angle;                                                   //set angle (q + dq)\n\n  ////////////////////////////solving//////////////////////////////////\n\n  solveForwardKinematics(&_manipulator);\n  //////////////checking dx///////////////\n  position_changed = math::positionDifference(target_pose.kinematic.position, _manipulator.getComponentPositionFromWorld(tool_name));\n  pre_Ek = position_changed.transpose() * We * position_changed;\n  ///////////////////////////////////////\n\n  /////////////////////////////debug/////////////////////////////////\n  #if defined(KINEMATICS_DEBUG)\n  Eigen::Vector3d target_orientation_rpy = math::convertRotationToRPY(target_pose.orientation);\n  Eigen::VectorXd debug_target_pose(6);\n  for(int t=0; t<3; t++)\n    debug_target_pose(t) = target_pose.position(t);\n  for(int t=0; t<3; t++)\n    debug_target_pose(t+3) = target_orientation_rpy(t);\n\n  Eigen::Vector3d present_position = _manipulator.getComponentPositionFromWorld(tool_name);\n  Eigen::MatrixXd present_orientation = _manipulator.getComponentOrientationFromWorld(tool_name);\n  Eigen::Vector3d present_orientation_rpy = math::convertRotationToRPY(present_orientation);\n  Eigen::VectorXd debug_present_pose(6);\n  for(int t=0; t<3; t++)\n    debug_present_pose(t) = present_position(t);\n  for(int t=0; t<3; t++)\n    debug_present_pose(t+3) = present_orientation_rpy(t);\n\n  log::println(\"------------------------------------\");\n  log::warn(\"iter : first\");\n  log::warn(\"Ek : \", pre_Ek*1000000000000);\n  log::println(\"tar_pose\");\n  log::println_VECTOR(debug_target_pose,16);\n  log::println(\"pre_pose\");\n  log::println_VECTOR(debug_present_pose,16);\n  log::println(\"delta_pose\");\n  log::println_VECTOR(debug_target_pose-debug_present_pose,16);\n  #endif\n  ////////////////////////////debug//////////////////////////////////\n\n  //////////////////////////solving loop///////////////////////////////\n  for (int8_t count = 0; count < iteration; count++)\n  {\n    //////////solve using jacobian//////////\n    jacobian = this->jacobian(&_manipulator, tool_name);\n    position_jacobian.row(0) = jacobian.row(0);\n    position_jacobian.row(1) = jacobian.row(1);\n    position_jacobian.row(2) = jacobian.row(2);\n    lambda = pre_Ek + param;\n\n    sr_jacobian = (position_jacobian.transpose() * We * position_jacobian) + (lambda * Wn);     //calculate sr_jacobian (J^T*we*J + lamda*Wn)\n    gerr = position_jacobian.transpose() * We * position_changed;                                //calculate gerr (J^T*we) dx\n\n    ColPivHouseholderQR<Eigen::MatrixXd> dec(sr_jacobian);                    //solving (get dq)\n    angle_changed = dec.solve(gerr);                                          //(J^T*we) * dx = (J^T*we*J + lamda*Wn) * dq\n\n    present_angle = _manipulator.getAllActiveJointPosition();\n    set_angle.clear();\n    for (int8_t index = 0; index < _manipulator.getDOF(); index++)\n      set_angle.push_back(_manipulator.getAllActiveJointPosition().at(index) + angle_changed(index));\n    _manipulator.setAllActiveJointPosition(set_angle);\n    solveForwardKinematics(&_manipulator);\n    ////////////////////////////////////////\n\n    //////////////checking dx///////////////\n    position_changed = math::positionDifference(target_pose.kinematic.position, _manipulator.getComponentPositionFromWorld(tool_name));\n    new_Ek = position_changed.transpose() * We * position_changed;\n    ////////////////////////////////////////\n\n    /////////////////////////////debug/////////////////////////////////\n    #if defined(KINEMATICS_DEBUG)\n    present_position = _manipulator.getComponentPositionFromWorld(tool_name);\n    present_orientation = _manipulator.getComponentOrientationFromWorld(tool_name);\n    present_orientation_rpy = math::convertRotationToRPY(present_orientation);\n    for(int t=0; t<3; t++)\n      debug_present_pose(t) = present_position(t);\n    for(int t=0; t<3; t++)\n      debug_present_pose(t+3) = present_orientation_rpy(t);\n    log::warn(\"iter : \", count,0);\n    log::warn(\"Ek : \", new_Ek*1000000000000);\n    log::println(\"tar_pose\");\n    log::println_VECTOR(debug_target_pose,16);\n    log::println(\"pre_pose\");\n    log::println_VECTOR(debug_present_pose,16);\n    log::println(\"delta_pose\");\n    log::println_VECTOR(debug_target_pose-debug_present_pose,16);\n    #endif\n    ////////////////////////////debug//////////////////////////////////\n\n    if (new_Ek < 1E-12)\n    {\n      /////////////////////////////debug/////////////////////////////////\n      #if defined(KINEMATICS_DEBUG)\n      log::warn(\"iter : \", count,0);\n      log::warn(\"Ek : \", new_Ek*1000000000000);\n      log::error(\"IK Success\");\n      log::println(\"------------------------------------\");\n      #endif\n      //////////////////////////debug//////////////////////////////////\n      *goal_joint_value = _manipulator.getAllActiveJointValue();\n      for(int8_t index = 0; index < _manipulator.getDOF(); index++)\n      {\n        goal_joint_value->at(index).velocity = 0.0;\n        goal_joint_value->at(index).acceleration = 0.0;\n        goal_joint_value->at(index).effort = 0.0;\n      }\n      return true;\n    }\n    else if (new_Ek < pre_Ek)\n    {\n      pre_Ek = new_Ek;\n    }\n    else\n    {\n      present_angle = _manipulator.getAllActiveJointPosition();\n      for (int8_t index = 0; index < _manipulator.getDOF(); index++)\n        set_angle.push_back(_manipulator.getAllActiveJointPosition().at(index) - (gamma * angle_changed(index)));\n      _manipulator.setAllActiveJointPosition(set_angle);\n\n      solveForwardKinematics(&_manipulator);\n    }\n  }\n  log::error(\"[position_only]fail to solve inverse kinematics (please change the solver)\");\n  *goal_joint_value = {};\n  return false;\n}\n\n\n/*****************************************************************************\n** Kinematics Solver Customized for OpenManipulator Chain\n*****************************************************************************/\nvoid SolverCustomizedforOMChain::setOption(const void *arg){}\n\nEigen::MatrixXd SolverCustomizedforOMChain::jacobian(Manipulator *manipulator, Name tool_name)\n{\n  Eigen::MatrixXd jacobian = Eigen::MatrixXd::Identity(6, manipulator->getDOF());\n\n  Eigen::Vector3d joint_axis = Eigen::Vector3d::Zero(3);\n\n  Eigen::Vector3d position_changed = Eigen::Vector3d::Zero(3);\n  Eigen::Vector3d orientation_changed = Eigen::Vector3d::Zero(3);\n  Eigen::VectorXd pose_changed = Eigen::VectorXd::Zero(6);\n\n  //////////////////////////////////////////////////////////////////////////////////\n\n  int8_t index = 0;\n  Name my_name =  manipulator->getWorldChildName();\n\n  for (int8_t size = 0; size < manipulator->getDOF(); size++)\n  {\n    Name parent_name = manipulator->getComponentParentName(my_name);\n    if (parent_name == manipulator->getWorldName())\n    {\n      joint_axis = manipulator->getWorldOrientation() * manipulator->getAxis(my_name);\n    }\n    else\n    {\n      joint_axis = manipulator->getComponentOrientationFromWorld(parent_name) * manipulator->getAxis(my_name);\n    }\n\n    position_changed = math::skewSymmetricMatrix(joint_axis) *\n                       (manipulator->getComponentPositionFromWorld(tool_name) - manipulator->getComponentPositionFromWorld(my_name));\n    orientation_changed = joint_axis;\n\n    pose_changed << position_changed(0),\n        position_changed(1),\n        position_changed(2),\n        orientation_changed(0),\n        orientation_changed(1),\n        orientation_changed(2);\n\n    jacobian.col(index) = pose_changed;\n    index++;\n    my_name = manipulator->getComponentChildName(my_name).at(0); // Get Child name which has active joint\n  }\n  return jacobian;\n}\n\nvoid SolverCustomizedforOMChain::solveForwardKinematics(Manipulator *manipulator)\n{\n  forwardSolverUsingChainRule(manipulator, manipulator->getWorldChildName());\n}\n\nbool SolverCustomizedforOMChain::solveInverseKinematics(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue> *goal_joint_value)\n{\n  return chainCustomInverseKinematics(manipulator, tool_name, target_pose, goal_joint_value);\n}\n\n\n//private\nvoid SolverCustomizedforOMChain::forwardSolverUsingChainRule(Manipulator *manipulator, Name component_name)\n{\n  Name my_name = component_name;\n  Name parent_name = manipulator->getComponentParentName(my_name);\n  int8_t number_of_child = manipulator->getComponentChildName(my_name).size();\n\n  Pose parent_pose_value;\n  Pose my_pose_value;\n\n  //Get Parent Pose\n  if (parent_name == manipulator->getWorldName())\n  {\n    parent_pose_value = manipulator->getWorldPose();\n  }\n  else\n  {\n    parent_pose_value = manipulator->getComponentPoseFromWorld(parent_name);\n  }\n\n  //position\n  my_pose_value.kinematic.position = parent_pose_value.kinematic.position\n                                   + (parent_pose_value.kinematic.orientation * manipulator->getComponentRelativePositionFromParent(my_name));\n  //orientation\n  my_pose_value.kinematic.orientation = parent_pose_value.kinematic.orientation * math::rodriguesRotationMatrix(manipulator->getAxis(my_name), manipulator->getJointPosition(my_name));\n  //linear velocity\n  my_pose_value.dynamic.linear.velocity = math::vector3(0.0, 0.0, 0.0);\n  //angular velocity\n  my_pose_value.dynamic.angular.velocity = math::vector3(0.0, 0.0, 0.0);\n  //linear acceleration\n  my_pose_value.dynamic.linear.acceleration = math::vector3(0.0, 0.0, 0.0);\n  //angular acceleration\n  my_pose_value.dynamic.angular.acceleration = math::vector3(0.0, 0.0, 0.0);\n\n  manipulator->setComponentPoseFromWorld(my_name, my_pose_value);\n\n  for (int8_t index = 0; index < number_of_child; index++)\n  {\n    Name child_name = manipulator->getComponentChildName(my_name).at(index);\n    forwardSolverUsingChainRule(manipulator, child_name);\n  }\n}\nbool SolverCustomizedforOMChain::chainCustomInverseKinematics(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue> *goal_joint_value)\n{\n  //manipulator\n  Manipulator _manipulator = *manipulator;\n\n  //solver parameter\n  double lambda = 0.0;\n  const double param = 0.002;\n  const int8_t iteration = 10;\n\n  const double gamma = 0.5;             //rollback delta\n\n  //sr sovler parameter\n  double wn_pos = 1 / 0.3;\n  double wn_ang = 1 / (2 * M_PI);\n  double pre_Ek = 0.0;\n  double new_Ek = 0.0;\n\n  Eigen::MatrixXd We(6, 6);\n  We << wn_pos, 0, 0, 0, 0, 0,\n      0, wn_pos, 0, 0, 0, 0,\n      0, 0, wn_pos, 0, 0, 0,\n      0, 0, 0, wn_ang, 0, 0,\n      0, 0, 0, 0, wn_ang, 0,\n      0, 0, 0, 0, 0, wn_ang;\n\n  Eigen::MatrixXd Wn = Eigen::MatrixXd::Identity(_manipulator.getDOF(), _manipulator.getDOF());\n\n  //jacobian\n  Eigen::MatrixXd jacobian = Eigen::MatrixXd::Identity(6, _manipulator.getDOF());\n  Eigen::MatrixXd sr_jacobian = Eigen::MatrixXd::Identity(_manipulator.getDOF(), _manipulator.getDOF());\n\n  //delta parameter\n  Eigen::VectorXd pose_changed = Eigen::VectorXd::Zero(6);\n  Eigen::VectorXd angle_changed = Eigen::VectorXd::Zero(_manipulator.getDOF());    //delta angle (dq)\n  Eigen::VectorXd gerr(_manipulator.getDOF());\n\n  //angle parameter\n  std::vector<double> present_angle;                                               //angle (q)\n  std::vector<double> set_angle;                                                   //set angle (q + dq)\n\n  ////////////////////////////solving//////////////////////////////////\n\n  solveForwardKinematics(&_manipulator);\n\n  //////////////make target ori//////////  //only OpenManipulator Chain\n  Eigen::Matrix3d present_orientation = _manipulator.getComponentOrientationFromWorld(tool_name);\n  Eigen::Vector3d present_orientation_rpy = math::convertRotationMatrixToRPYVector(present_orientation);\n  Eigen::Matrix3d target_orientation = target_pose.kinematic.orientation;\n  Eigen::Vector3d target_orientation_rpy = math::convertRotationMatrixToRPYVector(target_orientation);\n\n  Eigen::Vector3d joint1_rlative_position = _manipulator.getComponentRelativePositionFromParent(_manipulator.getWorldChildName());\n  Eigen::Vector3d target_position_from_joint1 = target_pose.kinematic.position - joint1_rlative_position;\n\n  target_orientation_rpy(0) = present_orientation_rpy(0);\n  target_orientation_rpy(1) = target_orientation_rpy(1);\n  target_orientation_rpy(2) = atan2(target_position_from_joint1(1) ,target_position_from_joint1(0));\n\n  target_pose.kinematic.orientation = math::convertRPYToRotationMatrix(target_orientation_rpy(0), target_orientation_rpy(1), target_orientation_rpy(2));\n  ///////////////////////////////////////\n\n  //////////////checking dx///////////////\n  pose_changed = math::poseDifference(target_pose.kinematic.position, _manipulator.getComponentPositionFromWorld(tool_name), target_pose.kinematic.orientation, _manipulator.getComponentOrientationFromWorld(tool_name));\n  pre_Ek = pose_changed.transpose() * We * pose_changed;\n  ///////////////////////////////////////\n\n  /////////////////////////////debug/////////////////////////////////\n  #if defined(KINEMATICS_DEBUG)\n  Eigen::VectorXd debug_target_pose(6);\n  for(int t=0; t<3; t++)\n    debug_target_pose(t) = target_pose.position(t);\n  for(int t=0; t<3; t++)\n    debug_target_pose(t+3) = target_orientation_rpy(t);\n\n  Eigen::Vector3d present_position = _manipulator.getComponentPositionFromWorld(tool_name);\n  Eigen::VectorXd debug_present_pose(6);\n  for(int t=0; t<3; t++)\n    debug_present_pose(t) = present_position(t);\n  for(int t=0; t<3; t++)\n    debug_present_pose(t+3) = present_orientation_rpy(t);\n\n  log::println(\"------------------------------------\");\n  log::warn(\"iter : first\");\n  log::warn(\"Ek : \", pre_Ek*1000000000000);\n  log::println(\"tar_pose\");\n  log::println_VECTOR(debug_target_pose,16);\n  log::println(\"pre_pose\");\n  log::println_VECTOR(debug_present_pose,16);\n  log::println(\"delta_pose\");\n  log::println_VECTOR(debug_target_pose-debug_present_pose,16);\n  #endif\n  ////////////////////////////debug//////////////////////////////////\n\n  //////////////////////////solving loop///////////////////////////////\n  for (int8_t count = 0; count < iteration; count++)\n  {\n    //////////solve using jacobian//////////\n    jacobian = this->jacobian(&_manipulator, tool_name);\n    lambda = pre_Ek + param;\n\n    sr_jacobian = (jacobian.transpose() * We * jacobian) + (lambda * Wn);     //calculate sr_jacobian (J^T*we*J + lamda*Wn)\n    gerr = jacobian.transpose() * We * pose_changed;                          //calculate gerr (J^T*we) dx\n\n    ColPivHouseholderQR<Eigen::MatrixXd> dec(sr_jacobian);                    //solving (get dq)\n    angle_changed = dec.solve(gerr);                                          //(J^T*we) * dx = (J^T*we*J + lamda*Wn) * dq\n\n    present_angle = _manipulator.getAllActiveJointPosition();\n    set_angle.clear();\n    for (int8_t index = 0; index < _manipulator.getDOF(); index++)\n      set_angle.push_back(present_angle.at(index) + angle_changed(index));\n    _manipulator.setAllActiveJointPosition(set_angle);\n    solveForwardKinematics(&_manipulator);\n    ////////////////////////////////////////\n\n    //////////////checking dx///////////////\n    pose_changed = math::poseDifference(target_pose.kinematic.position, _manipulator.getComponentPositionFromWorld(tool_name), target_pose.kinematic.orientation, _manipulator.getComponentOrientationFromWorld(tool_name));\n    new_Ek = pose_changed.transpose() * We * pose_changed;\n    ////////////////////////////////////////\n\n    /////////////////////////////debug/////////////////////////////////\n    #if defined(KINEMATICS_DEBUG)\n    present_position = _manipulator.getComponentPositionFromWorld(tool_name);\n    present_orientation = _manipulator.getComponentOrientationFromWorld(tool_name);\n    present_orientation_rpy = math::convertRotationToRPY(present_orientation);\n    for(int t=0; t<3; t++)\n      debug_present_pose(t) = present_position(t);\n    for(int t=0; t<3; t++)\n      debug_present_pose(t+3) = present_orientation_rpy(t);\n    log::warn(\"iter : \", count,0);\n    log::warn(\"Ek : \", new_Ek*1000000000000);\n    log::println(\"tar_pose\");\n    log::println_VECTOR(debug_target_pose,16);\n    log::println(\"pre_pose\");\n    log::println_VECTOR(debug_present_pose,16);\n    log::println(\"delta_pose\");\n    log::println_VECTOR(debug_target_pose-debug_present_pose,16);\n    #endif\n    ////////////////////////////debug//////////////////////////////////\n\n    if (new_Ek < 1E-12)\n    {\n      /////////////////////////////debug/////////////////////////////////\n      #if defined(KINEMATICS_DEBUG)\n      log::warn(\"iter : \", count,0);\n      log::warn(\"Ek : \", new_Ek*1000000000000);\n      log::error(\"Success\");\n      log::println(\"------------------------------------\");\n      #endif\n      //////////////////////////debug//////////////////////////////////\n      *goal_joint_value = _manipulator.getAllActiveJointValue();\n      for(int8_t index = 0; index < _manipulator.getDOF(); index++)\n      {\n        goal_joint_value->at(index).velocity = 0.0;\n        goal_joint_value->at(index).acceleration = 0.0;\n        goal_joint_value->at(index).effort = 0.0;\n      }\n      return true;\n    }\n    else if (new_Ek < pre_Ek)\n    {\n      pre_Ek = new_Ek;\n    }\n    else\n    {\n      present_angle = _manipulator.getAllActiveJointPosition();\n      for (int8_t index = 0; index < _manipulator.getDOF(); index++)\n        set_angle.push_back(present_angle.at(index) - (gamma * angle_changed(index)));\n      _manipulator.setAllActiveJointPosition(set_angle);\n\n      solveForwardKinematics(&_manipulator);\n    }\n  }\n  log::error(\"[OpenManipulator Chain Custom]fail to solve inverse kinematics\");\n  *goal_joint_value = {};\n  return false;\n}\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/open_manipulator_libs/src/open_manipulator.cpp",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include \"../include/open_manipulator_libs/open_manipulator.h\"\n\nOpenManipulator::OpenManipulator()\n{\n  // Use Default OpenMANIPULATOR-X ID setting\n  joint1_id = 11;\n  joint2_id = 12;\n  joint3_id = 13;\n  joint4_id = 14;\n  gripper_id = 15;\n}\nOpenManipulator::~OpenManipulator()\n{\n  delete kinematics_;\n  delete joint_;\n  delete tool_;\n  for(uint8_t index = 0; index < CUSTOM_TRAJECTORY_SIZE; index++)\n    delete custom_trajectory_[index];\n}\n\nvoid OpenManipulator::initOpenManipulator(bool using_actual_robot_state, STRING usb_port, STRING baud_rate, float control_loop_time)\n{\n  /*****************************************************************************\n  ** Initialize Manipulator Parameters\n  *****************************************************************************/\n  addWorld(\"world\",   // world name\n           \"joint1\"); // child name\n\n  addJoint(\"joint1\",  // my name\n           \"world\",   // parent name\n           \"joint2\",  // child name\n           math::vector3(0.012, 0.0, 0.017),                // relative position\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // relative orientation\n           Z_AXIS,    // axis of rotation\n           joint1_id, // actuator id\n           M_PI,      // max joint limit (3.14 rad)\n           -M_PI);    // min joint limit (-3.14 rad)\n\n  addJoint(\"joint2\",  // my name\n           \"joint1\",  // parent name\n           \"joint3\",  // child name\n           math::vector3(0.0, 0.0, 0.0595),                 // relative position\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // relative orientation\n           Y_AXIS,    // axis of rotation\n           joint2_id, // actuator id\n           M_PI_2,    // max joint limit (1.67 rad)\n           -2.05);    // min joint limit (-2.05 rad)\n\n  addJoint(\"joint3\",  // my name\n           \"joint2\",  // parent name\n           \"joint4\",  // child name\n           math::vector3(0.024, 0.0, 0.128),                // relative position\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // relative orientation\n           Y_AXIS,    // axis of rotation\n           joint3_id, // actuator id\n           1.53,      // max joint limit (1.53 rad)\n           -M_PI_2);  // min joint limit (-1.67 rad)\n\n  addJoint(\"joint4\",  // my name\n           \"joint3\",  // parent name\n           \"gripper\", // child name\n           math::vector3(0.124, 0.0, 0.0),                 // relative position\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // relative orientation\n           Y_AXIS,    // axis of rotation\n           joint4_id, // actuator id\n           2.0,       // max joint limit (2.0 rad)\n           -1.8);     // min joint limit (-1.8 rad)\n\n  addTool(\"gripper\",  // my name\n          \"joint4\",   // parent name\n          math::vector3(0.126, 0.0, 0.0),                 // relative position\n          math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // relative orientation\n          gripper_id, // actuator id\n          0.010,      // max gripper limit (0.01 m)\n          -0.010,     // min gripper limit (-0.01 m)\n          -0.015);    // Convert unit from `meter` to `radian`\n\n          \n  /*****************************************************************************\n  ** Initialize Kinematics \n  *****************************************************************************/\n  kinematics_ = new kinematics::SolverCustomizedforOMChain();\n  // kinematics_ = new kinematics::SolverUsingCRAndSRPositionOnlyJacobian();\n  addKinematics(kinematics_);\n\n  /*****************************************************************************\n  ** Initialize Custom Trajectory\n  *****************************************************************************/\n  custom_trajectory_[0] = new custom_trajectory::Line();\n  custom_trajectory_[1] = new custom_trajectory::Circle();\n  custom_trajectory_[2] = new custom_trajectory::Rhombus();\n  custom_trajectory_[3] = new custom_trajectory::Heart();\n\n  addCustomTrajectory(CUSTOM_TRAJECTORY_LINE, custom_trajectory_[0]);\n  addCustomTrajectory(CUSTOM_TRAJECTORY_CIRCLE, custom_trajectory_[1]);\n  addCustomTrajectory(CUSTOM_TRAJECTORY_RHOMBUS, custom_trajectory_[2]);\n  addCustomTrajectory(CUSTOM_TRAJECTORY_HEART, custom_trajectory_[3]);\n\n  if (using_actual_robot_state)\n  {\n    /*****************************************************************************\n    ** Initialize ㅓoint Actuator\n    *****************************************************************************/\n    // joint_ = new dynamixel::JointDynamixel();\n    joint_ = new dynamixel::JointDynamixelProfileControl(control_loop_time);\n    \n    // Set communication arguments\n    STRING dxl_comm_arg[2] = {usb_port, baud_rate};\n    void *p_dxl_comm_arg = &dxl_comm_arg;\n\n    // Set joint actuator id\n    std::vector<uint8_t> jointDxlId;\n    jointDxlId.push_back(joint1_id);\n    jointDxlId.push_back(joint2_id);\n    jointDxlId.push_back(joint3_id);\n    jointDxlId.push_back(joint4_id);\n    addJointActuator(JOINT_DYNAMIXEL, joint_, jointDxlId, p_dxl_comm_arg);\n\n    // Set joint actuator control mode\n    STRING joint_dxl_mode_arg = \"position_mode\";\n    void *p_joint_dxl_mode_arg = &joint_dxl_mode_arg;\n    setJointActuatorMode(JOINT_DYNAMIXEL, jointDxlId, p_joint_dxl_mode_arg);\n\n\n    /*****************************************************************************\n    ** Initialize Tool Actuator\n    *****************************************************************************/\n    tool_ = new dynamixel::GripperDynamixel();\n\n    // Set gripper actuator id \n    uint8_t gripperDxlId = gripper_id;\n    addToolActuator(TOOL_DYNAMIXEL, tool_, gripperDxlId, p_dxl_comm_arg);\n\n    // Set gripper actuator control mode\n    STRING gripper_dxl_mode_arg = \"current_based_position_mode\";\n    void *p_gripper_dxl_mode_arg = &gripper_dxl_mode_arg;\n    setToolActuatorMode(TOOL_DYNAMIXEL, p_gripper_dxl_mode_arg);\n\n    // Set gripper actuator parameter\n    STRING gripper_dxl_opt_arg[2];\n    void *p_gripper_dxl_opt_arg = &gripper_dxl_opt_arg;\n    gripper_dxl_opt_arg[0] = \"Profile_Acceleration\";\n    gripper_dxl_opt_arg[1] = \"20\";\n    setToolActuatorMode(TOOL_DYNAMIXEL, p_gripper_dxl_opt_arg);\n\n    gripper_dxl_opt_arg[0] = \"Profile_Velocity\";\n    gripper_dxl_opt_arg[1] = \"200\";\n    setToolActuatorMode(TOOL_DYNAMIXEL, p_gripper_dxl_opt_arg);\n\n\n    /*****************************************************************************\n    ** Enable actuators and Receive actuator values \n    *****************************************************************************/\n    // Enable All Actuators \n    enableAllActuator();\n\n    // Receive current angles from all actuators \n    receiveAllJointActuatorValue();\n    receiveAllToolActuatorValue();\n  }\n}\n\nvoid OpenManipulator::processOpenManipulator(double present_time)\n{\n  JointWaypoint goal_joint_value = getJointGoalValueFromTrajectory(present_time);\n  JointWaypoint goal_tool_value  = getToolGoalValue();\n\n  receiveAllJointActuatorValue();\n  receiveAllToolActuatorValue();\n  if(goal_joint_value.size() != 0) sendAllJointActuatorValue(goal_joint_value);\n  if(goal_tool_value.size() != 0) sendAllToolActuatorValue(goal_tool_value);\n  solveForwardKinematics();\n}\n\n// Use Custom ID settings\nvoid OpenManipulator::setOpenManipulatorCustomJointId(uint8_t joint1, uint8_t joint2, uint8_t joint3, uint8_t joint4, uint8_t gripper)\n{\n  joint1_id = joint1;\n  joint2_id = joint2;\n  joint3_id = joint3;\n  joint4_id = joint4;\n  gripper_id = gripper;\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/open_manipulator_libs.h",
    "content": "#include \"open_manipulator_libs/include/open_manipulator_libs/open_manipulator.h\"\n#include \"open_manipulator_libs/include/open_manipulator_libs/dynamixel.h\"\n#include \"open_manipulator_libs/include/open_manipulator_libs/kinematics.h\"\n#include \"open_manipulator_libs/include/open_manipulator_libs/custom_trajectory.h\"\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/open_manipulator_msgs/GetJointPosition.h",
    "content": "#ifndef _ROS_SERVICE_GetJointPosition_h\n#define _ROS_SERVICE_GetJointPosition_h\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"open_manipulator_msgs/JointPosition.h\"\n\nnamespace open_manipulator_msgs\n{\n\nstatic const char GETJOINTPOSITION[] = \"open_manipulator_msgs/GetJointPosition\";\n\n  class GetJointPositionRequest : public ros::Msg\n  {\n    public:\n      typedef const char* _planning_group_type;\n      _planning_group_type planning_group;\n\n    GetJointPositionRequest():\n      planning_group(\"\")\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      uint32_t length_planning_group = strlen(this->planning_group);\n      varToArr(outbuffer + offset, length_planning_group);\n      offset += 4;\n      memcpy(outbuffer + offset, this->planning_group, length_planning_group);\n      offset += length_planning_group;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      uint32_t length_planning_group;\n      arrToVar(length_planning_group, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_planning_group; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_planning_group-1]=0;\n      this->planning_group = (char *)(inbuffer + offset-1);\n      offset += length_planning_group;\n     return offset;\n    }\n\n    const char * getType(){ return GETJOINTPOSITION; };\n    const char * getMD5(){ return \"6b02e06b167eb20b51185dc7d0b638aa\"; };\n\n  };\n\n  class GetJointPositionResponse : public ros::Msg\n  {\n    public:\n      typedef open_manipulator_msgs::JointPosition _joint_position_type;\n      _joint_position_type joint_position;\n\n    GetJointPositionResponse():\n      joint_position()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->joint_position.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->joint_position.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return GETJOINTPOSITION; };\n    const char * getMD5(){ return \"e1f1ee99b5e77308297dc4eeedd305d4\"; };\n\n  };\n\n  class GetJointPosition {\n    public:\n    typedef GetJointPositionRequest Request;\n    typedef GetJointPositionResponse Response;\n  };\n\n}\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/open_manipulator_msgs/GetKinematicsPose.h",
    "content": "#ifndef _ROS_SERVICE_GetKinematicsPose_h\n#define _ROS_SERVICE_GetKinematicsPose_h\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"open_manipulator_msgs/KinematicsPose.h\"\n#include \"std_msgs/Header.h\"\n\nnamespace open_manipulator_msgs\n{\n\nstatic const char GETKINEMATICSPOSE[] = \"open_manipulator_msgs/GetKinematicsPose\";\n\n  class GetKinematicsPoseRequest : public ros::Msg\n  {\n    public:\n      typedef const char* _planning_group_type;\n      _planning_group_type planning_group;\n      typedef const char* _end_effector_name_type;\n      _end_effector_name_type end_effector_name;\n\n    GetKinematicsPoseRequest():\n      planning_group(\"\"),\n      end_effector_name(\"\")\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      uint32_t length_planning_group = strlen(this->planning_group);\n      varToArr(outbuffer + offset, length_planning_group);\n      offset += 4;\n      memcpy(outbuffer + offset, this->planning_group, length_planning_group);\n      offset += length_planning_group;\n      uint32_t length_end_effector_name = strlen(this->end_effector_name);\n      varToArr(outbuffer + offset, length_end_effector_name);\n      offset += 4;\n      memcpy(outbuffer + offset, this->end_effector_name, length_end_effector_name);\n      offset += length_end_effector_name;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      uint32_t length_planning_group;\n      arrToVar(length_planning_group, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_planning_group; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_planning_group-1]=0;\n      this->planning_group = (char *)(inbuffer + offset-1);\n      offset += length_planning_group;\n      uint32_t length_end_effector_name;\n      arrToVar(length_end_effector_name, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_end_effector_name; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_end_effector_name-1]=0;\n      this->end_effector_name = (char *)(inbuffer + offset-1);\n      offset += length_end_effector_name;\n     return offset;\n    }\n\n    const char * getType(){ return GETKINEMATICSPOSE; };\n    const char * getMD5(){ return \"14dd5674451c0fe6eacac0ded7197f30\"; };\n\n  };\n\n  class GetKinematicsPoseResponse : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef open_manipulator_msgs::KinematicsPose _kinematics_pose_type;\n      _kinematics_pose_type kinematics_pose;\n\n    GetKinematicsPoseResponse():\n      header(),\n      kinematics_pose()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      offset += this->kinematics_pose.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      offset += this->kinematics_pose.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return GETKINEMATICSPOSE; };\n    const char * getMD5(){ return \"3b64b73433e2775c9c4b7e1a00dd6995\"; };\n\n  };\n\n  class GetKinematicsPose {\n    public:\n    typedef GetKinematicsPoseRequest Request;\n    typedef GetKinematicsPoseResponse Response;\n  };\n\n}\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/open_manipulator_msgs/JointPosition.h",
    "content": "#ifndef _ROS_open_manipulator_msgs_JointPosition_h\n#define _ROS_open_manipulator_msgs_JointPosition_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace open_manipulator_msgs\n{\n\n  class JointPosition : public ros::Msg\n  {\n    public:\n      uint32_t joint_name_length;\n      typedef char* _joint_name_type;\n      _joint_name_type st_joint_name;\n      _joint_name_type * joint_name;\n      uint32_t position_length;\n      typedef float _position_type;\n      _position_type st_position;\n      _position_type * position;\n      typedef float _max_accelerations_scaling_factor_type;\n      _max_accelerations_scaling_factor_type max_accelerations_scaling_factor;\n      typedef float _max_velocity_scaling_factor_type;\n      _max_velocity_scaling_factor_type max_velocity_scaling_factor;\n\n    JointPosition():\n      joint_name_length(0), joint_name(NULL),\n      position_length(0), position(NULL),\n      max_accelerations_scaling_factor(0),\n      max_velocity_scaling_factor(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      *(outbuffer + offset + 0) = (this->joint_name_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->joint_name_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->joint_name_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->joint_name_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->joint_name_length);\n      for( uint32_t i = 0; i < joint_name_length; i++){\n      uint32_t length_joint_namei = strlen(this->joint_name[i]);\n      varToArr(outbuffer + offset, length_joint_namei);\n      offset += 4;\n      memcpy(outbuffer + offset, this->joint_name[i], length_joint_namei);\n      offset += length_joint_namei;\n      }\n      *(outbuffer + offset + 0) = (this->position_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->position_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->position_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->position_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->position_length);\n      for( uint32_t i = 0; i < position_length; i++){\n      offset += serializeAvrFloat64(outbuffer + offset, this->position[i]);\n      }\n      offset += serializeAvrFloat64(outbuffer + offset, this->max_accelerations_scaling_factor);\n      offset += serializeAvrFloat64(outbuffer + offset, this->max_velocity_scaling_factor);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      uint32_t joint_name_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      joint_name_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      joint_name_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      joint_name_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->joint_name_length);\n      if(joint_name_lengthT > joint_name_length)\n        this->joint_name = (char**)realloc(this->joint_name, joint_name_lengthT * sizeof(char*));\n      joint_name_length = joint_name_lengthT;\n      for( uint32_t i = 0; i < joint_name_length; i++){\n      uint32_t length_st_joint_name;\n      arrToVar(length_st_joint_name, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_st_joint_name; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_st_joint_name-1]=0;\n      this->st_joint_name = (char *)(inbuffer + offset-1);\n      offset += length_st_joint_name;\n        memcpy( &(this->joint_name[i]), &(this->st_joint_name), sizeof(char*));\n      }\n      uint32_t position_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      position_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      position_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      position_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->position_length);\n      if(position_lengthT > position_length)\n        this->position = (float*)realloc(this->position, position_lengthT * sizeof(float));\n      position_length = position_lengthT;\n      for( uint32_t i = 0; i < position_length; i++){\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->st_position));\n        memcpy( &(this->position[i]), &(this->st_position), sizeof(float));\n      }\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->max_accelerations_scaling_factor));\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->max_velocity_scaling_factor));\n     return offset;\n    }\n\n    const char * getType(){ return \"open_manipulator_msgs/JointPosition\"; };\n    const char * getMD5(){ return \"b6b6bc3417b5da955b766eb41a6c1698\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/open_manipulator_msgs/KinematicsPose.h",
    "content": "#ifndef _ROS_open_manipulator_msgs_KinematicsPose_h\n#define _ROS_open_manipulator_msgs_KinematicsPose_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"geometry_msgs/Pose.h\"\n\nnamespace open_manipulator_msgs\n{\n\n  class KinematicsPose : public ros::Msg\n  {\n    public:\n      typedef geometry_msgs::Pose _pose_type;\n      _pose_type pose;\n      typedef float _max_accelerations_scaling_factor_type;\n      _max_accelerations_scaling_factor_type max_accelerations_scaling_factor;\n      typedef float _max_velocity_scaling_factor_type;\n      _max_velocity_scaling_factor_type max_velocity_scaling_factor;\n      typedef float _tolerance_type;\n      _tolerance_type tolerance;\n\n    KinematicsPose():\n      pose(),\n      max_accelerations_scaling_factor(0),\n      max_velocity_scaling_factor(0),\n      tolerance(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->pose.serialize(outbuffer + offset);\n      offset += serializeAvrFloat64(outbuffer + offset, this->max_accelerations_scaling_factor);\n      offset += serializeAvrFloat64(outbuffer + offset, this->max_velocity_scaling_factor);\n      offset += serializeAvrFloat64(outbuffer + offset, this->tolerance);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->pose.deserialize(inbuffer + offset);\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->max_accelerations_scaling_factor));\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->max_velocity_scaling_factor));\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->tolerance));\n     return offset;\n    }\n\n    const char * getType(){ return \"open_manipulator_msgs/KinematicsPose\"; };\n    const char * getMD5(){ return \"bad8d5def2efabb0336490f8e9f6f2e2\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/open_manipulator_msgs/OpenManipulatorState.h",
    "content": "#ifndef _ROS_open_manipulator_msgs_OpenManipulatorState_h\n#define _ROS_open_manipulator_msgs_OpenManipulatorState_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace open_manipulator_msgs\n{\n\n  class OpenManipulatorState : public ros::Msg\n  {\n    public:\n      typedef const char* _open_manipulator_moving_state_type;\n      _open_manipulator_moving_state_type open_manipulator_moving_state;\n      typedef const char* _open_manipulator_actuator_state_type;\n      _open_manipulator_actuator_state_type open_manipulator_actuator_state;\n      const char* IS_MOVING =  \"IS_MOVING\";\n      const char* STOPPED =  \"STOPPED\";\n      const char* ACTUATOR_ENABLED =  \"ACTUATOR_ENABLED\";\n      const char* ACTUATOR_DISABLED =  \"ACTUATOR_DISABLED\";\n\n    OpenManipulatorState():\n      open_manipulator_moving_state(\"\"),\n      open_manipulator_actuator_state(\"\")\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      uint32_t length_open_manipulator_moving_state = strlen(this->open_manipulator_moving_state);\n      varToArr(outbuffer + offset, length_open_manipulator_moving_state);\n      offset += 4;\n      memcpy(outbuffer + offset, this->open_manipulator_moving_state, length_open_manipulator_moving_state);\n      offset += length_open_manipulator_moving_state;\n      uint32_t length_open_manipulator_actuator_state = strlen(this->open_manipulator_actuator_state);\n      varToArr(outbuffer + offset, length_open_manipulator_actuator_state);\n      offset += 4;\n      memcpy(outbuffer + offset, this->open_manipulator_actuator_state, length_open_manipulator_actuator_state);\n      offset += length_open_manipulator_actuator_state;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      uint32_t length_open_manipulator_moving_state;\n      arrToVar(length_open_manipulator_moving_state, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_open_manipulator_moving_state; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_open_manipulator_moving_state-1]=0;\n      this->open_manipulator_moving_state = (char *)(inbuffer + offset-1);\n      offset += length_open_manipulator_moving_state;\n      uint32_t length_open_manipulator_actuator_state;\n      arrToVar(length_open_manipulator_actuator_state, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_open_manipulator_actuator_state; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_open_manipulator_actuator_state-1]=0;\n      this->open_manipulator_actuator_state = (char *)(inbuffer + offset-1);\n      offset += length_open_manipulator_actuator_state;\n     return offset;\n    }\n\n    const char * getType(){ return \"open_manipulator_msgs/OpenManipulatorState\"; };\n    const char * getMD5(){ return \"35c95327a0dcb52791892bac52df33e8\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/open_manipulator_msgs/SetActuatorState.h",
    "content": "#ifndef _ROS_SERVICE_SetActuatorState_h\n#define _ROS_SERVICE_SetActuatorState_h\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace open_manipulator_msgs\n{\n\nstatic const char SETACTUATORSTATE[] = \"open_manipulator_msgs/SetActuatorState\";\n\n  class SetActuatorStateRequest : public ros::Msg\n  {\n    public:\n      typedef bool _set_actuator_state_type;\n      _set_actuator_state_type set_actuator_state;\n\n    SetActuatorStateRequest():\n      set_actuator_state(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      union {\n        bool real;\n        uint8_t base;\n      } u_set_actuator_state;\n      u_set_actuator_state.real = this->set_actuator_state;\n      *(outbuffer + offset + 0) = (u_set_actuator_state.base >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->set_actuator_state);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      union {\n        bool real;\n        uint8_t base;\n      } u_set_actuator_state;\n      u_set_actuator_state.base = 0;\n      u_set_actuator_state.base |= ((uint8_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      this->set_actuator_state = u_set_actuator_state.real;\n      offset += sizeof(this->set_actuator_state);\n     return offset;\n    }\n\n    const char * getType(){ return SETACTUATORSTATE; };\n    const char * getMD5(){ return \"0a8a1fa84fab126c7567fbb489a23ea5\"; };\n\n  };\n\n  class SetActuatorStateResponse : public ros::Msg\n  {\n    public:\n      typedef bool _is_planned_type;\n      _is_planned_type is_planned;\n\n    SetActuatorStateResponse():\n      is_planned(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      union {\n        bool real;\n        uint8_t base;\n      } u_is_planned;\n      u_is_planned.real = this->is_planned;\n      *(outbuffer + offset + 0) = (u_is_planned.base >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->is_planned);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      union {\n        bool real;\n        uint8_t base;\n      } u_is_planned;\n      u_is_planned.base = 0;\n      u_is_planned.base |= ((uint8_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      this->is_planned = u_is_planned.real;\n      offset += sizeof(this->is_planned);\n     return offset;\n    }\n\n    const char * getType(){ return SETACTUATORSTATE; };\n    const char * getMD5(){ return \"2638cc2443b1469b0e9e152083d7128d\"; };\n\n  };\n\n  class SetActuatorState {\n    public:\n    typedef SetActuatorStateRequest Request;\n    typedef SetActuatorStateResponse Response;\n  };\n\n}\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/open_manipulator_msgs/SetDrawingTrajectory.h",
    "content": "#ifndef _ROS_SERVICE_SetDrawingTrajectory_h\n#define _ROS_SERVICE_SetDrawingTrajectory_h\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace open_manipulator_msgs\n{\n\nstatic const char SETDRAWINGTRAJECTORY[] = \"open_manipulator_msgs/SetDrawingTrajectory\";\n\n  class SetDrawingTrajectoryRequest : public ros::Msg\n  {\n    public:\n      typedef const char* _end_effector_name_type;\n      _end_effector_name_type end_effector_name;\n      typedef const char* _drawing_trajectory_name_type;\n      _drawing_trajectory_name_type drawing_trajectory_name;\n      uint32_t param_length;\n      typedef float _param_type;\n      _param_type st_param;\n      _param_type * param;\n      typedef float _path_time_type;\n      _path_time_type path_time;\n\n    SetDrawingTrajectoryRequest():\n      end_effector_name(\"\"),\n      drawing_trajectory_name(\"\"),\n      param_length(0), param(NULL),\n      path_time(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      uint32_t length_end_effector_name = strlen(this->end_effector_name);\n      varToArr(outbuffer + offset, length_end_effector_name);\n      offset += 4;\n      memcpy(outbuffer + offset, this->end_effector_name, length_end_effector_name);\n      offset += length_end_effector_name;\n      uint32_t length_drawing_trajectory_name = strlen(this->drawing_trajectory_name);\n      varToArr(outbuffer + offset, length_drawing_trajectory_name);\n      offset += 4;\n      memcpy(outbuffer + offset, this->drawing_trajectory_name, length_drawing_trajectory_name);\n      offset += length_drawing_trajectory_name;\n      *(outbuffer + offset + 0) = (this->param_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->param_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->param_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->param_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->param_length);\n      for( uint32_t i = 0; i < param_length; i++){\n      offset += serializeAvrFloat64(outbuffer + offset, this->param[i]);\n      }\n      offset += serializeAvrFloat64(outbuffer + offset, this->path_time);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      uint32_t length_end_effector_name;\n      arrToVar(length_end_effector_name, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_end_effector_name; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_end_effector_name-1]=0;\n      this->end_effector_name = (char *)(inbuffer + offset-1);\n      offset += length_end_effector_name;\n      uint32_t length_drawing_trajectory_name;\n      arrToVar(length_drawing_trajectory_name, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_drawing_trajectory_name; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_drawing_trajectory_name-1]=0;\n      this->drawing_trajectory_name = (char *)(inbuffer + offset-1);\n      offset += length_drawing_trajectory_name;\n      uint32_t param_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      param_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      param_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      param_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->param_length);\n      if(param_lengthT > param_length)\n        this->param = (float*)realloc(this->param, param_lengthT * sizeof(float));\n      param_length = param_lengthT;\n      for( uint32_t i = 0; i < param_length; i++){\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->st_param));\n        memcpy( &(this->param[i]), &(this->st_param), sizeof(float));\n      }\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->path_time));\n     return offset;\n    }\n\n    const char * getType(){ return SETDRAWINGTRAJECTORY; };\n    const char * getMD5(){ return \"5b1621cd6a6a57a64c9ee8bfb64e3d14\"; };\n\n  };\n\n  class SetDrawingTrajectoryResponse : public ros::Msg\n  {\n    public:\n      typedef bool _is_planned_type;\n      _is_planned_type is_planned;\n\n    SetDrawingTrajectoryResponse():\n      is_planned(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      union {\n        bool real;\n        uint8_t base;\n      } u_is_planned;\n      u_is_planned.real = this->is_planned;\n      *(outbuffer + offset + 0) = (u_is_planned.base >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->is_planned);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      union {\n        bool real;\n        uint8_t base;\n      } u_is_planned;\n      u_is_planned.base = 0;\n      u_is_planned.base |= ((uint8_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      this->is_planned = u_is_planned.real;\n      offset += sizeof(this->is_planned);\n     return offset;\n    }\n\n    const char * getType(){ return SETDRAWINGTRAJECTORY; };\n    const char * getMD5(){ return \"2638cc2443b1469b0e9e152083d7128d\"; };\n\n  };\n\n  class SetDrawingTrajectory {\n    public:\n    typedef SetDrawingTrajectoryRequest Request;\n    typedef SetDrawingTrajectoryResponse Response;\n  };\n\n}\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/open_manipulator_msgs/SetJointPosition.h",
    "content": "#ifndef _ROS_SERVICE_SetJointPosition_h\n#define _ROS_SERVICE_SetJointPosition_h\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"open_manipulator_msgs/JointPosition.h\"\n\nnamespace open_manipulator_msgs\n{\n\nstatic const char SETJOINTPOSITION[] = \"open_manipulator_msgs/SetJointPosition\";\n\n  class SetJointPositionRequest : public ros::Msg\n  {\n    public:\n      typedef const char* _planning_group_type;\n      _planning_group_type planning_group;\n      typedef open_manipulator_msgs::JointPosition _joint_position_type;\n      _joint_position_type joint_position;\n      typedef float _path_time_type;\n      _path_time_type path_time;\n\n    SetJointPositionRequest():\n      planning_group(\"\"),\n      joint_position(),\n      path_time(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      uint32_t length_planning_group = strlen(this->planning_group);\n      varToArr(outbuffer + offset, length_planning_group);\n      offset += 4;\n      memcpy(outbuffer + offset, this->planning_group, length_planning_group);\n      offset += length_planning_group;\n      offset += this->joint_position.serialize(outbuffer + offset);\n      offset += serializeAvrFloat64(outbuffer + offset, this->path_time);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      uint32_t length_planning_group;\n      arrToVar(length_planning_group, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_planning_group; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_planning_group-1]=0;\n      this->planning_group = (char *)(inbuffer + offset-1);\n      offset += length_planning_group;\n      offset += this->joint_position.deserialize(inbuffer + offset);\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->path_time));\n     return offset;\n    }\n\n    const char * getType(){ return SETJOINTPOSITION; };\n    const char * getMD5(){ return \"ab867938df63c0b7946cf0ff4eeddfcc\"; };\n\n  };\n\n  class SetJointPositionResponse : public ros::Msg\n  {\n    public:\n      typedef bool _is_planned_type;\n      _is_planned_type is_planned;\n\n    SetJointPositionResponse():\n      is_planned(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      union {\n        bool real;\n        uint8_t base;\n      } u_is_planned;\n      u_is_planned.real = this->is_planned;\n      *(outbuffer + offset + 0) = (u_is_planned.base >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->is_planned);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      union {\n        bool real;\n        uint8_t base;\n      } u_is_planned;\n      u_is_planned.base = 0;\n      u_is_planned.base |= ((uint8_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      this->is_planned = u_is_planned.real;\n      offset += sizeof(this->is_planned);\n     return offset;\n    }\n\n    const char * getType(){ return SETJOINTPOSITION; };\n    const char * getMD5(){ return \"2638cc2443b1469b0e9e152083d7128d\"; };\n\n  };\n\n  class SetJointPosition {\n    public:\n    typedef SetJointPositionRequest Request;\n    typedef SetJointPositionResponse Response;\n  };\n\n}\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/open_manipulator_msgs/SetKinematicsPose.h",
    "content": "#ifndef _ROS_SERVICE_SetKinematicsPose_h\n#define _ROS_SERVICE_SetKinematicsPose_h\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"open_manipulator_msgs/KinematicsPose.h\"\n\nnamespace open_manipulator_msgs\n{\n\nstatic const char SETKINEMATICSPOSE[] = \"open_manipulator_msgs/SetKinematicsPose\";\n\n  class SetKinematicsPoseRequest : public ros::Msg\n  {\n    public:\n      typedef const char* _planning_group_type;\n      _planning_group_type planning_group;\n      typedef const char* _end_effector_name_type;\n      _end_effector_name_type end_effector_name;\n      typedef open_manipulator_msgs::KinematicsPose _kinematics_pose_type;\n      _kinematics_pose_type kinematics_pose;\n      typedef float _path_time_type;\n      _path_time_type path_time;\n\n    SetKinematicsPoseRequest():\n      planning_group(\"\"),\n      end_effector_name(\"\"),\n      kinematics_pose(),\n      path_time(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      uint32_t length_planning_group = strlen(this->planning_group);\n      varToArr(outbuffer + offset, length_planning_group);\n      offset += 4;\n      memcpy(outbuffer + offset, this->planning_group, length_planning_group);\n      offset += length_planning_group;\n      uint32_t length_end_effector_name = strlen(this->end_effector_name);\n      varToArr(outbuffer + offset, length_end_effector_name);\n      offset += 4;\n      memcpy(outbuffer + offset, this->end_effector_name, length_end_effector_name);\n      offset += length_end_effector_name;\n      offset += this->kinematics_pose.serialize(outbuffer + offset);\n      offset += serializeAvrFloat64(outbuffer + offset, this->path_time);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      uint32_t length_planning_group;\n      arrToVar(length_planning_group, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_planning_group; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_planning_group-1]=0;\n      this->planning_group = (char *)(inbuffer + offset-1);\n      offset += length_planning_group;\n      uint32_t length_end_effector_name;\n      arrToVar(length_end_effector_name, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_end_effector_name; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_end_effector_name-1]=0;\n      this->end_effector_name = (char *)(inbuffer + offset-1);\n      offset += length_end_effector_name;\n      offset += this->kinematics_pose.deserialize(inbuffer + offset);\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->path_time));\n     return offset;\n    }\n\n    const char * getType(){ return SETKINEMATICSPOSE; };\n    const char * getMD5(){ return \"c4791502d3cd986f50c19faec2e660dc\"; };\n\n  };\n\n  class SetKinematicsPoseResponse : public ros::Msg\n  {\n    public:\n      typedef bool _is_planned_type;\n      _is_planned_type is_planned;\n\n    SetKinematicsPoseResponse():\n      is_planned(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      union {\n        bool real;\n        uint8_t base;\n      } u_is_planned;\n      u_is_planned.real = this->is_planned;\n      *(outbuffer + offset + 0) = (u_is_planned.base >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->is_planned);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      union {\n        bool real;\n        uint8_t base;\n      } u_is_planned;\n      u_is_planned.base = 0;\n      u_is_planned.base |= ((uint8_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      this->is_planned = u_is_planned.real;\n      offset += sizeof(this->is_planned);\n     return offset;\n    }\n\n    const char * getType(){ return SETKINEMATICSPOSE; };\n    const char * getMD5(){ return \"2638cc2443b1469b0e9e152083d7128d\"; };\n\n  };\n\n  class SetKinematicsPose {\n    public:\n    typedef SetKinematicsPoseRequest Request;\n    typedef SetKinematicsPoseResponse Response;\n  };\n\n}\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/planar_libs/include/planar_libs/planar.h",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef PLANAR_H_\n#define PLANAR_H_\n\n#include \"planar_custom_trajectory.h\"\n#include \"planar_dynamixel.h\"\n#include \"planar_kinematics.h\"\n\n#define CUSTOM_TRAJECTORY_SIZE 4\n#define CUSTOM_TRAJECTORY_LINE    \"custom_trajectory_line\"\n#define CUSTOM_TRAJECTORY_CIRCLE  \"custom_trajectory_circle\"\n#define CUSTOM_TRAJECTORY_RHOMBUS \"custom_trajectory_rhombus\"\n#define CUSTOM_TRAJECTORY_HEART   \"custom_trajectory_heart\"\n\n#define DXL_SIZE 3\n#define JOINT_DYNAMIXEL \"joint_dxl\"\n\n#define RECEIVE_RATE 0.100 //s\n#define CONTROL_RATE 0.010 //s\n\n#define X_AXIS robotis_manipulator::math::vector3(1.0, 0.0, 0.0)\n#define Y_AXIS robotis_manipulator::math::vector3(0.0, 1.0, 0.0)\n#define Z_AXIS robotis_manipulator::math::vector3(0.0, 0.0, 1.0)\n\nclass Planar : public robotis_manipulator::RobotisManipulator\n{\nprivate:\n  robotis_manipulator::Kinematics *kinematics_;\n  robotis_manipulator::JointActuator *joint_;  \n  robotis_manipulator::CustomTaskTrajectory *custom_trajectory_[CUSTOM_TRAJECTORY_SIZE];\n\n  bool using_actual_robot_state_;\n  bool receive_data_flag_ = false;\n  double prev_receive_time_ = 0.0;\n  double prev_control_time_ = 0.0;\n\npublic:\n  Planar();\n  virtual ~Planar();\n\n  void initDebug();\n  void initOpenManipulator(bool using_actual_robot_state, \n                           STRING usb_port = \"/dev/ttyUSB0\", \n                           STRING baud_rate = \"1000000\", \n                           float control_rate = CONTROL_RATE);\n  void processOpenManipulator(double present_time);\n\n  bool getUsingActualRobotState();\n  bool getReceiveDataFlag();\n  double getPrevReceiveTime();\n\n  void setReceiveDataFlag(bool receive_data_flag);\n  void setPrevReceiveTime(double prev_receive_time);\n};\n\n#endif // PLANAR_H_\n\n\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/planar_libs/include/planar_libs/planar_custom_trajectory.h",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef PLANAR_CUSTOM_TRAJECTORY_H_\n#define PLANAR_CUSTOM_TRAJECTORY_H_\n\n#if defined(__OPENCR__)\n  #include <RobotisManipulator.h>\n#else\n  #include <robotis_manipulator/robotis_manipulator.h>\n#endif\n\nusing namespace robotis_manipulator;\nusing namespace Eigen;\n\nnamespace planar_custom_trajectory\n{\n  \nenum AXIS{\n\tX_AXIS,\n\tY_AXIS,\n\tZ_AXIS,\n};\n\n\n/*****************************************************************************\n** Line\n*****************************************************************************/\nclass Line : public robotis_manipulator::CustomTaskTrajectory\n{\nprivate:\n  TaskWaypoint start_pose_;\n  TaskWaypoint goal_pose_;\n\n  double acc_dec_time_;\n  double move_time_;\n  std::vector<double> vel_max_;\n\npublic:\n\tLine() {}\n\tvirtual ~Line() {}\n\n  void initLine(double move_time, TaskWaypoint start, TaskWaypoint delta);\n  TaskWaypoint drawLine(double time_var);\n\n  virtual void setOption(const void *arg);\n  virtual void makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg);\n  virtual TaskWaypoint getTaskWaypoint(double tick);\n};\n\n\n/*****************************************************************************\n** Circle\n*****************************************************************************/\nclass Circle : public robotis_manipulator::CustomTaskTrajectory\n{\nprivate:\n  robotis_manipulator::MinimumJerk path_generator_;\n  VectorXd coefficient_;\n\n  TaskWaypoint start_pose_;\n  TaskWaypoint goal_pose_;\n\n  double radius_;\n  double start_angular_position_;\n  double revolution_;\n\npublic:\n\tCircle() {}\n\tvirtual ~Circle() {}\n\n  void initCircle(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position);\n  TaskWaypoint drawCircle(double time_var);\n\n  virtual void setOption(const void *arg);\n  virtual void makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg);\n  virtual TaskWaypoint getTaskWaypoint(double tick);\n};\n\n\n/*****************************************************************************\n** Rhombus\n*****************************************************************************/\nclass Rhombus : public robotis_manipulator::CustomTaskTrajectory\n{\nprivate:\n  robotis_manipulator::MinimumJerk path_generator_;\n  VectorXd coefficient_;\n\n  TaskWaypoint start_pose_;\n  TaskWaypoint goal_pose_;\n\n  double radius_;\n  double start_angular_position_;\n  double revolution_;\n\npublic:\n\tRhombus() {}\n\tvirtual ~Rhombus() {}\n\n  void initRhombus(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position);\n  TaskWaypoint drawRhombus(double time_var);\n\n  virtual void setOption(const void *arg);\n  virtual void makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg);\n  virtual TaskWaypoint getTaskWaypoint(double tick);\n};\n\n\n/*****************************************************************************\n** Heart\n*****************************************************************************/\nclass Heart : public robotis_manipulator::CustomTaskTrajectory\n{\nprivate:\n  robotis_manipulator::MinimumJerk path_generator_;\n  VectorXd coefficient_;\n\n  TaskWaypoint start_pose_;\n  TaskWaypoint goal_pose_;\n\n  double radius_;\n  double start_angular_position_;\n  double revolution_;\n\npublic:\n\tHeart() {}\n\tvirtual ~Heart() {}\n\n  void initHeart(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position);\n  TaskWaypoint drawHeart(double tick);\n\n  virtual void setOption(const void *arg);\n  virtual void makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg);\n  virtual TaskWaypoint getTaskWaypoint(double tick);\n};\n\n\n} // namespace planar_custom_trajectory\n#endif // PLANAR_CUSTOM_TRAJECTORY_H_\n\n\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/planar_libs/include/planar_libs/planar_dynamixel.h",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef PLANAR_DYNAMIXEL_H_\n#define PLANAR_DYNAMIXEL_H_\n\n#if defined(__OPENCR__)\n  #include <RobotisManipulator.h>\n  #include <DynamixelWorkbench.h>\n#else\n  #include <robotis_manipulator/robotis_manipulator.h>\n  #include <dynamixel_workbench_toolbox/dynamixel_workbench.h>\n#endif\n\nnamespace planar_dynamixel\n{\n\n#define SYNC_WRITE_HANDLER 0\n#define SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT 0\n\n//#define CONTROL_LOOP_TIME 10;    //ms\n\n// Protocol 2.0\n#define ADDR_PRESENT_CURRENT_2 126\n#define ADDR_PRESENT_VELOCITY_2 128\n#define ADDR_PRESENT_POSITION_2 132\n#define ADDR_VELOCITY_TRAJECTORY_2 136\n#define ADDR_POSITION_TRAJECTORY_2 140\n#define ADDR_PROFILE_ACCELERATION_2 108\n#define ADDR_PROFILE_VELOCITY_2 112\n#define ADDR_GOAL_POSITION_2 116\n\n\n#define LENGTH_PRESENT_CURRENT_2 2\n#define LENGTH_PRESENT_VELOCITY_2 4\n#define LENGTH_PRESENT_POSITION_2 4\n#define LENGTH_VELOCITY_TRAJECTORY_2 4\n#define LENGTH_POSITION_TRAJECTORY_2 4\n#define LENGTH_PROFILE_ACCELERATION_2 4\n#define LENGTH_PROFILE_VELOCITY_2 4\n#define LENGTH_GOAL_POSITION_2 4\n\n\n// Protocol 1.0\n#define ADDR_PRESENT_CURRENT_1 = 40;\n#define ADDR_PRESENT_VELOCITY_1 = 38;\n#define ADDR_PRESENT_POSITION_1 = 36;\n\n#define LENGTH_PRESENT_CURRENT_1 = 2;\n#define LENGTH_PRESENT_VELOCITY_1 = 2;\n#define LENGTH_PRESENT_POSITION_1 = 2;\n\ntypedef struct\n{\n  std::vector<uint8_t> id;\n  uint8_t num;\n} Joint;\n\nclass JointDynamixel : public robotis_manipulator::JointActuator\n{\nprivate:\n  DynamixelWorkbench *dynamixel_workbench_;\n  Joint dynamixel_;\n\npublic:\n  JointDynamixel(){}\n  virtual ~JointDynamixel(){}\n\n\n  /*****************************************************************************\n  ** Joint Dynamixel Control Functions\n  *****************************************************************************/\n  virtual void init(std::vector<uint8_t> actuator_id, const void *arg);\n  virtual void setMode(std::vector<uint8_t> actuator_id, const void *arg);\n  virtual std::vector<uint8_t> getId();\n\n  virtual void enable();\n  virtual void disable();\n\n  virtual bool sendJointActuatorValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector);\n  virtual std::vector<robotis_manipulator::ActuatorValue> receiveJointActuatorValue(std::vector<uint8_t> actuator_id);\n\n\n  /*****************************************************************************\n  ** Functions called in Joint Dynamixel Control Functions\n  *****************************************************************************/\n  bool initialize(std::vector<uint8_t> actuator_id, STRING dxl_device_name, STRING dxl_baud_rate);\n  bool setOperatingMode(std::vector<uint8_t> actuator_id, STRING dynamixel_mode = \"position_mode\");\n  bool setSDKHandler(uint8_t actuator_id);\n  bool writeProfileValue(std::vector<uint8_t> actuator_id, STRING profile_mode, uint32_t value);\n  bool writeGoalPosition(std::vector<uint8_t> actuator_id, std::vector<double> radian_vector);\n  std::vector<robotis_manipulator::ActuatorValue> receiveAllDynamixelValue(std::vector<uint8_t> actuator_id);\n};\n\nclass JointDynamixelProfileControl : public robotis_manipulator::JointActuator\n{\nprivate:\n  DynamixelWorkbench *dynamixel_workbench_;\n  Joint dynamixel_;\n  float control_loop_time_; // unit: ms\n  std::map<uint8_t, robotis_manipulator::ActuatorValue> previous_goal_value_;\n\npublic:\n  JointDynamixelProfileControl(float control_loop_time = 0.010);\n  virtual ~JointDynamixelProfileControl(){}\n\n\n  /*****************************************************************************\n  ** Joint Dynamixel Profile Control Functions\n  *****************************************************************************/\n  virtual void init(std::vector<uint8_t> actuator_id, const void *arg);\n  virtual void setMode(std::vector<uint8_t> actuator_id, const void *arg);\n  virtual std::vector<uint8_t> getId();\n\n  virtual void enable();\n  virtual void disable();\n\n  virtual bool sendJointActuatorValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector);\n  virtual std::vector<robotis_manipulator::ActuatorValue> receiveJointActuatorValue(std::vector<uint8_t> actuator_id);\n\n\n  /*****************************************************************************\n  ** Functions called in Joint Dynamixel Profile Control Functions\n  *****************************************************************************/\n  bool initialize(std::vector<uint8_t> actuator_id, STRING dxl_device_name, STRING dxl_baud_rate);\n  bool setOperatingMode(std::vector<uint8_t> actuator_id, STRING dynamixel_mode = \"position_mode\");\n  bool setSDKHandler(uint8_t actuator_id);\n  bool writeProfileValue(std::vector<uint8_t> actuator_id, STRING profile_mode, uint32_t value);\n  bool writeGoalProfilingControlValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector);\n  std::vector<robotis_manipulator::ActuatorValue> receiveAllDynamixelValue(std::vector<uint8_t> actuator_id);\n};\n\nclass ToolDynamixel : public robotis_manipulator::ToolActuator\n{\n private:\n  DynamixelWorkbench *dynamixel_workbench_;\n  Joint dynamixel_;\n\n public:\n  ToolDynamixel() {}\n  virtual ~ToolDynamixel() {}\n\n\n  /*****************************************************************************\n  ** Tool Dynamixel Control Functions\n  *****************************************************************************/\n  virtual void init(uint8_t actuator_id, const void *arg);\n  virtual void setMode(const void *arg);\n  virtual uint8_t getId();\n\n  virtual void enable();\n  virtual void disable();\n\n  virtual bool sendToolActuatorValue(robotis_manipulator::ActuatorValue value);\n  virtual robotis_manipulator::ActuatorValue receiveToolActuatorValue();\n\n\n  /*****************************************************************************\n  ** Functions called in Tool Dynamixel Profile Control Functions\n  *****************************************************************************/\n  bool initialize(uint8_t actuator_id, STRING dxl_device_name, STRING dxl_baud_rate);\n  bool setOperatingMode(STRING dynamixel_mode = \"position_mode\");\n  bool writeProfileValue(STRING profile_mode, uint32_t value);\n  bool setSDKHandler();\n  bool writeGoalPosition(double radian);\n  double receiveDynamixelValue();\n};\n\n} // namespace planar_dynamixel\n#endif // PLANAR_DYNAMIXEL_H_\n\n\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/planar_libs/include/planar_libs/planar_kinematics.h",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef PLANAR_KINEMATICS_H_\n#define PLANAR_KINEMATICS_H_\n\n#if defined(__OPENCR__)\n  #include <RobotisManipulator.h>\n#else\n  #include <robotis_manipulator/robotis_manipulator.h>\n#endif\n\nusing namespace Eigen;\nusing namespace robotis_manipulator;\n\nnamespace planar_kinematics\n{\n\n/*****************************************************************************\n** Kinematics Solver Using Geometry\n*****************************************************************************/\nclass SolverUsingGeometry : public robotis_manipulator::Kinematics\n{\nprivate:\n  bool inverseKinematicsSolverUsingGeometry(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue>* goal_joint_value);\n\npublic:\n  SolverUsingGeometry(){}\n  virtual ~SolverUsingGeometry(){}\n\n  virtual void setOption(const void *arg);\n  virtual MatrixXd jacobian(Manipulator *manipulator, Name tool_name);\n  virtual void solveForwardKinematics(Manipulator *manipulator);\n  virtual bool solveInverseKinematics(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue>* goal_joint_value);\n};\n\n} // namespace planar_kinematics\n\n#endif // PLANAR_KINEMATICS_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/planar_libs/src/planar.cpp",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include \"../include/planar_libs/planar.h\"\n\nPlanar::Planar() {}\nPlanar::~Planar()\n{\n  delete kinematics_;\n  delete joint_;\n  for(uint8_t index = 0; index < CUSTOM_TRAJECTORY_SIZE; index++)\n    delete custom_trajectory_[index];\n}\n\nvoid Planar::initDebug()\n{\n  DEBUG.begin(57600); // Using Serial4(= SerialBT2)\n  log::print(\"OpenManipulator Debugging Port\");\n}\n\nvoid Planar::initOpenManipulator(bool using_actual_robot_state, STRING usb_port, STRING baud_rate, float control_rate)\n{\n  /*****************************************************************************\n  ** Set if using actual robot\n  *****************************************************************************/\n  using_actual_robot_state_ = using_actual_robot_state;  \n\n  /*****************************************************************************\n  ** Initialize Manipulator Parameters\n  *****************************************************************************/\n  addWorld(\"world\",   // world name\n           \"joint1\"); // child name\n\n  addJoint(\"joint1\",  // my name\n           \"world\",   // parent name\n           \"joint4\",  // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Z_AXIS,    // axis of rotation\n           1);        // actuator id\n\n  addJoint(\"joint2\",  // my name\n           \"world\",   // parent name\n           \"joint5\",  // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Y_AXIS,    // axis of rotation\n           2);        // actuator id\n\n  addJoint(\"joint3\",  // my name\n           \"world\",   // parent name\n           \"joint6\",  // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Y_AXIS,    // axis of rotation\n           3);        // actuator id\n\n  addJoint(\"joint4\",  // my name\n           \"joint1\",  // parent name\n           \"joint7\",  // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Y_AXIS,    // axis of rotation\n           -1);       // actuator id\n\n  addJoint(\"joint5\",  // my name\n           \"joint2\",  // parent name\n           \"joint8\",    // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Y_AXIS,    // axis of rotation\n           -1);       // actuator id\n\n  addJoint(\"joint6\",  // my name\n           \"joint3\",  // parent name\n           \"joint9\",    // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Y_AXIS,    // axis of rotation\n           -1);       // actuator id\n\n  addJoint(\"joint7\",  // my name\n           \"joint4\",  // parent name\n           \"tool\",    // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Y_AXIS,    // axis of rotation\n           -1);       // actuator id\n\n  addTool(\"tool\",     // my name\n          \"joint7\",   // Not used\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           -1);       // actuator id\n\n  /*****************************************************************************\n  ** Initialize Kinematics \n  *****************************************************************************/\n  kinematics_ = new planar_kinematics::SolverUsingGeometry();\n  addKinematics(kinematics_);\n\n  /*****************************************************************************\n  ** Initialize Custom Trajectory\n  *****************************************************************************/\n  custom_trajectory_[0] = new planar_custom_trajectory::Line();\n  custom_trajectory_[1] = new planar_custom_trajectory::Circle();\n  custom_trajectory_[2] = new planar_custom_trajectory::Rhombus();\n  custom_trajectory_[3] = new planar_custom_trajectory::Heart();\n\n  addCustomTrajectory(CUSTOM_TRAJECTORY_LINE, custom_trajectory_[0]);\n  addCustomTrajectory(CUSTOM_TRAJECTORY_CIRCLE, custom_trajectory_[1]);\n  addCustomTrajectory(CUSTOM_TRAJECTORY_RHOMBUS, custom_trajectory_[2]);\n  addCustomTrajectory(CUSTOM_TRAJECTORY_HEART, custom_trajectory_[3]);\n\n  if (using_actual_robot_state_)\n  {\n    /*****************************************************************************\n    ** Initialize ㅓoint Actuator\n    *****************************************************************************/\n    joint_ = new planar_dynamixel::JointDynamixelProfileControl(control_rate);\n\n    // Set communication arguments \n    STRING dxl_comm_arg[2] = {usb_port, baud_rate};\n    void *p_dxl_comm_arg = &dxl_comm_arg; \n\n    // Set joint actuator id \n    std::vector<uint8_t> jointDxlId;\n    jointDxlId.push_back(1);\n    jointDxlId.push_back(2);\n    jointDxlId.push_back(3);\n    addJointActuator(JOINT_DYNAMIXEL, joint_, jointDxlId, p_dxl_comm_arg);\n\n    // set joint actuator parameter\n    STRING joint_dxl_mode_arg = \"position_mode\";\n    void *p_joint_dxl_mode_arg = &joint_dxl_mode_arg;\n    setJointActuatorMode(JOINT_DYNAMIXEL, jointDxlId, p_joint_dxl_mode_arg);\n\n    /*****************************************************************************\n    ** Enable actuators and Receive actuator values \n    *****************************************************************************/\n    // Eanble all actuators \n    enableAllActuator();\n    \n    // Receive current angles from all actuators \n    receiveAllJointActuatorValue();\n  }\n}\n\n/*****************************************************************************\n** Process actuator values received from external controllers\n*****************************************************************************/\nvoid Planar::processOpenManipulator(double present_time)  \n{\n  if (present_time - prev_control_time_ >= CONTROL_RATE)  \n  {\n    JointWaypoint goal_joint_value = getJointGoalValueFromTrajectory(present_time);\n    if(goal_joint_value.size() != 0) sendAllJointActuatorValue(goal_joint_value);   \n\n    // Set previous control time\n    prev_control_time_ = millis()/1000.0;\n  }\n}\n\n/*****************************************************************************\n** State Functions\n*****************************************************************************/\n// Check if using acutal robot \nbool Planar::getUsingActualRobotState() \n{\n  return using_actual_robot_state_;\n}\n\n/* Check if the program read data within control rate) */\nbool Planar::getReceiveDataFlag()  \n{\n  return receive_data_flag_;\n}\n\n/* Get the previous time when data were received */\ndouble Planar::getPrevReceiveTime() \n{\n  return prev_receive_time_;\n}\n\n/* Set whether data were received or not */\nvoid Planar::setReceiveDataFlag(bool receive_data_flag) \n{\n  receive_data_flag_ = receive_data_flag;\n}\n\n/* Set the previous time when data were received */\nvoid Planar::setPrevReceiveTime(double prev_receive_time)  \n{\n  prev_receive_time_ = prev_receive_time;\n}\n\n\n\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/planar_libs/src/planar_custom_trajectory.cpp",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include \"../include/planar_libs/planar_custom_trajectory.h\"\n\nusing namespace planar_custom_trajectory;\nusing namespace Eigen;\n\n\n/*****************************************************************************\n** Line\n*****************************************************************************/\nvoid Line::initLine(double move_time, TaskWaypoint start, TaskWaypoint delta)\n{\n  move_time_ = move_time;\n  acc_dec_time_ = move_time_ * 0.2;\n  vel_max_.resize(3);\n\n  TaskWaypoint start_to_goal;\n\n  start_pose_ = start;\n\n  goal_pose_ .kinematic.orientation = start_pose_.kinematic.orientation;\n  goal_pose_ .kinematic.position = start.kinematic.position + delta.kinematic.position;\n\n  vel_max_.at(X_AXIS) = delta.kinematic.position(X_AXIS)/(move_time_ - acc_dec_time_);\n  vel_max_.at(Y_AXIS) = delta.kinematic.position(Y_AXIS)/(move_time_ - acc_dec_time_);\n  vel_max_.at(Z_AXIS) = delta.kinematic.position(Z_AXIS)/(move_time_ - acc_dec_time_);\n}\n\nTaskWaypoint Line::drawLine(double time_var)\n{\n  TaskWaypoint pose;\n\n  if(acc_dec_time_ >= time_var)\n  {\n    pose.kinematic.position(X_AXIS) = 0.5*vel_max_.at(X_AXIS)*pow(time_var, 2)/acc_dec_time_ + start_pose_.kinematic.position(X_AXIS);\n    pose.kinematic.position(Y_AXIS) = 0.5*vel_max_.at(Y_AXIS)*pow(time_var, 2)/acc_dec_time_ + start_pose_.kinematic.position(Y_AXIS);\n    pose.kinematic.position(Z_AXIS) = 0.5*vel_max_.at(Z_AXIS)*pow(time_var, 2)/acc_dec_time_ + start_pose_.kinematic.position(Z_AXIS);\n  }\n  else if(time_var > acc_dec_time_ && (move_time_ - acc_dec_time_) >= time_var )\n  {\n    pose.kinematic.position(X_AXIS) = vel_max_.at(X_AXIS)*(time_var-(acc_dec_time_*0.5)) + start_pose_.kinematic.position(X_AXIS);\n    pose.kinematic.position(Y_AXIS) = vel_max_.at(Y_AXIS)*(time_var-(acc_dec_time_*0.5)) + start_pose_.kinematic.position(Y_AXIS);\n    pose.kinematic.position(Z_AXIS) = vel_max_.at(Z_AXIS)*(time_var-(acc_dec_time_*0.5)) + start_pose_.kinematic.position(Z_AXIS);\n  }\n  else if(time_var > (move_time_ - acc_dec_time_) && (time_var < move_time_))\n  {\n    pose.kinematic.position(X_AXIS) = goal_pose_.kinematic.position(X_AXIS) - vel_max_.at(X_AXIS)*0.5/acc_dec_time_*(pow((move_time_-time_var),2));\n    pose.kinematic.position(Y_AXIS) = goal_pose_.kinematic.position(Y_AXIS) - vel_max_.at(Y_AXIS)*0.5/acc_dec_time_*(pow((move_time_-time_var),2));\n    pose.kinematic.position(Z_AXIS) = goal_pose_.kinematic.position(Z_AXIS) - vel_max_.at(Z_AXIS)*0.5/acc_dec_time_*(pow((move_time_-time_var),2));\n  }\n  else if(time_var <= move_time_)\n  {\n    pose.kinematic.position(X_AXIS) = goal_pose_.kinematic.position(X_AXIS);\n    pose.kinematic.position(Y_AXIS) = goal_pose_.kinematic.position(Y_AXIS);\n    pose.kinematic.position(Z_AXIS) = goal_pose_.kinematic.position(Z_AXIS);\n  }\n\n  pose.kinematic.orientation = start_pose_.kinematic.orientation;\n  pose.dynamic.linear.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.linear.acceleration = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.acceleration = Eigen::Vector3d::Zero(3);\n\n  return pose;\n}\n\nTaskWaypoint Line::getTaskWaypoint(double tick)\n{\n  return drawLine(tick);\n}\n\n\nvoid Line::makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg)\n{\n  TaskWaypoint *c_arg = (TaskWaypoint *)arg;\n  initLine(move_time, start, c_arg[0]);\n}\nvoid Line::setOption(const void *arg) {}\n\n\n/*****************************************************************************\n** Circle\n*****************************************************************************/\nvoid Circle::initCircle(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position)\n{\n  start_pose_ = start;\n\n  radius_ = radius;\n  revolution_ = revolution;\n  start_angular_position_ = start_angular_position;\n\n  Point drawingStart, drawingGoal;\n\n  drawingStart.position = 0.0;\n  drawingStart.velocity = 0.0;\n  drawingStart.acceleration = 0.0;\n  drawingStart.effort = 0.0;\n\n  drawingGoal.position = revolution_ * 2*M_PI;\n  drawingGoal.velocity = 0.0;\n  drawingGoal.acceleration = 0.0;\n  drawingGoal.effort = 0.0;\n\n  path_generator_.calcCoefficient(drawingStart, drawingGoal, move_time);\n  coefficient_ = path_generator_.getCoefficient();\n}\n\nTaskWaypoint Circle::drawCircle(double tick)\n{\n  // get time variable\n  double get_time_var = 0.0;\n\n  get_time_var = coefficient_(0) +\n                 coefficient_(1) * pow(tick, 1) +\n                 coefficient_(2) * pow(tick, 2) +\n                 coefficient_(3) * pow(tick, 3) +\n                 coefficient_(4) * pow(tick, 4) +\n                 coefficient_(5) * pow(tick, 5);\n\n  // set drawing trajectory\n  TaskWaypoint pose;\n\n  double diff_pose[2];\n\n  diff_pose[0] = (cos(get_time_var)-1)*cos(start_angular_position_) - sin(get_time_var)*sin(start_angular_position_);\n  diff_pose[1] = (cos(get_time_var)-1)*sin(start_angular_position_) + sin(get_time_var)*cos(start_angular_position_);\n\n  pose.kinematic.position(X_AXIS) = start_pose_.kinematic.position(X_AXIS) + radius_ * diff_pose[0];\n  pose.kinematic.position(Y_AXIS) = start_pose_.kinematic.position(Y_AXIS) + radius_ * diff_pose[1];\n  pose.kinematic.position(Z_AXIS) = start_pose_.kinematic.position(Z_AXIS);\n\n  pose.kinematic.orientation = start_pose_.kinematic.orientation;\n\n  pose.dynamic.linear.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.linear.acceleration = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.acceleration = Eigen::Vector3d::Zero(3);\n\n  return pose;\n}\n\nTaskWaypoint Circle::getTaskWaypoint(double tick)\n{\n  return drawCircle(tick);\n}\n\nvoid Circle::makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg)\n{\n  double *get_arg_ = (double *)arg;\n  initCircle(move_time, start, get_arg_[0], get_arg_[1], get_arg_[2]);\n}\n\nvoid Circle::setOption(const void *arg){}\n\n\n/*****************************************************************************\n** Rhombus\n*****************************************************************************/\nvoid Rhombus::initRhombus(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position)\n{\n  start_pose_ = start;\n\n  radius_ = radius;\n  revolution_ = revolution;\n  start_angular_position_ = start_angular_position;\n\n  Point drawingStart, drawingGoal;\n\n  drawingStart.position = 0.0;\n  drawingStart.velocity = 0.0;\n  drawingStart.acceleration = 0.0;\n  drawingStart.effort = 0.0;\n\n  drawingGoal.position = revolution_ * 2*M_PI;\n  drawingGoal.velocity = 0.0;\n  drawingGoal.acceleration = 0.0;\n  drawingGoal.effort = 0.0;\n\n  path_generator_.calcCoefficient(drawingStart, drawingGoal, move_time);\n  coefficient_ = path_generator_.getCoefficient();\n}\n\n\nTaskWaypoint Rhombus::drawRhombus(double tick)\n{\n  // get time variable\n  double get_time_var = 0.0;\n\n  get_time_var = coefficient_(0) +\n                 coefficient_(1) * pow(tick, 1) +\n                 coefficient_(2) * pow(tick, 2) +\n                 coefficient_(3) * pow(tick, 3) +\n                 coefficient_(4) * pow(tick, 4) +\n                 coefficient_(5) * pow(tick, 5); \n\n  // set drawing trajectory\n  TaskWaypoint pose;\n  double diff_pose[2];\n  double traj[2];\n\n  while(true)\n  {\n    if (get_time_var < PI*2) break;\n    get_time_var = get_time_var - PI*2;\n  }\n\n  if (get_time_var >= 0 && get_time_var < PI/2){\n    traj[0] = - get_time_var / (PI/2);\n    traj[1] = - get_time_var / (PI/2);\n  } else if (get_time_var >= PI/2 && get_time_var < PI){\n    traj[0] = - get_time_var / (PI/2);\n    traj[1] = get_time_var / (PI/2) - 2;\n  } else if (get_time_var >= PI && get_time_var < PI*3/2){\n    traj[0] = get_time_var / (PI/2) - 4;\n    traj[1] = get_time_var / (PI/2) - 2;\n  } else {\n    traj[0] = get_time_var / (PI/2) - 4;\n    traj[1] = - get_time_var / (PI/2) + 4;\n  }\n  \n\n  diff_pose[0] = traj[0]*cos(start_angular_position_) - traj[1]*sin(start_angular_position_);\n  diff_pose[1] = traj[0]*sin(start_angular_position_) + traj[1]*cos(start_angular_position_);\n\n  pose.kinematic.position(X_AXIS) = start_pose_.kinematic.position(X_AXIS) + radius_ * diff_pose[0];\n  pose.kinematic.position(Y_AXIS) = start_pose_.kinematic.position(Y_AXIS) + radius_ * diff_pose[1];\n  pose.kinematic.position(Z_AXIS) = start_pose_.kinematic.position(Z_AXIS);\n\n  pose.kinematic.orientation = start_pose_.kinematic.orientation;\n\n  pose.dynamic.linear.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.linear.acceleration = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.acceleration = Eigen::Vector3d::Zero(3);\n\n  return pose;\n}\n\n\nvoid Rhombus::makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg)\n{\n  double *get_arg_ = (double *)arg;\n  initRhombus(move_time, start, get_arg_[0], get_arg_[1], get_arg_[2]);\n}\n\nTaskWaypoint Rhombus::getTaskWaypoint(double tick)\n{\n  return drawRhombus(tick);\n}\nvoid Rhombus::setOption(const void *arg){}\n\n\n/*****************************************************************************\n** Heart\n*****************************************************************************/\nvoid Heart::initHeart(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position)\n{\n  start_pose_ = start;\n\n  radius_ = radius;\n  revolution_ = revolution;\n  start_angular_position_ = start_angular_position;\n\n  Point drawingStart, drawingGoal;\n\n  drawingStart.position = 0.0;\n  drawingStart.velocity = 0.0;\n  drawingStart.acceleration = 0.0;\n  drawingStart.effort = 0.0;\n\n  drawingGoal.position = revolution_ * 2*M_PI;\n  drawingGoal.velocity = 0.0;\n  drawingGoal.acceleration = 0.0;\n  drawingGoal.effort = 0.0;\n\n  path_generator_.calcCoefficient(drawingStart, drawingGoal, move_time);\n  coefficient_ = path_generator_.getCoefficient();\n}\n\nTaskWaypoint Heart::drawHeart(double tick)\n{\n  // get time variable\n  double get_time_var = 0.0;\n\n  get_time_var = coefficient_(0) +\n                 coefficient_(1) * pow(tick, 1) +\n                 coefficient_(2) * pow(tick, 2) +\n                 coefficient_(3) * pow(tick, 3) +\n                 coefficient_(4) * pow(tick, 4) +\n                 coefficient_(5) * pow(tick, 5);\n\n  // set drawing trajectory\n  TaskWaypoint pose;\n  double diff_pose[2];\n  double traj[2];\n\n\tdouble shift_offset = - 5.0;\n\n  traj[0] = (shift_offset + (13*cos(get_time_var) - 5*cos(2*get_time_var) - 2*cos(3*get_time_var) - cos(4*get_time_var))) / 16;\n  traj[1] = (16*sin(get_time_var)*sin(get_time_var)*sin(get_time_var)) / 16;\n\n  diff_pose[0] = traj[0]*cos(start_angular_position_) - traj[1]*sin(start_angular_position_);\n  diff_pose[1] = traj[0]*sin(start_angular_position_) + traj[1]*cos(start_angular_position_);\n\n  pose.kinematic.position(X_AXIS) = start_pose_.kinematic.position(X_AXIS) + radius_ * diff_pose[0];\n  pose.kinematic.position(Y_AXIS) = start_pose_.kinematic.position(Y_AXIS) + radius_ * diff_pose[1];\n  pose.kinematic.position(Z_AXIS) = start_pose_.kinematic.position(Z_AXIS);\n\n  pose.kinematic.orientation = start_pose_.kinematic.orientation;\n\n  pose.dynamic.linear.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.linear.acceleration = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.acceleration = Eigen::Vector3d::Zero(3);\n\n  return pose;\n}\n\nvoid Heart::makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg)\n{\n  double *get_arg_ = (double *)arg;\n  initHeart(move_time, start, get_arg_[0], get_arg_[1], get_arg_[2]);\n}\nvoid Heart::setOption(const void *arg){}\n\nTaskWaypoint Heart::getTaskWaypoint(double tick)\n{\n  return drawHeart(tick);\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/planar_libs/src/planar_dynamixel.cpp",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include \"../include/planar_libs/planar_dynamixel.h\"\n\nusing namespace planar_dynamixel;\nusing namespace robotis_manipulator;\n\n/*****************************************************************************\n** Joint Dynamixel Control Functions\n*****************************************************************************/\nvoid JointDynamixel::init(std::vector<uint8_t> actuator_id, const void *arg)\n{\n  STRING *get_arg_ = (STRING *)arg;\n\n  bool result = JointDynamixel::initialize(actuator_id ,get_arg_[0], get_arg_[1]);\n\n  if (result == false)\n    return;\n}\n\nvoid JointDynamixel::setMode(std::vector<uint8_t> actuator_id, const void *arg)\n{\n  bool result = false;\n  // const char* log = NULL;\n\n  STRING *get_arg_ = (STRING *)arg;\n\n  if (get_arg_[0] == \"position_mode\" || get_arg_[0] == \"current_based_position_mode\")\n  {\n    result = JointDynamixel::setOperatingMode(actuator_id, get_arg_[0]);\n    if (result == false)\n      return;\n\n    result = JointDynamixel::setSDKHandler(actuator_id.at(0));\n    if (result == false)\n      return;\n  }\n  else\n  {\n    result = JointDynamixel::writeProfileValue(actuator_id, get_arg_[0], std::atoi(get_arg_[1].c_str()));\n    if (result == false)\n      return;\n  }\n  return;\n}\n\nstd::vector<uint8_t> JointDynamixel::getId()\n{\n  return dynamixel_.id;\n}\n\nvoid JointDynamixel::enable()\n{\n  const char* log = NULL;\n  bool result = false;\n  \n  for (uint32_t index = 0; index < dynamixel_.num; index++)\n  {\n    result = dynamixel_workbench_->torqueOn(dynamixel_.id.at(index), &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  enabled_state_ = true;\n}\n\nvoid JointDynamixel::disable()\n{\n  const char* log = NULL;\n  bool result = false;\n  \n  for (uint32_t index = 0; index < dynamixel_.num; index++)\n  {\n    result = dynamixel_workbench_->torqueOff(dynamixel_.id.at(index), &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  enabled_state_ = false;\n}\n\nbool JointDynamixel::sendJointActuatorValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector)\n{\n  bool result = false;\n\n  std::vector<double> radian_vector;\n  for(uint32_t index = 0; index < value_vector.size(); index++)\n  {\n    radian_vector.push_back(value_vector.at(index).position);\n  }\n  result = JointDynamixel::writeGoalPosition(actuator_id, radian_vector);\n  if (result == false)\n    return false;\n\n  return true;\n}\n\nstd::vector<robotis_manipulator::ActuatorValue> JointDynamixel::receiveJointActuatorValue(std::vector<uint8_t> actuator_id)\n{\n  return JointDynamixel::receiveAllDynamixelValue(actuator_id);\n}\n\n\n/*****************************************************************************\n** Functions called in Joint Dynamixel Control Functions\n*****************************************************************************/\nbool JointDynamixel::initialize(std::vector<uint8_t> actuator_id, STRING dxl_device_name, STRING dxl_baud_rate)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  STRING return_delay_time_st = \"Return_Delay_Time\";\n  const char * return_delay_time_char = return_delay_time_st.c_str();\n\n  dynamixel_.id = actuator_id;\n  dynamixel_.num = actuator_id.size();\n\n  dynamixel_workbench_ = new DynamixelWorkbench;\n\n  result = dynamixel_workbench_->init(dxl_device_name.c_str(), std::atoi(dxl_baud_rate.c_str()), &log);\n  if (result == false)\n  {\n    log::error(log);\n  }    \n\n  uint16_t get_model_number;\n  for (uint8_t index = 0; index < dynamixel_.num; index++)\n  {\n    uint8_t id = dynamixel_.id.at(index);\n    result = dynamixel_workbench_->ping(id, &get_model_number, &log);\n\n    if (result == false)\n    {\n      log::error(log);\n      log::error(\"Please check your Dynamixel ID\");\n    }\n    else\n    {\n      char str[100];\n      sprintf(str, \"Joint Dynamixel ID : %d, Model Name : %s\", id, dynamixel_workbench_->getModelName(id));\n      log::println(str);\n\n      result = dynamixel_workbench_->setVelocityBasedProfile(id, &log);\n      if(result == false)\n      {\n        log::error(log);\n        log::error(\"Please check your Dynamixel firmware version (v38~)\");\n      }\n\n      result = dynamixel_workbench_->writeRegister(id, return_delay_time_char, 0, &log);\n      if (result == false)\n      {\n        log::error(log);\n        log::error(\"Please check your Dynamixel firmware version\");\n      }\n    }\n  }\n  return true;\n}\n\nbool JointDynamixel::setOperatingMode(std::vector<uint8_t> actuator_id, STRING dynamixel_mode)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const uint32_t velocity = 0;\n  const uint32_t acceleration = 0;\n  const uint32_t current = 0;\n\n  if (dynamixel_mode == \"position_mode\")\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->jointMode(actuator_id.at(num), velocity, acceleration, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n  else if (dynamixel_mode == \"current_based_position_mode\")\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->currentBasedPositionMode(actuator_id.at(num), current, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n  else\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->jointMode(actuator_id.at(num), velocity, acceleration, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n\n  return true;\n}\n\nbool JointDynamixel::setSDKHandler(uint8_t actuator_id)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  result = dynamixel_workbench_->addSyncWriteHandler(actuator_id, \"Goal_Position\", &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->addSyncReadHandler(ADDR_PRESENT_CURRENT_2, \n                                                    (LENGTH_PRESENT_CURRENT_2 + LENGTH_PRESENT_VELOCITY_2 + LENGTH_PRESENT_POSITION_2), \n                                                    &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\nbool JointDynamixel::writeProfileValue(std::vector<uint8_t> actuator_id, STRING profile_mode, uint32_t value)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const char * char_profile_mode = profile_mode.c_str();\n\n  for (uint8_t num = 0; num < actuator_id.size(); num++)\n  {\n    result = dynamixel_workbench_->writeRegister(actuator_id.at(num), char_profile_mode, value, &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n\n  return true;\n}\n\nbool JointDynamixel::writeGoalPosition(std::vector<uint8_t> actuator_id, std::vector<double> radian_vector)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  uint8_t id_array[actuator_id.size()];\n  int32_t goal_position[actuator_id.size()];\n\n  for (uint8_t index = 0; index < actuator_id.size(); index++)\n  {\n    id_array[index] = actuator_id.at(index);\n    goal_position[index] = dynamixel_workbench_->convertRadian2Value(actuator_id.at(index), radian_vector.at(index));\n  }\n\n  result = dynamixel_workbench_->syncWrite(SYNC_WRITE_HANDLER, id_array, actuator_id.size(), goal_position, 1, &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\nstd::vector<robotis_manipulator::ActuatorValue> JointDynamixel::receiveAllDynamixelValue(std::vector<uint8_t> actuator_id)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  std::vector<robotis_manipulator::ActuatorValue> all_actuator;\n\n  uint8_t id_array[actuator_id.size()];\n  for (uint8_t index = 0; index < actuator_id.size(); index++)\n    id_array[index] = actuator_id.at(index);\n\n  int32_t get_current[actuator_id.size()];\n  int32_t get_velocity[actuator_id.size()];\n  int32_t get_position[actuator_id.size()];\n\n  result = dynamixel_workbench_->syncRead(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                          id_array,\n                                          actuator_id.size(),\n                                          &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                id_array,\n                                                actuator_id.size(),\n                                                ADDR_PRESENT_CURRENT_2,\n                                                LENGTH_PRESENT_CURRENT_2,\n                                                get_current,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                 id_array,\n                                                 actuator_id.size(),\n                                                ADDR_PRESENT_VELOCITY_2,\n                                                LENGTH_PRESENT_VELOCITY_2,\n                                                get_velocity,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                 id_array,\n                                                 actuator_id.size(),\n                                                ADDR_PRESENT_POSITION_2,\n                                                LENGTH_PRESENT_POSITION_2,\n                                                get_position,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  for (uint8_t index = 0; index < actuator_id.size(); index++)\n  {\n    robotis_manipulator::ActuatorValue actuator;\n    actuator.effort = dynamixel_workbench_->convertValue2Current(get_current[index]);\n    actuator.velocity = dynamixel_workbench_->convertValue2Velocity(actuator_id.at(index), get_velocity[index]);\n    actuator.position = dynamixel_workbench_->convertValue2Radian(actuator_id.at(index), get_position[index]);\n\n    all_actuator.push_back(actuator);\n  }\n\n  return all_actuator;\n}\n\n\n/*****************************************************************************\n** Joint Dynamixel Profile Control Functions\n*****************************************************************************/\nJointDynamixelProfileControl::JointDynamixelProfileControl(float control_loop_time)\n{\n  control_loop_time_ = control_loop_time;\n}\n\nvoid JointDynamixelProfileControl::init(std::vector<uint8_t> actuator_id, const void *arg)\n{\n  STRING *get_arg_ = (STRING *)arg;\n\n  bool result = JointDynamixelProfileControl::initialize(actuator_id ,get_arg_[0], get_arg_[1]);\n\n  if (result == false)\n    return;\n}\n\nvoid JointDynamixelProfileControl::setMode(std::vector<uint8_t> actuator_id, const void *arg)\n{\n  bool result = false;\n  // const char* log = NULL;\n\n  STRING *get_arg_ = (STRING *)arg;\n\n  if (get_arg_[0] == \"position_mode\" || get_arg_[0] == \"current_based_position_mode\")\n  {\n    result = JointDynamixelProfileControl::setOperatingMode(actuator_id, get_arg_[0]);\n    if (result == false)\n      return;\n\n    result = JointDynamixelProfileControl::setSDKHandler(actuator_id.at(0));\n    if (result == false)\n      return;\n  }\n  else\n  {\n    result = JointDynamixelProfileControl::writeProfileValue(actuator_id, get_arg_[0], std::atoi(get_arg_[1].c_str()));\n    if (result == false)\n      return;\n  }\n  return;\n}\n\nstd::vector<uint8_t> JointDynamixelProfileControl::getId()\n{\n  return dynamixel_.id;\n}\n\nvoid JointDynamixelProfileControl::enable()\n{\n  const char* log = NULL;\n  bool result = false;\n\n  for (uint32_t index = 0; index < dynamixel_.num; index++)\n  {\n    result = dynamixel_workbench_->torqueOn(dynamixel_.id.at(index), &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  enabled_state_ = true;\n}\n\nvoid JointDynamixelProfileControl::disable()\n{\n  const char* log = NULL;\n  bool result = false;\n\n  for (uint32_t index = 0; index < dynamixel_.num; index++)\n  {\n    result = dynamixel_workbench_->torqueOff(dynamixel_.id.at(index), &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  enabled_state_ = false;\n}\n\nbool JointDynamixelProfileControl::sendJointActuatorValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector)\n{\n  bool result = false;\n\n  result = JointDynamixelProfileControl::writeGoalProfilingControlValue(actuator_id, value_vector);\n  if (result == false)\n    return false;\n\n  return true;\n}\n\nstd::vector<robotis_manipulator::ActuatorValue> JointDynamixelProfileControl::receiveJointActuatorValue(std::vector<uint8_t> actuator_id)\n{\n  return JointDynamixelProfileControl::receiveAllDynamixelValue(actuator_id);\n}\n\n\n/*****************************************************************************\n** Functions called in Joint Dynamixel Profile Control Functions\n*****************************************************************************/\nbool JointDynamixelProfileControl::initialize(std::vector<uint8_t> actuator_id, STRING dxl_device_name, STRING dxl_baud_rate)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  STRING return_delay_time_st = \"Return_Delay_Time\";\n  const char * return_delay_time_char = return_delay_time_st.c_str();\n\n  dynamixel_.id = actuator_id;\n  dynamixel_.num = actuator_id.size();\n\n  dynamixel_workbench_ = new DynamixelWorkbench;\n\n  result = dynamixel_workbench_->init(dxl_device_name.c_str(), std::atoi(dxl_baud_rate.c_str()), &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  uint16_t get_model_number;\n  for (uint8_t index = 0; index < dynamixel_.num; index++)\n  {\n    uint8_t id = dynamixel_.id.at(index);\n    result = dynamixel_workbench_->ping(id, &get_model_number, &log);\n\n    if (result == false)\n    {\n      log::error(log);\n      log::error(\"Please check your Dynamixel ID\");\n    }\n    else\n    {\n      char str[100];\n      sprintf(str, \"Joint Dynamixel ID : %d, Model Name : %s\", id, dynamixel_workbench_->getModelName(id));\n      log::println(str);\n\n      result = dynamixel_workbench_->setTimeBasedProfile(id, &log);\n      if(result == false)\n      {\n        log::error(log);\n        log::error(\"Please check your Dynamixel firmware version (v38~)\");\n      }\n\n      result = dynamixel_workbench_->writeRegister(id, return_delay_time_char, 0, &log);\n      if (result == false)\n      {\n        log::error(log);\n        log::error(\"Please check your Dynamixel firmware version\");\n      }\n    }\n  }\n  return true;\n}\n\nbool JointDynamixelProfileControl::setOperatingMode(std::vector<uint8_t> actuator_id, STRING dynamixel_mode)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const uint32_t velocity = uint32_t(control_loop_time_*1000) * 3;\n  const uint32_t acceleration = uint32_t(control_loop_time_*1000);\n  const uint32_t current = 0;\n\n  if (dynamixel_mode == \"position_mode\")\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->jointMode(actuator_id.at(num), velocity, acceleration, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n  else if (dynamixel_mode == \"current_based_position_mode\")\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->currentBasedPositionMode(actuator_id.at(num), current, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n  else\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->jointMode(actuator_id.at(num), velocity, acceleration, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n\n  return true;\n}\n\nbool JointDynamixelProfileControl::setSDKHandler(uint8_t actuator_id)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  result = dynamixel_workbench_->addSyncWriteHandler(actuator_id, \"Goal_Position\", &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->addSyncReadHandler(ADDR_PRESENT_CURRENT_2,\n                                                    (LENGTH_PRESENT_CURRENT_2 + LENGTH_PRESENT_VELOCITY_2 + LENGTH_PRESENT_POSITION_2),\n                                                    &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\nbool JointDynamixelProfileControl::writeProfileValue(std::vector<uint8_t> actuator_id, STRING profile_mode, uint32_t value)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const char * char_profile_mode = profile_mode.c_str();\n\n  for (uint8_t num = 0; num < actuator_id.size(); num++)\n  {\n    result = dynamixel_workbench_->writeRegister(actuator_id.at(num), char_profile_mode, value, &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  return true;\n}\n\nbool JointDynamixelProfileControl::writeGoalProfilingControlValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  uint8_t id_array[actuator_id.size()];\n  int32_t goal_value[actuator_id.size()];\n\n  //add tarajectory eq.\n  for(uint8_t index = 0; index < actuator_id.size(); index++)\n  {\n    float result_position;\n    float time_control = control_loop_time_;       //ms\n\n    if(previous_goal_value_.find(actuator_id.at(index)) == previous_goal_value_.end())\n    {\n      previous_goal_value_.insert(std::make_pair(actuator_id.at(index), value_vector.at(index)));\n    }\n\n    result_position = value_vector.at(index).position + 3*(value_vector.at(index).velocity * (time_control))/2;\n\n    id_array[index] = actuator_id.at(index);\n    goal_value[index] = dynamixel_workbench_->convertRadian2Value(actuator_id.at(index), result_position);\n\n    previous_goal_value_[actuator_id.at(index)] = value_vector.at(index);\n  }\n\n  result = dynamixel_workbench_->syncWrite(SYNC_WRITE_HANDLER, id_array, actuator_id.size(), goal_value, 1, &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n  return true;\n}\n\nstd::vector<robotis_manipulator::ActuatorValue> JointDynamixelProfileControl::receiveAllDynamixelValue(std::vector<uint8_t> actuator_id)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  std::vector<robotis_manipulator::ActuatorValue> all_actuator;\n\n  uint8_t id_array[actuator_id.size()];\n  for (uint8_t index = 0; index < actuator_id.size(); index++)\n    id_array[index] = actuator_id.at(index);\n\n  int32_t get_current[actuator_id.size()];\n  int32_t get_velocity[actuator_id.size()];\n  int32_t get_position[actuator_id.size()];\n\n  result = dynamixel_workbench_->syncRead(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                          id_array,\n                                          actuator_id.size(),\n                                          &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                id_array,\n                                                actuator_id.size(),\n                                                ADDR_PRESENT_CURRENT_2,\n                                                LENGTH_PRESENT_CURRENT_2,\n                                                get_current,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                 id_array,\n                                                 actuator_id.size(),\n                                                ADDR_PRESENT_VELOCITY_2,\n                                                LENGTH_PRESENT_VELOCITY_2,\n                                                get_velocity,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                 id_array,\n                                                 actuator_id.size(),\n                                                ADDR_PRESENT_POSITION_2,\n                                                LENGTH_PRESENT_POSITION_2,\n                                                get_position,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  for (uint8_t index = 0; index < actuator_id.size(); index++)\n  {\n    robotis_manipulator::ActuatorValue actuator;\n    actuator.effort = dynamixel_workbench_->convertValue2Current(get_current[index]);\n    actuator.velocity = dynamixel_workbench_->convertValue2Velocity(actuator_id.at(index), get_velocity[index]);\n    actuator.position = dynamixel_workbench_->convertValue2Radian(actuator_id.at(index), get_position[index]);\n\n    all_actuator.push_back(actuator);\n  }\n\n  return all_actuator;\n}\n\n\n/*****************************************************************************\n** Tool Dynamixel Control Functions\n*****************************************************************************/\nvoid ToolDynamixel::init(uint8_t actuator_id, const void *arg)\n{\n  STRING *get_arg_ = (STRING *)arg;\n\n  bool result = ToolDynamixel::initialize(actuator_id ,get_arg_[0], get_arg_[1]);\n\n  if (result == false)\n    return;\n}\n\nvoid ToolDynamixel::setMode(const void *arg)\n{\n  bool result = false;\n// const char* log = NULL;\n\n  STRING *get_arg_ = (STRING *)arg;\n\n  if (get_arg_[0] == \"position_mode\" || get_arg_[0] == \"current_based_position_mode\")\n  {\n    result = ToolDynamixel::setOperatingMode(get_arg_[0]);\n    if (result == false)\n      return;\n  }\n  else\n  {\n    result = ToolDynamixel::writeProfileValue(get_arg_[0], std::atoi(get_arg_[1].c_str()));\n    if (result == false)\n      return;\n  }\n\n  result = ToolDynamixel::setSDKHandler();\n  if (result == false)\n    return;\n}\n\nuint8_t ToolDynamixel::getId()\n{\n  return dynamixel_.id.at(0);\n}\n\nvoid ToolDynamixel::enable()\n{\n  const char* log = NULL;\n  bool result = false;\n  \n  result = dynamixel_workbench_->torqueOn(dynamixel_.id.at(0), &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n  enabled_state_ = true;\n}\n\nvoid ToolDynamixel::disable()\n{\n  const char* log = NULL;\n  bool result = false;\n  \n  result = dynamixel_workbench_->torqueOff(dynamixel_.id.at(0), &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n  enabled_state_ = false;\n}\n\nbool ToolDynamixel::sendToolActuatorValue(robotis_manipulator::ActuatorValue value)\n{\n  return ToolDynamixel::writeGoalPosition(value.position);\n}\n\nrobotis_manipulator::ActuatorValue ToolDynamixel::receiveToolActuatorValue()\n{\n  robotis_manipulator::ActuatorValue result;\n  result.position = ToolDynamixel::receiveDynamixelValue();\n  result.velocity = 0.0;\n  result.acceleration = 0.0;\n  result.effort = 0.0;\n  return result;\n}\n\n\n/*****************************************************************************\n** Functions called in Tool Dynamixel Profile Control Functions\n*****************************************************************************/\nbool ToolDynamixel::initialize(uint8_t actuator_id, STRING dxl_device_name, STRING dxl_baud_rate)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  STRING return_delay_time_st = \"Return_Delay_Time\";\n  const char * return_delay_time_char = return_delay_time_st.c_str();\n\n  dynamixel_.id.push_back(actuator_id);\n  dynamixel_.num = 1;\n\n  dynamixel_workbench_ = new DynamixelWorkbench;\n\n  result = dynamixel_workbench_->init(dxl_device_name.c_str(), std::atoi(dxl_baud_rate.c_str()), &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  uint16_t get_model_number;\n  result = dynamixel_workbench_->ping(dynamixel_.id.at(0), &get_model_number, &log);\n  if (result == false)\n  {\n    log::error(log);\n    log::error(\"Please check your Dynamixel ID\");\n  }\n  else\n  {\n    char str[100];\n    sprintf(str, \"Tool Dynamixel ID : %d, Model Name :\", dynamixel_.id.at(0));\n    strcat(str, dynamixel_workbench_->getModelName(dynamixel_.id.at(0)));\n    log::println(str);\n\n    result = dynamixel_workbench_->setVelocityBasedProfile(dynamixel_.id.at(0), &log);\n    if(result == false)\n    {\n      log::error(log);\n      log::error(\"Please check your Dynamixel firmware version (v38~)\");\n    }\n\n    result = dynamixel_workbench_->writeRegister(dynamixel_.id.at(0), return_delay_time_char, 0, &log);\n    if (result == false)\n    {\n      log::error(log);\n      log::error(\"Please check your Dynamixel firmware version\");\n    }\n  }\n\n  return true;\n}\n\nbool ToolDynamixel::setOperatingMode(STRING dynamixel_mode)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const uint32_t velocity = 0;\n  const uint32_t acceleration = 0;\n  const uint32_t current = 200;\n\n  if (dynamixel_mode == \"position_mode\")\n  {\n    result = dynamixel_workbench_->jointMode(dynamixel_.id.at(0), velocity, acceleration, &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  else if (dynamixel_mode == \"current_based_position_mode\")\n  {\n    result = dynamixel_workbench_->currentBasedPositionMode(dynamixel_.id.at(0), current, &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  else\n  {\n    result = dynamixel_workbench_->jointMode(dynamixel_.id.at(0), velocity, acceleration, &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n\n  return true;\n}\n\nbool ToolDynamixel::writeProfileValue(STRING profile_mode, uint32_t value)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const char * char_profile_mode = profile_mode.c_str();\n\n  result = dynamixel_workbench_->writeRegister(dynamixel_.id.at(0), char_profile_mode, value, &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\nbool ToolDynamixel::setSDKHandler()\n{\n  bool result = false;\n  const char* log = NULL;\n\n  result = dynamixel_workbench_->addSyncWriteHandler(dynamixel_.id.at(0), \"Goal_Position\", &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->addSyncReadHandler(dynamixel_.id.at(0),\n                                                    \"Present_Position\", \n                                                    &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\nbool ToolDynamixel::writeGoalPosition(double radian)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  int32_t goal_position = 0;\n\n  goal_position = dynamixel_workbench_->convertRadian2Value(dynamixel_.id.at(0), radian);\n\n  result = dynamixel_workbench_->syncWrite(SYNC_WRITE_HANDLER, &goal_position, &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\ndouble ToolDynamixel::receiveDynamixelValue()\n{\n  bool result = false;\n  const char* log = NULL;\n\n  int32_t get_value = 0;\n  uint8_t id_array[1] = {dynamixel_.id.at(0)};\n\n  result = dynamixel_workbench_->syncRead(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT, \n                                          id_array,\n                                          (uint8_t)1,\n                                          &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT, \n                                            id_array,\n                                            (uint8_t)1,\n                                            &get_value, \n                                            &log);\n  if (result == false)\n  {\n    log::error(log);\n  } \n\n  return dynamixel_workbench_->convertValue2Radian(dynamixel_.id.at(0), get_value);\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/planar_libs/src/planar_kinematics.cpp",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include \"../include/planar_libs/planar_kinematics.h\"\n\nusing namespace robotis_manipulator;\nusing namespace planar_kinematics;\n\n/*****************************************************************************\n** Kinematics Solver \n*****************************************************************************/\nvoid SolverUsingGeometry::setOption(const void *arg) {}\n\nEigen::MatrixXd SolverUsingGeometry::jacobian(Manipulator *manipulator, Name tool_name)\n{\n  return Eigen::MatrixXd::Identity(6, manipulator->getDOF());\n}\n\nvoid SolverUsingGeometry::solveForwardKinematics(Manipulator *manipulator) {}\n\nbool SolverUsingGeometry::solveInverseKinematics(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue> *goal_joint_value)\n{\n  return inverseKinematicsSolverUsingGeometry(manipulator, tool_name, target_pose, goal_joint_value);\n}\n\n/*****************************************************************************\n** Private\n*****************************************************************************/\nbool SolverUsingGeometry::inverseKinematicsSolverUsingGeometry(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue>* goal_joint_value)\n{\n  const double link[3] = {0.120, 0.098, 0.0366};\n  JointValue target_angle[7];\n  std::vector<JointValue> target_angle_vector;\n  double start_x[3], start_y[3];\n  double temp_x[3], temp_y[3];\n  double goal_x[3], goal_y[3];\n  double diff_x[3], diff_y[3];\n  Matrix3d goal_orientation;\n  double target_pose_length[3];\n  double alpha[3];\n  double temp_diff[3];\n\n  // Start pose for each set of two joints\n  for (uint8_t i=0; i<3; i++)\n  {\n    start_x[i] = cos(PI*2.0/3.0*i)*(-0.1705);\n    start_y[i] = sin(PI*2.0/3.0*i)*(-0.1705);\n  }\n\n  // Goal pose for each set of two joints after tool rotation\n  for (uint8_t i=0; i<3; i++){\n    temp_x[i] = target_pose.kinematic.position(0) + cos(PI*2.0/3.0*i)*(-link[2]);\n    temp_y[i] = target_pose.kinematic.position(1) + sin(PI*2.0/3.0*i)*(-link[2]);\n  }\n\n  goal_orientation = target_pose.kinematic.orientation;\n  if (goal_orientation(0,0) || goal_orientation(0,1) || goal_orientation(0,2)\n   || goal_orientation(1,0) || goal_orientation(1,1) || goal_orientation(1,2)\n   || goal_orientation(2,0) || goal_orientation(2,1) || goal_orientation(2,2))\n  {\n    goal_orientation(0,0) = 1;\n    goal_orientation(1,1) = 1;\n    goal_orientation(2,2) = 1;\n  }\n  for (uint8_t i=0; i<3; i++)\n  {\n    goal_x[i] = goal_orientation(0,0)*temp_x[i] + goal_orientation(0,1)*temp_y[i];\n    goal_y[i] = goal_orientation(1,0)*temp_x[i] + goal_orientation(1,1)*temp_y[i];\n    diff_x[i] = goal_x[i] - start_x[i];\n    diff_y[i] = goal_y[i] - start_y[i];\n    target_pose_length[i] = sqrt(diff_x[i]*diff_x[i] + diff_y[i]*diff_y[i]);\n  }\n\n  // Compute the Length of Position Difference and Target Angle\n  for (uint8_t i=0; i<3; i++)\n  {\n    alpha[i] = acos((target_pose_length[i]*target_pose_length[i] + link[0]*link[0] - link[1]*link[1]) \n                            / (2*target_pose_length[i]*link[0]));\n    temp_diff[i] = sin(-PI*2.0/3.0*i)*diff_x[i] + cos(-PI*2.0/3.0*i)*diff_y[i];\n    target_angle[i].position = acos(-temp_diff[i] / target_pose_length[i]) - alpha[i] - PI/4.0;\n  }\n\n  // Set Joint Angle \n  target_angle_vector.push_back(target_angle[0]);\n  target_angle_vector.push_back(target_angle[1]);\n  target_angle_vector.push_back(target_angle[2]);\n\n  for (uint8_t i=0; i<3; i++)\n  {\n    target_angle[i].position += PI/4.0; \n    target_angle[i+3].position = acos(-(temp_diff[i] - (-link[0]*cos(target_angle[i].position))) / link[1]) - target_angle[i].position - PI*7.0/12.0;\n    target_angle[i+3].position = acos((-sin(PI*2.0/3.0*i)*diff_x[i] + cos(PI*2.0/3.0*i)*diff_y[i] \n                              + link[0]*cos(target_angle[i].position)) / -link[1]) - target_angle[i].position - PI*7.0/12.0;\n  }\n\n  target_angle_vector.push_back(target_angle[3]);\n  target_angle_vector.push_back(target_angle[4]);\n  target_angle_vector.push_back(target_angle[5]);\n\n  target_angle[3].position += PI*7.0/12.0;\n  \n  target_angle[6].position =  PI/2.0 - target_angle[0].position - target_angle[3].position + PI/3.0;\n\n  target_angle_vector.push_back(target_angle[6]);\n  \n  *goal_joint_value = target_angle_vector;\n  manipulator->setAllJointValue(target_angle_vector);\n\n  return true;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/planar_libs.h",
    "content": "#include \"planar_libs/include/planar_libs/planar.h\"\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/scara_libs/include/scara_libs/scara.h",
    "content": "﻿/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef SCARA_H_\n#define SCARA_H_\n\n#include \"scara_custom_trajectory.h\"\n#include \"scara_dynamixel.h\"\n#include \"scara_kinematics.h\"\n\n#define CUSTOM_TRAJECTORY_SIZE 4\n#define CUSTOM_TRAJECTORY_LINE    \"custom_trajectory_line\"\n#define CUSTOM_TRAJECTORY_CIRCLE  \"custom_trajectory_circle\"\n#define CUSTOM_TRAJECTORY_RHOMBUS \"custom_trajectory_rhombus\"\n#define CUSTOM_TRAJECTORY_HEART   \"custom_trajectory_heart\"\n\n#define DXL_SIZE 4\n#define JOINT_DYNAMIXEL \"joint_dxl\"\n#define TOOL_DYNAMIXEL \"tool_dxl\"\n\n#define RECEIVE_RATE 0.100 // unit: s\n#define CONTROL_RATE 0.010 // unit: s\n\n#define X_AXIS robotis_manipulator::math::vector3(1.0, 0.0, 0.0)\n#define Y_AXIS robotis_manipulator::math::vector3(0.0, 1.0, 0.0)\n#define Z_AXIS robotis_manipulator::math::vector3(0.0, 0.0, 1.0)\n\nclass Scara : public robotis_manipulator::RobotisManipulator\n{\nprivate:\n  robotis_manipulator::Kinematics *kinematics_;\n  robotis_manipulator::JointActuator *joint_;  \n  robotis_manipulator::ToolActuator *tool_;    \n  robotis_manipulator::CustomTaskTrajectory *custom_trajectory_[CUSTOM_TRAJECTORY_SIZE];\n  \n  bool using_actual_robot_state_;\n  bool receive_data_flag_ = false;\n  double prev_receive_time_ = 0.0;\n  double prev_control_time_ = 0.0;\n\npublic:\n  Scara();\n  virtual ~Scara();\n\n  void initDebug();\n  void initOpenManipulator(bool using_actual_robot_state, \n                           STRING usb_port = \"/dev/ttyUSB0\", \n                           STRING baud_rate = \"1000000\", \n                           float control_rate = CONTROL_RATE);\n  void processOpenManipulator(double present_time);\n\n  bool getUsingActualRobotState();\n  bool getReceiveDataFlag();\n  double getPrevReceiveTime();\n\n  void setReceiveDataFlag(bool receive_data_flag);\n  void setPrevReceiveTime(double prev_receive_time);\n};\n\n#endif // SCARA_H_\n\n\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/scara_libs/include/scara_libs/scara_custom_trajectory.h",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef SCARA_CUSTOM_TRAJECTORY_H_\n#define SCARA_CUSTOM_TRAJECTORY_H_\n\n#if defined(__OPENCR__)\n  #include <RobotisManipulator.h>\n#else\n  #include <robotis_manipulator/robotis_manipulator.h>\n#endif\n\nusing namespace robotis_manipulator;\nusing namespace Eigen;\n\nnamespace scara_custom_trajectory\n{\n  \nenum AXIS{\n\tX_AXIS,\n\tY_AXIS,\n\tZ_AXIS,\n};\n\n/*****************************************************************************\n** Line\n*****************************************************************************/\nclass Line : public robotis_manipulator::CustomTaskTrajectory\n{\nprivate:\n  TaskWaypoint start_pose_;\n  TaskWaypoint goal_pose_;\n\n  double acc_dec_time_;\n  double move_time_;\n  std::vector<double> vel_max_;\n\npublic:\n\tLine() {}\n\tvirtual ~Line() {}\n\n  void initLine(double move_time, TaskWaypoint start, TaskWaypoint delta);\n  TaskWaypoint drawLine(double time_var);\n\n  virtual void setOption(const void *arg);\n  virtual void makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg);\n  virtual TaskWaypoint getTaskWaypoint(double tick);\n};\n\n\n/*****************************************************************************\n** Circle\n*****************************************************************************/\nclass Circle : public robotis_manipulator::CustomTaskTrajectory\n{\nprivate:\n  robotis_manipulator::MinimumJerk path_generator_;\n  VectorXd coefficient_;\n\n  TaskWaypoint start_pose_;\n  TaskWaypoint goal_pose_;\n\n  double radius_;\n  double start_angular_position_;\n  double revolution_;\n\npublic:\n\tCircle() {}\n\tvirtual ~Circle() {}\n\n  void initCircle(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position);\n  TaskWaypoint drawCircle(double time_var);\n\n  virtual void setOption(const void *arg);\n  virtual void makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg);\n  virtual TaskWaypoint getTaskWaypoint(double tick);\n};\n\n\n/*****************************************************************************\n** Rhombus\n*****************************************************************************/\nclass Rhombus : public robotis_manipulator::CustomTaskTrajectory\n{\nprivate:\n  robotis_manipulator::MinimumJerk path_generator_;\n  VectorXd coefficient_;\n\n  TaskWaypoint start_pose_;\n  TaskWaypoint goal_pose_;\n\n  double radius_;\n  double start_angular_position_;\n  double revolution_;\n\npublic:\n\tRhombus() {}\n\tvirtual ~Rhombus() {}\n\n  void initRhombus(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position);\n  TaskWaypoint drawRhombus(double time_var);\n\n  virtual void setOption(const void *arg);\n  virtual void makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg);\n  virtual TaskWaypoint getTaskWaypoint(double tick);\n};\n\n\n/*****************************************************************************\n** Heart\n*****************************************************************************/\nclass Heart : public robotis_manipulator::CustomTaskTrajectory\n{\nprivate:\n  robotis_manipulator::MinimumJerk path_generator_;\n  VectorXd coefficient_;\n\n  TaskWaypoint start_pose_;\n  TaskWaypoint goal_pose_;\n\n  double radius_;\n  double start_angular_position_;\n  double revolution_;\n\npublic:\n\tHeart() {}\n\tvirtual ~Heart() {}\n\n  void initHeart(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position);\n  TaskWaypoint drawHeart(double tick);\n\n  virtual void setOption(const void *arg);\n  virtual void makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg);\n  virtual TaskWaypoint getTaskWaypoint(double tick);\n};\n\n\n} // namespace scara_custom_trajectory\n#endif // SCARA_CUSTOM_TRAJECTORY_H_\n\n\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/scara_libs/include/scara_libs/scara_dynamixel.h",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef SCARA_DYNAMIXEL_H_\n#define SCARA_DYNAMIXEL_H_\n\n#if defined(__OPENCR__)\n  #include <RobotisManipulator.h>\n  #include <DynamixelWorkbench.h>\n#else\n  #include <robotis_manipulator/robotis_manipulator.h>\n  #include <dynamixel_workbench_toolbox/dynamixel_workbench.h>\n#endif\n\nnamespace scara_dynamixel\n{\n\n#define SYNC_WRITE_HANDLER 0\n#define SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT 0\n\n//#define CONTROL_LOOP_TIME 10;    //ms\n\n// Protocol 2.0\n#define ADDR_PRESENT_CURRENT_2 126\n#define ADDR_PRESENT_VELOCITY_2 128\n#define ADDR_PRESENT_POSITION_2 132\n#define ADDR_VELOCITY_TRAJECTORY_2 136\n#define ADDR_POSITION_TRAJECTORY_2 140\n#define ADDR_PROFILE_ACCELERATION_2 108\n#define ADDR_PROFILE_VELOCITY_2 112\n#define ADDR_GOAL_POSITION_2 116\n\n\n#define LENGTH_PRESENT_CURRENT_2 2\n#define LENGTH_PRESENT_VELOCITY_2 4\n#define LENGTH_PRESENT_POSITION_2 4\n#define LENGTH_VELOCITY_TRAJECTORY_2 4\n#define LENGTH_POSITION_TRAJECTORY_2 4\n#define LENGTH_PROFILE_ACCELERATION_2 4\n#define LENGTH_PROFILE_VELOCITY_2 4\n#define LENGTH_GOAL_POSITION_2 4\n\n\n// Protocol 1.0\n#define ADDR_PRESENT_CURRENT_1 = 40;\n#define ADDR_PRESENT_VELOCITY_1 = 38;\n#define ADDR_PRESENT_POSITION_1 = 36;\n\n#define LENGTH_PRESENT_CURRENT_1 = 2;\n#define LENGTH_PRESENT_VELOCITY_1 = 2;\n#define LENGTH_PRESENT_POSITION_1 = 2;\n\ntypedef struct\n{\n  std::vector<uint8_t> id;\n  uint8_t num;\n} Joint;\n\nclass JointDynamixel : public robotis_manipulator::JointActuator\n{\nprivate:\n  DynamixelWorkbench *dynamixel_workbench_;\n  Joint dynamixel_;\n\npublic:\n  JointDynamixel(){}\n  virtual ~JointDynamixel(){}\n\n\n  /*****************************************************************************\n  ** Joint Dynamixel Control Functions\n  *****************************************************************************/\n  virtual void init(std::vector<uint8_t> actuator_id, const void *arg);\n  virtual void setMode(std::vector<uint8_t> actuator_id, const void *arg);\n  virtual std::vector<uint8_t> getId();\n\n  virtual void enable();\n  virtual void disable();\n\n  virtual bool sendJointActuatorValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector);\n  virtual std::vector<robotis_manipulator::ActuatorValue> receiveJointActuatorValue(std::vector<uint8_t> actuator_id);\n\n\n  /*****************************************************************************\n  ** Functions called in Joint Dynamixel Control Functions\n  *****************************************************************************/\n  bool initialize(std::vector<uint8_t> actuator_id, STRING dxl_device_name, STRING dxl_baud_rate);\n  bool setOperatingMode(std::vector<uint8_t> actuator_id, STRING dynamixel_mode = \"position_mode\");\n  bool setSDKHandler(uint8_t actuator_id);\n  bool writeProfileValue(std::vector<uint8_t> actuator_id, STRING profile_mode, uint32_t value);\n  bool writeGoalPosition(std::vector<uint8_t> actuator_id, std::vector<double> radian_vector);\n  std::vector<robotis_manipulator::ActuatorValue> receiveAllDynamixelValue(std::vector<uint8_t> actuator_id);\n};\n\nclass JointDynamixelProfileControl : public robotis_manipulator::JointActuator\n{\nprivate:\n  DynamixelWorkbench *dynamixel_workbench_;\n  Joint dynamixel_;\n  float control_loop_time_; // unit: ms\n  std::map<uint8_t, robotis_manipulator::ActuatorValue> previous_goal_value_;\n\npublic:\n  JointDynamixelProfileControl(float control_loop_time = 0.010);\n  virtual ~JointDynamixelProfileControl(){}\n\n\n  /*****************************************************************************\n  ** Joint Dynamixel Profile Control Functions\n  *****************************************************************************/\n  virtual void init(std::vector<uint8_t> actuator_id, const void *arg);\n  virtual void setMode(std::vector<uint8_t> actuator_id, const void *arg);\n  virtual std::vector<uint8_t> getId();\n\n  virtual void enable();\n  virtual void disable();\n\n  virtual bool sendJointActuatorValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector);\n  virtual std::vector<robotis_manipulator::ActuatorValue> receiveJointActuatorValue(std::vector<uint8_t> actuator_id);\n\n\n  /*****************************************************************************\n  ** Functions called in Joint Dynamixel Profile Control Functions\n  *****************************************************************************/\n  bool initialize(std::vector<uint8_t> actuator_id, STRING dxl_device_name, STRING dxl_baud_rate);\n  bool setOperatingMode(std::vector<uint8_t> actuator_id, STRING dynamixel_mode = \"position_mode\");\n  bool setSDKHandler(uint8_t actuator_id);\n  bool writeProfileValue(std::vector<uint8_t> actuator_id, STRING profile_mode, uint32_t value);\n  bool writeGoalProfilingControlValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector);\n  std::vector<robotis_manipulator::ActuatorValue> receiveAllDynamixelValue(std::vector<uint8_t> actuator_id);\n};\n\nclass ToolDynamixel : public robotis_manipulator::ToolActuator\n{\n private:\n  DynamixelWorkbench *dynamixel_workbench_;\n  Joint dynamixel_;\n\n public:\n  ToolDynamixel() {}\n  virtual ~ToolDynamixel() {}\n\n\n  /*****************************************************************************\n  ** Tool Dynamixel Control Functions\n  *****************************************************************************/\n  virtual void init(uint8_t actuator_id, const void *arg);\n  virtual void setMode(const void *arg);\n  virtual uint8_t getId();\n\n  virtual void enable();\n  virtual void disable();\n\n  virtual bool sendToolActuatorValue(robotis_manipulator::ActuatorValue value);\n  virtual robotis_manipulator::ActuatorValue receiveToolActuatorValue();\n\n\n  /*****************************************************************************\n  ** Functions called in Tool Dynamixel Profile Control Functions\n  *****************************************************************************/\n  bool initialize(uint8_t actuator_id, STRING dxl_device_name, STRING dxl_baud_rate);\n  bool setOperatingMode(STRING dynamixel_mode = \"position_mode\");\n  bool writeProfileValue(STRING profile_mode, uint32_t value);\n  bool setSDKHandler();\n  bool writeGoalPosition(double radian);\n  double receiveDynamixelValue();\n};\n\n} // namespace scara_dynamixel\n#endif // SCARA_DYNAMIXEL_H_\n\n\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/scara_libs/include/scara_libs/scara_kinematics.h",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef SCARA_KINEMATICS_H_\n#define SCARA_KINEMATICS_H_\n\n#if defined(__OPENCR__)\n  #include <RobotisManipulator.h>\n#else\n  #include <robotis_manipulator/robotis_manipulator.h>\n#endif\n\nusing namespace Eigen;\nusing namespace robotis_manipulator;\n\nnamespace scara_kinematics\n{\n\n/*****************************************************************************\n** Kinematics Solver Using CHain Rule and Geometry\n*****************************************************************************/\nclass SolverUsingCRAndGeometry : public robotis_manipulator::Kinematics\n{\nprivate:\n  void forwardKinematicsSolverUsingChainRule(Manipulator *manipulator, Name component_name);\n  bool inverseKinematicsSolverUsingGeometry(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue>* goal_joint_value);\n\npublic:\n  SolverUsingCRAndGeometry() {}\n  virtual ~SolverUsingCRAndGeometry() {}\n\n  virtual void setOption(const void *arg);\n  virtual MatrixXd jacobian(Manipulator *manipulator, Name tool_name);\n  virtual void solveForwardKinematics(Manipulator *manipulator);\n  virtual bool solveInverseKinematics(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue>* goal_joint_value);\n};\n\n} // namespace scara_kinematics\n\n#endif // SCARA_KINEMATICS_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/scara_libs/src/scara.cpp",
    "content": "﻿/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include \"../include/scara_libs/scara.h\"\n\nScara::Scara() {}\nScara::~Scara()\n{\n  delete kinematics_;\n  delete joint_;\n  delete tool_;\n  for(uint8_t index = 0; index < CUSTOM_TRAJECTORY_SIZE; index++)\n    delete custom_trajectory_[index];\n}\n\nvoid Scara::initDebug()\n{\n  DEBUG.begin(57600); // Using Serial4(=SerialBT2)\n  log::print(\"OpenManipulator Debugging Port\"); \n}\n\nvoid Scara::initOpenManipulator(bool using_actual_robot_state, STRING usb_port, STRING baud_rate, float control_rate)\n{\n  /*****************************************************************************\n  ** Set if using actual robot\n  *****************************************************************************/\n  using_actual_robot_state_ = using_actual_robot_state;  \n\n  /*****************************************************************************\n  ** Initialize Manipulator Parameters\n  *****************************************************************************/\n  addWorld(\"world\",   // world name\n           \"joint1\"); // child name\n\n  addJoint(\"joint1\",  // my name\n           \"world\",   // parent name\n           \"joint2\",  // child name\n           math::vector3(-0.241, 0.0, 0.057),               // relative position\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // relative orientation\n           Z_AXIS,    // axis of rotation\n           1);        // actuator id\n\n  addJoint(\"joint2\",  // my name\n           \"joint1\",  // parent name\n           \"joint3\",  // child name\n           math::vector3(0.067, 0.0, 0.0),                  // relative position\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // relative orientation\n           Z_AXIS,    // axis of rotation\n           2);        // actuator id\n\n  addJoint(\"joint3\",  // my name\n           \"joint2\",  // parent name\n           \"tool\",    // child name\n           math::vector3(0.067, 0.0, 0.0),                  // relative position\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // relative orientation\n           Z_AXIS,    // axis of rotation\n           3);        // actuator id\n\n  addTool(\"tool\",     // my name\n          \"joint3\",   // parent name\n          math::vector3(0.107, 0.0, 0.0),                  // relative position\n          math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // relative orientation\n          4,          // actuator id\n          0.01,       // max joint limit \n          -0.51);     // min joint limit\n\n  /*****************************************************************************\n  ** Initialize Kinematics \n  *****************************************************************************/\n  kinematics_ = new scara_kinematics::SolverUsingCRAndGeometry();\n  addKinematics(kinematics_);\n\n  /*****************************************************************************\n  ** Initialize Custom Trajectory\n  *****************************************************************************/\n  custom_trajectory_[0] = new scara_custom_trajectory::Line();\n  custom_trajectory_[1] = new scara_custom_trajectory::Circle();\n  custom_trajectory_[2] = new scara_custom_trajectory::Rhombus();\n  custom_trajectory_[3] = new scara_custom_trajectory::Heart();\n\n  addCustomTrajectory(CUSTOM_TRAJECTORY_LINE, custom_trajectory_[0]);\n  addCustomTrajectory(CUSTOM_TRAJECTORY_CIRCLE, custom_trajectory_[1]);\n  addCustomTrajectory(CUSTOM_TRAJECTORY_RHOMBUS, custom_trajectory_[2]);\n  addCustomTrajectory(CUSTOM_TRAJECTORY_HEART, custom_trajectory_[3]);\n\n  if (using_actual_robot_state_)\n  {\n    /*****************************************************************************\n    ** Initialize ㅓoint Actuator\n    *****************************************************************************/\n    joint_ = new scara_dynamixel::JointDynamixelProfileControl(control_rate);\n\n    // Set communication arguments \n    STRING dxl_comm_arg[2] = {usb_port, baud_rate};\n    void *p_dxl_comm_arg = &dxl_comm_arg; \n\n    // Set joint actuator id \n    std::vector<uint8_t> jointDxlId;\n    jointDxlId.push_back(1);\n    jointDxlId.push_back(2);\n    jointDxlId.push_back(3);\n    addJointActuator(JOINT_DYNAMIXEL, joint_, jointDxlId, p_dxl_comm_arg);\n\n    // Set joint actuator control mode\n    STRING joint_dxl_mode_arg = \"position_mode\";\n    void *p_joint_dxl_mode_arg = &joint_dxl_mode_arg;\n    setJointActuatorMode(JOINT_DYNAMIXEL, jointDxlId, p_joint_dxl_mode_arg);\n\n    /*****************************************************************************\n    ** Initialize Tool Actuator\n    *****************************************************************************/\n    tool_ = new scara_dynamixel::ToolDynamixel();\n\n    // Set tool actuator id \n    uint8_t toolDxlId = 4;\n    addToolActuator(TOOL_DYNAMIXEL, tool_, toolDxlId, p_dxl_comm_arg);\n\n    // Set tool actuator control mode \n    STRING tool_dxl_mode_arg = \"position_mode\";\n    void *p_tool_dxl_mode_arg = &tool_dxl_mode_arg;\n    setToolActuatorMode(TOOL_DYNAMIXEL, p_tool_dxl_mode_arg);\n\n    /*****************************************************************************\n    ** Enable actuators and Receive actuator values \n    *****************************************************************************/\n    // Enable All Actuators \n    enableAllActuator();\n\n    // Receive current angles from all actuators \n    receiveAllJointActuatorValue();\n    receiveAllToolActuatorValue();\n  }\n}\n\n/*****************************************************************************\n** Process actuator values received from external controllers\n*****************************************************************************/\nvoid Scara::processOpenManipulator(double present_time)  \n{\n  if (present_time - prev_control_time_ >= CONTROL_RATE)  \n  {\n    JointWaypoint goal_joint_value = getJointGoalValueFromTrajectory(present_time);\n    JointWaypoint goal_tool_value  = getToolGoalValue();\n\n    if (using_actual_robot_state_)\n    {\n      receiveAllJointActuatorValue();   \n      receiveAllToolActuatorValue();    \n    }\n\n    if(goal_joint_value.size() != 0) sendAllJointActuatorValue(goal_joint_value);   \n    if(goal_tool_value.size() != 0) sendAllToolActuatorValue(goal_tool_value);\n    solveForwardKinematics(); \n\n    // Set previous control time\n    prev_control_time_ = millis()/1000.0;\n  }\n}\n\n/*****************************************************************************\n** State Functions\n*****************************************************************************/\n// Check if using acutal robot \nbool Scara::getUsingActualRobotState() \n{\n  return using_actual_robot_state_;\n}\n\n/* Check if the program read data within control rate) */\nbool Scara::getReceiveDataFlag()  \n{\n  return receive_data_flag_;\n}\n\n/* Get the previous time when data were received */\ndouble Scara::getPrevReceiveTime() \n{\n  return prev_receive_time_;\n}\n\n/* Set whether data were received or not */\nvoid Scara::setReceiveDataFlag(bool receive_data_flag) \n{\n  receive_data_flag_ = receive_data_flag;\n}\n\n/* Set the previous time when data were received */\nvoid Scara::setPrevReceiveTime(double prev_receive_time)  \n{\n  prev_receive_time_ = prev_receive_time;\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/scara_libs/src/scara_custom_trajectory.cpp",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include \"../include/scara_libs/scara_custom_trajectory.h\"\n\nusing namespace scara_custom_trajectory;\nusing namespace Eigen;\n\n\n/*****************************************************************************\n** Line\n*****************************************************************************/\nvoid Line::initLine(double move_time, TaskWaypoint start, TaskWaypoint delta)\n{\n  move_time_ = move_time;\n  acc_dec_time_ = move_time_ * 0.2;\n  vel_max_.resize(3);\n\n  TaskWaypoint start_to_goal;\n\n  start_pose_ = start;\n\n  goal_pose_ .kinematic.orientation = start_pose_.kinematic.orientation;\n  goal_pose_ .kinematic.position = start.kinematic.position + delta.kinematic.position;\n\n  vel_max_.at(X_AXIS) = delta.kinematic.position(X_AXIS)/(move_time_ - acc_dec_time_);\n  vel_max_.at(Y_AXIS) = delta.kinematic.position(Y_AXIS)/(move_time_ - acc_dec_time_);\n  vel_max_.at(Z_AXIS) = delta.kinematic.position(Z_AXIS)/(move_time_ - acc_dec_time_);\n}\n\nTaskWaypoint Line::drawLine(double time_var)\n{\n  TaskWaypoint pose;\n\n  if(acc_dec_time_ >= time_var)\n  {\n    pose.kinematic.position(X_AXIS) = 0.5*vel_max_.at(X_AXIS)*pow(time_var, 2)/acc_dec_time_ + start_pose_.kinematic.position(X_AXIS);\n    pose.kinematic.position(Y_AXIS) = 0.5*vel_max_.at(Y_AXIS)*pow(time_var, 2)/acc_dec_time_ + start_pose_.kinematic.position(Y_AXIS);\n    pose.kinematic.position(Z_AXIS) = 0.5*vel_max_.at(Z_AXIS)*pow(time_var, 2)/acc_dec_time_ + start_pose_.kinematic.position(Z_AXIS);\n  }\n  else if(time_var > acc_dec_time_ && (move_time_ - acc_dec_time_) >= time_var )\n  {\n    pose.kinematic.position(X_AXIS) = vel_max_.at(X_AXIS)*(time_var-(acc_dec_time_*0.5)) + start_pose_.kinematic.position(X_AXIS);\n    pose.kinematic.position(Y_AXIS) = vel_max_.at(Y_AXIS)*(time_var-(acc_dec_time_*0.5)) + start_pose_.kinematic.position(Y_AXIS);\n    pose.kinematic.position(Z_AXIS) = vel_max_.at(Z_AXIS)*(time_var-(acc_dec_time_*0.5)) + start_pose_.kinematic.position(Z_AXIS);\n  }\n  else if(time_var > (move_time_ - acc_dec_time_) && (time_var < move_time_))\n  {\n    pose.kinematic.position(X_AXIS) = goal_pose_.kinematic.position(X_AXIS) - vel_max_.at(X_AXIS)*0.5/acc_dec_time_*(pow((move_time_-time_var),2));\n    pose.kinematic.position(Y_AXIS) = goal_pose_.kinematic.position(Y_AXIS) - vel_max_.at(Y_AXIS)*0.5/acc_dec_time_*(pow((move_time_-time_var),2));\n    pose.kinematic.position(Z_AXIS) = goal_pose_.kinematic.position(Z_AXIS) - vel_max_.at(Z_AXIS)*0.5/acc_dec_time_*(pow((move_time_-time_var),2));\n  }\n  else if(time_var <= move_time_)\n  {\n    pose.kinematic.position(X_AXIS) = goal_pose_.kinematic.position(X_AXIS);\n    pose.kinematic.position(Y_AXIS) = goal_pose_.kinematic.position(Y_AXIS);\n    pose.kinematic.position(Z_AXIS) = goal_pose_.kinematic.position(Z_AXIS);\n  }\n\n  pose.kinematic.orientation = start_pose_.kinematic.orientation;\n  pose.dynamic.linear.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.linear.acceleration = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.acceleration = Eigen::Vector3d::Zero(3);\n\n  return pose;\n}\n\nTaskWaypoint Line::getTaskWaypoint(double tick)\n{\n  return drawLine(tick);\n}\n\n\nvoid Line::makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg)\n{\n  TaskWaypoint *c_arg = (TaskWaypoint *)arg;\n  initLine(move_time, start, c_arg[0]);\n}\nvoid Line::setOption(const void *arg) {}\n\n\n/*****************************************************************************\n** Circle\n*****************************************************************************/\nvoid Circle::initCircle(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position)\n{\n  start_pose_ = start;\n\n  radius_ = radius;\n  revolution_ = revolution;\n  start_angular_position_ = start_angular_position;\n\n  Point drawingStart, drawingGoal;\n\n  drawingStart.position = 0.0;\n  drawingStart.velocity = 0.0;\n  drawingStart.acceleration = 0.0;\n  drawingStart.effort = 0.0;\n\n  drawingGoal.position = revolution_ * 2*M_PI;\n  drawingGoal.velocity = 0.0;\n  drawingGoal.acceleration = 0.0;\n  drawingGoal.effort = 0.0;\n\n  path_generator_.calcCoefficient(drawingStart, drawingGoal, move_time);\n  coefficient_ = path_generator_.getCoefficient();\n}\n\nTaskWaypoint Circle::drawCircle(double tick)\n{\n  // get time variable\n  double get_time_var = 0.0;\n\n  get_time_var = coefficient_(0) +\n                 coefficient_(1) * pow(tick, 1) +\n                 coefficient_(2) * pow(tick, 2) +\n                 coefficient_(3) * pow(tick, 3) +\n                 coefficient_(4) * pow(tick, 4) +\n                 coefficient_(5) * pow(tick, 5);\n\n  // set drawing trajectory\n  TaskWaypoint pose;\n\n  double diff_pose[2];\n\n  diff_pose[0] = (cos(get_time_var)-1)*cos(start_angular_position_) - sin(get_time_var)*sin(start_angular_position_);\n  diff_pose[1] = (cos(get_time_var)-1)*sin(start_angular_position_) + sin(get_time_var)*cos(start_angular_position_);\n\n  pose.kinematic.position(X_AXIS) = start_pose_.kinematic.position(X_AXIS) + radius_ * diff_pose[0];\n  pose.kinematic.position(Y_AXIS) = start_pose_.kinematic.position(Y_AXIS) + radius_ * diff_pose[1];\n  pose.kinematic.position(Z_AXIS) = start_pose_.kinematic.position(Z_AXIS);\n\n  pose.kinematic.orientation = start_pose_.kinematic.orientation;\n\n  pose.dynamic.linear.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.linear.acceleration = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.acceleration = Eigen::Vector3d::Zero(3);\n\n  return pose;\n}\n\nTaskWaypoint Circle::getTaskWaypoint(double tick)\n{\n  return drawCircle(tick);\n}\n\nvoid Circle::makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg)\n{\n  double *get_arg_ = (double *)arg;\n  initCircle(move_time, start, get_arg_[0], get_arg_[1], get_arg_[2]);\n}\n\nvoid Circle::setOption(const void *arg){}\n\n\n/*****************************************************************************\n** Rhombus\n*****************************************************************************/\nvoid Rhombus::initRhombus(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position)\n{\n  start_pose_ = start;\n\n  radius_ = radius;\n  revolution_ = revolution;\n  start_angular_position_ = start_angular_position;\n\n  Point drawingStart, drawingGoal;\n\n  drawingStart.position = 0.0;\n  drawingStart.velocity = 0.0;\n  drawingStart.acceleration = 0.0;\n  drawingStart.effort = 0.0;\n\n  drawingGoal.position = revolution_ * 2*M_PI;\n  drawingGoal.velocity = 0.0;\n  drawingGoal.acceleration = 0.0;\n  drawingGoal.effort = 0.0;\n\n  path_generator_.calcCoefficient(drawingStart, drawingGoal, move_time);\n  coefficient_ = path_generator_.getCoefficient();\n}\n\n\nTaskWaypoint Rhombus::drawRhombus(double tick)\n{\n  // get time variable\n  double get_time_var = 0.0;\n\n  get_time_var = coefficient_(0) +\n                 coefficient_(1) * pow(tick, 1) +\n                 coefficient_(2) * pow(tick, 2) +\n                 coefficient_(3) * pow(tick, 3) +\n                 coefficient_(4) * pow(tick, 4) +\n                 coefficient_(5) * pow(tick, 5); \n\n  // set drawing trajectory\n  TaskWaypoint pose;\n  double diff_pose[2];\n  double traj[2];\n\n  while(true)\n  {\n    if (get_time_var < PI*2) break;\n    get_time_var = get_time_var - PI*2;\n  }\n\n  if (get_time_var >= 0 && get_time_var < PI/2){\n    traj[0] = - get_time_var / (PI/2);\n    traj[1] = - get_time_var / (PI/2);\n  } else if (get_time_var >= PI/2 && get_time_var < PI){\n    traj[0] = - get_time_var / (PI/2);\n    traj[1] = get_time_var / (PI/2) - 2;\n  } else if (get_time_var >= PI && get_time_var < PI*3/2){\n    traj[0] = get_time_var / (PI/2) - 4;\n    traj[1] = get_time_var / (PI/2) - 2;\n  } else {\n    traj[0] = get_time_var / (PI/2) - 4;\n    traj[1] = - get_time_var / (PI/2) + 4;\n  }\n  \n\n  diff_pose[0] = traj[0]*cos(start_angular_position_) - traj[1]*sin(start_angular_position_);\n  diff_pose[1] = traj[0]*sin(start_angular_position_) + traj[1]*cos(start_angular_position_);\n\n  pose.kinematic.position(X_AXIS) = start_pose_.kinematic.position(X_AXIS) + radius_ * diff_pose[0];\n  pose.kinematic.position(Y_AXIS) = start_pose_.kinematic.position(Y_AXIS) + radius_ * diff_pose[1];\n  pose.kinematic.position(Z_AXIS) = start_pose_.kinematic.position(Z_AXIS);\n\n  pose.kinematic.orientation = start_pose_.kinematic.orientation;\n\n  pose.dynamic.linear.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.linear.acceleration = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.acceleration = Eigen::Vector3d::Zero(3);\n\n  return pose;\n}\n\n\nvoid Rhombus::makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg)\n{\n  double *get_arg_ = (double *)arg;\n  initRhombus(move_time, start, get_arg_[0], get_arg_[1], get_arg_[2]);\n}\n\nTaskWaypoint Rhombus::getTaskWaypoint(double tick)\n{\n  return drawRhombus(tick);\n}\nvoid Rhombus::setOption(const void *arg){}\n\n\n/*****************************************************************************\n** Heart\n*****************************************************************************/\nvoid Heart::initHeart(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position)\n{\n  start_pose_ = start;\n\n  radius_ = radius;\n  revolution_ = revolution;\n  start_angular_position_ = start_angular_position;\n\n  Point drawingStart, drawingGoal;\n\n  drawingStart.position = 0.0;\n  drawingStart.velocity = 0.0;\n  drawingStart.acceleration = 0.0;\n  drawingStart.effort = 0.0;\n\n  drawingGoal.position = revolution_ * 2*M_PI;\n  drawingGoal.velocity = 0.0;\n  drawingGoal.acceleration = 0.0;\n  drawingGoal.effort = 0.0;\n\n  path_generator_.calcCoefficient(drawingStart, drawingGoal, move_time);\n  coefficient_ = path_generator_.getCoefficient();\n}\n\nTaskWaypoint Heart::drawHeart(double tick)\n{\n  // get time variable\n  double get_time_var = 0.0;\n\n  get_time_var = coefficient_(0) +\n                 coefficient_(1) * pow(tick, 1) +\n                 coefficient_(2) * pow(tick, 2) +\n                 coefficient_(3) * pow(tick, 3) +\n                 coefficient_(4) * pow(tick, 4) +\n                 coefficient_(5) * pow(tick, 5);\n\n  // set drawing trajectory\n  TaskWaypoint pose;\n  double diff_pose[2];\n  double traj[2];\n\n\tdouble shift_offset = - 5.0;\n\n  traj[0] = (shift_offset + (13*cos(get_time_var) - 5*cos(2*get_time_var) - 2*cos(3*get_time_var) - cos(4*get_time_var))) / 16;\n  traj[1] = (16*sin(get_time_var)*sin(get_time_var)*sin(get_time_var)) / 16;\n\n  diff_pose[0] = traj[0]*cos(start_angular_position_) - traj[1]*sin(start_angular_position_);\n  diff_pose[1] = traj[0]*sin(start_angular_position_) + traj[1]*cos(start_angular_position_);\n\n  pose.kinematic.position(X_AXIS) = start_pose_.kinematic.position(X_AXIS) + radius_ * diff_pose[0];\n  pose.kinematic.position(Y_AXIS) = start_pose_.kinematic.position(Y_AXIS) + radius_ * diff_pose[1];\n  pose.kinematic.position(Z_AXIS) = start_pose_.kinematic.position(Z_AXIS);\n\n  pose.kinematic.orientation = start_pose_.kinematic.orientation;\n\n  pose.dynamic.linear.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.linear.acceleration = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.acceleration = Eigen::Vector3d::Zero(3);\n\n  return pose;\n}\n\nvoid Heart::makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg)\n{\n  double *get_arg_ = (double *)arg;\n  initHeart(move_time, start, get_arg_[0], get_arg_[1], get_arg_[2]);\n}\nvoid Heart::setOption(const void *arg){}\n\nTaskWaypoint Heart::getTaskWaypoint(double tick)\n{\n  return drawHeart(tick);\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/scara_libs/src/scara_dynamixel.cpp",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include \"../include/scara_libs/scara_dynamixel.h\"\n\nusing namespace scara_dynamixel;\nusing namespace robotis_manipulator;\n\n/*****************************************************************************\n** Joint Dynamixel Control Functions\n*****************************************************************************/\nvoid JointDynamixel::init(std::vector<uint8_t> actuator_id, const void *arg)\n{\n  STRING *get_arg_ = (STRING *)arg;\n\n  bool result = JointDynamixel::initialize(actuator_id ,get_arg_[0], get_arg_[1]);\n\n  if (result == false)\n    return;\n}\n\nvoid JointDynamixel::setMode(std::vector<uint8_t> actuator_id, const void *arg)\n{\n  bool result = false;\n  // const char* log = NULL;\n\n  STRING *get_arg_ = (STRING *)arg;\n\n  if (get_arg_[0] == \"position_mode\" || get_arg_[0] == \"current_based_position_mode\")\n  {\n    result = JointDynamixel::setOperatingMode(actuator_id, get_arg_[0]);\n    if (result == false)\n      return;\n\n    result = JointDynamixel::setSDKHandler(actuator_id.at(0));\n    if (result == false)\n      return;\n  }\n  else\n  {\n    result = JointDynamixel::writeProfileValue(actuator_id, get_arg_[0], std::atoi(get_arg_[1].c_str()));\n    if (result == false)\n      return;\n  }\n  return;\n}\n\nstd::vector<uint8_t> JointDynamixel::getId()\n{\n  return dynamixel_.id;\n}\n\nvoid JointDynamixel::enable()\n{\n  const char* log = NULL;\n  bool result = false;\n  \n  for (uint32_t index = 0; index < dynamixel_.num; index++)\n  {\n    result = dynamixel_workbench_->torqueOn(dynamixel_.id.at(index), &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  enabled_state_ = true;\n}\n\nvoid JointDynamixel::disable()\n{\n  const char* log = NULL;\n  bool result = false;\n  \n  for (uint32_t index = 0; index < dynamixel_.num; index++)\n  {\n    result = dynamixel_workbench_->torqueOff(dynamixel_.id.at(index), &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  enabled_state_ = false;\n}\n\nbool JointDynamixel::sendJointActuatorValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector)\n{\n  bool result = false;\n\n  std::vector<double> radian_vector;\n  for(uint32_t index = 0; index < value_vector.size(); index++)\n  {\n    radian_vector.push_back(value_vector.at(index).position);\n  }\n  result = JointDynamixel::writeGoalPosition(actuator_id, radian_vector);\n  if (result == false)\n    return false;\n\n  return true;\n}\n\nstd::vector<robotis_manipulator::ActuatorValue> JointDynamixel::receiveJointActuatorValue(std::vector<uint8_t> actuator_id)\n{\n  return JointDynamixel::receiveAllDynamixelValue(actuator_id);\n}\n\n\n/*****************************************************************************\n** Functions called in Joint Dynamixel Control Functions\n*****************************************************************************/\nbool JointDynamixel::initialize(std::vector<uint8_t> actuator_id, STRING dxl_device_name, STRING dxl_baud_rate)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  STRING return_delay_time_st = \"Return_Delay_Time\";\n  const char * return_delay_time_char = return_delay_time_st.c_str();\n\n  dynamixel_.id = actuator_id;\n  dynamixel_.num = actuator_id.size();\n\n  dynamixel_workbench_ = new DynamixelWorkbench;\n\n  result = dynamixel_workbench_->init(dxl_device_name.c_str(), std::atoi(dxl_baud_rate.c_str()), &log);\n  if (result == false)\n  {\n    log::error(log);\n  }    \n\n  uint16_t get_model_number;\n  for (uint8_t index = 0; index < dynamixel_.num; index++)\n  {\n    uint8_t id = dynamixel_.id.at(index);\n    result = dynamixel_workbench_->ping(id, &get_model_number, &log);\n\n    if (result == false)\n    {\n      log::error(log);\n      log::error(\"Please check your Dynamixel ID\");\n    }\n    else\n    {\n      char str[100];\n      sprintf(str, \"Joint Dynamixel ID : %d, Model Name : %s\", id, dynamixel_workbench_->getModelName(id));\n      log::println(str);\n\n      result = dynamixel_workbench_->setVelocityBasedProfile(id, &log);\n      if(result == false)\n      {\n        log::error(log);\n        log::error(\"Please check your Dynamixel firmware version (v38~)\");\n      }\n\n      result = dynamixel_workbench_->writeRegister(id, return_delay_time_char, 0, &log);\n      if (result == false)\n      {\n        log::error(log);\n        log::error(\"Please check your Dynamixel firmware version\");\n      }\n    }\n  }\n  return true;\n}\n\nbool JointDynamixel::setOperatingMode(std::vector<uint8_t> actuator_id, STRING dynamixel_mode)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const uint32_t velocity = 0;\n  const uint32_t acceleration = 0;\n  const uint32_t current = 0;\n\n  if (dynamixel_mode == \"position_mode\")\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->jointMode(actuator_id.at(num), velocity, acceleration, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n  else if (dynamixel_mode == \"current_based_position_mode\")\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->currentBasedPositionMode(actuator_id.at(num), current, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n  else\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->jointMode(actuator_id.at(num), velocity, acceleration, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n\n  return true;\n}\n\nbool JointDynamixel::setSDKHandler(uint8_t actuator_id)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  result = dynamixel_workbench_->addSyncWriteHandler(actuator_id, \"Goal_Position\", &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->addSyncReadHandler(ADDR_PRESENT_CURRENT_2, \n                                                    (LENGTH_PRESENT_CURRENT_2 + LENGTH_PRESENT_VELOCITY_2 + LENGTH_PRESENT_POSITION_2), \n                                                    &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\nbool JointDynamixel::writeProfileValue(std::vector<uint8_t> actuator_id, STRING profile_mode, uint32_t value)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const char * char_profile_mode = profile_mode.c_str();\n\n  for (uint8_t num = 0; num < actuator_id.size(); num++)\n  {\n    result = dynamixel_workbench_->writeRegister(actuator_id.at(num), char_profile_mode, value, &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n\n  return true;\n}\n\nbool JointDynamixel::writeGoalPosition(std::vector<uint8_t> actuator_id, std::vector<double> radian_vector)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  uint8_t id_array[actuator_id.size()];\n  int32_t goal_position[actuator_id.size()];\n\n  for (uint8_t index = 0; index < actuator_id.size(); index++)\n  {\n    id_array[index] = actuator_id.at(index);\n    goal_position[index] = dynamixel_workbench_->convertRadian2Value(actuator_id.at(index), radian_vector.at(index));\n  }\n\n  result = dynamixel_workbench_->syncWrite(SYNC_WRITE_HANDLER, id_array, actuator_id.size(), goal_position, 1, &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\nstd::vector<robotis_manipulator::ActuatorValue> JointDynamixel::receiveAllDynamixelValue(std::vector<uint8_t> actuator_id)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  std::vector<robotis_manipulator::ActuatorValue> all_actuator;\n\n  uint8_t id_array[actuator_id.size()];\n  for (uint8_t index = 0; index < actuator_id.size(); index++)\n    id_array[index] = actuator_id.at(index);\n\n  int32_t get_current[actuator_id.size()];\n  int32_t get_velocity[actuator_id.size()];\n  int32_t get_position[actuator_id.size()];\n\n  result = dynamixel_workbench_->syncRead(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                          id_array,\n                                          actuator_id.size(),\n                                          &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                id_array,\n                                                actuator_id.size(),\n                                                ADDR_PRESENT_CURRENT_2,\n                                                LENGTH_PRESENT_CURRENT_2,\n                                                get_current,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                 id_array,\n                                                 actuator_id.size(),\n                                                ADDR_PRESENT_VELOCITY_2,\n                                                LENGTH_PRESENT_VELOCITY_2,\n                                                get_velocity,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                 id_array,\n                                                 actuator_id.size(),\n                                                ADDR_PRESENT_POSITION_2,\n                                                LENGTH_PRESENT_POSITION_2,\n                                                get_position,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  for (uint8_t index = 0; index < actuator_id.size(); index++)\n  {\n    robotis_manipulator::ActuatorValue actuator;\n    actuator.effort = dynamixel_workbench_->convertValue2Current(get_current[index]);\n    actuator.velocity = dynamixel_workbench_->convertValue2Velocity(actuator_id.at(index), get_velocity[index]);\n    actuator.position = dynamixel_workbench_->convertValue2Radian(actuator_id.at(index), get_position[index]);\n\n    all_actuator.push_back(actuator);\n  }\n\n  return all_actuator;\n}\n\n\n/*****************************************************************************\n** Joint Dynamixel Profile Control Functions\n*****************************************************************************/\nJointDynamixelProfileControl::JointDynamixelProfileControl(float control_loop_time)\n{\n  control_loop_time_ = control_loop_time;\n}\n\nvoid JointDynamixelProfileControl::init(std::vector<uint8_t> actuator_id, const void *arg)\n{\n  STRING *get_arg_ = (STRING *)arg;\n\n  bool result = JointDynamixelProfileControl::initialize(actuator_id ,get_arg_[0], get_arg_[1]);\n\n  if (result == false)\n    return;\n}\n\nvoid JointDynamixelProfileControl::setMode(std::vector<uint8_t> actuator_id, const void *arg)\n{\n  bool result = false;\n  // const char* log = NULL;\n\n  STRING *get_arg_ = (STRING *)arg;\n\n  if (get_arg_[0] == \"position_mode\" || get_arg_[0] == \"current_based_position_mode\")\n  {\n    result = JointDynamixelProfileControl::setOperatingMode(actuator_id, get_arg_[0]);\n    if (result == false)\n      return;\n\n    result = JointDynamixelProfileControl::setSDKHandler(actuator_id.at(0));\n    if (result == false)\n      return;\n  }\n  else\n  {\n    result = JointDynamixelProfileControl::writeProfileValue(actuator_id, get_arg_[0], std::atoi(get_arg_[1].c_str()));\n    if (result == false)\n      return;\n  }\n  return;\n}\n\nstd::vector<uint8_t> JointDynamixelProfileControl::getId()\n{\n  return dynamixel_.id;\n}\n\nvoid JointDynamixelProfileControl::enable()\n{\n  const char* log = NULL;\n  bool result = false;\n\n  for (uint32_t index = 0; index < dynamixel_.num; index++)\n  {\n    result = dynamixel_workbench_->torqueOn(dynamixel_.id.at(index), &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  enabled_state_ = true;\n}\n\nvoid JointDynamixelProfileControl::disable()\n{\n  const char* log = NULL;\n  bool result = false;\n\n  for (uint32_t index = 0; index < dynamixel_.num; index++)\n  {\n    result = dynamixel_workbench_->torqueOff(dynamixel_.id.at(index), &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  enabled_state_ = false;\n}\n\nbool JointDynamixelProfileControl::sendJointActuatorValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector)\n{\n  bool result = false;\n\n  result = JointDynamixelProfileControl::writeGoalProfilingControlValue(actuator_id, value_vector);\n  if (result == false)\n    return false;\n\n  return true;\n}\n\nstd::vector<robotis_manipulator::ActuatorValue> JointDynamixelProfileControl::receiveJointActuatorValue(std::vector<uint8_t> actuator_id)\n{\n  return JointDynamixelProfileControl::receiveAllDynamixelValue(actuator_id);\n}\n\n\n/*****************************************************************************\n** Functions called in Joint Dynamixel Profile Control Functions\n*****************************************************************************/\nbool JointDynamixelProfileControl::initialize(std::vector<uint8_t> actuator_id, STRING dxl_device_name, STRING dxl_baud_rate)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  STRING return_delay_time_st = \"Return_Delay_Time\";\n  const char * return_delay_time_char = return_delay_time_st.c_str();\n\n  dynamixel_.id = actuator_id;\n  dynamixel_.num = actuator_id.size();\n\n  dynamixel_workbench_ = new DynamixelWorkbench;\n\n  result = dynamixel_workbench_->init(dxl_device_name.c_str(), std::atoi(dxl_baud_rate.c_str()), &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  uint16_t get_model_number;\n  for (uint8_t index = 0; index < dynamixel_.num; index++)\n  {\n    uint8_t id = dynamixel_.id.at(index);\n    result = dynamixel_workbench_->ping(id, &get_model_number, &log);\n\n    if (result == false)\n    {\n      log::error(log);\n      log::error(\"Please check your Dynamixel ID\");\n    }\n    else\n    {\n      char str[100];\n      sprintf(str, \"Joint Dynamixel ID : %d, Model Name : %s\", id, dynamixel_workbench_->getModelName(id));\n      log::println(str);\n\n      result = dynamixel_workbench_->setTimeBasedProfile(id, &log);\n      if(result == false)\n      {\n        log::error(log);\n        log::error(\"Please check your Dynamixel firmware version (v38~)\");\n      }\n\n      result = dynamixel_workbench_->writeRegister(id, return_delay_time_char, 0, &log);\n      if (result == false)\n      {\n        log::error(log);\n        log::error(\"Please check your Dynamixel firmware version\");\n      }\n    }\n  }\n  return true;\n}\n\nbool JointDynamixelProfileControl::setOperatingMode(std::vector<uint8_t> actuator_id, STRING dynamixel_mode)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const uint32_t velocity = uint32_t(control_loop_time_*1000) * 3;\n  const uint32_t acceleration = uint32_t(control_loop_time_*1000);\n  const uint32_t current = 0;\n\n  if (dynamixel_mode == \"position_mode\")\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->jointMode(actuator_id.at(num), velocity, acceleration, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n  else if (dynamixel_mode == \"current_based_position_mode\")\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->currentBasedPositionMode(actuator_id.at(num), current, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n  else\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->jointMode(actuator_id.at(num), velocity, acceleration, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n\n  return true;\n}\n\nbool JointDynamixelProfileControl::setSDKHandler(uint8_t actuator_id)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  result = dynamixel_workbench_->addSyncWriteHandler(actuator_id, \"Goal_Position\", &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->addSyncReadHandler(ADDR_PRESENT_CURRENT_2,\n                                                    (LENGTH_PRESENT_CURRENT_2 + LENGTH_PRESENT_VELOCITY_2 + LENGTH_PRESENT_POSITION_2),\n                                                    &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\nbool JointDynamixelProfileControl::writeProfileValue(std::vector<uint8_t> actuator_id, STRING profile_mode, uint32_t value)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const char * char_profile_mode = profile_mode.c_str();\n\n  for (uint8_t num = 0; num < actuator_id.size(); num++)\n  {\n    result = dynamixel_workbench_->writeRegister(actuator_id.at(num), char_profile_mode, value, &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  return true;\n}\n\nbool JointDynamixelProfileControl::writeGoalProfilingControlValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  uint8_t id_array[actuator_id.size()];\n  int32_t goal_value[actuator_id.size()];\n\n  //add tarajectory eq.\n  for(uint8_t index = 0; index < actuator_id.size(); index++)\n  {\n    float result_position;\n    float time_control = control_loop_time_;       //ms\n\n    if(previous_goal_value_.find(actuator_id.at(index)) == previous_goal_value_.end())\n    {\n      previous_goal_value_.insert(std::make_pair(actuator_id.at(index), value_vector.at(index)));\n    }\n\n    result_position = value_vector.at(index).position + 3*(value_vector.at(index).velocity * (time_control))/2;\n\n    id_array[index] = actuator_id.at(index);\n    goal_value[index] = dynamixel_workbench_->convertRadian2Value(actuator_id.at(index), result_position);\n\n    previous_goal_value_[actuator_id.at(index)] = value_vector.at(index);\n  }\n\n  result = dynamixel_workbench_->syncWrite(SYNC_WRITE_HANDLER, id_array, actuator_id.size(), goal_value, 1, &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n  return true;\n}\n\nstd::vector<robotis_manipulator::ActuatorValue> JointDynamixelProfileControl::receiveAllDynamixelValue(std::vector<uint8_t> actuator_id)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  std::vector<robotis_manipulator::ActuatorValue> all_actuator;\n\n  uint8_t id_array[actuator_id.size()];\n  for (uint8_t index = 0; index < actuator_id.size(); index++)\n    id_array[index] = actuator_id.at(index);\n\n  int32_t get_current[actuator_id.size()];\n  int32_t get_velocity[actuator_id.size()];\n  int32_t get_position[actuator_id.size()];\n\n  result = dynamixel_workbench_->syncRead(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                          id_array,\n                                          actuator_id.size(),\n                                          &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                id_array,\n                                                actuator_id.size(),\n                                                ADDR_PRESENT_CURRENT_2,\n                                                LENGTH_PRESENT_CURRENT_2,\n                                                get_current,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                 id_array,\n                                                 actuator_id.size(),\n                                                ADDR_PRESENT_VELOCITY_2,\n                                                LENGTH_PRESENT_VELOCITY_2,\n                                                get_velocity,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                 id_array,\n                                                 actuator_id.size(),\n                                                ADDR_PRESENT_POSITION_2,\n                                                LENGTH_PRESENT_POSITION_2,\n                                                get_position,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  for (uint8_t index = 0; index < actuator_id.size(); index++)\n  {\n    robotis_manipulator::ActuatorValue actuator;\n    actuator.effort = dynamixel_workbench_->convertValue2Current(get_current[index]);\n    actuator.velocity = dynamixel_workbench_->convertValue2Velocity(actuator_id.at(index), get_velocity[index]);\n    actuator.position = dynamixel_workbench_->convertValue2Radian(actuator_id.at(index), get_position[index]);\n\n    all_actuator.push_back(actuator);\n  }\n\n  return all_actuator;\n}\n\n\n/*****************************************************************************\n** Tool Dynamixel Control Functions\n*****************************************************************************/\nvoid ToolDynamixel::init(uint8_t actuator_id, const void *arg)\n{\n  STRING *get_arg_ = (STRING *)arg;\n\n  bool result = ToolDynamixel::initialize(actuator_id ,get_arg_[0], get_arg_[1]);\n\n  if (result == false)\n    return;\n}\n\nvoid ToolDynamixel::setMode(const void *arg)\n{\n  bool result = false;\n// const char* log = NULL;\n\n  STRING *get_arg_ = (STRING *)arg;\n\n  if (get_arg_[0] == \"position_mode\" || get_arg_[0] == \"current_based_position_mode\")\n  {\n    result = ToolDynamixel::setOperatingMode(get_arg_[0]);\n    if (result == false)\n      return;\n  }\n  else\n  {\n    result = ToolDynamixel::writeProfileValue(get_arg_[0], std::atoi(get_arg_[1].c_str()));\n    if (result == false)\n      return;\n  }\n\n  result = ToolDynamixel::setSDKHandler();\n  if (result == false)\n    return;\n}\n\nuint8_t ToolDynamixel::getId()\n{\n  return dynamixel_.id.at(0);\n}\n\nvoid ToolDynamixel::enable()\n{\n  const char* log = NULL;\n  bool result = false;\n  \n  result = dynamixel_workbench_->torqueOn(dynamixel_.id.at(0), &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n  enabled_state_ = true;\n}\n\nvoid ToolDynamixel::disable()\n{\n  const char* log = NULL;\n  bool result = false;\n  \n  result = dynamixel_workbench_->torqueOff(dynamixel_.id.at(0), &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n  enabled_state_ = false;\n}\n\nbool ToolDynamixel::sendToolActuatorValue(robotis_manipulator::ActuatorValue value)\n{\n  return ToolDynamixel::writeGoalPosition(value.position);\n}\n\nrobotis_manipulator::ActuatorValue ToolDynamixel::receiveToolActuatorValue()\n{\n  robotis_manipulator::ActuatorValue result;\n  result.position = ToolDynamixel::receiveDynamixelValue();\n  result.velocity = 0.0;\n  result.acceleration = 0.0;\n  result.effort = 0.0;\n  return result;\n}\n\n\n/*****************************************************************************\n** Functions called in Tool Dynamixel Profile Control Functions\n*****************************************************************************/\nbool ToolDynamixel::initialize(uint8_t actuator_id, STRING dxl_device_name, STRING dxl_baud_rate)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  STRING return_delay_time_st = \"Return_Delay_Time\";\n  const char * return_delay_time_char = return_delay_time_st.c_str();\n\n  dynamixel_.id.push_back(actuator_id);\n  dynamixel_.num = 1;\n\n  dynamixel_workbench_ = new DynamixelWorkbench;\n\n  result = dynamixel_workbench_->init(dxl_device_name.c_str(), std::atoi(dxl_baud_rate.c_str()), &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  uint16_t get_model_number;\n  result = dynamixel_workbench_->ping(dynamixel_.id.at(0), &get_model_number, &log);\n  if (result == false)\n  {\n    log::error(log);\n    log::error(\"Please check your Dynamixel ID\");\n  }\n  else\n  {\n    char str[100];\n    sprintf(str, \"Tool Dynamixel ID : %d, Model Name :\", dynamixel_.id.at(0));\n    strcat(str, dynamixel_workbench_->getModelName(dynamixel_.id.at(0)));\n    log::println(str);\n\n    result = dynamixel_workbench_->setVelocityBasedProfile(dynamixel_.id.at(0), &log);\n    if(result == false)\n    {\n      log::error(log);\n      log::error(\"Please check your Dynamixel firmware version (v38~)\");\n    }\n\n    result = dynamixel_workbench_->writeRegister(dynamixel_.id.at(0), return_delay_time_char, 0, &log);\n    if (result == false)\n    {\n      log::error(log);\n      log::error(\"Please check your Dynamixel firmware version\");\n    }\n  }\n\n  return true;\n}\n\nbool ToolDynamixel::setOperatingMode(STRING dynamixel_mode)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const uint32_t velocity = 0;\n  const uint32_t acceleration = 0;\n  const uint32_t current = 200;\n\n  if (dynamixel_mode == \"position_mode\")\n  {\n    result = dynamixel_workbench_->jointMode(dynamixel_.id.at(0), velocity, acceleration, &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  else if (dynamixel_mode == \"current_based_position_mode\")\n  {\n    result = dynamixel_workbench_->currentBasedPositionMode(dynamixel_.id.at(0), current, &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  else\n  {\n    result = dynamixel_workbench_->jointMode(dynamixel_.id.at(0), velocity, acceleration, &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n\n  return true;\n}\n\nbool ToolDynamixel::writeProfileValue(STRING profile_mode, uint32_t value)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const char * char_profile_mode = profile_mode.c_str();\n\n  result = dynamixel_workbench_->writeRegister(dynamixel_.id.at(0), char_profile_mode, value, &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\nbool ToolDynamixel::setSDKHandler()\n{\n  bool result = false;\n  const char* log = NULL;\n\n  result = dynamixel_workbench_->addSyncWriteHandler(dynamixel_.id.at(0), \"Goal_Position\", &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->addSyncReadHandler(dynamixel_.id.at(0),\n                                                    \"Present_Position\", \n                                                    &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\nbool ToolDynamixel::writeGoalPosition(double radian)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  int32_t goal_position = 0;\n\n  goal_position = dynamixel_workbench_->convertRadian2Value(dynamixel_.id.at(0), radian);\n\n  result = dynamixel_workbench_->syncWrite(SYNC_WRITE_HANDLER, &goal_position, &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\ndouble ToolDynamixel::receiveDynamixelValue()\n{\n  bool result = false;\n  const char* log = NULL;\n\n  int32_t get_value = 0;\n  uint8_t id_array[1] = {dynamixel_.id.at(0)};\n\n  result = dynamixel_workbench_->syncRead(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT, \n                                          id_array,\n                                          (uint8_t)1,\n                                          &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT, \n                                            id_array,\n                                            (uint8_t)1,\n                                            &get_value, \n                                            &log);\n  if (result == false)\n  {\n    log::error(log);\n  } \n\n  return dynamixel_workbench_->convertValue2Radian(dynamixel_.id.at(0), get_value);\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/scara_libs/src/scara_kinematics.cpp",
    "content": "﻿/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include \"../include/scara_libs/scara_kinematics.h\"\n\nusing namespace robotis_manipulator;\nusing namespace scara_kinematics;\n\n/*****************************************************************************\n** Kinematics Solver \n*****************************************************************************/\nvoid SolverUsingCRAndGeometry::setOption(const void *arg) {}\n\nEigen::MatrixXd SolverUsingCRAndGeometry::jacobian(Manipulator *manipulator, Name tool_name)\n{\n  Eigen::MatrixXd jacobian = Eigen::MatrixXd::Identity(6, manipulator->getDOF());\n\n  Eigen::Vector3d joint_axis = Eigen::Vector3d::Zero(3);\n\n  Eigen::Vector3d position_changed = Eigen::Vector3d::Zero(3);\n  Eigen::Vector3d orientation_changed = Eigen::Vector3d::Zero(3);\n  Eigen::VectorXd pose_changed = Eigen::VectorXd::Zero(6);\n\n  int8_t index = 0;\n  Name my_name =  manipulator->getWorldChildName();\n\n  for (int8_t size = 0; size < manipulator->getDOF(); size++)\n  {\n    Name parent_name = manipulator->getComponentParentName(my_name);\n    if (parent_name == manipulator->getWorldName())\n    {\n      joint_axis = manipulator->getWorldOrientation() * manipulator->getAxis(my_name);\n    }\n    else\n    {\n      joint_axis = manipulator->getComponentOrientationFromWorld(parent_name) * manipulator->getAxis(my_name);\n    }\n\n    position_changed = math::skewSymmetricMatrix(joint_axis) *\n                       (manipulator->getComponentPositionFromWorld(tool_name) - manipulator->getComponentPositionFromWorld(my_name));\n    orientation_changed = joint_axis;\n\n    pose_changed << position_changed(0),\n        position_changed(1),\n        position_changed(2),\n        orientation_changed(0),\n        orientation_changed(1),\n        orientation_changed(2);\n\n    jacobian.col(index) = pose_changed;\n    index++;\n    my_name = manipulator->getComponentChildName(my_name).at(0); // Get Child name which has active joint\n  }\n  return jacobian;\n}\n\nvoid SolverUsingCRAndGeometry::solveForwardKinematics(Manipulator *manipulator)\n{\n  forwardKinematicsSolverUsingChainRule(manipulator, manipulator->getWorldChildName());\n}\n\nbool SolverUsingCRAndGeometry::solveInverseKinematics(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue> *goal_joint_value)\n{\n  return inverseKinematicsSolverUsingGeometry(manipulator, tool_name, target_pose, goal_joint_value);\n}\n\n/*****************************************************************************\n** Private\n*****************************************************************************/\nvoid SolverUsingCRAndGeometry::forwardKinematicsSolverUsingChainRule(Manipulator *manipulator, Name component_name)\n{\n  Name my_name = component_name;\n  Name parent_name = manipulator->getComponentParentName(my_name);\n  int8_t number_of_child = manipulator->getComponentChildName(my_name).size();\n\n  Pose parent_pose_value;\n  Pose my_pose_value;\n\n  //Get Parent Pose\n  if (parent_name == manipulator->getWorldName())\n  {\n    parent_pose_value = manipulator->getWorldPose();\n  }\n  else\n  {\n    parent_pose_value = manipulator->getComponentPoseFromWorld(parent_name);\n  }\n\n  //position\n  my_pose_value.kinematic.position = parent_pose_value.kinematic.position\n                                   + (parent_pose_value.kinematic.orientation * manipulator->getComponentRelativePositionFromParent(my_name));\n  //orientation\n  my_pose_value.kinematic.orientation = parent_pose_value.kinematic.orientation * math::rodriguesRotationMatrix(manipulator->getAxis(my_name), manipulator->getJointPosition(my_name));\n  //linear velocity\n  my_pose_value.dynamic.linear.velocity = math::vector3(0.0, 0.0, 0.0);\n  //angular velocity\n  my_pose_value.dynamic.angular.velocity = math::vector3(0.0, 0.0, 0.0);\n  //linear acceleration\n  my_pose_value.dynamic.linear.acceleration = math::vector3(0.0, 0.0, 0.0);\n  //angular acceleration\n  my_pose_value.dynamic.angular.acceleration = math::vector3(0.0, 0.0, 0.0);\n\n  manipulator->setComponentPoseFromWorld(my_name, my_pose_value);\n\n  for (int8_t index = 0; index < number_of_child; index++)\n  {\n    Name child_name = manipulator->getComponentChildName(my_name).at(index);\n    forwardKinematicsSolverUsingChainRule(manipulator, child_name);\n  }\n}\n\nbool SolverUsingCRAndGeometry::inverseKinematicsSolverUsingGeometry(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue>* goal_joint_value)\n{\n  const double link[3] = {0.067, 0.067, 0.107};\n  JointValue target_angle[3];\n  std::vector<JointValue> target_angle_vector;\n\n  // Compute the length from Joint1 to the end effector\n  double temp_target_pose[2];\n  double target_pose_length;\n  temp_target_pose[0] = target_pose.kinematic.position(0) + 0.241;\n  temp_target_pose[1] = target_pose.kinematic.position(1);\n  target_pose_length = sqrt((temp_target_pose[0])*temp_target_pose[0] + temp_target_pose[1]*temp_target_pose[1]);\n\n  // Compute the length of Position Difference and Target Angle\n  double error=1000.0; // random large initial value\n\n  for (uint16_t count=0; count<=900; count++){\n    double theta=(double)count/10*DEG2RAD;\n\n    // Assume theta = target_angle[1] = target_angle[2]\n    double alpha = acos((link[1]*link[1]+link[2]*link[2]-link[0]*link[0]-target_pose_length*target_pose_length+2*link[1]*link[2]*cos(theta))\n                  / (-2*target_pose_length*link[0]));\n    double beta = acos((link[0]*link[0]+link[1]*link[1]-link[2]*link[2]-target_pose_length*target_pose_length+2*link[0]*link[1]*cos(theta))\n                  / (-2*target_pose_length*link[2]));\n    double temp_error = abs(alpha + beta - 2*theta);\n\n    if (temp_error < error){\n      target_angle[0].position = PI/2 -acos(temp_target_pose[1]/target_pose_length) - alpha;\n      target_angle[1].position = theta;\n      target_angle[2].position = theta;\n      error = temp_error;\n    }\n  }\n\n  // Set joint angle \n  target_angle_vector.push_back(target_angle[0]);\n  target_angle_vector.push_back(target_angle[1]);\n  target_angle_vector.push_back(target_angle[2]);\n\n  *goal_joint_value = target_angle_vector; \n   \n  return true;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/scara_libs.h",
    "content": "#include \"scara_libs/include/scara_libs/scara.h\""
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/stewart_libs/include/stewart_libs/stewart.h",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef STEWART_H_\n#define STEWART_H_\n\n#include \"stewart_custom_trajectory.h\"\n#include \"stewart_dynamixel.h\"\n#include \"stewart_kinematics.h\"\n\n#define CUSTOM_TRAJECTORY_SIZE 4\n#define CUSTOM_TRAJECTORY_LINE    \"custom_trajectory_line\"\n#define CUSTOM_TRAJECTORY_CIRCLE  \"custom_trajectory_circle\"\n#define CUSTOM_TRAJECTORY_RHOMBUS \"custom_trajectory_rhombus\"\n#define CUSTOM_TRAJECTORY_HEART   \"custom_trajectory_heart\"\n\n#define DXL_SIZE 6\n#define JOINT_DYNAMIXEL \"joint_dxl\"\n\n#define RECEIVE_RATE 0.100 // unit: s\n#define CONTROL_RATE 0.010 // unit: s\n\n#define X_AXIS robotis_manipulator::math::vector3(1.0, 0.0, 0.0)\n#define Y_AXIS robotis_manipulator::math::vector3(0.0, 1.0, 0.0)\n#define Z_AXIS robotis_manipulator::math::vector3(0.0, 0.0, 1.0)\n\nclass Stewart : public robotis_manipulator::RobotisManipulator\n{\nprivate:\n  robotis_manipulator::Kinematics *kinematics_;\n  robotis_manipulator::JointActuator *joint_;  \n  robotis_manipulator::ToolActuator *tool_;    \n  robotis_manipulator::CustomTaskTrajectory *custom_trajectory_[CUSTOM_TRAJECTORY_SIZE];\n  \n  bool using_actual_robot_state_;\n  bool receive_data_flag_ = false;\n  double prev_receive_time_ = 0.0;\n  double prev_control_time_ = 0.0;\n\n public:\n  Stewart();\n  virtual ~Stewart();\n\n  void initDebug();\n  void initOpenManipulator(bool using_actual_robot_state, \n                           STRING usb_port = \"/dev/ttyUSB0\", \n                           STRING baud_rate = \"1000000\", \n                           float control_rate = CONTROL_RATE);\n  void processOpenManipulator(double present_time);\n\n  bool getUsingActualRobotState();\n  bool getReceiveDataFlag();\n  double getPrevReceiveTime();\n\n  void setReceiveDataFlag(bool receive_data_flag);\n  void setPrevReceiveTime(double prev_receive_time);\n};\n\n#endif // STEWART_H_\n\n\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/stewart_libs/include/stewart_libs/stewart_custom_trajectory.h",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef STEWART_CUSTOM_TRAJECTORY_H_\n#define STEWART_CUSTOM_TRAJECTORY_H_\n\n#if defined(__OPENCR__)\n  #include <RobotisManipulator.h>\n#else\n  #include <robotis_manipulator/robotis_manipulator.h>\n#endif\n\nusing namespace robotis_manipulator;\nusing namespace Eigen;\n\nnamespace stewart_custom_trajectory\n{\n  \nenum AXIS{\n\tX_AXIS,\n\tY_AXIS,\n\tZ_AXIS,\n};\n\n/*****************************************************************************\n** Line\n*****************************************************************************/\nclass Line : public robotis_manipulator::CustomTaskTrajectory\n{\nprivate:\n  TaskWaypoint start_pose_;\n  TaskWaypoint goal_pose_;\n\n  double acc_dec_time_;\n  double move_time_;\n  std::vector<double> vel_max_;\n\npublic:\n\tLine() {}\n\tvirtual ~Line() {}\n\n  void initLine(double move_time, TaskWaypoint start, TaskWaypoint delta);\n  TaskWaypoint drawLine(double time_var);\n\n  virtual void setOption(const void *arg);\n  virtual void makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg);\n  virtual TaskWaypoint getTaskWaypoint(double tick);\n};\n\n\n/*****************************************************************************\n** Circle\n*****************************************************************************/\nclass Circle : public robotis_manipulator::CustomTaskTrajectory\n{\nprivate:\n  robotis_manipulator::MinimumJerk path_generator_;\n  VectorXd coefficient_;\n\n  TaskWaypoint start_pose_;\n  TaskWaypoint goal_pose_;\n\n  double radius_;\n  double start_angular_position_;\n  double revolution_;\n\npublic:\n\tCircle() {}\n\tvirtual ~Circle() {}\n\n  void initCircle(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position);\n  TaskWaypoint drawCircle(double time_var);\n\n  virtual void setOption(const void *arg);\n  virtual void makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg);\n  virtual TaskWaypoint getTaskWaypoint(double tick);\n};\n\n\n/*****************************************************************************\n** Rhombus\n*****************************************************************************/\nclass Rhombus : public robotis_manipulator::CustomTaskTrajectory\n{\nprivate:\n  robotis_manipulator::MinimumJerk path_generator_;\n  VectorXd coefficient_;\n\n  TaskWaypoint start_pose_;\n  TaskWaypoint goal_pose_;\n\n  double radius_;\n  double start_angular_position_;\n  double revolution_;\n\npublic:\n\tRhombus() {}\n\tvirtual ~Rhombus() {}\n\n  void initRhombus(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position);\n  TaskWaypoint drawRhombus(double time_var);\n\n  virtual void setOption(const void *arg);\n  virtual void makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg);\n  virtual TaskWaypoint getTaskWaypoint(double tick);\n};\n\n\n/*****************************************************************************\n** Heart\n*****************************************************************************/\nclass Heart : public robotis_manipulator::CustomTaskTrajectory\n{\nprivate:\n  robotis_manipulator::MinimumJerk path_generator_;\n  VectorXd coefficient_;\n\n  TaskWaypoint start_pose_;\n  TaskWaypoint goal_pose_;\n\n  double radius_;\n  double start_angular_position_;\n  double revolution_;\n\npublic:\n\tHeart() {}\n\tvirtual ~Heart() {}\n\n  void initHeart(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position);\n  TaskWaypoint drawHeart(double tick);\n\n  virtual void setOption(const void *arg);\n  virtual void makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg);\n  virtual TaskWaypoint getTaskWaypoint(double tick);\n};\n\n\n} // namespace stewart_custom_trajectory\n#endif // STEWART_CUSTOM_TRAJECTORY_H_\n\n\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/stewart_libs/include/stewart_libs/stewart_dynamixel.h",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef STEWART_DYNAMIXEL_H_\n#define STEWART_DYNAMIXEL_H_\n\n#if defined(__OPENCR__)\n  #include <RobotisManipulator.h>\n  #include <DynamixelWorkbench.h>\n#else\n  #include <robotis_manipulator/robotis_manipulator.h>\n  #include <dynamixel_workbench_toolbox/dynamixel_workbench.h>\n#endif\n\nnamespace stewart_dynamixel\n{\n\n#define SYNC_WRITE_HANDLER 0\n#define SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT 0\n\n//#define CONTROL_LOOP_TIME 10;    //ms\n\n// Protocol 2.0\n#define ADDR_PRESENT_CURRENT_2 126\n#define ADDR_PRESENT_VELOCITY_2 128\n#define ADDR_PRESENT_POSITION_2 132\n#define ADDR_VELOCITY_TRAJECTORY_2 136\n#define ADDR_POSITION_TRAJECTORY_2 140\n#define ADDR_PROFILE_ACCELERATION_2 108\n#define ADDR_PROFILE_VELOCITY_2 112\n#define ADDR_GOAL_POSITION_2 116\n\n\n#define LENGTH_PRESENT_CURRENT_2 2\n#define LENGTH_PRESENT_VELOCITY_2 4\n#define LENGTH_PRESENT_POSITION_2 4\n#define LENGTH_VELOCITY_TRAJECTORY_2 4\n#define LENGTH_POSITION_TRAJECTORY_2 4\n#define LENGTH_PROFILE_ACCELERATION_2 4\n#define LENGTH_PROFILE_VELOCITY_2 4\n#define LENGTH_GOAL_POSITION_2 4\n\n\n// Protocol 1.0\n#define ADDR_PRESENT_CURRENT_1 = 40;\n#define ADDR_PRESENT_VELOCITY_1 = 38;\n#define ADDR_PRESENT_POSITION_1 = 36;\n\n#define LENGTH_PRESENT_CURRENT_1 = 2;\n#define LENGTH_PRESENT_VELOCITY_1 = 2;\n#define LENGTH_PRESENT_POSITION_1 = 2;\n\ntypedef struct\n{\n  std::vector<uint8_t> id;\n  uint8_t num;\n} Joint;\n\nclass JointDynamixel : public robotis_manipulator::JointActuator\n{\nprivate:\n  DynamixelWorkbench *dynamixel_workbench_;\n  Joint dynamixel_;\n\npublic:\n  JointDynamixel(){}\n  virtual ~JointDynamixel(){}\n\n\n  /*****************************************************************************\n  ** Joint Dynamixel Control Functions\n  *****************************************************************************/\n  virtual void init(std::vector<uint8_t> actuator_id, const void *arg);\n  virtual void setMode(std::vector<uint8_t> actuator_id, const void *arg);\n  virtual std::vector<uint8_t> getId();\n\n  virtual void enable();\n  virtual void disable();\n\n  virtual bool sendJointActuatorValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector);\n  virtual std::vector<robotis_manipulator::ActuatorValue> receiveJointActuatorValue(std::vector<uint8_t> actuator_id);\n\n\n  /*****************************************************************************\n  ** Functions called in Joint Dynamixel Control Functions\n  *****************************************************************************/\n  bool initialize(std::vector<uint8_t> actuator_id, STRING dxl_device_name, STRING dxl_baud_rate);\n  bool setOperatingMode(std::vector<uint8_t> actuator_id, STRING dynamixel_mode = \"position_mode\");\n  bool setSDKHandler(uint8_t actuator_id);\n  bool writeProfileValue(std::vector<uint8_t> actuator_id, STRING profile_mode, uint32_t value);\n  bool writeGoalPosition(std::vector<uint8_t> actuator_id, std::vector<double> radian_vector);\n  std::vector<robotis_manipulator::ActuatorValue> receiveAllDynamixelValue(std::vector<uint8_t> actuator_id);\n};\n\nclass JointDynamixelProfileControl : public robotis_manipulator::JointActuator\n{\nprivate:\n  DynamixelWorkbench *dynamixel_workbench_;\n  Joint dynamixel_;\n  float control_loop_time_; // unit: ms\n  std::map<uint8_t, robotis_manipulator::ActuatorValue> previous_goal_value_;\n\npublic:\n  JointDynamixelProfileControl(float control_loop_time = 0.010);\n  virtual ~JointDynamixelProfileControl(){}\n\n\n  /*****************************************************************************\n  ** Joint Dynamixel Profile Control Functions\n  *****************************************************************************/\n  virtual void init(std::vector<uint8_t> actuator_id, const void *arg);\n  virtual void setMode(std::vector<uint8_t> actuator_id, const void *arg);\n  virtual std::vector<uint8_t> getId();\n\n  virtual void enable();\n  virtual void disable();\n\n  virtual bool sendJointActuatorValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector);\n  virtual std::vector<robotis_manipulator::ActuatorValue> receiveJointActuatorValue(std::vector<uint8_t> actuator_id);\n\n\n  /*****************************************************************************\n  ** Functions called in Joint Dynamixel Profile Control Functions\n  *****************************************************************************/\n  bool initialize(std::vector<uint8_t> actuator_id, STRING dxl_device_name, STRING dxl_baud_rate);\n  bool setOperatingMode(std::vector<uint8_t> actuator_id, STRING dynamixel_mode = \"position_mode\");\n  bool setSDKHandler(uint8_t actuator_id);\n  bool writeProfileValue(std::vector<uint8_t> actuator_id, STRING profile_mode, uint32_t value);\n  bool writeGoalProfilingControlValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector);\n  std::vector<robotis_manipulator::ActuatorValue> receiveAllDynamixelValue(std::vector<uint8_t> actuator_id);\n};\n\nclass ToolDynamixel : public robotis_manipulator::ToolActuator\n{\n private:\n  DynamixelWorkbench *dynamixel_workbench_;\n  Joint dynamixel_;\n\n public:\n  ToolDynamixel() {}\n  virtual ~ToolDynamixel() {}\n\n\n  /*****************************************************************************\n  ** Tool Dynamixel Control Functions\n  *****************************************************************************/\n  virtual void init(uint8_t actuator_id, const void *arg);\n  virtual void setMode(const void *arg);\n  virtual uint8_t getId();\n\n  virtual void enable();\n  virtual void disable();\n\n  virtual bool sendToolActuatorValue(robotis_manipulator::ActuatorValue value);\n  virtual robotis_manipulator::ActuatorValue receiveToolActuatorValue();\n\n\n  /*****************************************************************************\n  ** Functions called in Tool Dynamixel Profile Control Functions\n  *****************************************************************************/\n  bool initialize(uint8_t actuator_id, STRING dxl_device_name, STRING dxl_baud_rate);\n  bool setOperatingMode(STRING dynamixel_mode = \"position_mode\");\n  bool writeProfileValue(STRING profile_mode, uint32_t value);\n  bool setSDKHandler();\n  bool writeGoalPosition(double radian);\n  double receiveDynamixelValue();\n};\n\n} // namespace stewart_dynamixel\n#endif // STEWART_DYNAMIXEL_H_\n\n\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/stewart_libs/include/stewart_libs/stewart_kinematics.h",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef STEWART_KINEMATICS_H_\n#define STEWART_KINEMATICS_H_\n\n#if defined(__OPENCR__)\n  #include <RobotisManipulator.h>\n#else\n  #include <robotis_manipulator/robotis_manipulator.h>\n#endif\n\nusing namespace Eigen;\nusing namespace robotis_manipulator;\n\nnamespace stewart_kinematics\n{\n\n/*****************************************************************************\n** Kinematics Solver Using Geometry\n*****************************************************************************/\nclass SolverUsingGeometry : public robotis_manipulator::Kinematics\n{\nprivate:\n  bool inverseKinematicsSolverUsingGeometry(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue>* goal_joint_value);\n\npublic:\n  SolverUsingGeometry() {}\n  virtual ~SolverUsingGeometry() {}\n\n  virtual void setOption(const void *arg);\n  virtual MatrixXd jacobian(Manipulator *manipulator, Name tool_name);\n  virtual void solveForwardKinematics(Manipulator *manipulator);\n  virtual bool solveInverseKinematics(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue>* goal_joint_value);\n};\n\n} // namespace stewart_kinematics\n\n#endif // STEWART_KINEMATICS_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/stewart_libs/src/stewart.cpp",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include \"../include/stewart_libs/stewart.h\"\n\nStewart::Stewart() {}\nStewart::~Stewart()\n{\n  delete kinematics_;\n  delete joint_;\n  delete tool_;\n  for(uint8_t index = 0; index < CUSTOM_TRAJECTORY_SIZE; index++)\n    delete custom_trajectory_[index];\n}\n\nvoid Stewart::initDebug()\n{\n  DEBUG.begin(57600); // Using Serial4(=SerialBT2)\n  log::print(\"OpenManipulator Debugging Port\"); \n}\n\nvoid Stewart::initOpenManipulator(bool using_actual_robot_state, STRING usb_port, STRING baud_rate, float control_rate)\n{\n  /*****************************************************************************\n  ** Set if using actual robot\n  *****************************************************************************/\n  using_actual_robot_state_ = using_actual_robot_state;  \n\n  /*****************************************************************************\n  ** Initialize Manipulator Parameters\n  *****************************************************************************/\n  addWorld(\"world\",   // world name\n           \"joint1\"); // child name\n\n  addJoint(\"joint01\",  // my name\n           \"world\",   // parent name\n           \"joint07\",  // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Z_AXIS,    // axis of rotation\n           1);        // actuator id\n\n  addJoint(\"joint02\",  // my name\n           \"world\",  // parent name\n           \"joint08\",  // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Z_AXIS,    // axis of rotation\n           2);        // actuator id\n\n  addJoint(\"joint03\",  // my name\n           \"world\",  // parent name\n           \"joint09\",  // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Z_AXIS,    // axis of rotation\n           3);        // actuator id\n\n  addJoint(\"joint04\",  // my name\n           \"world\",  // parent name\n           \"joint10\",  // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Z_AXIS,    // axis of rotation\n           4);        // actuator id\n\n  addJoint(\"joint05\",  // my name\n           \"world\",  // parent name\n           \"joint11\",  // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Z_AXIS,    // axis of rotation\n           5);        // actuator id\n\n  addJoint(\"joint06\",  // my name\n           \"world\",  // parent name\n           \"joint12\",    // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Z_AXIS,    // axis of rotation\n           6);        // actuator id\n\n  addJoint(\"joint07\",  // my name\n           \"joint01\",  // parent name\n           \"joint13\",    // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Z_AXIS,    // axis of rotation\n           -1);        // actuator id\n\n  addJoint(\"joint07_2\",  // my name\n           \"joint01\",  // parent name\n           \"joint13\",    // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Z_AXIS,    // axis of rotation\n           -1);        // actuator id\n\n  addJoint(\"joint08\",    // my name\n           \"joint02\",    // parent name\n           \"joint14\",   // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Z_AXIS,      // axis of rotation\n           -1);         // actuator id\n\n  addJoint(\"joint08_2\",  // my name\n           \"joint02\",    // parent name\n           \"joint14\",   // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Z_AXIS,      // axis of rotation\n           -1);         // actuator id\n\n  addJoint(\"joint09\",    // my name\n           \"joint03\",    // parent name\n           \"joint15\",   // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Z_AXIS,      // axis of rotation\n           -1);         // actuator id\n\n  addJoint(\"joint09_2\",  // my name\n           \"joint03\",    // parent name\n           \"joint15\",   // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Z_AXIS,      // axis of rotation\n           -1);         // actuator id\n\n  addJoint(\"joint10\",   // my name\n           \"joint04\",    // parent name\n           \"joint16\",   // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Z_AXIS,      // axis of rotation\n           -1);         // actuator id\n\n  addJoint(\"joint10_2\",  // my name\n           \"joint04\",  // parent name\n           \"joint16\",    // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Z_AXIS,    // axis of rotation\n           -1);        // actuator id\n\n  addJoint(\"joint11\",  // my name\n           \"joint05\",  // parent name\n           \"joint17\",    // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Z_AXIS,    // axis of rotation\n           -1);        // actuator id\n\n  addJoint(\"joint11_2\",  // my name\n           \"joint05\",  // parent name\n           \"joint17\",    // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Z_AXIS,    // axis of rotation\n           -1);        // actuator id\n\n  addJoint(\"joint12\",  // my name\n           \"joint06\",  // parent name\n           \"joint18\",    // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Z_AXIS,    // axis of rotation\n           -1);        // actuator id\n\n  addJoint(\"joint12_2\",  // my name\n           \"joint06\",  // parent name\n           \"joint18\",    // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Z_AXIS,    // axis of rotation\n           -1);        // actuator id\n\n  addJoint(\"joint13\",  // my name\n           \"joint07\",  // parent name\n           \"joint19\",    // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Z_AXIS,    // axis of rotation\n           -1);        // actuator id\n\n  addJoint(\"joint13_2\", // my name\n           \"joint07\",    // parent name\n           \"joint19\",      // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Z_AXIS,      // axis of rotation\n           -1);         // actuator id\n\n  addJoint(\"joint14\",  // my name\n           \"joint07\",   // parent name\n           \"tool\",     // child name\n           math::vector3(0.0, 0.0, 0.0),                    // Not used\n           math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n           Z_AXIS,     // axis of rotation\n           -1);        // actuator id\n\n  addTool(\"tool\",     // my name\n          \"joint14\",  // Not used\n          math::vector3(0.0, 0.0, 0.0),                    // Not used\n          math::convertRPYToRotationMatrix(0.0, 0.0, 0.0), // Not used\n          -1);        // actuator id\n\n  /*****************************************************************************\n  ** Initialize Kinematics \n  *****************************************************************************/\n  kinematics_ = new stewart_kinematics::SolverUsingGeometry();\n  addKinematics(kinematics_);\n  \n  /*****************************************************************************\n  ** Initialize Custom Trajectory\n  *****************************************************************************/\n  custom_trajectory_[0] = new stewart_custom_trajectory::Line();\n  custom_trajectory_[1] = new stewart_custom_trajectory::Circle();\n  custom_trajectory_[2] = new stewart_custom_trajectory::Rhombus();\n  custom_trajectory_[3] = new stewart_custom_trajectory::Heart();\n\n  addCustomTrajectory(CUSTOM_TRAJECTORY_LINE, custom_trajectory_[0]);\n  addCustomTrajectory(CUSTOM_TRAJECTORY_CIRCLE, custom_trajectory_[1]);\n  addCustomTrajectory(CUSTOM_TRAJECTORY_RHOMBUS, custom_trajectory_[2]);\n  addCustomTrajectory(CUSTOM_TRAJECTORY_HEART, custom_trajectory_[3]);\n\n  if (using_actual_robot_state_)\n  {\n    /*****************************************************************************\n    ** Initialize ㅓoint Actuator\n    *****************************************************************************/\n    joint_ = new stewart_dynamixel::JointDynamixelProfileControl(control_rate);\n\n    // Set communication arguments \n    STRING dxl_comm_arg[2] = {usb_port, baud_rate};\n    void *p_dxl_comm_arg = &dxl_comm_arg; \n\n    // Set joint actuator id \n    std::vector<uint8_t> jointDxlId;\n    jointDxlId.push_back(1);\n    jointDxlId.push_back(2);\n    jointDxlId.push_back(3);\n    jointDxlId.push_back(4);\n    jointDxlId.push_back(5);\n    jointDxlId.push_back(6);\n    addJointActuator(JOINT_DYNAMIXEL, joint_, jointDxlId, p_dxl_comm_arg);\n\n    // Set joint actuator control mode\n    STRING joint_dxl_mode_arg = \"position_mode\";\n    void *p_joint_dxl_mode_arg = &joint_dxl_mode_arg;\n    setJointActuatorMode(JOINT_DYNAMIXEL, jointDxlId, p_joint_dxl_mode_arg);\n\n    /*****************************************************************************\n    ** Enable actuators and Receive actuator values \n    *****************************************************************************/\n    // Enable All Actuators \n    enableAllActuator();\n\n    // Receive current angles from all actuators \n    receiveAllJointActuatorValue();\n  }\n}\n\n/*****************************************************************************\n** Process actuator values received from external controllers\n*****************************************************************************/\nvoid Stewart::processOpenManipulator(double present_time)\n{\n  if (present_time - prev_control_time_ >= CONTROL_RATE)\n  {\n    JointWaypoint goal_joint_value = getJointGoalValueFromTrajectory(present_time);\n    if(goal_joint_value.size() != 0) sendAllJointActuatorValue(goal_joint_value);\n    \n    // Set previous control time\n    prev_control_time_ = millis()/1000.0;\n  }\n}\n\n/*****************************************************************************\n** State Functions\n*****************************************************************************/\n// Check if using acutal robot \nbool Stewart::getUsingActualRobotState() \n{\n  return using_actual_robot_state_;\n}\n\n/* Check if the program read data within control rate) */\nbool Stewart::getReceiveDataFlag()  \n{\n  return receive_data_flag_;\n}\n\n/* Get the previous time when data were received */\ndouble Stewart::getPrevReceiveTime() \n{\n  return prev_receive_time_;\n}\n\n/* Set whether data were received or not */\nvoid Stewart::setReceiveDataFlag(bool receive_data_flag) \n{\n  receive_data_flag_ = receive_data_flag;\n}\n\n/* Set the previous time when data were received */\nvoid Stewart::setPrevReceiveTime(double prev_receive_time)  \n{\n  prev_receive_time_ = prev_receive_time;\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/stewart_libs/src/stewart_custom_trajectory.cpp",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include \"../include/stewart_libs/stewart_custom_trajectory.h\"\n\nusing namespace stewart_custom_trajectory;\nusing namespace Eigen;\n\n\n/*****************************************************************************\n** Line\n*****************************************************************************/\nvoid Line::initLine(double move_time, TaskWaypoint start, TaskWaypoint delta)\n{\n  move_time_ = move_time;\n  acc_dec_time_ = move_time_ * 0.2;\n  vel_max_.resize(3);\n\n  TaskWaypoint start_to_goal;\n\n  start_pose_ = start;\n\n  goal_pose_ .kinematic.orientation = start_pose_.kinematic.orientation;\n  goal_pose_ .kinematic.position = start.kinematic.position + delta.kinematic.position;\n\n  vel_max_.at(X_AXIS) = delta.kinematic.position(X_AXIS)/(move_time_ - acc_dec_time_);\n  vel_max_.at(Y_AXIS) = delta.kinematic.position(Y_AXIS)/(move_time_ - acc_dec_time_);\n  vel_max_.at(Z_AXIS) = delta.kinematic.position(Z_AXIS)/(move_time_ - acc_dec_time_);\n}\n\nTaskWaypoint Line::drawLine(double time_var)\n{\n  TaskWaypoint pose;\n\n  if(acc_dec_time_ >= time_var)\n  {\n    pose.kinematic.position(X_AXIS) = 0.5*vel_max_.at(X_AXIS)*pow(time_var, 2)/acc_dec_time_ + start_pose_.kinematic.position(X_AXIS);\n    pose.kinematic.position(Y_AXIS) = 0.5*vel_max_.at(Y_AXIS)*pow(time_var, 2)/acc_dec_time_ + start_pose_.kinematic.position(Y_AXIS);\n    pose.kinematic.position(Z_AXIS) = 0.5*vel_max_.at(Z_AXIS)*pow(time_var, 2)/acc_dec_time_ + start_pose_.kinematic.position(Z_AXIS);\n  }\n  else if(time_var > acc_dec_time_ && (move_time_ - acc_dec_time_) >= time_var )\n  {\n    pose.kinematic.position(X_AXIS) = vel_max_.at(X_AXIS)*(time_var-(acc_dec_time_*0.5)) + start_pose_.kinematic.position(X_AXIS);\n    pose.kinematic.position(Y_AXIS) = vel_max_.at(Y_AXIS)*(time_var-(acc_dec_time_*0.5)) + start_pose_.kinematic.position(Y_AXIS);\n    pose.kinematic.position(Z_AXIS) = vel_max_.at(Z_AXIS)*(time_var-(acc_dec_time_*0.5)) + start_pose_.kinematic.position(Z_AXIS);\n  }\n  else if(time_var > (move_time_ - acc_dec_time_) && (time_var < move_time_))\n  {\n    pose.kinematic.position(X_AXIS) = goal_pose_.kinematic.position(X_AXIS) - vel_max_.at(X_AXIS)*0.5/acc_dec_time_*(pow((move_time_-time_var),2));\n    pose.kinematic.position(Y_AXIS) = goal_pose_.kinematic.position(Y_AXIS) - vel_max_.at(Y_AXIS)*0.5/acc_dec_time_*(pow((move_time_-time_var),2));\n    pose.kinematic.position(Z_AXIS) = goal_pose_.kinematic.position(Z_AXIS) - vel_max_.at(Z_AXIS)*0.5/acc_dec_time_*(pow((move_time_-time_var),2));\n  }\n  else if(time_var <= move_time_)\n  {\n    pose.kinematic.position(X_AXIS) = goal_pose_.kinematic.position(X_AXIS);\n    pose.kinematic.position(Y_AXIS) = goal_pose_.kinematic.position(Y_AXIS);\n    pose.kinematic.position(Z_AXIS) = goal_pose_.kinematic.position(Z_AXIS);\n  }\n\n  pose.kinematic.orientation = start_pose_.kinematic.orientation;\n  pose.dynamic.linear.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.linear.acceleration = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.acceleration = Eigen::Vector3d::Zero(3);\n\n  return pose;\n}\n\nTaskWaypoint Line::getTaskWaypoint(double tick)\n{\n  return drawLine(tick);\n}\n\n\nvoid Line::makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg)\n{\n  TaskWaypoint *c_arg = (TaskWaypoint *)arg;\n  initLine(move_time, start, c_arg[0]);\n}\nvoid Line::setOption(const void *arg) {}\n\n\n/*****************************************************************************\n** Circle\n*****************************************************************************/\nvoid Circle::initCircle(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position)\n{\n  start_pose_ = start;\n\n  radius_ = radius;\n  revolution_ = revolution;\n  start_angular_position_ = start_angular_position;\n\n  Point drawingStart, drawingGoal;\n\n  drawingStart.position = 0.0;\n  drawingStart.velocity = 0.0;\n  drawingStart.acceleration = 0.0;\n  drawingStart.effort = 0.0;\n\n  drawingGoal.position = revolution_ * 2*M_PI;\n  drawingGoal.velocity = 0.0;\n  drawingGoal.acceleration = 0.0;\n  drawingGoal.effort = 0.0;\n\n  path_generator_.calcCoefficient(drawingStart, drawingGoal, move_time);\n  coefficient_ = path_generator_.getCoefficient();\n}\n\nTaskWaypoint Circle::drawCircle(double tick)\n{\n  // get time variable\n  double get_time_var = 0.0;\n\n  get_time_var = coefficient_(0) +\n                 coefficient_(1) * pow(tick, 1) +\n                 coefficient_(2) * pow(tick, 2) +\n                 coefficient_(3) * pow(tick, 3) +\n                 coefficient_(4) * pow(tick, 4) +\n                 coefficient_(5) * pow(tick, 5);\n\n  // set drawing trajectory\n  TaskWaypoint pose;\n\n  double diff_pose[2];\n\n  diff_pose[0] = (cos(get_time_var)-1)*cos(start_angular_position_) - sin(get_time_var)*sin(start_angular_position_);\n  diff_pose[1] = (cos(get_time_var)-1)*sin(start_angular_position_) + sin(get_time_var)*cos(start_angular_position_);\n\n  pose.kinematic.position(X_AXIS) = start_pose_.kinematic.position(X_AXIS) + radius_ * diff_pose[0];\n  pose.kinematic.position(Y_AXIS) = start_pose_.kinematic.position(Y_AXIS) + radius_ * diff_pose[1];\n  pose.kinematic.position(Z_AXIS) = start_pose_.kinematic.position(Z_AXIS);\n\n  pose.kinematic.orientation = start_pose_.kinematic.orientation;\n\n  pose.dynamic.linear.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.linear.acceleration = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.acceleration = Eigen::Vector3d::Zero(3);\n\n  return pose;\n}\n\nTaskWaypoint Circle::getTaskWaypoint(double tick)\n{\n  return drawCircle(tick);\n}\n\nvoid Circle::makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg)\n{\n  double *get_arg_ = (double *)arg;\n  initCircle(move_time, start, get_arg_[0], get_arg_[1], get_arg_[2]);\n}\n\nvoid Circle::setOption(const void *arg){}\n\n\n/*****************************************************************************\n** Rhombus\n*****************************************************************************/\nvoid Rhombus::initRhombus(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position)\n{\n  start_pose_ = start;\n\n  radius_ = radius;\n  revolution_ = revolution;\n  start_angular_position_ = start_angular_position;\n\n  Point drawingStart, drawingGoal;\n\n  drawingStart.position = 0.0;\n  drawingStart.velocity = 0.0;\n  drawingStart.acceleration = 0.0;\n  drawingStart.effort = 0.0;\n\n  drawingGoal.position = revolution_ * 2*M_PI;\n  drawingGoal.velocity = 0.0;\n  drawingGoal.acceleration = 0.0;\n  drawingGoal.effort = 0.0;\n\n  path_generator_.calcCoefficient(drawingStart, drawingGoal, move_time);\n  coefficient_ = path_generator_.getCoefficient();\n}\n\n\nTaskWaypoint Rhombus::drawRhombus(double tick)\n{\n  // get time variable\n  double get_time_var = 0.0;\n\n  get_time_var = coefficient_(0) +\n                 coefficient_(1) * pow(tick, 1) +\n                 coefficient_(2) * pow(tick, 2) +\n                 coefficient_(3) * pow(tick, 3) +\n                 coefficient_(4) * pow(tick, 4) +\n                 coefficient_(5) * pow(tick, 5); \n\n  // set drawing trajectory\n  TaskWaypoint pose;\n  double diff_pose[2];\n  double traj[2];\n\n  while(true)\n  {\n    if (get_time_var < PI*2) break;\n    get_time_var = get_time_var - PI*2;\n  }\n\n  if (get_time_var >= 0 && get_time_var < PI/2){\n    traj[0] = - get_time_var / (PI/2);\n    traj[1] = - get_time_var / (PI/2);\n  } else if (get_time_var >= PI/2 && get_time_var < PI){\n    traj[0] = - get_time_var / (PI/2);\n    traj[1] = get_time_var / (PI/2) - 2;\n  } else if (get_time_var >= PI && get_time_var < PI*3/2){\n    traj[0] = get_time_var / (PI/2) - 4;\n    traj[1] = get_time_var / (PI/2) - 2;\n  } else {\n    traj[0] = get_time_var / (PI/2) - 4;\n    traj[1] = - get_time_var / (PI/2) + 4;\n  }\n  \n\n  diff_pose[0] = traj[0]*cos(start_angular_position_) - traj[1]*sin(start_angular_position_);\n  diff_pose[1] = traj[0]*sin(start_angular_position_) + traj[1]*cos(start_angular_position_);\n\n  pose.kinematic.position(X_AXIS) = start_pose_.kinematic.position(X_AXIS) + radius_ * diff_pose[0];\n  pose.kinematic.position(Y_AXIS) = start_pose_.kinematic.position(Y_AXIS) + radius_ * diff_pose[1];\n  pose.kinematic.position(Z_AXIS) = start_pose_.kinematic.position(Z_AXIS);\n\n  pose.kinematic.orientation = start_pose_.kinematic.orientation;\n\n  pose.dynamic.linear.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.linear.acceleration = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.acceleration = Eigen::Vector3d::Zero(3);\n\n  return pose;\n}\n\n\nvoid Rhombus::makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg)\n{\n  double *get_arg_ = (double *)arg;\n  initRhombus(move_time, start, get_arg_[0], get_arg_[1], get_arg_[2]);\n}\n\nTaskWaypoint Rhombus::getTaskWaypoint(double tick)\n{\n  return drawRhombus(tick);\n}\nvoid Rhombus::setOption(const void *arg){}\n\n\n/*****************************************************************************\n** Heart\n*****************************************************************************/\nvoid Heart::initHeart(double move_time, TaskWaypoint start, double radius, double revolution, double start_angular_position)\n{\n  start_pose_ = start;\n\n  radius_ = radius;\n  revolution_ = revolution;\n  start_angular_position_ = start_angular_position;\n\n  Point drawingStart, drawingGoal;\n\n  drawingStart.position = 0.0;\n  drawingStart.velocity = 0.0;\n  drawingStart.acceleration = 0.0;\n  drawingStart.effort = 0.0;\n\n  drawingGoal.position = revolution_ * 2*M_PI;\n  drawingGoal.velocity = 0.0;\n  drawingGoal.acceleration = 0.0;\n  drawingGoal.effort = 0.0;\n\n  path_generator_.calcCoefficient(drawingStart, drawingGoal, move_time);\n  coefficient_ = path_generator_.getCoefficient();\n}\n\nTaskWaypoint Heart::drawHeart(double tick)\n{\n  // get time variable\n  double get_time_var = 0.0;\n\n  get_time_var = coefficient_(0) +\n                 coefficient_(1) * pow(tick, 1) +\n                 coefficient_(2) * pow(tick, 2) +\n                 coefficient_(3) * pow(tick, 3) +\n                 coefficient_(4) * pow(tick, 4) +\n                 coefficient_(5) * pow(tick, 5);\n\n  // set drawing trajectory\n  TaskWaypoint pose;\n  double diff_pose[2];\n  double traj[2];\n\n\tdouble shift_offset = - 5.0;\n\n  traj[0] = (shift_offset + (13*cos(get_time_var) - 5*cos(2*get_time_var) - 2*cos(3*get_time_var) - cos(4*get_time_var))) / 16;\n  traj[1] = (16*sin(get_time_var)*sin(get_time_var)*sin(get_time_var)) / 16;\n\n  diff_pose[0] = traj[0]*cos(start_angular_position_) - traj[1]*sin(start_angular_position_);\n  diff_pose[1] = traj[0]*sin(start_angular_position_) + traj[1]*cos(start_angular_position_);\n\n  pose.kinematic.position(X_AXIS) = start_pose_.kinematic.position(X_AXIS) + radius_ * diff_pose[0];\n  pose.kinematic.position(Y_AXIS) = start_pose_.kinematic.position(Y_AXIS) + radius_ * diff_pose[1];\n  pose.kinematic.position(Z_AXIS) = start_pose_.kinematic.position(Z_AXIS);\n\n  pose.kinematic.orientation = start_pose_.kinematic.orientation;\n\n  pose.dynamic.linear.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.linear.acceleration = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.velocity = Eigen::Vector3d::Zero(3);\n  pose.dynamic.angular.acceleration = Eigen::Vector3d::Zero(3);\n\n  return pose;\n}\n\nvoid Heart::makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg)\n{\n  double *get_arg_ = (double *)arg;\n  initHeart(move_time, start, get_arg_[0], get_arg_[1], get_arg_[2]);\n}\nvoid Heart::setOption(const void *arg){}\n\nTaskWaypoint Heart::getTaskWaypoint(double tick)\n{\n  return drawHeart(tick);\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/stewart_libs/src/stewart_dynamixel.cpp",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include \"../include/stewart_libs/stewart_dynamixel.h\"\n\nusing namespace stewart_dynamixel;\nusing namespace robotis_manipulator;\n\n/*****************************************************************************\n** Joint Dynamixel Control Functions\n*****************************************************************************/\nvoid JointDynamixel::init(std::vector<uint8_t> actuator_id, const void *arg)\n{\n  STRING *get_arg_ = (STRING *)arg;\n\n  bool result = JointDynamixel::initialize(actuator_id ,get_arg_[0], get_arg_[1]);\n\n  if (result == false)\n    return;\n}\n\nvoid JointDynamixel::setMode(std::vector<uint8_t> actuator_id, const void *arg)\n{\n  bool result = false;\n  // const char* log = NULL;\n\n  STRING *get_arg_ = (STRING *)arg;\n\n  if (get_arg_[0] == \"position_mode\" || get_arg_[0] == \"current_based_position_mode\")\n  {\n    result = JointDynamixel::setOperatingMode(actuator_id, get_arg_[0]);\n    if (result == false)\n      return;\n\n    result = JointDynamixel::setSDKHandler(actuator_id.at(0));\n    if (result == false)\n      return;\n  }\n  else\n  {\n    result = JointDynamixel::writeProfileValue(actuator_id, get_arg_[0], std::atoi(get_arg_[1].c_str()));\n    if (result == false)\n      return;\n  }\n  return;\n}\n\nstd::vector<uint8_t> JointDynamixel::getId()\n{\n  return dynamixel_.id;\n}\n\nvoid JointDynamixel::enable()\n{\n  const char* log = NULL;\n  bool result = false;\n  \n  for (uint32_t index = 0; index < dynamixel_.num; index++)\n  {\n    result = dynamixel_workbench_->torqueOn(dynamixel_.id.at(index), &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  enabled_state_ = true;\n}\n\nvoid JointDynamixel::disable()\n{\n  const char* log = NULL;\n  bool result = false;\n  \n  for (uint32_t index = 0; index < dynamixel_.num; index++)\n  {\n    result = dynamixel_workbench_->torqueOff(dynamixel_.id.at(index), &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  enabled_state_ = false;\n}\n\nbool JointDynamixel::sendJointActuatorValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector)\n{\n  bool result = false;\n\n  std::vector<double> radian_vector;\n  for(uint32_t index = 0; index < value_vector.size(); index++)\n  {\n    radian_vector.push_back(value_vector.at(index).position);\n  }\n  result = JointDynamixel::writeGoalPosition(actuator_id, radian_vector);\n  if (result == false)\n    return false;\n\n  return true;\n}\n\nstd::vector<robotis_manipulator::ActuatorValue> JointDynamixel::receiveJointActuatorValue(std::vector<uint8_t> actuator_id)\n{\n  return JointDynamixel::receiveAllDynamixelValue(actuator_id);\n}\n\n\n/*****************************************************************************\n** Functions called in Joint Dynamixel Control Functions\n*****************************************************************************/\nbool JointDynamixel::initialize(std::vector<uint8_t> actuator_id, STRING dxl_device_name, STRING dxl_baud_rate)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  STRING return_delay_time_st = \"Return_Delay_Time\";\n  const char * return_delay_time_char = return_delay_time_st.c_str();\n\n  dynamixel_.id = actuator_id;\n  dynamixel_.num = actuator_id.size();\n\n  dynamixel_workbench_ = new DynamixelWorkbench;\n\n  result = dynamixel_workbench_->init(dxl_device_name.c_str(), std::atoi(dxl_baud_rate.c_str()), &log);\n  if (result == false)\n  {\n    log::error(log);\n  }    \n\n  uint16_t get_model_number;\n  for (uint8_t index = 0; index < dynamixel_.num; index++)\n  {\n    uint8_t id = dynamixel_.id.at(index);\n    result = dynamixel_workbench_->ping(id, &get_model_number, &log);\n\n    if (result == false)\n    {\n      log::error(log);\n      log::error(\"Please check your Dynamixel ID\");\n    }\n    else\n    {\n      char str[100];\n      sprintf(str, \"Joint Dynamixel ID : %d, Model Name : %s\", id, dynamixel_workbench_->getModelName(id));\n      log::println(str);\n\n      result = dynamixel_workbench_->setVelocityBasedProfile(id, &log);\n      if(result == false)\n      {\n        log::error(log);\n        log::error(\"Please check your Dynamixel firmware version (v38~)\");\n      }\n\n      result = dynamixel_workbench_->writeRegister(id, return_delay_time_char, 0, &log);\n      if (result == false)\n      {\n        log::error(log);\n        log::error(\"Please check your Dynamixel firmware version\");\n      }\n    }\n  }\n  return true;\n}\n\nbool JointDynamixel::setOperatingMode(std::vector<uint8_t> actuator_id, STRING dynamixel_mode)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const uint32_t velocity = 0;\n  const uint32_t acceleration = 0;\n  const uint32_t current = 0;\n\n  if (dynamixel_mode == \"position_mode\")\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->jointMode(actuator_id.at(num), velocity, acceleration, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n  else if (dynamixel_mode == \"current_based_position_mode\")\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->currentBasedPositionMode(actuator_id.at(num), current, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n  else\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->jointMode(actuator_id.at(num), velocity, acceleration, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n\n  return true;\n}\n\nbool JointDynamixel::setSDKHandler(uint8_t actuator_id)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  result = dynamixel_workbench_->addSyncWriteHandler(actuator_id, \"Goal_Position\", &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->addSyncReadHandler(ADDR_PRESENT_CURRENT_2, \n                                                    (LENGTH_PRESENT_CURRENT_2 + LENGTH_PRESENT_VELOCITY_2 + LENGTH_PRESENT_POSITION_2), \n                                                    &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\nbool JointDynamixel::writeProfileValue(std::vector<uint8_t> actuator_id, STRING profile_mode, uint32_t value)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const char * char_profile_mode = profile_mode.c_str();\n\n  for (uint8_t num = 0; num < actuator_id.size(); num++)\n  {\n    result = dynamixel_workbench_->writeRegister(actuator_id.at(num), char_profile_mode, value, &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n\n  return true;\n}\n\nbool JointDynamixel::writeGoalPosition(std::vector<uint8_t> actuator_id, std::vector<double> radian_vector)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  uint8_t id_array[actuator_id.size()];\n  int32_t goal_position[actuator_id.size()];\n\n  for (uint8_t index = 0; index < actuator_id.size(); index++)\n  {\n    id_array[index] = actuator_id.at(index);\n    goal_position[index] = dynamixel_workbench_->convertRadian2Value(actuator_id.at(index), radian_vector.at(index));\n  }\n\n  result = dynamixel_workbench_->syncWrite(SYNC_WRITE_HANDLER, id_array, actuator_id.size(), goal_position, 1, &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\nstd::vector<robotis_manipulator::ActuatorValue> JointDynamixel::receiveAllDynamixelValue(std::vector<uint8_t> actuator_id)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  std::vector<robotis_manipulator::ActuatorValue> all_actuator;\n\n  uint8_t id_array[actuator_id.size()];\n  for (uint8_t index = 0; index < actuator_id.size(); index++)\n    id_array[index] = actuator_id.at(index);\n\n  int32_t get_current[actuator_id.size()];\n  int32_t get_velocity[actuator_id.size()];\n  int32_t get_position[actuator_id.size()];\n\n  result = dynamixel_workbench_->syncRead(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                          id_array,\n                                          actuator_id.size(),\n                                          &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                id_array,\n                                                actuator_id.size(),\n                                                ADDR_PRESENT_CURRENT_2,\n                                                LENGTH_PRESENT_CURRENT_2,\n                                                get_current,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                 id_array,\n                                                 actuator_id.size(),\n                                                ADDR_PRESENT_VELOCITY_2,\n                                                LENGTH_PRESENT_VELOCITY_2,\n                                                get_velocity,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                 id_array,\n                                                 actuator_id.size(),\n                                                ADDR_PRESENT_POSITION_2,\n                                                LENGTH_PRESENT_POSITION_2,\n                                                get_position,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  for (uint8_t index = 0; index < actuator_id.size(); index++)\n  {\n    robotis_manipulator::ActuatorValue actuator;\n    actuator.effort = dynamixel_workbench_->convertValue2Current(get_current[index]);\n    actuator.velocity = dynamixel_workbench_->convertValue2Velocity(actuator_id.at(index), get_velocity[index]);\n    actuator.position = dynamixel_workbench_->convertValue2Radian(actuator_id.at(index), get_position[index]);\n\n    all_actuator.push_back(actuator);\n  }\n\n  return all_actuator;\n}\n\n\n/*****************************************************************************\n** Joint Dynamixel Profile Control Functions\n*****************************************************************************/\nJointDynamixelProfileControl::JointDynamixelProfileControl(float control_loop_time)\n{\n  control_loop_time_ = control_loop_time;\n}\n\nvoid JointDynamixelProfileControl::init(std::vector<uint8_t> actuator_id, const void *arg)\n{\n  STRING *get_arg_ = (STRING *)arg;\n\n  bool result = JointDynamixelProfileControl::initialize(actuator_id ,get_arg_[0], get_arg_[1]);\n\n  if (result == false)\n    return;\n}\n\nvoid JointDynamixelProfileControl::setMode(std::vector<uint8_t> actuator_id, const void *arg)\n{\n  bool result = false;\n  // const char* log = NULL;\n\n  STRING *get_arg_ = (STRING *)arg;\n\n  if (get_arg_[0] == \"position_mode\" || get_arg_[0] == \"current_based_position_mode\")\n  {\n    result = JointDynamixelProfileControl::setOperatingMode(actuator_id, get_arg_[0]);\n    if (result == false)\n      return;\n\n    result = JointDynamixelProfileControl::setSDKHandler(actuator_id.at(0));\n    if (result == false)\n      return;\n  }\n  else\n  {\n    result = JointDynamixelProfileControl::writeProfileValue(actuator_id, get_arg_[0], std::atoi(get_arg_[1].c_str()));\n    if (result == false)\n      return;\n  }\n  return;\n}\n\nstd::vector<uint8_t> JointDynamixelProfileControl::getId()\n{\n  return dynamixel_.id;\n}\n\nvoid JointDynamixelProfileControl::enable()\n{\n  const char* log = NULL;\n  bool result = false;\n\n  for (uint32_t index = 0; index < dynamixel_.num; index++)\n  {\n    result = dynamixel_workbench_->torqueOn(dynamixel_.id.at(index), &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  enabled_state_ = true;\n}\n\nvoid JointDynamixelProfileControl::disable()\n{\n  const char* log = NULL;\n  bool result = false;\n\n  for (uint32_t index = 0; index < dynamixel_.num; index++)\n  {\n    result = dynamixel_workbench_->torqueOff(dynamixel_.id.at(index), &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  enabled_state_ = false;\n}\n\nbool JointDynamixelProfileControl::sendJointActuatorValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector)\n{\n  bool result = false;\n\n  result = JointDynamixelProfileControl::writeGoalProfilingControlValue(actuator_id, value_vector);\n  if (result == false)\n    return false;\n\n  return true;\n}\n\nstd::vector<robotis_manipulator::ActuatorValue> JointDynamixelProfileControl::receiveJointActuatorValue(std::vector<uint8_t> actuator_id)\n{\n  return JointDynamixelProfileControl::receiveAllDynamixelValue(actuator_id);\n}\n\n\n/*****************************************************************************\n** Functions called in Joint Dynamixel Profile Control Functions\n*****************************************************************************/\nbool JointDynamixelProfileControl::initialize(std::vector<uint8_t> actuator_id, STRING dxl_device_name, STRING dxl_baud_rate)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  STRING return_delay_time_st = \"Return_Delay_Time\";\n  const char * return_delay_time_char = return_delay_time_st.c_str();\n\n  dynamixel_.id = actuator_id;\n  dynamixel_.num = actuator_id.size();\n\n  dynamixel_workbench_ = new DynamixelWorkbench;\n\n  result = dynamixel_workbench_->init(dxl_device_name.c_str(), std::atoi(dxl_baud_rate.c_str()), &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  uint16_t get_model_number;\n  for (uint8_t index = 0; index < dynamixel_.num; index++)\n  {\n    uint8_t id = dynamixel_.id.at(index);\n    result = dynamixel_workbench_->ping(id, &get_model_number, &log);\n\n    if (result == false)\n    {\n      log::error(log);\n      log::error(\"Please check your Dynamixel ID\");\n    }\n    else\n    {\n      char str[100];\n      sprintf(str, \"Joint Dynamixel ID : %d, Model Name : %s\", id, dynamixel_workbench_->getModelName(id));\n      log::println(str);\n\n      result = dynamixel_workbench_->setTimeBasedProfile(id, &log);\n      if(result == false)\n      {\n        log::error(log);\n        log::error(\"Please check your Dynamixel firmware version (v38~)\");\n      }\n\n      result = dynamixel_workbench_->writeRegister(id, return_delay_time_char, 0, &log);\n      if (result == false)\n      {\n        log::error(log);\n        log::error(\"Please check your Dynamixel firmware version\");\n      }\n    }\n  }\n  return true;\n}\n\nbool JointDynamixelProfileControl::setOperatingMode(std::vector<uint8_t> actuator_id, STRING dynamixel_mode)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const uint32_t velocity = uint32_t(control_loop_time_*1000) * 3;\n  const uint32_t acceleration = uint32_t(control_loop_time_*1000);\n  const uint32_t current = 0;\n\n  if (dynamixel_mode == \"position_mode\")\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->jointMode(actuator_id.at(num), velocity, acceleration, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n  else if (dynamixel_mode == \"current_based_position_mode\")\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->currentBasedPositionMode(actuator_id.at(num), current, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n  else\n  {\n    for (uint8_t num = 0; num < actuator_id.size(); num++)\n    {\n      result = dynamixel_workbench_->jointMode(actuator_id.at(num), velocity, acceleration, &log);\n      if (result == false)\n      {\n        log::error(log);\n      }\n    }\n  }\n\n  return true;\n}\n\nbool JointDynamixelProfileControl::setSDKHandler(uint8_t actuator_id)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  result = dynamixel_workbench_->addSyncWriteHandler(actuator_id, \"Goal_Position\", &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->addSyncReadHandler(ADDR_PRESENT_CURRENT_2,\n                                                    (LENGTH_PRESENT_CURRENT_2 + LENGTH_PRESENT_VELOCITY_2 + LENGTH_PRESENT_POSITION_2),\n                                                    &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\nbool JointDynamixelProfileControl::writeProfileValue(std::vector<uint8_t> actuator_id, STRING profile_mode, uint32_t value)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const char * char_profile_mode = profile_mode.c_str();\n\n  for (uint8_t num = 0; num < actuator_id.size(); num++)\n  {\n    result = dynamixel_workbench_->writeRegister(actuator_id.at(num), char_profile_mode, value, &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  return true;\n}\n\nbool JointDynamixelProfileControl::writeGoalProfilingControlValue(std::vector<uint8_t> actuator_id, std::vector<robotis_manipulator::ActuatorValue> value_vector)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  uint8_t id_array[actuator_id.size()];\n  int32_t goal_value[actuator_id.size()];\n\n  //add tarajectory eq.\n  for(uint8_t index = 0; index < actuator_id.size(); index++)\n  {\n    float result_position;\n    float time_control = control_loop_time_;       //ms\n\n    if(previous_goal_value_.find(actuator_id.at(index)) == previous_goal_value_.end())\n    {\n      previous_goal_value_.insert(std::make_pair(actuator_id.at(index), value_vector.at(index)));\n    }\n\n    result_position = value_vector.at(index).position + 3*(value_vector.at(index).velocity * (time_control))/2;\n\n    id_array[index] = actuator_id.at(index);\n    goal_value[index] = dynamixel_workbench_->convertRadian2Value(actuator_id.at(index), result_position);\n\n    previous_goal_value_[actuator_id.at(index)] = value_vector.at(index);\n  }\n\n  result = dynamixel_workbench_->syncWrite(SYNC_WRITE_HANDLER, id_array, actuator_id.size(), goal_value, 1, &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n  return true;\n}\n\nstd::vector<robotis_manipulator::ActuatorValue> JointDynamixelProfileControl::receiveAllDynamixelValue(std::vector<uint8_t> actuator_id)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  std::vector<robotis_manipulator::ActuatorValue> all_actuator;\n\n  uint8_t id_array[actuator_id.size()];\n  for (uint8_t index = 0; index < actuator_id.size(); index++)\n    id_array[index] = actuator_id.at(index);\n\n  int32_t get_current[actuator_id.size()];\n  int32_t get_velocity[actuator_id.size()];\n  int32_t get_position[actuator_id.size()];\n\n  result = dynamixel_workbench_->syncRead(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                          id_array,\n                                          actuator_id.size(),\n                                          &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                id_array,\n                                                actuator_id.size(),\n                                                ADDR_PRESENT_CURRENT_2,\n                                                LENGTH_PRESENT_CURRENT_2,\n                                                get_current,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                 id_array,\n                                                 actuator_id.size(),\n                                                ADDR_PRESENT_VELOCITY_2,\n                                                LENGTH_PRESENT_VELOCITY_2,\n                                                get_velocity,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT,\n                                                 id_array,\n                                                 actuator_id.size(),\n                                                ADDR_PRESENT_POSITION_2,\n                                                LENGTH_PRESENT_POSITION_2,\n                                                get_position,\n                                                &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  for (uint8_t index = 0; index < actuator_id.size(); index++)\n  {\n    robotis_manipulator::ActuatorValue actuator;\n    actuator.effort = dynamixel_workbench_->convertValue2Current(get_current[index]);\n    actuator.velocity = dynamixel_workbench_->convertValue2Velocity(actuator_id.at(index), get_velocity[index]);\n    actuator.position = dynamixel_workbench_->convertValue2Radian(actuator_id.at(index), get_position[index]);\n\n    all_actuator.push_back(actuator);\n  }\n\n  return all_actuator;\n}\n\n\n/*****************************************************************************\n** Tool Dynamixel Control Functions\n*****************************************************************************/\nvoid ToolDynamixel::init(uint8_t actuator_id, const void *arg)\n{\n  STRING *get_arg_ = (STRING *)arg;\n\n  bool result = ToolDynamixel::initialize(actuator_id ,get_arg_[0], get_arg_[1]);\n\n  if (result == false)\n    return;\n}\n\nvoid ToolDynamixel::setMode(const void *arg)\n{\n  bool result = false;\n// const char* log = NULL;\n\n  STRING *get_arg_ = (STRING *)arg;\n\n  if (get_arg_[0] == \"position_mode\" || get_arg_[0] == \"current_based_position_mode\")\n  {\n    result = ToolDynamixel::setOperatingMode(get_arg_[0]);\n    if (result == false)\n      return;\n  }\n  else\n  {\n    result = ToolDynamixel::writeProfileValue(get_arg_[0], std::atoi(get_arg_[1].c_str()));\n    if (result == false)\n      return;\n  }\n\n  result = ToolDynamixel::setSDKHandler();\n  if (result == false)\n    return;\n}\n\nuint8_t ToolDynamixel::getId()\n{\n  return dynamixel_.id.at(0);\n}\n\nvoid ToolDynamixel::enable()\n{\n  const char* log = NULL;\n  bool result = false;\n  \n  result = dynamixel_workbench_->torqueOn(dynamixel_.id.at(0), &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n  enabled_state_ = true;\n}\n\nvoid ToolDynamixel::disable()\n{\n  const char* log = NULL;\n  bool result = false;\n  \n  result = dynamixel_workbench_->torqueOff(dynamixel_.id.at(0), &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n  enabled_state_ = false;\n}\n\nbool ToolDynamixel::sendToolActuatorValue(robotis_manipulator::ActuatorValue value)\n{\n  return ToolDynamixel::writeGoalPosition(value.position);\n}\n\nrobotis_manipulator::ActuatorValue ToolDynamixel::receiveToolActuatorValue()\n{\n  robotis_manipulator::ActuatorValue result;\n  result.position = ToolDynamixel::receiveDynamixelValue();\n  result.velocity = 0.0;\n  result.acceleration = 0.0;\n  result.effort = 0.0;\n  return result;\n}\n\n\n/*****************************************************************************\n** Functions called in Tool Dynamixel Profile Control Functions\n*****************************************************************************/\nbool ToolDynamixel::initialize(uint8_t actuator_id, STRING dxl_device_name, STRING dxl_baud_rate)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  STRING return_delay_time_st = \"Return_Delay_Time\";\n  const char * return_delay_time_char = return_delay_time_st.c_str();\n\n  dynamixel_.id.push_back(actuator_id);\n  dynamixel_.num = 1;\n\n  dynamixel_workbench_ = new DynamixelWorkbench;\n\n  result = dynamixel_workbench_->init(dxl_device_name.c_str(), std::atoi(dxl_baud_rate.c_str()), &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  uint16_t get_model_number;\n  result = dynamixel_workbench_->ping(dynamixel_.id.at(0), &get_model_number, &log);\n  if (result == false)\n  {\n    log::error(log);\n    log::error(\"Please check your Dynamixel ID\");\n  }\n  else\n  {\n    char str[100];\n    sprintf(str, \"Tool Dynamixel ID : %d, Model Name :\", dynamixel_.id.at(0));\n    strcat(str, dynamixel_workbench_->getModelName(dynamixel_.id.at(0)));\n    log::println(str);\n\n    result = dynamixel_workbench_->setVelocityBasedProfile(dynamixel_.id.at(0), &log);\n    if(result == false)\n    {\n      log::error(log);\n      log::error(\"Please check your Dynamixel firmware version (v38~)\");\n    }\n\n    result = dynamixel_workbench_->writeRegister(dynamixel_.id.at(0), return_delay_time_char, 0, &log);\n    if (result == false)\n    {\n      log::error(log);\n      log::error(\"Please check your Dynamixel firmware version\");\n    }\n  }\n\n  return true;\n}\n\nbool ToolDynamixel::setOperatingMode(STRING dynamixel_mode)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const uint32_t velocity = 0;\n  const uint32_t acceleration = 0;\n  const uint32_t current = 200;\n\n  if (dynamixel_mode == \"position_mode\")\n  {\n    result = dynamixel_workbench_->jointMode(dynamixel_.id.at(0), velocity, acceleration, &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  else if (dynamixel_mode == \"current_based_position_mode\")\n  {\n    result = dynamixel_workbench_->currentBasedPositionMode(dynamixel_.id.at(0), current, &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n  else\n  {\n    result = dynamixel_workbench_->jointMode(dynamixel_.id.at(0), velocity, acceleration, &log);\n    if (result == false)\n    {\n      log::error(log);\n    }\n  }\n\n  return true;\n}\n\nbool ToolDynamixel::writeProfileValue(STRING profile_mode, uint32_t value)\n{\n  const char* log = NULL;\n  bool result = false;\n\n  const char * char_profile_mode = profile_mode.c_str();\n\n  result = dynamixel_workbench_->writeRegister(dynamixel_.id.at(0), char_profile_mode, value, &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\nbool ToolDynamixel::setSDKHandler()\n{\n  bool result = false;\n  const char* log = NULL;\n\n  result = dynamixel_workbench_->addSyncWriteHandler(dynamixel_.id.at(0), \"Goal_Position\", &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->addSyncReadHandler(dynamixel_.id.at(0),\n                                                    \"Present_Position\", \n                                                    &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\nbool ToolDynamixel::writeGoalPosition(double radian)\n{\n  bool result = false;\n  const char* log = NULL;\n\n  int32_t goal_position = 0;\n\n  goal_position = dynamixel_workbench_->convertRadian2Value(dynamixel_.id.at(0), radian);\n\n  result = dynamixel_workbench_->syncWrite(SYNC_WRITE_HANDLER, &goal_position, &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  return true;\n}\n\ndouble ToolDynamixel::receiveDynamixelValue()\n{\n  bool result = false;\n  const char* log = NULL;\n\n  int32_t get_value = 0;\n  uint8_t id_array[1] = {dynamixel_.id.at(0)};\n\n  result = dynamixel_workbench_->syncRead(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT, \n                                          id_array,\n                                          (uint8_t)1,\n                                          &log);\n  if (result == false)\n  {\n    log::error(log);\n  }\n\n  result = dynamixel_workbench_->getSyncReadData(SYNC_READ_HANDLER_FOR_PRESENT_POSITION_VELOCITY_CURRENT, \n                                            id_array,\n                                            (uint8_t)1,\n                                            &get_value, \n                                            &log);\n  if (result == false)\n  {\n    log::error(log);\n  } \n\n  return dynamixel_workbench_->convertValue2Radian(dynamixel_.id.at(0), get_value);\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/stewart_libs/src/stewart_kinematics.cpp",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include \"../include/stewart_libs/stewart_kinematics.h\"\n\nusing namespace robotis_manipulator;\nusing namespace stewart_kinematics;\n\n/*****************************************************************************\n** Kinematics Solver \n*****************************************************************************/\nvoid SolverUsingGeometry::setOption(const void *arg) {}\n\nEigen::MatrixXd SolverUsingGeometry::jacobian(Manipulator *manipulator, Name tool_name) \n{\n  return Eigen::MatrixXd::Identity(6, manipulator->getDOF());\n}\n\nvoid SolverUsingGeometry::solveForwardKinematics(Manipulator *manipulator) {}\n\nbool SolverUsingGeometry::solveInverseKinematics(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue> *goal_joint_value)\n{\n  return inverseKinematicsSolverUsingGeometry(manipulator, tool_name, target_pose, goal_joint_value);\n}\n\n/*****************************************************************************\n** Private\n*****************************************************************************/\nbool SolverUsingGeometry::inverseKinematicsSolverUsingGeometry(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue> *goal_joint_value)\n{\n  std::vector<JointValue> target_angle_vector;\n\n  double temp_angle[6];\n  double temp_angle2[6];\n  JointValue target_angle[21];\n  double link[2] = {0.026, 0.1227};\n  double start_x[6], start_y[6], start_z[6],\n         temp_x[6], temp_y[6], temp_z[6],\n         target_x[6], target_y[6], target_z[6],\n         diff_x[6], diff_y[6], diff_z[6];\n  double temp[6], temp2[6];\n  double target_pose_length[6];\n  Matrix3d goal_orientation;\n  double elbow_x[6], elbow_y[6], elbow_z[6],\n         temp_elbow_x[6], temp_elbow_y[6], temp_elbow_z[6],\n         temp_target_x[6], temp_target_y[6], temp_target_z[6],\n         diff_x2[6], diff_y2[6], diff_z2[6],\n         diff_x3[6], diff_y3[6], diff_z3[6],\n         temp_target_angle[6], temp_target_angle2[6],\n         temp_diffx3[6], temp_diffy3[6], temp_diffz3[6],\n         temp_target_angle3[6], temp_target_angle4[6];\n\n  // Start pose for each set of two joints\n  for (int i=0; i<6; i++){\n    start_x[i] = cos(PI*2.0/3.0*(i/2) - pow(-1,i%2)*0.436)*(-0.0774);  \n    start_y[i] = sin(PI*2.0/3.0*(i/2) - pow(-1,i%2)*0.436)*(-0.0774);  \n    start_z[i] = -0.1057;\n  }  \n\n  // Goal pose for each set of two joints\n  for (int i=0; i<6; i++)\n  {\n    temp_x[i] = target_pose.kinematic.position(0) + cos(PI*2.0/3.0*(i/2) - pow(-1,i%2)*0.911)*(-0.07825);\n    temp_y[i] = target_pose.kinematic.position(1) + sin(PI*2.0/3.0*(i/2) - pow(-1,i%2)*0.911)*(-0.07825);\n    temp_z[i] = target_pose.kinematic.position(2);\n  }\n\n  // Goal Pose for each set of two joints after tool rotation\n  goal_orientation = target_pose.kinematic.orientation;\n  if (goal_orientation(0,0) && goal_orientation(0,1) && goal_orientation(0,2)\n   && goal_orientation(1,0) && goal_orientation(1,1) && goal_orientation(1,2)\n   && goal_orientation(2,0) && goal_orientation(2,1) && goal_orientation(2,2))\n  {\n    goal_orientation(0,0) = 1;\n    goal_orientation(1,1) = 1;\n    goal_orientation(2,2) = 1;\n  }\n  for (int i=0; i<6; i++)\n  {\n    target_x[i] = goal_orientation(0,0)*temp_x[i] + goal_orientation(0,1)*temp_y[i] + goal_orientation(0,2)*temp_z[i];\n    target_y[i] = goal_orientation(1,0)*temp_x[i] + goal_orientation(1,1)*temp_y[i] + goal_orientation(1,2)*temp_z[i];\n    target_z[i] = goal_orientation(2,0)*temp_x[i] + goal_orientation(2,1)*temp_y[i] + goal_orientation(2,2)*temp_z[i];\n  }\n\n  // Pose difference for each set of two joints\n  for (int i=0; i<6; i++)\n  {\n    diff_x[i] = target_x[i] - start_x[i];\n    diff_y[i] = target_y[i] - start_y[i];\n    diff_z[i] = target_z[i] - start_z[i];\n  }\n\n  for (int i=0; i<6; i++)\n  {\n    temp[i] = -diff_x[i]*sin(PI*2.0/3.0*(i/2) - pow(-1,i%2)*0.436)+diff_y[i]*cos(PI*2.0/3.0*(i/2) - pow(-1,i%2)*0.436);  \n    temp2[i] = sqrt(temp[i]*temp[i] + diff_z[i]*diff_z[i]);\n\n    temp_angle[i] = asin((link[1]*link[1] - link[0]*link[0] - diff_x[i]*diff_x[i] - diff_y[i]*diff_y[i] - diff_z[i]*diff_z[i])\n                    / (2.0*link[0]*temp2[i]));\n    temp_angle2[i] = pow(-1,i%2)*asin(temp[i] / temp2[i]);\n\n    target_angle[i].position = -temp_angle[i] + temp_angle2[i];  \n  }\n  target_angle[1].position = -target_angle[1].position;  \n  target_angle[3].position = -target_angle[3].position; \n  target_angle[5].position = -target_angle[5].position;\n\n  target_angle_vector.push_back(target_angle[0]);\n  target_angle_vector.push_back(target_angle[1]);\n  target_angle_vector.push_back(target_angle[2]);\n  target_angle_vector.push_back(target_angle[3]);\n  target_angle_vector.push_back(target_angle[4]);\n  target_angle_vector.push_back(target_angle[5]);\n\n  // Elbow pose\n  for (int i=0; i<6; i++)\n  {\n    // Adjust motor rotation direction\n    target_angle[i].position = -target_angle[i].position;  \n\n    elbow_x[i] = start_x[i] - sin(PI*2.0/3.0*(i/2) - pow(-1,i%2)*0.436)*link[0]*(-pow(-1,i%2))*cos(target_angle[i].position);\n    elbow_y[i] = start_y[i] + cos(PI*2.0/3.0*(i/2) - pow(-1,i%2)*0.436)*link[0]*(-pow(-1,i%2))*cos(target_angle[i].position);\n    elbow_z[i] = start_z[i] + link[0]*(-pow(-1,i%2))*sin(target_angle[i].position);\n  \n    temp_elbow_x[i] = cos(-(PI*2.0/3.0*(i/2) - pow(-1,i%2)*0.436))*elbow_x[i] - sin(-(PI*2.0/3.0*(i/2) - pow(-1,i%2)*0.436))*elbow_y[i];\n    temp_elbow_y[i] = sin(-(PI*2.0/3.0*(i/2) - pow(-1,i%2)*0.436))*elbow_x[i] + cos(-(PI*2.0/3.0*(i/2) - pow(-1,i%2)*0.436))*elbow_y[i];\n    temp_elbow_z[i] = elbow_z[i]; \n    temp_target_x[i] = cos(-(PI*2.0/3.0*(i/2) - pow(-1,i%2)*0.436))*target_x[i] - sin(-(PI*2.0/3.0*(i/2) - pow(-1,i%2)*0.436))*target_y[i];\n    temp_target_y[i] = sin(-(PI*2.0/3.0*(i/2) - pow(-1,i%2)*0.436))*target_x[i] + cos(-(PI*2.0/3.0*(i/2) - pow(-1,i%2)*0.436))*target_y[i];\n    temp_target_z[i] = target_z[i];\n  }\n  \n  for (int i=0; i<6; i++)\n  {\n    diff_x2[i] = temp_target_x[i] - temp_elbow_x[i];\n    diff_y2[i] = temp_target_y[i] - temp_elbow_y[i];\n    diff_z2[i] = temp_target_z[i] - temp_elbow_z[i];\n\n    target_angle[2*i+7].position = asin(diff_x2[i] / (pow(-1,i%2)*link[1]));\n    target_angle[2*i+6].position = +target_angle[i].position + pow(-1,i%2)*PI + asin(diff_z2[i]/(-link[1]*cos(target_angle[2*i+7].position)*pow(-1,i%2)));\n\n    // Set initial value to 0\n    target_angle[2*i+6].position = target_angle[2*i+6].position - pow(-1,i%2)*2.100;\n    target_angle[2*i+7].position = target_angle[2*i+7].position - pow(-1,i%2)*0.064;\n\n    target_angle_vector.push_back(target_angle[2*i+6]);\n    target_angle_vector.push_back(target_angle[2*i+7]);\n  }\n\n  target_angle[18].position = target_pose.kinematic.position(0);\n  target_angle[19].position = target_pose.kinematic.position(1);\n  target_angle[20].position = target_pose.kinematic.position(2);\n  target_angle_vector.push_back(target_angle[18]);\n  target_angle_vector.push_back(target_angle[19]);\n  target_angle_vector.push_back(target_angle[20]);\n\n  *goal_joint_value = target_angle_vector;\n  manipulator->setAllJointValue(target_angle_vector);\n\n  return true;\n}\n\n\n\n\n\n\n\n  // for (int i=0; i<6; i++)\n  // {\n  //   diff_x3[i] = temp_elbow_x[i] - (-0.0774);\n  //   diff_y3[i] = temp_elbow_y[i] - 0;\n  //   diff_z3[i] = temp_elbow_z[i] - (-0.1057);\n  // }\n\n  // for (int i=0; i<6; i++)\n  // {\n  //   temp_target_angle[i] = acos(diff_z2[i] / sqrt(diff_y3[i]*diff_y3[i] + diff_z3[i]*diff_z3[i]) * link[0] / link[1]);\n  //   temp_target_angle2[i] = acos(diff_z3[i] / sqrt(diff_y3[i]*diff_y3[i] + diff_z3[i]*diff_z3[i]));\n\n  //   if (i%2 == 0) \n  //   {\n  //     target_angle[2*i+6].position = -(temp_target_angle[i] + temp_target_angle2[i]);\n  //   } \n  //   else \n  //   {\n  //     target_angle[2*i+6].position = (temp_target_angle[i] + temp_target_angle2[i]);\n  //   }\n  // }\n\n  // for (int i=0; i<6; i++)\n  // {\n  //   temp_diffx3[i] = diff_x3[i];\n  //   temp_diffy3[i] = cos(target_angle[2*i+6].position)*diff_y3[i] - sin(target_angle[2*i+6].position)*diff_z3[i];\n  //   temp_diffz3[i] = sin(target_angle[2*i+6].position)*diff_y3[i] + cos(target_angle[2*i+6].position)*diff_z3[i];\n  // }\n\n  // for (int i=0; i<6; i++){\n  //   temp_target_angle3[i] = acos(diff_x2[i] / sqrt(temp_diffx3[i]*temp_diffx3[i] + temp_diffy3[i]*temp_diffy3[i]) * link[0] / link[1]);\n  //   temp_target_angle4[i] = acos(temp_diffx3[i] / sqrt(temp_diffx3[i]*temp_diffx3[i] + temp_diffy3[i]*temp_diffy3[i]));\n  //   target_angle[2*i+7].position = temp_target_angle3[i] - temp_target_angle4[i];\n  // }\n\n  // for (int i=0; i<6; i++)\n  // {\n  //   // target_angle[2*i+6].position = 0;\n  //   // target_angle[2*i+7].position = 0;\n  //   // target_angle[2*i+6].position = target_angle[2*i+6].position - 2.103914;\n  //   // target_angle[2*i+7].position = target_angle[2*i+7].position*75/125.8 + 0.075;\n  //   target_angle_vector.push_back(target_angle[2*i+6]);\n  //   target_angle_vector.push_back(target_angle[2*i+7]);\n  // }\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/OpenManipulator/src/stewart_libs.h",
    "content": "#include \"stewart_libs/include/stewart_libs/stewart.h\""
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RC100/RC100.cpp",
    "content": "/*******************************************************************************\r\n* Copyright (c) 2016, ROBOTIS CO., LTD.\r\n* All rights reserved.\r\n*\r\n* Redistribution and use in source and binary forms, with or without\r\n* modification, are permitted provided that the following conditions are met:\r\n*\r\n* * Redistributions of source code must retain the above copyright notice, this\r\n*   list of conditions and the following disclaimer.\r\n*\r\n* * Redistributions in binary form must reproduce the above copyright notice,\r\n*   this list of conditions and the following disclaimer in the documentation\r\n*   and/or other materials provided with the distribution.\r\n*\r\n* * Neither the name of ROBOTIS nor the names of its\r\n*   contributors may be used to endorse or promote products derived from\r\n*   this software without specific prior written permission.\r\n*\r\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n*******************************************************************************/\r\n\r\n/* Author: Taehoon Lim (Darby), HanCheol Cho, Ashe Kim */\r\n\r\n#include \"RC100.h\"\r\n\r\nRC100::RC100()\r\n{\r\n}\r\n\r\nRC100::~RC100()\r\n{\r\n}\r\n\r\nvoid RC100::begin(int num)\r\n{\r\n  if(num == 1)\r\n  {\r\n    Serial2.begin(57600);\r\n    number = num;\r\n  }\r\n  else if(num == 2)\r\n  {\r\n    Serial4.begin(57600);\r\n    number = num;\r\n  }\r\n  else\r\n  {\r\n    Serial2.begin(57600);\r\n    number = 1;\r\n  }\r\n  rc100_rx.state = 0;\r\n  rc100_rx.index = 0;\r\n  rc100_rx.received = false;\r\n}\r\n\r\nint RC100::available(void)\r\n{\r\n  if (number == 1)\r\n  {\r\n    if(Serial2.available())\r\n    {\r\n      return rc100Update(Serial2.read());\r\n    }\r\n  }\r\n  else if (number == 2)\r\n  {\r\n    if(Serial4.available())\r\n    {\r\n      return rc100Update(Serial4.read());\r\n    }\r\n  }\r\n\r\n  return false;\r\n}\r\n\r\nuint16_t RC100::readData(void)\r\n{\r\n  return rc100_rx.data;\r\n}\r\n\r\nbool RC100::rc100Update(uint8_t data)\r\n{\r\n  bool ret = false;\r\n  static uint8_t save_data;\r\n  static uint8_t inv_data;\r\n  static uint32_t time_t;\r\n\r\n  inv_data = ~data;\r\n\r\n  if (millis()-time_t > 100)\r\n  {\r\n    rc100_rx.state = 0;\r\n  }\r\n\r\n  switch(rc100_rx.state)\r\n  {\r\n    case 0:\r\n      if (data == 0xFF)\r\n      {\r\n        rc100_rx.state = 1;\r\n        time_t = millis();\r\n      }\r\n      break;\r\n\r\n    case 1:\r\n      if (data == 0x55)\r\n      {\r\n        rc100_rx.state    = 2;\r\n        rc100_rx.received = false;\r\n        rc100_rx.data     = 0;\r\n      }\r\n      else\r\n      {\r\n        rc100_rx.state = 0;\r\n      }\r\n      break;\r\n\r\n    case 2:\r\n      rc100_rx.data  = data;\r\n      save_data      = data;\r\n      rc100_rx.state = 3;\r\n      break;\r\n\r\n    case 3:\r\n      if (save_data == inv_data)\r\n      {\r\n        rc100_rx.state = 4;\r\n      }\r\n      else\r\n      {\r\n        rc100_rx.state = 0;\r\n      }\r\n      break;\r\n\r\n    case 4:\r\n      rc100_rx.data |= data<<8;\r\n      save_data      = data;\r\n      rc100_rx.state = 5;\r\n      break;\r\n\r\n    case 5:\r\n      if (save_data == inv_data)\r\n      {\r\n        rc100_rx.received = true;\r\n        ret = true;\r\n      }\r\n      rc100_rx.state = 0;\r\n      break;\r\n\r\n    default:\r\n      rc100_rx.state = 0;\r\n      break;\r\n  }\r\n\r\n  return ret;\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RC100/RC100.h",
    "content": "/*******************************************************************************\r\n* Copyright (c) 2016, ROBOTIS CO., LTD.\r\n* All rights reserved.\r\n*\r\n* Redistribution and use in source and binary forms, with or without\r\n* modification, are permitted provided that the following conditions are met:\r\n*\r\n* * Redistributions of source code must retain the above copyright notice, this\r\n*   list of conditions and the following disclaimer.\r\n*\r\n* * Redistributions in binary form must reproduce the above copyright notice,\r\n*   this list of conditions and the following disclaimer in the documentation\r\n*   and/or other materials provided with the distribution.\r\n*\r\n* * Neither the name of ROBOTIS nor the names of its\r\n*   contributors may be used to endorse or promote products derived from\r\n*   this software without specific prior written permission.\r\n*\r\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n*******************************************************************************/\r\n\r\n/* Author: Taehoon Lim (Darby), HanCheol Cho, Ashe Kim */\r\n\r\n#ifndef RC100_H_\r\n#define RC100_H_\r\n\r\n#include \"variant.h\"\r\n\r\n////////// define RC-100 button key value ////////////////\r\n#define RC100_BTN_U\t\t(1)\r\n#define RC100_BTN_D\t\t(2)\r\n#define RC100_BTN_L\t\t(4)\r\n#define RC100_BTN_R\t\t(8)\r\n#define RC100_BTN_1\t\t(16)\r\n#define RC100_BTN_2\t\t(32)\r\n#define RC100_BTN_3\t\t(64)\r\n#define RC100_BTN_4\t\t(128)\r\n#define RC100_BTN_5\t\t(256)\r\n#define RC100_BTN_6\t\t(512)\r\n\r\n#define PACKET_LENGTH \t\t6\r\n\r\nclass RC100 {\r\n public:\r\n   RC100();\r\n   virtual ~RC100();\r\n\r\n   void begin(int num);\r\n   int available(void);\r\n   uint16_t readData(void);\r\n\r\n private:\r\n\r\n   int8_t number;\r\n   typedef struct\r\n   {\r\n     uint8_t  state;\r\n     uint8_t  index;\r\n     bool     received;\r\n     uint16_t data;\r\n   } rc100_t;\r\n     rc100_t rc100_rx;\r\n\r\n  bool rc100Update(uint8_t data);\r\n  bool rc100Receive(unsigned char *pPacket, int numPacket);\r\n};\r\n#endif /* RC100_H_ */\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/ROS/OpenCR_ROS.cpp",
    "content": ""
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/ROS/OpenCR_ROS.h",
    "content": ""
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/ROS/examples/01. Basics/a_LED/a_LED.ino",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#include <ros.h>\n#include <std_msgs/String.h>\n#include <std_msgs/Byte.h>\n\n\nint led_pin_user[4] = { BDPIN_LED_USER_1, BDPIN_LED_USER_2, BDPIN_LED_USER_3, BDPIN_LED_USER_4 };\n\nros::NodeHandle  nh;\n\nvoid messageCb( const std_msgs::Byte& led_msg) {\n  int i;\n\n  for (i=0; i<4; i++)\n  {\n    if (led_msg.data & (1<<i))\n    {\n      digitalWrite(led_pin_user[i], LOW);\n    }\n    else\n    {\n      digitalWrite(led_pin_user[i], HIGH);\n    }\n  }\n}\n\nros::Subscriber<std_msgs::Byte> sub(\"led_out\", messageCb );\n\n\nvoid setup() {\n  pinMode(led_pin_user[0], OUTPUT);\n  pinMode(led_pin_user[1], OUTPUT);\n  pinMode(led_pin_user[2], OUTPUT);\n  pinMode(led_pin_user[3], OUTPUT);\n\n  nh.initNode();\n  nh.subscribe(sub);\n}\n\nvoid loop() {\n  nh.spinOnce();\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/ROS/examples/01. Basics/b_Button/b_Button.ino",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#include <ros.h>\n#include <std_msgs/Byte.h>\n\n\nros::NodeHandle nh;\n\nstd_msgs::Byte button_msg;\nros::Publisher pub_button(\"button\", &button_msg);\n\n\n\nvoid setup()\n{\n  nh.initNode();\n  nh.advertise(pub_button);\n\n  pinMode(BDPIN_PUSH_SW_1, INPUT);\n  pinMode(BDPIN_PUSH_SW_2, INPUT);\n}\n\nvoid loop()\n{\n  uint8_t reading = 0;\n  static uint32_t pre_time;\n\n\n  if (digitalRead(BDPIN_PUSH_SW_1) == HIGH)\n  {\n    reading |= 0x01;\n  }\n  if (digitalRead(BDPIN_PUSH_SW_2) == HIGH)\n  {\n    reading |= 0x02;\n  }\n\n  if (millis()-pre_time >= 50)\n  {\n    button_msg.data = reading;\n    pub_button.publish(&button_msg);\n    pre_time = millis();\n  }\n\n  nh.spinOnce();\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/ROS/examples/01. Basics/c_Voltage/c_Voltage.ino",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#include <ros.h>\n#include <std_msgs/Float32.h>\n\n\nros::NodeHandle nh;\n\nstd_msgs::Float32 voltage_msg;\nros::Publisher pub_voltage(\"voltage\", &voltage_msg);\n\n\n\nvoid setup()\n{\n  nh.initNode();\n  nh.advertise(pub_voltage);\n}\n\nvoid loop()\n{\n  static uint32_t pre_time;\n\n\n  if (millis()-pre_time >= 50)\n  {\n    voltage_msg.data = getPowerInVoltage();\n    pub_voltage.publish(&voltage_msg);\n    pre_time = millis();\n  }\n\n  nh.spinOnce();\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/ROS/examples/01. Basics/d_IMU/d_IMU.ino",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#include <ros.h>\n#include <sensor_msgs/Imu.h>\n#include <tf/tf.h>\n#include <tf/transform_broadcaster.h>\n\n#include <IMU.h>\n\n\nros::NodeHandle nh;\n\nsensor_msgs::Imu imu_msg;\nros::Publisher imu_pub(\"imu\", &imu_msg);\n\n\ngeometry_msgs::TransformStamped tfs_msg;\ntf::TransformBroadcaster tfbroadcaster;\n\ncIMU imu;\n\n\nvoid setup()\n{\n  nh.initNode();\n  nh.advertise(imu_pub);\n  tfbroadcaster.init(nh);\n\n  imu.begin();\n}\n\nvoid loop()\n{\n  static uint32_t pre_time;\n\n  imu.update();\n\n  if (millis()-pre_time >= 50)\n  {\n    pre_time = millis();\n\n    imu_msg.header.stamp    = nh.now();\n    imu_msg.header.frame_id = \"imu_link\";\n\n    imu_msg.angular_velocity.x = imu.gyroData[0];\n    imu_msg.angular_velocity.y = imu.gyroData[1];\n    imu_msg.angular_velocity.z = imu.gyroData[2];\n    imu_msg.angular_velocity_covariance[0] = 0.02;\n    imu_msg.angular_velocity_covariance[1] = 0;\n    imu_msg.angular_velocity_covariance[2] = 0;\n    imu_msg.angular_velocity_covariance[3] = 0;\n    imu_msg.angular_velocity_covariance[4] = 0.02;\n    imu_msg.angular_velocity_covariance[5] = 0;\n    imu_msg.angular_velocity_covariance[6] = 0;\n    imu_msg.angular_velocity_covariance[7] = 0;\n    imu_msg.angular_velocity_covariance[8] = 0.02;\n\n    imu_msg.linear_acceleration.x = imu.accData[0];\n    imu_msg.linear_acceleration.y = imu.accData[1];\n    imu_msg.linear_acceleration.z = imu.accData[2];\n    imu_msg.linear_acceleration_covariance[0] = 0.04;\n    imu_msg.linear_acceleration_covariance[1] = 0;\n    imu_msg.linear_acceleration_covariance[2] = 0;\n    imu_msg.linear_acceleration_covariance[3] = 0;\n    imu_msg.linear_acceleration_covariance[4] = 0.04;\n    imu_msg.linear_acceleration_covariance[5] = 0;\n    imu_msg.linear_acceleration_covariance[6] = 0;\n    imu_msg.linear_acceleration_covariance[7] = 0;\n    imu_msg.linear_acceleration_covariance[8] = 0.04;\n\n    imu_msg.orientation.w = imu.quat[0];\n    imu_msg.orientation.x = imu.quat[1];\n    imu_msg.orientation.y = imu.quat[2];\n    imu_msg.orientation.z = imu.quat[3];\n\n    imu_msg.orientation_covariance[0] = 0.0025;\n    imu_msg.orientation_covariance[1] = 0;\n    imu_msg.orientation_covariance[2] = 0;\n    imu_msg.orientation_covariance[3] = 0;\n    imu_msg.orientation_covariance[4] = 0.0025;\n    imu_msg.orientation_covariance[5] = 0;\n    imu_msg.orientation_covariance[6] = 0;\n    imu_msg.orientation_covariance[7] = 0;\n    imu_msg.orientation_covariance[8] = 0.0025;\n\n    imu_pub.publish(&imu_msg);\n\n    tfs_msg.header.stamp    = nh.now();\n    tfs_msg.header.frame_id = \"base_link\";\n    tfs_msg.child_frame_id  = \"imu_link\";\n    tfs_msg.transform.rotation.w = imu.quat[0];\n    tfs_msg.transform.rotation.x = imu.quat[1];\n    tfs_msg.transform.rotation.y = imu.quat[2];\n    tfs_msg.transform.rotation.z = imu.quat[3];\n\n    tfs_msg.transform.translation.x = 0.0;\n    tfs_msg.transform.translation.y = 0.0;\n    tfs_msg.transform.translation.z = 0.0;\n\n    tfbroadcaster.sendTransform(tfs_msg);\n  }\n\n  nh.spinOnce();\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/ROS/examples/02. Sensors/a_bumper/a_bumper.ino",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, Gilbert, HanCheol Cho */\n\n#include <ros.h>\n#include <std_msgs/Byte.h>\n#include <OLLO.h>\n\nOLLO touchOLLO;\nros::NodeHandle nh;\n\nstd_msgs::Byte bumper_msg;\nros::Publisher pub_bumper(\"bumper\", &bumper_msg);\n\n\n\nvoid setup()\n{\n  nh.initNode();\n  nh.advertise(pub_bumper);\n  \n  touchOLLO.begin(3,TOUCH_SENSOR);//OLLO Touch Module must be connected at port 3.\n  touchOLLO.begin(4,TOUCH_SENSOR);//OLLO Touch Module must be connected at port 4.\n}\n\nvoid loop()\n{\n  uint8_t reading = 0;\n  static uint32_t pre_time;\n \n  if (touchOLLO.read(3, TOUCH_SENSOR) == HIGH)\n  {\n    reading |= 0x02; // front side touch_sensor\n  }\n  \n  if (touchOLLO.read(4, TOUCH_SENSOR) == HIGH)\n  {\n    reading |= 0x01; // back side touch_sensor\n  }\n  \n  if (millis()-pre_time >= 50)\n  {\n    bumper_msg.data = reading;\n    pub_bumper.publish(&bumper_msg);\n    pre_time = millis();\n  }\n  \n  nh.spinOnce();\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/ROS/examples/02. Sensors/b_cliff/b_cliff.ino",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho, Gilbert */\n\n#include <ros.h>\n#include <std_msgs/UInt16.h>\n#include <OLLO.h>\n\nOLLO IROLLO;\nros::NodeHandle nh;\nstd_msgs::UInt16 cliff_msg;\nros::Publisher pub_cliff(\"cliff\", &cliff_msg);\n\nvoid setup()\n{\n  nh.initNode();\n  nh.advertise(pub_cliff);\n\n  Serial.begin(9600);\n  \n  IROLLO.begin(2, IR_SENSOR);//IR Module must be connected at port 1.\n}\n\nvoid loop()\n{\n  cliff_msg.data = IROLLO.read(2, IR_SENSOR);\n  pub_cliff.publish(&cliff_msg);\n    \n  Serial.println(cliff_msg.data);\n  delay(10);\n  nh.spinOnce();\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/ROS/examples/02. Sensors/c_Ultrasonic/c_Ultrasonic.ino",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho, Gilbert */\n\nconst int trigPin = BDPIN_GPIO_1;\nconst int echoPin = BDPIN_GPIO_2;\n\nfloat duration, distance;\n\nvoid setup() \n{\n  Serial.begin(9600);\n\n  pinMode(trigPin, OUTPUT);\n  pinMode(echoPin, INPUT);\n}\n\nvoid loop() \n{  \n  digitalWrite(trigPin, HIGH);\n  delay(10);\n  digitalWrite(trigPin, LOW);\n \n  duration = pulseIn(echoPin, HIGH);\n  distance = ((float)(340 * duration) / 10000) / 2;\n\n  Serial.print(\"duration: \");\n  Serial.print(duration);\n\n  Serial.print(\" distance: \");\n  Serial.println(distance);\n\n  delay(500);\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/ROS/examples/02. Sensors/d_Illumination/d_Illumination.ino",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho, Gilbert */\n\n#include <ros.h>\n#include <std_msgs/Float32.h>\n\nros::NodeHandle nh;\nstd_msgs::Float32 illumination_msg;\nros::Publisher pub_illumination(\"illumination\", &illumination_msg);\n\nvoid setup() \n{\n  nh.initNode();\n  nh.advertise(pub_illumination);\n  \n  Serial.begin(9600);\n}\n \nvoid loop()\n{\n  float reading = 0;\n  static uint32_t pre_time;\n\n  reading = analogRead(A1);\n  \n  if (millis()-pre_time >= 50)\n  {\n    illumination_msg.data = reading;\n    pub_illumination.publish(&illumination_msg);\n    pre_time = millis();\n    Serial.println(illumination_msg.data);\n  }\n  nh.spinOnce();\n}\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RTOS/library.properties",
    "content": "name=FreeRTOS\nversion=1.0.0\nauthor=\nmaintainer=\nsentence=Library for FreeRTOS\nparagraph=Library for FreeRTOS\ncategory=Display\nurl=https://github.com/adafruit/Adafruit_ILI9341\narchitectures=OpenCR\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RTOS/src/FreeRTOS.h",
    "content": "/*\r\n    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r\n    All rights reserved\r\n\r\n    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r\n\r\n    This file is part of the FreeRTOS distribution.\r\n\r\n    FreeRTOS is free software; you can redistribute it and/or modify it under\r\n    the terms of the GNU General Public License (version 2) as published by the\r\n    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r\n\r\n    ***************************************************************************\r\n    >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r\n    >>!   distribute a combined work that includes FreeRTOS without being   !<<\r\n    >>!   obliged to provide the source code for proprietary components     !<<\r\n    >>!   outside of the FreeRTOS kernel.                                   !<<\r\n    ***************************************************************************\r\n\r\n    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r\n    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r\n    FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r\n    link: http://www.freertos.org/a00114.html\r\n\r\n    ***************************************************************************\r\n     *                                                                       *\r\n     *    FreeRTOS provides completely free yet professionally developed,    *\r\n     *    robust, strictly quality controlled, supported, and cross          *\r\n     *    platform software that is more than just the market leader, it     *\r\n     *    is the industry's de facto standard.                               *\r\n     *                                                                       *\r\n     *    Help yourself get started quickly while simultaneously helping     *\r\n     *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r\n     *    tutorial book, reference manual, or both:                          *\r\n     *    http://www.FreeRTOS.org/Documentation                              *\r\n     *                                                                       *\r\n    ***************************************************************************\r\n\r\n    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r\n    the FAQ page \"My application does not run, what could be wrong?\".  Have you\r\n    defined configASSERT()?\r\n\r\n    http://www.FreeRTOS.org/support - In return for receiving this top quality\r\n    embedded software for free we request you assist our global community by\r\n    participating in the support forum.\r\n\r\n    http://www.FreeRTOS.org/training - Investing in training allows your team to\r\n    be as productive as possible as early as possible.  Now you can receive\r\n    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r\n    Ltd, and the world's leading authority on the world's leading RTOS.\r\n\r\n    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r\n    including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r\n    compatible FAT file system, and our tiny thread aware UDP/IP stack.\r\n\r\n    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r\n    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r\n\r\n    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r\n    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r\n    licenses offer ticketed support, indemnification and commercial middleware.\r\n\r\n    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r\n    engineered and independently SIL3 certified version for use in safety and\r\n    mission critical applications that require provable dependability.\r\n\r\n    1 tab == 4 spaces!\r\n*/\r\n\r\n#ifndef INC_FREERTOS_H\r\n#define INC_FREERTOS_H\r\n\r\n/*\r\n * Include the generic headers required for the FreeRTOS port being used.\r\n */\r\n#include <stddef.h>\r\n\r\n/*\r\n * If stdint.h cannot be located then:\r\n *   + If using GCC ensure the -nostdint options is *not* being used.\r\n *   + Ensure the project's include path includes the directory in which your\r\n *     compiler stores stdint.h.\r\n *   + Set any compiler options necessary for it to support C99, as technically\r\n *     stdint.h is only mandatory with C99 (FreeRTOS does not require C99 in any\r\n *     other way).\r\n *   + The FreeRTOS download includes a simple stdint.h definition that can be\r\n *     used in cases where none is provided by the compiler.  The files only\r\n *     contains the typedefs required to build FreeRTOS.  Read the instructions\r\n *     in FreeRTOS/source/stdint.readme for more information.\r\n */\r\n#include <stdint.h> /* READ COMMENT ABOVE. */\r\n\r\n#ifdef __cplusplus\r\nextern \"C\" {\r\n#endif\r\n\r\n/* Application specific configuration options. */\r\n#include \"FreeRTOSConfig.h\"\r\n\r\n/* Basic FreeRTOS definitions. */\r\n#include \"projdefs.h\"\r\n\r\n/* Definitions specific to the port being used. */\r\n#include \"portable.h\"\r\n\r\n/*\r\n * Check all the required application specific macros have been defined.\r\n * These macros are application specific and (as downloaded) are defined\r\n * within FreeRTOSConfig.h.\r\n */\r\n\r\n#ifndef configMINIMAL_STACK_SIZE\r\n\t#error Missing definition:  configMINIMAL_STACK_SIZE must be defined in FreeRTOSConfig.h.  configMINIMAL_STACK_SIZE defines the size (in words) of the stack allocated to the idle task.  Refer to the demo project provided for your port for a suitable value.\r\n#endif\r\n\r\n#ifndef configMAX_PRIORITIES\r\n\t#error Missing definition:  configMAX_PRIORITIES must be defined in FreeRTOSConfig.h.  See the Configuration section of the FreeRTOS API documentation for details.\r\n#endif\r\n\r\n#ifndef configUSE_PREEMPTION\r\n\t#error Missing definition:  configUSE_PREEMPTION must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.\r\n#endif\r\n\r\n#ifndef configUSE_IDLE_HOOK\r\n\t#error Missing definition:  configUSE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.\r\n#endif\r\n\r\n#ifndef configUSE_TICK_HOOK\r\n\t#error Missing definition:  configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.\r\n#endif\r\n\r\n#ifndef INCLUDE_vTaskPrioritySet\r\n\t#error Missing definition:  INCLUDE_vTaskPrioritySet must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.\r\n#endif\r\n\r\n#ifndef INCLUDE_uxTaskPriorityGet\r\n\t#error Missing definition:  INCLUDE_uxTaskPriorityGet must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.\r\n#endif\r\n\r\n#ifndef INCLUDE_vTaskDelete\r\n\t#error Missing definition:  INCLUDE_vTaskDelete must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.\r\n#endif\r\n\r\n#ifndef INCLUDE_vTaskSuspend\r\n\t#error Missing definition:  INCLUDE_vTaskSuspend must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.\r\n#endif\r\n\r\n#ifndef INCLUDE_vTaskDelayUntil\r\n\t#error Missing definition:  INCLUDE_vTaskDelayUntil must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.\r\n#endif\r\n\r\n#ifndef INCLUDE_vTaskDelay\r\n\t#error Missing definition:  INCLUDE_vTaskDelay must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.\r\n#endif\r\n\r\n#ifndef configUSE_16_BIT_TICKS\r\n\t#error Missing definition:  configUSE_16_BIT_TICKS must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.\r\n#endif\r\n\r\n#ifndef configMAX_PRIORITIES\r\n\t#error configMAX_PRIORITIES must be defined to be greater than or equal to 1.\r\n#endif\r\n\r\n#ifndef configUSE_CO_ROUTINES\r\n\t#define configUSE_CO_ROUTINES 0\r\n#endif\r\n\r\n#if configUSE_CO_ROUTINES != 0\r\n\t#ifndef configMAX_CO_ROUTINE_PRIORITIES\r\n\t\t#error configMAX_CO_ROUTINE_PRIORITIES must be greater than or equal to 1.\r\n\t#endif\r\n#endif\r\n\r\n#ifndef INCLUDE_xTaskGetIdleTaskHandle\r\n\t#define INCLUDE_xTaskGetIdleTaskHandle 0\r\n#endif\r\n\r\n#ifndef INCLUDE_xTimerGetTimerDaemonTaskHandle\r\n\t#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0\r\n#endif\r\n\r\n#ifndef INCLUDE_xQueueGetMutexHolder\r\n\t#define INCLUDE_xQueueGetMutexHolder 0\r\n#endif\r\n\r\n#ifndef INCLUDE_xSemaphoreGetMutexHolder\r\n\t#define INCLUDE_xSemaphoreGetMutexHolder INCLUDE_xQueueGetMutexHolder\r\n#endif\r\n\r\n#ifndef INCLUDE_pcTaskGetTaskName\r\n\t#define INCLUDE_pcTaskGetTaskName 0\r\n#endif\r\n\r\n#ifndef configUSE_APPLICATION_TASK_TAG\r\n\t#define configUSE_APPLICATION_TASK_TAG 0\r\n#endif\r\n\r\n#ifndef configNUM_THREAD_LOCAL_STORAGE_POINTERS\r\n\t#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0\r\n#endif\r\n\r\n#ifndef INCLUDE_uxTaskGetStackHighWaterMark\r\n\t#define INCLUDE_uxTaskGetStackHighWaterMark 0\r\n#endif\r\n\r\n#ifndef INCLUDE_eTaskGetState\r\n\t#define INCLUDE_eTaskGetState 0\r\n#endif\r\n\r\n#ifndef configUSE_RECURSIVE_MUTEXES\r\n\t#define configUSE_RECURSIVE_MUTEXES 0\r\n#endif\r\n\r\n#ifndef configUSE_MUTEXES\r\n\t#define configUSE_MUTEXES 0\r\n#endif\r\n\r\n#ifndef configUSE_TIMERS\r\n\t#define configUSE_TIMERS 0\r\n#endif\r\n\r\n#ifndef configUSE_COUNTING_SEMAPHORES\r\n\t#define configUSE_COUNTING_SEMAPHORES 0\r\n#endif\r\n\r\n#ifndef configUSE_ALTERNATIVE_API\r\n\t#define configUSE_ALTERNATIVE_API 0\r\n#endif\r\n\r\n#ifndef portCRITICAL_NESTING_IN_TCB\r\n\t#define portCRITICAL_NESTING_IN_TCB 0\r\n#endif\r\n\r\n#ifndef configMAX_TASK_NAME_LEN\r\n\t#define configMAX_TASK_NAME_LEN 16\r\n#endif\r\n\r\n#ifndef configIDLE_SHOULD_YIELD\r\n\t#define configIDLE_SHOULD_YIELD\t\t1\r\n#endif\r\n\r\n#if configMAX_TASK_NAME_LEN < 1\r\n\t#error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h\r\n#endif\r\n\r\n#ifndef INCLUDE_xTaskResumeFromISR\r\n\t#define INCLUDE_xTaskResumeFromISR 1\r\n#endif\r\n\r\n#ifndef INCLUDE_xEventGroupSetBitFromISR\r\n\t#define INCLUDE_xEventGroupSetBitFromISR 0\r\n#endif\r\n\r\n#ifndef INCLUDE_xTimerPendFunctionCall\r\n\t#define INCLUDE_xTimerPendFunctionCall 0\r\n#endif\r\n\r\n#ifndef configASSERT\r\n\t#define configASSERT( x )\r\n\t#define configASSERT_DEFINED 0\r\n#else\r\n\t#define configASSERT_DEFINED 1\r\n#endif\r\n\r\n/* The timers module relies on xTaskGetSchedulerState(). */\r\n#if configUSE_TIMERS == 1\r\n\r\n\t#ifndef configTIMER_TASK_PRIORITY\r\n\t\t#error If configUSE_TIMERS is set to 1 then configTIMER_TASK_PRIORITY must also be defined.\r\n\t#endif /* configTIMER_TASK_PRIORITY */\r\n\r\n\t#ifndef configTIMER_QUEUE_LENGTH\r\n\t\t#error If configUSE_TIMERS is set to 1 then configTIMER_QUEUE_LENGTH must also be defined.\r\n\t#endif /* configTIMER_QUEUE_LENGTH */\r\n\r\n\t#ifndef configTIMER_TASK_STACK_DEPTH\r\n\t\t#error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined.\r\n\t#endif /* configTIMER_TASK_STACK_DEPTH */\r\n\r\n#endif /* configUSE_TIMERS */\r\n\r\n#ifndef INCLUDE_xTaskGetSchedulerState\r\n\t#define INCLUDE_xTaskGetSchedulerState 0\r\n#endif\r\n\r\n#ifndef INCLUDE_xTaskGetCurrentTaskHandle\r\n\t#define INCLUDE_xTaskGetCurrentTaskHandle 0\r\n#endif\r\n\r\n\r\n#ifndef portSET_INTERRUPT_MASK_FROM_ISR\r\n\t#define portSET_INTERRUPT_MASK_FROM_ISR() 0\r\n#endif\r\n\r\n#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR\r\n\t#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue\r\n#endif\r\n\r\n#ifndef portCLEAN_UP_TCB\r\n\t#define portCLEAN_UP_TCB( pxTCB ) ( void ) pxTCB\r\n#endif\r\n\r\n#ifndef portPRE_TASK_DELETE_HOOK\r\n\t#define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxYieldPending )\r\n#endif\r\n\r\n#ifndef portSETUP_TCB\r\n\t#define portSETUP_TCB( pxTCB ) ( void ) pxTCB\r\n#endif\r\n\r\n#ifndef configQUEUE_REGISTRY_SIZE\r\n\t#define configQUEUE_REGISTRY_SIZE 0U\r\n#endif\r\n\r\n#if ( configQUEUE_REGISTRY_SIZE < 1 )\r\n\t#define vQueueAddToRegistry( xQueue, pcName )\r\n\t#define vQueueUnregisterQueue( xQueue )\r\n#endif\r\n\r\n#ifndef portPOINTER_SIZE_TYPE\r\n\t#define portPOINTER_SIZE_TYPE uint32_t\r\n#endif\r\n\r\n/* Remove any unused trace macros. */\r\n#ifndef traceSTART\r\n\t/* Used to perform any necessary initialisation - for example, open a file\r\n\tinto which trace is to be written. */\r\n\t#define traceSTART()\r\n#endif\r\n\r\n#ifndef traceEND\r\n\t/* Use to close a trace, for example close a file into which trace has been\r\n\twritten. */\r\n\t#define traceEND()\r\n#endif\r\n\r\n#ifndef traceTASK_SWITCHED_IN\r\n\t/* Called after a task has been selected to run.  pxCurrentTCB holds a pointer\r\n\tto the task control block of the selected task. */\r\n\t#define traceTASK_SWITCHED_IN()\r\n#endif\r\n\r\n#ifndef traceINCREASE_TICK_COUNT\r\n\t/* Called before stepping the tick count after waking from tickless idle\r\n\tsleep. */\r\n\t#define traceINCREASE_TICK_COUNT( x )\r\n#endif\r\n\r\n#ifndef traceLOW_POWER_IDLE_BEGIN\r\n\t/* Called immediately before entering tickless idle. */\r\n\t#define traceLOW_POWER_IDLE_BEGIN()\r\n#endif\r\n\r\n#ifndef\ttraceLOW_POWER_IDLE_END\r\n\t/* Called when returning to the Idle task after a tickless idle. */\r\n\t#define traceLOW_POWER_IDLE_END()\r\n#endif\r\n\r\n#ifndef traceTASK_SWITCHED_OUT\r\n\t/* Called before a task has been selected to run.  pxCurrentTCB holds a pointer\r\n\tto the task control block of the task being switched out. */\r\n\t#define traceTASK_SWITCHED_OUT()\r\n#endif\r\n\r\n#ifndef traceTASK_PRIORITY_INHERIT\r\n\t/* Called when a task attempts to take a mutex that is already held by a\r\n\tlower priority task.  pxTCBOfMutexHolder is a pointer to the TCB of the task\r\n\tthat holds the mutex.  uxInheritedPriority is the priority the mutex holder\r\n\twill inherit (the priority of the task that is attempting to obtain the\r\n\tmuted. */\r\n\t#define traceTASK_PRIORITY_INHERIT( pxTCBOfMutexHolder, uxInheritedPriority )\r\n#endif\r\n\r\n#ifndef traceTASK_PRIORITY_DISINHERIT\r\n\t/* Called when a task releases a mutex, the holding of which had resulted in\r\n\tthe task inheriting the priority of a higher priority task.\r\n\tpxTCBOfMutexHolder is a pointer to the TCB of the task that is releasing the\r\n\tmutex.  uxOriginalPriority is the task's configured (base) priority. */\r\n\t#define traceTASK_PRIORITY_DISINHERIT( pxTCBOfMutexHolder, uxOriginalPriority )\r\n#endif\r\n\r\n#ifndef traceBLOCKING_ON_QUEUE_RECEIVE\r\n\t/* Task is about to block because it cannot read from a\r\n\tqueue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore\r\n\tupon which the read was attempted.  pxCurrentTCB points to the TCB of the\r\n\ttask that attempted the read. */\r\n\t#define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue )\r\n#endif\r\n\r\n#ifndef traceBLOCKING_ON_QUEUE_SEND\r\n\t/* Task is about to block because it cannot write to a\r\n\tqueue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore\r\n\tupon which the write was attempted.  pxCurrentTCB points to the TCB of the\r\n\ttask that attempted the write. */\r\n\t#define traceBLOCKING_ON_QUEUE_SEND( pxQueue )\r\n#endif\r\n\r\n#ifndef configCHECK_FOR_STACK_OVERFLOW\r\n\t#define configCHECK_FOR_STACK_OVERFLOW 0\r\n#endif\r\n\r\n/* The following event macros are embedded in the kernel API calls. */\r\n\r\n#ifndef traceMOVED_TASK_TO_READY_STATE\r\n\t#define traceMOVED_TASK_TO_READY_STATE( pxTCB )\r\n#endif\r\n\r\n#ifndef traceQUEUE_CREATE\r\n\t#define traceQUEUE_CREATE( pxNewQueue )\r\n#endif\r\n\r\n#ifndef traceQUEUE_CREATE_FAILED\r\n\t#define traceQUEUE_CREATE_FAILED( ucQueueType )\r\n#endif\r\n\r\n#ifndef traceCREATE_MUTEX\r\n\t#define traceCREATE_MUTEX( pxNewQueue )\r\n#endif\r\n\r\n#ifndef traceCREATE_MUTEX_FAILED\r\n\t#define traceCREATE_MUTEX_FAILED()\r\n#endif\r\n\r\n#ifndef traceGIVE_MUTEX_RECURSIVE\r\n\t#define traceGIVE_MUTEX_RECURSIVE( pxMutex )\r\n#endif\r\n\r\n#ifndef traceGIVE_MUTEX_RECURSIVE_FAILED\r\n\t#define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex )\r\n#endif\r\n\r\n#ifndef traceTAKE_MUTEX_RECURSIVE\r\n\t#define traceTAKE_MUTEX_RECURSIVE( pxMutex )\r\n#endif\r\n\r\n#ifndef traceTAKE_MUTEX_RECURSIVE_FAILED\r\n\t#define traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex )\r\n#endif\r\n\r\n#ifndef traceCREATE_COUNTING_SEMAPHORE\r\n\t#define traceCREATE_COUNTING_SEMAPHORE()\r\n#endif\r\n\r\n#ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED\r\n\t#define traceCREATE_COUNTING_SEMAPHORE_FAILED()\r\n#endif\r\n\r\n#ifndef traceQUEUE_SEND\r\n\t#define traceQUEUE_SEND( pxQueue )\r\n#endif\r\n\r\n#ifndef traceQUEUE_SEND_FAILED\r\n\t#define traceQUEUE_SEND_FAILED( pxQueue )\r\n#endif\r\n\r\n#ifndef traceQUEUE_RECEIVE\r\n\t#define traceQUEUE_RECEIVE( pxQueue )\r\n#endif\r\n\r\n#ifndef traceQUEUE_PEEK\r\n\t#define traceQUEUE_PEEK( pxQueue )\r\n#endif\r\n\r\n#ifndef traceQUEUE_PEEK_FROM_ISR\r\n\t#define traceQUEUE_PEEK_FROM_ISR( pxQueue )\r\n#endif\r\n\r\n#ifndef traceQUEUE_RECEIVE_FAILED\r\n\t#define traceQUEUE_RECEIVE_FAILED( pxQueue )\r\n#endif\r\n\r\n#ifndef traceQUEUE_SEND_FROM_ISR\r\n\t#define traceQUEUE_SEND_FROM_ISR( pxQueue )\r\n#endif\r\n\r\n#ifndef traceQUEUE_SEND_FROM_ISR_FAILED\r\n\t#define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue )\r\n#endif\r\n\r\n#ifndef traceQUEUE_RECEIVE_FROM_ISR\r\n\t#define traceQUEUE_RECEIVE_FROM_ISR( pxQueue )\r\n#endif\r\n\r\n#ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED\r\n\t#define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue )\r\n#endif\r\n\r\n#ifndef traceQUEUE_PEEK_FROM_ISR_FAILED\r\n\t#define traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue )\r\n#endif\r\n\r\n#ifndef traceQUEUE_DELETE\r\n\t#define traceQUEUE_DELETE( pxQueue )\r\n#endif\r\n\r\n#ifndef traceTASK_CREATE\r\n\t#define traceTASK_CREATE( pxNewTCB )\r\n#endif\r\n\r\n#ifndef traceTASK_CREATE_FAILED\r\n\t#define traceTASK_CREATE_FAILED()\r\n#endif\r\n\r\n#ifndef traceTASK_DELETE\r\n\t#define traceTASK_DELETE( pxTaskToDelete )\r\n#endif\r\n\r\n#ifndef traceTASK_DELAY_UNTIL\r\n\t#define traceTASK_DELAY_UNTIL()\r\n#endif\r\n\r\n#ifndef traceTASK_DELAY\r\n\t#define traceTASK_DELAY()\r\n#endif\r\n\r\n#ifndef traceTASK_PRIORITY_SET\r\n\t#define traceTASK_PRIORITY_SET( pxTask, uxNewPriority )\r\n#endif\r\n\r\n#ifndef traceTASK_SUSPEND\r\n\t#define traceTASK_SUSPEND( pxTaskToSuspend )\r\n#endif\r\n\r\n#ifndef traceTASK_RESUME\r\n\t#define traceTASK_RESUME( pxTaskToResume )\r\n#endif\r\n\r\n#ifndef traceTASK_RESUME_FROM_ISR\r\n\t#define traceTASK_RESUME_FROM_ISR( pxTaskToResume )\r\n#endif\r\n\r\n#ifndef traceTASK_INCREMENT_TICK\r\n\t#define traceTASK_INCREMENT_TICK( xTickCount )\r\n#endif\r\n\r\n#ifndef traceTIMER_CREATE\r\n\t#define traceTIMER_CREATE( pxNewTimer )\r\n#endif\r\n\r\n#ifndef traceTIMER_CREATE_FAILED\r\n\t#define traceTIMER_CREATE_FAILED()\r\n#endif\r\n\r\n#ifndef traceTIMER_COMMAND_SEND\r\n\t#define traceTIMER_COMMAND_SEND( xTimer, xMessageID, xMessageValueValue, xReturn )\r\n#endif\r\n\r\n#ifndef traceTIMER_EXPIRED\r\n\t#define traceTIMER_EXPIRED( pxTimer )\r\n#endif\r\n\r\n#ifndef traceTIMER_COMMAND_RECEIVED\r\n\t#define traceTIMER_COMMAND_RECEIVED( pxTimer, xMessageID, xMessageValue )\r\n#endif\r\n\r\n#ifndef traceMALLOC\r\n    #define traceMALLOC( pvAddress, uiSize )\r\n#endif\r\n\r\n#ifndef traceFREE\r\n    #define traceFREE( pvAddress, uiSize )\r\n#endif\r\n\r\n#ifndef traceEVENT_GROUP_CREATE\r\n\t#define traceEVENT_GROUP_CREATE( xEventGroup )\r\n#endif\r\n\r\n#ifndef traceEVENT_GROUP_CREATE_FAILED\r\n\t#define traceEVENT_GROUP_CREATE_FAILED()\r\n#endif\r\n\r\n#ifndef traceEVENT_GROUP_SYNC_BLOCK\r\n\t#define traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor )\r\n#endif\r\n\r\n#ifndef traceEVENT_GROUP_SYNC_END\r\n\t#define traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred\r\n#endif\r\n\r\n#ifndef traceEVENT_GROUP_WAIT_BITS_BLOCK\r\n\t#define traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor )\r\n#endif\r\n\r\n#ifndef traceEVENT_GROUP_WAIT_BITS_END\r\n\t#define traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred\r\n#endif\r\n\r\n#ifndef traceEVENT_GROUP_CLEAR_BITS\r\n\t#define traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear )\r\n#endif\r\n\r\n#ifndef traceEVENT_GROUP_CLEAR_BITS_FROM_ISR\r\n\t#define traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear )\r\n#endif\r\n\r\n#ifndef traceEVENT_GROUP_SET_BITS\r\n\t#define traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet )\r\n#endif\r\n\r\n#ifndef traceEVENT_GROUP_SET_BITS_FROM_ISR\r\n\t#define traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet )\r\n#endif\r\n\r\n#ifndef traceEVENT_GROUP_DELETE\r\n\t#define traceEVENT_GROUP_DELETE( xEventGroup )\r\n#endif\r\n\r\n#ifndef tracePEND_FUNC_CALL\r\n\t#define tracePEND_FUNC_CALL(xFunctionToPend, pvParameter1, ulParameter2, ret)\r\n#endif\r\n\r\n#ifndef tracePEND_FUNC_CALL_FROM_ISR\r\n\t#define tracePEND_FUNC_CALL_FROM_ISR(xFunctionToPend, pvParameter1, ulParameter2, ret)\r\n#endif\r\n\r\n#ifndef traceQUEUE_REGISTRY_ADD\r\n\t#define traceQUEUE_REGISTRY_ADD(xQueue, pcQueueName)\r\n#endif\r\n\r\n#ifndef configGENERATE_RUN_TIME_STATS\r\n\t#define configGENERATE_RUN_TIME_STATS 0\r\n#endif\r\n\r\n#if ( configGENERATE_RUN_TIME_STATS == 1 )\r\n\r\n\t#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS\r\n\t\t#error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined.  portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base.\r\n\t#endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */\r\n\r\n\t#ifndef portGET_RUN_TIME_COUNTER_VALUE\r\n\t\t#ifndef portALT_GET_RUN_TIME_COUNTER_VALUE\r\n\t\t\t#error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined.  See the examples provided and the FreeRTOS web site for more information.\r\n\t\t#endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */\r\n\t#endif /* portGET_RUN_TIME_COUNTER_VALUE */\r\n\r\n#endif /* configGENERATE_RUN_TIME_STATS */\r\n\r\n#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS\r\n\t#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()\r\n#endif\r\n\r\n#ifndef configUSE_MALLOC_FAILED_HOOK\r\n\t#define configUSE_MALLOC_FAILED_HOOK 0\r\n#endif\r\n\r\n#ifndef portPRIVILEGE_BIT\r\n\t#define portPRIVILEGE_BIT ( ( UBaseType_t ) 0x00 )\r\n#endif\r\n\r\n#ifndef portYIELD_WITHIN_API\r\n\t#define portYIELD_WITHIN_API portYIELD\r\n#endif\r\n\r\n#ifndef pvPortMallocAligned\r\n\t#define pvPortMallocAligned( x, puxStackBuffer ) ( ( ( puxStackBuffer ) == NULL ) ? ( pvPortMalloc( ( x ) ) ) : ( puxStackBuffer ) )\r\n#endif\r\n\r\n#ifndef vPortFreeAligned\r\n\t#define vPortFreeAligned( pvBlockToFree ) vPortFree( pvBlockToFree )\r\n#endif\r\n\r\n#ifndef portSUPPRESS_TICKS_AND_SLEEP\r\n\t#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )\r\n#endif\r\n\r\n#ifndef configEXPECTED_IDLE_TIME_BEFORE_SLEEP\r\n\t#define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 2\r\n#endif\r\n\r\n#if configEXPECTED_IDLE_TIME_BEFORE_SLEEP < 2\r\n\t#error configEXPECTED_IDLE_TIME_BEFORE_SLEEP must not be less than 2\r\n#endif\r\n\r\n#ifndef configUSE_TICKLESS_IDLE\r\n\t#define configUSE_TICKLESS_IDLE 0\r\n#endif\r\n\r\n#ifndef configPRE_SLEEP_PROCESSING\r\n\t#define configPRE_SLEEP_PROCESSING( x )\r\n#endif\r\n\r\n#ifndef configPOST_SLEEP_PROCESSING\r\n\t#define configPOST_SLEEP_PROCESSING( x )\r\n#endif\r\n\r\n#ifndef configUSE_QUEUE_SETS\r\n\t#define configUSE_QUEUE_SETS 0\r\n#endif\r\n\r\n#ifndef portTASK_USES_FLOATING_POINT\r\n\t#define portTASK_USES_FLOATING_POINT()\r\n#endif\r\n\r\n#ifndef configUSE_TIME_SLICING\r\n\t#define configUSE_TIME_SLICING 1\r\n#endif\r\n\r\n#ifndef configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS\r\n\t#define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0\r\n#endif\r\n\r\n#ifndef configUSE_NEWLIB_REENTRANT\r\n\t#define configUSE_NEWLIB_REENTRANT 0\r\n#endif\r\n\r\n#ifndef configUSE_STATS_FORMATTING_FUNCTIONS\r\n\t#define configUSE_STATS_FORMATTING_FUNCTIONS 0\r\n#endif\r\n\r\n#ifndef portASSERT_IF_INTERRUPT_PRIORITY_INVALID\r\n\t#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()\r\n#endif\r\n\r\n#ifndef configUSE_TRACE_FACILITY\r\n\t#define configUSE_TRACE_FACILITY 0\r\n#endif\r\n\r\n#ifndef mtCOVERAGE_TEST_MARKER\r\n\t#define mtCOVERAGE_TEST_MARKER()\r\n#endif\r\n\r\n#ifndef mtCOVERAGE_TEST_DELAY\r\n\t#define mtCOVERAGE_TEST_DELAY()\r\n#endif\r\n\r\n#ifndef portASSERT_IF_IN_ISR\r\n\t#define portASSERT_IF_IN_ISR()\r\n#endif\r\n\r\n#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\r\n\t#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0\r\n#endif\r\n\r\n#ifndef configAPPLICATION_ALLOCATED_HEAP\r\n\t#define configAPPLICATION_ALLOCATED_HEAP 0\r\n#endif\r\n\r\n#ifndef configUSE_TASK_NOTIFICATIONS\r\n\t#define configUSE_TASK_NOTIFICATIONS 1\r\n#endif\r\n\r\n#ifndef portTICK_TYPE_IS_ATOMIC\r\n\t#define portTICK_TYPE_IS_ATOMIC 0\r\n#endif\r\n\r\n#if( portTICK_TYPE_IS_ATOMIC == 0 )\r\n\t/* Either variables of tick type cannot be read atomically, or\r\n\tportTICK_TYPE_IS_ATOMIC was not set - map the critical sections used when\r\n\tthe tick count is returned to the standard critical section macros. */\r\n\t#define portTICK_TYPE_ENTER_CRITICAL() portENTER_CRITICAL()\r\n\t#define portTICK_TYPE_EXIT_CRITICAL() portEXIT_CRITICAL()\r\n\t#define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR()\r\n\t#define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( ( x ) )\r\n#else\r\n\t/* The tick type can be read atomically, so critical sections used when the\r\n\ttick count is returned can be defined away. */\r\n\t#define portTICK_TYPE_ENTER_CRITICAL()\r\n\t#define portTICK_TYPE_EXIT_CRITICAL()\r\n\t#define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() 0\r\n\t#define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) ( void ) x\r\n#endif\r\n\r\n/* Definitions to allow backward compatibility with FreeRTOS versions prior to\r\nV8 if desired. */\r\n#ifndef configENABLE_BACKWARD_COMPATIBILITY\r\n\t#define configENABLE_BACKWARD_COMPATIBILITY 1\r\n#endif\r\n\r\n#if configENABLE_BACKWARD_COMPATIBILITY == 1\r\n\t#define eTaskStateGet eTaskGetState\r\n\t#define portTickType TickType_t\r\n\t#define xTaskHandle TaskHandle_t\r\n\t#define xQueueHandle QueueHandle_t\r\n\t#define xSemaphoreHandle SemaphoreHandle_t\r\n\t#define xQueueSetHandle QueueSetHandle_t\r\n\t#define xQueueSetMemberHandle QueueSetMemberHandle_t\r\n\t#define xTimeOutType TimeOut_t\r\n\t#define xMemoryRegion MemoryRegion_t\r\n\t#define xTaskParameters TaskParameters_t\r\n\t#define xTaskStatusType\tTaskStatus_t\r\n\t#define xTimerHandle TimerHandle_t\r\n\t#define xCoRoutineHandle CoRoutineHandle_t\r\n\t#define pdTASK_HOOK_CODE TaskHookFunction_t\r\n\t#define portTICK_RATE_MS portTICK_PERIOD_MS\r\n\r\n\t/* Backward compatibility within the scheduler code only - these definitions\r\n\tare not really required but are included for completeness. */\r\n\t#define tmrTIMER_CALLBACK TimerCallbackFunction_t\r\n\t#define pdTASK_CODE TaskFunction_t\r\n\t#define xListItem ListItem_t\r\n\t#define xList List_t\r\n#endif /* configENABLE_BACKWARD_COMPATIBILITY */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* INC_FREERTOS_H */\r\n\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RTOS/src/FreeRTOSConfig.h",
    "content": "/*\r\n    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r\n    All rights reserved\r\n\r\n    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r\n\r\n    This file is part of the FreeRTOS distribution.\r\n\r\n    FreeRTOS is free software; you can redistribute it and/or modify it under\r\n    the terms of the GNU General Public License (version 2) as published by the\r\n    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r\n\r\n\t***************************************************************************\r\n    >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r\n    >>!   distribute a combined work that includes FreeRTOS without being   !<<\r\n    >>!   obliged to provide the source code for proprietary components     !<<\r\n    >>!   outside of the FreeRTOS kernel.                                   !<<\r\n\t***************************************************************************\r\n\r\n    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r\n    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r\n    FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r\n    link: http://www.freertos.org/a00114.html\r\n\r\n    ***************************************************************************\r\n     *                                                                       *\r\n     *    FreeRTOS provides completely free yet professionally developed,    *\r\n     *    robust, strictly quality controlled, supported, and cross          *\r\n     *    platform software that is more than just the market leader, it     *\r\n     *    is the industry's de facto standard.                               *\r\n     *                                                                       *\r\n     *    Help yourself get started quickly while simultaneously helping     *\r\n     *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r\n     *    tutorial book, reference manual, or both:                          *\r\n     *    http://www.FreeRTOS.org/Documentation                              *\r\n     *                                                                       *\r\n    ***************************************************************************\r\n\r\n    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r\n\tthe FAQ page \"My application does not run, what could be wrong?\".  Have you\r\n\tdefined configASSERT()?\r\n\r\n\thttp://www.FreeRTOS.org/support - In return for receiving this top quality\r\n\tembedded software for free we request you assist our global community by\r\n\tparticipating in the support forum.\r\n\r\n\thttp://www.FreeRTOS.org/training - Investing in training allows your team to\r\n\tbe as productive as possible as early as possible.  Now you can receive\r\n\tFreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r\n\tLtd, and the world's leading authority on the world's leading RTOS.\r\n\r\n    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r\n    including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r\n    compatible FAT file system, and our tiny thread aware UDP/IP stack.\r\n\r\n    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r\n    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r\n\r\n    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r\n    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r\n    licenses offer ticketed support, indemnification and commercial middleware.\r\n\r\n    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r\n    engineered and independently SIL3 certified version for use in safety and\r\n    mission critical applications that require provable dependability.\r\n\r\n    1 tab == 4 spaces!\r\n*/\r\n\r\n\r\n#ifndef FREERTOS_CONFIG_H\r\n#define FREERTOS_CONFIG_H\r\n\r\n/*-----------------------------------------------------------\r\n * Application specific definitions.\r\n *\r\n * These definitions should be adjusted for your particular hardware and\r\n * application requirements.\r\n *\r\n * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r\n * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r\n *\r\n * See http://www.freertos.org/a00110.html.\r\n *----------------------------------------------------------*/\r\n\r\n/* Ensure stdint is only used by the compiler, and not the assembler. */\r\n#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__)\r\n #include <stdint.h>\r\n extern uint32_t SystemCoreClock;\r\n#endif\r\n\r\n#define configUSE_PREEMPTION              1\r\n#define configUSE_IDLE_HOOK               0\r\n#define configUSE_TICK_HOOK               0\r\n#define configCPU_CLOCK_HZ                (SystemCoreClock)\r\n#define configTICK_RATE_HZ                ((TickType_t)1000)\r\n#define configMAX_PRIORITIES              (7)\r\n#define configMINIMAL_STACK_SIZE          ((uint16_t)128)\r\n#define configTOTAL_HEAP_SIZE             ((size_t)(32 * 1024))\r\n#define configMAX_TASK_NAME_LEN           (16)\r\n#define configUSE_TRACE_FACILITY          1\r\n#define configUSE_16_BIT_TICKS            0\r\n#define configIDLE_SHOULD_YIELD           1\r\n#define configUSE_MUTEXES                 1\r\n#define configQUEUE_REGISTRY_SIZE         8\r\n#define configCHECK_FOR_STACK_OVERFLOW    0\r\n#define configUSE_RECURSIVE_MUTEXES       1\r\n#define configUSE_MALLOC_FAILED_HOOK      0\r\n#define configUSE_APPLICATION_TASK_TAG    0\r\n#define configUSE_COUNTING_SEMAPHORES     1\r\n#define configGENERATE_RUN_TIME_STATS     0\r\n\r\n/* Co-routine definitions. */\r\n#define configUSE_CO_ROUTINES           0\r\n#define configMAX_CO_ROUTINE_PRIORITIES (2)\r\n\r\n/* Software timer definitions. */\r\n#define configUSE_TIMERS             0\r\n#define configTIMER_TASK_PRIORITY    (2)\r\n#define configTIMER_QUEUE_LENGTH     10\r\n#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2)\r\n\r\n/* Set the following definitions to 1 to include the API function, or zero\r\nto exclude the API function. */\r\n#define INCLUDE_vTaskPrioritySet       1\r\n#define INCLUDE_uxTaskPriorityGet      1\r\n#define INCLUDE_vTaskDelete            1\r\n#define INCLUDE_vTaskCleanUpResources  0\r\n#define INCLUDE_vTaskSuspend           1\r\n#define INCLUDE_vTaskDelayUntil        0\r\n#define INCLUDE_vTaskDelay             1\r\n#define INCLUDE_xTaskGetSchedulerState 1\r\n\r\n/* Cortex-M specific definitions. */\r\n#ifdef __NVIC_PRIO_BITS\r\n /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */\r\n #define configPRIO_BITS         __NVIC_PRIO_BITS\r\n#else\r\n #define configPRIO_BITS         4        /* 15 priority levels */\r\n#endif\r\n\r\n/* The lowest interrupt priority that can be used in a call to a \"set priority\"\r\nfunction. */\r\n#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY   0xf\r\n\r\n/* The highest interrupt priority that can be used by any interrupt service\r\nroutine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL\r\nINTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER\r\nPRIORITY THAN THIS! (higher priorities are lower numeric values. */\r\n#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5\r\n\r\n/* Interrupt priorities used by the kernel port layer itself.  These are generic\r\nto all Cortex-M ports, and do not rely on any particular library functions. */\r\n#define configKERNEL_INTERRUPT_PRIORITY   ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r\n/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!\r\nSee http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */\r\n#define configMAX_SYSCALL_INTERRUPT_PRIORITY  ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r\n\r\n/* Normal assert() semantics without relying on the provision of an assert.h\r\nheader file. */\r\n#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }\r\n\r\n/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS\r\n   standard names. */\r\n#define vPortSVCHandler    SVC_Handler\r\n#define xPortPendSVHandler PendSV_Handler\r\n\r\n/* IMPORTANT: This define MUST be commented when used with STM32Cube firmware,\r\n              to prevent overwriting SysTick_Handler defined within STM32Cube HAL */\r\n/* #define xPortSysTickHandler SysTick_Handler */\r\n\r\n#endif /* FREERTOS_CONFIG_H */\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RTOS/src/RTOS.cpp",
    "content": ""
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RTOS/src/RTOS.h",
    "content": "#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n#include \"cmsis_os.h\"\n\n#ifdef __cplusplus\n}\n#endif\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RTOS/src/StackMacros.h",
    "content": "/*\r\n    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r\n    All rights reserved\r\n\r\n    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r\n\r\n    This file is part of the FreeRTOS distribution.\r\n\r\n    FreeRTOS is free software; you can redistribute it and/or modify it under\r\n    the terms of the GNU General Public License (version 2) as published by the\r\n    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r\n\r\n    ***************************************************************************\r\n    >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r\n    >>!   distribute a combined work that includes FreeRTOS without being   !<<\r\n    >>!   obliged to provide the source code for proprietary components     !<<\r\n    >>!   outside of the FreeRTOS kernel.                                   !<<\r\n    ***************************************************************************\r\n\r\n    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r\n    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r\n    FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r\n    link: http://www.freertos.org/a00114.html\r\n\r\n    ***************************************************************************\r\n     *                                                                       *\r\n     *    FreeRTOS provides completely free yet professionally developed,    *\r\n     *    robust, strictly quality controlled, supported, and cross          *\r\n     *    platform software that is more than just the market leader, it     *\r\n     *    is the industry's de facto standard.                               *\r\n     *                                                                       *\r\n     *    Help yourself get started quickly while simultaneously helping     *\r\n     *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r\n     *    tutorial book, reference manual, or both:                          *\r\n     *    http://www.FreeRTOS.org/Documentation                              *\r\n     *                                                                       *\r\n    ***************************************************************************\r\n\r\n    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r\n    the FAQ page \"My application does not run, what could be wrong?\".  Have you\r\n    defined configASSERT()?\r\n\r\n    http://www.FreeRTOS.org/support - In return for receiving this top quality\r\n    embedded software for free we request you assist our global community by\r\n    participating in the support forum.\r\n\r\n    http://www.FreeRTOS.org/training - Investing in training allows your team to\r\n    be as productive as possible as early as possible.  Now you can receive\r\n    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r\n    Ltd, and the world's leading authority on the world's leading RTOS.\r\n\r\n    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r\n    including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r\n    compatible FAT file system, and our tiny thread aware UDP/IP stack.\r\n\r\n    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r\n    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r\n\r\n    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r\n    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r\n    licenses offer ticketed support, indemnification and commercial middleware.\r\n\r\n    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r\n    engineered and independently SIL3 certified version for use in safety and\r\n    mission critical applications that require provable dependability.\r\n\r\n    1 tab == 4 spaces!\r\n*/\r\n\r\n#ifndef STACK_MACROS_H\r\n#define STACK_MACROS_H\r\n\r\n/*\r\n * Call the stack overflow hook function if the stack of the task being swapped\r\n * out is currently overflowed, or looks like it might have overflowed in the\r\n * past.\r\n *\r\n * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check\r\n * the current stack state only - comparing the current top of stack value to\r\n * the stack limit.  Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1\r\n * will also cause the last few stack bytes to be checked to ensure the value\r\n * to which the bytes were set when the task was created have not been\r\n * overwritten.  Note this second test does not guarantee that an overflowed\r\n * stack will always be recognised.\r\n */\r\n\r\n/*-----------------------------------------------------------*/\r\n\r\n#if( configCHECK_FOR_STACK_OVERFLOW == 0 )\r\n\r\n\t/* FreeRTOSConfig.h is not set to check for stack overflows. */\r\n\t#define taskFIRST_CHECK_FOR_STACK_OVERFLOW()\r\n\t#define taskSECOND_CHECK_FOR_STACK_OVERFLOW()\r\n\r\n#endif /* configCHECK_FOR_STACK_OVERFLOW == 0 */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if( configCHECK_FOR_STACK_OVERFLOW == 1 )\r\n\r\n\t/* FreeRTOSConfig.h is only set to use the first method of\r\n\toverflow checking. */\r\n\t#define taskSECOND_CHECK_FOR_STACK_OVERFLOW()\r\n\r\n#endif\r\n/*-----------------------------------------------------------*/\r\n\r\n#if( ( configCHECK_FOR_STACK_OVERFLOW > 0 ) && ( portSTACK_GROWTH < 0 ) )\r\n\r\n\t/* Only the current stack state is to be checked. */\r\n\t#define taskFIRST_CHECK_FOR_STACK_OVERFLOW()\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t/* Is the currently saved stack pointer within the stack limit? */\t\t\t\t\t\t\t\t\\\r\n\t\tif( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack )\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t\tvApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );\t\\\r\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t}\r\n\r\n#endif /* configCHECK_FOR_STACK_OVERFLOW > 0 */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if( ( configCHECK_FOR_STACK_OVERFLOW > 0 ) && ( portSTACK_GROWTH > 0 ) )\r\n\r\n\t/* Only the current stack state is to be checked. */\r\n\t#define taskFIRST_CHECK_FOR_STACK_OVERFLOW()\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t/* Is the currently saved stack pointer within the stack limit? */\t\t\t\t\t\t\t\t\\\r\n\t\tif( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack )\t\t\t\t\t\t\t\t\t\\\r\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t\tvApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );\t\\\r\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t}\r\n\r\n#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )\r\n\r\n\t#define taskSECOND_CHECK_FOR_STACK_OVERFLOW()\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\tstatic const uint8_t ucExpectedStackBytes[] = {\ttskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,\t\t\\\r\n\t\t\t\t\t\t\t\t\t\t\t\t\ttskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,\t\t\\\r\n\t\t\t\t\t\t\t\t\t\t\t\t\ttskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,\t\t\\\r\n\t\t\t\t\t\t\t\t\t\t\t\t\ttskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,\t\t\\\r\n\t\t\t\t\t\t\t\t\t\t\t\t\ttskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE };\t\\\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t/* Has the extremity of the task stack ever been written over? */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\tif( memcmp( ( void * ) pxCurrentTCB->pxStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )\t\t\t\\\r\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t\tvApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );\t\t\t\t\t\t\t\t\t\\\r\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t}\r\n\r\n#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )\r\n\r\n\t#define taskSECOND_CHECK_FOR_STACK_OVERFLOW()\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\tint8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\tstatic const uint8_t ucExpectedStackBytes[] = {\ttskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,\t\t\\\r\n\t\t\t\t\t\t\t\t\t\t\t\t\ttskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,\t\t\\\r\n\t\t\t\t\t\t\t\t\t\t\t\t\ttskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,\t\t\\\r\n\t\t\t\t\t\t\t\t\t\t\t\t\ttskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,\t\t\\\r\n\t\t\t\t\t\t\t\t\t\t\t\t\ttskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE };\t\\\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\tpcEndOfStack -= sizeof( ucExpectedStackBytes );\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t/* Has the extremity of the task stack ever been written over? */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\tif( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )\t\t\t\t\t\\\r\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t\tvApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );\t\t\t\t\t\t\t\t\t\\\r\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t}\r\n\r\n#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */\r\n/*-----------------------------------------------------------*/\r\n\r\n#endif /* STACK_MACROS_H */\r\n\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RTOS/src/cmsis_os.c",
    "content": "/* ----------------------------------------------------------------------\r\n * $Date:        5. February 2013\r\n * $Revision:    V1.02\r\n *\r\n * Project:      CMSIS-RTOS API\r\n * Title:        cmsis_os.c\r\n *\r\n * Version 0.02\r\n *    Initial Proposal Phase\r\n * Version 0.03\r\n *    osKernelStart added, optional feature: main started as thread\r\n *    osSemaphores have standard behavior\r\n *    osTimerCreate does not start the timer, added osTimerStart\r\n *    osThreadPass is renamed to osThreadYield\r\n * Version 1.01\r\n *    Support for C++ interface\r\n *     - const attribute removed from the osXxxxDef_t typedef's\r\n *     - const attribute added to the osXxxxDef macros\r\n *    Added: osTimerDelete, osMutexDelete, osSemaphoreDelete\r\n *    Added: osKernelInitialize\r\n * Version 1.02\r\n *    Control functions for short timeouts in microsecond resolution:\r\n *    Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec\r\n *    Removed: osSignalGet \r\n *    \r\n *  \r\n *----------------------------------------------------------------------------\r\n *\r\n * Portions COPYRIGHT 2015 STMicroelectronics\r\n * Portions Copyright (c) 2013 ARM LIMITED\r\n * All rights reserved.\r\n * Redistribution and use in source and binary forms, with or without\r\n * modification, are permitted provided that the following conditions are met:\r\n *  - Redistributions of source code must retain the above copyright\r\n *    notice, this list of conditions and the following disclaimer.\r\n *  - Redistributions in binary form must reproduce the above copyright\r\n *    notice, this list of conditions and the following disclaimer in the\r\n *    documentation and/or other materials provided with the distribution.\r\n *  - Neither the name of ARM  nor the names of its contributors may be used\r\n *    to endorse or promote products derived from this software without\r\n *    specific prior written permission.\r\n *\r\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r\n * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n * POSSIBILITY OF SUCH DAMAGE.\r\n *---------------------------------------------------------------------------*/\r\n\r\n /**\r\n  ******************************************************************************\r\n  * @file    cmsis_os.c\r\n  * @author  MCD Application Team\r\n  * @date    27-March-2015\r\n  * @brief   CMSIS-RTOS API implementation for FreeRTOS V8.2.1\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n#include <string.h>\r\n#include \"cmsis_os.h\"\r\n\r\nextern void xPortSysTickHandler(void);\r\n\r\n/* Convert from CMSIS type osPriority to FreeRTOS priority number */\r\nstatic unsigned portBASE_TYPE makeFreeRtosPriority (osPriority priority)\r\n{\r\n  unsigned portBASE_TYPE fpriority = tskIDLE_PRIORITY;\r\n  \r\n  if (priority != osPriorityError) {\r\n    fpriority += (priority - osPriorityIdle);\r\n  }\r\n  \r\n  return fpriority;\r\n}\r\n\r\n#if (INCLUDE_uxTaskPriorityGet == 1)\r\n/* Convert from FreeRTOS priority number to CMSIS type osPriority */\r\nstatic osPriority makeCmsisPriority (unsigned portBASE_TYPE fpriority)\r\n{\r\n  osPriority priority = osPriorityError;\r\n  \r\n  if ((fpriority - tskIDLE_PRIORITY) <= (osPriorityRealtime - osPriorityIdle)) {\r\n    priority = (osPriority)((int)osPriorityIdle + (int)(fpriority - tskIDLE_PRIORITY));\r\n  }\r\n  \r\n  return priority;\r\n}\r\n#endif\r\n\r\n\r\n/* Determine whether we are in thread mode or handler mode. */\r\nstatic int inHandlerMode (void)\r\n{\r\n  return __get_IPSR() != 0;\r\n}\r\n\r\n/*********************** Kernel Control Functions *****************************/\r\n/**\r\n* @brief  Initialize the RTOS Kernel for creating objects.\r\n* @retval status code that indicates the execution status of the function.\r\n* @note   MUST REMAIN UNCHANGED: \\b osKernelInitialize shall be consistent in every CMSIS-RTOS.\r\n*/\r\nosStatus osKernelInitialize (void);\r\n\r\n/**\r\n* @brief  Start the RTOS Kernel with executing the specified thread.\r\n* @param  thread_def    thread definition referenced with \\ref osThread.\r\n* @param  argument      pointer that is passed to the thread function as start argument.\r\n* @retval status code that indicates the execution status of the function\r\n* @note   MUST REMAIN UNCHANGED: \\b osKernelStart shall be consistent in every CMSIS-RTOS.\r\n*/\r\nosStatus osKernelStart (void)\r\n{\r\n  vTaskStartScheduler();\r\n  \r\n  return osOK;\r\n}\r\n\r\n/**\r\n* @brief  Check if the RTOS kernel is already started\r\n* @param  None\r\n* @retval (0) RTOS is not started\r\n*         (1) RTOS is started\r\n*         (-1) if this feature is disabled in FreeRTOSConfig.h \r\n* @note  MUST REMAIN UNCHANGED: \\b osKernelRunning shall be consistent in every CMSIS-RTOS.\r\n*/\r\nint32_t osKernelRunning(void)\r\n{\r\n#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\r\n  if (xTaskGetSchedulerState() == taskSCHEDULER_NOT_STARTED)\r\n    return 0;\r\n  else\r\n    return 1;\r\n#else\r\n\treturn (-1);\r\n#endif\t\r\n}\r\n\r\n#if (defined (osFeature_SysTick)  &&  (osFeature_SysTick != 0))     // System Timer available\r\n/**\r\n* @brief  Get the value of the Kernel SysTick timer\r\n* @param  None\r\n* @retval None\r\n* @note   MUST REMAIN UNCHANGED: \\b osKernelSysTick shall be consistent in every CMSIS-RTOS.\r\n*/\r\nuint32_t osKernelSysTick(void)\r\n{\r\n  if (inHandlerMode()) {\r\n    return xTaskGetTickCountFromISR();\r\n  }\r\n  else {\r\n    return xTaskGetTickCount();\r\n  }\r\n}\r\n#endif    // System Timer available\r\n/*********************** Thread Management *****************************/\r\n/**\r\n* @brief  Create a thread and add it to Active Threads and set it to state READY.\r\n* @param  thread_def    thread definition referenced with \\ref osThread.\r\n* @param  argument      pointer that is passed to the thread function as start argument.\r\n* @retval thread ID for reference by other functions or NULL in case of error.\r\n* @note   MUST REMAIN UNCHANGED: \\b osThreadCreate shall be consistent in every CMSIS-RTOS.\r\n*/\r\nosThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument)\r\n{\r\n  TaskHandle_t handle;\r\n  \r\n  \r\n  if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,\r\n              thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority),\r\n              &handle) != pdPASS)  {\r\n    return NULL;\r\n  }\r\n  \r\n  return handle;\r\n}\r\n\r\n/**\r\n* @brief  Return the thread ID of the current running thread.\r\n* @retval thread ID for reference by other functions or NULL in case of error.\r\n* @note   MUST REMAIN UNCHANGED: \\b osThreadGetId shall be consistent in every CMSIS-RTOS.\r\n*/\r\nosThreadId osThreadGetId (void)\r\n{\r\n#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )\r\n  return xTaskGetCurrentTaskHandle();\r\n#else\r\n\treturn NULL;\r\n#endif\r\n}\r\n\r\n/**\r\n* @brief  Terminate execution of a thread and remove it from Active Threads.\r\n* @param   thread_id   thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\r\n* @retval  status code that indicates the execution status of the function.\r\n* @note   MUST REMAIN UNCHANGED: \\b osThreadTerminate shall be consistent in every CMSIS-RTOS.\r\n*/\r\nosStatus osThreadTerminate (osThreadId thread_id)\r\n{\r\n#if (INCLUDE_vTaskDelete == 1)\r\n  vTaskDelete(thread_id);\r\n  return osOK;\r\n#else\r\n  return osErrorOS;\r\n#endif\r\n}\r\n\r\n/**\r\n* @brief  Pass control to next thread that is in state \\b READY.\r\n* @retval status code that indicates the execution status of the function.\r\n* @note   MUST REMAIN UNCHANGED: \\b osThreadYield shall be consistent in every CMSIS-RTOS.\r\n*/\r\nosStatus osThreadYield (void)\r\n{\r\n  taskYIELD();\r\n  \r\n  return osOK;\r\n}\r\n\r\n/**\r\n* @brief   Change priority of an active thread.\r\n* @param   thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\r\n* @param   priority      new priority value for the thread function.\r\n* @retval  status code that indicates the execution status of the function.\r\n* @note   MUST REMAIN UNCHANGED: \\b osThreadSetPriority shall be consistent in every CMSIS-RTOS.\r\n*/\r\nosStatus osThreadSetPriority (osThreadId thread_id, osPriority priority)\r\n{\r\n#if (INCLUDE_vTaskPrioritySet == 1)\r\n  vTaskPrioritySet(thread_id, makeFreeRtosPriority(priority));\r\n  return osOK;\r\n#else\r\n  return osErrorOS;\r\n#endif\r\n}\r\n\r\n/**\r\n* @brief   Get current priority of an active thread.\r\n* @param   thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\r\n* @retval  current priority value of the thread function.\r\n* @note   MUST REMAIN UNCHANGED: \\b osThreadGetPriority shall be consistent in every CMSIS-RTOS.\r\n*/\r\nosPriority osThreadGetPriority (osThreadId thread_id)\r\n{\r\n#if (INCLUDE_uxTaskPriorityGet == 1)\r\n  if (inHandlerMode())\r\n  {\r\n    return makeCmsisPriority(uxTaskPriorityGetFromISR(thread_id));  \r\n  }\r\n  else\r\n  {  \r\n    return makeCmsisPriority(uxTaskPriorityGet(thread_id));\r\n  }\r\n#else\r\n  return osPriorityError;\r\n#endif\r\n}\r\n\r\n/*********************** Generic Wait Functions *******************************/\r\n/**\r\n* @brief   Wait for Timeout (Time Delay)\r\n* @param   millisec      time delay value\r\n* @retval  status code that indicates the execution status of the function.\r\n*/\r\nosStatus osDelay (uint32_t millisec)\r\n{\r\n#if INCLUDE_vTaskDelay\r\n  TickType_t ticks = millisec / portTICK_PERIOD_MS;\r\n  \r\n  vTaskDelay(ticks ? ticks : 1);          /* Minimum delay = 1 tick */\r\n  \r\n  return osOK;\r\n#else\r\n  (void) millisec;\r\n  \r\n  return osErrorResource;\r\n#endif\r\n}\r\n\r\n#if (defined (osFeature_Wait)  &&  (osFeature_Wait != 0)) /* Generic Wait available */\r\n/**\r\n* @brief  Wait for Signal, Message, Mail, or Timeout\r\n* @param   millisec  timeout value or 0 in case of no time-out\r\n* @retval  event that contains signal, message, or mail information or error code.\r\n* @note   MUST REMAIN UNCHANGED: \\b osWait shall be consistent in every CMSIS-RTOS.\r\n*/\r\nosEvent osWait (uint32_t millisec);\r\n\r\n#endif  /* Generic Wait available */\r\n\r\n/***********************  Timer Management Functions ***************************/\r\n/**\r\n* @brief  Create a timer.\r\n* @param  timer_def     timer object referenced with \\ref osTimer.\r\n* @param  type          osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.\r\n* @param  argument      argument to the timer call back function.\r\n* @retval  timer ID for reference by other functions or NULL in case of error.\r\n* @note   MUST REMAIN UNCHANGED: \\b osTimerCreate shall be consistent in every CMSIS-RTOS.\r\n*/\r\nosTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument)\r\n{\r\n#if (configUSE_TIMERS == 1)\r\n  return xTimerCreate((const char *)\"\",\r\n                      1, // period should be filled when starting the Timer using osTimerStart\r\n                      (type == osTimerPeriodic) ? pdTRUE : pdFALSE,\r\n                      (void *) argument,\r\n                      (TaskFunction_t)timer_def->ptimer);\r\n#else \r\n\treturn NULL;\r\n#endif\r\n}\r\n\r\n/**\r\n* @brief  Start or restart a timer.\r\n* @param  timer_id      timer ID obtained by \\ref osTimerCreate.\r\n* @param  millisec      time delay value of the timer.\r\n* @retval  status code that indicates the execution status of the function\r\n* @note   MUST REMAIN UNCHANGED: \\b osTimerStart shall be consistent in every CMSIS-RTOS.\r\n*/\r\nosStatus osTimerStart (osTimerId timer_id, uint32_t millisec)\r\n{\r\n  osStatus result = osOK;\r\n#if (configUSE_TIMERS == 1)  \r\n\tportBASE_TYPE taskWoken = pdFALSE;\r\n  TickType_t ticks = millisec / portTICK_PERIOD_MS;\r\n  \r\n  if (xTimerIsTimerActive(timer_id) != pdFALSE)\r\n  {\r\n    if (inHandlerMode()) \r\n    {\r\n      if(xTimerResetFromISR(timer_id, &taskWoken) != pdPASS)\r\n      {\r\n        result = osErrorOS;\r\n      }\r\n      else\r\n      {\r\n        portEND_SWITCHING_ISR(taskWoken);\r\n        result = osOK;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      if (xTimerReset(timer_id, 0) != pdPASS)\r\n        result = osErrorOS;\r\n      else   \r\n        result = osOK;\r\n    }\r\n  }\r\n  else\r\n  {\r\n    if (ticks == 0)\r\n      ticks = 1;\r\n    \r\n    if (inHandlerMode()) \r\n    {\r\n      if (xTimerChangePeriodFromISR(timer_id, ticks, &taskWoken) != pdPASS) \r\n        result = osErrorOS;\r\n      else\r\n      {\r\n        xTimerStartFromISR(timer_id, &taskWoken);\r\n        portEND_SWITCHING_ISR(taskWoken);\r\n        result = osOK; \r\n      }\r\n    }\r\n    else \r\n    {\r\n      if (xTimerChangePeriod(timer_id, ticks, 0) != pdPASS)\r\n        result = osErrorOS;\r\n      else\r\n      {\r\n        if (xTimerStart(timer_id, 0) != pdPASS)\r\n          result = osErrorOS;\r\n      }\r\n    }\r\n  }\r\n#else \r\n  result = osErrorOS;\r\n#endif\r\n  return result;\r\n}\r\n\r\n/**\r\n* @brief  Stop a timer.\r\n* @param  timer_id      timer ID obtained by \\ref osTimerCreate\r\n* @retval  status code that indicates the execution status of the function.\r\n* @note   MUST REMAIN UNCHANGED: \\b osTimerStop shall be consistent in every CMSIS-RTOS.\r\n*/\r\nosStatus osTimerStop (osTimerId timer_id)\r\n{\r\n  osStatus result = osOK;\r\n#if (configUSE_TIMERS == 1)  \r\n  portBASE_TYPE taskWoken = pdFALSE;\r\n\r\n  if (inHandlerMode()) {\r\n    if (xTimerStopFromISR(timer_id, &taskWoken) != pdPASS) {\r\n      return osErrorOS;\r\n    }\r\n    portEND_SWITCHING_ISR(taskWoken);\r\n  }\r\n  else {\r\n    if (xTimerStop(timer_id, 0) != pdPASS) {\r\n      result = osErrorOS;\r\n    }\r\n  }\r\n#else \r\n  result = osErrorOS;\r\n#endif \r\n  return result;\r\n}\r\n\r\n/**\r\n* @brief  Delete a timer.\r\n* @param  timer_id      timer ID obtained by \\ref osTimerCreate\r\n* @retval  status code that indicates the execution status of the function.\r\n* @note   MUST REMAIN UNCHANGED: \\b osTimerDelete shall be consistent in every CMSIS-RTOS.\r\n*/\r\nosStatus osTimerDelete (osTimerId timer_id)\r\n{\r\nosStatus result = osOK;\r\n\r\n#if (configUSE_TIMERS == 1)\r\n\r\n   if (inHandlerMode()) {\r\n     return osErrorISR;\r\n  }\r\n  else { \r\n    if ((xTimerDelete(timer_id, osWaitForever )) != pdPASS) {\r\n      result = osErrorOS;\r\n    }\r\n  } \r\n    \r\n#else \r\n  result = osErrorOS;\r\n#endif \r\n \r\n  return result;\r\n}\r\n\r\n/***************************  Signal Management ********************************/\r\n/**\r\n* @brief  Set the specified Signal Flags of an active thread.\r\n* @param  thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\r\n* @param  signals       specifies the signal flags of the thread that should be set.\r\n* @retval  osOK if successful, osErrorOS if failed .\r\n* @note   MUST REMAIN UNCHANGED: \\b osSignalSet shall be consistent in every CMSIS-RTOS.\r\n*/\r\nint32_t osSignalSet (osThreadId thread_id, int32_t signal)\r\n{\r\n  BaseType_t xHigherPriorityTaskWoken = pdFALSE;\r\n  \r\n  if (inHandlerMode())\r\n  {\r\n    if(xTaskNotifyFromISR( thread_id, (uint32_t)signal, eSetBits, &xHigherPriorityTaskWoken ) != pdPASS )\r\n      return osErrorOS;\r\n\r\n    portYIELD_FROM_ISR( xHigherPriorityTaskWoken );\r\n  }  \r\n  else if(xTaskNotify( thread_id, (uint32_t)signal, eSetBits) != pdPASS )\r\n  {\r\n    return osErrorOS;\r\n  }\r\n  \r\n  return osOK;\r\n}\r\n\r\n/**\r\n* @brief  Clear the specified Signal Flags of an active thread.\r\n* @param  thread_id  thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\r\n* @param  signals    specifies the signal flags of the thread that shall be cleared.\r\n* @retval  previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.\r\n* @note   MUST REMAIN UNCHANGED: \\b osSignalClear shall be consistent in every CMSIS-RTOS.\r\n*/\r\nint32_t osSignalClear (osThreadId thread_id, int32_t signal);\r\n\r\n/**\r\n* @brief  Wait for one or more Signal Flags to become signaled for the current \\b RUNNING thread.\r\n* @param  signals   wait until all specified signal flags set or 0 for any single signal flag.\r\n* @param  millisec  timeout value or 0 in case of no time-out.\r\n* @retval  event flag information or error code.\r\n* @note   MUST REMAIN UNCHANGED: \\b osSignalWait shall be consistent in every CMSIS-RTOS.\r\n*/\r\nosEvent osSignalWait (int32_t signals, uint32_t millisec)\r\n{\r\n  osEvent ret;\r\n  TickType_t ticks;\r\n\r\n  ret.value.signals = 0;  \r\n  ticks = 0;\r\n  if (millisec == osWaitForever) {\r\n    ticks = portMAX_DELAY;\r\n  }\r\n  else if (millisec != 0) {\r\n    ticks = millisec / portTICK_PERIOD_MS;\r\n    if (ticks == 0) {\r\n      ticks = 1;\r\n    }\r\n  }  \r\n  \r\n  if (inHandlerMode())\r\n  {\r\n    ret.status = osErrorISR;  /*Not allowed in ISR*/\r\n  }\r\n  else\r\n  {\r\n    if(xTaskNotifyWait( 0,(uint32_t) signals, (uint32_t *)&ret.value.signals, ticks) != pdTRUE)\r\n    {\r\n      if(ticks == 0)  ret.status = osOK;\r\n      else  ret.status = osEventTimeout;\r\n    }\r\n    else if(ret.value.signals >= 0x80000000)\r\n    {\r\n      ret.status =  osErrorValue;     \r\n    }\r\n    else  ret.status =  osEventSignal;\r\n  }  \r\n  return ret;\r\n}\r\n\r\n/****************************  Mutex Management ********************************/\r\n/**\r\n* @brief  Create and Initialize a Mutex object\r\n* @param  mutex_def     mutex definition referenced with \\ref osMutex.\r\n* @retval  mutex ID for reference by other functions or NULL in case of error.\r\n* @note   MUST REMAIN UNCHANGED: \\b osMutexCreate shall be consistent in every CMSIS-RTOS.\r\n*/\r\nosMutexId osMutexCreate (const osMutexDef_t *mutex_def)\r\n{\r\n#if ( configUSE_MUTEXES == 1)\r\n  return xSemaphoreCreateMutex(); \r\n#else\r\n\treturn NULL;\r\n#endif\r\n}\r\n\r\n/**\r\n* @brief Wait until a Mutex becomes available\r\n* @param mutex_id      mutex ID obtained by \\ref osMutexCreate.\r\n* @param millisec      timeout value or 0 in case of no time-out.\r\n* @retval  status code that indicates the execution status of the function.\r\n* @note   MUST REMAIN UNCHANGED: \\b osMutexWait shall be consistent in every CMSIS-RTOS.\r\n*/\r\nosStatus osMutexWait (osMutexId mutex_id, uint32_t millisec)\r\n{\r\n  TickType_t ticks;\r\n  portBASE_TYPE taskWoken = pdFALSE;  \r\n  \r\n  \r\n  if (mutex_id == NULL) {\r\n    return osErrorParameter;\r\n  }\r\n  \r\n  ticks = 0;\r\n  if (millisec == osWaitForever) {\r\n    ticks = portMAX_DELAY;\r\n  }\r\n  else if (millisec != 0) {\r\n    ticks = millisec / portTICK_PERIOD_MS;\r\n    if (ticks == 0) {\r\n      ticks = 1;\r\n    }\r\n  }\r\n  \r\n  if (inHandlerMode()) {\r\n    if (xSemaphoreTakeFromISR(mutex_id, &taskWoken) != pdTRUE) {\r\n      return osErrorOS;\r\n    }\r\n\tportEND_SWITCHING_ISR(taskWoken);\r\n  } \r\n  else if (xSemaphoreTake(mutex_id, ticks) != pdTRUE) {\r\n    return osErrorOS;\r\n  }\r\n  \r\n  return osOK;\r\n}\r\n\r\n/**\r\n* @brief Release a Mutex that was obtained by \\ref osMutexWait\r\n* @param mutex_id      mutex ID obtained by \\ref osMutexCreate.\r\n* @retval  status code that indicates the execution status of the function.\r\n* @note   MUST REMAIN UNCHANGED: \\b osMutexRelease shall be consistent in every CMSIS-RTOS.\r\n*/\r\nosStatus osMutexRelease (osMutexId mutex_id)\r\n{\r\n  osStatus result = osOK;\r\n  portBASE_TYPE taskWoken = pdFALSE;\r\n  \r\n  if (inHandlerMode()) {\r\n    if (xSemaphoreGiveFromISR(mutex_id, &taskWoken) != pdTRUE) {\r\n      return osErrorOS;\r\n    }\r\n    portEND_SWITCHING_ISR(taskWoken);\r\n  }\r\n  else if (xSemaphoreGive(mutex_id) != pdTRUE) \r\n  {\r\n    result = osErrorOS;\r\n  }\r\n  return result;\r\n}\r\n\r\n/**\r\n* @brief Delete a Mutex\r\n* @param mutex_id  mutex ID obtained by \\ref osMutexCreate.\r\n* @retval  status code that indicates the execution status of the function.\r\n* @note   MUST REMAIN UNCHANGED: \\b osMutexDelete shall be consistent in every CMSIS-RTOS.\r\n*/\r\nosStatus osMutexDelete (osMutexId mutex_id)\r\n{\r\n  if (inHandlerMode()) {\r\n    return osErrorISR;\r\n  }\r\n\r\n  vQueueDelete(mutex_id);\r\n\r\n  return osOK;\r\n}\r\n\r\n/********************  Semaphore Management Functions **************************/\r\n\r\n#if (defined (osFeature_Semaphore)  &&  (osFeature_Semaphore != 0))\r\n\r\n/**\r\n* @brief Create and Initialize a Semaphore object used for managing resources\r\n* @param semaphore_def semaphore definition referenced with \\ref osSemaphore.\r\n* @param count         number of available resources.\r\n* @retval  semaphore ID for reference by other functions or NULL in case of error.\r\n* @note   MUST REMAIN UNCHANGED: \\b osSemaphoreCreate shall be consistent in every CMSIS-RTOS.\r\n*/\r\nosSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count)\r\n{\r\n  (void) semaphore_def;\r\n  osSemaphoreId sema;\r\n  \r\n  if (count == 1) {\r\n    vSemaphoreCreateBinary(sema);\r\n    return sema;\r\n  }\r\n\r\n#if (configUSE_COUNTING_SEMAPHORES == 1 )\t\r\n  return xSemaphoreCreateCounting(count, 0);\r\n#else\r\n  return NULL;\r\n#endif\r\n}\r\n\r\n/**\r\n* @brief Wait until a Semaphore token becomes available\r\n* @param  semaphore_id  semaphore object referenced with \\ref osSemaphore.\r\n* @param  millisec      timeout value or 0 in case of no time-out.\r\n* @retval  number of available tokens, or -1 in case of incorrect parameters.\r\n* @note   MUST REMAIN UNCHANGED: \\b osSemaphoreWait shall be consistent in every CMSIS-RTOS.\r\n*/\r\nint32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec)\r\n{\r\n  TickType_t ticks;\r\n  portBASE_TYPE taskWoken = pdFALSE;  \r\n  \r\n  \r\n  if (semaphore_id == NULL) {\r\n    return osErrorParameter;\r\n  }\r\n  \r\n  ticks = 0;\r\n  if (millisec == osWaitForever) {\r\n    ticks = portMAX_DELAY;\r\n  }\r\n  else if (millisec != 0) {\r\n    ticks = millisec / portTICK_PERIOD_MS;\r\n    if (ticks == 0) {\r\n      ticks = 1;\r\n    }\r\n  }\r\n  \r\n  if (inHandlerMode()) {\r\n    if (xSemaphoreTakeFromISR(semaphore_id, &taskWoken) != pdTRUE) {\r\n      return osErrorOS;\r\n    }\r\n\tportEND_SWITCHING_ISR(taskWoken);\r\n  }  \r\n  else if (xSemaphoreTake(semaphore_id, ticks) != pdTRUE) {\r\n    return osErrorOS;\r\n  }\r\n  \r\n  return osOK;\r\n}\r\n\r\n/**\r\n* @brief Release a Semaphore token\r\n* @param  semaphore_id  semaphore object referenced with \\ref osSemaphore.\r\n* @retval  status code that indicates the execution status of the function.\r\n* @note   MUST REMAIN UNCHANGED: \\b osSemaphoreRelease shall be consistent in every CMSIS-RTOS.\r\n*/\r\nosStatus osSemaphoreRelease (osSemaphoreId semaphore_id)\r\n{\r\n  osStatus result = osOK;\r\n  portBASE_TYPE taskWoken = pdFALSE;\r\n  \r\n  \r\n  if (inHandlerMode()) {\r\n    if (xSemaphoreGiveFromISR(semaphore_id, &taskWoken) != pdTRUE) {\r\n      return osErrorOS;\r\n    }\r\n    portEND_SWITCHING_ISR(taskWoken);\r\n  }\r\n  else {\r\n    if (xSemaphoreGive(semaphore_id) != pdTRUE) {\r\n      result = osErrorOS;\r\n    }\r\n  }\r\n  \r\n  return result;\r\n}\r\n\r\n/**\r\n* @brief Delete a Semaphore\r\n* @param  semaphore_id  semaphore object referenced with \\ref osSemaphore.\r\n* @retval  status code that indicates the execution status of the function.\r\n* @note   MUST REMAIN UNCHANGED: \\b osSemaphoreDelete shall be consistent in every CMSIS-RTOS.\r\n*/\r\nosStatus osSemaphoreDelete (osSemaphoreId semaphore_id)\r\n{\r\n  if (inHandlerMode()) {\r\n    return osErrorISR;\r\n  }\r\n\r\n  vSemaphoreDelete(semaphore_id);\r\n\r\n  return osOK; \r\n}\r\n\r\n#endif    /* Use Semaphores */\r\n\r\n/*******************   Memory Pool Management Functions  ***********************/\r\n\r\n#if (defined (osFeature_Pool)  &&  (osFeature_Pool != 0)) \r\n\r\n//TODO\r\n//This is a primitive and inefficient wrapper around the existing FreeRTOS memory management.\r\n//A better implementation will have to modify heap_x.c!\r\n\r\n\r\ntypedef struct os_pool_cb {\r\n  void *pool;\r\n  uint8_t *markers;\r\n  uint32_t pool_sz;\r\n  uint32_t item_sz;\r\n  uint32_t currentIndex;\r\n} os_pool_cb_t;\r\n\r\n\r\n/**\r\n* @brief Create and Initialize a memory pool\r\n* @param  pool_def      memory pool definition referenced with \\ref osPool.\r\n* @retval  memory pool ID for reference by other functions or NULL in case of error.\r\n* @note   MUST REMAIN UNCHANGED: \\b osPoolCreate shall be consistent in every CMSIS-RTOS.\r\n*/\r\nosPoolId osPoolCreate (const osPoolDef_t *pool_def)\r\n{\r\n  osPoolId thePool;\r\n  int itemSize = 4 * ((pool_def->item_sz + 3) / 4);\r\n  uint32_t i;\r\n  \r\n  /* First have to allocate memory for the pool control block. */\r\n  thePool = pvPortMalloc(sizeof(os_pool_cb_t));\r\n  if (thePool) {\r\n    thePool->pool_sz = pool_def->pool_sz;\r\n    thePool->item_sz = itemSize;\r\n    thePool->currentIndex = 0;\r\n    \r\n    /* Memory for markers */\r\n    thePool->markers = pvPortMalloc(pool_def->pool_sz);\r\n    if (thePool->markers) {\r\n      /* Now allocate the pool itself. */\r\n      thePool->pool = pvPortMalloc(pool_def->pool_sz * itemSize);\r\n      \r\n      if (thePool->pool) {\r\n        for (i = 0; i < pool_def->pool_sz; i++) {\r\n          thePool->markers[i] = 0;\r\n        }\r\n      }\r\n      else {\r\n        vPortFree(thePool->markers);\r\n        vPortFree(thePool);\r\n        thePool = NULL;\r\n      }\r\n    }\r\n    else {\r\n      vPortFree(thePool);\r\n      thePool = NULL;\r\n    }\r\n  }\r\n  \r\n  return thePool;\r\n}\r\n\r\n/**\r\n* @brief Allocate a memory block from a memory pool\r\n* @param pool_id       memory pool ID obtain referenced with \\ref osPoolCreate.\r\n* @retval  address of the allocated memory block or NULL in case of no memory available.\r\n* @note   MUST REMAIN UNCHANGED: \\b osPoolAlloc shall be consistent in every CMSIS-RTOS.\r\n*/\r\nvoid *osPoolAlloc (osPoolId pool_id)\r\n{\r\n  int dummy = 0;\r\n  void *p = NULL;\r\n  uint32_t i;\r\n  uint32_t index;\r\n  \r\n  if (inHandlerMode()) {\r\n    dummy = portSET_INTERRUPT_MASK_FROM_ISR();\r\n  }\r\n  else {\r\n    vPortEnterCritical();\r\n  }\r\n  \r\n  for (i = 0; i < pool_id->pool_sz; i++) {\r\n    index = pool_id->currentIndex + i;\r\n    if (index >= pool_id->pool_sz) {\r\n      index = 0;\r\n    }\r\n    \r\n    if (pool_id->markers[index] == 0) {\r\n      pool_id->markers[index] = 1;\r\n      p = (void *)((uint32_t)(pool_id->pool) + (index * pool_id->item_sz));\r\n      pool_id->currentIndex = index;\r\n      break;\r\n    }\r\n  }\r\n  \r\n  if (inHandlerMode()) {\r\n    portCLEAR_INTERRUPT_MASK_FROM_ISR(dummy);\r\n  }\r\n  else {\r\n    vPortExitCritical();\r\n  }\r\n  \r\n  return p;\r\n}\r\n\r\n/**\r\n* @brief Allocate a memory block from a memory pool and set memory block to zero\r\n* @param  pool_id       memory pool ID obtain referenced with \\ref osPoolCreate.\r\n* @retval  address of the allocated memory block or NULL in case of no memory available.\r\n* @note   MUST REMAIN UNCHANGED: \\b osPoolCAlloc shall be consistent in every CMSIS-RTOS.\r\n*/\r\nvoid *osPoolCAlloc (osPoolId pool_id)\r\n{\r\n  void *p = osPoolAlloc(pool_id);\r\n  \r\n  if (p != NULL)\r\n  {\r\n    memset(p, 0, sizeof(pool_id->pool_sz));\r\n  }\r\n  \r\n  return p;\r\n}\r\n\r\n/**\r\n* @brief Return an allocated memory block back to a specific memory pool\r\n* @param  pool_id       memory pool ID obtain referenced with \\ref osPoolCreate.\r\n* @param  block         address of the allocated memory block that is returned to the memory pool.\r\n* @retval  status code that indicates the execution status of the function.\r\n* @note   MUST REMAIN UNCHANGED: \\b osPoolFree shall be consistent in every CMSIS-RTOS.\r\n*/\r\nosStatus osPoolFree (osPoolId pool_id, void *block)\r\n{\r\n  uint32_t index;\r\n  \r\n  if (pool_id == NULL) {\r\n    return osErrorParameter;\r\n  }\r\n  \r\n  if (block == NULL) {\r\n    return osErrorParameter;\r\n  }\r\n  \r\n  if (block < pool_id->pool) {\r\n    return osErrorParameter;\r\n  }\r\n  \r\n  index = (uint32_t)block - (uint32_t)(pool_id->pool);\r\n  if (index % pool_id->item_sz) {\r\n    return osErrorParameter;\r\n  }\r\n  index = index / pool_id->item_sz;\r\n  if (index >= pool_id->pool_sz) {\r\n    return osErrorParameter;\r\n  }\r\n  \r\n  pool_id->markers[index] = 0;\r\n  \r\n  return osOK;\r\n}\r\n\r\n\r\n#endif   /* Use Memory Pool Management */\r\n\r\n/*******************   Message Queue Management Functions  *********************/\r\n\r\n#if (defined (osFeature_MessageQ)  &&  (osFeature_MessageQ != 0)) /* Use Message Queues */\r\n\r\n/**\r\n* @brief Create and Initialize a Message Queue\r\n* @param queue_def     queue definition referenced with \\ref osMessageQ.\r\n* @param  thread_id     thread ID (obtained by \\ref osThreadCreate or \\ref osThreadGetId) or NULL.\r\n* @retval  message queue ID for reference by other functions or NULL in case of error.\r\n* @note   MUST REMAIN UNCHANGED: \\b osMessageCreate shall be consistent in every CMSIS-RTOS.\r\n*/\r\nosMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id)\r\n{\r\n  (void) thread_id;\r\n  \r\n  return xQueueCreate(queue_def->queue_sz, queue_def->item_sz);\r\n}\r\n\r\n/**\r\n* @brief Put a Message to a Queue.\r\n* @param  queue_id  message queue ID obtained with \\ref osMessageCreate.\r\n* @param  info      message information.\r\n* @param  millisec  timeout value or 0 in case of no time-out.\r\n* @retval status code that indicates the execution status of the function.\r\n* @note   MUST REMAIN UNCHANGED: \\b osMessagePut shall be consistent in every CMSIS-RTOS.\r\n*/\r\nosStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec)\r\n{\r\n  portBASE_TYPE taskWoken = pdFALSE;\r\n  TickType_t ticks;\r\n  \r\n  ticks = millisec / portTICK_PERIOD_MS;\r\n  if (ticks == 0) {\r\n    ticks = 1;\r\n  }\r\n  \r\n  if (inHandlerMode()) {\r\n    if (xQueueSendFromISR(queue_id, &info, &taskWoken) != pdTRUE) {\r\n      return osErrorOS;\r\n    }\r\n    portEND_SWITCHING_ISR(taskWoken);\r\n  }\r\n  else {\r\n    if (xQueueSend(queue_id, &info, ticks) != pdTRUE) {\r\n      return osErrorOS;\r\n    }\r\n  }\r\n  \r\n  return osOK;\r\n}\r\n\r\n/**\r\n* @brief Get a Message or Wait for a Message from a Queue.\r\n* @param  queue_id  message queue ID obtained with \\ref osMessageCreate.\r\n* @param  millisec  timeout value or 0 in case of no time-out.\r\n* @retval event information that includes status code.\r\n* @note   MUST REMAIN UNCHANGED: \\b osMessageGet shall be consistent in every CMSIS-RTOS.\r\n*/\r\nosEvent osMessageGet (osMessageQId queue_id, uint32_t millisec)\r\n{\r\n  portBASE_TYPE taskWoken;\r\n  TickType_t ticks;\r\n  osEvent event;\r\n  \r\n  event.def.message_id = queue_id;\r\n  event.value.v = 0;\r\n  \r\n  if (queue_id == NULL) {\r\n    event.status = osErrorParameter;\r\n    return event;\r\n  }\r\n  \r\n  taskWoken = pdFALSE;\r\n  \r\n  ticks = 0;\r\n  if (millisec == osWaitForever) {\r\n    ticks = portMAX_DELAY;\r\n  }\r\n  else if (millisec != 0) {\r\n    ticks = millisec / portTICK_PERIOD_MS;\r\n    if (ticks == 0) {\r\n      ticks = 1;\r\n    }\r\n  }\r\n  \r\n  if (inHandlerMode()) {\r\n    if (xQueueReceiveFromISR(queue_id, &event.value.v, &taskWoken) == pdTRUE) {\r\n      /* We have mail */\r\n      event.status = osEventMessage;\r\n    }\r\n    else {\r\n      event.status = osOK;\r\n    }\r\n    portEND_SWITCHING_ISR(taskWoken);\r\n  }\r\n  else {\r\n    if (xQueueReceive(queue_id, &event.value.v, ticks) == pdTRUE) {\r\n      /* We have mail */\r\n      event.status = osEventMessage;\r\n    }\r\n    else {\r\n      event.status = (ticks == 0) ? osOK : osEventTimeout;\r\n    }\r\n  }\r\n  \r\n  return event;\r\n}\r\n\r\n#endif     /* Use Message Queues */\r\n\r\n/********************   Mail Queue Management Functions  ***********************/\r\n#if (defined (osFeature_MailQ)  &&  (osFeature_MailQ != 0))  /* Use Mail Queues */\r\n\r\n\r\ntypedef struct os_mailQ_cb {\r\n  const osMailQDef_t *queue_def;\r\n  QueueHandle_t handle;\r\n  osPoolId pool;\r\n} os_mailQ_cb_t;\r\n\r\n/**\r\n* @brief Create and Initialize mail queue\r\n* @param  queue_def     reference to the mail queue definition obtain with \\ref osMailQ\r\n* @param   thread_id     thread ID (obtained by \\ref osThreadCreate or \\ref osThreadGetId) or NULL.\r\n* @retval mail queue ID for reference by other functions or NULL in case of error.\r\n* @note   MUST REMAIN UNCHANGED: \\b osMailCreate shall be consistent in every CMSIS-RTOS.\r\n*/\r\nosMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id)\r\n{\r\n  (void) thread_id;\r\n  \r\n  osPoolDef_t pool_def = {queue_def->queue_sz, queue_def->item_sz};\r\n  \r\n  \r\n  /* Create a mail queue control block */\r\n  *(queue_def->cb) = pvPortMalloc(sizeof(struct os_mailQ_cb));\r\n  if (*(queue_def->cb) == NULL) {\r\n    return NULL;\r\n  }\r\n  (*(queue_def->cb))->queue_def = queue_def;\r\n  \r\n  /* Create a queue in FreeRTOS */\r\n  (*(queue_def->cb))->handle = xQueueCreate(queue_def->queue_sz, sizeof(void *));\r\n  if ((*(queue_def->cb))->handle == NULL) {\r\n    vPortFree(*(queue_def->cb));\r\n    return NULL;\r\n  }\r\n  \r\n  /* Create a mail pool */\r\n  (*(queue_def->cb))->pool = osPoolCreate(&pool_def);\r\n  if ((*(queue_def->cb))->pool == NULL) {\r\n    //TODO: Delete queue. How to do it in FreeRTOS?\r\n    vPortFree(*(queue_def->cb));\r\n    return NULL;\r\n  }\r\n  \r\n  return *(queue_def->cb);\r\n}\r\n\r\n/**\r\n* @brief Allocate a memory block from a mail\r\n* @param  queue_id      mail queue ID obtained with \\ref osMailCreate.\r\n* @param  millisec      timeout value or 0 in case of no time-out.\r\n* @retval pointer to memory block that can be filled with mail or NULL in case error.\r\n* @note   MUST REMAIN UNCHANGED: \\b osMailAlloc shall be consistent in every CMSIS-RTOS.\r\n*/\r\nvoid *osMailAlloc (osMailQId queue_id, uint32_t millisec)\r\n{\r\n  (void) millisec;\r\n  void *p;\r\n  \r\n  \r\n  if (queue_id == NULL) {\r\n    return NULL;\r\n  }\r\n  \r\n  p = osPoolAlloc(queue_id->pool);\r\n  \r\n  return p;\r\n}\r\n\r\n/**\r\n* @brief Allocate a memory block from a mail and set memory block to zero\r\n* @param  queue_id      mail queue ID obtained with \\ref osMailCreate.\r\n* @param  millisec      timeout value or 0 in case of no time-out.\r\n* @retval pointer to memory block that can be filled with mail or NULL in case error.\r\n* @note   MUST REMAIN UNCHANGED: \\b osMailCAlloc shall be consistent in every CMSIS-RTOS.\r\n*/\r\nvoid *osMailCAlloc (osMailQId queue_id, uint32_t millisec)\r\n{\r\n  uint32_t i;\r\n  void *p = osMailAlloc(queue_id, millisec);\r\n  \r\n  if (p) {\r\n    for (i = 0; i < sizeof(queue_id->queue_def->item_sz); i++) {\r\n      ((uint8_t *)p)[i] = 0;\r\n    }\r\n  }\r\n  \r\n  return p;\r\n}\r\n\r\n/**\r\n* @brief Put a mail to a queue\r\n* @param  queue_id      mail queue ID obtained with \\ref osMailCreate.\r\n* @param  mail          memory block previously allocated with \\ref osMailAlloc or \\ref osMailCAlloc.\r\n* @retval status code that indicates the execution status of the function.\r\n* @note   MUST REMAIN UNCHANGED: \\b osMailPut shall be consistent in every CMSIS-RTOS.\r\n*/\r\nosStatus osMailPut (osMailQId queue_id, void *mail)\r\n{\r\n  portBASE_TYPE taskWoken;\r\n  \r\n  \r\n  if (queue_id == NULL) {\r\n    return osErrorParameter;\r\n  }\r\n  \r\n  taskWoken = pdFALSE;\r\n  \r\n  if (inHandlerMode()) {\r\n    if (xQueueSendFromISR(queue_id->handle, &mail, &taskWoken) != pdTRUE) {\r\n      return osErrorOS;\r\n    }\r\n    portEND_SWITCHING_ISR(taskWoken);\r\n  }\r\n  else {\r\n    if (xQueueSend(queue_id->handle, &mail, 0) != pdTRUE) { \r\n      return osErrorOS;\r\n    }\r\n  }\r\n  \r\n  return osOK;\r\n}\r\n\r\n/**\r\n* @brief Get a mail from a queue\r\n* @param  queue_id   mail queue ID obtained with \\ref osMailCreate.\r\n* @param millisec    timeout value or 0 in case of no time-out\r\n* @retval event that contains mail information or error code.\r\n* @note   MUST REMAIN UNCHANGED: \\b osMailGet shall be consistent in every CMSIS-RTOS.\r\n*/\r\nosEvent osMailGet (osMailQId queue_id, uint32_t millisec)\r\n{\r\n  portBASE_TYPE taskWoken;\r\n  TickType_t ticks;\r\n  osEvent event;\r\n  \r\n  event.def.mail_id = queue_id;\r\n  \r\n  if (queue_id == NULL) {\r\n    event.status = osErrorParameter;\r\n    return event;\r\n  }\r\n  \r\n  taskWoken = pdFALSE;\r\n  \r\n  ticks = 0;\r\n  if (millisec == osWaitForever) {\r\n    ticks = portMAX_DELAY;\r\n  }\r\n  else if (millisec != 0) {\r\n    ticks = millisec / portTICK_PERIOD_MS;\r\n    if (ticks == 0) {\r\n      ticks = 1;\r\n    }\r\n  }\r\n  \r\n  if (inHandlerMode()) {\r\n    if (xQueueReceiveFromISR(queue_id->handle, &event.value.p, &taskWoken) == pdTRUE) {\r\n      /* We have mail */\r\n      event.status = osEventMail;\r\n    }\r\n    else {\r\n      event.status = osOK;\r\n    }\r\n    portEND_SWITCHING_ISR(taskWoken);\r\n  }\r\n  else {\r\n    if (xQueueReceive(queue_id->handle, &event.value.p, ticks) == pdTRUE) {\r\n      /* We have mail */\r\n      event.status = osEventMail;\r\n    }\r\n    else {\r\n      event.status = (ticks == 0) ? osOK : osEventTimeout;\r\n    }\r\n  }\r\n  \r\n  return event;\r\n}\r\n\r\n/**\r\n* @brief Free a memory block from a mail\r\n* @param  queue_id mail queue ID obtained with \\ref osMailCreate.\r\n* @param  mail     pointer to the memory block that was obtained with \\ref osMailGet.\r\n* @retval status code that indicates the execution status of the function.\r\n* @note   MUST REMAIN UNCHANGED: \\b osMailFree shall be consistent in every CMSIS-RTOS.\r\n*/\r\nosStatus osMailFree (osMailQId queue_id, void *mail)\r\n{\r\n  if (queue_id == NULL) {\r\n    return osErrorParameter;\r\n  }\r\n  \r\n  return osPoolFree(queue_id->pool, mail);\r\n}\r\n#endif  /* Use Mail Queues */\r\n\r\n/*************************** Additional specific APIs to Free RTOS ************/\r\n/**\r\n* @brief  Handles the tick increment\r\n* @param  none.\r\n* @retval none.\r\n*/\r\nvoid osSystickHandler(void)\r\n{\r\n\r\n#if (INCLUDE_xTaskGetSchedulerState  == 1 )\r\n  if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED)\r\n  {\r\n#endif  /* INCLUDE_xTaskGetSchedulerState */  \r\n    xPortSysTickHandler();\r\n#if (INCLUDE_xTaskGetSchedulerState  == 1 )\r\n  }\r\n#endif  /* INCLUDE_xTaskGetSchedulerState */  \r\n}\r\n\r\n#if ( INCLUDE_eTaskGetState == 1 )\r\n/**\r\n* @brief  Obtain the state of any thread.\r\n* @param   thread_id   thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\r\n* @retval  the stae of the thread, states are encoded by the osThreadState enumerated type.\r\n*/\r\nosThreadState osThreadGetState(osThreadId thread_id)\r\n{\r\n  eTaskState ThreadState;\r\n  osThreadState result;\r\n  \r\n  ThreadState = eTaskGetState(thread_id);\r\n  \r\n  switch (ThreadState)\r\n  {\r\n  case eRunning :\r\n    result = osThreadRunning;\r\n    break;\r\n  case eReady :\r\n    result = osThreadReady;\r\n    break;\r\n  case eBlocked :\r\n    result = osThreadBlocked;\r\n    break;\r\n  case eSuspended :\r\n    result = osThreadSuspended;\r\n    break;\r\n  case eDeleted :\r\n    result = osThreadDeleted;\r\n    break;\r\n  default:\r\n    result = osThreadError;\r\n  } \r\n  \r\n  return result;\r\n}\r\n#endif /* INCLUDE_eTaskGetState */\r\n\r\n#if (INCLUDE_eTaskGetState == 1)\r\n/**\r\n* @brief Check if a thread is already suspended or not.\r\n* @param thread_id thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\r\n* @retval status code that indicates the execution status of the function.\r\n*/\r\nosStatus osThreadIsSuspended(osThreadId thread_id)\r\n{\r\n  if (eTaskGetState(thread_id) == eSuspended)\r\n    return osOK;\r\n  else\r\n    return osErrorOS;\r\n}\r\n#endif /* INCLUDE_eTaskGetState */\r\n/**\r\n* @brief  Suspend execution of a thread.\r\n* @param   thread_id   thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\r\n* @retval  status code that indicates the execution status of the function.\r\n*/\r\nosStatus osThreadSuspend (osThreadId thread_id)\r\n{\r\n#if (INCLUDE_vTaskSuspend == 1)\r\n    vTaskSuspend(thread_id);\r\n  \r\n  return osOK;\r\n#else\r\n  return osErrorResource;\r\n#endif\r\n}\r\n\r\n/**\r\n* @brief  Resume execution of a suspended thread.\r\n* @param   thread_id   thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\r\n* @retval  status code that indicates the execution status of the function.\r\n*/\r\nosStatus osThreadResume (osThreadId thread_id)\r\n{\r\n#if (INCLUDE_vTaskSuspend == 1)  \r\n  if(inHandlerMode())\r\n  {\r\n    if (xTaskResumeFromISR(thread_id) == pdTRUE)\r\n    {\r\n      portYIELD_FROM_ISR(pdTRUE);\r\n    }\r\n  }\r\n  else\r\n  {\r\n    vTaskResume(thread_id);\r\n  }\r\n  return osOK;\r\n#else\r\n  return osErrorResource;\r\n#endif\r\n}\r\n\r\n/**\r\n* @brief  Suspend execution of a all active threads.\r\n* @retval  status code that indicates the execution status of the function.\r\n*/\r\nosStatus osThreadSuspendAll (void)\r\n{\r\n  vTaskSuspendAll();\r\n  \r\n  return osOK;\r\n}\r\n\r\n/**\r\n* @brief  Resume execution of a all suspended threads.\r\n* @retval  status code that indicates the execution status of the function.\r\n*/\r\nosStatus osThreadResumeAll (void)\r\n{\r\n  if (xTaskResumeAll() == pdTRUE)\r\n    return osOK;\r\n  else\r\n    return osErrorOS;\r\n  \r\n}\r\n\r\n/**\r\n* @brief  Delay a task until a specified time\r\n* @param   PreviousWakeTime   Pointer to a variable that holds the time at which the \r\n*          task was last unblocked. PreviousWakeTime must be initialised with the current time\r\n*          prior to its first use (PreviousWakeTime = osKernelSysTick() )\r\n* @param   millisec    time delay value\r\n* @retval  status code that indicates the execution status of the function.\r\n*/\r\nosStatus osDelayUntil (uint32_t *PreviousWakeTime, uint32_t millisec)\r\n{\r\n#if INCLUDE_vTaskDelayUntil\r\n  TickType_t ticks = (millisec / portTICK_PERIOD_MS);\r\n  vTaskDelayUntil((TickType_t *) PreviousWakeTime, ticks ? ticks : 1);\r\n  \r\n  return osOK;\r\n#else\r\n  (void) millisec;\r\n  (void) PreviousWakeTime;\r\n  \r\n  return osErrorResource;\r\n#endif\r\n}\r\n\r\n/**\r\n* @brief   Lists all the current threads, along with their current state \r\n*          and stack usage high water mark.\r\n* @param   buffer   A buffer into which the above mentioned details\r\n*          will be written\r\n* @retval  status code that indicates the execution status of the function.\r\n*/\r\nosStatus osThreadList (uint8_t *buffer)\r\n{\r\n#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) )\r\n  vTaskList((char *)buffer);\r\n#endif\r\n  return osOK;\r\n}\r\n\r\n/**\r\n* @brief  Receive an item from a queue without removing the item from the queue.\r\n* @param  queue_id  message queue ID obtained with \\ref osMessageCreate.\r\n* @param  millisec  timeout value or 0 in case of no time-out.\r\n* @retval event information that includes status code.\r\n*/\r\nosEvent osMessagePeek (osMessageQId queue_id, uint32_t millisec)\r\n{\r\n  TickType_t ticks;\r\n  osEvent event;\r\n  \r\n  event.def.message_id = queue_id;\r\n  \r\n  if (queue_id == NULL) {\r\n    event.status = osErrorParameter;\r\n    return event;\r\n  }\r\n  \r\n  ticks = 0;\r\n  if (millisec == osWaitForever) {\r\n    ticks = portMAX_DELAY;\r\n  }\r\n  else if (millisec != 0) {\r\n    ticks = millisec / portTICK_PERIOD_MS;\r\n    if (ticks == 0) {\r\n      ticks = 1;\r\n    }\r\n  }\r\n  \r\n  if (xQueuePeek(queue_id, &event.value.v, ticks) == pdTRUE) \r\n  {\r\n    /* We have mail */\r\n    event.status = osEventMessage;\r\n  }\r\n  else \r\n  {\r\n    event.status = (ticks == 0) ? osOK : osEventTimeout;\r\n  }\r\n  \r\n  return event;\r\n}\r\n\r\n/**\r\n* @brief  Create and Initialize a Recursive Mutex\r\n* @param  mutex_def     mutex definition referenced with \\ref osMutex.\r\n* @retval  mutex ID for reference by other functions or NULL in case of error..\r\n*/\r\nosMutexId osRecursiveMutexCreate (const osMutexDef_t *mutex_def)\r\n{\r\n  (void) mutex_def;\r\n#if (configUSE_RECURSIVE_MUTEXES == 1)\r\n  return xSemaphoreCreateRecursiveMutex();\r\n#else\r\n  return NULL;\r\n#endif\t\r\n}\r\n\r\n/**\r\n* @brief  Release a Recursive Mutex\r\n* @param   mutex_id      mutex ID obtained by \\ref osRecursiveMutexCreate.\r\n* @retval  status code that indicates the execution status of the function.\r\n*/\r\nosStatus osRecursiveMutexRelease (osMutexId mutex_id)\r\n{\r\n#if (configUSE_RECURSIVE_MUTEXES == 1)\r\n  osStatus result = osOK;\r\n \r\n  if (xSemaphoreGiveRecursive(mutex_id) != pdTRUE) \r\n  {\r\n    result = osErrorOS;\r\n  }\r\n  return result;\r\n#else\r\n\treturn osErrorResource;\r\n#endif\r\n}\r\n\r\n/**\r\n* @brief  Release a Recursive Mutex\r\n* @param   mutex_id    mutex ID obtained by \\ref osRecursiveMutexCreate.\r\n* @param millisec      timeout value or 0 in case of no time-out.\r\n* @retval  status code that indicates the execution status of the function.\r\n*/\r\nosStatus osRecursiveMutexWait (osMutexId mutex_id, uint32_t millisec)\r\n{\r\n#if (configUSE_RECURSIVE_MUTEXES == 1)\r\n  TickType_t ticks;\r\n  \r\n  if (mutex_id == NULL)\r\n  {\r\n    return osErrorParameter;\r\n  }\r\n  \r\n  ticks = 0;\r\n  if (millisec == osWaitForever) \r\n  {\r\n    ticks = portMAX_DELAY;\r\n  }\r\n  else if (millisec != 0) \r\n  {\r\n    ticks = millisec / portTICK_PERIOD_MS;\r\n    if (ticks == 0) \r\n    {\r\n      ticks = 1;\r\n    }\r\n  }\r\n  \r\n  if (xSemaphoreTakeRecursive(mutex_id, ticks) != pdTRUE) \r\n  {\r\n    return osErrorOS;\r\n  }\r\n  return osOK;\r\n#else\r\n\treturn osErrorResource;\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RTOS/src/cmsis_os.h",
    "content": "/* ----------------------------------------------------------------------\r\n * $Date:        5. February 2013\r\n * $Revision:    V1.02\r\n *\r\n * Project:      CMSIS-RTOS API\r\n * Title:        cmsis_os.h header file\r\n *\r\n * Version 0.02\r\n *    Initial Proposal Phase\r\n * Version 0.03\r\n *    osKernelStart added, optional feature: main started as thread\r\n *    osSemaphores have standard behavior\r\n *    osTimerCreate does not start the timer, added osTimerStart\r\n *    osThreadPass is renamed to osThreadYield\r\n * Version 1.01\r\n *    Support for C++ interface\r\n *     - const attribute removed from the osXxxxDef_t typedef's\r\n *     - const attribute added to the osXxxxDef macros\r\n *    Added: osTimerDelete, osMutexDelete, osSemaphoreDelete\r\n *    Added: osKernelInitialize\r\n * Version 1.02\r\n *    Control functions for short timeouts in microsecond resolution:\r\n *    Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec\r\n *    Removed: osSignalGet \r\n *    \r\n *  \r\n *----------------------------------------------------------------------------\r\n *\r\n * Portions COPYRIGHT 2015 STMicroelectronics\r\n * Portions Copyright (c) 2013 ARM LIMITED\r\n * All rights reserved.\r\n * Redistribution and use in source and binary forms, with or without\r\n * modification, are permitted provided that the following conditions are met:\r\n *  - Redistributions of source code must retain the above copyright\r\n *    notice, this list of conditions and the following disclaimer.\r\n *  - Redistributions in binary form must reproduce the above copyright\r\n *    notice, this list of conditions and the following disclaimer in the\r\n *    documentation and/or other materials provided with the distribution.\r\n *  - Neither the name of ARM  nor the names of its contributors may be used\r\n *    to endorse or promote products derived from this software without\r\n *    specific prior written permission.\r\n *\r\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r\n * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n * POSSIBILITY OF SUCH DAMAGE.\r\n *---------------------------------------------------------------------------*/\r\n\r\n /**\r\n  ******************************************************************************\r\n  * @file    cmsis_os.h\r\n  * @author  MCD Application Team\r\n  * @date    27-March-2015\r\n  * @brief   Header of cmsis_os.c\r\n  *          A new set of APIs are added in addition to existing ones, these APIs \r\n  *          are specific to FreeRTOS.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n #if   defined ( __CC_ARM )\r\n  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */\r\n  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */\r\n  #define __STATIC_INLINE  static __inline\r\n#elif defined ( __ICCARM__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */\r\n  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r\n  #define __STATIC_INLINE  static inline\r\n#elif defined ( __GNUC__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */\r\n  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */\r\n  #define __STATIC_INLINE  static inline\r\n#endif\r\n\r\n#include <stdint.h>\r\n#include <stddef.h>\r\n#include \"core_cmFunc.h\"\r\n\t\r\n#include \"FreeRTOS.h\"\r\n#include \"task.h\"\r\n#include \"timers.h\"\r\n#include \"queue.h\"\r\n#include \"semphr.h\"\r\n#include \"event_groups.h\"\r\n\r\n/**\r\n\\page cmsis_os_h Header File Template: cmsis_os.h\r\n\r\nThe file \\b cmsis_os.h is a template header file for a CMSIS-RTOS compliant Real-Time Operating System (RTOS).\r\nEach RTOS that is compliant with CMSIS-RTOS shall provide a specific \\b cmsis_os.h header file that represents\r\nits implementation.\r\n\r\nThe file cmsis_os.h contains:\r\n - CMSIS-RTOS API function definitions\r\n - struct definitions for parameters and return types\r\n - status and priority values used by CMSIS-RTOS API functions\r\n - macros for defining threads and other kernel objects\r\n\r\n\r\n<b>Name conventions and header file modifications</b>\r\n\r\nAll definitions are prefixed with \\b os to give an unique name space for CMSIS-RTOS functions.\r\nDefinitions that are prefixed \\b os_ are not used in the application code but local to this header file.\r\nAll definitions and functions that belong to a module are grouped and have a common prefix, i.e. \\b osThread.\r\n\r\nDefinitions that are marked with <b>CAN BE CHANGED</b> can be adapted towards the needs of the actual CMSIS-RTOS implementation.\r\nThese definitions can be specific to the underlying RTOS kernel.\r\n\r\nDefinitions that are marked with <b>MUST REMAIN UNCHANGED</b> cannot be altered. Otherwise the CMSIS-RTOS implementation is no longer\r\ncompliant to the standard. Note that some functions are optional and need not to be provided by every CMSIS-RTOS implementation.\r\n\r\n\r\n<b>Function calls from interrupt service routines</b>\r\n\r\nThe following CMSIS-RTOS functions can be called from threads and interrupt service routines (ISR):\r\n  - \\ref osSignalSet\r\n  - \\ref osSemaphoreRelease\r\n  - \\ref osPoolAlloc, \\ref osPoolCAlloc, \\ref osPoolFree\r\n  - \\ref osMessagePut, \\ref osMessageGet\r\n  - \\ref osMailAlloc, \\ref osMailCAlloc, \\ref osMailGet, \\ref osMailPut, \\ref osMailFree\r\n\r\nFunctions that cannot be called from an ISR are verifying the interrupt status and return in case that they are called\r\nfrom an ISR context the status code \\b osErrorISR. In some implementations this condition might be caught using the HARD FAULT vector.\r\n\r\nSome CMSIS-RTOS implementations support CMSIS-RTOS function calls from multiple ISR at the same time.\r\nIf this is impossible, the CMSIS-RTOS rejects calls by nested ISR functions with the status code \\b osErrorISRRecursive.\r\n\r\n\r\n<b>Define and reference object definitions</b>\r\n\r\nWith <b>\\#define osObjectsExternal</b> objects are defined as external symbols. This allows to create a consistent header file\r\nthat is used throughout a project as shown below:\r\n\r\n<i>Header File</i>\r\n\\code\r\n#include <cmsis_os.h>                                         // CMSIS RTOS header file\r\n\r\n// Thread definition\r\nextern void thread_sample (void const *argument);             // function prototype\r\nosThreadDef (thread_sample, osPriorityBelowNormal, 1, 100);\r\n\r\n// Pool definition\r\nosPoolDef(MyPool, 10, long);\r\n\\endcode\r\n\r\n\r\nThis header file defines all objects when included in a C/C++ source file. When <b>\\#define osObjectsExternal</b> is\r\npresent before the header file, the objects are defined as external symbols. A single consistent header file can therefore be\r\nused throughout the whole project.\r\n\r\n<i>Example</i>\r\n\\code\r\n#include \"osObjects.h\"     // Definition of the CMSIS-RTOS objects\r\n\\endcode\r\n\r\n\\code\r\n#define osObjectExternal   // Objects will be defined as external symbols\r\n#include \"osObjects.h\"     // Reference to the CMSIS-RTOS objects\r\n\\endcode\r\n\r\n*/\r\n\r\n#ifndef _CMSIS_OS_H\r\n#define _CMSIS_OS_H\r\n\r\n/// \\note MUST REMAIN UNCHANGED: \\b osCMSIS identifies the CMSIS-RTOS API version.\r\n#define osCMSIS           0x10002      ///< API version (main [31:16] .sub [15:0])\r\n\r\n/// \\note CAN BE CHANGED: \\b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number.\r\n#define osCMSIS_KERNEL    0x10000\t   ///< RTOS identification and version (main [31:16] .sub [15:0])\r\n\r\n/// \\note MUST REMAIN UNCHANGED: \\b osKernelSystemId shall be consistent in every CMSIS-RTOS.\r\n#define osKernelSystemId \"KERNEL V1.00\"   ///< RTOS identification string\r\n\r\n/// \\note MUST REMAIN UNCHANGED: \\b osFeature_xxx shall be consistent in every CMSIS-RTOS.\r\n#define osFeature_MainThread   1       ///< main thread      1=main can be thread, 0=not available\r\n#define osFeature_Pool         1       ///< Memory Pools:    1=available, 0=not available\r\n#define osFeature_MailQ        1       ///< Mail Queues:     1=available, 0=not available\r\n#define osFeature_MessageQ     1       ///< Message Queues:  1=available, 0=not available\r\n#define osFeature_Signals      8       ///< maximum number of Signal Flags available per thread\r\n#define osFeature_Semaphore    1      ///< osFeature_Semaphore function: 1=available, 0=not available\r\n#define osFeature_Wait         0       ///< osWait function: 1=available, 0=not available\r\n#define osFeature_SysTick      1       ///< osKernelSysTick functions: 1=available, 0=not available\r\n\r\n#ifdef  __cplusplus\r\nextern \"C\"\r\n{\r\n#endif\r\n\r\n\r\n// ==== Enumeration, structures, defines ====\r\n\r\n/// Priority used for thread control.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osPriority shall be consistent in every CMSIS-RTOS.\r\ntypedef enum  {\r\n  osPriorityIdle          = -3,          ///< priority: idle (lowest)\r\n  osPriorityLow           = -2,          ///< priority: low\r\n  osPriorityBelowNormal   = -1,          ///< priority: below normal\r\n  osPriorityNormal        =  0,          ///< priority: normal (default)\r\n  osPriorityAboveNormal   = +1,          ///< priority: above normal\r\n  osPriorityHigh          = +2,          ///< priority: high\r\n  osPriorityRealtime      = +3,          ///< priority: realtime (highest)\r\n  osPriorityError         =  0x84        ///< system cannot determine priority or thread has illegal priority\r\n} osPriority;\r\n\r\n/// Timeout value.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osWaitForever shall be consistent in every CMSIS-RTOS.\r\n#define osWaitForever     0xFFFFFFFF     ///< wait forever timeout value\r\n\r\n/// Status code values returned by CMSIS-RTOS functions.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osStatus shall be consistent in every CMSIS-RTOS.\r\ntypedef enum  {\r\n  osOK                    =     0,       ///< function completed; no error or event occurred.\r\n  osEventSignal           =  0x08,       ///< function completed; signal event occurred.\r\n  osEventMessage          =  0x10,       ///< function completed; message event occurred.\r\n  osEventMail             =  0x20,       ///< function completed; mail event occurred.\r\n  osEventTimeout          =  0x40,       ///< function completed; timeout occurred.\r\n  osErrorParameter        =  0x80,       ///< parameter error: a mandatory parameter was missing or specified an incorrect object.\r\n  osErrorResource         =  0x81,       ///< resource not available: a specified resource was not available.\r\n  osErrorTimeoutResource  =  0xC1,       ///< resource not available within given time: a specified resource was not available within the timeout period.\r\n  osErrorISR              =  0x82,       ///< not allowed in ISR context: the function cannot be called from interrupt service routines.\r\n  osErrorISRRecursive     =  0x83,       ///< function called multiple times from ISR with same object.\r\n  osErrorPriority         =  0x84,       ///< system cannot determine priority or thread has illegal priority.\r\n  osErrorNoMemory         =  0x85,       ///< system is out of memory: it was impossible to allocate or reserve memory for the operation.\r\n  osErrorValue            =  0x86,       ///< value of a parameter is out of range.\r\n  osErrorOS               =  0xFF,       ///< unspecified RTOS error: run-time error but no other error message fits.\r\n  os_status_reserved      =  0x7FFFFFFF  ///< prevent from enum down-size compiler optimization.\r\n} osStatus;\r\n\r\n#if ( INCLUDE_eTaskGetState == 1 )\r\n/* Thread state returned by osThreadGetState */\r\ntypedef enum {\r\n\tosThreadRunning   = 0x0,\t      /* A thread is querying the state of itself, so must be running. */\r\n\tosThreadReady     = 0x1 ,\t\t\t        /* The thread being queried is in a read or pending ready list. */\r\n\tosThreadBlocked   = 0x2,\t\t        /* The thread being queried is in the Blocked state. */\r\n\tosThreadSuspended = 0x3,\t      /* The thread being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */\r\n\tosThreadDeleted   = 0x4,\t\t          /* The thread being queried has been deleted, but its TCB has not yet been freed. */   \r\n  osThreadError     = 0x7FFFFFFF\r\n} osThreadState;\r\n#endif /* INCLUDE_eTaskGetState */\r\n\r\n/// Timer type value for the timer definition.\r\n/// \\note MUST REMAIN UNCHANGED: \\b os_timer_type shall be consistent in every CMSIS-RTOS.\r\ntypedef enum  {\r\n  osTimerOnce             =     0,       ///< one-shot timer\r\n  osTimerPeriodic         =     1        ///< repeating timer\r\n} os_timer_type;\r\n\r\n/// Entry point of a thread.\r\n/// \\note MUST REMAIN UNCHANGED: \\b os_pthread shall be consistent in every CMSIS-RTOS.\r\ntypedef void (*os_pthread) (void const *argument);\r\n\r\n/// Entry point of a timer call back function.\r\n/// \\note MUST REMAIN UNCHANGED: \\b os_ptimer shall be consistent in every CMSIS-RTOS.\r\ntypedef void (*os_ptimer) (void const *argument);\r\n\r\n// >>> the following data type definitions may shall adapted towards a specific RTOS\r\n\r\n/// Thread ID identifies the thread (pointer to a thread control block).\r\n/// \\note CAN BE CHANGED: \\b os_thread_cb is implementation specific in every CMSIS-RTOS.\r\ntypedef TaskHandle_t osThreadId;\r\n\r\n/// Timer ID identifies the timer (pointer to a timer control block).\r\n/// \\note CAN BE CHANGED: \\b os_timer_cb is implementation specific in every CMSIS-RTOS.\r\ntypedef TimerHandle_t osTimerId;\r\n\r\n/// Mutex ID identifies the mutex (pointer to a mutex control block).\r\n/// \\note CAN BE CHANGED: \\b os_mutex_cb is implementation specific in every CMSIS-RTOS.\r\ntypedef SemaphoreHandle_t osMutexId;\r\n\r\n/// Semaphore ID identifies the semaphore (pointer to a semaphore control block).\r\n/// \\note CAN BE CHANGED: \\b os_semaphore_cb is implementation specific in every CMSIS-RTOS.\r\ntypedef SemaphoreHandle_t osSemaphoreId;\r\n\r\n/// Pool ID identifies the memory pool (pointer to a memory pool control block).\r\n/// \\note CAN BE CHANGED: \\b os_pool_cb is implementation specific in every CMSIS-RTOS.\r\ntypedef struct os_pool_cb *osPoolId;\r\n\r\n/// Message ID identifies the message queue (pointer to a message queue control block).\r\n/// \\note CAN BE CHANGED: \\b os_messageQ_cb is implementation specific in every CMSIS-RTOS.\r\ntypedef QueueHandle_t osMessageQId;\r\n\r\n/// Mail ID identifies the mail queue (pointer to a mail queue control block).\r\n/// \\note CAN BE CHANGED: \\b os_mailQ_cb is implementation specific in every CMSIS-RTOS.\r\ntypedef struct os_mailQ_cb *osMailQId;\r\n\r\n\r\n/// Thread Definition structure contains startup information of a thread.\r\n/// \\note CAN BE CHANGED: \\b os_thread_def is implementation specific in every CMSIS-RTOS.\r\ntypedef struct os_thread_def  {\r\n  char                   *name;        ///< Thread name \r\n  os_pthread             pthread;      ///< start address of thread function\r\n  osPriority             tpriority;    ///< initial thread priority\r\n  uint32_t               instances;    ///< maximum number of instances of that thread function\r\n  uint32_t               stacksize;    ///< stack size requirements in bytes; 0 is default stack size\r\n} osThreadDef_t;\r\n\r\n/// Timer Definition structure contains timer parameters.\r\n/// \\note CAN BE CHANGED: \\b os_timer_def is implementation specific in every CMSIS-RTOS.\r\ntypedef struct os_timer_def  {\r\n  os_ptimer                 ptimer;    ///< start address of a timer function\r\n} osTimerDef_t;\r\n\r\n/// Mutex Definition structure contains setup information for a mutex.\r\n/// \\note CAN BE CHANGED: \\b os_mutex_def is implementation specific in every CMSIS-RTOS.\r\ntypedef struct os_mutex_def  {\r\n  uint32_t                   dummy;    ///< dummy value.\r\n} osMutexDef_t;\r\n\r\n/// Semaphore Definition structure contains setup information for a semaphore.\r\n/// \\note CAN BE CHANGED: \\b os_semaphore_def is implementation specific in every CMSIS-RTOS.\r\ntypedef struct os_semaphore_def  {\r\n  uint32_t                   dummy;    ///< dummy value.\r\n} osSemaphoreDef_t;\r\n\r\n/// Definition structure for memory block allocation.\r\n/// \\note CAN BE CHANGED: \\b os_pool_def is implementation specific in every CMSIS-RTOS.\r\ntypedef struct os_pool_def  {\r\n  uint32_t                 pool_sz;    ///< number of items (elements) in the pool\r\n  uint32_t                 item_sz;    ///< size of an item\r\n  void                       *pool;    ///< pointer to memory for pool\r\n} osPoolDef_t;\r\n\r\n/// Definition structure for message queue.\r\n/// \\note CAN BE CHANGED: \\b os_messageQ_def is implementation specific in every CMSIS-RTOS.\r\ntypedef struct os_messageQ_def  {\r\n  uint32_t                queue_sz;    ///< number of elements in the queue\r\n  uint32_t                 item_sz;    ///< size of an item\r\n  //void                       *pool;    ///< memory array for messages\r\n} osMessageQDef_t;\r\n\r\n/// Definition structure for mail queue.\r\n/// \\note CAN BE CHANGED: \\b os_mailQ_def is implementation specific in every CMSIS-RTOS.\r\ntypedef struct os_mailQ_def  {\r\n  uint32_t                queue_sz;    ///< number of elements in the queue\r\n  uint32_t                 item_sz;    ///< size of an item\r\n  struct os_mailQ_cb **cb;\r\n} osMailQDef_t;\r\n\r\n/// Event structure contains detailed information about an event.\r\n/// \\note MUST REMAIN UNCHANGED: \\b os_event shall be consistent in every CMSIS-RTOS.\r\n///       However the struct may be extended at the end.\r\ntypedef struct  {\r\n  osStatus                 status;     ///< status code: event or error information\r\n  union  {\r\n    uint32_t                    v;     ///< message as 32-bit value\r\n    void                       *p;     ///< message or mail as void pointer\r\n    int32_t               signals;     ///< signal flags\r\n  } value;                             ///< event value\r\n  union  {\r\n    osMailQId             mail_id;     ///< mail id obtained by \\ref osMailCreate\r\n    osMessageQId       message_id;     ///< message id obtained by \\ref osMessageCreate\r\n  } def;                               ///< event definition\r\n} osEvent;\r\n\r\n\r\n//  ==== Kernel Control Functions ====\r\n\r\n/// Initialize the RTOS Kernel for creating objects.\r\n/// \\return status code that indicates the execution status of the function.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osKernelInitialize shall be consistent in every CMSIS-RTOS.\r\nosStatus osKernelInitialize (void);\r\n\r\n/// Start the RTOS Kernel.\r\n/// \\return status code that indicates the execution status of the function.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osKernelStart shall be consistent in every CMSIS-RTOS.\r\nosStatus osKernelStart (void);\r\n\r\n/// Check if the RTOS kernel is already started.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osKernelRunning shall be consistent in every CMSIS-RTOS.\r\n/// \\return 0 RTOS is not started, 1 RTOS is started.\r\nint32_t osKernelRunning(void);\r\n\r\n#if (defined (osFeature_SysTick)  &&  (osFeature_SysTick != 0))     // System Timer available\r\n\r\n/// Get the RTOS kernel system timer counter \r\n/// \\note MUST REMAIN UNCHANGED: \\b osKernelSysTick shall be consistent in every CMSIS-RTOS.\r\n/// \\return RTOS kernel system timer as 32-bit value \r\nuint32_t osKernelSysTick (void);\r\n\r\n/// The RTOS kernel system timer frequency in Hz\r\n/// \\note Reflects the system timer setting and is typically defined in a configuration file.\r\n#define osKernelSysTickFrequency      (configTICK_RATE_HZ)\r\n\r\n/// Convert a microseconds value to a RTOS kernel system timer value.\r\n/// \\param         microsec     time value in microseconds.\r\n/// \\return time value normalized to the \\ref osKernelSysTickFrequency\r\n#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)\r\n\r\n#endif    // System Timer available\r\n\r\n//  ==== Thread Management ====\r\n\r\n/// Create a Thread Definition with function, priority, and stack requirements.\r\n/// \\param         name         name of the thread function.\r\n/// \\param         priority     initial priority of the thread function.\r\n/// \\param         instances    number of possible thread instances.\r\n/// \\param         stacksz      stack size (in bytes) requirements for the thread function.\r\n/// \\note CAN BE CHANGED: The parameters to \\b osThreadDef shall be consistent but the\r\n///       macro body is implementation specific in every CMSIS-RTOS.\r\n#if defined (osObjectsExternal)  // object is external\r\n#define osThreadDef(name, thread, priority, instances, stacksz)  \\\r\nextern const osThreadDef_t os_thread_def_##name\r\n#else                            // define the object\r\n#define osThreadDef(name, thread, priority, instances, stacksz)  \\\r\nconst osThreadDef_t os_thread_def_##name = \\\r\n{ #name, (thread), (priority), (instances), (stacksz)  }\r\n#endif\r\n\r\n/// Access a Thread definition.\r\n/// \\param         name          name of the thread definition object.\r\n/// \\note CAN BE CHANGED: The parameter to \\b osThread shall be consistent but the\r\n///       macro body is implementation specific in every CMSIS-RTOS.\r\n#define osThread(name)  \\\r\n&os_thread_def_##name\r\n\r\n/// Create a thread and add it to Active Threads and set it to state READY.\r\n/// \\param[in]     thread_def    thread definition referenced with \\ref osThread.\r\n/// \\param[in]     argument      pointer that is passed to the thread function as start argument.\r\n/// \\return thread ID for reference by other functions or NULL in case of error.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osThreadCreate shall be consistent in every CMSIS-RTOS.\r\nosThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument);\r\n\r\n/// Return the thread ID of the current running thread.\r\n/// \\return thread ID for reference by other functions or NULL in case of error.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osThreadGetId shall be consistent in every CMSIS-RTOS.\r\nosThreadId osThreadGetId (void);\r\n\r\n/// Terminate execution of a thread and remove it from Active Threads.\r\n/// \\param[in]     thread_id   thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\r\n/// \\return status code that indicates the execution status of the function.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osThreadTerminate shall be consistent in every CMSIS-RTOS.\r\nosStatus osThreadTerminate (osThreadId thread_id);\r\n\r\n/// Pass control to next thread that is in state \\b READY.\r\n/// \\return status code that indicates the execution status of the function.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osThreadYield shall be consistent in every CMSIS-RTOS.\r\nosStatus osThreadYield (void);\r\n\r\n/// Change priority of an active thread.\r\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\r\n/// \\param[in]     priority      new priority value for the thread function.\r\n/// \\return status code that indicates the execution status of the function.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osThreadSetPriority shall be consistent in every CMSIS-RTOS.\r\nosStatus osThreadSetPriority (osThreadId thread_id, osPriority priority);\r\n\r\n/// Get current priority of an active thread.\r\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\r\n/// \\return current priority value of the thread function.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osThreadGetPriority shall be consistent in every CMSIS-RTOS.\r\nosPriority osThreadGetPriority (osThreadId thread_id);\r\n\r\n\r\n//  ==== Generic Wait Functions ====\r\n\r\n/// Wait for Timeout (Time Delay).\r\n/// \\param[in]     millisec      time delay value\r\n/// \\return status code that indicates the execution status of the function.\r\nosStatus osDelay (uint32_t millisec);\r\n\r\n#if (defined (osFeature_Wait)  &&  (osFeature_Wait != 0))     // Generic Wait available\r\n\r\n/// Wait for Signal, Message, Mail, or Timeout.\r\n/// \\param[in] millisec          timeout value or 0 in case of no time-out\r\n/// \\return event that contains signal, message, or mail information or error code.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osWait shall be consistent in every CMSIS-RTOS.\r\nosEvent osWait (uint32_t millisec);\r\n\r\n#endif  // Generic Wait available\r\n\r\n\r\n//  ==== Timer Management Functions ====\r\n/// Define a Timer object.\r\n/// \\param         name          name of the timer object.\r\n/// \\param         function      name of the timer call back function.\r\n/// \\note CAN BE CHANGED: The parameter to \\b osTimerDef shall be consistent but the\r\n///       macro body is implementation specific in every CMSIS-RTOS.\r\n#if defined (osObjectsExternal)  // object is external\r\n#define osTimerDef(name, function)  \\\r\nextern const osTimerDef_t os_timer_def_##name\r\n#else                            // define the object\r\n#define osTimerDef(name, function)  \\\r\nconst osTimerDef_t os_timer_def_##name = \\\r\n{ (function) }\r\n#endif\r\n\r\n/// Access a Timer definition.\r\n/// \\param         name          name of the timer object.\r\n/// \\note CAN BE CHANGED: The parameter to \\b osTimer shall be consistent but the\r\n///       macro body is implementation specific in every CMSIS-RTOS.\r\n#define osTimer(name) \\\r\n&os_timer_def_##name\r\n\r\n/// Create a timer.\r\n/// \\param[in]     timer_def     timer object referenced with \\ref osTimer.\r\n/// \\param[in]     type          osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.\r\n/// \\param[in]     argument      argument to the timer call back function.\r\n/// \\return timer ID for reference by other functions or NULL in case of error.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osTimerCreate shall be consistent in every CMSIS-RTOS.\r\nosTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument);\r\n\r\n/// Start or restart a timer.\r\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerCreate.\r\n/// \\param[in]     millisec      time delay value of the timer.\r\n/// \\return status code that indicates the execution status of the function.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osTimerStart shall be consistent in every CMSIS-RTOS.\r\nosStatus osTimerStart (osTimerId timer_id, uint32_t millisec);\r\n\r\n/// Stop the timer.\r\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerCreate.\r\n/// \\return status code that indicates the execution status of the function.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osTimerStop shall be consistent in every CMSIS-RTOS.\r\nosStatus osTimerStop (osTimerId timer_id);\r\n\r\n/// Delete a timer that was created by \\ref osTimerCreate.\r\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerCreate.\r\n/// \\return status code that indicates the execution status of the function.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osTimerDelete shall be consistent in every CMSIS-RTOS.\r\nosStatus osTimerDelete (osTimerId timer_id);\r\n\r\n\r\n//  ==== Signal Management ====\r\n\r\n/// Set the specified Signal Flags of an active thread.\r\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\r\n/// \\param[in]     signals       specifies the signal flags of the thread that should be set.\r\n/// \\return osOK if successful, osErrorOS if failed.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osSignalSet shall be consistent in every CMSIS-RTOS.\r\nint32_t osSignalSet (osThreadId thread_id, int32_t signals);\r\n\r\n/// Clear the specified Signal Flags of an active thread.\r\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\r\n/// \\param[in]     signals       specifies the signal flags of the thread that shall be cleared.\r\n/// \\return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osSignalClear shall be consistent in every CMSIS-RTOS.\r\nint32_t osSignalClear (osThreadId thread_id, int32_t signals);\r\n\r\n/// Wait for one or more Signal Flags to become signaled for the current \\b RUNNING thread.\r\n/// \\param[in]     signals       wait until all specified signal flags set or 0 for any single signal flag.\r\n/// \\param[in]     millisec      timeout value or 0 in case of no time-out.\r\n/// \\return event flag information or error code.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osSignalWait shall be consistent in every CMSIS-RTOS.\r\nosEvent osSignalWait (int32_t signals, uint32_t millisec);\r\n\r\n\r\n//  ==== Mutex Management ====\r\n\r\n/// Define a Mutex.\r\n/// \\param         name          name of the mutex object.\r\n/// \\note CAN BE CHANGED: The parameter to \\b osMutexDef shall be consistent but the\r\n///       macro body is implementation specific in every CMSIS-RTOS.\r\n#if defined (osObjectsExternal)  // object is external\r\n#define osMutexDef(name)  \\\r\nextern const osMutexDef_t os_mutex_def_##name\r\n#else                            // define the object\r\n#define osMutexDef(name)  \\\r\nconst osMutexDef_t os_mutex_def_##name = { 0 }\r\n#endif\r\n\r\n/// Access a Mutex definition.\r\n/// \\param         name          name of the mutex object.\r\n/// \\note CAN BE CHANGED: The parameter to \\b osMutex shall be consistent but the\r\n///       macro body is implementation specific in every CMSIS-RTOS.\r\n#define osMutex(name)  \\\r\n&os_mutex_def_##name\r\n\r\n/// Create and Initialize a Mutex object.\r\n/// \\param[in]     mutex_def     mutex definition referenced with \\ref osMutex.\r\n/// \\return mutex ID for reference by other functions or NULL in case of error.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osMutexCreate shall be consistent in every CMSIS-RTOS.\r\nosMutexId osMutexCreate (const osMutexDef_t *mutex_def);\r\n\r\n/// Wait until a Mutex becomes available.\r\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexCreate.\r\n/// \\param[in]     millisec      timeout value or 0 in case of no time-out.\r\n/// \\return status code that indicates the execution status of the function.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osMutexWait shall be consistent in every CMSIS-RTOS.\r\nosStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);\r\n\r\n/// Release a Mutex that was obtained by \\ref osMutexWait.\r\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexCreate.\r\n/// \\return status code that indicates the execution status of the function.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osMutexRelease shall be consistent in every CMSIS-RTOS.\r\nosStatus osMutexRelease (osMutexId mutex_id);\r\n\r\n/// Delete a Mutex that was created by \\ref osMutexCreate.\r\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexCreate.\r\n/// \\return status code that indicates the execution status of the function.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osMutexDelete shall be consistent in every CMSIS-RTOS.\r\nosStatus osMutexDelete (osMutexId mutex_id);\r\n\r\n\r\n//  ==== Semaphore Management Functions ====\r\n\r\n#if (defined (osFeature_Semaphore)  &&  (osFeature_Semaphore != 0))     // Semaphore available\r\n\r\n/// Define a Semaphore object.\r\n/// \\param         name          name of the semaphore object.\r\n/// \\note CAN BE CHANGED: The parameter to \\b osSemaphoreDef shall be consistent but the\r\n///       macro body is implementation specific in every CMSIS-RTOS.\r\n#if defined (osObjectsExternal)  // object is external\r\n#define osSemaphoreDef(name)  \\\r\nextern const osSemaphoreDef_t os_semaphore_def_##name\r\n#else                            // define the object\r\n#define osSemaphoreDef(name)  \\\r\nconst osSemaphoreDef_t os_semaphore_def_##name = { 0 }\r\n#endif\r\n\r\n/// Access a Semaphore definition.\r\n/// \\param         name          name of the semaphore object.\r\n/// \\note CAN BE CHANGED: The parameter to \\b osSemaphore shall be consistent but the\r\n///       macro body is implementation specific in every CMSIS-RTOS.\r\n#define osSemaphore(name)  \\\r\n&os_semaphore_def_##name\r\n\r\n/// Create and Initialize a Semaphore object used for managing resources.\r\n/// \\param[in]     semaphore_def semaphore definition referenced with \\ref osSemaphore.\r\n/// \\param[in]     count         number of available resources.\r\n/// \\return semaphore ID for reference by other functions or NULL in case of error.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osSemaphoreCreate shall be consistent in every CMSIS-RTOS.\r\nosSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count);\r\n\r\n/// Wait until a Semaphore token becomes available.\r\n/// \\param[in]     semaphore_id  semaphore object referenced with \\ref osSemaphoreCreate.\r\n/// \\param[in]     millisec      timeout value or 0 in case of no time-out.\r\n/// \\return number of available tokens, or -1 in case of incorrect parameters.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osSemaphoreWait shall be consistent in every CMSIS-RTOS.\r\nint32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);\r\n\r\n/// Release a Semaphore token.\r\n/// \\param[in]     semaphore_id  semaphore object referenced with \\ref osSemaphoreCreate.\r\n/// \\return status code that indicates the execution status of the function.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osSemaphoreRelease shall be consistent in every CMSIS-RTOS.\r\nosStatus osSemaphoreRelease (osSemaphoreId semaphore_id);\r\n\r\n/// Delete a Semaphore that was created by \\ref osSemaphoreCreate.\r\n/// \\param[in]     semaphore_id  semaphore object referenced with \\ref osSemaphoreCreate.\r\n/// \\return status code that indicates the execution status of the function.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osSemaphoreDelete shall be consistent in every CMSIS-RTOS.\r\nosStatus osSemaphoreDelete (osSemaphoreId semaphore_id);\r\n\r\n#endif     // Semaphore available\r\n\r\n\r\n//  ==== Memory Pool Management Functions ====\r\n\r\n#if (defined (osFeature_Pool)  &&  (osFeature_Pool != 0))  // Memory Pool Management available\r\n\r\n/// \\brief Define a Memory Pool.\r\n/// \\param         name          name of the memory pool.\r\n/// \\param         no            maximum number of blocks (objects) in the memory pool.\r\n/// \\param         type          data type of a single block (object).\r\n/// \\note CAN BE CHANGED: The parameter to \\b osPoolDef shall be consistent but the\r\n///       macro body is implementation specific in every CMSIS-RTOS.\r\n#if defined (osObjectsExternal)  // object is external\r\n#define osPoolDef(name, no, type)   \\\r\nextern const osPoolDef_t os_pool_def_##name\r\n#else                            // define the object\r\n#define osPoolDef(name, no, type)   \\\r\nconst osPoolDef_t os_pool_def_##name = \\\r\n{ (no), sizeof(type), NULL }\r\n#endif\r\n\r\n/// \\brief Access a Memory Pool definition.\r\n/// \\param         name          name of the memory pool\r\n/// \\note CAN BE CHANGED: The parameter to \\b osPool shall be consistent but the\r\n///       macro body is implementation specific in every CMSIS-RTOS.\r\n#define osPool(name) \\\r\n&os_pool_def_##name\r\n\r\n/// Create and Initialize a memory pool.\r\n/// \\param[in]     pool_def      memory pool definition referenced with \\ref osPool.\r\n/// \\return memory pool ID for reference by other functions or NULL in case of error.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osPoolCreate shall be consistent in every CMSIS-RTOS.\r\nosPoolId osPoolCreate (const osPoolDef_t *pool_def);\r\n\r\n/// Allocate a memory block from a memory pool.\r\n/// \\param[in]     pool_id       memory pool ID obtain referenced with \\ref osPoolCreate.\r\n/// \\return address of the allocated memory block or NULL in case of no memory available.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osPoolAlloc shall be consistent in every CMSIS-RTOS.\r\nvoid *osPoolAlloc (osPoolId pool_id);\r\n\r\n/// Allocate a memory block from a memory pool and set memory block to zero.\r\n/// \\param[in]     pool_id       memory pool ID obtain referenced with \\ref osPoolCreate.\r\n/// \\return address of the allocated memory block or NULL in case of no memory available.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osPoolCAlloc shall be consistent in every CMSIS-RTOS.\r\nvoid *osPoolCAlloc (osPoolId pool_id);\r\n\r\n/// Return an allocated memory block back to a specific memory pool.\r\n/// \\param[in]     pool_id       memory pool ID obtain referenced with \\ref osPoolCreate.\r\n/// \\param[in]     block         address of the allocated memory block that is returned to the memory pool.\r\n/// \\return status code that indicates the execution status of the function.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osPoolFree shall be consistent in every CMSIS-RTOS.\r\nosStatus osPoolFree (osPoolId pool_id, void *block);\r\n\r\n#endif   // Memory Pool Management available\r\n\r\n\r\n//  ==== Message Queue Management Functions ====\r\n\r\n#if (defined (osFeature_MessageQ)  &&  (osFeature_MessageQ != 0))     // Message Queues available\r\n\r\n/// \\brief Create a Message Queue Definition.\r\n/// \\param         name          name of the queue.\r\n/// \\param         queue_sz      maximum number of messages in the queue.\r\n/// \\param         type          data type of a single message element (for debugger).\r\n/// \\note CAN BE CHANGED: The parameter to \\b osMessageQDef shall be consistent but the\r\n///       macro body is implementation specific in every CMSIS-RTOS.\r\n#if defined (osObjectsExternal)  // object is external\r\n#define osMessageQDef(name, queue_sz, type)   \\\r\nextern const osMessageQDef_t os_messageQ_def_##name\r\n#else                            // define the object\r\n#define osMessageQDef(name, queue_sz, type)   \\\r\nconst osMessageQDef_t os_messageQ_def_##name = \\\r\n{ (queue_sz), sizeof (type)  }\r\n#endif\r\n\r\n/// \\brief Access a Message Queue Definition.\r\n/// \\param         name          name of the queue\r\n/// \\note CAN BE CHANGED: The parameter to \\b osMessageQ shall be consistent but the\r\n///       macro body is implementation specific in every CMSIS-RTOS.\r\n#define osMessageQ(name) \\\r\n&os_messageQ_def_##name\r\n\r\n/// Create and Initialize a Message Queue.\r\n/// \\param[in]     queue_def     queue definition referenced with \\ref osMessageQ.\r\n/// \\param[in]     thread_id     thread ID (obtained by \\ref osThreadCreate or \\ref osThreadGetId) or NULL.\r\n/// \\return message queue ID for reference by other functions or NULL in case of error.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osMessageCreate shall be consistent in every CMSIS-RTOS.\r\nosMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);\r\n\r\n/// Put a Message to a Queue.\r\n/// \\param[in]     queue_id      message queue ID obtained with \\ref osMessageCreate.\r\n/// \\param[in]     info          message information.\r\n/// \\param[in]     millisec      timeout value or 0 in case of no time-out.\r\n/// \\return status code that indicates the execution status of the function.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osMessagePut shall be consistent in every CMSIS-RTOS.\r\nosStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);\r\n\r\n/// Get a Message or Wait for a Message from a Queue.\r\n/// \\param[in]     queue_id      message queue ID obtained with \\ref osMessageCreate.\r\n/// \\param[in]     millisec      timeout value or 0 in case of no time-out.\r\n/// \\return event information that includes status code.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osMessageGet shall be consistent in every CMSIS-RTOS.\r\nosEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);\r\n\r\n#endif     // Message Queues available\r\n\r\n\r\n//  ==== Mail Queue Management Functions ====\r\n\r\n#if (defined (osFeature_MailQ)  &&  (osFeature_MailQ != 0))     // Mail Queues available\r\n\r\n/// \\brief Create a Mail Queue Definition.\r\n/// \\param         name          name of the queue\r\n/// \\param         queue_sz      maximum number of messages in queue\r\n/// \\param         type          data type of a single message element\r\n/// \\note CAN BE CHANGED: The parameter to \\b osMailQDef shall be consistent but the\r\n///       macro body is implementation specific in every CMSIS-RTOS.\r\n#if defined (osObjectsExternal)  // object is external\r\n#define osMailQDef(name, queue_sz, type) \\\r\nextern struct os_mailQ_cb *os_mailQ_cb_##name \\\r\nextern osMailQDef_t os_mailQ_def_##name\r\n#else                            // define the object\r\n#define osMailQDef(name, queue_sz, type) \\\r\nstruct os_mailQ_cb *os_mailQ_cb_##name; \\\r\nconst osMailQDef_t os_mailQ_def_##name =  \\\r\n{ (queue_sz), sizeof (type), (&os_mailQ_cb_##name) }\r\n#endif\r\n\r\n/// \\brief Access a Mail Queue Definition.\r\n/// \\param         name          name of the queue\r\n/// \\note CAN BE CHANGED: The parameter to \\b osMailQ shall be consistent but the\r\n///       macro body is implementation specific in every CMSIS-RTOS.\r\n#define osMailQ(name)  \\\r\n&os_mailQ_def_##name\r\n\r\n/// Create and Initialize mail queue.\r\n/// \\param[in]     queue_def     reference to the mail queue definition obtain with \\ref osMailQ\r\n/// \\param[in]     thread_id     thread ID (obtained by \\ref osThreadCreate or \\ref osThreadGetId) or NULL.\r\n/// \\return mail queue ID for reference by other functions or NULL in case of error.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osMailCreate shall be consistent in every CMSIS-RTOS.\r\nosMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id);\r\n\r\n/// Allocate a memory block from a mail.\r\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\r\n/// \\param[in]     millisec      timeout value or 0 in case of no time-out\r\n/// \\return pointer to memory block that can be filled with mail or NULL in case of error.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osMailAlloc shall be consistent in every CMSIS-RTOS.\r\nvoid *osMailAlloc (osMailQId queue_id, uint32_t millisec);\r\n\r\n/// Allocate a memory block from a mail and set memory block to zero.\r\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\r\n/// \\param[in]     millisec      timeout value or 0 in case of no time-out\r\n/// \\return pointer to memory block that can be filled with mail or NULL in case of error.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osMailCAlloc shall be consistent in every CMSIS-RTOS.\r\nvoid *osMailCAlloc (osMailQId queue_id, uint32_t millisec);\r\n\r\n/// Put a mail to a queue.\r\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\r\n/// \\param[in]     mail          memory block previously allocated with \\ref osMailAlloc or \\ref osMailCAlloc.\r\n/// \\return status code that indicates the execution status of the function.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osMailPut shall be consistent in every CMSIS-RTOS.\r\nosStatus osMailPut (osMailQId queue_id, void *mail);\r\n\r\n/// Get a mail from a queue.\r\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\r\n/// \\param[in]     millisec      timeout value or 0 in case of no time-out\r\n/// \\return event that contains mail information or error code.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osMailGet shall be consistent in every CMSIS-RTOS.\r\nosEvent osMailGet (osMailQId queue_id, uint32_t millisec);\r\n\r\n/// Free a memory block from a mail.\r\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\r\n/// \\param[in]     mail          pointer to the memory block that was obtained with \\ref osMailGet.\r\n/// \\return status code that indicates the execution status of the function.\r\n/// \\note MUST REMAIN UNCHANGED: \\b osMailFree shall be consistent in every CMSIS-RTOS.\r\nosStatus osMailFree (osMailQId queue_id, void *mail);\r\n\r\n#endif  // Mail Queues available\r\n\r\n/*************************** Additional specific APIs to Free RTOS ************/\r\n/**\r\n* @brief  Handles the tick increment\r\n* @param  none.\r\n* @retval none.\r\n*/\r\nvoid osSystickHandler(void);\r\n\r\n#if ( INCLUDE_eTaskGetState == 1 )\r\n/**\r\n* @brief  Obtain the state of any thread.\r\n* @param   thread_id   thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\r\n* @retval  the stae of the thread, states are encoded by the osThreadState enumerated type.\r\n*/\r\nosThreadState osThreadGetState(osThreadId thread_id);\r\n#endif /* INCLUDE_eTaskGetState */\r\n\r\n#if ( INCLUDE_eTaskGetState == 1 )\r\n/**\r\n* @brief Check if a thread is already suspended or not.\r\n* @param thread_id thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\r\n* @retval status code that indicates the execution status of the function.\r\n*/\r\n\r\nosStatus osThreadIsSuspended(osThreadId thread_id);\r\n\r\n#endif /* INCLUDE_eTaskGetState */\r\n\r\n/**\r\n* @brief  Suspend execution of a thread.\r\n* @param   thread_id   thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\r\n* @retval  status code that indicates the execution status of the function.\r\n*/\r\nosStatus osThreadSuspend (osThreadId thread_id);\r\n\r\n/**\r\n* @brief  Resume execution of a suspended thread.\r\n* @param   thread_id   thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\r\n* @retval  status code that indicates the execution status of the function.\r\n*/\r\nosStatus osThreadResume (osThreadId thread_id);\r\n\r\n/**\r\n* @brief  Suspend execution of a all active threads.\r\n* @retval  status code that indicates the execution status of the function.\r\n*/\r\nosStatus osThreadSuspendAll (void);\r\n\r\n/**\r\n* @brief  Resume execution of a all suspended threads.\r\n* @retval  status code that indicates the execution status of the function.\r\n*/\r\nosStatus osThreadResumeAll (void);\r\n\r\n/**\r\n* @brief  Delay a task until a specified time\r\n* @param   PreviousWakeTime   Pointer to a variable that holds the time at which the \r\n*          task was last unblocked. PreviousWakeTime must be initialised with the current time\r\n*          prior to its first use (PreviousWakeTime = osKernelSysTick() )\r\n* @param   millisec    time delay value\r\n* @retval  status code that indicates the execution status of the function.\r\n*/\r\nosStatus osDelayUntil (uint32_t *PreviousWakeTime, uint32_t millisec);\r\n\r\n/**\r\n* @brief   Lists all the current threads, along with their current state \r\n*          and stack usage high water mark.\r\n* @param   buffer   A buffer into which the above mentioned details\r\n*          will be written\r\n* @retval  status code that indicates the execution status of the function.\r\n*/\r\nosStatus osThreadList (uint8_t *buffer);\r\n\r\n/**\r\n* @brief  Receive an item from a queue without removing the item from the queue.\r\n* @param  queue_id  message queue ID obtained with \\ref osMessageCreate.\r\n* @param  millisec  timeout value or 0 in case of no time-out.\r\n* @retval event information that includes status code.\r\n*/\r\nosEvent osMessagePeek (osMessageQId queue_id, uint32_t millisec);\r\n\r\n/**\r\n* @brief  Create and Initialize a Recursive Mutex\r\n* @param  mutex_def     mutex definition referenced with \\ref osMutex.\r\n* @retval  mutex ID for reference by other functions or NULL in case of error..\r\n*/\r\nosMutexId osRecursiveMutexCreate (const osMutexDef_t *mutex_def);\r\n\r\n/**\r\n* @brief  Release a Recursive Mutex\r\n* @param   mutex_id      mutex ID obtained by \\ref osRecursiveMutexCreate.\r\n* @retval  status code that indicates the execution status of the function.\r\n*/\r\nosStatus osRecursiveMutexRelease (osMutexId mutex_id);\r\n\r\n/**\r\n* @brief  Release a Recursive Mutex\r\n* @param   mutex_id    mutex ID obtained by \\ref osRecursiveMutexCreate.\r\n* @param millisec      timeout value or 0 in case of no time-out.\r\n* @retval  status code that indicates the execution status of the function.\r\n*/\r\nosStatus osRecursiveMutexWait (osMutexId mutex_id, uint32_t millisec);\r\n\r\n#ifdef  __cplusplus\r\n}\r\n#endif\r\n\r\n#endif  // _CMSIS_OS_H\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RTOS/src/croutine.c",
    "content": "/*\r\n    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r\n    All rights reserved\r\n\r\n    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r\n\r\n    This file is part of the FreeRTOS distribution.\r\n\r\n    FreeRTOS is free software; you can redistribute it and/or modify it under\r\n    the terms of the GNU General Public License (version 2) as published by the\r\n    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r\n\r\n    ***************************************************************************\r\n    >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r\n    >>!   distribute a combined work that includes FreeRTOS without being   !<<\r\n    >>!   obliged to provide the source code for proprietary components     !<<\r\n    >>!   outside of the FreeRTOS kernel.                                   !<<\r\n    ***************************************************************************\r\n\r\n    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r\n    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r\n    FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r\n    link: http://www.freertos.org/a00114.html\r\n\r\n    ***************************************************************************\r\n     *                                                                       *\r\n     *    FreeRTOS provides completely free yet professionally developed,    *\r\n     *    robust, strictly quality controlled, supported, and cross          *\r\n     *    platform software that is more than just the market leader, it     *\r\n     *    is the industry's de facto standard.                               *\r\n     *                                                                       *\r\n     *    Help yourself get started quickly while simultaneously helping     *\r\n     *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r\n     *    tutorial book, reference manual, or both:                          *\r\n     *    http://www.FreeRTOS.org/Documentation                              *\r\n     *                                                                       *\r\n    ***************************************************************************\r\n\r\n    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r\n    the FAQ page \"My application does not run, what could be wrong?\".  Have you\r\n    defined configASSERT()?\r\n\r\n    http://www.FreeRTOS.org/support - In return for receiving this top quality\r\n    embedded software for free we request you assist our global community by\r\n    participating in the support forum.\r\n\r\n    http://www.FreeRTOS.org/training - Investing in training allows your team to\r\n    be as productive as possible as early as possible.  Now you can receive\r\n    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r\n    Ltd, and the world's leading authority on the world's leading RTOS.\r\n\r\n    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r\n    including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r\n    compatible FAT file system, and our tiny thread aware UDP/IP stack.\r\n\r\n    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r\n    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r\n\r\n    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r\n    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r\n    licenses offer ticketed support, indemnification and commercial middleware.\r\n\r\n    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r\n    engineered and independently SIL3 certified version for use in safety and\r\n    mission critical applications that require provable dependability.\r\n\r\n    1 tab == 4 spaces!\r\n*/\r\n\r\n#include \"FreeRTOS.h\"\r\n#include \"task.h\"\r\n#include \"croutine.h\"\r\n\r\n/* Remove the whole file is co-routines are not being used. */\r\n#if( configUSE_CO_ROUTINES != 0 )\r\n\r\n/*\r\n * Some kernel aware debuggers require data to be viewed to be global, rather\r\n * than file scope.\r\n */\r\n#ifdef portREMOVE_STATIC_QUALIFIER\r\n\t#define static\r\n#endif\r\n\r\n\r\n/* Lists for ready and blocked co-routines. --------------------*/\r\nstatic List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ];\t/*< Prioritised ready co-routines. */\r\nstatic List_t xDelayedCoRoutineList1;\t\t\t\t\t\t\t\t\t/*< Delayed co-routines. */\r\nstatic List_t xDelayedCoRoutineList2;\t\t\t\t\t\t\t\t\t/*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */\r\nstatic List_t * pxDelayedCoRoutineList;\t\t\t\t\t\t\t\t\t/*< Points to the delayed co-routine list currently being used. */\r\nstatic List_t * pxOverflowDelayedCoRoutineList;\t\t\t\t\t\t\t/*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */\r\nstatic List_t xPendingReadyCoRoutineList;\t\t\t\t\t\t\t\t/*< Holds co-routines that have been readied by an external event.  They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */\r\n\r\n/* Other file private variables. --------------------------------*/\r\nCRCB_t * pxCurrentCoRoutine = NULL;\r\nstatic UBaseType_t uxTopCoRoutineReadyPriority = 0;\r\nstatic TickType_t xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0;\r\n\r\n/* The initial state of the co-routine when it is created. */\r\n#define corINITIAL_STATE\t( 0 )\r\n\r\n/*\r\n * Place the co-routine represented by pxCRCB into the appropriate ready queue\r\n * for the priority.  It is inserted at the end of the list.\r\n *\r\n * This macro accesses the co-routine ready lists and therefore must not be\r\n * used from within an ISR.\r\n */\r\n#define prvAddCoRoutineToReadyQueue( pxCRCB )\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\tif( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority )\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\tuxTopCoRoutineReadyPriority = pxCRCB->uxPriority;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\tvListInsertEnd( ( List_t * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) );\t\\\r\n}\r\n\r\n/*\r\n * Utility to ready all the lists used by the scheduler.  This is called\r\n * automatically upon the creation of the first co-routine.\r\n */\r\nstatic void prvInitialiseCoRoutineLists( void );\r\n\r\n/*\r\n * Co-routines that are readied by an interrupt cannot be placed directly into\r\n * the ready lists (there is no mutual exclusion).  Instead they are placed in\r\n * in the pending ready list in order that they can later be moved to the ready\r\n * list by the co-routine scheduler.\r\n */\r\nstatic void prvCheckPendingReadyList( void );\r\n\r\n/*\r\n * Macro that looks at the list of co-routines that are currently delayed to\r\n * see if any require waking.\r\n *\r\n * Co-routines are stored in the queue in the order of their wake time -\r\n * meaning once one co-routine has been found whose timer has not expired\r\n * we need not look any further down the list.\r\n */\r\nstatic void prvCheckDelayedList( void );\r\n\r\n/*-----------------------------------------------------------*/\r\n\r\nBaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex )\r\n{\r\nBaseType_t xReturn;\r\nCRCB_t *pxCoRoutine;\r\n\r\n\t/* Allocate the memory that will store the co-routine control block. */\r\n\tpxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) );\r\n\tif( pxCoRoutine )\r\n\t{\r\n\t\t/* If pxCurrentCoRoutine is NULL then this is the first co-routine to\r\n\t\tbe created and the co-routine data structures need initialising. */\r\n\t\tif( pxCurrentCoRoutine == NULL )\r\n\t\t{\r\n\t\t\tpxCurrentCoRoutine = pxCoRoutine;\r\n\t\t\tprvInitialiseCoRoutineLists();\r\n\t\t}\r\n\r\n\t\t/* Check the priority is within limits. */\r\n\t\tif( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES )\r\n\t\t{\r\n\t\t\tuxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1;\r\n\t\t}\r\n\r\n\t\t/* Fill out the co-routine control block from the function parameters. */\r\n\t\tpxCoRoutine->uxState = corINITIAL_STATE;\r\n\t\tpxCoRoutine->uxPriority = uxPriority;\r\n\t\tpxCoRoutine->uxIndex = uxIndex;\r\n\t\tpxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode;\r\n\r\n\t\t/* Initialise all the other co-routine control block parameters. */\r\n\t\tvListInitialiseItem( &( pxCoRoutine->xGenericListItem ) );\r\n\t\tvListInitialiseItem( &( pxCoRoutine->xEventListItem ) );\r\n\r\n\t\t/* Set the co-routine control block as a link back from the ListItem_t.\r\n\t\tThis is so we can get back to the containing CRCB from a generic item\r\n\t\tin a list. */\r\n\t\tlistSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine );\r\n\t\tlistSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine );\r\n\r\n\t\t/* Event lists are always in priority order. */\r\n\t\tlistSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), ( ( TickType_t ) configMAX_CO_ROUTINE_PRIORITIES - ( TickType_t ) uxPriority ) );\r\n\r\n\t\t/* Now the co-routine has been initialised it can be added to the ready\r\n\t\tlist at the correct priority. */\r\n\t\tprvAddCoRoutineToReadyQueue( pxCoRoutine );\r\n\r\n\t\txReturn = pdPASS;\r\n\t}\r\n\telse\r\n\t{\r\n\t\txReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;\r\n\t}\r\n\r\n\treturn xReturn;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nvoid vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList )\r\n{\r\nTickType_t xTimeToWake;\r\n\r\n\t/* Calculate the time to wake - this may overflow but this is\r\n\tnot a problem. */\r\n\txTimeToWake = xCoRoutineTickCount + xTicksToDelay;\r\n\r\n\t/* We must remove ourselves from the ready list before adding\r\n\tourselves to the blocked list as the same list item is used for\r\n\tboth lists. */\r\n\t( void ) uxListRemove( ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );\r\n\r\n\t/* The list item will be inserted in wake time order. */\r\n\tlistSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake );\r\n\r\n\tif( xTimeToWake < xCoRoutineTickCount )\r\n\t{\r\n\t\t/* Wake time has overflowed.  Place this item in the\r\n\t\toverflow list. */\r\n\t\tvListInsert( ( List_t * ) pxOverflowDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );\r\n\t}\r\n\telse\r\n\t{\r\n\t\t/* The wake time has not overflowed, so we can use the\r\n\t\tcurrent block list. */\r\n\t\tvListInsert( ( List_t * ) pxDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );\r\n\t}\r\n\r\n\tif( pxEventList )\r\n\t{\r\n\t\t/* Also add the co-routine to an event list.  If this is done then the\r\n\t\tfunction must be called with interrupts disabled. */\r\n\t\tvListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) );\r\n\t}\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nstatic void prvCheckPendingReadyList( void )\r\n{\r\n\t/* Are there any co-routines waiting to get moved to the ready list?  These\r\n\tare co-routines that have been readied by an ISR.  The ISR cannot access\r\n\tthe\tready lists itself. */\r\n\twhile( listLIST_IS_EMPTY( &xPendingReadyCoRoutineList ) == pdFALSE )\r\n\t{\r\n\t\tCRCB_t *pxUnblockedCRCB;\r\n\r\n\t\t/* The pending ready list can be accessed by an ISR. */\r\n\t\tportDISABLE_INTERRUPTS();\r\n\t\t{\r\n\t\t\tpxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( (&xPendingReadyCoRoutineList) );\r\n\t\t\t( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );\r\n\t\t}\r\n\t\tportENABLE_INTERRUPTS();\r\n\r\n\t\t( void ) uxListRemove( &( pxUnblockedCRCB->xGenericListItem ) );\r\n\t\tprvAddCoRoutineToReadyQueue( pxUnblockedCRCB );\r\n\t}\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nstatic void prvCheckDelayedList( void )\r\n{\r\nCRCB_t *pxCRCB;\r\n\r\n\txPassedTicks = xTaskGetTickCount() - xLastTickCount;\r\n\twhile( xPassedTicks )\r\n\t{\r\n\t\txCoRoutineTickCount++;\r\n\t\txPassedTicks--;\r\n\r\n\t\t/* If the tick count has overflowed we need to swap the ready lists. */\r\n\t\tif( xCoRoutineTickCount == 0 )\r\n\t\t{\r\n\t\t\tList_t * pxTemp;\r\n\r\n\t\t\t/* Tick count has overflowed so we need to swap the delay lists.  If there are\r\n\t\t\tany items in pxDelayedCoRoutineList here then there is an error! */\r\n\t\t\tpxTemp = pxDelayedCoRoutineList;\r\n\t\t\tpxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList;\r\n\t\t\tpxOverflowDelayedCoRoutineList = pxTemp;\r\n\t\t}\r\n\r\n\t\t/* See if this tick has made a timeout expire. */\r\n\t\twhile( listLIST_IS_EMPTY( pxDelayedCoRoutineList ) == pdFALSE )\r\n\t\t{\r\n\t\t\tpxCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList );\r\n\r\n\t\t\tif( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) )\r\n\t\t\t{\r\n\t\t\t\t/* Timeout not yet expired. */\r\n\t\t\t\tbreak;\r\n\t\t\t}\r\n\r\n\t\t\tportDISABLE_INTERRUPTS();\r\n\t\t\t{\r\n\t\t\t\t/* The event could have occurred just before this critical\r\n\t\t\t\tsection.  If this is the case then the generic list item will\r\n\t\t\t\thave been moved to the pending ready list and the following\r\n\t\t\t\tline is still valid.  Also the pvContainer parameter will have\r\n\t\t\t\tbeen set to NULL so the following lines are also valid. */\r\n\t\t\t\t( void ) uxListRemove( &( pxCRCB->xGenericListItem ) );\r\n\r\n\t\t\t\t/* Is the co-routine waiting on an event also? */\r\n\t\t\t\tif( pxCRCB->xEventListItem.pvContainer )\r\n\t\t\t\t{\r\n\t\t\t\t\t( void ) uxListRemove( &( pxCRCB->xEventListItem ) );\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\tportENABLE_INTERRUPTS();\r\n\r\n\t\t\tprvAddCoRoutineToReadyQueue( pxCRCB );\r\n\t\t}\r\n\t}\r\n\r\n\txLastTickCount = xCoRoutineTickCount;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nvoid vCoRoutineSchedule( void )\r\n{\r\n\t/* See if any co-routines readied by events need moving to the ready lists. */\r\n\tprvCheckPendingReadyList();\r\n\r\n\t/* See if any delayed co-routines have timed out. */\r\n\tprvCheckDelayedList();\r\n\r\n\t/* Find the highest priority queue that contains ready co-routines. */\r\n\twhile( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) )\r\n\t{\r\n\t\tif( uxTopCoRoutineReadyPriority == 0 )\r\n\t\t{\r\n\t\t\t/* No more co-routines to check. */\r\n\t\t\treturn;\r\n\t\t}\r\n\t\t--uxTopCoRoutineReadyPriority;\r\n\t}\r\n\r\n\t/* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines\r\n\t of the\tsame priority get an equal share of the processor time. */\r\n\tlistGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) );\r\n\r\n\t/* Call the co-routine. */\r\n\t( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex );\r\n\r\n\treturn;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nstatic void prvInitialiseCoRoutineLists( void )\r\n{\r\nUBaseType_t uxPriority;\r\n\r\n\tfor( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ )\r\n\t{\r\n\t\tvListInitialise( ( List_t * ) &( pxReadyCoRoutineLists[ uxPriority ] ) );\r\n\t}\r\n\r\n\tvListInitialise( ( List_t * ) &xDelayedCoRoutineList1 );\r\n\tvListInitialise( ( List_t * ) &xDelayedCoRoutineList2 );\r\n\tvListInitialise( ( List_t * ) &xPendingReadyCoRoutineList );\r\n\r\n\t/* Start with pxDelayedCoRoutineList using list1 and the\r\n\tpxOverflowDelayedCoRoutineList using list2. */\r\n\tpxDelayedCoRoutineList = &xDelayedCoRoutineList1;\r\n\tpxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nBaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList )\r\n{\r\nCRCB_t *pxUnblockedCRCB;\r\nBaseType_t xReturn;\r\n\r\n\t/* This function is called from within an interrupt.  It can only access\r\n\tevent lists and the pending ready list.  This function assumes that a\r\n\tcheck has already been made to ensure pxEventList is not empty. */\r\n\tpxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );\r\n\t( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );\r\n\tvListInsertEnd( ( List_t * ) &( xPendingReadyCoRoutineList ), &( pxUnblockedCRCB->xEventListItem ) );\r\n\r\n\tif( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority )\r\n\t{\r\n\t\txReturn = pdTRUE;\r\n\t}\r\n\telse\r\n\t{\r\n\t\txReturn = pdFALSE;\r\n\t}\r\n\r\n\treturn xReturn;\r\n}\r\n\r\n#endif /* configUSE_CO_ROUTINES == 0 */\r\n\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RTOS/src/croutine.h",
    "content": "/*\r\n    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r\n    All rights reserved\r\n\r\n    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r\n\r\n    This file is part of the FreeRTOS distribution.\r\n\r\n    FreeRTOS is free software; you can redistribute it and/or modify it under\r\n    the terms of the GNU General Public License (version 2) as published by the\r\n    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r\n\r\n    ***************************************************************************\r\n    >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r\n    >>!   distribute a combined work that includes FreeRTOS without being   !<<\r\n    >>!   obliged to provide the source code for proprietary components     !<<\r\n    >>!   outside of the FreeRTOS kernel.                                   !<<\r\n    ***************************************************************************\r\n\r\n    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r\n    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r\n    FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r\n    link: http://www.freertos.org/a00114.html\r\n\r\n    ***************************************************************************\r\n     *                                                                       *\r\n     *    FreeRTOS provides completely free yet professionally developed,    *\r\n     *    robust, strictly quality controlled, supported, and cross          *\r\n     *    platform software that is more than just the market leader, it     *\r\n     *    is the industry's de facto standard.                               *\r\n     *                                                                       *\r\n     *    Help yourself get started quickly while simultaneously helping     *\r\n     *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r\n     *    tutorial book, reference manual, or both:                          *\r\n     *    http://www.FreeRTOS.org/Documentation                              *\r\n     *                                                                       *\r\n    ***************************************************************************\r\n\r\n    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r\n    the FAQ page \"My application does not run, what could be wrong?\".  Have you\r\n    defined configASSERT()?\r\n\r\n    http://www.FreeRTOS.org/support - In return for receiving this top quality\r\n    embedded software for free we request you assist our global community by\r\n    participating in the support forum.\r\n\r\n    http://www.FreeRTOS.org/training - Investing in training allows your team to\r\n    be as productive as possible as early as possible.  Now you can receive\r\n    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r\n    Ltd, and the world's leading authority on the world's leading RTOS.\r\n\r\n    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r\n    including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r\n    compatible FAT file system, and our tiny thread aware UDP/IP stack.\r\n\r\n    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r\n    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r\n\r\n    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r\n    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r\n    licenses offer ticketed support, indemnification and commercial middleware.\r\n\r\n    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r\n    engineered and independently SIL3 certified version for use in safety and\r\n    mission critical applications that require provable dependability.\r\n\r\n    1 tab == 4 spaces!\r\n*/\r\n\r\n#ifndef CO_ROUTINE_H\r\n#define CO_ROUTINE_H\r\n\r\n#ifndef INC_FREERTOS_H\r\n\t#error \"include FreeRTOS.h must appear in source files before include croutine.h\"\r\n#endif\r\n\r\n#include \"list.h\"\r\n\r\n#ifdef __cplusplus\r\nextern \"C\" {\r\n#endif\r\n\r\n/* Used to hide the implementation of the co-routine control block.  The\r\ncontrol block structure however has to be included in the header due to\r\nthe macro implementation of the co-routine functionality. */\r\ntypedef void * CoRoutineHandle_t;\r\n\r\n/* Defines the prototype to which co-routine functions must conform. */\r\ntypedef void (*crCOROUTINE_CODE)( CoRoutineHandle_t, UBaseType_t );\r\n\r\ntypedef struct corCoRoutineControlBlock\r\n{\r\n\tcrCOROUTINE_CODE \tpxCoRoutineFunction;\r\n\tListItem_t\t\t\txGenericListItem;\t/*< List item used to place the CRCB in ready and blocked queues. */\r\n\tListItem_t\t\t\txEventListItem;\t\t/*< List item used to place the CRCB in event lists. */\r\n\tUBaseType_t \t\tuxPriority;\t\t\t/*< The priority of the co-routine in relation to other co-routines. */\r\n\tUBaseType_t \t\tuxIndex;\t\t\t/*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */\r\n\tuint16_t \t\t\tuxState;\t\t\t/*< Used internally by the co-routine implementation. */\r\n} CRCB_t; /* Co-routine control block.  Note must be identical in size down to uxPriority with TCB_t. */\r\n\r\n/**\r\n * croutine. h\r\n *<pre>\r\n BaseType_t xCoRoutineCreate(\r\n                                 crCOROUTINE_CODE pxCoRoutineCode,\r\n                                 UBaseType_t uxPriority,\r\n                                 UBaseType_t uxIndex\r\n                               );</pre>\r\n *\r\n * Create a new co-routine and add it to the list of co-routines that are\r\n * ready to run.\r\n *\r\n * @param pxCoRoutineCode Pointer to the co-routine function.  Co-routine\r\n * functions require special syntax - see the co-routine section of the WEB\r\n * documentation for more information.\r\n *\r\n * @param uxPriority The priority with respect to other co-routines at which\r\n *  the co-routine will run.\r\n *\r\n * @param uxIndex Used to distinguish between different co-routines that\r\n * execute the same function.  See the example below and the co-routine section\r\n * of the WEB documentation for further information.\r\n *\r\n * @return pdPASS if the co-routine was successfully created and added to a ready\r\n * list, otherwise an error code defined with ProjDefs.h.\r\n *\r\n * Example usage:\r\n   <pre>\r\n // Co-routine to be created.\r\n void vFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )\r\n {\r\n // Variables in co-routines must be declared static if they must maintain value across a blocking call.\r\n // This may not be necessary for const variables.\r\n static const char cLedToFlash[ 2 ] = { 5, 6 };\r\n static const TickType_t uxFlashRates[ 2 ] = { 200, 400 };\r\n\r\n     // Must start every co-routine with a call to crSTART();\r\n     crSTART( xHandle );\r\n\r\n     for( ;; )\r\n     {\r\n         // This co-routine just delays for a fixed period, then toggles\r\n         // an LED.  Two co-routines are created using this function, so\r\n         // the uxIndex parameter is used to tell the co-routine which\r\n         // LED to flash and how int32_t to delay.  This assumes xQueue has\r\n         // already been created.\r\n         vParTestToggleLED( cLedToFlash[ uxIndex ] );\r\n         crDELAY( xHandle, uxFlashRates[ uxIndex ] );\r\n     }\r\n\r\n     // Must end every co-routine with a call to crEND();\r\n     crEND();\r\n }\r\n\r\n // Function that creates two co-routines.\r\n void vOtherFunction( void )\r\n {\r\n uint8_t ucParameterToPass;\r\n TaskHandle_t xHandle;\r\n\r\n     // Create two co-routines at priority 0.  The first is given index 0\r\n     // so (from the code above) toggles LED 5 every 200 ticks.  The second\r\n     // is given index 1 so toggles LED 6 every 400 ticks.\r\n     for( uxIndex = 0; uxIndex < 2; uxIndex++ )\r\n     {\r\n         xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );\r\n     }\r\n }\r\n   </pre>\r\n * \\defgroup xCoRoutineCreate xCoRoutineCreate\r\n * \\ingroup Tasks\r\n */\r\nBaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex );\r\n\r\n\r\n/**\r\n * croutine. h\r\n *<pre>\r\n void vCoRoutineSchedule( void );</pre>\r\n *\r\n * Run a co-routine.\r\n *\r\n * vCoRoutineSchedule() executes the highest priority co-routine that is able\r\n * to run.  The co-routine will execute until it either blocks, yields or is\r\n * preempted by a task.  Co-routines execute cooperatively so one\r\n * co-routine cannot be preempted by another, but can be preempted by a task.\r\n *\r\n * If an application comprises of both tasks and co-routines then\r\n * vCoRoutineSchedule should be called from the idle task (in an idle task\r\n * hook).\r\n *\r\n * Example usage:\r\n   <pre>\r\n // This idle task hook will schedule a co-routine each time it is called.\r\n // The rest of the idle task will execute between co-routine calls.\r\n void vApplicationIdleHook( void )\r\n {\r\n\tvCoRoutineSchedule();\r\n }\r\n\r\n // Alternatively, if you do not require any other part of the idle task to\r\n // execute, the idle task hook can call vCoRoutineScheduler() within an\r\n // infinite loop.\r\n void vApplicationIdleHook( void )\r\n {\r\n    for( ;; )\r\n    {\r\n        vCoRoutineSchedule();\r\n    }\r\n }\r\n </pre>\r\n * \\defgroup vCoRoutineSchedule vCoRoutineSchedule\r\n * \\ingroup Tasks\r\n */\r\nvoid vCoRoutineSchedule( void );\r\n\r\n/**\r\n * croutine. h\r\n * <pre>\r\n crSTART( CoRoutineHandle_t xHandle );</pre>\r\n *\r\n * This macro MUST always be called at the start of a co-routine function.\r\n *\r\n * Example usage:\r\n   <pre>\r\n // Co-routine to be created.\r\n void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )\r\n {\r\n // Variables in co-routines must be declared static if they must maintain value across a blocking call.\r\n static int32_t ulAVariable;\r\n\r\n     // Must start every co-routine with a call to crSTART();\r\n     crSTART( xHandle );\r\n\r\n     for( ;; )\r\n     {\r\n          // Co-routine functionality goes here.\r\n     }\r\n\r\n     // Must end every co-routine with a call to crEND();\r\n     crEND();\r\n }</pre>\r\n * \\defgroup crSTART crSTART\r\n * \\ingroup Tasks\r\n */\r\n#define crSTART( pxCRCB ) switch( ( ( CRCB_t * )( pxCRCB ) )->uxState ) { case 0:\r\n\r\n/**\r\n * croutine. h\r\n * <pre>\r\n crEND();</pre>\r\n *\r\n * This macro MUST always be called at the end of a co-routine function.\r\n *\r\n * Example usage:\r\n   <pre>\r\n // Co-routine to be created.\r\n void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )\r\n {\r\n // Variables in co-routines must be declared static if they must maintain value across a blocking call.\r\n static int32_t ulAVariable;\r\n\r\n     // Must start every co-routine with a call to crSTART();\r\n     crSTART( xHandle );\r\n\r\n     for( ;; )\r\n     {\r\n          // Co-routine functionality goes here.\r\n     }\r\n\r\n     // Must end every co-routine with a call to crEND();\r\n     crEND();\r\n }</pre>\r\n * \\defgroup crSTART crSTART\r\n * \\ingroup Tasks\r\n */\r\n#define crEND() }\r\n\r\n/*\r\n * These macros are intended for internal use by the co-routine implementation\r\n * only.  The macros should not be used directly by application writers.\r\n */\r\n#define crSET_STATE0( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = (__LINE__ * 2); return; case (__LINE__ * 2):\r\n#define crSET_STATE1( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1):\r\n\r\n/**\r\n * croutine. h\r\n *<pre>\r\n crDELAY( CoRoutineHandle_t xHandle, TickType_t xTicksToDelay );</pre>\r\n *\r\n * Delay a co-routine for a fixed period of time.\r\n *\r\n * crDELAY can only be called from the co-routine function itself - not\r\n * from within a function called by the co-routine function.  This is because\r\n * co-routines do not maintain their own stack.\r\n *\r\n * @param xHandle The handle of the co-routine to delay.  This is the xHandle\r\n * parameter of the co-routine function.\r\n *\r\n * @param xTickToDelay The number of ticks that the co-routine should delay\r\n * for.  The actual amount of time this equates to is defined by\r\n * configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant portTICK_PERIOD_MS\r\n * can be used to convert ticks to milliseconds.\r\n *\r\n * Example usage:\r\n   <pre>\r\n // Co-routine to be created.\r\n void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )\r\n {\r\n // Variables in co-routines must be declared static if they must maintain value across a blocking call.\r\n // This may not be necessary for const variables.\r\n // We are to delay for 200ms.\r\n static const xTickType xDelayTime = 200 / portTICK_PERIOD_MS;\r\n\r\n     // Must start every co-routine with a call to crSTART();\r\n     crSTART( xHandle );\r\n\r\n     for( ;; )\r\n     {\r\n        // Delay for 200ms.\r\n        crDELAY( xHandle, xDelayTime );\r\n\r\n        // Do something here.\r\n     }\r\n\r\n     // Must end every co-routine with a call to crEND();\r\n     crEND();\r\n }</pre>\r\n * \\defgroup crDELAY crDELAY\r\n * \\ingroup Tasks\r\n */\r\n#define crDELAY( xHandle, xTicksToDelay )\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\tif( ( xTicksToDelay ) > 0 )\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\tvCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL );\t\t\t\t\t\t\t\\\r\n\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\tcrSET_STATE0( ( xHandle ) );\r\n\r\n/**\r\n * <pre>\r\n crQUEUE_SEND(\r\n                  CoRoutineHandle_t xHandle,\r\n                  QueueHandle_t pxQueue,\r\n                  void *pvItemToQueue,\r\n                  TickType_t xTicksToWait,\r\n                  BaseType_t *pxResult\r\n             )</pre>\r\n *\r\n * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine\r\n * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.\r\n *\r\n * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas\r\n * xQueueSend() and xQueueReceive() can only be used from tasks.\r\n *\r\n * crQUEUE_SEND can only be called from the co-routine function itself - not\r\n * from within a function called by the co-routine function.  This is because\r\n * co-routines do not maintain their own stack.\r\n *\r\n * See the co-routine section of the WEB documentation for information on\r\n * passing data between tasks and co-routines and between ISR's and\r\n * co-routines.\r\n *\r\n * @param xHandle The handle of the calling co-routine.  This is the xHandle\r\n * parameter of the co-routine function.\r\n *\r\n * @param pxQueue The handle of the queue on which the data will be posted.\r\n * The handle is obtained as the return value when the queue is created using\r\n * the xQueueCreate() API function.\r\n *\r\n * @param pvItemToQueue A pointer to the data being posted onto the queue.\r\n * The number of bytes of each queued item is specified when the queue is\r\n * created.  This number of bytes is copied from pvItemToQueue into the queue\r\n * itself.\r\n *\r\n * @param xTickToDelay The number of ticks that the co-routine should block\r\n * to wait for space to become available on the queue, should space not be\r\n * available immediately. The actual amount of time this equates to is defined\r\n * by configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant\r\n * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see example\r\n * below).\r\n *\r\n * @param pxResult The variable pointed to by pxResult will be set to pdPASS if\r\n * data was successfully posted onto the queue, otherwise it will be set to an\r\n * error defined within ProjDefs.h.\r\n *\r\n * Example usage:\r\n   <pre>\r\n // Co-routine function that blocks for a fixed period then posts a number onto\r\n // a queue.\r\n static void prvCoRoutineFlashTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )\r\n {\r\n // Variables in co-routines must be declared static if they must maintain value across a blocking call.\r\n static BaseType_t xNumberToPost = 0;\r\n static BaseType_t xResult;\r\n\r\n    // Co-routines must begin with a call to crSTART().\r\n    crSTART( xHandle );\r\n\r\n    for( ;; )\r\n    {\r\n        // This assumes the queue has already been created.\r\n        crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );\r\n\r\n        if( xResult != pdPASS )\r\n        {\r\n            // The message was not posted!\r\n        }\r\n\r\n        // Increment the number to be posted onto the queue.\r\n        xNumberToPost++;\r\n\r\n        // Delay for 100 ticks.\r\n        crDELAY( xHandle, 100 );\r\n    }\r\n\r\n    // Co-routines must end with a call to crEND().\r\n    crEND();\r\n }</pre>\r\n * \\defgroup crQUEUE_SEND crQUEUE_SEND\r\n * \\ingroup Tasks\r\n */\r\n#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult )\t\t\t\\\r\n{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t*( pxResult ) = xQueueCRSend( ( pxQueue) , ( pvItemToQueue) , ( xTicksToWait ) );\t\\\r\n\tif( *( pxResult ) == errQUEUE_BLOCKED )\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\tcrSET_STATE0( ( xHandle ) );\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t*pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 );\t\t\t\t\t\\\r\n\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\tif( *pxResult == errQUEUE_YIELD )\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\tcrSET_STATE1( ( xHandle ) );\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t*pxResult = pdPASS;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n}\r\n\r\n/**\r\n * croutine. h\r\n * <pre>\r\n  crQUEUE_RECEIVE(\r\n                     CoRoutineHandle_t xHandle,\r\n                     QueueHandle_t pxQueue,\r\n                     void *pvBuffer,\r\n                     TickType_t xTicksToWait,\r\n                     BaseType_t *pxResult\r\n                 )</pre>\r\n *\r\n * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine\r\n * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.\r\n *\r\n * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas\r\n * xQueueSend() and xQueueReceive() can only be used from tasks.\r\n *\r\n * crQUEUE_RECEIVE can only be called from the co-routine function itself - not\r\n * from within a function called by the co-routine function.  This is because\r\n * co-routines do not maintain their own stack.\r\n *\r\n * See the co-routine section of the WEB documentation for information on\r\n * passing data between tasks and co-routines and between ISR's and\r\n * co-routines.\r\n *\r\n * @param xHandle The handle of the calling co-routine.  This is the xHandle\r\n * parameter of the co-routine function.\r\n *\r\n * @param pxQueue The handle of the queue from which the data will be received.\r\n * The handle is obtained as the return value when the queue is created using\r\n * the xQueueCreate() API function.\r\n *\r\n * @param pvBuffer The buffer into which the received item is to be copied.\r\n * The number of bytes of each queued item is specified when the queue is\r\n * created.  This number of bytes is copied into pvBuffer.\r\n *\r\n * @param xTickToDelay The number of ticks that the co-routine should block\r\n * to wait for data to become available from the queue, should data not be\r\n * available immediately. The actual amount of time this equates to is defined\r\n * by configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant\r\n * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see the\r\n * crQUEUE_SEND example).\r\n *\r\n * @param pxResult The variable pointed to by pxResult will be set to pdPASS if\r\n * data was successfully retrieved from the queue, otherwise it will be set to\r\n * an error code as defined within ProjDefs.h.\r\n *\r\n * Example usage:\r\n <pre>\r\n // A co-routine receives the number of an LED to flash from a queue.  It\r\n // blocks on the queue until the number is received.\r\n static void prvCoRoutineFlashWorkTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )\r\n {\r\n // Variables in co-routines must be declared static if they must maintain value across a blocking call.\r\n static BaseType_t xResult;\r\n static UBaseType_t uxLEDToFlash;\r\n\r\n    // All co-routines must start with a call to crSTART().\r\n    crSTART( xHandle );\r\n\r\n    for( ;; )\r\n    {\r\n        // Wait for data to become available on the queue.\r\n        crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );\r\n\r\n        if( xResult == pdPASS )\r\n        {\r\n            // We received the LED to flash - flash it!\r\n            vParTestToggleLED( uxLEDToFlash );\r\n        }\r\n    }\r\n\r\n    crEND();\r\n }</pre>\r\n * \\defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE\r\n * \\ingroup Tasks\r\n */\r\n#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult )\t\t\t\\\r\n{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t*( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), ( xTicksToWait ) );\t\t\\\r\n\tif( *( pxResult ) == errQUEUE_BLOCKED ) \t\t\t\t\t\t\t\t\t\t\t\\\r\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\tcrSET_STATE0( ( xHandle ) );\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t*( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), 0 );\t\t\t\t\\\r\n\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\tif( *( pxResult ) == errQUEUE_YIELD )\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\tcrSET_STATE1( ( xHandle ) );\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t*( pxResult ) = pdPASS;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n}\r\n\r\n/**\r\n * croutine. h\r\n * <pre>\r\n  crQUEUE_SEND_FROM_ISR(\r\n                            QueueHandle_t pxQueue,\r\n                            void *pvItemToQueue,\r\n                            BaseType_t xCoRoutinePreviouslyWoken\r\n                       )</pre>\r\n *\r\n * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the\r\n * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()\r\n * functions used by tasks.\r\n *\r\n * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to\r\n * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and\r\n * xQueueReceiveFromISR() can only be used to pass data between a task and and\r\n * ISR.\r\n *\r\n * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue\r\n * that is being used from within a co-routine.\r\n *\r\n * See the co-routine section of the WEB documentation for information on\r\n * passing data between tasks and co-routines and between ISR's and\r\n * co-routines.\r\n *\r\n * @param xQueue The handle to the queue on which the item is to be posted.\r\n *\r\n * @param pvItemToQueue A pointer to the item that is to be placed on the\r\n * queue.  The size of the items the queue will hold was defined when the\r\n * queue was created, so this many bytes will be copied from pvItemToQueue\r\n * into the queue storage area.\r\n *\r\n * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto\r\n * the same queue multiple times from a single interrupt.  The first call\r\n * should always pass in pdFALSE.  Subsequent calls should pass in\r\n * the value returned from the previous call.\r\n *\r\n * @return pdTRUE if a co-routine was woken by posting onto the queue.  This is\r\n * used by the ISR to determine if a context switch may be required following\r\n * the ISR.\r\n *\r\n * Example usage:\r\n <pre>\r\n // A co-routine that blocks on a queue waiting for characters to be received.\r\n static void vReceivingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )\r\n {\r\n char cRxedChar;\r\n BaseType_t xResult;\r\n\r\n     // All co-routines must start with a call to crSTART().\r\n     crSTART( xHandle );\r\n\r\n     for( ;; )\r\n     {\r\n         // Wait for data to become available on the queue.  This assumes the\r\n         // queue xCommsRxQueue has already been created!\r\n         crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );\r\n\r\n         // Was a character received?\r\n         if( xResult == pdPASS )\r\n         {\r\n             // Process the character here.\r\n         }\r\n     }\r\n\r\n     // All co-routines must end with a call to crEND().\r\n     crEND();\r\n }\r\n\r\n // An ISR that uses a queue to send characters received on a serial port to\r\n // a co-routine.\r\n void vUART_ISR( void )\r\n {\r\n char cRxedChar;\r\n BaseType_t xCRWokenByPost = pdFALSE;\r\n\r\n     // We loop around reading characters until there are none left in the UART.\r\n     while( UART_RX_REG_NOT_EMPTY() )\r\n     {\r\n         // Obtain the character from the UART.\r\n         cRxedChar = UART_RX_REG;\r\n\r\n         // Post the character onto a queue.  xCRWokenByPost will be pdFALSE\r\n         // the first time around the loop.  If the post causes a co-routine\r\n         // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.\r\n         // In this manner we can ensure that if more than one co-routine is\r\n         // blocked on the queue only one is woken by this ISR no matter how\r\n         // many characters are posted to the queue.\r\n         xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );\r\n     }\r\n }</pre>\r\n * \\defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR\r\n * \\ingroup Tasks\r\n */\r\n#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) )\r\n\r\n\r\n/**\r\n * croutine. h\r\n * <pre>\r\n  crQUEUE_SEND_FROM_ISR(\r\n                            QueueHandle_t pxQueue,\r\n                            void *pvBuffer,\r\n                            BaseType_t * pxCoRoutineWoken\r\n                       )</pre>\r\n *\r\n * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the\r\n * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()\r\n * functions used by tasks.\r\n *\r\n * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to\r\n * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and\r\n * xQueueReceiveFromISR() can only be used to pass data between a task and and\r\n * ISR.\r\n *\r\n * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data\r\n * from a queue that is being used from within a co-routine (a co-routine\r\n * posted to the queue).\r\n *\r\n * See the co-routine section of the WEB documentation for information on\r\n * passing data between tasks and co-routines and between ISR's and\r\n * co-routines.\r\n *\r\n * @param xQueue The handle to the queue on which the item is to be posted.\r\n *\r\n * @param pvBuffer A pointer to a buffer into which the received item will be\r\n * placed.  The size of the items the queue will hold was defined when the\r\n * queue was created, so this many bytes will be copied from the queue into\r\n * pvBuffer.\r\n *\r\n * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become\r\n * available on the queue.  If crQUEUE_RECEIVE_FROM_ISR causes such a\r\n * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise\r\n * *pxCoRoutineWoken will remain unchanged.\r\n *\r\n * @return pdTRUE an item was successfully received from the queue, otherwise\r\n * pdFALSE.\r\n *\r\n * Example usage:\r\n <pre>\r\n // A co-routine that posts a character to a queue then blocks for a fixed\r\n // period.  The character is incremented each time.\r\n static void vSendingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )\r\n {\r\n // cChar holds its value while this co-routine is blocked and must therefore\r\n // be declared static.\r\n static char cCharToTx = 'a';\r\n BaseType_t xResult;\r\n\r\n     // All co-routines must start with a call to crSTART().\r\n     crSTART( xHandle );\r\n\r\n     for( ;; )\r\n     {\r\n         // Send the next character to the queue.\r\n         crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );\r\n\r\n         if( xResult == pdPASS )\r\n         {\r\n             // The character was successfully posted to the queue.\r\n         }\r\n\t\t else\r\n\t\t {\r\n\t\t\t// Could not post the character to the queue.\r\n\t\t }\r\n\r\n         // Enable the UART Tx interrupt to cause an interrupt in this\r\n\t\t // hypothetical UART.  The interrupt will obtain the character\r\n\t\t // from the queue and send it.\r\n\t\t ENABLE_RX_INTERRUPT();\r\n\r\n\t\t // Increment to the next character then block for a fixed period.\r\n\t\t // cCharToTx will maintain its value across the delay as it is\r\n\t\t // declared static.\r\n\t\t cCharToTx++;\r\n\t\t if( cCharToTx > 'x' )\r\n\t\t {\r\n\t\t\tcCharToTx = 'a';\r\n\t\t }\r\n\t\t crDELAY( 100 );\r\n     }\r\n\r\n     // All co-routines must end with a call to crEND().\r\n     crEND();\r\n }\r\n\r\n // An ISR that uses a queue to receive characters to send on a UART.\r\n void vUART_ISR( void )\r\n {\r\n char cCharToTx;\r\n BaseType_t xCRWokenByPost = pdFALSE;\r\n\r\n     while( UART_TX_REG_EMPTY() )\r\n     {\r\n         // Are there any characters in the queue waiting to be sent?\r\n\t\t // xCRWokenByPost will automatically be set to pdTRUE if a co-routine\r\n\t\t // is woken by the post - ensuring that only a single co-routine is\r\n\t\t // woken no matter how many times we go around this loop.\r\n         if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )\r\n\t\t {\r\n\t\t\t SEND_CHARACTER( cCharToTx );\r\n\t\t }\r\n     }\r\n }</pre>\r\n * \\defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR\r\n * \\ingroup Tasks\r\n */\r\n#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) )\r\n\r\n/*\r\n * This function is intended for internal use by the co-routine macros only.\r\n * The macro nature of the co-routine implementation requires that the\r\n * prototype appears here.  The function should not be used by application\r\n * writers.\r\n *\r\n * Removes the current co-routine from its ready list and places it in the\r\n * appropriate delayed list.\r\n */\r\nvoid vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList );\r\n\r\n/*\r\n * This function is intended for internal use by the queue implementation only.\r\n * The function should not be used by application writers.\r\n *\r\n * Removes the highest priority co-routine from the event list and places it in\r\n * the pending ready list.\r\n */\r\nBaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList );\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* CO_ROUTINE_H */\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RTOS/src/deprecated_definitions.h",
    "content": "/*\r\n    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r\n    All rights reserved\r\n\r\n    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r\n\r\n    This file is part of the FreeRTOS distribution.\r\n\r\n    FreeRTOS is free software; you can redistribute it and/or modify it under\r\n    the terms of the GNU General Public License (version 2) as published by the\r\n    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r\n\r\n    ***************************************************************************\r\n    >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r\n    >>!   distribute a combined work that includes FreeRTOS without being   !<<\r\n    >>!   obliged to provide the source code for proprietary components     !<<\r\n    >>!   outside of the FreeRTOS kernel.                                   !<<\r\n    ***************************************************************************\r\n\r\n    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r\n    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r\n    FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r\n    link: http://www.freertos.org/a00114.html\r\n\r\n    ***************************************************************************\r\n     *                                                                       *\r\n     *    FreeRTOS provides completely free yet professionally developed,    *\r\n     *    robust, strictly quality controlled, supported, and cross          *\r\n     *    platform software that is more than just the market leader, it     *\r\n     *    is the industry's de facto standard.                               *\r\n     *                                                                       *\r\n     *    Help yourself get started quickly while simultaneously helping     *\r\n     *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r\n     *    tutorial book, reference manual, or both:                          *\r\n     *    http://www.FreeRTOS.org/Documentation                              *\r\n     *                                                                       *\r\n    ***************************************************************************\r\n\r\n    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r\n    the FAQ page \"My application does not run, what could be wrong?\".  Have you\r\n    defined configASSERT()?\r\n\r\n    http://www.FreeRTOS.org/support - In return for receiving this top quality\r\n    embedded software for free we request you assist our global community by\r\n    participating in the support forum.\r\n\r\n    http://www.FreeRTOS.org/training - Investing in training allows your team to\r\n    be as productive as possible as early as possible.  Now you can receive\r\n    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r\n    Ltd, and the world's leading authority on the world's leading RTOS.\r\n\r\n    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r\n    including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r\n    compatible FAT file system, and our tiny thread aware UDP/IP stack.\r\n\r\n    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r\n    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r\n\r\n    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r\n    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r\n    licenses offer ticketed support, indemnification and commercial middleware.\r\n\r\n    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r\n    engineered and independently SIL3 certified version for use in safety and\r\n    mission critical applications that require provable dependability.\r\n\r\n    1 tab == 4 spaces!\r\n*/\r\n\r\n#ifndef DEPRECATED_DEFINITIONS_H\r\n#define DEPRECATED_DEFINITIONS_H\r\n\r\n\r\n/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a\r\npre-processor definition was used to ensure the pre-processor found the correct\r\nportmacro.h file for the port being used.  That scheme was deprecated in favour\r\nof setting the compiler's include path such that it found the correct\r\nportmacro.h file - removing the need for the constant and allowing the\r\nportmacro.h file to be located anywhere in relation to the port being used.  The\r\ndefinitions below remain in the code for backward compatibility only.  New\r\nprojects should not use them. */\r\n\r\n#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT\r\n\t#include \"..\\..\\Source\\portable\\owatcom\\16bitdos\\pc\\portmacro.h\"\r\n\ttypedef void ( __interrupt __far *pxISR )();\r\n#endif\r\n\r\n#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT\r\n\t#include \"..\\..\\Source\\portable\\owatcom\\16bitdos\\flsh186\\portmacro.h\"\r\n\ttypedef void ( __interrupt __far *pxISR )();\r\n#endif\r\n\r\n#ifdef GCC_MEGA_AVR\r\n\t#include \"../portable/GCC/ATMega323/portmacro.h\"\r\n#endif\r\n\r\n#ifdef IAR_MEGA_AVR\r\n\t#include \"../portable/IAR/ATMega323/portmacro.h\"\r\n#endif\r\n\r\n#ifdef MPLAB_PIC24_PORT\r\n\t#include \"../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h\"\r\n#endif\r\n\r\n#ifdef MPLAB_DSPIC_PORT\r\n\t#include \"../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h\"\r\n#endif\r\n\r\n#ifdef MPLAB_PIC18F_PORT\r\n\t#include \"../../Source/portable/MPLAB/PIC18F/portmacro.h\"\r\n#endif\r\n\r\n#ifdef MPLAB_PIC32MX_PORT\r\n\t#include \"../../Source/portable/MPLAB/PIC32MX/portmacro.h\"\r\n#endif\r\n\r\n#ifdef _FEDPICC\r\n\t#include \"libFreeRTOS/Include/portmacro.h\"\r\n#endif\r\n\r\n#ifdef SDCC_CYGNAL\r\n\t#include \"../../Source/portable/SDCC/Cygnal/portmacro.h\"\r\n#endif\r\n\r\n#ifdef GCC_ARM7\r\n\t#include \"../../Source/portable/GCC/ARM7_LPC2000/portmacro.h\"\r\n#endif\r\n\r\n#ifdef GCC_ARM7_ECLIPSE\r\n\t#include \"portmacro.h\"\r\n#endif\r\n\r\n#ifdef ROWLEY_LPC23xx\r\n\t#include \"../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h\"\r\n#endif\r\n\r\n#ifdef IAR_MSP430\r\n\t#include \"..\\..\\Source\\portable\\IAR\\MSP430\\portmacro.h\"\r\n#endif\r\n\r\n#ifdef GCC_MSP430\r\n\t#include \"../../Source/portable/GCC/MSP430F449/portmacro.h\"\r\n#endif\r\n\r\n#ifdef ROWLEY_MSP430\r\n\t#include \"../../Source/portable/Rowley/MSP430F449/portmacro.h\"\r\n#endif\r\n\r\n#ifdef ARM7_LPC21xx_KEIL_RVDS\r\n\t#include \"..\\..\\Source\\portable\\RVDS\\ARM7_LPC21xx\\portmacro.h\"\r\n#endif\r\n\r\n#ifdef SAM7_GCC\r\n\t#include \"../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h\"\r\n#endif\r\n\r\n#ifdef SAM7_IAR\r\n\t#include \"..\\..\\Source\\portable\\IAR\\AtmelSAM7S64\\portmacro.h\"\r\n#endif\r\n\r\n#ifdef SAM9XE_IAR\r\n\t#include \"..\\..\\Source\\portable\\IAR\\AtmelSAM9XE\\portmacro.h\"\r\n#endif\r\n\r\n#ifdef LPC2000_IAR\r\n\t#include \"..\\..\\Source\\portable\\IAR\\LPC2000\\portmacro.h\"\r\n#endif\r\n\r\n#ifdef STR71X_IAR\r\n\t#include \"..\\..\\Source\\portable\\IAR\\STR71x\\portmacro.h\"\r\n#endif\r\n\r\n#ifdef STR75X_IAR\r\n\t#include \"..\\..\\Source\\portable\\IAR\\STR75x\\portmacro.h\"\r\n#endif\r\n\r\n#ifdef STR75X_GCC\r\n\t#include \"..\\..\\Source\\portable\\GCC\\STR75x\\portmacro.h\"\r\n#endif\r\n\r\n#ifdef STR91X_IAR\r\n\t#include \"..\\..\\Source\\portable\\IAR\\STR91x\\portmacro.h\"\r\n#endif\r\n\r\n#ifdef GCC_H8S\r\n\t#include \"../../Source/portable/GCC/H8S2329/portmacro.h\"\r\n#endif\r\n\r\n#ifdef GCC_AT91FR40008\r\n\t#include \"../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h\"\r\n#endif\r\n\r\n#ifdef RVDS_ARMCM3_LM3S102\r\n\t#include \"../../Source/portable/RVDS/ARM_CM3/portmacro.h\"\r\n#endif\r\n\r\n#ifdef GCC_ARMCM3_LM3S102\r\n\t#include \"../../Source/portable/GCC/ARM_CM3/portmacro.h\"\r\n#endif\r\n\r\n#ifdef GCC_ARMCM3\r\n\t#include \"../../Source/portable/GCC/ARM_CM3/portmacro.h\"\r\n#endif\r\n\r\n#ifdef IAR_ARM_CM3\r\n\t#include \"../../Source/portable/IAR/ARM_CM3/portmacro.h\"\r\n#endif\r\n\r\n#ifdef IAR_ARMCM3_LM\r\n\t#include \"../../Source/portable/IAR/ARM_CM3/portmacro.h\"\r\n#endif\r\n\r\n#ifdef HCS12_CODE_WARRIOR\r\n\t#include \"../../Source/portable/CodeWarrior/HCS12/portmacro.h\"\r\n#endif\r\n\r\n#ifdef MICROBLAZE_GCC\r\n\t#include \"../../Source/portable/GCC/MicroBlaze/portmacro.h\"\r\n#endif\r\n\r\n#ifdef TERN_EE\r\n\t#include \"..\\..\\Source\\portable\\Paradigm\\Tern_EE\\small\\portmacro.h\"\r\n#endif\r\n\r\n#ifdef GCC_HCS12\r\n\t#include \"../../Source/portable/GCC/HCS12/portmacro.h\"\r\n#endif\r\n\r\n#ifdef GCC_MCF5235\r\n    #include \"../../Source/portable/GCC/MCF5235/portmacro.h\"\r\n#endif\r\n\r\n#ifdef COLDFIRE_V2_GCC\r\n\t#include \"../../../Source/portable/GCC/ColdFire_V2/portmacro.h\"\r\n#endif\r\n\r\n#ifdef COLDFIRE_V2_CODEWARRIOR\r\n\t#include \"../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h\"\r\n#endif\r\n\r\n#ifdef GCC_PPC405\r\n\t#include \"../../Source/portable/GCC/PPC405_Xilinx/portmacro.h\"\r\n#endif\r\n\r\n#ifdef GCC_PPC440\r\n\t#include \"../../Source/portable/GCC/PPC440_Xilinx/portmacro.h\"\r\n#endif\r\n\r\n#ifdef _16FX_SOFTUNE\r\n\t#include \"..\\..\\Source\\portable\\Softune\\MB96340\\portmacro.h\"\r\n#endif\r\n\r\n#ifdef BCC_INDUSTRIAL_PC_PORT\r\n\t/* A short file name has to be used in place of the normal\r\n\tFreeRTOSConfig.h when using the Borland compiler. */\r\n\t#include \"frconfig.h\"\r\n\t#include \"..\\portable\\BCC\\16BitDOS\\PC\\prtmacro.h\"\r\n    typedef void ( __interrupt __far *pxISR )();\r\n#endif\r\n\r\n#ifdef BCC_FLASH_LITE_186_PORT\r\n\t/* A short file name has to be used in place of the normal\r\n\tFreeRTOSConfig.h when using the Borland compiler. */\r\n\t#include \"frconfig.h\"\r\n\t#include \"..\\portable\\BCC\\16BitDOS\\flsh186\\prtmacro.h\"\r\n    typedef void ( __interrupt __far *pxISR )();\r\n#endif\r\n\r\n#ifdef __GNUC__\r\n   #ifdef __AVR32_AVR32A__\r\n\t   #include \"portmacro.h\"\r\n   #endif\r\n#endif\r\n\r\n#ifdef __ICCAVR32__\r\n   #ifdef __CORE__\r\n      #if __CORE__ == __AVR32A__\r\n\t      #include \"portmacro.h\"\r\n      #endif\r\n   #endif\r\n#endif\r\n\r\n#ifdef __91467D\r\n\t#include \"portmacro.h\"\r\n#endif\r\n\r\n#ifdef __96340\r\n\t#include \"portmacro.h\"\r\n#endif\r\n\r\n\r\n#ifdef __IAR_V850ES_Fx3__\r\n\t#include \"../../Source/portable/IAR/V850ES/portmacro.h\"\r\n#endif\r\n\r\n#ifdef __IAR_V850ES_Jx3__\r\n\t#include \"../../Source/portable/IAR/V850ES/portmacro.h\"\r\n#endif\r\n\r\n#ifdef __IAR_V850ES_Jx3_L__\r\n\t#include \"../../Source/portable/IAR/V850ES/portmacro.h\"\r\n#endif\r\n\r\n#ifdef __IAR_V850ES_Jx2__\r\n\t#include \"../../Source/portable/IAR/V850ES/portmacro.h\"\r\n#endif\r\n\r\n#ifdef __IAR_V850ES_Hx2__\r\n\t#include \"../../Source/portable/IAR/V850ES/portmacro.h\"\r\n#endif\r\n\r\n#ifdef __IAR_78K0R_Kx3__\r\n\t#include \"../../Source/portable/IAR/78K0R/portmacro.h\"\r\n#endif\r\n\r\n#ifdef __IAR_78K0R_Kx3L__\r\n\t#include \"../../Source/portable/IAR/78K0R/portmacro.h\"\r\n#endif\r\n\r\n#endif /* DEPRECATED_DEFINITIONS_H */\r\n\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RTOS/src/event_groups.c",
    "content": "/*\r\n    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r\n    All rights reserved\r\n\r\n    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r\n\r\n    This file is part of the FreeRTOS distribution.\r\n\r\n    FreeRTOS is free software; you can redistribute it and/or modify it under\r\n    the terms of the GNU General Public License (version 2) as published by the\r\n    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r\n\r\n    ***************************************************************************\r\n    >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r\n    >>!   distribute a combined work that includes FreeRTOS without being   !<<\r\n    >>!   obliged to provide the source code for proprietary components     !<<\r\n    >>!   outside of the FreeRTOS kernel.                                   !<<\r\n    ***************************************************************************\r\n\r\n    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r\n    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r\n    FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r\n    link: http://www.freertos.org/a00114.html\r\n\r\n    ***************************************************************************\r\n     *                                                                       *\r\n     *    FreeRTOS provides completely free yet professionally developed,    *\r\n     *    robust, strictly quality controlled, supported, and cross          *\r\n     *    platform software that is more than just the market leader, it     *\r\n     *    is the industry's de facto standard.                               *\r\n     *                                                                       *\r\n     *    Help yourself get started quickly while simultaneously helping     *\r\n     *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r\n     *    tutorial book, reference manual, or both:                          *\r\n     *    http://www.FreeRTOS.org/Documentation                              *\r\n     *                                                                       *\r\n    ***************************************************************************\r\n\r\n    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r\n    the FAQ page \"My application does not run, what could be wrong?\".  Have you\r\n    defined configASSERT()?\r\n\r\n    http://www.FreeRTOS.org/support - In return for receiving this top quality\r\n    embedded software for free we request you assist our global community by\r\n    participating in the support forum.\r\n\r\n    http://www.FreeRTOS.org/training - Investing in training allows your team to\r\n    be as productive as possible as early as possible.  Now you can receive\r\n    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r\n    Ltd, and the world's leading authority on the world's leading RTOS.\r\n\r\n    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r\n    including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r\n    compatible FAT file system, and our tiny thread aware UDP/IP stack.\r\n\r\n    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r\n    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r\n\r\n    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r\n    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r\n    licenses offer ticketed support, indemnification and commercial middleware.\r\n\r\n    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r\n    engineered and independently SIL3 certified version for use in safety and\r\n    mission critical applications that require provable dependability.\r\n\r\n    1 tab == 4 spaces!\r\n*/\r\n\r\n/* Standard includes. */\r\n#include <stdlib.h>\r\n\r\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r\nall the API functions to use the MPU wrappers.  That should only be done when\r\ntask.h is included from an application file. */\r\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r\n\r\n/* FreeRTOS includes. */\r\n#include \"FreeRTOS.h\"\r\n#include \"task.h\"\r\n#include \"timers.h\"\r\n#include \"event_groups.h\"\r\n\r\n/* Lint e961 and e750 are suppressed as a MISRA exception justified because the\r\nMPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the\r\nheader files above, but not in this file, in order to generate the correct\r\nprivileged Vs unprivileged linkage and placement. */\r\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */\r\n\r\n#if ( INCLUDE_xEventGroupSetBitFromISR == 1 ) && ( configUSE_TIMERS == 0 )\r\n\t#error configUSE_TIMERS must be set to 1 to make the xEventGroupSetBitFromISR() function available.\r\n#endif\r\n\r\n#if ( INCLUDE_xEventGroupSetBitFromISR == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 0 )\r\n\t#error INCLUDE_xTimerPendFunctionCall must also be set to one to make the xEventGroupSetBitFromISR() function available.\r\n#endif\r\n\r\n/* The following bit fields convey control information in a task's event list\r\nitem value.  It is important they don't clash with the\r\ntaskEVENT_LIST_ITEM_VALUE_IN_USE definition. */\r\n#if configUSE_16_BIT_TICKS == 1\r\n\t#define eventCLEAR_EVENTS_ON_EXIT_BIT\t0x0100U\r\n\t#define eventUNBLOCKED_DUE_TO_BIT_SET\t0x0200U\r\n\t#define eventWAIT_FOR_ALL_BITS\t\t\t0x0400U\r\n\t#define eventEVENT_BITS_CONTROL_BYTES\t0xff00U\r\n#else\r\n\t#define eventCLEAR_EVENTS_ON_EXIT_BIT\t0x01000000UL\r\n\t#define eventUNBLOCKED_DUE_TO_BIT_SET\t0x02000000UL\r\n\t#define eventWAIT_FOR_ALL_BITS\t\t\t0x04000000UL\r\n\t#define eventEVENT_BITS_CONTROL_BYTES\t0xff000000UL\r\n#endif\r\n\r\ntypedef struct xEventGroupDefinition\r\n{\r\n\tEventBits_t uxEventBits;\r\n\tList_t xTasksWaitingForBits;\t\t/*< List of tasks waiting for a bit to be set. */\r\n\r\n\t#if( configUSE_TRACE_FACILITY == 1 )\r\n\t\tUBaseType_t uxEventGroupNumber;\r\n\t#endif\r\n\r\n} EventGroup_t;\r\n\r\n/*-----------------------------------------------------------*/\r\n\r\n/*\r\n * Test the bits set in uxCurrentEventBits to see if the wait condition is met.\r\n * The wait condition is defined by xWaitForAllBits.  If xWaitForAllBits is\r\n * pdTRUE then the wait condition is met if all the bits set in uxBitsToWaitFor\r\n * are also set in uxCurrentEventBits.  If xWaitForAllBits is pdFALSE then the\r\n * wait condition is met if any of the bits set in uxBitsToWait for are also set\r\n * in uxCurrentEventBits.\r\n */\r\nstatic BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits );\r\n\r\n/*-----------------------------------------------------------*/\r\n\r\nEventGroupHandle_t xEventGroupCreate( void )\r\n{\r\nEventGroup_t *pxEventBits;\r\n\r\n\tpxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) );\r\n\tif( pxEventBits != NULL )\r\n\t{\r\n\t\tpxEventBits->uxEventBits = 0;\r\n\t\tvListInitialise( &( pxEventBits->xTasksWaitingForBits ) );\r\n\t\ttraceEVENT_GROUP_CREATE( pxEventBits );\r\n\t}\r\n\telse\r\n\t{\r\n\t\ttraceEVENT_GROUP_CREATE_FAILED();\r\n\t}\r\n\r\n\treturn ( EventGroupHandle_t ) pxEventBits;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nEventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait )\r\n{\r\nEventBits_t uxOriginalBitValue, uxReturn;\r\nEventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;\r\nBaseType_t xAlreadyYielded;\r\nBaseType_t xTimeoutOccurred = pdFALSE;\r\n\r\n\tconfigASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );\r\n\tconfigASSERT( uxBitsToWaitFor != 0 );\r\n\t#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\r\n\t{\r\n\t\tconfigASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );\r\n\t}\r\n\t#endif\r\n\r\n\tvTaskSuspendAll();\r\n\t{\r\n\t\tuxOriginalBitValue = pxEventBits->uxEventBits;\r\n\r\n\t\t( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet );\r\n\r\n\t\tif( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor )\r\n\t\t{\r\n\t\t\t/* All the rendezvous bits are now set - no need to block. */\r\n\t\t\tuxReturn = ( uxOriginalBitValue | uxBitsToSet );\r\n\r\n\t\t\t/* Rendezvous always clear the bits.  They will have been cleared\r\n\t\t\talready unless this is the only task in the rendezvous. */\r\n\t\t\tpxEventBits->uxEventBits &= ~uxBitsToWaitFor;\r\n\r\n\t\t\txTicksToWait = 0;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tif( xTicksToWait != ( TickType_t ) 0 )\r\n\t\t\t{\r\n\t\t\t\ttraceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor );\r\n\r\n\t\t\t\t/* Store the bits that the calling task is waiting for in the\r\n\t\t\t\ttask's event list item so the kernel knows when a match is\r\n\t\t\t\tfound.  Then enter the blocked state. */\r\n\t\t\t\tvTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait );\r\n\r\n\t\t\t\t/* This assignment is obsolete as uxReturn will get set after\r\n\t\t\t\tthe task unblocks, but some compilers mistakenly generate a\r\n\t\t\t\twarning about uxReturn being returned without being set if the\r\n\t\t\t\tassignment is omitted. */\r\n\t\t\t\tuxReturn = 0;\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\t/* The rendezvous bits were not set, but no block time was\r\n\t\t\t\tspecified - just return the current event bit value. */\r\n\t\t\t\tuxReturn = pxEventBits->uxEventBits;\r\n\t\t\t}\r\n\t\t}\r\n\t}\r\n\txAlreadyYielded = xTaskResumeAll();\r\n\r\n\tif( xTicksToWait != ( TickType_t ) 0 )\r\n\t{\r\n\t\tif( xAlreadyYielded == pdFALSE )\r\n\t\t{\r\n\t\t\tportYIELD_WITHIN_API();\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t}\r\n\r\n\t\t/* The task blocked to wait for its required bits to be set - at this\r\n\t\tpoint either the required bits were set or the block time expired.  If\r\n\t\tthe required bits were set they will have been stored in the task's\r\n\t\tevent list item, and they should now be retrieved then cleared. */\r\n\t\tuxReturn = uxTaskResetEventItemValue();\r\n\r\n\t\tif( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )\r\n\t\t{\r\n\t\t\t/* The task timed out, just return the current event bit value. */\r\n\t\t\ttaskENTER_CRITICAL();\r\n\t\t\t{\r\n\t\t\t\tuxReturn = pxEventBits->uxEventBits;\r\n\r\n\t\t\t\t/* Although the task got here because it timed out before the\r\n\t\t\t\tbits it was waiting for were set, it is possible that since it\r\n\t\t\t\tunblocked another task has set the bits.  If this is the case\r\n\t\t\t\tthen it needs to clear the bits before exiting. */\r\n\t\t\t\tif( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor )\r\n\t\t\t\t{\r\n\t\t\t\t\tpxEventBits->uxEventBits &= ~uxBitsToWaitFor;\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\ttaskEXIT_CRITICAL();\r\n\r\n\t\t\txTimeoutOccurred = pdTRUE;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\t/* The task unblocked because the bits were set. */\r\n\t\t}\r\n\r\n\t\t/* Control bits might be set as the task had blocked should not be\r\n\t\treturned. */\r\n\t\tuxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;\r\n\t}\r\n\r\n\ttraceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred );\r\n\r\n\treturn uxReturn;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nEventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait )\r\n{\r\nEventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;\r\nEventBits_t uxReturn, uxControlBits = 0;\r\nBaseType_t xWaitConditionMet, xAlreadyYielded;\r\nBaseType_t xTimeoutOccurred = pdFALSE;\r\n\r\n\t/* Check the user is not attempting to wait on the bits used by the kernel\r\n\titself, and that at least one bit is being requested. */\r\n\tconfigASSERT( xEventGroup );\r\n\tconfigASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );\r\n\tconfigASSERT( uxBitsToWaitFor != 0 );\r\n\t#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\r\n\t{\r\n\t\tconfigASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );\r\n\t}\r\n\t#endif\r\n\r\n\tvTaskSuspendAll();\r\n\t{\r\n\t\tconst EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits;\r\n\r\n\t\t/* Check to see if the wait condition is already met or not. */\r\n\t\txWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits );\r\n\r\n\t\tif( xWaitConditionMet != pdFALSE )\r\n\t\t{\r\n\t\t\t/* The wait condition has already been met so there is no need to\r\n\t\t\tblock. */\r\n\t\t\tuxReturn = uxCurrentEventBits;\r\n\t\t\txTicksToWait = ( TickType_t ) 0;\r\n\r\n\t\t\t/* Clear the wait bits if requested to do so. */\r\n\t\t\tif( xClearOnExit != pdFALSE )\r\n\t\t\t{\r\n\t\t\t\tpxEventBits->uxEventBits &= ~uxBitsToWaitFor;\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\t\t}\r\n\t\telse if( xTicksToWait == ( TickType_t ) 0 )\r\n\t\t{\r\n\t\t\t/* The wait condition has not been met, but no block time was\r\n\t\t\tspecified, so just return the current value. */\r\n\t\t\tuxReturn = uxCurrentEventBits;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\t/* The task is going to block to wait for its required bits to be\r\n\t\t\tset.  uxControlBits are used to remember the specified behaviour of\r\n\t\t\tthis call to xEventGroupWaitBits() - for use when the event bits\r\n\t\t\tunblock the task. */\r\n\t\t\tif( xClearOnExit != pdFALSE )\r\n\t\t\t{\r\n\t\t\t\tuxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT;\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\r\n\t\t\tif( xWaitForAllBits != pdFALSE )\r\n\t\t\t{\r\n\t\t\t\tuxControlBits |= eventWAIT_FOR_ALL_BITS;\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\r\n\t\t\t/* Store the bits that the calling task is waiting for in the\r\n\t\t\ttask's event list item so the kernel knows when a match is\r\n\t\t\tfound.  Then enter the blocked state. */\r\n\t\t\tvTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait );\r\n\r\n\t\t\t/* This is obsolete as it will get set after the task unblocks, but\r\n\t\t\tsome compilers mistakenly generate a warning about the variable\r\n\t\t\tbeing returned without being set if it is not done. */\r\n\t\t\tuxReturn = 0;\r\n\r\n\t\t\ttraceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor );\r\n\t\t}\r\n\t}\r\n\txAlreadyYielded = xTaskResumeAll();\r\n\r\n\tif( xTicksToWait != ( TickType_t ) 0 )\r\n\t{\r\n\t\tif( xAlreadyYielded == pdFALSE )\r\n\t\t{\r\n\t\t\tportYIELD_WITHIN_API();\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t}\r\n\r\n\t\t/* The task blocked to wait for its required bits to be set - at this\r\n\t\tpoint either the required bits were set or the block time expired.  If\r\n\t\tthe required bits were set they will have been stored in the task's\r\n\t\tevent list item, and they should now be retrieved then cleared. */\r\n\t\tuxReturn = uxTaskResetEventItemValue();\r\n\r\n\t\tif( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )\r\n\t\t{\r\n\t\t\ttaskENTER_CRITICAL();\r\n\t\t\t{\r\n\t\t\t\t/* The task timed out, just return the current event bit value. */\r\n\t\t\t\tuxReturn = pxEventBits->uxEventBits;\r\n\r\n\t\t\t\t/* It is possible that the event bits were updated between this\r\n\t\t\t\ttask leaving the Blocked state and running again. */\r\n\t\t\t\tif( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE )\r\n\t\t\t\t{\r\n\t\t\t\t\tif( xClearOnExit != pdFALSE )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tpxEventBits->uxEventBits &= ~uxBitsToWaitFor;\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\ttaskEXIT_CRITICAL();\r\n\r\n\t\t\t/* Prevent compiler warnings when trace macros are not used. */\r\n\t\t\txTimeoutOccurred = pdFALSE;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\t/* The task unblocked because the bits were set. */\r\n\t\t}\r\n\r\n\t\t/* The task blocked so control bits may have been set. */\r\n\t\tuxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;\r\n\t}\r\n\ttraceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred );\r\n\r\n\treturn uxReturn;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nEventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear )\r\n{\r\nEventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;\r\nEventBits_t uxReturn;\r\n\r\n\t/* Check the user is not attempting to clear the bits used by the kernel\r\n\titself. */\r\n\tconfigASSERT( xEventGroup );\r\n\tconfigASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 );\r\n\r\n\ttaskENTER_CRITICAL();\r\n\t{\r\n\t\ttraceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear );\r\n\r\n\t\t/* The value returned is the event group value prior to the bits being\r\n\t\tcleared. */\r\n\t\tuxReturn = pxEventBits->uxEventBits;\r\n\r\n\t\t/* Clear the bits. */\r\n\t\tpxEventBits->uxEventBits &= ~uxBitsToClear;\r\n\t}\r\n\ttaskEXIT_CRITICAL();\r\n\r\n\treturn uxReturn;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )\r\n\r\n\tBaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear )\r\n\t{\r\n\t\tBaseType_t xReturn;\r\n\r\n\t\ttraceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear );\r\n\t\txReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL );\r\n\r\n\t\treturn xReturn;\r\n\t}\r\n\r\n#endif\r\n/*-----------------------------------------------------------*/\r\n\r\nEventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup )\r\n{\r\nUBaseType_t uxSavedInterruptStatus;\r\nEventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;\r\nEventBits_t uxReturn;\r\n\r\n\tuxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\r\n\t{\r\n\t\tuxReturn = pxEventBits->uxEventBits;\r\n\t}\r\n\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\r\n\r\n\treturn uxReturn;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nEventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet )\r\n{\r\nListItem_t *pxListItem, *pxNext;\r\nListItem_t const *pxListEnd;\r\nList_t *pxList;\r\nEventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits;\r\nEventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;\r\nBaseType_t xMatchFound = pdFALSE;\r\n\r\n\t/* Check the user is not attempting to set the bits used by the kernel\r\n\titself. */\r\n\tconfigASSERT( xEventGroup );\r\n\tconfigASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 );\r\n\r\n\tpxList = &( pxEventBits->xTasksWaitingForBits );\r\n\tpxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */\r\n\tvTaskSuspendAll();\r\n\t{\r\n\t\ttraceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet );\r\n\r\n\t\tpxListItem = listGET_HEAD_ENTRY( pxList );\r\n\r\n\t\t/* Set the bits. */\r\n\t\tpxEventBits->uxEventBits |= uxBitsToSet;\r\n\r\n\t\t/* See if the new bit value should unblock any tasks. */\r\n\t\twhile( pxListItem != pxListEnd )\r\n\t\t{\r\n\t\t\tpxNext = listGET_NEXT( pxListItem );\r\n\t\t\tuxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem );\r\n\t\t\txMatchFound = pdFALSE;\r\n\r\n\t\t\t/* Split the bits waited for from the control bits. */\r\n\t\t\tuxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES;\r\n\t\t\tuxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES;\r\n\r\n\t\t\tif( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 )\r\n\t\t\t{\r\n\t\t\t\t/* Just looking for single bit being set. */\r\n\t\t\t\tif( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 )\r\n\t\t\t\t{\r\n\t\t\t\t\txMatchFound = pdTRUE;\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\telse if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor )\r\n\t\t\t{\r\n\t\t\t\t/* All bits are set. */\r\n\t\t\t\txMatchFound = pdTRUE;\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\t/* Need all bits to be set, but not all the bits were set. */\r\n\t\t\t}\r\n\r\n\t\t\tif( xMatchFound != pdFALSE )\r\n\t\t\t{\r\n\t\t\t\t/* The bits match.  Should the bits be cleared on exit? */\r\n\t\t\t\tif( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 )\r\n\t\t\t\t{\r\n\t\t\t\t\tuxBitsToClear |= uxBitsWaitedFor;\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\r\n\t\t\t\t/* Store the actual event flag value in the task's event list\r\n\t\t\t\titem before removing the task from the event list.  The\r\n\t\t\t\teventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows\r\n\t\t\t\tthat is was unblocked due to its required bits matching, rather\r\n\t\t\t\tthan because it timed out. */\r\n\t\t\t\t( void ) xTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET );\r\n\t\t\t}\r\n\r\n\t\t\t/* Move onto the next list item.  Note pxListItem->pxNext is not\r\n\t\t\tused here as the list item may have been removed from the event list\r\n\t\t\tand inserted into the ready/pending reading list. */\r\n\t\t\tpxListItem = pxNext;\r\n\t\t}\r\n\r\n\t\t/* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT\r\n\t\tbit was set in the control word. */\r\n\t\tpxEventBits->uxEventBits &= ~uxBitsToClear;\r\n\t}\r\n\t( void ) xTaskResumeAll();\r\n\r\n\treturn pxEventBits->uxEventBits;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nvoid vEventGroupDelete( EventGroupHandle_t xEventGroup )\r\n{\r\nEventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;\r\nconst List_t *pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits );\r\n\r\n\tvTaskSuspendAll();\r\n\t{\r\n\t\ttraceEVENT_GROUP_DELETE( xEventGroup );\r\n\r\n\t\twhile( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 )\r\n\t\t{\r\n\t\t\t/* Unblock the task, returning 0 as the event list is being deleted\r\n\t\t\tand\tcannot therefore have any bits set. */\r\n\t\t\tconfigASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) );\r\n\t\t\t( void ) xTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET );\r\n\t\t}\r\n\r\n\t\tvPortFree( pxEventBits );\r\n\t}\r\n\t( void ) xTaskResumeAll();\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\n/* For internal use only - execute a 'set bits' command that was pended from\r\nan interrupt. */\r\nvoid vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet )\r\n{\r\n\t( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet );\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\n/* For internal use only - execute a 'clear bits' command that was pended from\r\nan interrupt. */\r\nvoid vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear )\r\n{\r\n\t( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear );\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nstatic BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits )\r\n{\r\nBaseType_t xWaitConditionMet = pdFALSE;\r\n\r\n\tif( xWaitForAllBits == pdFALSE )\r\n\t{\r\n\t\t/* Task only has to wait for one bit within uxBitsToWaitFor to be\r\n\t\tset.  Is one already set? */\r\n\t\tif( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 )\r\n\t\t{\r\n\t\t\txWaitConditionMet = pdTRUE;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t}\r\n\t}\r\n\telse\r\n\t{\r\n\t\t/* Task has to wait for all the bits in uxBitsToWaitFor to be set.\r\n\t\tAre they set already? */\r\n\t\tif( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor )\r\n\t\t{\r\n\t\t\txWaitConditionMet = pdTRUE;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t}\r\n\t}\r\n\r\n\treturn xWaitConditionMet;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )\r\n\r\n\tBaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken )\r\n\t{\r\n\tBaseType_t xReturn;\r\n\r\n\t\ttraceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet );\r\n\t\txReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken );\r\n\r\n\t\treturn xReturn;\r\n\t}\r\n\r\n#endif\r\n/*-----------------------------------------------------------*/\r\n\r\n#if (configUSE_TRACE_FACILITY == 1)\r\n\r\n\tUBaseType_t uxEventGroupGetNumber( void* xEventGroup )\r\n\t{\r\n\tUBaseType_t xReturn;\r\n\tEventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;\r\n\r\n\t\tif( xEventGroup == NULL )\r\n\t\t{\r\n\t\t\txReturn = 0;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\txReturn = pxEventBits->uxEventGroupNumber;\r\n\t\t}\r\n\r\n\t\treturn xReturn;\r\n\t}\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RTOS/src/event_groups.h",
    "content": "/*\r\n    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r\n    All rights reserved\r\n\r\n    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r\n\r\n    This file is part of the FreeRTOS distribution.\r\n\r\n    FreeRTOS is free software; you can redistribute it and/or modify it under\r\n    the terms of the GNU General Public License (version 2) as published by the\r\n    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r\n\r\n    ***************************************************************************\r\n    >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r\n    >>!   distribute a combined work that includes FreeRTOS without being   !<<\r\n    >>!   obliged to provide the source code for proprietary components     !<<\r\n    >>!   outside of the FreeRTOS kernel.                                   !<<\r\n    ***************************************************************************\r\n\r\n    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r\n    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r\n    FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r\n    link: http://www.freertos.org/a00114.html\r\n\r\n    ***************************************************************************\r\n     *                                                                       *\r\n     *    FreeRTOS provides completely free yet professionally developed,    *\r\n     *    robust, strictly quality controlled, supported, and cross          *\r\n     *    platform software that is more than just the market leader, it     *\r\n     *    is the industry's de facto standard.                               *\r\n     *                                                                       *\r\n     *    Help yourself get started quickly while simultaneously helping     *\r\n     *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r\n     *    tutorial book, reference manual, or both:                          *\r\n     *    http://www.FreeRTOS.org/Documentation                              *\r\n     *                                                                       *\r\n    ***************************************************************************\r\n\r\n    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r\n    the FAQ page \"My application does not run, what could be wrong?\".  Have you\r\n    defined configASSERT()?\r\n\r\n    http://www.FreeRTOS.org/support - In return for receiving this top quality\r\n    embedded software for free we request you assist our global community by\r\n    participating in the support forum.\r\n\r\n    http://www.FreeRTOS.org/training - Investing in training allows your team to\r\n    be as productive as possible as early as possible.  Now you can receive\r\n    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r\n    Ltd, and the world's leading authority on the world's leading RTOS.\r\n\r\n    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r\n    including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r\n    compatible FAT file system, and our tiny thread aware UDP/IP stack.\r\n\r\n    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r\n    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r\n\r\n    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r\n    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r\n    licenses offer ticketed support, indemnification and commercial middleware.\r\n\r\n    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r\n    engineered and independently SIL3 certified version for use in safety and\r\n    mission critical applications that require provable dependability.\r\n\r\n    1 tab == 4 spaces!\r\n*/\r\n\r\n#ifndef EVENT_GROUPS_H\r\n#define EVENT_GROUPS_H\r\n\r\n#ifndef INC_FREERTOS_H\r\n\t#error \"include FreeRTOS.h\" must appear in source files before \"include event_groups.h\"\r\n#endif\r\n\r\n#include \"timers.h\"\r\n\r\n#ifdef __cplusplus\r\nextern \"C\" {\r\n#endif\r\n\r\n/**\r\n * An event group is a collection of bits to which an application can assign a\r\n * meaning.  For example, an application may create an event group to convey\r\n * the status of various CAN bus related events in which bit 0 might mean \"A CAN\r\n * message has been received and is ready for processing\", bit 1 might mean \"The\r\n * application has queued a message that is ready for sending onto the CAN\r\n * network\", and bit 2 might mean \"It is time to send a SYNC message onto the\r\n * CAN network\" etc.  A task can then test the bit values to see which events\r\n * are active, and optionally enter the Blocked state to wait for a specified\r\n * bit or a group of specified bits to be active.  To continue the CAN bus\r\n * example, a CAN controlling task can enter the Blocked state (and therefore\r\n * not consume any processing time) until either bit 0, bit 1 or bit 2 are\r\n * active, at which time the bit that was actually active would inform the task\r\n * which action it had to take (process a received message, send a message, or\r\n * send a SYNC).\r\n *\r\n * The event groups implementation contains intelligence to avoid race\r\n * conditions that would otherwise occur were an application to use a simple\r\n * variable for the same purpose.  This is particularly important with respect\r\n * to when a bit within an event group is to be cleared, and when bits have to\r\n * be set and then tested atomically - as is the case where event groups are\r\n * used to create a synchronisation point between multiple tasks (a\r\n * 'rendezvous').\r\n *\r\n * \\defgroup EventGroup\r\n */\r\n\r\n\r\n\r\n/**\r\n * event_groups.h\r\n *\r\n * Type by which event groups are referenced.  For example, a call to\r\n * xEventGroupCreate() returns an EventGroupHandle_t variable that can then\r\n * be used as a parameter to other event group functions.\r\n *\r\n * \\defgroup EventGroupHandle_t EventGroupHandle_t\r\n * \\ingroup EventGroup\r\n */\r\ntypedef void * EventGroupHandle_t;\r\n\r\n/* \r\n * The type that holds event bits always matches TickType_t - therefore the\r\n * number of bits it holds is set by configUSE_16_BIT_TICKS (16 bits if set to 1,\r\n * 32 bits if set to 0. \r\n *\r\n * \\defgroup EventBits_t EventBits_t\r\n * \\ingroup EventGroup\r\n */\r\ntypedef TickType_t EventBits_t;\r\n\r\n/**\r\n * event_groups.h\r\n *<pre>\r\n EventGroupHandle_t xEventGroupCreate( void );\r\n </pre>\r\n *\r\n * Create a new event group.  This function cannot be called from an interrupt.\r\n *\r\n * Although event groups are not related to ticks, for internal implementation\r\n * reasons the number of bits available for use in an event group is dependent\r\n * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h.  If\r\n * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit\r\n * 0 to bit 7).  If configUSE_16_BIT_TICKS is set to 0 then each event group has\r\n * 24 usable bits (bit 0 to bit 23).  The EventBits_t type is used to store\r\n * event bits within an event group.\r\n *\r\n * @return If the event group was created then a handle to the event group is\r\n * returned.  If there was insufficient FreeRTOS heap available to create the\r\n * event group then NULL is returned.  See http://www.freertos.org/a00111.html\r\n *\r\n * Example usage:\r\n   <pre>\r\n\t// Declare a variable to hold the created event group.\r\n\tEventGroupHandle_t xCreatedEventGroup;\r\n\r\n\t// Attempt to create the event group.\r\n\txCreatedEventGroup = xEventGroupCreate();\r\n\r\n\t// Was the event group created successfully?\r\n\tif( xCreatedEventGroup == NULL )\r\n\t{\r\n\t\t// The event group was not created because there was insufficient\r\n\t\t// FreeRTOS heap available.\r\n\t}\r\n\telse\r\n\t{\r\n\t\t// The event group was created.\r\n\t}\r\n   </pre>\r\n * \\defgroup xEventGroupCreate xEventGroupCreate\r\n * \\ingroup EventGroup\r\n */\r\nEventGroupHandle_t xEventGroupCreate( void ) PRIVILEGED_FUNCTION;\r\n\r\n/**\r\n * event_groups.h\r\n *<pre>\r\n\tEventBits_t xEventGroupWaitBits( \tEventGroupHandle_t xEventGroup,\r\n\t\t\t\t\t\t\t\t\t\tconst EventBits_t uxBitsToWaitFor,\r\n\t\t\t\t\t\t\t\t\t\tconst BaseType_t xClearOnExit,\r\n\t\t\t\t\t\t\t\t\t\tconst BaseType_t xWaitForAllBits,\r\n\t\t\t\t\t\t\t\t\t\tconst TickType_t xTicksToWait );\r\n </pre>\r\n *\r\n * [Potentially] block to wait for one or more bits to be set within a\r\n * previously created event group.\r\n *\r\n * This function cannot be called from an interrupt.\r\n *\r\n * @param xEventGroup The event group in which the bits are being tested.  The\r\n * event group must have previously been created using a call to\r\n * xEventGroupCreate().\r\n *\r\n * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test\r\n * inside the event group.  For example, to wait for bit 0 and/or bit 2 set\r\n * uxBitsToWaitFor to 0x05.  To wait for bits 0 and/or bit 1 and/or bit 2 set\r\n * uxBitsToWaitFor to 0x07.  Etc.\r\n *\r\n * @param xClearOnExit If xClearOnExit is set to pdTRUE then any bits within\r\n * uxBitsToWaitFor that are set within the event group will be cleared before\r\n * xEventGroupWaitBits() returns if the wait condition was met (if the function\r\n * returns for a reason other than a timeout).  If xClearOnExit is set to\r\n * pdFALSE then the bits set in the event group are not altered when the call to\r\n * xEventGroupWaitBits() returns.\r\n *\r\n * @param xWaitForAllBits If xWaitForAllBits is set to pdTRUE then\r\n * xEventGroupWaitBits() will return when either all the bits in uxBitsToWaitFor\r\n * are set or the specified block time expires.  If xWaitForAllBits is set to\r\n * pdFALSE then xEventGroupWaitBits() will return when any one of the bits set\r\n * in uxBitsToWaitFor is set or the specified block time expires.  The block\r\n * time is specified by the xTicksToWait parameter.\r\n *\r\n * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait\r\n * for one/all (depending on the xWaitForAllBits value) of the bits specified by\r\n * uxBitsToWaitFor to become set.\r\n *\r\n * @return The value of the event group at the time either the bits being waited\r\n * for became set, or the block time expired.  Test the return value to know\r\n * which bits were set.  If xEventGroupWaitBits() returned because its timeout\r\n * expired then not all the bits being waited for will be set.  If\r\n * xEventGroupWaitBits() returned because the bits it was waiting for were set\r\n * then the returned value is the event group value before any bits were\r\n * automatically cleared in the case that xClearOnExit parameter was set to\r\n * pdTRUE.\r\n *\r\n * Example usage:\r\n   <pre>\r\n   #define BIT_0\t( 1 << 0 )\r\n   #define BIT_4\t( 1 << 4 )\r\n\r\n   void aFunction( EventGroupHandle_t xEventGroup )\r\n   {\r\n   EventBits_t uxBits;\r\n   const TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;\r\n\r\n\t\t// Wait a maximum of 100ms for either bit 0 or bit 4 to be set within\r\n\t\t// the event group.  Clear the bits before exiting.\r\n\t\tuxBits = xEventGroupWaitBits(\r\n\t\t\t\t\txEventGroup,\t// The event group being tested.\r\n\t\t\t\t\tBIT_0 | BIT_4,\t// The bits within the event group to wait for.\r\n\t\t\t\t\tpdTRUE,\t\t\t// BIT_0 and BIT_4 should be cleared before returning.\r\n\t\t\t\t\tpdFALSE,\t\t// Don't wait for both bits, either bit will do.\r\n\t\t\t\t\txTicksToWait );\t// Wait a maximum of 100ms for either bit to be set.\r\n\r\n\t\tif( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )\r\n\t\t{\r\n\t\t\t// xEventGroupWaitBits() returned because both bits were set.\r\n\t\t}\r\n\t\telse if( ( uxBits & BIT_0 ) != 0 )\r\n\t\t{\r\n\t\t\t// xEventGroupWaitBits() returned because just BIT_0 was set.\r\n\t\t}\r\n\t\telse if( ( uxBits & BIT_4 ) != 0 )\r\n\t\t{\r\n\t\t\t// xEventGroupWaitBits() returned because just BIT_4 was set.\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\t// xEventGroupWaitBits() returned because xTicksToWait ticks passed\r\n\t\t\t// without either BIT_0 or BIT_4 becoming set.\r\n\t\t}\r\n   }\r\n   </pre>\r\n * \\defgroup xEventGroupWaitBits xEventGroupWaitBits\r\n * \\ingroup EventGroup\r\n */\r\nEventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\r\n\r\n/**\r\n * event_groups.h\r\n *<pre>\r\n\tEventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );\r\n </pre>\r\n *\r\n * Clear bits within an event group.  This function cannot be called from an\r\n * interrupt.\r\n *\r\n * @param xEventGroup The event group in which the bits are to be cleared.\r\n *\r\n * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear\r\n * in the event group.  For example, to clear bit 3 only, set uxBitsToClear to\r\n * 0x08.  To clear bit 3 and bit 0 set uxBitsToClear to 0x09.\r\n *\r\n * @return The value of the event group before the specified bits were cleared.\r\n *\r\n * Example usage:\r\n   <pre>\r\n   #define BIT_0\t( 1 << 0 )\r\n   #define BIT_4\t( 1 << 4 )\r\n\r\n   void aFunction( EventGroupHandle_t xEventGroup )\r\n   {\r\n   EventBits_t uxBits;\r\n\r\n\t\t// Clear bit 0 and bit 4 in xEventGroup.\r\n\t\tuxBits = xEventGroupClearBits(\r\n\t\t\t\t\t\t\t\txEventGroup,\t// The event group being updated.\r\n\t\t\t\t\t\t\t\tBIT_0 | BIT_4 );// The bits being cleared.\r\n\r\n\t\tif( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )\r\n\t\t{\r\n\t\t\t// Both bit 0 and bit 4 were set before xEventGroupClearBits() was\r\n\t\t\t// called.  Both will now be clear (not set).\r\n\t\t}\r\n\t\telse if( ( uxBits & BIT_0 ) != 0 )\r\n\t\t{\r\n\t\t\t// Bit 0 was set before xEventGroupClearBits() was called.  It will\r\n\t\t\t// now be clear.\r\n\t\t}\r\n\t\telse if( ( uxBits & BIT_4 ) != 0 )\r\n\t\t{\r\n\t\t\t// Bit 4 was set before xEventGroupClearBits() was called.  It will\r\n\t\t\t// now be clear.\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\t// Neither bit 0 nor bit 4 were set in the first place.\r\n\t\t}\r\n   }\r\n   </pre>\r\n * \\defgroup xEventGroupClearBits xEventGroupClearBits\r\n * \\ingroup EventGroup\r\n */\r\nEventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;\r\n\r\n/**\r\n * event_groups.h\r\n *<pre>\r\n\tBaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );\r\n </pre>\r\n *\r\n * A version of xEventGroupClearBits() that can be called from an interrupt.\r\n *\r\n * Setting bits in an event group is not a deterministic operation because there\r\n * are an unknown number of tasks that may be waiting for the bit or bits being\r\n * set.  FreeRTOS does not allow nondeterministic operations to be performed\r\n * while interrupts are disabled, so protects event groups that are accessed\r\n * from tasks by suspending the scheduler rather than disabling interrupts.  As\r\n * a result event groups cannot be accessed directly from an interrupt service\r\n * routine.  Therefore xEventGroupClearBitsFromISR() sends a message to the \r\n * timer task to have the clear operation performed in the context of the timer \r\n * task.\r\n *\r\n * @param xEventGroup The event group in which the bits are to be cleared.\r\n *\r\n * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear.\r\n * For example, to clear bit 3 only, set uxBitsToClear to 0x08.  To clear bit 3\r\n * and bit 0 set uxBitsToClear to 0x09.\r\n *\r\n * @return If the request to execute the function was posted successfully then \r\n * pdPASS is returned, otherwise pdFALSE is returned.  pdFALSE will be returned \r\n * if the timer service queue was full.\r\n *\r\n * Example usage:\r\n   <pre>\r\n   #define BIT_0\t( 1 << 0 )\r\n   #define BIT_4\t( 1 << 4 )\r\n\r\n   // An event group which it is assumed has already been created by a call to\r\n   // xEventGroupCreate().\r\n   EventGroupHandle_t xEventGroup;\r\n\r\n   void anInterruptHandler( void )\r\n   {\r\n\t\t// Clear bit 0 and bit 4 in xEventGroup.\r\n\t\txResult = xEventGroupClearBitsFromISR(\r\n\t\t\t\t\t\t\txEventGroup,\t // The event group being updated.\r\n\t\t\t\t\t\t\tBIT_0 | BIT_4 ); // The bits being set.\r\n\r\n\t\tif( xResult == pdPASS )\r\n\t\t{\r\n\t\t\t// The message was posted successfully.\r\n\t\t}\r\n  }\r\n   </pre>\r\n * \\defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR\r\n * \\ingroup EventGroup\r\n */\r\n#if( configUSE_TRACE_FACILITY == 1 )\r\n\tBaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );\r\n#else\r\n\t#define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL )\r\n#endif\r\n\r\n/**\r\n * event_groups.h\r\n *<pre>\r\n\tEventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );\r\n </pre>\r\n *\r\n * Set bits within an event group.\r\n * This function cannot be called from an interrupt.  xEventGroupSetBitsFromISR()\r\n * is a version that can be called from an interrupt.\r\n *\r\n * Setting bits in an event group will automatically unblock tasks that are\r\n * blocked waiting for the bits.\r\n *\r\n * @param xEventGroup The event group in which the bits are to be set.\r\n *\r\n * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.\r\n * For example, to set bit 3 only, set uxBitsToSet to 0x08.  To set bit 3\r\n * and bit 0 set uxBitsToSet to 0x09.\r\n *\r\n * @return The value of the event group at the time the call to\r\n * xEventGroupSetBits() returns.  There are two reasons why the returned value\r\n * might have the bits specified by the uxBitsToSet parameter cleared.  First,\r\n * if setting a bit results in a task that was waiting for the bit leaving the\r\n * blocked state then it is possible the bit will be cleared automatically\r\n * (see the xClearBitOnExit parameter of xEventGroupWaitBits()).  Second, any\r\n * unblocked (or otherwise Ready state) task that has a priority above that of\r\n * the task that called xEventGroupSetBits() will execute and may change the\r\n * event group value before the call to xEventGroupSetBits() returns.\r\n *\r\n * Example usage:\r\n   <pre>\r\n   #define BIT_0\t( 1 << 0 )\r\n   #define BIT_4\t( 1 << 4 )\r\n\r\n   void aFunction( EventGroupHandle_t xEventGroup )\r\n   {\r\n   EventBits_t uxBits;\r\n\r\n\t\t// Set bit 0 and bit 4 in xEventGroup.\r\n\t\tuxBits = xEventGroupSetBits(\r\n\t\t\t\t\t\t\txEventGroup,\t// The event group being updated.\r\n\t\t\t\t\t\t\tBIT_0 | BIT_4 );// The bits being set.\r\n\r\n\t\tif( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )\r\n\t\t{\r\n\t\t\t// Both bit 0 and bit 4 remained set when the function returned.\r\n\t\t}\r\n\t\telse if( ( uxBits & BIT_0 ) != 0 )\r\n\t\t{\r\n\t\t\t// Bit 0 remained set when the function returned, but bit 4 was\r\n\t\t\t// cleared.  It might be that bit 4 was cleared automatically as a\r\n\t\t\t// task that was waiting for bit 4 was removed from the Blocked\r\n\t\t\t// state.\r\n\t\t}\r\n\t\telse if( ( uxBits & BIT_4 ) != 0 )\r\n\t\t{\r\n\t\t\t// Bit 4 remained set when the function returned, but bit 0 was\r\n\t\t\t// cleared.  It might be that bit 0 was cleared automatically as a\r\n\t\t\t// task that was waiting for bit 0 was removed from the Blocked\r\n\t\t\t// state.\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\t// Neither bit 0 nor bit 4 remained set.  It might be that a task\r\n\t\t\t// was waiting for both of the bits to be set, and the bits were\r\n\t\t\t// cleared as the task left the Blocked state.\r\n\t\t}\r\n   }\r\n   </pre>\r\n * \\defgroup xEventGroupSetBits xEventGroupSetBits\r\n * \\ingroup EventGroup\r\n */\r\nEventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION;\r\n\r\n/**\r\n * event_groups.h\r\n *<pre>\r\n\tBaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken );\r\n </pre>\r\n *\r\n * A version of xEventGroupSetBits() that can be called from an interrupt.\r\n *\r\n * Setting bits in an event group is not a deterministic operation because there\r\n * are an unknown number of tasks that may be waiting for the bit or bits being\r\n * set.  FreeRTOS does not allow nondeterministic operations to be performed in\r\n * interrupts or from critical sections.  Therefore xEventGroupSetBitFromISR()\r\n * sends a message to the timer task to have the set operation performed in the\r\n * context of the timer task - where a scheduler lock is used in place of a\r\n * critical section.\r\n *\r\n * @param xEventGroup The event group in which the bits are to be set.\r\n *\r\n * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.\r\n * For example, to set bit 3 only, set uxBitsToSet to 0x08.  To set bit 3\r\n * and bit 0 set uxBitsToSet to 0x09.\r\n *\r\n * @param pxHigherPriorityTaskWoken As mentioned above, calling this function\r\n * will result in a message being sent to the timer daemon task.  If the\r\n * priority of the timer daemon task is higher than the priority of the\r\n * currently running task (the task the interrupt interrupted) then\r\n * *pxHigherPriorityTaskWoken will be set to pdTRUE by\r\n * xEventGroupSetBitsFromISR(), indicating that a context switch should be\r\n * requested before the interrupt exits.  For that reason\r\n * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the\r\n * example code below.\r\n *\r\n * @return If the request to execute the function was posted successfully then \r\n * pdPASS is returned, otherwise pdFALSE is returned.  pdFALSE will be returned \r\n * if the timer service queue was full.\r\n *\r\n * Example usage:\r\n   <pre>\r\n   #define BIT_0\t( 1 << 0 )\r\n   #define BIT_4\t( 1 << 4 )\r\n\r\n   // An event group which it is assumed has already been created by a call to\r\n   // xEventGroupCreate().\r\n   EventGroupHandle_t xEventGroup;\r\n\r\n   void anInterruptHandler( void )\r\n   {\r\n   BaseType_t xHigherPriorityTaskWoken, xResult;\r\n\r\n\t\t// xHigherPriorityTaskWoken must be initialised to pdFALSE.\r\n\t\txHigherPriorityTaskWoken = pdFALSE;\r\n\r\n\t\t// Set bit 0 and bit 4 in xEventGroup.\r\n\t\txResult = xEventGroupSetBitsFromISR(\r\n\t\t\t\t\t\t\txEventGroup,\t// The event group being updated.\r\n\t\t\t\t\t\t\tBIT_0 | BIT_4   // The bits being set.\r\n\t\t\t\t\t\t\t&xHigherPriorityTaskWoken );\r\n\r\n\t\t// Was the message posted successfully?\r\n\t\tif( xResult == pdPASS )\r\n\t\t{\r\n\t\t\t// If xHigherPriorityTaskWoken is now set to pdTRUE then a context\r\n\t\t\t// switch should be requested.  The macro used is port specific and \r\n\t\t\t// will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - \r\n\t\t\t// refer to the documentation page for the port being used.\r\n\t\t\tportYIELD_FROM_ISR( xHigherPriorityTaskWoken );\r\n\t\t}\r\n  }\r\n   </pre>\r\n * \\defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR\r\n * \\ingroup EventGroup\r\n */\r\n#if( configUSE_TRACE_FACILITY == 1 )\r\n\tBaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken );\r\n#else\r\n\t#define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken )\r\n#endif\r\n\r\n/**\r\n * event_groups.h\r\n *<pre>\r\n\tEventBits_t xEventGroupSync(\tEventGroupHandle_t xEventGroup,\r\n\t\t\t\t\t\t\t\t\tconst EventBits_t uxBitsToSet,\r\n\t\t\t\t\t\t\t\t\tconst EventBits_t uxBitsToWaitFor,\r\n\t\t\t\t\t\t\t\t\tTickType_t xTicksToWait );\r\n </pre>\r\n *\r\n * Atomically set bits within an event group, then wait for a combination of\r\n * bits to be set within the same event group.  This functionality is typically\r\n * used to synchronise multiple tasks, where each task has to wait for the other\r\n * tasks to reach a synchronisation point before proceeding.\r\n *\r\n * This function cannot be used from an interrupt.\r\n *\r\n * The function will return before its block time expires if the bits specified\r\n * by the uxBitsToWait parameter are set, or become set within that time.  In\r\n * this case all the bits specified by uxBitsToWait will be automatically\r\n * cleared before the function returns.\r\n *\r\n * @param xEventGroup The event group in which the bits are being tested.  The\r\n * event group must have previously been created using a call to\r\n * xEventGroupCreate().\r\n *\r\n * @param uxBitsToSet The bits to set in the event group before determining\r\n * if, and possibly waiting for, all the bits specified by the uxBitsToWait\r\n * parameter are set.\r\n *\r\n * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test\r\n * inside the event group.  For example, to wait for bit 0 and bit 2 set\r\n * uxBitsToWaitFor to 0x05.  To wait for bits 0 and bit 1 and bit 2 set\r\n * uxBitsToWaitFor to 0x07.  Etc.\r\n *\r\n * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait\r\n * for all of the bits specified by uxBitsToWaitFor to become set.\r\n *\r\n * @return The value of the event group at the time either the bits being waited\r\n * for became set, or the block time expired.  Test the return value to know\r\n * which bits were set.  If xEventGroupSync() returned because its timeout\r\n * expired then not all the bits being waited for will be set.  If\r\n * xEventGroupSync() returned because all the bits it was waiting for were\r\n * set then the returned value is the event group value before any bits were\r\n * automatically cleared.\r\n *\r\n * Example usage:\r\n <pre>\r\n // Bits used by the three tasks.\r\n #define TASK_0_BIT\t\t( 1 << 0 )\r\n #define TASK_1_BIT\t\t( 1 << 1 )\r\n #define TASK_2_BIT\t\t( 1 << 2 )\r\n\r\n #define ALL_SYNC_BITS ( TASK_0_BIT | TASK_1_BIT | TASK_2_BIT )\r\n\r\n // Use an event group to synchronise three tasks.  It is assumed this event\r\n // group has already been created elsewhere.\r\n EventGroupHandle_t xEventBits;\r\n\r\n void vTask0( void *pvParameters )\r\n {\r\n EventBits_t uxReturn;\r\n TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;\r\n\r\n\t for( ;; )\r\n\t {\r\n\t\t// Perform task functionality here.\r\n\r\n\t\t// Set bit 0 in the event flag to note this task has reached the\r\n\t\t// sync point.  The other two tasks will set the other two bits defined\r\n\t\t// by ALL_SYNC_BITS.  All three tasks have reached the synchronisation\r\n\t\t// point when all the ALL_SYNC_BITS are set.  Wait a maximum of 100ms\r\n\t\t// for this to happen.\r\n\t\tuxReturn = xEventGroupSync( xEventBits, TASK_0_BIT, ALL_SYNC_BITS, xTicksToWait );\r\n\r\n\t\tif( ( uxReturn & ALL_SYNC_BITS ) == ALL_SYNC_BITS )\r\n\t\t{\r\n\t\t\t// All three tasks reached the synchronisation point before the call\r\n\t\t\t// to xEventGroupSync() timed out.\r\n\t\t}\r\n\t}\r\n }\r\n\r\n void vTask1( void *pvParameters )\r\n {\r\n\t for( ;; )\r\n\t {\r\n\t\t// Perform task functionality here.\r\n\r\n\t\t// Set bit 1 in the event flag to note this task has reached the\r\n\t\t// synchronisation point.  The other two tasks will set the other two\r\n\t\t// bits defined by ALL_SYNC_BITS.  All three tasks have reached the\r\n\t\t// synchronisation point when all the ALL_SYNC_BITS are set.  Wait\r\n\t\t// indefinitely for this to happen.\r\n\t\txEventGroupSync( xEventBits, TASK_1_BIT, ALL_SYNC_BITS, portMAX_DELAY );\r\n\r\n\t\t// xEventGroupSync() was called with an indefinite block time, so\r\n\t\t// this task will only reach here if the syncrhonisation was made by all\r\n\t\t// three tasks, so there is no need to test the return value.\r\n\t }\r\n }\r\n\r\n void vTask2( void *pvParameters )\r\n {\r\n\t for( ;; )\r\n\t {\r\n\t\t// Perform task functionality here.\r\n\r\n\t\t// Set bit 2 in the event flag to note this task has reached the\r\n\t\t// synchronisation point.  The other two tasks will set the other two\r\n\t\t// bits defined by ALL_SYNC_BITS.  All three tasks have reached the\r\n\t\t// synchronisation point when all the ALL_SYNC_BITS are set.  Wait\r\n\t\t// indefinitely for this to happen.\r\n\t\txEventGroupSync( xEventBits, TASK_2_BIT, ALL_SYNC_BITS, portMAX_DELAY );\r\n\r\n\t\t// xEventGroupSync() was called with an indefinite block time, so\r\n\t\t// this task will only reach here if the syncrhonisation was made by all\r\n\t\t// three tasks, so there is no need to test the return value.\r\n\t}\r\n }\r\n\r\n </pre>\r\n * \\defgroup xEventGroupSync xEventGroupSync\r\n * \\ingroup EventGroup\r\n */\r\nEventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\r\n\r\n\r\n/**\r\n * event_groups.h\r\n *<pre>\r\n\tEventBits_t xEventGroupGetBits( EventGroupHandle_t xEventGroup );\r\n </pre>\r\n *\r\n * Returns the current value of the bits in an event group.  This function\r\n * cannot be used from an interrupt.\r\n *\r\n * @param xEventGroup The event group being queried.\r\n *\r\n * @return The event group bits at the time xEventGroupGetBits() was called.\r\n *\r\n * \\defgroup xEventGroupGetBits xEventGroupGetBits\r\n * \\ingroup EventGroup\r\n */\r\n#define xEventGroupGetBits( xEventGroup ) xEventGroupClearBits( xEventGroup, 0 )\r\n\r\n/**\r\n * event_groups.h\r\n *<pre>\r\n\tEventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup );\r\n </pre>\r\n *\r\n * A version of xEventGroupGetBits() that can be called from an ISR.\r\n *\r\n * @param xEventGroup The event group being queried.\r\n *\r\n * @return The event group bits at the time xEventGroupGetBitsFromISR() was called.\r\n *\r\n * \\defgroup xEventGroupGetBitsFromISR xEventGroupGetBitsFromISR\r\n * \\ingroup EventGroup\r\n */\r\nEventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup );\r\n\r\n/**\r\n * event_groups.h\r\n *<pre>\r\n\tvoid xEventGroupDelete( EventGroupHandle_t xEventGroup );\r\n </pre>\r\n *\r\n * Delete an event group that was previously created by a call to\r\n * xEventGroupCreate().  Tasks that are blocked on the event group will be\r\n * unblocked and obtain 0 as the event group's value.\r\n *\r\n * @param xEventGroup The event group being deleted.\r\n */\r\nvoid vEventGroupDelete( EventGroupHandle_t xEventGroup );\r\n\r\n/* For internal use only. */\r\nvoid vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet );\r\nvoid vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear );\r\n\r\n#if (configUSE_TRACE_FACILITY == 1)\r\n\tUBaseType_t uxEventGroupGetNumber( void* xEventGroup );\r\n#endif\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* EVENT_GROUPS_H */\r\n\r\n\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RTOS/src/heap_3.c",
    "content": "/*\r\n    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r\n    All rights reserved\r\n\r\n    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r\n\r\n    This file is part of the FreeRTOS distribution.\r\n\r\n    FreeRTOS is free software; you can redistribute it and/or modify it under\r\n    the terms of the GNU General Public License (version 2) as published by the\r\n    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r\n\r\n    ***************************************************************************\r\n    >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r\n    >>!   distribute a combined work that includes FreeRTOS without being   !<<\r\n    >>!   obliged to provide the source code for proprietary components     !<<\r\n    >>!   outside of the FreeRTOS kernel.                                   !<<\r\n    ***************************************************************************\r\n\r\n    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r\n    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r\n    FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r\n    link: http://www.freertos.org/a00114.html\r\n\r\n    ***************************************************************************\r\n     *                                                                       *\r\n     *    FreeRTOS provides completely free yet professionally developed,    *\r\n     *    robust, strictly quality controlled, supported, and cross          *\r\n     *    platform software that is more than just the market leader, it     *\r\n     *    is the industry's de facto standard.                               *\r\n     *                                                                       *\r\n     *    Help yourself get started quickly while simultaneously helping     *\r\n     *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r\n     *    tutorial book, reference manual, or both:                          *\r\n     *    http://www.FreeRTOS.org/Documentation                              *\r\n     *                                                                       *\r\n    ***************************************************************************\r\n\r\n    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r\n    the FAQ page \"My application does not run, what could be wrong?\".  Have you\r\n    defined configASSERT()?\r\n\r\n    http://www.FreeRTOS.org/support - In return for receiving this top quality\r\n    embedded software for free we request you assist our global community by\r\n    participating in the support forum.\r\n\r\n    http://www.FreeRTOS.org/training - Investing in training allows your team to\r\n    be as productive as possible as early as possible.  Now you can receive\r\n    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r\n    Ltd, and the world's leading authority on the world's leading RTOS.\r\n\r\n    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r\n    including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r\n    compatible FAT file system, and our tiny thread aware UDP/IP stack.\r\n\r\n    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r\n    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r\n\r\n    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r\n    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r\n    licenses offer ticketed support, indemnification and commercial middleware.\r\n\r\n    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r\n    engineered and independently SIL3 certified version for use in safety and\r\n    mission critical applications that require provable dependability.\r\n\r\n    1 tab == 4 spaces!\r\n*/\r\n\r\n\r\n/*\r\n * Implementation of pvPortMalloc() and vPortFree() that relies on the\r\n * compilers own malloc() and free() implementations.\r\n *\r\n * This file can only be used if the linker is configured to to generate\r\n * a heap memory area.\r\n *\r\n * See heap_1.c, heap_2.c and heap_4.c for alternative implementations, and the\r\n * memory management pages of http://www.FreeRTOS.org for more information.\r\n */\r\n\r\n#include <stdlib.h>\r\n\r\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r\nall the API functions to use the MPU wrappers.  That should only be done when\r\ntask.h is included from an application file. */\r\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r\n\r\n#include \"FreeRTOS.h\"\r\n#include \"task.h\"\r\n\r\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r\n\r\n/*-----------------------------------------------------------*/\r\n\r\nvoid *pvPortMalloc( size_t xWantedSize )\r\n{\r\nvoid *pvReturn;\r\n\r\n\tvTaskSuspendAll();\r\n\t{\r\n\t\tpvReturn = malloc( xWantedSize );\r\n\t\ttraceMALLOC( pvReturn, xWantedSize );\r\n\t}\r\n\t( void ) xTaskResumeAll();\r\n\r\n\t#if( configUSE_MALLOC_FAILED_HOOK == 1 )\r\n\t{\r\n\t\tif( pvReturn == NULL )\r\n\t\t{\r\n\t\t\textern void vApplicationMallocFailedHook( void );\r\n\t\t\tvApplicationMallocFailedHook();\r\n\t\t}\r\n\t}\r\n\t#endif\r\n\r\n\treturn pvReturn;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nvoid vPortFree( void *pv )\r\n{\r\n\tif( pv )\r\n\t{\r\n\t\tvTaskSuspendAll();\r\n\t\t{\r\n\t\t\tfree( pv );\r\n\t\t\ttraceFREE( pv, 0 );\r\n\t\t}\r\n\t\t( void ) xTaskResumeAll();\r\n\t}\r\n}\r\n\r\n\r\n\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RTOS/src/list.c",
    "content": "/*\r\n    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r\n    All rights reserved\r\n\r\n    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r\n\r\n    This file is part of the FreeRTOS distribution.\r\n\r\n    FreeRTOS is free software; you can redistribute it and/or modify it under\r\n    the terms of the GNU General Public License (version 2) as published by the\r\n    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r\n\r\n    ***************************************************************************\r\n    >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r\n    >>!   distribute a combined work that includes FreeRTOS without being   !<<\r\n    >>!   obliged to provide the source code for proprietary components     !<<\r\n    >>!   outside of the FreeRTOS kernel.                                   !<<\r\n    ***************************************************************************\r\n\r\n    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r\n    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r\n    FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r\n    link: http://www.freertos.org/a00114.html\r\n\r\n    ***************************************************************************\r\n     *                                                                       *\r\n     *    FreeRTOS provides completely free yet professionally developed,    *\r\n     *    robust, strictly quality controlled, supported, and cross          *\r\n     *    platform software that is more than just the market leader, it     *\r\n     *    is the industry's de facto standard.                               *\r\n     *                                                                       *\r\n     *    Help yourself get started quickly while simultaneously helping     *\r\n     *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r\n     *    tutorial book, reference manual, or both:                          *\r\n     *    http://www.FreeRTOS.org/Documentation                              *\r\n     *                                                                       *\r\n    ***************************************************************************\r\n\r\n    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r\n    the FAQ page \"My application does not run, what could be wrong?\".  Have you\r\n    defined configASSERT()?\r\n\r\n    http://www.FreeRTOS.org/support - In return for receiving this top quality\r\n    embedded software for free we request you assist our global community by\r\n    participating in the support forum.\r\n\r\n    http://www.FreeRTOS.org/training - Investing in training allows your team to\r\n    be as productive as possible as early as possible.  Now you can receive\r\n    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r\n    Ltd, and the world's leading authority on the world's leading RTOS.\r\n\r\n    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r\n    including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r\n    compatible FAT file system, and our tiny thread aware UDP/IP stack.\r\n\r\n    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r\n    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r\n\r\n    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r\n    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r\n    licenses offer ticketed support, indemnification and commercial middleware.\r\n\r\n    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r\n    engineered and independently SIL3 certified version for use in safety and\r\n    mission critical applications that require provable dependability.\r\n\r\n    1 tab == 4 spaces!\r\n*/\r\n\r\n\r\n#include <stdlib.h>\r\n#include \"FreeRTOS.h\"\r\n#include \"list.h\"\r\n\r\n/*-----------------------------------------------------------\r\n * PUBLIC LIST API documented in list.h\r\n *----------------------------------------------------------*/\r\n\r\nvoid vListInitialise( List_t * const pxList )\r\n{\r\n\t/* The list structure contains a list item which is used to mark the\r\n\tend of the list.  To initialise the list the list end is inserted\r\n\tas the only list entry. */\r\n\tpxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );\t\t\t/*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */\r\n\r\n\t/* The list end value is the highest possible value in the list to\r\n\tensure it remains at the end of the list. */\r\n\tpxList->xListEnd.xItemValue = portMAX_DELAY;\r\n\r\n\t/* The list end next and previous pointers point to itself so we know\r\n\twhen the list is empty. */\r\n\tpxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );\t/*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */\r\n\tpxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */\r\n\r\n\tpxList->uxNumberOfItems = ( UBaseType_t ) 0U;\r\n\r\n\t/* Write known values into the list if\r\n\tconfigUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */\r\n\tlistSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );\r\n\tlistSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nvoid vListInitialiseItem( ListItem_t * const pxItem )\r\n{\r\n\t/* Make sure the list item is not recorded as being on a list. */\r\n\tpxItem->pvContainer = NULL;\r\n\r\n\t/* Write known values into the list item if\r\n\tconfigUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */\r\n\tlistSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );\r\n\tlistSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nvoid vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )\r\n{\r\nListItem_t * const pxIndex = pxList->pxIndex;\r\n\r\n\t/* Only effective when configASSERT() is also defined, these tests may catch\r\n\tthe list data structures being overwritten in memory.  They will not catch\r\n\tdata errors caused by incorrect configuration or use of FreeRTOS. */\r\n\tlistTEST_LIST_INTEGRITY( pxList );\r\n\tlistTEST_LIST_ITEM_INTEGRITY( pxNewListItem );\r\n\r\n\t/* Insert a new list item into pxList, but rather than sort the list,\r\n\tmakes the new list item the last item to be removed by a call to\r\n\tlistGET_OWNER_OF_NEXT_ENTRY(). */\r\n\tpxNewListItem->pxNext = pxIndex;\r\n\tpxNewListItem->pxPrevious = pxIndex->pxPrevious;\r\n\r\n\t/* Only used during decision coverage testing. */\r\n\tmtCOVERAGE_TEST_DELAY();\r\n\r\n\tpxIndex->pxPrevious->pxNext = pxNewListItem;\r\n\tpxIndex->pxPrevious = pxNewListItem;\r\n\r\n\t/* Remember which list the item is in. */\r\n\tpxNewListItem->pvContainer = ( void * ) pxList;\r\n\r\n\t( pxList->uxNumberOfItems )++;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nvoid vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )\r\n{\r\nListItem_t *pxIterator;\r\nconst TickType_t xValueOfInsertion = pxNewListItem->xItemValue;\r\n\r\n\t/* Only effective when configASSERT() is also defined, these tests may catch\r\n\tthe list data structures being overwritten in memory.  They will not catch\r\n\tdata errors caused by incorrect configuration or use of FreeRTOS. */\r\n\tlistTEST_LIST_INTEGRITY( pxList );\r\n\tlistTEST_LIST_ITEM_INTEGRITY( pxNewListItem );\r\n\r\n\t/* Insert the new list item into the list, sorted in xItemValue order.\r\n\r\n\tIf the list already contains a list item with the same item value then the\r\n\tnew list item should be placed after it.  This ensures that TCB's which are\r\n\tstored in ready lists (all of which have the same xItemValue value) get a\r\n\tshare of the CPU.  However, if the xItemValue is the same as the back marker\r\n\tthe iteration loop below will not end.  Therefore the value is checked\r\n\tfirst, and the algorithm slightly modified if necessary. */\r\n\tif( xValueOfInsertion == portMAX_DELAY )\r\n\t{\r\n\t\tpxIterator = pxList->xListEnd.pxPrevious;\r\n\t}\r\n\telse\r\n\t{\r\n\t\t/* *** NOTE ***********************************************************\r\n\t\tIf you find your application is crashing here then likely causes are\r\n\t\tlisted below.  In addition see http://www.freertos.org/FAQHelp.html for\r\n\t\tmore tips, and ensure configASSERT() is defined!\r\n\t\thttp://www.freertos.org/a00110.html#configASSERT\r\n\r\n\t\t\t1) Stack overflow -\r\n\t\t\t   see http://www.freertos.org/Stacks-and-stack-overflow-checking.html\r\n\t\t\t2) Incorrect interrupt priority assignment, especially on Cortex-M\r\n\t\t\t   parts where numerically high priority values denote low actual\r\n\t\t\t   interrupt priorities, which can seem counter intuitive.  See\r\n\t\t\t   http://www.freertos.org/RTOS-Cortex-M3-M4.html and the definition\r\n\t\t\t   of configMAX_SYSCALL_INTERRUPT_PRIORITY on\r\n\t\t\t   http://www.freertos.org/a00110.html\r\n\t\t\t3) Calling an API function from within a critical section or when\r\n\t\t\t   the scheduler is suspended, or calling an API function that does\r\n\t\t\t   not end in \"FromISR\" from an interrupt.\r\n\t\t\t4) Using a queue or semaphore before it has been initialised or\r\n\t\t\t   before the scheduler has been started (are interrupts firing\r\n\t\t\t   before vTaskStartScheduler() has been called?).\r\n\t\t**********************************************************************/\r\n\r\n\t\tfor( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */\r\n\t\t{\r\n\t\t\t/* There is nothing to do here, just iterating to the wanted\r\n\t\t\tinsertion position. */\r\n\t\t}\r\n\t}\r\n\r\n\tpxNewListItem->pxNext = pxIterator->pxNext;\r\n\tpxNewListItem->pxNext->pxPrevious = pxNewListItem;\r\n\tpxNewListItem->pxPrevious = pxIterator;\r\n\tpxIterator->pxNext = pxNewListItem;\r\n\r\n\t/* Remember which list the item is in.  This allows fast removal of the\r\n\titem later. */\r\n\tpxNewListItem->pvContainer = ( void * ) pxList;\r\n\r\n\t( pxList->uxNumberOfItems )++;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nUBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )\r\n{\r\n/* The list item knows which list it is in.  Obtain the list from the list\r\nitem. */\r\nList_t * const pxList = ( List_t * ) pxItemToRemove->pvContainer;\r\n\r\n\tpxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;\r\n\tpxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;\r\n\r\n\t/* Only used during decision coverage testing. */\r\n\tmtCOVERAGE_TEST_DELAY();\r\n\r\n\t/* Make sure the index is left pointing to a valid item. */\r\n\tif( pxList->pxIndex == pxItemToRemove )\r\n\t{\r\n\t\tpxList->pxIndex = pxItemToRemove->pxPrevious;\r\n\t}\r\n\telse\r\n\t{\r\n\t\tmtCOVERAGE_TEST_MARKER();\r\n\t}\r\n\r\n\tpxItemToRemove->pvContainer = NULL;\r\n\t( pxList->uxNumberOfItems )--;\r\n\r\n\treturn pxList->uxNumberOfItems;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RTOS/src/list.h",
    "content": "/*\r\n    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r\n    All rights reserved\r\n\r\n    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r\n\r\n    This file is part of the FreeRTOS distribution.\r\n\r\n    FreeRTOS is free software; you can redistribute it and/or modify it under\r\n    the terms of the GNU General Public License (version 2) as published by the\r\n    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r\n\r\n    ***************************************************************************\r\n    >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r\n    >>!   distribute a combined work that includes FreeRTOS without being   !<<\r\n    >>!   obliged to provide the source code for proprietary components     !<<\r\n    >>!   outside of the FreeRTOS kernel.                                   !<<\r\n    ***************************************************************************\r\n\r\n    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r\n    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r\n    FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r\n    link: http://www.freertos.org/a00114.html\r\n\r\n    ***************************************************************************\r\n     *                                                                       *\r\n     *    FreeRTOS provides completely free yet professionally developed,    *\r\n     *    robust, strictly quality controlled, supported, and cross          *\r\n     *    platform software that is more than just the market leader, it     *\r\n     *    is the industry's de facto standard.                               *\r\n     *                                                                       *\r\n     *    Help yourself get started quickly while simultaneously helping     *\r\n     *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r\n     *    tutorial book, reference manual, or both:                          *\r\n     *    http://www.FreeRTOS.org/Documentation                              *\r\n     *                                                                       *\r\n    ***************************************************************************\r\n\r\n    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r\n    the FAQ page \"My application does not run, what could be wrong?\".  Have you\r\n    defined configASSERT()?\r\n\r\n    http://www.FreeRTOS.org/support - In return for receiving this top quality\r\n    embedded software for free we request you assist our global community by\r\n    participating in the support forum.\r\n\r\n    http://www.FreeRTOS.org/training - Investing in training allows your team to\r\n    be as productive as possible as early as possible.  Now you can receive\r\n    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r\n    Ltd, and the world's leading authority on the world's leading RTOS.\r\n\r\n    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r\n    including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r\n    compatible FAT file system, and our tiny thread aware UDP/IP stack.\r\n\r\n    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r\n    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r\n\r\n    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r\n    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r\n    licenses offer ticketed support, indemnification and commercial middleware.\r\n\r\n    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r\n    engineered and independently SIL3 certified version for use in safety and\r\n    mission critical applications that require provable dependability.\r\n\r\n    1 tab == 4 spaces!\r\n*/\r\n\r\n/*\r\n * This is the list implementation used by the scheduler.  While it is tailored\r\n * heavily for the schedulers needs, it is also available for use by\r\n * application code.\r\n *\r\n * list_ts can only store pointers to list_item_ts.  Each ListItem_t contains a\r\n * numeric value (xItemValue).  Most of the time the lists are sorted in\r\n * descending item value order.\r\n *\r\n * Lists are created already containing one list item.  The value of this\r\n * item is the maximum possible that can be stored, it is therefore always at\r\n * the end of the list and acts as a marker.  The list member pxHead always\r\n * points to this marker - even though it is at the tail of the list.  This\r\n * is because the tail contains a wrap back pointer to the true head of\r\n * the list.\r\n *\r\n * In addition to it's value, each list item contains a pointer to the next\r\n * item in the list (pxNext), a pointer to the list it is in (pxContainer)\r\n * and a pointer to back to the object that contains it.  These later two\r\n * pointers are included for efficiency of list manipulation.  There is\r\n * effectively a two way link between the object containing the list item and\r\n * the list item itself.\r\n *\r\n *\r\n * \\page ListIntroduction List Implementation\r\n * \\ingroup FreeRTOSIntro\r\n */\r\n\r\n#ifndef INC_FREERTOS_H\r\n\t#error FreeRTOS.h must be included before list.h\r\n#endif\r\n\r\n#ifndef LIST_H\r\n#define LIST_H\r\n\r\n/*\r\n * The list structure members are modified from within interrupts, and therefore\r\n * by rights should be declared volatile.  However, they are only modified in a\r\n * functionally atomic way (within critical sections of with the scheduler\r\n * suspended) and are either passed by reference into a function or indexed via\r\n * a volatile variable.  Therefore, in all use cases tested so far, the volatile\r\n * qualifier can be omitted in order to provide a moderate performance\r\n * improvement without adversely affecting functional behaviour.  The assembly\r\n * instructions generated by the IAR, ARM and GCC compilers when the respective\r\n * compiler's options were set for maximum optimisation has been inspected and\r\n * deemed to be as intended.  That said, as compiler technology advances, and\r\n * especially if aggressive cross module optimisation is used (a use case that\r\n * has not been exercised to any great extend) then it is feasible that the\r\n * volatile qualifier will be needed for correct optimisation.  It is expected\r\n * that a compiler removing essential code because, without the volatile\r\n * qualifier on the list structure members and with aggressive cross module\r\n * optimisation, the compiler deemed the code unnecessary will result in\r\n * complete and obvious failure of the scheduler.  If this is ever experienced\r\n * then the volatile qualifier can be inserted in the relevant places within the\r\n * list structures by simply defining configLIST_VOLATILE to volatile in\r\n * FreeRTOSConfig.h (as per the example at the bottom of this comment block).\r\n * If configLIST_VOLATILE is not defined then the preprocessor directives below\r\n * will simply #define configLIST_VOLATILE away completely.\r\n *\r\n * To use volatile list structure members then add the following line to\r\n * FreeRTOSConfig.h (without the quotes):\r\n * \"#define configLIST_VOLATILE volatile\"\r\n */\r\n#ifndef configLIST_VOLATILE\r\n\t#define configLIST_VOLATILE\r\n#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */\r\n\r\n#ifdef __cplusplus\r\nextern \"C\" {\r\n#endif\r\n\r\n/* Macros that can be used to place known values within the list structures,\r\nthen check that the known values do not get corrupted during the execution of\r\nthe application.   These may catch the list data structures being overwritten in\r\nmemory.  They will not catch data errors caused by incorrect configuration or\r\nuse of FreeRTOS.*/\r\n#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 )\r\n\t/* Define the macros to do nothing. */\r\n\t#define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE\r\n\t#define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE\r\n\t#define listFIRST_LIST_INTEGRITY_CHECK_VALUE\r\n\t#define listSECOND_LIST_INTEGRITY_CHECK_VALUE\r\n\t#define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )\r\n\t#define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )\r\n\t#define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList )\r\n\t#define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList )\r\n\t#define listTEST_LIST_ITEM_INTEGRITY( pxItem )\r\n\t#define listTEST_LIST_INTEGRITY( pxList )\r\n#else\r\n\t/* Define macros that add new members into the list structures. */\r\n\t#define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE\t\t\t\tTickType_t xListItemIntegrityValue1;\r\n\t#define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE\t\t\t\tTickType_t xListItemIntegrityValue2;\r\n\t#define listFIRST_LIST_INTEGRITY_CHECK_VALUE\t\t\t\t\tTickType_t xListIntegrityValue1;\r\n\t#define listSECOND_LIST_INTEGRITY_CHECK_VALUE\t\t\t\t\tTickType_t xListIntegrityValue2;\r\n\r\n\t/* Define macros that set the new structure members to known values. */\r\n\t#define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )\t\t( pxItem )->xListItemIntegrityValue1 = pdINTEGRITY_CHECK_VALUE\r\n\t#define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )\t( pxItem )->xListItemIntegrityValue2 = pdINTEGRITY_CHECK_VALUE\r\n\t#define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList )\t\t( pxList )->xListIntegrityValue1 = pdINTEGRITY_CHECK_VALUE\r\n\t#define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList )\t\t( pxList )->xListIntegrityValue2 = pdINTEGRITY_CHECK_VALUE\r\n\r\n\t/* Define macros that will assert if one of the structure members does not\r\n\tcontain its expected value. */\r\n\t#define listTEST_LIST_ITEM_INTEGRITY( pxItem )\t\tconfigASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxItem )->xListItemIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )\r\n\t#define listTEST_LIST_INTEGRITY( pxList )\t\t\tconfigASSERT( ( ( pxList )->xListIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxList )->xListIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )\r\n#endif /* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES */\r\n\r\n\r\n/*\r\n * Definition of the only type of object that a list can contain.\r\n */\r\nstruct xLIST_ITEM\r\n{\r\n\tlistFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE\t\t\t\t/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */\r\n\tconfigLIST_VOLATILE TickType_t xItemValue;\t\t\t/*< The value being listed.  In most cases this is used to sort the list in descending order. */\r\n\tstruct xLIST_ITEM * configLIST_VOLATILE pxNext;\t\t/*< Pointer to the next ListItem_t in the list. */\r\n\tstruct xLIST_ITEM * configLIST_VOLATILE pxPrevious;\t/*< Pointer to the previous ListItem_t in the list. */\r\n\tvoid * pvOwner;\t\t\t\t\t\t\t\t\t\t/*< Pointer to the object (normally a TCB) that contains the list item.  There is therefore a two way link between the object containing the list item and the list item itself. */\r\n\tvoid * configLIST_VOLATILE pvContainer;\t\t\t\t/*< Pointer to the list in which this list item is placed (if any). */\r\n\tlistSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE\t\t\t\t/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */\r\n};\r\ntypedef struct xLIST_ITEM ListItem_t;\t\t\t\t\t/* For some reason lint wants this as two separate definitions. */\r\n\r\nstruct xMINI_LIST_ITEM\r\n{\r\n\tlistFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE\t\t\t\t/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */\r\n\tconfigLIST_VOLATILE TickType_t xItemValue;\r\n\tstruct xLIST_ITEM * configLIST_VOLATILE pxNext;\r\n\tstruct xLIST_ITEM * configLIST_VOLATILE pxPrevious;\r\n};\r\ntypedef struct xMINI_LIST_ITEM MiniListItem_t;\r\n\r\n/*\r\n * Definition of the type of queue used by the scheduler.\r\n */\r\ntypedef struct xLIST\r\n{\r\n\tlistFIRST_LIST_INTEGRITY_CHECK_VALUE\t\t\t\t/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */\r\n\tconfigLIST_VOLATILE UBaseType_t uxNumberOfItems;\r\n\tListItem_t * configLIST_VOLATILE pxIndex;\t\t/*< Used to walk through the list.  Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */\r\n\tMiniListItem_t xListEnd;\t\t\t\t\t\t/*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */\r\n\tlistSECOND_LIST_INTEGRITY_CHECK_VALUE\t\t\t\t/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */\r\n} List_t;\r\n\r\n/*\r\n * Access macro to set the owner of a list item.  The owner of a list item\r\n * is the object (usually a TCB) that contains the list item.\r\n *\r\n * \\page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER\r\n * \\ingroup LinkedList\r\n */\r\n#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner )\t\t( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) )\r\n\r\n/*\r\n * Access macro to get the owner of a list item.  The owner of a list item\r\n * is the object (usually a TCB) that contains the list item.\r\n *\r\n * \\page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER\r\n * \\ingroup LinkedList\r\n */\r\n#define listGET_LIST_ITEM_OWNER( pxListItem )\t( ( pxListItem )->pvOwner )\r\n\r\n/*\r\n * Access macro to set the value of the list item.  In most cases the value is\r\n * used to sort the list in descending order.\r\n *\r\n * \\page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE\r\n * \\ingroup LinkedList\r\n */\r\n#define listSET_LIST_ITEM_VALUE( pxListItem, xValue )\t( ( pxListItem )->xItemValue = ( xValue ) )\r\n\r\n/*\r\n * Access macro to retrieve the value of the list item.  The value can\r\n * represent anything - for example the priority of a task, or the time at\r\n * which a task should be unblocked.\r\n *\r\n * \\page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE\r\n * \\ingroup LinkedList\r\n */\r\n#define listGET_LIST_ITEM_VALUE( pxListItem )\t( ( pxListItem )->xItemValue )\r\n\r\n/*\r\n * Access macro to retrieve the value of the list item at the head of a given\r\n * list.\r\n *\r\n * \\page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE\r\n * \\ingroup LinkedList\r\n */\r\n#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList )\t( ( ( pxList )->xListEnd ).pxNext->xItemValue )\r\n\r\n/*\r\n * Return the list item at the head of the list.\r\n *\r\n * \\page listGET_HEAD_ENTRY listGET_HEAD_ENTRY\r\n * \\ingroup LinkedList\r\n */\r\n#define listGET_HEAD_ENTRY( pxList )\t( ( ( pxList )->xListEnd ).pxNext )\r\n\r\n/*\r\n * Return the list item at the head of the list.\r\n *\r\n * \\page listGET_NEXT listGET_NEXT\r\n * \\ingroup LinkedList\r\n */\r\n#define listGET_NEXT( pxListItem )\t( ( pxListItem )->pxNext )\r\n\r\n/*\r\n * Return the list item that marks the end of the list\r\n *\r\n * \\page listGET_END_MARKER listGET_END_MARKER\r\n * \\ingroup LinkedList\r\n */\r\n#define listGET_END_MARKER( pxList )\t( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) )\r\n\r\n/*\r\n * Access macro to determine if a list contains any items.  The macro will\r\n * only have the value true if the list is empty.\r\n *\r\n * \\page listLIST_IS_EMPTY listLIST_IS_EMPTY\r\n * \\ingroup LinkedList\r\n */\r\n#define listLIST_IS_EMPTY( pxList )\t( ( BaseType_t ) ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) )\r\n\r\n/*\r\n * Access macro to return the number of items in the list.\r\n */\r\n#define listCURRENT_LIST_LENGTH( pxList )\t( ( pxList )->uxNumberOfItems )\r\n\r\n/*\r\n * Access function to obtain the owner of the next entry in a list.\r\n *\r\n * The list member pxIndex is used to walk through a list.  Calling\r\n * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list\r\n * and returns that entry's pxOwner parameter.  Using multiple calls to this\r\n * function it is therefore possible to move through every item contained in\r\n * a list.\r\n *\r\n * The pxOwner parameter of a list item is a pointer to the object that owns\r\n * the list item.  In the scheduler this is normally a task control block.\r\n * The pxOwner parameter effectively creates a two way link between the list\r\n * item and its owner.\r\n *\r\n * @param pxTCB pxTCB is set to the address of the owner of the next list item.\r\n * @param pxList The list from which the next item owner is to be returned.\r\n *\r\n * \\page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY\r\n * \\ingroup LinkedList\r\n */\r\n#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList )\t\t\t\t\t\t\t\t\t\t\\\r\n{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\nList_t * const pxConstList = ( pxList );\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t/* Increment the index to the next item and return the item, ensuring */\t\t\t\t\\\r\n\t/* we don't return the marker used at the end of the list.  */\t\t\t\t\t\t\t\\\r\n\t( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext;\t\t\t\t\t\t\t\\\r\n\tif( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) )\t\\\r\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext;\t\t\t\t\t\t\\\r\n\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t( pxTCB ) = ( pxConstList )->pxIndex->pvOwner;\t\t\t\t\t\t\t\t\t\t\t\\\r\n}\r\n\r\n\r\n/*\r\n * Access function to obtain the owner of the first entry in a list.  Lists\r\n * are normally sorted in ascending item value order.\r\n *\r\n * This function returns the pxOwner member of the first item in the list.\r\n * The pxOwner parameter of a list item is a pointer to the object that owns\r\n * the list item.  In the scheduler this is normally a task control block.\r\n * The pxOwner parameter effectively creates a two way link between the list\r\n * item and its owner.\r\n *\r\n * @param pxList The list from which the owner of the head item is to be\r\n * returned.\r\n *\r\n * \\page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY\r\n * \\ingroup LinkedList\r\n */\r\n#define listGET_OWNER_OF_HEAD_ENTRY( pxList )  ( (&( ( pxList )->xListEnd ))->pxNext->pvOwner )\r\n\r\n/*\r\n * Check to see if a list item is within a list.  The list item maintains a\r\n * \"container\" pointer that points to the list it is in.  All this macro does\r\n * is check to see if the container and the list match.\r\n *\r\n * @param pxList The list we want to know if the list item is within.\r\n * @param pxListItem The list item we want to know if is in the list.\r\n * @return pdTRUE if the list item is in the list, otherwise pdFALSE.\r\n */\r\n#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( BaseType_t ) ( ( pxListItem )->pvContainer == ( void * ) ( pxList ) ) )\r\n\r\n/*\r\n * Return the list a list item is contained within (referenced from).\r\n *\r\n * @param pxListItem The list item being queried.\r\n * @return A pointer to the List_t object that references the pxListItem\r\n */\r\n#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pvContainer )\r\n\r\n/*\r\n * This provides a crude means of knowing if a list has been initialised, as\r\n * pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise()\r\n * function.\r\n */\r\n#define listLIST_IS_INITIALISED( pxList ) ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY )\r\n\r\n/*\r\n * Must be called before a list is used!  This initialises all the members\r\n * of the list structure and inserts the xListEnd item into the list as a\r\n * marker to the back of the list.\r\n *\r\n * @param pxList Pointer to the list being initialised.\r\n *\r\n * \\page vListInitialise vListInitialise\r\n * \\ingroup LinkedList\r\n */\r\nvoid vListInitialise( List_t * const pxList );\r\n\r\n/*\r\n * Must be called before a list item is used.  This sets the list container to\r\n * null so the item does not think that it is already contained in a list.\r\n *\r\n * @param pxItem Pointer to the list item being initialised.\r\n *\r\n * \\page vListInitialiseItem vListInitialiseItem\r\n * \\ingroup LinkedList\r\n */\r\nvoid vListInitialiseItem( ListItem_t * const pxItem );\r\n\r\n/*\r\n * Insert a list item into a list.  The item will be inserted into the list in\r\n * a position determined by its item value (descending item value order).\r\n *\r\n * @param pxList The list into which the item is to be inserted.\r\n *\r\n * @param pxNewListItem The item that is to be placed in the list.\r\n *\r\n * \\page vListInsert vListInsert\r\n * \\ingroup LinkedList\r\n */\r\nvoid vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem );\r\n\r\n/*\r\n * Insert a list item into a list.  The item will be inserted in a position\r\n * such that it will be the last item within the list returned by multiple\r\n * calls to listGET_OWNER_OF_NEXT_ENTRY.\r\n *\r\n * The list member pvIndex is used to walk through a list.  Calling\r\n * listGET_OWNER_OF_NEXT_ENTRY increments pvIndex to the next item in the list.\r\n * Placing an item in a list using vListInsertEnd effectively places the item\r\n * in the list position pointed to by pvIndex.  This means that every other\r\n * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before\r\n * the pvIndex parameter again points to the item being inserted.\r\n *\r\n * @param pxList The list into which the item is to be inserted.\r\n *\r\n * @param pxNewListItem The list item to be inserted into the list.\r\n *\r\n * \\page vListInsertEnd vListInsertEnd\r\n * \\ingroup LinkedList\r\n */\r\nvoid vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem );\r\n\r\n/*\r\n * Remove an item from a list.  The list item has a pointer to the list that\r\n * it is in, so only the list item need be passed into the function.\r\n *\r\n * @param uxListRemove The item to be removed.  The item will remove itself from\r\n * the list pointed to by it's pxContainer parameter.\r\n *\r\n * @return The number of items that remain in the list after the list item has\r\n * been removed.\r\n *\r\n * \\page uxListRemove uxListRemove\r\n * \\ingroup LinkedList\r\n */\r\nUBaseType_t uxListRemove( ListItem_t * const pxItemToRemove );\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RTOS/src/mpu_wrappers.h",
    "content": "/*\r\n    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r\n    All rights reserved\r\n\r\n    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r\n\r\n    This file is part of the FreeRTOS distribution.\r\n\r\n    FreeRTOS is free software; you can redistribute it and/or modify it under\r\n    the terms of the GNU General Public License (version 2) as published by the\r\n    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r\n\r\n    ***************************************************************************\r\n    >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r\n    >>!   distribute a combined work that includes FreeRTOS without being   !<<\r\n    >>!   obliged to provide the source code for proprietary components     !<<\r\n    >>!   outside of the FreeRTOS kernel.                                   !<<\r\n    ***************************************************************************\r\n\r\n    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r\n    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r\n    FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r\n    link: http://www.freertos.org/a00114.html\r\n\r\n    ***************************************************************************\r\n     *                                                                       *\r\n     *    FreeRTOS provides completely free yet professionally developed,    *\r\n     *    robust, strictly quality controlled, supported, and cross          *\r\n     *    platform software that is more than just the market leader, it     *\r\n     *    is the industry's de facto standard.                               *\r\n     *                                                                       *\r\n     *    Help yourself get started quickly while simultaneously helping     *\r\n     *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r\n     *    tutorial book, reference manual, or both:                          *\r\n     *    http://www.FreeRTOS.org/Documentation                              *\r\n     *                                                                       *\r\n    ***************************************************************************\r\n\r\n    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r\n    the FAQ page \"My application does not run, what could be wrong?\".  Have you\r\n    defined configASSERT()?\r\n\r\n    http://www.FreeRTOS.org/support - In return for receiving this top quality\r\n    embedded software for free we request you assist our global community by\r\n    participating in the support forum.\r\n\r\n    http://www.FreeRTOS.org/training - Investing in training allows your team to\r\n    be as productive as possible as early as possible.  Now you can receive\r\n    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r\n    Ltd, and the world's leading authority on the world's leading RTOS.\r\n\r\n    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r\n    including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r\n    compatible FAT file system, and our tiny thread aware UDP/IP stack.\r\n\r\n    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r\n    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r\n\r\n    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r\n    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r\n    licenses offer ticketed support, indemnification and commercial middleware.\r\n\r\n    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r\n    engineered and independently SIL3 certified version for use in safety and\r\n    mission critical applications that require provable dependability.\r\n\r\n    1 tab == 4 spaces!\r\n*/\r\n\r\n#ifndef MPU_WRAPPERS_H\r\n#define MPU_WRAPPERS_H\r\n\r\n/* This file redefines API functions to be called through a wrapper macro, but\r\nonly for ports that are using the MPU. */\r\n#ifdef portUSING_MPU_WRAPPERS\r\n\r\n\t/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is\r\n\tincluded from queue.c or task.c to prevent it from having an effect within\r\n\tthose files. */\r\n\t#ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r\n\r\n\t\t#define xTaskGenericCreate\t\t\t\tMPU_xTaskGenericCreate\r\n\t\t#define vTaskAllocateMPURegions\t\t\tMPU_vTaskAllocateMPURegions\r\n\t\t#define vTaskDelete\t\t\t\t\t\tMPU_vTaskDelete\r\n\t\t#define vTaskDelayUntil\t\t\t\t\tMPU_vTaskDelayUntil\r\n\t\t#define vTaskDelay\t\t\t\t\t\tMPU_vTaskDelay\r\n\t\t#define uxTaskPriorityGet\t\t\t\tMPU_uxTaskPriorityGet\r\n\t\t#define vTaskPrioritySet\t\t\t\tMPU_vTaskPrioritySet\r\n\t\t#define eTaskGetState\t\t\t\t\tMPU_eTaskGetState\r\n\t\t#define vTaskSuspend\t\t\t\t\tMPU_vTaskSuspend\r\n\t\t#define vTaskResume\t\t\t\t\t\tMPU_vTaskResume\r\n\t\t#define vTaskSuspendAll\t\t\t\t\tMPU_vTaskSuspendAll\r\n\t\t#define xTaskResumeAll\t\t\t\t\tMPU_xTaskResumeAll\r\n\t\t#define xTaskGetTickCount\t\t\t\tMPU_xTaskGetTickCount\r\n\t\t#define uxTaskGetNumberOfTasks\t\t\tMPU_uxTaskGetNumberOfTasks\r\n\t\t#define vTaskList\t\t\t\t\t\tMPU_vTaskList\r\n\t\t#define vTaskGetRunTimeStats\t\t\tMPU_vTaskGetRunTimeStats\r\n\t\t#define vTaskSetApplicationTaskTag\t\tMPU_vTaskSetApplicationTaskTag\r\n\t\t#define xTaskGetApplicationTaskTag\t\tMPU_xTaskGetApplicationTaskTag\r\n\t\t#define xTaskCallApplicationTaskHook\tMPU_xTaskCallApplicationTaskHook\r\n\t\t#define uxTaskGetStackHighWaterMark\t\tMPU_uxTaskGetStackHighWaterMark\r\n\t\t#define xTaskGetCurrentTaskHandle\t\tMPU_xTaskGetCurrentTaskHandle\r\n\t\t#define xTaskGetSchedulerState\t\t\tMPU_xTaskGetSchedulerState\r\n\t\t#define xTaskGetIdleTaskHandle\t\t\tMPU_xTaskGetIdleTaskHandle\r\n\t\t#define uxTaskGetSystemState\t\t\tMPU_uxTaskGetSystemState\r\n\r\n\t\t#define xQueueGenericCreate\t\t\t\tMPU_xQueueGenericCreate\r\n\t\t#define xQueueCreateMutex\t\t\t\tMPU_xQueueCreateMutex\r\n\t\t#define xQueueGiveMutexRecursive\t\tMPU_xQueueGiveMutexRecursive\r\n\t\t#define xQueueTakeMutexRecursive\t\tMPU_xQueueTakeMutexRecursive\r\n\t\t#define xQueueCreateCountingSemaphore\tMPU_xQueueCreateCountingSemaphore\r\n\t\t#define xQueueGenericSend\t\t\t\tMPU_xQueueGenericSend\r\n\t\t#define xQueueAltGenericSend\t\t\tMPU_xQueueAltGenericSend\r\n\t\t#define xQueueAltGenericReceive\t\t\tMPU_xQueueAltGenericReceive\r\n\t\t#define xQueueGenericReceive\t\t\tMPU_xQueueGenericReceive\r\n\t\t#define uxQueueMessagesWaiting\t\t\tMPU_uxQueueMessagesWaiting\r\n\t\t#define vQueueDelete\t\t\t\t\tMPU_vQueueDelete\r\n\t\t#define xQueueGenericReset\t\t\t\tMPU_xQueueGenericReset\r\n\t\t#define xQueueCreateSet\t\t\t\t\tMPU_xQueueCreateSet\r\n\t\t#define xQueueSelectFromSet\t\t\t\tMPU_xQueueSelectFromSet\r\n\t\t#define xQueueAddToSet\t\t\t\t\tMPU_xQueueAddToSet\r\n\t\t#define xQueueRemoveFromSet\t\t\t\tMPU_xQueueRemoveFromSet\r\n\t\t#define xQueuePeekFromISR\t\t\t\tMPU_xQueuePeekFromISR\r\n\t\t#define xQueueGetMutexHolder\t\t\tMPU_xQueueGetMutexHolder\r\n\r\n\t\t#define pvPortMalloc\t\t\t\t\tMPU_pvPortMalloc\r\n\t\t#define vPortFree\t\t\t\t\t\tMPU_vPortFree\r\n\t\t#define xPortGetFreeHeapSize\t\t\tMPU_xPortGetFreeHeapSize\r\n\t\t#define vPortInitialiseBlocks\t\t\tMPU_vPortInitialiseBlocks\r\n\r\n\t\t#if configQUEUE_REGISTRY_SIZE > 0\r\n\t\t\t#define vQueueAddToRegistry\t\t\t\tMPU_vQueueAddToRegistry\r\n\t\t\t#define vQueueUnregisterQueue\t\t\tMPU_vQueueUnregisterQueue\r\n\t\t#endif\r\n\r\n\t\t/* Remove the privileged function macro. */\r\n\t\t#define PRIVILEGED_FUNCTION\r\n\r\n\t#else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */\r\n\r\n\t\t/* Ensure API functions go in the privileged execution section. */\r\n\t\t#define PRIVILEGED_FUNCTION __attribute__((section(\"privileged_functions\")))\r\n\t\t#define PRIVILEGED_DATA __attribute__((section(\"privileged_data\")))\r\n\r\n\t#endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */\r\n\r\n#else /* portUSING_MPU_WRAPPERS */\r\n\r\n\t#define PRIVILEGED_FUNCTION\r\n\t#define PRIVILEGED_DATA\r\n\t#define portUSING_MPU_WRAPPERS 0\r\n\r\n#endif /* portUSING_MPU_WRAPPERS */\r\n\r\n\r\n#endif /* MPU_WRAPPERS_H */\r\n\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RTOS/src/port.c",
    "content": "/*\r\n    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r\n    All rights reserved\r\n\r\n    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r\n\r\n    This file is part of the FreeRTOS distribution.\r\n\r\n    FreeRTOS is free software; you can redistribute it and/or modify it under\r\n    the terms of the GNU General Public License (version 2) as published by the\r\n    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r\n\r\n    ***************************************************************************\r\n    >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r\n    >>!   distribute a combined work that includes FreeRTOS without being   !<<\r\n    >>!   obliged to provide the source code for proprietary components     !<<\r\n    >>!   outside of the FreeRTOS kernel.                                   !<<\r\n    ***************************************************************************\r\n\r\n    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r\n    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r\n    FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r\n    link: http://www.freertos.org/a00114.html\r\n\r\n    ***************************************************************************\r\n     *                                                                       *\r\n     *    FreeRTOS provides completely free yet professionally developed,    *\r\n     *    robust, strictly quality controlled, supported, and cross          *\r\n     *    platform software that is more than just the market leader, it     *\r\n     *    is the industry's de facto standard.                               *\r\n     *                                                                       *\r\n     *    Help yourself get started quickly while simultaneously helping     *\r\n     *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r\n     *    tutorial book, reference manual, or both:                          *\r\n     *    http://www.FreeRTOS.org/Documentation                              *\r\n     *                                                                       *\r\n    ***************************************************************************\r\n\r\n    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r\n    the FAQ page \"My application does not run, what could be wrong?\".  Have you\r\n    defined configASSERT()?\r\n\r\n    http://www.FreeRTOS.org/support - In return for receiving this top quality\r\n    embedded software for free we request you assist our global community by\r\n    participating in the support forum.\r\n\r\n    http://www.FreeRTOS.org/training - Investing in training allows your team to\r\n    be as productive as possible as early as possible.  Now you can receive\r\n    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r\n    Ltd, and the world's leading authority on the world's leading RTOS.\r\n\r\n    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r\n    including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r\n    compatible FAT file system, and our tiny thread aware UDP/IP stack.\r\n\r\n    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r\n    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r\n\r\n    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r\n    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r\n    licenses offer ticketed support, indemnification and commercial middleware.\r\n\r\n    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r\n    engineered and independently SIL3 certified version for use in safety and\r\n    mission critical applications that require provable dependability.\r\n\r\n    1 tab == 4 spaces!\r\n*/\r\n\r\n/*-----------------------------------------------------------\r\n * Implementation of functions defined in portable.h for the ARM CM4F port.\r\n *----------------------------------------------------------*/\r\n\r\n/* Scheduler includes. */\r\n#include \"FreeRTOS.h\"\r\n#include \"task.h\"\r\n\r\n#ifndef __VFP_FP__\r\n\t#error This port can only be used when the project options are configured to enable hardware floating point support.\r\n#endif\r\n\r\n#ifndef configSYSTICK_CLOCK_HZ\r\n\t#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r\n\t/* Ensure the SysTick is clocked at the same frequency as the core. */\r\n\t#define portNVIC_SYSTICK_CLK_BIT\t( 1UL << 2UL )\r\n#else\r\n\t/* The way the SysTick is clocked is not modified in case it is not the same\r\n\tas the core. */\r\n\t#define portNVIC_SYSTICK_CLK_BIT\t( 0 )\r\n#endif\r\n\r\n/* Constants required to manipulate the core.  Registers first... */\r\n#define portNVIC_SYSTICK_CTRL_REG\t\t\t( * ( ( volatile uint32_t * ) 0xe000e010 ) )\r\n#define portNVIC_SYSTICK_LOAD_REG\t\t\t( * ( ( volatile uint32_t * ) 0xe000e014 ) )\r\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG\t( * ( ( volatile uint32_t * ) 0xe000e018 ) )\r\n#define portNVIC_SYSPRI2_REG\t\t\t\t( * ( ( volatile uint32_t * ) 0xe000ed20 ) )\r\n/* ...then bits in the registers. */\r\n#define portNVIC_SYSTICK_INT_BIT\t\t\t( 1UL << 1UL )\r\n#define portNVIC_SYSTICK_ENABLE_BIT\t\t\t( 1UL << 0UL )\r\n#define portNVIC_SYSTICK_COUNT_FLAG_BIT\t\t( 1UL << 16UL )\r\n#define portNVIC_PENDSVCLEAR_BIT \t\t\t( 1UL << 27UL )\r\n#define portNVIC_PEND_SYSTICK_CLEAR_BIT\t\t( 1UL << 25UL )\r\n\r\n#define portNVIC_PENDSV_PRI\t\t\t\t\t( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r\n#define portNVIC_SYSTICK_PRI\t\t\t\t( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r\n\r\n/* Constants required to check the validity of an interrupt priority. */\r\n#define portFIRST_USER_INTERRUPT_NUMBER\t\t( 16 )\r\n#define portNVIC_IP_REGISTERS_OFFSET_16 \t( 0xE000E3F0 )\r\n#define portAIRCR_REG\t\t\t\t\t\t( * ( ( volatile uint32_t * ) 0xE000ED0C ) )\r\n#define portMAX_8_BIT_VALUE\t\t\t\t\t( ( uint8_t ) 0xff )\r\n#define portTOP_BIT_OF_BYTE\t\t\t\t\t( ( uint8_t ) 0x80 )\r\n#define portMAX_PRIGROUP_BITS\t\t\t\t( ( uint8_t ) 7 )\r\n#define portPRIORITY_GROUP_MASK\t\t\t\t( 0x07UL << 8UL )\r\n#define portPRIGROUP_SHIFT\t\t\t\t\t( 8UL )\r\n\r\n/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */\r\n#define portVECTACTIVE_MASK\t\t\t\t\t( 0xFFUL )\r\n\r\n/* Constants required to manipulate the VFP. */\r\n#define portFPCCR\t\t\t\t\t( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */\r\n#define portASPEN_AND_LSPEN_BITS\t( 0x3UL << 30UL )\r\n\r\n/* Constants required to set up the initial stack. */\r\n#define portINITIAL_XPSR\t\t\t( 0x01000000 )\r\n#define portINITIAL_EXEC_RETURN\t\t( 0xfffffffd )\r\n\r\n/* The systick is a 24-bit counter. */\r\n#define portMAX_24_BIT_NUMBER\t\t\t\t( 0xffffffUL )\r\n\r\n/* A fiddle factor to estimate the number of SysTick counts that would have\r\noccurred while the SysTick counter is stopped during tickless idle\r\ncalculations. */\r\n#define portMISSED_COUNTS_FACTOR\t\t\t( 45UL )\r\n\r\n/* Let the user override the pre-loading of the initial LR with the address of\r\nprvTaskExitError() in case is messes up unwinding of the stack in the\r\ndebugger. */\r\n#ifdef configTASK_RETURN_ADDRESS\r\n\t#define portTASK_RETURN_ADDRESS\tconfigTASK_RETURN_ADDRESS\r\n#else\r\n\t#define portTASK_RETURN_ADDRESS\tprvTaskExitError\r\n#endif\r\n\r\n/* Each task maintains its own interrupt status in the critical nesting\r\nvariable. */\r\nstatic UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\r\n\r\n/*\r\n * Setup the timer to generate the tick interrupts.  The implementation in this\r\n * file is weak to allow application writers to change the timer used to\r\n * generate the tick interrupt.\r\n */\r\nvoid vPortSetupTimerInterrupt( void );\r\n\r\n/*\r\n * Exception handlers.\r\n */\r\nvoid xPortPendSVHandler( void ) __attribute__ (( naked ));\r\nvoid xPortSysTickHandler( void );\r\nvoid vPortSVCHandler( void ) __attribute__ (( naked ));\r\n\r\n/*\r\n * Start first task is a separate function so it can be tested in isolation.\r\n */\r\nstatic void prvPortStartFirstTask( void ) __attribute__ (( naked ));\r\n\r\n/*\r\n * Function to enable the VFP.\r\n */\r\n static void vPortEnableVFP( void ) __attribute__ (( naked ));\r\n\r\n/*\r\n * Used to catch tasks that attempt to return from their implementing function.\r\n */\r\nstatic void prvTaskExitError( void );\r\n\r\n/*-----------------------------------------------------------*/\r\n\r\n/*\r\n * The number of SysTick increments that make up one tick period.\r\n */\r\n#if configUSE_TICKLESS_IDLE == 1\r\n\tstatic uint32_t ulTimerCountsForOneTick = 0;\r\n#endif /* configUSE_TICKLESS_IDLE */\r\n\r\n/*\r\n * The maximum number of tick periods that can be suppressed is limited by the\r\n * 24 bit resolution of the SysTick timer.\r\n */\r\n#if configUSE_TICKLESS_IDLE == 1\r\n\tstatic uint32_t xMaximumPossibleSuppressedTicks = 0;\r\n#endif /* configUSE_TICKLESS_IDLE */\r\n\r\n/*\r\n * Compensate for the CPU cycles that pass while the SysTick is stopped (low\r\n * power functionality only.\r\n */\r\n#if configUSE_TICKLESS_IDLE == 1\r\n\tstatic uint32_t ulStoppedTimerCompensation = 0;\r\n#endif /* configUSE_TICKLESS_IDLE */\r\n\r\n/*\r\n * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\r\n * FreeRTOS API functions are not called from interrupts that have been assigned\r\n * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\r\n */\r\n#if ( configASSERT_DEFINED == 1 )\r\n\t static uint8_t ucMaxSysCallPriority = 0;\r\n\t static uint32_t ulMaxPRIGROUPValue = 0;\r\n\t static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;\r\n#endif /* configASSERT_DEFINED */\r\n\r\n/*-----------------------------------------------------------*/\r\n\r\n/*\r\n * See header file for description.\r\n */\r\nStackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\r\n{\r\n\t/* Simulate the stack frame as it would be created by a context switch\r\n\tinterrupt. */\r\n\r\n\t/* Offset added to account for the way the MCU uses the stack on entry/exit\r\n\tof interrupts, and to ensure alignment. */\r\n\tpxTopOfStack--;\r\n\r\n\t*pxTopOfStack = portINITIAL_XPSR;\t/* xPSR */\r\n\tpxTopOfStack--;\r\n\t*pxTopOfStack = ( StackType_t ) pxCode;\t/* PC */\r\n\tpxTopOfStack--;\r\n\t*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;\t/* LR */\r\n\r\n\t/* Save code space by skipping register initialisation. */\r\n\tpxTopOfStack -= 5;\t/* R12, R3, R2 and R1. */\r\n\t*pxTopOfStack = ( StackType_t ) pvParameters;\t/* R0 */\r\n\r\n\t/* A save method is being used that requires each task to maintain its\r\n\town exec return value. */\r\n\tpxTopOfStack--;\r\n\t*pxTopOfStack = portINITIAL_EXEC_RETURN;\r\n\r\n\tpxTopOfStack -= 8;\t/* R11, R10, R9, R8, R7, R6, R5 and R4. */\r\n\r\n\treturn pxTopOfStack;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nstatic void prvTaskExitError( void )\r\n{\r\n\t/* A function that implements a task must not exit or attempt to return to\r\n\tits caller as there is nothing to return to.  If a task wants to exit it\r\n\tshould instead call vTaskDelete( NULL ).\r\n\r\n\tArtificially force an assert() to be triggered if configASSERT() is\r\n\tdefined, then stop here so application writers can catch the error. */\r\n\tconfigASSERT( uxCriticalNesting == ~0UL );\r\n\tportDISABLE_INTERRUPTS();\r\n\tfor( ;; );\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nvoid vPortSVCHandler( void )\r\n{\r\n\t__asm volatile (\r\n\t\t\t\t\t\"\tldr\tr3, pxCurrentTCBConst2\t\t\\n\" /* Restore the context. */\r\n\t\t\t\t\t\"\tldr r1, [r3]\t\t\t\t\t\\n\" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */\r\n\t\t\t\t\t\"\tldr r0, [r1]\t\t\t\t\t\\n\" /* The first item in pxCurrentTCB is the task top of stack. */\r\n\t\t\t\t\t\"\tldmia r0!, {r4-r11, r14}\t\t\\n\" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\r\n\t\t\t\t\t\"\tmsr psp, r0\t\t\t\t\t\t\\n\" /* Restore the task stack pointer. */\r\n\t\t\t\t\t\"\tisb\t\t\t\t\t\t\t\t\\n\"\r\n\t\t\t\t\t\"\tmov r0, #0 \t\t\t\t\t\t\\n\"\r\n\t\t\t\t\t\"\tmsr\tbasepri, r0\t\t\t\t\t\\n\"\r\n\t\t\t\t\t\"\tbx r14\t\t\t\t\t\t\t\\n\"\r\n\t\t\t\t\t\"\t\t\t\t\t\t\t\t\t\\n\"\r\n\t\t\t\t\t\"\t.align 2\t\t\t\t\t\t\\n\"\r\n\t\t\t\t\t\"pxCurrentTCBConst2: .word pxCurrentTCB\t\t\t\t\\n\"\r\n\t\t\t\t);\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nstatic void prvPortStartFirstTask( void )\r\n{\r\n\t__asm volatile(\r\n\t\t\t\t\t\" ldr r0, =0xE000ED08 \t\\n\" /* Use the NVIC offset register to locate the stack. */\r\n\t\t\t\t\t\" ldr r0, [r0] \t\t\t\\n\"\r\n\t\t\t\t\t\" ldr r0, [r0] \t\t\t\\n\"\r\n\t\t\t\t\t\" msr msp, r0\t\t\t\\n\" /* Set the msp back to the start of the stack. */\r\n\t\t\t\t\t\" cpsie i\t\t\t\t\\n\" /* Globally enable interrupts. */\r\n\t\t\t\t\t\" cpsie f\t\t\t\t\\n\"\r\n\t\t\t\t\t\" dsb\t\t\t\t\t\\n\"\r\n\t\t\t\t\t\" isb\t\t\t\t\t\\n\"\r\n\t\t\t\t\t\" svc 0\t\t\t\t\t\\n\" /* System call to start first task. */\r\n\t\t\t\t\t\" nop\t\t\t\t\t\\n\"\r\n\t\t\t\t);\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\n/*\r\n * See header file for description.\r\n */\r\nBaseType_t xPortStartScheduler( void )\r\n{\r\n\t/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\r\n\tSee http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r\n\tconfigASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\r\n\r\n\t#if( configASSERT_DEFINED == 1 )\r\n\t{\r\n\t\tvolatile uint32_t ulOriginalPriority;\r\n\t\tvolatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r\n\t\tvolatile uint8_t ucMaxPriorityValue;\r\n\r\n\t\t/* Determine the maximum priority from which ISR safe FreeRTOS API\r\n\t\tfunctions can be called.  ISR safe functions are those that end in\r\n\t\t\"FromISR\".  FreeRTOS maintains separate thread and ISR API functions to\r\n\t\tensure interrupt entry is as fast and simple as possible.\r\n\r\n\t\tSave the interrupt priority value that is about to be clobbered. */\r\n\t\tulOriginalPriority = *pucFirstUserPriorityRegister;\r\n\r\n\t\t/* Determine the number of priority bits available.  First write to all\r\n\t\tpossible bits. */\r\n\t\t*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r\n\r\n\t\t/* Read the value back to see how many bits stuck. */\r\n\t\tucMaxPriorityValue = *pucFirstUserPriorityRegister;\r\n\r\n\t\t/* Use the same mask on the maximum system call priority. */\r\n\t\tucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r\n\r\n\t\t/* Calculate the maximum acceptable priority group value for the number\r\n\t\tof bits read back. */\r\n\t\tulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\r\n\t\twhile( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r\n\t\t{\r\n\t\t\tulMaxPRIGROUPValue--;\r\n\t\t\tucMaxPriorityValue <<= ( uint8_t ) 0x01;\r\n\t\t}\r\n\r\n\t\t/* Shift the priority group value back to its position within the AIRCR\r\n\t\tregister. */\r\n\t\tulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r\n\t\tulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\r\n\r\n\t\t/* Restore the clobbered interrupt priority register to its original\r\n\t\tvalue. */\r\n\t\t*pucFirstUserPriorityRegister = ulOriginalPriority;\r\n\t}\r\n\t#endif /* conifgASSERT_DEFINED */\r\n\r\n\t/* Make PendSV and SysTick the lowest priority interrupts. */\r\n\tportNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r\n\tportNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r\n\r\n\t/* Start the timer that generates the tick ISR.  Interrupts are disabled\r\n\there already. */\r\n\tvPortSetupTimerInterrupt();\r\n\r\n\t/* Initialise the critical nesting count ready for the first task. */\r\n\tuxCriticalNesting = 0;\r\n\r\n\t/* Ensure the VFP is enabled - it should be anyway. */\r\n\tvPortEnableVFP();\r\n\r\n\t/* Lazy save always. */\r\n\t*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;\r\n\r\n\t/* Start the first task. */\r\n\tprvPortStartFirstTask();\r\n\r\n\t/* Should never get here as the tasks will now be executing!  Call the task\r\n\texit error function to prevent compiler warnings about a static function\r\n\tnot being called in the case that the application writer overrides this\r\n\tfunctionality by defining configTASK_RETURN_ADDRESS. */\r\n\tprvTaskExitError();\r\n\r\n\t/* Should not get here! */\r\n\treturn 0;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nvoid vPortEndScheduler( void )\r\n{\r\n\t/* Not implemented in ports where there is nothing to return to.\r\n\tArtificially force an assert. */\r\n\tconfigASSERT( uxCriticalNesting == 1000UL );\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nvoid vPortEnterCritical( void )\r\n{\r\n\tportDISABLE_INTERRUPTS();\r\n\tuxCriticalNesting++;\r\n\r\n\t/* This is not the interrupt safe version of the enter critical function so\r\n\tassert() if it is being called from an interrupt context.  Only API\r\n\tfunctions that end in \"FromISR\" can be used in an interrupt.  Only assert if\r\n\tthe critical nesting count is 1 to protect against recursive calls if the\r\n\tassert function also uses a critical section. */\r\n\tif( uxCriticalNesting == 1 )\r\n\t{\r\n\t\tconfigASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );\r\n\t}\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nvoid vPortExitCritical( void )\r\n{\r\n\tconfigASSERT( uxCriticalNesting );\r\n\tuxCriticalNesting--;\r\n\tif( uxCriticalNesting == 0 )\r\n\t{\r\n\t\tportENABLE_INTERRUPTS();\r\n\t}\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nvoid xPortPendSVHandler( void )\r\n{\r\n\t/* This is a naked function. */\r\n\r\n\t__asm volatile\r\n\t(\r\n\t\"\tmrs r0, psp\t\t\t\t\t\t\t\\n\"\r\n\t\"\tisb\t\t\t\t\t\t\t\t\t\\n\"\r\n\t\"\t\t\t\t\t\t\t\t\t\t\\n\"\r\n\t\"\tldr\tr3, pxCurrentTCBConst\t\t\t\\n\" /* Get the location of the current TCB. */\r\n\t\"\tldr\tr2, [r3]\t\t\t\t\t\t\\n\"\r\n\t\"\t\t\t\t\t\t\t\t\t\t\\n\"\r\n\t\"\ttst r14, #0x10\t\t\t\t\t\t\\n\" /* Is the task using the FPU context?  If so, push high vfp registers. */\r\n\t\"\tit eq\t\t\t\t\t\t\t\t\\n\"\r\n\t\"\tvstmdbeq r0!, {s16-s31}\t\t\t\t\\n\"\r\n\t\"\t\t\t\t\t\t\t\t\t\t\\n\"\r\n\t\"\tstmdb r0!, {r4-r11, r14}\t\t\t\\n\" /* Save the core registers. */\r\n\t\"\t\t\t\t\t\t\t\t\t\t\\n\"\r\n\t\"\tstr r0, [r2]\t\t\t\t\t\t\\n\" /* Save the new top of stack into the first member of the TCB. */\r\n\t\"\t\t\t\t\t\t\t\t\t\t\\n\"\r\n\t\"\tstmdb sp!, {r3}\t\t\t\t\t\t\\n\"\r\n\t\"\tmov r0, %0 \t\t\t\t\t\t\t\\n\"\r\n\t\"\tcpsid i\t\t\t\t\t\t\t\t\\n\" /* Errata workaround. */\r\n\t\"\tmsr basepri, r0\t\t\t\t\t\t\\n\"\r\n\t\"\tdsb\t\t\t\t\t\t\t\t\t\\n\"\r\n\t\"   isb\t\t\t\t\t\t\t\t\t\\n\"\r\n\t\"\tcpsie i\t\t\t\t\t\t\t\t\\n\" /* Errata workaround. */\r\n\t\"\tbl vTaskSwitchContext\t\t\t\t\\n\"\r\n\t\"\tmov r0, #0\t\t\t\t\t\t\t\\n\"\r\n\t\"\tmsr basepri, r0\t\t\t\t\t\t\\n\"\r\n\t\"\tldmia sp!, {r3}\t\t\t\t\t\t\\n\"\r\n\t\"\t\t\t\t\t\t\t\t\t\t\\n\"\r\n\t\"\tldr r1, [r3]\t\t\t\t\t\t\\n\" /* The first item in pxCurrentTCB is the task top of stack. */\r\n\t\"\tldr r0, [r1]\t\t\t\t\t\t\\n\"\r\n\t\"\t\t\t\t\t\t\t\t\t\t\\n\"\r\n\t\"\tldmia r0!, {r4-r11, r14}\t\t\t\\n\" /* Pop the core registers. */\r\n\t\"\t\t\t\t\t\t\t\t\t\t\\n\"\r\n\t\"\ttst r14, #0x10\t\t\t\t\t\t\\n\" /* Is the task using the FPU context?  If so, pop the high vfp registers too. */\r\n\t\"\tit eq\t\t\t\t\t\t\t\t\\n\"\r\n\t\"\tvldmiaeq r0!, {s16-s31}\t\t\t\t\\n\"\r\n\t\"\t\t\t\t\t\t\t\t\t\t\\n\"\r\n\t\"\tmsr psp, r0\t\t\t\t\t\t\t\\n\"\r\n\t\"\tisb\t\t\t\t\t\t\t\t\t\\n\"\r\n\t\"\t\t\t\t\t\t\t\t\t\t\\n\"\r\n\t#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */\r\n\t\t#if WORKAROUND_PMU_CM001 == 1\r\n\t\"\t\t\tpush { r14 }\t\t\t\t\\n\"\r\n\t\"\t\t\tpop { pc }\t\t\t\t\t\\n\"\r\n\t\t#endif\r\n\t#endif\r\n\t\"\t\t\t\t\t\t\t\t\t\t\\n\"\r\n\t\"\tbx r14\t\t\t\t\t\t\t\t\\n\"\r\n\t\"\t\t\t\t\t\t\t\t\t\t\\n\"\r\n\t\"\t.align 2\t\t\t\t\t\t\t\\n\"\r\n\t\"pxCurrentTCBConst: .word pxCurrentTCB\t\\n\"\r\n\t::\"i\"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r\n\t);\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nvoid xPortSysTickHandler( void )\r\n{\r\n\t/* The SysTick runs at the lowest interrupt priority, so when this interrupt\r\n\texecutes all interrupts must be unmasked.  There is therefore no need to\r\n\tsave and then restore the interrupt mask value as its value is already\r\n\tknown. */\r\n\t( void ) portSET_INTERRUPT_MASK_FROM_ISR();\r\n\t{\r\n\t\t/* Increment the RTOS tick. */\r\n\t\tif( xTaskIncrementTick() != pdFALSE )\r\n\t\t{\r\n\t\t\t/* A context switch is required.  Context switching is performed in\r\n\t\t\tthe PendSV interrupt.  Pend the PendSV interrupt. */\r\n\t\t\tportNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r\n\t\t}\r\n\t}\r\n\tportCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\n#if configUSE_TICKLESS_IDLE == 1\r\n\r\n\t__attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\r\n\t{\r\n\tuint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL;\r\n\tTickType_t xModifiableIdleTime;\r\n\r\n\t\t/* Make sure the SysTick reload value does not overflow the counter. */\r\n\t\tif( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\r\n\t\t{\r\n\t\t\txExpectedIdleTime = xMaximumPossibleSuppressedTicks;\r\n\t\t}\r\n\r\n\t\t/* Stop the SysTick momentarily.  The time the SysTick is stopped for\r\n\t\tis accounted for as best it can be, but using the tickless mode will\r\n\t\tinevitably result in some tiny drift of the time maintained by the\r\n\t\tkernel with respect to calendar time. */\r\n\t\tportNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;\r\n\r\n\t\t/* Calculate the reload value required to wait xExpectedIdleTime\r\n\t\ttick periods.  -1 is used because this code will execute part way\r\n\t\tthrough one of the tick periods. */\r\n\t\tulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\r\n\t\tif( ulReloadValue > ulStoppedTimerCompensation )\r\n\t\t{\r\n\t\t\tulReloadValue -= ulStoppedTimerCompensation;\r\n\t\t}\r\n\r\n\t\t/* Enter a critical section but don't use the taskENTER_CRITICAL()\r\n\t\tmethod as that will mask interrupts that should exit sleep mode. */\r\n\t\t__asm volatile( \"cpsid i\" );\r\n\r\n\t\t/* If a context switch is pending or a task is waiting for the scheduler\r\n\t\tto be unsuspended then abandon the low power entry. */\r\n\t\tif( eTaskConfirmSleepModeStatus() == eAbortSleep )\r\n\t\t{\r\n\t\t\t/* Restart from whatever is left in the count register to complete\r\n\t\t\tthis tick period. */\r\n\t\t\tportNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;\r\n\r\n\t\t\t/* Restart SysTick. */\r\n\t\t\tportNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r\n\r\n\t\t\t/* Reset the reload register to the value required for normal tick\r\n\t\t\tperiods. */\r\n\t\t\tportNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r\n\r\n\t\t\t/* Re-enable interrupts - see comments above the cpsid instruction()\r\n\t\t\tabove. */\r\n\t\t\t__asm volatile( \"cpsie i\" );\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\t/* Set the new reload value. */\r\n\t\t\tportNVIC_SYSTICK_LOAD_REG = ulReloadValue;\r\n\r\n\t\t\t/* Clear the SysTick count flag and set the count value back to\r\n\t\t\tzero. */\r\n\t\t\tportNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r\n\r\n\t\t\t/* Restart SysTick. */\r\n\t\t\tportNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r\n\r\n\t\t\t/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\r\n\t\t\tset its parameter to 0 to indicate that its implementation contains\r\n\t\t\tits own wait for interrupt or wait for event instruction, and so wfi\r\n\t\t\tshould not be executed again.  However, the original expected idle\r\n\t\t\ttime variable must remain unmodified, so a copy is taken. */\r\n\t\t\txModifiableIdleTime = xExpectedIdleTime;\r\n\t\t\tconfigPRE_SLEEP_PROCESSING( &xModifiableIdleTime );\r\n\t\t\tif( xModifiableIdleTime > 0 )\r\n\t\t\t{\r\n\t\t\t\t__asm volatile( \"dsb\" );\r\n\t\t\t\t__asm volatile( \"wfi\" );\r\n\t\t\t\t__asm volatile( \"isb\" );\r\n\t\t\t}\r\n\t\t\tconfigPOST_SLEEP_PROCESSING( &xExpectedIdleTime );\r\n\r\n\t\t\t/* Stop SysTick.  Again, the time the SysTick is stopped for is\r\n\t\t\taccounted for as best it can be, but using the tickless mode will\r\n\t\t\tinevitably result in some tiny drift of the time maintained by the\r\n\t\t\tkernel with respect to calendar time. */\r\n\t\t\tulSysTickCTRL = portNVIC_SYSTICK_CTRL_REG;\r\n\t\t\tportNVIC_SYSTICK_CTRL_REG = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE_BIT );\r\n\r\n\t\t\t/* Re-enable interrupts - see comments above the cpsid instruction()\r\n\t\t\tabove. */\r\n\t\t\t__asm volatile( \"cpsie i\" );\r\n\r\n\t\t\tif( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r\n\t\t\t{\r\n\t\t\t\tuint32_t ulCalculatedLoadValue;\r\n\r\n\t\t\t\t/* The tick interrupt has already executed, and the SysTick\r\n\t\t\t\tcount reloaded with ulReloadValue.  Reset the\r\n\t\t\t\tportNVIC_SYSTICK_LOAD_REG with whatever remains of this tick\r\n\t\t\t\tperiod. */\r\n\t\t\t\tulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\r\n\r\n\t\t\t\t/* Don't allow a tiny value, or values that have somehow\r\n\t\t\t\tunderflowed because the post sleep hook did something\r\n\t\t\t\tthat took too long. */\r\n\t\t\t\tif( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\r\n\t\t\t\t{\r\n\t\t\t\t\tulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\r\n\t\t\t\t}\r\n\r\n\t\t\t\tportNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\r\n\r\n\t\t\t\t/* The tick interrupt handler will already have pended the tick\r\n\t\t\t\tprocessing in the kernel.  As the pending tick will be\r\n\t\t\t\tprocessed as soon as this function exits, the tick value\r\n\t\t\t\tmaintained by the tick is stepped forward by one less than the\r\n\t\t\t\ttime spent waiting. */\r\n\t\t\t\tulCompleteTickPeriods = xExpectedIdleTime - 1UL;\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\t/* Something other than the tick interrupt ended the sleep.\r\n\t\t\t\tWork out how long the sleep lasted rounded to complete tick\r\n\t\t\t\tperiods (not the ulReload value which accounted for part\r\n\t\t\t\tticks). */\r\n\t\t\t\tulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;\r\n\r\n\t\t\t\t/* How many complete tick periods passed while the processor\r\n\t\t\t\twas waiting? */\r\n\t\t\t\tulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\r\n\r\n\t\t\t\t/* The reload value is set to whatever fraction of a single tick\r\n\t\t\t\tperiod remains. */\r\n\t\t\t\tportNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\r\n\t\t\t}\r\n\r\n\t\t\t/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG\r\n\t\t\tagain, then set portNVIC_SYSTICK_LOAD_REG back to its standard\r\n\t\t\tvalue.  The critical section is used to ensure the tick interrupt\r\n\t\t\tcan only execute once in the case that the reload register is near\r\n\t\t\tzero. */\r\n\t\t\tportNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r\n\t\t\tportENTER_CRITICAL();\r\n\t\t\t{\r\n\t\t\t\tportNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r\n\t\t\t\tvTaskStepTick( ulCompleteTickPeriods );\r\n\t\t\t\tportNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r\n\t\t\t}\r\n\t\t\tportEXIT_CRITICAL();\r\n\t\t}\r\n\t}\r\n\r\n#endif /* #if configUSE_TICKLESS_IDLE */\r\n/*-----------------------------------------------------------*/\r\n\r\n/*\r\n * Setup the systick timer to generate the tick interrupts at the required\r\n * frequency.\r\n */\r\n__attribute__(( weak )) void vPortSetupTimerInterrupt( void )\r\n{\r\n\t/* Calculate the constants required to configure the tick interrupt. */\r\n\t#if configUSE_TICKLESS_IDLE == 1\r\n\t{\r\n\t\tulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\r\n\t\txMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\r\n\t\tulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\r\n\t}\r\n\t#endif /* configUSE_TICKLESS_IDLE */\r\n\r\n\t/* Configure SysTick to interrupt at the requested rate. */\r\n\tportNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r\n\tportNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\n/* This is a naked function. */\r\nstatic void vPortEnableVFP( void )\r\n{\r\n\t__asm volatile\r\n\t(\r\n\t\t\"\tldr.w r0, =0xE000ED88\t\t\\n\" /* The FPU enable bits are in the CPACR. */\r\n\t\t\"\tldr r1, [r0]\t\t\t\t\\n\"\r\n\t\t\"\t\t\t\t\t\t\t\t\\n\"\r\n\t\t\"\torr r1, r1, #( 0xf << 20 )\t\\n\" /* Enable CP10 and CP11 coprocessors, then save back. */\r\n\t\t\"\tstr r1, [r0]\t\t\t\t\\n\"\r\n\t\t\"\tbx r14\t\t\t\t\t\t\"\r\n\t);\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\n#if( configASSERT_DEFINED == 1 )\r\n\r\n\tvoid vPortValidateInterruptPriority( void )\r\n\t{\r\n\tuint32_t ulCurrentInterrupt;\r\n\tuint8_t ucCurrentPriority;\r\n\r\n\t\t/* Obtain the number of the currently executing interrupt. */\r\n\t\t__asm volatile( \"mrs %0, ipsr\" : \"=r\"( ulCurrentInterrupt ) );\r\n\r\n\t\t/* Is the interrupt number a user defined interrupt? */\r\n\t\tif( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r\n\t\t{\r\n\t\t\t/* Look up the interrupt's priority. */\r\n\t\t\tucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r\n\r\n\t\t\t/* The following assertion will fail if a service routine (ISR) for\r\n\t\t\tan interrupt that has been assigned a priority above\r\n\t\t\tconfigMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r\n\t\t\tfunction.  ISR safe FreeRTOS API functions must *only* be called\r\n\t\t\tfrom interrupts that have been assigned a priority at or below\r\n\t\t\tconfigMAX_SYSCALL_INTERRUPT_PRIORITY.\r\n\r\n\t\t\tNumerically low interrupt priority numbers represent logically high\r\n\t\t\tinterrupt priorities, therefore the priority of the interrupt must\r\n\t\t\tbe set to a value equal to or numerically *higher* than\r\n\t\t\tconfigMAX_SYSCALL_INTERRUPT_PRIORITY.\r\n\r\n\t\t\tInterrupts that\tuse the FreeRTOS API must not be left at their\r\n\t\t\tdefault priority of\tzero as that is the highest possible priority,\r\n\t\t\twhich is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\r\n\t\t\tand\ttherefore also guaranteed to be invalid.\r\n\r\n\t\t\tFreeRTOS maintains separate thread and ISR API functions to ensure\r\n\t\t\tinterrupt entry is as fast and simple as possible.\r\n\r\n\t\t\tThe following links provide detailed information:\r\n\t\t\thttp://www.freertos.org/RTOS-Cortex-M3-M4.html\r\n\t\t\thttp://www.freertos.org/FAQHelp.html */\r\n\t\t\tconfigASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r\n\t\t}\r\n\r\n\t\t/* Priority grouping:  The interrupt controller (NVIC) allows the bits\r\n\t\tthat define each interrupt's priority to be split between bits that\r\n\t\tdefine the interrupt's pre-emption priority bits and bits that define\r\n\t\tthe interrupt's sub-priority.  For simplicity all bits must be defined\r\n\t\tto be pre-emption priority bits.  The following assertion will fail if\r\n\t\tthis is not the case (if some bits represent a sub-priority).\r\n\r\n\t\tIf the application only uses CMSIS libraries for interrupt\r\n\t\tconfiguration then the correct setting can be achieved on all Cortex-M\r\n\t\tdevices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r\n\t\tscheduler.  Note however that some vendor specific peripheral libraries\r\n\t\tassume a non-zero priority group setting, in which cases using a value\r\n\t\tof zero will result in unpredicable behaviour. */\r\n\t\tconfigASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\r\n\t}\r\n\r\n#endif /* configASSERT_DEFINED */\r\n\r\n\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RTOS/src/portable.h",
    "content": "/*\r\n    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r\n    All rights reserved\r\n\r\n    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r\n\r\n    This file is part of the FreeRTOS distribution.\r\n\r\n    FreeRTOS is free software; you can redistribute it and/or modify it under\r\n    the terms of the GNU General Public License (version 2) as published by the\r\n    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r\n\r\n    ***************************************************************************\r\n    >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r\n    >>!   distribute a combined work that includes FreeRTOS without being   !<<\r\n    >>!   obliged to provide the source code for proprietary components     !<<\r\n    >>!   outside of the FreeRTOS kernel.                                   !<<\r\n    ***************************************************************************\r\n\r\n    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r\n    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r\n    FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r\n    link: http://www.freertos.org/a00114.html\r\n\r\n    ***************************************************************************\r\n     *                                                                       *\r\n     *    FreeRTOS provides completely free yet professionally developed,    *\r\n     *    robust, strictly quality controlled, supported, and cross          *\r\n     *    platform software that is more than just the market leader, it     *\r\n     *    is the industry's de facto standard.                               *\r\n     *                                                                       *\r\n     *    Help yourself get started quickly while simultaneously helping     *\r\n     *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r\n     *    tutorial book, reference manual, or both:                          *\r\n     *    http://www.FreeRTOS.org/Documentation                              *\r\n     *                                                                       *\r\n    ***************************************************************************\r\n\r\n    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r\n    the FAQ page \"My application does not run, what could be wrong?\".  Have you\r\n    defined configASSERT()?\r\n\r\n    http://www.FreeRTOS.org/support - In return for receiving this top quality\r\n    embedded software for free we request you assist our global community by\r\n    participating in the support forum.\r\n\r\n    http://www.FreeRTOS.org/training - Investing in training allows your team to\r\n    be as productive as possible as early as possible.  Now you can receive\r\n    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r\n    Ltd, and the world's leading authority on the world's leading RTOS.\r\n\r\n    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r\n    including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r\n    compatible FAT file system, and our tiny thread aware UDP/IP stack.\r\n\r\n    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r\n    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r\n\r\n    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r\n    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r\n    licenses offer ticketed support, indemnification and commercial middleware.\r\n\r\n    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r\n    engineered and independently SIL3 certified version for use in safety and\r\n    mission critical applications that require provable dependability.\r\n\r\n    1 tab == 4 spaces!\r\n*/\r\n\r\n/*-----------------------------------------------------------\r\n * Portable layer API.  Each function must be defined for each port.\r\n *----------------------------------------------------------*/\r\n\r\n#ifndef PORTABLE_H\r\n#define PORTABLE_H\r\n\r\n/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a\r\npre-processor definition was used to ensure the pre-processor found the correct\r\nportmacro.h file for the port being used.  That scheme was deprecated in favour\r\nof setting the compiler's include path such that it found the correct\r\nportmacro.h file - removing the need for the constant and allowing the\r\nportmacro.h file to be located anywhere in relation to the port being used.\r\nPurely for reasons of backward compatibility the old method is still valid, but\r\nto make it clear that new projects should not use it, support for the port\r\nspecific constants has been moved into the deprecated_definitions.h header\r\nfile. */\r\n#include \"deprecated_definitions.h\"\r\n\r\n/* If portENTER_CRITICAL is not defined then including deprecated_definitions.h\r\ndid not result in a portmacro.h header file being included - and it should be\r\nincluded here.  In this case the path to the correct portmacro.h header file\r\nmust be set in the compiler's include path. */\r\n#ifndef portENTER_CRITICAL\r\n\t#include \"portmacro.h\"\r\n#endif\r\n\r\n#if portBYTE_ALIGNMENT == 8\r\n\t#define portBYTE_ALIGNMENT_MASK ( 0x0007 )\r\n#endif\r\n\r\n#if portBYTE_ALIGNMENT == 4\r\n\t#define portBYTE_ALIGNMENT_MASK\t( 0x0003 )\r\n#endif\r\n\r\n#if portBYTE_ALIGNMENT == 2\r\n\t#define portBYTE_ALIGNMENT_MASK\t( 0x0001 )\r\n#endif\r\n\r\n#if portBYTE_ALIGNMENT == 1\r\n\t#define portBYTE_ALIGNMENT_MASK\t( 0x0000 )\r\n#endif\r\n\r\n#ifndef portBYTE_ALIGNMENT_MASK\r\n\t#error \"Invalid portBYTE_ALIGNMENT definition\"\r\n#endif\r\n\r\n#ifndef portNUM_CONFIGURABLE_REGIONS\r\n\t#define portNUM_CONFIGURABLE_REGIONS 1\r\n#endif\r\n\r\n#ifdef __cplusplus\r\nextern \"C\" {\r\n#endif\r\n\r\n#include \"mpu_wrappers.h\"\r\n\r\n/*\r\n * Setup the stack of a new task so it is ready to be placed under the\r\n * scheduler control.  The registers have to be placed on the stack in\r\n * the order that the port expects to find them.\r\n *\r\n */\r\n#if( portUSING_MPU_WRAPPERS == 1 )\r\n\tStackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;\r\n#else\r\n\tStackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;\r\n#endif\r\n\r\n/* Used by heap_5.c. */\r\ntypedef struct HeapRegion\r\n{\r\n\tuint8_t *pucStartAddress;\r\n\tsize_t xSizeInBytes;\r\n} HeapRegion_t;\r\n\r\n/*\r\n * Used to define multiple heap regions for use by heap_5.c.  This function\r\n * must be called before any calls to pvPortMalloc() - not creating a task,\r\n * queue, semaphore, mutex, software timer, event group, etc. will result in\r\n * pvPortMalloc being called.\r\n *\r\n * pxHeapRegions passes in an array of HeapRegion_t structures - each of which\r\n * defines a region of memory that can be used as the heap.  The array is\r\n * terminated by a HeapRegions_t structure that has a size of 0.  The region\r\n * with the lowest start address must appear first in the array.\r\n */\r\nvoid vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions );\r\n\r\n\r\n/*\r\n * Map to the memory management routines required for the port.\r\n */\r\nvoid *pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION;\r\nvoid vPortFree( void *pv ) PRIVILEGED_FUNCTION;\r\nvoid vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION;\r\nsize_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION;\r\nsize_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * Setup the hardware ready for the scheduler to take control.  This generally\r\n * sets up a tick interrupt and sets timers for the correct tick frequency.\r\n */\r\nBaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so\r\n * the hardware is left in its original condition after the scheduler stops\r\n * executing.\r\n */\r\nvoid vPortEndScheduler( void ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * The structures and methods of manipulating the MPU are contained within the\r\n * port layer.\r\n *\r\n * Fills the xMPUSettings structure with the memory region information\r\n * contained in xRegions.\r\n */\r\n#if( portUSING_MPU_WRAPPERS == 1 )\r\n\tstruct xMEMORY_REGION;\r\n\tvoid vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint16_t usStackDepth ) PRIVILEGED_FUNCTION;\r\n#endif\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* PORTABLE_H */\r\n\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RTOS/src/portmacro.h",
    "content": "/*\r\n    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r\n    All rights reserved\r\n\r\n    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r\n\r\n    This file is part of the FreeRTOS distribution.\r\n\r\n    FreeRTOS is free software; you can redistribute it and/or modify it under\r\n    the terms of the GNU General Public License (version 2) as published by the\r\n    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r\n\r\n    ***************************************************************************\r\n    >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r\n    >>!   distribute a combined work that includes FreeRTOS without being   !<<\r\n    >>!   obliged to provide the source code for proprietary components     !<<\r\n    >>!   outside of the FreeRTOS kernel.                                   !<<\r\n    ***************************************************************************\r\n\r\n    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r\n    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r\n    FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r\n    link: http://www.freertos.org/a00114.html\r\n\r\n    ***************************************************************************\r\n     *                                                                       *\r\n     *    FreeRTOS provides completely free yet professionally developed,    *\r\n     *    robust, strictly quality controlled, supported, and cross          *\r\n     *    platform software that is more than just the market leader, it     *\r\n     *    is the industry's de facto standard.                               *\r\n     *                                                                       *\r\n     *    Help yourself get started quickly while simultaneously helping     *\r\n     *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r\n     *    tutorial book, reference manual, or both:                          *\r\n     *    http://www.FreeRTOS.org/Documentation                              *\r\n     *                                                                       *\r\n    ***************************************************************************\r\n\r\n    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r\n    the FAQ page \"My application does not run, what could be wrong?\".  Have you\r\n    defined configASSERT()?\r\n\r\n    http://www.FreeRTOS.org/support - In return for receiving this top quality\r\n    embedded software for free we request you assist our global community by\r\n    participating in the support forum.\r\n\r\n    http://www.FreeRTOS.org/training - Investing in training allows your team to\r\n    be as productive as possible as early as possible.  Now you can receive\r\n    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r\n    Ltd, and the world's leading authority on the world's leading RTOS.\r\n\r\n    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r\n    including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r\n    compatible FAT file system, and our tiny thread aware UDP/IP stack.\r\n\r\n    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r\n    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r\n\r\n    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r\n    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r\n    licenses offer ticketed support, indemnification and commercial middleware.\r\n\r\n    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r\n    engineered and independently SIL3 certified version for use in safety and\r\n    mission critical applications that require provable dependability.\r\n\r\n    1 tab == 4 spaces!\r\n*/\r\n\r\n\r\n#ifndef PORTMACRO_H\r\n#define PORTMACRO_H\r\n\r\n#ifdef __cplusplus\r\nextern \"C\" {\r\n#endif\r\n\r\n/*-----------------------------------------------------------\r\n * Port specific definitions.\r\n *\r\n * The settings in this file configure FreeRTOS correctly for the\r\n * given hardware and compiler.\r\n *\r\n * These settings should not be altered.\r\n *-----------------------------------------------------------\r\n */\r\n\r\n/* Type definitions. */\r\n#define portCHAR\t\tchar\r\n#define portFLOAT\t\tfloat\r\n#define portDOUBLE\t\tdouble\r\n#define portLONG\t\tlong\r\n#define portSHORT\t\tshort\r\n#define portSTACK_TYPE\tuint32_t\r\n#define portBASE_TYPE\tlong\r\n\r\ntypedef portSTACK_TYPE StackType_t;\r\ntypedef long BaseType_t;\r\ntypedef unsigned long UBaseType_t;\r\n\r\n#if( configUSE_16_BIT_TICKS == 1 )\r\n\ttypedef uint16_t TickType_t;\r\n\t#define portMAX_DELAY ( TickType_t ) 0xffff\r\n#else\r\n\ttypedef uint32_t TickType_t;\r\n\t#define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r\n\r\n\t/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r\n\tnot need to be guarded with a critical section. */\r\n\t#define portTICK_TYPE_IS_ATOMIC 1\r\n#endif\r\n/*-----------------------------------------------------------*/\r\n\r\n/* Architecture specifics. */\r\n#define portSTACK_GROWTH\t\t\t( -1 )\r\n#define portTICK_PERIOD_MS\t\t\t( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r\n#define portBYTE_ALIGNMENT\t\t\t8\r\n/*-----------------------------------------------------------*/\r\n\r\n/* Scheduler utilities. */\r\n#define portYIELD() \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t/* Set a PendSV to request a context switch. */\t\t\t\t\t\t\t\t\\\r\n\tportNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\t\t\t\t\t\t\t\t\\\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t/* Barriers are normally not required but do ensure the code is completely\t\\\r\n\twithin the specified behaviour for the architecture. */\t\t\t\t\t\t\\\r\n\t__asm volatile( \"dsb\" );\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t__asm volatile( \"isb\" );\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n}\r\n\r\n#define portNVIC_INT_CTRL_REG\t\t( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r\n#define portNVIC_PENDSVSET_BIT\t\t( 1UL << 28UL )\r\n#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()\r\n#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r\n/*-----------------------------------------------------------*/\r\n\r\n/* Critical section management. */\r\nextern void vPortEnterCritical( void );\r\nextern void vPortExitCritical( void );\r\n#define portSET_INTERRUPT_MASK_FROM_ISR()\t\tulPortRaiseBASEPRI()\r\n#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)\tvPortSetBASEPRI(x)\r\n#define portDISABLE_INTERRUPTS()\t\t\t\tvPortRaiseBASEPRI()\r\n#define portENABLE_INTERRUPTS()\t\t\t\t\tvPortSetBASEPRI(0)\r\n#define portENTER_CRITICAL()\t\t\t\t\tvPortEnterCritical()\r\n#define portEXIT_CRITICAL()\t\t\t\t\t\tvPortExitCritical()\r\n\r\n/*-----------------------------------------------------------*/\r\n\r\n/* Task function macros as described on the FreeRTOS.org WEB site.  These are\r\nnot necessary for to use this port.  They are defined so the common demo files\r\n(which build with all the ports) will build. */\r\n#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r\n#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r\n/*-----------------------------------------------------------*/\r\n\r\n/* Tickless idle/low power functionality. */\r\n#ifndef portSUPPRESS_TICKS_AND_SLEEP\r\n\textern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\r\n\t#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )\r\n#endif\r\n/*-----------------------------------------------------------*/\r\n\r\n/* Architecture specific optimisations. */\r\n#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\r\n\t#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1\r\n#endif\r\n\r\n#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\r\n\r\n\t/* Generic helper function. */\r\n\t__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )\r\n\t{\r\n\tuint8_t ucReturn;\r\n\r\n\t\t__asm volatile ( \"clz %0, %1\" : \"=r\" ( ucReturn ) : \"r\" ( ulBitmap ) );\r\n\t\treturn ucReturn;\r\n\t}\r\n\r\n\t/* Check the configuration. */\r\n\t#if( configMAX_PRIORITIES > 32 )\r\n\t\t#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\r\n\t#endif\r\n\r\n\t/* Store/clear the ready priorities in a bit map. */\r\n\t#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\r\n\t#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\r\n\r\n\t/*-----------------------------------------------------------*/\r\n\r\n\t#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )\r\n\r\n#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\r\n\r\n/*-----------------------------------------------------------*/\r\n\r\n#ifdef configASSERT\r\n\tvoid vPortValidateInterruptPriority( void );\r\n\t#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() \tvPortValidateInterruptPriority()\r\n#endif\r\n\r\n/* portNOP() is not required by this port. */\r\n#define portNOP()\r\n\r\n#ifndef portFORCE_INLINE\r\n\t#define portFORCE_INLINE inline __attribute__(( always_inline))\r\n#endif\r\n\r\n/*-----------------------------------------------------------*/\r\n\r\nportFORCE_INLINE static void vPortRaiseBASEPRI( void )\r\n{\r\nuint32_t ulNewBASEPRI;\r\n\r\n\t__asm volatile\r\n\t(\r\n\t\t\"\tmov %0, %1\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\t\\\r\n\t\t\"\tcpsid i\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\" \\\r\n\t\t\"\tmsr basepri, %0\t\t\t\t\t\t\t\t\t\t\t\\n\" \\\r\n\t\t\"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\" \\\r\n\t\t\"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\" \\\r\n\t\t\"\tcpsie i\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\" \\\r\n\t\t:\"=r\" (ulNewBASEPRI) : \"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\r\n\t);\r\n}\r\n\r\n/*-----------------------------------------------------------*/\r\n\r\nportFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )\r\n{\r\nuint32_t ulOriginalBASEPRI, ulNewBASEPRI;\r\n\r\n\t__asm volatile\r\n\t(\r\n\t\t\"\tmrs %0, basepri\t\t\t\t\t\t\t\t\t\t\t\\n\" \\\r\n\t\t\"\tmov %1, %2\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\t\\\r\n\t\t\"\tcpsid i\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\" \\\r\n\t\t\"\tmsr basepri, %1\t\t\t\t\t\t\t\t\t\t\t\\n\" \\\r\n\t\t\"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\" \\\r\n\t\t\"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\" \\\r\n\t\t\"\tcpsie i\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\" \\\r\n\t\t:\"=r\" (ulOriginalBASEPRI), \"=r\" (ulNewBASEPRI) : \"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\r\n\t);\r\n\r\n\t/* This return will not be reached but is necessary to prevent compiler\r\n\twarnings. */\r\n\treturn ulOriginalBASEPRI;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nportFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )\r\n{\r\n\t__asm volatile\r\n\t(\r\n\t\t\"\tmsr basepri, %0\t\" :: \"r\" ( ulNewMaskValue )\r\n\t);\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* PORTMACRO_H */\r\n\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RTOS/src/projdefs.h",
    "content": "/*\r\n    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r\n    All rights reserved\r\n\r\n    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r\n\r\n    This file is part of the FreeRTOS distribution.\r\n\r\n    FreeRTOS is free software; you can redistribute it and/or modify it under\r\n    the terms of the GNU General Public License (version 2) as published by the\r\n    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r\n\r\n    ***************************************************************************\r\n    >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r\n    >>!   distribute a combined work that includes FreeRTOS without being   !<<\r\n    >>!   obliged to provide the source code for proprietary components     !<<\r\n    >>!   outside of the FreeRTOS kernel.                                   !<<\r\n    ***************************************************************************\r\n\r\n    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r\n    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r\n    FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r\n    link: http://www.freertos.org/a00114.html\r\n\r\n    ***************************************************************************\r\n     *                                                                       *\r\n     *    FreeRTOS provides completely free yet professionally developed,    *\r\n     *    robust, strictly quality controlled, supported, and cross          *\r\n     *    platform software that is more than just the market leader, it     *\r\n     *    is the industry's de facto standard.                               *\r\n     *                                                                       *\r\n     *    Help yourself get started quickly while simultaneously helping     *\r\n     *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r\n     *    tutorial book, reference manual, or both:                          *\r\n     *    http://www.FreeRTOS.org/Documentation                              *\r\n     *                                                                       *\r\n    ***************************************************************************\r\n\r\n    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r\n    the FAQ page \"My application does not run, what could be wrong?\".  Have you\r\n    defined configASSERT()?\r\n\r\n    http://www.FreeRTOS.org/support - In return for receiving this top quality\r\n    embedded software for free we request you assist our global community by\r\n    participating in the support forum.\r\n\r\n    http://www.FreeRTOS.org/training - Investing in training allows your team to\r\n    be as productive as possible as early as possible.  Now you can receive\r\n    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r\n    Ltd, and the world's leading authority on the world's leading RTOS.\r\n\r\n    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r\n    including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r\n    compatible FAT file system, and our tiny thread aware UDP/IP stack.\r\n\r\n    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r\n    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r\n\r\n    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r\n    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r\n    licenses offer ticketed support, indemnification and commercial middleware.\r\n\r\n    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r\n    engineered and independently SIL3 certified version for use in safety and\r\n    mission critical applications that require provable dependability.\r\n\r\n    1 tab == 4 spaces!\r\n*/\r\n\r\n#ifndef PROJDEFS_H\r\n#define PROJDEFS_H\r\n\r\n/*\r\n * Defines the prototype to which task functions must conform.  Defined in this\r\n * file to ensure the type is known before portable.h is included.\r\n */\r\ntypedef void (*TaskFunction_t)( void * );\r\n\r\n/* Converts a time in milliseconds to a time in ticks. */\r\n#define pdMS_TO_TICKS( xTimeInMs ) ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000 ) )\r\n\r\n#define pdFALSE\t\t\t( ( BaseType_t ) 0 )\r\n#define pdTRUE\t\t\t( ( BaseType_t ) 1 )\r\n\r\n#define pdPASS\t\t\t( pdTRUE )\r\n#define pdFAIL\t\t\t( pdFALSE )\r\n#define errQUEUE_EMPTY\t( ( BaseType_t ) 0 )\r\n#define errQUEUE_FULL\t( ( BaseType_t ) 0 )\r\n\r\n/* FreeRTOS error definitions. */\r\n#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY\t( -1 )\r\n#define errQUEUE_BLOCKED\t\t\t\t\t\t( -4 )\r\n#define errQUEUE_YIELD\t\t\t\t\t\t\t( -5 )\r\n\r\n/* Macros used for basic data corruption checks. */\r\n#ifndef configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES\r\n\t#define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES 0\r\n#endif\r\n\r\n#if( configUSE_16_BIT_TICKS == 1 )\r\n\t#define pdINTEGRITY_CHECK_VALUE 0x5a5a\r\n#else\r\n\t#define pdINTEGRITY_CHECK_VALUE 0x5a5a5a5aUL\r\n#endif\r\n\r\n/* The following endian values are used by FreeRTOS+ components, not FreeRTOS\r\nitself. */\r\n#define pdFREERTOS_LITTLE_ENDIAN\t0\r\n#define pdFREERTOS_BIG_ENDIAN\t\t1\r\n\r\n#endif /* PROJDEFS_H */\r\n\r\n\r\n\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RTOS/src/queue.c",
    "content": "/*\r\n    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r\n    All rights reserved\r\n\r\n    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r\n\r\n    This file is part of the FreeRTOS distribution.\r\n\r\n    FreeRTOS is free software; you can redistribute it and/or modify it under\r\n    the terms of the GNU General Public License (version 2) as published by the\r\n    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r\n\r\n    ***************************************************************************\r\n    >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r\n    >>!   distribute a combined work that includes FreeRTOS without being   !<<\r\n    >>!   obliged to provide the source code for proprietary components     !<<\r\n    >>!   outside of the FreeRTOS kernel.                                   !<<\r\n    ***************************************************************************\r\n\r\n    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r\n    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r\n    FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r\n    link: http://www.freertos.org/a00114.html\r\n\r\n    ***************************************************************************\r\n     *                                                                       *\r\n     *    FreeRTOS provides completely free yet professionally developed,    *\r\n     *    robust, strictly quality controlled, supported, and cross          *\r\n     *    platform software that is more than just the market leader, it     *\r\n     *    is the industry's de facto standard.                               *\r\n     *                                                                       *\r\n     *    Help yourself get started quickly while simultaneously helping     *\r\n     *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r\n     *    tutorial book, reference manual, or both:                          *\r\n     *    http://www.FreeRTOS.org/Documentation                              *\r\n     *                                                                       *\r\n    ***************************************************************************\r\n\r\n    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r\n    the FAQ page \"My application does not run, what could be wrong?\".  Have you\r\n    defined configASSERT()?\r\n\r\n    http://www.FreeRTOS.org/support - In return for receiving this top quality\r\n    embedded software for free we request you assist our global community by\r\n    participating in the support forum.\r\n\r\n    http://www.FreeRTOS.org/training - Investing in training allows your team to\r\n    be as productive as possible as early as possible.  Now you can receive\r\n    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r\n    Ltd, and the world's leading authority on the world's leading RTOS.\r\n\r\n    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r\n    including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r\n    compatible FAT file system, and our tiny thread aware UDP/IP stack.\r\n\r\n    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r\n    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r\n\r\n    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r\n    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r\n    licenses offer ticketed support, indemnification and commercial middleware.\r\n\r\n    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r\n    engineered and independently SIL3 certified version for use in safety and\r\n    mission critical applications that require provable dependability.\r\n\r\n    1 tab == 4 spaces!\r\n*/\r\n\r\n#include <stdlib.h>\r\n#include <string.h>\r\n\r\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r\nall the API functions to use the MPU wrappers.  That should only be done when\r\ntask.h is included from an application file. */\r\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r\n\r\n#include \"FreeRTOS.h\"\r\n#include \"task.h\"\r\n#include \"queue.h\"\r\n\r\n#if ( configUSE_CO_ROUTINES == 1 )\r\n\t#include \"croutine.h\"\r\n#endif\r\n\r\n/* Lint e961 and e750 are suppressed as a MISRA exception justified because the\r\nMPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the\r\nheader files above, but not in this file, in order to generate the correct\r\nprivileged Vs unprivileged linkage and placement. */\r\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */\r\n\r\n\r\n/* Constants used with the xRxLock and xTxLock structure members. */\r\n#define queueUNLOCKED\t\t\t\t\t( ( BaseType_t ) -1 )\r\n#define queueLOCKED_UNMODIFIED\t\t\t( ( BaseType_t ) 0 )\r\n\r\n/* When the Queue_t structure is used to represent a base queue its pcHead and\r\npcTail members are used as pointers into the queue storage area.  When the\r\nQueue_t structure is used to represent a mutex pcHead and pcTail pointers are\r\nnot necessary, and the pcHead pointer is set to NULL to indicate that the\r\npcTail pointer actually points to the mutex holder (if any).  Map alternative\r\nnames to the pcHead and pcTail structure members to ensure the readability of\r\nthe code is maintained despite this dual use of two structure members.  An\r\nalternative implementation would be to use a union, but use of a union is\r\nagainst the coding standard (although an exception to the standard has been\r\npermitted where the dual use also significantly changes the type of the\r\nstructure member). */\r\n#define pxMutexHolder\t\t\t\t\tpcTail\r\n#define uxQueueType\t\t\t\t\t\tpcHead\r\n#define queueQUEUE_IS_MUTEX\t\t\t\tNULL\r\n\r\n/* Semaphores do not actually store or copy data, so have an item size of\r\nzero. */\r\n#define queueSEMAPHORE_QUEUE_ITEM_LENGTH ( ( UBaseType_t ) 0 )\r\n#define queueMUTEX_GIVE_BLOCK_TIME\t\t ( ( TickType_t ) 0U )\r\n\r\n#if( configUSE_PREEMPTION == 0 )\r\n\t/* If the cooperative scheduler is being used then a yield should not be\r\n\tperformed just because a higher priority task has been woken. */\r\n\t#define queueYIELD_IF_USING_PREEMPTION()\r\n#else\r\n\t#define queueYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()\r\n#endif\r\n\r\n/*\r\n * Definition of the queue used by the scheduler.\r\n * Items are queued by copy, not reference.  See the following link for the\r\n * rationale: http://www.freertos.org/Embedded-RTOS-Queues.html\r\n */\r\ntypedef struct QueueDefinition\r\n{\r\n\tint8_t *pcHead;\t\t\t\t\t/*< Points to the beginning of the queue storage area. */\r\n\tint8_t *pcTail;\t\t\t\t\t/*< Points to the byte at the end of the queue storage area.  Once more byte is allocated than necessary to store the queue items, this is used as a marker. */\r\n\tint8_t *pcWriteTo;\t\t\t\t/*< Points to the free next place in the storage area. */\r\n\r\n\tunion\t\t\t\t\t\t\t/* Use of a union is an exception to the coding standard to ensure two mutually exclusive structure members don't appear simultaneously (wasting RAM). */\r\n\t{\r\n\t\tint8_t *pcReadFrom;\t\t\t/*< Points to the last place that a queued item was read from when the structure is used as a queue. */\r\n\t\tUBaseType_t uxRecursiveCallCount;/*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */\r\n\t} u;\r\n\r\n\tList_t xTasksWaitingToSend;\t\t/*< List of tasks that are blocked waiting to post onto this queue.  Stored in priority order. */\r\n\tList_t xTasksWaitingToReceive;\t/*< List of tasks that are blocked waiting to read from this queue.  Stored in priority order. */\r\n\r\n\tvolatile UBaseType_t uxMessagesWaiting;/*< The number of items currently in the queue. */\r\n\tUBaseType_t uxLength;\t\t\t/*< The length of the queue defined as the number of items it will hold, not the number of bytes. */\r\n\tUBaseType_t uxItemSize;\t\t\t/*< The size of each items that the queue will hold. */\r\n\r\n\tvolatile BaseType_t xRxLock;\t/*< Stores the number of items received from the queue (removed from the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */\r\n\tvolatile BaseType_t xTxLock;\t/*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */\r\n\r\n\t#if ( configUSE_TRACE_FACILITY == 1 )\r\n\t\tUBaseType_t uxQueueNumber;\r\n\t\tuint8_t ucQueueType;\r\n\t#endif\r\n\r\n\t#if ( configUSE_QUEUE_SETS == 1 )\r\n\t\tstruct QueueDefinition *pxQueueSetContainer;\r\n\t#endif\r\n\r\n} xQUEUE;\r\n\r\n/* The old xQUEUE name is maintained above then typedefed to the new Queue_t\r\nname below to enable the use of older kernel aware debuggers. */\r\ntypedef xQUEUE Queue_t;\r\n\r\n/*-----------------------------------------------------------*/\r\n\r\n/*\r\n * The queue registry is just a means for kernel aware debuggers to locate\r\n * queue structures.  It has no other purpose so is an optional component.\r\n */\r\n#if ( configQUEUE_REGISTRY_SIZE > 0 )\r\n\r\n\t/* The type stored within the queue registry array.  This allows a name\r\n\tto be assigned to each queue making kernel aware debugging a little\r\n\tmore user friendly. */\r\n\ttypedef struct QUEUE_REGISTRY_ITEM\r\n\t{\r\n\t\tconst char *pcQueueName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\r\n\t\tQueueHandle_t xHandle;\r\n\t} xQueueRegistryItem;\r\n\r\n\t/* The old xQueueRegistryItem name is maintained above then typedefed to the\r\n\tnew xQueueRegistryItem name below to enable the use of older kernel aware\r\n\tdebuggers. */\r\n\ttypedef xQueueRegistryItem QueueRegistryItem_t;\r\n\r\n\t/* The queue registry is simply an array of QueueRegistryItem_t structures.\r\n\tThe pcQueueName member of a structure being NULL is indicative of the\r\n\tarray position being vacant. */\r\n\tQueueRegistryItem_t xQueueRegistry[ configQUEUE_REGISTRY_SIZE ];\r\n\r\n#endif /* configQUEUE_REGISTRY_SIZE */\r\n\r\n/*\r\n * Unlocks a queue locked by a call to prvLockQueue.  Locking a queue does not\r\n * prevent an ISR from adding or removing items to the queue, but does prevent\r\n * an ISR from removing tasks from the queue event lists.  If an ISR finds a\r\n * queue is locked it will instead increment the appropriate queue lock count\r\n * to indicate that a task may require unblocking.  When the queue in unlocked\r\n * these lock counts are inspected, and the appropriate action taken.\r\n */\r\nstatic void prvUnlockQueue( Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * Uses a critical section to determine if there is any data in a queue.\r\n *\r\n * @return pdTRUE if the queue contains no items, otherwise pdFALSE.\r\n */\r\nstatic BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * Uses a critical section to determine if there is any space in a queue.\r\n *\r\n * @return pdTRUE if there is no space, otherwise pdFALSE;\r\n */\r\nstatic BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * Copies an item into the queue, either at the front of the queue or the\r\n * back of the queue.\r\n */\r\nstatic BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * Copies an item out of a queue.\r\n */\r\nstatic void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;\r\n\r\n#if ( configUSE_QUEUE_SETS == 1 )\r\n\t/*\r\n\t * Checks to see if a queue is a member of a queue set, and if so, notifies\r\n\t * the queue set that the queue contains data.\r\n\t */\r\n\tstatic BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;\r\n#endif\r\n\r\n/*-----------------------------------------------------------*/\r\n\r\n/*\r\n * Macro to mark a queue as locked.  Locking a queue prevents an ISR from\r\n * accessing the queue event lists.\r\n */\r\n#define prvLockQueue( pxQueue )\t\t\t\t\t\t\t\t\\\r\n\ttaskENTER_CRITICAL();\t\t\t\t\t\t\t\t\t\\\r\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\tif( ( pxQueue )->xRxLock == queueUNLOCKED )\t\t\t\\\r\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t\t( pxQueue )->xRxLock = queueLOCKED_UNMODIFIED;\t\\\r\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\tif( ( pxQueue )->xTxLock == queueUNLOCKED )\t\t\t\\\r\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t\t( pxQueue )->xTxLock = queueLOCKED_UNMODIFIED;\t\\\r\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\ttaskEXIT_CRITICAL()\r\n/*-----------------------------------------------------------*/\r\n\r\nBaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )\r\n{\r\nQueue_t * const pxQueue = ( Queue_t * ) xQueue;\r\n\r\n\tconfigASSERT( pxQueue );\r\n\r\n\ttaskENTER_CRITICAL();\r\n\t{\r\n\t\tpxQueue->pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize );\r\n\t\tpxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;\r\n\t\tpxQueue->pcWriteTo = pxQueue->pcHead;\r\n\t\tpxQueue->u.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - ( UBaseType_t ) 1U ) * pxQueue->uxItemSize );\r\n\t\tpxQueue->xRxLock = queueUNLOCKED;\r\n\t\tpxQueue->xTxLock = queueUNLOCKED;\r\n\r\n\t\tif( xNewQueue == pdFALSE )\r\n\t\t{\r\n\t\t\t/* If there are tasks blocked waiting to read from the queue, then\r\n\t\t\tthe tasks will remain blocked as after this function exits the queue\r\n\t\t\twill still be empty.  If there are tasks blocked waiting to write to\r\n\t\t\tthe queue, then one should be unblocked as after this function exits\r\n\t\t\tit will be possible to write to it. */\r\n\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\r\n\t\t\t{\r\n\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) == pdTRUE )\r\n\t\t\t\t{\r\n\t\t\t\t\tqueueYIELD_IF_USING_PREEMPTION();\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\t/* Ensure the event queues start in the correct state. */\r\n\t\t\tvListInitialise( &( pxQueue->xTasksWaitingToSend ) );\r\n\t\t\tvListInitialise( &( pxQueue->xTasksWaitingToReceive ) );\r\n\t\t}\r\n\t}\r\n\ttaskEXIT_CRITICAL();\r\n\r\n\t/* A value is returned for calling semantic consistency with previous\r\n\tversions. */\r\n\treturn pdPASS;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nQueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType )\r\n{\r\nQueue_t *pxNewQueue;\r\nsize_t xQueueSizeInBytes;\r\nQueueHandle_t xReturn = NULL;\r\nint8_t *pcAllocatedBuffer;\r\n\r\n\t/* Remove compiler warnings about unused parameters should\r\n\tconfigUSE_TRACE_FACILITY not be set to 1. */\r\n\t( void ) ucQueueType;\r\n\r\n\tconfigASSERT( uxQueueLength > ( UBaseType_t ) 0 );\r\n\r\n\tif( uxItemSize == ( UBaseType_t ) 0 )\r\n\t{\r\n\t\t/* There is not going to be a queue storage area. */\r\n\t\txQueueSizeInBytes = ( size_t ) 0;\r\n\t}\r\n\telse\r\n\t{\r\n\t\t/* The queue is one byte longer than asked for to make wrap checking\r\n\t\teasier/faster. */\r\n\t\txQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ) + ( size_t ) 1; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\r\n\t}\r\n\r\n\t/* Allocate the new queue structure and storage area. */\r\n\tpcAllocatedBuffer = ( int8_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes );\r\n\r\n\tif( pcAllocatedBuffer != NULL )\r\n\t{\r\n\t\tpxNewQueue = ( Queue_t * ) pcAllocatedBuffer; /*lint !e826 MISRA The buffer cannot be too small because it was dimensioned by sizeof( Queue_t ) + xQueueSizeInBytes. */\r\n\r\n\t\tif( uxItemSize == ( UBaseType_t ) 0 )\r\n\t\t{\r\n\t\t\t/* No RAM was allocated for the queue storage area, but PC head\r\n\t\t\tcannot be set to NULL because NULL is used as a key to say the queue\r\n\t\t\tis used as a mutex.  Therefore just set pcHead to point to the queue\r\n\t\t\tas a benign value that is known to be within the memory map. */\r\n\t\t\tpxNewQueue->pcHead = ( int8_t * ) pxNewQueue;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\t/* Jump past the queue structure to find the location of the queue\r\n\t\t\tstorage area - adding the padding bytes to get a better alignment. */\r\n\t\t\tpxNewQueue->pcHead = pcAllocatedBuffer + sizeof( Queue_t );\r\n\t\t}\r\n\r\n\t\t/* Initialise the queue members as described above where the queue type\r\n\t\tis defined. */\r\n\t\tpxNewQueue->uxLength = uxQueueLength;\r\n\t\tpxNewQueue->uxItemSize = uxItemSize;\r\n\t\t( void ) xQueueGenericReset( pxNewQueue, pdTRUE );\r\n\r\n\t\t#if ( configUSE_TRACE_FACILITY == 1 )\r\n\t\t{\r\n\t\t\tpxNewQueue->ucQueueType = ucQueueType;\r\n\t\t}\r\n\t\t#endif /* configUSE_TRACE_FACILITY */\r\n\r\n\t\t#if( configUSE_QUEUE_SETS == 1 )\r\n\t\t{\r\n\t\t\tpxNewQueue->pxQueueSetContainer = NULL;\r\n\t\t}\r\n\t\t#endif /* configUSE_QUEUE_SETS */\r\n\r\n\t\ttraceQUEUE_CREATE( pxNewQueue );\r\n\t\txReturn = pxNewQueue;\r\n\t}\r\n\telse\r\n\t{\r\n\t\tmtCOVERAGE_TEST_MARKER();\r\n\t}\r\n\r\n\tconfigASSERT( xReturn );\r\n\r\n\treturn xReturn;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( configUSE_MUTEXES == 1 )\r\n\r\n\tQueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )\r\n\t{\r\n\tQueue_t *pxNewQueue;\r\n\r\n\t\t/* Prevent compiler warnings about unused parameters if\r\n\t\tconfigUSE_TRACE_FACILITY does not equal 1. */\r\n\t\t( void ) ucQueueType;\r\n\r\n\t\t/* Allocate the new queue structure. */\r\n\t\tpxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) );\r\n\t\tif( pxNewQueue != NULL )\r\n\t\t{\r\n\t\t\t/* Information required for priority inheritance. */\r\n\t\t\tpxNewQueue->pxMutexHolder = NULL;\r\n\t\t\tpxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;\r\n\r\n\t\t\t/* Queues used as a mutex no data is actually copied into or out\r\n\t\t\tof the queue. */\r\n\t\t\tpxNewQueue->pcWriteTo = NULL;\r\n\t\t\tpxNewQueue->u.pcReadFrom = NULL;\r\n\r\n\t\t\t/* Each mutex has a length of 1 (like a binary semaphore) and\r\n\t\t\tan item size of 0 as nothing is actually copied into or out\r\n\t\t\tof the mutex. */\r\n\t\t\tpxNewQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;\r\n\t\t\tpxNewQueue->uxLength = ( UBaseType_t ) 1U;\r\n\t\t\tpxNewQueue->uxItemSize = ( UBaseType_t ) 0U;\r\n\t\t\tpxNewQueue->xRxLock = queueUNLOCKED;\r\n\t\t\tpxNewQueue->xTxLock = queueUNLOCKED;\r\n\r\n\t\t\t#if ( configUSE_TRACE_FACILITY == 1 )\r\n\t\t\t{\r\n\t\t\t\tpxNewQueue->ucQueueType = ucQueueType;\r\n\t\t\t}\r\n\t\t\t#endif\r\n\r\n\t\t\t#if ( configUSE_QUEUE_SETS == 1 )\r\n\t\t\t{\r\n\t\t\t\tpxNewQueue->pxQueueSetContainer = NULL;\r\n\t\t\t}\r\n\t\t\t#endif\r\n\r\n\t\t\t/* Ensure the event queues start with the correct state. */\r\n\t\t\tvListInitialise( &( pxNewQueue->xTasksWaitingToSend ) );\r\n\t\t\tvListInitialise( &( pxNewQueue->xTasksWaitingToReceive ) );\r\n\r\n\t\t\ttraceCREATE_MUTEX( pxNewQueue );\r\n\r\n\t\t\t/* Start with the semaphore in the expected state. */\r\n\t\t\t( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\ttraceCREATE_MUTEX_FAILED();\r\n\t\t}\r\n\r\n\t\tconfigASSERT( pxNewQueue );\r\n\t\treturn pxNewQueue;\r\n\t}\r\n\r\n#endif /* configUSE_MUTEXES */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )\r\n\r\n\tvoid* xQueueGetMutexHolder( QueueHandle_t xSemaphore )\r\n\t{\r\n\tvoid *pxReturn;\r\n\r\n\t\t/* This function is called by xSemaphoreGetMutexHolder(), and should not\r\n\t\tbe called directly.  Note:  This is a good way of determining if the\r\n\t\tcalling task is the mutex holder, but not a good way of determining the\r\n\t\tidentity of the mutex holder, as the holder may change between the\r\n\t\tfollowing critical section exiting and the function returning. */\r\n\t\ttaskENTER_CRITICAL();\r\n\t\t{\r\n\t\t\tif( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX )\r\n\t\t\t{\r\n\t\t\t\tpxReturn = ( void * ) ( ( Queue_t * ) xSemaphore )->pxMutexHolder;\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tpxReturn = NULL;\r\n\t\t\t}\r\n\t\t}\r\n\t\ttaskEXIT_CRITICAL();\r\n\r\n\t\treturn pxReturn;\r\n\t} /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */\r\n\r\n#endif\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( configUSE_RECURSIVE_MUTEXES == 1 )\r\n\r\n\tBaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex )\r\n\t{\r\n\tBaseType_t xReturn;\r\n\tQueue_t * const pxMutex = ( Queue_t * ) xMutex;\r\n\r\n\t\tconfigASSERT( pxMutex );\r\n\r\n\t\t/* If this is the task that holds the mutex then pxMutexHolder will not\r\n\t\tchange outside of this task.  If this task does not hold the mutex then\r\n\t\tpxMutexHolder can never coincidentally equal the tasks handle, and as\r\n\t\tthis is the only condition we are interested in it does not matter if\r\n\t\tpxMutexHolder is accessed simultaneously by another task.  Therefore no\r\n\t\tmutual exclusion is required to test the pxMutexHolder variable. */\r\n\t\tif( pxMutex->pxMutexHolder == ( void * ) xTaskGetCurrentTaskHandle() ) /*lint !e961 Not a redundant cast as TaskHandle_t is a typedef. */\r\n\t\t{\r\n\t\t\ttraceGIVE_MUTEX_RECURSIVE( pxMutex );\r\n\r\n\t\t\t/* uxRecursiveCallCount cannot be zero if pxMutexHolder is equal to\r\n\t\t\tthe task handle, therefore no underflow check is required.  Also,\r\n\t\t\tuxRecursiveCallCount is only modified by the mutex holder, and as\r\n\t\t\tthere can only be one, no mutual exclusion is required to modify the\r\n\t\t\tuxRecursiveCallCount member. */\r\n\t\t\t( pxMutex->u.uxRecursiveCallCount )--;\r\n\r\n\t\t\t/* Have we unwound the call count? */\r\n\t\t\tif( pxMutex->u.uxRecursiveCallCount == ( UBaseType_t ) 0 )\r\n\t\t\t{\r\n\t\t\t\t/* Return the mutex.  This will automatically unblock any other\r\n\t\t\t\ttask that might be waiting to access the mutex. */\r\n\t\t\t\t( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK );\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\r\n\t\t\txReturn = pdPASS;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\t/* The mutex cannot be given because the calling task is not the\r\n\t\t\tholder. */\r\n\t\t\txReturn = pdFAIL;\r\n\r\n\t\t\ttraceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );\r\n\t\t}\r\n\r\n\t\treturn xReturn;\r\n\t}\r\n\r\n#endif /* configUSE_RECURSIVE_MUTEXES */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( configUSE_RECURSIVE_MUTEXES == 1 )\r\n\r\n\tBaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait )\r\n\t{\r\n\tBaseType_t xReturn;\r\n\tQueue_t * const pxMutex = ( Queue_t * ) xMutex;\r\n\r\n\t\tconfigASSERT( pxMutex );\r\n\r\n\t\t/* Comments regarding mutual exclusion as per those within\r\n\t\txQueueGiveMutexRecursive(). */\r\n\r\n\t\ttraceTAKE_MUTEX_RECURSIVE( pxMutex );\r\n\r\n\t\tif( pxMutex->pxMutexHolder == ( void * ) xTaskGetCurrentTaskHandle() ) /*lint !e961 Cast is not redundant as TaskHandle_t is a typedef. */\r\n\t\t{\r\n\t\t\t( pxMutex->u.uxRecursiveCallCount )++;\r\n\t\t\txReturn = pdPASS;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\txReturn = xQueueGenericReceive( pxMutex, NULL, xTicksToWait, pdFALSE );\r\n\r\n\t\t\t/* pdPASS will only be returned if the mutex was successfully\r\n\t\t\tobtained.  The calling task may have entered the Blocked state\r\n\t\t\tbefore reaching here. */\r\n\t\t\tif( xReturn == pdPASS )\r\n\t\t\t{\r\n\t\t\t\t( pxMutex->u.uxRecursiveCallCount )++;\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\ttraceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex );\r\n\t\t\t}\r\n\t\t}\r\n\r\n\t\treturn xReturn;\r\n\t}\r\n\r\n#endif /* configUSE_RECURSIVE_MUTEXES */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( configUSE_COUNTING_SEMAPHORES == 1 )\r\n\r\n\tQueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount )\r\n\t{\r\n\tQueueHandle_t xHandle;\r\n\r\n\t\tconfigASSERT( uxMaxCount != 0 );\r\n\t\tconfigASSERT( uxInitialCount <= uxMaxCount );\r\n\r\n\t\txHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );\r\n\r\n\t\tif( xHandle != NULL )\r\n\t\t{\r\n\t\t\t( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;\r\n\r\n\t\t\ttraceCREATE_COUNTING_SEMAPHORE();\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\ttraceCREATE_COUNTING_SEMAPHORE_FAILED();\r\n\t\t}\r\n\r\n\t\tconfigASSERT( xHandle );\r\n\t\treturn xHandle;\r\n\t}\r\n\r\n#endif /* configUSE_COUNTING_SEMAPHORES */\r\n/*-----------------------------------------------------------*/\r\n\r\nBaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )\r\n{\r\nBaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;\r\nTimeOut_t xTimeOut;\r\nQueue_t * const pxQueue = ( Queue_t * ) xQueue;\r\n\r\n\tconfigASSERT( pxQueue );\r\n\tconfigASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );\r\n\tconfigASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );\r\n\t#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\r\n\t{\r\n\t\tconfigASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );\r\n\t}\r\n\t#endif\r\n\r\n\r\n\t/* This function relaxes the coding standard somewhat to allow return\r\n\tstatements within the function itself.  This is done in the interest\r\n\tof execution time efficiency. */\r\n\tfor( ;; )\r\n\t{\r\n\t\ttaskENTER_CRITICAL();\r\n\t\t{\r\n\t\t\t/* Is there room on the queue now?  The running task must be the\r\n\t\t\thighest priority task wanting to access the queue.  If the head item\r\n\t\t\tin the queue is to be overwritten then it does not matter if the\r\n\t\t\tqueue is full. */\r\n\t\t\tif( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )\r\n\t\t\t{\r\n\t\t\t\ttraceQUEUE_SEND( pxQueue );\r\n\t\t\t\txYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );\r\n\r\n\t\t\t\t#if ( configUSE_QUEUE_SETS == 1 )\r\n\t\t\t\t{\r\n\t\t\t\t\tif( pxQueue->pxQueueSetContainer != NULL )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tif( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) == pdTRUE )\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t/* The queue is a member of a queue set, and posting\r\n\t\t\t\t\t\t\tto the queue set caused a higher priority task to\r\n\t\t\t\t\t\t\tunblock. A context switch is required. */\r\n\t\t\t\t\t\t\tqueueYIELD_IF_USING_PREEMPTION();\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\telse\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t/* If there was a task waiting for data to arrive on the\r\n\t\t\t\t\t\tqueue then unblock it now. */\r\n\t\t\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) == pdTRUE )\r\n\t\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t\t/* The unblocked task has a priority higher than\r\n\t\t\t\t\t\t\t\tour own so yield immediately.  Yes it is ok to\r\n\t\t\t\t\t\t\t\tdo this from within the critical section - the\r\n\t\t\t\t\t\t\t\tkernel takes care of that. */\r\n\t\t\t\t\t\t\t\tqueueYIELD_IF_USING_PREEMPTION();\r\n\t\t\t\t\t\t\t}\r\n\t\t\t\t\t\t\telse\r\n\t\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t\t\t}\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\telse if( xYieldRequired != pdFALSE )\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t/* This path is a special case that will only get\r\n\t\t\t\t\t\t\texecuted if the task was holding multiple mutexes\r\n\t\t\t\t\t\t\tand the mutexes were given back in an order that is\r\n\t\t\t\t\t\t\tdifferent to that in which they were taken. */\r\n\t\t\t\t\t\t\tqueueYIELD_IF_USING_PREEMPTION();\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\telse\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t\t#else /* configUSE_QUEUE_SETS */\r\n\t\t\t\t{\r\n\t\t\t\t\t/* If there was a task waiting for data to arrive on the\r\n\t\t\t\t\tqueue then unblock it now. */\r\n\t\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) == pdTRUE )\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t/* The unblocked task has a priority higher than\r\n\t\t\t\t\t\t\tour own so yield immediately.  Yes it is ok to do\r\n\t\t\t\t\t\t\tthis from within the critical section - the kernel\r\n\t\t\t\t\t\t\ttakes care of that. */\r\n\t\t\t\t\t\t\tqueueYIELD_IF_USING_PREEMPTION();\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\telse\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse if( xYieldRequired != pdFALSE )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t/* This path is a special case that will only get\r\n\t\t\t\t\t\texecuted if the task was holding multiple mutexes and\r\n\t\t\t\t\t\tthe mutexes were given back in an order that is\r\n\t\t\t\t\t\tdifferent to that in which they were taken. */\r\n\t\t\t\t\t\tqueueYIELD_IF_USING_PREEMPTION();\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t\t#endif /* configUSE_QUEUE_SETS */\r\n\r\n\t\t\t\ttaskEXIT_CRITICAL();\r\n\t\t\t\treturn pdPASS;\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tif( xTicksToWait == ( TickType_t ) 0 )\r\n\t\t\t\t{\r\n\t\t\t\t\t/* The queue was full and no block time is specified (or\r\n\t\t\t\t\tthe block time has expired) so leave now. */\r\n\t\t\t\t\ttaskEXIT_CRITICAL();\r\n\r\n\t\t\t\t\t/* Return to the original privilege level before exiting\r\n\t\t\t\t\tthe function. */\r\n\t\t\t\t\ttraceQUEUE_SEND_FAILED( pxQueue );\r\n\t\t\t\t\treturn errQUEUE_FULL;\r\n\t\t\t\t}\r\n\t\t\t\telse if( xEntryTimeSet == pdFALSE )\r\n\t\t\t\t{\r\n\t\t\t\t\t/* The queue was full and a block time was specified so\r\n\t\t\t\t\tconfigure the timeout structure. */\r\n\t\t\t\t\tvTaskSetTimeOutState( &xTimeOut );\r\n\t\t\t\t\txEntryTimeSet = pdTRUE;\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\t/* Entry time was already set. */\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t}\r\n\t\ttaskEXIT_CRITICAL();\r\n\r\n\t\t/* Interrupts and other tasks can send to and receive from the queue\r\n\t\tnow the critical section has been exited. */\r\n\r\n\t\tvTaskSuspendAll();\r\n\t\tprvLockQueue( pxQueue );\r\n\r\n\t\t/* Update the timeout state to see if it has expired yet. */\r\n\t\tif( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )\r\n\t\t{\r\n\t\t\tif( prvIsQueueFull( pxQueue ) != pdFALSE )\r\n\t\t\t{\r\n\t\t\t\ttraceBLOCKING_ON_QUEUE_SEND( pxQueue );\r\n\t\t\t\tvTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );\r\n\r\n\t\t\t\t/* Unlocking the queue means queue events can effect the\r\n\t\t\t\tevent list.  It is possible\tthat interrupts occurring now\r\n\t\t\t\tremove this task from the event\tlist again - but as the\r\n\t\t\t\tscheduler is suspended the task will go onto the pending\r\n\t\t\t\tready last instead of the actual ready list. */\r\n\t\t\t\tprvUnlockQueue( pxQueue );\r\n\r\n\t\t\t\t/* Resuming the scheduler will move tasks from the pending\r\n\t\t\t\tready list into the ready list - so it is feasible that this\r\n\t\t\t\ttask is already in a ready list before it yields - in which\r\n\t\t\t\tcase the yield will not cause a context switch unless there\r\n\t\t\t\tis also a higher priority task in the pending ready list. */\r\n\t\t\t\tif( xTaskResumeAll() == pdFALSE )\r\n\t\t\t\t{\r\n\t\t\t\t\tportYIELD_WITHIN_API();\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\t/* Try again. */\r\n\t\t\t\tprvUnlockQueue( pxQueue );\r\n\t\t\t\t( void ) xTaskResumeAll();\r\n\t\t\t}\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\t/* The timeout has expired. */\r\n\t\t\tprvUnlockQueue( pxQueue );\r\n\t\t\t( void ) xTaskResumeAll();\r\n\r\n\t\t\t/* Return to the original privilege level before exiting the\r\n\t\t\tfunction. */\r\n\t\t\ttraceQUEUE_SEND_FAILED( pxQueue );\r\n\t\t\treturn errQUEUE_FULL;\r\n\t\t}\r\n\t}\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( configUSE_ALTERNATIVE_API == 1 )\r\n\r\n\tBaseType_t xQueueAltGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, BaseType_t xCopyPosition )\r\n\t{\r\n\tBaseType_t xEntryTimeSet = pdFALSE;\r\n\tTimeOut_t xTimeOut;\r\n\tQueue_t * const pxQueue = ( Queue_t * ) xQueue;\r\n\r\n\t\tconfigASSERT( pxQueue );\r\n\t\tconfigASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );\r\n\r\n\t\tfor( ;; )\r\n\t\t{\r\n\t\t\ttaskENTER_CRITICAL();\r\n\t\t\t{\r\n\t\t\t\t/* Is there room on the queue now?  To be running we must be\r\n\t\t\t\tthe highest priority task wanting to access the queue. */\r\n\t\t\t\tif( pxQueue->uxMessagesWaiting < pxQueue->uxLength )\r\n\t\t\t\t{\r\n\t\t\t\t\ttraceQUEUE_SEND( pxQueue );\r\n\t\t\t\t\tprvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );\r\n\r\n\t\t\t\t\t/* If there was a task waiting for data to arrive on the\r\n\t\t\t\t\tqueue then unblock it now. */\r\n\t\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) == pdTRUE )\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t/* The unblocked task has a priority higher than\r\n\t\t\t\t\t\t\tour own so yield immediately. */\r\n\t\t\t\t\t\t\tportYIELD_WITHIN_API();\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\telse\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t}\r\n\r\n\t\t\t\t\ttaskEXIT_CRITICAL();\r\n\t\t\t\t\treturn pdPASS;\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tif( xTicksToWait == ( TickType_t ) 0 )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\ttaskEXIT_CRITICAL();\r\n\t\t\t\t\t\treturn errQUEUE_FULL;\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse if( xEntryTimeSet == pdFALSE )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tvTaskSetTimeOutState( &xTimeOut );\r\n\t\t\t\t\t\txEntryTimeSet = pdTRUE;\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\ttaskEXIT_CRITICAL();\r\n\r\n\t\t\ttaskENTER_CRITICAL();\r\n\t\t\t{\r\n\t\t\t\tif( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )\r\n\t\t\t\t{\r\n\t\t\t\t\tif( prvIsQueueFull( pxQueue ) != pdFALSE )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\ttraceBLOCKING_ON_QUEUE_SEND( pxQueue );\r\n\t\t\t\t\t\tvTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );\r\n\t\t\t\t\t\tportYIELD_WITHIN_API();\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\ttaskEXIT_CRITICAL();\r\n\t\t\t\t\ttraceQUEUE_SEND_FAILED( pxQueue );\r\n\t\t\t\t\treturn errQUEUE_FULL;\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\ttaskEXIT_CRITICAL();\r\n\t\t}\r\n\t}\r\n\r\n#endif /* configUSE_ALTERNATIVE_API */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( configUSE_ALTERNATIVE_API == 1 )\r\n\r\n\tBaseType_t xQueueAltGenericReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait, BaseType_t xJustPeeking )\r\n\t{\r\n\tBaseType_t xEntryTimeSet = pdFALSE;\r\n\tTimeOut_t xTimeOut;\r\n\tint8_t *pcOriginalReadPosition;\r\n\tQueue_t * const pxQueue = ( Queue_t * ) xQueue;\r\n\r\n\t\tconfigASSERT( pxQueue );\r\n\t\tconfigASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );\r\n\r\n\t\tfor( ;; )\r\n\t\t{\r\n\t\t\ttaskENTER_CRITICAL();\r\n\t\t\t{\r\n\t\t\t\tif( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )\r\n\t\t\t\t{\r\n\t\t\t\t\t/* Remember our read position in case we are just peeking. */\r\n\t\t\t\t\tpcOriginalReadPosition = pxQueue->u.pcReadFrom;\r\n\r\n\t\t\t\t\tprvCopyDataFromQueue( pxQueue, pvBuffer );\r\n\r\n\t\t\t\t\tif( xJustPeeking == pdFALSE )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\ttraceQUEUE_RECEIVE( pxQueue );\r\n\r\n\t\t\t\t\t\t/* Data is actually being removed (not just peeked). */\r\n\t\t\t\t\t\t--( pxQueue->uxMessagesWaiting );\r\n\r\n\t\t\t\t\t\t#if ( configUSE_MUTEXES == 1 )\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\tif( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )\r\n\t\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t\t/* Record the information required to implement\r\n\t\t\t\t\t\t\t\tpriority inheritance should it become necessary. */\r\n\t\t\t\t\t\t\t\tpxQueue->pxMutexHolder = ( int8_t * ) xTaskGetCurrentTaskHandle();\r\n\t\t\t\t\t\t\t}\r\n\t\t\t\t\t\t\telse\r\n\t\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t\t\t}\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\t#endif\r\n\r\n\t\t\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) == pdTRUE )\r\n\t\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t\tportYIELD_WITHIN_API();\r\n\t\t\t\t\t\t\t}\r\n\t\t\t\t\t\t\telse\r\n\t\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t\t\t}\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\ttraceQUEUE_PEEK( pxQueue );\r\n\r\n\t\t\t\t\t\t/* The data is not being removed, so reset our read\r\n\t\t\t\t\t\tpointer. */\r\n\t\t\t\t\t\tpxQueue->u.pcReadFrom = pcOriginalReadPosition;\r\n\r\n\t\t\t\t\t\t/* The data is being left in the queue, so see if there are\r\n\t\t\t\t\t\tany other tasks waiting for the data. */\r\n\t\t\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t/* Tasks that are removed from the event list will get added to\r\n\t\t\t\t\t\t\tthe pending ready list as the scheduler is still suspended. */\r\n\t\t\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r\n\t\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t\t/* The task waiting has a higher priority than this task. */\r\n\t\t\t\t\t\t\t\tportYIELD_WITHIN_API();\r\n\t\t\t\t\t\t\t}\r\n\t\t\t\t\t\t\telse\r\n\t\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t\t\t}\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\telse\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t}\r\n\r\n\t\t\t\t\ttaskEXIT_CRITICAL();\r\n\t\t\t\t\treturn pdPASS;\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tif( xTicksToWait == ( TickType_t ) 0 )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\ttaskEXIT_CRITICAL();\r\n\t\t\t\t\t\ttraceQUEUE_RECEIVE_FAILED( pxQueue );\r\n\t\t\t\t\t\treturn errQUEUE_EMPTY;\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse if( xEntryTimeSet == pdFALSE )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tvTaskSetTimeOutState( &xTimeOut );\r\n\t\t\t\t\t\txEntryTimeSet = pdTRUE;\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\ttaskEXIT_CRITICAL();\r\n\r\n\t\t\ttaskENTER_CRITICAL();\r\n\t\t\t{\r\n\t\t\t\tif( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )\r\n\t\t\t\t{\r\n\t\t\t\t\tif( prvIsQueueEmpty( pxQueue ) != pdFALSE )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\ttraceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );\r\n\r\n\t\t\t\t\t\t#if ( configUSE_MUTEXES == 1 )\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\tif( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )\r\n\t\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t\ttaskENTER_CRITICAL();\r\n\t\t\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t\t\tvTaskPriorityInherit( ( void * ) pxQueue->pxMutexHolder );\r\n\t\t\t\t\t\t\t\t}\r\n\t\t\t\t\t\t\t\ttaskEXIT_CRITICAL();\r\n\t\t\t\t\t\t\t}\r\n\t\t\t\t\t\t\telse\r\n\t\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t\t\t}\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\t#endif\r\n\r\n\t\t\t\t\t\tvTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );\r\n\t\t\t\t\t\tportYIELD_WITHIN_API();\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\ttaskEXIT_CRITICAL();\r\n\t\t\t\t\ttraceQUEUE_RECEIVE_FAILED( pxQueue );\r\n\t\t\t\t\treturn errQUEUE_EMPTY;\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\ttaskEXIT_CRITICAL();\r\n\t\t}\r\n\t}\r\n\r\n\r\n#endif /* configUSE_ALTERNATIVE_API */\r\n/*-----------------------------------------------------------*/\r\n\r\nBaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )\r\n{\r\nBaseType_t xReturn;\r\nUBaseType_t uxSavedInterruptStatus;\r\nQueue_t * const pxQueue = ( Queue_t * ) xQueue;\r\n\r\n\tconfigASSERT( pxQueue );\r\n\tconfigASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );\r\n\tconfigASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );\r\n\r\n\t/* RTOS ports that support interrupt nesting have the concept of a maximum\r\n\tsystem call (or maximum API call) interrupt priority.  Interrupts that are\r\n\tabove the maximum system call priority are kept permanently enabled, even\r\n\twhen the RTOS kernel is in a critical section, but cannot make any calls to\r\n\tFreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h\r\n\tthen portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\r\n\tfailure if a FreeRTOS API function is called from an interrupt that has been\r\n\tassigned a priority above the configured maximum system call priority.\r\n\tOnly FreeRTOS functions that end in FromISR can be called from interrupts\r\n\tthat have been assigned a priority at or (logically) below the maximum\r\n\tsystem call\tinterrupt priority.  FreeRTOS maintains a separate interrupt\r\n\tsafe API to ensure interrupt entry is as fast and as simple as possible.\r\n\tMore information (albeit Cortex-M specific) is provided on the following\r\n\tlink: http://www.freertos.org/RTOS-Cortex-M3-M4.html */\r\n\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID();\r\n\r\n\t/* Similar to xQueueGenericSend, except without blocking if there is no room\r\n\tin the queue.  Also don't directly wake a task that was blocked on a queue\r\n\tread, instead return a flag to say whether a context switch is required or\r\n\tnot (i.e. has a task with a higher priority than us been woken by this\r\n\tpost). */\r\n\tuxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\r\n\t{\r\n\t\tif( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )\r\n\t\t{\r\n\t\t\ttraceQUEUE_SEND_FROM_ISR( pxQueue );\r\n\r\n\t\t\t/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a\r\n\t\t\tsemaphore or mutex.  That means prvCopyDataToQueue() cannot result\r\n\t\t\tin a task disinheriting a priority and prvCopyDataToQueue() can be\r\n\t\t\tcalled here even though the disinherit function does not check if\r\n\t\t\tthe scheduler is suspended before accessing the ready lists. */\r\n\t\t\t( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );\r\n\r\n\t\t\t/* The event list is not altered if the queue is locked.  This will\r\n\t\t\tbe done when the queue is unlocked later. */\r\n\t\t\tif( pxQueue->xTxLock == queueUNLOCKED )\r\n\t\t\t{\r\n\t\t\t\t#if ( configUSE_QUEUE_SETS == 1 )\r\n\t\t\t\t{\r\n\t\t\t\t\tif( pxQueue->pxQueueSetContainer != NULL )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tif( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) == pdTRUE )\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t/* The queue is a member of a queue set, and posting\r\n\t\t\t\t\t\t\tto the queue set caused a higher priority task to\r\n\t\t\t\t\t\t\tunblock.  A context switch is required. */\r\n\t\t\t\t\t\t\tif( pxHigherPriorityTaskWoken != NULL )\r\n\t\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t\t*pxHigherPriorityTaskWoken = pdTRUE;\r\n\t\t\t\t\t\t\t}\r\n\t\t\t\t\t\t\telse\r\n\t\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t\t\t}\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\telse\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r\n\t\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t\t/* The task waiting has a higher priority so\r\n\t\t\t\t\t\t\t\trecord that a context switch is required. */\r\n\t\t\t\t\t\t\t\tif( pxHigherPriorityTaskWoken != NULL )\r\n\t\t\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t\t\t*pxHigherPriorityTaskWoken = pdTRUE;\r\n\t\t\t\t\t\t\t\t}\r\n\t\t\t\t\t\t\t\telse\r\n\t\t\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t\t\t\t}\r\n\t\t\t\t\t\t\t}\r\n\t\t\t\t\t\t\telse\r\n\t\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t\t\t}\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\telse\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t\t#else /* configUSE_QUEUE_SETS */\r\n\t\t\t\t{\r\n\t\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t/* The task waiting has a higher priority so record that a\r\n\t\t\t\t\t\t\tcontext\tswitch is required. */\r\n\t\t\t\t\t\t\tif( pxHigherPriorityTaskWoken != NULL )\r\n\t\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t\t*pxHigherPriorityTaskWoken = pdTRUE;\r\n\t\t\t\t\t\t\t}\r\n\t\t\t\t\t\t\telse\r\n\t\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t\t\t}\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\telse\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t\t#endif /* configUSE_QUEUE_SETS */\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\t/* Increment the lock count so the task that unlocks the queue\r\n\t\t\t\tknows that data was posted while it was locked. */\r\n\t\t\t\t++( pxQueue->xTxLock );\r\n\t\t\t}\r\n\r\n\t\t\txReturn = pdPASS;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\ttraceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );\r\n\t\t\txReturn = errQUEUE_FULL;\r\n\t\t}\r\n\t}\r\n\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\r\n\r\n\treturn xReturn;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nBaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken )\r\n{\r\nBaseType_t xReturn;\r\nUBaseType_t uxSavedInterruptStatus;\r\nQueue_t * const pxQueue = ( Queue_t * ) xQueue;\r\n\r\n\t/* Similar to xQueueGenericSendFromISR() but used with semaphores where the\r\n\titem size is 0.  Don't directly wake a task that was blocked on a queue\r\n\tread, instead return a flag to say whether a context switch is required or\r\n\tnot (i.e. has a task with a higher priority than us been woken by this\r\n\tpost). */\r\n\r\n\tconfigASSERT( pxQueue );\r\n\r\n\t/* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR()\r\n\tif the item size is not 0. */\r\n\tconfigASSERT( pxQueue->uxItemSize == 0 );\r\n\r\n\t/* Normally a mutex would not be given from an interrupt, and doing so is\r\n\tdefinitely wrong if there is a mutex holder as priority inheritance makes no\r\n\tsense for an interrupts, only tasks. */\r\n\tconfigASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->pxMutexHolder != NULL ) ) );\r\n\r\n\t/* RTOS ports that support interrupt nesting have the concept of a maximum\r\n\tsystem call (or maximum API call) interrupt priority.  Interrupts that are\r\n\tabove the maximum system call priority are kept permanently enabled, even\r\n\twhen the RTOS kernel is in a critical section, but cannot make any calls to\r\n\tFreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h\r\n\tthen portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\r\n\tfailure if a FreeRTOS API function is called from an interrupt that has been\r\n\tassigned a priority above the configured maximum system call priority.\r\n\tOnly FreeRTOS functions that end in FromISR can be called from interrupts\r\n\tthat have been assigned a priority at or (logically) below the maximum\r\n\tsystem call\tinterrupt priority.  FreeRTOS maintains a separate interrupt\r\n\tsafe API to ensure interrupt entry is as fast and as simple as possible.\r\n\tMore information (albeit Cortex-M specific) is provided on the following\r\n\tlink: http://www.freertos.org/RTOS-Cortex-M3-M4.html */\r\n\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID();\r\n\r\n\tuxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\r\n\t{\r\n\t\t/* When the queue is used to implement a semaphore no data is ever\r\n\t\tmoved through the queue but it is still valid to see if the queue 'has\r\n\t\tspace'. */\r\n\t\tif( pxQueue->uxMessagesWaiting < pxQueue->uxLength )\r\n\t\t{\r\n\t\t\ttraceQUEUE_SEND_FROM_ISR( pxQueue );\r\n\r\n\t\t\t/* A task can only have an inherited priority if it is a mutex\r\n\t\t\tholder - and if there is a mutex holder then the mutex cannot be\r\n\t\t\tgiven from an ISR.  As this is the ISR version of the function it\r\n\t\t\tcan be assumed there is no mutex holder and no need to determine if\r\n\t\t\tpriority disinheritance is needed.  Simply increase the count of\r\n\t\t\tmessages (semaphores) available. */\r\n\t\t\t++( pxQueue->uxMessagesWaiting );\r\n\r\n\t\t\t/* The event list is not altered if the queue is locked.  This will\r\n\t\t\tbe done when the queue is unlocked later. */\r\n\t\t\tif( pxQueue->xTxLock == queueUNLOCKED )\r\n\t\t\t{\r\n\t\t\t\t#if ( configUSE_QUEUE_SETS == 1 )\r\n\t\t\t\t{\r\n\t\t\t\t\tif( pxQueue->pxQueueSetContainer != NULL )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tif( prvNotifyQueueSetContainer( pxQueue, queueSEND_TO_BACK ) == pdTRUE )\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t/* The semaphore is a member of a queue set, and\r\n\t\t\t\t\t\t\tposting\tto the queue set caused a higher priority\r\n\t\t\t\t\t\t\ttask to\tunblock.  A context switch is required. */\r\n\t\t\t\t\t\t\tif( pxHigherPriorityTaskWoken != NULL )\r\n\t\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t\t*pxHigherPriorityTaskWoken = pdTRUE;\r\n\t\t\t\t\t\t\t}\r\n\t\t\t\t\t\t\telse\r\n\t\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t\t\t}\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\telse\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r\n\t\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t\t/* The task waiting has a higher priority so\r\n\t\t\t\t\t\t\t\trecord that a context switch is required. */\r\n\t\t\t\t\t\t\t\tif( pxHigherPriorityTaskWoken != NULL )\r\n\t\t\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t\t\t*pxHigherPriorityTaskWoken = pdTRUE;\r\n\t\t\t\t\t\t\t\t}\r\n\t\t\t\t\t\t\t\telse\r\n\t\t\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t\t\t\t}\r\n\t\t\t\t\t\t\t}\r\n\t\t\t\t\t\t\telse\r\n\t\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t\t\t}\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\telse\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t\t#else /* configUSE_QUEUE_SETS */\r\n\t\t\t\t{\r\n\t\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t/* The task waiting has a higher priority so record that a\r\n\t\t\t\t\t\t\tcontext\tswitch is required. */\r\n\t\t\t\t\t\t\tif( pxHigherPriorityTaskWoken != NULL )\r\n\t\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t\t*pxHigherPriorityTaskWoken = pdTRUE;\r\n\t\t\t\t\t\t\t}\r\n\t\t\t\t\t\t\telse\r\n\t\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t\t\t}\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\telse\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t\t#endif /* configUSE_QUEUE_SETS */\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\t/* Increment the lock count so the task that unlocks the queue\r\n\t\t\t\tknows that data was posted while it was locked. */\r\n\t\t\t\t++( pxQueue->xTxLock );\r\n\t\t\t}\r\n\r\n\t\t\txReturn = pdPASS;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\ttraceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );\r\n\t\t\txReturn = errQUEUE_FULL;\r\n\t\t}\r\n\t}\r\n\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\r\n\r\n\treturn xReturn;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nBaseType_t xQueueGenericReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait, const BaseType_t xJustPeeking )\r\n{\r\nBaseType_t xEntryTimeSet = pdFALSE;\r\nTimeOut_t xTimeOut;\r\nint8_t *pcOriginalReadPosition;\r\nQueue_t * const pxQueue = ( Queue_t * ) xQueue;\r\n\r\n\tconfigASSERT( pxQueue );\r\n\tconfigASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );\r\n\t#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\r\n\t{\r\n\t\tconfigASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );\r\n\t}\r\n\t#endif\r\n\r\n\t/* This function relaxes the coding standard somewhat to allow return\r\n\tstatements within the function itself.  This is done in the interest\r\n\tof execution time efficiency. */\r\n\r\n\tfor( ;; )\r\n\t{\r\n\t\ttaskENTER_CRITICAL();\r\n\t\t{\r\n\t\t\t/* Is there data in the queue now?  To be running the calling task\r\n\t\t\tmust be\tthe highest priority task wanting to access the queue. */\r\n\t\t\tif( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )\r\n\t\t\t{\r\n\t\t\t\t/* Remember the read position in case the queue is only being\r\n\t\t\t\tpeeked. */\r\n\t\t\t\tpcOriginalReadPosition = pxQueue->u.pcReadFrom;\r\n\r\n\t\t\t\tprvCopyDataFromQueue( pxQueue, pvBuffer );\r\n\r\n\t\t\t\tif( xJustPeeking == pdFALSE )\r\n\t\t\t\t{\r\n\t\t\t\t\ttraceQUEUE_RECEIVE( pxQueue );\r\n\r\n\t\t\t\t\t/* Actually removing data, not just peeking. */\r\n\t\t\t\t\t--( pxQueue->uxMessagesWaiting );\r\n\r\n\t\t\t\t\t#if ( configUSE_MUTEXES == 1 )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tif( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t/* Record the information required to implement\r\n\t\t\t\t\t\t\tpriority inheritance should it become necessary. */\r\n\t\t\t\t\t\t\tpxQueue->pxMutexHolder = ( int8_t * ) pvTaskIncrementMutexHeldCount(); /*lint !e961 Cast is not redundant as TaskHandle_t is a typedef. */\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\telse\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t}\r\n\t\t\t\t\t#endif /* configUSE_MUTEXES */\r\n\r\n\t\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) == pdTRUE )\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\tqueueYIELD_IF_USING_PREEMPTION();\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\telse\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\ttraceQUEUE_PEEK( pxQueue );\r\n\r\n\t\t\t\t\t/* The data is not being removed, so reset the read\r\n\t\t\t\t\tpointer. */\r\n\t\t\t\t\tpxQueue->u.pcReadFrom = pcOriginalReadPosition;\r\n\r\n\t\t\t\t\t/* The data is being left in the queue, so see if there are\r\n\t\t\t\t\tany other tasks waiting for the data. */\r\n\t\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t/* The task waiting has a higher priority than this task. */\r\n\t\t\t\t\t\t\tqueueYIELD_IF_USING_PREEMPTION();\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\telse\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\r\n\t\t\t\ttaskEXIT_CRITICAL();\r\n\t\t\t\treturn pdPASS;\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tif( xTicksToWait == ( TickType_t ) 0 )\r\n\t\t\t\t{\r\n\t\t\t\t\t/* The queue was empty and no block time is specified (or\r\n\t\t\t\t\tthe block time has expired) so leave now. */\r\n\t\t\t\t\ttaskEXIT_CRITICAL();\r\n\t\t\t\t\ttraceQUEUE_RECEIVE_FAILED( pxQueue );\r\n\t\t\t\t\treturn errQUEUE_EMPTY;\r\n\t\t\t\t}\r\n\t\t\t\telse if( xEntryTimeSet == pdFALSE )\r\n\t\t\t\t{\r\n\t\t\t\t\t/* The queue was empty and a block time was specified so\r\n\t\t\t\t\tconfigure the timeout structure. */\r\n\t\t\t\t\tvTaskSetTimeOutState( &xTimeOut );\r\n\t\t\t\t\txEntryTimeSet = pdTRUE;\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\t/* Entry time was already set. */\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t}\r\n\t\ttaskEXIT_CRITICAL();\r\n\r\n\t\t/* Interrupts and other tasks can send to and receive from the queue\r\n\t\tnow the critical section has been exited. */\r\n\r\n\t\tvTaskSuspendAll();\r\n\t\tprvLockQueue( pxQueue );\r\n\r\n\t\t/* Update the timeout state to see if it has expired yet. */\r\n\t\tif( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )\r\n\t\t{\r\n\t\t\tif( prvIsQueueEmpty( pxQueue ) != pdFALSE )\r\n\t\t\t{\r\n\t\t\t\ttraceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );\r\n\r\n\t\t\t\t#if ( configUSE_MUTEXES == 1 )\r\n\t\t\t\t{\r\n\t\t\t\t\tif( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\ttaskENTER_CRITICAL();\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\tvTaskPriorityInherit( ( void * ) pxQueue->pxMutexHolder );\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\ttaskEXIT_CRITICAL();\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t\t#endif\r\n\r\n\t\t\t\tvTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );\r\n\t\t\t\tprvUnlockQueue( pxQueue );\r\n\t\t\t\tif( xTaskResumeAll() == pdFALSE )\r\n\t\t\t\t{\r\n\t\t\t\t\tportYIELD_WITHIN_API();\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\t/* Try again. */\r\n\t\t\t\tprvUnlockQueue( pxQueue );\r\n\t\t\t\t( void ) xTaskResumeAll();\r\n\t\t\t}\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tprvUnlockQueue( pxQueue );\r\n\t\t\t( void ) xTaskResumeAll();\r\n\t\t\ttraceQUEUE_RECEIVE_FAILED( pxQueue );\r\n\t\t\treturn errQUEUE_EMPTY;\r\n\t\t}\r\n\t}\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nBaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken )\r\n{\r\nBaseType_t xReturn;\r\nUBaseType_t uxSavedInterruptStatus;\r\nQueue_t * const pxQueue = ( Queue_t * ) xQueue;\r\n\r\n\tconfigASSERT( pxQueue );\r\n\tconfigASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );\r\n\r\n\t/* RTOS ports that support interrupt nesting have the concept of a maximum\r\n\tsystem call (or maximum API call) interrupt priority.  Interrupts that are\r\n\tabove the maximum system call priority are kept permanently enabled, even\r\n\twhen the RTOS kernel is in a critical section, but cannot make any calls to\r\n\tFreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h\r\n\tthen portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\r\n\tfailure if a FreeRTOS API function is called from an interrupt that has been\r\n\tassigned a priority above the configured maximum system call priority.\r\n\tOnly FreeRTOS functions that end in FromISR can be called from interrupts\r\n\tthat have been assigned a priority at or (logically) below the maximum\r\n\tsystem call\tinterrupt priority.  FreeRTOS maintains a separate interrupt\r\n\tsafe API to ensure interrupt entry is as fast and as simple as possible.\r\n\tMore information (albeit Cortex-M specific) is provided on the following\r\n\tlink: http://www.freertos.org/RTOS-Cortex-M3-M4.html */\r\n\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID();\r\n\r\n\tuxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\r\n\t{\r\n\t\t/* Cannot block in an ISR, so check there is data available. */\r\n\t\tif( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )\r\n\t\t{\r\n\t\t\ttraceQUEUE_RECEIVE_FROM_ISR( pxQueue );\r\n\r\n\t\t\tprvCopyDataFromQueue( pxQueue, pvBuffer );\r\n\t\t\t--( pxQueue->uxMessagesWaiting );\r\n\r\n\t\t\t/* If the queue is locked the event list will not be modified.\r\n\t\t\tInstead update the lock count so the task that unlocks the queue\r\n\t\t\twill know that an ISR has removed data while the queue was\r\n\t\t\tlocked. */\r\n\t\t\tif( pxQueue->xRxLock == queueUNLOCKED )\r\n\t\t\t{\r\n\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\r\n\t\t\t\t{\r\n\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t/* The task waiting has a higher priority than us so\r\n\t\t\t\t\t\tforce a context switch. */\r\n\t\t\t\t\t\tif( pxHigherPriorityTaskWoken != NULL )\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t*pxHigherPriorityTaskWoken = pdTRUE;\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\telse\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\t/* Increment the lock count so the task that unlocks the queue\r\n\t\t\t\tknows that data was removed while it was locked. */\r\n\t\t\t\t++( pxQueue->xRxLock );\r\n\t\t\t}\r\n\r\n\t\t\txReturn = pdPASS;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\txReturn = pdFAIL;\r\n\t\t\ttraceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );\r\n\t\t}\r\n\t}\r\n\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\r\n\r\n\treturn xReturn;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nBaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,  void * const pvBuffer )\r\n{\r\nBaseType_t xReturn;\r\nUBaseType_t uxSavedInterruptStatus;\r\nint8_t *pcOriginalReadPosition;\r\nQueue_t * const pxQueue = ( Queue_t * ) xQueue;\r\n\r\n\tconfigASSERT( pxQueue );\r\n\tconfigASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );\r\n\tconfigASSERT( pxQueue->uxItemSize != 0 ); /* Can't peek a semaphore. */\r\n\r\n\t/* RTOS ports that support interrupt nesting have the concept of a maximum\r\n\tsystem call (or maximum API call) interrupt priority.  Interrupts that are\r\n\tabove the maximum system call priority are kept permanently enabled, even\r\n\twhen the RTOS kernel is in a critical section, but cannot make any calls to\r\n\tFreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h\r\n\tthen portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\r\n\tfailure if a FreeRTOS API function is called from an interrupt that has been\r\n\tassigned a priority above the configured maximum system call priority.\r\n\tOnly FreeRTOS functions that end in FromISR can be called from interrupts\r\n\tthat have been assigned a priority at or (logically) below the maximum\r\n\tsystem call\tinterrupt priority.  FreeRTOS maintains a separate interrupt\r\n\tsafe API to ensure interrupt entry is as fast and as simple as possible.\r\n\tMore information (albeit Cortex-M specific) is provided on the following\r\n\tlink: http://www.freertos.org/RTOS-Cortex-M3-M4.html */\r\n\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID();\r\n\r\n\tuxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\r\n\t{\r\n\t\t/* Cannot block in an ISR, so check there is data available. */\r\n\t\tif( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )\r\n\t\t{\r\n\t\t\ttraceQUEUE_PEEK_FROM_ISR( pxQueue );\r\n\r\n\t\t\t/* Remember the read position so it can be reset as nothing is\r\n\t\t\tactually being removed from the queue. */\r\n\t\t\tpcOriginalReadPosition = pxQueue->u.pcReadFrom;\r\n\t\t\tprvCopyDataFromQueue( pxQueue, pvBuffer );\r\n\t\t\tpxQueue->u.pcReadFrom = pcOriginalReadPosition;\r\n\r\n\t\t\txReturn = pdPASS;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\txReturn = pdFAIL;\r\n\t\t\ttraceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue );\r\n\t\t}\r\n\t}\r\n\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\r\n\r\n\treturn xReturn;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nUBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue )\r\n{\r\nUBaseType_t uxReturn;\r\n\r\n\tconfigASSERT( xQueue );\r\n\r\n\ttaskENTER_CRITICAL();\r\n\t{\r\n\t\tuxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;\r\n\t}\r\n\ttaskEXIT_CRITICAL();\r\n\r\n\treturn uxReturn;\r\n} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */\r\n/*-----------------------------------------------------------*/\r\n\r\nUBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )\r\n{\r\nUBaseType_t uxReturn;\r\nQueue_t *pxQueue;\r\n\r\n\tpxQueue = ( Queue_t * ) xQueue;\r\n\tconfigASSERT( pxQueue );\r\n\r\n\ttaskENTER_CRITICAL();\r\n\t{\r\n\t\tuxReturn = pxQueue->uxLength - pxQueue->uxMessagesWaiting;\r\n\t}\r\n\ttaskEXIT_CRITICAL();\r\n\r\n\treturn uxReturn;\r\n} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */\r\n/*-----------------------------------------------------------*/\r\n\r\nUBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )\r\n{\r\nUBaseType_t uxReturn;\r\n\r\n\tconfigASSERT( xQueue );\r\n\r\n\tuxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;\r\n\r\n\treturn uxReturn;\r\n} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */\r\n/*-----------------------------------------------------------*/\r\n\r\nvoid vQueueDelete( QueueHandle_t xQueue )\r\n{\r\nQueue_t * const pxQueue = ( Queue_t * ) xQueue;\r\n\r\n\tconfigASSERT( pxQueue );\r\n\r\n\ttraceQUEUE_DELETE( pxQueue );\r\n\t#if ( configQUEUE_REGISTRY_SIZE > 0 )\r\n\t{\r\n\t\tvQueueUnregisterQueue( pxQueue );\r\n\t}\r\n\t#endif\r\n\tvPortFree( pxQueue );\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( configUSE_TRACE_FACILITY == 1 )\r\n\r\n\tUBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue )\r\n\t{\r\n\t\treturn ( ( Queue_t * ) xQueue )->uxQueueNumber;\r\n\t}\r\n\r\n#endif /* configUSE_TRACE_FACILITY */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( configUSE_TRACE_FACILITY == 1 )\r\n\r\n\tvoid vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber )\r\n\t{\r\n\t\t( ( Queue_t * ) xQueue )->uxQueueNumber = uxQueueNumber;\r\n\t}\r\n\r\n#endif /* configUSE_TRACE_FACILITY */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( configUSE_TRACE_FACILITY == 1 )\r\n\r\n\tuint8_t ucQueueGetQueueType( QueueHandle_t xQueue )\r\n\t{\r\n\t\treturn ( ( Queue_t * ) xQueue )->ucQueueType;\r\n\t}\r\n\r\n#endif /* configUSE_TRACE_FACILITY */\r\n/*-----------------------------------------------------------*/\r\n\r\nstatic BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )\r\n{\r\nBaseType_t xReturn = pdFALSE;\r\n\r\n\tif( pxQueue->uxItemSize == ( UBaseType_t ) 0 )\r\n\t{\r\n\t\t#if ( configUSE_MUTEXES == 1 )\r\n\t\t{\r\n\t\t\tif( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )\r\n\t\t\t{\r\n\t\t\t\t/* The mutex is no longer being held. */\r\n\t\t\t\txReturn = xTaskPriorityDisinherit( ( void * ) pxQueue->pxMutexHolder );\r\n\t\t\t\tpxQueue->pxMutexHolder = NULL;\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\t\t}\r\n\t\t#endif /* configUSE_MUTEXES */\r\n\t}\r\n\telse if( xPosition == queueSEND_TO_BACK )\r\n\t{\r\n\t\t( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. */\r\n\t\tpxQueue->pcWriteTo += pxQueue->uxItemSize;\r\n\t\tif( pxQueue->pcWriteTo >= pxQueue->pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */\r\n\t\t{\r\n\t\t\tpxQueue->pcWriteTo = pxQueue->pcHead;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t}\r\n\t}\r\n\telse\r\n\t{\r\n\t\t( void ) memcpy( ( void * ) pxQueue->u.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\r\n\t\tpxQueue->u.pcReadFrom -= pxQueue->uxItemSize;\r\n\t\tif( pxQueue->u.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */\r\n\t\t{\r\n\t\t\tpxQueue->u.pcReadFrom = ( pxQueue->pcTail - pxQueue->uxItemSize );\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t}\r\n\r\n\t\tif( xPosition == queueOVERWRITE )\r\n\t\t{\r\n\t\t\tif( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )\r\n\t\t\t{\r\n\t\t\t\t/* An item is not being added but overwritten, so subtract\r\n\t\t\t\tone from the recorded number of items in the queue so when\r\n\t\t\t\tone is added again below the number of recorded items remains\r\n\t\t\t\tcorrect. */\r\n\t\t\t\t--( pxQueue->uxMessagesWaiting );\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t}\r\n\t}\r\n\r\n\t++( pxQueue->uxMessagesWaiting );\r\n\r\n\treturn xReturn;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nstatic void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )\r\n{\r\n\tif( pxQueue->uxItemSize != ( UBaseType_t ) 0 )\r\n\t{\r\n\t\tpxQueue->u.pcReadFrom += pxQueue->uxItemSize;\r\n\t\tif( pxQueue->u.pcReadFrom >= pxQueue->pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */\r\n\t\t{\r\n\t\t\tpxQueue->u.pcReadFrom = pxQueue->pcHead;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t}\r\n\t\t( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 MISRA exception as the casts are only redundant for some ports.  Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. */\r\n\t}\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nstatic void prvUnlockQueue( Queue_t * const pxQueue )\r\n{\r\n\t/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */\r\n\r\n\t/* The lock counts contains the number of extra data items placed or\r\n\tremoved from the queue while the queue was locked.  When a queue is\r\n\tlocked items can be added or removed, but the event lists cannot be\r\n\tupdated. */\r\n\ttaskENTER_CRITICAL();\r\n\t{\r\n\t\t/* See if data was added to the queue while it was locked. */\r\n\t\twhile( pxQueue->xTxLock > queueLOCKED_UNMODIFIED )\r\n\t\t{\r\n\t\t\t/* Data was posted while the queue was locked.  Are any tasks\r\n\t\t\tblocked waiting for data to become available? */\r\n\t\t\t#if ( configUSE_QUEUE_SETS == 1 )\r\n\t\t\t{\r\n\t\t\t\tif( pxQueue->pxQueueSetContainer != NULL )\r\n\t\t\t\t{\r\n\t\t\t\t\tif( prvNotifyQueueSetContainer( pxQueue, queueSEND_TO_BACK ) == pdTRUE )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t/* The queue is a member of a queue set, and posting to\r\n\t\t\t\t\t\tthe queue set caused a higher priority task to unblock.\r\n\t\t\t\t\t\tA context switch is required. */\r\n\t\t\t\t\t\tvTaskMissedYield();\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\t/* Tasks that are removed from the event list will get added to\r\n\t\t\t\t\tthe pending ready list as the scheduler is still suspended. */\r\n\t\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t/* The task waiting has a higher priority so record that a\r\n\t\t\t\t\t\t\tcontext\tswitch is required. */\r\n\t\t\t\t\t\t\tvTaskMissedYield();\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\telse\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tbreak;\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\t#else /* configUSE_QUEUE_SETS */\r\n\t\t\t{\r\n\t\t\t\t/* Tasks that are removed from the event list will get added to\r\n\t\t\t\tthe pending ready list as the scheduler is still suspended. */\r\n\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r\n\t\t\t\t{\r\n\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t/* The task waiting has a higher priority so record that a\r\n\t\t\t\t\t\tcontext\tswitch is required. */\r\n\t\t\t\t\t\tvTaskMissedYield();\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tbreak;\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\t#endif /* configUSE_QUEUE_SETS */\r\n\r\n\t\t\t--( pxQueue->xTxLock );\r\n\t\t}\r\n\r\n\t\tpxQueue->xTxLock = queueUNLOCKED;\r\n\t}\r\n\ttaskEXIT_CRITICAL();\r\n\r\n\t/* Do the same for the Rx lock. */\r\n\ttaskENTER_CRITICAL();\r\n\t{\r\n\t\twhile( pxQueue->xRxLock > queueLOCKED_UNMODIFIED )\r\n\t\t{\r\n\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\r\n\t\t\t{\r\n\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\r\n\t\t\t\t{\r\n\t\t\t\t\tvTaskMissedYield();\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\r\n\t\t\t\t--( pxQueue->xRxLock );\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tbreak;\r\n\t\t\t}\r\n\t\t}\r\n\r\n\t\tpxQueue->xRxLock = queueUNLOCKED;\r\n\t}\r\n\ttaskEXIT_CRITICAL();\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nstatic BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )\r\n{\r\nBaseType_t xReturn;\r\n\r\n\ttaskENTER_CRITICAL();\r\n\t{\r\n\t\tif( pxQueue->uxMessagesWaiting == ( UBaseType_t )  0 )\r\n\t\t{\r\n\t\t\txReturn = pdTRUE;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\txReturn = pdFALSE;\r\n\t\t}\r\n\t}\r\n\ttaskEXIT_CRITICAL();\r\n\r\n\treturn xReturn;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nBaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue )\r\n{\r\nBaseType_t xReturn;\r\n\r\n\tconfigASSERT( xQueue );\r\n\tif( ( ( Queue_t * ) xQueue )->uxMessagesWaiting == ( UBaseType_t ) 0 )\r\n\t{\r\n\t\txReturn = pdTRUE;\r\n\t}\r\n\telse\r\n\t{\r\n\t\txReturn = pdFALSE;\r\n\t}\r\n\r\n\treturn xReturn;\r\n} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */\r\n/*-----------------------------------------------------------*/\r\n\r\nstatic BaseType_t prvIsQueueFull( const Queue_t *pxQueue )\r\n{\r\nBaseType_t xReturn;\r\n\r\n\ttaskENTER_CRITICAL();\r\n\t{\r\n\t\tif( pxQueue->uxMessagesWaiting == pxQueue->uxLength )\r\n\t\t{\r\n\t\t\txReturn = pdTRUE;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\txReturn = pdFALSE;\r\n\t\t}\r\n\t}\r\n\ttaskEXIT_CRITICAL();\r\n\r\n\treturn xReturn;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nBaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )\r\n{\r\nBaseType_t xReturn;\r\n\r\n\tconfigASSERT( xQueue );\r\n\tif( ( ( Queue_t * ) xQueue )->uxMessagesWaiting == ( ( Queue_t * ) xQueue )->uxLength )\r\n\t{\r\n\t\txReturn = pdTRUE;\r\n\t}\r\n\telse\r\n\t{\r\n\t\txReturn = pdFALSE;\r\n\t}\r\n\r\n\treturn xReturn;\r\n} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( configUSE_CO_ROUTINES == 1 )\r\n\r\n\tBaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait )\r\n\t{\r\n\tBaseType_t xReturn;\r\n\tQueue_t * const pxQueue = ( Queue_t * ) xQueue;\r\n\r\n\t\t/* If the queue is already full we may have to block.  A critical section\r\n\t\tis required to prevent an interrupt removing something from the queue\r\n\t\tbetween the check to see if the queue is full and blocking on the queue. */\r\n\t\tportDISABLE_INTERRUPTS();\r\n\t\t{\r\n\t\t\tif( prvIsQueueFull( pxQueue ) != pdFALSE )\r\n\t\t\t{\r\n\t\t\t\t/* The queue is full - do we want to block or just leave without\r\n\t\t\t\tposting? */\r\n\t\t\t\tif( xTicksToWait > ( TickType_t ) 0 )\r\n\t\t\t\t{\r\n\t\t\t\t\t/* As this is called from a coroutine we cannot block directly, but\r\n\t\t\t\t\treturn indicating that we need to block. */\r\n\t\t\t\t\tvCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) );\r\n\t\t\t\t\tportENABLE_INTERRUPTS();\r\n\t\t\t\t\treturn errQUEUE_BLOCKED;\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tportENABLE_INTERRUPTS();\r\n\t\t\t\t\treturn errQUEUE_FULL;\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t}\r\n\t\tportENABLE_INTERRUPTS();\r\n\r\n\t\tportDISABLE_INTERRUPTS();\r\n\t\t{\r\n\t\t\tif( pxQueue->uxMessagesWaiting < pxQueue->uxLength )\r\n\t\t\t{\r\n\t\t\t\t/* There is room in the queue, copy the data into the queue. */\r\n\t\t\t\tprvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );\r\n\t\t\t\txReturn = pdPASS;\r\n\r\n\t\t\t\t/* Were any co-routines waiting for data to become available? */\r\n\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r\n\t\t\t\t{\r\n\t\t\t\t\t/* In this instance the co-routine could be placed directly\r\n\t\t\t\t\tinto the ready list as we are within a critical section.\r\n\t\t\t\t\tInstead the same pending ready list mechanism is used as if\r\n\t\t\t\t\tthe event were caused from within an interrupt. */\r\n\t\t\t\t\tif( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t/* The co-routine waiting has a higher priority so record\r\n\t\t\t\t\t\tthat a yield might be appropriate. */\r\n\t\t\t\t\t\txReturn = errQUEUE_YIELD;\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\txReturn = errQUEUE_FULL;\r\n\t\t\t}\r\n\t\t}\r\n\t\tportENABLE_INTERRUPTS();\r\n\r\n\t\treturn xReturn;\r\n\t}\r\n\r\n#endif /* configUSE_CO_ROUTINES */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( configUSE_CO_ROUTINES == 1 )\r\n\r\n\tBaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait )\r\n\t{\r\n\tBaseType_t xReturn;\r\n\tQueue_t * const pxQueue = ( Queue_t * ) xQueue;\r\n\r\n\t\t/* If the queue is already empty we may have to block.  A critical section\r\n\t\tis required to prevent an interrupt adding something to the queue\r\n\t\tbetween the check to see if the queue is empty and blocking on the queue. */\r\n\t\tportDISABLE_INTERRUPTS();\r\n\t\t{\r\n\t\t\tif( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )\r\n\t\t\t{\r\n\t\t\t\t/* There are no messages in the queue, do we want to block or just\r\n\t\t\t\tleave with nothing? */\r\n\t\t\t\tif( xTicksToWait > ( TickType_t ) 0 )\r\n\t\t\t\t{\r\n\t\t\t\t\t/* As this is a co-routine we cannot block directly, but return\r\n\t\t\t\t\tindicating that we need to block. */\r\n\t\t\t\t\tvCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) );\r\n\t\t\t\t\tportENABLE_INTERRUPTS();\r\n\t\t\t\t\treturn errQUEUE_BLOCKED;\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tportENABLE_INTERRUPTS();\r\n\t\t\t\t\treturn errQUEUE_FULL;\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\t\t}\r\n\t\tportENABLE_INTERRUPTS();\r\n\r\n\t\tportDISABLE_INTERRUPTS();\r\n\t\t{\r\n\t\t\tif( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )\r\n\t\t\t{\r\n\t\t\t\t/* Data is available from the queue. */\r\n\t\t\t\tpxQueue->u.pcReadFrom += pxQueue->uxItemSize;\r\n\t\t\t\tif( pxQueue->u.pcReadFrom >= pxQueue->pcTail )\r\n\t\t\t\t{\r\n\t\t\t\t\tpxQueue->u.pcReadFrom = pxQueue->pcHead;\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\t\t\t\t--( pxQueue->uxMessagesWaiting );\r\n\t\t\t\t( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );\r\n\r\n\t\t\t\txReturn = pdPASS;\r\n\r\n\t\t\t\t/* Were any co-routines waiting for space to become available? */\r\n\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\r\n\t\t\t\t{\r\n\t\t\t\t\t/* In this instance the co-routine could be placed directly\r\n\t\t\t\t\tinto the ready list as we are within a critical section.\r\n\t\t\t\t\tInstead the same pending ready list mechanism is used as if\r\n\t\t\t\t\tthe event were caused from within an interrupt. */\r\n\t\t\t\t\tif( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\txReturn = errQUEUE_YIELD;\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\txReturn = pdFAIL;\r\n\t\t\t}\r\n\t\t}\r\n\t\tportENABLE_INTERRUPTS();\r\n\r\n\t\treturn xReturn;\r\n\t}\r\n\r\n#endif /* configUSE_CO_ROUTINES */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( configUSE_CO_ROUTINES == 1 )\r\n\r\n\tBaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken )\r\n\t{\r\n\tQueue_t * const pxQueue = ( Queue_t * ) xQueue;\r\n\r\n\t\t/* Cannot block within an ISR so if there is no space on the queue then\r\n\t\texit without doing anything. */\r\n\t\tif( pxQueue->uxMessagesWaiting < pxQueue->uxLength )\r\n\t\t{\r\n\t\t\tprvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );\r\n\r\n\t\t\t/* We only want to wake one co-routine per ISR, so check that a\r\n\t\t\tco-routine has not already been woken. */\r\n\t\t\tif( xCoRoutinePreviouslyWoken == pdFALSE )\r\n\t\t\t{\r\n\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r\n\t\t\t\t{\r\n\t\t\t\t\tif( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\treturn pdTRUE;\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t}\r\n\r\n\t\treturn xCoRoutinePreviouslyWoken;\r\n\t}\r\n\r\n#endif /* configUSE_CO_ROUTINES */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( configUSE_CO_ROUTINES == 1 )\r\n\r\n\tBaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxCoRoutineWoken )\r\n\t{\r\n\tBaseType_t xReturn;\r\n\tQueue_t * const pxQueue = ( Queue_t * ) xQueue;\r\n\r\n\t\t/* We cannot block from an ISR, so check there is data available. If\r\n\t\tnot then just leave without doing anything. */\r\n\t\tif( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )\r\n\t\t{\r\n\t\t\t/* Copy the data from the queue. */\r\n\t\t\tpxQueue->u.pcReadFrom += pxQueue->uxItemSize;\r\n\t\t\tif( pxQueue->u.pcReadFrom >= pxQueue->pcTail )\r\n\t\t\t{\r\n\t\t\t\tpxQueue->u.pcReadFrom = pxQueue->pcHead;\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\t\t\t--( pxQueue->uxMessagesWaiting );\r\n\t\t\t( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );\r\n\r\n\t\t\tif( ( *pxCoRoutineWoken ) == pdFALSE )\r\n\t\t\t{\r\n\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\r\n\t\t\t\t{\r\n\t\t\t\t\tif( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t*pxCoRoutineWoken = pdTRUE;\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\r\n\t\t\txReturn = pdPASS;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\txReturn = pdFAIL;\r\n\t\t}\r\n\r\n\t\treturn xReturn;\r\n\t}\r\n\r\n#endif /* configUSE_CO_ROUTINES */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( configQUEUE_REGISTRY_SIZE > 0 )\r\n\r\n\tvoid vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\r\n\t{\r\n\tUBaseType_t ux;\r\n\r\n\t\t/* See if there is an empty space in the registry.  A NULL name denotes\r\n\t\ta free slot. */\r\n\t\tfor( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )\r\n\t\t{\r\n\t\t\tif( xQueueRegistry[ ux ].pcQueueName == NULL )\r\n\t\t\t{\r\n\t\t\t\t/* Store the information on this queue. */\r\n\t\t\t\txQueueRegistry[ ux ].pcQueueName = pcQueueName;\r\n\t\t\t\txQueueRegistry[ ux ].xHandle = xQueue;\r\n\r\n\t\t\t\ttraceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );\r\n\t\t\t\tbreak;\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\t\t}\r\n\t}\r\n\r\n#endif /* configQUEUE_REGISTRY_SIZE */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( configQUEUE_REGISTRY_SIZE > 0 )\r\n\r\n\tvoid vQueueUnregisterQueue( QueueHandle_t xQueue )\r\n\t{\r\n\tUBaseType_t ux;\r\n\r\n\t\t/* See if the handle of the queue being unregistered in actually in the\r\n\t\tregistry. */\r\n\t\tfor( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )\r\n\t\t{\r\n\t\t\tif( xQueueRegistry[ ux ].xHandle == xQueue )\r\n\t\t\t{\r\n\t\t\t\t/* Set the name to NULL to show that this slot if free again. */\r\n\t\t\t\txQueueRegistry[ ux ].pcQueueName = NULL;\r\n\t\t\t\tbreak;\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\t\t}\r\n\r\n\t} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */\r\n\r\n#endif /* configQUEUE_REGISTRY_SIZE */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( configUSE_TIMERS == 1 )\r\n\r\n\tvoid vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait )\r\n\t{\r\n\tQueue_t * const pxQueue = ( Queue_t * ) xQueue;\r\n\r\n\t\t/* This function should not be called by application code hence the\r\n\t\t'Restricted' in its name.  It is not part of the public API.  It is\r\n\t\tdesigned for use by kernel code, and has special calling requirements.\r\n\t\tIt can result in vListInsert() being called on a list that can only\r\n\t\tpossibly ever have one item in it, so the list will be fast, but even\r\n\t\tso it should be called with the scheduler locked and not from a critical\r\n\t\tsection. */\r\n\r\n\t\t/* Only do anything if there are no messages in the queue.  This function\r\n\t\twill not actually cause the task to block, just place it on a blocked\r\n\t\tlist.  It will not block until the scheduler is unlocked - at which\r\n\t\ttime a yield will be performed.  If an item is added to the queue while\r\n\t\tthe queue is locked, and the calling task blocks on the queue, then the\r\n\t\tcalling task will be immediately unblocked when the queue is unlocked. */\r\n\t\tprvLockQueue( pxQueue );\r\n\t\tif( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )\r\n\t\t{\r\n\t\t\t/* There is nothing in the queue, block for the specified period. */\r\n\t\t\tvTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t}\r\n\t\tprvUnlockQueue( pxQueue );\r\n\t}\r\n\r\n#endif /* configUSE_TIMERS */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( configUSE_QUEUE_SETS == 1 )\r\n\r\n\tQueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength )\r\n\t{\r\n\tQueueSetHandle_t pxQueue;\r\n\r\n\t\tpxQueue = xQueueGenericCreate( uxEventQueueLength, sizeof( Queue_t * ), queueQUEUE_TYPE_SET );\r\n\r\n\t\treturn pxQueue;\r\n\t}\r\n\r\n#endif /* configUSE_QUEUE_SETS */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( configUSE_QUEUE_SETS == 1 )\r\n\r\n\tBaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )\r\n\t{\r\n\tBaseType_t xReturn;\r\n\r\n\t\ttaskENTER_CRITICAL();\r\n\t\t{\r\n\t\t\tif( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL )\r\n\t\t\t{\r\n\t\t\t\t/* Cannot add a queue/semaphore to more than one queue set. */\r\n\t\t\t\txReturn = pdFAIL;\r\n\t\t\t}\r\n\t\t\telse if( ( ( Queue_t * ) xQueueOrSemaphore )->uxMessagesWaiting != ( UBaseType_t ) 0 )\r\n\t\t\t{\r\n\t\t\t\t/* Cannot add a queue/semaphore to a queue set if there are already\r\n\t\t\t\titems in the queue/semaphore. */\r\n\t\t\t\txReturn = pdFAIL;\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\t( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer = xQueueSet;\r\n\t\t\t\txReturn = pdPASS;\r\n\t\t\t}\r\n\t\t}\r\n\t\ttaskEXIT_CRITICAL();\r\n\r\n\t\treturn xReturn;\r\n\t}\r\n\r\n#endif /* configUSE_QUEUE_SETS */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( configUSE_QUEUE_SETS == 1 )\r\n\r\n\tBaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )\r\n\t{\r\n\tBaseType_t xReturn;\r\n\tQueue_t * const pxQueueOrSemaphore = ( Queue_t * ) xQueueOrSemaphore;\r\n\r\n\t\tif( pxQueueOrSemaphore->pxQueueSetContainer != xQueueSet )\r\n\t\t{\r\n\t\t\t/* The queue was not a member of the set. */\r\n\t\t\txReturn = pdFAIL;\r\n\t\t}\r\n\t\telse if( pxQueueOrSemaphore->uxMessagesWaiting != ( UBaseType_t ) 0 )\r\n\t\t{\r\n\t\t\t/* It is dangerous to remove a queue from a set when the queue is\r\n\t\t\tnot empty because the queue set will still hold pending events for\r\n\t\t\tthe queue. */\r\n\t\t\txReturn = pdFAIL;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\ttaskENTER_CRITICAL();\r\n\t\t\t{\r\n\t\t\t\t/* The queue is no longer contained in the set. */\r\n\t\t\t\tpxQueueOrSemaphore->pxQueueSetContainer = NULL;\r\n\t\t\t}\r\n\t\t\ttaskEXIT_CRITICAL();\r\n\t\t\txReturn = pdPASS;\r\n\t\t}\r\n\r\n\t\treturn xReturn;\r\n\t} /*lint !e818 xQueueSet could not be declared as pointing to const as it is a typedef. */\r\n\r\n#endif /* configUSE_QUEUE_SETS */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( configUSE_QUEUE_SETS == 1 )\r\n\r\n\tQueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t const xTicksToWait )\r\n\t{\r\n\tQueueSetMemberHandle_t xReturn = NULL;\r\n\r\n\t\t( void ) xQueueGenericReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait, pdFALSE ); /*lint !e961 Casting from one typedef to another is not redundant. */\r\n\t\treturn xReturn;\r\n\t}\r\n\r\n#endif /* configUSE_QUEUE_SETS */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( configUSE_QUEUE_SETS == 1 )\r\n\r\n\tQueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet )\r\n\t{\r\n\tQueueSetMemberHandle_t xReturn = NULL;\r\n\r\n\t\t( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL ); /*lint !e961 Casting from one typedef to another is not redundant. */\r\n\t\treturn xReturn;\r\n\t}\r\n\r\n#endif /* configUSE_QUEUE_SETS */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( configUSE_QUEUE_SETS == 1 )\r\n\r\n\tstatic BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, const BaseType_t xCopyPosition )\r\n\t{\r\n\tQueue_t *pxQueueSetContainer = pxQueue->pxQueueSetContainer;\r\n\tBaseType_t xReturn = pdFALSE;\r\n\r\n\t\t/* This function must be called form a critical section. */\r\n\r\n\t\tconfigASSERT( pxQueueSetContainer );\r\n\t\tconfigASSERT( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength );\r\n\r\n\t\tif( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength )\r\n\t\t{\r\n\t\t\ttraceQUEUE_SEND( pxQueueSetContainer );\r\n\r\n\t\t\t/* The data copied is the handle of the queue that contains data. */\r\n\t\t\txReturn = prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, xCopyPosition );\r\n\r\n\t\t\tif( pxQueueSetContainer->xTxLock == queueUNLOCKED )\r\n\t\t\t{\r\n\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) == pdFALSE )\r\n\t\t\t\t{\r\n\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) != pdFALSE )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t/* The task waiting has a higher priority. */\r\n\t\t\t\t\t\txReturn = pdTRUE;\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\t( pxQueueSetContainer->xTxLock )++;\r\n\t\t\t}\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t}\r\n\r\n\t\treturn xReturn;\r\n\t}\r\n\r\n#endif /* configUSE_QUEUE_SETS */\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RTOS/src/queue.h",
    "content": "/*\r\n    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r\n    All rights reserved\r\n\r\n    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r\n\r\n    This file is part of the FreeRTOS distribution.\r\n\r\n    FreeRTOS is free software; you can redistribute it and/or modify it under\r\n    the terms of the GNU General Public License (version 2) as published by the\r\n    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r\n\r\n    ***************************************************************************\r\n    >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r\n    >>!   distribute a combined work that includes FreeRTOS without being   !<<\r\n    >>!   obliged to provide the source code for proprietary components     !<<\r\n    >>!   outside of the FreeRTOS kernel.                                   !<<\r\n    ***************************************************************************\r\n\r\n    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r\n    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r\n    FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r\n    link: http://www.freertos.org/a00114.html\r\n\r\n    ***************************************************************************\r\n     *                                                                       *\r\n     *    FreeRTOS provides completely free yet professionally developed,    *\r\n     *    robust, strictly quality controlled, supported, and cross          *\r\n     *    platform software that is more than just the market leader, it     *\r\n     *    is the industry's de facto standard.                               *\r\n     *                                                                       *\r\n     *    Help yourself get started quickly while simultaneously helping     *\r\n     *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r\n     *    tutorial book, reference manual, or both:                          *\r\n     *    http://www.FreeRTOS.org/Documentation                              *\r\n     *                                                                       *\r\n    ***************************************************************************\r\n\r\n    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r\n    the FAQ page \"My application does not run, what could be wrong?\".  Have you\r\n    defined configASSERT()?\r\n\r\n    http://www.FreeRTOS.org/support - In return for receiving this top quality\r\n    embedded software for free we request you assist our global community by\r\n    participating in the support forum.\r\n\r\n    http://www.FreeRTOS.org/training - Investing in training allows your team to\r\n    be as productive as possible as early as possible.  Now you can receive\r\n    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r\n    Ltd, and the world's leading authority on the world's leading RTOS.\r\n\r\n    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r\n    including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r\n    compatible FAT file system, and our tiny thread aware UDP/IP stack.\r\n\r\n    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r\n    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r\n\r\n    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r\n    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r\n    licenses offer ticketed support, indemnification and commercial middleware.\r\n\r\n    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r\n    engineered and independently SIL3 certified version for use in safety and\r\n    mission critical applications that require provable dependability.\r\n\r\n    1 tab == 4 spaces!\r\n*/\r\n\r\n\r\n#ifndef QUEUE_H\r\n#define QUEUE_H\r\n\r\n#ifndef INC_FREERTOS_H\r\n\t#error \"include FreeRTOS.h\" must appear in source files before \"include queue.h\"\r\n#endif\r\n\r\n#ifdef __cplusplus\r\nextern \"C\" {\r\n#endif\r\n\r\n\r\n/**\r\n * Type by which queues are referenced.  For example, a call to xQueueCreate()\r\n * returns an QueueHandle_t variable that can then be used as a parameter to\r\n * xQueueSend(), xQueueReceive(), etc.\r\n */\r\ntypedef void * QueueHandle_t;\r\n\r\n/**\r\n * Type by which queue sets are referenced.  For example, a call to\r\n * xQueueCreateSet() returns an xQueueSet variable that can then be used as a\r\n * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc.\r\n */\r\ntypedef void * QueueSetHandle_t;\r\n\r\n/**\r\n * Queue sets can contain both queues and semaphores, so the\r\n * QueueSetMemberHandle_t is defined as a type to be used where a parameter or\r\n * return value can be either an QueueHandle_t or an SemaphoreHandle_t.\r\n */\r\ntypedef void * QueueSetMemberHandle_t;\r\n\r\n/* For internal use only. */\r\n#define\tqueueSEND_TO_BACK\t\t( ( BaseType_t ) 0 )\r\n#define\tqueueSEND_TO_FRONT\t\t( ( BaseType_t ) 1 )\r\n#define queueOVERWRITE\t\t\t( ( BaseType_t ) 2 )\r\n\r\n/* For internal use only.  These definitions *must* match those in queue.c. */\r\n#define queueQUEUE_TYPE_BASE\t\t\t\t( ( uint8_t ) 0U )\r\n#define queueQUEUE_TYPE_SET\t\t\t\t\t( ( uint8_t ) 0U )\r\n#define queueQUEUE_TYPE_MUTEX \t\t\t\t( ( uint8_t ) 1U )\r\n#define queueQUEUE_TYPE_COUNTING_SEMAPHORE\t( ( uint8_t ) 2U )\r\n#define queueQUEUE_TYPE_BINARY_SEMAPHORE\t( ( uint8_t ) 3U )\r\n#define queueQUEUE_TYPE_RECURSIVE_MUTEX\t\t( ( uint8_t ) 4U )\r\n\r\n/**\r\n * queue. h\r\n * <pre>\r\n QueueHandle_t xQueueCreate(\r\n\t\t\t\t\t\t\t  UBaseType_t uxQueueLength,\r\n\t\t\t\t\t\t\t  UBaseType_t uxItemSize\r\n\t\t\t\t\t\t  );\r\n * </pre>\r\n *\r\n * Creates a new queue instance.  This allocates the storage required by the\r\n * new queue and returns a handle for the queue.\r\n *\r\n * @param uxQueueLength The maximum number of items that the queue can contain.\r\n *\r\n * @param uxItemSize The number of bytes each item in the queue will require.\r\n * Items are queued by copy, not by reference, so this is the number of bytes\r\n * that will be copied for each posted item.  Each item on the queue must be\r\n * the same size.\r\n *\r\n * @return If the queue is successfully create then a handle to the newly\r\n * created queue is returned.  If the queue cannot be created then 0 is\r\n * returned.\r\n *\r\n * Example usage:\r\n   <pre>\r\n struct AMessage\r\n {\r\n\tchar ucMessageID;\r\n\tchar ucData[ 20 ];\r\n };\r\n\r\n void vATask( void *pvParameters )\r\n {\r\n QueueHandle_t xQueue1, xQueue2;\r\n\r\n\t// Create a queue capable of containing 10 uint32_t values.\r\n\txQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );\r\n\tif( xQueue1 == 0 )\r\n\t{\r\n\t\t// Queue was not created and must not be used.\r\n\t}\r\n\r\n\t// Create a queue capable of containing 10 pointers to AMessage structures.\r\n\t// These should be passed by pointer as they contain a lot of data.\r\n\txQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );\r\n\tif( xQueue2 == 0 )\r\n\t{\r\n\t\t// Queue was not created and must not be used.\r\n\t}\r\n\r\n\t// ... Rest of task code.\r\n }\r\n </pre>\r\n * \\defgroup xQueueCreate xQueueCreate\r\n * \\ingroup QueueManagement\r\n */\r\n#define xQueueCreate( uxQueueLength, uxItemSize ) xQueueGenericCreate( uxQueueLength, uxItemSize, queueQUEUE_TYPE_BASE )\r\n\r\n/**\r\n * queue. h\r\n * <pre>\r\n BaseType_t xQueueSendToToFront(\r\n\t\t\t\t\t\t\t\t   QueueHandle_t\txQueue,\r\n\t\t\t\t\t\t\t\t   const void\t\t*pvItemToQueue,\r\n\t\t\t\t\t\t\t\t   TickType_t\t\txTicksToWait\r\n\t\t\t\t\t\t\t   );\r\n * </pre>\r\n *\r\n * This is a macro that calls xQueueGenericSend().\r\n *\r\n * Post an item to the front of a queue.  The item is queued by copy, not by\r\n * reference.  This function must not be called from an interrupt service\r\n * routine.  See xQueueSendFromISR () for an alternative which may be used\r\n * in an ISR.\r\n *\r\n * @param xQueue The handle to the queue on which the item is to be posted.\r\n *\r\n * @param pvItemToQueue A pointer to the item that is to be placed on the\r\n * queue.  The size of the items the queue will hold was defined when the\r\n * queue was created, so this many bytes will be copied from pvItemToQueue\r\n * into the queue storage area.\r\n *\r\n * @param xTicksToWait The maximum amount of time the task should block\r\n * waiting for space to become available on the queue, should it already\r\n * be full.  The call will return immediately if this is set to 0 and the\r\n * queue is full.  The time is defined in tick periods so the constant\r\n * portTICK_PERIOD_MS should be used to convert to real time if this is required.\r\n *\r\n * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.\r\n *\r\n * Example usage:\r\n   <pre>\r\n struct AMessage\r\n {\r\n\tchar ucMessageID;\r\n\tchar ucData[ 20 ];\r\n } xMessage;\r\n\r\n uint32_t ulVar = 10UL;\r\n\r\n void vATask( void *pvParameters )\r\n {\r\n QueueHandle_t xQueue1, xQueue2;\r\n struct AMessage *pxMessage;\r\n\r\n\t// Create a queue capable of containing 10 uint32_t values.\r\n\txQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );\r\n\r\n\t// Create a queue capable of containing 10 pointers to AMessage structures.\r\n\t// These should be passed by pointer as they contain a lot of data.\r\n\txQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );\r\n\r\n\t// ...\r\n\r\n\tif( xQueue1 != 0 )\r\n\t{\r\n\t\t// Send an uint32_t.  Wait for 10 ticks for space to become\r\n\t\t// available if necessary.\r\n\t\tif( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )\r\n\t\t{\r\n\t\t\t// Failed to post the message, even after 10 ticks.\r\n\t\t}\r\n\t}\r\n\r\n\tif( xQueue2 != 0 )\r\n\t{\r\n\t\t// Send a pointer to a struct AMessage object.  Don't block if the\r\n\t\t// queue is already full.\r\n\t\tpxMessage = & xMessage;\r\n\t\txQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );\r\n\t}\r\n\r\n\t// ... Rest of task code.\r\n }\r\n </pre>\r\n * \\defgroup xQueueSend xQueueSend\r\n * \\ingroup QueueManagement\r\n */\r\n#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT )\r\n\r\n/**\r\n * queue. h\r\n * <pre>\r\n BaseType_t xQueueSendToBack(\r\n\t\t\t\t\t\t\t\t   QueueHandle_t\txQueue,\r\n\t\t\t\t\t\t\t\t   const void\t\t*pvItemToQueue,\r\n\t\t\t\t\t\t\t\t   TickType_t\t\txTicksToWait\r\n\t\t\t\t\t\t\t   );\r\n * </pre>\r\n *\r\n * This is a macro that calls xQueueGenericSend().\r\n *\r\n * Post an item to the back of a queue.  The item is queued by copy, not by\r\n * reference.  This function must not be called from an interrupt service\r\n * routine.  See xQueueSendFromISR () for an alternative which may be used\r\n * in an ISR.\r\n *\r\n * @param xQueue The handle to the queue on which the item is to be posted.\r\n *\r\n * @param pvItemToQueue A pointer to the item that is to be placed on the\r\n * queue.  The size of the items the queue will hold was defined when the\r\n * queue was created, so this many bytes will be copied from pvItemToQueue\r\n * into the queue storage area.\r\n *\r\n * @param xTicksToWait The maximum amount of time the task should block\r\n * waiting for space to become available on the queue, should it already\r\n * be full.  The call will return immediately if this is set to 0 and the queue\r\n * is full.  The  time is defined in tick periods so the constant\r\n * portTICK_PERIOD_MS should be used to convert to real time if this is required.\r\n *\r\n * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.\r\n *\r\n * Example usage:\r\n   <pre>\r\n struct AMessage\r\n {\r\n\tchar ucMessageID;\r\n\tchar ucData[ 20 ];\r\n } xMessage;\r\n\r\n uint32_t ulVar = 10UL;\r\n\r\n void vATask( void *pvParameters )\r\n {\r\n QueueHandle_t xQueue1, xQueue2;\r\n struct AMessage *pxMessage;\r\n\r\n\t// Create a queue capable of containing 10 uint32_t values.\r\n\txQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );\r\n\r\n\t// Create a queue capable of containing 10 pointers to AMessage structures.\r\n\t// These should be passed by pointer as they contain a lot of data.\r\n\txQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );\r\n\r\n\t// ...\r\n\r\n\tif( xQueue1 != 0 )\r\n\t{\r\n\t\t// Send an uint32_t.  Wait for 10 ticks for space to become\r\n\t\t// available if necessary.\r\n\t\tif( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )\r\n\t\t{\r\n\t\t\t// Failed to post the message, even after 10 ticks.\r\n\t\t}\r\n\t}\r\n\r\n\tif( xQueue2 != 0 )\r\n\t{\r\n\t\t// Send a pointer to a struct AMessage object.  Don't block if the\r\n\t\t// queue is already full.\r\n\t\tpxMessage = & xMessage;\r\n\t\txQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );\r\n\t}\r\n\r\n\t// ... Rest of task code.\r\n }\r\n </pre>\r\n * \\defgroup xQueueSend xQueueSend\r\n * \\ingroup QueueManagement\r\n */\r\n#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )\r\n\r\n/**\r\n * queue. h\r\n * <pre>\r\n BaseType_t xQueueSend(\r\n\t\t\t\t\t\t\t  QueueHandle_t xQueue,\r\n\t\t\t\t\t\t\t  const void * pvItemToQueue,\r\n\t\t\t\t\t\t\t  TickType_t xTicksToWait\r\n\t\t\t\t\t\t );\r\n * </pre>\r\n *\r\n * This is a macro that calls xQueueGenericSend().  It is included for\r\n * backward compatibility with versions of FreeRTOS.org that did not\r\n * include the xQueueSendToFront() and xQueueSendToBack() macros.  It is\r\n * equivalent to xQueueSendToBack().\r\n *\r\n * Post an item on a queue.  The item is queued by copy, not by reference.\r\n * This function must not be called from an interrupt service routine.\r\n * See xQueueSendFromISR () for an alternative which may be used in an ISR.\r\n *\r\n * @param xQueue The handle to the queue on which the item is to be posted.\r\n *\r\n * @param pvItemToQueue A pointer to the item that is to be placed on the\r\n * queue.  The size of the items the queue will hold was defined when the\r\n * queue was created, so this many bytes will be copied from pvItemToQueue\r\n * into the queue storage area.\r\n *\r\n * @param xTicksToWait The maximum amount of time the task should block\r\n * waiting for space to become available on the queue, should it already\r\n * be full.  The call will return immediately if this is set to 0 and the\r\n * queue is full.  The time is defined in tick periods so the constant\r\n * portTICK_PERIOD_MS should be used to convert to real time if this is required.\r\n *\r\n * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.\r\n *\r\n * Example usage:\r\n   <pre>\r\n struct AMessage\r\n {\r\n\tchar ucMessageID;\r\n\tchar ucData[ 20 ];\r\n } xMessage;\r\n\r\n uint32_t ulVar = 10UL;\r\n\r\n void vATask( void *pvParameters )\r\n {\r\n QueueHandle_t xQueue1, xQueue2;\r\n struct AMessage *pxMessage;\r\n\r\n\t// Create a queue capable of containing 10 uint32_t values.\r\n\txQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );\r\n\r\n\t// Create a queue capable of containing 10 pointers to AMessage structures.\r\n\t// These should be passed by pointer as they contain a lot of data.\r\n\txQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );\r\n\r\n\t// ...\r\n\r\n\tif( xQueue1 != 0 )\r\n\t{\r\n\t\t// Send an uint32_t.  Wait for 10 ticks for space to become\r\n\t\t// available if necessary.\r\n\t\tif( xQueueSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )\r\n\t\t{\r\n\t\t\t// Failed to post the message, even after 10 ticks.\r\n\t\t}\r\n\t}\r\n\r\n\tif( xQueue2 != 0 )\r\n\t{\r\n\t\t// Send a pointer to a struct AMessage object.  Don't block if the\r\n\t\t// queue is already full.\r\n\t\tpxMessage = & xMessage;\r\n\t\txQueueSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );\r\n\t}\r\n\r\n\t// ... Rest of task code.\r\n }\r\n </pre>\r\n * \\defgroup xQueueSend xQueueSend\r\n * \\ingroup QueueManagement\r\n */\r\n#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )\r\n\r\n/**\r\n * queue. h\r\n * <pre>\r\n BaseType_t xQueueOverwrite(\r\n\t\t\t\t\t\t\t  QueueHandle_t xQueue,\r\n\t\t\t\t\t\t\t  const void * pvItemToQueue\r\n\t\t\t\t\t\t );\r\n * </pre>\r\n *\r\n * Only for use with queues that have a length of one - so the queue is either\r\n * empty or full.\r\n *\r\n * Post an item on a queue.  If the queue is already full then overwrite the\r\n * value held in the queue.  The item is queued by copy, not by reference.\r\n *\r\n * This function must not be called from an interrupt service routine.\r\n * See xQueueOverwriteFromISR () for an alternative which may be used in an ISR.\r\n *\r\n * @param xQueue The handle of the queue to which the data is being sent.\r\n *\r\n * @param pvItemToQueue A pointer to the item that is to be placed on the\r\n * queue.  The size of the items the queue will hold was defined when the\r\n * queue was created, so this many bytes will be copied from pvItemToQueue\r\n * into the queue storage area.\r\n *\r\n * @return xQueueOverwrite() is a macro that calls xQueueGenericSend(), and\r\n * therefore has the same return values as xQueueSendToFront().  However, pdPASS\r\n * is the only value that can be returned because xQueueOverwrite() will write\r\n * to the queue even when the queue is already full.\r\n *\r\n * Example usage:\r\n   <pre>\r\n\r\n void vFunction( void *pvParameters )\r\n {\r\n QueueHandle_t xQueue;\r\n uint32_t ulVarToSend, ulValReceived;\r\n\r\n\t// Create a queue to hold one uint32_t value.  It is strongly\r\n\t// recommended *not* to use xQueueOverwrite() on queues that can\r\n\t// contain more than one value, and doing so will trigger an assertion\r\n\t// if configASSERT() is defined.\r\n\txQueue = xQueueCreate( 1, sizeof( uint32_t ) );\r\n\r\n\t// Write the value 10 to the queue using xQueueOverwrite().\r\n\tulVarToSend = 10;\r\n\txQueueOverwrite( xQueue, &ulVarToSend );\r\n\r\n\t// Peeking the queue should now return 10, but leave the value 10 in\r\n\t// the queue.  A block time of zero is used as it is known that the\r\n\t// queue holds a value.\r\n\tulValReceived = 0;\r\n\txQueuePeek( xQueue, &ulValReceived, 0 );\r\n\r\n\tif( ulValReceived != 10 )\r\n\t{\r\n\t\t// Error unless the item was removed by a different task.\r\n\t}\r\n\r\n\t// The queue is still full.  Use xQueueOverwrite() to overwrite the\r\n\t// value held in the queue with 100.\r\n\tulVarToSend = 100;\r\n\txQueueOverwrite( xQueue, &ulVarToSend );\r\n\r\n\t// This time read from the queue, leaving the queue empty once more.\r\n\t// A block time of 0 is used again.\r\n\txQueueReceive( xQueue, &ulValReceived, 0 );\r\n\r\n\t// The value read should be the last value written, even though the\r\n\t// queue was already full when the value was written.\r\n\tif( ulValReceived != 100 )\r\n\t{\r\n\t\t// Error!\r\n\t}\r\n\r\n\t// ...\r\n}\r\n </pre>\r\n * \\defgroup xQueueOverwrite xQueueOverwrite\r\n * \\ingroup QueueManagement\r\n */\r\n#define xQueueOverwrite( xQueue, pvItemToQueue ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), 0, queueOVERWRITE )\r\n\r\n\r\n/**\r\n * queue. h\r\n * <pre>\r\n BaseType_t xQueueGenericSend(\r\n\t\t\t\t\t\t\t\t\tQueueHandle_t xQueue,\r\n\t\t\t\t\t\t\t\t\tconst void * pvItemToQueue,\r\n\t\t\t\t\t\t\t\t\tTickType_t xTicksToWait\r\n\t\t\t\t\t\t\t\t\tBaseType_t xCopyPosition\r\n\t\t\t\t\t\t\t\t);\r\n * </pre>\r\n *\r\n * It is preferred that the macros xQueueSend(), xQueueSendToFront() and\r\n * xQueueSendToBack() are used in place of calling this function directly.\r\n *\r\n * Post an item on a queue.  The item is queued by copy, not by reference.\r\n * This function must not be called from an interrupt service routine.\r\n * See xQueueSendFromISR () for an alternative which may be used in an ISR.\r\n *\r\n * @param xQueue The handle to the queue on which the item is to be posted.\r\n *\r\n * @param pvItemToQueue A pointer to the item that is to be placed on the\r\n * queue.  The size of the items the queue will hold was defined when the\r\n * queue was created, so this many bytes will be copied from pvItemToQueue\r\n * into the queue storage area.\r\n *\r\n * @param xTicksToWait The maximum amount of time the task should block\r\n * waiting for space to become available on the queue, should it already\r\n * be full.  The call will return immediately if this is set to 0 and the\r\n * queue is full.  The time is defined in tick periods so the constant\r\n * portTICK_PERIOD_MS should be used to convert to real time if this is required.\r\n *\r\n * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the\r\n * item at the back of the queue, or queueSEND_TO_FRONT to place the item\r\n * at the front of the queue (for high priority messages).\r\n *\r\n * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.\r\n *\r\n * Example usage:\r\n   <pre>\r\n struct AMessage\r\n {\r\n\tchar ucMessageID;\r\n\tchar ucData[ 20 ];\r\n } xMessage;\r\n\r\n uint32_t ulVar = 10UL;\r\n\r\n void vATask( void *pvParameters )\r\n {\r\n QueueHandle_t xQueue1, xQueue2;\r\n struct AMessage *pxMessage;\r\n\r\n\t// Create a queue capable of containing 10 uint32_t values.\r\n\txQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );\r\n\r\n\t// Create a queue capable of containing 10 pointers to AMessage structures.\r\n\t// These should be passed by pointer as they contain a lot of data.\r\n\txQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );\r\n\r\n\t// ...\r\n\r\n\tif( xQueue1 != 0 )\r\n\t{\r\n\t\t// Send an uint32_t.  Wait for 10 ticks for space to become\r\n\t\t// available if necessary.\r\n\t\tif( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10, queueSEND_TO_BACK ) != pdPASS )\r\n\t\t{\r\n\t\t\t// Failed to post the message, even after 10 ticks.\r\n\t\t}\r\n\t}\r\n\r\n\tif( xQueue2 != 0 )\r\n\t{\r\n\t\t// Send a pointer to a struct AMessage object.  Don't block if the\r\n\t\t// queue is already full.\r\n\t\tpxMessage = & xMessage;\r\n\t\txQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0, queueSEND_TO_BACK );\r\n\t}\r\n\r\n\t// ... Rest of task code.\r\n }\r\n </pre>\r\n * \\defgroup xQueueSend xQueueSend\r\n * \\ingroup QueueManagement\r\n */\r\nBaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;\r\n\r\n/**\r\n * queue. h\r\n * <pre>\r\n BaseType_t xQueuePeek(\r\n\t\t\t\t\t\t\t QueueHandle_t xQueue,\r\n\t\t\t\t\t\t\t void *pvBuffer,\r\n\t\t\t\t\t\t\t TickType_t xTicksToWait\r\n\t\t\t\t\t\t );</pre>\r\n *\r\n * This is a macro that calls the xQueueGenericReceive() function.\r\n *\r\n * Receive an item from a queue without removing the item from the queue.\r\n * The item is received by copy so a buffer of adequate size must be\r\n * provided.  The number of bytes copied into the buffer was defined when\r\n * the queue was created.\r\n *\r\n * Successfully received items remain on the queue so will be returned again\r\n * by the next call, or a call to xQueueReceive().\r\n *\r\n * This macro must not be used in an interrupt service routine.  See\r\n * xQueuePeekFromISR() for an alternative that can be called from an interrupt\r\n * service routine.\r\n *\r\n * @param xQueue The handle to the queue from which the item is to be\r\n * received.\r\n *\r\n * @param pvBuffer Pointer to the buffer into which the received item will\r\n * be copied.\r\n *\r\n * @param xTicksToWait The maximum amount of time the task should block\r\n * waiting for an item to receive should the queue be empty at the time\r\n * of the call.\t The time is defined in tick periods so the constant\r\n * portTICK_PERIOD_MS should be used to convert to real time if this is required.\r\n * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue\r\n * is empty.\r\n *\r\n * @return pdTRUE if an item was successfully received from the queue,\r\n * otherwise pdFALSE.\r\n *\r\n * Example usage:\r\n   <pre>\r\n struct AMessage\r\n {\r\n\tchar ucMessageID;\r\n\tchar ucData[ 20 ];\r\n } xMessage;\r\n\r\n QueueHandle_t xQueue;\r\n\r\n // Task to create a queue and post a value.\r\n void vATask( void *pvParameters )\r\n {\r\n struct AMessage *pxMessage;\r\n\r\n\t// Create a queue capable of containing 10 pointers to AMessage structures.\r\n\t// These should be passed by pointer as they contain a lot of data.\r\n\txQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );\r\n\tif( xQueue == 0 )\r\n\t{\r\n\t\t// Failed to create the queue.\r\n\t}\r\n\r\n\t// ...\r\n\r\n\t// Send a pointer to a struct AMessage object.  Don't block if the\r\n\t// queue is already full.\r\n\tpxMessage = & xMessage;\r\n\txQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );\r\n\r\n\t// ... Rest of task code.\r\n }\r\n\r\n // Task to peek the data from the queue.\r\n void vADifferentTask( void *pvParameters )\r\n {\r\n struct AMessage *pxRxedMessage;\r\n\r\n\tif( xQueue != 0 )\r\n\t{\r\n\t\t// Peek a message on the created queue.  Block for 10 ticks if a\r\n\t\t// message is not immediately available.\r\n\t\tif( xQueuePeek( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )\r\n\t\t{\r\n\t\t\t// pcRxedMessage now points to the struct AMessage variable posted\r\n\t\t\t// by vATask, but the item still remains on the queue.\r\n\t\t}\r\n\t}\r\n\r\n\t// ... Rest of task code.\r\n }\r\n </pre>\r\n * \\defgroup xQueueReceive xQueueReceive\r\n * \\ingroup QueueManagement\r\n */\r\n#define xQueuePeek( xQueue, pvBuffer, xTicksToWait ) xQueueGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdTRUE )\r\n\r\n/**\r\n * queue. h\r\n * <pre>\r\n BaseType_t xQueuePeekFromISR(\r\n\t\t\t\t\t\t\t\t\tQueueHandle_t xQueue,\r\n\t\t\t\t\t\t\t\t\tvoid *pvBuffer,\r\n\t\t\t\t\t\t\t\t);</pre>\r\n *\r\n * A version of xQueuePeek() that can be called from an interrupt service\r\n * routine (ISR).\r\n *\r\n * Receive an item from a queue without removing the item from the queue.\r\n * The item is received by copy so a buffer of adequate size must be\r\n * provided.  The number of bytes copied into the buffer was defined when\r\n * the queue was created.\r\n *\r\n * Successfully received items remain on the queue so will be returned again\r\n * by the next call, or a call to xQueueReceive().\r\n *\r\n * @param xQueue The handle to the queue from which the item is to be\r\n * received.\r\n *\r\n * @param pvBuffer Pointer to the buffer into which the received item will\r\n * be copied.\r\n *\r\n * @return pdTRUE if an item was successfully received from the queue,\r\n * otherwise pdFALSE.\r\n *\r\n * \\defgroup xQueuePeekFromISR xQueuePeekFromISR\r\n * \\ingroup QueueManagement\r\n */\r\nBaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;\r\n\r\n/**\r\n * queue. h\r\n * <pre>\r\n BaseType_t xQueueReceive(\r\n\t\t\t\t\t\t\t\t QueueHandle_t xQueue,\r\n\t\t\t\t\t\t\t\t void *pvBuffer,\r\n\t\t\t\t\t\t\t\t TickType_t xTicksToWait\r\n\t\t\t\t\t\t\t);</pre>\r\n *\r\n * This is a macro that calls the xQueueGenericReceive() function.\r\n *\r\n * Receive an item from a queue.  The item is received by copy so a buffer of\r\n * adequate size must be provided.  The number of bytes copied into the buffer\r\n * was defined when the queue was created.\r\n *\r\n * Successfully received items are removed from the queue.\r\n *\r\n * This function must not be used in an interrupt service routine.  See\r\n * xQueueReceiveFromISR for an alternative that can.\r\n *\r\n * @param xQueue The handle to the queue from which the item is to be\r\n * received.\r\n *\r\n * @param pvBuffer Pointer to the buffer into which the received item will\r\n * be copied.\r\n *\r\n * @param xTicksToWait The maximum amount of time the task should block\r\n * waiting for an item to receive should the queue be empty at the time\r\n * of the call.\t xQueueReceive() will return immediately if xTicksToWait\r\n * is zero and the queue is empty.  The time is defined in tick periods so the\r\n * constant portTICK_PERIOD_MS should be used to convert to real time if this is\r\n * required.\r\n *\r\n * @return pdTRUE if an item was successfully received from the queue,\r\n * otherwise pdFALSE.\r\n *\r\n * Example usage:\r\n   <pre>\r\n struct AMessage\r\n {\r\n\tchar ucMessageID;\r\n\tchar ucData[ 20 ];\r\n } xMessage;\r\n\r\n QueueHandle_t xQueue;\r\n\r\n // Task to create a queue and post a value.\r\n void vATask( void *pvParameters )\r\n {\r\n struct AMessage *pxMessage;\r\n\r\n\t// Create a queue capable of containing 10 pointers to AMessage structures.\r\n\t// These should be passed by pointer as they contain a lot of data.\r\n\txQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );\r\n\tif( xQueue == 0 )\r\n\t{\r\n\t\t// Failed to create the queue.\r\n\t}\r\n\r\n\t// ...\r\n\r\n\t// Send a pointer to a struct AMessage object.  Don't block if the\r\n\t// queue is already full.\r\n\tpxMessage = & xMessage;\r\n\txQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );\r\n\r\n\t// ... Rest of task code.\r\n }\r\n\r\n // Task to receive from the queue.\r\n void vADifferentTask( void *pvParameters )\r\n {\r\n struct AMessage *pxRxedMessage;\r\n\r\n\tif( xQueue != 0 )\r\n\t{\r\n\t\t// Receive a message on the created queue.  Block for 10 ticks if a\r\n\t\t// message is not immediately available.\r\n\t\tif( xQueueReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )\r\n\t\t{\r\n\t\t\t// pcRxedMessage now points to the struct AMessage variable posted\r\n\t\t\t// by vATask.\r\n\t\t}\r\n\t}\r\n\r\n\t// ... Rest of task code.\r\n }\r\n </pre>\r\n * \\defgroup xQueueReceive xQueueReceive\r\n * \\ingroup QueueManagement\r\n */\r\n#define xQueueReceive( xQueue, pvBuffer, xTicksToWait ) xQueueGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdFALSE )\r\n\r\n\r\n/**\r\n * queue. h\r\n * <pre>\r\n BaseType_t xQueueGenericReceive(\r\n\t\t\t\t\t\t\t\t\t   QueueHandle_t\txQueue,\r\n\t\t\t\t\t\t\t\t\t   void\t*pvBuffer,\r\n\t\t\t\t\t\t\t\t\t   TickType_t\txTicksToWait\r\n\t\t\t\t\t\t\t\t\t   BaseType_t\txJustPeek\r\n\t\t\t\t\t\t\t\t\t);</pre>\r\n *\r\n * It is preferred that the macro xQueueReceive() be used rather than calling\r\n * this function directly.\r\n *\r\n * Receive an item from a queue.  The item is received by copy so a buffer of\r\n * adequate size must be provided.  The number of bytes copied into the buffer\r\n * was defined when the queue was created.\r\n *\r\n * This function must not be used in an interrupt service routine.  See\r\n * xQueueReceiveFromISR for an alternative that can.\r\n *\r\n * @param xQueue The handle to the queue from which the item is to be\r\n * received.\r\n *\r\n * @param pvBuffer Pointer to the buffer into which the received item will\r\n * be copied.\r\n *\r\n * @param xTicksToWait The maximum amount of time the task should block\r\n * waiting for an item to receive should the queue be empty at the time\r\n * of the call.\t The time is defined in tick periods so the constant\r\n * portTICK_PERIOD_MS should be used to convert to real time if this is required.\r\n * xQueueGenericReceive() will return immediately if the queue is empty and\r\n * xTicksToWait is 0.\r\n *\r\n * @param xJustPeek When set to true, the item received from the queue is not\r\n * actually removed from the queue - meaning a subsequent call to\r\n * xQueueReceive() will return the same item.  When set to false, the item\r\n * being received from the queue is also removed from the queue.\r\n *\r\n * @return pdTRUE if an item was successfully received from the queue,\r\n * otherwise pdFALSE.\r\n *\r\n * Example usage:\r\n   <pre>\r\n struct AMessage\r\n {\r\n\tchar ucMessageID;\r\n\tchar ucData[ 20 ];\r\n } xMessage;\r\n\r\n QueueHandle_t xQueue;\r\n\r\n // Task to create a queue and post a value.\r\n void vATask( void *pvParameters )\r\n {\r\n struct AMessage *pxMessage;\r\n\r\n\t// Create a queue capable of containing 10 pointers to AMessage structures.\r\n\t// These should be passed by pointer as they contain a lot of data.\r\n\txQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );\r\n\tif( xQueue == 0 )\r\n\t{\r\n\t\t// Failed to create the queue.\r\n\t}\r\n\r\n\t// ...\r\n\r\n\t// Send a pointer to a struct AMessage object.  Don't block if the\r\n\t// queue is already full.\r\n\tpxMessage = & xMessage;\r\n\txQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );\r\n\r\n\t// ... Rest of task code.\r\n }\r\n\r\n // Task to receive from the queue.\r\n void vADifferentTask( void *pvParameters )\r\n {\r\n struct AMessage *pxRxedMessage;\r\n\r\n\tif( xQueue != 0 )\r\n\t{\r\n\t\t// Receive a message on the created queue.  Block for 10 ticks if a\r\n\t\t// message is not immediately available.\r\n\t\tif( xQueueGenericReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )\r\n\t\t{\r\n\t\t\t// pcRxedMessage now points to the struct AMessage variable posted\r\n\t\t\t// by vATask.\r\n\t\t}\r\n\t}\r\n\r\n\t// ... Rest of task code.\r\n }\r\n </pre>\r\n * \\defgroup xQueueReceive xQueueReceive\r\n * \\ingroup QueueManagement\r\n */\r\nBaseType_t xQueueGenericReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait, const BaseType_t xJustPeek ) PRIVILEGED_FUNCTION;\r\n\r\n/**\r\n * queue. h\r\n * <pre>UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue );</pre>\r\n *\r\n * Return the number of messages stored in a queue.\r\n *\r\n * @param xQueue A handle to the queue being queried.\r\n *\r\n * @return The number of messages available in the queue.\r\n *\r\n * \\defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting\r\n * \\ingroup QueueManagement\r\n */\r\nUBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\r\n\r\n/**\r\n * queue. h\r\n * <pre>UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue );</pre>\r\n *\r\n * Return the number of free spaces available in a queue.  This is equal to the\r\n * number of items that can be sent to the queue before the queue becomes full\r\n * if no items are removed.\r\n *\r\n * @param xQueue A handle to the queue being queried.\r\n *\r\n * @return The number of spaces available in the queue.\r\n *\r\n * \\defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting\r\n * \\ingroup QueueManagement\r\n */\r\nUBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\r\n\r\n/**\r\n * queue. h\r\n * <pre>void vQueueDelete( QueueHandle_t xQueue );</pre>\r\n *\r\n * Delete a queue - freeing all the memory allocated for storing of items\r\n * placed on the queue.\r\n *\r\n * @param xQueue A handle to the queue to be deleted.\r\n *\r\n * \\defgroup vQueueDelete vQueueDelete\r\n * \\ingroup QueueManagement\r\n */\r\nvoid vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\r\n\r\n/**\r\n * queue. h\r\n * <pre>\r\n BaseType_t xQueueSendToFrontFromISR(\r\n\t\t\t\t\t\t\t\t\t\t QueueHandle_t xQueue,\r\n\t\t\t\t\t\t\t\t\t\t const void *pvItemToQueue,\r\n\t\t\t\t\t\t\t\t\t\t BaseType_t *pxHigherPriorityTaskWoken\r\n\t\t\t\t\t\t\t\t\t  );\r\n </pre>\r\n *\r\n * This is a macro that calls xQueueGenericSendFromISR().\r\n *\r\n * Post an item to the front of a queue.  It is safe to use this macro from\r\n * within an interrupt service routine.\r\n *\r\n * Items are queued by copy not reference so it is preferable to only\r\n * queue small items, especially when called from an ISR.  In most cases\r\n * it would be preferable to store a pointer to the item being queued.\r\n *\r\n * @param xQueue The handle to the queue on which the item is to be posted.\r\n *\r\n * @param pvItemToQueue A pointer to the item that is to be placed on the\r\n * queue.  The size of the items the queue will hold was defined when the\r\n * queue was created, so this many bytes will be copied from pvItemToQueue\r\n * into the queue storage area.\r\n *\r\n * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set\r\n * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task\r\n * to unblock, and the unblocked task has a priority higher than the currently\r\n * running task.  If xQueueSendToFromFromISR() sets this value to pdTRUE then\r\n * a context switch should be requested before the interrupt is exited.\r\n *\r\n * @return pdTRUE if the data was successfully sent to the queue, otherwise\r\n * errQUEUE_FULL.\r\n *\r\n * Example usage for buffered IO (where the ISR can obtain more than one value\r\n * per call):\r\n   <pre>\r\n void vBufferISR( void )\r\n {\r\n char cIn;\r\n BaseType_t xHigherPrioritTaskWoken;\r\n\r\n\t// We have not woken a task at the start of the ISR.\r\n\txHigherPriorityTaskWoken = pdFALSE;\r\n\r\n\t// Loop until the buffer is empty.\r\n\tdo\r\n\t{\r\n\t\t// Obtain a byte from the buffer.\r\n\t\tcIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );\r\n\r\n\t\t// Post the byte.\r\n\t\txQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );\r\n\r\n\t} while( portINPUT_BYTE( BUFFER_COUNT ) );\r\n\r\n\t// Now the buffer is empty we can switch context if necessary.\r\n\tif( xHigherPriorityTaskWoken )\r\n\t{\r\n\t\ttaskYIELD ();\r\n\t}\r\n }\r\n </pre>\r\n *\r\n * \\defgroup xQueueSendFromISR xQueueSendFromISR\r\n * \\ingroup QueueManagement\r\n */\r\n#define xQueueSendToFrontFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT )\r\n\r\n\r\n/**\r\n * queue. h\r\n * <pre>\r\n BaseType_t xQueueSendToBackFromISR(\r\n\t\t\t\t\t\t\t\t\t\t QueueHandle_t xQueue,\r\n\t\t\t\t\t\t\t\t\t\t const void *pvItemToQueue,\r\n\t\t\t\t\t\t\t\t\t\t BaseType_t *pxHigherPriorityTaskWoken\r\n\t\t\t\t\t\t\t\t\t  );\r\n </pre>\r\n *\r\n * This is a macro that calls xQueueGenericSendFromISR().\r\n *\r\n * Post an item to the back of a queue.  It is safe to use this macro from\r\n * within an interrupt service routine.\r\n *\r\n * Items are queued by copy not reference so it is preferable to only\r\n * queue small items, especially when called from an ISR.  In most cases\r\n * it would be preferable to store a pointer to the item being queued.\r\n *\r\n * @param xQueue The handle to the queue on which the item is to be posted.\r\n *\r\n * @param pvItemToQueue A pointer to the item that is to be placed on the\r\n * queue.  The size of the items the queue will hold was defined when the\r\n * queue was created, so this many bytes will be copied from pvItemToQueue\r\n * into the queue storage area.\r\n *\r\n * @param pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set\r\n * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task\r\n * to unblock, and the unblocked task has a priority higher than the currently\r\n * running task.  If xQueueSendToBackFromISR() sets this value to pdTRUE then\r\n * a context switch should be requested before the interrupt is exited.\r\n *\r\n * @return pdTRUE if the data was successfully sent to the queue, otherwise\r\n * errQUEUE_FULL.\r\n *\r\n * Example usage for buffered IO (where the ISR can obtain more than one value\r\n * per call):\r\n   <pre>\r\n void vBufferISR( void )\r\n {\r\n char cIn;\r\n BaseType_t xHigherPriorityTaskWoken;\r\n\r\n\t// We have not woken a task at the start of the ISR.\r\n\txHigherPriorityTaskWoken = pdFALSE;\r\n\r\n\t// Loop until the buffer is empty.\r\n\tdo\r\n\t{\r\n\t\t// Obtain a byte from the buffer.\r\n\t\tcIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );\r\n\r\n\t\t// Post the byte.\r\n\t\txQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );\r\n\r\n\t} while( portINPUT_BYTE( BUFFER_COUNT ) );\r\n\r\n\t// Now the buffer is empty we can switch context if necessary.\r\n\tif( xHigherPriorityTaskWoken )\r\n\t{\r\n\t\ttaskYIELD ();\r\n\t}\r\n }\r\n </pre>\r\n *\r\n * \\defgroup xQueueSendFromISR xQueueSendFromISR\r\n * \\ingroup QueueManagement\r\n */\r\n#define xQueueSendToBackFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )\r\n\r\n/**\r\n * queue. h\r\n * <pre>\r\n BaseType_t xQueueOverwriteFromISR(\r\n\t\t\t\t\t\t\t  QueueHandle_t xQueue,\r\n\t\t\t\t\t\t\t  const void * pvItemToQueue,\r\n\t\t\t\t\t\t\t  BaseType_t *pxHigherPriorityTaskWoken\r\n\t\t\t\t\t\t );\r\n * </pre>\r\n *\r\n * A version of xQueueOverwrite() that can be used in an interrupt service\r\n * routine (ISR).\r\n *\r\n * Only for use with queues that can hold a single item - so the queue is either\r\n * empty or full.\r\n *\r\n * Post an item on a queue.  If the queue is already full then overwrite the\r\n * value held in the queue.  The item is queued by copy, not by reference.\r\n *\r\n * @param xQueue The handle to the queue on which the item is to be posted.\r\n *\r\n * @param pvItemToQueue A pointer to the item that is to be placed on the\r\n * queue.  The size of the items the queue will hold was defined when the\r\n * queue was created, so this many bytes will be copied from pvItemToQueue\r\n * into the queue storage area.\r\n *\r\n * @param pxHigherPriorityTaskWoken xQueueOverwriteFromISR() will set\r\n * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task\r\n * to unblock, and the unblocked task has a priority higher than the currently\r\n * running task.  If xQueueOverwriteFromISR() sets this value to pdTRUE then\r\n * a context switch should be requested before the interrupt is exited.\r\n *\r\n * @return xQueueOverwriteFromISR() is a macro that calls\r\n * xQueueGenericSendFromISR(), and therefore has the same return values as\r\n * xQueueSendToFrontFromISR().  However, pdPASS is the only value that can be\r\n * returned because xQueueOverwriteFromISR() will write to the queue even when\r\n * the queue is already full.\r\n *\r\n * Example usage:\r\n   <pre>\r\n\r\n QueueHandle_t xQueue;\r\n\r\n void vFunction( void *pvParameters )\r\n {\r\n \t// Create a queue to hold one uint32_t value.  It is strongly\r\n\t// recommended *not* to use xQueueOverwriteFromISR() on queues that can\r\n\t// contain more than one value, and doing so will trigger an assertion\r\n\t// if configASSERT() is defined.\r\n\txQueue = xQueueCreate( 1, sizeof( uint32_t ) );\r\n}\r\n\r\nvoid vAnInterruptHandler( void )\r\n{\r\n// xHigherPriorityTaskWoken must be set to pdFALSE before it is used.\r\nBaseType_t xHigherPriorityTaskWoken = pdFALSE;\r\nuint32_t ulVarToSend, ulValReceived;\r\n\r\n\t// Write the value 10 to the queue using xQueueOverwriteFromISR().\r\n\tulVarToSend = 10;\r\n\txQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );\r\n\r\n\t// The queue is full, but calling xQueueOverwriteFromISR() again will still\r\n\t// pass because the value held in the queue will be overwritten with the\r\n\t// new value.\r\n\tulVarToSend = 100;\r\n\txQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );\r\n\r\n\t// Reading from the queue will now return 100.\r\n\r\n\t// ...\r\n\r\n\tif( xHigherPrioritytaskWoken == pdTRUE )\r\n\t{\r\n\t\t// Writing to the queue caused a task to unblock and the unblocked task\r\n\t\t// has a priority higher than or equal to the priority of the currently\r\n\t\t// executing task (the task this interrupt interrupted).  Perform a context\r\n\t\t// switch so this interrupt returns directly to the unblocked task.\r\n\t\tportYIELD_FROM_ISR(); // or portEND_SWITCHING_ISR() depending on the port.\r\n\t}\r\n}\r\n </pre>\r\n * \\defgroup xQueueOverwriteFromISR xQueueOverwriteFromISR\r\n * \\ingroup QueueManagement\r\n */\r\n#define xQueueOverwriteFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueOVERWRITE )\r\n\r\n/**\r\n * queue. h\r\n * <pre>\r\n BaseType_t xQueueSendFromISR(\r\n\t\t\t\t\t\t\t\t\t QueueHandle_t xQueue,\r\n\t\t\t\t\t\t\t\t\t const void *pvItemToQueue,\r\n\t\t\t\t\t\t\t\t\t BaseType_t *pxHigherPriorityTaskWoken\r\n\t\t\t\t\t\t\t\t);\r\n </pre>\r\n *\r\n * This is a macro that calls xQueueGenericSendFromISR().  It is included\r\n * for backward compatibility with versions of FreeRTOS.org that did not\r\n * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR()\r\n * macros.\r\n *\r\n * Post an item to the back of a queue.  It is safe to use this function from\r\n * within an interrupt service routine.\r\n *\r\n * Items are queued by copy not reference so it is preferable to only\r\n * queue small items, especially when called from an ISR.  In most cases\r\n * it would be preferable to store a pointer to the item being queued.\r\n *\r\n * @param xQueue The handle to the queue on which the item is to be posted.\r\n *\r\n * @param pvItemToQueue A pointer to the item that is to be placed on the\r\n * queue.  The size of the items the queue will hold was defined when the\r\n * queue was created, so this many bytes will be copied from pvItemToQueue\r\n * into the queue storage area.\r\n *\r\n * @param pxHigherPriorityTaskWoken xQueueSendFromISR() will set\r\n * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task\r\n * to unblock, and the unblocked task has a priority higher than the currently\r\n * running task.  If xQueueSendFromISR() sets this value to pdTRUE then\r\n * a context switch should be requested before the interrupt is exited.\r\n *\r\n * @return pdTRUE if the data was successfully sent to the queue, otherwise\r\n * errQUEUE_FULL.\r\n *\r\n * Example usage for buffered IO (where the ISR can obtain more than one value\r\n * per call):\r\n   <pre>\r\n void vBufferISR( void )\r\n {\r\n char cIn;\r\n BaseType_t xHigherPriorityTaskWoken;\r\n\r\n\t// We have not woken a task at the start of the ISR.\r\n\txHigherPriorityTaskWoken = pdFALSE;\r\n\r\n\t// Loop until the buffer is empty.\r\n\tdo\r\n\t{\r\n\t\t// Obtain a byte from the buffer.\r\n\t\tcIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );\r\n\r\n\t\t// Post the byte.\r\n\t\txQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );\r\n\r\n\t} while( portINPUT_BYTE( BUFFER_COUNT ) );\r\n\r\n\t// Now the buffer is empty we can switch context if necessary.\r\n\tif( xHigherPriorityTaskWoken )\r\n\t{\r\n\t\t// Actual macro used here is port specific.\r\n\t\tportYIELD_FROM_ISR ();\r\n\t}\r\n }\r\n </pre>\r\n *\r\n * \\defgroup xQueueSendFromISR xQueueSendFromISR\r\n * \\ingroup QueueManagement\r\n */\r\n#define xQueueSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )\r\n\r\n/**\r\n * queue. h\r\n * <pre>\r\n BaseType_t xQueueGenericSendFromISR(\r\n\t\t\t\t\t\t\t\t\t\t   QueueHandle_t\t\txQueue,\r\n\t\t\t\t\t\t\t\t\t\t   const\tvoid\t*pvItemToQueue,\r\n\t\t\t\t\t\t\t\t\t\t   BaseType_t\t*pxHigherPriorityTaskWoken,\r\n\t\t\t\t\t\t\t\t\t\t   BaseType_t\txCopyPosition\r\n\t\t\t\t\t\t\t\t\t   );\r\n </pre>\r\n *\r\n * It is preferred that the macros xQueueSendFromISR(),\r\n * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place\r\n * of calling this function directly.  xQueueGiveFromISR() is an\r\n * equivalent for use by semaphores that don't actually copy any data.\r\n *\r\n * Post an item on a queue.  It is safe to use this function from within an\r\n * interrupt service routine.\r\n *\r\n * Items are queued by copy not reference so it is preferable to only\r\n * queue small items, especially when called from an ISR.  In most cases\r\n * it would be preferable to store a pointer to the item being queued.\r\n *\r\n * @param xQueue The handle to the queue on which the item is to be posted.\r\n *\r\n * @param pvItemToQueue A pointer to the item that is to be placed on the\r\n * queue.  The size of the items the queue will hold was defined when the\r\n * queue was created, so this many bytes will be copied from pvItemToQueue\r\n * into the queue storage area.\r\n *\r\n * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set\r\n * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task\r\n * to unblock, and the unblocked task has a priority higher than the currently\r\n * running task.  If xQueueGenericSendFromISR() sets this value to pdTRUE then\r\n * a context switch should be requested before the interrupt is exited.\r\n *\r\n * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the\r\n * item at the back of the queue, or queueSEND_TO_FRONT to place the item\r\n * at the front of the queue (for high priority messages).\r\n *\r\n * @return pdTRUE if the data was successfully sent to the queue, otherwise\r\n * errQUEUE_FULL.\r\n *\r\n * Example usage for buffered IO (where the ISR can obtain more than one value\r\n * per call):\r\n   <pre>\r\n void vBufferISR( void )\r\n {\r\n char cIn;\r\n BaseType_t xHigherPriorityTaskWokenByPost;\r\n\r\n\t// We have not woken a task at the start of the ISR.\r\n\txHigherPriorityTaskWokenByPost = pdFALSE;\r\n\r\n\t// Loop until the buffer is empty.\r\n\tdo\r\n\t{\r\n\t\t// Obtain a byte from the buffer.\r\n\t\tcIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );\r\n\r\n\t\t// Post each byte.\r\n\t\txQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK );\r\n\r\n\t} while( portINPUT_BYTE( BUFFER_COUNT ) );\r\n\r\n\t// Now the buffer is empty we can switch context if necessary.  Note that the\r\n\t// name of the yield function required is port specific.\r\n\tif( xHigherPriorityTaskWokenByPost )\r\n\t{\r\n\t\ttaskYIELD_YIELD_FROM_ISR();\r\n\t}\r\n }\r\n </pre>\r\n *\r\n * \\defgroup xQueueSendFromISR xQueueSendFromISR\r\n * \\ingroup QueueManagement\r\n */\r\nBaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;\r\nBaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;\r\n\r\n/**\r\n * queue. h\r\n * <pre>\r\n BaseType_t xQueueReceiveFromISR(\r\n\t\t\t\t\t\t\t\t\t   QueueHandle_t\txQueue,\r\n\t\t\t\t\t\t\t\t\t   void\t*pvBuffer,\r\n\t\t\t\t\t\t\t\t\t   BaseType_t *pxTaskWoken\r\n\t\t\t\t\t\t\t\t   );\r\n * </pre>\r\n *\r\n * Receive an item from a queue.  It is safe to use this function from within an\r\n * interrupt service routine.\r\n *\r\n * @param xQueue The handle to the queue from which the item is to be\r\n * received.\r\n *\r\n * @param pvBuffer Pointer to the buffer into which the received item will\r\n * be copied.\r\n *\r\n * @param pxTaskWoken A task may be blocked waiting for space to become\r\n * available on the queue.  If xQueueReceiveFromISR causes such a task to\r\n * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will\r\n * remain unchanged.\r\n *\r\n * @return pdTRUE if an item was successfully received from the queue,\r\n * otherwise pdFALSE.\r\n *\r\n * Example usage:\r\n   <pre>\r\n\r\n QueueHandle_t xQueue;\r\n\r\n // Function to create a queue and post some values.\r\n void vAFunction( void *pvParameters )\r\n {\r\n char cValueToPost;\r\n const TickType_t xTicksToWait = ( TickType_t )0xff;\r\n\r\n\t// Create a queue capable of containing 10 characters.\r\n\txQueue = xQueueCreate( 10, sizeof( char ) );\r\n\tif( xQueue == 0 )\r\n\t{\r\n\t\t// Failed to create the queue.\r\n\t}\r\n\r\n\t// ...\r\n\r\n\t// Post some characters that will be used within an ISR.  If the queue\r\n\t// is full then this task will block for xTicksToWait ticks.\r\n\tcValueToPost = 'a';\r\n\txQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );\r\n\tcValueToPost = 'b';\r\n\txQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );\r\n\r\n\t// ... keep posting characters ... this task may block when the queue\r\n\t// becomes full.\r\n\r\n\tcValueToPost = 'c';\r\n\txQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );\r\n }\r\n\r\n // ISR that outputs all the characters received on the queue.\r\n void vISR_Routine( void )\r\n {\r\n BaseType_t xTaskWokenByReceive = pdFALSE;\r\n char cRxedChar;\r\n\r\n\twhile( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )\r\n\t{\r\n\t\t// A character was received.  Output the character now.\r\n\t\tvOutputCharacter( cRxedChar );\r\n\r\n\t\t// If removing the character from the queue woke the task that was\r\n\t\t// posting onto the queue cTaskWokenByReceive will have been set to\r\n\t\t// pdTRUE.  No matter how many times this loop iterates only one\r\n\t\t// task will be woken.\r\n\t}\r\n\r\n\tif( cTaskWokenByPost != ( char ) pdFALSE;\r\n\t{\r\n\t\ttaskYIELD ();\r\n\t}\r\n }\r\n </pre>\r\n * \\defgroup xQueueReceiveFromISR xQueueReceiveFromISR\r\n * \\ingroup QueueManagement\r\n */\r\nBaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * Utilities to query queues that are safe to use from an ISR.  These utilities\r\n * should be used only from witin an ISR, or within a critical section.\r\n */\r\nBaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\r\nBaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\r\nUBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\r\n\r\n\r\n/*\r\n * xQueueAltGenericSend() is an alternative version of xQueueGenericSend().\r\n * Likewise xQueueAltGenericReceive() is an alternative version of\r\n * xQueueGenericReceive().\r\n *\r\n * The source code that implements the alternative (Alt) API is much\r\n * simpler\tbecause it executes everything from within a critical section.\r\n * This is\tthe approach taken by many other RTOSes, but FreeRTOS.org has the\r\n * preferred fully featured API too.  The fully featured API has more\r\n * complex\tcode that takes longer to execute, but makes much less use of\r\n * critical sections.  Therefore the alternative API sacrifices interrupt\r\n * responsiveness to gain execution speed, whereas the fully featured API\r\n * sacrifices execution speed to ensure better interrupt responsiveness.\r\n */\r\nBaseType_t xQueueAltGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, BaseType_t xCopyPosition );\r\nBaseType_t xQueueAltGenericReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait, BaseType_t xJustPeeking );\r\n#define xQueueAltSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueAltGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT )\r\n#define xQueueAltSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueAltGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )\r\n#define xQueueAltReceive( xQueue, pvBuffer, xTicksToWait ) xQueueAltGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdFALSE )\r\n#define xQueueAltPeek( xQueue, pvBuffer, xTicksToWait ) xQueueAltGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdTRUE )\r\n\r\n/*\r\n * The functions defined above are for passing data to and from tasks.  The\r\n * functions below are the equivalents for passing data to and from\r\n * co-routines.\r\n *\r\n * These functions are called from the co-routine macro implementation and\r\n * should not be called directly from application code.  Instead use the macro\r\n * wrappers defined within croutine.h.\r\n */\r\nBaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken );\r\nBaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxTaskWoken );\r\nBaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait );\r\nBaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait );\r\n\r\n/*\r\n * For internal use only.  Use xSemaphoreCreateMutex(),\r\n * xSemaphoreCreateCounting() or xSemaphoreGetMutexHolder() instead of calling\r\n * these functions directly.\r\n */\r\nQueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;\r\nQueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;\r\nvoid* xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * For internal use only.  Use xSemaphoreTakeMutexRecursive() or\r\n * xSemaphoreGiveMutexRecursive() instead of calling these functions directly.\r\n */\r\nBaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\r\nBaseType_t xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * Reset a queue back to its original empty state.  The return value is now\r\n * obsolete and is always set to pdPASS.\r\n */\r\n#define xQueueReset( xQueue ) xQueueGenericReset( xQueue, pdFALSE )\r\n\r\n/*\r\n * The registry is provided as a means for kernel aware debuggers to\r\n * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add\r\n * a queue, semaphore or mutex handle to the registry if you want the handle\r\n * to be available to a kernel aware debugger.  If you are not using a kernel\r\n * aware debugger then this function can be ignored.\r\n *\r\n * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the\r\n * registry can hold.  configQUEUE_REGISTRY_SIZE must be greater than 0\r\n * within FreeRTOSConfig.h for the registry to be available.  Its value\r\n * does not effect the number of queues, semaphores and mutexes that can be\r\n * created - just the number that the registry can hold.\r\n *\r\n * @param xQueue The handle of the queue being added to the registry.  This\r\n * is the handle returned by a call to xQueueCreate().  Semaphore and mutex\r\n * handles can also be passed in here.\r\n *\r\n * @param pcName The name to be associated with the handle.  This is the\r\n * name that the kernel aware debugger will display.  The queue registry only\r\n * stores a pointer to the string - so the string must be persistent (global or\r\n * preferably in ROM/Flash), not on the stack.\r\n */\r\n#if configQUEUE_REGISTRY_SIZE > 0\r\n\tvoid vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\r\n#endif\r\n\r\n/*\r\n * The registry is provided as a means for kernel aware debuggers to\r\n * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add\r\n * a queue, semaphore or mutex handle to the registry if you want the handle\r\n * to be available to a kernel aware debugger, and vQueueUnregisterQueue() to\r\n * remove the queue, semaphore or mutex from the register.  If you are not using\r\n * a kernel aware debugger then this function can be ignored.\r\n *\r\n * @param xQueue The handle of the queue being removed from the registry.\r\n */\r\n#if configQUEUE_REGISTRY_SIZE > 0\r\n\tvoid vQueueUnregisterQueue( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\r\n#endif\r\n\r\n/*\r\n * Generic version of the queue creation function, which is in turn called by\r\n * any queue, semaphore or mutex creation function or macro.\r\n */\r\nQueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * Queue sets provide a mechanism to allow a task to block (pend) on a read\r\n * operation from multiple queues or semaphores simultaneously.\r\n *\r\n * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this\r\n * function.\r\n *\r\n * A queue set must be explicitly created using a call to xQueueCreateSet()\r\n * before it can be used.  Once created, standard FreeRTOS queues and semaphores\r\n * can be added to the set using calls to xQueueAddToSet().\r\n * xQueueSelectFromSet() is then used to determine which, if any, of the queues\r\n * or semaphores contained in the set is in a state where a queue read or\r\n * semaphore take operation would be successful.\r\n *\r\n * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html\r\n * for reasons why queue sets are very rarely needed in practice as there are\r\n * simpler methods of blocking on multiple objects.\r\n *\r\n * Note 2:  Blocking on a queue set that contains a mutex will not cause the\r\n * mutex holder to inherit the priority of the blocked task.\r\n *\r\n * Note 3:  An additional 4 bytes of RAM is required for each space in a every\r\n * queue added to a queue set.  Therefore counting semaphores that have a high\r\n * maximum count value should not be added to a queue set.\r\n *\r\n * Note 4:  A receive (in the case of a queue) or take (in the case of a\r\n * semaphore) operation must not be performed on a member of a queue set unless\r\n * a call to xQueueSelectFromSet() has first returned a handle to that set member.\r\n *\r\n * @param uxEventQueueLength Queue sets store events that occur on\r\n * the queues and semaphores contained in the set.  uxEventQueueLength specifies\r\n * the maximum number of events that can be queued at once.  To be absolutely\r\n * certain that events are not lost uxEventQueueLength should be set to the\r\n * total sum of the length of the queues added to the set, where binary\r\n * semaphores and mutexes have a length of 1, and counting semaphores have a\r\n * length set by their maximum count value.  Examples:\r\n *  + If a queue set is to hold a queue of length 5, another queue of length 12,\r\n *    and a binary semaphore, then uxEventQueueLength should be set to\r\n *    (5 + 12 + 1), or 18.\r\n *  + If a queue set is to hold three binary semaphores then uxEventQueueLength\r\n *    should be set to (1 + 1 + 1 ), or 3.\r\n *  + If a queue set is to hold a counting semaphore that has a maximum count of\r\n *    5, and a counting semaphore that has a maximum count of 3, then\r\n *    uxEventQueueLength should be set to (5 + 3), or 8.\r\n *\r\n * @return If the queue set is created successfully then a handle to the created\r\n * queue set is returned.  Otherwise NULL is returned.\r\n */\r\nQueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * Adds a queue or semaphore to a queue set that was previously created by a\r\n * call to xQueueCreateSet().\r\n *\r\n * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this\r\n * function.\r\n *\r\n * Note 1:  A receive (in the case of a queue) or take (in the case of a\r\n * semaphore) operation must not be performed on a member of a queue set unless\r\n * a call to xQueueSelectFromSet() has first returned a handle to that set member.\r\n *\r\n * @param xQueueOrSemaphore The handle of the queue or semaphore being added to\r\n * the queue set (cast to an QueueSetMemberHandle_t type).\r\n *\r\n * @param xQueueSet The handle of the queue set to which the queue or semaphore\r\n * is being added.\r\n *\r\n * @return If the queue or semaphore was successfully added to the queue set\r\n * then pdPASS is returned.  If the queue could not be successfully added to the\r\n * queue set because it is already a member of a different queue set then pdFAIL\r\n * is returned.\r\n */\r\nBaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * Removes a queue or semaphore from a queue set.  A queue or semaphore can only\r\n * be removed from a set if the queue or semaphore is empty.\r\n *\r\n * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this\r\n * function.\r\n *\r\n * @param xQueueOrSemaphore The handle of the queue or semaphore being removed\r\n * from the queue set (cast to an QueueSetMemberHandle_t type).\r\n *\r\n * @param xQueueSet The handle of the queue set in which the queue or semaphore\r\n * is included.\r\n *\r\n * @return If the queue or semaphore was successfully removed from the queue set\r\n * then pdPASS is returned.  If the queue was not in the queue set, or the\r\n * queue (or semaphore) was not empty, then pdFAIL is returned.\r\n */\r\nBaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * xQueueSelectFromSet() selects from the members of a queue set a queue or\r\n * semaphore that either contains data (in the case of a queue) or is available\r\n * to take (in the case of a semaphore).  xQueueSelectFromSet() effectively\r\n * allows a task to block (pend) on a read operation on all the queues and\r\n * semaphores in a queue set simultaneously.\r\n *\r\n * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this\r\n * function.\r\n *\r\n * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html\r\n * for reasons why queue sets are very rarely needed in practice as there are\r\n * simpler methods of blocking on multiple objects.\r\n *\r\n * Note 2:  Blocking on a queue set that contains a mutex will not cause the\r\n * mutex holder to inherit the priority of the blocked task.\r\n *\r\n * Note 3:  A receive (in the case of a queue) or take (in the case of a\r\n * semaphore) operation must not be performed on a member of a queue set unless\r\n * a call to xQueueSelectFromSet() has first returned a handle to that set member.\r\n *\r\n * @param xQueueSet The queue set on which the task will (potentially) block.\r\n *\r\n * @param xTicksToWait The maximum time, in ticks, that the calling task will\r\n * remain in the Blocked state (with other tasks executing) to wait for a member\r\n * of the queue set to be ready for a successful queue read or semaphore take\r\n * operation.\r\n *\r\n * @return xQueueSelectFromSet() will return the handle of a queue (cast to\r\n * a QueueSetMemberHandle_t type) contained in the queue set that contains data,\r\n * or the handle of a semaphore (cast to a QueueSetMemberHandle_t type) contained\r\n * in the queue set that is available, or NULL if no such queue or semaphore\r\n * exists before before the specified block time expires.\r\n */\r\nQueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * A version of xQueueSelectFromSet() that can be used from an ISR.\r\n */\r\nQueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;\r\n\r\n/* Not public API functions. */\r\nvoid vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\r\nBaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) PRIVILEGED_FUNCTION;\r\nvoid vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION;\r\nUBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\r\nuint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* QUEUE_H */\r\n\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RTOS/src/readme.txt",
    "content": "Each real time kernel port consists of three files that contain the core kernel\r\ncomponents and are common to every port, and one or more files that are \r\nspecific to a particular microcontroller and or compiler.\r\n\r\n+ The FreeRTOS/Source directory contains the three files that are common to \r\nevery port - list.c, queue.c and tasks.c.  The kernel is contained within these \r\nthree files.  croutine.c implements the optional co-routine functionality - which\r\nis normally only used on very memory limited systems.\r\n\r\n+ The FreeRTOS/Source/Portable directory contains the files that are specific to \r\na particular microcontroller and or compiler.\r\n\r\n+ The FreeRTOS/Source/include directory contains the real time kernel header \r\nfiles.\r\n\r\nSee the readme file in the FreeRTOS/Source/Portable directory for more \r\ninformation."
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RTOS/src/semphr.h",
    "content": "/*\r\n    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r\n    All rights reserved\r\n\r\n    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r\n\r\n    This file is part of the FreeRTOS distribution.\r\n\r\n    FreeRTOS is free software; you can redistribute it and/or modify it under\r\n    the terms of the GNU General Public License (version 2) as published by the\r\n    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r\n\r\n    ***************************************************************************\r\n    >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r\n    >>!   distribute a combined work that includes FreeRTOS without being   !<<\r\n    >>!   obliged to provide the source code for proprietary components     !<<\r\n    >>!   outside of the FreeRTOS kernel.                                   !<<\r\n    ***************************************************************************\r\n\r\n    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r\n    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r\n    FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r\n    link: http://www.freertos.org/a00114.html\r\n\r\n    ***************************************************************************\r\n     *                                                                       *\r\n     *    FreeRTOS provides completely free yet professionally developed,    *\r\n     *    robust, strictly quality controlled, supported, and cross          *\r\n     *    platform software that is more than just the market leader, it     *\r\n     *    is the industry's de facto standard.                               *\r\n     *                                                                       *\r\n     *    Help yourself get started quickly while simultaneously helping     *\r\n     *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r\n     *    tutorial book, reference manual, or both:                          *\r\n     *    http://www.FreeRTOS.org/Documentation                              *\r\n     *                                                                       *\r\n    ***************************************************************************\r\n\r\n    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r\n    the FAQ page \"My application does not run, what could be wrong?\".  Have you\r\n    defined configASSERT()?\r\n\r\n    http://www.FreeRTOS.org/support - In return for receiving this top quality\r\n    embedded software for free we request you assist our global community by\r\n    participating in the support forum.\r\n\r\n    http://www.FreeRTOS.org/training - Investing in training allows your team to\r\n    be as productive as possible as early as possible.  Now you can receive\r\n    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r\n    Ltd, and the world's leading authority on the world's leading RTOS.\r\n\r\n    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r\n    including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r\n    compatible FAT file system, and our tiny thread aware UDP/IP stack.\r\n\r\n    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r\n    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r\n\r\n    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r\n    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r\n    licenses offer ticketed support, indemnification and commercial middleware.\r\n\r\n    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r\n    engineered and independently SIL3 certified version for use in safety and\r\n    mission critical applications that require provable dependability.\r\n\r\n    1 tab == 4 spaces!\r\n*/\r\n\r\n#ifndef SEMAPHORE_H\r\n#define SEMAPHORE_H\r\n\r\n#ifndef INC_FREERTOS_H\r\n\t#error \"include FreeRTOS.h\" must appear in source files before \"include semphr.h\"\r\n#endif\r\n\r\n#include \"queue.h\"\r\n\r\ntypedef QueueHandle_t SemaphoreHandle_t;\r\n\r\n#define semBINARY_SEMAPHORE_QUEUE_LENGTH\t( ( uint8_t ) 1U )\r\n#define semSEMAPHORE_QUEUE_ITEM_LENGTH\t\t( ( uint8_t ) 0U )\r\n#define semGIVE_BLOCK_TIME\t\t\t\t\t( ( TickType_t ) 0U )\r\n\r\n\r\n/**\r\n * semphr. h\r\n * <pre>vSemaphoreCreateBinary( SemaphoreHandle_t xSemaphore )</pre>\r\n *\r\n * This old vSemaphoreCreateBinary() macro is now deprecated in favour of the\r\n * xSemaphoreCreateBinary() function.  Note that binary semaphores created using\r\n * the vSemaphoreCreateBinary() macro are created in a state such that the\r\n * first call to 'take' the semaphore would pass, whereas binary semaphores\r\n * created using xSemaphoreCreateBinary() are created in a state such that the\r\n * the semaphore must first be 'given' before it can be 'taken'.\r\n *\r\n * <i>Macro</i> that implements a semaphore by using the existing queue mechanism.\r\n * The queue length is 1 as this is a binary semaphore.  The data size is 0\r\n * as we don't want to actually store any data - we just want to know if the\r\n * queue is empty or full.\r\n *\r\n * This type of semaphore can be used for pure synchronisation between tasks or\r\n * between an interrupt and a task.  The semaphore need not be given back once\r\n * obtained, so one task/interrupt can continuously 'give' the semaphore while\r\n * another continuously 'takes' the semaphore.  For this reason this type of\r\n * semaphore does not use a priority inheritance mechanism.  For an alternative\r\n * that does use priority inheritance see xSemaphoreCreateMutex().\r\n *\r\n * @param xSemaphore Handle to the created semaphore.  Should be of type SemaphoreHandle_t.\r\n *\r\n * Example usage:\r\n <pre>\r\n SemaphoreHandle_t xSemaphore = NULL;\r\n\r\n void vATask( void * pvParameters )\r\n {\r\n    // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().\r\n    // This is a macro so pass the variable in directly.\r\n    vSemaphoreCreateBinary( xSemaphore );\r\n\r\n    if( xSemaphore != NULL )\r\n    {\r\n        // The semaphore was created successfully.\r\n        // The semaphore can now be used.\r\n    }\r\n }\r\n </pre>\r\n * \\defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary\r\n * \\ingroup Semaphores\r\n */\r\n#define vSemaphoreCreateBinary( xSemaphore )\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t( xSemaphore ) = xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE );\t\\\r\n\t\tif( ( xSemaphore ) != NULL )\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t\t( void ) xSemaphoreGive( ( xSemaphore ) );\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t}\r\n\r\n/**\r\n * semphr. h\r\n * <pre>SemaphoreHandle_t xSemaphoreCreateBinary( void )</pre>\r\n *\r\n * The old vSemaphoreCreateBinary() macro is now deprecated in favour of this\r\n * xSemaphoreCreateBinary() function.  Note that binary semaphores created using\r\n * the vSemaphoreCreateBinary() macro are created in a state such that the\r\n * first call to 'take' the semaphore would pass, whereas binary semaphores\r\n * created using xSemaphoreCreateBinary() are created in a state such that the\r\n * the semaphore must first be 'given' before it can be 'taken'.\r\n *\r\n * Function that creates a semaphore by using the existing queue mechanism.\r\n * The queue length is 1 as this is a binary semaphore.  The data size is 0\r\n * as nothing is actually stored - all that is important is whether the queue is\r\n * empty or full (the binary semaphore is available or not).\r\n *\r\n * This type of semaphore can be used for pure synchronisation between tasks or\r\n * between an interrupt and a task.  The semaphore need not be given back once\r\n * obtained, so one task/interrupt can continuously 'give' the semaphore while\r\n * another continuously 'takes' the semaphore.  For this reason this type of\r\n * semaphore does not use a priority inheritance mechanism.  For an alternative\r\n * that does use priority inheritance see xSemaphoreCreateMutex().\r\n *\r\n * @return Handle to the created semaphore.\r\n *\r\n * Example usage:\r\n <pre>\r\n SemaphoreHandle_t xSemaphore = NULL;\r\n\r\n void vATask( void * pvParameters )\r\n {\r\n    // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().\r\n    // This is a macro so pass the variable in directly.\r\n    xSemaphore = xSemaphoreCreateBinary();\r\n\r\n    if( xSemaphore != NULL )\r\n    {\r\n        // The semaphore was created successfully.\r\n        // The semaphore can now be used.\r\n    }\r\n }\r\n </pre>\r\n * \\defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary\r\n * \\ingroup Semaphores\r\n */\r\n#define xSemaphoreCreateBinary() xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE )\r\n\r\n/**\r\n * semphr. h\r\n * <pre>xSemaphoreTake(\r\n *                   SemaphoreHandle_t xSemaphore,\r\n *                   TickType_t xBlockTime\r\n *               )</pre>\r\n *\r\n * <i>Macro</i> to obtain a semaphore.  The semaphore must have previously been\r\n * created with a call to vSemaphoreCreateBinary(), xSemaphoreCreateMutex() or\r\n * xSemaphoreCreateCounting().\r\n *\r\n * @param xSemaphore A handle to the semaphore being taken - obtained when\r\n * the semaphore was created.\r\n *\r\n * @param xBlockTime The time in ticks to wait for the semaphore to become\r\n * available.  The macro portTICK_PERIOD_MS can be used to convert this to a\r\n * real time.  A block time of zero can be used to poll the semaphore.  A block\r\n * time of portMAX_DELAY can be used to block indefinitely (provided\r\n * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h).\r\n *\r\n * @return pdTRUE if the semaphore was obtained.  pdFALSE\r\n * if xBlockTime expired without the semaphore becoming available.\r\n *\r\n * Example usage:\r\n <pre>\r\n SemaphoreHandle_t xSemaphore = NULL;\r\n\r\n // A task that creates a semaphore.\r\n void vATask( void * pvParameters )\r\n {\r\n    // Create the semaphore to guard a shared resource.\r\n    vSemaphoreCreateBinary( xSemaphore );\r\n }\r\n\r\n // A task that uses the semaphore.\r\n void vAnotherTask( void * pvParameters )\r\n {\r\n    // ... Do other things.\r\n\r\n    if( xSemaphore != NULL )\r\n    {\r\n        // See if we can obtain the semaphore.  If the semaphore is not available\r\n        // wait 10 ticks to see if it becomes free.\r\n        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )\r\n        {\r\n            // We were able to obtain the semaphore and can now access the\r\n            // shared resource.\r\n\r\n            // ...\r\n\r\n            // We have finished accessing the shared resource.  Release the\r\n            // semaphore.\r\n            xSemaphoreGive( xSemaphore );\r\n        }\r\n        else\r\n        {\r\n            // We could not obtain the semaphore and can therefore not access\r\n            // the shared resource safely.\r\n        }\r\n    }\r\n }\r\n </pre>\r\n * \\defgroup xSemaphoreTake xSemaphoreTake\r\n * \\ingroup Semaphores\r\n */\r\n#define xSemaphoreTake( xSemaphore, xBlockTime )\t\txQueueGenericReceive( ( QueueHandle_t ) ( xSemaphore ), NULL, ( xBlockTime ), pdFALSE )\r\n\r\n/**\r\n * semphr. h\r\n * xSemaphoreTakeRecursive(\r\n *                          SemaphoreHandle_t xMutex,\r\n *                          TickType_t xBlockTime\r\n *                        )\r\n *\r\n * <i>Macro</i> to recursively obtain, or 'take', a mutex type semaphore.\r\n * The mutex must have previously been created using a call to\r\n * xSemaphoreCreateRecursiveMutex();\r\n *\r\n * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this\r\n * macro to be available.\r\n *\r\n * This macro must not be used on mutexes created using xSemaphoreCreateMutex().\r\n *\r\n * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex\r\n * doesn't become available again until the owner has called\r\n * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,\r\n * if a task successfully 'takes' the same mutex 5 times then the mutex will\r\n * not be available to any other task until it has also  'given' the mutex back\r\n * exactly five times.\r\n *\r\n * @param xMutex A handle to the mutex being obtained.  This is the\r\n * handle returned by xSemaphoreCreateRecursiveMutex();\r\n *\r\n * @param xBlockTime The time in ticks to wait for the semaphore to become\r\n * available.  The macro portTICK_PERIOD_MS can be used to convert this to a\r\n * real time.  A block time of zero can be used to poll the semaphore.  If\r\n * the task already owns the semaphore then xSemaphoreTakeRecursive() will\r\n * return immediately no matter what the value of xBlockTime.\r\n *\r\n * @return pdTRUE if the semaphore was obtained.  pdFALSE if xBlockTime\r\n * expired without the semaphore becoming available.\r\n *\r\n * Example usage:\r\n <pre>\r\n SemaphoreHandle_t xMutex = NULL;\r\n\r\n // A task that creates a mutex.\r\n void vATask( void * pvParameters )\r\n {\r\n    // Create the mutex to guard a shared resource.\r\n    xMutex = xSemaphoreCreateRecursiveMutex();\r\n }\r\n\r\n // A task that uses the mutex.\r\n void vAnotherTask( void * pvParameters )\r\n {\r\n    // ... Do other things.\r\n\r\n    if( xMutex != NULL )\r\n    {\r\n        // See if we can obtain the mutex.  If the mutex is not available\r\n        // wait 10 ticks to see if it becomes free.\r\n        if( xSemaphoreTakeRecursive( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )\r\n        {\r\n            // We were able to obtain the mutex and can now access the\r\n            // shared resource.\r\n\r\n            // ...\r\n            // For some reason due to the nature of the code further calls to\r\n\t\t\t// xSemaphoreTakeRecursive() are made on the same mutex.  In real\r\n\t\t\t// code these would not be just sequential calls as this would make\r\n\t\t\t// no sense.  Instead the calls are likely to be buried inside\r\n\t\t\t// a more complex call structure.\r\n            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );\r\n            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );\r\n\r\n            // The mutex has now been 'taken' three times, so will not be\r\n\t\t\t// available to another task until it has also been given back\r\n\t\t\t// three times.  Again it is unlikely that real code would have\r\n\t\t\t// these calls sequentially, but instead buried in a more complex\r\n\t\t\t// call structure.  This is just for illustrative purposes.\r\n            xSemaphoreGiveRecursive( xMutex );\r\n\t\t\txSemaphoreGiveRecursive( xMutex );\r\n\t\t\txSemaphoreGiveRecursive( xMutex );\r\n\r\n\t\t\t// Now the mutex can be taken by other tasks.\r\n        }\r\n        else\r\n        {\r\n            // We could not obtain the mutex and can therefore not access\r\n            // the shared resource safely.\r\n        }\r\n    }\r\n }\r\n </pre>\r\n * \\defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive\r\n * \\ingroup Semaphores\r\n */\r\n#define xSemaphoreTakeRecursive( xMutex, xBlockTime )\txQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) )\r\n\r\n\r\n/*\r\n * xSemaphoreAltTake() is an alternative version of xSemaphoreTake().\r\n *\r\n * The source code that implements the alternative (Alt) API is much\r\n * simpler\tbecause it executes everything from within a critical section.\r\n * This is\tthe approach taken by many other RTOSes, but FreeRTOS.org has the\r\n * preferred fully featured API too.  The fully featured API has more\r\n * complex\tcode that takes longer to execute, but makes much less use of\r\n * critical sections.  Therefore the alternative API sacrifices interrupt\r\n * responsiveness to gain execution speed, whereas the fully featured API\r\n * sacrifices execution speed to ensure better interrupt responsiveness.\r\n */\r\n#define xSemaphoreAltTake( xSemaphore, xBlockTime )\t\txQueueAltGenericReceive( ( QueueHandle_t ) ( xSemaphore ), NULL, ( xBlockTime ), pdFALSE )\r\n\r\n/**\r\n * semphr. h\r\n * <pre>xSemaphoreGive( SemaphoreHandle_t xSemaphore )</pre>\r\n *\r\n * <i>Macro</i> to release a semaphore.  The semaphore must have previously been\r\n * created with a call to vSemaphoreCreateBinary(), xSemaphoreCreateMutex() or\r\n * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake().\r\n *\r\n * This macro must not be used from an ISR.  See xSemaphoreGiveFromISR () for\r\n * an alternative which can be used from an ISR.\r\n *\r\n * This macro must also not be used on semaphores created using\r\n * xSemaphoreCreateRecursiveMutex().\r\n *\r\n * @param xSemaphore A handle to the semaphore being released.  This is the\r\n * handle returned when the semaphore was created.\r\n *\r\n * @return pdTRUE if the semaphore was released.  pdFALSE if an error occurred.\r\n * Semaphores are implemented using queues.  An error can occur if there is\r\n * no space on the queue to post a message - indicating that the\r\n * semaphore was not first obtained correctly.\r\n *\r\n * Example usage:\r\n <pre>\r\n SemaphoreHandle_t xSemaphore = NULL;\r\n\r\n void vATask( void * pvParameters )\r\n {\r\n    // Create the semaphore to guard a shared resource.\r\n    vSemaphoreCreateBinary( xSemaphore );\r\n\r\n    if( xSemaphore != NULL )\r\n    {\r\n        if( xSemaphoreGive( xSemaphore ) != pdTRUE )\r\n        {\r\n            // We would expect this call to fail because we cannot give\r\n            // a semaphore without first \"taking\" it!\r\n        }\r\n\r\n        // Obtain the semaphore - don't block if the semaphore is not\r\n        // immediately available.\r\n        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 0 ) )\r\n        {\r\n            // We now have the semaphore and can access the shared resource.\r\n\r\n            // ...\r\n\r\n            // We have finished accessing the shared resource so can free the\r\n            // semaphore.\r\n            if( xSemaphoreGive( xSemaphore ) != pdTRUE )\r\n            {\r\n                // We would not expect this call to fail because we must have\r\n                // obtained the semaphore to get here.\r\n            }\r\n        }\r\n    }\r\n }\r\n </pre>\r\n * \\defgroup xSemaphoreGive xSemaphoreGive\r\n * \\ingroup Semaphores\r\n */\r\n#define xSemaphoreGive( xSemaphore )\t\txQueueGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK )\r\n\r\n/**\r\n * semphr. h\r\n * <pre>xSemaphoreGiveRecursive( SemaphoreHandle_t xMutex )</pre>\r\n *\r\n * <i>Macro</i> to recursively release, or 'give', a mutex type semaphore.\r\n * The mutex must have previously been created using a call to\r\n * xSemaphoreCreateRecursiveMutex();\r\n *\r\n * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this\r\n * macro to be available.\r\n *\r\n * This macro must not be used on mutexes created using xSemaphoreCreateMutex().\r\n *\r\n * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex\r\n * doesn't become available again until the owner has called\r\n * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,\r\n * if a task successfully 'takes' the same mutex 5 times then the mutex will\r\n * not be available to any other task until it has also  'given' the mutex back\r\n * exactly five times.\r\n *\r\n * @param xMutex A handle to the mutex being released, or 'given'.  This is the\r\n * handle returned by xSemaphoreCreateMutex();\r\n *\r\n * @return pdTRUE if the semaphore was given.\r\n *\r\n * Example usage:\r\n <pre>\r\n SemaphoreHandle_t xMutex = NULL;\r\n\r\n // A task that creates a mutex.\r\n void vATask( void * pvParameters )\r\n {\r\n    // Create the mutex to guard a shared resource.\r\n    xMutex = xSemaphoreCreateRecursiveMutex();\r\n }\r\n\r\n // A task that uses the mutex.\r\n void vAnotherTask( void * pvParameters )\r\n {\r\n    // ... Do other things.\r\n\r\n    if( xMutex != NULL )\r\n    {\r\n        // See if we can obtain the mutex.  If the mutex is not available\r\n        // wait 10 ticks to see if it becomes free.\r\n        if( xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ) == pdTRUE )\r\n        {\r\n            // We were able to obtain the mutex and can now access the\r\n            // shared resource.\r\n\r\n            // ...\r\n            // For some reason due to the nature of the code further calls to\r\n\t\t\t// xSemaphoreTakeRecursive() are made on the same mutex.  In real\r\n\t\t\t// code these would not be just sequential calls as this would make\r\n\t\t\t// no sense.  Instead the calls are likely to be buried inside\r\n\t\t\t// a more complex call structure.\r\n            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );\r\n            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );\r\n\r\n            // The mutex has now been 'taken' three times, so will not be\r\n\t\t\t// available to another task until it has also been given back\r\n\t\t\t// three times.  Again it is unlikely that real code would have\r\n\t\t\t// these calls sequentially, it would be more likely that the calls\r\n\t\t\t// to xSemaphoreGiveRecursive() would be called as a call stack\r\n\t\t\t// unwound.  This is just for demonstrative purposes.\r\n            xSemaphoreGiveRecursive( xMutex );\r\n\t\t\txSemaphoreGiveRecursive( xMutex );\r\n\t\t\txSemaphoreGiveRecursive( xMutex );\r\n\r\n\t\t\t// Now the mutex can be taken by other tasks.\r\n        }\r\n        else\r\n        {\r\n            // We could not obtain the mutex and can therefore not access\r\n            // the shared resource safely.\r\n        }\r\n    }\r\n }\r\n </pre>\r\n * \\defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive\r\n * \\ingroup Semaphores\r\n */\r\n#define xSemaphoreGiveRecursive( xMutex )\txQueueGiveMutexRecursive( ( xMutex ) )\r\n\r\n/*\r\n * xSemaphoreAltGive() is an alternative version of xSemaphoreGive().\r\n *\r\n * The source code that implements the alternative (Alt) API is much\r\n * simpler\tbecause it executes everything from within a critical section.\r\n * This is\tthe approach taken by many other RTOSes, but FreeRTOS.org has the\r\n * preferred fully featured API too.  The fully featured API has more\r\n * complex\tcode that takes longer to execute, but makes much less use of\r\n * critical sections.  Therefore the alternative API sacrifices interrupt\r\n * responsiveness to gain execution speed, whereas the fully featured API\r\n * sacrifices execution speed to ensure better interrupt responsiveness.\r\n */\r\n#define xSemaphoreAltGive( xSemaphore )\t\txQueueAltGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK )\r\n\r\n/**\r\n * semphr. h\r\n * <pre>\r\n xSemaphoreGiveFromISR(\r\n                          SemaphoreHandle_t xSemaphore,\r\n                          BaseType_t *pxHigherPriorityTaskWoken\r\n                      )</pre>\r\n *\r\n * <i>Macro</i> to  release a semaphore.  The semaphore must have previously been\r\n * created with a call to vSemaphoreCreateBinary() or xSemaphoreCreateCounting().\r\n *\r\n * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())\r\n * must not be used with this macro.\r\n *\r\n * This macro can be used from an ISR.\r\n *\r\n * @param xSemaphore A handle to the semaphore being released.  This is the\r\n * handle returned when the semaphore was created.\r\n *\r\n * @param pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set\r\n * *pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task\r\n * to unblock, and the unblocked task has a priority higher than the currently\r\n * running task.  If xSemaphoreGiveFromISR() sets this value to pdTRUE then\r\n * a context switch should be requested before the interrupt is exited.\r\n *\r\n * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL.\r\n *\r\n * Example usage:\r\n <pre>\r\n \\#define LONG_TIME 0xffff\r\n \\#define TICKS_TO_WAIT\t10\r\n SemaphoreHandle_t xSemaphore = NULL;\r\n\r\n // Repetitive task.\r\n void vATask( void * pvParameters )\r\n {\r\n    for( ;; )\r\n    {\r\n        // We want this task to run every 10 ticks of a timer.  The semaphore\r\n        // was created before this task was started.\r\n\r\n        // Block waiting for the semaphore to become available.\r\n        if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )\r\n        {\r\n            // It is time to execute.\r\n\r\n            // ...\r\n\r\n            // We have finished our task.  Return to the top of the loop where\r\n            // we will block on the semaphore until it is time to execute\r\n            // again.  Note when using the semaphore for synchronisation with an\r\n\t\t\t// ISR in this manner there is no need to 'give' the semaphore back.\r\n        }\r\n    }\r\n }\r\n\r\n // Timer ISR\r\n void vTimerISR( void * pvParameters )\r\n {\r\n static uint8_t ucLocalTickCount = 0;\r\n static BaseType_t xHigherPriorityTaskWoken;\r\n\r\n    // A timer tick has occurred.\r\n\r\n    // ... Do other time functions.\r\n\r\n    // Is it time for vATask () to run?\r\n\txHigherPriorityTaskWoken = pdFALSE;\r\n    ucLocalTickCount++;\r\n    if( ucLocalTickCount >= TICKS_TO_WAIT )\r\n    {\r\n        // Unblock the task by releasing the semaphore.\r\n        xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken );\r\n\r\n        // Reset the count so we release the semaphore again in 10 ticks time.\r\n        ucLocalTickCount = 0;\r\n    }\r\n\r\n    if( xHigherPriorityTaskWoken != pdFALSE )\r\n    {\r\n        // We can force a context switch here.  Context switching from an\r\n        // ISR uses port specific syntax.  Check the demo task for your port\r\n        // to find the syntax required.\r\n    }\r\n }\r\n </pre>\r\n * \\defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR\r\n * \\ingroup Semaphores\r\n */\r\n#define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken )\txQueueGiveFromISR( ( QueueHandle_t ) ( xSemaphore ), ( pxHigherPriorityTaskWoken ) )\r\n\r\n/**\r\n * semphr. h\r\n * <pre>\r\n xSemaphoreTakeFromISR(\r\n                          SemaphoreHandle_t xSemaphore,\r\n                          BaseType_t *pxHigherPriorityTaskWoken\r\n                      )</pre>\r\n *\r\n * <i>Macro</i> to  take a semaphore from an ISR.  The semaphore must have\r\n * previously been created with a call to vSemaphoreCreateBinary() or\r\n * xSemaphoreCreateCounting().\r\n *\r\n * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())\r\n * must not be used with this macro.\r\n *\r\n * This macro can be used from an ISR, however taking a semaphore from an ISR\r\n * is not a common operation.  It is likely to only be useful when taking a\r\n * counting semaphore when an interrupt is obtaining an object from a resource\r\n * pool (when the semaphore count indicates the number of resources available).\r\n *\r\n * @param xSemaphore A handle to the semaphore being taken.  This is the\r\n * handle returned when the semaphore was created.\r\n *\r\n * @param pxHigherPriorityTaskWoken xSemaphoreTakeFromISR() will set\r\n * *pxHigherPriorityTaskWoken to pdTRUE if taking the semaphore caused a task\r\n * to unblock, and the unblocked task has a priority higher than the currently\r\n * running task.  If xSemaphoreTakeFromISR() sets this value to pdTRUE then\r\n * a context switch should be requested before the interrupt is exited.\r\n *\r\n * @return pdTRUE if the semaphore was successfully taken, otherwise\r\n * pdFALSE\r\n */\r\n#define xSemaphoreTakeFromISR( xSemaphore, pxHigherPriorityTaskWoken )\txQueueReceiveFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ) )\r\n\r\n/**\r\n * semphr. h\r\n * <pre>SemaphoreHandle_t xSemaphoreCreateMutex( void )</pre>\r\n *\r\n * <i>Macro</i> that implements a mutex semaphore by using the existing queue\r\n * mechanism.\r\n *\r\n * Mutexes created using this macro can be accessed using the xSemaphoreTake()\r\n * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and\r\n * xSemaphoreGiveRecursive() macros should not be used.\r\n *\r\n * This type of semaphore uses a priority inheritance mechanism so a task\r\n * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the\r\n * semaphore it is no longer required.\r\n *\r\n * Mutex type semaphores cannot be used from within interrupt service routines.\r\n *\r\n * See vSemaphoreCreateBinary() for an alternative implementation that can be\r\n * used for pure synchronisation (where one task or interrupt always 'gives' the\r\n * semaphore and another always 'takes' the semaphore) and from within interrupt\r\n * service routines.\r\n *\r\n * @return xSemaphore Handle to the created mutex semaphore.  Should be of type\r\n *\t\tSemaphoreHandle_t.\r\n *\r\n * Example usage:\r\n <pre>\r\n SemaphoreHandle_t xSemaphore;\r\n\r\n void vATask( void * pvParameters )\r\n {\r\n    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().\r\n    // This is a macro so pass the variable in directly.\r\n    xSemaphore = xSemaphoreCreateMutex();\r\n\r\n    if( xSemaphore != NULL )\r\n    {\r\n        // The semaphore was created successfully.\r\n        // The semaphore can now be used.\r\n    }\r\n }\r\n </pre>\r\n * \\defgroup vSemaphoreCreateMutex vSemaphoreCreateMutex\r\n * \\ingroup Semaphores\r\n */\r\n#define xSemaphoreCreateMutex() xQueueCreateMutex( queueQUEUE_TYPE_MUTEX )\r\n\r\n\r\n/**\r\n * semphr. h\r\n * <pre>SemaphoreHandle_t xSemaphoreCreateRecursiveMutex( void )</pre>\r\n *\r\n * <i>Macro</i> that implements a recursive mutex by using the existing queue\r\n * mechanism.\r\n *\r\n * Mutexes created using this macro can be accessed using the\r\n * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The\r\n * xSemaphoreTake() and xSemaphoreGive() macros should not be used.\r\n *\r\n * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex\r\n * doesn't become available again until the owner has called\r\n * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,\r\n * if a task successfully 'takes' the same mutex 5 times then the mutex will\r\n * not be available to any other task until it has also  'given' the mutex back\r\n * exactly five times.\r\n *\r\n * This type of semaphore uses a priority inheritance mechanism so a task\r\n * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the\r\n * semaphore it is no longer required.\r\n *\r\n * Mutex type semaphores cannot be used from within interrupt service routines.\r\n *\r\n * See vSemaphoreCreateBinary() for an alternative implementation that can be\r\n * used for pure synchronisation (where one task or interrupt always 'gives' the\r\n * semaphore and another always 'takes' the semaphore) and from within interrupt\r\n * service routines.\r\n *\r\n * @return xSemaphore Handle to the created mutex semaphore.  Should be of type\r\n *\t\tSemaphoreHandle_t.\r\n *\r\n * Example usage:\r\n <pre>\r\n SemaphoreHandle_t xSemaphore;\r\n\r\n void vATask( void * pvParameters )\r\n {\r\n    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().\r\n    // This is a macro so pass the variable in directly.\r\n    xSemaphore = xSemaphoreCreateRecursiveMutex();\r\n\r\n    if( xSemaphore != NULL )\r\n    {\r\n        // The semaphore was created successfully.\r\n        // The semaphore can now be used.\r\n    }\r\n }\r\n </pre>\r\n * \\defgroup vSemaphoreCreateMutex vSemaphoreCreateMutex\r\n * \\ingroup Semaphores\r\n */\r\n#define xSemaphoreCreateRecursiveMutex() xQueueCreateMutex( queueQUEUE_TYPE_RECURSIVE_MUTEX )\r\n\r\n/**\r\n * semphr. h\r\n * <pre>SemaphoreHandle_t xSemaphoreCreateCounting( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount )</pre>\r\n *\r\n * <i>Macro</i> that creates a counting semaphore by using the existing\r\n * queue mechanism.\r\n *\r\n * Counting semaphores are typically used for two things:\r\n *\r\n * 1) Counting events.\r\n *\r\n *    In this usage scenario an event handler will 'give' a semaphore each time\r\n *    an event occurs (incrementing the semaphore count value), and a handler\r\n *    task will 'take' a semaphore each time it processes an event\r\n *    (decrementing the semaphore count value).  The count value is therefore\r\n *    the difference between the number of events that have occurred and the\r\n *    number that have been processed.  In this case it is desirable for the\r\n *    initial count value to be zero.\r\n *\r\n * 2) Resource management.\r\n *\r\n *    In this usage scenario the count value indicates the number of resources\r\n *    available.  To obtain control of a resource a task must first obtain a\r\n *    semaphore - decrementing the semaphore count value.  When the count value\r\n *    reaches zero there are no free resources.  When a task finishes with the\r\n *    resource it 'gives' the semaphore back - incrementing the semaphore count\r\n *    value.  In this case it is desirable for the initial count value to be\r\n *    equal to the maximum count value, indicating that all resources are free.\r\n *\r\n * @param uxMaxCount The maximum count value that can be reached.  When the\r\n *        semaphore reaches this value it can no longer be 'given'.\r\n *\r\n * @param uxInitialCount The count value assigned to the semaphore when it is\r\n *        created.\r\n *\r\n * @return Handle to the created semaphore.  Null if the semaphore could not be\r\n *         created.\r\n *\r\n * Example usage:\r\n <pre>\r\n SemaphoreHandle_t xSemaphore;\r\n\r\n void vATask( void * pvParameters )\r\n {\r\n SemaphoreHandle_t xSemaphore = NULL;\r\n\r\n    // Semaphore cannot be used before a call to xSemaphoreCreateCounting().\r\n    // The max value to which the semaphore can count should be 10, and the\r\n    // initial value assigned to the count should be 0.\r\n    xSemaphore = xSemaphoreCreateCounting( 10, 0 );\r\n\r\n    if( xSemaphore != NULL )\r\n    {\r\n        // The semaphore was created successfully.\r\n        // The semaphore can now be used.\r\n    }\r\n }\r\n </pre>\r\n * \\defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting\r\n * \\ingroup Semaphores\r\n */\r\n#define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ) xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) )\r\n\r\n/**\r\n * semphr. h\r\n * <pre>void vSemaphoreDelete( SemaphoreHandle_t xSemaphore );</pre>\r\n *\r\n * Delete a semaphore.  This function must be used with care.  For example,\r\n * do not delete a mutex type semaphore if the mutex is held by a task.\r\n *\r\n * @param xSemaphore A handle to the semaphore to be deleted.\r\n *\r\n * \\defgroup vSemaphoreDelete vSemaphoreDelete\r\n * \\ingroup Semaphores\r\n */\r\n#define vSemaphoreDelete( xSemaphore ) vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) )\r\n\r\n/**\r\n * semphr.h\r\n * <pre>TaskHandle_t xSemaphoreGetMutexHolder( SemaphoreHandle_t xMutex );</pre>\r\n *\r\n * If xMutex is indeed a mutex type semaphore, return the current mutex holder.\r\n * If xMutex is not a mutex type semaphore, or the mutex is available (not held\r\n * by a task), return NULL.\r\n *\r\n * Note: This is a good way of determining if the calling task is the mutex\r\n * holder, but not a good way of determining the identity of the mutex holder as\r\n * the holder may change between the function exiting and the returned value\r\n * being tested.\r\n */\r\n#define xSemaphoreGetMutexHolder( xSemaphore ) xQueueGetMutexHolder( ( xSemaphore ) )\r\n\r\n#endif /* SEMAPHORE_H */\r\n\r\n\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RTOS/src/st_readme.txt",
    "content": "\r\n  @verbatim\r\n  ******************************************************************************\r\n  *\r\n  *           Portions COPYRIGHT 2015 STMicroelectronics\r\n  *           Portions Copyright (C) 2015 Real Time Engineers Ltd, All rights reserved\r\n  *\r\n  * @file    st_readme.txt \r\n  * @author  MCD Application Team\r\n  * @brief   This file lists the main modification done by STMicroelectronics on\r\n  *          FreeRTOS for integration with STM32Cube solution.\r\n  *          For more details on FreeRTOS implementation on STM32Cube, please refer \r\n  *          to UM1722 \"Developing Applications on STM32Cube with FreeRTOS\"  \r\n  ******************************************************************************\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  @endverbatim\r\n\r\n### 27-March-2015 ###\r\n=====================\r\n  The purpose of this release is to Upgrade to use FreeRTOS V8.2.1.\r\n\r\n  + Major change of the version 8.2.1 is the support of CM7 core. \r\n  For STM32F746xx/STM32F756xx devices, need to use port files under Source/Portable/XXX/ARM_CM7/r0p1,\r\n  where XXX refers to the compiler used.\r\n\r\n  + It also provides implementation of osSignal management APIs, osSignalSet() and osSignalWait(),\r\n  fixes osMassage queue size, osMailQDef macro and osDelayUntil parameters.\r\n  \r\n  + In this release an alignment has been done in ARM_CM4 and ARM_CM3 port.c versus ARM_CM0 port.c \r\n  regarding the use of macros configPRE_SLEEP_PROCESSING and configPOST_SLEEP_PROCESSING, these tow macros\r\n  are now taking as parameter as pointer to TickType_t.  \r\n\r\n  + cmsis_os.c\r\n    - Add implementation of osSignalSet() and osSignalWait() APIs\r\n    - Fix massage queue size in osMessageCreate API\r\n    - osDelayUntil: parameter PreviousWakeTime is now passed as a pointer. \r\n    - Enabling Mail queue management APIs (temporary removed in previous version).\r\n    - Function \"osThreadGetPriority\" uses now uxTaskPriorityGetFromISR if called from an interrupt handler, if not use uxTaskPriorityGet.\r\n\r\n  + cmsis_os.h\r\n    - osFeature_Wait is defined to 0 to indicate that osWait function is not available (as specified by cmsis_os template by ARM)  \r\n    - Fix compilation issue with osMailQDef macro.\r\n    - Enabling Mail queue management APIs (temporary removed in previous version)\r\n\r\n  + freeRTOS sources : \r\n    - ARM_CM3 port.c and ARM_CM4 port.c:\r\n      function vPortSuppressTicksAndSleep : configPRE_SLEEP_PROCESSING and configPOST_SLEEP_PROCESSING are now taking\r\n      as parameter as pointer to TickType_t.\r\n      The purpose of this change is to align the CM3 and CM4 implementation with CM0 one.       \r\n\r\n  + Note :\r\n    - osSignalSet returns an int32_t value which is a a status (osOK or osError) \r\n      instead of the previous signal value as specified in cmsis_os template by ARM. \r\n      This is mainly due to freeRTOS implementation, the return value will be aligned (with the cmsis os template by ARM) as soon as the freeRTOS next version will allow it.\r\n\r\n    - osThreadDef() macro is defined in the freeRTOS cmsis_os.h wrapper as follow : \r\n        osThreadDef(name, thread, priority, instances, stacksz)\r\n      the macro osThreadDef() as defined in ARM cmsis_os.h is defined with 4 parameters :\r\n      name : name of the thread function. \r\n      priority : initial priority of the thread function.\r\n      instances : number of possible thread instances.\r\n      stacksz : stack size (in bytes) requirements for the thread function.\r\n      \r\n    - osThreadDef as defined in the ARM template file cmsis_os.h assumes that the thread name is the same as the thread function name.\r\n      where the freeRTOS implementation gives separate parameters for the thread name and the thread function name.\r\n      \r\n      care must be taken when porting an application from/to another OS to/from freeRTOS cmsis_os regarding this macro.\r\n      \r\n        the macro osThreadDef() as defined in ARM cmsis_os.h template is defined with 4 parameters :\r\n           name : name of the thread function.\r\n           priority : initial priority of the thread function.\r\n           instances : number of possible thread instances.\r\n           stacksz : stack size (in bytes) requirements for the thread function.\r\n        \r\n        the macro osThreadDef() as defined in freeRTOS cmsis_os.h is defined with 5 parameters :\r\n           name : name of the thread (used for debugging and trace).\r\n           thread : name of the thread function\r\n           priority : initial priority of the thread function.\r\n           instances : number of possible thread instances.\r\n           stacksz : stack size (in bytes) requirements for the thread function.\r\n\r\n\r\n### 25-December-2014 ###\r\n========================\r\n  The purpose of this release is to remove compilation errors and warning. It also reintroduces\r\n  the function osThreadIsSuspended() which has been removed in the version V1.2.0.\r\n\r\n  + cmsis_os.c\r\n      - osThreadGetPriority() and makeCmsisPriority(): replace INCLUDE_vTaskPriorityGet by the correct\r\n         freeRTOS constant uxTaskPriorityGet.\r\n         The version 1.2.2 is using a wrong constant INCLUDE_vTaskPriorityGet, while the correct freeRTOS\r\n         constant is uxTaskPriorityGet.\r\n         This fix ensure a safe use of osThreadGetPriority() function.\r\n\r\n      - osThreadIsSuspended(): this function has been removed in version V1.2.0, it is now available gain.\r\n         User can either use this function to check if a Thread is suspended either use function osThreadGetState,\r\n         which is more generic, to check the exact state of a thread.\r\n                                               \r\n      - osThreadList(): this function is now taking as argument a pointer to uint8_t instead of a pointer to int8_t.\r\n         The change is made to remove a compilation warning.\r\n\r\n      - osRecursiveMutexCreate(): the prototype has been changed to osMutexId osRecursiveMutexCreate (const osMutexDef_t *mutex_def)\r\n          This change is made to make osRecursiveMutexCreate() compatible with function MutexCreate().\r\n          It also allow the better use of the function in conjunction with the macro osMutex, note that osMutex return a\r\n          \"const osMutexDef_t *mutex_def\".\r\n          example : osMutex1Id = osRecursiveMutexCreate (osMutex(Mutex1));\r\n\r\n      - Fix implementation of functions osSemaphoreWait(), osMutexRelease() and osMutexWait() by using the appropriate\r\n         freeRTOS FromISR APIs when called from an interrupt.\r\n\r\n      - Fix compilation warning when the constant INCLUDE_eTaskGetState is not defined\r\n\r\n  + cmsis_os.h\r\n      - osThreadIsSuspended(): add function prototype.\r\n      - osThreadList(): function prototype modified as described in cmsis_os.c section.\r\n      - osRecursiveMutexCreate(): function modified as described in cmsis_os.c section.\r\n\r\n  + Important note:\r\n    Mail Queue Management Functions are not supported in this cmsis_os version, will be added in the next release.\r\n\r\n\r\n### 04-December-2014 ###\r\n========================\r\n  + cmsis_os.c, osSemaphoreCreate(): use vSemaphoreCreateBinary() instead of xSemaphoreCreateBinary(),\r\n    to keep compatibility with application code developed on FreeRTOS V7.6.0.\r\n\r\n\r\n### 07-November-2014 ###\r\n========================\r\n  + cmsis_os.h: modify the osThreadState enum to fix warning generated by ARMCC compiler\r\n  + task.c: add preprocessor compilation condition for prvTaskIsTaskSuspended() function \r\n            (it's build only when INCLUDE_vTaskSuspend option is enabled in FreeRTOSConfig.h file)\r\n\r\n\r\n### 04-November-2014 ###\r\n========================\r\n  + Upgrade to use FreeRTOS V8.1.2 and CMSIS-RTOS V1.02.\r\n  + cmsis_os.c\r\n      - Almost of CMSIS-RTOS APIs are implemented for FreeRTOS\r\n      - Additional wrapper APIs created for FreeRTOS\r\n\r\n  + Important note:\r\n    When upgrading existing application code to use this last version, the following \r\n    update should be considered:\r\n      - osThreadIsSuspended() is no longer public API in FreeRTOS and it should\r\n        be replaced by the wrapping of eTaskGetState()\r\n      - osKernelStart() API changed, must be updated\r\n      - update FreeRTOSConfig.h file, taking FreeRTOSConfig_template.h file as reference\r\n\r\n\r\n### 13-June-2014 ###\r\n====================\r\n  + FreeRTOSConfig_template.h: add this definition #define INCLUDE_xTaskGetSchedulerState 1\r\n                               to enable the use of xTaskGetSchedulerState() API in the \r\n                               application code. \r\n\r\n\r\n### 30-April-2014 ###\r\n=====================\r\n  + cmsis_os.c: add preprocessor compilation condition when calling some FreeRTOS APIs, to avoid link\r\n                errors with MDK-ARM when some FreeRTOS features are not enabled in FreeRTOSConfig.h\r\n\r\n\r\n### 22-April-2014 ###\r\n=====================\r\n  + Add Tickles mode for CM0 port (IAR, GCC, RVDS).\r\n\r\n\r\n### 18-February-2014 ###\r\n========================\r\n   + FreeRTOS V7.6.0 customized version for STM32Cube solution.\r\n\r\n\r\n * <h3><center>&copy; COPYRIGHT STMicroelectronics</center></h3>\r\n */\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RTOS/src/stdint.readme",
    "content": "\r\n#ifndef FREERTOS_STDINT\r\n#define FREERTOS_STDINT\r\n\r\n/*******************************************************************************\r\n * THIS IS NOT A FULL stdint.h IMPLEMENTATION - It only contains the definitions\r\n * necessary to build the FreeRTOS code.  It is provided to allow FreeRTOS to be\r\n * built using compilers that do not provide their own stdint.h definition.\r\n *\r\n * To use this file:\r\n *\r\n *    1) Copy this file into the directory that contains your FreeRTOSConfig.h\r\n *       header file, as that directory will already be in the compilers include\r\n *       path.\r\n *\r\n *    2) Rename the copied file stdint.h.\r\n *\r\n */\r\n\r\ntypedef signed char int8_t;\r\ntypedef unsigned char uint8_t;\r\ntypedef short int16_t;\r\ntypedef unsigned short uint16_t;\r\ntypedef long int32_t;\r\ntypedef unsigned long uint32_t;\r\n\r\n#endif /* FREERTOS_STDINT */\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RTOS/src/task.h",
    "content": "/*\r\n    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r\n    All rights reserved\r\n\r\n    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r\n\r\n    This file is part of the FreeRTOS distribution.\r\n\r\n    FreeRTOS is free software; you can redistribute it and/or modify it under\r\n    the terms of the GNU General Public License (version 2) as published by the\r\n    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r\n\r\n    ***************************************************************************\r\n    >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r\n    >>!   distribute a combined work that includes FreeRTOS without being   !<<\r\n    >>!   obliged to provide the source code for proprietary components     !<<\r\n    >>!   outside of the FreeRTOS kernel.                                   !<<\r\n    ***************************************************************************\r\n\r\n    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r\n    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r\n    FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r\n    link: http://www.freertos.org/a00114.html\r\n\r\n    ***************************************************************************\r\n     *                                                                       *\r\n     *    FreeRTOS provides completely free yet professionally developed,    *\r\n     *    robust, strictly quality controlled, supported, and cross          *\r\n     *    platform software that is more than just the market leader, it     *\r\n     *    is the industry's de facto standard.                               *\r\n     *                                                                       *\r\n     *    Help yourself get started quickly while simultaneously helping     *\r\n     *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r\n     *    tutorial book, reference manual, or both:                          *\r\n     *    http://www.FreeRTOS.org/Documentation                              *\r\n     *                                                                       *\r\n    ***************************************************************************\r\n\r\n    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r\n    the FAQ page \"My application does not run, what could be wrong?\".  Have you\r\n    defined configASSERT()?\r\n\r\n    http://www.FreeRTOS.org/support - In return for receiving this top quality\r\n    embedded software for free we request you assist our global community by\r\n    participating in the support forum.\r\n\r\n    http://www.FreeRTOS.org/training - Investing in training allows your team to\r\n    be as productive as possible as early as possible.  Now you can receive\r\n    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r\n    Ltd, and the world's leading authority on the world's leading RTOS.\r\n\r\n    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r\n    including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r\n    compatible FAT file system, and our tiny thread aware UDP/IP stack.\r\n\r\n    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r\n    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r\n\r\n    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r\n    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r\n    licenses offer ticketed support, indemnification and commercial middleware.\r\n\r\n    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r\n    engineered and independently SIL3 certified version for use in safety and\r\n    mission critical applications that require provable dependability.\r\n\r\n    1 tab == 4 spaces!\r\n*/\r\n\r\n\r\n#ifndef INC_TASK_H\r\n#define INC_TASK_H\r\n\r\n#ifndef INC_FREERTOS_H\r\n\t#error \"include FreeRTOS.h must appear in source files before include task.h\"\r\n#endif\r\n\r\n#include \"list.h\"\r\n\r\n#ifdef __cplusplus\r\nextern \"C\" {\r\n#endif\r\n\r\n/*-----------------------------------------------------------\r\n * MACROS AND DEFINITIONS\r\n *----------------------------------------------------------*/\r\n\r\n#define tskKERNEL_VERSION_NUMBER \"V8.2.1\"\r\n#define tskKERNEL_VERSION_MAJOR 8\r\n#define tskKERNEL_VERSION_MINOR 2\r\n#define tskKERNEL_VERSION_BUILD 1\r\n\r\n/**\r\n * task. h\r\n *\r\n * Type by which tasks are referenced.  For example, a call to xTaskCreate\r\n * returns (via a pointer parameter) an TaskHandle_t variable that can then\r\n * be used as a parameter to vTaskDelete to delete the task.\r\n *\r\n * \\defgroup TaskHandle_t TaskHandle_t\r\n * \\ingroup Tasks\r\n */\r\ntypedef void * TaskHandle_t;\r\n\r\n/*\r\n * Defines the prototype to which the application task hook function must\r\n * conform.\r\n */\r\ntypedef BaseType_t (*TaskHookFunction_t)( void * );\r\n\r\n/* Task states returned by eTaskGetState. */\r\ntypedef enum\r\n{\r\n\teRunning = 0,\t/* A task is querying the state of itself, so must be running. */\r\n\teReady,\t\t\t/* The task being queried is in a read or pending ready list. */\r\n\teBlocked,\t\t/* The task being queried is in the Blocked state. */\r\n\teSuspended,\t\t/* The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */\r\n\teDeleted\t\t/* The task being queried has been deleted, but its TCB has not yet been freed. */\r\n} eTaskState;\r\n\r\n/* Actions that can be performed when vTaskNotify() is called. */\r\ntypedef enum\r\n{\r\n\teNoAction = 0,\t\t\t\t/* Notify the task without updating its notify value. */\r\n\teSetBits,\t\t\t\t\t/* Set bits in the task's notification value. */\r\n\teIncrement,\t\t\t\t\t/* Increment the task's notification value. */\r\n\teSetValueWithOverwrite,\t\t/* Set the task's notification value to a specific value even if the previous value has not yet been read by the task. */\r\n\teSetValueWithoutOverwrite\t/* Set the task's notification value if the previous value has been read by the task. */\r\n} eNotifyAction;\r\n\r\n/*\r\n * Used internally only.\r\n */\r\ntypedef struct xTIME_OUT\r\n{\r\n\tBaseType_t xOverflowCount;\r\n\tTickType_t xTimeOnEntering;\r\n} TimeOut_t;\r\n\r\n/*\r\n * Defines the memory ranges allocated to the task when an MPU is used.\r\n */\r\ntypedef struct xMEMORY_REGION\r\n{\r\n\tvoid *pvBaseAddress;\r\n\tuint32_t ulLengthInBytes;\r\n\tuint32_t ulParameters;\r\n} MemoryRegion_t;\r\n\r\n/*\r\n * Parameters required to create an MPU protected task.\r\n */\r\ntypedef struct xTASK_PARAMETERS\r\n{\r\n\tTaskFunction_t pvTaskCode;\r\n\tconst char * const pcName;\t/*lint !e971 Unqualified char types are allowed for strings and single characters only. */\r\n\tuint16_t usStackDepth;\r\n\tvoid *pvParameters;\r\n\tUBaseType_t uxPriority;\r\n\tStackType_t *puxStackBuffer;\r\n\tMemoryRegion_t xRegions[ portNUM_CONFIGURABLE_REGIONS ];\r\n} TaskParameters_t;\r\n\r\n/* Used with the uxTaskGetSystemState() function to return the state of each task\r\nin the system. */\r\ntypedef struct xTASK_STATUS\r\n{\r\n\tTaskHandle_t xHandle;\t\t\t/* The handle of the task to which the rest of the information in the structure relates. */\r\n\tconst char *pcTaskName;\t\t\t/* A pointer to the task's name.  This value will be invalid if the task was deleted since the structure was populated! */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\r\n\tUBaseType_t xTaskNumber;\t\t/* A number unique to the task. */\r\n\teTaskState eCurrentState;\t\t/* The state in which the task existed when the structure was populated. */\r\n\tUBaseType_t uxCurrentPriority;\t/* The priority at which the task was running (may be inherited) when the structure was populated. */\r\n\tUBaseType_t uxBasePriority;\t\t/* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex.  Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */\r\n\tuint32_t ulRunTimeCounter;\t\t/* The total run time allocated to the task so far, as defined by the run time stats clock.  See http://www.freertos.org/rtos-run-time-stats.html.  Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */\r\n\tuint16_t usStackHighWaterMark;\t/* The minimum amount of stack space that has remained for the task since the task was created.  The closer this value is to zero the closer the task has come to overflowing its stack. */\r\n} TaskStatus_t;\r\n\r\n/* Possible return values for eTaskConfirmSleepModeStatus(). */\r\ntypedef enum\r\n{\r\n\teAbortSleep = 0,\t\t/* A task has been made ready or a context switch pended since portSUPPORESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */\r\n\teStandardSleep,\t\t\t/* Enter a sleep mode that will not last any longer than the expected idle time. */\r\n\teNoTasksWaitingTimeout\t/* No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt. */\r\n} eSleepModeStatus;\r\n\r\n\r\n/**\r\n * Defines the priority used by the idle task.  This must not be modified.\r\n *\r\n * \\ingroup TaskUtils\r\n */\r\n#define tskIDLE_PRIORITY\t\t\t( ( UBaseType_t ) 0U )\r\n\r\n/**\r\n * task. h\r\n *\r\n * Macro for forcing a context switch.\r\n *\r\n * \\defgroup taskYIELD taskYIELD\r\n * \\ingroup SchedulerControl\r\n */\r\n#define taskYIELD()\t\t\t\t\tportYIELD()\r\n\r\n/**\r\n * task. h\r\n *\r\n * Macro to mark the start of a critical code region.  Preemptive context\r\n * switches cannot occur when in a critical region.\r\n *\r\n * NOTE: This may alter the stack (depending on the portable implementation)\r\n * so must be used with care!\r\n *\r\n * \\defgroup taskENTER_CRITICAL taskENTER_CRITICAL\r\n * \\ingroup SchedulerControl\r\n */\r\n#define taskENTER_CRITICAL()\t\tportENTER_CRITICAL()\r\n#define taskENTER_CRITICAL_FROM_ISR( x ) portSET_INTERRUPT_MASK_FROM_ISR( x )\r\n\r\n/**\r\n * task. h\r\n *\r\n * Macro to mark the end of a critical code region.  Preemptive context\r\n * switches cannot occur when in a critical region.\r\n *\r\n * NOTE: This may alter the stack (depending on the portable implementation)\r\n * so must be used with care!\r\n *\r\n * \\defgroup taskEXIT_CRITICAL taskEXIT_CRITICAL\r\n * \\ingroup SchedulerControl\r\n */\r\n#define taskEXIT_CRITICAL()\t\t\tportEXIT_CRITICAL()\r\n#define taskEXIT_CRITICAL_FROM_ISR() portCLEAR_INTERRUPT_MASK_FROM_ISR()\r\n/**\r\n * task. h\r\n *\r\n * Macro to disable all maskable interrupts.\r\n *\r\n * \\defgroup taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS\r\n * \\ingroup SchedulerControl\r\n */\r\n#define taskDISABLE_INTERRUPTS()\tportDISABLE_INTERRUPTS()\r\n\r\n/**\r\n * task. h\r\n *\r\n * Macro to enable microcontroller interrupts.\r\n *\r\n * \\defgroup taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS\r\n * \\ingroup SchedulerControl\r\n */\r\n#define taskENABLE_INTERRUPTS()\t\tportENABLE_INTERRUPTS()\r\n\r\n/* Definitions returned by xTaskGetSchedulerState().  taskSCHEDULER_SUSPENDED is\r\n0 to generate more optimal code when configASSERT() is defined as the constant\r\nis used in assert() statements. */\r\n#define taskSCHEDULER_SUSPENDED\t\t( ( BaseType_t ) 0 )\r\n#define taskSCHEDULER_NOT_STARTED\t( ( BaseType_t ) 1 )\r\n#define taskSCHEDULER_RUNNING\t\t( ( BaseType_t ) 2 )\r\n\r\n\r\n/*-----------------------------------------------------------\r\n * TASK CREATION API\r\n *----------------------------------------------------------*/\r\n\r\n/**\r\n * task. h\r\n *<pre>\r\n BaseType_t xTaskCreate(\r\n\t\t\t\t\t\t\t  TaskFunction_t pvTaskCode,\r\n\t\t\t\t\t\t\t  const char * const pcName,\r\n\t\t\t\t\t\t\t  uint16_t usStackDepth,\r\n\t\t\t\t\t\t\t  void *pvParameters,\r\n\t\t\t\t\t\t\t  UBaseType_t uxPriority,\r\n\t\t\t\t\t\t\t  TaskHandle_t *pvCreatedTask\r\n\t\t\t\t\t\t  );</pre>\r\n *\r\n * Create a new task and add it to the list of tasks that are ready to run.\r\n *\r\n * xTaskCreate() can only be used to create a task that has unrestricted\r\n * access to the entire microcontroller memory map.  Systems that include MPU\r\n * support can alternatively create an MPU constrained task using\r\n * xTaskCreateRestricted().\r\n *\r\n * @param pvTaskCode Pointer to the task entry function.  Tasks\r\n * must be implemented to never return (i.e. continuous loop).\r\n *\r\n * @param pcName A descriptive name for the task.  This is mainly used to\r\n * facilitate debugging.  Max length defined by configMAX_TASK_NAME_LEN - default\r\n * is 16.\r\n *\r\n * @param usStackDepth The size of the task stack specified as the number of\r\n * variables the stack can hold - not the number of bytes.  For example, if\r\n * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes\r\n * will be allocated for stack storage.\r\n *\r\n * @param pvParameters Pointer that will be used as the parameter for the task\r\n * being created.\r\n *\r\n * @param uxPriority The priority at which the task should run.  Systems that\r\n * include MPU support can optionally create tasks in a privileged (system)\r\n * mode by setting bit portPRIVILEGE_BIT of the priority parameter.  For\r\n * example, to create a privileged task at priority 2 the uxPriority parameter\r\n * should be set to ( 2 | portPRIVILEGE_BIT ).\r\n *\r\n * @param pvCreatedTask Used to pass back a handle by which the created task\r\n * can be referenced.\r\n *\r\n * @return pdPASS if the task was successfully created and added to a ready\r\n * list, otherwise an error code defined in the file projdefs.h\r\n *\r\n * Example usage:\r\n   <pre>\r\n // Task to be created.\r\n void vTaskCode( void * pvParameters )\r\n {\r\n\t for( ;; )\r\n\t {\r\n\t\t // Task code goes here.\r\n\t }\r\n }\r\n\r\n // Function that creates a task.\r\n void vOtherFunction( void )\r\n {\r\n static uint8_t ucParameterToPass;\r\n TaskHandle_t xHandle = NULL;\r\n\r\n\t // Create the task, storing the handle.  Note that the passed parameter ucParameterToPass\r\n\t // must exist for the lifetime of the task, so in this case is declared static.  If it was just an\r\n\t // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time\r\n\t // the new task attempts to access it.\r\n\t xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );\r\n     configASSERT( xHandle );\r\n\r\n\t // Use the handle to delete the task.\r\n     if( xHandle != NULL )\r\n     {\r\n\t     vTaskDelete( xHandle );\r\n     }\r\n }\r\n   </pre>\r\n * \\defgroup xTaskCreate xTaskCreate\r\n * \\ingroup Tasks\r\n */\r\n#define xTaskCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask ) xTaskGenericCreate( ( pvTaskCode ), ( pcName ), ( usStackDepth ), ( pvParameters ), ( uxPriority ), ( pxCreatedTask ), ( NULL ), ( NULL ) )\r\n\r\n/**\r\n * task. h\r\n *<pre>\r\n BaseType_t xTaskCreateRestricted( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );</pre>\r\n *\r\n * xTaskCreateRestricted() should only be used in systems that include an MPU\r\n * implementation.\r\n *\r\n * Create a new task and add it to the list of tasks that are ready to run.\r\n * The function parameters define the memory regions and associated access\r\n * permissions allocated to the task.\r\n *\r\n * @param pxTaskDefinition Pointer to a structure that contains a member\r\n * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API\r\n * documentation) plus an optional stack buffer and the memory region\r\n * definitions.\r\n *\r\n * @param pxCreatedTask Used to pass back a handle by which the created task\r\n * can be referenced.\r\n *\r\n * @return pdPASS if the task was successfully created and added to a ready\r\n * list, otherwise an error code defined in the file projdefs.h\r\n *\r\n * Example usage:\r\n   <pre>\r\n// Create an TaskParameters_t structure that defines the task to be created.\r\nstatic const TaskParameters_t xCheckTaskParameters =\r\n{\r\n\tvATask,\t\t// pvTaskCode - the function that implements the task.\r\n\t\"ATask\",\t// pcName - just a text name for the task to assist debugging.\r\n\t100,\t\t// usStackDepth\t- the stack size DEFINED IN WORDS.\r\n\tNULL,\t\t// pvParameters - passed into the task function as the function parameters.\r\n\t( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.\r\n\tcStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.\r\n\r\n\t// xRegions - Allocate up to three separate memory regions for access by\r\n\t// the task, with appropriate access permissions.  Different processors have\r\n\t// different memory alignment requirements - refer to the FreeRTOS documentation\r\n\t// for full information.\r\n\t{\r\n\t\t// Base address\t\t\t\t\tLength\tParameters\r\n        { cReadWriteArray,\t\t\t\t32,\t\tportMPU_REGION_READ_WRITE },\r\n        { cReadOnlyArray,\t\t\t\t32,\t\tportMPU_REGION_READ_ONLY },\r\n        { cPrivilegedOnlyAccessArray,\t128,\tportMPU_REGION_PRIVILEGED_READ_WRITE }\r\n\t}\r\n};\r\n\r\nint main( void )\r\n{\r\nTaskHandle_t xHandle;\r\n\r\n\t// Create a task from the const structure defined above.  The task handle\r\n\t// is requested (the second parameter is not NULL) but in this case just for\r\n\t// demonstration purposes as its not actually used.\r\n\txTaskCreateRestricted( &xRegTest1Parameters, &xHandle );\r\n\r\n\t// Start the scheduler.\r\n\tvTaskStartScheduler();\r\n\r\n\t// Will only get here if there was insufficient memory to create the idle\r\n\t// and/or timer task.\r\n\tfor( ;; );\r\n}\r\n   </pre>\r\n * \\defgroup xTaskCreateRestricted xTaskCreateRestricted\r\n * \\ingroup Tasks\r\n */\r\n#define xTaskCreateRestricted( x, pxCreatedTask ) xTaskGenericCreate( ((x)->pvTaskCode), ((x)->pcName), ((x)->usStackDepth), ((x)->pvParameters), ((x)->uxPriority), (pxCreatedTask), ((x)->puxStackBuffer), ((x)->xRegions) )\r\n\r\n/**\r\n * task. h\r\n *<pre>\r\n void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );</pre>\r\n *\r\n * Memory regions are assigned to a restricted task when the task is created by\r\n * a call to xTaskCreateRestricted().  These regions can be redefined using\r\n * vTaskAllocateMPURegions().\r\n *\r\n * @param xTask The handle of the task being updated.\r\n *\r\n * @param xRegions A pointer to an MemoryRegion_t structure that contains the\r\n * new memory region definitions.\r\n *\r\n * Example usage:\r\n   <pre>\r\n// Define an array of MemoryRegion_t structures that configures an MPU region\r\n// allowing read/write access for 1024 bytes starting at the beginning of the\r\n// ucOneKByte array.  The other two of the maximum 3 definable regions are\r\n// unused so set to zero.\r\nstatic const MemoryRegion_t xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] =\r\n{\r\n\t// Base address\t\tLength\t\tParameters\r\n\t{ ucOneKByte,\t\t1024,\t\tportMPU_REGION_READ_WRITE },\r\n\t{ 0,\t\t\t\t0,\t\t\t0 },\r\n\t{ 0,\t\t\t\t0,\t\t\t0 }\r\n};\r\n\r\nvoid vATask( void *pvParameters )\r\n{\r\n\t// This task was created such that it has access to certain regions of\r\n\t// memory as defined by the MPU configuration.  At some point it is\r\n\t// desired that these MPU regions are replaced with that defined in the\r\n\t// xAltRegions const struct above.  Use a call to vTaskAllocateMPURegions()\r\n\t// for this purpose.  NULL is used as the task handle to indicate that this\r\n\t// function should modify the MPU regions of the calling task.\r\n\tvTaskAllocateMPURegions( NULL, xAltRegions );\r\n\r\n\t// Now the task can continue its function, but from this point on can only\r\n\t// access its stack and the ucOneKByte array (unless any other statically\r\n\t// defined or shared regions have been declared elsewhere).\r\n}\r\n   </pre>\r\n * \\defgroup xTaskCreateRestricted xTaskCreateRestricted\r\n * \\ingroup Tasks\r\n */\r\nvoid vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION;\r\n\r\n/**\r\n * task. h\r\n * <pre>void vTaskDelete( TaskHandle_t xTask );</pre>\r\n *\r\n * INCLUDE_vTaskDelete must be defined as 1 for this function to be available.\r\n * See the configuration section for more information.\r\n *\r\n * Remove a task from the RTOS real time kernel's management.  The task being\r\n * deleted will be removed from all ready, blocked, suspended and event lists.\r\n *\r\n * NOTE:  The idle task is responsible for freeing the kernel allocated\r\n * memory from tasks that have been deleted.  It is therefore important that\r\n * the idle task is not starved of microcontroller processing time if your\r\n * application makes any calls to vTaskDelete ().  Memory allocated by the\r\n * task code is not automatically freed, and should be freed before the task\r\n * is deleted.\r\n *\r\n * See the demo application file death.c for sample code that utilises\r\n * vTaskDelete ().\r\n *\r\n * @param xTask The handle of the task to be deleted.  Passing NULL will\r\n * cause the calling task to be deleted.\r\n *\r\n * Example usage:\r\n   <pre>\r\n void vOtherFunction( void )\r\n {\r\n TaskHandle_t xHandle;\r\n\r\n\t // Create the task, storing the handle.\r\n\t xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );\r\n\r\n\t // Use the handle to delete the task.\r\n\t vTaskDelete( xHandle );\r\n }\r\n   </pre>\r\n * \\defgroup vTaskDelete vTaskDelete\r\n * \\ingroup Tasks\r\n */\r\nvoid vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION;\r\n\r\n/*-----------------------------------------------------------\r\n * TASK CONTROL API\r\n *----------------------------------------------------------*/\r\n\r\n/**\r\n * task. h\r\n * <pre>void vTaskDelay( const TickType_t xTicksToDelay );</pre>\r\n *\r\n * Delay a task for a given number of ticks.  The actual time that the\r\n * task remains blocked depends on the tick rate.  The constant\r\n * portTICK_PERIOD_MS can be used to calculate real time from the tick\r\n * rate - with the resolution of one tick period.\r\n *\r\n * INCLUDE_vTaskDelay must be defined as 1 for this function to be available.\r\n * See the configuration section for more information.\r\n *\r\n *\r\n * vTaskDelay() specifies a time at which the task wishes to unblock relative to\r\n * the time at which vTaskDelay() is called.  For example, specifying a block\r\n * period of 100 ticks will cause the task to unblock 100 ticks after\r\n * vTaskDelay() is called.  vTaskDelay() does not therefore provide a good method\r\n * of controlling the frequency of a periodic task as the path taken through the\r\n * code, as well as other task and interrupt activity, will effect the frequency\r\n * at which vTaskDelay() gets called and therefore the time at which the task\r\n * next executes.  See vTaskDelayUntil() for an alternative API function designed\r\n * to facilitate fixed frequency execution.  It does this by specifying an\r\n * absolute time (rather than a relative time) at which the calling task should\r\n * unblock.\r\n *\r\n * @param xTicksToDelay The amount of time, in tick periods, that\r\n * the calling task should block.\r\n *\r\n * Example usage:\r\n\r\n void vTaskFunction( void * pvParameters )\r\n {\r\n // Block for 500ms.\r\n const TickType_t xDelay = 500 / portTICK_PERIOD_MS;\r\n\r\n\t for( ;; )\r\n\t {\r\n\t\t // Simply toggle the LED every 500ms, blocking between each toggle.\r\n\t\t vToggleLED();\r\n\t\t vTaskDelay( xDelay );\r\n\t }\r\n }\r\n\r\n * \\defgroup vTaskDelay vTaskDelay\r\n * \\ingroup TaskCtrl\r\n */\r\nvoid vTaskDelay( const TickType_t xTicksToDelay ) PRIVILEGED_FUNCTION;\r\n\r\n/**\r\n * task. h\r\n * <pre>void vTaskDelayUntil( TickType_t *pxPreviousWakeTime, const TickType_t xTimeIncrement );</pre>\r\n *\r\n * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available.\r\n * See the configuration section for more information.\r\n *\r\n * Delay a task until a specified time.  This function can be used by periodic\r\n * tasks to ensure a constant execution frequency.\r\n *\r\n * This function differs from vTaskDelay () in one important aspect:  vTaskDelay () will\r\n * cause a task to block for the specified number of ticks from the time vTaskDelay () is\r\n * called.  It is therefore difficult to use vTaskDelay () by itself to generate a fixed\r\n * execution frequency as the time between a task starting to execute and that task\r\n * calling vTaskDelay () may not be fixed [the task may take a different path though the\r\n * code between calls, or may get interrupted or preempted a different number of times\r\n * each time it executes].\r\n *\r\n * Whereas vTaskDelay () specifies a wake time relative to the time at which the function\r\n * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to\r\n * unblock.\r\n *\r\n * The constant portTICK_PERIOD_MS can be used to calculate real time from the tick\r\n * rate - with the resolution of one tick period.\r\n *\r\n * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the\r\n * task was last unblocked.  The variable must be initialised with the current time\r\n * prior to its first use (see the example below).  Following this the variable is\r\n * automatically updated within vTaskDelayUntil ().\r\n *\r\n * @param xTimeIncrement The cycle time period.  The task will be unblocked at\r\n * time *pxPreviousWakeTime + xTimeIncrement.  Calling vTaskDelayUntil with the\r\n * same xTimeIncrement parameter value will cause the task to execute with\r\n * a fixed interface period.\r\n *\r\n * Example usage:\r\n   <pre>\r\n // Perform an action every 10 ticks.\r\n void vTaskFunction( void * pvParameters )\r\n {\r\n TickType_t xLastWakeTime;\r\n const TickType_t xFrequency = 10;\r\n\r\n\t // Initialise the xLastWakeTime variable with the current time.\r\n\t xLastWakeTime = xTaskGetTickCount ();\r\n\t for( ;; )\r\n\t {\r\n\t\t // Wait for the next cycle.\r\n\t\t vTaskDelayUntil( &xLastWakeTime, xFrequency );\r\n\r\n\t\t // Perform action here.\r\n\t }\r\n }\r\n   </pre>\r\n * \\defgroup vTaskDelayUntil vTaskDelayUntil\r\n * \\ingroup TaskCtrl\r\n */\r\nvoid vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) PRIVILEGED_FUNCTION;\r\n\r\n/**\r\n * task. h\r\n * <pre>UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask );</pre>\r\n *\r\n * INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available.\r\n * See the configuration section for more information.\r\n *\r\n * Obtain the priority of any task.\r\n *\r\n * @param xTask Handle of the task to be queried.  Passing a NULL\r\n * handle results in the priority of the calling task being returned.\r\n *\r\n * @return The priority of xTask.\r\n *\r\n * Example usage:\r\n   <pre>\r\n void vAFunction( void )\r\n {\r\n TaskHandle_t xHandle;\r\n\r\n\t // Create a task, storing the handle.\r\n\t xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );\r\n\r\n\t // ...\r\n\r\n\t // Use the handle to obtain the priority of the created task.\r\n\t // It was created with tskIDLE_PRIORITY, but may have changed\r\n\t // it itself.\r\n\t if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )\r\n\t {\r\n\t\t // The task has changed it's priority.\r\n\t }\r\n\r\n\t // ...\r\n\r\n\t // Is our priority higher than the created task?\r\n\t if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )\r\n\t {\r\n\t\t // Our priority (obtained using NULL handle) is higher.\r\n\t }\r\n }\r\n   </pre>\r\n * \\defgroup uxTaskPriorityGet uxTaskPriorityGet\r\n * \\ingroup TaskCtrl\r\n */\r\nUBaseType_t uxTaskPriorityGet( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\r\n\r\n/**\r\n * task. h\r\n * <pre>UBaseType_t uxTaskPriorityGetFromISR( TaskHandle_t xTask );</pre>\r\n *\r\n * A version of uxTaskPriorityGet() that can be used from an ISR.\r\n */\r\nUBaseType_t uxTaskPriorityGetFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\r\n\r\n/**\r\n * task. h\r\n * <pre>eTaskState eTaskGetState( TaskHandle_t xTask );</pre>\r\n *\r\n * INCLUDE_eTaskGetState must be defined as 1 for this function to be available.\r\n * See the configuration section for more information.\r\n *\r\n * Obtain the state of any task.  States are encoded by the eTaskState\r\n * enumerated type.\r\n *\r\n * @param xTask Handle of the task to be queried.\r\n *\r\n * @return The state of xTask at the time the function was called.  Note the\r\n * state of the task might change between the function being called, and the\r\n * functions return value being tested by the calling task.\r\n */\r\neTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\r\n\r\n/**\r\n * task. h\r\n * <pre>void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );</pre>\r\n *\r\n * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available.\r\n * See the configuration section for more information.\r\n *\r\n * Set the priority of any task.\r\n *\r\n * A context switch will occur before the function returns if the priority\r\n * being set is higher than the currently executing task.\r\n *\r\n * @param xTask Handle to the task for which the priority is being set.\r\n * Passing a NULL handle results in the priority of the calling task being set.\r\n *\r\n * @param uxNewPriority The priority to which the task will be set.\r\n *\r\n * Example usage:\r\n   <pre>\r\n void vAFunction( void )\r\n {\r\n TaskHandle_t xHandle;\r\n\r\n\t // Create a task, storing the handle.\r\n\t xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );\r\n\r\n\t // ...\r\n\r\n\t // Use the handle to raise the priority of the created task.\r\n\t vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );\r\n\r\n\t // ...\r\n\r\n\t // Use a NULL handle to raise our priority to the same value.\r\n\t vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );\r\n }\r\n   </pre>\r\n * \\defgroup vTaskPrioritySet vTaskPrioritySet\r\n * \\ingroup TaskCtrl\r\n */\r\nvoid vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION;\r\n\r\n/**\r\n * task. h\r\n * <pre>void vTaskSuspend( TaskHandle_t xTaskToSuspend );</pre>\r\n *\r\n * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.\r\n * See the configuration section for more information.\r\n *\r\n * Suspend any task.  When suspended a task will never get any microcontroller\r\n * processing time, no matter what its priority.\r\n *\r\n * Calls to vTaskSuspend are not accumulative -\r\n * i.e. calling vTaskSuspend () twice on the same task still only requires one\r\n * call to vTaskResume () to ready the suspended task.\r\n *\r\n * @param xTaskToSuspend Handle to the task being suspended.  Passing a NULL\r\n * handle will cause the calling task to be suspended.\r\n *\r\n * Example usage:\r\n   <pre>\r\n void vAFunction( void )\r\n {\r\n TaskHandle_t xHandle;\r\n\r\n\t // Create a task, storing the handle.\r\n\t xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );\r\n\r\n\t // ...\r\n\r\n\t // Use the handle to suspend the created task.\r\n\t vTaskSuspend( xHandle );\r\n\r\n\t // ...\r\n\r\n\t // The created task will not run during this period, unless\r\n\t // another task calls vTaskResume( xHandle ).\r\n\r\n\t //...\r\n\r\n\r\n\t // Suspend ourselves.\r\n\t vTaskSuspend( NULL );\r\n\r\n\t // We cannot get here unless another task calls vTaskResume\r\n\t // with our handle as the parameter.\r\n }\r\n   </pre>\r\n * \\defgroup vTaskSuspend vTaskSuspend\r\n * \\ingroup TaskCtrl\r\n */\r\nvoid vTaskSuspend( TaskHandle_t xTaskToSuspend ) PRIVILEGED_FUNCTION;\r\n\r\n/**\r\n * task. h\r\n * <pre>void vTaskResume( TaskHandle_t xTaskToResume );</pre>\r\n *\r\n * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.\r\n * See the configuration section for more information.\r\n *\r\n * Resumes a suspended task.\r\n *\r\n * A task that has been suspended by one or more calls to vTaskSuspend ()\r\n * will be made available for running again by a single call to\r\n * vTaskResume ().\r\n *\r\n * @param xTaskToResume Handle to the task being readied.\r\n *\r\n * Example usage:\r\n   <pre>\r\n void vAFunction( void )\r\n {\r\n TaskHandle_t xHandle;\r\n\r\n\t // Create a task, storing the handle.\r\n\t xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );\r\n\r\n\t // ...\r\n\r\n\t // Use the handle to suspend the created task.\r\n\t vTaskSuspend( xHandle );\r\n\r\n\t // ...\r\n\r\n\t // The created task will not run during this period, unless\r\n\t // another task calls vTaskResume( xHandle ).\r\n\r\n\t //...\r\n\r\n\r\n\t // Resume the suspended task ourselves.\r\n\t vTaskResume( xHandle );\r\n\r\n\t // The created task will once again get microcontroller processing\r\n\t // time in accordance with its priority within the system.\r\n }\r\n   </pre>\r\n * \\defgroup vTaskResume vTaskResume\r\n * \\ingroup TaskCtrl\r\n */\r\nvoid vTaskResume( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;\r\n\r\n/**\r\n * task. h\r\n * <pre>void xTaskResumeFromISR( TaskHandle_t xTaskToResume );</pre>\r\n *\r\n * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be\r\n * available.  See the configuration section for more information.\r\n *\r\n * An implementation of vTaskResume() that can be called from within an ISR.\r\n *\r\n * A task that has been suspended by one or more calls to vTaskSuspend ()\r\n * will be made available for running again by a single call to\r\n * xTaskResumeFromISR ().\r\n *\r\n * xTaskResumeFromISR() should not be used to synchronise a task with an\r\n * interrupt if there is a chance that the interrupt could arrive prior to the\r\n * task being suspended - as this can lead to interrupts being missed. Use of a\r\n * semaphore as a synchronisation mechanism would avoid this eventuality.\r\n *\r\n * @param xTaskToResume Handle to the task being readied.\r\n *\r\n * @return pdTRUE if resuming the task should result in a context switch,\r\n * otherwise pdFALSE. This is used by the ISR to determine if a context switch\r\n * may be required following the ISR.\r\n *\r\n * \\defgroup vTaskResumeFromISR vTaskResumeFromISR\r\n * \\ingroup TaskCtrl\r\n */\r\nBaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;\r\n\r\n/*-----------------------------------------------------------\r\n * SCHEDULER CONTROL\r\n *----------------------------------------------------------*/\r\n\r\n/**\r\n * task. h\r\n * <pre>void vTaskStartScheduler( void );</pre>\r\n *\r\n * Starts the real time kernel tick processing.  After calling the kernel\r\n * has control over which tasks are executed and when.\r\n *\r\n * See the demo application file main.c for an example of creating\r\n * tasks and starting the kernel.\r\n *\r\n * Example usage:\r\n   <pre>\r\n void vAFunction( void )\r\n {\r\n\t // Create at least one task before starting the kernel.\r\n\t xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\r\n\r\n\t // Start the real time kernel with preemption.\r\n\t vTaskStartScheduler ();\r\n\r\n\t // Will not get here unless a task calls vTaskEndScheduler ()\r\n }\r\n   </pre>\r\n *\r\n * \\defgroup vTaskStartScheduler vTaskStartScheduler\r\n * \\ingroup SchedulerControl\r\n */\r\nvoid vTaskStartScheduler( void ) PRIVILEGED_FUNCTION;\r\n\r\n/**\r\n * task. h\r\n * <pre>void vTaskEndScheduler( void );</pre>\r\n *\r\n * NOTE:  At the time of writing only the x86 real mode port, which runs on a PC\r\n * in place of DOS, implements this function.\r\n *\r\n * Stops the real time kernel tick.  All created tasks will be automatically\r\n * deleted and multitasking (either preemptive or cooperative) will\r\n * stop.  Execution then resumes from the point where vTaskStartScheduler ()\r\n * was called, as if vTaskStartScheduler () had just returned.\r\n *\r\n * See the demo application file main. c in the demo/PC directory for an\r\n * example that uses vTaskEndScheduler ().\r\n *\r\n * vTaskEndScheduler () requires an exit function to be defined within the\r\n * portable layer (see vPortEndScheduler () in port. c for the PC port).  This\r\n * performs hardware specific operations such as stopping the kernel tick.\r\n *\r\n * vTaskEndScheduler () will cause all of the resources allocated by the\r\n * kernel to be freed - but will not free resources allocated by application\r\n * tasks.\r\n *\r\n * Example usage:\r\n   <pre>\r\n void vTaskCode( void * pvParameters )\r\n {\r\n\t for( ;; )\r\n\t {\r\n\t\t // Task code goes here.\r\n\r\n\t\t // At some point we want to end the real time kernel processing\r\n\t\t // so call ...\r\n\t\t vTaskEndScheduler ();\r\n\t }\r\n }\r\n\r\n void vAFunction( void )\r\n {\r\n\t // Create at least one task before starting the kernel.\r\n\t xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\r\n\r\n\t // Start the real time kernel with preemption.\r\n\t vTaskStartScheduler ();\r\n\r\n\t // Will only get here when the vTaskCode () task has called\r\n\t // vTaskEndScheduler ().  When we get here we are back to single task\r\n\t // execution.\r\n }\r\n   </pre>\r\n *\r\n * \\defgroup vTaskEndScheduler vTaskEndScheduler\r\n * \\ingroup SchedulerControl\r\n */\r\nvoid vTaskEndScheduler( void ) PRIVILEGED_FUNCTION;\r\n\r\n/**\r\n * task. h\r\n * <pre>void vTaskSuspendAll( void );</pre>\r\n *\r\n * Suspends the scheduler without disabling interrupts.  Context switches will\r\n * not occur while the scheduler is suspended.\r\n *\r\n * After calling vTaskSuspendAll () the calling task will continue to execute\r\n * without risk of being swapped out until a call to xTaskResumeAll () has been\r\n * made.\r\n *\r\n * API functions that have the potential to cause a context switch (for example,\r\n * vTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler\r\n * is suspended.\r\n *\r\n * Example usage:\r\n   <pre>\r\n void vTask1( void * pvParameters )\r\n {\r\n\t for( ;; )\r\n\t {\r\n\t\t // Task code goes here.\r\n\r\n\t\t // ...\r\n\r\n\t\t // At some point the task wants to perform a long operation during\r\n\t\t // which it does not want to get swapped out.  It cannot use\r\n\t\t // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the\r\n\t\t // operation may cause interrupts to be missed - including the\r\n\t\t // ticks.\r\n\r\n\t\t // Prevent the real time kernel swapping out the task.\r\n\t\t vTaskSuspendAll ();\r\n\r\n\t\t // Perform the operation here.  There is no need to use critical\r\n\t\t // sections as we have all the microcontroller processing time.\r\n\t\t // During this time interrupts will still operate and the kernel\r\n\t\t // tick count will be maintained.\r\n\r\n\t\t // ...\r\n\r\n\t\t // The operation is complete.  Restart the kernel.\r\n\t\t xTaskResumeAll ();\r\n\t }\r\n }\r\n   </pre>\r\n * \\defgroup vTaskSuspendAll vTaskSuspendAll\r\n * \\ingroup SchedulerControl\r\n */\r\nvoid vTaskSuspendAll( void ) PRIVILEGED_FUNCTION;\r\n\r\n/**\r\n * task. h\r\n * <pre>BaseType_t xTaskResumeAll( void );</pre>\r\n *\r\n * Resumes scheduler activity after it was suspended by a call to\r\n * vTaskSuspendAll().\r\n *\r\n * xTaskResumeAll() only resumes the scheduler.  It does not unsuspend tasks\r\n * that were previously suspended by a call to vTaskSuspend().\r\n *\r\n * @return If resuming the scheduler caused a context switch then pdTRUE is\r\n *\t\t  returned, otherwise pdFALSE is returned.\r\n *\r\n * Example usage:\r\n   <pre>\r\n void vTask1( void * pvParameters )\r\n {\r\n\t for( ;; )\r\n\t {\r\n\t\t // Task code goes here.\r\n\r\n\t\t // ...\r\n\r\n\t\t // At some point the task wants to perform a long operation during\r\n\t\t // which it does not want to get swapped out.  It cannot use\r\n\t\t // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the\r\n\t\t // operation may cause interrupts to be missed - including the\r\n\t\t // ticks.\r\n\r\n\t\t // Prevent the real time kernel swapping out the task.\r\n\t\t vTaskSuspendAll ();\r\n\r\n\t\t // Perform the operation here.  There is no need to use critical\r\n\t\t // sections as we have all the microcontroller processing time.\r\n\t\t // During this time interrupts will still operate and the real\r\n\t\t // time kernel tick count will be maintained.\r\n\r\n\t\t // ...\r\n\r\n\t\t // The operation is complete.  Restart the kernel.  We want to force\r\n\t\t // a context switch - but there is no point if resuming the scheduler\r\n\t\t // caused a context switch already.\r\n\t\t if( !xTaskResumeAll () )\r\n\t\t {\r\n\t\t\t  taskYIELD ();\r\n\t\t }\r\n\t }\r\n }\r\n   </pre>\r\n * \\defgroup xTaskResumeAll xTaskResumeAll\r\n * \\ingroup SchedulerControl\r\n */\r\nBaseType_t xTaskResumeAll( void ) PRIVILEGED_FUNCTION;\r\n\r\n/*-----------------------------------------------------------\r\n * TASK UTILITIES\r\n *----------------------------------------------------------*/\r\n\r\n/**\r\n * task. h\r\n * <PRE>TickType_t xTaskGetTickCount( void );</PRE>\r\n *\r\n * @return The count of ticks since vTaskStartScheduler was called.\r\n *\r\n * \\defgroup xTaskGetTickCount xTaskGetTickCount\r\n * \\ingroup TaskUtils\r\n */\r\nTickType_t xTaskGetTickCount( void ) PRIVILEGED_FUNCTION;\r\n\r\n/**\r\n * task. h\r\n * <PRE>TickType_t xTaskGetTickCountFromISR( void );</PRE>\r\n *\r\n * @return The count of ticks since vTaskStartScheduler was called.\r\n *\r\n * This is a version of xTaskGetTickCount() that is safe to be called from an\r\n * ISR - provided that TickType_t is the natural word size of the\r\n * microcontroller being used or interrupt nesting is either not supported or\r\n * not being used.\r\n *\r\n * \\defgroup xTaskGetTickCountFromISR xTaskGetTickCountFromISR\r\n * \\ingroup TaskUtils\r\n */\r\nTickType_t xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION;\r\n\r\n/**\r\n * task. h\r\n * <PRE>uint16_t uxTaskGetNumberOfTasks( void );</PRE>\r\n *\r\n * @return The number of tasks that the real time kernel is currently managing.\r\n * This includes all ready, blocked and suspended tasks.  A task that\r\n * has been deleted but not yet freed by the idle task will also be\r\n * included in the count.\r\n *\r\n * \\defgroup uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks\r\n * \\ingroup TaskUtils\r\n */\r\nUBaseType_t uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION;\r\n\r\n/**\r\n * task. h\r\n * <PRE>char *pcTaskGetTaskName( TaskHandle_t xTaskToQuery );</PRE>\r\n *\r\n * @return The text (human readable) name of the task referenced by the handle\r\n * xTaskToQuery.  A task can query its own name by either passing in its own\r\n * handle, or by setting xTaskToQuery to NULL.  INCLUDE_pcTaskGetTaskName must be\r\n * set to 1 in FreeRTOSConfig.h for pcTaskGetTaskName() to be available.\r\n *\r\n * \\defgroup pcTaskGetTaskName pcTaskGetTaskName\r\n * \\ingroup TaskUtils\r\n */\r\nchar *pcTaskGetTaskName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\r\n\r\n/**\r\n * task.h\r\n * <PRE>UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask );</PRE>\r\n *\r\n * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for\r\n * this function to be available.\r\n *\r\n * Returns the high water mark of the stack associated with xTask.  That is,\r\n * the minimum free stack space there has been (in words, so on a 32 bit machine\r\n * a value of 1 means 4 bytes) since the task started.  The smaller the returned\r\n * number the closer the task has come to overflowing its stack.\r\n *\r\n * @param xTask Handle of the task associated with the stack to be checked.\r\n * Set xTask to NULL to check the stack of the calling task.\r\n *\r\n * @return The smallest amount of free stack space there has been (in words, so\r\n * actual spaces on the stack rather than bytes) since the task referenced by\r\n * xTask was created.\r\n */\r\nUBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\r\n\r\n/* When using trace macros it is sometimes necessary to include task.h before\r\nFreeRTOS.h.  When this is done TaskHookFunction_t will not yet have been defined,\r\nso the following two prototypes will cause a compilation error.  This can be\r\nfixed by simply guarding against the inclusion of these two prototypes unless\r\nthey are explicitly required by the configUSE_APPLICATION_TASK_TAG configuration\r\nconstant. */\r\n#ifdef configUSE_APPLICATION_TASK_TAG\r\n\t#if configUSE_APPLICATION_TASK_TAG == 1\r\n\t\t/**\r\n\t\t * task.h\r\n\t\t * <pre>void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction );</pre>\r\n\t\t *\r\n\t\t * Sets pxHookFunction to be the task hook function used by the task xTask.\r\n\t\t * Passing xTask as NULL has the effect of setting the calling tasks hook\r\n\t\t * function.\r\n\t\t */\r\n\t\tvoid vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) PRIVILEGED_FUNCTION;\r\n\r\n\t\t/**\r\n\t\t * task.h\r\n\t\t * <pre>void xTaskGetApplicationTaskTag( TaskHandle_t xTask );</pre>\r\n\t\t *\r\n\t\t * Returns the pxHookFunction value assigned to the task xTask.\r\n\t\t */\r\n\t\tTaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\r\n\t#endif /* configUSE_APPLICATION_TASK_TAG ==1 */\r\n#endif /* ifdef configUSE_APPLICATION_TASK_TAG */\r\n\r\n#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )\r\n\r\n\t/* Each task contains an array of pointers that is dimensioned by the\r\n\tconfigNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h.  The\r\n\tkernel does not use the pointers itself, so the application writer can use\r\n\tthe pointers for any purpose they wish.  The following two functions are\r\n\tused to set and query a pointer respectively. */\r\n\tvoid vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue );\r\n\tvoid *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex );\r\n\r\n#endif\r\n\r\n/**\r\n * task.h\r\n * <pre>BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );</pre>\r\n *\r\n * Calls the hook function associated with xTask.  Passing xTask as NULL has\r\n * the effect of calling the Running tasks (the calling task) hook function.\r\n *\r\n * pvParameter is passed to the hook function for the task to interpret as it\r\n * wants.  The return value is the value returned by the task hook function\r\n * registered by the user.\r\n */\r\nBaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) PRIVILEGED_FUNCTION;\r\n\r\n/**\r\n * xTaskGetIdleTaskHandle() is only available if\r\n * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h.\r\n *\r\n * Simply returns the handle of the idle task.  It is not valid to call\r\n * xTaskGetIdleTaskHandle() before the scheduler has been started.\r\n */\r\nTaskHandle_t xTaskGetIdleTaskHandle( void );\r\n\r\n/**\r\n * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for\r\n * uxTaskGetSystemState() to be available.\r\n *\r\n * uxTaskGetSystemState() populates an TaskStatus_t structure for each task in\r\n * the system.  TaskStatus_t structures contain, among other things, members\r\n * for the task handle, task name, task priority, task state, and total amount\r\n * of run time consumed by the task.  See the TaskStatus_t structure\r\n * definition in this file for the full member list.\r\n *\r\n * NOTE:  This function is intended for debugging use only as its use results in\r\n * the scheduler remaining suspended for an extended period.\r\n *\r\n * @param pxTaskStatusArray A pointer to an array of TaskStatus_t structures.\r\n * The array must contain at least one TaskStatus_t structure for each task\r\n * that is under the control of the RTOS.  The number of tasks under the control\r\n * of the RTOS can be determined using the uxTaskGetNumberOfTasks() API function.\r\n *\r\n * @param uxArraySize The size of the array pointed to by the pxTaskStatusArray\r\n * parameter.  The size is specified as the number of indexes in the array, or\r\n * the number of TaskStatus_t structures contained in the array, not by the\r\n * number of bytes in the array.\r\n *\r\n * @param pulTotalRunTime If configGENERATE_RUN_TIME_STATS is set to 1 in\r\n * FreeRTOSConfig.h then *pulTotalRunTime is set by uxTaskGetSystemState() to the\r\n * total run time (as defined by the run time stats clock, see\r\n * http://www.freertos.org/rtos-run-time-stats.html) since the target booted.\r\n * pulTotalRunTime can be set to NULL to omit the total run time information.\r\n *\r\n * @return The number of TaskStatus_t structures that were populated by\r\n * uxTaskGetSystemState().  This should equal the number returned by the\r\n * uxTaskGetNumberOfTasks() API function, but will be zero if the value passed\r\n * in the uxArraySize parameter was too small.\r\n *\r\n * Example usage:\r\n   <pre>\r\n    // This example demonstrates how a human readable table of run time stats\r\n\t// information is generated from raw data provided by uxTaskGetSystemState().\r\n\t// The human readable table is written to pcWriteBuffer\r\n\tvoid vTaskGetRunTimeStats( char *pcWriteBuffer )\r\n\t{\r\n\tTaskStatus_t *pxTaskStatusArray;\r\n\tvolatile UBaseType_t uxArraySize, x;\r\n\tuint32_t ulTotalRunTime, ulStatsAsPercentage;\r\n\r\n\t\t// Make sure the write buffer does not contain a string.\r\n\t\t*pcWriteBuffer = 0x00;\r\n\r\n\t\t// Take a snapshot of the number of tasks in case it changes while this\r\n\t\t// function is executing.\r\n\t\tuxArraySize = uxTaskGetNumberOfTasks();\r\n\r\n\t\t// Allocate a TaskStatus_t structure for each task.  An array could be\r\n\t\t// allocated statically at compile time.\r\n\t\tpxTaskStatusArray = pvPortMalloc( uxArraySize * sizeof( TaskStatus_t ) );\r\n\r\n\t\tif( pxTaskStatusArray != NULL )\r\n\t\t{\r\n\t\t\t// Generate raw status information about each task.\r\n\t\t\tuxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalRunTime );\r\n\r\n\t\t\t// For percentage calculations.\r\n\t\t\tulTotalRunTime /= 100UL;\r\n\r\n\t\t\t// Avoid divide by zero errors.\r\n\t\t\tif( ulTotalRunTime > 0 )\r\n\t\t\t{\r\n\t\t\t\t// For each populated position in the pxTaskStatusArray array,\r\n\t\t\t\t// format the raw data as human readable ASCII data\r\n\t\t\t\tfor( x = 0; x < uxArraySize; x++ )\r\n\t\t\t\t{\r\n\t\t\t\t\t// What percentage of the total run time has the task used?\r\n\t\t\t\t\t// This will always be rounded down to the nearest integer.\r\n\t\t\t\t\t// ulTotalRunTimeDiv100 has already been divided by 100.\r\n\t\t\t\t\tulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalRunTime;\r\n\r\n\t\t\t\t\tif( ulStatsAsPercentage > 0UL )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tsprintf( pcWriteBuffer, \"%s\\t\\t%lu\\t\\t%lu%%\\r\\n\", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t// If the percentage is zero here then the task has\r\n\t\t\t\t\t\t// consumed less than 1% of the total run time.\r\n\t\t\t\t\t\tsprintf( pcWriteBuffer, \"%s\\t\\t%lu\\t\\t<1%%\\r\\n\", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter );\r\n\t\t\t\t\t}\r\n\r\n\t\t\t\t\tpcWriteBuffer += strlen( ( char * ) pcWriteBuffer );\r\n\t\t\t\t}\r\n\t\t\t}\r\n\r\n\t\t\t// The array is no longer needed, free the memory it consumes.\r\n\t\t\tvPortFree( pxTaskStatusArray );\r\n\t\t}\r\n\t}\r\n\t</pre>\r\n */\r\nUBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime );\r\n\r\n/**\r\n * task. h\r\n * <PRE>void vTaskList( char *pcWriteBuffer );</PRE>\r\n *\r\n * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must\r\n * both be defined as 1 for this function to be available.  See the\r\n * configuration section of the FreeRTOS.org website for more information.\r\n *\r\n * NOTE 1: This function will disable interrupts for its duration.  It is\r\n * not intended for normal application runtime use but as a debug aid.\r\n *\r\n * Lists all the current tasks, along with their current state and stack\r\n * usage high water mark.\r\n *\r\n * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or\r\n * suspended ('S').\r\n *\r\n * PLEASE NOTE:\r\n *\r\n * This function is provided for convenience only, and is used by many of the\r\n * demo applications.  Do not consider it to be part of the scheduler.\r\n *\r\n * vTaskList() calls uxTaskGetSystemState(), then formats part of the\r\n * uxTaskGetSystemState() output into a human readable table that displays task\r\n * names, states and stack usage.\r\n *\r\n * vTaskList() has a dependency on the sprintf() C library function that might\r\n * bloat the code size, use a lot of stack, and provide different results on\r\n * different platforms.  An alternative, tiny, third party, and limited\r\n * functionality implementation of sprintf() is provided in many of the\r\n * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note\r\n * printf-stdarg.c does not provide a full snprintf() implementation!).\r\n *\r\n * It is recommended that production systems call uxTaskGetSystemState()\r\n * directly to get access to raw stats data, rather than indirectly through a\r\n * call to vTaskList().\r\n *\r\n * @param pcWriteBuffer A buffer into which the above mentioned details\r\n * will be written, in ASCII form.  This buffer is assumed to be large\r\n * enough to contain the generated report.  Approximately 40 bytes per\r\n * task should be sufficient.\r\n *\r\n * \\defgroup vTaskList vTaskList\r\n * \\ingroup TaskUtils\r\n */\r\nvoid vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\r\n\r\n/**\r\n * task. h\r\n * <PRE>void vTaskGetRunTimeStats( char *pcWriteBuffer );</PRE>\r\n *\r\n * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS\r\n * must both be defined as 1 for this function to be available.  The application\r\n * must also then provide definitions for\r\n * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()\r\n * to configure a peripheral timer/counter and return the timers current count\r\n * value respectively.  The counter should be at least 10 times the frequency of\r\n * the tick count.\r\n *\r\n * NOTE 1: This function will disable interrupts for its duration.  It is\r\n * not intended for normal application runtime use but as a debug aid.\r\n *\r\n * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total\r\n * accumulated execution time being stored for each task.  The resolution\r\n * of the accumulated time value depends on the frequency of the timer\r\n * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.\r\n * Calling vTaskGetRunTimeStats() writes the total execution time of each\r\n * task into a buffer, both as an absolute count value and as a percentage\r\n * of the total system execution time.\r\n *\r\n * NOTE 2:\r\n *\r\n * This function is provided for convenience only, and is used by many of the\r\n * demo applications.  Do not consider it to be part of the scheduler.\r\n *\r\n * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part of the\r\n * uxTaskGetSystemState() output into a human readable table that displays the\r\n * amount of time each task has spent in the Running state in both absolute and\r\n * percentage terms.\r\n *\r\n * vTaskGetRunTimeStats() has a dependency on the sprintf() C library function\r\n * that might bloat the code size, use a lot of stack, and provide different\r\n * results on different platforms.  An alternative, tiny, third party, and\r\n * limited functionality implementation of sprintf() is provided in many of the\r\n * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note\r\n * printf-stdarg.c does not provide a full snprintf() implementation!).\r\n *\r\n * It is recommended that production systems call uxTaskGetSystemState() directly\r\n * to get access to raw stats data, rather than indirectly through a call to\r\n * vTaskGetRunTimeStats().\r\n *\r\n * @param pcWriteBuffer A buffer into which the execution times will be\r\n * written, in ASCII form.  This buffer is assumed to be large enough to\r\n * contain the generated report.  Approximately 40 bytes per task should\r\n * be sufficient.\r\n *\r\n * \\defgroup vTaskGetRunTimeStats vTaskGetRunTimeStats\r\n * \\ingroup TaskUtils\r\n */\r\nvoid vTaskGetRunTimeStats( char *pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\r\n\r\n/**\r\n * task. h\r\n * <PRE>BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction );</PRE>\r\n *\r\n * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this\r\n * function to be available.\r\n *\r\n * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private\r\n * \"notification value\", which is a 32-bit unsigned integer (uint32_t).\r\n *\r\n * Events can be sent to a task using an intermediary object.  Examples of such\r\n * objects are queues, semaphores, mutexes and event groups.  Task notifications\r\n * are a method of sending an event directly to a task without the need for such\r\n * an intermediary object.\r\n *\r\n * A notification sent to a task can optionally perform an action, such as\r\n * update, overwrite or increment the task's notification value.  In that way\r\n * task notifications can be used to send data to a task, or be used as light\r\n * weight and fast binary or counting semaphores.\r\n *\r\n * A notification sent to a task will remain pending until it is cleared by the\r\n * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was\r\n * already in the Blocked state to wait for a notification when the notification\r\n * arrives then the task will automatically be removed from the Blocked state\r\n * (unblocked) and the notification cleared.\r\n *\r\n * A task can use xTaskNotifyWait() to [optionally] block to wait for a\r\n * notification to be pending, or ulTaskNotifyTake() to [optionally] block\r\n * to wait for its notification value to have a non-zero value.  The task does\r\n * not consume any CPU time while it is in the Blocked state.\r\n *\r\n * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.\r\n *\r\n * @param xTaskToNotify The handle of the task being notified.  The handle to a\r\n * task can be returned from the xTaskCreate() API function used to create the\r\n * task, and the handle of the currently running task can be obtained by calling\r\n * xTaskGetCurrentTaskHandle().\r\n *\r\n * @param ulValue Data that can be sent with the notification.  How the data is\r\n * used depends on the value of the eAction parameter.\r\n *\r\n * @param eAction Specifies how the notification updates the task's notification\r\n * value, if at all.  Valid values for eAction are as follows:\r\n *\r\n *\teSetBits -\r\n *\tThe task's notification value is bitwise ORed with ulValue.  xTaskNofify()\r\n * \talways returns pdPASS in this case.\r\n *\r\n *\teIncrement -\r\n *\tThe task's notification value is incremented.  ulValue is not used and\r\n *\txTaskNotify() always returns pdPASS in this case.\r\n *\r\n *\teSetValueWithOverwrite -\r\n *\tThe task's notification value is set to the value of ulValue, even if the\r\n *\ttask being notified had not yet processed the previous notification (the\r\n *\ttask already had a notification pending).  xTaskNotify() always returns\r\n *\tpdPASS in this case.\r\n *\r\n *\teSetValueWithoutOverwrite -\r\n *\tIf the task being notified did not already have a notification pending then\r\n *\tthe task's notification value is set to ulValue and xTaskNotify() will\r\n *\treturn pdPASS.  If the task being notified already had a notification\r\n *\tpending then no action is performed and pdFAIL is returned.\r\n *\r\n *\teNoAction -\r\n *\tThe task receives a notification without its notification value being\r\n *\tupdated.  ulValue is not used and xTaskNotify() always returns pdPASS in\r\n *\tthis case.\r\n *\r\n *  pulPreviousNotificationValue -\r\n *  Can be used to pass out the subject task's notification value before any\r\n *  bits are modified by the notify function.\r\n *\r\n * @return Dependent on the value of eAction.  See the description of the\r\n * eAction parameter.\r\n *\r\n * \\defgroup xTaskNotify xTaskNotify\r\n * \\ingroup TaskNotifications\r\n */\r\nBaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue );\r\n#define xTaskNotify( xTaskToNotify, ulValue, eAction ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL )\r\n#define xTaskNotifyAndQuery( xTaskToNotify, ulValue, eAction, pulPreviousNotifyValue ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) )\r\n\r\n/**\r\n * task. h\r\n * <PRE>BaseType_t xTaskNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken );</PRE>\r\n *\r\n * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this\r\n * function to be available.\r\n *\r\n * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private\r\n * \"notification value\", which is a 32-bit unsigned integer (uint32_t).\r\n *\r\n * A version of xTaskNotify() that can be used from an interrupt service routine\r\n * (ISR).\r\n *\r\n * Events can be sent to a task using an intermediary object.  Examples of such\r\n * objects are queues, semaphores, mutexes and event groups.  Task notifications\r\n * are a method of sending an event directly to a task without the need for such\r\n * an intermediary object.\r\n *\r\n * A notification sent to a task can optionally perform an action, such as\r\n * update, overwrite or increment the task's notification value.  In that way\r\n * task notifications can be used to send data to a task, or be used as light\r\n * weight and fast binary or counting semaphores.\r\n *\r\n * A notification sent to a task will remain pending until it is cleared by the\r\n * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was\r\n * already in the Blocked state to wait for a notification when the notification\r\n * arrives then the task will automatically be removed from the Blocked state\r\n * (unblocked) and the notification cleared.\r\n *\r\n * A task can use xTaskNotifyWait() to [optionally] block to wait for a\r\n * notification to be pending, or ulTaskNotifyTake() to [optionally] block\r\n * to wait for its notification value to have a non-zero value.  The task does\r\n * not consume any CPU time while it is in the Blocked state.\r\n *\r\n * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.\r\n *\r\n * @param xTaskToNotify The handle of the task being notified.  The handle to a\r\n * task can be returned from the xTaskCreate() API function used to create the\r\n * task, and the handle of the currently running task can be obtained by calling\r\n * xTaskGetCurrentTaskHandle().\r\n *\r\n * @param ulValue Data that can be sent with the notification.  How the data is\r\n * used depends on the value of the eAction parameter.\r\n *\r\n * @param eAction Specifies how the notification updates the task's notification\r\n * value, if at all.  Valid values for eAction are as follows:\r\n *\r\n *\teSetBits -\r\n *\tThe task's notification value is bitwise ORed with ulValue.  xTaskNofify()\r\n * \talways returns pdPASS in this case.\r\n *\r\n *\teIncrement -\r\n *\tThe task's notification value is incremented.  ulValue is not used and\r\n *\txTaskNotify() always returns pdPASS in this case.\r\n *\r\n *\teSetValueWithOverwrite -\r\n *\tThe task's notification value is set to the value of ulValue, even if the\r\n *\ttask being notified had not yet processed the previous notification (the\r\n *\ttask already had a notification pending).  xTaskNotify() always returns\r\n *\tpdPASS in this case.\r\n *\r\n *\teSetValueWithoutOverwrite -\r\n *\tIf the task being notified did not already have a notification pending then\r\n *\tthe task's notification value is set to ulValue and xTaskNotify() will\r\n *\treturn pdPASS.  If the task being notified already had a notification\r\n *\tpending then no action is performed and pdFAIL is returned.\r\n *\r\n *\teNoAction -\r\n *\tThe task receives a notification without its notification value being\r\n *\tupdated.  ulValue is not used and xTaskNotify() always returns pdPASS in\r\n *\tthis case.\r\n *\r\n * @param pxHigherPriorityTaskWoken  xTaskNotifyFromISR() will set\r\n * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the\r\n * task to which the notification was sent to leave the Blocked state, and the\r\n * unblocked task has a priority higher than the currently running task.  If\r\n * xTaskNotifyFromISR() sets this value to pdTRUE then a context switch should\r\n * be requested before the interrupt is exited.  How a context switch is\r\n * requested from an ISR is dependent on the port - see the documentation page\r\n * for the port in use.\r\n *\r\n * @return Dependent on the value of eAction.  See the description of the\r\n * eAction parameter.\r\n *\r\n * \\defgroup xTaskNotify xTaskNotify\r\n * \\ingroup TaskNotifications\r\n */\r\nBaseType_t xTaskNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken );\r\n\r\n/**\r\n * task. h\r\n * <PRE>BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );</pre>\r\n *\r\n * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this\r\n * function to be available.\r\n *\r\n * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private\r\n * \"notification value\", which is a 32-bit unsigned integer (uint32_t).\r\n *\r\n * Events can be sent to a task using an intermediary object.  Examples of such\r\n * objects are queues, semaphores, mutexes and event groups.  Task notifications\r\n * are a method of sending an event directly to a task without the need for such\r\n * an intermediary object.\r\n *\r\n * A notification sent to a task can optionally perform an action, such as\r\n * update, overwrite or increment the task's notification value.  In that way\r\n * task notifications can be used to send data to a task, or be used as light\r\n * weight and fast binary or counting semaphores.\r\n *\r\n * A notification sent to a task will remain pending until it is cleared by the\r\n * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was\r\n * already in the Blocked state to wait for a notification when the notification\r\n * arrives then the task will automatically be removed from the Blocked state\r\n * (unblocked) and the notification cleared.\r\n *\r\n * A task can use xTaskNotifyWait() to [optionally] block to wait for a\r\n * notification to be pending, or ulTaskNotifyTake() to [optionally] block\r\n * to wait for its notification value to have a non-zero value.  The task does\r\n * not consume any CPU time while it is in the Blocked state.\r\n *\r\n * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.\r\n *\r\n * @param ulBitsToClearOnEntry Bits that are set in ulBitsToClearOnEntry value\r\n * will be cleared in the calling task's notification value before the task\r\n * checks to see if any notifications are pending, and optionally blocks if no\r\n * notifications are pending.  Setting ulBitsToClearOnEntry to ULONG_MAX (if\r\n * limits.h is included) or 0xffffffffUL (if limits.h is not included) will have\r\n * the effect of resetting the task's notification value to 0.  Setting\r\n * ulBitsToClearOnEntry to 0 will leave the task's notification value unchanged.\r\n *\r\n * @param ulBitsToClearOnExit If a notification is pending or received before\r\n * the calling task exits the xTaskNotifyWait() function then the task's\r\n * notification value (see the xTaskNotify() API function) is passed out using\r\n * the pulNotificationValue parameter.  Then any bits that are set in\r\n * ulBitsToClearOnExit will be cleared in the task's notification value (note\r\n * *pulNotificationValue is set before any bits are cleared).  Setting\r\n * ulBitsToClearOnExit to ULONG_MAX (if limits.h is included) or 0xffffffffUL\r\n * (if limits.h is not included) will have the effect of resetting the task's\r\n * notification value to 0 before the function exits.  Setting\r\n * ulBitsToClearOnExit to 0 will leave the task's notification value unchanged\r\n * when the function exits (in which case the value passed out in\r\n * pulNotificationValue will match the task's notification value).\r\n *\r\n * @param pulNotificationValue Used to pass the task's notification value out\r\n * of the function.  Note the value passed out will not be effected by the\r\n * clearing of any bits caused by ulBitsToClearOnExit being non-zero.\r\n *\r\n * @param xTicksToWait The maximum amount of time that the task should wait in\r\n * the Blocked state for a notification to be received, should a notification\r\n * not already be pending when xTaskNotifyWait() was called.  The task\r\n * will not consume any processing time while it is in the Blocked state.  This\r\n * is specified in kernel ticks, the macro pdMS_TO_TICSK( value_in_ms ) can be\r\n * used to convert a time specified in milliseconds to a time specified in\r\n * ticks.\r\n *\r\n * @return If a notification was received (including notifications that were\r\n * already pending when xTaskNotifyWait was called) then pdPASS is\r\n * returned.  Otherwise pdFAIL is returned.\r\n *\r\n * \\defgroup xTaskNotifyWait xTaskNotifyWait\r\n * \\ingroup TaskNotifications\r\n */\r\nBaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );\r\n\r\n/**\r\n * task. h\r\n * <PRE>BaseType_t xTaskNotifyGive( TaskHandle_t xTaskToNotify );</PRE>\r\n *\r\n * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro\r\n * to be available.\r\n *\r\n * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private\r\n * \"notification value\", which is a 32-bit unsigned integer (uint32_t).\r\n *\r\n * Events can be sent to a task using an intermediary object.  Examples of such\r\n * objects are queues, semaphores, mutexes and event groups.  Task notifications\r\n * are a method of sending an event directly to a task without the need for such\r\n * an intermediary object.\r\n *\r\n * A notification sent to a task can optionally perform an action, such as\r\n * update, overwrite or increment the task's notification value.  In that way\r\n * task notifications can be used to send data to a task, or be used as light\r\n * weight and fast binary or counting semaphores.\r\n *\r\n * xTaskNotifyGive() is a helper macro intended for use when task notifications\r\n * are used as light weight and faster binary or counting semaphore equivalents.\r\n * Actual FreeRTOS semaphores are given using the xSemaphoreGive() API function,\r\n * the equivalent action that instead uses a task notification is\r\n * xTaskNotifyGive().\r\n *\r\n * When task notifications are being used as a binary or counting semaphore\r\n * equivalent then the task being notified should wait for the notification\r\n * using the ulTaskNotificationTake() API function rather than the\r\n * xTaskNotifyWait() API function.\r\n *\r\n * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.\r\n *\r\n * @param xTaskToNotify The handle of the task being notified.  The handle to a\r\n * task can be returned from the xTaskCreate() API function used to create the\r\n * task, and the handle of the currently running task can be obtained by calling\r\n * xTaskGetCurrentTaskHandle().\r\n *\r\n * @return xTaskNotifyGive() is a macro that calls xTaskNotify() with the\r\n * eAction parameter set to eIncrement - so pdPASS is always returned.\r\n *\r\n * \\defgroup xTaskNotifyGive xTaskNotifyGive\r\n * \\ingroup TaskNotifications\r\n */\r\n#define xTaskNotifyGive( xTaskToNotify ) xTaskNotify( ( xTaskToNotify ), 0, eIncrement );\r\n\r\n/**\r\n * task. h\r\n * <PRE>void vTaskNotifyGiveFromISR( TaskHandle_t xTaskHandle, BaseType_t *pxHigherPriorityTaskWoken );\r\n *\r\n * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro\r\n * to be available.\r\n *\r\n * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private\r\n * \"notification value\", which is a 32-bit unsigned integer (uint32_t).\r\n *\r\n * A version of xTaskNotifyGive() that can be called from an interrupt service\r\n * routine (ISR).\r\n *\r\n * Events can be sent to a task using an intermediary object.  Examples of such\r\n * objects are queues, semaphores, mutexes and event groups.  Task notifications\r\n * are a method of sending an event directly to a task without the need for such\r\n * an intermediary object.\r\n *\r\n * A notification sent to a task can optionally perform an action, such as\r\n * update, overwrite or increment the task's notification value.  In that way\r\n * task notifications can be used to send data to a task, or be used as light\r\n * weight and fast binary or counting semaphores.\r\n *\r\n * vTaskNotifyGiveFromISR() is intended for use when task notifications are\r\n * used as light weight and faster binary or counting semaphore equivalents.\r\n * Actual FreeRTOS semaphores are given from an ISR using the\r\n * xSemaphoreGiveFromISR() API function, the equivalent action that instead uses\r\n * a task notification is vTaskNotifyGiveFromISR().\r\n *\r\n * When task notifications are being used as a binary or counting semaphore\r\n * equivalent then the task being notified should wait for the notification\r\n * using the ulTaskNotificationTake() API function rather than the\r\n * xTaskNotifyWait() API function.\r\n *\r\n * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.\r\n *\r\n * @param xTaskToNotify The handle of the task being notified.  The handle to a\r\n * task can be returned from the xTaskCreate() API function used to create the\r\n * task, and the handle of the currently running task can be obtained by calling\r\n * xTaskGetCurrentTaskHandle().\r\n *\r\n * @param pxHigherPriorityTaskWoken  vTaskNotifyGiveFromISR() will set\r\n * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the\r\n * task to which the notification was sent to leave the Blocked state, and the\r\n * unblocked task has a priority higher than the currently running task.  If\r\n * vTaskNotifyGiveFromISR() sets this value to pdTRUE then a context switch\r\n * should be requested before the interrupt is exited.  How a context switch is\r\n * requested from an ISR is dependent on the port - see the documentation page\r\n * for the port in use.\r\n *\r\n * \\defgroup xTaskNotifyWait xTaskNotifyWait\r\n * \\ingroup TaskNotifications\r\n */\r\nvoid vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken );\r\n\r\n/**\r\n * task. h\r\n * <PRE>uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );</pre>\r\n *\r\n * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this\r\n * function to be available.\r\n *\r\n * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private\r\n * \"notification value\", which is a 32-bit unsigned integer (uint32_t).\r\n *\r\n * Events can be sent to a task using an intermediary object.  Examples of such\r\n * objects are queues, semaphores, mutexes and event groups.  Task notifications\r\n * are a method of sending an event directly to a task without the need for such\r\n * an intermediary object.\r\n *\r\n * A notification sent to a task can optionally perform an action, such as\r\n * update, overwrite or increment the task's notification value.  In that way\r\n * task notifications can be used to send data to a task, or be used as light\r\n * weight and fast binary or counting semaphores.\r\n *\r\n * ulTaskNotifyTake() is intended for use when a task notification is used as a\r\n * faster and lighter weight binary or counting semaphore alternative.  Actual\r\n * FreeRTOS semaphores are taken using the xSemaphoreTake() API function, the\r\n * equivalent action that instead uses a task notification is\r\n * ulTaskNotifyTake().\r\n *\r\n * When a task is using its notification value as a binary or counting semaphore\r\n * other tasks should send notifications to it using the xTaskNotifyGive()\r\n * macro, or xTaskNotify() function with the eAction parameter set to\r\n * eIncrement.\r\n *\r\n * ulTaskNotifyTake() can either clear the task's notification value to\r\n * zero on exit, in which case the notification value acts like a binary\r\n * semaphore, or decrement the task's notification value on exit, in which case\r\n * the notification value acts like a counting semaphore.\r\n *\r\n * A task can use ulTaskNotifyTake() to [optionally] block to wait for a\r\n * the task's notification value to be non-zero.  The task does not consume any\r\n * CPU time while it is in the Blocked state.\r\n *\r\n * Where as xTaskNotifyWait() will return when a notification is pending,\r\n * ulTaskNotifyTake() will return when the task's notification value is\r\n * not zero.\r\n *\r\n * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.\r\n *\r\n * @param xClearCountOnExit if xClearCountOnExit is pdFALSE then the task's\r\n * notification value is decremented when the function exits.  In this way the\r\n * notification value acts like a counting semaphore.  If xClearCountOnExit is\r\n * not pdFALSE then the task's notification value is cleared to zero when the\r\n * function exits.  In this way the notification value acts like a binary\r\n * semaphore.\r\n *\r\n * @param xTicksToWait The maximum amount of time that the task should wait in\r\n * the Blocked state for the task's notification value to be greater than zero,\r\n * should the count not already be greater than zero when\r\n * ulTaskNotifyTake() was called.  The task will not consume any processing\r\n * time while it is in the Blocked state.  This is specified in kernel ticks,\r\n * the macro pdMS_TO_TICSK( value_in_ms ) can be used to convert a time\r\n * specified in milliseconds to a time specified in ticks.\r\n *\r\n * @return The task's notification count before it is either cleared to zero or\r\n * decremented (see the xClearCountOnExit parameter).\r\n *\r\n * \\defgroup ulTaskNotifyTake ulTaskNotifyTake\r\n * \\ingroup TaskNotifications\r\n */\r\nuint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );\r\n\r\n/*-----------------------------------------------------------\r\n * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES\r\n *----------------------------------------------------------*/\r\n\r\n/*\r\n * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY\r\n * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS\r\n * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.\r\n *\r\n * Called from the real time kernel tick (either preemptive or cooperative),\r\n * this increments the tick count and checks if any tasks that are blocked\r\n * for a finite period required removing from a blocked list and placing on\r\n * a ready list.  If a non-zero value is returned then a context switch is\r\n * required because either:\r\n *   + A task was removed from a blocked list because its timeout had expired,\r\n *     or\r\n *   + Time slicing is in use and there is a task of equal priority to the\r\n *     currently running task.\r\n */\r\nBaseType_t xTaskIncrementTick( void ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN\r\n * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.\r\n *\r\n * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.\r\n *\r\n * Removes the calling task from the ready list and places it both\r\n * on the list of tasks waiting for a particular event, and the\r\n * list of delayed tasks.  The task will be removed from both lists\r\n * and replaced on the ready list should either the event occur (and\r\n * there be no higher priority tasks waiting on the same event) or\r\n * the delay period expires.\r\n *\r\n * The 'unordered' version replaces the event list item value with the\r\n * xItemValue value, and inserts the list item at the end of the list.\r\n *\r\n * The 'ordered' version uses the existing event list item value (which is the\r\n * owning tasks priority) to insert the list item into the event list is task\r\n * priority order.\r\n *\r\n * @param pxEventList The list containing tasks that are blocked waiting\r\n * for the event to occur.\r\n *\r\n * @param xItemValue The item value to use for the event list item when the\r\n * event list is not ordered by task priority.\r\n *\r\n * @param xTicksToWait The maximum amount of time that the task should wait\r\n * for the event to occur.  This is specified in kernel ticks,the constant\r\n * portTICK_PERIOD_MS can be used to convert kernel ticks into a real time\r\n * period.\r\n */\r\nvoid vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\r\nvoid vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN\r\n * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.\r\n *\r\n * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.\r\n *\r\n * This function performs nearly the same function as vTaskPlaceOnEventList().\r\n * The difference being that this function does not permit tasks to block\r\n * indefinitely, whereas vTaskPlaceOnEventList() does.\r\n *\r\n */\r\nvoid vTaskPlaceOnEventListRestricted( List_t * const pxEventList, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN\r\n * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.\r\n *\r\n * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.\r\n *\r\n * Removes a task from both the specified event list and the list of blocked\r\n * tasks, and places it on a ready queue.\r\n *\r\n * xTaskRemoveFromEventList()/xTaskRemoveFromUnorderedEventList() will be called\r\n * if either an event occurs to unblock a task, or the block timeout period\r\n * expires.\r\n *\r\n * xTaskRemoveFromEventList() is used when the event list is in task priority\r\n * order.  It removes the list item from the head of the event list as that will\r\n * have the highest priority owning task of all the tasks on the event list.\r\n * xTaskRemoveFromUnorderedEventList() is used when the event list is not\r\n * ordered and the event list items hold something other than the owning tasks\r\n * priority.  In this case the event list item value is updated to the value\r\n * passed in the xItemValue parameter.\r\n *\r\n * @return pdTRUE if the task being removed has a higher priority than the task\r\n * making the call, otherwise pdFALSE.\r\n */\r\nBaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) PRIVILEGED_FUNCTION;\r\nBaseType_t xTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY\r\n * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS\r\n * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.\r\n *\r\n * Sets the pointer to the current TCB to the TCB of the highest priority task\r\n * that is ready to run.\r\n */\r\nvoid vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE.  THEY ARE USED BY\r\n * THE EVENT BITS MODULE.\r\n */\r\nTickType_t uxTaskResetEventItemValue( void ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * Return the handle of the calling task.\r\n */\r\nTaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * Capture the current time status for future reference.\r\n */\r\nvoid vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * Compare the time status now with that previously captured to see if the\r\n * timeout has expired.\r\n */\r\nBaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * Shortcut used by the queue implementation to prevent unnecessary call to\r\n * taskYIELD();\r\n */\r\nvoid vTaskMissedYield( void ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * Returns the scheduler state as taskSCHEDULER_RUNNING,\r\n * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED.\r\n */\r\nBaseType_t xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * Raises the priority of the mutex holder to that of the calling task should\r\n * the mutex holder have a priority less than the calling task.\r\n */\r\nvoid vTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * Set the priority of a task back to its proper priority in the case that it\r\n * inherited a higher priority while it was holding a semaphore.\r\n */\r\nBaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * Generic version of the task creation function which is in turn called by the\r\n * xTaskCreate() and xTaskCreateRestricted() macros.\r\n */\r\nBaseType_t xTaskGenericCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask, StackType_t * const puxStackBuffer, const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\r\n\r\n/*\r\n * Get the uxTCBNumber assigned to the task referenced by the xTask parameter.\r\n */\r\nUBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * Set the uxTaskNumber of the task referenced by the xTask parameter to\r\n * uxHandle.\r\n */\r\nvoid vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * Only available when configUSE_TICKLESS_IDLE is set to 1.\r\n * If tickless mode is being used, or a low power mode is implemented, then\r\n * the tick interrupt will not execute during idle periods.  When this is the\r\n * case, the tick count value maintained by the scheduler needs to be kept up\r\n * to date with the actual execution time by being skipped forward by a time\r\n * equal to the idle period.\r\n */\r\nvoid vTaskStepTick( const TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * Only avilable when configUSE_TICKLESS_IDLE is set to 1.\r\n * Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port\r\n * specific sleep function to determine if it is ok to proceed with the sleep,\r\n * and if it is ok to proceed, if it is ok to sleep indefinitely.\r\n *\r\n * This function is necessary because portSUPPRESS_TICKS_AND_SLEEP() is only\r\n * called with the scheduler suspended, not from within a critical section.  It\r\n * is therefore possible for an interrupt to request a context switch between\r\n * portSUPPRESS_TICKS_AND_SLEEP() and the low power mode actually being\r\n * entered.  eTaskConfirmSleepModeStatus() should be called from a short\r\n * critical section between the timer being stopped and the sleep mode being\r\n * entered to ensure it is ok to proceed into the sleep mode.\r\n */\r\neSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * For internal use only.  Increment the mutex held count when a mutex is\r\n * taken and return the handle of the task that has taken the mutex.\r\n */\r\nvoid *pvTaskIncrementMutexHeldCount( void );\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n#endif /* INC_TASK_H */\r\n\r\n\r\n\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RTOS/src/tasks.c",
    "content": "/*\r\n    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r\n    All rights reserved\r\n\r\n    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r\n\r\n    This file is part of the FreeRTOS distribution.\r\n\r\n    FreeRTOS is free software; you can redistribute it and/or modify it under\r\n    the terms of the GNU General Public License (version 2) as published by the\r\n    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r\n\r\n    ***************************************************************************\r\n    >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r\n    >>!   distribute a combined work that includes FreeRTOS without being   !<<\r\n    >>!   obliged to provide the source code for proprietary components     !<<\r\n    >>!   outside of the FreeRTOS kernel.                                   !<<\r\n    ***************************************************************************\r\n\r\n    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r\n    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r\n    FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r\n    link: http://www.freertos.org/a00114.html\r\n\r\n    ***************************************************************************\r\n     *                                                                       *\r\n     *    FreeRTOS provides completely free yet professionally developed,    *\r\n     *    robust, strictly quality controlled, supported, and cross          *\r\n     *    platform software that is more than just the market leader, it     *\r\n     *    is the industry's de facto standard.                               *\r\n     *                                                                       *\r\n     *    Help yourself get started quickly while simultaneously helping     *\r\n     *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r\n     *    tutorial book, reference manual, or both:                          *\r\n     *    http://www.FreeRTOS.org/Documentation                              *\r\n     *                                                                       *\r\n    ***************************************************************************\r\n\r\n    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r\n    the FAQ page \"My application does not run, what could be wrong?\".  Have you\r\n    defined configASSERT()?\r\n\r\n    http://www.FreeRTOS.org/support - In return for receiving this top quality\r\n    embedded software for free we request you assist our global community by\r\n    participating in the support forum.\r\n\r\n    http://www.FreeRTOS.org/training - Investing in training allows your team to\r\n    be as productive as possible as early as possible.  Now you can receive\r\n    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r\n    Ltd, and the world's leading authority on the world's leading RTOS.\r\n\r\n    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r\n    including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r\n    compatible FAT file system, and our tiny thread aware UDP/IP stack.\r\n\r\n    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r\n    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r\n\r\n    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r\n    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r\n    licenses offer ticketed support, indemnification and commercial middleware.\r\n\r\n    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r\n    engineered and independently SIL3 certified version for use in safety and\r\n    mission critical applications that require provable dependability.\r\n\r\n    1 tab == 4 spaces!\r\n*/\r\n\r\n/* Standard includes. */\r\n#include <stdlib.h>\r\n#include <string.h>\r\n\r\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r\nall the API functions to use the MPU wrappers.  That should only be done when\r\ntask.h is included from an application file. */\r\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r\n\r\n/* FreeRTOS includes. */\r\n#include \"FreeRTOS.h\"\r\n#include \"task.h\"\r\n#include \"timers.h\"\r\n#include \"StackMacros.h\"\r\n\r\n/* Lint e961 and e750 are suppressed as a MISRA exception justified because the\r\nMPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the\r\nheader files above, but not in this file, in order to generate the correct\r\nprivileged Vs unprivileged linkage and placement. */\r\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */\r\n\r\n/* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting\r\nfunctions but without including stdio.h here. */\r\n#if ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 )\r\n\t/* At the bottom of this file are two optional functions that can be used\r\n\tto generate human readable text from the raw data generated by the\r\n\tuxTaskGetSystemState() function.  Note the formatting functions are provided\r\n\tfor convenience only, and are NOT considered part of the kernel. */\r\n\t#include <stdio.h>\r\n#endif /* configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) */\r\n\r\n/* Sanity check the configuration. */\r\n#if configUSE_TICKLESS_IDLE != 0\r\n\t#if INCLUDE_vTaskSuspend != 1\r\n\t\t#error INCLUDE_vTaskSuspend must be set to 1 if configUSE_TICKLESS_IDLE is not set to 0\r\n\t#endif /* INCLUDE_vTaskSuspend */\r\n#endif /* configUSE_TICKLESS_IDLE */\r\n\r\n/*\r\n * Defines the size, in words, of the stack allocated to the idle task.\r\n */\r\n#define tskIDLE_STACK_SIZE\tconfigMINIMAL_STACK_SIZE\r\n\r\n#if( configUSE_PREEMPTION == 0 )\r\n\t/* If the cooperative scheduler is being used then a yield should not be\r\n\tperformed just because a higher priority task has been woken. */\r\n\t#define taskYIELD_IF_USING_PREEMPTION()\r\n#else\r\n\t#define taskYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()\r\n#endif\r\n\r\n/* Value that can be assigned to the eNotifyState member of the TCB. */\r\ntypedef enum\r\n{\r\n\teNotWaitingNotification = 0,\r\n\teWaitingNotification,\r\n\teNotified\r\n} eNotifyValue;\r\n\r\n/*\r\n * Task control block.  A task control block (TCB) is allocated for each task,\r\n * and stores task state information, including a pointer to the task's context\r\n * (the task's run time environment, including register values)\r\n */\r\ntypedef struct tskTaskControlBlock\r\n{\r\n\tvolatile StackType_t\t*pxTopOfStack;\t/*< Points to the location of the last item placed on the tasks stack.  THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */\r\n\r\n\t#if ( portUSING_MPU_WRAPPERS == 1 )\r\n\t\txMPU_SETTINGS\txMPUSettings;\t\t/*< The MPU settings are defined as part of the port layer.  THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */\r\n\t\tBaseType_t\t\txUsingStaticallyAllocatedStack; /* Set to pdTRUE if the stack is a statically allocated array, and pdFALSE if the stack is dynamically allocated. */\r\n\t#endif\r\n\r\n\tListItem_t\t\t\txGenericListItem;\t/*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */\r\n\tListItem_t\t\t\txEventListItem;\t\t/*< Used to reference a task from an event list. */\r\n\tUBaseType_t\t\t\tuxPriority;\t\t\t/*< The priority of the task.  0 is the lowest priority. */\r\n\tStackType_t\t\t\t*pxStack;\t\t\t/*< Points to the start of the stack. */\r\n\tchar\t\t\t\tpcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created.  Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\r\n\r\n\t#if ( portSTACK_GROWTH > 0 )\r\n\t\tStackType_t\t\t*pxEndOfStack;\t\t/*< Points to the end of the stack on architectures where the stack grows up from low memory. */\r\n\t#endif\r\n\r\n\t#if ( portCRITICAL_NESTING_IN_TCB == 1 )\r\n\t\tUBaseType_t \tuxCriticalNesting; \t/*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */\r\n\t#endif\r\n\r\n\t#if ( configUSE_TRACE_FACILITY == 1 )\r\n\t\tUBaseType_t\t\tuxTCBNumber;\t\t/*< Stores a number that increments each time a TCB is created.  It allows debuggers to determine when a task has been deleted and then recreated. */\r\n\t\tUBaseType_t  \tuxTaskNumber;\t\t/*< Stores a number specifically for use by third party trace code. */\r\n\t#endif\r\n\r\n\t#if ( configUSE_MUTEXES == 1 )\r\n\t\tUBaseType_t \tuxBasePriority;\t\t/*< The priority last assigned to the task - used by the priority inheritance mechanism. */\r\n\t\tUBaseType_t \tuxMutexesHeld;\r\n\t#endif\r\n\r\n\t#if ( configUSE_APPLICATION_TASK_TAG == 1 )\r\n\t\tTaskHookFunction_t pxTaskTag;\r\n\t#endif\r\n\r\n\t#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )\r\n\t\tvoid *pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];\r\n\t#endif\r\n\r\n\t#if ( configGENERATE_RUN_TIME_STATS == 1 )\r\n\t\tuint32_t\t\tulRunTimeCounter;\t/*< Stores the amount of time the task has spent in the Running state. */\r\n\t#endif\r\n\r\n\t#if ( configUSE_NEWLIB_REENTRANT == 1 )\r\n\t\t/* Allocate a Newlib reent structure that is specific to this task.\r\n\t\tNote Newlib support has been included by popular demand, but is not\r\n\t\tused by the FreeRTOS maintainers themselves.  FreeRTOS is not\r\n\t\tresponsible for resulting newlib operation.  User must be familiar with\r\n\t\tnewlib and must provide system-wide implementations of the necessary\r\n\t\tstubs. Be warned that (at the time of writing) the current newlib design\r\n\t\timplements a system-wide malloc() that must be provided with locks. */\r\n\t\tstruct \t_reent xNewLib_reent;\r\n\t#endif\r\n\r\n\t#if ( configUSE_TASK_NOTIFICATIONS == 1 )\r\n\t\tvolatile uint32_t ulNotifiedValue;\r\n\t\tvolatile eNotifyValue eNotifyState;\r\n\t#endif\r\n\r\n} tskTCB;\r\n\r\n/* The old tskTCB name is maintained above then typedefed to the new TCB_t name\r\nbelow to enable the use of older kernel aware debuggers. */\r\ntypedef tskTCB TCB_t;\r\n\r\n/*\r\n * Some kernel aware debuggers require the data the debugger needs access to to\r\n * be global, rather than file scope.\r\n */\r\n#ifdef portREMOVE_STATIC_QUALIFIER\r\n\t#define static\r\n#endif\r\n\r\n/*lint -e956 A manual analysis and inspection has been used to determine which\r\nstatic variables must be declared volatile. */\r\n\r\nPRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;\r\n\r\n/* Lists for ready and blocked tasks. --------------------*/\r\nPRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ];/*< Prioritised ready tasks. */\r\nPRIVILEGED_DATA static List_t xDelayedTaskList1;\t\t\t\t\t\t/*< Delayed tasks. */\r\nPRIVILEGED_DATA static List_t xDelayedTaskList2;\t\t\t\t\t\t/*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */\r\nPRIVILEGED_DATA static List_t * volatile pxDelayedTaskList;\t\t\t\t/*< Points to the delayed task list currently being used. */\r\nPRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList;\t\t/*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */\r\nPRIVILEGED_DATA static List_t xPendingReadyList;\t\t\t\t\t\t/*< Tasks that have been readied while the scheduler was suspended.  They will be moved to the ready list when the scheduler is resumed. */\r\n\r\n#if ( INCLUDE_vTaskDelete == 1 )\r\n\r\n\tPRIVILEGED_DATA static List_t xTasksWaitingTermination;\t\t\t\t/*< Tasks that have been deleted - but their memory not yet freed. */\r\n\tPRIVILEGED_DATA static volatile UBaseType_t uxTasksDeleted = ( UBaseType_t ) 0U;\r\n\r\n#endif\r\n\r\n#if ( INCLUDE_vTaskSuspend == 1 )\r\n\r\n\tPRIVILEGED_DATA static List_t xSuspendedTaskList;\t\t\t\t\t/*< Tasks that are currently suspended. */\r\n\r\n#endif\r\n\r\n#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )\r\n\r\n\tPRIVILEGED_DATA static TaskHandle_t xIdleTaskHandle = NULL;\t\t\t/*< Holds the handle of the idle task.  The idle task is created automatically when the scheduler is started. */\r\n\r\n#endif\r\n\r\n/* Other file private variables. --------------------------------*/\r\nPRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks \t= ( UBaseType_t ) 0U;\r\nPRIVILEGED_DATA static volatile TickType_t xTickCount \t\t\t\t= ( TickType_t ) 0U;\r\nPRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority \t\t= tskIDLE_PRIORITY;\r\nPRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning \t\t= pdFALSE;\r\nPRIVILEGED_DATA static volatile UBaseType_t uxPendedTicks \t\t\t= ( UBaseType_t ) 0U;\r\nPRIVILEGED_DATA static volatile BaseType_t xYieldPending \t\t\t= pdFALSE;\r\nPRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows \t\t\t= ( BaseType_t ) 0;\r\nPRIVILEGED_DATA static UBaseType_t uxTaskNumber \t\t\t\t\t= ( UBaseType_t ) 0U;\r\nPRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime\t\t= portMAX_DELAY;\r\n\r\n/* Context switches are held pending while the scheduler is suspended.  Also,\r\ninterrupts must not manipulate the xGenericListItem of a TCB, or any of the\r\nlists the xGenericListItem can be referenced from, if the scheduler is suspended.\r\nIf an interrupt needs to unblock a task while the scheduler is suspended then it\r\nmoves the task's event list item into the xPendingReadyList, ready for the\r\nkernel to move the task from the pending ready list into the real ready list\r\nwhen the scheduler is unsuspended.  The pending ready list itself can only be\r\naccessed from a critical section. */\r\nPRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended\t= ( UBaseType_t ) pdFALSE;\r\n\r\n#if ( configGENERATE_RUN_TIME_STATS == 1 )\r\n\r\n\tPRIVILEGED_DATA static uint32_t ulTaskSwitchedInTime = 0UL;\t/*< Holds the value of a timer/counter the last time a task was switched in. */\r\n\tPRIVILEGED_DATA static uint32_t ulTotalRunTime = 0UL;\t\t/*< Holds the total amount of execution time as defined by the run time counter clock. */\r\n\r\n#endif\r\n\r\n/*lint +e956 */\r\n\r\n/* Debugging and trace facilities private variables and macros. ------------*/\r\n\r\n/*\r\n * The value used to fill the stack of a task when the task is created.  This\r\n * is used purely for checking the high water mark for tasks.\r\n */\r\n#define tskSTACK_FILL_BYTE\t( 0xa5U )\r\n\r\n/*\r\n * Macros used by vListTask to indicate which state a task is in.\r\n */\r\n#define tskBLOCKED_CHAR\t\t( 'B' )\r\n#define tskREADY_CHAR\t\t( 'R' )\r\n#define tskDELETED_CHAR\t\t( 'D' )\r\n#define tskSUSPENDED_CHAR\t( 'S' )\r\n\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )\r\n\r\n\t/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 0 then task selection is\r\n\tperformed in a generic way that is not optimised to any particular\r\n\tmicrocontroller architecture. */\r\n\r\n\t/* uxTopReadyPriority holds the priority of the highest priority ready\r\n\tstate task. */\r\n\t#define taskRECORD_READY_PRIORITY( uxPriority )\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\tif( ( uxPriority ) > uxTopReadyPriority )\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t\tuxTopReadyPriority = ( uxPriority );\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t} /* taskRECORD_READY_PRIORITY */\r\n\r\n\t/*-----------------------------------------------------------*/\r\n\r\n\t#define taskSELECT_HIGHEST_PRIORITY_TASK()\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t/* Find the highest priority queue that contains ready tasks. */\t\t\t\t\t\t\t\t\\\r\n\t\twhile( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopReadyPriority ] ) ) )\t\t\t\t\t\t\\\r\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t\tconfigASSERT( uxTopReadyPriority );\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t\t--uxTopReadyPriority;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t/* listGET_OWNER_OF_NEXT_ENTRY indexes through the list, so the tasks of\t\t\t\t\t\t\\\r\n\t\tthe\tsame priority get an equal share of the processor time. */\t\t\t\t\t\t\t\t\t\\\r\n\t\tlistGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopReadyPriority ] ) );\t\t\\\r\n\t} /* taskSELECT_HIGHEST_PRIORITY_TASK */\r\n\r\n\t/*-----------------------------------------------------------*/\r\n\r\n\t/* Define away taskRESET_READY_PRIORITY() and portRESET_READY_PRIORITY() as\r\n\tthey are only required when a port optimised method of task selection is\r\n\tbeing used. */\r\n\t#define taskRESET_READY_PRIORITY( uxPriority )\r\n\t#define portRESET_READY_PRIORITY( uxPriority, uxTopReadyPriority )\r\n\r\n#else /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\r\n\r\n\t/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 1 then task selection is\r\n\tperformed in a way that is tailored to the particular microcontroller\r\n\tarchitecture being used. */\r\n\r\n\t/* A port optimised version is provided.  Call the port defined macros. */\r\n\t#define taskRECORD_READY_PRIORITY( uxPriority )\tportRECORD_READY_PRIORITY( uxPriority, uxTopReadyPriority )\r\n\r\n\t/*-----------------------------------------------------------*/\r\n\r\n\t#define taskSELECT_HIGHEST_PRIORITY_TASK()\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\tUBaseType_t uxTopPriority;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t/* Find the highest priority queue that contains ready tasks. */\t\t\t\t\t\t\t\\\r\n\t\tportGET_HIGHEST_PRIORITY( uxTopPriority, uxTopReadyPriority );\t\t\t\t\t\t\t\t\\\r\n\t\tconfigASSERT( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ uxTopPriority ] ) ) > 0 );\t\t\\\r\n\t\tlistGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );\t\t\\\r\n\t} /* taskSELECT_HIGHEST_PRIORITY_TASK() */\r\n\r\n\t/*-----------------------------------------------------------*/\r\n\r\n\t/* A port optimised version is provided, call it only if the TCB being reset\r\n\tis being referenced from a ready list.  If it is referenced from a delayed\r\n\tor suspended list then it won't be in a ready list. */\r\n\t#define taskRESET_READY_PRIORITY( uxPriority )\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\tif( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ ( uxPriority ) ] ) ) == ( UBaseType_t ) 0 )\t\\\r\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t\tportRESET_READY_PRIORITY( ( uxPriority ), ( uxTopReadyPriority ) );\t\t\t\t\t\t\t\\\r\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t}\r\n\r\n#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\r\n\r\n/*-----------------------------------------------------------*/\r\n\r\n/* pxDelayedTaskList and pxOverflowDelayedTaskList are switched when the tick\r\ncount overflows. */\r\n#define taskSWITCH_DELAYED_LISTS()\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\tList_t *pxTemp;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\t/* The delayed tasks list should be empty when the lists are switched. */\t\t\t\t\t\t\\\r\n\tconfigASSERT( ( listLIST_IS_EMPTY( pxDelayedTaskList ) ) );\t\t\t\t\t\t\t\t\t\t\\\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\tpxTemp = pxDelayedTaskList;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\tpxDelayedTaskList = pxOverflowDelayedTaskList;\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\tpxOverflowDelayedTaskList = pxTemp;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\txNumOfOverflows++;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\tprvResetNextTaskUnblockTime();\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n}\r\n\r\n/*-----------------------------------------------------------*/\r\n\r\n/*\r\n * Place the task represented by pxTCB into the appropriate ready list for\r\n * the task.  It is inserted at the end of the list.\r\n */\r\n#define prvAddTaskToReadyList( pxTCB )\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\ttraceMOVED_TASK_TO_READY_STATE( pxTCB );\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\ttaskRECORD_READY_PRIORITY( ( pxTCB )->uxPriority );\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n\tvListInsertEnd( &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xGenericListItem ) )\r\n/*-----------------------------------------------------------*/\r\n\r\n/*\r\n * Several functions take an TaskHandle_t parameter that can optionally be NULL,\r\n * where NULL is used to indicate that the handle of the currently executing\r\n * task should be used in place of the parameter.  This macro simply checks to\r\n * see if the parameter is NULL and returns a pointer to the appropriate TCB.\r\n */\r\n#define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? ( TCB_t * ) pxCurrentTCB : ( TCB_t * ) ( pxHandle ) )\r\n\r\n/* The item value of the event list item is normally used to hold the priority\r\nof the task to which it belongs (coded to allow it to be held in reverse\r\npriority order).  However, it is occasionally borrowed for other purposes.  It\r\nis important its value is not updated due to a task priority change while it is\r\nbeing used for another purpose.  The following bit definition is used to inform\r\nthe scheduler that the value should not be changed - in which case it is the\r\nresponsibility of whichever module is using the value to ensure it gets set back\r\nto its original value when it is released. */\r\n#if configUSE_16_BIT_TICKS == 1\r\n\t#define taskEVENT_LIST_ITEM_VALUE_IN_USE\t0x8000U\r\n#else\r\n\t#define taskEVENT_LIST_ITEM_VALUE_IN_USE\t0x80000000UL\r\n#endif\r\n\r\n/* Callback function prototypes. --------------------------*/\r\n#if configCHECK_FOR_STACK_OVERFLOW > 0\r\n\textern void vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName );\r\n#endif\r\n\r\n#if configUSE_TICK_HOOK > 0\r\n\textern void vApplicationTickHook( void );\r\n#endif\r\n\r\n/* File private functions. --------------------------------*/\r\n\r\n/*\r\n * Utility to ready a TCB for a given task.  Mainly just copies the parameters\r\n * into the TCB structure.\r\n */\r\nstatic void prvInitialiseTCBVariables( TCB_t * const pxTCB, const char * const pcName, UBaseType_t uxPriority, const MemoryRegion_t * const xRegions, const uint16_t usStackDepth ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\r\n\r\n/**\r\n * Utility task that simply returns pdTRUE if the task referenced by xTask is\r\n * currently in the Suspended state, or pdFALSE if the task referenced by xTask\r\n * is in any other state.\r\n */\r\n#if ( INCLUDE_vTaskSuspend == 1 )\r\n\tstatic BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\r\n#endif /* INCLUDE_vTaskSuspend */\r\n\r\n/*\r\n * Utility to ready all the lists used by the scheduler.  This is called\r\n * automatically upon the creation of the first task.\r\n */\r\nstatic void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * The idle task, which as all tasks is implemented as a never ending loop.\r\n * The idle task is automatically created and added to the ready lists upon\r\n * creation of the first user task.\r\n *\r\n * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific\r\n * language extensions.  The equivalent prototype for this function is:\r\n *\r\n * void prvIdleTask( void *pvParameters );\r\n *\r\n */\r\nstatic portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters );\r\n\r\n/*\r\n * Utility to free all memory allocated by the scheduler to hold a TCB,\r\n * including the stack pointed to by the TCB.\r\n *\r\n * This does not free memory allocated by the task itself (i.e. memory\r\n * allocated by calls to pvPortMalloc from within the tasks application code).\r\n */\r\n#if ( INCLUDE_vTaskDelete == 1 )\r\n\r\n\tstatic void prvDeleteTCB( TCB_t *pxTCB ) PRIVILEGED_FUNCTION;\r\n\r\n#endif\r\n\r\n/*\r\n * Used only by the idle task.  This checks to see if anything has been placed\r\n * in the list of tasks waiting to be deleted.  If so the task is cleaned up\r\n * and its TCB deleted.\r\n */\r\nstatic void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * The currently executing task is entering the Blocked state.  Add the task to\r\n * either the current or the overflow delayed task list.\r\n */\r\nstatic void prvAddCurrentTaskToDelayedList( const TickType_t xTimeToWake ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * Allocates memory from the heap for a TCB and associated stack.  Checks the\r\n * allocation was successful.\r\n */\r\nstatic TCB_t *prvAllocateTCBAndStack( const uint16_t usStackDepth, StackType_t * const puxStackBuffer ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * Fills an TaskStatus_t structure with information on each task that is\r\n * referenced from the pxList list (which may be a ready list, a delayed list,\r\n * a suspended list, etc.).\r\n *\r\n * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM\r\n * NORMAL APPLICATION CODE.\r\n */\r\n#if ( configUSE_TRACE_FACILITY == 1 )\r\n\r\n\tstatic UBaseType_t prvListTaskWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState ) PRIVILEGED_FUNCTION;\r\n\r\n#endif\r\n\r\n/*\r\n * When a task is created, the stack of the task is filled with a known value.\r\n * This function determines the 'high water mark' of the task stack by\r\n * determining how much of the stack remains at the original preset value.\r\n */\r\n#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )\r\n\r\n\tstatic uint16_t prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION;\r\n\r\n#endif\r\n\r\n/*\r\n * Return the amount of time, in ticks, that will pass before the kernel will\r\n * next move a task from the Blocked state to the Running state.\r\n *\r\n * This conditional compilation should use inequality to 0, not equality to 1.\r\n * This is to ensure portSUPPRESS_TICKS_AND_SLEEP() can be called when user\r\n * defined low power mode implementations require configUSE_TICKLESS_IDLE to be\r\n * set to a value other than 1.\r\n */\r\n#if ( configUSE_TICKLESS_IDLE != 0 )\r\n\r\n\tstatic TickType_t prvGetExpectedIdleTime( void ) PRIVILEGED_FUNCTION;\r\n\r\n#endif\r\n\r\n/*\r\n * Set xNextTaskUnblockTime to the time at which the next Blocked state task\r\n * will exit the Blocked state.\r\n */\r\nstatic void prvResetNextTaskUnblockTime( void );\r\n\r\n#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )\r\n\r\n\t/*\r\n\t * Helper function used to pad task names with spaces when printing out\r\n\t * human readable tables of task information.\r\n\t */\r\n\tstatic char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName );\r\n\r\n#endif\r\n/*-----------------------------------------------------------*/\r\n\r\nBaseType_t xTaskGenericCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask, StackType_t * const puxStackBuffer, const MemoryRegion_t * const xRegions ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\r\n{\r\nBaseType_t xReturn;\r\nTCB_t * pxNewTCB;\r\nStackType_t *pxTopOfStack;\r\n\r\n\tconfigASSERT( pxTaskCode );\r\n\tconfigASSERT( ( ( uxPriority & ( UBaseType_t ) ( ~portPRIVILEGE_BIT ) ) < ( UBaseType_t ) configMAX_PRIORITIES ) );\r\n\r\n\t/* Allocate the memory required by the TCB and stack for the new task,\r\n\tchecking that the allocation was successful. */\r\n\tpxNewTCB = prvAllocateTCBAndStack( usStackDepth, puxStackBuffer );\r\n\r\n\tif( pxNewTCB != NULL )\r\n\t{\r\n\t\t#if( portUSING_MPU_WRAPPERS == 1 )\r\n\t\t\t/* Should the task be created in privileged mode? */\r\n\t\t\tBaseType_t xRunPrivileged;\r\n\t\t\tif( ( uxPriority & portPRIVILEGE_BIT ) != 0U )\r\n\t\t\t{\r\n\t\t\t\txRunPrivileged = pdTRUE;\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\txRunPrivileged = pdFALSE;\r\n\t\t\t}\r\n\t\t\tuxPriority &= ~portPRIVILEGE_BIT;\r\n\r\n\t\t\tif( puxStackBuffer != NULL )\r\n\t\t\t{\r\n\t\t\t\t/* The application provided its own stack.  Note this so no\r\n\t\t\t\tattempt is made to delete the stack should that task be\r\n\t\t\t\tdeleted. */\r\n\t\t\t\tpxNewTCB->xUsingStaticallyAllocatedStack = pdTRUE;\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\t/* The stack was allocated dynamically.  Note this so it can be\r\n\t\t\t\tdeleted again if the task is deleted. */\r\n\t\t\t\tpxNewTCB->xUsingStaticallyAllocatedStack = pdFALSE;\r\n\t\t\t}\r\n\t\t#endif /* portUSING_MPU_WRAPPERS == 1 */\r\n\r\n\t\t/* Calculate the top of stack address.  This depends on whether the\r\n\t\tstack grows from high memory to low (as per the 80x86) or vice versa.\r\n\t\tportSTACK_GROWTH is used to make the result positive or negative as\r\n\t\trequired by the port. */\r\n\t\t#if( portSTACK_GROWTH < 0 )\r\n\t\t{\r\n\t\t\tpxTopOfStack = pxNewTCB->pxStack + ( usStackDepth - ( uint16_t ) 1 );\r\n\t\t\tpxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 MISRA exception.  Avoiding casts between pointers and integers is not practical.  Size differences accounted for using portPOINTER_SIZE_TYPE type. */\r\n\r\n\t\t\t/* Check the alignment of the calculated top of stack is correct. */\r\n\t\t\tconfigASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );\r\n\t\t}\r\n\t\t#else /* portSTACK_GROWTH */\r\n\t\t{\r\n\t\t\tpxTopOfStack = pxNewTCB->pxStack;\r\n\r\n\t\t\t/* Check the alignment of the stack buffer is correct. */\r\n\t\t\tconfigASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxNewTCB->pxStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );\r\n\r\n\t\t\t/* If we want to use stack checking on architectures that use\r\n\t\t\ta positive stack growth direction then we also need to store the\r\n\t\t\tother extreme of the stack space. */\r\n\t\t\tpxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( usStackDepth - 1 );\r\n\t\t}\r\n\t\t#endif /* portSTACK_GROWTH */\r\n\r\n\t\t/* Setup the newly allocated TCB with the initial state of the task. */\r\n\t\tprvInitialiseTCBVariables( pxNewTCB, pcName, uxPriority, xRegions, usStackDepth );\r\n\r\n\t\t/* Initialize the TCB stack to look as if the task was already running,\r\n\t\tbut had been interrupted by the scheduler.  The return address is set\r\n\t\tto the start of the task function. Once the stack has been initialised\r\n\t\tthe\ttop of stack variable is updated. */\r\n\t\t#if( portUSING_MPU_WRAPPERS == 1 )\r\n\t\t{\r\n\t\t\tpxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );\r\n\t\t}\r\n\t\t#else /* portUSING_MPU_WRAPPERS */\r\n\t\t{\r\n\t\t\tpxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );\r\n\t\t}\r\n\t\t#endif /* portUSING_MPU_WRAPPERS */\r\n\r\n\t\tif( ( void * ) pxCreatedTask != NULL )\r\n\t\t{\r\n\t\t\t/* Pass the TCB out - in an anonymous way.  The calling function/\r\n\t\t\ttask can use this as a handle to delete the task later if\r\n\t\t\trequired.*/\r\n\t\t\t*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t}\r\n\r\n\t\t/* Ensure interrupts don't access the task lists while they are being\r\n\t\tupdated. */\r\n\t\ttaskENTER_CRITICAL();\r\n\t\t{\r\n\t\t\tuxCurrentNumberOfTasks++;\r\n\t\t\tif( pxCurrentTCB == NULL )\r\n\t\t\t{\r\n\t\t\t\t/* There are no other tasks, or all the other tasks are in\r\n\t\t\t\tthe suspended state - make this the current task. */\r\n\t\t\t\tpxCurrentTCB =  pxNewTCB;\r\n\r\n\t\t\t\tif( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )\r\n\t\t\t\t{\r\n\t\t\t\t\t/* This is the first task to be created so do the preliminary\r\n\t\t\t\t\tinitialisation required.  We will not recover if this call\r\n\t\t\t\t\tfails, but we will report the failure. */\r\n\t\t\t\t\tprvInitialiseTaskLists();\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\t/* If the scheduler is not already running, make this task the\r\n\t\t\t\tcurrent task if it is the highest priority task to be created\r\n\t\t\t\tso far. */\r\n\t\t\t\tif( xSchedulerRunning == pdFALSE )\r\n\t\t\t\t{\r\n\t\t\t\t\tif( pxCurrentTCB->uxPriority <= uxPriority )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tpxCurrentTCB = pxNewTCB;\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\t\t\t}\r\n\r\n\t\t\tuxTaskNumber++;\r\n\r\n\t\t\t#if ( configUSE_TRACE_FACILITY == 1 )\r\n\t\t\t{\r\n\t\t\t\t/* Add a counter into the TCB for tracing only. */\r\n\t\t\t\tpxNewTCB->uxTCBNumber = uxTaskNumber;\r\n\t\t\t}\r\n\t\t\t#endif /* configUSE_TRACE_FACILITY */\r\n\t\t\ttraceTASK_CREATE( pxNewTCB );\r\n\r\n\t\t\tprvAddTaskToReadyList( pxNewTCB );\r\n\r\n\t\t\txReturn = pdPASS;\r\n\t\t\tportSETUP_TCB( pxNewTCB );\r\n\t\t}\r\n\t\ttaskEXIT_CRITICAL();\r\n\t}\r\n\telse\r\n\t{\r\n\t\txReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;\r\n\t\ttraceTASK_CREATE_FAILED();\r\n\t}\r\n\r\n\tif( xReturn == pdPASS )\r\n\t{\r\n\t\tif( xSchedulerRunning != pdFALSE )\r\n\t\t{\r\n\t\t\t/* If the created task is of a higher priority than the current task\r\n\t\t\tthen it should run now. */\r\n\t\t\tif( pxCurrentTCB->uxPriority < uxPriority )\r\n\t\t\t{\r\n\t\t\t\ttaskYIELD_IF_USING_PREEMPTION();\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t}\r\n\t}\r\n\r\n\treturn xReturn;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( INCLUDE_vTaskDelete == 1 )\r\n\r\n\tvoid vTaskDelete( TaskHandle_t xTaskToDelete )\r\n\t{\r\n\tTCB_t *pxTCB;\r\n\r\n\t\ttaskENTER_CRITICAL();\r\n\t\t{\r\n\t\t\t/* If null is passed in here then it is the calling task that is\r\n\t\t\tbeing deleted. */\r\n\t\t\tpxTCB = prvGetTCBFromHandle( xTaskToDelete );\r\n\r\n\t\t\t/* Remove task from the ready list and place in the\ttermination list.\r\n\t\t\tThis will stop the task from be scheduled.  The idle task will check\r\n\t\t\tthe termination list and free up any memory allocated by the\r\n\t\t\tscheduler for the TCB and stack. */\r\n\t\t\tif( uxListRemove( &( pxTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r\n\t\t\t{\r\n\t\t\t\ttaskRESET_READY_PRIORITY( pxTCB->uxPriority );\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\r\n\t\t\t/* Is the task waiting on an event also? */\r\n\t\t\tif( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )\r\n\t\t\t{\r\n\t\t\t\t( void ) uxListRemove( &( pxTCB->xEventListItem ) );\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\r\n\t\t\tvListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xGenericListItem ) );\r\n\r\n\t\t\t/* Increment the ucTasksDeleted variable so the idle task knows\r\n\t\t\tthere is a task that has been deleted and that it should therefore\r\n\t\t\tcheck the xTasksWaitingTermination list. */\r\n\t\t\t++uxTasksDeleted;\r\n\r\n\t\t\t/* Increment the uxTaskNumberVariable also so kernel aware debuggers\r\n\t\t\tcan detect that the task lists need re-generating. */\r\n\t\t\tuxTaskNumber++;\r\n\r\n\t\t\ttraceTASK_DELETE( pxTCB );\r\n\t\t}\r\n\t\ttaskEXIT_CRITICAL();\r\n\r\n\t\t/* Force a reschedule if it is the currently running task that has just\r\n\t\tbeen deleted. */\r\n\t\tif( xSchedulerRunning != pdFALSE )\r\n\t\t{\r\n\t\t\tif( pxTCB == pxCurrentTCB )\r\n\t\t\t{\r\n\t\t\t\tconfigASSERT( uxSchedulerSuspended == 0 );\r\n\r\n\t\t\t\t/* The pre-delete hook is primarily for the Windows simulator,\r\n\t\t\t\tin which Windows specific clean up operations are performed,\r\n\t\t\t\tafter which it is not possible to yield away from this task -\r\n\t\t\t\thence xYieldPending is used to latch that a context switch is\r\n\t\t\t\trequired. */\r\n\t\t\t\tportPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending );\r\n\t\t\t\tportYIELD_WITHIN_API();\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\t/* Reset the next expected unblock time in case it referred to\r\n\t\t\t\tthe task that has just been deleted. */\r\n\t\t\t\ttaskENTER_CRITICAL();\r\n\t\t\t\t{\r\n\t\t\t\t\tprvResetNextTaskUnblockTime();\r\n\t\t\t\t}\r\n\t\t\t\ttaskEXIT_CRITICAL();\r\n\t\t\t}\r\n\t\t}\r\n\t}\r\n\r\n#endif /* INCLUDE_vTaskDelete */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( INCLUDE_vTaskDelayUntil == 1 )\r\n\r\n\tvoid vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement )\r\n\t{\r\n\tTickType_t xTimeToWake;\r\n\tBaseType_t xAlreadyYielded, xShouldDelay = pdFALSE;\r\n\r\n\t\tconfigASSERT( pxPreviousWakeTime );\r\n\t\tconfigASSERT( ( xTimeIncrement > 0U ) );\r\n\t\tconfigASSERT( uxSchedulerSuspended == 0 );\r\n\r\n\t\tvTaskSuspendAll();\r\n\t\t{\r\n\t\t\t/* Minor optimisation.  The tick count cannot change in this\r\n\t\t\tblock. */\r\n\t\t\tconst TickType_t xConstTickCount = xTickCount;\r\n\r\n\t\t\t/* Generate the tick time at which the task wants to wake. */\r\n\t\t\txTimeToWake = *pxPreviousWakeTime + xTimeIncrement;\r\n\r\n\t\t\tif( xConstTickCount < *pxPreviousWakeTime )\r\n\t\t\t{\r\n\t\t\t\t/* The tick count has overflowed since this function was\r\n\t\t\t\tlasted called.  In this case the only time we should ever\r\n\t\t\t\tactually delay is if the wake time has also\toverflowed,\r\n\t\t\t\tand the wake time is greater than the tick time.  When this\r\n\t\t\t\tis the case it is as if neither time had overflowed. */\r\n\t\t\t\tif( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xConstTickCount ) )\r\n\t\t\t\t{\r\n\t\t\t\t\txShouldDelay = pdTRUE;\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\t/* The tick time has not overflowed.  In this case we will\r\n\t\t\t\tdelay if either the wake time has overflowed, and/or the\r\n\t\t\t\ttick time is less than the wake time. */\r\n\t\t\t\tif( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xConstTickCount ) )\r\n\t\t\t\t{\r\n\t\t\t\t\txShouldDelay = pdTRUE;\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\t\t\t}\r\n\r\n\t\t\t/* Update the wake time ready for the next call. */\r\n\t\t\t*pxPreviousWakeTime = xTimeToWake;\r\n\r\n\t\t\tif( xShouldDelay != pdFALSE )\r\n\t\t\t{\r\n\t\t\t\ttraceTASK_DELAY_UNTIL();\r\n\r\n\t\t\t\t/* Remove the task from the ready list before adding it to the\r\n\t\t\t\tblocked list as the same list item is used for both lists. */\r\n\t\t\t\tif( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r\n\t\t\t\t{\r\n\t\t\t\t\t/* The current task must be in a ready list, so there is\r\n\t\t\t\t\tno need to check, and the port reset macro can be called\r\n\t\t\t\t\tdirectly. */\r\n\t\t\t\t\tportRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\r\n\t\t\t\tprvAddCurrentTaskToDelayedList( xTimeToWake );\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\t\t}\r\n\t\txAlreadyYielded = xTaskResumeAll();\r\n\r\n\t\t/* Force a reschedule if xTaskResumeAll has not already done so, we may\r\n\t\thave put ourselves to sleep. */\r\n\t\tif( xAlreadyYielded == pdFALSE )\r\n\t\t{\r\n\t\t\tportYIELD_WITHIN_API();\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t}\r\n\t}\r\n\r\n#endif /* INCLUDE_vTaskDelayUntil */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( INCLUDE_vTaskDelay == 1 )\r\n\r\n\tvoid vTaskDelay( const TickType_t xTicksToDelay )\r\n\t{\r\n\tTickType_t xTimeToWake;\r\n\tBaseType_t xAlreadyYielded = pdFALSE;\r\n\r\n\r\n\t\t/* A delay time of zero just forces a reschedule. */\r\n\t\tif( xTicksToDelay > ( TickType_t ) 0U )\r\n\t\t{\r\n\t\t\tconfigASSERT( uxSchedulerSuspended == 0 );\r\n\t\t\tvTaskSuspendAll();\r\n\t\t\t{\r\n\t\t\t\ttraceTASK_DELAY();\r\n\r\n\t\t\t\t/* A task that is removed from the event list while the\r\n\t\t\t\tscheduler is suspended will not get placed in the ready\r\n\t\t\t\tlist or removed from the blocked list until the scheduler\r\n\t\t\t\tis resumed.\r\n\r\n\t\t\t\tThis task cannot be in an event list as it is the currently\r\n\t\t\t\texecuting task. */\r\n\r\n\t\t\t\t/* Calculate the time to wake - this may overflow but this is\r\n\t\t\t\tnot a problem. */\r\n\t\t\t\txTimeToWake = xTickCount + xTicksToDelay;\r\n\r\n\t\t\t\t/* We must remove ourselves from the ready list before adding\r\n\t\t\t\tourselves to the blocked list as the same list item is used for\r\n\t\t\t\tboth lists. */\r\n\t\t\t\tif( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r\n\t\t\t\t{\r\n\t\t\t\t\t/* The current task must be in a ready list, so there is\r\n\t\t\t\t\tno need to check, and the port reset macro can be called\r\n\t\t\t\t\tdirectly. */\r\n\t\t\t\t\tportRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\t\t\t\tprvAddCurrentTaskToDelayedList( xTimeToWake );\r\n\t\t\t}\r\n\t\t\txAlreadyYielded = xTaskResumeAll();\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t}\r\n\r\n\t\t/* Force a reschedule if xTaskResumeAll has not already done so, we may\r\n\t\thave put ourselves to sleep. */\r\n\t\tif( xAlreadyYielded == pdFALSE )\r\n\t\t{\r\n\t\t\tportYIELD_WITHIN_API();\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t}\r\n\t}\r\n\r\n#endif /* INCLUDE_vTaskDelay */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( INCLUDE_eTaskGetState == 1 )\r\n\r\n\teTaskState eTaskGetState( TaskHandle_t xTask )\r\n\t{\r\n\teTaskState eReturn;\r\n\tList_t *pxStateList;\r\n\tconst TCB_t * const pxTCB = ( TCB_t * ) xTask;\r\n\r\n\t\tconfigASSERT( pxTCB );\r\n\r\n\t\tif( pxTCB == pxCurrentTCB )\r\n\t\t{\r\n\t\t\t/* The task calling this function is querying its own state. */\r\n\t\t\teReturn = eRunning;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\ttaskENTER_CRITICAL();\r\n\t\t\t{\r\n\t\t\t\tpxStateList = ( List_t * ) listLIST_ITEM_CONTAINER( &( pxTCB->xGenericListItem ) );\r\n\t\t\t}\r\n\t\t\ttaskEXIT_CRITICAL();\r\n\r\n\t\t\tif( ( pxStateList == pxDelayedTaskList ) || ( pxStateList == pxOverflowDelayedTaskList ) )\r\n\t\t\t{\r\n\t\t\t\t/* The task being queried is referenced from one of the Blocked\r\n\t\t\t\tlists. */\r\n\t\t\t\teReturn = eBlocked;\r\n\t\t\t}\r\n\r\n\t\t\t#if ( INCLUDE_vTaskSuspend == 1 )\r\n\t\t\t\telse if( pxStateList == &xSuspendedTaskList )\r\n\t\t\t\t{\r\n\t\t\t\t\t/* The task being queried is referenced from the suspended\r\n\t\t\t\t\tlist.  Is it genuinely suspended or is it block\r\n\t\t\t\t\tindefinitely? */\r\n\t\t\t\t\tif( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\teReturn = eSuspended;\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\teReturn = eBlocked;\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t#endif\r\n\r\n\t\t\t#if ( INCLUDE_vTaskDelete == 1 )\r\n\t\t\t\telse if( pxStateList == &xTasksWaitingTermination )\r\n\t\t\t\t{\r\n\t\t\t\t\t/* The task being queried is referenced from the deleted\r\n\t\t\t\t\ttasks list. */\r\n\t\t\t\t\teReturn = eDeleted;\r\n\t\t\t\t}\r\n\t\t\t#endif\r\n\r\n\t\t\telse /*lint !e525 Negative indentation is intended to make use of pre-processor clearer. */\r\n\t\t\t{\r\n\t\t\t\t/* If the task is not in any other state, it must be in the\r\n\t\t\t\tReady (including pending ready) state. */\r\n\t\t\t\teReturn = eReady;\r\n\t\t\t}\r\n\t\t}\r\n\r\n\t\treturn eReturn;\r\n\t} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */\r\n\r\n#endif /* INCLUDE_eTaskGetState */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( INCLUDE_uxTaskPriorityGet == 1 )\r\n\r\n\tUBaseType_t uxTaskPriorityGet( TaskHandle_t xTask )\r\n\t{\r\n\tTCB_t *pxTCB;\r\n\tUBaseType_t uxReturn;\r\n\r\n\t\ttaskENTER_CRITICAL();\r\n\t\t{\r\n\t\t\t/* If null is passed in here then we are changing the\r\n\t\t\tpriority of the calling function. */\r\n\t\t\tpxTCB = prvGetTCBFromHandle( xTask );\r\n\t\t\tuxReturn = pxTCB->uxPriority;\r\n\t\t}\r\n\t\ttaskEXIT_CRITICAL();\r\n\r\n\t\treturn uxReturn;\r\n\t}\r\n\r\n#endif /* INCLUDE_uxTaskPriorityGet */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( INCLUDE_uxTaskPriorityGet == 1 )\r\n\r\n\tUBaseType_t uxTaskPriorityGetFromISR( TaskHandle_t xTask )\r\n\t{\r\n\tTCB_t *pxTCB;\r\n\tUBaseType_t uxReturn, uxSavedInterruptState;\r\n\r\n\t\t/* RTOS ports that support interrupt nesting have the concept of a\r\n\t\tmaximum\tsystem call (or maximum API call) interrupt priority.\r\n\t\tInterrupts that are\tabove the maximum system call priority are keep\r\n\t\tpermanently enabled, even when the RTOS kernel is in a critical section,\r\n\t\tbut cannot make any calls to FreeRTOS API functions.  If configASSERT()\r\n\t\tis defined in FreeRTOSConfig.h then\r\n\t\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\r\n\t\tfailure if a FreeRTOS API function is called from an interrupt that has\r\n\t\tbeen assigned a priority above the configured maximum system call\r\n\t\tpriority.  Only FreeRTOS functions that end in FromISR can be called\r\n\t\tfrom interrupts\tthat have been assigned a priority at or (logically)\r\n\t\tbelow the maximum system call interrupt priority.  FreeRTOS maintains a\r\n\t\tseparate interrupt safe API to ensure interrupt entry is as fast and as\r\n\t\tsimple as possible.  More information (albeit Cortex-M specific) is\r\n\t\tprovided on the following link:\r\n\t\thttp://www.freertos.org/RTOS-Cortex-M3-M4.html */\r\n\t\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID();\r\n\r\n\t\tuxSavedInterruptState = portSET_INTERRUPT_MASK_FROM_ISR();\r\n\t\t{\r\n\t\t\t/* If null is passed in here then it is the priority of the calling\r\n\t\t\ttask that is being queried. */\r\n\t\t\tpxTCB = prvGetTCBFromHandle( xTask );\r\n\t\t\tuxReturn = pxTCB->uxPriority;\r\n\t\t}\r\n\t\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptState );\r\n\r\n\t\treturn uxReturn;\r\n\t}\r\n\r\n#endif /* INCLUDE_uxTaskPriorityGet */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( INCLUDE_vTaskPrioritySet == 1 )\r\n\r\n\tvoid vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority )\r\n\t{\r\n\tTCB_t *pxTCB;\r\n\tUBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry;\r\n\tBaseType_t xYieldRequired = pdFALSE;\r\n\r\n\t\tconfigASSERT( ( uxNewPriority < configMAX_PRIORITIES ) );\r\n\r\n\t\t/* Ensure the new priority is valid. */\r\n\t\tif( uxNewPriority >= ( UBaseType_t ) configMAX_PRIORITIES )\r\n\t\t{\r\n\t\t\tuxNewPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t}\r\n\r\n\t\ttaskENTER_CRITICAL();\r\n\t\t{\r\n\t\t\t/* If null is passed in here then it is the priority of the calling\r\n\t\t\ttask that is being changed. */\r\n\t\t\tpxTCB = prvGetTCBFromHandle( xTask );\r\n\r\n\t\t\ttraceTASK_PRIORITY_SET( pxTCB, uxNewPriority );\r\n\r\n\t\t\t#if ( configUSE_MUTEXES == 1 )\r\n\t\t\t{\r\n\t\t\t\tuxCurrentBasePriority = pxTCB->uxBasePriority;\r\n\t\t\t}\r\n\t\t\t#else\r\n\t\t\t{\r\n\t\t\t\tuxCurrentBasePriority = pxTCB->uxPriority;\r\n\t\t\t}\r\n\t\t\t#endif\r\n\r\n\t\t\tif( uxCurrentBasePriority != uxNewPriority )\r\n\t\t\t{\r\n\t\t\t\t/* The priority change may have readied a task of higher\r\n\t\t\t\tpriority than the calling task. */\r\n\t\t\t\tif( uxNewPriority > uxCurrentBasePriority )\r\n\t\t\t\t{\r\n\t\t\t\t\tif( pxTCB != pxCurrentTCB )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t/* The priority of a task other than the currently\r\n\t\t\t\t\t\trunning task is being raised.  Is the priority being\r\n\t\t\t\t\t\traised above that of the running task? */\r\n\t\t\t\t\t\tif( uxNewPriority >= pxCurrentTCB->uxPriority )\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\txYieldRequired = pdTRUE;\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\telse\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t/* The priority of the running task is being raised,\r\n\t\t\t\t\t\tbut the running task must already be the highest\r\n\t\t\t\t\t\tpriority task able to run so no yield is required. */\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t\telse if( pxTCB == pxCurrentTCB )\r\n\t\t\t\t{\r\n\t\t\t\t\t/* Setting the priority of the running task down means\r\n\t\t\t\t\tthere may now be another task of higher priority that\r\n\t\t\t\t\tis ready to execute. */\r\n\t\t\t\t\txYieldRequired = pdTRUE;\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\t/* Setting the priority of any other task down does not\r\n\t\t\t\t\trequire a yield as the running task must be above the\r\n\t\t\t\t\tnew priority of the task being modified. */\r\n\t\t\t\t}\r\n\r\n\t\t\t\t/* Remember the ready list the task might be referenced from\r\n\t\t\t\tbefore its uxPriority member is changed so the\r\n\t\t\t\ttaskRESET_READY_PRIORITY() macro can function correctly. */\r\n\t\t\t\tuxPriorityUsedOnEntry = pxTCB->uxPriority;\r\n\r\n\t\t\t\t#if ( configUSE_MUTEXES == 1 )\r\n\t\t\t\t{\r\n\t\t\t\t\t/* Only change the priority being used if the task is not\r\n\t\t\t\t\tcurrently using an inherited priority. */\r\n\t\t\t\t\tif( pxTCB->uxBasePriority == pxTCB->uxPriority )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tpxTCB->uxPriority = uxNewPriority;\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t}\r\n\r\n\t\t\t\t\t/* The base priority gets set whatever. */\r\n\t\t\t\t\tpxTCB->uxBasePriority = uxNewPriority;\r\n\t\t\t\t}\r\n\t\t\t\t#else\r\n\t\t\t\t{\r\n\t\t\t\t\tpxTCB->uxPriority = uxNewPriority;\r\n\t\t\t\t}\r\n\t\t\t\t#endif\r\n\r\n\t\t\t\t/* Only reset the event list item value if the value is not\r\n\t\t\t\tbeing used for anything else. */\r\n\t\t\t\tif( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )\r\n\t\t\t\t{\r\n\t\t\t\t\tlistSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\r\n\t\t\t\t/* If the task is in the blocked or suspended list we need do\r\n\t\t\t\tnothing more than change it's priority variable. However, if\r\n\t\t\t\tthe task is in a ready list it needs to be removed and placed\r\n\t\t\t\tin the list appropriate to its new priority. */\r\n\t\t\t\tif( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xGenericListItem ) ) != pdFALSE )\r\n\t\t\t\t{\r\n\t\t\t\t\t/* The task is currently in its ready list - remove before adding\r\n\t\t\t\t\tit to it's new ready list.  As we are in a critical section we\r\n\t\t\t\t\tcan do this even if the scheduler is suspended. */\r\n\t\t\t\t\tif( uxListRemove( &( pxTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t/* It is known that the task is in its ready list so\r\n\t\t\t\t\t\tthere is no need to check again and the port level\r\n\t\t\t\t\t\treset macro can be called directly. */\r\n\t\t\t\t\t\tportRESET_READY_PRIORITY( uxPriorityUsedOnEntry, uxTopReadyPriority );\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t}\r\n\t\t\t\t\tprvAddTaskToReadyList( pxTCB );\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\r\n\t\t\t\tif( xYieldRequired == pdTRUE )\r\n\t\t\t\t{\r\n\t\t\t\t\ttaskYIELD_IF_USING_PREEMPTION();\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\r\n\t\t\t\t/* Remove compiler warning about unused variables when the port\r\n\t\t\t\toptimised task selection is not being used. */\r\n\t\t\t\t( void ) uxPriorityUsedOnEntry;\r\n\t\t\t}\r\n\t\t}\r\n\t\ttaskEXIT_CRITICAL();\r\n\t}\r\n\r\n#endif /* INCLUDE_vTaskPrioritySet */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( INCLUDE_vTaskSuspend == 1 )\r\n\r\n\tvoid vTaskSuspend( TaskHandle_t xTaskToSuspend )\r\n\t{\r\n\tTCB_t *pxTCB;\r\n\r\n\t\ttaskENTER_CRITICAL();\r\n\t\t{\r\n\t\t\t/* If null is passed in here then it is the running task that is\r\n\t\t\tbeing suspended. */\r\n\t\t\tpxTCB = prvGetTCBFromHandle( xTaskToSuspend );\r\n\r\n\t\t\ttraceTASK_SUSPEND( pxTCB );\r\n\r\n\t\t\t/* Remove task from the ready/delayed list and place in the\r\n\t\t\tsuspended list. */\r\n\t\t\tif( uxListRemove( &( pxTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r\n\t\t\t{\r\n\t\t\t\ttaskRESET_READY_PRIORITY( pxTCB->uxPriority );\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\r\n\t\t\t/* Is the task waiting on an event also? */\r\n\t\t\tif( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )\r\n\t\t\t{\r\n\t\t\t\t( void ) uxListRemove( &( pxTCB->xEventListItem ) );\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\r\n\t\t\tvListInsertEnd( &xSuspendedTaskList, &( pxTCB->xGenericListItem ) );\r\n\t\t}\r\n\t\ttaskEXIT_CRITICAL();\r\n\r\n\t\tif( pxTCB == pxCurrentTCB )\r\n\t\t{\r\n\t\t\tif( xSchedulerRunning != pdFALSE )\r\n\t\t\t{\r\n\t\t\t\t/* The current task has just been suspended. */\r\n\t\t\t\tconfigASSERT( uxSchedulerSuspended == 0 );\r\n\t\t\t\tportYIELD_WITHIN_API();\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\t/* The scheduler is not running, but the task that was pointed\r\n\t\t\t\tto by pxCurrentTCB has just been suspended and pxCurrentTCB\r\n\t\t\t\tmust be adjusted to point to a different task. */\r\n\t\t\t\tif( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks )\r\n\t\t\t\t{\r\n\t\t\t\t\t/* No other tasks are ready, so set pxCurrentTCB back to\r\n\t\t\t\t\tNULL so when the next task is created pxCurrentTCB will\r\n\t\t\t\t\tbe set to point to it no matter what its relative priority\r\n\t\t\t\t\tis. */\r\n\t\t\t\t\tpxCurrentTCB = NULL;\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tvTaskSwitchContext();\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tif( xSchedulerRunning != pdFALSE )\r\n\t\t\t{\r\n\t\t\t\t/* A task other than the currently running task was suspended,\r\n\t\t\t\treset the next expected unblock time in case it referred to the\r\n\t\t\t\ttask that is now in the Suspended state. */\r\n\t\t\t\ttaskENTER_CRITICAL();\r\n\t\t\t\t{\r\n\t\t\t\t\tprvResetNextTaskUnblockTime();\r\n\t\t\t\t}\r\n\t\t\t\ttaskEXIT_CRITICAL();\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\t\t}\r\n\t}\r\n\r\n#endif /* INCLUDE_vTaskSuspend */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( INCLUDE_vTaskSuspend == 1 )\r\n\r\n\tstatic BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask )\r\n\t{\r\n\tBaseType_t xReturn = pdFALSE;\r\n\tconst TCB_t * const pxTCB = ( TCB_t * ) xTask;\r\n\r\n\t\t/* Accesses xPendingReadyList so must be called from a critical\r\n\t\tsection. */\r\n\r\n\t\t/* It does not make sense to check if the calling task is suspended. */\r\n\t\tconfigASSERT( xTask );\r\n\r\n\t\t/* Is the task being resumed actually in the suspended list? */\r\n\t\tif( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xGenericListItem ) ) != pdFALSE )\r\n\t\t{\r\n\t\t\t/* Has the task already been resumed from within an ISR? */\r\n\t\t\tif( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE )\r\n\t\t\t{\r\n\t\t\t\t/* Is it in the suspended list because it is in the\tSuspended\r\n\t\t\t\tstate, or because is is blocked with no timeout? */\r\n\t\t\t\tif( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE )\r\n\t\t\t\t{\r\n\t\t\t\t\txReturn = pdTRUE;\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t}\r\n\r\n\t\treturn xReturn;\r\n\t} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */\r\n\r\n#endif /* INCLUDE_vTaskSuspend */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( INCLUDE_vTaskSuspend == 1 )\r\n\r\n\tvoid vTaskResume( TaskHandle_t xTaskToResume )\r\n\t{\r\n\tTCB_t * const pxTCB = ( TCB_t * ) xTaskToResume;\r\n\r\n\t\t/* It does not make sense to resume the calling task. */\r\n\t\tconfigASSERT( xTaskToResume );\r\n\r\n\t\t/* The parameter cannot be NULL as it is impossible to resume the\r\n\t\tcurrently executing task. */\r\n\t\tif( ( pxTCB != NULL ) && ( pxTCB != pxCurrentTCB ) )\r\n\t\t{\r\n\t\t\ttaskENTER_CRITICAL();\r\n\t\t\t{\r\n\t\t\t\tif( prvTaskIsTaskSuspended( pxTCB ) == pdTRUE )\r\n\t\t\t\t{\r\n\t\t\t\t\ttraceTASK_RESUME( pxTCB );\r\n\r\n\t\t\t\t\t/* As we are in a critical section we can access the ready\r\n\t\t\t\t\tlists even if the scheduler is suspended. */\r\n\t\t\t\t\t( void ) uxListRemove(  &( pxTCB->xGenericListItem ) );\r\n\t\t\t\t\tprvAddTaskToReadyList( pxTCB );\r\n\r\n\t\t\t\t\t/* We may have just resumed a higher priority task. */\r\n\t\t\t\t\tif( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t/* This yield may not cause the task just resumed to run,\r\n\t\t\t\t\t\tbut will leave the lists in the correct state for the\r\n\t\t\t\t\t\tnext yield. */\r\n\t\t\t\t\t\ttaskYIELD_IF_USING_PREEMPTION();\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\ttaskEXIT_CRITICAL();\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t}\r\n\t}\r\n\r\n#endif /* INCLUDE_vTaskSuspend */\r\n\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )\r\n\r\n\tBaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume )\r\n\t{\r\n\tBaseType_t xYieldRequired = pdFALSE;\r\n\tTCB_t * const pxTCB = ( TCB_t * ) xTaskToResume;\r\n\tUBaseType_t uxSavedInterruptStatus;\r\n\r\n\t\tconfigASSERT( xTaskToResume );\r\n\r\n\t\t/* RTOS ports that support interrupt nesting have the concept of a\r\n\t\tmaximum\tsystem call (or maximum API call) interrupt priority.\r\n\t\tInterrupts that are\tabove the maximum system call priority are keep\r\n\t\tpermanently enabled, even when the RTOS kernel is in a critical section,\r\n\t\tbut cannot make any calls to FreeRTOS API functions.  If configASSERT()\r\n\t\tis defined in FreeRTOSConfig.h then\r\n\t\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\r\n\t\tfailure if a FreeRTOS API function is called from an interrupt that has\r\n\t\tbeen assigned a priority above the configured maximum system call\r\n\t\tpriority.  Only FreeRTOS functions that end in FromISR can be called\r\n\t\tfrom interrupts\tthat have been assigned a priority at or (logically)\r\n\t\tbelow the maximum system call interrupt priority.  FreeRTOS maintains a\r\n\t\tseparate interrupt safe API to ensure interrupt entry is as fast and as\r\n\t\tsimple as possible.  More information (albeit Cortex-M specific) is\r\n\t\tprovided on the following link:\r\n\t\thttp://www.freertos.org/RTOS-Cortex-M3-M4.html */\r\n\t\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID();\r\n\r\n\t\tuxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\r\n\t\t{\r\n\t\t\tif( prvTaskIsTaskSuspended( pxTCB ) == pdTRUE )\r\n\t\t\t{\r\n\t\t\t\ttraceTASK_RESUME_FROM_ISR( pxTCB );\r\n\r\n\t\t\t\t/* Check the ready lists can be accessed. */\r\n\t\t\t\tif( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\r\n\t\t\t\t{\r\n\t\t\t\t\t/* Ready lists can be accessed so move the task from the\r\n\t\t\t\t\tsuspended list to the ready list directly. */\r\n\t\t\t\t\tif( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\txYieldRequired = pdTRUE;\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t}\r\n\r\n\t\t\t\t\t( void ) uxListRemove(  &( pxTCB->xGenericListItem ) );\r\n\t\t\t\t\tprvAddTaskToReadyList( pxTCB );\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\t/* The delayed or ready lists cannot be accessed so the task\r\n\t\t\t\t\tis held in the pending ready list until the scheduler is\r\n\t\t\t\t\tunsuspended. */\r\n\t\t\t\t\tvListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\t\t}\r\n\t\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\r\n\r\n\t\treturn xYieldRequired;\r\n\t}\r\n\r\n#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */\r\n/*-----------------------------------------------------------*/\r\n\r\nvoid vTaskStartScheduler( void )\r\n{\r\nBaseType_t xReturn;\r\n\r\n\t/* Add the idle task at the lowest priority. */\r\n\t#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )\r\n\t{\r\n\t\t/* Create the idle task, storing its handle in xIdleTaskHandle so it can\r\n\t\tbe returned by the xTaskGetIdleTaskHandle() function. */\r\n\t\txReturn = xTaskCreate( prvIdleTask, \"IDLE\", tskIDLE_STACK_SIZE, ( void * ) NULL, ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), &xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */\r\n\t}\r\n\t#else\r\n\t{\r\n\t\t/* Create the idle task without storing its handle. */\r\n\t\txReturn = xTaskCreate( prvIdleTask, \"IDLE\", tskIDLE_STACK_SIZE, ( void * ) NULL, ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), NULL );  /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */\r\n\t}\r\n\t#endif /* INCLUDE_xTaskGetIdleTaskHandle */\r\n\r\n\t#if ( configUSE_TIMERS == 1 )\r\n\t{\r\n\t\tif( xReturn == pdPASS )\r\n\t\t{\r\n\t\t\txReturn = xTimerCreateTimerTask();\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t}\r\n\t}\r\n\t#endif /* configUSE_TIMERS */\r\n\r\n\tif( xReturn == pdPASS )\r\n\t{\r\n\t\t/* Interrupts are turned off here, to ensure a tick does not occur\r\n\t\tbefore or during the call to xPortStartScheduler().  The stacks of\r\n\t\tthe created tasks contain a status word with interrupts switched on\r\n\t\tso interrupts will automatically get re-enabled when the first task\r\n\t\tstarts to run. */\r\n\t\tportDISABLE_INTERRUPTS();\r\n\r\n\t\t#if ( configUSE_NEWLIB_REENTRANT == 1 )\r\n\t\t{\r\n\t\t\t/* Switch Newlib's _impure_ptr variable to point to the _reent\r\n\t\t\tstructure specific to the task that will run first. */\r\n\t\t\t_impure_ptr = &( pxCurrentTCB->xNewLib_reent );\r\n\t\t}\r\n\t\t#endif /* configUSE_NEWLIB_REENTRANT */\r\n\r\n\t\txSchedulerRunning = pdTRUE;\r\n\t\txTickCount = ( TickType_t ) 0U;\r\n\r\n\t\t/* If configGENERATE_RUN_TIME_STATS is defined then the following\r\n\t\tmacro must be defined to configure the timer/counter used to generate\r\n\t\tthe run time counter time base. */\r\n\t\tportCONFIGURE_TIMER_FOR_RUN_TIME_STATS();\r\n\r\n\t\t/* Setting up the timer tick is hardware specific and thus in the\r\n\t\tportable interface. */\r\n\t\tif( xPortStartScheduler() != pdFALSE )\r\n\t\t{\r\n\t\t\t/* Should not reach here as if the scheduler is running the\r\n\t\t\tfunction will not return. */\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\t/* Should only reach here if a task calls xTaskEndScheduler(). */\r\n\t\t}\r\n\t}\r\n\telse\r\n\t{\r\n\t\t/* This line will only be reached if the kernel could not be started,\r\n\t\tbecause there was not enough FreeRTOS heap to create the idle task\r\n\t\tor the timer task. */\r\n\t\tconfigASSERT( xReturn );\r\n\t}\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nvoid vTaskEndScheduler( void )\r\n{\r\n\t/* Stop the scheduler interrupts and call the portable scheduler end\r\n\troutine so the original ISRs can be restored if necessary.  The port\r\n\tlayer must ensure interrupts enable\tbit is left in the correct state. */\r\n\tportDISABLE_INTERRUPTS();\r\n\txSchedulerRunning = pdFALSE;\r\n\tvPortEndScheduler();\r\n}\r\n/*----------------------------------------------------------*/\r\n\r\nvoid vTaskSuspendAll( void )\r\n{\r\n\t/* A critical section is not required as the variable is of type\r\n\tBaseType_t.  Please read Richard Barry's reply in the following link to a\r\n\tpost in the FreeRTOS support forum before reporting this as a bug! -\r\n\thttp://goo.gl/wu4acr */\r\n\t++uxSchedulerSuspended;\r\n}\r\n/*----------------------------------------------------------*/\r\n\r\n#if ( configUSE_TICKLESS_IDLE != 0 )\r\n\r\n\tstatic TickType_t prvGetExpectedIdleTime( void )\r\n\t{\r\n\tTickType_t xReturn;\r\n\r\n\t\tif( pxCurrentTCB->uxPriority > tskIDLE_PRIORITY )\r\n\t\t{\r\n\t\t\txReturn = 0;\r\n\t\t}\r\n\t\telse if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1 )\r\n\t\t{\r\n\t\t\t/* There are other idle priority tasks in the ready state.  If\r\n\t\t\ttime slicing is used then the very next tick interrupt must be\r\n\t\t\tprocessed. */\r\n\t\t\txReturn = 0;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\txReturn = xNextTaskUnblockTime - xTickCount;\r\n\t\t}\r\n\r\n\t\treturn xReturn;\r\n\t}\r\n\r\n#endif /* configUSE_TICKLESS_IDLE */\r\n/*----------------------------------------------------------*/\r\n\r\nBaseType_t xTaskResumeAll( void )\r\n{\r\nTCB_t *pxTCB;\r\nBaseType_t xAlreadyYielded = pdFALSE;\r\n\r\n\t/* If uxSchedulerSuspended is zero then this function does not match a\r\n\tprevious call to vTaskSuspendAll(). */\r\n\tconfigASSERT( uxSchedulerSuspended );\r\n\r\n\t/* It is possible that an ISR caused a task to be removed from an event\r\n\tlist while the scheduler was suspended.  If this was the case then the\r\n\tremoved task will have been added to the xPendingReadyList.  Once the\r\n\tscheduler has been resumed it is safe to move all the pending ready\r\n\ttasks from this list into their appropriate ready list. */\r\n\ttaskENTER_CRITICAL();\r\n\t{\r\n\t\t--uxSchedulerSuspended;\r\n\r\n\t\tif( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\r\n\t\t{\r\n\t\t\tif( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )\r\n\t\t\t{\r\n\t\t\t\t/* Move any readied tasks from the pending list into the\r\n\t\t\t\tappropriate ready list. */\r\n\t\t\t\twhile( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )\r\n\t\t\t\t{\r\n\t\t\t\t\tpxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) );\r\n\t\t\t\t\t( void ) uxListRemove( &( pxTCB->xEventListItem ) );\r\n\t\t\t\t\t( void ) uxListRemove( &( pxTCB->xGenericListItem ) );\r\n\t\t\t\t\tprvAddTaskToReadyList( pxTCB );\r\n\r\n\t\t\t\t\t/* If the moved task has a priority higher than the current\r\n\t\t\t\t\ttask then a yield must be performed. */\r\n\t\t\t\t\tif( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\txYieldPending = pdTRUE;\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\r\n\t\t\t\t/* If any ticks occurred while the scheduler was suspended then\r\n\t\t\t\tthey should be processed now.  This ensures the tick count does\r\n\t\t\t\tnot\tslip, and that any delayed tasks are resumed at the correct\r\n\t\t\t\ttime. */\r\n\t\t\t\tif( uxPendedTicks > ( UBaseType_t ) 0U )\r\n\t\t\t\t{\r\n\t\t\t\t\twhile( uxPendedTicks > ( UBaseType_t ) 0U )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tif( xTaskIncrementTick() != pdFALSE )\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\txYieldPending = pdTRUE;\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\telse\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\t--uxPendedTicks;\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\r\n\t\t\t\tif( xYieldPending == pdTRUE )\r\n\t\t\t\t{\r\n\t\t\t\t\t#if( configUSE_PREEMPTION != 0 )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\txAlreadyYielded = pdTRUE;\r\n\t\t\t\t\t}\r\n\t\t\t\t\t#endif\r\n\t\t\t\t\ttaskYIELD_IF_USING_PREEMPTION();\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t}\r\n\t}\r\n\ttaskEXIT_CRITICAL();\r\n\r\n\treturn xAlreadyYielded;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nTickType_t xTaskGetTickCount( void )\r\n{\r\nTickType_t xTicks;\r\n\r\n\t/* Critical section required if running on a 16 bit processor. */\r\n\tportTICK_TYPE_ENTER_CRITICAL();\r\n\t{\r\n\t\txTicks = xTickCount;\r\n\t}\r\n\tportTICK_TYPE_EXIT_CRITICAL();\r\n\r\n\treturn xTicks;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nTickType_t xTaskGetTickCountFromISR( void )\r\n{\r\nTickType_t xReturn;\r\nUBaseType_t uxSavedInterruptStatus;\r\n\r\n\t/* RTOS ports that support interrupt nesting have the concept of a maximum\r\n\tsystem call (or maximum API call) interrupt priority.  Interrupts that are\r\n\tabove the maximum system call priority are kept permanently enabled, even\r\n\twhen the RTOS kernel is in a critical section, but cannot make any calls to\r\n\tFreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h\r\n\tthen portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\r\n\tfailure if a FreeRTOS API function is called from an interrupt that has been\r\n\tassigned a priority above the configured maximum system call priority.\r\n\tOnly FreeRTOS functions that end in FromISR can be called from interrupts\r\n\tthat have been assigned a priority at or (logically) below the maximum\r\n\tsystem call\tinterrupt priority.  FreeRTOS maintains a separate interrupt\r\n\tsafe API to ensure interrupt entry is as fast and as simple as possible.\r\n\tMore information (albeit Cortex-M specific) is provided on the following\r\n\tlink: http://www.freertos.org/RTOS-Cortex-M3-M4.html */\r\n\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID();\r\n\r\n\tuxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR();\r\n\t{\r\n\t\txReturn = xTickCount;\r\n\t}\r\n\tportTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\r\n\r\n\treturn xReturn;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nUBaseType_t uxTaskGetNumberOfTasks( void )\r\n{\r\n\t/* A critical section is not required because the variables are of type\r\n\tBaseType_t. */\r\n\treturn uxCurrentNumberOfTasks;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( INCLUDE_pcTaskGetTaskName == 1 )\r\n\r\n\tchar *pcTaskGetTaskName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\r\n\t{\r\n\tTCB_t *pxTCB;\r\n\r\n\t\t/* If null is passed in here then the name of the calling task is being queried. */\r\n\t\tpxTCB = prvGetTCBFromHandle( xTaskToQuery );\r\n\t\tconfigASSERT( pxTCB );\r\n\t\treturn &( pxTCB->pcTaskName[ 0 ] );\r\n\t}\r\n\r\n#endif /* INCLUDE_pcTaskGetTaskName */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( configUSE_TRACE_FACILITY == 1 )\r\n\r\n\tUBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime )\r\n\t{\r\n\tUBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES;\r\n\r\n\t\tvTaskSuspendAll();\r\n\t\t{\r\n\t\t\t/* Is there a space in the array for each task in the system? */\r\n\t\t\tif( uxArraySize >= uxCurrentNumberOfTasks )\r\n\t\t\t{\r\n\t\t\t\t/* Fill in an TaskStatus_t structure with information on each\r\n\t\t\t\ttask in the Ready state. */\r\n\t\t\t\tdo\r\n\t\t\t\t{\r\n\t\t\t\t\tuxQueue--;\r\n\t\t\t\t\tuxTask += prvListTaskWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady );\r\n\r\n\t\t\t\t} while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\r\n\r\n\t\t\t\t/* Fill in an TaskStatus_t structure with information on each\r\n\t\t\t\ttask in the Blocked state. */\r\n\t\t\t\tuxTask += prvListTaskWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked );\r\n\t\t\t\tuxTask += prvListTaskWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked );\r\n\r\n\t\t\t\t#if( INCLUDE_vTaskDelete == 1 )\r\n\t\t\t\t{\r\n\t\t\t\t\t/* Fill in an TaskStatus_t structure with information on\r\n\t\t\t\t\teach task that has been deleted but not yet cleaned up. */\r\n\t\t\t\t\tuxTask += prvListTaskWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted );\r\n\t\t\t\t}\r\n\t\t\t\t#endif\r\n\r\n\t\t\t\t#if ( INCLUDE_vTaskSuspend == 1 )\r\n\t\t\t\t{\r\n\t\t\t\t\t/* Fill in an TaskStatus_t structure with information on\r\n\t\t\t\t\teach task in the Suspended state. */\r\n\t\t\t\t\tuxTask += prvListTaskWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended );\r\n\t\t\t\t}\r\n\t\t\t\t#endif\r\n\r\n\t\t\t\t#if ( configGENERATE_RUN_TIME_STATS == 1)\r\n\t\t\t\t{\r\n\t\t\t\t\tif( pulTotalRunTime != NULL )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE\r\n\t\t\t\t\t\t\tportALT_GET_RUN_TIME_COUNTER_VALUE( ( *pulTotalRunTime ) );\r\n\t\t\t\t\t\t#else\r\n\t\t\t\t\t\t\t*pulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();\r\n\t\t\t\t\t\t#endif\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t\t#else\r\n\t\t\t\t{\r\n\t\t\t\t\tif( pulTotalRunTime != NULL )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t*pulTotalRunTime = 0;\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t\t#endif\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\t\t}\r\n\t\t( void ) xTaskResumeAll();\r\n\r\n\t\treturn uxTask;\r\n\t}\r\n\r\n#endif /* configUSE_TRACE_FACILITY */\r\n/*----------------------------------------------------------*/\r\n\r\n#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )\r\n\r\n\tTaskHandle_t xTaskGetIdleTaskHandle( void )\r\n\t{\r\n\t\t/* If xTaskGetIdleTaskHandle() is called before the scheduler has been\r\n\t\tstarted, then xIdleTaskHandle will be NULL. */\r\n\t\tconfigASSERT( ( xIdleTaskHandle != NULL ) );\r\n\t\treturn xIdleTaskHandle;\r\n\t}\r\n\r\n#endif /* INCLUDE_xTaskGetIdleTaskHandle */\r\n/*----------------------------------------------------------*/\r\n\r\n/* This conditional compilation should use inequality to 0, not equality to 1.\r\nThis is to ensure vTaskStepTick() is available when user defined low power mode\r\nimplementations require configUSE_TICKLESS_IDLE to be set to a value other than\r\n1. */\r\n#if ( configUSE_TICKLESS_IDLE != 0 )\r\n\r\n\tvoid vTaskStepTick( const TickType_t xTicksToJump )\r\n\t{\r\n\t\t/* Correct the tick count value after a period during which the tick\r\n\t\twas suppressed.  Note this does *not* call the tick hook function for\r\n\t\teach stepped tick. */\r\n\t\tconfigASSERT( ( xTickCount + xTicksToJump ) <= xNextTaskUnblockTime );\r\n\t\txTickCount += xTicksToJump;\r\n\t\ttraceINCREASE_TICK_COUNT( xTicksToJump );\r\n\t}\r\n\r\n#endif /* configUSE_TICKLESS_IDLE */\r\n/*----------------------------------------------------------*/\r\n\r\nBaseType_t xTaskIncrementTick( void )\r\n{\r\nTCB_t * pxTCB;\r\nTickType_t xItemValue;\r\nBaseType_t xSwitchRequired = pdFALSE;\r\n\r\n\t/* Called by the portable layer each time a tick interrupt occurs.\r\n\tIncrements the tick then checks to see if the new tick value will cause any\r\n\ttasks to be unblocked. */\r\n\ttraceTASK_INCREMENT_TICK( xTickCount );\r\n\tif( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\r\n\t{\r\n\t\t/* Increment the RTOS tick, switching the delayed and overflowed\r\n\t\tdelayed lists if it wraps to 0. */\r\n\t\t++xTickCount;\r\n\r\n\t\t{\r\n\t\t\t/* Minor optimisation.  The tick count cannot change in this\r\n\t\t\tblock. */\r\n\t\t\tconst TickType_t xConstTickCount = xTickCount;\r\n\r\n\t\t\tif( xConstTickCount == ( TickType_t ) 0U )\r\n\t\t\t{\r\n\t\t\t\ttaskSWITCH_DELAYED_LISTS();\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\r\n\t\t\t/* See if this tick has made a timeout expire.  Tasks are stored in\r\n\t\t\tthe\tqueue in the order of their wake time - meaning once one task\r\n\t\t\thas been found whose block time has not expired there is no need to\r\n\t\t\tlook any further down the list. */\r\n\t\t\tif( xConstTickCount >= xNextTaskUnblockTime )\r\n\t\t\t{\r\n\t\t\t\tfor( ;; )\r\n\t\t\t\t{\r\n\t\t\t\t\tif( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t/* The delayed list is empty.  Set xNextTaskUnblockTime\r\n\t\t\t\t\t\tto the maximum possible value so it is extremely\r\n\t\t\t\t\t\tunlikely that the\r\n\t\t\t\t\t\tif( xTickCount >= xNextTaskUnblockTime ) test will pass\r\n\t\t\t\t\t\tnext time through. */\r\n\t\t\t\t\t\txNextTaskUnblockTime = portMAX_DELAY;\r\n\t\t\t\t\t\tbreak;\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t/* The delayed list is not empty, get the value of the\r\n\t\t\t\t\t\titem at the head of the delayed list.  This is the time\r\n\t\t\t\t\t\tat which the task at the head of the delayed list must\r\n\t\t\t\t\t\tbe removed from the Blocked state. */\r\n\t\t\t\t\t\tpxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList );\r\n\t\t\t\t\t\txItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xGenericListItem ) );\r\n\r\n\t\t\t\t\t\tif( xConstTickCount < xItemValue )\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t/* It is not time to unblock this item yet, but the\r\n\t\t\t\t\t\t\titem value is the time at which the task at the head\r\n\t\t\t\t\t\t\tof the blocked list must be removed from the Blocked\r\n\t\t\t\t\t\t\tstate -\tso record the item value in\r\n\t\t\t\t\t\t\txNextTaskUnblockTime. */\r\n\t\t\t\t\t\t\txNextTaskUnblockTime = xItemValue;\r\n\t\t\t\t\t\t\tbreak;\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\telse\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t\t}\r\n\r\n\t\t\t\t\t\t/* It is time to remove the item from the Blocked state. */\r\n\t\t\t\t\t\t( void ) uxListRemove( &( pxTCB->xGenericListItem ) );\r\n\r\n\t\t\t\t\t\t/* Is the task waiting on an event also?  If so remove\r\n\t\t\t\t\t\tit from the event list. */\r\n\t\t\t\t\t\tif( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t( void ) uxListRemove( &( pxTCB->xEventListItem ) );\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\telse\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t\t}\r\n\r\n\t\t\t\t\t\t/* Place the unblocked task into the appropriate ready\r\n\t\t\t\t\t\tlist. */\r\n\t\t\t\t\t\tprvAddTaskToReadyList( pxTCB );\r\n\r\n\t\t\t\t\t\t/* A task being unblocked cannot cause an immediate\r\n\t\t\t\t\t\tcontext switch if preemption is turned off. */\r\n\t\t\t\t\t\t#if (  configUSE_PREEMPTION == 1 )\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t/* Preemption is on, but a context switch should\r\n\t\t\t\t\t\t\tonly be performed if the unblocked task has a\r\n\t\t\t\t\t\t\tpriority that is equal to or higher than the\r\n\t\t\t\t\t\t\tcurrently executing task. */\r\n\t\t\t\t\t\t\tif( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )\r\n\t\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t\txSwitchRequired = pdTRUE;\r\n\t\t\t\t\t\t\t}\r\n\t\t\t\t\t\t\telse\r\n\t\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t\t\t}\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\t#endif /* configUSE_PREEMPTION */\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t}\r\n\r\n\t\t/* Tasks of equal priority to the currently running task will share\r\n\t\tprocessing time (time slice) if preemption is on, and the application\r\n\t\twriter has not explicitly turned time slicing off. */\r\n\t\t#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )\r\n\t\t{\r\n\t\t\tif( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )\r\n\t\t\t{\r\n\t\t\t\txSwitchRequired = pdTRUE;\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\t\t}\r\n\t\t#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */\r\n\r\n\t\t#if ( configUSE_TICK_HOOK == 1 )\r\n\t\t{\r\n\t\t\t/* Guard against the tick hook being called when the pended tick\r\n\t\t\tcount is being unwound (when the scheduler is being unlocked). */\r\n\t\t\tif( uxPendedTicks == ( UBaseType_t ) 0U )\r\n\t\t\t{\r\n\t\t\t\tvApplicationTickHook();\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\t\t}\r\n\t\t#endif /* configUSE_TICK_HOOK */\r\n\t}\r\n\telse\r\n\t{\r\n\t\t++uxPendedTicks;\r\n\r\n\t\t/* The tick hook gets called at regular intervals, even if the\r\n\t\tscheduler is locked. */\r\n\t\t#if ( configUSE_TICK_HOOK == 1 )\r\n\t\t{\r\n\t\t\tvApplicationTickHook();\r\n\t\t}\r\n\t\t#endif\r\n\t}\r\n\r\n\t#if ( configUSE_PREEMPTION == 1 )\r\n\t{\r\n\t\tif( xYieldPending != pdFALSE )\r\n\t\t{\r\n\t\t\txSwitchRequired = pdTRUE;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t}\r\n\t}\r\n\t#endif /* configUSE_PREEMPTION */\r\n\r\n\treturn xSwitchRequired;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( configUSE_APPLICATION_TASK_TAG == 1 )\r\n\r\n\tvoid vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction )\r\n\t{\r\n\tTCB_t *xTCB;\r\n\r\n\t\t/* If xTask is NULL then it is the task hook of the calling task that is\r\n\t\tgetting set. */\r\n\t\tif( xTask == NULL )\r\n\t\t{\r\n\t\t\txTCB = ( TCB_t * ) pxCurrentTCB;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\txTCB = ( TCB_t * ) xTask;\r\n\t\t}\r\n\r\n\t\t/* Save the hook function in the TCB.  A critical section is required as\r\n\t\tthe value can be accessed from an interrupt. */\r\n\t\ttaskENTER_CRITICAL();\r\n\t\t\txTCB->pxTaskTag = pxHookFunction;\r\n\t\ttaskEXIT_CRITICAL();\r\n\t}\r\n\r\n#endif /* configUSE_APPLICATION_TASK_TAG */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( configUSE_APPLICATION_TASK_TAG == 1 )\r\n\r\n\tTaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask )\r\n\t{\r\n\tTCB_t *xTCB;\r\n\tTaskHookFunction_t xReturn;\r\n\r\n\t\t/* If xTask is NULL then we are setting our own task hook. */\r\n\t\tif( xTask == NULL )\r\n\t\t{\r\n\t\t\txTCB = ( TCB_t * ) pxCurrentTCB;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\txTCB = ( TCB_t * ) xTask;\r\n\t\t}\r\n\r\n\t\t/* Save the hook function in the TCB.  A critical section is required as\r\n\t\tthe value can be accessed from an interrupt. */\r\n\t\ttaskENTER_CRITICAL();\r\n\t\t{\r\n\t\t\txReturn = xTCB->pxTaskTag;\r\n\t\t}\r\n\t\ttaskEXIT_CRITICAL();\r\n\r\n\t\treturn xReturn;\r\n\t}\r\n\r\n#endif /* configUSE_APPLICATION_TASK_TAG */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( configUSE_APPLICATION_TASK_TAG == 1 )\r\n\r\n\tBaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter )\r\n\t{\r\n\tTCB_t *xTCB;\r\n\tBaseType_t xReturn;\r\n\r\n\t\t/* If xTask is NULL then we are calling our own task hook. */\r\n\t\tif( xTask == NULL )\r\n\t\t{\r\n\t\t\txTCB = ( TCB_t * ) pxCurrentTCB;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\txTCB = ( TCB_t * ) xTask;\r\n\t\t}\r\n\r\n\t\tif( xTCB->pxTaskTag != NULL )\r\n\t\t{\r\n\t\t\txReturn = xTCB->pxTaskTag( pvParameter );\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\txReturn = pdFAIL;\r\n\t\t}\r\n\r\n\t\treturn xReturn;\r\n\t}\r\n\r\n#endif /* configUSE_APPLICATION_TASK_TAG */\r\n/*-----------------------------------------------------------*/\r\n\r\nvoid vTaskSwitchContext( void )\r\n{\r\n\tif( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )\r\n\t{\r\n\t\t/* The scheduler is currently suspended - do not allow a context\r\n\t\tswitch. */\r\n\t\txYieldPending = pdTRUE;\r\n\t}\r\n\telse\r\n\t{\r\n\t\txYieldPending = pdFALSE;\r\n\t\ttraceTASK_SWITCHED_OUT();\r\n\r\n\t\t#if ( configGENERATE_RUN_TIME_STATS == 1 )\r\n\t\t{\r\n\t\t\t\t#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE\r\n\t\t\t\t\tportALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime );\r\n\t\t\t\t#else\r\n\t\t\t\t\tulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();\r\n\t\t\t\t#endif\r\n\r\n\t\t\t\t/* Add the amount of time the task has been running to the\r\n\t\t\t\taccumulated\ttime so far.  The time the task started running was\r\n\t\t\t\tstored in ulTaskSwitchedInTime.  Note that there is no overflow\r\n\t\t\t\tprotection here\tso count values are only valid until the timer\r\n\t\t\t\toverflows.  The guard against negative values is to protect\r\n\t\t\t\tagainst suspect run time stat counter implementations - which\r\n\t\t\t\tare provided by the application, not the kernel. */\r\n\t\t\t\tif( ulTotalRunTime > ulTaskSwitchedInTime )\r\n\t\t\t\t{\r\n\t\t\t\t\tpxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime );\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\t\t\t\tulTaskSwitchedInTime = ulTotalRunTime;\r\n\t\t}\r\n\t\t#endif /* configGENERATE_RUN_TIME_STATS */\r\n\r\n\t\t/* Check for stack overflow, if configured. */\r\n\t\ttaskFIRST_CHECK_FOR_STACK_OVERFLOW();\r\n\t\ttaskSECOND_CHECK_FOR_STACK_OVERFLOW();\r\n\r\n\t\t/* Select a new task to run using either the generic C or port\r\n\t\toptimised asm code. */\r\n\t\ttaskSELECT_HIGHEST_PRIORITY_TASK();\r\n\t\ttraceTASK_SWITCHED_IN();\r\n\r\n\t\t#if ( configUSE_NEWLIB_REENTRANT == 1 )\r\n\t\t{\r\n\t\t\t/* Switch Newlib's _impure_ptr variable to point to the _reent\r\n\t\t\tstructure specific to this task. */\r\n\t\t\t_impure_ptr = &( pxCurrentTCB->xNewLib_reent );\r\n\t\t}\r\n\t\t#endif /* configUSE_NEWLIB_REENTRANT */\r\n\t}\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nvoid vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )\r\n{\r\nTickType_t xTimeToWake;\r\n\r\n\tconfigASSERT( pxEventList );\r\n\r\n\t/* THIS FUNCTION MUST BE CALLED WITH EITHER INTERRUPTS DISABLED OR THE\r\n\tSCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */\r\n\r\n\t/* Place the event list item of the TCB in the appropriate event list.\r\n\tThis is placed in the list in priority order so the highest priority task\r\n\tis the first to be woken by the event.  The queue that contains the event\r\n\tlist is locked, preventing simultaneous access from interrupts. */\r\n\tvListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );\r\n\r\n\t/* The task must be removed from from the ready list before it is added to\r\n\tthe blocked list as the same list item is used for both lists.  Exclusive\r\n\taccess to the ready lists guaranteed because the scheduler is locked. */\r\n\tif( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r\n\t{\r\n\t\t/* The current task must be in a ready list, so there is no need to\r\n\t\tcheck, and the port reset macro can be called directly. */\r\n\t\tportRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );\r\n\t}\r\n\telse\r\n\t{\r\n\t\tmtCOVERAGE_TEST_MARKER();\r\n\t}\r\n\r\n\t#if ( INCLUDE_vTaskSuspend == 1 )\r\n\t{\r\n\t\tif( xTicksToWait == portMAX_DELAY )\r\n\t\t{\r\n\t\t\t/* Add the task to the suspended task list instead of a delayed task\r\n\t\t\tlist to ensure the task is not woken by a timing event.  It will\r\n\t\t\tblock indefinitely. */\r\n\t\t\tvListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xGenericListItem ) );\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\t/* Calculate the time at which the task should be woken if the event\r\n\t\t\tdoes not occur.  This may overflow but this doesn't matter, the\r\n\t\t\tscheduler will handle it. */\r\n\t\t\txTimeToWake = xTickCount + xTicksToWait;\r\n\t\t\tprvAddCurrentTaskToDelayedList( xTimeToWake );\r\n\t\t}\r\n\t}\r\n\t#else /* INCLUDE_vTaskSuspend */\r\n\t{\r\n\t\t\t/* Calculate the time at which the task should be woken if the event does\r\n\t\t\tnot occur.  This may overflow but this doesn't matter, the scheduler\r\n\t\t\twill handle it. */\r\n\t\t\txTimeToWake = xTickCount + xTicksToWait;\r\n\t\t\tprvAddCurrentTaskToDelayedList( xTimeToWake );\r\n\t}\r\n\t#endif /* INCLUDE_vTaskSuspend */\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nvoid vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait )\r\n{\r\nTickType_t xTimeToWake;\r\n\r\n\tconfigASSERT( pxEventList );\r\n\r\n\t/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by\r\n\tthe event groups implementation. */\r\n\tconfigASSERT( uxSchedulerSuspended != 0 );\r\n\r\n\t/* Store the item value in the event list item.  It is safe to access the\r\n\tevent list item here as interrupts won't access the event list item of a\r\n\ttask that is not in the Blocked state. */\r\n\tlistSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );\r\n\r\n\t/* Place the event list item of the TCB at the end of the appropriate event\r\n\tlist.  It is safe to access the event list here because it is part of an\r\n\tevent group implementation - and interrupts don't access event groups\r\n\tdirectly (instead they access them indirectly by pending function calls to\r\n\tthe task level). */\r\n\tvListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );\r\n\r\n\t/* The task must be removed from the ready list before it is added to the\r\n\tblocked list.  Exclusive access can be assured to the ready list as the\r\n\tscheduler is locked. */\r\n\tif( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r\n\t{\r\n\t\t/* The current task must be in a ready list, so there is no need to\r\n\t\tcheck, and the port reset macro can be called directly. */\r\n\t\tportRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );\r\n\t}\r\n\telse\r\n\t{\r\n\t\tmtCOVERAGE_TEST_MARKER();\r\n\t}\r\n\r\n\t#if ( INCLUDE_vTaskSuspend == 1 )\r\n\t{\r\n\t\tif( xTicksToWait == portMAX_DELAY )\r\n\t\t{\r\n\t\t\t/* Add the task to the suspended task list instead of a delayed task\r\n\t\t\tlist to ensure it is not woken by a timing event.  It will block\r\n\t\t\tindefinitely. */\r\n\t\t\tvListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xGenericListItem ) );\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\t/* Calculate the time at which the task should be woken if the event\r\n\t\t\tdoes not occur.  This may overflow but this doesn't matter, the\r\n\t\t\tkernel will manage it correctly. */\r\n\t\t\txTimeToWake = xTickCount + xTicksToWait;\r\n\t\t\tprvAddCurrentTaskToDelayedList( xTimeToWake );\r\n\t\t}\r\n\t}\r\n\t#else /* INCLUDE_vTaskSuspend */\r\n\t{\r\n\t\t\t/* Calculate the time at which the task should be woken if the event does\r\n\t\t\tnot occur.  This may overflow but this doesn't matter, the kernel\r\n\t\t\twill manage it correctly. */\r\n\t\t\txTimeToWake = xTickCount + xTicksToWait;\r\n\t\t\tprvAddCurrentTaskToDelayedList( xTimeToWake );\r\n\t}\r\n\t#endif /* INCLUDE_vTaskSuspend */\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\n#if configUSE_TIMERS == 1\r\n\r\n\tvoid vTaskPlaceOnEventListRestricted( List_t * const pxEventList, const TickType_t xTicksToWait )\r\n\t{\r\n\tTickType_t xTimeToWake;\r\n\r\n\t\tconfigASSERT( pxEventList );\r\n\r\n\t\t/* This function should not be called by application code hence the\r\n\t\t'Restricted' in its name.  It is not part of the public API.  It is\r\n\t\tdesigned for use by kernel code, and has special calling requirements -\r\n\t\tit should be called with the scheduler suspended. */\r\n\r\n\r\n\t\t/* Place the event list item of the TCB in the appropriate event list.\r\n\t\tIn this case it is assume that this is the only task that is going to\r\n\t\tbe waiting on this event list, so the faster vListInsertEnd() function\r\n\t\tcan be used in place of vListInsert. */\r\n\t\tvListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );\r\n\r\n\t\t/* We must remove this task from the ready list before adding it to the\r\n\t\tblocked list as the same list item is used for both lists.  This\r\n\t\tfunction is called with the scheduler locked so interrupts will not\r\n\t\taccess the lists at the same time. */\r\n\t\tif( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r\n\t\t{\r\n\t\t\t/* The current task must be in a ready list, so there is no need to\r\n\t\t\tcheck, and the port reset macro can be called directly. */\r\n\t\t\tportRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t}\r\n\r\n\t\t/* Calculate the time at which the task should be woken if the event does\r\n\t\tnot occur.  This may overflow but this doesn't matter. */\r\n\t\txTimeToWake = xTickCount + xTicksToWait;\r\n\r\n\t\ttraceTASK_DELAY_UNTIL();\r\n\t\tprvAddCurrentTaskToDelayedList( xTimeToWake );\r\n\t}\r\n\r\n#endif /* configUSE_TIMERS */\r\n/*-----------------------------------------------------------*/\r\n\r\nBaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )\r\n{\r\nTCB_t *pxUnblockedTCB;\r\nBaseType_t xReturn;\r\n\r\n\t/* THIS FUNCTION MUST BE CALLED FROM A CRITICAL SECTION.  It can also be\r\n\tcalled from a critical section within an ISR. */\r\n\r\n\t/* The event list is sorted in priority order, so the first in the list can\r\n\tbe removed as it is known to be the highest priority.  Remove the TCB from\r\n\tthe delayed list, and add it to the ready list.\r\n\r\n\tIf an event is for a queue that is locked then this function will never\r\n\tget called - the lock count on the queue will get modified instead.  This\r\n\tmeans exclusive access to the event list is guaranteed here.\r\n\r\n\tThis function assumes that a check has already been made to ensure that\r\n\tpxEventList is not empty. */\r\n\tpxUnblockedTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );\r\n\tconfigASSERT( pxUnblockedTCB );\r\n\t( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );\r\n\r\n\tif( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\r\n\t{\r\n\t\t( void ) uxListRemove( &( pxUnblockedTCB->xGenericListItem ) );\r\n\t\tprvAddTaskToReadyList( pxUnblockedTCB );\r\n\t}\r\n\telse\r\n\t{\r\n\t\t/* The delayed and ready lists cannot be accessed, so hold this task\r\n\t\tpending until the scheduler is resumed. */\r\n\t\tvListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );\r\n\t}\r\n\r\n\tif( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )\r\n\t{\r\n\t\t/* Return true if the task removed from the event list has a higher\r\n\t\tpriority than the calling task.  This allows the calling task to know if\r\n\t\tit should force a context switch now. */\r\n\t\txReturn = pdTRUE;\r\n\r\n\t\t/* Mark that a yield is pending in case the user is not using the\r\n\t\t\"xHigherPriorityTaskWoken\" parameter to an ISR safe FreeRTOS function. */\r\n\t\txYieldPending = pdTRUE;\r\n\t}\r\n\telse\r\n\t{\r\n\t\txReturn = pdFALSE;\r\n\t}\r\n\r\n\t#if( configUSE_TICKLESS_IDLE == 1 )\r\n\t{\r\n\t\t/* If a task is blocked on a kernel object then xNextTaskUnblockTime\r\n\t\tmight be set to the blocked task's time out time.  If the task is\r\n\t\tunblocked for a reason other than a timeout xNextTaskUnblockTime is\r\n\t\tnormally left unchanged, because it is automatically get reset to a new\r\n\t\tvalue when the tick count equals xNextTaskUnblockTime.  However if\r\n\t\ttickless idling is used it might be more important to enter sleep mode\r\n\t\tat the earliest possible time - so reset xNextTaskUnblockTime here to\r\n\t\tensure it is updated at the earliest possible time. */\r\n\t\tprvResetNextTaskUnblockTime();\r\n\t}\r\n\t#endif\r\n\r\n\treturn xReturn;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nBaseType_t xTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue )\r\n{\r\nTCB_t *pxUnblockedTCB;\r\nBaseType_t xReturn;\r\n\r\n\t/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by\r\n\tthe event flags implementation. */\r\n\tconfigASSERT( uxSchedulerSuspended != pdFALSE );\r\n\r\n\t/* Store the new item value in the event list. */\r\n\tlistSET_LIST_ITEM_VALUE( pxEventListItem, xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );\r\n\r\n\t/* Remove the event list form the event flag.  Interrupts do not access\r\n\tevent flags. */\r\n\tpxUnblockedTCB = ( TCB_t * ) listGET_LIST_ITEM_OWNER( pxEventListItem );\r\n\tconfigASSERT( pxUnblockedTCB );\r\n\t( void ) uxListRemove( pxEventListItem );\r\n\r\n\t/* Remove the task from the delayed list and add it to the ready list.  The\r\n\tscheduler is suspended so interrupts will not be accessing the ready\r\n\tlists. */\r\n\t( void ) uxListRemove( &( pxUnblockedTCB->xGenericListItem ) );\r\n\tprvAddTaskToReadyList( pxUnblockedTCB );\r\n\r\n\tif( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )\r\n\t{\r\n\t\t/* Return true if the task removed from the event list has\r\n\t\ta higher priority than the calling task.  This allows\r\n\t\tthe calling task to know if it should force a context\r\n\t\tswitch now. */\r\n\t\txReturn = pdTRUE;\r\n\r\n\t\t/* Mark that a yield is pending in case the user is not using the\r\n\t\t\"xHigherPriorityTaskWoken\" parameter to an ISR safe FreeRTOS function. */\r\n\t\txYieldPending = pdTRUE;\r\n\t}\r\n\telse\r\n\t{\r\n\t\txReturn = pdFALSE;\r\n\t}\r\n\r\n\treturn xReturn;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nvoid vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )\r\n{\r\n\tconfigASSERT( pxTimeOut );\r\n\tpxTimeOut->xOverflowCount = xNumOfOverflows;\r\n\tpxTimeOut->xTimeOnEntering = xTickCount;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nBaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )\r\n{\r\nBaseType_t xReturn;\r\n\r\n\tconfigASSERT( pxTimeOut );\r\n\tconfigASSERT( pxTicksToWait );\r\n\r\n\ttaskENTER_CRITICAL();\r\n\t{\r\n\t\t/* Minor optimisation.  The tick count cannot change in this block. */\r\n\t\tconst TickType_t xConstTickCount = xTickCount;\r\n\r\n\t\t#if ( INCLUDE_vTaskSuspend == 1 )\r\n\t\t\t/* If INCLUDE_vTaskSuspend is set to 1 and the block time specified is\r\n\t\t\tthe maximum block time then the task should block indefinitely, and\r\n\t\t\ttherefore never time out. */\r\n\t\t\tif( *pxTicksToWait == portMAX_DELAY )\r\n\t\t\t{\r\n\t\t\t\txReturn = pdFALSE;\r\n\t\t\t}\r\n\t\t\telse /* We are not blocking indefinitely, perform the checks below. */\r\n\t\t#endif\r\n\r\n\t\tif( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */\r\n\t\t{\r\n\t\t\t/* The tick count is greater than the time at which vTaskSetTimeout()\r\n\t\t\twas called, but has also overflowed since vTaskSetTimeOut() was called.\r\n\t\t\tIt must have wrapped all the way around and gone past us again. This\r\n\t\t\tpassed since vTaskSetTimeout() was called. */\r\n\t\t\txReturn = pdTRUE;\r\n\t\t}\r\n\t\telse if( ( xConstTickCount - pxTimeOut->xTimeOnEntering ) < *pxTicksToWait )\r\n\t\t{\r\n\t\t\t/* Not a genuine timeout. Adjust parameters for time remaining. */\r\n\t\t\t*pxTicksToWait -= ( xConstTickCount -  pxTimeOut->xTimeOnEntering );\r\n\t\t\tvTaskSetTimeOutState( pxTimeOut );\r\n\t\t\txReturn = pdFALSE;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\txReturn = pdTRUE;\r\n\t\t}\r\n\t}\r\n\ttaskEXIT_CRITICAL();\r\n\r\n\treturn xReturn;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nvoid vTaskMissedYield( void )\r\n{\r\n\txYieldPending = pdTRUE;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( configUSE_TRACE_FACILITY == 1 )\r\n\r\n\tUBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask )\r\n\t{\r\n\tUBaseType_t uxReturn;\r\n\tTCB_t *pxTCB;\r\n\r\n\t\tif( xTask != NULL )\r\n\t\t{\r\n\t\t\tpxTCB = ( TCB_t * ) xTask;\r\n\t\t\tuxReturn = pxTCB->uxTaskNumber;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tuxReturn = 0U;\r\n\t\t}\r\n\r\n\t\treturn uxReturn;\r\n\t}\r\n\r\n#endif /* configUSE_TRACE_FACILITY */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( configUSE_TRACE_FACILITY == 1 )\r\n\r\n\tvoid vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle )\r\n\t{\r\n\tTCB_t *pxTCB;\r\n\r\n\t\tif( xTask != NULL )\r\n\t\t{\r\n\t\t\tpxTCB = ( TCB_t * ) xTask;\r\n\t\t\tpxTCB->uxTaskNumber = uxHandle;\r\n\t\t}\r\n\t}\r\n\r\n#endif /* configUSE_TRACE_FACILITY */\r\n\r\n/*\r\n * -----------------------------------------------------------\r\n * The Idle task.\r\n * ----------------------------------------------------------\r\n *\r\n * The portTASK_FUNCTION() macro is used to allow port/compiler specific\r\n * language extensions.  The equivalent prototype for this function is:\r\n *\r\n * void prvIdleTask( void *pvParameters );\r\n *\r\n */\r\nstatic portTASK_FUNCTION( prvIdleTask, pvParameters )\r\n{\r\n\t/* Stop warnings. */\r\n\t( void ) pvParameters;\r\n\r\n\tfor( ;; )\r\n\t{\r\n\t\t/* See if any tasks have been deleted. */\r\n\t\tprvCheckTasksWaitingTermination();\r\n\r\n\t\t#if ( configUSE_PREEMPTION == 0 )\r\n\t\t{\r\n\t\t\t/* If we are not using preemption we keep forcing a task switch to\r\n\t\t\tsee if any other task has become available.  If we are using\r\n\t\t\tpreemption we don't need to do this as any task becoming available\r\n\t\t\twill automatically get the processor anyway. */\r\n\t\t\ttaskYIELD();\r\n\t\t}\r\n\t\t#endif /* configUSE_PREEMPTION */\r\n\r\n\t\t#if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )\r\n\t\t{\r\n\t\t\t/* When using preemption tasks of equal priority will be\r\n\t\t\ttimesliced.  If a task that is sharing the idle priority is ready\r\n\t\t\tto run then the idle task should yield before the end of the\r\n\t\t\ttimeslice.\r\n\r\n\t\t\tA critical region is not required here as we are just reading from\r\n\t\t\tthe list, and an occasional incorrect value will not matter.  If\r\n\t\t\tthe ready list at the idle priority contains more than one task\r\n\t\t\tthen a task other than the idle task is ready to execute. */\r\n\t\t\tif( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )\r\n\t\t\t{\r\n\t\t\t\ttaskYIELD();\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\t\t}\r\n\t\t#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */\r\n\r\n\t\t#if ( configUSE_IDLE_HOOK == 1 )\r\n\t\t{\r\n\t\t\textern void vApplicationIdleHook( void );\r\n\r\n\t\t\t/* Call the user defined function from within the idle task.  This\r\n\t\t\tallows the application designer to add background functionality\r\n\t\t\twithout the overhead of a separate task.\r\n\t\t\tNOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,\r\n\t\t\tCALL A FUNCTION THAT MIGHT BLOCK. */\r\n\t\t\tvApplicationIdleHook();\r\n\t\t}\r\n\t\t#endif /* configUSE_IDLE_HOOK */\r\n\r\n\t\t/* This conditional compilation should use inequality to 0, not equality\r\n\t\tto 1.  This is to ensure portSUPPRESS_TICKS_AND_SLEEP() is called when\r\n\t\tuser defined low power mode\timplementations require\r\n\t\tconfigUSE_TICKLESS_IDLE to be set to a value other than 1. */\r\n\t\t#if ( configUSE_TICKLESS_IDLE != 0 )\r\n\t\t{\r\n\t\tTickType_t xExpectedIdleTime;\r\n\r\n\t\t\t/* It is not desirable to suspend then resume the scheduler on\r\n\t\t\teach iteration of the idle task.  Therefore, a preliminary\r\n\t\t\ttest of the expected idle time is performed without the\r\n\t\t\tscheduler suspended.  The result here is not necessarily\r\n\t\t\tvalid. */\r\n\t\t\txExpectedIdleTime = prvGetExpectedIdleTime();\r\n\r\n\t\t\tif( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )\r\n\t\t\t{\r\n\t\t\t\tvTaskSuspendAll();\r\n\t\t\t\t{\r\n\t\t\t\t\t/* Now the scheduler is suspended, the expected idle\r\n\t\t\t\t\ttime can be sampled again, and this time its value can\r\n\t\t\t\t\tbe used. */\r\n\t\t\t\t\tconfigASSERT( xNextTaskUnblockTime >= xTickCount );\r\n\t\t\t\t\txExpectedIdleTime = prvGetExpectedIdleTime();\r\n\r\n\t\t\t\t\tif( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\ttraceLOW_POWER_IDLE_BEGIN();\r\n\t\t\t\t\t\tportSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime );\r\n\t\t\t\t\t\ttraceLOW_POWER_IDLE_END();\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t\t( void ) xTaskResumeAll();\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\t\t}\r\n\t\t#endif /* configUSE_TICKLESS_IDLE */\r\n\t}\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\n#if configUSE_TICKLESS_IDLE != 0\r\n\r\n\teSleepModeStatus eTaskConfirmSleepModeStatus( void )\r\n\t{\r\n\teSleepModeStatus eReturn = eStandardSleep;\r\n\r\n\t\tif( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0 )\r\n\t\t{\r\n\t\t\t/* A task was made ready while the scheduler was suspended. */\r\n\t\t\teReturn = eAbortSleep;\r\n\t\t}\r\n\t\telse if( xYieldPending != pdFALSE )\r\n\t\t{\r\n\t\t\t/* A yield was pended while the scheduler was suspended. */\r\n\t\t\teReturn = eAbortSleep;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\t#if configUSE_TIMERS == 0\r\n\t\t\t{\r\n\t\t\t\t/* The idle task exists in addition to the application tasks. */\r\n\t\t\t\tconst UBaseType_t uxNonApplicationTasks = 1;\r\n\r\n\t\t\t\t/* If timers are not being used and all the tasks are in the\r\n\t\t\t\tsuspended list (which might mean they have an infinite block\r\n\t\t\t\ttime rather than actually being suspended) then it is safe to\r\n\t\t\t\tturn all clocks off and just wait for external interrupts. */\r\n\t\t\t\tif( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == ( uxCurrentNumberOfTasks - uxNonApplicationTasks ) )\r\n\t\t\t\t{\r\n\t\t\t\t\teReturn = eNoTasksWaitingTimeout;\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\t#endif /* configUSE_TIMERS */\r\n\t\t}\r\n\r\n\t\treturn eReturn;\r\n\t}\r\n#endif /* configUSE_TICKLESS_IDLE */\r\n/*-----------------------------------------------------------*/\r\n\r\nstatic void prvInitialiseTCBVariables( TCB_t * const pxTCB, const char * const pcName, UBaseType_t uxPriority, const MemoryRegion_t * const xRegions, const uint16_t usStackDepth ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\r\n{\r\nUBaseType_t x;\r\n\r\n\t/* Store the task name in the TCB. */\r\n\tfor( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )\r\n\t{\r\n\t\tpxTCB->pcTaskName[ x ] = pcName[ x ];\r\n\r\n\t\t/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than\r\n\t\tconfigMAX_TASK_NAME_LEN characters just in case the memory after the\r\n\t\tstring is not accessible (extremely unlikely). */\r\n\t\tif( pcName[ x ] == 0x00 )\r\n\t\t{\r\n\t\t\tbreak;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t}\r\n\t}\r\n\r\n\t/* Ensure the name string is terminated in the case that the string length\r\n\twas greater or equal to configMAX_TASK_NAME_LEN. */\r\n\tpxTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\\0';\r\n\r\n\t/* This is used as an array index so must ensure it's not too large.  First\r\n\tremove the privilege bit if one is present. */\r\n\tif( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )\r\n\t{\r\n\t\tuxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;\r\n\t}\r\n\telse\r\n\t{\r\n\t\tmtCOVERAGE_TEST_MARKER();\r\n\t}\r\n\r\n\tpxTCB->uxPriority = uxPriority;\r\n\t#if ( configUSE_MUTEXES == 1 )\r\n\t{\r\n\t\tpxTCB->uxBasePriority = uxPriority;\r\n\t\tpxTCB->uxMutexesHeld = 0;\r\n\t}\r\n\t#endif /* configUSE_MUTEXES */\r\n\r\n\tvListInitialiseItem( &( pxTCB->xGenericListItem ) );\r\n\tvListInitialiseItem( &( pxTCB->xEventListItem ) );\r\n\r\n\t/* Set the pxTCB as a link back from the ListItem_t.  This is so we can get\r\n\tback to\tthe containing TCB from a generic item in a list. */\r\n\tlistSET_LIST_ITEM_OWNER( &( pxTCB->xGenericListItem ), pxTCB );\r\n\r\n\t/* Event lists are always in priority order. */\r\n\tlistSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\r\n\tlistSET_LIST_ITEM_OWNER( &( pxTCB->xEventListItem ), pxTCB );\r\n\r\n\t#if ( portCRITICAL_NESTING_IN_TCB == 1 )\r\n\t{\r\n\t\tpxTCB->uxCriticalNesting = ( UBaseType_t ) 0U;\r\n\t}\r\n\t#endif /* portCRITICAL_NESTING_IN_TCB */\r\n\r\n\t#if ( configUSE_APPLICATION_TASK_TAG == 1 )\r\n\t{\r\n\t\tpxTCB->pxTaskTag = NULL;\r\n\t}\r\n\t#endif /* configUSE_APPLICATION_TASK_TAG */\r\n\r\n\t#if ( configGENERATE_RUN_TIME_STATS == 1 )\r\n\t{\r\n\t\tpxTCB->ulRunTimeCounter = 0UL;\r\n\t}\r\n\t#endif /* configGENERATE_RUN_TIME_STATS */\r\n\r\n\t#if ( portUSING_MPU_WRAPPERS == 1 )\r\n\t{\r\n\t\tvPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, pxTCB->pxStack, usStackDepth );\r\n\t}\r\n\t#else /* portUSING_MPU_WRAPPERS */\r\n\t{\r\n\t\t( void ) xRegions;\r\n\t\t( void ) usStackDepth;\r\n\t}\r\n\t#endif /* portUSING_MPU_WRAPPERS */\r\n\r\n\t#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )\r\n\t{\r\n\t\tfor( x = 0; x < ( UBaseType_t ) configNUM_THREAD_LOCAL_STORAGE_POINTERS; x++ )\r\n\t\t{\r\n\t\t\tpxTCB->pvThreadLocalStoragePointers[ x ] = NULL;\r\n\t\t}\r\n\t}\r\n\t#endif\r\n\r\n\t#if ( configUSE_TASK_NOTIFICATIONS == 1 )\r\n\t{\r\n\t\tpxTCB->ulNotifiedValue = 0;\r\n\t\tpxTCB->eNotifyState = eNotWaitingNotification;\r\n\t}\r\n\t#endif\r\n\r\n\t#if ( configUSE_NEWLIB_REENTRANT == 1 )\r\n\t{\r\n\t\t/* Initialise this task's Newlib reent structure. */\r\n\t\t_REENT_INIT_PTR( ( &( pxTCB->xNewLib_reent ) ) );\r\n\t}\r\n\t#endif /* configUSE_NEWLIB_REENTRANT */\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )\r\n\r\n\tvoid vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue )\r\n\t{\r\n\tTCB_t *pxTCB;\r\n\r\n\t\tif( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )\r\n\t\t{\r\n\t\t\tpxTCB = prvGetTCBFromHandle( xTaskToSet );\r\n\t\t\tpxTCB->pvThreadLocalStoragePointers[ xIndex ] = pvValue;\r\n\t\t}\r\n\t}\r\n\r\n#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )\r\n\r\n\tvoid *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex )\r\n\t{\r\n\tvoid *pvReturn = NULL;\r\n\tTCB_t *pxTCB;\r\n\r\n\t\tif( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )\r\n\t\t{\r\n\t\t\tpxTCB = prvGetTCBFromHandle( xTaskToQuery );\r\n\t\t\tpvReturn = pxTCB->pvThreadLocalStoragePointers[ xIndex ];\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tpvReturn = NULL;\r\n\t\t}\r\n\r\n\t\treturn pvReturn;\r\n\t}\r\n\r\n#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( portUSING_MPU_WRAPPERS == 1 )\r\n\r\n\tvoid vTaskAllocateMPURegions( TaskHandle_t xTaskToModify, const MemoryRegion_t * const xRegions )\r\n\t{\r\n\tTCB_t *pxTCB;\r\n\r\n\t\t/* If null is passed in here then we are deleting ourselves. */\r\n\t\tpxTCB = prvGetTCBFromHandle( xTaskToModify );\r\n\r\n        vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, NULL, 0 );\r\n\t}\r\n\r\n#endif /* portUSING_MPU_WRAPPERS */\r\n/*-----------------------------------------------------------*/\r\n\r\nstatic void prvInitialiseTaskLists( void )\r\n{\r\nUBaseType_t uxPriority;\r\n\r\n\tfor( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )\r\n\t{\r\n\t\tvListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );\r\n\t}\r\n\r\n\tvListInitialise( &xDelayedTaskList1 );\r\n\tvListInitialise( &xDelayedTaskList2 );\r\n\tvListInitialise( &xPendingReadyList );\r\n\r\n\t#if ( INCLUDE_vTaskDelete == 1 )\r\n\t{\r\n\t\tvListInitialise( &xTasksWaitingTermination );\r\n\t}\r\n\t#endif /* INCLUDE_vTaskDelete */\r\n\r\n\t#if ( INCLUDE_vTaskSuspend == 1 )\r\n\t{\r\n\t\tvListInitialise( &xSuspendedTaskList );\r\n\t}\r\n\t#endif /* INCLUDE_vTaskSuspend */\r\n\r\n\t/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList\r\n\tusing list2. */\r\n\tpxDelayedTaskList = &xDelayedTaskList1;\r\n\tpxOverflowDelayedTaskList = &xDelayedTaskList2;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nstatic void prvCheckTasksWaitingTermination( void )\r\n{\r\n\t#if ( INCLUDE_vTaskDelete == 1 )\r\n\t{\r\n\t\tBaseType_t xListIsEmpty;\r\n\r\n\t\t/* ucTasksDeleted is used to prevent vTaskSuspendAll() being called\r\n\t\ttoo often in the idle task. */\r\n\t\twhile( uxTasksDeleted > ( UBaseType_t ) 0U )\r\n\t\t{\r\n\t\t\tvTaskSuspendAll();\r\n\t\t\t{\r\n\t\t\t\txListIsEmpty = listLIST_IS_EMPTY( &xTasksWaitingTermination );\r\n\t\t\t}\r\n\t\t\t( void ) xTaskResumeAll();\r\n\r\n\t\t\tif( xListIsEmpty == pdFALSE )\r\n\t\t\t{\r\n\t\t\t\tTCB_t *pxTCB;\r\n\r\n\t\t\t\ttaskENTER_CRITICAL();\r\n\t\t\t\t{\r\n\t\t\t\t\tpxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) );\r\n\t\t\t\t\t( void ) uxListRemove( &( pxTCB->xGenericListItem ) );\r\n\t\t\t\t\t--uxCurrentNumberOfTasks;\r\n\t\t\t\t\t--uxTasksDeleted;\r\n\t\t\t\t}\r\n\t\t\t\ttaskEXIT_CRITICAL();\r\n\r\n\t\t\t\tprvDeleteTCB( pxTCB );\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\t\t}\r\n\t}\r\n\t#endif /* vTaskDelete */\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nstatic void prvAddCurrentTaskToDelayedList( const TickType_t xTimeToWake )\r\n{\r\n\t/* The list item will be inserted in wake time order. */\r\n\tlistSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake );\r\n\r\n\tif( xTimeToWake < xTickCount )\r\n\t{\r\n\t\t/* Wake time has overflowed.  Place this item in the overflow list. */\r\n\t\tvListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xGenericListItem ) );\r\n\t}\r\n\telse\r\n\t{\r\n\t\t/* The wake time has not overflowed, so the current block list is used. */\r\n\t\tvListInsert( pxDelayedTaskList, &( pxCurrentTCB->xGenericListItem ) );\r\n\r\n\t\t/* If the task entering the blocked state was placed at the head of the\r\n\t\tlist of blocked tasks then xNextTaskUnblockTime needs to be updated\r\n\t\ttoo. */\r\n\t\tif( xTimeToWake < xNextTaskUnblockTime )\r\n\t\t{\r\n\t\t\txNextTaskUnblockTime = xTimeToWake;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t}\r\n\t}\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nstatic TCB_t *prvAllocateTCBAndStack( const uint16_t usStackDepth, StackType_t * const puxStackBuffer )\r\n{\r\nTCB_t *pxNewTCB;\r\n\r\n\t/* If the stack grows down then allocate the stack then the TCB so the stack\r\n\tdoes not grow into the TCB.  Likewise if the stack grows up then allocate\r\n\tthe TCB then the stack. */\r\n\t#if( portSTACK_GROWTH > 0 )\r\n\t{\r\n\t\t/* Allocate space for the TCB.  Where the memory comes from depends on\r\n\t\tthe implementation of the port malloc function. */\r\n\t\tpxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );\r\n\r\n\t\tif( pxNewTCB != NULL )\r\n\t\t{\r\n\t\t\t/* Allocate space for the stack used by the task being created.\r\n\t\t\tThe base of the stack memory stored in the TCB so the task can\r\n\t\t\tbe deleted later if required. */\r\n\t\t\tpxNewTCB->pxStack = ( StackType_t * ) pvPortMallocAligned( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ), puxStackBuffer ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\r\n\r\n\t\t\tif( pxNewTCB->pxStack == NULL )\r\n\t\t\t{\r\n\t\t\t\t/* Could not allocate the stack.  Delete the allocated TCB. */\r\n\t\t\t\tvPortFree( pxNewTCB );\r\n\t\t\t\tpxNewTCB = NULL;\r\n\t\t\t}\r\n\t\t}\r\n\t}\r\n\t#else /* portSTACK_GROWTH */\r\n\t{\r\n\tStackType_t *pxStack;\r\n\r\n\t\t/* Allocate space for the stack used by the task being created. */\r\n\t\tpxStack = ( StackType_t * ) pvPortMallocAligned( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ), puxStackBuffer ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\r\n\r\n\t\tif( pxStack != NULL )\r\n\t\t{\r\n\t\t\t/* Allocate space for the TCB.  Where the memory comes from depends\r\n\t\t\ton the implementation of the port malloc function. */\r\n\t\t\tpxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );\r\n\r\n\t\t\tif( pxNewTCB != NULL )\r\n\t\t\t{\r\n\t\t\t\t/* Store the stack location in the TCB. */\r\n\t\t\t\tpxNewTCB->pxStack = pxStack;\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\t/* The stack cannot be used as the TCB was not created.  Free it\r\n\t\t\t\tagain. */\r\n\t\t\t\tvPortFree( pxStack );\r\n\t\t\t}\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tpxNewTCB = NULL;\r\n\t\t}\r\n\t}\r\n\t#endif /* portSTACK_GROWTH */\r\n\r\n\tif( pxNewTCB != NULL )\r\n\t{\r\n\t\t/* Avoid dependency on memset() if it is not required. */\r\n\t\t#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )\r\n\t\t{\r\n\t\t\t/* Just to help debugging. */\r\n\t\t\t( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) usStackDepth * sizeof( StackType_t ) );\r\n\t\t}\r\n\t\t#endif /* ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) ) ) */\r\n\t}\r\n\r\n\treturn pxNewTCB;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( configUSE_TRACE_FACILITY == 1 )\r\n\r\n\tstatic UBaseType_t prvListTaskWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState )\r\n\t{\r\n\tvolatile TCB_t *pxNextTCB, *pxFirstTCB;\r\n\tUBaseType_t uxTask = 0;\r\n\r\n\t\tif( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )\r\n\t\t{\r\n\t\t\tlistGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );\r\n\r\n\t\t\t/* Populate an TaskStatus_t structure within the\r\n\t\t\tpxTaskStatusArray array for each task that is referenced from\r\n\t\t\tpxList.  See the definition of TaskStatus_t in task.h for the\r\n\t\t\tmeaning of each TaskStatus_t structure member. */\r\n\t\t\tdo\r\n\t\t\t{\r\n\t\t\t\tlistGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList );\r\n\r\n\t\t\t\tpxTaskStatusArray[ uxTask ].xHandle = ( TaskHandle_t ) pxNextTCB;\r\n\t\t\t\tpxTaskStatusArray[ uxTask ].pcTaskName = ( const char * ) &( pxNextTCB->pcTaskName [ 0 ] );\r\n\t\t\t\tpxTaskStatusArray[ uxTask ].xTaskNumber = pxNextTCB->uxTCBNumber;\r\n\t\t\t\tpxTaskStatusArray[ uxTask ].eCurrentState = eState;\r\n\t\t\t\tpxTaskStatusArray[ uxTask ].uxCurrentPriority = pxNextTCB->uxPriority;\r\n\r\n\t\t\t\t#if ( INCLUDE_vTaskSuspend == 1 )\r\n\t\t\t\t{\r\n\t\t\t\t\t/* If the task is in the suspended list then there is a chance\r\n\t\t\t\t\tit is actually just blocked indefinitely - so really it should\r\n\t\t\t\t\tbe reported as being in the Blocked state. */\r\n\t\t\t\t\tif( eState == eSuspended )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tif( listLIST_ITEM_CONTAINER( &( pxNextTCB->xEventListItem ) ) != NULL )\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\tpxTaskStatusArray[ uxTask ].eCurrentState = eBlocked;\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t\t#endif /* INCLUDE_vTaskSuspend */\r\n\r\n\t\t\t\t#if ( configUSE_MUTEXES == 1 )\r\n\t\t\t\t{\r\n\t\t\t\t\tpxTaskStatusArray[ uxTask ].uxBasePriority = pxNextTCB->uxBasePriority;\r\n\t\t\t\t}\r\n\t\t\t\t#else\r\n\t\t\t\t{\r\n\t\t\t\t\tpxTaskStatusArray[ uxTask ].uxBasePriority = 0;\r\n\t\t\t\t}\r\n\t\t\t\t#endif\r\n\r\n\t\t\t\t#if ( configGENERATE_RUN_TIME_STATS == 1 )\r\n\t\t\t\t{\r\n\t\t\t\t\tpxTaskStatusArray[ uxTask ].ulRunTimeCounter = pxNextTCB->ulRunTimeCounter;\r\n\t\t\t\t}\r\n\t\t\t\t#else\r\n\t\t\t\t{\r\n\t\t\t\t\tpxTaskStatusArray[ uxTask ].ulRunTimeCounter = 0;\r\n\t\t\t\t}\r\n\t\t\t\t#endif\r\n\r\n\t\t\t\t#if ( portSTACK_GROWTH > 0 )\r\n\t\t\t\t{\r\n\t\t\t\t\tpxTaskStatusArray[ uxTask ].usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxNextTCB->pxEndOfStack );\r\n\t\t\t\t}\r\n\t\t\t\t#else\r\n\t\t\t\t{\r\n\t\t\t\t\tpxTaskStatusArray[ uxTask ].usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxNextTCB->pxStack );\r\n\t\t\t\t}\r\n\t\t\t\t#endif\r\n\r\n\t\t\t\tuxTask++;\r\n\r\n\t\t\t} while( pxNextTCB != pxFirstTCB );\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t}\r\n\r\n\t\treturn uxTask;\r\n\t}\r\n\r\n#endif /* configUSE_TRACE_FACILITY */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )\r\n\r\n\tstatic uint16_t prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )\r\n\t{\r\n\tuint32_t ulCount = 0U;\r\n\r\n\t\twhile( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE )\r\n\t\t{\r\n\t\t\tpucStackByte -= portSTACK_GROWTH;\r\n\t\t\tulCount++;\r\n\t\t}\r\n\r\n\t\tulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */\r\n\r\n\t\treturn ( uint16_t ) ulCount;\r\n\t}\r\n\r\n#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) ) */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )\r\n\r\n\tUBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask )\r\n\t{\r\n\tTCB_t *pxTCB;\r\n\tuint8_t *pucEndOfStack;\r\n\tUBaseType_t uxReturn;\r\n\r\n\t\tpxTCB = prvGetTCBFromHandle( xTask );\r\n\r\n\t\t#if portSTACK_GROWTH < 0\r\n\t\t{\r\n\t\t\tpucEndOfStack = ( uint8_t * ) pxTCB->pxStack;\r\n\t\t}\r\n\t\t#else\r\n\t\t{\r\n\t\t\tpucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;\r\n\t\t}\r\n\t\t#endif\r\n\r\n\t\tuxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack );\r\n\r\n\t\treturn uxReturn;\r\n\t}\r\n\r\n#endif /* INCLUDE_uxTaskGetStackHighWaterMark */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( INCLUDE_vTaskDelete == 1 )\r\n\r\n\tstatic void prvDeleteTCB( TCB_t *pxTCB )\r\n\t{\r\n\t\t/* This call is required specifically for the TriCore port.  It must be\r\n\t\tabove the vPortFree() calls.  The call is also used by ports/demos that\r\n\t\twant to allocate and clean RAM statically. */\r\n\t\tportCLEAN_UP_TCB( pxTCB );\r\n\r\n\t\t/* Free up the memory allocated by the scheduler for the task.  It is up\r\n\t\tto the task to free any memory allocated at the application level. */\r\n\t\t#if ( configUSE_NEWLIB_REENTRANT == 1 )\r\n\t\t{\r\n\t\t\t_reclaim_reent( &( pxTCB->xNewLib_reent ) );\r\n\t\t}\r\n\t\t#endif /* configUSE_NEWLIB_REENTRANT */\r\n\r\n\t\t#if( portUSING_MPU_WRAPPERS == 1 )\r\n\t\t{\r\n\t\t\t/* Only free the stack if it was allocated dynamically in the first\r\n\t\t\tplace. */\r\n\t\t\tif( pxTCB->xUsingStaticallyAllocatedStack == pdFALSE )\r\n\t\t\t{\r\n\t\t\t\tvPortFreeAligned( pxTCB->pxStack );\r\n\t\t\t}\r\n\t\t}\r\n\t\t#else\r\n\t\t{\r\n\t\t\tvPortFreeAligned( pxTCB->pxStack );\r\n\t\t}\r\n\t\t#endif\r\n\r\n\t\tvPortFree( pxTCB );\r\n\t}\r\n\r\n#endif /* INCLUDE_vTaskDelete */\r\n/*-----------------------------------------------------------*/\r\n\r\nstatic void prvResetNextTaskUnblockTime( void )\r\n{\r\nTCB_t *pxTCB;\r\n\r\n\tif( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )\r\n\t{\r\n\t\t/* The new current delayed list is empty.  Set xNextTaskUnblockTime to\r\n\t\tthe maximum possible value so it is\textremely unlikely that the\r\n\t\tif( xTickCount >= xNextTaskUnblockTime ) test will pass until\r\n\t\tthere is an item in the delayed list. */\r\n\t\txNextTaskUnblockTime = portMAX_DELAY;\r\n\t}\r\n\telse\r\n\t{\r\n\t\t/* The new current delayed list is not empty, get the value of\r\n\t\tthe item at the head of the delayed list.  This is the time at\r\n\t\twhich the task at the head of the delayed list should be removed\r\n\t\tfrom the Blocked state. */\r\n\t\t( pxTCB ) = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList );\r\n\t\txNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xGenericListItem ) );\r\n\t}\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )\r\n\r\n\tTaskHandle_t xTaskGetCurrentTaskHandle( void )\r\n\t{\r\n\tTaskHandle_t xReturn;\r\n\r\n\t\t/* A critical section is not required as this is not called from\r\n\t\tan interrupt and the current TCB will always be the same for any\r\n\t\tindividual execution thread. */\r\n\t\txReturn = pxCurrentTCB;\r\n\r\n\t\treturn xReturn;\r\n\t}\r\n\r\n#endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\r\n\r\n\tBaseType_t xTaskGetSchedulerState( void )\r\n\t{\r\n\tBaseType_t xReturn;\r\n\r\n\t\tif( xSchedulerRunning == pdFALSE )\r\n\t\t{\r\n\t\t\txReturn = taskSCHEDULER_NOT_STARTED;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tif( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\r\n\t\t\t{\r\n\t\t\t\txReturn = taskSCHEDULER_RUNNING;\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\txReturn = taskSCHEDULER_SUSPENDED;\r\n\t\t\t}\r\n\t\t}\r\n\r\n\t\treturn xReturn;\r\n\t}\r\n\r\n#endif /* ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( configUSE_MUTEXES == 1 )\r\n\r\n\tvoid vTaskPriorityInherit( TaskHandle_t const pxMutexHolder )\r\n\t{\r\n\tTCB_t * const pxTCB = ( TCB_t * ) pxMutexHolder;\r\n\r\n\t\t/* If the mutex was given back by an interrupt while the queue was\r\n\t\tlocked then the mutex holder might now be NULL. */\r\n\t\tif( pxMutexHolder != NULL )\r\n\t\t{\r\n\t\t\t/* If the holder of the mutex has a priority below the priority of\r\n\t\t\tthe task attempting to obtain the mutex then it will temporarily\r\n\t\t\tinherit the priority of the task attempting to obtain the mutex. */\r\n\t\t\tif( pxTCB->uxPriority < pxCurrentTCB->uxPriority )\r\n\t\t\t{\r\n\t\t\t\t/* Adjust the mutex holder state to account for its new\r\n\t\t\t\tpriority.  Only reset the event list item value if the value is\r\n\t\t\t\tnot\tbeing used for anything else. */\r\n\t\t\t\tif( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )\r\n\t\t\t\t{\r\n\t\t\t\t\tlistSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\r\n\t\t\t\t/* If the task being modified is in the ready state it will need\r\n\t\t\t\tto be moved into a new list. */\r\n\t\t\t\tif( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxTCB->uxPriority ] ), &( pxTCB->xGenericListItem ) ) != pdFALSE )\r\n\t\t\t\t{\r\n\t\t\t\t\tif( uxListRemove( &( pxTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\ttaskRESET_READY_PRIORITY( pxTCB->uxPriority );\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t}\r\n\r\n\t\t\t\t\t/* Inherit the priority before being moved into the new list. */\r\n\t\t\t\t\tpxTCB->uxPriority = pxCurrentTCB->uxPriority;\r\n\t\t\t\t\tprvAddTaskToReadyList( pxTCB );\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\t/* Just inherit the priority. */\r\n\t\t\t\t\tpxTCB->uxPriority = pxCurrentTCB->uxPriority;\r\n\t\t\t\t}\r\n\r\n\t\t\t\ttraceTASK_PRIORITY_INHERIT( pxTCB, pxCurrentTCB->uxPriority );\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t}\r\n\t}\r\n\r\n#endif /* configUSE_MUTEXES */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( configUSE_MUTEXES == 1 )\r\n\r\n\tBaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )\r\n\t{\r\n\tTCB_t * const pxTCB = ( TCB_t * ) pxMutexHolder;\r\n\tBaseType_t xReturn = pdFALSE;\r\n\r\n\t\tif( pxMutexHolder != NULL )\r\n\t\t{\r\n\t\t\t/* A task can only have an inherited priority if it holds the mutex.\r\n\t\t\tIf the mutex is held by a task then it cannot be given from an\r\n\t\t\tinterrupt, and if a mutex is given by the holding task then it must\r\n\t\t\tbe the running state task. */\r\n\t\t\tconfigASSERT( pxTCB == pxCurrentTCB );\r\n\r\n\t\t\tconfigASSERT( pxTCB->uxMutexesHeld );\r\n\t\t\t( pxTCB->uxMutexesHeld )--;\r\n\r\n\t\t\t/* Has the holder of the mutex inherited the priority of another\r\n\t\t\ttask? */\r\n\t\t\tif( pxTCB->uxPriority != pxTCB->uxBasePriority )\r\n\t\t\t{\r\n\t\t\t\t/* Only disinherit if no other mutexes are held. */\r\n\t\t\t\tif( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )\r\n\t\t\t\t{\r\n\t\t\t\t\t/* A task can only have an inherited priority if it holds\r\n\t\t\t\t\tthe mutex.  If the mutex is held by a task then it cannot be\r\n\t\t\t\t\tgiven from an interrupt, and if a mutex is given by the\r\n\t\t\t\t\tholding\ttask then it must be the running state task.  Remove\r\n\t\t\t\t\tthe\tholding task from the ready\tlist. */\r\n\t\t\t\t\tif( uxListRemove( &( pxTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\ttaskRESET_READY_PRIORITY( pxTCB->uxPriority );\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t}\r\n\r\n\t\t\t\t\t/* Disinherit the priority before adding the task into the\r\n\t\t\t\t\tnew\tready list. */\r\n\t\t\t\t\ttraceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );\r\n\t\t\t\t\tpxTCB->uxPriority = pxTCB->uxBasePriority;\r\n\r\n\t\t\t\t\t/* Reset the event list item value.  It cannot be in use for\r\n\t\t\t\t\tany other purpose if this task is running, and it must be\r\n\t\t\t\t\trunning to give back the mutex. */\r\n\t\t\t\t\tlistSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\r\n\t\t\t\t\tprvAddTaskToReadyList( pxTCB );\r\n\r\n\t\t\t\t\t/* Return true to indicate that a context switch is required.\r\n\t\t\t\t\tThis is only actually required in the corner case whereby\r\n\t\t\t\t\tmultiple mutexes were held and the mutexes were given back\r\n\t\t\t\t\tin an order different to that in which they were taken.\r\n\t\t\t\t\tIf a context switch did not occur when the first mutex was\r\n\t\t\t\t\treturned, even if a task was waiting on it, then a context\r\n\t\t\t\t\tswitch should occur when the last mutex is returned whether\r\n\t\t\t\t\ta task is waiting on it or not. */\r\n\t\t\t\t\txReturn = pdTRUE;\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t}\r\n\r\n\t\treturn xReturn;\r\n\t}\r\n\r\n#endif /* configUSE_MUTEXES */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( portCRITICAL_NESTING_IN_TCB == 1 )\r\n\r\n\tvoid vTaskEnterCritical( void )\r\n\t{\r\n\t\tportDISABLE_INTERRUPTS();\r\n\r\n\t\tif( xSchedulerRunning != pdFALSE )\r\n\t\t{\r\n\t\t\t( pxCurrentTCB->uxCriticalNesting )++;\r\n\r\n\t\t\t/* This is not the interrupt safe version of the enter critical\r\n\t\t\tfunction so\tassert() if it is being called from an interrupt\r\n\t\t\tcontext.  Only API functions that end in \"FromISR\" can be used in an\r\n\t\t\tinterrupt.  Only assert if the critical nesting count is 1 to\r\n\t\t\tprotect against recursive calls if the assert function also uses a\r\n\t\t\tcritical section. */\r\n\t\t\tif( pxCurrentTCB->uxCriticalNesting == 1 )\r\n\t\t\t{\r\n\t\t\t\tportASSERT_IF_IN_ISR();\r\n\t\t\t}\r\n\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t}\r\n\t}\r\n\r\n#endif /* portCRITICAL_NESTING_IN_TCB */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( portCRITICAL_NESTING_IN_TCB == 1 )\r\n\r\n\tvoid vTaskExitCritical( void )\r\n\t{\r\n\t\tif( xSchedulerRunning != pdFALSE )\r\n\t\t{\r\n\t\t\tif( pxCurrentTCB->uxCriticalNesting > 0U )\r\n\t\t\t{\r\n\t\t\t\t( pxCurrentTCB->uxCriticalNesting )--;\r\n\r\n\t\t\t\tif( pxCurrentTCB->uxCriticalNesting == 0U )\r\n\t\t\t\t{\r\n\t\t\t\t\tportENABLE_INTERRUPTS();\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t}\r\n\t}\r\n\r\n#endif /* portCRITICAL_NESTING_IN_TCB */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )\r\n\r\n\tstatic char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName )\r\n\t{\r\n\tBaseType_t x;\r\n\r\n\t\t/* Start by copying the entire string. */\r\n\t\tstrcpy( pcBuffer, pcTaskName );\r\n\r\n\t\t/* Pad the end of the string with spaces to ensure columns line up when\r\n\t\tprinted out. */\r\n\t\tfor( x = strlen( pcBuffer ); x < ( configMAX_TASK_NAME_LEN - 1 ); x++ )\r\n\t\t{\r\n\t\t\tpcBuffer[ x ] = ' ';\r\n\t\t}\r\n\r\n\t\t/* Terminate. */\r\n\t\tpcBuffer[ x ] = 0x00;\r\n\r\n\t\t/* Return the new end of string. */\r\n\t\treturn &( pcBuffer[ x ] );\r\n\t}\r\n\r\n#endif /* ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )\r\n\r\n\tvoid vTaskList( char * pcWriteBuffer )\r\n\t{\r\n\tTaskStatus_t *pxTaskStatusArray;\r\n\tvolatile UBaseType_t uxArraySize, x;\r\n\tchar cStatus;\r\n\r\n\t\t/*\r\n\t\t * PLEASE NOTE:\r\n\t\t *\r\n\t\t * This function is provided for convenience only, and is used by many\r\n\t\t * of the demo applications.  Do not consider it to be part of the\r\n\t\t * scheduler.\r\n\t\t *\r\n\t\t * vTaskList() calls uxTaskGetSystemState(), then formats part of the\r\n\t\t * uxTaskGetSystemState() output into a human readable table that\r\n\t\t * displays task names, states and stack usage.\r\n\t\t *\r\n\t\t * vTaskList() has a dependency on the sprintf() C library function that\r\n\t\t * might bloat the code size, use a lot of stack, and provide different\r\n\t\t * results on different platforms.  An alternative, tiny, third party,\r\n\t\t * and limited functionality implementation of sprintf() is provided in\r\n\t\t * many of the FreeRTOS/Demo sub-directories in a file called\r\n\t\t * printf-stdarg.c (note printf-stdarg.c does not provide a full\r\n\t\t * snprintf() implementation!).\r\n\t\t *\r\n\t\t * It is recommended that production systems call uxTaskGetSystemState()\r\n\t\t * directly to get access to raw stats data, rather than indirectly\r\n\t\t * through a call to vTaskList().\r\n\t\t */\r\n\r\n\r\n\t\t/* Make sure the write buffer does not contain a string. */\r\n\t\t*pcWriteBuffer = 0x00;\r\n\r\n\t\t/* Take a snapshot of the number of tasks in case it changes while this\r\n\t\tfunction is executing. */\r\n\t\tuxArraySize = uxCurrentNumberOfTasks;\r\n\r\n\t\t/* Allocate an array index for each task. */\r\n\t\tpxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) );\r\n\r\n\t\tif( pxTaskStatusArray != NULL )\r\n\t\t{\r\n\t\t\t/* Generate the (binary) data. */\r\n\t\t\tuxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, NULL );\r\n\r\n\t\t\t/* Create a human readable table from the binary data. */\r\n\t\t\tfor( x = 0; x < uxArraySize; x++ )\r\n\t\t\t{\r\n\t\t\t\tswitch( pxTaskStatusArray[ x ].eCurrentState )\r\n\t\t\t\t{\r\n\t\t\t\t\tcase eReady:\t\tcStatus = tskREADY_CHAR;\r\n\t\t\t\t\t\t\t\t\t\tbreak;\r\n\r\n\t\t\t\t\tcase eBlocked:\t\tcStatus = tskBLOCKED_CHAR;\r\n\t\t\t\t\t\t\t\t\t\tbreak;\r\n\r\n\t\t\t\t\tcase eSuspended:\tcStatus = tskSUSPENDED_CHAR;\r\n\t\t\t\t\t\t\t\t\t\tbreak;\r\n\r\n\t\t\t\t\tcase eDeleted:\t\tcStatus = tskDELETED_CHAR;\r\n\t\t\t\t\t\t\t\t\t\tbreak;\r\n\r\n\t\t\t\t\tdefault:\t\t\t/* Should not get here, but it is included\r\n\t\t\t\t\t\t\t\t\t\tto prevent static checking errors. */\r\n\t\t\t\t\t\t\t\t\t\tcStatus = 0x00;\r\n\t\t\t\t\t\t\t\t\t\tbreak;\r\n\t\t\t\t}\r\n\r\n\t\t\t\t/* Write the task name to the string, padding with spaces so it\r\n\t\t\t\tcan be printed in tabular form more easily. */\r\n\t\t\t\tpcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );\r\n\r\n\t\t\t\t/* Write the rest of the string. */\r\n\t\t\t\tsprintf( pcWriteBuffer, \"\\t%c\\t%u\\t%u\\t%u\\r\\n\", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber );\r\n\t\t\t\tpcWriteBuffer += strlen( pcWriteBuffer );\r\n\t\t\t}\r\n\r\n\t\t\t/* Free the array again. */\r\n\t\t\tvPortFree( pxTaskStatusArray );\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t}\r\n\t}\r\n\r\n#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */\r\n/*----------------------------------------------------------*/\r\n\r\n#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )\r\n\r\n\tvoid vTaskGetRunTimeStats( char *pcWriteBuffer )\r\n\t{\r\n\tTaskStatus_t *pxTaskStatusArray;\r\n\tvolatile UBaseType_t uxArraySize, x;\r\n\tuint32_t ulTotalTime, ulStatsAsPercentage;\r\n\r\n\t\t#if( configUSE_TRACE_FACILITY != 1 )\r\n\t\t{\r\n\t\t\t#error configUSE_TRACE_FACILITY must also be set to 1 in FreeRTOSConfig.h to use vTaskGetRunTimeStats().\r\n\t\t}\r\n\t\t#endif\r\n\r\n\t\t/*\r\n\t\t * PLEASE NOTE:\r\n\t\t *\r\n\t\t * This function is provided for convenience only, and is used by many\r\n\t\t * of the demo applications.  Do not consider it to be part of the\r\n\t\t * scheduler.\r\n\t\t *\r\n\t\t * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part\r\n\t\t * of the uxTaskGetSystemState() output into a human readable table that\r\n\t\t * displays the amount of time each task has spent in the Running state\r\n\t\t * in both absolute and percentage terms.\r\n\t\t *\r\n\t\t * vTaskGetRunTimeStats() has a dependency on the sprintf() C library\r\n\t\t * function that might bloat the code size, use a lot of stack, and\r\n\t\t * provide different results on different platforms.  An alternative,\r\n\t\t * tiny, third party, and limited functionality implementation of\r\n\t\t * sprintf() is provided in many of the FreeRTOS/Demo sub-directories in\r\n\t\t * a file called printf-stdarg.c (note printf-stdarg.c does not provide\r\n\t\t * a full snprintf() implementation!).\r\n\t\t *\r\n\t\t * It is recommended that production systems call uxTaskGetSystemState()\r\n\t\t * directly to get access to raw stats data, rather than indirectly\r\n\t\t * through a call to vTaskGetRunTimeStats().\r\n\t\t */\r\n\r\n\t\t/* Make sure the write buffer does not contain a string. */\r\n\t\t*pcWriteBuffer = 0x00;\r\n\r\n\t\t/* Take a snapshot of the number of tasks in case it changes while this\r\n\t\tfunction is executing. */\r\n\t\tuxArraySize = uxCurrentNumberOfTasks;\r\n\r\n\t\t/* Allocate an array index for each task. */\r\n\t\tpxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) );\r\n\r\n\t\tif( pxTaskStatusArray != NULL )\r\n\t\t{\r\n\t\t\t/* Generate the (binary) data. */\r\n\t\t\tuxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalTime );\r\n\r\n\t\t\t/* For percentage calculations. */\r\n\t\t\tulTotalTime /= 100UL;\r\n\r\n\t\t\t/* Avoid divide by zero errors. */\r\n\t\t\tif( ulTotalTime > 0 )\r\n\t\t\t{\r\n\t\t\t\t/* Create a human readable table from the binary data. */\r\n\t\t\t\tfor( x = 0; x < uxArraySize; x++ )\r\n\t\t\t\t{\r\n\t\t\t\t\t/* What percentage of the total run time has the task used?\r\n\t\t\t\t\tThis will always be rounded down to the nearest integer.\r\n\t\t\t\t\tulTotalRunTimeDiv100 has already been divided by 100. */\r\n\t\t\t\t\tulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalTime;\r\n\r\n\t\t\t\t\t/* Write the task name to the string, padding with\r\n\t\t\t\t\tspaces so it can be printed in tabular form more\r\n\t\t\t\t\teasily. */\r\n\t\t\t\t\tpcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );\r\n\r\n\t\t\t\t\tif( ulStatsAsPercentage > 0UL )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t#ifdef portLU_PRINTF_SPECIFIER_REQUIRED\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\tsprintf( pcWriteBuffer, \"\\t%lu\\t\\t%lu%%\\r\\n\", pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\t#else\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t/* sizeof( int ) == sizeof( long ) so a smaller\r\n\t\t\t\t\t\t\tprintf() library can be used. */\r\n\t\t\t\t\t\t\tsprintf( pcWriteBuffer, \"\\t%u\\t\\t%u%%\\r\\n\", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage );\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\t#endif\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t/* If the percentage is zero here then the task has\r\n\t\t\t\t\t\tconsumed less than 1% of the total run time. */\r\n\t\t\t\t\t\t#ifdef portLU_PRINTF_SPECIFIER_REQUIRED\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\tsprintf( pcWriteBuffer, \"\\t%lu\\t\\t<1%%\\r\\n\", pxTaskStatusArray[ x ].ulRunTimeCounter );\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\t#else\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t/* sizeof( int ) == sizeof( long ) so a smaller\r\n\t\t\t\t\t\t\tprintf() library can be used. */\r\n\t\t\t\t\t\t\tsprintf( pcWriteBuffer, \"\\t%u\\t\\t<1%%\\r\\n\", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter );\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\t#endif\r\n\t\t\t\t\t}\r\n\r\n\t\t\t\t\tpcWriteBuffer += strlen( pcWriteBuffer );\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\r\n\t\t\t/* Free the array again. */\r\n\t\t\tvPortFree( pxTaskStatusArray );\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t}\r\n\t}\r\n\r\n#endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */\r\n/*-----------------------------------------------------------*/\r\n\r\nTickType_t uxTaskResetEventItemValue( void )\r\n{\r\nTickType_t uxReturn;\r\n\r\n\tuxReturn = listGET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ) );\r\n\r\n\t/* Reset the event list item to its normal value - so it can be used with\r\n\tqueues and semaphores. */\r\n\tlistSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\r\n\r\n\treturn uxReturn;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( configUSE_MUTEXES == 1 )\r\n\r\n\tvoid *pvTaskIncrementMutexHeldCount( void )\r\n\t{\r\n\t\t/* If xSemaphoreCreateMutex() is called before any tasks have been created\r\n\t\tthen pxCurrentTCB will be NULL. */\r\n\t\tif( pxCurrentTCB != NULL )\r\n\t\t{\r\n\t\t\t( pxCurrentTCB->uxMutexesHeld )++;\r\n\t\t}\r\n\r\n\t\treturn pxCurrentTCB;\r\n\t}\r\n\r\n#endif /* configUSE_MUTEXES */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if( configUSE_TASK_NOTIFICATIONS == 1 )\r\n\r\n\tuint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait )\r\n\t{\r\n\tTickType_t xTimeToWake;\r\n\tuint32_t ulReturn;\r\n\r\n\t\ttaskENTER_CRITICAL();\r\n\t\t{\r\n\t\t\t/* Only block if the notification count is not already non-zero. */\r\n\t\t\tif( pxCurrentTCB->ulNotifiedValue == 0UL )\r\n\t\t\t{\r\n\t\t\t\t/* Mark this task as waiting for a notification. */\r\n\t\t\t\tpxCurrentTCB->eNotifyState = eWaitingNotification;\r\n\r\n\t\t\t\tif( xTicksToWait > ( TickType_t ) 0 )\r\n\t\t\t\t{\r\n\t\t\t\t\t/* The task is going to block.  First it must be removed\r\n\t\t\t\t\tfrom the ready list. */\r\n\t\t\t\t\tif( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t/* The current task must be in a ready list, so there is\r\n\t\t\t\t\t\tno need to check, and the port reset macro can be called\r\n\t\t\t\t\t\tdirectly. */\r\n\t\t\t\t\t\tportRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t}\r\n\r\n\t\t\t\t\t#if ( INCLUDE_vTaskSuspend == 1 )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tif( xTicksToWait == portMAX_DELAY )\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t/* Add the task to the suspended task list instead\r\n\t\t\t\t\t\t\tof a delayed task list to ensure the task is not\r\n\t\t\t\t\t\t\twoken by a timing event.  It will block\r\n\t\t\t\t\t\t\tindefinitely. */\r\n\t\t\t\t\t\t\tvListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xGenericListItem ) );\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\telse\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t/* Calculate the time at which the task should be\r\n\t\t\t\t\t\t\twoken if no notification events occur.  This may\r\n\t\t\t\t\t\t\toverflow but this doesn't matter, the scheduler will\r\n\t\t\t\t\t\t\thandle it. */\r\n\t\t\t\t\t\t\txTimeToWake = xTickCount + xTicksToWait;\r\n\t\t\t\t\t\t\tprvAddCurrentTaskToDelayedList( xTimeToWake );\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t}\r\n\t\t\t\t\t#else /* INCLUDE_vTaskSuspend */\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t\t/* Calculate the time at which the task should be\r\n\t\t\t\t\t\t\twoken if the event does not occur.  This may\r\n\t\t\t\t\t\t\toverflow but this doesn't matter, the scheduler will\r\n\t\t\t\t\t\t\thandle it. */\r\n\t\t\t\t\t\t\txTimeToWake = xTickCount + xTicksToWait;\r\n\t\t\t\t\t\t\tprvAddCurrentTaskToDelayedList( xTimeToWake );\r\n\t\t\t\t\t}\r\n\t\t\t\t\t#endif /* INCLUDE_vTaskSuspend */\r\n\r\n\t\t\t\t\t/* All ports are written to allow a yield in a critical\r\n\t\t\t\t\tsection (some will yield immediately, others wait until the\r\n\t\t\t\t\tcritical section exits) - but it is not something that\r\n\t\t\t\t\tapplication code should ever do. */\r\n\t\t\t\t\tportYIELD_WITHIN_API();\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\t\t}\r\n\t\ttaskEXIT_CRITICAL();\r\n\r\n\t\ttaskENTER_CRITICAL();\r\n\t\t{\r\n\t\t\tulReturn = pxCurrentTCB->ulNotifiedValue;\r\n\r\n\t\t\tif( ulReturn != 0UL )\r\n\t\t\t{\r\n\t\t\t\tif( xClearCountOnExit != pdFALSE )\r\n\t\t\t\t{\r\n\t\t\t\t\tpxCurrentTCB->ulNotifiedValue = 0UL;\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\t( pxCurrentTCB->ulNotifiedValue )--;\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\r\n\t\t\tpxCurrentTCB->eNotifyState = eNotWaitingNotification;\r\n\t\t}\r\n\t\ttaskEXIT_CRITICAL();\r\n\r\n\t\treturn ulReturn;\r\n\t}\r\n\r\n#endif /* configUSE_TASK_NOTIFICATIONS */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if( configUSE_TASK_NOTIFICATIONS == 1 )\r\n\r\n\tBaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait )\r\n\t{\r\n\tTickType_t xTimeToWake;\r\n\tBaseType_t xReturn;\r\n\r\n\t\ttaskENTER_CRITICAL();\r\n\t\t{\r\n\t\t\t/* Only block if a notification is not already pending. */\r\n\t\t\tif( pxCurrentTCB->eNotifyState != eNotified )\r\n\t\t\t{\r\n\t\t\t\t/* Clear bits in the task's notification value as bits may get\r\n\t\t\t\tset\tby the notifying task or interrupt.  This can be used to\r\n\t\t\t\tclear the value to zero. */\r\n\t\t\t\tpxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry;\r\n\r\n\t\t\t\t/* Mark this task as waiting for a notification. */\r\n\t\t\t\tpxCurrentTCB->eNotifyState = eWaitingNotification;\r\n\r\n\t\t\t\tif( xTicksToWait > ( TickType_t ) 0 )\r\n\t\t\t\t{\r\n\t\t\t\t\t/* The task is going to block.  First it must be removed\r\n\t\t\t\t\tfrom the\tready list. */\r\n\t\t\t\t\tif( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t/* The current task must be in a ready list, so there is\r\n\t\t\t\t\t\tno need to check, and the port reset macro can be called\r\n\t\t\t\t\t\tdirectly. */\r\n\t\t\t\t\t\tportRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t}\r\n\r\n\t\t\t\t\t#if ( INCLUDE_vTaskSuspend == 1 )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tif( xTicksToWait == portMAX_DELAY )\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t/* Add the task to the suspended task list instead\r\n\t\t\t\t\t\t\tof a delayed task list to ensure the task is not\r\n\t\t\t\t\t\t\twoken by a timing event.  It will block\r\n\t\t\t\t\t\t\tindefinitely. */\r\n\t\t\t\t\t\t\tvListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xGenericListItem ) );\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\telse\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\t/* Calculate the time at which the task should be\r\n\t\t\t\t\t\t\twoken if no notification events occur.  This may\r\n\t\t\t\t\t\t\toverflow but this doesn't matter, the scheduler will\r\n\t\t\t\t\t\t\thandle it. */\r\n\t\t\t\t\t\t\txTimeToWake = xTickCount + xTicksToWait;\r\n\t\t\t\t\t\t\tprvAddCurrentTaskToDelayedList( xTimeToWake );\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t}\r\n\t\t\t\t\t#else /* INCLUDE_vTaskSuspend */\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t\t/* Calculate the time at which the task should be\r\n\t\t\t\t\t\t\twoken if the event does not occur.  This may\r\n\t\t\t\t\t\t\toverflow but this doesn't matter, the scheduler will\r\n\t\t\t\t\t\t\thandle it. */\r\n\t\t\t\t\t\t\txTimeToWake = xTickCount + xTicksToWait;\r\n\t\t\t\t\t\t\tprvAddCurrentTaskToDelayedList( xTimeToWake );\r\n\t\t\t\t\t}\r\n\t\t\t\t\t#endif /* INCLUDE_vTaskSuspend */\r\n\r\n\t\t\t\t\t/* All ports are written to allow a yield in a critical\r\n\t\t\t\t\tsection (some will yield immediately, others wait until the\r\n\t\t\t\t\tcritical section exits) - but it is not something that\r\n\t\t\t\t\tapplication code should ever do. */\r\n\t\t\t\t\tportYIELD_WITHIN_API();\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\t\t}\r\n\t\ttaskEXIT_CRITICAL();\r\n\r\n\t\ttaskENTER_CRITICAL();\r\n\t\t{\r\n\t\t\tif( pulNotificationValue != NULL )\r\n\t\t\t{\r\n\t\t\t\t/* Output the current notification value, which may or may not\r\n\t\t\t\thave changed. */\r\n\t\t\t\t*pulNotificationValue = pxCurrentTCB->ulNotifiedValue;\r\n\t\t\t}\r\n\r\n\t\t\t/* If eNotifyValue is set then either the task never entered the\r\n\t\t\tblocked state (because a notification was already pending) or the\r\n\t\t\ttask unblocked because of a notification.  Otherwise the task\r\n\t\t\tunblocked because of a timeout. */\r\n\t\t\tif( pxCurrentTCB->eNotifyState == eWaitingNotification )\r\n\t\t\t{\r\n\t\t\t\t/* A notification was not received. */\r\n\t\t\t\txReturn = pdFALSE;\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\t/* A notification was already pending or a notification was\r\n\t\t\t\treceived while the task was waiting. */\r\n\t\t\t\tpxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit;\r\n\t\t\t\txReturn = pdTRUE;\r\n\t\t\t}\r\n\r\n\t\t\tpxCurrentTCB->eNotifyState = eNotWaitingNotification;\r\n\t\t}\r\n\t\ttaskEXIT_CRITICAL();\r\n\r\n\t\treturn xReturn;\r\n\t}\r\n\r\n#endif /* configUSE_TASK_NOTIFICATIONS */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if( configUSE_TASK_NOTIFICATIONS == 1 )\r\n\r\n\tBaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue )\r\n\t{\r\n\tTCB_t * pxTCB;\r\n\teNotifyValue eOriginalNotifyState;\r\n\tBaseType_t xReturn = pdPASS;\r\n\r\n\t\tconfigASSERT( xTaskToNotify );\r\n\t\tpxTCB = ( TCB_t * ) xTaskToNotify;\r\n\r\n\t\ttaskENTER_CRITICAL();\r\n\t\t{\r\n\t\t\tif( pulPreviousNotificationValue != NULL )\r\n\t\t\t{\r\n\t\t\t\t*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;\r\n\t\t\t}\r\n\r\n\t\t\teOriginalNotifyState = pxTCB->eNotifyState;\r\n\r\n\t\t\tpxTCB->eNotifyState = eNotified;\r\n\r\n\t\t\tswitch( eAction )\r\n\t\t\t{\r\n\t\t\t\tcase eSetBits\t:\r\n\t\t\t\t\tpxTCB->ulNotifiedValue |= ulValue;\r\n\t\t\t\t\tbreak;\r\n\r\n\t\t\t\tcase eIncrement\t:\r\n\t\t\t\t\t( pxTCB->ulNotifiedValue )++;\r\n\t\t\t\t\tbreak;\r\n\r\n\t\t\t\tcase eSetValueWithOverwrite\t:\r\n\t\t\t\t\tpxTCB->ulNotifiedValue = ulValue;\r\n\t\t\t\t\tbreak;\r\n\r\n\t\t\t\tcase eSetValueWithoutOverwrite :\r\n\t\t\t\t\tif( eOriginalNotifyState != eNotified )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tpxTCB->ulNotifiedValue = ulValue;\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t/* The value could not be written to the task. */\r\n\t\t\t\t\t\txReturn = pdFAIL;\r\n\t\t\t\t\t}\r\n\t\t\t\t\tbreak;\r\n\r\n\t\t\t\tcase eNoAction:\r\n\t\t\t\t\t/* The task is being notified without its notify value being\r\n\t\t\t\t\tupdated. */\r\n\t\t\t\t\tbreak;\r\n\t\t\t}\r\n\r\n\r\n\t\t\t/* If the task is in the blocked state specifically to wait for a\r\n\t\t\tnotification then unblock it now. */\r\n\t\t\tif( eOriginalNotifyState == eWaitingNotification )\r\n\t\t\t{\r\n\t\t\t\t( void ) uxListRemove( &( pxTCB->xGenericListItem ) );\r\n\t\t\t\tprvAddTaskToReadyList( pxTCB );\r\n\r\n\t\t\t\t/* The task should not have been on an event list. */\r\n\t\t\t\tconfigASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );\r\n\r\n\t\t\t\tif( pxTCB->uxPriority > pxCurrentTCB->uxPriority )\r\n\t\t\t\t{\r\n\t\t\t\t\t/* The notified task has a priority above the currently\r\n\t\t\t\t\texecuting task so a yield is required. */\r\n\t\t\t\t\ttaskYIELD_IF_USING_PREEMPTION();\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\t\t}\r\n\t\ttaskEXIT_CRITICAL();\r\n\r\n\t\treturn xReturn;\r\n\t}\r\n\r\n#endif /* configUSE_TASK_NOTIFICATIONS */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if( configUSE_TASK_NOTIFICATIONS == 1 )\r\n\r\n\tBaseType_t xTaskNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken )\r\n\t{\r\n\tTCB_t * pxTCB;\r\n\teNotifyValue eOriginalNotifyState;\r\n\tBaseType_t xReturn = pdPASS;\r\n\tUBaseType_t uxSavedInterruptStatus;\r\n\r\n\t\tconfigASSERT( xTaskToNotify );\r\n\r\n\t\t/* RTOS ports that support interrupt nesting have the concept of a\r\n\t\tmaximum\tsystem call (or maximum API call) interrupt priority.\r\n\t\tInterrupts that are\tabove the maximum system call priority are keep\r\n\t\tpermanently enabled, even when the RTOS kernel is in a critical section,\r\n\t\tbut cannot make any calls to FreeRTOS API functions.  If configASSERT()\r\n\t\tis defined in FreeRTOSConfig.h then\r\n\t\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\r\n\t\tfailure if a FreeRTOS API function is called from an interrupt that has\r\n\t\tbeen assigned a priority above the configured maximum system call\r\n\t\tpriority.  Only FreeRTOS functions that end in FromISR can be called\r\n\t\tfrom interrupts\tthat have been assigned a priority at or (logically)\r\n\t\tbelow the maximum system call interrupt priority.  FreeRTOS maintains a\r\n\t\tseparate interrupt safe API to ensure interrupt entry is as fast and as\r\n\t\tsimple as possible.  More information (albeit Cortex-M specific) is\r\n\t\tprovided on the following link:\r\n\t\thttp://www.freertos.org/RTOS-Cortex-M3-M4.html */\r\n\t\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID();\r\n\r\n\t\tpxTCB = ( TCB_t * ) xTaskToNotify;\r\n\r\n\t\tuxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\r\n\t\t{\r\n\t\t\teOriginalNotifyState = pxTCB->eNotifyState;\r\n\r\n\t\t\tpxTCB->eNotifyState = eNotified;\r\n\r\n\t\t\tswitch( eAction )\r\n\t\t\t{\r\n\t\t\t\tcase eSetBits\t:\r\n\t\t\t\t\tpxTCB->ulNotifiedValue |= ulValue;\r\n\t\t\t\t\tbreak;\r\n\r\n\t\t\t\tcase eIncrement\t:\r\n\t\t\t\t\t( pxTCB->ulNotifiedValue )++;\r\n\t\t\t\t\tbreak;\r\n\r\n\t\t\t\tcase eSetValueWithOverwrite\t:\r\n\t\t\t\t\tpxTCB->ulNotifiedValue = ulValue;\r\n\t\t\t\t\tbreak;\r\n\r\n\t\t\t\tcase eSetValueWithoutOverwrite :\r\n\t\t\t\t\tif( eOriginalNotifyState != eNotified )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tpxTCB->ulNotifiedValue = ulValue;\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t/* The value could not be written to the task. */\r\n\t\t\t\t\t\txReturn = pdFAIL;\r\n\t\t\t\t\t}\r\n\t\t\t\t\tbreak;\r\n\r\n\t\t\t\tcase eNoAction :\r\n\t\t\t\t\t/* The task is being notified without its notify value being\r\n\t\t\t\t\tupdated. */\r\n\t\t\t\t\tbreak;\r\n\t\t\t}\r\n\r\n\r\n\t\t\t/* If the task is in the blocked state specifically to wait for a\r\n\t\t\tnotification then unblock it now. */\r\n\t\t\tif( eOriginalNotifyState == eWaitingNotification )\r\n\t\t\t{\r\n\t\t\t\t/* The task should not have been on an event list. */\r\n\t\t\t\tconfigASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );\r\n\r\n\t\t\t\tif( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\r\n\t\t\t\t{\r\n\t\t\t\t\t( void ) uxListRemove( &( pxTCB->xGenericListItem ) );\r\n\t\t\t\t\tprvAddTaskToReadyList( pxTCB );\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\t/* The delayed and ready lists cannot be accessed, so hold\r\n\t\t\t\t\tthis task pending until the scheduler is resumed. */\r\n\t\t\t\t\tvListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );\r\n\t\t\t\t}\r\n\r\n\t\t\t\tif( pxTCB->uxPriority > pxCurrentTCB->uxPriority )\r\n\t\t\t\t{\r\n\t\t\t\t\t/* The notified task has a priority above the currently\r\n\t\t\t\t\texecuting task so a yield is required. */\r\n\t\t\t\t\tif( pxHigherPriorityTaskWoken != NULL )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t*pxHigherPriorityTaskWoken = pdTRUE;\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t}\r\n\t\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\r\n\r\n\t\treturn xReturn;\r\n\t}\r\n\r\n#endif /* configUSE_TASK_NOTIFICATIONS */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if( configUSE_TASK_NOTIFICATIONS == 1 )\r\n\r\n\tvoid vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken )\r\n\t{\r\n\tTCB_t * pxTCB;\r\n\teNotifyValue eOriginalNotifyState;\r\n\tUBaseType_t uxSavedInterruptStatus;\r\n\r\n\t\tconfigASSERT( xTaskToNotify );\r\n\r\n\t\t/* RTOS ports that support interrupt nesting have the concept of a\r\n\t\tmaximum\tsystem call (or maximum API call) interrupt priority.\r\n\t\tInterrupts that are\tabove the maximum system call priority are keep\r\n\t\tpermanently enabled, even when the RTOS kernel is in a critical section,\r\n\t\tbut cannot make any calls to FreeRTOS API functions.  If configASSERT()\r\n\t\tis defined in FreeRTOSConfig.h then\r\n\t\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\r\n\t\tfailure if a FreeRTOS API function is called from an interrupt that has\r\n\t\tbeen assigned a priority above the configured maximum system call\r\n\t\tpriority.  Only FreeRTOS functions that end in FromISR can be called\r\n\t\tfrom interrupts\tthat have been assigned a priority at or (logically)\r\n\t\tbelow the maximum system call interrupt priority.  FreeRTOS maintains a\r\n\t\tseparate interrupt safe API to ensure interrupt entry is as fast and as\r\n\t\tsimple as possible.  More information (albeit Cortex-M specific) is\r\n\t\tprovided on the following link:\r\n\t\thttp://www.freertos.org/RTOS-Cortex-M3-M4.html */\r\n\t\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID();\r\n\r\n\t\tpxTCB = ( TCB_t * ) xTaskToNotify;\r\n\r\n\t\tuxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\r\n\t\t{\r\n\t\t\teOriginalNotifyState = pxTCB->eNotifyState;\r\n\t\t\tpxTCB->eNotifyState = eNotified;\r\n\r\n\t\t\t/* 'Giving' is equivalent to incrementing a count in a counting\r\n\t\t\tsemaphore. */\r\n\t\t\t( pxTCB->ulNotifiedValue )++;\r\n\r\n\t\t\t/* If the task is in the blocked state specifically to wait for a\r\n\t\t\tnotification then unblock it now. */\r\n\t\t\tif( eOriginalNotifyState == eWaitingNotification )\r\n\t\t\t{\r\n\t\t\t\t/* The task should not have been on an event list. */\r\n\t\t\t\tconfigASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );\r\n\r\n\t\t\t\tif( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\r\n\t\t\t\t{\r\n\t\t\t\t\t( void ) uxListRemove( &( pxTCB->xGenericListItem ) );\r\n\t\t\t\t\tprvAddTaskToReadyList( pxTCB );\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\t/* The delayed and ready lists cannot be accessed, so hold\r\n\t\t\t\t\tthis task pending until the scheduler is resumed. */\r\n\t\t\t\t\tvListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );\r\n\t\t\t\t}\r\n\r\n\t\t\t\tif( pxTCB->uxPriority > pxCurrentTCB->uxPriority )\r\n\t\t\t\t{\r\n\t\t\t\t\t/* The notified task has a priority above the currently\r\n\t\t\t\t\texecuting task so a yield is required. */\r\n\t\t\t\t\tif( pxHigherPriorityTaskWoken != NULL )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t*pxHigherPriorityTaskWoken = pdTRUE;\r\n\t\t\t\t\t}\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t}\r\n\t\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\r\n\t}\r\n\r\n#endif /* configUSE_TASK_NOTIFICATIONS */\r\n\r\n/*-----------------------------------------------------------*/\r\n\r\n\r\n#ifdef FREERTOS_MODULE_TEST\r\n\t#include \"tasks_test_access_functions.h\"\r\n#endif\r\n\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RTOS/src/timers.c",
    "content": "/*\r\n    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r\n    All rights reserved\r\n\r\n    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r\n\r\n    This file is part of the FreeRTOS distribution.\r\n\r\n    FreeRTOS is free software; you can redistribute it and/or modify it under\r\n    the terms of the GNU General Public License (version 2) as published by the\r\n    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r\n\r\n    ***************************************************************************\r\n    >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r\n    >>!   distribute a combined work that includes FreeRTOS without being   !<<\r\n    >>!   obliged to provide the source code for proprietary components     !<<\r\n    >>!   outside of the FreeRTOS kernel.                                   !<<\r\n    ***************************************************************************\r\n\r\n    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r\n    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r\n    FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r\n    link: http://www.freertos.org/a00114.html\r\n\r\n    ***************************************************************************\r\n     *                                                                       *\r\n     *    FreeRTOS provides completely free yet professionally developed,    *\r\n     *    robust, strictly quality controlled, supported, and cross          *\r\n     *    platform software that is more than just the market leader, it     *\r\n     *    is the industry's de facto standard.                               *\r\n     *                                                                       *\r\n     *    Help yourself get started quickly while simultaneously helping     *\r\n     *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r\n     *    tutorial book, reference manual, or both:                          *\r\n     *    http://www.FreeRTOS.org/Documentation                              *\r\n     *                                                                       *\r\n    ***************************************************************************\r\n\r\n    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r\n    the FAQ page \"My application does not run, what could be wrong?\".  Have you\r\n    defined configASSERT()?\r\n\r\n    http://www.FreeRTOS.org/support - In return for receiving this top quality\r\n    embedded software for free we request you assist our global community by\r\n    participating in the support forum.\r\n\r\n    http://www.FreeRTOS.org/training - Investing in training allows your team to\r\n    be as productive as possible as early as possible.  Now you can receive\r\n    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r\n    Ltd, and the world's leading authority on the world's leading RTOS.\r\n\r\n    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r\n    including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r\n    compatible FAT file system, and our tiny thread aware UDP/IP stack.\r\n\r\n    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r\n    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r\n\r\n    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r\n    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r\n    licenses offer ticketed support, indemnification and commercial middleware.\r\n\r\n    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r\n    engineered and independently SIL3 certified version for use in safety and\r\n    mission critical applications that require provable dependability.\r\n\r\n    1 tab == 4 spaces!\r\n*/\r\n\r\n/* Standard includes. */\r\n#include <stdlib.h>\r\n\r\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r\nall the API functions to use the MPU wrappers.  That should only be done when\r\ntask.h is included from an application file. */\r\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r\n\r\n#include \"FreeRTOS.h\"\r\n#include \"task.h\"\r\n#include \"queue.h\"\r\n#include \"timers.h\"\r\n\r\n#if ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 0 )\r\n\t#error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available.\r\n#endif\r\n\r\n/* Lint e961 and e750 are suppressed as a MISRA exception justified because the\r\nMPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the\r\nheader files above, but not in this file, in order to generate the correct\r\nprivileged Vs unprivileged linkage and placement. */\r\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */\r\n\r\n\r\n/* This entire source file will be skipped if the application is not configured\r\nto include software timer functionality.  This #if is closed at the very bottom\r\nof this file.  If you want to include software timer functionality then ensure\r\nconfigUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */\r\n#if ( configUSE_TIMERS == 1 )\r\n\r\n/* Misc definitions. */\r\n#define tmrNO_DELAY\t\t( TickType_t ) 0U\r\n\r\n/* The definition of the timers themselves. */\r\ntypedef struct tmrTimerControl\r\n{\r\n\tconst char\t\t\t\t*pcTimerName;\t\t/*<< Text name.  This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\r\n\tListItem_t\t\t\t\txTimerListItem;\t\t/*<< Standard linked list item as used by all kernel features for event management. */\r\n\tTickType_t\t\t\t\txTimerPeriodInTicks;/*<< How quickly and often the timer expires. */\r\n\tUBaseType_t\t\t\t\tuxAutoReload;\t\t/*<< Set to pdTRUE if the timer should be automatically restarted once expired.  Set to pdFALSE if the timer is, in effect, a one-shot timer. */\r\n\tvoid \t\t\t\t\t*pvTimerID;\t\t\t/*<< An ID to identify the timer.  This allows the timer to be identified when the same callback is used for multiple timers. */\r\n\tTimerCallbackFunction_t\tpxCallbackFunction;\t/*<< The function that will be called when the timer expires. */\r\n\t#if( configUSE_TRACE_FACILITY == 1 )\r\n\t\tUBaseType_t\t\t\tuxTimerNumber;\t\t/*<< An ID assigned by trace tools such as FreeRTOS+Trace */\r\n\t#endif\r\n} xTIMER;\r\n\r\n/* The old xTIMER name is maintained above then typedefed to the new Timer_t\r\nname below to enable the use of older kernel aware debuggers. */\r\ntypedef xTIMER Timer_t;\r\n\r\n/* The definition of messages that can be sent and received on the timer queue.\r\nTwo types of message can be queued - messages that manipulate a software timer,\r\nand messages that request the execution of a non-timer related callback.  The\r\ntwo message types are defined in two separate structures, xTimerParametersType\r\nand xCallbackParametersType respectively. */\r\ntypedef struct tmrTimerParameters\r\n{\r\n\tTickType_t\t\t\txMessageValue;\t\t/*<< An optional value used by a subset of commands, for example, when changing the period of a timer. */\r\n\tTimer_t *\t\t\tpxTimer;\t\t\t/*<< The timer to which the command will be applied. */\r\n} TimerParameter_t;\r\n\r\n\r\ntypedef struct tmrCallbackParameters\r\n{\r\n\tPendedFunction_t\tpxCallbackFunction;\t/* << The callback function to execute. */\r\n\tvoid *pvParameter1;\t\t\t\t\t\t/* << The value that will be used as the callback functions first parameter. */\r\n\tuint32_t ulParameter2;\t\t\t\t\t/* << The value that will be used as the callback functions second parameter. */\r\n} CallbackParameters_t;\r\n\r\n/* The structure that contains the two message types, along with an identifier\r\nthat is used to determine which message type is valid. */\r\ntypedef struct tmrTimerQueueMessage\r\n{\r\n\tBaseType_t\t\t\txMessageID;\t\t\t/*<< The command being sent to the timer service task. */\r\n\tunion\r\n\t{\r\n\t\tTimerParameter_t xTimerParameters;\r\n\r\n\t\t/* Don't include xCallbackParameters if it is not going to be used as\r\n\t\tit makes the structure (and therefore the timer queue) larger. */\r\n\t\t#if ( INCLUDE_xTimerPendFunctionCall == 1 )\r\n\t\t\tCallbackParameters_t xCallbackParameters;\r\n\t\t#endif /* INCLUDE_xTimerPendFunctionCall */\r\n\t} u;\r\n} DaemonTaskMessage_t;\r\n\r\n/*lint -e956 A manual analysis and inspection has been used to determine which\r\nstatic variables must be declared volatile. */\r\n\r\n/* The list in which active timers are stored.  Timers are referenced in expire\r\ntime order, with the nearest expiry time at the front of the list.  Only the\r\ntimer service task is allowed to access these lists. */\r\nPRIVILEGED_DATA static List_t xActiveTimerList1;\r\nPRIVILEGED_DATA static List_t xActiveTimerList2;\r\nPRIVILEGED_DATA static List_t *pxCurrentTimerList;\r\nPRIVILEGED_DATA static List_t *pxOverflowTimerList;\r\n\r\n/* A queue that is used to send commands to the timer service task. */\r\nPRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL;\r\n\r\n#if ( INCLUDE_xTimerGetTimerDaemonTaskHandle == 1 )\r\n\r\n\tPRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL;\r\n\r\n#endif\r\n\r\n/*lint +e956 */\r\n\r\n/*-----------------------------------------------------------*/\r\n\r\n/*\r\n * Initialise the infrastructure used by the timer service task if it has not\r\n * been initialised already.\r\n */\r\nstatic void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * The timer service task (daemon).  Timer functionality is controlled by this\r\n * task.  Other tasks communicate with the timer service task using the\r\n * xTimerQueue queue.\r\n */\r\nstatic void prvTimerTask( void *pvParameters ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * Called by the timer service task to interpret and process a command it\r\n * received on the timer queue.\r\n */\r\nstatic void\tprvProcessReceivedCommands( void ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * Insert the timer into either xActiveTimerList1, or xActiveTimerList2,\r\n * depending on if the expire time causes a timer counter overflow.\r\n */\r\nstatic BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * An active timer has reached its expire time.  Reload the timer if it is an\r\n * auto reload timer, then call its callback.\r\n */\r\nstatic void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * The tick count has overflowed.  Switch the timer lists after ensuring the\r\n * current timer list does not still reference some timers.\r\n */\r\nstatic void prvSwitchTimerLists( void ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * Obtain the current tick count, setting *pxTimerListsWereSwitched to pdTRUE\r\n * if a tick count overflow occurred since prvSampleTimeNow() was last called.\r\n */\r\nstatic TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * If the timer list contains any active timers then return the expire time of\r\n * the timer that will expire first and set *pxListWasEmpty to false.  If the\r\n * timer list does not contain any timers then return 0 and set *pxListWasEmpty\r\n * to pdTRUE.\r\n */\r\nstatic TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) PRIVILEGED_FUNCTION;\r\n\r\n/*\r\n * If a timer has expired, process it.  Otherwise, block the timer service task\r\n * until either a timer does expire or a command is received.\r\n */\r\nstatic void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, const BaseType_t xListWasEmpty ) PRIVILEGED_FUNCTION;\r\n\r\n/*-----------------------------------------------------------*/\r\n\r\nBaseType_t xTimerCreateTimerTask( void )\r\n{\r\nBaseType_t xReturn = pdFAIL;\r\n\r\n\t/* This function is called when the scheduler is started if\r\n\tconfigUSE_TIMERS is set to 1.  Check that the infrastructure used by the\r\n\ttimer service task has been created/initialised.  If timers have already\r\n\tbeen created then the initialisation will already have been performed. */\r\n\tprvCheckForValidListAndQueue();\r\n\r\n\tif( xTimerQueue != NULL )\r\n\t{\r\n\t\t#if ( INCLUDE_xTimerGetTimerDaemonTaskHandle == 1 )\r\n\t\t{\r\n\t\t\t/* Create the timer task, storing its handle in xTimerTaskHandle so\r\n\t\t\tit can be returned by the xTimerGetTimerDaemonTaskHandle() function. */\r\n\t\t\txReturn = xTaskCreate( prvTimerTask, \"Tmr Svc\", ( uint16_t ) configTIMER_TASK_STACK_DEPTH, NULL, ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, &xTimerTaskHandle );\r\n\t\t}\r\n\t\t#else\r\n\t\t{\r\n\t\t\t/* Create the timer task without storing its handle. */\r\n\t\t\txReturn = xTaskCreate( prvTimerTask, \"Tmr Svc\", ( uint16_t ) configTIMER_TASK_STACK_DEPTH, NULL, ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, NULL);\r\n\t\t}\r\n\t\t#endif\r\n\t}\r\n\telse\r\n\t{\r\n\t\tmtCOVERAGE_TEST_MARKER();\r\n\t}\r\n\r\n\tconfigASSERT( xReturn );\r\n\treturn xReturn;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nTimerHandle_t xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\r\n{\r\nTimer_t *pxNewTimer;\r\n\r\n\t/* Allocate the timer structure. */\r\n\tif( xTimerPeriodInTicks == ( TickType_t ) 0U )\r\n\t{\r\n\t\tpxNewTimer = NULL;\r\n\t}\r\n\telse\r\n\t{\r\n\t\tpxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) );\r\n\t\tif( pxNewTimer != NULL )\r\n\t\t{\r\n\t\t\t/* Ensure the infrastructure used by the timer service task has been\r\n\t\t\tcreated/initialised. */\r\n\t\t\tprvCheckForValidListAndQueue();\r\n\r\n\t\t\t/* Initialise the timer structure members using the function parameters. */\r\n\t\t\tpxNewTimer->pcTimerName = pcTimerName;\r\n\t\t\tpxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks;\r\n\t\t\tpxNewTimer->uxAutoReload = uxAutoReload;\r\n\t\t\tpxNewTimer->pvTimerID = pvTimerID;\r\n\t\t\tpxNewTimer->pxCallbackFunction = pxCallbackFunction;\r\n\t\t\tvListInitialiseItem( &( pxNewTimer->xTimerListItem ) );\r\n\r\n\t\t\ttraceTIMER_CREATE( pxNewTimer );\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\ttraceTIMER_CREATE_FAILED();\r\n\t\t}\r\n\t}\r\n\r\n\t/* 0 is not a valid value for xTimerPeriodInTicks. */\r\n\tconfigASSERT( ( xTimerPeriodInTicks > 0 ) );\r\n\r\n\treturn ( TimerHandle_t ) pxNewTimer;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nBaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )\r\n{\r\nBaseType_t xReturn = pdFAIL;\r\nDaemonTaskMessage_t xMessage;\r\n\r\n\t/* Send a message to the timer service task to perform a particular action\r\n\ton a particular timer definition. */\r\n\tif( xTimerQueue != NULL )\r\n\t{\r\n\t\t/* Send a command to the timer service task to start the xTimer timer. */\r\n\t\txMessage.xMessageID = xCommandID;\r\n\t\txMessage.u.xTimerParameters.xMessageValue = xOptionalValue;\r\n\t\txMessage.u.xTimerParameters.pxTimer = ( Timer_t * ) xTimer;\r\n\r\n\t\tif( xCommandID < tmrFIRST_FROM_ISR_COMMAND )\r\n\t\t{\r\n\t\t\tif( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )\r\n\t\t\t{\r\n\t\t\t\txReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\txReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );\r\n\t\t\t}\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\txReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );\r\n\t\t}\r\n\r\n\t\ttraceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn );\r\n\t}\r\n\telse\r\n\t{\r\n\t\tmtCOVERAGE_TEST_MARKER();\r\n\t}\r\n\r\n\treturn xReturn;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\n#if ( INCLUDE_xTimerGetTimerDaemonTaskHandle == 1 )\r\n\r\n\tTaskHandle_t xTimerGetTimerDaemonTaskHandle( void )\r\n\t{\r\n\t\t/* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been\r\n\t\tstarted, then xTimerTaskHandle will be NULL. */\r\n\t\tconfigASSERT( ( xTimerTaskHandle != NULL ) );\r\n\t\treturn xTimerTaskHandle;\r\n\t}\r\n\r\n#endif\r\n/*-----------------------------------------------------------*/\r\n\r\nconst char * pcTimerGetTimerName( TimerHandle_t xTimer )\r\n{\r\nTimer_t *pxTimer = ( Timer_t * ) xTimer;\r\n\r\n\treturn pxTimer->pcTimerName;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nstatic void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )\r\n{\r\nBaseType_t xResult;\r\nTimer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList );\r\n\r\n\t/* Remove the timer from the list of active timers.  A check has already\r\n\tbeen performed to ensure the list is not empty. */\r\n\t( void ) uxListRemove( &( pxTimer->xTimerListItem ) );\r\n\ttraceTIMER_EXPIRED( pxTimer );\r\n\r\n\t/* If the timer is an auto reload timer then calculate the next\r\n\texpiry time and re-insert the timer in the list of active timers. */\r\n\tif( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE )\r\n\t{\r\n\t\t/* The timer is inserted into a list using a time relative to anything\r\n\t\tother than the current time.  It will therefore be inserted into the\r\n\t\tcorrect list relative to the time this task thinks it is now. */\r\n\t\tif( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) == pdTRUE )\r\n\t\t{\r\n\t\t\t/* The timer expired before it was added to the active timer\r\n\t\t\tlist.  Reload it now.  */\r\n\t\t\txResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );\r\n\t\t\tconfigASSERT( xResult );\r\n\t\t\t( void ) xResult;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t}\r\n\t}\r\n\telse\r\n\t{\r\n\t\tmtCOVERAGE_TEST_MARKER();\r\n\t}\r\n\r\n\t/* Call the timer callback. */\r\n\tpxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nstatic void prvTimerTask( void *pvParameters )\r\n{\r\nTickType_t xNextExpireTime;\r\nBaseType_t xListWasEmpty;\r\n\r\n\t/* Just to avoid compiler warnings. */\r\n\t( void ) pvParameters;\r\n\r\n\tfor( ;; )\r\n\t{\r\n\t\t/* Query the timers list to see if it contains any timers, and if so,\r\n\t\tobtain the time at which the next timer will expire. */\r\n\t\txNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );\r\n\r\n\t\t/* If a timer has expired, process it.  Otherwise, block this task\r\n\t\tuntil either a timer does expire, or a command is received. */\r\n\t\tprvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );\r\n\r\n\t\t/* Empty the command queue. */\r\n\t\tprvProcessReceivedCommands();\r\n\t}\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nstatic void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, const BaseType_t xListWasEmpty )\r\n{\r\nTickType_t xTimeNow;\r\nBaseType_t xTimerListsWereSwitched;\r\n\r\n\tvTaskSuspendAll();\r\n\t{\r\n\t\t/* Obtain the time now to make an assessment as to whether the timer\r\n\t\thas expired or not.  If obtaining the time causes the lists to switch\r\n\t\tthen don't process this timer as any timers that remained in the list\r\n\t\twhen the lists were switched will have been processed within the\r\n\t\tprvSampleTimeNow() function. */\r\n\t\txTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );\r\n\t\tif( xTimerListsWereSwitched == pdFALSE )\r\n\t\t{\r\n\t\t\t/* The tick count has not overflowed, has the timer expired? */\r\n\t\t\tif( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )\r\n\t\t\t{\r\n\t\t\t\t( void ) xTaskResumeAll();\r\n\t\t\t\tprvProcessExpiredTimer( xNextExpireTime, xTimeNow );\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\t/* The tick count has not overflowed, and the next expire\r\n\t\t\t\ttime has not been reached yet.  This task should therefore\r\n\t\t\t\tblock to wait for the next expire time or a command to be\r\n\t\t\t\treceived - whichever comes first.  The following line cannot\r\n\t\t\t\tbe reached unless xNextExpireTime > xTimeNow, except in the\r\n\t\t\t\tcase when the current timer list is empty. */\r\n\t\t\t\tvQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ) );\r\n\r\n\t\t\t\tif( xTaskResumeAll() == pdFALSE )\r\n\t\t\t\t{\r\n\t\t\t\t\t/* Yield to wait for either a command to arrive, or the\r\n\t\t\t\t\tblock time to expire.  If a command arrived between the\r\n\t\t\t\t\tcritical section being exited and this yield then the yield\r\n\t\t\t\t\twill not cause the task to block. */\r\n\t\t\t\t\tportYIELD_WITHIN_API();\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\t( void ) xTaskResumeAll();\r\n\t\t}\r\n\t}\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nstatic TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )\r\n{\r\nTickType_t xNextExpireTime;\r\n\r\n\t/* Timers are listed in expiry time order, with the head of the list\r\n\treferencing the task that will expire first.  Obtain the time at which\r\n\tthe timer with the nearest expiry time will expire.  If there are no\r\n\tactive timers then just set the next expire time to 0.  That will cause\r\n\tthis task to unblock when the tick count overflows, at which point the\r\n\ttimer lists will be switched and the next expiry time can be\r\n\tre-assessed.  */\r\n\t*pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );\r\n\tif( *pxListWasEmpty == pdFALSE )\r\n\t{\r\n\t\txNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );\r\n\t}\r\n\telse\r\n\t{\r\n\t\t/* Ensure the task unblocks when the tick count rolls over. */\r\n\t\txNextExpireTime = ( TickType_t ) 0U;\r\n\t}\r\n\r\n\treturn xNextExpireTime;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nstatic TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )\r\n{\r\nTickType_t xTimeNow;\r\nPRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */\r\n\r\n\txTimeNow = xTaskGetTickCount();\r\n\r\n\tif( xTimeNow < xLastTime )\r\n\t{\r\n\t\tprvSwitchTimerLists();\r\n\t\t*pxTimerListsWereSwitched = pdTRUE;\r\n\t}\r\n\telse\r\n\t{\r\n\t\t*pxTimerListsWereSwitched = pdFALSE;\r\n\t}\r\n\r\n\txLastTime = xTimeNow;\r\n\r\n\treturn xTimeNow;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nstatic BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime )\r\n{\r\nBaseType_t xProcessTimerNow = pdFALSE;\r\n\r\n\tlistSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );\r\n\tlistSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );\r\n\r\n\tif( xNextExpiryTime <= xTimeNow )\r\n\t{\r\n\t\t/* Has the expiry time elapsed between the command to start/reset a\r\n\t\ttimer was issued, and the time the command was processed? */\r\n\t\tif( ( xTimeNow - xCommandTime ) >= pxTimer->xTimerPeriodInTicks )\r\n\t\t{\r\n\t\t\t/* The time between a command being issued and the command being\r\n\t\t\tprocessed actually exceeds the timers period.  */\r\n\t\t\txProcessTimerNow = pdTRUE;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tvListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );\r\n\t\t}\r\n\t}\r\n\telse\r\n\t{\r\n\t\tif( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )\r\n\t\t{\r\n\t\t\t/* If, since the command was issued, the tick count has overflowed\r\n\t\t\tbut the expiry time has not, then the timer must have already passed\r\n\t\t\tits expiry time and should be processed immediately. */\r\n\t\t\txProcessTimerNow = pdTRUE;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tvListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );\r\n\t\t}\r\n\t}\r\n\r\n\treturn xProcessTimerNow;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nstatic void\tprvProcessReceivedCommands( void )\r\n{\r\nDaemonTaskMessage_t xMessage;\r\nTimer_t *pxTimer;\r\nBaseType_t xTimerListsWereSwitched, xResult;\r\nTickType_t xTimeNow;\r\n\r\n\twhile( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */\r\n\t{\r\n\t\t#if ( INCLUDE_xTimerPendFunctionCall == 1 )\r\n\t\t{\r\n\t\t\t/* Negative commands are pended function calls rather than timer\r\n\t\t\tcommands. */\r\n\t\t\tif( xMessage.xMessageID < ( BaseType_t ) 0 )\r\n\t\t\t{\r\n\t\t\t\tconst CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );\r\n\r\n\t\t\t\t/* The timer uses the xCallbackParameters member to request a\r\n\t\t\t\tcallback be executed.  Check the callback is not NULL. */\r\n\t\t\t\tconfigASSERT( pxCallback );\r\n\r\n\t\t\t\t/* Call the function. */\r\n\t\t\t\tpxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\t\t}\r\n\t\t#endif /* INCLUDE_xTimerPendFunctionCall */\r\n\r\n\t\t/* Commands that are positive are timer commands rather than pended\r\n\t\tfunction calls. */\r\n\t\tif( xMessage.xMessageID >= ( BaseType_t ) 0 )\r\n\t\t{\r\n\t\t\t/* The messages uses the xTimerParameters member to work on a\r\n\t\t\tsoftware timer. */\r\n\t\t\tpxTimer = xMessage.u.xTimerParameters.pxTimer;\r\n\r\n\t\t\tif( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE )\r\n\t\t\t{\r\n\t\t\t\t/* The timer is in a list, remove it. */\r\n\t\t\t\t( void ) uxListRemove( &( pxTimer->xTimerListItem ) );\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t}\r\n\r\n\t\t\ttraceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue );\r\n\r\n\t\t\t/* In this case the xTimerListsWereSwitched parameter is not used, but\r\n\t\t\tit must be present in the function call.  prvSampleTimeNow() must be\r\n\t\t\tcalled after the message is received from xTimerQueue so there is no\r\n\t\t\tpossibility of a higher priority task adding a message to the message\r\n\t\t\tqueue with a time that is ahead of the timer daemon task (because it\r\n\t\t\tpre-empted the timer daemon task after the xTimeNow value was set). */\r\n\t\t\txTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );\r\n\r\n\t\t\tswitch( xMessage.xMessageID )\r\n\t\t\t{\r\n\t\t\t\tcase tmrCOMMAND_START :\r\n\t\t\t    case tmrCOMMAND_START_FROM_ISR :\r\n\t\t\t    case tmrCOMMAND_RESET :\r\n\t\t\t    case tmrCOMMAND_RESET_FROM_ISR :\r\n\t\t\t\tcase tmrCOMMAND_START_DONT_TRACE :\r\n\t\t\t\t\t/* Start or restart a timer. */\r\n\t\t\t\t\tif( prvInsertTimerInActiveList( pxTimer,  xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) == pdTRUE )\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\t/* The timer expired before it was added to the active\r\n\t\t\t\t\t\ttimer list.  Process it now. */\r\n\t\t\t\t\t\tpxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );\r\n\t\t\t\t\t\ttraceTIMER_EXPIRED( pxTimer );\r\n\r\n\t\t\t\t\t\tif( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE )\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\txResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );\r\n\t\t\t\t\t\t\tconfigASSERT( xResult );\r\n\t\t\t\t\t\t\t( void ) xResult;\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t\telse\r\n\t\t\t\t\t\t{\r\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t\t}\r\n\t\t\t\t\t}\r\n\t\t\t\t\telse\r\n\t\t\t\t\t{\r\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t\t}\r\n\t\t\t\t\tbreak;\r\n\r\n\t\t\t\tcase tmrCOMMAND_STOP :\r\n\t\t\t\tcase tmrCOMMAND_STOP_FROM_ISR :\r\n\t\t\t\t\t/* The timer has already been removed from the active list.\r\n\t\t\t\t\tThere is nothing to do here. */\r\n\t\t\t\t\tbreak;\r\n\r\n\t\t\t\tcase tmrCOMMAND_CHANGE_PERIOD :\r\n\t\t\t\tcase tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :\r\n\t\t\t\t\tpxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;\r\n\t\t\t\t\tconfigASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );\r\n\r\n\t\t\t\t\t/* The new period does not really have a reference, and can be\r\n\t\t\t\t\tlonger or shorter than the old one.  The command time is\r\n\t\t\t\t\ttherefore set to the current time, and as the period cannot be\r\n\t\t\t\t\tzero the next expiry time can only be in the future, meaning\r\n\t\t\t\t\t(unlike for the xTimerStart() case above) there is no fail case\r\n\t\t\t\t\tthat needs to be handled here. */\r\n\t\t\t\t\t( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );\r\n\t\t\t\t\tbreak;\r\n\r\n\t\t\t\tcase tmrCOMMAND_DELETE :\r\n\t\t\t\t\t/* The timer has already been removed from the active list,\r\n\t\t\t\t\tjust free up the memory. */\r\n\t\t\t\t\tvPortFree( pxTimer );\r\n\t\t\t\t\tbreak;\r\n\r\n\t\t\t\tdefault\t:\r\n\t\t\t\t\t/* Don't expect to get here. */\r\n\t\t\t\t\tbreak;\r\n\t\t\t}\r\n\t\t}\r\n\t}\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nstatic void prvSwitchTimerLists( void )\r\n{\r\nTickType_t xNextExpireTime, xReloadTime;\r\nList_t *pxTemp;\r\nTimer_t *pxTimer;\r\nBaseType_t xResult;\r\n\r\n\t/* The tick count has overflowed.  The timer lists must be switched.\r\n\tIf there are any timers still referenced from the current timer list\r\n\tthen they must have expired and should be processed before the lists\r\n\tare switched. */\r\n\twhile( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )\r\n\t{\r\n\t\txNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );\r\n\r\n\t\t/* Remove the timer from the list. */\r\n\t\tpxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList );\r\n\t\t( void ) uxListRemove( &( pxTimer->xTimerListItem ) );\r\n\t\ttraceTIMER_EXPIRED( pxTimer );\r\n\r\n\t\t/* Execute its callback, then send a command to restart the timer if\r\n\t\tit is an auto-reload timer.  It cannot be restarted here as the lists\r\n\t\thave not yet been switched. */\r\n\t\tpxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );\r\n\r\n\t\tif( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE )\r\n\t\t{\r\n\t\t\t/* Calculate the reload value, and if the reload value results in\r\n\t\t\tthe timer going into the same timer list then it has already expired\r\n\t\t\tand the timer should be re-inserted into the current list so it is\r\n\t\t\tprocessed again within this loop.  Otherwise a command should be sent\r\n\t\t\tto restart the timer to ensure it is only inserted into a list after\r\n\t\t\tthe lists have been swapped. */\r\n\t\t\txReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );\r\n\t\t\tif( xReloadTime > xNextExpireTime )\r\n\t\t\t{\r\n\t\t\t\tlistSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );\r\n\t\t\t\tlistSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );\r\n\t\t\t\tvListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\txResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );\r\n\t\t\t\tconfigASSERT( xResult );\r\n\t\t\t\t( void ) xResult;\r\n\t\t\t}\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t}\r\n\t}\r\n\r\n\tpxTemp = pxCurrentTimerList;\r\n\tpxCurrentTimerList = pxOverflowTimerList;\r\n\tpxOverflowTimerList = pxTemp;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nstatic void prvCheckForValidListAndQueue( void )\r\n{\r\n\t/* Check that the list from which active timers are referenced, and the\r\n\tqueue used to communicate with the timer service, have been\r\n\tinitialised. */\r\n\ttaskENTER_CRITICAL();\r\n\t{\r\n\t\tif( xTimerQueue == NULL )\r\n\t\t{\r\n\t\t\tvListInitialise( &xActiveTimerList1 );\r\n\t\t\tvListInitialise( &xActiveTimerList2 );\r\n\t\t\tpxCurrentTimerList = &xActiveTimerList1;\r\n\t\t\tpxOverflowTimerList = &xActiveTimerList2;\r\n\t\t\txTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ) );\r\n\t\t\tconfigASSERT( xTimerQueue );\r\n\r\n\t\t\t#if ( configQUEUE_REGISTRY_SIZE > 0 )\r\n\t\t\t{\r\n\t\t\t\tif( xTimerQueue != NULL )\r\n\t\t\t\t{\r\n\t\t\t\t\tvQueueAddToRegistry( xTimerQueue, \"TmrQ\" );\r\n\t\t\t\t}\r\n\t\t\t\telse\r\n\t\t\t\t{\r\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\t#endif /* configQUEUE_REGISTRY_SIZE */\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tmtCOVERAGE_TEST_MARKER();\r\n\t\t}\r\n\t}\r\n\ttaskEXIT_CRITICAL();\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nBaseType_t xTimerIsTimerActive( TimerHandle_t xTimer )\r\n{\r\nBaseType_t xTimerIsInActiveList;\r\nTimer_t *pxTimer = ( Timer_t * ) xTimer;\r\n\r\n\t/* Is the timer in the list of active timers? */\r\n\ttaskENTER_CRITICAL();\r\n\t{\r\n\t\t/* Checking to see if it is in the NULL list in effect checks to see if\r\n\t\tit is referenced from either the current or the overflow timer lists in\r\n\t\tone go, but the logic has to be reversed, hence the '!'. */\r\n\t\txTimerIsInActiveList = ( BaseType_t ) !( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) );\r\n\t}\r\n\ttaskEXIT_CRITICAL();\r\n\r\n\treturn xTimerIsInActiveList;\r\n} /*lint !e818 Can't be pointer to const due to the typedef. */\r\n/*-----------------------------------------------------------*/\r\n\r\nvoid *pvTimerGetTimerID( const TimerHandle_t xTimer )\r\n{\r\nTimer_t * const pxTimer = ( Timer_t * ) xTimer;\r\nvoid *pvReturn;\r\n\r\n\tconfigASSERT( xTimer );\r\n\r\n\ttaskENTER_CRITICAL();\r\n\t{\r\n\t\tpvReturn = pxTimer->pvTimerID;\r\n\t}\r\n\ttaskEXIT_CRITICAL();\r\n\r\n\treturn pvReturn;\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\nvoid vTimerSetTimerID( const TimerHandle_t xTimer, void *pvNewID )\r\n{\r\nTimer_t * const pxTimer = ( Timer_t * ) xTimer;\r\n\r\n\tconfigASSERT( xTimer );\r\n\r\n\ttaskENTER_CRITICAL();\r\n\t{\r\n\t\tpxTimer->pvTimerID = pvNewID;\r\n\t}\r\n\ttaskEXIT_CRITICAL();\r\n}\r\n/*-----------------------------------------------------------*/\r\n\r\n#if( INCLUDE_xTimerPendFunctionCall == 1 )\r\n\r\n\tBaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken )\r\n\t{\r\n\tDaemonTaskMessage_t xMessage;\r\n\tBaseType_t xReturn;\r\n\r\n\t\t/* Complete the message with the function parameters and post it to the\r\n\t\tdaemon task. */\r\n\t\txMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR;\r\n\t\txMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;\r\n\t\txMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;\r\n\t\txMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;\r\n\r\n\t\txReturn = xQueueSendFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );\r\n\r\n\t\ttracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, xReturn );\r\n\r\n\t\treturn xReturn;\r\n\t}\r\n\r\n#endif /* INCLUDE_xTimerPendFunctionCall */\r\n/*-----------------------------------------------------------*/\r\n\r\n#if( INCLUDE_xTimerPendFunctionCall == 1 )\r\n\r\n\tBaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait )\r\n\t{\r\n\tDaemonTaskMessage_t xMessage;\r\n\tBaseType_t xReturn;\r\n\r\n\t\t/* This function can only be called after a timer has been created or\r\n\t\tafter the scheduler has been started because, until then, the timer\r\n\t\tqueue does not exist. */\r\n\t\tconfigASSERT( xTimerQueue );\r\n\r\n\t\t/* Complete the message with the function parameters and post it to the\r\n\t\tdaemon task. */\r\n\t\txMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK;\r\n\t\txMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;\r\n\t\txMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;\r\n\t\txMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;\r\n\r\n\t\txReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );\r\n\r\n\t\ttracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, xReturn );\r\n\r\n\t\treturn xReturn;\r\n\t}\r\n\r\n#endif /* INCLUDE_xTimerPendFunctionCall */\r\n/*-----------------------------------------------------------*/\r\n\r\n/* This entire source file will be skipped if the application is not configured\r\nto include software timer functionality.  If you want to include software timer\r\nfunctionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */\r\n#endif /* configUSE_TIMERS == 1 */\r\n\r\n\r\n\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RTOS/src/timers.h",
    "content": "/*\r\n    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r\n    All rights reserved\r\n\r\n    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r\n\r\n    This file is part of the FreeRTOS distribution.\r\n\r\n    FreeRTOS is free software; you can redistribute it and/or modify it under\r\n    the terms of the GNU General Public License (version 2) as published by the\r\n    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r\n\r\n    ***************************************************************************\r\n    >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r\n    >>!   distribute a combined work that includes FreeRTOS without being   !<<\r\n    >>!   obliged to provide the source code for proprietary components     !<<\r\n    >>!   outside of the FreeRTOS kernel.                                   !<<\r\n    ***************************************************************************\r\n\r\n    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r\n    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r\n    FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r\n    link: http://www.freertos.org/a00114.html\r\n\r\n    ***************************************************************************\r\n     *                                                                       *\r\n     *    FreeRTOS provides completely free yet professionally developed,    *\r\n     *    robust, strictly quality controlled, supported, and cross          *\r\n     *    platform software that is more than just the market leader, it     *\r\n     *    is the industry's de facto standard.                               *\r\n     *                                                                       *\r\n     *    Help yourself get started quickly while simultaneously helping     *\r\n     *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r\n     *    tutorial book, reference manual, or both:                          *\r\n     *    http://www.FreeRTOS.org/Documentation                              *\r\n     *                                                                       *\r\n    ***************************************************************************\r\n\r\n    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r\n    the FAQ page \"My application does not run, what could be wrong?\".  Have you\r\n    defined configASSERT()?\r\n\r\n    http://www.FreeRTOS.org/support - In return for receiving this top quality\r\n    embedded software for free we request you assist our global community by\r\n    participating in the support forum.\r\n\r\n    http://www.FreeRTOS.org/training - Investing in training allows your team to\r\n    be as productive as possible as early as possible.  Now you can receive\r\n    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r\n    Ltd, and the world's leading authority on the world's leading RTOS.\r\n\r\n    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r\n    including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r\n    compatible FAT file system, and our tiny thread aware UDP/IP stack.\r\n\r\n    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r\n    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r\n\r\n    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r\n    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r\n    licenses offer ticketed support, indemnification and commercial middleware.\r\n\r\n    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r\n    engineered and independently SIL3 certified version for use in safety and\r\n    mission critical applications that require provable dependability.\r\n\r\n    1 tab == 4 spaces!\r\n*/\r\n\r\n\r\n#ifndef TIMERS_H\r\n#define TIMERS_H\r\n\r\n#ifndef INC_FREERTOS_H\r\n\t#error \"include FreeRTOS.h must appear in source files before include timers.h\"\r\n#endif\r\n\r\n/*lint -e537 This headers are only multiply included if the application code\r\nhappens to also be including task.h. */\r\n#include \"task.h\"\r\n/*lint +e537 */\r\n\r\n#ifdef __cplusplus\r\nextern \"C\" {\r\n#endif\r\n\r\n/*-----------------------------------------------------------\r\n * MACROS AND DEFINITIONS\r\n *----------------------------------------------------------*/\r\n\r\n/* IDs for commands that can be sent/received on the timer queue.  These are to\r\nbe used solely through the macros that make up the public software timer API,\r\nas defined below.  The commands that are sent from interrupts must use the\r\nhighest numbers as tmrFIRST_FROM_ISR_COMMAND is used to determine if the task\r\nor interrupt version of the queue send function should be used. */\r\n#define tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR \t( ( BaseType_t ) -2 )\r\n#define tmrCOMMAND_EXECUTE_CALLBACK\t\t\t\t( ( BaseType_t ) -1 )\r\n#define tmrCOMMAND_START_DONT_TRACE\t\t\t\t( ( BaseType_t ) 0 )\r\n#define tmrCOMMAND_START\t\t\t\t\t    ( ( BaseType_t ) 1 )\r\n#define tmrCOMMAND_RESET\t\t\t\t\t\t( ( BaseType_t ) 2 )\r\n#define tmrCOMMAND_STOP\t\t\t\t\t\t\t( ( BaseType_t ) 3 )\r\n#define tmrCOMMAND_CHANGE_PERIOD\t\t\t\t( ( BaseType_t ) 4 )\r\n#define tmrCOMMAND_DELETE\t\t\t\t\t\t( ( BaseType_t ) 5 )\r\n\r\n#define tmrFIRST_FROM_ISR_COMMAND\t\t\t\t( ( BaseType_t ) 6 )\r\n#define tmrCOMMAND_START_FROM_ISR\t\t\t\t( ( BaseType_t ) 6 )\r\n#define tmrCOMMAND_RESET_FROM_ISR\t\t\t\t( ( BaseType_t ) 7 )\r\n#define tmrCOMMAND_STOP_FROM_ISR\t\t\t\t( ( BaseType_t ) 8 )\r\n#define tmrCOMMAND_CHANGE_PERIOD_FROM_ISR\t\t( ( BaseType_t ) 9 )\r\n\r\n\r\n/**\r\n * Type by which software timers are referenced.  For example, a call to\r\n * xTimerCreate() returns an TimerHandle_t variable that can then be used to\r\n * reference the subject timer in calls to other software timer API functions\r\n * (for example, xTimerStart(), xTimerReset(), etc.).\r\n */\r\ntypedef void * TimerHandle_t;\r\n\r\n/*\r\n * Defines the prototype to which timer callback functions must conform.\r\n */\r\ntypedef void (*TimerCallbackFunction_t)( TimerHandle_t xTimer );\r\n\r\n/*\r\n * Defines the prototype to which functions used with the\r\n * xTimerPendFunctionCallFromISR() function must conform.\r\n */\r\ntypedef void (*PendedFunction_t)( void *, uint32_t );\r\n\r\n/**\r\n * TimerHandle_t xTimerCreate( \tconst char * const pcTimerName,\r\n * \t\t\t\t\t\t\t\tTickType_t xTimerPeriodInTicks,\r\n * \t\t\t\t\t\t\t\tUBaseType_t uxAutoReload,\r\n * \t\t\t\t\t\t\t\tvoid * pvTimerID,\r\n * \t\t\t\t\t\t\t\tTimerCallbackFunction_t pxCallbackFunction );\r\n *\r\n * Creates a new software timer instance.  This allocates the storage required\r\n * by the new timer, initialises the new timers internal state, and returns a\r\n * handle by which the new timer can be referenced.\r\n *\r\n * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),\r\n * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and\r\n * xTimerChangePeriodFromISR() API functions can all be used to transition a\r\n * timer into the active state.\r\n *\r\n * @param pcTimerName A text name that is assigned to the timer.  This is done\r\n * purely to assist debugging.  The kernel itself only ever references a timer\r\n * by its handle, and never by its name.\r\n *\r\n * @param xTimerPeriodInTicks The timer period.  The time is defined in tick\r\n * periods so the constant portTICK_PERIOD_MS can be used to convert a time that\r\n * has been specified in milliseconds.  For example, if the timer must expire\r\n * after 100 ticks, then xTimerPeriodInTicks should be set to 100.\r\n * Alternatively, if the timer must expire after 500ms, then xPeriod can be set\r\n * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or\r\n * equal to 1000.\r\n *\r\n * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will\r\n * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.\r\n * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and\r\n * enter the dormant state after it expires.\r\n *\r\n * @param pvTimerID An identifier that is assigned to the timer being created.\r\n * Typically this would be used in the timer callback function to identify which\r\n * timer expired when the same callback function is assigned to more than one\r\n * timer.\r\n *\r\n * @param pxCallbackFunction The function to call when the timer expires.\r\n * Callback functions must have the prototype defined by TimerCallbackFunction_t,\r\n * which is\t\"void vCallbackFunction( TimerHandle_t xTimer );\".\r\n *\r\n * @return If the timer is successfully created then a handle to the newly\r\n * created timer is returned.  If the timer cannot be created (because either\r\n * there is insufficient FreeRTOS heap remaining to allocate the timer\r\n * structures, or the timer period was set to 0) then NULL is returned.\r\n *\r\n * Example usage:\r\n * @verbatim\r\n * #define NUM_TIMERS 5\r\n *\r\n * // An array to hold handles to the created timers.\r\n * TimerHandle_t xTimers[ NUM_TIMERS ];\r\n *\r\n * // An array to hold a count of the number of times each timer expires.\r\n * int32_t lExpireCounters[ NUM_TIMERS ] = { 0 };\r\n *\r\n * // Define a callback function that will be used by multiple timer instances.\r\n * // The callback function does nothing but count the number of times the\r\n * // associated timer expires, and stop the timer once the timer has expired\r\n * // 10 times.\r\n * void vTimerCallback( TimerHandle_t pxTimer )\r\n * {\r\n * int32_t lArrayIndex;\r\n * const int32_t xMaxExpiryCountBeforeStopping = 10;\r\n *\r\n * \t   // Optionally do something if the pxTimer parameter is NULL.\r\n * \t   configASSERT( pxTimer );\r\n *\r\n *     // Which timer expired?\r\n *     lArrayIndex = ( int32_t ) pvTimerGetTimerID( pxTimer );\r\n *\r\n *     // Increment the number of times that pxTimer has expired.\r\n *     lExpireCounters[ lArrayIndex ] += 1;\r\n *\r\n *     // If the timer has expired 10 times then stop it from running.\r\n *     if( lExpireCounters[ lArrayIndex ] == xMaxExpiryCountBeforeStopping )\r\n *     {\r\n *         // Do not use a block time if calling a timer API function from a\r\n *         // timer callback function, as doing so could cause a deadlock!\r\n *         xTimerStop( pxTimer, 0 );\r\n *     }\r\n * }\r\n *\r\n * void main( void )\r\n * {\r\n * int32_t x;\r\n *\r\n *     // Create then start some timers.  Starting the timers before the scheduler\r\n *     // has been started means the timers will start running immediately that\r\n *     // the scheduler starts.\r\n *     for( x = 0; x < NUM_TIMERS; x++ )\r\n *     {\r\n *         xTimers[ x ] = xTimerCreate(    \"Timer\",       // Just a text name, not used by the kernel.\r\n *                                         ( 100 * x ),   // The timer period in ticks.\r\n *                                         pdTRUE,        // The timers will auto-reload themselves when they expire.\r\n *                                         ( void * ) x,  // Assign each timer a unique id equal to its array index.\r\n *                                         vTimerCallback // Each timer calls the same callback when it expires.\r\n *                                     );\r\n *\r\n *         if( xTimers[ x ] == NULL )\r\n *         {\r\n *             // The timer was not created.\r\n *         }\r\n *         else\r\n *         {\r\n *             // Start the timer.  No block time is specified, and even if one was\r\n *             // it would be ignored because the scheduler has not yet been\r\n *             // started.\r\n *             if( xTimerStart( xTimers[ x ], 0 ) != pdPASS )\r\n *             {\r\n *                 // The timer could not be set into the Active state.\r\n *             }\r\n *         }\r\n *     }\r\n *\r\n *     // ...\r\n *     // Create tasks here.\r\n *     // ...\r\n *\r\n *     // Starting the scheduler will start the timers running as they have already\r\n *     // been set into the active state.\r\n *     xTaskStartScheduler();\r\n *\r\n *     // Should not reach here.\r\n *     for( ;; );\r\n * }\r\n * @endverbatim\r\n */\r\nTimerHandle_t xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\r\n\r\n/**\r\n * void *pvTimerGetTimerID( TimerHandle_t xTimer );\r\n *\r\n * Returns the ID assigned to the timer.\r\n *\r\n * IDs are assigned to timers using the pvTimerID parameter of the call to\r\n * xTimerCreated() that was used to create the timer, and by calling the\r\n * vTimerSetTimerID() API function.\r\n *\r\n * If the same callback function is assigned to multiple timers then the timer\r\n * ID can be used as time specific (timer local) storage.\r\n *\r\n * @param xTimer The timer being queried.\r\n *\r\n * @return The ID assigned to the timer being queried.\r\n *\r\n * Example usage:\r\n *\r\n * See the xTimerCreate() API function example usage scenario.\r\n */\r\nvoid *pvTimerGetTimerID( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;\r\n\r\n/**\r\n * void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID );\r\n *\r\n * Sets the ID assigned to the timer.\r\n *\r\n * IDs are assigned to timers using the pvTimerID parameter of the call to\r\n * xTimerCreated() that was used to create the timer.\r\n *\r\n * If the same callback function is assigned to multiple timers then the timer\r\n * ID can be used as time specific (timer local) storage.\r\n *\r\n * @param xTimer The timer being updated.\r\n *\r\n * @param pvNewID The ID to assign to the timer.\r\n *\r\n * Example usage:\r\n *\r\n * See the xTimerCreate() API function example usage scenario.\r\n */\r\nvoid vTimerSetTimerID( const TimerHandle_t xTimer, void *pvNewID ) PRIVILEGED_FUNCTION;\r\n\r\n/**\r\n * BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer );\r\n *\r\n * Queries a timer to see if it is active or dormant.\r\n *\r\n * A timer will be dormant if:\r\n *     1) It has been created but not started, or\r\n *     2) It is an expired one-shot timer that has not been restarted.\r\n *\r\n * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),\r\n * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and\r\n * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the\r\n * active state.\r\n *\r\n * @param xTimer The timer being queried.\r\n *\r\n * @return pdFALSE will be returned if the timer is dormant.  A value other than\r\n * pdFALSE will be returned if the timer is active.\r\n *\r\n * Example usage:\r\n * @verbatim\r\n * // This function assumes xTimer has already been created.\r\n * void vAFunction( TimerHandle_t xTimer )\r\n * {\r\n *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently \"if( xTimerIsTimerActive( xTimer ) )\"\r\n *     {\r\n *         // xTimer is active, do something.\r\n *     }\r\n *     else\r\n *     {\r\n *         // xTimer is not active, do something else.\r\n *     }\r\n * }\r\n * @endverbatim\r\n */\r\nBaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;\r\n\r\n/**\r\n * TaskHandle_t xTimerGetTimerDaemonTaskHandle( void );\r\n *\r\n * xTimerGetTimerDaemonTaskHandle() is only available if\r\n * INCLUDE_xTimerGetTimerDaemonTaskHandle is set to 1 in FreeRTOSConfig.h.\r\n *\r\n * Simply returns the handle of the timer service/daemon task.  It it not valid\r\n * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started.\r\n */\r\nTaskHandle_t xTimerGetTimerDaemonTaskHandle( void );\r\n\r\n/**\r\n * BaseType_t xTimerStart( TimerHandle_t xTimer, TickType_t xTicksToWait );\r\n *\r\n * Timer functionality is provided by a timer service/daemon task.  Many of the\r\n * public FreeRTOS timer API functions send commands to the timer service task\r\n * through a queue called the timer command queue.  The timer command queue is\r\n * private to the kernel itself and is not directly accessible to application\r\n * code.  The length of the timer command queue is set by the\r\n * configTIMER_QUEUE_LENGTH configuration constant.\r\n *\r\n * xTimerStart() starts a timer that was previously created using the\r\n * xTimerCreate() API function.  If the timer had already been started and was\r\n * already in the active state, then xTimerStart() has equivalent functionality\r\n * to the xTimerReset() API function.\r\n *\r\n * Starting a timer ensures the timer is in the active state.  If the timer\r\n * is not stopped, deleted, or reset in the mean time, the callback function\r\n * associated with the timer will get called 'n' ticks after xTimerStart() was\r\n * called, where 'n' is the timers defined period.\r\n *\r\n * It is valid to call xTimerStart() before the scheduler has been started, but\r\n * when this is done the timer will not actually start until the scheduler is\r\n * started, and the timers expiry time will be relative to when the scheduler is\r\n * started, not relative to when xTimerStart() was called.\r\n *\r\n * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStart()\r\n * to be available.\r\n *\r\n * @param xTimer The handle of the timer being started/restarted.\r\n *\r\n * @param xTicksToWait Specifies the time, in ticks, that the calling task should\r\n * be held in the Blocked state to wait for the start command to be successfully\r\n * sent to the timer command queue, should the queue already be full when\r\n * xTimerStart() was called.  xTicksToWait is ignored if xTimerStart() is called\r\n * before the scheduler is started.\r\n *\r\n * @return pdFAIL will be returned if the start command could not be sent to\r\n * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will\r\n * be returned if the command was successfully sent to the timer command queue.\r\n * When the command is actually processed will depend on the priority of the\r\n * timer service/daemon task relative to other tasks in the system, although the\r\n * timers expiry time is relative to when xTimerStart() is actually called.  The\r\n * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY\r\n * configuration constant.\r\n *\r\n * Example usage:\r\n *\r\n * See the xTimerCreate() API function example usage scenario.\r\n *\r\n */\r\n#define xTimerStart( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )\r\n\r\n/**\r\n * BaseType_t xTimerStop( TimerHandle_t xTimer, TickType_t xTicksToWait );\r\n *\r\n * Timer functionality is provided by a timer service/daemon task.  Many of the\r\n * public FreeRTOS timer API functions send commands to the timer service task\r\n * through a queue called the timer command queue.  The timer command queue is\r\n * private to the kernel itself and is not directly accessible to application\r\n * code.  The length of the timer command queue is set by the\r\n * configTIMER_QUEUE_LENGTH configuration constant.\r\n *\r\n * xTimerStop() stops a timer that was previously started using either of the\r\n * The xTimerStart(), xTimerReset(), xTimerStartFromISR(), xTimerResetFromISR(),\r\n * xTimerChangePeriod() or xTimerChangePeriodFromISR() API functions.\r\n *\r\n * Stopping a timer ensures the timer is not in the active state.\r\n *\r\n * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStop()\r\n * to be available.\r\n *\r\n * @param xTimer The handle of the timer being stopped.\r\n *\r\n * @param xTicksToWait Specifies the time, in ticks, that the calling task should\r\n * be held in the Blocked state to wait for the stop command to be successfully\r\n * sent to the timer command queue, should the queue already be full when\r\n * xTimerStop() was called.  xTicksToWait is ignored if xTimerStop() is called\r\n * before the scheduler is started.\r\n *\r\n * @return pdFAIL will be returned if the stop command could not be sent to\r\n * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will\r\n * be returned if the command was successfully sent to the timer command queue.\r\n * When the command is actually processed will depend on the priority of the\r\n * timer service/daemon task relative to other tasks in the system.  The timer\r\n * service/daemon task priority is set by the configTIMER_TASK_PRIORITY\r\n * configuration constant.\r\n *\r\n * Example usage:\r\n *\r\n * See the xTimerCreate() API function example usage scenario.\r\n *\r\n */\r\n#define xTimerStop( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xTicksToWait ) )\r\n\r\n/**\r\n * BaseType_t xTimerChangePeriod( \tTimerHandle_t xTimer,\r\n *\t\t\t\t\t\t\t\t\t\tTickType_t xNewPeriod,\r\n *\t\t\t\t\t\t\t\t\t\tTickType_t xTicksToWait );\r\n *\r\n * Timer functionality is provided by a timer service/daemon task.  Many of the\r\n * public FreeRTOS timer API functions send commands to the timer service task\r\n * through a queue called the timer command queue.  The timer command queue is\r\n * private to the kernel itself and is not directly accessible to application\r\n * code.  The length of the timer command queue is set by the\r\n * configTIMER_QUEUE_LENGTH configuration constant.\r\n *\r\n * xTimerChangePeriod() changes the period of a timer that was previously\r\n * created using the xTimerCreate() API function.\r\n *\r\n * xTimerChangePeriod() can be called to change the period of an active or\r\n * dormant state timer.\r\n *\r\n * The configUSE_TIMERS configuration constant must be set to 1 for\r\n * xTimerChangePeriod() to be available.\r\n *\r\n * @param xTimer The handle of the timer that is having its period changed.\r\n *\r\n * @param xNewPeriod The new period for xTimer. Timer periods are specified in\r\n * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time\r\n * that has been specified in milliseconds.  For example, if the timer must\r\n * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,\r\n * if the timer must expire after 500ms, then xNewPeriod can be set to\r\n * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than\r\n * or equal to 1000.\r\n *\r\n * @param xTicksToWait Specifies the time, in ticks, that the calling task should\r\n * be held in the Blocked state to wait for the change period command to be\r\n * successfully sent to the timer command queue, should the queue already be\r\n * full when xTimerChangePeriod() was called.  xTicksToWait is ignored if\r\n * xTimerChangePeriod() is called before the scheduler is started.\r\n *\r\n * @return pdFAIL will be returned if the change period command could not be\r\n * sent to the timer command queue even after xTicksToWait ticks had passed.\r\n * pdPASS will be returned if the command was successfully sent to the timer\r\n * command queue.  When the command is actually processed will depend on the\r\n * priority of the timer service/daemon task relative to other tasks in the\r\n * system.  The timer service/daemon task priority is set by the\r\n * configTIMER_TASK_PRIORITY configuration constant.\r\n *\r\n * Example usage:\r\n * @verbatim\r\n * // This function assumes xTimer has already been created.  If the timer\r\n * // referenced by xTimer is already active when it is called, then the timer\r\n * // is deleted.  If the timer referenced by xTimer is not active when it is\r\n * // called, then the period of the timer is set to 500ms and the timer is\r\n * // started.\r\n * void vAFunction( TimerHandle_t xTimer )\r\n * {\r\n *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently \"if( xTimerIsTimerActive( xTimer ) )\"\r\n *     {\r\n *         // xTimer is already active - delete it.\r\n *         xTimerDelete( xTimer );\r\n *     }\r\n *     else\r\n *     {\r\n *         // xTimer is not active, change its period to 500ms.  This will also\r\n *         // cause the timer to start.  Block for a maximum of 100 ticks if the\r\n *         // change period command cannot immediately be sent to the timer\r\n *         // command queue.\r\n *         if( xTimerChangePeriod( xTimer, 500 / portTICK_PERIOD_MS, 100 ) == pdPASS )\r\n *         {\r\n *             // The command was successfully sent.\r\n *         }\r\n *         else\r\n *         {\r\n *             // The command could not be sent, even after waiting for 100 ticks\r\n *             // to pass.  Take appropriate action here.\r\n *         }\r\n *     }\r\n * }\r\n * @endverbatim\r\n */\r\n #define xTimerChangePeriod( xTimer, xNewPeriod, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xTicksToWait ) )\r\n\r\n/**\r\n * BaseType_t xTimerDelete( TimerHandle_t xTimer, TickType_t xTicksToWait );\r\n *\r\n * Timer functionality is provided by a timer service/daemon task.  Many of the\r\n * public FreeRTOS timer API functions send commands to the timer service task\r\n * through a queue called the timer command queue.  The timer command queue is\r\n * private to the kernel itself and is not directly accessible to application\r\n * code.  The length of the timer command queue is set by the\r\n * configTIMER_QUEUE_LENGTH configuration constant.\r\n *\r\n * xTimerDelete() deletes a timer that was previously created using the\r\n * xTimerCreate() API function.\r\n *\r\n * The configUSE_TIMERS configuration constant must be set to 1 for\r\n * xTimerDelete() to be available.\r\n *\r\n * @param xTimer The handle of the timer being deleted.\r\n *\r\n * @param xTicksToWait Specifies the time, in ticks, that the calling task should\r\n * be held in the Blocked state to wait for the delete command to be\r\n * successfully sent to the timer command queue, should the queue already be\r\n * full when xTimerDelete() was called.  xTicksToWait is ignored if xTimerDelete()\r\n * is called before the scheduler is started.\r\n *\r\n * @return pdFAIL will be returned if the delete command could not be sent to\r\n * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will\r\n * be returned if the command was successfully sent to the timer command queue.\r\n * When the command is actually processed will depend on the priority of the\r\n * timer service/daemon task relative to other tasks in the system.  The timer\r\n * service/daemon task priority is set by the configTIMER_TASK_PRIORITY\r\n * configuration constant.\r\n *\r\n * Example usage:\r\n *\r\n * See the xTimerChangePeriod() API function example usage scenario.\r\n */\r\n#define xTimerDelete( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xTicksToWait ) )\r\n\r\n/**\r\n * BaseType_t xTimerReset( TimerHandle_t xTimer, TickType_t xTicksToWait );\r\n *\r\n * Timer functionality is provided by a timer service/daemon task.  Many of the\r\n * public FreeRTOS timer API functions send commands to the timer service task\r\n * through a queue called the timer command queue.  The timer command queue is\r\n * private to the kernel itself and is not directly accessible to application\r\n * code.  The length of the timer command queue is set by the\r\n * configTIMER_QUEUE_LENGTH configuration constant.\r\n *\r\n * xTimerReset() re-starts a timer that was previously created using the\r\n * xTimerCreate() API function.  If the timer had already been started and was\r\n * already in the active state, then xTimerReset() will cause the timer to\r\n * re-evaluate its expiry time so that it is relative to when xTimerReset() was\r\n * called.  If the timer was in the dormant state then xTimerReset() has\r\n * equivalent functionality to the xTimerStart() API function.\r\n *\r\n * Resetting a timer ensures the timer is in the active state.  If the timer\r\n * is not stopped, deleted, or reset in the mean time, the callback function\r\n * associated with the timer will get called 'n' ticks after xTimerReset() was\r\n * called, where 'n' is the timers defined period.\r\n *\r\n * It is valid to call xTimerReset() before the scheduler has been started, but\r\n * when this is done the timer will not actually start until the scheduler is\r\n * started, and the timers expiry time will be relative to when the scheduler is\r\n * started, not relative to when xTimerReset() was called.\r\n *\r\n * The configUSE_TIMERS configuration constant must be set to 1 for xTimerReset()\r\n * to be available.\r\n *\r\n * @param xTimer The handle of the timer being reset/started/restarted.\r\n *\r\n * @param xTicksToWait Specifies the time, in ticks, that the calling task should\r\n * be held in the Blocked state to wait for the reset command to be successfully\r\n * sent to the timer command queue, should the queue already be full when\r\n * xTimerReset() was called.  xTicksToWait is ignored if xTimerReset() is called\r\n * before the scheduler is started.\r\n *\r\n * @return pdFAIL will be returned if the reset command could not be sent to\r\n * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will\r\n * be returned if the command was successfully sent to the timer command queue.\r\n * When the command is actually processed will depend on the priority of the\r\n * timer service/daemon task relative to other tasks in the system, although the\r\n * timers expiry time is relative to when xTimerStart() is actually called.  The\r\n * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY\r\n * configuration constant.\r\n *\r\n * Example usage:\r\n * @verbatim\r\n * // When a key is pressed, an LCD back-light is switched on.  If 5 seconds pass\r\n * // without a key being pressed, then the LCD back-light is switched off.  In\r\n * // this case, the timer is a one-shot timer.\r\n *\r\n * TimerHandle_t xBacklightTimer = NULL;\r\n *\r\n * // The callback function assigned to the one-shot timer.  In this case the\r\n * // parameter is not used.\r\n * void vBacklightTimerCallback( TimerHandle_t pxTimer )\r\n * {\r\n *     // The timer expired, therefore 5 seconds must have passed since a key\r\n *     // was pressed.  Switch off the LCD back-light.\r\n *     vSetBacklightState( BACKLIGHT_OFF );\r\n * }\r\n *\r\n * // The key press event handler.\r\n * void vKeyPressEventHandler( char cKey )\r\n * {\r\n *     // Ensure the LCD back-light is on, then reset the timer that is\r\n *     // responsible for turning the back-light off after 5 seconds of\r\n *     // key inactivity.  Wait 10 ticks for the command to be successfully sent\r\n *     // if it cannot be sent immediately.\r\n *     vSetBacklightState( BACKLIGHT_ON );\r\n *     if( xTimerReset( xBacklightTimer, 100 ) != pdPASS )\r\n *     {\r\n *         // The reset command was not executed successfully.  Take appropriate\r\n *         // action here.\r\n *     }\r\n *\r\n *     // Perform the rest of the key processing here.\r\n * }\r\n *\r\n * void main( void )\r\n * {\r\n * int32_t x;\r\n *\r\n *     // Create then start the one-shot timer that is responsible for turning\r\n *     // the back-light off if no keys are pressed within a 5 second period.\r\n *     xBacklightTimer = xTimerCreate( \"BacklightTimer\",           // Just a text name, not used by the kernel.\r\n *                                     ( 5000 / portTICK_PERIOD_MS), // The timer period in ticks.\r\n *                                     pdFALSE,                    // The timer is a one-shot timer.\r\n *                                     0,                          // The id is not used by the callback so can take any value.\r\n *                                     vBacklightTimerCallback     // The callback function that switches the LCD back-light off.\r\n *                                   );\r\n *\r\n *     if( xBacklightTimer == NULL )\r\n *     {\r\n *         // The timer was not created.\r\n *     }\r\n *     else\r\n *     {\r\n *         // Start the timer.  No block time is specified, and even if one was\r\n *         // it would be ignored because the scheduler has not yet been\r\n *         // started.\r\n *         if( xTimerStart( xBacklightTimer, 0 ) != pdPASS )\r\n *         {\r\n *             // The timer could not be set into the Active state.\r\n *         }\r\n *     }\r\n *\r\n *     // ...\r\n *     // Create tasks here.\r\n *     // ...\r\n *\r\n *     // Starting the scheduler will start the timer running as it has already\r\n *     // been set into the active state.\r\n *     xTaskStartScheduler();\r\n *\r\n *     // Should not reach here.\r\n *     for( ;; );\r\n * }\r\n * @endverbatim\r\n */\r\n#define xTimerReset( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )\r\n\r\n/**\r\n * BaseType_t xTimerStartFromISR( \tTimerHandle_t xTimer,\r\n *\t\t\t\t\t\t\t\t\tBaseType_t *pxHigherPriorityTaskWoken );\r\n *\r\n * A version of xTimerStart() that can be called from an interrupt service\r\n * routine.\r\n *\r\n * @param xTimer The handle of the timer being started/restarted.\r\n *\r\n * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most\r\n * of its time in the Blocked state, waiting for messages to arrive on the timer\r\n * command queue.  Calling xTimerStartFromISR() writes a message to the timer\r\n * command queue, so has the potential to transition the timer service/daemon\r\n * task out of the Blocked state.  If calling xTimerStartFromISR() causes the\r\n * timer service/daemon task to leave the Blocked state, and the timer service/\r\n * daemon task has a priority equal to or greater than the currently executing\r\n * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will\r\n * get set to pdTRUE internally within the xTimerStartFromISR() function.  If\r\n * xTimerStartFromISR() sets this value to pdTRUE then a context switch should\r\n * be performed before the interrupt exits.\r\n *\r\n * @return pdFAIL will be returned if the start command could not be sent to\r\n * the timer command queue.  pdPASS will be returned if the command was\r\n * successfully sent to the timer command queue.  When the command is actually\r\n * processed will depend on the priority of the timer service/daemon task\r\n * relative to other tasks in the system, although the timers expiry time is\r\n * relative to when xTimerStartFromISR() is actually called.  The timer\r\n * service/daemon task priority is set by the configTIMER_TASK_PRIORITY\r\n * configuration constant.\r\n *\r\n * Example usage:\r\n * @verbatim\r\n * // This scenario assumes xBacklightTimer has already been created.  When a\r\n * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass\r\n * // without a key being pressed, then the LCD back-light is switched off.  In\r\n * // this case, the timer is a one-shot timer, and unlike the example given for\r\n * // the xTimerReset() function, the key press event handler is an interrupt\r\n * // service routine.\r\n *\r\n * // The callback function assigned to the one-shot timer.  In this case the\r\n * // parameter is not used.\r\n * void vBacklightTimerCallback( TimerHandle_t pxTimer )\r\n * {\r\n *     // The timer expired, therefore 5 seconds must have passed since a key\r\n *     // was pressed.  Switch off the LCD back-light.\r\n *     vSetBacklightState( BACKLIGHT_OFF );\r\n * }\r\n *\r\n * // The key press interrupt service routine.\r\n * void vKeyPressEventInterruptHandler( void )\r\n * {\r\n * BaseType_t xHigherPriorityTaskWoken = pdFALSE;\r\n *\r\n *     // Ensure the LCD back-light is on, then restart the timer that is\r\n *     // responsible for turning the back-light off after 5 seconds of\r\n *     // key inactivity.  This is an interrupt service routine so can only\r\n *     // call FreeRTOS API functions that end in \"FromISR\".\r\n *     vSetBacklightState( BACKLIGHT_ON );\r\n *\r\n *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here\r\n *     // as both cause the timer to re-calculate its expiry time.\r\n *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was\r\n *     // declared (in this function).\r\n *     if( xTimerStartFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )\r\n *     {\r\n *         // The start command was not executed successfully.  Take appropriate\r\n *         // action here.\r\n *     }\r\n *\r\n *     // Perform the rest of the key processing here.\r\n *\r\n *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch\r\n *     // should be performed.  The syntax required to perform a context switch\r\n *     // from inside an ISR varies from port to port, and from compiler to\r\n *     // compiler.  Inspect the demos for the port you are using to find the\r\n *     // actual syntax required.\r\n *     if( xHigherPriorityTaskWoken != pdFALSE )\r\n *     {\r\n *         // Call the interrupt safe yield function here (actual function\r\n *         // depends on the FreeRTOS port being used).\r\n *     }\r\n * }\r\n * @endverbatim\r\n */\r\n#define xTimerStartFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )\r\n\r\n/**\r\n * BaseType_t xTimerStopFromISR( \tTimerHandle_t xTimer,\r\n *\t\t\t\t\t\t\t\t\tBaseType_t *pxHigherPriorityTaskWoken );\r\n *\r\n * A version of xTimerStop() that can be called from an interrupt service\r\n * routine.\r\n *\r\n * @param xTimer The handle of the timer being stopped.\r\n *\r\n * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most\r\n * of its time in the Blocked state, waiting for messages to arrive on the timer\r\n * command queue.  Calling xTimerStopFromISR() writes a message to the timer\r\n * command queue, so has the potential to transition the timer service/daemon\r\n * task out of the Blocked state.  If calling xTimerStopFromISR() causes the\r\n * timer service/daemon task to leave the Blocked state, and the timer service/\r\n * daemon task has a priority equal to or greater than the currently executing\r\n * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will\r\n * get set to pdTRUE internally within the xTimerStopFromISR() function.  If\r\n * xTimerStopFromISR() sets this value to pdTRUE then a context switch should\r\n * be performed before the interrupt exits.\r\n *\r\n * @return pdFAIL will be returned if the stop command could not be sent to\r\n * the timer command queue.  pdPASS will be returned if the command was\r\n * successfully sent to the timer command queue.  When the command is actually\r\n * processed will depend on the priority of the timer service/daemon task\r\n * relative to other tasks in the system.  The timer service/daemon task\r\n * priority is set by the configTIMER_TASK_PRIORITY configuration constant.\r\n *\r\n * Example usage:\r\n * @verbatim\r\n * // This scenario assumes xTimer has already been created and started.  When\r\n * // an interrupt occurs, the timer should be simply stopped.\r\n *\r\n * // The interrupt service routine that stops the timer.\r\n * void vAnExampleInterruptServiceRoutine( void )\r\n * {\r\n * BaseType_t xHigherPriorityTaskWoken = pdFALSE;\r\n *\r\n *     // The interrupt has occurred - simply stop the timer.\r\n *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined\r\n *     // (within this function).  As this is an interrupt service routine, only\r\n *     // FreeRTOS API functions that end in \"FromISR\" can be used.\r\n *     if( xTimerStopFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )\r\n *     {\r\n *         // The stop command was not executed successfully.  Take appropriate\r\n *         // action here.\r\n *     }\r\n *\r\n *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch\r\n *     // should be performed.  The syntax required to perform a context switch\r\n *     // from inside an ISR varies from port to port, and from compiler to\r\n *     // compiler.  Inspect the demos for the port you are using to find the\r\n *     // actual syntax required.\r\n *     if( xHigherPriorityTaskWoken != pdFALSE )\r\n *     {\r\n *         // Call the interrupt safe yield function here (actual function\r\n *         // depends on the FreeRTOS port being used).\r\n *     }\r\n * }\r\n * @endverbatim\r\n */\r\n#define xTimerStopFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP_FROM_ISR, 0, ( pxHigherPriorityTaskWoken ), 0U )\r\n\r\n/**\r\n * BaseType_t xTimerChangePeriodFromISR( TimerHandle_t xTimer,\r\n *\t\t\t\t\t\t\t\t\t\t TickType_t xNewPeriod,\r\n *\t\t\t\t\t\t\t\t\t\t BaseType_t *pxHigherPriorityTaskWoken );\r\n *\r\n * A version of xTimerChangePeriod() that can be called from an interrupt\r\n * service routine.\r\n *\r\n * @param xTimer The handle of the timer that is having its period changed.\r\n *\r\n * @param xNewPeriod The new period for xTimer. Timer periods are specified in\r\n * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time\r\n * that has been specified in milliseconds.  For example, if the timer must\r\n * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,\r\n * if the timer must expire after 500ms, then xNewPeriod can be set to\r\n * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than\r\n * or equal to 1000.\r\n *\r\n * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most\r\n * of its time in the Blocked state, waiting for messages to arrive on the timer\r\n * command queue.  Calling xTimerChangePeriodFromISR() writes a message to the\r\n * timer command queue, so has the potential to transition the timer service/\r\n * daemon task out of the Blocked state.  If calling xTimerChangePeriodFromISR()\r\n * causes the timer service/daemon task to leave the Blocked state, and the\r\n * timer service/daemon task has a priority equal to or greater than the\r\n * currently executing task (the task that was interrupted), then\r\n * *pxHigherPriorityTaskWoken will get set to pdTRUE internally within the\r\n * xTimerChangePeriodFromISR() function.  If xTimerChangePeriodFromISR() sets\r\n * this value to pdTRUE then a context switch should be performed before the\r\n * interrupt exits.\r\n *\r\n * @return pdFAIL will be returned if the command to change the timers period\r\n * could not be sent to the timer command queue.  pdPASS will be returned if the\r\n * command was successfully sent to the timer command queue.  When the command\r\n * is actually processed will depend on the priority of the timer service/daemon\r\n * task relative to other tasks in the system.  The timer service/daemon task\r\n * priority is set by the configTIMER_TASK_PRIORITY configuration constant.\r\n *\r\n * Example usage:\r\n * @verbatim\r\n * // This scenario assumes xTimer has already been created and started.  When\r\n * // an interrupt occurs, the period of xTimer should be changed to 500ms.\r\n *\r\n * // The interrupt service routine that changes the period of xTimer.\r\n * void vAnExampleInterruptServiceRoutine( void )\r\n * {\r\n * BaseType_t xHigherPriorityTaskWoken = pdFALSE;\r\n *\r\n *     // The interrupt has occurred - change the period of xTimer to 500ms.\r\n *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined\r\n *     // (within this function).  As this is an interrupt service routine, only\r\n *     // FreeRTOS API functions that end in \"FromISR\" can be used.\r\n *     if( xTimerChangePeriodFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )\r\n *     {\r\n *         // The command to change the timers period was not executed\r\n *         // successfully.  Take appropriate action here.\r\n *     }\r\n *\r\n *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch\r\n *     // should be performed.  The syntax required to perform a context switch\r\n *     // from inside an ISR varies from port to port, and from compiler to\r\n *     // compiler.  Inspect the demos for the port you are using to find the\r\n *     // actual syntax required.\r\n *     if( xHigherPriorityTaskWoken != pdFALSE )\r\n *     {\r\n *         // Call the interrupt safe yield function here (actual function\r\n *         // depends on the FreeRTOS port being used).\r\n *     }\r\n * }\r\n * @endverbatim\r\n */\r\n#define xTimerChangePeriodFromISR( xTimer, xNewPeriod, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD_FROM_ISR, ( xNewPeriod ), ( pxHigherPriorityTaskWoken ), 0U )\r\n\r\n/**\r\n * BaseType_t xTimerResetFromISR( \tTimerHandle_t xTimer,\r\n *\t\t\t\t\t\t\t\t\tBaseType_t *pxHigherPriorityTaskWoken );\r\n *\r\n * A version of xTimerReset() that can be called from an interrupt service\r\n * routine.\r\n *\r\n * @param xTimer The handle of the timer that is to be started, reset, or\r\n * restarted.\r\n *\r\n * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most\r\n * of its time in the Blocked state, waiting for messages to arrive on the timer\r\n * command queue.  Calling xTimerResetFromISR() writes a message to the timer\r\n * command queue, so has the potential to transition the timer service/daemon\r\n * task out of the Blocked state.  If calling xTimerResetFromISR() causes the\r\n * timer service/daemon task to leave the Blocked state, and the timer service/\r\n * daemon task has a priority equal to or greater than the currently executing\r\n * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will\r\n * get set to pdTRUE internally within the xTimerResetFromISR() function.  If\r\n * xTimerResetFromISR() sets this value to pdTRUE then a context switch should\r\n * be performed before the interrupt exits.\r\n *\r\n * @return pdFAIL will be returned if the reset command could not be sent to\r\n * the timer command queue.  pdPASS will be returned if the command was\r\n * successfully sent to the timer command queue.  When the command is actually\r\n * processed will depend on the priority of the timer service/daemon task\r\n * relative to other tasks in the system, although the timers expiry time is\r\n * relative to when xTimerResetFromISR() is actually called.  The timer service/daemon\r\n * task priority is set by the configTIMER_TASK_PRIORITY configuration constant.\r\n *\r\n * Example usage:\r\n * @verbatim\r\n * // This scenario assumes xBacklightTimer has already been created.  When a\r\n * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass\r\n * // without a key being pressed, then the LCD back-light is switched off.  In\r\n * // this case, the timer is a one-shot timer, and unlike the example given for\r\n * // the xTimerReset() function, the key press event handler is an interrupt\r\n * // service routine.\r\n *\r\n * // The callback function assigned to the one-shot timer.  In this case the\r\n * // parameter is not used.\r\n * void vBacklightTimerCallback( TimerHandle_t pxTimer )\r\n * {\r\n *     // The timer expired, therefore 5 seconds must have passed since a key\r\n *     // was pressed.  Switch off the LCD back-light.\r\n *     vSetBacklightState( BACKLIGHT_OFF );\r\n * }\r\n *\r\n * // The key press interrupt service routine.\r\n * void vKeyPressEventInterruptHandler( void )\r\n * {\r\n * BaseType_t xHigherPriorityTaskWoken = pdFALSE;\r\n *\r\n *     // Ensure the LCD back-light is on, then reset the timer that is\r\n *     // responsible for turning the back-light off after 5 seconds of\r\n *     // key inactivity.  This is an interrupt service routine so can only\r\n *     // call FreeRTOS API functions that end in \"FromISR\".\r\n *     vSetBacklightState( BACKLIGHT_ON );\r\n *\r\n *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here\r\n *     // as both cause the timer to re-calculate its expiry time.\r\n *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was\r\n *     // declared (in this function).\r\n *     if( xTimerResetFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )\r\n *     {\r\n *         // The reset command was not executed successfully.  Take appropriate\r\n *         // action here.\r\n *     }\r\n *\r\n *     // Perform the rest of the key processing here.\r\n *\r\n *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch\r\n *     // should be performed.  The syntax required to perform a context switch\r\n *     // from inside an ISR varies from port to port, and from compiler to\r\n *     // compiler.  Inspect the demos for the port you are using to find the\r\n *     // actual syntax required.\r\n *     if( xHigherPriorityTaskWoken != pdFALSE )\r\n *     {\r\n *         // Call the interrupt safe yield function here (actual function\r\n *         // depends on the FreeRTOS port being used).\r\n *     }\r\n * }\r\n * @endverbatim\r\n */\r\n#define xTimerResetFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )\r\n\r\n\r\n/**\r\n * BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,\r\n *                                          void *pvParameter1,\r\n *                                          uint32_t ulParameter2,\r\n *                                          BaseType_t *pxHigherPriorityTaskWoken );\r\n *\r\n *\r\n * Used from application interrupt service routines to defer the execution of a\r\n * function to the RTOS daemon task (the timer service task, hence this function\r\n * is implemented in timers.c and is prefixed with 'Timer').\r\n *\r\n * Ideally an interrupt service routine (ISR) is kept as short as possible, but\r\n * sometimes an ISR either has a lot of processing to do, or needs to perform\r\n * processing that is not deterministic.  In these cases\r\n * xTimerPendFunctionCallFromISR() can be used to defer processing of a function\r\n * to the RTOS daemon task.\r\n *\r\n * A mechanism is provided that allows the interrupt to return directly to the\r\n * task that will subsequently execute the pended callback function.  This\r\n * allows the callback function to execute contiguously in time with the\r\n * interrupt - just as if the callback had executed in the interrupt itself.\r\n *\r\n * @param xFunctionToPend The function to execute from the timer service/\r\n * daemon task.  The function must conform to the PendedFunction_t\r\n * prototype.\r\n *\r\n * @param pvParameter1 The value of the callback function's first parameter.\r\n * The parameter has a void * type to allow it to be used to pass any type.\r\n * For example, unsigned longs can be cast to a void *, or the void * can be\r\n * used to point to a structure.\r\n *\r\n * @param ulParameter2 The value of the callback function's second parameter.\r\n *\r\n * @param pxHigherPriorityTaskWoken As mentioned above, calling this function\r\n * will result in a message being sent to the timer daemon task.  If the\r\n * priority of the timer daemon task (which is set using\r\n * configTIMER_TASK_PRIORITY in FreeRTOSConfig.h) is higher than the priority of\r\n * the currently running task (the task the interrupt interrupted) then\r\n * *pxHigherPriorityTaskWoken will be set to pdTRUE within\r\n * xTimerPendFunctionCallFromISR(), indicating that a context switch should be\r\n * requested before the interrupt exits.  For that reason\r\n * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the\r\n * example code below.\r\n *\r\n * @return pdPASS is returned if the message was successfully sent to the\r\n * timer daemon task, otherwise pdFALSE is returned.\r\n *\r\n * Example usage:\r\n * @verbatim\r\n *\r\n *\t// The callback function that will execute in the context of the daemon task.\r\n *  // Note callback functions must all use this same prototype.\r\n *  void vProcessInterface( void *pvParameter1, uint32_t ulParameter2 )\r\n *\t{\r\n *\t\tBaseType_t xInterfaceToService;\r\n *\r\n *\t\t// The interface that requires servicing is passed in the second\r\n *      // parameter.  The first parameter is not used in this case.\r\n *\t\txInterfaceToService = ( BaseType_t ) ulParameter2;\r\n *\r\n *\t\t// ...Perform the processing here...\r\n *\t}\r\n *\r\n *\t// An ISR that receives data packets from multiple interfaces\r\n *  void vAnISR( void )\r\n *\t{\r\n *\t\tBaseType_t xInterfaceToService, xHigherPriorityTaskWoken;\r\n *\r\n *\t\t// Query the hardware to determine which interface needs processing.\r\n *\t\txInterfaceToService = prvCheckInterfaces();\r\n *\r\n *      // The actual processing is to be deferred to a task.  Request the\r\n *      // vProcessInterface() callback function is executed, passing in the\r\n *\t\t// number of the interface that needs processing.  The interface to\r\n *\t\t// service is passed in the second parameter.  The first parameter is\r\n *\t\t// not used in this case.\r\n *\t\txHigherPriorityTaskWoken = pdFALSE;\r\n *\t\txTimerPendFunctionCallFromISR( vProcessInterface, NULL, ( uint32_t ) xInterfaceToService, &xHigherPriorityTaskWoken );\r\n *\r\n *\t\t// If xHigherPriorityTaskWoken is now set to pdTRUE then a context\r\n *\t\t// switch should be requested.  The macro used is port specific and will\r\n *\t\t// be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to\r\n *\t\t// the documentation page for the port being used.\r\n *\t\tportYIELD_FROM_ISR( xHigherPriorityTaskWoken );\r\n *\r\n *\t}\r\n * @endverbatim\r\n */\r\nBaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken );\r\n\r\n /**\r\n  * BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,\r\n  *                                    void *pvParameter1,\r\n  *                                    uint32_t ulParameter2,\r\n  *                                    TickType_t xTicksToWait );\r\n  *\r\n  *\r\n  * Used to defer the execution of a function to the RTOS daemon task (the timer\r\n  * service task, hence this function is implemented in timers.c and is prefixed\r\n  * with 'Timer').\r\n  *\r\n  * @param xFunctionToPend The function to execute from the timer service/\r\n  * daemon task.  The function must conform to the PendedFunction_t\r\n  * prototype.\r\n  *\r\n  * @param pvParameter1 The value of the callback function's first parameter.\r\n  * The parameter has a void * type to allow it to be used to pass any type.\r\n  * For example, unsigned longs can be cast to a void *, or the void * can be\r\n  * used to point to a structure.\r\n  *\r\n  * @param ulParameter2 The value of the callback function's second parameter.\r\n  *\r\n  * @param xTicksToWait Calling this function will result in a message being\r\n  * sent to the timer daemon task on a queue.  xTicksToWait is the amount of\r\n  * time the calling task should remain in the Blocked state (so not using any\r\n  * processing time) for space to become available on the timer queue if the\r\n  * queue is found to be full.\r\n  *\r\n  * @return pdPASS is returned if the message was successfully sent to the\r\n  * timer daemon task, otherwise pdFALSE is returned.\r\n  *\r\n  */\r\nBaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait );\r\n\r\n/**\r\n * const char * const pcTimerGetTimerName( TimerHandle_t xTimer );\r\n *\r\n * Returns the name that was assigned to a timer when the timer was created.\r\n *\r\n * @param xTimer The handle of the timer being queried.\r\n *\r\n * @return The name assigned to the timer specified by the xTimer parameter.\r\n */\r\nconst char * pcTimerGetTimerName( TimerHandle_t xTimer ); /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\r\n\r\n/*\r\n * Functions beyond this part are not part of the public API and are intended\r\n * for use by the kernel only.\r\n */\r\nBaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION;\r\nBaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n#endif /* TIMERS_H */\r\n\r\n\r\n\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RobotisManipulator/include/robotis_manipulator/robotis_manipulator.h",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef ROBOTIS_MANIPULATOR_H_\n#define ROBOTIS_MANIPULATOR_H_\n\n#include \"robotis_manipulator_common.h\"\n#include \"robotis_manipulator_manager.h\"\n#include \"robotis_manipulator_trajectory_generator.h\"\n#include \"robotis_manipulator_math.h\"\n#include \"robotis_manipulator_log.h\"\n\n#include <algorithm>\n\nnamespace robotis_manipulator\n{\n\nclass RobotisManipulator\n{\nprivate:\n  Manipulator manipulator_;\n  Trajectory trajectory_;\n  Kinematics *kinematics_;\n  std::map<Name, JointActuator *> joint_actuator_;\n  std::map<Name, ToolActuator *> tool_actuator_;\n\n  bool trajectory_initialized_state_;\n  bool actuator_added_state_;\n  bool moving_state_;\n  bool step_moving_state_;\n\nprivate:\n  void startMoving();\n\n  JointWaypoint getTrajectoryJointValue(double tick_time);\n\npublic:\n  RobotisManipulator();\n  virtual ~RobotisManipulator();\n\n\n  /*****************************************************************************\n  ** Initialize Function\n  *****************************************************************************/\n  void addWorld(Name world_name,\n                Name child_name,\n                Eigen::Vector3d world_position = Eigen::Vector3d::Zero(),\n                Eigen::Matrix3d world_orientation = Eigen::Matrix3d::Identity());\n\n  void addJoint(Name my_name,\n                Name parent_name,\n                Name child_name,\n                Eigen::Vector3d relative_position,\n                Eigen::Matrix3d relative_orientation,\n                Eigen::Vector3d axis_of_rotation = Eigen::Vector3d::Zero(),\n                int8_t joint_actuator_id = -1, \n                double max_position_limit = M_PI, \n                double min_position_limit = -M_PI,\n                double coefficient = 1.0,\n                double mass = 0.0,\n                Eigen::Matrix3d inertia_tensor = Eigen::Matrix3d::Identity(),\n                Eigen::Vector3d center_of_mass = Eigen::Vector3d::Zero());\n\n  void addTool(Name my_name,\n               Name parent_name,\n               Eigen::Vector3d relative_position,\n               Eigen::Matrix3d relative_orientation,\n               int8_t tool_id = -1, \n               double max_position_limit = M_PI, \n               double min_position_limit = -M_PI,\n               double coefficient = 1.0,\n               double mass = 0.0,\n               Eigen::Matrix3d inertia_tensor = Eigen::Matrix3d::Identity(),\n               Eigen::Vector3d center_of_mass = Eigen::Vector3d::Zero());\n\n  void addComponentChild(Name my_name, Name child_name);\n  void printManipulatorSetting();\n\n  void addKinematics(Kinematics *kinematics);\n  void addJointActuator(Name actuator_name, JointActuator *joint_actuator, std::vector<uint8_t> id_array, const void *arg);\n  void addToolActuator(Name tool_name, ToolActuator *tool_actuator, uint8_t id, const void *arg);\n  void addCustomTrajectory(Name trajectory_name, CustomJointTrajectory *custom_trajectory);\n  void addCustomTrajectory(Name trajectory_name, CustomTaskTrajectory *custom_trajectory);\n\n\n  /*****************************************************************************\n  ** Manipulator Function\n  *****************************************************************************/\n  Manipulator *getManipulator();\n\n  JointValue getJointValue(Name joint_name);\n  JointValue getToolValue(Name tool_name);\n  std::vector<JointValue> getAllActiveJointValue();\n  std::vector<JointValue> getAllJointValue();\n  std::vector<double> getAllToolPosition();\n  std::vector<JointValue> getAllToolValue();\n  KinematicPose getKinematicPose(Name component_name);\n  DynamicPose getDynamicPose(Name component_name);\n  Pose getPose(Name component_name);\n\n\n  /*****************************************************************************\n  ** Kinematics Function (Including Virtual Function)\n  *****************************************************************************/\n  Eigen::MatrixXd jacobian(Name tool_name);\n  void solveForwardKinematics();\n  bool solveInverseKinematics(Name tool_name, Pose goal_pose, std::vector<JointValue> *goal_joint_value);\n  void setKinematicsOption(const void* arg);\n\n\n  /*****************************************************************************\n  ** Actuator Function (Including Virtual Function)\n  *****************************************************************************/\n  void setJointActuatorMode(Name actuator_name, std::vector<uint8_t> id_array, const void *arg);\n  void setToolActuatorMode(Name actuator_name, const void *arg);\n  std::vector<uint8_t> getJointActuatorId(Name actuator_name);\n  uint8_t getToolActuatorId(Name actuator_name);\n  void enableActuator(Name actuator_name);\n  void disableActuator(Name actuator_name);\n  void enableAllJointActuator();\n  void disableAllJointActuator();\n  void enableAllToolActuator();\n  void disableAllToolActuator();\n  void enableAllActuator();\n  void disableAllActuator();\n  bool getActuatorEnabledState(Name actuator_name);\n\n  bool sendJointActuatorValue(Name joint_component_name, JointValue value);\n  bool sendMultipleJointActuatorValue(std::vector<Name> joint_component_name, std::vector<JointValue> value_vector);\n  bool sendAllJointActuatorValue(std::vector<JointValue> value_vector);\n  JointValue receiveJointActuatorValue(Name joint_component_name);\n  std::vector<JointValue> receiveMultipleJointActuatorValue(std::vector<Name> joint_component_name);\n  std::vector<JointValue> receiveAllJointActuatorValue();\n\n  bool sendToolActuatorValue(Name tool_component_name, JointValue value);\n  bool sendMultipleToolActuatorValue(std::vector<Name> tool_component_name, std::vector<JointValue> value_vector);\n  bool sendAllToolActuatorValue(std::vector<JointValue> value_vector);\n  JointValue receiveToolActuatorValue(Name tool_component_name);\n  std::vector<JointValue> receiveMultipleToolActuatorValue(std::vector<Name> tool_component_name);\n  std::vector<JointValue> receiveAllToolActuatorValue();\n\n\n  /*****************************************************************************\n  ** Time Function\n  *****************************************************************************/\n  double getTrajectoryMoveTime();\n  bool getMovingState();\n\n\n  /*****************************************************************************\n  ** Check Joint Limit Function\n  *****************************************************************************/\n  bool checkJointLimit(Name component_name, double position);\n  bool checkJointLimit(Name component_name, JointValue value);\n  bool checkJointLimit(std::vector<Name> component_name, std::vector<double> position_vector);\n  bool checkJointLimit(std::vector<Name> component_name, std::vector<JointValue> value_vector);\n\n\n  /*****************************************************************************\n  ** Trajectory Control Fuction\n  *****************************************************************************/\n  Trajectory *getTrajectory();\n  void makeJointTrajectoryFromPresentPosition(std::vector<double> delta_goal_joint_position, double move_time, std::vector<JointValue> present_joint_value = {});\n  void makeJointTrajectory(std::vector<double> goal_joint_position, double move_time, std::vector<JointValue> present_joint_value = {});\n  void makeJointTrajectory(std::vector<JointValue> goal_joint_value, double move_time, std::vector<JointValue> present_joint_value = {});\n  void makeJointTrajectory(Name tool_name, Eigen::Vector3d goal_position, double move_time, std::vector<JointValue> present_joint_value = {});\n  void makeJointTrajectory(Name tool_name, Eigen::Matrix3d goal_orientation, double move_time, std::vector<JointValue> present_joint_value = {});\n  void makeJointTrajectory(Name tool_name, KinematicPose goal_pose, double move_time, std::vector<JointValue> present_joint_value = {});\n\n  void makeTaskTrajectoryFromPresentPose(Name tool_name, Eigen::Vector3d position_meter, double move_time, std::vector<JointValue> present_joint_value = {});\n  void makeTaskTrajectoryFromPresentPose(Name tool_name, Eigen::Matrix3d orientation_meter, double move_time, std::vector<JointValue> present_joint_value = {});\n  void makeTaskTrajectoryFromPresentPose(Name tool_name, KinematicPose goal_pose_delta, double move_time, std::vector<JointValue> present_joint_value = {});\n  void makeTaskTrajectory(Name tool_name, Eigen::Vector3d goal_position, double move_time, std::vector<JointValue> present_joint_value = {});\n  void makeTaskTrajectory(Name tool_name, Eigen::Matrix3d goal_orientation, double move_time, std::vector<JointValue> present_joint_value = {});\n  void makeTaskTrajectory(Name tool_name, KinematicPose goal_pose, double move_time, std::vector<JointValue> present_joint_value = {});\n\n  void setCustomTrajectoryOption(Name trajectory_name, const void* arg);\n  void makeCustomTrajectory(Name trajectory_name, Name tool_name, const void *arg, double move_time, std::vector<JointValue> present_joint_value = {});\n  void makeCustomTrajectory(Name trajectory_name, const void *arg, double move_time, std::vector<JointValue> present_joint_value = {});\n\n  void sleepTrajectory(double wait_time, std::vector<JointValue> present_joint_value = {});\n\n  void makeToolTrajectory(Name tool_name, double tool_goal_position);\n\n  std::vector<JointValue> getJointGoalValueFromTrajectory(double present_time);\n  std::vector<JointValue> getToolGoalValue();\n  std::vector<JointValue> getJointGoalValueFromTrajectoryTickTime(double tick_time);\n};\n} // namespace ROBOTIS_MANIPULATOR\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RobotisManipulator/include/robotis_manipulator/robotis_manipulator_common.h",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef ROBOTIS_MANIPULATOR_COMMON_H\n#define ROBOTIS_MANIPULATOR_COMMON_H\n\n#include <unistd.h>\n#if defined(__OPENCR__)\n  #include <Eigen.h>  // Calls main Eigen matrix class library\n  #include <Eigen/LU> // Calls inverse, determinant, LU decomp., etc.\n  #include <WString.h>\n#else\n  #include <eigen3/Eigen/Eigen>\n  #include <eigen3/Eigen/LU>\n#endif\n#include <math.h>\n#include <vector>\n#include <map>\n#include \"robotis_manipulator_math.h\"\n#include \"robotis_manipulator_log.h\"\n\nnamespace robotis_manipulator\n{\n\ntypedef STRING Name;\n\n\n/*****************************************************************************\n** Value Set\n*****************************************************************************/\ntypedef struct _KinematicPose\n{\n  Eigen::Vector3d position;\n  Eigen::Matrix3d orientation;\n} KinematicPose;\n\ntypedef struct _Dynamicvector\n{\n  Eigen::Vector3d velocity;\n  Eigen::Vector3d acceleration;\n} Dynamicvector;\n\ntypedef struct _DynamicPose\n{\n  Dynamicvector linear;\n  Dynamicvector angular;\n} DynamicPose;\n\ntypedef struct _Inertia\n{\n  double mass;\n  Eigen::Matrix3d inertia_tensor;\n  Eigen::Vector3d center_of_mass;\n} Inertia;\n\ntypedef struct _Limit\n{\n  double maximum;\n  double minimum;\n} Limit;\n\n\n/*****************************************************************************\n** Time Set\n*****************************************************************************/\ntypedef struct _Time\n{\n  double total_move_time;\n  double present_time;\n  double start_time;\n} Time;\n\n\n/*****************************************************************************\n** Trajectory Set\n*****************************************************************************/\ntypedef enum _TrajectoryType\n{\n  NONE = 0,\n  JOINT_TRAJECTORY,\n  TASK_TRAJECTORY,\n  CUSTOM_JOINT_TRAJECTORY,\n  CUSTOM_TASK_TRAJECTORY\n} TrajectoryType;\n\ntypedef struct _Point\n{\n  double position;\n  double velocity;\n  double acceleration;\n  double effort;\n} Point, ActuatorValue, JointValue, ToolValue;\n\ntypedef std::vector<JointValue> JointWaypoint;\n\ntypedef struct _TaskWaypoint\n{\n  KinematicPose kinematic;\n  DynamicPose dynamic;\n} TaskWaypoint, Pose;\n\n\n/*****************************************************************************\n** Component Set\n*****************************************************************************/\ntypedef enum _ComponentType\n{\n  PASSIVE_JOINT_COMPONENT = 0,\n  ACTIVE_JOINT_COMPONENT,\n  TOOL_COMPONENT\n} ComponentType;\n\ntypedef struct _ChainingName\n{\n  Name parent;\n  std::vector<Name> child;\n} ChainingName;\n\ntypedef struct _Relative\n{\n  KinematicPose pose_from_parent;\n  Inertia inertia;\n} Relative;\n\ntypedef struct _JointConstant\n{\n  int8_t id;\n  Eigen::Vector3d axis;\n  double coefficient;       // joint angle over actuator angle\n  Limit position_limit;\n} JointConstant;\n\ntypedef struct _World\n{\n  Name name;\n  Name child;\n  Pose pose;\n} World;\n\ntypedef struct _Component\n{\n  //constant\n  ChainingName name;\n  ComponentType component_type;\n  Relative relative;\n  JointConstant joint_constant;\n\n  //variable\n  Pose pose_from_world;\n  JointValue joint_value;\n\n  //Actuator\n  Name actuator_name;\n} Component;\n\n\n/*****************************************************************************\n** Manipulator Class\n*****************************************************************************/\nclass Manipulator\n{\nprivate:\n  int8_t dof_;\n  World world_;\n  std::map<Name, Component> component_;\n\npublic:\n  Manipulator();\n  ~Manipulator() {}\n\n  /*****************************************************************************\n  ** Add Function\n  *****************************************************************************/\n  void addWorld(Name world_name,\n                Name child_name,\n                Eigen::Vector3d world_position = Eigen::Vector3d::Zero(),\n                Eigen::Matrix3d world_orientation = Eigen::Matrix3d::Identity());\n\n  void addJoint(Name my_name,\n                Name parent_name,\n                Name child_name,\n                Eigen::Vector3d relative_position,\n                Eigen::Matrix3d relative_orientation,\n                Eigen::Vector3d axis_of_rotation = Eigen::Vector3d::Zero(),\n                int8_t joint_actuator_id = -1, \n                double max_position_limit = M_PI, \n                double min_position_limit = -M_PI,\n                double coefficient = 1.0,\n                double mass = 0.0,\n                Eigen::Matrix3d inertia_tensor = Eigen::Matrix3d::Identity(),\n                Eigen::Vector3d center_of_mass = Eigen::Vector3d::Zero());\n\n  void addTool(Name my_name,\n               Name parent_name,\n               Eigen::Vector3d relative_position,\n               Eigen::Matrix3d relative_orientation,\n               int8_t tool_id = -1, \n               double max_position_limit = M_PI, \n               double min_position_limit = -M_PI,\n               double coefficient = 1.0,\n               double mass = 0.0,\n               Eigen::Matrix3d inertia_tensor = Eigen::Matrix3d::Identity(),\n               Eigen::Vector3d center_of_mass = Eigen::Vector3d::Zero());\n\n  void addComponentChild(Name my_name, Name child_name);\n  void printManipulatorSetting();\n\n\n  /*****************************************************************************\n  ** Set Function\n  *****************************************************************************/\n  void setWorldPose(Pose world_pose);\n  void setWorldKinematicPose(KinematicPose world_kinematic_pose);\n  void setWorldPosition(Eigen::Vector3d world_position);\n  void setWorldOrientation(Eigen::Matrix3d world_orientation);\n  void setWorldDynamicPose(DynamicPose world_dynamic_pose);\n  void setWorldLinearVelocity(Eigen::Vector3d world_linear_velocity);\n  void setWorldAngularVelocity(Eigen::Vector3d world_angular_velocity);\n  void setWorldLinearAcceleration(Eigen::Vector3d world_linear_acceleration);\n  void setWorldAngularAcceleration(Eigen::Vector3d world_angular_acceleration);\n  void setComponent(Name component_name, Component component);\n  void setComponentActuatorName(Name component_name, Name actuator_name);\n  void setComponentPoseFromWorld(Name component_name, Pose pose_to_world);\n  void setComponentKinematicPoseFromWorld(Name component_name, KinematicPose pose_to_world);\n  void setComponentPositionFromWorld(Name component_name, Eigen::Vector3d position_to_world);\n  void setComponentOrientationFromWorld(Name component_name, Eigen::Matrix3d orientation_to_wolrd);\n  void setComponentDynamicPoseFromWorld(Name component_name, DynamicPose dynamic_pose);\n\n  void setJointPosition(Name name, double position);\n  void setJointVelocity(Name name, double velocity);\n  void setJointAcceleration(Name name, double acceleration);\n  void setJointEffort(Name name, double effort);\n  void setJointValue(Name name, JointValue joint_value);\n\n  void setAllActiveJointPosition(std::vector<double> joint_position_vector);\n  void setAllActiveJointValue(std::vector<JointValue> joint_value_vector);\n  void setAllJointPosition(std::vector<double> joint_position_vector);\n  void setAllJointValue(std::vector<JointValue> joint_value_vector);\n  void setAllToolPosition(std::vector<double> tool_position_vector);\n  void setAllToolValue(std::vector<JointValue> tool_value_vector);\n\n\n  /*****************************************************************************\n  ** Get Function\n  *****************************************************************************/\n  int8_t getDOF();\n  Name getWorldName();\n  Name getWorldChildName();\n  Pose getWorldPose();\n  KinematicPose getWorldKinematicPose();\n  Eigen::Vector3d getWorldPosition();\n  Eigen::Matrix3d getWorldOrientation();\n  DynamicPose getWorldDynamicPose();\n  int8_t getComponentSize();\n  std::map<Name, Component> getAllComponent();\n  std::map<Name, Component>::iterator getIteratorBegin();\n  std::map<Name, Component>::iterator getIteratorEnd();\n  Component getComponent(Name component_name);\n  Name getComponentActuatorName(Name component_name);\n  Name getComponentParentName(Name component_name);\n  std::vector<Name> getComponentChildName(Name component_name);\n  Pose getComponentPoseFromWorld(Name component_name);\n  KinematicPose getComponentKinematicPoseFromWorld(Name component_name);\n  Eigen::Vector3d getComponentPositionFromWorld(Name component_name);\n  Eigen::Matrix3d getComponentOrientationFromWorld(Name component_name);\n  DynamicPose getComponentDynamicPoseFromWorld(Name component_name);\n  KinematicPose getComponentRelativePoseFromParent(Name component_name);\n  Eigen::Vector3d getComponentRelativePositionFromParent(Name component_name);\n  Eigen::Matrix3d getComponentRelativeOrientationFromParent(Name component_name);\n\n  int8_t getId(Name component_name);\n  double getCoefficient(Name component_name);\n  Eigen::Vector3d getAxis(Name component_name);\n  double getJointPosition(Name component_name);\n  double getJointVelocity(Name component_name);\n  double getJointAcceleration(Name component_name);\n  double getJointEffort(Name component_name);\n  JointValue getJointValue(Name component_name);\n\n  double getComponentMass(Name component_name);\n  Eigen::Matrix3d getComponentInertiaTensor(Name component_name);\n  Eigen::Vector3d getComponentCenterOfMass(Name component_name);\n\n  std::vector<double> getAllJointPosition();\n  std::vector<JointValue> getAllJointValue();\n  std::vector<double> getAllActiveJointPosition();\n  std::vector<JointValue> getAllActiveJointValue();\n  std::vector<double> getAllToolPosition();\n  std::vector<JointValue> getAllToolValue();\n\n  std::vector<uint8_t> getAllJointID();\n  std::vector<uint8_t> getAllActiveJointID();\n  std::vector<Name> getAllToolComponentName();\n  std::vector<Name> getAllActiveJointComponentName();\n\n\n  /*****************************************************************************\n  ** Check Function\n  *****************************************************************************/\n  bool checkJointLimit(Name Component_name, double value);\n  bool checkComponentType(Name component_name, ComponentType component_type);\n\n\n  /*****************************************************************************\n  ** Find Function\n  *****************************************************************************/\n  Name findComponentNameUsingId(int8_t id);\n};\n\n}\n#endif // ROBOTIS_MANIPULATOR_COMMON_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RobotisManipulator/include/robotis_manipulator/robotis_manipulator_log.h",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef ROBOTIS_MANIPULATOR_LOG_H\n#define ROBOTIS_MANIPULATOR_LOG_H\n\n#include <unistd.h>\n#include <vector>\n\n#if defined(__OPENCR__)\n  #include <Eigen.h>\n  #include <WString.h>\n  #include \"variant.h\"\n\n  #define DEBUG SerialBT2\n#else\n  #include <string>\n\n  #define ANSI_COLOR_RED     \"\\x1b[31m\"\n  #define ANSI_COLOR_GREEN   \"\\x1b[32m\"\n  #define ANSI_COLOR_YELLOW  \"\\x1b[33m\"\n  #define ANSI_COLOR_BLUE    \"\\x1b[34m\"\n  #define ANSI_COLOR_MAGENTA \"\\x1b[35m\"\n  #define ANSI_COLOR_CYAN    \"\\x1b[36m\"\n  #define ANSI_COLOR_RESET   \"\\x1b[0m\"\n#endif\n\n#if defined(__OPENCR__)\n  typedef String\t\t  STRING;\n#else\n  typedef std::string STRING;\n#endif\n\nnamespace robotis_manipulator\n{\nnamespace log{\n\n  void print(STRING str, STRING color = \"DEFAULT\");\n  void print(STRING str, double data, uint8_t decimal_point = 3, STRING color = \"DEFAULT\");\n  void print(const char* str, STRING color = \"DEFAULT\");\n  void print(const char* str, double data, uint8_t decimal_point = 3, STRING color = \"DEFAULT\");\n\n  void println(STRING str, STRING color = \"DEFAULT\");\n  void println(STRING str, double data, uint8_t decimal_point = 3, STRING color = \"DEFAULT\");\n  void println(const char* str, STRING color = \"DEFAULT\");\n  void println(const char* str, double data, uint8_t decimal_point = 3, STRING color = \"DEFAULT\");\n\n  void info(STRING str);\n  void info(STRING str, double data, uint8_t decimal_point = 3);\n  void info(const char* str);\n  void info(const char* str, double data, uint8_t decimal_point = 3);\n  void warn(STRING str);\n  void warn(STRING str, double data, uint8_t decimal_point = 3);\n  void warn(const char* str);\n  void warn(const char* str, double data, uint8_t decimal_point = 3);\n  void error(STRING str);\n  void error(STRING str, double data, uint8_t decimal_point = 3);\n  void error(const char* str);\n  void error(const char* str, double data, uint8_t decimal_point = 3);\n\n  template <typename T> void print_vector(std::vector<T> &vec, uint8_t decimal_point = 3)\n  {\n  #if defined(__OPENCR__)\n    DEBUG.print(\"(\");\n    for (uint8_t i = 0; i < vec.size(); i++)\n    {\n      DEBUG.print(vec.at(i), decimal_point);\n      if(i != vec.size()-1)\n        DEBUG.print(\", \");\n      else\n        DEBUG.println(\")\");\n    }\n  #else\n    printf(\"(\");\n    for (uint8_t i = 0; i < vec.size(); i++)\n    {\n      printf(\"%.*lf\", decimal_point, vec.at(i));\n      if(i != vec.size()-1)\n        printf(\", \");\n      else\n        printf(\")\\n\");\n    }\n  #endif\n  }\n\n  template <typename vector> void print_vector(vector &vec, uint8_t decimal_point = 3)\n  {\n  #if defined(__OPENCR__)\n    DEBUG.print(\"(\");\n    for (uint8_t i = 0; i < vec.size(); i++)\n    {\n      DEBUG.print(vec(i), decimal_point);\n      if(i != vec.size()-1)\n        DEBUG.print(\", \");\n      else\n        DEBUG.println(\")\");\n    }\n  #else\n    printf(\"(\");\n    for (uint8_t i = 0; i < vec.size(); i++)\n    {\n      printf(\"%.*lf\", decimal_point, vec(i));\n      if(i != vec.size()-1)\n        printf(\", \");\n      else\n        printf(\")\\n\");\n    }\n  #endif\n  }\n\n  template <typename matrix> void print_matrix(matrix &m, uint8_t decimal_point = 3)\n  {\n  #if defined(__OPENCR__)\n\n    for (uint8_t i = 0; i < m.rows(); i++)\n    {\n      if(i == 0)\n        DEBUG.print(\"(\");\n      else\n        DEBUG.print(\" \");\n      for (uint8_t j = 0; j < m.cols(); j++)\n      {\n        DEBUG.print(m(i, j), decimal_point);\n        if(j != m.cols()-1)\n          DEBUG.print(\", \");\n      }\n      if(i != m.rows()-1)\n        DEBUG.println(\"\");\n      else\n        DEBUG.println(\")\");\n    }\n  #else\n\n    for (uint8_t i = 0; i < m.rows(); i++)\n    {\n      if(i == 0)\n        printf(\"(\");\n      else\n        printf(\" \");\n      for (uint8_t j = 0; j < m.cols(); j++)\n      {\n        printf(\"%.*lf\", decimal_point, m(i, j));\n        if(j != m.cols()-1)\n          printf(\", \");\n      }\n      if(i != m.rows()-1)\n        printf(\"\\n\");\n      else\n        printf(\")\\n\");\n    }\n  #endif\n  }\n\n} //log\n} //robotis_manipulator\n\n#endif // ROBOTIS_MANIPULATOR_LOG_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RobotisManipulator/include/robotis_manipulator/robotis_manipulator_manager.h",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef ROBOTIS_MANIPULATOR_MANAGER_H_\n#define ROBOTIS_MANIPULATOR_MANAGER_H_\n\n#if defined(__OPENCR__)\n  #include <Eigen.h>  // Calls main Eigen matrix class library\n#else\n  #include <eigen3/Eigen/Eigen>\n#endif\n\n#include \"robotis_manipulator_common.h\"\n\nnamespace robotis_manipulator\n{\n\nclass Kinematics\n{\npublic:\n  Kinematics() {}\n  virtual ~Kinematics() {}\n\n  virtual void setOption(const void *arg) = 0;\n  virtual Eigen::MatrixXd jacobian(Manipulator *manipulator, Name tool_name) = 0;\n  virtual void solveForwardKinematics(Manipulator *manipulator) = 0;\n  virtual bool solveInverseKinematics(Manipulator *manipulator, Name tool_name, Pose target_pose, std::vector<JointValue>* goal_joint_position) = 0;\n};\n\nclass JointActuator\n{\npublic:\n  bool enabled_state_;\n\n  JointActuator() : enabled_state_(false) {}\n  virtual ~JointActuator() {}\n\n  virtual void init(std::vector<uint8_t> actuator_id, const void *arg) = 0;\n  virtual void setMode(std::vector<uint8_t> actuator_id, const void *arg) = 0;\n  virtual std::vector<uint8_t> getId() = 0;\n\n  virtual void enable() = 0;\n  virtual void disable() = 0;\n\n  virtual bool sendJointActuatorValue(std::vector<uint8_t> actuator_id, std::vector<ActuatorValue> value_vector) = 0;\n  virtual std::vector<ActuatorValue> receiveJointActuatorValue(std::vector<uint8_t> actuator_id) = 0;\n\n  bool findId(uint8_t actuator_id);\n  bool getEnabledState();\n};\n\nclass ToolActuator\n{\npublic:\n  bool enabled_state_;\n\n  ToolActuator():enabled_state_(false){}\n  virtual ~ToolActuator() {}\n\n  virtual void init(uint8_t actuator_id, const void *arg) = 0;\n  virtual void setMode(const void *arg) = 0;\n  virtual uint8_t getId() = 0;\n\n  virtual void enable() = 0;\n  virtual void disable() = 0;\n\n  virtual bool sendToolActuatorValue(ActuatorValue value) = 0;\n  virtual ActuatorValue receiveToolActuatorValue() = 0;\n\n  bool findId(uint8_t actuator_id);\n  bool getEnabledState();\n};\n\n\nclass CustomJointTrajectory\n{\npublic:\n  CustomJointTrajectory() {}\n  virtual ~CustomJointTrajectory() {}\n\n  virtual void makeJointTrajectory(double move_time, JointWaypoint start, const void *arg) = 0; \n  virtual void setOption(const void *arg) = 0;\n  virtual JointWaypoint getJointWaypoint(double tick) = 0;\n};\n\nclass CustomTaskTrajectory\n{\npublic:\n  CustomTaskTrajectory() {}\n  virtual ~CustomTaskTrajectory() {}\n\n  virtual void makeTaskTrajectory(double move_time, TaskWaypoint start, const void *arg) = 0; \n  virtual void setOption(const void *arg) = 0;\n  virtual TaskWaypoint getTaskWaypoint(double tick) = 0;\n};\n\n} // namespace ROBOTIS_MANIPULATOR\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RobotisManipulator/include/robotis_manipulator/robotis_manipulator_math.h",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef ROBOTIS_MANIPULATOR_MATH_H_\n#define ROBOTIS_MANIPULATOR_MATH_H_\n\n#include <unistd.h>\n\n#if defined(__OPENCR__)\n  #include <Eigen.h>  // Calls main Eigen matrix class library\n  #include <Eigen/LU> // Calls inverse, determinant, LU decomp., etc.\n  #include <Eigen/Geometry>\n#else\n  #include <eigen3/Eigen/Eigen>\n  #include <eigen3/Eigen/LU>\n#endif\n\n#include <math.h>\n\n#define DEG2RAD 0.01745329252 //(M_PI / 180.0)\n#define RAD2DEG 57.2957795131 //(180.0 / M_PI)\n\nnamespace robotis_manipulator\n{\n\nnamespace math {\n\n/*****************************************************************************\n** Make a Vector or Matrix\n*****************************************************************************/\nEigen::Vector3d vector3(double v1, double v2, double v3);\nEigen::Matrix3d matrix3(double m11, double m12, double m13,\n                        double m21, double m22, double m23,\n                        double m31, double m32, double m33);\nEigen::Matrix3d inertiaMatrix(double ixx, double ixy, double ixz , double iyy , double iyz, double izz);\n\n\n/*****************************************************************************\n** Convert\n*****************************************************************************/\n// Translation Vector\nEigen::Vector3d convertXYZToVector(double x, double y, double z);\n\n// Rotation \nEigen::Matrix3d convertRollAngleToRotationMatrix(double angle);\nEigen::Matrix3d convertPitchAngleToRotationMatrix(double angle);\nEigen::Matrix3d convertYawAngleToRotationMatrix(double angle);\nEigen::Vector3d convertRotationMatrixToRPYVector(const Eigen::Matrix3d& rotation_matrix);\nEigen::Matrix3d convertRPYToRotationMatrix(double roll, double pitch, double yaw);\nEigen::Quaterniond convertRPYToQuaternion(double roll, double pitch, double yaw);\nEigen::Quaterniond convertRotationMatrixToQuaternion(const Eigen::Matrix3d& rotation_matrix);\nEigen::Vector3d convertQuaternionToRPYVector(const Eigen::Quaterniond& quaternion);\nEigen::Matrix3d convertQuaternionToRotationMatrix(const Eigen::Quaterniond& quaternion);\nEigen::Vector3d convertRotationMatrixToOmega(const Eigen::Matrix3d& rotation_matrix);\n\n// Transformation Matrix\nEigen::Matrix4d convertXYZRPYToTransformationMatrix(double x, double y, double z , double roll, double pitch, double yaw);\nEigen::Matrix4d convertXYZToTransformationMatrix(double x, double y, double z);\nEigen::Matrix4d convertRPYToTransformationMatrix(double roll, double pitch, double yaw);\n\n// Dynamic Value\nEigen::Vector3d convertOmegaToRPYVelocity(Eigen::Vector3d rpy_vector, Eigen::Vector3d omega);\nEigen::Vector3d convertRPYVelocityToOmega(Eigen::Vector3d rpy_vector, Eigen::Vector3d rpy_velocity);\nEigen::Vector3d convertOmegaDotToRPYAcceleration(Eigen::Vector3d rpy_vector, Eigen::Vector3d rpy_velocity, Eigen::Vector3d omega_dot);\nEigen::Vector3d convertRPYAccelerationToOmegaDot(Eigen::Vector3d rpy_vector, Eigen::Vector3d rpy_velocity, Eigen::Vector3d rpy_acceleration);\n\n\n/*****************************************************************************\n** Math\n*****************************************************************************/\ndouble sign(double value);\n\nEigen::Matrix4d inverseTransformationMatrix(const Eigen::MatrixXd& transformation_matrix);\nEigen::Vector3d matrixLogarithm(Eigen::Matrix3d rotation_matrix);\nEigen::Matrix3d skewSymmetricMatrix(Eigen::Vector3d v);\nEigen::Matrix3d rodriguesRotationMatrix(Eigen::Vector3d axis, double angle);\n\nEigen::Vector3d positionDifference(Eigen::Vector3d desired_position, Eigen::Vector3d present_position);\nEigen::Vector3d orientationDifference(Eigen::Matrix3d desired_orientation, Eigen::Matrix3d present_orientation);\nEigen::VectorXd poseDifference(Eigen::Vector3d desired_position, Eigen::Vector3d present_position,\n                        Eigen::Matrix3d desired_orientation, Eigen::Matrix3d present_orientation);\n\n} // math\n} // namespace robotis_manipulator\n\n#endif // ROBOTIS_MANIPULATOR_MATH_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RobotisManipulator/include/robotis_manipulator/robotis_manipulator_trajectory_generator.h",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#ifndef ROBOTIS_MNAMIPULATOR_TRAJECTORY_GENERATOR_H_\n#define ROBOTIS_MNAMIPULATOR_TRAJECTORY_GENERATOR_H_\n\n#include <math.h>\n#include <vector>\n\n#include \"robotis_manipulator_manager.h\"\n\n#if defined(__OPENCR__)\n  #include <Eigen.h>  // Calls main Eigen matrix class library\n  #include <Eigen/LU> // Calls inverse, determinant, LU decomp., etc.\n  #include <Eigen/QR>\n#else\n  #include <eigen3/Eigen/Eigen>\n  #include <eigen3/Eigen/LU>\n  #include <eigen3/Eigen/QR>\n\n  #define PI 3.141592\n#endif\n\nnamespace robotis_manipulator\n{\nclass MinimumJerk\n{\nprivate:\n  Eigen::VectorXd coefficient_;\n\npublic:\n  MinimumJerk();\n  virtual ~MinimumJerk();\n\n  void calcCoefficient(Point start,\n                       Point goal,\n                       double move_time);\n\n  Eigen::VectorXd getCoefficient();\n};\n\nclass JointTrajectory\n{\nprivate:\n  uint8_t coefficient_size_;\n  MinimumJerk minimum_jerk_trajectory_generator_;\n  Eigen::MatrixXd minimum_jerk_coefficient_;\n\npublic:\n  JointTrajectory();\n  virtual ~JointTrajectory();\n\n  void makeJointTrajectory(double move_time,\n            JointWaypoint start,\n            JointWaypoint goal\n            );\n  Eigen::MatrixXd getMinimumJerkCoefficient();\n  JointWaypoint getJointWaypoint(double tick);\n};\n\nclass TaskTrajectory\n{\nprivate:\n  uint8_t coefficient_size_;\n  MinimumJerk minimum_jerk_trajectory_generator_;\n  Eigen::MatrixXd minimum_jerk_coefficient_;\n\npublic:\n  TaskTrajectory();\n  virtual ~TaskTrajectory();\n\n  void makeTaskTrajectory(double move_time,\n            TaskWaypoint start,\n            TaskWaypoint goal\n            );\n  Eigen::MatrixXd getMinimumJerkCoefficient();\n  TaskWaypoint getTaskWaypoint(double tick);\n};\n\n\n/*****************************************************************************\n** Trajectory Class\n*****************************************************************************/\nclass Trajectory\n{\nprivate:\n  TrajectoryType trajectory_type_;\n  Time trajectory_time_;\n  Manipulator manipulator_;\n\n  JointTrajectory joint_;\n  TaskTrajectory task_;\n  std::map<Name, CustomJointTrajectory *> cus_joint_;\n  std::map<Name, CustomTaskTrajectory *> cus_task_;\n\n  Name present_custom_trajectory_name_;\n  Name present_control_tool_name_;\n\npublic:\n  Trajectory() {}\n  ~Trajectory() {}\n\n  // Time\n  void setMoveTime(double move_time);\n  void setPresentTime(double present_time);\n  void setStartTimeToPresentTime();\n  void setStartTime(double start_time);\n  double getMoveTime();\n  double getTickTime();\n\n  // Manipulator\n  void setManipulator(Manipulator manipulator);\n  Manipulator* getManipulator();\n\n  // Get Trajectory\n  JointTrajectory getJointTrajectory();\n  TaskTrajectory getTaskTrajectory();\n  CustomJointTrajectory* getCustomJointTrajectory(Name name);\n  CustomTaskTrajectory* getCustomTaskTrajectory(Name name);\n\n  // Custom Trajectory Setting\n  void addCustomTrajectory(Name trajectory_name, CustomJointTrajectory *custom_trajectory);\n  void addCustomTrajectory(Name trajectory_name, CustomTaskTrajectory *custom_trajectory);\n  void setCustomTrajectoryOption(Name trajectory_name, const void* arg);\n  void setPresentControlToolName(Name present_control_tool_name);\n  Name getPresentCustomTrajectoryName();\n  Name getPresentControlToolName();\n\n  // First Waypoint\n  void initTrajectoryWaypoint(Manipulator actual_manipulator, Kinematics *kinematics);\n\n  // Present Waypoint\n  void updatePresentWaypoint(Kinematics* kinematics); //forward kinematics,dynamics\n  void setPresentJointWaypoint(JointWaypoint joint_value_vector);\n  void setPresentTaskWaypoint(Name tool_name, TaskWaypoint tool_position_value_vector);\n  JointWaypoint getPresentJointWaypoint();\n  TaskWaypoint getPresentTaskWaypoint(Name tool_name);\n\n  JointWaypoint removeWaypointDynamicData(JointWaypoint value);\n  TaskWaypoint removeWaypointDynamicData(TaskWaypoint value);\n\n  // Trajectory\n  void setTrajectoryType(TrajectoryType trajectory_type);\n  bool checkTrajectoryType(TrajectoryType trajectory_type);\n  void makeJointTrajectory(JointWaypoint start_way_point, JointWaypoint goal_way_point);\n  void makeTaskTrajectory(TaskWaypoint start_way_point, TaskWaypoint goal_way_point);\n  void makeCustomTrajectory(Name trajectory_name, JointWaypoint start_way_point, const void *arg);\n  void makeCustomTrajectory(Name trajectory_name, TaskWaypoint start_way_point, const void *arg);\n\n  // Tool\n  void setToolGoalPosition(Name tool_name, double tool_goal_position);\n  void setToolGoalValue(Name tool_name, JointValue tool_goal_value);\n  double getToolGoalPosition(Name tool_name);\n  JointValue getToolGoalValue(Name tool_name);\n};\n\n} // namespace robotis_manipulator\n#endif // ROBOTIS_MNAMIPULATOR_TRAJECTORY_GENERATOR_H_\n\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RobotisManipulator/library.properties",
    "content": "name=RobotisManipulator\nversion=0.0.1\nauthor=\nmaintainer=Pyo(pyo@robotis.com)\nsentence=\nparagraph=\ncategory=Other\nurl=https://github.com/ROBOTIS-GIT/robotis_manipulator\narchitectures=OpenCR\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RobotisManipulator/src/RobotisManipulator.h",
    "content": "#include \"../include/robotis_manipulator/robotis_manipulator.h\""
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RobotisManipulator/src/robotis_manipulator/robotis_manipulator.cpp",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include \"../../include/robotis_manipulator/robotis_manipulator.h\"\n\nusing namespace robotis_manipulator;\n\n\n/*****************************************************************************\n** Constructor and Destructor\n*****************************************************************************/\nRobotisManipulator::RobotisManipulator()\n{\n  moving_state_ = false;\n  actuator_added_state_ = false;\n  step_moving_state_ = false;\n  trajectory_initialized_state_ = false;\n}\n\nRobotisManipulator::~RobotisManipulator() {}\n\n\n/*****************************************************************************\n** Initialize Function\n*****************************************************************************/\nvoid RobotisManipulator::addWorld(Name world_name,\n                           Name child_name,\n                           Eigen::Vector3d world_position,\n                           Eigen::Matrix3d world_orientation)\n{\n  manipulator_.addWorld(world_name, child_name, world_position, world_orientation);\n}\n\nvoid RobotisManipulator::addJoint(Name my_name,\n                                  Name parent_name,\n                                  Name child_name,\n                                  Eigen::Vector3d relative_position,\n                                  Eigen::Matrix3d relative_orientation,\n                                  Eigen::Vector3d axis_of_rotation,\n                                  int8_t joint_actuator_id,\n                                  double max_position_limit,\n                                  double min_position_limit,\n                                  double coefficient,\n                                  double mass,\n                                  Eigen::Matrix3d inertia_tensor,\n                                  Eigen::Vector3d center_of_mass)\n{\n  manipulator_.addJoint(my_name, parent_name, child_name, \n                        relative_position, relative_orientation, axis_of_rotation, joint_actuator_id, \n                        max_position_limit, min_position_limit, coefficient, mass, \n                        inertia_tensor, center_of_mass);\n}\n\nvoid RobotisManipulator::addComponentChild(Name my_name, Name child_name)\n{\n  manipulator_.addComponentChild(my_name, child_name);\n}\n\nvoid RobotisManipulator::addTool(Name my_name,\n                                 Name parent_name,\n                                 Eigen::Vector3d relative_position,\n                                 Eigen::Matrix3d relative_orientation,\n                                 int8_t tool_id,\n                                 double max_position_limit,\n                                 double min_position_limit,\n                                 double coefficient,\n                                 double mass,\n                                 Eigen::Matrix3d inertia_tensor,\n                                 Eigen::Vector3d center_of_mass)\n{\n  manipulator_.addTool(my_name, parent_name,\n                       relative_position, relative_orientation, tool_id, \n                       max_position_limit, min_position_limit, coefficient, mass,\n                       inertia_tensor, center_of_mass);\n}\n\nvoid RobotisManipulator::printManipulatorSetting()\n{\n  manipulator_.printManipulatorSetting();\n}\n\nvoid RobotisManipulator::addKinematics(Kinematics *kinematics)\n{\n  kinematics_= kinematics;\n}\n\nvoid RobotisManipulator::addJointActuator(Name actuator_name, JointActuator *joint_actuator, std::vector<uint8_t> id_array, const void *arg)\n{\n  joint_actuator_.insert(std::make_pair(actuator_name, joint_actuator));\n  if(joint_actuator_.find(actuator_name) != joint_actuator_.end())\n  {\n    joint_actuator_.at(actuator_name)->init(id_array, arg);\n  }\n  else\n  {\n    //error\n  }\n  for(uint32_t index = 0; index < id_array.size(); index++)\n  {\n    manipulator_.setComponentActuatorName(manipulator_.findComponentNameUsingId(id_array.at(index)),actuator_name);\n  }\n  actuator_added_state_ = true;\n}\n\nvoid RobotisManipulator::addToolActuator(Name actuator_name, ToolActuator *tool_actuator, uint8_t id, const void *arg)\n{\n  tool_actuator_.insert(std::make_pair(actuator_name, tool_actuator));\n  if(tool_actuator_.find(actuator_name) != tool_actuator_.end())\n  {\n    tool_actuator_.at(actuator_name)->init(id, arg);\n  }\n  else\n  {\n    //error\n  }\n  manipulator_.setComponentActuatorName(manipulator_.findComponentNameUsingId(id),actuator_name);\n  actuator_added_state_ = true;\n}\n\nvoid RobotisManipulator::addCustomTrajectory(Name trajectory_name, CustomJointTrajectory *custom_trajectory)\n{\n  trajectory_.addCustomTrajectory(trajectory_name, custom_trajectory);\n}\n\nvoid RobotisManipulator::addCustomTrajectory(Name trajectory_name, CustomTaskTrajectory *custom_trajectory)\n{\n  trajectory_.addCustomTrajectory(trajectory_name, custom_trajectory);\n}\n\n\n/*****************************************************************************\n** Manipulator Function\n*****************************************************************************/\nManipulator *RobotisManipulator::getManipulator()\n{\n  return &manipulator_;\n}\n\nJointValue RobotisManipulator::getJointValue(Name joint_name)\n{\n  return manipulator_.getJointValue(joint_name);\n}\n\nJointValue RobotisManipulator::getToolValue(Name tool_name)\n{\n  return manipulator_.getJointValue(tool_name);\n}\n\nstd::vector<JointValue> RobotisManipulator::getAllActiveJointValue()\n{\n  return manipulator_.getAllActiveJointValue();\n}\n\nstd::vector<JointValue> RobotisManipulator::getAllJointValue()\n{\n  return manipulator_.getAllJointValue();\n}\n\nstd::vector<double> RobotisManipulator::getAllToolPosition()\n{\n  return manipulator_.getAllToolPosition();\n}\n\nstd::vector<JointValue> RobotisManipulator::getAllToolValue()\n{\n  return manipulator_.getAllToolValue();\n}\n\nKinematicPose RobotisManipulator::getKinematicPose(Name component_name)\n{\n  return manipulator_.getComponentKinematicPoseFromWorld(component_name);\n}\n\nDynamicPose RobotisManipulator::getDynamicPose(Name component_name)\n{\n  return manipulator_.getComponentDynamicPoseFromWorld(component_name);\n}\n\nPose RobotisManipulator::getPose(Name component_name)\n{\n  return manipulator_.getComponentPoseFromWorld(component_name);\n}\n\n\n/*****************************************************************************\n** Kinematics Function (Including Virtual Function)\n*****************************************************************************/\nEigen::MatrixXd RobotisManipulator::jacobian(Name tool_name)\n{\n  return kinematics_->jacobian(&manipulator_, tool_name);\n}\n\nvoid RobotisManipulator::solveForwardKinematics()\n{\n  return kinematics_->solveForwardKinematics(&manipulator_);\n}\n\nbool RobotisManipulator::solveInverseKinematics(Name tool_name, Pose goal_pose, std::vector<JointValue>* goal_joint_value)\n{\n  return kinematics_->solveInverseKinematics(&manipulator_, tool_name, goal_pose, goal_joint_value);\n}\n\nvoid RobotisManipulator::setKinematicsOption(const void* arg)\n{\n  kinematics_->setOption(arg);\n}\n\n\n/*****************************************************************************\n** Actuator Function (Including Virtual Function)\n*****************************************************************************/\nvoid RobotisManipulator::setJointActuatorMode(Name actuator_name, std::vector<uint8_t> id_array, const void *arg)\n{\n  if(actuator_added_state_)\n  {\n    if(joint_actuator_.find(actuator_name) != joint_actuator_.end())\n    {\n      joint_actuator_.at(actuator_name)->setMode(id_array, arg);\n    }\n    else\n    {\n      robotis_manipulator::log::error(\"[jointActuatorSetMode] Worng Actuator Name.\");\n    }\n  }\n}\n\nvoid RobotisManipulator::setToolActuatorMode(Name actuator_name, const void *arg)\n{\n  if(actuator_added_state_)\n  {\n    if(tool_actuator_.find(actuator_name) != tool_actuator_.end())\n    {\n      tool_actuator_.at(actuator_name)->setMode(arg);\n    }\n    else\n    {\n      //error\n    }\n  }\n}\n\nstd::vector<uint8_t> RobotisManipulator::getJointActuatorId(Name actuator_name)\n{\n  if(actuator_added_state_)\n  {\n    if(joint_actuator_.find(actuator_name) != joint_actuator_.end())\n    {\n      return joint_actuator_.at(actuator_name)->getId();\n    }\n    else\n    {\n      //error\n    }\n  }\n  return {};\n}\n\nuint8_t RobotisManipulator::getToolActuatorId(Name actuator_name)\n{\n  if(actuator_added_state_)\n  {\n    if(tool_actuator_.find(actuator_name) != tool_actuator_.end())\n    {\n      return tool_actuator_.at(actuator_name)->getId();\n    }\n    else\n    {\n      //error\n    }\n  }\n  return {};\n}\n\nvoid RobotisManipulator::enableActuator(Name actuator_name)\n{\n  if(actuator_added_state_)\n  {\n    if(joint_actuator_.find(actuator_name) != joint_actuator_.end())\n    {\n      joint_actuator_.at(actuator_name)->enable();\n    }\n    else if(tool_actuator_.find(actuator_name) != tool_actuator_.end())\n    {\n      tool_actuator_.at(actuator_name)->enable();\n    }\n    else\n    {\n      //error\n    }\n  }\n  trajectory_initialized_state_ = false;\n}\n\nvoid RobotisManipulator::disableActuator(Name actuator_name)\n{\n  if(actuator_added_state_)\n  {\n    if(joint_actuator_.find(actuator_name) != joint_actuator_.end())\n    {\n      joint_actuator_.at(actuator_name)->disable();\n    }\n    else if(tool_actuator_.find(actuator_name) != tool_actuator_.end())\n    {\n      tool_actuator_.at(actuator_name)->disable();\n    }\n    else\n    {\n      //error\n    }\n  }\n}\n\nvoid RobotisManipulator::enableAllJointActuator()\n{\n  if(actuator_added_state_)\n  {\n    std::map<Name, JointActuator *>::iterator it_joint_actuator;\n    for(it_joint_actuator = joint_actuator_.begin(); it_joint_actuator != joint_actuator_.end(); it_joint_actuator++)\n    {\n      joint_actuator_.at(it_joint_actuator->first)->enable();\n    }\n  }\n  trajectory_initialized_state_ = false;\n}\n\nvoid RobotisManipulator::disableAllJointActuator()\n{\n  if(actuator_added_state_)\n  {\n    std::map<Name, JointActuator *>::iterator it_joint_actuator;\n    for(it_joint_actuator = joint_actuator_.begin(); it_joint_actuator != joint_actuator_.end(); it_joint_actuator++)\n    {\n      joint_actuator_.at(it_joint_actuator->first)->disable();\n    }\n  }\n}\n\nvoid RobotisManipulator::enableAllToolActuator()\n{\n  if(actuator_added_state_)\n  {\n    std::map<Name, ToolActuator *>::iterator it_tool_actuator;\n    for(it_tool_actuator = tool_actuator_.begin(); it_tool_actuator != tool_actuator_.end(); it_tool_actuator++)\n    {\n      tool_actuator_.at(it_tool_actuator->first)->enable();\n    }\n  }\n  trajectory_initialized_state_ = false;\n}\n\nvoid RobotisManipulator::disableAllToolActuator()\n{\n  if(actuator_added_state_)\n  {\n    std::map<Name, ToolActuator *>::iterator it_tool_actuator;\n    for(it_tool_actuator = tool_actuator_.begin(); it_tool_actuator != tool_actuator_.end(); it_tool_actuator++)\n    {\n      tool_actuator_.at(it_tool_actuator->first)->disable();\n    }\n  }\n}\n\nvoid RobotisManipulator::enableAllActuator()\n{\n  if(actuator_added_state_)\n  {\n    std::map<Name, JointActuator *>::iterator it_joint_actuator;\n    for(it_joint_actuator = joint_actuator_.begin(); it_joint_actuator != joint_actuator_.end(); it_joint_actuator++)\n    {\n      joint_actuator_.at(it_joint_actuator->first)->enable();\n    }\n    std::map<Name, ToolActuator *>::iterator it_tool_actuator;\n    for(it_tool_actuator = tool_actuator_.begin(); it_tool_actuator != tool_actuator_.end(); it_tool_actuator++)\n    {\n      tool_actuator_.at(it_tool_actuator->first)->enable();\n    }\n  }\n  trajectory_initialized_state_ = false;\n}\n\nvoid RobotisManipulator::disableAllActuator()\n{\n  if(actuator_added_state_)\n  {\n    std::map<Name, JointActuator *>::iterator it_joint_actuator;\n    for(it_joint_actuator = joint_actuator_.begin(); it_joint_actuator != joint_actuator_.end(); it_joint_actuator++)\n    {\n      joint_actuator_.at(it_joint_actuator->first)->disable();\n    }\n    std::map<Name, ToolActuator *>::iterator it_tool_actuator;\n    for(it_tool_actuator = tool_actuator_.begin(); it_tool_actuator != tool_actuator_.end(); it_tool_actuator++)\n    {\n      tool_actuator_.at(it_tool_actuator->first)->disable();\n    }\n  }\n}\n\nbool RobotisManipulator::getActuatorEnabledState(Name actuator_name)\n{\n  if(actuator_added_state_)\n  {\n    if(joint_actuator_.find(actuator_name) != joint_actuator_.end())\n    {\n      return joint_actuator_.at(actuator_name)->getEnabledState();\n    }\n    else if(tool_actuator_.find(actuator_name) != tool_actuator_.end())\n    {\n      return tool_actuator_.at(actuator_name)->getEnabledState();\n    }\n    else\n    {\n      return {};\n    }\n  }\n  return {};\n}\n\nbool RobotisManipulator::sendJointActuatorValue(Name joint_component_name, JointValue value)\n{\n  // trajectory manipulator set\n  // trajectory_.getManipulator()->setJointValue(joint_component_name,value);\n  // trajectory_.updatePresentWayPoint(kinematics_dynamics_);\n\n  if(actuator_added_state_)\n  {\n    double coefficient = manipulator_.getCoefficient(joint_component_name);\n    value.position = value.position / coefficient;\n    value.velocity = value.velocity / coefficient;\n    value.acceleration = value.acceleration / coefficient;\n    value.effort = value.effort;\n\n    std::vector<uint8_t> id;\n    std::vector<JointValue> value_vector;\n    id.push_back(manipulator_.getId(joint_component_name));\n    value_vector.push_back(value);\n\n    //send to actuator\n    return joint_actuator_.at(manipulator_.getComponentActuatorName(joint_component_name))->sendJointActuatorValue(id, value_vector);\n  }\n  else\n  {\n    manipulator_.setJointValue(joint_component_name, value);\n    return true;\n  }\n  return false;\n}\n\nbool RobotisManipulator::sendMultipleJointActuatorValue(std::vector<Name> joint_component_name, std::vector<JointValue> value_vector)\n{\n  if(joint_component_name.size() != value_vector.size())\n    return false; //error;\n\n  // trajectory manipulator set\n  // for(uint8_t index = 0; index < joint_component_name.size(); index++)\n  //   trajectory_.getManipulator()->setJointValue(joint_component_name.at(index), value_vector.at(index));\n  // trajectory_.updatePresentWayPoint(kinematics_dynamics_);\n\n  if(actuator_added_state_)\n  {\n    std::vector<int8_t> joint_id;\n    for(uint32_t index = 0; index < value_vector.size(); index++)\n    {\n      double coefficient = manipulator_.getCoefficient(joint_component_name.at(index));\n      value_vector.at(index).position = value_vector.at(index).position / coefficient;\n      value_vector.at(index).velocity = value_vector.at(index).velocity / coefficient;\n      value_vector.at(index).acceleration = value_vector.at(index).acceleration / coefficient;\n      value_vector.at(index).effort = value_vector.at(index).effort;\n      joint_id.push_back(manipulator_.getId(joint_component_name.at(index)));\n    }\n\n    std::vector<uint8_t> single_actuator_id;\n    std::vector<JointValue> single_value_vector;\n    std::map<Name, JointActuator *>::iterator it_joint_actuator;\n    for(it_joint_actuator = joint_actuator_.begin(); it_joint_actuator != joint_actuator_.end(); it_joint_actuator++)\n    {\n      single_actuator_id = joint_actuator_.at(it_joint_actuator->first)->getId();\n      for(uint32_t index = 0; index < single_actuator_id.size(); index++)\n      {\n        for(uint32_t index2=0; index2 < joint_id.size(); index2++)\n        {\n           if(single_actuator_id.at(index) == joint_id.at(index2))\n           {\n             single_value_vector.push_back(value_vector.at(index2));\n           }\n        }\n      }\n      joint_actuator_.at(it_joint_actuator->first)->sendJointActuatorValue(single_actuator_id, single_value_vector);\n    }\n    return true;\n  }\n  else\n  {\n    //set to manipulator\n    for(uint8_t index = 0; index < joint_component_name.size(); index++)\n      manipulator_.setJointValue(joint_component_name.at(index), value_vector.at(index));\n    return true;\n  }\n  return false;\n}\n\nbool RobotisManipulator::sendAllJointActuatorValue(std::vector<JointValue> value_vector)\n{\n  // trajectory manipulator set\n  // trajectory_.setPresentJointWayPoint(value_vector);\n  // trajectory_.updatePresentWayPoint(kinematics_dynamics_);\n\n  if(actuator_added_state_)\n  {\n    std::map<Name, Component>::iterator it;\n    std::vector<int8_t> joint_id;\n    int index = 0;\n    for (it = manipulator_.getIteratorBegin(); it != manipulator_.getIteratorEnd(); it++)\n    {\n      if(manipulator_.checkComponentType(it->first, ACTIVE_JOINT_COMPONENT))\n      {\n        double coefficient = manipulator_.getCoefficient(it->first);\n        value_vector.at(index).position = value_vector.at(index).position / coefficient;\n        value_vector.at(index).velocity = value_vector.at(index).velocity / coefficient;\n        value_vector.at(index).acceleration = value_vector.at(index).acceleration / coefficient;\n        value_vector.at(index).effort = value_vector.at(index).effort;\n        joint_id.push_back(manipulator_.getId(it->first));\n        index++;\n      }\n    }\n\n    std::vector<uint8_t> single_actuator_id;\n    std::vector<JointValue> single_value_vector;\n    std::map<Name, JointActuator *>::iterator it_joint_actuator;\n    for(it_joint_actuator = joint_actuator_.begin(); it_joint_actuator != joint_actuator_.end(); it_joint_actuator++)\n    {\n      single_actuator_id = joint_actuator_.at(it_joint_actuator->first)->getId();\n      for(uint32_t index = 0; index < single_actuator_id.size(); index++)\n      {\n        for(uint32_t index2=0; index2 < joint_id.size(); index2++)\n        {\n           if(single_actuator_id.at(index) == joint_id.at(index2))\n           {\n             single_value_vector.push_back(value_vector.at(index2));\n           }\n        }\n      }\n      joint_actuator_.at(it_joint_actuator->first)->sendJointActuatorValue(single_actuator_id, single_value_vector);\n    }\n    return true;\n  }\n  else\n  {\n    //set to manipulator\n    manipulator_.setAllActiveJointValue(value_vector);\n  }\n  return false;\n}\n\nJointValue RobotisManipulator::receiveJointActuatorValue(Name joint_component_name)\n{\n  if(actuator_added_state_)\n  {\n    std::vector<uint8_t> actuator_id;\n    std::vector<JointValue> result;\n\n    actuator_id.push_back(manipulator_.getId(joint_component_name));\n\n    result = joint_actuator_.at(manipulator_.getComponentActuatorName(joint_component_name))->receiveJointActuatorValue(actuator_id);\n\n    double coefficient = manipulator_.getCoefficient(joint_component_name);\n    result.at(0).position = result.at(0).position * coefficient;\n    result.at(0).velocity = result.at(0).velocity * coefficient;\n    result.at(0).acceleration = result.at(0).acceleration * coefficient;\n    result.at(0).effort = result.at(0).effort;\n\n    manipulator_.setJointValue(joint_component_name, result.at(0));\n    return result.at(0);\n  }\n  return {};\n}\n\nstd::vector<JointValue> RobotisManipulator::receiveMultipleJointActuatorValue(std::vector<Name> joint_component_name)\n{\n  if(actuator_added_state_)\n  {\n    std::vector<JointValue> get_value_vector;\n    std::vector<uint8_t> get_actuator_id;\n\n    std::vector<JointValue> single_value_vector;\n    std::vector<uint8_t> single_actuator_id;\n    std::map<Name, JointActuator *>::iterator it_joint_actuator;\n    for(it_joint_actuator = joint_actuator_.begin(); it_joint_actuator != joint_actuator_.end(); it_joint_actuator++)\n    {\n      single_actuator_id = joint_actuator_.at(it_joint_actuator->first)->getId();\n      single_value_vector = joint_actuator_.at(it_joint_actuator->first)->receiveJointActuatorValue(single_actuator_id);\n      for(uint32_t index=0; index < single_actuator_id.size(); index++)\n      {\n        get_actuator_id.push_back(single_actuator_id.at(index));\n        get_value_vector.push_back(single_value_vector.at(index));\n      }\n    }\n\n    std::vector<JointValue> result_vector;\n    JointValue result;\n\n    for(uint32_t index = 0; index < joint_component_name.size(); index++)\n    {\n      for(uint32_t index2 = 0; index2 < get_actuator_id.size(); index2++)\n      {\n        if(manipulator_.getId(joint_component_name.at(index)) == get_actuator_id.at(index2))\n        {\n          double coefficient = manipulator_.getCoefficient(joint_component_name.at(index));\n          result.position = get_value_vector.at(index2).position * coefficient;\n          result.velocity = get_value_vector.at(index2).velocity * coefficient;\n          result.acceleration = get_value_vector.at(index2).acceleration * coefficient;\n          result.effort = get_value_vector.at(index2).effort;\n          manipulator_.setJointValue(joint_component_name.at(index), result);\n          result_vector.push_back(result);\n        }\n      }\n    }\n\n    return result_vector;\n  }\n  return {};\n}\n\nstd::vector<JointValue> RobotisManipulator::receiveAllJointActuatorValue()\n{\n  if(actuator_added_state_)\n  {\n    std::vector<JointValue> get_value_vector;\n    std::vector<uint8_t> get_actuator_id;\n\n    std::vector<JointValue> single_value_vector;\n    std::vector<uint8_t> single_actuator_id;\n    std::map<Name, JointActuator *>::iterator it_joint_actuator;\n    for(it_joint_actuator = joint_actuator_.begin(); it_joint_actuator != joint_actuator_.end(); it_joint_actuator++)\n    {\n      single_actuator_id = joint_actuator_.at(it_joint_actuator->first)->getId();\n      single_value_vector = joint_actuator_.at(it_joint_actuator->first)->receiveJointActuatorValue(single_actuator_id);\n      for(uint32_t index=0; index < single_actuator_id.size(); index++)\n      {\n        get_actuator_id.push_back(single_actuator_id.at(index));\n        get_value_vector.push_back(single_value_vector.at(index));\n      }\n    }\n\n    std::map<Name, Component>::iterator it;\n    std::vector<JointValue> result_vector;\n    JointValue result;\n\n    for (it = manipulator_.getIteratorBegin(); it != manipulator_.getIteratorEnd(); it++)\n    {\n      for(uint32_t index2 = 0; index2 < get_actuator_id.size(); index2++)\n      {\n        if(manipulator_.checkComponentType(it->first,ACTIVE_JOINT_COMPONENT) && manipulator_.getId(it->first) == get_actuator_id.at(index2))\n        {\n          double coefficient = manipulator_.getCoefficient(it->first);\n          result.position = get_value_vector.at(index2).position * coefficient;\n          result.velocity = get_value_vector.at(index2).velocity * coefficient;\n          result.acceleration = get_value_vector.at(index2).acceleration * coefficient;\n          result.effort = get_value_vector.at(index2).effort;\n          manipulator_.setJointValue(it->first, result);\n          result_vector.push_back(result);\n        }\n      }\n    }\n\n    return result_vector;\n  }\n  return {};\n}\n/////////////////////////////////////////\n\nbool RobotisManipulator::sendToolActuatorValue(Name tool_component_name, JointValue value)\n{\n  // trajectory manipulator set\n  // trajectory_.getManipulator()->setJointValue(tool_component_name,value);\n\n  if(actuator_added_state_)\n  {\n    double coefficient;\n    coefficient = manipulator_.getCoefficient(tool_component_name);\n    value.position = value.position / coefficient;\n    value.velocity = value.velocity / coefficient;\n    value.acceleration = value.acceleration / coefficient;\n    value.effort = value.effort;\n\n    return tool_actuator_.at(manipulator_.getComponentActuatorName(tool_component_name))->sendToolActuatorValue(value);\n  }\n  else\n  {\n    //set to manipulator\n    manipulator_.setJointValue(tool_component_name, value);\n    return true;\n  }\n  return false;\n}\n\nbool RobotisManipulator::sendMultipleToolActuatorValue(std::vector<Name> tool_component_name, std::vector<JointValue> value_vector)\n{\n  // trajectory manipulator set\n  // for(uint8_t index = 0; index < tool_component_name.size(); index++)\n  //   trajectory_.getManipulator()->setJointValue(tool_component_name.at(index), value_vector.at(index));\n\n  if(actuator_added_state_)\n  {\n    for (uint32_t index = 0; index < tool_component_name.size(); index++)\n    {\n      double coefficient = manipulator_.getCoefficient(tool_component_name.at(index));\n      value_vector.at(index).position = value_vector.at(index).position / coefficient;\n      value_vector.at(index).velocity = value_vector.at(index).velocity / coefficient;\n      value_vector.at(index).acceleration = value_vector.at(index).acceleration / coefficient;\n\n      if(!tool_actuator_.at(manipulator_.getComponentActuatorName(tool_component_name.at(index)))->sendToolActuatorValue(value_vector.at(index)))\n        return false;\n    }\n    return true;\n  }\n  else\n  {\n    //set to manipulator\n    for(uint8_t index = 0; index < tool_component_name.size(); index++)\n      manipulator_.setJointValue(tool_component_name.at(index), value_vector.at(index));\n    return true;\n  }\n  return false;\n}\n\nbool RobotisManipulator::sendAllToolActuatorValue(std::vector<JointValue> value_vector)\n{\n  // trajectory manipulator set\n  // trajectory_.getManipulator()->setAllToolValue(value_vector);\n\n  if(actuator_added_state_)\n  {\n    std::vector<Name> tool_component_name;\n    tool_component_name = manipulator_.getAllToolComponentName();\n    for (uint32_t index = 0; index < tool_component_name.size(); index++)\n    {\n      double coefficient = manipulator_.getCoefficient(tool_component_name.at(index));\n      value_vector.at(index).position = value_vector.at(index).position / coefficient;\n      value_vector.at(index).velocity = value_vector.at(index).velocity / coefficient;\n      value_vector.at(index).acceleration = value_vector.at(index).acceleration / coefficient;\n\n      if(!tool_actuator_.at(manipulator_.getComponentActuatorName(tool_component_name.at(index)))->sendToolActuatorValue(value_vector.at(index)))\n        return false;\n    }\n    return true;\n  }\n  else\n  {\n    //set to manipualtor\n    manipulator_.setAllToolValue(value_vector);\n  }\n  return false;\n}\n\nJointValue RobotisManipulator::receiveToolActuatorValue(Name tool_component_name)\n{\n  if(actuator_added_state_)\n  {\n    JointValue result;\n    result = tool_actuator_.at(manipulator_.getComponentActuatorName(tool_component_name))->receiveToolActuatorValue();\n\n    double coefficient = manipulator_.getCoefficient(tool_component_name);\n    result.position = result.position * coefficient;\n    result.velocity = result.velocity * coefficient;\n    result.acceleration = result.acceleration * coefficient;\n\n    manipulator_.setJointValue(tool_component_name, result);\n    return result;\n  }\n  return {};\n}\n\nstd::vector<JointValue> RobotisManipulator::receiveMultipleToolActuatorValue(std::vector<Name> tool_component_name)\n{\n  if(actuator_added_state_)\n  {\n    std::vector<JointValue> result_vector;\n    ActuatorValue result;\n    for (uint32_t index = 0; index < tool_component_name.size(); index++)\n    {\n      result = tool_actuator_.at(manipulator_.getComponentActuatorName(tool_component_name.at(index)))->receiveToolActuatorValue();\n\n      double coefficient = manipulator_.getCoefficient(tool_component_name.at(index));\n      result.position = result.position * coefficient;\n      result.velocity = result.velocity * coefficient;\n      result.acceleration = result.acceleration * coefficient;\n\n      manipulator_.setJointValue(tool_component_name.at(index), result);\n      result_vector.push_back(result);\n    }\n    return result_vector;\n  }\n  return {};\n}\n\nstd::vector<JointValue> RobotisManipulator::receiveAllToolActuatorValue()\n{\n  if(actuator_added_state_)\n  {\n    std::vector<Name> tool_component_name;\n    tool_component_name = manipulator_.getAllToolComponentName();\n    std::vector<JointValue> result_vector;\n    ActuatorValue result;\n    for (uint32_t index = 0; index < tool_component_name.size(); index++)\n    {\n      result = tool_actuator_.at(manipulator_.getComponentActuatorName(tool_component_name.at(index)))->receiveToolActuatorValue();\n\n      double coefficient = manipulator_.getCoefficient(tool_component_name.at(index));\n      result.position = result.position * coefficient;\n      result.velocity = result.velocity * coefficient;\n      result.acceleration = result.acceleration * coefficient;\n\n      manipulator_.setJointValue(tool_component_name.at(index), result);\n      result_vector.push_back(result);\n    }\n    return result_vector;\n  }\n  return {};\n}\n\n\n\n/*****************************************************************************\n** Time Function\n*****************************************************************************/\nvoid RobotisManipulator::startMoving()      //Private\n{\n  moving_state_ = true;\n  trajectory_.setStartTimeToPresentTime();\n}\n\ndouble RobotisManipulator::getTrajectoryMoveTime()\n{\n  return trajectory_.getMoveTime();\n}\n\nbool RobotisManipulator::getMovingState()\n{\n  return moving_state_;\n}\n\n\n/*****************************************************************************\n** Check Joint Limit Function\n*****************************************************************************/\nbool RobotisManipulator::checkJointLimit(Name component_name, double joint_position)\n{\n  if(trajectory_.getManipulator()->checkJointLimit(component_name, joint_position))\n    return true;\n  else\n  {\n    log::error(\"[checkJointLimit] Goal value exceeded limit at \" + STRING(component_name) + \".\");\n    return false;\n  }\n}\n\nbool RobotisManipulator::checkJointLimit(Name component_name, JointValue value)\n{\n  if(trajectory_.getManipulator()->checkJointLimit(component_name, value.position))\n    return true;\n  else\n  {\n    log::error(\"[checkJointLimit] Goal value exceeded limit at \" + STRING(component_name) + \".\");\n    return false;\n  }\n}\n\nbool RobotisManipulator::checkJointLimit(std::vector<Name> component_name, std::vector<double> position_vector)\n{\n  for(uint32_t index = 0; index < component_name.size(); index++)\n  {\n    if(!trajectory_.getManipulator()->checkJointLimit(component_name.at(index), position_vector.at(index)))\n    {\n      log::error(\"[checkJointLimit] Goal value exceeded limit at \" + STRING(component_name.at(index)) + \".\");\n      return false;\n    }\n  }\n  return true;\n}\n\nbool RobotisManipulator::checkJointLimit(std::vector<Name> component_name, std::vector<JointValue> value_vector)\n{\n  for(uint32_t index = 0; index < component_name.size(); index++)\n  {\n    if(!trajectory_.getManipulator()->checkJointLimit(component_name.at(index), value_vector.at(index).position))\n    {\n      log::error(\"[checkJointLimit] Goal value exceeded limit at \" + STRING(component_name.at(index)) + \".\");\n      return false;\n    }\n  }\n  return true;\n}\n\n\n/*****************************************************************************\n** Trajectory Control Fuction\n*****************************************************************************/\nTrajectory *RobotisManipulator::getTrajectory()\n{\n  return &trajectory_;\n}\n\nvoid RobotisManipulator::makeJointTrajectoryFromPresentPosition(std::vector<double> delta_goal_joint_position, double move_time, std::vector<JointValue> present_joint_value)\n{\n  if(present_joint_value.size() != 0)\n  {\n    trajectory_.setPresentJointWaypoint(present_joint_value);\n    trajectory_.updatePresentWaypoint(kinematics_);\n  }\n\n  JointWaypoint present_way_point = trajectory_.getPresentJointWaypoint();\n  std::vector<double> goal_joint_position;\n  for(int i = 0; i < trajectory_.getManipulator()->getDOF(); i ++)\n    goal_joint_position.push_back(present_way_point.at(i).position + delta_goal_joint_position.at(i));\n\n  makeJointTrajectory(goal_joint_position, move_time);\n}\n\nvoid RobotisManipulator::makeJointTrajectory(std::vector<double> goal_joint_position, double move_time, std::vector<JointValue> present_joint_value)\n{\n  trajectory_.setTrajectoryType(JOINT_TRAJECTORY);\n  trajectory_.setMoveTime(move_time);\n\n  if(present_joint_value.size() != 0)\n  {\n    trajectory_.setPresentJointWaypoint(present_joint_value);\n    trajectory_.updatePresentWaypoint(kinematics_);\n  }\n\n  JointWaypoint present_way_point = trajectory_.getPresentJointWaypoint();\n\n  JointValue goal_way_point_temp;\n  JointWaypoint goal_way_point;\n  for (uint8_t index = 0; index < trajectory_.getManipulator()->getDOF(); index++)\n  {\n    goal_way_point_temp.position = goal_joint_position.at(index);\n    goal_way_point_temp.velocity = 0.0;\n    goal_way_point_temp.acceleration = 0.0;\n    goal_way_point_temp.effort = 0.0;\n\n    goal_way_point.push_back(goal_way_point_temp);\n  }\n\n  if(getMovingState())\n  {\n    moving_state_=false;\n    while(!step_moving_state_);\n  }\n  trajectory_.makeJointTrajectory(present_way_point, goal_way_point);\n  startMoving();\n}\n\nvoid RobotisManipulator::makeJointTrajectory(std::vector<JointValue> goal_joint_value, double move_time, std::vector<JointValue> present_joint_value)\n{\n  trajectory_.setTrajectoryType(JOINT_TRAJECTORY);\n  trajectory_.setMoveTime(move_time);\n\n  if(present_joint_value.size() != 0)\n  {\n    trajectory_.setPresentJointWaypoint(present_joint_value);\n    trajectory_.updatePresentWaypoint(kinematics_);\n  }\n\n  JointWaypoint present_way_point = trajectory_.getPresentJointWaypoint();\n\n  if(getMovingState())\n  {\n    moving_state_=false;\n    while(!step_moving_state_);\n  }\n  trajectory_.makeJointTrajectory(present_way_point, goal_joint_value);\n  startMoving();\n}\n\nvoid RobotisManipulator::makeJointTrajectory(Name tool_name, Eigen::Vector3d goal_position, double move_time, std::vector<JointValue> present_joint_value)\n{\n  if(present_joint_value.size() != 0)\n  {\n    trajectory_.setPresentJointWaypoint(present_joint_value);\n    trajectory_.updatePresentWaypoint(kinematics_);\n  }\n\n  KinematicPose goal_pose;\n\n  goal_pose.position = goal_position;\n  goal_pose.orientation = trajectory_.getManipulator()->getComponentOrientationFromWorld(tool_name);\n  makeJointTrajectory(tool_name, goal_pose, move_time);\n}\n\nvoid RobotisManipulator::makeJointTrajectory(Name tool_name, Eigen::Matrix3d goal_orientation, double move_time, std::vector<JointValue> present_joint_value)\n{\n  if(present_joint_value.size() != 0)\n  {\n    trajectory_.setPresentJointWaypoint(present_joint_value);\n    trajectory_.updatePresentWaypoint(kinematics_);\n  }\n\n  KinematicPose goal_pose;\n\n  goal_pose.position = trajectory_.getManipulator()->getComponentPositionFromWorld(tool_name);\n  goal_pose.orientation = goal_orientation;\n  makeJointTrajectory(tool_name, goal_pose, move_time);\n}\n\nvoid RobotisManipulator::makeJointTrajectory(Name tool_name, KinematicPose goal_pose, double move_time, std::vector<JointValue> present_joint_value)\n{\n  if(present_joint_value.size() != 0)\n  {\n    trajectory_.setPresentJointWaypoint(present_joint_value);\n    trajectory_.updatePresentWaypoint(kinematics_);\n  }\n\n  trajectory_.setTrajectoryType(JOINT_TRAJECTORY);\n  trajectory_.setMoveTime(move_time);\n\n  JointWaypoint present_way_point = trajectory_.getPresentJointWaypoint();\n\n  Pose temp_goal_pose;\n  temp_goal_pose.kinematic = goal_pose;\n  temp_goal_pose = trajectory_.removeWaypointDynamicData(temp_goal_pose);\n  std::vector<JointValue> goal_joint_angle;\n  if(kinematics_->solveInverseKinematics(trajectory_.getManipulator(), tool_name, temp_goal_pose, &goal_joint_angle))\n  {\n    if(getMovingState())\n    {\n      moving_state_=false;\n      while(!step_moving_state_) ;\n    }\n    trajectory_.makeJointTrajectory(present_way_point, goal_joint_angle);\n    startMoving();\n  }\n  else\n    log::error(\"[JOINT_TRAJECTORY] Fail to solve IK\");\n}\n\nvoid RobotisManipulator::makeTaskTrajectoryFromPresentPose(Name tool_name, Eigen::Vector3d position_meter, double move_time, std::vector<JointValue> present_joint_value)\n{\n  if(present_joint_value.size() != 0)\n  {\n    trajectory_.setPresentJointWaypoint(present_joint_value);\n    trajectory_.updatePresentWaypoint(kinematics_);\n  }\n\n  KinematicPose goal_pose;\n\n  goal_pose.position = trajectory_.getManipulator()->getComponentPositionFromWorld(tool_name) + position_meter;\n  goal_pose.orientation = trajectory_.getManipulator()->getComponentOrientationFromWorld(tool_name);\n  makeTaskTrajectory(tool_name, goal_pose, move_time);\n}\n\nvoid RobotisManipulator::makeTaskTrajectoryFromPresentPose(Name tool_name, Eigen::Matrix3d orientation_meter, double move_time, std::vector<JointValue> present_joint_value)\n{\n  if(present_joint_value.size() != 0)\n  {\n    trajectory_.setPresentJointWaypoint(present_joint_value);\n    trajectory_.updatePresentWaypoint(kinematics_);\n  }\n\n  KinematicPose goal_pose;\n\n  goal_pose.position = trajectory_.getManipulator()->getComponentPositionFromWorld(tool_name);\n  goal_pose.orientation = orientation_meter * trajectory_.getManipulator()->getComponentOrientationFromWorld(tool_name);\n  makeTaskTrajectory(tool_name, goal_pose, move_time);\n}\n\nvoid RobotisManipulator::makeTaskTrajectoryFromPresentPose(Name tool_name, KinematicPose goal_pose_delta, double move_time, std::vector<JointValue> present_joint_value)\n{\n  if(present_joint_value.size() != 0)\n  {\n    trajectory_.setPresentJointWaypoint(present_joint_value);\n    trajectory_.updatePresentWaypoint(kinematics_);\n  }\n\n  KinematicPose goal_pose;\n\n  goal_pose.position = trajectory_.getManipulator()->getComponentPositionFromWorld(tool_name) + goal_pose_delta.position;\n  goal_pose.orientation = goal_pose_delta.orientation * trajectory_.getManipulator()->getComponentOrientationFromWorld(tool_name);\n  makeTaskTrajectory(tool_name, goal_pose, move_time);\n}\n\nvoid RobotisManipulator::makeTaskTrajectory(Name tool_name, Eigen::Vector3d goal_position, double move_time, std::vector<JointValue> present_joint_value)\n{\n  if(present_joint_value.size() != 0)\n  {\n    trajectory_.setPresentJointWaypoint(present_joint_value);\n    trajectory_.updatePresentWaypoint(kinematics_);\n  }\n\n  KinematicPose goal_pose;\n\n  goal_pose.position = goal_position;\n  goal_pose.orientation = trajectory_.getManipulator()->getComponentOrientationFromWorld(tool_name);\n  makeTaskTrajectory(tool_name, goal_pose, move_time);\n}\n\nvoid RobotisManipulator::makeTaskTrajectory(Name tool_name, Eigen::Matrix3d goal_orientation, double move_time, std::vector<JointValue> present_joint_value)\n{\n  if(present_joint_value.size() != 0)\n  {\n    trajectory_.setPresentJointWaypoint(present_joint_value);\n    trajectory_.updatePresentWaypoint(kinematics_);\n  }\n\n  KinematicPose goal_pose;\n\n  goal_pose.position = trajectory_.getManipulator()->getComponentPositionFromWorld(tool_name);\n  goal_pose.orientation = goal_orientation;\n  makeTaskTrajectory(tool_name, goal_pose, move_time);\n}\n\nvoid RobotisManipulator::makeTaskTrajectory(Name tool_name, KinematicPose goal_pose, double move_time, std::vector<JointValue> present_joint_value)\n{\n  trajectory_.setTrajectoryType(TASK_TRAJECTORY);\n  trajectory_.setPresentControlToolName(tool_name);\n  trajectory_.setMoveTime(move_time);\n\n  if(present_joint_value.size() != 0)\n  {\n    trajectory_.setPresentJointWaypoint(present_joint_value);\n    trajectory_.updatePresentWaypoint(kinematics_);\n  }\n\n  TaskWaypoint present_task_way_point = trajectory_.getPresentTaskWaypoint(tool_name);\n\n  TaskWaypoint goal_task_way_point;                             //data conversion\n  goal_task_way_point.kinematic = goal_pose;\n  goal_task_way_point = trajectory_.removeWaypointDynamicData(goal_task_way_point);\n\n  if(getMovingState())\n  {\n    moving_state_=false;\n    while(!step_moving_state_) ;\n  }\n  trajectory_.makeTaskTrajectory(present_task_way_point, goal_task_way_point);\n  startMoving();\n}\n\nvoid RobotisManipulator::setCustomTrajectoryOption(Name trajectory_name, const void* arg)\n{\n  trajectory_.setCustomTrajectoryOption(trajectory_name, arg);\n}\n\nvoid RobotisManipulator::makeCustomTrajectory(Name trajectory_name, Name tool_name, const void *arg, double move_time, std::vector<JointValue> present_joint_value)\n{\n  trajectory_.setTrajectoryType(CUSTOM_TASK_TRAJECTORY);\n  trajectory_.setPresentControlToolName(tool_name);\n  trajectory_.setMoveTime(move_time);\n\n  if(present_joint_value.size() != 0)\n  {\n    trajectory_.setPresentJointWaypoint(present_joint_value);\n    trajectory_.updatePresentWaypoint(kinematics_);\n  }\n\n  TaskWaypoint present_task_way_point = trajectory_.getPresentTaskWaypoint(tool_name);\n\n  if(getMovingState())\n  {\n    moving_state_=false;\n    while(!step_moving_state_) ;\n  }\n  trajectory_.makeCustomTrajectory(trajectory_name, present_task_way_point, arg);\n  startMoving();\n}\n\nvoid RobotisManipulator::makeCustomTrajectory(Name trajectory_name, const void *arg, double move_time, std::vector<JointValue> present_joint_value)\n{\n  trajectory_.setTrajectoryType(CUSTOM_JOINT_TRAJECTORY);\n  trajectory_.setMoveTime(move_time);\n\n  if(present_joint_value.size() != 0)\n  {\n    trajectory_.setPresentJointWaypoint(present_joint_value);\n    trajectory_.updatePresentWaypoint(kinematics_);\n  }\n\n  JointWaypoint present_joint_way_point = trajectory_.getPresentJointWaypoint();\n\n  if(getMovingState())\n  {\n    moving_state_=false;\n    while(!step_moving_state_) ;\n  }\n  trajectory_.makeCustomTrajectory(trajectory_name, present_joint_way_point, arg);\n  startMoving();\n}\n\nvoid RobotisManipulator::sleepTrajectory(double wait_time, std::vector<JointValue> present_joint_value)\n{\n  trajectory_.setTrajectoryType(JOINT_TRAJECTORY);\n  trajectory_.setMoveTime(wait_time);\n\n  if(present_joint_value.size() != 0)\n  {\n    trajectory_.setPresentJointWaypoint(present_joint_value);\n    trajectory_.updatePresentWaypoint(kinematics_);\n  }\n\n  JointWaypoint present_joint_way_point = trajectory_.getPresentJointWaypoint();\n  JointWaypoint goal_way_point_vector = trajectory_.getPresentJointWaypoint();\n  goal_way_point_vector = trajectory_.removeWaypointDynamicData(goal_way_point_vector);\n\n  if(getMovingState())\n  {\n    moving_state_= false;\n    while(!step_moving_state_) ;\n  }\n  trajectory_.makeJointTrajectory(present_joint_way_point, goal_way_point_vector);\n  startMoving();\n}\n\nvoid RobotisManipulator::makeToolTrajectory(Name tool_name, double tool_goal_position)\n{\n  JointValue tool_value;\n  tool_value.position = tool_goal_position;\n  tool_value.velocity = 0.0;\n  tool_value.acceleration = 0.0;\n  tool_value.effort =0.0;\n\n  if(checkJointLimit(tool_name, tool_value))\n  {\n    trajectory_.setToolGoalValue(tool_name, tool_value);\n  }\n}\n\n\n\nJointWaypoint RobotisManipulator::getTrajectoryJointValue(double tick_time)       //Private\n{\n  JointWaypoint joint_way_point_value;\n\n  ////////////////////////Joint Trajectory/////////////////////////\n  if(trajectory_.checkTrajectoryType(JOINT_TRAJECTORY))\n  {\n    joint_way_point_value = trajectory_.getJointTrajectory().getJointWaypoint(tick_time);\n\n    if(!checkJointLimit(trajectory_.getManipulator()->getAllActiveJointComponentName(), joint_way_point_value))\n    {\n      joint_way_point_value = trajectory_.removeWaypointDynamicData(trajectory_.getPresentJointWaypoint());\n      moving_state_ = false;\n    }\n\n    // Set present joint task value to trajectory manipulator\n    trajectory_.setPresentJointWaypoint(joint_way_point_value);\n    trajectory_.updatePresentWaypoint(kinematics_);\n  }\n  /////////////////////////////////////////////////////////////////\n  ///\n  /////////////////////////Task Trajectory/////////////////////////\n  else if(trajectory_.checkTrajectoryType(TASK_TRAJECTORY))\n  {\n    TaskWaypoint task_way_point;\n    task_way_point = trajectory_.getTaskTrajectory().getTaskWaypoint(tick_time);\n\n    if(kinematics_->solveInverseKinematics(trajectory_.getManipulator(), trajectory_.getPresentControlToolName(), task_way_point, &joint_way_point_value))\n    {\n      if(!checkJointLimit(trajectory_.getManipulator()->getAllActiveJointComponentName(), joint_way_point_value))\n      {\n        joint_way_point_value = trajectory_.removeWaypointDynamicData(trajectory_.getPresentJointWaypoint());\n        task_way_point = trajectory_.removeWaypointDynamicData(trajectory_.getPresentTaskWaypoint(trajectory_.getPresentControlToolName()));\n        moving_state_ = false;\n      }\n    }\n    else\n    {\n      joint_way_point_value = trajectory_.removeWaypointDynamicData(trajectory_.getPresentJointWaypoint());\n      task_way_point = trajectory_.removeWaypointDynamicData(trajectory_.getPresentTaskWaypoint(trajectory_.getPresentControlToolName()));\n      log::error(\"[TASK_TRAJECTORY] fail to solve IK\");\n      moving_state_ = false;\n    }\n\n    // Set present joint task value to trajectory manipulator\n    trajectory_.setPresentJointWaypoint(joint_way_point_value);\n    trajectory_.setPresentTaskWaypoint(trajectory_.getPresentControlToolName(), task_way_point);\n  }\n  /////////////////////////////////////////////////////////////////\n  ///\n  //////////////////////Custom Trajectory/////////////////////////\n  else if(trajectory_.checkTrajectoryType(CUSTOM_JOINT_TRAJECTORY))\n  {\n    joint_way_point_value = trajectory_.getCustomJointTrajectory(trajectory_.getPresentCustomTrajectoryName())->getJointWaypoint(tick_time);\n\n    if(!checkJointLimit(trajectory_.getManipulator()->getAllActiveJointComponentName(), joint_way_point_value))\n    {\n      joint_way_point_value = trajectory_.removeWaypointDynamicData(trajectory_.getPresentJointWaypoint());\n      moving_state_ = false;\n    }\n    \n    // Set present joint task value to trajectory manipulator\n    trajectory_.setPresentJointWaypoint(joint_way_point_value);\n    trajectory_.updatePresentWaypoint(kinematics_);\n  }\n  else if(trajectory_.checkTrajectoryType(CUSTOM_TASK_TRAJECTORY))\n  {\n    TaskWaypoint task_way_point;\n    task_way_point = trajectory_.getCustomTaskTrajectory(trajectory_.getPresentCustomTrajectoryName())->getTaskWaypoint(tick_time);\n\n    if(kinematics_->solveInverseKinematics(trajectory_.getManipulator(), trajectory_.getPresentControlToolName(), task_way_point, &joint_way_point_value))\n    {\n      if(!checkJointLimit(trajectory_.getManipulator()->getAllActiveJointComponentName(), joint_way_point_value))\n      {\n        joint_way_point_value = trajectory_.removeWaypointDynamicData(trajectory_.getPresentJointWaypoint());\n        task_way_point = trajectory_.removeWaypointDynamicData(trajectory_.getPresentTaskWaypoint(trajectory_.getPresentControlToolName()));\n        moving_state_ = false;\n      }\n    }\n    else\n    {\n      joint_way_point_value = trajectory_.removeWaypointDynamicData(trajectory_.getPresentJointWaypoint());\n      task_way_point = trajectory_.removeWaypointDynamicData(trajectory_.getPresentTaskWaypoint(trajectory_.getPresentControlToolName()));\n      log::error(\"[CUSTOM_TASK_TRAJECTORY] fail to solve IK\");\n      moving_state_ = false;\n    }\n\n    // Set present joint task value to trajectory manipulator\n    trajectory_.setPresentJointWaypoint(joint_way_point_value);\n    trajectory_.setPresentTaskWaypoint(trajectory_.getPresentControlToolName(), task_way_point);\n  }\n  /////////////////////////////////////////////////////////////////\n\n//  Eigen::Vector3d print_temp = trajectory_.getManipulator()->getComponentDynamicPoseFromWorld(\"gripper\").angular.velocity;\n//  log::PRINT(\"ang vel\");\n//  log::PRINT_VECTOR(print_temp);\n\n  return joint_way_point_value;\n}\n\nstd::vector<JointValue> RobotisManipulator::getJointGoalValueFromTrajectory(double present_time)\n{\n  trajectory_.setPresentTime(present_time);\n\n  if(!trajectory_initialized_state_)\n  {\n    trajectory_.initTrajectoryWaypoint(manipulator_, kinematics_);\n    trajectory_initialized_state_ = true;\n  }\n\n  if(moving_state_)\n  {\n    step_moving_state_ = false;\n    JointWaypoint joint_goal_way_point;\n    double tick_time = trajectory_.getTickTime();\n\n    if(tick_time < trajectory_.getMoveTime())\n    {   \n      moving_state_ = true;\n      joint_goal_way_point = getTrajectoryJointValue(tick_time);\n    }\n    else\n    {\n      moving_state_ = false;\n      joint_goal_way_point =  getTrajectoryJointValue(trajectory_.getMoveTime());\n    }\n    step_moving_state_ = true;\n    return joint_goal_way_point;\n  }\n  return {};\n}\n\nstd::vector<JointValue> RobotisManipulator::getJointGoalValueFromTrajectoryTickTime(double tick_time)\n{\n  if(!trajectory_initialized_state_)\n  {\n    trajectory_.initTrajectoryWaypoint(manipulator_, kinematics_);\n    trajectory_initialized_state_ = true;\n  }\n\n  if(moving_state_)\n  {\n    step_moving_state_ = false;\n    JointWaypoint joint_goal_way_point ;\n    if(tick_time < trajectory_.getMoveTime())\n    {\n      moving_state_ = true;\n      joint_goal_way_point = getTrajectoryJointValue(tick_time);\n    }\n    else\n    {\n      moving_state_ = false;\n      joint_goal_way_point = getTrajectoryJointValue(trajectory_.getMoveTime());\n    }\n    step_moving_state_ = true;\n    return joint_goal_way_point;\n  }\n  return {};\n}\n\nstd::vector<JointValue> RobotisManipulator::getToolGoalValue()\n{\n  std::vector<JointValue> result_vector;\n  std::vector<Name> tool_component_name = trajectory_.getManipulator()->getAllToolComponentName();\n  for(uint32_t index =0; index<tool_component_name.size(); index++)\n  {\n    result_vector.push_back(trajectory_.getToolGoalValue(tool_component_name.at(index)));\n  }\n  return result_vector;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RobotisManipulator/src/robotis_manipulator/robotis_manipulator_common.cpp",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include \"../../include/robotis_manipulator/robotis_manipulator_common.h\"\n\nusing namespace robotis_manipulator;\n\nManipulator::Manipulator():dof_(0){}\n\n/*****************************************************************************\n** Add Function\n*****************************************************************************/\nvoid Manipulator::addWorld(Name world_name,\n                           Name child_name,\n                           Eigen::Vector3d world_position,\n                           Eigen::Matrix3d world_orientation)\n{\n  world_.name = world_name;\n  world_.child = child_name;\n  world_.pose.kinematic.position = world_position;\n  world_.pose.kinematic.orientation = world_orientation;\n  world_.pose.dynamic.linear.velocity = Eigen::Vector3d::Zero();\n  world_.pose.dynamic.linear.acceleration = Eigen::Vector3d::Zero();\n  world_.pose.dynamic.angular.velocity = Eigen::Vector3d::Zero();\n  world_.pose.dynamic.angular.acceleration = Eigen::Vector3d::Zero();\n}\n\nvoid Manipulator::addJoint(Name my_name,\n                           Name parent_name,\n                           Name child_name,\n                           Eigen::Vector3d relative_position,\n                           Eigen::Matrix3d relative_orientation,\n                           Eigen::Vector3d axis_of_rotation,\n                           int8_t joint_actuator_id,\n                           double max_position_limit,\n                           double min_position_limit,\n                           double coefficient,\n                           double mass,\n                           Eigen::Matrix3d inertia_tensor,\n                           Eigen::Vector3d center_of_mass)\n{\n  Component temp_component;\n  if (joint_actuator_id != -1)\n  {\n    dof_++;\n    temp_component.component_type = ACTIVE_JOINT_COMPONENT;\n  }\n  else\n  {\n    temp_component.component_type = PASSIVE_JOINT_COMPONENT;\n  }\n\n  temp_component.name.parent = parent_name;\n  temp_component.name.child.push_back(child_name);\n  temp_component.relative.pose_from_parent.position = relative_position;\n  temp_component.relative.pose_from_parent.orientation = relative_orientation;\n  temp_component.relative.inertia.mass = mass;\n  temp_component.relative.inertia.inertia_tensor = inertia_tensor;\n  temp_component.relative.inertia.center_of_mass = center_of_mass;\n  temp_component.joint_constant.id = joint_actuator_id;\n  temp_component.joint_constant.coefficient = coefficient;\n  temp_component.joint_constant.axis = axis_of_rotation;\n  temp_component.joint_constant.position_limit.maximum = max_position_limit;\n  temp_component.joint_constant.position_limit.minimum = min_position_limit;\n\n  temp_component.pose_from_world.kinematic.position = Eigen::Vector3d::Zero();\n  temp_component.pose_from_world.kinematic.orientation = Eigen::Matrix3d::Identity();\n  temp_component.pose_from_world.dynamic.linear.velocity = Eigen::Vector3d::Zero();\n  temp_component.pose_from_world.dynamic.linear.acceleration = Eigen::Vector3d::Zero();\n  temp_component.pose_from_world.dynamic.angular.velocity = Eigen::Vector3d::Zero();\n  temp_component.pose_from_world.dynamic.angular.acceleration = Eigen::Vector3d::Zero();\n\n  temp_component.joint_value.position = 0.0;\n  temp_component.joint_value.velocity = 0.0;\n  temp_component.joint_value.effort = 0.0;\n\n  component_.insert(std::make_pair(my_name, temp_component));\n}\n\nvoid Manipulator::addTool(Name my_name,\n                          Name parent_name,\n                          Eigen::Vector3d relative_position,\n                          Eigen::Matrix3d relative_orientation,\n                          int8_t tool_id,\n                          double max_position_limit,\n                          double min_position_limit,\n                          double coefficient,\n                          double mass,\n                          Eigen::Matrix3d inertia_tensor,\n                          Eigen::Vector3d center_of_mass)\n{\n  Component temp_component;\n\n  temp_component.name.parent = parent_name;\n  temp_component.name.child.resize(0);\n  temp_component.component_type = TOOL_COMPONENT;\n  temp_component.relative.pose_from_parent.position = relative_position;\n  temp_component.relative.pose_from_parent.orientation = relative_orientation;\n  temp_component.relative.inertia.mass = mass;\n  temp_component.relative.inertia.inertia_tensor = inertia_tensor;\n  temp_component.relative.inertia.center_of_mass = center_of_mass;\n  temp_component.joint_constant.id = tool_id;\n  temp_component.joint_constant.coefficient = coefficient;\n  temp_component.joint_constant.axis = Eigen::Vector3d::Zero();\n  temp_component.joint_constant.position_limit.maximum = max_position_limit;\n  temp_component.joint_constant.position_limit.minimum = min_position_limit;\n\n  temp_component.pose_from_world.kinematic.position = Eigen::Vector3d::Zero();\n  temp_component.pose_from_world.kinematic.orientation = Eigen::Matrix3d::Identity();\n  temp_component.pose_from_world.dynamic.linear.velocity = Eigen::Vector3d::Zero();\n  temp_component.pose_from_world.dynamic.linear.acceleration = Eigen::Vector3d::Zero();\n  temp_component.pose_from_world.dynamic.angular.velocity = Eigen::Vector3d::Zero();\n  temp_component.pose_from_world.dynamic.angular.acceleration = Eigen::Vector3d::Zero();\n\n  temp_component.joint_value.position = 0.0;\n  temp_component.joint_value.velocity = 0.0;\n  temp_component.joint_value.effort = 0.0;\n\n  component_.insert(std::make_pair(my_name, temp_component));\n}\n\nvoid Manipulator::addComponentChild(Name my_name, Name child_name)\n{\n  component_.at(my_name).name.child.push_back(child_name);\n}\n\nvoid Manipulator::printManipulatorSetting()\n{\n  log::println(\"----------<Manipulator Description>----------\");\n  log::println(\"<Degree of Freedom>\\n\", dof_);\n  log::println(\"<Number of Components>\\n\", component_.size());\n  log::println(\"\");\n  log::println(\"<World Configuration>\");\n  log::println(\" [Name]\");\n  log::print(\" -World Name : \"); log::println(STRING(world_.name));\n  log::print(\" -Child Name : \"); log::println(STRING(world_.child));\n  log::println(\" [Static Pose]\");\n  log::println(\" -Position : \");\n  log::print_vector(world_.pose.kinematic.position);\n  log::println(\" -Orientation : \");\n  log::print_matrix(world_.pose.kinematic.orientation);\n  log::println(\" [Dynamic Pose]\");\n  log::println(\" -Linear Velocity : \");\n  log::print_vector(world_.pose.dynamic.linear.velocity);\n  log::println(\" -Linear acceleration : \");\n  log::print_vector(world_.pose.dynamic.linear.acceleration);\n  log::println(\" -Angular Velocity : \");\n  log::print_vector(world_.pose.dynamic.angular.velocity);\n  log::println(\" -Angular acceleration : \");\n  log::print_vector(world_.pose.dynamic.angular.acceleration);\n\n  std::vector<double> result_vector;\n  std::map<Name, Component>::iterator it_component;\n\n  for (it_component = component_.begin(); it_component != component_.end(); it_component++)\n  {\n    log::println(\"\");\n    log::println(\"<\"); log::print(STRING(it_component->first)); log::print(\"Configuration>\");\n    if(component_.at(it_component->first).component_type == ACTIVE_JOINT_COMPONENT)\n      log::println(\" [Component Type]\\n  Active Joint\");\n    else if(component_.at(it_component->first).component_type == PASSIVE_JOINT_COMPONENT)\n      log::println(\" [Component Type]\\n  Passive Joint\");\n    else if(component_.at(it_component->first).component_type == TOOL_COMPONENT)\n      log::println(\" [Component Type]\\n  Tool\");\n    log::println(\" [Name]\");\n    log::print(\" -Parent Name : \"); log::println(STRING(component_.at(it_component->first).name.parent));\n    for(uint32_t index = 0; index < component_.at(it_component->first).name.child.size(); index++)\n    {\n      log::print(\" -Child Name\",index+1,0);\n      log::print(\" : \");\n      log::println(STRING(component_.at(it_component->first).name.child.at(index)));\n    }\n    log::println(\" [Actuator]\");\n    log::print(\" -Actuator Name : \");\n    log::println(STRING(component_.at(it_component->first).actuator_name));\n    log::print(\" -ID : \");\n    log::println(\"\", component_.at(it_component->first).joint_constant.id,0);\n    log::println(\" -Joint Axis : \");\n    log::print_vector(component_.at(it_component->first).joint_constant.axis);\n    log::print(\" -Coefficient : \");\n    log::println(\"\", component_.at(it_component->first).joint_constant.coefficient);\n    log::println(\" -Position Limit : \");\n    log::print(\"    Maximum :\", component_.at(it_component->first).joint_constant.position_limit.maximum);\n    log::println(\", Minimum :\", component_.at(it_component->first).joint_constant.position_limit.minimum);\n\n    log::println(\" [Actuator Value]\");\n    log::println(\" -Position : \", component_.at(it_component->first).joint_value.position);\n    log::println(\" -Velocity : \", component_.at(it_component->first).joint_value.velocity);\n    log::println(\" -Acceleration : \", component_.at(it_component->first).joint_value.acceleration);\n    log::println(\" -Effort : \", component_.at(it_component->first).joint_value.effort);\n\n    log::println(\" [Constant]\");\n    log::println(\" -Relative Position from parent component : \");\n    log::print_vector(component_.at(it_component->first).relative.pose_from_parent.position);\n    log::println(\" -Relative Orientation from parent component : \");\n    log::print_matrix(component_.at(it_component->first).relative.pose_from_parent.orientation);\n    log::print(\" -Mass : \");\n    log::println(\"\", component_.at(it_component->first).relative.inertia.mass);\n    log::println(\" -Inertia Tensor : \");\n    log::print_matrix(component_.at(it_component->first).relative.inertia.inertia_tensor);\n    log::println(\" -Center of Mass : \");\n    log::print_vector(component_.at(it_component->first).relative.inertia.center_of_mass);\n\n    log::println(\" [Variable]\");\n    log::println(\" -Position : \");\n    log::print_vector(component_.at(it_component->first).pose_from_world.kinematic.position);\n    log::println(\" -Orientation : \");\n    log::print_matrix(component_.at(it_component->first).pose_from_world.kinematic.orientation);\n    log::println(\" -Linear Velocity : \");\n    log::print_vector(component_.at(it_component->first).pose_from_world.dynamic.linear.velocity);\n    log::println(\" -Linear acceleration : \");\n    log::print_vector(component_.at(it_component->first).pose_from_world.dynamic.linear.acceleration);\n    log::println(\" -Angular Velocity : \");\n    log::print_vector(component_.at(it_component->first).pose_from_world.dynamic.angular.velocity);\n    log::println(\" -Angular acceleration : \");\n    log::print_vector(component_.at(it_component->first).pose_from_world.dynamic.angular.acceleration);\n  }\n  log::println(\"---------------------------------------------\");\n}\n\n\n/*****************************************************************************\n** Set Function\n*****************************************************************************/\nvoid Manipulator::setWorldPose(Pose world_pose)\n{\n  world_.pose = world_pose;\n}\n\nvoid Manipulator::setWorldKinematicPose(KinematicPose world_kinematic_pose)\n{\n  world_.pose.kinematic = world_kinematic_pose;\n}\n\nvoid Manipulator::setWorldPosition(Eigen::Vector3d world_position)\n{\n  world_.pose.kinematic.position = world_position;\n}\n\nvoid Manipulator::setWorldOrientation(Eigen::Matrix3d world_orientation)\n{\n  world_.pose.kinematic.orientation = world_orientation;\n}\n\nvoid Manipulator::setWorldDynamicPose(DynamicPose world_dynamic_pose)\n{\n  world_.pose.dynamic = world_dynamic_pose;\n}\n\nvoid Manipulator::setWorldLinearVelocity(Eigen::Vector3d world_linear_velocity)\n{\n  world_.pose.dynamic.linear.velocity = world_linear_velocity;\n}\n\nvoid Manipulator::setWorldAngularVelocity(Eigen::Vector3d world_angular_velocity)\n{\n  world_.pose.dynamic.angular.velocity = world_angular_velocity;\n}\n\nvoid Manipulator::setWorldLinearAcceleration(Eigen::Vector3d world_linear_acceleration)\n{\n  world_.pose.dynamic.linear.acceleration = world_linear_acceleration;\n}\n\nvoid Manipulator::setWorldAngularAcceleration(Eigen::Vector3d world_angular_acceleration)\n{\n  world_.pose.dynamic.angular.acceleration = world_angular_acceleration;\n}\n\nvoid Manipulator::setComponent(Name component_name, Component component)\n{\n  component_.at(component_name) = component;\n}\n\nvoid Manipulator::setComponentActuatorName(Name component_name, Name actuator_name)\n{\n  component_.at(component_name).actuator_name = actuator_name;\n}\n\nvoid Manipulator::setComponentPoseFromWorld(Name component_name, Pose pose_to_world)\n{\n  if (component_.find(component_name) != component_.end())\n  {\n    component_.at(component_name).pose_from_world = pose_to_world;\n  }\n  else\n  {\n    log::error(\"[setComponentPoseFromWorld] Wrong name.\");\n  }\n}\n\nvoid Manipulator::setComponentKinematicPoseFromWorld(Name component_name, KinematicPose pose_to_world)\n{\n  if (component_.find(component_name) != component_.end())\n  {\n    component_.at(component_name).pose_from_world.kinematic = pose_to_world;\n  }\n  else\n  {\n    log::error(\"[setComponentKinematicPoseFromWorld] Wrong name.\");\n  }\n}\n\nvoid Manipulator::setComponentPositionFromWorld(Name component_name, Eigen::Vector3d position_to_world)\n{\n  if (component_.find(component_name) != component_.end())\n  {\n    component_.at(component_name).pose_from_world.kinematic.position = position_to_world;\n  }\n  else\n  {\n    log::error(\"[setComponentPositionFromWorld] Wrong name.\");\n  }\n}\n\nvoid Manipulator::setComponentOrientationFromWorld(Name component_name, Eigen::Matrix3d orientation_to_wolrd)\n{\n  if (component_.find(component_name) != component_.end())\n  {\n    component_.at(component_name).pose_from_world.kinematic.orientation = orientation_to_wolrd;\n  }\n  else\n  {\n    log::error(\"[setComponentOrientationFromWorld] Wrong name.\");\n  }\n}\n\nvoid Manipulator::setComponentDynamicPoseFromWorld(Name component_name, DynamicPose dynamic_pose)\n{\n  if (component_.find(component_name) != component_.end())\n  {\n    component_.at(component_name).pose_from_world.dynamic = dynamic_pose;\n  }\n  else\n  {\n    log::error(\"[setComponentDynamicPoseFromWorld] Wrong name.\");\n  }\n}\n\nvoid Manipulator::setJointPosition(Name component_name, double position)\n{\n  component_.at(component_name).joint_value.position = position;\n}\n\nvoid Manipulator::setJointVelocity(Name component_name, double velocity)\n{\n  component_.at(component_name).joint_value.velocity = velocity;\n}\n\nvoid Manipulator::setJointAcceleration(Name component_name, double acceleration)\n{\n  component_.at(component_name).joint_value.acceleration = acceleration;\n}\n\nvoid Manipulator::setJointEffort(Name component_name, double effort)\n{\n  component_.at(component_name).joint_value.effort = effort;\n}\n\nvoid Manipulator::setJointValue(Name component_name, JointValue joint_value)\n{\n  component_.at(component_name).joint_value = joint_value;\n}\n\nvoid Manipulator::setAllActiveJointPosition(std::vector<double> joint_position_vector)\n{\n  int8_t index = 0;\n  std::map<Name, Component>::iterator it_component;\n\n  for (it_component = component_.begin(); it_component != component_.end(); it_component++)\n  {\n    if (component_.at(it_component->first).component_type == ACTIVE_JOINT_COMPONENT)\n    {\n      component_.at(it_component->first).joint_value.position = joint_position_vector.at(index);\n      index++;\n    }\n  }\n}\n\nvoid Manipulator::setAllActiveJointValue(std::vector<JointValue> joint_value_vector)\n{\n  int8_t index = 0;\n  std::map<Name, Component>::iterator it_component;\n\n  for (it_component = component_.begin(); it_component != component_.end(); it_component++)\n  {\n    if (component_.at(it_component->first).component_type == ACTIVE_JOINT_COMPONENT)\n    {\n      component_.at(it_component->first).joint_value.position = joint_value_vector.at(index).position;\n      component_.at(it_component->first).joint_value.velocity = joint_value_vector.at(index).velocity;\n      component_.at(it_component->first).joint_value.acceleration = joint_value_vector.at(index).acceleration;\n      component_.at(it_component->first).joint_value.effort = joint_value_vector.at(index).effort;\n      index++;\n    }\n  }\n}\n\nvoid Manipulator::setAllJointPosition(std::vector<double> joint_position_vector)\n{\n  int8_t index = 0;\n  std::map<Name, Component>::iterator it_component;\n\n  for (it_component = component_.begin(); it_component != component_.end(); it_component++)\n  {\n    if (component_.at(it_component->first).component_type == ACTIVE_JOINT_COMPONENT || component_.at(it_component->first).component_type == PASSIVE_JOINT_COMPONENT)\n    {\n      component_.at(it_component->first).joint_value.position = joint_position_vector.at(index);\n      index++;\n    }\n  }\n}\n\nvoid Manipulator::setAllJointValue(std::vector<JointValue> joint_value_vector)\n{\n  int8_t index = 0;\n  std::map<Name, Component>::iterator it_component;\n\n  for (it_component = component_.begin(); it_component != component_.end(); it_component++)\n  {\n    if (component_.at(it_component->first).component_type == ACTIVE_JOINT_COMPONENT || component_.at(it_component->first).component_type == PASSIVE_JOINT_COMPONENT)\n    {\n      component_.at(it_component->first).joint_value = joint_value_vector.at(index);\n      index++;\n    }\n  }\n}\n\nvoid Manipulator::setAllToolPosition(std::vector<double> tool_position_vector)\n{\n  int8_t index = 0;\n  std::map<Name, Component>::iterator it_component;\n\n  for (it_component = component_.begin(); it_component != component_.end(); it_component++)\n  {\n    if (component_.at(it_component->first).component_type == TOOL_COMPONENT)\n    {\n      component_.at(it_component->first).joint_value.position = tool_position_vector.at(index);\n      index++;\n    }\n  }\n}\n\nvoid Manipulator::setAllToolValue(std::vector<JointValue> tool_value_vector)\n{\n  int8_t index = 0;\n  std::map<Name, Component>::iterator it_component;\n\n  for (it_component = component_.begin(); it_component != component_.end(); it_component++)\n  {\n    if (component_.at(it_component->first).component_type == TOOL_COMPONENT)\n    {\n      component_.at(it_component->first).joint_value = tool_value_vector.at(index);\n      index++;\n    }\n  }\n}\n\n\n/*****************************************************************************\n** Get Function\n*****************************************************************************/\nint8_t Manipulator::getDOF()\n{\n  return dof_;\n}\n\nName Manipulator::getWorldName()\n{\n  return world_.name;\n}\n\nName Manipulator::getWorldChildName()\n{\n  return world_.child;\n}\n\nPose Manipulator::getWorldPose()\n{\n  return world_.pose;\n}\n\nKinematicPose Manipulator::getWorldKinematicPose()\n{\n  return world_.pose.kinematic;\n}\n\nEigen::Vector3d Manipulator::getWorldPosition()\n{\n  return world_.pose.kinematic.position;\n}\n\nEigen::Matrix3d Manipulator::getWorldOrientation()\n{\n  return world_.pose.kinematic.orientation;\n}\n\nDynamicPose Manipulator::getWorldDynamicPose()\n{\n  return world_.pose.dynamic;\n}\n\nint8_t Manipulator::getComponentSize()\n{\n  return component_.size();\n}\n\nstd::map<Name, Component> Manipulator::getAllComponent()\n{\n  return component_;\n}\n\nstd::map<Name, Component>::iterator Manipulator::getIteratorBegin()\n{\n  return component_.begin();\n}\n\nstd::map<Name, Component>::iterator Manipulator::getIteratorEnd()\n{\n  return component_.end();;\n}\n\nComponent Manipulator::getComponent(Name component_name)\n{\n  return component_.at(component_name);\n}\n\nName Manipulator::getComponentActuatorName(Name component_name)\n{\n  return component_.at(component_name).actuator_name;\n}\n\nName Manipulator::getComponentParentName(Name component_name)\n{\n  return component_.at(component_name).name.parent;\n}\n\nstd::vector<Name> Manipulator::getComponentChildName(Name component_name)\n{\n  return component_.at(component_name).name.child;\n}\n\nPose Manipulator::getComponentPoseFromWorld(Name component_name)\n{\n  return component_.at(component_name).pose_from_world;\n}\n\nKinematicPose Manipulator::getComponentKinematicPoseFromWorld(Name component_name)\n{\n  return component_.at(component_name).pose_from_world.kinematic;\n}\n\nEigen::Vector3d Manipulator::getComponentPositionFromWorld(Name component_name)\n{\n  return component_.at(component_name).pose_from_world.kinematic.position;\n}\n\nEigen::Matrix3d Manipulator::getComponentOrientationFromWorld(Name component_name)\n{\n  return component_.at(component_name).pose_from_world.kinematic.orientation;\n}\n\nDynamicPose Manipulator::getComponentDynamicPoseFromWorld(Name component_name)\n{\n  return component_.at(component_name).pose_from_world.dynamic;\n}\n\nKinematicPose Manipulator::getComponentRelativePoseFromParent(Name component_name)\n{\n  return component_.at(component_name).relative.pose_from_parent;\n}\n\nEigen::Vector3d Manipulator::getComponentRelativePositionFromParent(Name component_name)\n{\n  return component_.at(component_name).relative.pose_from_parent.position;\n}\n\nEigen::Matrix3d Manipulator::getComponentRelativeOrientationFromParent(Name component_name)\n{\n  return component_.at(component_name).relative.pose_from_parent.orientation;\n}\n\nint8_t Manipulator::getId(Name component_name)\n{\n  return component_.at(component_name).joint_constant.id;\n}\n\ndouble Manipulator::getCoefficient(Name component_name)\n{\n  return component_.at(component_name).joint_constant.coefficient;\n}\n\nEigen::Vector3d Manipulator::getAxis(Name component_name)\n{\n  return component_.at(component_name).joint_constant.axis;\n}\n\ndouble Manipulator::getJointPosition(Name component_name)\n{\n  return component_.at(component_name).joint_value.position;\n}\n\ndouble Manipulator::getJointVelocity(Name component_name)\n{\n  return component_.at(component_name).joint_value.velocity;\n}\n\ndouble Manipulator::getJointAcceleration(Name component_name)\n{\n  return component_.at(component_name).joint_value.acceleration;\n}\n\ndouble Manipulator::getJointEffort(Name component_name)\n{\n  return component_.at(component_name).joint_value.effort;\n}\n\nJointValue Manipulator::getJointValue(Name component_name)\n{\n  return component_.at(component_name).joint_value;\n}\n\ndouble Manipulator::getComponentMass(Name component_name)\n{\n  return component_.at(component_name).relative.inertia.mass;\n}\n\nEigen::Matrix3d Manipulator::getComponentInertiaTensor(Name component_name)\n{\n  return component_.at(component_name).relative.inertia.inertia_tensor;\n}\n\nEigen::Vector3d Manipulator::getComponentCenterOfMass(Name component_name)\n{\n  return component_.at(component_name).relative.inertia.center_of_mass;\n}\n\nstd::vector<double> Manipulator::getAllJointPosition()\n{\n  std::vector<double> result_vector;\n  std::map<Name, Component>::iterator it_component;\n\n  for (it_component = component_.begin(); it_component != component_.end(); it_component++)\n  {\n    if (checkComponentType(it_component->first, ACTIVE_JOINT_COMPONENT) || checkComponentType(it_component->first, PASSIVE_JOINT_COMPONENT))\n    {\n      result_vector.push_back(component_.at(it_component->first).joint_value.position);\n    }\n  }\n  return result_vector;\n}\n\nstd::vector<JointValue> Manipulator::getAllJointValue()\n{\n  std::vector<JointValue> result_vector;\n  std::map<Name, Component>::iterator it_component;\n\n  for (it_component = component_.begin(); it_component != component_.end(); it_component++)\n  {\n    if (checkComponentType(it_component->first, ACTIVE_JOINT_COMPONENT) || checkComponentType(it_component->first, PASSIVE_JOINT_COMPONENT))\n    {\n      result_vector.push_back(component_.at(it_component->first).joint_value);\n    }\n  }\n  return result_vector;\n}\n\nstd::vector<double> Manipulator::getAllActiveJointPosition()\n{\n  std::vector<double> result_vector;\n  std::map<Name, Component>::iterator it_component;\n\n  for (it_component = component_.begin(); it_component != component_.end(); it_component++)\n  {\n    if (checkComponentType(it_component->first, ACTIVE_JOINT_COMPONENT))\n    {\n      result_vector.push_back(component_.at(it_component->first).joint_value.position);\n    }\n  }\n  return result_vector;\n}\n\nstd::vector<JointValue> Manipulator::getAllActiveJointValue()\n{\n  std::vector<JointValue> result_vector;\n  std::map<Name, Component>::iterator it_component;\n\n  for (it_component = component_.begin(); it_component != component_.end(); it_component++)\n  {\n    if (checkComponentType(it_component->first, ACTIVE_JOINT_COMPONENT))\n    {\n      result_vector.push_back(component_.at(it_component->first).joint_value);\n    }\n  }\n  return result_vector;\n}\n\nstd::vector<double> Manipulator::getAllToolPosition()\n{\n  std::vector<double> result_vector;\n  std::map<Name, Component>::iterator it_component;\n\n  for (it_component = component_.begin(); it_component != component_.end(); it_component++)\n  {\n    if (checkComponentType(it_component->first, TOOL_COMPONENT))\n    {\n      result_vector.push_back(component_.at(it_component->first).joint_value.position);\n    }\n  }\n  return result_vector;\n}\n\n\nstd::vector<JointValue> Manipulator::getAllToolValue()\n{\n  std::vector<JointValue> result_vector;\n  std::map<Name, Component>::iterator it_component;\n\n  for (it_component = component_.begin(); it_component != component_.end(); it_component++)\n  {\n    if (checkComponentType(it_component->first, TOOL_COMPONENT))\n    {\n      result_vector.push_back(component_.at(it_component->first).joint_value);\n    }\n  }\n  return result_vector;\n}\n\nstd::vector<uint8_t> Manipulator::getAllJointID()\n{\n  std::vector<uint8_t> joint_id;\n  std::map<Name, Component>::iterator it_component;\n\n  for (it_component = component_.begin(); it_component != component_.end(); it_component++)\n  {\n    if (checkComponentType(it_component->first, ACTIVE_JOINT_COMPONENT) || checkComponentType(it_component->first, PASSIVE_JOINT_COMPONENT))\n    {\n      joint_id.push_back(component_.at(it_component->first).joint_constant.id);\n    }\n  }\n  return joint_id;\n}\n\nstd::vector<uint8_t> Manipulator::getAllActiveJointID()\n{\n  std::vector<uint8_t> active_joint_id;\n  std::map<Name, Component>::iterator it_component;\n\n  for (it_component = component_.begin(); it_component != component_.end(); it_component++)\n  {\n    if (checkComponentType(it_component->first, ACTIVE_JOINT_COMPONENT))\n    {\n      active_joint_id.push_back(component_.at(it_component->first).joint_constant.id);\n    }\n  }\n  return active_joint_id;\n}\n\n\nstd::vector<Name> Manipulator::getAllToolComponentName()\n{\n  std::vector<Name> tool_name;\n  std::map<Name, Component>::iterator it_component;\n\n  for (it_component = component_.begin(); it_component != component_.end(); it_component++)\n  {\n    if (checkComponentType(it_component->first, TOOL_COMPONENT))\n    {\n      tool_name.push_back(it_component->first);\n    }\n  }\n  return tool_name;\n}\n\nstd::vector<Name> Manipulator::getAllActiveJointComponentName()\n{\n  std::vector<Name> active_joint_name;\n  std::map<Name, Component>::iterator it_component;\n\n  for (it_component = component_.begin(); it_component != component_.end(); it_component++)\n  {\n    if (checkComponentType(it_component->first, ACTIVE_JOINT_COMPONENT))\n    {\n      active_joint_name.push_back(it_component->first);\n    }\n  }\n  return active_joint_name;\n}\n\n\n/*****************************************************************************\n** Check Function\n*****************************************************************************/\nbool Manipulator::checkJointLimit(Name component_name, double value)\n{\n  if(component_.at(component_name).joint_constant.position_limit.maximum < value)\n    return false;\n  else if(component_.at(component_name).joint_constant.position_limit.minimum > value)\n    return false;\n  else\n    return true;\n}\n\nbool Manipulator::checkComponentType(Name component_name, ComponentType component_type)\n{\n  if(component_.at(component_name).component_type == component_type)\n    return true;\n  else\n    return false;\n}\n\n\n/*****************************************************************************\n** Find Function\n*****************************************************************************/\nName Manipulator::findComponentNameUsingId(int8_t id)\n{\n  std::map<Name, Component>::iterator it_component;\n\n  for (it_component = component_.begin(); it_component != component_.end(); it_component++)\n  {\n    if (component_.at(it_component->first).joint_constant.id == id)\n    {\n      return it_component->first;\n    }\n  }\n  return {};\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RobotisManipulator/src/robotis_manipulator/robotis_manipulator_log.cpp",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include \"../../include/robotis_manipulator/robotis_manipulator_log.h\"\n\nvoid robotis_manipulator::log::print(STRING str, STRING color)\n{\n#if defined(__OPENCR__)\n  DEBUG.print(str);\n#else\n       if(color == \"RED\")      printf(ANSI_COLOR_RED);\n  else if(color == \"GREEN\")    printf(ANSI_COLOR_GREEN);\n  else if(color == \"YELLOW\")   printf(ANSI_COLOR_YELLOW);\n  else if(color == \"BLUE\")     printf(ANSI_COLOR_BLUE);\n  else if(color == \"MAGENTA\")  printf(ANSI_COLOR_MAGENTA);\n  else if(color == \"CYAN\")     printf(ANSI_COLOR_CYAN);\n  printf(\"%s\", str.c_str());\n  printf(ANSI_COLOR_RESET);\n#endif\n}\nvoid robotis_manipulator::log::print(STRING str, double data, uint8_t decimal_point, STRING color)\n{\n#if defined(__OPENCR__)\n  DEBUG.print(str);\n  DEBUG.print(data, decimal_point);\n#else\n       if(color == \"RED\")      printf(ANSI_COLOR_RED);\n  else if(color == \"GREEN\")    printf(ANSI_COLOR_GREEN);\n  else if(color == \"YELLOW\")   printf(ANSI_COLOR_YELLOW);\n  else if(color == \"BLUE\")     printf(ANSI_COLOR_BLUE);\n  else if(color == \"MAGENTA\")  printf(ANSI_COLOR_MAGENTA);\n  else if(color == \"CYAN\")     printf(ANSI_COLOR_CYAN);\n  printf(\"%s %.*lf\", str.c_str(), decimal_point, data);\n  printf(ANSI_COLOR_RESET);\n#endif\n}\nvoid robotis_manipulator::log::print(const char* str, STRING color)\n{\n#if defined(__OPENCR__)\n  DEBUG.print(str);\n#else\n       if(color == \"RED\")      printf(ANSI_COLOR_RED);\n  else if(color == \"GREEN\")    printf(ANSI_COLOR_GREEN);\n  else if(color == \"YELLOW\")   printf(ANSI_COLOR_YELLOW);\n  else if(color == \"BLUE\")     printf(ANSI_COLOR_BLUE);\n  else if(color == \"MAGENTA\")  printf(ANSI_COLOR_MAGENTA);\n  else if(color == \"CYAN\")     printf(ANSI_COLOR_CYAN);\n  printf(\"%s\", str);\n  printf(ANSI_COLOR_RESET);\n#endif\n}\nvoid robotis_manipulator::log::print(const char* str, double data, uint8_t decimal_point, STRING color)\n{\n#if defined(__OPENCR__)\n  DEBUG.print(str);\n  DEBUG.print(data, decimal_point);\n#else\n       if(color == \"RED\")      printf(ANSI_COLOR_RED);\n  else if(color == \"GREEN\")    printf(ANSI_COLOR_GREEN);\n  else if(color == \"YELLOW\")   printf(ANSI_COLOR_YELLOW);\n  else if(color == \"BLUE\")     printf(ANSI_COLOR_BLUE);\n  else if(color == \"MAGENTA\")  printf(ANSI_COLOR_MAGENTA);\n  else if(color == \"CYAN\")     printf(ANSI_COLOR_CYAN);\n  printf(\"%s %.*lf\", str, decimal_point, data);\n  printf(ANSI_COLOR_RESET);\n#endif\n}\n\n\nvoid robotis_manipulator::log::println(STRING str, STRING color)\n{\n#if defined(__OPENCR__)\n  DEBUG.println(str);\n#else\n       if(color == \"RED\")      printf(ANSI_COLOR_RED);\n  else if(color == \"GREEN\")    printf(ANSI_COLOR_GREEN);\n  else if(color == \"YELLOW\")   printf(ANSI_COLOR_YELLOW);\n  else if(color == \"BLUE\")     printf(ANSI_COLOR_BLUE);\n  else if(color == \"MAGENTA\")  printf(ANSI_COLOR_MAGENTA);\n  else if(color == \"CYAN\")     printf(ANSI_COLOR_CYAN);\n  printf(\"%s\\n\", str.c_str());\n  printf(ANSI_COLOR_RESET);\n#endif\n}\nvoid robotis_manipulator::log::println(STRING str, double data, uint8_t decimal_point, STRING color)\n{\n#if defined(__OPENCR__)\n  DEBUG.print(str);\n  DEBUG.println(data, decimal_point);\n#else\n     if(color == \"RED\")      printf(ANSI_COLOR_RED);\n  else if(color == \"GREEN\")    printf(ANSI_COLOR_GREEN);\n  else if(color == \"YELLOW\")   printf(ANSI_COLOR_YELLOW);\n  else if(color == \"BLUE\")     printf(ANSI_COLOR_BLUE);\n  else if(color == \"MAGENTA\")  printf(ANSI_COLOR_MAGENTA);\n  else if(color == \"CYAN\")     printf(ANSI_COLOR_CYAN);\n  printf(\"%s %.*lf\\n\", str.c_str(), decimal_point, data);\n  printf(ANSI_COLOR_RESET);\n#endif\n}\nvoid robotis_manipulator::log::println(const char* str, STRING color)\n{\n#if defined(__OPENCR__)\n  DEBUG.println(str);\n#else\n       if(color == \"RED\")      printf(ANSI_COLOR_RED);\n  else if(color == \"GREEN\")    printf(ANSI_COLOR_GREEN);\n  else if(color == \"YELLOW\")   printf(ANSI_COLOR_YELLOW);\n  else if(color == \"BLUE\")     printf(ANSI_COLOR_BLUE);\n  else if(color == \"MAGENTA\")  printf(ANSI_COLOR_MAGENTA);\n  else if(color == \"CYAN\")     printf(ANSI_COLOR_CYAN);\n  printf(\"%s\\n\", str);\n  printf(ANSI_COLOR_RESET);\n#endif\n}\nvoid robotis_manipulator::log::println(const char* str, double data, uint8_t decimal_point, STRING color)\n{\n#if defined(__OPENCR__)\n  DEBUG.print(str);\n  DEBUG.println(data, decimal_point);\n#else\n       if(color == \"RED\")      printf(ANSI_COLOR_RED);\n  else if(color == \"GREEN\")    printf(ANSI_COLOR_GREEN);\n  else if(color == \"YELLOW\")   printf(ANSI_COLOR_YELLOW);\n  else if(color == \"BLUE\")     printf(ANSI_COLOR_BLUE);\n  else if(color == \"MAGENTA\")  printf(ANSI_COLOR_MAGENTA);\n  else if(color == \"CYAN\")     printf(ANSI_COLOR_CYAN);\n  printf(\"%s %.*lf\\n\", str, decimal_point, data);\n  printf(ANSI_COLOR_RESET);\n#endif\n}\n\nvoid robotis_manipulator::log::info(STRING str)\n{\n#if defined(__OPENCR__)\n  DEBUG.print(\"[INFO] \");\n  DEBUG.println(str);\n#else\n  printf(\"[INFO] %s\\n\", str.c_str());\n#endif\n}\nvoid robotis_manipulator::log::info(STRING str, double data, uint8_t decimal_point)\n{\n#if defined(__OPENCR__)\n  DEBUG.print(\"[INFO] \");\n  DEBUG.print(str);\n  DEBUG.println(data, decimal_point);\n#else\n  printf(\"[INFO] %s %.*lf\\n\", str.c_str(), decimal_point, data);\n#endif\n}\nvoid robotis_manipulator::log::info(const char* str)\n{\n#if defined(__OPENCR__)\n  DEBUG.print(\"[INFO] \");\n  DEBUG.println(str);\n#else\n  printf(\"[INFO] %s\\n\", str);\n#endif\n}\nvoid robotis_manipulator::log::info(const char* str, double data, uint8_t decimal_point)\n{\n#if defined(__OPENCR__)\n  DEBUG.print(\"[INFO] \");\n  DEBUG.print(str);\n  DEBUG.println(data, decimal_point);\n#else\n  printf(\"[INFO] %s %.*lf\\n\", str, decimal_point, data);\n#endif\n}\nvoid robotis_manipulator::log::warn(STRING str)\n{\n#if defined(__OPENCR__)\n  DEBUG.print(\"[WARN] \");\n  DEBUG.println(str);\n#else\n  printf(ANSI_COLOR_YELLOW);\n  printf(\"[WARN] %s\\n\", str.c_str());\n  printf(ANSI_COLOR_RESET);\n#endif\n}\nvoid robotis_manipulator::log::warn(STRING str, double data, uint8_t decimal_point)\n{\n#if defined(__OPENCR__)\n  DEBUG.print(\"[WARN] \");\n  DEBUG.print(str);\n  DEBUG.println(data, decimal_point);\n#else\n  printf(ANSI_COLOR_YELLOW);\n  printf(\"[WARN] %s %.*lf\\n\",str.c_str(), decimal_point, data);\n  printf(ANSI_COLOR_RESET);\n#endif\n}\nvoid robotis_manipulator::log::warn(const char* str)\n{\n#if defined(__OPENCR__)\n  DEBUG.print(\"[WARN] \");\n  DEBUG.println(str);\n#else\n  printf(ANSI_COLOR_YELLOW);\n  printf(\"[WARN] %s\\n\", str);\n  printf(ANSI_COLOR_RESET);\n#endif\n}\nvoid robotis_manipulator::log::warn(const char* str, double data, uint8_t decimal_point)\n{\n#if defined(__OPENCR__)\n  DEBUG.print(\"[WARN] \");\n  DEBUG.print(str);\n  DEBUG.println(data, decimal_point);\n#else\n  printf(ANSI_COLOR_YELLOW);\n  printf(\"[WARN] %s %.*lf\\n\", str, decimal_point, data);\n  printf(ANSI_COLOR_RESET);\n#endif\n}\nvoid robotis_manipulator::log::error(STRING str)\n{\n#if defined(__OPENCR__)\n  DEBUG.print(\"[ERROR] \");\n  DEBUG.println(str);\n#else\n  printf(ANSI_COLOR_RED);\n  printf(\"[ERROR] %s\\n\", str.c_str());\n  printf(ANSI_COLOR_RESET);\n#endif\n}\nvoid robotis_manipulator::log::error(STRING str, double data, uint8_t decimal_point)\n{\n#if defined(__OPENCR__)\n  DEBUG.print(\"[ERROR] \");\n  DEBUG.print(str);\n  DEBUG.println(data, decimal_point);\n#else\n  printf(ANSI_COLOR_RED);\n  printf(\"[ERROR] %s %.*lf\\n\", str.c_str(), decimal_point, data);\n  printf(ANSI_COLOR_RESET);\n#endif\n}\n\nvoid robotis_manipulator::log::error(const char* str)\n{\n#if defined(__OPENCR__)\n  DEBUG.print(\"[ERROR] \");\n  DEBUG.println(str);\n#else\n  printf(ANSI_COLOR_RED);\n  printf(\"[ERROR] %s\\n\", str);\n  printf(ANSI_COLOR_RESET);\n#endif\n}\nvoid robotis_manipulator::log::error(const char* str, double data, uint8_t decimal_point)\n{\n#if defined(__OPENCR__)\n  DEBUG.print(\"[ERROR] \");\n  DEBUG.print(str);\n  DEBUG.println(data, decimal_point);\n#else\n  printf(ANSI_COLOR_RED);\n  printf(\"[ERROR] %s %.*lf\\n\", str, decimal_point, data);\n  printf(ANSI_COLOR_RESET);\n#endif\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RobotisManipulator/src/robotis_manipulator/robotis_manipulator_manager.cpp",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include \"../../include/robotis_manipulator/robotis_manipulator_manager.h\"\n\nusing namespace robotis_manipulator;\n\nbool JointActuator::findId(uint8_t actuator_id)\n{\n  std::vector<uint8_t> id = getId();\n  for(uint32_t index = 0; index < id.size(); index++)\n  {\n    if(id.at(index) == actuator_id)\n      return true;\n  }\n  return false;\n}\n\nbool JointActuator::getEnabledState()\n{\n  return enabled_state_;\n}\n\nbool ToolActuator::findId(uint8_t actuator_id)\n{\n  if(getId() == actuator_id)\n  {\n    return true;\n  }\n  return false;\n}\n\nbool ToolActuator::getEnabledState()\n{\n  return enabled_state_;\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RobotisManipulator/src/robotis_manipulator/robotis_manipulator_math.cpp",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include \"../../include/robotis_manipulator/robotis_manipulator_math.h\"\n\n/*****************************************************************************\n** Make a Vector or Matrix\n*****************************************************************************/\nEigen::Vector3d robotis_manipulator::math::vector3(double v1, double v2, double v3)\n{\n  Eigen::Vector3d temp;\n  temp << v1, v2, v3;\n  return temp;\n}\n\nEigen::Matrix3d robotis_manipulator::math::matrix3(double m11, double m12, double m13,\n                        double m21, double m22, double m23,\n                        double m31, double m32, double m33)\n{\n  Eigen::Matrix3d temp;\n  temp << m11, m12, m13, m21, m22, m23, m31, m32, m33;\n  return temp;\n}\n\nEigen::Matrix3d robotis_manipulator::math::inertiaMatrix(double ixx, double ixy, double ixz , double iyy , double iyz, double izz)\n{\n  Eigen::Matrix3d inertia;\n  inertia <<\n      ixx, ixy, ixz,\n      ixy, iyy, iyz,\n      ixz, iyz, izz;\n\n  return inertia;\n}\n\n\n/*****************************************************************************\n** Convert\n*****************************************************************************/\n// Translation Vector\nEigen::Vector3d robotis_manipulator::math::convertXYZToVector(double x, double y, double z)\n{\n  Eigen::Vector3d position;\n  position << x, y, z;\n\n  return position;\n}\n\n//Rotation\nEigen::Matrix3d robotis_manipulator::math::convertRollAngleToRotationMatrix(double angle)\n{\n  Eigen::Matrix3d rotation(3,3);\n  rotation <<\n      1.0, 0.0, 0.0,\n      0.0, cos(angle), -sin(angle),\n      0.0, sin(angle), cos(angle);\n\n  return rotation;\n}\n\nEigen::Matrix3d robotis_manipulator::math::convertPitchAngleToRotationMatrix(double angle)\n{\n  Eigen::Matrix3d rotation(3,3);\n  rotation <<\n      cos(angle), 0.0, sin(angle),\n      0.0, 1.0, 0.0,\n      -sin(angle), 0.0, cos(angle);\n\n  return rotation;\n}\n\nEigen::Matrix3d robotis_manipulator::math::convertYawAngleToRotationMatrix(double angle)\n{\n  Eigen::Matrix3d rotation(3,3);\n  rotation <<\n      cos(angle), -sin(angle), 0.0,\n      sin(angle), cos(angle), 0.0,\n      0.0, 0.0, 1.0;\n\n  return rotation;\n}\n\nEigen::Vector3d robotis_manipulator::math::convertRotationMatrixToRPYVector(const Eigen::Matrix3d& rotation)\n{\n  Eigen::Vector3d rpy;// = Eigen::MatrixXd::Zero(3,1);\n  rpy.coeffRef(0,0) = atan2(rotation.coeff(2,1), rotation.coeff(2,2));\n  rpy.coeffRef(1,0) = atan2(-rotation.coeff(2,0), sqrt(pow(rotation.coeff(2,1), 2) + pow(rotation.coeff(2,2),2)));\n  rpy.coeffRef(2,0) = atan2 (rotation.coeff(1,0), rotation.coeff(0,0));\n\n  return rpy;\n}\n\nEigen::Matrix3d robotis_manipulator::math::convertRPYToRotationMatrix(double roll, double pitch, double yaw)\n{\n  Eigen::Matrix3d rotation = robotis_manipulator::math::convertYawAngleToRotationMatrix(yaw)*robotis_manipulator::math::convertPitchAngleToRotationMatrix(pitch)*robotis_manipulator::math::convertRollAngleToRotationMatrix(roll);\n\n  return rotation;\n}\n\nEigen::Quaterniond robotis_manipulator::math::convertRPYToQuaternion(double roll, double pitch, double yaw)\n{\n Eigen::Quaterniond quaternion;\n quaternion = robotis_manipulator::math::convertRPYToRotationMatrix(roll,pitch,yaw);\n\n return quaternion;\n}\n\nEigen::Quaterniond robotis_manipulator::math::convertRotationMatrixToQuaternion(const Eigen::Matrix3d& rotation)\n{\n  Eigen::Quaterniond quaternion;\n  quaternion = rotation;\n\n  return quaternion;\n}\n\nEigen::Vector3d robotis_manipulator::math::convertQuaternionToRPYVector(const Eigen::Quaterniond& quaternion)\n{\n  Eigen::Vector3d rpy = robotis_manipulator::math::convertRotationMatrixToRPYVector(quaternion.toRotationMatrix());\n\n  return rpy;\n}\n\nEigen::Matrix3d robotis_manipulator::math::convertQuaternionToRotationMatrix(const Eigen::Quaterniond& quaternion)\n{\n  Eigen::Matrix3d rotation = quaternion.toRotationMatrix();\n\n  return rotation;\n}\n\nEigen::Vector3d robotis_manipulator::math::convertRotationMatrixToOmega(const Eigen::Matrix3d& rotation_matrix)\n{\n  return robotis_manipulator::math::matrixLogarithm(rotation_matrix);\n}\n\n// Transformation Matrix\nEigen::Matrix4d robotis_manipulator::math::convertXYZRPYToTransformationMatrix(double position_x, double position_y, double position_z , double roll , double pitch , double yaw)\n{\n  Eigen::Matrix4d transformation = robotis_manipulator::math::convertRPYToTransformationMatrix(roll, pitch, yaw);\n  transformation.coeffRef(0,3) = position_x;\n  transformation.coeffRef(1,3) = position_y;\n  transformation.coeffRef(2,3) = position_z;\n\n  return transformation;\n}\n\nEigen::Matrix4d robotis_manipulator::math::convertXYZToTransformationMatrix(double position_x, double position_y, double position_z)\n{\n  Eigen::Matrix4d mat_translation;\n\n  mat_translation <<\n      1, 0, 0, position_x,\n      0, 1, 0, position_y,\n      0, 0, 1, position_z,\n      0, 0, 0,          1;\n\n  return mat_translation;\n}\n\nEigen::Matrix4d robotis_manipulator::math::convertRPYToTransformationMatrix(double roll, double pitch, double yaw )\n{\n  double sr = sin(roll), cr = cos(roll);\n  double sp = sin(pitch), cp = cos(pitch);\n  double sy = sin(yaw), cy = cos(yaw);\n\n  Eigen::Matrix4d mat_roll;\n  Eigen::Matrix4d mat_pitch;\n  Eigen::Matrix4d mat_yaw;\n\n  mat_roll <<\n      1, 0, 0, 0,\n      0, cr, -sr, 0,\n      0, sr, cr, 0,\n      0, 0, 0, 1;\n\n  mat_pitch <<\n      cp, 0, sp, 0,\n      0, 1, 0, 0,\n      -sp, 0, cp, 0,\n      0, 0, 0, 1;\n\n  mat_yaw <<\n      cy, -sy, 0, 0,\n      sy, cy, 0, 0,\n      0, 0, 1, 0,\n      0, 0, 0, 1;\n\n  Eigen::Matrix4d mat_rpy = (mat_yaw*mat_pitch)*mat_roll;\n\n  return mat_rpy;\n}\n\nEigen::Matrix4d robotis_manipulator::math::inverseTransformationMatrix(const Eigen::MatrixXd& transform)\n{\n  // If T is Transform Matrix A from B, the BOA is translation component coordi. B to coordi. A\n\n  Eigen::Vector3d vec_boa;\n  Eigen::Vector3d vec_x, vec_y, vec_z;\n  Eigen::Matrix4d inv_t;\n\n  vec_boa(0) = -transform(0,3);\n  vec_boa(1) = -transform(1,3);\n  vec_boa(2) = -transform(2,3);\n\n  vec_x(0) = transform(0,0); vec_x(1) = transform(1,0); vec_x(2) = transform(2,0);\n  vec_y(0) = transform(0,1); vec_y(1) = transform(1,1); vec_y(2) = transform(2,1);\n  vec_z(0) = transform(0,2); vec_z(1) = transform(1,2); vec_z(2) = transform(2,2);\n\n  inv_t <<\n      vec_x(0), vec_x(1), vec_x(2), vec_boa.dot(vec_x),\n      vec_y(0), vec_y(1), vec_y(2), vec_boa.dot(vec_y),\n      vec_z(0), vec_z(1), vec_z(2), vec_boa.dot(vec_z),\n      0, 0, 0, 1;\n\n  return inv_t;\n}\n\n//Dynamic value\nEigen::Vector3d robotis_manipulator::math::convertOmegaToRPYVelocity(Eigen::Vector3d rpy_vector, Eigen::Vector3d omega)\n{\n  Eigen::Matrix3d c_inverse;\n  Eigen::Vector3d rpy_velocity;\n\n  c_inverse << 1, sin(rpy_vector(0))*tan(rpy_vector(1)), cos(rpy_vector(0))*tan(rpy_vector(1)),\n       0, cos(rpy_vector(0)),                    -sin(rpy_vector(0)),\n       0, sin(rpy_vector(0))/cos(rpy_vector(1)), cos(rpy_vector(0))/cos(rpy_vector(1));\n\n  rpy_velocity = c_inverse * omega;\n  return rpy_velocity;\n}\n\nEigen::Vector3d robotis_manipulator::math::convertRPYVelocityToOmega(Eigen::Vector3d rpy_vector, Eigen::Vector3d rpy_velocity)\n{\n  Eigen::Matrix3d c;\n  Eigen::Vector3d omega;\n\n  c << 1, 0,                     -sin(rpy_vector(1)),\n        0, cos(rpy_vector(0)),    sin(rpy_vector(0))*cos(rpy_vector(1)),\n        0, -sin(rpy_vector(0)), cos(rpy_vector(0))*cos(rpy_vector(1));\n\n  omega = c * rpy_velocity;\n  return omega;\n}\n\nEigen::Vector3d robotis_manipulator::math::convertOmegaDotToRPYAcceleration(Eigen::Vector3d rpy_vector, Eigen::Vector3d rpy_velocity, Eigen::Vector3d omega_dot)\n{\n  Eigen::Vector3d c_dot;\n  Eigen::Matrix3d c_inverse;\n  Eigen::Vector3d rpy_acceleration;\n\n  c_dot << -cos(rpy_vector[1]) * rpy_velocity[1] * rpy_velocity[2],\n           -sin(rpy_vector[0]) * rpy_velocity[0] * rpy_velocity[1] - sin(rpy_vector[0]) * sin(rpy_vector[1]) * rpy_velocity[1] * rpy_velocity[2] + cos(rpy_vector[0]) * cos(rpy_vector[1]) * rpy_velocity[0] * rpy_velocity[2],\n           -cos(rpy_vector[0]) * rpy_velocity[0] * rpy_velocity[1] - sin(rpy_vector[0]) * cos(rpy_vector[1]) * rpy_velocity[0] * rpy_velocity[2] - cos(rpy_vector[0]) * sin(rpy_vector[1]) * rpy_velocity[1] * rpy_velocity[2];\n\n  c_inverse << 1, sin(rpy_vector(0))*tan(rpy_vector(1)), cos(rpy_vector(0))*tan(rpy_vector(1)),\n       0, cos(rpy_vector(0)),                    -sin(rpy_vector(0)),\n       0, sin(rpy_vector(0))/cos(rpy_vector(1)), cos(rpy_vector(0))/cos(rpy_vector(1));\n\n  rpy_acceleration = c_inverse * (omega_dot - c_dot);\n  return rpy_acceleration;\n}\n\nEigen::Vector3d robotis_manipulator::math::convertRPYAccelerationToOmegaDot(Eigen::Vector3d rpy_vector, Eigen::Vector3d rpy_velocity, Eigen::Vector3d rpy_acceleration)\n{\n  Eigen::Vector3d c_dot;\n  Eigen::Matrix3d c;\n  Eigen::Vector3d omega_dot;\n\n  c_dot << -cos(rpy_vector[1]) * rpy_velocity[1] * rpy_velocity[2],\n           -sin(rpy_vector[0]) * rpy_velocity[0] * rpy_velocity[1] - sin(rpy_vector[0]) * sin(rpy_vector[1]) * rpy_velocity[1] * rpy_velocity[2] + cos(rpy_vector[0]) * cos(rpy_vector[1]) * rpy_velocity[0] * rpy_velocity[2],\n           -cos(rpy_vector[0]) * rpy_velocity[0] * rpy_velocity[1] - sin(rpy_vector[0]) * cos(rpy_vector[1]) * rpy_velocity[0] * rpy_velocity[2] - cos(rpy_vector[0]) * sin(rpy_vector[1]) * rpy_velocity[1] * rpy_velocity[2];\n\n  c << 1, 0,                     -sin(rpy_vector(1)),\n        0, cos(rpy_vector(0)),    sin(rpy_vector(0))*cos(rpy_vector(1)),\n        0, -sin(rpy_vector(0)), cos(rpy_vector(0))*cos(rpy_vector(1));\n\n  omega_dot = c_dot + c * rpy_acceleration;\n  return omega_dot;\n}\n\n\n/*****************************************************************************\n** Math\n*****************************************************************************/\ndouble robotis_manipulator::math::sign(double value)\n{\n  if (value >= 0.0)\n  {\n    return 1.0;\n  }\n  else\n  {\n    return -1.0;\n  }\n}\n\nEigen::Vector3d robotis_manipulator::math::matrixLogarithm(Eigen::Matrix3d rotation_matrix)\n{\n  Eigen::Matrix3d R = rotation_matrix;\n  Eigen::Vector3d l = Eigen::Vector3d::Zero();\n  Eigen::Vector3d rotation_vector = Eigen::Vector3d::Zero();\n\n  double theta = 0.0;\n  // double diag = 0.0;\n  bool diagonal_matrix = R.isDiagonal();\n\n  l << R(2, 1) - R(1, 2),\n      R(0, 2) - R(2, 0),\n      R(1, 0) - R(0, 1);\n  theta = atan2(l.norm(), R(0, 0) + R(1, 1) + R(2, 2) - 1);\n  // diag = R.determinant();\n\n  if (R.isIdentity())\n  {\n    rotation_vector.setZero(3);\n    return rotation_vector;\n  }\n  \n  if (diagonal_matrix == true)\n  {\n    rotation_vector << R(0, 0) + 1, R(1, 1) + 1, R(2, 2) + 1;\n    rotation_vector = rotation_vector * M_PI_2;\n  }\n  else\n  {\n    rotation_vector = theta * (l / l.norm());\n  }\n  return rotation_vector;\n}\n\nEigen::Matrix3d robotis_manipulator::math::skewSymmetricMatrix(Eigen::Vector3d v)\n{\n  Eigen::Matrix3d skew_symmetric_matrix = Eigen::Matrix3d::Zero();\n  skew_symmetric_matrix << 0, -v(2), v(1),\n      v(2), 0, -v(0),\n      -v(1), v(0), 0;\n  return skew_symmetric_matrix;\n}\n\nEigen::Matrix3d robotis_manipulator::math::rodriguesRotationMatrix(Eigen::Vector3d axis, double angle)\n{\n  Eigen::Matrix3d skew_symmetric_matrix = Eigen::Matrix3d::Zero();\n  Eigen::Matrix3d rotation_matrix = Eigen::Matrix3d::Zero();\n  Eigen::Matrix3d Identity_matrix = Eigen::Matrix3d::Identity();\n\n  skew_symmetric_matrix = robotis_manipulator::math::skewSymmetricMatrix(axis);\n  rotation_matrix = Identity_matrix +\n                    skew_symmetric_matrix * sin(angle) +\n                    skew_symmetric_matrix * skew_symmetric_matrix * (1 - cos(angle));\n  return rotation_matrix;\n}\n\nEigen::Vector3d robotis_manipulator::math::positionDifference(Eigen::Vector3d desired_position, Eigen::Vector3d present_position)\n{\n  Eigen::Vector3d position_difference;\n  position_difference = desired_position - present_position;\n\n  return position_difference;\n}\n\nEigen::Vector3d robotis_manipulator::math::orientationDifference(Eigen::Matrix3d desired_orientation, Eigen::Matrix3d present_orientation)\n{\n  Eigen::Vector3d orientation_difference;\n  orientation_difference = present_orientation * robotis_manipulator::math::matrixLogarithm(present_orientation.transpose() * desired_orientation);\n\n  return orientation_difference;\n}\n\nEigen::VectorXd robotis_manipulator::math::poseDifference(Eigen::Vector3d desired_position, Eigen::Vector3d present_position,\n                              Eigen::Matrix3d desired_orientation, Eigen::Matrix3d present_orientation)\n{\n  Eigen::Vector3d position_difference;\n  Eigen::Vector3d orientation_difference;\n  Eigen::VectorXd pose_difference(6);\n\n  position_difference = robotis_manipulator::math::positionDifference(desired_position, present_position);\n  orientation_difference = robotis_manipulator::math::orientationDifference(desired_orientation, present_orientation);\n  pose_difference << position_difference(0), position_difference(1), position_difference(2),\n      orientation_difference(0), orientation_difference(1), orientation_difference(2);\n\n  return pose_difference;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/RobotisManipulator/src/robotis_manipulator/robotis_manipulator_trajectory_generator.cpp",
    "content": "﻿/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Darby Lim, Hye-Jong KIM, Ryan Shim, Yong-Ho Na */\n\n#include \"../../include/robotis_manipulator/robotis_manipulator_trajectory_generator.h\"\n\nusing namespace robotis_manipulator;\n\nMinimumJerk::MinimumJerk()\n{\n  coefficient_ = Eigen::VectorXd::Zero(6);\n}\n\nMinimumJerk::~MinimumJerk() {}\n\nvoid MinimumJerk::calcCoefficient(Point start,\n                                  Point goal,\n                                  double move_time)\n{\n  Eigen::Matrix3d A = Eigen::Matrix3d::Identity(3, 3);\n  Eigen::Vector3d x = Eigen::Vector3d::Zero();\n  Eigen::Vector3d b = Eigen::Vector3d::Zero();\n\n  A << pow(move_time, 3), pow(move_time, 4), pow(move_time, 5),\n      3 * pow(move_time, 2), 4 * pow(move_time, 3), 5 * pow(move_time, 4),\n      6 * pow(move_time, 1), 12 * pow(move_time, 2), 20 * pow(move_time, 3);\n\n  coefficient_(0) = start.position;\n  coefficient_(1) = start.velocity;\n  coefficient_(2) = 0.5 * start.acceleration;\n\n  b << (goal.position - start.position - (start.velocity * move_time + 0.5 * start.acceleration * pow(move_time, 2))),\n      (goal.velocity - start.velocity - (start.acceleration * move_time)),\n      (goal.acceleration - start.acceleration);\n\n  Eigen::ColPivHouseholderQR<Eigen::Matrix3d> dec(A);\n  x = dec.solve(b);\n\n  coefficient_(3) = x(0);\n  coefficient_(4) = x(1);\n  coefficient_(5) = x(2);\n}\n\nEigen::VectorXd MinimumJerk::getCoefficient()\n{\n  return coefficient_;\n}\n\n//-------------------- Joint trajectory --------------------//\n\nJointTrajectory::JointTrajectory()\n{}\n\nJointTrajectory::~JointTrajectory() {}\n\nvoid JointTrajectory::makeJointTrajectory(double move_time, JointWaypoint start,\n                           JointWaypoint goal)\n{\n  coefficient_size_ = start.size();\n  minimum_jerk_coefficient_.resize(6,coefficient_size_);\n  for (uint8_t index = 0; index < coefficient_size_; index++)\n  {\n    minimum_jerk_trajectory_generator_.calcCoefficient(start.at(index),\n                                    goal.at(index),\n                                    move_time);\n\n    minimum_jerk_coefficient_.col(index) = minimum_jerk_trajectory_generator_.getCoefficient();\n  }\n}\n\nJointWaypoint JointTrajectory::getJointWaypoint(double tick)\n{\n  JointWaypoint joint_way_point;\n  for (uint8_t index = 0; index < coefficient_size_; index++)\n  {\n    JointValue single_joint_way_point;\n\n    single_joint_way_point.position = minimum_jerk_coefficient_(0, index) +\n             minimum_jerk_coefficient_(1, index) * pow(tick, 1) +\n             minimum_jerk_coefficient_(2, index) * pow(tick, 2) +\n             minimum_jerk_coefficient_(3, index) * pow(tick, 3) +\n             minimum_jerk_coefficient_(4, index) * pow(tick, 4) +\n             minimum_jerk_coefficient_(5, index) * pow(tick, 5);\n\n    single_joint_way_point.velocity = minimum_jerk_coefficient_(1, index) +\n             2 * minimum_jerk_coefficient_(2, index) * pow(tick, 1) +\n             3 * minimum_jerk_coefficient_(3, index) * pow(tick, 2) +\n             4 * minimum_jerk_coefficient_(4, index) * pow(tick, 3) +\n             5 * minimum_jerk_coefficient_(5, index) * pow(tick, 4);\n\n    single_joint_way_point.acceleration = 2 * minimum_jerk_coefficient_(2, index) +\n             6 * minimum_jerk_coefficient_(3, index) * pow(tick, 1) +\n             12 * minimum_jerk_coefficient_(4, index) * pow(tick, 2) +\n             20 * minimum_jerk_coefficient_(5, index) * pow(tick, 3);\n\n    single_joint_way_point.effort = 0.0;\n\n    joint_way_point.push_back(single_joint_way_point);\n  }\n\n  return joint_way_point;\n}\n\nEigen::MatrixXd JointTrajectory::getMinimumJerkCoefficient()\n{\n  return minimum_jerk_coefficient_;\n}\n\n//-------------------- Task trajectory --------------------//\n\nTaskTrajectory::TaskTrajectory()\n{\n  minimum_jerk_coefficient_ = Eigen::MatrixXd::Identity(6, 4);\n}\nTaskTrajectory::~TaskTrajectory() {}\n\nvoid TaskTrajectory::makeTaskTrajectory(double move_time, TaskWaypoint start,\n                           TaskWaypoint goal)\n{\n  std::vector<Point> start_way_point;\n  std::vector<Point> goal_way_point;\n\n  ////////////////////////////////////position////////////////////////////////////\n  for(uint8_t i = 0; i < 3; i++)      //x, y, z\n  {\n    Point position_temp;\n    position_temp.position = start.kinematic.position[i];\n    position_temp.velocity = start.dynamic.linear.velocity[i];\n    position_temp.acceleration = start.dynamic.linear.acceleration[i];\n    position_temp.effort = 0.0;\n    start_way_point.push_back(position_temp);\n\n    position_temp.position = goal.kinematic.position[i];\n    position_temp.velocity = goal.dynamic.linear.velocity[i];\n    position_temp.acceleration = goal.dynamic.linear.acceleration[i];\n    position_temp.effort = 0.0;\n    goal_way_point.push_back(position_temp);\n  }\n  ////////////////////////////////////////////////////////////////////////////////\n\n  //////////////////////////////////orientation///////////////////////////////////\n\n  Eigen::Vector3d start_orientation_rpy;\n  Eigen::Vector3d start_ang_vel_rpy;\n  Eigen::Vector3d start_ang_acc_rpy;\n\n  start_orientation_rpy = math::convertRotationMatrixToRPYVector(start.kinematic.orientation);\n  start_ang_vel_rpy = math::convertOmegaToRPYVelocity(start_orientation_rpy, start.dynamic.angular.velocity);\n  start_ang_acc_rpy = math::convertOmegaDotToRPYAcceleration(start_orientation_rpy, start_ang_vel_rpy, start.dynamic.angular.acceleration);\n\n  Eigen::Vector3d goal_orientation_rpy;\n  Eigen::Vector3d goal_ang_vel_rpy;\n  Eigen::Vector3d goal_ang_acc_rpy;\n\n  goal_orientation_rpy = math::convertRotationMatrixToRPYVector(goal.kinematic.orientation);\n  goal_ang_vel_rpy = math::convertOmegaToRPYVelocity(goal_orientation_rpy, goal.dynamic.angular.velocity);\n  start_ang_acc_rpy = math::convertOmegaDotToRPYAcceleration(goal_orientation_rpy, goal_ang_vel_rpy, goal.dynamic.angular.acceleration);\n\n  for(uint8_t i = 0; i < 3; i++)    //roll, pitch, yaw\n  {\n    Point orientation_temp;\n    orientation_temp.position = start_orientation_rpy[i];\n    orientation_temp.velocity = start_ang_vel_rpy[i];\n    orientation_temp.acceleration = start_ang_acc_rpy[i];\n    orientation_temp.effort = 0.0;\n    start_way_point.push_back(orientation_temp);\n\n    orientation_temp.position = goal_orientation_rpy[i];\n    orientation_temp.velocity = goal_ang_vel_rpy[i];\n    orientation_temp.acceleration = goal_ang_acc_rpy[i];\n    orientation_temp.effort = 0.0;\n    goal_way_point.push_back(orientation_temp);\n  }\n  ////////////////////////////////////////////////////////////////////////////////\n\n  coefficient_size_ = start_way_point.size();\n  minimum_jerk_coefficient_.resize(6,coefficient_size_);\n  for (uint8_t index = 0; index < coefficient_size_; index++)\n  {\n    minimum_jerk_trajectory_generator_.calcCoefficient(start_way_point.at(index),\n                                    goal_way_point.at(index),\n                                    move_time);\n\n    minimum_jerk_coefficient_.col(index) = minimum_jerk_trajectory_generator_.getCoefficient();\n  }\n}\n\nTaskWaypoint TaskTrajectory::getTaskWaypoint(double tick)\n{\n  std::vector<Point> result_point;\n  for (uint8_t index = 0; index < coefficient_size_; index++)\n  {\n    Point single_task_way_point;\n\n    single_task_way_point.position = minimum_jerk_coefficient_(0, index) +\n             minimum_jerk_coefficient_(1, index) * pow(tick, 1) +\n             minimum_jerk_coefficient_(2, index) * pow(tick, 2) +\n             minimum_jerk_coefficient_(3, index) * pow(tick, 3) +\n             minimum_jerk_coefficient_(4, index) * pow(tick, 4) +\n             minimum_jerk_coefficient_(5, index) * pow(tick, 5);\n\n    single_task_way_point.velocity = minimum_jerk_coefficient_(1, index) +\n             2 * minimum_jerk_coefficient_(2, index) * pow(tick, 1) +\n             3 * minimum_jerk_coefficient_(3, index) * pow(tick, 2) +\n             4 * minimum_jerk_coefficient_(4, index) * pow(tick, 3) +\n             5 * minimum_jerk_coefficient_(5, index) * pow(tick, 4);\n\n    single_task_way_point.acceleration = 2 * minimum_jerk_coefficient_(2, index) +\n             6 * minimum_jerk_coefficient_(3, index) * pow(tick, 1) +\n             12 * minimum_jerk_coefficient_(4, index) * pow(tick, 2) +\n             20 * minimum_jerk_coefficient_(5, index) * pow(tick, 3);\n\n    single_task_way_point.effort = 0.0;\n\n    result_point.push_back(single_task_way_point);\n  }\n\n  TaskWaypoint task_way_point;\n  ////////////////////////////////////position////////////////////////////////////\n  for(uint8_t i = 0; i < 3; i++)        //x ,y ,z\n  {\n    task_way_point.kinematic.position[i] = result_point.at(i).position;\n    task_way_point.dynamic.linear.velocity[i] = result_point.at(i).velocity;\n    task_way_point.dynamic.linear.acceleration[i] = result_point.at(i).acceleration;\n  }\n  ////////////////////////////////////////////////////////////////////////////////\n\n  //////////////////////////////////orientation///////////////////////////////////\n  Eigen::Vector3d rpy_orientation;\n  rpy_orientation << result_point.at(3).position, result_point.at(4).position, result_point.at(5).position;\n  task_way_point.kinematic.orientation = math::convertRPYToRotationMatrix(result_point.at(3).position,   //roll\n                                                                       result_point.at(4).position,   //pitch\n                                                                       result_point.at(5).position);   //yaw\n\n  Eigen::Vector3d rpy_velocity;\n  rpy_velocity << result_point.at(3).velocity, result_point.at(4).velocity, result_point.at(5).velocity;\n  task_way_point.dynamic.angular.velocity = math::convertRPYVelocityToOmega(rpy_orientation, rpy_velocity);\n\n  Eigen::Vector3d rpy_acceleration;\n  rpy_acceleration << result_point.at(3).acceleration, result_point.at(4).acceleration, result_point.at(5).acceleration;\n  task_way_point.dynamic.angular.acceleration = math::convertRPYAccelerationToOmegaDot(rpy_orientation, rpy_velocity, rpy_acceleration);\n\n  return task_way_point;\n}\n\nEigen::MatrixXd TaskTrajectory::getMinimumJerkCoefficient()\n{\n  return minimum_jerk_coefficient_;\n}\n\n\n/*****************************************************************************\n** Trajectory Class\n*****************************************************************************/\nvoid Trajectory::setMoveTime(double move_time)\n{\n  trajectory_time_.total_move_time = move_time;\n}\n\nvoid Trajectory::setPresentTime(double present_time)\n{\n  trajectory_time_.present_time = present_time;\n}\n\nvoid Trajectory::setStartTimeToPresentTime()\n{\n  trajectory_time_.start_time = trajectory_time_.present_time;\n}\n\nvoid Trajectory::setStartTime(double start_time)\n{\n  trajectory_time_.start_time = start_time;\n}\n\ndouble Trajectory::getMoveTime()\n{\n  return trajectory_time_.total_move_time;\n}\n\ndouble Trajectory::getTickTime()\n{\n  return trajectory_time_.present_time - trajectory_time_.start_time;\n}\n\nvoid Trajectory::setManipulator(Manipulator manipulator)\n{\n  manipulator_= manipulator;\n}\n\nManipulator* Trajectory::getManipulator()\n{\n  return &manipulator_;\n}\n\nJointTrajectory Trajectory::getJointTrajectory()\n{\n  return joint_;\n}\n\nTaskTrajectory Trajectory::getTaskTrajectory()\n{\n  return task_;\n}\n\nCustomJointTrajectory *Trajectory::getCustomJointTrajectory(Name name)\n{\n  return cus_joint_.at(name);\n}\n\nCustomTaskTrajectory *Trajectory::getCustomTaskTrajectory(Name name)\n{\n  return cus_task_.at(name);\n}\n\nvoid Trajectory::addCustomTrajectory(Name trajectory_name, CustomJointTrajectory *custom_trajectory)\n{\n  cus_joint_.insert(std::make_pair(trajectory_name, custom_trajectory));\n}\n\nvoid Trajectory::addCustomTrajectory(Name trajectory_name, CustomTaskTrajectory *custom_trajectory)\n{\n  cus_task_.insert(std::make_pair(trajectory_name, custom_trajectory));\n}\n\nvoid Trajectory::setCustomTrajectoryOption(Name trajectory_name, const void* arg)\n{\n  if(cus_joint_.find(trajectory_name) != cus_joint_.end())\n    cus_joint_.at(trajectory_name)->setOption(arg);\n  else if(cus_task_.find(trajectory_name) != cus_task_.end())\n    cus_task_.at(trajectory_name)->setOption(arg);\n}\n\nvoid Trajectory::setPresentControlToolName(Name present_control_tool_name)\n{\n  present_control_tool_name_ = present_control_tool_name;\n}\n\nName Trajectory::getPresentCustomTrajectoryName()\n{\n  return present_custom_trajectory_name_;\n}\n\nName Trajectory::getPresentControlToolName()\n{\n return present_control_tool_name_;\n}\n\nvoid Trajectory::initTrajectoryWaypoint(Manipulator actual_manipulator, Kinematics *kinematics)\n{\n  setManipulator(actual_manipulator);\n  JointWaypoint joint_way_point_vector;\n  joint_way_point_vector = getManipulator()->getAllActiveJointValue();\n\n  setPresentJointWaypoint(joint_way_point_vector);\n  updatePresentWaypoint(kinematics);\n}\n\nvoid Trajectory::updatePresentWaypoint(Kinematics *kinematics)\n{\n  //kinematics\n  kinematics->solveForwardKinematics(&manipulator_);\n}\n\nvoid Trajectory::setPresentJointWaypoint(JointWaypoint joint_value_vector)\n{\n  manipulator_.setAllActiveJointValue(joint_value_vector);\n}\n\nvoid Trajectory::setPresentTaskWaypoint(Name tool_name, TaskWaypoint tool_value_vector)\n{\n  manipulator_.setComponentPoseFromWorld(tool_name, tool_value_vector);\n}\n\nJointWaypoint Trajectory::getPresentJointWaypoint()\n{\n  return manipulator_.getAllActiveJointValue();\n}\n\nTaskWaypoint Trajectory::getPresentTaskWaypoint(Name tool_name)\n{\n  return manipulator_.getComponentPoseFromWorld(tool_name);\n}\n\nJointWaypoint Trajectory::removeWaypointDynamicData(JointWaypoint value)\n{\n  for(uint32_t index =0; index < value.size(); index++)\n  {\n    value.at(index).velocity = 0.0;\n    value.at(index).acceleration = 0.0;\n    value.at(index).effort = 0.0;\n  }\n  return value;\n}\n\nTaskWaypoint Trajectory::removeWaypointDynamicData(TaskWaypoint value)\n{\n  value.dynamic.linear.velocity = Eigen::Vector3d::Zero(3);\n  value.dynamic.linear.acceleration = Eigen::Vector3d::Zero(3);\n  value.dynamic.angular.velocity = Eigen::Vector3d::Zero(3);\n  value.dynamic.angular.acceleration = Eigen::Vector3d::Zero(3);\n  return value;\n}\n\n\n//Trajectory\nvoid Trajectory::setTrajectoryType(TrajectoryType trajectory_type)\n{\n  trajectory_type_ = trajectory_type;\n}\n\nbool Trajectory::checkTrajectoryType(TrajectoryType trajectory_type)\n{\n  if(trajectory_type_==trajectory_type)\n    return true;\n  else\n    return false;\n}\n\nvoid Trajectory::makeJointTrajectory(JointWaypoint start_way_point, JointWaypoint goal_way_point)\n{\n  joint_.makeJointTrajectory(trajectory_time_.total_move_time, start_way_point, goal_way_point);\n}\n\nvoid Trajectory::makeTaskTrajectory(TaskWaypoint start_way_point, TaskWaypoint goal_way_point)\n{\n  task_.makeTaskTrajectory(trajectory_time_.total_move_time, start_way_point, goal_way_point);\n}\n\nvoid Trajectory::makeCustomTrajectory(Name trajectory_name, JointWaypoint start_way_point, const void *arg)\n{\n  if(cus_joint_.find(trajectory_name) != cus_joint_.end())\n  {\n    present_custom_trajectory_name_ = trajectory_name;\n    cus_joint_.at(trajectory_name)->makeJointTrajectory(trajectory_time_.total_move_time, start_way_point, arg);\n  }\n  else\n    log::error(\"[makeCustomTrajectory] Wrong way point type.\");\n}\n\nvoid Trajectory::makeCustomTrajectory(Name trajectory_name, TaskWaypoint start_way_point, const void *arg)\n{\n  if(cus_task_.find(trajectory_name) != cus_task_.end())\n  {\n    present_custom_trajectory_name_ = trajectory_name;\n    cus_task_.at(trajectory_name)->makeTaskTrajectory(trajectory_time_.total_move_time, start_way_point, arg);\n  }\n  else\n    log::error(\"[makeCustomTrajectory] Wrong way point type.\");\n}\n\n//tool\nvoid Trajectory::setToolGoalPosition(Name tool_name, double tool_goal_position)\n{\n  manipulator_.setJointPosition(tool_name, tool_goal_position);\n}\n\n\nvoid Trajectory::setToolGoalValue(Name tool_name, JointValue tool_goal_value)\n{\n  manipulator_.setJointValue(tool_name, tool_goal_value);\n}\n\ndouble Trajectory::getToolGoalPosition(Name tool_name)\n{\n  return manipulator_.getJointPosition(tool_name);\n}\n\nJointValue Trajectory::getToolGoalValue(Name tool_name)\n{\n  return manipulator_.getJointValue(tool_name);\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/SPI/EventResponder.cpp",
    "content": "/* EventResponder - Simple event-based programming for Arduino\n * Copyright 2017 Paul Stoffregen\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n * SOFTWARE.\n */\n\n/* EventResponder is an experimental API, almost certain to\n * incompatibly change as it develops.  Please understand any\n * programs you write now using EventResponder may need to be\n * updated as EventResponder develops.\n *\n * Please post EventResponder post your feedback here:\n *     https://forum.pjrc.com/threads/44723-Arduino-Events\n */\n\n#include <Arduino.h>\n#include \"EventResponder.h\"\n\n\nbool EventResponder::clearEvent()\n{\n\tbool ret = false;\n\tif (_triggered) {\n\t\t_triggered = false;\n\t\tret = true;\n\t}\n\treturn ret;\n}\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/SPI/EventResponder.h",
    "content": "/* EventResponder - Simple event-based programming for Arduino\n * Copyright 2017 Paul Stoffregen\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\n * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\n * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n * SOFTWARE.\n */\n\n/* EventResponder is an experimental API, almost certain to\n * incompatibly change as it develops.  Please understand any\n * programs you write now using EventResponder may need to be\n * updated as EventResponder develops.\n *\n * Please post your EventResponder feedback here:\n *     https://forum.pjrc.com/threads/44723-Arduino-Events\n */\n\n// This version was completely reduced to minimums for SPI...\n// By Kurt\n\n#if !defined(EventResponder_h) && defined(__cplusplus)\n#define EventResponder_h\n\n#include <Arduino.h>\n\n/* EventResponder lets you control how your program responds to an event.\n * Imagine a basketball or football (American soccer) player who gets the\n * ball.  Usually they will pass to another player who has the best\n * opportunity to score.  Similarly in Arduino programming, events are\n * often triggered within interrupts or other timing sensitive code.\n * EventResponder can call your function a short time later, giving you\n * the ability to use Arduino functions and libraries which would not\n * be safe to use from an interrupt.  However, some situations do call\n * for the most immediate response, even if doing so is more difficult.\n * EventResponder lets you choose how your function will be called,\n * without editing the timers or libraries which trigger the events.\n *\n * Event handling functions called by EventResponder should complete\n * their work quickly.  Avoid delays or operations which may take\n * substantial time.  While your function runs, no other event functions\n * (attached the same way) are able to run.\n *\n * If your EventResponder is triggered more than once before your\n * function can run, only the last trigger is used.  Prior triggering,\n * including the status integer and data pointer, are overwritten and\n * your function is called only one time, based on the last trigger\n * event.\n */\n\nclass EventResponder;\ntypedef EventResponder& EventResponderRef;\ntypedef void (*EventResponderFunction)(EventResponderRef);\nclass EventResponder\n{\npublic:\n\tEventResponder() {\n\t\t_status = 0;\n\t\t_function = NULL;\n\t\t_data = NULL;\n\t\t_context = NULL;\n\t\t_type = EventTypeDetached;\n\t\t_triggered = false;\n\t}\n\t~EventResponder() {\n\t\tdetach();\n\t}\n\tenum EventType { // these are not meant for public consumption...\n\t\tEventTypeDetached = 0, // no function is called\n\t\tEventTypeImmediate    // function is called immediately\n\t};\n\n\t// Attach a function to be called from yield().  This should be the\n\t// default way to use EventResponder.  Calls from yield() allow use\n\t// of Arduino libraries, String, Serial, etc.\n\tvoid attach(EventResponderFunction function, uint8_t priority=128) {\n\t\tUNUSED(priority);\n\t\t_function = function;\n\t\t_type = EventTypeImmediate;\n\t}\n\n\t// Attach a function to be called immediately.  This provides the\n\t// fastest possible response, but your function must be carefully\n\t// designed.\n\tvoid attachImmediate(EventResponderFunction function) {\n\t\t_function = function;\n\t\t_type = EventTypeImmediate;\n\t}\n\n\t// Do not call any function.  The user's program must occasionally check\n\t// whether the event has occurred, or use one of the wait functions.\n\tvoid detach() {\n\t}\n\n\t// Trigger the event.  An optional status code and data may be provided.\n\t// The code triggering the event does NOT control which of the above\n\t// response methods will be used.\n\tvirtual void triggerEvent(int status=0, void *data=NULL) {\n\t\t_status = status;\n\t\t_data = data;\n\t\tif (_type == EventTypeImmediate) {\n\t\t\t(*_function)(*this);\n\t\t} else {\n\t\t\t//triggerEventNotImmediate();\n\t\t}\n\t}\n\t// Clear an event which has been triggered, but has not yet caused a\n\t// function to be called.\n\tbool clearEvent();\n\n\t// Get the event's status code.  Typically this will indicate if the event was\n\t// triggered due to successful completion, or how much data was successfully\n\t// processed (positive numbers) or an error (negative numbers).  The\n\t// exact meaning of this status code depends on the code or library which\n\t// triggers the event.\n\tint getStatus() { return _status; }\n\n\t// Get the optional data pointer associated with the event.  Often this\n\t// will be NULL, or will be the object instance which triggered the event.\n\t// Some libraries may use this to pass data associated with the event.\n\tvoid * getData() { return _data; }\n\n\t// An optional \"context\" may be associated with each EventResponder.\n\t// When more than one EventResponder has the same function attached, these\n\t// may be used to allow the function to obtain extra information needed\n\t// depending on which EventResponder called it.\n\tvoid setContext(void *context) { _context = context; }\n\tvoid * getContext() { return _context; }\n\n\t// Wait for event(s) to occur.  These are most likely to be useful when\n\t// used with a scheduler or RTOS.\n\tbool waitForEvent(EventResponderRef event, int timeout);\n\tEventResponder * waitForEvent(EventResponder *list, int listsize, int timeout);\n\n\toperator bool() { return _triggered; }\nprotected:\n\tint _status;\n\tEventResponderFunction _function;\n\tvoid *_data;\n\tvoid *_context;\n\tEventType _type;\n\tbool _triggered;\nprivate:\n};\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/SPI/SPI.cpp",
    "content": "/****************************************************************************\r\n *\r\n * SPI Master library for Arduino STM32 + HAL + CubeMX (HALMX).\r\n *\r\n * Copyright (c) 2016 by Vassilis Serasidis <info@serasidis.gr>\r\n * Home: http://www.serasidis.gr\r\n * email: avrsite@yahoo.gr\r\n *\r\n * Arduino_STM32 forum: http://www.stm32duino.com\r\n *\r\n * This file is free software; you can redistribute it and/or modify\r\n * it under the terms of either the GNU General Public License version 2\r\n * or the GNU Lesser General Public License version 2.1, both as\r\n * published by the Free Software Foundation.\r\n *\r\n ****************************************************************************/\r\n\r\n\r\n#include <SPI.h>\r\n#include <chip.h>\r\n\r\n\r\n\r\n/* Create an SPIClass instance */\r\nSPIClass SPI    (SPI2, 50000000);\r\nSPIClass SPI_IMU(SPI1, 100000000);\r\nSPIClass SPI_EXT(SPI4, 100000000);\r\n\r\n\r\nSPIClass::SPIClass(SPI_TypeDef *spiPort, uint32_t spi_clock) {\r\n  _spiPort = spiPort;\r\n\r\n  if(spiPort == SPI1)\r\n    _hspi = &hspi1;\r\n  else if(spiPort == SPI2)\r\n    _hspi = &hspi2;\r\n  else if(spiPort == SPI4)\r\n    _hspi = &hspi4;\r\n  _spi_clock = spi_clock;\r\n}\r\n\r\n/**\r\n * This constructor is written for backward compatibility with Arduino_STM32\r\n * @Usage example: SPIClass my_spi(2) for using the SPI2 interface\r\n */\r\nSPIClass::SPIClass(uint8_t spiPort){\r\n  switch(spiPort){\r\n    case 1:\r\n      _spiPort = SPI1;\r\n      _hspi = &hspi1;\r\n    break;\r\n\r\n    case 2:\r\n      _spiPort = SPI2;\r\n      _hspi = &hspi2;\r\n    break;\r\n    case 4:\r\n      _spiPort = SPI4;\r\n      _hspi = &hspi4;\r\n    break;\r\n  }\r\n}\r\n\r\n\r\nvoid SPIClass::begin(void) {\r\n  init();\r\n}\r\n\r\nvoid SPIClass::beginFast(void) {\r\n  drv_spi_enable_dma(_hspi);\r\n  init();\r\n}\r\n\r\nvoid SPIClass::init(void){\r\n  // Keep track of transaction logical values.\r\n  //_clockDiv = SPI_CLOCK_DIV16;\r\n  _bitOrder = MSBFIRST;\r\n  _dataMode = SPI_MODE0;\r\n  _dma_state = DMA_NOTINITIALIZED;\r\n  _dma_event_responder   = NULL;\r\n  _hspi->Instance               = _spiPort;\r\n  _hspi->Init.Mode              = SPI_MODE_MASTER;\r\n  _hspi->Init.Direction         = SPI_DIRECTION_2LINES;\r\n  _hspi->Init.DataSize          = SPI_DATASIZE_8BIT;\r\n  _hspi->Init.CLKPolarity       = SPI_POLARITY_LOW;\r\n  _hspi->Init.CLKPhase          = SPI_PHASE_1EDGE;\r\n  _hspi->Init.NSS               = SPI_NSS_SOFT;\r\n  _hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16; // 4.5 Mbit\r\n  _hspi->Init.FirstBit          = SPI_FIRSTBIT_MSB;\r\n  _hspi->Init.TIMode            = SPI_TIMODE_DISABLE;\r\n  _hspi->Init.CRCCalculation    = SPI_CRCCALCULATION_DISABLE;\r\n  _hspi->Init.CRCPolynomial     = 10;\r\n  HAL_SPI_Init(_hspi);\r\n}\r\n\r\nvoid SPIClass::end()\r\n{\r\n  \r\n}\r\n\r\nuint8_t SPIClass::transfer(uint8_t data) const{\r\n  uint8_t ret;\r\n  HAL_SPI_TransmitReceive(_hspi, &data, &ret, 1, 0xffff);\r\n\treturn ret;\r\n}\r\n\r\nuint16_t SPIClass::transfer16(uint16_t data) {\r\n  uint8_t tBuf[2];\r\n  uint8_t rBuf[2];\r\n  uint16_t ret;\r\n  tBuf[1] = (uint8_t)data;\r\n  tBuf[0] = (uint8_t)(data>>8);\r\n  HAL_SPI_TransmitReceive(_hspi, (uint8_t *)&tBuf, (uint8_t *)&rBuf, 2, 0xffff);\r\n\r\n  ret = rBuf[0];\r\n  ret <<= 8;\r\n  ret += rBuf[1];\r\n\r\n  return ret;\r\n}\r\n\r\n\r\nvoid SPIClass::transfer(const void * buf, void * retbuf, size_t count) {\r\n  if ((count == 0) || ((buf == NULL) && (retbuf == NULL))) return;    // nothing to do\r\n\r\n//  bool dma_enabled = drv_spi_dma_enabled(_hspi);\r\n  HAL_StatusTypeDef status;\r\n  if (retbuf == NULL) { \r\n    // write only transfer\r\n    status = HAL_SPI_Transmit(_hspi, (uint8_t *)buf, count, 0xffff);\r\n  } else if (buf == NULL) {\r\n    // Read only buffer\r\n    status = HAL_SPI_Receive(_hspi, (uint8_t*)retbuf, count, 0xffff);\r\n  } else {\r\n    // standard Read/write buffer transfer\r\n    // start off without DMA support\r\n    status = HAL_SPI_TransmitReceive(_hspi, (uint8_t *)buf, (uint8_t*)retbuf, count, 0xffff);\r\n  }\r\n  if (status != HAL_OK) \r\n  {\r\n    Serial.print(\"transfer status: \");\r\n    Serial.println((int)status, DEC);\r\n  }\r\n}\r\n\r\n\r\n// Write only functions many used by Adafruit libraries.\r\n\r\nvoid SPIClass::write(uint8_t data) {\r\n  HAL_SPI_Transmit(_hspi, &data, 1, 0xffff);\r\n}\r\n\r\nvoid SPIClass::write16(uint16_t data) {\r\n  uint8_t tBuf[2];\r\n  tBuf[0] = (uint8_t)(data>>8);\r\n  tBuf[1] = (uint8_t)data;\r\n  HAL_SPI_Transmit(_hspi, tBuf, 2, 0xffff);\r\n}\r\n\r\nvoid SPIClass::write32(uint32_t data) {\r\n  uint8_t tBuf[4];\r\n  tBuf[0] = (uint8_t)(data>>24);\r\n  tBuf[1] = (uint8_t)(data>>16);\r\n  tBuf[2] = (uint8_t)(data>>8);\r\n  tBuf[3] = (uint8_t)data;\r\n  HAL_SPI_Transmit(_hspi, tBuf, 4, 0xffff);\r\n}\r\n\r\nvoid SPIClass::writeBytes(uint8_t * data, uint32_t size) {\r\n  HAL_SPI_Transmit(_hspi, data, size, 0xffff);\r\n}\r\n\r\nvoid SPIClass::writePixels(const void * data, uint32_t size) { //ili9341 compatible\r\n    // First pass a hack! need to reverse bytes... Use internal buffer.. \r\n    uint8_t tBuf[64];\r\n    uint16_t *pixels = (uint16_t *)data;\r\n\r\n    // size is the number of bytes. \r\n    while (size) {\r\n      uint8_t *pb = tBuf;\r\n\r\n      uint32_t cb = (size > 64)? 64 : size;\r\n\r\n      for (uint32_t i = 0; i < cb; i += 2) {\r\n        *pb++ = *pixels >> 8;\r\n        *pb++ = (uint8_t)*pixels;\r\n        pixels++;\r\n      }\r\n      HAL_SPI_Transmit(_hspi, tBuf, cb, 0xffff);\r\n      size -= cb; \r\n\r\n    }\r\n}\r\n\r\n\r\n\r\nvoid SPIClass::setBitOrder(uint8_t bitOrder) {\r\n  _bitOrder = bitOrder;\r\n  if (bitOrder == 1)\r\n    _hspi->Init.FirstBit = SPI_FIRSTBIT_MSB;\r\n  else\r\n    _hspi->Init.FirstBit = SPI_FIRSTBIT_LSB;\r\n    HAL_SPI_Init(_hspi);\r\n}\r\n\r\n\r\nvoid SPIClass::setClockDivider(uint8_t clockDiv) {\r\n  _clock = 0;   // clear out so we will set in setClock\r\n  switch(clockDiv){\r\n    case SPI_CLOCK_DIV2:\r\n      _hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;\r\n    break;\r\n    case SPI_CLOCK_DIV4:\r\n      _hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4;\r\n    break;\r\n    case SPI_CLOCK_DIV8:\r\n      _hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8;\r\n    break;\r\n    case SPI_CLOCK_DIV16:\r\n      _hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16;\r\n    break;\r\n    case SPI_CLOCK_DIV32:\r\n      _hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32;\r\n    break;\r\n    case SPI_CLOCK_DIV64:\r\n      _hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_64;\r\n    break;\r\n    case SPI_CLOCK_DIV128:\r\n      _hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_128;\r\n    break;\r\n    case SPI_CLOCK_DIV256:\r\n      _hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256;\r\n    break;\r\n  }\r\n  HAL_SPI_Init(_hspi);\r\n}\r\n\r\nvoid SPIClass::setClock(uint32_t clock) {\r\n  _clock = clock; // remember our new clock  \r\n  if (clock >= _spi_clock / 2) {\r\n    _hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;\r\n  } else if (clock >= _spi_clock / 4) {\r\n    _hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4;\r\n  } else if (clock >= _spi_clock / 8) {\r\n    _hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8;\r\n  } else if (clock >= _spi_clock / 16) {\r\n    _hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16;\r\n  } else if (clock >= _spi_clock / 32) {\r\n    _hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32;\r\n  } else if (clock >= _spi_clock / 64) {\r\n    _hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_64;\r\n  } else if (clock >= _spi_clock / 128) {\r\n    _hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_128;\r\n  } else {\r\n    _hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_128;  // Our slowest mode\r\n  }\r\n  HAL_SPI_Init(_hspi);\r\n}\r\n\r\nvoid SPIClass::setDataMode(uint8_t dataMode){\r\n\r\n  switch( dataMode )\r\n  {\r\n    _dataMode = dataMode;\r\n    // CPOL=0, CPHA=0\r\n    case SPI_MODE0:\r\n      _hspi->Init.CLKPolarity = SPI_POLARITY_LOW;\r\n      _hspi->Init.CLKPhase    = SPI_PHASE_1EDGE;\r\n      HAL_SPI_Init(_hspi);\r\n      break;\r\n\r\n    // CPOL=0, CPHA=1\r\n    case SPI_MODE1:\r\n      _hspi->Init.CLKPolarity = SPI_POLARITY_LOW;\r\n      _hspi->Init.CLKPhase    = SPI_PHASE_2EDGE;\r\n      HAL_SPI_Init(_hspi);\r\n      break;\r\n\r\n    // CPOL=1, CPHA=0\r\n    case SPI_MODE2:\r\n      _hspi->Init.CLKPolarity  = SPI_POLARITY_HIGH;\r\n      _hspi->Init.CLKPhase    = SPI_PHASE_1EDGE;\r\n      HAL_SPI_Init(_hspi);\r\n      break;\r\n\r\n    // CPOL=1, CPHA=1\r\n    case SPI_MODE3:\r\n      _hspi->Init.CLKPolarity  = SPI_POLARITY_HIGH;\r\n      _hspi->Init.CLKPhase    = SPI_PHASE_2EDGE;\r\n      HAL_SPI_Init(_hspi);\r\n      break;\r\n  }\r\n}\r\n//=========================================================================\r\n// Main Async Transfer function\r\n//=========================================================================\r\n\r\nbool SPIClass::transfer(const void *buf, void *retbuf, size_t count, EventResponderRef event_responder) {\r\n//    Serial.println(\"Transfer with Event Call\"); Serial.flush();\r\n  if (_dma_state == DMA_ACTIVE)\r\n    return false; // already active\r\n  else if (_dma_state == DMA_NOTINITIALIZED)\r\n  {\r\n//    Serial.println(\"Before SPI enable DMA\"); Serial.flush();\r\n    drv_spi_enable_dma(_hspi);\r\n    _dma_state = DMA_IDLE;\r\n  }\r\n//  Serial.println(\"Before Clear event\");  Serial.flush();\r\n  event_responder.clearEvent(); // Make sure it is not set yet\r\n  if (count < 2) {\r\n    // Use non-async version to simplify cases...\r\n    transfer(buf, retbuf, count);\r\n    event_responder.triggerEvent();\r\n    return true;\r\n  }\r\n\r\n  if ((count == 0) || ((buf == NULL) && (retbuf == NULL))) return false;    // nothing to do\r\n\r\n  _dma_event_responder = &event_responder;  // remember the event object\r\n  //bool dma_enabled = drv_spi_dma_enabled(_hspi);\r\n  // new version handles where buf or retbuf are null\r\n  drv_spi_start_dma_txrx(_hspi, (uint8_t *)buf, (uint8_t *)retbuf, count, &dmaCallback);\r\n  _dma_state = DMA_ACTIVE;\r\n  return true;\r\n}\r\n\r\nvoid SPIClass::dmaCallback(SPI_HandleTypeDef* hspi)\r\n{\r\n  // Static function call from our DMA DRV code\r\n  if (hspi == &hspi1) SPI_IMU.processDMACallback();\r\n  else if (hspi == &hspi2) SPI.processDMACallback();\r\n  else if (hspi == &hspi4) SPI_EXT.processDMACallback();\r\n\r\n}\r\n\r\nvoid SPIClass::processDMACallback()\r\n{\r\n  // We have been called back, that the DMA completed\r\n  if (_dma_event_responder)\r\n  {\r\n    _dma_state = DMA_COMPETED;   // set back to 1 in case our call wants to start up dma again\r\n    _dma_event_responder->triggerEvent();\r\n  }\r\n\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/SPI/SPI.h",
    "content": "/****************************************************************************\n *\n * SPI Master library for Arduino STM32 + HAL + CubeMX (HALMX).\n *\n * Copyright (c) 2016 by Vassilis Serasidis <info@serasidis.gr>\n * Home: http://www.serasidis.gr\n * email: avrsite@yahoo.gr\n *\n * Arduino_STM32 forum: http://www.stm32duino.com\n *\n * This file is free software; you can redistribute it and/or modify\n * it under the terms of either the GNU General Public License version 2\n * or the GNU Lesser General Public License version 2.1, both as\n * published by the Free Software Foundation.\n *\n ****************************************************************************/\n\n\n#ifndef _SPI_H_INCLUDED\n#define _SPI_H_INCLUDED\n\n#include <chip.h>\n#include \"variant.h\"\n\n// SPI_HAS_TRANSACTION means SPI has beginTransaction(), endTransaction(),\n// usingInterrupt(), and SPISetting(clock, bitOrder, dataMode)\n#define SPI_HAS_TRANSACTION 1\n// SPI_HAS_TRANSFER_BUF - is defined to signify that this library supports\n// a version of transfer which allows you to pass in both TX and RX buffer\n// pointers, either of which could be NULL\n#define SPI_HAS_TRANSFER_BUF 1\n\n#if defined(__has_include) && __has_include(<EventResponder.h>)\n#define SPI_HAS_TRANSFER_ASYNC 1\n#include <EventResponder.h>\n#endif\n\n\n\n#define SPI_CLOCK_DIV4      0x00\n#define SPI_CLOCK_DIV16     0x01\n#define SPI_CLOCK_DIV64     0x02\n#define SPI_CLOCK_DIV128    0x03\n#define SPI_CLOCK_DIV2      0x04\n#define SPI_CLOCK_DIV8      0x05\n#define SPI_CLOCK_DIV32     0x06\n#define SPI_CLOCK_DIV256    0x07\n\n#define SPI_MODE0           0\n#define SPI_MODE1           1\n#define SPI_MODE2           2\n#define SPI_MODE3           3\n\n\n#ifdef USE_SPI1\nextern SPI_HandleTypeDef hspi1;\n#endif\n#ifdef USE_SPI2\nextern SPI_HandleTypeDef hspi2;\n#endif\n#ifdef USE_SPI4\nextern SPI_HandleTypeDef hspi4;\n#endif\n\n\nclass SPISettings {\npublic:\n  SPISettings(uint32_t clock, uint8_t bitOrder, uint8_t dataMode)\n  {\n    if (__builtin_constant_p(clock)) {\n      init_Inline(clock, bitOrder, dataMode);\n    } else {\n      init_NotInline(clock, bitOrder, dataMode);\n    }\n  }\n  SPISettings()\n  {\n    init_Inline(4000000, MSBFIRST, SPI_MODE0);\n  }\nprivate:\n  void init_NotInline(uint32_t clock, uint8_t bitOrder, uint8_t dataMode) {\n    init_Inline(clock, bitOrder, dataMode);\n  }\n\n\n//The devices feature up to six SPIs in slave and master modes in full-duplex and simplex communication modes. \n// SPI1, SPI4, SPI5, and SPI6 can communicate at up to 50 Mbits/s, SPI2 and SPI3 can communicate at up to 25 Mbit/s. \n  void init_Inline(uint32_t clock, uint8_t bitOrder, uint8_t dataMode) \n    __attribute__((__always_inline__))  {\n      _clock = clock;\n      _bitOrder = bitOrder;\n      _dataMode = dataMode;\n  }\n\n  //uint8_t _clockDiv;\n  uint32_t _clock;\n  uint8_t _bitOrder;\n  uint8_t _dataMode;\n\n  friend class SPIClass;\n};\n\n\nclass SPIClass {\n  public:\n    SPIClass(SPI_TypeDef *spiPort, uint32_t spi_clock);\n    SPIClass(uint8_t spiPort);\n    void begin(void);\n    void beginFast(void);\n\n    void beginTransaction(SPISettings settings)\n    {\n      if (settings._clock != _clock) {\n        setClock(settings._clock);\n      }\n      if (settings._bitOrder != _bitOrder) {\n        setBitOrder(settings._bitOrder);\n      }\n      if (settings._dataMode != _dataMode) {\n        setDataMode(settings._dataMode);\n      }\n    }\n    void endTransaction(void)\n    {\n    }\n\n    // Disable the SPI bus\n    static void end();\n\n    uint8_t transfer(uint8_t _data) const;\n    uint16_t transfer16(uint16_t data);\n//    void transfer(void *buf, size_t count);\n\n    void inline transfer(void *buf, size_t count) {transfer(buf, buf, count);}\n    //void setTransferWriteFill(uint8_t ch ) {_transferWriteFill = ch;}\n    void transfer(const void * buf, void * retbuf, size_t count);\n\n\n    // Write only functions similar to ESP32 and the like\n    void write(uint8_t data);\n    void write16(uint16_t data);\n    void write32(uint32_t data);\n    void writeBytes(uint8_t * data, uint32_t size);\n\n    void inline writeFast(void *buf, size_t count) {transfer(buf, NULL, count);}\n    void writePixels(const void * data, uint32_t size);//ili9341 compatible\n\n\n    void setBitOrder(uint8_t bitOrder);\n    void setClockDivider(uint8_t clockDiv);\n    void setClock(uint32_t clock);\n    void setDataMode(uint8_t dataMode);\n\n#ifdef SPI_HAS_TRANSFER_ASYNC\n  bool transfer(const void *txBuffer, void *rxBuffer, size_t count,  EventResponderRef  event_responder);\n#endif\n\n  enum DMAState {DMA_NOTINITIALIZED=0, DMA_IDLE, DMA_ACTIVE, DMA_COMPETED};\n  private:\n    //uint32_t _Mode;\n    uint32_t _Direction;\n    uint32_t _DataSize;\n    uint32_t _CLKPolarity;\n    uint32_t _CLKPhase;\n    uint32_t _NSS;\n    uint32_t _BaudRatePrescaler;\n    uint32_t _FirstBit;\n    uint32_t _TIMode;\n    uint32_t _CRCCalculation;\n    uint32_t _CRCPolynomial;\n    // Keep track of values we set for transactions \n    uint32_t _clock;\n    uint8_t _bitOrder;\n    uint8_t _dataMode;\n    uint32_t _spi_clock;   \n\n    SPI_HandleTypeDef *_hspi;\n    SPI_TypeDef *_spiPort;\n#ifdef SPI_HAS_TRANSFER_ASYNC\n    uint8_t  _dma_state;\n    EventResponder *_dma_event_responder;\nstatic void dmaCallback(SPI_HandleTypeDef* hspi);\n    void processDMACallback();\n#endif\n    void init(void);\n\n};\n\nextern SPIClass SPI;\nextern SPIClass SPI_IMU;\nextern SPIClass SPI_EXT;\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/SPI/keywords.txt",
    "content": "#######################################\n# Syntax Coloring Map SPI\n#######################################\n\n#######################################\n# Datatypes (KEYWORD1)\n#######################################\n\nSPI\tKEYWORD1\n\n#######################################\n# Methods and Functions (KEYWORD2)\n#######################################\nbegin\t\t\tKEYWORD2\nend\t\t\t\tKEYWORD2\nbeginTransaction\tKEYWORD2\nendTransaction\tKEYWORD2\ntransfer\t\tKEYWORD2\ntransfer16\t\tKEYWORD2\nwriteFast\t\tKEYWORD2\nwrite\t\tKEYWORD2\nwrite16\t\tKEYWORD2\nwrite32\t\tKEYWORD2\nwriteBytes\t\tKEYWORD2\nwritePixels\t\tKEYWORD2\n#setBitOrder\tKEYWORD2\nsetDataMode\t\tKEYWORD2\nsetClockDivider\tKEYWORD2\n\n#######################################\n# Constants (LITERAL1)\n#######################################\nSPI_MODE0\t\tLITERAL1\nSPI_MODE1\t\tLITERAL1\nSPI_MODE2\t\tLITERAL1\nSPI_MODE3\t\tLITERAL1\n\nSPI_CONTINUE\tLITERAL1\nSPI_LAST\t\tLITERAL1\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Servo/README.adoc",
    "content": "= Servo Library for Arduino =\n\nThis library allows an Arduino board to control RC (hobby) servo motors.\n\nFor more information about this library please visit us at\nhttp://www.arduino.cc/en/Reference/Servo\n\n== License ==\n\nCopyright (c) 2013 Arduino LLC. All right reserved.\nCopyright (c) 2009 Michael Margolis.  All right reserved.\n\nThis library is free software; you can redistribute it and/or\nmodify it under the terms of the GNU Lesser General Public\nLicense as published by the Free Software Foundation; either\nversion 2.1 of the License, or (at your option) any later version.\n\nThis library is distributed in the hope that it will be useful,\nbut WITHOUT ANY WARRANTY; without even the implied warranty of\nMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\nLesser General Public License for more details.\n\nYou should have received a copy of the GNU Lesser General Public\nLicense along with this library; if not, write to the Free Software\nFoundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Servo/keywords.txt",
    "content": "#######################################\r\n# Syntax Coloring Map Servo\r\n#######################################\r\n\r\n#######################################\r\n# Datatypes (KEYWORD1)\r\n#######################################\r\nServo\t\t\tKEYWORD1\r\n\r\n#######################################\r\n# Methods and Functions (KEYWORD2)\r\n#######################################\r\nattach\t\t\tKEYWORD2\r\ndetach\t\t\tKEYWORD2\r\nwrite\t\t\tKEYWORD2\r\nwriteMicroseconds\tKEYWORD2\r\nread\t\t\tKEYWORD2\r\nreadMicroseconds\tKEYWORD2\r\nattached\t\tKEYWORD2\r\n\r\n#######################################\r\n# Constants (LITERAL1)\r\n#######################################\r\nMIN_ANGLE\t\tLITERAL1\r\nMAX_ANGLE\t\tLITERAL1\r\nMIN_PULSE_WIDTH\t\tLITERAL1\r\nMAX_PULSE_WIDTH\t\tLITERAL1\r\nDEFAULT_PULSE_WIDTH\tLITERAL1\r\nREFRESH_INTERVAL\tLITERAL1\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Servo/library.properties",
    "content": "name=Servo\nversion=1.1.2\nauthor=Michael Margolis, Arduino / Kei, Robotis\nmaintainer=Arduino <info@arduino.cc> / kei <kkw@robotis.com>\nsentence=Allows Arduino/Genuino boards to control a variety of servo motors.\nparagraph=This library can control a great number of servos.<br />It makes careful use of timers: the library can control 12 servos using only 1 timer.<br />On the Arduino Due you can control up to 60 servos.<br />\ncategory=Device Control\nurl=http://www.arduino.cc/en/Reference/Servo\narchitectures=OpenCR\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Servo/src/Servo.cpp",
    "content": "/*\n  Copyright (c) 2013 Arduino LLC. All right reserved.\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n  Lesser General Public License for more details.\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\n*/\n\n#include <Arduino.h>\n\n#include \"Servo.h\"\n#include \"drv_pwm.h\"\n\n\n\n#define SERVO_DEFAULT_FREQ          (1000000/REFRESH_INTERVAL)\n\n// Unit conversions\n#define ANGLE_TO_US(a)    ((uint16_t)(map((a), this->minAngle, this->maxAngle, \\\n                                        this->minPW, this->maxPW)))\n#define US_TO_ANGLE(us)   ((int16_t)(map((us), this->minPW, this->maxPW,  \\\n                                       this->minAngle, this->maxAngle)))\n\n#define SERVO_MIN() (MIN_PULSE_WIDTH - this->min * 4)  // minimum value in uS for this servo\n#define SERVO_MAX() (MAX_PULSE_WIDTH - this->max * 4)  // maximum value in uS for this servo\n\n\nServo::Servo()\n{\n    this->resetFields();\n}\n\nuint8_t Servo::attach(int pin)\n{\n  return this->attach(pin, MIN_PULSE_WIDTH, MAX_PULSE_WIDTH);\n}\n\nuint8_t Servo::attach(int pin, int min, int max)\n{\n    //analogWriteResolution(16);\n    this->pin = pin;\n    this->min = (MIN_PULSE_WIDTH - min)/4;\n    this->max = (MIN_PULSE_WIDTH - min)/4;\n\n    drv_pwm_set_freq((uint32_t)pin, SERVO_DEFAULT_FREQ);\n    drv_pwm_setup((uint32_t)pin);\n\n    this->is_attached = true;\n\n    return true;\n}\n\nbool Servo::attached()\n{\n    return this->is_attached;\n}\n\nvoid Servo::detach()\n{\n    drv_pwm_release(this->pin);\n}\n\nvoid Servo::write(int value)\n{\n  if(value < MIN_PULSE_WIDTH)\n  {  // treat values less than 544 as angles in degrees (valid values in microseconds are handled as microseconds)\n    if(value < 0) value = 0;\n    if(value > 180) value = 180;\n    value = map(value, 0, 180, SERVO_MIN(),  SERVO_MAX());\n  }\n  this->writeMicroseconds(value);\n}\n\nint Servo::read() {\n    int a = US_TO_ANGLE(this->readMicroseconds());\n    // map() round-trips in a weird way we mostly correct for here;\n    // the round-trip is still sometimes off-by-one for write(1) and\n    // write(179).\n    return a == this->minAngle || a == this->maxAngle ? a : a + 1;\n}\n\nvoid Servo::writeMicroseconds(int pulseWidth) {\n    if (!this->attached()) {\n        return;\n    }\n\n    pulseWidth = constrain(pulseWidth, this->minPW, this->maxPW);\n    pulseWidth = map(pulseWidth, 0, REFRESH_INTERVAL, 0, 4096);\n\n    drv_pwm_set_duty(this->pin, 12, pulseWidth);\n}\n\nint Servo::readMicroseconds() {\n    if (!this->attached()) {\n        return 0;\n    }\n    \n    uint32_t ret_us;\n    uint32_t pwm_period = drv_pwm_get_period(this->pin);\n    uint32_t pwm_pulse = drv_pwm_get_pulse(this->pin);\n    ret_us = map(pwm_pulse, 0, pwm_period, 0, REFRESH_INTERVAL);\n\n    return (int) ret_us;\n}\n\nvoid Servo::resetFields(void)\n{\n    this->is_attached = false;\n    this->minAngle = MIN_ANGLE;\n    this->maxAngle = MAX_ANGLE;\n    this->minPW = MIN_PULSE_WIDTH;\n    this->maxPW = MAX_PULSE_WIDTH;\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Servo/src/Servo.h",
    "content": "/*\n  Servo.h - Interrupt driven Servo library for Arduino using 16 bit timers- Version 2\n  Copyright (c) 2009 Michael Margolis.  All right reserved.\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n  Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n/* \n  A servo is activated by creating an instance of the Servo class passing \n  the desired pin to the attach() method.\n  The servos are pulsed in the background using the value most recently \n  written using the write() method.\n\n  Note that analogWrite of PWM on pins associated with the timer are \n  disabled when the first servo is attached.\n  Timers are seized as needed in groups of 12 servos - 24 servos use two \n  timers, 48 servos will use four.\n  The sequence used to sieze timers is defined in timers.h\n\n  The methods are:\n\n    Servo - Class for manipulating servo motors connected to Arduino pins.\n\n    attach(pin )  - Attaches a servo motor to an i/o pin.\n    attach(pin, min, max  ) - Attaches to a pin setting min and max values in microseconds\n    default min is 544, max is 2400  \n \n    write()     - Sets the servo angle in degrees.  (invalid angle that is valid as pulse in microseconds is treated as microseconds)\n    writeMicroseconds() - Sets the servo pulse width in microseconds \n    read()      - Gets the last written servo pulse width as an angle between 0 and 180. \n    readMicroseconds()   - Gets the last written servo pulse width in microseconds. (was read_us() in first release)\n    attached()  - Returns true if there is a servo attached. \n    detach()    - Stops an attached servos from pulsing its i/o pin. \n */\n\n#ifndef Servo_h\n#define Servo_h\n\n#include <inttypes.h>\n\n\n#define MIN_ANGLE               0\n#define MAX_ANGLE             180\n#define MIN_PULSE_WIDTH       544     // the shortest pulse sent to a servo  \n#define MAX_PULSE_WIDTH      2400     // the longest pulse sent to a servo \n#define DEFAULT_PULSE_WIDTH  1500     // default pulse width when servo is attached\n#define REFRESH_INTERVAL    20000     // minumim time to refresh servos in microseconds \n\n\nclass Servo\n{\npublic:\n  Servo();\n  uint8_t attach(int pin);           // attach the given pin to the next free channel, sets pinMode, returns channel number or 0 if failure\n  uint8_t attach(int pin, int min, int max); // as above but also sets min and max values for writes. \n  void detach();\n  void write(int value);             // if value is < 200 its treated as an angle, otherwise as pulse width in microseconds \n  void writeMicroseconds(int value); // Write pulse width in microseconds \n  int read();                        // returns current pulse width as an angle between 0 and 180 degrees\n  int readMicroseconds();            // returns current pulse width in microseconds for this servo (was read_us() in first release)\n  bool attached();                   // return true if this servo is attached, otherwise false \nprivate:\n   uint8_t pin;                      // index into the channel data for this servo\n   bool    is_attached;\n   int8_t  min;                      // minimum is this value times 4 added to MIN_PULSE_WIDTH    \n   int8_t  max;                      // maximum is this value times 4 added to MAX_PULSE_WIDTH   \n   uint16_t  minPW;\n   uint16_t  maxPW;\n   int16_t   minAngle;\n   int16_t   maxAngle;\n\n   void resetFields(void);\n};\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Touch/Touch.cpp",
    "content": "\r\n#include <Touch.h>\r\n#include <LCD.h>\r\n#include <XPT2046.h>\r\n#include <stdlib.h>\r\n#include <math.h>\r\n//#include <Serial.h>\r\n\r\n\r\nvoid TP::tp_init(void)\r\n{\r\n\tXpt.xpt2046_init();\r\n\ts_tTouch.chStatus = 0;\r\n\t//Serial.begin(9600, SERIAL_8N1);\r\n}\r\n\r\nvoid TP::tp_draw_touch_point(uint16_t hwXpos, uint16_t hwYpos, uint16_t hwColor)\r\n{\r\n\tTft.lcd_draw_line(hwXpos - 12, hwYpos, hwXpos + 13, hwYpos, hwColor);\r\n\tTft.lcd_draw_line(hwXpos, hwYpos - 12, hwXpos, hwYpos + 13, hwColor);\r\n\tTft.lcd_draw_point(hwXpos + 1, hwYpos + 1, hwColor);\r\n\tTft.lcd_draw_point(hwXpos - 1, hwYpos + 1, hwColor);\r\n\tTft.lcd_draw_point(hwXpos + 1, hwYpos - 1, hwColor);\r\n\tTft.lcd_draw_point(hwXpos - 1, hwYpos - 1, hwColor);\r\n\tTft.lcd_draw_circle(hwXpos, hwYpos, 6, hwColor);\r\n}\r\n\r\nvoid TP::tp_draw_big_point(uint16_t hwXpos, uint16_t hwYpos, uint16_t hwColor)\r\n{\r\n\tTft.lcd_draw_point(hwXpos, hwYpos, hwColor);\r\n\tTft.lcd_draw_point(hwXpos + 1, hwYpos, hwColor);\r\n\tTft.lcd_draw_point(hwXpos, hwYpos + 1, hwColor);\r\n\tTft.lcd_draw_point(hwXpos + 1, hwYpos + 1, hwColor);\r\n}\r\n\r\nvoid TP::tp_show_single_info(uint16_t* pos)\r\n{\r\n\t\r\n\ttp_scan(1);\r\n\tif((s_tTouch.chStatus & 0xC0) == TP_PRESSED)\r\n\t{\t\r\n\t\ts_tTouch.chStatus &= ~(1 << 6);\r\n\t\tpos[0] = s_tTouch.hwXpos;\r\n\t\tpos[1] = s_tTouch.hwYpos;\r\n\t}\r\n}\r\n\r\nvoid TP::tp_show_info(uint16_t hwXpos0, uint16_t hwYpos0,\r\n                     uint16_t hwXpos1, uint16_t hwYpos1,\r\n                     uint16_t hwXpos2, uint16_t hwYpos2,\r\n                     uint16_t hwXpos3, uint16_t hwYpos3, uint16_t hwFac)\r\n{\r\n\r\n\tTft.lcd_display_string(40, 160, (const uint8_t *)\"x1\", 16, RED);\r\n\tTft.lcd_display_string(40 + 80, 160, (const uint8_t *)\"y1\", 16, RED);\r\n\r\n\tTft.lcd_display_string(40, 180, (const uint8_t *)\"x2\", 16, RED);\r\n\tTft.lcd_display_string(40 + 80, 180, (const uint8_t *)\"y2\", 16, RED);\r\n\r\n\tTft.lcd_display_string(40, 200, (const uint8_t *)\"x3\", 16, RED);\r\n\tTft.lcd_display_string(40 + 80, 200, (const uint8_t *)\"y3\", 16, RED);\r\n\r\n\tTft.lcd_display_string(40, 220, (const uint8_t *)\"x4\", 16, RED);\r\n\tTft.lcd_display_string(40 + 80, 220, (const uint8_t *)\"y4\", 16, RED);\r\n\r\n\tTft.lcd_display_string(40, 240, (const uint8_t *)\"fac is:\", 16, RED);\r\n\r\n\tTft.lcd_display_num(40 + 24, 160, hwXpos0, 4, 16, RED);\r\n\tTft.lcd_display_num(40 + 24 + 80, 160, hwYpos0, 4, 16, RED);\r\n\r\n\tTft.lcd_display_num(40 + 24, 180, hwXpos1, 4, 16, RED);\r\n\tTft.lcd_display_num(40 + 24 + 80, 180, hwYpos1, 4, 16, RED);\r\n\r\n\tTft.lcd_display_num(40 + 24, 200, hwXpos2, 4, 16, RED);\r\n\tTft.lcd_display_num(40 + 24 + 80, 200, hwYpos2, 4, 16, RED);\r\n\r\n\tTft.lcd_display_num(40 + 24, 220, hwXpos3, 4, 16, RED);\r\n\tTft.lcd_display_num(40 + 24 + 80, 220, hwYpos3, 4, 16, RED);\r\n\r\n\tTft.lcd_display_num(40 + 56, 240, hwFac, 3, 16, RED);\r\n}\r\n\r\nuint8_t TP::tp_scan(uint8_t chCoordType)\r\n{\r\n\tif (!(__XPT2046_IRQ_READ())) {\r\n\t\tif (chCoordType) {\r\n\t\t\tXpt.xpt2046_twice_read_xy(&s_tTouch.hwXpos, &s_tTouch.hwYpos);\r\n\t\t} else if (Xpt.xpt2046_twice_read_xy(&s_tTouch.hwXpos, &s_tTouch.hwYpos)) {\r\n\t\t\t//s_tTouch.hwXpos = 0.066 * s_tTouch.hwXpos + (-12);//s_tTouch.fXfac * s_tTouch.hwXpos + s_tTouch.iXoff;\r\n\t\t\t//s_tTouch.hwYpos = (-0.089) * s_tTouch.hwYpos + (352);//s_tTouch.fYfac * s_tTouch.hwYpos + s_tTouch.iYoff;\r\n\t\t\ts_tTouch.hwXpos = s_tTouch.fXfac * s_tTouch.hwXpos + s_tTouch.iXoff;\r\n\t\t\ts_tTouch.hwYpos = s_tTouch.fYfac * s_tTouch.hwYpos + s_tTouch.iYoff;\r\n\t\t}\r\n\t\tif (0 == (s_tTouch.chStatus & TP_PRESS_DOWN)) {\r\n\t\t\ts_tTouch.chStatus = TP_PRESS_DOWN | TP_PRESSED;\r\n\t\t\ts_tTouch.hwXpos0 = s_tTouch.hwXpos;\r\n\t\t\ts_tTouch.hwYpos0 = s_tTouch.hwYpos;\r\n\t\t} \r\n\r\n\t} else {\r\n\t\tif (s_tTouch.chStatus & TP_PRESS_DOWN) {\r\n\t\t\ts_tTouch.chStatus &= ~(1 << 7);\r\n\t\t} else {\r\n\t\t\ts_tTouch.hwXpos0 = 0;\r\n\t\t\ts_tTouch.hwYpos0 = 0;\r\n\t\t\ts_tTouch.hwXpos = 0xffff;\r\n\t\t\ts_tTouch.hwYpos = 0xffff;\r\n\t\t}\r\n\t}\r\n\r\n\treturn (s_tTouch.chStatus & TP_PRESS_DOWN);\r\n}\r\n\r\n\r\nvoid TP::tp_adjust(void)\r\n{\t\r\n\tuint8_t  cnt = 0;\r\n\tuint16_t hwTimeout = 0, d1, d2, pos_temp[4][2];\r\n\tuint32_t tem1, tem2;\r\n\tfloat fac;\t\t\t\t\r\n\r\n\tTft.lcd_clear_screen(WHITE);\r\n\tTft.lcd_display_string(40, 40, (const uint8_t *)\"Please use the stylus click the cross on the screen. The cross will always move until the screen adjustment is completed.\",\r\n\t\t\t\t\t16, RED);\r\n\ttp_draw_touch_point(20, 20, RED);\r\n\ts_tTouch.chStatus = 0;\r\n\ts_tTouch.fXfac = 0;\r\n\twhile (1) {\r\n\t\ttp_scan(1);\r\n\t\tif((s_tTouch.chStatus & 0xC0) == TP_PRESSED) {\t\r\n\t\t\thwTimeout = 0;\r\n\t\t\ts_tTouch.chStatus &= ~(1 << 6);\r\n\t\t\t\t\t\t   \t\t\t   \r\n\t\t\tpos_temp[cnt][0] = s_tTouch.hwXpos;\r\n\t\t\tpos_temp[cnt][1] = s_tTouch.hwYpos;\r\n\t\t\tcnt ++;\t  \r\n\t\t\tswitch(cnt) {\t\t\t   \r\n\t\t\t\tcase 1:\t\t\t\t\t\t \r\n\t\t\t\t\ttp_draw_touch_point(20, 20, WHITE);\r\n\t\t\t\t\ttp_draw_touch_point(LCD_WIDTH - 20, 20, RED);\r\n\t\t\t\t\tbreak;\r\n\t\t\t\tcase 2:\r\n\t\t\t\t\ttp_draw_touch_point(LCD_WIDTH - 20, 20, WHITE);\r\n\t\t\t\t\ttp_draw_touch_point(20, LCD_HEIGHT - 20, RED);\r\n\t\t\t\t\tbreak;\r\n\t\t\t\tcase 3:\r\n\t\t\t\t\ttp_draw_touch_point(20, LCD_HEIGHT - 20, WHITE);\r\n\t\t\t\t\ttp_draw_touch_point(LCD_WIDTH - 20, LCD_HEIGHT - 20, RED);\r\n\t\t\t\t\tbreak;\r\n\t\t\t\tcase 4:\t\r\n\t\t\t\t\ttem1=abs((int16_t)(pos_temp[0][0]-pos_temp[1][0]));//x1-x2\r\n\t\t\t\t\ttem2=abs((int16_t)(pos_temp[0][1]-pos_temp[1][1]));//y1-y2\r\n\t\t\t\t\ttem1*=tem1;\r\n\t\t\t\t\ttem2*=tem2;\r\n\t\t\t\t\ttem1+=tem2;\r\n\t\t\t\t\td1=sqrt(tem1);\r\n\r\n\t\t\t\t\ttem1=abs((int16_t)(pos_temp[2][0]-pos_temp[3][0]));//x3-x4\r\n\t\t\t\t\ttem2=abs((int16_t)(pos_temp[2][1]-pos_temp[3][1]));//y3-y4\r\n\t\t\t\t\ttem1*=tem1;\r\n\t\t\t\t\ttem2*=tem2;\r\n\t\t\t\t\ttem1+=tem2;\r\n\t\t\t\t\td2=sqrt(tem1);\r\n\t\t\t\t\tfac=(float)d1/d2;\r\n\t\t\t\t\tif(fac<0.95||fac>1.05||d1==0||d2==0) {\r\n\t\t\t\t\t\tcnt=0;\r\n\t\t\t\t\t\t//Serial.print(d1, DEC);\r\n\t\t\t\t\t\t//Serial.print(\"\\t\"); \r\n\t\t\t\t\t\t//Serial.print(d2, DEC);\r\n\t\t\t\t\t\t//Serial.print(\"\\t\"); \r\n\t\t\t\t\t\t//Serial.println(fac, 2);\r\n \t\t\t\t\t\ttp_show_info(pos_temp[0][0],pos_temp[0][1],pos_temp[1][0],pos_temp[1][1],pos_temp[2][0],pos_temp[2][1],pos_temp[3][0],pos_temp[3][1],fac*100);//??��o?��oy?Y   \r\n\t\t\t\t\t\tdelay(1000);\r\n\t\t\t\t\t\tTft.lcd_fill_rect(96, 240, 24, 16, WHITE);\r\n\t\t\t\t\t\ttp_draw_touch_point(LCD_WIDTH - 20, LCD_HEIGHT - 20, WHITE);\r\n\t\t\t\t\t\ttp_draw_touch_point(20, 20, RED);\r\n\t\t\t\t\t\tcontinue;\r\n\t\t\t\t\t}\r\n\r\n\t\t\t\t\ttem1=abs((int16_t)(pos_temp[0][0]-pos_temp[2][0]));//x1-x3\r\n\t\t\t\t\ttem2=abs((int16_t)(pos_temp[0][1]-pos_temp[2][1]));//y1-y3\r\n\t\t\t\t\ttem1*=tem1;\r\n\t\t\t\t\ttem2*=tem2;\r\n\t\t\t\t\ttem1+=tem2;\r\n\t\t\t\t\td1=sqrt(tem1);//\r\n\r\n\t\t\t\t\ttem1=abs((int16_t)(pos_temp[1][0]-pos_temp[3][0]));//x2-x4\r\n\t\t\t\t\ttem2=abs((int16_t)(pos_temp[1][1]-pos_temp[3][1]));//y2-y4\r\n\t\t\t\t\ttem1*=tem1;\r\n\t\t\t\t\ttem2*=tem2;\r\n\t\t\t\t\ttem1+=tem2;\r\n\t\t\t\t\td2=sqrt(tem1);//\r\n\t\t\t\t\tfac=(float)d1/d2;\r\n\t\t\t\t\tif(fac<0.95||fac>1.05) {\r\n\t\t\t\t\t\tcnt=0;\r\n\t\t\t\t\t\t//Serial.print(d1, DEC);\r\n\t\t\t\t\t\t//Serial.print(\"\\t\"); \r\n\t\t\t\t\t\t//Serial.print(d2, DEC);\r\n\t\t\t\t\t\t//Serial.print(\"\\t\"); \r\n\t\t\t\t\t\t//Serial.println(fac, 2);\r\n \t\t\t\t\t\ttp_show_info(pos_temp[0][0],pos_temp[0][1],pos_temp[1][0],pos_temp[1][1],pos_temp[2][0],pos_temp[2][1],pos_temp[3][0],pos_temp[3][1],fac*100);//??��o?��oy?Y   \r\n\t\t\t\t\t\tdelay(1000);\r\n\t\t\t\t\t\tTft.lcd_fill_rect(96, 240, 24, 16, WHITE);\r\n\t\t\t\t\t\ttp_draw_touch_point(LCD_WIDTH - 20, LCD_HEIGHT - 20, WHITE);\r\n\t\t\t\t\t\ttp_draw_touch_point(20, 20, RED);\r\n\t\t\t\t\t\tcontinue;\r\n\t\t\t\t\t}//\r\n\t\t\t\t\t\t\t\t   \r\n\t\t\t\t\ttem1=abs((int16_t)(pos_temp[1][0]-pos_temp[2][0]));//x1-x3\r\n\t\t\t\t\ttem2=abs((int16_t)(pos_temp[1][1]-pos_temp[2][1]));//y1-y3\r\n\t\t\t\t\ttem1*=tem1;\r\n\t\t\t\t\ttem2*=tem2;\r\n\t\t\t\t\ttem1+=tem2;\r\n\t\t\t\t\td1=sqrt(tem1);//\r\n\r\n\t\t\t\t\ttem1=abs((int16_t)(pos_temp[0][0]-pos_temp[3][0]));//x2-x4\r\n\t\t\t\t\ttem2=abs((int16_t)(pos_temp[0][1]-pos_temp[3][1]));//y2-y4\r\n\t\t\t\t\ttem1*=tem1;\r\n\t\t\t\t\ttem2*=tem2;\r\n\t\t\t\t\ttem1+=tem2;\r\n\t\t\t\t\td2=sqrt(tem1);//\r\n\t\t\t\t\tfac=(float)d1/d2;\r\n\t\t\t\t\tif(fac<0.95||fac>1.05) {\r\n\t\t\t\t\t\tcnt=0;\t\r\n\t\t\t\t\t\t//Serial.print(d1, DEC);\r\n\t\t\t\t\t\t//Serial.print(\"\\t\"); \r\n\t\t\t\t\t\t//Serial.print(d2, DEC);\r\n\t\t\t\t\t\t//Serial.print(\"\\t\"); \r\n\t\t\t\t\t\t//Serial.println(fac, 2);\r\n \t\t\t\t\t\ttp_show_info(pos_temp[0][0],pos_temp[0][1],pos_temp[1][0],pos_temp[1][1],pos_temp[2][0],pos_temp[2][1],pos_temp[3][0],pos_temp[3][1],fac*100);//??��o?��oy?Y   \r\n\t\t\t\t\t\tdelay(1000);\r\n\t\t\t\t\t\tTft.lcd_fill_rect(96, 240, 24, 16, WHITE);\r\n\t\t\t\t\t\ttp_draw_touch_point(LCD_WIDTH - 20, LCD_HEIGHT - 20, WHITE);\r\n\t\t\t\t\t\ttp_draw_touch_point(20, 20, RED);\r\n\t\t\t\t\t\tcontinue;\r\n\t\t\t\t\t}\r\n\r\n\t\t\t\t\ts_tTouch.fXfac = (float)(LCD_WIDTH - 40) / (int16_t)(pos_temp[1][0] - pos_temp[0][0]);\t\r\n\t\t\t\t\ts_tTouch.iXoff = (LCD_WIDTH - s_tTouch.fXfac * (pos_temp[1][0] + pos_temp[0][0])) / 2;\r\n\r\n\t\t\t\t\ts_tTouch.fYfac = (float)(LCD_HEIGHT - 40) / (int16_t)(pos_temp[2][1] - pos_temp[0][1]);\t  \r\n\t\t\t\t\ts_tTouch.iYoff = (LCD_HEIGHT - s_tTouch.fYfac * (pos_temp[2][1] + pos_temp[0][1])) / 2;\r\n\r\n\t\t\t\t\t\r\n\t\t\t\t\tif(abs(s_tTouch.fXfac) > 2 || abs(s_tTouch.fYfac) > 2) {\r\n\t\t\t\t\t\tcnt=0;\r\n \t\t\t\t    \ttp_draw_touch_point(LCD_WIDTH - 20, LCD_HEIGHT - 20, WHITE);\r\n\t\t\t\t\t\ttp_draw_touch_point(20, 20, RED);\t\t\t\t\t\t\t\t\r\n\t\t\t\t\t\tTft.lcd_display_string(40, 26, (const uint8_t *)\"TP Need readjust!\", 16, RED);\r\n\t\t\t\t\t\tcontinue;\r\n\t\t\t\t\t}\r\n\t\t\t\t\tTft.lcd_clear_screen(WHITE);\r\n\t\t\t\t\tTft.lcd_display_string(35, 110, (const uint8_t *)\"Touch Screen Adjust OK!\", 16, BLUE);\r\n\t\t\t\t\tdelay(1000); \r\n \t\t\t\t\tTft.lcd_clear_screen(WHITE);  \r\n\t\t\t\t\treturn;\t\t\t\t \r\n\t\t\t}\r\n\t\t}\r\n\t\tdelay(10);\r\n\t\tif (++ hwTimeout >= 1000) {\r\n\t\t\tbreak;\r\n\t\t}\r\n \t}\r\n}\r\n\r\n\r\nvoid TP::tp_dialog(void)\r\n{\r\n\tTft.lcd_clear_screen(WHITE);\r\n\tTft.lcd_display_string(LCD_WIDTH - 40, 0, (const uint8_t *)\"CLEAR\", 16, BLUE);\r\n}\r\n\r\nvoid TP::tp_draw_board(void)\r\n{\r\n\ttp_scan(0);\r\n\tif (s_tTouch.chStatus & TP_PRESS_DOWN) {\r\n\t\tif (s_tTouch.hwXpos < LCD_WIDTH && s_tTouch.hwYpos < LCD_HEIGHT) {\r\n\t\t\tif (s_tTouch.hwXpos > (LCD_WIDTH - 40) && s_tTouch.hwYpos < 16) {\r\n\t\t\t\ttp_dialog();\r\n\t\t\t} else {\r\n\t\t\t\ttp_draw_big_point(s_tTouch.hwXpos, s_tTouch.hwYpos, RED);\r\n\t\t\t}\r\n\t\t}\r\n\t}\r\n}\r\n\r\nTP Tp = TP();\r\n\r\n\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Touch/Touch.h",
    "content": "#ifndef __TOUCH_H_\r\n#define __TOUCH_H_\r\n\r\n#include <Arduino.h>\r\n#include <avr/pgmspace.h>\r\n\r\n\r\n#define TP_PRESS_DOWN           0x80\r\n#define TP_PRESSED              0x40\r\n\r\ntypedef struct {\r\n\tuint16_t hwXpos0;\r\n\tuint16_t hwYpos0;\r\n\tuint16_t hwXpos;\r\n\tuint16_t hwYpos;\r\n\tuint8_t chStatus;\r\n\tuint8_t chType;\r\n\tshort iXoff;\r\n\tshort iYoff;\r\n\tfloat fXfac;\r\n\tfloat fYfac;\r\n} tp_dev_t;\r\n\r\nclass TP\r\n{\r\nprivate :\r\n\ttp_dev_t s_tTouch;\r\n\tuint8_t tp_scan(uint8_t chCoordType);\r\n\t\r\n\t\r\n\tvoid tp_show_info(uint16_t hwXpos0, uint16_t hwYpos0,\r\n\t\t\t\t\t\t uint16_t hwXpos1, uint16_t hwYpos1,\r\n\t\t\t\t\t\t uint16_t hwXpos2, uint16_t hwYpos2,\r\n\t\t\t\t\t\t uint16_t hwXpos3, uint16_t hwYpos3, uint16_t hwFac);\r\n\t\r\n\r\npublic:\r\n\t\r\n\tvoid tp_show_single_info(uint16_t* pos);\r\n\tvoid tp_init(void);\r\n\tvoid tp_adjust(void);\r\n\tvoid tp_dialog(void);\r\n\tvoid tp_draw_board(void);\r\n\tvoid tp_draw_big_point(uint16_t hwXpos, uint16_t hwYpos, uint16_t hwColor);\r\n\tvoid tp_draw_touch_point(uint16_t hwXpos, uint16_t hwYpos, uint16_t hwColor);\r\n};\r\n\r\nextern TP Tp;\r\n\r\n#endif\r\n\r\n\r\n\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Waveshare_HX8347D/README.txt",
    "content": "This is a library for the Adafruit HX8357 display products\n\nThis library works with the Adafruit 3.5\" Breakout\n  ----> http://www.adafruit.com/products/2050\n \nCheck out the links above for our tutorials and wiring diagrams.\nThese displays use SPI to communicate, 4 or 5 pins are required\nto interface (RST is optional).\n\nAdafruit invests time and resources providing this open source code,\nplease support Adafruit and open-source hardware by purchasing\nproducts from Adafruit!\n\nWritten by Limor Fried/Ladyada for Adafruit Industries.\nMIT license, all text above must be included in any redistribution\n\nTo download. click the DOWNLOADS button in the top right corner, rename the uncompressed folder Adafruit_HX8357. Check that the Adafruit_HX8357 folder contains Adafruit_HX8357.cpp and Adafruit_HX8357.\n\nPlace the Adafruit_HX8357 library folder your arduinosketchfolder/libraries/ folder. You may need to create the libraries subfolder if its your first library. Restart the IDE\n\nAlso requires the Adafruit_GFX library for Arduino.\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Waveshare_HX8347D/Waveshare_HX8347D.cpp",
    "content": "\n#include \"Waveshare_HX8347D.h\"\n#include <avr/pgmspace.h>\n#include <limits.h>\n#include <SPI.h>\n\n\n#define USE_FRAME_BUFFER     1\n\n\n\n#define spiWrite(x)     SPI.transfer(x)\n#define spiWrite16(x)   SPI.transfer16(x)\n\n\n#if USE_FRAME_BUFFER == 1\nuint16_t frame_buf[320*240];\n#endif\n\n\nWaveshare_HX8347D::Waveshare_HX8347D(int8_t cs, int8_t dc, int8_t led, int8_t rst) : Adafruit_GFX(HX8347D_TFTWIDTH, HX8347D_TFTHEIGHT) {\n  _cs   = cs;\n  _dc   = dc;\n  _led  = led;\n  _rst  = rst;\n}\n\n\n\nvoid Waveshare_HX8347D::writeCommand(uint8_t c) {\n  digitalWrite(_dc, LOW);\n  digitalWrite(_cs, LOW);\n\n  spiWrite(c);\n\n  digitalWrite(_cs, HIGH);\n}\n\n\nvoid Waveshare_HX8347D::writeData(uint8_t c) {\n  digitalWrite(_dc, HIGH);\n  digitalWrite(_cs, LOW);\n\n  spiWrite(c);\n\n  digitalWrite(_cs, HIGH);\n}\n\n\nvoid Waveshare_HX8347D::writeData16(uint16_t c) {\n  digitalWrite(_dc, HIGH);\n  digitalWrite(_cs, LOW);\n\n  spiWrite16(c);\n\n  digitalWrite(_cs, HIGH);\n}\n\n\nvoid Waveshare_HX8347D::writeReg(uint8_t cmd, uint8_t param) {\n  digitalWrite(_dc, LOW);\n\n  digitalWrite(_cs, LOW);\n  spiWrite(cmd);\n\n  digitalWrite(_dc, HIGH);\n\n  spiWrite(param);\n  digitalWrite(_cs, HIGH);\n}\n\n\nvoid Waveshare_HX8347D::writeReg16(uint8_t cmd, uint16_t param) {\n  digitalWrite(_dc, LOW);\n\n  digitalWrite(_cs, LOW);\n  spiWrite(cmd);\n\n\n  digitalWrite(_dc, HIGH);\n\n  spiWrite16(param);\n  digitalWrite(_cs, HIGH);\n}\n\n\nvoid Waveshare_HX8347D::begin(uint8_t type) {\n\n  pinMode(_led, OUTPUT);\n  pinMode(_dc,  OUTPUT);\n  pinMode(_cs,  OUTPUT);\n\n  digitalWrite(_cs, HIGH);\n\n  pinMode(5, OUTPUT);\n  pinMode(4, OUTPUT);\n  digitalWrite(5, HIGH);\n  digitalWrite(4, HIGH);\n\n  //SPI.begin();\n  SPI.beginFast();\n\n  SPI.setDataMode(SPI_MODE3);\n  SPI.setBitOrder(MSBFIRST);\n  SPI.setClockDivider(SPI_CLOCK_DIV4);\n\n  initRegs();\n\n  setLedPower(100);\n}\n\nconst uint8_t initdataQT2[] PROGMEM =\n{\n  //driving ability\n  0x40| 2, 0xEA, 0x00,\n  0x40| 2, 0xEB, 0x20,\n  0x40| 2, 0xEC, 0x0C,\n  0x40| 2, 0xED, 0xC4,\n  0x40| 2, 0xE8, 0x40,\n  0x40| 2, 0xE9, 0x38,\n  0x40| 2, 0xF1, 0x01,\n  0x40| 2, 0xF2, 0x10,\n  0x40| 2, 0x27, 0xA3,\n  //power voltage\n  0x40| 2, 0x1B, 0x1B,\n  0x40| 2, 0x1A, 0x01,\n  0x40| 2, 0x24, 0x2F,\n  0x40| 2, 0x25, 0x57,\n  //VCOM offset\n  0x40| 2, 0x23, 0x8D,\n  //power on\n  0x40| 2, 0x18, 0x36,\n  0x40| 2, 0x19, 0x01, //start osc\n  0x40| 2, 0x01, 0x00, //wakeup\n  0x40| 2, 0x1F, 0x88,\n  0xC0| 5, //5ms\n  0x40| 2, 0x1F, 0x80,\n  0xC0| 5, //5ms\n  0x40| 2, 0x1F, 0x90,\n  0xC0| 5, //5ms\n  0x40| 2, 0x1F, 0xD0,\n  0xC0| 5, //5ms\n  //color selection\n  0x40| 2, 0x17, 0x05, //0x05=65k, 0x06=262k\n  //panel characteristic\n  0x40| 2, 0x36, 0x00,\n  //display options\n  0x40| 2, 0x16, 0xA8,\n  0x40| 2, 0x03, 0x00, //x0\n  0x40| 2, 0x02, 0x00, //x0\n  0x40| 2, 0x05, ((HX8347D_TFTWIDTH-1)>>0)&0xFF,\n  0x40| 2, 0x04, ((HX8347D_TFTWIDTH-1)>>8)&0xFF,\n  0x40| 2, 0x07, 0x00, //y0\n  0x40| 2, 0x06, 0x00, //y0\n  0x40| 2, 0x09, ((HX8347D_TFTHEIGHT-1)>>0)&0xFF,\n  0x40| 2, 0x08, ((HX8347D_TFTHEIGHT-1)>>8)&0xFF,\n  //display on\n  0x40| 2, 0x28, 0x38,\n  0xC0|50, //50ms\n  0x40| 2, 0x28, 0x3C,\n  0xC0| 5, //5ms\n  0xFF   , 0xFF\n};\n\n\nvoid Waveshare_HX8347D::initRegs(void)\n{\n  uint_least8_t c, d, i;\n  const PROGMEM uint8_t *ptr;\n\n  //reset\n  digitalWrite(_cs, HIGH);\n\n  //send init commands and data\n  ptr = &initdataQT2[0];\n  while(1)\n  {\n    c = *(ptr);\n    ptr++;\n    if(c == 0xFF) //end of data\n    {\n      break;\n    }\n    switch(c&0xC0)\n    {\n      case 0x40: //command + data\n        for(i=c&0x3F; i!=0; i-=2)\n        {\n          c = *(ptr);\n          ptr++;\n          d = *(ptr);\n          ptr++;\n          writeReg(c, d);\n        }\n        break;\n      case 0xC0: //delay\n        c = c&0x3F;\n        delay(c);\n        break;\n    }\n  }\n\n  //clear display buffer\n  //fillScreen(0);\n\n  return;\n}\n\nvoid Waveshare_HX8347D::setLedPower(uint_least8_t power)\n{\n  if(power == 0) //off\n  {\n    analogWrite(_led, 0);\n    digitalWrite(_led, LOW);\n  }\n  else if(power >= 100) //100%\n  {\n    analogWrite(_led, 255);\n    digitalWrite(_led, HIGH);\n  }\n  else //1...99%\n  {\n    analogWrite(_led, (uint16_t)power*255/100);\n  }\n\n  return;\n}\n\n\nvoid Waveshare_HX8347D::setAddrWindow(uint16_t x0, uint16_t y0, uint16_t x1,\n uint16_t y1) {\n\n  writeReg(0x03, (x0>>0)); //set x0\n  writeReg(0x02, (x0>>8)); //set x0\n  writeReg(0x05, (x1>>0)); //set x1\n  writeReg(0x04, (x1>>8)); //set x1\n  writeReg(0x07, (y0>>0)); //set y0\n  writeReg(0x06, (y0>>8)); //set y0\n  writeReg(0x09, (y1>>0)); //set y1\n  writeReg(0x08, (y1>>8)); //set y1\n\n  writeCommand(0x22);\n}\n\n\nvoid Waveshare_HX8347D::pushColor(uint16_t color) {\n\n  writeData16(color);\n}\n\n\n#if USE_FRAME_BUFFER == 1\n\nvoid Waveshare_HX8347D::drawPixel(int16_t x, int16_t y, uint16_t color) {\n\n  if((x < 0) ||(x >= _width) || (y < 0) || (y >= _height)) return;\n\n  frame_buf[y*_width+x] = color>>8 | color<<8;\n}\n\n\nvoid Waveshare_HX8347D::drawFastVLine(int16_t x, int16_t y, int16_t h,\n uint16_t color) {\n\n  // Rudimentary clipping\n  if((x >= _width) || (y >= _height)) return;\n\n  if((y+h-1) >= _height)\n    h = _height-y;\n\n  color = color>>8 | color<<8;\n\n  for(int i=0; i<h; i++)\n  {\n    frame_buf[(y+i)*_width+x] = color;\n  }\n}\n\n\nvoid Waveshare_HX8347D::drawFastHLine(int16_t x, int16_t y, int16_t w,\n  uint16_t color) {\n\n  // Rudimentary clipping\n  if((x >= _width) || (y >= _height)) return;\n  if((x+w-1) >= _width)  w = _width-x;\n\n\n  color = color>>8 | color<<8;\n\n  for(int i=0; i<w; i++)\n  {\n    frame_buf[y*_width+x+i] = color;\n  }\n\n\n}\n\nvoid Waveshare_HX8347D::fillScreen(uint16_t color) {\n  fillRect(0, 0, _width, _height, color);\n}\n\n// fill a rectangle\nvoid Waveshare_HX8347D::fillRect(int16_t x, int16_t y, int16_t w, int16_t h,\n  uint16_t color) {\n\n  int32_t x_o = x;\n  int32_t y_o = y;\n\n  // rudimentary clipping (drawChar w/big text requires this)\n  if((x >= _width) || (y >= _height)) return;\n  if((x + w - 1) >= _width)  w = _width  - x;\n  if((y + h - 1) >= _height) h = _height - y;\n\n  uint8_t hi = color >> 8, lo = color;\n\n  color = lo<<8 | hi<<0;\n\n  for(y=0; y<h; y++) {\n    for(x=0; x<w; x++) {\n      frame_buf[(y_o+y)*_width+(x_o+x)] = color;\n    }\n  }\n}\n#else\n\n\n\n\n\n\n\n\n\n\n\n\nvoid Waveshare_HX8347D::drawPixel(int16_t x, int16_t y, uint16_t color) {\n\n  if((x < 0) ||(x >= _width) || (y < 0) || (y >= _height)) return;\n\n  setAddrWindow(x,y,x,y);\n  writeData16(color);\n}\n\n\nvoid Waveshare_HX8347D::drawFastVLine(int16_t x, int16_t y, int16_t h,\n uint16_t color) {\n\n  // Rudimentary clipping\n  if((x >= _width) || (y >= _height)) return;\n\n  if((y+h-1) >= _height)\n    h = _height-y;\n\n  setAddrWindow(x, y, x, y+h-1);\n\n  uint8_t hi = color >> 8, lo = color;\n\n  digitalWrite(_dc, HIGH);\n  digitalWrite(_cs, LOW);\n\n  while (h--) {\n    writeData16(color);\n  }\n\n  digitalWrite(_cs, HIGH);\n}\n\n\nvoid Waveshare_HX8347D::drawFastHLine(int16_t x, int16_t y, int16_t w,\n  uint16_t color) {\n\n  // Rudimentary clipping\n  if((x >= _width) || (y >= _height)) return;\n  if((x+w-1) >= _width)  w = _width-x;\n  setAddrWindow(x, y, x+w-1, y);\n\n  uint8_t hi = color >> 8, lo = color;\n  digitalWrite(_dc, HIGH);\n  digitalWrite(_cs, LOW);\n\n  while (w--) {\n    writeData(color);\n  }\n\n  digitalWrite(_cs, HIGH);\n}\n\nvoid Waveshare_HX8347D::fillScreen(uint16_t color) {\n  fillRect(0, 0, _width, _height, color);\n}\n\n\n// fill a rectangle\nvoid Waveshare_HX8347D::fillRect(int16_t x, int16_t y, int16_t w, int16_t h,\n  uint16_t color) {\n\n  // rudimentary clipping (drawChar w/big text requires this)\n  if((x >= _width) || (y >= _height)) return;\n  if((x + w - 1) >= _width)  w = _width  - x;\n  if((y + h - 1) >= _height) h = _height - y;\n\n  setAddrWindow(x, y, x+w-1, y+h-1);\n\n  uint8_t hi = color >> 8, lo = color;\n\n  for(y=h; y>0; y--) {\n    for(x=w; x>0; x--) {\n      pushColor(color);\n    }\n  }\n}\n\n#endif\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n// Pass 8-bit (each) R,G,B, get back 16-bit packed color\nuint16_t Waveshare_HX8347D::color565(uint8_t r, uint8_t g, uint8_t b) {\n  return ((r & 0xF8) << 8) | ((g & 0xFC) << 3) | (b >> 3);\n}\n\n\n#define MADCTL_MY  0x80\n#define MADCTL_MX  0x40\n#define MADCTL_MV  0x20\n#define MADCTL_ML  0x10\n#define MADCTL_RGB 0x00\n#define MADCTL_BGR 0x08\n#define MADCTL_MH  0x04\n\nvoid Waveshare_HX8347D::setRotation(uint8_t m) {\n\n  uint_least8_t p;\n\n\n  rotation = m % 4; // can't be higher than 3\n  switch (rotation) {\n   case 0:\n     //writedata(MADCTL_MX | MADCTL_MY | MADCTL_RGB);\n     _width  = HX8347D_TFTWIDTH;\n     _height = HX8347D_TFTHEIGHT;\n     p = 0xA8; //MY=1 MX=0 MV=1 ML=0 BGR=1\n     break;\n   case 1:\n     //writedata(MADCTL_MV | MADCTL_MY | MADCTL_RGB);\n     _width  = HX8347D_TFTHEIGHT;\n     _height = HX8347D_TFTWIDTH;\n     p = 0x08; //MY=0 MX=0 MV=0 ML=0 BGR=1\n     break;\n  case 2:\n    //writedata( MADCTL_RGB);\n     _width  = HX8347D_TFTWIDTH;\n     _height = HX8347D_TFTHEIGHT;\n     p = 0x68; //MY=0 MX=1 MV=1 ML=0 BGR=1\n    break;\n   case 3:\n     //writedata(MADCTL_MX | MADCTL_MV | MADCTL_RGB);\n     _width  = HX8347D_TFTHEIGHT;\n     _height = HX8347D_TFTWIDTH;\n     p = 0xC8; //MY=1 MX=0 MV=1 ML=0 BGR=1\n     break;\n  }\n\n  writeReg(0x16, p);\n  setAddrWindow(0, 0, _width-1, _height-1);\n}\n\n\nvoid Waveshare_HX8347D::invertDisplay(boolean i) {\n  //writecommand(i ? HX8357_INVON : HX8357_INVOFF);\n}\n\n\nvoid Waveshare_HX8347D::drawFrame(void)\n{\n\n#if USE_FRAME_BUFFER == 1\n  setAddrWindow(0, 0, _width-1, _height-1);\n\n  digitalWrite(_dc, HIGH);\n  digitalWrite(_cs, LOW);\n\n  SPI.writeFast(frame_buf, _width*_height*2);\n\n\n  digitalWrite(_cs, HIGH);\n#endif\n}\n\n\n////////// stuff not actively being used, but kept for posterity\n\n\nuint8_t Waveshare_HX8347D::spiRead(void) {\n  uint8_t r = 0;\n\n  r = SPI.transfer(0x00);\n\n  return r;\n}\n\n uint8_t Waveshare_HX8347D::readData(void) {\n   digitalWrite(_dc, HIGH);\n   digitalWrite(_cs, LOW);\n   uint8_t r = spiRead();\n   digitalWrite(_cs, HIGH);\n\n   return r;\n}\n\n\nuint8_t Waveshare_HX8347D::readCommand(uint8_t c, uint8_t index) {\n   digitalWrite(_dc, LOW);\n   digitalWrite(_cs, LOW);\n\n   spiwrite(c);\n\n   digitalWrite(_dc, HIGH);\n   uint8_t r = spiRead();\n   digitalWrite(_cs, HIGH);\n   return r;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Waveshare_HX8347D/Waveshare_HX8347D.h",
    "content": "/***************************************************\n  This is our library for the Adafruit HX8357D Breakout\n  ----> http://www.adafruit.com/products/2050\n\n  Check out the links above for our tutorials and wiring diagrams\n  These displays use SPI to communicate, 4 or 5 pins are required to\n  interface (RST is optional)\n  Adafruit invests time and resources providing this open source code,\n  please support Adafruit and open-source hardware by purchasing\n  products from Adafruit!\n\n  Written by Limor Fried/Ladyada for Adafruit Industries.\n  MIT license, all text above must be included in any redistribution\n ****************************************************/\n\n#ifndef _WAVESHARE_HX8347D_H\n#define _WAVESHARE_HX8347D_H\n\n#include <Arduino.h>\n#include <Print.h>\n#include <Adafruit_GFX.h>\n#include <avr/pgmspace.h>\n\n\n\n#define HX8347D_TFTWIDTH  320\n#define HX8347D_TFTHEIGHT 240\n\n\n#define\tHX8347D_BLACK   0x0000\n#define\tHX8347D_BLUE    0x001F\n#define\tHX8347D_RED     0xF800\n#define\tHX8347D_GREEN   0x07E0\n#define HX8347D_CYAN    0x07FF\n#define HX8347D_MAGENTA 0xF81F\n#define HX8347D_YELLOW  0xFFE0\n#define HX8347D_WHITE   0xFFFF\n\n\nclass Waveshare_HX8347D : public Adafruit_GFX {\n\n public:\n\n  Waveshare_HX8347D(int8_t _cs = 10, int8_t _dc = 7, int8_t _led = 9, int8_t _rst = -1);\n\n  void      begin(uint8_t type = 0);\n  void      setAddrWindow(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1);\n  void      pushColor(uint16_t color);\n  void      fillScreen(uint16_t color);\n  void      drawPixel(int16_t x, int16_t y, uint16_t color);\n  void      drawFastVLine(int16_t x, int16_t y, int16_t h, uint16_t color);\n  void      drawFastHLine(int16_t x, int16_t y, int16_t w, uint16_t color);\n  void      fillRect(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color);\n  void      setRotation(uint8_t r);\n  void      invertDisplay(boolean i);\n  uint16_t  color565(uint8_t r, uint8_t g, uint8_t b);\n\n\n  void      spiwrite(uint8_t);\n  uint8_t   spiRead(void);\n\n\n  uint8_t   readData(void);\n  uint8_t   readCommand(uint8_t reg, uint8_t index = 0);\n\n  void      writeCommand(uint8_t c);\n  void      writeData(uint8_t d);\n  void      writeData16(uint16_t c);\n\n  void      writeReg(uint8_t cmd, uint8_t param);\n  void      writeReg16(uint8_t cmd, uint16_t param);\n\n  void      setLedPower(uint_least8_t power);\n\n  void      drawFrame(void);\n\n private:\n  uint8_t tabcolor;\n  int8_t  _cs, _dc, _rst, _led;\n\n\n  void initRegs(void);\n};\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Waveshare_HX8347D/library.properties",
    "content": "name=Waveshare HX8347D\nversion=1.0.0\nauthor=ROBOTIS\nmaintainer=chc@robotis.com\nsentence=Waveshare HX8347D display library for OpenCR\nparagraph=Waveshare HX8347D display library for OpenCR\ncategory=Display\nurl=\narchitectures=OpenCR\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Wire/README",
    "content": "Wirish soft (bit-banged) implementation of the Wire I2C library.\n\nThis implementation is synchronous, and thus supports only a subset of\nthe full Wire interface.  \n\nBe sure to tie SDA and SCL high with ~2k resistors\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Wire/SlowSoftI2CMaster.cpp",
    "content": "/* Arduino Slow Software I2C Master \n   Copyright (c) 2017 Bernhard Nebel.\n\n   This library is free software; you can redistribute it and/or\n   modify it under the terms of the GNU Lesser General Public License\n   as published by the Free Software Foundation; either version 3 of\n   the License, or (at your option) any later version.\n\n   This library is distributed in the hope that it will be useful, but\n   WITHOUT ANY WARRANTY; without even the implied warranty of\n   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n   Lesser General Public License for more details.\n\n   You should have received a copy of the GNU Lesser General Public\n   License along with this library; if not, write to the Free Software\n   Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301\n   USA\n*/\n\n\n\n#include <SlowSoftI2CMaster.h>\n\nSlowSoftI2CMaster::SlowSoftI2CMaster(uint8_t sda, uint8_t scl) {\n  _sda = sda;\n  _scl = scl;\n  _pullup = false;\n}\n\nSlowSoftI2CMaster::SlowSoftI2CMaster(uint8_t sda, uint8_t scl, bool internal_pullup) {\n  _sda = sda;\n  _scl = scl;\n  _pullup = internal_pullup;\n}\n// Init function. Needs to be called once in the beginning.\n// Returns false if SDA or SCL are low, which probably means \n// a I2C bus lockup or that the lines are not pulled up.\nbool SlowSoftI2CMaster::i2c_init(void) {\n  digitalWrite(_sda, LOW);\n  digitalWrite(_scl, LOW);\n  setHigh(_sda);\n  setHigh(_scl);\n  if (digitalRead(_sda) == LOW || digitalRead(_scl) == LOW) return false;\n  return true;\n}\n\nbool SlowSoftI2CMaster::i2c_init(uint8_t sda_pin, uint8_t scl_pin) {\n\n  _sda = sda_pin;\n  _scl = scl_pin;\n\n  return i2c_init();\n}\n\n// Start transfer function: <addr> is the 8-bit I2C address (including the R/W\n// bit). \n// Return: true if the slave replies with an \"acknowledge\", false otherwise\nbool SlowSoftI2CMaster::i2c_start(uint8_t addr) {\n  setLow(_sda);\n  delayMicroseconds(DELAY);\n  setLow(_scl);\n  return i2c_write(addr);\n}\n\n// Try to start transfer until an ACK is returned\nvoid SlowSoftI2CMaster::i2c_start_wait(uint8_t addr) {\n  while (!i2c_start(addr)) i2c_stop();\n}\n\n// Repeated start function: After having claimed the bus with a start condition,\n// you can address another or the same chip again without an intervening \n// stop condition.\n// Return: true if the slave replies with an \"acknowledge\", false otherwise\nbool SlowSoftI2CMaster::i2c_rep_start(uint8_t addr) {\n  setHigh(_sda);\n  setHigh(_scl);\n  delayMicroseconds(DELAY);\n  return i2c_start(addr);\n}\n\n// Issue a stop condition, freeing the bus.\nvoid SlowSoftI2CMaster::i2c_stop(void) {\n  setLow(_sda);\n  delayMicroseconds(DELAY);\n  setHigh(_scl);\n  delayMicroseconds(DELAY);\n  setHigh(_sda);\n  delayMicroseconds(DELAY);\n}\n\n// Write one byte to the slave chip that had been addressed\n// by the previous start call. <value> is the byte to be sent.\n// Return: true if the slave replies with an \"acknowledge\", false otherwise\nbool SlowSoftI2CMaster::i2c_write(uint8_t value) {\n  for (uint8_t curr = 0X80; curr != 0; curr >>= 1) {\n    if (curr & value) setHigh(_sda); else  setLow(_sda); \n    setHigh(_scl);\n    delayMicroseconds(DELAY);\n    setLow(_scl);\n  }\n  // get Ack or Nak\n  setHigh(_sda);\n  setHigh(_scl);\n  delayMicroseconds(DELAY/2);\n  uint8_t ack = digitalRead(_sda);\n  setLow(_scl);\n  delayMicroseconds(DELAY/2);\n  setLow(_sda);\n  return ack == 0;\n}\n\n// Read one byte. If <last> is true, we send a NAK after having received \n// the byte in order to terminate the read sequence. \nuint8_t SlowSoftI2CMaster::i2c_read(bool last) {\n  uint8_t b = 0;\n  setHigh(_sda);\n  for (uint8_t i = 0; i < 8; i++) {\n    b <<= 1;\n    delayMicroseconds(DELAY);\n    setHigh(_scl);\n    if (digitalRead(_sda)) b |= 1;\n    setLow(_scl);\n  }\n  if (last) setHigh(_sda); else setLow(_sda);\n  setHigh(_scl);\n  delayMicroseconds(DELAY/2);\n  setLow(_scl);\n  delayMicroseconds(DELAY/2);\n  setLow(_sda);\n  return b;\n}\n\nvoid SlowSoftI2CMaster::setLow(uint8_t pin) {\n    noInterrupts();\n    if (_pullup)\n      digitalWrite(pin, LOW);\n    pinMode(pin, OUTPUT);\n    interrupts();\n}\n\n\nvoid SlowSoftI2CMaster::setHigh(uint8_t pin) {\n    noInterrupts();\n    if (_pullup)\n      pinMode(pin, INPUT_PULLUP);\n    else\n      pinMode(pin, INPUT);\n    interrupts();\n}\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Wire/SlowSoftI2CMaster.h",
    "content": "/* Arduino Slow Software I2C Master \n   Copyright (c) 2017 Bernhard Nebel.\n\n   This library is free software; you can redistribute it and/or\n   modify it under the terms of the GNU Lesser General Public\n   License as published by the Free Software Foundation; either\n   version 3 of the License, or (at your option) any later version.\n\n   This library is distributed in the hope that it will be useful,\n   but WITHOUT ANY WARRANTY; without even the implied warranty of\n   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n   Lesser General Public License for more details.\n\n   You should have received a copy of the GNU Lesser General Public\n   License along with this library; if not, write to the Free Software\n   Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n#ifndef SLOW_SOFT_I2C_MASTER_H\n#define SLOW_SOFT_I2C_MASTER_H\n\n#include <Arduino.h>\n#include <inttypes.h>\n\n#define I2C_READ      1\n#define I2C_WRITE     0\n#define DELAY         0 // usec delay\n#define BUFFER_LENGTH 32\n\nclass SlowSoftI2CMaster {\n public:\n  SlowSoftI2CMaster(uint8_t sda, uint8_t scl);\n  SlowSoftI2CMaster(uint8_t sda, uint8_t scl, bool internal_pullup);\n  bool i2c_init(void);\n  bool i2c_init(uint8_t sda_pin, uint8_t scl_pin);\n  bool i2c_start(uint8_t addr);\n  void i2c_start_wait(uint8_t addr);\n  bool i2c_rep_start(uint8_t addr);\n  void i2c_stop(void);\n  bool i2c_write(uint8_t value);\n  uint8_t i2c_read(bool last);\n  bool error;\n  \n private:\n  void setHigh(uint8_t pin);\n  void setLow(uint8_t pin);\n  uint8_t _sda;\n  uint8_t _scl;\n  bool _pullup;\n};\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Wire/Wire.cpp",
    "content": "/*\n   TwoWire.cpp - A Wire-like wrapper for SlowSoftI2CMaster.\n\n   It is derived from the Arduino Wire library and for this reason is\n   published under the terms of the GNU Lesser General Public License\n   as published by the Free Software Foundation; either version 2.1 of\n   the License, or (at your option) any later version.\n*/\n\n#include <Wire.h>\n\n#ifdef USE_SLOW_SOFT_I2C_MASTER\n\n//=============================================================================\n// Software I2C - master only\n//=============================================================================\nTwoWire::TwoWire(uint8_t sda, uint8_t scl) {\n  si2c = new SlowSoftI2CMaster(sda, scl);\n}\n\nvoid TwoWire::begin(void) {\n  rxBufferIndex = 0;\n  rxBufferLength = 0;\n  error = 0;\n  transmitting = false;\n\n  si2c->i2c_init();\n}\n\nvoid TwoWire::begin(uint8_t sda_pin, uint8_t scl_pin) {\n  rxBufferIndex = 0;\n  rxBufferLength = 0;\n  error = 0;\n  transmitting = false;\n\n  si2c->i2c_init(sda_pin, scl_pin);\n}\n\nvoid  TwoWire::end(void) {\n  free(si2c);\n  si2c = NULL;\n}\n\nvoid  TwoWire::setClock(uint32_t frequency) {\n  UNUSED(frequency);  // Change at some point?\n}\n\nvoid  TwoWire::beginTransmission(uint8_t address) {\n  if (transmitting) {\n    error = (si2c->i2c_rep_start((address<<1)|I2C_WRITE) ? 0 : 2);\n  } else {\n    error = (si2c->i2c_start((address<<1)|I2C_WRITE) ? 0 : 2);\n  }\n  // indicate that we are transmitting\n  transmitting = 1;\n}\n\nvoid  TwoWire::beginTransmission(int address) {\n  beginTransmission((uint8_t)address);\n}\n\nuint8_t  TwoWire::endTransmission(uint8_t sendStop)\n{\n  uint8_t transError = error;\n  if (sendStop) {\n    si2c->i2c_stop();\n    transmitting = 0;\n  }\n  error = 0;\n  return transError;\n}\n\n//  This provides backwards compatibility with the original\n//  definition, and expected behaviour, of endTransmission\n//\nuint8_t  TwoWire::endTransmission(void)\n{\n  return endTransmission(true);\n}\n\nsize_t  TwoWire::write(uint8_t data) {\n  if (si2c->i2c_write(data)) {\n    return 1;\n  } else {\n    if (error == 0) error = 3;\n    return 0;\n  }\n}\n\nsize_t  TwoWire::write(const uint8_t *data, size_t quantity) {\n  size_t trans = 0;\n  for(size_t i = 0; i < quantity; ++i){\n    trans += write(data[i]);\n  }\n  return trans;\n}\n\nuint8_t TwoWire::requestFrom(uint8_t address, uint8_t quantity,\n        uint32_t iaddress, uint8_t isize, uint8_t sendStop) {\n  uint8_t localerror = 0;\n  if (isize > 0) {\n    // send internal address; this mode allows sending a repeated start to access\n    // some devices' internal registers. This function is executed by the hardware\n    // TWI module on other processors (for example Due's TWI_IADR and TWI_MMR registers)\n    beginTransmission(address);\n    // the maximum size of internal address is 3 bytes\n    if (isize > 3){\n      isize = 3;\n    }\n    // write internal register address - most significant byte first\n    while (isize-- > 0)\n      write((uint8_t)(iaddress >> (isize*8)));\n    endTransmission(false);\n  }\n  // clamp to buffer length\n  if(quantity > BUFFER_LENGTH){\n    quantity = BUFFER_LENGTH;\n  }\n  localerror = !si2c->i2c_rep_start((address<<1) | I2C_READ);\n  if (error == 0 && localerror) error = 2;\n  // perform blocking read into buffer\n  for (uint8_t cnt=0; cnt < quantity; cnt++)\n    rxBuffer[cnt] = si2c->i2c_read(cnt == quantity-1);\n  // set rx buffer iterator vars\n  rxBufferIndex = 0;\n  rxBufferLength = quantity;\n  if (sendStop) {\n    transmitting = 0;\n    si2c->i2c_stop();\n  }\n  return quantity;\n}\n\nuint8_t TwoWire::requestFrom(uint8_t address, uint8_t quantity, uint8_t sendStop) {\n  return requestFrom((uint8_t)address, (uint8_t)quantity, (uint32_t)0, (uint8_t)0, (uint8_t)sendStop);\n}\n\nuint8_t TwoWire::requestFrom(int address, int quantity, int sendStop) {\n  return requestFrom((uint8_t)address, (uint8_t)quantity, (uint8_t)sendStop);\n}\n\n\nuint8_t TwoWire::requestFrom(uint8_t address, uint8_t quantity) {\n  return requestFrom((uint8_t)address, (uint8_t)quantity, (uint8_t)true);\n}\n\nuint8_t TwoWire::requestFrom(int address, int quantity) {\n  return requestFrom((uint8_t)address, (uint8_t)quantity, (uint8_t)true);\n}\n\nint TwoWire::available(void) {\n  return rxBufferLength - rxBufferIndex;\n}\n\nint TwoWire::read(void) {\n  int value = -1;\n  if(rxBufferIndex < rxBufferLength){\n    value = rxBuffer[rxBufferIndex];\n    ++rxBufferIndex;\n  }\n  return value;\n}\n\nint TwoWire::peek(void) {\n  int value = -1;\n\n  if(rxBufferIndex < rxBufferLength){\n    value = rxBuffer[rxBufferIndex];\n  }\n  return value;\n}\n\nvoid TwoWire::flush(void) {\n}\n\nTwoWire Wire(14, 15);\n\n\n#else\n//=============================================================================\n// Hardware I2C\n//=============================================================================\n#ifdef WIRE_USE_DEBUG_IO_PINS\n#include <digitalWriteFast.h>\n#define debugDigitalWrite(pin, value) digitalWriteFast((pin), (value))\n#else\n#define debugDigitalWrite(pin, value)\n#endif\n\n\n#define I2C_TIMEOUT_ADDR    ((uint32_t)10000)       /* 10 s  */\n#define I2C_TIMEOUT_BUSY    ((uint32_t)25)          /* 25 ms */\n#define I2C_TIMEOUT_DIR     ((uint32_t)25)          /* 25 ms */\n#define I2C_TIMEOUT_RXNE    ((uint32_t)25)          /* 25 ms */\n#define I2C_TIMEOUT_STOPF   ((uint32_t)25)          /* 25 ms */\n#define I2C_TIMEOUT_TC      ((uint32_t)25)          /* 25 ms */\n#define I2C_TIMEOUT_TCR     ((uint32_t)25)          /* 25 ms */\n#define I2C_TIMEOUT_TXIS    ((uint32_t)25)          /* 25 ms */\n#define I2C_TIMEOUT_FLAG    ((uint32_t)25)          /* 25 ms */\n\n\n\nTwoWire::TwoWire(I2C_HandleTypeDef *hi2c) {\n  hi2c_ = hi2c; // remember the i2c object\n  \n  // Init some of the I2C Handle init structure. \n  hi2c_->Init.OwnAddress1     = 0x00;  // Lets init the whole structure.\n  hi2c_->Init.AddressingMode  = I2C_ADDRESSINGMODE_7BIT;\n  hi2c_->Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;\n  hi2c_->Init.OwnAddress2     = 0xFF;\n  hi2c_->Init.OwnAddress2Masks  = I2C_OA2_NOMASK;\n  hi2c_->Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;\n  hi2c_->Init.NoStretchMode   = I2C_NOSTRETCH_DISABLE;\n  user_onRequest = NULL;\n  user_onReceive = NULL;\n\n  frequency_ = 100000;\n  state_ = 0; // Begin has not been called. \n  sendStop_ = 1;      // assume last call did a stop...\n}\n\n\nvoid TwoWire::begin(void) {\n  hi2c_->Init.OwnAddress1 = 0x00;\n\n  rxBufferIndex = 0;\n  rxBufferLength = 0;\n  txBufferIndex = 0;\n  txBufferLength = 0;\n  error = 0;\n  slave_mode = 0;\n  transmitting = false;\n  state_ = 1;\n#ifdef WIRE_USE_DEBUG_IO_PINS\n  pinMode(WIRE_DEBUG_RECEIVE_FROM, OUTPUT);\n  digitalWriteFast(WIRE_DEBUG_RECEIVE_FROM, LOW);\n  pinMode(WIRE_DEBUG_END_TRANSFER, OUTPUT);\n  digitalWriteFast(WIRE_DEBUG_END_TRANSFER, LOW);\n#endif\n  setClock(frequency_);   // set the clock.\n}\n\nvoid TwoWire::begin(uint8_t address) {\n  // TODO: Implement slave mode. \n  hi2c_->Init.OwnAddress1 = address << 1;  // 7 bit passed in\n  rxBufferIndex = 0;\n  rxBufferLength = 0;\n  txBufferIndex = 0;\n  txBufferLength = 0;\n  error = 0;\n  slave_mode = 1;  // Need to see how to update slave address and direction with init?\n  transmitting = false;\n  state_ = 1;\n  setClock(frequency_);   // set the clock.\n\n  // Setup to get interrupt when we get a slave address match\n  __HAL_I2C_ENABLE_IT(hi2c_, I2C_IT_ADDRI);\n}\n\n\nvoid  TwoWire::end(void) {\n  HAL_I2C_DeInit(hi2c_);\n  state_ = 0;\n}\n\nvoid  TwoWire::setClock(uint32_t frequency) {\n  if (state_) {\n    // BUGBUG: Need to figure this out more...\n    if     (frequency <  400000 ) hi2c_->Init.Timing = 0x20404768; // Ask for something < 400K use 100K\n    else if(frequency < 1000000 ) hi2c_->Init.Timing = 0x6000030D; // Ask for someting under 1000K so use 400K\n    else                          hi2c_->Init.Timing = 0x00200922; // 0x50310001; // Ask for 1000K+ try to give 1000K\n\n    HAL_StatusTypeDef hal_status;\n    if ((hal_status = HAL_I2C_Init(hi2c_)) != HAL_OK) {  // Maybe should check for success...\n      //Serial.printf(\"HAL_I2C_Init failed: %d\\n\", (int)hal_status);\n    }\n    /* Enable the Analog I2C Filter */\n    HAL_I2CEx_ConfigAnalogFilter(hi2c_,I2C_ANALOGFILTER_ENABLE);\n  } else {\n    frequency_ = frequency; // remember it away. \n  }\n}\n\nvoid  TwoWire::beginTransmission(uint8_t address) {\n  device_address = address << 1; // save away the address, preshift it\n  transmitting = 1;\n  txBufferLength = 0;\n}\n\nvoid  TwoWire::beginTransmission(int address) {\n  beginTransmission((uint8_t)address);\n}\n\n\nuint8_t  TwoWire::endTransmission(uint8_t sendStop)\n{\n  // Not sure how to control if send stop or not?\n  if (transmitting) {\n    //status = HAL_I2C_Master_Transmit(hi2c_, device_address<<1, txBuffer, txBufferLength, WIRE_TX_TIMEOUT);\n    uint8_t *pData = txBuffer;\n    uint16_t Size = txBufferLength;\n  \n    if(hi2c_->State != HAL_I2C_STATE_READY) return HAL_BUSY;\n\n    // If our last call did a sendStop we should not do something if bus is busy\n    if(sendStop_ && (__HAL_I2C_GET_FLAG(hi2c_, I2C_FLAG_BUSY) == SET)) return HAL_BUSY;\n\n    /* Process Locked */\n    __HAL_LOCK(hi2c_);\n    \n    hi2c_->State = HAL_I2C_STATE_MASTER_BUSY_TX;\n    hi2c_->ErrorCode   = HAL_I2C_ERROR_NONE;\n    \n    // Now lets build the CR2 register. \n    // Mode will depend on if sendStop is set\n    transferConfig(device_address,txBufferLength, sendStop? I2C_AUTOEND_MODE : I2C_SOFTEND_MODE, \n        I2C_GENERATE_START_WRITE);\n\n    sendStop_ = sendStop; // remember for the next call...\n\n    while(Size > 0) {\n      /* Wait until TXIS flag is set */\n      if(waitOnTXISFlagUntilTimeout(WIRE_TX_TIMEOUT) != HAL_OK) {\n        if(hi2c_->ErrorCode == HAL_I2C_ERROR_AF) {\n          return HAL_ERROR; \n        } else {\n          return HAL_TIMEOUT;\n        }\n      }\n\n      /* Write data to TXDR */\n      hi2c_->Instance->TXDR = (*pData++);\n      Size--;\n    }\n    \n    // Check to see which flag we should get at the end...\n    if (sendStop) {\n      if(waitOnFlagUntilTimeout( I2C_FLAG_STOPF, I2C_TIMEOUT_STOPF) != HAL_OK) {\n        if(hi2c_->ErrorCode == HAL_I2C_ERROR_AF) {\n          return HAL_ERROR; \n        } else {\n          return HAL_TIMEOUT;\n        }\n      }\n      __HAL_I2C_CLEAR_FLAG(hi2c_, I2C_FLAG_STOPF);\n  \n      /* Clear Configuration Register 2 */\n      I2C_RESET_CR2(hi2c_);\n    } else {\n      // not generating stop so wait until Transfer complete\n      debugDigitalWrite(WIRE_DEBUG_END_TRANSFER, HIGH);\n      if(waitOnFlagUntilTimeout(I2C_FLAG_TC, WIRE_TX_TIMEOUT) != HAL_OK) {\n        debugDigitalWrite(WIRE_DEBUG_END_TRANSFER, LOW);\n        debugDigitalWrite(WIRE_DEBUG_END_TRANSFER, HIGH);\n        debugDigitalWrite(WIRE_DEBUG_END_TRANSFER, LOW);\n        if(hi2c_->ErrorCode == HAL_I2C_ERROR_AF) {\n          return HAL_ERROR; \n        } else {\n          return HAL_TIMEOUT;\n        }\n      }\n      debugDigitalWrite(WIRE_DEBUG_END_TRANSFER, LOW);\n      // Not sure if we need to reset CR2?  or wait for stop condtion? \n      // Assuming not and next transfer will do it.\n    }\n  \n    hi2c_->State = HAL_I2C_STATE_READY;    \n  \n    /* Process Unlocked */\n    __HAL_UNLOCK(hi2c_);\n\n    transmitting = false; \n  }\n  return 0; \n}\n\n//  This provides backwards compatibility with the original\n//  definition, and expected behaviour, of endTransmission\n//\nuint8_t  TwoWire::endTransmission(void)\n{\n  return endTransmission(true);\n}\n\nsize_t  TwoWire::write(uint8_t data) {\n  if (transmitting || slave_mode) {\n    if (txBufferLength >= BUFFER_LENGTH+1) {\n      setWriteError();\n      return 0;\n    }\n    txBuffer[txBufferLength++] = data;\n    return 1;\n  }\n  return 0;\n}\n\nsize_t  TwoWire::write(const uint8_t *data, size_t quantity) {\n  size_t trans = 0;\n  for(size_t i = 0; i < quantity; ++i){\n    trans += write(data[i]);\n  }\n  return trans;\n}\n\n#ifdef LATER\nuint8_t TwoWire::requestFrom(uint8_t address, uint8_t quantity,\n        uint32_t iaddress, uint8_t isize, uint8_t sendStop) {\n}\n#endif\n\nuint8_t TwoWire::requestFrom(uint8_t address, uint8_t quantity, uint8_t sendStop) {\n  // Hardware I2C... \n  rxBufferIndex = 0;\n  rxBufferLength = 0;\n  uint8_t *data_in_ptr = rxBuffer;\n  if (quantity > sizeof(rxBuffer)) {\n    quantity = sizeof(rxBuffer);\n  }\n  uint8_t count_left_to_read = quantity;\n\n  if(hi2c_->State == HAL_I2C_STATE_READY)\n  {    \n    // If last call did a sendStop then we should not continue if the BUS is busy\n    if(sendStop_ && (__HAL_I2C_GET_FLAG(hi2c_, I2C_FLAG_BUSY) == SET))\n    {\n      //Serial.println(\"TwoWire::requestFrom Busy\");\n      return 0; //HAL_BUSY;\n    }\n    /* Process Locked */\n    __HAL_LOCK(hi2c_);\n    \n    hi2c_->State = HAL_I2C_STATE_MASTER_BUSY_RX;\n    hi2c_->ErrorCode   = HAL_I2C_ERROR_NONE;\n    \n    transferConfig(address<<1,  quantity, sendStop? I2C_AUTOEND_MODE : I2C_SOFTEND_MODE, \n        I2C_GENERATE_START_READ);\n    sendStop_ = sendStop; // remember for the next call...\n    \n    do\n    {\n      /* Wait until RXNE flag is set */\n      HAL_StatusTypeDef hstatus;\n      if((hstatus = waitOnRXNEFlagUntilTimeout(I2C_TIMEOUT_RXNE)) != HAL_OK) {\n          //Serial.printf(\"TwoWire::requestFrom RXNE %d %d\\n\", hstatus, count_left_to_read);\n          rxBufferLength = quantity - count_left_to_read;  // BUGBUG: seeing what was actually read\n\n          return 0; // an error\n      }       \n      \n      /* Write data to RXDR */\n\n      debugDigitalWrite(WIRE_DEBUG_RECEIVE_FROM, HIGH);\n      (*data_in_ptr++) =hi2c_->Instance->RXDR;\n      count_left_to_read--;\n      debugDigitalWrite(WIRE_DEBUG_RECEIVE_FROM, LOW);\n\n    } while(count_left_to_read > 0);\n    \n\n    if (sendStop) {\n      /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\n      /* Wait until STOPF flag is set */\n      if(waitOnFlagUntilTimeout( I2C_FLAG_STOPF, I2C_TIMEOUT_STOPF) != HAL_OK) {\n        //Serial.println(\"TwoWire::requestFrom STOPF\");\n        return 0; // no bytes\n      }\n      \n      /* Clear STOP Flag */\n      __HAL_I2C_CLEAR_FLAG(hi2c_, I2C_FLAG_STOPF);\n      \n      /* Clear Configuration Register 2 */\n      I2C_RESET_CR2(hi2c_);\n    } else {\n      // not generating stop so wait until Transfer compelte\n      if(waitOnFlagUntilTimeout(I2C_FLAG_TC, WIRE_TX_TIMEOUT) != HAL_OK) {\n        if(hi2c_->ErrorCode == HAL_I2C_ERROR_AF) {\n          return HAL_ERROR; \n        } else {\n          return HAL_TIMEOUT;\n        }\n      }\n      // Not sure if we need to reset CR2?  or wait for stop condtion? \n      // Assuming not and next transfer will do it.\n    }    \n    hi2c_->State = HAL_I2C_STATE_READY;    \n    \n    /* Process Unlocked */\n    __HAL_UNLOCK(hi2c_);\n    rxBufferLength = quantity;\n    \n    return quantity;\n  }\n  //Serial.println(\"TwoWire::requestFrom not Ready\");\n  return 0;  // An error so say we did not receive anything.  \n}\n\nuint8_t TwoWire::requestFrom(int address, int quantity, int sendStop) {\n  return requestFrom((uint8_t)address, (uint8_t)quantity, (uint8_t)sendStop);\n}\n\n\nuint8_t TwoWire::requestFrom(uint8_t address, uint8_t quantity) {\n  return requestFrom((uint8_t)address, (uint8_t)quantity, (uint8_t)true);\n}\n\nuint8_t TwoWire::requestFrom(int address, int quantity) {\n  return requestFrom((uint8_t)address, (uint8_t)quantity, (uint8_t)true);\n}\n\nint TwoWire::available(void) {\n  return rxBufferLength - rxBufferIndex;\n}\n\nint TwoWire::read(void) {\n  int value = -1;\n  if(rxBufferIndex < rxBufferLength){\n    value = rxBuffer[rxBufferIndex];\n    ++rxBufferIndex;\n  }\n  return value;\n}\n\nint TwoWire::peek(void) {\n  int value = -1;\n\n  if(rxBufferIndex < rxBufferLength){\n    value = rxBuffer[rxBufferIndex];\n  }\n  return value;\n}\n\nvoid TwoWire::flush(void) {\n}\n\n\nvoid TwoWire::onReceive(void (*function)(int numBytes)) {\n  user_onReceive = function;\n}\n\nvoid TwoWire::onRequest(void (*function)(void)) {\n  user_onRequest = function;\n}\n\n//=============================================================================\n// Callback functions from HAL I2C\n//=============================================================================\n\n//-------------------------------------\n// Process Address match\n//-------------------------------------\nvoid HAL_I2C_SlaveAddrCpltCallback(I2C_HandleTypeDef *hi2c) {\n  if (hi2c == Wire.hi2c_) {\n    Wire.processAddrCallback();\n  } else if (hi2c == Wire1.hi2c_ )\n    Wire1.processAddrCallback();  \n}\n\n// Process Address select callback\nvoid TwoWire::processAddrCallback(void) {\n  // lets check to see they are writing data to us or wanting data from us\n  if (__HAL_I2C_GET_FLAG(hi2c_, I2C_FLAG_DIR) == SET) {\n    // We received request from other side, so, lets call of to our \n    // users call back to let them put data into TX buffer.  \n    // Not sure if we should clear buffer first?  Will start off doing so\n    txBufferIndex = 0;\n    txBufferLength = 0;\n    if (user_onRequest) {\n      (*user_onRequest)();\n      __HAL_I2C_CLEAR_FLAG(hi2c_, I2C_FLAG_TXE); // Clear out anything that was previously in TXDR\n      HAL_I2C_Slave_Transmit_IT(hi2c_, txBuffer, txBufferLength);\n    }\n\n  } else {\n    // They are sending us data setup to do receive...\n    HAL_I2C_Slave_Receive_IT(hi2c_, rxBuffer, sizeof(rxBuffer));\n  }\n}\n\n\n//-------------------------------------\n// Process slave receiving data complete\n//-------------------------------------\nvoid HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) {\n  // map this handle to which Wire object\n  if (hi2c == Wire.hi2c_) {\n    Wire.processRXCallback();\n  } else if (hi2c == Wire1.hi2c_ )\n    Wire1.processRXCallback();  \n}\n\nvoid TwoWire::processRXCallback(void) {\n  // Lets see if we can figure out what happened...\n  rxBufferLength = (uint32_t)(hi2c_->pBuffPtr-rxBuffer);\n  rxBufferIndex = 0;  // setup the index to first one\n//  Serial.printf(\"ProcessRXCallback: %x %x %x %d\\n\", (uint32_t)hi2c_->pBuffPtr,\n//    hi2c_->XferSize, hi2c_->XferCount, rxBufferLength);\n\n  if (user_onReceive) {\n    (*user_onReceive)(rxBufferLength);\n  }\n  // Setup to try to receive next message.\n  HAL_I2C_Slave_Receive_IT(hi2c_, rxBuffer, sizeof(rxBuffer));\n}\n\n//-------------------------------------\n// Process slave transmit data complete\n//-------------------------------------\nvoid HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) {\n  // map this handle to which Wire object\n  if (hi2c == Wire.hi2c_) {\n    Wire.processTXCallback();\n  } else if (hi2c == Wire1.hi2c_ )\n    Wire1.processTXCallback();  \n}\n\nvoid TwoWire::processTXCallback(void) {\n  // Lets see if we can figure out what happened...\n  txBufferLength = (uint32_t)(hi2c_->pBuffPtr-txBuffer);\n  \n  HAL_I2C_Slave_Transmit_IT(hi2c_, txBuffer, txBufferLength);\n}\n\n//-------------------------------------\n// Process HAL errors detected\n//-------------------------------------\nvoid HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) {\n  UNUSED(hi2c);\n  //Serial.println(\"HAL_I2C_ErrorCallback called\");\n}\n\n\n//=============================================================================\n// Helper functions from stm32fxx_hal_i2c.c\n//=============================================================================\nHAL_StatusTypeDef TwoWire::waitOnTXISFlagUntilTimeout(uint32_t Timeout)  \n{  \n  uint32_t tickstart = HAL_GetTick();\n  \n  while(__HAL_I2C_GET_FLAG(hi2c_, I2C_FLAG_TXIS) == RESET)\n  {\n    /* Check if a NACK is detected */\n    if(isAcknowledgeFailed(Timeout) != HAL_OK)\n    {\n      return HAL_ERROR;\n    }\n    \n    /* Check for the Timeout */\n    if(Timeout != HAL_MAX_DELAY)\n    {\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\n      {\n        hi2c_->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\n        hi2c_->State= HAL_I2C_STATE_READY;\n        \n        /* Process Unlocked */\n        __HAL_UNLOCK(hi2c_);\n        \n        return HAL_TIMEOUT;\n      }\n    }\n  }\n  return HAL_OK;      \n}\n\n\nHAL_StatusTypeDef TwoWire::waitOnRXNEFlagUntilTimeout(uint32_t Timeout)\n{  \n  uint32_t tickstart = 0x00;\n  tickstart = HAL_GetTick();\n  \n  while(__HAL_I2C_GET_FLAG(hi2c_, I2C_FLAG_RXNE) == RESET)\n  {\n    /* Check if a NACK is detected */\n    if(isAcknowledgeFailed(Timeout) != HAL_OK)\n    {\n      //Serial.println(\"NACK\");\n      return HAL_ERROR;\n    }\n    \n    // See if it was set during the wait for ACK...\n    if(__HAL_I2C_GET_FLAG(hi2c_, I2C_FLAG_RXNE) != RESET) \n    {\n      break;  // Data is available so break out of loop\n    }\n\n    /* Check if a STOPF is detected */\n    if(__HAL_I2C_GET_FLAG(hi2c_, I2C_FLAG_STOPF) == SET)\n    {\n      /* Clear STOP Flag */\n      __HAL_I2C_CLEAR_FLAG(hi2c_, I2C_FLAG_STOPF);\n      \n      /* Clear Configuration Register 2 */\n      I2C_RESET_CR2(hi2c_);\n      \n      hi2c_->ErrorCode = HAL_I2C_ERROR_NONE;\n      hi2c_->State= HAL_I2C_STATE_READY;\n      \n      /* Process Unlocked */\n      __HAL_UNLOCK(hi2c_);\n      \n      //Serial.println(\"STOPF\");\n      return HAL_ERROR;\n    }\n    \n    /* Check for the Timeout */\n    if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\n    {\n      hi2c_->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\n      hi2c_->State= HAL_I2C_STATE_READY;\n      \n      /* Process Unlocked */\n      __HAL_UNLOCK(hi2c_);\n      \n      return HAL_TIMEOUT;\n    }\n  }\n  return HAL_OK;\n}\n\n\n\nHAL_StatusTypeDef TwoWire::waitOnFlagUntilTimeout(uint32_t flag, uint32_t Timeout)\n{  \n  uint32_t tickstart = 0x00;\n  tickstart = HAL_GetTick();\n  \n  while(__HAL_I2C_GET_FLAG(hi2c_, flag) == RESET)\n  {\n    /* Check if a NACK is detected */\n    if(isAcknowledgeFailed(Timeout) != HAL_OK)\n    {\n      return HAL_ERROR;\n    }\n    \n    /* Check for the Timeout */\n    if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\n    {\n      hi2c_->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\n      hi2c_->State= HAL_I2C_STATE_READY;\n      \n      /* Process Unlocked */\n      __HAL_UNLOCK(hi2c_);\n      \n      return HAL_TIMEOUT;\n    }\n  }\n  return HAL_OK;\n}\n\n\n/**\n  * @brief  This function handles Acknowledge failed detection during an I2C Communication.\n  * @param  hi2c_ : Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @param  Timeout: Timeout duration\n  * @retval HAL status\n  */\nHAL_StatusTypeDef TwoWire::isAcknowledgeFailed(uint32_t Timeout)\n{\n  uint32_t tickstart = 0x00;\n  tickstart = HAL_GetTick();\n  \n  if(__HAL_I2C_GET_FLAG(hi2c_, I2C_FLAG_AF) == SET)\n  {\n    /* Wait until STOP Flag is reset */\n    /* AutoEnd should be initiate after AF */\n    while(__HAL_I2C_GET_FLAG(hi2c_, I2C_FLAG_STOPF) == RESET)\n    {\n      /* Check for the Timeout */\n      if(Timeout != HAL_MAX_DELAY)\n      {\n        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\n        {\n          hi2c_->State= HAL_I2C_STATE_READY;\n          /* Process Unlocked */\n          __HAL_UNLOCK(hi2c_);\n          return HAL_TIMEOUT;\n        }\n      }\n    }\n    \n    /* Clear NACKF Flag */\n    __HAL_I2C_CLEAR_FLAG(hi2c_, I2C_FLAG_AF);\n    \n    /* Clear STOP Flag */\n    __HAL_I2C_CLEAR_FLAG(hi2c_, I2C_FLAG_STOPF);\n    \n    /* Flush TX register if not empty */\n    if(__HAL_I2C_GET_FLAG(hi2c_, I2C_FLAG_TXE) == RESET)\n    {\n      __HAL_I2C_CLEAR_FLAG(hi2c_, I2C_FLAG_TXE);\n    }\n    \n    /* Clear Configuration Register 2 */\n    I2C_RESET_CR2(hi2c_);\n    \n    hi2c_->ErrorCode = HAL_I2C_ERROR_AF;\n    hi2c_->State= HAL_I2C_STATE_READY;\n    \n    /* Process Unlocked */\n    __HAL_UNLOCK(hi2c_);\n    \n    return HAL_ERROR;\n  }\n  return HAL_OK;\n}\n\nvoid TwoWire::transferConfig(uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)\n{\n  uint32_t tmpreg = 0;\n  \n   /* Get the CR2 register value */\n  tmpreg = hi2c_->Instance->CR2;\n  \n  /* clear tmpreg specific bits */\n  tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));\n  \n  /* update tmpreg */\n  tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \\\n    (uint32_t)Mode | (uint32_t)Request);\n  \n  /* update CR2 register */\n  hi2c_->Instance->CR2 = tmpreg;  \n}  \n\n//=============================================================================\n// Set up IRQ handlers for the Wire objects...\n// Note: Should probably be in the HAL driver file, but this way only happens\n// if app includes wire. \n//=============================================================================\n#if 0\nvoid I2C1_EV_IRQHandler(void) {\n  HAL_I2C_EV_IRQHandler(&Wire.i2c_handle_);\n}\n\nvoid I2C2_EV_IRQHandler(void)  {\n  HAL_I2C_EV_IRQHandler(&Wire1.i2c_handle_);\n}\n\nvoid I2C1_ER_IRQHandler(void) {\n  HAL_I2C_ER_IRQHandler(&Wire.i2c_handle_);\n}\n\nvoid I2C2_ER_IRQHandler(void)  {\n  HAL_I2C_ER_IRQHandler(&Wire1.i2c_handle_);\n}\n#endif\n\n//=============================================================================\n// Define our hardware I2C objects\n//=============================================================================\n\nTwoWire Wire(&drv_i2c_handles[0]);\nTwoWire Wire1(&drv_i2c_handles[1]);\n\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Wire/Wire.h",
    "content": "/*\n  TwoWire.h - TWI/I2C library for Arduino & Wiring\n  Copyright (c) 2006 Nicholas Zambetti.  All right reserved.\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n  Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n\n  Modified 2012 by Todd Krein (todd@krein.org) to implement repeated starts\n*/\n\n/*\n * Arduino srl - www.arduino.org\n * 2016 Jun 9: Edited Francesco Alessi (alfran) - francesco@arduino.org\n */\n//#define USE_SLOW_SOFT_I2C_MASTER\n\n#ifndef TwoWire_h\n#define TwoWire_h\n\n#include \"variant.h\"\n#include <inttypes.h>\n#include \"Stream.h\"\n#ifdef USE_SLOW_SOFT_I2C_MASTER\n#include <SlowSoftI2CMaster.h>\n\n\nclass TwoWire : public Stream\n{\nprivate:\n  uint8_t rxBuffer[BUFFER_LENGTH];\n  uint8_t rxBufferIndex;\n  uint8_t rxBufferLength;\n  uint8_t transmitting;\n  uint8_t error;\n  SlowSoftI2CMaster *si2c;\npublic:\n  TwoWire(uint8_t sda, uint8_t scl);\n  void begin(void);\n  void begin(uint8_t sda_pin, uint8_t scl_pin);\n  void end(void);\n  void setClock(uint32_t frequency);\n  void beginTransmission(uint8_t address);\n  void beginTransmission(int address);\n  uint8_t endTransmission(uint8_t sendStop);\n  uint8_t endTransmission(void);\n  size_t write(uint8_t data);\n  size_t write(const uint8_t *data, size_t quantity);\n  uint8_t requestFrom(uint8_t address, uint8_t quantity,\n          uint32_t iaddress, uint8_t isize, uint8_t sendStop);\n  uint8_t requestFrom(uint8_t address, uint8_t quantity, uint8_t sendStop);\n  uint8_t requestFrom(int address, int quantity, int sendStop);\n  uint8_t requestFrom(uint8_t address, uint8_t quantity);\n  uint8_t requestFrom(int address, int quantity);\n  int available(void);\n  int read(void);\n  int peek(void);\n  void flush(void);\n  inline size_t write(unsigned long n) { return write((uint8_t)n); }\n  inline size_t write(long n) { return write((uint8_t)n); }\n  inline size_t write(unsigned int n) { return write((uint8_t)n); }\n  inline size_t write(int n) { return write((uint8_t)n); }\n  using Print::write;\n};\n\n#else  \n//=============================================================================\n// Lets try hardware I2C\n//=============================================================================\n// Some temporary DEBUG defines\n//#define WIRE_USE_DEBUG_IO_PINS  // If defined enables debug\n#define WIRE_DEBUG_RECEIVE_FROM 11\n#define WIRE_DEBUG_END_TRANSFER 9\n// Some default buffer length and timeouts \n#define BUFFER_LENGTH 32\n#define WIRE_TX_TIMEOUT 1000 // timeout in ms\n#define WIRE_RX_TIMEOUT 1000 // timeout in ms\n\n\n\n//=============================================================================\n// Define some external call backs and interrupt handlers\n//=============================================================================\nextern void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);\nextern void HAL_I2C_SlaveAddrCpltCallback(I2C_HandleTypeDef *hi2c);\nextern \"C\" void I2C1_EV_IRQHandler(void);\nextern \"C\" void I2C2_EV_IRQHandler(void);\nextern \"C\" void I2C1_ER_IRQHandler(void);\nextern \"C\" void I2C2_ER_IRQHandler(void);\n\n//=============================================================================\n// TwoWire class definition\n//=============================================================================\nclass TwoWire : public Stream\n{\n\npublic:\n  friend void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);\n  friend void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);\n  friend void HAL_I2C_SlaveAddrCpltCallback(I2C_HandleTypeDef *hi2c);\n  friend void I2C1_EV_IRQHandler(void);\n  friend void I2C2_EV_IRQHandler(void);\n  friend void I2C1_ER_IRQHandler(void);\n  friend void I2C2_ER_IRQHandler(void);\n\n  TwoWire(I2C_HandleTypeDef *hi2c);\n  void begin(void);\n  void begin(uint8_t address);\n  void begin(int address) {\n    begin((uint8_t)address);\n  }\n  void end(void);\n  void setClock(uint32_t frequency);\n  void beginTransmission(uint8_t address);\n  void beginTransmission(int address);\n  uint8_t endTransmission(uint8_t sendStop);\n  uint8_t endTransmission(void);\n  size_t write(uint8_t data);\n  size_t write(const uint8_t *data, size_t quantity);\n//  uint8_t requestFrom(uint8_t address, uint8_t quantity,\n//          uint32_t iaddress, uint8_t isize, uint8_t sendStop);\n  uint8_t requestFrom(uint8_t address, uint8_t quantity, uint8_t sendStop);\n  uint8_t requestFrom(int address, int quantity, int sendStop);\n  uint8_t requestFrom(uint8_t address, uint8_t quantity);\n  uint8_t requestFrom(int address, int quantity);\n  int available(void);\n  int read(void);\n  int peek(void);\n  void flush(void);\n  inline size_t write(unsigned long n) { return write((uint8_t)n); }\n  inline size_t write(long n) { return write((uint8_t)n); }\n  inline size_t write(unsigned int n) { return write((uint8_t)n); }\n  inline size_t write(int n) { return write((uint8_t)n); }\n  using Print::write;\n\n  void onReceive(void (*function)(int numBytes));\n  void onRequest(void (*function)(void));\n  // Process Client ISR Callbacks    \n  void processTXCallback(void);\n  void processRXCallback(void);  \n  void processAddrCallback(void);\n\n\nprivate:\n  // Helper functions brought over from HAL I2C code\n  HAL_StatusTypeDef waitOnTXISFlagUntilTimeout(uint32_t Timeout);\n  HAL_StatusTypeDef waitOnRXNEFlagUntilTimeout(uint32_t Timeout);\n  HAL_StatusTypeDef waitOnFlagUntilTimeout(uint32_t flag, uint32_t Timeout);\n  HAL_StatusTypeDef isAcknowledgeFailed(uint32_t Timeout);\n\n  void transferConfig(uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);\n\n  uint8_t rxBuffer[BUFFER_LENGTH];\n  uint8_t rxBufferIndex;\n  uint8_t rxBufferLength;\n\n  uint16_t device_address;\n  uint32_t frequency_;\n  uint8_t txBuffer[BUFFER_LENGTH];\n  uint8_t txBufferIndex;\n  uint8_t txBufferLength;\n  uint8_t transmitting;\n  uint8_t error;\n  uint8_t slave_mode;\n  uint8_t state_;                      // What state are we in 0=not active 1=begin() called\n  uint8_t sendStop_;                  // Last communications do sendStop?\n  I2C_HandleTypeDef *hi2c_;           // Handle to the hardware I2c...\n  void (*user_onRequest)(void);\n  void (*user_onReceive)(int);\n\n};\n\n#endif\n//=============================================================================\n// Define standard objects\n//=============================================================================\nextern TwoWire Wire;\nextern TwoWire Wire1;\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/Wire/keywords.txt",
    "content": "#######################################\n# Syntax Coloring Map for Wire(i2c)\n#######################################\n\n#######################################\n# Datatypes (KEYWORD1)\n#######################################\n\n#######################################\n# Methods and Functions (KEYWORD2)\n#######################################\nwriteOneByte\tKEYWORD2\nreadOneByte\tKEYWORD2\nbeginTransmission\tKEYWORD2\nendTransmission\tKEYWORD2\nrequestFrom\tKEYWORD2\nsend\tKEYWORD2\nreceive\tKEYWORD2\ni2c_start\tKEYWORD2\ni2c_get_ack\tKEYWORD2\ni2c_send_ack\tKEYWORD2\ni2c_send_nack\tKEYWORD2\ni2c_shift_in\tKEYWORD2\ni2c_shift_out\tKEYWORD2\n\n\n#######################################\n# Class (KEYWORD3)\n#######################################\nWire\tKEYWORD3\tWire_i2c\n\n\n#######################################\n# Constants (LITERAL1)\n#######################################\nWIRE_BUFSIZ\t\tLITERAL1\nSUCCESS\tLITERAL1\nENACKADDR\tLITERAL1\nENACKTRNS\tLITERAL1\nEOTHER\tLITERAL1\nSDA\tLITERAL1\nSCL\tLITERAL1\nI2C_WRITE\tLITERAL1\nI2C_READ\tLITERAL1\nI2C_DELAY\tLITERAL1\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/XPT2046/XPT2046.cpp",
    "content": "\r\n#include <XPT2046.h>\r\n\r\nvoid XPT::xpt2046_init(void)\r\n{\r\n\tuint16_t hwXpos, hwYpos;\r\n\t\t\r\n\t__XPT2046_CS_OUT();\r\n\t__XPT2046_CS_SET();\r\n\t__XPT2046_IRQ_IN();\r\n\r\n\txpt2046_read_xy(&hwXpos, &hwYpos);\r\n}\r\n\r\nvoid XPT::xpt2046_read_xy(uint16_t *phwXpos, uint16_t *phwYpos)\r\n{\r\n\t*phwXpos = xpt2046_read_average(0xD0);\r\n\t*phwYpos = xpt2046_read_average(0x90);\r\n}\r\n\r\n\r\n#define ERR_RANGE 50\r\nbool XPT::xpt2046_twice_read_xy(uint16_t *phwXpos, uint16_t *phwYpos)\r\n{\r\n\tuint16_t hwXpos1, hwYpos1, hwXpos2, hwYpos2;\r\n\r\n\txpt2046_read_xy(&hwXpos1, &hwYpos1);\r\n\txpt2046_read_xy(&hwXpos2, &hwYpos2);\r\n\r\n\tif (((hwXpos2 <= hwXpos1 && hwXpos1 < hwXpos2 + ERR_RANGE) || (hwXpos1 <= hwXpos2 && hwXpos2 < hwXpos1 + ERR_RANGE))\r\n\t&& ((hwYpos2 <= hwYpos1 && hwYpos1 < hwYpos2 + ERR_RANGE) || (hwYpos1 <= hwYpos2 && hwYpos2 < hwYpos1 + ERR_RANGE))) {\r\n\t\t*phwXpos = (hwXpos1 + hwXpos2) / 2;\r\n\t\t*phwYpos = (hwYpos1 + hwYpos2) / 2;\r\n\t\treturn true;\r\n\t}\r\n\r\n\treturn false;\r\n}\r\n\r\nXPT Xpt = XPT();\r\n\r\n\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/XPT2046/XPT2046.h",
    "content": "#ifndef __XPT2046_H\r\n#define __XPT2046_H\r\n\r\n#include <Arduino.h>\r\n#include <avr/pgmspace.h>\r\n#include <SPI.h>\r\n\r\n\r\n#define BIT(__N)  (uint8_t)(1 << (__N))\r\n\r\n\r\n#if  defined(__AVR_ATmega32U4__)\r\n\r\n#define __XPT2046_CS_OUT()      DDRD |= BIT(4)\r\n#define __XPT2046_CS_SET()      PORTD |=  BIT(4)\r\n#define __XPT2046_CS_CLR()      PORTD &=~ BIT(4)\r\n\r\n#define __XPT2046_IRQ_IN()      DDRD &=~ BIT(0);PORTD |=  BIT(0)\r\n#define __XPT2046_IRQ_READ()    (PIND & BIT(0))\r\n\r\n#define __XPT2046_WRITE_BYTE(__DATA)       SPI.transfer(__DATA)\r\n          \r\n#define __SD_CS_DISABLE()       DDRD |= BIT(6); PORTD |=  BIT(6)\r\n\r\n#define __XPT2046_CS_DISABLE()    DDRD |= 0x10; PORTD |=  0x10\r\n\r\n#elif defined(__AVR_ATmega328__)\r\n\r\n#define __XPT2046_CS_OUT()      DDRD |= BIT(4)\r\n#define __XPT2046_CS_SET()      PORTD |=  BIT(4)\r\n#define __XPT2046_CS_CLR()      PORTD &=~ BIT(4)\r\n\r\n#define __XPT2046_IRQ_IN()      DDRD &=~ BIT(3);PORTD |=  BIT(3)\r\n#define __XPT2046_IRQ_READ()    (PIND & BIT(3))\r\n\r\n#define __XPT2046_WRITE_BYTE(__DATA)       SPI.transfer(__DATA)\r\n          \r\n#define __SD_CS_DISABLE()       DDRD |= BIT(5); PORTD |=  BIT(5)\r\n\r\n#define __XPT2046_CS_DISABLE()    DDRD |= 0x10; PORTD |=  0x10\r\n\r\n#else\r\n\r\n#define TP_IRQ_PIN         3\r\n#define TP_CS_PIN          4\r\n#define SD_CS_PIN          5\r\n\r\n#define __XPT2046_CS_OUT()      pinMode(TP_CS_PIN, OUTPUT)\r\n#define __XPT2046_CS_SET()      digitalWrite(TP_CS_PIN, HIGH)\r\n#define __XPT2046_CS_CLR()      digitalWrite(TP_CS_PIN, LOW)\r\n\r\n#define __XPT2046_IRQ_IN()      do { \\\r\n                                    pinMode(TP_IRQ_PIN, INPUT); \\\r\n                                    digitalWrite(TP_IRQ_PIN, HIGH); \\\r\n                                } while (0)\r\n#define __XPT2046_IRQ_READ()    digitalRead(TP_IRQ_PIN)\r\n#define __XPT2046_WRITE_BYTE(__DATA)       SPI.transfer(__DATA)\r\n#define __SD_CS_DISABLE()       do { \\\r\n                                    pinMode(SD_CS_PIN, OUTPUT); \\\r\n                                    digitalWrite(SD_CS_PIN, HIGH); \\\r\n                                } while (0)\r\n#define __XPT2046_CS_DISABLE()  __XPT2046_CS_SET()\r\n\r\n#endif\r\n\r\n\r\n\r\n\r\n\r\n\r\nclass XPT\r\n{\r\n\r\npublic:\r\n    \r\n    inline uint8_t xpt2046_write_byte(uint8_t chData)\r\n    {\r\n        return __XPT2046_WRITE_BYTE(chData);\r\n    }\r\n\r\n    uint16_t xpt2046_read_ad_value(uint8_t chCmd)\r\n    {\r\n        uint16_t hwData = 0;\r\n    \r\n        __XPT2046_CS_CLR();\r\n        xpt2046_write_byte(chCmd);\r\n        hwData = xpt2046_write_byte(0x00);\r\n        hwData <<= 8;\r\n        hwData |= xpt2046_write_byte(0x00);\r\n        hwData >>= 4;\r\n       __XPT2046_CS_SET();\r\n        \r\n        return hwData;\r\n    }\r\n    \r\n#define READ_TIMES  5\r\n#define LOST_NUM    1\r\n    uint16_t xpt2046_read_average(uint8_t chCmd)\r\n    {\r\n        uint8_t i, j;\r\n        uint16_t hwbuffer[READ_TIMES], hwSum = 0, hwTemp;\r\n\r\n        for (i = 0; i < READ_TIMES; i ++) {\r\n            hwbuffer[i] = xpt2046_read_ad_value(chCmd);\r\n        }\r\n        for (i = 0; i < READ_TIMES - 1; i ++) {\r\n            for (j = i + 1; j < READ_TIMES; j ++) {\r\n                if (hwbuffer[i] > hwbuffer[j]) {\r\n                    hwTemp = hwbuffer[i];\r\n                    hwbuffer[i] = hwbuffer[j];\r\n                    hwbuffer[j] = hwTemp;\r\n                }\r\n            }\r\n        }\r\n        for (i = LOST_NUM; i < READ_TIMES - LOST_NUM; i ++) {\r\n            hwSum += hwbuffer[i];\r\n        }\r\n        hwTemp = hwSum / (READ_TIMES - 2 * LOST_NUM);\r\n\r\n        return hwTemp;\r\n    }\r\n    \r\n    void xpt2046_init(void);\r\n    void xpt2046_read_xy(uint16_t *phwXpos, uint16_t *phwYpos);\r\n    bool xpt2046_twice_read_xy(uint16_t *phwXpos, uint16_t *phwYpos);\r\n};\r\n\r\nextern uint8_t g_chXcmd, g_chYcmd;\r\nextern XPT Xpt;\r\n\r\n#endif\r\n\r\n\r\n\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_burger/turtlebot3_core/turtlebot3_burger.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#ifndef TURTLEBOT3_BURGER_H_\n#define TURTLEBOT3_BURGER_H_\n\n#define NAME                             \"Burger\"\n\n#define WHEEL_RADIUS                     0.033           // meter\n#define WHEEL_SEPARATION                 0.160           // meter (BURGER : 0.160, WAFFLE : 0.287)\n#define TURNING_RADIUS                   0.080           // meter (BURGER : 0.080, WAFFLE : 0.1435)\n#define ROBOT_RADIUS                     0.105           // meter (BURGER : 0.105, WAFFLE : 0.220)\n#define ENCODER_MIN                      -2147483648     // raw\n#define ENCODER_MAX                      2147483648      // raw\n\n#define MAX_LINEAR_VELOCITY              (WHEEL_RADIUS * 2 * 3.14159265359 * 61 / 60) // m/s  (BURGER : 61[rpm], WAFFLE : 77[rpm])\n#define MAX_ANGULAR_VELOCITY             (MAX_LINEAR_VELOCITY / TURNING_RADIUS)       // rad/s\n\n#define MIN_LINEAR_VELOCITY              -MAX_LINEAR_VELOCITY  \n#define MIN_ANGULAR_VELOCITY             -MAX_ANGULAR_VELOCITY \n\n#endif  //TURTLEBOT3_BURGER_H_"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_burger/turtlebot3_core/turtlebot3_core.ino",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho, Gilbert */\n\n#include \"turtlebot3_core_config.h\"\n\n/*******************************************************************************\n* Setup function\n*******************************************************************************/\nvoid setup()\n{\n  DEBUG_SERIAL.begin(57600);\n\n  // Initialize ROS node handle, advertise and subscribe the topics\n  nh.initNode();\n  nh.getHardware()->setBaud(115200);\n\n  nh.subscribe(cmd_vel_sub);\n  nh.subscribe(sound_sub);\n  nh.subscribe(motor_power_sub);\n  nh.subscribe(reset_sub);\n\n  nh.advertise(sensor_state_pub);  \n  nh.advertise(version_info_pub);\n  nh.advertise(imu_pub);\n  nh.advertise(cmd_vel_rc100_pub);\n  nh.advertise(odom_pub);\n  nh.advertise(joint_states_pub);\n  nh.advertise(battery_state_pub);\n  nh.advertise(mag_pub);\n\n  tf_broadcaster.init(nh);\n\n  // Setting for Dynamixel motors\n  motor_driver.init(NAME);\n\n  // Setting for IMU\n  sensors.init();\n\n  // Init diagnosis\n  diagnosis.init();\n\n  // Setting for ROBOTIS RC100 remote controller and cmd_vel\n  controllers.init(MAX_LINEAR_VELOCITY, MAX_ANGULAR_VELOCITY);\n\n  // Setting for SLAM and navigation (odometry, joint states, TF)\n  initOdom();\n\n  initJointStates();\n\n  prev_update_time = millis();\n\n  pinMode(LED_WORKING_CHECK, OUTPUT);\n\n  setup_end = true;\n}\n\n/*******************************************************************************\n* Loop function\n*******************************************************************************/\nvoid loop()\n{\n  uint32_t t = millis();\n  updateTime();\n  updateVariable(nh.connected());\n  updateTFPrefix(nh.connected());\n\n  if ((t-tTime[0]) >= (1000 / CONTROL_MOTOR_SPEED_FREQUENCY))\n  {\n    updateGoalVelocity();\n    if ((t-tTime[6]) > CONTROL_MOTOR_TIMEOUT) \n    {\n      motor_driver.controlMotor(WHEEL_RADIUS, WHEEL_SEPARATION, zero_velocity);\n    } \n    else {\n      motor_driver.controlMotor(WHEEL_RADIUS, WHEEL_SEPARATION, goal_velocity);\n    }\n    tTime[0] = t;\n  }\n\n  if ((t-tTime[1]) >= (1000 / CMD_VEL_PUBLISH_FREQUENCY))\n  {\n    publishCmdVelFromRC100Msg();\n    tTime[1] = t;\n  }\n\n  if ((t-tTime[2]) >= (1000 / DRIVE_INFORMATION_PUBLISH_FREQUENCY))\n  {\n    publishSensorStateMsg();\n    publishBatteryStateMsg();\n    publishDriveInformation();\n    tTime[2] = t;\n  }\n\n  if ((t-tTime[3]) >= (1000 / IMU_PUBLISH_FREQUENCY))\n  {\n    publishImuMsg();\n    publishMagMsg();\n    tTime[3] = t;\n  }\n\n  if ((t-tTime[4]) >= (1000 / VERSION_INFORMATION_PUBLISH_FREQUENCY))\n  {\n    publishVersionInfoMsg();\n    tTime[4] = t;\n  }\n\n#ifdef DEBUG\n  if ((t-tTime[5]) >= (1000 / DEBUG_LOG_FREQUENCY))\n  {\n    sendDebuglog();\n    tTime[5] = t;\n  }\n#endif\n\n  // Send log message after ROS connection\n  sendLogMsg();\n\n  // Receive data from RC100 \n  bool clicked_state = controllers.getRCdata(goal_velocity_from_rc100);\n  if (clicked_state == true)  \n    tTime[6] = millis();\n\n  // Check push button pressed for simple test drive\n  driveTest(diagnosis.getButtonPress(3000));\n\n  // Update the IMU unit\n  sensors.updateIMU();\n\n  // TODO\n  // Update sonar data\n  // sensors.updateSonar(t);\n\n  // Start Gyro Calibration after ROS connection\n  updateGyroCali(nh.connected());\n\n  // Show LED status\n  diagnosis.showLedStatus(nh.connected());\n\n  // Update Voltage\n  battery_state = diagnosis.updateVoltageCheck(setup_end);\n\n  // Call all the callbacks waiting to be called at that point in time\n  nh.spinOnce();\n\n  // Wait the serial link time to process\n  waitForSerialLink(nh.connected());\n}\n\n/*******************************************************************************\n* Callback function for cmd_vel msg\n*******************************************************************************/\nvoid commandVelocityCallback(const geometry_msgs::Twist& cmd_vel_msg)\n{\n  goal_velocity_from_cmd[LINEAR]  = cmd_vel_msg.linear.x;\n  goal_velocity_from_cmd[ANGULAR] = cmd_vel_msg.angular.z;\n\n  goal_velocity_from_cmd[LINEAR]  = constrain(goal_velocity_from_cmd[LINEAR],  MIN_LINEAR_VELOCITY, MAX_LINEAR_VELOCITY);\n  goal_velocity_from_cmd[ANGULAR] = constrain(goal_velocity_from_cmd[ANGULAR], MIN_ANGULAR_VELOCITY, MAX_ANGULAR_VELOCITY);\n  tTime[6] = millis();\n}\n\n/*******************************************************************************\n* Callback function for sound msg\n*******************************************************************************/\nvoid soundCallback(const turtlebot3_msgs::Sound& sound_msg)\n{\n  sensors.makeSound(sound_msg.value);\n}\n\n/*******************************************************************************\n* Callback function for motor_power msg\n*******************************************************************************/\nvoid motorPowerCallback(const std_msgs::Bool& power_msg)\n{\n  bool dxl_power = power_msg.data;\n\n  motor_driver.setTorque(dxl_power);\n}\n\n/*******************************************************************************\n* Callback function for reset msg\n*******************************************************************************/\nvoid resetCallback(const std_msgs::Empty& reset_msg)\n{ \n  char log_msg[50];\n\n  (void)(reset_msg);\n\n  sprintf(log_msg, \"Start Calibration of Gyro\");\n  nh.loginfo(log_msg);\n\n  sensors.calibrationGyro();\n\n  sprintf(log_msg, \"Calibration End\");\n  nh.loginfo(log_msg);\n\n  initOdom();\n\n  sprintf(log_msg, \"Reset Odometry\");\n  nh.loginfo(log_msg);  \n}\n\n/*******************************************************************************\n* Publish msgs (CMD Velocity data from RC100 : angular velocity, linear velocity)\n*******************************************************************************/\nvoid publishCmdVelFromRC100Msg(void)\n{\n  cmd_vel_rc100_msg.linear.x  = goal_velocity_from_rc100[LINEAR];\n  cmd_vel_rc100_msg.angular.z = goal_velocity_from_rc100[ANGULAR];\n\n  cmd_vel_rc100_pub.publish(&cmd_vel_rc100_msg);\n}\n\n/*******************************************************************************\n* Publish msgs (IMU data: angular velocity, linear acceleration, orientation)\n*******************************************************************************/\nvoid publishImuMsg(void)\n{\n  imu_msg = sensors.getIMU();\n\n  imu_msg.header.stamp    = rosNow();\n  imu_msg.header.frame_id = imu_frame_id;\n\n  imu_pub.publish(&imu_msg);\n}\n\n/*******************************************************************************\n* Publish msgs (Magnetic data)\n*******************************************************************************/\nvoid publishMagMsg(void)\n{\n  mag_msg = sensors.getMag();\n\n  mag_msg.header.stamp    = rosNow();\n  mag_msg.header.frame_id = mag_frame_id;\n\n  mag_pub.publish(&mag_msg);\n}\n\n/*******************************************************************************\n* Publish msgs (sensor_state: bumpers, cliffs, buttons, encoders, battery)\n*******************************************************************************/\nvoid publishSensorStateMsg(void)\n{\n  bool dxl_comm_result = false;\n\n  sensor_state_msg.header.stamp = rosNow();\n  sensor_state_msg.battery = sensors.checkVoltage();\n\n  dxl_comm_result = motor_driver.readEncoder(sensor_state_msg.left_encoder, sensor_state_msg.right_encoder);\n\n  if (dxl_comm_result == true)\n    updateMotorInfo(sensor_state_msg.left_encoder, sensor_state_msg.right_encoder);\n  else\n    return;\n\n  sensor_state_msg.bumper = sensors.checkPushBumper();\n\n  sensor_state_msg.cliff = sensors.getIRsensorData();\n\n  // TODO\n  // sensor_state_msg.sonar = sensors.getSonarData();\n\n  sensor_state_msg.illumination = sensors.getIlluminationData();\n  \n  sensor_state_msg.button = sensors.checkPushButton();\n\n  sensor_state_msg.torque = motor_driver.getTorque();\n\n  sensor_state_pub.publish(&sensor_state_msg);\n}\n\n/*******************************************************************************\n* Publish msgs (version info)\n*******************************************************************************/\nvoid publishVersionInfoMsg(void)\n{\n  version_info_msg.hardware = \"0.0.0\";\n  version_info_msg.software = \"0.0.0\";\n  version_info_msg.firmware = FIRMWARE_VER;\n\n  version_info_pub.publish(&version_info_msg);\n}\n\n/*******************************************************************************\n* Publish msgs (battery_state)\n*******************************************************************************/\nvoid publishBatteryStateMsg(void)\n{\n  battery_state_msg.header.stamp = rosNow();\n  battery_state_msg.design_capacity = 1.8f; //Ah\n  battery_state_msg.voltage = sensors.checkVoltage();\n  battery_state_msg.percentage = (float)(battery_state_msg.voltage / 11.1f);\n\n  if (battery_state == 0)\n    battery_state_msg.present = false;\n  else\n    battery_state_msg.present = true;  \n\n  battery_state_pub.publish(&battery_state_msg);\n}\n\n/*******************************************************************************\n* Publish msgs (odometry, joint states, tf)\n*******************************************************************************/\nvoid publishDriveInformation(void)\n{\n  unsigned long time_now = millis();\n  unsigned long step_time = time_now - prev_update_time;\n\n  prev_update_time = time_now;\n  ros::Time stamp_now = rosNow();\n\n  // calculate odometry\n  calcOdometry((double)(step_time * 0.001));\n\n  // odometry\n  updateOdometry();\n  odom.header.stamp = stamp_now;\n  odom_pub.publish(&odom);\n\n  // odometry tf\n  updateTF(odom_tf);\n  odom_tf.header.stamp = stamp_now;\n  tf_broadcaster.sendTransform(odom_tf);\n\n  // joint states\n  updateJointStates();\n  joint_states.header.stamp = stamp_now;\n  joint_states_pub.publish(&joint_states);\n}\n\n/*******************************************************************************\n* Update TF Prefix\n*******************************************************************************/\nvoid updateTFPrefix(bool isConnected)\n{\n  static bool isChecked = false;\n  char log_msg[50];\n\n  if (isConnected)\n  {\n    if (isChecked == false)\n    {\n      nh.getParam(\"~tf_prefix\", &get_tf_prefix);\n\n      if (!strcmp(get_tf_prefix, \"\"))\n      {\n        sprintf(odom_header_frame_id, \"odom\");\n        sprintf(odom_child_frame_id, \"base_footprint\");  \n\n        sprintf(imu_frame_id, \"imu_link\");\n        sprintf(mag_frame_id, \"mag_link\");\n        sprintf(joint_state_header_frame_id, \"base_link\");\n      }\n      else\n      {\n        strcpy(odom_header_frame_id, get_tf_prefix);\n        strcpy(odom_child_frame_id, get_tf_prefix);\n\n        strcpy(imu_frame_id, get_tf_prefix);\n        strcpy(mag_frame_id, get_tf_prefix);\n        strcpy(joint_state_header_frame_id, get_tf_prefix);\n\n        strcat(odom_header_frame_id, \"/odom\");\n        strcat(odom_child_frame_id, \"/base_footprint\");\n\n        strcat(imu_frame_id, \"/imu_link\");\n        strcat(mag_frame_id, \"/mag_link\");\n        strcat(joint_state_header_frame_id, \"/base_link\");\n      }\n\n      sprintf(log_msg, \"Setup TF on Odometry [%s]\", odom_header_frame_id);\n      nh.loginfo(log_msg); \n\n      sprintf(log_msg, \"Setup TF on IMU [%s]\", imu_frame_id);\n      nh.loginfo(log_msg); \n\n      sprintf(log_msg, \"Setup TF on MagneticField [%s]\", mag_frame_id);\n      nh.loginfo(log_msg); \n\n      sprintf(log_msg, \"Setup TF on JointState [%s]\", joint_state_header_frame_id);\n      nh.loginfo(log_msg); \n\n      isChecked = true;\n    }\n  }\n  else\n  {\n    isChecked = false;\n  }\n}\n\n/*******************************************************************************\n* Update the odometry\n*******************************************************************************/\nvoid updateOdometry(void)\n{\n  odom.header.frame_id = odom_header_frame_id;\n  odom.child_frame_id  = odom_child_frame_id;\n\n  odom.pose.pose.position.x = odom_pose[0];\n  odom.pose.pose.position.y = odom_pose[1];\n  odom.pose.pose.position.z = 0;\n  odom.pose.pose.orientation = tf::createQuaternionFromYaw(odom_pose[2]);\n\n  odom.twist.twist.linear.x  = odom_vel[0];\n  odom.twist.twist.angular.z = odom_vel[2];\n}\n\n/*******************************************************************************\n* Update the joint states \n*******************************************************************************/\nvoid updateJointStates(void)\n{\n  static float joint_states_pos[WHEEL_NUM] = {0.0, 0.0};\n  static float joint_states_vel[WHEEL_NUM] = {0.0, 0.0};\n  //static float joint_states_eff[WHEEL_NUM] = {0.0, 0.0};\n\n  joint_states_pos[LEFT]  = last_rad[LEFT];\n  joint_states_pos[RIGHT] = last_rad[RIGHT];\n\n  joint_states_vel[LEFT]  = last_velocity[LEFT];\n  joint_states_vel[RIGHT] = last_velocity[RIGHT];\n\n  joint_states.position = joint_states_pos;\n  joint_states.velocity = joint_states_vel;\n}\n\n/*******************************************************************************\n* CalcUpdateulate the TF\n*******************************************************************************/\nvoid updateTF(geometry_msgs::TransformStamped& odom_tf)\n{\n  odom_tf.header = odom.header;\n  odom_tf.child_frame_id = odom.child_frame_id;\n  odom_tf.transform.translation.x = odom.pose.pose.position.x;\n  odom_tf.transform.translation.y = odom.pose.pose.position.y;\n  odom_tf.transform.translation.z = odom.pose.pose.position.z;\n  odom_tf.transform.rotation      = odom.pose.pose.orientation;\n}\n\n/*******************************************************************************\n* Update motor information\n*******************************************************************************/\nvoid updateMotorInfo(int32_t left_tick, int32_t right_tick)\n{\n  int32_t current_tick = 0;\n  static int32_t last_tick[WHEEL_NUM] = {0, 0};\n  \n  if (init_encoder)\n  {\n    for (int index = 0; index < WHEEL_NUM; index++)\n    {\n      last_diff_tick[index] = 0;\n      last_tick[index]      = 0;\n      last_rad[index]       = 0.0;\n\n      last_velocity[index]  = 0.0;\n    }  \n\n    last_tick[LEFT] = left_tick;\n    last_tick[RIGHT] = right_tick;\n\n    init_encoder = false;\n    return;\n  }\n\n  current_tick = left_tick;\n\n  last_diff_tick[LEFT] = current_tick - last_tick[LEFT];\n  last_tick[LEFT]      = current_tick;\n  last_rad[LEFT]       += TICK2RAD * (double)last_diff_tick[LEFT];\n\n  current_tick = right_tick;\n\n  last_diff_tick[RIGHT] = current_tick - last_tick[RIGHT];\n  last_tick[RIGHT]      = current_tick;\n  last_rad[RIGHT]       += TICK2RAD * (double)last_diff_tick[RIGHT];\n}\n\n/*******************************************************************************\n* Calculate the odometry\n*******************************************************************************/\nbool calcOdometry(double diff_time)\n{\n  float* orientation;\n  double wheel_l, wheel_r;      // rotation value of wheel [rad]\n  double delta_s, theta, delta_theta;\n  static double last_theta = 0.0;\n  double v, w;                  // v = translational velocity [m/s], w = rotational velocity [rad/s]\n  double step_time;\n\n  wheel_l = wheel_r = 0.0;\n  delta_s = delta_theta = theta = 0.0;\n  v = w = 0.0;\n  step_time = 0.0;\n\n  step_time = diff_time;\n\n  if (step_time == 0)\n    return false;\n\n  wheel_l = TICK2RAD * (double)last_diff_tick[LEFT];\n  wheel_r = TICK2RAD * (double)last_diff_tick[RIGHT];\n\n  if (isnan(wheel_l))\n    wheel_l = 0.0;\n\n  if (isnan(wheel_r))\n    wheel_r = 0.0;\n\n  delta_s     = WHEEL_RADIUS * (wheel_r + wheel_l) / 2.0;\n  // theta = WHEEL_RADIUS * (wheel_r - wheel_l) / WHEEL_SEPARATION;  \n  orientation = sensors.getOrientation();\n  theta       = atan2f(orientation[1]*orientation[2] + orientation[0]*orientation[3], \n                0.5f - orientation[2]*orientation[2] - orientation[3]*orientation[3]);\n\n  delta_theta = theta - last_theta;\n\n  // compute odometric pose\n  odom_pose[0] += delta_s * cos(odom_pose[2] + (delta_theta / 2.0));\n  odom_pose[1] += delta_s * sin(odom_pose[2] + (delta_theta / 2.0));\n  odom_pose[2] += delta_theta;\n\n  // compute odometric instantaneouse velocity\n\n  v = delta_s / step_time;\n  w = delta_theta / step_time;\n\n  odom_vel[0] = v;\n  odom_vel[1] = 0.0;\n  odom_vel[2] = w;\n\n  last_velocity[LEFT]  = wheel_l / step_time;\n  last_velocity[RIGHT] = wheel_r / step_time;\n  last_theta = theta;\n\n  return true;\n}\n\n/*******************************************************************************\n* Turtlebot3 test drive using push buttons\n*******************************************************************************/\nvoid driveTest(uint8_t buttons)\n{\n  static bool move[2] = {false, false};\n  static int32_t saved_tick[2] = {0, 0};\n  static double diff_encoder = 0.0;\n\n  int32_t current_tick[2] = {0, 0};\n\n  motor_driver.readEncoder(current_tick[LEFT], current_tick[RIGHT]);\n\n  if (buttons & (1<<0))  \n  {\n    move[LINEAR] = true;\n    saved_tick[RIGHT] = current_tick[RIGHT];\n\n    diff_encoder = TEST_DISTANCE / (0.207 / 4096); // (Circumference of Wheel) / (The number of tick per revolution)\n    tTime[6] = millis();\n  }\n  else if (buttons & (1<<1))\n  {\n    move[ANGULAR] = true;\n    saved_tick[RIGHT] = current_tick[RIGHT];\n\n    diff_encoder = (TEST_RADIAN * TURNING_RADIUS) / (0.207 / 4096);\n    tTime[6] = millis();\n  }\n\n  if (move[LINEAR])\n  {    \n    if (abs(saved_tick[RIGHT] - current_tick[RIGHT]) <= diff_encoder)\n    {\n      goal_velocity_from_button[LINEAR]  = 0.05;\n      tTime[6] = millis();\n    }\n    else\n    {\n      goal_velocity_from_button[LINEAR]  = 0.0;\n      move[LINEAR] = false;\n    }\n  }\n  else if (move[ANGULAR])\n  {   \n    if (abs(saved_tick[RIGHT] - current_tick[RIGHT]) <= diff_encoder)\n    {\n      goal_velocity_from_button[ANGULAR]= -0.7;\n      tTime[6] = millis();\n    }\n    else\n    {\n      goal_velocity_from_button[ANGULAR]  = 0.0;\n      move[ANGULAR] = false;\n    }\n  }\n}\n\n/*******************************************************************************\n* Update variable (initialization)\n*******************************************************************************/\nvoid updateVariable(bool isConnected)\n{\n  static bool variable_flag = false;\n  \n  if (isConnected)\n  {\n    if (variable_flag == false)\n    {      \n      sensors.initIMU();\n      initOdom();\n\n      variable_flag = true;\n    }\n  }\n  else\n  {\n    variable_flag = false;\n  }\n}\n\n/*******************************************************************************\n* Wait for Serial Link\n*******************************************************************************/\nvoid waitForSerialLink(bool isConnected)\n{\n  static bool wait_flag = false;\n  \n  if (isConnected)\n  {\n    if (wait_flag == false)\n    {      \n      delay(10);\n\n      wait_flag = true;\n    }\n  }\n  else\n  {\n    wait_flag = false;\n  }\n}\n\n/*******************************************************************************\n* Update the base time for interpolation\n*******************************************************************************/\nvoid updateTime()\n{\n  current_offset = millis();\n  current_time = nh.now();\n}\n\n/*******************************************************************************\n* ros::Time::now() implementation\n*******************************************************************************/\nros::Time rosNow()\n{\n  return nh.now();\n}\n\n/*******************************************************************************\n* Time Interpolation function (deprecated)\n*******************************************************************************/\nros::Time addMicros(ros::Time & t, uint32_t _micros)\n{\n  uint32_t sec, nsec;\n\n  sec  = _micros / 1000 + t.sec;\n  nsec = _micros % 1000000000 + t.nsec;\n\n  return ros::Time(sec, nsec);\n}\n\n/*******************************************************************************\n* Start Gyro Calibration\n*******************************************************************************/\nvoid updateGyroCali(bool isConnected)\n{\n  static bool isEnded = false;\n  char log_msg[50];\n\n  (void)(isConnected);\n\n  if (nh.connected())\n  {\n    if (isEnded == false)\n    {\n      sprintf(log_msg, \"Start Calibration of Gyro\");\n      nh.loginfo(log_msg);\n\n      sensors.calibrationGyro();\n\n      sprintf(log_msg, \"Calibration End\");\n      nh.loginfo(log_msg);\n\n      isEnded = true;\n    }\n  }\n  else\n  {\n    isEnded = false;\n  }\n}\n\n/*******************************************************************************\n* Send log message\n*******************************************************************************/\nvoid sendLogMsg(void)\n{\n  static bool log_flag = false;\n  char log_msg[100];  \n\n  String name             = NAME;\n  String firmware_version = FIRMWARE_VER;\n  String bringup_log      = \"This core(v\" + firmware_version + \") is compatible with TB3 \" + name;\n   \n  const char* init_log_data = bringup_log.c_str();\n\n  if (nh.connected())\n  {\n    if (log_flag == false)\n    {      \n      sprintf(log_msg, \"--------------------------\");\n      nh.loginfo(log_msg);\n\n      sprintf(log_msg, \"Connected to OpenCR board!\");\n      nh.loginfo(log_msg);\n\n      sprintf(log_msg, init_log_data);\n      nh.loginfo(log_msg);\n\n      sprintf(log_msg, \"--------------------------\");\n      nh.loginfo(log_msg);\n\n      log_flag = true;\n    }\n  }\n  else\n  {\n    log_flag = false;\n  }\n}\n\n/*******************************************************************************\n* Initialization odometry data\n*******************************************************************************/\nvoid initOdom(void)\n{\n  init_encoder = true;\n\n  for (int index = 0; index < 3; index++)\n  {\n    odom_pose[index] = 0.0;\n    odom_vel[index]  = 0.0;\n  }\n\n  odom.pose.pose.position.x = 0.0;\n  odom.pose.pose.position.y = 0.0;\n  odom.pose.pose.position.z = 0.0;\n\n  odom.pose.pose.orientation.x = 0.0;\n  odom.pose.pose.orientation.y = 0.0;\n  odom.pose.pose.orientation.z = 0.0;\n  odom.pose.pose.orientation.w = 0.0;\n\n  odom.twist.twist.linear.x  = 0.0;\n  odom.twist.twist.angular.z = 0.0;\n}\n\n/*******************************************************************************\n* Initialization joint states data\n*******************************************************************************/\nvoid initJointStates(void)\n{\n  static char *joint_states_name[] = {(char*)\"wheel_left_joint\", (char*)\"wheel_right_joint\"};\n\n  joint_states.header.frame_id = joint_state_header_frame_id;\n  joint_states.name            = joint_states_name;\n\n  joint_states.name_length     = WHEEL_NUM;\n  joint_states.position_length = WHEEL_NUM;\n  joint_states.velocity_length = WHEEL_NUM;\n  joint_states.effort_length   = WHEEL_NUM;\n}\n\n/*******************************************************************************\n* Update Goal Velocity\n*******************************************************************************/\nvoid updateGoalVelocity(void)\n{\n  goal_velocity[LINEAR]  = goal_velocity_from_button[LINEAR]  + goal_velocity_from_cmd[LINEAR]  + goal_velocity_from_rc100[LINEAR];\n  goal_velocity[ANGULAR] = goal_velocity_from_button[ANGULAR] + goal_velocity_from_cmd[ANGULAR] + goal_velocity_from_rc100[ANGULAR];\n\n  sensors.setLedPattern(goal_velocity[LINEAR], goal_velocity[ANGULAR]);\n}\n\n/*******************************************************************************\n* Send Debug data\n*******************************************************************************/\nvoid sendDebuglog(void)\n{\n  DEBUG_SERIAL.println(\"---------------------------------------\");\n  DEBUG_SERIAL.println(\"EXTERNAL SENSORS\");\n  DEBUG_SERIAL.println(\"---------------------------------------\");\n  DEBUG_SERIAL.print(\"Bumper : \"); DEBUG_SERIAL.println(sensors.checkPushBumper());\n  DEBUG_SERIAL.print(\"Cliff : \"); DEBUG_SERIAL.println(sensors.getIRsensorData());\n  DEBUG_SERIAL.print(\"Sonar : \"); DEBUG_SERIAL.println(sensors.getSonarData());\n  DEBUG_SERIAL.print(\"Illumination : \"); DEBUG_SERIAL.println(sensors.getIlluminationData());\n\n  DEBUG_SERIAL.println(\"---------------------------------------\");\n  DEBUG_SERIAL.println(\"OpenCR SENSORS\");\n  DEBUG_SERIAL.println(\"---------------------------------------\");\n  DEBUG_SERIAL.print(\"Battery : \"); DEBUG_SERIAL.println(sensors.checkVoltage());\n  DEBUG_SERIAL.println(\"Button : \" + String(sensors.checkPushButton()));\n\n  float* quat = sensors.getOrientation();\n\n  DEBUG_SERIAL.println(\"IMU : \");\n  DEBUG_SERIAL.print(\"    w : \"); DEBUG_SERIAL.println(quat[0]);\n  DEBUG_SERIAL.print(\"    x : \"); DEBUG_SERIAL.println(quat[1]);\n  DEBUG_SERIAL.print(\"    y : \"); DEBUG_SERIAL.println(quat[2]);\n  DEBUG_SERIAL.print(\"    z : \"); DEBUG_SERIAL.println(quat[3]);\n  \n  DEBUG_SERIAL.println(\"---------------------------------------\");\n  DEBUG_SERIAL.println(\"DYNAMIXELS\");\n  DEBUG_SERIAL.println(\"---------------------------------------\");\n  DEBUG_SERIAL.println(\"Torque : \" + String(motor_driver.getTorque()));\n\n  int32_t encoder[WHEEL_NUM] = {0, 0};\n  motor_driver.readEncoder(encoder[LEFT], encoder[RIGHT]);\n  \n  DEBUG_SERIAL.println(\"Encoder(left) : \" + String(encoder[LEFT]));\n  DEBUG_SERIAL.println(\"Encoder(right) : \" + String(encoder[RIGHT]));\n\n  DEBUG_SERIAL.println(\"---------------------------------------\");\n  DEBUG_SERIAL.println(\"TurtleBot3\");\n  DEBUG_SERIAL.println(\"---------------------------------------\");\n  DEBUG_SERIAL.println(\"Odometry : \");   \n  DEBUG_SERIAL.print(\"         x : \"); DEBUG_SERIAL.println(odom_pose[0]);\n  DEBUG_SERIAL.print(\"         y : \"); DEBUG_SERIAL.println(odom_pose[1]);\n  DEBUG_SERIAL.print(\"     theta : \"); DEBUG_SERIAL.println(odom_pose[2]);\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_burger/turtlebot3_core/turtlebot3_core_config.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho, Gilbert */\n\n#ifndef TURTLEBOT3_CORE_CONFIG_H_\n#define TURTLEBOT3_CORE_CONFIG_H_\n// #define NOETIC_SUPPORT          //uncomment this if writing code for ROS1 Noetic\n\n#include <ros.h>\n#include <ros/time.h>\n#include <std_msgs/Bool.h>\n#include <std_msgs/Empty.h>\n#include <std_msgs/Int32.h>\n#include <sensor_msgs/JointState.h>\n#include <geometry_msgs/Vector3.h>\n#include <tf/tf.h>\n#include <tf/transform_broadcaster.h>\n#include <nav_msgs/Odometry.h>\n\n#include <turtlebot3_msgs/SensorState.h>\n#include <turtlebot3_msgs/Sound.h>\n#include <turtlebot3_msgs/VersionInfo.h>\n\n#include <TurtleBot3.h>\n#include \"turtlebot3_burger.h\"\n\n#include <math.h>\n\n#define FIRMWARE_VER \"1.2.6\"\n\n#define CONTROL_MOTOR_SPEED_FREQUENCY          30   //hz\n#define CONTROL_MOTOR_TIMEOUT                  500  //ms\n#define IMU_PUBLISH_FREQUENCY                  200  //hz\n#define CMD_VEL_PUBLISH_FREQUENCY              30   //hz\n#define DRIVE_INFORMATION_PUBLISH_FREQUENCY    30   //hz\n#define VERSION_INFORMATION_PUBLISH_FREQUENCY  1    //hz \n#define DEBUG_LOG_FREQUENCY                    10   //hz \n\n#define WHEEL_NUM                        2\n\n#define LEFT                             0\n#define RIGHT                            1\n\n#define LINEAR                           0\n#define ANGULAR                          1\n\n#define DEG2RAD(x)                       (x * 0.01745329252)  // *PI/180\n#define RAD2DEG(x)                       (x * 57.2957795131)  // *180/PI\n\n#define TICK2RAD                         0.001533981  // 0.087890625[deg] * 3.14159265359 / 180 = 0.001533981f\n\n#define TEST_DISTANCE                    0.300     // meter\n#define TEST_RADIAN                      3.14      // 180 degree\n\n// #define DEBUG                            \n#define DEBUG_SERIAL                     SerialBT2\n\n// Callback function prototypes\nvoid commandVelocityCallback(const geometry_msgs::Twist& cmd_vel_msg);\nvoid soundCallback(const turtlebot3_msgs::Sound& sound_msg);\nvoid motorPowerCallback(const std_msgs::Bool& power_msg);\nvoid resetCallback(const std_msgs::Empty& reset_msg);\n\n// Function prototypes\nvoid publishCmdVelFromRC100Msg(void);\nvoid publishImuMsg(void);\nvoid publishMagMsg(void);\nvoid publishSensorStateMsg(void);\nvoid publishVersionInfoMsg(void);\nvoid publishBatteryStateMsg(void);\nvoid publishDriveInformation(void);\n\nros::Time rosNow(void);\nros::Time addMicros(ros::Time & t, uint32_t _micros); // deprecated\n\nvoid updateVariable(bool isConnected);\nvoid updateMotorInfo(int32_t left_tick, int32_t right_tick);\nvoid updateTime(void);\nvoid updateOdometry(void);\nvoid updateJoint(void);\nvoid updateTF(geometry_msgs::TransformStamped& odom_tf);\nvoid updateGyroCali(bool isConnected);\nvoid updateGoalVelocity(void);\nvoid updateTFPrefix(bool isConnected);\n\nvoid initOdom(void);\nvoid initJointStates(void);\n\nbool calcOdometry(double diff_time);\n\nvoid sendLogMsg(void);\nvoid waitForSerialLink(bool isConnected);\n\n/*******************************************************************************\n* ROS NodeHandle\n*******************************************************************************/\nros::NodeHandle nh;\nros::Time current_time;\nuint32_t current_offset;\n\n/*******************************************************************************\n* ROS Parameter\n*******************************************************************************/\nchar get_prefix[10];\nchar* get_tf_prefix = get_prefix;\n\nchar odom_header_frame_id[30];\nchar odom_child_frame_id[30];\n\nchar imu_frame_id[30];\nchar mag_frame_id[30];\n\nchar joint_state_header_frame_id[30];\n\n/*******************************************************************************\n* Subscriber\n*******************************************************************************/\nros::Subscriber<geometry_msgs::Twist> cmd_vel_sub(\"cmd_vel\", commandVelocityCallback);\n\nros::Subscriber<turtlebot3_msgs::Sound> sound_sub(\"sound\", soundCallback);\n\nros::Subscriber<std_msgs::Bool> motor_power_sub(\"motor_power\", motorPowerCallback);\n\nros::Subscriber<std_msgs::Empty> reset_sub(\"reset\", resetCallback);\n\n/*******************************************************************************\n* Publisher\n*******************************************************************************/\n// Bumpers, cliffs, buttons, encoders, battery of Turtlebot3\nturtlebot3_msgs::SensorState sensor_state_msg;\nros::Publisher sensor_state_pub(\"sensor_state\", &sensor_state_msg);\n\n// Version information of Turtlebot3\nturtlebot3_msgs::VersionInfo version_info_msg;\nros::Publisher version_info_pub(\"firmware_version\", &version_info_msg);\n\n// IMU of Turtlebot3\nsensor_msgs::Imu imu_msg;\nros::Publisher imu_pub(\"imu\", &imu_msg);\n\n// Command velocity of Turtlebot3 using RC100 remote controller\ngeometry_msgs::Twist cmd_vel_rc100_msg;\nros::Publisher cmd_vel_rc100_pub(\"cmd_vel_rc100\", &cmd_vel_rc100_msg);\n\n// Odometry of Turtlebot3\nnav_msgs::Odometry odom;\nros::Publisher odom_pub(\"odom\", &odom);\n\n// Joint(Dynamixel) state of Turtlebot3\nsensor_msgs::JointState joint_states;\nros::Publisher joint_states_pub(\"joint_states\", &joint_states);\n\n// Battey state of Turtlebot3\n#if defined NOETIC_SUPPORT\nsensor_msgs::BatteryStateNoetic battery_state_msg;\n#else\nsensor_msgs::BatteryState battery_state_msg;\n#endif\nros::Publisher battery_state_pub(\"battery_state\", &battery_state_msg);\n\n// Magnetic field\nsensor_msgs::MagneticField mag_msg;\nros::Publisher mag_pub(\"magnetic_field\", &mag_msg);\n\n/*******************************************************************************\n* Transform Broadcaster\n*******************************************************************************/\n// TF of Turtlebot3\ngeometry_msgs::TransformStamped odom_tf;\ntf::TransformBroadcaster tf_broadcaster;\n\n/*******************************************************************************\n* SoftwareTimer of Turtlebot3\n*******************************************************************************/\nstatic uint32_t tTime[10];\n\n/*******************************************************************************\n* Declaration for motor\n*******************************************************************************/\nTurtlebot3MotorDriver motor_driver;\n\n/*******************************************************************************\n* Calculation for odometry\n*******************************************************************************/\nbool init_encoder = true;\nint32_t last_diff_tick[WHEEL_NUM] = {0, 0};\ndouble  last_rad[WHEEL_NUM]       = {0.0, 0.0};\n\n/*******************************************************************************\n* Update Joint State\n*******************************************************************************/\ndouble  last_velocity[WHEEL_NUM]  = {0.0, 0.0};\n\n/*******************************************************************************\n* Declaration for sensors\n*******************************************************************************/\nTurtlebot3Sensor sensors;\n\n/*******************************************************************************\n* Declaration for controllers\n*******************************************************************************/\nTurtlebot3Controller controllers;\nfloat zero_velocity[WHEEL_NUM] = {0.0, 0.0};\nfloat goal_velocity[WHEEL_NUM] = {0.0, 0.0};\nfloat goal_velocity_from_button[WHEEL_NUM] = {0.0, 0.0};\nfloat goal_velocity_from_cmd[WHEEL_NUM] = {0.0, 0.0};\nfloat goal_velocity_from_rc100[WHEEL_NUM] = {0.0, 0.0};\n\n/*******************************************************************************\n* Declaration for diagnosis\n*******************************************************************************/\nTurtlebot3Diagnosis diagnosis;\n\n/*******************************************************************************\n* Declaration for SLAM and navigation\n*******************************************************************************/\nunsigned long prev_update_time;\nfloat odom_pose[3];\ndouble odom_vel[3];\n\n/*******************************************************************************\n* Declaration for Battery\n*******************************************************************************/\nbool setup_end        = false;\nuint8_t battery_state = 0;\n\n#endif // TURTLEBOT3_CORE_CONFIG_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_bike/turtlebot3_bike.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#include <math.h>\n\n#include <RC100.h>\n\n#include \"turtlebot3_bike_motor_driver.h\"\n\n#define WHEEL_RADIUS                    0.033     // meter\n#define WHEEL_SEPARATION                0.16      // meter (BURGER => 0.16, WAFFLE => 0.287)\n#define ROBOT_LENGTH                    0.165     // meter\n\n#define ENCODER_MIN                     -2147483648     // raw\n#define ENCODER_MAX                     2147483648      // raw\n\n#define VELOCITY_CONSTANT_VAULE         1263.632956882  // V = r * w = r * RPM * 0.10472\n                                                        //   = 0.033 * 0.229 * Goal RPM * 0.10472\n                                                        // Goal RPM = V * 1263.632956882\n\n#define CONTROL_PERIOD                  8000\n\n#define MAX_LINEAR_VELOCITY             0.22   // m/s\n#define MAX_ANGULAR_VELOCITY            2.84   // rad/s\n#define VELOCITY_LINEAR_X               0.01   // m/s\n#define VELOCITY_ANGULAR_Z              0.1    // rad/s\n#define SCALE_VELOCITY_LINEAR_X         1\n#define SCALE_VELOCITY_ANGULAR_Z        1\n\n#define DEG2RAD(x)                      (x * 0.01745329252)  // *PI/180\n#define RAD2DEG(x)                      (x * 57.2957795131)  // *180/PI\n\n// Function prototypes\nvoid receiveRemoteControlData(void);\nvoid controlMotorSpeed(void);\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_bike/turtlebot3_bike.ino",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#include \"turtlebot3_bike.h\"\n\n/*******************************************************************************\n* Declaration for Hardware Timer (Interrupt control)\n*******************************************************************************/\nHardwareTimer Timer(TIMER_CH1);\n\n/*******************************************************************************\n* Declaration for RC100 remote conroller\n*******************************************************************************/\nRC100 remote_controller;\ndouble const_cmd_vel    = 0.2;\n\n/*******************************************************************************\n* Declaration for motor\n*******************************************************************************/\nTurtlebot3MotorDriver motor_driver;\n\ndouble linear_x              = 0.0;\ndouble angular_z             = 0.0;\ndouble goal_linear_velocity  = 0.0;\ndouble goal_angular_velocity = 0.0;\n\nvoid setup()\n{\n  // Setting for Dynamixel motors\n  motor_driver.init();\n\n  // Setting for RC100 remote control and cmd_vel\n  remote_controller.begin(1);  //57600bps for RC100\n\n  pinMode(13, OUTPUT);\n\n  SerialBT2.begin(57600);\n\n  // Start Dynamixel Control Interrupt\n  startDynamixelControlInterrupt();\n}\n\nvoid loop()\n{\n  receiveRemoteControlData();\n}\n\nvoid startDynamixelControlInterrupt()\n{\n  Timer.pause();\n  Timer.setPeriod(CONTROL_PERIOD);           // in microseconds\n  Timer.attachInterrupt(controlBike);\n  Timer.refresh();\n  Timer.resume();\n}\n\n/*******************************************************************************\n* Receive RC100 remote controller data\n*******************************************************************************/\nvoid receiveRemoteControlData(void)\n{\n  int received_data = 0;\n\n  if (remote_controller.available())\n  {\n    received_data = remote_controller.readData();\n\n    if (received_data & RC100_BTN_U)\n    {\n      linear_x  += VELOCITY_LINEAR_X * SCALE_VELOCITY_LINEAR_X;\n    }\n    else if (received_data & RC100_BTN_D)\n    {\n      linear_x  -= VELOCITY_LINEAR_X * SCALE_VELOCITY_LINEAR_X;\n    }\n\n    if (received_data & RC100_BTN_L)\n    {\n      angular_z += VELOCITY_ANGULAR_Z * SCALE_VELOCITY_ANGULAR_Z;\n    }\n    else if (received_data & RC100_BTN_R)\n    {\n      angular_z -= VELOCITY_ANGULAR_Z * SCALE_VELOCITY_ANGULAR_Z;\n    }\n\n    if (received_data & RC100_BTN_1)\n    {\n\n    }\n    else if (received_data & RC100_BTN_2)\n    {\n\n    }\n    else if (received_data & RC100_BTN_3)\n    {\n\n    }\n    else if (received_data & RC100_BTN_4)\n    {\n\n    }\n\n    if (received_data & RC100_BTN_6)\n    {\n      linear_x  = const_cmd_vel;\n      angular_z = 0.0;\n    }\n    else if (received_data & RC100_BTN_5)\n    {\n      linear_x  = 0.0;\n      angular_z = 0.0;\n    }\n\n    if (linear_x > MAX_LINEAR_VELOCITY)\n    {\n      linear_x = MAX_LINEAR_VELOCITY;\n    }\n\n    if (angular_z > MAX_ANGULAR_VELOCITY)\n    {\n      angular_z = MAX_ANGULAR_VELOCITY;\n    }\n\n    goal_linear_velocity  = linear_x;\n    goal_angular_velocity = angular_z;\n  }\n}\n\n/*******************************************************************************\n* Control bike speed\n*******************************************************************************/\nvoid controlBike()\n{\n  bool dxl_comm_result = false;\n\n  double wheel1_spd_cmd, wheel2_spd_cmd;\n  double lin_vel1, lin_vel2;\n  double lin_pos3;\n\n  double rotation_center;\n\n  wheel1_spd_cmd = goal_linear_velocity - (goal_angular_velocity * WHEEL_SEPARATION / 2);\n  wheel2_spd_cmd = goal_linear_velocity + (goal_angular_velocity * WHEEL_SEPARATION / 2);\n\n  lin_vel1 = wheel1_spd_cmd * VELOCITY_CONSTANT_VAULE;\n  if (lin_vel1 > LIMIT_X_MAX_VELOCITY)\n  {\n    lin_vel1 =  LIMIT_X_MAX_VELOCITY;\n  }\n  else if (lin_vel1 < -LIMIT_X_MAX_VELOCITY)\n  {\n    lin_vel1 = -LIMIT_X_MAX_VELOCITY;\n  }\n\n  lin_vel2 = wheel2_spd_cmd * VELOCITY_CONSTANT_VAULE;\n  if (lin_vel2 > LIMIT_X_MAX_VELOCITY)\n  {\n    lin_vel2 =  LIMIT_X_MAX_VELOCITY;\n  }\n  else if (lin_vel2 < -LIMIT_X_MAX_VELOCITY)\n  {\n    lin_vel2 = -LIMIT_X_MAX_VELOCITY;\n  }\n\n  rotation_center = (WHEEL_SEPARATION / 2.0) * (lin_vel1 + lin_vel2) / (lin_vel1 - lin_vel2);\n\n  if (lin_vel1 != lin_vel2)\n  {\n    lin_pos3 = X_POS_MAX * atan(ROBOT_LENGTH / rotation_center) / (2.0 * PI) + X_POS_CENTER;\n  }\n  else\n  {\n    lin_pos3 = X_POS_CENTER;\n  }\n\n  dxl_comm_result = motor_driver.controlMotor((int64_t)lin_vel1, (int64_t)lin_vel2, (int64_t)lin_pos3);\n  if (dxl_comm_result == false)\n    return;\n}\n\n// EOF\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_bike/turtlebot3_bike_motor_driver.cpp",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#include \"turtlebot3_bike_motor_driver.h\"\n\nTurtlebot3MotorDriver::Turtlebot3MotorDriver()\n: baudrate_(BAUDRATE),\n  protocol_version_(PROTOCOL_VERSION),\n  left_rear_wheel_id_(DXL_LEFT_REAR_ID), right_rear_wheel_id_(DXL_RIGHT_REAR_ID),\n  front_joint_id_(DXL_FRONT_ID)\n{\n}\n\nTurtlebot3MotorDriver::~Turtlebot3MotorDriver()\n{\n  closeDynamixel();\n}\n\nbool Turtlebot3MotorDriver::init(void)\n{\n  portHandler_   = dynamixel::PortHandler::getPortHandler(DEVICENAME);\n  packetHandler_ = dynamixel::PacketHandler::getPacketHandler(PROTOCOL_VERSION);\n\n  // Open port\n  if (portHandler_->openPort())\n  {\n    ERROR_PRINT(\"Port is opened\");\n  }\n  else\n  {\n    ERROR_PRINT(\"Port couldn't be opened\");\n\n    return false;\n  }\n\n  // Set port baudrate\n  if (portHandler_->setBaudRate(baudrate_))\n  {\n    ERROR_PRINT(\"Baudrate is set\");\n  }\n  else\n  {\n    ERROR_PRINT(\"Baudrate couldn't be set\");\n\n    return false;\n  }\n\n  // Enable Dynamixel Torque\n  setTorque(left_rear_wheel_id_, true);\n  setTorque(right_rear_wheel_id_, true);\n  setTorque(front_joint_id_, true);\n\n  setProfileVelocity(front_joint_id_, 120); //TODO : precise calculation\n\n  groupSyncWriteVelocity_ = new dynamixel::GroupSyncWrite(portHandler_, packetHandler_, ADDR_X_GOAL_VELOCITY, LEN_X_GOAL_VELOCITY);\n  groupBulkWrite_ = new dynamixel::GroupBulkWrite(portHandler_, packetHandler_);\n\n  return true;\n}\n\nbool Turtlebot3MotorDriver::setTorque(uint8_t id, bool onoff)\n{\n  uint8_t dxl_error = 0;\n  int dxl_comm_result = COMM_TX_FAIL;\n\n  dxl_comm_result = packetHandler_->write1ByteTxRx(portHandler_, id, ADDR_X_TORQUE_ENABLE, onoff, &dxl_error);\n  if(dxl_comm_result != COMM_SUCCESS)\n  {\n    packetHandler_->getTxRxResult(dxl_comm_result);\n  }\n  else if(dxl_error != 0)\n  {\n    packetHandler_->getRxPacketError(dxl_error);\n  }\n}\n\nbool Turtlebot3MotorDriver::setProfileAcceleration(uint8_t id, uint32_t value)\n{\n  uint8_t dxl_error = 0;\n  int dxl_comm_result = COMM_TX_FAIL;\n\n  dxl_comm_result = packetHandler_->write4ByteTxRx(portHandler_, id, ADDR_X_PROFILE_ACCELERATION, value, &dxl_error);\n  if (dxl_comm_result != COMM_SUCCESS)\n  {\n    packetHandler_->getTxRxResult(dxl_comm_result);\n  }\n  else if(dxl_error != 0)\n  {\n    packetHandler_->getRxPacketError(dxl_error);\n  }\n}\n\nbool Turtlebot3MotorDriver::setProfileVelocity(uint8_t id, uint32_t value)\n{\n  uint8_t dxl_error = 0;\n  int dxl_comm_result = COMM_TX_FAIL;\n\n  dxl_comm_result = packetHandler_->write4ByteTxRx(portHandler_, id, ADDR_X_PROFILE_VELOCITY, value, &dxl_error);\n  if(dxl_comm_result != COMM_SUCCESS)\n  {\n    packetHandler_->getTxRxResult(dxl_comm_result);\n  }\n  else if(dxl_error != 0)\n  {\n    packetHandler_->getRxPacketError(dxl_error);\n  }\n}\n\nvoid Turtlebot3MotorDriver::closeDynamixel(void)\n{\n  // Disable Dynamixel Torque\n  setTorque(left_rear_wheel_id_, false);\n  setTorque(right_rear_wheel_id_, false);\n  setTorque(front_joint_id_, false);\n\n  // Close port\n  portHandler_->closePort();\n}\n\nbool Turtlebot3MotorDriver::controlMotor(int64_t left_rear_wheel_value, int64_t right_rear_wheel_value, int64_t front_joint_value)\n{\n  bool dxl_addparam_result_;\n  int8_t dxl_comm_result_;\n\n  dxl_addparam_result_ = groupBulkWrite_->addParam(left_rear_wheel_id_, ADDR_X_GOAL_VELOCITY, LEN_X_GOAL_VELOCITY, (uint8_t*)&left_rear_wheel_value);\n  if (dxl_addparam_result_ != true)\n    return false;\n\n  dxl_addparam_result_ = groupBulkWrite_->addParam(right_rear_wheel_id_, ADDR_X_GOAL_VELOCITY, LEN_X_GOAL_VELOCITY, (uint8_t*)&right_rear_wheel_value);\n  if (dxl_addparam_result_ != true)\n    return false;\n\n  dxl_addparam_result_ = groupBulkWrite_->addParam(front_joint_id_, ADDR_X_GOAL_POSITION, LEN_X_GOAL_POSITION, (uint8_t*)&front_joint_value);\n  if (dxl_addparam_result_ != true)\n    return false;\n\n  dxl_comm_result_ = groupBulkWrite_->txPacket();\n  if (dxl_comm_result_ != COMM_SUCCESS)\n  {\n    packetHandler_->getTxRxResult(dxl_comm_result_);\n    return false;\n  }\n\n  groupBulkWrite_->clearParam();\n  return true;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_bike/turtlebot3_bike_motor_driver.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#ifndef TURTLEBOT3_BIKE_MOTOR_DRIVER_H_\n#define TURTLEBOT3_BIKE_MOTOR_DRIVER_H_\n\n#include <DynamixelSDK.h>\n\n// Control table address (Dynamixel X-series)\n#define ADDR_X_TORQUE_ENABLE            64\n#define ADDR_X_GOAL_VELOCITY            104\n#define ADDR_X_PROFILE_ACCELERATION     108\n#define ADDR_X_PROFILE_VELOCITY         112\n#define ADDR_X_GOAL_POSITION            116\n#define ADDR_X_REALTIME_TICK            120\n#define ADDR_X_PRESENT_VELOCITY         128\n#define ADDR_X_PRESENT_POSITION         132\n\n// Limit values (XM430-W210-T)\n#define LIMIT_X_MAX_VELOCITY            240\n\n// Data Byte Length\n#define LEN_X_TORQUE_ENABLE             1\n#define LEN_X_GOAL_VELOCITY             4\n#define LEN_X_GOAL_POSITION             4\n#define LEN_X_REALTIME_TICK             2\n#define LEN_X_PRESENT_VELOCITY          4\n#define LEN_X_PRESENT_POSITION          4\n\n#define PROTOCOL_VERSION                2.0     // Dynamixel protocol version 2.0\n\n#define DXL_LEFT_REAR_ID                1       // ID of left rear motor\n#define DXL_RIGHT_REAR_ID               2       // ID of right rear motor\n#define DXL_FRONT_ID                    3       // ID of front motor\n#define BAUDRATE                        1000000 // baud rate of Dynamixel\n#define DEVICENAME                      \"\"      // no need setting on OpenCR\n\n#define TORQUE_ENABLE                   1       // Value for enabling the torque\n#define TORQUE_DISABLE                  0       // Value for disabling the torque\n\n#define X_POS_MIN                       0\n#define X_POS_MAX                       4095\n#define X_POS_CENTER                    2048\n\nclass Turtlebot3MotorDriver\n{\n public:\n  Turtlebot3MotorDriver();\n  ~Turtlebot3MotorDriver();\n  bool init(void);\n  void closeDynamixel(void);\n  bool setTorque(uint8_t id, bool onoff);\n  bool setProfileAcceleration(uint8_t id, uint32_t value);\n  bool setProfileVelocity(uint8_t id, uint32_t value);\n  bool controlMotor(int64_t left_wheel_value, int64_t right_wheel_value, int64_t front_joint_value);\n\n private:\n  uint32_t baudrate_;\n  float  protocol_version_;\n  uint8_t left_rear_wheel_id_, right_rear_wheel_id_;\n  uint8_t front_joint_id_;\n\n  dynamixel::PortHandler *portHandler_;\n  dynamixel::PacketHandler *packetHandler_;\n\n  dynamixel::GroupSyncWrite *groupSyncWriteVelocity_;\n  dynamixel::GroupBulkWrite *groupBulkWrite_;\n  // dynamixel::GroupSyncRead *groupSyncReadEncoder_;\n};\n\n#endif // TURTLEBOT3_BIKE_MOTOR_DRIVER_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_car/turtlebot3_car.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#include <math.h>\n\n#include <RC100.h>\n\n#include \"turtlebot3_car_motor_driver.h\"\n\n#define WHEEL_RADIUS                    0.033     // meter\n#define WHEEL_SEPARATION                0.16      // meter (BURGER => 0.16, WAFFLE => 0.287)\n#define ROBOT_LENGTH                    0.165     // meter\n\n#define ENCODER_MIN                     -2147483648     // raw\n#define ENCODER_MAX                     2147483648      // raw\n\n#define VELOCITY_CONSTANT_VAULE         1263.632956882  // V = r * w = r * RPM * 0.10472\n                                                        //   = 0.033 * 0.229 * Goal RPM * 0.10472\n                                                        // Goal RPM = V * 1263.632956882\n\n#define CONTROL_PERIOD                  8000\n\n#define MAX_LINEAR_VELOCITY             0.22   // m/s\n#define MAX_ANGULAR_VELOCITY            2.84   // rad/s\n#define VELOCITY_LINEAR_X               0.01   // m/s\n#define VELOCITY_ANGULAR_Z              0.1    // rad/s\n#define SCALE_VELOCITY_LINEAR_X         1\n#define SCALE_VELOCITY_ANGULAR_Z        1\n\n#define DEG2RAD(x)                      (x * 0.01745329252)  // *PI/180\n#define RAD2DEG(x)                      (x * 57.2957795131)  // *180/PI\n\n// Function prototypes\nvoid receiveRemoteControlData(void);\nvoid controlMotorSpeed(void);\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_car/turtlebot3_car.ino",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#include \"turtlebot3_car.h\"\n\n/*******************************************************************************\n* Declaration for Hardware Timer (Interrupt control)\n*******************************************************************************/\nHardwareTimer Timer(TIMER_CH1);\n\n/*******************************************************************************\n* Declaration for RC100 remote conroller\n*******************************************************************************/\nRC100 remote_controller;\ndouble const_cmd_vel    = 0.2;\n\n/*******************************************************************************\n* Declaration for motor\n*******************************************************************************/\nTurtlebot3MotorDriver motor_driver;\n\ndouble linear_x              = 0.0;\ndouble angular               = 0.0;\ndouble goal_linear_velocity  = 0.0;\ndouble goal_angular_position = 0.0;\n\nvoid setup()\n{\n  // Setting for Dynamixel motors\n  motor_driver.init();\n\n  // Setting for RC100 remote control and cmd_vel\n  remote_controller.begin(1);  //57600bps for RC100\n\n  pinMode(13, OUTPUT);\n\n  SerialBT2.begin(57600);\n\n  // Start Dynamixel Control Interrupt\n  startDynamixelControlInterrupt();\n}\n\nvoid loop()\n{\n  receiveRemoteControlData();\n}\n\nvoid startDynamixelControlInterrupt()\n{\n  Timer.pause();\n  Timer.setPeriod(CONTROL_PERIOD);           // in microseconds\n  Timer.attachInterrupt(controlCar);\n  Timer.refresh();\n  Timer.resume();\n}\n\n/*******************************************************************************\n* Receive RC100 remote controller data\n*******************************************************************************/\nvoid receiveRemoteControlData(void)\n{\n  int received_data = 0;\n\n  if (remote_controller.available())\n  {\n    received_data = remote_controller.readData();\n\n    if (received_data & RC100_BTN_U)\n    {\n      angular = 0.0;\n    }\n    else if (received_data & RC100_BTN_D)\n    {\n    }\n\n    if (received_data & RC100_BTN_L)\n    {\n      angular = (TURN_VALUE / (X_POS_MAX + 1.0)) * 2 * PI;\n    }\n    else if (received_data & RC100_BTN_R)\n    {\n      angular = -(TURN_VALUE / (X_POS_MAX + 1.0)) * 2 * PI;\n    }\n\n    if (received_data & RC100_BTN_1)\n    {\n      linear_x += VELOCITY_LINEAR_X * SCALE_VELOCITY_LINEAR_X;\n    }\n    else if (received_data & RC100_BTN_2)\n    {\n\n    }\n    else if (received_data & RC100_BTN_3)\n    {\n      linear_x -= VELOCITY_LINEAR_X * SCALE_VELOCITY_LINEAR_X;\n    }\n    else if (received_data & RC100_BTN_4)\n    {\n\n    }\n\n    if (received_data & RC100_BTN_6)\n    {\n      linear_x  = const_cmd_vel;\n      angular = 0.0;\n    }\n    else if (received_data & RC100_BTN_5)\n    {\n      linear_x  = 0.0;\n      angular = 0.0;\n    }\n\n    if (linear_x > MAX_LINEAR_VELOCITY)\n    {\n      linear_x = MAX_LINEAR_VELOCITY;\n    }\n\n    goal_linear_velocity  = linear_x;\n    goal_angular_position = angular;\n  }\n}\n\n/*******************************************************************************\n* Control bike speed\n*******************************************************************************/\nvoid controlCar()\n{\n  bool dxl_comm_result = false;\n\n  double wheel_spd_cmd;\n  double lin_pos1;\n  double lin_vel2;\n\n  lin_pos1 = (X_POS_MAX * goal_angular_position) / (2.0 * PI) + X_POS_CENTER;\n\n  wheel_spd_cmd = goal_linear_velocity;\n\n  lin_vel2 = wheel_spd_cmd * VELOCITY_CONSTANT_VAULE;\n  if (lin_vel2 > LIMIT_X_MAX_VELOCITY)\n  {\n    lin_vel2 =  LIMIT_X_MAX_VELOCITY;\n  }\n  else if (lin_vel2 < -LIMIT_X_MAX_VELOCITY)\n  {\n    lin_vel2 = -LIMIT_X_MAX_VELOCITY;\n  }\n\n  dxl_comm_result = motor_driver.controlMotor((int64_t)lin_pos1, (int64_t)lin_vel2);\n  if (dxl_comm_result == false)\n    return;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_car/turtlebot3_car_motor_driver.cpp",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#include \"turtlebot3_car_motor_driver.h\"\n\nTurtlebot3MotorDriver::Turtlebot3MotorDriver()\n: baudrate_(BAUDRATE),\n  protocol_version_(PROTOCOL_VERSION),\n  rear_wheel_id_(DXL_REAR_ID),\n  front_joint_id_(DXL_FRONT_ID)\n{\n}\n\nTurtlebot3MotorDriver::~Turtlebot3MotorDriver()\n{\n  closeDynamixel();\n}\n\nbool Turtlebot3MotorDriver::init(void)\n{\n  portHandler_   = dynamixel::PortHandler::getPortHandler(DEVICENAME);\n  packetHandler_ = dynamixel::PacketHandler::getPacketHandler(PROTOCOL_VERSION);\n\n  // Open port\n  if (portHandler_->openPort())\n  {\n    ERROR_PRINT(\"Port is opened\");\n  }\n  else\n  {\n    ERROR_PRINT(\"Port couldn't be opened\");\n\n    return false;\n  }\n\n  // Set port baudrate\n  if (portHandler_->setBaudRate(baudrate_))\n  {\n    ERROR_PRINT(\"Baudrate is set\");\n  }\n  else\n  {\n    ERROR_PRINT(\"Baudrate couldn't be set\");\n\n    return false;\n  }\n\n  // Enable Dynamixel Torque\n  setTorque(front_joint_id_, true);\n  setTorque(rear_wheel_id_, true);\n\n  setProfileVelocity(front_joint_id_, 30); //TODO : precise calculation\n\n  groupBulkWrite_ = new dynamixel::GroupBulkWrite(portHandler_, packetHandler_);\n\n  return true;\n}\n\nbool Turtlebot3MotorDriver::setTorque(uint8_t id, bool onoff)\n{\n  uint8_t dxl_error = 0;\n  int dxl_comm_result = COMM_TX_FAIL;\n\n  dxl_comm_result = packetHandler_->write1ByteTxRx(portHandler_, id, ADDR_X_TORQUE_ENABLE, onoff, &dxl_error);\n  if(dxl_comm_result != COMM_SUCCESS)\n  {\n    packetHandler_->getTxRxResult(dxl_comm_result);\n  }\n  else if(dxl_error != 0)\n  {\n    packetHandler_->getRxPacketError(dxl_error);\n  }\n}\n\nbool Turtlebot3MotorDriver::setProfileAcceleration(uint8_t id, uint32_t value)\n{\n  uint8_t dxl_error = 0;\n  int dxl_comm_result = COMM_TX_FAIL;\n\n  dxl_comm_result = packetHandler_->write4ByteTxRx(portHandler_, id, ADDR_X_PROFILE_ACCELERATION, value, &dxl_error);\n  if (dxl_comm_result != COMM_SUCCESS)\n  {\n    packetHandler_->getTxRxResult(dxl_comm_result);\n  }\n  else if(dxl_error != 0)\n  {\n    packetHandler_->getRxPacketError(dxl_error);\n  }\n}\n\nbool Turtlebot3MotorDriver::setProfileVelocity(uint8_t id, uint32_t value)\n{\n  uint8_t dxl_error = 0;\n  int dxl_comm_result = COMM_TX_FAIL;\n\n  dxl_comm_result = packetHandler_->write4ByteTxRx(portHandler_, id, ADDR_X_PROFILE_VELOCITY, value, &dxl_error);\n  if(dxl_comm_result != COMM_SUCCESS)\n  {\n    packetHandler_->getTxRxResult(dxl_comm_result);\n  }\n  else if(dxl_error != 0)\n  {\n    packetHandler_->getRxPacketError(dxl_error);\n  }\n}\n\nvoid Turtlebot3MotorDriver::closeDynamixel(void)\n{\n  // Disable Dynamixel Torque\n  setTorque(front_joint_id_, false);\n  setTorque(rear_wheel_id_, false);\n\n  // Close port\n  portHandler_->closePort();\n}\n\nbool Turtlebot3MotorDriver::controlMotor(int64_t front_joint_value, int64_t rear_wheel_value)\n{\n  bool dxl_addparam_result_;\n  int8_t dxl_comm_result_;\n\n  dxl_addparam_result_ = groupBulkWrite_->addParam(front_joint_id_, ADDR_X_GOAL_POSITION, LEN_X_GOAL_POSITION, (uint8_t*)&front_joint_value);\n  if (dxl_addparam_result_ != true)\n    return false;\n\n  dxl_addparam_result_ = groupBulkWrite_->addParam(rear_wheel_id_, ADDR_X_GOAL_VELOCITY, LEN_X_GOAL_VELOCITY, (uint8_t*)&rear_wheel_value);\n  if (dxl_addparam_result_ != true)\n    return false;\n\n  dxl_comm_result_ = groupBulkWrite_->txPacket();\n  if (dxl_comm_result_ != COMM_SUCCESS)\n  {\n    packetHandler_->getTxRxResult(dxl_comm_result_);\n    return false;\n  }\n\n  groupBulkWrite_->clearParam();\n  return true;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_car/turtlebot3_car_motor_driver.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#ifndef TURTLEBOT3_BIKE_MOTOR_DRIVER_H_\n#define TURTLEBOT3_BIKE_MOTOR_DRIVER_H_\n\n#include <DynamixelSDK.h>\n\n// Control table address (Dynamixel X-series)\n#define ADDR_X_TORQUE_ENABLE            64\n#define ADDR_X_GOAL_VELOCITY            104\n#define ADDR_X_PROFILE_ACCELERATION     108\n#define ADDR_X_PROFILE_VELOCITY         112\n#define ADDR_X_GOAL_POSITION            116\n#define ADDR_X_REALTIME_TICK            120\n#define ADDR_X_PRESENT_VELOCITY         128\n#define ADDR_X_PRESENT_POSITION         132\n\n// Limit values (XM430-W210-T)\n#define LIMIT_X_MAX_VELOCITY            240\n\n// Data Byte Length\n#define LEN_X_TORQUE_ENABLE             1\n#define LEN_X_GOAL_VELOCITY             4\n#define LEN_X_GOAL_POSITION             4\n#define LEN_X_REALTIME_TICK             2\n#define LEN_X_PRESENT_VELOCITY          4\n#define LEN_X_PRESENT_POSITION          4\n\n#define PROTOCOL_VERSION                2.0     // Dynamixel protocol version 2.0\n\n#define DXL_REAR_ID                     2       // ID of rear motor\n#define DXL_FRONT_ID                    1       // ID of front motor\n#define BAUDRATE                        1000000 // baud rate of Dynamixel\n#define DEVICENAME                      \"\"      // no need setting on OpenCR\n\n#define TORQUE_ENABLE                   1       // Value for enabling the torque\n#define TORQUE_DISABLE                  0       // Value for disabling the torque\n\n#define TURN_VALUE                      204\n\n#define X_POS_MIN                       0\n#define X_POS_MAX                       4095\n#define X_POS_CENTER                    2868 // Don't need to use this value... actual center position value of the Dynamixel is 2048\n\nclass Turtlebot3MotorDriver\n{\n public:\n  Turtlebot3MotorDriver();\n  ~Turtlebot3MotorDriver();\n  bool init(void);\n  void closeDynamixel(void);\n  bool setTorque(uint8_t id, bool onoff);\n  bool setProfileAcceleration(uint8_t id, uint32_t value);\n  bool setProfileVelocity(uint8_t id, uint32_t value);\n  bool controlMotor(int64_t front_joint_value, int64_t rear_wheel_value);\n\n private:\n  uint32_t baudrate_;\n  float  protocol_version_;\n  uint8_t rear_wheel_id_;\n  uint8_t front_joint_id_;\n\n  dynamixel::PortHandler *portHandler_;\n  dynamixel::PacketHandler *packetHandler_;\n\n  dynamixel::GroupBulkWrite *groupBulkWrite_;\n};\n\n#endif // TURTLEBOT3_CAR_MOTOR_DRIVER_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_conveyor/turtlebot3_conveyor.h",
    "content": "#include <RC100.h>\n\n#define BODY_LENGTH           25.6\n#define SPEED_ADD_ON          2\n\nclass DynamixelStatus\n{\n private:\n   int velocity = 200;\n\n   int32_t wheel_vel[4] = {0, };\n   int32_t joint_angle[4] = {0, };\n\n   enum MODE\n   {\n     NONE = 0\n     , FORWARD, BACKWARD, RLEFT, RRIGHT, PLEFT, PRIGHT\n     , PLEFT_FORWARD, PRIGHT_FORWARD, PLEFT_BACKWARD, PRIGHT_BACKWARD, RLEFT_FORWARD, RRIGHT_FORWARD, RLEFT_BACKWARD, RRIGHT_BACKWARD, RLEFT_PLEFT, RLEFT_PRIGHT, RRIGHT_PLEFT, RRIGHT_PRIGHT\n     , RLEFT_PLEFT_FORWARD, RLEFT_PLEFT_BACKWARD, RRIGHT_PLEFT_FORWARD, RRIGHT_PLEFT_BACKWARD, RLEFT_PRIGHT_FORWARD, RLEFT_PRIGHT_BACKWARD, RRIGHT_PRIGHT_FORWARD, RRIGHT_PRIGHT_BACKWARD\n   } mobile_mode;\n\n public:\n   double distance_from_center = 25.6;\n\n   int wheel_l_r_vel, wheel_r_r_vel, wheel_l_f_vel, wheel_r_f_vel;\n   int joint_l_r_angle, joint_r_r_angle, joint_l_f_angle, joint_r_f_angle;\n\n   DynamixelStatus()\n   : wheel_l_r_vel(0), wheel_r_r_vel(0), wheel_l_f_vel(0), wheel_r_f_vel(0)\n   , joint_l_r_angle(0), joint_r_r_angle(0), joint_l_f_angle(0), joint_r_f_angle(0)\n   { }\n\n   MODE getDirection(int rcData)\n   {\n     switch (rcData)\n     {\n      case (RC100_BTN_U): mobile_mode = FORWARD; break;\n      case (RC100_BTN_D): mobile_mode = BACKWARD; break;\n      case (RC100_BTN_L): mobile_mode = RLEFT; break;\n      case (RC100_BTN_R): mobile_mode = RRIGHT; break;\n      case (RC100_BTN_2): mobile_mode = PLEFT; break;\n      case (RC100_BTN_4): mobile_mode = PRIGHT; break;\n\n      case (RC100_BTN_U + RC100_BTN_1): mobile_mode = PLEFT_FORWARD; break;\n      case (RC100_BTN_U + RC100_BTN_3): mobile_mode = PRIGHT_FORWARD; break;\n      case (RC100_BTN_D + RC100_BTN_1): mobile_mode = PLEFT_BACKWARD; break;\n      case (RC100_BTN_D + RC100_BTN_3): mobile_mode = PRIGHT_BACKWARD; break;\n      case (RC100_BTN_U + RC100_BTN_L): mobile_mode = RLEFT_FORWARD; break;\n      case (RC100_BTN_U + RC100_BTN_R): mobile_mode = RRIGHT_FORWARD; break;\n      case (RC100_BTN_D + RC100_BTN_L): mobile_mode = RLEFT_BACKWARD; break;\n      case (RC100_BTN_D + RC100_BTN_R): mobile_mode = RRIGHT_BACKWARD; break;\n      case (RC100_BTN_L + RC100_BTN_6): mobile_mode = RLEFT_PLEFT; break;\n      case (RC100_BTN_L + RC100_BTN_5): mobile_mode = RLEFT_PRIGHT; break;\n      case (RC100_BTN_R + RC100_BTN_6): mobile_mode = RRIGHT_PLEFT; break;\n      case (RC100_BTN_R + RC100_BTN_5): mobile_mode = RRIGHT_PRIGHT; break;\n\n      case (RC100_BTN_L + RC100_BTN_6 + RC100_BTN_U): mobile_mode = RLEFT_PLEFT_FORWARD; break;\n      case (RC100_BTN_L + RC100_BTN_6 + RC100_BTN_D): mobile_mode = RLEFT_PLEFT_BACKWARD; break;\n      case (RC100_BTN_R + RC100_BTN_6 + RC100_BTN_U): mobile_mode = RRIGHT_PLEFT_FORWARD; break;\n      case (RC100_BTN_R + RC100_BTN_6 + RC100_BTN_D): mobile_mode = RRIGHT_PLEFT_BACKWARD; break;\n      case (RC100_BTN_L + RC100_BTN_5 + RC100_BTN_U): mobile_mode = RLEFT_PRIGHT_FORWARD; break;\n      case (RC100_BTN_L + RC100_BTN_5 + RC100_BTN_D): mobile_mode = RLEFT_PRIGHT_BACKWARD; break;\n      case (RC100_BTN_R + RC100_BTN_5 + RC100_BTN_U): mobile_mode = RRIGHT_PRIGHT_FORWARD; break;\n      case (RC100_BTN_R + RC100_BTN_5 + RC100_BTN_D): mobile_mode = RRIGHT_PRIGHT_BACKWARD; break;\n\n      default: \n                // if (rcData & RC100_BTN_1) { if (velocity <= 245) velocity += 5; }\n                if (rcData & RC100_BTN_2) { if (distance_from_center >= (12.8 * sqrt(2.0) + 2.0)) distance_from_center -= 2.0; }\n                // else if (rcData & RC100_BTN_3) { if (velocity >= 5) velocity -= 5; }\n                else if (rcData & RC100_BTN_4) { if (distance_from_center <= 49.2) distance_from_center += 2.0; }\n                else { mobile_mode = NONE; }\n                break;\n     }\n\n     return mobile_mode;\n   }\n\n   void setParams()\n   {\n     switch (mobile_mode)\n     {\n       case FORWARD:                wheel_l_r_vel = -velocity * SPEED_ADD_ON; wheel_r_r_vel = velocity * SPEED_ADD_ON; wheel_l_f_vel = -velocity * SPEED_ADD_ON; wheel_r_f_vel = velocity * SPEED_ADD_ON;\n                                    joint_l_r_angle = 512; joint_r_r_angle = -512; joint_l_f_angle = -512; joint_r_f_angle = 512;\n                                    break;\n       case BACKWARD:               wheel_l_r_vel = velocity * SPEED_ADD_ON; wheel_r_r_vel = -velocity * SPEED_ADD_ON; wheel_l_f_vel = velocity * SPEED_ADD_ON; wheel_r_f_vel = -velocity * SPEED_ADD_ON;\n                                    joint_l_r_angle = 512; joint_r_r_angle = -512; joint_l_f_angle = -512; joint_r_f_angle = 512;\n                                    break;\n       case RLEFT:                  wheel_l_r_vel = velocity; wheel_r_r_vel = velocity; wheel_l_f_vel = velocity; wheel_r_f_vel = velocity;\n                                    joint_l_r_angle = 0; joint_r_r_angle = 0; joint_l_f_angle = 0; joint_r_f_angle = 0;\n                                    break;\n       case RRIGHT:                 wheel_l_r_vel = -velocity; wheel_r_r_vel = -velocity; wheel_l_f_vel = -velocity; wheel_r_f_vel = -velocity;\n                                    joint_l_r_angle = 0; joint_r_r_angle = 0; joint_l_f_angle = 0; joint_r_f_angle = 0;\n                                    break;\n       case PLEFT:                  wheel_l_r_vel = -velocity * SPEED_ADD_ON; wheel_r_r_vel = -velocity * SPEED_ADD_ON; wheel_l_f_vel = velocity * SPEED_ADD_ON; wheel_r_f_vel = velocity * SPEED_ADD_ON;\n                                    joint_l_r_angle = -512; joint_r_r_angle = 512; joint_l_f_angle = 512; joint_r_f_angle = -512;\n                                    break;\n       case PRIGHT:                 wheel_l_r_vel = velocity * SPEED_ADD_ON; wheel_r_r_vel = velocity * SPEED_ADD_ON; wheel_l_f_vel = -velocity * SPEED_ADD_ON; wheel_r_f_vel = -velocity * SPEED_ADD_ON;\n                                    joint_l_r_angle = -512; joint_r_r_angle = 512; joint_l_f_angle = 512; joint_r_f_angle = -512;\n                                    break;\n\n       case PLEFT_FORWARD:          wheel_l_r_vel = -velocity * SPEED_ADD_ON; wheel_r_r_vel = -velocity * SPEED_ADD_ON; wheel_l_f_vel = velocity * SPEED_ADD_ON; wheel_r_f_vel = velocity * SPEED_ADD_ON;\n                                    joint_l_r_angle = 0; joint_r_r_angle = 1024; joint_l_f_angle = 1024; joint_r_f_angle = 0;\n                                    break;\n       case PRIGHT_FORWARD:         wheel_l_r_vel = velocity * SPEED_ADD_ON; wheel_r_r_vel = velocity * SPEED_ADD_ON; wheel_l_f_vel = -velocity * SPEED_ADD_ON; wheel_r_f_vel = -velocity * SPEED_ADD_ON;\n                                    joint_l_r_angle = -1024; joint_r_r_angle = 0; joint_l_f_angle = 0; joint_r_f_angle = -1024;\n                                    break;\n       case PLEFT_BACKWARD:         wheel_l_r_vel = -velocity * SPEED_ADD_ON; wheel_r_r_vel = -velocity * SPEED_ADD_ON; wheel_l_f_vel = velocity * SPEED_ADD_ON; wheel_r_f_vel = velocity * SPEED_ADD_ON;\n                                    joint_l_r_angle = -1024; joint_r_r_angle = 0; joint_l_f_angle = 0; joint_r_f_angle = -1024;\n                                    break;\n       case PRIGHT_BACKWARD:        wheel_l_r_vel = velocity * SPEED_ADD_ON; wheel_r_r_vel = velocity * SPEED_ADD_ON; wheel_l_f_vel = -velocity * SPEED_ADD_ON; wheel_r_f_vel = -velocity * SPEED_ADD_ON;\n                                    joint_l_r_angle = 0; joint_r_r_angle = 1024; joint_l_f_angle = 1024; joint_r_f_angle = 0;\n                                    break;\n       case RLEFT_FORWARD:          wheel_l_r_vel = -(int)((velocity * (BODY_LENGTH / 2.0)) / ((distance_from_center + (BODY_LENGTH / 2.0)) * cos(atan(distance_from_center / (BODY_LENGTH / 2.0)))));\n                                    wheel_r_r_vel = (int)((velocity * (BODY_LENGTH / 2.0)) / ((distance_from_center + (BODY_LENGTH / 2.0)) * cos(atan((distance_from_center + BODY_LENGTH) / (BODY_LENGTH / 2.0)))));\n                                    wheel_l_f_vel = -(int)((velocity * (BODY_LENGTH / 2.0)) / ((distance_from_center + (BODY_LENGTH / 2.0)) * cos(atan(distance_from_center / (BODY_LENGTH / 2.0)))));\n                                    wheel_r_f_vel = (int)((velocity * (BODY_LENGTH / 2.0)) / ((distance_from_center + (BODY_LENGTH / 2.0)) * cos(atan((distance_from_center + BODY_LENGTH) / (BODY_LENGTH / 2.0)))));\n                                    joint_l_r_angle = (1536 - (int)(2048.0 * atan(distance_from_center / (BODY_LENGTH / 2.0)) / PI));\n                                    joint_r_r_angle = (512 - (int)(2048.0 * atan((distance_from_center + BODY_LENGTH) / (BODY_LENGTH / 2.0)) / PI));\n                                    joint_l_f_angle = -(1536 - (int)(2048.0 * atan(distance_from_center / (BODY_LENGTH / 2.0)) / PI));\n                                    joint_r_f_angle = -(512 - (int)(2048.0 * atan((distance_from_center + BODY_LENGTH) / (BODY_LENGTH / 2.0)) / PI));\n                                    break;\n       case RRIGHT_FORWARD:         wheel_l_r_vel = -(int)((velocity * (BODY_LENGTH / 2.0)) / ((distance_from_center + (BODY_LENGTH / 2.0)) * cos(atan((distance_from_center + BODY_LENGTH) / (BODY_LENGTH / 2.0)))));\n                                    wheel_r_r_vel = (int)((velocity * (BODY_LENGTH / 2.0)) / ((distance_from_center + (BODY_LENGTH / 2.0)) * cos(atan(distance_from_center / (BODY_LENGTH / 2.0)))));\n                                    wheel_l_f_vel = -(int)((velocity * (BODY_LENGTH / 2.0)) / ((distance_from_center + (BODY_LENGTH / 2.0)) * cos(atan((distance_from_center + BODY_LENGTH) / (BODY_LENGTH / 2.0)))));\n                                    wheel_r_f_vel = (int)((velocity * (BODY_LENGTH / 2.0)) / ((distance_from_center + (BODY_LENGTH / 2.0)) * cos(atan(distance_from_center / (BODY_LENGTH / 2.0)))));\n                                    joint_l_r_angle = -(512 - (int)(2048.0 * atan((distance_from_center + BODY_LENGTH) / (BODY_LENGTH / 2.0)) / PI));\n                                    joint_r_r_angle = -(1536 - (int)(2048.0 * atan(distance_from_center / (BODY_LENGTH / 2.0)) / PI));\n                                    joint_l_f_angle = (512 - (int)(2048.0 * atan((distance_from_center + BODY_LENGTH) / (BODY_LENGTH / 2.0)) / PI));\n                                    joint_r_f_angle = (1536 - (int)(2048.0 * atan(distance_from_center / (BODY_LENGTH / 2.0)) / PI));\n                                    break;\n       case RLEFT_BACKWARD:         wheel_l_r_vel = (int)((velocity * (BODY_LENGTH / 2.0)) / ((distance_from_center + (BODY_LENGTH / 2.0)) * cos(atan(distance_from_center / (BODY_LENGTH / 2.0)))));\n                                    wheel_r_r_vel = -(int)((velocity * (BODY_LENGTH / 2.0)) / ((distance_from_center + (BODY_LENGTH / 2.0)) * cos(atan((distance_from_center + BODY_LENGTH) / (BODY_LENGTH / 2.0)))));\n                                    wheel_l_f_vel = (int)((velocity * (BODY_LENGTH / 2.0)) / ((distance_from_center + (BODY_LENGTH / 2.0)) * cos(atan(distance_from_center / (BODY_LENGTH / 2.0)))));\n                                    wheel_r_f_vel = -(int)((velocity * (BODY_LENGTH / 2.0)) / ((distance_from_center + (BODY_LENGTH / 2.0)) * cos(atan((distance_from_center + BODY_LENGTH) / (BODY_LENGTH / 2.0)))));\n                                    joint_l_r_angle = (1536 - (int)(2048.0 * atan(distance_from_center / (BODY_LENGTH / 2.0)) / PI));\n                                    joint_r_r_angle = (512 - (int)(2048.0 * atan((distance_from_center + BODY_LENGTH) / (BODY_LENGTH / 2.0)) / PI));\n                                    joint_l_f_angle = -(1536 - (int)(2048.0 * atan(distance_from_center / (BODY_LENGTH / 2.0)) / PI));\n                                    joint_r_f_angle = -(512 - (int)(2048.0 * atan((distance_from_center + BODY_LENGTH) / (BODY_LENGTH / 2.0)) / PI));\n                                    break;\n       case RRIGHT_BACKWARD:        wheel_l_r_vel = (int)((velocity * (BODY_LENGTH / 2.0)) / ((distance_from_center + (BODY_LENGTH / 2.0)) * cos(atan((distance_from_center + BODY_LENGTH) / (BODY_LENGTH / 2.0)))));\n                                    wheel_r_r_vel = -(int)((velocity * (BODY_LENGTH / 2.0)) / ((distance_from_center + (BODY_LENGTH / 2.0)) * cos(atan(distance_from_center / (BODY_LENGTH / 2.0)))));\n                                    wheel_l_f_vel = (int)((velocity * (BODY_LENGTH / 2.0)) / ((distance_from_center + (BODY_LENGTH / 2.0)) * cos(atan((distance_from_center + BODY_LENGTH) / (BODY_LENGTH / 2.0)))));\n                                    wheel_r_f_vel = -(int)((velocity * (BODY_LENGTH / 2.0)) / ((distance_from_center + (BODY_LENGTH / 2.0)) * cos(atan(distance_from_center / (BODY_LENGTH / 2.0)))));\n                                    joint_l_r_angle = -(512 - (int)(2048.0 * atan((distance_from_center + BODY_LENGTH) / (BODY_LENGTH / 2.0)) / PI));\n                                    joint_r_r_angle = -(1536 - (int)(2048.0 * atan(distance_from_center / (BODY_LENGTH / 2.0)) / PI));\n                                    joint_l_f_angle = (512 - (int)(2048.0 * atan((distance_from_center + BODY_LENGTH) / (BODY_LENGTH / 2.0)) / PI));\n                                    joint_r_f_angle = (1536 - (int)(2048.0 * atan(distance_from_center / (BODY_LENGTH / 2.0)) / PI));\n                                    break;\n       case RLEFT_PLEFT:            wheel_l_r_vel = -(int)((velocity * (BODY_LENGTH / 2.0)) / ((distance_from_center + (BODY_LENGTH / 2.0)) * cos(atan(distance_from_center / (BODY_LENGTH / 2.0)))));\n                                    wheel_r_r_vel = -(int)((velocity * (BODY_LENGTH / 2.0)) / ((distance_from_center + (BODY_LENGTH / 2.0)) * cos(atan(distance_from_center / (BODY_LENGTH / 2.0)))));\n                                    wheel_l_f_vel = (int)((velocity * (BODY_LENGTH / 2.0)) / ((distance_from_center + (BODY_LENGTH / 2.0)) * cos(atan((distance_from_center + BODY_LENGTH) / (BODY_LENGTH / 2.0)))));\n                                    wheel_r_f_vel = (int)((velocity * (BODY_LENGTH / 2.0)) / ((distance_from_center + (BODY_LENGTH / 2.0)) * cos(atan((distance_from_center + BODY_LENGTH) / (BODY_LENGTH / 2.0)))));\n                                    joint_l_r_angle = -(1536 - (int)(2048.0 * atan(distance_from_center / (BODY_LENGTH / 2.0)) / PI));\n                                    joint_r_r_angle = (1536 - (int)(2048.0 * atan(distance_from_center / (BODY_LENGTH / 2.0)) / PI));\n                                    joint_l_f_angle = -(512 - (int)(2048.0 * atan((distance_from_center + BODY_LENGTH) / (BODY_LENGTH / 2.0)) / PI));\n                                    joint_r_f_angle = (512 - (int)(2048.0 * atan((distance_from_center + BODY_LENGTH) / (BODY_LENGTH / 2.0)) / PI));\n                                    break;\n       case RLEFT_PRIGHT:           wheel_l_r_vel = (int)((velocity * (BODY_LENGTH / 2.0)) / ((distance_from_center + (BODY_LENGTH / 2.0)) * cos(atan((distance_from_center + BODY_LENGTH) / (BODY_LENGTH / 2.0)))));\n                                    wheel_r_r_vel = (int)((velocity * (BODY_LENGTH / 2.0)) / ((distance_from_center + (BODY_LENGTH / 2.0)) * cos(atan((distance_from_center + BODY_LENGTH) / (BODY_LENGTH / 2.0)))));\n                                    wheel_l_f_vel = -(int)((velocity * (BODY_LENGTH / 2.0)) / ((distance_from_center + (BODY_LENGTH / 2.0)) * cos(atan(distance_from_center / (BODY_LENGTH / 2.0)))));\n                                    wheel_r_f_vel = -(int)((velocity * (BODY_LENGTH / 2.0)) / ((distance_from_center + (BODY_LENGTH / 2.0)) * cos(atan(distance_from_center / (BODY_LENGTH / 2.0)))));\n                                    joint_l_r_angle = (512 - (int)(2048.0 * atan((distance_from_center + BODY_LENGTH) / (BODY_LENGTH / 2.0)) / PI));\n                                    joint_r_r_angle = -(512 - (int)(2048.0 * atan((distance_from_center + BODY_LENGTH) / (BODY_LENGTH / 2.0)) / PI));\n                                    joint_l_f_angle = (1536 - (int)(2048.0 * atan(distance_from_center / (BODY_LENGTH / 2.0)) / PI));\n                                    joint_r_f_angle = -(1536 - (int)(2048.0 * atan(distance_from_center / (BODY_LENGTH / 2.0)) / PI));\n                                    break;\n       case RRIGHT_PLEFT:           wheel_l_r_vel = -(int)((velocity * (BODY_LENGTH / 2.0)) / ((distance_from_center + (BODY_LENGTH / 2.0)) * cos(atan((distance_from_center + BODY_LENGTH) / (BODY_LENGTH / 2.0)))));\n                                    wheel_r_r_vel = -(int)((velocity * (BODY_LENGTH / 2.0)) / ((distance_from_center + (BODY_LENGTH / 2.0)) * cos(atan((distance_from_center + BODY_LENGTH) / (BODY_LENGTH / 2.0)))));\n                                    wheel_l_f_vel = (int)((velocity * (BODY_LENGTH / 2.0)) / ((distance_from_center + (BODY_LENGTH / 2.0)) * cos(atan(distance_from_center / (BODY_LENGTH / 2.0)))));\n                                    wheel_r_f_vel = (int)((velocity * (BODY_LENGTH / 2.0)) / ((distance_from_center + (BODY_LENGTH / 2.0)) * cos(atan(distance_from_center / (BODY_LENGTH / 2.0)))));\n                                    joint_l_r_angle = (512 - (int)(2048.0 * atan((distance_from_center + BODY_LENGTH) / (BODY_LENGTH / 2.0)) / PI));\n                                    joint_r_r_angle = -(512 - (int)(2048.0 * atan((distance_from_center + BODY_LENGTH) / (BODY_LENGTH / 2.0)) / PI));\n                                    joint_l_f_angle = (1536 - (int)(2048.0 * atan(distance_from_center / (BODY_LENGTH / 2.0)) / PI));\n                                    joint_r_f_angle = -(1536 - (int)(2048.0 * atan(distance_from_center / (BODY_LENGTH / 2.0)) / PI));\n                                    break;\n       case RRIGHT_PRIGHT:          wheel_l_r_vel = (int)((velocity * (BODY_LENGTH / 2.0)) / ((distance_from_center + (BODY_LENGTH / 2.0)) * cos(atan(distance_from_center / (BODY_LENGTH / 2.0)))));\n                                    wheel_r_r_vel = (int)((velocity * (BODY_LENGTH / 2.0)) / ((distance_from_center + (BODY_LENGTH / 2.0)) * cos(atan(distance_from_center / (BODY_LENGTH / 2.0)))));\n                                    wheel_l_f_vel = -(int)((velocity * (BODY_LENGTH / 2.0)) / ((distance_from_center + (BODY_LENGTH / 2.0)) * cos(atan((distance_from_center + BODY_LENGTH) / (BODY_LENGTH / 2.0)))));\n                                    wheel_r_f_vel = -(int)((velocity * (BODY_LENGTH / 2.0)) / ((distance_from_center + (BODY_LENGTH / 2.0)) * cos(atan((distance_from_center + BODY_LENGTH) / (BODY_LENGTH / 2.0)))));\n                                    joint_l_r_angle = -(1536 - (int)(2048.0 * atan(distance_from_center / (BODY_LENGTH / 2.0)) / PI));\n                                    joint_r_r_angle = (1536 - (int)(2048.0 * atan(distance_from_center / (BODY_LENGTH / 2.0)) / PI));\n                                    joint_l_f_angle = -(512 - (int)(2048.0 * atan((distance_from_center + BODY_LENGTH) / (BODY_LENGTH / 2.0)) / PI));\n                                    joint_r_f_angle = (512 - (int)(2048.0 * atan((distance_from_center + BODY_LENGTH) / (BODY_LENGTH / 2.0)) / PI));\n                                    break;\n\n       case RLEFT_PLEFT_FORWARD:    wheel_l_r_vel = -(int)(velocity * distance_from_center / (distance_from_center + (BODY_LENGTH / sqrt(2.0))));\n                                    wheel_r_r_vel = (int)(velocity * (BODY_LENGTH / sqrt(2.0)) / (cos(atan((distance_from_center / (BODY_LENGTH / sqrt(2.0)) + 1.0))) * (distance_from_center + (BODY_LENGTH / sqrt(2.0)))));\n                                    wheel_l_f_vel = (int)(velocity * (BODY_LENGTH / sqrt(2.0)) / (cos(atan((distance_from_center / (BODY_LENGTH / sqrt(2.0)) + 1.0))) * (distance_from_center + (BODY_LENGTH / sqrt(2.0)))));\n                                    wheel_r_f_vel = (int)(velocity * (distance_from_center + BODY_LENGTH * sqrt(2.0)) / (distance_from_center + (BODY_LENGTH / sqrt(2.0))));\n                                    joint_l_r_angle = 0;\n                                    joint_r_r_angle = -(2048 - (int)(2048.0 * atan((distance_from_center / (BODY_LENGTH / sqrt(2.0)) + 1.0) / PI)));\n                                    joint_l_f_angle = (2048 - (int)(2048.0 * atan((distance_from_center / (BODY_LENGTH / sqrt(2.0)) + 1.0) / PI)));\n                                    joint_r_f_angle = 0;\n                                    break;\n       case RLEFT_PLEFT_BACKWARD:   wheel_l_r_vel = (int)(velocity * distance_from_center / (distance_from_center + (BODY_LENGTH / sqrt(2.0))));\n                                    wheel_r_r_vel = -(int)(velocity * (BODY_LENGTH / sqrt(2.0)) / (cos(atan((distance_from_center / (BODY_LENGTH / sqrt(2.0)) + 1.0))) * (distance_from_center + (BODY_LENGTH / sqrt(2.0)))));\n                                    wheel_l_f_vel = -(int)(velocity * (BODY_LENGTH / sqrt(2.0)) / (cos(atan((distance_from_center / (BODY_LENGTH / sqrt(2.0)) + 1.0))) * (distance_from_center + (BODY_LENGTH / sqrt(2.0)))));\n                                    wheel_r_f_vel = -(int)(velocity * (distance_from_center + BODY_LENGTH * sqrt(2.0)) / (distance_from_center + (BODY_LENGTH / sqrt(2.0))));\n                                    joint_l_r_angle = 0;\n                                    joint_r_r_angle = -(2048 - (int)(2048.0 * atan((distance_from_center / (BODY_LENGTH / sqrt(2.0)) + 1.0) / PI)));\n                                    joint_l_f_angle = (2048 - (int)(2048.0 * atan((distance_from_center / (BODY_LENGTH / sqrt(2.0)) + 1.0) / PI)));\n                                    joint_r_f_angle = 0;\n                                    break;\n       case RRIGHT_PLEFT_FORWARD:   wheel_l_r_vel = -(int)(velocity * (distance_from_center + BODY_LENGTH * sqrt(2.0)) / (distance_from_center + (BODY_LENGTH / sqrt(2.0))));\n                                    wheel_r_r_vel = -(int)(velocity * (BODY_LENGTH / sqrt(2.0)) / (cos(atan((distance_from_center / (BODY_LENGTH / sqrt(2.0)) + 1.0))) * (distance_from_center + (BODY_LENGTH / sqrt(2.0)))));\n                                    wheel_l_f_vel = -(int)(velocity * (BODY_LENGTH / sqrt(2.0)) / (cos(atan((distance_from_center / (BODY_LENGTH / sqrt(2.0)) + 1.0))) * (distance_from_center + (BODY_LENGTH / sqrt(2.0)))));\n                                    wheel_r_f_vel = (int)(velocity * distance_from_center / (distance_from_center + (BODY_LENGTH / sqrt(2.0))));\n                                    joint_l_r_angle = 0;\n                                    joint_r_r_angle = (2048 - (int)(2048.0 * atan((distance_from_center / (BODY_LENGTH / sqrt(2.0)) + 1.0) / PI)));\n                                    joint_l_f_angle = -(2048 - (int)(2048.0 * atan((distance_from_center / (BODY_LENGTH / sqrt(2.0)) + 1.0) / PI)));\n                                    joint_r_f_angle = 0;\n                                    break;\n       case RRIGHT_PLEFT_BACKWARD:  wheel_l_r_vel = (int)(velocity * (distance_from_center + BODY_LENGTH * sqrt(2.0)) / (distance_from_center + (BODY_LENGTH / sqrt(2.0))));\n                                    wheel_r_r_vel = (int)(velocity * (BODY_LENGTH / sqrt(2.0)) / (cos(atan((distance_from_center / (BODY_LENGTH / sqrt(2.0)) + 1.0))) * (distance_from_center + (BODY_LENGTH / sqrt(2.0)))));\n                                    wheel_l_f_vel = (int)(velocity * (BODY_LENGTH / sqrt(2.0)) / (cos(atan((distance_from_center / (BODY_LENGTH / sqrt(2.0)) + 1.0))) * (distance_from_center + (BODY_LENGTH / sqrt(2.0)))));\n                                    wheel_r_f_vel = -(int)(velocity * distance_from_center / (distance_from_center + (BODY_LENGTH / sqrt(2.0))));\n                                    joint_l_r_angle = 0;\n                                    joint_r_r_angle = (2048 - (int)(2048.0 * atan((distance_from_center / (BODY_LENGTH / sqrt(2.0)) + 1.0) / PI)));\n                                    joint_l_f_angle = -(2048 - (int)(2048.0 * atan((distance_from_center / (BODY_LENGTH / sqrt(2.0)) + 1.0) / PI)));\n                                    joint_r_f_angle = 0;\n                                    break;\n       case RLEFT_PRIGHT_FORWARD:   wheel_l_r_vel = (int)(velocity * (BODY_LENGTH / sqrt(2.0)) / (cos(atan((distance_from_center / (BODY_LENGTH / sqrt(2.0)) + 1.0))) * (distance_from_center + (BODY_LENGTH / sqrt(2.0)))));\n                                    wheel_r_r_vel = (int)(velocity * (distance_from_center + BODY_LENGTH * sqrt(2.0)) / (distance_from_center + (BODY_LENGTH / sqrt(2.0))));\n                                    wheel_l_f_vel = -(int)(velocity * distance_from_center / (distance_from_center + (BODY_LENGTH / sqrt(2.0))));\n                                    wheel_r_f_vel = (int)(velocity * (BODY_LENGTH / sqrt(2.0)) / (cos(atan((distance_from_center / (BODY_LENGTH / sqrt(2.0)) + 1.0))) * (distance_from_center + (BODY_LENGTH / sqrt(2.0)))));\n                                    joint_l_r_angle = -(2048 - (int)(2048.0 * atan((distance_from_center / (BODY_LENGTH / sqrt(2.0)) + 1.0) / PI)));\n                                    joint_r_r_angle = 0;\n                                    joint_l_f_angle = 0;\n                                    joint_r_f_angle = (2048 - (int)(2048.0 * atan((distance_from_center / (BODY_LENGTH / sqrt(2.0)) + 1.0) / PI)));\n                                    break;\n       case RLEFT_PRIGHT_BACKWARD:  wheel_l_r_vel = (int)(velocity * distance_from_center / (distance_from_center + (BODY_LENGTH / sqrt(2.0))));\n                                    wheel_r_r_vel = -(int)(velocity * (BODY_LENGTH / sqrt(2.0)) / (cos(atan((distance_from_center / (BODY_LENGTH / sqrt(2.0)) + 1.0))) * (distance_from_center + (BODY_LENGTH / sqrt(2.0)))));\n                                    wheel_l_f_vel = -(int)(velocity * (BODY_LENGTH / sqrt(2.0)) / (cos(atan((distance_from_center / (BODY_LENGTH / sqrt(2.0)) + 1.0))) * (distance_from_center + (BODY_LENGTH / sqrt(2.0)))));\n                                    wheel_r_f_vel = -(int)(velocity * (distance_from_center + BODY_LENGTH * sqrt(2.0)) / (distance_from_center + (BODY_LENGTH / sqrt(2.0))));\n                                    joint_l_r_angle = 0;\n                                    joint_r_r_angle = -(2048 - (int)(2048.0 * atan((distance_from_center / (BODY_LENGTH / sqrt(2.0)) + 1.0) / PI)));\n                                    joint_l_f_angle = (2048 - (int)(2048.0 * atan((distance_from_center / (BODY_LENGTH / sqrt(2.0)) + 1.0) / PI)));\n                                    joint_r_f_angle = 0;\n                                    break;\n       case RRIGHT_PRIGHT_FORWARD:  wheel_l_r_vel = -(int)(velocity * (BODY_LENGTH / sqrt(2.0)) / (cos(atan((distance_from_center / (BODY_LENGTH / sqrt(2.0)) + 1.0))) * (distance_from_center + (BODY_LENGTH / sqrt(2.0)))));\n                                    wheel_r_r_vel = (int)(velocity * distance_from_center / (distance_from_center + (BODY_LENGTH / sqrt(2.0))));\n                                    wheel_l_f_vel = -(int)(velocity * (distance_from_center + BODY_LENGTH * sqrt(2.0)) / (distance_from_center + (BODY_LENGTH / sqrt(2.0))));\n                                    wheel_r_f_vel = -(int)(velocity * (BODY_LENGTH / sqrt(2.0)) / (cos(atan((distance_from_center / (BODY_LENGTH / sqrt(2.0)) + 1.0))) * (distance_from_center + (BODY_LENGTH / sqrt(2.0)))));\n                                    joint_l_r_angle = (2048 - (int)(2048.0 * atan((distance_from_center / (BODY_LENGTH / sqrt(2.0)) + 1.0) / PI)));\n                                    joint_r_r_angle = 0;\n                                    joint_l_f_angle = 0;\n                                    joint_r_f_angle = -(2048 - (int)(2048.0 * atan((distance_from_center / (BODY_LENGTH / sqrt(2.0)) + 1.0) / PI)));\n                                    break;\n       case RRIGHT_PRIGHT_BACKWARD: wheel_l_r_vel = (int)(velocity * (distance_from_center + BODY_LENGTH * sqrt(2.0)) / (distance_from_center + (BODY_LENGTH / sqrt(2.0))));\n                                    wheel_r_r_vel = (int)(velocity * (BODY_LENGTH / sqrt(2.0)) / (cos(atan((distance_from_center / (BODY_LENGTH / sqrt(2.0)) + 1.0))) * (distance_from_center + (BODY_LENGTH / sqrt(2.0)))));\n                                    wheel_l_f_vel = (int)(velocity * (BODY_LENGTH / sqrt(2.0)) / (cos(atan((distance_from_center / (BODY_LENGTH / sqrt(2.0)) + 1.0))) * (distance_from_center + (BODY_LENGTH / sqrt(2.0)))));\n                                    wheel_r_f_vel = -(int)(velocity * distance_from_center / (distance_from_center + (BODY_LENGTH / sqrt(2.0))));\n                                    joint_l_r_angle = 0;\n                                    joint_r_r_angle = (2048 - (int)(2048.0 * atan((distance_from_center / (BODY_LENGTH / sqrt(2.0)) + 1.0) / PI)));\n                                    joint_l_f_angle = -(2048 - (int)(2048.0 * atan((distance_from_center / (BODY_LENGTH / sqrt(2.0)) + 1.0) / PI)));\n                                    joint_r_f_angle = 0;\n                                    break;\n\n       default:                     wheel_l_r_vel = 0; wheel_r_r_vel = 0; wheel_l_f_vel = 0; wheel_r_f_vel = 0;\n                                    break;\n     }\n   }\n\n   int showMode()\n   {\n     return (int)mobile_mode;\n   }\n\n   int32_t* setJointAngle()\n   {\n     if (joint_l_r_angle < -1024) joint_l_r_angle = -1024;\n     else if (joint_l_r_angle > 1024) joint_l_r_angle = 1024;\n     if (joint_r_r_angle < -1024) joint_r_r_angle = -1024;\n     else if (joint_r_r_angle > 1024) joint_r_r_angle = 1024;\n     if (joint_l_f_angle < -1024) joint_l_f_angle = -1024;\n     else if (joint_l_f_angle > 1024) joint_l_f_angle = 1024;\n     if (joint_r_f_angle < -1024) joint_r_f_angle = -1024;\n     else if (joint_r_f_angle > 1024) joint_r_f_angle = 1024;\n\n     joint_angle[0] = joint_l_r_angle + 2048;\n     joint_angle[1] = joint_r_r_angle + 2048;\n     joint_angle[2] = joint_l_f_angle + 2048;\n     joint_angle[3] = joint_r_f_angle + 2048;\n\n    //  joint_angle[0] = JOINT_L_R;\n    //  joint_angle[1] = joint_l_r_angle + 2048;\n    //  joint_angle[2] = JOINT_R_R;\n    //  joint_angle[3] = joint_r_r_angle + 2048;\n    //  joint_angle[4] = JOINT_L_F;\n    //  joint_angle[5] = joint_l_f_angle + 2048;\n    //  joint_angle[6] = JOINT_R_F;\n    //  joint_angle[7] = joint_r_f_angle + 2048;\n\n     return joint_angle;\n   }\n\n   int32_t* setWheelVel()\n   {\n     wheel_vel[0] = wheel_l_r_vel;\n     wheel_vel[1] = wheel_r_r_vel;\n     wheel_vel[2] = wheel_l_f_vel;\n     wheel_vel[3] = wheel_r_f_vel;\n\n    //  wheel_vel[0] = WHEEL_L_R;\n    //  wheel_vel[1] = wheel_l_r_vel;\n    //  wheel_vel[2] = WHEEL_R_R;\n    //  wheel_vel[3] = wheel_r_r_vel;\n    //  wheel_vel[4] = WHEEL_L_F;\n    //  wheel_vel[5] = wheel_l_f_vel;\n    //  wheel_vel[6] = WHEEL_R_F;\n    //  wheel_vel[7] = wheel_r_f_vel;\n\n     return wheel_vel;\n   }\n};"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_conveyor/turtlebot3_conveyor.ino",
    "content": "#include \"turtlebot3_conveyor.h\"\n#include \"turtlebot3_conveyor_motor_driver.h\"\n\n#define LOOP_TIME_SEC 0.010f\n\nRC100 rc100;\nDynamixelStatus conveyor;\nTurtlebot3MotorDriver motor_driver;\n\nuint8_t conveyor_joint[4] = {JOINT_L_R, JOINT_R_R, JOINT_L_F, JOINT_R_F};\nuint8_t conveyor_wheel[4] = {WHEEL_L_R, WHEEL_R_R, WHEEL_L_F, WHEEL_R_F};\n\nvoid setup()\n{\n  Serial.begin(57600);\n  // while(!Serial);\n\n  rc100.begin(1);\n  motor_driver.init();\n}\n\nvoid loop()\n{\n  static uint32_t previous_time = 0;\n  uint32_t present_time = millis();\n\n  getRC100Data();\n\n  if((present_time - previous_time) >= (LOOP_TIME_SEC * 1000))\n  {\n    motor_driver.controlJoints(conveyor.setJointAngle());\n    motor_driver.controlWheels(conveyor.setWheelVel());\n\n    previous_time = millis();\n  } \n}\n\nvoid getRC100Data()\n{\n  if (rc100.available())\n  {    \n    int rcData = rc100.readData();\n\n    conveyor.getDirection(rcData);\n    delay(1);\n\n    conveyor.setParams();\n  }\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_conveyor/turtlebot3_conveyor_motor_driver.cpp",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#include \"turtlebot3_conveyor_motor_driver.h\"\n\nTurtlebot3MotorDriver::Turtlebot3MotorDriver()\n: baudrate_(BAUDRATE),\n  protocol_version_(PROTOCOL_VERSION)\n{\n}\n\nTurtlebot3MotorDriver::~Turtlebot3MotorDriver()\n{\n  closeDynamixel();\n}\n\nbool Turtlebot3MotorDriver::init(void)\n{\n  portHandler_   = dynamixel::PortHandler::getPortHandler(DEVICENAME);\n  packetHandler_ = dynamixel::PacketHandler::getPacketHandler(PROTOCOL_VERSION);\n\n  // Open port\n  if (portHandler_->openPort())\n  {\n    ERROR_PRINT(\"Port is opened\");\n  }\n  else\n  {\n    ERROR_PRINT(\"Port couldn't be opened\");\n\n    return false;\n  }\n\n  // Set port baudrate\n  if (portHandler_->setBaudRate(baudrate_))\n  {\n    ERROR_PRINT(\"Baudrate is set\");\n  }\n  else\n  {\n    ERROR_PRINT(\"Baudrate couldn't be set\");\n\n    return false;\n  }\n\n  // Enable Dynamixel Torque\n  setTorque(WHEEL_L_R, true);\n  setTorque(WHEEL_R_R, true);\n  setTorque(WHEEL_L_F, true);\n  setTorque(WHEEL_R_F, true);\n\n  setTorque(JOINT_L_R, true);\n  setTorque(JOINT_R_R, true);\n  setTorque(JOINT_L_F, true);\n  setTorque(JOINT_R_F, true);\n\n  groupSyncWriteVelocity_ = new dynamixel::GroupSyncWrite(portHandler_, packetHandler_, ADDR_X_GOAL_VELOCITY, LEN_X_GOAL_VELOCITY);\n  groupSyncWritePosition_ = new dynamixel::GroupSyncWrite(portHandler_, packetHandler_, ADDR_X_GOAL_POSITION, LEN_X_GOAL_POSITION);\n\n  return true;\n}\n\nbool Turtlebot3MotorDriver::setTorque(uint8_t id, bool onoff)\n{\n  uint8_t dxl_error = 0;\n  int dxl_comm_result = COMM_TX_FAIL;\n\n  dxl_comm_result = packetHandler_->write1ByteTxRx(portHandler_, id, ADDR_X_TORQUE_ENABLE, onoff, &dxl_error);\n  if(dxl_comm_result != COMM_SUCCESS)\n  {\n    packetHandler_->getTxRxResult(dxl_comm_result);\n  }\n  else if(dxl_error != 0)\n  {\n    packetHandler_->getRxPacketError(dxl_error);\n  }\n}\n\nvoid Turtlebot3MotorDriver::closeDynamixel(void)\n{\n  // Disable Dynamixel Torque\n  setTorque(WHEEL_L_R, false);\n  setTorque(WHEEL_R_R, false);\n  setTorque(WHEEL_L_F, false);\n  setTorque(WHEEL_R_F, false);\n\n  setTorque(JOINT_L_R, false);\n  setTorque(JOINT_R_R, false);\n  setTorque(JOINT_L_F, false);\n  setTorque(JOINT_R_F, false);\n\n  // Close port\n  portHandler_->closePort();\n}\n\nbool Turtlebot3MotorDriver::controlJoints(int32_t *value)\n{\n  bool dxl_addparam_result_;\n  int8_t dxl_comm_result_;\n\n  dxl_addparam_result_ = groupSyncWritePosition_->addParam(JOINT_L_R, (uint8_t*)&value[0]);\n  if (dxl_addparam_result_ != true)\n    return false;\n\n  dxl_addparam_result_ = groupSyncWritePosition_->addParam(JOINT_R_R, (uint8_t*)&value[1]);\n  if (dxl_addparam_result_ != true)\n    return false;\n\n  dxl_addparam_result_ = groupSyncWritePosition_->addParam(JOINT_L_F, (uint8_t*)&value[2]);\n  if (dxl_addparam_result_ != true)\n    return false;\n\n  dxl_addparam_result_ = groupSyncWritePosition_->addParam(JOINT_R_F, (uint8_t*)&value[3]);\n  if (dxl_addparam_result_ != true)\n    return false;\n\n  dxl_comm_result_ = groupSyncWritePosition_->txPacket();\n  if (dxl_comm_result_ != COMM_SUCCESS)\n  {\n    packetHandler_->getTxRxResult(dxl_comm_result_);\n    return false;\n  }\n\n  groupSyncWritePosition_->clearParam();\n  return true;\n}\n\nbool Turtlebot3MotorDriver::controlWheels(int32_t *value)\n{\n  bool dxl_addparam_result_;\n  int8_t dxl_comm_result_;\n\n  dxl_addparam_result_ = groupSyncWriteVelocity_->addParam(WHEEL_L_R, (uint8_t*)&value[0]);\n  if (dxl_addparam_result_ != true)\n    return false;\n\n  dxl_addparam_result_ = groupSyncWriteVelocity_->addParam(WHEEL_R_R, (uint8_t*)&value[1]);\n  if (dxl_addparam_result_ != true)\n    return false;\n\n  dxl_addparam_result_ = groupSyncWriteVelocity_->addParam(WHEEL_L_F, (uint8_t*)&value[2]);\n  if (dxl_addparam_result_ != true)\n    return false;\n\n  dxl_addparam_result_ = groupSyncWriteVelocity_->addParam(WHEEL_R_F, (uint8_t*)&value[3]);\n  if (dxl_addparam_result_ != true)\n    return false;\n\n  dxl_comm_result_ = groupSyncWriteVelocity_->txPacket();\n  if (dxl_comm_result_ != COMM_SUCCESS)\n  {\n    packetHandler_->getTxRxResult(dxl_comm_result_);\n    return false;\n  }\n\n  groupSyncWriteVelocity_->clearParam();\n  return true;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_conveyor/turtlebot3_conveyor_motor_driver.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#ifndef TURTLEBOT3_CONVEYOR_MOTOR_DRIVER_H_\n#define TURTLEBOT3_CONVEYOR_MOTOR_DRIVER_H_\n\n#include <DynamixelSDK.h>\n\n// Control table address (Dynamixel X-series)\n#define ADDR_X_TORQUE_ENABLE            64\n#define ADDR_X_GOAL_VELOCITY            104\n#define ADDR_X_PROFILE_ACCELERATION     108\n#define ADDR_X_PROFILE_VELOCITY         112\n#define ADDR_X_GOAL_POSITION            116\n#define ADDR_X_REALTIME_TICK            120\n#define ADDR_X_PRESENT_VELOCITY         128\n#define ADDR_X_PRESENT_POSITION         132\n\n// Limit values (XM430-W210-T)\n#define LIMIT_X_MAX_VELOCITY            240\n\n// Data Byte Length\n#define LEN_X_TORQUE_ENABLE             1\n#define LEN_X_GOAL_VELOCITY             4\n#define LEN_X_GOAL_POSITION             4\n#define LEN_X_REALTIME_TICK             2\n#define LEN_X_PRESENT_VELOCITY          4\n#define LEN_X_PRESENT_POSITION          4\n\n#define PROTOCOL_VERSION                2.0     // Dynamixel protocol version 2.0\n\n#define WHEEL_L_R 1\n#define WHEEL_R_R 2\n#define WHEEL_L_F 3\n#define WHEEL_R_F 4\n\n#define JOINT_L_R 5\n#define JOINT_R_R 6\n#define JOINT_L_F 7\n#define JOINT_R_F 8\n\n#define BAUDRATE                        1000000 // baud rate of Dynamixel\n#define DEVICENAME                      \"\"      // no need setting on OpenCR\n\n#define TORQUE_ENABLE                   1       // Value for enabling the torque\n#define TORQUE_DISABLE                  0       // Value for disabling the torque\n\nclass Turtlebot3MotorDriver\n{\n public:\n  Turtlebot3MotorDriver();\n  ~Turtlebot3MotorDriver();\n  bool init(void);\n  void closeDynamixel(void);\n  bool setTorque(uint8_t id, bool onoff);\n  bool setProfileAcceleration(uint8_t id, uint32_t value);\n  bool setProfileVelocity(uint8_t id, uint32_t value);\n  bool controlJoints(int32_t *value);\n  bool controlWheels(int32_t *value);\n\n\n private:\n  uint32_t baudrate_;\n  float  protocol_version_;\n\n  dynamixel::PortHandler *portHandler_;\n  dynamixel::PacketHandler *packetHandler_;\n\n  dynamixel::GroupSyncWrite *groupSyncWriteVelocity_;\n  dynamixel::GroupSyncWrite *groupSyncWritePosition_;\n};\n\n#endif // TURTLEBOT3_CONVEYOR_MOTOR_DRIVER_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_mecanum/turtlebot3_mecanum.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#include <math.h>\n\n#include <RC100.h>\n\n#include \"turtlebot3_mecanum_motor_driver.h\"\n\n#define DEBUG\n\n#define WHEEL_RADIUS                    0.03      // meter\n#define WHEEL_SEPARATION_X              0.1005    // 170mm/2 + 31mm/2\n#define WHEEL_SEPARATION_Y              0.085     // 200mm/2 - 30mm/2\n#define DISTANCE_CENTER_TO_WHEEL        0.165     // meter\n\n#define ENCODER_MIN                     -2147483648     // raw\n#define ENCODER_MAX                     2147483648      // raw\n\n#define RPM_CONSTANT_VALUE              0.229\n\n#define CONTROL_PERIOD                  8000\n\n#define MAX_LINEAR_VELOCITY             0.22   // m/s\n#define MAX_ANGULAR_VELOCITY            2.84   // rad/s\n#define VELOCITY_LINEAR_X               0.01   // m/s\n#define VELOCITY_LINEAR_Y               0.01   // m/s\n#define VELOCITY_ANGULAR_Z              0.1    // rad/s\n#define SCALE_VELOCITY_LINEAR_X         1\n#define SCALE_VELOCITY_LINEAR_Y         1\n#define SCALE_VELOCITY_ANGULAR_Z        1\n\n#define MECANUMWHEEL_NUM                4\n#define LIMIT_X_MAX_VALUE               480\n\n#define DEG2RAD(x)                      (x * 0.01745329252)  // *PI/180\n#define RAD2DEG(x)                      (x * 57.2957795131)  // *180/PI\n\nvoid receiveRemoteControlData(void);\nvoid controlMotorSpeed(void);\nvoid controlMecanum();\n\n// Ref : H.Taheri, B.Qiao, N.Ghaeminezhad, \"Kinematic Model of a Four Mecanum Wheeled Mobile Robot\",\n//       International Journal of Computer Applications, 3 March 2015\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_mecanum/turtlebot3_mecanum.ino",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#include \"turtlebot3_mecanum.h\"\n\n/*******************************************************************************\n* Declaration for Hardware Timer (Interrupt control)\n*******************************************************************************/\nHardwareTimer Timer(TIMER_CH1);\n\n/*******************************************************************************\n* Declaration for RC100 remote conroller\n*******************************************************************************/\nRC100 remote_controller;\ndouble const_cmd_vel    = 0.2;\n\n/*******************************************************************************\n* Declaration for motor\n*******************************************************************************/\nTurtlebot3MotorDriver motor_driver;\n\ndouble linear_x                = 0.0;\ndouble linear_y                = 0.0;\ndouble angular_z               = 0.0;\ndouble goal_linear_x_velocity  = 0.0;\ndouble goal_linear_y_velocity  = 0.0;\ndouble goal_angular_velocity   = 0.0;\n\nvoid setup()\n{\n  // Setting for Dynamixel motors\n  motor_driver.init();\n\n  // Setting for RC100 remote control and cmd_vel\n  remote_controller.begin(1);  //57600bps for RC100\n\n  pinMode(13, OUTPUT);\n\n  SerialBT2.begin(57600);\n\n  // Start Dynamixel Control Interrupt\n  startDynamixelControlInterrupt();\n}\n\nvoid loop()\n{\n  receiveRemoteControl();\n}\n\nvoid startDynamixelControlInterrupt()\n{\n  Timer.pause();\n  Timer.setPeriod(CONTROL_PERIOD);           // in microseconds\n  Timer.attachInterrupt(controlMecanum);\n  Timer.refresh();\n  Timer.resume();\n}\n\n/*******************************************************************************\n* Receive RC100 remote controller data\n*******************************************************************************/\nvoid receiveRemoteControl(void)\n{\n  int received_data = 0;\n\n  if (remote_controller.available())\n  {\n    received_data = remote_controller.readData();\n\n    if (received_data & RC100_BTN_U)\n    {\n      linear_x  += VELOCITY_LINEAR_X * SCALE_VELOCITY_LINEAR_X;\n    }\n    else if (received_data & RC100_BTN_D)\n    {\n      linear_x  -= VELOCITY_LINEAR_X * SCALE_VELOCITY_LINEAR_X;\n    }\n\n    if (received_data & RC100_BTN_L)\n    {\n      linear_y -= VELOCITY_LINEAR_Y * SCALE_VELOCITY_LINEAR_Y;\n    }\n    else if (received_data & RC100_BTN_R)\n    {\n      linear_y += VELOCITY_LINEAR_Y * SCALE_VELOCITY_LINEAR_Y;\n    }\n\n    if (received_data & RC100_BTN_1)\n    {\n\n    }\n    else if (received_data & RC100_BTN_2)\n    {\n      angular_z += VELOCITY_ANGULAR_Z * SCALE_VELOCITY_ANGULAR_Z;\n    }\n    else if (received_data & RC100_BTN_3)\n    {\n\n    }\n    else if (received_data & RC100_BTN_4)\n    {\n      angular_z -= VELOCITY_ANGULAR_Z * SCALE_VELOCITY_ANGULAR_Z;\n    }\n\n    if (received_data & RC100_BTN_6)\n    {\n      linear_x  = const_cmd_vel;\n      linear_y  = 0.0;\n      angular_z = 0.0;\n    }\n    else if (received_data & RC100_BTN_5)\n    {\n      linear_x  = 0.0;\n      linear_y  = 0.0;\n      angular_z = 0.0;\n    }\n\n    if (linear_x > MAX_LINEAR_VELOCITY)\n    {\n      linear_x = MAX_LINEAR_VELOCITY;\n    }\n\n    if (angular_z > MAX_ANGULAR_VELOCITY)\n    {\n      angular_z = MAX_ANGULAR_VELOCITY;\n    }\n\n    goal_linear_x_velocity  = linear_x;\n    goal_linear_y_velocity  = linear_y;\n    goal_angular_velocity   = angular_z;\n  }\n}\n\n/*******************************************************************************\n* Control mecanum speed\n*******************************************************************************/\nvoid controlMecanum()\n{\n  bool dxl_comm_result = false;\n\n  int64_t wheel_value[MECANUMWHEEL_NUM] = {0, 0, 0, 0};\n  double wheel_angular_velocity[MECANUMWHEEL_NUM] = {0.0, 0.0, 0.0, 0.0};\n\n  wheel_angular_velocity[0] = (1/WHEEL_RADIUS) * (goal_linear_x_velocity - goal_linear_y_velocity - (WHEEL_SEPARATION_X + WHEEL_SEPARATION_Y) * goal_angular_velocity);\n  wheel_angular_velocity[1] = (1/WHEEL_RADIUS) * (goal_linear_x_velocity + goal_linear_y_velocity + (WHEEL_SEPARATION_X + WHEEL_SEPARATION_Y) * goal_angular_velocity);\n  wheel_angular_velocity[2] = (1/WHEEL_RADIUS) * (goal_linear_x_velocity + goal_linear_y_velocity - (WHEEL_SEPARATION_X + WHEEL_SEPARATION_Y) * goal_angular_velocity);\n  wheel_angular_velocity[3] = (1/WHEEL_RADIUS) * (goal_linear_x_velocity - goal_linear_y_velocity + (WHEEL_SEPARATION_X + WHEEL_SEPARATION_Y) * goal_angular_velocity);\n\n  for (int id = 0; id < MECANUMWHEEL_NUM; id++)\n  {\n    wheel_value[id] = wheel_angular_velocity[id] * 9.54 / RPM_CONSTANT_VALUE;\n\n    if (wheel_value[id] > LIMIT_X_MAX_VALUE)       wheel_value[id] =  LIMIT_X_MAX_VALUE;\n    else if (wheel_value[id] < -LIMIT_X_MAX_VALUE) wheel_value[id] = -LIMIT_X_MAX_VALUE;\n  }\n\n#ifdef DEBUG\n  Serial.print(\"Vx : \");  Serial.print(goal_linear_x_velocity);\n  Serial.print(\" Vy : \"); Serial.print(goal_linear_y_velocity);\n  Serial.print(\" W : \"); Serial.println(goal_angular_velocity);\n#endif\n\n  dxl_comm_result = motor_driver.controlMotor((int64_t)wheel_value[0], (int64_t)wheel_value[1], (int64_t)wheel_value[2], (int64_t)wheel_value[3]);\n  if (dxl_comm_result == false)\n    return;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_mecanum/turtlebot3_mecanum_motor_driver.cpp",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#include \"turtlebot3_mecanum_motor_driver.h\"\n\nTurtlebot3MotorDriver::Turtlebot3MotorDriver()\n: baudrate_(BAUDRATE),\n  protocol_version_(PROTOCOL_VERSION),\n  left_rear_wheel_id_(DXL_LEFT_REAR_ID), right_rear_wheel_id_(DXL_RIGHT_REAR_ID),\n  left_front_wheel_id_(DXL_LEFT_FRONT_ID), right_front_wheel_id_(DXL_RIGHT_FRONT_ID)\n{\n}\n\nTurtlebot3MotorDriver::~Turtlebot3MotorDriver()\n{\n  closeDynamixel();\n}\n\nbool Turtlebot3MotorDriver::init(void)\n{\n  portHandler_   = dynamixel::PortHandler::getPortHandler(DEVICENAME);\n  packetHandler_ = dynamixel::PacketHandler::getPacketHandler(PROTOCOL_VERSION);\n\n  // Open port\n  if (portHandler_->openPort())\n  {\n    ERROR_PRINT(\"Port is opened\");\n  }\n  else\n  {\n    ERROR_PRINT(\"Port couldn't be opened\");\n\n    return false;\n  }\n\n  // Set port baudrate\n  if (portHandler_->setBaudRate(baudrate_))\n  {\n    ERROR_PRINT(\"Baudrate is set\");\n  }\n  else\n  {\n    ERROR_PRINT(\"Baudrate couldn't be set\");\n\n    return false;\n  }\n\n  // Enable Dynamixel Torque\n  setTorque(left_rear_wheel_id_, true);\n  setTorque(right_rear_wheel_id_, true);\n  setTorque(left_front_wheel_id_, true);\n  setTorque(right_front_wheel_id_, true);\n\n  groupSyncWriteVelocity_ = new dynamixel::GroupSyncWrite(portHandler_, packetHandler_, ADDR_X_GOAL_VELOCITY, LEN_X_GOAL_VELOCITY);\n\n  return true;\n}\n\nbool Turtlebot3MotorDriver::setTorque(uint8_t id, bool onoff)\n{\n  uint8_t dxl_error = 0;\n  int dxl_comm_result = COMM_TX_FAIL;\n\n  dxl_comm_result = packetHandler_->write1ByteTxRx(portHandler_, id, ADDR_X_TORQUE_ENABLE, onoff, &dxl_error);\n  if(dxl_comm_result != COMM_SUCCESS)\n  {\n    packetHandler_->getTxRxResult(dxl_comm_result);\n  }\n  else if(dxl_error != 0)\n  {\n    packetHandler_->getRxPacketError(dxl_error);\n  }\n}\n\nvoid Turtlebot3MotorDriver::closeDynamixel(void)\n{\n  // Disable Dynamixel Torque\n  setTorque(left_rear_wheel_id_, false);\n  setTorque(right_rear_wheel_id_, false);\n  setTorque(left_front_wheel_id_, false);\n  setTorque(right_front_wheel_id_, false);\n\n  // Close port\n  portHandler_->closePort();\n}\n\nbool Turtlebot3MotorDriver::controlMotor(int64_t left_rear_wheel_value, int64_t right_rear_wheel_value, int64_t left_front_wheel_value, int64_t right_front_wheel_value)\n{\n  bool dxl_addparam_result_;\n  int8_t dxl_comm_result_;\n\n  dxl_addparam_result_ = groupSyncWriteVelocity_->addParam(left_rear_wheel_id_, (uint8_t*)&left_rear_wheel_value);\n  if (dxl_addparam_result_ != true)\n    return false;\n\n  dxl_addparam_result_ = groupSyncWriteVelocity_->addParam(right_rear_wheel_id_, (uint8_t*)&right_rear_wheel_value);\n  if (dxl_addparam_result_ != true)\n    return false;\n\n  dxl_addparam_result_ = groupSyncWriteVelocity_->addParam(left_front_wheel_id_, (uint8_t*)&left_front_wheel_value);\n  if (dxl_addparam_result_ != true)\n    return false;\n\n  dxl_addparam_result_ = groupSyncWriteVelocity_->addParam(right_front_wheel_id_, (uint8_t*)&right_front_wheel_value);\n  if (dxl_addparam_result_ != true)\n    return false;\n\n  dxl_comm_result_ = groupSyncWriteVelocity_->txPacket();\n  if (dxl_comm_result_ != COMM_SUCCESS)\n  {\n    packetHandler_->getTxRxResult(dxl_comm_result_);\n    return false;\n  }\n\n  groupSyncWriteVelocity_->clearParam();\n  return true;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_mecanum/turtlebot3_mecanum_motor_driver.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#ifndef TURTLEBOT3_MECANUM_MOTOR_DRIVER_H_\n#define TURTLEBOT3_MECANUM_MOTOR_DRIVER_H_\n\n#include <DynamixelSDK.h>\n\n// Control table address (Dynamixel X-series)\n#define ADDR_X_TORQUE_ENABLE            64\n#define ADDR_X_GOAL_VELOCITY            104\n#define ADDR_X_PROFILE_ACCELERATION     108\n#define ADDR_X_PROFILE_VELOCITY         112\n#define ADDR_X_GOAL_POSITION            116\n#define ADDR_X_REALTIME_TICK            120\n#define ADDR_X_PRESENT_VELOCITY         128\n#define ADDR_X_PRESENT_POSITION         132\n\n// Limit values (XM430-W210-T)\n#define LIMIT_X_MAX_VELOCITY            240\n\n// Data Byte Length\n#define LEN_X_TORQUE_ENABLE             1\n#define LEN_X_GOAL_VELOCITY             4\n#define LEN_X_GOAL_POSITION             4\n#define LEN_X_REALTIME_TICK             2\n#define LEN_X_PRESENT_VELOCITY          4\n#define LEN_X_PRESENT_POSITION          4\n\n#define PROTOCOL_VERSION                2.0     // Dynamixel protocol version 2.0\n\n#define DXL_LEFT_REAR_ID                1       // ID of left rear motor\n#define DXL_RIGHT_REAR_ID               2       // ID of right rear motor\n#define DXL_LEFT_FRONT_ID               3       // ID of left front motor\n#define DXL_RIGHT_FRONT_ID              4       // ID of right front motor\n#define BAUDRATE                        1000000 // baud rate of Dynamixel\n#define DEVICENAME                      \"\"      // no need setting on OpenCR\n\n#define TORQUE_ENABLE                   1       // Value for enabling the torque\n#define TORQUE_DISABLE                  0       // Value for disabling the torque\n\nclass Turtlebot3MotorDriver\n{\n public:\n  Turtlebot3MotorDriver();\n  ~Turtlebot3MotorDriver();\n  bool init(void);\n  void closeDynamixel(void);\n  bool setTorque(uint8_t id, bool onoff);\n  bool setProfileAcceleration(uint8_t id, uint32_t value);\n  bool setProfileVelocity(uint8_t id, uint32_t value);\n  bool controlMotor(int64_t left_rear_wheel_value, int64_t right_rear_wheel_value, int64_t left_front_wheel_value, int64_t right_front_wheel_value);\n\n private:\n  uint32_t baudrate_;\n  float  protocol_version_;\n  uint8_t left_rear_wheel_id_, right_rear_wheel_id_;\n  uint8_t left_front_wheel_id_, right_front_wheel_id_;\n\n  dynamixel::PortHandler *portHandler_;\n  dynamixel::PacketHandler *packetHandler_;\n\n  dynamixel::GroupSyncWrite *groupSyncWriteVelocity_;\n};\n\n#endif // TURTLEBOT3_MECANUM_MOTOR_DRIVER_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_monster/turtlebot3_monster.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#include <math.h>\n\n#include <RC100.h>\n\n#include \"turtlebot3_monster_motor_driver.h\"\n\n#define WHEEL_RADIUS                    0.033     // meter\n#define WHEEL_SEPARATION                0.16      // meter (BURGER => 0.16, WAFFLE => 0.287)\n// #define ROBOT_LENGTH                    0.165     // meter\n\n#define WHEEL_POS_FROM_CENTER_X_1       -0.100    // meter\n#define WHEEL_POS_FROM_CENTER_Y_1       -0.128    // meter\n#define WHEEL_POS_FROM_CENTER_X_2       0.100     // meter\n#define WHEEL_POS_FROM_CENTER_Y_2       -0.128    // meter\n#define WHEEL_POS_FROM_CENTER_X_3       -0.100    // meter\n#define WHEEL_POS_FROM_CENTER_Y_3       0.128     // meter\n#define WHEEL_POS_FROM_CENTER_X_4       0.100     // meter\n#define WHEEL_POS_FROM_CENTER_Y_4       0.128     // meter\n\n#define ENCODER_MIN                     -2147483648     // raw\n#define ENCODER_MAX                     2147483648      // raw\n\n#define VELOCITY_CONSTANT_VAULE         1263.632956882  // V = r * w = r * RPM * 0.10472\n                                                        //   = 0.033 * 0.229 * Goal RPM * 0.10472\n                                                        // Goal RPM = V * 1263.632956882\n\n#define CONTROL_PERIOD                  8000\n\n#define MAX_LINEAR_VELOCITY             0.22   // m/s\n#define MAX_ANGULAR_VELOCITY            2.84   // rad/s\n#define VELOCITY_LINEAR_X               0.01   // m/s\n#define VELOCITY_ANGULAR_Z              0.1    // rad/s\n#define SCALE_VELOCITY_LINEAR_X         1\n#define SCALE_VELOCITY_ANGULAR_Z        1\n\n#define DEG2RAD(x)                      (x * 0.01745329252)  // *PI/180\n#define RAD2DEG(x)                      (x * 57.2957795131)  // *180/PI\n\n// Function prototypes\nvoid receiveRemoteControlData(void);\nvoid controlMotorSpeed(void);\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_monster/turtlebot3_monster.ino",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#include \"turtlebot3_monster.h\"\n\n/*******************************************************************************\n* Declaration for Hardware Timer (Interrupt control)\n*******************************************************************************/\nHardwareTimer Timer(TIMER_CH1);\n\n/*******************************************************************************\n* Declaration for RC100 remote conroller\n*******************************************************************************/\nRC100 remote_controller;\ndouble const_cmd_vel    = 0.2;\n\n/*******************************************************************************\n* Declaration for motor\n*******************************************************************************/\nTurtlebot3MotorDriver motor_driver;\n\ndouble linear_x              = 0.0;\ndouble angular_z             = 0.0;\ndouble goal_linear_velocity  = 0.0;\ndouble goal_angular_velocity = 0.0;\n\nvoid setup()\n{\n  // Setting for Dynamixel motors\n  motor_driver.init();\n\n  // Setting for RC100 remote control and cmd_vel\n  remote_controller.begin(1);  //57600bps for RC100\n\n  pinMode(13, OUTPUT);\n\n  SerialBT2.begin(57600);\n\n  // Start Dynamixel Control Interrupt\n  startDynamixelControlInterrupt();\n}\n\nvoid loop()\n{\n  receiveRemoteControlData();\n}\n\nvoid startDynamixelControlInterrupt()\n{\n  Timer.pause();\n  Timer.setPeriod(CONTROL_PERIOD);           // in microseconds\n  Timer.attachInterrupt(controlMonster);\n  Timer.refresh();\n  Timer.resume();\n}\n\n/*******************************************************************************\n* Receive RC100 remote controller data\n*******************************************************************************/\nvoid receiveRemoteControlData(void)\n{\n  int received_data = 0;\n\n  if (remote_controller.available())\n  {\n    received_data = remote_controller.readData();\n\n    if (received_data & RC100_BTN_U)\n    {\n      linear_x  += VELOCITY_LINEAR_X * SCALE_VELOCITY_LINEAR_X;\n    }\n    else if (received_data & RC100_BTN_D)\n    {\n      linear_x  -= VELOCITY_LINEAR_X * SCALE_VELOCITY_LINEAR_X;\n    }\n\n    if (received_data & RC100_BTN_L)\n    {\n      angular_z += VELOCITY_ANGULAR_Z * SCALE_VELOCITY_ANGULAR_Z;\n    }\n    else if (received_data & RC100_BTN_R)\n    {\n      angular_z -= VELOCITY_ANGULAR_Z * SCALE_VELOCITY_ANGULAR_Z;\n    }\n\n    if (received_data & RC100_BTN_1)\n    {\n\n    }\n    else if (received_data & RC100_BTN_2)\n    {\n\n    }\n    else if (received_data & RC100_BTN_3)\n    {\n\n    }\n    else if (received_data & RC100_BTN_4)\n    {\n\n    }\n\n    if (received_data & RC100_BTN_6)\n    {\n      linear_x  = const_cmd_vel;\n      angular_z = 0.0;\n    }\n    else if (received_data & RC100_BTN_5)\n    {\n      linear_x  = 0.0;\n      angular_z = 0.0;\n    }\n\n    if (linear_x > MAX_LINEAR_VELOCITY)\n    {\n      linear_x = MAX_LINEAR_VELOCITY;\n    }\n\n    if (angular_z > MAX_ANGULAR_VELOCITY)\n    {\n      angular_z = MAX_ANGULAR_VELOCITY;\n    }\n\n    goal_linear_velocity  = linear_x;\n    goal_angular_velocity = angular_z;\n  }\n}\n\n/*******************************************************************************\n* Control bike speed\n*******************************************************************************/\nvoid controlMonster()\n{\n  bool dxl_comm_result = false;\n\n  double wheel1_spd_cmd, wheel2_spd_cmd, wheel3_spd_cmd, wheel4_spd_cmd;\n  double lin_vel1, lin_vel2, lin_vel3, lin_vel4;\n\n  double rotation_center;\n\n  wheel1_spd_cmd = goal_linear_velocity - (sqrt(WHEEL_POS_FROM_CENTER_X_1 * WHEEL_POS_FROM_CENTER_X_1 + WHEEL_POS_FROM_CENTER_Y_1 * WHEEL_POS_FROM_CENTER_Y_1) * goal_angular_velocity) * cos(atan(WHEEL_POS_FROM_CENTER_Y_1 / WHEEL_POS_FROM_CENTER_X_1));\n\n  wheel2_spd_cmd = goal_linear_velocity + (sqrt(WHEEL_POS_FROM_CENTER_X_2 * WHEEL_POS_FROM_CENTER_X_2 + WHEEL_POS_FROM_CENTER_Y_2 * WHEEL_POS_FROM_CENTER_Y_2) * goal_angular_velocity) * cos(atan(WHEEL_POS_FROM_CENTER_Y_2 / WHEEL_POS_FROM_CENTER_X_2));\n\n  wheel3_spd_cmd = goal_linear_velocity - (sqrt(WHEEL_POS_FROM_CENTER_X_3 * WHEEL_POS_FROM_CENTER_X_3 + WHEEL_POS_FROM_CENTER_Y_3 * WHEEL_POS_FROM_CENTER_Y_3) * goal_angular_velocity) * cos(atan(WHEEL_POS_FROM_CENTER_Y_3 / WHEEL_POS_FROM_CENTER_X_3));\n\n  wheel4_spd_cmd = goal_linear_velocity + (sqrt(WHEEL_POS_FROM_CENTER_X_4 * WHEEL_POS_FROM_CENTER_X_4 + WHEEL_POS_FROM_CENTER_Y_4 * WHEEL_POS_FROM_CENTER_Y_4) * goal_angular_velocity) * cos(atan(WHEEL_POS_FROM_CENTER_Y_4 / WHEEL_POS_FROM_CENTER_X_4));\n\n  lin_vel1 = wheel1_spd_cmd * VELOCITY_CONSTANT_VAULE;\n  if (lin_vel1 > LIMIT_X_MAX_VELOCITY)\n  {\n    lin_vel1 =  LIMIT_X_MAX_VELOCITY;\n  }\n  else if (lin_vel1 < -LIMIT_X_MAX_VELOCITY)\n  {\n    lin_vel1 = -LIMIT_X_MAX_VELOCITY;\n  }\n\n  lin_vel2 = -1 * wheel2_spd_cmd * VELOCITY_CONSTANT_VAULE;\n  if (lin_vel2 > LIMIT_X_MAX_VELOCITY)\n  {\n    lin_vel2 =  LIMIT_X_MAX_VELOCITY;\n  }\n  else if (lin_vel2 < -LIMIT_X_MAX_VELOCITY)\n  {\n    lin_vel2 = -LIMIT_X_MAX_VELOCITY;\n  }\n\n  lin_vel3 = wheel3_spd_cmd * VELOCITY_CONSTANT_VAULE;\n  if (lin_vel3 > LIMIT_X_MAX_VELOCITY)\n  {\n    lin_vel3 =  LIMIT_X_MAX_VELOCITY;\n  }\n  else if (lin_vel3 < -LIMIT_X_MAX_VELOCITY)\n  {\n    lin_vel3 = -LIMIT_X_MAX_VELOCITY;\n  }\n\n  lin_vel4 = -1 * wheel4_spd_cmd * VELOCITY_CONSTANT_VAULE;\n  if (lin_vel4 > LIMIT_X_MAX_VELOCITY)\n  {\n    lin_vel4 =  LIMIT_X_MAX_VELOCITY;\n  }\n  else if (lin_vel4 < -LIMIT_X_MAX_VELOCITY)\n  {\n    lin_vel4 = -LIMIT_X_MAX_VELOCITY;\n  }\n\n  dxl_comm_result = motor_driver.controlMotor((int64_t)lin_vel1, (int64_t)lin_vel2, (int64_t)lin_vel3, (int64_t)lin_vel4);\n  if (dxl_comm_result == false)\n    return;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_monster/turtlebot3_monster_motor_driver.cpp",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#include \"turtlebot3_monster_motor_driver.h\"\n\nTurtlebot3MotorDriver::Turtlebot3MotorDriver()\n: baudrate_(BAUDRATE),\n  protocol_version_(PROTOCOL_VERSION),\n  left_rear_wheel_id_(DXL_LEFT_REAR_ID), right_rear_wheel_id_(DXL_RIGHT_REAR_ID),\n  left_front_wheel_id_(DXL_LEFT_FRONT_ID), right_front_wheel_id_(DXL_RIGHT_FRONT_ID)\n{\n}\n\nTurtlebot3MotorDriver::~Turtlebot3MotorDriver()\n{\n  closeDynamixel();\n}\n\nbool Turtlebot3MotorDriver::init(void)\n{\n  portHandler_   = dynamixel::PortHandler::getPortHandler(DEVICENAME);\n  packetHandler_ = dynamixel::PacketHandler::getPacketHandler(PROTOCOL_VERSION);\n\n  // Open port\n  if (portHandler_->openPort())\n  {\n    ERROR_PRINT(\"Port is opened\");\n  }\n  else\n  {\n    ERROR_PRINT(\"Port couldn't be opened\");\n\n    return false;\n  }\n\n  // Set port baudrate\n  if (portHandler_->setBaudRate(baudrate_))\n  {\n    ERROR_PRINT(\"Baudrate is set\");\n  }\n  else\n  {\n    ERROR_PRINT(\"Baudrate couldn't be set\");\n\n    return false;\n  }\n\n  // Enable Dynamixel Torque\n  setTorque(left_rear_wheel_id_, true);\n  setTorque(right_rear_wheel_id_, true);\n  setTorque(left_front_wheel_id_, true);\n  setTorque(right_front_wheel_id_, true);\n\n  groupSyncWriteVelocity_ = new dynamixel::GroupSyncWrite(portHandler_, packetHandler_, ADDR_X_GOAL_VELOCITY, LEN_X_GOAL_VELOCITY);\n\n  return true;\n}\n\nbool Turtlebot3MotorDriver::setTorque(uint8_t id, bool onoff)\n{\n  uint8_t dxl_error = 0;\n  int dxl_comm_result = COMM_TX_FAIL;\n\n  dxl_comm_result = packetHandler_->write1ByteTxRx(portHandler_, id, ADDR_X_TORQUE_ENABLE, onoff, &dxl_error);\n  if(dxl_comm_result != COMM_SUCCESS)\n  {\n    packetHandler_->getTxRxResult(dxl_comm_result);\n  }\n  else if(dxl_error != 0)\n  {\n    packetHandler_->getRxPacketError(dxl_error);\n  }\n}\n\nvoid Turtlebot3MotorDriver::closeDynamixel(void)\n{\n  // Disable Dynamixel Torque\n  setTorque(left_rear_wheel_id_, false);\n  setTorque(right_rear_wheel_id_, false);\n  setTorque(left_front_wheel_id_, false);\n  setTorque(right_front_wheel_id_, false);\n\n  // Close port\n  portHandler_->closePort();\n}\n\nbool Turtlebot3MotorDriver::controlMotor(int64_t left_rear_wheel_value, int64_t right_rear_wheel_value, int64_t left_front_wheel_value, int64_t right_front_wheel_value)\n{\n  bool dxl_addparam_result_;\n  int8_t dxl_comm_result_;\n\n  dxl_addparam_result_ = groupSyncWriteVelocity_->addParam(left_rear_wheel_id_, (uint8_t*)&left_rear_wheel_value);\n  if (dxl_addparam_result_ != true)\n    return false;\n\n  dxl_addparam_result_ = groupSyncWriteVelocity_->addParam(right_rear_wheel_id_, (uint8_t*)&right_rear_wheel_value);\n  if (dxl_addparam_result_ != true)\n    return false;\n\n  dxl_addparam_result_ = groupSyncWriteVelocity_->addParam(left_front_wheel_id_, (uint8_t*)&left_front_wheel_value);\n  if (dxl_addparam_result_ != true)\n    return false;\n\n  dxl_addparam_result_ = groupSyncWriteVelocity_->addParam(right_front_wheel_id_, (uint8_t*)&right_front_wheel_value);\n  if (dxl_addparam_result_ != true)\n    return false;\n\n  dxl_comm_result_ = groupSyncWriteVelocity_->txPacket();\n  if (dxl_comm_result_ != COMM_SUCCESS)\n  {\n    packetHandler_->getTxRxResult(dxl_comm_result_);\n    return false;\n  }\n\n  groupSyncWriteVelocity_->clearParam();\n  return true;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_monster/turtlebot3_monster_motor_driver.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#ifndef TURTLEBOT3_MONSTER_MOTOR_DRIVER_H_\n#define TURTLEBOT3_MONSTER_MOTOR_DRIVER_H_\n\n#include <DynamixelSDK.h>\n\n// Control table address (Dynamixel X-series)\n#define ADDR_X_TORQUE_ENABLE            64\n#define ADDR_X_GOAL_VELOCITY            104\n#define ADDR_X_PROFILE_ACCELERATION     108\n#define ADDR_X_PROFILE_VELOCITY         112\n#define ADDR_X_GOAL_POSITION            116\n#define ADDR_X_REALTIME_TICK            120\n#define ADDR_X_PRESENT_VELOCITY         128\n#define ADDR_X_PRESENT_POSITION         132\n\n// Limit values (XM430-W210-T)\n#define LIMIT_X_MAX_VELOCITY            240\n\n// Data Byte Length\n#define LEN_X_TORQUE_ENABLE             1\n#define LEN_X_GOAL_VELOCITY             4\n#define LEN_X_GOAL_POSITION             4\n#define LEN_X_REALTIME_TICK             2\n#define LEN_X_PRESENT_VELOCITY          4\n#define LEN_X_PRESENT_POSITION          4\n\n#define PROTOCOL_VERSION                2.0     // Dynamixel protocol version 2.0\n\n#define DXL_LEFT_REAR_ID                1       // ID of left rear motor\n#define DXL_RIGHT_REAR_ID               2       // ID of right rear motor\n#define DXL_LEFT_FRONT_ID               3       // ID of left front motor\n#define DXL_RIGHT_FRONT_ID              4       // ID of right front motor\n#define BAUDRATE                        1000000 // baud rate of Dynamixel\n#define DEVICENAME                      \"\"      // no need setting on OpenCR\n\n#define TORQUE_ENABLE                   1       // Value for enabling the torque\n#define TORQUE_DISABLE                  0       // Value for disabling the torque\n\nclass Turtlebot3MotorDriver\n{\n public:\n  Turtlebot3MotorDriver();\n  ~Turtlebot3MotorDriver();\n  bool init(void);\n  void closeDynamixel(void);\n  bool setTorque(uint8_t id, bool onoff);\n  bool setProfileAcceleration(uint8_t id, uint32_t value);\n  bool setProfileVelocity(uint8_t id, uint32_t value);\n  bool controlMotor(int64_t left_rear_wheel_value, int64_t right_rear_wheel_value, int64_t left_front_wheel_value, int64_t right_front_wheel_value);\n\n private:\n  uint32_t baudrate_;\n  float  protocol_version_;\n  uint8_t left_rear_wheel_id_, right_rear_wheel_id_;\n  uint8_t left_front_wheel_id_, right_front_wheel_id_;\n\n  dynamixel::PortHandler *portHandler_;\n  dynamixel::PacketHandler *packetHandler_;\n\n  dynamixel::GroupSyncWrite *groupSyncWriteVelocity_;\n};\n\n#endif // TURTLEBOT3_MONSTER_MOTOR_DRIVER_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_omni/turtlebot3_omni.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#include <math.h>\n\n#include <RC100.h>\n\n#include \"turtlebot3_omni_motor_driver.h\"\n\n#define DEBUG\n\n#define WHEEL_RADIUS                    0.03      // meter\n#define WHEEL_SEPARATION_ANGLE          60        // degree\n#define DISTANCE_CENTER_TO_WHEEL        0.122     // meter\n\n#define ENCODER_MIN                     -2147483648     // raw\n#define ENCODER_MAX                     2147483648      // raw\n\n#define RPM_CONSTANT_VALUE              0.229\n\n#define CONTROL_PERIOD                  8000\n\n#define MAX_LINEAR_VELOCITY             0.22   // m/s\n#define MAX_ANGULAR_VELOCITY            2.84   // rad/s\n#define VELOCITY_LINEAR_X               0.01   // m/s\n#define VELOCITY_LINEAR_Y               0.01   // m/s\n#define VELOCITY_ANGULAR_Z              0.1    // rad/s\n#define SCALE_VELOCITY_LINEAR_X         1\n#define SCALE_VELOCITY_LINEAR_Y         1\n#define SCALE_VELOCITY_ANGULAR_Z        1\n\n#define OMNIWHEEL_NUM                   3\n#define LIMIT_X_MAX_VALUE               480\n\n#define DEG2RAD(x)                      (x * 0.01745329252)  // *PI/180\n#define RAD2DEG(x)                      (x * 57.2957795131)  // *180/PI\n\nvoid receiveRemoteControlData(void);\nvoid controlMotorSpeed(void);\nvoid controlOmni();\n\n// Ref : http://www.revistas.unal.edu.co/index.php/ingeinv/article/view/47763/52384\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_omni/turtlebot3_omni.ino",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#include \"turtlebot3_omni.h\"\n\n/*******************************************************************************\n* Declaration for Hardware Timer (Interrupt control)\n*******************************************************************************/\nHardwareTimer Timer(TIMER_CH1);\n\n/*******************************************************************************\n* Declaration for RC100 remote conroller\n*******************************************************************************/\nRC100 remote_controller;\ndouble const_cmd_vel    = 0.2;\n\n/*******************************************************************************\n* Declaration for motor\n*******************************************************************************/\nTurtlebot3MotorDriver motor_driver;\n\ndouble linear_x                = 0.0;\ndouble linear_y                = 0.0;\ndouble angular_z               = 0.0;\ndouble goal_linear_x_velocity  = 0.0;\ndouble goal_linear_y_velocity  = 0.0;\ndouble goal_angular_velocity   = 0.0;\n\nvoid setup()\n{\n  // Setting for Dynamixel motors\n  motor_driver.init();\n\n  // Setting for RC100 remote control and cmd_vel\n  remote_controller.begin(1);  //57600bps for RC100\n\n  pinMode(13, OUTPUT);\n\n  SerialBT2.begin(57600);\n\n  // Start Dynamixel Control Interrupt\n  startDynamixelControlInterrupt();\n}\n\nvoid loop()\n{\n  receiveRemoteControl();\n}\n\nvoid startDynamixelControlInterrupt()\n{\n  Timer.pause();\n  Timer.setPeriod(CONTROL_PERIOD);           // in microseconds\n  Timer.attachInterrupt(controlOmni);\n  Timer.refresh();\n  Timer.resume();\n}\n\n/*******************************************************************************\n* Receive RC100 remote controller data\n*******************************************************************************/\nvoid receiveRemoteControl(void)\n{\n  int received_data = 0;\n\n  if (remote_controller.available())\n  {\n    received_data = remote_controller.readData();\n\n    if (received_data & RC100_BTN_U)\n    {\n      linear_x  += VELOCITY_LINEAR_X * SCALE_VELOCITY_LINEAR_X;\n    }\n    else if (received_data & RC100_BTN_D)\n    {\n      linear_x  -= VELOCITY_LINEAR_X * SCALE_VELOCITY_LINEAR_X;\n    }\n\n    if (received_data & RC100_BTN_L)\n    {\n      linear_y -= VELOCITY_LINEAR_Y * SCALE_VELOCITY_LINEAR_Y;\n    }\n    else if (received_data & RC100_BTN_R)\n    {\n      linear_y += VELOCITY_LINEAR_Y * SCALE_VELOCITY_LINEAR_Y;\n    }\n\n    if (received_data & RC100_BTN_1)\n    {\n\n    }\n    else if (received_data & RC100_BTN_2)\n    {\n      angular_z += VELOCITY_ANGULAR_Z * SCALE_VELOCITY_ANGULAR_Z;\n    }\n    else if (received_data & RC100_BTN_3)\n    {\n\n    }\n    else if (received_data & RC100_BTN_4)\n    {\n      angular_z -= VELOCITY_ANGULAR_Z * SCALE_VELOCITY_ANGULAR_Z;\n    }\n\n    if (received_data & RC100_BTN_6)\n    {\n      linear_x  = const_cmd_vel;\n      linear_y  = 0.0;\n      angular_z = 0.0;\n    }\n    else if (received_data & RC100_BTN_5)\n    {\n      linear_x  = 0.0;\n      linear_y  = 0.0;\n      angular_z = 0.0;\n    }\n\n    if (linear_x > MAX_LINEAR_VELOCITY)\n    {\n      linear_x = MAX_LINEAR_VELOCITY;\n    }\n\n    if (angular_z > MAX_ANGULAR_VELOCITY)\n    {\n      angular_z = MAX_ANGULAR_VELOCITY;\n    }\n\n    goal_linear_x_velocity  = linear_x;\n    goal_linear_y_velocity  = linear_y;\n    goal_angular_velocity   = angular_z;\n  }\n}\n\n/*******************************************************************************\n* Control onmi speed\n*******************************************************************************/\nvoid controlOmni()\n{\n  bool dxl_comm_result = false;\n\n  int64_t wheel_value[OMNIWHEEL_NUM] = {0, 0, 0};\n  double wheel_angular_velocity[OMNIWHEEL_NUM] = {0.0, 0.0, 0.0};\n\n  wheel_angular_velocity[0] = (goal_linear_x_velocity * 0) + (goal_linear_y_velocity * (1 / WHEEL_RADIUS)) + (goal_angular_velocity * (-DISTANCE_CENTER_TO_WHEEL/WHEEL_RADIUS));\n  wheel_angular_velocity[1] = (goal_linear_x_velocity * (sqrt(3) / (2 * WHEEL_RADIUS))) + (goal_linear_y_velocity * (-1 / (2 * WHEEL_RADIUS))) + (goal_angular_velocity * (-DISTANCE_CENTER_TO_WHEEL/WHEEL_RADIUS));\n  wheel_angular_velocity[2] = (goal_linear_x_velocity * (sqrt(3) / (-2 * WHEEL_RADIUS))) + (goal_linear_y_velocity * (-1 / (2 * WHEEL_RADIUS))) + (goal_angular_velocity * (-DISTANCE_CENTER_TO_WHEEL/WHEEL_RADIUS));\n\n  for (int id = 0; id < OMNIWHEEL_NUM; id++)\n  {\n    wheel_value[id] = wheel_angular_velocity[id] * 9.54 /  RPM_CONSTANT_VALUE;\n\n    if (wheel_value[id] > LIMIT_X_MAX_VALUE)       wheel_value[id] =  LIMIT_X_MAX_VALUE;\n    else if (wheel_value[id] < -LIMIT_X_MAX_VALUE) wheel_value[id] = -LIMIT_X_MAX_VALUE;\n  }\n\n#ifdef DEBUG\n  Serial.print(\"Vx : \");  Serial.print(goal_linear_x_velocity);\n  Serial.print(\" Vy : \"); Serial.print(goal_linear_y_velocity);\n  Serial.print(\" W : \"); Serial.println(goal_angular_velocity);\n#endif\n\n  dxl_comm_result = motor_driver.controlMotor((int64_t)wheel_value[0], (int64_t)wheel_value[1], (int64_t)wheel_value[2]);\n  if (dxl_comm_result == false)\n    return;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_omni/turtlebot3_omni_motor_driver.cpp",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#include \"turtlebot3_omni_motor_driver.h\"\n\nTurtlebot3MotorDriver::Turtlebot3MotorDriver()\n: baudrate_(BAUDRATE),\n  protocol_version_(PROTOCOL_VERSION),\n  first_wheel_id_(DXL_FIRST_ID),\n  second_wheel_id_(DXL_SECOND_ID),\n  third_wheel_id_(DXL_THIRD_ID)\n{\n}\n\nTurtlebot3MotorDriver::~Turtlebot3MotorDriver()\n{\n  closeDynamixel();\n}\n\nbool Turtlebot3MotorDriver::init(void)\n{\n  portHandler_   = dynamixel::PortHandler::getPortHandler(DEVICENAME);\n  packetHandler_ = dynamixel::PacketHandler::getPacketHandler(PROTOCOL_VERSION);\n\n  // Open port\n  if (portHandler_->openPort())\n  {\n    ERROR_PRINT(\"Port is opened\");\n  }\n  else\n  {\n    ERROR_PRINT(\"Port couldn't be opened\");\n\n    return false;\n  }\n\n  // Set port baudrate\n  if (portHandler_->setBaudRate(baudrate_))\n  {\n    ERROR_PRINT(\"Baudrate is set\");\n  }\n  else\n  {\n    ERROR_PRINT(\"Baudrate couldn't be set\");\n\n    return false;\n  }\n\n  // Enable Dynamixel Torque\n  setTorque(first_wheel_id_, true);\n  setTorque(second_wheel_id_, true);\n  setTorque(third_wheel_id_, true);\n\n  groupSyncWriteVelocity_ = new dynamixel::GroupSyncWrite(portHandler_, packetHandler_, ADDR_X_GOAL_VELOCITY, LEN_X_GOAL_VELOCITY);\n\n  return true;\n}\n\nbool Turtlebot3MotorDriver::setTorque(uint8_t id, bool onoff)\n{\n  uint8_t dxl_error = 0;\n  int dxl_comm_result = COMM_TX_FAIL;\n\n  dxl_comm_result = packetHandler_->write1ByteTxRx(portHandler_, id, ADDR_X_TORQUE_ENABLE, onoff, &dxl_error);\n  if(dxl_comm_result != COMM_SUCCESS)\n  {\n    packetHandler_->getTxRxResult(dxl_comm_result);\n  }\n  else if(dxl_error != 0)\n  {\n    packetHandler_->getRxPacketError(dxl_error);\n  }\n}\n\nvoid Turtlebot3MotorDriver::closeDynamixel(void)\n{\n  // Disable Dynamixel Torque\n  setTorque(first_wheel_id_, false);\n  setTorque(second_wheel_id_, false);\n  setTorque(third_wheel_id_, false);\n\n  // Close port\n  portHandler_->closePort();\n}\n\nbool Turtlebot3MotorDriver::controlMotor(int64_t first_wheel_value, int64_t second_wheel_value, int64_t third_wheel_value)\n{\n  bool dxl_addparam_result_;\n  int8_t dxl_comm_result_;\n\n  dxl_addparam_result_ = groupSyncWriteVelocity_->addParam(first_wheel_id_, (uint8_t*)&first_wheel_value);\n  if (dxl_addparam_result_ != true)\n    return false;\n\n  dxl_addparam_result_ = groupSyncWriteVelocity_->addParam(second_wheel_id_, (uint8_t*)&second_wheel_value);\n  if (dxl_addparam_result_ != true)\n    return false;\n\n  dxl_addparam_result_ = groupSyncWriteVelocity_->addParam(third_wheel_id_, (uint8_t*)&third_wheel_value);\n  if (dxl_addparam_result_ != true)\n    return false;\n\n  dxl_comm_result_ = groupSyncWriteVelocity_->txPacket();\n  if (dxl_comm_result_ != COMM_SUCCESS)\n  {\n    packetHandler_->getTxRxResult(dxl_comm_result_);\n    return false;\n  }\n\n  groupSyncWriteVelocity_->clearParam();\n  return true;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_omni/turtlebot3_omni_motor_driver.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#ifndef TURTLEBOT3_OMNI_MOTOR_DRIVER_H_\n#define TURTLEBOT3_OMNI_MOTOR_DRIVER_H_\n\n#include <DynamixelSDK.h>\n\n// Control table address (Dynamixel X-series)\n#define ADDR_X_TORQUE_ENABLE            64\n#define ADDR_X_GOAL_VELOCITY            104\n#define ADDR_X_PROFILE_ACCELERATION     108\n#define ADDR_X_PROFILE_VELOCITY         112\n#define ADDR_X_GOAL_POSITION            116\n#define ADDR_X_REALTIME_TICK            120\n#define ADDR_X_PRESENT_VELOCITY         128\n#define ADDR_X_PRESENT_POSITION         132\n\n// Limit values (XM430-W210-T)\n#define LIMIT_X_MAX_VELOCITY            240\n\n// Data Byte Length\n#define LEN_X_TORQUE_ENABLE             1\n#define LEN_X_GOAL_VELOCITY             4\n#define LEN_X_GOAL_POSITION             4\n#define LEN_X_REALTIME_TICK             2\n#define LEN_X_PRESENT_VELOCITY          4\n#define LEN_X_PRESENT_POSITION          4\n\n#define PROTOCOL_VERSION                2.0     // Dynamixel protocol version 2.0\n\n#define DXL_FIRST_ID                    1       // ID of left rear motor\n#define DXL_SECOND_ID                   2       // ID of right rear motor\n#define DXL_THIRD_ID                    3       // ID of left front motor\n#define BAUDRATE                        1000000 // baud rate of Dynamixel\n#define DEVICENAME                      \"\"      // no need setting on OpenCR\n\n#define TORQUE_ENABLE                   1       // Value for enabling the torque\n#define TORQUE_DISABLE                  0       // Value for disabling the torque\n\nclass Turtlebot3MotorDriver\n{\n public:\n  Turtlebot3MotorDriver();\n  ~Turtlebot3MotorDriver();\n  bool init(void);\n  void closeDynamixel(void);\n  bool setTorque(uint8_t id, bool onoff);\n  bool setProfileAcceleration(uint8_t id, uint32_t value);\n  bool setProfileVelocity(uint8_t id, uint32_t value);\n  bool controlMotor(int64_t first_wheel_value, int64_t second_wheel_value, int64_t third_wheel_value);\n\n private:\n  uint32_t baudrate_;\n  float  protocol_version_;\n  uint8_t first_wheel_id_, second_wheel_id_, third_wheel_id_;\n\n  dynamixel::PortHandler *portHandler_;\n  dynamixel::PacketHandler *packetHandler_;\n\n  dynamixel::GroupSyncWrite *groupSyncWriteVelocity_;\n};\n\n#endif // TURTLEBOT3_OMNI_MOTOR_DRIVER_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_realturtlebot/turtlebot3_realturtlebot.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#include <math.h>\n\n#include <RC100.h>\n\n#include \"turtlebot3_realturtlebot_motor_driver.h\"\n\n#define WHEEL_RADIUS                    0.033     // meter\n#define WHEEL_SEPARATION                0.16      // meter (BURGER => 0.16, WAFFLE => 0.287)\n#define ROBOT_LENGTH                    0.165     // meter\n\n#define ENCODER_MIN                     -2147483648     // raw\n#define ENCODER_MAX                     2147483648      // raw\n\n#define VELOCITY_CONSTANT_VAULE         1263.632956882  // V = r * w = r * RPM * 0.10472\n                                                        //   = 0.033 * 0.229 * Goal RPM * 0.10472\n                                                        // Goal RPM = V * 1263.632956882\n\n#define CONTROL_PERIOD                  8000\n\n#define MAX_LINEAR_VELOCITY             0.22   // m/s\n#define MAX_ANGULAR_VELOCITY            2.84   // rad/s\n#define VELOCITY_LINEAR_X               0.01   // m/s\n#define VELOCITY_ANGULAR_Z              0.1    // rad/s\n#define SCALE_VELOCITY_LINEAR_X         1\n#define SCALE_VELOCITY_ANGULAR_Z        1\n\n#define DEG2RAD(x)                      (x * 0.01745329252)  // *PI/180\n#define RAD2DEG(x)                      (x * 57.2957795131)  // *180/PI\n\n// Function prototypes\nvoid receiveRemoteControlData(void);\nvoid controlMotorSpeed(void);\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_realturtlebot/turtlebot3_realturtlebot.ino",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#include \"turtlebot3_realturtlebot.h\"\n#include \"turtlebot3_realturtlebot_motion.h\"\n\n/*******************************************************************************\n* Declaration for Hardware Timer (Interrupt control)\n*******************************************************************************/\nHardwareTimer Timer(TIMER_CH1);\n\n/*******************************************************************************\n* Declaration for RC100 remote conroller\n*******************************************************************************/\nRC100 remote_controller;\n\n/*******************************************************************************\n* Declaration for motor\n*******************************************************************************/\nTurtlebot3MotorDriver motor_driver;\n\nTurtlebotMotion turtlebotMotion;\n\nvoid setup()\n{\n  // Setting for Dynamixel motors\n  motor_driver.init();\n\n  // Setting for RC100 remote control and cmd_vel\n  remote_controller.begin(1);  //57600bps for RC100\n\n  pinMode(13, OUTPUT);\n\n  SerialBT2.begin(57600);\n\n  // Init Motion\n  controlRealTurtleBot();\n}\n\nvoid loop()\n{\n  receiveRemoteControlData();\n}\n\nvoid startDynamixelControlInterrupt()\n{\n  Timer.pause();\n  Timer.setPeriod(CONTROL_PERIOD);           // in microseconds\n  Timer.attachInterrupt(controlRealTurtleBot);\n  Timer.refresh();\n  Timer.resume();\n}\n\n/*******************************************************************************\n* Receive RC100 remote controller data\n*******************************************************************************/\nvoid receiveRemoteControlData(void)\n{\n  int received_data = 0;\n\n  if (remote_controller.available())\n  {\n    received_data = remote_controller.readData();\n\n    turtlebotMotion.getDirection(received_data);\n\n    controlRealTurtleBot();\n\n    remote_controller.begin(1);  // refresh remote controller buffer\n  }\n}\n\n/*******************************************************************************\n* Control Real TurtleBot\n*******************************************************************************/\nvoid controlRealTurtleBot()\n{\n  int pres_pos[8] = {0, };\n  int* goal_pos;\n  double dist[8] = {0.0, };\n  int goal_pos_dist_int[8] = {0, };\n  double goal_pos_dist_db[8] = {0.0, };\n\n  turtlebotMotion.setParams();\n\n  for (int motion_num = 0; motion_num < turtlebotMotion.motion_all_num; motion_num++)\n  {\n    double dist_number = turtlebotMotion.time_duration[motion_num] / 0.008;\n\n    goal_pos = turtlebotMotion.setJointAngle(motion_num);\n    motor_driver.syncRead(ADDR_X_PRESENT_POSITION, LEN_X_PRESENT_POSITION, pres_pos);\n\n    for (int joint_num = 0; joint_num < 8; joint_num++)\n    {\n      dist[joint_num] = (goal_pos[joint_num] * 1.0 - pres_pos[joint_num] * 1.0) / dist_number;\n      goal_pos_dist_db[joint_num] = pres_pos[joint_num] * 1.0;\n    }\n\n    for (int res_num = 0; res_num < (int)dist_number; res_num++)\n    {\n      for (int joint_num = 0; joint_num < 8; joint_num++)\n      {\n        goal_pos_dist_db[joint_num] += dist[joint_num];\n        goal_pos_dist_int[joint_num] = (int)goal_pos_dist_db[joint_num];\n      }\n\n      motor_driver.syncWrite(ADDR_X_GOAL_POSITION, LEN_X_GOAL_POSITION, goal_pos_dist_int);\n\n      delay(8);\n    }\n\n    delay(turtlebotMotion.time_space[motion_num] * 1000.0);\n  }\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_realturtlebot/turtlebot3_realturtlebot_motion.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#ifndef TURTLEBOT3_REALTURTLEBOT_MOTION_H_\n#define TURTLEBOT3_REALTURTLEBOT_MOTION_H_\n\n#include <RC100.h>\n\n#define SPEED_ADD_ON      2\n#define MOTION_NUM        20\n\n#define FASTER            4.0\n\nclass TurtlebotMotion\n{\n private:\n   int joint_angle[8] = {0, };\n\n   enum MODE\n   {\n     NONE = 0\n     , FORWARD1, FORWARD2, FORWARD3, FORWARD4\n     , STANDING_POSE2, STANDING_POSE3\n     , GRUMBLE1, GRUMBLE2, RLEFT, RRIGHT, PLEFT, PRIGHT\n     , LOOK_AROUND_LEFT, LOOK_AROUND_RIGHT\n     , PLEFT_FORWARD, PRIGHT_FORWARD, PLEFT_BACKWARD, PRIGHT_BACKWARD\n     , RLEFT_FORWARD2, RLEFT_FORWARD3\n     , RRIGHT_FORWARD2, RRIGHT_FORWARD3\n     , RLEFT_BACKWARD, RRIGHT_BACKWARD, RLEFT_PLEFT, RLEFT_PRIGHT, RRIGHT_PLEFT, RRIGHT_PRIGHT\n   } mobile_mode, pres_mobile_mode;\n\n public:\n   int shoulder_left_rear_angle[MOTION_NUM] = {0, }, shoulder_right_rear_angle[MOTION_NUM] = {0, }, shoulder_left_front_angle[MOTION_NUM] = {0, }, shoulder_right_front_angle[MOTION_NUM] = {0, };\n   int leg_left_rear_angle[MOTION_NUM] = {0, }, leg_right_rear_angle[MOTION_NUM] = {0, }, leg_left_front_angle[MOTION_NUM] = {0, }, leg_right_front_angle[MOTION_NUM] = {0, };\n   int head_yaw = 2048, head_pitch = 3072; // 1848 ~ 2248 : 3072 ~ 2560\n   int motion_all_num;\n   double time_duration[MOTION_NUM] = {0.0, }, time_space[MOTION_NUM] = {0.0, };\n\n   TurtlebotMotion()\n   : motion_all_num(1)\n   { }\n\n   MODE getDirection(int rcData)\n   {\n     switch (rcData)\n     {\n      case (RC100_BTN_U): if (pres_mobile_mode == NONE)\n                          {\n                            mobile_mode = FORWARD1;\n                          }\n                          else if (pres_mobile_mode == FORWARD1)\n                          {\n                            mobile_mode = FORWARD2;\n                          }\n                          else if (pres_mobile_mode == FORWARD2)\n                          {\n                            mobile_mode = FORWARD3;\n                          }\n                          else if (pres_mobile_mode == FORWARD3)\n                          {\n                            mobile_mode = FORWARD2;\n                          }\n                          pres_mobile_mode = mobile_mode;\n                          break;\n      case (RC100_BTN_L): if (pres_mobile_mode == NONE)\n                          {\n                            mobile_mode = RLEFT;\n                          }\n                          else if (pres_mobile_mode == FORWARD2)\n                          {\n                            mobile_mode = STANDING_POSE2;\n                          }\n                          else if (pres_mobile_mode == FORWARD3)\n                          {\n                            mobile_mode = STANDING_POSE3;\n                          }\n                          pres_mobile_mode = mobile_mode;\n                          break;\n      case (RC100_BTN_R): if (pres_mobile_mode == NONE)\n                          {\n                            mobile_mode = RRIGHT;\n                          }\n                          else if (pres_mobile_mode == FORWARD2)\n                          {\n                            mobile_mode = STANDING_POSE2;\n                          }\n                          else if (pres_mobile_mode == FORWARD3)\n                          {\n                            mobile_mode = STANDING_POSE3;\n                          }\n                          pres_mobile_mode = mobile_mode;\n                          break;\n      case (RC100_BTN_2): if (head_yaw < 2228) // 2248\n                            head_yaw += 20;\n                          break;\n      case (RC100_BTN_4): if (head_yaw > 1868) // 1848\n                            head_yaw -= 20;\n                          break;\n      case (RC100_BTN_1): if (head_pitch > 2580) // 2560\n                            head_pitch -= 20;\n                          break;\n      case (RC100_BTN_3): if (head_pitch < 3052) // 3072\n                            head_pitch += 20;\n                          break;\n      case (RC100_BTN_6): if (pres_mobile_mode == NONE)\n                            mobile_mode = LOOK_AROUND_LEFT;\n                          pres_mobile_mode = mobile_mode;\n                          break;\n      case (RC100_BTN_5): if (pres_mobile_mode == NONE)\n                            mobile_mode = LOOK_AROUND_RIGHT;\n                          pres_mobile_mode = mobile_mode;\n                          break;\n\n      case (RC100_BTN_U + RC100_BTN_L): if (pres_mobile_mode == NONE)\n                                        {\n                                          mobile_mode = FORWARD1;\n                                        }\n                                        else if (pres_mobile_mode == FORWARD1)\n                                        {\n                                          mobile_mode = RLEFT_FORWARD3;\n                                        }\n                                        else if (pres_mobile_mode == FORWARD2)\n                                        {\n                                          mobile_mode = RLEFT_FORWARD2;\n                                        }\n                                        else if (pres_mobile_mode == FORWARD3)\n                                        {\n                                          mobile_mode = RLEFT_FORWARD3;\n                                        }\n                                        pres_mobile_mode = mobile_mode;\n                                        break;\n\n      case (RC100_BTN_U + RC100_BTN_R): if (pres_mobile_mode == NONE)\n                                        {\n                                          mobile_mode = FORWARD1;\n                                        }\n                                        else if (pres_mobile_mode == FORWARD1)\n                                        {\n                                          mobile_mode = RRIGHT_FORWARD3;\n                                        }\n                                        else if (pres_mobile_mode == FORWARD2)\n                                        {\n                                          mobile_mode = RRIGHT_FORWARD2;\n                                        }\n                                        else if (pres_mobile_mode == FORWARD3)\n                                        {\n                                          mobile_mode = RRIGHT_FORWARD3;\n                                        }\n                                        pres_mobile_mode = mobile_mode;\n                                        break;\n\n\n      case (RC100_BTN_U + RC100_BTN_D): if (pres_mobile_mode == NONE)\n                                        {\n                                          mobile_mode = NONE;\n                                        }\n                                        else if (pres_mobile_mode == FORWARD2)\n                                        {\n                                          mobile_mode = STANDING_POSE2;\n                                        }\n                                        else if (pres_mobile_mode == FORWARD3)\n                                        {\n                                          mobile_mode = STANDING_POSE3;\n                                        }\n                                        else if ((pres_mobile_mode == STANDING_POSE2) || (pres_mobile_mode == STANDING_POSE3))\n                                        {\n                                          mobile_mode = NONE;\n                                        }\n                                        pres_mobile_mode = mobile_mode;\n                                        break;\n\n      case (RC100_BTN_D + RC100_BTN_1): if (pres_mobile_mode == NONE)\n                                        {\n                                          mobile_mode = GRUMBLE1;\n                                        }\n                                        pres_mobile_mode = mobile_mode;\n                                        break;\n      case (RC100_BTN_D + RC100_BTN_2): if (pres_mobile_mode == NONE)\n                                        {\n                                          mobile_mode = GRUMBLE2;\n                                        }\n                                        pres_mobile_mode = mobile_mode;\n                                        break;\n\n      default: mobile_mode = NONE;\n               pres_mobile_mode = mobile_mode;\n               break;\n     }\n\n     return mobile_mode;\n   }\n\n   void setParams()\n   {\n     switch (mobile_mode)\n     {\n       case FORWARD1:               motion_all_num = 8;\n                                    shoulder_left_rear_angle[0] = 0;    shoulder_right_rear_angle[0] = 0;    shoulder_left_front_angle[0] = 0;    shoulder_right_front_angle[0] = 0;\n                                    leg_left_rear_angle[0] = 0;         leg_right_rear_angle[0] = 0;         leg_left_front_angle[0] = 0;         leg_right_front_angle[0] = 0;\n                                    time_duration[0] = 0.4 / FASTER;    time_space[0] = .0;\n                                    shoulder_left_rear_angle[1] = 0;    shoulder_right_rear_angle[1] = 0;    shoulder_left_front_angle[1] = 0;    shoulder_right_front_angle[1] = 0;\n                                    leg_left_rear_angle[1] = 256;       leg_right_rear_angle[1] = 0;         leg_left_front_angle[1] = 0;         leg_right_front_angle[1] = 0;\n                                    time_duration[1] = 0.1 / FASTER;    time_space[1] = .0;\n                                    shoulder_left_rear_angle[2] = 700;  shoulder_right_rear_angle[2] = 0;    shoulder_left_front_angle[2] = 0;    shoulder_right_front_angle[2] = 0;\n                                    leg_left_rear_angle[2] = 512;       leg_right_rear_angle[2] = 0;         leg_left_front_angle[2] = 0;         leg_right_front_angle[2] = 0;\n                                    time_duration[2] = 0.2 / FASTER;    time_space[2] = .0;\n                                    shoulder_left_rear_angle[3] = 700;  shoulder_right_rear_angle[3] = 0;    shoulder_left_front_angle[3] = 0;    shoulder_right_front_angle[3] = 0;\n                                    leg_left_rear_angle[3] = 0;         leg_right_rear_angle[3] = 0;         leg_left_front_angle[3] = 0;         leg_right_front_angle[3] = 0;\n                                    time_duration[3] = 0.1 / FASTER;    time_space[3] = .0;\n\n\n                                    shoulder_left_rear_angle[4] = 700;  shoulder_right_rear_angle[4] = 0;    shoulder_left_front_angle[4] = 0;    shoulder_right_front_angle[4] = 0;\n                                    leg_left_rear_angle[4] = 0;         leg_right_rear_angle[4] = 0;         leg_left_front_angle[4] = -512;      leg_right_front_angle[4] = 0;\n                                    time_duration[4] = 0.1 / FASTER;    time_space[4] = .0;\n                                    shoulder_left_rear_angle[5] = 0;    shoulder_right_rear_angle[5] = 0;    shoulder_left_front_angle[5] = 0;    shoulder_right_front_angle[5] = 700;\n                                    leg_left_rear_angle[5] = 0;         leg_right_rear_angle[5] = -256;      leg_left_front_angle[5] = 0;         leg_right_front_angle[5] = 0;\n                                    time_duration[5] = 0.4 / FASTER;    time_space[5] = .0;\n                                    shoulder_left_rear_angle[6] = 0;    shoulder_right_rear_angle[6] = -700; shoulder_left_front_angle[6] = 0;    shoulder_right_front_angle[6] = 700;\n                                    leg_left_rear_angle[6] = 0;         leg_right_rear_angle[6] = -512;      leg_left_front_angle[6] = 0;         leg_right_front_angle[6] = 0;\n                                    time_duration[6] = 0.2 / FASTER;    time_space[6] = .0;\n                                    shoulder_left_rear_angle[7] = 0;    shoulder_right_rear_angle[7] = -700; shoulder_left_front_angle[7] = 0;    shoulder_right_front_angle[7] = 700;\n                                    leg_left_rear_angle[7] = 0;         leg_right_rear_angle[7] = 0;         leg_left_front_angle[7] = 0;         leg_right_front_angle[7] = 0;\n                                    time_duration[7] = 0.1 / FASTER;    time_space[7] = .0;\n\n                                    mobile_mode = FORWARD3;\n                                    pres_mobile_mode = mobile_mode;\n\n                                    break;\n       case FORWARD2:               motion_all_num = 5;\n                                    shoulder_left_rear_angle[0] = 0;    shoulder_right_rear_angle[0] = -700; shoulder_left_front_angle[0] = 0;    shoulder_right_front_angle[0] = 700;\n                                    leg_left_rear_angle[0] = 0;         leg_right_rear_angle[0] = 0;         leg_left_front_angle[0] = 0;         leg_right_front_angle[0] = 256;\n                                    time_duration[0] = 0.1 / FASTER;       time_space[0] = .0;\n                                    shoulder_left_rear_angle[1] = 0;    shoulder_right_rear_angle[1] = -700; shoulder_left_front_angle[1] = 0;    shoulder_right_front_angle[1] = 0;\n                                    leg_left_rear_angle[1] = 0;         leg_right_rear_angle[1] = 0;         leg_left_front_angle[1] = 0;         leg_right_front_angle[1] = 512;\n                                    time_duration[1] = 0.2 / FASTER;       time_space[1] = .0;\n                                    shoulder_left_rear_angle[2] = 0;    shoulder_right_rear_angle[2] = 0;    shoulder_left_front_angle[2] = -700; shoulder_right_front_angle[2] = 0;\n                                    leg_left_rear_angle[2] = 512;       leg_right_rear_angle[2] = 0;         leg_left_front_angle[2] = 0;         leg_right_front_angle[2] = 0;\n                                    time_duration[2] = 0.4 / FASTER;       time_space[2] = .0;\n                                    shoulder_left_rear_angle[3] = 700;  shoulder_right_rear_angle[3] = 0;    shoulder_left_front_angle[3] = -700; shoulder_right_front_angle[3] = 0;\n                                    leg_left_rear_angle[3] = 512;       leg_right_rear_angle[3] = 0;         leg_left_front_angle[3] = 0;         leg_right_front_angle[3] = 0;\n                                    time_duration[3] = 0.2 / FASTER;       time_space[3] = .0;\n                                    shoulder_left_rear_angle[4] = 700;  shoulder_right_rear_angle[4] = 0;    shoulder_left_front_angle[4] = -700; shoulder_right_front_angle[4] = 0;\n                                    leg_left_rear_angle[4] = 0;         leg_right_rear_angle[4] = 0;         leg_left_front_angle[4] = 0;         leg_right_front_angle[4] = 0;\n                                    time_duration[4] = 0.1 / FASTER;       time_space[4] = .0;\n                                    break;\n       case FORWARD3:               motion_all_num = 5;\n                                    shoulder_left_rear_angle[0] = 700; shoulder_right_rear_angle[0] = 0;     shoulder_left_front_angle[0] = -700; shoulder_right_front_angle[0] = 0;\n                                    leg_left_rear_angle[0] = 0;        leg_right_rear_angle[0] = 0;          leg_left_front_angle[0] = -256;      leg_right_front_angle[0] = 0;\n                                    time_duration[0] = 0.1 / FASTER;      time_space[0] = .0;\n                                    shoulder_left_rear_angle[1] = 700; shoulder_right_rear_angle[1] = 0;     shoulder_left_front_angle[1] = 0;    shoulder_right_front_angle[1] = 0;\n                                    leg_left_rear_angle[1] = 0;        leg_right_rear_angle[1] = 0;          leg_left_front_angle[1] = -512;      leg_right_front_angle[1] = 0;\n                                    time_duration[1] = 0.2 / FASTER;      time_space[1] = .0;\n                                    shoulder_left_rear_angle[2] = 0;   shoulder_right_rear_angle[2] = 0;     shoulder_left_front_angle[2] = 0;    shoulder_right_front_angle[2] = 700;\n                                    leg_left_rear_angle[2] = 0;        leg_right_rear_angle[2] = -512;       leg_left_front_angle[2] = 0;         leg_right_front_angle[2] = 0;\n                                    time_duration[2] = 0.4 / FASTER;      time_space[2] = .0;\n                                    shoulder_left_rear_angle[3] = 0;   shoulder_right_rear_angle[3] = -700;  shoulder_left_front_angle[3] = 0;    shoulder_right_front_angle[3] = 700;\n                                    leg_left_rear_angle[3] = 0;        leg_right_rear_angle[3] = -512;       leg_left_front_angle[3] = 0;         leg_right_front_angle[3] = 0;\n                                    time_duration[3] = 0.2 / FASTER;      time_space[3] = .0;\n                                    shoulder_left_rear_angle[4] = 0;   shoulder_right_rear_angle[4] = -700;  shoulder_left_front_angle[4] = 0;    shoulder_right_front_angle[4] = 700;\n                                    leg_left_rear_angle[4] = 0;        leg_right_rear_angle[4] = 0;          leg_left_front_angle[4] = 0;         leg_right_front_angle[4] = 0;\n                                    time_duration[4] = 0.1 / FASTER;      time_space[4] = .0;\n                                    break;\n\n      case RLEFT_FORWARD2:          motion_all_num = 9;\n                                    shoulder_left_rear_angle[0] = 700;    shoulder_right_rear_angle[0] = 0; shoulder_left_front_angle[0] = -700;    shoulder_right_front_angle[0] = 0;\n                                    leg_left_rear_angle[0] = 0;         leg_right_rear_angle[0] = 0;         leg_left_front_angle[0] = -256;         leg_right_front_angle[0] = 0;\n                                    time_duration[0] = 0.1 / FASTER;       time_space[0] = .0;\n                                    shoulder_left_rear_angle[1] = 700;    shoulder_right_rear_angle[1] = 0; shoulder_left_front_angle[1] = 0;    shoulder_right_front_angle[1] = 0;\n                                    leg_left_rear_angle[1] = 0;         leg_right_rear_angle[1] = 0;         leg_left_front_angle[1] = -512;         leg_right_front_angle[1] = 0;\n                                    time_duration[1] = 0.2 / FASTER;       time_space[1] = .0;\n\n                                    shoulder_left_rear_angle[2] = 700;    shoulder_right_rear_angle[2] = 500;    shoulder_left_front_angle[2] = 0; shoulder_right_front_angle[2] = 700;\n                                    leg_left_rear_angle[2] = 0;       leg_right_rear_angle[2] = 0;         leg_left_front_angle[2] = 0;         leg_right_front_angle[2] = 0;\n                                    time_duration[2] = 0.4 / FASTER;       time_space[2] = .0;\n                                    shoulder_left_rear_angle[3] = 700;    shoulder_right_rear_angle[3] = 500;    shoulder_left_front_angle[3] = 0; shoulder_right_front_angle[3] = 700;\n                                    leg_left_rear_angle[3] = 256;       leg_right_rear_angle[3] = 0;         leg_left_front_angle[3] = 0;         leg_right_front_angle[3] = 0;\n                                    time_duration[3] = 0.1 / FASTER;       time_space[3] = .0;\n                                    shoulder_left_rear_angle[4] = 0;  shoulder_right_rear_angle[4] = 500;    shoulder_left_front_angle[4] = 0; shoulder_right_front_angle[4] = 700;\n                                    leg_left_rear_angle[4] = 512;       leg_right_rear_angle[4] = 0;         leg_left_front_angle[4] = 0;         leg_right_front_angle[4] = 0;\n                                    time_duration[4] = 0.2 / FASTER;       time_space[4] = .0;\n                                    shoulder_left_rear_angle[5] = 0;  shoulder_right_rear_angle[5] = 500;    shoulder_left_front_angle[5] = 0; shoulder_right_front_angle[5] = 700;\n                                    leg_left_rear_angle[5] = 0;       leg_right_rear_angle[5] = 0;         leg_left_front_angle[5] = 0;         leg_right_front_angle[5] = 0;\n                                    time_duration[5] = 0.1 / FASTER;       time_space[5] = .0;\n                                    shoulder_left_rear_angle[6] = 0;  shoulder_right_rear_angle[6] = 500;    shoulder_left_front_angle[6] = 0; shoulder_right_front_angle[6] = 700;\n                                    leg_left_rear_angle[6] = 256;         leg_right_rear_angle[6] = 0;         leg_left_front_angle[6] = 0;         leg_right_front_angle[6] = 0;\n                                    time_duration[6] = 0.1 / FASTER;       time_space[6] = .0;\n\n                                    shoulder_left_rear_angle[7] = 0;  shoulder_right_rear_angle[7] = -700;    shoulder_left_front_angle[7] = 0; shoulder_right_front_angle[7] = 700;\n                                    leg_left_rear_angle[7] = 0;         leg_right_rear_angle[7] = -512;         leg_left_front_angle[7] = 0;         leg_right_front_angle[7] = 0;\n                                    time_duration[7] = 0.2 / FASTER;       time_space[7] = .0;\n                                    shoulder_left_rear_angle[8] = 0;  shoulder_right_rear_angle[8] = -700;    shoulder_left_front_angle[8] = 0; shoulder_right_front_angle[8] = 700;\n                                    leg_left_rear_angle[8] = 0;         leg_right_rear_angle[8] = 0;         leg_left_front_angle[8] = 0;         leg_right_front_angle[8] = 0;\n                                    time_duration[8] = 0.1 / FASTER;       time_space[8] = .0;\n\n                                    mobile_mode = FORWARD3;\n                                    pres_mobile_mode = mobile_mode;\n                                    break;\n\n      case RLEFT_FORWARD3:          motion_all_num = 6;\n                                    shoulder_left_rear_angle[0] = 0; shoulder_right_rear_angle[0] = -700;     shoulder_left_front_angle[0] = 0; shoulder_right_front_angle[0] = 700;\n                                    leg_left_rear_angle[0] = 0;        leg_right_rear_angle[0] = 0;          leg_left_front_angle[0] = 0;      leg_right_front_angle[0] = 256;\n                                    time_duration[0] = 0.1 / FASTER;      time_space[0] = .0;\n                                    shoulder_left_rear_angle[1] = 0; shoulder_right_rear_angle[1] = -700;     shoulder_left_front_angle[1] = 0;    shoulder_right_front_angle[1] = -700;\n                                    leg_left_rear_angle[1] = 0;        leg_right_rear_angle[1] = 0;          leg_left_front_angle[1] = 0;      leg_right_front_angle[1] = 512;\n                                    time_duration[1] = 0.2 / FASTER;      time_space[1] = .0;\n                                    shoulder_left_rear_angle[2] = 0; shoulder_right_rear_angle[2] = -700;     shoulder_left_front_angle[2] = 0;    shoulder_right_front_angle[2] = -700;\n                                    leg_left_rear_angle[2] = 0;        leg_right_rear_angle[2] = 0;          leg_left_front_angle[2] = 0;      leg_right_front_angle[2] = 0;\n                                    time_duration[2] = 0.1 / FASTER;      time_space[2] = .0;\n                                    shoulder_left_rear_angle[2 + 1] = 700;   shoulder_right_rear_angle[2 + 1] = 0;     shoulder_left_front_angle[2 + 1] = 0;    shoulder_right_front_angle[2 + 1] = 0;\n                                    leg_left_rear_angle[2 + 1] = 0;        leg_right_rear_angle[2 + 1] = 0;       leg_left_front_angle[2 + 1] = -256;         leg_right_front_angle[2 + 1] = 0;\n                                    time_duration[2 + 1] = 0.4 / FASTER;      time_space[2 + 1] = .0;\n                                    shoulder_left_rear_angle[3 + 1] = 700;   shoulder_right_rear_angle[3 + 1] = 0;  shoulder_left_front_angle[3 + 1] = -700;    shoulder_right_front_angle[3 + 1] = 0;\n                                    leg_left_rear_angle[3 + 1] = 0;        leg_right_rear_angle[3 + 1] = 0;       leg_left_front_angle[3 + 1] = -512;         leg_right_front_angle[3 + 1] = 0;\n                                    time_duration[3 + 1] = 0.2 / FASTER;      time_space[3 + 1] = .0;\n                                    shoulder_left_rear_angle[4 + 1] = 700;   shoulder_right_rear_angle[4 + 1] = 0;  shoulder_left_front_angle[4 + 1] = -700;    shoulder_right_front_angle[4 + 1] = 0;\n                                    leg_left_rear_angle[4 + 1] = 0;        leg_right_rear_angle[4 + 1] = 0;          leg_left_front_angle[4 + 1] = 0;         leg_right_front_angle[4 + 1] = 0;\n                                    time_duration[4 + 1] = 0.1 / FASTER;      time_space[4 + 1] = .0;\n\n                                    mobile_mode = FORWARD2;\n                                    pres_mobile_mode = mobile_mode;\n                                    break;\n\n     case RRIGHT_FORWARD2:         motion_all_num = 6;\n                                   shoulder_left_rear_angle[0] = 700; shoulder_right_rear_angle[0] = 0;     shoulder_left_front_angle[0] = -700; shoulder_right_front_angle[0] = 0;\n                                   leg_left_rear_angle[0] = 0;        leg_right_rear_angle[0] = 0;          leg_left_front_angle[0] = -256;      leg_right_front_angle[0] = 0;\n                                   time_duration[0] = 0.1 / FASTER;      time_space[0] = .0;\n                                   shoulder_left_rear_angle[1] = 700; shoulder_right_rear_angle[1] = 0;     shoulder_left_front_angle[1] = 700;    shoulder_right_front_angle[1] = 0;\n                                   leg_left_rear_angle[1] = 0;        leg_right_rear_angle[1] = 0;          leg_left_front_angle[1] = -512;      leg_right_front_angle[1] = 0;\n                                   time_duration[1] = 0.2 / FASTER;      time_space[1] = .0;\n                                   shoulder_left_rear_angle[2] = 700; shoulder_right_rear_angle[2] = 0;     shoulder_left_front_angle[2] = 700;    shoulder_right_front_angle[2] = 0;\n                                   leg_left_rear_angle[2] = 0;        leg_right_rear_angle[2] = 0;          leg_left_front_angle[2] = 0;      leg_right_front_angle[2] = 0;\n                                   time_duration[2] = 0.1 / FASTER;      time_space[2] = .0;\n                                   shoulder_left_rear_angle[2 + 1] = 0;   shoulder_right_rear_angle[2 + 1] = -700;     shoulder_left_front_angle[2 + 1] = 0;    shoulder_right_front_angle[2 + 1] = 0;\n                                   leg_left_rear_angle[2 + 1] = 0;        leg_right_rear_angle[2 + 1] = 0;       leg_left_front_angle[2 + 1] = 0;         leg_right_front_angle[2 + 1] = 256;\n                                   time_duration[2 + 1] = 0.4 / FASTER;      time_space[2 + 1] = .0;\n                                   shoulder_left_rear_angle[3 + 1] = 0;   shoulder_right_rear_angle[3 + 1] = -700;  shoulder_left_front_angle[3 + 1] = 0;    shoulder_right_front_angle[3 + 1] = 700;\n                                   leg_left_rear_angle[3 + 1] = 0;        leg_right_rear_angle[3 + 1] = 0;       leg_left_front_angle[3 + 1] = 0;         leg_right_front_angle[3 + 1] = 512;\n                                   time_duration[3 + 1] = 0.2 / FASTER;      time_space[3 + 1] = .0;\n                                   shoulder_left_rear_angle[4 + 1] = 0;   shoulder_right_rear_angle[4 + 1] = -700;  shoulder_left_front_angle[4 + 1] = 0;    shoulder_right_front_angle[4 + 1] = 700;\n                                   leg_left_rear_angle[4 + 1] = 0;        leg_right_rear_angle[4 + 1] = 0;          leg_left_front_angle[4 + 1] = 0;         leg_right_front_angle[4 + 1] = 0;\n                                   time_duration[4 + 1] = 0.1 / FASTER;      time_space[4 + 1] = .0;\n\n                                   mobile_mode = FORWARD3;\n                                   pres_mobile_mode = mobile_mode;\n                                   break;\n     case RRIGHT_FORWARD3:         motion_all_num = 9;\n                                   shoulder_left_rear_angle[0] = 0;    shoulder_right_rear_angle[0] = -700; shoulder_left_front_angle[0] = 0;    shoulder_right_front_angle[0] = 700;\n                                   leg_left_rear_angle[0] = 0;         leg_right_rear_angle[0] = 0;         leg_left_front_angle[0] = 0;         leg_right_front_angle[0] = 256;\n                                   time_duration[0] = 0.1 / FASTER;       time_space[0] = .0;\n                                   shoulder_left_rear_angle[1] = 0;    shoulder_right_rear_angle[1] = -700; shoulder_left_front_angle[1] = 0;    shoulder_right_front_angle[1] = 0;\n                                   leg_left_rear_angle[1] = 0;         leg_right_rear_angle[1] = 0;         leg_left_front_angle[1] = 0;         leg_right_front_angle[1] = 512;\n                                   time_duration[1] = 0.2 / FASTER;       time_space[1] = .0;\n                                   shoulder_left_rear_angle[2] = -500;    shoulder_right_rear_angle[2] = -700;    shoulder_left_front_angle[2] = -700; shoulder_right_front_angle[2] = 0;\n                                   leg_left_rear_angle[2] = 0;       leg_right_rear_angle[2] = 0;         leg_left_front_angle[2] = 0;         leg_right_front_angle[2] = 0;\n                                   time_duration[2] = 0.4 / FASTER;       time_space[2] = .0;\n                                   shoulder_left_rear_angle[3] = -500;    shoulder_right_rear_angle[3] = -700;    shoulder_left_front_angle[3] = -700; shoulder_right_front_angle[3] = 0;\n                                   leg_left_rear_angle[3] = 0;       leg_right_rear_angle[3] = -256;         leg_left_front_angle[3] = 0;         leg_right_front_angle[3] = 0;\n                                   time_duration[3] = 0.1 / FASTER;       time_space[3] = .0;\n                                   shoulder_left_rear_angle[4] = -500;  shoulder_right_rear_angle[4] = 0;    shoulder_left_front_angle[4] = -700; shoulder_right_front_angle[4] = 0;\n                                   leg_left_rear_angle[4] = 0;       leg_right_rear_angle[4] = -512;         leg_left_front_angle[4] = 0;         leg_right_front_angle[4] = 0;\n                                   time_duration[4] = 0.2 / FASTER;       time_space[4] = .0;\n                                   shoulder_left_rear_angle[5] = -500;  shoulder_right_rear_angle[5] = 0;    shoulder_left_front_angle[5] = -700; shoulder_right_front_angle[5] = 0;\n                                   leg_left_rear_angle[5] = 0;       leg_right_rear_angle[5] = 0;         leg_left_front_angle[5] = 0;         leg_right_front_angle[5] = 0;\n                                   time_duration[5] = 0.1 / FASTER;       time_space[5] = .0;\n                                   shoulder_left_rear_angle[6] = -500;  shoulder_right_rear_angle[6] = 0;    shoulder_left_front_angle[6] = -700; shoulder_right_front_angle[6] = 0;\n                                   leg_left_rear_angle[6] = 256;         leg_right_rear_angle[6] = 0;         leg_left_front_angle[6] = 0;         leg_right_front_angle[6] = 0;\n                                   time_duration[6] = 0.1 / FASTER;       time_space[6] = .0;\n                                   shoulder_left_rear_angle[7] = 700;  shoulder_right_rear_angle[7] = 0;    shoulder_left_front_angle[7] = -700; shoulder_right_front_angle[7] = 0;\n                                   leg_left_rear_angle[7] = 512;         leg_right_rear_angle[7] = 0;         leg_left_front_angle[7] = 0;         leg_right_front_angle[7] = 0;\n                                   time_duration[7] = 0.2 / FASTER;       time_space[7] = .0;\n                                   shoulder_left_rear_angle[8] = 700;  shoulder_right_rear_angle[8] = 0;    shoulder_left_front_angle[8] = -700; shoulder_right_front_angle[8] = 0;\n                                   leg_left_rear_angle[8] = 0;         leg_right_rear_angle[8] = 0;         leg_left_front_angle[8] = 0;         leg_right_front_angle[8] = 0;\n                                   time_duration[8] = 0.1 / FASTER;       time_space[8] = .0;\n\n                                   mobile_mode = FORWARD2;\n                                   pres_mobile_mode = mobile_mode;\n                                   break;\n\n       case NONE:                   motion_all_num = 1;\n                                    shoulder_left_rear_angle[0] = 0;   shoulder_right_rear_angle[0] = 0;     shoulder_left_front_angle[0] = 0;    shoulder_right_front_angle[0] = 0;\n                                    leg_left_rear_angle[0] = 0;        leg_right_rear_angle[0] = 0;          leg_left_front_angle[0] = 0;         leg_right_front_angle[0] = 0;\n                                    time_duration[0] = 2.0;      time_space[0] = .0;\n                                    break;\n\n       case STANDING_POSE2:     motion_all_num = 6;\n                                    shoulder_left_rear_angle[0] = 700; shoulder_right_rear_angle[0] = 0;     shoulder_left_front_angle[0] = -700; shoulder_right_front_angle[0] = 0;\n                                    leg_left_rear_angle[0] = 0;        leg_right_rear_angle[0] = 0;          leg_left_front_angle[0] = -512;      leg_right_front_angle[0] = 0;\n                                    time_duration[0] = 0.1 / FASTER;      time_space[0] = .0;\n                                    shoulder_left_rear_angle[1] = 700; shoulder_right_rear_angle[1] = 0;     shoulder_left_front_angle[1] = 0;    shoulder_right_front_angle[1] = 0;\n                                    leg_left_rear_angle[1] = 0;        leg_right_rear_angle[1] = 0;          leg_left_front_angle[1] = -512;      leg_right_front_angle[1] = 0;\n                                    time_duration[1] = 0.2 / FASTER;      time_space[1] = .0;\n                                    shoulder_left_rear_angle[2] = 700; shoulder_right_rear_angle[2] = 0;     shoulder_left_front_angle[2] = 0;    shoulder_right_front_angle[2] = 0;\n                                    leg_left_rear_angle[2] = 0;        leg_right_rear_angle[2] = 0;          leg_left_front_angle[2] = 0;         leg_right_front_angle[2] = 0;\n                                    time_duration[2] = 0.1 / FASTER;      time_space[2] = .0;\n                                    shoulder_left_rear_angle[3] = 700; shoulder_right_rear_angle[3] = 0;     shoulder_left_front_angle[3] = 0;    shoulder_right_front_angle[3] = 0;\n                                    leg_left_rear_angle[3] = 512;      leg_right_rear_angle[3] = 0;          leg_left_front_angle[3] = 0;         leg_right_front_angle[3] = 0;\n                                    time_duration[3] = 0.2 / FASTER;      time_space[3] = .0;\n                                    shoulder_left_rear_angle[4] = 0;   shoulder_right_rear_angle[4] = 0;     shoulder_left_front_angle[4] = 0;    shoulder_right_front_angle[4] = 0;\n                                    leg_left_rear_angle[4] = 512;      leg_right_rear_angle[4] = 0;          leg_left_front_angle[4] = 0;         leg_right_front_angle[4] = 0;\n                                    time_duration[4] = 0.1 / FASTER;      time_space[4] = .0;\n                                    shoulder_left_rear_angle[5] = 0;   shoulder_right_rear_angle[5] = 0;     shoulder_left_front_angle[5] = 0;    shoulder_right_front_angle[5] = 0;\n                                    leg_left_rear_angle[5] = 0;        leg_right_rear_angle[5] = 0;          leg_left_front_angle[5] = 0;         leg_right_front_angle[5] = 0;\n                                    time_duration[5] = 0.1 / FASTER;      time_space[5] = .0;\n\n                                    mobile_mode = NONE;\n                                    pres_mobile_mode = mobile_mode;\n                                    break;\n\n       case STANDING_POSE3:     motion_all_num = 6;\n                                    shoulder_left_rear_angle[0] = 0;   shoulder_right_rear_angle[0] = -700;  shoulder_left_front_angle[0] = 0;    shoulder_right_front_angle[0] = 700;\n                                    leg_left_rear_angle[0] = 0;        leg_right_rear_angle[0] = 0;          leg_left_front_angle[0] = 0;         leg_right_front_angle[0] = 512;\n                                    time_duration[0] = 0.1 / FASTER;      time_space[0] = .0;\n                                    shoulder_left_rear_angle[1] = 0;   shoulder_right_rear_angle[1] = -700;  shoulder_left_front_angle[1] = 0;    shoulder_right_front_angle[1] = 0;\n                                    leg_left_rear_angle[1] = 0;        leg_right_rear_angle[1] = 0;          leg_left_front_angle[1] = 0;         leg_right_front_angle[1] = 512;\n                                    time_duration[1] = 0.2 / FASTER;      time_space[1] = .0;\n                                    shoulder_left_rear_angle[2] = 0;   shoulder_right_rear_angle[2] = -700;  shoulder_left_front_angle[2] = 0;    shoulder_right_front_angle[2] = 0;\n                                    leg_left_rear_angle[2] = 0;        leg_right_rear_angle[2] = 0;          leg_left_front_angle[2] = 0;         leg_right_front_angle[2] = 0;\n                                    time_duration[2] = 0.1 / FASTER;      time_space[2] = .0;\n                                    shoulder_left_rear_angle[3] = 0;   shoulder_right_rear_angle[3] = -700;  shoulder_left_front_angle[3] = 0;    shoulder_right_front_angle[3] = 0;\n                                    leg_left_rear_angle[3] = 0;        leg_right_rear_angle[3] = -512;       leg_left_front_angle[3] = 0;         leg_right_front_angle[3] = 0;\n                                    time_duration[3] = 0.1 / FASTER;      time_space[3] = .0;\n                                    shoulder_left_rear_angle[4] = 0;   shoulder_right_rear_angle[4] = 0;     shoulder_left_front_angle[4] = 0;    shoulder_right_front_angle[4] = 0;\n                                    leg_left_rear_angle[4] = 0;        leg_right_rear_angle[4] = -512;       leg_left_front_angle[4] = 0;         leg_right_front_angle[4] = 0;\n                                    time_duration[4] = 0.1 / FASTER;      time_space[4] = .0;\n                                    shoulder_left_rear_angle[5] = 0;   shoulder_right_rear_angle[5] = 0;     shoulder_left_front_angle[5] = 0;    shoulder_right_front_angle[5] = 0;\n                                    leg_left_rear_angle[5] = 0;        leg_right_rear_angle[5] = 0;          leg_left_front_angle[5] = 0;         leg_right_front_angle[5] = 0;\n                                    time_duration[5] = 0.1 / FASTER;      time_space[5] = .0;\n\n                                    mobile_mode = NONE;\n                                    pres_mobile_mode = mobile_mode;\n                                    break;\n\n       case GRUMBLE1:               motion_all_num = 6;\n                                    shoulder_left_rear_angle[0] = 0;  shoulder_right_rear_angle[0] = 0;  shoulder_left_front_angle[0] = 0;  shoulder_right_front_angle[0] = 0;\n                                    leg_left_rear_angle[0] = 256;       leg_right_rear_angle[0] = -256;      leg_left_front_angle[0] = -256;      leg_right_front_angle[0] = 256;\n                                    time_duration[0] = 0.1 / FASTER;       time_space[0] = .0;\n                                    shoulder_left_rear_angle[1] = 0;  shoulder_right_rear_angle[1] = 0;  shoulder_left_front_angle[1] = 0;  shoulder_right_front_angle[1] = 0;\n                                    leg_left_rear_angle[1] = 0;       leg_right_rear_angle[1] = 0;      leg_left_front_angle[1] = 0;      leg_right_front_angle[1] = 0;\n                                    time_duration[1] = 0.1 / FASTER;       time_space[1] = .0;\n                                    shoulder_left_rear_angle[0 + 2] = 0;  shoulder_right_rear_angle[0 + 2] = 0;  shoulder_left_front_angle[0 + 2] = 0;  shoulder_right_front_angle[0 + 2] = 0;\n                                    leg_left_rear_angle[0 + 2] = 256;       leg_right_rear_angle[0 + 2] = -256;      leg_left_front_angle[0 + 2] = -256;      leg_right_front_angle[0 + 2] = 256;\n                                    time_duration[0 + 2] = 0.1 / FASTER;       time_space[0 + 2] = .0;\n                                    shoulder_left_rear_angle[1 + 2] = 0;  shoulder_right_rear_angle[1 + 2] = 0;  shoulder_left_front_angle[1 + 2] = 0;  shoulder_right_front_angle[1 + 2] = 0;\n                                    leg_left_rear_angle[1 + 2] = 0;       leg_right_rear_angle[1 + 2] = 0;      leg_left_front_angle[1 + 2] = 0;      leg_right_front_angle[1 + 2] = 0;\n                                    time_duration[1 + 2] = 0.1 / FASTER;       time_space[1 + 2] = .0;\n                                    shoulder_left_rear_angle[0 + 4] = 0;  shoulder_right_rear_angle[0 + 4] = 0;  shoulder_left_front_angle[0 + 4] = 0;  shoulder_right_front_angle[0 + 4] = 0;\n                                    leg_left_rear_angle[0 + 4] = 256;       leg_right_rear_angle[0 + 4] = -256;      leg_left_front_angle[0 + 4] = -256;      leg_right_front_angle[0 + 4] = 256;\n                                    time_duration[0 + 4] = 0.1 / FASTER;       time_space[0 + 4] = .0;\n                                    shoulder_left_rear_angle[1 + 4] = 0;  shoulder_right_rear_angle[1 + 4] = 0;  shoulder_left_front_angle[1 + 4] = 0;  shoulder_right_front_angle[1 + 4] = 0;\n                                    leg_left_rear_angle[1 + 4] = 0;       leg_right_rear_angle[1 + 4] = 0;      leg_left_front_angle[1 + 4] = 0;      leg_right_front_angle[1 + 4] = 0;\n                                    time_duration[1 + 4] = 0.1 / FASTER;       time_space[1 + 4] = .0;\n\n                                    mobile_mode = NONE;\n                                    pres_mobile_mode = mobile_mode;\n                                    break;\n\n       case GRUMBLE2:               motion_all_num = 6;\n                                    shoulder_left_rear_angle[0] = 256;  shoulder_right_rear_angle[0] = -256;  shoulder_left_front_angle[0] = -256;  shoulder_right_front_angle[0] = 256;\n                                    leg_left_rear_angle[0] = 0;       leg_right_rear_angle[0] = 0;      leg_left_front_angle[0] = 0;      leg_right_front_angle[0] = 0;\n                                    time_duration[0] = 0.1 / FASTER;       time_space[0] = .0;\n                                    shoulder_left_rear_angle[1] = 0;  shoulder_right_rear_angle[1] = 0;  shoulder_left_front_angle[1] = 0;  shoulder_right_front_angle[1] = 0;\n                                    leg_left_rear_angle[1] = 0;       leg_right_rear_angle[1] = 0;      leg_left_front_angle[1] = 0;      leg_right_front_angle[1] = 0;\n                                    time_duration[1] = 0.1 / FASTER;       time_space[1] = .0;\n                                    shoulder_left_rear_angle[0 + 2] = 256;  shoulder_right_rear_angle[0 + 2] = -256;  shoulder_left_front_angle[0 + 2] = -256;  shoulder_right_front_angle[0 + 2] = 256;\n                                    leg_left_rear_angle[0 + 2] = 0;       leg_right_rear_angle[0 + 2] = 0;      leg_left_front_angle[0 + 2] = 0;      leg_right_front_angle[0 + 2] = 0;\n                                    time_duration[0 + 2] = 0.1 / FASTER;       time_space[0 + 2] = .0;\n                                    shoulder_left_rear_angle[1 + 2] = 0;  shoulder_right_rear_angle[1 + 2] = 0;  shoulder_left_front_angle[1 + 2] = 0;  shoulder_right_front_angle[1 + 2] = 0;\n                                    leg_left_rear_angle[1 + 2] = 0;       leg_right_rear_angle[1 + 2] = 0;      leg_left_front_angle[1 + 2] = 0;      leg_right_front_angle[1 + 2] = 0;\n                                    time_duration[1 + 2] = 0.1 / FASTER;       time_space[1 + 2] = .0;\n                                    shoulder_left_rear_angle[0 + 4] = 256;  shoulder_right_rear_angle[0 + 4] = -256;  shoulder_left_front_angle[0 + 4] = -256;  shoulder_right_front_angle[0 + 4] = 256;\n                                    leg_left_rear_angle[0 + 4] = 0;       leg_right_rear_angle[0 + 4] = 0;      leg_left_front_angle[0 + 4] = 0;      leg_right_front_angle[0 + 4] = 0;\n                                    time_duration[0 + 4] = 0.1 / FASTER;       time_space[0 + 4] = .0;\n                                    shoulder_left_rear_angle[1 + 4] = 0;  shoulder_right_rear_angle[1 + 4] = 0;  shoulder_left_front_angle[1 + 4] = 0;  shoulder_right_front_angle[1 + 4] = 0;\n                                    leg_left_rear_angle[1 + 4] = 0;       leg_right_rear_angle[1 + 4] = 0;      leg_left_front_angle[1 + 4] = 0;      leg_right_front_angle[1 + 4] = 0;\n                                    time_duration[1 + 4] = 0.1 / FASTER;       time_space[1 + 4] = .0;\n\n                                    mobile_mode = NONE;\n                                    pres_mobile_mode = mobile_mode;\n                                    break;\n\n       case LOOK_AROUND_LEFT:       motion_all_num = 2;\n                                    shoulder_left_rear_angle[0] = 700;  shoulder_right_rear_angle[0] = 700;  shoulder_left_front_angle[0] = 700;  shoulder_right_front_angle[0] = 700;\n                                    leg_left_rear_angle[0] = 0;       leg_right_rear_angle[0] = 0;      leg_left_front_angle[0] = 0;      leg_right_front_angle[0] = 0;\n                                    time_duration[0] = 2.0 / FASTER;       time_space[0] = 2.0;\n                                    shoulder_left_rear_angle[1] = 0;  shoulder_right_rear_angle[1] = 0;  shoulder_left_front_angle[1] = 0;  shoulder_right_front_angle[1] = 0;\n                                    leg_left_rear_angle[1] = 0;       leg_right_rear_angle[1] = 0;      leg_left_front_angle[1] = 0;      leg_right_front_angle[1] = 0;\n                                    time_duration[1] = 2.0 / FASTER;       time_space[1] = .0;\n\n                                    mobile_mode = NONE;\n                                    pres_mobile_mode = mobile_mode;\n                                    break;\n       case LOOK_AROUND_RIGHT:       motion_all_num = 2;\n                                    shoulder_left_rear_angle[0] = -700;  shoulder_right_rear_angle[0] = -700;  shoulder_left_front_angle[0] = -700;  shoulder_right_front_angle[0] = -700;\n                                    leg_left_rear_angle[0] = 0;       leg_right_rear_angle[0] = 0;      leg_left_front_angle[0] = 0;      leg_right_front_angle[0] = 0;\n                                    time_duration[0] = 2.0 / FASTER;       time_space[0] = 2.0;\n                                    shoulder_left_rear_angle[1] = 0;  shoulder_right_rear_angle[1] = 0;  shoulder_left_front_angle[1] = 0;  shoulder_right_front_angle[1] = 0;\n                                    leg_left_rear_angle[1] = 0;       leg_right_rear_angle[1] = 0;      leg_left_front_angle[1] = 0;      leg_right_front_angle[1] = 0;\n                                    time_duration[1] = 2.0 / FASTER;       time_space[1] = .0;\n\n                                    mobile_mode = NONE;\n                                    pres_mobile_mode = mobile_mode;\n                                    break;\n\n       case RLEFT:                  motion_all_num = 13;\n                                    shoulder_left_rear_angle[0] = 500;  shoulder_right_rear_angle[0] = 500;  shoulder_left_front_angle[0] = 500;  shoulder_right_front_angle[0] = 500;\n                                    leg_left_rear_angle[0] = 0;         leg_right_rear_angle[0] = 0;         leg_left_front_angle[0] = 0;         leg_right_front_angle[0] = 0;\n                                    time_duration[0] = 0.1 / FASTER;       time_space[0] = .0;\n\n                                    shoulder_left_rear_angle[1] = 500;  shoulder_right_rear_angle[1] = 500;  shoulder_left_front_angle[1] = 500;  shoulder_right_front_angle[1] = 500;\n                                    leg_left_rear_angle[1] = 0;         leg_right_rear_angle[1] = -256;      leg_left_front_angle[1] = 0;         leg_right_front_angle[1] = 0;\n                                    time_duration[1] = 0.1 / FASTER;       time_space[1] = .0;\n                                    shoulder_left_rear_angle[2] = 500;  shoulder_right_rear_angle[2] = 0;    shoulder_left_front_angle[2] = 500;  shoulder_right_front_angle[2] = 500;\n                                    leg_left_rear_angle[2] = 0;         leg_right_rear_angle[2] = -512;      leg_left_front_angle[2] = 0;         leg_right_front_angle[2] = 0;\n                                    time_duration[2] = 0.2 / FASTER;       time_space[2] = .0;\n                                    shoulder_left_rear_angle[3] = 500;  shoulder_right_rear_angle[3] = 0;    shoulder_left_front_angle[3] = 500;  shoulder_right_front_angle[3] = 500;\n                                    leg_left_rear_angle[3] = 0;         leg_right_rear_angle[3] = 0;         leg_left_front_angle[3] = 0;         leg_right_front_angle[3] = 0;\n                                    time_duration[3] = 0.1 / FASTER;       time_space[3] = .0;\n\n                                    shoulder_left_rear_angle[4] = 500;  shoulder_right_rear_angle[4] = 0;    shoulder_left_front_angle[4] = 500;  shoulder_right_front_angle[4] = 500;\n                                    leg_left_rear_angle[4] = 0;         leg_right_rear_angle[4] = 0;         leg_left_front_angle[4] = 0;         leg_right_front_angle[4] = 256;\n                                    time_duration[4] = 0.1 / FASTER;       time_space[4] = .0;\n                                    shoulder_left_rear_angle[5] = 500;  shoulder_right_rear_angle[5] = 0;    shoulder_left_front_angle[5] = 500;  shoulder_right_front_angle[5] = 0;\n                                    leg_left_rear_angle[5] = 0;         leg_right_rear_angle[5] = 0;         leg_left_front_angle[5] = 0;         leg_right_front_angle[5] = 512;\n                                    time_duration[5] = 0.2 / FASTER;       time_space[5] = .0;\n                                    shoulder_left_rear_angle[6] = 500;  shoulder_right_rear_angle[6] = 0;    shoulder_left_front_angle[6] = 500;  shoulder_right_front_angle[6] = 0;\n                                    leg_left_rear_angle[6] = 0;         leg_right_rear_angle[6] = 0;         leg_left_front_angle[6] = 0;         leg_right_front_angle[6] = 0;\n                                    time_duration[6] = 0.1 / FASTER;       time_space[6] = .0;\n\n                                    shoulder_left_rear_angle[7] = 500;    shoulder_right_rear_angle[7] = 0;    shoulder_left_front_angle[7] = 500;    shoulder_right_front_angle[7] = 0;\n                                    leg_left_rear_angle[7] = 0;       leg_right_rear_angle[7] = 0;         leg_left_front_angle[7] = -256;         leg_right_front_angle[7] = 0;\n                                    time_duration[7] = 0.1 / FASTER;       time_space[7] = .0;\n                                    shoulder_left_rear_angle[8] = 500;  shoulder_right_rear_angle[8] = 0;    shoulder_left_front_angle[8] = 0;    shoulder_right_front_angle[8] = 0;\n                                    leg_left_rear_angle[8] = 0;       leg_right_rear_angle[8] = 0;         leg_left_front_angle[8] = -512;         leg_right_front_angle[8] = 0;\n                                    time_duration[8] = 0.2 / FASTER;       time_space[8] = .0;\n                                    shoulder_left_rear_angle[9] = 500;  shoulder_right_rear_angle[9] = 0;    shoulder_left_front_angle[9] = 0;    shoulder_right_front_angle[9] = 0;\n                                    leg_left_rear_angle[9] = 0;         leg_right_rear_angle[9] = 0;         leg_left_front_angle[9] = 0;         leg_right_front_angle[9] = 0;\n                                    time_duration[9] = 0.1 / FASTER;       time_space[9] = .0;\n\n                                    shoulder_left_rear_angle[10] = 500;    shoulder_right_rear_angle[10] = 0;    shoulder_left_front_angle[10] = 0;    shoulder_right_front_angle[10] = 0;\n                                    leg_left_rear_angle[10] = 256;       leg_right_rear_angle[10] = 0;         leg_left_front_angle[10] = 0;         leg_right_front_angle[10] = 0;\n                                    time_duration[10] = 0.1 / FASTER;       time_space[10] = .0;\n                                    shoulder_left_rear_angle[11] = 0;  shoulder_right_rear_angle[11] = 0;    shoulder_left_front_angle[11] = 0;    shoulder_right_front_angle[11] = 0;\n                                    leg_left_rear_angle[11] = 512;       leg_right_rear_angle[11] = 0;         leg_left_front_angle[11] = 0;         leg_right_front_angle[11] = 0;\n                                    time_duration[11] = 0.2 / FASTER;       time_space[11] = .0;\n                                    shoulder_left_rear_angle[12] = 0;  shoulder_right_rear_angle[12] = 0;    shoulder_left_front_angle[12] = 0;    shoulder_right_front_angle[12] = 0;\n                                    leg_left_rear_angle[12] = 0;         leg_right_rear_angle[12] = 0;         leg_left_front_angle[12] = 0;         leg_right_front_angle[12] = 0;\n                                    time_duration[12] = 0.1 / FASTER;       time_space[12] = .0;\n\n                                    mobile_mode = NONE;\n                                    pres_mobile_mode = mobile_mode;\n\n                                    break;\n       case RRIGHT:                 motion_all_num = 13;\n                                    shoulder_left_rear_angle[0] = -500;    shoulder_right_rear_angle[0] = -500;    shoulder_left_front_angle[0] = -500;    shoulder_right_front_angle[0] = -500;\n                                    leg_left_rear_angle[0] = 0;         leg_right_rear_angle[0] = 0;         leg_left_front_angle[0] = 0;         leg_right_front_angle[0] = 0;\n                                    time_duration[0] = 0.1 / FASTER;       time_space[0] = .0;\n\n                                    shoulder_left_rear_angle[1] = -500;    shoulder_right_rear_angle[1] = -500;    shoulder_left_front_angle[1] = -500;    shoulder_right_front_angle[1] = -500;\n                                    leg_left_rear_angle[1] = 256;       leg_right_rear_angle[1] = 0;         leg_left_front_angle[1] = 0;         leg_right_front_angle[1] = 0;\n                                    time_duration[1] = 0.1 / FASTER;       time_space[1] = .0;\n                                    shoulder_left_rear_angle[2] = 0;  shoulder_right_rear_angle[2] = -500;    shoulder_left_front_angle[2] = -500;    shoulder_right_front_angle[2] = -500;\n                                    leg_left_rear_angle[2] = 512;       leg_right_rear_angle[2] = 0;         leg_left_front_angle[2] = 0;         leg_right_front_angle[2] = 0;\n                                    time_duration[2] = 0.2 / FASTER;       time_space[2] = .0;\n                                    shoulder_left_rear_angle[3] = 0;  shoulder_right_rear_angle[3] = -500;    shoulder_left_front_angle[3] = -500;    shoulder_right_front_angle[3] = -500;\n                                    leg_left_rear_angle[3] = 0;         leg_right_rear_angle[3] = 0;         leg_left_front_angle[3] = 0;         leg_right_front_angle[3] = 0;\n                                    time_duration[3] = 0.1 / FASTER;       time_space[3] = .0;\n\n                                    shoulder_left_rear_angle[4] = 0;    shoulder_right_rear_angle[4] = -500;    shoulder_left_front_angle[4] = -500;    shoulder_right_front_angle[4] = -500;\n                                    leg_left_rear_angle[4] = 0;       leg_right_rear_angle[4] = 0;         leg_left_front_angle[4] = 0;         leg_right_front_angle[4] = 0;\n                                    time_duration[4] = 0.1 / FASTER;       time_space[4] = .0;\n                                    shoulder_left_rear_angle[5] = 0;  shoulder_right_rear_angle[5] = -500;    shoulder_left_front_angle[5] = 0;    shoulder_right_front_angle[5] = -500;\n                                    leg_left_rear_angle[5] = 0;       leg_right_rear_angle[5] = 0;         leg_left_front_angle[5] = -256;         leg_right_front_angle[5] = 0;\n                                    time_duration[5] = 0.2 / FASTER;       time_space[5] = .0;\n                                    shoulder_left_rear_angle[6] = 0;  shoulder_right_rear_angle[6] = -500;    shoulder_left_front_angle[6] = 0;    shoulder_right_front_angle[6] = -500;\n                                    leg_left_rear_angle[6] = 0;         leg_right_rear_angle[6] = 0;         leg_left_front_angle[6] = -512;         leg_right_front_angle[6] = 0;\n                                    time_duration[6] = 0.1 / FASTER;       time_space[6] = .0;\n\n                                    shoulder_left_rear_angle[7] = 0;    shoulder_right_rear_angle[7] = -500;    shoulder_left_front_angle[7] = 0;    shoulder_right_front_angle[7] = -500;\n                                    leg_left_rear_angle[7] = 0;       leg_right_rear_angle[7] = 0;         leg_left_front_angle[7] = 0;         leg_right_front_angle[7] = 0;\n                                    time_duration[7] = 0.1 / FASTER;       time_space[7] = .0;\n                                    shoulder_left_rear_angle[8] = 0;  shoulder_right_rear_angle[8] = -500;    shoulder_left_front_angle[8] = 0;    shoulder_right_front_angle[8] = 0;\n                                    leg_left_rear_angle[8] = 0;       leg_right_rear_angle[8] = 0;         leg_left_front_angle[8] = 0;         leg_right_front_angle[8] = 256;\n                                    time_duration[8] = 0.2 / FASTER;       time_space[8] = .0;\n                                    shoulder_left_rear_angle[9] = 0;  shoulder_right_rear_angle[9] = -500;    shoulder_left_front_angle[9] = 0;    shoulder_right_front_angle[9] = 0;\n                                    leg_left_rear_angle[9] = 0;         leg_right_rear_angle[9] = 0;         leg_left_front_angle[9] = 0;         leg_right_front_angle[9] = 512;\n                                    time_duration[9] = 0.1 / FASTER;       time_space[9] = .0;\n\n                                    shoulder_left_rear_angle[10] = 0;    shoulder_right_rear_angle[10] = -500;    shoulder_left_front_angle[10] = 0;    shoulder_right_front_angle[10] = 0;\n                                    leg_left_rear_angle[10] = 0;       leg_right_rear_angle[10] = -256;         leg_left_front_angle[10] = 0;         leg_right_front_angle[10] = 0;\n                                    time_duration[10] = 0.1 / FASTER;       time_space[10] = .0;\n                                    shoulder_left_rear_angle[11] = 0;  shoulder_right_rear_angle[11] = 0;    shoulder_left_front_angle[11] = 0;    shoulder_right_front_angle[11] = 0;\n                                    leg_left_rear_angle[11] = 0;       leg_right_rear_angle[11] = -512;         leg_left_front_angle[11] = 0;         leg_right_front_angle[11] = 0;\n                                    time_duration[11] = 0.2 / FASTER;       time_space[11] = .0;\n                                    shoulder_left_rear_angle[12] = 0;  shoulder_right_rear_angle[12] = 0;    shoulder_left_front_angle[12] = 0;    shoulder_right_front_angle[12] = 0;\n                                    leg_left_rear_angle[12] = 0;         leg_right_rear_angle[12] = 0;         leg_left_front_angle[12] = 0;         leg_right_front_angle[12] = 0;\n                                    time_duration[12] = 0.1 / FASTER;       time_space[12] = .0;\n\n                                    mobile_mode = NONE;\n                                    pres_mobile_mode = mobile_mode;\n\n                                    break;\n\n      default:              motion_all_num = 1;\n                            shoulder_left_rear_angle[0] = 0; shoulder_right_rear_angle[0] = 0; shoulder_left_front_angle[0] = 0; shoulder_right_front_angle[0] = 0;\n                            leg_left_rear_angle[0] = 0; leg_right_rear_angle[0] = 0; leg_left_front_angle[0] = 0; leg_right_front_angle[0] = 0;\n                            time_duration[0] = 1.0; time_space[0] = 1.0;\n                            break;\n      }\n    }\n\n    int showMode()\n    {\n      return (int)mobile_mode;\n    }\n\n    int* setJointAngle(int motion_num)\n    {\n      if (leg_left_rear_angle[motion_num] < 0)\n      {\n        leg_left_rear_angle[motion_num] = 0;\n      }\n      else if (leg_left_rear_angle[motion_num] > 512)\n      {\n        leg_left_rear_angle[motion_num] = 512;\n      }\n\n      if (leg_right_rear_angle[motion_num] < -512)\n      {\n        leg_right_rear_angle[motion_num] = -512;\n      }\n      else if (leg_right_rear_angle[motion_num] > 0)\n      {\n        leg_right_rear_angle[motion_num] = 0;\n      }\n\n      if (leg_left_front_angle[motion_num] < -512)\n      {\n        leg_left_front_angle[motion_num] = -512;\n      }\n      else if (leg_left_front_angle[motion_num] > 0)\n      {\n        leg_left_front_angle[motion_num] = 0;\n      }\n\n      if (leg_right_front_angle[motion_num] < 0)\n      {\n        leg_right_front_angle[motion_num] = 0;\n      }\n      else if (leg_right_front_angle[motion_num] > 512)\n      {\n        leg_right_front_angle[motion_num] = 512;\n      }\n\n      if (shoulder_left_rear_angle[motion_num] < -1024)\n      {\n        shoulder_left_rear_angle[motion_num] = -1024;\n      }\n      else if (shoulder_left_rear_angle[motion_num] > 1024)\n      {\n        shoulder_left_rear_angle[motion_num] = 1024;\n      }\n\n      if (shoulder_right_rear_angle[motion_num] < -1024)\n      {\n        shoulder_right_rear_angle[motion_num] = -1024;\n      }\n      else if (shoulder_right_rear_angle[motion_num] > 1024)\n      {\n        shoulder_right_rear_angle[motion_num] = 1024;\n      }\n\n      if (shoulder_left_front_angle[motion_num] < -1024)\n      {\n        shoulder_left_front_angle[motion_num] = -1024;\n      }\n      else if (shoulder_left_front_angle[motion_num] > 768)\n      {\n        shoulder_left_front_angle[motion_num] = 768;\n      }\n\n      if (shoulder_right_front_angle[motion_num] < -768)\n      {\n        shoulder_right_front_angle[motion_num] = -768;\n      }\n      else if (shoulder_right_front_angle[motion_num] > 1024)\n      {\n        shoulder_right_front_angle[motion_num] = 1024;\n      }\n\n      joint_angle[0] = leg_left_rear_angle[motion_num] + 1024;\n      joint_angle[1] = leg_right_rear_angle[motion_num] + 3072;\n      joint_angle[2] = leg_left_front_angle[motion_num] + 3072;\n      joint_angle[3] = leg_right_front_angle[motion_num] + 1024;\n      joint_angle[4] = shoulder_left_rear_angle[motion_num] + 2048;\n      joint_angle[5] = shoulder_right_rear_angle[motion_num] + 2048;\n      joint_angle[6] = shoulder_left_front_angle[motion_num] + 2048;\n      joint_angle[7] = shoulder_right_front_angle[motion_num] + 2048;\n\n      return joint_angle;\n    }\n};\n\n#endif // TURTLEBOT3_REALTURTLEBOT_MOTION_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_realturtlebot/turtlebot3_realturtlebot_motor_driver.cpp",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#include \"turtlebot3_realturtlebot_motor_driver.h\"\n\nTurtlebot3MotorDriver::Turtlebot3MotorDriver()\n: baudrate_(BAUDRATE),\n  protocol_version_(PROTOCOL_VERSION)\n{\n}\n\nTurtlebot3MotorDriver::~Turtlebot3MotorDriver()\n{\n  closeDynamixel();\n}\n\nbool Turtlebot3MotorDriver::init(void)\n{\n  portHandler_   = dynamixel::PortHandler::getPortHandler(DEVICENAME);\n  packetHandler_ = dynamixel::PacketHandler::getPacketHandler(PROTOCOL_VERSION);\n\n  // Open port\n  if (portHandler_->openPort())\n  {\n    ERROR_PRINT(\"Port is opened\");\n  }\n  else\n  {\n    ERROR_PRINT(\"Port couldn't be opened\");\n\n    return false;\n  }\n\n  // Set port baudrate\n  if (portHandler_->setBaudRate(baudrate_))\n  {\n    ERROR_PRINT(\"Baudrate is set\");\n  }\n  else\n  {\n    ERROR_PRINT(\"Baudrate couldn't be set\");\n\n    return false;\n  }\n\n  // Enable Dynamixel Torque\n  setTorque(DXL_LEG_LEFT_REAR_ID, true);\n  setTorque(DXL_LEG_RIGHT_REAR_ID, true);\n  setTorque(DXL_LEG_LEFT_FRONT_ID, true);\n  setTorque(DXL_LEG_RIGHT_FRONT_ID, true);\n  setTorque(DXL_SHOULDER_LEFT_REAR_ID, true);\n  setTorque(DXL_SHOULDER_RIGHT_REAR_ID, true);\n  setTorque(DXL_SHOULDER_LEFT_FRONT_ID, true);\n  setTorque(DXL_SHOULDER_RIGHT_FRONT_ID, true);\n  setTorque(DXL_HEAD_YAW_ID, true);\n  setTorque(DXL_HEAD_PITCH_ID, true);\n\n  // setProfileVelocity(front_joint_id_, 120); //TODO : precise calculation\n\n  return true;\n}\n\nbool Turtlebot3MotorDriver::setTorque(uint8_t id, bool onoff)\n{\n  uint8_t dxl_error = 0;\n  int dxl_comm_result = COMM_TX_FAIL;\n\n  dxl_comm_result = packetHandler_->write1ByteTxRx(portHandler_, id, ADDR_X_TORQUE_ENABLE, onoff, &dxl_error);\n  if(dxl_comm_result != COMM_SUCCESS)\n  {\n    packetHandler_->getTxRxResult(dxl_comm_result);\n  }\n  else if(dxl_error != 0)\n  {\n    packetHandler_->getRxPacketError(dxl_error);\n  }\n}\n\nbool Turtlebot3MotorDriver::setProfileAcceleration(uint8_t id, uint32_t value)\n{\n  uint8_t dxl_error = 0;\n  int dxl_comm_result = COMM_TX_FAIL;\n\n  dxl_comm_result = packetHandler_->write4ByteTxRx(portHandler_, id, ADDR_X_PROFILE_ACCELERATION, value, &dxl_error);\n  if (dxl_comm_result != COMM_SUCCESS)\n  {\n    packetHandler_->getTxRxResult(dxl_comm_result);\n  }\n  else if(dxl_error != 0)\n  {\n    packetHandler_->getRxPacketError(dxl_error);\n  }\n}\n\nbool Turtlebot3MotorDriver::setProfileVelocity(uint8_t id, uint32_t value)\n{\n  uint8_t dxl_error = 0;\n  int dxl_comm_result = COMM_TX_FAIL;\n\n  dxl_comm_result = packetHandler_->write4ByteTxRx(portHandler_, id, ADDR_X_PROFILE_VELOCITY, value, &dxl_error);\n  if(dxl_comm_result != COMM_SUCCESS)\n  {\n    packetHandler_->getTxRxResult(dxl_comm_result);\n  }\n  else if(dxl_error != 0)\n  {\n    packetHandler_->getRxPacketError(dxl_error);\n  }\n}\n\nvoid Turtlebot3MotorDriver::closeDynamixel(void)\n{\n  // Disable Dynamixel Torque\n  setTorque(DXL_LEG_LEFT_REAR_ID, false);\n  setTorque(DXL_LEG_RIGHT_REAR_ID, false);\n  setTorque(DXL_LEG_LEFT_FRONT_ID, false);\n  setTorque(DXL_LEG_RIGHT_FRONT_ID, false);\n  setTorque(DXL_SHOULDER_LEFT_REAR_ID, false);\n  setTorque(DXL_SHOULDER_RIGHT_REAR_ID, false);\n  setTorque(DXL_SHOULDER_LEFT_FRONT_ID, false);\n  setTorque(DXL_SHOULDER_RIGHT_FRONT_ID, false);\n  setTorque(DXL_HEAD_YAW_ID, false);\n  setTorque(DXL_HEAD_PITCH_ID, false);\n\n  // Close port\n  portHandler_->closePort();\n}\n\nvoid Turtlebot3MotorDriver::syncWrite(int address, int length, int value)\n{\n  // Initialize GroupSyncWrite instance\n  dynamixel::GroupSyncWrite groupSyncWrite(portHandler_, packetHandler_, address, length);\n\n  // Add Dynamixels goal values to the Syncwrite storage\n  groupSyncWrite.addParam(DXL_LEG_LEFT_REAR_ID, (uint8_t*)&value);\n  groupSyncWrite.addParam(DXL_LEG_RIGHT_REAR_ID, (uint8_t*)&value);\n  groupSyncWrite.addParam(DXL_LEG_LEFT_FRONT_ID, (uint8_t*)&value);\n  groupSyncWrite.addParam(DXL_LEG_RIGHT_FRONT_ID, (uint8_t*)&value);\n  groupSyncWrite.addParam(DXL_SHOULDER_LEFT_REAR_ID, (uint8_t*)&value);\n  groupSyncWrite.addParam(DXL_SHOULDER_RIGHT_REAR_ID, (uint8_t*)&value);\n  groupSyncWrite.addParam(DXL_SHOULDER_LEFT_FRONT_ID, (uint8_t*)&value);\n  groupSyncWrite.addParam(DXL_SHOULDER_RIGHT_FRONT_ID, (uint8_t*)&value);\n\n  // Syncwrite goal position\n  groupSyncWrite.txPacket();\n\n  // Clear syncwrite parameter storage\n  groupSyncWrite.clearParam();\n}\n\nvoid Turtlebot3MotorDriver::syncWrite(int address, int length, int* value)\n{\n  // Initialize GroupSyncWrite instance\n  dynamixel::GroupSyncWrite groupSyncWrite(portHandler_, packetHandler_, address, length);\n\n  // Add Dynamixels goal values to the Syncwrite storage\n  groupSyncWrite.addParam(DXL_LEG_LEFT_REAR_ID, (uint8_t*)&value[0]);\n  groupSyncWrite.addParam(DXL_LEG_RIGHT_REAR_ID, (uint8_t*)&value[1]);\n  groupSyncWrite.addParam(DXL_LEG_LEFT_FRONT_ID, (uint8_t*)&value[2]);\n  groupSyncWrite.addParam(DXL_LEG_RIGHT_FRONT_ID, (uint8_t*)&value[3]);\n  groupSyncWrite.addParam(DXL_SHOULDER_LEFT_REAR_ID, (uint8_t*)&value[4]);\n  groupSyncWrite.addParam(DXL_SHOULDER_RIGHT_REAR_ID, (uint8_t*)&value[5]);\n  groupSyncWrite.addParam(DXL_SHOULDER_LEFT_FRONT_ID, (uint8_t*)&value[6]);\n  groupSyncWrite.addParam(DXL_SHOULDER_RIGHT_FRONT_ID, (uint8_t*)&value[7]);\n\n  // Syncwrite goal position\n  groupSyncWrite.txPacket();\n\n  // Clear syncwrite parameter storage\n  groupSyncWrite.clearParam();\n}\n\nvoid Turtlebot3MotorDriver::syncRead(int address, int length, int* readValues)\n{\n  // Initialize Groupsyncread instance for Present Position\n  dynamixel::GroupSyncRead groupSyncRead(portHandler_, packetHandler_, address, length);\n\n  // Add parameter storage for Dynamixel#1 present position value\n  groupSyncRead.addParam(DXL_LEG_LEFT_REAR_ID);\n  groupSyncRead.addParam(DXL_LEG_RIGHT_REAR_ID);\n  groupSyncRead.addParam(DXL_LEG_LEFT_FRONT_ID);\n  groupSyncRead.addParam(DXL_LEG_RIGHT_FRONT_ID);\n  groupSyncRead.addParam(DXL_SHOULDER_LEFT_REAR_ID);\n  groupSyncRead.addParam(DXL_SHOULDER_RIGHT_REAR_ID);\n  groupSyncRead.addParam(DXL_SHOULDER_LEFT_FRONT_ID);\n  groupSyncRead.addParam(DXL_SHOULDER_RIGHT_FRONT_ID);\n\n  groupSyncRead.txRxPacket();\n\n  readValues[0] = (int)groupSyncRead.getData(DXL_LEG_LEFT_REAR_ID, address, length);\n  readValues[1] = (int)groupSyncRead.getData(DXL_LEG_RIGHT_REAR_ID, address, length);\n  readValues[2] = (int)groupSyncRead.getData(DXL_LEG_LEFT_FRONT_ID, address, length);\n  readValues[3] = (int)groupSyncRead.getData(DXL_LEG_RIGHT_FRONT_ID, address, length);\n  readValues[4] = (int)groupSyncRead.getData(DXL_SHOULDER_LEFT_REAR_ID, address, length);\n  readValues[5] = (int)groupSyncRead.getData(DXL_SHOULDER_RIGHT_REAR_ID, address, length);\n  readValues[6] = (int)groupSyncRead.getData(DXL_SHOULDER_LEFT_FRONT_ID, address, length);\n  readValues[7] = (int)groupSyncRead.getData(DXL_SHOULDER_RIGHT_FRONT_ID, address, length);\n\n  groupSyncRead.clearParam();\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_realturtlebot/turtlebot3_realturtlebot_motor_driver.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#ifndef TURTLEBOT3_REALTURTLEBOT_MOTOR_DRIVER_H_\n#define TURTLEBOT3_REALTURTLEBOT_MOTOR_DRIVER_H_\n\n#include <DynamixelSDK.h>\n\n// Control table address (Dynamixel X-series)\n#define ADDR_X_TORQUE_ENABLE            64\n#define ADDR_X_GOAL_VELOCITY            104\n#define ADDR_X_PROFILE_ACCELERATION     108\n#define ADDR_X_PROFILE_VELOCITY         112\n#define ADDR_X_GOAL_POSITION            116\n#define ADDR_X_REALTIME_TICK            120\n#define ADDR_X_PRESENT_VELOCITY         128\n#define ADDR_X_PRESENT_POSITION         132\n\n// Limit values (XM430-W210-T)\n#define LIMIT_X_MAX_VELOCITY            240\n\n// Data Byte Length\n#define LEN_X_TORQUE_ENABLE             1\n#define LEN_X_GOAL_VELOCITY             4\n#define LEN_X_GOAL_POSITION             4\n#define LEN_X_REALTIME_TICK             2\n#define LEN_X_PRESENT_VELOCITY          4\n#define LEN_X_PRESENT_POSITION          4\n\n#define PROTOCOL_VERSION                2.0     // Dynamixel protocol version 2.0\n\n#define DXL_LEG_LEFT_REAR_ID            1       // ID of left rear leg motor\n#define DXL_LEG_RIGHT_REAR_ID           2       // ID of right rear leg motor\n#define DXL_LEG_LEFT_FRONT_ID           3       // ID of left front leg motor\n#define DXL_LEG_RIGHT_FRONT_ID          4       // ID of right front leg motor\n#define DXL_SHOULDER_LEFT_REAR_ID       5       // ID of left rear shoulder motor\n#define DXL_SHOULDER_RIGHT_REAR_ID      6       // ID of right rear shoulder motor\n#define DXL_SHOULDER_LEFT_FRONT_ID      7       // ID of left front shoulder motor\n#define DXL_SHOULDER_RIGHT_FRONT_ID     8       // ID of right front shoulder motor\n#define DXL_HEAD_YAW_ID                 9       // ID of head yaw motor\n#define DXL_HEAD_PITCH_ID               10      // ID of head pitch motor\n\n\n#define BAUDRATE                        1000000 // baud rate of Dynamixel\n#define DEVICENAME                      \"\"      // no need setting on OpenCR\n\n#define TORQUE_ENABLE                   1       // Value for enabling the torque\n#define TORQUE_DISABLE                  0       // Value for disabling the torque\n\n#define X_POS_MIN                       0\n#define X_POS_MAX                       4095\n#define X_POS_CENTER                    2048\n\nclass Turtlebot3MotorDriver\n{\n public:\n  Turtlebot3MotorDriver();\n  ~Turtlebot3MotorDriver();\n  bool init(void);\n  void closeDynamixel(void);\n  bool setTorque(uint8_t id, bool onoff);\n  bool setProfileAcceleration(uint8_t id, uint32_t value);\n  bool setProfileVelocity(uint8_t id, uint32_t value);\n  void syncWrite(int address, int length, int value);\n  void syncWrite(int address, int length, int* value);\n  void syncRead(int address, int length, int* readValues);\n\n\n private:\n  uint32_t baudrate_;\n  float  protocol_version_;\n\n  dynamixel::PortHandler *portHandler_;\n  dynamixel::PacketHandler *packetHandler_;\n};\n\n#endif // TURTLEBOT3_REALTURTLEBOT_MOTOR_DRIVER_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_road_train/turtlebot3_road_train.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho, Ashe Kim */\n\n#include <math.h>\n\n#include <RC100.h>\n\n#include \"turtlebot3_road_train_motor_driver.h\"\n\n#define WHEEL_RADIUS                    0.033     // meter\n#define WHEEL_SEPARATION                0.160     // meter (BURGER => 0.16, WAFFLE => 0.287)\n// #define ROBOT_LENGTH                    0.165     // meter\n\n#define ENCODER_MIN                     -2147483648     // raw\n#define ENCODER_MAX                     2147483648      // raw\n\n#define VELOCITY_CONSTANT_VAULE         1263.632956882  // V = r * w = r * RPM * 0.10472\n                                                        //   = 0.033 * 0.229 * Goal RPM * 0.10472\n                                                        // Goal RPM = V * 1263.632956882\n\n#define CONTROL_PERIOD                  8000\n\n#define MAX_LINEAR_VELOCITY             0.22   // m/s\n#define MAX_ANGULAR_VELOCITY            2.84   // rad/s\n#define VELOCITY_LINEAR_X               0.01   // m/s\n#define VELOCITY_ANGULAR_Z              0.1    // rad/s\n#define SCALE_VELOCITY_LINEAR_X         1\n#define SCALE_VELOCITY_ANGULAR_Z        1\n\n#define DEG2RAD(x)                      (x * 0.01745329252)  // *PI/180\n#define RAD2DEG(x)                      (x * 57.2957795131)  // *180/PI\n\n// Function prototypes\nvoid receiveRemoteControlData(void);\nvoid controlMotorSpeed(void);\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_road_train/turtlebot3_road_train.ino",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho, Ashe Kim */\n\n#include \"turtlebot3_road_train.h\"\n\n/*******************************************************************************\n* Declaration for Hardware Timer (Interrupt control)\n*******************************************************************************/\nHardwareTimer Timer(TIMER_CH1);\n\n/*******************************************************************************\n* Declaration for RC100 remote conroller\n*******************************************************************************/\nRC100 remote_controller;\ndouble const_cmd_vel    = 0.2;\n\n/*******************************************************************************\n* Declaration for motor\n*******************************************************************************/\nTurtlebot3MotorDriver motor_driver;\n\ndouble linear_x              = 0.0;\ndouble angular_z             = 0.0;\ndouble goal_linear_velocity  = 0.0;\ndouble goal_angular_velocity = 0.0;\n\nvoid setup()\n{\n  // Setting for Dynamixel motors\n  motor_driver.init();\n\n  // Setting for RC100 remote control and cmd_vel\n  remote_controller.begin(1);  //57600bps for RC100\n\n  pinMode(13, OUTPUT);\n\n  SerialBT2.begin(57600);\n\n  // Start Dynamixel Control Interrupt\n  startDynamixelControlInterrupt();\n}\n\nvoid loop()\n{\n  receiveRemoteControlData();\n}\n\nvoid startDynamixelControlInterrupt()\n{\n  Timer.pause();\n  Timer.setPeriod(CONTROL_PERIOD);           // in microseconds\n  Timer.attachInterrupt(controlRoadTrain);\n  Timer.refresh();\n  Timer.resume();\n}\n\n/*******************************************************************************\n* Receive RC100 remote controller data\n*******************************************************************************/\nvoid receiveRemoteControlData(void)\n{\n  int received_data = 0;\n\n  if (remote_controller.available())\n  {\n    received_data = remote_controller.readData();\n\n    if (received_data & RC100_BTN_U)\n    {\n      linear_x  += VELOCITY_LINEAR_X * SCALE_VELOCITY_LINEAR_X;\n    }\n    else if (received_data & RC100_BTN_D)\n    {\n      linear_x  -= VELOCITY_LINEAR_X * SCALE_VELOCITY_LINEAR_X;\n    }\n\n    if (received_data & RC100_BTN_L)\n    {\n      angular_z += VELOCITY_ANGULAR_Z * SCALE_VELOCITY_ANGULAR_Z;\n    }\n    else if (received_data & RC100_BTN_R)\n    {\n      angular_z -= VELOCITY_ANGULAR_Z * SCALE_VELOCITY_ANGULAR_Z;\n    }\n\n    if (received_data & RC100_BTN_1)\n    {\n\n    }\n    else if (received_data & RC100_BTN_2)\n    {\n\n    }\n    else if (received_data & RC100_BTN_3)\n    {\n\n    }\n    else if (received_data & RC100_BTN_4)\n    {\n\n    }\n\n    if (received_data & RC100_BTN_6)\n    {\n      linear_x  = const_cmd_vel;\n      angular_z = 0.0;\n    }\n    else if (received_data & RC100_BTN_5)\n    {\n      linear_x  = 0.0;\n      angular_z = 0.0;\n    }\n\n    if (linear_x > MAX_LINEAR_VELOCITY)\n    {\n      linear_x = MAX_LINEAR_VELOCITY;\n    }\n\n    if (angular_z > MAX_ANGULAR_VELOCITY)\n    {\n      angular_z = MAX_ANGULAR_VELOCITY;\n    }\n\n    goal_linear_velocity  = linear_x;\n    goal_angular_velocity = angular_z;\n  }\n}\n\n/*******************************************************************************\n* Control road_train speed\n*******************************************************************************/\nvoid controlRoadTrain()\n{\n  bool dxl_comm_result = false;\n\n  double wheel1_spd_cmd, wheel2_spd_cmd;\n  double lin_vel1, lin_vel2;\n  double rotation_center;\n\n  wheel1_spd_cmd = goal_linear_velocity - (goal_angular_velocity * WHEEL_SEPARATION / 2);\n  wheel2_spd_cmd = goal_linear_velocity + (goal_angular_velocity * WHEEL_SEPARATION / 2);\n\n\n  lin_vel1 = wheel1_spd_cmd * VELOCITY_CONSTANT_VAULE;\n  if (lin_vel1 > LIMIT_X_MAX_VELOCITY)\n  {\n    lin_vel1 =  LIMIT_X_MAX_VELOCITY;\n  }\n  else if (lin_vel1 < -LIMIT_X_MAX_VELOCITY)\n  {\n    lin_vel1 = -LIMIT_X_MAX_VELOCITY;\n  }\n\n  lin_vel2 =  wheel2_spd_cmd * VELOCITY_CONSTANT_VAULE;\n  if (lin_vel2 > LIMIT_X_MAX_VELOCITY)\n  {\n    lin_vel2 =  LIMIT_X_MAX_VELOCITY;\n  }\n  else if (lin_vel2 < -LIMIT_X_MAX_VELOCITY)\n  {\n    lin_vel2 = -LIMIT_X_MAX_VELOCITY;\n  }\n\n  dxl_comm_result = motor_driver.controlMotor((int64_t)lin_vel1, (int64_t)lin_vel2);\n  if (dxl_comm_result == false)\n    return;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_road_train/turtlebot3_road_train_motor_driver.cpp",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho, Ashe Kim */\n\n#include \"turtlebot3_road_train_motor_driver.h\"\n\nTurtlebot3MotorDriver::Turtlebot3MotorDriver()\n: baudrate_(BAUDRATE),\n  protocol_version_(PROTOCOL_VERSION),\n  left_wheel_id_(DXL_LEFT_ID), right_wheel_id_(DXL_RIGHT_ID)\n{\n}\n\nTurtlebot3MotorDriver::~Turtlebot3MotorDriver()\n{\n  closeDynamixel();\n}\n\nbool Turtlebot3MotorDriver::init(void)\n{\n  portHandler_   = dynamixel::PortHandler::getPortHandler(DEVICENAME);\n  packetHandler_ = dynamixel::PacketHandler::getPacketHandler(PROTOCOL_VERSION);\n\n  // Open port\n  if (portHandler_->openPort())\n  {\n    ERROR_PRINT(\"Port is opened\");\n  }\n  else\n  {\n    ERROR_PRINT(\"Port couldn't be opened\");\n\n    return false;\n  }\n\n  // Set port baudrate\n  if (portHandler_->setBaudRate(baudrate_))\n  {\n    ERROR_PRINT(\"Baudrate is set\");\n  }\n  else\n  {\n    ERROR_PRINT(\"Baudrate couldn't be set\");\n\n    return false;\n  }\n\n  // Enable Dynamixel Torque\n  setTorque(left_wheel_id_, true);\n  setTorque(right_wheel_id_, true);\n\n  groupSyncWriteVelocity_ = new dynamixel::GroupSyncWrite(portHandler_, packetHandler_, ADDR_X_GOAL_VELOCITY, LEN_X_GOAL_VELOCITY);\n\n  return true;\n}\n\nbool Turtlebot3MotorDriver::setTorque(uint8_t id, bool onoff)\n{\n  uint8_t dxl_error = 0;\n  int dxl_comm_result = COMM_TX_FAIL;\n\n  dxl_comm_result = packetHandler_->write1ByteTxRx(portHandler_, id, ADDR_X_TORQUE_ENABLE, onoff, &dxl_error);\n  if(dxl_comm_result != COMM_SUCCESS)\n  {\n    packetHandler_->getTxRxResult(dxl_comm_result);\n  }\n  else if(dxl_error != 0)\n  {\n    packetHandler_->getRxPacketError(dxl_error);\n  }\n}\n\nvoid Turtlebot3MotorDriver::closeDynamixel(void)\n{\n  // Disable Dynamixel Torque\n  setTorque(left_wheel_id_, false);\n  setTorque(right_wheel_id_, false);\n\n  // Close port\n  portHandler_->closePort();\n}\n\nbool Turtlebot3MotorDriver::controlMotor( int64_t left_wheel_value, int64_t right_wheel_value)\n{\n  bool dxl_addparam_result_;\n  int8_t dxl_comm_result_;\n\n  dxl_addparam_result_ = groupSyncWriteVelocity_->addParam(left_wheel_id_, (uint8_t*)&left_wheel_value);\n  if (dxl_addparam_result_ != true)\n    return false;\n\n  dxl_addparam_result_ = groupSyncWriteVelocity_->addParam(right_wheel_id_, (uint8_t*)&right_wheel_value);\n  if (dxl_addparam_result_ != true)\n    return false;\n\n  dxl_comm_result_ = groupSyncWriteVelocity_->txPacket();\n  if (dxl_comm_result_ != COMM_SUCCESS)\n  {\n    packetHandler_->getTxRxResult(dxl_comm_result_);\n    return false;\n  }\n\n  groupSyncWriteVelocity_->clearParam();\n  return true;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_road_train/turtlebot3_road_train_motor_driver.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho, Ashe Kim */\n\n#ifndef TURTLEBOT3_ROADTRAIN_MOTOR_DRIVER_H_\n#define TURTLEBOT3_ROADTRAIN_MOTOR_DRIVER_H_\n\n#include <DynamixelSDK.h>\n\n// Control table address (Dynamixel X-series)\n#define ADDR_X_TORQUE_ENABLE            64\n#define ADDR_X_GOAL_VELOCITY            104\n#define ADDR_X_GOAL_POSITION            116\n#define ADDR_X_REALTIME_TICK            120\n#define ADDR_X_PRESENT_VELOCITY         128\n#define ADDR_X_PRESENT_POSITION         132\n\n// Limit values (XM430-W210-T)\n#define LIMIT_X_MAX_VELOCITY            240\n\n// Data Byte Length\n#define LEN_X_TORQUE_ENABLE             1\n#define LEN_X_GOAL_VELOCITY             4\n#define LEN_X_GOAL_POSITION             4\n#define LEN_X_REALTIME_TICK             2\n#define LEN_X_PRESENT_VELOCITY          4\n#define LEN_X_PRESENT_POSITION          4\n\n#define PROTOCOL_VERSION                2.0     // Dynamixel protocol version 2.0\n\n#define DXL_LEFT_ID                     1       // ID of left motor\n#define DXL_RIGHT_ID                    2       // ID of right motor\n#define BAUDRATE                        1000000 // baud rate of Dynamixel\n#define DEVICENAME                      \"\"      // no need setting on OpenCR\n\n#define TORQUE_ENABLE                   1       // Value for enabling the torque\n#define TORQUE_DISABLE                  0       // Value for disabling the torque\n\nclass Turtlebot3MotorDriver\n{\n public:\n  Turtlebot3MotorDriver();\n  ~Turtlebot3MotorDriver();\n  bool init(void);\n  void closeDynamixel(void);\n  bool setTorque(uint8_t id, bool onoff);\n  bool setProfileAcceleration(uint8_t id, uint32_t value);\n  bool setProfileVelocity(uint8_t id, uint32_t value);\n  bool controlMotor(int64_t left_wheel_value, int64_t right_wheel_value);\n\n private:\n  uint32_t baudrate_;\n  float  protocol_version_;\n  uint8_t left_wheel_id_, right_wheel_id_;\n\n  dynamixel::PortHandler *portHandler_;\n  dynamixel::PacketHandler *packetHandler_;\n\n  dynamixel::GroupSyncWrite *groupSyncWriteVelocity_;\n};\n\n#endif // TURTLEBOT3_ROADTRAIN_MOTOR_DRIVER_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_segway/turtlebot3_segway.h",
    "content": "#ifndef TURTLEBOT3_EXAMPLE06_SEGWAY_CONFIG_H\n#define TURTLEBOT3_EXAMPLE06_SEGWAY_CONFIG_H\n\n#include <IMU.h>\n#include <Filters.h>\n\n#include \"turtlebot3_segway_motor_driver.h\"\n\n#define DEBUG\n\n#define PWM_LIMIT                       885\n#define CONTOL_PERIOD                   7000     // in microseconds\n\nvoid startDynamixelControlInterrupt();\nvoid imuInit();\nvoid getAngle(float angle[3]);\nvoid controlSegway();\n\n#endif // TURTLEBOT3_EXAMPLE06_SEGWAY_CONFIG_H\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_segway/turtlebot3_segway.ino",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#include \"turtlebot3_segway.h\"\n\n/*******************************************************************************\n* Declaration for Hardware Timer (Interrupt control)\n*******************************************************************************/\nHardwareTimer Timer(TIMER_CH1);\n\n/*******************************************************************************\n* Declaration for IMU\n*******************************************************************************/\ncIMU IMU;\n\n/*******************************************************************************\n* Declaration for Filter\n*******************************************************************************/\nfloat filterFrequency = 1.0;    // Hz\nFilterOnePole lowpassFilter(LOWPASS, filterFrequency);\n\n/*******************************************************************************\n* Declaration for motor\n*******************************************************************************/\nTurtlebot3MotorDriver motor_driver;\n\nfloat angle[3] = {0.0,0.0,0.0}; //roll, pitch, yaw\n\n// initial angle offset\nfloat angle_offset = 0.0;\n\n// keyboard input\nchar keyboard;\n\n// Set PID gain\nfloat p_gain = 4000.0;\nfloat i_gain = 2.0;\nfloat d_gain = 78.0;\n\nfloat control_output = 0.0;\n\nvoid setup()\n{\n  // Setting for Dynamixel motors\n  motor_driver.init();\n\n  // Initialization IMU\n  imuInit();\n}\n\nvoid loop()\n{\n  if (IMU.update() > 0)\n    getAngle(angle);\n\n#ifdef DEBUG\n  if (Serial.available())\n  {\n    keyboard = Serial.read();\n    if (keyboard == 'u')\n    {\n      p_gain = p_gain + 1.0;\n    }\n    else if (keyboard == 'j')\n    {\n      p_gain = p_gain - 1.0;\n    }\n    else if (keyboard == 'o')\n    {\n      d_gain = d_gain + 0.1;\n    }\n    else if (keyboard == 'l')\n    {\n      d_gain = d_gain - 0.1;\n    }\n    else if (keyboard == 'i')\n    {\n      i_gain = i_gain + 0.1;\n    }\n    else if (keyboard == 'k')\n    {\n      i_gain = i_gain - 0.1;\n    }\n    else if (keyboard == 'a')\n    {\n      angle_offset = angle_offset + 0.01;\n    }\n    else if (keyboard == 's')\n    {\n      angle_offset = angle_offset - 0.01;\n    }\n  }\n\n  Serial.print(\" P : \");\n  Serial.print(p_gain);\n  Serial.print(\" I : \");\n  Serial.print(i_gain);\n  Serial.print(\" D : \");\n  Serial.print(d_gain);\n  Serial.print(\" offset : \");\n  Serial.print(angle_offset);\n  Serial.print(\" output : \");\n  Serial.print(control_output);\n  Serial.print(\" angle : \");\n  Serial.println(angle[0]);\n#endif\n}\n\n/*******************************************************************************\n* Get angle from IMU\n*******************************************************************************/\nvoid getAngle(float angle[3])\n{\n  float roll, pitch, yaw;\n\n  roll  = IMU.rpy[0];\n  pitch = IMU.rpy[1];\n  yaw   = IMU.rpy[2];\n\n  angle[0] = lowpassFilter.input(pitch) + angle_offset;\n  angle[1] = pitch + angle_offset;\n}\n\nvoid startDynamixelControlInterrupt()\n{\n  Timer.pause();\n  Timer.setPeriod(CONTOL_PERIOD);           // in microseconds\n  Timer.attachInterrupt(controlSegway);\n  Timer.refresh();\n  Timer.resume();\n}\n\n/*******************************************************************************\n* Initialization of IMU\n*******************************************************************************/\nvoid imuInit()\n{\n  IMU.begin();\n\n  IMU.SEN.acc_cali_start();\n  while( IMU.SEN.acc_cali_get_done() == false )\n  {\n    IMU.update();\n  }\n\n  // Start Dynamixel Control Interrupt\n  startDynamixelControlInterrupt();\n}\n\n/*******************************************************************************\n* Control segway PWM\n*******************************************************************************/\nvoid controlSegway(void)\n{\n  bool dxl_comm_result = false;\n  static float control_input = 0.0;\n\n  static float cur_error = 0.0, pre_error = 0.0, integral = 0.0, derivative = 0.0;\n  static float diff_time = 0.007;\n\n  static int16_t cnt = 0;           // timer counter\n\n  cur_error  = control_input - angle[0];\n  integral   = integral + (cur_error * diff_time);\n  derivative = (cur_error - pre_error) / diff_time;\n\n  if (cnt > 500)\n  {\n    integral = 0.0;\n    cnt = 0;\n  }\n  else\n  {\n    cnt++;\n  }\n\n  control_output = p_gain * cur_error +\n                   i_gain * integral  +\n                   d_gain * derivative;\n\n  if (control_output >= PWM_LIMIT)\n  {\n    control_output = PWM_LIMIT;\n  }\n  else if (control_output <= (-1) * PWM_LIMIT)\n  {\n    control_output = (-1) * PWM_LIMIT;\n  }\n  pre_error = cur_error;\n\n  dxl_comm_result = motor_driver.controlMotor((int64_t)control_output, (int64_t)control_output);\n  if (dxl_comm_result == false)\n    return;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_segway/turtlebot3_segway_motor_driver.cpp",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#include \"turtlebot3_segway_motor_driver.h\"\n\nTurtlebot3MotorDriver::Turtlebot3MotorDriver()\n: baudrate_(BAUDRATE),\n  protocol_version_(PROTOCOL_VERSION),\n  left_wheel_id_(DXL_LEFT_ID),\n  right_wheel_id_(DXL_RIGHT_ID)\n{\n}\n\nTurtlebot3MotorDriver::~Turtlebot3MotorDriver()\n{\n  closeDynamixel();\n}\n\nbool Turtlebot3MotorDriver::init(void)\n{\n  portHandler_   = dynamixel::PortHandler::getPortHandler(DEVICENAME);\n  packetHandler_ = dynamixel::PacketHandler::getPacketHandler(PROTOCOL_VERSION);\n\n  // Open port\n  if (portHandler_->openPort())\n  {\n    ERROR_PRINT(\"Port is opened\");\n  }\n  else\n  {\n    ERROR_PRINT(\"Port couldn't be opened\");\n\n    return false;\n  }\n\n  // Set port baudrate\n  if (portHandler_->setBaudRate(baudrate_))\n  {\n    ERROR_PRINT(\"Baudrate is set\");\n  }\n  else\n  {\n    ERROR_PRINT(\"Baudrate couldn't be set\");\n\n    return false;\n  }\n\n  // Enable Dynamixel Torque\n  setTorque(left_wheel_id_, true);\n  setTorque(right_wheel_id_, true);\n\n  groupSyncWritePWM_ = new dynamixel::GroupSyncWrite(portHandler_, packetHandler_, ADDR_X_GOAL_PWM, LEN_X_GOAL_PWM);\n\n  return true;\n}\n\nbool Turtlebot3MotorDriver::setTorque(uint8_t id, bool onoff)\n{\n  uint8_t dxl_error = 0;\n  int dxl_comm_result = COMM_TX_FAIL;\n\n  dxl_comm_result = packetHandler_->write1ByteTxRx(portHandler_, id, ADDR_X_TORQUE_ENABLE, onoff, &dxl_error);\n  if(dxl_comm_result != COMM_SUCCESS)\n  {\n    packetHandler_->getTxRxResult(dxl_comm_result);\n  }\n  else if(dxl_error != 0)\n  {\n    packetHandler_->getRxPacketError(dxl_error);\n  }\n}\n\nvoid Turtlebot3MotorDriver::closeDynamixel(void)\n{\n  // Disable Dynamixel Torque\n  setTorque(left_wheel_id_, false);\n  setTorque(right_wheel_id_, false);\n\n  // Close port\n  portHandler_->closePort();\n}\n\nbool Turtlebot3MotorDriver::controlMotor(int64_t left_wheel_value, int64_t right_wheel_value)\n{\n  bool dxl_addparam_result_;\n  int8_t dxl_comm_result_;\n\n  dxl_addparam_result_ = groupSyncWritePWM_->addParam(left_wheel_id_, (uint8_t*)&left_wheel_value);\n  if (dxl_addparam_result_ != true)\n    return false;\n\n  dxl_addparam_result_ = groupSyncWritePWM_->addParam(right_wheel_id_, (uint8_t*)&right_wheel_value);\n  if (dxl_addparam_result_ != true)\n    return false;\n\n  dxl_comm_result_ = groupSyncWritePWM_->txPacket();\n  if (dxl_comm_result_ != COMM_SUCCESS)\n  {\n    packetHandler_->getTxRxResult(dxl_comm_result_);\n    return false;\n  }\n\n  groupSyncWritePWM_->clearParam();\n  return true;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_segway/turtlebot3_segway_motor_driver.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#ifndef TURTLEBOT3_SEGWAY_MOTOR_DRIVER_H_\n#define TURTLEBOT3_SEGWAY_MOTOR_DRIVER_H_\n\n#include <DynamixelSDK.h>\n\n// Control table address (Dynamixel X-series)\n#define ADDR_X_TORQUE_ENABLE            64\n#define ADDR_X_GOAL_PWM                 100\n#define ADDR_X_GOAL_VELOCITY            104\n#define ADDR_X_PROFILE_ACCELERATION     108\n#define ADDR_X_PROFILE_VELOCITY         112\n#define ADDR_X_GOAL_POSITION            116\n#define ADDR_X_REALTIME_TICK            120\n#define ADDR_X_PRESENT_VELOCITY         128\n#define ADDR_X_PRESENT_POSITION         132\n\n// Limit values (XM430-W210-T)\n#define LIMIT_X_MAX_VELOCITY            240\n\n// Data Byte Length\n#define LEN_X_TORQUE_ENABLE             1\n#define LEN_X_GOAL_PWM                  2\n#define LEN_X_GOAL_VELOCITY             4\n#define LEN_X_GOAL_POSITION             4\n#define LEN_X_REALTIME_TICK             2\n#define LEN_X_PRESENT_VELOCITY          4\n#define LEN_X_PRESENT_POSITION          4\n\n#define PROTOCOL_VERSION                2.0     // Dynamixel protocol version 2.0\n\n#define DXL_LEFT_ID                     1       // ID of left rear motor\n#define DXL_RIGHT_ID                    2       // ID of right rear motor\n#define BAUDRATE                        1000000 // baud rate of Dynamixel\n#define DEVICENAME                      \"\"      // no need setting on OpenCR\n\n#define TORQUE_ENABLE                   1       // Value for enabling the torque\n#define TORQUE_DISABLE                  0       // Value for disabling the torque\n\nclass Turtlebot3MotorDriver\n{\n public:\n  Turtlebot3MotorDriver();\n  ~Turtlebot3MotorDriver();\n  bool init(void);\n  void closeDynamixel(void);\n  bool setTorque(uint8_t id, bool onoff);\n  bool controlMotor(int64_t left_wheel_value, int64_t right_wheel_value);\n\n private:\n  uint32_t baudrate_;\n  float  protocol_version_;\n  uint8_t left_wheel_id_, right_wheel_id_;\n\n  dynamixel::PortHandler *portHandler_;\n  dynamixel::PacketHandler *packetHandler_;\n\n  dynamixel::GroupSyncWrite *groupSyncWritePWM_;\n};\n\n#endif // TURTLEBOT3_SEGWAY_MOTOR_DRIVER_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_tank/turtlebot3_tank.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#include <math.h>\n\n#include <RC100.h>\n\n#include \"turtlebot3_tank_motor_driver.h\"\n\n#define WHEEL_RADIUS                    0.033     // meter\n#define WHEEL_SEPARATION                0.16      // meter\n#define TURNING_RADIUS                  0.080     // meter\n\n#define ENCODER_MIN                     -2147483648     // raw\n#define ENCODER_MAX                     2147483648      // raw\n\n#define RPM_CONSTANT_VALUE              0.229\n\n#define CONTROL_PERIOD                  8000\n\n#define VELOCITY_CONSTANT_VAULE         1263.632956882  // V = r * w = r * RPM * 0.10472\n                                                        //   = 0.033 * 0.229 * Goal RPM * 0.10472\n                                                        // Goal RPM = V * 1263.632956882\n\n#define MAX_LINEAR_VELOCITY             0.22   // m/s\n#define MAX_ANGULAR_VELOCITY            2.84   // rad/s\n#define VELOCITY_LINEAR_X               0.01   // m/s\n#define VELOCITY_ANGULAR_Z              0.1    // rad/s\n#define SCALE_VELOCITY_LINEAR_X         1\n#define SCALE_VELOCITY_ANGULAR_Z        1\n\n#define LIMIT_X_MAX_VALUE               480\n\n#define DEG2RAD(x)                      (x * 0.01745329252)  // *PI/180\n#define RAD2DEG(x)                      (x * 57.2957795131)  // *180/PI\n\n// Function prototypes\nvoid receiveRemoteControlData(void);\nvoid controlMotorSpeed(void);\nvoid controlTank(void);\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_tank/turtlebot3_tank.ino",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#include \"turtlebot3_tank.h\"\n\n/*******************************************************************************\n* Declaration for Hardware Timer (Interrupt control)\n*******************************************************************************/\nHardwareTimer Timer(TIMER_CH1);\n\n/*******************************************************************************\n* Declaration for RC100 remote conroller\n*******************************************************************************/\nRC100 remote_controller;\ndouble const_cmd_vel    = 0.2;\n\n/*******************************************************************************\n* Declaration for motor\n*******************************************************************************/\nTurtlebot3MotorDriver motor_driver;\n\ndouble linear_x              = 0.0;\ndouble angular_z             = 0.0;\ndouble goal_linear_velocity  = 0.0;\ndouble goal_angular_velocity = 0.0;\n\nvoid setup()\n{\n  // Setting for Dynamixel motors\n  motor_driver.init();\n\n  // Setting for RC100 remote control and cmd_vel\n  remote_controller.begin(1);  //57600bps for RC100\n\n  pinMode(13, OUTPUT);\n\n  SerialBT2.begin(57600);\n\n  // Start Dynamixel Control Interrupt\n  startDynamixelControlInterrupt();\n}\n\nvoid loop()\n{\n  receiveRemoteControlData();\n}\n\nvoid startDynamixelControlInterrupt()\n{\n  Timer.pause();\n  Timer.setPeriod(CONTROL_PERIOD);           // in microseconds\n  Timer.attachInterrupt(controlTank);\n  Timer.refresh();\n  Timer.resume();\n}\n\n/*******************************************************************************\n* Receive RC100 remote controller data\n*******************************************************************************/\nvoid receiveRemoteControlData(void)\n{\n  int received_data = 0;\n\n  if (remote_controller.available())\n  {\n    received_data = remote_controller.readData();\n\n    if (received_data & RC100_BTN_U)\n    {\n      linear_x  += VELOCITY_LINEAR_X * SCALE_VELOCITY_LINEAR_X;\n    }\n    else if (received_data & RC100_BTN_D)\n    {\n      linear_x  -= VELOCITY_LINEAR_X * SCALE_VELOCITY_LINEAR_X;\n    }\n\n    if (received_data & RC100_BTN_L)\n    {\n      angular_z += VELOCITY_ANGULAR_Z * SCALE_VELOCITY_ANGULAR_Z;\n    }\n    else if (received_data & RC100_BTN_R)\n    {\n      angular_z -= VELOCITY_ANGULAR_Z * SCALE_VELOCITY_ANGULAR_Z;\n    }\n\n    if (received_data & RC100_BTN_1)\n    {\n\n    }\n    else if (received_data & RC100_BTN_2)\n    {\n\n    }\n    else if (received_data & RC100_BTN_3)\n    {\n\n    }\n    else if (received_data & RC100_BTN_4)\n    {\n\n    }\n\n    if (received_data & RC100_BTN_6)\n    {\n      linear_x  = const_cmd_vel;\n      angular_z = 0.0;\n    }\n    else if (received_data & RC100_BTN_5)\n    {\n      linear_x  = 0.0;\n      angular_z = 0.0;\n    }\n\n    if (linear_x > MAX_LINEAR_VELOCITY)\n    {\n      linear_x = MAX_LINEAR_VELOCITY;\n    }\n\n    if (angular_z > MAX_ANGULAR_VELOCITY)\n    {\n      angular_z = MAX_ANGULAR_VELOCITY;\n    }\n\n    goal_linear_velocity  = linear_x;\n    goal_angular_velocity = angular_z;\n  }\n}\n\n/*******************************************************************************\n* Control tank speed\n*******************************************************************************/\nvoid controlTank()\n{\n  bool dxl_comm_result = false;\n\n  const int8_t motor_num = 2;\n\n  int64_t wheel_value[motor_num] = {0, 0};             //LEFT, RIGHT\n  double wheel_angular_velocity[motor_num] = {0.0, 0.0};\n\n  wheel_angular_velocity[0] = goal_linear_velocity - (goal_angular_velocity * WHEEL_SEPARATION / 2);\n  wheel_angular_velocity[1] = goal_linear_velocity + (goal_angular_velocity * WHEEL_SEPARATION / 2);\n\n  for (int id = 0; id < motor_num; id++)\n  {\n    wheel_value[id] = wheel_angular_velocity[id] * VELOCITY_CONSTANT_VAULE;\n\n    if (wheel_value[id] > LIMIT_X_MAX_VALUE)       wheel_value[id] =  LIMIT_X_MAX_VALUE;\n    else if (wheel_value[id] < -LIMIT_X_MAX_VALUE) wheel_value[id] = -LIMIT_X_MAX_VALUE;\n  }\n\n  dxl_comm_result = motor_driver.controlMotor((int64_t)wheel_value[0], (int64_t)wheel_value[1]);\n  if (dxl_comm_result == false)\n    return;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_tank/turtlebot3_tank_motor_driver.cpp",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#include \"turtlebot3_tank_motor_driver.h\"\n\nTurtlebot3MotorDriver::Turtlebot3MotorDriver()\n: baudrate_(BAUDRATE),\n  protocol_version_(PROTOCOL_VERSION),\n  left_wheel_id_(DXL_LEFT_ID),\n  right_wheel_id_(DXL_RIGHT_ID)\n{\n}\n\nTurtlebot3MotorDriver::~Turtlebot3MotorDriver()\n{\n  closeDynamixel();\n}\n\nbool Turtlebot3MotorDriver::init(void)\n{\n  portHandler_   = dynamixel::PortHandler::getPortHandler(DEVICENAME);\n  packetHandler_ = dynamixel::PacketHandler::getPacketHandler(PROTOCOL_VERSION);\n\n  // Open port\n  if (portHandler_->openPort())\n  {\n    ERROR_PRINT(\"Port is opened\");\n  }\n  else\n  {\n    ERROR_PRINT(\"Port couldn't be opened\");\n\n    return false;\n  }\n\n  // Set port baudrate\n  if (portHandler_->setBaudRate(baudrate_))\n  {\n    ERROR_PRINT(\"Baudrate is set\");\n  }\n  else\n  {\n    ERROR_PRINT(\"Baudrate couldn't be set\");\n\n    return false;\n  }\n\n  // Enable Dynamixel Torque\n  setTorque(left_wheel_id_, true);\n  setTorque(right_wheel_id_, true);\n\n  groupSyncWriteVelocity_ = new dynamixel::GroupSyncWrite(portHandler_, packetHandler_, ADDR_X_GOAL_VELOCITY, LEN_X_GOAL_VELOCITY);\n\n  return true;\n}\n\nbool Turtlebot3MotorDriver::setTorque(uint8_t id, bool onoff)\n{\n  uint8_t dxl_error = 0;\n  int dxl_comm_result = COMM_TX_FAIL;\n\n  dxl_comm_result = packetHandler_->write1ByteTxRx(portHandler_, id, ADDR_X_TORQUE_ENABLE, onoff, &dxl_error);\n  if(dxl_comm_result != COMM_SUCCESS)\n  {\n    packetHandler_->getTxRxResult(dxl_comm_result);\n  }\n  else if(dxl_error != 0)\n  {\n    packetHandler_->getRxPacketError(dxl_error);\n  }\n}\n\nvoid Turtlebot3MotorDriver::closeDynamixel(void)\n{\n  // Disable Dynamixel Torque\n  setTorque(left_wheel_id_, false);\n  setTorque(right_wheel_id_, false);\n\n  // Close port\n  portHandler_->closePort();\n}\n\nbool Turtlebot3MotorDriver::controlMotor(int64_t left_wheel_value, int64_t right_wheel_value)\n{\n  bool dxl_addparam_result_;\n  int8_t dxl_comm_result_;\n\n  dxl_addparam_result_ = groupSyncWriteVelocity_->addParam(left_wheel_id_, (uint8_t*)&left_wheel_value);\n  if (dxl_addparam_result_ != true)\n    return false;\n\n  dxl_addparam_result_ = groupSyncWriteVelocity_->addParam(right_wheel_id_, (uint8_t*)&right_wheel_value);\n  if (dxl_addparam_result_ != true)\n    return false;\n\n  dxl_comm_result_ = groupSyncWriteVelocity_->txPacket();\n  if (dxl_comm_result_ != COMM_SUCCESS)\n  {\n    packetHandler_->getTxRxResult(dxl_comm_result_);\n    return false;\n  }\n\n  groupSyncWriteVelocity_->clearParam();\n  return true;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_friends/turtlebot3_tank/turtlebot3_tank_motor_driver.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#ifndef TURTLEBOT3_TANK_MOTOR_DRIVER_H_\n#define TURTLEBOT3_TANK_MOTOR_DRIVER_H_\n\n#include <DynamixelSDK.h>\n\n// Control table address (Dynamixel X-series)\n#define ADDR_X_TORQUE_ENABLE            64\n#define ADDR_X_GOAL_VELOCITY            104\n#define ADDR_X_PROFILE_ACCELERATION     108\n#define ADDR_X_PROFILE_VELOCITY         112\n#define ADDR_X_GOAL_POSITION            116\n#define ADDR_X_REALTIME_TICK            120\n#define ADDR_X_PRESENT_VELOCITY         128\n#define ADDR_X_PRESENT_POSITION         132\n\n// Limit values (XM430-W210-T)\n#define LIMIT_X_MAX_VELOCITY            240\n\n// Data Byte Length\n#define LEN_X_TORQUE_ENABLE             1\n#define LEN_X_GOAL_VELOCITY             4\n#define LEN_X_GOAL_POSITION             4\n#define LEN_X_REALTIME_TICK             2\n#define LEN_X_PRESENT_VELOCITY          4\n#define LEN_X_PRESENT_POSITION          4\n\n#define PROTOCOL_VERSION                2.0     // Dynamixel protocol version 2.0\n\n#define DXL_LEFT_ID                     1       // ID of left rear motor\n#define DXL_RIGHT_ID                    2       // ID of right rear motor\n#define BAUDRATE                        1000000 // baud rate of Dynamixel\n#define DEVICENAME                      \"\"      // no need setting on OpenCR\n\n#define TORQUE_ENABLE                   1       // Value for enabling the torque\n#define TORQUE_DISABLE                  0       // Value for disabling the torque\n\nclass Turtlebot3MotorDriver\n{\n public:\n  Turtlebot3MotorDriver();\n  ~Turtlebot3MotorDriver();\n  bool init(void);\n  void closeDynamixel(void);\n  bool setTorque(uint8_t id, bool onoff);\n  bool setProfileAcceleration(uint8_t id, uint32_t value);\n  bool setProfileVelocity(uint8_t id, uint32_t value);\n  bool controlMotor(int64_t left_wheel_value, int64_t right_wheel_value);\n\n private:\n  uint32_t baudrate_;\n  float  protocol_version_;\n  uint8_t left_wheel_id_, right_wheel_id_;\n\n  dynamixel::PortHandler *portHandler_;\n  dynamixel::PacketHandler *packetHandler_;\n\n  dynamixel::GroupSyncWrite *groupSyncWriteVelocity_;\n};\n\n#endif // TURTLEBOT3_TANK_MOTOR_DRIVER_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_setup/turtlebot3_setup_motor/turtlebot3_setup_motor.ino",
    "content": "/*******************************************************************************\n  Copyright 2016 ROBOTIS CO., LTD.\n\n  Licensed under the Apache License, Version 2.0 (the \"License\");\n  you may not use this file except in compliance with the License.\n  You may obtain a copy of the License at\n\n      http://www.apache.org/licenses/LICENSE-2.0\n\n  Unless required by applicable law or agreed to in writing, software\n  distributed under the License is distributed on an \"AS IS\" BASIS,\n  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n  See the License for the specific language governing permissions and\n  limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n#include <DynamixelSDK.h>\n#include <stdarg.h>\n\n// Protocol version\n#define PROTOCOL_VERSION1               1.0                 // See which protocol version is used in the Dynamixel\n#define PROTOCOL_VERSION2               2.0\n\n// Default setting\n#if defined(__OPENCR__) \n#define DEVICENAME                      \"/dev/OpenCR\"       // Device name not used on OpenCR\n#elif defined(__OPENCM904__)\n#define DEVICENAME                      \"3\"                 // Default to external (OpenCM485 expansion) on OpenCM9.04\n#endif\n\n// ex) Windows: \"COM1\"   Linux: \"/dev/ttyUSB0\"\n#define CMD_SERIAL                      Serial              // USB Serial\n\n\n\ntypedef union\n{\n  uint8_t  u8Data[4];\n  uint16_t u16Data[2];\n  uint32_t u32Data;\n\n  int8_t   s8Data[4];\n  int16_t  s16Data[2];\n  int32_t  s32Data;\n} dxl_ret_t;\n\nchar *dev_name = (char*)DEVICENAME;\n\n// Initialize Packethandler2 instance\ndynamixel::PacketHandler *packetHandler2;\ndynamixel::PortHandler   *portHandler;\n\n\nint tb3_id = -1;\nint tb3_baud = -1;\n\n\nbool requestConfirm(void);\nbool findMotor(int id);\nbool setupMotorLeft(void);\nbool setupMotorRight(void);\nvoid testMotor(uint8_t id);\n\n\nvoid      write(dynamixel::PortHandler *portHandler, dynamixel::PacketHandler *packetHandler, uint8_t id, uint16_t addr, uint16_t length, uint32_t value);\ndxl_ret_t read(dynamixel::PortHandler *portHandler, dynamixel::PacketHandler *packetHandler, uint8_t id, uint16_t addr, uint16_t length);\n\n\n\nvoid setup()\n{\n  CMD_SERIAL.begin(57600);\n  while (!CMD_SERIAL);\n\n\n  packetHandler2 = dynamixel::PacketHandler::getPacketHandler(PROTOCOL_VERSION2);\n  portHandler    = dynamixel::PortHandler::getPortHandler(dev_name);\n\n  // Open port\n  if (portHandler->openPort())\n  {\n    CMD_SERIAL.println(\"Succeeded to open the port!\");\n    CMD_SERIAL.printf(\" - Device Name : %s\\r\\n\", dev_name);\n    CMD_SERIAL.printf(\" - Baudrate    : %d\\r\\n\", portHandler->getBaudRate());\n    tb3_baud = portHandler->getBaudRate();\n  }\n  else\n  {\n    CMD_SERIAL.printf(\"Failed to open the port! [%s]\\n\", dev_name);\n    CMD_SERIAL.printf(\"Press any key to terminate...\\n\");\n    while (1);\n  }\n\n\n  CMD_SERIAL.println(\"\\r\\nStart turtlebot3 setup motor\");\n  drawTitle();\n}\n\nvoid loop()\n{\n  uint8_t ch;\n\n  if (CMD_SERIAL.available())\n  {\n    ch = CMD_SERIAL.read();\n\n    if (ch == '1')\n    {\n      flushCmd();\n      if (requestConfirm() == true)\n      {\n        CMD_SERIAL.println(\"setup.... left\");\n\n        if (findMotor(1) == true)\n        {\n          setupMotorLeft();\n        }\n      }\n    }\n    if (ch == '2')\n    {\n      flushCmd();\n      if (requestConfirm() == true)\n      {\n        CMD_SERIAL.println(\"setup.... right\");\n\n        if (findMotor(2) == true)\n        {\n          setupMotorRight();\n        }\n      }\n    }\n    if (ch == '3')\n    {\n      flushCmd();\n      CMD_SERIAL.println(\"test.... left\");\n      testMotor(1);\n    }\n    if (ch == '4')\n    {\n      flushCmd();\n      CMD_SERIAL.println(\"test.... right\");\n      testMotor(2);\n    }\n\n    drawTitle();\n    flushCmd();\n  }\n}\n\nvoid drawTitle(void)\n{\n  CMD_SERIAL.println(\" \");\n  CMD_SERIAL.println(\" \");\n  CMD_SERIAL.println(\"1. setup left  motor\");\n  CMD_SERIAL.println(\"2. setup right motor\");\n  CMD_SERIAL.println(\"3. test  left  motor\");\n  CMD_SERIAL.println(\"4. test  right motor\");\n  CMD_SERIAL.print(\">> \");\n}\n\nbool requestConfirm(void)\n{\n  uint8_t ch;\n\n\n  CMD_SERIAL.print(\"Do you really want to setup ? y/n : \");\n\n  while (1)\n  {\n    if (CMD_SERIAL.available())\n    {\n      ch = CMD_SERIAL.read();\n\n      if (ch == 'y' || ch == 'Y')\n      {\n        CMD_SERIAL.println(\"yes\");\n        flushCmd();\n        return true;\n      }\n\n      break;\n    }\n  }\n\n  CMD_SERIAL.println(\"no\");\n  return false;\n}\n\nvoid flushCmd(void)\n{\n  uint8_t ch;\n\n  while (CMD_SERIAL.available())\n  {\n    ch = CMD_SERIAL.read();\n  }\n}\n\n\nbool findMotor(int id)\n{\n  uint32_t baud_tbl[2] = { 57600, 1000000 };\n#define COUNT_BAUD (sizeof(baud_tbl)/sizeof(baud_tbl[0]))\n  uint32_t index;\n  uint32_t baud_pre;\n\n  std::vector<unsigned char> vec;\n\n\n  baud_pre = portHandler->getBaudRate();\n\n  tb3_id = -1;\n\n  CMD_SERIAL.println(\"Find Motor...\");\n\n  // First try to find the specific servo ID wanted\n  for (index = 0; index < COUNT_BAUD; index++)\n  {\n    portHandler->setBaudRate(baud_tbl[index]);\n    uint16_t model_number;\n    int dxl_comm_result = packetHandler2->ping(portHandler, id, &model_number);\n    if (dxl_comm_result == COMM_SUCCESS)\n    {\n      if (tb3_id == -1)\n      {\n        tb3_id = id;\n        tb3_baud =  baud_tbl[index];\n      }\n      else\n      {\n        CMD_SERIAL.printf(\"Warning Servo %d found at two baud rates %d and %d using %d\\n\",\n                          id, tb3_baud, baud_tbl[index], baud_tbl[index]);\n        tb3_baud =  baud_tbl[index];\n      }\n    }\n  }\n\n  if (tb3_id != -1)\n  {\n    CMD_SERIAL.println(\"    ... SUCCESS\");\n    CMD_SERIAL.printf(\"    [ID: %d found at baud: %d]\\n\", id, tb3_baud );\n    portHandler->setBaudRate(tb3_baud);\n    return true;\n  }\n\n  // Did not find the actual ID we were looking for so see if we find any servos?\n  for (index = 0; index < COUNT_BAUD; index++)\n  {\n    CMD_SERIAL.printf(\"    setbaud : %d\\r\\n\", baud_tbl[index]);\n\n    portHandler->setBaudRate(baud_tbl[index]);\n    tb3_baud =  baud_tbl[index];\n\n    // Lets see if we find the actual one we want to update?\n    int dxl_comm_result = packetHandler2->broadcastPing(portHandler, vec);\n    if (dxl_comm_result != COMM_SUCCESS)\n    {\n      CMD_SERIAL.println(packetHandler2->getTxRxResult(dxl_comm_result));\n      continue;\n    }\n\n    for (unsigned int i = 0; i < vec.size(); i++)\n    {\n      CMD_SERIAL.println(\"    ... SUCCESS\");\n      CMD_SERIAL.println(\"    [ID:\" + String(vec.at(i)) + \"]\");\n      tb3_id = vec.at(i);\n    }\n\n    if (vec.size() > 0)\n    {\n      CMD_SERIAL.println(\"    found motor\");\n      if (vec.size() > 1)\n      {\n        CMD_SERIAL.printf(\"    WARNING: multiple servos found, using id: %d\\n\", tb3_id);\n        if (!requestConfirm())\n        {\n          tb3_id = -1;  // setup to abort...\n        }\n      }\n\n      break;\n    }\n    else\n    {\n      CMD_SERIAL.println(\"    not found\");\n    }\n  }\n\n  if (tb3_id < 0)\n  {\n    portHandler->setBaudRate(baud_pre);\n    return false;\n  }\n  else\n  {\n    return true;\n  }\n}\n\nbool setupMotorLeft(void)\n{\n  CMD_SERIAL.println(\"Setup Motor Left...\");\n\n\n  if (tb3_id < 0)\n  {\n    CMD_SERIAL.println(\"    no dxl motors\");\n  }\n  else\n  {\n    write(portHandler, packetHandler2, tb3_id, 64, 1, 0);\n    write(portHandler, packetHandler2, tb3_id, 7, 1, 1);\n    tb3_id = 1;\n    write(portHandler, packetHandler2, tb3_id, 8, 1, 3);\n    portHandler->setBaudRate(1000000);\n    write(portHandler, packetHandler2, tb3_id, 10, 1, 0);\n    write(portHandler, packetHandler2, tb3_id, 11, 1, 1);\n    CMD_SERIAL.println(\"    ok\");\n  }\n}\n\nbool setupMotorRight(void)\n{\n  CMD_SERIAL.println(\"Setup Motor Right...\");\n\n\n  if (tb3_id < 0)\n  {\n    CMD_SERIAL.println(\"    no dxl motors\");\n  }\n  else\n  {\n    write(portHandler, packetHandler2, tb3_id, 64, 1, 0);\n    write(portHandler, packetHandler2, tb3_id, 7, 1, 2);\n    tb3_id = 2;\n    write(portHandler, packetHandler2, tb3_id, 8, 1, 3);\n    portHandler->setBaudRate(1000000);\n    write(portHandler, packetHandler2, tb3_id, 10, 1, 1);\n    write(portHandler, packetHandler2, tb3_id, 11, 1, 1);\n    CMD_SERIAL.println(\"    ok\");\n  }\n}\n\nvoid testMotor(uint8_t id)\n{\n  uint32_t pre_time;\n  uint8_t  toggle = 0;\n\n  if (id == 1)\n  {\n    CMD_SERIAL.printf(\"Test Motor Left...\");\n  }\n  else\n  {\n    CMD_SERIAL.printf(\"Test Motor Right...\");\n  }\n  // We run at 1000000\n  portHandler->setBaudRate(1000000);\n\n  uint16_t model_number;\n  int dxl_comm_result = packetHandler2->ping(portHandler, id, &model_number);\n  if (dxl_comm_result == COMM_SUCCESS)\n  {\n    CMD_SERIAL.printf(\" found type: %d\\n\", model_number);\n    write(portHandler, packetHandler2, id, 64, 1, 1);\n\n    toggle = 0;\n    pre_time = millis();\n    write(portHandler, packetHandler2, id, 104, 4, 100);\n    while (1)\n    {\n      if (CMD_SERIAL.available())\n      {\n        flushCmd();\n        break;\n      }\n\n      if (millis() - pre_time > 1000)\n      {\n        pre_time = millis();\n\n        toggle ^= 1;\n\n        if (toggle)\n        {\n          write(portHandler, packetHandler2, id, 104, 4, 0);\n        }\n        else\n        {\n          write(portHandler, packetHandler2, id, 104, 4, 100);\n        }\n      }\n    }\n    write(portHandler, packetHandler2, id, 104, 4, 0);\n  }\n  else\n  {\n    CMD_SERIAL.printf(\"    dxl motor ID:%d not found\\n\", id);\n  }\n}\n\nvoid write(dynamixel::PortHandler *portHandler, dynamixel::PacketHandler *packetHandler, uint8_t id, uint16_t addr, uint16_t length, uint32_t value)\n{\n  uint8_t dxl_error = 0;\n  int dxl_comm_result = COMM_TX_FAIL;\n\n  if (length == 1)\n  {\n    dxl_comm_result = packetHandler->write1ByteTxRx(portHandler, id, addr, (uint8_t)value, &dxl_error);\n  }\n  else if (length == 2)\n  {\n    dxl_comm_result = packetHandler->write2ByteTxRx(portHandler, id, addr, (uint16_t)value, &dxl_error);\n  }\n  else if (length == 4)\n  {\n    dxl_comm_result = packetHandler->write4ByteTxRx(portHandler, id, addr, (uint32_t)value, &dxl_error);\n  }\n\n  if (dxl_comm_result == COMM_SUCCESS)\n  {\n    if (dxl_error != 0) CMD_SERIAL.println(packetHandler->getRxPacketError(dxl_error));\n  }\n  else\n  {\n    CMD_SERIAL.println(packetHandler->getTxRxResult(dxl_error));\n    CMD_SERIAL.println(\"Fail to write!\");\n  }\n}\n\ndxl_ret_t read(dynamixel::PortHandler *portHandler, dynamixel::PacketHandler *packetHandler, uint8_t id, uint16_t addr, uint16_t length)\n{\n  uint8_t dxl_error = 0;\n  int     dxl_comm_result = COMM_TX_FAIL;\n  dxl_ret_t ret;\n\n  int8_t  value8    = 0;\n  int16_t value16   = 0;\n  int32_t value32   = 0;\n\n\n  if (length == 1)\n  {\n    dxl_comm_result = packetHandler->read1ByteTxRx(portHandler, id, addr, (uint8_t*)&value8, &dxl_error);\n  }\n  else if (length == 2)\n  {\n    dxl_comm_result = packetHandler->read2ByteTxRx(portHandler, id, addr, (uint16_t*)&value16, &dxl_error);\n  }\n  else if (length == 4)\n  {\n    dxl_comm_result = packetHandler->read4ByteTxRx(portHandler, id, addr, (uint32_t*)&value32, &dxl_error);\n  }\n\n  if (dxl_comm_result == COMM_SUCCESS)\n  {\n    if (dxl_error != 0) CMD_SERIAL.println(packetHandler->getRxPacketError(dxl_error));\n\n    if (length == 1)\n    {\n      ret.u32Data = value8;\n    }\n    else if (length == 2)\n    {\n      ret.u32Data = value16;\n    }\n    else if (length == 4)\n    {\n      ret.u32Data = value32;\n    }\n  }\n  else\n  {\n    CMD_SERIAL.println(packetHandler->getTxRxResult(dxl_error));\n    CMD_SERIAL.println(\"Fail to read! \");\n  }\n\n  return ret;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_waffle/turtlebot3_core/turtlebot3_core.ino",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho, Gilbert */\n\n#include \"turtlebot3_core_config.h\"\n\n/*******************************************************************************\n* Setup function\n*******************************************************************************/\nvoid setup()\n{\n  DEBUG_SERIAL.begin(57600);\n\n  // Initialize ROS node handle, advertise and subscribe the topics\n  nh.initNode();\n  nh.getHardware()->setBaud(115200);\n\n  nh.subscribe(cmd_vel_sub);\n  nh.subscribe(sound_sub);\n  nh.subscribe(motor_power_sub);\n  nh.subscribe(reset_sub);\n\n  nh.advertise(sensor_state_pub);  \n  nh.advertise(version_info_pub);\n  nh.advertise(imu_pub);\n  nh.advertise(cmd_vel_rc100_pub);\n  nh.advertise(odom_pub);\n  nh.advertise(joint_states_pub);\n  nh.advertise(battery_state_pub);\n  nh.advertise(mag_pub);\n\n  tf_broadcaster.init(nh);\n\n  // Setting for Dynamixel motors\n  motor_driver.init(NAME);\n\n  // Setting for IMU\n  sensors.init();\n\n  // Init diagnosis\n  diagnosis.init();\n\n  // Setting for ROBOTIS RC100 remote controller and cmd_vel\n  controllers.init(MAX_LINEAR_VELOCITY, MAX_ANGULAR_VELOCITY);\n\n  // Setting for SLAM and navigation (odometry, joint states, TF)\n  initOdom();\n\n  initJointStates();\n\n  prev_update_time = millis();\n\n  pinMode(LED_WORKING_CHECK, OUTPUT);\n\n  setup_end = true;\n}\n\n/*******************************************************************************\n* Loop function\n*******************************************************************************/\nvoid loop()\n{\n  uint32_t t = millis();\n  updateTime();\n  updateVariable(nh.connected());\n  updateTFPrefix(nh.connected());\n\n  if ((t-tTime[0]) >= (1000 / CONTROL_MOTOR_SPEED_FREQUENCY))\n  {\n    updateGoalVelocity();\n    if ((t-tTime[6]) > CONTROL_MOTOR_TIMEOUT) \n    {\n      motor_driver.controlMotor(WHEEL_RADIUS, WHEEL_SEPARATION, zero_velocity);\n    } \n    else {\n      motor_driver.controlMotor(WHEEL_RADIUS, WHEEL_SEPARATION, goal_velocity);\n    }\n    tTime[0] = t;\n  }\n\n  if ((t-tTime[1]) >= (1000 / CMD_VEL_PUBLISH_FREQUENCY))\n  {\n    publishCmdVelFromRC100Msg();\n    tTime[1] = t;\n  }\n\n  if ((t-tTime[2]) >= (1000 / DRIVE_INFORMATION_PUBLISH_FREQUENCY))\n  {\n    publishSensorStateMsg();\n    publishBatteryStateMsg();\n    publishDriveInformation();\n    tTime[2] = t;\n  }\n\n  if ((t-tTime[3]) >= (1000 / IMU_PUBLISH_FREQUENCY))\n  {\n    publishImuMsg();\n    publishMagMsg();\n    tTime[3] = t;\n  }\n\n  if ((t-tTime[4]) >= (1000 / VERSION_INFORMATION_PUBLISH_FREQUENCY))\n  {\n    publishVersionInfoMsg();\n    tTime[4] = t;\n  }\n\n#ifdef DEBUG\n  if ((t-tTime[5]) >= (1000 / DEBUG_LOG_FREQUENCY))\n  {\n    sendDebuglog();\n    tTime[5] = t;\n  }\n#endif\n\n  // Send log message after ROS connection\n  sendLogMsg();\n\n  // Receive data from RC100 \n  bool clicked_state = controllers.getRCdata(goal_velocity_from_rc100);\n  if (clicked_state == true)  \n    tTime[6] = millis();\n\n  // Check push button pressed for simple test drive\n  driveTest(diagnosis.getButtonPress(3000));\n\n  // Update the IMU unit\n  sensors.updateIMU();\n\n  // TODO\n  // Update sonar data\n  // sensors.updateSonar(t);\n\n  // Start Gyro Calibration after ROS connection\n  updateGyroCali(nh.connected());\n\n  // Show LED status\n  diagnosis.showLedStatus(nh.connected());\n\n  // Update Voltage\n  battery_state = diagnosis.updateVoltageCheck(setup_end);\n\n  // Call all the callbacks waiting to be called at that point in time\n  nh.spinOnce();\n\n  // Wait the serial link time to process\n  waitForSerialLink(nh.connected());\n}\n\n/*******************************************************************************\n* Callback function for cmd_vel msg\n*******************************************************************************/\nvoid commandVelocityCallback(const geometry_msgs::Twist& cmd_vel_msg)\n{\n  goal_velocity_from_cmd[LINEAR]  = cmd_vel_msg.linear.x;\n  goal_velocity_from_cmd[ANGULAR] = cmd_vel_msg.angular.z;\n\n  goal_velocity_from_cmd[LINEAR]  = constrain(goal_velocity_from_cmd[LINEAR],  MIN_LINEAR_VELOCITY, MAX_LINEAR_VELOCITY);\n  goal_velocity_from_cmd[ANGULAR] = constrain(goal_velocity_from_cmd[ANGULAR], MIN_ANGULAR_VELOCITY, MAX_ANGULAR_VELOCITY);\n  tTime[6] = millis();\n}\n\n/*******************************************************************************\n* Callback function for sound msg\n*******************************************************************************/\nvoid soundCallback(const turtlebot3_msgs::Sound& sound_msg)\n{\n  sensors.makeSound(sound_msg.value);\n}\n\n/*******************************************************************************\n* Callback function for motor_power msg\n*******************************************************************************/\nvoid motorPowerCallback(const std_msgs::Bool& power_msg)\n{\n  bool dxl_power = power_msg.data;\n\n  motor_driver.setTorque(dxl_power);\n}\n\n/*******************************************************************************\n* Callback function for reset msg\n*******************************************************************************/\nvoid resetCallback(const std_msgs::Empty& reset_msg)\n{\n  char log_msg[50];\n\n  (void)(reset_msg);\n\n  sprintf(log_msg, \"Start Calibration of Gyro\");\n  nh.loginfo(log_msg);\n\n  sensors.calibrationGyro();\n\n  sprintf(log_msg, \"Calibration End\");\n  nh.loginfo(log_msg);\n\n  initOdom();\n\n  sprintf(log_msg, \"Reset Odometry\");\n  nh.loginfo(log_msg);  \n}\n\n/*******************************************************************************\n* Publish msgs (CMD Velocity data from RC100 : angular velocity, linear velocity)\n*******************************************************************************/\nvoid publishCmdVelFromRC100Msg(void)\n{\n  cmd_vel_rc100_msg.linear.x  = goal_velocity_from_rc100[LINEAR];\n  cmd_vel_rc100_msg.angular.z = goal_velocity_from_rc100[ANGULAR];\n\n  cmd_vel_rc100_pub.publish(&cmd_vel_rc100_msg);\n}\n\n/*******************************************************************************\n* Publish msgs (IMU data: angular velocity, linear acceleration, orientation)\n*******************************************************************************/\nvoid publishImuMsg(void)\n{\n  imu_msg = sensors.getIMU();\n\n  imu_msg.header.stamp    = rosNow();\n  imu_msg.header.frame_id = imu_frame_id;\n\n  imu_pub.publish(&imu_msg);\n}\n\n/*******************************************************************************\n* Publish msgs (Magnetic data)\n*******************************************************************************/\nvoid publishMagMsg(void)\n{\n  mag_msg = sensors.getMag();\n\n  mag_msg.header.stamp    = rosNow();\n  mag_msg.header.frame_id = mag_frame_id;\n\n  mag_pub.publish(&mag_msg);\n}\n\n/*******************************************************************************\n* Publish msgs (sensor_state: bumpers, cliffs, buttons, encoders, battery)\n*******************************************************************************/\nvoid publishSensorStateMsg(void)\n{\n  bool dxl_comm_result = false;\n\n  sensor_state_msg.header.stamp = rosNow();\n  sensor_state_msg.battery = sensors.checkVoltage();\n\n  dxl_comm_result = motor_driver.readEncoder(sensor_state_msg.left_encoder, sensor_state_msg.right_encoder);\n\n  if (dxl_comm_result == true)\n    updateMotorInfo(sensor_state_msg.left_encoder, sensor_state_msg.right_encoder);\n  else\n    return;\n\n  sensor_state_msg.bumper = sensors.checkPushBumper();\n\n  sensor_state_msg.cliff = sensors.getIRsensorData();\n\n  // TODO\n  // sensor_state_msg.sonar = sensors.getSonarData();\n\n  sensor_state_msg.illumination = sensors.getIlluminationData();\n  \n  sensor_state_msg.button = sensors.checkPushButton();\n\n  sensor_state_msg.torque = motor_driver.getTorque();\n\n  sensor_state_pub.publish(&sensor_state_msg);\n}\n\n/*******************************************************************************\n* Publish msgs (version info)\n*******************************************************************************/\nvoid publishVersionInfoMsg(void)\n{\n  version_info_msg.hardware = \"0.0.0\";\n  version_info_msg.software = \"0.0.0\";\n  version_info_msg.firmware = FIRMWARE_VER;\n\n  version_info_pub.publish(&version_info_msg);\n}\n\n/*******************************************************************************\n* Publish msgs (battery_state)\n*******************************************************************************/\nvoid publishBatteryStateMsg(void)\n{\n  battery_state_msg.header.stamp = rosNow();\n  battery_state_msg.design_capacity = 1.8f; //Ah\n  battery_state_msg.voltage = sensors.checkVoltage();\n  battery_state_msg.percentage = (float)(battery_state_msg.voltage / 11.1f);\n\n  if (battery_state == 0)\n    battery_state_msg.present = false;\n  else\n    battery_state_msg.present = true;  \n\n  battery_state_pub.publish(&battery_state_msg);\n}\n\n/*******************************************************************************\n* Publish msgs (odometry, joint states, tf)\n*******************************************************************************/\nvoid publishDriveInformation(void)\n{\n  unsigned long time_now = millis();\n  unsigned long step_time = time_now - prev_update_time;\n\n  prev_update_time = time_now;\n  ros::Time stamp_now = rosNow();\n\n  // calculate odometry\n  calcOdometry((double)(step_time * 0.001));\n\n  // odometry\n  updateOdometry();\n  odom.header.stamp = stamp_now;\n  odom_pub.publish(&odom);\n\n  // odometry tf\n  updateTF(odom_tf);\n  odom_tf.header.stamp = stamp_now;\n  tf_broadcaster.sendTransform(odom_tf);\n\n  // joint states\n  updateJointStates();\n  joint_states.header.stamp = stamp_now;\n  joint_states_pub.publish(&joint_states);\n}\n\n/*******************************************************************************\n* Update TF Prefix\n*******************************************************************************/\nvoid updateTFPrefix(bool isConnected)\n{\n  static bool isChecked = false;\n  char log_msg[50];\n\n  if (isConnected)\n  {\n    if (isChecked == false)\n    {\n      nh.getParam(\"~tf_prefix\", &get_tf_prefix);\n\n      if (!strcmp(get_tf_prefix, \"\"))\n      {\n        sprintf(odom_header_frame_id, \"odom\");\n        sprintf(odom_child_frame_id, \"base_footprint\");  \n\n        sprintf(imu_frame_id, \"imu_link\");\n        sprintf(mag_frame_id, \"mag_link\");\n        sprintf(joint_state_header_frame_id, \"base_link\");\n      }\n      else\n      {\n        strcpy(odom_header_frame_id, get_tf_prefix);\n        strcpy(odom_child_frame_id, get_tf_prefix);\n\n        strcpy(imu_frame_id, get_tf_prefix);\n        strcpy(mag_frame_id, get_tf_prefix);\n        strcpy(joint_state_header_frame_id, get_tf_prefix);\n\n        strcat(odom_header_frame_id, \"/odom\");\n        strcat(odom_child_frame_id, \"/base_footprint\");\n\n        strcat(imu_frame_id, \"/imu_link\");\n        strcat(mag_frame_id, \"/mag_link\");\n        strcat(joint_state_header_frame_id, \"/base_link\");\n      }\n\n      sprintf(log_msg, \"Setup TF on Odometry [%s]\", odom_header_frame_id);\n      nh.loginfo(log_msg); \n\n      sprintf(log_msg, \"Setup TF on IMU [%s]\", imu_frame_id);\n      nh.loginfo(log_msg); \n\n      sprintf(log_msg, \"Setup TF on MagneticField [%s]\", mag_frame_id);\n      nh.loginfo(log_msg); \n\n      sprintf(log_msg, \"Setup TF on JointState [%s]\", joint_state_header_frame_id);\n      nh.loginfo(log_msg); \n\n      isChecked = true;\n    }\n  }\n  else\n  {\n    isChecked = false;\n  }\n}\n\n/*******************************************************************************\n* Update the odometry\n*******************************************************************************/\nvoid updateOdometry(void)\n{\n  odom.header.frame_id = odom_header_frame_id;\n  odom.child_frame_id  = odom_child_frame_id;\n\n  odom.pose.pose.position.x = odom_pose[0];\n  odom.pose.pose.position.y = odom_pose[1];\n  odom.pose.pose.position.z = 0;\n  odom.pose.pose.orientation = tf::createQuaternionFromYaw(odom_pose[2]);\n\n  odom.twist.twist.linear.x  = odom_vel[0];\n  odom.twist.twist.angular.z = odom_vel[2];\n}\n\n/*******************************************************************************\n* Update the joint states \n*******************************************************************************/\nvoid updateJointStates(void)\n{\n  static float joint_states_pos[WHEEL_NUM] = {0.0, 0.0};\n  static float joint_states_vel[WHEEL_NUM] = {0.0, 0.0};\n  //static float joint_states_eff[WHEEL_NUM] = {0.0, 0.0};\n\n  joint_states_pos[LEFT]  = last_rad[LEFT];\n  joint_states_pos[RIGHT] = last_rad[RIGHT];\n\n  joint_states_vel[LEFT]  = last_velocity[LEFT];\n  joint_states_vel[RIGHT] = last_velocity[RIGHT];\n\n  joint_states.position = joint_states_pos;\n  joint_states.velocity = joint_states_vel;\n}\n\n/*******************************************************************************\n* CalcUpdateulate the TF\n*******************************************************************************/\nvoid updateTF(geometry_msgs::TransformStamped& odom_tf)\n{\n  odom_tf.header = odom.header;\n  odom_tf.child_frame_id = odom.child_frame_id;\n  odom_tf.transform.translation.x = odom.pose.pose.position.x;\n  odom_tf.transform.translation.y = odom.pose.pose.position.y;\n  odom_tf.transform.translation.z = odom.pose.pose.position.z;\n  odom_tf.transform.rotation      = odom.pose.pose.orientation;\n}\n\n/*******************************************************************************\n* Update motor information\n*******************************************************************************/\nvoid updateMotorInfo(int32_t left_tick, int32_t right_tick)\n{\n  int32_t current_tick = 0;\n  static int32_t last_tick[WHEEL_NUM] = {0, 0};\n  \n  if (init_encoder)\n  {\n    for (int index = 0; index < WHEEL_NUM; index++)\n    {\n      last_diff_tick[index] = 0;\n      last_tick[index]      = 0;\n      last_rad[index]       = 0.0;\n\n      last_velocity[index]  = 0.0;\n    }  \n\n    last_tick[LEFT] = left_tick;\n    last_tick[RIGHT] = right_tick;\n\n    init_encoder = false;\n    return;\n  }\n\n  current_tick = left_tick;\n\n  last_diff_tick[LEFT] = current_tick - last_tick[LEFT];\n  last_tick[LEFT]      = current_tick;\n  last_rad[LEFT]       += TICK2RAD * (double)last_diff_tick[LEFT];\n\n  current_tick = right_tick;\n\n  last_diff_tick[RIGHT] = current_tick - last_tick[RIGHT];\n  last_tick[RIGHT]      = current_tick;\n  last_rad[RIGHT]       += TICK2RAD * (double)last_diff_tick[RIGHT];\n}\n\n/*******************************************************************************\n* Calculate the odometry\n*******************************************************************************/\nbool calcOdometry(double diff_time)\n{\n  float* orientation;\n  double wheel_l, wheel_r;      // rotation value of wheel [rad]\n  double delta_s, theta, delta_theta;\n  static double last_theta = 0.0;\n  double v, w;                  // v = translational velocity [m/s], w = rotational velocity [rad/s]\n  double step_time;\n\n  wheel_l = wheel_r = 0.0;\n  delta_s = delta_theta = theta = 0.0;\n  v = w = 0.0;\n  step_time = 0.0;\n\n  step_time = diff_time;\n\n  if (step_time == 0)\n    return false;\n\n  wheel_l = TICK2RAD * (double)last_diff_tick[LEFT];\n  wheel_r = TICK2RAD * (double)last_diff_tick[RIGHT];\n\n  if (isnan(wheel_l))\n    wheel_l = 0.0;\n\n  if (isnan(wheel_r))\n    wheel_r = 0.0;\n\n  delta_s     = WHEEL_RADIUS * (wheel_r + wheel_l) / 2.0;\n  // theta = WHEEL_RADIUS * (wheel_r - wheel_l) / WHEEL_SEPARATION;  \n  orientation = sensors.getOrientation();\n  theta       = atan2f(orientation[1]*orientation[2] + orientation[0]*orientation[3], \n                0.5f - orientation[2]*orientation[2] - orientation[3]*orientation[3]);\n\n  delta_theta = theta - last_theta;\n\n  // compute odometric pose\n  odom_pose[0] += delta_s * cos(odom_pose[2] + (delta_theta / 2.0));\n  odom_pose[1] += delta_s * sin(odom_pose[2] + (delta_theta / 2.0));\n  odom_pose[2] += delta_theta;\n\n  // compute odometric instantaneouse velocity\n\n  v = delta_s / step_time;\n  w = delta_theta / step_time;\n\n  odom_vel[0] = v;\n  odom_vel[1] = 0.0;\n  odom_vel[2] = w;\n\n  last_velocity[LEFT]  = wheel_l / step_time;\n  last_velocity[RIGHT] = wheel_r / step_time;\n  last_theta = theta;\n\n  return true;\n}\n\n/*******************************************************************************\n* Turtlebot3 test drive using push buttons\n*******************************************************************************/\nvoid driveTest(uint8_t buttons)\n{\n  static bool move[2] = {false, false};\n  static int32_t saved_tick[2] = {0, 0};\n  static double diff_encoder = 0.0;\n\n  int32_t current_tick[2] = {0, 0};\n\n  motor_driver.readEncoder(current_tick[LEFT], current_tick[RIGHT]);\n\n  if (buttons & (1<<0))  \n  {\n    move[LINEAR] = true;\n    saved_tick[RIGHT] = current_tick[RIGHT];\n\n    diff_encoder = TEST_DISTANCE / (0.207 / 4096); // (Circumference of Wheel) / (The number of tick per revolution)\n    tTime[6] = millis();\n  }\n  else if (buttons & (1<<1))\n  {\n    move[ANGULAR] = true;\n    saved_tick[RIGHT] = current_tick[RIGHT];\n\n    diff_encoder = (TEST_RADIAN * TURNING_RADIUS) / (0.207 / 4096);\n    tTime[6] = millis();\n  }\n\n  if (move[LINEAR])\n  {    \n    if (abs(saved_tick[RIGHT] - current_tick[RIGHT]) <= diff_encoder)\n    {\n      goal_velocity_from_button[LINEAR]  = 0.05;\n      tTime[6] = millis();\n    }\n    else\n    {\n      goal_velocity_from_button[LINEAR]  = 0.0;\n      move[LINEAR] = false;\n    }\n  }\n  else if (move[ANGULAR])\n  {   \n    if (abs(saved_tick[RIGHT] - current_tick[RIGHT]) <= diff_encoder)\n    {\n      goal_velocity_from_button[ANGULAR]= -0.7;\n      tTime[6] = millis();\n    }\n    else\n    {\n      goal_velocity_from_button[ANGULAR]  = 0.0;\n      move[ANGULAR] = false;\n    }\n  }\n}\n\n/*******************************************************************************\n* Update variable (initialization)\n*******************************************************************************/\nvoid updateVariable(bool isConnected)\n{\n  static bool variable_flag = false;\n  \n  if (isConnected)\n  {\n    if (variable_flag == false)\n    {      \n      sensors.initIMU();\n      initOdom();\n\n      variable_flag = true;\n    }\n  }\n  else\n  {\n    variable_flag = false;\n  }\n}\n\n/*******************************************************************************\n* Wait for Serial Link\n*******************************************************************************/\nvoid waitForSerialLink(bool isConnected)\n{\n  static bool wait_flag = false;\n  \n  if (isConnected)\n  {\n    if (wait_flag == false)\n    {      \n      delay(10);\n\n      wait_flag = true;\n    }\n  }\n  else\n  {\n    wait_flag = false;\n  }\n}\n\n/*******************************************************************************\n* Update the base time for interpolation\n*******************************************************************************/\nvoid updateTime()\n{\n  current_offset = millis();\n  current_time = nh.now();\n}\n\n/*******************************************************************************\n* ros::Time::now() implementation\n*******************************************************************************/\nros::Time rosNow()\n{\n  return nh.now();\n}\n\n/*******************************************************************************\n* Time Interpolation function (deprecated)\n*******************************************************************************/\nros::Time addMicros(ros::Time & t, uint32_t _micros)\n{\n  uint32_t sec, nsec;\n\n  sec  = _micros / 1000 + t.sec;\n  nsec = _micros % 1000000000 + t.nsec;\n\n  return ros::Time(sec, nsec);\n}\n\n/*******************************************************************************\n* Start Gyro Calibration\n*******************************************************************************/\nvoid updateGyroCali(bool isConnected)\n{\n  static bool isEnded = false;\n  char log_msg[50];\n\n  (void)(isConnected);\n\n  if (nh.connected())\n  {\n    if (isEnded == false)\n    {\n      sprintf(log_msg, \"Start Calibration of Gyro\");\n      nh.loginfo(log_msg);\n\n      sensors.calibrationGyro();\n\n      sprintf(log_msg, \"Calibration End\");\n      nh.loginfo(log_msg);\n\n      isEnded = true;\n    }\n  }\n  else\n  {\n    isEnded = false;\n  }\n}\n\n/*******************************************************************************\n* Send log message\n*******************************************************************************/\nvoid sendLogMsg(void)\n{\n  static bool log_flag = false;\n  char log_msg[100];  \n\n  String name             = NAME;\n  String firmware_version = FIRMWARE_VER;\n  String bringup_log      = \"This core(v\" + firmware_version + \") is compatible with TB3 \" + name;\n   \n  const char* init_log_data = bringup_log.c_str();\n\n  if (nh.connected())\n  {\n    if (log_flag == false)\n    {      \n      sprintf(log_msg, \"--------------------------\");\n      nh.loginfo(log_msg);\n\n      sprintf(log_msg, \"Connected to OpenCR board!\");\n      nh.loginfo(log_msg);\n\n      sprintf(log_msg, init_log_data);\n      nh.loginfo(log_msg);\n\n      sprintf(log_msg, \"--------------------------\");\n      nh.loginfo(log_msg);\n\n      log_flag = true;\n    }\n  }\n  else\n  {\n    log_flag = false;\n  }\n}\n\n/*******************************************************************************\n* Initialization odometry data\n*******************************************************************************/\nvoid initOdom(void)\n{\n  init_encoder = true;\n\n  for (int index = 0; index < 3; index++)\n  {\n    odom_pose[index] = 0.0;\n    odom_vel[index]  = 0.0;\n  }\n\n  odom.pose.pose.position.x = 0.0;\n  odom.pose.pose.position.y = 0.0;\n  odom.pose.pose.position.z = 0.0;\n\n  odom.pose.pose.orientation.x = 0.0;\n  odom.pose.pose.orientation.y = 0.0;\n  odom.pose.pose.orientation.z = 0.0;\n  odom.pose.pose.orientation.w = 0.0;\n\n  odom.twist.twist.linear.x  = 0.0;\n  odom.twist.twist.angular.z = 0.0;\n}\n\n/*******************************************************************************\n* Initialization joint states data\n*******************************************************************************/\nvoid initJointStates(void)\n{\n  static char *joint_states_name[] = {(char*)\"wheel_left_joint\", (char*)\"wheel_right_joint\"};\n\n  joint_states.header.frame_id = joint_state_header_frame_id;\n  joint_states.name            = joint_states_name;\n\n  joint_states.name_length     = WHEEL_NUM;\n  joint_states.position_length = WHEEL_NUM;\n  joint_states.velocity_length = WHEEL_NUM;\n  joint_states.effort_length   = WHEEL_NUM;\n}\n\n/*******************************************************************************\n* Update Goal Velocity\n*******************************************************************************/\nvoid updateGoalVelocity(void)\n{\n  goal_velocity[LINEAR]  = goal_velocity_from_button[LINEAR]  + goal_velocity_from_cmd[LINEAR]  + goal_velocity_from_rc100[LINEAR];\n  goal_velocity[ANGULAR] = goal_velocity_from_button[ANGULAR] + goal_velocity_from_cmd[ANGULAR] + goal_velocity_from_rc100[ANGULAR];\n\n  sensors.setLedPattern(goal_velocity[LINEAR], goal_velocity[ANGULAR]);\n}\n\n/*******************************************************************************\n* Send Debug data\n*******************************************************************************/\nvoid sendDebuglog(void)\n{\n  DEBUG_SERIAL.println(\"---------------------------------------\");\n  DEBUG_SERIAL.println(\"EXTERNAL SENSORS\");\n  DEBUG_SERIAL.println(\"---------------------------------------\");\n  DEBUG_SERIAL.print(\"Bumper : \"); DEBUG_SERIAL.println(sensors.checkPushBumper());\n  DEBUG_SERIAL.print(\"Cliff : \"); DEBUG_SERIAL.println(sensors.getIRsensorData());\n  DEBUG_SERIAL.print(\"Sonar : \"); DEBUG_SERIAL.println(sensors.getSonarData());\n  DEBUG_SERIAL.print(\"Illumination : \"); DEBUG_SERIAL.println(sensors.getIlluminationData());\n\n  DEBUG_SERIAL.println(\"---------------------------------------\");\n  DEBUG_SERIAL.println(\"OpenCR SENSORS\");\n  DEBUG_SERIAL.println(\"---------------------------------------\");\n  DEBUG_SERIAL.print(\"Battery : \"); DEBUG_SERIAL.println(sensors.checkVoltage());\n  DEBUG_SERIAL.println(\"Button : \" + String(sensors.checkPushButton()));\n\n  float* quat = sensors.getOrientation();\n\n  DEBUG_SERIAL.println(\"IMU : \");\n  DEBUG_SERIAL.print(\"    w : \"); DEBUG_SERIAL.println(quat[0]);\n  DEBUG_SERIAL.print(\"    x : \"); DEBUG_SERIAL.println(quat[1]);\n  DEBUG_SERIAL.print(\"    y : \"); DEBUG_SERIAL.println(quat[2]);\n  DEBUG_SERIAL.print(\"    z : \"); DEBUG_SERIAL.println(quat[3]);\n  \n  DEBUG_SERIAL.println(\"---------------------------------------\");\n  DEBUG_SERIAL.println(\"DYNAMIXELS\");\n  DEBUG_SERIAL.println(\"---------------------------------------\");\n  DEBUG_SERIAL.println(\"Torque : \" + String(motor_driver.getTorque()));\n\n  int32_t encoder[WHEEL_NUM] = {0, 0};\n  motor_driver.readEncoder(encoder[LEFT], encoder[RIGHT]);\n  \n  DEBUG_SERIAL.println(\"Encoder(left) : \" + String(encoder[LEFT]));\n  DEBUG_SERIAL.println(\"Encoder(right) : \" + String(encoder[RIGHT]));\n\n  DEBUG_SERIAL.println(\"---------------------------------------\");\n  DEBUG_SERIAL.println(\"TurtleBot3\");\n  DEBUG_SERIAL.println(\"---------------------------------------\");\n  DEBUG_SERIAL.println(\"Odometry : \");   \n  DEBUG_SERIAL.print(\"         x : \"); DEBUG_SERIAL.println(odom_pose[0]);\n  DEBUG_SERIAL.print(\"         y : \"); DEBUG_SERIAL.println(odom_pose[1]);\n  DEBUG_SERIAL.print(\"     theta : \"); DEBUG_SERIAL.println(odom_pose[2]);\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_waffle/turtlebot3_core/turtlebot3_core_config.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho, Gilbert */\n\n#ifndef TURTLEBOT3_CORE_CONFIG_H_\n#define TURTLEBOT3_CORE_CONFIG_H_\n// #define NOETIC_SUPPORT          //uncomment this if writing code for ROS1 Noetic\n\n#include <ros.h>\n#include <ros/time.h>\n#include <std_msgs/Bool.h>\n#include <std_msgs/Empty.h>\n#include <std_msgs/Int32.h>\n#include <sensor_msgs/JointState.h>\n#include <geometry_msgs/Vector3.h>\n#include <tf/tf.h>\n#include <tf/transform_broadcaster.h>\n#include <nav_msgs/Odometry.h>\n\n#include <turtlebot3_msgs/SensorState.h>\n#include <turtlebot3_msgs/Sound.h>\n#include <turtlebot3_msgs/VersionInfo.h>\n\n#include <TurtleBot3.h>\n#include \"turtlebot3_waffle.h\"\n\n#include <math.h>\n\n#define FIRMWARE_VER \"1.2.6\"\n\n#define CONTROL_MOTOR_SPEED_FREQUENCY          30   //hz\n#define CONTROL_MOTOR_TIMEOUT                  500  //ms\n#define IMU_PUBLISH_FREQUENCY                  200  //hz\n#define CMD_VEL_PUBLISH_FREQUENCY              30   //hz\n#define DRIVE_INFORMATION_PUBLISH_FREQUENCY    30   //hz\n#define VERSION_INFORMATION_PUBLISH_FREQUENCY  1    //hz \n#define DEBUG_LOG_FREQUENCY                    10   //hz \n\n#define WHEEL_NUM                        2\n\n#define LEFT                             0\n#define RIGHT                            1\n\n#define LINEAR                           0\n#define ANGULAR                          1\n\n#define DEG2RAD(x)                       (x * 0.01745329252)  // *PI/180\n#define RAD2DEG(x)                       (x * 57.2957795131)  // *180/PI\n\n#define TICK2RAD                         0.001533981  // 0.087890625[deg] * 3.14159265359 / 180 = 0.001533981f\n\n#define TEST_DISTANCE                    0.300     // meter\n#define TEST_RADIAN                      3.14      // 180 degree\n\n// #define DEBUG                            \n#define DEBUG_SERIAL                     SerialBT2\n\n// Callback function prototypes\nvoid commandVelocityCallback(const geometry_msgs::Twist& cmd_vel_msg);\nvoid soundCallback(const turtlebot3_msgs::Sound& sound_msg);\nvoid motorPowerCallback(const std_msgs::Bool& power_msg);\nvoid resetCallback(const std_msgs::Empty& reset_msg);\n\n// Function prototypes\nvoid publishCmdVelFromRC100Msg(void);\nvoid publishImuMsg(void);\nvoid publishMagMsg(void);\nvoid publishSensorStateMsg(void);\nvoid publishVersionInfoMsg(void);\nvoid publishBatteryStateMsg(void);\nvoid publishDriveInformation(void);\n\nros::Time rosNow(void);\nros::Time addMicros(ros::Time & t, uint32_t _micros); // deprecated\n\nvoid updateVariable(bool isConnected);\nvoid updateMotorInfo(int32_t left_tick, int32_t right_tick);\nvoid updateTime(void);\nvoid updateOdometry(void);\nvoid updateJoint(void);\nvoid updateTF(geometry_msgs::TransformStamped& odom_tf);\nvoid updateGyroCali(bool isConnected);\nvoid updateGoalVelocity(void);\nvoid updateTFPrefix(bool isConnected);\n\nvoid initOdom(void);\nvoid initJointStates(void);\n\nbool calcOdometry(double diff_time);\n\nvoid sendLogMsg(void);\nvoid waitForSerialLink(bool isConnected);\n\n/*******************************************************************************\n* ROS NodeHandle\n*******************************************************************************/\nros::NodeHandle nh;\nros::Time current_time;\nuint32_t current_offset;\n\n/*******************************************************************************\n* ROS Parameter\n*******************************************************************************/\nchar get_prefix[10];\nchar* get_tf_prefix = get_prefix;\n\nchar odom_header_frame_id[30];\nchar odom_child_frame_id[30];\n\nchar imu_frame_id[30];\nchar mag_frame_id[30];\n\nchar joint_state_header_frame_id[30];\n\n/*******************************************************************************\n* Subscriber\n*******************************************************************************/\nros::Subscriber<geometry_msgs::Twist> cmd_vel_sub(\"cmd_vel\", commandVelocityCallback);\n\nros::Subscriber<turtlebot3_msgs::Sound> sound_sub(\"sound\", soundCallback);\n\nros::Subscriber<std_msgs::Bool> motor_power_sub(\"motor_power\", motorPowerCallback);\n\nros::Subscriber<std_msgs::Empty> reset_sub(\"reset\", resetCallback);\n\n/*******************************************************************************\n* Publisher\n*******************************************************************************/\n// Bumpers, cliffs, buttons, encoders, battery of Turtlebot3\nturtlebot3_msgs::SensorState sensor_state_msg;\nros::Publisher sensor_state_pub(\"sensor_state\", &sensor_state_msg);\n\n// Version information of Turtlebot3\nturtlebot3_msgs::VersionInfo version_info_msg;\nros::Publisher version_info_pub(\"firmware_version\", &version_info_msg);\n\n// IMU of Turtlebot3\nsensor_msgs::Imu imu_msg;\nros::Publisher imu_pub(\"imu\", &imu_msg);\n\n// Command velocity of Turtlebot3 using RC100 remote controller\ngeometry_msgs::Twist cmd_vel_rc100_msg;\nros::Publisher cmd_vel_rc100_pub(\"cmd_vel_rc100\", &cmd_vel_rc100_msg);\n\n// Odometry of Turtlebot3\nnav_msgs::Odometry odom;\nros::Publisher odom_pub(\"odom\", &odom);\n\n// Joint(Dynamixel) state of Turtlebot3\nsensor_msgs::JointState joint_states;\nros::Publisher joint_states_pub(\"joint_states\", &joint_states);\n\n// Battey state of Turtlebot3\n#if defined NOETIC_SUPPORT\nsensor_msgs::BatteryStateNoetic battery_state_msg;\n#else\nsensor_msgs::BatteryState battery_state_msg;\n#endif\nros::Publisher battery_state_pub(\"battery_state\", &battery_state_msg);\n\n// Magnetic field\nsensor_msgs::MagneticField mag_msg;\nros::Publisher mag_pub(\"magnetic_field\", &mag_msg);\n\n/*******************************************************************************\n* Transform Broadcaster\n*******************************************************************************/\n// TF of Turtlebot3\ngeometry_msgs::TransformStamped odom_tf;\ntf::TransformBroadcaster tf_broadcaster;\n\n/*******************************************************************************\n* SoftwareTimer of Turtlebot3\n*******************************************************************************/\nstatic uint32_t tTime[10];\n\n/*******************************************************************************\n* Declaration for motor\n*******************************************************************************/\nTurtlebot3MotorDriver motor_driver;\n\n/*******************************************************************************\n* Calculation for odometry\n*******************************************************************************/\nbool init_encoder = true;\nint32_t last_diff_tick[WHEEL_NUM] = {0, 0};\ndouble  last_rad[WHEEL_NUM]       = {0.0, 0.0};\n\n/*******************************************************************************\n* Update Joint State\n*******************************************************************************/\ndouble  last_velocity[WHEEL_NUM]  = {0.0, 0.0};\n\n/*******************************************************************************\n* Declaration for sensors\n*******************************************************************************/\nTurtlebot3Sensor sensors;\n\n/*******************************************************************************\n* Declaration for controllers\n*******************************************************************************/\nTurtlebot3Controller controllers;\nfloat zero_velocity[WHEEL_NUM] = {0.0, 0.0};\nfloat goal_velocity[WHEEL_NUM] = {0.0, 0.0};\nfloat goal_velocity_from_button[WHEEL_NUM] = {0.0, 0.0};\nfloat goal_velocity_from_cmd[WHEEL_NUM] = {0.0, 0.0};\nfloat goal_velocity_from_rc100[WHEEL_NUM] = {0.0, 0.0};\n\n/*******************************************************************************\n* Declaration for diagnosis\n*******************************************************************************/\nTurtlebot3Diagnosis diagnosis;\n\n/*******************************************************************************\n* Declaration for SLAM and navigation\n*******************************************************************************/\nunsigned long prev_update_time;\nfloat odom_pose[3];\ndouble odom_vel[3];\n\n/*******************************************************************************\n* Declaration for Battery\n*******************************************************************************/\nbool setup_end        = false;\nuint8_t battery_state = 0;\n\n#endif // TURTLEBOT3_CORE_CONFIG_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_waffle/turtlebot3_core/turtlebot3_waffle.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#ifndef TURTLEBOT3_WAFFLE_H_\n#define TURTLEBOT3_WAFFLE_H_\n\n#define NAME                             \"Waffle or Waffle Pi\"\n\n#define WHEEL_RADIUS                     0.033           // meter\n#define WHEEL_SEPARATION                 0.287           // meter (BURGER : 0.160, WAFFLE : 0.287)\n#define TURNING_RADIUS                   0.1435          // meter (BURGER : 0.080, WAFFLE : 0.1435)\n#define ROBOT_RADIUS                     0.220           // meter (BURGER : 0.105, WAFFLE : 0.220)\n#define ENCODER_MIN                      -2147483648     // raw\n#define ENCODER_MAX                      2147483648      // raw\n\n#define MAX_LINEAR_VELOCITY              (WHEEL_RADIUS * 2 * 3.14159265359 * 77 / 60) // m/s  (BURGER : 61[rpm], WAFFLE : 77[rpm])\n#define MAX_ANGULAR_VELOCITY             (MAX_LINEAR_VELOCITY / TURNING_RADIUS)       // rad/s\n\n#define MIN_LINEAR_VELOCITY              -MAX_LINEAR_VELOCITY  \n#define MIN_ANGULAR_VELOCITY             -MAX_ANGULAR_VELOCITY \n\n#endif  //TURTLEBOT3_WAFFLE_H_"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_with_open_manipulator/turtlebot3_with_open_manipulator_core/open_manipulator_driver.cpp",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Taehun Lim (Darby) */\n\n#include \"open_manipulator_driver.h\"\n\nOpenManipulatorDriver::OpenManipulatorDriver()\n  :torque_state_(false)\n{\n}\n\nOpenManipulatorDriver::~OpenManipulatorDriver()\n{\n  closeDynamixel();\n}\n\nbool OpenManipulatorDriver::init(uint8_t *joint_id, uint8_t joint_cnt, uint8_t *gripper_id, uint8_t gripper_cnt)\n{\n  DEBUG_SERIAL.begin(57600);\n\n  const char *log;\n  bool result = false;\n\n  result = dxl_wb_.init(DEVICENAME, BAUDRATE, &log);\n  if (result == false)\n  {\n    DEBUG_SERIAL.println(log);\n    DEBUG_SERIAL.println(\"Failed to init\");\n  }\n  else\n  {\n    DEBUG_SERIAL.print(\"Succeeded to init : \");\n    DEBUG_SERIAL.println(BAUDRATE);  \n  }\n\n  uint16_t model_number = 0;\n  for (uint8_t num = 0; num < joint_cnt; num++)\n  {\n    result = dxl_wb_.ping(joint_id[num], &model_number, &log);\n    if (result == false)\n    {\n      DEBUG_SERIAL.println(log);\n      DEBUG_SERIAL.println(\"Failed to ping\");\n    }\n    else\n    {\n      DEBUG_SERIAL.println(\"Succeeded to ping\");\n      DEBUG_SERIAL.print(\"id : \");\n      DEBUG_SERIAL.print(joint_id[num]);\n      DEBUG_SERIAL.print(\" model_number : \");\n      DEBUG_SERIAL.println(model_number);\n\n      if (dxl_wb_.getProtocolVersion() == 2.0f)\n      {\n        result = dxl_wb_.torqueOff(joint_id[num], &log);\n        if (result == false)\n        {\n          DEBUG_SERIAL.println(log);\n          DEBUG_SERIAL.println(\"Failed to set torque off\");\n        }\n        else\n        {\n          DEBUG_SERIAL.println(\"Succeeded to set torque off\");\n        }\n\n        result = dxl_wb_.setTimeBasedProfile(joint_id[num], &log);\n        if (result == false)\n        {\n          DEBUG_SERIAL.println(log);\n          DEBUG_SERIAL.println(\"Failed to set velocity based profile mode\");\n        }\n        else\n        {\n          DEBUG_SERIAL.println(\"Succeeded to set velocity based profile mode\");\n        }\n      }\n\n      result = dxl_wb_.jointMode(joint_id[num], 0, 0, &log);\n      if (result == false)\n      {\n        DEBUG_SERIAL.println(log);\n        DEBUG_SERIAL.println(\"Failed to change joint mode\");\n      }\n      else\n      {\n        DEBUG_SERIAL.println(\"Succeeded to change joint mode\");\n      }\n\n      joint_.id[num] = joint_id[num];\n      joint_.cnt = joint_cnt;\n    }\n  }\n\n  for (uint8_t num = 0; num < gripper_cnt; num++)\n  {\n    result = dxl_wb_.ping(gripper_id[num], &model_number, &log);\n    if (result == false)\n    {\n      DEBUG_SERIAL.println(log);\n      DEBUG_SERIAL.println(\"Failed to ping\");\n    }\n    else\n    {\n      DEBUG_SERIAL.println(\"Succeeded to ping\");\n      DEBUG_SERIAL.print(\"id : \");\n      DEBUG_SERIAL.print(gripper_id[num]);\n      DEBUG_SERIAL.print(\" model_number : \");\n      DEBUG_SERIAL.println(model_number);\n\n      result = dxl_wb_.currentBasedPositionMode(gripper_id[num], 100, &log);\n      if (result == false)\n      {\n        DEBUG_SERIAL.println(log);\n        DEBUG_SERIAL.println(\"Failed to change gripper mode\");\n        DEBUG_SERIAL.println(\"Set joint mode to gripper\");\n        \n        if (dxl_wb_.getProtocolVersion() == 2.0f)\n        {\n          result = dxl_wb_.torqueOff(joint_id[num], &log);  \n          if (result == true) DEBUG_SERIAL.println(\"Succeeded to set torque off\");\n\n          result = dxl_wb_.setTimeBasedProfile(joint_id[num], &log);\n          if (result == true) DEBUG_SERIAL.println(\"Succeeded to set velocity based profile mode\");\n        }\n\n        result = dxl_wb_.jointMode(gripper_id[num], 0, 0, &log);\n        if (result == true) DEBUG_SERIAL.println(\"Succeeded to change joint mode\");\n      }\n      else\n      {\n        DEBUG_SERIAL.println(\"Succeeded to change gripper mode\");\n      }\n\n      gripper_.id[num] = gripper_id[num];\n      gripper_.cnt = gripper_cnt;\n    }\n  }\n\n  torque_state_ = true;\n\n  result = dxl_wb_.addSyncWriteHandler(joint_.id[0], \"Goal_Position\", &log);\n  if (result == false)\n  {\n    DEBUG_SERIAL.println(log);\n    DEBUG_SERIAL.println(\"Failed to add sync write handler\");\n  }\n\n  if (dxl_wb_.getProtocolVersion() == 2.0f)\n  {\n    const uint8_t ADDR_PROFILE_ACCELERATION = 108;\n    const uint8_t LEN_PROFILE_ACCELERATION_PROFILE_VELOCITY = 4+4;\n    const uint8_t ADDR_PRESENT_CURRENT = 126;\n    const uint8_t LEN_PROFILE_CURRENT_VELOCITY_POSITION = 2+4+4;\n\n    result = dxl_wb_.addSyncWriteHandler(ADDR_PROFILE_ACCELERATION, LEN_PROFILE_ACCELERATION_PROFILE_VELOCITY, &log);\n    if (result == false)\n    {\n      DEBUG_SERIAL.println(log);\n      DEBUG_SERIAL.println(\"Failed to add sync write handler\");\n    }\n\n    result = dxl_wb_.addSyncReadHandler(ADDR_PRESENT_CURRENT, \n                                         LEN_PROFILE_CURRENT_VELOCITY_POSITION, \n                                         &log);\n    if (result == false)\n    {\n      DEBUG_SERIAL.println(log);\n      DEBUG_SERIAL.println(\"Failed to add sync read handler\");\n    }\n  }\n\n  double init_joint_position[4] = {0.0, -1.57, 1.20, 0.6};\n  double init_gripper_position[1] = {0.0};\n\n  writeJointProfileControlParam(3.0f, 0.75f);\n  writeGripperProfileControlParam(0.0f);\n  writeJointPosition(init_joint_position);  \n  writeGripperPosition(init_gripper_position);\n\n  writeJointProfileControlParam(0.0f);\n  writeGripperProfileControlParam(0.0f);\n\n  DEBUG_SERIAL.println(\"Succeeded to init OpenManipulator Driver\");\n\n  return true;\n}\n\nvoid OpenManipulatorDriver::closeDynamixel(void)\n{\n  // Disable Dynamixel Torque\n  setTorque(false);\n}\n\nbool OpenManipulatorDriver::setTorque(bool onoff)\n{ \n  const char *log;\n  bool result = false;\n\n  for (int num = 0; num < joint_.cnt; num++)  \n  {\n    result = dxl_wb_.torque(joint_.id[num], onoff, &log);\n    if (result == false)\n    {\n      DEBUG_SERIAL.println(log);\n    }\n    else\n    {\n      DEBUG_SERIAL.println(\"Succeeded to set torque\");\n    }\n  }\n\n  for (int num = 0; num < gripper_.cnt; num++)  \n  {\n    result = dxl_wb_.torque(gripper_.id[num], onoff, &log);\n    if (result == false)\n    {\n      DEBUG_SERIAL.println(log);\n    }\n    else\n    {\n      DEBUG_SERIAL.println(\"Succeeded to set torque\");\n    }\n  }\n\n  if (result == true)\n    torque_state_ = onoff;\n\n  return result;\n}\n\nbool OpenManipulatorDriver::getTorqueState()\n{\n  return torque_state_;\n}\n\nbool OpenManipulatorDriver::syncReadDynamixelInfo(void)\n{\n  const char *log;\n  bool result = false;\n  const uint8_t HANDLER_INDEX = 0;\n\n  if (dxl_wb_.getProtocolVersion() == 2.0f)\n  {\n    result = dxl_wb_.syncRead(HANDLER_INDEX, &log);\n    if (result == false)\n    {\n      DEBUG_SERIAL.println(log);\n      DEBUG_SERIAL.println(\"Failed to sync read position\");\n    }\n  }\n\n  return true;\n}\n\nbool OpenManipulatorDriver::getPosition(double *get_data)\n{\n  const char *log;\n  bool result = false;\n  const uint8_t HANDLER_INDEX = 0;\n  const uint8_t ADDR_PRESENT_POSITION_2 = 132;\n  const uint8_t LENGTH_PRESENT_POSITION_2 = 4;\n\n  int32_t get_present_joint_position[joint_.cnt];\n  int32_t get_present_gripper_position[gripper_.cnt];\n\n  if (dxl_wb_.getProtocolVersion() == 2.0f)\n  {\n    result = dxl_wb_.getSyncReadData(HANDLER_INDEX, \n                                    &joint_.id[0], \n                                    joint_.cnt, \n                                    ADDR_PRESENT_POSITION_2,\n                                    LENGTH_PRESENT_POSITION_2,\n                                    &get_present_joint_position[0], \n                                    &log);\n    if (result == false)\n    {\n      DEBUG_SERIAL.println(log);\n    }\n\n    result = dxl_wb_.getSyncReadData(HANDLER_INDEX, \n                                &gripper_.id[0], \n                                gripper_.cnt, \n                                ADDR_PRESENT_POSITION_2,\n                                LENGTH_PRESENT_POSITION_2,\n                                &get_present_gripper_position[0], \n                                &log);\n    if (result == false)\n    {\n      DEBUG_SERIAL.println(log);\n    }\n\n    for (uint8_t num = 0; num < joint_.cnt; num++)\n    {\n      get_data[num] = dxl_wb_.convertValue2Radian(joint_.id[num], get_present_joint_position[num]);\n    }\n\n    for (uint8_t num = 0; num < gripper_.cnt; num++)\n    {\n      get_data[joint_.cnt + num] = dxl_wb_.convertValue2Radian(gripper_.id[num], get_present_gripper_position[num]);\n    }  \n  }\n  else if (dxl_wb_.getProtocolVersion() == 1.0f)\n  {\n    for (uint8_t num = 0; num < joint_.cnt; num++)\n    {\n      result = dxl_wb_.itemRead(joint_.id[num], \"Present_Position\", &get_present_joint_position[num], &log);\n      if (result == false)\n      {\n        DEBUG_SERIAL.println(log);\n        DEBUG_SERIAL.println(\"Failed to get joint present position\");\n      }\n      else\n      {\n        get_data[num] = dxl_wb_.convertValue2Radian(joint_.id[num], get_present_joint_position[num]);\n      }\n    }\n\n    for (uint8_t num = 0; num < gripper_.cnt; num++)\n    {\n      result = dxl_wb_.itemRead(gripper_.id[num], \"Present_Position\", &get_present_gripper_position[num], &log);\n      if (result == false)\n      {\n        DEBUG_SERIAL.println(log);\n        DEBUG_SERIAL.println(\"Failed to get gripper present position\");\n      }\n      else\n      {\n        get_data[joint_.cnt + num] = dxl_wb_.convertValue2Radian(gripper_.id[num], get_present_gripper_position[num]);\n      }\n    }\n  }\n\n  return true;\n}\n\nbool OpenManipulatorDriver::getVelocity(double *get_data)\n{\n  const char *log;\n  bool result = false;\n  const uint8_t HANDLER_INDEX = 0;\n  const uint8_t ADDR_PRESENT_VELOCITY_2 = 128;\n  const uint8_t LENGTH_PRESENT_VELOCITY_2 = 4;\n\n  int32_t get_present_joint_velocity[joint_.cnt];\n  int32_t get_present_gripper_velocity[gripper_.cnt];\n\n  if (dxl_wb_.getProtocolVersion() == 2.0f)\n  {\n    result = dxl_wb_.getSyncReadData(HANDLER_INDEX, \n                                    &joint_.id[0], \n                                    joint_.cnt, \n                                    ADDR_PRESENT_VELOCITY_2,\n                                    LENGTH_PRESENT_VELOCITY_2,\n                                    &get_present_joint_velocity[0], \n                                    &log);\n    if (result == false)\n    {\n      DEBUG_SERIAL.println(log);\n    }\n\n    result = dxl_wb_.getSyncReadData(HANDLER_INDEX, \n                                &gripper_.id[0], \n                                gripper_.cnt, \n                                ADDR_PRESENT_VELOCITY_2,\n                                LENGTH_PRESENT_VELOCITY_2,\n                                &get_present_gripper_velocity[0], \n                                &log);\n    if (result == false)\n    {\n      DEBUG_SERIAL.println(log);\n    }\n\n    for (uint8_t num = 0; num < joint_.cnt; num++)\n    {\n      get_data[num] = dxl_wb_.convertValue2Velocity(joint_.id[num], get_present_joint_velocity[num]);\n    }\n\n    for (uint8_t num = 0; num < gripper_.cnt; num++)\n    {\n      get_data[joint_.cnt + num] = dxl_wb_.convertValue2Velocity(gripper_.id[num], get_present_gripper_velocity[num]);\n    } \n  }\n  else\n  {\n    return false;\n  }\n\n  return true;\n}\n\nbool OpenManipulatorDriver::getCurrent(double *get_data)\n{\n  const char *log;\n  bool result = false;\n  const uint8_t HANDLER_INDEX = 0;\n  const uint8_t ADDR_PRESENT_CURRENT_2 = 126;\n  const uint8_t LENGTH_PRESENT_CURRENT_2 = 2;\n\n  int32_t get_present_joint_current[joint_.cnt];\n  int32_t get_present_gripper_current[gripper_.cnt];\n\n  if (dxl_wb_.getProtocolVersion() == 2.0f)\n  {\n    result = dxl_wb_.getSyncReadData(HANDLER_INDEX, \n                                    &joint_.id[0], \n                                    joint_.cnt, \n                                    ADDR_PRESENT_CURRENT_2,\n                                    LENGTH_PRESENT_CURRENT_2,\n                                    &get_present_joint_current[0], \n                                    &log);\n    if (result == false)\n    {\n      DEBUG_SERIAL.println(log);\n    }\n\n    result = dxl_wb_.getSyncReadData(HANDLER_INDEX, \n                                &gripper_.id[0], \n                                gripper_.cnt, \n                                ADDR_PRESENT_CURRENT_2,\n                                LENGTH_PRESENT_CURRENT_2,\n                                &get_present_gripper_current[0], \n                                &log);\n    if (result == false)\n    {\n      DEBUG_SERIAL.println(log);\n    }\n\n    for (uint8_t num = 0; num < joint_.cnt; num++)\n    {\n      get_data[num] = dxl_wb_.convertValue2Current(get_present_joint_current[num]);\n    }\n\n    for (uint8_t num = 0; num < gripper_.cnt; num++)\n    {\n      get_data[joint_.cnt + num] = dxl_wb_.convertValue2Current(get_present_gripper_current[num]);\n    }  \n  }\n  else\n  {\n    return false;\n  }\n\n  return true;\n}\n\nbool OpenManipulatorDriver::writeJointProfileControlParam(double set_time, double acc)\n{\n  const char *log;\n  bool result = false;\n  const uint8_t HANDLER_INDEX = 1;\n  int32_t goal_data[joint_.cnt*2];\n\n  for (uint8_t num = 0; num < joint_.cnt * 2; num = num + 2)\n  {\n    goal_data[num] = acc * 1000;\n    goal_data[num+1] = set_time * 1000;\n  }\n\n  if (dxl_wb_.getProtocolVersion() == 2.0f)\n  {\n    result = dxl_wb_.syncWrite(HANDLER_INDEX, joint_.id, joint_.cnt, &goal_data[0], 2, &log);\n    if (result == false)\n    {\n      DEBUG_SERIAL.println(log);\n      DEBUG_SERIAL.println(\"Failed to sync write param for profile\");\n    }\n  }\n  else\n  {\n    return false;\n  }\n\n  return true;\n}\n\nbool OpenManipulatorDriver::writeJointPosition(double *set_data)\n{\n  const char *log;\n  bool result = false;\n  const uint8_t HANDLER_INDEX = 0;\n  int32_t goal_position[joint_.cnt];\n\n  for (int num = 0; num < joint_.cnt; num++)\n  {\n    goal_position[num] = dxl_wb_.convertRadian2Value(joint_.id[num], set_data[num]);\n  }\n\n  result = dxl_wb_.syncWrite(HANDLER_INDEX, joint_.id, joint_.cnt, &goal_position[0], 1, &log);\n  if (result == false)\n  {\n    DEBUG_SERIAL.println(log);\n    DEBUG_SERIAL.println(\"Failed to sync write position\");\n  }\n\n  return true;\n}\n\nbool OpenManipulatorDriver::writeGripperProfileControlParam(double set_time)\n{\n  const char *log;\n  bool result = false;\n  const uint8_t HANDLER_INDEX = 1;\n  int32_t goal_data[gripper_.cnt*2];\n\n  for (uint8_t num = 0; num < gripper_.cnt; num++)\n  {\n    goal_data[num] = (set_time * 1000) / 4;\n    goal_data[num+1] = set_time * 1000;\n  }\n\n  if (dxl_wb_.getProtocolVersion() == 2.0f)\n  {\n    result = dxl_wb_.syncWrite(HANDLER_INDEX, gripper_.id, gripper_.cnt, &goal_data[0], 2, &log);\n    if (result == false)\n    {\n      DEBUG_SERIAL.println(log);\n      DEBUG_SERIAL.println(\"Failed to sync write param for profile\");\n    }\n  }\n  else\n  {\n    return false;\n  }\n\n  return true;\n}\n\nbool OpenManipulatorDriver::writeGripperPosition(double *set_data)\n{\n  const char *log;\n  bool result = false;\n  const uint8_t HANDLER_INDEX = 0;\n  int32_t goal_position[gripper_.cnt];\n\n  for (int num = 0; num < gripper_.cnt; num++)\n  {\n    goal_position[num] = dxl_wb_.convertRadian2Value(gripper_.id[num], set_data[num]);\n  }\n\n  result = dxl_wb_.syncWrite(HANDLER_INDEX, gripper_.id, gripper_.cnt, &goal_position[0], 1, &log);\n  if (result == false)\n  {\n    DEBUG_SERIAL.println(log);\n    DEBUG_SERIAL.println(\"Failed to sync write position\");\n  }\n\n  return true;\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_with_open_manipulator/turtlebot3_with_open_manipulator_core/open_manipulator_driver.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Taehun Lim (Darby) */\n\n#ifndef OPEN_MANIPULATOR_DRIVER_H_\n#define OPEN_MANIPULATOR_DRIVER_H_\n\n#include <DynamixelWorkbench.h>\n\n#define BAUDRATE                        1000000 // baurd rate of Dynamixel\n#define DEVICENAME                      \"\"      // no need setting on OpenCR\n\n#define JOINT_ID_1                       11\n#define JOINT_ID_2                       12\n#define JOINT_ID_3                       13\n#define JOINT_ID_4                       14\n#define JOINT_CNT                        4\n\n#define GRIPPER_ID_1                     15\n#define GRIPPER_CNT                      1\n\n#define DEBUG_SERIAL  SerialBT2\n\ntypedef struct\n{\n  uint8_t id[20];\n  uint8_t cnt;\n} Dynamixel;\n\nclass OpenManipulatorDriver\n{\n public:\n  OpenManipulatorDriver();\n  ~OpenManipulatorDriver();\n\n  bool init(uint8_t *joint_id, uint8_t joint_cnt, uint8_t *gripper_id, uint8_t gripper_cnt);\n  void closeDynamixel(void);\n  bool setTorque(bool onoff);\n  bool getTorqueState(void);\n  bool syncReadDynamixelInfo(void);\n  bool getPosition(double *get_data);\n  bool getVelocity(double *get_data);\n  bool getCurrent(double *get_data);\n  bool writeJointPosition(double *set_data);\n  bool writeJointProfileControlParam(double set_time, double acc = 0.0f);\n  bool writeGripperPosition(double *set_data);\n  bool writeGripperProfileControlParam(double set_time);\n\n private:\n  DynamixelWorkbench dxl_wb_;\n\n  Dynamixel joint_;\n  Dynamixel gripper_;\n\n  bool torque_state_;\n};\n\n#endif // OPEN_MANIPULATOR_DRIVER_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_with_open_manipulator/turtlebot3_with_open_manipulator_core/turtlebot3_with_open_manipulator.h",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#ifndef TURTLEBOT3_WITH_OPEN_MANIPULATOR_H_\n#define TURTLEBOT3_WITH_OPEN_MANIPULATOR_H_\n\n#include \"open_manipulator_driver.h\"\n\n#define NAME                             \"Waffle or Waffle Pi\"\n\n#define WHEEL_RADIUS                     0.033           // meter\n#define WHEEL_SEPARATION                 0.287           // meter (BURGER : 0.160, WAFFLE : 0.287)\n#define TURNING_RADIUS                   0.1435          // meter (BURGER : 0.080, WAFFLE : 0.1435)\n#define ROBOT_RADIUS                     0.220           // meter (BURGER : 0.105, WAFFLE : 0.220)\n#define ENCODER_MIN                      -2147483648     // raw\n#define ENCODER_MAX                      2147483648      // raw\n\n#define MAX_LINEAR_VELOCITY              (WHEEL_RADIUS * 2 * 3.14159265359 * 77 / 60) // m/s  (BURGER : 61[rpm], WAFFLE : 77[rpm])\n#define MAX_ANGULAR_VELOCITY             (MAX_LINEAR_VELOCITY / TURNING_RADIUS)       // rad/s\n\n#define MIN_LINEAR_VELOCITY              -MAX_LINEAR_VELOCITY  \n#define MIN_ANGULAR_VELOCITY             -MAX_ANGULAR_VELOCITY \n\n#endif  //TURTLEBOT3_WITH_OPEN_MANIPULATOR_H_"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_with_open_manipulator/turtlebot3_with_open_manipulator_core/turtlebot3_with_open_manipulator_core.ino",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#include \"turtlebot3_with_open_manipulator_core_config.h\"\n\n/*******************************************************************************\n* Setup function\n*******************************************************************************/\nvoid setup()\n{\n  DEBUG_SERIAL.begin(57600);\n\n  // Initialize ROS node handle, advertise and subscribe the topics\n  nh.initNode();\n  nh.getHardware()->setBaud(115200);\n\n  nh.subscribe(cmd_vel_sub);\n  nh.subscribe(joint_position_sub);\n  nh.subscribe(joint_move_time_sub);\n  nh.subscribe(gripper_position_sub);\n  nh.subscribe(gripper_move_time_sub);\n  nh.subscribe(sound_sub);\n  nh.subscribe(motor_power_sub);\n  nh.subscribe(reset_sub);\n\n  nh.advertise(sensor_state_pub);\n  nh.advertise(version_info_pub);\n  nh.advertise(imu_pub);\n  nh.advertise(cmd_vel_rc100_pub);\n  nh.advertise(odom_pub);\n  nh.advertise(joint_states_pub);\n  nh.advertise(battery_state_pub);\n  nh.advertise(mag_pub);\n\n  tf_broadcaster.init(nh);\n\n  // Setting for Dynamixel motors\n  motor_driver.init(NAME);\n  manipulator_driver.init(&joint_id[0], joint_cnt, &gripper_id[0], gripper_cnt);\n\n  // Setting for IMU\n  sensors.init();\n\n  // Init diagnosis\n  diagnosis.init();\n\n  // Setting for ROBOTIS RC100 remote controller and cmd_vel\n  controllers.init(MAX_LINEAR_VELOCITY, MAX_ANGULAR_VELOCITY);\n\n  // Setting for SLAM and navigation (odometry, joint states, TF)\n  initOdom();\n\n  initJointStates();\n\n  prev_update_time = millis();\n\n  pinMode(LED_WORKING_CHECK, OUTPUT);\n\n  setup_end = true;\n}\n\n/*******************************************************************************\n* Loop function\n*******************************************************************************/\nvoid loop()\n{\n  uint32_t t = millis();\n  updateTime();\n  updateVariable(nh.connected());\n  updateTFPrefix(nh.connected());\n\n  if ((t-tTime[0]) >= (1000 / CONTROL_MOTOR_SPEED_FREQUENCY))\n  {\n    updateGoalVelocity(nh.connected());\n    motor_driver.controlMotor(WHEEL_RADIUS, WHEEL_SEPARATION, goal_velocity);\n    tTime[0] = t;\n  }\n\n  if ((t-tTime[1]) >= (1000 / CMD_VEL_PUBLISH_FREQUENCY))\n  {\n    publishCmdVelFromRC100Msg();\n    tTime[1] = t;\n  }\n\n  if ((t-tTime[2]) >= (1000 / DRIVE_INFORMATION_PUBLISH_FREQUENCY))\n  {\n    publishSensorStateMsg();\n    publishBatteryStateMsg();\n    publishDriveInformation();\n    tTime[2] = t;\n  }\n\n  if ((t-tTime[3]) >= (1000 / IMU_PUBLISH_FREQUENCY))\n  {\n    publishImuMsg();\n    publishMagMsg();\n    tTime[3] = t;\n  }\n\n  if ((t-tTime[4]) >= (1000 / VERSION_INFORMATION_PUBLISH_FREQUENCY))\n  {\n    publishVersionInfoMsg();\n    tTime[4] = t;\n  }\n\n#ifdef DEBUG\n  if ((t-tTime[5]) >= (1000 / DEBUG_LOG_FREQUENCY))\n  {\n    sendDebuglog();\n    tTime[5] = t;\n  }\n#endif\n\n  if ((t-tTime[6]) >= (1000 / JOINT_CONTROL_FREQEUNCY))\n  {\n    jointControl();\n    tTime[6] = t;\n  }\n\n  // Send log message after ROS connection\n  sendLogMsg();\n\n  // Receive data from RC100\n  controllers.getRCdata(goal_velocity_from_rc100);\n\n  // Check push button pressed for simple test drive\n  driveTest(diagnosis.getButtonPress(3000));\n\n  // Update the IMU unit\n  sensors.updateIMU();\n\n  // TODO\n  // Update sonar data\n  // sensors.updateSonar(t);\n\n  // Start Gyro Calibration after ROS connection\n  updateGyroCali();\n\n  // Show LED status\n  diagnosis.showLedStatus(nh.connected());\n\n  // Update Voltage\n  battery_state = diagnosis.updateVoltageCheck(setup_end);\n\n  // Call all the callbacks waiting to be called at that point in time\n  nh.spinOnce();\n\n  // Wait the serial link time to process\n  waitForSerialLink(nh.connected());\n}\n\n/*******************************************************************************\n* Callback function for cmd_vel msg\n*******************************************************************************/\nvoid commandVelocityCallback(const geometry_msgs::Twist& cmd_vel_msg)\n{\n  goal_velocity_from_cmd[LINEAR]  = cmd_vel_msg.linear.x;\n  goal_velocity_from_cmd[ANGULAR] = cmd_vel_msg.angular.z;\n\n  goal_velocity_from_cmd[LINEAR]  = constrain(goal_velocity_from_cmd[LINEAR],  MIN_LINEAR_VELOCITY, MAX_LINEAR_VELOCITY);\n  goal_velocity_from_cmd[ANGULAR] = constrain(goal_velocity_from_cmd[ANGULAR], MIN_ANGULAR_VELOCITY, MAX_ANGULAR_VELOCITY);\n}\n\n/*******************************************************************************\n* Callback function for joint trajectory msg\n*******************************************************************************/\nvoid jointTrajectoryPointCallback(const std_msgs::Float64MultiArray& joint_trajectory_point_msg)\n{\n  if (is_moving == false)\n  {\n    joint_trajectory_point = joint_trajectory_point_msg;\n    is_moving = true;\n  }\n}\n\n/*******************************************************************************\n* Callback function for joint move time msg\n*******************************************************************************/\nvoid jointMoveTimeCallback(const std_msgs::Float64& time_msg)\n{\n  double data = time_msg.data;\n\n  manipulator_driver.writeJointProfileControlParam(data);\n}\n\n/*******************************************************************************\n* Callback function for gripper position msg\n*******************************************************************************/\nvoid gripperPositionCallback(const std_msgs::Float64MultiArray& gripper_msg)\n{\n  double goal_gripper_position[5] = {0.0, };\n  const double OPEN_MANIPULATOR_GRIPPER_OFFSET = -0.015f;\n\n  for (int index = 0; index < gripper_cnt; index++)\n    goal_gripper_position[index] = gripper_msg.data[index] / OPEN_MANIPULATOR_GRIPPER_OFFSET;\n\n  manipulator_driver.writeGripperPosition(goal_gripper_position);\n}\n\n/*******************************************************************************\n* Callback function for gripper move time msg\n*******************************************************************************/\nvoid gripperMoveTimeCallback(const std_msgs::Float64& time_msg)\n{\n  double data = time_msg.data;\n\n  manipulator_driver.writeGripperProfileControlParam(data);\n}\n\n/*******************************************************************************\n* Callback function for sound msg\n*******************************************************************************/\nvoid soundCallback(const turtlebot3_msgs::Sound& sound_msg)\n{\n  sensors.makeSound(sound_msg.value);\n}\n\n/*******************************************************************************\n* Callback function for motor_power msg\n*******************************************************************************/\nvoid motorPowerCallback(const std_msgs::Bool& power_msg)\n{\n  bool dxl_power = power_msg.data;\n\n  motor_driver.setTorque(dxl_power);\n  manipulator_driver.setTorque(dxl_power);\n}\n\n/*******************************************************************************\n* Callback function for reset msg\n*******************************************************************************/\nvoid resetCallback(const std_msgs::Empty& reset_msg)\n{\n  char log_msg[50];\n\n  (void)(reset_msg);\n\n  sprintf(log_msg, \"Start Calibration of Gyro\");\n  nh.loginfo(log_msg);\n\n  sensors.calibrationGyro();\n\n  sprintf(log_msg, \"Calibration End\");\n  nh.loginfo(log_msg);\n\n  initOdom();\n\n  sprintf(log_msg, \"Reset Odometry\");\n  nh.loginfo(log_msg);\n}\n\n/*******************************************************************************\n* Publish msgs (CMD Velocity data from RC100 : angular velocity, linear velocity)\n*******************************************************************************/\nvoid publishCmdVelFromRC100Msg(void)\n{\n  cmd_vel_rc100_msg.linear.x  = goal_velocity_from_rc100[LINEAR];\n  cmd_vel_rc100_msg.angular.z = goal_velocity_from_rc100[ANGULAR];\n\n  cmd_vel_rc100_pub.publish(&cmd_vel_rc100_msg);\n}\n\n/*******************************************************************************\n* Publish msgs (IMU data: angular velocity, linear acceleration, orientation)\n*******************************************************************************/\nvoid publishImuMsg(void)\n{\n  imu_msg = sensors.getIMU();\n\n  imu_msg.header.stamp    = rosNow();\n  imu_msg.header.frame_id = imu_frame_id;\n\n  imu_pub.publish(&imu_msg);\n}\n\n/*******************************************************************************\n* Publish msgs (Magnetic data)\n*******************************************************************************/\nvoid publishMagMsg(void)\n{\n  mag_msg = sensors.getMag();\n\n  mag_msg.header.stamp    = rosNow();\n  mag_msg.header.frame_id = mag_frame_id;\n\n  mag_pub.publish(&mag_msg);\n}\n\n/*******************************************************************************\n* Publish msgs (sensor_state: bumpers, cliffs, buttons, encoders, battery)\n*******************************************************************************/\nvoid publishSensorStateMsg(void)\n{\n  bool dxl_comm_result = false;\n\n  sensor_state_msg.header.stamp = rosNow();\n  sensor_state_msg.battery = sensors.checkVoltage();\n\n  dxl_comm_result = motor_driver.readEncoder(sensor_state_msg.left_encoder, sensor_state_msg.right_encoder);\n\n  if (dxl_comm_result == true)\n    updateMotorInfo(sensor_state_msg.left_encoder, sensor_state_msg.right_encoder);\n  else\n    return;\n\n  sensor_state_msg.bumper = sensors.checkPushBumper();\n\n  sensor_state_msg.cliff = sensors.getIRsensorData();\n\n  // TODO\n  // sensor_state_msg.sonar = sensors.getSonarData();\n\n  sensor_state_msg.illumination = sensors.getIlluminationData();\n\n  sensor_state_msg.button = sensors.checkPushButton();\n\n  sensor_state_msg.torque = motor_driver.getTorque();\n\n  sensor_state_pub.publish(&sensor_state_msg);\n}\n\n/*******************************************************************************\n* Publish msgs (version info)\n*******************************************************************************/\nvoid publishVersionInfoMsg(void)\n{\n  version_info_msg.hardware = \"0.0.0\";\n  version_info_msg.software = \"0.0.0\";\n  version_info_msg.firmware = FIRMWARE_VER;\n\n  version_info_pub.publish(&version_info_msg);\n}\n\n/*******************************************************************************\n* Publish msgs (battery_state)\n*******************************************************************************/\nvoid publishBatteryStateMsg(void)\n{\n  battery_state_msg.header.stamp = rosNow();\n  battery_state_msg.design_capacity = 1.8f; //Ah\n  battery_state_msg.voltage = sensors.checkVoltage();\n  battery_state_msg.percentage = (float)(battery_state_msg.voltage / 11.1f);\n\n  if (battery_state == 0)\n    battery_state_msg.present = false;\n  else\n    battery_state_msg.present = true;\n\n  battery_state_pub.publish(&battery_state_msg);\n}\n\n/*******************************************************************************\n* Publish msgs (odometry, joint states, tf)\n*******************************************************************************/\nvoid publishDriveInformation(void)\n{\n  unsigned long time_now = millis();\n  unsigned long step_time = time_now - prev_update_time;\n\n  prev_update_time = time_now;\n  ros::Time stamp_now = rosNow();\n\n  // calculate odometry\n  calcOdometry((double)(step_time * 0.001));\n\n  // odometry\n  updateOdometry();\n  odom.header.stamp = stamp_now;\n  odom_pub.publish(&odom);\n\n  // odometry tf\n  updateTF(odom_tf);\n  odom_tf.header.stamp = stamp_now;\n  tf_broadcaster.sendTransform(odom_tf);\n\n  // joint states\n  updateJointStates();\n  joint_states.header.stamp = stamp_now;\n  joint_states_pub.publish(&joint_states);\n}\n\n/*******************************************************************************\n* Update TF Prefix\n*******************************************************************************/\nvoid updateTFPrefix(bool isConnected)\n{\n  static bool isChecked = false;\n  char log_msg[50];\n\n  if (isConnected)\n  {\n    if (isChecked == false)\n    {\n      nh.getParam(\"~tf_prefix\", &get_tf_prefix);\n\n      if (!strcmp(get_tf_prefix, \"\"))\n      {\n        sprintf(odom_header_frame_id, \"odom\");\n        sprintf(odom_child_frame_id, \"base_footprint\");\n\n        sprintf(imu_frame_id, \"imu_link\");\n        sprintf(mag_frame_id, \"mag_link\");\n        sprintf(joint_state_header_frame_id, \"base_link\");\n      }\n      else\n      {\n        strcpy(odom_header_frame_id, get_tf_prefix);\n        strcpy(odom_child_frame_id, get_tf_prefix);\n\n        strcpy(imu_frame_id, get_tf_prefix);\n        strcpy(mag_frame_id, get_tf_prefix);\n        strcpy(joint_state_header_frame_id, get_tf_prefix);\n\n        strcat(odom_header_frame_id, \"/odom\");\n        strcat(odom_child_frame_id, \"/base_footprint\");\n\n        strcat(imu_frame_id, \"/imu_link\");\n        strcat(mag_frame_id, \"/mag_link\");\n        strcat(joint_state_header_frame_id, \"/base_link\");\n      }\n\n      sprintf(log_msg, \"Setup TF on Odometry [%s]\", odom_header_frame_id);\n      nh.loginfo(log_msg);\n\n      sprintf(log_msg, \"Setup TF on IMU [%s]\", imu_frame_id);\n      nh.loginfo(log_msg);\n\n      sprintf(log_msg, \"Setup TF on MagneticField [%s]\", mag_frame_id);\n      nh.loginfo(log_msg);\n\n      sprintf(log_msg, \"Setup TF on JointState [%s]\", joint_state_header_frame_id);\n      nh.loginfo(log_msg);\n\n      isChecked = true;\n    }\n  }\n  else\n  {\n    isChecked = false;\n  }\n}\n\n/*******************************************************************************\n* Update the odometry\n*******************************************************************************/\nvoid updateOdometry(void)\n{\n  odom.header.frame_id = odom_header_frame_id;\n  odom.child_frame_id  = odom_child_frame_id;\n\n  odom.pose.pose.position.x = odom_pose[0];\n  odom.pose.pose.position.y = odom_pose[1];\n  odom.pose.pose.position.z = 0;\n  odom.pose.pose.orientation = tf::createQuaternionFromYaw(odom_pose[2]);\n\n  odom.twist.twist.linear.x  = odom_vel[0];\n  odom.twist.twist.angular.z = odom_vel[2];\n}\n\n/*******************************************************************************\n* Update the joint states\n*******************************************************************************/\nvoid updateJointStates(void)\n{\n  static float joint_states_pos[20] = {0.0, };\n  static float joint_states_vel[20] = {0.0, };\n  static float joint_states_eff[20] = {0.0, };\n\n  const double OPEN_MANIPULATOR_GRIPPER_OFFSET = -0.015f;\n\n  double get_joint_position[joint_cnt + gripper_cnt];\n  double get_joint_velocity[joint_cnt + gripper_cnt];\n  double get_joint_current[joint_cnt + gripper_cnt];\n\n  manipulator_driver.syncReadDynamixelInfo();\n  manipulator_driver.getPosition(get_joint_position);\n  manipulator_driver.getVelocity(get_joint_velocity);\n  manipulator_driver.getCurrent(get_joint_current);\n\n  joint_states_pos[LEFT]  = last_rad[LEFT];\n  joint_states_pos[RIGHT] = last_rad[RIGHT];\n\n  joint_states_vel[LEFT]  = last_velocity[LEFT];\n  joint_states_vel[RIGHT] = last_velocity[RIGHT];\n\n  for (uint8_t num = 0; num < (joint_cnt + gripper_cnt); num++)\n  {\n    if (num >= joint_cnt)\n      get_joint_position[num] = get_joint_position[num] * OPEN_MANIPULATOR_GRIPPER_OFFSET;\n\n    joint_states_pos[WHEEL_NUM + num] = get_joint_position[num];\n    joint_states_vel[WHEEL_NUM + num] = get_joint_velocity[num];\n    joint_states_eff[WHEEL_NUM + num] = get_joint_current[num];\n  }\n\n  joint_states.position = joint_states_pos;\n  joint_states.velocity = joint_states_vel;\n  joint_states.effort = joint_states_eff;\n}\n\n/*******************************************************************************\n* CalcUpdateulate the TF\n*******************************************************************************/\nvoid updateTF(geometry_msgs::TransformStamped& odom_tf)\n{\n  odom_tf.header = odom.header;\n  odom_tf.child_frame_id = odom.child_frame_id;\n  odom_tf.transform.translation.x = odom.pose.pose.position.x;\n  odom_tf.transform.translation.y = odom.pose.pose.position.y;\n  odom_tf.transform.translation.z = odom.pose.pose.position.z;\n  odom_tf.transform.rotation      = odom.pose.pose.orientation;\n}\n\n/*******************************************************************************\n* Update motor information\n*******************************************************************************/\nvoid updateMotorInfo(int32_t left_tick, int32_t right_tick)\n{\n  int32_t current_tick = 0;\n  static int32_t last_tick[WHEEL_NUM] = {0, 0};\n\n  if (init_encoder)\n  {\n    for (int index = 0; index < WHEEL_NUM; index++)\n    {\n      last_diff_tick[index] = 0.0;\n      last_tick[index]      = 0;\n      last_rad[index]       = 0.0;\n\n      last_velocity[index]  = 0.0;\n    }\n\n    last_tick[LEFT] = left_tick;\n    last_tick[RIGHT] = right_tick;\n\n    init_encoder = false;\n    return;\n  }\n\n  current_tick = left_tick;\n\n  last_diff_tick[LEFT] = current_tick - last_tick[LEFT];\n  last_tick[LEFT]      = current_tick;\n  last_rad[LEFT]       += TICK2RAD * (double)last_diff_tick[LEFT];\n\n  current_tick = right_tick;\n\n  last_diff_tick[RIGHT] = current_tick - last_tick[RIGHT];\n  last_tick[RIGHT]      = current_tick;\n  last_rad[RIGHT]       += TICK2RAD * (double)last_diff_tick[RIGHT];\n}\n\n/*******************************************************************************\n* Calculate the odometry\n*******************************************************************************/\nbool calcOdometry(double diff_time)\n{\n  float* orientation;\n  double wheel_l, wheel_r;      // rotation value of wheel [rad]\n  double delta_s, theta, delta_theta;\n  static double last_theta = 0.0;\n  double v, w;                  // v = translational velocity [m/s], w = rotational velocity [rad/s]\n  double step_time;\n\n  wheel_l = wheel_r = 0.0;\n  delta_s = delta_theta = theta = 0.0;\n  v = w = 0.0;\n  step_time = 0.0;\n\n  step_time = diff_time;\n\n  if (step_time == 0)\n    return false;\n\n  wheel_l = TICK2RAD * (double)last_diff_tick[LEFT];\n  wheel_r = TICK2RAD * (double)last_diff_tick[RIGHT];\n\n  if (isnan(wheel_l))\n    wheel_l = 0.0;\n\n  if (isnan(wheel_r))\n    wheel_r = 0.0;\n\n  delta_s     = WHEEL_RADIUS * (wheel_r + wheel_l) / 2.0;\n  // theta = WHEEL_RADIUS * (wheel_r - wheel_l) / WHEEL_SEPARATION;\n  orientation = sensors.getOrientation();\n  theta       = atan2f(orientation[1]*orientation[2] + orientation[0]*orientation[3],\n                0.5f - orientation[2]*orientation[2] - orientation[3]*orientation[3]);\n\n  delta_theta = theta - last_theta;\n\n  // compute odometric pose\n  odom_pose[0] += delta_s * cos(odom_pose[2] + (delta_theta / 2.0));\n  odom_pose[1] += delta_s * sin(odom_pose[2] + (delta_theta / 2.0));\n  odom_pose[2] += delta_theta;\n\n  // compute odometric instantaneouse velocity\n\n  v = delta_s / step_time;\n  w = delta_theta / step_time;\n\n  odom_vel[0] = v;\n  odom_vel[1] = 0.0;\n  odom_vel[2] = w;\n\n  last_velocity[LEFT]  = wheel_l / step_time;\n  last_velocity[RIGHT] = wheel_r / step_time;\n  last_theta = theta;\n\n  return true;\n}\n\n/*******************************************************************************\n* Manipulator's joint control\n*******************************************************************************/\nvoid jointControl(void)\n{\n  const uint8_t POINT_SIZE = joint_cnt + 1; // Add time parameter\n  const double JOINT_CONTROL_PERIOD = 1.0f / (double)JOINT_CONTROL_FREQEUNCY;\n  static uint32_t points = 0;\n\n  static uint16_t wait_for_write = 0;\n  static uint16_t loop_cnt = 0;\n\n  if (is_moving == true)\n  {\n    uint32_t all_points_cnt = joint_trajectory_point.data_length;\n    uint8_t write_cnt = 0;\n\n    if (loop_cnt < (wait_for_write))\n    {\n      loop_cnt++;\n      return;\n    }\n    else\n    {\n      double goal_joint_position[joint_cnt];\n      double move_time = 0.0f;\n\n      if (points == 0) move_time = joint_trajectory_point.data[points + POINT_SIZE] - joint_trajectory_point.data[points];\n      else if ((points + POINT_SIZE) >= all_points_cnt) move_time = joint_trajectory_point.data[points] / 2.0f;\n      else  move_time = joint_trajectory_point.data[points] - joint_trajectory_point.data[points - POINT_SIZE];\n\n      for (uint32_t positions = points + 1; positions < (points + POINT_SIZE); positions++)\n      {\n        if ((points + POINT_SIZE) >= all_points_cnt)\n        {\n          goal_joint_position[write_cnt] = joint_trajectory_point.data[positions];\n        }\n        else\n        {\n          double offset = 2.0f * (joint_trajectory_point.data[positions + POINT_SIZE] - joint_trajectory_point.data[positions]);\n          goal_joint_position[write_cnt] = joint_trajectory_point.data[positions] + offset;\n        }\n        write_cnt++;\n      }\n\n      manipulator_driver.writeJointProfileControlParam(move_time * 2.0f);\n      manipulator_driver.writeJointPosition(goal_joint_position);\n\n      wait_for_write = move_time / JOINT_CONTROL_PERIOD;\n      points = points + POINT_SIZE;\n\n      if (points >= all_points_cnt)\n      {\n        points = 0;\n        wait_for_write = 0;\n        is_moving = false;\n      }\n      else\n      {\n        loop_cnt = 0;\n      }\n    }\n  }\n}\n\n/*******************************************************************************\n* Turtlebot3 test drive using push buttons\n*******************************************************************************/\nvoid driveTest(uint8_t buttons)\n{\n  static bool move[2] = {false, false};\n  static int32_t saved_tick[2] = {0, 0};\n  static double diff_encoder = 0.0;\n\n  int32_t current_tick[2] = {0, 0};\n\n  motor_driver.readEncoder(current_tick[LEFT], current_tick[RIGHT]);\n\n  if (buttons & (1<<0))\n  {\n    move[LINEAR] = true;\n    saved_tick[RIGHT] = current_tick[RIGHT];\n\n    diff_encoder = TEST_DISTANCE / (0.207 / 4096); // (Circumference of Wheel) / (The number of tick per revolution)\n  }\n  else if (buttons & (1<<1))\n  {\n    move[ANGULAR] = true;\n    saved_tick[RIGHT] = current_tick[RIGHT];\n\n    diff_encoder = (TEST_RADIAN * TURNING_RADIUS) / (0.207 / 4096);\n  }\n\n  if (move[LINEAR])\n  {\n    if (abs(saved_tick[RIGHT] - current_tick[RIGHT]) <= diff_encoder)\n    {\n      goal_velocity_from_button[LINEAR]  = 0.05;\n    }\n    else\n    {\n      goal_velocity_from_button[LINEAR]  = 0.0;\n      move[LINEAR] = false;\n    }\n  }\n  else if (move[ANGULAR])\n  {\n    if (abs(saved_tick[RIGHT] - current_tick[RIGHT]) <= diff_encoder)\n    {\n      goal_velocity_from_button[ANGULAR]= -0.7;\n    }\n    else\n    {\n      goal_velocity_from_button[ANGULAR]  = 0.0;\n      move[ANGULAR] = false;\n    }\n  }\n}\n\n/*******************************************************************************\n* Update variable (initialization)\n*******************************************************************************/\nvoid updateVariable(bool isConnected)\n{\n  static bool variable_flag = false;\n\n  if (isConnected)\n  {\n    if (variable_flag == false)\n    {\n      sensors.initIMU();\n      initOdom();\n\n      variable_flag = true;\n    }\n  }\n  else\n  {\n    variable_flag = false;\n  }\n}\n\n/*******************************************************************************\n* Wait for Serial Link\n*******************************************************************************/\nvoid waitForSerialLink(bool isConnected)\n{\n  static bool wait_flag = false;\n\n  if (isConnected)\n  {\n    if (wait_flag == false)\n    {\n      delay(10);\n\n      wait_flag = true;\n    }\n  }\n  else\n  {\n    wait_flag = false;\n  }\n}\n\n/*******************************************************************************\n* Update the base time for interpolation\n*******************************************************************************/\nvoid updateTime()\n{\n  current_offset = millis();\n  current_time = nh.now();\n}\n\n/*******************************************************************************\n* ros::Time::now() implementation\n*******************************************************************************/\nros::Time rosNow()\n{\n  return nh.now();\n}\n\n/*******************************************************************************\n* Time Interpolation function (deprecated)\n*******************************************************************************/\nros::Time addMicros(ros::Time & t, uint32_t _micros)\n{\n  uint32_t sec, nsec;\n\n  sec  = _micros / 1000 + t.sec;\n  nsec = _micros % 1000000000 + t.nsec;\n\n  return ros::Time(sec, nsec);\n}\n\n/*******************************************************************************\n* Start Gyro Calibration\n*******************************************************************************/\nvoid updateGyroCali(void)\n{\n  static bool isEnded = false;\n  char log_msg[50];\n\n  if (nh.connected())\n  {\n    if (isEnded == false)\n    {\n      sprintf(log_msg, \"Start Calibration of Gyro\");\n      nh.loginfo(log_msg);\n\n      sensors.calibrationGyro();\n\n      sprintf(log_msg, \"Calibration End\");\n      nh.loginfo(log_msg);\n\n      isEnded = true;\n    }\n  }\n  else\n  {\n    isEnded = false;\n  }\n}\n\n/*******************************************************************************\n* Send log message\n*******************************************************************************/\nvoid sendLogMsg(void)\n{\n  static bool log_flag = false;\n  char log_msg[100];\n\n  String firmware_version = FIRMWARE_VER;\n  String bringup_log      = \"This core(v\" + firmware_version + \") is compatible with TB3 with OpenManipulator\";\n\n  const char* init_log_data = bringup_log.c_str();\n\n  if (nh.connected())\n  {\n    if (log_flag == false)\n    {\n      sprintf(log_msg, \"--------------------------\");\n      nh.loginfo(log_msg);\n\n      sprintf(log_msg, \"Connected to OpenCR board!\");\n      nh.loginfo(log_msg);\n\n//       sprintf(log_msg, init_log_data);\n//       nh.loginfo(log_msg);\n\n      sprintf(log_msg, \"--------------------------\");\n      nh.loginfo(log_msg);\n\n      log_flag = true;\n    }\n  }\n  else\n  {\n    log_flag = false;\n  }\n}\n\n/*******************************************************************************\n* Initialization odometry data\n*******************************************************************************/\nvoid initOdom(void)\n{\n  init_encoder = true;\n\n  for (int index = 0; index < 3; index++)\n  {\n    odom_pose[index] = 0.0;\n    odom_vel[index]  = 0.0;\n  }\n\n  odom.pose.pose.position.x = 0.0;\n  odom.pose.pose.position.y = 0.0;\n  odom.pose.pose.position.z = 0.0;\n\n  odom.pose.pose.orientation.x = 0.0;\n  odom.pose.pose.orientation.y = 0.0;\n  odom.pose.pose.orientation.z = 0.0;\n  odom.pose.pose.orientation.w = 0.0;\n\n  odom.twist.twist.linear.x  = 0.0;\n  odom.twist.twist.angular.z = 0.0;\n}\n\n/*******************************************************************************\n* Initialization joint states data\n*******************************************************************************/\nvoid initJointStates(void)\n{\n  static char *joint_states_name[] = {\"wheel_left_joint\", \"wheel_right_joint\", \"joint1\", \"joint2\", \"joint3\", \"joint4\", \"gripper\"};\n\n  joint_states.header.frame_id = joint_state_header_frame_id;\n  joint_states.name            = joint_states_name;\n\n  joint_states.name_length     = WHEEL_NUM + joint_cnt + gripper_cnt;\n  joint_states.position_length = WHEEL_NUM + joint_cnt + gripper_cnt;\n  joint_states.velocity_length = WHEEL_NUM + joint_cnt + gripper_cnt;\n  joint_states.effort_length   = WHEEL_NUM + joint_cnt + gripper_cnt;\n}\n\n/*******************************************************************************\n* Update Goal Velocity\n*******************************************************************************/\nvoid updateGoalVelocity(bool isConnected)\n{\n    if(!isConnected){\n    goal_velocity_from_cmd[LINEAR] = 0.0;\n    goal_velocity_from_cmd[ANGULAR] = 0.0;\n  }\n  goal_velocity[LINEAR]  = goal_velocity_from_button[LINEAR]  + goal_velocity_from_cmd[LINEAR]  + goal_velocity_from_rc100[LINEAR];\n  goal_velocity[ANGULAR] = goal_velocity_from_button[ANGULAR] + goal_velocity_from_cmd[ANGULAR] + goal_velocity_from_rc100[ANGULAR];\n}\n\n/*******************************************************************************\n* map (return double)\n*******************************************************************************/\ndouble mapd(double x, double in_min, double in_max, double out_min, double out_max)\n{\n  return (x - in_min) * (out_max - out_min) / (in_max - in_min) + out_min;\n}\n\n/*******************************************************************************\n* Send Debug data\n*******************************************************************************/\nvoid sendDebuglog(void)\n{\n  DEBUG_SERIAL.println(\"---------------------------------------\");\n  DEBUG_SERIAL.println(\"EXTERNAL SENSORS\");\n  DEBUG_SERIAL.println(\"---------------------------------------\");\n  DEBUG_SERIAL.print(\"Bumper : \"); DEBUG_SERIAL.println(sensors.checkPushBumper());\n  DEBUG_SERIAL.print(\"Cliff : \"); DEBUG_SERIAL.println(sensors.getIRsensorData());\n  DEBUG_SERIAL.print(\"Sonar : \"); DEBUG_SERIAL.println(sensors.getSonarData());\n  DEBUG_SERIAL.print(\"Illumination : \"); DEBUG_SERIAL.println(sensors.getIlluminationData());\n\n  DEBUG_SERIAL.println(\"---------------------------------------\");\n  DEBUG_SERIAL.println(\"OpenCR SENSORS\");\n  DEBUG_SERIAL.println(\"---------------------------------------\");\n  DEBUG_SERIAL.print(\"Battery : \"); DEBUG_SERIAL.println(sensors.checkVoltage());\n  DEBUG_SERIAL.println(\"Button : \" + String(sensors.checkPushButton()));\n\n  float* quat = sensors.getOrientation();\n\n  DEBUG_SERIAL.println(\"IMU : \");\n  DEBUG_SERIAL.print(\"    w : \"); DEBUG_SERIAL.println(quat[0]);\n  DEBUG_SERIAL.print(\"    x : \"); DEBUG_SERIAL.println(quat[1]);\n  DEBUG_SERIAL.print(\"    y : \"); DEBUG_SERIAL.println(quat[2]);\n  DEBUG_SERIAL.print(\"    z : \"); DEBUG_SERIAL.println(quat[3]);\n\n  DEBUG_SERIAL.println(\"---------------------------------------\");\n  DEBUG_SERIAL.println(\"DYNAMIXELS\");\n  DEBUG_SERIAL.println(\"---------------------------------------\");\n  DEBUG_SERIAL.println(\"Torque(wheel) : \" + String(motor_driver.getTorque()));\n  DEBUG_SERIAL.println(\"Torque(joint) : \" + String(manipulator_driver.getTorqueState()));\n\n  int32_t encoder[WHEEL_NUM] = {0, 0};\n  motor_driver.readEncoder(encoder[LEFT], encoder[RIGHT]);\n\n  DEBUG_SERIAL.println(\"Encoder(left) : \" + String(encoder[LEFT]));\n  DEBUG_SERIAL.println(\"Encoder(right) : \" + String(encoder[RIGHT]));\n\n  double present_position[joint_cnt + gripper_cnt];\n  manipulator_driver.getPosition(present_position);\n\n  for (uint8_t num = 0; num < joint_cnt + gripper_cnt; num++)\n  {\n    DEBUG_SERIAL.print(\"Present Position(Joint_\");\n    DEBUG_SERIAL.print(num);\n    DEBUG_SERIAL.print(\") : \");\n    DEBUG_SERIAL.println(present_position[num]);\n  }\n\n  DEBUG_SERIAL.println(\"---------------------------------------\");\n  DEBUG_SERIAL.println(\"TurtleBot3\");\n  DEBUG_SERIAL.println(\"---------------------------------------\");\n  DEBUG_SERIAL.println(\"Odometry : \");\n  DEBUG_SERIAL.print(\"         x : \"); DEBUG_SERIAL.println(odom_pose[0]);\n  DEBUG_SERIAL.print(\"         y : \"); DEBUG_SERIAL.println(odom_pose[1]);\n  DEBUG_SERIAL.print(\"     theta : \"); DEBUG_SERIAL.println(odom_pose[2]);\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/examples/turtlebot3_with_open_manipulator/turtlebot3_with_open_manipulator_core/turtlebot3_with_open_manipulator_core_config.h",
    "content": "/*******************************************************************************\n* Copyright 2018 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#ifndef TURTLEBOT3_WITH_OPEN_MANIPULATOR_CORE_CONFIG_H_\n#define TURTLEBOT3_WITH_OPEN_MANIPULATOR_CORE_CONFIG_H_\n// #define NOETIC_SUPPORT          //uncomment this if writing code for ROS1 Noetic\n\n#include <ros.h>\n#include <ros/time.h>\n#include <std_msgs/Bool.h>\n#include <std_msgs/Empty.h>\n#include <std_msgs/Int32.h>\n#include <std_msgs/Float64.h>\n#include <std_msgs/Float64MultiArray.h>\n#include <sensor_msgs/JointState.h>\n#include <geometry_msgs/Vector3.h>\n#include <geometry_msgs/Twist.h>\n#include <tf/tf.h>\n#include <tf/transform_broadcaster.h>\n#include <nav_msgs/Odometry.h>\n\n#include <turtlebot3_msgs/SensorState.h>\n#include <turtlebot3_msgs/Sound.h>\n#include <turtlebot3_msgs/VersionInfo.h>\n\n#include <TurtleBot3.h>\n#include \"turtlebot3_with_open_manipulator.h\"\n\n#include <math.h>\n\n#define FIRMWARE_VER \"2.0.2\"\n\n#define CONTROL_MOTOR_SPEED_FREQUENCY          30   //hz\n#define IMU_PUBLISH_FREQUENCY                  200  //hz\n#define CMD_VEL_PUBLISH_FREQUENCY              30   //hz\n#define DRIVE_INFORMATION_PUBLISH_FREQUENCY    30   //hz\n#define VERSION_INFORMATION_PUBLISH_FREQUENCY  1    //hz \n#define DEBUG_LOG_FREQUENCY                    10   //hz \n#define JOINT_CONTROL_FREQEUNCY                100  //hz \n\n#define WHEEL_NUM                        2\n\n#define LEFT                             0\n#define RIGHT                            1\n\n#define LINEAR                           0\n#define ANGULAR                          1\n\n#define DEG2RAD(x)                       (x * 0.01745329252)  // *PI/180\n#define RAD2DEG(x)                       (x * 57.2957795131)  // *180/PI\n\n#define TICK2RAD                         0.001533981  // 0.087890625[deg] * 3.14159265359 / 180 = 0.001533981f\n\n#define TEST_DISTANCE                    0.300     // meter\n#define TEST_RADIAN                      3.14      // 180 degree\n\n// #define DEBUG                            \n#define DEBUG_SERIAL                     SerialBT2\n\n// Callback function prototypes\nvoid commandVelocityCallback(const geometry_msgs::Twist& cmd_vel_msg);\nvoid jointTrajectoryPointCallback(const std_msgs::Float64MultiArray& joint_trajectory_point_msg);\nvoid jointMoveTimeCallback(const std_msgs::Float64& time_msg);\nvoid gripperPositionCallback(const std_msgs::Float64MultiArray& pos_msg);\nvoid gripperMoveTimeCallback(const std_msgs::Float64& time_msg);\nvoid soundCallback(const turtlebot3_msgs::Sound& sound_msg);\nvoid motorPowerCallback(const std_msgs::Bool& power_msg);\nvoid resetCallback(const std_msgs::Empty& reset_msg);\n\n// Function prototypes\nvoid publishCmdVelFromRC100Msg(void);\nvoid publishImuMsg(void);\nvoid publishMagMsg(void);\nvoid publishSensorStateMsg(void);\nvoid publishVersionInfoMsg(void);\nvoid publishBatteryStateMsg(void);\nvoid publishDriveInformation(void);\n\nros::Time rosNow(void);\nros::Time addMicros(ros::Time & t, uint32_t _micros); // deprecated\n\nvoid updateVariable(bool isConnected);\nvoid updateMotorInfo(int32_t left_tick, int32_t right_tick);\nvoid updateTime(void);\nvoid updateOdometry(void);\nvoid updateJoint(void);\nvoid updateTF(geometry_msgs::TransformStamped& odom_tf);\nvoid updateGyroCali(bool isConnected);\nvoid updateGoalVelocity(void);\nvoid updateTFPrefix(bool isConnected);\n\nvoid initOdom(void);\nvoid initJointStates(void);\n\nbool calcOdometry(double diff_time);\n\nvoid jointControl(void);\n\nvoid sendLogMsg(void);\nvoid waitForSerialLink(bool isConnected);\n\ndouble mapd(double x, double in_min, double in_max, double out_min, double out_max);\n\n/*******************************************************************************\n* ROS NodeHandle\n*******************************************************************************/\nros::NodeHandle nh;\nros::Time current_time;\nuint32_t current_offset;\n\n/*******************************************************************************\n* ROS Parameter\n*******************************************************************************/\nchar get_prefix[100];\nchar* get_tf_prefix = get_prefix;\n\nchar odom_header_frame_id[30];\nchar odom_child_frame_id[30];\n\nchar imu_frame_id[30];\nchar mag_frame_id[30];\n\nchar joint_state_header_frame_id[30];\n\n/*******************************************************************************\n* Subscriber\n*******************************************************************************/\nros::Subscriber<geometry_msgs::Twist> cmd_vel_sub(\"cmd_vel\", commandVelocityCallback);\n\nros::Subscriber<std_msgs::Float64MultiArray> joint_position_sub(\"joint_trajectory_point\", jointTrajectoryPointCallback);\n\nros::Subscriber<std_msgs::Float64> joint_move_time_sub(\"joint_move_time\", jointMoveTimeCallback);\n\nros::Subscriber<std_msgs::Float64MultiArray> gripper_position_sub(\"gripper_position\", gripperPositionCallback);\n\nros::Subscriber<std_msgs::Float64> gripper_move_time_sub(\"gripper_move_time\", gripperMoveTimeCallback);\n\nros::Subscriber<turtlebot3_msgs::Sound> sound_sub(\"sound\", soundCallback);\n\nros::Subscriber<std_msgs::Bool> motor_power_sub(\"motor_power\", motorPowerCallback);\n\nros::Subscriber<std_msgs::Empty> reset_sub(\"reset\", resetCallback);\n\n/*******************************************************************************\n* Publisher\n*******************************************************************************/\n// Bumpers, cliffs, buttons, encoders, battery of Turtlebot3\nturtlebot3_msgs::SensorState sensor_state_msg;\nros::Publisher sensor_state_pub(\"sensor_state\", &sensor_state_msg);\n\n// Version information of Turtlebot3\nturtlebot3_msgs::VersionInfo version_info_msg;\nros::Publisher version_info_pub(\"firmware_version\", &version_info_msg);\n\n// IMU of Turtlebot3\nsensor_msgs::Imu imu_msg;\nros::Publisher imu_pub(\"imu\", &imu_msg);\n\n// Command velocity of Turtlebot3 using RC100 remote controller\ngeometry_msgs::Twist cmd_vel_rc100_msg;\nros::Publisher cmd_vel_rc100_pub(\"cmd_vel_rc100\", &cmd_vel_rc100_msg);\n\n// Odometry of Turtlebot3\nnav_msgs::Odometry odom;\nros::Publisher odom_pub(\"odom\", &odom);\n\n// Joint(Dynamixel) state of Turtlebot3\nsensor_msgs::JointState joint_states;\nros::Publisher joint_states_pub(\"joint_states\", &joint_states);\n\n// Battey state of Turtlebot3\n#if defined NOETIC_SUPPORT\nsensor_msgs::BatteryStateNoetic battery_state_msg;\n#else\nsensor_msgs::BatteryState battery_state_msg;\n#endif\nros::Publisher battery_state_pub(\"battery_state\", &battery_state_msg);\n\n// Magnetic field\nsensor_msgs::MagneticField mag_msg;\nros::Publisher mag_pub(\"magnetic_field\", &mag_msg);\n\n/*******************************************************************************\n* Transform Broadcaster\n*******************************************************************************/\n// TF of Turtlebot3\ngeometry_msgs::TransformStamped odom_tf;\ntf::TransformBroadcaster tf_broadcaster;\n\n/*******************************************************************************\n* SoftwareTimer of Turtlebot3\n*******************************************************************************/\nstatic uint32_t tTime[10];\n\n/*******************************************************************************\n* Declaration for motor\n*******************************************************************************/\nTurtlebot3MotorDriver motor_driver;\nOpenManipulatorDriver manipulator_driver;\n\nuint8_t joint_id[JOINT_CNT] = {JOINT_ID_1, JOINT_ID_2, JOINT_ID_3, JOINT_ID_4};\nuint8_t joint_cnt = JOINT_CNT;\n\nuint8_t gripper_id[GRIPPER_CNT] = {GRIPPER_ID_1};\nuint8_t gripper_cnt = GRIPPER_CNT;\n\n/*******************************************************************************\n* Calculation for odometry\n*******************************************************************************/\nbool init_encoder = true;\nint32_t last_diff_tick[WHEEL_NUM] = {0, 0};\ndouble  last_rad[WHEEL_NUM]       = {0.0, 0.0};\n\n/*******************************************************************************\n* Update Joint State\n*******************************************************************************/\ndouble  last_velocity[WHEEL_NUM]  = {0.0, 0.0};\n\n/*******************************************************************************\n* Declaration for sensors\n*******************************************************************************/\nTurtlebot3Sensor sensors;\n\n/*******************************************************************************\n* Declaration for controllers\n*******************************************************************************/\nTurtlebot3Controller controllers;\nfloat goal_velocity[WHEEL_NUM] = {0.0, 0.0};\nfloat goal_velocity_from_button[WHEEL_NUM] = {0.0, 0.0};\nfloat goal_velocity_from_cmd[WHEEL_NUM] = {0.0, 0.0};\nfloat goal_velocity_from_rc100[WHEEL_NUM] = {0.0, 0.0};\n\n/*******************************************************************************\n* Declaration for diagnosis\n*******************************************************************************/\nTurtlebot3Diagnosis diagnosis;\n\n/*******************************************************************************\n* Declaration for SLAM and navigation\n*******************************************************************************/\nunsigned long prev_update_time;\nfloat odom_pose[3];\ndouble odom_vel[3];\n\n/*******************************************************************************\n* Declaration for Battery\n*******************************************************************************/\nbool setup_end        = false;\nuint8_t battery_state = 0;\n\n/*******************************************************************************\n* Joint Control\n*******************************************************************************/\nbool is_moving        = false;\nstd_msgs::Float64MultiArray joint_trajectory_point;\n\n#endif // TURTLEBOT3_WITH_OPEN_MANIPULATOR_CONFIG_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/include/turtlebot3/turtlebot3.h",
    "content": "#include \"turtlebot3_motor_driver.h\"\n#include \"turtlebot3_sensor.h\"\n#include \"turtlebot3_controller.h\"\n#include \"turtlebot3_diagnosis.h\"\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/include/turtlebot3/turtlebot3_controller.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#ifndef TURTLEBOT3_CONTROLLER_H_\n#define TURTLEBOT3_CONTROLLER_H_\n\n#include <RC100.h>\n\n#include <geometry_msgs/Twist.h>\n\n#define CONST_VEL 0.2\n\n#define VELOCITY_LINEAR_X                0.01   // m/s\n#define VELOCITY_ANGULAR_Z               0.1    // rad/s\n\n#define DEBUG_SERIAL SerialBT2\n\nnamespace Internal {\n  static uint16_t dummy_raw_data_;\n}\n\nclass Turtlebot3Controller\n{\n public:\n  Turtlebot3Controller();\n  ~Turtlebot3Controller();\n\n  bool init(float max_lin_vel, float max_ang_vel, uint8_t scale_lin_vel = 1, uint8_t scale_ang_vel = 1);\n\n  bool getRCdata(float *get_cmd_vel, uint16_t &raw_data = Internal::dummy_raw_data_);\n\n private:\n  geometry_msgs::Twist cmd_vel_;\n  RC100 rc100_;\n\n  double const_cmd_vel_;\n\n  float max_lin_vel_;\n  float min_lin_vel_;\n  float max_ang_vel_;\n  float min_ang_vel_;\n  uint8_t scale_lin_vel_;\n  uint8_t scale_ang_vel_;\n};\n\n#endif // TURTLEBOT3_CONTROLLER_H_"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/include/turtlebot3/turtlebot3_diagnosis.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#ifndef TURTLEBOT3_DIAGNOSIS_H_\n#define TURTLEBOT3_DIAGNOSIS_H_\n\n#include <Arduino.h>\n\n#define LED_TXD                          0\n#define LED_RXD                          1\n#define LED_LOW_BATTERY                  2\n#define LED_ROS_CONNECT                  3\n#define LED_WORKING_CHECK                13\n\n#define BATTERY_POWER_OFF                0\n#define BATTERY_POWER_STARTUP            1\n#define BATTERY_POWER_NORMAL             2\n#define BATTERY_POWER_CHECK              3\n#define BATTERY_POWER_WARNNING           4\n\n#define WAIT_FOR_BUTTON_PRESS            0\n#define WAIT_SECOND                      1\n#define CHECK_BUTTON_RELEASED            2\n\n#define DEBUG_SERIAL  SerialBT2\n\nclass Turtlebot3Diagnosis\n{\n public:\n  Turtlebot3Diagnosis();\n  ~Turtlebot3Diagnosis();\n\n  bool init();\n\n  void showLedStatus(bool isConnected);\n  void updateRxTxLed(void);\n\n  void setPowerOn(void);\n  void setPowerOff(void);\n\n  uint8_t updateVoltageCheck(bool check_setup);\n\n  uint8_t getButtonPress(uint16_t time_to_press);  \n\n private:\n\n};\n\n#endif // TURTLEBOT3_DIAGNOSIS_H_"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/include/turtlebot3/turtlebot3_motor_driver.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#ifndef TURTLEBOT3_MOTOR_DRIVER_H_\n#define TURTLEBOT3_MOTOR_DRIVER_H_\n\n#include \"variant.h\"\n#include <DynamixelSDK.h>\n\n// Control table address (Dynamixel X-series)\n#define ADDR_X_TORQUE_ENABLE            64\n#define ADDR_X_GOAL_VELOCITY            104\n#define ADDR_X_GOAL_POSITION            116\n#define ADDR_X_REALTIME_TICK            120\n#define ADDR_X_PRESENT_VELOCITY         128\n#define ADDR_X_PRESENT_POSITION         132\n\n// Limit values (XM430-W210-T and XM430-W350-T)\n#define BURGER_DXL_LIMIT_MAX_VELOCITY            265     // MAX RPM is 61 when XL is powered 12.0V\n#define WAFFLE_DXL_LIMIT_MAX_VELOCITY            330     // MAX RPM is 77 when XM is powered 12.0V\n\n// Data Byte Length\n#define LEN_X_TORQUE_ENABLE             1\n#define LEN_X_GOAL_VELOCITY             4\n#define LEN_X_GOAL_POSITION             4\n#define LEN_X_REALTIME_TICK             2\n#define LEN_X_PRESENT_VELOCITY          4\n#define LEN_X_PRESENT_POSITION          4\n\n#define PROTOCOL_VERSION                2.0     // Dynamixel protocol version 2.0\n\n#define DXL_LEFT_ID                     1       // ID of left motor\n#define DXL_RIGHT_ID                    2       // ID of right motor\n\n#define BAUDRATE                        1000000 // baurd rate of Dynamixel\n#define DEVICENAME                      \"\"      // no need setting on OpenCR\n\n#define TORQUE_ENABLE                   1       // Value for enabling the torque\n#define TORQUE_DISABLE                  0       // Value for disabling the torque\n\n#define LEFT                            0\n#define RIGHT                           1\n\n#define LINEAR                          0\n#define ANGULAR                         1\n\n#define VELOCITY_CONSTANT_VALUE         41.69988758  // V = r * w = r     *        (RPM             * 0.10472)\n                                                     //           = r     * (0.229 * Goal_Velocity) * 0.10472\n                                                     //\n                                                     // Goal_Velocity = V / r * 41.69988757710309\n\n#define DEBUG_SERIAL  SerialBT2\n\nclass Turtlebot3MotorDriver\n{\n public:\n  Turtlebot3MotorDriver();\n  ~Turtlebot3MotorDriver();\n  bool init(String turtlebot3);\n  void close(void);\n  bool setTorque(bool onoff);\n  bool getTorque();\n  bool readEncoder(int32_t &left_value, int32_t &right_value);\n  bool writeVelocity(int64_t left_value, int64_t right_value);\n  bool controlMotor(const float wheel_radius, const float wheel_separation, float* value);\n\n private:\n  uint32_t baudrate_;\n  float  protocol_version_;\n  uint8_t left_wheel_id_;\n  uint8_t right_wheel_id_;\n  bool torque_;\n\n  uint16_t dynamixel_limit_max_velocity_;\n\n  dynamixel::PortHandler *portHandler_;\n  dynamixel::PacketHandler *packetHandler_;\n\n  dynamixel::GroupSyncWrite *groupSyncWriteVelocity_;\n  dynamixel::GroupSyncRead *groupSyncReadEncoder_;\n};\n\n#endif // TURTLEBOT3_MOTOR_DRIVER_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/include/turtlebot3/turtlebot3_sensor.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho, Gilbert */\n\n#ifndef TURTLEBOT3_SENSOR_H_\n#define TURTLEBOT3_SENSOR_H_\n\n#include <IMU.h>\n\n#include <sensor_msgs/Imu.h>\n#include <sensor_msgs/MagneticField.h>\n\n#if defined NOETIC_SUPPORT\n  #include <sensor_msgs/BatteryStateNoetic.h>\n#else\n  #include <sensor_msgs/BatteryState.h>\n#endif\n\n#include \"OLLO.h\"\n\n#define ACCEL_FACTOR                      0.000598550415   // (ADC_Value / Scale) * 9.80665            => Range : +- 2[g]\n                                                           //                                             Scale : +- 16384\n#define GYRO_FACTOR                       0.0010642        // (ADC_Value/Scale) * (pi/180)             => Range : +- 2000[deg/s]\n                                                           //                                             Scale : +- 16.4[deg/s]\n\n#define MAG_FACTOR                        15e-8\n\n#define DEBUG_SERIAL  SerialBT2\n\ntypedef struct LED_PIN_ARRAY\n{\n  int front_left;\n  int front_right;\n  int back_left;\n  int back_right;\n}LedPinArray;\n \ntypedef struct SONAR_PIN\n{\n  int trig;\n  int echo;\n}SonarPin;\n\nclass Turtlebot3Sensor\n{\n public:\n  Turtlebot3Sensor();\n  ~Turtlebot3Sensor();\n\n  bool init(void);\n\n  // IMU\n  void initIMU(void);\n  sensor_msgs::Imu getIMU(void);\n  void updateIMU(void);\n  void calibrationGyro(void);\n\n  float* getOrientation(void);\n  sensor_msgs::MagneticField getMag(void);\n\n  // Battery\n  float checkVoltage(void);\n\n  // Button\n  uint8_t checkPushButton(void);\n\n  // Sound\n  void melody(uint16_t* note, uint8_t note_num, uint8_t* durations);\n  void makeSound(uint8_t index);  \n\n  // Bumper\n  void initBumper(void);\n  uint8_t checkPushBumper(void);\n\n  // Cliff sensor\n  void initIR(void);\n  float getIRsensorData(void);\n\n  // Sonar sensor\n  void initSonar(void);\n  void updateSonar(uint32_t t);\n  float getSonarData(void);\n\n  // Illumination sensor\n  float getIlluminationData(void);\n\n  // led pattern\n  void initLED(void);\n  void setLedPattern(double linear_vel, double angular_vel);\n private:\n  sensor_msgs::Imu           imu_msg_;\n  #if defined NOETIC_SUPPORT\n    sensor_msgs::BatteryStateNoetic  battery_state_msg_;\n  #else\n    sensor_msgs::BatteryState  battery_state_msg_;\n  #endif\n  sensor_msgs::MagneticField mag_msg_;\n\n  cIMU imu_;\n  OLLO ollo_;\n\n  LedPinArray led_pin_array_;\n  SonarPin sonar_pin_;\n\n  float sonar_data_;\n};\n\n#endif // TURTLEBOT3_SENSOR_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/library.properties",
    "content": "name=TurtleBot3\nversion=0.1.0\nauthor=Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho\nmaintainer=Will Son(willson@robotis.com)\nsentence=library for TurtleBot3\nparagraph=\ncategory=Data Processing\nurl=https://github.com/ROBOTIS-GIT/turtlebot3\narchitectures=OpenCR\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/src/TurtleBot3.h",
    "content": "#include \"../include/turtlebot3/turtlebot3.h\""
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/src/turtlebot3/turtlebot3_controller.cpp",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#include \"../../include/turtlebot3/turtlebot3_controller.h\"\n\nTurtlebot3Controller::Turtlebot3Controller()\n{\n  const_cmd_vel_ = CONST_VEL;\n}\n\nTurtlebot3Controller::~Turtlebot3Controller()\n{\n  DEBUG_SERIAL.end();\n}\n\nbool Turtlebot3Controller::init(float max_lin_vel, float max_ang_vel, uint8_t scale_lin_vel, uint8_t scale_ang_vel)\n{\n  DEBUG_SERIAL.begin(57600);\n  // 57600bps baudrate for RC100 control\n  rc100_.begin(1);  \n\n  max_lin_vel_ = max_lin_vel;\n  min_lin_vel_ = (-1)*max_lin_vel;\n  max_ang_vel_ = max_ang_vel;\n  min_ang_vel_ = (-1)*max_ang_vel;\n  scale_lin_vel_ = scale_lin_vel;\n  scale_ang_vel_ = scale_ang_vel;\n\n  DEBUG_SERIAL.println(\"Success to init Controller\");\n  return true;\n}\n\nbool Turtlebot3Controller::getRCdata(float *get_cmd_vel, uint16_t &raw_data)\n{\n  uint16_t received_data = 0;\n  bool clicked_state = false;\n\n  static float lin_x = 0.0, ang_z = 0.0;\n  \n  if (rc100_.available())\n  {\n    received_data = rc100_.readData();\n    if (&raw_data != &Internal::dummy_raw_data_)\n      raw_data = received_data;\n\n    if (received_data & RC100_BTN_U)\n    {\n      lin_x += VELOCITY_LINEAR_X * scale_lin_vel_;\n      clicked_state = true;\n    }\n    else if (received_data & RC100_BTN_D)\n    {\n      lin_x -= VELOCITY_LINEAR_X * scale_lin_vel_;\n      clicked_state = true;\n    }\n    else if (received_data & RC100_BTN_L)\n    {\n      ang_z += VELOCITY_ANGULAR_Z * scale_ang_vel_;\n      clicked_state = true;\n    }\n    else if (received_data & RC100_BTN_R)\n    {\n      ang_z -= VELOCITY_ANGULAR_Z * scale_ang_vel_;\n      clicked_state = true;\n    }\n    else if (received_data & RC100_BTN_6)\n    {\n      lin_x = const_cmd_vel_;\n      ang_z = 0.0;\n      clicked_state = true;\n    }\n    else if (received_data & RC100_BTN_5)\n    {\n      lin_x = 0.0;\n      ang_z = 0.0;\n      clicked_state = true;\n    }\n    else\n    {\n      lin_x = lin_x;\n      ang_z = ang_z;\n    }\n\n    lin_x = constrain(lin_x, min_lin_vel_, max_lin_vel_);\n    ang_z = constrain(ang_z, min_ang_vel_, max_ang_vel_);\n\n    get_cmd_vel[0] = lin_x;\n    get_cmd_vel[1] = ang_z;\n  }\n\n  return clicked_state;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/src/turtlebot3/turtlebot3_diagnosis.cpp",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#include \"../../include/turtlebot3/turtlebot3_diagnosis.h\"\n\nTurtlebot3Diagnosis::Turtlebot3Diagnosis()\n{\n}\n\nTurtlebot3Diagnosis::~Turtlebot3Diagnosis()\n{\n  DEBUG_SERIAL.end();  \n}\n\nbool Turtlebot3Diagnosis::init(void)\n{\n  DEBUG_SERIAL.begin(57600);\n\n  DEBUG_SERIAL.println(\"Success to init Diagnosis\");\n  return true;\n}\n\nvoid Turtlebot3Diagnosis::showLedStatus(bool isConnected)\n{\n  static uint32_t t_time = millis();\n\n  if ((millis()-t_time) >= 500)\n  {\n    t_time = millis();\n    digitalWrite(LED_WORKING_CHECK, !digitalRead(LED_WORKING_CHECK));\n  }\n\n  if (getPowerInVoltage() < 11.1)\n  {\n    setLedOn(LED_LOW_BATTERY);\n  }\n  else\n  {\n    setLedOff(LED_LOW_BATTERY);\n  }\n\n  if (isConnected)\n  {\n    setLedOn(LED_ROS_CONNECT);\n  }\n  else\n  {\n    setLedOff(LED_ROS_CONNECT);\n  }\n\n  updateRxTxLed();\n}\n\nvoid Turtlebot3Diagnosis::updateRxTxLed(void)\n{\n  static uint32_t rx_led_update_time;\n  static uint32_t tx_led_update_time;\n  static uint32_t rx_cnt;\n  static uint32_t tx_cnt;\n\n  if ((millis()-tx_led_update_time) > 50)\n  {\n    tx_led_update_time = millis();\n\n    if (tx_cnt != Serial.getTxCnt())\n    {\n      setLedToggle(LED_TXD);\n    }\n    else\n    {\n      setLedOff(LED_TXD);\n    }\n\n    tx_cnt = Serial.getTxCnt();\n  }\n\n  if ((millis()-rx_led_update_time) > 50)\n  {\n    rx_led_update_time = millis();\n\n    if (rx_cnt != Serial.getRxCnt())\n    {\n      setLedToggle(LED_RXD);\n    }\n    else\n    {\n      setLedOff(LED_RXD);\n    }\n\n    rx_cnt = Serial.getRxCnt();\n  }\n}\n\nvoid Turtlebot3Diagnosis::setPowerOn(void)\n{\n  digitalWrite(BDPIN_DXL_PWR_EN, HIGH);\n}\n\nvoid Turtlebot3Diagnosis::setPowerOff(void)\n{\n  digitalWrite(BDPIN_DXL_PWR_EN, LOW);\n}\n\nuint8_t Turtlebot3Diagnosis::updateVoltageCheck(bool check_setup)\n{  \n  static uint8_t battery_voltage     = 0;\n  static float   battery_valtage_raw = 0;\n  static uint8_t battery_state       = BATTERY_POWER_OFF;\n\n  static bool startup = false;\n  static int vol_index = 0;\n  static int prev_state = 0;\n  static int alram_state = 0;\n  static int check_index = 0;\n\n  int i;\n  float vol_sum;\n  float vol_value;\n\n  static uint32_t process_time[8] = {0,};\n  static float    vol_value_tbl[10] = {0,};\n\n  float voltage_ref       = 11.0 + 0.0;\n  float voltage_ref_warn  = 11.0 + 0.0;\n\n\n  if (startup == false)\n  {\n    startup = true;\n    for (i=0; i<8; i++)\n    {\n      process_time[i] = millis();\n    }\n  }\n\n  if (millis()-process_time[0] > 100)\n  {\n    process_time[0] = millis();\n\n    vol_value_tbl[vol_index] = getPowerInVoltage();\n\n    vol_index++;\n    vol_index %= 10;\n\n    vol_sum = 0;\n    for(i=0; i<10; i++)\n    {\n      vol_sum += vol_value_tbl[i];\n    }\n    vol_value = vol_sum/10;\n    battery_valtage_raw = vol_value;\n\n    //Serial.println(vol_value);\n\n    battery_voltage = vol_value;\n  }\n  (void)(battery_voltage);\n\n\n  if(millis()-process_time[1] > 1000)\n  {\n    process_time[1] = millis();\n\n    //Serial.println(battery_state);\n\n    switch(battery_state)\n    {\n      case BATTERY_POWER_OFF:\n        if (check_setup == true)\n        {\n          alram_state = 0;\n          if(battery_valtage_raw > 5.0)\n          {\n            check_index    = 0;\n            prev_state     = battery_state;\n            battery_state = BATTERY_POWER_STARTUP;\n          }\n          else\n          {\n            noTone(BDPIN_BUZZER);\n          }\n        }\n        break;\n\n      case BATTERY_POWER_STARTUP:\n        if(battery_valtage_raw > voltage_ref)\n        {\n          check_index   = 0;\n          prev_state    = battery_state;\n          battery_state = BATTERY_POWER_NORMAL;\n          setPowerOn();\n        }\n\n        if(check_index < 5)\n        {\n          check_index++;\n        }\n        else\n        {\n          if (battery_valtage_raw > 5.0)\n          {\n            prev_state    = battery_state;\n            battery_state = BATTERY_POWER_CHECK;\n          }\n          else\n          {\n            prev_state    = battery_state;\n            battery_state = BATTERY_POWER_OFF;\n          }\n        }\n        break;\n\n      case BATTERY_POWER_NORMAL:\n        alram_state = 0;\n        if(battery_valtage_raw < voltage_ref)\n        {\n          prev_state    = battery_state;\n          battery_state = BATTERY_POWER_CHECK;\n          check_index   = 0;\n        }\n        break;\n\n      case BATTERY_POWER_CHECK:\n        if(check_index < 5)\n        {\n          check_index++;\n        }\n        else\n        {\n          if(battery_valtage_raw < voltage_ref_warn)\n          {\n            setPowerOff();\n            prev_state    = battery_state;\n            battery_state = BATTERY_POWER_WARNNING;\n          }\n        }\n        if(battery_valtage_raw >= voltage_ref)\n        {\n          setPowerOn();\n          prev_state    = battery_state;\n          battery_state = BATTERY_POWER_NORMAL;\n        }\n        break;\n\n      case BATTERY_POWER_WARNNING:\n        alram_state ^= 1;\n        if(alram_state)\n        {\n          tone(BDPIN_BUZZER, 1000, 500);\n        }\n\n        if(battery_valtage_raw > voltage_ref)\n        {\n          setPowerOn();\n          prev_state    = battery_state;\n          battery_state = BATTERY_POWER_NORMAL;\n        }\n        else\n        {\n          setPowerOff();\n        }\n\n        if(battery_valtage_raw < 5.0)\n        {\n          setPowerOff();\n          prev_state    = battery_state;\n          battery_state = BATTERY_POWER_OFF;\n        }\n        break;\n\n      default:\n        break;\n    }\n  }\n\n  (void)(prev_state);\n\n  return battery_state;\n}\n\nuint8_t Turtlebot3Diagnosis::getButtonPress(uint16_t time_to_press)\n{\n  uint8_t button_state = 0;\n  static uint32_t t_time[2];\n  static uint8_t button_state_num[2] = {0, };\n\n  for (int button_num = 0; button_num < 2; button_num++)\n  {\n    switch (button_state_num[button_num])\n    {\n     case WAIT_FOR_BUTTON_PRESS:\n       if (getPushButton() & (1 << button_num))\n       {\n         t_time[button_num] = millis();\n         button_state_num[button_num] = WAIT_SECOND;\n       }\n       break;\n\n     case WAIT_SECOND:\n       if ((millis()-t_time[button_num]) >= time_to_press)\n       {\n         if (getPushButton() & (1 << button_num))\n         {\n           button_state_num[button_num] = CHECK_BUTTON_RELEASED;\n           button_state |= (1 << button_num);\n         }\n         else\n         {\n           button_state_num[button_num] = WAIT_FOR_BUTTON_PRESS;\n         }\n       }\n       break;\n\n     case CHECK_BUTTON_RELEASED:\n       if (!(getPushButton() & (1 << button_num)))\n         button_state_num[button_num] = WAIT_FOR_BUTTON_PRESS;\n       break;\n\n     default :\n       button_state_num[button_num] = WAIT_FOR_BUTTON_PRESS;\n       break;\n    }\n  }\n\n  return button_state;\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/src/turtlebot3/turtlebot3_motor_driver.cpp",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho */\n\n#include \"../../include/turtlebot3/turtlebot3_motor_driver.h\"\n\nTurtlebot3MotorDriver::Turtlebot3MotorDriver()\n: baudrate_(BAUDRATE),\n  protocol_version_(PROTOCOL_VERSION),\n  left_wheel_id_(DXL_LEFT_ID),\n  right_wheel_id_(DXL_RIGHT_ID)\n{\n  torque_ = false;\n  dynamixel_limit_max_velocity_ = BURGER_DXL_LIMIT_MAX_VELOCITY;\n}\n\nTurtlebot3MotorDriver::~Turtlebot3MotorDriver()\n{\n  close();\n}\n\nbool Turtlebot3MotorDriver::init(String turtlebot3)\n{\n  DEBUG_SERIAL.begin(57600);\n  portHandler_   = dynamixel::PortHandler::getPortHandler(DEVICENAME);\n  packetHandler_ = dynamixel::PacketHandler::getPacketHandler(PROTOCOL_VERSION);\n\n  // Open port\n  if (portHandler_->openPort() == false)\n  {\n    DEBUG_SERIAL.println(\"Failed to open port(Motor Driver)\");\n    return false;\n  }\n\n  // Set port baudrate\n  if (portHandler_->setBaudRate(baudrate_) == false)\n  {\n    DEBUG_SERIAL.println(\"Failed to set baud rate(Motor Driver)\");\n    return false;\n  }\n\n  // Enable Dynamixel Torque\n  setTorque(true);\n\n  groupSyncWriteVelocity_ = new dynamixel::GroupSyncWrite(portHandler_, packetHandler_, ADDR_X_GOAL_VELOCITY, LEN_X_GOAL_VELOCITY);\n  groupSyncReadEncoder_   = new dynamixel::GroupSyncRead(portHandler_, packetHandler_, ADDR_X_PRESENT_POSITION, LEN_X_PRESENT_POSITION);\n  \n  if (turtlebot3 == \"Burger\")\n    dynamixel_limit_max_velocity_ = BURGER_DXL_LIMIT_MAX_VELOCITY;\n  else if (turtlebot3 == \"Waffle or Waffle Pi\")\n    dynamixel_limit_max_velocity_ = WAFFLE_DXL_LIMIT_MAX_VELOCITY;\n  else\n    dynamixel_limit_max_velocity_ = BURGER_DXL_LIMIT_MAX_VELOCITY;\n\n  DEBUG_SERIAL.println(\"Success to init Motor Driver\");\n  return true;\n}\n\nbool Turtlebot3MotorDriver::setTorque(bool onoff)\n{\n  uint8_t dxl_error = 0;\n  int dxl_comm_result = COMM_TX_FAIL;\n\n  torque_ = onoff;\n\n  dxl_comm_result = packetHandler_->write1ByteTxRx(portHandler_, DXL_LEFT_ID, ADDR_X_TORQUE_ENABLE, onoff, &dxl_error);\n  if(dxl_comm_result != COMM_SUCCESS)\n  {\n    Serial.println(packetHandler_->getTxRxResult(dxl_comm_result));\n    return false;\n  }\n  else if(dxl_error != 0)\n  {\n    Serial.println(packetHandler_->getRxPacketError(dxl_error));\n    return false;\n  }\n\n  dxl_comm_result = packetHandler_->write1ByteTxRx(portHandler_, DXL_RIGHT_ID, ADDR_X_TORQUE_ENABLE, onoff, &dxl_error);\n  if(dxl_comm_result != COMM_SUCCESS)\n  {\n    Serial.println(packetHandler_->getTxRxResult(dxl_comm_result));\n    return false;\n  }\n  else if(dxl_error != 0)\n  {\n    Serial.println(packetHandler_->getRxPacketError(dxl_error));\n    return false;\n  }\n\n  return true;\n}\n\nbool Turtlebot3MotorDriver::getTorque()\n{\n  return torque_;\n}\n\nvoid Turtlebot3MotorDriver::close(void)\n{\n  // Disable Dynamixel Torque\n  setTorque(false);\n\n  // Close port\n  portHandler_->closePort();\n  DEBUG_SERIAL.end();\n}\n\nbool Turtlebot3MotorDriver::readEncoder(int32_t &left_value, int32_t &right_value)\n{\n  int dxl_comm_result = COMM_TX_FAIL;              // Communication result\n  bool dxl_addparam_result = false;                // addParam result\n  bool dxl_getdata_result = false;                 // GetParam result\n\n  // Set parameter\n  dxl_addparam_result = groupSyncReadEncoder_->addParam(left_wheel_id_);\n  if (dxl_addparam_result != true)\n    return false;\n\n  dxl_addparam_result = groupSyncReadEncoder_->addParam(right_wheel_id_);\n  if (dxl_addparam_result != true)\n    return false;\n\n  // Syncread present position\n  dxl_comm_result = groupSyncReadEncoder_->txRxPacket();\n  if (dxl_comm_result != COMM_SUCCESS)\n    Serial.println(packetHandler_->getTxRxResult(dxl_comm_result));\n\n  // Check if groupSyncRead data of Dynamixels are available\n  dxl_getdata_result = groupSyncReadEncoder_->isAvailable(left_wheel_id_, ADDR_X_PRESENT_POSITION, LEN_X_PRESENT_POSITION);\n  if (dxl_getdata_result != true)\n    return false;\n\n  dxl_getdata_result = groupSyncReadEncoder_->isAvailable(right_wheel_id_, ADDR_X_PRESENT_POSITION, LEN_X_PRESENT_POSITION);\n  if (dxl_getdata_result != true)\n    return false;\n\n  // Get data\n  left_value  = groupSyncReadEncoder_->getData(left_wheel_id_,  ADDR_X_PRESENT_POSITION, LEN_X_PRESENT_POSITION);\n  right_value = groupSyncReadEncoder_->getData(right_wheel_id_, ADDR_X_PRESENT_POSITION, LEN_X_PRESENT_POSITION);\n\n  groupSyncReadEncoder_->clearParam();\n  return true;\n}\n\nbool Turtlebot3MotorDriver::writeVelocity(int64_t left_value, int64_t right_value)\n{\n  bool dxl_addparam_result;\n  int8_t dxl_comm_result;\n\n  uint8_t left_data_byte[4] = {0, };\n  uint8_t right_data_byte[4] = {0, };\n\n\n  left_data_byte[0] = DXL_LOBYTE(DXL_LOWORD(left_value));\n  left_data_byte[1] = DXL_HIBYTE(DXL_LOWORD(left_value));\n  left_data_byte[2] = DXL_LOBYTE(DXL_HIWORD(left_value));\n  left_data_byte[3] = DXL_HIBYTE(DXL_HIWORD(left_value));\n\n  dxl_addparam_result = groupSyncWriteVelocity_->addParam(left_wheel_id_, (uint8_t*)&left_data_byte);\n  if (dxl_addparam_result != true)\n    return false;\n\n  right_data_byte[0] = DXL_LOBYTE(DXL_LOWORD(right_value));\n  right_data_byte[1] = DXL_HIBYTE(DXL_LOWORD(right_value));\n  right_data_byte[2] = DXL_LOBYTE(DXL_HIWORD(right_value));\n  right_data_byte[3] = DXL_HIBYTE(DXL_HIWORD(right_value));\n\n  dxl_addparam_result = groupSyncWriteVelocity_->addParam(right_wheel_id_, (uint8_t*)&right_data_byte);\n  if (dxl_addparam_result != true)\n    return false;\n\n  dxl_comm_result = groupSyncWriteVelocity_->txPacket();\n  if (dxl_comm_result != COMM_SUCCESS)\n  {\n    Serial.println(packetHandler_->getTxRxResult(dxl_comm_result));\n    return false;\n  }\n\n  groupSyncWriteVelocity_->clearParam();\n  return true;\n}\n\nbool Turtlebot3MotorDriver::controlMotor(const float wheel_radius, const float wheel_separation, float* value)\n{\n  bool dxl_comm_result = false;\n  \n  float wheel_velocity_cmd[2];\n\n  float lin_vel = value[LINEAR];\n  float ang_vel = value[ANGULAR];\n\n  wheel_velocity_cmd[LEFT]   = lin_vel - (ang_vel * wheel_separation / 2);\n  wheel_velocity_cmd[RIGHT]  = lin_vel + (ang_vel * wheel_separation / 2);\n\n  wheel_velocity_cmd[LEFT]  = constrain(wheel_velocity_cmd[LEFT]  * VELOCITY_CONSTANT_VALUE / wheel_radius, -dynamixel_limit_max_velocity_, dynamixel_limit_max_velocity_);\n  wheel_velocity_cmd[RIGHT] = constrain(wheel_velocity_cmd[RIGHT] * VELOCITY_CONSTANT_VALUE / wheel_radius, -dynamixel_limit_max_velocity_, dynamixel_limit_max_velocity_);\n\n  dxl_comm_result = writeVelocity((int64_t)wheel_velocity_cmd[LEFT], (int64_t)wheel_velocity_cmd[RIGHT]);\n  if (dxl_comm_result == false)\n    return false;\n\n  return true;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3/src/turtlebot3/turtlebot3_sensor.cpp",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n/* Authors: Yoonseok Pyo, Leon Jung, Darby Lim, HanCheol Cho, Gilbert */\n\n#include \"../../include/turtlebot3/turtlebot3_sensor.h\"\n\nTurtlebot3Sensor::Turtlebot3Sensor()\n{\n}\n\nTurtlebot3Sensor::~Turtlebot3Sensor()\n{\n  DEBUG_SERIAL.end();\n}\n\nbool Turtlebot3Sensor::init(void)\n{\n  DEBUG_SERIAL.begin(57600);\n\n  initBumper();\n  initIR();\n  initSonar();\n  initLED();\n\n  uint8_t get_error_code = 0x00;\n\n  #if defined NOETIC_SUPPORT\n    battery_state_msg_.temperature     = NAN;\n  #endif\n\n  battery_state_msg_.current         = NAN;\n  battery_state_msg_.charge          = NAN;\n  battery_state_msg_.capacity        = NAN;\n  battery_state_msg_.design_capacity = NAN;\n  battery_state_msg_.percentage      = NAN;\n\n  get_error_code = imu_.begin();\n\n  if (get_error_code != 0x00)\n    DEBUG_SERIAL.println(\"Failed to init Sensor\");\n  else\n    DEBUG_SERIAL.println(\"Success to init Sensor\");\n\n  return get_error_code;\n}\n\nvoid Turtlebot3Sensor::initIMU(void)\n{\n  imu_.begin();\n}\n\nvoid Turtlebot3Sensor::updateIMU(void)\n{\n  imu_.update();\n}\n\nvoid Turtlebot3Sensor::calibrationGyro()\n{\n  uint32_t pre_time;\n  uint32_t t_time;\n\n  const uint8_t led_ros_connect = 3;\n\n  imu_.SEN.gyro_cali_start();\n  \n  t_time   = millis();\n  pre_time = millis();\n\n  while(!imu_.SEN.gyro_cali_get_done())\n  {\n    imu_.update();\n\n    if (millis()-pre_time > 5000)\n    {\n      break;\n    }\n    if (millis()-t_time > 100)\n    {\n      t_time = millis();\n      setLedToggle(led_ros_connect);\n    }\n  }\n}\n\nsensor_msgs::Imu Turtlebot3Sensor::getIMU(void)\n{\n  imu_msg_.angular_velocity.x = imu_.SEN.gyroADC[0] * GYRO_FACTOR;\n  imu_msg_.angular_velocity.y = imu_.SEN.gyroADC[1] * GYRO_FACTOR;\n  imu_msg_.angular_velocity.z = imu_.SEN.gyroADC[2] * GYRO_FACTOR;\n  imu_msg_.angular_velocity_covariance[0] = 0.02;\n  imu_msg_.angular_velocity_covariance[1] = 0;\n  imu_msg_.angular_velocity_covariance[2] = 0;\n  imu_msg_.angular_velocity_covariance[3] = 0;\n  imu_msg_.angular_velocity_covariance[4] = 0.02;\n  imu_msg_.angular_velocity_covariance[5] = 0;\n  imu_msg_.angular_velocity_covariance[6] = 0;\n  imu_msg_.angular_velocity_covariance[7] = 0;\n  imu_msg_.angular_velocity_covariance[8] = 0.02;\n\n  imu_msg_.linear_acceleration.x = imu_.SEN.accADC[0] * ACCEL_FACTOR;\n  imu_msg_.linear_acceleration.y = imu_.SEN.accADC[1] * ACCEL_FACTOR;\n  imu_msg_.linear_acceleration.z = imu_.SEN.accADC[2] * ACCEL_FACTOR;\n\n  imu_msg_.linear_acceleration_covariance[0] = 0.04;\n  imu_msg_.linear_acceleration_covariance[1] = 0;\n  imu_msg_.linear_acceleration_covariance[2] = 0;\n  imu_msg_.linear_acceleration_covariance[3] = 0;\n  imu_msg_.linear_acceleration_covariance[4] = 0.04;\n  imu_msg_.linear_acceleration_covariance[5] = 0;\n  imu_msg_.linear_acceleration_covariance[6] = 0;\n  imu_msg_.linear_acceleration_covariance[7] = 0;\n  imu_msg_.linear_acceleration_covariance[8] = 0.04;\n\n  imu_msg_.orientation.w = imu_.quat[0];\n  imu_msg_.orientation.x = imu_.quat[1];\n  imu_msg_.orientation.y = imu_.quat[2];\n  imu_msg_.orientation.z = imu_.quat[3];\n\n  imu_msg_.orientation_covariance[0] = 0.0025;\n  imu_msg_.orientation_covariance[1] = 0;\n  imu_msg_.orientation_covariance[2] = 0;\n  imu_msg_.orientation_covariance[3] = 0;\n  imu_msg_.orientation_covariance[4] = 0.0025;\n  imu_msg_.orientation_covariance[5] = 0;\n  imu_msg_.orientation_covariance[6] = 0;\n  imu_msg_.orientation_covariance[7] = 0;\n  imu_msg_.orientation_covariance[8] = 0.0025;\n\n  return imu_msg_;\n}\n\nfloat* Turtlebot3Sensor::getOrientation(void)\n{\n  static float orientation[4];\n\n  orientation[0] = imu_.quat[0];\n  orientation[1] = imu_.quat[1];\n  orientation[2] = imu_.quat[2];\n  orientation[3] = imu_.quat[3];\n\n  return orientation;\n}\n\nsensor_msgs::MagneticField Turtlebot3Sensor::getMag(void)\n{\n  mag_msg_.magnetic_field.x = imu_.SEN.magADC[0] * MAG_FACTOR;\n  mag_msg_.magnetic_field.y = imu_.SEN.magADC[1] * MAG_FACTOR;\n  mag_msg_.magnetic_field.z = imu_.SEN.magADC[2] * MAG_FACTOR;\n\n  mag_msg_.magnetic_field_covariance[0] = 0.0048;\n  mag_msg_.magnetic_field_covariance[1] = 0;\n  mag_msg_.magnetic_field_covariance[2] = 0;\n  mag_msg_.magnetic_field_covariance[3] = 0;\n  mag_msg_.magnetic_field_covariance[4] = 0.0048;\n  mag_msg_.magnetic_field_covariance[5] = 0;\n  mag_msg_.magnetic_field_covariance[6] = 0;\n  mag_msg_.magnetic_field_covariance[7] = 0;\n  mag_msg_.magnetic_field_covariance[8] = 0.0048;\n\n  return mag_msg_;\n}\n\nfloat Turtlebot3Sensor::checkVoltage(void)\n{\n  float vol_value;\n  \n  vol_value = getPowerInVoltage();\n\n  return vol_value;\n}\n\nuint8_t Turtlebot3Sensor::checkPushButton(void)\n{\n  return getPushButton();\n}\n\nvoid Turtlebot3Sensor::melody(uint16_t* note, uint8_t note_num, uint8_t* durations)\n{\n  for (int thisNote = 0; thisNote < note_num; thisNote++) \n  {\n    // to calculate the note duration, take one second\n    // divided by the note type.\n    //e.g. quarter note = 1000 / 4, eighth note = 1000/8, etc.\n    int noteDuration = 1000 / durations[thisNote];\n    tone(BDPIN_BUZZER, note[thisNote], noteDuration);\n\n    // to distinguish the notes, set a minimum time between them.\n    // the note's duration + 30% seems to work well:\n    int pauseBetweenNotes = noteDuration * 1.30;\n    delay(pauseBetweenNotes);\n    // stop the tone playing:\n    noTone(BDPIN_BUZZER);\n  }\n}\n\nvoid Turtlebot3Sensor::makeSound(uint8_t index)\n{\n  const uint16_t NOTE_C4 = 262;\n  const uint16_t NOTE_D4 = 294;\n  const uint16_t NOTE_E4 = 330;\n  const uint16_t NOTE_F4 = 349;\n  const uint16_t NOTE_G4 = 392;\n  const uint16_t NOTE_A4 = 440;\n  const uint16_t NOTE_B4 = 494;\n  const uint16_t NOTE_C5 = 523;\n//  const uint16_t NOTE_C6 = 1047;\n\n  const uint8_t OFF         = 0;\n  const uint8_t ON          = 1;\n  const uint8_t LOW_BATTERY = 2;\n  const uint8_t ERROR       = 3;\n  const uint8_t BUTTON1     = 4;\n  const uint8_t BUTTON2     = 5;\n\n  uint16_t note[8]     = {0, 0};\n  uint8_t  duration[8] = {0, 0};\n\n  switch (index)\n  {\n    case ON:\n      note[0] = NOTE_C4;   duration[0] = 4;\n      note[1] = NOTE_D4;   duration[1] = 4;\n      note[2] = NOTE_E4;   duration[2] = 4;\n      note[3] = NOTE_F4;   duration[3] = 4;\n      note[4] = NOTE_G4;   duration[4] = 4;\n      note[5] = NOTE_A4;   duration[5] = 4;\n      note[6] = NOTE_B4;   duration[6] = 4;\n      note[7] = NOTE_C5;   duration[7] = 4;   \n     break;\n\n    case OFF:\n      note[0] = NOTE_C5;   duration[0] = 4;\n      note[1] = NOTE_B4;   duration[1] = 4;\n      note[2] = NOTE_A4;   duration[2] = 4;\n      note[3] = NOTE_G4;   duration[3] = 4;\n      note[4] = NOTE_F4;   duration[4] = 4;\n      note[5] = NOTE_E4;   duration[5] = 4;\n      note[6] = NOTE_D4;   duration[6] = 4;\n      note[7] = NOTE_C4;   duration[7] = 4;  \n     break;\n\n    case LOW_BATTERY:\n      note[0] = 1000;      duration[0] = 1;\n      note[1] = 1000;      duration[1] = 1;\n      note[2] = 1000;      duration[2] = 1;\n      note[3] = 1000;      duration[3] = 1;\n      note[4] = 0;         duration[4] = 8;\n      note[5] = 0;         duration[5] = 8;\n      note[6] = 0;         duration[6] = 8;\n      note[7] = 0;         duration[7] = 8;\n     break;\n\n    case ERROR:\n      note[0] = 1000;      duration[0] = 3;\n      note[1] = 500;       duration[1] = 3;\n      note[2] = 1000;      duration[2] = 3;\n      note[3] = 500;       duration[3] = 3;\n      note[4] = 1000;      duration[4] = 3;\n      note[5] = 500;       duration[5] = 3;\n      note[6] = 1000;      duration[6] = 3;\n      note[7] = 500;       duration[7] = 3;\n     break;\n\n    case BUTTON1:\n     break;\n\n    case BUTTON2:\n     break;\n\n    default:\n      note[0] = NOTE_C4;   duration[0] = 4;\n      note[1] = NOTE_D4;   duration[1] = 4;\n      note[2] = NOTE_E4;   duration[2] = 4;\n      note[3] = NOTE_F4;   duration[3] = 4;\n      note[4] = NOTE_G4;   duration[4] = 4;\n      note[5] = NOTE_A4;   duration[5] = 4;\n      note[6] = NOTE_B4;   duration[6] = 4;\n      note[7] = NOTE_C4;   duration[7] = 4; \n     break;\n  }\n\n  melody(note, 8, duration);\n}\n\nvoid Turtlebot3Sensor::initBumper(void)\n{\n  ollo_.begin(3, TOUCH_SENSOR);\n  ollo_.begin(4, TOUCH_SENSOR);\n}\n\nuint8_t Turtlebot3Sensor::checkPushBumper(void)\n{\n  uint8_t push_state = 0;\n\n  if      (ollo_.read(3, TOUCH_SENSOR) == HIGH) push_state = 2;\n  else if (ollo_.read(4, TOUCH_SENSOR) == HIGH) push_state = 1;\n  else    push_state = 0;\n  \n  return push_state;\n}\n\nvoid Turtlebot3Sensor::initIR(void)\n{\n  ollo_.begin(2, IR_SENSOR);\n}\n\nfloat Turtlebot3Sensor::getIRsensorData(void)\n{\n  float ir_data = ollo_.read(2, IR_SENSOR);\n  \n  return ir_data;\n}\n\nvoid Turtlebot3Sensor::initSonar(void)\n{\n  sonar_pin_.trig = BDPIN_GPIO_1;\n  sonar_pin_.echo = BDPIN_GPIO_2;\n\n  pinMode(sonar_pin_.trig, OUTPUT);\n  pinMode(sonar_pin_.echo, INPUT);\n}\n\nvoid Turtlebot3Sensor::updateSonar(uint32_t t)\n{\n  static uint32_t t_time = 0;\n  static bool make_pulse = TRUE;\n  static bool get_duration = FALSE;\n\n  float distance = 0.0, duration = 0.0;\n\n  if (make_pulse == TRUE)\n  {\n    digitalWrite(sonar_pin_.trig, HIGH);\n\n    if (t - t_time >= 10)\n    {\n      digitalWrite(sonar_pin_.trig, LOW);\n\n      get_duration = TRUE;\n      make_pulse = FALSE;\n\n      t_time = t;\n    }\n  }\n\n  if (get_duration == TRUE)\n  {\n    duration = pulseIn(sonar_pin_.echo, HIGH);\n    distance = ((float)(340 * duration) / 10000) / 2;\n\n    make_pulse = TRUE;\n    get_duration = FALSE;\n  }\n\n  sonar_data_ = distance;\n}\n\nfloat Turtlebot3Sensor::getSonarData(void)\n{\n  float distance = 0.0;\n\n  distance = sonar_data_;\n\n  return distance;\n}\n\nfloat Turtlebot3Sensor::getIlluminationData(void)\n{\n  uint16_t light;\n\n  light = analogRead(A1);\n\n  return light;\n}\n\nvoid Turtlebot3Sensor::initLED(void)\n{\n  led_pin_array_.front_left  = BDPIN_GPIO_4;\n  led_pin_array_.front_right = BDPIN_GPIO_6;\n  led_pin_array_.back_left   = BDPIN_GPIO_8;\n  led_pin_array_.back_right  = BDPIN_GPIO_10;\n \n  pinMode(led_pin_array_.front_left, OUTPUT);\n  pinMode(led_pin_array_.front_right, OUTPUT);\n  pinMode(led_pin_array_.back_left, OUTPUT);\n  pinMode(led_pin_array_.back_right, OUTPUT);\n}\n\nvoid Turtlebot3Sensor::setLedPattern(double linear_vel, double angular_vel)\n{\n  if (linear_vel > 0.0 && angular_vel == 0.0)     // front\n  {\n    digitalWrite(led_pin_array_.front_left, HIGH);\n    digitalWrite(led_pin_array_.front_right, HIGH);\n    digitalWrite(led_pin_array_.back_left, LOW);\n    digitalWrite(led_pin_array_.back_right, LOW);\n  }\n  else if (linear_vel >= 0.0 && angular_vel > 0.0)  // front left\n  {\n    digitalWrite(led_pin_array_.front_left, HIGH);\n    digitalWrite(led_pin_array_.front_right, LOW);\n    digitalWrite(led_pin_array_.back_left, LOW);\n    digitalWrite(led_pin_array_.back_right, LOW);\n  }\n  else if (linear_vel >= 0.0 && angular_vel < 0.0)  // front right\n  {\n    digitalWrite(led_pin_array_.front_left, LOW);\n    digitalWrite(led_pin_array_.front_right, HIGH);\n    digitalWrite(led_pin_array_.back_left, LOW);\n    digitalWrite(led_pin_array_.back_right, LOW);\n  }\n  else if (linear_vel < 0.0 && angular_vel == 0.0) // back\n  {\n    digitalWrite(led_pin_array_.front_left, LOW);\n    digitalWrite(led_pin_array_.front_right, LOW);\n    digitalWrite(led_pin_array_.back_left, HIGH);\n    digitalWrite(led_pin_array_.back_right, HIGH);\n  }\n  else if (linear_vel <= 0.0 && angular_vel > 0.0)  // back right\n  {\n    digitalWrite(led_pin_array_.front_left, LOW);\n    digitalWrite(led_pin_array_.front_right, LOW);\n    digitalWrite(led_pin_array_.back_left, LOW);\n    digitalWrite(led_pin_array_.back_right, HIGH);\n  }\n  else if (linear_vel <= 0.0 && angular_vel < 0.0)  // back left\n  {\n    digitalWrite(led_pin_array_.front_left, LOW);\n    digitalWrite(led_pin_array_.front_right, LOW);\n    digitalWrite(led_pin_array_.back_left, HIGH);\n    digitalWrite(led_pin_array_.back_right, LOW);\n  }\n  else \n  {\n    digitalWrite(led_pin_array_.front_left, LOW);\n    digitalWrite(led_pin_array_.front_right, LOW);\n    digitalWrite(led_pin_array_.back_left, LOW);\n    digitalWrite(led_pin_array_.back_right, LOW);\n  }\n}\n\n\n\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros2/examples/turtlebot3_burger/turtlebot3_burger.ino",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n#include <TurtleBot3_ROS2.h>\n\n/*******************************************************************************\n* Setup function\n*******************************************************************************/\nvoid setup()\n{\n  // Begin TurtleBot3 core for support Burger.\n  TurtleBot3Core::begin(\"Burger\");\n}\n\n/*******************************************************************************\n* Loop function\n*******************************************************************************/\nvoid loop()\n{\n  // Run TurtleBot3 core for communicating with ROS2 node, sensing several sensors and controlling actuators.\n  TurtleBot3Core::run();\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros2/examples/turtlebot3_manipulation/turtlebot3_manipulation.ino",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n#include <TurtleBot3_ROS2.h>\n\n/*******************************************************************************\n* Setup function\n*******************************************************************************/\nvoid setup()\n{\n  // Begin TurtleBot3 core for support Waffle.\n  TurtleBot3Core::begin(\"Waffle_OpenManipulator\");\n}\n\n/*******************************************************************************\n* Loop function\n*******************************************************************************/\nvoid loop()\n{\n  // Run TurtleBot3 core for communicating with ROS2 node, sensing several sensors and controlling actuators.\n  TurtleBot3Core::run();\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros2/examples/turtlebot3_waffle/turtlebot3_waffle.ino",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n#include <TurtleBot3_ROS2.h>\n\n/*******************************************************************************\n* Setup function\n*******************************************************************************/\nvoid setup()\n{\n  // Begin TurtleBot3 core for support Waffle.\n  TurtleBot3Core::begin(\"Waffle\");\n}\n\n/*******************************************************************************\n* Loop function\n*******************************************************************************/\nvoid loop()\n{\n  // Run TurtleBot3 core for communicating with ROS2 node, sensing several sensors and controlling actuators.\n  TurtleBot3Core::run();\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros2/include/turtlebot3/open_manipulator_driver.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n#ifndef OPEN_MANIPULATOR_DRIVER_H_\n#define OPEN_MANIPULATOR_DRIVER_H_\n\n#include <Dynamixel2Arduino.h>\n\n\nenum JointMotorLocation{\n  JOINT_1 = 0,\n  JOINT_2,\n  JOINT_3,\n  JOINT_4,\n  GRIPPER,\n  JOINT_MOTOR_NUM_MAX\n};\n\ntypedef struct\n{\n  int32_t value[JOINT_MOTOR_NUM_MAX];\n} joint_position_info_t;\n\ntypedef struct\n{\n  int32_t value[JOINT_MOTOR_NUM_MAX];\n} joint_velocity_info_t;\n\ntypedef struct\n{\n  int16_t value[JOINT_MOTOR_NUM_MAX];\n} joint_current_info_t;\n\ntypedef struct\n{\n  uint32_t value[JOINT_MOTOR_NUM_MAX];\n} joint_accel_info_t;\n\n\nclass OpenManipulatorDriver\n{\n public:\n  OpenManipulatorDriver(Dynamixel2Arduino &dxl_param);\n  ~OpenManipulatorDriver();\n  \n  bool init(void);\n  void close(void);\n\n  bool is_connected();  \n\n  bool set_torque(bool onoff);\n  bool get_torque(void);\n  \n  bool read_goal_position(joint_position_info_t &position_info);\n  bool read_present_position(joint_position_info_t &position_info);\n  bool read_present_velocity(joint_velocity_info_t &velocity_info);\n  bool read_present_current(joint_current_info_t &current_info);\n  bool read_profile_acceleration(joint_accel_info_t &accel_info);  \n  bool read_profile_velocity(joint_accel_info_t &accel_info);  \n  bool read_goal_current(joint_current_info_t &current_info);\n  \n  bool write_goal_position_joint(joint_position_info_t &position_info);\n  bool write_profile_acceleration_joint(joint_accel_info_t &accel_info);\n  bool write_profile_velocity_joint(joint_accel_info_t &accel_info);\n  bool write_goal_current_joint(joint_current_info_t &current_info);\n\n  bool write_goal_position_gripper(joint_position_info_t &position_info);\n  bool write_profile_acceleration_gripper(joint_accel_info_t &accel_info);\n  bool write_profile_velocity_gripper(joint_accel_info_t &accel_info);\n  bool write_goal_current_gripper(joint_current_info_t &current_info);\n\n private:\n  \n  bool is_ready(void);\n\n  uint8_t motor_id_[JOINT_MOTOR_NUM_MAX];\n  bool torque_;\n  bool is_init_;\n  bool is_connected_;\n  Dynamixel2Arduino &dxl;\n};\n\n#endif // OPEN_MANIPULATOR_DRIVER_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros2/include/turtlebot3/turtlebot3.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n#ifndef TURTLEBOT3_H_\n#define TURTLEBOT3_H_\n\n#include <stdint.h>\n#include \"turtlebot3_motor_driver.h\"\n#include \"turtlebot3_sensor.h\"\n#include \"turtlebot3_controller.h\"\n#include \"turtlebot3_diagnosis.h\"\n#include \"open_manipulator_driver.h\"\n\n#define DEBUG_ENABLE 1\n\n#if DEBUG_ENABLE\n  #define DEBUG_SERIAL_BEGIN(x) SerialBT2.begin(x)\n  #define DEBUG_PRINT(x) SerialBT2.print(x)\n  #define DEBUG_PRINTLN(x) SerialBT2.println(x)\n#else\n  #define DEBUG_SERIAL_BEGIN(x) \n  #define DEBUG_PRINT(x) \n  #define DEBUG_PRINTLN(x) \n#endif\n\nconst uint8_t FIRMWARE_VER = 5; //DYNAMIXEL2Arduino v0.6.1 or higher is required.\nconst uint32_t INTERVAL_MS_TO_CONTROL_MOTOR = 20;\nconst uint32_t INTERVAL_MS_TO_UPDATE_CONTROL_ITEM = 20;\n\nnamespace TurtleBot3Core{\n  void begin(const char* model_name);\n  void run();\n} //namespace TurtleBot3Core\n\n\n\n#endif // TURTLEBOT3_H_\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros2/include/turtlebot3/turtlebot3_controller.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n#ifndef TURTLEBOT3_CONTROLLER_H_\n#define TURTLEBOT3_CONTROLLER_H_\n\n#include <RC100.h>\n\n#define CONST_VEL 0.2\n\n#define VELOCITY_LINEAR_X                0.01   // m/s\n#define VELOCITY_ANGULAR_Z               0.1    // rad/s\n\nclass Turtlebot3Controller\n{\n public:\n  Turtlebot3Controller();\n  ~Turtlebot3Controller();\n\n  bool init(float max_lin_vel, float max_ang_vel, uint8_t scale_lin_vel = 1, uint8_t scale_ang_vel = 1);\n\n  void getRCdata(float *get_cmd_vel);\n\n private:\n  RC100 rc100_;\n\n  double const_cmd_vel_;\n\n  float max_lin_vel_;\n  float min_lin_vel_;\n  float max_ang_vel_;\n  float min_ang_vel_;\n  uint8_t scale_lin_vel_;\n  uint8_t scale_ang_vel_;\n};\n\n#endif // TURTLEBOT3_CONTROLLER_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros2/include/turtlebot3/turtlebot3_diagnosis.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n#ifndef TURTLEBOT3_DIAGNOSIS_H_\n#define TURTLEBOT3_DIAGNOSIS_H_\n\n#include <Arduino.h>\n\n#define LED_TXD                          0\n#define LED_RXD                          1\n#define LED_LOW_BATTERY                  2\n#define LED_ROS_CONNECT                  3\n#define LED_WORKING_CHECK                13\n\n#define BATTERY_POWER_OFF                0\n#define BATTERY_POWER_STARTUP            1\n#define BATTERY_POWER_NORMAL             2\n#define BATTERY_POWER_CHECK              3\n#define BATTERY_POWER_WARNNING           4\n\n#define WAIT_FOR_BUTTON_PRESS            0\n#define WAIT_SECOND                      1\n#define CHECK_BUTTON_RELEASED            2\n\nenum DEVICE_STATUS{\n  STATUS_NOT_CONNECTED_MOTORS = -1,\n  STATUS_RUNNING              = 0\n};\n\nclass Turtlebot3Diagnosis\n{\n public:\n  Turtlebot3Diagnosis();\n  ~Turtlebot3Diagnosis();\n\n  bool init();\n\n  void showLedStatus(bool isConnected);\n  void updateRxTxLed(void);\n\n  void setPowerOn(void);\n  void setPowerOff(void);\n\n  uint8_t updateVoltageCheck(bool check_setup);\n\n  uint8_t getButtonPress(uint16_t time_to_press);  \n\n private:\n\n};\n\n#endif // TURTLEBOT3_DIAGNOSIS_H_"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros2/include/turtlebot3/turtlebot3_motor_driver.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n#ifndef TURTLEBOT3_MOTOR_DRIVER_H_\n#define TURTLEBOT3_MOTOR_DRIVER_H_\n\n#include <Dynamixel2Arduino.h>\n\n#define TORQUE_ENABLE ControlTableItem::TORQUE_ENABLE\n\nenum MortorLocation{\n  LEFT = 0,\n  RIGHT,\n  MOTOR_NUM_MAX\n};\n\nenum VelocityType{\n  LINEAR = 0,\n  ANGULAR,\n  TYPE_NUM_MAX\n};\n\n\nclass Turtlebot3MotorDriver\n{\n public:\n  Turtlebot3MotorDriver();\n  ~Turtlebot3MotorDriver();\n  \n  bool init(void);\n  void close(void);\n\n  bool is_connected();\n\n  bool set_torque(bool onoff);\n  bool get_torque();\n  \n  bool read_present_position(int32_t &left_value, int32_t &right_value);\n  bool read_present_velocity(int32_t &left_value, int32_t &right_value);\n  bool read_present_current(int16_t &left_value, int16_t &right_value);\n  bool read_profile_acceleration(uint32_t &left_value, uint32_t &right_value);\n  \n  bool write_velocity(int32_t left_value, int32_t right_value);\n  bool write_profile_acceleration(uint32_t left_value, uint32_t right_value);\n\n  bool control_motors(const float wheel_separation, float linear_value, float angular_value);\n\n  Dynamixel2Arduino& getDxl();\n  \n private:\n  uint8_t left_wheel_id_;\n  uint8_t right_wheel_id_;\n  bool torque_;\n};\n\n#endif // TURTLEBOT3_MOTOR_DRIVER_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros2/include/turtlebot3/turtlebot3_sensor.h",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n#ifndef TURTLEBOT3_SENSOR_H_\n#define TURTLEBOT3_SENSOR_H_\n\n#include <IMU.h>\n\n#include \"OLLO.h\"\n\n#define ACCEL_FACTOR                      0.000598550415   // (ADC_Value / Scale) * 9.80665            => Range : +- 2[g]\n                                                           //                                             Scale : +- 16384\n#define GYRO_FACTOR                       0.0010642        // (ADC_Value/Scale) * (pi/180)             => Range : +- 2000[deg/s]\n                                                           //                                             Scale : +- 16.4[deg/s]\n\n#define MAG_FACTOR                        15e-8\n\ntypedef struct LED_PIN_ARRAY\n{\n  int front_left;\n  int front_right;\n  int back_left;\n  int back_right;\n}LedPinArray;\n \ntypedef struct SONAR_PIN\n{\n  int trig;\n  int echo;\n}SonarPin;\n\nclass Turtlebot3Sensor\n{\n public:\n  Turtlebot3Sensor();\n  ~Turtlebot3Sensor();\n\n  bool init(void);\n\n  // IMU\n  void initIMU(void);\n  float* getIMU(void);\n  void updateIMU(void);\n  void calibrationGyro(void);\n\n  float* getImuAngularVelocity(void);\n  float* getImuLinearAcc(void);\n  float* getImuMagnetic(void);\n  float* getOrientation(void);\n  \n  // Battery\n  float checkVoltage(void);\n\n  // Button\n  uint8_t checkPushButton(void);\n\n  // Sound\n  void onMelody();\n  void makeMelody(uint8_t index);  \n\n  // Bumper\n  void initBumper(void);\n  bool getBumper1State();\n  bool getBumper2State();\n  uint8_t checkPushBumper(void);\n\n  // Cliff sensor\n  void initIR(void);\n  float getIRsensorData(void);\n\n  // Sonar sensor\n  void initSonar(void);\n  void updateSonar(uint32_t t);\n  float getSonarData(void);\n\n  // Illumination sensor\n  float getIlluminationData(void);\n\n  // led pattern\n  void initLED(void);\n  void setLedPattern(double linear_vel, double angular_vel);\n private:\n  cIMU imu_;\n  OLLO ollo_;\n\n  LedPinArray led_pin_array_;\n  SonarPin sonar_pin_;\n\n  float sonar_data_;\n\n  bool is_melody_play_complete_;\n  uint16_t melody_note_[8];\n  uint8_t melody_duration_[8];\n};\n\n#endif // TURTLEBOT3_SENSOR_H_\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros2/library.properties",
    "content": "name=TurtleBot3 ROS2\nversion=1.0.0\nauthor=Kei Ki\nmaintainer=Will Son(willson@robotis.com)\nsentence=library for TurtleBot3 ROS2 using DYNAMIXEL 2.0 protocol\nparagraph=\ncategory=Data Processing\nurl=https://github.com/ROBOTIS-GIT/turtlebot3\narchitectures=OpenCR\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros2/src/TurtleBot3_ROS2.h",
    "content": "#include \"../include/turtlebot3/turtlebot3.h\""
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros2/src/turtlebot3/open_manipulator_driver.cpp",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n#include \"../../include/turtlebot3/open_manipulator_driver.h\"\n\n\n/* DYNAMIXEL Information for controlling motors and  */\nconst uint8_t DXL_MOTOR_ID_JOINT_1 = 11; \nconst uint8_t DXL_MOTOR_ID_JOINT_2 = 12; \nconst uint8_t DXL_MOTOR_ID_JOINT_3 = 13; \nconst uint8_t DXL_MOTOR_ID_JOINT_4 = 14; \nconst uint8_t DXL_MOTOR_ID_GRIPPER = 15; \n\nstatic ParamForSyncReadInst_t sync_read_param;\nstatic ParamForSyncWriteInst_t sync_write_param;\nstatic RecvInfoFromStatusInst_t read_result;\n\n\n\nOpenManipulatorDriver::OpenManipulatorDriver(Dynamixel2Arduino &dxl_param)\n: dxl(dxl_param),\n  torque_(false),\n  is_init_(false),\n  is_connected_(false)\n{\n  motor_id_[JOINT_1] = DXL_MOTOR_ID_JOINT_1;\n  motor_id_[JOINT_2] = DXL_MOTOR_ID_JOINT_2;\n  motor_id_[JOINT_3] = DXL_MOTOR_ID_JOINT_3;\n  motor_id_[JOINT_4] = DXL_MOTOR_ID_JOINT_4;\n  motor_id_[GRIPPER] = DXL_MOTOR_ID_GRIPPER;\n}\n\nOpenManipulatorDriver::~OpenManipulatorDriver()\n{\n  close();\n}\n\nbool OpenManipulatorDriver::init(void)\n{\n  sync_write_param.id_count = JOINT_MOTOR_NUM_MAX;\n  for (int i=0; i<JOINT_MOTOR_NUM_MAX; i++){\n    sync_write_param.xel[i].id = motor_id_[i];\n  }\n\n  sync_read_param.addr = 132;\n  sync_read_param.length = 4;\n  sync_read_param.id_count = JOINT_MOTOR_NUM_MAX;\n  for (int i=0; i<JOINT_MOTOR_NUM_MAX; i++){\n    sync_read_param.xel[i].id = motor_id_[i];    \n  }\n\n  // Enable Dynamixel Torque\n  set_torque(true);\n\n  is_init_ = true;\n\n  return true;\n}\n\nbool OpenManipulatorDriver::is_connected()\n{\n  bool ret = true;\n\n  if (is_init_ == false) return false;\n\n  for (int i=0; i<JOINT_MOTOR_NUM_MAX; i++) {\n    if (dxl.ping(motor_id_[i]) == false) {\n      ret = false;\n      break;\n    }\n  }\n\n  is_connected_ = ret;\n  \n  return ret;\n}\n\nbool OpenManipulatorDriver::is_ready(void)\n{\n  if (is_init_ == false) return false;\n  if (is_connected_ == false) return false;\n\n  return true;\n}\n\nbool OpenManipulatorDriver::set_torque(bool onoff)\n{\n  bool ret = false;\n  \n  if (is_ready() == false) return false;\n\n  sync_write_param.addr = 64;\n  sync_write_param.length = 1;\n  sync_write_param.id_count = JOINT_MOTOR_NUM_MAX;\n\n  for (int i=0; i<JOINT_MOTOR_NUM_MAX; i++){\n    sync_write_param.xel[i].data[0] = onoff;\n  }\n\n  if(dxl.syncWrite(sync_write_param) == true){\n    ret = true;\n    torque_ = onoff;\n  }\n\n  return ret;\n}\n\nbool OpenManipulatorDriver::get_torque()\n{\n  bool ret = true;\n\n  if (is_ready() == false) return false;\n\n  for (int i=0; i<JOINT_MOTOR_NUM_MAX; i++) {\n    if (dxl.readControlTableItem(ControlTableItem::TORQUE_ENABLE, motor_id_[i]) == false) {\n      ret = false;\n      break;\n    }\n  }\n\n  torque_ = ret;\n\n  return torque_;\n}\n\nvoid OpenManipulatorDriver::close(void)\n{\n  if (is_ready() == false) return;\n\n  // Disable Dynamixel Torque\n  set_torque(false);\n}\n\nbool OpenManipulatorDriver::read_goal_position(joint_position_info_t &position_info)\n{\n  bool ret = false;\n\n  if (is_ready() == false) return false;\n\n  sync_read_param.addr = 116;\n  sync_read_param.length = 4;\n  sync_read_param.id_count = JOINT_MOTOR_NUM_MAX;\n\n  if(dxl.syncRead(sync_read_param, read_result)){\n    for (int i=0; i<sync_read_param.id_count; i++) {\n      memcpy(&position_info.value[i], read_result.xel[i].data, read_result.xel[i].length);\n    }\n    ret = true;\n  }\n\n  return ret;\n}\n\nbool OpenManipulatorDriver::read_present_position(joint_position_info_t &position_info)\n{\n  bool ret = false;\n\n  if (is_ready() == false) return false;\n\n  sync_read_param.addr = 132;\n  sync_read_param.length = 4;\n  sync_read_param.id_count = JOINT_MOTOR_NUM_MAX;\n\n  if(dxl.syncRead(sync_read_param, read_result)){\n    for (int i=0; i<sync_read_param.id_count; i++) {\n      memcpy(&position_info.value[i], read_result.xel[i].data, read_result.xel[i].length);\n    }\n    ret = true;\n  }\n\n  return ret;\n}\n\nbool OpenManipulatorDriver::read_present_velocity(joint_velocity_info_t &velocity_info)\n{\n  bool ret = false;\n\n  if (is_ready() == false) return false;\n\n  sync_read_param.addr = 128;\n  sync_read_param.length = 4;\n  sync_read_param.id_count = JOINT_MOTOR_NUM_MAX;\n\n  if(dxl.syncRead(sync_read_param, read_result)){\n    for (int i=0; i<sync_read_param.id_count; i++) {\n      memcpy(&velocity_info.value[i], read_result.xel[i].data, read_result.xel[i].length);\n    }\n    ret = true;\n  }\n\n  return ret;\n}\n\nbool OpenManipulatorDriver::read_present_current(joint_current_info_t &current_info)\n{\n  bool ret = false;\n\n  if (is_ready() == false) return false;\n\n  sync_read_param.addr = 126;\n  sync_read_param.length = 2;\n  sync_read_param.id_count = JOINT_MOTOR_NUM_MAX;\n\n  if(dxl.syncRead(sync_read_param, read_result)){\n    for (int i=0; i<sync_read_param.id_count; i++) {\n      memcpy(&current_info.value[i], read_result.xel[i].data, read_result.xel[i].length);\n    }\n    ret = true;\n  }\n\n  return ret;\n}\n\nbool OpenManipulatorDriver::read_profile_acceleration(joint_accel_info_t &accel_info)\n{\n  bool ret = false;\n\n  if (is_ready() == false) return false;\n\n  sync_read_param.addr = 108;\n  sync_read_param.length = 4;\n  sync_read_param.id_count = JOINT_MOTOR_NUM_MAX;\n\n  if(dxl.syncRead(sync_read_param, read_result)){\n    for (int i=0; i<sync_read_param.id_count; i++) {\n      memcpy(&accel_info.value[i], read_result.xel[i].data, read_result.xel[i].length);\n    }\n    ret = true;\n  }\n\n  return ret;\n}\n\nbool OpenManipulatorDriver::read_profile_velocity(joint_accel_info_t &accel_info)\n{\n  bool ret = false;\n\n  if (is_ready() == false) return false;\n\n  sync_read_param.addr = 112;\n  sync_read_param.length = 4;\n  sync_read_param.id_count = JOINT_MOTOR_NUM_MAX;\n\n  if(dxl.syncRead(sync_read_param, read_result)){\n    for (int i=0; i<sync_read_param.id_count; i++) {\n      memcpy(&accel_info.value[i], read_result.xel[i].data, read_result.xel[i].length);\n    }\n    ret = true;\n  }\n\n  return ret;\n}\n\nbool OpenManipulatorDriver::read_goal_current(joint_current_info_t &current_info)\n{\n  bool ret = false;\n\n  if (is_ready() == false) return false;\n\n  sync_read_param.addr = 102;\n  sync_read_param.length = 2;\n  sync_read_param.id_count = JOINT_MOTOR_NUM_MAX;\n\n  if(dxl.syncRead(sync_read_param, read_result)){\n    for (int i=0; i<sync_read_param.id_count; i++) {\n      memcpy(&current_info.value[i], read_result.xel[i].data, read_result.xel[i].length);\n    }\n    ret = true;\n  }\n\n  return ret;\n}\n\nbool OpenManipulatorDriver::write_goal_position_joint(joint_position_info_t &position_info)\n{\n  bool ret = false;\n\n  if (is_ready() == false) return false;\n\n  sync_write_param.addr = 116;\n  sync_write_param.length = 4;\n  sync_write_param.id_count = JOINT_MOTOR_NUM_MAX - 1;\n\n  for (int i=0; i<sync_write_param.id_count; i++) {\n    memcpy(sync_write_param.xel[i].data, &position_info.value[i], sync_write_param.length);\n  }\n\n  if(dxl.syncWrite(sync_write_param)){\n    ret = true;\n  }\n\n  return ret;\n}\n\nbool OpenManipulatorDriver::write_profile_acceleration_joint(joint_accel_info_t &accel_info)\n{\n  bool ret = false;\n\n  if (is_ready() == false) return false;\n\n  sync_write_param.addr = 108;\n  sync_write_param.length = 4;\n  sync_write_param.id_count = JOINT_MOTOR_NUM_MAX - 1;\n\n  for (int i=0; i<sync_write_param.id_count; i++) {\n    memcpy(sync_write_param.xel[i].data, &accel_info.value[i], sync_write_param.length);\n  }\n\n  if(dxl.syncWrite(sync_write_param)){\n    ret = true;\n  }\n\n  return ret;\n}\n\nbool OpenManipulatorDriver::write_profile_velocity_joint(joint_accel_info_t &accel_info)\n{\n  bool ret = false;\n\n  if (is_ready() == false) return false;\n\n  sync_write_param.addr = 112;\n  sync_write_param.length = 4;\n  sync_write_param.id_count = JOINT_MOTOR_NUM_MAX - 1;\n\n  for (int i=0; i<sync_write_param.id_count; i++) {\n    memcpy(sync_write_param.xel[i].data, &accel_info.value[i], sync_write_param.length);\n  }\n\n  if(dxl.syncWrite(sync_write_param)){\n    ret = true;\n  }\n\n  return ret;\n}\n\nbool OpenManipulatorDriver::write_goal_current_joint(joint_current_info_t &current_info)\n{\n  bool ret = false;\n\n  if (is_ready() == false) return false;\n\n  sync_write_param.addr = 102;\n  sync_write_param.length = 2;\n  sync_write_param.id_count = JOINT_MOTOR_NUM_MAX - 1;\n\n  for (int i=0; i<sync_write_param.id_count; i++) {\n    memcpy(sync_write_param.xel[i].data, &current_info.value[i], sync_write_param.length);\n  }\n\n  if(dxl.syncWrite(sync_write_param)){\n    ret = true;\n  }\n\n  return ret;\n}\n\nbool OpenManipulatorDriver::write_goal_position_gripper(joint_position_info_t &position_info)\n{\n  bool ret = false;\n\n  if (is_ready() == false) return false;\n\n  ret = dxl.writeControlTableItem(ControlTableItem::GOAL_POSITION, motor_id_[GRIPPER], position_info.value[GRIPPER]);\n\n  return ret;\n}\n\nbool OpenManipulatorDriver::write_profile_acceleration_gripper(joint_accel_info_t &accel_info)\n{\n  bool ret = false;\n\n  if (is_ready() == false) return false;\n\n  ret = dxl.writeControlTableItem(ControlTableItem::PROFILE_ACCELERATION, motor_id_[GRIPPER], accel_info.value[GRIPPER]);\n\n  return ret;\n}\n\nbool OpenManipulatorDriver::write_profile_velocity_gripper(joint_accel_info_t &accel_info)\n{\n  bool ret = false;\n\n  if (is_ready() == false) return false;\n\n  ret = dxl.writeControlTableItem(ControlTableItem::PROFILE_VELOCITY, motor_id_[GRIPPER], accel_info.value[GRIPPER]);\n\n  return ret;\n}\n\nbool OpenManipulatorDriver::write_goal_current_gripper(joint_current_info_t &current_info)\n{\n  bool ret = false;\n\n  if (is_ready() == false) return false;\n\n  ret = dxl.writeControlTableItem(ControlTableItem::GOAL_CURRENT, motor_id_[GRIPPER], current_info.value[GRIPPER]);\n\n  return ret;\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros2/src/turtlebot3/turtlebot3.cpp",
    "content": "/*******************************************************************************\r\n* Copyright 2016 ROBOTIS CO., LTD.\r\n*\r\n* Licensed under the Apache License, Version 2.0 (the \"License\");\r\n* you may not use this file except in compliance with the License.\r\n* You may obtain a copy of the License at\r\n*\r\n*     http://www.apache.org/licenses/LICENSE-2.0\r\n*\r\n* Unless required by applicable law or agreed to in writing, software\r\n* distributed under the License is distributed on an \"AS IS\" BASIS,\r\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n* See the License for the specific language governing permissions and\r\n* limitations under the License.\r\n*******************************************************************************/\r\n\r\n#include \"../../include/turtlebot3/turtlebot3.h\"\r\n\r\n/*******************************************************************************\r\n* Definition of dependency data according to TB3 model.\r\n*******************************************************************************/\r\ntypedef struct TB3ModelInfo{\r\n  const char* model_str;\r\n  uint32_t model_info;\r\n  float wheel_radius;\r\n  float wheel_separation;\r\n  float turning_radius;\r\n  float robot_radius;\r\n  bool has_manipulator;\r\n} TB3ModelInfo;\r\n\r\nstatic const TB3ModelInfo burger_info = {\r\n  \"Burger\",\r\n  1,\r\n  0.033,\r\n  0.160,\r\n  0.080,\r\n  0.105,\r\n  false,\r\n};\r\n\r\nstatic const TB3ModelInfo waffle_info = {\r\n  \"Waffle\",\r\n  2,\r\n  0.033,\r\n  0.287,\r\n  0.1435,\r\n  0.220,\r\n  false,\r\n};\r\n\r\nstatic const TB3ModelInfo waffle_with_manipulator_info = {\r\n  \"Waffle_OpenManipulator\",\r\n  3,\r\n  0.033,\r\n  0.287,\r\n  0.1435,\r\n  0.220,\r\n  true,\r\n};\r\n\r\n\r\n/*******************************************************************************\r\n* Declaration for motors\r\n*******************************************************************************/\r\nstatic Turtlebot3MotorDriver motor_driver;\r\nstatic OpenManipulatorDriver manipulator_driver(motor_driver.getDxl());\r\n\r\nstatic const TB3ModelInfo* p_tb3_model_info;\r\nstatic float max_linear_velocity, min_linear_velocity;\r\nstatic float max_angular_velocity, min_angular_velocity;\r\n\r\nstatic float goal_velocity[VelocityType::TYPE_NUM_MAX] = {0.0, 0.0};\r\nstatic float goal_velocity_from_cmd[MortorLocation::MOTOR_NUM_MAX] = {0.0, 0.0};\r\nstatic float goal_velocity_from_rc100[MortorLocation::MOTOR_NUM_MAX] = {0.0, 0.0};\r\nstatic float goal_velocity_from_button[MortorLocation::MOTOR_NUM_MAX] = {0.0, 0.0};\r\n\r\nstatic void update_goal_velocity_from_3values(void);\r\nstatic void test_motors_with_buttons(uint8_t buttons);\r\nstatic bool get_connection_state_with_motors();\r\nstatic void set_connection_state_with_motors(bool is_connected);\r\nstatic bool get_connection_state_with_joints();\r\nstatic void set_connection_state_with_joints(bool is_connected);\r\n\r\n/*******************************************************************************\r\n* Declaration for sensors\r\n*******************************************************************************/\r\nstatic Turtlebot3Sensor sensors;\r\n\r\n/*******************************************************************************\r\n* Declaration for diagnosis\r\n*******************************************************************************/\r\nstatic Turtlebot3Diagnosis diagnosis;\r\n\r\n/*******************************************************************************\r\n* Declaration for controllers\r\n*******************************************************************************/\r\nstatic Turtlebot3Controller controllers;\r\n\r\n/*******************************************************************************\r\n* Declaration for DYNAMIXEL Slave Function\r\n*******************************************************************************/\r\n#define SERIAL_DXL_SLAVE Serial\r\nconst uint8_t ID_DXL_SLAVE = 200;\r\nconst uint16_t MODEL_NUM_DXL_SLAVE = 0x5000;\r\nconst float PROTOCOL_VERSION_DXL_SLAVE = 2.0;\r\nconst uint32_t HEARTBEAT_TIMEOUT_MS = 500;\r\n\r\nstatic void dxl_slave_write_callback_func(uint16_t addr, uint8_t &dxl_err_code, void* arg);\r\n\r\nstatic bool get_connection_state_with_ros2_node();\r\nstatic void set_connection_state_with_ros2_node(bool is_connected);\r\nstatic void update_connection_state_with_ros2_node();\r\n\r\nstatic void update_imu(uint32_t interval_ms);\r\nstatic void update_times(uint32_t interval_ms);\r\nstatic void update_gpios(uint32_t interval_ms);\r\nstatic void update_motor_status(uint32_t interval_ms);\r\nstatic void update_battery_status(uint32_t interval_ms);\r\nstatic void update_analog_sensors(uint32_t interval_ms);\r\nstatic void update_joint_status(uint32_t interval_ms);\r\n\r\n\r\nDYNAMIXEL::USBSerialPortHandler port_dxl_slave(SERIAL_DXL_SLAVE);\r\nDYNAMIXEL::Slave dxl_slave(port_dxl_slave, MODEL_NUM_DXL_SLAVE);\r\n\r\nenum ControlTableItemAddr{\r\n  ADDR_MODEL_INFORM    = 2,\r\n  \r\n  ADDR_MILLIS          = 10,\r\n\r\n  ADDR_DEBUG_MODE      = 14,  \r\n  ADDR_CONNECT_ROS2    = 15,\r\n  ADDR_CONNECT_MANIP   = 16,\r\n\r\n  ADDR_DEVICE_STATUS   = 18,\r\n  ADDR_HEARTBEAT       = 19,\r\n\r\n  ADDR_USER_LED_1      = 20,\r\n  ADDR_USER_LED_2      = 21,\r\n  ADDR_USER_LED_3      = 22,\r\n  ADDR_USER_LED_4      = 23,\r\n\r\n  ADDR_BUTTON_1        = 26,\r\n  ADDR_BUTTON_2        = 27,\r\n  ADDR_BUMPER_1        = 28,\r\n  ADDR_BUMPER_2        = 29,\r\n\r\n  ADDR_ILLUMINATION    = 30,\r\n  ADDR_IR              = 34,\r\n  ADDR_SORNA           = 38,\r\n\r\n  ADDR_BATTERY_VOLTAGE = 42,\r\n  ADDR_BATTERY_PERCENT = 46,\r\n\r\n  ADDR_SOUND           = 50,\r\n\r\n  ADDR_IMU_RECALIBRATION  = 59,\r\n  ADDR_ANGULAR_VELOCITY_X = 60,\r\n  ADDR_ANGULAR_VELOCITY_Y = 64,\r\n  ADDR_ANGULAR_VELOCITY_Z = 68,\r\n  ADDR_LINEAR_ACC_X       = 72,\r\n  ADDR_LINEAR_ACC_Y       = 76,\r\n  ADDR_LINEAR_ACC_Z       = 80,\r\n  ADDR_MAGNETIC_X         = 84,\r\n  ADDR_MAGNETIC_Y         = 88,\r\n  ADDR_MAGNETIC_Z         = 92,\r\n  ADDR_ORIENTATION_W      = 96,\r\n  ADDR_ORIENTATION_X      = 100,\r\n  ADDR_ORIENTATION_Y      = 104,\r\n  ADDR_ORIENTATION_Z      = 108,\r\n  \r\n  ADDR_PRESENT_CURRENT_L  = 120,\r\n  ADDR_PRESENT_CURRENT_R  = 124,\r\n  ADDR_PRESENT_VELOCITY_L = 128,\r\n  ADDR_PRESENT_VELOCITY_R = 132,\r\n  ADDR_PRESENT_POSITION_L = 136,\r\n  ADDR_PRESENT_POSITION_R = 140,\r\n  \r\n  ADDR_MOTOR_CONNECT      = 148,\r\n  ADDR_MOTOR_TORQUE       = 149,\r\n  ADDR_CMD_VEL_LINEAR_X   = 150,\r\n  ADDR_CMD_VEL_LINEAR_Y   = 154,\r\n  ADDR_CMD_VEL_LINEAR_Z   = 158,\r\n  ADDR_CMD_VEL_ANGULAR_X  = 162,\r\n  ADDR_CMD_VEL_ANGULAR_Y  = 166,\r\n  ADDR_CMD_VEL_ANGULAR_Z  = 170,\r\n  ADDR_PROFILE_ACC_L      = 174,\r\n  ADDR_PROFILE_ACC_R      = 178,\r\n\r\n  ADDR_TORQUE_JOINT             = 199,\r\n\r\n  ADDR_GOAL_POSITION_JOINT_1    = 200,\r\n  ADDR_GOAL_POSITION_JOINT_2    = 204,\r\n  ADDR_GOAL_POSITION_JOINT_3    = 208,\r\n  ADDR_GOAL_POSITION_JOINT_4    = 212,\r\n  ADDR_GOAL_POSITION_GRIPPER    = 216,\r\n  ADDR_GOAL_POSITION_WR_JOINT   = 220,\r\n  ADDR_GOAL_POSITION_WR_GRIPPER = 221,\r\n  ADDR_GOAL_POSITION_RD         = 222,\r\n\r\n  ADDR_PRESENT_POSITION_JOINT_1 = 224,\r\n  ADDR_PRESENT_POSITION_JOINT_2 = 228,\r\n  ADDR_PRESENT_POSITION_JOINT_3 = 232,\r\n  ADDR_PRESENT_POSITION_JOINT_4 = 236,\r\n  ADDR_PRESENT_POSITION_GRIPPER = 240,\r\n\r\n  ADDR_PRESENT_VELOCITY_JOINT_1 = 244,\r\n  ADDR_PRESENT_VELOCITY_JOINT_2 = 248,\r\n  ADDR_PRESENT_VELOCITY_JOINT_3 = 252,\r\n  ADDR_PRESENT_VELOCITY_JOINT_4 = 256,\r\n  ADDR_PRESENT_VELOCITY_GRIPPER = 260,\r\n\r\n  ADDR_PRESENT_CURRENT_JOINT_1  = 264,\r\n  ADDR_PRESENT_CURRENT_JOINT_2  = 266,\r\n  ADDR_PRESENT_CURRENT_JOINT_3  = 268,\r\n  ADDR_PRESENT_CURRENT_JOINT_4  = 270,\r\n  ADDR_PRESENT_CURRENT_GRIPPER  = 272,\r\n\r\n  ADDR_PROFILE_ACC_JOINT_1      = 284,\r\n  ADDR_PROFILE_ACC_JOINT_2      = 288,\r\n  ADDR_PROFILE_ACC_JOINT_3      = 292,\r\n  ADDR_PROFILE_ACC_JOINT_4      = 296,\r\n  ADDR_PROFILE_ACC_GRIPPER      = 300,\r\n  ADDR_PROFILE_ACC_WR_JOINT     = 304,\r\n  ADDR_PROFILE_ACC_WR_GRIPPER   = 305,\r\n  ADDR_PROFILE_ACC_RD           = 306,\r\n\r\n  ADDR_PROFILE_VEL_JOINT_1      = 308,\r\n  ADDR_PROFILE_VEL_JOINT_2      = 312,\r\n  ADDR_PROFILE_VEL_JOINT_3      = 316,\r\n  ADDR_PROFILE_VEL_JOINT_4      = 320,\r\n  ADDR_PROFILE_VEL_GRIPPER      = 324,\r\n  ADDR_PROFILE_VEL_WR_JOINT     = 328,\r\n  ADDR_PROFILE_VEL_WR_GRIPPER   = 329,\r\n  ADDR_PROFILE_VEL_RD           = 330,\r\n\r\n  ADDR_GOAL_CURRENT_JOINT_1     = 332,\r\n  ADDR_GOAL_CURRENT_JOINT_2     = 334,\r\n  ADDR_GOAL_CURRENT_JOINT_3     = 336,\r\n  ADDR_GOAL_CURRENT_JOINT_4     = 338,\r\n  ADDR_GOAL_CURRENT_GRIPPER     = 340,  \r\n  ADDR_GOAL_CURRENT_WR_JOINT    = 342,\r\n  ADDR_GOAL_CURRENT_WR_GRIPPER  = 343,\r\n  ADDR_GOAL_CURRENT_RD          = 344,\r\n\r\n};\r\n\r\ntypedef struct ControlItemVariables{\r\n  uint32_t model_inform;\r\n\r\n  uint32_t dev_time_millis;\r\n  uint32_t dev_time_micros;\r\n\r\n  int8_t device_status;\r\n  uint8_t heart_beat;\r\n  bool debug_mode;\r\n  bool is_connect_ros2_node;\r\n  bool is_connect_motors;\r\n  bool is_connect_manipulator;\r\n\r\n  bool user_led[4];\r\n  bool push_button[2];\r\n  bool bumper[2];\r\n\r\n  uint16_t illumination;\r\n  uint32_t ir_sensor;\r\n  float sornar;\r\n\r\n  uint32_t bat_voltage_x100;\r\n  uint32_t bat_percent_x100;\r\n\r\n  uint8_t buzzer_sound;\r\n\r\n  bool imu_recalibration;\r\n  float angular_vel[3];\r\n  float linear_acc[3];\r\n  float magnetic[3];\r\n  float orientation[4];\r\n\r\n  int32_t present_position[MortorLocation::MOTOR_NUM_MAX];\r\n  int32_t present_velocity[MortorLocation::MOTOR_NUM_MAX];\r\n  int32_t present_current[MortorLocation::MOTOR_NUM_MAX];\r\n\r\n  bool motor_torque_enable_state;\r\n  int32_t cmd_vel_linear[3];\r\n  int32_t cmd_vel_angular[3];\r\n  uint32_t profile_acceleration[MortorLocation::MOTOR_NUM_MAX];\r\n\r\n  bool joint_torque_enable_state;\r\n  joint_position_info_t joint_goal_position;  \r\n  joint_position_info_t joint_present_position;\r\n  joint_velocity_info_t joint_present_velocity;\r\n  joint_current_info_t joint_present_current;\r\n  joint_accel_info_t joint_profile_acc;\r\n  joint_accel_info_t joint_profile_vel;\r\n  joint_current_info_t joint_goal_current;\r\n\r\n  bool joint_goal_position_wr_joint;\r\n  bool joint_goal_position_wr_gripper;\r\n  bool joint_goal_position_rd;\r\n\r\n  bool joint_profile_acc_wr_joint;\r\n  bool joint_profile_acc_wr_gripper;\r\n  bool joint_profile_acc_rd;\r\n\r\n  bool joint_profile_vel_wr_joint;\r\n  bool joint_profile_vel_wr_gripper;\r\n  bool joint_profile_vel_rd;\r\n\r\n  bool joint_goal_current_wr_joint;\r\n  bool joint_goal_current_wr_gripper;\r\n  bool joint_goal_current_rd;\r\n\r\n}ControlItemVariables;\r\n\r\nstatic ControlItemVariables control_items;\r\n\r\n\r\n/*******************************************************************************\r\n* Definition for TurtleBot3Core 'begin()' function\r\n*******************************************************************************/\r\nvoid TurtleBot3Core::begin(const char* model_name)\r\n{\r\n  uint16_t model_motor_rpm;\r\n\r\n  if(strcmp(model_name, \"Burger\") == 0 || strcmp(model_name, \"burger\") == 0){\r\n    p_tb3_model_info = &burger_info;\r\n    model_motor_rpm = 61;\r\n  }else if(strcmp(model_name, \"Waffle\") == 0 || strcmp(model_name, \"waffle\") == 0){\r\n    p_tb3_model_info = &waffle_info;\r\n    model_motor_rpm = 77;\r\n  }else if(strcmp(model_name, \"Waffle_OpenManipulator\") == 0){\r\n    p_tb3_model_info = &waffle_with_manipulator_info;\r\n    model_motor_rpm = 77;\r\n  }else{\r\n    p_tb3_model_info = &burger_info;\r\n    model_motor_rpm = 61;\r\n  }\r\n\r\n  max_linear_velocity = p_tb3_model_info->wheel_radius*2*PI*model_motor_rpm/60;\r\n  min_linear_velocity = -max_linear_velocity;\r\n  max_angular_velocity = max_linear_velocity/p_tb3_model_info->turning_radius;\r\n  min_angular_velocity = -max_angular_velocity;\r\n\r\n  bool ret; (void)ret;\r\n  DEBUG_SERIAL_BEGIN(57600);\r\n  DEBUG_PRINTLN(\" \");\r\n  DEBUG_PRINTLN(\"Version : V221004R1\");\r\n  DEBUG_PRINTLN(\"Begin Start...\");\r\n\r\n  // Setting for Dynamixel motors\r\n  ret = motor_driver.init();\r\n  DEBUG_PRINTLN(ret==true?\"Motor driver setup completed.\":\"Motor driver setup failed.\");\r\n  // Setting for IMU\r\n  ret = sensors.init();\r\n  DEBUG_PRINTLN(ret==true?\"Sensors setup completed.\":\"Sensors setup failed.\");\r\n  // Init diagnosis\r\n  ret = diagnosis.init();\r\n  DEBUG_PRINTLN(ret==true?\"Diagnosis setup completed.\":\"Diagnosis setup failed.\");\r\n  // Setting for ROBOTIS RC100 remote controller and cmd_vel\r\n  ret = controllers.init(max_linear_velocity, max_angular_velocity);\r\n  DEBUG_PRINTLN(ret==true?\"RC100 Controller setup completed.\":\"RC100 Controller setup failed.\");\r\n\r\n  if (p_tb3_model_info->has_manipulator == true)\r\n  {    \r\n    ret = manipulator_driver.init();\r\n    DEBUG_PRINTLN(ret==true?\"Manipulator driver setup completed.\":\"Manipulator driver setup failed.\");\r\n  }\r\n\r\n  DEBUG_PRINT(\"Dynamixel2Arduino Item Max : \");\r\n  DEBUG_PRINTLN(CONTROL_ITEM_MAX);\r\n\r\n  control_items.debug_mode = false;\r\n  control_items.is_connect_ros2_node = false;\r\n  control_items.is_connect_manipulator = false;  \r\n\r\n  // Port begin\r\n  dxl_slave.begin();\r\n  // Init DXL Slave function\r\n  dxl_slave.setPortProtocolVersion(PROTOCOL_VERSION_DXL_SLAVE);\r\n  dxl_slave.setFirmwareVersion(FIRMWARE_VER);\r\n  dxl_slave.setID(ID_DXL_SLAVE);\r\n\r\n  /* Add control items for Slave */\r\n  // Items for model information of device\r\n  control_items.model_inform = p_tb3_model_info->model_info;\r\n  dxl_slave.addControlItem(ADDR_MODEL_INFORM, control_items.model_inform);\r\n  // Items for Timer of device\r\n  dxl_slave.addControlItem(ADDR_MILLIS, control_items.dev_time_millis);\r\n\r\n  // Items to debug mode\r\n  dxl_slave.addControlItem(ADDR_DEBUG_MODE, control_items.debug_mode);\r\n  // Items to connect ros2\r\n  dxl_slave.addControlItem(ADDR_CONNECT_ROS2, control_items.is_connect_ros2_node);\r\n  // Items to connect manipulator\r\n  dxl_slave.addControlItem(ADDR_CONNECT_MANIP, control_items.is_connect_manipulator);\r\n\r\n  // Items to inform device status\r\n  dxl_slave.addControlItem(ADDR_DEVICE_STATUS, control_items.device_status);\r\n  // Items to check connection state with node\r\n  dxl_slave.addControlItem(ADDR_HEARTBEAT, control_items.heart_beat);\r\n  // Items for GPIO\r\n  dxl_slave.addControlItem(ADDR_USER_LED_1, control_items.user_led[0]);\r\n  dxl_slave.addControlItem(ADDR_USER_LED_2, control_items.user_led[1]);\r\n  dxl_slave.addControlItem(ADDR_USER_LED_3, control_items.user_led[2]);\r\n  dxl_slave.addControlItem(ADDR_USER_LED_4, control_items.user_led[3]);\r\n  dxl_slave.addControlItem(ADDR_BUTTON_1, control_items.push_button[0]);\r\n  dxl_slave.addControlItem(ADDR_BUTTON_2, control_items.push_button[1]);\r\n  dxl_slave.addControlItem(ADDR_BUMPER_1, control_items.bumper[0]);\r\n  dxl_slave.addControlItem(ADDR_BUMPER_2, control_items.bumper[1]);\r\n  // Items for Analog sensors\r\n  dxl_slave.addControlItem(ADDR_ILLUMINATION, control_items.illumination);\r\n  dxl_slave.addControlItem(ADDR_IR, control_items.ir_sensor);\r\n  dxl_slave.addControlItem(ADDR_SORNA, control_items.sornar);\r\n  // Items for Battery\r\n  dxl_slave.addControlItem(ADDR_BATTERY_VOLTAGE, control_items.bat_voltage_x100);\r\n  dxl_slave.addControlItem(ADDR_BATTERY_PERCENT, control_items.bat_percent_x100);\r\n  // Items for Buzzer\r\n  dxl_slave.addControlItem(ADDR_SOUND, control_items.buzzer_sound);\r\n  // Items for IMU\r\n  dxl_slave.addControlItem(ADDR_IMU_RECALIBRATION, control_items.imu_recalibration);\r\n  dxl_slave.addControlItem(ADDR_ANGULAR_VELOCITY_X, control_items.angular_vel[0]);\r\n  dxl_slave.addControlItem(ADDR_ANGULAR_VELOCITY_Y, control_items.angular_vel[1]);\r\n  dxl_slave.addControlItem(ADDR_ANGULAR_VELOCITY_Z, control_items.angular_vel[2]);\r\n  dxl_slave.addControlItem(ADDR_LINEAR_ACC_X, control_items.linear_acc[0]);\r\n  dxl_slave.addControlItem(ADDR_LINEAR_ACC_Y, control_items.linear_acc[1]);\r\n  dxl_slave.addControlItem(ADDR_LINEAR_ACC_Z, control_items.linear_acc[2]);\r\n  dxl_slave.addControlItem(ADDR_MAGNETIC_X, control_items.magnetic[0]);\r\n  dxl_slave.addControlItem(ADDR_MAGNETIC_Y, control_items.magnetic[1]);\r\n  dxl_slave.addControlItem(ADDR_MAGNETIC_Z, control_items.magnetic[2]);\r\n  dxl_slave.addControlItem(ADDR_ORIENTATION_W, control_items.orientation[0]);\r\n  dxl_slave.addControlItem(ADDR_ORIENTATION_X, control_items.orientation[1]);\r\n  dxl_slave.addControlItem(ADDR_ORIENTATION_Y, control_items.orientation[2]);\r\n  dxl_slave.addControlItem(ADDR_ORIENTATION_Z, control_items.orientation[3]);\r\n  // Items to check status of motors\r\n  dxl_slave.addControlItem(ADDR_PRESENT_POSITION_L, control_items.present_position[MortorLocation::LEFT]);\r\n  dxl_slave.addControlItem(ADDR_PRESENT_POSITION_R, control_items.present_position[MortorLocation::RIGHT]);\r\n  dxl_slave.addControlItem(ADDR_PRESENT_VELOCITY_L, control_items.present_velocity[MortorLocation::LEFT]);\r\n  dxl_slave.addControlItem(ADDR_PRESENT_VELOCITY_R, control_items.present_velocity[MortorLocation::RIGHT]);\r\n  dxl_slave.addControlItem(ADDR_PRESENT_CURRENT_L, control_items.present_current[MortorLocation::LEFT]);\r\n  dxl_slave.addControlItem(ADDR_PRESENT_CURRENT_R, control_items.present_current[MortorLocation::RIGHT]);\r\n  // Items to control motors\r\n  dxl_slave.addControlItem(ADDR_MOTOR_CONNECT, control_items.is_connect_motors);\r\n  dxl_slave.addControlItem(ADDR_MOTOR_TORQUE, control_items.motor_torque_enable_state);\r\n  dxl_slave.addControlItem(ADDR_CMD_VEL_LINEAR_X, control_items.cmd_vel_linear[0]);\r\n  dxl_slave.addControlItem(ADDR_CMD_VEL_LINEAR_Y, control_items.cmd_vel_linear[1]);\r\n  dxl_slave.addControlItem(ADDR_CMD_VEL_LINEAR_Z, control_items.cmd_vel_linear[2]);\r\n  dxl_slave.addControlItem(ADDR_CMD_VEL_ANGULAR_X, control_items.cmd_vel_angular[0]);\r\n  dxl_slave.addControlItem(ADDR_CMD_VEL_ANGULAR_Y, control_items.cmd_vel_angular[1]);\r\n  dxl_slave.addControlItem(ADDR_CMD_VEL_ANGULAR_Z, control_items.cmd_vel_angular[2]);  \r\n  dxl_slave.addControlItem(ADDR_PROFILE_ACC_L, control_items.profile_acceleration[MortorLocation::LEFT]);\r\n  dxl_slave.addControlItem(ADDR_PROFILE_ACC_R, control_items.profile_acceleration[MortorLocation::RIGHT]);\r\n\r\n  if (p_tb3_model_info->has_manipulator == true) {\r\n    control_items.joint_goal_position_wr_joint = false;\r\n    control_items.joint_goal_position_wr_gripper = false;\r\n    control_items.joint_goal_position_rd = false;\r\n    control_items.joint_profile_acc_wr_joint = false;\r\n    control_items.joint_profile_acc_wr_gripper = false;\r\n    control_items.joint_profile_acc_rd = false;\r\n    control_items.joint_profile_vel_wr_joint = false;\r\n    control_items.joint_profile_vel_wr_gripper = false;\r\n    control_items.joint_profile_vel_rd = false;\r\n    control_items.joint_goal_current_wr_joint = false;\r\n    control_items.joint_goal_current_wr_gripper = false;\r\n    control_items.joint_goal_current_rd = false;\r\n\r\n    // Items to joint motors\r\n    dxl_slave.addControlItem(ADDR_TORQUE_JOINT, control_items.joint_torque_enable_state);\r\n\r\n    dxl_slave.addControlItem(ADDR_GOAL_POSITION_JOINT_1, control_items.joint_goal_position.value[JOINT_1]);\r\n    dxl_slave.addControlItem(ADDR_GOAL_POSITION_JOINT_2, control_items.joint_goal_position.value[JOINT_2]);\r\n    dxl_slave.addControlItem(ADDR_GOAL_POSITION_JOINT_3, control_items.joint_goal_position.value[JOINT_3]);\r\n    dxl_slave.addControlItem(ADDR_GOAL_POSITION_JOINT_4, control_items.joint_goal_position.value[JOINT_4]);\r\n    dxl_slave.addControlItem(ADDR_GOAL_POSITION_GRIPPER, control_items.joint_goal_position.value[GRIPPER]);\r\n    dxl_slave.addControlItem(ADDR_GOAL_POSITION_WR_JOINT, control_items.joint_goal_position_wr_joint);\r\n    dxl_slave.addControlItem(ADDR_GOAL_POSITION_WR_GRIPPER, control_items.joint_goal_position_wr_gripper);\r\n    dxl_slave.addControlItem(ADDR_GOAL_POSITION_RD, control_items.joint_goal_position_rd);\r\n\r\n    dxl_slave.addControlItem(ADDR_PRESENT_POSITION_JOINT_1, control_items.joint_present_position.value[JOINT_1]);\r\n    dxl_slave.addControlItem(ADDR_PRESENT_POSITION_JOINT_2, control_items.joint_present_position.value[JOINT_2]);\r\n    dxl_slave.addControlItem(ADDR_PRESENT_POSITION_JOINT_3, control_items.joint_present_position.value[JOINT_3]);\r\n    dxl_slave.addControlItem(ADDR_PRESENT_POSITION_JOINT_4, control_items.joint_present_position.value[JOINT_4]);\r\n    dxl_slave.addControlItem(ADDR_PRESENT_POSITION_GRIPPER, control_items.joint_present_position.value[GRIPPER]);\r\n\r\n    dxl_slave.addControlItem(ADDR_PRESENT_VELOCITY_JOINT_1, control_items.joint_present_velocity.value[JOINT_1]);\r\n    dxl_slave.addControlItem(ADDR_PRESENT_VELOCITY_JOINT_2, control_items.joint_present_velocity.value[JOINT_2]);\r\n    dxl_slave.addControlItem(ADDR_PRESENT_VELOCITY_JOINT_3, control_items.joint_present_velocity.value[JOINT_3]);\r\n    dxl_slave.addControlItem(ADDR_PRESENT_VELOCITY_JOINT_4, control_items.joint_present_velocity.value[JOINT_4]);\r\n    dxl_slave.addControlItem(ADDR_PRESENT_VELOCITY_GRIPPER, control_items.joint_present_velocity.value[GRIPPER]);\r\n\r\n    dxl_slave.addControlItem(ADDR_PRESENT_CURRENT_JOINT_1, control_items.joint_present_current.value[JOINT_1]);\r\n    dxl_slave.addControlItem(ADDR_PRESENT_CURRENT_JOINT_2, control_items.joint_present_current.value[JOINT_2]);\r\n    dxl_slave.addControlItem(ADDR_PRESENT_CURRENT_JOINT_3, control_items.joint_present_current.value[JOINT_3]);\r\n    dxl_slave.addControlItem(ADDR_PRESENT_CURRENT_JOINT_4, control_items.joint_present_current.value[JOINT_4]);\r\n    dxl_slave.addControlItem(ADDR_PRESENT_CURRENT_GRIPPER, control_items.joint_present_current.value[GRIPPER]);\r\n\r\n    dxl_slave.addControlItem(ADDR_PROFILE_ACC_JOINT_1, control_items.joint_profile_acc.value[JOINT_1]);\r\n    dxl_slave.addControlItem(ADDR_PROFILE_ACC_JOINT_2, control_items.joint_profile_acc.value[JOINT_2]);\r\n    dxl_slave.addControlItem(ADDR_PROFILE_ACC_JOINT_3, control_items.joint_profile_acc.value[JOINT_3]);\r\n    dxl_slave.addControlItem(ADDR_PROFILE_ACC_JOINT_4, control_items.joint_profile_acc.value[JOINT_4]);\r\n    dxl_slave.addControlItem(ADDR_PROFILE_ACC_GRIPPER, control_items.joint_profile_acc.value[GRIPPER]);\r\n    dxl_slave.addControlItem(ADDR_PROFILE_ACC_WR_JOINT, control_items.joint_profile_acc_wr_joint);\r\n    dxl_slave.addControlItem(ADDR_PROFILE_ACC_WR_GRIPPER, control_items.joint_profile_acc_wr_gripper);\r\n    dxl_slave.addControlItem(ADDR_PROFILE_ACC_RD, control_items.joint_profile_acc_rd);\r\n\r\n    dxl_slave.addControlItem(ADDR_PROFILE_VEL_JOINT_1, control_items.joint_profile_vel.value[JOINT_1]);\r\n    dxl_slave.addControlItem(ADDR_PROFILE_VEL_JOINT_2, control_items.joint_profile_vel.value[JOINT_2]);\r\n    dxl_slave.addControlItem(ADDR_PROFILE_VEL_JOINT_3, control_items.joint_profile_vel.value[JOINT_3]);\r\n    dxl_slave.addControlItem(ADDR_PROFILE_VEL_JOINT_4, control_items.joint_profile_vel.value[JOINT_4]);\r\n    dxl_slave.addControlItem(ADDR_PROFILE_VEL_GRIPPER, control_items.joint_profile_vel.value[GRIPPER]);\r\n    dxl_slave.addControlItem(ADDR_PROFILE_VEL_WR_JOINT, control_items.joint_profile_vel_wr_joint);\r\n    dxl_slave.addControlItem(ADDR_PROFILE_VEL_WR_GRIPPER, control_items.joint_profile_vel_wr_gripper);\r\n    dxl_slave.addControlItem(ADDR_PROFILE_VEL_RD, control_items.joint_profile_vel_rd);\r\n\r\n    dxl_slave.addControlItem(ADDR_GOAL_CURRENT_JOINT_1, control_items.joint_goal_current.value[JOINT_1]);\r\n    dxl_slave.addControlItem(ADDR_GOAL_CURRENT_JOINT_2, control_items.joint_goal_current.value[JOINT_2]);\r\n    dxl_slave.addControlItem(ADDR_GOAL_CURRENT_JOINT_3, control_items.joint_goal_current.value[JOINT_3]);\r\n    dxl_slave.addControlItem(ADDR_GOAL_CURRENT_JOINT_4, control_items.joint_goal_current.value[JOINT_4]);\r\n    dxl_slave.addControlItem(ADDR_GOAL_CURRENT_GRIPPER, control_items.joint_goal_current.value[GRIPPER]);\r\n    dxl_slave.addControlItem(ADDR_GOAL_CURRENT_WR_JOINT, control_items.joint_goal_current_wr_joint);\r\n    dxl_slave.addControlItem(ADDR_GOAL_CURRENT_WR_GRIPPER, control_items.joint_goal_current_wr_gripper);\r\n    dxl_slave.addControlItem(ADDR_GOAL_CURRENT_RD, control_items.joint_goal_current_rd);    \r\n  }\r\n\r\n  // Set user callback function for processing write command from master.\r\n  dxl_slave.setWriteCallbackFunc(dxl_slave_write_callback_func);\r\n\r\n  // Check connection state with motors.\r\n  if(motor_driver.is_connected() == true){\r\n    motor_driver.set_torque(true);\r\n    control_items.device_status = STATUS_RUNNING;\r\n    set_connection_state_with_motors(true);\r\n    DEBUG_PRINTLN(\"Wheel motors are connected\");\r\n  }else{\r\n    control_items.device_status = STATUS_NOT_CONNECTED_MOTORS;\r\n    set_connection_state_with_motors(false);\r\n    DEBUG_PRINTLN(\"Can't communicate with the motor!\");\r\n    DEBUG_PRINTLN(\"  Please check the connection to the motor and the power supply.\");\r\n    DEBUG_PRINTLN();\r\n  } \r\n  control_items.is_connect_motors = get_connection_state_with_motors();  \r\n\r\n  if (p_tb3_model_info->has_manipulator == true) {\r\n    // Check connection state with joints.\r\n    if(manipulator_driver.is_connected() == true){\r\n      manipulator_driver.set_torque(true);    \r\n      control_items.is_connect_manipulator = true;\r\n      set_connection_state_with_joints(true);\r\n      DEBUG_PRINTLN(\"Joint motors are connected\");      \r\n    }else{\r\n      control_items.is_connect_manipulator = false;\r\n      set_connection_state_with_joints(false);\r\n      DEBUG_PRINTLN(\"Can't communicate with the joint!\");\r\n      DEBUG_PRINTLN(\"  Please check the connection to the joint motor and the power supply.\");\r\n      DEBUG_PRINTLN();\r\n    } \r\n  }\r\n\r\n  // Init IMU \r\n  sensors.initIMU();\r\n  sensors.calibrationGyro();\r\n\r\n  //To indicate that the initialization is complete.\r\n  sensors.makeMelody(1); \r\n\r\n  DEBUG_PRINTLN(\"Begin End...\");\r\n}\r\n\r\n/*******************************************************************************\r\n* Definition for TurtleBot3Core 'run()' function\r\n*******************************************************************************/\r\nvoid TurtleBot3Core::run()\r\n{\r\n  static uint32_t pre_time_to_control_motor;\r\n\r\n  // Check connection state with ROS2 node\r\n  update_connection_state_with_ros2_node();\r\n\r\n  /* For diagnosis */\r\n  // Show LED status\r\n  diagnosis.showLedStatus(get_connection_state_with_ros2_node());\r\n  // Update Voltage\r\n  diagnosis.updateVoltageCheck(true);\r\n  // Check push button pressed for simple test drive\r\n  test_motors_with_buttons(diagnosis.getButtonPress(3000));\r\n\r\n  /* For sensing and run buzzer */\r\n  // Update the IMU unit\r\n  sensors.updateIMU();\r\n  // Update sonar data\r\n  // TODO: sensors.updateSonar(t);\r\n  // Run buzzer if there is still melody to play.\r\n  sensors.onMelody();\r\n\r\n  /* For getting command from rc100 */\r\n  // Receive data from RC100 \r\n  controllers.getRCdata(goal_velocity_from_rc100);\r\n\r\n  /* For processing DYNAMIXEL slave function */\r\n  // Update control table of OpenCR to communicate with ROS2 node\r\n  update_imu(INTERVAL_MS_TO_UPDATE_CONTROL_ITEM);\r\n  update_times(INTERVAL_MS_TO_UPDATE_CONTROL_ITEM);\r\n  update_gpios(INTERVAL_MS_TO_UPDATE_CONTROL_ITEM);\r\n  update_motor_status(INTERVAL_MS_TO_UPDATE_CONTROL_ITEM);\r\n  update_battery_status(INTERVAL_MS_TO_UPDATE_CONTROL_ITEM);\r\n  update_analog_sensors(INTERVAL_MS_TO_UPDATE_CONTROL_ITEM);\r\n  update_joint_status(INTERVAL_MS_TO_UPDATE_CONTROL_ITEM);\r\n\r\n  // Packet processing with ROS2 Node.\r\n  dxl_slave.processPacket();\r\n\r\n  /* For controlling DYNAMIXEL motors (Wheels) */  \r\n  if (millis()-pre_time_to_control_motor >= INTERVAL_MS_TO_CONTROL_MOTOR)\r\n  {\r\n    pre_time_to_control_motor = millis();\r\n    if(get_connection_state_with_ros2_node() == false){\r\n      memset(goal_velocity_from_cmd, 0, sizeof(goal_velocity_from_cmd));\r\n    }\r\n    update_goal_velocity_from_3values();\r\n    if(get_connection_state_with_motors() == true){\r\n      motor_driver.control_motors(p_tb3_model_info->wheel_separation, goal_velocity[VelocityType::LINEAR], goal_velocity[VelocityType::ANGULAR]);\r\n    }\r\n  }  \r\n}\r\n\r\n\r\n/*******************************************************************************\r\n* Function definition for updating velocity values \r\n* to be used for control of DYNAMIXEL(motors).\r\n*******************************************************************************/\r\nvoid update_goal_velocity_from_3values(void)\r\n{\r\n  goal_velocity[VelocityType::LINEAR]  = goal_velocity_from_button[VelocityType::LINEAR]  + goal_velocity_from_cmd[VelocityType::LINEAR]  + goal_velocity_from_rc100[VelocityType::LINEAR];\r\n  goal_velocity[VelocityType::ANGULAR] = goal_velocity_from_button[VelocityType::ANGULAR] + goal_velocity_from_cmd[VelocityType::ANGULAR] + goal_velocity_from_rc100[VelocityType::ANGULAR];\r\n\r\n  sensors.setLedPattern(goal_velocity[VelocityType::LINEAR], goal_velocity[VelocityType::ANGULAR]);\r\n}\r\n\r\n\r\n/*******************************************************************************\r\n* Function definition for updating control items in TB3.\r\n*******************************************************************************/\r\nfloat map_float(float x, float in_min, float in_max, float out_min, float out_max)\r\n{\r\n  return (x - in_min) * (out_max - out_min) / (in_max - in_min) + out_min;\r\n}\r\n\r\nvoid update_times(uint32_t interval_ms)\r\n{\r\n  static uint32_t pre_time = 0;\r\n\r\n  if(millis() - pre_time >= interval_ms){\r\n    pre_time = millis();\r\n\r\n    control_items.dev_time_millis = millis();\r\n    control_items.dev_time_micros = micros();\r\n  } \r\n}\r\n\r\nvoid update_gpios(uint32_t interval_ms)\r\n{\r\n  static uint32_t pre_time = 0;\r\n\r\n  if(millis() - pre_time >= interval_ms){\r\n    pre_time = millis();\r\n\r\n    control_items.user_led[0] = digitalRead(BDPIN_GPIO_4);\r\n    control_items.user_led[1] = digitalRead(BDPIN_GPIO_6);\r\n    control_items.user_led[2] = digitalRead(BDPIN_GPIO_8);\r\n    control_items.user_led[3] = digitalRead(BDPIN_GPIO_10);\r\n\r\n    control_items.push_button[0] = digitalRead(BDPIN_PUSH_SW_1);\r\n    control_items.push_button[1] = digitalRead(BDPIN_PUSH_SW_2);\r\n\r\n    control_items.bumper[0] = sensors.getBumper1State();\r\n    control_items.bumper[1] = sensors.getBumper2State();\r\n  }  \r\n}\r\n\r\nvoid update_battery_status(uint32_t interval_ms)\r\n{\r\n  static uint32_t pre_time = 0;\r\n  float bat_voltage, bat_percent;\r\n\r\n  if(millis() - pre_time >= interval_ms){\r\n    pre_time = millis();\r\n\r\n    bat_voltage = sensors.checkVoltage();\r\n    control_items.bat_voltage_x100 = (uint32_t)(bat_voltage*100);\r\n\r\n    if(bat_voltage >= 3.5*3){\r\n      bat_percent = map_float(bat_voltage, 3.5*3, 4.1*3, 0.0, 100.0);\r\n      control_items.bat_percent_x100 = (uint32_t)(bat_percent*100);\r\n    }\r\n  }\r\n}\r\n\r\nvoid update_analog_sensors(uint32_t interval_ms)\r\n{\r\n  static uint32_t pre_time = 0;\r\n\r\n  if(millis() - pre_time >= interval_ms){\r\n    pre_time = millis();\r\n\r\n    control_items.illumination = (uint16_t)sensors.getIlluminationData();\r\n    control_items.ir_sensor = (uint32_t)sensors.getIRsensorData();\r\n    control_items.sornar = (float)sensors.getSonarData();\r\n  }\r\n}\r\n\r\nvoid update_imu(uint32_t interval_ms)\r\n{\r\n  static uint32_t pre_time = 0;\r\n  float* p_imu_data;\r\n\r\n  if(millis() - pre_time >= interval_ms){\r\n    pre_time = millis();\r\n\r\n    p_imu_data = sensors.getImuAngularVelocity();\r\n    memcpy(control_items.angular_vel, p_imu_data, sizeof(control_items.angular_vel));\r\n\r\n    p_imu_data = sensors.getImuLinearAcc();\r\n    memcpy(control_items.linear_acc, p_imu_data, sizeof(control_items.linear_acc));\r\n\r\n    p_imu_data = sensors.getImuMagnetic();\r\n    memcpy(control_items.magnetic, p_imu_data, sizeof(control_items.magnetic));\r\n\r\n    p_imu_data = sensors.getOrientation();\r\n    memcpy(control_items.orientation, p_imu_data, sizeof(control_items.orientation));\r\n  }  \r\n}\r\n\r\nvoid update_motor_status(uint32_t interval_ms)\r\n{\r\n  static uint32_t pre_time;\r\n  int16_t current_l, current_r;\r\n\r\n  if(millis() - pre_time >= interval_ms){\r\n    pre_time = millis();\r\n\r\n\r\n    uint32_t pre_time_dxl;\r\n\r\n    pre_time_dxl = millis();\r\n    if(get_connection_state_with_motors() == true){\r\n      motor_driver.read_present_position(control_items.present_position[MortorLocation::LEFT], control_items.present_position[MortorLocation::RIGHT]);\r\n      motor_driver.read_present_velocity(control_items.present_velocity[MortorLocation::LEFT], control_items.present_velocity[MortorLocation::RIGHT]);\r\n      if(motor_driver.read_present_current(current_l, current_r) == true){\r\n        control_items.present_current[MortorLocation::LEFT] = current_l;\r\n        control_items.present_current[MortorLocation::RIGHT] = current_r;\r\n      }\r\n\r\n      control_items.motor_torque_enable_state = motor_driver.get_torque();\r\n    }\r\n  }  \r\n}\r\n\r\nvoid update_joint_status(uint32_t interval_ms)\r\n{\r\n  static uint32_t pre_time;\r\n\r\n  if(millis() - pre_time >= interval_ms){\r\n    pre_time = millis();\r\n\r\n    manipulator_driver.read_present_position(control_items.joint_present_position);\r\n    manipulator_driver.read_present_velocity(control_items.joint_present_velocity);\r\n    manipulator_driver.read_present_current(control_items.joint_present_current);\r\n\r\n    if(get_connection_state_with_joints() == true){\r\n\r\n      control_items.joint_torque_enable_state = manipulator_driver.get_torque();\r\n    }\r\n  }  \r\n}\r\n\r\n/*******************************************************************************\r\n* Callback function definition to be used in communication with the ROS2 node.\r\n*******************************************************************************/\r\nstatic void dxl_slave_write_callback_func(uint16_t item_addr, uint8_t &dxl_err_code, void* arg)\r\n{\r\n  (void)arg;\r\n\r\n  switch(item_addr)\r\n  {\r\n    case ADDR_MODEL_INFORM:\r\n      control_items.model_inform = p_tb3_model_info->model_info;\r\n      dxl_err_code = DXL_ERR_ACCESS;\r\n      break;\r\n\r\n    case ADDR_DEBUG_MODE:\r\n      if (control_items.debug_mode == true)\r\n        DEBUG_PRINTLN(\"Debug Mode : Enabled\");\r\n      else\r\n        DEBUG_PRINTLN(\"Debug Mode : Disabled\");\r\n      break;\r\n\r\n    case ADDR_SOUND:\r\n      sensors.makeMelody(control_items.buzzer_sound);\r\n      break;\r\n\r\n    case ADDR_IMU_RECALIBRATION:\r\n      if(control_items.imu_recalibration == true){\r\n        sensors.calibrationGyro();\r\n        control_items.imu_recalibration = false;\r\n      }\r\n      break;\r\n\r\n    case ADDR_MOTOR_TORQUE:\r\n      if(get_connection_state_with_motors() == true)\r\n        motor_driver.set_torque(control_items.motor_torque_enable_state);\r\n      break;\r\n\r\n    case ADDR_CMD_VEL_LINEAR_X:\r\n      goal_velocity_from_cmd[VelocityType::LINEAR] = constrain((float)(control_items.cmd_vel_linear[0]*0.01f), min_linear_velocity, max_linear_velocity);\r\n      break;\r\n\r\n    case ADDR_CMD_VEL_ANGULAR_Z:\r\n      goal_velocity_from_cmd[VelocityType::ANGULAR] = constrain((float)(control_items.cmd_vel_angular[2]*0.01f), min_angular_velocity, max_angular_velocity);\r\n      break;            \r\n\r\n    case ADDR_PROFILE_ACC_L:\r\n    case ADDR_PROFILE_ACC_R:\r\n      if(get_connection_state_with_motors() == true)\r\n        motor_driver.write_profile_acceleration(control_items.profile_acceleration[MortorLocation::LEFT], control_items.profile_acceleration[MortorLocation::RIGHT]);\r\n      break;\r\n\r\n    case ADDR_TORQUE_JOINT:\r\n      manipulator_driver.set_torque(control_items.joint_torque_enable_state);\r\n      break;\r\n\r\n    // ADDR_GOAL_POSITION\r\n    //\r\n    case ADDR_GOAL_POSITION_WR_JOINT:\r\n      if (get_connection_state_with_ros2_node() == true && control_items.joint_goal_position_wr_joint == true) {\r\n        manipulator_driver.write_goal_position_joint(control_items.joint_goal_position);\r\n      }\r\n      control_items.joint_goal_position_wr_joint = false;\r\n      break;\r\n\r\n    case ADDR_GOAL_POSITION_WR_GRIPPER:\r\n      if (get_connection_state_with_ros2_node() == true && control_items.joint_goal_position_wr_gripper == true) {\r\n        manipulator_driver.write_goal_position_gripper(control_items.joint_goal_position);\r\n      }\r\n      control_items.joint_goal_position_wr_gripper = false;\r\n      break;\r\n\r\n    case ADDR_GOAL_POSITION_RD:\r\n      if (control_items.joint_goal_position_rd == true) {\r\n        manipulator_driver.read_goal_position(control_items.joint_goal_position);\r\n      }\r\n      control_items.joint_goal_position_rd = false;\r\n      break;\r\n\r\n    // ADDR_PROFILE_ACC\r\n    //\r\n    case ADDR_PROFILE_ACC_WR_JOINT:\r\n      if (get_connection_state_with_ros2_node() == true && control_items.joint_profile_acc_wr_joint == true) {\r\n        manipulator_driver.write_profile_acceleration_joint(control_items.joint_profile_acc);\r\n      }\r\n      control_items.joint_profile_acc_wr_joint = false;\r\n      break;      \r\n\r\n    case ADDR_PROFILE_ACC_WR_GRIPPER:\r\n      if (get_connection_state_with_ros2_node() == true && control_items.joint_profile_acc_wr_gripper == true) {\r\n        manipulator_driver.write_profile_acceleration_gripper(control_items.joint_profile_acc);\r\n      }\r\n      control_items.joint_profile_acc_wr_joint = false;\r\n      break;      \r\n\r\n    case ADDR_PROFILE_ACC_RD:\r\n      if (control_items.joint_profile_acc_rd == true) {\r\n        manipulator_driver.read_profile_acceleration(control_items.joint_profile_acc);\r\n      }\r\n      control_items.joint_profile_acc_rd = false;\r\n      break;     \r\n\r\n    // ADDR_PROFILE_VEL\r\n    //\r\n    case ADDR_PROFILE_VEL_WR_JOINT:\r\n      if (get_connection_state_with_ros2_node() == true && control_items.joint_profile_vel_wr_joint == true) {\r\n        manipulator_driver.write_profile_velocity_joint(control_items.joint_profile_vel);\r\n      }\r\n      control_items.joint_profile_vel_wr_joint = false;\r\n      break;      \r\n\r\n    case ADDR_PROFILE_VEL_WR_GRIPPER:\r\n      if (get_connection_state_with_ros2_node() == true && control_items.joint_profile_vel_wr_gripper == true) {\r\n        manipulator_driver.write_profile_velocity_gripper(control_items.joint_profile_vel);\r\n      }\r\n      control_items.joint_profile_vel_wr_gripper = false;\r\n      break;   \r\n\r\n    case ADDR_PROFILE_VEL_RD:\r\n      if (control_items.joint_profile_vel_rd == true) {\r\n        manipulator_driver.read_profile_velocity(control_items.joint_profile_vel);\r\n      }\r\n      control_items.joint_profile_vel_rd = false;\r\n      break;      \r\n\r\n    // ADDR_GOAL_CURRENT\r\n    //\r\n    case ADDR_GOAL_CURRENT_WR_JOINT:\r\n      if (get_connection_state_with_ros2_node() == true && control_items.joint_goal_current_wr_joint == true) {\r\n        manipulator_driver.write_goal_current_joint(control_items.joint_goal_current);\r\n      }\r\n      control_items.joint_goal_current_wr_joint = false;\r\n      break;      \r\n\r\n    case ADDR_GOAL_CURRENT_WR_GRIPPER:\r\n      if (get_connection_state_with_ros2_node() == true && control_items.joint_goal_current_wr_gripper == true) {\r\n        manipulator_driver.write_goal_current_gripper(control_items.joint_goal_current);\r\n      }\r\n      control_items.joint_goal_current_wr_gripper = false;\r\n      break;   \r\n\r\n    case ADDR_GOAL_CURRENT_RD:\r\n      if (control_items.joint_goal_current_rd == true) {\r\n        manipulator_driver.read_goal_current(control_items.joint_goal_current);\r\n      }\r\n      control_items.joint_goal_current_rd = false;\r\n      break;        \r\n  }\r\n}\r\n\r\n\r\n/*******************************************************************************\r\n* Function definition to check the connection status with the ROS2 node.\r\n*******************************************************************************/\r\nstatic bool connection_state_with_ros2_node = false;\r\n\r\nstatic bool get_connection_state_with_ros2_node()\r\n{\r\n  return connection_state_with_ros2_node;\r\n}\r\n\r\nstatic void set_connection_state_with_ros2_node(bool is_connected)\r\n{\r\n  connection_state_with_ros2_node = is_connected;\r\n}\r\n\r\nvoid update_connection_state_with_ros2_node()\r\n{\r\n  static uint32_t pre_time;\r\n  static uint8_t pre_data;\r\n  static bool pre_state;\r\n\r\n  //To wait for IMU Calibration\r\n  if(pre_state != get_connection_state_with_ros2_node()){\r\n    pre_state = get_connection_state_with_ros2_node();\r\n    pre_time = millis();\r\n    return;\r\n  }\r\n\r\n  if(pre_data != control_items.heart_beat || control_items.debug_mode == true){\r\n    pre_time = millis();\r\n    pre_data = control_items.heart_beat;\r\n    set_connection_state_with_ros2_node(true);\r\n  }else{\r\n    if(millis()-pre_time >= HEARTBEAT_TIMEOUT_MS){\r\n      pre_time = millis();\r\n      set_connection_state_with_ros2_node(false);\r\n    }\r\n  }\r\n\r\n  control_items.is_connect_ros2_node = get_connection_state_with_ros2_node();\r\n}\r\n\r\n\r\n/*******************************************************************************\r\n* Function definition to check the connection with the motor.\r\n*******************************************************************************/\r\nstatic bool is_connected_motors = false;\r\n\r\nstatic bool get_connection_state_with_motors()\r\n{\r\n  return is_connected_motors;\r\n}\r\n\r\nstatic void set_connection_state_with_motors(bool is_connected)\r\n{\r\n  is_connected_motors = is_connected;\r\n}\r\n\r\n/*******************************************************************************\r\n* Function definition to check the connection with the motor.\r\n*******************************************************************************/\r\nstatic bool is_connected_joints = false;\r\n\r\nstatic bool get_connection_state_with_joints()\r\n{\r\n  return is_connected_joints;\r\n}\r\n\r\nstatic void set_connection_state_with_joints(bool is_connected)\r\n{\r\n  is_connected_joints = is_connected;\r\n}\r\n\r\n/*******************************************************************************\r\n* Function definition to test motors using the built-in buttons of OpenCR.\r\n*******************************************************************************/\r\nconst float TICK2RAD = 0.001533981; // 0.087890625[deg] * 3.14159265359 / 180 = 0.001533981f\r\nconst float TEST_DISTANCE = 0.300; // meter\r\nconst float TEST_RADIAN = 3.14; // 180 degree\r\n\r\nvoid test_motors_with_buttons(uint8_t buttons)\r\n{\r\n  static bool move[2] = {false, false};\r\n  static int32_t saved_tick[2] = {0, 0};\r\n  static double diff_encoder = 0.0;\r\n\r\n  int32_t current_tick[2] = {0, 0};\r\n\r\n  if(get_connection_state_with_motors() == true){\r\n    motor_driver.read_present_position(current_tick[MortorLocation::LEFT], current_tick[MortorLocation::RIGHT]);\r\n  }\r\n\r\n  if (buttons & (1<<0))  \r\n  {\r\n    move[VelocityType::LINEAR] = true;\r\n    saved_tick[MortorLocation::RIGHT] = current_tick[MortorLocation::RIGHT];\r\n\r\n    diff_encoder = TEST_DISTANCE / (0.207 / 4096); // (Circumference of Wheel) / (The number of tick per revolution)\r\n  }\r\n  else if (buttons & (1<<1))\r\n  {\r\n    move[VelocityType::ANGULAR] = true;\r\n    saved_tick[MortorLocation::RIGHT] = current_tick[MortorLocation::RIGHT];\r\n\r\n    diff_encoder = (TEST_RADIAN * p_tb3_model_info->turning_radius) / (0.207 / 4096);\r\n  }\r\n\r\n  if (move[VelocityType::LINEAR])\r\n  {    \r\n    if (abs(saved_tick[MortorLocation::RIGHT] - current_tick[MortorLocation::RIGHT]) <= diff_encoder)\r\n    {\r\n      goal_velocity_from_button[VelocityType::LINEAR]  = 0.05;\r\n    }\r\n    else\r\n    {\r\n      goal_velocity_from_button[VelocityType::LINEAR]  = 0.0;\r\n      move[VelocityType::LINEAR] = false;\r\n    }\r\n  }\r\n  else if (move[VelocityType::ANGULAR])\r\n  {   \r\n    if (abs(saved_tick[MortorLocation::RIGHT] - current_tick[MortorLocation::RIGHT]) <= diff_encoder)\r\n    {\r\n      goal_velocity_from_button[VelocityType::ANGULAR]= -0.7;\r\n    }\r\n    else\r\n    {\r\n      goal_velocity_from_button[VelocityType::ANGULAR]  = 0.0;\r\n      move[VelocityType::ANGULAR] = false;\r\n    }\r\n  }\r\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros2/src/turtlebot3/turtlebot3_controller.cpp",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n#include \"../../include/turtlebot3/turtlebot3_controller.h\"\n\nTurtlebot3Controller::Turtlebot3Controller()\n{\n  const_cmd_vel_ = CONST_VEL;\n}\n\nTurtlebot3Controller::~Turtlebot3Controller()\n{}\n\nbool Turtlebot3Controller::init(float max_lin_vel, float max_ang_vel, uint8_t scale_lin_vel, uint8_t scale_ang_vel)\n{\n  // 57600bps baudrate for RC100 control\n  rc100_.begin(1);  \n\n  max_lin_vel_ = max_lin_vel;\n  min_lin_vel_ = (-1)*max_lin_vel;\n  max_ang_vel_ = max_ang_vel;\n  min_ang_vel_ = (-1)*max_ang_vel;\n  scale_lin_vel_ = scale_lin_vel;\n  scale_ang_vel_ = scale_ang_vel;\n\n  return true;\n}\n\nvoid Turtlebot3Controller::getRCdata(float *get_cmd_vel)\n{\n  uint16_t received_data = 0;\n\n  static float lin_x = 0.0, ang_z = 0.0;\n  \n  if (rc100_.available())\n  {\n    received_data = rc100_.readData();\n\n    if (received_data & RC100_BTN_U)\n    {\n      lin_x += VELOCITY_LINEAR_X * scale_lin_vel_;\n    }\n    else if (received_data & RC100_BTN_D)\n    {\n      lin_x -= VELOCITY_LINEAR_X * scale_lin_vel_;\n    }\n    else if (received_data & RC100_BTN_L)\n    {\n      ang_z += VELOCITY_ANGULAR_Z * scale_ang_vel_;\n    }\n    else if (received_data & RC100_BTN_R)\n    {\n      ang_z -= VELOCITY_ANGULAR_Z * scale_ang_vel_;\n    }\n    else if (received_data & RC100_BTN_6)\n    {\n      lin_x = const_cmd_vel_;\n      ang_z = 0.0;\n    }\n    else if (received_data & RC100_BTN_5)\n    {\n      lin_x = 0.0;\n      ang_z = 0.0;\n    }\n    else\n    {\n      lin_x = lin_x;\n      ang_z = ang_z;\n    }\n\n    lin_x = constrain(lin_x, min_lin_vel_, max_lin_vel_);\n    ang_z = constrain(ang_z, min_ang_vel_, max_ang_vel_);\n\n    get_cmd_vel[0] = lin_x;\n    get_cmd_vel[1] = ang_z;\n  }\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros2/src/turtlebot3/turtlebot3_diagnosis.cpp",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n#include \"../../include/turtlebot3/turtlebot3_diagnosis.h\"\n\nTurtlebot3Diagnosis::Turtlebot3Diagnosis()\n{\n}\n\nTurtlebot3Diagnosis::~Turtlebot3Diagnosis()\n{}\n\nbool Turtlebot3Diagnosis::init(void)\n{\n  pinMode(LED_WORKING_CHECK, OUTPUT);\n\n  return true;\n}\n\nvoid Turtlebot3Diagnosis::showLedStatus(bool isConnected)\n{\n  static uint32_t t_time = millis();\n\n  if ((millis()-t_time) >= 500)\n  {\n    t_time = millis();\n    digitalWrite(LED_WORKING_CHECK, !digitalRead(LED_WORKING_CHECK));\n  }\n\n  if (getPowerInVoltage() < 11.1)\n  {\n    setLedOn(LED_LOW_BATTERY);\n  }\n  else\n  {\n    setLedOff(LED_LOW_BATTERY);\n  }\n\n  if (isConnected)\n  {\n    setLedOn(LED_ROS_CONNECT);\n  }\n  else\n  {\n    setLedOff(LED_ROS_CONNECT);\n  }\n\n  updateRxTxLed();\n}\n\nvoid Turtlebot3Diagnosis::updateRxTxLed(void)\n{\n  static uint32_t rx_led_update_time;\n  static uint32_t tx_led_update_time;\n  static uint32_t rx_cnt;\n  static uint32_t tx_cnt;\n\n  if ((millis()-tx_led_update_time) > 50)\n  {\n    tx_led_update_time = millis();\n\n    if (tx_cnt != Serial.getTxCnt())\n    {\n      setLedToggle(LED_TXD);\n    }\n    else\n    {\n      setLedOff(LED_TXD);\n    }\n\n    tx_cnt = Serial.getTxCnt();\n  }\n\n  if ((millis()-rx_led_update_time) > 50)\n  {\n    rx_led_update_time = millis();\n\n    if (rx_cnt != Serial.getRxCnt())\n    {\n      setLedToggle(LED_RXD);\n    }\n    else\n    {\n      setLedOff(LED_RXD);\n    }\n\n    rx_cnt = Serial.getRxCnt();\n  }\n}\n\nvoid Turtlebot3Diagnosis::setPowerOn(void)\n{\n  digitalWrite(BDPIN_DXL_PWR_EN, HIGH);\n}\n\nvoid Turtlebot3Diagnosis::setPowerOff(void)\n{\n  digitalWrite(BDPIN_DXL_PWR_EN, LOW);\n}\n\nuint8_t Turtlebot3Diagnosis::updateVoltageCheck(bool check_setup)\n{  \n  //static uint8_t battery_voltage     = 0;\n  static float   battery_voltage_raw = 0;\n  static uint8_t battery_state       = BATTERY_POWER_OFF;\n\n  static bool startup = false;\n  static int vol_index = 0;\n  static int prev_state = 0;\n  static int alram_state = 0;\n  static int check_index = 0;\n\n  int i;\n  float vol_sum;\n  float vol_value;\n\n  static uint32_t process_time[8] = {0,};\n  static float    vol_value_tbl[10] = {0,};\n\n  float voltage_ref       = 11.0 + 0.0;\n  float voltage_ref_warn  = 11.0 + 0.0;\n\n\n  if (startup == false)\n  {\n    startup = true;\n    for (i=0; i<8; i++)\n    {\n      process_time[i] = millis();\n    }\n  }\n\n  if (millis()-process_time[0] > 100)\n  {\n    process_time[0] = millis();\n\n    vol_value_tbl[vol_index] = getPowerInVoltage();\n\n    vol_index++;\n    vol_index %= 10;\n\n    vol_sum = 0;\n    for(i=0; i<10; i++)\n    {\n      vol_sum += vol_value_tbl[i];\n    }\n    vol_value = vol_sum/10;\n    battery_voltage_raw = vol_value;\n\n    //Serial.println(vol_value);\n\n    //battery_voltage = vol_value;\n  }\n\n\n  if(millis()-process_time[1] > 1000)\n  {\n    process_time[1] = millis();\n\n    //Serial.println(battery_state);\n\n    switch(battery_state)\n    {\n      case BATTERY_POWER_OFF:\n        if (check_setup == true)\n        {\n          alram_state = 0;\n          if(battery_voltage_raw > 5.0)\n          {\n            check_index    = 0;\n            prev_state     = battery_state;\n            battery_state = BATTERY_POWER_STARTUP;\n          }\n          else\n          {\n            noTone(BDPIN_BUZZER);\n          }\n        }\n        break;\n\n      case BATTERY_POWER_STARTUP:\n        if(battery_voltage_raw > voltage_ref)\n        {\n          check_index   = 0;\n          prev_state    = battery_state;\n          battery_state = BATTERY_POWER_NORMAL;\n          setPowerOn();\n        }\n\n        if(check_index < 5)\n        {\n          check_index++;\n        }\n        else\n        {\n          if (battery_voltage_raw > 5.0)\n          {\n            prev_state    = battery_state;\n            battery_state = BATTERY_POWER_CHECK;\n          }\n          else\n          {\n            prev_state    = battery_state;\n            battery_state = BATTERY_POWER_OFF;\n          }\n        }\n        break;\n\n      case BATTERY_POWER_NORMAL:\n        alram_state = 0;\n        if(battery_voltage_raw < voltage_ref)\n        {\n          prev_state    = battery_state;\n          battery_state = BATTERY_POWER_CHECK;\n          check_index   = 0;\n        }\n        break;\n\n      case BATTERY_POWER_CHECK:\n        if(check_index < 5)\n        {\n          check_index++;\n        }\n        else\n        {\n          if(battery_voltage_raw < voltage_ref_warn)\n          {\n            setPowerOff();\n            prev_state    = battery_state;\n            battery_state = BATTERY_POWER_WARNNING;\n          }\n        }\n        if(battery_voltage_raw >= voltage_ref)\n        {\n          setPowerOn();\n          prev_state    = battery_state;\n          battery_state = BATTERY_POWER_NORMAL;\n        }\n        break;\n\n      case BATTERY_POWER_WARNNING:\n        alram_state ^= 1;\n        if(alram_state)\n        {\n          tone(BDPIN_BUZZER, 1000, 500);\n        }\n\n        if(battery_voltage_raw > voltage_ref)\n        {\n          setPowerOn();\n          prev_state    = battery_state;\n          battery_state = BATTERY_POWER_NORMAL;\n        }\n        else\n        {\n          setPowerOff();\n        }\n\n        if(battery_voltage_raw < 5.0)\n        {\n          setPowerOff();\n          prev_state    = battery_state;\n          battery_state = BATTERY_POWER_OFF;\n        }\n        break;\n\n      default:\n        break;\n    }\n  }\n\n  (void)(prev_state);\n\n  return battery_state;\n}\n\nuint8_t Turtlebot3Diagnosis::getButtonPress(uint16_t time_to_press)\n{\n  uint8_t button_state = 0;\n  static uint32_t t_time[2];\n  static uint8_t button_state_num[2] = {0, };\n\n  for (int button_num = 0; button_num < 2; button_num++)\n  {\n    switch (button_state_num[button_num])\n    {\n     case WAIT_FOR_BUTTON_PRESS:\n       if (getPushButton() & (1 << button_num))\n       {\n         t_time[button_num] = millis();\n         button_state_num[button_num] = WAIT_SECOND;\n       }\n       break;\n\n     case WAIT_SECOND:\n       if ((millis()-t_time[button_num]) >= time_to_press)\n       {\n         if (getPushButton() & (1 << button_num))\n         {\n           button_state_num[button_num] = CHECK_BUTTON_RELEASED;\n           button_state |= (1 << button_num);\n         }\n         else\n         {\n           button_state_num[button_num] = WAIT_FOR_BUTTON_PRESS;\n         }\n       }\n       break;\n\n     case CHECK_BUTTON_RELEASED:\n       if (!(getPushButton() & (1 << button_num)))\n         button_state_num[button_num] = WAIT_FOR_BUTTON_PRESS;\n       break;\n\n     default :\n       button_state_num[button_num] = WAIT_FOR_BUTTON_PRESS;\n       break;\n    }\n  }\n\n  return button_state;\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros2/src/turtlebot3/turtlebot3_motor_driver.cpp",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n#include \"../../include/turtlebot3/turtlebot3_motor_driver.h\"\n\n// Limit values (XM430-W210-T and XM430-W350-T)\n// MAX RPM is 77 when DXL is powered 12.0V\n// 77 / 0.229 (RPM) = 336.24454...\nconst uint16_t LIMIT_X_MAX_VELOCITY = 337; \n// V = r * w = r     *        (RPM             * 0.10472)\n//           = 0.033 * (0.229 * Goal_Velocity) * 0.10472\n// Goal_Velocity = V * 1263.632956882\nconst float VELOCITY_CONSTANT_VALUE = 1263.632956882; \n\n/* DYNAMIXEL Information for controlling motors and  */\nconst uint8_t DXL_MOTOR_ID_LEFT = 1; // ID of left motor\nconst uint8_t DXL_MOTOR_ID_RIGHT = 2; // ID of right motor\nconst float DXL_PORT_PROTOCOL_VERSION = 2.0; // Dynamixel protocol version 2.0\nconst uint32_t DXL_PORT_BAUDRATE = 1000000; // baurd rate of Dynamixel\nconst int OPENCR_DXL_DIR_PIN = 84; // Arduino pin number of DYNAMIXEL direction pin on OpenCR.\n\nParamForSyncReadInst_t sync_read_param;\nParamForSyncWriteInst_t sync_write_param;\nRecvInfoFromStatusInst_t read_result;\nDynamixel2Arduino dxl(Serial3, OPENCR_DXL_DIR_PIN);\n\n\n\nTurtlebot3MotorDriver::Turtlebot3MotorDriver()\n: left_wheel_id_(DXL_MOTOR_ID_LEFT),\n  right_wheel_id_(DXL_MOTOR_ID_RIGHT),\n  torque_(false)\n{\n}\n\nTurtlebot3MotorDriver::~Turtlebot3MotorDriver()\n{\n  close();\n  digitalWrite(BDPIN_DXL_PWR_EN, LOW);\n}\n\nbool Turtlebot3MotorDriver::init(void)\n{\n  pinMode(BDPIN_DXL_PWR_EN, OUTPUT);\n  digitalWrite(BDPIN_DXL_PWR_EN, HIGH);\n  drv_dxl_init();\n\n  dxl.begin(DXL_PORT_BAUDRATE);\n  dxl.setPortProtocolVersion(DXL_PORT_PROTOCOL_VERSION);\n\n  sync_write_param.id_count = 2;\n  sync_write_param.xel[LEFT].id = left_wheel_id_;\n  sync_write_param.xel[RIGHT].id = right_wheel_id_;\n\n  sync_read_param.addr = 132;\n  sync_read_param.length = 4;\n  sync_read_param.id_count = 2;\n  sync_read_param.xel[LEFT].id = left_wheel_id_;\n  sync_read_param.xel[RIGHT].id = right_wheel_id_;\n\n  // Enable Dynamixel Torque\n  set_torque(true);\n\n  return true;\n}\n\nDynamixel2Arduino& Turtlebot3MotorDriver::getDxl()\n{\n  return dxl;\n}\n\nbool Turtlebot3MotorDriver::is_connected()\n{\n  return (dxl.ping(DXL_MOTOR_ID_LEFT) == true && dxl.ping(DXL_MOTOR_ID_RIGHT) == true);\n}\n\nbool Turtlebot3MotorDriver::set_torque(bool onoff)\n{\n  bool ret = false;\n\n  sync_write_param.addr = 64;\n  sync_write_param.length = 1;\n  sync_write_param.xel[LEFT].data[0] = onoff;\n  sync_write_param.xel[RIGHT].data[0] = onoff;\n\n  if(dxl.syncWrite(sync_write_param) == true){\n    ret = true;\n    torque_ = onoff;\n  }\n\n  return ret;\n}\n\nbool Turtlebot3MotorDriver::get_torque()\n{\n  if(dxl.readControlTableItem(TORQUE_ENABLE, left_wheel_id_) == true\n    && dxl.readControlTableItem(TORQUE_ENABLE, right_wheel_id_) == true){\n    torque_ = true;\n  }else{\n    torque_ = false;\n  }\n\n  return torque_;\n}\n\nvoid Turtlebot3MotorDriver::close(void)\n{\n  // Disable Dynamixel Torque\n  set_torque(false);\n}\n\nbool Turtlebot3MotorDriver::read_present_position(int32_t &left_value, int32_t &right_value)\n{\n  bool ret = false;\n\n  sync_read_param.addr = 132;\n  sync_read_param.length = 4;\n\n  if(dxl.syncRead(sync_read_param, read_result)){\n    memcpy(&left_value, read_result.xel[LEFT].data, read_result.xel[LEFT].length);\n    memcpy(&right_value, read_result.xel[RIGHT].data, read_result.xel[RIGHT].length);\n    ret = true;\n  }\n\n  return ret;\n}\n\nbool Turtlebot3MotorDriver::read_present_velocity(int32_t &left_value, int32_t &right_value)\n{\n  bool ret = false;\n\n  sync_read_param.addr = 128;\n  sync_read_param.length = 4;\n\n  if(dxl.syncRead(sync_read_param, read_result)){\n    memcpy(&left_value, read_result.xel[LEFT].data, read_result.xel[LEFT].length);\n    memcpy(&right_value, read_result.xel[RIGHT].data, read_result.xel[RIGHT].length);\n    ret = true;\n  }\n\n  return ret;\n}\n\nbool Turtlebot3MotorDriver::read_present_current(int16_t &left_value, int16_t &right_value)\n{\n  bool ret = false;\n\n  sync_read_param.addr = 126;\n  sync_read_param.length = 2;\n\n  if(dxl.syncRead(sync_read_param, read_result)){\n    memcpy(&left_value, read_result.xel[LEFT].data, read_result.xel[LEFT].length);\n    memcpy(&right_value, read_result.xel[RIGHT].data, read_result.xel[RIGHT].length);\n    ret = true;\n  }\n\n  return ret;\n}\n\nbool Turtlebot3MotorDriver::read_profile_acceleration(uint32_t &left_value, uint32_t &right_value)\n{\n  bool ret = false;\n\n  sync_read_param.addr = 108;\n  sync_read_param.length = 4;\n\n  if(dxl.syncRead(sync_read_param, read_result)){\n    memcpy(&left_value, read_result.xel[LEFT].data, read_result.xel[LEFT].length);\n    memcpy(&right_value, read_result.xel[RIGHT].data, read_result.xel[RIGHT].length);\n    ret = true;\n  }\n\n  return ret;\n}\n\n\nbool Turtlebot3MotorDriver::write_velocity(int32_t left_value, int32_t right_value)\n{\n  bool ret = false;\n\n  sync_write_param.addr = 104;\n  sync_write_param.length = 4;\n  memcpy(sync_write_param.xel[LEFT].data, &left_value, sync_write_param.length);\n  memcpy(sync_write_param.xel[RIGHT].data, &right_value, sync_write_param.length);\n\n  if(dxl.syncWrite(sync_write_param)){\n    ret = true;\n  }\n\n  return ret;\n}\n\nbool Turtlebot3MotorDriver::write_profile_acceleration(uint32_t left_value, uint32_t right_value)\n{\n  bool ret = false;\n\n  sync_write_param.addr = 108;\n  sync_write_param.length = 4;\n  memcpy(sync_write_param.xel[LEFT].data, &left_value, sync_write_param.length);\n  memcpy(sync_write_param.xel[RIGHT].data, &right_value, sync_write_param.length);\n\n  if(dxl.syncWrite(sync_write_param)){\n    ret = true;\n  }\n\n  return ret;\n}\n\nbool Turtlebot3MotorDriver::control_motors(const float wheel_separation, float linear_value, float angular_value)\n{\n  bool dxl_comm_result = false;\n  \n  float wheel_velocity[MortorLocation::MOTOR_NUM_MAX];\n  float lin_vel = linear_value;\n  float ang_vel = angular_value;\n\n  wheel_velocity[LEFT]   = lin_vel - (ang_vel * wheel_separation / 2);\n  wheel_velocity[RIGHT]  = lin_vel + (ang_vel * wheel_separation / 2);\n\n  wheel_velocity[LEFT]  = constrain(wheel_velocity[LEFT]  * VELOCITY_CONSTANT_VALUE, -LIMIT_X_MAX_VELOCITY, LIMIT_X_MAX_VELOCITY);\n  wheel_velocity[RIGHT] = constrain(wheel_velocity[RIGHT] * VELOCITY_CONSTANT_VALUE, -LIMIT_X_MAX_VELOCITY, LIMIT_X_MAX_VELOCITY);\n\n  dxl_comm_result = write_velocity((int32_t)wheel_velocity[LEFT], (int32_t)wheel_velocity[RIGHT]);\n  if (dxl_comm_result == false)\n    return false;\n\n  return true;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros2/src/turtlebot3/turtlebot3_sensor.cpp",
    "content": "/*******************************************************************************\n* Copyright 2016 ROBOTIS CO., LTD.\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n*     http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*******************************************************************************/\n\n#include \"../../include/turtlebot3/turtlebot3_sensor.h\"\n\nTurtlebot3Sensor::Turtlebot3Sensor()\n{\n}\n\nTurtlebot3Sensor::~Turtlebot3Sensor()\n{}\n\nbool Turtlebot3Sensor::init(void)\n{\n  bool ret = false;\n\n  initBumper();\n  initIR();\n  initSonar();\n  initLED();\n\n  uint8_t get_error_code = imu_.begin();\n\n  if (get_error_code == 0x00)\n    ret = true;\n\n  return ret;\n}\n\nvoid Turtlebot3Sensor::initIMU(void)\n{\n  imu_.begin();\n}\n\nvoid Turtlebot3Sensor::updateIMU(void)\n{\n  imu_.update();\n}\n\nvoid Turtlebot3Sensor::calibrationGyro()\n{\n  uint32_t pre_time;\n  uint32_t t_time;\n\n  const uint8_t led_ros_connect = 3;\n\n  imu_.SEN.gyro_cali_start();\n  \n  t_time   = millis();\n  pre_time = millis();\n\n  while(!imu_.SEN.gyro_cali_get_done())\n  {\n    imu_.update();\n\n    if (millis()-pre_time > 5000)\n    {\n      break;\n    }\n    if (millis()-t_time > 100)\n    {\n      t_time = millis();\n      setLedToggle(led_ros_connect);\n    }\n  }\n}\n\nfloat* Turtlebot3Sensor::getImuAngularVelocity(void)\n{\n  static float angular_vel[3];\n\n  angular_vel[0] = imu_.SEN.gyroADC[0] * GYRO_FACTOR;\n  angular_vel[1] = imu_.SEN.gyroADC[1] * GYRO_FACTOR;\n  angular_vel[2] = imu_.SEN.gyroADC[2] * GYRO_FACTOR;\n\n  return angular_vel;\n}\n\nfloat* Turtlebot3Sensor::getImuLinearAcc(void)\n{\n  static float linear_acc[3];\n\n  linear_acc[0] = imu_.SEN.accADC[0] * ACCEL_FACTOR;\n  linear_acc[1] = imu_.SEN.accADC[1] * ACCEL_FACTOR;\n  linear_acc[2] = imu_.SEN.accADC[2] * ACCEL_FACTOR;\n\n  return linear_acc;\n}\n\nfloat* Turtlebot3Sensor::getImuMagnetic(void)\n{\n  static float magnetic[3];\n\n  magnetic[0] = imu_.SEN.magADC[0] * MAG_FACTOR;\n  magnetic[1] = imu_.SEN.magADC[1] * MAG_FACTOR;\n  magnetic[2] = imu_.SEN.magADC[2] * MAG_FACTOR;\n\n  return magnetic;\n}\n\nfloat* Turtlebot3Sensor::getOrientation(void)\n{\n  static float orientation[4];\n\n  orientation[0] = imu_.quat[0];\n  orientation[1] = imu_.quat[1];\n  orientation[2] = imu_.quat[2];\n  orientation[3] = imu_.quat[3];\n\n  return orientation;\n}\n\nfloat Turtlebot3Sensor::checkVoltage(void)\n{\n  float vol_value;\n  \n  vol_value = getPowerInVoltage();\n\n  return vol_value;\n}\n\nuint8_t Turtlebot3Sensor::checkPushButton(void)\n{\n  return getPushButton();\n}\n\nvoid Turtlebot3Sensor::onMelody()\n{\n  static uint8_t pre_note_number = 7, current_note_number;\n  static uint32_t pre_time;\n  static uint32_t note_duration, pause_time_ms_between_notes;\n\n  if(is_melody_play_complete_ == false){\n    if(pre_note_number != current_note_number){\n      // to calculate the note duration, take one second\n      // divided by the note type.\n      //e.g. quarter note = 1000 / 4, eighth note = 1000/8, etc.\n      note_duration = 1000/melody_duration_[current_note_number];    \n      // to distinguish the notes, set a minimum time between them.\n      // the note's duration + 30% seems to work well:\n      pause_time_ms_between_notes = note_duration * 1.30;\n\n      tone(BDPIN_BUZZER, melody_note_[current_note_number], note_duration);\n      \n      pre_note_number = current_note_number;\n      pre_time = millis();\n    }else{\n      if(millis()-pre_time >= pause_time_ms_between_notes){\n        pre_time = millis();\n        noTone(BDPIN_BUZZER);\n        current_note_number++;\n\n        if(current_note_number == 8){\n          is_melody_play_complete_ = true;\n          current_note_number = 0;\n        }\n      }\n    }\n  }\n}\n\nvoid Turtlebot3Sensor::makeMelody(uint8_t index)\n{\n  const uint16_t NOTE_C4 = 262;\n  const uint16_t NOTE_D4 = 294;\n  const uint16_t NOTE_E4 = 330;\n  const uint16_t NOTE_F4 = 349;\n  const uint16_t NOTE_G4 = 392;\n  const uint16_t NOTE_A4 = 440;\n  const uint16_t NOTE_B4 = 494;\n  const uint16_t NOTE_C5 = 523;\n  //const uint16_t NOTE_C6 = 1047;\n\n  const uint8_t OFF         = 0;\n  const uint8_t ON          = 1;\n  const uint8_t LOW_BATTERY = 2;\n  const uint8_t ERROR       = 3;\n  const uint8_t BUTTON1     = 4;\n  const uint8_t BUTTON2     = 5;\n\n  switch (index)\n  {\n    case ON:\n      melody_note_[0] = NOTE_C4;   melody_duration_[0] = 4;\n      melody_note_[1] = NOTE_D4;   melody_duration_[1] = 4;\n      melody_note_[2] = NOTE_E4;   melody_duration_[2] = 4;\n      melody_note_[3] = NOTE_F4;   melody_duration_[3] = 4;\n      melody_note_[4] = NOTE_G4;   melody_duration_[4] = 4;\n      melody_note_[5] = NOTE_A4;   melody_duration_[5] = 4;\n      melody_note_[6] = NOTE_B4;   melody_duration_[6] = 4;\n      melody_note_[7] = NOTE_C5;   melody_duration_[7] = 4;\n     break;\n\n    case OFF:\n      melody_note_[0] = NOTE_C5;   melody_duration_[0] = 4;\n      melody_note_[1] = NOTE_B4;   melody_duration_[1] = 4;\n      melody_note_[2] = NOTE_A4;   melody_duration_[2] = 4;\n      melody_note_[3] = NOTE_G4;   melody_duration_[3] = 4;\n      melody_note_[4] = NOTE_F4;   melody_duration_[4] = 4;\n      melody_note_[5] = NOTE_E4;   melody_duration_[5] = 4;\n      melody_note_[6] = NOTE_D4;   melody_duration_[6] = 4;\n      melody_note_[7] = NOTE_C4;   melody_duration_[7] = 4;  \n     break;\n\n    case LOW_BATTERY:\n      melody_note_[0] = 1000;      melody_duration_[0] = 1;\n      melody_note_[1] = 1000;      melody_duration_[1] = 1;\n      melody_note_[2] = 1000;      melody_duration_[2] = 1;\n      melody_note_[3] = 1000;      melody_duration_[3] = 1;\n      melody_note_[4] = 0;         melody_duration_[4] = 8;\n      melody_note_[5] = 0;         melody_duration_[5] = 8;\n      melody_note_[6] = 0;         melody_duration_[6] = 8;\n      melody_note_[7] = 0;         melody_duration_[7] = 8;\n     break;\n\n    case ERROR:\n      melody_note_[0] = 1000;      melody_duration_[0] = 3;\n      melody_note_[1] = 500;       melody_duration_[1] = 3;\n      melody_note_[2] = 1000;      melody_duration_[2] = 3;\n      melody_note_[3] = 500;       melody_duration_[3] = 3;\n      melody_note_[4] = 1000;      melody_duration_[4] = 3;\n      melody_note_[5] = 500;       melody_duration_[5] = 3;\n      melody_note_[6] = 1000;      melody_duration_[6] = 3;\n      melody_note_[7] = 500;       melody_duration_[7] = 3;\n     break;\n\n    case BUTTON1:\n    case BUTTON2:\n    default:\n      return;\n  }\n\n  is_melody_play_complete_ = false;\n}\n\nvoid Turtlebot3Sensor::initBumper(void)\n{\n  ollo_.begin(3, TOUCH_SENSOR);\n  ollo_.begin(4, TOUCH_SENSOR);\n}\n\nuint8_t Turtlebot3Sensor::checkPushBumper(void)\n{\n  uint8_t push_state = 0;\n\n  if      (ollo_.read(3, TOUCH_SENSOR) == HIGH) push_state = 2;\n  else if (ollo_.read(4, TOUCH_SENSOR) == HIGH) push_state = 1;\n  else    push_state = 0;\n  \n  return push_state;\n}\n\nbool Turtlebot3Sensor::getBumper1State()\n{\n  return ollo_.read(3, TOUCH_SENSOR); \n}\n\nbool Turtlebot3Sensor::getBumper2State()\n{\n  return ollo_.read(4, TOUCH_SENSOR);\n}\n\nvoid Turtlebot3Sensor::initIR(void)\n{\n  ollo_.begin(2, IR_SENSOR);\n}\n\nfloat Turtlebot3Sensor::getIRsensorData(void)\n{\n  float ir_data = ollo_.read(2, IR_SENSOR);\n  \n  return ir_data;\n}\n\nvoid Turtlebot3Sensor::initSonar(void)\n{\n  sonar_pin_.trig = BDPIN_GPIO_1;\n  sonar_pin_.echo = BDPIN_GPIO_2;\n\n  pinMode(sonar_pin_.trig, OUTPUT);\n  pinMode(sonar_pin_.echo, INPUT);\n}\n\nvoid Turtlebot3Sensor::updateSonar(uint32_t t)\n{\n  static uint32_t t_time = 0;\n  static bool make_pulse = TRUE;\n  static bool get_duration = FALSE;\n\n  float distance = 0.0, duration = 0.0;\n\n  if (make_pulse == TRUE)\n  {\n    digitalWrite(sonar_pin_.trig, HIGH);\n\n    if (t - t_time >= 10)\n    {\n      digitalWrite(sonar_pin_.trig, LOW);\n\n      get_duration = TRUE;\n      make_pulse = FALSE;\n\n      t_time = t;\n    }\n  }\n\n  if (get_duration == TRUE)\n  {\n    duration = pulseIn(sonar_pin_.echo, HIGH);\n    distance = ((float)(340 * duration) / 10000) / 2;\n\n    make_pulse = TRUE;\n    get_duration = FALSE;\n  }\n\n  sonar_data_ = distance;\n}\n\nfloat Turtlebot3Sensor::getSonarData(void)\n{\n  float distance = 0.0;\n\n  distance = sonar_data_;\n\n  return distance;\n}\n\nfloat Turtlebot3Sensor::getIlluminationData(void)\n{\n  uint16_t light;\n\n  light = analogRead(A1);\n\n  return light;\n}\n\nvoid Turtlebot3Sensor::initLED(void)\n{\n  led_pin_array_.front_left  = BDPIN_GPIO_4;\n  led_pin_array_.front_right = BDPIN_GPIO_6;\n  led_pin_array_.back_left   = BDPIN_GPIO_8;\n  led_pin_array_.back_right  = BDPIN_GPIO_10;\n \n  pinMode(led_pin_array_.front_left, OUTPUT);\n  pinMode(led_pin_array_.front_right, OUTPUT);\n  pinMode(led_pin_array_.back_left, OUTPUT);\n  pinMode(led_pin_array_.back_right, OUTPUT);\n}\n\nvoid Turtlebot3Sensor::setLedPattern(double linear_vel, double angular_vel)\n{\n  if (linear_vel > 0.0 && angular_vel == 0.0)     // front\n  {\n    digitalWrite(led_pin_array_.front_left, HIGH);\n    digitalWrite(led_pin_array_.front_right, HIGH);\n    digitalWrite(led_pin_array_.back_left, LOW);\n    digitalWrite(led_pin_array_.back_right, LOW);\n  }\n  else if (linear_vel >= 0.0 && angular_vel > 0.0)  // front left\n  {\n    digitalWrite(led_pin_array_.front_left, HIGH);\n    digitalWrite(led_pin_array_.front_right, LOW);\n    digitalWrite(led_pin_array_.back_left, LOW);\n    digitalWrite(led_pin_array_.back_right, LOW);\n  }\n  else if (linear_vel >= 0.0 && angular_vel < 0.0)  // front right\n  {\n    digitalWrite(led_pin_array_.front_left, LOW);\n    digitalWrite(led_pin_array_.front_right, HIGH);\n    digitalWrite(led_pin_array_.back_left, LOW);\n    digitalWrite(led_pin_array_.back_right, LOW);\n  }\n  else if (linear_vel < 0.0 && angular_vel == 0.0) // back\n  {\n    digitalWrite(led_pin_array_.front_left, LOW);\n    digitalWrite(led_pin_array_.front_right, LOW);\n    digitalWrite(led_pin_array_.back_left, HIGH);\n    digitalWrite(led_pin_array_.back_right, HIGH);\n  }\n  else if (linear_vel <= 0.0 && angular_vel > 0.0)  // back right\n  {\n    digitalWrite(led_pin_array_.front_left, LOW);\n    digitalWrite(led_pin_array_.front_right, LOW);\n    digitalWrite(led_pin_array_.back_left, LOW);\n    digitalWrite(led_pin_array_.back_right, HIGH);\n  }\n  else if (linear_vel <= 0.0 && angular_vel < 0.0)  // back left\n  {\n    digitalWrite(led_pin_array_.front_left, LOW);\n    digitalWrite(led_pin_array_.front_right, LOW);\n    digitalWrite(led_pin_array_.back_left, HIGH);\n    digitalWrite(led_pin_array_.back_right, LOW);\n  }\n  else \n  {\n    digitalWrite(led_pin_array_.front_left, LOW);\n    digitalWrite(led_pin_array_.front_right, LOW);\n    digitalWrite(led_pin_array_.back_left, LOW);\n    digitalWrite(led_pin_array_.back_right, LOW);\n  }\n}\n\n\n\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/ArduinoHardware.h",
    "content": "/*\n * Software License Agreement (BSD License)\n *\n * Copyright (c) 2011, Willow Garage, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n *  * Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n *  * Redistributions in binary form must reproduce the above\n *    copyright notice, this list of conditions and the following\n *    disclaimer in the documentation and/or other materials provided\n *    with the distribution.\n *  * Neither the name of Willow Garage, Inc. nor the names of its\n *    contributors may be used to endorse or promote prducts derived\n *    from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef ROS_ARDUINO_HARDWARE_H_\n#define ROS_ARDUINO_HARDWARE_H_\n\n#if ARDUINO>=100\n  #include <Arduino.h>  // Arduino 1.0\n#else\n  #include <WProgram.h>  // Arduino 0022\n#endif\n\n#if defined(__MK20DX128__) || defined(__MK20DX256__)\n  #if defined(USE_TEENSY_HW_SERIAL)\n    #define SERIAL_CLASS HardwareSerial // Teensy HW Serial\n  #else\n    #include <usb_serial.h>  // Teensy 3.0 and 3.1\n    #define SERIAL_CLASS usb_serial_class\n  #endif\n#elif defined(_SAM3XA_)\n  #include <UARTClass.h>  // Arduino Due\n  #define SERIAL_CLASS UARTClass\n#elif defined(USE_USBCON)\n  // Arduino Leonardo USB Serial Port\n  #define SERIAL_CLASS Serial_\n#else\n  #include <HardwareSerial.h>  // Arduino AVR\n  #define SERIAL_CLASS USBSerial // USBSerial / UARTClass (Bluetooth Device) on OpenCR\n#endif\n\nclass ArduinoHardware {\n  public:\n    ArduinoHardware(SERIAL_CLASS* io , long baud= 57600){\n      iostream = io;\n      baud_ = baud;\n    }\n    ArduinoHardware()\n    {\n#if defined(USBCON) and !(defined(USE_USBCON))\n      /* Leonardo support */\n      iostream = &Serial2;\n#elif defined(USE_TEENSY_HW_SERIAL)\n      iostream = &Serial2;\n#else\n      iostream = &Serial;\n#endif\n      baud_ = 57600;\n    }\n    ArduinoHardware(ArduinoHardware& h){\n      this->iostream = iostream;\n      this->baud_ = h.baud_;\n    }\n\n    void setBaud(long baud){\n      this->baud_= baud;\n    }\n\n    int getBaud(){return baud_;}\n\n    void init(){\n#if defined(USE_USBCON)\n      // Startup delay as a fail-safe to upload a new sketch\n      delay(3000);\n#endif\n      iostream->begin(baud_);\n    }\n\n    int read(){return iostream->read();};\n    void write(uint8_t* data, int length)\n    {\n      //for(int i=0; i<length; i++)\n      //  iostream->write(data[i]);\n      #if 1\n      iostream->write(data, length);\n      #else\n      uint32_t t_time;\n      uint32_t tx_length;\n\n      t_time = millis();\n      while(1)\n      {\n        tx_length = iostream->write(data, length);\n\n        if(tx_length == length)\n          break;\n\n        if(millis()-t_time > 1000)\n        {\n          break;\n        }\n      }\n      #endif\n    }\n\n    unsigned long time(){return millis();}\n\n  protected:\n    SERIAL_CLASS* iostream;\n    long baud_;\n};\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/duration.cpp",
    "content": "/*\n * Software License Agreement (BSD License)\n *\n * Copyright (c) 2011, Willow Garage, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n *  * Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n *  * Redistributions in binary form must reproduce the above\n *    copyright notice, this list of conditions and the following\n *    disclaimer in the documentation and/or other materials provided\n *    with the distribution.\n *  * Neither the name of Willow Garage, Inc. nor the names of its\n *    contributors may be used to endorse or promote prducts derived\n *    from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include <math.h>\n#include \"ros/duration.h\"\n\nnamespace ros\n{\n  void normalizeSecNSecSigned(int32_t &sec, int32_t &nsec)\n  {\n    int32_t nsec_part = nsec;\n    int32_t sec_part = sec;\n\n    while (nsec_part > 1000000000L)\n    {\n      nsec_part -= 1000000000L;\n      ++sec_part;\n    }\n    while (nsec_part < 0)\n    {\n      nsec_part += 1000000000L;\n      --sec_part;\n    }\n    sec = sec_part;\n    nsec = nsec_part;\n  }\n\n  Duration& Duration::operator+=(const Duration &rhs)\n  {\n    sec += rhs.sec;\n    nsec += rhs.nsec;\n    normalizeSecNSecSigned(sec, nsec);\n    return *this;\n  }\n\n  Duration& Duration::operator-=(const Duration &rhs){\n    sec += -rhs.sec;\n    nsec += -rhs.nsec;\n    normalizeSecNSecSigned(sec, nsec);\n    return *this;\n  }\n\n  Duration& Duration::operator*=(double scale){\n    sec *= scale;\n    nsec *= scale;\n    normalizeSecNSecSigned(sec, nsec);\n    return *this;\n  }\n\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/geometry_msgs/Accel.h",
    "content": "#ifndef _ROS_geometry_msgs_Accel_h\n#define _ROS_geometry_msgs_Accel_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"geometry_msgs/Vector3.h\"\n\nnamespace geometry_msgs\n{\n\n  class Accel : public ros::Msg\n  {\n    public:\n      typedef geometry_msgs::Vector3 _linear_type;\n      _linear_type linear;\n      typedef geometry_msgs::Vector3 _angular_type;\n      _angular_type angular;\n\n    Accel():\n      linear(),\n      angular()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->linear.serialize(outbuffer + offset);\n      offset += this->angular.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->linear.deserialize(inbuffer + offset);\n      offset += this->angular.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return \"geometry_msgs/Accel\"; };\n    const char * getMD5(){ return \"9f195f881246fdfa2798d1d3eebca84a\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/geometry_msgs/AccelStamped.h",
    "content": "#ifndef _ROS_geometry_msgs_AccelStamped_h\n#define _ROS_geometry_msgs_AccelStamped_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n#include \"geometry_msgs/Accel.h\"\n\nnamespace geometry_msgs\n{\n\n  class AccelStamped : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef geometry_msgs::Accel _accel_type;\n      _accel_type accel;\n\n    AccelStamped():\n      header(),\n      accel()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      offset += this->accel.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      offset += this->accel.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return \"geometry_msgs/AccelStamped\"; };\n    const char * getMD5(){ return \"d8a98a5d81351b6eb0578c78557e7659\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/geometry_msgs/AccelWithCovariance.h",
    "content": "#ifndef _ROS_geometry_msgs_AccelWithCovariance_h\n#define _ROS_geometry_msgs_AccelWithCovariance_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"geometry_msgs/Accel.h\"\n\nnamespace geometry_msgs\n{\n\n  class AccelWithCovariance : public ros::Msg\n  {\n    public:\n      typedef geometry_msgs::Accel _accel_type;\n      _accel_type accel;\n      float covariance[36];\n\n    AccelWithCovariance():\n      accel(),\n      covariance()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->accel.serialize(outbuffer + offset);\n      for( uint32_t i = 0; i < 36; i++){\n      offset += serializeAvrFloat64(outbuffer + offset, this->covariance[i]);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->accel.deserialize(inbuffer + offset);\n      for( uint32_t i = 0; i < 36; i++){\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->covariance[i]));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"geometry_msgs/AccelWithCovariance\"; };\n    const char * getMD5(){ return \"ad5a718d699c6be72a02b8d6a139f334\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/geometry_msgs/AccelWithCovarianceStamped.h",
    "content": "#ifndef _ROS_geometry_msgs_AccelWithCovarianceStamped_h\n#define _ROS_geometry_msgs_AccelWithCovarianceStamped_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n#include \"geometry_msgs/AccelWithCovariance.h\"\n\nnamespace geometry_msgs\n{\n\n  class AccelWithCovarianceStamped : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef geometry_msgs::AccelWithCovariance _accel_type;\n      _accel_type accel;\n\n    AccelWithCovarianceStamped():\n      header(),\n      accel()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      offset += this->accel.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      offset += this->accel.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return \"geometry_msgs/AccelWithCovarianceStamped\"; };\n    const char * getMD5(){ return \"96adb295225031ec8d57fb4251b0a886\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/geometry_msgs/Inertia.h",
    "content": "#ifndef _ROS_geometry_msgs_Inertia_h\n#define _ROS_geometry_msgs_Inertia_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"geometry_msgs/Vector3.h\"\n\nnamespace geometry_msgs\n{\n\n  class Inertia : public ros::Msg\n  {\n    public:\n      typedef float _m_type;\n      _m_type m;\n      typedef geometry_msgs::Vector3 _com_type;\n      _com_type com;\n      typedef float _ixx_type;\n      _ixx_type ixx;\n      typedef float _ixy_type;\n      _ixy_type ixy;\n      typedef float _ixz_type;\n      _ixz_type ixz;\n      typedef float _iyy_type;\n      _iyy_type iyy;\n      typedef float _iyz_type;\n      _iyz_type iyz;\n      typedef float _izz_type;\n      _izz_type izz;\n\n    Inertia():\n      m(0),\n      com(),\n      ixx(0),\n      ixy(0),\n      ixz(0),\n      iyy(0),\n      iyz(0),\n      izz(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += serializeAvrFloat64(outbuffer + offset, this->m);\n      offset += this->com.serialize(outbuffer + offset);\n      offset += serializeAvrFloat64(outbuffer + offset, this->ixx);\n      offset += serializeAvrFloat64(outbuffer + offset, this->ixy);\n      offset += serializeAvrFloat64(outbuffer + offset, this->ixz);\n      offset += serializeAvrFloat64(outbuffer + offset, this->iyy);\n      offset += serializeAvrFloat64(outbuffer + offset, this->iyz);\n      offset += serializeAvrFloat64(outbuffer + offset, this->izz);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->m));\n      offset += this->com.deserialize(inbuffer + offset);\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->ixx));\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->ixy));\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->ixz));\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->iyy));\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->iyz));\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->izz));\n     return offset;\n    }\n\n    const char * getType(){ return \"geometry_msgs/Inertia\"; };\n    const char * getMD5(){ return \"1d26e4bb6c83ff141c5cf0d883c2b0fe\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/geometry_msgs/InertiaStamped.h",
    "content": "#ifndef _ROS_geometry_msgs_InertiaStamped_h\n#define _ROS_geometry_msgs_InertiaStamped_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n#include \"geometry_msgs/Inertia.h\"\n\nnamespace geometry_msgs\n{\n\n  class InertiaStamped : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef geometry_msgs::Inertia _inertia_type;\n      _inertia_type inertia;\n\n    InertiaStamped():\n      header(),\n      inertia()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      offset += this->inertia.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      offset += this->inertia.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return \"geometry_msgs/InertiaStamped\"; };\n    const char * getMD5(){ return \"ddee48caeab5a966c5e8d166654a9ac7\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/geometry_msgs/Point.h",
    "content": "#ifndef _ROS_geometry_msgs_Point_h\n#define _ROS_geometry_msgs_Point_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace geometry_msgs\n{\n\n  class Point : public ros::Msg\n  {\n    public:\n      typedef float _x_type;\n      _x_type x;\n      typedef float _y_type;\n      _y_type y;\n      typedef float _z_type;\n      _z_type z;\n\n    Point():\n      x(0),\n      y(0),\n      z(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += serializeAvrFloat64(outbuffer + offset, this->x);\n      offset += serializeAvrFloat64(outbuffer + offset, this->y);\n      offset += serializeAvrFloat64(outbuffer + offset, this->z);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->x));\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->y));\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->z));\n     return offset;\n    }\n\n    const char * getType(){ return \"geometry_msgs/Point\"; };\n    const char * getMD5(){ return \"4a842b65f413084dc2b10fb484ea7f17\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/geometry_msgs/Point32.h",
    "content": "#ifndef _ROS_geometry_msgs_Point32_h\n#define _ROS_geometry_msgs_Point32_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace geometry_msgs\n{\n\n  class Point32 : public ros::Msg\n  {\n    public:\n      typedef float _x_type;\n      _x_type x;\n      typedef float _y_type;\n      _y_type y;\n      typedef float _z_type;\n      _z_type z;\n\n    Point32():\n      x(0),\n      y(0),\n      z(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      union {\n        float real;\n        uint32_t base;\n      } u_x;\n      u_x.real = this->x;\n      *(outbuffer + offset + 0) = (u_x.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_x.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_x.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_x.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->x);\n      union {\n        float real;\n        uint32_t base;\n      } u_y;\n      u_y.real = this->y;\n      *(outbuffer + offset + 0) = (u_y.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_y.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_y.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_y.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->y);\n      union {\n        float real;\n        uint32_t base;\n      } u_z;\n      u_z.real = this->z;\n      *(outbuffer + offset + 0) = (u_z.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_z.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_z.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_z.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->z);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      union {\n        float real;\n        uint32_t base;\n      } u_x;\n      u_x.base = 0;\n      u_x.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_x.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_x.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_x.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->x = u_x.real;\n      offset += sizeof(this->x);\n      union {\n        float real;\n        uint32_t base;\n      } u_y;\n      u_y.base = 0;\n      u_y.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_y.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_y.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_y.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->y = u_y.real;\n      offset += sizeof(this->y);\n      union {\n        float real;\n        uint32_t base;\n      } u_z;\n      u_z.base = 0;\n      u_z.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_z.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_z.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_z.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->z = u_z.real;\n      offset += sizeof(this->z);\n     return offset;\n    }\n\n    const char * getType(){ return \"geometry_msgs/Point32\"; };\n    const char * getMD5(){ return \"cc153912f1453b708d221682bc23d9ac\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/geometry_msgs/PointStamped.h",
    "content": "#ifndef _ROS_geometry_msgs_PointStamped_h\n#define _ROS_geometry_msgs_PointStamped_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n#include \"geometry_msgs/Point.h\"\n\nnamespace geometry_msgs\n{\n\n  class PointStamped : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef geometry_msgs::Point _point_type;\n      _point_type point;\n\n    PointStamped():\n      header(),\n      point()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      offset += this->point.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      offset += this->point.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return \"geometry_msgs/PointStamped\"; };\n    const char * getMD5(){ return \"c63aecb41bfdfd6b7e1fac37c7cbe7bf\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/geometry_msgs/Polygon.h",
    "content": "#ifndef _ROS_geometry_msgs_Polygon_h\n#define _ROS_geometry_msgs_Polygon_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"geometry_msgs/Point32.h\"\n\nnamespace geometry_msgs\n{\n\n  class Polygon : public ros::Msg\n  {\n    public:\n      uint32_t points_length;\n      typedef geometry_msgs::Point32 _points_type;\n      _points_type st_points;\n      _points_type * points;\n\n    Polygon():\n      points_length(0), points(NULL)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      *(outbuffer + offset + 0) = (this->points_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->points_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->points_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->points_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->points_length);\n      for( uint32_t i = 0; i < points_length; i++){\n      offset += this->points[i].serialize(outbuffer + offset);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      uint32_t points_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      points_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      points_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      points_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->points_length);\n      if(points_lengthT > points_length)\n        this->points = (geometry_msgs::Point32*)realloc(this->points, points_lengthT * sizeof(geometry_msgs::Point32));\n      points_length = points_lengthT;\n      for( uint32_t i = 0; i < points_length; i++){\n      offset += this->st_points.deserialize(inbuffer + offset);\n        memcpy( &(this->points[i]), &(this->st_points), sizeof(geometry_msgs::Point32));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"geometry_msgs/Polygon\"; };\n    const char * getMD5(){ return \"cd60a26494a087f577976f0329fa120e\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/geometry_msgs/PolygonStamped.h",
    "content": "#ifndef _ROS_geometry_msgs_PolygonStamped_h\n#define _ROS_geometry_msgs_PolygonStamped_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n#include \"geometry_msgs/Polygon.h\"\n\nnamespace geometry_msgs\n{\n\n  class PolygonStamped : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef geometry_msgs::Polygon _polygon_type;\n      _polygon_type polygon;\n\n    PolygonStamped():\n      header(),\n      polygon()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      offset += this->polygon.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      offset += this->polygon.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return \"geometry_msgs/PolygonStamped\"; };\n    const char * getMD5(){ return \"c6be8f7dc3bee7fe9e8d296070f53340\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/geometry_msgs/Pose.h",
    "content": "#ifndef _ROS_geometry_msgs_Pose_h\n#define _ROS_geometry_msgs_Pose_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"geometry_msgs/Point.h\"\n#include \"geometry_msgs/Quaternion.h\"\n\nnamespace geometry_msgs\n{\n\n  class Pose : public ros::Msg\n  {\n    public:\n      typedef geometry_msgs::Point _position_type;\n      _position_type position;\n      typedef geometry_msgs::Quaternion _orientation_type;\n      _orientation_type orientation;\n\n    Pose():\n      position(),\n      orientation()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->position.serialize(outbuffer + offset);\n      offset += this->orientation.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->position.deserialize(inbuffer + offset);\n      offset += this->orientation.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return \"geometry_msgs/Pose\"; };\n    const char * getMD5(){ return \"e45d45a5a1ce597b249e23fb30fc871f\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/geometry_msgs/Pose2D.h",
    "content": "#ifndef _ROS_geometry_msgs_Pose2D_h\n#define _ROS_geometry_msgs_Pose2D_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace geometry_msgs\n{\n\n  class Pose2D : public ros::Msg\n  {\n    public:\n      typedef float _x_type;\n      _x_type x;\n      typedef float _y_type;\n      _y_type y;\n      typedef float _theta_type;\n      _theta_type theta;\n\n    Pose2D():\n      x(0),\n      y(0),\n      theta(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += serializeAvrFloat64(outbuffer + offset, this->x);\n      offset += serializeAvrFloat64(outbuffer + offset, this->y);\n      offset += serializeAvrFloat64(outbuffer + offset, this->theta);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->x));\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->y));\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->theta));\n     return offset;\n    }\n\n    const char * getType(){ return \"geometry_msgs/Pose2D\"; };\n    const char * getMD5(){ return \"938fa65709584ad8e77d238529be13b8\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/geometry_msgs/PoseArray.h",
    "content": "#ifndef _ROS_geometry_msgs_PoseArray_h\n#define _ROS_geometry_msgs_PoseArray_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n#include \"geometry_msgs/Pose.h\"\n\nnamespace geometry_msgs\n{\n\n  class PoseArray : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      uint32_t poses_length;\n      typedef geometry_msgs::Pose _poses_type;\n      _poses_type st_poses;\n      _poses_type * poses;\n\n    PoseArray():\n      header(),\n      poses_length(0), poses(NULL)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      *(outbuffer + offset + 0) = (this->poses_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->poses_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->poses_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->poses_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->poses_length);\n      for( uint32_t i = 0; i < poses_length; i++){\n      offset += this->poses[i].serialize(outbuffer + offset);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      uint32_t poses_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      poses_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      poses_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      poses_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->poses_length);\n      if(poses_lengthT > poses_length)\n        this->poses = (geometry_msgs::Pose*)realloc(this->poses, poses_lengthT * sizeof(geometry_msgs::Pose));\n      poses_length = poses_lengthT;\n      for( uint32_t i = 0; i < poses_length; i++){\n      offset += this->st_poses.deserialize(inbuffer + offset);\n        memcpy( &(this->poses[i]), &(this->st_poses), sizeof(geometry_msgs::Pose));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"geometry_msgs/PoseArray\"; };\n    const char * getMD5(){ return \"916c28c5764443f268b296bb671b9d97\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/geometry_msgs/PoseStamped.h",
    "content": "#ifndef _ROS_geometry_msgs_PoseStamped_h\n#define _ROS_geometry_msgs_PoseStamped_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n#include \"geometry_msgs/Pose.h\"\n\nnamespace geometry_msgs\n{\n\n  class PoseStamped : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef geometry_msgs::Pose _pose_type;\n      _pose_type pose;\n\n    PoseStamped():\n      header(),\n      pose()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      offset += this->pose.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      offset += this->pose.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return \"geometry_msgs/PoseStamped\"; };\n    const char * getMD5(){ return \"d3812c3cbc69362b77dc0b19b345f8f5\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/geometry_msgs/PoseWithCovariance.h",
    "content": "#ifndef _ROS_geometry_msgs_PoseWithCovariance_h\n#define _ROS_geometry_msgs_PoseWithCovariance_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"geometry_msgs/Pose.h\"\n\nnamespace geometry_msgs\n{\n\n  class PoseWithCovariance : public ros::Msg\n  {\n    public:\n      typedef geometry_msgs::Pose _pose_type;\n      _pose_type pose;\n      float covariance[36];\n\n    PoseWithCovariance():\n      pose(),\n      covariance()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->pose.serialize(outbuffer + offset);\n      for( uint32_t i = 0; i < 36; i++){\n      offset += serializeAvrFloat64(outbuffer + offset, this->covariance[i]);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->pose.deserialize(inbuffer + offset);\n      for( uint32_t i = 0; i < 36; i++){\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->covariance[i]));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"geometry_msgs/PoseWithCovariance\"; };\n    const char * getMD5(){ return \"c23e848cf1b7533a8d7c259073a97e6f\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/geometry_msgs/PoseWithCovarianceStamped.h",
    "content": "#ifndef _ROS_geometry_msgs_PoseWithCovarianceStamped_h\n#define _ROS_geometry_msgs_PoseWithCovarianceStamped_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n#include \"geometry_msgs/PoseWithCovariance.h\"\n\nnamespace geometry_msgs\n{\n\n  class PoseWithCovarianceStamped : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef geometry_msgs::PoseWithCovariance _pose_type;\n      _pose_type pose;\n\n    PoseWithCovarianceStamped():\n      header(),\n      pose()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      offset += this->pose.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      offset += this->pose.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return \"geometry_msgs/PoseWithCovarianceStamped\"; };\n    const char * getMD5(){ return \"953b798c0f514ff060a53a3498ce6246\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/geometry_msgs/Quaternion.h",
    "content": "#ifndef _ROS_geometry_msgs_Quaternion_h\n#define _ROS_geometry_msgs_Quaternion_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace geometry_msgs\n{\n\n  class Quaternion : public ros::Msg\n  {\n    public:\n      typedef float _x_type;\n      _x_type x;\n      typedef float _y_type;\n      _y_type y;\n      typedef float _z_type;\n      _z_type z;\n      typedef float _w_type;\n      _w_type w;\n\n    Quaternion():\n      x(0),\n      y(0),\n      z(0),\n      w(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += serializeAvrFloat64(outbuffer + offset, this->x);\n      offset += serializeAvrFloat64(outbuffer + offset, this->y);\n      offset += serializeAvrFloat64(outbuffer + offset, this->z);\n      offset += serializeAvrFloat64(outbuffer + offset, this->w);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->x));\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->y));\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->z));\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->w));\n     return offset;\n    }\n\n    const char * getType(){ return \"geometry_msgs/Quaternion\"; };\n    const char * getMD5(){ return \"a779879fadf0160734f906b8c19c7004\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/geometry_msgs/QuaternionStamped.h",
    "content": "#ifndef _ROS_geometry_msgs_QuaternionStamped_h\n#define _ROS_geometry_msgs_QuaternionStamped_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n#include \"geometry_msgs/Quaternion.h\"\n\nnamespace geometry_msgs\n{\n\n  class QuaternionStamped : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef geometry_msgs::Quaternion _quaternion_type;\n      _quaternion_type quaternion;\n\n    QuaternionStamped():\n      header(),\n      quaternion()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      offset += this->quaternion.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      offset += this->quaternion.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return \"geometry_msgs/QuaternionStamped\"; };\n    const char * getMD5(){ return \"e57f1e547e0e1fd13504588ffc8334e2\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/geometry_msgs/Transform.h",
    "content": "#ifndef _ROS_geometry_msgs_Transform_h\n#define _ROS_geometry_msgs_Transform_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"geometry_msgs/Vector3.h\"\n#include \"geometry_msgs/Quaternion.h\"\n\nnamespace geometry_msgs\n{\n\n  class Transform : public ros::Msg\n  {\n    public:\n      typedef geometry_msgs::Vector3 _translation_type;\n      _translation_type translation;\n      typedef geometry_msgs::Quaternion _rotation_type;\n      _rotation_type rotation;\n\n    Transform():\n      translation(),\n      rotation()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->translation.serialize(outbuffer + offset);\n      offset += this->rotation.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->translation.deserialize(inbuffer + offset);\n      offset += this->rotation.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return \"geometry_msgs/Transform\"; };\n    const char * getMD5(){ return \"ac9eff44abf714214112b05d54a3cf9b\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/geometry_msgs/TransformStamped.h",
    "content": "#ifndef _ROS_geometry_msgs_TransformStamped_h\n#define _ROS_geometry_msgs_TransformStamped_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n#include \"geometry_msgs/Transform.h\"\n\nnamespace geometry_msgs\n{\n\n  class TransformStamped : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef const char* _child_frame_id_type;\n      _child_frame_id_type child_frame_id;\n      typedef geometry_msgs::Transform _transform_type;\n      _transform_type transform;\n\n    TransformStamped():\n      header(),\n      child_frame_id(\"\"),\n      transform()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      uint32_t length_child_frame_id = strlen(this->child_frame_id);\n      varToArr(outbuffer + offset, length_child_frame_id);\n      offset += 4;\n      memcpy(outbuffer + offset, this->child_frame_id, length_child_frame_id);\n      offset += length_child_frame_id;\n      offset += this->transform.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      uint32_t length_child_frame_id;\n      arrToVar(length_child_frame_id, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_child_frame_id; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_child_frame_id-1]=0;\n      this->child_frame_id = (char *)(inbuffer + offset-1);\n      offset += length_child_frame_id;\n      offset += this->transform.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return \"geometry_msgs/TransformStamped\"; };\n    const char * getMD5(){ return \"b5764a33bfeb3588febc2682852579b0\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/geometry_msgs/Twist.h",
    "content": "#ifndef _ROS_geometry_msgs_Twist_h\n#define _ROS_geometry_msgs_Twist_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"geometry_msgs/Vector3.h\"\n\nnamespace geometry_msgs\n{\n\n  class Twist : public ros::Msg\n  {\n    public:\n      typedef geometry_msgs::Vector3 _linear_type;\n      _linear_type linear;\n      typedef geometry_msgs::Vector3 _angular_type;\n      _angular_type angular;\n\n    Twist():\n      linear(),\n      angular()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->linear.serialize(outbuffer + offset);\n      offset += this->angular.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->linear.deserialize(inbuffer + offset);\n      offset += this->angular.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return \"geometry_msgs/Twist\"; };\n    const char * getMD5(){ return \"9f195f881246fdfa2798d1d3eebca84a\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/geometry_msgs/TwistStamped.h",
    "content": "#ifndef _ROS_geometry_msgs_TwistStamped_h\n#define _ROS_geometry_msgs_TwistStamped_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n#include \"geometry_msgs/Twist.h\"\n\nnamespace geometry_msgs\n{\n\n  class TwistStamped : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef geometry_msgs::Twist _twist_type;\n      _twist_type twist;\n\n    TwistStamped():\n      header(),\n      twist()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      offset += this->twist.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      offset += this->twist.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return \"geometry_msgs/TwistStamped\"; };\n    const char * getMD5(){ return \"98d34b0043a2093cf9d9345ab6eef12e\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/geometry_msgs/TwistWithCovariance.h",
    "content": "#ifndef _ROS_geometry_msgs_TwistWithCovariance_h\n#define _ROS_geometry_msgs_TwistWithCovariance_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"geometry_msgs/Twist.h\"\n\nnamespace geometry_msgs\n{\n\n  class TwistWithCovariance : public ros::Msg\n  {\n    public:\n      typedef geometry_msgs::Twist _twist_type;\n      _twist_type twist;\n      float covariance[36];\n\n    TwistWithCovariance():\n      twist(),\n      covariance()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->twist.serialize(outbuffer + offset);\n      for( uint32_t i = 0; i < 36; i++){\n      offset += serializeAvrFloat64(outbuffer + offset, this->covariance[i]);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->twist.deserialize(inbuffer + offset);\n      for( uint32_t i = 0; i < 36; i++){\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->covariance[i]));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"geometry_msgs/TwistWithCovariance\"; };\n    const char * getMD5(){ return \"1fe8a28e6890a4cc3ae4c3ca5c7d82e6\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/geometry_msgs/TwistWithCovarianceStamped.h",
    "content": "#ifndef _ROS_geometry_msgs_TwistWithCovarianceStamped_h\n#define _ROS_geometry_msgs_TwistWithCovarianceStamped_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n#include \"geometry_msgs/TwistWithCovariance.h\"\n\nnamespace geometry_msgs\n{\n\n  class TwistWithCovarianceStamped : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef geometry_msgs::TwistWithCovariance _twist_type;\n      _twist_type twist;\n\n    TwistWithCovarianceStamped():\n      header(),\n      twist()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      offset += this->twist.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      offset += this->twist.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return \"geometry_msgs/TwistWithCovarianceStamped\"; };\n    const char * getMD5(){ return \"8927a1a12fb2607ceea095b2dc440a96\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/geometry_msgs/Vector3.h",
    "content": "#ifndef _ROS_geometry_msgs_Vector3_h\n#define _ROS_geometry_msgs_Vector3_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace geometry_msgs\n{\n\n  class Vector3 : public ros::Msg\n  {\n    public:\n      typedef float _x_type;\n      _x_type x;\n      typedef float _y_type;\n      _y_type y;\n      typedef float _z_type;\n      _z_type z;\n\n    Vector3():\n      x(0),\n      y(0),\n      z(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += serializeAvrFloat64(outbuffer + offset, this->x);\n      offset += serializeAvrFloat64(outbuffer + offset, this->y);\n      offset += serializeAvrFloat64(outbuffer + offset, this->z);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->x));\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->y));\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->z));\n     return offset;\n    }\n\n    const char * getType(){ return \"geometry_msgs/Vector3\"; };\n    const char * getMD5(){ return \"4a842b65f413084dc2b10fb484ea7f17\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/geometry_msgs/Vector3Stamped.h",
    "content": "#ifndef _ROS_geometry_msgs_Vector3Stamped_h\n#define _ROS_geometry_msgs_Vector3Stamped_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n#include \"geometry_msgs/Vector3.h\"\n\nnamespace geometry_msgs\n{\n\n  class Vector3Stamped : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef geometry_msgs::Vector3 _vector_type;\n      _vector_type vector;\n\n    Vector3Stamped():\n      header(),\n      vector()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      offset += this->vector.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      offset += this->vector.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return \"geometry_msgs/Vector3Stamped\"; };\n    const char * getMD5(){ return \"7b324c7325e683bf02a9b14b01090ec7\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/geometry_msgs/Wrench.h",
    "content": "#ifndef _ROS_geometry_msgs_Wrench_h\n#define _ROS_geometry_msgs_Wrench_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"geometry_msgs/Vector3.h\"\n\nnamespace geometry_msgs\n{\n\n  class Wrench : public ros::Msg\n  {\n    public:\n      typedef geometry_msgs::Vector3 _force_type;\n      _force_type force;\n      typedef geometry_msgs::Vector3 _torque_type;\n      _torque_type torque;\n\n    Wrench():\n      force(),\n      torque()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->force.serialize(outbuffer + offset);\n      offset += this->torque.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->force.deserialize(inbuffer + offset);\n      offset += this->torque.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return \"geometry_msgs/Wrench\"; };\n    const char * getMD5(){ return \"4f539cf138b23283b520fd271b567936\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/geometry_msgs/WrenchStamped.h",
    "content": "#ifndef _ROS_geometry_msgs_WrenchStamped_h\n#define _ROS_geometry_msgs_WrenchStamped_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n#include \"geometry_msgs/Wrench.h\"\n\nnamespace geometry_msgs\n{\n\n  class WrenchStamped : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef geometry_msgs::Wrench _wrench_type;\n      _wrench_type wrench;\n\n    WrenchStamped():\n      header(),\n      wrench()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      offset += this->wrench.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      offset += this->wrench.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return \"geometry_msgs/WrenchStamped\"; };\n    const char * getMD5(){ return \"d78d3cb249ce23087ade7e7d0c40cfa7\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/nav_msgs/GetMap.h",
    "content": "#ifndef _ROS_SERVICE_GetMap_h\n#define _ROS_SERVICE_GetMap_h\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"nav_msgs/OccupancyGrid.h\"\n\nnamespace nav_msgs\n{\n\nstatic const char GETMAP[] = \"nav_msgs/GetMap\";\n\n  class GetMapRequest : public ros::Msg\n  {\n    public:\n\n    GetMapRequest()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n     return offset;\n    }\n\n    const char * getType(){ return GETMAP; };\n    const char * getMD5(){ return \"d41d8cd98f00b204e9800998ecf8427e\"; };\n\n  };\n\n  class GetMapResponse : public ros::Msg\n  {\n    public:\n      typedef nav_msgs::OccupancyGrid _map_type;\n      _map_type map;\n\n    GetMapResponse():\n      map()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->map.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->map.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return GETMAP; };\n    const char * getMD5(){ return \"6cdd0a18e0aff5b0a3ca2326a89b54ff\"; };\n\n  };\n\n  class GetMap {\n    public:\n    typedef GetMapRequest Request;\n    typedef GetMapResponse Response;\n  };\n\n}\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/nav_msgs/GetMapAction.h",
    "content": "#ifndef _ROS_nav_msgs_GetMapAction_h\n#define _ROS_nav_msgs_GetMapAction_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"nav_msgs/GetMapActionGoal.h\"\n#include \"nav_msgs/GetMapActionResult.h\"\n#include \"nav_msgs/GetMapActionFeedback.h\"\n\nnamespace nav_msgs\n{\n\n  class GetMapAction : public ros::Msg\n  {\n    public:\n      typedef nav_msgs::GetMapActionGoal _action_goal_type;\n      _action_goal_type action_goal;\n      typedef nav_msgs::GetMapActionResult _action_result_type;\n      _action_result_type action_result;\n      typedef nav_msgs::GetMapActionFeedback _action_feedback_type;\n      _action_feedback_type action_feedback;\n\n    GetMapAction():\n      action_goal(),\n      action_result(),\n      action_feedback()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->action_goal.serialize(outbuffer + offset);\n      offset += this->action_result.serialize(outbuffer + offset);\n      offset += this->action_feedback.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->action_goal.deserialize(inbuffer + offset);\n      offset += this->action_result.deserialize(inbuffer + offset);\n      offset += this->action_feedback.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return \"nav_msgs/GetMapAction\"; };\n    const char * getMD5(){ return \"e611ad23fbf237c031b7536416dc7cd7\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/nav_msgs/GetMapActionFeedback.h",
    "content": "#ifndef _ROS_nav_msgs_GetMapActionFeedback_h\n#define _ROS_nav_msgs_GetMapActionFeedback_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n#include \"actionlib_msgs/GoalStatus.h\"\n#include \"nav_msgs/GetMapFeedback.h\"\n\nnamespace nav_msgs\n{\n\n  class GetMapActionFeedback : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef actionlib_msgs::GoalStatus _status_type;\n      _status_type status;\n      typedef nav_msgs::GetMapFeedback _feedback_type;\n      _feedback_type feedback;\n\n    GetMapActionFeedback():\n      header(),\n      status(),\n      feedback()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      offset += this->status.serialize(outbuffer + offset);\n      offset += this->feedback.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      offset += this->status.deserialize(inbuffer + offset);\n      offset += this->feedback.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return \"nav_msgs/GetMapActionFeedback\"; };\n    const char * getMD5(){ return \"aae20e09065c3809e8a8e87c4c8953fd\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/nav_msgs/GetMapActionGoal.h",
    "content": "#ifndef _ROS_nav_msgs_GetMapActionGoal_h\n#define _ROS_nav_msgs_GetMapActionGoal_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n#include \"actionlib_msgs/GoalID.h\"\n#include \"nav_msgs/GetMapGoal.h\"\n\nnamespace nav_msgs\n{\n\n  class GetMapActionGoal : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef actionlib_msgs::GoalID _goal_id_type;\n      _goal_id_type goal_id;\n      typedef nav_msgs::GetMapGoal _goal_type;\n      _goal_type goal;\n\n    GetMapActionGoal():\n      header(),\n      goal_id(),\n      goal()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      offset += this->goal_id.serialize(outbuffer + offset);\n      offset += this->goal.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      offset += this->goal_id.deserialize(inbuffer + offset);\n      offset += this->goal.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return \"nav_msgs/GetMapActionGoal\"; };\n    const char * getMD5(){ return \"4b30be6cd12b9e72826df56b481f40e0\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/nav_msgs/GetMapActionResult.h",
    "content": "#ifndef _ROS_nav_msgs_GetMapActionResult_h\n#define _ROS_nav_msgs_GetMapActionResult_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n#include \"actionlib_msgs/GoalStatus.h\"\n#include \"nav_msgs/GetMapResult.h\"\n\nnamespace nav_msgs\n{\n\n  class GetMapActionResult : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef actionlib_msgs::GoalStatus _status_type;\n      _status_type status;\n      typedef nav_msgs::GetMapResult _result_type;\n      _result_type result;\n\n    GetMapActionResult():\n      header(),\n      status(),\n      result()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      offset += this->status.serialize(outbuffer + offset);\n      offset += this->result.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      offset += this->status.deserialize(inbuffer + offset);\n      offset += this->result.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return \"nav_msgs/GetMapActionResult\"; };\n    const char * getMD5(){ return \"ac66e5b9a79bb4bbd33dab245236c892\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/nav_msgs/GetMapFeedback.h",
    "content": "#ifndef _ROS_nav_msgs_GetMapFeedback_h\n#define _ROS_nav_msgs_GetMapFeedback_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace nav_msgs\n{\n\n  class GetMapFeedback : public ros::Msg\n  {\n    public:\n\n    GetMapFeedback()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n     return offset;\n    }\n\n    const char * getType(){ return \"nav_msgs/GetMapFeedback\"; };\n    const char * getMD5(){ return \"d41d8cd98f00b204e9800998ecf8427e\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/nav_msgs/GetMapGoal.h",
    "content": "#ifndef _ROS_nav_msgs_GetMapGoal_h\n#define _ROS_nav_msgs_GetMapGoal_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace nav_msgs\n{\n\n  class GetMapGoal : public ros::Msg\n  {\n    public:\n\n    GetMapGoal()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n     return offset;\n    }\n\n    const char * getType(){ return \"nav_msgs/GetMapGoal\"; };\n    const char * getMD5(){ return \"d41d8cd98f00b204e9800998ecf8427e\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/nav_msgs/GetMapResult.h",
    "content": "#ifndef _ROS_nav_msgs_GetMapResult_h\n#define _ROS_nav_msgs_GetMapResult_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"nav_msgs/OccupancyGrid.h\"\n\nnamespace nav_msgs\n{\n\n  class GetMapResult : public ros::Msg\n  {\n    public:\n      typedef nav_msgs::OccupancyGrid _map_type;\n      _map_type map;\n\n    GetMapResult():\n      map()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->map.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->map.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return \"nav_msgs/GetMapResult\"; };\n    const char * getMD5(){ return \"6cdd0a18e0aff5b0a3ca2326a89b54ff\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/nav_msgs/GetPlan.h",
    "content": "#ifndef _ROS_SERVICE_GetPlan_h\n#define _ROS_SERVICE_GetPlan_h\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"geometry_msgs/PoseStamped.h\"\n#include \"nav_msgs/Path.h\"\n\nnamespace nav_msgs\n{\n\nstatic const char GETPLAN[] = \"nav_msgs/GetPlan\";\n\n  class GetPlanRequest : public ros::Msg\n  {\n    public:\n      typedef geometry_msgs::PoseStamped _start_type;\n      _start_type start;\n      typedef geometry_msgs::PoseStamped _goal_type;\n      _goal_type goal;\n      typedef float _tolerance_type;\n      _tolerance_type tolerance;\n\n    GetPlanRequest():\n      start(),\n      goal(),\n      tolerance(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->start.serialize(outbuffer + offset);\n      offset += this->goal.serialize(outbuffer + offset);\n      union {\n        float real;\n        uint32_t base;\n      } u_tolerance;\n      u_tolerance.real = this->tolerance;\n      *(outbuffer + offset + 0) = (u_tolerance.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_tolerance.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_tolerance.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_tolerance.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->tolerance);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->start.deserialize(inbuffer + offset);\n      offset += this->goal.deserialize(inbuffer + offset);\n      union {\n        float real;\n        uint32_t base;\n      } u_tolerance;\n      u_tolerance.base = 0;\n      u_tolerance.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_tolerance.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_tolerance.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_tolerance.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->tolerance = u_tolerance.real;\n      offset += sizeof(this->tolerance);\n     return offset;\n    }\n\n    const char * getType(){ return GETPLAN; };\n    const char * getMD5(){ return \"e25a43e0752bcca599a8c2eef8282df8\"; };\n\n  };\n\n  class GetPlanResponse : public ros::Msg\n  {\n    public:\n      typedef nav_msgs::Path _plan_type;\n      _plan_type plan;\n\n    GetPlanResponse():\n      plan()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->plan.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->plan.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return GETPLAN; };\n    const char * getMD5(){ return \"0002bc113c0259d71f6cf8cbc9430e18\"; };\n\n  };\n\n  class GetPlan {\n    public:\n    typedef GetPlanRequest Request;\n    typedef GetPlanResponse Response;\n  };\n\n}\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/nav_msgs/GridCells.h",
    "content": "#ifndef _ROS_nav_msgs_GridCells_h\n#define _ROS_nav_msgs_GridCells_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n#include \"geometry_msgs/Point.h\"\n\nnamespace nav_msgs\n{\n\n  class GridCells : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef float _cell_width_type;\n      _cell_width_type cell_width;\n      typedef float _cell_height_type;\n      _cell_height_type cell_height;\n      uint32_t cells_length;\n      typedef geometry_msgs::Point _cells_type;\n      _cells_type st_cells;\n      _cells_type * cells;\n\n    GridCells():\n      header(),\n      cell_width(0),\n      cell_height(0),\n      cells_length(0), cells(NULL)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      union {\n        float real;\n        uint32_t base;\n      } u_cell_width;\n      u_cell_width.real = this->cell_width;\n      *(outbuffer + offset + 0) = (u_cell_width.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_cell_width.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_cell_width.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_cell_width.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->cell_width);\n      union {\n        float real;\n        uint32_t base;\n      } u_cell_height;\n      u_cell_height.real = this->cell_height;\n      *(outbuffer + offset + 0) = (u_cell_height.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_cell_height.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_cell_height.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_cell_height.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->cell_height);\n      *(outbuffer + offset + 0) = (this->cells_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->cells_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->cells_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->cells_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->cells_length);\n      for( uint32_t i = 0; i < cells_length; i++){\n      offset += this->cells[i].serialize(outbuffer + offset);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      union {\n        float real;\n        uint32_t base;\n      } u_cell_width;\n      u_cell_width.base = 0;\n      u_cell_width.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_cell_width.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_cell_width.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_cell_width.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->cell_width = u_cell_width.real;\n      offset += sizeof(this->cell_width);\n      union {\n        float real;\n        uint32_t base;\n      } u_cell_height;\n      u_cell_height.base = 0;\n      u_cell_height.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_cell_height.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_cell_height.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_cell_height.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->cell_height = u_cell_height.real;\n      offset += sizeof(this->cell_height);\n      uint32_t cells_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      cells_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      cells_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      cells_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->cells_length);\n      if(cells_lengthT > cells_length)\n        this->cells = (geometry_msgs::Point*)realloc(this->cells, cells_lengthT * sizeof(geometry_msgs::Point));\n      cells_length = cells_lengthT;\n      for( uint32_t i = 0; i < cells_length; i++){\n      offset += this->st_cells.deserialize(inbuffer + offset);\n        memcpy( &(this->cells[i]), &(this->st_cells), sizeof(geometry_msgs::Point));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"nav_msgs/GridCells\"; };\n    const char * getMD5(){ return \"b9e4f5df6d28e272ebde00a3994830f5\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/nav_msgs/MapMetaData.h",
    "content": "#ifndef _ROS_nav_msgs_MapMetaData_h\n#define _ROS_nav_msgs_MapMetaData_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"ros/time.h\"\n#include \"geometry_msgs/Pose.h\"\n\nnamespace nav_msgs\n{\n\n  class MapMetaData : public ros::Msg\n  {\n    public:\n      typedef ros::Time _map_load_time_type;\n      _map_load_time_type map_load_time;\n      typedef float _resolution_type;\n      _resolution_type resolution;\n      typedef uint32_t _width_type;\n      _width_type width;\n      typedef uint32_t _height_type;\n      _height_type height;\n      typedef geometry_msgs::Pose _origin_type;\n      _origin_type origin;\n\n    MapMetaData():\n      map_load_time(),\n      resolution(0),\n      width(0),\n      height(0),\n      origin()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      *(outbuffer + offset + 0) = (this->map_load_time.sec >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->map_load_time.sec >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->map_load_time.sec >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->map_load_time.sec >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->map_load_time.sec);\n      *(outbuffer + offset + 0) = (this->map_load_time.nsec >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->map_load_time.nsec >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->map_load_time.nsec >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->map_load_time.nsec >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->map_load_time.nsec);\n      union {\n        float real;\n        uint32_t base;\n      } u_resolution;\n      u_resolution.real = this->resolution;\n      *(outbuffer + offset + 0) = (u_resolution.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_resolution.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_resolution.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_resolution.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->resolution);\n      *(outbuffer + offset + 0) = (this->width >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->width >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->width >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->width >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->width);\n      *(outbuffer + offset + 0) = (this->height >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->height >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->height >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->height >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->height);\n      offset += this->origin.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      this->map_load_time.sec =  ((uint32_t) (*(inbuffer + offset)));\n      this->map_load_time.sec |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->map_load_time.sec |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->map_load_time.sec |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->map_load_time.sec);\n      this->map_load_time.nsec =  ((uint32_t) (*(inbuffer + offset)));\n      this->map_load_time.nsec |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->map_load_time.nsec |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->map_load_time.nsec |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->map_load_time.nsec);\n      union {\n        float real;\n        uint32_t base;\n      } u_resolution;\n      u_resolution.base = 0;\n      u_resolution.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_resolution.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_resolution.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_resolution.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->resolution = u_resolution.real;\n      offset += sizeof(this->resolution);\n      this->width =  ((uint32_t) (*(inbuffer + offset)));\n      this->width |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->width |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->width |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->width);\n      this->height =  ((uint32_t) (*(inbuffer + offset)));\n      this->height |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->height |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->height |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->height);\n      offset += this->origin.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return \"nav_msgs/MapMetaData\"; };\n    const char * getMD5(){ return \"10cfc8a2818024d3248802c00c95f11b\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/nav_msgs/OccupancyGrid.h",
    "content": "#ifndef _ROS_nav_msgs_OccupancyGrid_h\n#define _ROS_nav_msgs_OccupancyGrid_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n#include \"nav_msgs/MapMetaData.h\"\n\nnamespace nav_msgs\n{\n\n  class OccupancyGrid : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef nav_msgs::MapMetaData _info_type;\n      _info_type info;\n      uint32_t data_length;\n      typedef int8_t _data_type;\n      _data_type st_data;\n      _data_type * data;\n\n    OccupancyGrid():\n      header(),\n      info(),\n      data_length(0), data(NULL)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      offset += this->info.serialize(outbuffer + offset);\n      *(outbuffer + offset + 0) = (this->data_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->data_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->data_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->data_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->data_length);\n      for( uint32_t i = 0; i < data_length; i++){\n      union {\n        int8_t real;\n        uint8_t base;\n      } u_datai;\n      u_datai.real = this->data[i];\n      *(outbuffer + offset + 0) = (u_datai.base >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->data[i]);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      offset += this->info.deserialize(inbuffer + offset);\n      uint32_t data_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->data_length);\n      if(data_lengthT > data_length)\n        this->data = (int8_t*)realloc(this->data, data_lengthT * sizeof(int8_t));\n      data_length = data_lengthT;\n      for( uint32_t i = 0; i < data_length; i++){\n      union {\n        int8_t real;\n        uint8_t base;\n      } u_st_data;\n      u_st_data.base = 0;\n      u_st_data.base |= ((uint8_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      this->st_data = u_st_data.real;\n      offset += sizeof(this->st_data);\n        memcpy( &(this->data[i]), &(this->st_data), sizeof(int8_t));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"nav_msgs/OccupancyGrid\"; };\n    const char * getMD5(){ return \"3381f2d731d4076ec5c71b0759edbe4e\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/nav_msgs/Odometry.h",
    "content": "#ifndef _ROS_nav_msgs_Odometry_h\n#define _ROS_nav_msgs_Odometry_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n#include \"geometry_msgs/PoseWithCovariance.h\"\n#include \"geometry_msgs/TwistWithCovariance.h\"\n\nnamespace nav_msgs\n{\n\n  class Odometry : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef const char* _child_frame_id_type;\n      _child_frame_id_type child_frame_id;\n      typedef geometry_msgs::PoseWithCovariance _pose_type;\n      _pose_type pose;\n      typedef geometry_msgs::TwistWithCovariance _twist_type;\n      _twist_type twist;\n\n    Odometry():\n      header(),\n      child_frame_id(\"\"),\n      pose(),\n      twist()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      uint32_t length_child_frame_id = strlen(this->child_frame_id);\n      varToArr(outbuffer + offset, length_child_frame_id);\n      offset += 4;\n      memcpy(outbuffer + offset, this->child_frame_id, length_child_frame_id);\n      offset += length_child_frame_id;\n      offset += this->pose.serialize(outbuffer + offset);\n      offset += this->twist.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      uint32_t length_child_frame_id;\n      arrToVar(length_child_frame_id, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_child_frame_id; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_child_frame_id-1]=0;\n      this->child_frame_id = (char *)(inbuffer + offset-1);\n      offset += length_child_frame_id;\n      offset += this->pose.deserialize(inbuffer + offset);\n      offset += this->twist.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return \"nav_msgs/Odometry\"; };\n    const char * getMD5(){ return \"cd5e73d190d741a2f92e81eda573aca7\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/nav_msgs/Path.h",
    "content": "#ifndef _ROS_nav_msgs_Path_h\n#define _ROS_nav_msgs_Path_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n#include \"geometry_msgs/PoseStamped.h\"\n\nnamespace nav_msgs\n{\n\n  class Path : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      uint32_t poses_length;\n      typedef geometry_msgs::PoseStamped _poses_type;\n      _poses_type st_poses;\n      _poses_type * poses;\n\n    Path():\n      header(),\n      poses_length(0), poses(NULL)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      *(outbuffer + offset + 0) = (this->poses_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->poses_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->poses_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->poses_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->poses_length);\n      for( uint32_t i = 0; i < poses_length; i++){\n      offset += this->poses[i].serialize(outbuffer + offset);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      uint32_t poses_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      poses_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      poses_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      poses_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->poses_length);\n      if(poses_lengthT > poses_length)\n        this->poses = (geometry_msgs::PoseStamped*)realloc(this->poses, poses_lengthT * sizeof(geometry_msgs::PoseStamped));\n      poses_length = poses_lengthT;\n      for( uint32_t i = 0; i < poses_length; i++){\n      offset += this->st_poses.deserialize(inbuffer + offset);\n        memcpy( &(this->poses[i]), &(this->st_poses), sizeof(geometry_msgs::PoseStamped));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"nav_msgs/Path\"; };\n    const char * getMD5(){ return \"6227e2b7e9cce15051f669a5e197bbf7\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/nav_msgs/SetMap.h",
    "content": "#ifndef _ROS_SERVICE_SetMap_h\n#define _ROS_SERVICE_SetMap_h\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"nav_msgs/OccupancyGrid.h\"\n#include \"geometry_msgs/PoseWithCovarianceStamped.h\"\n\nnamespace nav_msgs\n{\n\nstatic const char SETMAP[] = \"nav_msgs/SetMap\";\n\n  class SetMapRequest : public ros::Msg\n  {\n    public:\n      typedef nav_msgs::OccupancyGrid _map_type;\n      _map_type map;\n      typedef geometry_msgs::PoseWithCovarianceStamped _initial_pose_type;\n      _initial_pose_type initial_pose;\n\n    SetMapRequest():\n      map(),\n      initial_pose()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->map.serialize(outbuffer + offset);\n      offset += this->initial_pose.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->map.deserialize(inbuffer + offset);\n      offset += this->initial_pose.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return SETMAP; };\n    const char * getMD5(){ return \"91149a20d7be299b87c340df8cc94fd4\"; };\n\n  };\n\n  class SetMapResponse : public ros::Msg\n  {\n    public:\n      typedef bool _success_type;\n      _success_type success;\n\n    SetMapResponse():\n      success(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      union {\n        bool real;\n        uint8_t base;\n      } u_success;\n      u_success.real = this->success;\n      *(outbuffer + offset + 0) = (u_success.base >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->success);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      union {\n        bool real;\n        uint8_t base;\n      } u_success;\n      u_success.base = 0;\n      u_success.base |= ((uint8_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      this->success = u_success.real;\n      offset += sizeof(this->success);\n     return offset;\n    }\n\n    const char * getType(){ return SETMAP; };\n    const char * getMD5(){ return \"358e233cde0c8a8bcfea4ce193f8fc15\"; };\n\n  };\n\n  class SetMap {\n    public:\n    typedef SetMapRequest Request;\n    typedef SetMapResponse Response;\n  };\n\n}\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/ros/duration.h",
    "content": "/*\n * Software License Agreement (BSD License)\n *\n * Copyright (c) 2011, Willow Garage, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n *  * Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n *  * Redistributions in binary form must reproduce the above\n *    copyright notice, this list of conditions and the following\n *    disclaimer in the documentation and/or other materials provided\n *    with the distribution.\n *  * Neither the name of Willow Garage, Inc. nor the names of its\n *    contributors may be used to endorse or promote prducts derived\n *    from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _ROS_DURATION_H_\n#define _ROS_DURATION_H_\n\n#include <math.h>\n#include <stdint.h>\n\nnamespace ros\n{\n\nvoid normalizeSecNSecSigned(int32_t& sec, int32_t& nsec);\n\nclass Duration\n{\npublic:\n  int32_t sec, nsec;\n\n  Duration() : sec(0), nsec(0) {}\n  Duration(int32_t _sec, int32_t _nsec) : sec(_sec), nsec(_nsec)\n  {\n    normalizeSecNSecSigned(sec, nsec);\n  }\n\n  double toSec() const\n  {\n    return (double)sec + 1e-9 * (double)nsec;\n  };\n  void fromSec(double t)\n  {\n    sec = (uint32_t) floor(t);\n    nsec = (uint32_t) round((t - sec) * 1e9);\n  };\n\n  Duration& operator+=(const Duration &rhs);\n  Duration& operator-=(const Duration &rhs);\n  Duration& operator*=(double scale);\n};\n\n}\n\n#endif\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/ros/msg.h",
    "content": "/*\n * Software License Agreement (BSD License)\n *\n * Copyright (c) 2011, Willow Garage, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n *  * Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n *  * Redistributions in binary form must reproduce the above\n *    copyright notice, this list of conditions and the following\n *    disclaimer in the documentation and/or other materials provided\n *    with the distribution.\n *  * Neither the name of Willow Garage, Inc. nor the names of its\n *    contributors may be used to endorse or promote prducts derived\n *    from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _ROS_MSG_H_\n#define _ROS_MSG_H_\n\n#include <stdint.h>\n#include <stddef.h>\n\nnamespace ros\n{\n\n/* Base Message Type */\nclass Msg\n{\npublic:\n  virtual int serialize(unsigned char *outbuffer) const = 0;\n  virtual int deserialize(unsigned char *data) = 0;\n  virtual const char * getType() = 0;\n  virtual const char * getMD5() = 0;\n\n  /**\n   * @brief This tricky function handles promoting a 32bit float to a 64bit\n   *        double, so that AVR can publish messages containing float64\n   *        fields, despite AVV having no native support for double.\n   *\n   * @param[out] outbuffer pointer for buffer to serialize to.\n   * @param[in] f value to serialize.\n   *\n   * @return number of bytes to advance the buffer pointer.\n   *\n   */\n  static int serializeAvrFloat64(unsigned char* outbuffer, const float f)\n  {\n    const int32_t* val = (int32_t*) &f;\n    int32_t exp = ((*val >> 23) & 255);\n    if (exp != 0)\n    {\n      exp += 1023 - 127;\n    }\n\n    int32_t sig = *val;\n    *(outbuffer++) = 0;\n    *(outbuffer++) = 0;\n    *(outbuffer++) = 0;\n    *(outbuffer++) = (sig << 5) & 0xff;\n    *(outbuffer++) = (sig >> 3) & 0xff;\n    *(outbuffer++) = (sig >> 11) & 0xff;\n    *(outbuffer++) = ((exp << 4) & 0xF0) | ((sig >> 19) & 0x0F);\n    *(outbuffer++) = (exp >> 4) & 0x7F;\n\n    // Mark negative bit as necessary.\n    if (f < 0)\n    {\n      *(outbuffer - 1) |= 0x80;\n    }\n\n    return 8;\n  }\n\n  /**\n   * @brief This tricky function handles demoting a 64bit double to a\n   *        32bit float, so that AVR can understand messages containing\n   *        float64 fields, despite AVR having no native support for double.\n   *\n   * @param[in] inbuffer pointer for buffer to deserialize from.\n   * @param[out] f pointer to place the deserialized value in.\n   *\n   * @return number of bytes to advance the buffer pointer.\n   */\n  static int deserializeAvrFloat64(const unsigned char* inbuffer, float* f)\n  {\n    uint32_t* val = (uint32_t*)f;\n    inbuffer += 3;\n\n    // Copy truncated mantissa.\n    *val = ((uint32_t)(*(inbuffer++)) >> 5 & 0x07);\n    *val |= ((uint32_t)(*(inbuffer++)) & 0xff) << 3;\n    *val |= ((uint32_t)(*(inbuffer++)) & 0xff) << 11;\n    *val |= ((uint32_t)(*inbuffer) & 0x0f) << 19;\n\n    // Copy truncated exponent.\n    uint32_t exp = ((uint32_t)(*(inbuffer++)) & 0xf0) >> 4;\n    exp |= ((uint32_t)(*inbuffer) & 0x7f) << 4;\n    if (exp != 0)\n    {\n      *val |= ((exp) - 1023 + 127) << 23;\n    }\n\n    // Copy negative sign.\n    *val |= ((uint32_t)(*(inbuffer++)) & 0x80) << 24;\n\n    return 8;\n  }\n\n  // Copy data from variable into a byte array\n  template<typename A, typename V>\n  static void varToArr(A arr, const V var)\n  {\n    for (size_t i = 0; i < sizeof(V); i++)\n      arr[i] = (var >> (8 * i));\n  }\n\n  // Copy data from a byte array into variable\n  template<typename V, typename A>\n  static void arrToVar(V& var, const A arr)\n  {\n    var = 0;\n    for (size_t i = 0; i < sizeof(V); i++)\n      var |= (arr[i] << (8 * i));\n  }\n\n};\n\n}  // namespace ros\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/ros/node_handle.h",
    "content": "/*\n * Software License Agreement (BSD License)\n *\n * Copyright (c) 2011, Willow Garage, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n *  * Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n *  * Redistributions in binary form must reproduce the above\n *    copyright notice, this list of conditions and the following\n *    disclaimer in the documentation and/or other materials provided\n *    with the distribution.\n *  * Neither the name of Willow Garage, Inc. nor the names of its\n *    contributors may be used to endorse or promote prducts derived\n *    from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef ROS_NODE_HANDLE_H_\n#define ROS_NODE_HANDLE_H_\n\n#include <stdint.h>\n\n#include \"std_msgs/Time.h\"\n#include \"rosserial_msgs/TopicInfo.h\"\n#include \"rosserial_msgs/Log.h\"\n#include \"rosserial_msgs/RequestParam.h\"\n\n#include \"ros/msg.h\"\n\nnamespace ros\n{\n\nclass NodeHandleBase_\n{\npublic:\n  virtual int publish(int id, const Msg* msg) = 0;\n  virtual int spinOnce() = 0;\n  virtual bool connected() = 0;\n};\n}\n\n#include \"ros/publisher.h\"\n#include \"ros/subscriber.h\"\n#include \"ros/service_server.h\"\n#include \"ros/service_client.h\"\n\nnamespace ros\n{\n\nconst int SPIN_OK = 0;\nconst int SPIN_ERR = -1;\nconst int SPIN_TIMEOUT = -2;\n\nconst uint8_t SYNC_SECONDS  = 5;\nconst uint8_t MODE_FIRST_FF = 0;\n/*\n * The second sync byte is a protocol version. It's value is 0xff for the first\n * version of the rosserial protocol (used up to hydro), 0xfe for the second version\n * (introduced in hydro), 0xfd for the next, and so on. Its purpose is to enable\n * detection of mismatched protocol versions (e.g. hydro rosserial_python with groovy\n * rosserial_arduino. It must be changed in both this file and in\n * rosserial_python/src/rosserial_python/SerialClient.py\n */\nconst uint8_t MODE_PROTOCOL_VER   = 1;\nconst uint8_t PROTOCOL_VER1       = 0xff; // through groovy\nconst uint8_t PROTOCOL_VER2       = 0xfe; // in hydro\nconst uint8_t PROTOCOL_VER        = PROTOCOL_VER2;\nconst uint8_t MODE_SIZE_L         = 2;\nconst uint8_t MODE_SIZE_H         = 3;\nconst uint8_t MODE_SIZE_CHECKSUM  = 4;    // checksum for msg size received from size L and H\nconst uint8_t MODE_TOPIC_L        = 5;    // waiting for topic id\nconst uint8_t MODE_TOPIC_H        = 6;\nconst uint8_t MODE_MESSAGE        = 7;\nconst uint8_t MODE_MSG_CHECKSUM   = 8;    // checksum for msg and topic id\n\n\nconst uint8_t SERIAL_MSG_TIMEOUT  = 20;   // 20 milliseconds to recieve all of message data\n\nusing rosserial_msgs::TopicInfo;\n\n/* Node Handle */\ntemplate<class Hardware,\n         int MAX_SUBSCRIBERS = 25,\n         int MAX_PUBLISHERS = 25,\n         int INPUT_SIZE = 512,\n         int OUTPUT_SIZE = 512>\nclass NodeHandle_ : public NodeHandleBase_\n{\nprotected:\n  Hardware hardware_;\n\n  /* time used for syncing */\n  uint32_t rt_time;\n\n  /* used for computing current time */\n  uint32_t sec_offset, nsec_offset;\n\n  /* Spinonce maximum work timeout */\n  uint32_t spin_timeout_;\n\n  uint8_t message_in[INPUT_SIZE];\n  uint8_t message_out[OUTPUT_SIZE];\n\n  Publisher * publishers[MAX_PUBLISHERS];\n  Subscriber_ * subscribers[MAX_SUBSCRIBERS];\n\n  /*\n   * Setup Functions\n   */\npublic:\n  NodeHandle_() : configured_(false)\n  {\n\n    for (unsigned int i = 0; i < MAX_PUBLISHERS; i++)\n      publishers[i] = 0;\n\n    for (unsigned int i = 0; i < MAX_SUBSCRIBERS; i++)\n      subscribers[i] = 0;\n\n    for (unsigned int i = 0; i < INPUT_SIZE; i++)\n      message_in[i] = 0;\n\n    for (unsigned int i = 0; i < OUTPUT_SIZE; i++)\n      message_out[i] = 0;\n\n    req_param_resp.ints_length = 0;\n    req_param_resp.ints = NULL;\n    req_param_resp.floats_length = 0;\n    req_param_resp.floats = NULL;\n    req_param_resp.ints_length = 0;\n    req_param_resp.ints = NULL;\n\n    spin_timeout_ = 0;\n  }\n\n  Hardware* getHardware()\n  {\n    return &hardware_;\n  }\n\n  /* Start serial, initialize buffers */\n  void initNode()\n  {\n    hardware_.init();\n    mode_ = 0;\n    bytes_ = 0;\n    index_ = 0;\n    topic_ = 0;\n  };\n\n  /* Start a named port, which may be network server IP, initialize buffers */\n  void initNode(char *portName)\n  {\n    hardware_.init(portName);\n    mode_ = 0;\n    bytes_ = 0;\n    index_ = 0;\n    topic_ = 0;\n  };\n\n  /**\n   * @brief Sets the maximum time in millisconds that spinOnce() can work.\n   * This will not effect the processing of the buffer, as spinOnce processes\n   * one byte at a time. It simply sets the maximum time that one call can\n   * process for. You can choose to clear the buffer if that is beneficial if\n   * SPIN_TIMEOUT is returned from spinOnce().\n   * @param timeout The timeout in milliseconds that spinOnce will function.\n   */\n  void setSpinTimeout(const uint32_t& timeout)\n  {\n     spin_timeout_ = timeout;\n  }\n\nprotected:\n  //State machine variables for spinOnce\n  int mode_;\n  int bytes_;\n  int topic_;\n  int index_;\n  int checksum_;\n\n  bool configured_;\n\n  /* used for syncing the time */\n  uint32_t last_sync_time;\n  uint32_t last_sync_receive_time;\n  uint32_t last_msg_timeout_time;\n\npublic:\n  /* This function goes in your loop() function, it handles\n   *  serial input and callbacks for subscribers.\n   */\n\n\n  virtual int spinOnce()\n  {\n    /* restart if timed out */\n    uint32_t c_time = hardware_.time();\n    if ((c_time - last_sync_receive_time) > (SYNC_SECONDS * 2200))\n    {\n      configured_ = false;\n    }\n\n    /* reset if message has timed out */\n    if (mode_ != MODE_FIRST_FF)\n    {\n      if (c_time > last_msg_timeout_time)\n      {\n        mode_ = MODE_FIRST_FF;\n      }\n    }\n\n    /* while available buffer, read data */\n    while (true)\n    {\n      // If a timeout has been specified, check how long spinOnce has been running.\n      if (spin_timeout_ > 0)\n      {\n        // If the maximum processing timeout has been exceeded, exit with error.\n        // The next spinOnce can continue where it left off, or optionally\n        // based on the application in use, the hardware buffer could be flushed\n        // and start fresh.\n        if ((hardware_.time() - c_time) > spin_timeout_)\n        {\n          // Exit the spin, processing timeout exceeded.\n          return SPIN_TIMEOUT;\n        }\n      }\n      int data = hardware_.read();\n      if (data < 0)\n        break;\n      checksum_ += data;\n      if (mode_ == MODE_MESSAGE)          /* message data being recieved */\n      {\n        message_in[index_++] = data;\n        bytes_--;\n        if (bytes_ == 0)                 /* is message complete? if so, checksum */\n          mode_ = MODE_MSG_CHECKSUM;\n      }\n      else if (mode_ == MODE_FIRST_FF)\n      {\n        if (data == 0xff)\n        {\n          mode_++;\n          last_msg_timeout_time = c_time + SERIAL_MSG_TIMEOUT;\n        }\n        else if (hardware_.time() - c_time > (SYNC_SECONDS * 1000))\n        {\n          /* We have been stuck in spinOnce too long, return error */\n          configured_ = false;\n          return SPIN_TIMEOUT;\n        }\n      }\n      else if (mode_ == MODE_PROTOCOL_VER)\n      {\n        if (data == PROTOCOL_VER)\n        {\n          mode_++;\n        }\n        else\n        {\n          mode_ = MODE_FIRST_FF;\n          if (configured_ == false)\n            requestSyncTime();  /* send a msg back showing our protocol version */\n        }\n      }\n      else if (mode_ == MODE_SIZE_L)      /* bottom half of message size */\n      {\n        bytes_ = data;\n        index_ = 0;\n        mode_++;\n        checksum_ = data;               /* first byte for calculating size checksum */\n      }\n      else if (mode_ == MODE_SIZE_H)      /* top half of message size */\n      {\n        bytes_ += data << 8;\n        mode_++;\n      }\n      else if (mode_ == MODE_SIZE_CHECKSUM)\n      {\n        if ((checksum_ % 256) == 255)\n          mode_++;\n        else\n          mode_ = MODE_FIRST_FF;          /* Abandon the frame if the msg len is wrong */\n      }\n      else if (mode_ == MODE_TOPIC_L)     /* bottom half of topic id */\n      {\n        topic_ = data;\n        mode_++;\n        checksum_ = data;               /* first byte included in checksum */\n      }\n      else if (mode_ == MODE_TOPIC_H)     /* top half of topic id */\n      {\n        topic_ += data << 8;\n        mode_ = MODE_MESSAGE;\n        if (bytes_ == 0)\n          mode_ = MODE_MSG_CHECKSUM;\n      }\n      else if (mode_ == MODE_MSG_CHECKSUM)    /* do checksum */\n      {\n        mode_ = MODE_FIRST_FF;\n        if ((checksum_ % 256) == 255)\n        {\n          if (topic_ == TopicInfo::ID_PUBLISHER)\n          {\n            requestSyncTime();\n            negotiateTopics();\n            last_sync_time = c_time;\n            last_sync_receive_time = c_time;\n            return SPIN_ERR;\n          }\n          else if (topic_ == TopicInfo::ID_TIME)\n          {\n            syncTime(message_in);\n          }\n          else if (topic_ == TopicInfo::ID_PARAMETER_REQUEST)\n          {\n            req_param_resp.deserialize(message_in);\n            param_recieved = true;\n          }\n          else if (topic_ == TopicInfo::ID_TX_STOP)\n          {\n            configured_ = false;\n          }\n          else\n          {\n            if (subscribers[topic_ - 100])\n              subscribers[topic_ - 100]->callback(message_in);\n          }\n        }\n      }\n    }\n\n    /* occasionally sync time */\n    if (configured_ && ((c_time - last_sync_time) > (SYNC_SECONDS * 500)))\n    {\n      requestSyncTime();\n      last_sync_time = c_time;\n    }\n\n    return SPIN_OK;\n  }\n\n\n  /* Are we connected to the PC? */\n  virtual bool connected()\n  {\n    return configured_;\n  };\n\n  /********************************************************************\n   * Time functions\n   */\n\n  void requestSyncTime()\n  {\n    std_msgs::Time t;\n    publish(TopicInfo::ID_TIME, &t);\n    rt_time = hardware_.time();\n  }\n\n  void syncTime(uint8_t * data)\n  {\n    std_msgs::Time t;\n    uint32_t offset = hardware_.time() - rt_time;\n\n    t.deserialize(data);\n    t.data.sec += offset / 1000;\n    t.data.nsec += (offset % 1000) * 1000000UL;\n\n    this->setNow(t.data);\n    last_sync_receive_time = hardware_.time();\n  }\n\n  Time now()\n  {\n    uint32_t ms = hardware_.time()-last_sync_receive_time;\n    Time current_time;\n    current_time.sec = ms / 1000 + sec_offset;\n    current_time.nsec = (ms % 1000) * 1000000UL + nsec_offset;\n    normalizeSecNSec(current_time.sec, current_time.nsec);\n    return current_time;\n  }\n\n  void setNow(Time & new_now)\n  {\n    //uint32_t ms = hardware_.time();\n    sec_offset = new_now.sec;\n    nsec_offset = new_now.nsec;\n    normalizeSecNSec(sec_offset, nsec_offset);\n  }\n\n  /********************************************************************\n   * Topic Management\n   */\n\n  /* Register a new publisher */\n  bool advertise(Publisher & p)\n  {\n    for (int i = 0; i < MAX_PUBLISHERS; i++)\n    {\n      if (publishers[i] == 0) // empty slot\n      {\n        publishers[i] = &p;\n        p.id_ = i + 100 + MAX_SUBSCRIBERS;\n        p.nh_ = this;\n        return true;\n      }\n    }\n    return false;\n  }\n\n  /* Register a new subscriber */\n  template<typename SubscriberT>\n  bool subscribe(SubscriberT& s)\n  {\n    for (int i = 0; i < MAX_SUBSCRIBERS; i++)\n    {\n      if (subscribers[i] == 0) // empty slot\n      {\n        subscribers[i] = static_cast<Subscriber_*>(&s);\n        s.id_ = i + 100;\n        return true;\n      }\n    }\n    return false;\n  }\n\n  /* Register a new Service Server */\n  template<typename MReq, typename MRes, typename ObjT>\n  bool advertiseService(ServiceServer<MReq, MRes, ObjT>& srv)\n  {\n    bool v = advertise(srv.pub);\n    for (int i = 0; i < MAX_SUBSCRIBERS; i++)\n    {\n      if (subscribers[i] == 0) // empty slot\n      {\n        subscribers[i] = static_cast<Subscriber_*>(&srv);\n        srv.id_ = i + 100;\n        return v;\n      }\n    }\n    return false;\n  }\n\n  /* Register a new Service Client */\n  template<typename MReq, typename MRes>\n  bool serviceClient(ServiceClient<MReq, MRes>& srv)\n  {\n    bool v = advertise(srv.pub);\n    for (int i = 0; i < MAX_SUBSCRIBERS; i++)\n    {\n      if (subscribers[i] == 0) // empty slot\n      {\n        subscribers[i] = static_cast<Subscriber_*>(&srv);\n        srv.id_ = i + 100;\n        return v;\n      }\n    }\n    return false;\n  }\n\n  void negotiateTopics()\n  {\n    rosserial_msgs::TopicInfo ti;\n    int i;\n    for (i = 0; i < MAX_PUBLISHERS; i++)\n    {\n      if (publishers[i] != 0) // non-empty slot\n      {\n        ti.topic_id = publishers[i]->id_;\n        ti.topic_name = (char *) publishers[i]->topic_;\n        ti.message_type = (char *) publishers[i]->msg_->getType();\n        ti.md5sum = (char *) publishers[i]->msg_->getMD5();\n        ti.buffer_size = OUTPUT_SIZE;\n        publish(publishers[i]->getEndpointType(), &ti);\n      }\n    }\n    for (i = 0; i < MAX_SUBSCRIBERS; i++)\n    {\n      if (subscribers[i] != 0) // non-empty slot\n      {\n        ti.topic_id = subscribers[i]->id_;\n        ti.topic_name = (char *) subscribers[i]->topic_;\n        ti.message_type = (char *) subscribers[i]->getMsgType();\n        ti.md5sum = (char *) subscribers[i]->getMsgMD5();\n        ti.buffer_size = INPUT_SIZE;\n        publish(subscribers[i]->getEndpointType(), &ti);\n      }\n    }\n    configured_ = true;\n  }\n\n  virtual int publish(int id, const Msg * msg)\n  {\n    if (id >= 100 && !configured_)\n      return 0;\n\n    /* serialize message */\n    int l = msg->serialize(message_out + 7);\n\n    /* setup the header */\n    message_out[0] = 0xff;\n    message_out[1] = PROTOCOL_VER;\n    message_out[2] = (uint8_t)((uint16_t)l & 255);\n    message_out[3] = (uint8_t)((uint16_t)l >> 8);\n    message_out[4] = 255 - ((message_out[2] + message_out[3]) % 256);\n    message_out[5] = (uint8_t)((int16_t)id & 255);\n    message_out[6] = (uint8_t)((int16_t)id >> 8);\n\n    /* calculate checksum */\n    int chk = 0;\n    for (int i = 5; i < l + 7; i++)\n      chk += message_out[i];\n    l += 7;\n    message_out[l++] = 255 - (chk % 256);\n\n    if (l <= OUTPUT_SIZE)\n    {\n      hardware_.write(message_out, l);\n      return l;\n    }\n    else\n    {\n      logerror(\"Message from device dropped: message larger than buffer.\");\n      return -1;\n    }\n  }\n\n  /********************************************************************\n   * Logging\n   */\n\nprivate:\n  void log(char byte, const char * msg)\n  {\n    rosserial_msgs::Log l;\n    l.level = byte;\n    l.msg = (char*)msg;\n    publish(rosserial_msgs::TopicInfo::ID_LOG, &l);\n  }\n\npublic:\n  void logdebug(const char* msg)\n  {\n    log(rosserial_msgs::Log::ROSDEBUG, msg);\n  }\n  void loginfo(const char * msg)\n  {\n    log(rosserial_msgs::Log::INFO, msg);\n  }\n  void logwarn(const char *msg)\n  {\n    log(rosserial_msgs::Log::WARN, msg);\n  }\n  void logerror(const char*msg)\n  {\n    log(rosserial_msgs::Log::ERROR, msg);\n  }\n  void logfatal(const char*msg)\n  {\n    log(rosserial_msgs::Log::FATAL, msg);\n  }\n\n  /********************************************************************\n   * Parameters\n   */\n\nprivate:\n  bool param_recieved;\n  rosserial_msgs::RequestParamResponse req_param_resp;\n\n  bool requestParam(const char * name, int time_out =  1000)\n  {\n    param_recieved = false;\n    rosserial_msgs::RequestParamRequest req;\n    req.name  = (char*)name;\n    publish(TopicInfo::ID_PARAMETER_REQUEST, &req);\n    uint32_t end_time = hardware_.time() + time_out;\n    while (!param_recieved)\n    {\n      spinOnce();\n      if (hardware_.time() > end_time)\n      {\n        logwarn(\"Failed to get param: timeout expired\");\n        return false;\n      }\n    }\n    return true;\n  }\n\npublic:\n  bool getParam(const char* name, int* param, int length = 1, int timeout = 1000)\n  {\n    if (requestParam(name, timeout))\n    {\n      if (length == req_param_resp.ints_length)\n      {\n        //copy it over\n        for (int i = 0; i < length; i++)\n          param[i] = req_param_resp.ints[i];\n        return true;\n      }\n      else\n      {\n        logwarn(\"Failed to get param: length mismatch\");\n      }\n    }\n    return false;\n  }\n  bool getParam(const char* name, float* param, int length = 1, int timeout = 1000)\n  {\n    if (requestParam(name, timeout))\n    {\n      if (length == req_param_resp.floats_length)\n      {\n        //copy it over\n        for (int i = 0; i < length; i++)\n          param[i] = req_param_resp.floats[i];\n        return true;\n      }\n      else\n      {\n        logwarn(\"Failed to get param: length mismatch\");\n      }\n    }\n    return false;\n  }\n  bool getParam(const char* name, char** param, int length = 1, int timeout = 1000)\n  {\n    if (requestParam(name, timeout))\n    {\n      if (length == (int)req_param_resp.strings_length)\n      {\n        //copy it over\n        for (int i = 0; i < length; i++)\n          strcpy(param[i], req_param_resp.strings[i]);\n        return true;\n      }\n      else\n      {\n        logwarn(\"Failed to get param: length mismatch\");\n      }\n    }\n    return false;\n  }\n};\n\n}\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/ros/publisher.h",
    "content": "/*\n * Software License Agreement (BSD License)\n *\n * Copyright (c) 2011, Willow Garage, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n *  * Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n *  * Redistributions in binary form must reproduce the above\n *    copyright notice, this list of conditions and the following\n *    disclaimer in the documentation and/or other materials provided\n *    with the distribution.\n *  * Neither the name of Willow Garage, Inc. nor the names of its\n *    contributors may be used to endorse or promote prducts derived\n *    from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _ROS_PUBLISHER_H_\n#define _ROS_PUBLISHER_H_\n\n#include \"rosserial_msgs/TopicInfo.h\"\n#include \"ros/node_handle.h\"\n\nnamespace ros\n{\n\n/* Generic Publisher */\nclass Publisher\n{\npublic:\n  Publisher(const char * topic_name, Msg * msg, int endpoint = rosserial_msgs::TopicInfo::ID_PUBLISHER) :\n    topic_(topic_name),\n    msg_(msg),\n    endpoint_(endpoint) {};\n\n  int publish(const Msg * msg)\n  {\n    return nh_->publish(id_, msg);\n  };\n  int getEndpointType()\n  {\n    return endpoint_;\n  }\n\n  const char * topic_;\n  Msg *msg_;\n  // id_ and no_ are set by NodeHandle when we advertise\n  int id_;\n  NodeHandleBase_* nh_;\n\nprivate:\n  int endpoint_;\n};\n\n}\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/ros/service_client.h",
    "content": "/*\n * Software License Agreement (BSD License)\n *\n * Copyright (c) 2011, Willow Garage, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n *  * Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n *  * Redistributions in binary form must reproduce the above\n *    copyright notice, this list of conditions and the following\n *    disclaimer in the documentation and/or other materials provided\n *    with the distribution.\n *  * Neither the name of Willow Garage, Inc. nor the names of its\n *    contributors may be used to endorse or promote prducts derived\n *    from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _ROS_SERVICE_CLIENT_H_\n#define _ROS_SERVICE_CLIENT_H_\n\n#include \"rosserial_msgs/TopicInfo.h\"\n\n#include \"ros/publisher.h\"\n#include \"ros/subscriber.h\"\n\nnamespace ros\n{\n\ntemplate<typename MReq , typename MRes>\nclass ServiceClient : public Subscriber_\n{\npublic:\n  ServiceClient(const char* topic_name) :\n    pub(topic_name, &req, rosserial_msgs::TopicInfo::ID_SERVICE_CLIENT + rosserial_msgs::TopicInfo::ID_PUBLISHER)\n  {\n    this->topic_ = topic_name;\n    this->waiting = true;\n  }\n\n  virtual void call(const MReq & request, MRes & response)\n  {\n    if (!pub.nh_->connected()) return;\n    ret = &response;\n    waiting = true;\n    pub.publish(&request);\n    while (waiting && pub.nh_->connected())\n      if (pub.nh_->spinOnce() < 0) break;\n  }\n\n  // these refer to the subscriber\n  virtual void callback(unsigned char *data)\n  {\n    ret->deserialize(data);\n    waiting = false;\n  }\n  virtual const char * getMsgType()\n  {\n    return this->resp.getType();\n  }\n  virtual const char * getMsgMD5()\n  {\n    return this->resp.getMD5();\n  }\n  virtual int getEndpointType()\n  {\n    return rosserial_msgs::TopicInfo::ID_SERVICE_CLIENT + rosserial_msgs::TopicInfo::ID_SUBSCRIBER;\n  }\n\n  MReq req;\n  MRes resp;\n  MRes * ret;\n  bool waiting;\n  Publisher pub;\n};\n\n}\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/ros/service_server.h",
    "content": "/*\n * Software License Agreement (BSD License)\n *\n * Copyright (c) 2011, Willow Garage, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n *  * Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n *  * Redistributions in binary form must reproduce the above\n *    copyright notice, this list of conditions and the following\n *    disclaimer in the documentation and/or other materials provided\n *    with the distribution.\n *  * Neither the name of Willow Garage, Inc. nor the names of its\n *    contributors may be used to endorse or promote prducts derived\n *    from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _ROS_SERVICE_SERVER_H_\n#define _ROS_SERVICE_SERVER_H_\n\n#include \"rosserial_msgs/TopicInfo.h\"\n\n#include \"ros/publisher.h\"\n#include \"ros/subscriber.h\"\n\nnamespace ros\n{\n\ntemplate<typename MReq , typename MRes, typename ObjT = void>\nclass ServiceServer : public Subscriber_\n{\npublic:\n  typedef void(ObjT::*CallbackT)(const MReq&,  MRes&);\n\n  ServiceServer(const char* topic_name, CallbackT cb, ObjT* obj) :\n    pub(topic_name, &resp, rosserial_msgs::TopicInfo::ID_SERVICE_SERVER + rosserial_msgs::TopicInfo::ID_PUBLISHER),\n    obj_(obj)\n  {\n    this->topic_ = topic_name;\n    this->cb_ = cb;\n  }\n\n  // these refer to the subscriber\n  virtual void callback(unsigned char *data)\n  {\n    req.deserialize(data);\n    (obj_->*cb_)(req, resp);\n    pub.publish(&resp);\n  }\n  virtual const char * getMsgType()\n  {\n    return this->req.getType();\n  }\n  virtual const char * getMsgMD5()\n  {\n    return this->req.getMD5();\n  }\n  virtual int getEndpointType()\n  {\n    return rosserial_msgs::TopicInfo::ID_SERVICE_SERVER + rosserial_msgs::TopicInfo::ID_SUBSCRIBER;\n  }\n\n  MReq req;\n  MRes resp;\n  Publisher pub;\nprivate:\n  CallbackT cb_;\n  ObjT* obj_;\n};\n\ntemplate<typename MReq , typename MRes>\nclass ServiceServer<MReq, MRes, void> : public Subscriber_\n{\npublic:\n  typedef void(*CallbackT)(const MReq&,  MRes&);\n\n  ServiceServer(const char* topic_name, CallbackT cb) :\n    pub(topic_name, &resp, rosserial_msgs::TopicInfo::ID_SERVICE_SERVER + rosserial_msgs::TopicInfo::ID_PUBLISHER)\n  {\n    this->topic_ = topic_name;\n    this->cb_ = cb;\n  }\n\n  // these refer to the subscriber\n  virtual void callback(unsigned char *data)\n  {\n    req.deserialize(data);\n    cb_(req, resp);\n    pub.publish(&resp);\n  }\n  virtual const char * getMsgType()\n  {\n    return this->req.getType();\n  }\n  virtual const char * getMsgMD5()\n  {\n    return this->req.getMD5();\n  }\n  virtual int getEndpointType()\n  {\n    return rosserial_msgs::TopicInfo::ID_SERVICE_SERVER + rosserial_msgs::TopicInfo::ID_SUBSCRIBER;\n  }\n\n  MReq req;\n  MRes resp;\n  Publisher pub;\nprivate:\n  CallbackT cb_;\n};\n\n}\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/ros/subscriber.h",
    "content": "/*\n * Software License Agreement (BSD License)\n *\n * Copyright (c) 2011, Willow Garage, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n *  * Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n *  * Redistributions in binary form must reproduce the above\n *    copyright notice, this list of conditions and the following\n *    disclaimer in the documentation and/or other materials provided\n *    with the distribution.\n *  * Neither the name of Willow Garage, Inc. nor the names of its\n *    contributors may be used to endorse or promote prducts derived\n *    from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef ROS_SUBSCRIBER_H_\n#define ROS_SUBSCRIBER_H_\n\n#include \"rosserial_msgs/TopicInfo.h\"\n\nnamespace ros\n{\n\n/* Base class for objects subscribers. */\nclass Subscriber_\n{\npublic:\n  virtual void callback(unsigned char *data) = 0;\n  virtual int getEndpointType() = 0;\n\n  // id_ is set by NodeHandle when we advertise\n  int id_;\n\n  virtual const char * getMsgType() = 0;\n  virtual const char * getMsgMD5() = 0;\n  const char * topic_;\n};\n\n/* Bound function subscriber. */\ntemplate<typename MsgT, typename ObjT = void>\nclass Subscriber: public Subscriber_\n{\npublic:\n  typedef void(ObjT::*CallbackT)(const MsgT&);\n  MsgT msg;\n\n  Subscriber(const char * topic_name, CallbackT cb, ObjT* obj, int endpoint = rosserial_msgs::TopicInfo::ID_SUBSCRIBER) :\n    cb_(cb),\n    obj_(obj),\n    endpoint_(endpoint)\n  {\n    topic_ = topic_name;\n  };\n\n  virtual void callback(unsigned char* data)\n  {\n    msg.deserialize(data);\n    (obj_->*cb_)(msg);\n  }\n\n  virtual const char * getMsgType()\n  {\n    return this->msg.getType();\n  }\n  virtual const char * getMsgMD5()\n  {\n    return this->msg.getMD5();\n  }\n  virtual int getEndpointType()\n  {\n    return endpoint_;\n  }\n\nprivate:\n  CallbackT cb_;\n  ObjT* obj_;\n  int endpoint_;\n};\n\n/* Standalone function subscriber. */\ntemplate<typename MsgT>\nclass Subscriber<MsgT, void>: public Subscriber_\n{\npublic:\n  typedef void(*CallbackT)(const MsgT&);\n  MsgT msg;\n\n  Subscriber(const char * topic_name, CallbackT cb, int endpoint = rosserial_msgs::TopicInfo::ID_SUBSCRIBER) :\n    cb_(cb),\n    endpoint_(endpoint)\n  {\n    topic_ = topic_name;\n  };\n\n  virtual void callback(unsigned char* data)\n  {\n    msg.deserialize(data);\n    this->cb_(msg);\n  }\n\n  virtual const char * getMsgType()\n  {\n    return this->msg.getType();\n  }\n  virtual const char * getMsgMD5()\n  {\n    return this->msg.getMD5();\n  }\n  virtual int getEndpointType()\n  {\n    return endpoint_;\n  }\n\nprivate:\n  CallbackT cb_;\n  int endpoint_;\n};\n\n}\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/ros/time.h",
    "content": "/*\n * Software License Agreement (BSD License)\n *\n * Copyright (c) 2011, Willow Garage, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n *  * Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n *  * Redistributions in binary form must reproduce the above\n *    copyright notice, this list of conditions and the following\n *    disclaimer in the documentation and/or other materials provided\n *    with the distribution.\n *  * Neither the name of Willow Garage, Inc. nor the names of its\n *    contributors may be used to endorse or promote prducts derived\n *    from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef ROS_TIME_H_\n#define ROS_TIME_H_\n\n#include \"ros/duration.h\"\n#include <math.h>\n#include <stdint.h>\n\nnamespace ros\n{\nvoid normalizeSecNSec(uint32_t &sec, uint32_t &nsec);\n\nclass Time\n{\npublic:\n  uint32_t sec, nsec;\n\n  Time() : sec(0), nsec(0) {}\n  Time(uint32_t _sec, uint32_t _nsec) : sec(_sec), nsec(_nsec)\n  {\n    normalizeSecNSec(sec, nsec);\n  }\n\n  double toSec() const\n  {\n    return (double)sec + 1e-9 * (double)nsec;\n  };\n  void fromSec(double t)\n  {\n    sec = (uint32_t) floor(t);\n    nsec = (uint32_t) round((t - sec) * 1e9);\n  };\n\n  uint32_t toNsec()\n  {\n    return (uint32_t)sec * 1000000000ull + (uint32_t)nsec;\n  };\n  Time& fromNSec(int32_t t);\n\n  Time& operator +=(const Duration &rhs);\n  Time& operator -=(const Duration &rhs);\n\n  static Time now();\n  static void setNow(Time & new_now);\n};\n\n}\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/ros.h",
    "content": "/*\n * Software License Agreement (BSD License)\n *\n * Copyright (c) 2011, Willow Garage, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n *  * Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n *  * Redistributions in binary form must reproduce the above\n *    copyright notice, this list of conditions and the following\n *    disclaimer in the documentation and/or other materials provided\n *    with the distribution.\n *  * Neither the name of Willow Garage, Inc. nor the names of its\n *    contributors may be used to endorse or promote prducts derived\n *    from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _ROS_H_\n#define _ROS_H_\n\n#include \"ros/node_handle.h\"\n#include \"ArduinoHardware.h\"\n\nnamespace ros\n{\n#if defined(__AVR_ATmega8__) || defined(__AVR_ATmega168__)\n  /* downsize our buffers */\n  typedef NodeHandle_<ArduinoHardware, 6, 6, 150, 150> NodeHandle;\n\n#elif defined(__AVR_ATmega328P__)\n\n  typedef NodeHandle_<ArduinoHardware, 25, 25, 280, 280> NodeHandle;\n\n#else\n  /* Publishers, Subscribers, Buffer Sizes for OpenCR*/\n  typedef NodeHandle_<ArduinoHardware, 25, 25, 1024, 1024> NodeHandle;\n\n#endif\n}\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/roscpp/Empty.h",
    "content": "#ifndef _ROS_SERVICE_Empty_h\n#define _ROS_SERVICE_Empty_h\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace roscpp\n{\n\nstatic const char EMPTY[] = \"roscpp/Empty\";\n\n  class EmptyRequest : public ros::Msg\n  {\n    public:\n\n    EmptyRequest()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n     return offset;\n    }\n\n    const char * getType(){ return EMPTY; };\n    const char * getMD5(){ return \"d41d8cd98f00b204e9800998ecf8427e\"; };\n\n  };\n\n  class EmptyResponse : public ros::Msg\n  {\n    public:\n\n    EmptyResponse()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n     return offset;\n    }\n\n    const char * getType(){ return EMPTY; };\n    const char * getMD5(){ return \"d41d8cd98f00b204e9800998ecf8427e\"; };\n\n  };\n\n  class Empty {\n    public:\n    typedef EmptyRequest Request;\n    typedef EmptyResponse Response;\n  };\n\n}\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/roscpp/GetLoggers.h",
    "content": "#ifndef _ROS_SERVICE_GetLoggers_h\n#define _ROS_SERVICE_GetLoggers_h\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"roscpp/Logger.h\"\n\nnamespace roscpp\n{\n\nstatic const char GETLOGGERS[] = \"roscpp/GetLoggers\";\n\n  class GetLoggersRequest : public ros::Msg\n  {\n    public:\n\n    GetLoggersRequest()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n     return offset;\n    }\n\n    const char * getType(){ return GETLOGGERS; };\n    const char * getMD5(){ return \"d41d8cd98f00b204e9800998ecf8427e\"; };\n\n  };\n\n  class GetLoggersResponse : public ros::Msg\n  {\n    public:\n      uint32_t loggers_length;\n      typedef roscpp::Logger _loggers_type;\n      _loggers_type st_loggers;\n      _loggers_type * loggers;\n\n    GetLoggersResponse():\n      loggers_length(0), loggers(NULL)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      *(outbuffer + offset + 0) = (this->loggers_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->loggers_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->loggers_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->loggers_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->loggers_length);\n      for( uint32_t i = 0; i < loggers_length; i++){\n      offset += this->loggers[i].serialize(outbuffer + offset);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      uint32_t loggers_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      loggers_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      loggers_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      loggers_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->loggers_length);\n      if(loggers_lengthT > loggers_length)\n        this->loggers = (roscpp::Logger*)realloc(this->loggers, loggers_lengthT * sizeof(roscpp::Logger));\n      loggers_length = loggers_lengthT;\n      for( uint32_t i = 0; i < loggers_length; i++){\n      offset += this->st_loggers.deserialize(inbuffer + offset);\n        memcpy( &(this->loggers[i]), &(this->st_loggers), sizeof(roscpp::Logger));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return GETLOGGERS; };\n    const char * getMD5(){ return \"32e97e85527d4678a8f9279894bb64b0\"; };\n\n  };\n\n  class GetLoggers {\n    public:\n    typedef GetLoggersRequest Request;\n    typedef GetLoggersResponse Response;\n  };\n\n}\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/roscpp/Logger.h",
    "content": "#ifndef _ROS_roscpp_Logger_h\n#define _ROS_roscpp_Logger_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace roscpp\n{\n\n  class Logger : public ros::Msg\n  {\n    public:\n      typedef const char* _name_type;\n      _name_type name;\n      typedef const char* _level_type;\n      _level_type level;\n\n    Logger():\n      name(\"\"),\n      level(\"\")\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      uint32_t length_name = strlen(this->name);\n      varToArr(outbuffer + offset, length_name);\n      offset += 4;\n      memcpy(outbuffer + offset, this->name, length_name);\n      offset += length_name;\n      uint32_t length_level = strlen(this->level);\n      varToArr(outbuffer + offset, length_level);\n      offset += 4;\n      memcpy(outbuffer + offset, this->level, length_level);\n      offset += length_level;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      uint32_t length_name;\n      arrToVar(length_name, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_name; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_name-1]=0;\n      this->name = (char *)(inbuffer + offset-1);\n      offset += length_name;\n      uint32_t length_level;\n      arrToVar(length_level, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_level; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_level-1]=0;\n      this->level = (char *)(inbuffer + offset-1);\n      offset += length_level;\n     return offset;\n    }\n\n    const char * getType(){ return \"roscpp/Logger\"; };\n    const char * getMD5(){ return \"a6069a2ff40db7bd32143dd66e1f408e\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/roscpp/SetLoggerLevel.h",
    "content": "#ifndef _ROS_SERVICE_SetLoggerLevel_h\n#define _ROS_SERVICE_SetLoggerLevel_h\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace roscpp\n{\n\nstatic const char SETLOGGERLEVEL[] = \"roscpp/SetLoggerLevel\";\n\n  class SetLoggerLevelRequest : public ros::Msg\n  {\n    public:\n      typedef const char* _logger_type;\n      _logger_type logger;\n      typedef const char* _level_type;\n      _level_type level;\n\n    SetLoggerLevelRequest():\n      logger(\"\"),\n      level(\"\")\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      uint32_t length_logger = strlen(this->logger);\n      varToArr(outbuffer + offset, length_logger);\n      offset += 4;\n      memcpy(outbuffer + offset, this->logger, length_logger);\n      offset += length_logger;\n      uint32_t length_level = strlen(this->level);\n      varToArr(outbuffer + offset, length_level);\n      offset += 4;\n      memcpy(outbuffer + offset, this->level, length_level);\n      offset += length_level;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      uint32_t length_logger;\n      arrToVar(length_logger, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_logger; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_logger-1]=0;\n      this->logger = (char *)(inbuffer + offset-1);\n      offset += length_logger;\n      uint32_t length_level;\n      arrToVar(length_level, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_level; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_level-1]=0;\n      this->level = (char *)(inbuffer + offset-1);\n      offset += length_level;\n     return offset;\n    }\n\n    const char * getType(){ return SETLOGGERLEVEL; };\n    const char * getMD5(){ return \"51da076440d78ca1684d36c868df61ea\"; };\n\n  };\n\n  class SetLoggerLevelResponse : public ros::Msg\n  {\n    public:\n\n    SetLoggerLevelResponse()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n     return offset;\n    }\n\n    const char * getType(){ return SETLOGGERLEVEL; };\n    const char * getMD5(){ return \"d41d8cd98f00b204e9800998ecf8427e\"; };\n\n  };\n\n  class SetLoggerLevel {\n    public:\n    typedef SetLoggerLevelRequest Request;\n    typedef SetLoggerLevelResponse Response;\n  };\n\n}\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/rosserial_arduino/Adc.h",
    "content": "#ifndef _ROS_rosserial_arduino_Adc_h\n#define _ROS_rosserial_arduino_Adc_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace rosserial_arduino\n{\n\n  class Adc : public ros::Msg\n  {\n    public:\n      typedef uint16_t _adc0_type;\n      _adc0_type adc0;\n      typedef uint16_t _adc1_type;\n      _adc1_type adc1;\n      typedef uint16_t _adc2_type;\n      _adc2_type adc2;\n      typedef uint16_t _adc3_type;\n      _adc3_type adc3;\n      typedef uint16_t _adc4_type;\n      _adc4_type adc4;\n      typedef uint16_t _adc5_type;\n      _adc5_type adc5;\n\n    Adc():\n      adc0(0),\n      adc1(0),\n      adc2(0),\n      adc3(0),\n      adc4(0),\n      adc5(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      *(outbuffer + offset + 0) = (this->adc0 >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->adc0 >> (8 * 1)) & 0xFF;\n      offset += sizeof(this->adc0);\n      *(outbuffer + offset + 0) = (this->adc1 >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->adc1 >> (8 * 1)) & 0xFF;\n      offset += sizeof(this->adc1);\n      *(outbuffer + offset + 0) = (this->adc2 >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->adc2 >> (8 * 1)) & 0xFF;\n      offset += sizeof(this->adc2);\n      *(outbuffer + offset + 0) = (this->adc3 >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->adc3 >> (8 * 1)) & 0xFF;\n      offset += sizeof(this->adc3);\n      *(outbuffer + offset + 0) = (this->adc4 >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->adc4 >> (8 * 1)) & 0xFF;\n      offset += sizeof(this->adc4);\n      *(outbuffer + offset + 0) = (this->adc5 >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->adc5 >> (8 * 1)) & 0xFF;\n      offset += sizeof(this->adc5);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      this->adc0 =  ((uint16_t) (*(inbuffer + offset)));\n      this->adc0 |= ((uint16_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      offset += sizeof(this->adc0);\n      this->adc1 =  ((uint16_t) (*(inbuffer + offset)));\n      this->adc1 |= ((uint16_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      offset += sizeof(this->adc1);\n      this->adc2 =  ((uint16_t) (*(inbuffer + offset)));\n      this->adc2 |= ((uint16_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      offset += sizeof(this->adc2);\n      this->adc3 =  ((uint16_t) (*(inbuffer + offset)));\n      this->adc3 |= ((uint16_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      offset += sizeof(this->adc3);\n      this->adc4 =  ((uint16_t) (*(inbuffer + offset)));\n      this->adc4 |= ((uint16_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      offset += sizeof(this->adc4);\n      this->adc5 =  ((uint16_t) (*(inbuffer + offset)));\n      this->adc5 |= ((uint16_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      offset += sizeof(this->adc5);\n     return offset;\n    }\n\n    const char * getType(){ return \"rosserial_arduino/Adc\"; };\n    const char * getMD5(){ return \"6d7853a614e2e821319068311f2af25b\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/rosserial_arduino/Test.h",
    "content": "#ifndef _ROS_SERVICE_Test_h\n#define _ROS_SERVICE_Test_h\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace rosserial_arduino\n{\n\nstatic const char TEST[] = \"rosserial_arduino/Test\";\n\n  class TestRequest : public ros::Msg\n  {\n    public:\n      typedef const char* _input_type;\n      _input_type input;\n\n    TestRequest():\n      input(\"\")\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      uint32_t length_input = strlen(this->input);\n      varToArr(outbuffer + offset, length_input);\n      offset += 4;\n      memcpy(outbuffer + offset, this->input, length_input);\n      offset += length_input;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      uint32_t length_input;\n      arrToVar(length_input, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_input; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_input-1]=0;\n      this->input = (char *)(inbuffer + offset-1);\n      offset += length_input;\n     return offset;\n    }\n\n    const char * getType(){ return TEST; };\n    const char * getMD5(){ return \"39e92f1778057359c64c7b8a7d7b19de\"; };\n\n  };\n\n  class TestResponse : public ros::Msg\n  {\n    public:\n      typedef const char* _output_type;\n      _output_type output;\n\n    TestResponse():\n      output(\"\")\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      uint32_t length_output = strlen(this->output);\n      varToArr(outbuffer + offset, length_output);\n      offset += 4;\n      memcpy(outbuffer + offset, this->output, length_output);\n      offset += length_output;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      uint32_t length_output;\n      arrToVar(length_output, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_output; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_output-1]=0;\n      this->output = (char *)(inbuffer + offset-1);\n      offset += length_output;\n     return offset;\n    }\n\n    const char * getType(){ return TEST; };\n    const char * getMD5(){ return \"0825d95fdfa2c8f4bbb4e9c74bccd3fd\"; };\n\n  };\n\n  class Test {\n    public:\n    typedef TestRequest Request;\n    typedef TestResponse Response;\n  };\n\n}\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/rosserial_msgs/Log.h",
    "content": "#ifndef _ROS_rosserial_msgs_Log_h\n#define _ROS_rosserial_msgs_Log_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace rosserial_msgs\n{\n\n  class Log : public ros::Msg\n  {\n    public:\n      typedef uint8_t _level_type;\n      _level_type level;\n      typedef const char* _msg_type;\n      _msg_type msg;\n      enum { ROSDEBUG = 0 };\n      enum { INFO = 1 };\n      enum { WARN = 2 };\n      enum { ERROR = 3 };\n      enum { FATAL = 4 };\n\n    Log():\n      level(0),\n      msg(\"\")\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      *(outbuffer + offset + 0) = (this->level >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->level);\n      uint32_t length_msg = strlen(this->msg);\n      varToArr(outbuffer + offset, length_msg);\n      offset += 4;\n      memcpy(outbuffer + offset, this->msg, length_msg);\n      offset += length_msg;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      this->level =  ((uint8_t) (*(inbuffer + offset)));\n      offset += sizeof(this->level);\n      uint32_t length_msg;\n      arrToVar(length_msg, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_msg; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_msg-1]=0;\n      this->msg = (char *)(inbuffer + offset-1);\n      offset += length_msg;\n     return offset;\n    }\n\n    const char * getType(){ return \"rosserial_msgs/Log\"; };\n    const char * getMD5(){ return \"11abd731c25933261cd6183bd12d6295\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/rosserial_msgs/RequestMessageInfo.h",
    "content": "#ifndef _ROS_SERVICE_RequestMessageInfo_h\n#define _ROS_SERVICE_RequestMessageInfo_h\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace rosserial_msgs\n{\n\nstatic const char REQUESTMESSAGEINFO[] = \"rosserial_msgs/RequestMessageInfo\";\n\n  class RequestMessageInfoRequest : public ros::Msg\n  {\n    public:\n      typedef const char* _type_type;\n      _type_type type;\n\n    RequestMessageInfoRequest():\n      type(\"\")\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      uint32_t length_type = strlen(this->type);\n      varToArr(outbuffer + offset, length_type);\n      offset += 4;\n      memcpy(outbuffer + offset, this->type, length_type);\n      offset += length_type;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      uint32_t length_type;\n      arrToVar(length_type, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_type; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_type-1]=0;\n      this->type = (char *)(inbuffer + offset-1);\n      offset += length_type;\n     return offset;\n    }\n\n    const char * getType(){ return REQUESTMESSAGEINFO; };\n    const char * getMD5(){ return \"dc67331de85cf97091b7d45e5c64ab75\"; };\n\n  };\n\n  class RequestMessageInfoResponse : public ros::Msg\n  {\n    public:\n      typedef const char* _md5_type;\n      _md5_type md5;\n      typedef const char* _definition_type;\n      _definition_type definition;\n\n    RequestMessageInfoResponse():\n      md5(\"\"),\n      definition(\"\")\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      uint32_t length_md5 = strlen(this->md5);\n      varToArr(outbuffer + offset, length_md5);\n      offset += 4;\n      memcpy(outbuffer + offset, this->md5, length_md5);\n      offset += length_md5;\n      uint32_t length_definition = strlen(this->definition);\n      varToArr(outbuffer + offset, length_definition);\n      offset += 4;\n      memcpy(outbuffer + offset, this->definition, length_definition);\n      offset += length_definition;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      uint32_t length_md5;\n      arrToVar(length_md5, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_md5; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_md5-1]=0;\n      this->md5 = (char *)(inbuffer + offset-1);\n      offset += length_md5;\n      uint32_t length_definition;\n      arrToVar(length_definition, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_definition; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_definition-1]=0;\n      this->definition = (char *)(inbuffer + offset-1);\n      offset += length_definition;\n     return offset;\n    }\n\n    const char * getType(){ return REQUESTMESSAGEINFO; };\n    const char * getMD5(){ return \"fe452186a069bed40f09b8628fe5eac8\"; };\n\n  };\n\n  class RequestMessageInfo {\n    public:\n    typedef RequestMessageInfoRequest Request;\n    typedef RequestMessageInfoResponse Response;\n  };\n\n}\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/rosserial_msgs/RequestParam.h",
    "content": "#ifndef _ROS_SERVICE_RequestParam_h\n#define _ROS_SERVICE_RequestParam_h\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace rosserial_msgs\n{\n\nstatic const char REQUESTPARAM[] = \"rosserial_msgs/RequestParam\";\n\n  class RequestParamRequest : public ros::Msg\n  {\n    public:\n      typedef const char* _name_type;\n      _name_type name;\n\n    RequestParamRequest():\n      name(\"\")\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      uint32_t length_name = strlen(this->name);\n      varToArr(outbuffer + offset, length_name);\n      offset += 4;\n      memcpy(outbuffer + offset, this->name, length_name);\n      offset += length_name;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      uint32_t length_name;\n      arrToVar(length_name, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_name; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_name-1]=0;\n      this->name = (char *)(inbuffer + offset-1);\n      offset += length_name;\n     return offset;\n    }\n\n    const char * getType(){ return REQUESTPARAM; };\n    const char * getMD5(){ return \"c1f3d28f1b044c871e6eff2e9fc3c667\"; };\n\n  };\n\n  class RequestParamResponse : public ros::Msg\n  {\n    public:\n      uint32_t ints_length;\n      typedef int32_t _ints_type;\n      _ints_type st_ints;\n      _ints_type * ints;\n      uint32_t floats_length;\n      typedef float _floats_type;\n      _floats_type st_floats;\n      _floats_type * floats;\n      uint32_t strings_length;\n      typedef char* _strings_type;\n      _strings_type st_strings;\n      _strings_type * strings;\n\n    RequestParamResponse():\n      ints_length(0), ints(NULL),\n      floats_length(0), floats(NULL),\n      strings_length(0), strings(NULL)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      *(outbuffer + offset + 0) = (this->ints_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->ints_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->ints_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->ints_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->ints_length);\n      for( uint32_t i = 0; i < ints_length; i++){\n      union {\n        int32_t real;\n        uint32_t base;\n      } u_intsi;\n      u_intsi.real = this->ints[i];\n      *(outbuffer + offset + 0) = (u_intsi.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_intsi.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_intsi.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_intsi.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->ints[i]);\n      }\n      *(outbuffer + offset + 0) = (this->floats_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->floats_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->floats_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->floats_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->floats_length);\n      for( uint32_t i = 0; i < floats_length; i++){\n      union {\n        float real;\n        uint32_t base;\n      } u_floatsi;\n      u_floatsi.real = this->floats[i];\n      *(outbuffer + offset + 0) = (u_floatsi.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_floatsi.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_floatsi.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_floatsi.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->floats[i]);\n      }\n      *(outbuffer + offset + 0) = (this->strings_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->strings_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->strings_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->strings_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->strings_length);\n      for( uint32_t i = 0; i < strings_length; i++){\n      uint32_t length_stringsi = strlen(this->strings[i]);\n      varToArr(outbuffer + offset, length_stringsi);\n      offset += 4;\n      memcpy(outbuffer + offset, this->strings[i], length_stringsi);\n      offset += length_stringsi;\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      uint32_t ints_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      ints_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      ints_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      ints_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->ints_length);\n      if(ints_lengthT > ints_length)\n        this->ints = (int32_t*)realloc(this->ints, ints_lengthT * sizeof(int32_t));\n      ints_length = ints_lengthT;\n      for( uint32_t i = 0; i < ints_length; i++){\n      union {\n        int32_t real;\n        uint32_t base;\n      } u_st_ints;\n      u_st_ints.base = 0;\n      u_st_ints.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_st_ints.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_st_ints.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_st_ints.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->st_ints = u_st_ints.real;\n      offset += sizeof(this->st_ints);\n        memcpy( &(this->ints[i]), &(this->st_ints), sizeof(int32_t));\n      }\n      uint32_t floats_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      floats_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      floats_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      floats_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->floats_length);\n      if(floats_lengthT > floats_length)\n        this->floats = (float*)realloc(this->floats, floats_lengthT * sizeof(float));\n      floats_length = floats_lengthT;\n      for( uint32_t i = 0; i < floats_length; i++){\n      union {\n        float real;\n        uint32_t base;\n      } u_st_floats;\n      u_st_floats.base = 0;\n      u_st_floats.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_st_floats.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_st_floats.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_st_floats.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->st_floats = u_st_floats.real;\n      offset += sizeof(this->st_floats);\n        memcpy( &(this->floats[i]), &(this->st_floats), sizeof(float));\n      }\n      uint32_t strings_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      strings_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      strings_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      strings_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->strings_length);\n      if(strings_lengthT > strings_length)\n        this->strings = (char**)realloc(this->strings, strings_lengthT * sizeof(char*));\n      strings_length = strings_lengthT;\n      for( uint32_t i = 0; i < strings_length; i++){\n      uint32_t length_st_strings;\n      arrToVar(length_st_strings, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_st_strings; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_st_strings-1]=0;\n      this->st_strings = (char *)(inbuffer + offset-1);\n      offset += length_st_strings;\n        memcpy( &(this->strings[i]), &(this->st_strings), sizeof(char*));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return REQUESTPARAM; };\n    const char * getMD5(){ return \"9f0e98bda65981986ddf53afa7a40e49\"; };\n\n  };\n\n  class RequestParam {\n    public:\n    typedef RequestParamRequest Request;\n    typedef RequestParamResponse Response;\n  };\n\n}\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/rosserial_msgs/RequestServiceInfo.h",
    "content": "#ifndef _ROS_SERVICE_RequestServiceInfo_h\n#define _ROS_SERVICE_RequestServiceInfo_h\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace rosserial_msgs\n{\n\nstatic const char REQUESTSERVICEINFO[] = \"rosserial_msgs/RequestServiceInfo\";\n\n  class RequestServiceInfoRequest : public ros::Msg\n  {\n    public:\n      typedef const char* _service_type;\n      _service_type service;\n\n    RequestServiceInfoRequest():\n      service(\"\")\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      uint32_t length_service = strlen(this->service);\n      varToArr(outbuffer + offset, length_service);\n      offset += 4;\n      memcpy(outbuffer + offset, this->service, length_service);\n      offset += length_service;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      uint32_t length_service;\n      arrToVar(length_service, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_service; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_service-1]=0;\n      this->service = (char *)(inbuffer + offset-1);\n      offset += length_service;\n     return offset;\n    }\n\n    const char * getType(){ return REQUESTSERVICEINFO; };\n    const char * getMD5(){ return \"1cbcfa13b08f6d36710b9af8741e6112\"; };\n\n  };\n\n  class RequestServiceInfoResponse : public ros::Msg\n  {\n    public:\n      typedef const char* _service_md5_type;\n      _service_md5_type service_md5;\n      typedef const char* _request_md5_type;\n      _request_md5_type request_md5;\n      typedef const char* _response_md5_type;\n      _response_md5_type response_md5;\n\n    RequestServiceInfoResponse():\n      service_md5(\"\"),\n      request_md5(\"\"),\n      response_md5(\"\")\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      uint32_t length_service_md5 = strlen(this->service_md5);\n      varToArr(outbuffer + offset, length_service_md5);\n      offset += 4;\n      memcpy(outbuffer + offset, this->service_md5, length_service_md5);\n      offset += length_service_md5;\n      uint32_t length_request_md5 = strlen(this->request_md5);\n      varToArr(outbuffer + offset, length_request_md5);\n      offset += 4;\n      memcpy(outbuffer + offset, this->request_md5, length_request_md5);\n      offset += length_request_md5;\n      uint32_t length_response_md5 = strlen(this->response_md5);\n      varToArr(outbuffer + offset, length_response_md5);\n      offset += 4;\n      memcpy(outbuffer + offset, this->response_md5, length_response_md5);\n      offset += length_response_md5;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      uint32_t length_service_md5;\n      arrToVar(length_service_md5, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_service_md5; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_service_md5-1]=0;\n      this->service_md5 = (char *)(inbuffer + offset-1);\n      offset += length_service_md5;\n      uint32_t length_request_md5;\n      arrToVar(length_request_md5, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_request_md5; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_request_md5-1]=0;\n      this->request_md5 = (char *)(inbuffer + offset-1);\n      offset += length_request_md5;\n      uint32_t length_response_md5;\n      arrToVar(length_response_md5, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_response_md5; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_response_md5-1]=0;\n      this->response_md5 = (char *)(inbuffer + offset-1);\n      offset += length_response_md5;\n     return offset;\n    }\n\n    const char * getType(){ return REQUESTSERVICEINFO; };\n    const char * getMD5(){ return \"c3d6dd25b909596479fbbc6559fa6874\"; };\n\n  };\n\n  class RequestServiceInfo {\n    public:\n    typedef RequestServiceInfoRequest Request;\n    typedef RequestServiceInfoResponse Response;\n  };\n\n}\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/rosserial_msgs/TopicInfo.h",
    "content": "#ifndef _ROS_rosserial_msgs_TopicInfo_h\n#define _ROS_rosserial_msgs_TopicInfo_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace rosserial_msgs\n{\n\n  class TopicInfo : public ros::Msg\n  {\n    public:\n      typedef uint16_t _topic_id_type;\n      _topic_id_type topic_id;\n      typedef const char* _topic_name_type;\n      _topic_name_type topic_name;\n      typedef const char* _message_type_type;\n      _message_type_type message_type;\n      typedef const char* _md5sum_type;\n      _md5sum_type md5sum;\n      typedef int32_t _buffer_size_type;\n      _buffer_size_type buffer_size;\n      enum { ID_PUBLISHER = 0 };\n      enum { ID_SUBSCRIBER = 1 };\n      enum { ID_SERVICE_SERVER = 2 };\n      enum { ID_SERVICE_CLIENT = 4 };\n      enum { ID_PARAMETER_REQUEST = 6 };\n      enum { ID_LOG = 7 };\n      enum { ID_TIME = 10 };\n      enum { ID_TX_STOP = 11 };\n\n    TopicInfo():\n      topic_id(0),\n      topic_name(\"\"),\n      message_type(\"\"),\n      md5sum(\"\"),\n      buffer_size(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      *(outbuffer + offset + 0) = (this->topic_id >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->topic_id >> (8 * 1)) & 0xFF;\n      offset += sizeof(this->topic_id);\n      uint32_t length_topic_name = strlen(this->topic_name);\n      varToArr(outbuffer + offset, length_topic_name);\n      offset += 4;\n      memcpy(outbuffer + offset, this->topic_name, length_topic_name);\n      offset += length_topic_name;\n      uint32_t length_message_type = strlen(this->message_type);\n      varToArr(outbuffer + offset, length_message_type);\n      offset += 4;\n      memcpy(outbuffer + offset, this->message_type, length_message_type);\n      offset += length_message_type;\n      uint32_t length_md5sum = strlen(this->md5sum);\n      varToArr(outbuffer + offset, length_md5sum);\n      offset += 4;\n      memcpy(outbuffer + offset, this->md5sum, length_md5sum);\n      offset += length_md5sum;\n      union {\n        int32_t real;\n        uint32_t base;\n      } u_buffer_size;\n      u_buffer_size.real = this->buffer_size;\n      *(outbuffer + offset + 0) = (u_buffer_size.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_buffer_size.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_buffer_size.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_buffer_size.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->buffer_size);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      this->topic_id =  ((uint16_t) (*(inbuffer + offset)));\n      this->topic_id |= ((uint16_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      offset += sizeof(this->topic_id);\n      uint32_t length_topic_name;\n      arrToVar(length_topic_name, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_topic_name; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_topic_name-1]=0;\n      this->topic_name = (char *)(inbuffer + offset-1);\n      offset += length_topic_name;\n      uint32_t length_message_type;\n      arrToVar(length_message_type, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_message_type; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_message_type-1]=0;\n      this->message_type = (char *)(inbuffer + offset-1);\n      offset += length_message_type;\n      uint32_t length_md5sum;\n      arrToVar(length_md5sum, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_md5sum; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_md5sum-1]=0;\n      this->md5sum = (char *)(inbuffer + offset-1);\n      offset += length_md5sum;\n      union {\n        int32_t real;\n        uint32_t base;\n      } u_buffer_size;\n      u_buffer_size.base = 0;\n      u_buffer_size.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_buffer_size.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_buffer_size.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_buffer_size.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->buffer_size = u_buffer_size.real;\n      offset += sizeof(this->buffer_size);\n     return offset;\n    }\n\n    const char * getType(){ return \"rosserial_msgs/TopicInfo\"; };\n    const char * getMD5(){ return \"0ad51f88fc44892f8c10684077646005\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/sensor_msgs/BatteryState.h",
    "content": "#ifndef _ROS_sensor_msgs_BatteryState_h\n#define _ROS_sensor_msgs_BatteryState_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n\nnamespace sensor_msgs\n{\n\n  class BatteryState : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef float _voltage_type;\n      _voltage_type voltage;\n      typedef float _current_type;\n      _current_type current;\n      typedef float _charge_type;\n      _charge_type charge;\n      typedef float _capacity_type;\n      _capacity_type capacity;\n      typedef float _design_capacity_type;\n      _design_capacity_type design_capacity;\n      typedef float _percentage_type;\n      _percentage_type percentage;\n      typedef uint8_t _power_supply_status_type;\n      _power_supply_status_type power_supply_status;\n      typedef uint8_t _power_supply_health_type;\n      _power_supply_health_type power_supply_health;\n      typedef uint8_t _power_supply_technology_type;\n      _power_supply_technology_type power_supply_technology;\n      typedef bool _present_type;\n      _present_type present;\n      uint32_t cell_voltage_length;\n      typedef float _cell_voltage_type;\n      _cell_voltage_type st_cell_voltage;\n      _cell_voltage_type * cell_voltage;\n      typedef const char* _location_type;\n      _location_type location;\n      typedef const char* _serial_number_type;\n      _serial_number_type serial_number;\n      enum { POWER_SUPPLY_STATUS_UNKNOWN =  0 };\n      enum { POWER_SUPPLY_STATUS_CHARGING =  1 };\n      enum { POWER_SUPPLY_STATUS_DISCHARGING =  2 };\n      enum { POWER_SUPPLY_STATUS_NOT_CHARGING =  3 };\n      enum { POWER_SUPPLY_STATUS_FULL =  4 };\n      enum { POWER_SUPPLY_HEALTH_UNKNOWN =  0 };\n      enum { POWER_SUPPLY_HEALTH_GOOD =  1 };\n      enum { POWER_SUPPLY_HEALTH_OVERHEAT =  2 };\n      enum { POWER_SUPPLY_HEALTH_DEAD =  3 };\n      enum { POWER_SUPPLY_HEALTH_OVERVOLTAGE =  4 };\n      enum { POWER_SUPPLY_HEALTH_UNSPEC_FAILURE =  5 };\n      enum { POWER_SUPPLY_HEALTH_COLD =  6 };\n      enum { POWER_SUPPLY_HEALTH_WATCHDOG_TIMER_EXPIRE =  7 };\n      enum { POWER_SUPPLY_HEALTH_SAFETY_TIMER_EXPIRE =  8 };\n      enum { POWER_SUPPLY_TECHNOLOGY_UNKNOWN =  0 };\n      enum { POWER_SUPPLY_TECHNOLOGY_NIMH =  1 };\n      enum { POWER_SUPPLY_TECHNOLOGY_LION =  2 };\n      enum { POWER_SUPPLY_TECHNOLOGY_LIPO =  3 };\n      enum { POWER_SUPPLY_TECHNOLOGY_LIFE =  4 };\n      enum { POWER_SUPPLY_TECHNOLOGY_NICD =  5 };\n      enum { POWER_SUPPLY_TECHNOLOGY_LIMN =  6 };\n\n    BatteryState():\n      header(),\n      voltage(0),\n      current(0),\n      charge(0),\n      capacity(0),\n      design_capacity(0),\n      percentage(0),\n      power_supply_status(0),\n      power_supply_health(0),\n      power_supply_technology(0),\n      present(0),\n      cell_voltage_length(0), cell_voltage(NULL),\n      location(\"\"),\n      serial_number(\"\")\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      union {\n        float real;\n        uint32_t base;\n      } u_voltage;\n      u_voltage.real = this->voltage;\n      *(outbuffer + offset + 0) = (u_voltage.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_voltage.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_voltage.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_voltage.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->voltage);\n      union {\n        float real;\n        uint32_t base;\n      } u_current;\n      u_current.real = this->current;\n      *(outbuffer + offset + 0) = (u_current.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_current.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_current.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_current.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->current);\n      union {\n        float real;\n        uint32_t base;\n      } u_charge;\n      u_charge.real = this->charge;\n      *(outbuffer + offset + 0) = (u_charge.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_charge.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_charge.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_charge.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->charge);\n      union {\n        float real;\n        uint32_t base;\n      } u_capacity;\n      u_capacity.real = this->capacity;\n      *(outbuffer + offset + 0) = (u_capacity.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_capacity.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_capacity.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_capacity.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->capacity);\n      union {\n        float real;\n        uint32_t base;\n      } u_design_capacity;\n      u_design_capacity.real = this->design_capacity;\n      *(outbuffer + offset + 0) = (u_design_capacity.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_design_capacity.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_design_capacity.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_design_capacity.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->design_capacity);\n      union {\n        float real;\n        uint32_t base;\n      } u_percentage;\n      u_percentage.real = this->percentage;\n      *(outbuffer + offset + 0) = (u_percentage.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_percentage.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_percentage.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_percentage.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->percentage);\n      *(outbuffer + offset + 0) = (this->power_supply_status >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->power_supply_status);\n      *(outbuffer + offset + 0) = (this->power_supply_health >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->power_supply_health);\n      *(outbuffer + offset + 0) = (this->power_supply_technology >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->power_supply_technology);\n      union {\n        bool real;\n        uint8_t base;\n      } u_present;\n      u_present.real = this->present;\n      *(outbuffer + offset + 0) = (u_present.base >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->present);\n      *(outbuffer + offset + 0) = (this->cell_voltage_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->cell_voltage_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->cell_voltage_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->cell_voltage_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->cell_voltage_length);\n      for( uint32_t i = 0; i < cell_voltage_length; i++){\n      union {\n        float real;\n        uint32_t base;\n      } u_cell_voltagei;\n      u_cell_voltagei.real = this->cell_voltage[i];\n      *(outbuffer + offset + 0) = (u_cell_voltagei.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_cell_voltagei.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_cell_voltagei.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_cell_voltagei.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->cell_voltage[i]);\n      }\n      uint32_t length_location = strlen(this->location);\n      varToArr(outbuffer + offset, length_location);\n      offset += 4;\n      memcpy(outbuffer + offset, this->location, length_location);\n      offset += length_location;\n      uint32_t length_serial_number = strlen(this->serial_number);\n      varToArr(outbuffer + offset, length_serial_number);\n      offset += 4;\n      memcpy(outbuffer + offset, this->serial_number, length_serial_number);\n      offset += length_serial_number;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      union {\n        float real;\n        uint32_t base;\n      } u_voltage;\n      u_voltage.base = 0;\n      u_voltage.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_voltage.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_voltage.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_voltage.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->voltage = u_voltage.real;\n      offset += sizeof(this->voltage);\n      union {\n        float real;\n        uint32_t base;\n      } u_current;\n      u_current.base = 0;\n      u_current.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_current.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_current.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_current.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->current = u_current.real;\n      offset += sizeof(this->current);\n      union {\n        float real;\n        uint32_t base;\n      } u_charge;\n      u_charge.base = 0;\n      u_charge.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_charge.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_charge.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_charge.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->charge = u_charge.real;\n      offset += sizeof(this->charge);\n      union {\n        float real;\n        uint32_t base;\n      } u_capacity;\n      u_capacity.base = 0;\n      u_capacity.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_capacity.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_capacity.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_capacity.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->capacity = u_capacity.real;\n      offset += sizeof(this->capacity);\n      union {\n        float real;\n        uint32_t base;\n      } u_design_capacity;\n      u_design_capacity.base = 0;\n      u_design_capacity.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_design_capacity.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_design_capacity.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_design_capacity.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->design_capacity = u_design_capacity.real;\n      offset += sizeof(this->design_capacity);\n      union {\n        float real;\n        uint32_t base;\n      } u_percentage;\n      u_percentage.base = 0;\n      u_percentage.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_percentage.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_percentage.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_percentage.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->percentage = u_percentage.real;\n      offset += sizeof(this->percentage);\n      this->power_supply_status =  ((uint8_t) (*(inbuffer + offset)));\n      offset += sizeof(this->power_supply_status);\n      this->power_supply_health =  ((uint8_t) (*(inbuffer + offset)));\n      offset += sizeof(this->power_supply_health);\n      this->power_supply_technology =  ((uint8_t) (*(inbuffer + offset)));\n      offset += sizeof(this->power_supply_technology);\n      union {\n        bool real;\n        uint8_t base;\n      } u_present;\n      u_present.base = 0;\n      u_present.base |= ((uint8_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      this->present = u_present.real;\n      offset += sizeof(this->present);\n      uint32_t cell_voltage_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      cell_voltage_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      cell_voltage_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      cell_voltage_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->cell_voltage_length);\n      if(cell_voltage_lengthT > cell_voltage_length)\n        this->cell_voltage = (float*)realloc(this->cell_voltage, cell_voltage_lengthT * sizeof(float));\n      cell_voltage_length = cell_voltage_lengthT;\n      for( uint32_t i = 0; i < cell_voltage_length; i++){\n      union {\n        float real;\n        uint32_t base;\n      } u_st_cell_voltage;\n      u_st_cell_voltage.base = 0;\n      u_st_cell_voltage.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_st_cell_voltage.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_st_cell_voltage.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_st_cell_voltage.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->st_cell_voltage = u_st_cell_voltage.real;\n      offset += sizeof(this->st_cell_voltage);\n        memcpy( &(this->cell_voltage[i]), &(this->st_cell_voltage), sizeof(float));\n      }\n      uint32_t length_location;\n      arrToVar(length_location, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_location; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_location-1]=0;\n      this->location = (char *)(inbuffer + offset-1);\n      offset += length_location;\n      uint32_t length_serial_number;\n      arrToVar(length_serial_number, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_serial_number; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_serial_number-1]=0;\n      this->serial_number = (char *)(inbuffer + offset-1);\n      offset += length_serial_number;\n     return offset;\n    }\n\n    const char * getType(){ return \"sensor_msgs/BatteryState\"; };\n    const char * getMD5(){ return \"476f837fa6771f6e16e3bf4ef96f8770\"; };\n\n  };\n\n}\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/sensor_msgs/BatteryStateNoetic.h",
    "content": "#ifndef _ROS_sensor_msgs_BatteryStateNoetic_h\n#define _ROS_sensor_msgs_BatteryStateNoetic_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n\nnamespace sensor_msgs\n{\n\n  class BatteryStateNoetic : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef float _voltage_type;\n      _voltage_type voltage;\n      typedef float _temperature_type;\n      _temperature_type temperature;\n      typedef float _current_type;\n      _current_type current;\n      typedef float _charge_type;\n      _charge_type charge;\n      typedef float _capacity_type;\n      _capacity_type capacity;\n      typedef float _design_capacity_type;\n      _design_capacity_type design_capacity;\n      typedef float _percentage_type;\n      _percentage_type percentage;\n      typedef uint8_t _power_supply_status_type;\n      _power_supply_status_type power_supply_status;\n      typedef uint8_t _power_supply_health_type;\n      _power_supply_health_type power_supply_health;\n      typedef uint8_t _power_supply_technology_type;\n      _power_supply_technology_type power_supply_technology;\n      typedef bool _present_type;\n      _present_type present;\n      uint32_t cell_voltage_length;\n      typedef float _cell_voltage_type;\n      _cell_voltage_type st_cell_voltage;\n      _cell_voltage_type * cell_voltage;\n      uint32_t cell_temperature_length;\n      typedef float _cell_temperature_type;\n      _cell_temperature_type st_cell_temperature;\n      _cell_temperature_type * cell_temperature;\n      typedef const char* _location_type;\n      _location_type location;\n      typedef const char* _serial_number_type;\n      _serial_number_type serial_number;\n      enum { POWER_SUPPLY_STATUS_UNKNOWN =  0 };\n      enum { POWER_SUPPLY_STATUS_CHARGING =  1 };\n      enum { POWER_SUPPLY_STATUS_DISCHARGING =  2 };\n      enum { POWER_SUPPLY_STATUS_NOT_CHARGING =  3 };\n      enum { POWER_SUPPLY_STATUS_FULL =  4 };\n      enum { POWER_SUPPLY_HEALTH_UNKNOWN =  0 };\n      enum { POWER_SUPPLY_HEALTH_GOOD =  1 };\n      enum { POWER_SUPPLY_HEALTH_OVERHEAT =  2 };\n      enum { POWER_SUPPLY_HEALTH_DEAD =  3 };\n      enum { POWER_SUPPLY_HEALTH_OVERVOLTAGE =  4 };\n      enum { POWER_SUPPLY_HEALTH_UNSPEC_FAILURE =  5 };\n      enum { POWER_SUPPLY_HEALTH_COLD =  6 };\n      enum { POWER_SUPPLY_HEALTH_WATCHDOG_TIMER_EXPIRE =  7 };\n      enum { POWER_SUPPLY_HEALTH_SAFETY_TIMER_EXPIRE =  8 };\n      enum { POWER_SUPPLY_TECHNOLOGY_UNKNOWN =  0 };\n      enum { POWER_SUPPLY_TECHNOLOGY_NIMH =  1 };\n      enum { POWER_SUPPLY_TECHNOLOGY_LION =  2 };\n      enum { POWER_SUPPLY_TECHNOLOGY_LIPO =  3 };\n      enum { POWER_SUPPLY_TECHNOLOGY_LIFE =  4 };\n      enum { POWER_SUPPLY_TECHNOLOGY_NICD =  5 };\n      enum { POWER_SUPPLY_TECHNOLOGY_LIMN =  6 };\n\n    BatteryStateNoetic():\n      header(),\n      voltage(0),\n      temperature(0),\n      current(0),\n      charge(0),\n      capacity(0),\n      design_capacity(0),\n      percentage(0),\n      power_supply_status(0),\n      power_supply_health(0),\n      power_supply_technology(0),\n      present(0),\n      cell_voltage_length(0), cell_voltage(NULL),\n      cell_temperature_length(0), cell_temperature(NULL),\n      location(\"\"),\n      serial_number(\"\")\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      union {\n        float real;\n        uint32_t base;\n      } u_voltage;\n      u_voltage.real = this->voltage;\n      *(outbuffer + offset + 0) = (u_voltage.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_voltage.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_voltage.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_voltage.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->voltage);\n      union {\n        float real;\n        uint32_t base;\n      } u_temperature;\n      u_temperature.real = this->temperature;\n      *(outbuffer + offset + 0) = (u_temperature.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_temperature.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_temperature.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_temperature.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->temperature);\n      union {\n        float real;\n        uint32_t base;\n      } u_current;\n      u_current.real = this->current;\n      *(outbuffer + offset + 0) = (u_current.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_current.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_current.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_current.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->current);\n      union {\n        float real;\n        uint32_t base;\n      } u_charge;\n      u_charge.real = this->charge;\n      *(outbuffer + offset + 0) = (u_charge.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_charge.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_charge.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_charge.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->charge);\n      union {\n        float real;\n        uint32_t base;\n      } u_capacity;\n      u_capacity.real = this->capacity;\n      *(outbuffer + offset + 0) = (u_capacity.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_capacity.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_capacity.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_capacity.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->capacity);\n      union {\n        float real;\n        uint32_t base;\n      } u_design_capacity;\n      u_design_capacity.real = this->design_capacity;\n      *(outbuffer + offset + 0) = (u_design_capacity.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_design_capacity.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_design_capacity.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_design_capacity.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->design_capacity);\n      union {\n        float real;\n        uint32_t base;\n      } u_percentage;\n      u_percentage.real = this->percentage;\n      *(outbuffer + offset + 0) = (u_percentage.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_percentage.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_percentage.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_percentage.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->percentage);\n      *(outbuffer + offset + 0) = (this->power_supply_status >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->power_supply_status);\n      *(outbuffer + offset + 0) = (this->power_supply_health >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->power_supply_health);\n      *(outbuffer + offset + 0) = (this->power_supply_technology >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->power_supply_technology);\n      union {\n        bool real;\n        uint8_t base;\n      } u_present;\n      u_present.real = this->present;\n      *(outbuffer + offset + 0) = (u_present.base >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->present);\n      *(outbuffer + offset + 0) = (this->cell_voltage_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->cell_voltage_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->cell_voltage_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->cell_voltage_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->cell_voltage_length);\n      for( uint32_t i = 0; i < cell_voltage_length; i++){\n      union {\n        float real;\n        uint32_t base;\n      } u_cell_voltagei;\n      u_cell_voltagei.real = this->cell_voltage[i];\n      *(outbuffer + offset + 0) = (u_cell_voltagei.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_cell_voltagei.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_cell_voltagei.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_cell_voltagei.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->cell_voltage[i]);\n      }\n      *(outbuffer + offset + 0) = (this->cell_temperature_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->cell_temperature_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->cell_temperature_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->cell_temperature_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->cell_temperature_length);\n      for( uint32_t i = 0; i < cell_temperature_length; i++){\n      union {\n        float real;\n        uint32_t base;\n      } u_cell_temperaturei;\n      u_cell_temperaturei.real = this->cell_temperature[i];\n      *(outbuffer + offset + 0) = (u_cell_temperaturei.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_cell_temperaturei.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_cell_temperaturei.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_cell_temperaturei.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->cell_temperature[i]);\n      }\n      uint32_t length_location = strlen(this->location);\n      varToArr(outbuffer + offset, length_location);\n      offset += 4;\n      memcpy(outbuffer + offset, this->location, length_location);\n      offset += length_location;\n      uint32_t length_serial_number = strlen(this->serial_number);\n      varToArr(outbuffer + offset, length_serial_number);\n      offset += 4;\n      memcpy(outbuffer + offset, this->serial_number, length_serial_number);\n      offset += length_serial_number;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      union {\n        float real;\n        uint32_t base;\n      } u_voltage;\n      u_voltage.base = 0;\n      u_voltage.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_voltage.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_voltage.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_voltage.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->voltage = u_voltage.real;\n      offset += sizeof(this->voltage);\n      union {\n        float real;\n        uint32_t base;\n      } u_temperature;\n      u_temperature.base = 0;\n      u_temperature.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_temperature.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_temperature.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_temperature.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->temperature = u_temperature.real;\n      offset += sizeof(this->temperature);\n      union {\n        float real;\n        uint32_t base;\n      } u_current;\n      u_current.base = 0;\n      u_current.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_current.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_current.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_current.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->current = u_current.real;\n      offset += sizeof(this->current);\n      union {\n        float real;\n        uint32_t base;\n      } u_charge;\n      u_charge.base = 0;\n      u_charge.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_charge.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_charge.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_charge.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->charge = u_charge.real;\n      offset += sizeof(this->charge);\n      union {\n        float real;\n        uint32_t base;\n      } u_capacity;\n      u_capacity.base = 0;\n      u_capacity.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_capacity.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_capacity.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_capacity.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->capacity = u_capacity.real;\n      offset += sizeof(this->capacity);\n      union {\n        float real;\n        uint32_t base;\n      } u_design_capacity;\n      u_design_capacity.base = 0;\n      u_design_capacity.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_design_capacity.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_design_capacity.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_design_capacity.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->design_capacity = u_design_capacity.real;\n      offset += sizeof(this->design_capacity);\n      union {\n        float real;\n        uint32_t base;\n      } u_percentage;\n      u_percentage.base = 0;\n      u_percentage.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_percentage.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_percentage.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_percentage.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->percentage = u_percentage.real;\n      offset += sizeof(this->percentage);\n      this->power_supply_status =  ((uint8_t) (*(inbuffer + offset)));\n      offset += sizeof(this->power_supply_status);\n      this->power_supply_health =  ((uint8_t) (*(inbuffer + offset)));\n      offset += sizeof(this->power_supply_health);\n      this->power_supply_technology =  ((uint8_t) (*(inbuffer + offset)));\n      offset += sizeof(this->power_supply_technology);\n      union {\n        bool real;\n        uint8_t base;\n      } u_present;\n      u_present.base = 0;\n      u_present.base |= ((uint8_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      this->present = u_present.real;\n      offset += sizeof(this->present);\n      uint32_t cell_voltage_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      cell_voltage_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      cell_voltage_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      cell_voltage_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->cell_voltage_length);\n      if(cell_voltage_lengthT > cell_voltage_length)\n        this->cell_voltage = (float*)realloc(this->cell_voltage, cell_voltage_lengthT * sizeof(float));\n      cell_voltage_length = cell_voltage_lengthT;\n      for( uint32_t i = 0; i < cell_voltage_length; i++){\n      union {\n        float real;\n        uint32_t base;\n      } u_st_cell_voltage;\n      u_st_cell_voltage.base = 0;\n      u_st_cell_voltage.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_st_cell_voltage.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_st_cell_voltage.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_st_cell_voltage.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->st_cell_voltage = u_st_cell_voltage.real;\n      offset += sizeof(this->st_cell_voltage);\n        memcpy( &(this->cell_voltage[i]), &(this->st_cell_voltage), sizeof(float));\n      }\n      uint32_t cell_temperature_lengthT = ((uint32_t) (*(inbuffer + offset)));\n      cell_temperature_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      cell_temperature_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      cell_temperature_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->cell_temperature_length);\n      if(cell_temperature_lengthT > cell_temperature_length)\n        this->cell_temperature = (float*)realloc(this->cell_temperature, cell_temperature_lengthT * sizeof(float));\n      cell_temperature_length = cell_temperature_lengthT;\n      for( uint32_t i = 0; i < cell_temperature_length; i++){\n      union {\n        float real;\n        uint32_t base;\n      } u_st_cell_temperature;\n      u_st_cell_temperature.base = 0;\n      u_st_cell_temperature.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_st_cell_temperature.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_st_cell_temperature.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_st_cell_temperature.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->st_cell_temperature = u_st_cell_temperature.real;\n      offset += sizeof(this->st_cell_temperature);\n        memcpy( &(this->cell_temperature[i]), &(this->st_cell_temperature), sizeof(float));\n      }\n      uint32_t length_location;\n      arrToVar(length_location, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_location; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_location-1]=0;\n      this->location = (char *)(inbuffer + offset-1);\n      offset += length_location;\n      uint32_t length_serial_number;\n      arrToVar(length_serial_number, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_serial_number; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_serial_number-1]=0;\n      this->serial_number = (char *)(inbuffer + offset-1);\n      offset += length_serial_number;\n     return offset;\n    }\n\n    const char * getType(){ return \"sensor_msgs/BatteryState\"; };\n    const char * getMD5(){ return \"4ddae7f048e32fda22cac764685e3974\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/sensor_msgs/CameraInfo.h",
    "content": "#ifndef _ROS_sensor_msgs_CameraInfo_h\n#define _ROS_sensor_msgs_CameraInfo_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n#include \"sensor_msgs/RegionOfInterest.h\"\n\nnamespace sensor_msgs\n{\n\n  class CameraInfo : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef uint32_t _height_type;\n      _height_type height;\n      typedef uint32_t _width_type;\n      _width_type width;\n      typedef const char* _distortion_model_type;\n      _distortion_model_type distortion_model;\n      uint32_t D_length;\n      typedef float _D_type;\n      _D_type st_D;\n      _D_type * D;\n      float K[9];\n      float R[9];\n      float P[12];\n      typedef uint32_t _binning_x_type;\n      _binning_x_type binning_x;\n      typedef uint32_t _binning_y_type;\n      _binning_y_type binning_y;\n      typedef sensor_msgs::RegionOfInterest _roi_type;\n      _roi_type roi;\n\n    CameraInfo():\n      header(),\n      height(0),\n      width(0),\n      distortion_model(\"\"),\n      D_length(0), D(NULL),\n      K(),\n      R(),\n      P(),\n      binning_x(0),\n      binning_y(0),\n      roi()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      *(outbuffer + offset + 0) = (this->height >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->height >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->height >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->height >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->height);\n      *(outbuffer + offset + 0) = (this->width >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->width >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->width >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->width >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->width);\n      uint32_t length_distortion_model = strlen(this->distortion_model);\n      varToArr(outbuffer + offset, length_distortion_model);\n      offset += 4;\n      memcpy(outbuffer + offset, this->distortion_model, length_distortion_model);\n      offset += length_distortion_model;\n      *(outbuffer + offset + 0) = (this->D_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->D_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->D_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->D_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->D_length);\n      for( uint32_t i = 0; i < D_length; i++){\n      offset += serializeAvrFloat64(outbuffer + offset, this->D[i]);\n      }\n      for( uint32_t i = 0; i < 9; i++){\n      offset += serializeAvrFloat64(outbuffer + offset, this->K[i]);\n      }\n      for( uint32_t i = 0; i < 9; i++){\n      offset += serializeAvrFloat64(outbuffer + offset, this->R[i]);\n      }\n      for( uint32_t i = 0; i < 12; i++){\n      offset += serializeAvrFloat64(outbuffer + offset, this->P[i]);\n      }\n      *(outbuffer + offset + 0) = (this->binning_x >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->binning_x >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->binning_x >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->binning_x >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->binning_x);\n      *(outbuffer + offset + 0) = (this->binning_y >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->binning_y >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->binning_y >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->binning_y >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->binning_y);\n      offset += this->roi.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      this->height =  ((uint32_t) (*(inbuffer + offset)));\n      this->height |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->height |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->height |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->height);\n      this->width =  ((uint32_t) (*(inbuffer + offset)));\n      this->width |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->width |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->width |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->width);\n      uint32_t length_distortion_model;\n      arrToVar(length_distortion_model, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_distortion_model; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_distortion_model-1]=0;\n      this->distortion_model = (char *)(inbuffer + offset-1);\n      offset += length_distortion_model;\n      uint32_t D_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      D_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      D_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      D_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->D_length);\n      if(D_lengthT > D_length)\n        this->D = (float*)realloc(this->D, D_lengthT * sizeof(float));\n      D_length = D_lengthT;\n      for( uint32_t i = 0; i < D_length; i++){\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->st_D));\n        memcpy( &(this->D[i]), &(this->st_D), sizeof(float));\n      }\n      for( uint32_t i = 0; i < 9; i++){\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->K[i]));\n      }\n      for( uint32_t i = 0; i < 9; i++){\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->R[i]));\n      }\n      for( uint32_t i = 0; i < 12; i++){\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->P[i]));\n      }\n      this->binning_x =  ((uint32_t) (*(inbuffer + offset)));\n      this->binning_x |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->binning_x |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->binning_x |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->binning_x);\n      this->binning_y =  ((uint32_t) (*(inbuffer + offset)));\n      this->binning_y |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->binning_y |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->binning_y |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->binning_y);\n      offset += this->roi.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return \"sensor_msgs/CameraInfo\"; };\n    const char * getMD5(){ return \"c9a58c1b0b154e0e6da7578cb991d214\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/sensor_msgs/ChannelFloat32.h",
    "content": "#ifndef _ROS_sensor_msgs_ChannelFloat32_h\n#define _ROS_sensor_msgs_ChannelFloat32_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace sensor_msgs\n{\n\n  class ChannelFloat32 : public ros::Msg\n  {\n    public:\n      typedef const char* _name_type;\n      _name_type name;\n      uint32_t values_length;\n      typedef float _values_type;\n      _values_type st_values;\n      _values_type * values;\n\n    ChannelFloat32():\n      name(\"\"),\n      values_length(0), values(NULL)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      uint32_t length_name = strlen(this->name);\n      varToArr(outbuffer + offset, length_name);\n      offset += 4;\n      memcpy(outbuffer + offset, this->name, length_name);\n      offset += length_name;\n      *(outbuffer + offset + 0) = (this->values_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->values_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->values_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->values_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->values_length);\n      for( uint32_t i = 0; i < values_length; i++){\n      union {\n        float real;\n        uint32_t base;\n      } u_valuesi;\n      u_valuesi.real = this->values[i];\n      *(outbuffer + offset + 0) = (u_valuesi.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_valuesi.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_valuesi.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_valuesi.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->values[i]);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      uint32_t length_name;\n      arrToVar(length_name, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_name; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_name-1]=0;\n      this->name = (char *)(inbuffer + offset-1);\n      offset += length_name;\n      uint32_t values_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      values_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      values_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      values_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->values_length);\n      if(values_lengthT > values_length)\n        this->values = (float*)realloc(this->values, values_lengthT * sizeof(float));\n      values_length = values_lengthT;\n      for( uint32_t i = 0; i < values_length; i++){\n      union {\n        float real;\n        uint32_t base;\n      } u_st_values;\n      u_st_values.base = 0;\n      u_st_values.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_st_values.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_st_values.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_st_values.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->st_values = u_st_values.real;\n      offset += sizeof(this->st_values);\n        memcpy( &(this->values[i]), &(this->st_values), sizeof(float));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"sensor_msgs/ChannelFloat32\"; };\n    const char * getMD5(){ return \"3d40139cdd33dfedcb71ffeeeb42ae7f\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/sensor_msgs/CompressedImage.h",
    "content": "#ifndef _ROS_sensor_msgs_CompressedImage_h\n#define _ROS_sensor_msgs_CompressedImage_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n\nnamespace sensor_msgs\n{\n\n  class CompressedImage : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef const char* _format_type;\n      _format_type format;\n      uint32_t data_length;\n      typedef uint8_t _data_type;\n      _data_type st_data;\n      _data_type * data;\n\n    CompressedImage():\n      header(),\n      format(\"\"),\n      data_length(0), data(NULL)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      uint32_t length_format = strlen(this->format);\n      varToArr(outbuffer + offset, length_format);\n      offset += 4;\n      memcpy(outbuffer + offset, this->format, length_format);\n      offset += length_format;\n      *(outbuffer + offset + 0) = (this->data_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->data_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->data_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->data_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->data_length);\n      for( uint32_t i = 0; i < data_length; i++){\n      *(outbuffer + offset + 0) = (this->data[i] >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->data[i]);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      uint32_t length_format;\n      arrToVar(length_format, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_format; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_format-1]=0;\n      this->format = (char *)(inbuffer + offset-1);\n      offset += length_format;\n      uint32_t data_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->data_length);\n      if(data_lengthT > data_length)\n        this->data = (uint8_t*)realloc(this->data, data_lengthT * sizeof(uint8_t));\n      data_length = data_lengthT;\n      for( uint32_t i = 0; i < data_length; i++){\n      this->st_data =  ((uint8_t) (*(inbuffer + offset)));\n      offset += sizeof(this->st_data);\n        memcpy( &(this->data[i]), &(this->st_data), sizeof(uint8_t));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"sensor_msgs/CompressedImage\"; };\n    const char * getMD5(){ return \"8f7a12909da2c9d3332d540a0977563f\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/sensor_msgs/FluidPressure.h",
    "content": "#ifndef _ROS_sensor_msgs_FluidPressure_h\n#define _ROS_sensor_msgs_FluidPressure_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n\nnamespace sensor_msgs\n{\n\n  class FluidPressure : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef float _fluid_pressure_type;\n      _fluid_pressure_type fluid_pressure;\n      typedef float _variance_type;\n      _variance_type variance;\n\n    FluidPressure():\n      header(),\n      fluid_pressure(0),\n      variance(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      offset += serializeAvrFloat64(outbuffer + offset, this->fluid_pressure);\n      offset += serializeAvrFloat64(outbuffer + offset, this->variance);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->fluid_pressure));\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->variance));\n     return offset;\n    }\n\n    const char * getType(){ return \"sensor_msgs/FluidPressure\"; };\n    const char * getMD5(){ return \"804dc5cea1c5306d6a2eb80b9833befe\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/sensor_msgs/Illuminance.h",
    "content": "#ifndef _ROS_sensor_msgs_Illuminance_h\n#define _ROS_sensor_msgs_Illuminance_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n\nnamespace sensor_msgs\n{\n\n  class Illuminance : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef float _illuminance_type;\n      _illuminance_type illuminance;\n      typedef float _variance_type;\n      _variance_type variance;\n\n    Illuminance():\n      header(),\n      illuminance(0),\n      variance(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      offset += serializeAvrFloat64(outbuffer + offset, this->illuminance);\n      offset += serializeAvrFloat64(outbuffer + offset, this->variance);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->illuminance));\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->variance));\n     return offset;\n    }\n\n    const char * getType(){ return \"sensor_msgs/Illuminance\"; };\n    const char * getMD5(){ return \"8cf5febb0952fca9d650c3d11a81a188\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/sensor_msgs/Image.h",
    "content": "#ifndef _ROS_sensor_msgs_Image_h\n#define _ROS_sensor_msgs_Image_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n\nnamespace sensor_msgs\n{\n\n  class Image : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef uint32_t _height_type;\n      _height_type height;\n      typedef uint32_t _width_type;\n      _width_type width;\n      typedef const char* _encoding_type;\n      _encoding_type encoding;\n      typedef uint8_t _is_bigendian_type;\n      _is_bigendian_type is_bigendian;\n      typedef uint32_t _step_type;\n      _step_type step;\n      uint32_t data_length;\n      typedef uint8_t _data_type;\n      _data_type st_data;\n      _data_type * data;\n\n    Image():\n      header(),\n      height(0),\n      width(0),\n      encoding(\"\"),\n      is_bigendian(0),\n      step(0),\n      data_length(0), data(NULL)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      *(outbuffer + offset + 0) = (this->height >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->height >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->height >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->height >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->height);\n      *(outbuffer + offset + 0) = (this->width >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->width >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->width >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->width >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->width);\n      uint32_t length_encoding = strlen(this->encoding);\n      varToArr(outbuffer + offset, length_encoding);\n      offset += 4;\n      memcpy(outbuffer + offset, this->encoding, length_encoding);\n      offset += length_encoding;\n      *(outbuffer + offset + 0) = (this->is_bigendian >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->is_bigendian);\n      *(outbuffer + offset + 0) = (this->step >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->step >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->step >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->step >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->step);\n      *(outbuffer + offset + 0) = (this->data_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->data_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->data_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->data_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->data_length);\n      for( uint32_t i = 0; i < data_length; i++){\n      *(outbuffer + offset + 0) = (this->data[i] >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->data[i]);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      this->height =  ((uint32_t) (*(inbuffer + offset)));\n      this->height |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->height |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->height |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->height);\n      this->width =  ((uint32_t) (*(inbuffer + offset)));\n      this->width |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->width |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->width |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->width);\n      uint32_t length_encoding;\n      arrToVar(length_encoding, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_encoding; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_encoding-1]=0;\n      this->encoding = (char *)(inbuffer + offset-1);\n      offset += length_encoding;\n      this->is_bigendian =  ((uint8_t) (*(inbuffer + offset)));\n      offset += sizeof(this->is_bigendian);\n      this->step =  ((uint32_t) (*(inbuffer + offset)));\n      this->step |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->step |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->step |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->step);\n      uint32_t data_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->data_length);\n      if(data_lengthT > data_length)\n        this->data = (uint8_t*)realloc(this->data, data_lengthT * sizeof(uint8_t));\n      data_length = data_lengthT;\n      for( uint32_t i = 0; i < data_length; i++){\n      this->st_data =  ((uint8_t) (*(inbuffer + offset)));\n      offset += sizeof(this->st_data);\n        memcpy( &(this->data[i]), &(this->st_data), sizeof(uint8_t));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"sensor_msgs/Image\"; };\n    const char * getMD5(){ return \"060021388200f6f0f447d0fcd9c64743\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/sensor_msgs/Imu.h",
    "content": "#ifndef _ROS_sensor_msgs_Imu_h\n#define _ROS_sensor_msgs_Imu_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n#include \"geometry_msgs/Quaternion.h\"\n#include \"geometry_msgs/Vector3.h\"\n\nnamespace sensor_msgs\n{\n\n  class Imu : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef geometry_msgs::Quaternion _orientation_type;\n      _orientation_type orientation;\n      float orientation_covariance[9];\n      typedef geometry_msgs::Vector3 _angular_velocity_type;\n      _angular_velocity_type angular_velocity;\n      float angular_velocity_covariance[9];\n      typedef geometry_msgs::Vector3 _linear_acceleration_type;\n      _linear_acceleration_type linear_acceleration;\n      float linear_acceleration_covariance[9];\n\n    Imu():\n      header(),\n      orientation(),\n      orientation_covariance(),\n      angular_velocity(),\n      angular_velocity_covariance(),\n      linear_acceleration(),\n      linear_acceleration_covariance()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      offset += this->orientation.serialize(outbuffer + offset);\n      for( uint32_t i = 0; i < 9; i++){\n      offset += serializeAvrFloat64(outbuffer + offset, this->orientation_covariance[i]);\n      }\n      offset += this->angular_velocity.serialize(outbuffer + offset);\n      for( uint32_t i = 0; i < 9; i++){\n      offset += serializeAvrFloat64(outbuffer + offset, this->angular_velocity_covariance[i]);\n      }\n      offset += this->linear_acceleration.serialize(outbuffer + offset);\n      for( uint32_t i = 0; i < 9; i++){\n      offset += serializeAvrFloat64(outbuffer + offset, this->linear_acceleration_covariance[i]);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      offset += this->orientation.deserialize(inbuffer + offset);\n      for( uint32_t i = 0; i < 9; i++){\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->orientation_covariance[i]));\n      }\n      offset += this->angular_velocity.deserialize(inbuffer + offset);\n      for( uint32_t i = 0; i < 9; i++){\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->angular_velocity_covariance[i]));\n      }\n      offset += this->linear_acceleration.deserialize(inbuffer + offset);\n      for( uint32_t i = 0; i < 9; i++){\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->linear_acceleration_covariance[i]));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"sensor_msgs/Imu\"; };\n    const char * getMD5(){ return \"6a62c6daae103f4ff57a132d6f95cec2\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/sensor_msgs/JointState.h",
    "content": "#ifndef _ROS_sensor_msgs_JointState_h\n#define _ROS_sensor_msgs_JointState_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n\nnamespace sensor_msgs\n{\n\n  class JointState : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      uint32_t name_length;\n      typedef char* _name_type;\n      _name_type st_name;\n      _name_type * name;\n      uint32_t position_length;\n      typedef float _position_type;\n      _position_type st_position;\n      _position_type * position;\n      uint32_t velocity_length;\n      typedef float _velocity_type;\n      _velocity_type st_velocity;\n      _velocity_type * velocity;\n      uint32_t effort_length;\n      typedef float _effort_type;\n      _effort_type st_effort;\n      _effort_type * effort;\n\n    JointState():\n      header(),\n      name_length(0), name(NULL),\n      position_length(0), position(NULL),\n      velocity_length(0), velocity(NULL),\n      effort_length(0), effort(NULL)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      *(outbuffer + offset + 0) = (this->name_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->name_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->name_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->name_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->name_length);\n      for( uint32_t i = 0; i < name_length; i++){\n      uint32_t length_namei = strlen(this->name[i]);\n      varToArr(outbuffer + offset, length_namei);\n      offset += 4;\n      memcpy(outbuffer + offset, this->name[i], length_namei);\n      offset += length_namei;\n      }\n      *(outbuffer + offset + 0) = (this->position_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->position_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->position_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->position_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->position_length);\n      for( uint32_t i = 0; i < position_length; i++){\n      offset += serializeAvrFloat64(outbuffer + offset, this->position[i]);\n      }\n      *(outbuffer + offset + 0) = (this->velocity_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->velocity_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->velocity_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->velocity_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->velocity_length);\n      for( uint32_t i = 0; i < velocity_length; i++){\n      offset += serializeAvrFloat64(outbuffer + offset, this->velocity[i]);\n      }\n      *(outbuffer + offset + 0) = (this->effort_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->effort_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->effort_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->effort_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->effort_length);\n      for( uint32_t i = 0; i < effort_length; i++){\n      offset += serializeAvrFloat64(outbuffer + offset, this->effort[i]);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      uint32_t name_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      name_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      name_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      name_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->name_length);\n      if(name_lengthT > name_length)\n        this->name = (char**)realloc(this->name, name_lengthT * sizeof(char*));\n      name_length = name_lengthT;\n      for( uint32_t i = 0; i < name_length; i++){\n      uint32_t length_st_name;\n      arrToVar(length_st_name, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_st_name; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_st_name-1]=0;\n      this->st_name = (char *)(inbuffer + offset-1);\n      offset += length_st_name;\n        memcpy( &(this->name[i]), &(this->st_name), sizeof(char*));\n      }\n      uint32_t position_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      position_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      position_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      position_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->position_length);\n      if(position_lengthT > position_length)\n        this->position = (float*)realloc(this->position, position_lengthT * sizeof(float));\n      position_length = position_lengthT;\n      for( uint32_t i = 0; i < position_length; i++){\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->st_position));\n        memcpy( &(this->position[i]), &(this->st_position), sizeof(float));\n      }\n      uint32_t velocity_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      velocity_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      velocity_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      velocity_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->velocity_length);\n      if(velocity_lengthT > velocity_length)\n        this->velocity = (float*)realloc(this->velocity, velocity_lengthT * sizeof(float));\n      velocity_length = velocity_lengthT;\n      for( uint32_t i = 0; i < velocity_length; i++){\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->st_velocity));\n        memcpy( &(this->velocity[i]), &(this->st_velocity), sizeof(float));\n      }\n      uint32_t effort_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      effort_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      effort_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      effort_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->effort_length);\n      if(effort_lengthT > effort_length)\n        this->effort = (float*)realloc(this->effort, effort_lengthT * sizeof(float));\n      effort_length = effort_lengthT;\n      for( uint32_t i = 0; i < effort_length; i++){\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->st_effort));\n        memcpy( &(this->effort[i]), &(this->st_effort), sizeof(float));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"sensor_msgs/JointState\"; };\n    const char * getMD5(){ return \"3066dcd76a6cfaef579bd0f34173e9fd\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/sensor_msgs/Joy.h",
    "content": "#ifndef _ROS_sensor_msgs_Joy_h\n#define _ROS_sensor_msgs_Joy_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n\nnamespace sensor_msgs\n{\n\n  class Joy : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      uint32_t axes_length;\n      typedef float _axes_type;\n      _axes_type st_axes;\n      _axes_type * axes;\n      uint32_t buttons_length;\n      typedef int32_t _buttons_type;\n      _buttons_type st_buttons;\n      _buttons_type * buttons;\n\n    Joy():\n      header(),\n      axes_length(0), axes(NULL),\n      buttons_length(0), buttons(NULL)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      *(outbuffer + offset + 0) = (this->axes_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->axes_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->axes_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->axes_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->axes_length);\n      for( uint32_t i = 0; i < axes_length; i++){\n      union {\n        float real;\n        uint32_t base;\n      } u_axesi;\n      u_axesi.real = this->axes[i];\n      *(outbuffer + offset + 0) = (u_axesi.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_axesi.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_axesi.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_axesi.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->axes[i]);\n      }\n      *(outbuffer + offset + 0) = (this->buttons_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->buttons_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->buttons_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->buttons_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->buttons_length);\n      for( uint32_t i = 0; i < buttons_length; i++){\n      union {\n        int32_t real;\n        uint32_t base;\n      } u_buttonsi;\n      u_buttonsi.real = this->buttons[i];\n      *(outbuffer + offset + 0) = (u_buttonsi.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_buttonsi.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_buttonsi.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_buttonsi.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->buttons[i]);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      uint32_t axes_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      axes_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      axes_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      axes_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->axes_length);\n      if(axes_lengthT > axes_length)\n        this->axes = (float*)realloc(this->axes, axes_lengthT * sizeof(float));\n      axes_length = axes_lengthT;\n      for( uint32_t i = 0; i < axes_length; i++){\n      union {\n        float real;\n        uint32_t base;\n      } u_st_axes;\n      u_st_axes.base = 0;\n      u_st_axes.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_st_axes.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_st_axes.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_st_axes.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->st_axes = u_st_axes.real;\n      offset += sizeof(this->st_axes);\n        memcpy( &(this->axes[i]), &(this->st_axes), sizeof(float));\n      }\n      uint32_t buttons_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      buttons_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      buttons_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      buttons_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->buttons_length);\n      if(buttons_lengthT > buttons_length)\n        this->buttons = (int32_t*)realloc(this->buttons, buttons_lengthT * sizeof(int32_t));\n      buttons_length = buttons_lengthT;\n      for( uint32_t i = 0; i < buttons_length; i++){\n      union {\n        int32_t real;\n        uint32_t base;\n      } u_st_buttons;\n      u_st_buttons.base = 0;\n      u_st_buttons.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_st_buttons.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_st_buttons.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_st_buttons.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->st_buttons = u_st_buttons.real;\n      offset += sizeof(this->st_buttons);\n        memcpy( &(this->buttons[i]), &(this->st_buttons), sizeof(int32_t));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"sensor_msgs/Joy\"; };\n    const char * getMD5(){ return \"5a9ea5f83505693b71e785041e67a8bb\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/sensor_msgs/JoyFeedback.h",
    "content": "#ifndef _ROS_sensor_msgs_JoyFeedback_h\n#define _ROS_sensor_msgs_JoyFeedback_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace sensor_msgs\n{\n\n  class JoyFeedback : public ros::Msg\n  {\n    public:\n      typedef uint8_t _type_type;\n      _type_type type;\n      typedef uint8_t _id_type;\n      _id_type id;\n      typedef float _intensity_type;\n      _intensity_type intensity;\n      enum { TYPE_LED =  0 };\n      enum { TYPE_RUMBLE =  1 };\n      enum { TYPE_BUZZER =  2 };\n\n    JoyFeedback():\n      type(0),\n      id(0),\n      intensity(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      *(outbuffer + offset + 0) = (this->type >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->type);\n      *(outbuffer + offset + 0) = (this->id >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->id);\n      union {\n        float real;\n        uint32_t base;\n      } u_intensity;\n      u_intensity.real = this->intensity;\n      *(outbuffer + offset + 0) = (u_intensity.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_intensity.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_intensity.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_intensity.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->intensity);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      this->type =  ((uint8_t) (*(inbuffer + offset)));\n      offset += sizeof(this->type);\n      this->id =  ((uint8_t) (*(inbuffer + offset)));\n      offset += sizeof(this->id);\n      union {\n        float real;\n        uint32_t base;\n      } u_intensity;\n      u_intensity.base = 0;\n      u_intensity.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_intensity.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_intensity.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_intensity.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->intensity = u_intensity.real;\n      offset += sizeof(this->intensity);\n     return offset;\n    }\n\n    const char * getType(){ return \"sensor_msgs/JoyFeedback\"; };\n    const char * getMD5(){ return \"f4dcd73460360d98f36e55ee7f2e46f1\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/sensor_msgs/JoyFeedbackArray.h",
    "content": "#ifndef _ROS_sensor_msgs_JoyFeedbackArray_h\n#define _ROS_sensor_msgs_JoyFeedbackArray_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"sensor_msgs/JoyFeedback.h\"\n\nnamespace sensor_msgs\n{\n\n  class JoyFeedbackArray : public ros::Msg\n  {\n    public:\n      uint32_t array_length;\n      typedef sensor_msgs::JoyFeedback _array_type;\n      _array_type st_array;\n      _array_type * array;\n\n    JoyFeedbackArray():\n      array_length(0), array(NULL)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      *(outbuffer + offset + 0) = (this->array_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->array_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->array_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->array_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->array_length);\n      for( uint32_t i = 0; i < array_length; i++){\n      offset += this->array[i].serialize(outbuffer + offset);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      uint32_t array_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      array_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      array_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      array_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->array_length);\n      if(array_lengthT > array_length)\n        this->array = (sensor_msgs::JoyFeedback*)realloc(this->array, array_lengthT * sizeof(sensor_msgs::JoyFeedback));\n      array_length = array_lengthT;\n      for( uint32_t i = 0; i < array_length; i++){\n      offset += this->st_array.deserialize(inbuffer + offset);\n        memcpy( &(this->array[i]), &(this->st_array), sizeof(sensor_msgs::JoyFeedback));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"sensor_msgs/JoyFeedbackArray\"; };\n    const char * getMD5(){ return \"cde5730a895b1fc4dee6f91b754b213d\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/sensor_msgs/LaserEcho.h",
    "content": "#ifndef _ROS_sensor_msgs_LaserEcho_h\n#define _ROS_sensor_msgs_LaserEcho_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace sensor_msgs\n{\n\n  class LaserEcho : public ros::Msg\n  {\n    public:\n      uint32_t echoes_length;\n      typedef float _echoes_type;\n      _echoes_type st_echoes;\n      _echoes_type * echoes;\n\n    LaserEcho():\n      echoes_length(0), echoes(NULL)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      *(outbuffer + offset + 0) = (this->echoes_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->echoes_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->echoes_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->echoes_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->echoes_length);\n      for( uint32_t i = 0; i < echoes_length; i++){\n      union {\n        float real;\n        uint32_t base;\n      } u_echoesi;\n      u_echoesi.real = this->echoes[i];\n      *(outbuffer + offset + 0) = (u_echoesi.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_echoesi.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_echoesi.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_echoesi.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->echoes[i]);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      uint32_t echoes_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      echoes_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      echoes_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      echoes_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->echoes_length);\n      if(echoes_lengthT > echoes_length)\n        this->echoes = (float*)realloc(this->echoes, echoes_lengthT * sizeof(float));\n      echoes_length = echoes_lengthT;\n      for( uint32_t i = 0; i < echoes_length; i++){\n      union {\n        float real;\n        uint32_t base;\n      } u_st_echoes;\n      u_st_echoes.base = 0;\n      u_st_echoes.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_st_echoes.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_st_echoes.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_st_echoes.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->st_echoes = u_st_echoes.real;\n      offset += sizeof(this->st_echoes);\n        memcpy( &(this->echoes[i]), &(this->st_echoes), sizeof(float));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"sensor_msgs/LaserEcho\"; };\n    const char * getMD5(){ return \"8bc5ae449b200fba4d552b4225586696\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/sensor_msgs/LaserScan.h",
    "content": "#ifndef _ROS_sensor_msgs_LaserScan_h\n#define _ROS_sensor_msgs_LaserScan_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n\nnamespace sensor_msgs\n{\n\n  class LaserScan : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef float _angle_min_type;\n      _angle_min_type angle_min;\n      typedef float _angle_max_type;\n      _angle_max_type angle_max;\n      typedef float _angle_increment_type;\n      _angle_increment_type angle_increment;\n      typedef float _time_increment_type;\n      _time_increment_type time_increment;\n      typedef float _scan_time_type;\n      _scan_time_type scan_time;\n      typedef float _range_min_type;\n      _range_min_type range_min;\n      typedef float _range_max_type;\n      _range_max_type range_max;\n      uint32_t ranges_length;\n      typedef float _ranges_type;\n      _ranges_type st_ranges;\n      _ranges_type * ranges;\n      uint32_t intensities_length;\n      typedef float _intensities_type;\n      _intensities_type st_intensities;\n      _intensities_type * intensities;\n\n    LaserScan():\n      header(),\n      angle_min(0),\n      angle_max(0),\n      angle_increment(0),\n      time_increment(0),\n      scan_time(0),\n      range_min(0),\n      range_max(0),\n      ranges_length(0), ranges(NULL),\n      intensities_length(0), intensities(NULL)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      union {\n        float real;\n        uint32_t base;\n      } u_angle_min;\n      u_angle_min.real = this->angle_min;\n      *(outbuffer + offset + 0) = (u_angle_min.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_angle_min.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_angle_min.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_angle_min.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->angle_min);\n      union {\n        float real;\n        uint32_t base;\n      } u_angle_max;\n      u_angle_max.real = this->angle_max;\n      *(outbuffer + offset + 0) = (u_angle_max.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_angle_max.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_angle_max.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_angle_max.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->angle_max);\n      union {\n        float real;\n        uint32_t base;\n      } u_angle_increment;\n      u_angle_increment.real = this->angle_increment;\n      *(outbuffer + offset + 0) = (u_angle_increment.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_angle_increment.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_angle_increment.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_angle_increment.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->angle_increment);\n      union {\n        float real;\n        uint32_t base;\n      } u_time_increment;\n      u_time_increment.real = this->time_increment;\n      *(outbuffer + offset + 0) = (u_time_increment.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_time_increment.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_time_increment.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_time_increment.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->time_increment);\n      union {\n        float real;\n        uint32_t base;\n      } u_scan_time;\n      u_scan_time.real = this->scan_time;\n      *(outbuffer + offset + 0) = (u_scan_time.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_scan_time.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_scan_time.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_scan_time.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->scan_time);\n      union {\n        float real;\n        uint32_t base;\n      } u_range_min;\n      u_range_min.real = this->range_min;\n      *(outbuffer + offset + 0) = (u_range_min.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_range_min.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_range_min.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_range_min.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->range_min);\n      union {\n        float real;\n        uint32_t base;\n      } u_range_max;\n      u_range_max.real = this->range_max;\n      *(outbuffer + offset + 0) = (u_range_max.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_range_max.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_range_max.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_range_max.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->range_max);\n      *(outbuffer + offset + 0) = (this->ranges_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->ranges_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->ranges_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->ranges_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->ranges_length);\n      for( uint32_t i = 0; i < ranges_length; i++){\n      union {\n        float real;\n        uint32_t base;\n      } u_rangesi;\n      u_rangesi.real = this->ranges[i];\n      *(outbuffer + offset + 0) = (u_rangesi.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_rangesi.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_rangesi.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_rangesi.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->ranges[i]);\n      }\n      *(outbuffer + offset + 0) = (this->intensities_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->intensities_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->intensities_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->intensities_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->intensities_length);\n      for( uint32_t i = 0; i < intensities_length; i++){\n      union {\n        float real;\n        uint32_t base;\n      } u_intensitiesi;\n      u_intensitiesi.real = this->intensities[i];\n      *(outbuffer + offset + 0) = (u_intensitiesi.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_intensitiesi.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_intensitiesi.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_intensitiesi.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->intensities[i]);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      union {\n        float real;\n        uint32_t base;\n      } u_angle_min;\n      u_angle_min.base = 0;\n      u_angle_min.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_angle_min.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_angle_min.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_angle_min.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->angle_min = u_angle_min.real;\n      offset += sizeof(this->angle_min);\n      union {\n        float real;\n        uint32_t base;\n      } u_angle_max;\n      u_angle_max.base = 0;\n      u_angle_max.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_angle_max.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_angle_max.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_angle_max.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->angle_max = u_angle_max.real;\n      offset += sizeof(this->angle_max);\n      union {\n        float real;\n        uint32_t base;\n      } u_angle_increment;\n      u_angle_increment.base = 0;\n      u_angle_increment.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_angle_increment.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_angle_increment.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_angle_increment.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->angle_increment = u_angle_increment.real;\n      offset += sizeof(this->angle_increment);\n      union {\n        float real;\n        uint32_t base;\n      } u_time_increment;\n      u_time_increment.base = 0;\n      u_time_increment.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_time_increment.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_time_increment.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_time_increment.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->time_increment = u_time_increment.real;\n      offset += sizeof(this->time_increment);\n      union {\n        float real;\n        uint32_t base;\n      } u_scan_time;\n      u_scan_time.base = 0;\n      u_scan_time.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_scan_time.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_scan_time.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_scan_time.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->scan_time = u_scan_time.real;\n      offset += sizeof(this->scan_time);\n      union {\n        float real;\n        uint32_t base;\n      } u_range_min;\n      u_range_min.base = 0;\n      u_range_min.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_range_min.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_range_min.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_range_min.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->range_min = u_range_min.real;\n      offset += sizeof(this->range_min);\n      union {\n        float real;\n        uint32_t base;\n      } u_range_max;\n      u_range_max.base = 0;\n      u_range_max.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_range_max.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_range_max.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_range_max.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->range_max = u_range_max.real;\n      offset += sizeof(this->range_max);\n      uint32_t ranges_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      ranges_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      ranges_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      ranges_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->ranges_length);\n      if(ranges_lengthT > ranges_length)\n        this->ranges = (float*)realloc(this->ranges, ranges_lengthT * sizeof(float));\n      ranges_length = ranges_lengthT;\n      for( uint32_t i = 0; i < ranges_length; i++){\n      union {\n        float real;\n        uint32_t base;\n      } u_st_ranges;\n      u_st_ranges.base = 0;\n      u_st_ranges.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_st_ranges.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_st_ranges.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_st_ranges.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->st_ranges = u_st_ranges.real;\n      offset += sizeof(this->st_ranges);\n        memcpy( &(this->ranges[i]), &(this->st_ranges), sizeof(float));\n      }\n      uint32_t intensities_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      intensities_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      intensities_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      intensities_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->intensities_length);\n      if(intensities_lengthT > intensities_length)\n        this->intensities = (float*)realloc(this->intensities, intensities_lengthT * sizeof(float));\n      intensities_length = intensities_lengthT;\n      for( uint32_t i = 0; i < intensities_length; i++){\n      union {\n        float real;\n        uint32_t base;\n      } u_st_intensities;\n      u_st_intensities.base = 0;\n      u_st_intensities.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_st_intensities.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_st_intensities.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_st_intensities.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->st_intensities = u_st_intensities.real;\n      offset += sizeof(this->st_intensities);\n        memcpy( &(this->intensities[i]), &(this->st_intensities), sizeof(float));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"sensor_msgs/LaserScan\"; };\n    const char * getMD5(){ return \"90c7ef2dc6895d81024acba2ac42f369\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/sensor_msgs/MagneticField.h",
    "content": "#ifndef _ROS_sensor_msgs_MagneticField_h\n#define _ROS_sensor_msgs_MagneticField_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n#include \"geometry_msgs/Vector3.h\"\n\nnamespace sensor_msgs\n{\n\n  class MagneticField : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef geometry_msgs::Vector3 _magnetic_field_type;\n      _magnetic_field_type magnetic_field;\n      float magnetic_field_covariance[9];\n\n    MagneticField():\n      header(),\n      magnetic_field(),\n      magnetic_field_covariance()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      offset += this->magnetic_field.serialize(outbuffer + offset);\n      for( uint32_t i = 0; i < 9; i++){\n      offset += serializeAvrFloat64(outbuffer + offset, this->magnetic_field_covariance[i]);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      offset += this->magnetic_field.deserialize(inbuffer + offset);\n      for( uint32_t i = 0; i < 9; i++){\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->magnetic_field_covariance[i]));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"sensor_msgs/MagneticField\"; };\n    const char * getMD5(){ return \"2f3b0b43eed0c9501de0fa3ff89a45aa\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/sensor_msgs/MultiDOFJointState.h",
    "content": "#ifndef _ROS_sensor_msgs_MultiDOFJointState_h\n#define _ROS_sensor_msgs_MultiDOFJointState_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n#include \"geometry_msgs/Transform.h\"\n#include \"geometry_msgs/Twist.h\"\n#include \"geometry_msgs/Wrench.h\"\n\nnamespace sensor_msgs\n{\n\n  class MultiDOFJointState : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      uint32_t joint_names_length;\n      typedef char* _joint_names_type;\n      _joint_names_type st_joint_names;\n      _joint_names_type * joint_names;\n      uint32_t transforms_length;\n      typedef geometry_msgs::Transform _transforms_type;\n      _transforms_type st_transforms;\n      _transforms_type * transforms;\n      uint32_t twist_length;\n      typedef geometry_msgs::Twist _twist_type;\n      _twist_type st_twist;\n      _twist_type * twist;\n      uint32_t wrench_length;\n      typedef geometry_msgs::Wrench _wrench_type;\n      _wrench_type st_wrench;\n      _wrench_type * wrench;\n\n    MultiDOFJointState():\n      header(),\n      joint_names_length(0), joint_names(NULL),\n      transforms_length(0), transforms(NULL),\n      twist_length(0), twist(NULL),\n      wrench_length(0), wrench(NULL)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      *(outbuffer + offset + 0) = (this->joint_names_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->joint_names_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->joint_names_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->joint_names_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->joint_names_length);\n      for( uint32_t i = 0; i < joint_names_length; i++){\n      uint32_t length_joint_namesi = strlen(this->joint_names[i]);\n      varToArr(outbuffer + offset, length_joint_namesi);\n      offset += 4;\n      memcpy(outbuffer + offset, this->joint_names[i], length_joint_namesi);\n      offset += length_joint_namesi;\n      }\n      *(outbuffer + offset + 0) = (this->transforms_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->transforms_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->transforms_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->transforms_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->transforms_length);\n      for( uint32_t i = 0; i < transforms_length; i++){\n      offset += this->transforms[i].serialize(outbuffer + offset);\n      }\n      *(outbuffer + offset + 0) = (this->twist_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->twist_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->twist_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->twist_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->twist_length);\n      for( uint32_t i = 0; i < twist_length; i++){\n      offset += this->twist[i].serialize(outbuffer + offset);\n      }\n      *(outbuffer + offset + 0) = (this->wrench_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->wrench_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->wrench_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->wrench_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->wrench_length);\n      for( uint32_t i = 0; i < wrench_length; i++){\n      offset += this->wrench[i].serialize(outbuffer + offset);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      uint32_t joint_names_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      joint_names_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      joint_names_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      joint_names_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->joint_names_length);\n      if(joint_names_lengthT > joint_names_length)\n        this->joint_names = (char**)realloc(this->joint_names, joint_names_lengthT * sizeof(char*));\n      joint_names_length = joint_names_lengthT;\n      for( uint32_t i = 0; i < joint_names_length; i++){\n      uint32_t length_st_joint_names;\n      arrToVar(length_st_joint_names, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_st_joint_names; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_st_joint_names-1]=0;\n      this->st_joint_names = (char *)(inbuffer + offset-1);\n      offset += length_st_joint_names;\n        memcpy( &(this->joint_names[i]), &(this->st_joint_names), sizeof(char*));\n      }\n      uint32_t transforms_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      transforms_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      transforms_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      transforms_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->transforms_length);\n      if(transforms_lengthT > transforms_length)\n        this->transforms = (geometry_msgs::Transform*)realloc(this->transforms, transforms_lengthT * sizeof(geometry_msgs::Transform));\n      transforms_length = transforms_lengthT;\n      for( uint32_t i = 0; i < transforms_length; i++){\n      offset += this->st_transforms.deserialize(inbuffer + offset);\n        memcpy( &(this->transforms[i]), &(this->st_transforms), sizeof(geometry_msgs::Transform));\n      }\n      uint32_t twist_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      twist_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      twist_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      twist_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->twist_length);\n      if(twist_lengthT > twist_length)\n        this->twist = (geometry_msgs::Twist*)realloc(this->twist, twist_lengthT * sizeof(geometry_msgs::Twist));\n      twist_length = twist_lengthT;\n      for( uint32_t i = 0; i < twist_length; i++){\n      offset += this->st_twist.deserialize(inbuffer + offset);\n        memcpy( &(this->twist[i]), &(this->st_twist), sizeof(geometry_msgs::Twist));\n      }\n      uint32_t wrench_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      wrench_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      wrench_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      wrench_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->wrench_length);\n      if(wrench_lengthT > wrench_length)\n        this->wrench = (geometry_msgs::Wrench*)realloc(this->wrench, wrench_lengthT * sizeof(geometry_msgs::Wrench));\n      wrench_length = wrench_lengthT;\n      for( uint32_t i = 0; i < wrench_length; i++){\n      offset += this->st_wrench.deserialize(inbuffer + offset);\n        memcpy( &(this->wrench[i]), &(this->st_wrench), sizeof(geometry_msgs::Wrench));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"sensor_msgs/MultiDOFJointState\"; };\n    const char * getMD5(){ return \"690f272f0640d2631c305eeb8301e59d\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/sensor_msgs/MultiEchoLaserScan.h",
    "content": "#ifndef _ROS_sensor_msgs_MultiEchoLaserScan_h\n#define _ROS_sensor_msgs_MultiEchoLaserScan_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n#include \"sensor_msgs/LaserEcho.h\"\n\nnamespace sensor_msgs\n{\n\n  class MultiEchoLaserScan : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef float _angle_min_type;\n      _angle_min_type angle_min;\n      typedef float _angle_max_type;\n      _angle_max_type angle_max;\n      typedef float _angle_increment_type;\n      _angle_increment_type angle_increment;\n      typedef float _time_increment_type;\n      _time_increment_type time_increment;\n      typedef float _scan_time_type;\n      _scan_time_type scan_time;\n      typedef float _range_min_type;\n      _range_min_type range_min;\n      typedef float _range_max_type;\n      _range_max_type range_max;\n      uint32_t ranges_length;\n      typedef sensor_msgs::LaserEcho _ranges_type;\n      _ranges_type st_ranges;\n      _ranges_type * ranges;\n      uint32_t intensities_length;\n      typedef sensor_msgs::LaserEcho _intensities_type;\n      _intensities_type st_intensities;\n      _intensities_type * intensities;\n\n    MultiEchoLaserScan():\n      header(),\n      angle_min(0),\n      angle_max(0),\n      angle_increment(0),\n      time_increment(0),\n      scan_time(0),\n      range_min(0),\n      range_max(0),\n      ranges_length(0), ranges(NULL),\n      intensities_length(0), intensities(NULL)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      union {\n        float real;\n        uint32_t base;\n      } u_angle_min;\n      u_angle_min.real = this->angle_min;\n      *(outbuffer + offset + 0) = (u_angle_min.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_angle_min.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_angle_min.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_angle_min.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->angle_min);\n      union {\n        float real;\n        uint32_t base;\n      } u_angle_max;\n      u_angle_max.real = this->angle_max;\n      *(outbuffer + offset + 0) = (u_angle_max.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_angle_max.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_angle_max.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_angle_max.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->angle_max);\n      union {\n        float real;\n        uint32_t base;\n      } u_angle_increment;\n      u_angle_increment.real = this->angle_increment;\n      *(outbuffer + offset + 0) = (u_angle_increment.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_angle_increment.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_angle_increment.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_angle_increment.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->angle_increment);\n      union {\n        float real;\n        uint32_t base;\n      } u_time_increment;\n      u_time_increment.real = this->time_increment;\n      *(outbuffer + offset + 0) = (u_time_increment.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_time_increment.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_time_increment.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_time_increment.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->time_increment);\n      union {\n        float real;\n        uint32_t base;\n      } u_scan_time;\n      u_scan_time.real = this->scan_time;\n      *(outbuffer + offset + 0) = (u_scan_time.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_scan_time.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_scan_time.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_scan_time.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->scan_time);\n      union {\n        float real;\n        uint32_t base;\n      } u_range_min;\n      u_range_min.real = this->range_min;\n      *(outbuffer + offset + 0) = (u_range_min.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_range_min.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_range_min.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_range_min.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->range_min);\n      union {\n        float real;\n        uint32_t base;\n      } u_range_max;\n      u_range_max.real = this->range_max;\n      *(outbuffer + offset + 0) = (u_range_max.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_range_max.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_range_max.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_range_max.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->range_max);\n      *(outbuffer + offset + 0) = (this->ranges_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->ranges_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->ranges_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->ranges_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->ranges_length);\n      for( uint32_t i = 0; i < ranges_length; i++){\n      offset += this->ranges[i].serialize(outbuffer + offset);\n      }\n      *(outbuffer + offset + 0) = (this->intensities_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->intensities_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->intensities_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->intensities_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->intensities_length);\n      for( uint32_t i = 0; i < intensities_length; i++){\n      offset += this->intensities[i].serialize(outbuffer + offset);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      union {\n        float real;\n        uint32_t base;\n      } u_angle_min;\n      u_angle_min.base = 0;\n      u_angle_min.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_angle_min.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_angle_min.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_angle_min.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->angle_min = u_angle_min.real;\n      offset += sizeof(this->angle_min);\n      union {\n        float real;\n        uint32_t base;\n      } u_angle_max;\n      u_angle_max.base = 0;\n      u_angle_max.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_angle_max.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_angle_max.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_angle_max.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->angle_max = u_angle_max.real;\n      offset += sizeof(this->angle_max);\n      union {\n        float real;\n        uint32_t base;\n      } u_angle_increment;\n      u_angle_increment.base = 0;\n      u_angle_increment.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_angle_increment.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_angle_increment.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_angle_increment.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->angle_increment = u_angle_increment.real;\n      offset += sizeof(this->angle_increment);\n      union {\n        float real;\n        uint32_t base;\n      } u_time_increment;\n      u_time_increment.base = 0;\n      u_time_increment.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_time_increment.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_time_increment.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_time_increment.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->time_increment = u_time_increment.real;\n      offset += sizeof(this->time_increment);\n      union {\n        float real;\n        uint32_t base;\n      } u_scan_time;\n      u_scan_time.base = 0;\n      u_scan_time.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_scan_time.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_scan_time.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_scan_time.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->scan_time = u_scan_time.real;\n      offset += sizeof(this->scan_time);\n      union {\n        float real;\n        uint32_t base;\n      } u_range_min;\n      u_range_min.base = 0;\n      u_range_min.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_range_min.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_range_min.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_range_min.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->range_min = u_range_min.real;\n      offset += sizeof(this->range_min);\n      union {\n        float real;\n        uint32_t base;\n      } u_range_max;\n      u_range_max.base = 0;\n      u_range_max.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_range_max.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_range_max.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_range_max.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->range_max = u_range_max.real;\n      offset += sizeof(this->range_max);\n      uint32_t ranges_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      ranges_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      ranges_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      ranges_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->ranges_length);\n      if(ranges_lengthT > ranges_length)\n        this->ranges = (sensor_msgs::LaserEcho*)realloc(this->ranges, ranges_lengthT * sizeof(sensor_msgs::LaserEcho));\n      ranges_length = ranges_lengthT;\n      for( uint32_t i = 0; i < ranges_length; i++){\n      offset += this->st_ranges.deserialize(inbuffer + offset);\n        memcpy( &(this->ranges[i]), &(this->st_ranges), sizeof(sensor_msgs::LaserEcho));\n      }\n      uint32_t intensities_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      intensities_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      intensities_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      intensities_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->intensities_length);\n      if(intensities_lengthT > intensities_length)\n        this->intensities = (sensor_msgs::LaserEcho*)realloc(this->intensities, intensities_lengthT * sizeof(sensor_msgs::LaserEcho));\n      intensities_length = intensities_lengthT;\n      for( uint32_t i = 0; i < intensities_length; i++){\n      offset += this->st_intensities.deserialize(inbuffer + offset);\n        memcpy( &(this->intensities[i]), &(this->st_intensities), sizeof(sensor_msgs::LaserEcho));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"sensor_msgs/MultiEchoLaserScan\"; };\n    const char * getMD5(){ return \"6fefb0c6da89d7c8abe4b339f5c2f8fb\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/sensor_msgs/NavSatFix.h",
    "content": "#ifndef _ROS_sensor_msgs_NavSatFix_h\n#define _ROS_sensor_msgs_NavSatFix_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n#include \"sensor_msgs/NavSatStatus.h\"\n\nnamespace sensor_msgs\n{\n\n  class NavSatFix : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef sensor_msgs::NavSatStatus _status_type;\n      _status_type status;\n      typedef float _latitude_type;\n      _latitude_type latitude;\n      typedef float _longitude_type;\n      _longitude_type longitude;\n      typedef float _altitude_type;\n      _altitude_type altitude;\n      float position_covariance[9];\n      typedef uint8_t _position_covariance_type_type;\n      _position_covariance_type_type position_covariance_type;\n      enum { COVARIANCE_TYPE_UNKNOWN =  0 };\n      enum { COVARIANCE_TYPE_APPROXIMATED =  1 };\n      enum { COVARIANCE_TYPE_DIAGONAL_KNOWN =  2 };\n      enum { COVARIANCE_TYPE_KNOWN =  3 };\n\n    NavSatFix():\n      header(),\n      status(),\n      latitude(0),\n      longitude(0),\n      altitude(0),\n      position_covariance(),\n      position_covariance_type(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      offset += this->status.serialize(outbuffer + offset);\n      offset += serializeAvrFloat64(outbuffer + offset, this->latitude);\n      offset += serializeAvrFloat64(outbuffer + offset, this->longitude);\n      offset += serializeAvrFloat64(outbuffer + offset, this->altitude);\n      for( uint32_t i = 0; i < 9; i++){\n      offset += serializeAvrFloat64(outbuffer + offset, this->position_covariance[i]);\n      }\n      *(outbuffer + offset + 0) = (this->position_covariance_type >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->position_covariance_type);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      offset += this->status.deserialize(inbuffer + offset);\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->latitude));\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->longitude));\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->altitude));\n      for( uint32_t i = 0; i < 9; i++){\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->position_covariance[i]));\n      }\n      this->position_covariance_type =  ((uint8_t) (*(inbuffer + offset)));\n      offset += sizeof(this->position_covariance_type);\n     return offset;\n    }\n\n    const char * getType(){ return \"sensor_msgs/NavSatFix\"; };\n    const char * getMD5(){ return \"2d3a8cd499b9b4a0249fb98fd05cfa48\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/sensor_msgs/NavSatStatus.h",
    "content": "#ifndef _ROS_sensor_msgs_NavSatStatus_h\n#define _ROS_sensor_msgs_NavSatStatus_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace sensor_msgs\n{\n\n  class NavSatStatus : public ros::Msg\n  {\n    public:\n      typedef int8_t _status_type;\n      _status_type status;\n      typedef uint16_t _service_type;\n      _service_type service;\n      enum { STATUS_NO_FIX =   -1         };\n      enum { STATUS_FIX =       0         };\n      enum { STATUS_SBAS_FIX =  1         };\n      enum { STATUS_GBAS_FIX =  2         };\n      enum { SERVICE_GPS =      1 };\n      enum { SERVICE_GLONASS =  2 };\n      enum { SERVICE_COMPASS =  4       };\n      enum { SERVICE_GALILEO =  8 };\n\n    NavSatStatus():\n      status(0),\n      service(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      union {\n        int8_t real;\n        uint8_t base;\n      } u_status;\n      u_status.real = this->status;\n      *(outbuffer + offset + 0) = (u_status.base >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->status);\n      *(outbuffer + offset + 0) = (this->service >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->service >> (8 * 1)) & 0xFF;\n      offset += sizeof(this->service);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      union {\n        int8_t real;\n        uint8_t base;\n      } u_status;\n      u_status.base = 0;\n      u_status.base |= ((uint8_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      this->status = u_status.real;\n      offset += sizeof(this->status);\n      this->service =  ((uint16_t) (*(inbuffer + offset)));\n      this->service |= ((uint16_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      offset += sizeof(this->service);\n     return offset;\n    }\n\n    const char * getType(){ return \"sensor_msgs/NavSatStatus\"; };\n    const char * getMD5(){ return \"331cdbddfa4bc96ffc3b9ad98900a54c\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/sensor_msgs/PointCloud.h",
    "content": "#ifndef _ROS_sensor_msgs_PointCloud_h\n#define _ROS_sensor_msgs_PointCloud_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n#include \"geometry_msgs/Point32.h\"\n#include \"sensor_msgs/ChannelFloat32.h\"\n\nnamespace sensor_msgs\n{\n\n  class PointCloud : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      uint32_t points_length;\n      typedef geometry_msgs::Point32 _points_type;\n      _points_type st_points;\n      _points_type * points;\n      uint32_t channels_length;\n      typedef sensor_msgs::ChannelFloat32 _channels_type;\n      _channels_type st_channels;\n      _channels_type * channels;\n\n    PointCloud():\n      header(),\n      points_length(0), points(NULL),\n      channels_length(0), channels(NULL)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      *(outbuffer + offset + 0) = (this->points_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->points_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->points_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->points_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->points_length);\n      for( uint32_t i = 0; i < points_length; i++){\n      offset += this->points[i].serialize(outbuffer + offset);\n      }\n      *(outbuffer + offset + 0) = (this->channels_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->channels_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->channels_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->channels_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->channels_length);\n      for( uint32_t i = 0; i < channels_length; i++){\n      offset += this->channels[i].serialize(outbuffer + offset);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      uint32_t points_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      points_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      points_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      points_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->points_length);\n      if(points_lengthT > points_length)\n        this->points = (geometry_msgs::Point32*)realloc(this->points, points_lengthT * sizeof(geometry_msgs::Point32));\n      points_length = points_lengthT;\n      for( uint32_t i = 0; i < points_length; i++){\n      offset += this->st_points.deserialize(inbuffer + offset);\n        memcpy( &(this->points[i]), &(this->st_points), sizeof(geometry_msgs::Point32));\n      }\n      uint32_t channels_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      channels_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      channels_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      channels_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->channels_length);\n      if(channels_lengthT > channels_length)\n        this->channels = (sensor_msgs::ChannelFloat32*)realloc(this->channels, channels_lengthT * sizeof(sensor_msgs::ChannelFloat32));\n      channels_length = channels_lengthT;\n      for( uint32_t i = 0; i < channels_length; i++){\n      offset += this->st_channels.deserialize(inbuffer + offset);\n        memcpy( &(this->channels[i]), &(this->st_channels), sizeof(sensor_msgs::ChannelFloat32));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"sensor_msgs/PointCloud\"; };\n    const char * getMD5(){ return \"d8e9c3f5afbdd8a130fd1d2763945fca\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/sensor_msgs/PointCloud2.h",
    "content": "#ifndef _ROS_sensor_msgs_PointCloud2_h\n#define _ROS_sensor_msgs_PointCloud2_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n#include \"sensor_msgs/PointField.h\"\n\nnamespace sensor_msgs\n{\n\n  class PointCloud2 : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef uint32_t _height_type;\n      _height_type height;\n      typedef uint32_t _width_type;\n      _width_type width;\n      uint32_t fields_length;\n      typedef sensor_msgs::PointField _fields_type;\n      _fields_type st_fields;\n      _fields_type * fields;\n      typedef bool _is_bigendian_type;\n      _is_bigendian_type is_bigendian;\n      typedef uint32_t _point_step_type;\n      _point_step_type point_step;\n      typedef uint32_t _row_step_type;\n      _row_step_type row_step;\n      uint32_t data_length;\n      typedef uint8_t _data_type;\n      _data_type st_data;\n      _data_type * data;\n      typedef bool _is_dense_type;\n      _is_dense_type is_dense;\n\n    PointCloud2():\n      header(),\n      height(0),\n      width(0),\n      fields_length(0), fields(NULL),\n      is_bigendian(0),\n      point_step(0),\n      row_step(0),\n      data_length(0), data(NULL),\n      is_dense(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      *(outbuffer + offset + 0) = (this->height >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->height >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->height >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->height >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->height);\n      *(outbuffer + offset + 0) = (this->width >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->width >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->width >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->width >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->width);\n      *(outbuffer + offset + 0) = (this->fields_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->fields_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->fields_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->fields_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->fields_length);\n      for( uint32_t i = 0; i < fields_length; i++){\n      offset += this->fields[i].serialize(outbuffer + offset);\n      }\n      union {\n        bool real;\n        uint8_t base;\n      } u_is_bigendian;\n      u_is_bigendian.real = this->is_bigendian;\n      *(outbuffer + offset + 0) = (u_is_bigendian.base >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->is_bigendian);\n      *(outbuffer + offset + 0) = (this->point_step >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->point_step >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->point_step >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->point_step >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->point_step);\n      *(outbuffer + offset + 0) = (this->row_step >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->row_step >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->row_step >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->row_step >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->row_step);\n      *(outbuffer + offset + 0) = (this->data_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->data_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->data_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->data_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->data_length);\n      for( uint32_t i = 0; i < data_length; i++){\n      *(outbuffer + offset + 0) = (this->data[i] >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->data[i]);\n      }\n      union {\n        bool real;\n        uint8_t base;\n      } u_is_dense;\n      u_is_dense.real = this->is_dense;\n      *(outbuffer + offset + 0) = (u_is_dense.base >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->is_dense);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      this->height =  ((uint32_t) (*(inbuffer + offset)));\n      this->height |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->height |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->height |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->height);\n      this->width =  ((uint32_t) (*(inbuffer + offset)));\n      this->width |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->width |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->width |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->width);\n      uint32_t fields_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      fields_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      fields_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      fields_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->fields_length);\n      if(fields_lengthT > fields_length)\n        this->fields = (sensor_msgs::PointField*)realloc(this->fields, fields_lengthT * sizeof(sensor_msgs::PointField));\n      fields_length = fields_lengthT;\n      for( uint32_t i = 0; i < fields_length; i++){\n      offset += this->st_fields.deserialize(inbuffer + offset);\n        memcpy( &(this->fields[i]), &(this->st_fields), sizeof(sensor_msgs::PointField));\n      }\n      union {\n        bool real;\n        uint8_t base;\n      } u_is_bigendian;\n      u_is_bigendian.base = 0;\n      u_is_bigendian.base |= ((uint8_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      this->is_bigendian = u_is_bigendian.real;\n      offset += sizeof(this->is_bigendian);\n      this->point_step =  ((uint32_t) (*(inbuffer + offset)));\n      this->point_step |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->point_step |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->point_step |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->point_step);\n      this->row_step =  ((uint32_t) (*(inbuffer + offset)));\n      this->row_step |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->row_step |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->row_step |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->row_step);\n      uint32_t data_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->data_length);\n      if(data_lengthT > data_length)\n        this->data = (uint8_t*)realloc(this->data, data_lengthT * sizeof(uint8_t));\n      data_length = data_lengthT;\n      for( uint32_t i = 0; i < data_length; i++){\n      this->st_data =  ((uint8_t) (*(inbuffer + offset)));\n      offset += sizeof(this->st_data);\n        memcpy( &(this->data[i]), &(this->st_data), sizeof(uint8_t));\n      }\n      union {\n        bool real;\n        uint8_t base;\n      } u_is_dense;\n      u_is_dense.base = 0;\n      u_is_dense.base |= ((uint8_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      this->is_dense = u_is_dense.real;\n      offset += sizeof(this->is_dense);\n     return offset;\n    }\n\n    const char * getType(){ return \"sensor_msgs/PointCloud2\"; };\n    const char * getMD5(){ return \"1158d486dd51d683ce2f1be655c3c181\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/sensor_msgs/PointField.h",
    "content": "#ifndef _ROS_sensor_msgs_PointField_h\n#define _ROS_sensor_msgs_PointField_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace sensor_msgs\n{\n\n  class PointField : public ros::Msg\n  {\n    public:\n      typedef const char* _name_type;\n      _name_type name;\n      typedef uint32_t _offset_type;\n      _offset_type offset;\n      typedef uint8_t _datatype_type;\n      _datatype_type datatype;\n      typedef uint32_t _count_type;\n      _count_type count;\n      enum { INT8 =  1 };\n      enum { UINT8 =  2 };\n      enum { INT16 =  3 };\n      enum { UINT16 =  4 };\n      enum { INT32 =  5 };\n      enum { UINT32 =  6 };\n      enum { FLOAT32 =  7 };\n      enum { FLOAT64 =  8 };\n\n    PointField():\n      name(\"\"),\n      offset(0),\n      datatype(0),\n      count(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      uint32_t length_name = strlen(this->name);\n      varToArr(outbuffer + offset, length_name);\n      offset += 4;\n      memcpy(outbuffer + offset, this->name, length_name);\n      offset += length_name;\n      *(outbuffer + offset + 0) = (this->offset >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->offset >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->offset >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->offset >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->offset);\n      *(outbuffer + offset + 0) = (this->datatype >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->datatype);\n      *(outbuffer + offset + 0) = (this->count >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->count >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->count >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->count >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->count);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      uint32_t length_name;\n      arrToVar(length_name, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_name; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_name-1]=0;\n      this->name = (char *)(inbuffer + offset-1);\n      offset += length_name;\n      this->offset =  ((uint32_t) (*(inbuffer + offset)));\n      this->offset |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->offset |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->offset |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->offset);\n      this->datatype =  ((uint8_t) (*(inbuffer + offset)));\n      offset += sizeof(this->datatype);\n      this->count =  ((uint32_t) (*(inbuffer + offset)));\n      this->count |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->count |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->count |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->count);\n     return offset;\n    }\n\n    const char * getType(){ return \"sensor_msgs/PointField\"; };\n    const char * getMD5(){ return \"268eacb2962780ceac86cbd17e328150\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/sensor_msgs/Range.h",
    "content": "#ifndef _ROS_sensor_msgs_Range_h\n#define _ROS_sensor_msgs_Range_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n\nnamespace sensor_msgs\n{\n\n  class Range : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef uint8_t _radiation_type_type;\n      _radiation_type_type radiation_type;\n      typedef float _field_of_view_type;\n      _field_of_view_type field_of_view;\n      typedef float _min_range_type;\n      _min_range_type min_range;\n      typedef float _max_range_type;\n      _max_range_type max_range;\n      typedef float _range_type;\n      _range_type range;\n      enum { ULTRASOUND = 0 };\n      enum { INFRARED = 1 };\n\n    Range():\n      header(),\n      radiation_type(0),\n      field_of_view(0),\n      min_range(0),\n      max_range(0),\n      range(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      *(outbuffer + offset + 0) = (this->radiation_type >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->radiation_type);\n      union {\n        float real;\n        uint32_t base;\n      } u_field_of_view;\n      u_field_of_view.real = this->field_of_view;\n      *(outbuffer + offset + 0) = (u_field_of_view.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_field_of_view.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_field_of_view.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_field_of_view.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->field_of_view);\n      union {\n        float real;\n        uint32_t base;\n      } u_min_range;\n      u_min_range.real = this->min_range;\n      *(outbuffer + offset + 0) = (u_min_range.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_min_range.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_min_range.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_min_range.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->min_range);\n      union {\n        float real;\n        uint32_t base;\n      } u_max_range;\n      u_max_range.real = this->max_range;\n      *(outbuffer + offset + 0) = (u_max_range.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_max_range.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_max_range.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_max_range.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->max_range);\n      union {\n        float real;\n        uint32_t base;\n      } u_range;\n      u_range.real = this->range;\n      *(outbuffer + offset + 0) = (u_range.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_range.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_range.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_range.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->range);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      this->radiation_type =  ((uint8_t) (*(inbuffer + offset)));\n      offset += sizeof(this->radiation_type);\n      union {\n        float real;\n        uint32_t base;\n      } u_field_of_view;\n      u_field_of_view.base = 0;\n      u_field_of_view.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_field_of_view.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_field_of_view.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_field_of_view.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->field_of_view = u_field_of_view.real;\n      offset += sizeof(this->field_of_view);\n      union {\n        float real;\n        uint32_t base;\n      } u_min_range;\n      u_min_range.base = 0;\n      u_min_range.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_min_range.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_min_range.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_min_range.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->min_range = u_min_range.real;\n      offset += sizeof(this->min_range);\n      union {\n        float real;\n        uint32_t base;\n      } u_max_range;\n      u_max_range.base = 0;\n      u_max_range.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_max_range.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_max_range.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_max_range.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->max_range = u_max_range.real;\n      offset += sizeof(this->max_range);\n      union {\n        float real;\n        uint32_t base;\n      } u_range;\n      u_range.base = 0;\n      u_range.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_range.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_range.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_range.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->range = u_range.real;\n      offset += sizeof(this->range);\n     return offset;\n    }\n\n    const char * getType(){ return \"sensor_msgs/Range\"; };\n    const char * getMD5(){ return \"c005c34273dc426c67a020a87bc24148\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/sensor_msgs/RegionOfInterest.h",
    "content": "#ifndef _ROS_sensor_msgs_RegionOfInterest_h\n#define _ROS_sensor_msgs_RegionOfInterest_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace sensor_msgs\n{\n\n  class RegionOfInterest : public ros::Msg\n  {\n    public:\n      typedef uint32_t _x_offset_type;\n      _x_offset_type x_offset;\n      typedef uint32_t _y_offset_type;\n      _y_offset_type y_offset;\n      typedef uint32_t _height_type;\n      _height_type height;\n      typedef uint32_t _width_type;\n      _width_type width;\n      typedef bool _do_rectify_type;\n      _do_rectify_type do_rectify;\n\n    RegionOfInterest():\n      x_offset(0),\n      y_offset(0),\n      height(0),\n      width(0),\n      do_rectify(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      *(outbuffer + offset + 0) = (this->x_offset >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->x_offset >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->x_offset >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->x_offset >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->x_offset);\n      *(outbuffer + offset + 0) = (this->y_offset >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->y_offset >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->y_offset >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->y_offset >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->y_offset);\n      *(outbuffer + offset + 0) = (this->height >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->height >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->height >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->height >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->height);\n      *(outbuffer + offset + 0) = (this->width >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->width >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->width >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->width >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->width);\n      union {\n        bool real;\n        uint8_t base;\n      } u_do_rectify;\n      u_do_rectify.real = this->do_rectify;\n      *(outbuffer + offset + 0) = (u_do_rectify.base >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->do_rectify);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      this->x_offset =  ((uint32_t) (*(inbuffer + offset)));\n      this->x_offset |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->x_offset |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->x_offset |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->x_offset);\n      this->y_offset =  ((uint32_t) (*(inbuffer + offset)));\n      this->y_offset |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->y_offset |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->y_offset |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->y_offset);\n      this->height =  ((uint32_t) (*(inbuffer + offset)));\n      this->height |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->height |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->height |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->height);\n      this->width =  ((uint32_t) (*(inbuffer + offset)));\n      this->width |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->width |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->width |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->width);\n      union {\n        bool real;\n        uint8_t base;\n      } u_do_rectify;\n      u_do_rectify.base = 0;\n      u_do_rectify.base |= ((uint8_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      this->do_rectify = u_do_rectify.real;\n      offset += sizeof(this->do_rectify);\n     return offset;\n    }\n\n    const char * getType(){ return \"sensor_msgs/RegionOfInterest\"; };\n    const char * getMD5(){ return \"bdb633039d588fcccb441a4d43ccfe09\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/sensor_msgs/RelativeHumidity.h",
    "content": "#ifndef _ROS_sensor_msgs_RelativeHumidity_h\n#define _ROS_sensor_msgs_RelativeHumidity_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n\nnamespace sensor_msgs\n{\n\n  class RelativeHumidity : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef float _relative_humidity_type;\n      _relative_humidity_type relative_humidity;\n      typedef float _variance_type;\n      _variance_type variance;\n\n    RelativeHumidity():\n      header(),\n      relative_humidity(0),\n      variance(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      offset += serializeAvrFloat64(outbuffer + offset, this->relative_humidity);\n      offset += serializeAvrFloat64(outbuffer + offset, this->variance);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->relative_humidity));\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->variance));\n     return offset;\n    }\n\n    const char * getType(){ return \"sensor_msgs/RelativeHumidity\"; };\n    const char * getMD5(){ return \"8730015b05955b7e992ce29a2678d90f\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/sensor_msgs/SetCameraInfo.h",
    "content": "#ifndef _ROS_SERVICE_SetCameraInfo_h\n#define _ROS_SERVICE_SetCameraInfo_h\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"sensor_msgs/CameraInfo.h\"\n\nnamespace sensor_msgs\n{\n\nstatic const char SETCAMERAINFO[] = \"sensor_msgs/SetCameraInfo\";\n\n  class SetCameraInfoRequest : public ros::Msg\n  {\n    public:\n      typedef sensor_msgs::CameraInfo _camera_info_type;\n      _camera_info_type camera_info;\n\n    SetCameraInfoRequest():\n      camera_info()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->camera_info.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->camera_info.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return SETCAMERAINFO; };\n    const char * getMD5(){ return \"ee34be01fdeee563d0d99cd594d5581d\"; };\n\n  };\n\n  class SetCameraInfoResponse : public ros::Msg\n  {\n    public:\n      typedef bool _success_type;\n      _success_type success;\n      typedef const char* _status_message_type;\n      _status_message_type status_message;\n\n    SetCameraInfoResponse():\n      success(0),\n      status_message(\"\")\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      union {\n        bool real;\n        uint8_t base;\n      } u_success;\n      u_success.real = this->success;\n      *(outbuffer + offset + 0) = (u_success.base >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->success);\n      uint32_t length_status_message = strlen(this->status_message);\n      varToArr(outbuffer + offset, length_status_message);\n      offset += 4;\n      memcpy(outbuffer + offset, this->status_message, length_status_message);\n      offset += length_status_message;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      union {\n        bool real;\n        uint8_t base;\n      } u_success;\n      u_success.base = 0;\n      u_success.base |= ((uint8_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      this->success = u_success.real;\n      offset += sizeof(this->success);\n      uint32_t length_status_message;\n      arrToVar(length_status_message, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_status_message; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_status_message-1]=0;\n      this->status_message = (char *)(inbuffer + offset-1);\n      offset += length_status_message;\n     return offset;\n    }\n\n    const char * getType(){ return SETCAMERAINFO; };\n    const char * getMD5(){ return \"2ec6f3eff0161f4257b808b12bc830c2\"; };\n\n  };\n\n  class SetCameraInfo {\n    public:\n    typedef SetCameraInfoRequest Request;\n    typedef SetCameraInfoResponse Response;\n  };\n\n}\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/sensor_msgs/Temperature.h",
    "content": "#ifndef _ROS_sensor_msgs_Temperature_h\n#define _ROS_sensor_msgs_Temperature_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n\nnamespace sensor_msgs\n{\n\n  class Temperature : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef float _temperature_type;\n      _temperature_type temperature;\n      typedef float _variance_type;\n      _variance_type variance;\n\n    Temperature():\n      header(),\n      temperature(0),\n      variance(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      offset += serializeAvrFloat64(outbuffer + offset, this->temperature);\n      offset += serializeAvrFloat64(outbuffer + offset, this->variance);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->temperature));\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->variance));\n     return offset;\n    }\n\n    const char * getType(){ return \"sensor_msgs/Temperature\"; };\n    const char * getMD5(){ return \"ff71b307acdbe7c871a5a6d7ed359100\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/sensor_msgs/TimeReference.h",
    "content": "#ifndef _ROS_sensor_msgs_TimeReference_h\n#define _ROS_sensor_msgs_TimeReference_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n#include \"ros/time.h\"\n\nnamespace sensor_msgs\n{\n\n  class TimeReference : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef ros::Time _time_ref_type;\n      _time_ref_type time_ref;\n      typedef const char* _source_type;\n      _source_type source;\n\n    TimeReference():\n      header(),\n      time_ref(),\n      source(\"\")\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      *(outbuffer + offset + 0) = (this->time_ref.sec >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->time_ref.sec >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->time_ref.sec >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->time_ref.sec >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->time_ref.sec);\n      *(outbuffer + offset + 0) = (this->time_ref.nsec >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->time_ref.nsec >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->time_ref.nsec >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->time_ref.nsec >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->time_ref.nsec);\n      uint32_t length_source = strlen(this->source);\n      varToArr(outbuffer + offset, length_source);\n      offset += 4;\n      memcpy(outbuffer + offset, this->source, length_source);\n      offset += length_source;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      this->time_ref.sec =  ((uint32_t) (*(inbuffer + offset)));\n      this->time_ref.sec |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->time_ref.sec |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->time_ref.sec |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->time_ref.sec);\n      this->time_ref.nsec =  ((uint32_t) (*(inbuffer + offset)));\n      this->time_ref.nsec |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->time_ref.nsec |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->time_ref.nsec |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->time_ref.nsec);\n      uint32_t length_source;\n      arrToVar(length_source, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_source; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_source-1]=0;\n      this->source = (char *)(inbuffer + offset-1);\n      offset += length_source;\n     return offset;\n    }\n\n    const char * getType(){ return \"sensor_msgs/TimeReference\"; };\n    const char * getMD5(){ return \"fded64a0265108ba86c3d38fb11c0c16\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/std_msgs/Bool.h",
    "content": "#ifndef _ROS_std_msgs_Bool_h\n#define _ROS_std_msgs_Bool_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace std_msgs\n{\n\n  class Bool : public ros::Msg\n  {\n    public:\n      typedef bool _data_type;\n      _data_type data;\n\n    Bool():\n      data(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      union {\n        bool real;\n        uint8_t base;\n      } u_data;\n      u_data.real = this->data;\n      *(outbuffer + offset + 0) = (u_data.base >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->data);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      union {\n        bool real;\n        uint8_t base;\n      } u_data;\n      u_data.base = 0;\n      u_data.base |= ((uint8_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      this->data = u_data.real;\n      offset += sizeof(this->data);\n     return offset;\n    }\n\n    const char * getType(){ return \"std_msgs/Bool\"; };\n    const char * getMD5(){ return \"8b94c1b53db61fb6aed406028ad6332a\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/std_msgs/Byte.h",
    "content": "#ifndef _ROS_std_msgs_Byte_h\n#define _ROS_std_msgs_Byte_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace std_msgs\n{\n\n  class Byte : public ros::Msg\n  {\n    public:\n      typedef int8_t _data_type;\n      _data_type data;\n\n    Byte():\n      data(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      union {\n        int8_t real;\n        uint8_t base;\n      } u_data;\n      u_data.real = this->data;\n      *(outbuffer + offset + 0) = (u_data.base >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->data);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      union {\n        int8_t real;\n        uint8_t base;\n      } u_data;\n      u_data.base = 0;\n      u_data.base |= ((uint8_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      this->data = u_data.real;\n      offset += sizeof(this->data);\n     return offset;\n    }\n\n    const char * getType(){ return \"std_msgs/Byte\"; };\n    const char * getMD5(){ return \"ad736a2e8818154c487bb80fe42ce43b\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/std_msgs/ByteMultiArray.h",
    "content": "#ifndef _ROS_std_msgs_ByteMultiArray_h\n#define _ROS_std_msgs_ByteMultiArray_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/MultiArrayLayout.h\"\n\nnamespace std_msgs\n{\n\n  class ByteMultiArray : public ros::Msg\n  {\n    public:\n      typedef std_msgs::MultiArrayLayout _layout_type;\n      _layout_type layout;\n      uint32_t data_length;\n      typedef int8_t _data_type;\n      _data_type st_data;\n      _data_type * data;\n\n    ByteMultiArray():\n      layout(),\n      data_length(0), data(NULL)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->layout.serialize(outbuffer + offset);\n      *(outbuffer + offset + 0) = (this->data_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->data_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->data_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->data_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->data_length);\n      for( uint32_t i = 0; i < data_length; i++){\n      union {\n        int8_t real;\n        uint8_t base;\n      } u_datai;\n      u_datai.real = this->data[i];\n      *(outbuffer + offset + 0) = (u_datai.base >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->data[i]);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->layout.deserialize(inbuffer + offset);\n      uint32_t data_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->data_length);\n      if(data_lengthT > data_length)\n        this->data = (int8_t*)realloc(this->data, data_lengthT * sizeof(int8_t));\n      data_length = data_lengthT;\n      for( uint32_t i = 0; i < data_length; i++){\n      union {\n        int8_t real;\n        uint8_t base;\n      } u_st_data;\n      u_st_data.base = 0;\n      u_st_data.base |= ((uint8_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      this->st_data = u_st_data.real;\n      offset += sizeof(this->st_data);\n        memcpy( &(this->data[i]), &(this->st_data), sizeof(int8_t));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"std_msgs/ByteMultiArray\"; };\n    const char * getMD5(){ return \"70ea476cbcfd65ac2f68f3cda1e891fe\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/std_msgs/Char.h",
    "content": "#ifndef _ROS_std_msgs_Char_h\n#define _ROS_std_msgs_Char_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace std_msgs\n{\n\n  class Char : public ros::Msg\n  {\n    public:\n      typedef uint8_t _data_type;\n      _data_type data;\n\n    Char():\n      data(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      *(outbuffer + offset + 0) = (this->data >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->data);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      this->data =  ((uint8_t) (*(inbuffer + offset)));\n      offset += sizeof(this->data);\n     return offset;\n    }\n\n    const char * getType(){ return \"std_msgs/Char\"; };\n    const char * getMD5(){ return \"1bf77f25acecdedba0e224b162199717\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/std_msgs/ColorRGBA.h",
    "content": "#ifndef _ROS_std_msgs_ColorRGBA_h\n#define _ROS_std_msgs_ColorRGBA_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace std_msgs\n{\n\n  class ColorRGBA : public ros::Msg\n  {\n    public:\n      typedef float _r_type;\n      _r_type r;\n      typedef float _g_type;\n      _g_type g;\n      typedef float _b_type;\n      _b_type b;\n      typedef float _a_type;\n      _a_type a;\n\n    ColorRGBA():\n      r(0),\n      g(0),\n      b(0),\n      a(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      union {\n        float real;\n        uint32_t base;\n      } u_r;\n      u_r.real = this->r;\n      *(outbuffer + offset + 0) = (u_r.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_r.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_r.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_r.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->r);\n      union {\n        float real;\n        uint32_t base;\n      } u_g;\n      u_g.real = this->g;\n      *(outbuffer + offset + 0) = (u_g.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_g.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_g.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_g.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->g);\n      union {\n        float real;\n        uint32_t base;\n      } u_b;\n      u_b.real = this->b;\n      *(outbuffer + offset + 0) = (u_b.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_b.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_b.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_b.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->b);\n      union {\n        float real;\n        uint32_t base;\n      } u_a;\n      u_a.real = this->a;\n      *(outbuffer + offset + 0) = (u_a.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_a.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_a.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_a.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->a);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      union {\n        float real;\n        uint32_t base;\n      } u_r;\n      u_r.base = 0;\n      u_r.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_r.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_r.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_r.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->r = u_r.real;\n      offset += sizeof(this->r);\n      union {\n        float real;\n        uint32_t base;\n      } u_g;\n      u_g.base = 0;\n      u_g.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_g.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_g.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_g.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->g = u_g.real;\n      offset += sizeof(this->g);\n      union {\n        float real;\n        uint32_t base;\n      } u_b;\n      u_b.base = 0;\n      u_b.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_b.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_b.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_b.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->b = u_b.real;\n      offset += sizeof(this->b);\n      union {\n        float real;\n        uint32_t base;\n      } u_a;\n      u_a.base = 0;\n      u_a.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_a.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_a.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_a.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->a = u_a.real;\n      offset += sizeof(this->a);\n     return offset;\n    }\n\n    const char * getType(){ return \"std_msgs/ColorRGBA\"; };\n    const char * getMD5(){ return \"a29a96539573343b1310c73607334b00\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/std_msgs/Duration.h",
    "content": "#ifndef _ROS_std_msgs_Duration_h\n#define _ROS_std_msgs_Duration_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"ros/duration.h\"\n\nnamespace std_msgs\n{\n\n  class Duration : public ros::Msg\n  {\n    public:\n      typedef ros::Duration _data_type;\n      _data_type data;\n\n    Duration():\n      data()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      *(outbuffer + offset + 0) = (this->data.sec >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->data.sec >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->data.sec >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->data.sec >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->data.sec);\n      *(outbuffer + offset + 0) = (this->data.nsec >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->data.nsec >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->data.nsec >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->data.nsec >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->data.nsec);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      this->data.sec =  ((uint32_t) (*(inbuffer + offset)));\n      this->data.sec |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->data.sec |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->data.sec |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->data.sec);\n      this->data.nsec =  ((uint32_t) (*(inbuffer + offset)));\n      this->data.nsec |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->data.nsec |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->data.nsec |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->data.nsec);\n     return offset;\n    }\n\n    const char * getType(){ return \"std_msgs/Duration\"; };\n    const char * getMD5(){ return \"3e286caf4241d664e55f3ad380e2ae46\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/std_msgs/Empty.h",
    "content": "#ifndef _ROS_std_msgs_Empty_h\n#define _ROS_std_msgs_Empty_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace std_msgs\n{\n\n  class Empty : public ros::Msg\n  {\n    public:\n\n    Empty()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n     return offset;\n    }\n\n    const char * getType(){ return \"std_msgs/Empty\"; };\n    const char * getMD5(){ return \"d41d8cd98f00b204e9800998ecf8427e\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/std_msgs/Float32.h",
    "content": "#ifndef _ROS_std_msgs_Float32_h\n#define _ROS_std_msgs_Float32_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace std_msgs\n{\n\n  class Float32 : public ros::Msg\n  {\n    public:\n      typedef float _data_type;\n      _data_type data;\n\n    Float32():\n      data(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      union {\n        float real;\n        uint32_t base;\n      } u_data;\n      u_data.real = this->data;\n      *(outbuffer + offset + 0) = (u_data.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_data.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_data.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_data.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->data);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      union {\n        float real;\n        uint32_t base;\n      } u_data;\n      u_data.base = 0;\n      u_data.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_data.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_data.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_data.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->data = u_data.real;\n      offset += sizeof(this->data);\n     return offset;\n    }\n\n    const char * getType(){ return \"std_msgs/Float32\"; };\n    const char * getMD5(){ return \"73fcbf46b49191e672908e50842a83d4\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/std_msgs/Float32MultiArray.h",
    "content": "#ifndef _ROS_std_msgs_Float32MultiArray_h\n#define _ROS_std_msgs_Float32MultiArray_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/MultiArrayLayout.h\"\n\nnamespace std_msgs\n{\n\n  class Float32MultiArray : public ros::Msg\n  {\n    public:\n      typedef std_msgs::MultiArrayLayout _layout_type;\n      _layout_type layout;\n      uint32_t data_length;\n      typedef float _data_type;\n      _data_type st_data;\n      _data_type * data;\n\n    Float32MultiArray():\n      layout(),\n      data_length(0), data(NULL)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->layout.serialize(outbuffer + offset);\n      *(outbuffer + offset + 0) = (this->data_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->data_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->data_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->data_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->data_length);\n      for( uint32_t i = 0; i < data_length; i++){\n      union {\n        float real;\n        uint32_t base;\n      } u_datai;\n      u_datai.real = this->data[i];\n      *(outbuffer + offset + 0) = (u_datai.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_datai.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_datai.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_datai.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->data[i]);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->layout.deserialize(inbuffer + offset);\n      uint32_t data_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->data_length);\n      if(data_lengthT > data_length)\n        this->data = (float*)realloc(this->data, data_lengthT * sizeof(float));\n      data_length = data_lengthT;\n      for( uint32_t i = 0; i < data_length; i++){\n      union {\n        float real;\n        uint32_t base;\n      } u_st_data;\n      u_st_data.base = 0;\n      u_st_data.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_st_data.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_st_data.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_st_data.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->st_data = u_st_data.real;\n      offset += sizeof(this->st_data);\n        memcpy( &(this->data[i]), &(this->st_data), sizeof(float));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"std_msgs/Float32MultiArray\"; };\n    const char * getMD5(){ return \"6a40e0ffa6a17a503ac3f8616991b1f6\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/std_msgs/Float64.h",
    "content": "#ifndef _ROS_std_msgs_Float64_h\n#define _ROS_std_msgs_Float64_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace std_msgs\n{\n\n  class Float64 : public ros::Msg\n  {\n    public:\n      typedef float _data_type;\n      _data_type data;\n\n    Float64():\n      data(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += serializeAvrFloat64(outbuffer + offset, this->data);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->data));\n     return offset;\n    }\n\n    const char * getType(){ return \"std_msgs/Float64\"; };\n    const char * getMD5(){ return \"fdb28210bfa9d7c91146260178d9a584\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/std_msgs/Float64MultiArray.h",
    "content": "#ifndef _ROS_std_msgs_Float64MultiArray_h\n#define _ROS_std_msgs_Float64MultiArray_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/MultiArrayLayout.h\"\n\nnamespace std_msgs\n{\n\n  class Float64MultiArray : public ros::Msg\n  {\n    public:\n      typedef std_msgs::MultiArrayLayout _layout_type;\n      _layout_type layout;\n      uint32_t data_length;\n      typedef float _data_type;\n      _data_type st_data;\n      _data_type * data;\n\n    Float64MultiArray():\n      layout(),\n      data_length(0), data(NULL)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->layout.serialize(outbuffer + offset);\n      *(outbuffer + offset + 0) = (this->data_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->data_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->data_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->data_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->data_length);\n      for( uint32_t i = 0; i < data_length; i++){\n      offset += serializeAvrFloat64(outbuffer + offset, this->data[i]);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->layout.deserialize(inbuffer + offset);\n      uint32_t data_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->data_length);\n      if(data_lengthT > data_length)\n        this->data = (float*)realloc(this->data, data_lengthT * sizeof(float));\n      data_length = data_lengthT;\n      for( uint32_t i = 0; i < data_length; i++){\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->st_data));\n        memcpy( &(this->data[i]), &(this->st_data), sizeof(float));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"std_msgs/Float64MultiArray\"; };\n    const char * getMD5(){ return \"4b7d974086d4060e7db4613a7e6c3ba4\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/std_msgs/Header.h",
    "content": "#ifndef _ROS_std_msgs_Header_h\n#define _ROS_std_msgs_Header_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"ros/time.h\"\n\nnamespace std_msgs\n{\n\n  class Header : public ros::Msg\n  {\n    public:\n      typedef uint32_t _seq_type;\n      _seq_type seq;\n      typedef ros::Time _stamp_type;\n      _stamp_type stamp;\n      typedef const char* _frame_id_type;\n      _frame_id_type frame_id;\n\n    Header():\n      seq(0),\n      stamp(),\n      frame_id(\"\")\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      *(outbuffer + offset + 0) = (this->seq >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->seq >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->seq >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->seq >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->seq);\n      *(outbuffer + offset + 0) = (this->stamp.sec >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->stamp.sec >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->stamp.sec >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->stamp.sec >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->stamp.sec);\n      *(outbuffer + offset + 0) = (this->stamp.nsec >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->stamp.nsec >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->stamp.nsec >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->stamp.nsec >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->stamp.nsec);\n      uint32_t length_frame_id = strlen(this->frame_id);\n      varToArr(outbuffer + offset, length_frame_id);\n      offset += 4;\n      memcpy(outbuffer + offset, this->frame_id, length_frame_id);\n      offset += length_frame_id;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      this->seq =  ((uint32_t) (*(inbuffer + offset)));\n      this->seq |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->seq |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->seq |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->seq);\n      this->stamp.sec =  ((uint32_t) (*(inbuffer + offset)));\n      this->stamp.sec |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->stamp.sec |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->stamp.sec |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->stamp.sec);\n      this->stamp.nsec =  ((uint32_t) (*(inbuffer + offset)));\n      this->stamp.nsec |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->stamp.nsec |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->stamp.nsec |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->stamp.nsec);\n      uint32_t length_frame_id;\n      arrToVar(length_frame_id, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_frame_id; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_frame_id-1]=0;\n      this->frame_id = (char *)(inbuffer + offset-1);\n      offset += length_frame_id;\n     return offset;\n    }\n\n    const char * getType(){ return \"std_msgs/Header\"; };\n    const char * getMD5(){ return \"2176decaecbce78abc3b96ef049fabed\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/std_msgs/Int16.h",
    "content": "#ifndef _ROS_std_msgs_Int16_h\n#define _ROS_std_msgs_Int16_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace std_msgs\n{\n\n  class Int16 : public ros::Msg\n  {\n    public:\n      typedef int16_t _data_type;\n      _data_type data;\n\n    Int16():\n      data(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      union {\n        int16_t real;\n        uint16_t base;\n      } u_data;\n      u_data.real = this->data;\n      *(outbuffer + offset + 0) = (u_data.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_data.base >> (8 * 1)) & 0xFF;\n      offset += sizeof(this->data);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      union {\n        int16_t real;\n        uint16_t base;\n      } u_data;\n      u_data.base = 0;\n      u_data.base |= ((uint16_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_data.base |= ((uint16_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->data = u_data.real;\n      offset += sizeof(this->data);\n     return offset;\n    }\n\n    const char * getType(){ return \"std_msgs/Int16\"; };\n    const char * getMD5(){ return \"8524586e34fbd7cb1c08c5f5f1ca0e57\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/std_msgs/Int16MultiArray.h",
    "content": "#ifndef _ROS_std_msgs_Int16MultiArray_h\n#define _ROS_std_msgs_Int16MultiArray_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/MultiArrayLayout.h\"\n\nnamespace std_msgs\n{\n\n  class Int16MultiArray : public ros::Msg\n  {\n    public:\n      typedef std_msgs::MultiArrayLayout _layout_type;\n      _layout_type layout;\n      uint32_t data_length;\n      typedef int16_t _data_type;\n      _data_type st_data;\n      _data_type * data;\n\n    Int16MultiArray():\n      layout(),\n      data_length(0), data(NULL)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->layout.serialize(outbuffer + offset);\n      *(outbuffer + offset + 0) = (this->data_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->data_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->data_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->data_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->data_length);\n      for( uint32_t i = 0; i < data_length; i++){\n      union {\n        int16_t real;\n        uint16_t base;\n      } u_datai;\n      u_datai.real = this->data[i];\n      *(outbuffer + offset + 0) = (u_datai.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_datai.base >> (8 * 1)) & 0xFF;\n      offset += sizeof(this->data[i]);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->layout.deserialize(inbuffer + offset);\n      uint32_t data_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->data_length);\n      if(data_lengthT > data_length)\n        this->data = (int16_t*)realloc(this->data, data_lengthT * sizeof(int16_t));\n      data_length = data_lengthT;\n      for( uint32_t i = 0; i < data_length; i++){\n      union {\n        int16_t real;\n        uint16_t base;\n      } u_st_data;\n      u_st_data.base = 0;\n      u_st_data.base |= ((uint16_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_st_data.base |= ((uint16_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->st_data = u_st_data.real;\n      offset += sizeof(this->st_data);\n        memcpy( &(this->data[i]), &(this->st_data), sizeof(int16_t));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"std_msgs/Int16MultiArray\"; };\n    const char * getMD5(){ return \"d9338d7f523fcb692fae9d0a0e9f067c\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/std_msgs/Int32.h",
    "content": "#ifndef _ROS_std_msgs_Int32_h\n#define _ROS_std_msgs_Int32_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace std_msgs\n{\n\n  class Int32 : public ros::Msg\n  {\n    public:\n      typedef int32_t _data_type;\n      _data_type data;\n\n    Int32():\n      data(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      union {\n        int32_t real;\n        uint32_t base;\n      } u_data;\n      u_data.real = this->data;\n      *(outbuffer + offset + 0) = (u_data.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_data.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_data.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_data.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->data);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      union {\n        int32_t real;\n        uint32_t base;\n      } u_data;\n      u_data.base = 0;\n      u_data.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_data.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_data.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_data.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->data = u_data.real;\n      offset += sizeof(this->data);\n     return offset;\n    }\n\n    const char * getType(){ return \"std_msgs/Int32\"; };\n    const char * getMD5(){ return \"da5909fbe378aeaf85e547e830cc1bb7\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/std_msgs/Int32MultiArray.h",
    "content": "#ifndef _ROS_std_msgs_Int32MultiArray_h\n#define _ROS_std_msgs_Int32MultiArray_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/MultiArrayLayout.h\"\n\nnamespace std_msgs\n{\n\n  class Int32MultiArray : public ros::Msg\n  {\n    public:\n      typedef std_msgs::MultiArrayLayout _layout_type;\n      _layout_type layout;\n      uint32_t data_length;\n      typedef int32_t _data_type;\n      _data_type st_data;\n      _data_type * data;\n\n    Int32MultiArray():\n      layout(),\n      data_length(0), data(NULL)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->layout.serialize(outbuffer + offset);\n      *(outbuffer + offset + 0) = (this->data_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->data_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->data_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->data_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->data_length);\n      for( uint32_t i = 0; i < data_length; i++){\n      union {\n        int32_t real;\n        uint32_t base;\n      } u_datai;\n      u_datai.real = this->data[i];\n      *(outbuffer + offset + 0) = (u_datai.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_datai.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_datai.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_datai.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->data[i]);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->layout.deserialize(inbuffer + offset);\n      uint32_t data_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->data_length);\n      if(data_lengthT > data_length)\n        this->data = (int32_t*)realloc(this->data, data_lengthT * sizeof(int32_t));\n      data_length = data_lengthT;\n      for( uint32_t i = 0; i < data_length; i++){\n      union {\n        int32_t real;\n        uint32_t base;\n      } u_st_data;\n      u_st_data.base = 0;\n      u_st_data.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_st_data.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_st_data.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_st_data.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->st_data = u_st_data.real;\n      offset += sizeof(this->st_data);\n        memcpy( &(this->data[i]), &(this->st_data), sizeof(int32_t));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"std_msgs/Int32MultiArray\"; };\n    const char * getMD5(){ return \"1d99f79f8b325b44fee908053e9c945b\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/std_msgs/Int64.h",
    "content": "#ifndef _ROS_std_msgs_Int64_h\n#define _ROS_std_msgs_Int64_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace std_msgs\n{\n\n  class Int64 : public ros::Msg\n  {\n    public:\n      typedef int64_t _data_type;\n      _data_type data;\n\n    Int64():\n      data(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      union {\n        int64_t real;\n        uint64_t base;\n      } u_data;\n      u_data.real = this->data;\n      *(outbuffer + offset + 0) = (u_data.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_data.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_data.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_data.base >> (8 * 3)) & 0xFF;\n      *(outbuffer + offset + 4) = (u_data.base >> (8 * 4)) & 0xFF;\n      *(outbuffer + offset + 5) = (u_data.base >> (8 * 5)) & 0xFF;\n      *(outbuffer + offset + 6) = (u_data.base >> (8 * 6)) & 0xFF;\n      *(outbuffer + offset + 7) = (u_data.base >> (8 * 7)) & 0xFF;\n      offset += sizeof(this->data);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      union {\n        int64_t real;\n        uint64_t base;\n      } u_data;\n      u_data.base = 0;\n      u_data.base |= ((uint64_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_data.base |= ((uint64_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_data.base |= ((uint64_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_data.base |= ((uint64_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      u_data.base |= ((uint64_t) (*(inbuffer + offset + 4))) << (8 * 4);\n      u_data.base |= ((uint64_t) (*(inbuffer + offset + 5))) << (8 * 5);\n      u_data.base |= ((uint64_t) (*(inbuffer + offset + 6))) << (8 * 6);\n      u_data.base |= ((uint64_t) (*(inbuffer + offset + 7))) << (8 * 7);\n      this->data = u_data.real;\n      offset += sizeof(this->data);\n     return offset;\n    }\n\n    const char * getType(){ return \"std_msgs/Int64\"; };\n    const char * getMD5(){ return \"34add168574510e6e17f5d23ecc077ef\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/std_msgs/Int64MultiArray.h",
    "content": "#ifndef _ROS_std_msgs_Int64MultiArray_h\n#define _ROS_std_msgs_Int64MultiArray_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/MultiArrayLayout.h\"\n\nnamespace std_msgs\n{\n\n  class Int64MultiArray : public ros::Msg\n  {\n    public:\n      typedef std_msgs::MultiArrayLayout _layout_type;\n      _layout_type layout;\n      uint32_t data_length;\n      typedef int64_t _data_type;\n      _data_type st_data;\n      _data_type * data;\n\n    Int64MultiArray():\n      layout(),\n      data_length(0), data(NULL)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->layout.serialize(outbuffer + offset);\n      *(outbuffer + offset + 0) = (this->data_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->data_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->data_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->data_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->data_length);\n      for( uint32_t i = 0; i < data_length; i++){\n      union {\n        int64_t real;\n        uint64_t base;\n      } u_datai;\n      u_datai.real = this->data[i];\n      *(outbuffer + offset + 0) = (u_datai.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_datai.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_datai.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_datai.base >> (8 * 3)) & 0xFF;\n      *(outbuffer + offset + 4) = (u_datai.base >> (8 * 4)) & 0xFF;\n      *(outbuffer + offset + 5) = (u_datai.base >> (8 * 5)) & 0xFF;\n      *(outbuffer + offset + 6) = (u_datai.base >> (8 * 6)) & 0xFF;\n      *(outbuffer + offset + 7) = (u_datai.base >> (8 * 7)) & 0xFF;\n      offset += sizeof(this->data[i]);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->layout.deserialize(inbuffer + offset);\n      uint32_t data_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->data_length);\n      if(data_lengthT > data_length)\n        this->data = (int64_t*)realloc(this->data, data_lengthT * sizeof(int64_t));\n      data_length = data_lengthT;\n      for( uint32_t i = 0; i < data_length; i++){\n      union {\n        int64_t real;\n        uint64_t base;\n      } u_st_data;\n      u_st_data.base = 0;\n      u_st_data.base |= ((uint64_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_st_data.base |= ((uint64_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_st_data.base |= ((uint64_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_st_data.base |= ((uint64_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      u_st_data.base |= ((uint64_t) (*(inbuffer + offset + 4))) << (8 * 4);\n      u_st_data.base |= ((uint64_t) (*(inbuffer + offset + 5))) << (8 * 5);\n      u_st_data.base |= ((uint64_t) (*(inbuffer + offset + 6))) << (8 * 6);\n      u_st_data.base |= ((uint64_t) (*(inbuffer + offset + 7))) << (8 * 7);\n      this->st_data = u_st_data.real;\n      offset += sizeof(this->st_data);\n        memcpy( &(this->data[i]), &(this->st_data), sizeof(int64_t));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"std_msgs/Int64MultiArray\"; };\n    const char * getMD5(){ return \"54865aa6c65be0448113a2afc6a49270\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/std_msgs/Int8.h",
    "content": "#ifndef _ROS_std_msgs_Int8_h\n#define _ROS_std_msgs_Int8_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace std_msgs\n{\n\n  class Int8 : public ros::Msg\n  {\n    public:\n      typedef int8_t _data_type;\n      _data_type data;\n\n    Int8():\n      data(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      union {\n        int8_t real;\n        uint8_t base;\n      } u_data;\n      u_data.real = this->data;\n      *(outbuffer + offset + 0) = (u_data.base >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->data);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      union {\n        int8_t real;\n        uint8_t base;\n      } u_data;\n      u_data.base = 0;\n      u_data.base |= ((uint8_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      this->data = u_data.real;\n      offset += sizeof(this->data);\n     return offset;\n    }\n\n    const char * getType(){ return \"std_msgs/Int8\"; };\n    const char * getMD5(){ return \"27ffa0c9c4b8fb8492252bcad9e5c57b\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/std_msgs/Int8MultiArray.h",
    "content": "#ifndef _ROS_std_msgs_Int8MultiArray_h\n#define _ROS_std_msgs_Int8MultiArray_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/MultiArrayLayout.h\"\n\nnamespace std_msgs\n{\n\n  class Int8MultiArray : public ros::Msg\n  {\n    public:\n      typedef std_msgs::MultiArrayLayout _layout_type;\n      _layout_type layout;\n      uint32_t data_length;\n      typedef int8_t _data_type;\n      _data_type st_data;\n      _data_type * data;\n\n    Int8MultiArray():\n      layout(),\n      data_length(0), data(NULL)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->layout.serialize(outbuffer + offset);\n      *(outbuffer + offset + 0) = (this->data_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->data_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->data_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->data_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->data_length);\n      for( uint32_t i = 0; i < data_length; i++){\n      union {\n        int8_t real;\n        uint8_t base;\n      } u_datai;\n      u_datai.real = this->data[i];\n      *(outbuffer + offset + 0) = (u_datai.base >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->data[i]);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->layout.deserialize(inbuffer + offset);\n      uint32_t data_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->data_length);\n      if(data_lengthT > data_length)\n        this->data = (int8_t*)realloc(this->data, data_lengthT * sizeof(int8_t));\n      data_length = data_lengthT;\n      for( uint32_t i = 0; i < data_length; i++){\n      union {\n        int8_t real;\n        uint8_t base;\n      } u_st_data;\n      u_st_data.base = 0;\n      u_st_data.base |= ((uint8_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      this->st_data = u_st_data.real;\n      offset += sizeof(this->st_data);\n        memcpy( &(this->data[i]), &(this->st_data), sizeof(int8_t));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"std_msgs/Int8MultiArray\"; };\n    const char * getMD5(){ return \"d7c1af35a1b4781bbe79e03dd94b7c13\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/std_msgs/MultiArrayDimension.h",
    "content": "#ifndef _ROS_std_msgs_MultiArrayDimension_h\n#define _ROS_std_msgs_MultiArrayDimension_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace std_msgs\n{\n\n  class MultiArrayDimension : public ros::Msg\n  {\n    public:\n      typedef const char* _label_type;\n      _label_type label;\n      typedef uint32_t _size_type;\n      _size_type size;\n      typedef uint32_t _stride_type;\n      _stride_type stride;\n\n    MultiArrayDimension():\n      label(\"\"),\n      size(0),\n      stride(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      uint32_t length_label = strlen(this->label);\n      varToArr(outbuffer + offset, length_label);\n      offset += 4;\n      memcpy(outbuffer + offset, this->label, length_label);\n      offset += length_label;\n      *(outbuffer + offset + 0) = (this->size >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->size >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->size >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->size >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->size);\n      *(outbuffer + offset + 0) = (this->stride >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->stride >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->stride >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->stride >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->stride);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      uint32_t length_label;\n      arrToVar(length_label, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_label; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_label-1]=0;\n      this->label = (char *)(inbuffer + offset-1);\n      offset += length_label;\n      this->size =  ((uint32_t) (*(inbuffer + offset)));\n      this->size |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->size |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->size |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->size);\n      this->stride =  ((uint32_t) (*(inbuffer + offset)));\n      this->stride |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->stride |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->stride |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->stride);\n     return offset;\n    }\n\n    const char * getType(){ return \"std_msgs/MultiArrayDimension\"; };\n    const char * getMD5(){ return \"4cd0c83a8683deae40ecdac60e53bfa8\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/std_msgs/MultiArrayLayout.h",
    "content": "#ifndef _ROS_std_msgs_MultiArrayLayout_h\n#define _ROS_std_msgs_MultiArrayLayout_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/MultiArrayDimension.h\"\n\nnamespace std_msgs\n{\n\n  class MultiArrayLayout : public ros::Msg\n  {\n    public:\n      uint32_t dim_length;\n      typedef std_msgs::MultiArrayDimension _dim_type;\n      _dim_type st_dim;\n      _dim_type * dim;\n      typedef uint32_t _data_offset_type;\n      _data_offset_type data_offset;\n\n    MultiArrayLayout():\n      dim_length(0), dim(NULL),\n      data_offset(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      *(outbuffer + offset + 0) = (this->dim_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->dim_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->dim_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->dim_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->dim_length);\n      for( uint32_t i = 0; i < dim_length; i++){\n      offset += this->dim[i].serialize(outbuffer + offset);\n      }\n      *(outbuffer + offset + 0) = (this->data_offset >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->data_offset >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->data_offset >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->data_offset >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->data_offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      uint32_t dim_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      dim_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      dim_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      dim_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->dim_length);\n      if(dim_lengthT > dim_length)\n        this->dim = (std_msgs::MultiArrayDimension*)realloc(this->dim, dim_lengthT * sizeof(std_msgs::MultiArrayDimension));\n      dim_length = dim_lengthT;\n      for( uint32_t i = 0; i < dim_length; i++){\n      offset += this->st_dim.deserialize(inbuffer + offset);\n        memcpy( &(this->dim[i]), &(this->st_dim), sizeof(std_msgs::MultiArrayDimension));\n      }\n      this->data_offset =  ((uint32_t) (*(inbuffer + offset)));\n      this->data_offset |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->data_offset |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->data_offset |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->data_offset);\n     return offset;\n    }\n\n    const char * getType(){ return \"std_msgs/MultiArrayLayout\"; };\n    const char * getMD5(){ return \"0fed2a11c13e11c5571b4e2a995a91a3\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/std_msgs/String.h",
    "content": "#ifndef _ROS_std_msgs_String_h\n#define _ROS_std_msgs_String_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace std_msgs\n{\n\n  class String : public ros::Msg\n  {\n    public:\n      typedef const char* _data_type;\n      _data_type data;\n\n    String():\n      data(\"\")\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      uint32_t length_data = strlen(this->data);\n      varToArr(outbuffer + offset, length_data);\n      offset += 4;\n      memcpy(outbuffer + offset, this->data, length_data);\n      offset += length_data;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      uint32_t length_data;\n      arrToVar(length_data, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_data; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_data-1]=0;\n      this->data = (char *)(inbuffer + offset-1);\n      offset += length_data;\n     return offset;\n    }\n\n    const char * getType(){ return \"std_msgs/String\"; };\n    const char * getMD5(){ return \"992ce8a1687cec8c8bd883ec73ca41d1\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/std_msgs/Time.h",
    "content": "#ifndef _ROS_std_msgs_Time_h\n#define _ROS_std_msgs_Time_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"ros/time.h\"\n\nnamespace std_msgs\n{\n\n  class Time : public ros::Msg\n  {\n    public:\n      typedef ros::Time _data_type;\n      _data_type data;\n\n    Time():\n      data()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      *(outbuffer + offset + 0) = (this->data.sec >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->data.sec >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->data.sec >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->data.sec >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->data.sec);\n      *(outbuffer + offset + 0) = (this->data.nsec >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->data.nsec >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->data.nsec >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->data.nsec >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->data.nsec);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      this->data.sec =  ((uint32_t) (*(inbuffer + offset)));\n      this->data.sec |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->data.sec |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->data.sec |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->data.sec);\n      this->data.nsec =  ((uint32_t) (*(inbuffer + offset)));\n      this->data.nsec |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->data.nsec |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->data.nsec |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->data.nsec);\n     return offset;\n    }\n\n    const char * getType(){ return \"std_msgs/Time\"; };\n    const char * getMD5(){ return \"cd7166c74c552c311fbcc2fe5a7bc289\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/std_msgs/UInt16.h",
    "content": "#ifndef _ROS_std_msgs_UInt16_h\n#define _ROS_std_msgs_UInt16_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace std_msgs\n{\n\n  class UInt16 : public ros::Msg\n  {\n    public:\n      typedef uint16_t _data_type;\n      _data_type data;\n\n    UInt16():\n      data(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      *(outbuffer + offset + 0) = (this->data >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->data >> (8 * 1)) & 0xFF;\n      offset += sizeof(this->data);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      this->data =  ((uint16_t) (*(inbuffer + offset)));\n      this->data |= ((uint16_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      offset += sizeof(this->data);\n     return offset;\n    }\n\n    const char * getType(){ return \"std_msgs/UInt16\"; };\n    const char * getMD5(){ return \"1df79edf208b629fe6b81923a544552d\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/std_msgs/UInt16MultiArray.h",
    "content": "#ifndef _ROS_std_msgs_UInt16MultiArray_h\n#define _ROS_std_msgs_UInt16MultiArray_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/MultiArrayLayout.h\"\n\nnamespace std_msgs\n{\n\n  class UInt16MultiArray : public ros::Msg\n  {\n    public:\n      typedef std_msgs::MultiArrayLayout _layout_type;\n      _layout_type layout;\n      uint32_t data_length;\n      typedef uint16_t _data_type;\n      _data_type st_data;\n      _data_type * data;\n\n    UInt16MultiArray():\n      layout(),\n      data_length(0), data(NULL)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->layout.serialize(outbuffer + offset);\n      *(outbuffer + offset + 0) = (this->data_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->data_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->data_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->data_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->data_length);\n      for( uint32_t i = 0; i < data_length; i++){\n      *(outbuffer + offset + 0) = (this->data[i] >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->data[i] >> (8 * 1)) & 0xFF;\n      offset += sizeof(this->data[i]);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->layout.deserialize(inbuffer + offset);\n      uint32_t data_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->data_length);\n      if(data_lengthT > data_length)\n        this->data = (uint16_t*)realloc(this->data, data_lengthT * sizeof(uint16_t));\n      data_length = data_lengthT;\n      for( uint32_t i = 0; i < data_length; i++){\n      this->st_data =  ((uint16_t) (*(inbuffer + offset)));\n      this->st_data |= ((uint16_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      offset += sizeof(this->st_data);\n        memcpy( &(this->data[i]), &(this->st_data), sizeof(uint16_t));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"std_msgs/UInt16MultiArray\"; };\n    const char * getMD5(){ return \"52f264f1c973c4b73790d384c6cb4484\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/std_msgs/UInt32.h",
    "content": "#ifndef _ROS_std_msgs_UInt32_h\n#define _ROS_std_msgs_UInt32_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace std_msgs\n{\n\n  class UInt32 : public ros::Msg\n  {\n    public:\n      typedef uint32_t _data_type;\n      _data_type data;\n\n    UInt32():\n      data(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      *(outbuffer + offset + 0) = (this->data >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->data >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->data >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->data >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->data);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      this->data =  ((uint32_t) (*(inbuffer + offset)));\n      this->data |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->data |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->data |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->data);\n     return offset;\n    }\n\n    const char * getType(){ return \"std_msgs/UInt32\"; };\n    const char * getMD5(){ return \"304a39449588c7f8ce2df6e8001c5fce\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/std_msgs/UInt32MultiArray.h",
    "content": "#ifndef _ROS_std_msgs_UInt32MultiArray_h\n#define _ROS_std_msgs_UInt32MultiArray_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/MultiArrayLayout.h\"\n\nnamespace std_msgs\n{\n\n  class UInt32MultiArray : public ros::Msg\n  {\n    public:\n      typedef std_msgs::MultiArrayLayout _layout_type;\n      _layout_type layout;\n      uint32_t data_length;\n      typedef uint32_t _data_type;\n      _data_type st_data;\n      _data_type * data;\n\n    UInt32MultiArray():\n      layout(),\n      data_length(0), data(NULL)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->layout.serialize(outbuffer + offset);\n      *(outbuffer + offset + 0) = (this->data_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->data_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->data_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->data_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->data_length);\n      for( uint32_t i = 0; i < data_length; i++){\n      *(outbuffer + offset + 0) = (this->data[i] >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->data[i] >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->data[i] >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->data[i] >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->data[i]);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->layout.deserialize(inbuffer + offset);\n      uint32_t data_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->data_length);\n      if(data_lengthT > data_length)\n        this->data = (uint32_t*)realloc(this->data, data_lengthT * sizeof(uint32_t));\n      data_length = data_lengthT;\n      for( uint32_t i = 0; i < data_length; i++){\n      this->st_data =  ((uint32_t) (*(inbuffer + offset)));\n      this->st_data |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->st_data |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->st_data |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->st_data);\n        memcpy( &(this->data[i]), &(this->st_data), sizeof(uint32_t));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"std_msgs/UInt32MultiArray\"; };\n    const char * getMD5(){ return \"4d6a180abc9be191b96a7eda6c8a233d\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/std_msgs/UInt64.h",
    "content": "#ifndef _ROS_std_msgs_UInt64_h\n#define _ROS_std_msgs_UInt64_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace std_msgs\n{\n\n  class UInt64 : public ros::Msg\n  {\n    public:\n      typedef uint64_t _data_type;\n      _data_type data;\n\n    UInt64():\n      data(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      union {\n        uint64_t real;\n        uint32_t base;\n      } u_data;\n      u_data.real = this->data;\n      *(outbuffer + offset + 0) = (u_data.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_data.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_data.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_data.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->data);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      union {\n        uint64_t real;\n        uint32_t base;\n      } u_data;\n      u_data.base = 0;\n      u_data.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_data.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_data.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_data.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->data = u_data.real;\n      offset += sizeof(this->data);\n     return offset;\n    }\n\n    const char * getType(){ return \"std_msgs/UInt64\"; };\n    const char * getMD5(){ return \"1b2a79973e8bf53d7b53acb71299cb57\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/std_msgs/UInt64MultiArray.h",
    "content": "#ifndef _ROS_std_msgs_UInt64MultiArray_h\n#define _ROS_std_msgs_UInt64MultiArray_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/MultiArrayLayout.h\"\n\nnamespace std_msgs\n{\n\n  class UInt64MultiArray : public ros::Msg\n  {\n    public:\n      typedef std_msgs::MultiArrayLayout _layout_type;\n      _layout_type layout;\n      uint32_t data_length;\n      typedef uint64_t _data_type;\n      _data_type st_data;\n      _data_type * data;\n\n    UInt64MultiArray():\n      layout(),\n      data_length(0), data(NULL)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->layout.serialize(outbuffer + offset);\n      *(outbuffer + offset + 0) = (this->data_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->data_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->data_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->data_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->data_length);\n      for( uint32_t i = 0; i < data_length; i++){\n      union {\n        uint64_t real;\n        uint32_t base;\n      } u_datai;\n      u_datai.real = this->data[i];\n      *(outbuffer + offset + 0) = (u_datai.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_datai.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_datai.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_datai.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->data[i]);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->layout.deserialize(inbuffer + offset);\n      uint32_t data_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->data_length);\n      if(data_lengthT > data_length)\n        this->data = (uint64_t*)realloc(this->data, data_lengthT * sizeof(uint64_t));\n      data_length = data_lengthT;\n      for( uint32_t i = 0; i < data_length; i++){\n      union {\n        uint64_t real;\n        uint32_t base;\n      } u_st_data;\n      u_st_data.base = 0;\n      u_st_data.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_st_data.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_st_data.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_st_data.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->st_data = u_st_data.real;\n      offset += sizeof(this->st_data);\n        memcpy( &(this->data[i]), &(this->st_data), sizeof(uint64_t));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"std_msgs/UInt64MultiArray\"; };\n    const char * getMD5(){ return \"6088f127afb1d6c72927aa1247e945af\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/std_msgs/UInt8.h",
    "content": "#ifndef _ROS_std_msgs_UInt8_h\n#define _ROS_std_msgs_UInt8_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace std_msgs\n{\n\n  class UInt8 : public ros::Msg\n  {\n    public:\n      typedef uint8_t _data_type;\n      _data_type data;\n\n    UInt8():\n      data(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      *(outbuffer + offset + 0) = (this->data >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->data);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      this->data =  ((uint8_t) (*(inbuffer + offset)));\n      offset += sizeof(this->data);\n     return offset;\n    }\n\n    const char * getType(){ return \"std_msgs/UInt8\"; };\n    const char * getMD5(){ return \"7c8164229e7d2c17eb95e9231617fdee\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/std_msgs/UInt8MultiArray.h",
    "content": "#ifndef _ROS_std_msgs_UInt8MultiArray_h\n#define _ROS_std_msgs_UInt8MultiArray_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/MultiArrayLayout.h\"\n\nnamespace std_msgs\n{\n\n  class UInt8MultiArray : public ros::Msg\n  {\n    public:\n      typedef std_msgs::MultiArrayLayout _layout_type;\n      _layout_type layout;\n      uint32_t data_length;\n      typedef uint8_t _data_type;\n      _data_type st_data;\n      _data_type * data;\n\n    UInt8MultiArray():\n      layout(),\n      data_length(0), data(NULL)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->layout.serialize(outbuffer + offset);\n      *(outbuffer + offset + 0) = (this->data_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->data_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->data_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->data_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->data_length);\n      for( uint32_t i = 0; i < data_length; i++){\n      *(outbuffer + offset + 0) = (this->data[i] >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->data[i]);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->layout.deserialize(inbuffer + offset);\n      uint32_t data_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      data_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->data_length);\n      if(data_lengthT > data_length)\n        this->data = (uint8_t*)realloc(this->data, data_lengthT * sizeof(uint8_t));\n      data_length = data_lengthT;\n      for( uint32_t i = 0; i < data_length; i++){\n      this->st_data =  ((uint8_t) (*(inbuffer + offset)));\n      offset += sizeof(this->st_data);\n        memcpy( &(this->data[i]), &(this->st_data), sizeof(uint8_t));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"std_msgs/UInt8MultiArray\"; };\n    const char * getMD5(){ return \"82373f1612381bb6ee473b5cd6f5d89c\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/std_srvs/Empty.h",
    "content": "#ifndef _ROS_SERVICE_Empty_h\n#define _ROS_SERVICE_Empty_h\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace std_srvs\n{\n\nstatic const char EMPTY[] = \"std_srvs/Empty\";\n\n  class EmptyRequest : public ros::Msg\n  {\n    public:\n\n    EmptyRequest()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n     return offset;\n    }\n\n    const char * getType(){ return EMPTY; };\n    const char * getMD5(){ return \"d41d8cd98f00b204e9800998ecf8427e\"; };\n\n  };\n\n  class EmptyResponse : public ros::Msg\n  {\n    public:\n\n    EmptyResponse()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n     return offset;\n    }\n\n    const char * getType(){ return EMPTY; };\n    const char * getMD5(){ return \"d41d8cd98f00b204e9800998ecf8427e\"; };\n\n  };\n\n  class Empty {\n    public:\n    typedef EmptyRequest Request;\n    typedef EmptyResponse Response;\n  };\n\n}\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/std_srvs/SetBool.h",
    "content": "#ifndef _ROS_SERVICE_SetBool_h\n#define _ROS_SERVICE_SetBool_h\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace std_srvs\n{\n\nstatic const char SETBOOL[] = \"std_srvs/SetBool\";\n\n  class SetBoolRequest : public ros::Msg\n  {\n    public:\n      typedef bool _data_type;\n      _data_type data;\n\n    SetBoolRequest():\n      data(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      union {\n        bool real;\n        uint8_t base;\n      } u_data;\n      u_data.real = this->data;\n      *(outbuffer + offset + 0) = (u_data.base >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->data);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      union {\n        bool real;\n        uint8_t base;\n      } u_data;\n      u_data.base = 0;\n      u_data.base |= ((uint8_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      this->data = u_data.real;\n      offset += sizeof(this->data);\n     return offset;\n    }\n\n    const char * getType(){ return SETBOOL; };\n    const char * getMD5(){ return \"8b94c1b53db61fb6aed406028ad6332a\"; };\n\n  };\n\n  class SetBoolResponse : public ros::Msg\n  {\n    public:\n      typedef bool _success_type;\n      _success_type success;\n      typedef const char* _message_type;\n      _message_type message;\n\n    SetBoolResponse():\n      success(0),\n      message(\"\")\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      union {\n        bool real;\n        uint8_t base;\n      } u_success;\n      u_success.real = this->success;\n      *(outbuffer + offset + 0) = (u_success.base >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->success);\n      uint32_t length_message = strlen(this->message);\n      varToArr(outbuffer + offset, length_message);\n      offset += 4;\n      memcpy(outbuffer + offset, this->message, length_message);\n      offset += length_message;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      union {\n        bool real;\n        uint8_t base;\n      } u_success;\n      u_success.base = 0;\n      u_success.base |= ((uint8_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      this->success = u_success.real;\n      offset += sizeof(this->success);\n      uint32_t length_message;\n      arrToVar(length_message, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_message; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_message-1]=0;\n      this->message = (char *)(inbuffer + offset-1);\n      offset += length_message;\n     return offset;\n    }\n\n    const char * getType(){ return SETBOOL; };\n    const char * getMD5(){ return \"937c9679a518e3a18d831e57125ea522\"; };\n\n  };\n\n  class SetBool {\n    public:\n    typedef SetBoolRequest Request;\n    typedef SetBoolResponse Response;\n  };\n\n}\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/std_srvs/Trigger.h",
    "content": "#ifndef _ROS_SERVICE_Trigger_h\n#define _ROS_SERVICE_Trigger_h\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace std_srvs\n{\n\nstatic const char TRIGGER[] = \"std_srvs/Trigger\";\n\n  class TriggerRequest : public ros::Msg\n  {\n    public:\n\n    TriggerRequest()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n     return offset;\n    }\n\n    const char * getType(){ return TRIGGER; };\n    const char * getMD5(){ return \"d41d8cd98f00b204e9800998ecf8427e\"; };\n\n  };\n\n  class TriggerResponse : public ros::Msg\n  {\n    public:\n      typedef bool _success_type;\n      _success_type success;\n      typedef const char* _message_type;\n      _message_type message;\n\n    TriggerResponse():\n      success(0),\n      message(\"\")\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      union {\n        bool real;\n        uint8_t base;\n      } u_success;\n      u_success.real = this->success;\n      *(outbuffer + offset + 0) = (u_success.base >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->success);\n      uint32_t length_message = strlen(this->message);\n      varToArr(outbuffer + offset, length_message);\n      offset += 4;\n      memcpy(outbuffer + offset, this->message, length_message);\n      offset += length_message;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      union {\n        bool real;\n        uint8_t base;\n      } u_success;\n      u_success.base = 0;\n      u_success.base |= ((uint8_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      this->success = u_success.real;\n      offset += sizeof(this->success);\n      uint32_t length_message;\n      arrToVar(length_message, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_message; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_message-1]=0;\n      this->message = (char *)(inbuffer + offset-1);\n      offset += length_message;\n     return offset;\n    }\n\n    const char * getType(){ return TRIGGER; };\n    const char * getMD5(){ return \"937c9679a518e3a18d831e57125ea522\"; };\n\n  };\n\n  class Trigger {\n    public:\n    typedef TriggerRequest Request;\n    typedef TriggerResponse Response;\n  };\n\n}\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/tf/FrameGraph.h",
    "content": "#ifndef _ROS_SERVICE_FrameGraph_h\n#define _ROS_SERVICE_FrameGraph_h\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace tf\n{\n\nstatic const char FRAMEGRAPH[] = \"tf/FrameGraph\";\n\n  class FrameGraphRequest : public ros::Msg\n  {\n    public:\n\n    FrameGraphRequest()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n     return offset;\n    }\n\n    const char * getType(){ return FRAMEGRAPH; };\n    const char * getMD5(){ return \"d41d8cd98f00b204e9800998ecf8427e\"; };\n\n  };\n\n  class FrameGraphResponse : public ros::Msg\n  {\n    public:\n      typedef const char* _dot_graph_type;\n      _dot_graph_type dot_graph;\n\n    FrameGraphResponse():\n      dot_graph(\"\")\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      uint32_t length_dot_graph = strlen(this->dot_graph);\n      varToArr(outbuffer + offset, length_dot_graph);\n      offset += 4;\n      memcpy(outbuffer + offset, this->dot_graph, length_dot_graph);\n      offset += length_dot_graph;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      uint32_t length_dot_graph;\n      arrToVar(length_dot_graph, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_dot_graph; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_dot_graph-1]=0;\n      this->dot_graph = (char *)(inbuffer + offset-1);\n      offset += length_dot_graph;\n     return offset;\n    }\n\n    const char * getType(){ return FRAMEGRAPH; };\n    const char * getMD5(){ return \"c4af9ac907e58e906eb0b6e3c58478c0\"; };\n\n  };\n\n  class FrameGraph {\n    public:\n    typedef FrameGraphRequest Request;\n    typedef FrameGraphResponse Response;\n  };\n\n}\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/tf/tf.h",
    "content": "/*\n * Software License Agreement (BSD License)\n *\n * Copyright (c) 2011, Willow Garage, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n *  * Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n *  * Redistributions in binary form must reproduce the above\n *    copyright notice, this list of conditions and the following\n *    disclaimer in the documentation and/or other materials provided\n *    with the distribution.\n *  * Neither the name of Willow Garage, Inc. nor the names of its\n *    contributors may be used to endorse or promote prducts derived\n *    from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef ROS_TF_H_\n#define ROS_TF_H_\n\n#include \"geometry_msgs/TransformStamped.h\"\n\nnamespace tf\n{\n\nstatic inline geometry_msgs::Quaternion createQuaternionFromYaw(double yaw)\n{\n  geometry_msgs::Quaternion q;\n  q.x = 0;\n  q.y = 0;\n  q.z = sin(yaw * 0.5);\n  q.w = cos(yaw * 0.5);\n  return q;\n}\n\n}\n\n#endif\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/tf/tfMessage.h",
    "content": "#ifndef _ROS_tf_tfMessage_h\n#define _ROS_tf_tfMessage_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"geometry_msgs/TransformStamped.h\"\n\nnamespace tf\n{\n\n  class tfMessage : public ros::Msg\n  {\n    public:\n      uint32_t transforms_length;\n      typedef geometry_msgs::TransformStamped _transforms_type;\n      _transforms_type st_transforms;\n      _transforms_type * transforms;\n\n    tfMessage():\n      transforms_length(0), transforms(NULL)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      *(outbuffer + offset + 0) = (this->transforms_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->transforms_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->transforms_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->transforms_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->transforms_length);\n      for( uint32_t i = 0; i < transforms_length; i++){\n      offset += this->transforms[i].serialize(outbuffer + offset);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      uint32_t transforms_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      transforms_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      transforms_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      transforms_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->transforms_length);\n      if(transforms_lengthT > transforms_length)\n        this->transforms = (geometry_msgs::TransformStamped*)realloc(this->transforms, transforms_lengthT * sizeof(geometry_msgs::TransformStamped));\n      transforms_length = transforms_lengthT;\n      for( uint32_t i = 0; i < transforms_length; i++){\n      offset += this->st_transforms.deserialize(inbuffer + offset);\n        memcpy( &(this->transforms[i]), &(this->st_transforms), sizeof(geometry_msgs::TransformStamped));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"tf/tfMessage\"; };\n    const char * getMD5(){ return \"94810edda583a504dfda3829e70d7eec\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/tf/transform_broadcaster.h",
    "content": "/*\n * Software License Agreement (BSD License)\n *\n * Copyright (c) 2011, Willow Garage, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n *  * Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n *  * Redistributions in binary form must reproduce the above\n *    copyright notice, this list of conditions and the following\n *    disclaimer in the documentation and/or other materials provided\n *    with the distribution.\n *  * Neither the name of Willow Garage, Inc. nor the names of its\n *    contributors may be used to endorse or promote prducts derived\n *    from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef ROS_TRANSFORM_BROADCASTER_H_\n#define ROS_TRANSFORM_BROADCASTER_H_\n\n#include \"ros.h\"\n#include \"tfMessage.h\"\n\nnamespace tf\n{\n\nclass TransformBroadcaster\n{\npublic:\n  TransformBroadcaster() : publisher_(\"/tf\", &internal_msg) {}\n\n  void init(ros::NodeHandle &nh)\n  {\n    nh.advertise(publisher_);\n  }\n\n  void sendTransform(geometry_msgs::TransformStamped &transform)\n  {\n    internal_msg.transforms_length = 1;\n    internal_msg.transforms = &transform;\n    publisher_.publish(&internal_msg);\n  }\n\nprivate:\n  tf::tfMessage internal_msg;\n  ros::Publisher publisher_;\n};\n\n}\n\n#endif\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/tf2_msgs/FrameGraph.h",
    "content": "#ifndef _ROS_SERVICE_FrameGraph_h\n#define _ROS_SERVICE_FrameGraph_h\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace tf2_msgs\n{\n\nstatic const char FRAMEGRAPH[] = \"tf2_msgs/FrameGraph\";\n\n  class FrameGraphRequest : public ros::Msg\n  {\n    public:\n\n    FrameGraphRequest()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n     return offset;\n    }\n\n    const char * getType(){ return FRAMEGRAPH; };\n    const char * getMD5(){ return \"d41d8cd98f00b204e9800998ecf8427e\"; };\n\n  };\n\n  class FrameGraphResponse : public ros::Msg\n  {\n    public:\n      typedef const char* _frame_yaml_type;\n      _frame_yaml_type frame_yaml;\n\n    FrameGraphResponse():\n      frame_yaml(\"\")\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      uint32_t length_frame_yaml = strlen(this->frame_yaml);\n      varToArr(outbuffer + offset, length_frame_yaml);\n      offset += 4;\n      memcpy(outbuffer + offset, this->frame_yaml, length_frame_yaml);\n      offset += length_frame_yaml;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      uint32_t length_frame_yaml;\n      arrToVar(length_frame_yaml, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_frame_yaml; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_frame_yaml-1]=0;\n      this->frame_yaml = (char *)(inbuffer + offset-1);\n      offset += length_frame_yaml;\n     return offset;\n    }\n\n    const char * getType(){ return FRAMEGRAPH; };\n    const char * getMD5(){ return \"437ea58e9463815a0d511c7326b686b0\"; };\n\n  };\n\n  class FrameGraph {\n    public:\n    typedef FrameGraphRequest Request;\n    typedef FrameGraphResponse Response;\n  };\n\n}\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/tf2_msgs/LookupTransformAction.h",
    "content": "#ifndef _ROS_tf2_msgs_LookupTransformAction_h\n#define _ROS_tf2_msgs_LookupTransformAction_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"tf2_msgs/LookupTransformActionGoal.h\"\n#include \"tf2_msgs/LookupTransformActionResult.h\"\n#include \"tf2_msgs/LookupTransformActionFeedback.h\"\n\nnamespace tf2_msgs\n{\n\n  class LookupTransformAction : public ros::Msg\n  {\n    public:\n      typedef tf2_msgs::LookupTransformActionGoal _action_goal_type;\n      _action_goal_type action_goal;\n      typedef tf2_msgs::LookupTransformActionResult _action_result_type;\n      _action_result_type action_result;\n      typedef tf2_msgs::LookupTransformActionFeedback _action_feedback_type;\n      _action_feedback_type action_feedback;\n\n    LookupTransformAction():\n      action_goal(),\n      action_result(),\n      action_feedback()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->action_goal.serialize(outbuffer + offset);\n      offset += this->action_result.serialize(outbuffer + offset);\n      offset += this->action_feedback.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->action_goal.deserialize(inbuffer + offset);\n      offset += this->action_result.deserialize(inbuffer + offset);\n      offset += this->action_feedback.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return \"tf2_msgs/LookupTransformAction\"; };\n    const char * getMD5(){ return \"7ee01ba91a56c2245c610992dbaa3c37\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/tf2_msgs/LookupTransformActionFeedback.h",
    "content": "#ifndef _ROS_tf2_msgs_LookupTransformActionFeedback_h\n#define _ROS_tf2_msgs_LookupTransformActionFeedback_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n#include \"actionlib_msgs/GoalStatus.h\"\n#include \"tf2_msgs/LookupTransformFeedback.h\"\n\nnamespace tf2_msgs\n{\n\n  class LookupTransformActionFeedback : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef actionlib_msgs::GoalStatus _status_type;\n      _status_type status;\n      typedef tf2_msgs::LookupTransformFeedback _feedback_type;\n      _feedback_type feedback;\n\n    LookupTransformActionFeedback():\n      header(),\n      status(),\n      feedback()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      offset += this->status.serialize(outbuffer + offset);\n      offset += this->feedback.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      offset += this->status.deserialize(inbuffer + offset);\n      offset += this->feedback.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return \"tf2_msgs/LookupTransformActionFeedback\"; };\n    const char * getMD5(){ return \"aae20e09065c3809e8a8e87c4c8953fd\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/tf2_msgs/LookupTransformActionGoal.h",
    "content": "#ifndef _ROS_tf2_msgs_LookupTransformActionGoal_h\n#define _ROS_tf2_msgs_LookupTransformActionGoal_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n#include \"actionlib_msgs/GoalID.h\"\n#include \"tf2_msgs/LookupTransformGoal.h\"\n\nnamespace tf2_msgs\n{\n\n  class LookupTransformActionGoal : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef actionlib_msgs::GoalID _goal_id_type;\n      _goal_id_type goal_id;\n      typedef tf2_msgs::LookupTransformGoal _goal_type;\n      _goal_type goal;\n\n    LookupTransformActionGoal():\n      header(),\n      goal_id(),\n      goal()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      offset += this->goal_id.serialize(outbuffer + offset);\n      offset += this->goal.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      offset += this->goal_id.deserialize(inbuffer + offset);\n      offset += this->goal.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return \"tf2_msgs/LookupTransformActionGoal\"; };\n    const char * getMD5(){ return \"f2e7bcdb75c847978d0351a13e699da5\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/tf2_msgs/LookupTransformActionResult.h",
    "content": "#ifndef _ROS_tf2_msgs_LookupTransformActionResult_h\n#define _ROS_tf2_msgs_LookupTransformActionResult_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n#include \"actionlib_msgs/GoalStatus.h\"\n#include \"tf2_msgs/LookupTransformResult.h\"\n\nnamespace tf2_msgs\n{\n\n  class LookupTransformActionResult : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef actionlib_msgs::GoalStatus _status_type;\n      _status_type status;\n      typedef tf2_msgs::LookupTransformResult _result_type;\n      _result_type result;\n\n    LookupTransformActionResult():\n      header(),\n      status(),\n      result()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      offset += this->status.serialize(outbuffer + offset);\n      offset += this->result.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      offset += this->status.deserialize(inbuffer + offset);\n      offset += this->result.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return \"tf2_msgs/LookupTransformActionResult\"; };\n    const char * getMD5(){ return \"ac26ce75a41384fa8bb4dc10f491ab90\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/tf2_msgs/LookupTransformFeedback.h",
    "content": "#ifndef _ROS_tf2_msgs_LookupTransformFeedback_h\n#define _ROS_tf2_msgs_LookupTransformFeedback_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace tf2_msgs\n{\n\n  class LookupTransformFeedback : public ros::Msg\n  {\n    public:\n\n    LookupTransformFeedback()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n     return offset;\n    }\n\n    const char * getType(){ return \"tf2_msgs/LookupTransformFeedback\"; };\n    const char * getMD5(){ return \"d41d8cd98f00b204e9800998ecf8427e\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/tf2_msgs/LookupTransformGoal.h",
    "content": "#ifndef _ROS_tf2_msgs_LookupTransformGoal_h\n#define _ROS_tf2_msgs_LookupTransformGoal_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"ros/time.h\"\n#include \"ros/duration.h\"\n\nnamespace tf2_msgs\n{\n\n  class LookupTransformGoal : public ros::Msg\n  {\n    public:\n      typedef const char* _target_frame_type;\n      _target_frame_type target_frame;\n      typedef const char* _source_frame_type;\n      _source_frame_type source_frame;\n      typedef ros::Time _source_time_type;\n      _source_time_type source_time;\n      typedef ros::Duration _timeout_type;\n      _timeout_type timeout;\n      typedef ros::Time _target_time_type;\n      _target_time_type target_time;\n      typedef const char* _fixed_frame_type;\n      _fixed_frame_type fixed_frame;\n      typedef bool _advanced_type;\n      _advanced_type advanced;\n\n    LookupTransformGoal():\n      target_frame(\"\"),\n      source_frame(\"\"),\n      source_time(),\n      timeout(),\n      target_time(),\n      fixed_frame(\"\"),\n      advanced(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      uint32_t length_target_frame = strlen(this->target_frame);\n      varToArr(outbuffer + offset, length_target_frame);\n      offset += 4;\n      memcpy(outbuffer + offset, this->target_frame, length_target_frame);\n      offset += length_target_frame;\n      uint32_t length_source_frame = strlen(this->source_frame);\n      varToArr(outbuffer + offset, length_source_frame);\n      offset += 4;\n      memcpy(outbuffer + offset, this->source_frame, length_source_frame);\n      offset += length_source_frame;\n      *(outbuffer + offset + 0) = (this->source_time.sec >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->source_time.sec >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->source_time.sec >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->source_time.sec >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->source_time.sec);\n      *(outbuffer + offset + 0) = (this->source_time.nsec >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->source_time.nsec >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->source_time.nsec >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->source_time.nsec >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->source_time.nsec);\n      *(outbuffer + offset + 0) = (this->timeout.sec >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->timeout.sec >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->timeout.sec >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->timeout.sec >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->timeout.sec);\n      *(outbuffer + offset + 0) = (this->timeout.nsec >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->timeout.nsec >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->timeout.nsec >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->timeout.nsec >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->timeout.nsec);\n      *(outbuffer + offset + 0) = (this->target_time.sec >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->target_time.sec >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->target_time.sec >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->target_time.sec >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->target_time.sec);\n      *(outbuffer + offset + 0) = (this->target_time.nsec >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->target_time.nsec >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->target_time.nsec >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->target_time.nsec >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->target_time.nsec);\n      uint32_t length_fixed_frame = strlen(this->fixed_frame);\n      varToArr(outbuffer + offset, length_fixed_frame);\n      offset += 4;\n      memcpy(outbuffer + offset, this->fixed_frame, length_fixed_frame);\n      offset += length_fixed_frame;\n      union {\n        bool real;\n        uint8_t base;\n      } u_advanced;\n      u_advanced.real = this->advanced;\n      *(outbuffer + offset + 0) = (u_advanced.base >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->advanced);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      uint32_t length_target_frame;\n      arrToVar(length_target_frame, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_target_frame; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_target_frame-1]=0;\n      this->target_frame = (char *)(inbuffer + offset-1);\n      offset += length_target_frame;\n      uint32_t length_source_frame;\n      arrToVar(length_source_frame, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_source_frame; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_source_frame-1]=0;\n      this->source_frame = (char *)(inbuffer + offset-1);\n      offset += length_source_frame;\n      this->source_time.sec =  ((uint32_t) (*(inbuffer + offset)));\n      this->source_time.sec |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->source_time.sec |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->source_time.sec |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->source_time.sec);\n      this->source_time.nsec =  ((uint32_t) (*(inbuffer + offset)));\n      this->source_time.nsec |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->source_time.nsec |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->source_time.nsec |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->source_time.nsec);\n      this->timeout.sec =  ((uint32_t) (*(inbuffer + offset)));\n      this->timeout.sec |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->timeout.sec |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->timeout.sec |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->timeout.sec);\n      this->timeout.nsec =  ((uint32_t) (*(inbuffer + offset)));\n      this->timeout.nsec |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->timeout.nsec |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->timeout.nsec |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->timeout.nsec);\n      this->target_time.sec =  ((uint32_t) (*(inbuffer + offset)));\n      this->target_time.sec |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->target_time.sec |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->target_time.sec |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->target_time.sec);\n      this->target_time.nsec =  ((uint32_t) (*(inbuffer + offset)));\n      this->target_time.nsec |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->target_time.nsec |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->target_time.nsec |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->target_time.nsec);\n      uint32_t length_fixed_frame;\n      arrToVar(length_fixed_frame, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_fixed_frame; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_fixed_frame-1]=0;\n      this->fixed_frame = (char *)(inbuffer + offset-1);\n      offset += length_fixed_frame;\n      union {\n        bool real;\n        uint8_t base;\n      } u_advanced;\n      u_advanced.base = 0;\n      u_advanced.base |= ((uint8_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      this->advanced = u_advanced.real;\n      offset += sizeof(this->advanced);\n     return offset;\n    }\n\n    const char * getType(){ return \"tf2_msgs/LookupTransformGoal\"; };\n    const char * getMD5(){ return \"35e3720468131d675a18bb6f3e5f22f8\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/tf2_msgs/LookupTransformResult.h",
    "content": "#ifndef _ROS_tf2_msgs_LookupTransformResult_h\n#define _ROS_tf2_msgs_LookupTransformResult_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"geometry_msgs/TransformStamped.h\"\n#include \"tf2_msgs/TF2Error.h\"\n\nnamespace tf2_msgs\n{\n\n  class LookupTransformResult : public ros::Msg\n  {\n    public:\n      typedef geometry_msgs::TransformStamped _transform_type;\n      _transform_type transform;\n      typedef tf2_msgs::TF2Error _error_type;\n      _error_type error;\n\n    LookupTransformResult():\n      transform(),\n      error()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->transform.serialize(outbuffer + offset);\n      offset += this->error.serialize(outbuffer + offset);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->transform.deserialize(inbuffer + offset);\n      offset += this->error.deserialize(inbuffer + offset);\n     return offset;\n    }\n\n    const char * getType(){ return \"tf2_msgs/LookupTransformResult\"; };\n    const char * getMD5(){ return \"3fe5db6a19ca9cfb675418c5ad875c36\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/tf2_msgs/TF2Error.h",
    "content": "#ifndef _ROS_tf2_msgs_TF2Error_h\n#define _ROS_tf2_msgs_TF2Error_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace tf2_msgs\n{\n\n  class TF2Error : public ros::Msg\n  {\n    public:\n      typedef uint8_t _error_type;\n      _error_type error;\n      typedef const char* _error_string_type;\n      _error_string_type error_string;\n      enum { NO_ERROR =  0 };\n      enum { LOOKUP_ERROR =  1 };\n      enum { CONNECTIVITY_ERROR =  2 };\n      enum { EXTRAPOLATION_ERROR =  3 };\n      enum { INVALID_ARGUMENT_ERROR =  4 };\n      enum { TIMEOUT_ERROR =  5 };\n      enum { TRANSFORM_ERROR =  6 };\n\n    TF2Error():\n      error(0),\n      error_string(\"\")\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      *(outbuffer + offset + 0) = (this->error >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->error);\n      uint32_t length_error_string = strlen(this->error_string);\n      varToArr(outbuffer + offset, length_error_string);\n      offset += 4;\n      memcpy(outbuffer + offset, this->error_string, length_error_string);\n      offset += length_error_string;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      this->error =  ((uint8_t) (*(inbuffer + offset)));\n      offset += sizeof(this->error);\n      uint32_t length_error_string;\n      arrToVar(length_error_string, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_error_string; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_error_string-1]=0;\n      this->error_string = (char *)(inbuffer + offset-1);\n      offset += length_error_string;\n     return offset;\n    }\n\n    const char * getType(){ return \"tf2_msgs/TF2Error\"; };\n    const char * getMD5(){ return \"bc6848fd6fd750c92e38575618a4917d\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/tf2_msgs/TFMessage.h",
    "content": "#ifndef _ROS_tf2_msgs_TFMessage_h\n#define _ROS_tf2_msgs_TFMessage_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"geometry_msgs/TransformStamped.h\"\n\nnamespace tf2_msgs\n{\n\n  class TFMessage : public ros::Msg\n  {\n    public:\n      uint32_t transforms_length;\n      typedef geometry_msgs::TransformStamped _transforms_type;\n      _transforms_type st_transforms;\n      _transforms_type * transforms;\n\n    TFMessage():\n      transforms_length(0), transforms(NULL)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      *(outbuffer + offset + 0) = (this->transforms_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->transforms_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->transforms_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->transforms_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->transforms_length);\n      for( uint32_t i = 0; i < transforms_length; i++){\n      offset += this->transforms[i].serialize(outbuffer + offset);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      uint32_t transforms_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      transforms_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      transforms_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      transforms_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->transforms_length);\n      if(transforms_lengthT > transforms_length)\n        this->transforms = (geometry_msgs::TransformStamped*)realloc(this->transforms, transforms_lengthT * sizeof(geometry_msgs::TransformStamped));\n      transforms_length = transforms_lengthT;\n      for( uint32_t i = 0; i < transforms_length; i++){\n      offset += this->st_transforms.deserialize(inbuffer + offset);\n        memcpy( &(this->transforms[i]), &(this->st_transforms), sizeof(geometry_msgs::TransformStamped));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"tf2_msgs/TFMessage\"; };\n    const char * getMD5(){ return \"94810edda583a504dfda3829e70d7eec\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/time.cpp",
    "content": "/*\n * Software License Agreement (BSD License)\n *\n * Copyright (c) 2011, Willow Garage, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n *  * Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n *  * Redistributions in binary form must reproduce the above\n *    copyright notice, this list of conditions and the following\n *    disclaimer in the documentation and/or other materials provided\n *    with the distribution.\n *  * Neither the name of Willow Garage, Inc. nor the names of its\n *    contributors may be used to endorse or promote prducts derived\n *    from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \"ros/time.h\"\n\nnamespace ros\n{\n  void normalizeSecNSec(uint32_t& sec, uint32_t& nsec){\n    uint32_t nsec_part= nsec % 1000000000UL;\n    uint32_t sec_part = nsec / 1000000000UL;\n    sec += sec_part;\n    nsec = nsec_part;\n  }\n\n  Time& Time::fromNSec(int32_t t)\n  {\n    sec = t / 1000000000;\n    nsec = t % 1000000000;\n    normalizeSecNSec(sec, nsec);\n    return *this;\n  }\n\n  Time& Time::operator +=(const Duration &rhs)\n  {\n    sec += rhs.sec;\n    nsec += rhs.nsec;\n    normalizeSecNSec(sec, nsec);\n    return *this;\n  }\n\n  Time& Time::operator -=(const Duration &rhs){\n    sec += -rhs.sec;\n    nsec += -rhs.nsec;\n    normalizeSecNSec(sec, nsec);\n    return *this;\n  }\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/trajectory_msgs/JointTrajectory.h",
    "content": "#ifndef _ROS_trajectory_msgs_JointTrajectory_h\n#define _ROS_trajectory_msgs_JointTrajectory_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n#include \"trajectory_msgs/JointTrajectoryPoint.h\"\n\nnamespace trajectory_msgs\n{\n\n  class JointTrajectory : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      uint32_t joint_names_length;\n      typedef char* _joint_names_type;\n      _joint_names_type st_joint_names;\n      _joint_names_type * joint_names;\n      uint32_t points_length;\n      typedef trajectory_msgs::JointTrajectoryPoint _points_type;\n      _points_type st_points;\n      _points_type * points;\n\n    JointTrajectory():\n      header(),\n      joint_names_length(0), joint_names(NULL),\n      points_length(0), points(NULL)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      *(outbuffer + offset + 0) = (this->joint_names_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->joint_names_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->joint_names_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->joint_names_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->joint_names_length);\n      for( uint32_t i = 0; i < joint_names_length; i++){\n      uint32_t length_joint_namesi = strlen(this->joint_names[i]);\n      varToArr(outbuffer + offset, length_joint_namesi);\n      offset += 4;\n      memcpy(outbuffer + offset, this->joint_names[i], length_joint_namesi);\n      offset += length_joint_namesi;\n      }\n      *(outbuffer + offset + 0) = (this->points_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->points_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->points_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->points_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->points_length);\n      for( uint32_t i = 0; i < points_length; i++){\n      offset += this->points[i].serialize(outbuffer + offset);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      uint32_t joint_names_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      joint_names_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      joint_names_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      joint_names_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->joint_names_length);\n      if(joint_names_lengthT > joint_names_length)\n        this->joint_names = (char**)realloc(this->joint_names, joint_names_lengthT * sizeof(char*));\n      joint_names_length = joint_names_lengthT;\n      for( uint32_t i = 0; i < joint_names_length; i++){\n      uint32_t length_st_joint_names;\n      arrToVar(length_st_joint_names, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_st_joint_names; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_st_joint_names-1]=0;\n      this->st_joint_names = (char *)(inbuffer + offset-1);\n      offset += length_st_joint_names;\n        memcpy( &(this->joint_names[i]), &(this->st_joint_names), sizeof(char*));\n      }\n      uint32_t points_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      points_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      points_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      points_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->points_length);\n      if(points_lengthT > points_length)\n        this->points = (trajectory_msgs::JointTrajectoryPoint*)realloc(this->points, points_lengthT * sizeof(trajectory_msgs::JointTrajectoryPoint));\n      points_length = points_lengthT;\n      for( uint32_t i = 0; i < points_length; i++){\n      offset += this->st_points.deserialize(inbuffer + offset);\n        memcpy( &(this->points[i]), &(this->st_points), sizeof(trajectory_msgs::JointTrajectoryPoint));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"trajectory_msgs/JointTrajectory\"; };\n    const char * getMD5(){ return \"65b4f94a94d1ed67169da35a02f33d3f\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/trajectory_msgs/JointTrajectoryPoint.h",
    "content": "#ifndef _ROS_trajectory_msgs_JointTrajectoryPoint_h\n#define _ROS_trajectory_msgs_JointTrajectoryPoint_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"ros/duration.h\"\n\nnamespace trajectory_msgs\n{\n\n  class JointTrajectoryPoint : public ros::Msg\n  {\n    public:\n      uint32_t positions_length;\n      typedef float _positions_type;\n      _positions_type st_positions;\n      _positions_type * positions;\n      uint32_t velocities_length;\n      typedef float _velocities_type;\n      _velocities_type st_velocities;\n      _velocities_type * velocities;\n      uint32_t accelerations_length;\n      typedef float _accelerations_type;\n      _accelerations_type st_accelerations;\n      _accelerations_type * accelerations;\n      uint32_t effort_length;\n      typedef float _effort_type;\n      _effort_type st_effort;\n      _effort_type * effort;\n      typedef ros::Duration _time_from_start_type;\n      _time_from_start_type time_from_start;\n\n    JointTrajectoryPoint():\n      positions_length(0), positions(NULL),\n      velocities_length(0), velocities(NULL),\n      accelerations_length(0), accelerations(NULL),\n      effort_length(0), effort(NULL),\n      time_from_start()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      *(outbuffer + offset + 0) = (this->positions_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->positions_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->positions_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->positions_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->positions_length);\n      for( uint32_t i = 0; i < positions_length; i++){\n      offset += serializeAvrFloat64(outbuffer + offset, this->positions[i]);\n      }\n      *(outbuffer + offset + 0) = (this->velocities_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->velocities_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->velocities_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->velocities_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->velocities_length);\n      for( uint32_t i = 0; i < velocities_length; i++){\n      offset += serializeAvrFloat64(outbuffer + offset, this->velocities[i]);\n      }\n      *(outbuffer + offset + 0) = (this->accelerations_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->accelerations_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->accelerations_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->accelerations_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->accelerations_length);\n      for( uint32_t i = 0; i < accelerations_length; i++){\n      offset += serializeAvrFloat64(outbuffer + offset, this->accelerations[i]);\n      }\n      *(outbuffer + offset + 0) = (this->effort_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->effort_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->effort_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->effort_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->effort_length);\n      for( uint32_t i = 0; i < effort_length; i++){\n      offset += serializeAvrFloat64(outbuffer + offset, this->effort[i]);\n      }\n      *(outbuffer + offset + 0) = (this->time_from_start.sec >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->time_from_start.sec >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->time_from_start.sec >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->time_from_start.sec >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->time_from_start.sec);\n      *(outbuffer + offset + 0) = (this->time_from_start.nsec >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->time_from_start.nsec >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->time_from_start.nsec >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->time_from_start.nsec >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->time_from_start.nsec);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      uint32_t positions_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      positions_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      positions_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      positions_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->positions_length);\n      if(positions_lengthT > positions_length)\n        this->positions = (float*)realloc(this->positions, positions_lengthT * sizeof(float));\n      positions_length = positions_lengthT;\n      for( uint32_t i = 0; i < positions_length; i++){\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->st_positions));\n        memcpy( &(this->positions[i]), &(this->st_positions), sizeof(float));\n      }\n      uint32_t velocities_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      velocities_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      velocities_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      velocities_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->velocities_length);\n      if(velocities_lengthT > velocities_length)\n        this->velocities = (float*)realloc(this->velocities, velocities_lengthT * sizeof(float));\n      velocities_length = velocities_lengthT;\n      for( uint32_t i = 0; i < velocities_length; i++){\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->st_velocities));\n        memcpy( &(this->velocities[i]), &(this->st_velocities), sizeof(float));\n      }\n      uint32_t accelerations_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      accelerations_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      accelerations_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      accelerations_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->accelerations_length);\n      if(accelerations_lengthT > accelerations_length)\n        this->accelerations = (float*)realloc(this->accelerations, accelerations_lengthT * sizeof(float));\n      accelerations_length = accelerations_lengthT;\n      for( uint32_t i = 0; i < accelerations_length; i++){\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->st_accelerations));\n        memcpy( &(this->accelerations[i]), &(this->st_accelerations), sizeof(float));\n      }\n      uint32_t effort_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      effort_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      effort_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      effort_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->effort_length);\n      if(effort_lengthT > effort_length)\n        this->effort = (float*)realloc(this->effort, effort_lengthT * sizeof(float));\n      effort_length = effort_lengthT;\n      for( uint32_t i = 0; i < effort_length; i++){\n      offset += deserializeAvrFloat64(inbuffer + offset, &(this->st_effort));\n        memcpy( &(this->effort[i]), &(this->st_effort), sizeof(float));\n      }\n      this->time_from_start.sec =  ((uint32_t) (*(inbuffer + offset)));\n      this->time_from_start.sec |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->time_from_start.sec |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->time_from_start.sec |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->time_from_start.sec);\n      this->time_from_start.nsec =  ((uint32_t) (*(inbuffer + offset)));\n      this->time_from_start.nsec |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->time_from_start.nsec |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->time_from_start.nsec |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->time_from_start.nsec);\n     return offset;\n    }\n\n    const char * getType(){ return \"trajectory_msgs/JointTrajectoryPoint\"; };\n    const char * getMD5(){ return \"f3cd1e1c4d320c79d6985c904ae5dcd3\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/trajectory_msgs/MultiDOFJointTrajectory.h",
    "content": "#ifndef _ROS_trajectory_msgs_MultiDOFJointTrajectory_h\n#define _ROS_trajectory_msgs_MultiDOFJointTrajectory_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n#include \"trajectory_msgs/MultiDOFJointTrajectoryPoint.h\"\n\nnamespace trajectory_msgs\n{\n\n  class MultiDOFJointTrajectory : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      uint32_t joint_names_length;\n      typedef char* _joint_names_type;\n      _joint_names_type st_joint_names;\n      _joint_names_type * joint_names;\n      uint32_t points_length;\n      typedef trajectory_msgs::MultiDOFJointTrajectoryPoint _points_type;\n      _points_type st_points;\n      _points_type * points;\n\n    MultiDOFJointTrajectory():\n      header(),\n      joint_names_length(0), joint_names(NULL),\n      points_length(0), points(NULL)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      *(outbuffer + offset + 0) = (this->joint_names_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->joint_names_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->joint_names_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->joint_names_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->joint_names_length);\n      for( uint32_t i = 0; i < joint_names_length; i++){\n      uint32_t length_joint_namesi = strlen(this->joint_names[i]);\n      varToArr(outbuffer + offset, length_joint_namesi);\n      offset += 4;\n      memcpy(outbuffer + offset, this->joint_names[i], length_joint_namesi);\n      offset += length_joint_namesi;\n      }\n      *(outbuffer + offset + 0) = (this->points_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->points_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->points_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->points_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->points_length);\n      for( uint32_t i = 0; i < points_length; i++){\n      offset += this->points[i].serialize(outbuffer + offset);\n      }\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      uint32_t joint_names_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      joint_names_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      joint_names_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      joint_names_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->joint_names_length);\n      if(joint_names_lengthT > joint_names_length)\n        this->joint_names = (char**)realloc(this->joint_names, joint_names_lengthT * sizeof(char*));\n      joint_names_length = joint_names_lengthT;\n      for( uint32_t i = 0; i < joint_names_length; i++){\n      uint32_t length_st_joint_names;\n      arrToVar(length_st_joint_names, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_st_joint_names; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_st_joint_names-1]=0;\n      this->st_joint_names = (char *)(inbuffer + offset-1);\n      offset += length_st_joint_names;\n        memcpy( &(this->joint_names[i]), &(this->st_joint_names), sizeof(char*));\n      }\n      uint32_t points_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      points_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      points_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      points_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->points_length);\n      if(points_lengthT > points_length)\n        this->points = (trajectory_msgs::MultiDOFJointTrajectoryPoint*)realloc(this->points, points_lengthT * sizeof(trajectory_msgs::MultiDOFJointTrajectoryPoint));\n      points_length = points_lengthT;\n      for( uint32_t i = 0; i < points_length; i++){\n      offset += this->st_points.deserialize(inbuffer + offset);\n        memcpy( &(this->points[i]), &(this->st_points), sizeof(trajectory_msgs::MultiDOFJointTrajectoryPoint));\n      }\n     return offset;\n    }\n\n    const char * getType(){ return \"trajectory_msgs/MultiDOFJointTrajectory\"; };\n    const char * getMD5(){ return \"ef145a45a5f47b77b7f5cdde4b16c942\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/trajectory_msgs/MultiDOFJointTrajectoryPoint.h",
    "content": "#ifndef _ROS_trajectory_msgs_MultiDOFJointTrajectoryPoint_h\n#define _ROS_trajectory_msgs_MultiDOFJointTrajectoryPoint_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"geometry_msgs/Transform.h\"\n#include \"geometry_msgs/Twist.h\"\n#include \"ros/duration.h\"\n\nnamespace trajectory_msgs\n{\n\n  class MultiDOFJointTrajectoryPoint : public ros::Msg\n  {\n    public:\n      uint32_t transforms_length;\n      typedef geometry_msgs::Transform _transforms_type;\n      _transforms_type st_transforms;\n      _transforms_type * transforms;\n      uint32_t velocities_length;\n      typedef geometry_msgs::Twist _velocities_type;\n      _velocities_type st_velocities;\n      _velocities_type * velocities;\n      uint32_t accelerations_length;\n      typedef geometry_msgs::Twist _accelerations_type;\n      _accelerations_type st_accelerations;\n      _accelerations_type * accelerations;\n      typedef ros::Duration _time_from_start_type;\n      _time_from_start_type time_from_start;\n\n    MultiDOFJointTrajectoryPoint():\n      transforms_length(0), transforms(NULL),\n      velocities_length(0), velocities(NULL),\n      accelerations_length(0), accelerations(NULL),\n      time_from_start()\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      *(outbuffer + offset + 0) = (this->transforms_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->transforms_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->transforms_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->transforms_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->transforms_length);\n      for( uint32_t i = 0; i < transforms_length; i++){\n      offset += this->transforms[i].serialize(outbuffer + offset);\n      }\n      *(outbuffer + offset + 0) = (this->velocities_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->velocities_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->velocities_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->velocities_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->velocities_length);\n      for( uint32_t i = 0; i < velocities_length; i++){\n      offset += this->velocities[i].serialize(outbuffer + offset);\n      }\n      *(outbuffer + offset + 0) = (this->accelerations_length >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->accelerations_length >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->accelerations_length >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->accelerations_length >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->accelerations_length);\n      for( uint32_t i = 0; i < accelerations_length; i++){\n      offset += this->accelerations[i].serialize(outbuffer + offset);\n      }\n      *(outbuffer + offset + 0) = (this->time_from_start.sec >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->time_from_start.sec >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->time_from_start.sec >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->time_from_start.sec >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->time_from_start.sec);\n      *(outbuffer + offset + 0) = (this->time_from_start.nsec >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (this->time_from_start.nsec >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (this->time_from_start.nsec >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (this->time_from_start.nsec >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->time_from_start.nsec);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      uint32_t transforms_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      transforms_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      transforms_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      transforms_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->transforms_length);\n      if(transforms_lengthT > transforms_length)\n        this->transforms = (geometry_msgs::Transform*)realloc(this->transforms, transforms_lengthT * sizeof(geometry_msgs::Transform));\n      transforms_length = transforms_lengthT;\n      for( uint32_t i = 0; i < transforms_length; i++){\n      offset += this->st_transforms.deserialize(inbuffer + offset);\n        memcpy( &(this->transforms[i]), &(this->st_transforms), sizeof(geometry_msgs::Transform));\n      }\n      uint32_t velocities_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      velocities_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      velocities_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      velocities_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->velocities_length);\n      if(velocities_lengthT > velocities_length)\n        this->velocities = (geometry_msgs::Twist*)realloc(this->velocities, velocities_lengthT * sizeof(geometry_msgs::Twist));\n      velocities_length = velocities_lengthT;\n      for( uint32_t i = 0; i < velocities_length; i++){\n      offset += this->st_velocities.deserialize(inbuffer + offset);\n        memcpy( &(this->velocities[i]), &(this->st_velocities), sizeof(geometry_msgs::Twist));\n      }\n      uint32_t accelerations_lengthT = ((uint32_t) (*(inbuffer + offset))); \n      accelerations_lengthT |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1); \n      accelerations_lengthT |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2); \n      accelerations_lengthT |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3); \n      offset += sizeof(this->accelerations_length);\n      if(accelerations_lengthT > accelerations_length)\n        this->accelerations = (geometry_msgs::Twist*)realloc(this->accelerations, accelerations_lengthT * sizeof(geometry_msgs::Twist));\n      accelerations_length = accelerations_lengthT;\n      for( uint32_t i = 0; i < accelerations_length; i++){\n      offset += this->st_accelerations.deserialize(inbuffer + offset);\n        memcpy( &(this->accelerations[i]), &(this->st_accelerations), sizeof(geometry_msgs::Twist));\n      }\n      this->time_from_start.sec =  ((uint32_t) (*(inbuffer + offset)));\n      this->time_from_start.sec |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->time_from_start.sec |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->time_from_start.sec |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->time_from_start.sec);\n      this->time_from_start.nsec =  ((uint32_t) (*(inbuffer + offset)));\n      this->time_from_start.nsec |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      this->time_from_start.nsec |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      this->time_from_start.nsec |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      offset += sizeof(this->time_from_start.nsec);\n     return offset;\n    }\n\n    const char * getType(){ return \"trajectory_msgs/MultiDOFJointTrajectoryPoint\"; };\n    const char * getMD5(){ return \"3ebe08d1abd5b65862d50e09430db776\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/turtlebot3_msgs/SensorState.h",
    "content": "#ifndef _ROS_turtlebot3_msgs_SensorState_h\n#define _ROS_turtlebot3_msgs_SensorState_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n#include \"std_msgs/Header.h\"\n\nnamespace turtlebot3_msgs\n{\n\n  class SensorState : public ros::Msg\n  {\n    public:\n      typedef std_msgs::Header _header_type;\n      _header_type header;\n      typedef uint8_t _bumper_type;\n      _bumper_type bumper;\n      typedef float _cliff_type;\n      _cliff_type cliff;\n      typedef float _sonar_type;\n      _sonar_type sonar;\n      typedef float _illumination_type;\n      _illumination_type illumination;\n      typedef uint8_t _led_type;\n      _led_type led;\n      typedef uint8_t _button_type;\n      _button_type button;\n      typedef bool _torque_type;\n      _torque_type torque;\n      typedef int32_t _left_encoder_type;\n      _left_encoder_type left_encoder;\n      typedef int32_t _right_encoder_type;\n      _right_encoder_type right_encoder;\n      typedef float _battery_type;\n      _battery_type battery;\n      enum { BUMPER_FORWARD =  1 };\n      enum { BUMPER_BACKWARD =  2 };\n      enum { CLIFF =  1 };\n      enum { SONAR =  1 };\n      enum { ILLUMINATION =  1 };\n      enum { BUTTON0 =  1 };\n      enum { BUTTON1 =  2 };\n      enum { ERROR_LEFT_MOTOR =  1 };\n      enum { ERROR_RIGHT_MOTOR =  2 };\n      enum { TORQUE_ON =  1 };\n      enum { TORQUE_OFF =  2 };\n\n    SensorState():\n      header(),\n      bumper(0),\n      cliff(0),\n      sonar(0),\n      illumination(0),\n      led(0),\n      button(0),\n      torque(0),\n      left_encoder(0),\n      right_encoder(0),\n      battery(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      offset += this->header.serialize(outbuffer + offset);\n      *(outbuffer + offset + 0) = (this->bumper >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->bumper);\n      union {\n        float real;\n        uint32_t base;\n      } u_cliff;\n      u_cliff.real = this->cliff;\n      *(outbuffer + offset + 0) = (u_cliff.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_cliff.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_cliff.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_cliff.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->cliff);\n      union {\n        float real;\n        uint32_t base;\n      } u_sonar;\n      u_sonar.real = this->sonar;\n      *(outbuffer + offset + 0) = (u_sonar.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_sonar.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_sonar.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_sonar.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->sonar);\n      union {\n        float real;\n        uint32_t base;\n      } u_illumination;\n      u_illumination.real = this->illumination;\n      *(outbuffer + offset + 0) = (u_illumination.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_illumination.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_illumination.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_illumination.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->illumination);\n      *(outbuffer + offset + 0) = (this->led >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->led);\n      *(outbuffer + offset + 0) = (this->button >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->button);\n      union {\n        bool real;\n        uint8_t base;\n      } u_torque;\n      u_torque.real = this->torque;\n      *(outbuffer + offset + 0) = (u_torque.base >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->torque);\n      union {\n        int32_t real;\n        uint32_t base;\n      } u_left_encoder;\n      u_left_encoder.real = this->left_encoder;\n      *(outbuffer + offset + 0) = (u_left_encoder.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_left_encoder.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_left_encoder.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_left_encoder.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->left_encoder);\n      union {\n        int32_t real;\n        uint32_t base;\n      } u_right_encoder;\n      u_right_encoder.real = this->right_encoder;\n      *(outbuffer + offset + 0) = (u_right_encoder.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_right_encoder.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_right_encoder.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_right_encoder.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->right_encoder);\n      union {\n        float real;\n        uint32_t base;\n      } u_battery;\n      u_battery.real = this->battery;\n      *(outbuffer + offset + 0) = (u_battery.base >> (8 * 0)) & 0xFF;\n      *(outbuffer + offset + 1) = (u_battery.base >> (8 * 1)) & 0xFF;\n      *(outbuffer + offset + 2) = (u_battery.base >> (8 * 2)) & 0xFF;\n      *(outbuffer + offset + 3) = (u_battery.base >> (8 * 3)) & 0xFF;\n      offset += sizeof(this->battery);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      offset += this->header.deserialize(inbuffer + offset);\n      this->bumper =  ((uint8_t) (*(inbuffer + offset)));\n      offset += sizeof(this->bumper);\n      union {\n        float real;\n        uint32_t base;\n      } u_cliff;\n      u_cliff.base = 0;\n      u_cliff.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_cliff.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_cliff.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_cliff.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->cliff = u_cliff.real;\n      offset += sizeof(this->cliff);\n      union {\n        float real;\n        uint32_t base;\n      } u_sonar;\n      u_sonar.base = 0;\n      u_sonar.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_sonar.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_sonar.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_sonar.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->sonar = u_sonar.real;\n      offset += sizeof(this->sonar);\n      union {\n        float real;\n        uint32_t base;\n      } u_illumination;\n      u_illumination.base = 0;\n      u_illumination.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_illumination.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_illumination.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_illumination.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->illumination = u_illumination.real;\n      offset += sizeof(this->illumination);\n      this->led =  ((uint8_t) (*(inbuffer + offset)));\n      offset += sizeof(this->led);\n      this->button =  ((uint8_t) (*(inbuffer + offset)));\n      offset += sizeof(this->button);\n      union {\n        bool real;\n        uint8_t base;\n      } u_torque;\n      u_torque.base = 0;\n      u_torque.base |= ((uint8_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      this->torque = u_torque.real;\n      offset += sizeof(this->torque);\n      union {\n        int32_t real;\n        uint32_t base;\n      } u_left_encoder;\n      u_left_encoder.base = 0;\n      u_left_encoder.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_left_encoder.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_left_encoder.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_left_encoder.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->left_encoder = u_left_encoder.real;\n      offset += sizeof(this->left_encoder);\n      union {\n        int32_t real;\n        uint32_t base;\n      } u_right_encoder;\n      u_right_encoder.base = 0;\n      u_right_encoder.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_right_encoder.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_right_encoder.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_right_encoder.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->right_encoder = u_right_encoder.real;\n      offset += sizeof(this->right_encoder);\n      union {\n        float real;\n        uint32_t base;\n      } u_battery;\n      u_battery.base = 0;\n      u_battery.base |= ((uint32_t) (*(inbuffer + offset + 0))) << (8 * 0);\n      u_battery.base |= ((uint32_t) (*(inbuffer + offset + 1))) << (8 * 1);\n      u_battery.base |= ((uint32_t) (*(inbuffer + offset + 2))) << (8 * 2);\n      u_battery.base |= ((uint32_t) (*(inbuffer + offset + 3))) << (8 * 3);\n      this->battery = u_battery.real;\n      offset += sizeof(this->battery);\n     return offset;\n    }\n\n    const char * getType(){ return \"turtlebot3_msgs/SensorState\"; };\n    const char * getMD5(){ return \"7250c1dc0b61c4190e78f528f599285f\"; };\n\n  };\n\n}\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/turtlebot3_msgs/Sound.h",
    "content": "#ifndef _ROS_turtlebot3_msgs_Sound_h\n#define _ROS_turtlebot3_msgs_Sound_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace turtlebot3_msgs\n{\n\n  class Sound : public ros::Msg\n  {\n    public:\n      typedef uint8_t _value_type;\n      _value_type value;\n      enum { OFF =  0 };\n      enum { ON =  1 };\n      enum { LOW_BATTERY =  2 };\n      enum { ERROR =  3 };\n      enum { BUTTON1 =  4 };\n      enum { BUTTON2 =  5 };\n\n    Sound():\n      value(0)\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      *(outbuffer + offset + 0) = (this->value >> (8 * 0)) & 0xFF;\n      offset += sizeof(this->value);\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      this->value =  ((uint8_t) (*(inbuffer + offset)));\n      offset += sizeof(this->value);\n     return offset;\n    }\n\n    const char * getType(){ return \"turtlebot3_msgs/Sound\"; };\n    const char * getMD5(){ return \"e1f8c7f8a9a61383b5734fbdeca2f99a\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/libraries/turtlebot3_ros_lib/turtlebot3_msgs/VersionInfo.h",
    "content": "#ifndef _ROS_turtlebot3_msgs_VersionInfo_h\n#define _ROS_turtlebot3_msgs_VersionInfo_h\n\n#include <stdint.h>\n#include <string.h>\n#include <stdlib.h>\n#include \"ros/msg.h\"\n\nnamespace turtlebot3_msgs\n{\n\n  class VersionInfo : public ros::Msg\n  {\n    public:\n      typedef const char* _hardware_type;\n      _hardware_type hardware;\n      typedef const char* _firmware_type;\n      _firmware_type firmware;\n      typedef const char* _software_type;\n      _software_type software;\n\n    VersionInfo():\n      hardware(\"\"),\n      firmware(\"\"),\n      software(\"\")\n    {\n    }\n\n    virtual int serialize(unsigned char *outbuffer) const\n    {\n      int offset = 0;\n      uint32_t length_hardware = strlen(this->hardware);\n      varToArr(outbuffer + offset, length_hardware);\n      offset += 4;\n      memcpy(outbuffer + offset, this->hardware, length_hardware);\n      offset += length_hardware;\n      uint32_t length_firmware = strlen(this->firmware);\n      varToArr(outbuffer + offset, length_firmware);\n      offset += 4;\n      memcpy(outbuffer + offset, this->firmware, length_firmware);\n      offset += length_firmware;\n      uint32_t length_software = strlen(this->software);\n      varToArr(outbuffer + offset, length_software);\n      offset += 4;\n      memcpy(outbuffer + offset, this->software, length_software);\n      offset += length_software;\n      return offset;\n    }\n\n    virtual int deserialize(unsigned char *inbuffer)\n    {\n      int offset = 0;\n      uint32_t length_hardware;\n      arrToVar(length_hardware, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_hardware; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_hardware-1]=0;\n      this->hardware = (char *)(inbuffer + offset-1);\n      offset += length_hardware;\n      uint32_t length_firmware;\n      arrToVar(length_firmware, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_firmware; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_firmware-1]=0;\n      this->firmware = (char *)(inbuffer + offset-1);\n      offset += length_firmware;\n      uint32_t length_software;\n      arrToVar(length_software, (inbuffer + offset));\n      offset += 4;\n      for(unsigned int k= offset; k< offset+length_software; ++k){\n          inbuffer[k-1]=inbuffer[k];\n      }\n      inbuffer[offset+length_software-1]=0;\n      this->software = (char *)(inbuffer + offset-1);\n      offset += length_software;\n     return offset;\n    }\n\n    const char * getType(){ return \"turtlebot3_msgs/VersionInfo\"; };\n    const char * getMD5(){ return \"43e0361461af2970a33107409403ef3c\"; };\n\n  };\n\n}\n#endif"
  },
  {
    "path": "arduino/opencr_arduino/opencr/platform.txt",
    "content": "#\r\n#\tMap of STM32 cube MX CMSIS HAL drivers to underlay maple libs\r\n#\r\n#  configured by sheepdoll (Julie S Porter) 2015\r\n#  modified by Baram\r\n# For more info:\r\n# https://github.com/arduino/Arduino/wiki/Arduino-IDE-1.5---3rd-party-Hardware-specification\r\n# http://stm32duino.com/\r\n# http://oroca.org\r\n\r\nname=OpenCR\r\nversion=1.0.0\r\n\r\ncompiler.warning_flags=-w -DDEBUG_LEVEL=DEBUG_NONE\r\ncompiler.warning_flags.none=-w -DDEBUG_LEVEL=DEBUG_NONE\r\ncompiler.warning_flags.default=-DDEBUG_LEVEL=DEBUG_NONE\r\ncompiler.warning_flags.more=-Wall -DDEBUG_LEVEL=DEBUG_FAULT\r\ncompiler.warning_flags.all=-Wall -Wextra -DDEBUG_LEVEL=DEBUG_ALL\r\n\r\n# compiler variables\r\n# ----------------------\r\ncompiler.path={runtime.tools.opencr_gcc.path}/bin/\r\ncompiler.c.cmd=arm-none-eabi-gcc\r\ncompiler.c.flags=-c -g -O2 -std=gnu11 -mfloat-abi=softfp -mfpu=fpv5-sp-d16 {compiler.warning_flags} -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -DBOARD_{build.variant}\r\ncompiler.c.elf.cmd=arm-none-eabi-g++\r\ncompiler.c.elf.flags=-Os -Wl,--gc-sections\r\ncompiler.S.cmd=arm-none-eabi-gcc\r\ncompiler.S.flags=-c -g -x assembler-with-cpp -MMD\r\ncompiler.cpp.cmd=arm-none-eabi-g++\r\ncompiler.cpp.flags=-c -g -O2 -std=gnu++11 -mfloat-abi=softfp -mfpu=fpv5-sp-d16 {compiler.warning_flags} -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -fno-rtti -fno-exceptions -DBOARD_{build.variant}\r\ncompiler.ar.cmd=arm-none-eabi-ar\r\ncompiler.ar.flags=rcs\r\ncompiler.objcopy.cmd=arm-none-eabi-objcopy\r\ncompiler.objcopy.eep.flags=-O ihex -j .eeprom --set-section-flags=.eeprom=alloc,load --no-change-warnings --change-section-lma .eeprom=0\r\ncompiler.elf2hex.flags=-O binary\r\ncompiler.elf2hex.cmd=arm-none-eabi-objcopy\r\ncompiler.ldflags=\r\ncompiler.size.cmd=arm-none-eabi-size\r\ncompiler.define=-DARDUINO=\r\ncompiler.libraries.ldflags=\r\n\r\n\r\nbuild.cpu_flags=\r\nbuild.hs_flag=\r\nbuild.upload_flags=\r\n#build.extra_flags= {build.upload_flags} {build.cpu_flags} {build.hs_flag} {build.common_flags}\r\n\r\n\r\n# These can be overridden in platform.local.txt\r\ncompiler.c.extra_flags=\r\ncompiler.c.elf.extra_flags=\"-L{build.variant.path}/ld\"\r\ncompiler.cpp.extra_flags=\r\ncompiler.S.extra_flags=\r\ncompiler.ar.extra_flags=\r\ncompiler.elf2hex.extra_flags=\r\n\r\n\r\n## Compiler include paths\r\n\r\n\r\n\r\n# sheepdoll a better more generic library include paths\r\ncompiler.libs.c.flags= \"-I{build.variant.path}/{build.inc1}\" \"-I{build.variant.path}/{build.inc2}\" \"-I{build.variant.path}/{build.inc3}\" \"-I{build.variant.path}/{build.inc4}\" \"-I{build.variant.path}/{build.inc5}\" \"-I{build.variant.path}/{build.inc6}\" \"-I{build.variant.path}/{build.inc7}\"\r\n\r\n\r\n# build patterns\r\n# ---------------------\r\n\r\n## Compile c files\r\nrecipe.c.o.pattern=\"{compiler.path}{compiler.c.cmd}\" {compiler.c.flags} -mcpu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.c.extra_flags} {build.extra_flags} {build.cpu_flags} {build.common_flags} {compiler.libs.c.flags} {includes} \"{source_file}\" -o \"{object_file}\"\r\n###\r\n\r\n## Compile c++ files\r\nrecipe.cpp.o.pattern=\"{compiler.path}{compiler.cpp.cmd}\" {compiler.cpp.flags} -mcpu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.cpp.extra_flags} {build.extra_flags} {build.cpu_flags} {build.hs_flag} {build.common_flags} {compiler.libs.c.flags} {includes} \"{source_file}\" -o \"{object_file}\"\r\n#### {compiler.libs.c.flags}  before includes\r\n\r\n## Compile S files\r\nrecipe.S.o.pattern=\"{compiler.path}{compiler.c.cmd}\" {compiler.S.flags} -mcpu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.S.extra_flags} {build.extra_flags} {build.cpu_flags} {build.hs_flag} {build.common_flags} {compiler.libs.c.flags} {includes} \"{source_file}\" -o \"{object_file}\"\r\nrecipe.s.o.pattern=\"{compiler.path}{compiler.c.cmd}\" {compiler.S.flags} -mcpu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.S.extra_flags} {build.extra_flags} {build.cpu_flags} {build.hs_flag} {build.common_flags} {compiler.libs.c.flags} {includes} \"{source_file}\" -o \"{object_file}\"\r\n\r\n\r\n## Create archives\r\nrecipe.ar.pattern=\"{compiler.path}{compiler.ar.cmd}\" {compiler.ar.flags} {compiler.ar.extra_flags} \"{archive_file_path}\" \"{object_file}\"\r\nrecipe.c.combine.pattern=\"{compiler.path}{compiler.c.elf.cmd}\" {compiler.c.elf.flags} -mcpu={build.mcu} \"-T{build.variant.path}/{build.ldscript}\" \"-Wl,-Map,{build.path}/{build.project_name}.map\" {compiler.c.elf.extra_flags} -o \"{build.path}/{build.project_name}.elf\" \"-L{build.path}\" -lm -lgcc -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-unresolved-symbols -Wl,--start-group {object_files} -Wl,--whole-archive \"{build.path}/{archive_file}\" -Wl,--no-whole-archive {compiler.libraries.ldflags} -Wl,--end-group\r\n\r\n## Create eeprom\r\nrecipe.objcopy.eep.pattern=\r\n\r\n## Create hex or binary\r\nrecipe.objcopy.hex.pattern=\"{compiler.path}{compiler.elf2hex.cmd}\" {compiler.elf2hex.flags} {compiler.elf2hex.extra_flags} \"{build.path}/{build.project_name}.elf\" \"{build.path}/{build.project_name}.bin\"\r\n\r\n## Save binary\r\nrecipe.output.tmp_file={build.project_name}.bin\r\nrecipe.output.save_file={build.project_name}.{build.variant}.bin\r\n\r\n\r\n## Compute size\r\n# ---------------------\r\nrecipe.size.pattern=\"{compiler.path}{compiler.size.cmd}\" -A \"{build.path}/{build.project_name}.elf\"\r\nrecipe.size.regex=^(?:\\.text|\\.data|\\.rodata|\\.text.align|\\.ARM.exidx)\\s+([0-9]+).*\r\nrecipe.size.regex.data=^(?:\\.data|\\.bss|\\.noinit)\\s+([0-9]+).*\r\n\r\n\r\n# Uploader tools\r\n# -------------------\r\ntools.opencr_ld.cmd=opencr_ld\r\ntools.opencr_ld.cmd.windows=opencr_ld.exe\r\n#tools.opencr_ld.path={runtime.hardware.path}/tools/win\r\n#tools.opencr_ld.path.macosx={runtime.hardware.path}/tools/macosx\r\n#tools.opencr_ld.path.linux={runtime.hardware.path}/tools/linux\r\ntools.opencr_ld.path={runtime.tools.opencr_tools.path}/win\r\ntools.opencr_ld.path.macosx={runtime.tools.opencr_tools.path}/macosx\r\ntools.opencr_ld.path.linux={runtime.tools.opencr_tools.path}/linux\r\n\r\ntools.opencr_ld.upload.params.verbose=-d\r\ntools.opencr_ld.upload.params.quiet=n\r\ntools.opencr_ld.upload.pattern=\"{path}/{cmd}\" \"{serial.port}\" \"115200\" \"{build.path}/{build.project_name}.bin\" \"1\"\r\n\r\ntools.dfu_util.cmd=dfu-util\r\ntools.dfu_util.cmd.windows=dfu-util.exe\r\ntools.dfu_util.path={runtime.tools.opencr_tools.path}/win/dfu-util\r\ntools.dfu_util.path.macosx={runtime.tools.opencr_tools.path}/macosx/dfu-util\r\ntools.dfu_util.path.linux={runtime.tools.opencr_tools.path}/linux/dfu-util\r\n\r\ntools.dfu_util.erase.params.verbose=-v\r\ntools.dfu_util.erase.params.quiet=-q -q\r\ntools.dfu_util.erase.pattern=\r\n\r\ntools.dfu_util.bootloader.params.verbose=-v -v -v -v\r\ntools.dfu_util.bootloader.params.quiet=-q -q\r\ntools.dfu_util.bootloader.pattern=\"{path}/{cmd}\" -d 0483:df11 -a 0 -s 0x08000000 -D \"{runtime.platform.path}/bootloaders/{bootloader.file}\"\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/programmers.txt",
    "content": "dfu_util.name=DFU_UTIL\ndfu_util.communication=serial\ndfu_util.protocol=dfu_util\ndfu_util.program.protocol=dfu_util\ndfu_util.program.tool=dfu_util\ndfu_util.program.extra_params=-P{serial.port}\n\n\n\n\n\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/bsp/opencr/bsp.c",
    "content": "/*\n *  bsp.c\n *\n *  boart support package\n *\n *  Created on: 2017. 3. 16.\n *      Author: Baram\n */\n #include \"bsp.h\"\n\n #include \"hw.h\"\n\n #include \"usbd_core.h\"\n #include \"usbd_desc.h\"\n #include \"usbd_cdc.h\"\n #include \"usbd_cdc_interface.h\"\n\n\n\n\nUSBD_HandleTypeDef USBD_Device;\n\nextern void stop();\n\n\nvoid bsp_mpu_config(void);\n\n\n\nvoid bsp_init()\n{\n  // STM32Cube HAL Init\n  HAL_Init();\n\n  // Clock Setup\n  // SYSCLK(Hz)    = 216000000\n  // HCLK(Hz)      = 216000000\n  // HSE(Hz)       = 25000000\n  SystemClock_Config();\n\n  SCB_EnableDCache();\n  SCB_EnableICache();\n\n\n  __HAL_RCC_GPIOA_CLK_ENABLE();\n  __HAL_RCC_GPIOB_CLK_ENABLE();\n  __HAL_RCC_GPIOC_CLK_ENABLE();\n  __HAL_RCC_GPIOD_CLK_ENABLE();\n  __HAL_RCC_GPIOE_CLK_ENABLE();\n  __HAL_RCC_GPIOG_CLK_ENABLE();\n  __HAL_RCC_GPIOF_CLK_ENABLE();\n\n\n\n  //HAL_Delay(100);\n\n  /* Init Device Library */\n  USBD_Init(&USBD_Device, &VCP_Desc, 0);\n\n\n  /* Add Supported Class */\n  USBD_RegisterClass(&USBD_Device, USBD_CDC_CLASS);\n\n  /* Add CDC Interface Class */\n  USBD_CDC_RegisterInterface(&USBD_Device, &USBD_CDC_fops);\n\n  /* Start Device Process */\n  USBD_Start(&USBD_Device);\n}\n\n\nvoid bsp_deinit()\n{\n\n  USBD_DeInit(&USBD_Device);\n  HAL_DeInit();\n  __disable_irq();\n\n  SCB_InvalidateDCache();\n  SCB_InvalidateICache();\n  SCB_DisableDCache();\n  SCB_DisableICache();\n\n}\n\n\nvoid bsp_mpu_config(void)\n{\n  MPU_Region_InitTypeDef MPU_InitStruct;\n\n  /* Disable the MPU */\n  HAL_MPU_Disable();\n\n  /* Configure the MPU attributes as WT for SRAM */\n  MPU_InitStruct.Enable = MPU_REGION_ENABLE;\n  MPU_InitStruct.BaseAddress = 0x20010000;\n  MPU_InitStruct.Size = MPU_REGION_SIZE_256KB;\n  MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;\n  MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;\n  MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;\n  MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;\n  MPU_InitStruct.Number = MPU_REGION_NUMBER0;\n  MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;\n  MPU_InitStruct.SubRegionDisable = 0x00;\n  MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;\n\n  HAL_MPU_ConfigRegion(&MPU_InitStruct);\n\n  /* Enable the MPU */\n  HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/bsp/opencr/bsp.h",
    "content": "/*\n *  bsp.h\n *\n *  boart support package\n *\n *  Created on: 2017. 3. 16.\n *      Author: Baram\n */\n\n#ifndef BSP_H\n#define BSP_H\n\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n\n#include <stdint.h>\n\n#include \"def.h\"\n#include \"stm32f746xx.h\"\n#include \"stm32f7xx_hal.h\"\n#include \"system_clock.h\"\n\n\n#define USE_USB_FS\n\n\n\n\n\nvoid bsp_init();\nvoid bsp_deinit();\n\nvoid bsp_mpu_config(void);\n\n#ifdef __cplusplus\n}\n#endif\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/bsp/opencr/include/arm_common_tables.h",
    "content": "/* ----------------------------------------------------------------------\r\n* Copyright (C) 2010-2014 ARM Limited. All rights reserved.\r\n*\r\n* $Date:        19. October 2015\r\n* $Revision: \tV.1.4.5 a\r\n*\r\n* Project: \t    CMSIS DSP Library\r\n* Title:\t    arm_common_tables.h\r\n*\r\n* Description:\tThis file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions\r\n*\r\n* Target Processor: Cortex-M4/Cortex-M3\r\n*\r\n* Redistribution and use in source and binary forms, with or without\r\n* modification, are permitted provided that the following conditions\r\n* are met:\r\n*   - Redistributions of source code must retain the above copyright\r\n*     notice, this list of conditions and the following disclaimer.\r\n*   - Redistributions in binary form must reproduce the above copyright\r\n*     notice, this list of conditions and the following disclaimer in\r\n*     the documentation and/or other materials provided with the\r\n*     distribution.\r\n*   - Neither the name of ARM LIMITED nor the names of its contributors\r\n*     may be used to endorse or promote products derived from this\r\n*     software without specific prior written permission.\r\n*\r\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\r\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\r\n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n* POSSIBILITY OF SUCH DAMAGE.\r\n* -------------------------------------------------------------------- */\r\n\r\n#ifndef _ARM_COMMON_TABLES_H\r\n#define _ARM_COMMON_TABLES_H\r\n\r\n#include \"arm_math.h\"\r\n\r\nextern const uint16_t armBitRevTable[1024];\r\nextern const q15_t armRecipTableQ15[64];\r\nextern const q31_t armRecipTableQ31[64];\r\n/* extern const q31_t realCoefAQ31[1024]; */\r\n/* extern const q31_t realCoefBQ31[1024]; */\r\nextern const float32_t twiddleCoef_16[32];\r\nextern const float32_t twiddleCoef_32[64];\r\nextern const float32_t twiddleCoef_64[128];\r\nextern const float32_t twiddleCoef_128[256];\r\nextern const float32_t twiddleCoef_256[512];\r\nextern const float32_t twiddleCoef_512[1024];\r\nextern const float32_t twiddleCoef_1024[2048];\r\nextern const float32_t twiddleCoef_2048[4096];\r\nextern const float32_t twiddleCoef_4096[8192];\r\n#define twiddleCoef twiddleCoef_4096\r\nextern const q31_t twiddleCoef_16_q31[24];\r\nextern const q31_t twiddleCoef_32_q31[48];\r\nextern const q31_t twiddleCoef_64_q31[96];\r\nextern const q31_t twiddleCoef_128_q31[192];\r\nextern const q31_t twiddleCoef_256_q31[384];\r\nextern const q31_t twiddleCoef_512_q31[768];\r\nextern const q31_t twiddleCoef_1024_q31[1536];\r\nextern const q31_t twiddleCoef_2048_q31[3072];\r\nextern const q31_t twiddleCoef_4096_q31[6144];\r\nextern const q15_t twiddleCoef_16_q15[24];\r\nextern const q15_t twiddleCoef_32_q15[48];\r\nextern const q15_t twiddleCoef_64_q15[96];\r\nextern const q15_t twiddleCoef_128_q15[192];\r\nextern const q15_t twiddleCoef_256_q15[384];\r\nextern const q15_t twiddleCoef_512_q15[768];\r\nextern const q15_t twiddleCoef_1024_q15[1536];\r\nextern const q15_t twiddleCoef_2048_q15[3072];\r\nextern const q15_t twiddleCoef_4096_q15[6144];\r\nextern const float32_t twiddleCoef_rfft_32[32];\r\nextern const float32_t twiddleCoef_rfft_64[64];\r\nextern const float32_t twiddleCoef_rfft_128[128];\r\nextern const float32_t twiddleCoef_rfft_256[256];\r\nextern const float32_t twiddleCoef_rfft_512[512];\r\nextern const float32_t twiddleCoef_rfft_1024[1024];\r\nextern const float32_t twiddleCoef_rfft_2048[2048];\r\nextern const float32_t twiddleCoef_rfft_4096[4096];\r\n\r\n\r\n/* floating-point bit reversal tables */\r\n#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )\r\n#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )\r\n#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )\r\n#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )\r\n#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )\r\n#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )\r\n#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)\r\n#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)\r\n#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)\r\n\r\nextern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];\r\nextern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];\r\nextern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];\r\nextern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];\r\nextern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];\r\nextern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];\r\nextern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];\r\nextern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];\r\nextern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];\r\n\r\n/* fixed-point bit reversal tables */\r\n#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )\r\n#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )\r\n#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )\r\n#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )\r\n#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )\r\n#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )\r\n#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )\r\n#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)\r\n#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)\r\n\r\nextern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];\r\nextern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];\r\nextern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];\r\nextern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];\r\nextern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];\r\nextern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];\r\nextern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];\r\nextern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];\r\nextern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];\r\n\r\n/* Tables for Fast Math Sine and Cosine */\r\nextern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];\r\nextern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];\r\nextern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];\r\n\r\n#endif /*  ARM_COMMON_TABLES_H */\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/bsp/opencr/include/arm_const_structs.h",
    "content": "/* ----------------------------------------------------------------------\r\n* Copyright (C) 2010-2014 ARM Limited. All rights reserved.\r\n*\r\n* $Date:        19. March 2015\r\n* $Revision: \tV.1.4.5\r\n*\r\n* Project: \t    CMSIS DSP Library\r\n* Title:\t    arm_const_structs.h\r\n*\r\n* Description:\tThis file has constant structs that are initialized for\r\n*              user convenience.  For example, some can be given as\r\n*              arguments to the arm_cfft_f32() function.\r\n*\r\n* Target Processor: Cortex-M4/Cortex-M3\r\n*\r\n* Redistribution and use in source and binary forms, with or without\r\n* modification, are permitted provided that the following conditions\r\n* are met:\r\n*   - Redistributions of source code must retain the above copyright\r\n*     notice, this list of conditions and the following disclaimer.\r\n*   - Redistributions in binary form must reproduce the above copyright\r\n*     notice, this list of conditions and the following disclaimer in\r\n*     the documentation and/or other materials provided with the\r\n*     distribution.\r\n*   - Neither the name of ARM LIMITED nor the names of its contributors\r\n*     may be used to endorse or promote products derived from this\r\n*     software without specific prior written permission.\r\n*\r\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\r\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\r\n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n* POSSIBILITY OF SUCH DAMAGE.\r\n* -------------------------------------------------------------------- */\r\n\r\n#ifndef _ARM_CONST_STRUCTS_H\r\n#define _ARM_CONST_STRUCTS_H\r\n\r\n#include \"arm_math.h\"\r\n#include \"arm_common_tables.h\"\r\n\r\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;\r\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;\r\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;\r\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;\r\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;\r\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;\r\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;\r\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;\r\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;\r\n\r\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;\r\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;\r\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;\r\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;\r\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;\r\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;\r\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;\r\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;\r\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;\r\n\r\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;\r\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;\r\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;\r\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;\r\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;\r\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;\r\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;\r\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;\r\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;\r\n\r\n#endif\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/bsp/opencr/include/arm_math.h",
    "content": "/* ----------------------------------------------------------------------\r\n* Copyright (C) 2010-2015 ARM Limited. All rights reserved.\r\n*\r\n* $Date:        20. October 2015\r\n* $Revision:    V1.4.5 b\r\n*\r\n* Project:      CMSIS DSP Library\r\n* Title:        arm_math.h\r\n*\r\n* Description:  Public header file for CMSIS DSP Library\r\n*\r\n* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0\r\n*\r\n* Redistribution and use in source and binary forms, with or without\r\n* modification, are permitted provided that the following conditions\r\n* are met:\r\n*   - Redistributions of source code must retain the above copyright\r\n*     notice, this list of conditions and the following disclaimer.\r\n*   - Redistributions in binary form must reproduce the above copyright\r\n*     notice, this list of conditions and the following disclaimer in\r\n*     the documentation and/or other materials provided with the\r\n*     distribution.\r\n*   - Neither the name of ARM LIMITED nor the names of its contributors\r\n*     may be used to endorse or promote products derived from this\r\n*     software without specific prior written permission.\r\n*\r\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\r\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\r\n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n* POSSIBILITY OF SUCH DAMAGE.\r\n * -------------------------------------------------------------------- */\r\n\r\n/**\r\n   \\mainpage CMSIS DSP Software Library\r\n   *\r\n   * Introduction\r\n   * ------------\r\n   *\r\n   * This user manual describes the CMSIS DSP software library,\r\n   * a suite of common signal processing functions for use on Cortex-M processor based devices.\r\n   *\r\n   * The library is divided into a number of functions each covering a specific category:\r\n   * - Basic math functions\r\n   * - Fast math functions\r\n   * - Complex math functions\r\n   * - Filters\r\n   * - Matrix functions\r\n   * - Transforms\r\n   * - Motor control functions\r\n   * - Statistical functions\r\n   * - Support functions\r\n   * - Interpolation functions\r\n   *\r\n   * The library has separate functions for operating on 8-bit integers, 16-bit integers,\r\n   * 32-bit integer and 32-bit floating-point values.\r\n   *\r\n   * Using the Library\r\n   * ------------\r\n   *\r\n   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.\r\n   * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7)\r\n   * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7)\r\n   * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7)\r\n   * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7)\r\n   * - arm_cortexM7l_math.lib (Little endian on Cortex-M7)\r\n   * - arm_cortexM7b_math.lib (Big endian on Cortex-M7)\r\n   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)\r\n   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)\r\n   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)\r\n   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)\r\n   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)\r\n   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)\r\n   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+)\r\n   * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+)\r\n   *\r\n   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.\r\n   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single\r\n   * public header file <code> arm_math.h</code> for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.\r\n   * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or  ARM_MATH_CM3 or\r\n   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.\r\n   *\r\n   * Examples\r\n   * --------\r\n   *\r\n   * The library ships with a number of examples which demonstrate how to use the library functions.\r\n   *\r\n   * Toolchain Support\r\n   * ------------\r\n   *\r\n   * The library has been developed and tested with MDK-ARM version 5.14.0.0\r\n   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.\r\n   *\r\n   * Building the Library\r\n   * ------------\r\n   *\r\n   * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\\\DSP_Lib\\\\Source\\\\ARM</code> folder.\r\n   * - arm_cortexM_math.uvprojx\r\n   *\r\n   *\r\n   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.\r\n   *\r\n   * Pre-processor Macros\r\n   * ------------\r\n   *\r\n   * Each library project have differant pre-processor macros.\r\n   *\r\n   * - UNALIGNED_SUPPORT_DISABLE:\r\n   *\r\n   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access\r\n   *\r\n   * - ARM_MATH_BIG_ENDIAN:\r\n   *\r\n   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.\r\n   *\r\n   * - ARM_MATH_MATRIX_CHECK:\r\n   *\r\n   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices\r\n   *\r\n   * - ARM_MATH_ROUNDING:\r\n   *\r\n   * Define macro ARM_MATH_ROUNDING for rounding on support functions\r\n   *\r\n   * - ARM_MATH_CMx:\r\n   *\r\n   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target\r\n   * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and\r\n   * ARM_MATH_CM7 for building the library on cortex-M7.\r\n   *\r\n   * - __FPU_PRESENT:\r\n   *\r\n   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries\r\n   *\r\n   * <hr>\r\n   * CMSIS-DSP in ARM::CMSIS Pack\r\n   * -----------------------------\r\n   *\r\n   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:\r\n   * |File/Folder                   |Content                                                                 |\r\n   * |------------------------------|------------------------------------------------------------------------|\r\n   * |\\b CMSIS\\\\Documentation\\\\DSP  | This documentation                                                     |\r\n   * |\\b CMSIS\\\\DSP_Lib             | Software license agreement (license.txt)                               |\r\n   * |\\b CMSIS\\\\DSP_Lib\\\\Examples   | Example projects demonstrating the usage of the library functions      |\r\n   * |\\b CMSIS\\\\DSP_Lib\\\\Source     | Source files for rebuilding the library                                |\r\n   *\r\n   * <hr>\r\n   * Revision History of CMSIS-DSP\r\n   * ------------\r\n   * Please refer to \\ref ChangeLog_pg.\r\n   *\r\n   * Copyright Notice\r\n   * ------------\r\n   *\r\n   * Copyright (C) 2010-2015 ARM Limited. All rights reserved.\r\n   */\r\n\r\n\r\n/**\r\n * @defgroup groupMath Basic Math Functions\r\n */\r\n\r\n/**\r\n * @defgroup groupFastMath Fast Math Functions\r\n * This set of functions provides a fast approximation to sine, cosine, and square root.\r\n * As compared to most of the other functions in the CMSIS math library, the fast math functions\r\n * operate on individual values and not arrays.\r\n * There are separate functions for Q15, Q31, and floating-point data.\r\n *\r\n */\r\n\r\n/**\r\n * @defgroup groupCmplxMath Complex Math Functions\r\n * This set of functions operates on complex data vectors.\r\n * The data in the complex arrays is stored in an interleaved fashion\r\n * (real, imag, real, imag, ...).\r\n * In the API functions, the number of samples in a complex array refers\r\n * to the number of complex values; the array contains twice this number of\r\n * real values.\r\n */\r\n\r\n/**\r\n * @defgroup groupFilters Filtering Functions\r\n */\r\n\r\n/**\r\n * @defgroup groupMatrix Matrix Functions\r\n *\r\n * This set of functions provides basic matrix math operations.\r\n * The functions operate on matrix data structures.  For example,\r\n * the type\r\n * definition for the floating-point matrix structure is shown\r\n * below:\r\n * <pre>\r\n *     typedef struct\r\n *     {\r\n *       uint16_t numRows;     // number of rows of the matrix.\r\n *       uint16_t numCols;     // number of columns of the matrix.\r\n *       float32_t *pData;     // points to the data of the matrix.\r\n *     } arm_matrix_instance_f32;\r\n * </pre>\r\n * There are similar definitions for Q15 and Q31 data types.\r\n *\r\n * The structure specifies the size of the matrix and then points to\r\n * an array of data.  The array is of size <code>numRows X numCols</code>\r\n * and the values are arranged in row order.  That is, the\r\n * matrix element (i, j) is stored at:\r\n * <pre>\r\n *     pData[i*numCols + j]\r\n * </pre>\r\n *\r\n * \\par Init Functions\r\n * There is an associated initialization function for each type of matrix\r\n * data structure.\r\n * The initialization function sets the values of the internal structure fields.\r\n * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>\r\n * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.\r\n *\r\n * \\par\r\n * Use of the initialization function is optional. However, if initialization function is used\r\n * then the instance structure cannot be placed into a const data section.\r\n * To place the instance structure in a const data\r\n * section, manually initialize the data structure.  For example:\r\n * <pre>\r\n * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>\r\n * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>\r\n * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>\r\n * </pre>\r\n * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>\r\n * specifies the number of columns, and <code>pData</code> points to the\r\n * data array.\r\n *\r\n * \\par Size Checking\r\n * By default all of the matrix functions perform size checking on the input and\r\n * output matrices.  For example, the matrix addition function verifies that the\r\n * two input matrices and the output matrix all have the same number of rows and\r\n * columns.  If the size check fails the functions return:\r\n * <pre>\r\n *     ARM_MATH_SIZE_MISMATCH\r\n * </pre>\r\n * Otherwise the functions return\r\n * <pre>\r\n *     ARM_MATH_SUCCESS\r\n * </pre>\r\n * There is some overhead associated with this matrix size checking.\r\n * The matrix size checking is enabled via the \\#define\r\n * <pre>\r\n *     ARM_MATH_MATRIX_CHECK\r\n * </pre>\r\n * within the library project settings.  By default this macro is defined\r\n * and size checking is enabled.  By changing the project settings and\r\n * undefining this macro size checking is eliminated and the functions\r\n * run a bit faster.  With size checking disabled the functions always\r\n * return <code>ARM_MATH_SUCCESS</code>.\r\n */\r\n\r\n/**\r\n * @defgroup groupTransforms Transform Functions\r\n */\r\n\r\n/**\r\n * @defgroup groupController Controller Functions\r\n */\r\n\r\n/**\r\n * @defgroup groupStats Statistics Functions\r\n */\r\n/**\r\n * @defgroup groupSupport Support Functions\r\n */\r\n\r\n/**\r\n * @defgroup groupInterpolation Interpolation Functions\r\n * These functions perform 1- and 2-dimensional interpolation of data.\r\n * Linear interpolation is used for 1-dimensional data and\r\n * bilinear interpolation is used for 2-dimensional data.\r\n */\r\n\r\n/**\r\n * @defgroup groupExamples Examples\r\n */\r\n#ifndef _ARM_MATH_H\r\n#define _ARM_MATH_H\r\n\r\n/* ignore some GCC warnings */\r\n#if defined ( __GNUC__ )\r\n#pragma GCC diagnostic push\r\n#pragma GCC diagnostic ignored \"-Wsign-conversion\"\r\n#pragma GCC diagnostic ignored \"-Wconversion\"\r\n#pragma GCC diagnostic ignored \"-Wunused-parameter\"\r\n#endif\r\n\r\n#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */\r\n\r\n#if defined(ARM_MATH_CM7)\r\n  #include \"core_cm7.h\"\r\n#elif defined (ARM_MATH_CM4)\r\n  #include \"core_cm4.h\"\r\n#elif defined (ARM_MATH_CM3)\r\n  #include \"core_cm3.h\"\r\n#elif defined (ARM_MATH_CM0)\r\n  #include \"core_cm0.h\"\r\n  #define ARM_MATH_CM0_FAMILY\r\n#elif defined (ARM_MATH_CM0PLUS)\r\n  #include \"core_cm0plus.h\"\r\n  #define ARM_MATH_CM0_FAMILY\r\n#else\r\n  #error \"Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0\"\r\n#endif\r\n\r\n#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */\r\n#include \"string.h\"\r\n#include \"math.h\"\r\n#ifdef   __cplusplus\r\nextern \"C\"\r\n{\r\n#endif\r\n\r\n\r\n  /**\r\n   * @brief Macros required for reciprocal calculation in Normalized LMS\r\n   */\r\n\r\n#define DELTA_Q31          (0x100)\r\n#define DELTA_Q15          0x5\r\n#define INDEX_MASK         0x0000003F\r\n#ifndef PI\r\n#define PI                 3.14159265358979f\r\n#endif\r\n\r\n  /**\r\n   * @brief Macros required for SINE and COSINE Fast math approximations\r\n   */\r\n\r\n#define FAST_MATH_TABLE_SIZE  512\r\n#define FAST_MATH_Q31_SHIFT   (32 - 10)\r\n#define FAST_MATH_Q15_SHIFT   (16 - 10)\r\n#define CONTROLLER_Q31_SHIFT  (32 - 9)\r\n#define TABLE_SIZE  256\r\n#define TABLE_SPACING_Q31     0x400000\r\n#define TABLE_SPACING_Q15     0x80\r\n\r\n  /**\r\n   * @brief Macros required for SINE and COSINE Controller functions\r\n   */\r\n  /* 1.31(q31) Fixed value of 2/360 */\r\n  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */\r\n#define INPUT_SPACING         0xB60B61\r\n\r\n  /**\r\n   * @brief Macro for Unaligned Support\r\n   */\r\n#ifndef UNALIGNED_SUPPORT_DISABLE\r\n    #define ALIGN4\r\n#else\r\n  #if defined  (__GNUC__)\r\n    #define ALIGN4 __attribute__((aligned(4)))\r\n  #else\r\n    #define ALIGN4 __align(4)\r\n  #endif\r\n#endif   /* #ifndef UNALIGNED_SUPPORT_DISABLE */\r\n\r\n  /**\r\n   * @brief Error status returned by some functions in the library.\r\n   */\r\n\r\n  typedef enum\r\n  {\r\n    ARM_MATH_SUCCESS = 0,                /**< No error */\r\n    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */\r\n    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */\r\n    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */\r\n    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */\r\n    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */\r\n    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */\r\n  } arm_status;\r\n\r\n  /**\r\n   * @brief 8-bit fractional data type in 1.7 format.\r\n   */\r\n  typedef int8_t q7_t;\r\n\r\n  /**\r\n   * @brief 16-bit fractional data type in 1.15 format.\r\n   */\r\n  typedef int16_t q15_t;\r\n\r\n  /**\r\n   * @brief 32-bit fractional data type in 1.31 format.\r\n   */\r\n  typedef int32_t q31_t;\r\n\r\n  /**\r\n   * @brief 64-bit fractional data type in 1.63 format.\r\n   */\r\n  typedef int64_t q63_t;\r\n\r\n  /**\r\n   * @brief 32-bit floating-point type definition.\r\n   */\r\n  typedef float float32_t;\r\n\r\n  /**\r\n   * @brief 64-bit floating-point type definition.\r\n   */\r\n  typedef double float64_t;\r\n\r\n  /**\r\n   * @brief definition to read/write two 16 bit values.\r\n   */\r\n#if defined __CC_ARM\r\n  #define __SIMD32_TYPE int32_t __packed\r\n  #define CMSIS_UNUSED __attribute__((unused))\r\n\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #define __SIMD32_TYPE int32_t\r\n  #define CMSIS_UNUSED __attribute__((unused))\r\n\r\n#elif defined __GNUC__\r\n  #define __SIMD32_TYPE int32_t\r\n  #define CMSIS_UNUSED __attribute__((unused))\r\n\r\n#elif defined __ICCARM__\r\n  #define __SIMD32_TYPE int32_t __packed\r\n  #define CMSIS_UNUSED\r\n\r\n#elif defined __CSMC__\r\n  #define __SIMD32_TYPE int32_t\r\n  #define CMSIS_UNUSED\r\n\r\n#elif defined __TASKING__\r\n  #define __SIMD32_TYPE __unaligned int32_t\r\n  #define CMSIS_UNUSED\r\n\r\n#else\r\n  #error Unknown compiler\r\n#endif\r\n\r\n#define __SIMD32(addr)        (*(__SIMD32_TYPE **) & (addr))\r\n#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))\r\n#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))\r\n#define __SIMD64(addr)        (*(int64_t **) & (addr))\r\n\r\n#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)\r\n  /**\r\n   * @brief definition to pack two 16 bit values.\r\n   */\r\n#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \\\r\n                                         (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )\r\n#define __PKHTB(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0xFFFF0000) | \\\r\n                                         (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )\r\n\r\n#endif\r\n\r\n\r\n   /**\r\n   * @brief definition to pack four 8 bit values.\r\n   */\r\n#ifndef ARM_MATH_BIG_ENDIAN\r\n\r\n#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) | \\\r\n                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) | \\\r\n                                (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \\\r\n                                (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )\r\n#else\r\n\r\n#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) | \\\r\n                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) | \\\r\n                                (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \\\r\n                                (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )\r\n\r\n#endif\r\n\r\n\r\n  /**\r\n   * @brief Clips Q63 to Q31 values.\r\n   */\r\n  static __INLINE q31_t clip_q63_to_q31(\r\n  q63_t x)\r\n  {\r\n    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\r\n      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;\r\n  }\r\n\r\n  /**\r\n   * @brief Clips Q63 to Q15 values.\r\n   */\r\n  static __INLINE q15_t clip_q63_to_q15(\r\n  q63_t x)\r\n  {\r\n    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\r\n      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);\r\n  }\r\n\r\n  /**\r\n   * @brief Clips Q31 to Q7 values.\r\n   */\r\n  static __INLINE q7_t clip_q31_to_q7(\r\n  q31_t x)\r\n  {\r\n    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?\r\n      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;\r\n  }\r\n\r\n  /**\r\n   * @brief Clips Q31 to Q15 values.\r\n   */\r\n  static __INLINE q15_t clip_q31_to_q15(\r\n  q31_t x)\r\n  {\r\n    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?\r\n      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;\r\n  }\r\n\r\n  /**\r\n   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.\r\n   */\r\n\r\n  static __INLINE q63_t mult32x64(\r\n  q63_t x,\r\n  q31_t y)\r\n  {\r\n    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +\r\n            (((q63_t) (x >> 32) * y)));\r\n  }\r\n\r\n/*\r\n  #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )\r\n  #define __CLZ __clz\r\n  #endif\r\n */\r\n/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */\r\n#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__))  )\r\n  static __INLINE uint32_t __CLZ(\r\n  q31_t data);\r\n\r\n  static __INLINE uint32_t __CLZ(\r\n  q31_t data)\r\n  {\r\n    uint32_t count = 0;\r\n    uint32_t mask = 0x80000000;\r\n\r\n    while((data & mask) == 0)\r\n    {\r\n      count += 1u;\r\n      mask = mask >> 1u;\r\n    }\r\n\r\n    return (count);\r\n  }\r\n#endif\r\n\r\n  /**\r\n   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.\r\n   */\r\n\r\n  static __INLINE uint32_t arm_recip_q31(\r\n  q31_t in,\r\n  q31_t * dst,\r\n  q31_t * pRecipTable)\r\n  {\r\n    q31_t out;\r\n    uint32_t tempVal;\r\n    uint32_t index, i;\r\n    uint32_t signBits;\r\n\r\n    if(in > 0)\r\n    {\r\n      signBits = ((uint32_t) (__CLZ( in) - 1));\r\n    }\r\n    else\r\n    {\r\n      signBits = ((uint32_t) (__CLZ(-in) - 1));\r\n    }\r\n\r\n    /* Convert input sample to 1.31 format */\r\n    in = (in << signBits);\r\n\r\n    /* calculation of index for initial approximated Val */\r\n    index = (uint32_t)(in >> 24);\r\n    index = (index & INDEX_MASK);\r\n\r\n    /* 1.31 with exp 1 */\r\n    out = pRecipTable[index];\r\n\r\n    /* calculation of reciprocal value */\r\n    /* running approximation for two iterations */\r\n    for (i = 0u; i < 2u; i++)\r\n    {\r\n      tempVal = (uint32_t) (((q63_t) in * out) >> 31);\r\n      tempVal = 0x7FFFFFFFu - tempVal;\r\n      /*      1.31 with exp 1 */\r\n      /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */\r\n      out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);\r\n    }\r\n\r\n    /* write output */\r\n    *dst = out;\r\n\r\n    /* return num of signbits of out = 1/in value */\r\n    return (signBits + 1u);\r\n  }\r\n\r\n\r\n  /**\r\n   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.\r\n   */\r\n  static __INLINE uint32_t arm_recip_q15(\r\n  q15_t in,\r\n  q15_t * dst,\r\n  q15_t * pRecipTable)\r\n  {\r\n    q15_t out = 0;\r\n    uint32_t tempVal = 0;\r\n    uint32_t index = 0, i = 0;\r\n    uint32_t signBits = 0;\r\n\r\n    if(in > 0)\r\n    {\r\n      signBits = ((uint32_t)(__CLZ( in) - 17));\r\n    }\r\n    else\r\n    {\r\n      signBits = ((uint32_t)(__CLZ(-in) - 17));\r\n    }\r\n\r\n    /* Convert input sample to 1.15 format */\r\n    in = (in << signBits);\r\n\r\n    /* calculation of index for initial approximated Val */\r\n    index = (uint32_t)(in >>  8);\r\n    index = (index & INDEX_MASK);\r\n\r\n    /*      1.15 with exp 1  */\r\n    out = pRecipTable[index];\r\n\r\n    /* calculation of reciprocal value */\r\n    /* running approximation for two iterations */\r\n    for (i = 0u; i < 2u; i++)\r\n    {\r\n      tempVal = (uint32_t) (((q31_t) in * out) >> 15);\r\n      tempVal = 0x7FFFu - tempVal;\r\n      /*      1.15 with exp 1 */\r\n      out = (q15_t) (((q31_t) out * tempVal) >> 14);\r\n      /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */\r\n    }\r\n\r\n    /* write output */\r\n    *dst = out;\r\n\r\n    /* return num of signbits of out = 1/in value */\r\n    return (signBits + 1);\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined intrinisic function for only M0 processors\r\n   */\r\n#if defined(ARM_MATH_CM0_FAMILY)\r\n  static __INLINE q31_t __SSAT(\r\n  q31_t x,\r\n  uint32_t y)\r\n  {\r\n    int32_t posMax, negMin;\r\n    uint32_t i;\r\n\r\n    posMax = 1;\r\n    for (i = 0; i < (y - 1); i++)\r\n    {\r\n      posMax = posMax * 2;\r\n    }\r\n\r\n    if(x > 0)\r\n    {\r\n      posMax = (posMax - 1);\r\n\r\n      if(x > posMax)\r\n      {\r\n        x = posMax;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      negMin = -posMax;\r\n\r\n      if(x < negMin)\r\n      {\r\n        x = negMin;\r\n      }\r\n    }\r\n    return (x);\r\n  }\r\n#endif /* end of ARM_MATH_CM0_FAMILY */\r\n\r\n\r\n  /*\r\n   * @brief C custom defined intrinsic function for M3 and M0 processors\r\n   */\r\n#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)\r\n\r\n  /*\r\n   * @brief C custom defined QADD8 for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __QADD8(\r\n  uint32_t x,\r\n  uint32_t y)\r\n  {\r\n    q31_t r, s, t, u;\r\n\r\n    r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;\r\n    s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;\r\n    t = __SSAT(((((q31_t)x <<  8) >> 24) + (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;\r\n    u = __SSAT(((((q31_t)x      ) >> 24) + (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;\r\n\r\n    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined QSUB8 for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __QSUB8(\r\n  uint32_t x,\r\n  uint32_t y)\r\n  {\r\n    q31_t r, s, t, u;\r\n\r\n    r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;\r\n    s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;\r\n    t = __SSAT(((((q31_t)x <<  8) >> 24) - (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;\r\n    u = __SSAT(((((q31_t)x      ) >> 24) - (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;\r\n\r\n    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined QADD16 for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __QADD16(\r\n  uint32_t x,\r\n  uint32_t y)\r\n  {\r\n/*  q31_t r,     s;  without initialisation 'arm_offset_q15 test' fails  but 'intrinsic' tests pass! for armCC */\r\n    q31_t r = 0, s = 0;\r\n\r\n    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\r\n    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;\r\n\r\n    return ((uint32_t)((s << 16) | (r      )));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined SHADD16 for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __SHADD16(\r\n  uint32_t x,\r\n  uint32_t y)\r\n  {\r\n    q31_t r, s;\r\n\r\n    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r\n    s = (((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r\n\r\n    return ((uint32_t)((s << 16) | (r      )));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined QSUB16 for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __QSUB16(\r\n  uint32_t x,\r\n  uint32_t y)\r\n  {\r\n    q31_t r, s;\r\n\r\n    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\r\n    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;\r\n\r\n    return ((uint32_t)((s << 16) | (r      )));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined SHSUB16 for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __SHSUB16(\r\n  uint32_t x,\r\n  uint32_t y)\r\n  {\r\n    q31_t r, s;\r\n\r\n    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r\n    s = (((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r\n\r\n    return ((uint32_t)((s << 16) | (r      )));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined QASX for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __QASX(\r\n  uint32_t x,\r\n  uint32_t y)\r\n  {\r\n    q31_t r, s;\r\n\r\n    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;\r\n    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\r\n\r\n    return ((uint32_t)((s << 16) | (r      )));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined SHASX for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __SHASX(\r\n  uint32_t x,\r\n  uint32_t y)\r\n  {\r\n    q31_t r, s;\r\n\r\n    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r\n    s = (((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r\n\r\n    return ((uint32_t)((s << 16) | (r      )));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined QSAX for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __QSAX(\r\n  uint32_t x,\r\n  uint32_t y)\r\n  {\r\n    q31_t r, s;\r\n\r\n    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;\r\n    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\r\n\r\n    return ((uint32_t)((s << 16) | (r      )));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined SHSAX for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __SHSAX(\r\n  uint32_t x,\r\n  uint32_t y)\r\n  {\r\n    q31_t r, s;\r\n\r\n    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r\n    s = (((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r\n\r\n    return ((uint32_t)((s << 16) | (r      )));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined SMUSDX for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __SMUSDX(\r\n  uint32_t x,\r\n  uint32_t y)\r\n  {\r\n    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -\r\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));\r\n  }\r\n\r\n  /*\r\n   * @brief C custom defined SMUADX for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __SMUADX(\r\n  uint32_t x,\r\n  uint32_t y)\r\n  {\r\n    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +\r\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined QADD for M3 and M0 processors\r\n   */\r\n  static __INLINE int32_t __QADD(\r\n  int32_t x,\r\n  int32_t y)\r\n  {\r\n    return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined QSUB for M3 and M0 processors\r\n   */\r\n  static __INLINE int32_t __QSUB(\r\n  int32_t x,\r\n  int32_t y)\r\n  {\r\n    return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined SMLAD for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __SMLAD(\r\n  uint32_t x,\r\n  uint32_t y,\r\n  uint32_t sum)\r\n  {\r\n    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +\r\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +\r\n                       ( ((q31_t)sum    )                                  )   ));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined SMLADX for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __SMLADX(\r\n  uint32_t x,\r\n  uint32_t y,\r\n  uint32_t sum)\r\n  {\r\n    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +\r\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +\r\n                       ( ((q31_t)sum    )                                  )   ));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined SMLSDX for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __SMLSDX(\r\n  uint32_t x,\r\n  uint32_t y,\r\n  uint32_t sum)\r\n  {\r\n    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -\r\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +\r\n                       ( ((q31_t)sum    )                                  )   ));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined SMLALD for M3 and M0 processors\r\n   */\r\n  static __INLINE uint64_t __SMLALD(\r\n  uint32_t x,\r\n  uint32_t y,\r\n  uint64_t sum)\r\n  {\r\n/*  return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */\r\n    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +\r\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +\r\n                       ( ((q63_t)sum    )                                  )   ));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined SMLALDX for M3 and M0 processors\r\n   */\r\n  static __INLINE uint64_t __SMLALDX(\r\n  uint32_t x,\r\n  uint32_t y,\r\n  uint64_t sum)\r\n  {\r\n/*  return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */\r\n    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +\r\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +\r\n                       ( ((q63_t)sum    )                                  )   ));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined SMUAD for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __SMUAD(\r\n  uint32_t x,\r\n  uint32_t y)\r\n  {\r\n    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +\r\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined SMUSD for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __SMUSD(\r\n  uint32_t x,\r\n  uint32_t y)\r\n  {\r\n    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -\r\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined SXTB16 for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __SXTB16(\r\n  uint32_t x)\r\n  {\r\n    return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |\r\n                       ((((q31_t)x <<  8) >>  8) & (q31_t)0xFFFF0000)  ));\r\n  }\r\n\r\n#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the Q7 FIR filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numTaps;        /**< number of filter coefficients in the filter. */\r\n    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/\r\n  } arm_fir_instance_q7;\r\n\r\n  /**\r\n   * @brief Instance structure for the Q15 FIR filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numTaps;         /**< number of filter coefficients in the filter. */\r\n    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/\r\n  } arm_fir_instance_q15;\r\n\r\n  /**\r\n   * @brief Instance structure for the Q31 FIR filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numTaps;         /**< number of filter coefficients in the filter. */\r\n    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */\r\n  } arm_fir_instance_q31;\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point FIR filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numTaps;     /**< number of filter coefficients in the filter. */\r\n    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */\r\n  } arm_fir_instance_f32;\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q7 FIR filter.\r\n   * @param[in]  S          points to an instance of the Q7 FIR filter structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_fir_q7(\r\n  const arm_fir_instance_q7 * S,\r\n  q7_t * pSrc,\r\n  q7_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the Q7 FIR filter.\r\n   * @param[in,out] S          points to an instance of the Q7 FIR structure.\r\n   * @param[in]     numTaps    Number of filter coefficients in the filter.\r\n   * @param[in]     pCoeffs    points to the filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   * @param[in]     blockSize  number of samples that are processed.\r\n   */\r\n  void arm_fir_init_q7(\r\n  arm_fir_instance_q7 * S,\r\n  uint16_t numTaps,\r\n  q7_t * pCoeffs,\r\n  q7_t * pState,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q15 FIR filter.\r\n   * @param[in]  S          points to an instance of the Q15 FIR structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_fir_q15(\r\n  const arm_fir_instance_q15 * S,\r\n  q15_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.\r\n   * @param[in]  S          points to an instance of the Q15 FIR filter structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_fir_fast_q15(\r\n  const arm_fir_instance_q15 * S,\r\n  q15_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the Q15 FIR filter.\r\n   * @param[in,out] S          points to an instance of the Q15 FIR filter structure.\r\n   * @param[in]     numTaps    Number of filter coefficients in the filter. Must be even and greater than or equal to 4.\r\n   * @param[in]     pCoeffs    points to the filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   * @param[in]     blockSize  number of samples that are processed at a time.\r\n   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if\r\n   * <code>numTaps</code> is not a supported value.\r\n   */\r\n  arm_status arm_fir_init_q15(\r\n  arm_fir_instance_q15 * S,\r\n  uint16_t numTaps,\r\n  q15_t * pCoeffs,\r\n  q15_t * pState,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q31 FIR filter.\r\n   * @param[in]  S          points to an instance of the Q31 FIR filter structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_fir_q31(\r\n  const arm_fir_instance_q31 * S,\r\n  q31_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.\r\n   * @param[in]  S          points to an instance of the Q31 FIR structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_fir_fast_q31(\r\n  const arm_fir_instance_q31 * S,\r\n  q31_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the Q31 FIR filter.\r\n   * @param[in,out] S          points to an instance of the Q31 FIR structure.\r\n   * @param[in]     numTaps    Number of filter coefficients in the filter.\r\n   * @param[in]     pCoeffs    points to the filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   * @param[in]     blockSize  number of samples that are processed at a time.\r\n   */\r\n  void arm_fir_init_q31(\r\n  arm_fir_instance_q31 * S,\r\n  uint16_t numTaps,\r\n  q31_t * pCoeffs,\r\n  q31_t * pState,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the floating-point FIR filter.\r\n   * @param[in]  S          points to an instance of the floating-point FIR structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_fir_f32(\r\n  const arm_fir_instance_f32 * S,\r\n  float32_t * pSrc,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the floating-point FIR filter.\r\n   * @param[in,out] S          points to an instance of the floating-point FIR filter structure.\r\n   * @param[in]     numTaps    Number of filter coefficients in the filter.\r\n   * @param[in]     pCoeffs    points to the filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   * @param[in]     blockSize  number of samples that are processed at a time.\r\n   */\r\n  void arm_fir_init_f32(\r\n  arm_fir_instance_f32 * S,\r\n  uint16_t numTaps,\r\n  float32_t * pCoeffs,\r\n  float32_t * pState,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the Q15 Biquad cascade filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    int8_t numStages;        /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */\r\n    q15_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */\r\n    q15_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */\r\n    int8_t postShift;        /**< Additional shift, in bits, applied to each output sample. */\r\n  } arm_biquad_casd_df1_inst_q15;\r\n\r\n  /**\r\n   * @brief Instance structure for the Q31 Biquad cascade filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */\r\n    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */\r\n    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */\r\n    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */\r\n  } arm_biquad_casd_df1_inst_q31;\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point Biquad cascade filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */\r\n    float32_t *pState;       /**< Points to the array of state coefficients.  The array is of length 4*numStages. */\r\n    float32_t *pCoeffs;      /**< Points to the array of coefficients.  The array is of length 5*numStages. */\r\n  } arm_biquad_casd_df1_inst_f32;\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q15 Biquad cascade filter.\r\n   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_biquad_cascade_df1_q15(\r\n  const arm_biquad_casd_df1_inst_q15 * S,\r\n  q15_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the Q15 Biquad cascade filter.\r\n   * @param[in,out] S          points to an instance of the Q15 Biquad cascade structure.\r\n   * @param[in]     numStages  number of 2nd order stages in the filter.\r\n   * @param[in]     pCoeffs    points to the filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format\r\n   */\r\n  void arm_biquad_cascade_df1_init_q15(\r\n  arm_biquad_casd_df1_inst_q15 * S,\r\n  uint8_t numStages,\r\n  q15_t * pCoeffs,\r\n  q15_t * pState,\r\n  int8_t postShift);\r\n\r\n\r\n  /**\r\n   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.\r\n   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_biquad_cascade_df1_fast_q15(\r\n  const arm_biquad_casd_df1_inst_q15 * S,\r\n  q15_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q31 Biquad cascade filter\r\n   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_biquad_cascade_df1_q31(\r\n  const arm_biquad_casd_df1_inst_q31 * S,\r\n  q31_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.\r\n   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_biquad_cascade_df1_fast_q31(\r\n  const arm_biquad_casd_df1_inst_q31 * S,\r\n  q31_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the Q31 Biquad cascade filter.\r\n   * @param[in,out] S          points to an instance of the Q31 Biquad cascade structure.\r\n   * @param[in]     numStages  number of 2nd order stages in the filter.\r\n   * @param[in]     pCoeffs    points to the filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format\r\n   */\r\n  void arm_biquad_cascade_df1_init_q31(\r\n  arm_biquad_casd_df1_inst_q31 * S,\r\n  uint8_t numStages,\r\n  q31_t * pCoeffs,\r\n  q31_t * pState,\r\n  int8_t postShift);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the floating-point Biquad cascade filter.\r\n   * @param[in]  S          points to an instance of the floating-point Biquad cascade structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_biquad_cascade_df1_f32(\r\n  const arm_biquad_casd_df1_inst_f32 * S,\r\n  float32_t * pSrc,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the floating-point Biquad cascade filter.\r\n   * @param[in,out] S          points to an instance of the floating-point Biquad cascade structure.\r\n   * @param[in]     numStages  number of 2nd order stages in the filter.\r\n   * @param[in]     pCoeffs    points to the filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   */\r\n  void arm_biquad_cascade_df1_init_f32(\r\n  arm_biquad_casd_df1_inst_f32 * S,\r\n  uint8_t numStages,\r\n  float32_t * pCoeffs,\r\n  float32_t * pState);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point matrix structure.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numRows;     /**< number of rows of the matrix.     */\r\n    uint16_t numCols;     /**< number of columns of the matrix.  */\r\n    float32_t *pData;     /**< points to the data of the matrix. */\r\n  } arm_matrix_instance_f32;\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point matrix structure.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numRows;     /**< number of rows of the matrix.     */\r\n    uint16_t numCols;     /**< number of columns of the matrix.  */\r\n    float64_t *pData;     /**< points to the data of the matrix. */\r\n  } arm_matrix_instance_f64;\r\n\r\n  /**\r\n   * @brief Instance structure for the Q15 matrix structure.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numRows;     /**< number of rows of the matrix.     */\r\n    uint16_t numCols;     /**< number of columns of the matrix.  */\r\n    q15_t *pData;         /**< points to the data of the matrix. */\r\n  } arm_matrix_instance_q15;\r\n\r\n  /**\r\n   * @brief Instance structure for the Q31 matrix structure.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numRows;     /**< number of rows of the matrix.     */\r\n    uint16_t numCols;     /**< number of columns of the matrix.  */\r\n    q31_t *pData;         /**< points to the data of the matrix. */\r\n  } arm_matrix_instance_q31;\r\n\r\n\r\n  /**\r\n   * @brief Floating-point matrix addition.\r\n   * @param[in]  pSrcA  points to the first input matrix structure\r\n   * @param[in]  pSrcB  points to the second input matrix structure\r\n   * @param[out] pDst   points to output matrix structure\r\n   * @return     The function returns either\r\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_add_f32(\r\n  const arm_matrix_instance_f32 * pSrcA,\r\n  const arm_matrix_instance_f32 * pSrcB,\r\n  arm_matrix_instance_f32 * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Q15 matrix addition.\r\n   * @param[in]   pSrcA  points to the first input matrix structure\r\n   * @param[in]   pSrcB  points to the second input matrix structure\r\n   * @param[out]  pDst   points to output matrix structure\r\n   * @return     The function returns either\r\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_add_q15(\r\n  const arm_matrix_instance_q15 * pSrcA,\r\n  const arm_matrix_instance_q15 * pSrcB,\r\n  arm_matrix_instance_q15 * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Q31 matrix addition.\r\n   * @param[in]  pSrcA  points to the first input matrix structure\r\n   * @param[in]  pSrcB  points to the second input matrix structure\r\n   * @param[out] pDst   points to output matrix structure\r\n   * @return     The function returns either\r\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_add_q31(\r\n  const arm_matrix_instance_q31 * pSrcA,\r\n  const arm_matrix_instance_q31 * pSrcB,\r\n  arm_matrix_instance_q31 * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Floating-point, complex, matrix multiplication.\r\n   * @param[in]  pSrcA  points to the first input matrix structure\r\n   * @param[in]  pSrcB  points to the second input matrix structure\r\n   * @param[out] pDst   points to output matrix structure\r\n   * @return     The function returns either\r\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_cmplx_mult_f32(\r\n  const arm_matrix_instance_f32 * pSrcA,\r\n  const arm_matrix_instance_f32 * pSrcB,\r\n  arm_matrix_instance_f32 * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Q15, complex,  matrix multiplication.\r\n   * @param[in]  pSrcA  points to the first input matrix structure\r\n   * @param[in]  pSrcB  points to the second input matrix structure\r\n   * @param[out] pDst   points to output matrix structure\r\n   * @return     The function returns either\r\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_cmplx_mult_q15(\r\n  const arm_matrix_instance_q15 * pSrcA,\r\n  const arm_matrix_instance_q15 * pSrcB,\r\n  arm_matrix_instance_q15 * pDst,\r\n  q15_t * pScratch);\r\n\r\n\r\n  /**\r\n   * @brief Q31, complex, matrix multiplication.\r\n   * @param[in]  pSrcA  points to the first input matrix structure\r\n   * @param[in]  pSrcB  points to the second input matrix structure\r\n   * @param[out] pDst   points to output matrix structure\r\n   * @return     The function returns either\r\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_cmplx_mult_q31(\r\n  const arm_matrix_instance_q31 * pSrcA,\r\n  const arm_matrix_instance_q31 * pSrcB,\r\n  arm_matrix_instance_q31 * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Floating-point matrix transpose.\r\n   * @param[in]  pSrc  points to the input matrix\r\n   * @param[out] pDst  points to the output matrix\r\n   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>\r\n   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_trans_f32(\r\n  const arm_matrix_instance_f32 * pSrc,\r\n  arm_matrix_instance_f32 * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Q15 matrix transpose.\r\n   * @param[in]  pSrc  points to the input matrix\r\n   * @param[out] pDst  points to the output matrix\r\n   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>\r\n   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_trans_q15(\r\n  const arm_matrix_instance_q15 * pSrc,\r\n  arm_matrix_instance_q15 * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Q31 matrix transpose.\r\n   * @param[in]  pSrc  points to the input matrix\r\n   * @param[out] pDst  points to the output matrix\r\n   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>\r\n   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_trans_q31(\r\n  const arm_matrix_instance_q31 * pSrc,\r\n  arm_matrix_instance_q31 * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Floating-point matrix multiplication\r\n   * @param[in]  pSrcA  points to the first input matrix structure\r\n   * @param[in]  pSrcB  points to the second input matrix structure\r\n   * @param[out] pDst   points to output matrix structure\r\n   * @return     The function returns either\r\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_mult_f32(\r\n  const arm_matrix_instance_f32 * pSrcA,\r\n  const arm_matrix_instance_f32 * pSrcB,\r\n  arm_matrix_instance_f32 * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Q15 matrix multiplication\r\n   * @param[in]  pSrcA   points to the first input matrix structure\r\n   * @param[in]  pSrcB   points to the second input matrix structure\r\n   * @param[out] pDst    points to output matrix structure\r\n   * @param[in]  pState  points to the array for storing intermediate results\r\n   * @return     The function returns either\r\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_mult_q15(\r\n  const arm_matrix_instance_q15 * pSrcA,\r\n  const arm_matrix_instance_q15 * pSrcB,\r\n  arm_matrix_instance_q15 * pDst,\r\n  q15_t * pState);\r\n\r\n\r\n  /**\r\n   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\r\n   * @param[in]  pSrcA   points to the first input matrix structure\r\n   * @param[in]  pSrcB   points to the second input matrix structure\r\n   * @param[out] pDst    points to output matrix structure\r\n   * @param[in]  pState  points to the array for storing intermediate results\r\n   * @return     The function returns either\r\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_mult_fast_q15(\r\n  const arm_matrix_instance_q15 * pSrcA,\r\n  const arm_matrix_instance_q15 * pSrcB,\r\n  arm_matrix_instance_q15 * pDst,\r\n  q15_t * pState);\r\n\r\n\r\n  /**\r\n   * @brief Q31 matrix multiplication\r\n   * @param[in]  pSrcA  points to the first input matrix structure\r\n   * @param[in]  pSrcB  points to the second input matrix structure\r\n   * @param[out] pDst   points to output matrix structure\r\n   * @return     The function returns either\r\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_mult_q31(\r\n  const arm_matrix_instance_q31 * pSrcA,\r\n  const arm_matrix_instance_q31 * pSrcB,\r\n  arm_matrix_instance_q31 * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\r\n   * @param[in]  pSrcA  points to the first input matrix structure\r\n   * @param[in]  pSrcB  points to the second input matrix structure\r\n   * @param[out] pDst   points to output matrix structure\r\n   * @return     The function returns either\r\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_mult_fast_q31(\r\n  const arm_matrix_instance_q31 * pSrcA,\r\n  const arm_matrix_instance_q31 * pSrcB,\r\n  arm_matrix_instance_q31 * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Floating-point matrix subtraction\r\n   * @param[in]  pSrcA  points to the first input matrix structure\r\n   * @param[in]  pSrcB  points to the second input matrix structure\r\n   * @param[out] pDst   points to output matrix structure\r\n   * @return     The function returns either\r\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_sub_f32(\r\n  const arm_matrix_instance_f32 * pSrcA,\r\n  const arm_matrix_instance_f32 * pSrcB,\r\n  arm_matrix_instance_f32 * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Q15 matrix subtraction\r\n   * @param[in]  pSrcA  points to the first input matrix structure\r\n   * @param[in]  pSrcB  points to the second input matrix structure\r\n   * @param[out] pDst   points to output matrix structure\r\n   * @return     The function returns either\r\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_sub_q15(\r\n  const arm_matrix_instance_q15 * pSrcA,\r\n  const arm_matrix_instance_q15 * pSrcB,\r\n  arm_matrix_instance_q15 * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Q31 matrix subtraction\r\n   * @param[in]  pSrcA  points to the first input matrix structure\r\n   * @param[in]  pSrcB  points to the second input matrix structure\r\n   * @param[out] pDst   points to output matrix structure\r\n   * @return     The function returns either\r\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_sub_q31(\r\n  const arm_matrix_instance_q31 * pSrcA,\r\n  const arm_matrix_instance_q31 * pSrcB,\r\n  arm_matrix_instance_q31 * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Floating-point matrix scaling.\r\n   * @param[in]  pSrc   points to the input matrix\r\n   * @param[in]  scale  scale factor\r\n   * @param[out] pDst   points to the output matrix\r\n   * @return     The function returns either\r\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_scale_f32(\r\n  const arm_matrix_instance_f32 * pSrc,\r\n  float32_t scale,\r\n  arm_matrix_instance_f32 * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Q15 matrix scaling.\r\n   * @param[in]  pSrc        points to input matrix\r\n   * @param[in]  scaleFract  fractional portion of the scale factor\r\n   * @param[in]  shift       number of bits to shift the result by\r\n   * @param[out] pDst        points to output matrix\r\n   * @return     The function returns either\r\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_scale_q15(\r\n  const arm_matrix_instance_q15 * pSrc,\r\n  q15_t scaleFract,\r\n  int32_t shift,\r\n  arm_matrix_instance_q15 * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Q31 matrix scaling.\r\n   * @param[in]  pSrc        points to input matrix\r\n   * @param[in]  scaleFract  fractional portion of the scale factor\r\n   * @param[in]  shift       number of bits to shift the result by\r\n   * @param[out] pDst        points to output matrix structure\r\n   * @return     The function returns either\r\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_scale_q31(\r\n  const arm_matrix_instance_q31 * pSrc,\r\n  q31_t scaleFract,\r\n  int32_t shift,\r\n  arm_matrix_instance_q31 * pDst);\r\n\r\n\r\n  /**\r\n   * @brief  Q31 matrix initialization.\r\n   * @param[in,out] S         points to an instance of the floating-point matrix structure.\r\n   * @param[in]     nRows     number of rows in the matrix.\r\n   * @param[in]     nColumns  number of columns in the matrix.\r\n   * @param[in]     pData     points to the matrix data array.\r\n   */\r\n  void arm_mat_init_q31(\r\n  arm_matrix_instance_q31 * S,\r\n  uint16_t nRows,\r\n  uint16_t nColumns,\r\n  q31_t * pData);\r\n\r\n\r\n  /**\r\n   * @brief  Q15 matrix initialization.\r\n   * @param[in,out] S         points to an instance of the floating-point matrix structure.\r\n   * @param[in]     nRows     number of rows in the matrix.\r\n   * @param[in]     nColumns  number of columns in the matrix.\r\n   * @param[in]     pData     points to the matrix data array.\r\n   */\r\n  void arm_mat_init_q15(\r\n  arm_matrix_instance_q15 * S,\r\n  uint16_t nRows,\r\n  uint16_t nColumns,\r\n  q15_t * pData);\r\n\r\n\r\n  /**\r\n   * @brief  Floating-point matrix initialization.\r\n   * @param[in,out] S         points to an instance of the floating-point matrix structure.\r\n   * @param[in]     nRows     number of rows in the matrix.\r\n   * @param[in]     nColumns  number of columns in the matrix.\r\n   * @param[in]     pData     points to the matrix data array.\r\n   */\r\n  void arm_mat_init_f32(\r\n  arm_matrix_instance_f32 * S,\r\n  uint16_t nRows,\r\n  uint16_t nColumns,\r\n  float32_t * pData);\r\n\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the Q15 PID Control.\r\n   */\r\n  typedef struct\r\n  {\r\n    q15_t A0;           /**< The derived gain, A0 = Kp + Ki + Kd . */\r\n#ifdef ARM_MATH_CM0_FAMILY\r\n    q15_t A1;\r\n    q15_t A2;\r\n#else\r\n    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/\r\n#endif\r\n    q15_t state[3];     /**< The state array of length 3. */\r\n    q15_t Kp;           /**< The proportional gain. */\r\n    q15_t Ki;           /**< The integral gain. */\r\n    q15_t Kd;           /**< The derivative gain. */\r\n  } arm_pid_instance_q15;\r\n\r\n  /**\r\n   * @brief Instance structure for the Q31 PID Control.\r\n   */\r\n  typedef struct\r\n  {\r\n    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */\r\n    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */\r\n    q31_t A2;            /**< The derived gain, A2 = Kd . */\r\n    q31_t state[3];      /**< The state array of length 3. */\r\n    q31_t Kp;            /**< The proportional gain. */\r\n    q31_t Ki;            /**< The integral gain. */\r\n    q31_t Kd;            /**< The derivative gain. */\r\n  } arm_pid_instance_q31;\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point PID Control.\r\n   */\r\n  typedef struct\r\n  {\r\n    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */\r\n    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */\r\n    float32_t A2;          /**< The derived gain, A2 = Kd . */\r\n    float32_t state[3];    /**< The state array of length 3. */\r\n    float32_t Kp;          /**< The proportional gain. */\r\n    float32_t Ki;          /**< The integral gain. */\r\n    float32_t Kd;          /**< The derivative gain. */\r\n  } arm_pid_instance_f32;\r\n\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the floating-point PID Control.\r\n   * @param[in,out] S               points to an instance of the PID structure.\r\n   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.\r\n   */\r\n  void arm_pid_init_f32(\r\n  arm_pid_instance_f32 * S,\r\n  int32_t resetStateFlag);\r\n\r\n\r\n  /**\r\n   * @brief  Reset function for the floating-point PID Control.\r\n   * @param[in,out] S  is an instance of the floating-point PID Control structure\r\n   */\r\n  void arm_pid_reset_f32(\r\n  arm_pid_instance_f32 * S);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the Q31 PID Control.\r\n   * @param[in,out] S               points to an instance of the Q15 PID structure.\r\n   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.\r\n   */\r\n  void arm_pid_init_q31(\r\n  arm_pid_instance_q31 * S,\r\n  int32_t resetStateFlag);\r\n\r\n\r\n  /**\r\n   * @brief  Reset function for the Q31 PID Control.\r\n   * @param[in,out] S   points to an instance of the Q31 PID Control structure\r\n   */\r\n\r\n  void arm_pid_reset_q31(\r\n  arm_pid_instance_q31 * S);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the Q15 PID Control.\r\n   * @param[in,out] S               points to an instance of the Q15 PID structure.\r\n   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.\r\n   */\r\n  void arm_pid_init_q15(\r\n  arm_pid_instance_q15 * S,\r\n  int32_t resetStateFlag);\r\n\r\n\r\n  /**\r\n   * @brief  Reset function for the Q15 PID Control.\r\n   * @param[in,out] S  points to an instance of the q15 PID Control structure\r\n   */\r\n  void arm_pid_reset_q15(\r\n  arm_pid_instance_q15 * S);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point Linear Interpolate function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint32_t nValues;           /**< nValues */\r\n    float32_t x1;               /**< x1 */\r\n    float32_t xSpacing;         /**< xSpacing */\r\n    float32_t *pYData;          /**< pointer to the table of Y values */\r\n  } arm_linear_interp_instance_f32;\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point bilinear interpolation function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numRows;   /**< number of rows in the data table. */\r\n    uint16_t numCols;   /**< number of columns in the data table. */\r\n    float32_t *pData;   /**< points to the data table. */\r\n  } arm_bilinear_interp_instance_f32;\r\n\r\n   /**\r\n   * @brief Instance structure for the Q31 bilinear interpolation function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numRows;   /**< number of rows in the data table. */\r\n    uint16_t numCols;   /**< number of columns in the data table. */\r\n    q31_t *pData;       /**< points to the data table. */\r\n  } arm_bilinear_interp_instance_q31;\r\n\r\n   /**\r\n   * @brief Instance structure for the Q15 bilinear interpolation function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numRows;   /**< number of rows in the data table. */\r\n    uint16_t numCols;   /**< number of columns in the data table. */\r\n    q15_t *pData;       /**< points to the data table. */\r\n  } arm_bilinear_interp_instance_q15;\r\n\r\n   /**\r\n   * @brief Instance structure for the Q15 bilinear interpolation function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numRows;   /**< number of rows in the data table. */\r\n    uint16_t numCols;   /**< number of columns in the data table. */\r\n    q7_t *pData;        /**< points to the data table. */\r\n  } arm_bilinear_interp_instance_q7;\r\n\r\n\r\n  /**\r\n   * @brief Q7 vector multiplication.\r\n   * @param[in]  pSrcA      points to the first input vector\r\n   * @param[in]  pSrcB      points to the second input vector\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   */\r\n  void arm_mult_q7(\r\n  q7_t * pSrcA,\r\n  q7_t * pSrcB,\r\n  q7_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Q15 vector multiplication.\r\n   * @param[in]  pSrcA      points to the first input vector\r\n   * @param[in]  pSrcB      points to the second input vector\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   */\r\n  void arm_mult_q15(\r\n  q15_t * pSrcA,\r\n  q15_t * pSrcB,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Q31 vector multiplication.\r\n   * @param[in]  pSrcA      points to the first input vector\r\n   * @param[in]  pSrcB      points to the second input vector\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   */\r\n  void arm_mult_q31(\r\n  q31_t * pSrcA,\r\n  q31_t * pSrcB,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Floating-point vector multiplication.\r\n   * @param[in]  pSrcA      points to the first input vector\r\n   * @param[in]  pSrcB      points to the second input vector\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   */\r\n  void arm_mult_f32(\r\n  float32_t * pSrcA,\r\n  float32_t * pSrcB,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the Q15 CFFT/CIFFT function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t fftLen;                 /**< length of the FFT. */\r\n    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r\n    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r\n    q15_t *pTwiddle;                 /**< points to the Sin twiddle factor table. */\r\n    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */\r\n    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r\n    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r\n  } arm_cfft_radix2_instance_q15;\r\n\r\n/* Deprecated */\r\n  arm_status arm_cfft_radix2_init_q15(\r\n  arm_cfft_radix2_instance_q15 * S,\r\n  uint16_t fftLen,\r\n  uint8_t ifftFlag,\r\n  uint8_t bitReverseFlag);\r\n\r\n/* Deprecated */\r\n  void arm_cfft_radix2_q15(\r\n  const arm_cfft_radix2_instance_q15 * S,\r\n  q15_t * pSrc);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the Q15 CFFT/CIFFT function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t fftLen;                 /**< length of the FFT. */\r\n    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r\n    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r\n    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */\r\n    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */\r\n    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r\n    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r\n  } arm_cfft_radix4_instance_q15;\r\n\r\n/* Deprecated */\r\n  arm_status arm_cfft_radix4_init_q15(\r\n  arm_cfft_radix4_instance_q15 * S,\r\n  uint16_t fftLen,\r\n  uint8_t ifftFlag,\r\n  uint8_t bitReverseFlag);\r\n\r\n/* Deprecated */\r\n  void arm_cfft_radix4_q15(\r\n  const arm_cfft_radix4_instance_q15 * S,\r\n  q15_t * pSrc);\r\n\r\n  /**\r\n   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t fftLen;                 /**< length of the FFT. */\r\n    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r\n    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r\n    q31_t *pTwiddle;                 /**< points to the Twiddle factor table. */\r\n    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */\r\n    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r\n    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r\n  } arm_cfft_radix2_instance_q31;\r\n\r\n/* Deprecated */\r\n  arm_status arm_cfft_radix2_init_q31(\r\n  arm_cfft_radix2_instance_q31 * S,\r\n  uint16_t fftLen,\r\n  uint8_t ifftFlag,\r\n  uint8_t bitReverseFlag);\r\n\r\n/* Deprecated */\r\n  void arm_cfft_radix2_q31(\r\n  const arm_cfft_radix2_instance_q31 * S,\r\n  q31_t * pSrc);\r\n\r\n  /**\r\n   * @brief Instance structure for the Q31 CFFT/CIFFT function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t fftLen;                 /**< length of the FFT. */\r\n    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r\n    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r\n    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */\r\n    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */\r\n    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r\n    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r\n  } arm_cfft_radix4_instance_q31;\r\n\r\n/* Deprecated */\r\n  void arm_cfft_radix4_q31(\r\n  const arm_cfft_radix4_instance_q31 * S,\r\n  q31_t * pSrc);\r\n\r\n/* Deprecated */\r\n  arm_status arm_cfft_radix4_init_q31(\r\n  arm_cfft_radix4_instance_q31 * S,\r\n  uint16_t fftLen,\r\n  uint8_t ifftFlag,\r\n  uint8_t bitReverseFlag);\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point CFFT/CIFFT function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t fftLen;                   /**< length of the FFT. */\r\n    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r\n    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r\n    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */\r\n    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */\r\n    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r\n    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r\n    float32_t onebyfftLen;             /**< value of 1/fftLen. */\r\n  } arm_cfft_radix2_instance_f32;\r\n\r\n/* Deprecated */\r\n  arm_status arm_cfft_radix2_init_f32(\r\n  arm_cfft_radix2_instance_f32 * S,\r\n  uint16_t fftLen,\r\n  uint8_t ifftFlag,\r\n  uint8_t bitReverseFlag);\r\n\r\n/* Deprecated */\r\n  void arm_cfft_radix2_f32(\r\n  const arm_cfft_radix2_instance_f32 * S,\r\n  float32_t * pSrc);\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point CFFT/CIFFT function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t fftLen;                   /**< length of the FFT. */\r\n    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r\n    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r\n    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */\r\n    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */\r\n    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r\n    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r\n    float32_t onebyfftLen;             /**< value of 1/fftLen. */\r\n  } arm_cfft_radix4_instance_f32;\r\n\r\n/* Deprecated */\r\n  arm_status arm_cfft_radix4_init_f32(\r\n  arm_cfft_radix4_instance_f32 * S,\r\n  uint16_t fftLen,\r\n  uint8_t ifftFlag,\r\n  uint8_t bitReverseFlag);\r\n\r\n/* Deprecated */\r\n  void arm_cfft_radix4_f32(\r\n  const arm_cfft_radix4_instance_f32 * S,\r\n  float32_t * pSrc);\r\n\r\n  /**\r\n   * @brief Instance structure for the fixed-point CFFT/CIFFT function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t fftLen;                   /**< length of the FFT. */\r\n    const q15_t *pTwiddle;             /**< points to the Twiddle factor table. */\r\n    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */\r\n    uint16_t bitRevLength;             /**< bit reversal table length. */\r\n  } arm_cfft_instance_q15;\r\n\r\nvoid arm_cfft_q15(\r\n    const arm_cfft_instance_q15 * S,\r\n    q15_t * p1,\r\n    uint8_t ifftFlag,\r\n    uint8_t bitReverseFlag);\r\n\r\n  /**\r\n   * @brief Instance structure for the fixed-point CFFT/CIFFT function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t fftLen;                   /**< length of the FFT. */\r\n    const q31_t *pTwiddle;             /**< points to the Twiddle factor table. */\r\n    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */\r\n    uint16_t bitRevLength;             /**< bit reversal table length. */\r\n  } arm_cfft_instance_q31;\r\n\r\nvoid arm_cfft_q31(\r\n    const arm_cfft_instance_q31 * S,\r\n    q31_t * p1,\r\n    uint8_t ifftFlag,\r\n    uint8_t bitReverseFlag);\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point CFFT/CIFFT function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t fftLen;                   /**< length of the FFT. */\r\n    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */\r\n    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */\r\n    uint16_t bitRevLength;             /**< bit reversal table length. */\r\n  } arm_cfft_instance_f32;\r\n\r\n  void arm_cfft_f32(\r\n  const arm_cfft_instance_f32 * S,\r\n  float32_t * p1,\r\n  uint8_t ifftFlag,\r\n  uint8_t bitReverseFlag);\r\n\r\n  /**\r\n   * @brief Instance structure for the Q15 RFFT/RIFFT function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint32_t fftLenReal;                      /**< length of the real FFT. */\r\n    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r\n    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r\n    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r\n    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */\r\n    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */\r\n    const arm_cfft_instance_q15 *pCfft;       /**< points to the complex FFT instance. */\r\n  } arm_rfft_instance_q15;\r\n\r\n  arm_status arm_rfft_init_q15(\r\n  arm_rfft_instance_q15 * S,\r\n  uint32_t fftLenReal,\r\n  uint32_t ifftFlagR,\r\n  uint32_t bitReverseFlag);\r\n\r\n  void arm_rfft_q15(\r\n  const arm_rfft_instance_q15 * S,\r\n  q15_t * pSrc,\r\n  q15_t * pDst);\r\n\r\n  /**\r\n   * @brief Instance structure for the Q31 RFFT/RIFFT function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint32_t fftLenReal;                        /**< length of the real FFT. */\r\n    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r\n    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r\n    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r\n    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */\r\n    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */\r\n    const arm_cfft_instance_q31 *pCfft;         /**< points to the complex FFT instance. */\r\n  } arm_rfft_instance_q31;\r\n\r\n  arm_status arm_rfft_init_q31(\r\n  arm_rfft_instance_q31 * S,\r\n  uint32_t fftLenReal,\r\n  uint32_t ifftFlagR,\r\n  uint32_t bitReverseFlag);\r\n\r\n  void arm_rfft_q31(\r\n  const arm_rfft_instance_q31 * S,\r\n  q31_t * pSrc,\r\n  q31_t * pDst);\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point RFFT/RIFFT function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint32_t fftLenReal;                        /**< length of the real FFT. */\r\n    uint16_t fftLenBy2;                         /**< length of the complex FFT. */\r\n    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r\n    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r\n    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r\n    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */\r\n    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */\r\n    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */\r\n  } arm_rfft_instance_f32;\r\n\r\n  arm_status arm_rfft_init_f32(\r\n  arm_rfft_instance_f32 * S,\r\n  arm_cfft_radix4_instance_f32 * S_CFFT,\r\n  uint32_t fftLenReal,\r\n  uint32_t ifftFlagR,\r\n  uint32_t bitReverseFlag);\r\n\r\n  void arm_rfft_f32(\r\n  const arm_rfft_instance_f32 * S,\r\n  float32_t * pSrc,\r\n  float32_t * pDst);\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point RFFT/RIFFT function.\r\n   */\r\ntypedef struct\r\n  {\r\n    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */\r\n    uint16_t fftLenRFFT;             /**< length of the real sequence */\r\n    float32_t * pTwiddleRFFT;        /**< Twiddle factors real stage  */\r\n  } arm_rfft_fast_instance_f32 ;\r\n\r\narm_status arm_rfft_fast_init_f32 (\r\n   arm_rfft_fast_instance_f32 * S,\r\n   uint16_t fftLen);\r\n\r\nvoid arm_rfft_fast_f32(\r\n  arm_rfft_fast_instance_f32 * S,\r\n  float32_t * p, float32_t * pOut,\r\n  uint8_t ifftFlag);\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point DCT4/IDCT4 function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t N;                          /**< length of the DCT4. */\r\n    uint16_t Nby2;                       /**< half of the length of the DCT4. */\r\n    float32_t normalize;                 /**< normalizing factor. */\r\n    float32_t *pTwiddle;                 /**< points to the twiddle factor table. */\r\n    float32_t *pCosFactor;               /**< points to the cosFactor table. */\r\n    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */\r\n    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */\r\n  } arm_dct4_instance_f32;\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the floating-point DCT4/IDCT4.\r\n   * @param[in,out] S          points to an instance of floating-point DCT4/IDCT4 structure.\r\n   * @param[in]     S_RFFT     points to an instance of floating-point RFFT/RIFFT structure.\r\n   * @param[in]     S_CFFT     points to an instance of floating-point CFFT/CIFFT structure.\r\n   * @param[in]     N          length of the DCT4.\r\n   * @param[in]     Nby2       half of the length of the DCT4.\r\n   * @param[in]     normalize  normalizing factor.\r\n   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.\r\n   */\r\n  arm_status arm_dct4_init_f32(\r\n  arm_dct4_instance_f32 * S,\r\n  arm_rfft_instance_f32 * S_RFFT,\r\n  arm_cfft_radix4_instance_f32 * S_CFFT,\r\n  uint16_t N,\r\n  uint16_t Nby2,\r\n  float32_t normalize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the floating-point DCT4/IDCT4.\r\n   * @param[in]     S              points to an instance of the floating-point DCT4/IDCT4 structure.\r\n   * @param[in]     pState         points to state buffer.\r\n   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.\r\n   */\r\n  void arm_dct4_f32(\r\n  const arm_dct4_instance_f32 * S,\r\n  float32_t * pState,\r\n  float32_t * pInlineBuffer);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the Q31 DCT4/IDCT4 function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t N;                          /**< length of the DCT4. */\r\n    uint16_t Nby2;                       /**< half of the length of the DCT4. */\r\n    q31_t normalize;                     /**< normalizing factor. */\r\n    q31_t *pTwiddle;                     /**< points to the twiddle factor table. */\r\n    q31_t *pCosFactor;                   /**< points to the cosFactor table. */\r\n    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */\r\n    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */\r\n  } arm_dct4_instance_q31;\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the Q31 DCT4/IDCT4.\r\n   * @param[in,out] S          points to an instance of Q31 DCT4/IDCT4 structure.\r\n   * @param[in]     S_RFFT     points to an instance of Q31 RFFT/RIFFT structure\r\n   * @param[in]     S_CFFT     points to an instance of Q31 CFFT/CIFFT structure\r\n   * @param[in]     N          length of the DCT4.\r\n   * @param[in]     Nby2       half of the length of the DCT4.\r\n   * @param[in]     normalize  normalizing factor.\r\n   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.\r\n   */\r\n  arm_status arm_dct4_init_q31(\r\n  arm_dct4_instance_q31 * S,\r\n  arm_rfft_instance_q31 * S_RFFT,\r\n  arm_cfft_radix4_instance_q31 * S_CFFT,\r\n  uint16_t N,\r\n  uint16_t Nby2,\r\n  q31_t normalize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q31 DCT4/IDCT4.\r\n   * @param[in]     S              points to an instance of the Q31 DCT4 structure.\r\n   * @param[in]     pState         points to state buffer.\r\n   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.\r\n   */\r\n  void arm_dct4_q31(\r\n  const arm_dct4_instance_q31 * S,\r\n  q31_t * pState,\r\n  q31_t * pInlineBuffer);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the Q15 DCT4/IDCT4 function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t N;                          /**< length of the DCT4. */\r\n    uint16_t Nby2;                       /**< half of the length of the DCT4. */\r\n    q15_t normalize;                     /**< normalizing factor. */\r\n    q15_t *pTwiddle;                     /**< points to the twiddle factor table. */\r\n    q15_t *pCosFactor;                   /**< points to the cosFactor table. */\r\n    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */\r\n    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */\r\n  } arm_dct4_instance_q15;\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the Q15 DCT4/IDCT4.\r\n   * @param[in,out] S          points to an instance of Q15 DCT4/IDCT4 structure.\r\n   * @param[in]     S_RFFT     points to an instance of Q15 RFFT/RIFFT structure.\r\n   * @param[in]     S_CFFT     points to an instance of Q15 CFFT/CIFFT structure.\r\n   * @param[in]     N          length of the DCT4.\r\n   * @param[in]     Nby2       half of the length of the DCT4.\r\n   * @param[in]     normalize  normalizing factor.\r\n   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.\r\n   */\r\n  arm_status arm_dct4_init_q15(\r\n  arm_dct4_instance_q15 * S,\r\n  arm_rfft_instance_q15 * S_RFFT,\r\n  arm_cfft_radix4_instance_q15 * S_CFFT,\r\n  uint16_t N,\r\n  uint16_t Nby2,\r\n  q15_t normalize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q15 DCT4/IDCT4.\r\n   * @param[in]     S              points to an instance of the Q15 DCT4 structure.\r\n   * @param[in]     pState         points to state buffer.\r\n   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.\r\n   */\r\n  void arm_dct4_q15(\r\n  const arm_dct4_instance_q15 * S,\r\n  q15_t * pState,\r\n  q15_t * pInlineBuffer);\r\n\r\n\r\n  /**\r\n   * @brief Floating-point vector addition.\r\n   * @param[in]  pSrcA      points to the first input vector\r\n   * @param[in]  pSrcB      points to the second input vector\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   */\r\n  void arm_add_f32(\r\n  float32_t * pSrcA,\r\n  float32_t * pSrcB,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Q7 vector addition.\r\n   * @param[in]  pSrcA      points to the first input vector\r\n   * @param[in]  pSrcB      points to the second input vector\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   */\r\n  void arm_add_q7(\r\n  q7_t * pSrcA,\r\n  q7_t * pSrcB,\r\n  q7_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Q15 vector addition.\r\n   * @param[in]  pSrcA      points to the first input vector\r\n   * @param[in]  pSrcB      points to the second input vector\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   */\r\n  void arm_add_q15(\r\n  q15_t * pSrcA,\r\n  q15_t * pSrcB,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Q31 vector addition.\r\n   * @param[in]  pSrcA      points to the first input vector\r\n   * @param[in]  pSrcB      points to the second input vector\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   */\r\n  void arm_add_q31(\r\n  q31_t * pSrcA,\r\n  q31_t * pSrcB,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Floating-point vector subtraction.\r\n   * @param[in]  pSrcA      points to the first input vector\r\n   * @param[in]  pSrcB      points to the second input vector\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   */\r\n  void arm_sub_f32(\r\n  float32_t * pSrcA,\r\n  float32_t * pSrcB,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Q7 vector subtraction.\r\n   * @param[in]  pSrcA      points to the first input vector\r\n   * @param[in]  pSrcB      points to the second input vector\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   */\r\n  void arm_sub_q7(\r\n  q7_t * pSrcA,\r\n  q7_t * pSrcB,\r\n  q7_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Q15 vector subtraction.\r\n   * @param[in]  pSrcA      points to the first input vector\r\n   * @param[in]  pSrcB      points to the second input vector\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   */\r\n  void arm_sub_q15(\r\n  q15_t * pSrcA,\r\n  q15_t * pSrcB,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Q31 vector subtraction.\r\n   * @param[in]  pSrcA      points to the first input vector\r\n   * @param[in]  pSrcB      points to the second input vector\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   */\r\n  void arm_sub_q31(\r\n  q31_t * pSrcA,\r\n  q31_t * pSrcB,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Multiplies a floating-point vector by a scalar.\r\n   * @param[in]  pSrc       points to the input vector\r\n   * @param[in]  scale      scale factor to be applied\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in the vector\r\n   */\r\n  void arm_scale_f32(\r\n  float32_t * pSrc,\r\n  float32_t scale,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Multiplies a Q7 vector by a scalar.\r\n   * @param[in]  pSrc        points to the input vector\r\n   * @param[in]  scaleFract  fractional portion of the scale value\r\n   * @param[in]  shift       number of bits to shift the result by\r\n   * @param[out] pDst        points to the output vector\r\n   * @param[in]  blockSize   number of samples in the vector\r\n   */\r\n  void arm_scale_q7(\r\n  q7_t * pSrc,\r\n  q7_t scaleFract,\r\n  int8_t shift,\r\n  q7_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Multiplies a Q15 vector by a scalar.\r\n   * @param[in]  pSrc        points to the input vector\r\n   * @param[in]  scaleFract  fractional portion of the scale value\r\n   * @param[in]  shift       number of bits to shift the result by\r\n   * @param[out] pDst        points to the output vector\r\n   * @param[in]  blockSize   number of samples in the vector\r\n   */\r\n  void arm_scale_q15(\r\n  q15_t * pSrc,\r\n  q15_t scaleFract,\r\n  int8_t shift,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Multiplies a Q31 vector by a scalar.\r\n   * @param[in]  pSrc        points to the input vector\r\n   * @param[in]  scaleFract  fractional portion of the scale value\r\n   * @param[in]  shift       number of bits to shift the result by\r\n   * @param[out] pDst        points to the output vector\r\n   * @param[in]  blockSize   number of samples in the vector\r\n   */\r\n  void arm_scale_q31(\r\n  q31_t * pSrc,\r\n  q31_t scaleFract,\r\n  int8_t shift,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Q7 vector absolute value.\r\n   * @param[in]  pSrc       points to the input buffer\r\n   * @param[out] pDst       points to the output buffer\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   */\r\n  void arm_abs_q7(\r\n  q7_t * pSrc,\r\n  q7_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Floating-point vector absolute value.\r\n   * @param[in]  pSrc       points to the input buffer\r\n   * @param[out] pDst       points to the output buffer\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   */\r\n  void arm_abs_f32(\r\n  float32_t * pSrc,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Q15 vector absolute value.\r\n   * @param[in]  pSrc       points to the input buffer\r\n   * @param[out] pDst       points to the output buffer\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   */\r\n  void arm_abs_q15(\r\n  q15_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Q31 vector absolute value.\r\n   * @param[in]  pSrc       points to the input buffer\r\n   * @param[out] pDst       points to the output buffer\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   */\r\n  void arm_abs_q31(\r\n  q31_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Dot product of floating-point vectors.\r\n   * @param[in]  pSrcA      points to the first input vector\r\n   * @param[in]  pSrcB      points to the second input vector\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   * @param[out] result     output result returned here\r\n   */\r\n  void arm_dot_prod_f32(\r\n  float32_t * pSrcA,\r\n  float32_t * pSrcB,\r\n  uint32_t blockSize,\r\n  float32_t * result);\r\n\r\n\r\n  /**\r\n   * @brief Dot product of Q7 vectors.\r\n   * @param[in]  pSrcA      points to the first input vector\r\n   * @param[in]  pSrcB      points to the second input vector\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   * @param[out] result     output result returned here\r\n   */\r\n  void arm_dot_prod_q7(\r\n  q7_t * pSrcA,\r\n  q7_t * pSrcB,\r\n  uint32_t blockSize,\r\n  q31_t * result);\r\n\r\n\r\n  /**\r\n   * @brief Dot product of Q15 vectors.\r\n   * @param[in]  pSrcA      points to the first input vector\r\n   * @param[in]  pSrcB      points to the second input vector\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   * @param[out] result     output result returned here\r\n   */\r\n  void arm_dot_prod_q15(\r\n  q15_t * pSrcA,\r\n  q15_t * pSrcB,\r\n  uint32_t blockSize,\r\n  q63_t * result);\r\n\r\n\r\n  /**\r\n   * @brief Dot product of Q31 vectors.\r\n   * @param[in]  pSrcA      points to the first input vector\r\n   * @param[in]  pSrcB      points to the second input vector\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   * @param[out] result     output result returned here\r\n   */\r\n  void arm_dot_prod_q31(\r\n  q31_t * pSrcA,\r\n  q31_t * pSrcB,\r\n  uint32_t blockSize,\r\n  q63_t * result);\r\n\r\n\r\n  /**\r\n   * @brief  Shifts the elements of a Q7 vector a specified number of bits.\r\n   * @param[in]  pSrc       points to the input vector\r\n   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in the vector\r\n   */\r\n  void arm_shift_q7(\r\n  q7_t * pSrc,\r\n  int8_t shiftBits,\r\n  q7_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Shifts the elements of a Q15 vector a specified number of bits.\r\n   * @param[in]  pSrc       points to the input vector\r\n   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in the vector\r\n   */\r\n  void arm_shift_q15(\r\n  q15_t * pSrc,\r\n  int8_t shiftBits,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Shifts the elements of a Q31 vector a specified number of bits.\r\n   * @param[in]  pSrc       points to the input vector\r\n   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in the vector\r\n   */\r\n  void arm_shift_q31(\r\n  q31_t * pSrc,\r\n  int8_t shiftBits,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Adds a constant offset to a floating-point vector.\r\n   * @param[in]  pSrc       points to the input vector\r\n   * @param[in]  offset     is the offset to be added\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in the vector\r\n   */\r\n  void arm_offset_f32(\r\n  float32_t * pSrc,\r\n  float32_t offset,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Adds a constant offset to a Q7 vector.\r\n   * @param[in]  pSrc       points to the input vector\r\n   * @param[in]  offset     is the offset to be added\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in the vector\r\n   */\r\n  void arm_offset_q7(\r\n  q7_t * pSrc,\r\n  q7_t offset,\r\n  q7_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Adds a constant offset to a Q15 vector.\r\n   * @param[in]  pSrc       points to the input vector\r\n   * @param[in]  offset     is the offset to be added\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in the vector\r\n   */\r\n  void arm_offset_q15(\r\n  q15_t * pSrc,\r\n  q15_t offset,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Adds a constant offset to a Q31 vector.\r\n   * @param[in]  pSrc       points to the input vector\r\n   * @param[in]  offset     is the offset to be added\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in the vector\r\n   */\r\n  void arm_offset_q31(\r\n  q31_t * pSrc,\r\n  q31_t offset,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Negates the elements of a floating-point vector.\r\n   * @param[in]  pSrc       points to the input vector\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in the vector\r\n   */\r\n  void arm_negate_f32(\r\n  float32_t * pSrc,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Negates the elements of a Q7 vector.\r\n   * @param[in]  pSrc       points to the input vector\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in the vector\r\n   */\r\n  void arm_negate_q7(\r\n  q7_t * pSrc,\r\n  q7_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Negates the elements of a Q15 vector.\r\n   * @param[in]  pSrc       points to the input vector\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in the vector\r\n   */\r\n  void arm_negate_q15(\r\n  q15_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Negates the elements of a Q31 vector.\r\n   * @param[in]  pSrc       points to the input vector\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in the vector\r\n   */\r\n  void arm_negate_q31(\r\n  q31_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Copies the elements of a floating-point vector.\r\n   * @param[in]  pSrc       input pointer\r\n   * @param[out] pDst       output pointer\r\n   * @param[in]  blockSize  number of samples to process\r\n   */\r\n  void arm_copy_f32(\r\n  float32_t * pSrc,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Copies the elements of a Q7 vector.\r\n   * @param[in]  pSrc       input pointer\r\n   * @param[out] pDst       output pointer\r\n   * @param[in]  blockSize  number of samples to process\r\n   */\r\n  void arm_copy_q7(\r\n  q7_t * pSrc,\r\n  q7_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Copies the elements of a Q15 vector.\r\n   * @param[in]  pSrc       input pointer\r\n   * @param[out] pDst       output pointer\r\n   * @param[in]  blockSize  number of samples to process\r\n   */\r\n  void arm_copy_q15(\r\n  q15_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Copies the elements of a Q31 vector.\r\n   * @param[in]  pSrc       input pointer\r\n   * @param[out] pDst       output pointer\r\n   * @param[in]  blockSize  number of samples to process\r\n   */\r\n  void arm_copy_q31(\r\n  q31_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Fills a constant value into a floating-point vector.\r\n   * @param[in]  value      input value to be filled\r\n   * @param[out] pDst       output pointer\r\n   * @param[in]  blockSize  number of samples to process\r\n   */\r\n  void arm_fill_f32(\r\n  float32_t value,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Fills a constant value into a Q7 vector.\r\n   * @param[in]  value      input value to be filled\r\n   * @param[out] pDst       output pointer\r\n   * @param[in]  blockSize  number of samples to process\r\n   */\r\n  void arm_fill_q7(\r\n  q7_t value,\r\n  q7_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Fills a constant value into a Q15 vector.\r\n   * @param[in]  value      input value to be filled\r\n   * @param[out] pDst       output pointer\r\n   * @param[in]  blockSize  number of samples to process\r\n   */\r\n  void arm_fill_q15(\r\n  q15_t value,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Fills a constant value into a Q31 vector.\r\n   * @param[in]  value      input value to be filled\r\n   * @param[out] pDst       output pointer\r\n   * @param[in]  blockSize  number of samples to process\r\n   */\r\n  void arm_fill_q31(\r\n  q31_t value,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n/**\r\n * @brief Convolution of floating-point sequences.\r\n * @param[in]  pSrcA    points to the first input sequence.\r\n * @param[in]  srcALen  length of the first input sequence.\r\n * @param[in]  pSrcB    points to the second input sequence.\r\n * @param[in]  srcBLen  length of the second input sequence.\r\n * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.\r\n */\r\n  void arm_conv_f32(\r\n  float32_t * pSrcA,\r\n  uint32_t srcALen,\r\n  float32_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  float32_t * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Convolution of Q15 sequences.\r\n   * @param[in]  pSrcA      points to the first input sequence.\r\n   * @param[in]  srcALen    length of the first input sequence.\r\n   * @param[in]  pSrcB      points to the second input sequence.\r\n   * @param[in]  srcBLen    length of the second input sequence.\r\n   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.\r\n   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r\n   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).\r\n   */\r\n  void arm_conv_opt_q15(\r\n  q15_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q15_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q15_t * pDst,\r\n  q15_t * pScratch1,\r\n  q15_t * pScratch2);\r\n\r\n\r\n/**\r\n * @brief Convolution of Q15 sequences.\r\n * @param[in]  pSrcA    points to the first input sequence.\r\n * @param[in]  srcALen  length of the first input sequence.\r\n * @param[in]  pSrcB    points to the second input sequence.\r\n * @param[in]  srcBLen  length of the second input sequence.\r\n * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.\r\n */\r\n  void arm_conv_q15(\r\n  q15_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q15_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q15_t * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r\n   * @param[in]  pSrcA    points to the first input sequence.\r\n   * @param[in]  srcALen  length of the first input sequence.\r\n   * @param[in]  pSrcB    points to the second input sequence.\r\n   * @param[in]  srcBLen  length of the second input sequence.\r\n   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.\r\n   */\r\n  void arm_conv_fast_q15(\r\n          q15_t * pSrcA,\r\n          uint32_t srcALen,\r\n          q15_t * pSrcB,\r\n          uint32_t srcBLen,\r\n          q15_t * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r\n   * @param[in]  pSrcA      points to the first input sequence.\r\n   * @param[in]  srcALen    length of the first input sequence.\r\n   * @param[in]  pSrcB      points to the second input sequence.\r\n   * @param[in]  srcBLen    length of the second input sequence.\r\n   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.\r\n   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r\n   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).\r\n   */\r\n  void arm_conv_fast_opt_q15(\r\n  q15_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q15_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q15_t * pDst,\r\n  q15_t * pScratch1,\r\n  q15_t * pScratch2);\r\n\r\n\r\n  /**\r\n   * @brief Convolution of Q31 sequences.\r\n   * @param[in]  pSrcA    points to the first input sequence.\r\n   * @param[in]  srcALen  length of the first input sequence.\r\n   * @param[in]  pSrcB    points to the second input sequence.\r\n   * @param[in]  srcBLen  length of the second input sequence.\r\n   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.\r\n   */\r\n  void arm_conv_q31(\r\n  q31_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q31_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q31_t * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r\n   * @param[in]  pSrcA    points to the first input sequence.\r\n   * @param[in]  srcALen  length of the first input sequence.\r\n   * @param[in]  pSrcB    points to the second input sequence.\r\n   * @param[in]  srcBLen  length of the second input sequence.\r\n   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.\r\n   */\r\n  void arm_conv_fast_q31(\r\n  q31_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q31_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q31_t * pDst);\r\n\r\n\r\n    /**\r\n   * @brief Convolution of Q7 sequences.\r\n   * @param[in]  pSrcA      points to the first input sequence.\r\n   * @param[in]  srcALen    length of the first input sequence.\r\n   * @param[in]  pSrcB      points to the second input sequence.\r\n   * @param[in]  srcBLen    length of the second input sequence.\r\n   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.\r\n   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r\n   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\r\n   */\r\n  void arm_conv_opt_q7(\r\n  q7_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q7_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q7_t * pDst,\r\n  q15_t * pScratch1,\r\n  q15_t * pScratch2);\r\n\r\n\r\n  /**\r\n   * @brief Convolution of Q7 sequences.\r\n   * @param[in]  pSrcA    points to the first input sequence.\r\n   * @param[in]  srcALen  length of the first input sequence.\r\n   * @param[in]  pSrcB    points to the second input sequence.\r\n   * @param[in]  srcBLen  length of the second input sequence.\r\n   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.\r\n   */\r\n  void arm_conv_q7(\r\n  q7_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q7_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q7_t * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Partial convolution of floating-point sequences.\r\n   * @param[in]  pSrcA       points to the first input sequence.\r\n   * @param[in]  srcALen     length of the first input sequence.\r\n   * @param[in]  pSrcB       points to the second input sequence.\r\n   * @param[in]  srcBLen     length of the second input sequence.\r\n   * @param[out] pDst        points to the block of output data\r\n   * @param[in]  firstIndex  is the first output sample to start with.\r\n   * @param[in]  numPoints   is the number of output points to be computed.\r\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r\n   */\r\n  arm_status arm_conv_partial_f32(\r\n  float32_t * pSrcA,\r\n  uint32_t srcALen,\r\n  float32_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  float32_t * pDst,\r\n  uint32_t firstIndex,\r\n  uint32_t numPoints);\r\n\r\n\r\n  /**\r\n   * @brief Partial convolution of Q15 sequences.\r\n   * @param[in]  pSrcA       points to the first input sequence.\r\n   * @param[in]  srcALen     length of the first input sequence.\r\n   * @param[in]  pSrcB       points to the second input sequence.\r\n   * @param[in]  srcBLen     length of the second input sequence.\r\n   * @param[out] pDst        points to the block of output data\r\n   * @param[in]  firstIndex  is the first output sample to start with.\r\n   * @param[in]  numPoints   is the number of output points to be computed.\r\n   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r\n   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).\r\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r\n   */\r\n  arm_status arm_conv_partial_opt_q15(\r\n  q15_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q15_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q15_t * pDst,\r\n  uint32_t firstIndex,\r\n  uint32_t numPoints,\r\n  q15_t * pScratch1,\r\n  q15_t * pScratch2);\r\n\r\n\r\n  /**\r\n   * @brief Partial convolution of Q15 sequences.\r\n   * @param[in]  pSrcA       points to the first input sequence.\r\n   * @param[in]  srcALen     length of the first input sequence.\r\n   * @param[in]  pSrcB       points to the second input sequence.\r\n   * @param[in]  srcBLen     length of the second input sequence.\r\n   * @param[out] pDst        points to the block of output data\r\n   * @param[in]  firstIndex  is the first output sample to start with.\r\n   * @param[in]  numPoints   is the number of output points to be computed.\r\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r\n   */\r\n  arm_status arm_conv_partial_q15(\r\n  q15_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q15_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q15_t * pDst,\r\n  uint32_t firstIndex,\r\n  uint32_t numPoints);\r\n\r\n\r\n  /**\r\n   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r\n   * @param[in]  pSrcA       points to the first input sequence.\r\n   * @param[in]  srcALen     length of the first input sequence.\r\n   * @param[in]  pSrcB       points to the second input sequence.\r\n   * @param[in]  srcBLen     length of the second input sequence.\r\n   * @param[out] pDst        points to the block of output data\r\n   * @param[in]  firstIndex  is the first output sample to start with.\r\n   * @param[in]  numPoints   is the number of output points to be computed.\r\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r\n   */\r\n  arm_status arm_conv_partial_fast_q15(\r\n  q15_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q15_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q15_t * pDst,\r\n  uint32_t firstIndex,\r\n  uint32_t numPoints);\r\n\r\n\r\n  /**\r\n   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r\n   * @param[in]  pSrcA       points to the first input sequence.\r\n   * @param[in]  srcALen     length of the first input sequence.\r\n   * @param[in]  pSrcB       points to the second input sequence.\r\n   * @param[in]  srcBLen     length of the second input sequence.\r\n   * @param[out] pDst        points to the block of output data\r\n   * @param[in]  firstIndex  is the first output sample to start with.\r\n   * @param[in]  numPoints   is the number of output points to be computed.\r\n   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r\n   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).\r\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r\n   */\r\n  arm_status arm_conv_partial_fast_opt_q15(\r\n  q15_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q15_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q15_t * pDst,\r\n  uint32_t firstIndex,\r\n  uint32_t numPoints,\r\n  q15_t * pScratch1,\r\n  q15_t * pScratch2);\r\n\r\n\r\n  /**\r\n   * @brief Partial convolution of Q31 sequences.\r\n   * @param[in]  pSrcA       points to the first input sequence.\r\n   * @param[in]  srcALen     length of the first input sequence.\r\n   * @param[in]  pSrcB       points to the second input sequence.\r\n   * @param[in]  srcBLen     length of the second input sequence.\r\n   * @param[out] pDst        points to the block of output data\r\n   * @param[in]  firstIndex  is the first output sample to start with.\r\n   * @param[in]  numPoints   is the number of output points to be computed.\r\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r\n   */\r\n  arm_status arm_conv_partial_q31(\r\n  q31_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q31_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q31_t * pDst,\r\n  uint32_t firstIndex,\r\n  uint32_t numPoints);\r\n\r\n\r\n  /**\r\n   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r\n   * @param[in]  pSrcA       points to the first input sequence.\r\n   * @param[in]  srcALen     length of the first input sequence.\r\n   * @param[in]  pSrcB       points to the second input sequence.\r\n   * @param[in]  srcBLen     length of the second input sequence.\r\n   * @param[out] pDst        points to the block of output data\r\n   * @param[in]  firstIndex  is the first output sample to start with.\r\n   * @param[in]  numPoints   is the number of output points to be computed.\r\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r\n   */\r\n  arm_status arm_conv_partial_fast_q31(\r\n  q31_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q31_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q31_t * pDst,\r\n  uint32_t firstIndex,\r\n  uint32_t numPoints);\r\n\r\n\r\n  /**\r\n   * @brief Partial convolution of Q7 sequences\r\n   * @param[in]  pSrcA       points to the first input sequence.\r\n   * @param[in]  srcALen     length of the first input sequence.\r\n   * @param[in]  pSrcB       points to the second input sequence.\r\n   * @param[in]  srcBLen     length of the second input sequence.\r\n   * @param[out] pDst        points to the block of output data\r\n   * @param[in]  firstIndex  is the first output sample to start with.\r\n   * @param[in]  numPoints   is the number of output points to be computed.\r\n   * @param[in]  pScratch1   points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r\n   * @param[in]  pScratch2   points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\r\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r\n   */\r\n  arm_status arm_conv_partial_opt_q7(\r\n  q7_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q7_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q7_t * pDst,\r\n  uint32_t firstIndex,\r\n  uint32_t numPoints,\r\n  q15_t * pScratch1,\r\n  q15_t * pScratch2);\r\n\r\n\r\n/**\r\n   * @brief Partial convolution of Q7 sequences.\r\n   * @param[in]  pSrcA       points to the first input sequence.\r\n   * @param[in]  srcALen     length of the first input sequence.\r\n   * @param[in]  pSrcB       points to the second input sequence.\r\n   * @param[in]  srcBLen     length of the second input sequence.\r\n   * @param[out] pDst        points to the block of output data\r\n   * @param[in]  firstIndex  is the first output sample to start with.\r\n   * @param[in]  numPoints   is the number of output points to be computed.\r\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r\n   */\r\n  arm_status arm_conv_partial_q7(\r\n  q7_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q7_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q7_t * pDst,\r\n  uint32_t firstIndex,\r\n  uint32_t numPoints);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the Q15 FIR decimator.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint8_t M;                  /**< decimation factor. */\r\n    uint16_t numTaps;           /**< number of coefficients in the filter. */\r\n    q15_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/\r\n    q15_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n  } arm_fir_decimate_instance_q15;\r\n\r\n  /**\r\n   * @brief Instance structure for the Q31 FIR decimator.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint8_t M;                  /**< decimation factor. */\r\n    uint16_t numTaps;           /**< number of coefficients in the filter. */\r\n    q31_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/\r\n    q31_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n  } arm_fir_decimate_instance_q31;\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point FIR decimator.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint8_t M;                  /**< decimation factor. */\r\n    uint16_t numTaps;           /**< number of coefficients in the filter. */\r\n    float32_t *pCoeffs;         /**< points to the coefficient array. The array is of length numTaps.*/\r\n    float32_t *pState;          /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n  } arm_fir_decimate_instance_f32;\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the floating-point FIR decimator.\r\n   * @param[in]  S          points to an instance of the floating-point FIR decimator structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data\r\n   * @param[in]  blockSize  number of input samples to process per call.\r\n   */\r\n  void arm_fir_decimate_f32(\r\n  const arm_fir_decimate_instance_f32 * S,\r\n  float32_t * pSrc,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the floating-point FIR decimator.\r\n   * @param[in,out] S          points to an instance of the floating-point FIR decimator structure.\r\n   * @param[in]     numTaps    number of coefficients in the filter.\r\n   * @param[in]     M          decimation factor.\r\n   * @param[in]     pCoeffs    points to the filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   * @param[in]     blockSize  number of input samples to process per call.\r\n   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r\n   * <code>blockSize</code> is not a multiple of <code>M</code>.\r\n   */\r\n  arm_status arm_fir_decimate_init_f32(\r\n  arm_fir_decimate_instance_f32 * S,\r\n  uint16_t numTaps,\r\n  uint8_t M,\r\n  float32_t * pCoeffs,\r\n  float32_t * pState,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q15 FIR decimator.\r\n   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data\r\n   * @param[in]  blockSize  number of input samples to process per call.\r\n   */\r\n  void arm_fir_decimate_q15(\r\n  const arm_fir_decimate_instance_q15 * S,\r\n  q15_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\r\n   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data\r\n   * @param[in]  blockSize  number of input samples to process per call.\r\n   */\r\n  void arm_fir_decimate_fast_q15(\r\n  const arm_fir_decimate_instance_q15 * S,\r\n  q15_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the Q15 FIR decimator.\r\n   * @param[in,out] S          points to an instance of the Q15 FIR decimator structure.\r\n   * @param[in]     numTaps    number of coefficients in the filter.\r\n   * @param[in]     M          decimation factor.\r\n   * @param[in]     pCoeffs    points to the filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   * @param[in]     blockSize  number of input samples to process per call.\r\n   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r\n   * <code>blockSize</code> is not a multiple of <code>M</code>.\r\n   */\r\n  arm_status arm_fir_decimate_init_q15(\r\n  arm_fir_decimate_instance_q15 * S,\r\n  uint16_t numTaps,\r\n  uint8_t M,\r\n  q15_t * pCoeffs,\r\n  q15_t * pState,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q31 FIR decimator.\r\n   * @param[in]  S     points to an instance of the Q31 FIR decimator structure.\r\n   * @param[in]  pSrc  points to the block of input data.\r\n   * @param[out] pDst  points to the block of output data\r\n   * @param[in] blockSize number of input samples to process per call.\r\n   */\r\n  void arm_fir_decimate_q31(\r\n  const arm_fir_decimate_instance_q31 * S,\r\n  q31_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n  /**\r\n   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\r\n   * @param[in]  S          points to an instance of the Q31 FIR decimator structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data\r\n   * @param[in]  blockSize  number of input samples to process per call.\r\n   */\r\n  void arm_fir_decimate_fast_q31(\r\n  arm_fir_decimate_instance_q31 * S,\r\n  q31_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the Q31 FIR decimator.\r\n   * @param[in,out] S          points to an instance of the Q31 FIR decimator structure.\r\n   * @param[in]     numTaps    number of coefficients in the filter.\r\n   * @param[in]     M          decimation factor.\r\n   * @param[in]     pCoeffs    points to the filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   * @param[in]     blockSize  number of input samples to process per call.\r\n   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r\n   * <code>blockSize</code> is not a multiple of <code>M</code>.\r\n   */\r\n  arm_status arm_fir_decimate_init_q31(\r\n  arm_fir_decimate_instance_q31 * S,\r\n  uint16_t numTaps,\r\n  uint8_t M,\r\n  q31_t * pCoeffs,\r\n  q31_t * pState,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the Q15 FIR interpolator.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint8_t L;                      /**< upsample factor. */\r\n    uint16_t phaseLength;           /**< length of each polyphase filter component. */\r\n    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */\r\n    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\r\n  } arm_fir_interpolate_instance_q15;\r\n\r\n  /**\r\n   * @brief Instance structure for the Q31 FIR interpolator.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint8_t L;                      /**< upsample factor. */\r\n    uint16_t phaseLength;           /**< length of each polyphase filter component. */\r\n    q31_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */\r\n    q31_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\r\n  } arm_fir_interpolate_instance_q31;\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point FIR interpolator.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint8_t L;                     /**< upsample factor. */\r\n    uint16_t phaseLength;          /**< length of each polyphase filter component. */\r\n    float32_t *pCoeffs;            /**< points to the coefficient array. The array is of length L*phaseLength. */\r\n    float32_t *pState;             /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */\r\n  } arm_fir_interpolate_instance_f32;\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q15 FIR interpolator.\r\n   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of input samples to process per call.\r\n   */\r\n  void arm_fir_interpolate_q15(\r\n  const arm_fir_interpolate_instance_q15 * S,\r\n  q15_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the Q15 FIR interpolator.\r\n   * @param[in,out] S          points to an instance of the Q15 FIR interpolator structure.\r\n   * @param[in]     L          upsample factor.\r\n   * @param[in]     numTaps    number of filter coefficients in the filter.\r\n   * @param[in]     pCoeffs    points to the filter coefficient buffer.\r\n   * @param[in]     pState     points to the state buffer.\r\n   * @param[in]     blockSize  number of input samples to process per call.\r\n   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r\n   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r\n   */\r\n  arm_status arm_fir_interpolate_init_q15(\r\n  arm_fir_interpolate_instance_q15 * S,\r\n  uint8_t L,\r\n  uint16_t numTaps,\r\n  q15_t * pCoeffs,\r\n  q15_t * pState,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q31 FIR interpolator.\r\n   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of input samples to process per call.\r\n   */\r\n  void arm_fir_interpolate_q31(\r\n  const arm_fir_interpolate_instance_q31 * S,\r\n  q31_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the Q31 FIR interpolator.\r\n   * @param[in,out] S          points to an instance of the Q31 FIR interpolator structure.\r\n   * @param[in]     L          upsample factor.\r\n   * @param[in]     numTaps    number of filter coefficients in the filter.\r\n   * @param[in]     pCoeffs    points to the filter coefficient buffer.\r\n   * @param[in]     pState     points to the state buffer.\r\n   * @param[in]     blockSize  number of input samples to process per call.\r\n   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r\n   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r\n   */\r\n  arm_status arm_fir_interpolate_init_q31(\r\n  arm_fir_interpolate_instance_q31 * S,\r\n  uint8_t L,\r\n  uint16_t numTaps,\r\n  q31_t * pCoeffs,\r\n  q31_t * pState,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the floating-point FIR interpolator.\r\n   * @param[in]  S          points to an instance of the floating-point FIR interpolator structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of input samples to process per call.\r\n   */\r\n  void arm_fir_interpolate_f32(\r\n  const arm_fir_interpolate_instance_f32 * S,\r\n  float32_t * pSrc,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the floating-point FIR interpolator.\r\n   * @param[in,out] S          points to an instance of the floating-point FIR interpolator structure.\r\n   * @param[in]     L          upsample factor.\r\n   * @param[in]     numTaps    number of filter coefficients in the filter.\r\n   * @param[in]     pCoeffs    points to the filter coefficient buffer.\r\n   * @param[in]     pState     points to the state buffer.\r\n   * @param[in]     blockSize  number of input samples to process per call.\r\n   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r\n   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r\n   */\r\n  arm_status arm_fir_interpolate_init_f32(\r\n  arm_fir_interpolate_instance_f32 * S,\r\n  uint8_t L,\r\n  uint16_t numTaps,\r\n  float32_t * pCoeffs,\r\n  float32_t * pState,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the high precision Q31 Biquad cascade filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */\r\n    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */\r\n    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */\r\n    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */\r\n  } arm_biquad_cas_df1_32x64_ins_q31;\r\n\r\n\r\n  /**\r\n   * @param[in]  S          points to an instance of the high precision Q31 Biquad cascade filter structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_biquad_cas_df1_32x64_q31(\r\n  const arm_biquad_cas_df1_32x64_ins_q31 * S,\r\n  q31_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @param[in,out] S          points to an instance of the high precision Q31 Biquad cascade filter structure.\r\n   * @param[in]     numStages  number of 2nd order stages in the filter.\r\n   * @param[in]     pCoeffs    points to the filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   * @param[in]     postShift  shift to be applied to the output. Varies according to the coefficients format\r\n   */\r\n  void arm_biquad_cas_df1_32x64_init_q31(\r\n  arm_biquad_cas_df1_32x64_ins_q31 * S,\r\n  uint8_t numStages,\r\n  q31_t * pCoeffs,\r\n  q63_t * pState,\r\n  uint8_t postShift);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */\r\n    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */\r\n    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */\r\n  } arm_biquad_cascade_df2T_instance_f32;\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */\r\n    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */\r\n    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */\r\n  } arm_biquad_cascade_stereo_df2T_instance_f32;\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */\r\n    float64_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */\r\n    float64_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */\r\n  } arm_biquad_cascade_df2T_instance_f64;\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.\r\n   * @param[in]  S          points to an instance of the filter data structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_biquad_cascade_df2T_f32(\r\n  const arm_biquad_cascade_df2T_instance_f32 * S,\r\n  float32_t * pSrc,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels\r\n   * @param[in]  S          points to an instance of the filter data structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_biquad_cascade_stereo_df2T_f32(\r\n  const arm_biquad_cascade_stereo_df2T_instance_f32 * S,\r\n  float32_t * pSrc,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.\r\n   * @param[in]  S          points to an instance of the filter data structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_biquad_cascade_df2T_f64(\r\n  const arm_biquad_cascade_df2T_instance_f64 * S,\r\n  float64_t * pSrc,\r\n  float64_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r\n   * @param[in,out] S          points to an instance of the filter data structure.\r\n   * @param[in]     numStages  number of 2nd order stages in the filter.\r\n   * @param[in]     pCoeffs    points to the filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   */\r\n  void arm_biquad_cascade_df2T_init_f32(\r\n  arm_biquad_cascade_df2T_instance_f32 * S,\r\n  uint8_t numStages,\r\n  float32_t * pCoeffs,\r\n  float32_t * pState);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r\n   * @param[in,out] S          points to an instance of the filter data structure.\r\n   * @param[in]     numStages  number of 2nd order stages in the filter.\r\n   * @param[in]     pCoeffs    points to the filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   */\r\n  void arm_biquad_cascade_stereo_df2T_init_f32(\r\n  arm_biquad_cascade_stereo_df2T_instance_f32 * S,\r\n  uint8_t numStages,\r\n  float32_t * pCoeffs,\r\n  float32_t * pState);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r\n   * @param[in,out] S          points to an instance of the filter data structure.\r\n   * @param[in]     numStages  number of 2nd order stages in the filter.\r\n   * @param[in]     pCoeffs    points to the filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   */\r\n  void arm_biquad_cascade_df2T_init_f64(\r\n  arm_biquad_cascade_df2T_instance_f64 * S,\r\n  uint8_t numStages,\r\n  float64_t * pCoeffs,\r\n  float64_t * pState);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the Q15 FIR lattice filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numStages;                  /**< number of filter stages. */\r\n    q15_t *pState;                       /**< points to the state variable array. The array is of length numStages. */\r\n    q15_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */\r\n  } arm_fir_lattice_instance_q15;\r\n\r\n  /**\r\n   * @brief Instance structure for the Q31 FIR lattice filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numStages;                  /**< number of filter stages. */\r\n    q31_t *pState;                       /**< points to the state variable array. The array is of length numStages. */\r\n    q31_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */\r\n  } arm_fir_lattice_instance_q31;\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point FIR lattice filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numStages;                  /**< number of filter stages. */\r\n    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */\r\n    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */\r\n  } arm_fir_lattice_instance_f32;\r\n\r\n\r\n  /**\r\n   * @brief Initialization function for the Q15 FIR lattice filter.\r\n   * @param[in] S          points to an instance of the Q15 FIR lattice structure.\r\n   * @param[in] numStages  number of filter stages.\r\n   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.\r\n   * @param[in] pState     points to the state buffer.  The array is of length numStages.\r\n   */\r\n  void arm_fir_lattice_init_q15(\r\n  arm_fir_lattice_instance_q15 * S,\r\n  uint16_t numStages,\r\n  q15_t * pCoeffs,\r\n  q15_t * pState);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q15 FIR lattice filter.\r\n   * @param[in]  S          points to an instance of the Q15 FIR lattice structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_fir_lattice_q15(\r\n  const arm_fir_lattice_instance_q15 * S,\r\n  q15_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Initialization function for the Q31 FIR lattice filter.\r\n   * @param[in] S          points to an instance of the Q31 FIR lattice structure.\r\n   * @param[in] numStages  number of filter stages.\r\n   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.\r\n   * @param[in] pState     points to the state buffer.   The array is of length numStages.\r\n   */\r\n  void arm_fir_lattice_init_q31(\r\n  arm_fir_lattice_instance_q31 * S,\r\n  uint16_t numStages,\r\n  q31_t * pCoeffs,\r\n  q31_t * pState);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q31 FIR lattice filter.\r\n   * @param[in]  S          points to an instance of the Q31 FIR lattice structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_fir_lattice_q31(\r\n  const arm_fir_lattice_instance_q31 * S,\r\n  q31_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n/**\r\n * @brief Initialization function for the floating-point FIR lattice filter.\r\n * @param[in] S          points to an instance of the floating-point FIR lattice structure.\r\n * @param[in] numStages  number of filter stages.\r\n * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.\r\n * @param[in] pState     points to the state buffer.  The array is of length numStages.\r\n */\r\n  void arm_fir_lattice_init_f32(\r\n  arm_fir_lattice_instance_f32 * S,\r\n  uint16_t numStages,\r\n  float32_t * pCoeffs,\r\n  float32_t * pState);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the floating-point FIR lattice filter.\r\n   * @param[in]  S          points to an instance of the floating-point FIR lattice structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_fir_lattice_f32(\r\n  const arm_fir_lattice_instance_f32 * S,\r\n  float32_t * pSrc,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the Q15 IIR lattice filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numStages;                  /**< number of stages in the filter. */\r\n    q15_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */\r\n    q15_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */\r\n    q15_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */\r\n  } arm_iir_lattice_instance_q15;\r\n\r\n  /**\r\n   * @brief Instance structure for the Q31 IIR lattice filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numStages;                  /**< number of stages in the filter. */\r\n    q31_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */\r\n    q31_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */\r\n    q31_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */\r\n  } arm_iir_lattice_instance_q31;\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point IIR lattice filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numStages;                  /**< number of stages in the filter. */\r\n    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages+blockSize. */\r\n    float32_t *pkCoeffs;                 /**< points to the reflection coefficient array. The array is of length numStages. */\r\n    float32_t *pvCoeffs;                 /**< points to the ladder coefficient array. The array is of length numStages+1. */\r\n  } arm_iir_lattice_instance_f32;\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the floating-point IIR lattice filter.\r\n   * @param[in]  S          points to an instance of the floating-point IIR lattice structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_iir_lattice_f32(\r\n  const arm_iir_lattice_instance_f32 * S,\r\n  float32_t * pSrc,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Initialization function for the floating-point IIR lattice filter.\r\n   * @param[in] S          points to an instance of the floating-point IIR lattice structure.\r\n   * @param[in] numStages  number of stages in the filter.\r\n   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.\r\n   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.\r\n   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize-1.\r\n   * @param[in] blockSize  number of samples to process.\r\n   */\r\n  void arm_iir_lattice_init_f32(\r\n  arm_iir_lattice_instance_f32 * S,\r\n  uint16_t numStages,\r\n  float32_t * pkCoeffs,\r\n  float32_t * pvCoeffs,\r\n  float32_t * pState,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q31 IIR lattice filter.\r\n   * @param[in]  S          points to an instance of the Q31 IIR lattice structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_iir_lattice_q31(\r\n  const arm_iir_lattice_instance_q31 * S,\r\n  q31_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Initialization function for the Q31 IIR lattice filter.\r\n   * @param[in] S          points to an instance of the Q31 IIR lattice structure.\r\n   * @param[in] numStages  number of stages in the filter.\r\n   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.\r\n   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.\r\n   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize.\r\n   * @param[in] blockSize  number of samples to process.\r\n   */\r\n  void arm_iir_lattice_init_q31(\r\n  arm_iir_lattice_instance_q31 * S,\r\n  uint16_t numStages,\r\n  q31_t * pkCoeffs,\r\n  q31_t * pvCoeffs,\r\n  q31_t * pState,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q15 IIR lattice filter.\r\n   * @param[in]  S          points to an instance of the Q15 IIR lattice structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_iir_lattice_q15(\r\n  const arm_iir_lattice_instance_q15 * S,\r\n  q15_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n/**\r\n * @brief Initialization function for the Q15 IIR lattice filter.\r\n * @param[in] S          points to an instance of the fixed-point Q15 IIR lattice structure.\r\n * @param[in] numStages  number of stages in the filter.\r\n * @param[in] pkCoeffs   points to reflection coefficient buffer.  The array is of length numStages.\r\n * @param[in] pvCoeffs   points to ladder coefficient buffer.  The array is of length numStages+1.\r\n * @param[in] pState     points to state buffer.  The array is of length numStages+blockSize.\r\n * @param[in] blockSize  number of samples to process per call.\r\n */\r\n  void arm_iir_lattice_init_q15(\r\n  arm_iir_lattice_instance_q15 * S,\r\n  uint16_t numStages,\r\n  q15_t * pkCoeffs,\r\n  q15_t * pvCoeffs,\r\n  q15_t * pState,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point LMS filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numTaps;    /**< number of coefficients in the filter. */\r\n    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */\r\n    float32_t mu;        /**< step size that controls filter coefficient updates. */\r\n  } arm_lms_instance_f32;\r\n\r\n\r\n  /**\r\n   * @brief Processing function for floating-point LMS filter.\r\n   * @param[in]  S          points to an instance of the floating-point LMS filter structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[in]  pRef       points to the block of reference data.\r\n   * @param[out] pOut       points to the block of output data.\r\n   * @param[out] pErr       points to the block of error data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_lms_f32(\r\n  const arm_lms_instance_f32 * S,\r\n  float32_t * pSrc,\r\n  float32_t * pRef,\r\n  float32_t * pOut,\r\n  float32_t * pErr,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Initialization function for floating-point LMS filter.\r\n   * @param[in] S          points to an instance of the floating-point LMS filter structure.\r\n   * @param[in] numTaps    number of filter coefficients.\r\n   * @param[in] pCoeffs    points to the coefficient buffer.\r\n   * @param[in] pState     points to state buffer.\r\n   * @param[in] mu         step size that controls filter coefficient updates.\r\n   * @param[in] blockSize  number of samples to process.\r\n   */\r\n  void arm_lms_init_f32(\r\n  arm_lms_instance_f32 * S,\r\n  uint16_t numTaps,\r\n  float32_t * pCoeffs,\r\n  float32_t * pState,\r\n  float32_t mu,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the Q15 LMS filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numTaps;    /**< number of coefficients in the filter. */\r\n    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */\r\n    q15_t mu;            /**< step size that controls filter coefficient updates. */\r\n    uint32_t postShift;  /**< bit shift applied to coefficients. */\r\n  } arm_lms_instance_q15;\r\n\r\n\r\n  /**\r\n   * @brief Initialization function for the Q15 LMS filter.\r\n   * @param[in] S          points to an instance of the Q15 LMS filter structure.\r\n   * @param[in] numTaps    number of filter coefficients.\r\n   * @param[in] pCoeffs    points to the coefficient buffer.\r\n   * @param[in] pState     points to the state buffer.\r\n   * @param[in] mu         step size that controls filter coefficient updates.\r\n   * @param[in] blockSize  number of samples to process.\r\n   * @param[in] postShift  bit shift applied to coefficients.\r\n   */\r\n  void arm_lms_init_q15(\r\n  arm_lms_instance_q15 * S,\r\n  uint16_t numTaps,\r\n  q15_t * pCoeffs,\r\n  q15_t * pState,\r\n  q15_t mu,\r\n  uint32_t blockSize,\r\n  uint32_t postShift);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for Q15 LMS filter.\r\n   * @param[in]  S          points to an instance of the Q15 LMS filter structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[in]  pRef       points to the block of reference data.\r\n   * @param[out] pOut       points to the block of output data.\r\n   * @param[out] pErr       points to the block of error data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_lms_q15(\r\n  const arm_lms_instance_q15 * S,\r\n  q15_t * pSrc,\r\n  q15_t * pRef,\r\n  q15_t * pOut,\r\n  q15_t * pErr,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the Q31 LMS filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numTaps;    /**< number of coefficients in the filter. */\r\n    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */\r\n    q31_t mu;            /**< step size that controls filter coefficient updates. */\r\n    uint32_t postShift;  /**< bit shift applied to coefficients. */\r\n  } arm_lms_instance_q31;\r\n\r\n\r\n  /**\r\n   * @brief Processing function for Q31 LMS filter.\r\n   * @param[in]  S          points to an instance of the Q15 LMS filter structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[in]  pRef       points to the block of reference data.\r\n   * @param[out] pOut       points to the block of output data.\r\n   * @param[out] pErr       points to the block of error data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_lms_q31(\r\n  const arm_lms_instance_q31 * S,\r\n  q31_t * pSrc,\r\n  q31_t * pRef,\r\n  q31_t * pOut,\r\n  q31_t * pErr,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Initialization function for Q31 LMS filter.\r\n   * @param[in] S          points to an instance of the Q31 LMS filter structure.\r\n   * @param[in] numTaps    number of filter coefficients.\r\n   * @param[in] pCoeffs    points to coefficient buffer.\r\n   * @param[in] pState     points to state buffer.\r\n   * @param[in] mu         step size that controls filter coefficient updates.\r\n   * @param[in] blockSize  number of samples to process.\r\n   * @param[in] postShift  bit shift applied to coefficients.\r\n   */\r\n  void arm_lms_init_q31(\r\n  arm_lms_instance_q31 * S,\r\n  uint16_t numTaps,\r\n  q31_t * pCoeffs,\r\n  q31_t * pState,\r\n  q31_t mu,\r\n  uint32_t blockSize,\r\n  uint32_t postShift);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point normalized LMS filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numTaps;     /**< number of coefficients in the filter. */\r\n    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */\r\n    float32_t mu;         /**< step size that control filter coefficient updates. */\r\n    float32_t energy;     /**< saves previous frame energy. */\r\n    float32_t x0;         /**< saves previous input sample. */\r\n  } arm_lms_norm_instance_f32;\r\n\r\n\r\n  /**\r\n   * @brief Processing function for floating-point normalized LMS filter.\r\n   * @param[in]  S          points to an instance of the floating-point normalized LMS filter structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[in]  pRef       points to the block of reference data.\r\n   * @param[out] pOut       points to the block of output data.\r\n   * @param[out] pErr       points to the block of error data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_lms_norm_f32(\r\n  arm_lms_norm_instance_f32 * S,\r\n  float32_t * pSrc,\r\n  float32_t * pRef,\r\n  float32_t * pOut,\r\n  float32_t * pErr,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Initialization function for floating-point normalized LMS filter.\r\n   * @param[in] S          points to an instance of the floating-point LMS filter structure.\r\n   * @param[in] numTaps    number of filter coefficients.\r\n   * @param[in] pCoeffs    points to coefficient buffer.\r\n   * @param[in] pState     points to state buffer.\r\n   * @param[in] mu         step size that controls filter coefficient updates.\r\n   * @param[in] blockSize  number of samples to process.\r\n   */\r\n  void arm_lms_norm_init_f32(\r\n  arm_lms_norm_instance_f32 * S,\r\n  uint16_t numTaps,\r\n  float32_t * pCoeffs,\r\n  float32_t * pState,\r\n  float32_t mu,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the Q31 normalized LMS filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numTaps;     /**< number of coefficients in the filter. */\r\n    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */\r\n    q31_t mu;             /**< step size that controls filter coefficient updates. */\r\n    uint8_t postShift;    /**< bit shift applied to coefficients. */\r\n    q31_t *recipTable;    /**< points to the reciprocal initial value table. */\r\n    q31_t energy;         /**< saves previous frame energy. */\r\n    q31_t x0;             /**< saves previous input sample. */\r\n  } arm_lms_norm_instance_q31;\r\n\r\n\r\n  /**\r\n   * @brief Processing function for Q31 normalized LMS filter.\r\n   * @param[in]  S          points to an instance of the Q31 normalized LMS filter structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[in]  pRef       points to the block of reference data.\r\n   * @param[out] pOut       points to the block of output data.\r\n   * @param[out] pErr       points to the block of error data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_lms_norm_q31(\r\n  arm_lms_norm_instance_q31 * S,\r\n  q31_t * pSrc,\r\n  q31_t * pRef,\r\n  q31_t * pOut,\r\n  q31_t * pErr,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Initialization function for Q31 normalized LMS filter.\r\n   * @param[in] S          points to an instance of the Q31 normalized LMS filter structure.\r\n   * @param[in] numTaps    number of filter coefficients.\r\n   * @param[in] pCoeffs    points to coefficient buffer.\r\n   * @param[in] pState     points to state buffer.\r\n   * @param[in] mu         step size that controls filter coefficient updates.\r\n   * @param[in] blockSize  number of samples to process.\r\n   * @param[in] postShift  bit shift applied to coefficients.\r\n   */\r\n  void arm_lms_norm_init_q31(\r\n  arm_lms_norm_instance_q31 * S,\r\n  uint16_t numTaps,\r\n  q31_t * pCoeffs,\r\n  q31_t * pState,\r\n  q31_t mu,\r\n  uint32_t blockSize,\r\n  uint8_t postShift);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the Q15 normalized LMS filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numTaps;     /**< Number of coefficients in the filter. */\r\n    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */\r\n    q15_t mu;             /**< step size that controls filter coefficient updates. */\r\n    uint8_t postShift;    /**< bit shift applied to coefficients. */\r\n    q15_t *recipTable;    /**< Points to the reciprocal initial value table. */\r\n    q15_t energy;         /**< saves previous frame energy. */\r\n    q15_t x0;             /**< saves previous input sample. */\r\n  } arm_lms_norm_instance_q15;\r\n\r\n\r\n  /**\r\n   * @brief Processing function for Q15 normalized LMS filter.\r\n   * @param[in]  S          points to an instance of the Q15 normalized LMS filter structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[in]  pRef       points to the block of reference data.\r\n   * @param[out] pOut       points to the block of output data.\r\n   * @param[out] pErr       points to the block of error data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_lms_norm_q15(\r\n  arm_lms_norm_instance_q15 * S,\r\n  q15_t * pSrc,\r\n  q15_t * pRef,\r\n  q15_t * pOut,\r\n  q15_t * pErr,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Initialization function for Q15 normalized LMS filter.\r\n   * @param[in] S          points to an instance of the Q15 normalized LMS filter structure.\r\n   * @param[in] numTaps    number of filter coefficients.\r\n   * @param[in] pCoeffs    points to coefficient buffer.\r\n   * @param[in] pState     points to state buffer.\r\n   * @param[in] mu         step size that controls filter coefficient updates.\r\n   * @param[in] blockSize  number of samples to process.\r\n   * @param[in] postShift  bit shift applied to coefficients.\r\n   */\r\n  void arm_lms_norm_init_q15(\r\n  arm_lms_norm_instance_q15 * S,\r\n  uint16_t numTaps,\r\n  q15_t * pCoeffs,\r\n  q15_t * pState,\r\n  q15_t mu,\r\n  uint32_t blockSize,\r\n  uint8_t postShift);\r\n\r\n\r\n  /**\r\n   * @brief Correlation of floating-point sequences.\r\n   * @param[in]  pSrcA    points to the first input sequence.\r\n   * @param[in]  srcALen  length of the first input sequence.\r\n   * @param[in]  pSrcB    points to the second input sequence.\r\n   * @param[in]  srcBLen  length of the second input sequence.\r\n   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\r\n   */\r\n  void arm_correlate_f32(\r\n  float32_t * pSrcA,\r\n  uint32_t srcALen,\r\n  float32_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  float32_t * pDst);\r\n\r\n\r\n   /**\r\n   * @brief Correlation of Q15 sequences\r\n   * @param[in]  pSrcA     points to the first input sequence.\r\n   * @param[in]  srcALen   length of the first input sequence.\r\n   * @param[in]  pSrcB     points to the second input sequence.\r\n   * @param[in]  srcBLen   length of the second input sequence.\r\n   * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\r\n   * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r\n   */\r\n  void arm_correlate_opt_q15(\r\n  q15_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q15_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q15_t * pDst,\r\n  q15_t * pScratch);\r\n\r\n\r\n  /**\r\n   * @brief Correlation of Q15 sequences.\r\n   * @param[in]  pSrcA    points to the first input sequence.\r\n   * @param[in]  srcALen  length of the first input sequence.\r\n   * @param[in]  pSrcB    points to the second input sequence.\r\n   * @param[in]  srcBLen  length of the second input sequence.\r\n   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\r\n   */\r\n\r\n  void arm_correlate_q15(\r\n  q15_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q15_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q15_t * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.\r\n   * @param[in]  pSrcA    points to the first input sequence.\r\n   * @param[in]  srcALen  length of the first input sequence.\r\n   * @param[in]  pSrcB    points to the second input sequence.\r\n   * @param[in]  srcBLen  length of the second input sequence.\r\n   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\r\n   */\r\n\r\n  void arm_correlate_fast_q15(\r\n  q15_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q15_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q15_t * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.\r\n   * @param[in]  pSrcA     points to the first input sequence.\r\n   * @param[in]  srcALen   length of the first input sequence.\r\n   * @param[in]  pSrcB     points to the second input sequence.\r\n   * @param[in]  srcBLen   length of the second input sequence.\r\n   * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\r\n   * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r\n   */\r\n  void arm_correlate_fast_opt_q15(\r\n  q15_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q15_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q15_t * pDst,\r\n  q15_t * pScratch);\r\n\r\n\r\n  /**\r\n   * @brief Correlation of Q31 sequences.\r\n   * @param[in]  pSrcA    points to the first input sequence.\r\n   * @param[in]  srcALen  length of the first input sequence.\r\n   * @param[in]  pSrcB    points to the second input sequence.\r\n   * @param[in]  srcBLen  length of the second input sequence.\r\n   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\r\n   */\r\n  void arm_correlate_q31(\r\n  q31_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q31_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q31_t * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r\n   * @param[in]  pSrcA    points to the first input sequence.\r\n   * @param[in]  srcALen  length of the first input sequence.\r\n   * @param[in]  pSrcB    points to the second input sequence.\r\n   * @param[in]  srcBLen  length of the second input sequence.\r\n   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\r\n   */\r\n  void arm_correlate_fast_q31(\r\n  q31_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q31_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q31_t * pDst);\r\n\r\n\r\n /**\r\n   * @brief Correlation of Q7 sequences.\r\n   * @param[in]  pSrcA      points to the first input sequence.\r\n   * @param[in]  srcALen    length of the first input sequence.\r\n   * @param[in]  pSrcB      points to the second input sequence.\r\n   * @param[in]  srcBLen    length of the second input sequence.\r\n   * @param[out] pDst       points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\r\n   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r\n   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\r\n   */\r\n  void arm_correlate_opt_q7(\r\n  q7_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q7_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q7_t * pDst,\r\n  q15_t * pScratch1,\r\n  q15_t * pScratch2);\r\n\r\n\r\n  /**\r\n   * @brief Correlation of Q7 sequences.\r\n   * @param[in]  pSrcA    points to the first input sequence.\r\n   * @param[in]  srcALen  length of the first input sequence.\r\n   * @param[in]  pSrcB    points to the second input sequence.\r\n   * @param[in]  srcBLen  length of the second input sequence.\r\n   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\r\n   */\r\n  void arm_correlate_q7(\r\n  q7_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q7_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q7_t * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point sparse FIR filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numTaps;             /**< number of coefficients in the filter. */\r\n    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */\r\n    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r\n    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/\r\n    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */\r\n    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */\r\n  } arm_fir_sparse_instance_f32;\r\n\r\n  /**\r\n   * @brief Instance structure for the Q31 sparse FIR filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numTaps;             /**< number of coefficients in the filter. */\r\n    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */\r\n    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r\n    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/\r\n    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */\r\n    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */\r\n  } arm_fir_sparse_instance_q31;\r\n\r\n  /**\r\n   * @brief Instance structure for the Q15 sparse FIR filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numTaps;             /**< number of coefficients in the filter. */\r\n    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */\r\n    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r\n    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/\r\n    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */\r\n    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */\r\n  } arm_fir_sparse_instance_q15;\r\n\r\n  /**\r\n   * @brief Instance structure for the Q7 sparse FIR filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numTaps;             /**< number of coefficients in the filter. */\r\n    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */\r\n    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r\n    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/\r\n    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */\r\n    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */\r\n  } arm_fir_sparse_instance_q7;\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the floating-point sparse FIR filter.\r\n   * @param[in]  S           points to an instance of the floating-point sparse FIR structure.\r\n   * @param[in]  pSrc        points to the block of input data.\r\n   * @param[out] pDst        points to the block of output data\r\n   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.\r\n   * @param[in]  blockSize   number of input samples to process per call.\r\n   */\r\n  void arm_fir_sparse_f32(\r\n  arm_fir_sparse_instance_f32 * S,\r\n  float32_t * pSrc,\r\n  float32_t * pDst,\r\n  float32_t * pScratchIn,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the floating-point sparse FIR filter.\r\n   * @param[in,out] S          points to an instance of the floating-point sparse FIR structure.\r\n   * @param[in]     numTaps    number of nonzero coefficients in the filter.\r\n   * @param[in]     pCoeffs    points to the array of filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   * @param[in]     pTapDelay  points to the array of offset times.\r\n   * @param[in]     maxDelay   maximum offset time supported.\r\n   * @param[in]     blockSize  number of samples that will be processed per block.\r\n   */\r\n  void arm_fir_sparse_init_f32(\r\n  arm_fir_sparse_instance_f32 * S,\r\n  uint16_t numTaps,\r\n  float32_t * pCoeffs,\r\n  float32_t * pState,\r\n  int32_t * pTapDelay,\r\n  uint16_t maxDelay,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q31 sparse FIR filter.\r\n   * @param[in]  S           points to an instance of the Q31 sparse FIR structure.\r\n   * @param[in]  pSrc        points to the block of input data.\r\n   * @param[out] pDst        points to the block of output data\r\n   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.\r\n   * @param[in]  blockSize   number of input samples to process per call.\r\n   */\r\n  void arm_fir_sparse_q31(\r\n  arm_fir_sparse_instance_q31 * S,\r\n  q31_t * pSrc,\r\n  q31_t * pDst,\r\n  q31_t * pScratchIn,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the Q31 sparse FIR filter.\r\n   * @param[in,out] S          points to an instance of the Q31 sparse FIR structure.\r\n   * @param[in]     numTaps    number of nonzero coefficients in the filter.\r\n   * @param[in]     pCoeffs    points to the array of filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   * @param[in]     pTapDelay  points to the array of offset times.\r\n   * @param[in]     maxDelay   maximum offset time supported.\r\n   * @param[in]     blockSize  number of samples that will be processed per block.\r\n   */\r\n  void arm_fir_sparse_init_q31(\r\n  arm_fir_sparse_instance_q31 * S,\r\n  uint16_t numTaps,\r\n  q31_t * pCoeffs,\r\n  q31_t * pState,\r\n  int32_t * pTapDelay,\r\n  uint16_t maxDelay,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q15 sparse FIR filter.\r\n   * @param[in]  S            points to an instance of the Q15 sparse FIR structure.\r\n   * @param[in]  pSrc         points to the block of input data.\r\n   * @param[out] pDst         points to the block of output data\r\n   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.\r\n   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.\r\n   * @param[in]  blockSize    number of input samples to process per call.\r\n   */\r\n  void arm_fir_sparse_q15(\r\n  arm_fir_sparse_instance_q15 * S,\r\n  q15_t * pSrc,\r\n  q15_t * pDst,\r\n  q15_t * pScratchIn,\r\n  q31_t * pScratchOut,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the Q15 sparse FIR filter.\r\n   * @param[in,out] S          points to an instance of the Q15 sparse FIR structure.\r\n   * @param[in]     numTaps    number of nonzero coefficients in the filter.\r\n   * @param[in]     pCoeffs    points to the array of filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   * @param[in]     pTapDelay  points to the array of offset times.\r\n   * @param[in]     maxDelay   maximum offset time supported.\r\n   * @param[in]     blockSize  number of samples that will be processed per block.\r\n   */\r\n  void arm_fir_sparse_init_q15(\r\n  arm_fir_sparse_instance_q15 * S,\r\n  uint16_t numTaps,\r\n  q15_t * pCoeffs,\r\n  q15_t * pState,\r\n  int32_t * pTapDelay,\r\n  uint16_t maxDelay,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q7 sparse FIR filter.\r\n   * @param[in]  S            points to an instance of the Q7 sparse FIR structure.\r\n   * @param[in]  pSrc         points to the block of input data.\r\n   * @param[out] pDst         points to the block of output data\r\n   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.\r\n   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.\r\n   * @param[in]  blockSize    number of input samples to process per call.\r\n   */\r\n  void arm_fir_sparse_q7(\r\n  arm_fir_sparse_instance_q7 * S,\r\n  q7_t * pSrc,\r\n  q7_t * pDst,\r\n  q7_t * pScratchIn,\r\n  q31_t * pScratchOut,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the Q7 sparse FIR filter.\r\n   * @param[in,out] S          points to an instance of the Q7 sparse FIR structure.\r\n   * @param[in]     numTaps    number of nonzero coefficients in the filter.\r\n   * @param[in]     pCoeffs    points to the array of filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   * @param[in]     pTapDelay  points to the array of offset times.\r\n   * @param[in]     maxDelay   maximum offset time supported.\r\n   * @param[in]     blockSize  number of samples that will be processed per block.\r\n   */\r\n  void arm_fir_sparse_init_q7(\r\n  arm_fir_sparse_instance_q7 * S,\r\n  uint16_t numTaps,\r\n  q7_t * pCoeffs,\r\n  q7_t * pState,\r\n  int32_t * pTapDelay,\r\n  uint16_t maxDelay,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Floating-point sin_cos function.\r\n   * @param[in]  theta   input value in degrees\r\n   * @param[out] pSinVal  points to the processed sine output.\r\n   * @param[out] pCosVal  points to the processed cos output.\r\n   */\r\n  void arm_sin_cos_f32(\r\n  float32_t theta,\r\n  float32_t * pSinVal,\r\n  float32_t * pCosVal);\r\n\r\n\r\n  /**\r\n   * @brief  Q31 sin_cos function.\r\n   * @param[in]  theta    scaled input value in degrees\r\n   * @param[out] pSinVal  points to the processed sine output.\r\n   * @param[out] pCosVal  points to the processed cosine output.\r\n   */\r\n  void arm_sin_cos_q31(\r\n  q31_t theta,\r\n  q31_t * pSinVal,\r\n  q31_t * pCosVal);\r\n\r\n\r\n  /**\r\n   * @brief  Floating-point complex conjugate.\r\n   * @param[in]  pSrc        points to the input vector\r\n   * @param[out] pDst        points to the output vector\r\n   * @param[in]  numSamples  number of complex samples in each vector\r\n   */\r\n  void arm_cmplx_conj_f32(\r\n  float32_t * pSrc,\r\n  float32_t * pDst,\r\n  uint32_t numSamples);\r\n\r\n  /**\r\n   * @brief  Q31 complex conjugate.\r\n   * @param[in]  pSrc        points to the input vector\r\n   * @param[out] pDst        points to the output vector\r\n   * @param[in]  numSamples  number of complex samples in each vector\r\n   */\r\n  void arm_cmplx_conj_q31(\r\n  q31_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t numSamples);\r\n\r\n\r\n  /**\r\n   * @brief  Q15 complex conjugate.\r\n   * @param[in]  pSrc        points to the input vector\r\n   * @param[out] pDst        points to the output vector\r\n   * @param[in]  numSamples  number of complex samples in each vector\r\n   */\r\n  void arm_cmplx_conj_q15(\r\n  q15_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t numSamples);\r\n\r\n\r\n  /**\r\n   * @brief  Floating-point complex magnitude squared\r\n   * @param[in]  pSrc        points to the complex input vector\r\n   * @param[out] pDst        points to the real output vector\r\n   * @param[in]  numSamples  number of complex samples in the input vector\r\n   */\r\n  void arm_cmplx_mag_squared_f32(\r\n  float32_t * pSrc,\r\n  float32_t * pDst,\r\n  uint32_t numSamples);\r\n\r\n\r\n  /**\r\n   * @brief  Q31 complex magnitude squared\r\n   * @param[in]  pSrc        points to the complex input vector\r\n   * @param[out] pDst        points to the real output vector\r\n   * @param[in]  numSamples  number of complex samples in the input vector\r\n   */\r\n  void arm_cmplx_mag_squared_q31(\r\n  q31_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t numSamples);\r\n\r\n\r\n  /**\r\n   * @brief  Q15 complex magnitude squared\r\n   * @param[in]  pSrc        points to the complex input vector\r\n   * @param[out] pDst        points to the real output vector\r\n   * @param[in]  numSamples  number of complex samples in the input vector\r\n   */\r\n  void arm_cmplx_mag_squared_q15(\r\n  q15_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t numSamples);\r\n\r\n\r\n /**\r\n   * @ingroup groupController\r\n   */\r\n\r\n  /**\r\n   * @defgroup PID PID Motor Control\r\n   *\r\n   * A Proportional Integral Derivative (PID) controller is a generic feedback control\r\n   * loop mechanism widely used in industrial control systems.\r\n   * A PID controller is the most commonly used type of feedback controller.\r\n   *\r\n   * This set of functions implements (PID) controllers\r\n   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample\r\n   * of data and each call to the function returns a single processed value.\r\n   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>\r\n   * is the input sample value. The functions return the output value.\r\n   *\r\n   * \\par Algorithm:\r\n   * <pre>\r\n   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]\r\n   *    A0 = Kp + Ki + Kd\r\n   *    A1 = (-Kp ) - (2 * Kd )\r\n   *    A2 = Kd  </pre>\r\n   *\r\n   * \\par\r\n   * where \\c Kp is proportional constant, \\c Ki is Integral constant and \\c Kd is Derivative constant\r\n   *\r\n   * \\par\r\n   * \\image html PID.gif \"Proportional Integral Derivative Controller\"\r\n   *\r\n   * \\par\r\n   * The PID controller calculates an \"error\" value as the difference between\r\n   * the measured output and the reference input.\r\n   * The controller attempts to minimize the error by adjusting the process control inputs.\r\n   * The proportional value determines the reaction to the current error,\r\n   * the integral value determines the reaction based on the sum of recent errors,\r\n   * and the derivative value determines the reaction based on the rate at which the error has been changing.\r\n   *\r\n   * \\par Instance Structure\r\n   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.\r\n   * A separate instance structure must be defined for each PID Controller.\r\n   * There are separate instance structure declarations for each of the 3 supported data types.\r\n   *\r\n   * \\par Reset Functions\r\n   * There is also an associated reset function for each data type which clears the state array.\r\n   *\r\n   * \\par Initialization Functions\r\n   * There is also an associated initialization function for each data type.\r\n   * The initialization function performs the following operations:\r\n   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.\r\n   * - Zeros out the values in the state buffer.\r\n   *\r\n   * \\par\r\n   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.\r\n   *\r\n   * \\par Fixed-Point Behavior\r\n   * Care must be taken when using the fixed-point versions of the PID Controller functions.\r\n   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.\r\n   * Refer to the function specific documentation below for usage guidelines.\r\n   */\r\n\r\n  /**\r\n   * @addtogroup PID\r\n   * @{\r\n   */\r\n\r\n  /**\r\n   * @brief  Process function for the floating-point PID Control.\r\n   * @param[in,out] S   is an instance of the floating-point PID Control structure\r\n   * @param[in]     in  input sample to process\r\n   * @return out processed output sample.\r\n   */\r\n  static __INLINE float32_t arm_pid_f32(\r\n  arm_pid_instance_f32 * S,\r\n  float32_t in)\r\n  {\r\n    float32_t out;\r\n\r\n    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */\r\n    out = (S->A0 * in) +\r\n      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);\r\n\r\n    /* Update state */\r\n    S->state[1] = S->state[0];\r\n    S->state[0] = in;\r\n    S->state[2] = out;\r\n\r\n    /* return to application */\r\n    return (out);\r\n\r\n  }\r\n\r\n  /**\r\n   * @brief  Process function for the Q31 PID Control.\r\n   * @param[in,out] S  points to an instance of the Q31 PID Control structure\r\n   * @param[in]     in  input sample to process\r\n   * @return out processed output sample.\r\n   *\r\n   * <b>Scaling and Overflow Behavior:</b>\r\n   * \\par\r\n   * The function is implemented using an internal 64-bit accumulator.\r\n   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.\r\n   * Thus, if the accumulator result overflows it wraps around rather than clip.\r\n   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.\r\n   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.\r\n   */\r\n  static __INLINE q31_t arm_pid_q31(\r\n  arm_pid_instance_q31 * S,\r\n  q31_t in)\r\n  {\r\n    q63_t acc;\r\n    q31_t out;\r\n\r\n    /* acc = A0 * x[n]  */\r\n    acc = (q63_t) S->A0 * in;\r\n\r\n    /* acc += A1 * x[n-1] */\r\n    acc += (q63_t) S->A1 * S->state[0];\r\n\r\n    /* acc += A2 * x[n-2]  */\r\n    acc += (q63_t) S->A2 * S->state[1];\r\n\r\n    /* convert output to 1.31 format to add y[n-1] */\r\n    out = (q31_t) (acc >> 31u);\r\n\r\n    /* out += y[n-1] */\r\n    out += S->state[2];\r\n\r\n    /* Update state */\r\n    S->state[1] = S->state[0];\r\n    S->state[0] = in;\r\n    S->state[2] = out;\r\n\r\n    /* return to application */\r\n    return (out);\r\n  }\r\n\r\n\r\n  /**\r\n   * @brief  Process function for the Q15 PID Control.\r\n   * @param[in,out] S   points to an instance of the Q15 PID Control structure\r\n   * @param[in]     in  input sample to process\r\n   * @return out processed output sample.\r\n   *\r\n   * <b>Scaling and Overflow Behavior:</b>\r\n   * \\par\r\n   * The function is implemented using a 64-bit internal accumulator.\r\n   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.\r\n   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.\r\n   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.\r\n   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.\r\n   * Lastly, the accumulator is saturated to yield a result in 1.15 format.\r\n   */\r\n  static __INLINE q15_t arm_pid_q15(\r\n  arm_pid_instance_q15 * S,\r\n  q15_t in)\r\n  {\r\n    q63_t acc;\r\n    q15_t out;\r\n\r\n#ifndef ARM_MATH_CM0_FAMILY\r\n    __SIMD32_TYPE *vstate;\r\n\r\n    /* Implementation of PID controller */\r\n\r\n    /* acc = A0 * x[n]  */\r\n    acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);\r\n\r\n    /* acc += A1 * x[n-1] + A2 * x[n-2]  */\r\n    vstate = __SIMD32_CONST(S->state);\r\n    acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);\r\n#else\r\n    /* acc = A0 * x[n]  */\r\n    acc = ((q31_t) S->A0) * in;\r\n\r\n    /* acc += A1 * x[n-1] + A2 * x[n-2]  */\r\n    acc += (q31_t) S->A1 * S->state[0];\r\n    acc += (q31_t) S->A2 * S->state[1];\r\n#endif\r\n\r\n    /* acc += y[n-1] */\r\n    acc += (q31_t) S->state[2] << 15;\r\n\r\n    /* saturate the output */\r\n    out = (q15_t) (__SSAT((acc >> 15), 16));\r\n\r\n    /* Update state */\r\n    S->state[1] = S->state[0];\r\n    S->state[0] = in;\r\n    S->state[2] = out;\r\n\r\n    /* return to application */\r\n    return (out);\r\n  }\r\n\r\n  /**\r\n   * @} end of PID group\r\n   */\r\n\r\n\r\n  /**\r\n   * @brief Floating-point matrix inverse.\r\n   * @param[in]  src   points to the instance of the input floating-point matrix structure.\r\n   * @param[out] dst   points to the instance of the output floating-point matrix structure.\r\n   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.\r\n   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.\r\n   */\r\n  arm_status arm_mat_inverse_f32(\r\n  const arm_matrix_instance_f32 * src,\r\n  arm_matrix_instance_f32 * dst);\r\n\r\n\r\n  /**\r\n   * @brief Floating-point matrix inverse.\r\n   * @param[in]  src   points to the instance of the input floating-point matrix structure.\r\n   * @param[out] dst   points to the instance of the output floating-point matrix structure.\r\n   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.\r\n   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.\r\n   */\r\n  arm_status arm_mat_inverse_f64(\r\n  const arm_matrix_instance_f64 * src,\r\n  arm_matrix_instance_f64 * dst);\r\n\r\n\r\n\r\n  /**\r\n   * @ingroup groupController\r\n   */\r\n\r\n  /**\r\n   * @defgroup clarke Vector Clarke Transform\r\n   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.\r\n   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents\r\n   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.\r\n   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below\r\n   * \\image html clarke.gif Stator current space vector and its components in (a,b).\r\n   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>\r\n   * can be calculated using only <code>Ia</code> and <code>Ib</code>.\r\n   *\r\n   * The function operates on a single sample of data and each call to the function returns the processed output.\r\n   * The library provides separate functions for Q31 and floating-point data types.\r\n   * \\par Algorithm\r\n   * \\image html clarkeFormula.gif\r\n   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and\r\n   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.\r\n   * \\par Fixed-Point Behavior\r\n   * Care must be taken when using the Q31 version of the Clarke transform.\r\n   * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r\n   * Refer to the function specific documentation below for usage guidelines.\r\n   */\r\n\r\n  /**\r\n   * @addtogroup clarke\r\n   * @{\r\n   */\r\n\r\n  /**\r\n   *\r\n   * @brief  Floating-point Clarke transform\r\n   * @param[in]  Ia       input three-phase coordinate <code>a</code>\r\n   * @param[in]  Ib       input three-phase coordinate <code>b</code>\r\n   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha\r\n   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta\r\n   */\r\n  static __INLINE void arm_clarke_f32(\r\n  float32_t Ia,\r\n  float32_t Ib,\r\n  float32_t * pIalpha,\r\n  float32_t * pIbeta)\r\n  {\r\n    /* Calculate pIalpha using the equation, pIalpha = Ia */\r\n    *pIalpha = Ia;\r\n\r\n    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */\r\n    *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);\r\n  }\r\n\r\n\r\n  /**\r\n   * @brief  Clarke transform for Q31 version\r\n   * @param[in]  Ia       input three-phase coordinate <code>a</code>\r\n   * @param[in]  Ib       input three-phase coordinate <code>b</code>\r\n   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha\r\n   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta\r\n   *\r\n   * <b>Scaling and Overflow Behavior:</b>\r\n   * \\par\r\n   * The function is implemented using an internal 32-bit accumulator.\r\n   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r\n   * There is saturation on the addition, hence there is no risk of overflow.\r\n   */\r\n  static __INLINE void arm_clarke_q31(\r\n  q31_t Ia,\r\n  q31_t Ib,\r\n  q31_t * pIalpha,\r\n  q31_t * pIbeta)\r\n  {\r\n    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */\r\n\r\n    /* Calculating pIalpha from Ia by equation pIalpha = Ia */\r\n    *pIalpha = Ia;\r\n\r\n    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */\r\n    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);\r\n\r\n    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */\r\n    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);\r\n\r\n    /* pIbeta is calculated by adding the intermediate products */\r\n    *pIbeta = __QADD(product1, product2);\r\n  }\r\n\r\n  /**\r\n   * @} end of clarke group\r\n   */\r\n\r\n  /**\r\n   * @brief  Converts the elements of the Q7 vector to Q31 vector.\r\n   * @param[in]  pSrc       input pointer\r\n   * @param[out] pDst       output pointer\r\n   * @param[in]  blockSize  number of samples to process\r\n   */\r\n  void arm_q7_to_q31(\r\n  q7_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n\r\n  /**\r\n   * @ingroup groupController\r\n   */\r\n\r\n  /**\r\n   * @defgroup inv_clarke Vector Inverse Clarke Transform\r\n   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.\r\n   *\r\n   * The function operates on a single sample of data and each call to the function returns the processed output.\r\n   * The library provides separate functions for Q31 and floating-point data types.\r\n   * \\par Algorithm\r\n   * \\image html clarkeInvFormula.gif\r\n   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and\r\n   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.\r\n   * \\par Fixed-Point Behavior\r\n   * Care must be taken when using the Q31 version of the Clarke transform.\r\n   * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r\n   * Refer to the function specific documentation below for usage guidelines.\r\n   */\r\n\r\n  /**\r\n   * @addtogroup inv_clarke\r\n   * @{\r\n   */\r\n\r\n   /**\r\n   * @brief  Floating-point Inverse Clarke transform\r\n   * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha\r\n   * @param[in]  Ibeta   input two-phase orthogonal vector axis beta\r\n   * @param[out] pIa     points to output three-phase coordinate <code>a</code>\r\n   * @param[out] pIb     points to output three-phase coordinate <code>b</code>\r\n   */\r\n  static __INLINE void arm_inv_clarke_f32(\r\n  float32_t Ialpha,\r\n  float32_t Ibeta,\r\n  float32_t * pIa,\r\n  float32_t * pIb)\r\n  {\r\n    /* Calculating pIa from Ialpha by equation pIa = Ialpha */\r\n    *pIa = Ialpha;\r\n\r\n    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */\r\n    *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;\r\n  }\r\n\r\n\r\n  /**\r\n   * @brief  Inverse Clarke transform for Q31 version\r\n   * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha\r\n   * @param[in]  Ibeta   input two-phase orthogonal vector axis beta\r\n   * @param[out] pIa     points to output three-phase coordinate <code>a</code>\r\n   * @param[out] pIb     points to output three-phase coordinate <code>b</code>\r\n   *\r\n   * <b>Scaling and Overflow Behavior:</b>\r\n   * \\par\r\n   * The function is implemented using an internal 32-bit accumulator.\r\n   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r\n   * There is saturation on the subtraction, hence there is no risk of overflow.\r\n   */\r\n  static __INLINE void arm_inv_clarke_q31(\r\n  q31_t Ialpha,\r\n  q31_t Ibeta,\r\n  q31_t * pIa,\r\n  q31_t * pIb)\r\n  {\r\n    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */\r\n\r\n    /* Calculating pIa from Ialpha by equation pIa = Ialpha */\r\n    *pIa = Ialpha;\r\n\r\n    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */\r\n    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);\r\n\r\n    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */\r\n    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);\r\n\r\n    /* pIb is calculated by subtracting the products */\r\n    *pIb = __QSUB(product2, product1);\r\n  }\r\n\r\n  /**\r\n   * @} end of inv_clarke group\r\n   */\r\n\r\n  /**\r\n   * @brief  Converts the elements of the Q7 vector to Q15 vector.\r\n   * @param[in]  pSrc       input pointer\r\n   * @param[out] pDst       output pointer\r\n   * @param[in]  blockSize  number of samples to process\r\n   */\r\n  void arm_q7_to_q15(\r\n  q7_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n\r\n  /**\r\n   * @ingroup groupController\r\n   */\r\n\r\n  /**\r\n   * @defgroup park Vector Park Transform\r\n   *\r\n   * Forward Park transform converts the input two-coordinate vector to flux and torque components.\r\n   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents\r\n   * from the stationary to the moving reference frame and control the spatial relationship between\r\n   * the stator vector current and rotor flux vector.\r\n   * If we consider the d axis aligned with the rotor flux, the diagram below shows the\r\n   * current vector and the relationship from the two reference frames:\r\n   * \\image html park.gif \"Stator current space vector and its component in (a,b) and in the d,q rotating reference frame\"\r\n   *\r\n   * The function operates on a single sample of data and each call to the function returns the processed output.\r\n   * The library provides separate functions for Q31 and floating-point data types.\r\n   * \\par Algorithm\r\n   * \\image html parkFormula.gif\r\n   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,\r\n   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the\r\n   * cosine and sine values of theta (rotor flux position).\r\n   * \\par Fixed-Point Behavior\r\n   * Care must be taken when using the Q31 version of the Park transform.\r\n   * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r\n   * Refer to the function specific documentation below for usage guidelines.\r\n   */\r\n\r\n  /**\r\n   * @addtogroup park\r\n   * @{\r\n   */\r\n\r\n  /**\r\n   * @brief Floating-point Park transform\r\n   * @param[in]  Ialpha  input two-phase vector coordinate alpha\r\n   * @param[in]  Ibeta   input two-phase vector coordinate beta\r\n   * @param[out] pId     points to output   rotor reference frame d\r\n   * @param[out] pIq     points to output   rotor reference frame q\r\n   * @param[in]  sinVal  sine value of rotation angle theta\r\n   * @param[in]  cosVal  cosine value of rotation angle theta\r\n   *\r\n   * The function implements the forward Park transform.\r\n   *\r\n   */\r\n  static __INLINE void arm_park_f32(\r\n  float32_t Ialpha,\r\n  float32_t Ibeta,\r\n  float32_t * pId,\r\n  float32_t * pIq,\r\n  float32_t sinVal,\r\n  float32_t cosVal)\r\n  {\r\n    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */\r\n    *pId = Ialpha * cosVal + Ibeta * sinVal;\r\n\r\n    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */\r\n    *pIq = -Ialpha * sinVal + Ibeta * cosVal;\r\n  }\r\n\r\n\r\n  /**\r\n   * @brief  Park transform for Q31 version\r\n   * @param[in]  Ialpha  input two-phase vector coordinate alpha\r\n   * @param[in]  Ibeta   input two-phase vector coordinate beta\r\n   * @param[out] pId     points to output rotor reference frame d\r\n   * @param[out] pIq     points to output rotor reference frame q\r\n   * @param[in]  sinVal  sine value of rotation angle theta\r\n   * @param[in]  cosVal  cosine value of rotation angle theta\r\n   *\r\n   * <b>Scaling and Overflow Behavior:</b>\r\n   * \\par\r\n   * The function is implemented using an internal 32-bit accumulator.\r\n   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r\n   * There is saturation on the addition and subtraction, hence there is no risk of overflow.\r\n   */\r\n  static __INLINE void arm_park_q31(\r\n  q31_t Ialpha,\r\n  q31_t Ibeta,\r\n  q31_t * pId,\r\n  q31_t * pIq,\r\n  q31_t sinVal,\r\n  q31_t cosVal)\r\n  {\r\n    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */\r\n    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */\r\n\r\n    /* Intermediate product is calculated by (Ialpha * cosVal) */\r\n    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);\r\n\r\n    /* Intermediate product is calculated by (Ibeta * sinVal) */\r\n    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);\r\n\r\n\r\n    /* Intermediate product is calculated by (Ialpha * sinVal) */\r\n    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);\r\n\r\n    /* Intermediate product is calculated by (Ibeta * cosVal) */\r\n    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);\r\n\r\n    /* Calculate pId by adding the two intermediate products 1 and 2 */\r\n    *pId = __QADD(product1, product2);\r\n\r\n    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */\r\n    *pIq = __QSUB(product4, product3);\r\n  }\r\n\r\n  /**\r\n   * @} end of park group\r\n   */\r\n\r\n  /**\r\n   * @brief  Converts the elements of the Q7 vector to floating-point vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[out] pDst       is output pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   */\r\n  void arm_q7_to_float(\r\n  q7_t * pSrc,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @ingroup groupController\r\n   */\r\n\r\n  /**\r\n   * @defgroup inv_park Vector Inverse Park transform\r\n   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.\r\n   *\r\n   * The function operates on a single sample of data and each call to the function returns the processed output.\r\n   * The library provides separate functions for Q31 and floating-point data types.\r\n   * \\par Algorithm\r\n   * \\image html parkInvFormula.gif\r\n   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,\r\n   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the\r\n   * cosine and sine values of theta (rotor flux position).\r\n   * \\par Fixed-Point Behavior\r\n   * Care must be taken when using the Q31 version of the Park transform.\r\n   * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r\n   * Refer to the function specific documentation below for usage guidelines.\r\n   */\r\n\r\n  /**\r\n   * @addtogroup inv_park\r\n   * @{\r\n   */\r\n\r\n   /**\r\n   * @brief  Floating-point Inverse Park transform\r\n   * @param[in]  Id       input coordinate of rotor reference frame d\r\n   * @param[in]  Iq       input coordinate of rotor reference frame q\r\n   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha\r\n   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta\r\n   * @param[in]  sinVal   sine value of rotation angle theta\r\n   * @param[in]  cosVal   cosine value of rotation angle theta\r\n   */\r\n  static __INLINE void arm_inv_park_f32(\r\n  float32_t Id,\r\n  float32_t Iq,\r\n  float32_t * pIalpha,\r\n  float32_t * pIbeta,\r\n  float32_t sinVal,\r\n  float32_t cosVal)\r\n  {\r\n    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */\r\n    *pIalpha = Id * cosVal - Iq * sinVal;\r\n\r\n    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */\r\n    *pIbeta = Id * sinVal + Iq * cosVal;\r\n  }\r\n\r\n\r\n  /**\r\n   * @brief  Inverse Park transform for   Q31 version\r\n   * @param[in]  Id       input coordinate of rotor reference frame d\r\n   * @param[in]  Iq       input coordinate of rotor reference frame q\r\n   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha\r\n   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta\r\n   * @param[in]  sinVal   sine value of rotation angle theta\r\n   * @param[in]  cosVal   cosine value of rotation angle theta\r\n   *\r\n   * <b>Scaling and Overflow Behavior:</b>\r\n   * \\par\r\n   * The function is implemented using an internal 32-bit accumulator.\r\n   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r\n   * There is saturation on the addition, hence there is no risk of overflow.\r\n   */\r\n  static __INLINE void arm_inv_park_q31(\r\n  q31_t Id,\r\n  q31_t Iq,\r\n  q31_t * pIalpha,\r\n  q31_t * pIbeta,\r\n  q31_t sinVal,\r\n  q31_t cosVal)\r\n  {\r\n    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */\r\n    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */\r\n\r\n    /* Intermediate product is calculated by (Id * cosVal) */\r\n    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);\r\n\r\n    /* Intermediate product is calculated by (Iq * sinVal) */\r\n    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);\r\n\r\n\r\n    /* Intermediate product is calculated by (Id * sinVal) */\r\n    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);\r\n\r\n    /* Intermediate product is calculated by (Iq * cosVal) */\r\n    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);\r\n\r\n    /* Calculate pIalpha by using the two intermediate products 1 and 2 */\r\n    *pIalpha = __QSUB(product1, product2);\r\n\r\n    /* Calculate pIbeta by using the two intermediate products 3 and 4 */\r\n    *pIbeta = __QADD(product4, product3);\r\n  }\r\n\r\n  /**\r\n   * @} end of Inverse park group\r\n   */\r\n\r\n\r\n  /**\r\n   * @brief  Converts the elements of the Q31 vector to floating-point vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[out] pDst       is output pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   */\r\n  void arm_q31_to_float(\r\n  q31_t * pSrc,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n  /**\r\n   * @ingroup groupInterpolation\r\n   */\r\n\r\n  /**\r\n   * @defgroup LinearInterpolate Linear Interpolation\r\n   *\r\n   * Linear interpolation is a method of curve fitting using linear polynomials.\r\n   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line\r\n   *\r\n   * \\par\r\n   * \\image html LinearInterp.gif \"Linear interpolation\"\r\n   *\r\n   * \\par\r\n   * A  Linear Interpolate function calculates an output value(y), for the input(x)\r\n   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)\r\n   *\r\n   * \\par Algorithm:\r\n   * <pre>\r\n   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))\r\n   *       where x0, x1 are nearest values of input x\r\n   *             y0, y1 are nearest values to output y\r\n   * </pre>\r\n   *\r\n   * \\par\r\n   * This set of functions implements Linear interpolation process\r\n   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single\r\n   * sample of data and each call to the function returns a single processed value.\r\n   * <code>S</code> points to an instance of the Linear Interpolate function data structure.\r\n   * <code>x</code> is the input sample value. The functions returns the output value.\r\n   *\r\n   * \\par\r\n   * if x is outside of the table boundary, Linear interpolation returns first value of the table\r\n   * if x is below input range and returns last value of table if x is above range.\r\n   */\r\n\r\n  /**\r\n   * @addtogroup LinearInterpolate\r\n   * @{\r\n   */\r\n\r\n  /**\r\n   * @brief  Process function for the floating-point Linear Interpolation Function.\r\n   * @param[in,out] S  is an instance of the floating-point Linear Interpolation structure\r\n   * @param[in]     x  input sample to process\r\n   * @return y processed output sample.\r\n   *\r\n   */\r\n  static __INLINE float32_t arm_linear_interp_f32(\r\n  arm_linear_interp_instance_f32 * S,\r\n  float32_t x)\r\n  {\r\n    float32_t y;\r\n    float32_t x0, x1;                            /* Nearest input values */\r\n    float32_t y0, y1;                            /* Nearest output values */\r\n    float32_t xSpacing = S->xSpacing;            /* spacing between input values */\r\n    int32_t i;                                   /* Index variable */\r\n    float32_t *pYData = S->pYData;               /* pointer to output table */\r\n\r\n    /* Calculation of index */\r\n    i = (int32_t) ((x - S->x1) / xSpacing);\r\n\r\n    if(i < 0)\r\n    {\r\n      /* Iniatilize output for below specified range as least output value of table */\r\n      y = pYData[0];\r\n    }\r\n    else if((uint32_t)i >= S->nValues)\r\n    {\r\n      /* Iniatilize output for above specified range as last output value of table */\r\n      y = pYData[S->nValues - 1];\r\n    }\r\n    else\r\n    {\r\n      /* Calculation of nearest input values */\r\n      x0 = S->x1 +  i      * xSpacing;\r\n      x1 = S->x1 + (i + 1) * xSpacing;\r\n\r\n      /* Read of nearest output values */\r\n      y0 = pYData[i];\r\n      y1 = pYData[i + 1];\r\n\r\n      /* Calculation of output */\r\n      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));\r\n\r\n    }\r\n\r\n    /* returns output value */\r\n    return (y);\r\n  }\r\n\r\n\r\n   /**\r\n   *\r\n   * @brief  Process function for the Q31 Linear Interpolation Function.\r\n   * @param[in] pYData   pointer to Q31 Linear Interpolation table\r\n   * @param[in] x        input sample to process\r\n   * @param[in] nValues  number of table values\r\n   * @return y processed output sample.\r\n   *\r\n   * \\par\r\n   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r\n   * This function can support maximum of table size 2^12.\r\n   *\r\n   */\r\n  static __INLINE q31_t arm_linear_interp_q31(\r\n  q31_t * pYData,\r\n  q31_t x,\r\n  uint32_t nValues)\r\n  {\r\n    q31_t y;                                     /* output */\r\n    q31_t y0, y1;                                /* Nearest output values */\r\n    q31_t fract;                                 /* fractional part */\r\n    int32_t index;                               /* Index to read nearest output values */\r\n\r\n    /* Input is in 12.20 format */\r\n    /* 12 bits for the table index */\r\n    /* Index value calculation */\r\n    index = ((x & (q31_t)0xFFF00000) >> 20);\r\n\r\n    if(index >= (int32_t)(nValues - 1))\r\n    {\r\n      return (pYData[nValues - 1]);\r\n    }\r\n    else if(index < 0)\r\n    {\r\n      return (pYData[0]);\r\n    }\r\n    else\r\n    {\r\n      /* 20 bits for the fractional part */\r\n      /* shift left by 11 to keep fract in 1.31 format */\r\n      fract = (x & 0x000FFFFF) << 11;\r\n\r\n      /* Read two nearest output values from the index in 1.31(q31) format */\r\n      y0 = pYData[index];\r\n      y1 = pYData[index + 1];\r\n\r\n      /* Calculation of y0 * (1-fract) and y is in 2.30 format */\r\n      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));\r\n\r\n      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */\r\n      y += ((q31_t) (((q63_t) y1 * fract) >> 32));\r\n\r\n      /* Convert y to 1.31 format */\r\n      return (y << 1u);\r\n    }\r\n  }\r\n\r\n\r\n  /**\r\n   *\r\n   * @brief  Process function for the Q15 Linear Interpolation Function.\r\n   * @param[in] pYData   pointer to Q15 Linear Interpolation table\r\n   * @param[in] x        input sample to process\r\n   * @param[in] nValues  number of table values\r\n   * @return y processed output sample.\r\n   *\r\n   * \\par\r\n   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r\n   * This function can support maximum of table size 2^12.\r\n   *\r\n   */\r\n  static __INLINE q15_t arm_linear_interp_q15(\r\n  q15_t * pYData,\r\n  q31_t x,\r\n  uint32_t nValues)\r\n  {\r\n    q63_t y;                                     /* output */\r\n    q15_t y0, y1;                                /* Nearest output values */\r\n    q31_t fract;                                 /* fractional part */\r\n    int32_t index;                               /* Index to read nearest output values */\r\n\r\n    /* Input is in 12.20 format */\r\n    /* 12 bits for the table index */\r\n    /* Index value calculation */\r\n    index = ((x & (int32_t)0xFFF00000) >> 20);\r\n\r\n    if(index >= (int32_t)(nValues - 1))\r\n    {\r\n      return (pYData[nValues - 1]);\r\n    }\r\n    else if(index < 0)\r\n    {\r\n      return (pYData[0]);\r\n    }\r\n    else\r\n    {\r\n      /* 20 bits for the fractional part */\r\n      /* fract is in 12.20 format */\r\n      fract = (x & 0x000FFFFF);\r\n\r\n      /* Read two nearest output values from the index */\r\n      y0 = pYData[index];\r\n      y1 = pYData[index + 1];\r\n\r\n      /* Calculation of y0 * (1-fract) and y is in 13.35 format */\r\n      y = ((q63_t) y0 * (0xFFFFF - fract));\r\n\r\n      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */\r\n      y += ((q63_t) y1 * (fract));\r\n\r\n      /* convert y to 1.15 format */\r\n      return (q15_t) (y >> 20);\r\n    }\r\n  }\r\n\r\n\r\n  /**\r\n   *\r\n   * @brief  Process function for the Q7 Linear Interpolation Function.\r\n   * @param[in] pYData   pointer to Q7 Linear Interpolation table\r\n   * @param[in] x        input sample to process\r\n   * @param[in] nValues  number of table values\r\n   * @return y processed output sample.\r\n   *\r\n   * \\par\r\n   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r\n   * This function can support maximum of table size 2^12.\r\n   */\r\n  static __INLINE q7_t arm_linear_interp_q7(\r\n  q7_t * pYData,\r\n  q31_t x,\r\n  uint32_t nValues)\r\n  {\r\n    q31_t y;                                     /* output */\r\n    q7_t y0, y1;                                 /* Nearest output values */\r\n    q31_t fract;                                 /* fractional part */\r\n    uint32_t index;                              /* Index to read nearest output values */\r\n\r\n    /* Input is in 12.20 format */\r\n    /* 12 bits for the table index */\r\n    /* Index value calculation */\r\n    if (x < 0)\r\n    {\r\n      return (pYData[0]);\r\n    }\r\n    index = (x >> 20) & 0xfff;\r\n\r\n    if(index >= (nValues - 1))\r\n    {\r\n      return (pYData[nValues - 1]);\r\n    }\r\n    else\r\n    {\r\n      /* 20 bits for the fractional part */\r\n      /* fract is in 12.20 format */\r\n      fract = (x & 0x000FFFFF);\r\n\r\n      /* Read two nearest output values from the index and are in 1.7(q7) format */\r\n      y0 = pYData[index];\r\n      y1 = pYData[index + 1];\r\n\r\n      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */\r\n      y = ((y0 * (0xFFFFF - fract)));\r\n\r\n      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */\r\n      y += (y1 * fract);\r\n\r\n      /* convert y to 1.7(q7) format */\r\n      return (q7_t) (y >> 20);\r\n     }\r\n  }\r\n\r\n  /**\r\n   * @} end of LinearInterpolate group\r\n   */\r\n\r\n  /**\r\n   * @brief  Fast approximation to the trigonometric sine function for floating-point data.\r\n   * @param[in] x  input value in radians.\r\n   * @return  sin(x).\r\n   */\r\n  float32_t arm_sin_f32(\r\n  float32_t x);\r\n\r\n\r\n  /**\r\n   * @brief  Fast approximation to the trigonometric sine function for Q31 data.\r\n   * @param[in] x  Scaled input value in radians.\r\n   * @return  sin(x).\r\n   */\r\n  q31_t arm_sin_q31(\r\n  q31_t x);\r\n\r\n\r\n  /**\r\n   * @brief  Fast approximation to the trigonometric sine function for Q15 data.\r\n   * @param[in] x  Scaled input value in radians.\r\n   * @return  sin(x).\r\n   */\r\n  q15_t arm_sin_q15(\r\n  q15_t x);\r\n\r\n\r\n  /**\r\n   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.\r\n   * @param[in] x  input value in radians.\r\n   * @return  cos(x).\r\n   */\r\n  float32_t arm_cos_f32(\r\n  float32_t x);\r\n\r\n\r\n  /**\r\n   * @brief Fast approximation to the trigonometric cosine function for Q31 data.\r\n   * @param[in] x  Scaled input value in radians.\r\n   * @return  cos(x).\r\n   */\r\n  q31_t arm_cos_q31(\r\n  q31_t x);\r\n\r\n\r\n  /**\r\n   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.\r\n   * @param[in] x  Scaled input value in radians.\r\n   * @return  cos(x).\r\n   */\r\n  q15_t arm_cos_q15(\r\n  q15_t x);\r\n\r\n\r\n  /**\r\n   * @ingroup groupFastMath\r\n   */\r\n\r\n\r\n  /**\r\n   * @defgroup SQRT Square Root\r\n   *\r\n   * Computes the square root of a number.\r\n   * There are separate functions for Q15, Q31, and floating-point data types.\r\n   * The square root function is computed using the Newton-Raphson algorithm.\r\n   * This is an iterative algorithm of the form:\r\n   * <pre>\r\n   *      x1 = x0 - f(x0)/f'(x0)\r\n   * </pre>\r\n   * where <code>x1</code> is the current estimate,\r\n   * <code>x0</code> is the previous estimate, and\r\n   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.\r\n   * For the square root function, the algorithm reduces to:\r\n   * <pre>\r\n   *     x0 = in/2                         [initial guess]\r\n   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]\r\n   * </pre>\r\n   */\r\n\r\n\r\n  /**\r\n   * @addtogroup SQRT\r\n   * @{\r\n   */\r\n\r\n  /**\r\n   * @brief  Floating-point square root function.\r\n   * @param[in]  in    input value.\r\n   * @param[out] pOut  square root of input value.\r\n   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r\n   * <code>in</code> is negative value and returns zero output for negative values.\r\n   */\r\n  static __INLINE arm_status arm_sqrt_f32(\r\n  float32_t in,\r\n  float32_t * pOut)\r\n  {\r\n    if(in >= 0.0f)\r\n    {\r\n\r\n#if   (__FPU_USED == 1) && defined ( __CC_ARM   )\r\n      *pOut = __sqrtf(in);\r\n#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\r\n      *pOut = __builtin_sqrtf(in);\r\n#elif (__FPU_USED == 1) && defined(__GNUC__)\r\n      *pOut = __builtin_sqrtf(in);\r\n#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)\r\n      __ASM(\"VSQRT.F32 %0,%1\" : \"=t\"(*pOut) : \"t\"(in));\r\n#else\r\n      *pOut = sqrtf(in);\r\n#endif\r\n\r\n      return (ARM_MATH_SUCCESS);\r\n    }\r\n    else\r\n    {\r\n      *pOut = 0.0f;\r\n      return (ARM_MATH_ARGUMENT_ERROR);\r\n    }\r\n  }\r\n\r\n\r\n  /**\r\n   * @brief Q31 square root function.\r\n   * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.\r\n   * @param[out] pOut  square root of input value.\r\n   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r\n   * <code>in</code> is negative value and returns zero output for negative values.\r\n   */\r\n  arm_status arm_sqrt_q31(\r\n  q31_t in,\r\n  q31_t * pOut);\r\n\r\n\r\n  /**\r\n   * @brief  Q15 square root function.\r\n   * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.\r\n   * @param[out] pOut  square root of input value.\r\n   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r\n   * <code>in</code> is negative value and returns zero output for negative values.\r\n   */\r\n  arm_status arm_sqrt_q15(\r\n  q15_t in,\r\n  q15_t * pOut);\r\n\r\n  /**\r\n   * @} end of SQRT group\r\n   */\r\n\r\n\r\n  /**\r\n   * @brief floating-point Circular write function.\r\n   */\r\n  static __INLINE void arm_circularWrite_f32(\r\n  int32_t * circBuffer,\r\n  int32_t L,\r\n  uint16_t * writeOffset,\r\n  int32_t bufferInc,\r\n  const int32_t * src,\r\n  int32_t srcInc,\r\n  uint32_t blockSize)\r\n  {\r\n    uint32_t i = 0u;\r\n    int32_t wOffset;\r\n\r\n    /* Copy the value of Index pointer that points\r\n     * to the current location where the input samples to be copied */\r\n    wOffset = *writeOffset;\r\n\r\n    /* Loop over the blockSize */\r\n    i = blockSize;\r\n\r\n    while(i > 0u)\r\n    {\r\n      /* copy the input sample to the circular buffer */\r\n      circBuffer[wOffset] = *src;\r\n\r\n      /* Update the input pointer */\r\n      src += srcInc;\r\n\r\n      /* Circularly update wOffset.  Watch out for positive and negative value */\r\n      wOffset += bufferInc;\r\n      if(wOffset >= L)\r\n        wOffset -= L;\r\n\r\n      /* Decrement the loop counter */\r\n      i--;\r\n    }\r\n\r\n    /* Update the index pointer */\r\n    *writeOffset = (uint16_t)wOffset;\r\n  }\r\n\r\n\r\n\r\n  /**\r\n   * @brief floating-point Circular Read function.\r\n   */\r\n  static __INLINE void arm_circularRead_f32(\r\n  int32_t * circBuffer,\r\n  int32_t L,\r\n  int32_t * readOffset,\r\n  int32_t bufferInc,\r\n  int32_t * dst,\r\n  int32_t * dst_base,\r\n  int32_t dst_length,\r\n  int32_t dstInc,\r\n  uint32_t blockSize)\r\n  {\r\n    uint32_t i = 0u;\r\n    int32_t rOffset, dst_end;\r\n\r\n    /* Copy the value of Index pointer that points\r\n     * to the current location from where the input samples to be read */\r\n    rOffset = *readOffset;\r\n    dst_end = (int32_t) (dst_base + dst_length);\r\n\r\n    /* Loop over the blockSize */\r\n    i = blockSize;\r\n\r\n    while(i > 0u)\r\n    {\r\n      /* copy the sample from the circular buffer to the destination buffer */\r\n      *dst = circBuffer[rOffset];\r\n\r\n      /* Update the input pointer */\r\n      dst += dstInc;\r\n\r\n      if(dst == (int32_t *) dst_end)\r\n      {\r\n        dst = dst_base;\r\n      }\r\n\r\n      /* Circularly update rOffset.  Watch out for positive and negative value  */\r\n      rOffset += bufferInc;\r\n\r\n      if(rOffset >= L)\r\n      {\r\n        rOffset -= L;\r\n      }\r\n\r\n      /* Decrement the loop counter */\r\n      i--;\r\n    }\r\n\r\n    /* Update the index pointer */\r\n    *readOffset = rOffset;\r\n  }\r\n\r\n\r\n  /**\r\n   * @brief Q15 Circular write function.\r\n   */\r\n  static __INLINE void arm_circularWrite_q15(\r\n  q15_t * circBuffer,\r\n  int32_t L,\r\n  uint16_t * writeOffset,\r\n  int32_t bufferInc,\r\n  const q15_t * src,\r\n  int32_t srcInc,\r\n  uint32_t blockSize)\r\n  {\r\n    uint32_t i = 0u;\r\n    int32_t wOffset;\r\n\r\n    /* Copy the value of Index pointer that points\r\n     * to the current location where the input samples to be copied */\r\n    wOffset = *writeOffset;\r\n\r\n    /* Loop over the blockSize */\r\n    i = blockSize;\r\n\r\n    while(i > 0u)\r\n    {\r\n      /* copy the input sample to the circular buffer */\r\n      circBuffer[wOffset] = *src;\r\n\r\n      /* Update the input pointer */\r\n      src += srcInc;\r\n\r\n      /* Circularly update wOffset.  Watch out for positive and negative value */\r\n      wOffset += bufferInc;\r\n      if(wOffset >= L)\r\n        wOffset -= L;\r\n\r\n      /* Decrement the loop counter */\r\n      i--;\r\n    }\r\n\r\n    /* Update the index pointer */\r\n    *writeOffset = (uint16_t)wOffset;\r\n  }\r\n\r\n\r\n  /**\r\n   * @brief Q15 Circular Read function.\r\n   */\r\n  static __INLINE void arm_circularRead_q15(\r\n  q15_t * circBuffer,\r\n  int32_t L,\r\n  int32_t * readOffset,\r\n  int32_t bufferInc,\r\n  q15_t * dst,\r\n  q15_t * dst_base,\r\n  int32_t dst_length,\r\n  int32_t dstInc,\r\n  uint32_t blockSize)\r\n  {\r\n    uint32_t i = 0;\r\n    int32_t rOffset, dst_end;\r\n\r\n    /* Copy the value of Index pointer that points\r\n     * to the current location from where the input samples to be read */\r\n    rOffset = *readOffset;\r\n\r\n    dst_end = (int32_t) (dst_base + dst_length);\r\n\r\n    /* Loop over the blockSize */\r\n    i = blockSize;\r\n\r\n    while(i > 0u)\r\n    {\r\n      /* copy the sample from the circular buffer to the destination buffer */\r\n      *dst = circBuffer[rOffset];\r\n\r\n      /* Update the input pointer */\r\n      dst += dstInc;\r\n\r\n      if(dst == (q15_t *) dst_end)\r\n      {\r\n        dst = dst_base;\r\n      }\r\n\r\n      /* Circularly update wOffset.  Watch out for positive and negative value */\r\n      rOffset += bufferInc;\r\n\r\n      if(rOffset >= L)\r\n      {\r\n        rOffset -= L;\r\n      }\r\n\r\n      /* Decrement the loop counter */\r\n      i--;\r\n    }\r\n\r\n    /* Update the index pointer */\r\n    *readOffset = rOffset;\r\n  }\r\n\r\n\r\n  /**\r\n   * @brief Q7 Circular write function.\r\n   */\r\n  static __INLINE void arm_circularWrite_q7(\r\n  q7_t * circBuffer,\r\n  int32_t L,\r\n  uint16_t * writeOffset,\r\n  int32_t bufferInc,\r\n  const q7_t * src,\r\n  int32_t srcInc,\r\n  uint32_t blockSize)\r\n  {\r\n    uint32_t i = 0u;\r\n    int32_t wOffset;\r\n\r\n    /* Copy the value of Index pointer that points\r\n     * to the current location where the input samples to be copied */\r\n    wOffset = *writeOffset;\r\n\r\n    /* Loop over the blockSize */\r\n    i = blockSize;\r\n\r\n    while(i > 0u)\r\n    {\r\n      /* copy the input sample to the circular buffer */\r\n      circBuffer[wOffset] = *src;\r\n\r\n      /* Update the input pointer */\r\n      src += srcInc;\r\n\r\n      /* Circularly update wOffset.  Watch out for positive and negative value */\r\n      wOffset += bufferInc;\r\n      if(wOffset >= L)\r\n        wOffset -= L;\r\n\r\n      /* Decrement the loop counter */\r\n      i--;\r\n    }\r\n\r\n    /* Update the index pointer */\r\n    *writeOffset = (uint16_t)wOffset;\r\n  }\r\n\r\n\r\n  /**\r\n   * @brief Q7 Circular Read function.\r\n   */\r\n  static __INLINE void arm_circularRead_q7(\r\n  q7_t * circBuffer,\r\n  int32_t L,\r\n  int32_t * readOffset,\r\n  int32_t bufferInc,\r\n  q7_t * dst,\r\n  q7_t * dst_base,\r\n  int32_t dst_length,\r\n  int32_t dstInc,\r\n  uint32_t blockSize)\r\n  {\r\n    uint32_t i = 0;\r\n    int32_t rOffset, dst_end;\r\n\r\n    /* Copy the value of Index pointer that points\r\n     * to the current location from where the input samples to be read */\r\n    rOffset = *readOffset;\r\n\r\n    dst_end = (int32_t) (dst_base + dst_length);\r\n\r\n    /* Loop over the blockSize */\r\n    i = blockSize;\r\n\r\n    while(i > 0u)\r\n    {\r\n      /* copy the sample from the circular buffer to the destination buffer */\r\n      *dst = circBuffer[rOffset];\r\n\r\n      /* Update the input pointer */\r\n      dst += dstInc;\r\n\r\n      if(dst == (q7_t *) dst_end)\r\n      {\r\n        dst = dst_base;\r\n      }\r\n\r\n      /* Circularly update rOffset.  Watch out for positive and negative value */\r\n      rOffset += bufferInc;\r\n\r\n      if(rOffset >= L)\r\n      {\r\n        rOffset -= L;\r\n      }\r\n\r\n      /* Decrement the loop counter */\r\n      i--;\r\n    }\r\n\r\n    /* Update the index pointer */\r\n    *readOffset = rOffset;\r\n  }\r\n\r\n\r\n  /**\r\n   * @brief  Sum of the squares of the elements of a Q31 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output value.\r\n   */\r\n  void arm_power_q31(\r\n  q31_t * pSrc,\r\n  uint32_t blockSize,\r\n  q63_t * pResult);\r\n\r\n\r\n  /**\r\n   * @brief  Sum of the squares of the elements of a floating-point vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output value.\r\n   */\r\n  void arm_power_f32(\r\n  float32_t * pSrc,\r\n  uint32_t blockSize,\r\n  float32_t * pResult);\r\n\r\n\r\n  /**\r\n   * @brief  Sum of the squares of the elements of a Q15 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output value.\r\n   */\r\n  void arm_power_q15(\r\n  q15_t * pSrc,\r\n  uint32_t blockSize,\r\n  q63_t * pResult);\r\n\r\n\r\n  /**\r\n   * @brief  Sum of the squares of the elements of a Q7 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output value.\r\n   */\r\n  void arm_power_q7(\r\n  q7_t * pSrc,\r\n  uint32_t blockSize,\r\n  q31_t * pResult);\r\n\r\n\r\n  /**\r\n   * @brief  Mean value of a Q7 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output value.\r\n   */\r\n  void arm_mean_q7(\r\n  q7_t * pSrc,\r\n  uint32_t blockSize,\r\n  q7_t * pResult);\r\n\r\n\r\n  /**\r\n   * @brief  Mean value of a Q15 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output value.\r\n   */\r\n  void arm_mean_q15(\r\n  q15_t * pSrc,\r\n  uint32_t blockSize,\r\n  q15_t * pResult);\r\n\r\n\r\n  /**\r\n   * @brief  Mean value of a Q31 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output value.\r\n   */\r\n  void arm_mean_q31(\r\n  q31_t * pSrc,\r\n  uint32_t blockSize,\r\n  q31_t * pResult);\r\n\r\n\r\n  /**\r\n   * @brief  Mean value of a floating-point vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output value.\r\n   */\r\n  void arm_mean_f32(\r\n  float32_t * pSrc,\r\n  uint32_t blockSize,\r\n  float32_t * pResult);\r\n\r\n\r\n  /**\r\n   * @brief  Variance of the elements of a floating-point vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output value.\r\n   */\r\n  void arm_var_f32(\r\n  float32_t * pSrc,\r\n  uint32_t blockSize,\r\n  float32_t * pResult);\r\n\r\n\r\n  /**\r\n   * @brief  Variance of the elements of a Q31 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output value.\r\n   */\r\n  void arm_var_q31(\r\n  q31_t * pSrc,\r\n  uint32_t blockSize,\r\n  q31_t * pResult);\r\n\r\n\r\n  /**\r\n   * @brief  Variance of the elements of a Q15 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output value.\r\n   */\r\n  void arm_var_q15(\r\n  q15_t * pSrc,\r\n  uint32_t blockSize,\r\n  q15_t * pResult);\r\n\r\n\r\n  /**\r\n   * @brief  Root Mean Square of the elements of a floating-point vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output value.\r\n   */\r\n  void arm_rms_f32(\r\n  float32_t * pSrc,\r\n  uint32_t blockSize,\r\n  float32_t * pResult);\r\n\r\n\r\n  /**\r\n   * @brief  Root Mean Square of the elements of a Q31 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output value.\r\n   */\r\n  void arm_rms_q31(\r\n  q31_t * pSrc,\r\n  uint32_t blockSize,\r\n  q31_t * pResult);\r\n\r\n\r\n  /**\r\n   * @brief  Root Mean Square of the elements of a Q15 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output value.\r\n   */\r\n  void arm_rms_q15(\r\n  q15_t * pSrc,\r\n  uint32_t blockSize,\r\n  q15_t * pResult);\r\n\r\n\r\n  /**\r\n   * @brief  Standard deviation of the elements of a floating-point vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output value.\r\n   */\r\n  void arm_std_f32(\r\n  float32_t * pSrc,\r\n  uint32_t blockSize,\r\n  float32_t * pResult);\r\n\r\n\r\n  /**\r\n   * @brief  Standard deviation of the elements of a Q31 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output value.\r\n   */\r\n  void arm_std_q31(\r\n  q31_t * pSrc,\r\n  uint32_t blockSize,\r\n  q31_t * pResult);\r\n\r\n\r\n  /**\r\n   * @brief  Standard deviation of the elements of a Q15 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output value.\r\n   */\r\n  void arm_std_q15(\r\n  q15_t * pSrc,\r\n  uint32_t blockSize,\r\n  q15_t * pResult);\r\n\r\n\r\n  /**\r\n   * @brief  Floating-point complex magnitude\r\n   * @param[in]  pSrc        points to the complex input vector\r\n   * @param[out] pDst        points to the real output vector\r\n   * @param[in]  numSamples  number of complex samples in the input vector\r\n   */\r\n  void arm_cmplx_mag_f32(\r\n  float32_t * pSrc,\r\n  float32_t * pDst,\r\n  uint32_t numSamples);\r\n\r\n\r\n  /**\r\n   * @brief  Q31 complex magnitude\r\n   * @param[in]  pSrc        points to the complex input vector\r\n   * @param[out] pDst        points to the real output vector\r\n   * @param[in]  numSamples  number of complex samples in the input vector\r\n   */\r\n  void arm_cmplx_mag_q31(\r\n  q31_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t numSamples);\r\n\r\n\r\n  /**\r\n   * @brief  Q15 complex magnitude\r\n   * @param[in]  pSrc        points to the complex input vector\r\n   * @param[out] pDst        points to the real output vector\r\n   * @param[in]  numSamples  number of complex samples in the input vector\r\n   */\r\n  void arm_cmplx_mag_q15(\r\n  q15_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t numSamples);\r\n\r\n\r\n  /**\r\n   * @brief  Q15 complex dot product\r\n   * @param[in]  pSrcA       points to the first input vector\r\n   * @param[in]  pSrcB       points to the second input vector\r\n   * @param[in]  numSamples  number of complex samples in each vector\r\n   * @param[out] realResult  real part of the result returned here\r\n   * @param[out] imagResult  imaginary part of the result returned here\r\n   */\r\n  void arm_cmplx_dot_prod_q15(\r\n  q15_t * pSrcA,\r\n  q15_t * pSrcB,\r\n  uint32_t numSamples,\r\n  q31_t * realResult,\r\n  q31_t * imagResult);\r\n\r\n\r\n  /**\r\n   * @brief  Q31 complex dot product\r\n   * @param[in]  pSrcA       points to the first input vector\r\n   * @param[in]  pSrcB       points to the second input vector\r\n   * @param[in]  numSamples  number of complex samples in each vector\r\n   * @param[out] realResult  real part of the result returned here\r\n   * @param[out] imagResult  imaginary part of the result returned here\r\n   */\r\n  void arm_cmplx_dot_prod_q31(\r\n  q31_t * pSrcA,\r\n  q31_t * pSrcB,\r\n  uint32_t numSamples,\r\n  q63_t * realResult,\r\n  q63_t * imagResult);\r\n\r\n\r\n  /**\r\n   * @brief  Floating-point complex dot product\r\n   * @param[in]  pSrcA       points to the first input vector\r\n   * @param[in]  pSrcB       points to the second input vector\r\n   * @param[in]  numSamples  number of complex samples in each vector\r\n   * @param[out] realResult  real part of the result returned here\r\n   * @param[out] imagResult  imaginary part of the result returned here\r\n   */\r\n  void arm_cmplx_dot_prod_f32(\r\n  float32_t * pSrcA,\r\n  float32_t * pSrcB,\r\n  uint32_t numSamples,\r\n  float32_t * realResult,\r\n  float32_t * imagResult);\r\n\r\n\r\n  /**\r\n   * @brief  Q15 complex-by-real multiplication\r\n   * @param[in]  pSrcCmplx   points to the complex input vector\r\n   * @param[in]  pSrcReal    points to the real input vector\r\n   * @param[out] pCmplxDst   points to the complex output vector\r\n   * @param[in]  numSamples  number of samples in each vector\r\n   */\r\n  void arm_cmplx_mult_real_q15(\r\n  q15_t * pSrcCmplx,\r\n  q15_t * pSrcReal,\r\n  q15_t * pCmplxDst,\r\n  uint32_t numSamples);\r\n\r\n\r\n  /**\r\n   * @brief  Q31 complex-by-real multiplication\r\n   * @param[in]  pSrcCmplx   points to the complex input vector\r\n   * @param[in]  pSrcReal    points to the real input vector\r\n   * @param[out] pCmplxDst   points to the complex output vector\r\n   * @param[in]  numSamples  number of samples in each vector\r\n   */\r\n  void arm_cmplx_mult_real_q31(\r\n  q31_t * pSrcCmplx,\r\n  q31_t * pSrcReal,\r\n  q31_t * pCmplxDst,\r\n  uint32_t numSamples);\r\n\r\n\r\n  /**\r\n   * @brief  Floating-point complex-by-real multiplication\r\n   * @param[in]  pSrcCmplx   points to the complex input vector\r\n   * @param[in]  pSrcReal    points to the real input vector\r\n   * @param[out] pCmplxDst   points to the complex output vector\r\n   * @param[in]  numSamples  number of samples in each vector\r\n   */\r\n  void arm_cmplx_mult_real_f32(\r\n  float32_t * pSrcCmplx,\r\n  float32_t * pSrcReal,\r\n  float32_t * pCmplxDst,\r\n  uint32_t numSamples);\r\n\r\n\r\n  /**\r\n   * @brief  Minimum value of a Q7 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] result     is output pointer\r\n   * @param[in]  index      is the array index of the minimum value in the input buffer.\r\n   */\r\n  void arm_min_q7(\r\n  q7_t * pSrc,\r\n  uint32_t blockSize,\r\n  q7_t * result,\r\n  uint32_t * index);\r\n\r\n\r\n  /**\r\n   * @brief  Minimum value of a Q15 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output pointer\r\n   * @param[in]  pIndex     is the array index of the minimum value in the input buffer.\r\n   */\r\n  void arm_min_q15(\r\n  q15_t * pSrc,\r\n  uint32_t blockSize,\r\n  q15_t * pResult,\r\n  uint32_t * pIndex);\r\n\r\n\r\n  /**\r\n   * @brief  Minimum value of a Q31 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output pointer\r\n   * @param[out] pIndex     is the array index of the minimum value in the input buffer.\r\n   */\r\n  void arm_min_q31(\r\n  q31_t * pSrc,\r\n  uint32_t blockSize,\r\n  q31_t * pResult,\r\n  uint32_t * pIndex);\r\n\r\n\r\n  /**\r\n   * @brief  Minimum value of a floating-point vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output pointer\r\n   * @param[out] pIndex     is the array index of the minimum value in the input buffer.\r\n   */\r\n  void arm_min_f32(\r\n  float32_t * pSrc,\r\n  uint32_t blockSize,\r\n  float32_t * pResult,\r\n  uint32_t * pIndex);\r\n\r\n\r\n/**\r\n * @brief Maximum value of a Q7 vector.\r\n * @param[in]  pSrc       points to the input buffer\r\n * @param[in]  blockSize  length of the input vector\r\n * @param[out] pResult    maximum value returned here\r\n * @param[out] pIndex     index of maximum value returned here\r\n */\r\n  void arm_max_q7(\r\n  q7_t * pSrc,\r\n  uint32_t blockSize,\r\n  q7_t * pResult,\r\n  uint32_t * pIndex);\r\n\r\n\r\n/**\r\n * @brief Maximum value of a Q15 vector.\r\n * @param[in]  pSrc       points to the input buffer\r\n * @param[in]  blockSize  length of the input vector\r\n * @param[out] pResult    maximum value returned here\r\n * @param[out] pIndex     index of maximum value returned here\r\n */\r\n  void arm_max_q15(\r\n  q15_t * pSrc,\r\n  uint32_t blockSize,\r\n  q15_t * pResult,\r\n  uint32_t * pIndex);\r\n\r\n\r\n/**\r\n * @brief Maximum value of a Q31 vector.\r\n * @param[in]  pSrc       points to the input buffer\r\n * @param[in]  blockSize  length of the input vector\r\n * @param[out] pResult    maximum value returned here\r\n * @param[out] pIndex     index of maximum value returned here\r\n */\r\n  void arm_max_q31(\r\n  q31_t * pSrc,\r\n  uint32_t blockSize,\r\n  q31_t * pResult,\r\n  uint32_t * pIndex);\r\n\r\n\r\n/**\r\n * @brief Maximum value of a floating-point vector.\r\n * @param[in]  pSrc       points to the input buffer\r\n * @param[in]  blockSize  length of the input vector\r\n * @param[out] pResult    maximum value returned here\r\n * @param[out] pIndex     index of maximum value returned here\r\n */\r\n  void arm_max_f32(\r\n  float32_t * pSrc,\r\n  uint32_t blockSize,\r\n  float32_t * pResult,\r\n  uint32_t * pIndex);\r\n\r\n\r\n  /**\r\n   * @brief  Q15 complex-by-complex multiplication\r\n   * @param[in]  pSrcA       points to the first input vector\r\n   * @param[in]  pSrcB       points to the second input vector\r\n   * @param[out] pDst        points to the output vector\r\n   * @param[in]  numSamples  number of complex samples in each vector\r\n   */\r\n  void arm_cmplx_mult_cmplx_q15(\r\n  q15_t * pSrcA,\r\n  q15_t * pSrcB,\r\n  q15_t * pDst,\r\n  uint32_t numSamples);\r\n\r\n\r\n  /**\r\n   * @brief  Q31 complex-by-complex multiplication\r\n   * @param[in]  pSrcA       points to the first input vector\r\n   * @param[in]  pSrcB       points to the second input vector\r\n   * @param[out] pDst        points to the output vector\r\n   * @param[in]  numSamples  number of complex samples in each vector\r\n   */\r\n  void arm_cmplx_mult_cmplx_q31(\r\n  q31_t * pSrcA,\r\n  q31_t * pSrcB,\r\n  q31_t * pDst,\r\n  uint32_t numSamples);\r\n\r\n\r\n  /**\r\n   * @brief  Floating-point complex-by-complex multiplication\r\n   * @param[in]  pSrcA       points to the first input vector\r\n   * @param[in]  pSrcB       points to the second input vector\r\n   * @param[out] pDst        points to the output vector\r\n   * @param[in]  numSamples  number of complex samples in each vector\r\n   */\r\n  void arm_cmplx_mult_cmplx_f32(\r\n  float32_t * pSrcA,\r\n  float32_t * pSrcB,\r\n  float32_t * pDst,\r\n  uint32_t numSamples);\r\n\r\n\r\n  /**\r\n   * @brief Converts the elements of the floating-point vector to Q31 vector.\r\n   * @param[in]  pSrc       points to the floating-point input vector\r\n   * @param[out] pDst       points to the Q31 output vector\r\n   * @param[in]  blockSize  length of the input vector\r\n   */\r\n  void arm_float_to_q31(\r\n  float32_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Converts the elements of the floating-point vector to Q15 vector.\r\n   * @param[in]  pSrc       points to the floating-point input vector\r\n   * @param[out] pDst       points to the Q15 output vector\r\n   * @param[in]  blockSize  length of the input vector\r\n   */\r\n  void arm_float_to_q15(\r\n  float32_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Converts the elements of the floating-point vector to Q7 vector.\r\n   * @param[in]  pSrc       points to the floating-point input vector\r\n   * @param[out] pDst       points to the Q7 output vector\r\n   * @param[in]  blockSize  length of the input vector\r\n   */\r\n  void arm_float_to_q7(\r\n  float32_t * pSrc,\r\n  q7_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Converts the elements of the Q31 vector to Q15 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[out] pDst       is output pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   */\r\n  void arm_q31_to_q15(\r\n  q31_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Converts the elements of the Q31 vector to Q7 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[out] pDst       is output pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   */\r\n  void arm_q31_to_q7(\r\n  q31_t * pSrc,\r\n  q7_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Converts the elements of the Q15 vector to floating-point vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[out] pDst       is output pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   */\r\n  void arm_q15_to_float(\r\n  q15_t * pSrc,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Converts the elements of the Q15 vector to Q31 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[out] pDst       is output pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   */\r\n  void arm_q15_to_q31(\r\n  q15_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Converts the elements of the Q15 vector to Q7 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[out] pDst       is output pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   */\r\n  void arm_q15_to_q7(\r\n  q15_t * pSrc,\r\n  q7_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @ingroup groupInterpolation\r\n   */\r\n\r\n  /**\r\n   * @defgroup BilinearInterpolate Bilinear Interpolation\r\n   *\r\n   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.\r\n   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process\r\n   * determines values between the grid points.\r\n   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.\r\n   * Bilinear interpolation is often used in image processing to rescale images.\r\n   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.\r\n   *\r\n   * <b>Algorithm</b>\r\n   * \\par\r\n   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.\r\n   * For floating-point, the instance structure is defined as:\r\n   * <pre>\r\n   *   typedef struct\r\n   *   {\r\n   *     uint16_t numRows;\r\n   *     uint16_t numCols;\r\n   *     float32_t *pData;\r\n   * } arm_bilinear_interp_instance_f32;\r\n   * </pre>\r\n   *\r\n   * \\par\r\n   * where <code>numRows</code> specifies the number of rows in the table;\r\n   * <code>numCols</code> specifies the number of columns in the table;\r\n   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.\r\n   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.\r\n   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.\r\n   *\r\n   * \\par\r\n   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:\r\n   * <pre>\r\n   *     XF = floor(x)\r\n   *     YF = floor(y)\r\n   * </pre>\r\n   * \\par\r\n   * The interpolated output point is computed as:\r\n   * <pre>\r\n   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))\r\n   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))\r\n   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)\r\n   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)\r\n   * </pre>\r\n   * Note that the coordinates (x, y) contain integer and fractional components.\r\n   * The integer components specify which portion of the table to use while the\r\n   * fractional components control the interpolation processor.\r\n   *\r\n   * \\par\r\n   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.\r\n   */\r\n\r\n  /**\r\n   * @addtogroup BilinearInterpolate\r\n   * @{\r\n   */\r\n\r\n\r\n  /**\r\n  *\r\n  * @brief  Floating-point bilinear interpolation.\r\n  * @param[in,out] S  points to an instance of the interpolation structure.\r\n  * @param[in]     X  interpolation coordinate.\r\n  * @param[in]     Y  interpolation coordinate.\r\n  * @return out interpolated value.\r\n  */\r\n  static __INLINE float32_t arm_bilinear_interp_f32(\r\n  const arm_bilinear_interp_instance_f32 * S,\r\n  float32_t X,\r\n  float32_t Y)\r\n  {\r\n    float32_t out;\r\n    float32_t f00, f01, f10, f11;\r\n    float32_t *pData = S->pData;\r\n    int32_t xIndex, yIndex, index;\r\n    float32_t xdiff, ydiff;\r\n    float32_t b1, b2, b3, b4;\r\n\r\n    xIndex = (int32_t) X;\r\n    yIndex = (int32_t) Y;\r\n\r\n    /* Care taken for table outside boundary */\r\n    /* Returns zero output when values are outside table boundary */\r\n    if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))\r\n    {\r\n      return (0);\r\n    }\r\n\r\n    /* Calculation of index for two nearest points in X-direction */\r\n    index = (xIndex - 1) + (yIndex - 1) * S->numCols;\r\n\r\n\r\n    /* Read two nearest points in X-direction */\r\n    f00 = pData[index];\r\n    f01 = pData[index + 1];\r\n\r\n    /* Calculation of index for two nearest points in Y-direction */\r\n    index = (xIndex - 1) + (yIndex) * S->numCols;\r\n\r\n\r\n    /* Read two nearest points in Y-direction */\r\n    f10 = pData[index];\r\n    f11 = pData[index + 1];\r\n\r\n    /* Calculation of intermediate values */\r\n    b1 = f00;\r\n    b2 = f01 - f00;\r\n    b3 = f10 - f00;\r\n    b4 = f00 - f01 - f10 + f11;\r\n\r\n    /* Calculation of fractional part in X */\r\n    xdiff = X - xIndex;\r\n\r\n    /* Calculation of fractional part in Y */\r\n    ydiff = Y - yIndex;\r\n\r\n    /* Calculation of bi-linear interpolated output */\r\n    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;\r\n\r\n    /* return to application */\r\n    return (out);\r\n  }\r\n\r\n\r\n  /**\r\n  *\r\n  * @brief  Q31 bilinear interpolation.\r\n  * @param[in,out] S  points to an instance of the interpolation structure.\r\n  * @param[in]     X  interpolation coordinate in 12.20 format.\r\n  * @param[in]     Y  interpolation coordinate in 12.20 format.\r\n  * @return out interpolated value.\r\n  */\r\n  static __INLINE q31_t arm_bilinear_interp_q31(\r\n  arm_bilinear_interp_instance_q31 * S,\r\n  q31_t X,\r\n  q31_t Y)\r\n  {\r\n    q31_t out;                                   /* Temporary output */\r\n    q31_t acc = 0;                               /* output */\r\n    q31_t xfract, yfract;                        /* X, Y fractional parts */\r\n    q31_t x1, x2, y1, y2;                        /* Nearest output values */\r\n    int32_t rI, cI;                              /* Row and column indices */\r\n    q31_t *pYData = S->pData;                    /* pointer to output table values */\r\n    uint32_t nCols = S->numCols;                 /* num of rows */\r\n\r\n    /* Input is in 12.20 format */\r\n    /* 12 bits for the table index */\r\n    /* Index value calculation */\r\n    rI = ((X & (q31_t)0xFFF00000) >> 20);\r\n\r\n    /* Input is in 12.20 format */\r\n    /* 12 bits for the table index */\r\n    /* Index value calculation */\r\n    cI = ((Y & (q31_t)0xFFF00000) >> 20);\r\n\r\n    /* Care taken for table outside boundary */\r\n    /* Returns zero output when values are outside table boundary */\r\n    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\r\n    {\r\n      return (0);\r\n    }\r\n\r\n    /* 20 bits for the fractional part */\r\n    /* shift left xfract by 11 to keep 1.31 format */\r\n    xfract = (X & 0x000FFFFF) << 11u;\r\n\r\n    /* Read two nearest output values from the index */\r\n    x1 = pYData[(rI) + (int32_t)nCols * (cI)    ];\r\n    x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];\r\n\r\n    /* 20 bits for the fractional part */\r\n    /* shift left yfract by 11 to keep 1.31 format */\r\n    yfract = (Y & 0x000FFFFF) << 11u;\r\n\r\n    /* Read two nearest output values from the index */\r\n    y1 = pYData[(rI) + (int32_t)nCols * (cI + 1)    ];\r\n    y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];\r\n\r\n    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */\r\n    out = ((q31_t) (((q63_t) x1  * (0x7FFFFFFF - xfract)) >> 32));\r\n    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));\r\n\r\n    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */\r\n    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));\r\n    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));\r\n\r\n    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */\r\n    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));\r\n    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\r\n\r\n    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */\r\n    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));\r\n    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\r\n\r\n    /* Convert acc to 1.31(q31) format */\r\n    return ((q31_t)(acc << 2));\r\n  }\r\n\r\n\r\n  /**\r\n  * @brief  Q15 bilinear interpolation.\r\n  * @param[in,out] S  points to an instance of the interpolation structure.\r\n  * @param[in]     X  interpolation coordinate in 12.20 format.\r\n  * @param[in]     Y  interpolation coordinate in 12.20 format.\r\n  * @return out interpolated value.\r\n  */\r\n  static __INLINE q15_t arm_bilinear_interp_q15(\r\n  arm_bilinear_interp_instance_q15 * S,\r\n  q31_t X,\r\n  q31_t Y)\r\n  {\r\n    q63_t acc = 0;                               /* output */\r\n    q31_t out;                                   /* Temporary output */\r\n    q15_t x1, x2, y1, y2;                        /* Nearest output values */\r\n    q31_t xfract, yfract;                        /* X, Y fractional parts */\r\n    int32_t rI, cI;                              /* Row and column indices */\r\n    q15_t *pYData = S->pData;                    /* pointer to output table values */\r\n    uint32_t nCols = S->numCols;                 /* num of rows */\r\n\r\n    /* Input is in 12.20 format */\r\n    /* 12 bits for the table index */\r\n    /* Index value calculation */\r\n    rI = ((X & (q31_t)0xFFF00000) >> 20);\r\n\r\n    /* Input is in 12.20 format */\r\n    /* 12 bits for the table index */\r\n    /* Index value calculation */\r\n    cI = ((Y & (q31_t)0xFFF00000) >> 20);\r\n\r\n    /* Care taken for table outside boundary */\r\n    /* Returns zero output when values are outside table boundary */\r\n    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\r\n    {\r\n      return (0);\r\n    }\r\n\r\n    /* 20 bits for the fractional part */\r\n    /* xfract should be in 12.20 format */\r\n    xfract = (X & 0x000FFFFF);\r\n\r\n    /* Read two nearest output values from the index */\r\n    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];\r\n    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];\r\n\r\n    /* 20 bits for the fractional part */\r\n    /* yfract should be in 12.20 format */\r\n    yfract = (Y & 0x000FFFFF);\r\n\r\n    /* Read two nearest output values from the index */\r\n    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];\r\n    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];\r\n\r\n    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */\r\n\r\n    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */\r\n    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */\r\n    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);\r\n    acc = ((q63_t) out * (0xFFFFF - yfract));\r\n\r\n    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */\r\n    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);\r\n    acc += ((q63_t) out * (xfract));\r\n\r\n    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */\r\n    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);\r\n    acc += ((q63_t) out * (yfract));\r\n\r\n    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */\r\n    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);\r\n    acc += ((q63_t) out * (yfract));\r\n\r\n    /* acc is in 13.51 format and down shift acc by 36 times */\r\n    /* Convert out to 1.15 format */\r\n    return ((q15_t)(acc >> 36));\r\n  }\r\n\r\n\r\n  /**\r\n  * @brief  Q7 bilinear interpolation.\r\n  * @param[in,out] S  points to an instance of the interpolation structure.\r\n  * @param[in]     X  interpolation coordinate in 12.20 format.\r\n  * @param[in]     Y  interpolation coordinate in 12.20 format.\r\n  * @return out interpolated value.\r\n  */\r\n  static __INLINE q7_t arm_bilinear_interp_q7(\r\n  arm_bilinear_interp_instance_q7 * S,\r\n  q31_t X,\r\n  q31_t Y)\r\n  {\r\n    q63_t acc = 0;                               /* output */\r\n    q31_t out;                                   /* Temporary output */\r\n    q31_t xfract, yfract;                        /* X, Y fractional parts */\r\n    q7_t x1, x2, y1, y2;                         /* Nearest output values */\r\n    int32_t rI, cI;                              /* Row and column indices */\r\n    q7_t *pYData = S->pData;                     /* pointer to output table values */\r\n    uint32_t nCols = S->numCols;                 /* num of rows */\r\n\r\n    /* Input is in 12.20 format */\r\n    /* 12 bits for the table index */\r\n    /* Index value calculation */\r\n    rI = ((X & (q31_t)0xFFF00000) >> 20);\r\n\r\n    /* Input is in 12.20 format */\r\n    /* 12 bits for the table index */\r\n    /* Index value calculation */\r\n    cI = ((Y & (q31_t)0xFFF00000) >> 20);\r\n\r\n    /* Care taken for table outside boundary */\r\n    /* Returns zero output when values are outside table boundary */\r\n    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\r\n    {\r\n      return (0);\r\n    }\r\n\r\n    /* 20 bits for the fractional part */\r\n    /* xfract should be in 12.20 format */\r\n    xfract = (X & (q31_t)0x000FFFFF);\r\n\r\n    /* Read two nearest output values from the index */\r\n    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];\r\n    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];\r\n\r\n    /* 20 bits for the fractional part */\r\n    /* yfract should be in 12.20 format */\r\n    yfract = (Y & (q31_t)0x000FFFFF);\r\n\r\n    /* Read two nearest output values from the index */\r\n    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];\r\n    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];\r\n\r\n    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */\r\n    out = ((x1 * (0xFFFFF - xfract)));\r\n    acc = (((q63_t) out * (0xFFFFF - yfract)));\r\n\r\n    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */\r\n    out = ((x2 * (0xFFFFF - yfract)));\r\n    acc += (((q63_t) out * (xfract)));\r\n\r\n    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */\r\n    out = ((y1 * (0xFFFFF - xfract)));\r\n    acc += (((q63_t) out * (yfract)));\r\n\r\n    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */\r\n    out = ((y2 * (yfract)));\r\n    acc += (((q63_t) out * (xfract)));\r\n\r\n    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */\r\n    return ((q7_t)(acc >> 40));\r\n  }\r\n\r\n  /**\r\n   * @} end of BilinearInterpolate group\r\n   */\r\n\r\n\r\n/* SMMLAR */\r\n#define multAcc_32x32_keep32_R(a, x, y) \\\r\n    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)\r\n\r\n/* SMMLSR */\r\n#define multSub_32x32_keep32_R(a, x, y) \\\r\n    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)\r\n\r\n/* SMMULR */\r\n#define mult_32x32_keep32_R(a, x, y) \\\r\n    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)\r\n\r\n/* SMMLA */\r\n#define multAcc_32x32_keep32(a, x, y) \\\r\n    a += (q31_t) (((q63_t) x * y) >> 32)\r\n\r\n/* SMMLS */\r\n#define multSub_32x32_keep32(a, x, y) \\\r\n    a -= (q31_t) (((q63_t) x * y) >> 32)\r\n\r\n/* SMMUL */\r\n#define mult_32x32_keep32(a, x, y) \\\r\n    a = (q31_t) (((q63_t) x * y ) >> 32)\r\n\r\n\r\n#if defined ( __CC_ARM )\r\n  /* Enter low optimization region - place directly above function definition */\r\n  #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)\r\n    #define LOW_OPTIMIZATION_ENTER \\\r\n       _Pragma (\"push\")         \\\r\n       _Pragma (\"O1\")\r\n  #else\r\n    #define LOW_OPTIMIZATION_ENTER\r\n  #endif\r\n\r\n  /* Exit low optimization region - place directly after end of function definition */\r\n  #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)\r\n    #define LOW_OPTIMIZATION_EXIT \\\r\n       _Pragma (\"pop\")\r\n  #else\r\n    #define LOW_OPTIMIZATION_EXIT\r\n  #endif\r\n\r\n  /* Enter low optimization region - place directly above function definition */\r\n  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r\n\r\n  /* Exit low optimization region - place directly after end of function definition */\r\n  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r\n\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #define LOW_OPTIMIZATION_ENTER\r\n  #define LOW_OPTIMIZATION_EXIT\r\n  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r\n  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r\n\r\n#elif defined(__GNUC__)\r\n  #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize(\"-O1\") ))\r\n  #define LOW_OPTIMIZATION_EXIT\r\n  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r\n  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r\n\r\n#elif defined(__ICCARM__)\r\n  /* Enter low optimization region - place directly above function definition */\r\n  #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)\r\n    #define LOW_OPTIMIZATION_ENTER \\\r\n       _Pragma (\"optimize=low\")\r\n  #else\r\n    #define LOW_OPTIMIZATION_ENTER\r\n  #endif\r\n\r\n  /* Exit low optimization region - place directly after end of function definition */\r\n  #define LOW_OPTIMIZATION_EXIT\r\n\r\n  /* Enter low optimization region - place directly above function definition */\r\n  #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)\r\n    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \\\r\n       _Pragma (\"optimize=low\")\r\n  #else\r\n    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r\n  #endif\r\n\r\n  /* Exit low optimization region - place directly after end of function definition */\r\n  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r\n\r\n#elif defined(__CSMC__)\r\n  #define LOW_OPTIMIZATION_ENTER\r\n  #define LOW_OPTIMIZATION_EXIT\r\n  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r\n  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r\n\r\n#elif defined(__TASKING__)\r\n  #define LOW_OPTIMIZATION_ENTER\r\n  #define LOW_OPTIMIZATION_EXIT\r\n  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r\n  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r\n\r\n#endif\r\n\r\n\r\n#ifdef   __cplusplus\r\n}\r\n#endif\r\n\r\n\r\n#if defined ( __GNUC__ )\r\n#pragma GCC diagnostic pop\r\n#endif\r\n\r\n#endif /* _ARM_MATH_H */\r\n\r\n/**\r\n *\r\n * End of file.\r\n */\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/bsp/opencr/include/cmsis_armcc.h",
    "content": "/**************************************************************************//**\r\n * @file     cmsis_armcc.h\r\n * @brief    CMSIS Cortex-M Core Function/Instruction Header File\r\n * @version  V4.30\r\n * @date     20. October 2015\r\n ******************************************************************************/\r\n/* Copyright (c) 2009 - 2015 ARM LIMITED\r\n\r\n   All rights reserved.\r\n   Redistribution and use in source and binary forms, with or without\r\n   modification, are permitted provided that the following conditions are met:\r\n   - Redistributions of source code must retain the above copyright\r\n     notice, this list of conditions and the following disclaimer.\r\n   - Redistributions in binary form must reproduce the above copyright\r\n     notice, this list of conditions and the following disclaimer in the\r\n     documentation and/or other materials provided with the distribution.\r\n   - Neither the name of ARM nor the names of its contributors may be used\r\n     to endorse or promote products derived from this software without\r\n     specific prior written permission.\r\n   *\r\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n   POSSIBILITY OF SUCH DAMAGE.\r\n   ---------------------------------------------------------------------------*/\r\n\r\n\r\n#ifndef __CMSIS_ARMCC_H\r\n#define __CMSIS_ARMCC_H\r\n\r\n\r\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)\r\n  #error \"Please use ARM Compiler Toolchain V4.0.677 or later!\"\r\n#endif\r\n\r\n/* ###########################  Core Function Access  ########################### */\r\n/** \\ingroup  CMSIS_Core_FunctionInterface\r\n    \\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r\n  @{\r\n */\r\n\r\n/* intrinsic void __enable_irq();     */\r\n/* intrinsic void __disable_irq();    */\r\n\r\n/**\r\n  \\brief   Get Control Register\r\n  \\details Returns the content of the Control Register.\r\n  \\return               Control Register value\r\n */\r\n__STATIC_INLINE uint32_t __get_CONTROL(void)\r\n{\r\n  register uint32_t __regControl         __ASM(\"control\");\r\n  return(__regControl);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Control Register\r\n  \\details Writes the given value to the Control Register.\r\n  \\param [in]    control  Control Register value to set\r\n */\r\n__STATIC_INLINE void __set_CONTROL(uint32_t control)\r\n{\r\n  register uint32_t __regControl         __ASM(\"control\");\r\n  __regControl = control;\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get IPSR Register\r\n  \\details Returns the content of the IPSR Register.\r\n  \\return               IPSR Register value\r\n */\r\n__STATIC_INLINE uint32_t __get_IPSR(void)\r\n{\r\n  register uint32_t __regIPSR          __ASM(\"ipsr\");\r\n  return(__regIPSR);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get APSR Register\r\n  \\details Returns the content of the APSR Register.\r\n  \\return               APSR Register value\r\n */\r\n__STATIC_INLINE uint32_t __get_APSR(void)\r\n{\r\n  register uint32_t __regAPSR          __ASM(\"apsr\");\r\n  return(__regAPSR);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get xPSR Register\r\n  \\details Returns the content of the xPSR Register.\r\n  \\return               xPSR Register value\r\n */\r\n__STATIC_INLINE uint32_t __get_xPSR(void)\r\n{\r\n  register uint32_t __regXPSR          __ASM(\"xpsr\");\r\n  return(__regXPSR);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Process Stack Pointer\r\n  \\details Returns the current value of the Process Stack Pointer (PSP).\r\n  \\return               PSP Register value\r\n */\r\n__STATIC_INLINE uint32_t __get_PSP(void)\r\n{\r\n  register uint32_t __regProcessStackPointer  __ASM(\"psp\");\r\n  return(__regProcessStackPointer);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Process Stack Pointer\r\n  \\details Assigns the given value to the Process Stack Pointer (PSP).\r\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\r\n */\r\n__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r\n{\r\n  register uint32_t __regProcessStackPointer  __ASM(\"psp\");\r\n  __regProcessStackPointer = topOfProcStack;\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Main Stack Pointer\r\n  \\details Returns the current value of the Main Stack Pointer (MSP).\r\n  \\return               MSP Register value\r\n */\r\n__STATIC_INLINE uint32_t __get_MSP(void)\r\n{\r\n  register uint32_t __regMainStackPointer     __ASM(\"msp\");\r\n  return(__regMainStackPointer);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Main Stack Pointer\r\n  \\details Assigns the given value to the Main Stack Pointer (MSP).\r\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\r\n */\r\n__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r\n{\r\n  register uint32_t __regMainStackPointer     __ASM(\"msp\");\r\n  __regMainStackPointer = topOfMainStack;\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Priority Mask\r\n  \\details Returns the current state of the priority mask bit from the Priority Mask Register.\r\n  \\return               Priority Mask value\r\n */\r\n__STATIC_INLINE uint32_t __get_PRIMASK(void)\r\n{\r\n  register uint32_t __regPriMask         __ASM(\"primask\");\r\n  return(__regPriMask);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Priority Mask\r\n  \\details Assigns the given value to the Priority Mask Register.\r\n  \\param [in]    priMask  Priority Mask\r\n */\r\n__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r\n{\r\n  register uint32_t __regPriMask         __ASM(\"primask\");\r\n  __regPriMask = (priMask);\r\n}\r\n\r\n\r\n#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\r\n\r\n/**\r\n  \\brief   Enable FIQ\r\n  \\details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r\n           Can only be executed in Privileged modes.\r\n */\r\n#define __enable_fault_irq                __enable_fiq\r\n\r\n\r\n/**\r\n  \\brief   Disable FIQ\r\n  \\details Disables FIQ interrupts by setting the F-bit in the CPSR.\r\n           Can only be executed in Privileged modes.\r\n */\r\n#define __disable_fault_irq               __disable_fiq\r\n\r\n\r\n/**\r\n  \\brief   Get Base Priority\r\n  \\details Returns the current value of the Base Priority register.\r\n  \\return               Base Priority register value\r\n */\r\n__STATIC_INLINE uint32_t  __get_BASEPRI(void)\r\n{\r\n  register uint32_t __regBasePri         __ASM(\"basepri\");\r\n  return(__regBasePri);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Base Priority\r\n  \\details Assigns the given value to the Base Priority register.\r\n  \\param [in]    basePri  Base Priority value to set\r\n */\r\n__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)\r\n{\r\n  register uint32_t __regBasePri         __ASM(\"basepri\");\r\n  __regBasePri = (basePri & 0xFFU);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Base Priority with condition\r\n  \\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r\n           or the new value increases the BASEPRI priority level.\r\n  \\param [in]    basePri  Base Priority value to set\r\n */\r\n__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)\r\n{\r\n  register uint32_t __regBasePriMax      __ASM(\"basepri_max\");\r\n  __regBasePriMax = (basePri & 0xFFU);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Fault Mask\r\n  \\details Returns the current value of the Fault Mask register.\r\n  \\return               Fault Mask register value\r\n */\r\n__STATIC_INLINE uint32_t __get_FAULTMASK(void)\r\n{\r\n  register uint32_t __regFaultMask       __ASM(\"faultmask\");\r\n  return(__regFaultMask);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Fault Mask\r\n  \\details Assigns the given value to the Fault Mask register.\r\n  \\param [in]    faultMask  Fault Mask value to set\r\n */\r\n__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r\n{\r\n  register uint32_t __regFaultMask       __ASM(\"faultmask\");\r\n  __regFaultMask = (faultMask & (uint32_t)1);\r\n}\r\n\r\n#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */\r\n\r\n\r\n#if       (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)\r\n\r\n/**\r\n  \\brief   Get FPSCR\r\n  \\details Returns the current value of the Floating Point Status/Control register.\r\n  \\return               Floating Point Status/Control register value\r\n */\r\n__STATIC_INLINE uint32_t __get_FPSCR(void)\r\n{\r\n#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r\n  register uint32_t __regfpscr         __ASM(\"fpscr\");\r\n  return(__regfpscr);\r\n#else\r\n   return(0U);\r\n#endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set FPSCR\r\n  \\details Assigns the given value to the Floating Point Status/Control register.\r\n  \\param [in]    fpscr  Floating Point Status/Control value to set\r\n */\r\n__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r\n{\r\n#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r\n  register uint32_t __regfpscr         __ASM(\"fpscr\");\r\n  __regfpscr = (fpscr);\r\n#endif\r\n}\r\n\r\n#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */\r\n\r\n\r\n\r\n/*@} end of CMSIS_Core_RegAccFunctions */\r\n\r\n\r\n/* ##########################  Core Instruction Access  ######################### */\r\n/** \\defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r\n  Access to dedicated instructions\r\n  @{\r\n*/\r\n\r\n/**\r\n  \\brief   No Operation\r\n  \\details No Operation does nothing. This instruction can be used for code alignment purposes.\r\n */\r\n#define __NOP                             __nop\r\n\r\n\r\n/**\r\n  \\brief   Wait For Interrupt\r\n  \\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r\n */\r\n#define __WFI                             __wfi\r\n\r\n\r\n/**\r\n  \\brief   Wait For Event\r\n  \\details Wait For Event is a hint instruction that permits the processor to enter\r\n           a low-power state until one of a number of events occurs.\r\n */\r\n#define __WFE                             __wfe\r\n\r\n\r\n/**\r\n  \\brief   Send Event\r\n  \\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r\n */\r\n#define __SEV                             __sev\r\n\r\n\r\n/**\r\n  \\brief   Instruction Synchronization Barrier\r\n  \\details Instruction Synchronization Barrier flushes the pipeline in the processor,\r\n           so that all instructions following the ISB are fetched from cache or memory,\r\n           after the instruction has been completed.\r\n */\r\n#define __ISB() do {\\\r\n                   __schedule_barrier();\\\r\n                   __isb(0xF);\\\r\n                   __schedule_barrier();\\\r\n                } while (0U)\r\n\r\n/**\r\n  \\brief   Data Synchronization Barrier\r\n  \\details Acts as a special kind of Data Memory Barrier.\r\n           It completes when all explicit memory accesses before this instruction complete.\r\n */\r\n#define __DSB() do {\\\r\n                   __schedule_barrier();\\\r\n                   __dsb(0xF);\\\r\n                   __schedule_barrier();\\\r\n                } while (0U)\r\n\r\n/**\r\n  \\brief   Data Memory Barrier\r\n  \\details Ensures the apparent order of the explicit memory operations before\r\n           and after the instruction, without ensuring their completion.\r\n */\r\n#define __DMB() do {\\\r\n                   __schedule_barrier();\\\r\n                   __dmb(0xF);\\\r\n                   __schedule_barrier();\\\r\n                } while (0U)\r\n\r\n/**\r\n  \\brief   Reverse byte order (32 bit)\r\n  \\details Reverses the byte order in integer value.\r\n  \\param [in]    value  Value to reverse\r\n  \\return               Reversed value\r\n */\r\n#define __REV                             __rev\r\n\r\n\r\n/**\r\n  \\brief   Reverse byte order (16 bit)\r\n  \\details Reverses the byte order in two unsigned short values.\r\n  \\param [in]    value  Value to reverse\r\n  \\return               Reversed value\r\n */\r\n#ifndef __NO_EMBEDDED_ASM\r\n__attribute__((section(\".rev16_text\"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)\r\n{\r\n  rev16 r0, r0\r\n  bx lr\r\n}\r\n#endif\r\n\r\n/**\r\n  \\brief   Reverse byte order in signed short value\r\n  \\details Reverses the byte order in a signed short value with sign extension to integer.\r\n  \\param [in]    value  Value to reverse\r\n  \\return               Reversed value\r\n */\r\n#ifndef __NO_EMBEDDED_ASM\r\n__attribute__((section(\".revsh_text\"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)\r\n{\r\n  revsh r0, r0\r\n  bx lr\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Rotate Right in unsigned value (32 bit)\r\n  \\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r\n  \\param [in]    value  Value to rotate\r\n  \\param [in]    value  Number of Bits to rotate\r\n  \\return               Rotated value\r\n */\r\n#define __ROR                             __ror\r\n\r\n\r\n/**\r\n  \\brief   Breakpoint\r\n  \\details Causes the processor to enter Debug state.\r\n           Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r\n  \\param [in]    value  is ignored by the processor.\r\n                 If required, a debugger can use it to store additional information about the breakpoint.\r\n */\r\n#define __BKPT(value)                       __breakpoint(value)\r\n\r\n\r\n/**\r\n  \\brief   Reverse bit order of value\r\n  \\details Reverses the bit order of the given value.\r\n  \\param [in]    value  Value to reverse\r\n  \\return               Reversed value\r\n */\r\n#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\r\n  #define __RBIT                          __rbit\r\n#else\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r\n{\r\n  uint32_t result;\r\n  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */\r\n\r\n  result = value;                      /* r will be reversed bits of v; first get LSB of v */\r\n  for (value >>= 1U; value; value >>= 1U)\r\n  {\r\n    result <<= 1U;\r\n    result |= value & 1U;\r\n    s--;\r\n  }\r\n  result <<= s;                        /* shift when v's highest bits are zero */\r\n  return(result);\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Count leading zeros\r\n  \\details Counts the number of leading zeros of a data value.\r\n  \\param [in]  value  Value to count the leading zeros\r\n  \\return             number of leading zeros in value\r\n */\r\n#define __CLZ                             __clz\r\n\r\n\r\n#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\r\n\r\n/**\r\n  \\brief   LDR Exclusive (8 bit)\r\n  \\details Executes a exclusive LDR instruction for 8 bit value.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return             value of type uint8_t at (*ptr)\r\n */\r\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r\n  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))\r\n#else\r\n  #define __LDREXB(ptr)          _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") ((uint8_t ) __ldrex(ptr))  _Pragma(\"pop\")\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   LDR Exclusive (16 bit)\r\n  \\details Executes a exclusive LDR instruction for 16 bit values.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return        value of type uint16_t at (*ptr)\r\n */\r\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r\n  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))\r\n#else\r\n  #define __LDREXH(ptr)          _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") ((uint16_t) __ldrex(ptr))  _Pragma(\"pop\")\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   LDR Exclusive (32 bit)\r\n  \\details Executes a exclusive LDR instruction for 32 bit values.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return        value of type uint32_t at (*ptr)\r\n */\r\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r\n  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))\r\n#else\r\n  #define __LDREXW(ptr)          _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") ((uint32_t ) __ldrex(ptr))  _Pragma(\"pop\")\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   STR Exclusive (8 bit)\r\n  \\details Executes a exclusive STR instruction for 8 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n  \\return          0  Function succeeded\r\n  \\return          1  Function failed\r\n */\r\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r\n  #define __STREXB(value, ptr)                                                 __strex(value, ptr)\r\n#else\r\n  #define __STREXB(value, ptr)   _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") __strex(value, ptr)        _Pragma(\"pop\")\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   STR Exclusive (16 bit)\r\n  \\details Executes a exclusive STR instruction for 16 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n  \\return          0  Function succeeded\r\n  \\return          1  Function failed\r\n */\r\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r\n  #define __STREXH(value, ptr)                                                 __strex(value, ptr)\r\n#else\r\n  #define __STREXH(value, ptr)   _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") __strex(value, ptr)        _Pragma(\"pop\")\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   STR Exclusive (32 bit)\r\n  \\details Executes a exclusive STR instruction for 32 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n  \\return          0  Function succeeded\r\n  \\return          1  Function failed\r\n */\r\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r\n  #define __STREXW(value, ptr)                                                 __strex(value, ptr)\r\n#else\r\n  #define __STREXW(value, ptr)   _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") __strex(value, ptr)        _Pragma(\"pop\")\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Remove the exclusive lock\r\n  \\details Removes the exclusive lock which is created by LDREX.\r\n */\r\n#define __CLREX                           __clrex\r\n\r\n\r\n/**\r\n  \\brief   Signed Saturate\r\n  \\details Saturates a signed value.\r\n  \\param [in]  value  Value to be saturated\r\n  \\param [in]    sat  Bit position to saturate to (1..32)\r\n  \\return             Saturated value\r\n */\r\n#define __SSAT                            __ssat\r\n\r\n\r\n/**\r\n  \\brief   Unsigned Saturate\r\n  \\details Saturates an unsigned value.\r\n  \\param [in]  value  Value to be saturated\r\n  \\param [in]    sat  Bit position to saturate to (0..31)\r\n  \\return             Saturated value\r\n */\r\n#define __USAT                            __usat\r\n\r\n\r\n/**\r\n  \\brief   Rotate Right with Extend (32 bit)\r\n  \\details Moves each bit of a bitstring right by one bit.\r\n           The carry input is shifted in at the left end of the bitstring.\r\n  \\param [in]    value  Value to rotate\r\n  \\return               Rotated value\r\n */\r\n#ifndef __NO_EMBEDDED_ASM\r\n__attribute__((section(\".rrx_text\"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)\r\n{\r\n  rrx r0, r0\r\n  bx lr\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   LDRT Unprivileged (8 bit)\r\n  \\details Executes a Unprivileged LDRT instruction for 8 bit value.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return             value of type uint8_t at (*ptr)\r\n */\r\n#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))\r\n\r\n\r\n/**\r\n  \\brief   LDRT Unprivileged (16 bit)\r\n  \\details Executes a Unprivileged LDRT instruction for 16 bit values.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return        value of type uint16_t at (*ptr)\r\n */\r\n#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))\r\n\r\n\r\n/**\r\n  \\brief   LDRT Unprivileged (32 bit)\r\n  \\details Executes a Unprivileged LDRT instruction for 32 bit values.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return        value of type uint32_t at (*ptr)\r\n */\r\n#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))\r\n\r\n\r\n/**\r\n  \\brief   STRT Unprivileged (8 bit)\r\n  \\details Executes a Unprivileged STRT instruction for 8 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n */\r\n#define __STRBT(value, ptr)               __strt(value, ptr)\r\n\r\n\r\n/**\r\n  \\brief   STRT Unprivileged (16 bit)\r\n  \\details Executes a Unprivileged STRT instruction for 16 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n */\r\n#define __STRHT(value, ptr)               __strt(value, ptr)\r\n\r\n\r\n/**\r\n  \\brief   STRT Unprivileged (32 bit)\r\n  \\details Executes a Unprivileged STRT instruction for 32 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n */\r\n#define __STRT(value, ptr)                __strt(value, ptr)\r\n\r\n#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */\r\n\r\n/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r\n\r\n\r\n/* ###################  Compiler specific Intrinsics  ########################### */\r\n/** \\defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r\n  Access to dedicated SIMD instructions\r\n  @{\r\n*/\r\n\r\n#if (__CORTEX_M >= 0x04U)  /* only for Cortex-M4 and above */\r\n\r\n#define __SADD8                           __sadd8\r\n#define __QADD8                           __qadd8\r\n#define __SHADD8                          __shadd8\r\n#define __UADD8                           __uadd8\r\n#define __UQADD8                          __uqadd8\r\n#define __UHADD8                          __uhadd8\r\n#define __SSUB8                           __ssub8\r\n#define __QSUB8                           __qsub8\r\n#define __SHSUB8                          __shsub8\r\n#define __USUB8                           __usub8\r\n#define __UQSUB8                          __uqsub8\r\n#define __UHSUB8                          __uhsub8\r\n#define __SADD16                          __sadd16\r\n#define __QADD16                          __qadd16\r\n#define __SHADD16                         __shadd16\r\n#define __UADD16                          __uadd16\r\n#define __UQADD16                         __uqadd16\r\n#define __UHADD16                         __uhadd16\r\n#define __SSUB16                          __ssub16\r\n#define __QSUB16                          __qsub16\r\n#define __SHSUB16                         __shsub16\r\n#define __USUB16                          __usub16\r\n#define __UQSUB16                         __uqsub16\r\n#define __UHSUB16                         __uhsub16\r\n#define __SASX                            __sasx\r\n#define __QASX                            __qasx\r\n#define __SHASX                           __shasx\r\n#define __UASX                            __uasx\r\n#define __UQASX                           __uqasx\r\n#define __UHASX                           __uhasx\r\n#define __SSAX                            __ssax\r\n#define __QSAX                            __qsax\r\n#define __SHSAX                           __shsax\r\n#define __USAX                            __usax\r\n#define __UQSAX                           __uqsax\r\n#define __UHSAX                           __uhsax\r\n#define __USAD8                           __usad8\r\n#define __USADA8                          __usada8\r\n#define __SSAT16                          __ssat16\r\n#define __USAT16                          __usat16\r\n#define __UXTB16                          __uxtb16\r\n#define __UXTAB16                         __uxtab16\r\n#define __SXTB16                          __sxtb16\r\n#define __SXTAB16                         __sxtab16\r\n#define __SMUAD                           __smuad\r\n#define __SMUADX                          __smuadx\r\n#define __SMLAD                           __smlad\r\n#define __SMLADX                          __smladx\r\n#define __SMLALD                          __smlald\r\n#define __SMLALDX                         __smlaldx\r\n#define __SMUSD                           __smusd\r\n#define __SMUSDX                          __smusdx\r\n#define __SMLSD                           __smlsd\r\n#define __SMLSDX                          __smlsdx\r\n#define __SMLSLD                          __smlsld\r\n#define __SMLSLDX                         __smlsldx\r\n#define __SEL                             __sel\r\n#define __QADD                            __qadd\r\n#define __QSUB                            __qsub\r\n\r\n#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \\\r\n                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )\r\n\r\n#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \\\r\n                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )\r\n\r\n#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \\\r\n                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))\r\n\r\n#endif /* (__CORTEX_M >= 0x04) */\r\n/*@} end of group CMSIS_SIMD_intrinsics */\r\n\r\n\r\n#endif /* __CMSIS_ARMCC_H */\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/bsp/opencr/include/cmsis_armcc_V6.h",
    "content": "/**************************************************************************//**\r\n * @file     cmsis_armcc_V6.h\r\n * @brief    CMSIS Cortex-M Core Function/Instruction Header File\r\n * @version  V4.30\r\n * @date     20. October 2015\r\n ******************************************************************************/\r\n/* Copyright (c) 2009 - 2015 ARM LIMITED\r\n\r\n   All rights reserved.\r\n   Redistribution and use in source and binary forms, with or without\r\n   modification, are permitted provided that the following conditions are met:\r\n   - Redistributions of source code must retain the above copyright\r\n     notice, this list of conditions and the following disclaimer.\r\n   - Redistributions in binary form must reproduce the above copyright\r\n     notice, this list of conditions and the following disclaimer in the\r\n     documentation and/or other materials provided with the distribution.\r\n   - Neither the name of ARM nor the names of its contributors may be used\r\n     to endorse or promote products derived from this software without\r\n     specific prior written permission.\r\n   *\r\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n   POSSIBILITY OF SUCH DAMAGE.\r\n   ---------------------------------------------------------------------------*/\r\n\r\n\r\n#ifndef __CMSIS_ARMCC_V6_H\r\n#define __CMSIS_ARMCC_V6_H\r\n\r\n\r\n/* ###########################  Core Function Access  ########################### */\r\n/** \\ingroup  CMSIS_Core_FunctionInterface\r\n    \\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief   Enable IRQ Interrupts\r\n  \\details Enables IRQ interrupts by clearing the I-bit in the CPSR.\r\n           Can only be executed in Privileged modes.\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)\r\n{\r\n  __ASM volatile (\"cpsie i\" : : : \"memory\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Disable IRQ Interrupts\r\n  \\details Disables IRQ interrupts by setting the I-bit in the CPSR.\r\n           Can only be executed in Privileged modes.\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)\r\n{\r\n  __ASM volatile (\"cpsid i\" : : : \"memory\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Control Register\r\n  \\details Returns the content of the Control Register.\r\n  \\return               Control Register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, control\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Get Control Register (non-secure)\r\n  \\details Returns the content of the non-secure Control Register when in secure mode.\r\n  \\return               non-secure Control Register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, control_ns\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Set Control Register\r\n  \\details Writes the given value to the Control Register.\r\n  \\param [in]    control  Control Register value to set\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)\r\n{\r\n  __ASM volatile (\"MSR control, %0\" : : \"r\" (control) : \"memory\");\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Set Control Register (non-secure)\r\n  \\details Writes the given value to the non-secure Control Register when in secure state.\r\n  \\param [in]    control  Control Register value to set\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)\r\n{\r\n  __ASM volatile (\"MSR control_ns, %0\" : : \"r\" (control) : \"memory\");\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Get IPSR Register\r\n  \\details Returns the content of the IPSR Register.\r\n  \\return               IPSR Register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, ipsr\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Get IPSR Register (non-secure)\r\n  \\details Returns the content of the non-secure IPSR Register when in secure state.\r\n  \\return               IPSR Register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, ipsr_ns\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Get APSR Register\r\n  \\details Returns the content of the APSR Register.\r\n  \\return               APSR Register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, apsr\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Get APSR Register (non-secure)\r\n  \\details Returns the content of the non-secure APSR Register when in secure state.\r\n  \\return               APSR Register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, apsr_ns\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Get xPSR Register\r\n  \\details Returns the content of the xPSR Register.\r\n  \\return               xPSR Register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, xpsr\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Get xPSR Register (non-secure)\r\n  \\details Returns the content of the non-secure xPSR Register when in secure state.\r\n  \\return               xPSR Register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, xpsr_ns\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Get Process Stack Pointer\r\n  \\details Returns the current value of the Process Stack Pointer (PSP).\r\n  \\return               PSP Register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)\r\n{\r\n  register uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, psp\"  : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Get Process Stack Pointer (non-secure)\r\n  \\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.\r\n  \\return               PSP Register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)\r\n{\r\n  register uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, psp_ns\"  : \"=r\" (result) );\r\n  return(result);\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Set Process Stack Pointer\r\n  \\details Assigns the given value to the Process Stack Pointer (PSP).\r\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r\n{\r\n  __ASM volatile (\"MSR psp, %0\" : : \"r\" (topOfProcStack) : \"sp\");\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Set Process Stack Pointer (non-secure)\r\n  \\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.\r\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)\r\n{\r\n  __ASM volatile (\"MSR psp_ns, %0\" : : \"r\" (topOfProcStack) : \"sp\");\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Get Main Stack Pointer\r\n  \\details Returns the current value of the Main Stack Pointer (MSP).\r\n  \\return               MSP Register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)\r\n{\r\n  register uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, msp\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Get Main Stack Pointer (non-secure)\r\n  \\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.\r\n  \\return               MSP Register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)\r\n{\r\n  register uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, msp_ns\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Set Main Stack Pointer\r\n  \\details Assigns the given value to the Main Stack Pointer (MSP).\r\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r\n{\r\n  __ASM volatile (\"MSR msp, %0\" : : \"r\" (topOfMainStack) : \"sp\");\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Set Main Stack Pointer (non-secure)\r\n  \\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.\r\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)\r\n{\r\n  __ASM volatile (\"MSR msp_ns, %0\" : : \"r\" (topOfMainStack) : \"sp\");\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Get Priority Mask\r\n  \\details Returns the current state of the priority mask bit from the Priority Mask Register.\r\n  \\return               Priority Mask value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, primask\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Get Priority Mask (non-secure)\r\n  \\details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.\r\n  \\return               Priority Mask value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, primask_ns\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Set Priority Mask\r\n  \\details Assigns the given value to the Priority Mask Register.\r\n  \\param [in]    priMask  Priority Mask\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r\n{\r\n  __ASM volatile (\"MSR primask, %0\" : : \"r\" (priMask) : \"memory\");\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Set Priority Mask (non-secure)\r\n  \\details Assigns the given value to the non-secure Priority Mask Register when in secure state.\r\n  \\param [in]    priMask  Priority Mask\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)\r\n{\r\n  __ASM volatile (\"MSR primask_ns, %0\" : : \"r\" (priMask) : \"memory\");\r\n}\r\n#endif\r\n\r\n\r\n#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U))  /* ToDo:  ARMCC_V6: check if this is ok for cortex >=3 */\r\n\r\n/**\r\n  \\brief   Enable FIQ\r\n  \\details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r\n           Can only be executed in Privileged modes.\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)\r\n{\r\n  __ASM volatile (\"cpsie f\" : : : \"memory\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Disable FIQ\r\n  \\details Disables FIQ interrupts by setting the F-bit in the CPSR.\r\n           Can only be executed in Privileged modes.\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)\r\n{\r\n  __ASM volatile (\"cpsid f\" : : : \"memory\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Base Priority\r\n  \\details Returns the current value of the Base Priority register.\r\n  \\return               Base Priority register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, basepri\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Get Base Priority (non-secure)\r\n  \\details Returns the current value of the non-secure Base Priority register when in secure state.\r\n  \\return               Base Priority register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, basepri_ns\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Set Base Priority\r\n  \\details Assigns the given value to the Base Priority register.\r\n  \\param [in]    basePri  Base Priority value to set\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value)\r\n{\r\n  __ASM volatile (\"MSR basepri, %0\" : : \"r\" (value) : \"memory\");\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Set Base Priority (non-secure)\r\n  \\details Assigns the given value to the non-secure Base Priority register when in secure state.\r\n  \\param [in]    basePri  Base Priority value to set\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value)\r\n{\r\n  __ASM volatile (\"MSR basepri_ns, %0\" : : \"r\" (value) : \"memory\");\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Set Base Priority with condition\r\n  \\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r\n           or the new value increases the BASEPRI priority level.\r\n  \\param [in]    basePri  Base Priority value to set\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)\r\n{\r\n  __ASM volatile (\"MSR basepri_max, %0\" : : \"r\" (value) : \"memory\");\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Set Base Priority with condition (non_secure)\r\n  \\details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled,\r\n\t       or the new value increases the BASEPRI priority level.\r\n  \\param [in]    basePri  Base Priority value to set\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value)\r\n{\r\n  __ASM volatile (\"MSR basepri_max_ns, %0\" : : \"r\" (value) : \"memory\");\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Get Fault Mask\r\n  \\details Returns the current value of the Fault Mask register.\r\n  \\return               Fault Mask register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, faultmask\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Get Fault Mask (non-secure)\r\n  \\details Returns the current value of the non-secure Fault Mask register when in secure state.\r\n  \\return               Fault Mask register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, faultmask_ns\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Set Fault Mask\r\n  \\details Assigns the given value to the Fault Mask register.\r\n  \\param [in]    faultMask  Fault Mask value to set\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r\n{\r\n  __ASM volatile (\"MSR faultmask, %0\" : : \"r\" (faultMask) : \"memory\");\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Set Fault Mask (non-secure)\r\n  \\details Assigns the given value to the non-secure Fault Mask register when in secure state.\r\n  \\param [in]    faultMask  Fault Mask value to set\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)\r\n{\r\n  __ASM volatile (\"MSR faultmask_ns, %0\" : : \"r\" (faultMask) : \"memory\");\r\n}\r\n#endif\r\n\r\n\r\n#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */\r\n\r\n\r\n#if (__ARM_ARCH_8M__ == 1U)\r\n\r\n/**\r\n  \\brief   Get Process Stack Pointer Limit\r\n  \\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).\r\n  \\return               PSPLIM Register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)\r\n{\r\n  register uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, psplim\"  : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M')     /* ToDo:  ARMCC_V6: check predefined macro for mainline */\r\n/**\r\n  \\brief   Get Process Stack Pointer Limit (non-secure)\r\n  \\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\r\n  \\return               PSPLIM Register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)\r\n{\r\n  register uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, psplim_ns\"  : \"=r\" (result) );\r\n  return(result);\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Set Process Stack Pointer Limit\r\n  \\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).\r\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)\r\n{\r\n  __ASM volatile (\"MSR psplim, %0\" : : \"r\" (ProcStackPtrLimit));\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M')     /* ToDo:  ARMCC_V6: check predefined macro for mainline */\r\n/**\r\n  \\brief   Set Process Stack Pointer (non-secure)\r\n  \\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\r\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)\r\n{\r\n  __ASM volatile (\"MSR psplim_ns, %0\\n\" : : \"r\" (ProcStackPtrLimit));\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Get Main Stack Pointer Limit\r\n  \\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).\r\n  \\return               MSPLIM Register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)\r\n{\r\n  register uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, msplim\" : \"=r\" (result) );\r\n\r\n  return(result);\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M')     /* ToDo:  ARMCC_V6: check predefined macro for mainline */\r\n/**\r\n  \\brief   Get Main Stack Pointer Limit (non-secure)\r\n  \\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.\r\n  \\return               MSPLIM Register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)\r\n{\r\n  register uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, msplim_ns\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Set Main Stack Pointer Limit\r\n  \\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).\r\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)\r\n{\r\n  __ASM volatile (\"MSR msplim, %0\" : : \"r\" (MainStackPtrLimit));\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M')     /* ToDo:  ARMCC_V6: check predefined macro for mainline */\r\n/**\r\n  \\brief   Set Main Stack Pointer Limit (non-secure)\r\n  \\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.\r\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer value to set\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)\r\n{\r\n  __ASM volatile (\"MSR msplim_ns, %0\" : : \"r\" (MainStackPtrLimit));\r\n}\r\n#endif\r\n\r\n#endif /* (__ARM_ARCH_8M__ == 1U) */\r\n\r\n\r\n#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U))  /* ToDo:  ARMCC_V6: check if this is ok for cortex >=4 */\r\n\r\n/**\r\n  \\brief   Get FPSCR\r\n  \\details eturns the current value of the Floating Point Status/Control register.\r\n  \\return               Floating Point Status/Control register value\r\n */\r\n#define __get_FPSCR      __builtin_arm_get_fpscr\r\n#if 0\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)\r\n{\r\n#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"\");                                 /* Empty asm statement works as a scheduling barrier */\r\n  __ASM volatile (\"VMRS %0, fpscr\" : \"=r\" (result) );\r\n  __ASM volatile (\"\");\r\n  return(result);\r\n#else\r\n   return(0);\r\n#endif\r\n}\r\n#endif\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Get FPSCR (non-secure)\r\n  \\details Returns the current value of the non-secure Floating Point Status/Control register when in secure state.\r\n  \\return               Floating Point Status/Control register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void)\r\n{\r\n#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"\");                                 /* Empty asm statement works as a scheduling barrier */\r\n  __ASM volatile (\"VMRS %0, fpscr_ns\" : \"=r\" (result) );\r\n  __ASM volatile (\"\");\r\n  return(result);\r\n#else\r\n   return(0);\r\n#endif\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Set FPSCR\r\n  \\details Assigns the given value to the Floating Point Status/Control register.\r\n  \\param [in]    fpscr  Floating Point Status/Control value to set\r\n */\r\n#define __set_FPSCR      __builtin_arm_set_fpscr\r\n#if 0\r\n__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r\n{\r\n#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r\n  __ASM volatile (\"\");                                 /* Empty asm statement works as a scheduling barrier */\r\n  __ASM volatile (\"VMSR fpscr, %0\" : : \"r\" (fpscr) : \"vfpcc\");\r\n  __ASM volatile (\"\");\r\n#endif\r\n}\r\n#endif\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Set FPSCR (non-secure)\r\n  \\details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state.\r\n  \\param [in]    fpscr  Floating Point Status/Control value to set\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr)\r\n{\r\n#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r\n  __ASM volatile (\"\");                                 /* Empty asm statement works as a scheduling barrier */\r\n  __ASM volatile (\"VMSR fpscr_ns, %0\" : : \"r\" (fpscr) : \"vfpcc\");\r\n  __ASM volatile (\"\");\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */\r\n\r\n\r\n\r\n/*@} end of CMSIS_Core_RegAccFunctions */\r\n\r\n\r\n/* ##########################  Core Instruction Access  ######################### */\r\n/** \\defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r\n  Access to dedicated instructions\r\n  @{\r\n*/\r\n\r\n/* Define macros for porting to both thumb1 and thumb2.\r\n * For thumb1, use low register (r0-r7), specified by constraint \"l\"\r\n * Otherwise, use general registers, specified by constraint \"r\" */\r\n#if defined (__thumb__) && !defined (__thumb2__)\r\n#define __CMSIS_GCC_OUT_REG(r) \"=l\" (r)\r\n#define __CMSIS_GCC_USE_REG(r) \"l\" (r)\r\n#else\r\n#define __CMSIS_GCC_OUT_REG(r) \"=r\" (r)\r\n#define __CMSIS_GCC_USE_REG(r) \"r\" (r)\r\n#endif\r\n\r\n/**\r\n  \\brief   No Operation\r\n  \\details No Operation does nothing. This instruction can be used for code alignment purposes.\r\n */\r\n#define __NOP          __builtin_arm_nop\r\n\r\n/**\r\n  \\brief   Wait For Interrupt\r\n  \\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r\n */\r\n#define __WFI          __builtin_arm_wfi\r\n\r\n\r\n/**\r\n  \\brief   Wait For Event\r\n  \\details Wait For Event is a hint instruction that permits the processor to enter\r\n           a low-power state until one of a number of events occurs.\r\n */\r\n#define __WFE          __builtin_arm_wfe\r\n\r\n\r\n/**\r\n  \\brief   Send Event\r\n  \\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r\n */\r\n#define __SEV          __builtin_arm_sev\r\n\r\n\r\n/**\r\n  \\brief   Instruction Synchronization Barrier\r\n  \\details Instruction Synchronization Barrier flushes the pipeline in the processor,\r\n           so that all instructions following the ISB are fetched from cache or memory,\r\n           after the instruction has been completed.\r\n */\r\n#define __ISB()        __builtin_arm_isb(0xF);\r\n\r\n/**\r\n  \\brief   Data Synchronization Barrier\r\n  \\details Acts as a special kind of Data Memory Barrier.\r\n           It completes when all explicit memory accesses before this instruction complete.\r\n */\r\n#define __DSB()        __builtin_arm_dsb(0xF);\r\n\r\n\r\n/**\r\n  \\brief   Data Memory Barrier\r\n  \\details Ensures the apparent order of the explicit memory operations before\r\n           and after the instruction, without ensuring their completion.\r\n */\r\n#define __DMB()        __builtin_arm_dmb(0xF);\r\n\r\n\r\n/**\r\n  \\brief   Reverse byte order (32 bit)\r\n  \\details Reverses the byte order in integer value.\r\n  \\param [in]    value  Value to reverse\r\n  \\return               Reversed value\r\n */\r\n#define __REV          __builtin_bswap32\r\n\r\n\r\n/**\r\n  \\brief   Reverse byte order (16 bit)\r\n  \\details Reverses the byte order in two unsigned short values.\r\n  \\param [in]    value  Value to reverse\r\n  \\return               Reversed value\r\n */\r\n#define __REV16          __builtin_bswap16                           /* ToDo:  ARMCC_V6: check if __builtin_bswap16 could be used */\r\n#if 0\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"rev16 %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r\n  return(result);\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Reverse byte order in signed short value\r\n  \\details Reverses the byte order in a signed short value with sign extension to integer.\r\n  \\param [in]    value  Value to reverse\r\n  \\return               Reversed value\r\n */\r\n                                                          /* ToDo:  ARMCC_V6: check if __builtin_bswap16 could be used */\r\n__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)\r\n{\r\n  int32_t result;\r\n\r\n  __ASM volatile (\"revsh %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r\n  return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Rotate Right in unsigned value (32 bit)\r\n  \\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r\n  \\param [in]    op1  Value to rotate\r\n  \\param [in]    op2  Number of Bits to rotate\r\n  \\return               Rotated value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r\n{\r\n  return (op1 >> op2) | (op1 << (32U - op2));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Breakpoint\r\n  \\details Causes the processor to enter Debug state.\r\n            Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r\n    \\param [in]    value  is ignored by the processor.\r\n                   If required, a debugger can use it to store additional information about the breakpoint.\r\n */\r\n#define __BKPT(value)                       __ASM volatile (\"bkpt \"#value)\r\n\r\n\r\n/**\r\n  \\brief   Reverse bit order of value\r\n  \\details Reverses the bit order of the given value.\r\n  \\param [in]    value  Value to reverse\r\n  \\return               Reversed value\r\n */\r\n                                                          /* ToDo:  ARMCC_V6: check if __builtin_arm_rbit is supported */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r\n{\r\n  uint32_t result;\r\n\r\n#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U))  /* ToDo:  ARMCC_V6: check if this is ok for cortex >=3 */\r\n   __ASM volatile (\"rbit %0, %1\" : \"=r\" (result) : \"r\" (value) );\r\n#else\r\n  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */\r\n\r\n  result = value;                      /* r will be reversed bits of v; first get LSB of v */\r\n  for (value >>= 1U; value; value >>= 1U)\r\n  {\r\n    result <<= 1U;\r\n    result |= value & 1U;\r\n    s--;\r\n  }\r\n  result <<= s;                        /* shift when v's highest bits are zero */\r\n#endif\r\n  return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Count leading zeros\r\n  \\details Counts the number of leading zeros of a data value.\r\n  \\param [in]  value  Value to count the leading zeros\r\n  \\return             number of leading zeros in value\r\n */\r\n#define __CLZ             __builtin_clz\r\n\r\n\r\n#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U))  /* ToDo:  ARMCC_V6: check if this is ok for cortex >=3 */\r\n\r\n/**\r\n  \\brief   LDR Exclusive (8 bit)\r\n  \\details Executes a exclusive LDR instruction for 8 bit value.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return             value of type uint8_t at (*ptr)\r\n */\r\n#define __LDREXB        (uint8_t)__builtin_arm_ldrex\r\n\r\n\r\n/**\r\n  \\brief   LDR Exclusive (16 bit)\r\n  \\details Executes a exclusive LDR instruction for 16 bit values.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return        value of type uint16_t at (*ptr)\r\n */\r\n#define __LDREXH        (uint16_t)__builtin_arm_ldrex\r\n\r\n\r\n/**\r\n  \\brief   LDR Exclusive (32 bit)\r\n  \\details Executes a exclusive LDR instruction for 32 bit values.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return        value of type uint32_t at (*ptr)\r\n */\r\n#define __LDREXW        (uint32_t)__builtin_arm_ldrex\r\n\r\n\r\n/**\r\n  \\brief   STR Exclusive (8 bit)\r\n  \\details Executes a exclusive STR instruction for 8 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n  \\return          0  Function succeeded\r\n  \\return          1  Function failed\r\n */\r\n#define __STREXB        (uint32_t)__builtin_arm_strex\r\n\r\n\r\n/**\r\n  \\brief   STR Exclusive (16 bit)\r\n  \\details Executes a exclusive STR instruction for 16 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n  \\return          0  Function succeeded\r\n  \\return          1  Function failed\r\n */\r\n#define __STREXH        (uint32_t)__builtin_arm_strex\r\n\r\n\r\n/**\r\n  \\brief   STR Exclusive (32 bit)\r\n  \\details Executes a exclusive STR instruction for 32 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n  \\return          0  Function succeeded\r\n  \\return          1  Function failed\r\n */\r\n#define __STREXW        (uint32_t)__builtin_arm_strex\r\n\r\n\r\n/**\r\n  \\brief   Remove the exclusive lock\r\n  \\details Removes the exclusive lock which is created by LDREX.\r\n */\r\n#define __CLREX             __builtin_arm_clrex\r\n\r\n\r\n/**\r\n  \\brief   Signed Saturate\r\n  \\details Saturates a signed value.\r\n  \\param [in]  value  Value to be saturated\r\n  \\param [in]    sat  Bit position to saturate to (1..32)\r\n  \\return             Saturated value\r\n */\r\n/*#define __SSAT             __builtin_arm_ssat*/\r\n#define __SSAT(ARG1,ARG2) \\\r\n({                          \\\r\n  int32_t __RES, __ARG1 = (ARG1); \\\r\n  __ASM (\"ssat %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\r\n  __RES; \\\r\n })\r\n\r\n\r\n/**\r\n  \\brief   Unsigned Saturate\r\n  \\details Saturates an unsigned value.\r\n  \\param [in]  value  Value to be saturated\r\n  \\param [in]    sat  Bit position to saturate to (0..31)\r\n  \\return             Saturated value\r\n */\r\n#define __USAT             __builtin_arm_usat\r\n#if 0\r\n#define __USAT(ARG1,ARG2) \\\r\n({                          \\\r\n  uint32_t __RES, __ARG1 = (ARG1); \\\r\n  __ASM (\"usat %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\r\n  __RES; \\\r\n })\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Rotate Right with Extend (32 bit)\r\n  \\details Moves each bit of a bitstring right by one bit.\r\n           The carry input is shifted in at the left end of the bitstring.\r\n  \\param [in]    value  Value to rotate\r\n  \\return               Rotated value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"rrx %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r\n  return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   LDRT Unprivileged (8 bit)\r\n  \\details Executes a Unprivileged LDRT instruction for 8 bit value.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return             value of type uint8_t at (*ptr)\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)\r\n{\r\n    uint32_t result;\r\n\r\n   __ASM volatile (\"ldrbt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\r\n   return ((uint8_t) result);    /* Add explicit type cast here */\r\n}\r\n\r\n\r\n/**\r\n  \\brief   LDRT Unprivileged (16 bit)\r\n  \\details Executes a Unprivileged LDRT instruction for 16 bit values.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return        value of type uint16_t at (*ptr)\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)\r\n{\r\n    uint32_t result;\r\n\r\n   __ASM volatile (\"ldrht %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\r\n   return ((uint16_t) result);    /* Add explicit type cast here */\r\n}\r\n\r\n\r\n/**\r\n  \\brief   LDRT Unprivileged (32 bit)\r\n  \\details Executes a Unprivileged LDRT instruction for 32 bit values.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return        value of type uint32_t at (*ptr)\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)\r\n{\r\n    uint32_t result;\r\n\r\n   __ASM volatile (\"ldrt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\r\n   return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   STRT Unprivileged (8 bit)\r\n  \\details Executes a Unprivileged STRT instruction for 8 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\r\n{\r\n   __ASM volatile (\"strbt %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\r\n}\r\n\r\n\r\n/**\r\n  \\brief   STRT Unprivileged (16 bit)\r\n  \\details Executes a Unprivileged STRT instruction for 16 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\r\n{\r\n   __ASM volatile (\"strht %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\r\n}\r\n\r\n\r\n/**\r\n  \\brief   STRT Unprivileged (32 bit)\r\n  \\details Executes a Unprivileged STRT instruction for 32 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\r\n{\r\n   __ASM volatile (\"strt %1, %0\" : \"=Q\" (*ptr) : \"r\" (value) );\r\n}\r\n\r\n#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */\r\n\r\n\r\n#if (__ARM_ARCH_8M__ == 1U)\r\n\r\n/**\r\n  \\brief   Load-Acquire (8 bit)\r\n  \\details Executes a LDAB instruction for 8 bit value.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return             value of type uint8_t at (*ptr)\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)\r\n{\r\n    uint32_t result;\r\n\r\n   __ASM volatile (\"ldab %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\r\n   return ((uint8_t) result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Load-Acquire (16 bit)\r\n  \\details Executes a LDAH instruction for 16 bit values.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return        value of type uint16_t at (*ptr)\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)\r\n{\r\n    uint32_t result;\r\n\r\n   __ASM volatile (\"ldah %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\r\n   return ((uint16_t) result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Load-Acquire (32 bit)\r\n  \\details Executes a LDA instruction for 32 bit values.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return        value of type uint32_t at (*ptr)\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)\r\n{\r\n    uint32_t result;\r\n\r\n   __ASM volatile (\"lda %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\r\n   return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Store-Release (8 bit)\r\n  \\details Executes a STLB instruction for 8 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)\r\n{\r\n   __ASM volatile (\"stlb %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Store-Release (16 bit)\r\n  \\details Executes a STLH instruction for 16 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)\r\n{\r\n   __ASM volatile (\"stlh %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Store-Release (32 bit)\r\n  \\details Executes a STL instruction for 32 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)\r\n{\r\n   __ASM volatile (\"stl %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Load-Acquire Exclusive (8 bit)\r\n  \\details Executes a LDAB exclusive instruction for 8 bit value.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return             value of type uint8_t at (*ptr)\r\n */\r\n#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex\r\n\r\n\r\n/**\r\n  \\brief   Load-Acquire Exclusive (16 bit)\r\n  \\details Executes a LDAH exclusive instruction for 16 bit values.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return        value of type uint16_t at (*ptr)\r\n */\r\n#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex\r\n\r\n\r\n/**\r\n  \\brief   Load-Acquire Exclusive (32 bit)\r\n  \\details Executes a LDA exclusive instruction for 32 bit values.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return        value of type uint32_t at (*ptr)\r\n */\r\n#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex\r\n\r\n\r\n/**\r\n  \\brief   Store-Release Exclusive (8 bit)\r\n  \\details Executes a STLB exclusive instruction for 8 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n  \\return          0  Function succeeded\r\n  \\return          1  Function failed\r\n */\r\n#define     __STLEXB                 (uint32_t)__builtin_arm_stlex\r\n\r\n\r\n/**\r\n  \\brief   Store-Release Exclusive (16 bit)\r\n  \\details Executes a STLH exclusive instruction for 16 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n  \\return          0  Function succeeded\r\n  \\return          1  Function failed\r\n */\r\n#define     __STLEXH                 (uint32_t)__builtin_arm_stlex\r\n\r\n\r\n/**\r\n  \\brief   Store-Release Exclusive (32 bit)\r\n  \\details Executes a STL exclusive instruction for 32 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n  \\return          0  Function succeeded\r\n  \\return          1  Function failed\r\n */\r\n#define     __STLEX                  (uint32_t)__builtin_arm_stlex\r\n\r\n#endif /* (__ARM_ARCH_8M__ == 1U) */\r\n\r\n/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r\n\r\n\r\n/* ###################  Compiler specific Intrinsics  ########################### */\r\n/** \\defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r\n  Access to dedicated SIMD instructions\r\n  @{\r\n*/\r\n\r\n#if (__ARM_FEATURE_DSP == 1U)        /* ToDo:  ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"sadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"qadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"shadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uqadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uhadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"ssub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"qsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"shsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"usub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uqsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uhsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"sadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"qadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"shadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uqadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uhadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"ssub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"qsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"shsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"usub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uqsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uhsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"sasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"qasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"shasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uqasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uhasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"ssax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"qsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"shsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"usax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uqsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uhsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"usad8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"usada8 %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\r\n  return(result);\r\n}\r\n\r\n#define __SSAT16(ARG1,ARG2) \\\r\n({                          \\\r\n  uint32_t __RES, __ARG1 = (ARG1); \\\r\n  __ASM (\"ssat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\r\n  __RES; \\\r\n })\r\n\r\n#define __USAT16(ARG1,ARG2) \\\r\n({                          \\\r\n  uint32_t __RES, __ARG1 = (ARG1); \\\r\n  __ASM (\"usat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\r\n  __RES; \\\r\n })\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"sxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"sxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"smuad %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"smuadx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"smlad %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"smladx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\r\n{\r\n  union llreg_u{\r\n    uint32_t w32[2];\r\n    uint64_t w64;\r\n  } llr;\r\n  llr.w64 = acc;\r\n\r\n#ifndef __ARMEB__   /* Little endian */\r\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\r\n#else               /* Big endian */\r\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\r\n#endif\r\n\r\n  return(llr.w64);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\r\n{\r\n  union llreg_u{\r\n    uint32_t w32[2];\r\n    uint64_t w64;\r\n  } llr;\r\n  llr.w64 = acc;\r\n\r\n#ifndef __ARMEB__   /* Little endian */\r\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\r\n#else               /* Big endian */\r\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\r\n#endif\r\n\r\n  return(llr.w64);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"smusd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"smusdx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"smlsd %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"smlsdx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\r\n{\r\n  union llreg_u{\r\n    uint32_t w32[2];\r\n    uint64_t w64;\r\n  } llr;\r\n  llr.w64 = acc;\r\n\r\n#ifndef __ARMEB__   /* Little endian */\r\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\r\n#else               /* Big endian */\r\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\r\n#endif\r\n\r\n  return(llr.w64);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\r\n{\r\n  union llreg_u{\r\n    uint32_t w32[2];\r\n    uint64_t w64;\r\n  } llr;\r\n  llr.w64 = acc;\r\n\r\n#ifndef __ARMEB__   /* Little endian */\r\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\r\n#else               /* Big endian */\r\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\r\n#endif\r\n\r\n  return(llr.w64);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"sel %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE  int32_t __QADD( int32_t op1,  int32_t op2)\r\n{\r\n  int32_t result;\r\n\r\n  __ASM volatile (\"qadd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE  int32_t __QSUB( int32_t op1,  int32_t op2)\r\n{\r\n  int32_t result;\r\n\r\n  __ASM volatile (\"qsub %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n#define __PKHBT(ARG1,ARG2,ARG3) \\\r\n({                          \\\r\n  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\\r\n  __ASM (\"pkhbt %0, %1, %2, lsl %3\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2), \"I\" (ARG3)  ); \\\r\n  __RES; \\\r\n })\r\n\r\n#define __PKHTB(ARG1,ARG2,ARG3) \\\r\n({                          \\\r\n  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\\r\n  if (ARG3 == 0) \\\r\n    __ASM (\"pkhtb %0, %1, %2\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2)  ); \\\r\n  else \\\r\n    __ASM (\"pkhtb %0, %1, %2, asr %3\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2), \"I\" (ARG3)  ); \\\r\n  __RES; \\\r\n })\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\r\n{\r\n int32_t result;\r\n\r\n __ASM volatile (\"smmla %0, %1, %2, %3\" : \"=r\" (result): \"r\"  (op1), \"r\" (op2), \"r\" (op3) );\r\n return(result);\r\n}\r\n\r\n#endif /* (__ARM_FEATURE_DSP == 1U) */\r\n/*@} end of group CMSIS_SIMD_intrinsics */\r\n\r\n\r\n#endif /* __CMSIS_ARMCC_V6_H */\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/bsp/opencr/include/cmsis_gcc.h",
    "content": "/**************************************************************************//**\r\n * @file     cmsis_gcc.h\r\n * @brief    CMSIS Cortex-M Core Function/Instruction Header File\r\n * @version  V4.30\r\n * @date     20. October 2015\r\n ******************************************************************************/\r\n/* Copyright (c) 2009 - 2015 ARM LIMITED\r\n\r\n   All rights reserved.\r\n   Redistribution and use in source and binary forms, with or without\r\n   modification, are permitted provided that the following conditions are met:\r\n   - Redistributions of source code must retain the above copyright\r\n     notice, this list of conditions and the following disclaimer.\r\n   - Redistributions in binary form must reproduce the above copyright\r\n     notice, this list of conditions and the following disclaimer in the\r\n     documentation and/or other materials provided with the distribution.\r\n   - Neither the name of ARM nor the names of its contributors may be used\r\n     to endorse or promote products derived from this software without\r\n     specific prior written permission.\r\n   *\r\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n   POSSIBILITY OF SUCH DAMAGE.\r\n   ---------------------------------------------------------------------------*/\r\n\r\n\r\n#ifndef __CMSIS_GCC_H\r\n#define __CMSIS_GCC_H\r\n\r\n/* ignore some GCC warnings */\r\n#if defined ( __GNUC__ )\r\n#pragma GCC diagnostic push\r\n#pragma GCC diagnostic ignored \"-Wsign-conversion\"\r\n#pragma GCC diagnostic ignored \"-Wconversion\"\r\n#pragma GCC diagnostic ignored \"-Wunused-parameter\"\r\n#endif\r\n\r\n\r\n/* ###########################  Core Function Access  ########################### */\r\n/** \\ingroup  CMSIS_Core_FunctionInterface\r\n    \\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief   Enable IRQ Interrupts\r\n  \\details Enables IRQ interrupts by clearing the I-bit in the CPSR.\r\n           Can only be executed in Privileged modes.\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)\r\n{\r\n  __ASM volatile (\"cpsie i\" : : : \"memory\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Disable IRQ Interrupts\r\n  \\details Disables IRQ interrupts by setting the I-bit in the CPSR.\r\n  Can only be executed in Privileged modes.\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)\r\n{\r\n  __ASM volatile (\"cpsid i\" : : : \"memory\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Control Register\r\n  \\details Returns the content of the Control Register.\r\n  \\return               Control Register value\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, control\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Control Register\r\n  \\details Writes the given value to the Control Register.\r\n  \\param [in]    control  Control Register value to set\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)\r\n{\r\n  __ASM volatile (\"MSR control, %0\" : : \"r\" (control) : \"memory\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get IPSR Register\r\n  \\details Returns the content of the IPSR Register.\r\n  \\return               IPSR Register value\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, ipsr\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get APSR Register\r\n  \\details Returns the content of the APSR Register.\r\n  \\return               APSR Register value\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, apsr\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get xPSR Register\r\n  \\details Returns the content of the xPSR Register.\r\n\r\n    \\return               xPSR Register value\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, xpsr\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Process Stack Pointer\r\n  \\details Returns the current value of the Process Stack Pointer (PSP).\r\n  \\return               PSP Register value\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)\r\n{\r\n  register uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, psp\\n\"  : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Process Stack Pointer\r\n  \\details Assigns the given value to the Process Stack Pointer (PSP).\r\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r\n{\r\n  __ASM volatile (\"MSR psp, %0\\n\" : : \"r\" (topOfProcStack) : \"sp\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Main Stack Pointer\r\n  \\details Returns the current value of the Main Stack Pointer (MSP).\r\n  \\return               MSP Register value\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)\r\n{\r\n  register uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, msp\\n\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Main Stack Pointer\r\n  \\details Assigns the given value to the Main Stack Pointer (MSP).\r\n\r\n    \\param [in]    topOfMainStack  Main Stack Pointer value to set\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r\n{\r\n  __ASM volatile (\"MSR msp, %0\\n\" : : \"r\" (topOfMainStack) : \"sp\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Priority Mask\r\n  \\details Returns the current state of the priority mask bit from the Priority Mask Register.\r\n  \\return               Priority Mask value\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, primask\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Priority Mask\r\n  \\details Assigns the given value to the Priority Mask Register.\r\n  \\param [in]    priMask  Priority Mask\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r\n{\r\n  __ASM volatile (\"MSR primask, %0\" : : \"r\" (priMask) : \"memory\");\r\n}\r\n\r\n\r\n#if       (__CORTEX_M >= 0x03U)\r\n\r\n/**\r\n  \\brief   Enable FIQ\r\n  \\details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r\n           Can only be executed in Privileged modes.\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)\r\n{\r\n  __ASM volatile (\"cpsie f\" : : : \"memory\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Disable FIQ\r\n  \\details Disables FIQ interrupts by setting the F-bit in the CPSR.\r\n           Can only be executed in Privileged modes.\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)\r\n{\r\n  __ASM volatile (\"cpsid f\" : : : \"memory\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Base Priority\r\n  \\details Returns the current value of the Base Priority register.\r\n  \\return               Base Priority register value\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, basepri\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Base Priority\r\n  \\details Assigns the given value to the Base Priority register.\r\n  \\param [in]    basePri  Base Priority value to set\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)\r\n{\r\n  __ASM volatile (\"MSR basepri, %0\" : : \"r\" (value) : \"memory\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Base Priority with condition\r\n  \\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r\n           or the new value increases the BASEPRI priority level.\r\n  \\param [in]    basePri  Base Priority value to set\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)\r\n{\r\n  __ASM volatile (\"MSR basepri_max, %0\" : : \"r\" (value) : \"memory\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Fault Mask\r\n  \\details Returns the current value of the Fault Mask register.\r\n  \\return               Fault Mask register value\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, faultmask\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Fault Mask\r\n  \\details Assigns the given value to the Fault Mask register.\r\n  \\param [in]    faultMask  Fault Mask value to set\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r\n{\r\n  __ASM volatile (\"MSR faultmask, %0\" : : \"r\" (faultMask) : \"memory\");\r\n}\r\n\r\n#endif /* (__CORTEX_M >= 0x03U) */\r\n\r\n\r\n#if       (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)\r\n\r\n/**\r\n  \\brief   Get FPSCR\r\n  \\details Returns the current value of the Floating Point Status/Control register.\r\n  \\return               Floating Point Status/Control register value\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)\r\n{\r\n#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r\n  uint32_t result;\r\n\r\n  /* Empty asm statement works as a scheduling barrier */\r\n  __ASM volatile (\"\");\r\n  __ASM volatile (\"VMRS %0, fpscr\" : \"=r\" (result) );\r\n  __ASM volatile (\"\");\r\n  return(result);\r\n#else\r\n   return(0);\r\n#endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set FPSCR\r\n  \\details Assigns the given value to the Floating Point Status/Control register.\r\n  \\param [in]    fpscr  Floating Point Status/Control value to set\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r\n{\r\n#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r\n  /* Empty asm statement works as a scheduling barrier */\r\n  __ASM volatile (\"\");\r\n  __ASM volatile (\"VMSR fpscr, %0\" : : \"r\" (fpscr) : \"vfpcc\");\r\n  __ASM volatile (\"\");\r\n#endif\r\n}\r\n\r\n#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */\r\n\r\n\r\n\r\n/*@} end of CMSIS_Core_RegAccFunctions */\r\n\r\n\r\n/* ##########################  Core Instruction Access  ######################### */\r\n/** \\defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r\n  Access to dedicated instructions\r\n  @{\r\n*/\r\n\r\n/* Define macros for porting to both thumb1 and thumb2.\r\n * For thumb1, use low register (r0-r7), specified by constraint \"l\"\r\n * Otherwise, use general registers, specified by constraint \"r\" */\r\n#if defined (__thumb__) && !defined (__thumb2__)\r\n#define __CMSIS_GCC_OUT_REG(r) \"=l\" (r)\r\n#define __CMSIS_GCC_USE_REG(r) \"l\" (r)\r\n#else\r\n#define __CMSIS_GCC_OUT_REG(r) \"=r\" (r)\r\n#define __CMSIS_GCC_USE_REG(r) \"r\" (r)\r\n#endif\r\n\r\n/**\r\n  \\brief   No Operation\r\n  \\details No Operation does nothing. This instruction can be used for code alignment purposes.\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)\r\n{\r\n  __ASM volatile (\"nop\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Wait For Interrupt\r\n  \\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)\r\n{\r\n  __ASM volatile (\"wfi\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Wait For Event\r\n  \\details Wait For Event is a hint instruction that permits the processor to enter\r\n    a low-power state until one of a number of events occurs.\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)\r\n{\r\n  __ASM volatile (\"wfe\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Send Event\r\n  \\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)\r\n{\r\n  __ASM volatile (\"sev\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Instruction Synchronization Barrier\r\n  \\details Instruction Synchronization Barrier flushes the pipeline in the processor,\r\n           so that all instructions following the ISB are fetched from cache or memory,\r\n           after the instruction has been completed.\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)\r\n{\r\n  __ASM volatile (\"isb 0xF\":::\"memory\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Data Synchronization Barrier\r\n  \\details Acts as a special kind of Data Memory Barrier.\r\n           It completes when all explicit memory accesses before this instruction complete.\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)\r\n{\r\n  __ASM volatile (\"dsb 0xF\":::\"memory\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Data Memory Barrier\r\n  \\details Ensures the apparent order of the explicit memory operations before\r\n           and after the instruction, without ensuring their completion.\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)\r\n{\r\n  __ASM volatile (\"dmb 0xF\":::\"memory\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Reverse byte order (32 bit)\r\n  \\details Reverses the byte order in integer value.\r\n  \\param [in]    value  Value to reverse\r\n  \\return               Reversed value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)\r\n{\r\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\r\n  return __builtin_bswap32(value);\r\n#else\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"rev %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r\n  return(result);\r\n#endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Reverse byte order (16 bit)\r\n  \\details Reverses the byte order in two unsigned short values.\r\n  \\param [in]    value  Value to reverse\r\n  \\return               Reversed value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"rev16 %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r\n  return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Reverse byte order in signed short value\r\n  \\details Reverses the byte order in a signed short value with sign extension to integer.\r\n  \\param [in]    value  Value to reverse\r\n  \\return               Reversed value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)\r\n{\r\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r\n  return (short)__builtin_bswap16(value);\r\n#else\r\n  int32_t result;\r\n\r\n  __ASM volatile (\"revsh %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r\n  return(result);\r\n#endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Rotate Right in unsigned value (32 bit)\r\n  \\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r\n  \\param [in]    value  Value to rotate\r\n  \\param [in]    value  Number of Bits to rotate\r\n  \\return               Rotated value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r\n{\r\n  return (op1 >> op2) | (op1 << (32U - op2));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Breakpoint\r\n  \\details Causes the processor to enter Debug state.\r\n           Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r\n  \\param [in]    value  is ignored by the processor.\r\n                 If required, a debugger can use it to store additional information about the breakpoint.\r\n */\r\n#define __BKPT(value)                       __ASM volatile (\"bkpt \"#value)\r\n\r\n\r\n/**\r\n  \\brief   Reverse bit order of value\r\n  \\details Reverses the bit order of the given value.\r\n  \\param [in]    value  Value to reverse\r\n  \\return               Reversed value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r\n{\r\n  uint32_t result;\r\n\r\n#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\r\n   __ASM volatile (\"rbit %0, %1\" : \"=r\" (result) : \"r\" (value) );\r\n#else\r\n  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */\r\n\r\n  result = value;                      /* r will be reversed bits of v; first get LSB of v */\r\n  for (value >>= 1U; value; value >>= 1U)\r\n  {\r\n    result <<= 1U;\r\n    result |= value & 1U;\r\n    s--;\r\n  }\r\n  result <<= s;                        /* shift when v's highest bits are zero */\r\n#endif\r\n  return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Count leading zeros\r\n  \\details Counts the number of leading zeros of a data value.\r\n  \\param [in]  value  Value to count the leading zeros\r\n  \\return             number of leading zeros in value\r\n */\r\n#define __CLZ             __builtin_clz\r\n\r\n\r\n#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\r\n\r\n/**\r\n  \\brief   LDR Exclusive (8 bit)\r\n  \\details Executes a exclusive LDR instruction for 8 bit value.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return             value of type uint8_t at (*ptr)\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)\r\n{\r\n    uint32_t result;\r\n\r\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r\n   __ASM volatile (\"ldrexb %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\r\n#else\r\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\r\n       accepted by assembler. So has to use following less efficient pattern.\r\n    */\r\n   __ASM volatile (\"ldrexb %0, [%1]\" : \"=r\" (result) : \"r\" (addr) : \"memory\" );\r\n#endif\r\n   return ((uint8_t) result);    /* Add explicit type cast here */\r\n}\r\n\r\n\r\n/**\r\n  \\brief   LDR Exclusive (16 bit)\r\n  \\details Executes a exclusive LDR instruction for 16 bit values.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return        value of type uint16_t at (*ptr)\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)\r\n{\r\n    uint32_t result;\r\n\r\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r\n   __ASM volatile (\"ldrexh %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\r\n#else\r\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\r\n       accepted by assembler. So has to use following less efficient pattern.\r\n    */\r\n   __ASM volatile (\"ldrexh %0, [%1]\" : \"=r\" (result) : \"r\" (addr) : \"memory\" );\r\n#endif\r\n   return ((uint16_t) result);    /* Add explicit type cast here */\r\n}\r\n\r\n\r\n/**\r\n  \\brief   LDR Exclusive (32 bit)\r\n  \\details Executes a exclusive LDR instruction for 32 bit values.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return        value of type uint32_t at (*ptr)\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)\r\n{\r\n    uint32_t result;\r\n\r\n   __ASM volatile (\"ldrex %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\r\n   return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   STR Exclusive (8 bit)\r\n  \\details Executes a exclusive STR instruction for 8 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n  \\return          0  Function succeeded\r\n  \\return          1  Function failed\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r\n{\r\n   uint32_t result;\r\n\r\n   __ASM volatile (\"strexb %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*addr) : \"r\" ((uint32_t)value) );\r\n   return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   STR Exclusive (16 bit)\r\n  \\details Executes a exclusive STR instruction for 16 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n  \\return          0  Function succeeded\r\n  \\return          1  Function failed\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r\n{\r\n   uint32_t result;\r\n\r\n   __ASM volatile (\"strexh %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*addr) : \"r\" ((uint32_t)value) );\r\n   return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   STR Exclusive (32 bit)\r\n  \\details Executes a exclusive STR instruction for 32 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n  \\return          0  Function succeeded\r\n  \\return          1  Function failed\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r\n{\r\n   uint32_t result;\r\n\r\n   __ASM volatile (\"strex %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*addr) : \"r\" (value) );\r\n   return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Remove the exclusive lock\r\n  \\details Removes the exclusive lock which is created by LDREX.\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)\r\n{\r\n  __ASM volatile (\"clrex\" ::: \"memory\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Signed Saturate\r\n  \\details Saturates a signed value.\r\n  \\param [in]  value  Value to be saturated\r\n  \\param [in]    sat  Bit position to saturate to (1..32)\r\n  \\return             Saturated value\r\n */\r\n#define __SSAT(ARG1,ARG2) \\\r\n({                          \\\r\n  uint32_t __RES, __ARG1 = (ARG1); \\\r\n  __ASM (\"ssat %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\r\n  __RES; \\\r\n })\r\n\r\n\r\n/**\r\n  \\brief   Unsigned Saturate\r\n  \\details Saturates an unsigned value.\r\n  \\param [in]  value  Value to be saturated\r\n  \\param [in]    sat  Bit position to saturate to (0..31)\r\n  \\return             Saturated value\r\n */\r\n#define __USAT(ARG1,ARG2) \\\r\n({                          \\\r\n  uint32_t __RES, __ARG1 = (ARG1); \\\r\n  __ASM (\"usat %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\r\n  __RES; \\\r\n })\r\n\r\n\r\n/**\r\n  \\brief   Rotate Right with Extend (32 bit)\r\n  \\details Moves each bit of a bitstring right by one bit.\r\n           The carry input is shifted in at the left end of the bitstring.\r\n  \\param [in]    value  Value to rotate\r\n  \\return               Rotated value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"rrx %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r\n  return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   LDRT Unprivileged (8 bit)\r\n  \\details Executes a Unprivileged LDRT instruction for 8 bit value.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return             value of type uint8_t at (*ptr)\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)\r\n{\r\n    uint32_t result;\r\n\r\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r\n   __ASM volatile (\"ldrbt %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\r\n#else\r\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\r\n       accepted by assembler. So has to use following less efficient pattern.\r\n    */\r\n   __ASM volatile (\"ldrbt %0, [%1]\" : \"=r\" (result) : \"r\" (addr) : \"memory\" );\r\n#endif\r\n   return ((uint8_t) result);    /* Add explicit type cast here */\r\n}\r\n\r\n\r\n/**\r\n  \\brief   LDRT Unprivileged (16 bit)\r\n  \\details Executes a Unprivileged LDRT instruction for 16 bit values.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return        value of type uint16_t at (*ptr)\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)\r\n{\r\n    uint32_t result;\r\n\r\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r\n   __ASM volatile (\"ldrht %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\r\n#else\r\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\r\n       accepted by assembler. So has to use following less efficient pattern.\r\n    */\r\n   __ASM volatile (\"ldrht %0, [%1]\" : \"=r\" (result) : \"r\" (addr) : \"memory\" );\r\n#endif\r\n   return ((uint16_t) result);    /* Add explicit type cast here */\r\n}\r\n\r\n\r\n/**\r\n  \\brief   LDRT Unprivileged (32 bit)\r\n  \\details Executes a Unprivileged LDRT instruction for 32 bit values.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return        value of type uint32_t at (*ptr)\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)\r\n{\r\n    uint32_t result;\r\n\r\n   __ASM volatile (\"ldrt %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\r\n   return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   STRT Unprivileged (8 bit)\r\n  \\details Executes a Unprivileged STRT instruction for 8 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)\r\n{\r\n   __ASM volatile (\"strbt %1, %0\" : \"=Q\" (*addr) : \"r\" ((uint32_t)value) );\r\n}\r\n\r\n\r\n/**\r\n  \\brief   STRT Unprivileged (16 bit)\r\n  \\details Executes a Unprivileged STRT instruction for 16 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)\r\n{\r\n   __ASM volatile (\"strht %1, %0\" : \"=Q\" (*addr) : \"r\" ((uint32_t)value) );\r\n}\r\n\r\n\r\n/**\r\n  \\brief   STRT Unprivileged (32 bit)\r\n  \\details Executes a Unprivileged STRT instruction for 32 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)\r\n{\r\n   __ASM volatile (\"strt %1, %0\" : \"=Q\" (*addr) : \"r\" (value) );\r\n}\r\n\r\n#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */\r\n\r\n/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r\n\r\n\r\n/* ###################  Compiler specific Intrinsics  ########################### */\r\n/** \\defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r\n  Access to dedicated SIMD instructions\r\n  @{\r\n*/\r\n\r\n#if (__CORTEX_M >= 0x04U)  /* only for Cortex-M4 and above */\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"sadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"qadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"shadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uqadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uhadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"ssub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"qsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"shsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"usub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uqsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uhsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"sadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"qadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"shadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uqadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uhadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"ssub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"qsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"shsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"usub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uqsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uhsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"sasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"qasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"shasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uqasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uhasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"ssax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"qsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"shsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"usax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uqsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uhsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"usad8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"usada8 %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\r\n  return(result);\r\n}\r\n\r\n#define __SSAT16(ARG1,ARG2) \\\r\n({                          \\\r\n  int32_t __RES, __ARG1 = (ARG1); \\\r\n  __ASM (\"ssat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\r\n  __RES; \\\r\n })\r\n\r\n#define __USAT16(ARG1,ARG2) \\\r\n({                          \\\r\n  uint32_t __RES, __ARG1 = (ARG1); \\\r\n  __ASM (\"usat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\r\n  __RES; \\\r\n })\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"sxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"sxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"smuad %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"smuadx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"smlad %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"smladx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\r\n{\r\n  union llreg_u{\r\n    uint32_t w32[2];\r\n    uint64_t w64;\r\n  } llr;\r\n  llr.w64 = acc;\r\n\r\n#ifndef __ARMEB__   /* Little endian */\r\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\r\n#else               /* Big endian */\r\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\r\n#endif\r\n\r\n  return(llr.w64);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\r\n{\r\n  union llreg_u{\r\n    uint32_t w32[2];\r\n    uint64_t w64;\r\n  } llr;\r\n  llr.w64 = acc;\r\n\r\n#ifndef __ARMEB__   /* Little endian */\r\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\r\n#else               /* Big endian */\r\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\r\n#endif\r\n\r\n  return(llr.w64);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"smusd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"smusdx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"smlsd %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"smlsdx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\r\n{\r\n  union llreg_u{\r\n    uint32_t w32[2];\r\n    uint64_t w64;\r\n  } llr;\r\n  llr.w64 = acc;\r\n\r\n#ifndef __ARMEB__   /* Little endian */\r\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\r\n#else               /* Big endian */\r\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\r\n#endif\r\n\r\n  return(llr.w64);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\r\n{\r\n  union llreg_u{\r\n    uint32_t w32[2];\r\n    uint64_t w64;\r\n  } llr;\r\n  llr.w64 = acc;\r\n\r\n#ifndef __ARMEB__   /* Little endian */\r\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\r\n#else               /* Big endian */\r\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\r\n#endif\r\n\r\n  return(llr.w64);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"sel %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE  int32_t __QADD( int32_t op1,  int32_t op2)\r\n{\r\n  int32_t result;\r\n\r\n  __ASM volatile (\"qadd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE  int32_t __QSUB( int32_t op1,  int32_t op2)\r\n{\r\n  int32_t result;\r\n\r\n  __ASM volatile (\"qsub %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n#define __PKHBT(ARG1,ARG2,ARG3) \\\r\n({                          \\\r\n  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\\r\n  __ASM (\"pkhbt %0, %1, %2, lsl %3\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2), \"I\" (ARG3)  ); \\\r\n  __RES; \\\r\n })\r\n\r\n#define __PKHTB(ARG1,ARG2,ARG3) \\\r\n({                          \\\r\n  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\\r\n  if (ARG3 == 0) \\\r\n    __ASM (\"pkhtb %0, %1, %2\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2)  ); \\\r\n  else \\\r\n    __ASM (\"pkhtb %0, %1, %2, asr %3\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2), \"I\" (ARG3)  ); \\\r\n  __RES; \\\r\n })\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\r\n{\r\n int32_t result;\r\n\r\n __ASM volatile (\"smmla %0, %1, %2, %3\" : \"=r\" (result): \"r\"  (op1), \"r\" (op2), \"r\" (op3) );\r\n return(result);\r\n}\r\n\r\n#endif /* (__CORTEX_M >= 0x04) */\r\n/*@} end of group CMSIS_SIMD_intrinsics */\r\n\r\n\r\n#if defined ( __GNUC__ )\r\n#pragma GCC diagnostic pop\r\n#endif\r\n\r\n#endif /* __CMSIS_GCC_H */\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/bsp/opencr/include/core_cm0.h",
    "content": "/**************************************************************************//**\r\n * @file     core_cm0.h\r\n * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File\r\n * @version  V4.30\r\n * @date     20. October 2015\r\n ******************************************************************************/\r\n/* Copyright (c) 2009 - 2015 ARM LIMITED\r\n\r\n   All rights reserved.\r\n   Redistribution and use in source and binary forms, with or without\r\n   modification, are permitted provided that the following conditions are met:\r\n   - Redistributions of source code must retain the above copyright\r\n     notice, this list of conditions and the following disclaimer.\r\n   - Redistributions in binary form must reproduce the above copyright\r\n     notice, this list of conditions and the following disclaimer in the\r\n     documentation and/or other materials provided with the distribution.\r\n   - Neither the name of ARM nor the names of its contributors may be used\r\n     to endorse or promote products derived from this software without\r\n     specific prior written permission.\r\n   *\r\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n   POSSIBILITY OF SUCH DAMAGE.\r\n   ---------------------------------------------------------------------------*/\r\n\r\n\r\n#if   defined ( __ICCARM__ )\r\n #pragma system_include         /* treat file as system include file for MISRA check */\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #pragma clang system_header   /* treat file as system include file */\r\n#endif\r\n\r\n#ifndef __CORE_CM0_H_GENERIC\r\n#define __CORE_CM0_H_GENERIC\r\n\r\n#include <stdint.h>\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/**\r\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r\n  CMSIS violates the following MISRA-C:2004 rules:\r\n\r\n   \\li Required Rule 8.5, object/function definition in header file.<br>\r\n     Function definitions in header files are used to allow 'inlining'.\r\n\r\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r\n     Unions are used for effective representation of core registers.\r\n\r\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\r\n     Function-like macros are used to allow more efficient code.\r\n */\r\n\r\n\r\n/*******************************************************************************\r\n *                 CMSIS definitions\r\n ******************************************************************************/\r\n/**\r\n  \\ingroup Cortex_M0\r\n  @{\r\n */\r\n\r\n/*  CMSIS CM0 definitions */\r\n#define __CM0_CMSIS_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CMSIS HAL main version */\r\n#define __CM0_CMSIS_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CMSIS HAL sub version */\r\n#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \\\r\n                                    __CM0_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL version number */\r\n\r\n#define __CORTEX_M                (0x00U)                                      /*!< Cortex-M Core */\r\n\r\n\r\n#if   defined ( __CC_ARM )\r\n  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */\r\n  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */\r\n  #define __STATIC_INLINE  static __inline\r\n\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */\r\n  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */\r\n  #define __STATIC_INLINE  static __inline\r\n\r\n#elif defined ( __GNUC__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __ICCARM__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __TMS470__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __TASKING__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __CSMC__ )\r\n  #define __packed\r\n  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */\r\n  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#else\r\n  #error Unknown compiler\r\n#endif\r\n\r\n/** __FPU_USED indicates whether an FPU is used or not.\r\n    This core does not support an FPU at all\r\n*/\r\n#define __FPU_USED       0U\r\n\r\n#if defined ( __CC_ARM )\r\n  #if defined __TARGET_FPU_VFP\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #if defined __ARM_PCS_VFP\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __GNUC__ )\r\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __ICCARM__ )\r\n  #if defined __ARMVFP__\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __TMS470__ )\r\n  #if defined __TI_VFP_SUPPORT__\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __TASKING__ )\r\n  #if defined __FPU_VFP__\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __CSMC__ )\r\n  #if ( __CSMC__ & 0x400U)\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#endif\r\n\r\n#include \"core_cmInstr.h\"                /* Core Instruction Access */\r\n#include \"core_cmFunc.h\"                 /* Core Function Access */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __CORE_CM0_H_GENERIC */\r\n\r\n#ifndef __CMSIS_GENERIC\r\n\r\n#ifndef __CORE_CM0_H_DEPENDANT\r\n#define __CORE_CM0_H_DEPENDANT\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* check device defines and use defaults */\r\n#if defined __CHECK_DEVICE_DEFINES\r\n  #ifndef __CM0_REV\r\n    #define __CM0_REV               0x0000U\r\n    #warning \"__CM0_REV not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __NVIC_PRIO_BITS\r\n    #define __NVIC_PRIO_BITS          2U\r\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __Vendor_SysTickConfig\r\n    #define __Vendor_SysTickConfig    0U\r\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\r\n  #endif\r\n#endif\r\n\r\n/* IO definitions (access restrictions to peripheral registers) */\r\n/**\r\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\r\n\r\n    <strong>IO Type Qualifiers</strong> are used\r\n    \\li to specify the access to peripheral variables.\r\n    \\li for automatic generation of peripheral register debug information.\r\n*/\r\n#ifdef __cplusplus\r\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\r\n#else\r\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r\n#endif\r\n#define     __O     volatile             /*!< Defines 'write only' permissions */\r\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r\n\r\n/* following defines should be used for structure members */\r\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r\n\r\n/*@} end of group Cortex_M0 */\r\n\r\n\r\n\r\n/*******************************************************************************\r\n *                 Register Abstraction\r\n  Core Register contain:\r\n  - Core Register\r\n  - Core NVIC Register\r\n  - Core SCB Register\r\n  - Core SysTick Register\r\n ******************************************************************************/\r\n/**\r\n  \\defgroup CMSIS_core_register Defines and Type Definitions\r\n  \\brief Type definitions and defines for Cortex-M processor based devices.\r\n*/\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_CORE  Status and Control Registers\r\n  \\brief      Core Register type definitions.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Union type to access the Application Program Status Register (APSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\r\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} APSR_Type;\r\n\r\n/* APSR Register Definitions */\r\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r\n\r\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r\n\r\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r\n\r\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} IPSR_Type;\r\n\r\n/* IPSR Register Definitions */\r\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\r\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\r\n    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\r\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} xPSR_Type;\r\n\r\n/* xPSR Register Definitions */\r\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r\n\r\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r\n\r\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r\n\r\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r\n\r\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r\n\r\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Control Registers (CONTROL).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */\r\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\r\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} CONTROL_Type;\r\n\r\n/* CONTROL Register Definitions */\r\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r\n\r\n/*@} end of group CMSIS_CORE */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r\n  \\brief      Type definitions for the NVIC Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r\n        uint32_t RESERVED0[31U];\r\n  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r\n        uint32_t RSERVED1[31U];\r\n  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r\n        uint32_t RESERVED2[31U];\r\n  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r\n        uint32_t RESERVED3[31U];\r\n        uint32_t RESERVED4[64U];\r\n  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\r\n}  NVIC_Type;\r\n\r\n/*@} end of group CMSIS_NVIC */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\r\n  \\brief    Type definitions for the System Control Block Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Control Block (SCB).\r\n */\r\ntypedef struct\r\n{\r\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r\n        uint32_t RESERVED0;\r\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r\n        uint32_t RESERVED1;\r\n  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\r\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r\n} SCB_Type;\r\n\r\n/* SCB CPUID Register Definitions */\r\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r\n\r\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r\n\r\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r\n\r\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r\n\r\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r\n\r\n/* SCB Interrupt Control State Register Definitions */\r\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\r\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\r\n\r\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r\n\r\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r\n\r\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r\n\r\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r\n\r\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r\n\r\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r\n\r\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r\n\r\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r\n\r\n/* SCB Application Interrupt and Reset Control Register Definitions */\r\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r\n\r\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r\n\r\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r\n\r\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r\n\r\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r\n\r\n/* SCB System Control Register Definitions */\r\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r\n\r\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r\n\r\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r\n\r\n/* SCB Configuration Control Register Definitions */\r\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\r\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\r\n\r\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r\n\r\n/* SCB System Handler Control and State Register Definitions */\r\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r\n\r\n/*@} end of group CMSIS_SCB */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r\n  \\brief    Type definitions for the System Timer Registers.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Timer (SysTick).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r\n} SysTick_Type;\r\n\r\n/* SysTick Control / Status Register Definitions */\r\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r\n\r\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r\n\r\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r\n\r\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r\n\r\n/* SysTick Reload Register Definitions */\r\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r\n\r\n/* SysTick Current Register Definitions */\r\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r\n\r\n/* SysTick Calibration Register Definitions */\r\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r\n\r\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r\n\r\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r\n\r\n/*@} end of group CMSIS_SysTick */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r\n  \\brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\r\n            Therefore they are not covered by the Cortex-M0 header file.\r\n  @{\r\n */\r\n/*@} end of group CMSIS_CoreDebug */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\r\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief   Mask and shift a bit field value for use in a register bit range.\r\n  \\param[in] field  Name of the register bit field.\r\n  \\param[in] value  Value of the bit field.\r\n  \\return           Masked and shifted value.\r\n*/\r\n#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)\r\n\r\n/**\r\n  \\brief     Mask and shift a register value to extract a bit filed value.\r\n  \\param[in] field  Name of the register bit field.\r\n  \\param[in] value  Value of register.\r\n  \\return           Masked and shifted bit field value.\r\n*/\r\n#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)\r\n\r\n/*@} end of group CMSIS_core_bitfield */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_core_base     Core Definitions\r\n  \\brief      Definitions for base addresses, unions, and structures.\r\n  @{\r\n */\r\n\r\n/* Memory mapping of Cortex-M0 Hardware */\r\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\r\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\r\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\r\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\r\n\r\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\r\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\r\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\r\n\r\n\r\n/*@} */\r\n\r\n\r\n\r\n/*******************************************************************************\r\n *                Hardware Abstraction Layer\r\n  Core Function Interface contains:\r\n  - Core NVIC Functions\r\n  - Core SysTick Functions\r\n  - Core Register Access Functions\r\n ******************************************************************************/\r\n/**\r\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r\n*/\r\n\r\n\r\n\r\n/* ##########################   NVIC functions  #################################### */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\r\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\r\n  @{\r\n */\r\n\r\n/* Interrupt Priorities are WORD accessible only under ARMv6M                   */\r\n/* The following MACROS handle generation of the register offset and byte masks */\r\n#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\r\n#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\r\n#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\r\n\r\n\r\n/**\r\n  \\brief   Enable External Interrupt\r\n  \\details Enables a device-specific interrupt in the NVIC interrupt controller.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Disable External Interrupt\r\n  \\details Disables a device-specific interrupt in the NVIC interrupt controller.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Pending Interrupt\r\n  \\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\return             0  Interrupt status is not pending.\r\n  \\return             1  Interrupt status is pending.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Pending Interrupt\r\n  \\details Sets the pending bit of an external interrupt.\r\n  \\param [in]      IRQn  Interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Clear Pending Interrupt\r\n  \\details Clears the pending bit of an external interrupt.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Interrupt Priority\r\n  \\details Sets the priority of an interrupt.\r\n  \\note    The priority cannot be set for every core interrupt.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\param [in]  priority  Priority to set.\r\n */\r\n__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r\n{\r\n  if ((int32_t)(IRQn) < 0)\r\n  {\r\n    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r\n  }\r\n  else\r\n  {\r\n    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Interrupt Priority\r\n  \\details Reads the priority of an interrupt.\r\n           The interrupt number can be positive to specify an external (device specific) interrupt,\r\n           or negative to specify an internal (core) interrupt.\r\n  \\param [in]   IRQn  Interrupt number.\r\n  \\return             Interrupt Priority.\r\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r\n{\r\n\r\n  if ((int32_t)(IRQn) < 0)\r\n  {\r\n    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r\n  }\r\n  else\r\n  {\r\n    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   System Reset\r\n  \\details Initiates a system reset request to reset the MCU.\r\n */\r\n__STATIC_INLINE void NVIC_SystemReset(void)\r\n{\r\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\r\n                                                                       buffered write are completed before reset */\r\n  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r\n                 SCB_AIRCR_SYSRESETREQ_Msk);\r\n  __DSB();                                                          /* Ensure completion of memory access */\r\n\r\n  for(;;)                                                           /* wait until reset */\r\n  {\r\n    __NOP();\r\n  }\r\n}\r\n\r\n/*@} end of CMSIS_Core_NVICFunctions */\r\n\r\n\r\n\r\n/* ##################################    SysTick function  ############################################ */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r\n  \\brief    Functions that configure the System.\r\n  @{\r\n */\r\n\r\n#if (__Vendor_SysTickConfig == 0U)\r\n\r\n/**\r\n  \\brief   System Tick Configuration\r\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r\n           Counter is in free running mode to generate periodic interrupts.\r\n  \\param [in]  ticks  Number of ticks between two interrupts.\r\n  \\return          0  Function succeeded.\r\n  \\return          1  Function failed.\r\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r\n           must contain a vendor-specific implementation of this function.\r\n */\r\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r\n{\r\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r\n  {\r\n    return (1UL);                                                   /* Reload value impossible */\r\n  }\r\n\r\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r\n                   SysTick_CTRL_TICKINT_Msk   |\r\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r\n  return (0UL);                                                     /* Function successful */\r\n}\r\n\r\n#endif\r\n\r\n/*@} end of CMSIS_Core_SysTickFunctions */\r\n\r\n\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __CORE_CM0_H_DEPENDANT */\r\n\r\n#endif /* __CMSIS_GENERIC */\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/bsp/opencr/include/core_cm0plus.h",
    "content": "/**************************************************************************//**\r\n * @file     core_cm0plus.h\r\n * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File\r\n * @version  V4.30\r\n * @date     20. October 2015\r\n ******************************************************************************/\r\n/* Copyright (c) 2009 - 2015 ARM LIMITED\r\n\r\n   All rights reserved.\r\n   Redistribution and use in source and binary forms, with or without\r\n   modification, are permitted provided that the following conditions are met:\r\n   - Redistributions of source code must retain the above copyright\r\n     notice, this list of conditions and the following disclaimer.\r\n   - Redistributions in binary form must reproduce the above copyright\r\n     notice, this list of conditions and the following disclaimer in the\r\n     documentation and/or other materials provided with the distribution.\r\n   - Neither the name of ARM nor the names of its contributors may be used\r\n     to endorse or promote products derived from this software without\r\n     specific prior written permission.\r\n   *\r\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n   POSSIBILITY OF SUCH DAMAGE.\r\n   ---------------------------------------------------------------------------*/\r\n\r\n\r\n#if   defined ( __ICCARM__ )\r\n #pragma system_include         /* treat file as system include file for MISRA check */\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #pragma clang system_header   /* treat file as system include file */\r\n#endif\r\n\r\n#ifndef __CORE_CM0PLUS_H_GENERIC\r\n#define __CORE_CM0PLUS_H_GENERIC\r\n\r\n#include <stdint.h>\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/**\r\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r\n  CMSIS violates the following MISRA-C:2004 rules:\r\n\r\n   \\li Required Rule 8.5, object/function definition in header file.<br>\r\n     Function definitions in header files are used to allow 'inlining'.\r\n\r\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r\n     Unions are used for effective representation of core registers.\r\n\r\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\r\n     Function-like macros are used to allow more efficient code.\r\n */\r\n\r\n\r\n/*******************************************************************************\r\n *                 CMSIS definitions\r\n ******************************************************************************/\r\n/**\r\n  \\ingroup Cortex-M0+\r\n  @{\r\n */\r\n\r\n/*  CMSIS CM0+ definitions */\r\n#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U)                                   /*!< [31:16] CMSIS HAL main version */\r\n#define __CM0PLUS_CMSIS_VERSION_SUB  (0x1EU)                                   /*!< [15:0]  CMSIS HAL sub version */\r\n#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \\\r\n                                       __CM0PLUS_CMSIS_VERSION_SUB           ) /*!< CMSIS HAL version number */\r\n\r\n#define __CORTEX_M                (0x00U)                                      /*!< Cortex-M Core */\r\n\r\n\r\n#if   defined ( __CC_ARM )\r\n  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */\r\n  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */\r\n  #define __STATIC_INLINE  static __inline\r\n\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */\r\n  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */\r\n  #define __STATIC_INLINE  static __inline\r\n\r\n#elif defined ( __GNUC__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __ICCARM__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __TMS470__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __TASKING__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __CSMC__ )\r\n  #define __packed\r\n  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */\r\n  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#else\r\n  #error Unknown compiler\r\n#endif\r\n\r\n/** __FPU_USED indicates whether an FPU is used or not.\r\n    This core does not support an FPU at all\r\n*/\r\n#define __FPU_USED       0U\r\n\r\n#if defined ( __CC_ARM )\r\n  #if defined __TARGET_FPU_VFP\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #if defined __ARM_PCS_VFP\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __GNUC__ )\r\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __ICCARM__ )\r\n  #if defined __ARMVFP__\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __TMS470__ )\r\n  #if defined __TI_VFP_SUPPORT__\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __TASKING__ )\r\n  #if defined __FPU_VFP__\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __CSMC__ )\r\n  #if ( __CSMC__ & 0x400U)\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#endif\r\n\r\n#include \"core_cmInstr.h\"                /* Core Instruction Access */\r\n#include \"core_cmFunc.h\"                 /* Core Function Access */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __CORE_CM0PLUS_H_GENERIC */\r\n\r\n#ifndef __CMSIS_GENERIC\r\n\r\n#ifndef __CORE_CM0PLUS_H_DEPENDANT\r\n#define __CORE_CM0PLUS_H_DEPENDANT\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* check device defines and use defaults */\r\n#if defined __CHECK_DEVICE_DEFINES\r\n  #ifndef __CM0PLUS_REV\r\n    #define __CM0PLUS_REV             0x0000U\r\n    #warning \"__CM0PLUS_REV not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __MPU_PRESENT\r\n    #define __MPU_PRESENT             0U\r\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __VTOR_PRESENT\r\n    #define __VTOR_PRESENT            0U\r\n    #warning \"__VTOR_PRESENT not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __NVIC_PRIO_BITS\r\n    #define __NVIC_PRIO_BITS          2U\r\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __Vendor_SysTickConfig\r\n    #define __Vendor_SysTickConfig    0U\r\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\r\n  #endif\r\n#endif\r\n\r\n/* IO definitions (access restrictions to peripheral registers) */\r\n/**\r\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\r\n\r\n    <strong>IO Type Qualifiers</strong> are used\r\n    \\li to specify the access to peripheral variables.\r\n    \\li for automatic generation of peripheral register debug information.\r\n*/\r\n#ifdef __cplusplus\r\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\r\n#else\r\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r\n#endif\r\n#define     __O     volatile             /*!< Defines 'write only' permissions */\r\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r\n\r\n/* following defines should be used for structure members */\r\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r\n\r\n/*@} end of group Cortex-M0+ */\r\n\r\n\r\n\r\n/*******************************************************************************\r\n *                 Register Abstraction\r\n  Core Register contain:\r\n  - Core Register\r\n  - Core NVIC Register\r\n  - Core SCB Register\r\n  - Core SysTick Register\r\n  - Core MPU Register\r\n ******************************************************************************/\r\n/**\r\n  \\defgroup CMSIS_core_register Defines and Type Definitions\r\n  \\brief Type definitions and defines for Cortex-M processor based devices.\r\n*/\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_CORE  Status and Control Registers\r\n  \\brief      Core Register type definitions.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Union type to access the Application Program Status Register (APSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\r\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} APSR_Type;\r\n\r\n/* APSR Register Definitions */\r\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r\n\r\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r\n\r\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r\n\r\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} IPSR_Type;\r\n\r\n/* IPSR Register Definitions */\r\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\r\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\r\n    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\r\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} xPSR_Type;\r\n\r\n/* xPSR Register Definitions */\r\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r\n\r\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r\n\r\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r\n\r\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r\n\r\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r\n\r\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Control Registers (CONTROL).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\r\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\r\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} CONTROL_Type;\r\n\r\n/* CONTROL Register Definitions */\r\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r\n\r\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\r\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\r\n\r\n/*@} end of group CMSIS_CORE */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r\n  \\brief      Type definitions for the NVIC Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r\n        uint32_t RESERVED0[31U];\r\n  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r\n        uint32_t RSERVED1[31U];\r\n  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r\n        uint32_t RESERVED2[31U];\r\n  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r\n        uint32_t RESERVED3[31U];\r\n        uint32_t RESERVED4[64U];\r\n  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\r\n}  NVIC_Type;\r\n\r\n/*@} end of group CMSIS_NVIC */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\r\n  \\brief    Type definitions for the System Control Block Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Control Block (SCB).\r\n */\r\ntypedef struct\r\n{\r\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r\n#if (__VTOR_PRESENT == 1U)\r\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\r\n#else\r\n        uint32_t RESERVED0;\r\n#endif\r\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r\n        uint32_t RESERVED1;\r\n  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\r\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r\n} SCB_Type;\r\n\r\n/* SCB CPUID Register Definitions */\r\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r\n\r\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r\n\r\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r\n\r\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r\n\r\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r\n\r\n/* SCB Interrupt Control State Register Definitions */\r\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\r\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\r\n\r\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r\n\r\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r\n\r\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r\n\r\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r\n\r\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r\n\r\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r\n\r\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r\n\r\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r\n\r\n#if (__VTOR_PRESENT == 1U)\r\n/* SCB Interrupt Control State Register Definitions */\r\n#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */\r\n#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */\r\n#endif\r\n\r\n/* SCB Application Interrupt and Reset Control Register Definitions */\r\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r\n\r\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r\n\r\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r\n\r\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r\n\r\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r\n\r\n/* SCB System Control Register Definitions */\r\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r\n\r\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r\n\r\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r\n\r\n/* SCB Configuration Control Register Definitions */\r\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\r\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\r\n\r\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r\n\r\n/* SCB System Handler Control and State Register Definitions */\r\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r\n\r\n/*@} end of group CMSIS_SCB */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r\n  \\brief    Type definitions for the System Timer Registers.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Timer (SysTick).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r\n} SysTick_Type;\r\n\r\n/* SysTick Control / Status Register Definitions */\r\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r\n\r\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r\n\r\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r\n\r\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r\n\r\n/* SysTick Reload Register Definitions */\r\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r\n\r\n/* SysTick Current Register Definitions */\r\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r\n\r\n/* SysTick Calibration Register Definitions */\r\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r\n\r\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r\n\r\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r\n\r\n/*@} end of group CMSIS_SysTick */\r\n\r\n#if (__MPU_PRESENT == 1U)\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\r\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\r\n */\r\ntypedef struct\r\n{\r\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\r\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\r\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\r\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\r\n} MPU_Type;\r\n\r\n/* MPU Type Register Definitions */\r\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\r\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r\n\r\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\r\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r\n\r\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\r\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\r\n\r\n/* MPU Control Register Definitions */\r\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\r\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r\n\r\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\r\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r\n\r\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\r\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\r\n\r\n/* MPU Region Number Register Definitions */\r\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\r\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\r\n\r\n/* MPU Region Base Address Register Definitions */\r\n#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */\r\n#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */\r\n\r\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\r\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\r\n\r\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\r\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\r\n\r\n/* MPU Region Attribute and Size Register Definitions */\r\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\r\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\r\n\r\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\r\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\r\n\r\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\r\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\r\n\r\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\r\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\r\n\r\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\r\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\r\n\r\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\r\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\r\n\r\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\r\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\r\n\r\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\r\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\r\n\r\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\r\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\r\n\r\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\r\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\r\n\r\n/*@} end of group CMSIS_MPU */\r\n#endif\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r\n  \\brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\r\n            Therefore they are not covered by the Cortex-M0+ header file.\r\n  @{\r\n */\r\n/*@} end of group CMSIS_CoreDebug */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\r\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief   Mask and shift a bit field value for use in a register bit range.\r\n  \\param[in] field  Name of the register bit field.\r\n  \\param[in] value  Value of the bit field.\r\n  \\return           Masked and shifted value.\r\n*/\r\n#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)\r\n\r\n/**\r\n  \\brief     Mask and shift a register value to extract a bit filed value.\r\n  \\param[in] field  Name of the register bit field.\r\n  \\param[in] value  Value of register.\r\n  \\return           Masked and shifted bit field value.\r\n*/\r\n#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)\r\n\r\n/*@} end of group CMSIS_core_bitfield */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_core_base     Core Definitions\r\n  \\brief      Definitions for base addresses, unions, and structures.\r\n  @{\r\n */\r\n\r\n/* Memory mapping of Cortex-M0+ Hardware */\r\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\r\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\r\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\r\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\r\n\r\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\r\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\r\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\r\n\r\n#if (__MPU_PRESENT == 1U)\r\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\r\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\r\n#endif\r\n\r\n/*@} */\r\n\r\n\r\n\r\n/*******************************************************************************\r\n *                Hardware Abstraction Layer\r\n  Core Function Interface contains:\r\n  - Core NVIC Functions\r\n  - Core SysTick Functions\r\n  - Core Register Access Functions\r\n ******************************************************************************/\r\n/**\r\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r\n*/\r\n\r\n\r\n\r\n/* ##########################   NVIC functions  #################################### */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\r\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\r\n  @{\r\n */\r\n\r\n/* Interrupt Priorities are WORD accessible only under ARMv6M                   */\r\n/* The following MACROS handle generation of the register offset and byte masks */\r\n#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\r\n#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\r\n#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\r\n\r\n\r\n/**\r\n  \\brief   Enable External Interrupt\r\n  \\details Enables a device-specific interrupt in the NVIC interrupt controller.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Disable External Interrupt\r\n  \\details Disables a device-specific interrupt in the NVIC interrupt controller.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Pending Interrupt\r\n  \\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\return             0  Interrupt status is not pending.\r\n  \\return             1  Interrupt status is pending.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Pending Interrupt\r\n  \\details Sets the pending bit of an external interrupt.\r\n  \\param [in]      IRQn  Interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Clear Pending Interrupt\r\n  \\details Clears the pending bit of an external interrupt.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Interrupt Priority\r\n  \\details Sets the priority of an interrupt.\r\n  \\note    The priority cannot be set for every core interrupt.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\param [in]  priority  Priority to set.\r\n */\r\n__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r\n{\r\n  if ((int32_t)(IRQn) < 0)\r\n  {\r\n    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r\n  }\r\n  else\r\n  {\r\n    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Interrupt Priority\r\n  \\details Reads the priority of an interrupt.\r\n           The interrupt number can be positive to specify an external (device specific) interrupt,\r\n           or negative to specify an internal (core) interrupt.\r\n  \\param [in]   IRQn  Interrupt number.\r\n  \\return             Interrupt Priority.\r\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r\n{\r\n\r\n  if ((int32_t)(IRQn) < 0)\r\n  {\r\n    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r\n  }\r\n  else\r\n  {\r\n    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   System Reset\r\n  \\details Initiates a system reset request to reset the MCU.\r\n */\r\n__STATIC_INLINE void NVIC_SystemReset(void)\r\n{\r\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\r\n                                                                       buffered write are completed before reset */\r\n  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r\n                 SCB_AIRCR_SYSRESETREQ_Msk);\r\n  __DSB();                                                          /* Ensure completion of memory access */\r\n\r\n  for(;;)                                                           /* wait until reset */\r\n  {\r\n    __NOP();\r\n  }\r\n}\r\n\r\n/*@} end of CMSIS_Core_NVICFunctions */\r\n\r\n\r\n\r\n/* ##################################    SysTick function  ############################################ */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r\n  \\brief    Functions that configure the System.\r\n  @{\r\n */\r\n\r\n#if (__Vendor_SysTickConfig == 0U)\r\n\r\n/**\r\n  \\brief   System Tick Configuration\r\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r\n           Counter is in free running mode to generate periodic interrupts.\r\n  \\param [in]  ticks  Number of ticks between two interrupts.\r\n  \\return          0  Function succeeded.\r\n  \\return          1  Function failed.\r\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r\n           must contain a vendor-specific implementation of this function.\r\n */\r\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r\n{\r\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r\n  {\r\n    return (1UL);                                                   /* Reload value impossible */\r\n  }\r\n\r\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r\n                   SysTick_CTRL_TICKINT_Msk   |\r\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r\n  return (0UL);                                                     /* Function successful */\r\n}\r\n\r\n#endif\r\n\r\n/*@} end of CMSIS_Core_SysTickFunctions */\r\n\r\n\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __CORE_CM0PLUS_H_DEPENDANT */\r\n\r\n#endif /* __CMSIS_GENERIC */\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/bsp/opencr/include/core_cm3.h",
    "content": "/**************************************************************************//**\r\n * @file     core_cm3.h\r\n * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r\n * @version  V4.30\r\n * @date     20. October 2015\r\n ******************************************************************************/\r\n/* Copyright (c) 2009 - 2015 ARM LIMITED\r\n\r\n   All rights reserved.\r\n   Redistribution and use in source and binary forms, with or without\r\n   modification, are permitted provided that the following conditions are met:\r\n   - Redistributions of source code must retain the above copyright\r\n     notice, this list of conditions and the following disclaimer.\r\n   - Redistributions in binary form must reproduce the above copyright\r\n     notice, this list of conditions and the following disclaimer in the\r\n     documentation and/or other materials provided with the distribution.\r\n   - Neither the name of ARM nor the names of its contributors may be used\r\n     to endorse or promote products derived from this software without\r\n     specific prior written permission.\r\n   *\r\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n   POSSIBILITY OF SUCH DAMAGE.\r\n   ---------------------------------------------------------------------------*/\r\n\r\n\r\n#if   defined ( __ICCARM__ )\r\n #pragma system_include         /* treat file as system include file for MISRA check */\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #pragma clang system_header   /* treat file as system include file */\r\n#endif\r\n\r\n#ifndef __CORE_CM3_H_GENERIC\r\n#define __CORE_CM3_H_GENERIC\r\n\r\n#include <stdint.h>\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/**\r\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r\n  CMSIS violates the following MISRA-C:2004 rules:\r\n\r\n   \\li Required Rule 8.5, object/function definition in header file.<br>\r\n     Function definitions in header files are used to allow 'inlining'.\r\n\r\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r\n     Unions are used for effective representation of core registers.\r\n\r\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\r\n     Function-like macros are used to allow more efficient code.\r\n */\r\n\r\n\r\n/*******************************************************************************\r\n *                 CMSIS definitions\r\n ******************************************************************************/\r\n/**\r\n  \\ingroup Cortex_M3\r\n  @{\r\n */\r\n\r\n/*  CMSIS CM3 definitions */\r\n#define __CM3_CMSIS_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CMSIS HAL main version */\r\n#define __CM3_CMSIS_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CMSIS HAL sub version */\r\n#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \\\r\n                                    __CM3_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL version number */\r\n\r\n#define __CORTEX_M                (0x03U)                                      /*!< Cortex-M Core */\r\n\r\n\r\n#if   defined ( __CC_ARM )\r\n  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */\r\n  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */\r\n  #define __STATIC_INLINE  static __inline\r\n\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */\r\n  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */\r\n  #define __STATIC_INLINE  static __inline\r\n\r\n#elif defined ( __GNUC__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __ICCARM__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __TMS470__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __TASKING__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __CSMC__ )\r\n  #define __packed\r\n  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */\r\n  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#else\r\n  #error Unknown compiler\r\n#endif\r\n\r\n/** __FPU_USED indicates whether an FPU is used or not.\r\n    This core does not support an FPU at all\r\n*/\r\n#define __FPU_USED       0U\r\n\r\n#if defined ( __CC_ARM )\r\n  #if defined __TARGET_FPU_VFP\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #if defined __ARM_PCS_VFP\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __GNUC__ )\r\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __ICCARM__ )\r\n  #if defined __ARMVFP__\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __TMS470__ )\r\n  #if defined __TI_VFP_SUPPORT__\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __TASKING__ )\r\n  #if defined __FPU_VFP__\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __CSMC__ )\r\n  #if ( __CSMC__ & 0x400U)\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#endif\r\n\r\n#include \"core_cmInstr.h\"                /* Core Instruction Access */\r\n#include \"core_cmFunc.h\"                 /* Core Function Access */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __CORE_CM3_H_GENERIC */\r\n\r\n#ifndef __CMSIS_GENERIC\r\n\r\n#ifndef __CORE_CM3_H_DEPENDANT\r\n#define __CORE_CM3_H_DEPENDANT\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* check device defines and use defaults */\r\n#if defined __CHECK_DEVICE_DEFINES\r\n  #ifndef __CM3_REV\r\n    #define __CM3_REV               0x0200U\r\n    #warning \"__CM3_REV not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __MPU_PRESENT\r\n    #define __MPU_PRESENT             0U\r\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __NVIC_PRIO_BITS\r\n    #define __NVIC_PRIO_BITS          4U\r\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __Vendor_SysTickConfig\r\n    #define __Vendor_SysTickConfig    0U\r\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\r\n  #endif\r\n#endif\r\n\r\n/* IO definitions (access restrictions to peripheral registers) */\r\n/**\r\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\r\n\r\n    <strong>IO Type Qualifiers</strong> are used\r\n    \\li to specify the access to peripheral variables.\r\n    \\li for automatic generation of peripheral register debug information.\r\n*/\r\n#ifdef __cplusplus\r\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\r\n#else\r\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r\n#endif\r\n#define     __O     volatile             /*!< Defines 'write only' permissions */\r\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r\n\r\n/* following defines should be used for structure members */\r\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r\n\r\n/*@} end of group Cortex_M3 */\r\n\r\n\r\n\r\n/*******************************************************************************\r\n *                 Register Abstraction\r\n  Core Register contain:\r\n  - Core Register\r\n  - Core NVIC Register\r\n  - Core SCB Register\r\n  - Core SysTick Register\r\n  - Core Debug Register\r\n  - Core MPU Register\r\n ******************************************************************************/\r\n/**\r\n  \\defgroup CMSIS_core_register Defines and Type Definitions\r\n  \\brief Type definitions and defines for Cortex-M processor based devices.\r\n*/\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_CORE  Status and Control Registers\r\n  \\brief      Core Register type definitions.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Union type to access the Application Program Status Register (APSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */\r\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} APSR_Type;\r\n\r\n/* APSR Register Definitions */\r\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r\n\r\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r\n\r\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r\n\r\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r\n\r\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\r\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} IPSR_Type;\r\n\r\n/* IPSR Register Definitions */\r\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\r\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\r\n    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */\r\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} xPSR_Type;\r\n\r\n/* xPSR Register Definitions */\r\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r\n\r\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r\n\r\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r\n\r\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r\n\r\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\r\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\r\n\r\n#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */\r\n#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */\r\n\r\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r\n\r\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Control Registers (CONTROL).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\r\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\r\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} CONTROL_Type;\r\n\r\n/* CONTROL Register Definitions */\r\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r\n\r\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\r\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\r\n\r\n/*@} end of group CMSIS_CORE */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r\n  \\brief      Type definitions for the NVIC Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r\n        uint32_t RESERVED0[24U];\r\n  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r\n        uint32_t RSERVED1[24U];\r\n  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r\n        uint32_t RESERVED2[24U];\r\n  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r\n        uint32_t RESERVED3[24U];\r\n  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\r\n        uint32_t RESERVED4[56U];\r\n  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\r\n        uint32_t RESERVED5[644U];\r\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\r\n}  NVIC_Type;\r\n\r\n/* Software Triggered Interrupt Register Definitions */\r\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\r\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\r\n\r\n/*@} end of group CMSIS_NVIC */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\r\n  \\brief    Type definitions for the System Control Block Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Control Block (SCB).\r\n */\r\ntypedef struct\r\n{\r\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\r\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r\n  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\r\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\r\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\r\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\r\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\r\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\r\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\r\n  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */\r\n  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */\r\n  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\r\n  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\r\n  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\r\n        uint32_t RESERVED0[5U];\r\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\r\n} SCB_Type;\r\n\r\n/* SCB CPUID Register Definitions */\r\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r\n\r\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r\n\r\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r\n\r\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r\n\r\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r\n\r\n/* SCB Interrupt Control State Register Definitions */\r\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\r\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\r\n\r\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r\n\r\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r\n\r\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r\n\r\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r\n\r\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r\n\r\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r\n\r\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r\n\r\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\r\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\r\n\r\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r\n\r\n/* SCB Vector Table Offset Register Definitions */\r\n#if (__CM3_REV < 0x0201U)                   /* core r2p1 */\r\n#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */\r\n#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */\r\n\r\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\r\n#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */\r\n#else\r\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\r\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\r\n#endif\r\n\r\n/* SCB Application Interrupt and Reset Control Register Definitions */\r\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r\n\r\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r\n\r\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r\n\r\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\r\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\r\n\r\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r\n\r\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r\n\r\n#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\r\n#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\r\n\r\n/* SCB System Control Register Definitions */\r\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r\n\r\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r\n\r\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r\n\r\n/* SCB Configuration Control Register Definitions */\r\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\r\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\r\n\r\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\r\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\r\n\r\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\r\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\r\n\r\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r\n\r\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\r\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\r\n\r\n#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\r\n#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\r\n\r\n/* SCB System Handler Control and State Register Definitions */\r\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\r\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\r\n\r\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\r\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\r\n\r\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\r\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\r\n\r\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r\n\r\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\r\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r\n\r\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\r\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r\n\r\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\r\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\r\n\r\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\r\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\r\n\r\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\r\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\r\n\r\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\r\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\r\n\r\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\r\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\r\n\r\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\r\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\r\n\r\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\r\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\r\n\r\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\r\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\r\n\r\n/* SCB Configurable Fault Status Register Definitions */\r\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\r\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\r\n\r\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\r\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\r\n\r\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r\n\r\n/* SCB Hard Fault Status Register Definitions */\r\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\r\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\r\n\r\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\r\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\r\n\r\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\r\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\r\n\r\n/* SCB Debug Fault Status Register Definitions */\r\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\r\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\r\n\r\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\r\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\r\n\r\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\r\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\r\n\r\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\r\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\r\n\r\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\r\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\r\n\r\n/*@} end of group CMSIS_SCB */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\r\n */\r\ntypedef struct\r\n{\r\n        uint32_t RESERVED0[1U];\r\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\r\n#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U))\r\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\r\n#else\r\n        uint32_t RESERVED1[1U];\r\n#endif\r\n} SCnSCB_Type;\r\n\r\n/* Interrupt Controller Type Register Definitions */\r\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\r\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\r\n\r\n/* Auxiliary Control Register Definitions */\r\n\r\n#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */\r\n#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */\r\n\r\n#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */\r\n#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */\r\n\r\n#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\r\n#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\r\n\r\n/*@} end of group CMSIS_SCnotSCB */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r\n  \\brief    Type definitions for the System Timer Registers.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Timer (SysTick).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r\n} SysTick_Type;\r\n\r\n/* SysTick Control / Status Register Definitions */\r\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r\n\r\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r\n\r\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r\n\r\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r\n\r\n/* SysTick Reload Register Definitions */\r\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r\n\r\n/* SysTick Current Register Definitions */\r\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r\n\r\n/* SysTick Calibration Register Definitions */\r\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r\n\r\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r\n\r\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r\n\r\n/*@} end of group CMSIS_SysTick */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\r\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r\n */\r\ntypedef struct\r\n{\r\n  __OM  union\r\n  {\r\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\r\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\r\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\r\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\r\n        uint32_t RESERVED0[864U];\r\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\r\n        uint32_t RESERVED1[15U];\r\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\r\n        uint32_t RESERVED2[15U];\r\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\r\n        uint32_t RESERVED3[29U];\r\n  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\r\n  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\r\n  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\r\n        uint32_t RESERVED4[43U];\r\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\r\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\r\n        uint32_t RESERVED5[6U];\r\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\r\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\r\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\r\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\r\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\r\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\r\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\r\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\r\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\r\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\r\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\r\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\r\n} ITM_Type;\r\n\r\n/* ITM Trace Privilege Register Definitions */\r\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\r\n#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */\r\n\r\n/* ITM Trace Control Register Definitions */\r\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\r\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\r\n\r\n#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\r\n#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */\r\n\r\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\r\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\r\n\r\n#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\r\n#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\r\n\r\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\r\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\r\n\r\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\r\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\r\n\r\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\r\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\r\n\r\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\r\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\r\n\r\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\r\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\r\n\r\n/* ITM Integration Write Register Definitions */\r\n#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */\r\n#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\r\n\r\n/* ITM Integration Read Register Definitions */\r\n#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */\r\n#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\r\n\r\n/* ITM Integration Mode Control Register Definitions */\r\n#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */\r\n#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\r\n\r\n/* ITM Lock Status Register Definitions */\r\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\r\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\r\n\r\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\r\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\r\n\r\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\r\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\r\n\r\n/*@}*/ /* end of group CMSIS_ITM */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\r\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\r\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\r\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\r\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\r\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\r\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\r\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\r\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\r\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\r\n  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\r\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\r\n        uint32_t RESERVED0[1U];\r\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\r\n  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\r\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\r\n        uint32_t RESERVED1[1U];\r\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\r\n  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\r\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\r\n        uint32_t RESERVED2[1U];\r\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\r\n  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\r\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\r\n} DWT_Type;\r\n\r\n/* DWT Control Register Definitions */\r\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\r\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\r\n\r\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\r\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\r\n\r\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\r\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\r\n\r\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\r\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\r\n\r\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\r\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\r\n\r\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\r\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\r\n\r\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\r\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\r\n\r\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\r\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\r\n\r\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\r\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\r\n\r\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\r\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\r\n\r\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\r\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\r\n\r\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\r\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\r\n\r\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\r\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\r\n\r\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\r\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\r\n\r\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\r\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\r\n\r\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\r\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\r\n\r\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\r\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\r\n\r\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\r\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\r\n\r\n/* DWT CPI Count Register Definitions */\r\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\r\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\r\n\r\n/* DWT Exception Overhead Count Register Definitions */\r\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\r\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\r\n\r\n/* DWT Sleep Count Register Definitions */\r\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\r\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r\n\r\n/* DWT LSU Count Register Definitions */\r\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\r\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\r\n\r\n/* DWT Folded-instruction Count Register Definitions */\r\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\r\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\r\n\r\n/* DWT Comparator Mask Register Definitions */\r\n#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\r\n#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\r\n\r\n/* DWT Comparator Function Register Definitions */\r\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\r\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\r\n\r\n#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\r\n#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\r\n\r\n#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\r\n#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\r\n\r\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\r\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\r\n\r\n#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\r\n#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\r\n\r\n#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\r\n#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\r\n\r\n#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\r\n#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\r\n\r\n#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\r\n#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\r\n\r\n#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\r\n#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\r\n\r\n/*@}*/ /* end of group CMSIS_DWT */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\r\n  \\brief    Type definitions for the Trace Port Interface (TPI)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\r\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\r\n        uint32_t RESERVED0[2U];\r\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\r\n        uint32_t RESERVED1[55U];\r\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\r\n        uint32_t RESERVED2[131U];\r\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\r\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\r\n  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\r\n        uint32_t RESERVED3[759U];\r\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */\r\n  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\r\n  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\r\n        uint32_t RESERVED4[1U];\r\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\r\n  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\r\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\r\n        uint32_t RESERVED5[39U];\r\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\r\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\r\n        uint32_t RESERVED7[8U];\r\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\r\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\r\n} TPI_Type;\r\n\r\n/* TPI Asynchronous Clock Prescaler Register Definitions */\r\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\r\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\r\n\r\n/* TPI Selected Pin Protocol Register Definitions */\r\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\r\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\r\n\r\n/* TPI Formatter and Flush Status Register Definitions */\r\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\r\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\r\n\r\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\r\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\r\n\r\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\r\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\r\n\r\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\r\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\r\n\r\n/* TPI Formatter and Flush Control Register Definitions */\r\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\r\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\r\n\r\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\r\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\r\n\r\n/* TPI TRIGGER Register Definitions */\r\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\r\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\r\n\r\n/* TPI Integration ETM Data Register Definitions (FIFO0) */\r\n#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\r\n#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\r\n\r\n#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\r\n#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\r\n\r\n#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\r\n#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\r\n\r\n#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\r\n#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\r\n\r\n#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\r\n#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\r\n\r\n#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\r\n#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\r\n\r\n#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\r\n#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\r\n\r\n/* TPI ITATBCTR2 Register Definitions */\r\n#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */\r\n#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */\r\n\r\n/* TPI Integration ITM Data Register Definitions (FIFO1) */\r\n#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\r\n#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\r\n\r\n#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\r\n#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\r\n\r\n#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\r\n#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\r\n\r\n#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\r\n#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\r\n\r\n#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\r\n#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\r\n\r\n#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\r\n#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\r\n\r\n#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\r\n#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\r\n\r\n/* TPI ITATBCTR0 Register Definitions */\r\n#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */\r\n#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */\r\n\r\n/* TPI Integration Mode Control Register Definitions */\r\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\r\n#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\r\n\r\n/* TPI DEVID Register Definitions */\r\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\r\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\r\n\r\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\r\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\r\n\r\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\r\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\r\n\r\n#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\r\n#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\r\n\r\n#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\r\n#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\r\n\r\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\r\n#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\r\n\r\n/* TPI DEVTYPE Register Definitions */\r\n#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */\r\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\r\n\r\n#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */\r\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\r\n\r\n/*@}*/ /* end of group CMSIS_TPI */\r\n\r\n\r\n#if (__MPU_PRESENT == 1U)\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\r\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\r\n */\r\ntypedef struct\r\n{\r\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\r\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\r\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\r\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\r\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\r\n  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\r\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\r\n  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\r\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\r\n  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\r\n} MPU_Type;\r\n\r\n/* MPU Type Register Definitions */\r\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\r\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r\n\r\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\r\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r\n\r\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\r\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\r\n\r\n/* MPU Control Register Definitions */\r\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\r\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r\n\r\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\r\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r\n\r\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\r\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\r\n\r\n/* MPU Region Number Register Definitions */\r\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\r\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\r\n\r\n/* MPU Region Base Address Register Definitions */\r\n#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\r\n#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\r\n\r\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\r\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\r\n\r\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\r\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\r\n\r\n/* MPU Region Attribute and Size Register Definitions */\r\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\r\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\r\n\r\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\r\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\r\n\r\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\r\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\r\n\r\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\r\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\r\n\r\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\r\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\r\n\r\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\r\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\r\n\r\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\r\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\r\n\r\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\r\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\r\n\r\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\r\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\r\n\r\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\r\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\r\n\r\n/*@} end of group CMSIS_MPU */\r\n#endif\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r\n  \\brief    Type definitions for the Core Debug Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\r\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\r\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\r\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\r\n} CoreDebug_Type;\r\n\r\n/* Debug Halting Control and Status Register Definitions */\r\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\r\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\r\n\r\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\r\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r\n\r\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r\n\r\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\r\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r\n\r\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\r\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\r\n\r\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\r\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\r\n\r\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\r\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\r\n\r\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r\n\r\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\r\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r\n\r\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\r\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\r\n\r\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\r\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\r\n\r\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r\n\r\n/* Debug Core Register Selector Register Definitions */\r\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\r\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\r\n\r\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\r\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\r\n\r\n/* Debug Exception and Monitor Control Register Definitions */\r\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\r\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\r\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\r\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\r\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\r\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\r\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\r\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\r\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\r\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\r\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\r\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\r\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r\n\r\n/*@} end of group CMSIS_CoreDebug */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\r\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief   Mask and shift a bit field value for use in a register bit range.\r\n  \\param[in] field  Name of the register bit field.\r\n  \\param[in] value  Value of the bit field.\r\n  \\return           Masked and shifted value.\r\n*/\r\n#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)\r\n\r\n/**\r\n  \\brief     Mask and shift a register value to extract a bit filed value.\r\n  \\param[in] field  Name of the register bit field.\r\n  \\param[in] value  Value of register.\r\n  \\return           Masked and shifted bit field value.\r\n*/\r\n#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)\r\n\r\n/*@} end of group CMSIS_core_bitfield */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_core_base     Core Definitions\r\n  \\brief      Definitions for base addresses, unions, and structures.\r\n  @{\r\n */\r\n\r\n/* Memory mapping of Cortex-M3 Hardware */\r\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\r\n#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\r\n#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\r\n#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\r\n#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\r\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\r\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\r\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\r\n\r\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\r\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\r\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\r\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\r\n#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\r\n#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\r\n#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\r\n#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\r\n\r\n#if (__MPU_PRESENT == 1U)\r\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\r\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\r\n#endif\r\n\r\n/*@} */\r\n\r\n\r\n\r\n/*******************************************************************************\r\n *                Hardware Abstraction Layer\r\n  Core Function Interface contains:\r\n  - Core NVIC Functions\r\n  - Core SysTick Functions\r\n  - Core Debug Functions\r\n  - Core Register Access Functions\r\n ******************************************************************************/\r\n/**\r\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r\n*/\r\n\r\n\r\n\r\n/* ##########################   NVIC functions  #################################### */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\r\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief   Set Priority Grouping\r\n  \\details Sets the priority grouping field using the required unlock sequence.\r\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r\n           Only values from 0..7 are used.\r\n           In case of a conflict between priority grouping and available\r\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r\n  \\param [in]      PriorityGroup  Priority grouping field.\r\n */\r\n__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r\n{\r\n  uint32_t reg_value;\r\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\r\n\r\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\r\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\r\n  reg_value  =  (reg_value                                   |\r\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r\n                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */\r\n  SCB->AIRCR =  reg_value;\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Priority Grouping\r\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\r\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r\n{\r\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Enable External Interrupt\r\n  \\details Enables a device-specific interrupt in the NVIC interrupt controller.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Disable External Interrupt\r\n  \\details Disables a device-specific interrupt in the NVIC interrupt controller.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Pending Interrupt\r\n  \\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\return             0  Interrupt status is not pending.\r\n  \\return             1  Interrupt status is pending.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Pending Interrupt\r\n  \\details Sets the pending bit of an external interrupt.\r\n  \\param [in]      IRQn  Interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Clear Pending Interrupt\r\n  \\details Clears the pending bit of an external interrupt.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Active Interrupt\r\n  \\details Reads the active register in NVIC and returns the active bit.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\return             0  Interrupt status is not active.\r\n  \\return             1  Interrupt status is active.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r\n{\r\n  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Interrupt Priority\r\n  \\details Sets the priority of an interrupt.\r\n  \\note    The priority cannot be set for every core interrupt.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\param [in]  priority  Priority to set.\r\n */\r\n__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r\n{\r\n  if ((int32_t)(IRQn) < 0)\r\n  {\r\n    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r\n  }\r\n  else\r\n  {\r\n    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Interrupt Priority\r\n  \\details Reads the priority of an interrupt.\r\n           The interrupt number can be positive to specify an external (device specific) interrupt,\r\n           or negative to specify an internal (core) interrupt.\r\n  \\param [in]   IRQn  Interrupt number.\r\n  \\return             Interrupt Priority.\r\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r\n{\r\n\r\n  if ((int32_t)(IRQn) < 0)\r\n  {\r\n    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r\n  }\r\n  else\r\n  {\r\n    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Encode Priority\r\n  \\details Encodes the priority for an interrupt with the given priority group,\r\n           preemptive priority value, and subpriority value.\r\n           In case of a conflict between priority grouping and available\r\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r\n  \\param [in]     PriorityGroup  Used priority group.\r\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\r\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\r\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\r\n */\r\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r\n{\r\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r\n  uint32_t PreemptPriorityBits;\r\n  uint32_t SubPriorityBits;\r\n\r\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r\n\r\n  return (\r\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\r\n         );\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Decode Priority\r\n  \\details Decodes an interrupt priority value with a given priority group to\r\n           preemptive priority value and subpriority value.\r\n           In case of a conflict between priority grouping and available\r\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\r\n  \\param [in]     PriorityGroup  Used priority group.\r\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\r\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\r\n */\r\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r\n{\r\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r\n  uint32_t PreemptPriorityBits;\r\n  uint32_t SubPriorityBits;\r\n\r\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r\n\r\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   System Reset\r\n  \\details Initiates a system reset request to reset the MCU.\r\n */\r\n__STATIC_INLINE void NVIC_SystemReset(void)\r\n{\r\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\r\n                                                                       buffered write are completed before reset */\r\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\r\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\r\n  __DSB();                                                          /* Ensure completion of memory access */\r\n\r\n  for(;;)                                                           /* wait until reset */\r\n  {\r\n    __NOP();\r\n  }\r\n}\r\n\r\n/*@} end of CMSIS_Core_NVICFunctions */\r\n\r\n\r\n\r\n/* ##################################    SysTick function  ############################################ */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r\n  \\brief    Functions that configure the System.\r\n  @{\r\n */\r\n\r\n#if (__Vendor_SysTickConfig == 0U)\r\n\r\n/**\r\n  \\brief   System Tick Configuration\r\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r\n           Counter is in free running mode to generate periodic interrupts.\r\n  \\param [in]  ticks  Number of ticks between two interrupts.\r\n  \\return          0  Function succeeded.\r\n  \\return          1  Function failed.\r\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r\n           must contain a vendor-specific implementation of this function.\r\n */\r\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r\n{\r\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r\n  {\r\n    return (1UL);                                                   /* Reload value impossible */\r\n  }\r\n\r\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r\n                   SysTick_CTRL_TICKINT_Msk   |\r\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r\n  return (0UL);                                                     /* Function successful */\r\n}\r\n\r\n#endif\r\n\r\n/*@} end of CMSIS_Core_SysTickFunctions */\r\n\r\n\r\n\r\n/* ##################################### Debug In/Output function ########################################### */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\r\n  \\brief    Functions that access the ITM debug interface.\r\n  @{\r\n */\r\n\r\nextern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters. */\r\n#define                 ITM_RXBUFFER_EMPTY   0x5AA55AA5U /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\r\n\r\n\r\n/**\r\n  \\brief   ITM Send Character\r\n  \\details Transmits a character via the ITM channel 0, and\r\n           \\li Just returns when no debugger is connected that has booked the output.\r\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r\n  \\param [in]     ch  Character to transmit.\r\n  \\returns            Character to transmit.\r\n */\r\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r\n{\r\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\r\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\r\n  {\r\n    while (ITM->PORT[0U].u32 == 0UL)\r\n    {\r\n      __NOP();\r\n    }\r\n    ITM->PORT[0U].u8 = (uint8_t)ch;\r\n  }\r\n  return (ch);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   ITM Receive Character\r\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\r\n  \\return             Received character.\r\n  \\return         -1  No character pending.\r\n */\r\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r\n{\r\n  int32_t ch = -1;                           /* no character available */\r\n\r\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r\n  {\r\n    ch = ITM_RxBuffer;\r\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\r\n  }\r\n\r\n  return (ch);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   ITM Check Character\r\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\r\n  \\return          0  No character available.\r\n  \\return          1  Character available.\r\n */\r\n__STATIC_INLINE int32_t ITM_CheckChar (void)\r\n{\r\n\r\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r\n  {\r\n    return (0);                              /* no character available */\r\n  }\r\n  else\r\n  {\r\n    return (1);                              /*    character available */\r\n  }\r\n}\r\n\r\n/*@} end of CMSIS_core_DebugFunctions */\r\n\r\n\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __CORE_CM3_H_DEPENDANT */\r\n\r\n#endif /* __CMSIS_GENERIC */\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/bsp/opencr/include/core_cm4.h",
    "content": "/**************************************************************************//**\r\n * @file     core_cm4.h\r\n * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File\r\n * @version  V4.30\r\n * @date     20. October 2015\r\n ******************************************************************************/\r\n/* Copyright (c) 2009 - 2015 ARM LIMITED\r\n\r\n   All rights reserved.\r\n   Redistribution and use in source and binary forms, with or without\r\n   modification, are permitted provided that the following conditions are met:\r\n   - Redistributions of source code must retain the above copyright\r\n     notice, this list of conditions and the following disclaimer.\r\n   - Redistributions in binary form must reproduce the above copyright\r\n     notice, this list of conditions and the following disclaimer in the\r\n     documentation and/or other materials provided with the distribution.\r\n   - Neither the name of ARM nor the names of its contributors may be used\r\n     to endorse or promote products derived from this software without\r\n     specific prior written permission.\r\n   *\r\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n   POSSIBILITY OF SUCH DAMAGE.\r\n   ---------------------------------------------------------------------------*/\r\n\r\n\r\n#if   defined ( __ICCARM__ )\r\n #pragma system_include         /* treat file as system include file for MISRA check */\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #pragma clang system_header   /* treat file as system include file */\r\n#endif\r\n\r\n#ifndef __CORE_CM4_H_GENERIC\r\n#define __CORE_CM4_H_GENERIC\r\n\r\n#include <stdint.h>\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/**\r\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r\n  CMSIS violates the following MISRA-C:2004 rules:\r\n\r\n   \\li Required Rule 8.5, object/function definition in header file.<br>\r\n     Function definitions in header files are used to allow 'inlining'.\r\n\r\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r\n     Unions are used for effective representation of core registers.\r\n\r\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\r\n     Function-like macros are used to allow more efficient code.\r\n */\r\n\r\n\r\n/*******************************************************************************\r\n *                 CMSIS definitions\r\n ******************************************************************************/\r\n/**\r\n  \\ingroup Cortex_M4\r\n  @{\r\n */\r\n\r\n/*  CMSIS CM4 definitions */\r\n#define __CM4_CMSIS_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CMSIS HAL main version */\r\n#define __CM4_CMSIS_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CMSIS HAL sub version */\r\n#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \\\r\n                                    __CM4_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL version number */\r\n\r\n#define __CORTEX_M                (0x04U)                                      /*!< Cortex-M Core */\r\n\r\n\r\n#if   defined ( __CC_ARM )\r\n  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */\r\n  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */\r\n  #define __STATIC_INLINE  static __inline\r\n\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */\r\n  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */\r\n  #define __STATIC_INLINE  static __inline\r\n\r\n#elif defined ( __GNUC__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __ICCARM__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __TMS470__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __TASKING__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __CSMC__ )\r\n  #define __packed\r\n  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */\r\n  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#else\r\n  #error Unknown compiler\r\n#endif\r\n\r\n/** __FPU_USED indicates whether an FPU is used or not.\r\n    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r\n*/\r\n#if defined ( __CC_ARM )\r\n  #if defined __TARGET_FPU_VFP\r\n    #if (__FPU_PRESENT == 1U)\r\n      #define __FPU_USED       1U\r\n    #else\r\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n      #define __FPU_USED       0U\r\n    #endif\r\n  #else\r\n    #define __FPU_USED         0U\r\n  #endif\r\n\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #if defined __ARM_PCS_VFP\r\n    #if (__FPU_PRESENT == 1)\r\n      #define __FPU_USED       1U\r\n    #else\r\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n      #define __FPU_USED       0U\r\n    #endif\r\n  #else\r\n    #define __FPU_USED         0U\r\n  #endif\r\n\r\n#elif defined ( __GNUC__ )\r\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r\n    #if (__FPU_PRESENT == 1U)\r\n      #define __FPU_USED       1U\r\n    #else\r\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n      #define __FPU_USED       0U\r\n    #endif\r\n  #else\r\n    #define __FPU_USED         0U\r\n  #endif\r\n\r\n#elif defined ( __ICCARM__ )\r\n  #if defined __ARMVFP__\r\n    #if (__FPU_PRESENT == 1U)\r\n      #define __FPU_USED       1U\r\n    #else\r\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n      #define __FPU_USED       0U\r\n    #endif\r\n  #else\r\n    #define __FPU_USED         0U\r\n  #endif\r\n\r\n#elif defined ( __TMS470__ )\r\n  #if defined __TI_VFP_SUPPORT__\r\n    #if (__FPU_PRESENT == 1U)\r\n      #define __FPU_USED       1U\r\n    #else\r\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n      #define __FPU_USED       0U\r\n    #endif\r\n  #else\r\n    #define __FPU_USED         0U\r\n  #endif\r\n\r\n#elif defined ( __TASKING__ )\r\n  #if defined __FPU_VFP__\r\n    #if (__FPU_PRESENT == 1U)\r\n      #define __FPU_USED       1U\r\n    #else\r\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n      #define __FPU_USED       0U\r\n    #endif\r\n  #else\r\n    #define __FPU_USED         0U\r\n  #endif\r\n\r\n#elif defined ( __CSMC__ )\r\n  #if ( __CSMC__ & 0x400U)\r\n    #if (__FPU_PRESENT == 1U)\r\n      #define __FPU_USED       1U\r\n    #else\r\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n      #define __FPU_USED       0U\r\n    #endif\r\n  #else\r\n    #define __FPU_USED         0U\r\n  #endif\r\n\r\n#endif\r\n\r\n#include \"core_cmInstr.h\"                /* Core Instruction Access */\r\n#include \"core_cmFunc.h\"                 /* Core Function Access */\r\n#include \"core_cmSimd.h\"                 /* Compiler specific SIMD Intrinsics */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __CORE_CM4_H_GENERIC */\r\n\r\n#ifndef __CMSIS_GENERIC\r\n\r\n#ifndef __CORE_CM4_H_DEPENDANT\r\n#define __CORE_CM4_H_DEPENDANT\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* check device defines and use defaults */\r\n#if defined __CHECK_DEVICE_DEFINES\r\n  #ifndef __CM4_REV\r\n    #define __CM4_REV               0x0000U\r\n    #warning \"__CM4_REV not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __FPU_PRESENT\r\n    #define __FPU_PRESENT             0U\r\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __MPU_PRESENT\r\n    #define __MPU_PRESENT             0U\r\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __NVIC_PRIO_BITS\r\n    #define __NVIC_PRIO_BITS          4U\r\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __Vendor_SysTickConfig\r\n    #define __Vendor_SysTickConfig    0U\r\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\r\n  #endif\r\n#endif\r\n\r\n/* IO definitions (access restrictions to peripheral registers) */\r\n/**\r\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\r\n\r\n    <strong>IO Type Qualifiers</strong> are used\r\n    \\li to specify the access to peripheral variables.\r\n    \\li for automatic generation of peripheral register debug information.\r\n*/\r\n#ifdef __cplusplus\r\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\r\n#else\r\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r\n#endif\r\n#define     __O     volatile             /*!< Defines 'write only' permissions */\r\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r\n\r\n/* following defines should be used for structure members */\r\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r\n\r\n/*@} end of group Cortex_M4 */\r\n\r\n\r\n\r\n/*******************************************************************************\r\n *                 Register Abstraction\r\n  Core Register contain:\r\n  - Core Register\r\n  - Core NVIC Register\r\n  - Core SCB Register\r\n  - Core SysTick Register\r\n  - Core Debug Register\r\n  - Core MPU Register\r\n  - Core FPU Register\r\n ******************************************************************************/\r\n/**\r\n  \\defgroup CMSIS_core_register Defines and Type Definitions\r\n  \\brief Type definitions and defines for Cortex-M processor based devices.\r\n*/\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_CORE  Status and Control Registers\r\n  \\brief      Core Register type definitions.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Union type to access the Application Program Status Register (APSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\r\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\r\n    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\r\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} APSR_Type;\r\n\r\n/* APSR Register Definitions */\r\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r\n\r\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r\n\r\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r\n\r\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r\n\r\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\r\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\r\n\r\n#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\r\n#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} IPSR_Type;\r\n\r\n/* IPSR Register Definitions */\r\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r\n    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */\r\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\r\n    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\r\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\r\n    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */\r\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} xPSR_Type;\r\n\r\n/* xPSR Register Definitions */\r\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r\n\r\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r\n\r\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r\n\r\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r\n\r\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\r\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\r\n\r\n#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */\r\n#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */\r\n\r\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r\n\r\n#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\r\n#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\r\n\r\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Control Registers (CONTROL).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\r\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\r\n    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */\r\n    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} CONTROL_Type;\r\n\r\n/* CONTROL Register Definitions */\r\n#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\r\n#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\r\n\r\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r\n\r\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\r\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\r\n\r\n/*@} end of group CMSIS_CORE */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r\n  \\brief      Type definitions for the NVIC Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r\n        uint32_t RESERVED0[24U];\r\n  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r\n        uint32_t RSERVED1[24U];\r\n  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r\n        uint32_t RESERVED2[24U];\r\n  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r\n        uint32_t RESERVED3[24U];\r\n  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\r\n        uint32_t RESERVED4[56U];\r\n  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\r\n        uint32_t RESERVED5[644U];\r\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\r\n}  NVIC_Type;\r\n\r\n/* Software Triggered Interrupt Register Definitions */\r\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\r\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\r\n\r\n/*@} end of group CMSIS_NVIC */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\r\n  \\brief    Type definitions for the System Control Block Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Control Block (SCB).\r\n */\r\ntypedef struct\r\n{\r\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\r\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r\n  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\r\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\r\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\r\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\r\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\r\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\r\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\r\n  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */\r\n  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */\r\n  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\r\n  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\r\n  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\r\n        uint32_t RESERVED0[5U];\r\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\r\n} SCB_Type;\r\n\r\n/* SCB CPUID Register Definitions */\r\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r\n\r\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r\n\r\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r\n\r\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r\n\r\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r\n\r\n/* SCB Interrupt Control State Register Definitions */\r\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\r\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\r\n\r\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r\n\r\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r\n\r\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r\n\r\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r\n\r\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r\n\r\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r\n\r\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r\n\r\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\r\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\r\n\r\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r\n\r\n/* SCB Vector Table Offset Register Definitions */\r\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\r\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\r\n\r\n/* SCB Application Interrupt and Reset Control Register Definitions */\r\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r\n\r\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r\n\r\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r\n\r\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\r\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\r\n\r\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r\n\r\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r\n\r\n#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\r\n#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\r\n\r\n/* SCB System Control Register Definitions */\r\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r\n\r\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r\n\r\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r\n\r\n/* SCB Configuration Control Register Definitions */\r\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\r\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\r\n\r\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\r\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\r\n\r\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\r\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\r\n\r\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r\n\r\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\r\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\r\n\r\n#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\r\n#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\r\n\r\n/* SCB System Handler Control and State Register Definitions */\r\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\r\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\r\n\r\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\r\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\r\n\r\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\r\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\r\n\r\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r\n\r\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\r\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r\n\r\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\r\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r\n\r\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\r\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\r\n\r\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\r\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\r\n\r\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\r\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\r\n\r\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\r\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\r\n\r\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\r\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\r\n\r\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\r\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\r\n\r\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\r\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\r\n\r\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\r\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\r\n\r\n/* SCB Configurable Fault Status Register Definitions */\r\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\r\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\r\n\r\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\r\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\r\n\r\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r\n\r\n/* SCB Hard Fault Status Register Definitions */\r\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\r\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\r\n\r\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\r\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\r\n\r\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\r\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\r\n\r\n/* SCB Debug Fault Status Register Definitions */\r\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\r\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\r\n\r\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\r\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\r\n\r\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\r\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\r\n\r\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\r\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\r\n\r\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\r\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\r\n\r\n/*@} end of group CMSIS_SCB */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\r\n */\r\ntypedef struct\r\n{\r\n        uint32_t RESERVED0[1U];\r\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\r\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\r\n} SCnSCB_Type;\r\n\r\n/* Interrupt Controller Type Register Definitions */\r\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\r\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\r\n\r\n/* Auxiliary Control Register Definitions */\r\n#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */\r\n#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */\r\n\r\n#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */\r\n#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */\r\n\r\n#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */\r\n#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */\r\n\r\n#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */\r\n#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */\r\n\r\n#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\r\n#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\r\n\r\n/*@} end of group CMSIS_SCnotSCB */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r\n  \\brief    Type definitions for the System Timer Registers.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Timer (SysTick).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r\n} SysTick_Type;\r\n\r\n/* SysTick Control / Status Register Definitions */\r\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r\n\r\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r\n\r\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r\n\r\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r\n\r\n/* SysTick Reload Register Definitions */\r\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r\n\r\n/* SysTick Current Register Definitions */\r\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r\n\r\n/* SysTick Calibration Register Definitions */\r\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r\n\r\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r\n\r\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r\n\r\n/*@} end of group CMSIS_SysTick */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\r\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r\n */\r\ntypedef struct\r\n{\r\n  __OM  union\r\n  {\r\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\r\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\r\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\r\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\r\n        uint32_t RESERVED0[864U];\r\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\r\n        uint32_t RESERVED1[15U];\r\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\r\n        uint32_t RESERVED2[15U];\r\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\r\n        uint32_t RESERVED3[29U];\r\n  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\r\n  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\r\n  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\r\n        uint32_t RESERVED4[43U];\r\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\r\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\r\n        uint32_t RESERVED5[6U];\r\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\r\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\r\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\r\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\r\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\r\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\r\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\r\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\r\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\r\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\r\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\r\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\r\n} ITM_Type;\r\n\r\n/* ITM Trace Privilege Register Definitions */\r\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\r\n#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */\r\n\r\n/* ITM Trace Control Register Definitions */\r\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\r\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\r\n\r\n#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\r\n#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */\r\n\r\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\r\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\r\n\r\n#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\r\n#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\r\n\r\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\r\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\r\n\r\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\r\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\r\n\r\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\r\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\r\n\r\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\r\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\r\n\r\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\r\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\r\n\r\n/* ITM Integration Write Register Definitions */\r\n#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */\r\n#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\r\n\r\n/* ITM Integration Read Register Definitions */\r\n#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */\r\n#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\r\n\r\n/* ITM Integration Mode Control Register Definitions */\r\n#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */\r\n#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\r\n\r\n/* ITM Lock Status Register Definitions */\r\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\r\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\r\n\r\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\r\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\r\n\r\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\r\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\r\n\r\n/*@}*/ /* end of group CMSIS_ITM */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\r\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\r\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\r\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\r\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\r\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\r\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\r\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\r\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\r\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\r\n  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\r\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\r\n        uint32_t RESERVED0[1U];\r\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\r\n  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\r\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\r\n        uint32_t RESERVED1[1U];\r\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\r\n  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\r\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\r\n        uint32_t RESERVED2[1U];\r\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\r\n  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\r\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\r\n} DWT_Type;\r\n\r\n/* DWT Control Register Definitions */\r\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\r\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\r\n\r\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\r\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\r\n\r\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\r\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\r\n\r\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\r\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\r\n\r\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\r\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\r\n\r\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\r\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\r\n\r\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\r\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\r\n\r\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\r\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\r\n\r\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\r\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\r\n\r\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\r\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\r\n\r\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\r\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\r\n\r\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\r\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\r\n\r\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\r\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\r\n\r\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\r\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\r\n\r\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\r\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\r\n\r\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\r\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\r\n\r\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\r\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\r\n\r\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\r\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\r\n\r\n/* DWT CPI Count Register Definitions */\r\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\r\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\r\n\r\n/* DWT Exception Overhead Count Register Definitions */\r\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\r\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\r\n\r\n/* DWT Sleep Count Register Definitions */\r\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\r\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r\n\r\n/* DWT LSU Count Register Definitions */\r\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\r\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\r\n\r\n/* DWT Folded-instruction Count Register Definitions */\r\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\r\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\r\n\r\n/* DWT Comparator Mask Register Definitions */\r\n#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\r\n#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\r\n\r\n/* DWT Comparator Function Register Definitions */\r\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\r\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\r\n\r\n#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\r\n#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\r\n\r\n#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\r\n#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\r\n\r\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\r\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\r\n\r\n#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\r\n#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\r\n\r\n#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\r\n#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\r\n\r\n#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\r\n#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\r\n\r\n#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\r\n#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\r\n\r\n#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\r\n#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\r\n\r\n/*@}*/ /* end of group CMSIS_DWT */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\r\n  \\brief    Type definitions for the Trace Port Interface (TPI)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\r\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\r\n        uint32_t RESERVED0[2U];\r\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\r\n        uint32_t RESERVED1[55U];\r\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\r\n        uint32_t RESERVED2[131U];\r\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\r\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\r\n  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\r\n        uint32_t RESERVED3[759U];\r\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */\r\n  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\r\n  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\r\n        uint32_t RESERVED4[1U];\r\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\r\n  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\r\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\r\n        uint32_t RESERVED5[39U];\r\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\r\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\r\n        uint32_t RESERVED7[8U];\r\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\r\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\r\n} TPI_Type;\r\n\r\n/* TPI Asynchronous Clock Prescaler Register Definitions */\r\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\r\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\r\n\r\n/* TPI Selected Pin Protocol Register Definitions */\r\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\r\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\r\n\r\n/* TPI Formatter and Flush Status Register Definitions */\r\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\r\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\r\n\r\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\r\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\r\n\r\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\r\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\r\n\r\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\r\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\r\n\r\n/* TPI Formatter and Flush Control Register Definitions */\r\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\r\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\r\n\r\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\r\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\r\n\r\n/* TPI TRIGGER Register Definitions */\r\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\r\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\r\n\r\n/* TPI Integration ETM Data Register Definitions (FIFO0) */\r\n#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\r\n#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\r\n\r\n#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\r\n#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\r\n\r\n#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\r\n#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\r\n\r\n#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\r\n#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\r\n\r\n#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\r\n#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\r\n\r\n#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\r\n#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\r\n\r\n#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\r\n#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\r\n\r\n/* TPI ITATBCTR2 Register Definitions */\r\n#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */\r\n#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */\r\n\r\n/* TPI Integration ITM Data Register Definitions (FIFO1) */\r\n#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\r\n#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\r\n\r\n#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\r\n#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\r\n\r\n#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\r\n#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\r\n\r\n#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\r\n#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\r\n\r\n#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\r\n#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\r\n\r\n#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\r\n#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\r\n\r\n#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\r\n#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\r\n\r\n/* TPI ITATBCTR0 Register Definitions */\r\n#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */\r\n#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */\r\n\r\n/* TPI Integration Mode Control Register Definitions */\r\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\r\n#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\r\n\r\n/* TPI DEVID Register Definitions */\r\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\r\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\r\n\r\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\r\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\r\n\r\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\r\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\r\n\r\n#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\r\n#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\r\n\r\n#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\r\n#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\r\n\r\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\r\n#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\r\n\r\n/* TPI DEVTYPE Register Definitions */\r\n#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */\r\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\r\n\r\n#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */\r\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\r\n\r\n/*@}*/ /* end of group CMSIS_TPI */\r\n\r\n\r\n#if (__MPU_PRESENT == 1U)\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\r\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\r\n */\r\ntypedef struct\r\n{\r\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\r\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\r\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\r\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\r\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\r\n  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\r\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\r\n  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\r\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\r\n  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\r\n} MPU_Type;\r\n\r\n/* MPU Type Register Definitions */\r\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\r\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r\n\r\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\r\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r\n\r\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\r\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\r\n\r\n/* MPU Control Register Definitions */\r\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\r\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r\n\r\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\r\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r\n\r\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\r\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\r\n\r\n/* MPU Region Number Register Definitions */\r\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\r\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\r\n\r\n/* MPU Region Base Address Register Definitions */\r\n#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\r\n#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\r\n\r\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\r\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\r\n\r\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\r\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\r\n\r\n/* MPU Region Attribute and Size Register Definitions */\r\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\r\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\r\n\r\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\r\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\r\n\r\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\r\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\r\n\r\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\r\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\r\n\r\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\r\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\r\n\r\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\r\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\r\n\r\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\r\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\r\n\r\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\r\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\r\n\r\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\r\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\r\n\r\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\r\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\r\n\r\n/*@} end of group CMSIS_MPU */\r\n#endif\r\n\r\n\r\n#if (__FPU_PRESENT == 1U)\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_FPU     Floating Point Unit (FPU)\r\n  \\brief    Type definitions for the Floating Point Unit (FPU)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Floating Point Unit (FPU).\r\n */\r\ntypedef struct\r\n{\r\n        uint32_t RESERVED0[1U];\r\n  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\r\n  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\r\n  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\r\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */\r\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */\r\n} FPU_Type;\r\n\r\n/* Floating-Point Context Control Register Definitions */\r\n#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\r\n#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\r\n\r\n#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\r\n#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\r\n\r\n#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\r\n#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\r\n\r\n#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\r\n#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\r\n\r\n#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\r\n#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\r\n\r\n#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\r\n#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\r\n\r\n#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\r\n#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\r\n\r\n#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\r\n#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\r\n\r\n#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\r\n#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\r\n\r\n/* Floating-Point Context Address Register Definitions */\r\n#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\r\n#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\r\n\r\n/* Floating-Point Default Status Control Register Definitions */\r\n#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\r\n#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\r\n\r\n#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\r\n#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\r\n\r\n#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\r\n#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\r\n\r\n#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\r\n#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\r\n\r\n/* Media and FP Feature Register 0 Definitions */\r\n#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */\r\n#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */\r\n\r\n#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */\r\n#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */\r\n\r\n#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */\r\n#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */\r\n\r\n#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */\r\n#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */\r\n\r\n#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */\r\n#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */\r\n\r\n#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */\r\n#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */\r\n\r\n#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */\r\n#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */\r\n\r\n#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */\r\n#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */\r\n\r\n/* Media and FP Feature Register 1 Definitions */\r\n#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */\r\n#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */\r\n\r\n#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */\r\n#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */\r\n\r\n#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */\r\n#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */\r\n\r\n#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */\r\n#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */\r\n\r\n/*@} end of group CMSIS_FPU */\r\n#endif\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r\n  \\brief    Type definitions for the Core Debug Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\r\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\r\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\r\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\r\n} CoreDebug_Type;\r\n\r\n/* Debug Halting Control and Status Register Definitions */\r\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\r\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\r\n\r\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\r\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r\n\r\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r\n\r\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\r\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r\n\r\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\r\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\r\n\r\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\r\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\r\n\r\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\r\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\r\n\r\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r\n\r\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\r\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r\n\r\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\r\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\r\n\r\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\r\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\r\n\r\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r\n\r\n/* Debug Core Register Selector Register Definitions */\r\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\r\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\r\n\r\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\r\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\r\n\r\n/* Debug Exception and Monitor Control Register Definitions */\r\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\r\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\r\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\r\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\r\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\r\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\r\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\r\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\r\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\r\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\r\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\r\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\r\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r\n\r\n/*@} end of group CMSIS_CoreDebug */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\r\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief   Mask and shift a bit field value for use in a register bit range.\r\n  \\param[in] field  Name of the register bit field.\r\n  \\param[in] value  Value of the bit field.\r\n  \\return           Masked and shifted value.\r\n*/\r\n#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)\r\n\r\n/**\r\n  \\brief     Mask and shift a register value to extract a bit filed value.\r\n  \\param[in] field  Name of the register bit field.\r\n  \\param[in] value  Value of register.\r\n  \\return           Masked and shifted bit field value.\r\n*/\r\n#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)\r\n\r\n/*@} end of group CMSIS_core_bitfield */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_core_base     Core Definitions\r\n  \\brief      Definitions for base addresses, unions, and structures.\r\n  @{\r\n */\r\n\r\n/* Memory mapping of Cortex-M4 Hardware */\r\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\r\n#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\r\n#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\r\n#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\r\n#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\r\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\r\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\r\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\r\n\r\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\r\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\r\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\r\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\r\n#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\r\n#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\r\n#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\r\n#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\r\n\r\n#if (__MPU_PRESENT == 1U)\r\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\r\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\r\n#endif\r\n\r\n#if (__FPU_PRESENT == 1U)\r\n  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */\r\n  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */\r\n#endif\r\n\r\n/*@} */\r\n\r\n\r\n\r\n/*******************************************************************************\r\n *                Hardware Abstraction Layer\r\n  Core Function Interface contains:\r\n  - Core NVIC Functions\r\n  - Core SysTick Functions\r\n  - Core Debug Functions\r\n  - Core Register Access Functions\r\n ******************************************************************************/\r\n/**\r\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r\n*/\r\n\r\n\r\n\r\n/* ##########################   NVIC functions  #################################### */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\r\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief   Set Priority Grouping\r\n  \\details Sets the priority grouping field using the required unlock sequence.\r\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r\n           Only values from 0..7 are used.\r\n           In case of a conflict between priority grouping and available\r\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r\n  \\param [in]      PriorityGroup  Priority grouping field.\r\n */\r\n__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r\n{\r\n  uint32_t reg_value;\r\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\r\n\r\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\r\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\r\n  reg_value  =  (reg_value                                   |\r\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r\n                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */\r\n  SCB->AIRCR =  reg_value;\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Priority Grouping\r\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\r\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r\n{\r\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Enable External Interrupt\r\n  \\details Enables a device-specific interrupt in the NVIC interrupt controller.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Disable External Interrupt\r\n  \\details Disables a device-specific interrupt in the NVIC interrupt controller.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Pending Interrupt\r\n  \\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\return             0  Interrupt status is not pending.\r\n  \\return             1  Interrupt status is pending.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Pending Interrupt\r\n  \\details Sets the pending bit of an external interrupt.\r\n  \\param [in]      IRQn  Interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Clear Pending Interrupt\r\n  \\details Clears the pending bit of an external interrupt.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Active Interrupt\r\n  \\details Reads the active register in NVIC and returns the active bit.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\return             0  Interrupt status is not active.\r\n  \\return             1  Interrupt status is active.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r\n{\r\n  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Interrupt Priority\r\n  \\details Sets the priority of an interrupt.\r\n  \\note    The priority cannot be set for every core interrupt.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\param [in]  priority  Priority to set.\r\n */\r\n__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r\n{\r\n  if ((int32_t)(IRQn) < 0)\r\n  {\r\n    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r\n  }\r\n  else\r\n  {\r\n    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Interrupt Priority\r\n  \\details Reads the priority of an interrupt.\r\n           The interrupt number can be positive to specify an external (device specific) interrupt,\r\n           or negative to specify an internal (core) interrupt.\r\n  \\param [in]   IRQn  Interrupt number.\r\n  \\return             Interrupt Priority.\r\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r\n{\r\n\r\n  if ((int32_t)(IRQn) < 0)\r\n  {\r\n    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r\n  }\r\n  else\r\n  {\r\n    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Encode Priority\r\n  \\details Encodes the priority for an interrupt with the given priority group,\r\n           preemptive priority value, and subpriority value.\r\n           In case of a conflict between priority grouping and available\r\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r\n  \\param [in]     PriorityGroup  Used priority group.\r\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\r\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\r\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\r\n */\r\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r\n{\r\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r\n  uint32_t PreemptPriorityBits;\r\n  uint32_t SubPriorityBits;\r\n\r\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r\n\r\n  return (\r\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\r\n         );\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Decode Priority\r\n  \\details Decodes an interrupt priority value with a given priority group to\r\n           preemptive priority value and subpriority value.\r\n           In case of a conflict between priority grouping and available\r\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\r\n  \\param [in]     PriorityGroup  Used priority group.\r\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\r\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\r\n */\r\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r\n{\r\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r\n  uint32_t PreemptPriorityBits;\r\n  uint32_t SubPriorityBits;\r\n\r\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r\n\r\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   System Reset\r\n  \\details Initiates a system reset request to reset the MCU.\r\n */\r\n__STATIC_INLINE void NVIC_SystemReset(void)\r\n{\r\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\r\n                                                                       buffered write are completed before reset */\r\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\r\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\r\n  __DSB();                                                          /* Ensure completion of memory access */\r\n\r\n  for(;;)                                                           /* wait until reset */\r\n  {\r\n    __NOP();\r\n  }\r\n}\r\n\r\n/*@} end of CMSIS_Core_NVICFunctions */\r\n\r\n\r\n\r\n/* ##################################    SysTick function  ############################################ */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r\n  \\brief    Functions that configure the System.\r\n  @{\r\n */\r\n\r\n#if (__Vendor_SysTickConfig == 0U)\r\n\r\n/**\r\n  \\brief   System Tick Configuration\r\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r\n           Counter is in free running mode to generate periodic interrupts.\r\n  \\param [in]  ticks  Number of ticks between two interrupts.\r\n  \\return          0  Function succeeded.\r\n  \\return          1  Function failed.\r\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r\n           must contain a vendor-specific implementation of this function.\r\n */\r\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r\n{\r\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r\n  {\r\n    return (1UL);                                                   /* Reload value impossible */\r\n  }\r\n\r\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r\n                   SysTick_CTRL_TICKINT_Msk   |\r\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r\n  return (0UL);                                                     /* Function successful */\r\n}\r\n\r\n#endif\r\n\r\n/*@} end of CMSIS_Core_SysTickFunctions */\r\n\r\n\r\n\r\n/* ##################################### Debug In/Output function ########################################### */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\r\n  \\brief    Functions that access the ITM debug interface.\r\n  @{\r\n */\r\n\r\nextern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters. */\r\n#define                 ITM_RXBUFFER_EMPTY   0x5AA55AA5U /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\r\n\r\n\r\n/**\r\n  \\brief   ITM Send Character\r\n  \\details Transmits a character via the ITM channel 0, and\r\n           \\li Just returns when no debugger is connected that has booked the output.\r\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r\n  \\param [in]     ch  Character to transmit.\r\n  \\returns            Character to transmit.\r\n */\r\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r\n{\r\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\r\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\r\n  {\r\n    while (ITM->PORT[0U].u32 == 0UL)\r\n    {\r\n      __NOP();\r\n    }\r\n    ITM->PORT[0U].u8 = (uint8_t)ch;\r\n  }\r\n  return (ch);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   ITM Receive Character\r\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\r\n  \\return             Received character.\r\n  \\return         -1  No character pending.\r\n */\r\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r\n{\r\n  int32_t ch = -1;                           /* no character available */\r\n\r\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r\n  {\r\n    ch = ITM_RxBuffer;\r\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\r\n  }\r\n\r\n  return (ch);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   ITM Check Character\r\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\r\n  \\return          0  No character available.\r\n  \\return          1  Character available.\r\n */\r\n__STATIC_INLINE int32_t ITM_CheckChar (void)\r\n{\r\n\r\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r\n  {\r\n    return (0);                              /* no character available */\r\n  }\r\n  else\r\n  {\r\n    return (1);                              /*    character available */\r\n  }\r\n}\r\n\r\n/*@} end of CMSIS_core_DebugFunctions */\r\n\r\n\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __CORE_CM4_H_DEPENDANT */\r\n\r\n#endif /* __CMSIS_GENERIC */\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/bsp/opencr/include/core_cm7.h",
    "content": "/**************************************************************************//**\r\n * @file     core_cm7.h\r\n * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File\r\n * @version  V4.30\r\n * @date     20. October 2015\r\n ******************************************************************************/\r\n/* Copyright (c) 2009 - 2015 ARM LIMITED\r\n\r\n   All rights reserved.\r\n   Redistribution and use in source and binary forms, with or without\r\n   modification, are permitted provided that the following conditions are met:\r\n   - Redistributions of source code must retain the above copyright\r\n     notice, this list of conditions and the following disclaimer.\r\n   - Redistributions in binary form must reproduce the above copyright\r\n     notice, this list of conditions and the following disclaimer in the\r\n     documentation and/or other materials provided with the distribution.\r\n   - Neither the name of ARM nor the names of its contributors may be used\r\n     to endorse or promote products derived from this software without\r\n     specific prior written permission.\r\n   *\r\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n   POSSIBILITY OF SUCH DAMAGE.\r\n   ---------------------------------------------------------------------------*/\r\n\r\n\r\n#if   defined ( __ICCARM__ )\r\n #pragma system_include         /* treat file as system include file for MISRA check */\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #pragma clang system_header   /* treat file as system include file */\r\n#endif\r\n\r\n#ifndef __CORE_CM7_H_GENERIC\r\n#define __CORE_CM7_H_GENERIC\r\n\r\n#include <stdint.h>\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/**\r\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r\n  CMSIS violates the following MISRA-C:2004 rules:\r\n\r\n   \\li Required Rule 8.5, object/function definition in header file.<br>\r\n     Function definitions in header files are used to allow 'inlining'.\r\n\r\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r\n     Unions are used for effective representation of core registers.\r\n\r\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\r\n     Function-like macros are used to allow more efficient code.\r\n */\r\n\r\n\r\n/*******************************************************************************\r\n *                 CMSIS definitions\r\n ******************************************************************************/\r\n/**\r\n  \\ingroup Cortex_M7\r\n  @{\r\n */\r\n\r\n/*  CMSIS CM7 definitions */\r\n#define __CM7_CMSIS_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CMSIS HAL main version */\r\n#define __CM7_CMSIS_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CMSIS HAL sub version */\r\n#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \\\r\n                                    __CM7_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL version number */\r\n\r\n#define __CORTEX_M                (0x07U)                                      /*!< Cortex-M Core */\r\n\r\n\r\n#if   defined ( __CC_ARM )\r\n  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */\r\n  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */\r\n  #define __STATIC_INLINE  static __inline\r\n\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */\r\n  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */\r\n  #define __STATIC_INLINE  static __inline\r\n\r\n#elif defined ( __GNUC__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __ICCARM__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __TMS470__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __TASKING__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __CSMC__ )\r\n  #define __packed\r\n  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */\r\n  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#else\r\n  #error Unknown compiler\r\n#endif\r\n\r\n/** __FPU_USED indicates whether an FPU is used or not.\r\n    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r\n*/\r\n#if defined ( __CC_ARM )\r\n  #if defined __TARGET_FPU_VFP\r\n    #if (__FPU_PRESENT == 1U)\r\n      #define __FPU_USED       1U\r\n    #else\r\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n      #define __FPU_USED       0U\r\n    #endif\r\n  #else\r\n    #define __FPU_USED         0U\r\n  #endif\r\n\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #if defined __ARM_PCS_VFP\r\n    #if (__FPU_PRESENT == 1)\r\n      #define __FPU_USED       1U\r\n    #else\r\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n      #define __FPU_USED       0U\r\n    #endif\r\n  #else\r\n    #define __FPU_USED         0U\r\n  #endif\r\n\r\n#elif defined ( __GNUC__ )\r\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r\n    #if (__FPU_PRESENT == 1U)\r\n      #define __FPU_USED       1U\r\n    #else\r\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n      #define __FPU_USED       0U\r\n    #endif\r\n  #else\r\n    #define __FPU_USED         0U\r\n  #endif\r\n\r\n#elif defined ( __ICCARM__ )\r\n  #if defined __ARMVFP__\r\n    #if (__FPU_PRESENT == 1U)\r\n      #define __FPU_USED       1U\r\n    #else\r\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n      #define __FPU_USED       0U\r\n    #endif\r\n  #else\r\n    #define __FPU_USED         0U\r\n  #endif\r\n\r\n#elif defined ( __TMS470__ )\r\n  #if defined __TI_VFP_SUPPORT__\r\n    #if (__FPU_PRESENT == 1U)\r\n      #define __FPU_USED       1U\r\n    #else\r\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n      #define __FPU_USED       0U\r\n    #endif\r\n  #else\r\n    #define __FPU_USED         0U\r\n  #endif\r\n\r\n#elif defined ( __TASKING__ )\r\n  #if defined __FPU_VFP__\r\n    #if (__FPU_PRESENT == 1U)\r\n      #define __FPU_USED       1U\r\n    #else\r\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n      #define __FPU_USED       0U\r\n    #endif\r\n  #else\r\n    #define __FPU_USED         0U\r\n  #endif\r\n\r\n#elif defined ( __CSMC__ )\r\n  #if ( __CSMC__ & 0x400U)\r\n    #if (__FPU_PRESENT == 1U)\r\n      #define __FPU_USED       1U\r\n    #else\r\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n      #define __FPU_USED       0U\r\n    #endif\r\n  #else\r\n    #define __FPU_USED         0U\r\n  #endif\r\n\r\n#endif\r\n\r\n#include \"core_cmInstr.h\"                /* Core Instruction Access */\r\n#include \"core_cmFunc.h\"                 /* Core Function Access */\r\n#include \"core_cmSimd.h\"                 /* Compiler specific SIMD Intrinsics */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __CORE_CM7_H_GENERIC */\r\n\r\n#ifndef __CMSIS_GENERIC\r\n\r\n#ifndef __CORE_CM7_H_DEPENDANT\r\n#define __CORE_CM7_H_DEPENDANT\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* check device defines and use defaults */\r\n#if defined __CHECK_DEVICE_DEFINES\r\n  #ifndef __CM7_REV\r\n    #define __CM7_REV               0x0000U\r\n    #warning \"__CM7_REV not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __FPU_PRESENT\r\n    #define __FPU_PRESENT             0U\r\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __MPU_PRESENT\r\n    #define __MPU_PRESENT             0U\r\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __ICACHE_PRESENT\r\n    #define __ICACHE_PRESENT          0U\r\n    #warning \"__ICACHE_PRESENT not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __DCACHE_PRESENT\r\n    #define __DCACHE_PRESENT          0U\r\n    #warning \"__DCACHE_PRESENT not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __DTCM_PRESENT\r\n    #define __DTCM_PRESENT            0U\r\n    #warning \"__DTCM_PRESENT        not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __NVIC_PRIO_BITS\r\n    #define __NVIC_PRIO_BITS          3U\r\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __Vendor_SysTickConfig\r\n    #define __Vendor_SysTickConfig    0U\r\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\r\n  #endif\r\n#endif\r\n\r\n/* IO definitions (access restrictions to peripheral registers) */\r\n/**\r\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\r\n\r\n    <strong>IO Type Qualifiers</strong> are used\r\n    \\li to specify the access to peripheral variables.\r\n    \\li for automatic generation of peripheral register debug information.\r\n*/\r\n#ifdef __cplusplus\r\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\r\n#else\r\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r\n#endif\r\n#define     __O     volatile             /*!< Defines 'write only' permissions */\r\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r\n\r\n/* following defines should be used for structure members */\r\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r\n\r\n/*@} end of group Cortex_M7 */\r\n\r\n\r\n\r\n/*******************************************************************************\r\n *                 Register Abstraction\r\n  Core Register contain:\r\n  - Core Register\r\n  - Core NVIC Register\r\n  - Core SCB Register\r\n  - Core SysTick Register\r\n  - Core Debug Register\r\n  - Core MPU Register\r\n  - Core FPU Register\r\n ******************************************************************************/\r\n/**\r\n  \\defgroup CMSIS_core_register Defines and Type Definitions\r\n  \\brief Type definitions and defines for Cortex-M processor based devices.\r\n*/\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_CORE  Status and Control Registers\r\n  \\brief      Core Register type definitions.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Union type to access the Application Program Status Register (APSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\r\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\r\n    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\r\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} APSR_Type;\r\n\r\n/* APSR Register Definitions */\r\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r\n\r\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r\n\r\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r\n\r\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r\n\r\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\r\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\r\n\r\n#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\r\n#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} IPSR_Type;\r\n\r\n/* IPSR Register Definitions */\r\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r\n    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */\r\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\r\n    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\r\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\r\n    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */\r\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} xPSR_Type;\r\n\r\n/* xPSR Register Definitions */\r\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r\n\r\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r\n\r\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r\n\r\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r\n\r\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\r\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\r\n\r\n#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */\r\n#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */\r\n\r\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r\n\r\n#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\r\n#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\r\n\r\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Control Registers (CONTROL).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\r\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\r\n    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */\r\n    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} CONTROL_Type;\r\n\r\n/* CONTROL Register Definitions */\r\n#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\r\n#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\r\n\r\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r\n\r\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\r\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\r\n\r\n/*@} end of group CMSIS_CORE */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r\n  \\brief      Type definitions for the NVIC Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r\n        uint32_t RESERVED0[24U];\r\n  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r\n        uint32_t RSERVED1[24U];\r\n  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r\n        uint32_t RESERVED2[24U];\r\n  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r\n        uint32_t RESERVED3[24U];\r\n  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\r\n        uint32_t RESERVED4[56U];\r\n  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\r\n        uint32_t RESERVED5[644U];\r\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\r\n}  NVIC_Type;\r\n\r\n/* Software Triggered Interrupt Register Definitions */\r\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\r\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\r\n\r\n/*@} end of group CMSIS_NVIC */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\r\n  \\brief    Type definitions for the System Control Block Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Control Block (SCB).\r\n */\r\ntypedef struct\r\n{\r\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\r\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r\n  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\r\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\r\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\r\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\r\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\r\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\r\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\r\n  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */\r\n  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */\r\n  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\r\n  __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\r\n  __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\r\n        uint32_t RESERVED0[1U];\r\n  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */\r\n  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */\r\n  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */\r\n  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */\r\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\r\n        uint32_t RESERVED3[93U];\r\n  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */\r\n        uint32_t RESERVED4[15U];\r\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */\r\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */\r\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1 */\r\n        uint32_t RESERVED5[1U];\r\n  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */\r\n        uint32_t RESERVED6[1U];\r\n  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */\r\n  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */\r\n  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */\r\n  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */\r\n  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */\r\n  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */\r\n  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */\r\n  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */\r\n        uint32_t RESERVED7[6U];\r\n  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */\r\n  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */\r\n  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */\r\n  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */\r\n  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */\r\n        uint32_t RESERVED8[1U];\r\n  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */\r\n} SCB_Type;\r\n\r\n/* SCB CPUID Register Definitions */\r\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r\n\r\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r\n\r\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r\n\r\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r\n\r\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r\n\r\n/* SCB Interrupt Control State Register Definitions */\r\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\r\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\r\n\r\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r\n\r\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r\n\r\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r\n\r\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r\n\r\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r\n\r\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r\n\r\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r\n\r\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\r\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\r\n\r\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r\n\r\n/* SCB Vector Table Offset Register Definitions */\r\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\r\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\r\n\r\n/* SCB Application Interrupt and Reset Control Register Definitions */\r\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r\n\r\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r\n\r\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r\n\r\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\r\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\r\n\r\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r\n\r\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r\n\r\n#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\r\n#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\r\n\r\n/* SCB System Control Register Definitions */\r\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r\n\r\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r\n\r\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r\n\r\n/* SCB Configuration Control Register Definitions */\r\n#define SCB_CCR_BP_Pos                      18U                                           /*!< SCB CCR: Branch prediction enable bit Position */\r\n#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */\r\n\r\n#define SCB_CCR_IC_Pos                      17U                                           /*!< SCB CCR: Instruction cache enable bit Position */\r\n#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */\r\n\r\n#define SCB_CCR_DC_Pos                      16U                                           /*!< SCB CCR: Cache enable bit Position */\r\n#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */\r\n\r\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\r\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\r\n\r\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\r\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\r\n\r\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\r\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\r\n\r\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r\n\r\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\r\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\r\n\r\n#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\r\n#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\r\n\r\n/* SCB System Handler Control and State Register Definitions */\r\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\r\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\r\n\r\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\r\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\r\n\r\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\r\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\r\n\r\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r\n\r\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\r\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r\n\r\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\r\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r\n\r\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\r\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\r\n\r\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\r\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\r\n\r\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\r\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\r\n\r\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\r\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\r\n\r\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\r\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\r\n\r\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\r\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\r\n\r\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\r\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\r\n\r\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\r\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\r\n\r\n/* SCB Configurable Fault Status Register Definitions */\r\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\r\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\r\n\r\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\r\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\r\n\r\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r\n\r\n/* SCB Hard Fault Status Register Definitions */\r\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\r\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\r\n\r\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\r\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\r\n\r\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\r\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\r\n\r\n/* SCB Debug Fault Status Register Definitions */\r\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\r\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\r\n\r\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\r\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\r\n\r\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\r\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\r\n\r\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\r\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\r\n\r\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\r\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\r\n\r\n/* SCB Cache Level ID Register Definitions */\r\n#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */\r\n#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */\r\n\r\n#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */\r\n#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */\r\n\r\n/* SCB Cache Type Register Definitions */\r\n#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */\r\n#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */\r\n\r\n#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */\r\n#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */\r\n\r\n#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */\r\n#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */\r\n\r\n#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */\r\n#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */\r\n\r\n#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */\r\n#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */\r\n\r\n/* SCB Cache Size ID Register Definitions */\r\n#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */\r\n#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */\r\n\r\n#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */\r\n#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */\r\n\r\n#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */\r\n#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */\r\n\r\n#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */\r\n#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */\r\n\r\n#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */\r\n#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */\r\n\r\n#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */\r\n#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */\r\n\r\n#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */\r\n#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */\r\n\r\n/* SCB Cache Size Selection Register Definitions */\r\n#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */\r\n#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */\r\n\r\n#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */\r\n#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */\r\n\r\n/* SCB Software Triggered Interrupt Register Definitions */\r\n#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */\r\n#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */\r\n\r\n/* SCB D-Cache Invalidate by Set-way Register Definitions */\r\n#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */\r\n#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */\r\n\r\n#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */\r\n#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */\r\n\r\n/* SCB D-Cache Clean by Set-way Register Definitions */\r\n#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */\r\n#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */\r\n\r\n#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */\r\n#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */\r\n\r\n/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\r\n#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */\r\n#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */\r\n\r\n#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */\r\n#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */\r\n\r\n/* Instruction Tightly-Coupled Memory Control Register Definitions */\r\n#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */\r\n#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */\r\n\r\n#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */\r\n#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */\r\n\r\n#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */\r\n#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */\r\n\r\n#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */\r\n#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */\r\n\r\n/* Data Tightly-Coupled Memory Control Register Definitions */\r\n#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */\r\n#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */\r\n\r\n#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */\r\n#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */\r\n\r\n#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */\r\n#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */\r\n\r\n#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */\r\n#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */\r\n\r\n/* AHBP Control Register Definitions */\r\n#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */\r\n#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */\r\n\r\n#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */\r\n#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */\r\n\r\n/* L1 Cache Control Register Definitions */\r\n#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */\r\n#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */\r\n\r\n#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */\r\n#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */\r\n\r\n#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */\r\n#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */\r\n\r\n/* AHBS Control Register Definitions */\r\n#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */\r\n#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */\r\n\r\n#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */\r\n#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */\r\n\r\n#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/\r\n#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */\r\n\r\n/* Auxiliary Bus Fault Status Register Definitions */\r\n#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/\r\n#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */\r\n\r\n#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/\r\n#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */\r\n\r\n#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/\r\n#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */\r\n\r\n#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/\r\n#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */\r\n\r\n#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/\r\n#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */\r\n\r\n#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/\r\n#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */\r\n\r\n/*@} end of group CMSIS_SCB */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\r\n */\r\ntypedef struct\r\n{\r\n        uint32_t RESERVED0[1U];\r\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\r\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\r\n} SCnSCB_Type;\r\n\r\n/* Interrupt Controller Type Register Definitions */\r\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\r\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\r\n\r\n/* Auxiliary Control Register Definitions */\r\n#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: DISITMATBFLUSH Position */\r\n#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */\r\n\r\n#define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: DISRAMODE Position */\r\n#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */\r\n\r\n#define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: FPEXCODIS Position */\r\n#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */\r\n\r\n#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */\r\n#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */\r\n\r\n#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\r\n#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\r\n\r\n/*@} end of group CMSIS_SCnotSCB */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r\n  \\brief    Type definitions for the System Timer Registers.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Timer (SysTick).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r\n} SysTick_Type;\r\n\r\n/* SysTick Control / Status Register Definitions */\r\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r\n\r\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r\n\r\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r\n\r\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r\n\r\n/* SysTick Reload Register Definitions */\r\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r\n\r\n/* SysTick Current Register Definitions */\r\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r\n\r\n/* SysTick Calibration Register Definitions */\r\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r\n\r\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r\n\r\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r\n\r\n/*@} end of group CMSIS_SysTick */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\r\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r\n */\r\ntypedef struct\r\n{\r\n  __OM  union\r\n  {\r\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\r\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\r\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\r\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\r\n        uint32_t RESERVED0[864U];\r\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\r\n        uint32_t RESERVED1[15U];\r\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\r\n        uint32_t RESERVED2[15U];\r\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\r\n        uint32_t RESERVED3[29U];\r\n  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\r\n  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\r\n  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\r\n        uint32_t RESERVED4[43U];\r\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\r\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\r\n        uint32_t RESERVED5[6U];\r\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\r\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\r\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\r\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\r\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\r\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\r\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\r\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\r\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\r\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\r\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\r\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\r\n} ITM_Type;\r\n\r\n/* ITM Trace Privilege Register Definitions */\r\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\r\n#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */\r\n\r\n/* ITM Trace Control Register Definitions */\r\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\r\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\r\n\r\n#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\r\n#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */\r\n\r\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\r\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\r\n\r\n#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\r\n#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\r\n\r\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\r\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\r\n\r\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\r\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\r\n\r\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\r\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\r\n\r\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\r\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\r\n\r\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\r\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\r\n\r\n/* ITM Integration Write Register Definitions */\r\n#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */\r\n#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\r\n\r\n/* ITM Integration Read Register Definitions */\r\n#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */\r\n#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\r\n\r\n/* ITM Integration Mode Control Register Definitions */\r\n#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */\r\n#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\r\n\r\n/* ITM Lock Status Register Definitions */\r\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\r\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\r\n\r\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\r\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\r\n\r\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\r\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\r\n\r\n/*@}*/ /* end of group CMSIS_ITM */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\r\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\r\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\r\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\r\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\r\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\r\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\r\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\r\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\r\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\r\n  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\r\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\r\n        uint32_t RESERVED0[1U];\r\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\r\n  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\r\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\r\n        uint32_t RESERVED1[1U];\r\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\r\n  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\r\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\r\n        uint32_t RESERVED2[1U];\r\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\r\n  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\r\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\r\n        uint32_t RESERVED3[981U];\r\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */\r\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */\r\n} DWT_Type;\r\n\r\n/* DWT Control Register Definitions */\r\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\r\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\r\n\r\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\r\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\r\n\r\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\r\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\r\n\r\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\r\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\r\n\r\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\r\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\r\n\r\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\r\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\r\n\r\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\r\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\r\n\r\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\r\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\r\n\r\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\r\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\r\n\r\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\r\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\r\n\r\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\r\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\r\n\r\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\r\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\r\n\r\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\r\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\r\n\r\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\r\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\r\n\r\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\r\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\r\n\r\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\r\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\r\n\r\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\r\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\r\n\r\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\r\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\r\n\r\n/* DWT CPI Count Register Definitions */\r\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\r\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\r\n\r\n/* DWT Exception Overhead Count Register Definitions */\r\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\r\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\r\n\r\n/* DWT Sleep Count Register Definitions */\r\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\r\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r\n\r\n/* DWT LSU Count Register Definitions */\r\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\r\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\r\n\r\n/* DWT Folded-instruction Count Register Definitions */\r\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\r\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\r\n\r\n/* DWT Comparator Mask Register Definitions */\r\n#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\r\n#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\r\n\r\n/* DWT Comparator Function Register Definitions */\r\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\r\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\r\n\r\n#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\r\n#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\r\n\r\n#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\r\n#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\r\n\r\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\r\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\r\n\r\n#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\r\n#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\r\n\r\n#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\r\n#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\r\n\r\n#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\r\n#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\r\n\r\n#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\r\n#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\r\n\r\n#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\r\n#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\r\n\r\n/*@}*/ /* end of group CMSIS_DWT */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\r\n  \\brief    Type definitions for the Trace Port Interface (TPI)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\r\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\r\n        uint32_t RESERVED0[2U];\r\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\r\n        uint32_t RESERVED1[55U];\r\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\r\n        uint32_t RESERVED2[131U];\r\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\r\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\r\n  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\r\n        uint32_t RESERVED3[759U];\r\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */\r\n  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\r\n  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\r\n        uint32_t RESERVED4[1U];\r\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\r\n  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\r\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\r\n        uint32_t RESERVED5[39U];\r\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\r\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\r\n        uint32_t RESERVED7[8U];\r\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\r\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\r\n} TPI_Type;\r\n\r\n/* TPI Asynchronous Clock Prescaler Register Definitions */\r\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\r\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\r\n\r\n/* TPI Selected Pin Protocol Register Definitions */\r\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\r\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\r\n\r\n/* TPI Formatter and Flush Status Register Definitions */\r\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\r\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\r\n\r\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\r\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\r\n\r\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\r\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\r\n\r\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\r\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\r\n\r\n/* TPI Formatter and Flush Control Register Definitions */\r\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\r\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\r\n\r\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\r\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\r\n\r\n/* TPI TRIGGER Register Definitions */\r\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\r\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\r\n\r\n/* TPI Integration ETM Data Register Definitions (FIFO0) */\r\n#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\r\n#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\r\n\r\n#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\r\n#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\r\n\r\n#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\r\n#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\r\n\r\n#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\r\n#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\r\n\r\n#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\r\n#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\r\n\r\n#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\r\n#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\r\n\r\n#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\r\n#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\r\n\r\n/* TPI ITATBCTR2 Register Definitions */\r\n#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */\r\n#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */\r\n\r\n/* TPI Integration ITM Data Register Definitions (FIFO1) */\r\n#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\r\n#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\r\n\r\n#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\r\n#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\r\n\r\n#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\r\n#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\r\n\r\n#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\r\n#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\r\n\r\n#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\r\n#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\r\n\r\n#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\r\n#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\r\n\r\n#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\r\n#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\r\n\r\n/* TPI ITATBCTR0 Register Definitions */\r\n#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */\r\n#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */\r\n\r\n/* TPI Integration Mode Control Register Definitions */\r\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\r\n#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\r\n\r\n/* TPI DEVID Register Definitions */\r\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\r\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\r\n\r\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\r\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\r\n\r\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\r\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\r\n\r\n#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\r\n#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\r\n\r\n#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\r\n#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\r\n\r\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\r\n#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\r\n\r\n/* TPI DEVTYPE Register Definitions */\r\n#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */\r\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\r\n\r\n#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */\r\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\r\n\r\n/*@}*/ /* end of group CMSIS_TPI */\r\n\r\n\r\n#if (__MPU_PRESENT == 1U)\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\r\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\r\n */\r\ntypedef struct\r\n{\r\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\r\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\r\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\r\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\r\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\r\n  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\r\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\r\n  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\r\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\r\n  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\r\n} MPU_Type;\r\n\r\n/* MPU Type Register Definitions */\r\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\r\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r\n\r\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\r\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r\n\r\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\r\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\r\n\r\n/* MPU Control Register Definitions */\r\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\r\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r\n\r\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\r\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r\n\r\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\r\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\r\n\r\n/* MPU Region Number Register Definitions */\r\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\r\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\r\n\r\n/* MPU Region Base Address Register Definitions */\r\n#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\r\n#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\r\n\r\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\r\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\r\n\r\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\r\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\r\n\r\n/* MPU Region Attribute and Size Register Definitions */\r\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\r\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\r\n\r\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\r\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\r\n\r\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\r\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\r\n\r\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\r\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\r\n\r\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\r\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\r\n\r\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\r\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\r\n\r\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\r\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\r\n\r\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\r\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\r\n\r\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\r\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\r\n\r\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\r\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\r\n\r\n/*@} end of group CMSIS_MPU */\r\n#endif\r\n\r\n\r\n#if (__FPU_PRESENT == 1U)\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_FPU     Floating Point Unit (FPU)\r\n  \\brief    Type definitions for the Floating Point Unit (FPU)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Floating Point Unit (FPU).\r\n */\r\ntypedef struct\r\n{\r\n        uint32_t RESERVED0[1U];\r\n  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\r\n  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\r\n  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\r\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */\r\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */\r\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */\r\n} FPU_Type;\r\n\r\n/* Floating-Point Context Control Register Definitions */\r\n#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\r\n#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\r\n\r\n#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\r\n#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\r\n\r\n#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\r\n#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\r\n\r\n#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\r\n#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\r\n\r\n#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\r\n#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\r\n\r\n#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\r\n#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\r\n\r\n#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\r\n#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\r\n\r\n#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\r\n#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\r\n\r\n#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\r\n#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\r\n\r\n/* Floating-Point Context Address Register Definitions */\r\n#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\r\n#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\r\n\r\n/* Floating-Point Default Status Control Register Definitions */\r\n#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\r\n#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\r\n\r\n#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\r\n#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\r\n\r\n#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\r\n#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\r\n\r\n#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\r\n#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\r\n\r\n/* Media and FP Feature Register 0 Definitions */\r\n#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */\r\n#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */\r\n\r\n#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */\r\n#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */\r\n\r\n#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */\r\n#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */\r\n\r\n#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */\r\n#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */\r\n\r\n#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */\r\n#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */\r\n\r\n#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */\r\n#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */\r\n\r\n#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */\r\n#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */\r\n\r\n#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */\r\n#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */\r\n\r\n/* Media and FP Feature Register 1 Definitions */\r\n#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */\r\n#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */\r\n\r\n#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */\r\n#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */\r\n\r\n#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */\r\n#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */\r\n\r\n#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */\r\n#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */\r\n\r\n/* Media and FP Feature Register 2 Definitions */\r\n\r\n/*@} end of group CMSIS_FPU */\r\n#endif\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r\n  \\brief    Type definitions for the Core Debug Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\r\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\r\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\r\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\r\n} CoreDebug_Type;\r\n\r\n/* Debug Halting Control and Status Register Definitions */\r\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\r\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\r\n\r\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\r\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r\n\r\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r\n\r\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\r\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r\n\r\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\r\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\r\n\r\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\r\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\r\n\r\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\r\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\r\n\r\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r\n\r\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\r\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r\n\r\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\r\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\r\n\r\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\r\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\r\n\r\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r\n\r\n/* Debug Core Register Selector Register Definitions */\r\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\r\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\r\n\r\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\r\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\r\n\r\n/* Debug Exception and Monitor Control Register Definitions */\r\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\r\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\r\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\r\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\r\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\r\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\r\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\r\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\r\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\r\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\r\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\r\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\r\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r\n\r\n/*@} end of group CMSIS_CoreDebug */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\r\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief   Mask and shift a bit field value for use in a register bit range.\r\n  \\param[in] field  Name of the register bit field.\r\n  \\param[in] value  Value of the bit field.\r\n  \\return           Masked and shifted value.\r\n*/\r\n#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)\r\n\r\n/**\r\n  \\brief     Mask and shift a register value to extract a bit filed value.\r\n  \\param[in] field  Name of the register bit field.\r\n  \\param[in] value  Value of register.\r\n  \\return           Masked and shifted bit field value.\r\n*/\r\n#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)\r\n\r\n/*@} end of group CMSIS_core_bitfield */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_core_base     Core Definitions\r\n  \\brief      Definitions for base addresses, unions, and structures.\r\n  @{\r\n */\r\n\r\n/* Memory mapping of Cortex-M4 Hardware */\r\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\r\n#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\r\n#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\r\n#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\r\n#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\r\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\r\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\r\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\r\n\r\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\r\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\r\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\r\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\r\n#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\r\n#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\r\n#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\r\n#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\r\n\r\n#if (__MPU_PRESENT == 1U)\r\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\r\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\r\n#endif\r\n\r\n#if (__FPU_PRESENT == 1U)\r\n  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */\r\n  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */\r\n#endif\r\n\r\n/*@} */\r\n\r\n\r\n\r\n/*******************************************************************************\r\n *                Hardware Abstraction Layer\r\n  Core Function Interface contains:\r\n  - Core NVIC Functions\r\n  - Core SysTick Functions\r\n  - Core Debug Functions\r\n  - Core Register Access Functions\r\n ******************************************************************************/\r\n/**\r\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r\n*/\r\n\r\n\r\n\r\n/* ##########################   NVIC functions  #################################### */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\r\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief   Set Priority Grouping\r\n  \\details Sets the priority grouping field using the required unlock sequence.\r\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r\n           Only values from 0..7 are used.\r\n           In case of a conflict between priority grouping and available\r\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r\n  \\param [in]      PriorityGroup  Priority grouping field.\r\n */\r\n__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r\n{\r\n  uint32_t reg_value;\r\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\r\n\r\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\r\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\r\n  reg_value  =  (reg_value                                   |\r\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r\n                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */\r\n  SCB->AIRCR =  reg_value;\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Priority Grouping\r\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\r\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r\n{\r\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Enable External Interrupt\r\n  \\details Enables a device-specific interrupt in the NVIC interrupt controller.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Disable External Interrupt\r\n  \\details Disables a device-specific interrupt in the NVIC interrupt controller.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Pending Interrupt\r\n  \\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\return             0  Interrupt status is not pending.\r\n  \\return             1  Interrupt status is pending.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Pending Interrupt\r\n  \\details Sets the pending bit of an external interrupt.\r\n  \\param [in]      IRQn  Interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Clear Pending Interrupt\r\n  \\details Clears the pending bit of an external interrupt.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Active Interrupt\r\n  \\details Reads the active register in NVIC and returns the active bit.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\return             0  Interrupt status is not active.\r\n  \\return             1  Interrupt status is active.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r\n{\r\n  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Interrupt Priority\r\n  \\details Sets the priority of an interrupt.\r\n  \\note    The priority cannot be set for every core interrupt.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\param [in]  priority  Priority to set.\r\n */\r\n__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r\n{\r\n  if ((int32_t)(IRQn) < 0)\r\n  {\r\n    SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r\n  }\r\n  else\r\n  {\r\n    NVIC->IP[((uint32_t)(int32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Interrupt Priority\r\n  \\details Reads the priority of an interrupt.\r\n           The interrupt number can be positive to specify an external (device specific) interrupt,\r\n           or negative to specify an internal (core) interrupt.\r\n  \\param [in]   IRQn  Interrupt number.\r\n  \\return             Interrupt Priority.\r\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r\n{\r\n\r\n  if ((int32_t)(IRQn) < 0)\r\n  {\r\n    return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r\n  }\r\n  else\r\n  {\r\n    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Encode Priority\r\n  \\details Encodes the priority for an interrupt with the given priority group,\r\n           preemptive priority value, and subpriority value.\r\n           In case of a conflict between priority grouping and available\r\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r\n  \\param [in]     PriorityGroup  Used priority group.\r\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\r\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\r\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\r\n */\r\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r\n{\r\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r\n  uint32_t PreemptPriorityBits;\r\n  uint32_t SubPriorityBits;\r\n\r\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r\n\r\n  return (\r\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\r\n         );\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Decode Priority\r\n  \\details Decodes an interrupt priority value with a given priority group to\r\n           preemptive priority value and subpriority value.\r\n           In case of a conflict between priority grouping and available\r\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\r\n  \\param [in]     PriorityGroup  Used priority group.\r\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\r\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\r\n */\r\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r\n{\r\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r\n  uint32_t PreemptPriorityBits;\r\n  uint32_t SubPriorityBits;\r\n\r\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r\n\r\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   System Reset\r\n  \\details Initiates a system reset request to reset the MCU.\r\n */\r\n__STATIC_INLINE void NVIC_SystemReset(void)\r\n{\r\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\r\n                                                                       buffered write are completed before reset */\r\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\r\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\r\n  __DSB();                                                          /* Ensure completion of memory access */\r\n\r\n  for(;;)                                                           /* wait until reset */\r\n  {\r\n    __NOP();\r\n  }\r\n}\r\n\r\n/*@} end of CMSIS_Core_NVICFunctions */\r\n\r\n\r\n/* ##########################  FPU functions  #################################### */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\r\n  \\brief    Function that provides FPU type.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief   get FPU type\r\n  \\details returns the FPU type\r\n  \\returns\r\n   - \\b  0: No FPU\r\n   - \\b  1: Single precision FPU\r\n   - \\b  2: Double + Single precision FPU\r\n */\r\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r\n{\r\n  uint32_t mvfr0;\r\n\r\n  mvfr0 = SCB->MVFR0;\r\n  if        ((mvfr0 & 0x00000FF0UL) == 0x220UL)\r\n  {\r\n    return 2UL;           /* Double + Single precision FPU */\r\n  }\r\n  else if ((mvfr0 & 0x00000FF0UL) == 0x020UL)\r\n  {\r\n    return 1UL;           /* Single precision FPU */\r\n  }\r\n  else\r\n  {\r\n    return 0UL;           /* No FPU */\r\n  }\r\n}\r\n\r\n\r\n/*@} end of CMSIS_Core_FpuFunctions */\r\n\r\n\r\n\r\n/* ##########################  Cache functions  #################################### */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_CacheFunctions Cache Functions\r\n  \\brief    Functions that configure Instruction and Data cache.\r\n  @{\r\n */\r\n\r\n/* Cache Size ID Register Macros */\r\n#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)\r\n#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )\r\n\r\n\r\n/**\r\n  \\brief   Enable I-Cache\r\n  \\details Turns on I-Cache\r\n  */\r\n__STATIC_INLINE void SCB_EnableICache (void)\r\n{\r\n  #if (__ICACHE_PRESENT == 1U)\r\n    __DSB();\r\n    __ISB();\r\n    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */\r\n    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */\r\n    __DSB();\r\n    __ISB();\r\n  #endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Disable I-Cache\r\n  \\details Turns off I-Cache\r\n  */\r\n__STATIC_INLINE void SCB_DisableICache (void)\r\n{\r\n  #if (__ICACHE_PRESENT == 1U)\r\n    __DSB();\r\n    __ISB();\r\n    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */\r\n    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */\r\n    __DSB();\r\n    __ISB();\r\n  #endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Invalidate I-Cache\r\n  \\details Invalidates I-Cache\r\n  */\r\n__STATIC_INLINE void SCB_InvalidateICache (void)\r\n{\r\n  #if (__ICACHE_PRESENT == 1U)\r\n    __DSB();\r\n    __ISB();\r\n    SCB->ICIALLU = 0UL;\r\n    __DSB();\r\n    __ISB();\r\n  #endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Enable D-Cache\r\n  \\details Turns on D-Cache\r\n  */\r\n__STATIC_INLINE void SCB_EnableDCache (void)\r\n{\r\n  #if (__DCACHE_PRESENT == 1U)\r\n    uint32_t ccsidr;\r\n    uint32_t sets;\r\n    uint32_t ways;\r\n\r\n    SCB->CSSELR = (0U << 1U) | 0U;          /* Level 1 data cache */\r\n    __DSB();\r\n\r\n    ccsidr = SCB->CCSIDR;\r\n\r\n                                            /* invalidate D-Cache */\r\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r\n    do {\r\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r\n      do {\r\n        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\r\n                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );\r\n        #if defined ( __CC_ARM )\r\n          __schedule_barrier();\r\n        #endif\r\n      } while (ways--);\r\n    } while(sets--);\r\n    __DSB();\r\n\r\n    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */\r\n\r\n    __DSB();\r\n    __ISB();\r\n  #endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Disable D-Cache\r\n  \\details Turns off D-Cache\r\n  */\r\n__STATIC_INLINE void SCB_DisableDCache (void)\r\n{\r\n  #if (__DCACHE_PRESENT == 1U)\r\n    uint32_t ccsidr;\r\n    uint32_t sets;\r\n    uint32_t ways;\r\n\r\n    SCB->CSSELR = (0U << 1U) | 0U;          /* Level 1 data cache */\r\n    __DSB();\r\n\r\n    ccsidr = SCB->CCSIDR;\r\n\r\n    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */\r\n\r\n                                            /* clean & invalidate D-Cache */\r\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r\n    do {\r\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r\n      do {\r\n        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\r\n                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );\r\n        #if defined ( __CC_ARM )\r\n          __schedule_barrier();\r\n        #endif\r\n      } while (ways--);\r\n    } while(sets--);\r\n\r\n    __DSB();\r\n    __ISB();\r\n  #endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Invalidate D-Cache\r\n  \\details Invalidates D-Cache\r\n  */\r\n__STATIC_INLINE void SCB_InvalidateDCache (void)\r\n{\r\n  #if (__DCACHE_PRESENT == 1U)\r\n    uint32_t ccsidr;\r\n    uint32_t sets;\r\n    uint32_t ways;\r\n\r\n    SCB->CSSELR = (0U << 1U) | 0U;          /* Level 1 data cache */\r\n    __DSB();\r\n\r\n    ccsidr = SCB->CCSIDR;\r\n\r\n                                            /* invalidate D-Cache */\r\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r\n    do {\r\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r\n      do {\r\n        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\r\n                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );\r\n        #if defined ( __CC_ARM )\r\n          __schedule_barrier();\r\n        #endif\r\n      } while (ways--);\r\n    } while(sets--);\r\n\r\n    __DSB();\r\n    __ISB();\r\n  #endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Clean D-Cache\r\n  \\details Cleans D-Cache\r\n  */\r\n__STATIC_INLINE void SCB_CleanDCache (void)\r\n{\r\n  #if (__DCACHE_PRESENT == 1U)\r\n    uint32_t ccsidr;\r\n    uint32_t sets;\r\n    uint32_t ways;\r\n\r\n    SCB->CSSELR = (0U << 1U) | 0U;          /* Level 1 data cache */\r\n    __DSB();\r\n\r\n    ccsidr = SCB->CCSIDR;\r\n\r\n                                            /* clean D-Cache */\r\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r\n    do {\r\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r\n      do {\r\n        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |\r\n                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );\r\n        #if defined ( __CC_ARM )\r\n          __schedule_barrier();\r\n        #endif\r\n      } while (ways--);\r\n    } while(sets--);\r\n\r\n    __DSB();\r\n    __ISB();\r\n  #endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Clean & Invalidate D-Cache\r\n  \\details Cleans and Invalidates D-Cache\r\n  */\r\n__STATIC_INLINE void SCB_CleanInvalidateDCache (void)\r\n{\r\n  #if (__DCACHE_PRESENT == 1U)\r\n    uint32_t ccsidr;\r\n    uint32_t sets;\r\n    uint32_t ways;\r\n\r\n    SCB->CSSELR = (0U << 1U) | 0U;          /* Level 1 data cache */\r\n    __DSB();\r\n\r\n    ccsidr = SCB->CCSIDR;\r\n\r\n                                            /* clean & invalidate D-Cache */\r\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r\n    do {\r\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r\n      do {\r\n        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\r\n                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );\r\n        #if defined ( __CC_ARM )\r\n          __schedule_barrier();\r\n        #endif\r\n      } while (ways--);\r\n    } while(sets--);\r\n\r\n    __DSB();\r\n    __ISB();\r\n  #endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   D-Cache Invalidate by address\r\n  \\details Invalidates D-Cache for the given address\r\n  \\param[in]   addr    address (aligned to 32-byte boundary)\r\n  \\param[in]   dsize   size of memory block (in number of bytes)\r\n*/\r\n__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)\r\n{\r\n  #if (__DCACHE_PRESENT == 1U)\r\n     int32_t op_size = dsize;\r\n    uint32_t op_addr = (uint32_t)addr;\r\n     int32_t linesize = 32U;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r\n\r\n    __DSB();\r\n\r\n    while (op_size > 0) {\r\n      SCB->DCIMVAC = op_addr;\r\n      op_addr += linesize;\r\n      op_size -= linesize;\r\n    }\r\n\r\n    __DSB();\r\n    __ISB();\r\n  #endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   D-Cache Clean by address\r\n  \\details Cleans D-Cache for the given address\r\n  \\param[in]   addr    address (aligned to 32-byte boundary)\r\n  \\param[in]   dsize   size of memory block (in number of bytes)\r\n*/\r\n__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)\r\n{\r\n  #if (__DCACHE_PRESENT == 1)\r\n     int32_t op_size = dsize;\r\n    uint32_t op_addr = (uint32_t) addr;\r\n     int32_t linesize = 32U;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r\n\r\n    __DSB();\r\n\r\n    while (op_size > 0) {\r\n      SCB->DCCMVAC = op_addr;\r\n      op_addr += linesize;\r\n      op_size -= linesize;\r\n    }\r\n\r\n    __DSB();\r\n    __ISB();\r\n  #endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   D-Cache Clean and Invalidate by address\r\n  \\details Cleans and invalidates D_Cache for the given address\r\n  \\param[in]   addr    address (aligned to 32-byte boundary)\r\n  \\param[in]   dsize   size of memory block (in number of bytes)\r\n*/\r\n__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)\r\n{\r\n  #if (__DCACHE_PRESENT == 1U)\r\n     int32_t op_size = dsize;\r\n    uint32_t op_addr = (uint32_t) addr;\r\n     int32_t linesize = 32U;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r\n\r\n    __DSB();\r\n\r\n    while (op_size > 0) {\r\n      SCB->DCCIMVAC = op_addr;\r\n      op_addr += linesize;\r\n      op_size -= linesize;\r\n    }\r\n\r\n    __DSB();\r\n    __ISB();\r\n  #endif\r\n}\r\n\r\n\r\n/*@} end of CMSIS_Core_CacheFunctions */\r\n\r\n\r\n\r\n/* ##################################    SysTick function  ############################################ */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r\n  \\brief    Functions that configure the System.\r\n  @{\r\n */\r\n\r\n#if (__Vendor_SysTickConfig == 0U)\r\n\r\n/**\r\n  \\brief   System Tick Configuration\r\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r\n           Counter is in free running mode to generate periodic interrupts.\r\n  \\param [in]  ticks  Number of ticks between two interrupts.\r\n  \\return          0  Function succeeded.\r\n  \\return          1  Function failed.\r\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r\n           must contain a vendor-specific implementation of this function.\r\n */\r\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r\n{\r\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r\n  {\r\n    return (1UL);                                                   /* Reload value impossible */\r\n  }\r\n\r\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r\n                   SysTick_CTRL_TICKINT_Msk   |\r\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r\n  return (0UL);                                                     /* Function successful */\r\n}\r\n\r\n#endif\r\n\r\n/*@} end of CMSIS_Core_SysTickFunctions */\r\n\r\n\r\n\r\n/* ##################################### Debug In/Output function ########################################### */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\r\n  \\brief    Functions that access the ITM debug interface.\r\n  @{\r\n */\r\n\r\nextern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters. */\r\n#define                 ITM_RXBUFFER_EMPTY   0x5AA55AA5U /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\r\n\r\n\r\n/**\r\n  \\brief   ITM Send Character\r\n  \\details Transmits a character via the ITM channel 0, and\r\n           \\li Just returns when no debugger is connected that has booked the output.\r\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r\n  \\param [in]     ch  Character to transmit.\r\n  \\returns            Character to transmit.\r\n */\r\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r\n{\r\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\r\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\r\n  {\r\n    while (ITM->PORT[0U].u32 == 0UL)\r\n    {\r\n      __NOP();\r\n    }\r\n    ITM->PORT[0U].u8 = (uint8_t)ch;\r\n  }\r\n  return (ch);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   ITM Receive Character\r\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\r\n  \\return             Received character.\r\n  \\return         -1  No character pending.\r\n */\r\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r\n{\r\n  int32_t ch = -1;                           /* no character available */\r\n\r\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r\n  {\r\n    ch = ITM_RxBuffer;\r\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\r\n  }\r\n\r\n  return (ch);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   ITM Check Character\r\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\r\n  \\return          0  No character available.\r\n  \\return          1  Character available.\r\n */\r\n__STATIC_INLINE int32_t ITM_CheckChar (void)\r\n{\r\n\r\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r\n  {\r\n    return (0);                              /* no character available */\r\n  }\r\n  else\r\n  {\r\n    return (1);                              /*    character available */\r\n  }\r\n}\r\n\r\n/*@} end of CMSIS_core_DebugFunctions */\r\n\r\n\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __CORE_CM7_H_DEPENDANT */\r\n\r\n#endif /* __CMSIS_GENERIC */\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/bsp/opencr/include/core_cmFunc.h",
    "content": "/**************************************************************************//**\r\n * @file     core_cmFunc.h\r\n * @brief    CMSIS Cortex-M Core Function Access Header File\r\n * @version  V4.30\r\n * @date     20. October 2015\r\n ******************************************************************************/\r\n/* Copyright (c) 2009 - 2015 ARM LIMITED\r\n\r\n   All rights reserved.\r\n   Redistribution and use in source and binary forms, with or without\r\n   modification, are permitted provided that the following conditions are met:\r\n   - Redistributions of source code must retain the above copyright\r\n     notice, this list of conditions and the following disclaimer.\r\n   - Redistributions in binary form must reproduce the above copyright\r\n     notice, this list of conditions and the following disclaimer in the\r\n     documentation and/or other materials provided with the distribution.\r\n   - Neither the name of ARM nor the names of its contributors may be used\r\n     to endorse or promote products derived from this software without\r\n     specific prior written permission.\r\n   *\r\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n   POSSIBILITY OF SUCH DAMAGE.\r\n   ---------------------------------------------------------------------------*/\r\n\r\n\r\n#if   defined ( __ICCARM__ )\r\n #pragma system_include         /* treat file as system include file for MISRA check */\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #pragma clang system_header   /* treat file as system include file */\r\n#endif\r\n\r\n#ifndef __CORE_CMFUNC_H\r\n#define __CORE_CMFUNC_H\r\n\r\n\r\n/* ###########################  Core Function Access  ########################### */\r\n/** \\ingroup  CMSIS_Core_FunctionInterface\r\n    \\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r\n  @{\r\n*/\r\n\r\n/*------------------ RealView Compiler -----------------*/\r\n#if   defined ( __CC_ARM )\r\n  #include \"cmsis_armcc.h\"\r\n\r\n/*------------------ ARM Compiler V6 -------------------*/\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #include \"cmsis_armcc_V6.h\"\r\n\r\n/*------------------ GNU Compiler ----------------------*/\r\n#elif defined ( __GNUC__ )\r\n  #include \"cmsis_gcc.h\"\r\n\r\n/*------------------ ICC Compiler ----------------------*/\r\n#elif defined ( __ICCARM__ )\r\n  #include <cmsis_iar.h>\r\n\r\n/*------------------ TI CCS Compiler -------------------*/\r\n#elif defined ( __TMS470__ )\r\n  #include <cmsis_ccs.h>\r\n\r\n/*------------------ TASKING Compiler ------------------*/\r\n#elif defined ( __TASKING__ )\r\n  /*\r\n   * The CMSIS functions have been implemented as intrinsics in the compiler.\r\n   * Please use \"carm -?i\" to get an up to date list of all intrinsics,\r\n   * Including the CMSIS ones.\r\n   */\r\n\r\n/*------------------ COSMIC Compiler -------------------*/\r\n#elif defined ( __CSMC__ )\r\n  #include <cmsis_csm.h>\r\n\r\n#endif\r\n\r\n/*@} end of CMSIS_Core_RegAccFunctions */\r\n\r\n#endif /* __CORE_CMFUNC_H */\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/bsp/opencr/include/core_cmInstr.h",
    "content": "/**************************************************************************//**\r\n * @file     core_cmInstr.h\r\n * @brief    CMSIS Cortex-M Core Instruction Access Header File\r\n * @version  V4.30\r\n * @date     20. October 2015\r\n ******************************************************************************/\r\n/* Copyright (c) 2009 - 2015 ARM LIMITED\r\n\r\n   All rights reserved.\r\n   Redistribution and use in source and binary forms, with or without\r\n   modification, are permitted provided that the following conditions are met:\r\n   - Redistributions of source code must retain the above copyright\r\n     notice, this list of conditions and the following disclaimer.\r\n   - Redistributions in binary form must reproduce the above copyright\r\n     notice, this list of conditions and the following disclaimer in the\r\n     documentation and/or other materials provided with the distribution.\r\n   - Neither the name of ARM nor the names of its contributors may be used\r\n     to endorse or promote products derived from this software without\r\n     specific prior written permission.\r\n   *\r\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n   POSSIBILITY OF SUCH DAMAGE.\r\n   ---------------------------------------------------------------------------*/\r\n\r\n\r\n#if   defined ( __ICCARM__ )\r\n #pragma system_include         /* treat file as system include file for MISRA check */\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #pragma clang system_header   /* treat file as system include file */\r\n#endif\r\n\r\n#ifndef __CORE_CMINSTR_H\r\n#define __CORE_CMINSTR_H\r\n\r\n\r\n/* ##########################  Core Instruction Access  ######################### */\r\n/** \\defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r\n  Access to dedicated instructions\r\n  @{\r\n*/\r\n\r\n/*------------------ RealView Compiler -----------------*/\r\n#if   defined ( __CC_ARM )\r\n  #include \"cmsis_armcc.h\"\r\n\r\n/*------------------ ARM Compiler V6 -------------------*/\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #include \"cmsis_armcc_V6.h\"\r\n\r\n/*------------------ GNU Compiler ----------------------*/\r\n#elif defined ( __GNUC__ )\r\n  #include \"cmsis_gcc.h\"\r\n\r\n/*------------------ ICC Compiler ----------------------*/\r\n#elif defined ( __ICCARM__ )\r\n  #include <cmsis_iar.h>\r\n\r\n/*------------------ TI CCS Compiler -------------------*/\r\n#elif defined ( __TMS470__ )\r\n  #include <cmsis_ccs.h>\r\n\r\n/*------------------ TASKING Compiler ------------------*/\r\n#elif defined ( __TASKING__ )\r\n  /*\r\n   * The CMSIS functions have been implemented as intrinsics in the compiler.\r\n   * Please use \"carm -?i\" to get an up to date list of all intrinsics,\r\n   * Including the CMSIS ones.\r\n   */\r\n\r\n/*------------------ COSMIC Compiler -------------------*/\r\n#elif defined ( __CSMC__ )\r\n  #include <cmsis_csm.h>\r\n\r\n#endif\r\n\r\n/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r\n\r\n#endif /* __CORE_CMINSTR_H */\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/bsp/opencr/include/core_cmSimd.h",
    "content": "/**************************************************************************//**\r\n * @file     core_cmSimd.h\r\n * @brief    CMSIS Cortex-M SIMD Header File\r\n * @version  V4.30\r\n * @date     20. October 2015\r\n ******************************************************************************/\r\n/* Copyright (c) 2009 - 2015 ARM LIMITED\r\n\r\n   All rights reserved.\r\n   Redistribution and use in source and binary forms, with or without\r\n   modification, are permitted provided that the following conditions are met:\r\n   - Redistributions of source code must retain the above copyright\r\n     notice, this list of conditions and the following disclaimer.\r\n   - Redistributions in binary form must reproduce the above copyright\r\n     notice, this list of conditions and the following disclaimer in the\r\n     documentation and/or other materials provided with the distribution.\r\n   - Neither the name of ARM nor the names of its contributors may be used\r\n     to endorse or promote products derived from this software without\r\n     specific prior written permission.\r\n   *\r\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n   POSSIBILITY OF SUCH DAMAGE.\r\n   ---------------------------------------------------------------------------*/\r\n\r\n\r\n#if   defined ( __ICCARM__ )\r\n #pragma system_include         /* treat file as system include file for MISRA check */\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #pragma clang system_header   /* treat file as system include file */\r\n#endif\r\n\r\n#ifndef __CORE_CMSIMD_H\r\n#define __CORE_CMSIMD_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n\r\n/* ###################  Compiler specific Intrinsics  ########################### */\r\n/** \\defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r\n  Access to dedicated SIMD instructions\r\n  @{\r\n*/\r\n\r\n/*------------------ RealView Compiler -----------------*/\r\n#if   defined ( __CC_ARM )\r\n  #include \"cmsis_armcc.h\"\r\n\r\n/*------------------ ARM Compiler V6 -------------------*/\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #include \"cmsis_armcc_V6.h\"\r\n\r\n/*------------------ GNU Compiler ----------------------*/\r\n#elif defined ( __GNUC__ )\r\n  #include \"cmsis_gcc.h\"\r\n\r\n/*------------------ ICC Compiler ----------------------*/\r\n#elif defined ( __ICCARM__ )\r\n  #include <cmsis_iar.h>\r\n\r\n/*------------------ TI CCS Compiler -------------------*/\r\n#elif defined ( __TMS470__ )\r\n  #include <cmsis_ccs.h>\r\n\r\n/*------------------ TASKING Compiler ------------------*/\r\n#elif defined ( __TASKING__ )\r\n  /*\r\n   * The CMSIS functions have been implemented as intrinsics in the compiler.\r\n   * Please use \"carm -?i\" to get an up to date list of all intrinsics,\r\n   * Including the CMSIS ones.\r\n   */\r\n\r\n/*------------------ COSMIC Compiler -------------------*/\r\n#elif defined ( __CSMC__ )\r\n  #include <cmsis_csm.h>\r\n\r\n#endif\r\n\r\n/*@} end of group CMSIS_SIMD_intrinsics */\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __CORE_CMSIMD_H */\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/bsp/opencr/include/core_sc000.h",
    "content": "/**************************************************************************//**\r\n * @file     core_sc000.h\r\n * @brief    CMSIS SC000 Core Peripheral Access Layer Header File\r\n * @version  V4.30\r\n * @date     20. October 2015\r\n ******************************************************************************/\r\n/* Copyright (c) 2009 - 2015 ARM LIMITED\r\n\r\n   All rights reserved.\r\n   Redistribution and use in source and binary forms, with or without\r\n   modification, are permitted provided that the following conditions are met:\r\n   - Redistributions of source code must retain the above copyright\r\n     notice, this list of conditions and the following disclaimer.\r\n   - Redistributions in binary form must reproduce the above copyright\r\n     notice, this list of conditions and the following disclaimer in the\r\n     documentation and/or other materials provided with the distribution.\r\n   - Neither the name of ARM nor the names of its contributors may be used\r\n     to endorse or promote products derived from this software without\r\n     specific prior written permission.\r\n   *\r\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n   POSSIBILITY OF SUCH DAMAGE.\r\n   ---------------------------------------------------------------------------*/\r\n\r\n\r\n#if   defined ( __ICCARM__ )\r\n #pragma system_include         /* treat file as system include file for MISRA check */\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #pragma clang system_header   /* treat file as system include file */\r\n#endif\r\n\r\n#ifndef __CORE_SC000_H_GENERIC\r\n#define __CORE_SC000_H_GENERIC\r\n\r\n#include <stdint.h>\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/**\r\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r\n  CMSIS violates the following MISRA-C:2004 rules:\r\n\r\n   \\li Required Rule 8.5, object/function definition in header file.<br>\r\n     Function definitions in header files are used to allow 'inlining'.\r\n\r\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r\n     Unions are used for effective representation of core registers.\r\n\r\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\r\n     Function-like macros are used to allow more efficient code.\r\n */\r\n\r\n\r\n/*******************************************************************************\r\n *                 CMSIS definitions\r\n ******************************************************************************/\r\n/**\r\n  \\ingroup SC000\r\n  @{\r\n */\r\n\r\n/*  CMSIS SC000 definitions */\r\n#define __SC000_CMSIS_VERSION_MAIN  (0x04U)                                    /*!< [31:16] CMSIS HAL main version */\r\n#define __SC000_CMSIS_VERSION_SUB   (0x1EU)                                    /*!< [15:0]  CMSIS HAL sub version */\r\n#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \\\r\n                                      __SC000_CMSIS_VERSION_SUB           )    /*!< CMSIS HAL version number */\r\n\r\n#define __CORTEX_SC                 (000U)                                     /*!< Cortex secure core */\r\n\r\n\r\n#if   defined ( __CC_ARM )\r\n  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */\r\n  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */\r\n  #define __STATIC_INLINE  static __inline\r\n\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */\r\n  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */\r\n  #define __STATIC_INLINE  static __inline\r\n\r\n#elif defined ( __GNUC__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __ICCARM__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __TMS470__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __TASKING__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __CSMC__ )\r\n  #define __packed\r\n  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */\r\n  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#else\r\n  #error Unknown compiler\r\n#endif\r\n\r\n/** __FPU_USED indicates whether an FPU is used or not.\r\n    This core does not support an FPU at all\r\n*/\r\n#define __FPU_USED       0U\r\n\r\n#if defined ( __CC_ARM )\r\n  #if defined __TARGET_FPU_VFP\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #if defined __ARM_PCS_VFP\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __GNUC__ )\r\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __ICCARM__ )\r\n  #if defined __ARMVFP__\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __TMS470__ )\r\n  #if defined __TI_VFP_SUPPORT__\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __TASKING__ )\r\n  #if defined __FPU_VFP__\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __CSMC__ )\r\n  #if ( __CSMC__ & 0x400U)\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#endif\r\n\r\n#include \"core_cmInstr.h\"                /* Core Instruction Access */\r\n#include \"core_cmFunc.h\"                 /* Core Function Access */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __CORE_SC000_H_GENERIC */\r\n\r\n#ifndef __CMSIS_GENERIC\r\n\r\n#ifndef __CORE_SC000_H_DEPENDANT\r\n#define __CORE_SC000_H_DEPENDANT\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* check device defines and use defaults */\r\n#if defined __CHECK_DEVICE_DEFINES\r\n  #ifndef __SC000_REV\r\n    #define __SC000_REV             0x0000U\r\n    #warning \"__SC000_REV not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __MPU_PRESENT\r\n    #define __MPU_PRESENT             0U\r\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __NVIC_PRIO_BITS\r\n    #define __NVIC_PRIO_BITS          2U\r\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __Vendor_SysTickConfig\r\n    #define __Vendor_SysTickConfig    0U\r\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\r\n  #endif\r\n#endif\r\n\r\n/* IO definitions (access restrictions to peripheral registers) */\r\n/**\r\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\r\n\r\n    <strong>IO Type Qualifiers</strong> are used\r\n    \\li to specify the access to peripheral variables.\r\n    \\li for automatic generation of peripheral register debug information.\r\n*/\r\n#ifdef __cplusplus\r\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\r\n#else\r\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r\n#endif\r\n#define     __O     volatile             /*!< Defines 'write only' permissions */\r\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r\n\r\n/* following defines should be used for structure members */\r\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r\n\r\n/*@} end of group SC000 */\r\n\r\n\r\n\r\n/*******************************************************************************\r\n *                 Register Abstraction\r\n  Core Register contain:\r\n  - Core Register\r\n  - Core NVIC Register\r\n  - Core SCB Register\r\n  - Core SysTick Register\r\n  - Core MPU Register\r\n ******************************************************************************/\r\n/**\r\n  \\defgroup CMSIS_core_register Defines and Type Definitions\r\n  \\brief Type definitions and defines for Cortex-M processor based devices.\r\n*/\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_CORE  Status and Control Registers\r\n  \\brief      Core Register type definitions.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Union type to access the Application Program Status Register (APSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\r\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} APSR_Type;\r\n\r\n/* APSR Register Definitions */\r\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r\n\r\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r\n\r\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r\n\r\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} IPSR_Type;\r\n\r\n/* IPSR Register Definitions */\r\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\r\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\r\n    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\r\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} xPSR_Type;\r\n\r\n/* xPSR Register Definitions */\r\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r\n\r\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r\n\r\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r\n\r\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r\n\r\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r\n\r\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Control Registers (CONTROL).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */\r\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\r\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} CONTROL_Type;\r\n\r\n/* CONTROL Register Definitions */\r\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r\n\r\n/*@} end of group CMSIS_CORE */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r\n  \\brief      Type definitions for the NVIC Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r\n        uint32_t RESERVED0[31U];\r\n  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r\n        uint32_t RSERVED1[31U];\r\n  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r\n        uint32_t RESERVED2[31U];\r\n  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r\n        uint32_t RESERVED3[31U];\r\n        uint32_t RESERVED4[64U];\r\n  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\r\n}  NVIC_Type;\r\n\r\n/*@} end of group CMSIS_NVIC */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\r\n  \\brief    Type definitions for the System Control Block Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Control Block (SCB).\r\n */\r\ntypedef struct\r\n{\r\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\r\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r\n        uint32_t RESERVED0[1U];\r\n  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\r\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r\n        uint32_t RESERVED1[154U];\r\n  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */\r\n} SCB_Type;\r\n\r\n/* SCB CPUID Register Definitions */\r\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r\n\r\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r\n\r\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r\n\r\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r\n\r\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r\n\r\n/* SCB Interrupt Control State Register Definitions */\r\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\r\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\r\n\r\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r\n\r\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r\n\r\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r\n\r\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r\n\r\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r\n\r\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r\n\r\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r\n\r\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r\n\r\n/* SCB Interrupt Control State Register Definitions */\r\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\r\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\r\n\r\n/* SCB Application Interrupt and Reset Control Register Definitions */\r\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r\n\r\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r\n\r\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r\n\r\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r\n\r\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r\n\r\n/* SCB System Control Register Definitions */\r\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r\n\r\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r\n\r\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r\n\r\n/* SCB Configuration Control Register Definitions */\r\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\r\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\r\n\r\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r\n\r\n/* SCB System Handler Control and State Register Definitions */\r\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r\n\r\n/*@} end of group CMSIS_SCB */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\r\n */\r\ntypedef struct\r\n{\r\n        uint32_t RESERVED0[2U];\r\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\r\n} SCnSCB_Type;\r\n\r\n/* Auxiliary Control Register Definitions */\r\n#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\r\n#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\r\n\r\n/*@} end of group CMSIS_SCnotSCB */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r\n  \\brief    Type definitions for the System Timer Registers.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Timer (SysTick).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r\n} SysTick_Type;\r\n\r\n/* SysTick Control / Status Register Definitions */\r\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r\n\r\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r\n\r\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r\n\r\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r\n\r\n/* SysTick Reload Register Definitions */\r\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r\n\r\n/* SysTick Current Register Definitions */\r\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r\n\r\n/* SysTick Calibration Register Definitions */\r\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r\n\r\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r\n\r\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r\n\r\n/*@} end of group CMSIS_SysTick */\r\n\r\n#if (__MPU_PRESENT == 1U)\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\r\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\r\n */\r\ntypedef struct\r\n{\r\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\r\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\r\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\r\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\r\n} MPU_Type;\r\n\r\n/* MPU Type Register Definitions */\r\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\r\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r\n\r\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\r\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r\n\r\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\r\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\r\n\r\n/* MPU Control Register Definitions */\r\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\r\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r\n\r\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\r\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r\n\r\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\r\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\r\n\r\n/* MPU Region Number Register Definitions */\r\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\r\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\r\n\r\n/* MPU Region Base Address Register Definitions */\r\n#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */\r\n#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */\r\n\r\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\r\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\r\n\r\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\r\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\r\n\r\n/* MPU Region Attribute and Size Register Definitions */\r\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\r\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\r\n\r\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\r\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\r\n\r\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\r\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\r\n\r\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\r\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\r\n\r\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\r\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\r\n\r\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\r\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\r\n\r\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\r\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\r\n\r\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\r\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\r\n\r\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\r\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\r\n\r\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\r\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\r\n\r\n/*@} end of group CMSIS_MPU */\r\n#endif\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r\n  \\brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\r\n            Therefore they are not covered by the SC000 header file.\r\n  @{\r\n */\r\n/*@} end of group CMSIS_CoreDebug */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\r\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief   Mask and shift a bit field value for use in a register bit range.\r\n  \\param[in] field  Name of the register bit field.\r\n  \\param[in] value  Value of the bit field.\r\n  \\return           Masked and shifted value.\r\n*/\r\n#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)\r\n\r\n/**\r\n  \\brief     Mask and shift a register value to extract a bit filed value.\r\n  \\param[in] field  Name of the register bit field.\r\n  \\param[in] value  Value of register.\r\n  \\return           Masked and shifted bit field value.\r\n*/\r\n#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)\r\n\r\n/*@} end of group CMSIS_core_bitfield */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_core_base     Core Definitions\r\n  \\brief      Definitions for base addresses, unions, and structures.\r\n  @{\r\n */\r\n\r\n/* Memory mapping of SC000 Hardware */\r\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\r\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\r\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\r\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\r\n\r\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\r\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\r\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\r\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\r\n\r\n#if (__MPU_PRESENT == 1U)\r\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\r\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\r\n#endif\r\n\r\n/*@} */\r\n\r\n\r\n\r\n/*******************************************************************************\r\n *                Hardware Abstraction Layer\r\n  Core Function Interface contains:\r\n  - Core NVIC Functions\r\n  - Core SysTick Functions\r\n  - Core Register Access Functions\r\n ******************************************************************************/\r\n/**\r\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r\n*/\r\n\r\n\r\n\r\n/* ##########################   NVIC functions  #################################### */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\r\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\r\n  @{\r\n */\r\n\r\n/* Interrupt Priorities are WORD accessible only under ARMv6M                   */\r\n/* The following MACROS handle generation of the register offset and byte masks */\r\n#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\r\n#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\r\n#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\r\n\r\n\r\n/**\r\n  \\brief   Enable External Interrupt\r\n  \\details Enables a device-specific interrupt in the NVIC interrupt controller.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Disable External Interrupt\r\n  \\details Disables a device-specific interrupt in the NVIC interrupt controller.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Pending Interrupt\r\n  \\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\return             0  Interrupt status is not pending.\r\n  \\return             1  Interrupt status is pending.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Pending Interrupt\r\n  \\details Sets the pending bit of an external interrupt.\r\n  \\param [in]      IRQn  Interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Clear Pending Interrupt\r\n  \\details Clears the pending bit of an external interrupt.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Interrupt Priority\r\n  \\details Sets the priority of an interrupt.\r\n  \\note    The priority cannot be set for every core interrupt.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\param [in]  priority  Priority to set.\r\n */\r\n__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r\n{\r\n  if ((int32_t)(IRQn) < 0)\r\n  {\r\n    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r\n  }\r\n  else\r\n  {\r\n    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Interrupt Priority\r\n  \\details Reads the priority of an interrupt.\r\n           The interrupt number can be positive to specify an external (device specific) interrupt,\r\n           or negative to specify an internal (core) interrupt.\r\n  \\param [in]   IRQn  Interrupt number.\r\n  \\return             Interrupt Priority.\r\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r\n{\r\n\r\n  if ((int32_t)(IRQn) < 0)\r\n  {\r\n    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r\n  }\r\n  else\r\n  {\r\n    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   System Reset\r\n  \\details Initiates a system reset request to reset the MCU.\r\n */\r\n__STATIC_INLINE void NVIC_SystemReset(void)\r\n{\r\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\r\n                                                                       buffered write are completed before reset */\r\n  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r\n                 SCB_AIRCR_SYSRESETREQ_Msk);\r\n  __DSB();                                                          /* Ensure completion of memory access */\r\n\r\n  for(;;)                                                           /* wait until reset */\r\n  {\r\n    __NOP();\r\n  }\r\n}\r\n\r\n/*@} end of CMSIS_Core_NVICFunctions */\r\n\r\n\r\n\r\n/* ##################################    SysTick function  ############################################ */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r\n  \\brief    Functions that configure the System.\r\n  @{\r\n */\r\n\r\n#if (__Vendor_SysTickConfig == 0U)\r\n\r\n/**\r\n  \\brief   System Tick Configuration\r\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r\n           Counter is in free running mode to generate periodic interrupts.\r\n  \\param [in]  ticks  Number of ticks between two interrupts.\r\n  \\return          0  Function succeeded.\r\n  \\return          1  Function failed.\r\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r\n           must contain a vendor-specific implementation of this function.\r\n */\r\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r\n{\r\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r\n  {\r\n    return (1UL);                                                   /* Reload value impossible */\r\n  }\r\n\r\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r\n                   SysTick_CTRL_TICKINT_Msk   |\r\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r\n  return (0UL);                                                     /* Function successful */\r\n}\r\n\r\n#endif\r\n\r\n/*@} end of CMSIS_Core_SysTickFunctions */\r\n\r\n\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __CORE_SC000_H_DEPENDANT */\r\n\r\n#endif /* __CMSIS_GENERIC */\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/bsp/opencr/include/core_sc300.h",
    "content": "/**************************************************************************//**\r\n * @file     core_sc300.h\r\n * @brief    CMSIS SC300 Core Peripheral Access Layer Header File\r\n * @version  V4.30\r\n * @date     20. October 2015\r\n ******************************************************************************/\r\n/* Copyright (c) 2009 - 2015 ARM LIMITED\r\n\r\n   All rights reserved.\r\n   Redistribution and use in source and binary forms, with or without\r\n   modification, are permitted provided that the following conditions are met:\r\n   - Redistributions of source code must retain the above copyright\r\n     notice, this list of conditions and the following disclaimer.\r\n   - Redistributions in binary form must reproduce the above copyright\r\n     notice, this list of conditions and the following disclaimer in the\r\n     documentation and/or other materials provided with the distribution.\r\n   - Neither the name of ARM nor the names of its contributors may be used\r\n     to endorse or promote products derived from this software without\r\n     specific prior written permission.\r\n   *\r\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n   POSSIBILITY OF SUCH DAMAGE.\r\n   ---------------------------------------------------------------------------*/\r\n\r\n\r\n#if   defined ( __ICCARM__ )\r\n #pragma system_include         /* treat file as system include file for MISRA check */\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #pragma clang system_header   /* treat file as system include file */\r\n#endif\r\n\r\n#ifndef __CORE_SC300_H_GENERIC\r\n#define __CORE_SC300_H_GENERIC\r\n\r\n#include <stdint.h>\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/**\r\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r\n  CMSIS violates the following MISRA-C:2004 rules:\r\n\r\n   \\li Required Rule 8.5, object/function definition in header file.<br>\r\n     Function definitions in header files are used to allow 'inlining'.\r\n\r\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r\n     Unions are used for effective representation of core registers.\r\n\r\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\r\n     Function-like macros are used to allow more efficient code.\r\n */\r\n\r\n\r\n/*******************************************************************************\r\n *                 CMSIS definitions\r\n ******************************************************************************/\r\n/**\r\n  \\ingroup SC3000\r\n  @{\r\n */\r\n\r\n/*  CMSIS SC300 definitions */\r\n#define __SC300_CMSIS_VERSION_MAIN  (0x04U)                                    /*!< [31:16] CMSIS HAL main version */\r\n#define __SC300_CMSIS_VERSION_SUB   (0x1EU)                                    /*!< [15:0]  CMSIS HAL sub version */\r\n#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16U) | \\\r\n                                      __SC300_CMSIS_VERSION_SUB           )    /*!< CMSIS HAL version number */\r\n\r\n#define __CORTEX_SC                 (300U)                                     /*!< Cortex secure core */\r\n\r\n\r\n#if   defined ( __CC_ARM )\r\n  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */\r\n  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */\r\n  #define __STATIC_INLINE  static __inline\r\n\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */\r\n  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */\r\n  #define __STATIC_INLINE  static __inline\r\n\r\n#elif defined ( __GNUC__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __ICCARM__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __TMS470__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __TASKING__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __CSMC__ )\r\n  #define __packed\r\n  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */\r\n  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#else\r\n  #error Unknown compiler\r\n#endif\r\n\r\n/** __FPU_USED indicates whether an FPU is used or not.\r\n    This core does not support an FPU at all\r\n*/\r\n#define __FPU_USED       0U\r\n\r\n#if defined ( __CC_ARM )\r\n  #if defined __TARGET_FPU_VFP\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #if defined __ARM_PCS_VFP\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __GNUC__ )\r\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __ICCARM__ )\r\n  #if defined __ARMVFP__\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __TMS470__ )\r\n  #if defined __TI_VFP_SUPPORT__\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __TASKING__ )\r\n  #if defined __FPU_VFP__\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __CSMC__ )\r\n  #if ( __CSMC__ & 0x400U)\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#endif\r\n\r\n#include \"core_cmInstr.h\"                /* Core Instruction Access */\r\n#include \"core_cmFunc.h\"                 /* Core Function Access */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __CORE_SC300_H_GENERIC */\r\n\r\n#ifndef __CMSIS_GENERIC\r\n\r\n#ifndef __CORE_SC300_H_DEPENDANT\r\n#define __CORE_SC300_H_DEPENDANT\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* check device defines and use defaults */\r\n#if defined __CHECK_DEVICE_DEFINES\r\n  #ifndef __SC300_REV\r\n    #define __SC300_REV               0x0000U\r\n    #warning \"__SC300_REV not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __MPU_PRESENT\r\n    #define __MPU_PRESENT             0U\r\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __NVIC_PRIO_BITS\r\n    #define __NVIC_PRIO_BITS          4U\r\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __Vendor_SysTickConfig\r\n    #define __Vendor_SysTickConfig    0U\r\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\r\n  #endif\r\n#endif\r\n\r\n/* IO definitions (access restrictions to peripheral registers) */\r\n/**\r\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\r\n\r\n    <strong>IO Type Qualifiers</strong> are used\r\n    \\li to specify the access to peripheral variables.\r\n    \\li for automatic generation of peripheral register debug information.\r\n*/\r\n#ifdef __cplusplus\r\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\r\n#else\r\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r\n#endif\r\n#define     __O     volatile             /*!< Defines 'write only' permissions */\r\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r\n\r\n/* following defines should be used for structure members */\r\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r\n\r\n/*@} end of group SC300 */\r\n\r\n\r\n\r\n/*******************************************************************************\r\n *                 Register Abstraction\r\n  Core Register contain:\r\n  - Core Register\r\n  - Core NVIC Register\r\n  - Core SCB Register\r\n  - Core SysTick Register\r\n  - Core Debug Register\r\n  - Core MPU Register\r\n ******************************************************************************/\r\n/**\r\n  \\defgroup CMSIS_core_register Defines and Type Definitions\r\n  \\brief Type definitions and defines for Cortex-M processor based devices.\r\n*/\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_CORE  Status and Control Registers\r\n  \\brief      Core Register type definitions.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Union type to access the Application Program Status Register (APSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */\r\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} APSR_Type;\r\n\r\n/* APSR Register Definitions */\r\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r\n\r\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r\n\r\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r\n\r\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r\n\r\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\r\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} IPSR_Type;\r\n\r\n/* IPSR Register Definitions */\r\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\r\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\r\n    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */\r\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} xPSR_Type;\r\n\r\n/* xPSR Register Definitions */\r\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r\n\r\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r\n\r\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r\n\r\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r\n\r\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\r\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\r\n\r\n#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */\r\n#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */\r\n\r\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r\n\r\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Control Registers (CONTROL).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\r\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\r\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} CONTROL_Type;\r\n\r\n/* CONTROL Register Definitions */\r\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r\n\r\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\r\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\r\n\r\n/*@} end of group CMSIS_CORE */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r\n  \\brief      Type definitions for the NVIC Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r\n        uint32_t RESERVED0[24U];\r\n  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r\n        uint32_t RSERVED1[24U];\r\n  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r\n        uint32_t RESERVED2[24U];\r\n  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r\n        uint32_t RESERVED3[24U];\r\n  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\r\n        uint32_t RESERVED4[56U];\r\n  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\r\n        uint32_t RESERVED5[644U];\r\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\r\n}  NVIC_Type;\r\n\r\n/* Software Triggered Interrupt Register Definitions */\r\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\r\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\r\n\r\n/*@} end of group CMSIS_NVIC */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\r\n  \\brief    Type definitions for the System Control Block Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Control Block (SCB).\r\n */\r\ntypedef struct\r\n{\r\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\r\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r\n  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\r\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\r\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\r\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\r\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\r\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\r\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\r\n  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */\r\n  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */\r\n  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\r\n  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\r\n  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\r\n        uint32_t RESERVED0[5U];\r\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\r\n        uint32_t RESERVED1[129U];\r\n  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */\r\n} SCB_Type;\r\n\r\n/* SCB CPUID Register Definitions */\r\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r\n\r\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r\n\r\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r\n\r\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r\n\r\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r\n\r\n/* SCB Interrupt Control State Register Definitions */\r\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\r\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\r\n\r\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r\n\r\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r\n\r\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r\n\r\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r\n\r\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r\n\r\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r\n\r\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r\n\r\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\r\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\r\n\r\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r\n\r\n/* SCB Vector Table Offset Register Definitions */\r\n#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */\r\n#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */\r\n\r\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\r\n#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */\r\n\r\n/* SCB Application Interrupt and Reset Control Register Definitions */\r\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r\n\r\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r\n\r\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r\n\r\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\r\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\r\n\r\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r\n\r\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r\n\r\n#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\r\n#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\r\n\r\n/* SCB System Control Register Definitions */\r\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r\n\r\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r\n\r\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r\n\r\n/* SCB Configuration Control Register Definitions */\r\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\r\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\r\n\r\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\r\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\r\n\r\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\r\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\r\n\r\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r\n\r\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\r\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\r\n\r\n#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\r\n#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\r\n\r\n/* SCB System Handler Control and State Register Definitions */\r\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\r\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\r\n\r\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\r\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\r\n\r\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\r\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\r\n\r\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r\n\r\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\r\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r\n\r\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\r\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r\n\r\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\r\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\r\n\r\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\r\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\r\n\r\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\r\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\r\n\r\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\r\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\r\n\r\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\r\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\r\n\r\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\r\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\r\n\r\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\r\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\r\n\r\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\r\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\r\n\r\n/* SCB Configurable Fault Status Register Definitions */\r\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\r\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\r\n\r\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\r\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\r\n\r\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r\n\r\n/* SCB Hard Fault Status Register Definitions */\r\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\r\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\r\n\r\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\r\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\r\n\r\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\r\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\r\n\r\n/* SCB Debug Fault Status Register Definitions */\r\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\r\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\r\n\r\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\r\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\r\n\r\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\r\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\r\n\r\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\r\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\r\n\r\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\r\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\r\n\r\n/*@} end of group CMSIS_SCB */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\r\n */\r\ntypedef struct\r\n{\r\n        uint32_t RESERVED0[1U];\r\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\r\n        uint32_t RESERVED1[1U];\r\n} SCnSCB_Type;\r\n\r\n/* Interrupt Controller Type Register Definitions */\r\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\r\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\r\n\r\n/*@} end of group CMSIS_SCnotSCB */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r\n  \\brief    Type definitions for the System Timer Registers.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Timer (SysTick).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r\n} SysTick_Type;\r\n\r\n/* SysTick Control / Status Register Definitions */\r\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r\n\r\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r\n\r\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r\n\r\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r\n\r\n/* SysTick Reload Register Definitions */\r\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r\n\r\n/* SysTick Current Register Definitions */\r\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r\n\r\n/* SysTick Calibration Register Definitions */\r\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r\n\r\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r\n\r\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r\n\r\n/*@} end of group CMSIS_SysTick */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\r\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r\n */\r\ntypedef struct\r\n{\r\n  __OM  union\r\n  {\r\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\r\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\r\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\r\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\r\n        uint32_t RESERVED0[864U];\r\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\r\n        uint32_t RESERVED1[15U];\r\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\r\n        uint32_t RESERVED2[15U];\r\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\r\n        uint32_t RESERVED3[29U];\r\n  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\r\n  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\r\n  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\r\n        uint32_t RESERVED4[43U];\r\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\r\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\r\n        uint32_t RESERVED5[6U];\r\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\r\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\r\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\r\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\r\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\r\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\r\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\r\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\r\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\r\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\r\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\r\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\r\n} ITM_Type;\r\n\r\n/* ITM Trace Privilege Register Definitions */\r\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\r\n#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */\r\n\r\n/* ITM Trace Control Register Definitions */\r\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\r\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\r\n\r\n#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\r\n#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */\r\n\r\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\r\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\r\n\r\n#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\r\n#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\r\n\r\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\r\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\r\n\r\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\r\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\r\n\r\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\r\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\r\n\r\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\r\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\r\n\r\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\r\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\r\n\r\n/* ITM Integration Write Register Definitions */\r\n#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */\r\n#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\r\n\r\n/* ITM Integration Read Register Definitions */\r\n#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */\r\n#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\r\n\r\n/* ITM Integration Mode Control Register Definitions */\r\n#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */\r\n#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\r\n\r\n/* ITM Lock Status Register Definitions */\r\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\r\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\r\n\r\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\r\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\r\n\r\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\r\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\r\n\r\n/*@}*/ /* end of group CMSIS_ITM */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\r\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\r\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\r\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\r\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\r\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\r\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\r\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\r\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\r\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\r\n  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\r\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\r\n        uint32_t RESERVED0[1U];\r\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\r\n  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\r\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\r\n        uint32_t RESERVED1[1U];\r\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\r\n  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\r\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\r\n        uint32_t RESERVED2[1U];\r\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\r\n  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\r\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\r\n} DWT_Type;\r\n\r\n/* DWT Control Register Definitions */\r\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\r\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\r\n\r\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\r\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\r\n\r\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\r\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\r\n\r\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\r\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\r\n\r\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\r\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\r\n\r\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\r\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\r\n\r\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\r\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\r\n\r\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\r\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\r\n\r\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\r\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\r\n\r\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\r\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\r\n\r\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\r\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\r\n\r\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\r\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\r\n\r\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\r\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\r\n\r\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\r\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\r\n\r\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\r\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\r\n\r\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\r\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\r\n\r\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\r\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\r\n\r\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\r\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\r\n\r\n/* DWT CPI Count Register Definitions */\r\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\r\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\r\n\r\n/* DWT Exception Overhead Count Register Definitions */\r\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\r\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\r\n\r\n/* DWT Sleep Count Register Definitions */\r\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\r\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r\n\r\n/* DWT LSU Count Register Definitions */\r\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\r\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\r\n\r\n/* DWT Folded-instruction Count Register Definitions */\r\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\r\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\r\n\r\n/* DWT Comparator Mask Register Definitions */\r\n#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\r\n#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\r\n\r\n/* DWT Comparator Function Register Definitions */\r\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\r\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\r\n\r\n#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\r\n#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\r\n\r\n#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\r\n#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\r\n\r\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\r\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\r\n\r\n#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\r\n#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\r\n\r\n#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\r\n#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\r\n\r\n#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\r\n#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\r\n\r\n#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\r\n#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\r\n\r\n#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\r\n#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\r\n\r\n/*@}*/ /* end of group CMSIS_DWT */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\r\n  \\brief    Type definitions for the Trace Port Interface (TPI)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\r\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\r\n        uint32_t RESERVED0[2U];\r\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\r\n        uint32_t RESERVED1[55U];\r\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\r\n        uint32_t RESERVED2[131U];\r\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\r\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\r\n  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\r\n        uint32_t RESERVED3[759U];\r\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */\r\n  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\r\n  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\r\n        uint32_t RESERVED4[1U];\r\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\r\n  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\r\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\r\n        uint32_t RESERVED5[39U];\r\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\r\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\r\n        uint32_t RESERVED7[8U];\r\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\r\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\r\n} TPI_Type;\r\n\r\n/* TPI Asynchronous Clock Prescaler Register Definitions */\r\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\r\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\r\n\r\n/* TPI Selected Pin Protocol Register Definitions */\r\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\r\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\r\n\r\n/* TPI Formatter and Flush Status Register Definitions */\r\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\r\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\r\n\r\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\r\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\r\n\r\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\r\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\r\n\r\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\r\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\r\n\r\n/* TPI Formatter and Flush Control Register Definitions */\r\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\r\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\r\n\r\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\r\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\r\n\r\n/* TPI TRIGGER Register Definitions */\r\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\r\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\r\n\r\n/* TPI Integration ETM Data Register Definitions (FIFO0) */\r\n#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\r\n#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\r\n\r\n#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\r\n#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\r\n\r\n#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\r\n#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\r\n\r\n#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\r\n#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\r\n\r\n#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\r\n#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\r\n\r\n#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\r\n#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\r\n\r\n#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\r\n#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\r\n\r\n/* TPI ITATBCTR2 Register Definitions */\r\n#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */\r\n#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */\r\n\r\n/* TPI Integration ITM Data Register Definitions (FIFO1) */\r\n#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\r\n#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\r\n\r\n#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\r\n#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\r\n\r\n#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\r\n#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\r\n\r\n#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\r\n#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\r\n\r\n#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\r\n#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\r\n\r\n#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\r\n#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\r\n\r\n#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\r\n#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\r\n\r\n/* TPI ITATBCTR0 Register Definitions */\r\n#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */\r\n#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */\r\n\r\n/* TPI Integration Mode Control Register Definitions */\r\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\r\n#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\r\n\r\n/* TPI DEVID Register Definitions */\r\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\r\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\r\n\r\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\r\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\r\n\r\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\r\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\r\n\r\n#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\r\n#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\r\n\r\n#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\r\n#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\r\n\r\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\r\n#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\r\n\r\n/* TPI DEVTYPE Register Definitions */\r\n#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */\r\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\r\n\r\n#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */\r\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\r\n\r\n/*@}*/ /* end of group CMSIS_TPI */\r\n\r\n\r\n#if (__MPU_PRESENT == 1U)\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\r\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\r\n */\r\ntypedef struct\r\n{\r\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\r\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\r\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\r\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\r\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\r\n  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\r\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\r\n  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\r\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\r\n  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\r\n} MPU_Type;\r\n\r\n/* MPU Type Register Definitions */\r\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\r\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r\n\r\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\r\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r\n\r\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\r\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\r\n\r\n/* MPU Control Register Definitions */\r\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\r\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r\n\r\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\r\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r\n\r\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\r\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\r\n\r\n/* MPU Region Number Register Definitions */\r\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\r\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\r\n\r\n/* MPU Region Base Address Register Definitions */\r\n#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\r\n#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\r\n\r\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\r\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\r\n\r\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\r\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\r\n\r\n/* MPU Region Attribute and Size Register Definitions */\r\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\r\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\r\n\r\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\r\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\r\n\r\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\r\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\r\n\r\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\r\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\r\n\r\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\r\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\r\n\r\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\r\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\r\n\r\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\r\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\r\n\r\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\r\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\r\n\r\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\r\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\r\n\r\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\r\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\r\n\r\n/*@} end of group CMSIS_MPU */\r\n#endif\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r\n  \\brief    Type definitions for the Core Debug Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\r\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\r\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\r\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\r\n} CoreDebug_Type;\r\n\r\n/* Debug Halting Control and Status Register Definitions */\r\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\r\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\r\n\r\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\r\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r\n\r\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r\n\r\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\r\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r\n\r\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\r\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\r\n\r\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\r\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\r\n\r\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\r\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\r\n\r\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r\n\r\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\r\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r\n\r\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\r\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\r\n\r\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\r\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\r\n\r\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r\n\r\n/* Debug Core Register Selector Register Definitions */\r\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\r\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\r\n\r\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\r\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\r\n\r\n/* Debug Exception and Monitor Control Register Definitions */\r\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\r\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\r\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\r\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\r\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\r\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\r\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\r\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\r\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\r\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\r\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\r\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\r\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r\n\r\n/*@} end of group CMSIS_CoreDebug */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\r\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief   Mask and shift a bit field value for use in a register bit range.\r\n  \\param[in] field  Name of the register bit field.\r\n  \\param[in] value  Value of the bit field.\r\n  \\return           Masked and shifted value.\r\n*/\r\n#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)\r\n\r\n/**\r\n  \\brief     Mask and shift a register value to extract a bit filed value.\r\n  \\param[in] field  Name of the register bit field.\r\n  \\param[in] value  Value of register.\r\n  \\return           Masked and shifted bit field value.\r\n*/\r\n#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)\r\n\r\n/*@} end of group CMSIS_core_bitfield */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_core_base     Core Definitions\r\n  \\brief      Definitions for base addresses, unions, and structures.\r\n  @{\r\n */\r\n\r\n/* Memory mapping of Cortex-M3 Hardware */\r\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\r\n#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\r\n#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\r\n#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\r\n#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\r\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\r\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\r\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\r\n\r\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\r\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\r\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\r\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\r\n#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\r\n#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\r\n#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\r\n#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\r\n\r\n#if (__MPU_PRESENT == 1U)\r\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\r\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\r\n#endif\r\n\r\n/*@} */\r\n\r\n\r\n\r\n/*******************************************************************************\r\n *                Hardware Abstraction Layer\r\n  Core Function Interface contains:\r\n  - Core NVIC Functions\r\n  - Core SysTick Functions\r\n  - Core Debug Functions\r\n  - Core Register Access Functions\r\n ******************************************************************************/\r\n/**\r\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r\n*/\r\n\r\n\r\n\r\n/* ##########################   NVIC functions  #################################### */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\r\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief   Set Priority Grouping\r\n  \\details Sets the priority grouping field using the required unlock sequence.\r\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r\n           Only values from 0..7 are used.\r\n           In case of a conflict between priority grouping and available\r\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r\n  \\param [in]      PriorityGroup  Priority grouping field.\r\n */\r\n__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r\n{\r\n  uint32_t reg_value;\r\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\r\n\r\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\r\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\r\n  reg_value  =  (reg_value                                   |\r\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r\n                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */\r\n  SCB->AIRCR =  reg_value;\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Priority Grouping\r\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\r\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r\n{\r\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Enable External Interrupt\r\n  \\details Enables a device-specific interrupt in the NVIC interrupt controller.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Disable External Interrupt\r\n  \\details Disables a device-specific interrupt in the NVIC interrupt controller.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Pending Interrupt\r\n  \\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\return             0  Interrupt status is not pending.\r\n  \\return             1  Interrupt status is pending.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Pending Interrupt\r\n  \\details Sets the pending bit of an external interrupt.\r\n  \\param [in]      IRQn  Interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Clear Pending Interrupt\r\n  \\details Clears the pending bit of an external interrupt.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Active Interrupt\r\n  \\details Reads the active register in NVIC and returns the active bit.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\return             0  Interrupt status is not active.\r\n  \\return             1  Interrupt status is active.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r\n{\r\n  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Interrupt Priority\r\n  \\details Sets the priority of an interrupt.\r\n  \\note    The priority cannot be set for every core interrupt.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\param [in]  priority  Priority to set.\r\n */\r\n__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r\n{\r\n  if ((int32_t)(IRQn) < 0)\r\n  {\r\n    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r\n  }\r\n  else\r\n  {\r\n    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Interrupt Priority\r\n  \\details Reads the priority of an interrupt.\r\n           The interrupt number can be positive to specify an external (device specific) interrupt,\r\n           or negative to specify an internal (core) interrupt.\r\n  \\param [in]   IRQn  Interrupt number.\r\n  \\return             Interrupt Priority.\r\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r\n{\r\n\r\n  if ((int32_t)(IRQn) < 0)\r\n  {\r\n    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r\n  }\r\n  else\r\n  {\r\n    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Encode Priority\r\n  \\details Encodes the priority for an interrupt with the given priority group,\r\n           preemptive priority value, and subpriority value.\r\n           In case of a conflict between priority grouping and available\r\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r\n  \\param [in]     PriorityGroup  Used priority group.\r\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\r\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\r\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\r\n */\r\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r\n{\r\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r\n  uint32_t PreemptPriorityBits;\r\n  uint32_t SubPriorityBits;\r\n\r\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r\n\r\n  return (\r\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\r\n         );\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Decode Priority\r\n  \\details Decodes an interrupt priority value with a given priority group to\r\n           preemptive priority value and subpriority value.\r\n           In case of a conflict between priority grouping and available\r\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\r\n  \\param [in]     PriorityGroup  Used priority group.\r\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\r\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\r\n */\r\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r\n{\r\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r\n  uint32_t PreemptPriorityBits;\r\n  uint32_t SubPriorityBits;\r\n\r\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r\n\r\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   System Reset\r\n  \\details Initiates a system reset request to reset the MCU.\r\n */\r\n__STATIC_INLINE void NVIC_SystemReset(void)\r\n{\r\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\r\n                                                                       buffered write are completed before reset */\r\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\r\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\r\n  __DSB();                                                          /* Ensure completion of memory access */\r\n\r\n  for(;;)                                                           /* wait until reset */\r\n  {\r\n    __NOP();\r\n  }\r\n}\r\n\r\n/*@} end of CMSIS_Core_NVICFunctions */\r\n\r\n\r\n\r\n/* ##################################    SysTick function  ############################################ */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r\n  \\brief    Functions that configure the System.\r\n  @{\r\n */\r\n\r\n#if (__Vendor_SysTickConfig == 0U)\r\n\r\n/**\r\n  \\brief   System Tick Configuration\r\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r\n           Counter is in free running mode to generate periodic interrupts.\r\n  \\param [in]  ticks  Number of ticks between two interrupts.\r\n  \\return          0  Function succeeded.\r\n  \\return          1  Function failed.\r\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r\n           must contain a vendor-specific implementation of this function.\r\n */\r\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r\n{\r\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r\n  {\r\n    return (1UL);                                                   /* Reload value impossible */\r\n  }\r\n\r\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r\n                   SysTick_CTRL_TICKINT_Msk   |\r\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r\n  return (0UL);                                                     /* Function successful */\r\n}\r\n\r\n#endif\r\n\r\n/*@} end of CMSIS_Core_SysTickFunctions */\r\n\r\n\r\n\r\n/* ##################################### Debug In/Output function ########################################### */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\r\n  \\brief    Functions that access the ITM debug interface.\r\n  @{\r\n */\r\n\r\nextern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters. */\r\n#define                 ITM_RXBUFFER_EMPTY   0x5AA55AA5U /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\r\n\r\n\r\n/**\r\n  \\brief   ITM Send Character\r\n  \\details Transmits a character via the ITM channel 0, and\r\n           \\li Just returns when no debugger is connected that has booked the output.\r\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r\n  \\param [in]     ch  Character to transmit.\r\n  \\returns            Character to transmit.\r\n */\r\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r\n{\r\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\r\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\r\n  {\r\n    while (ITM->PORT[0U].u32 == 0UL)\r\n    {\r\n      __NOP();\r\n    }\r\n    ITM->PORT[0U].u8 = (uint8_t)ch;\r\n  }\r\n  return (ch);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   ITM Receive Character\r\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\r\n  \\return             Received character.\r\n  \\return         -1  No character pending.\r\n */\r\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r\n{\r\n  int32_t ch = -1;                           /* no character available */\r\n\r\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r\n  {\r\n    ch = ITM_RxBuffer;\r\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\r\n  }\r\n\r\n  return (ch);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   ITM Check Character\r\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\r\n  \\return          0  No character available.\r\n  \\return          1  Character available.\r\n */\r\n__STATIC_INLINE int32_t ITM_CheckChar (void)\r\n{\r\n\r\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r\n  {\r\n    return (0);                              /* no character available */\r\n  }\r\n  else\r\n  {\r\n    return (1);                              /*    character available */\r\n  }\r\n}\r\n\r\n/*@} end of CMSIS_core_DebugFunctions */\r\n\r\n\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __CORE_SC300_H_DEPENDANT */\r\n\r\n#endif /* __CMSIS_GENERIC */\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/bsp/opencr/ldscript/opencr_flash.ld",
    "content": "/*\n*****************************************************************************\n**\n\n**  File        : LinkerScript.ld\n**\n**  Abstract    : Linker script for STM32F746IGTx Device with\n**                1024KByte FLASH, 320KByte RAM\n**\n**                Set heap size, stack size and stack location according\n**                to application requirements.\n**\n**                Set memory bank area and size if external memory is used.\n**\n**  Target      : STMicroelectronics STM32\n**\n**\n**  Distribution: The file is distributed as is, without any warranty\n**                of any kind.\n**\n**  (c)Copyright Ac6.\n**  You may use this file as-is or modify it according to the needs of your\n**  project. Distribution of this file (unmodified or modified) is not\n**  permitted. Ac6 permit registered System Workbench for MCU users the\n**  rights to distribute the assembled, compiled & linked contents of this\n**  file as part of an application binary file, provided that it is built\n**  using the System Workbench for MCU toolchain.\n**\n*****************************************************************************\n*/\n\n/* Entry Point */\nENTRY(Reset_Handler)\n\n/* Highest address of the user mode stack */\n_estack = 0x2004FFFF;    /* end of RAM */\n/* Generate a link error if heap and stack don't fit into RAM */\n_Min_Heap_Size  = 0x8000; /* 8K required amount of heap  */\n_Min_Stack_Size = 0x2800; /* required amount of stack */\n\n/* Specify the memory areas */\nMEMORY\n{\n\nFLASH (rx)      : ORIGIN = 0x08040000, LENGTH = 768K\nRAM_DTCM (xrw)  : ORIGIN = 0x20000000, LENGTH = 0x10000\nRAM (xrw)       : ORIGIN = 0x200114EC, LENGTH = 0x3EB14\nQSPI (rx)       : ORIGIN = 0x90000000, LENGTH = 16M\n\n}\n\n/* Define output sections */\nSECTIONS\n{\n  /* The startup code goes first into FLASH */\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) /* Startup code */\n    . = ALIGN(4);\n  } >FLASH\n\n  /* The program code and other data goes into FLASH */\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           /* .text sections (code) */\n    *(.text*)          /* .text* sections (code) */\n    *(.glue_7)         /* glue arm to thumb code */\n    *(.glue_7t)        /* glue thumb to arm code */\n    *(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        /* define a global symbols at end of code */\n  } >FLASH\n\n  /* Constant data goes into FLASH */\n  .rodata :\n  {\n    . = ALIGN(4);\n    *(.rodata)         /* .rodata sections (constants, strings, etc.) */\n    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */\n    . = ALIGN(4);\n  } >FLASH\n\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n  .ARM : {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  /* used by the startup to initialize data */\n  _sidata = LOADADDR(.data);\n\n  /* Initialized data sections goes into RAM, load LMA copy after code */\n  .data :\n  {\n    . = ALIGN(4);\n    _sdata = .;        /* create a global symbol at data start */\n    *(.data)           /* .data sections */\n    *(.data*)          /* .data* sections */\n\n    . = ALIGN(4);\n    _edata = .;        /* define a global symbol at data end */\n  } >RAM AT> FLASH\n\n\n  /* Uninitialized data section */\n  . = ALIGN(4);\n  .bss :\n  {\n    /* This is used by the startup in order to initialize the .bss secion */\n    _sbss = .;         /* define a global symbol at bss start */\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         /* define a global symbol at bss end */\n    __bss_end__ = _ebss;\n  } >RAM\n\n  /* User_heap_stack section, used to check that there is enough RAM left */\n  ._user_heap_stack :\n  {\n    . = ALIGN(4);\n    PROVIDE ( end = . );\n    PROVIDE ( _end = . );\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(4);\n  } >RAM\n\n\n\n  /* Remove information from the standard libraries */\n  /DISCARD/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n  .NoneCacheableMem (NOLOAD): { *(.NoneCacheableMem) } >RAM_DTCM\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/bsp/opencr/startup/startup_stm32f746xx.S",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file      startup_stm32f746xx.s\r\n  * @author    MCD Application Team\r\n  * @brief     STM32F746xx Devices vector table for GCC based toolchain. \r\n  *            This module performs:\r\n  *                - Set the initial SP\r\n  *                - Set the initial PC == Reset_Handler,\r\n  *                - Set the vector table entries with the exceptions ISR address\r\n  *                - Branches to main in the C library (which eventually\r\n  *                  calls main()).\r\n  *            After Reset the Cortex-M7 processor is in Thread mode,\r\n  *            priority is Privileged, and the Stack is set to Main.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n    \r\n  .syntax unified\r\n  .cpu cortex-m7\r\n  .fpu softvfp\r\n  .thumb\r\n\r\n.global  g_pfnVectors\r\n.global  Default_Handler\r\n\r\n/* start address for the initialization values of the .data section. \r\ndefined in linker script */\r\n.word  _sidata\r\n/* start address for the .data section. defined in linker script */  \r\n.word  _sdata\r\n/* end address for the .data section. defined in linker script */\r\n.word  _edata\r\n/* start address for the .bss section. defined in linker script */\r\n.word  _sbss\r\n/* end address for the .bss section. defined in linker script */\r\n.word  _ebss\r\n/* stack used for SystemInit_ExtMemCtl; always internal RAM used */\r\n\r\n/**\r\n * @brief  This is the code that gets called when the processor first\r\n *          starts execution following a reset event. Only the absolutely\r\n *          necessary set is performed, after which the application\r\n *          supplied main() routine is called. \r\n * @param  None\r\n * @retval : None\r\n*/\r\n\r\n    .section  .text.Reset_Handler\r\n  .weak  Reset_Handler\r\n  .type  Reset_Handler, %function\r\nReset_Handler:  \r\n  ldr   sp, =_estack      /* set stack pointer */\r\n\r\n/* Copy the data segment initializers from flash to SRAM */  \r\n  movs  r1, #0\r\n  b  LoopCopyDataInit\r\n\r\nCopyDataInit:\r\n  ldr  r3, =_sidata\r\n  ldr  r3, [r3, r1]\r\n  str  r3, [r0, r1]\r\n  adds  r1, r1, #4\r\n    \r\nLoopCopyDataInit:\r\n  ldr  r0, =_sdata\r\n  ldr  r3, =_edata\r\n  adds  r2, r0, r1\r\n  cmp  r2, r3\r\n  bcc  CopyDataInit\r\n  ldr  r2, =_sbss\r\n  b  LoopFillZerobss\r\n/* Zero fill the bss segment. */  \r\nFillZerobss:\r\n  movs  r3, #0\r\n  str  r3, [r2], #4\r\n    \r\nLoopFillZerobss:\r\n  ldr  r3, = _ebss\r\n  cmp  r2, r3\r\n  bcc  FillZerobss\r\n\r\n/* Call the clock system initialization function.*/\r\n  bl  SystemInit   \r\n/* Call static constructors */\r\n    bl __libc_init_array\r\n/* Call the application's entry point.*/\r\n  bl  main\r\n  bx  lr    \r\n.size  Reset_Handler, .-Reset_Handler\r\n\r\n/**\r\n * @brief  This is the code that gets called when the processor receives an \r\n *         unexpected interrupt.  This simply enters an infinite loop, preserving\r\n *         the system state for examination by a debugger.\r\n * @param  None     \r\n * @retval None       \r\n*/\r\n    .section  .text.Default_Handler,\"ax\",%progbits\r\nDefault_Handler:\r\nInfinite_Loop:\r\n  b  Infinite_Loop\r\n  .size  Default_Handler, .-Default_Handler\r\n/******************************************************************************\r\n*\r\n* The minimal vector table for a Cortex M7. Note that the proper constructs\r\n* must be placed on this to ensure that it ends up at physical address\r\n* 0x0000.0000.\r\n* \r\n*******************************************************************************/\r\n   .section  .isr_vector,\"a\",%progbits\r\n  .type  g_pfnVectors, %object\r\n  .size  g_pfnVectors, .-g_pfnVectors\r\n   \r\n   \r\ng_pfnVectors:\r\n  .word  _estack\r\n  .word  Reset_Handler\r\n\r\n  .word  NMI_Handler\r\n  .word  HardFault_Handler\r\n  .word  MemManage_Handler\r\n  .word  BusFault_Handler\r\n  .word  UsageFault_Handler\r\n  .word  0\r\n  .word  0\r\n  .word  0\r\n  .word  0\r\n  .word  SVC_Handler\r\n  .word  DebugMon_Handler\r\n  .word  0\r\n  .word  PendSV_Handler\r\n  .word  SysTick_Handler\r\n  \r\n  /* External Interrupts */\r\n  .word     WWDG_IRQHandler                   /* Window WatchDog              */                                        \r\n  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */                        \r\n  .word     TAMP_STAMP_IRQHandler             /* Tamper and TimeStamps through the EXTI line */            \r\n  .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI line */                      \r\n  .word     FLASH_IRQHandler                  /* FLASH                        */                                          \r\n  .word     RCC_IRQHandler                    /* RCC                          */                                            \r\n  .word     EXTI0_IRQHandler                  /* EXTI Line0                   */                        \r\n  .word     EXTI1_IRQHandler                  /* EXTI Line1                   */                          \r\n  .word     EXTI2_IRQHandler                  /* EXTI Line2                   */                          \r\n  .word     EXTI3_IRQHandler                  /* EXTI Line3                   */                          \r\n  .word     EXTI4_IRQHandler                  /* EXTI Line4                   */                          \r\n  .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                */                  \r\n  .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                */                   \r\n  .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                */                   \r\n  .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                */                   \r\n  .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                */                   \r\n  .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                */                   \r\n  .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                */                   \r\n  .word     ADC_IRQHandler                    /* ADC1, ADC2 and ADC3s         */                   \r\n  .word     CAN1_TX_IRQHandler                /* CAN1 TX                      */                         \r\n  .word     CAN1_RX0_IRQHandler               /* CAN1 RX0                     */                          \r\n  .word     CAN1_RX1_IRQHandler               /* CAN1 RX1                     */                          \r\n  .word     CAN1_SCE_IRQHandler               /* CAN1 SCE                     */                          \r\n  .word     EXTI9_5_IRQHandler                /* External Line[9:5]s          */                          \r\n  .word     TIM1_BRK_TIM9_IRQHandler          /* TIM1 Break and TIM9          */         \r\n  .word     TIM1_UP_TIM10_IRQHandler          /* TIM1 Update and TIM10        */         \r\n  .word     TIM1_TRG_COM_TIM11_IRQHandler     /* TIM1 Trigger and Commutation and TIM11 */\r\n  .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */                          \r\n  .word     TIM2_IRQHandler                   /* TIM2                         */                   \r\n  .word     TIM3_IRQHandler                   /* TIM3                         */                   \r\n  .word     TIM4_IRQHandler                   /* TIM4                         */                   \r\n  .word     I2C1_EV_IRQHandler                /* I2C1 Event                   */                          \r\n  .word     I2C1_ER_IRQHandler                /* I2C1 Error                   */                          \r\n  .word     I2C2_EV_IRQHandler                /* I2C2 Event                   */                          \r\n  .word     I2C2_ER_IRQHandler                /* I2C2 Error                   */                            \r\n  .word     SPI1_IRQHandler                   /* SPI1                         */                   \r\n  .word     SPI2_IRQHandler                   /* SPI2                         */                   \r\n  .word     USART1_IRQHandler                 /* USART1                       */                   \r\n  .word     USART2_IRQHandler                 /* USART2                       */                   \r\n  .word     USART3_IRQHandler                 /* USART3                       */                   \r\n  .word     EXTI15_10_IRQHandler              /* External Line[15:10]s        */                          \r\n  .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through EXTI Line */                 \r\n  .word     OTG_FS_WKUP_IRQHandler            /* USB OTG FS Wakeup through EXTI line */                       \r\n  .word     TIM8_BRK_TIM12_IRQHandler         /* TIM8 Break and TIM12         */         \r\n  .word     TIM8_UP_TIM13_IRQHandler          /* TIM8 Update and TIM13        */         \r\n  .word     TIM8_TRG_COM_TIM14_IRQHandler     /* TIM8 Trigger and Commutation and TIM14 */\r\n  .word     TIM8_CC_IRQHandler                /* TIM8 Capture Compare         */                          \r\n  .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                 */                          \r\n  .word     FMC_IRQHandler                    /* FMC                          */                   \r\n  .word     SDMMC1_IRQHandler                 /* SDMMC1                       */                   \r\n  .word     TIM5_IRQHandler                   /* TIM5                         */                   \r\n  .word     SPI3_IRQHandler                   /* SPI3                         */                   \r\n  .word     UART4_IRQHandler                  /* UART4                        */                   \r\n  .word     UART5_IRQHandler                  /* UART5                        */                   \r\n  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC1&2 underrun errors */                   \r\n  .word     TIM7_IRQHandler                   /* TIM7                         */\r\n  .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                */                   \r\n  .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                */                   \r\n  .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                */                   \r\n  .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                */                   \r\n  .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */                   \r\n  .word     ETH_IRQHandler                    /* Ethernet                     */                   \r\n  .word     ETH_WKUP_IRQHandler               /* Ethernet Wakeup through EXTI line */                     \r\n  .word     CAN2_TX_IRQHandler                /* CAN2 TX                      */                          \r\n  .word     CAN2_RX0_IRQHandler               /* CAN2 RX0                     */                          \r\n  .word     CAN2_RX1_IRQHandler               /* CAN2 RX1                     */                          \r\n  .word     CAN2_SCE_IRQHandler               /* CAN2 SCE                     */                          \r\n  .word     OTG_FS_IRQHandler                 /* USB OTG FS                   */                   \r\n  .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */                   \r\n  .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */                   \r\n  .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */                   \r\n  .word     USART6_IRQHandler                 /* USART6                       */                    \r\n  .word     I2C3_EV_IRQHandler                /* I2C3 event                   */                          \r\n  .word     I2C3_ER_IRQHandler                /* I2C3 error                   */                          \r\n  .word     OTG_HS_EP1_OUT_IRQHandler         /* USB OTG HS End Point 1 Out   */                   \r\n  .word     OTG_HS_EP1_IN_IRQHandler          /* USB OTG HS End Point 1 In    */                   \r\n  .word     OTG_HS_WKUP_IRQHandler            /* USB OTG HS Wakeup through EXTI */                         \r\n  .word     OTG_HS_IRQHandler                 /* USB OTG HS                   */                   \r\n  .word     DCMI_IRQHandler                   /* DCMI                         */                   \r\n  .word     0                                 /* Reserved                     */                   \r\n  .word     RNG_IRQHandler                    /* Rng                          */\r\n  .word     FPU_IRQHandler                    /* FPU                          */\r\n  .word     UART7_IRQHandler                  /* UART7                        */      \r\n  .word     UART8_IRQHandler                  /* UART8                        */\r\n  .word     SPI4_IRQHandler                   /* SPI4                         */\r\n  .word     SPI5_IRQHandler                   /* SPI5                           */\r\n  .word     SPI6_IRQHandler                   /* SPI6                         */\r\n  .word     SAI1_IRQHandler                   /* SAI1                          */\r\n  .word     LTDC_IRQHandler                   /* LTDC                          */\r\n  .word     LTDC_ER_IRQHandler                /* LTDC error                      */\r\n  .word     DMA2D_IRQHandler                  /* DMA2D                          */\r\n  .word     SAI2_IRQHandler                   /* SAI2                         */\r\n  .word     QUADSPI_IRQHandler                /* QUADSPI                      */\r\n  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */\r\n  .word     CEC_IRQHandler                    /* HDMI_CEC                     */\r\n  .word     I2C4_EV_IRQHandler                /* I2C4 Event                   */\r\n  .word     I2C4_ER_IRQHandler                /* I2C4 Error                   */\r\n  .word     SPDIF_RX_IRQHandler               /* SPDIF_RX                     */  \r\n  \r\n/*******************************************************************************\r\n*\r\n* Provide weak aliases for each Exception handler to the Default_Handler. \r\n* As they are weak aliases, any function with the same name will override \r\n* this definition.\r\n* \r\n*******************************************************************************/\r\n   .weak      NMI_Handler\r\n   .thumb_set NMI_Handler,Default_Handler\r\n  \r\n   .weak      HardFault_Handler\r\n   .thumb_set HardFault_Handler,Default_Handler\r\n  \r\n   .weak      MemManage_Handler\r\n   .thumb_set MemManage_Handler,Default_Handler\r\n  \r\n   .weak      BusFault_Handler\r\n   .thumb_set BusFault_Handler,Default_Handler\r\n\r\n   .weak      UsageFault_Handler\r\n   .thumb_set UsageFault_Handler,Default_Handler\r\n\r\n   .weak      SVC_Handler\r\n   .thumb_set SVC_Handler,Default_Handler\r\n\r\n   .weak      DebugMon_Handler\r\n   .thumb_set DebugMon_Handler,Default_Handler\r\n\r\n   .weak      PendSV_Handler\r\n   .thumb_set PendSV_Handler,Default_Handler\r\n\r\n   .weak      SysTick_Handler\r\n   .thumb_set SysTick_Handler,Default_Handler              \r\n  \r\n   .weak      WWDG_IRQHandler                   \r\n   .thumb_set WWDG_IRQHandler,Default_Handler      \r\n                  \r\n   .weak      PVD_IRQHandler      \r\n   .thumb_set PVD_IRQHandler,Default_Handler\r\n               \r\n   .weak      TAMP_STAMP_IRQHandler            \r\n   .thumb_set TAMP_STAMP_IRQHandler,Default_Handler\r\n            \r\n   .weak      RTC_WKUP_IRQHandler                  \r\n   .thumb_set RTC_WKUP_IRQHandler,Default_Handler\r\n            \r\n   .weak      FLASH_IRQHandler         \r\n   .thumb_set FLASH_IRQHandler,Default_Handler\r\n                  \r\n   .weak      RCC_IRQHandler      \r\n   .thumb_set RCC_IRQHandler,Default_Handler\r\n                  \r\n   .weak      EXTI0_IRQHandler         \r\n   .thumb_set EXTI0_IRQHandler,Default_Handler\r\n                  \r\n   .weak      EXTI1_IRQHandler         \r\n   .thumb_set EXTI1_IRQHandler,Default_Handler\r\n                     \r\n   .weak      EXTI2_IRQHandler         \r\n   .thumb_set EXTI2_IRQHandler,Default_Handler \r\n                 \r\n   .weak      EXTI3_IRQHandler         \r\n   .thumb_set EXTI3_IRQHandler,Default_Handler\r\n                        \r\n   .weak      EXTI4_IRQHandler         \r\n   .thumb_set EXTI4_IRQHandler,Default_Handler\r\n                  \r\n   .weak      DMA1_Stream0_IRQHandler               \r\n   .thumb_set DMA1_Stream0_IRQHandler,Default_Handler\r\n         \r\n   .weak      DMA1_Stream1_IRQHandler               \r\n   .thumb_set DMA1_Stream1_IRQHandler,Default_Handler\r\n                  \r\n   .weak      DMA1_Stream2_IRQHandler               \r\n   .thumb_set DMA1_Stream2_IRQHandler,Default_Handler\r\n                  \r\n   .weak      DMA1_Stream3_IRQHandler               \r\n   .thumb_set DMA1_Stream3_IRQHandler,Default_Handler \r\n                 \r\n   .weak      DMA1_Stream4_IRQHandler              \r\n   .thumb_set DMA1_Stream4_IRQHandler,Default_Handler\r\n                  \r\n   .weak      DMA1_Stream5_IRQHandler               \r\n   .thumb_set DMA1_Stream5_IRQHandler,Default_Handler\r\n                  \r\n   .weak      DMA1_Stream6_IRQHandler               \r\n   .thumb_set DMA1_Stream6_IRQHandler,Default_Handler\r\n                  \r\n   .weak      ADC_IRQHandler      \r\n   .thumb_set ADC_IRQHandler,Default_Handler\r\n               \r\n   .weak      CAN1_TX_IRQHandler   \r\n   .thumb_set CAN1_TX_IRQHandler,Default_Handler\r\n            \r\n   .weak      CAN1_RX0_IRQHandler                  \r\n   .thumb_set CAN1_RX0_IRQHandler,Default_Handler\r\n                           \r\n   .weak      CAN1_RX1_IRQHandler                  \r\n   .thumb_set CAN1_RX1_IRQHandler,Default_Handler\r\n            \r\n   .weak      CAN1_SCE_IRQHandler                  \r\n   .thumb_set CAN1_SCE_IRQHandler,Default_Handler\r\n            \r\n   .weak      EXTI9_5_IRQHandler   \r\n   .thumb_set EXTI9_5_IRQHandler,Default_Handler\r\n            \r\n   .weak      TIM1_BRK_TIM9_IRQHandler            \r\n   .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler\r\n            \r\n   .weak      TIM1_UP_TIM10_IRQHandler            \r\n   .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler\r\n\r\n   .weak      TIM1_TRG_COM_TIM11_IRQHandler      \r\n   .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler\r\n      \r\n   .weak      TIM1_CC_IRQHandler   \r\n   .thumb_set TIM1_CC_IRQHandler,Default_Handler\r\n                  \r\n   .weak      TIM2_IRQHandler            \r\n   .thumb_set TIM2_IRQHandler,Default_Handler\r\n                  \r\n   .weak      TIM3_IRQHandler            \r\n   .thumb_set TIM3_IRQHandler,Default_Handler\r\n                  \r\n   .weak      TIM4_IRQHandler            \r\n   .thumb_set TIM4_IRQHandler,Default_Handler\r\n                  \r\n   .weak      I2C1_EV_IRQHandler   \r\n   .thumb_set I2C1_EV_IRQHandler,Default_Handler\r\n                     \r\n   .weak      I2C1_ER_IRQHandler   \r\n   .thumb_set I2C1_ER_IRQHandler,Default_Handler\r\n                     \r\n   .weak      I2C2_EV_IRQHandler   \r\n   .thumb_set I2C2_EV_IRQHandler,Default_Handler\r\n                  \r\n   .weak      I2C2_ER_IRQHandler   \r\n   .thumb_set I2C2_ER_IRQHandler,Default_Handler\r\n                           \r\n   .weak      SPI1_IRQHandler            \r\n   .thumb_set SPI1_IRQHandler,Default_Handler\r\n                        \r\n   .weak      SPI2_IRQHandler            \r\n   .thumb_set SPI2_IRQHandler,Default_Handler\r\n                  \r\n   .weak      USART1_IRQHandler      \r\n   .thumb_set USART1_IRQHandler,Default_Handler\r\n                     \r\n   .weak      USART2_IRQHandler      \r\n   .thumb_set USART2_IRQHandler,Default_Handler\r\n                     \r\n   .weak      USART3_IRQHandler      \r\n   .thumb_set USART3_IRQHandler,Default_Handler\r\n                  \r\n   .weak      EXTI15_10_IRQHandler               \r\n   .thumb_set EXTI15_10_IRQHandler,Default_Handler\r\n               \r\n   .weak      RTC_Alarm_IRQHandler               \r\n   .thumb_set RTC_Alarm_IRQHandler,Default_Handler\r\n            \r\n   .weak      OTG_FS_WKUP_IRQHandler         \r\n   .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler\r\n            \r\n   .weak      TIM8_BRK_TIM12_IRQHandler         \r\n   .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler\r\n         \r\n   .weak      TIM8_UP_TIM13_IRQHandler            \r\n   .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler\r\n         \r\n   .weak      TIM8_TRG_COM_TIM14_IRQHandler      \r\n   .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler\r\n      \r\n   .weak      TIM8_CC_IRQHandler   \r\n   .thumb_set TIM8_CC_IRQHandler,Default_Handler\r\n                  \r\n   .weak      DMA1_Stream7_IRQHandler               \r\n   .thumb_set DMA1_Stream7_IRQHandler,Default_Handler\r\n                     \r\n   .weak      FMC_IRQHandler            \r\n   .thumb_set FMC_IRQHandler,Default_Handler\r\n                     \r\n   .weak      SDMMC1_IRQHandler            \r\n   .thumb_set SDMMC1_IRQHandler,Default_Handler\r\n                     \r\n   .weak      TIM5_IRQHandler            \r\n   .thumb_set TIM5_IRQHandler,Default_Handler\r\n                     \r\n   .weak      SPI3_IRQHandler            \r\n   .thumb_set SPI3_IRQHandler,Default_Handler\r\n                     \r\n   .weak      UART4_IRQHandler         \r\n   .thumb_set UART4_IRQHandler,Default_Handler\r\n                  \r\n   .weak      UART5_IRQHandler         \r\n   .thumb_set UART5_IRQHandler,Default_Handler\r\n                  \r\n   .weak      TIM6_DAC_IRQHandler                  \r\n   .thumb_set TIM6_DAC_IRQHandler,Default_Handler\r\n               \r\n   .weak      TIM7_IRQHandler            \r\n   .thumb_set TIM7_IRQHandler,Default_Handler\r\n         \r\n   .weak      DMA2_Stream0_IRQHandler               \r\n   .thumb_set DMA2_Stream0_IRQHandler,Default_Handler\r\n               \r\n   .weak      DMA2_Stream1_IRQHandler               \r\n   .thumb_set DMA2_Stream1_IRQHandler,Default_Handler\r\n                  \r\n   .weak      DMA2_Stream2_IRQHandler               \r\n   .thumb_set DMA2_Stream2_IRQHandler,Default_Handler\r\n            \r\n   .weak      DMA2_Stream3_IRQHandler               \r\n   .thumb_set DMA2_Stream3_IRQHandler,Default_Handler\r\n            \r\n   .weak      DMA2_Stream4_IRQHandler               \r\n   .thumb_set DMA2_Stream4_IRQHandler,Default_Handler\r\n   \r\n   .weak      DMA2_Stream4_IRQHandler               \r\n   .thumb_set DMA2_Stream4_IRQHandler,Default_Handler   \r\n\r\n   .weak      ETH_IRQHandler   \r\n   .thumb_set ETH_IRQHandler,Default_Handler\r\n   \r\n   .weak      ETH_WKUP_IRQHandler   \r\n   .thumb_set ETH_WKUP_IRQHandler,Default_Handler\r\n\r\n   .weak      CAN2_TX_IRQHandler   \r\n   .thumb_set CAN2_TX_IRQHandler,Default_Handler   \r\n                           \r\n   .weak      CAN2_RX0_IRQHandler                  \r\n   .thumb_set CAN2_RX0_IRQHandler,Default_Handler\r\n                           \r\n   .weak      CAN2_RX1_IRQHandler                  \r\n   .thumb_set CAN2_RX1_IRQHandler,Default_Handler\r\n                           \r\n   .weak      CAN2_SCE_IRQHandler                  \r\n   .thumb_set CAN2_SCE_IRQHandler,Default_Handler\r\n                           \r\n   .weak      OTG_FS_IRQHandler      \r\n   .thumb_set OTG_FS_IRQHandler,Default_Handler\r\n                     \r\n   .weak      DMA2_Stream5_IRQHandler               \r\n   .thumb_set DMA2_Stream5_IRQHandler,Default_Handler\r\n                  \r\n   .weak      DMA2_Stream6_IRQHandler               \r\n   .thumb_set DMA2_Stream6_IRQHandler,Default_Handler\r\n                  \r\n   .weak      DMA2_Stream7_IRQHandler               \r\n   .thumb_set DMA2_Stream7_IRQHandler,Default_Handler\r\n                  \r\n   .weak      USART6_IRQHandler      \r\n   .thumb_set USART6_IRQHandler,Default_Handler\r\n                        \r\n   .weak      I2C3_EV_IRQHandler   \r\n   .thumb_set I2C3_EV_IRQHandler,Default_Handler\r\n                        \r\n   .weak      I2C3_ER_IRQHandler   \r\n   .thumb_set I2C3_ER_IRQHandler,Default_Handler\r\n                        \r\n   .weak      OTG_HS_EP1_OUT_IRQHandler         \r\n   .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler\r\n               \r\n   .weak      OTG_HS_EP1_IN_IRQHandler            \r\n   .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler\r\n               \r\n   .weak      OTG_HS_WKUP_IRQHandler         \r\n   .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler\r\n            \r\n   .weak      OTG_HS_IRQHandler      \r\n   .thumb_set OTG_HS_IRQHandler,Default_Handler\r\n                  \r\n   .weak      DCMI_IRQHandler            \r\n   .thumb_set DCMI_IRQHandler,Default_Handler\r\n\r\n   .weak      RNG_IRQHandler            \r\n   .thumb_set RNG_IRQHandler,Default_Handler   \r\n\r\n   .weak      FPU_IRQHandler                  \r\n   .thumb_set FPU_IRQHandler,Default_Handler\r\n\r\n   .weak      UART7_IRQHandler                  \r\n   .thumb_set UART7_IRQHandler,Default_Handler\r\n\r\n   .weak      UART8_IRQHandler                  \r\n   .thumb_set UART8_IRQHandler,Default_Handler   \r\n\r\n   .weak      SPI4_IRQHandler            \r\n   .thumb_set SPI4_IRQHandler,Default_Handler\r\n   \r\n   .weak      SPI5_IRQHandler            \r\n   .thumb_set SPI5_IRQHandler,Default_Handler\r\n\r\n   .weak      SPI6_IRQHandler            \r\n   .thumb_set SPI6_IRQHandler,Default_Handler   \r\n\r\n   .weak      SAI1_IRQHandler            \r\n   .thumb_set SAI1_IRQHandler,Default_Handler\r\n   \r\n   .weak      LTDC_IRQHandler            \r\n   .thumb_set LTDC_IRQHandler,Default_Handler\r\n\r\n   .weak      LTDC_ER_IRQHandler            \r\n   .thumb_set LTDC_ER_IRQHandler,Default_Handler\r\n\r\n   .weak      DMA2D_IRQHandler            \r\n   .thumb_set DMA2D_IRQHandler,Default_Handler   \r\n\r\n   .weak      SAI2_IRQHandler            \r\n   .thumb_set SAI2_IRQHandler,Default_Handler\r\n   \r\n   .weak      QUADSPI_IRQHandler            \r\n   .thumb_set QUADSPI_IRQHandler,Default_Handler\r\n \r\n   .weak      LPTIM1_IRQHandler            \r\n   .thumb_set LPTIM1_IRQHandler,Default_Handler\r\n\r\n   .weak      CEC_IRQHandler            \r\n   .thumb_set CEC_IRQHandler,Default_Handler\r\n   \r\n   .weak      I2C4_EV_IRQHandler            \r\n   .thumb_set I2C4_EV_IRQHandler,Default_Handler \r\n \r\n   .weak      I2C4_ER_IRQHandler            \r\n   .thumb_set I2C4_ER_IRQHandler,Default_Handler\r\n   \r\n   .weak      SPDIF_RX_IRQHandler            \r\n   .thumb_set SPDIF_RX_IRQHandler,Default_Handler \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/        \r\n \r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/bsp/opencr/stm32f746xx.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f746xx.h\r\n  * @author  MCD Application Team\r\n  * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer Header File.\r\n  *\r\n  *          This file contains:\r\n  *           - Data structures and the address mapping for all peripherals\r\n  *           - Peripheral's registers declarations and bits definition\r\n  *           - Macros to access peripherals registers hardware\r\n  *\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/** @addtogroup CMSIS_Device\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup stm32f746xx\r\n  * @{\r\n  */\r\n\r\n#ifndef __STM32F746xx_H\r\n#define __STM32F746xx_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif /* __cplusplus */\r\n\r\n/** @addtogroup Configuration_section_for_CMSIS\r\n  * @{\r\n  */\r\n\r\n/**\r\n * @brief STM32F7xx Interrupt Number Definition, according to the selected device\r\n *        in @ref Library_configuration_section\r\n */\r\ntypedef enum\r\n{\r\n/******  Cortex-M7 Processor Exceptions Numbers ****************************************************************/\r\n  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */\r\n  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M7 Memory Management Interrupt                           */\r\n  BusFault_IRQn               = -11,    /*!< 5 Cortex-M7 Bus Fault Interrupt                                   */\r\n  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M7 Usage Fault Interrupt                                 */\r\n  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M7 SV Call Interrupt                                    */\r\n  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M7 Debug Monitor Interrupt                              */\r\n  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M7 Pend SV Interrupt                                    */\r\n  SysTick_IRQn                = -1,     /*!< 15 Cortex-M7 System Tick Interrupt                                */\r\n/******  STM32 specific Interrupt Numbers **********************************************************************/\r\n  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */\r\n  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */\r\n  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */\r\n  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */\r\n  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */\r\n  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */\r\n  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */\r\n  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */\r\n  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */\r\n  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */\r\n  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */\r\n  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */\r\n  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */\r\n  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */\r\n  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */\r\n  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */\r\n  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */\r\n  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */\r\n  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */\r\n  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */\r\n  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */\r\n  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */\r\n  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */\r\n  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */\r\n  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */\r\n  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */\r\n  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */\r\n  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */\r\n  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */\r\n  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */\r\n  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */\r\n  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */\r\n  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */\r\n  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */\r\n  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */\r\n  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */\r\n  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */\r\n  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */\r\n  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */\r\n  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */\r\n  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */\r\n  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */\r\n  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */\r\n  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */\r\n  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */\r\n  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */\r\n  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */\r\n  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */\r\n  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */\r\n  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */\r\n  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */\r\n  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */\r\n  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */\r\n  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */\r\n  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */\r\n  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */\r\n  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */\r\n  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */\r\n  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */\r\n  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */\r\n  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */\r\n  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */\r\n  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */\r\n  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */\r\n  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */\r\n  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */\r\n  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */\r\n  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */\r\n  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */\r\n  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */\r\n  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */\r\n  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */\r\n  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */\r\n  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */\r\n  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */\r\n  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */\r\n  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */\r\n  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */\r\n  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */\r\n  RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */\r\n  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */\r\n  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */\r\n  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */\r\n  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */\r\n  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */\r\n  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */\r\n  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */\r\n  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */\r\n  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */\r\n  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */\r\n  SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */\r\n  QUADSPI_IRQn                = 92,     /*!< Quad SPI global interrupt                                         */\r\n  LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */\r\n  CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */\r\n  I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */\r\n  I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */\r\n  SPDIF_RX_IRQn               = 97,     /*!< SPDIF-RX global Interrupt                                         */\r\n} IRQn_Type;\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n * @brief Configuration of the Cortex-M7 Processor and Core Peripherals\r\n */\r\n#define __CM7_REV                 0x0001U  /*!< Cortex-M7 revision r0p1                       */\r\n#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */\r\n#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */\r\n#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */\r\n#define __FPU_PRESENT             1       /*!< FPU present                                   */\r\n#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */\r\n#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */\r\n#include \"core_cm7.h\"                     /*!< Cortex-M7 processor and core peripherals      */\r\n\r\n\r\n#include \"system_stm32f7xx.h\"\r\n#include <stdint.h>\r\n\r\n/** @addtogroup Peripheral_registers_structures\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief Analog to Digital Converter\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */\r\n  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */\r\n  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */\r\n  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */\r\n  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */\r\n  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */\r\n  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */\r\n  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */\r\n  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */\r\n  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */\r\n  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */\r\n  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */\r\n  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */\r\n  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */\r\n  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/\r\n  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */\r\n  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */\r\n  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */\r\n  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */\r\n  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */\r\n} ADC_TypeDef;\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */\r\n  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */\r\n  __IO uint32_t CDR;    /*!< ADC common regular data register for dual\r\n                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */\r\n} ADC_Common_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief Controller Area Network TxMailBox\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */\r\n  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */\r\n  __IO uint32_t TDLR; /*!< CAN mailbox data low register */\r\n  __IO uint32_t TDHR; /*!< CAN mailbox data high register */\r\n} CAN_TxMailBox_TypeDef;\r\n\r\n/**\r\n  * @brief Controller Area Network FIFOMailBox\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */\r\n  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */\r\n  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */\r\n  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */\r\n} CAN_FIFOMailBox_TypeDef;\r\n\r\n/**\r\n  * @brief Controller Area Network FilterRegister\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */\r\n  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */\r\n} CAN_FilterRegister_TypeDef;\r\n\r\n/**\r\n  * @brief Controller Area Network\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */\r\n  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */\r\n  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */\r\n  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */\r\n  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */\r\n  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */\r\n  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */\r\n  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */\r\n  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */\r\n  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */\r\n  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */\r\n  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */\r\n  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */\r\n  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */\r\n  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */\r\n  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */\r\n  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */\r\n  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */\r\n  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */\r\n  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */\r\n  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */\r\n  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */\r\n} CAN_TypeDef;\r\n\r\n/**\r\n  * @brief HDMI-CEC\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;           /*!< CEC control register,                                       Address offset:0x00 */\r\n  __IO uint32_t CFGR;         /*!< CEC configuration register,                                 Address offset:0x04 */\r\n  __IO uint32_t TXDR;         /*!< CEC Tx data register ,                                      Address offset:0x08 */\r\n  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,                                       Address offset:0x0C */\r\n  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register,                          Address offset:0x10 */\r\n  __IO uint32_t IER;          /*!< CEC interrupt enable register,                              Address offset:0x14 */\r\n}CEC_TypeDef;\r\n\r\n/**\r\n  * @brief CRC calculation unit\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t  DR;          /*!< CRC Data register,                           Address offset: 0x00 */\r\n  __IO uint8_t   IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */\r\n  uint8_t        RESERVED0;   /*!< Reserved, 0x05                                                    */\r\n  uint16_t       RESERVED1;   /*!< Reserved, 0x06                                                    */\r\n  __IO uint32_t  CR;          /*!< CRC Control register,                        Address offset: 0x08 */\r\n  uint32_t       RESERVED2;   /*!< Reserved,                                                    0x0C */\r\n  __IO uint32_t  INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */\r\n  __IO uint32_t  POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */\r\n} CRC_TypeDef;\r\n\r\n/**\r\n  * @brief Digital to Analog Converter\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */\r\n  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */\r\n  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */\r\n  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */\r\n  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */\r\n  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */\r\n  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */\r\n  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */\r\n  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */\r\n  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */\r\n  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */\r\n  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */\r\n  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */\r\n  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */\r\n} DAC_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief Debug MCU\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */\r\n  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */\r\n  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */\r\n  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */\r\n}DBGMCU_TypeDef;\r\n\r\n/**\r\n  * @brief DCMI\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */\r\n  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */\r\n  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */\r\n  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */\r\n  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */\r\n  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */\r\n  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */\r\n  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */\r\n  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */\r\n  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */\r\n  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */\r\n} DCMI_TypeDef;\r\n\r\n/**\r\n  * @brief DMA Controller\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;     /*!< DMA stream x configuration register      */\r\n  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */\r\n  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */\r\n  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */\r\n  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */\r\n  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */\r\n} DMA_Stream_TypeDef;\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */\r\n  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */\r\n  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */\r\n  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */\r\n} DMA_TypeDef;\r\n\r\n/**\r\n  * @brief DMA2D Controller\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */\r\n  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */\r\n  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */\r\n  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */\r\n  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */\r\n  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */\r\n  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */\r\n  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */\r\n  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */\r\n  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */\r\n  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */\r\n  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */\r\n  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */\r\n  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */\r\n  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */\r\n  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */\r\n  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */\r\n  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */\r\n  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */\r\n  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */\r\n  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */\r\n  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */\r\n  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */\r\n} DMA2D_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief Ethernet MAC\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t MACCR;\r\n  __IO uint32_t MACFFR;\r\n  __IO uint32_t MACHTHR;\r\n  __IO uint32_t MACHTLR;\r\n  __IO uint32_t MACMIIAR;\r\n  __IO uint32_t MACMIIDR;\r\n  __IO uint32_t MACFCR;\r\n  __IO uint32_t MACVLANTR;             /*    8 */\r\n  uint32_t      RESERVED0[2];\r\n  __IO uint32_t MACRWUFFR;             /*   11 */\r\n  __IO uint32_t MACPMTCSR;\r\n  uint32_t      RESERVED1;\r\n  __IO uint32_t MACDBGR;\r\n  __IO uint32_t MACSR;                 /*   15 */\r\n  __IO uint32_t MACIMR;\r\n  __IO uint32_t MACA0HR;\r\n  __IO uint32_t MACA0LR;\r\n  __IO uint32_t MACA1HR;\r\n  __IO uint32_t MACA1LR;\r\n  __IO uint32_t MACA2HR;\r\n  __IO uint32_t MACA2LR;\r\n  __IO uint32_t MACA3HR;\r\n  __IO uint32_t MACA3LR;               /*   24 */\r\n  uint32_t      RESERVED2[40];\r\n  __IO uint32_t MMCCR;                 /*   65 */\r\n  __IO uint32_t MMCRIR;\r\n  __IO uint32_t MMCTIR;\r\n  __IO uint32_t MMCRIMR;\r\n  __IO uint32_t MMCTIMR;               /*   69 */\r\n  uint32_t      RESERVED3[14];\r\n  __IO uint32_t MMCTGFSCCR;            /*   84 */\r\n  __IO uint32_t MMCTGFMSCCR;\r\n  uint32_t      RESERVED4[5];\r\n  __IO uint32_t MMCTGFCR;\r\n  uint32_t      RESERVED5[10];\r\n  __IO uint32_t MMCRFCECR;\r\n  __IO uint32_t MMCRFAECR;\r\n  uint32_t      RESERVED6[10];\r\n  __IO uint32_t MMCRGUFCR;\r\n  uint32_t      RESERVED7[334];\r\n  __IO uint32_t PTPTSCR;\r\n  __IO uint32_t PTPSSIR;\r\n  __IO uint32_t PTPTSHR;\r\n  __IO uint32_t PTPTSLR;\r\n  __IO uint32_t PTPTSHUR;\r\n  __IO uint32_t PTPTSLUR;\r\n  __IO uint32_t PTPTSAR;\r\n  __IO uint32_t PTPTTHR;\r\n  __IO uint32_t PTPTTLR;\r\n  __IO uint32_t RESERVED8;\r\n  __IO uint32_t PTPTSSR;\r\n  uint32_t      RESERVED9[565];\r\n  __IO uint32_t DMABMR;\r\n  __IO uint32_t DMATPDR;\r\n  __IO uint32_t DMARPDR;\r\n  __IO uint32_t DMARDLAR;\r\n  __IO uint32_t DMATDLAR;\r\n  __IO uint32_t DMASR;\r\n  __IO uint32_t DMAOMR;\r\n  __IO uint32_t DMAIER;\r\n  __IO uint32_t DMAMFBOCR;\r\n  __IO uint32_t DMARSWTR;\r\n  uint32_t      RESERVED10[8];\r\n  __IO uint32_t DMACHTDR;\r\n  __IO uint32_t DMACHRDR;\r\n  __IO uint32_t DMACHTBAR;\r\n  __IO uint32_t DMACHRBAR;\r\n} ETH_TypeDef;\r\n\r\n/**\r\n  * @brief External Interrupt/Event Controller\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */\r\n  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */\r\n  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */\r\n  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */\r\n  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */\r\n  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */\r\n} EXTI_TypeDef;\r\n\r\n/**\r\n  * @brief FLASH Registers\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t ACR;      /*!< FLASH access control register,     Address offset: 0x00 */\r\n  __IO uint32_t KEYR;     /*!< FLASH key register,                Address offset: 0x04 */\r\n  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,         Address offset: 0x08 */\r\n  __IO uint32_t SR;       /*!< FLASH status register,             Address offset: 0x0C */\r\n  __IO uint32_t CR;       /*!< FLASH control register,            Address offset: 0x10 */\r\n  __IO uint32_t OPTCR;    /*!< FLASH option control register ,    Address offset: 0x14 */\r\n  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1 ,  Address offset: 0x18 */\r\n} FLASH_TypeDef;\r\n\r\n\r\n\r\n/**\r\n  * @brief Flexible Memory Controller\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */\r\n} FMC_Bank1_TypeDef;\r\n\r\n/**\r\n  * @brief Flexible Memory Controller Bank1E\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */\r\n} FMC_Bank1E_TypeDef;\r\n\r\n/**\r\n  * @brief Flexible Memory Controller Bank3\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t PCR;        /*!< NAND Flash control register,                       Address offset: 0x80 */\r\n  __IO uint32_t SR;         /*!< NAND Flash FIFO status and interrupt register,     Address offset: 0x84 */\r\n  __IO uint32_t PMEM;       /*!< NAND Flash Common memory space timing register,    Address offset: 0x88 */\r\n  __IO uint32_t PATT;       /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */\r\n  uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                          */\r\n  __IO uint32_t ECCR;       /*!< NAND Flash ECC result registers,                   Address offset: 0x94 */\r\n} FMC_Bank3_TypeDef;\r\n\r\n/**\r\n  * @brief Flexible Memory Controller Bank5_6\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */\r\n  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */\r\n  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */\r\n  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */\r\n  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */\r\n} FMC_Bank5_6_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief General Purpose I/O\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */\r\n  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */\r\n  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */\r\n  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */\r\n  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */\r\n  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */\r\n  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */\r\n  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */\r\n  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */\r\n} GPIO_TypeDef;\r\n\r\n/**\r\n  * @brief System configuration controller\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */\r\n  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */\r\n  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */\r\n  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */\r\n  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */\r\n} SYSCFG_TypeDef;\r\n\r\n/**\r\n  * @brief Inter-integrated Circuit Interface\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */\r\n  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */\r\n  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */\r\n  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */\r\n  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */\r\n  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */\r\n  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */\r\n  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */\r\n  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */\r\n  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */\r\n  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */\r\n} I2C_TypeDef;\r\n\r\n/**\r\n  * @brief Independent WATCHDOG\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */\r\n  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */\r\n  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */\r\n  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */\r\n  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */\r\n} IWDG_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief LCD-TFT Display Controller\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04 */\r\n  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */\r\n  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */\r\n  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */\r\n  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */\r\n  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */\r\n  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20 */\r\n  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */\r\n  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28 */\r\n  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */\r\n  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30 */\r\n  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */\r\n  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */\r\n  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */\r\n  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */\r\n  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */\r\n  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */\r\n} LTDC_TypeDef;\r\n\r\n/**\r\n  * @brief LCD-TFT Display layer x Controller\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */\r\n  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */\r\n  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */\r\n  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */\r\n  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */\r\n  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */\r\n  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */\r\n  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */\r\n  uint32_t      RESERVED0[2];  /*!< Reserved */\r\n  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */\r\n  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */\r\n  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */\r\n  uint32_t      RESERVED1[3];  /*!< Reserved */\r\n  __IO uint32_t CLUTWR;        /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */\r\n\r\n} LTDC_Layer_TypeDef;\r\n\r\n/**\r\n  * @brief Power Control\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR1;   /*!< PWR power control register 1,        Address offset: 0x00 */\r\n  __IO uint32_t CSR1;  /*!< PWR power control/status register 2, Address offset: 0x04 */\r\n  __IO uint32_t CR2;   /*!< PWR power control register 2,        Address offset: 0x08 */\r\n  __IO uint32_t CSR2;  /*!< PWR power control/status register 2, Address offset: 0x0C */\r\n} PWR_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief Reset and Clock Control\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */\r\n  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */\r\n  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */\r\n  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */\r\n  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */\r\n  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */\r\n  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */\r\n  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */\r\n  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */\r\n  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */\r\n  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */\r\n  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */\r\n  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */\r\n  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */\r\n  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */\r\n  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */\r\n  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */\r\n  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */\r\n  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */\r\n  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */\r\n  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */\r\n  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */\r\n  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */\r\n  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */\r\n  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */\r\n  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */\r\n  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */\r\n  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */\r\n  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */\r\n  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */\r\n  __IO uint32_t PLLSAICFGR;    /*!< RCC PLLSAI configuration register,                           Address offset: 0x88 */\r\n  __IO uint32_t DCKCFGR1;      /*!< RCC Dedicated Clocks configuration register1,                 Address offset: 0x8C */\r\n  __IO uint32_t DCKCFGR2;      /*!< RCC Dedicated Clocks configuration register 2,               Address offset: 0x90 */\r\n\r\n} RCC_TypeDef;\r\n\r\n/**\r\n  * @brief Real-Time Clock\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */\r\n  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */\r\n  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */\r\n  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */\r\n  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */\r\n  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */\r\n       uint32_t reserved;   /*!< Reserved  */\r\n  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */\r\n  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */\r\n  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */\r\n  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */\r\n  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */\r\n  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */\r\n  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */\r\n  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */\r\n  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */\r\n  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */\r\n  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */\r\n  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */\r\n  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset: 0x4C */\r\n  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */\r\n  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */\r\n  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */\r\n  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */\r\n  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */\r\n  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */\r\n  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */\r\n  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */\r\n  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */\r\n  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */\r\n  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */\r\n  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */\r\n  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */\r\n  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */\r\n  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */\r\n  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */\r\n  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */\r\n  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */\r\n  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */\r\n  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */\r\n  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */\r\n  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */\r\n  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */\r\n  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */\r\n  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */\r\n  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */\r\n  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */\r\n  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */\r\n  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */\r\n  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */\r\n  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */\r\n  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */\r\n} RTC_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief Serial Audio Interface\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */\r\n} SAI_TypeDef;\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */\r\n  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */\r\n  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */\r\n  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */\r\n  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */\r\n  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */\r\n  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */\r\n  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */\r\n} SAI_Block_TypeDef;\r\n\r\n/**\r\n  * @brief SPDIF-RX Interface\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */\r\n  __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */\r\n  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */\r\n  __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */\r\n  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */\r\n  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */\r\n  __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */\r\n} SPDIFRX_TypeDef;\r\n\r\n/**\r\n  * @brief SD host Interface\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t POWER;          /*!< SDMMC power control register,    Address offset: 0x00 */\r\n  __IO uint32_t CLKCR;          /*!< SDMMClock control register,     Address offset: 0x04 */\r\n  __IO uint32_t ARG;            /*!< SDMMC argument register,         Address offset: 0x08 */\r\n  __IO uint32_t CMD;            /*!< SDMMC command register,          Address offset: 0x0C */\r\n  __I uint32_t  RESPCMD;        /*!< SDMMC command response register, Address offset: 0x10 */\r\n  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,       Address offset: 0x14 */\r\n  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,       Address offset: 0x18 */\r\n  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,       Address offset: 0x1C */\r\n  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,       Address offset: 0x20 */\r\n  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,       Address offset: 0x24 */\r\n  __IO uint32_t DLEN;           /*!< SDMMC data length register,      Address offset: 0x28 */\r\n  __IO uint32_t DCTRL;          /*!< SDMMC data control register,     Address offset: 0x2C */\r\n  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,     Address offset: 0x30 */\r\n  __I uint32_t  STA;            /*!< SDMMC status register,           Address offset: 0x34 */\r\n  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,  Address offset: 0x38 */\r\n  __IO uint32_t MASK;           /*!< SDMMC mask register,             Address offset: 0x3C */\r\n  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */\r\n  __I uint32_t  FIFOCNT;        /*!< SDMMC FIFO counter register,     Address offset: 0x48 */\r\n  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */\r\n  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,        Address offset: 0x80 */\r\n} SDMMC_TypeDef;\r\n\r\n/**\r\n  * @brief Serial Peripheral Interface\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */\r\n  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */\r\n  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */\r\n  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */\r\n  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */\r\n  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */\r\n  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */\r\n  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */\r\n  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */\r\n} SPI_TypeDef;\r\n\r\n/**\r\n  * @brief QUAD Serial Peripheral Interface\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */\r\n  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */\r\n  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */\r\n  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */\r\n  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */\r\n  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */\r\n  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */\r\n  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */\r\n  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */\r\n  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */\r\n  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */\r\n  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */\r\n  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */\r\n} QUADSPI_TypeDef;\r\n\r\n/**\r\n  * @brief TIM\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */\r\n  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */\r\n  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */\r\n  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */\r\n  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */\r\n  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */\r\n  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */\r\n  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */\r\n  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */\r\n  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */\r\n  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */\r\n  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */\r\n  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */\r\n  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */\r\n  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */\r\n  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */\r\n  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */\r\n  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */\r\n  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */\r\n  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */\r\n  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */\r\n  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */\r\n  __IO uint32_t CCR5;        /*!< TIM capture/compare mode register5,       Address offset: 0x58 */\r\n  __IO uint32_t CCR6;        /*!< TIM capture/compare mode register6,       Address offset: 0x5C */\r\n\r\n} TIM_TypeDef;\r\n\r\n/**\r\n  * @brief LPTIMIMER\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */\r\n  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */\r\n  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */\r\n  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                       Address offset: 0x0C */\r\n  __IO uint32_t CR;       /*!< LPTIM Control register,                             Address offset: 0x10 */\r\n  __IO uint32_t CMP;      /*!< LPTIM Compare register,                             Address offset: 0x14 */\r\n  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                          Address offset: 0x18 */\r\n  __IO uint32_t CNT;      /*!< LPTIM Counter register,                             Address offset: 0x1C */\r\n} LPTIM_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief Universal Synchronous Asynchronous Receiver Transmitter\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */\r\n  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */\r\n  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */\r\n  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */\r\n  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */\r\n  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */\r\n  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */\r\n  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */\r\n  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */\r\n  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */\r\n  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */\r\n} USART_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief Window WATCHDOG\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */\r\n  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */\r\n  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */\r\n} WWDG_TypeDef;\r\n\r\n\r\n/**\r\n  * @brief RNG\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */\r\n  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */\r\n  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */\r\n} RNG_TypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @brief USB_OTG_Core_Registers\r\n  */\r\ntypedef struct\r\n{\r\n __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */\r\n  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */\r\n  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */\r\n  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */\r\n  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */\r\n  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */\r\n  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */\r\n  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */\r\n  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */\r\n  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */\r\n  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */\r\n  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */\r\n  uint32_t Reserved30[2];             /*!< Reserved                                     030h */\r\n  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */\r\n  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */\r\n  uint32_t  Reserved5[3];             /*!< Reserved                                040h-048h */\r\n  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */\r\n  uint32_t  Reserved6;                /*!< Reserved                                     050h */\r\n  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */\r\n  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */\r\n  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */\r\n   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */\r\n    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */\r\n  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */\r\n  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */\r\n} USB_OTG_GlobalTypeDef;\r\n\r\n\r\n/**\r\n  * @brief USB_OTG_device_Registers\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */\r\n  __IO uint32_t DCTL;            /*!< dev Control Register         804h */\r\n  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */\r\n  uint32_t Reserved0C;           /*!< Reserved                     80Ch */\r\n  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */\r\n  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */\r\n  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */\r\n  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */\r\n  uint32_t  Reserved20;          /*!< Reserved                     820h */\r\n  uint32_t Reserved9;            /*!< Reserved                     824h */\r\n  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */\r\n  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */\r\n  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */\r\n  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */\r\n  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */\r\n  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */\r\n  uint32_t Reserved40;           /*!< dedicated EP mask            840h */\r\n  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */\r\n  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */\r\n  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */\r\n} USB_OTG_DeviceTypeDef;\r\n\r\n\r\n/**\r\n  * @brief USB_OTG_IN_Endpoint-Specific_Register\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */\r\n  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */\r\n  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */\r\n  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */\r\n  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */\r\n  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */\r\n  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */\r\n  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */\r\n} USB_OTG_INEndpointTypeDef;\r\n\r\n\r\n/**\r\n  * @brief USB_OTG_OUT_Endpoint-Specific_Registers\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */\r\n  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */\r\n  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */\r\n  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */\r\n  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */\r\n  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */\r\n  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */\r\n} USB_OTG_OUTEndpointTypeDef;\r\n\r\n\r\n/**\r\n  * @brief USB_OTG_Host_Mode_Register_Structures\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */\r\n  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */\r\n  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */\r\n  uint32_t Reserved40C;           /*!< Reserved                             40Ch */\r\n  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */\r\n  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */\r\n  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */\r\n} USB_OTG_HostTypeDef;\r\n\r\n/**\r\n  * @brief USB_OTG_Host_Channel_Specific_Registers\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */\r\n  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */\r\n  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */\r\n  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */\r\n  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */\r\n  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */\r\n  uint32_t Reserved[2];           /*!< Reserved                                      */\r\n} USB_OTG_HostChannelTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n\r\n\r\n/** @addtogroup Peripheral_memory_map\r\n  * @{\r\n  */\r\n#define RAMITCM_BASE           0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM  */\r\n#define FLASHITCM_BASE         0x00200000U /*!< Base address of : (up to 1 MB) embedded FLASH memory  accessible over ITCM              */\r\n#define FLASHAXI_BASE          0x08000000U /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI                */\r\n#define RAMDTCM_BASE           0x20000000U /*!< Base address of : 64KB system data RAM accessible over DTCM                             */\r\n#define PERIPH_BASE            0x40000000U /*!< Base address of : AHB/ABP Peripherals                                                   */\r\n#define BKPSRAM_BASE           0x40024000U /*!< Base address of : Backup SRAM(4 KB)                                                     */\r\n#define QSPI_BASE              0x90000000U /*!< Base address of : QSPI memories  accessible over AXI                                    */\r\n#define FMC_R_BASE             0xA0000000U /*!< Base address of : FMC Control registers                                                 */\r\n#define QSPI_R_BASE            0xA0001000U /*!< Base address of : QSPI Control  registers                                               */\r\n#define SRAM1_BASE             0x20010000U /*!< Base address of : 240KB RAM1 accessible over AXI/AHB                                    */\r\n#define SRAM2_BASE             0x2004C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB                                     */\r\n#define FLASH_END              0x080FFFFFU /*!< FLASH end address */\r\n#define FLASH_OTP_BASE         0x1FF0F000U /*!< Base address of : (up to 1024 Bytes) embedded FLASH OTP Area                            */\r\n#define FLASH_OTP_END          0x1FF0F41FU /*!< End address of : (up to 1024 Bytes) embedded FLASH OTP Area                             */\r\n\r\n/* Legacy define */\r\n#define FLASH_BASE     FLASHAXI_BASE\r\n\r\n/*!< Peripheral memory map */\r\n#define APB1PERIPH_BASE        PERIPH_BASE\r\n#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)\r\n#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)\r\n#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)\r\n\r\n/*!< APB1 peripherals */\r\n#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)\r\n#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)\r\n#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)\r\n#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)\r\n#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)\r\n#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)\r\n#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800U)\r\n#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00U)\r\n#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000U)\r\n#define LPTIM1_BASE           (APB1PERIPH_BASE + 0x2400U)\r\n#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)\r\n#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)\r\n#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)\r\n#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)\r\n#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)\r\n#define SPDIFRX_BASE          (APB1PERIPH_BASE + 0x4000U)\r\n#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)\r\n#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)\r\n#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)\r\n#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)\r\n#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)\r\n#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)\r\n#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)\r\n#define I2C4_BASE             (APB1PERIPH_BASE + 0x6000U)\r\n#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)\r\n#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)\r\n#define CEC_BASE              (APB1PERIPH_BASE + 0x6C00U)\r\n#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)\r\n#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)\r\n#define UART7_BASE            (APB1PERIPH_BASE + 0x7800U)\r\n#define UART8_BASE            (APB1PERIPH_BASE + 0x7C00U)\r\n\r\n/*!< APB2 peripherals */\r\n#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)\r\n#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400U)\r\n#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)\r\n#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)\r\n#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)\r\n#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100U)\r\n#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200U)\r\n#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)\r\n#define SDMMC1_BASE           (APB2PERIPH_BASE + 0x2C00U)\r\n#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)\r\n#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400U)\r\n#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)\r\n#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)\r\n#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)\r\n#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)\r\n#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)\r\n#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000U)\r\n#define SPI6_BASE             (APB2PERIPH_BASE + 0x5400U)\r\n#define SAI1_BASE             (APB2PERIPH_BASE + 0x5800U)\r\n#define SAI2_BASE             (APB2PERIPH_BASE + 0x5C00U)\r\n#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004U)\r\n#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024U)\r\n#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004U)\r\n#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024U)\r\n#define LTDC_BASE             (APB2PERIPH_BASE + 0x6800U)\r\n#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84U)\r\n#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104U)\r\n/*!< AHB1 peripherals */\r\n#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)\r\n#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)\r\n#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)\r\n#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)\r\n#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)\r\n#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400U)\r\n#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800U)\r\n#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)\r\n#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000U)\r\n#define GPIOJ_BASE            (AHB1PERIPH_BASE + 0x2400U)\r\n#define GPIOK_BASE            (AHB1PERIPH_BASE + 0x2800U)\r\n#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)\r\n#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)\r\n#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)\r\n#define UID_BASE              0x1FF0F420U                   /*!< Unique device ID register base address */\r\n#define FLASHSIZE_BASE        0x1FF0F442U                   /*!< FLASH Size register base address */\r\n#define PACKAGE_BASE          0x1FFF7BF0U                   /*!< Package size register base address */\r\n/* Legacy define */\r\n#define PACKAGESIZE_BASE      PACKAGE_BASE\r\n\r\n#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)\r\n#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)\r\n#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)\r\n#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)\r\n#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)\r\n#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)\r\n#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)\r\n#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)\r\n#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)\r\n#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)\r\n#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)\r\n#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)\r\n#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)\r\n#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)\r\n#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)\r\n#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)\r\n#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)\r\n#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)\r\n#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000U)\r\n#define ETH_MAC_BASE          (ETH_BASE)\r\n#define ETH_MMC_BASE          (ETH_BASE + 0x0100U)\r\n#define ETH_PTP_BASE          (ETH_BASE + 0x0700U)\r\n#define ETH_DMA_BASE          (ETH_BASE + 0x1000U)\r\n#define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000U)\r\n/*!< AHB2 peripherals */\r\n#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000U)\r\n#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800U)\r\n/*!< FMC Bankx registers base address */\r\n#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000U)\r\n#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104U)\r\n#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080U)\r\n#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140U)\r\n\r\n/* Debug MCU registers base address */\r\n#define DBGMCU_BASE           0xE0042000U\r\n\r\n/*!< USB registers base address */\r\n#define USB_OTG_HS_PERIPH_BASE               0x40040000U\r\n#define USB_OTG_FS_PERIPH_BASE               0x50000000U\r\n\r\n#define USB_OTG_GLOBAL_BASE                  0x000U\r\n#define USB_OTG_DEVICE_BASE                  0x800U\r\n#define USB_OTG_IN_ENDPOINT_BASE             0x900U\r\n#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U\r\n#define USB_OTG_EP_REG_SIZE                  0x20U\r\n#define USB_OTG_HOST_BASE                    0x400U\r\n#define USB_OTG_HOST_PORT_BASE               0x440U\r\n#define USB_OTG_HOST_CHANNEL_BASE            0x500U\r\n#define USB_OTG_HOST_CHANNEL_SIZE            0x20U\r\n#define USB_OTG_PCGCCTL_BASE                 0xE00U\r\n#define USB_OTG_FIFO_BASE                    0x1000U\r\n#define USB_OTG_FIFO_SIZE                    0x1000U\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup Peripheral_declaration\r\n  * @{\r\n  */\r\n#define TIM2                ((TIM_TypeDef *) TIM2_BASE)\r\n#define TIM3                ((TIM_TypeDef *) TIM3_BASE)\r\n#define TIM4                ((TIM_TypeDef *) TIM4_BASE)\r\n#define TIM5                ((TIM_TypeDef *) TIM5_BASE)\r\n#define TIM6                ((TIM_TypeDef *) TIM6_BASE)\r\n#define TIM7                ((TIM_TypeDef *) TIM7_BASE)\r\n#define TIM12               ((TIM_TypeDef *) TIM12_BASE)\r\n#define TIM13               ((TIM_TypeDef *) TIM13_BASE)\r\n#define TIM14               ((TIM_TypeDef *) TIM14_BASE)\r\n#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)\r\n#define RTC                 ((RTC_TypeDef *) RTC_BASE)\r\n#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)\r\n#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)\r\n#define SPI2                ((SPI_TypeDef *) SPI2_BASE)\r\n#define SPI3                ((SPI_TypeDef *) SPI3_BASE)\r\n#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)\r\n#define USART2              ((USART_TypeDef *) USART2_BASE)\r\n#define USART3              ((USART_TypeDef *) USART3_BASE)\r\n#define UART4               ((USART_TypeDef *) UART4_BASE)\r\n#define UART5               ((USART_TypeDef *) UART5_BASE)\r\n#define I2C1                ((I2C_TypeDef *) I2C1_BASE)\r\n#define I2C2                ((I2C_TypeDef *) I2C2_BASE)\r\n#define I2C3                ((I2C_TypeDef *) I2C3_BASE)\r\n#define I2C4                ((I2C_TypeDef *) I2C4_BASE)\r\n#define CAN1                ((CAN_TypeDef *) CAN1_BASE)\r\n#define CAN2                ((CAN_TypeDef *) CAN2_BASE)\r\n#define CEC                 ((CEC_TypeDef *) CEC_BASE)\r\n#define PWR                 ((PWR_TypeDef *) PWR_BASE)\r\n#define DAC1                ((DAC_TypeDef *) DAC_BASE)\r\n#define DAC                 ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */\r\n#define UART7               ((USART_TypeDef *) UART7_BASE)\r\n#define UART8               ((USART_TypeDef *) UART8_BASE)\r\n#define TIM1                ((TIM_TypeDef *) TIM1_BASE)\r\n#define TIM8                ((TIM_TypeDef *) TIM8_BASE)\r\n#define USART1              ((USART_TypeDef *) USART1_BASE)\r\n#define USART6              ((USART_TypeDef *) USART6_BASE)\r\n#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)\r\n#define ADC1                ((ADC_TypeDef *) ADC1_BASE)\r\n#define ADC2                ((ADC_TypeDef *) ADC2_BASE)\r\n#define ADC3                ((ADC_TypeDef *) ADC3_BASE)\r\n#define ADC123_COMMON       ((ADC_Common_TypeDef *) ADC_BASE)\r\n#define SDMMC1              ((SDMMC_TypeDef *) SDMMC1_BASE)\r\n#define SPI1                ((SPI_TypeDef *) SPI1_BASE)\r\n#define SPI4                ((SPI_TypeDef *) SPI4_BASE)\r\n#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)\r\n#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)\r\n#define TIM9                ((TIM_TypeDef *) TIM9_BASE)\r\n#define TIM10               ((TIM_TypeDef *) TIM10_BASE)\r\n#define TIM11               ((TIM_TypeDef *) TIM11_BASE)\r\n#define SPI5                ((SPI_TypeDef *) SPI5_BASE)\r\n#define SPI6                ((SPI_TypeDef *) SPI6_BASE)\r\n#define SAI1                ((SAI_TypeDef *) SAI1_BASE)\r\n#define SAI2                ((SAI_TypeDef *) SAI2_BASE)\r\n#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)\r\n#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)\r\n#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)\r\n#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)\r\n#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)\r\n#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)\r\n#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)\r\n#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)\r\n#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)\r\n#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)\r\n#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)\r\n#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)\r\n#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)\r\n#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)\r\n#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)\r\n#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)\r\n#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)\r\n#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)\r\n#define CRC                 ((CRC_TypeDef *) CRC_BASE)\r\n#define RCC                 ((RCC_TypeDef *) RCC_BASE)\r\n#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)\r\n#define DMA1                ((DMA_TypeDef *) DMA1_BASE)\r\n#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)\r\n#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)\r\n#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)\r\n#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)\r\n#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)\r\n#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)\r\n#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)\r\n#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)\r\n#define DMA2                ((DMA_TypeDef *) DMA2_BASE)\r\n#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)\r\n#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)\r\n#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)\r\n#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)\r\n#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)\r\n#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)\r\n#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)\r\n#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)\r\n#define ETH                 ((ETH_TypeDef *) ETH_BASE)\r\n#define DMA2D               ((DMA2D_TypeDef *)DMA2D_BASE)\r\n#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)\r\n#define RNG                 ((RNG_TypeDef *) RNG_BASE)\r\n#define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)\r\n#define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)\r\n#define FMC_Bank3           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)\r\n#define FMC_Bank5_6         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)\r\n#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)\r\n#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)\r\n#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)\r\n#define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup Exported_constants\r\n  * @{\r\n  */\r\n\r\n  /** @addtogroup Peripheral_Registers_Bits_Definition\r\n  * @{\r\n  */\r\n\r\n/******************************************************************************/\r\n/*                         Peripheral Registers_Bits_Definition               */\r\n/******************************************************************************/\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                        Analog to Digital Converter                         */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bit definition for ADC_SR register  ********************/\r\n#define ADC_SR_AWD_Pos            (0U)                                         \r\n#define ADC_SR_AWD_Msk            (0x1U << ADC_SR_AWD_Pos)                     /*!< 0x00000001 */\r\n#define ADC_SR_AWD                ADC_SR_AWD_Msk                               /*!<Analog watchdog flag                                 */\r\n#define ADC_SR_EOC_Pos            (1U)                                         \r\n#define ADC_SR_EOC_Msk            (0x1U << ADC_SR_EOC_Pos)                     /*!< 0x00000002 */\r\n#define ADC_SR_EOC                ADC_SR_EOC_Msk                               /*!<End of conversion                                    */\r\n#define ADC_SR_JEOC_Pos           (2U)                                         \r\n#define ADC_SR_JEOC_Msk           (0x1U << ADC_SR_JEOC_Pos)                    /*!< 0x00000004 */\r\n#define ADC_SR_JEOC               ADC_SR_JEOC_Msk                              /*!<Injected channel end of conversion                   */\r\n#define ADC_SR_JSTRT_Pos          (3U)                                         \r\n#define ADC_SR_JSTRT_Msk          (0x1U << ADC_SR_JSTRT_Pos)                   /*!< 0x00000008 */\r\n#define ADC_SR_JSTRT              ADC_SR_JSTRT_Msk                             /*!<Injected channel Start flag                          */\r\n#define ADC_SR_STRT_Pos           (4U)                                         \r\n#define ADC_SR_STRT_Msk           (0x1U << ADC_SR_STRT_Pos)                    /*!< 0x00000010 */\r\n#define ADC_SR_STRT               ADC_SR_STRT_Msk                              /*!<Regular channel Start flag                           */\r\n#define ADC_SR_OVR_Pos            (5U)                                         \r\n#define ADC_SR_OVR_Msk            (0x1U << ADC_SR_OVR_Pos)                     /*!< 0x00000020 */\r\n#define ADC_SR_OVR                ADC_SR_OVR_Msk                               /*!<Overrun flag                                         */\r\n\r\n/*******************  Bit definition for ADC_CR1 register  ********************/\r\n#define ADC_CR1_AWDCH_Pos         (0U)                                         \r\n#define ADC_CR1_AWDCH_Msk         (0x1FU << ADC_CR1_AWDCH_Pos)                 /*!< 0x0000001F */\r\n#define ADC_CR1_AWDCH             ADC_CR1_AWDCH_Msk                            /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */\r\n#define ADC_CR1_AWDCH_0           (0x01U << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000001 */\r\n#define ADC_CR1_AWDCH_1           (0x02U << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000002 */\r\n#define ADC_CR1_AWDCH_2           (0x04U << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000004 */\r\n#define ADC_CR1_AWDCH_3           (0x08U << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000008 */\r\n#define ADC_CR1_AWDCH_4           (0x10U << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000010 */\r\n#define ADC_CR1_EOCIE_Pos         (5U)                                         \r\n#define ADC_CR1_EOCIE_Msk         (0x1U << ADC_CR1_EOCIE_Pos)                  /*!< 0x00000020 */\r\n#define ADC_CR1_EOCIE             ADC_CR1_EOCIE_Msk                            /*!<Interrupt enable for EOC                             */\r\n#define ADC_CR1_AWDIE_Pos         (6U)                                         \r\n#define ADC_CR1_AWDIE_Msk         (0x1U << ADC_CR1_AWDIE_Pos)                  /*!< 0x00000040 */\r\n#define ADC_CR1_AWDIE             ADC_CR1_AWDIE_Msk                            /*!<AAnalog Watchdog interrupt enable                    */\r\n#define ADC_CR1_JEOCIE_Pos        (7U)                                         \r\n#define ADC_CR1_JEOCIE_Msk        (0x1U << ADC_CR1_JEOCIE_Pos)                 /*!< 0x00000080 */\r\n#define ADC_CR1_JEOCIE            ADC_CR1_JEOCIE_Msk                           /*!<Interrupt enable for injected channels               */\r\n#define ADC_CR1_SCAN_Pos          (8U)                                         \r\n#define ADC_CR1_SCAN_Msk          (0x1U << ADC_CR1_SCAN_Pos)                   /*!< 0x00000100 */\r\n#define ADC_CR1_SCAN              ADC_CR1_SCAN_Msk                             /*!<Scan mode */\r\n#define ADC_CR1_AWDSGL_Pos        (9U)                                         \r\n#define ADC_CR1_AWDSGL_Msk        (0x1U << ADC_CR1_AWDSGL_Pos)                 /*!< 0x00000200 */\r\n#define ADC_CR1_AWDSGL            ADC_CR1_AWDSGL_Msk                           /*!<Enable the watchdog on a single channel in scan mode */\r\n#define ADC_CR1_JAUTO_Pos         (10U)                                        \r\n#define ADC_CR1_JAUTO_Msk         (0x1U << ADC_CR1_JAUTO_Pos)                  /*!< 0x00000400 */\r\n#define ADC_CR1_JAUTO             ADC_CR1_JAUTO_Msk                            /*!<Automatic injected group conversion                  */\r\n#define ADC_CR1_DISCEN_Pos        (11U)                                        \r\n#define ADC_CR1_DISCEN_Msk        (0x1U << ADC_CR1_DISCEN_Pos)                 /*!< 0x00000800 */\r\n#define ADC_CR1_DISCEN            ADC_CR1_DISCEN_Msk                           /*!<Discontinuous mode on regular channels               */\r\n#define ADC_CR1_JDISCEN_Pos       (12U)                                        \r\n#define ADC_CR1_JDISCEN_Msk       (0x1U << ADC_CR1_JDISCEN_Pos)                /*!< 0x00001000 */\r\n#define ADC_CR1_JDISCEN           ADC_CR1_JDISCEN_Msk                          /*!<Discontinuous mode on injected channels              */\r\n#define ADC_CR1_DISCNUM_Pos       (13U)                                        \r\n#define ADC_CR1_DISCNUM_Msk       (0x7U << ADC_CR1_DISCNUM_Pos)                /*!< 0x0000E000 */\r\n#define ADC_CR1_DISCNUM           ADC_CR1_DISCNUM_Msk                          /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */\r\n#define ADC_CR1_DISCNUM_0         (0x1U << ADC_CR1_DISCNUM_Pos)                /*!< 0x00002000 */\r\n#define ADC_CR1_DISCNUM_1         (0x2U << ADC_CR1_DISCNUM_Pos)                /*!< 0x00004000 */\r\n#define ADC_CR1_DISCNUM_2         (0x4U << ADC_CR1_DISCNUM_Pos)                /*!< 0x00008000 */\r\n#define ADC_CR1_JAWDEN_Pos        (22U)                                        \r\n#define ADC_CR1_JAWDEN_Msk        (0x1U << ADC_CR1_JAWDEN_Pos)                 /*!< 0x00400000 */\r\n#define ADC_CR1_JAWDEN            ADC_CR1_JAWDEN_Msk                           /*!<Analog watchdog enable on injected channels          */\r\n#define ADC_CR1_AWDEN_Pos         (23U)                                        \r\n#define ADC_CR1_AWDEN_Msk         (0x1U << ADC_CR1_AWDEN_Pos)                  /*!< 0x00800000 */\r\n#define ADC_CR1_AWDEN             ADC_CR1_AWDEN_Msk                            /*!<Analog watchdog enable on regular channels           */\r\n#define ADC_CR1_RES_Pos           (24U)                                        \r\n#define ADC_CR1_RES_Msk           (0x3U << ADC_CR1_RES_Pos)                    /*!< 0x03000000 */\r\n#define ADC_CR1_RES               ADC_CR1_RES_Msk                              /*!<RES[2:0] bits (Resolution)                           */\r\n#define ADC_CR1_RES_0             (0x1U << ADC_CR1_RES_Pos)                    /*!< 0x01000000 */\r\n#define ADC_CR1_RES_1             (0x2U << ADC_CR1_RES_Pos)                    /*!< 0x02000000 */\r\n#define ADC_CR1_OVRIE_Pos         (26U)                                        \r\n#define ADC_CR1_OVRIE_Msk         (0x1U << ADC_CR1_OVRIE_Pos)                  /*!< 0x04000000 */\r\n#define ADC_CR1_OVRIE             ADC_CR1_OVRIE_Msk                            /*!<overrun interrupt enable */\r\n\r\n/*******************  Bit definition for ADC_CR2 register  ********************/\r\n#define ADC_CR2_ADON_Pos          (0U)                                         \r\n#define ADC_CR2_ADON_Msk          (0x1U << ADC_CR2_ADON_Pos)                   /*!< 0x00000001 */\r\n#define ADC_CR2_ADON              ADC_CR2_ADON_Msk                             /*!<A/D Converter ON / OFF                                       */\r\n#define ADC_CR2_CONT_Pos          (1U)                                         \r\n#define ADC_CR2_CONT_Msk          (0x1U << ADC_CR2_CONT_Pos)                   /*!< 0x00000002 */\r\n#define ADC_CR2_CONT              ADC_CR2_CONT_Msk                             /*!<Continuous Conversion                                        */\r\n#define ADC_CR2_DMA_Pos           (8U)                                         \r\n#define ADC_CR2_DMA_Msk           (0x1U << ADC_CR2_DMA_Pos)                    /*!< 0x00000100 */\r\n#define ADC_CR2_DMA               ADC_CR2_DMA_Msk                              /*!<Direct Memory access mode                                    */\r\n#define ADC_CR2_DDS_Pos           (9U)                                         \r\n#define ADC_CR2_DDS_Msk           (0x1U << ADC_CR2_DDS_Pos)                    /*!< 0x00000200 */\r\n#define ADC_CR2_DDS               ADC_CR2_DDS_Msk                              /*!<DMA disable selection (Single ADC)                           */\r\n#define ADC_CR2_EOCS_Pos          (10U)                                        \r\n#define ADC_CR2_EOCS_Msk          (0x1U << ADC_CR2_EOCS_Pos)                   /*!< 0x00000400 */\r\n#define ADC_CR2_EOCS              ADC_CR2_EOCS_Msk                             /*!<End of conversion selection                                  */\r\n#define ADC_CR2_ALIGN_Pos         (11U)                                        \r\n#define ADC_CR2_ALIGN_Msk         (0x1U << ADC_CR2_ALIGN_Pos)                  /*!< 0x00000800 */\r\n#define ADC_CR2_ALIGN             ADC_CR2_ALIGN_Msk                            /*!<Data Alignment                                               */\r\n#define ADC_CR2_JEXTSEL_Pos       (16U)                                        \r\n#define ADC_CR2_JEXTSEL_Msk       (0xFU << ADC_CR2_JEXTSEL_Pos)                /*!< 0x000F0000 */\r\n#define ADC_CR2_JEXTSEL           ADC_CR2_JEXTSEL_Msk                          /*!<JEXTSEL[3:0] bits (External event select for injected group) */\r\n#define ADC_CR2_JEXTSEL_0         (0x1U << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00010000 */\r\n#define ADC_CR2_JEXTSEL_1         (0x2U << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00020000 */\r\n#define ADC_CR2_JEXTSEL_2         (0x4U << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00040000 */\r\n#define ADC_CR2_JEXTSEL_3         (0x8U << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00080000 */\r\n#define ADC_CR2_JEXTEN_Pos        (20U)                                        \r\n#define ADC_CR2_JEXTEN_Msk        (0x3U << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00300000 */\r\n#define ADC_CR2_JEXTEN            ADC_CR2_JEXTEN_Msk                           /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */\r\n#define ADC_CR2_JEXTEN_0          (0x1U << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00100000 */\r\n#define ADC_CR2_JEXTEN_1          (0x2U << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00200000 */\r\n#define ADC_CR2_JSWSTART_Pos      (22U)                                        \r\n#define ADC_CR2_JSWSTART_Msk      (0x1U << ADC_CR2_JSWSTART_Pos)               /*!< 0x00400000 */\r\n#define ADC_CR2_JSWSTART          ADC_CR2_JSWSTART_Msk                         /*!<Start Conversion of injected channels */\r\n#define ADC_CR2_EXTSEL_Pos        (24U)                                        \r\n#define ADC_CR2_EXTSEL_Msk        (0xFU << ADC_CR2_EXTSEL_Pos)                 /*!< 0x0F000000 */\r\n#define ADC_CR2_EXTSEL            ADC_CR2_EXTSEL_Msk                           /*!<EXTSEL[3:0] bits (External Event Select for regular group) */\r\n#define ADC_CR2_EXTSEL_0          (0x1U << ADC_CR2_EXTSEL_Pos)                 /*!< 0x01000000 */\r\n#define ADC_CR2_EXTSEL_1          (0x2U << ADC_CR2_EXTSEL_Pos)                 /*!< 0x02000000 */\r\n#define ADC_CR2_EXTSEL_2          (0x4U << ADC_CR2_EXTSEL_Pos)                 /*!< 0x04000000 */\r\n#define ADC_CR2_EXTSEL_3          (0x8U << ADC_CR2_EXTSEL_Pos)                 /*!< 0x08000000 */\r\n#define ADC_CR2_EXTEN_Pos         (28U)                                        \r\n#define ADC_CR2_EXTEN_Msk         (0x3U << ADC_CR2_EXTEN_Pos)                  /*!< 0x30000000 */\r\n#define ADC_CR2_EXTEN             ADC_CR2_EXTEN_Msk                            /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */\r\n#define ADC_CR2_EXTEN_0           (0x1U << ADC_CR2_EXTEN_Pos)                  /*!< 0x10000000 */\r\n#define ADC_CR2_EXTEN_1           (0x2U << ADC_CR2_EXTEN_Pos)                  /*!< 0x20000000 */\r\n#define ADC_CR2_SWSTART_Pos       (30U)                                        \r\n#define ADC_CR2_SWSTART_Msk       (0x1U << ADC_CR2_SWSTART_Pos)                /*!< 0x40000000 */\r\n#define ADC_CR2_SWSTART           ADC_CR2_SWSTART_Msk                          /*!<Start Conversion of regular channels */\r\n\r\n/******************  Bit definition for ADC_SMPR1 register  *******************/\r\n#define ADC_SMPR1_SMP10_Pos       (0U)                                         \r\n#define ADC_SMPR1_SMP10_Msk       (0x7U << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000007 */\r\n#define ADC_SMPR1_SMP10           ADC_SMPR1_SMP10_Msk                          /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */\r\n#define ADC_SMPR1_SMP10_0         (0x1U << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000001 */\r\n#define ADC_SMPR1_SMP10_1         (0x2U << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000002 */\r\n#define ADC_SMPR1_SMP10_2         (0x4U << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000004 */\r\n#define ADC_SMPR1_SMP11_Pos       (3U)                                         \r\n#define ADC_SMPR1_SMP11_Msk       (0x7U << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000038 */\r\n#define ADC_SMPR1_SMP11           ADC_SMPR1_SMP11_Msk                          /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */\r\n#define ADC_SMPR1_SMP11_0         (0x1U << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000008 */\r\n#define ADC_SMPR1_SMP11_1         (0x2U << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000010 */\r\n#define ADC_SMPR1_SMP11_2         (0x4U << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000020 */\r\n#define ADC_SMPR1_SMP12_Pos       (6U)                                         \r\n#define ADC_SMPR1_SMP12_Msk       (0x7U << ADC_SMPR1_SMP12_Pos)                /*!< 0x000001C0 */\r\n#define ADC_SMPR1_SMP12           ADC_SMPR1_SMP12_Msk                          /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */\r\n#define ADC_SMPR1_SMP12_0         (0x1U << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000040 */\r\n#define ADC_SMPR1_SMP12_1         (0x2U << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000080 */\r\n#define ADC_SMPR1_SMP12_2         (0x4U << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000100 */\r\n#define ADC_SMPR1_SMP13_Pos       (9U)                                         \r\n#define ADC_SMPR1_SMP13_Msk       (0x7U << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000E00 */\r\n#define ADC_SMPR1_SMP13           ADC_SMPR1_SMP13_Msk                          /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */\r\n#define ADC_SMPR1_SMP13_0         (0x1U << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000200 */\r\n#define ADC_SMPR1_SMP13_1         (0x2U << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000400 */\r\n#define ADC_SMPR1_SMP13_2         (0x4U << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000800 */\r\n#define ADC_SMPR1_SMP14_Pos       (12U)                                        \r\n#define ADC_SMPR1_SMP14_Msk       (0x7U << ADC_SMPR1_SMP14_Pos)                /*!< 0x00007000 */\r\n#define ADC_SMPR1_SMP14           ADC_SMPR1_SMP14_Msk                          /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */\r\n#define ADC_SMPR1_SMP14_0         (0x1U << ADC_SMPR1_SMP14_Pos)                /*!< 0x00001000 */\r\n#define ADC_SMPR1_SMP14_1         (0x2U << ADC_SMPR1_SMP14_Pos)                /*!< 0x00002000 */\r\n#define ADC_SMPR1_SMP14_2         (0x4U << ADC_SMPR1_SMP14_Pos)                /*!< 0x00004000 */\r\n#define ADC_SMPR1_SMP15_Pos       (15U)                                        \r\n#define ADC_SMPR1_SMP15_Msk       (0x7U << ADC_SMPR1_SMP15_Pos)                /*!< 0x00038000 */\r\n#define ADC_SMPR1_SMP15           ADC_SMPR1_SMP15_Msk                          /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */\r\n#define ADC_SMPR1_SMP15_0         (0x1U << ADC_SMPR1_SMP15_Pos)                /*!< 0x00008000 */\r\n#define ADC_SMPR1_SMP15_1         (0x2U << ADC_SMPR1_SMP15_Pos)                /*!< 0x00010000 */\r\n#define ADC_SMPR1_SMP15_2         (0x4U << ADC_SMPR1_SMP15_Pos)                /*!< 0x00020000 */\r\n#define ADC_SMPR1_SMP16_Pos       (18U)                                        \r\n#define ADC_SMPR1_SMP16_Msk       (0x7U << ADC_SMPR1_SMP16_Pos)                /*!< 0x001C0000 */\r\n#define ADC_SMPR1_SMP16           ADC_SMPR1_SMP16_Msk                          /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */\r\n#define ADC_SMPR1_SMP16_0         (0x1U << ADC_SMPR1_SMP16_Pos)                /*!< 0x00040000 */\r\n#define ADC_SMPR1_SMP16_1         (0x2U << ADC_SMPR1_SMP16_Pos)                /*!< 0x00080000 */\r\n#define ADC_SMPR1_SMP16_2         (0x4U << ADC_SMPR1_SMP16_Pos)                /*!< 0x00100000 */\r\n#define ADC_SMPR1_SMP17_Pos       (21U)                                        \r\n#define ADC_SMPR1_SMP17_Msk       (0x7U << ADC_SMPR1_SMP17_Pos)                /*!< 0x00E00000 */\r\n#define ADC_SMPR1_SMP17           ADC_SMPR1_SMP17_Msk                          /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */\r\n#define ADC_SMPR1_SMP17_0         (0x1U << ADC_SMPR1_SMP17_Pos)                /*!< 0x00200000 */\r\n#define ADC_SMPR1_SMP17_1         (0x2U << ADC_SMPR1_SMP17_Pos)                /*!< 0x00400000 */\r\n#define ADC_SMPR1_SMP17_2         (0x4U << ADC_SMPR1_SMP17_Pos)                /*!< 0x00800000 */\r\n#define ADC_SMPR1_SMP18_Pos       (24U)                                        \r\n#define ADC_SMPR1_SMP18_Msk       (0x7U << ADC_SMPR1_SMP18_Pos)                /*!< 0x07000000 */\r\n#define ADC_SMPR1_SMP18           ADC_SMPR1_SMP18_Msk                          /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */\r\n#define ADC_SMPR1_SMP18_0         (0x1U << ADC_SMPR1_SMP18_Pos)                /*!< 0x01000000 */\r\n#define ADC_SMPR1_SMP18_1         (0x2U << ADC_SMPR1_SMP18_Pos)                /*!< 0x02000000 */\r\n#define ADC_SMPR1_SMP18_2         (0x4U << ADC_SMPR1_SMP18_Pos)                /*!< 0x04000000 */\r\n\r\n/******************  Bit definition for ADC_SMPR2 register  *******************/\r\n#define ADC_SMPR2_SMP0_Pos        (0U)                                         \r\n#define ADC_SMPR2_SMP0_Msk        (0x7U << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000007 */\r\n#define ADC_SMPR2_SMP0            ADC_SMPR2_SMP0_Msk                           /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */\r\n#define ADC_SMPR2_SMP0_0          (0x1U << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000001 */\r\n#define ADC_SMPR2_SMP0_1          (0x2U << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000002 */\r\n#define ADC_SMPR2_SMP0_2          (0x4U << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000004 */\r\n#define ADC_SMPR2_SMP1_Pos        (3U)                                         \r\n#define ADC_SMPR2_SMP1_Msk        (0x7U << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000038 */\r\n#define ADC_SMPR2_SMP1            ADC_SMPR2_SMP1_Msk                           /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */\r\n#define ADC_SMPR2_SMP1_0          (0x1U << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000008 */\r\n#define ADC_SMPR2_SMP1_1          (0x2U << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000010 */\r\n#define ADC_SMPR2_SMP1_2          (0x4U << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000020 */\r\n#define ADC_SMPR2_SMP2_Pos        (6U)                                         \r\n#define ADC_SMPR2_SMP2_Msk        (0x7U << ADC_SMPR2_SMP2_Pos)                 /*!< 0x000001C0 */\r\n#define ADC_SMPR2_SMP2            ADC_SMPR2_SMP2_Msk                           /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */\r\n#define ADC_SMPR2_SMP2_0          (0x1U << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000040 */\r\n#define ADC_SMPR2_SMP2_1          (0x2U << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000080 */\r\n#define ADC_SMPR2_SMP2_2          (0x4U << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000100 */\r\n#define ADC_SMPR2_SMP3_Pos        (9U)                                         \r\n#define ADC_SMPR2_SMP3_Msk        (0x7U << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000E00 */\r\n#define ADC_SMPR2_SMP3            ADC_SMPR2_SMP3_Msk                           /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */\r\n#define ADC_SMPR2_SMP3_0          (0x1U << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000200 */\r\n#define ADC_SMPR2_SMP3_1          (0x2U << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000400 */\r\n#define ADC_SMPR2_SMP3_2          (0x4U << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000800 */\r\n#define ADC_SMPR2_SMP4_Pos        (12U)                                        \r\n#define ADC_SMPR2_SMP4_Msk        (0x7U << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00007000 */\r\n#define ADC_SMPR2_SMP4            ADC_SMPR2_SMP4_Msk                           /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */\r\n#define ADC_SMPR2_SMP4_0          (0x1U << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00001000 */\r\n#define ADC_SMPR2_SMP4_1          (0x2U << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00002000 */\r\n#define ADC_SMPR2_SMP4_2          (0x4U << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00004000 */\r\n#define ADC_SMPR2_SMP5_Pos        (15U)                                        \r\n#define ADC_SMPR2_SMP5_Msk        (0x7U << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00038000 */\r\n#define ADC_SMPR2_SMP5            ADC_SMPR2_SMP5_Msk                           /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */\r\n#define ADC_SMPR2_SMP5_0          (0x1U << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00008000 */\r\n#define ADC_SMPR2_SMP5_1          (0x2U << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00010000 */\r\n#define ADC_SMPR2_SMP5_2          (0x4U << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00020000 */\r\n#define ADC_SMPR2_SMP6_Pos        (18U)                                        \r\n#define ADC_SMPR2_SMP6_Msk        (0x7U << ADC_SMPR2_SMP6_Pos)                 /*!< 0x001C0000 */\r\n#define ADC_SMPR2_SMP6            ADC_SMPR2_SMP6_Msk                           /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */\r\n#define ADC_SMPR2_SMP6_0          (0x1U << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00040000 */\r\n#define ADC_SMPR2_SMP6_1          (0x2U << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00080000 */\r\n#define ADC_SMPR2_SMP6_2          (0x4U << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00100000 */\r\n#define ADC_SMPR2_SMP7_Pos        (21U)                                        \r\n#define ADC_SMPR2_SMP7_Msk        (0x7U << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00E00000 */\r\n#define ADC_SMPR2_SMP7            ADC_SMPR2_SMP7_Msk                           /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */\r\n#define ADC_SMPR2_SMP7_0          (0x1U << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00200000 */\r\n#define ADC_SMPR2_SMP7_1          (0x2U << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00400000 */\r\n#define ADC_SMPR2_SMP7_2          (0x4U << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00800000 */\r\n#define ADC_SMPR2_SMP8_Pos        (24U)                                        \r\n#define ADC_SMPR2_SMP8_Msk        (0x7U << ADC_SMPR2_SMP8_Pos)                 /*!< 0x07000000 */\r\n#define ADC_SMPR2_SMP8            ADC_SMPR2_SMP8_Msk                           /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */\r\n#define ADC_SMPR2_SMP8_0          (0x1U << ADC_SMPR2_SMP8_Pos)                 /*!< 0x01000000 */\r\n#define ADC_SMPR2_SMP8_1          (0x2U << ADC_SMPR2_SMP8_Pos)                 /*!< 0x02000000 */\r\n#define ADC_SMPR2_SMP8_2          (0x4U << ADC_SMPR2_SMP8_Pos)                 /*!< 0x04000000 */\r\n#define ADC_SMPR2_SMP9_Pos        (27U)                                        \r\n#define ADC_SMPR2_SMP9_Msk        (0x7U << ADC_SMPR2_SMP9_Pos)                 /*!< 0x38000000 */\r\n#define ADC_SMPR2_SMP9            ADC_SMPR2_SMP9_Msk                           /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */\r\n#define ADC_SMPR2_SMP9_0          (0x1U << ADC_SMPR2_SMP9_Pos)                 /*!< 0x08000000 */\r\n#define ADC_SMPR2_SMP9_1          (0x2U << ADC_SMPR2_SMP9_Pos)                 /*!< 0x10000000 */\r\n#define ADC_SMPR2_SMP9_2          (0x4U << ADC_SMPR2_SMP9_Pos)                 /*!< 0x20000000 */\r\n\r\n/******************  Bit definition for ADC_JOFR1 register  *******************/\r\n#define ADC_JOFR1_JOFFSET1_Pos    (0U)                                         \r\n#define ADC_JOFR1_JOFFSET1_Msk    (0xFFFU << ADC_JOFR1_JOFFSET1_Pos)           /*!< 0x00000FFF */\r\n#define ADC_JOFR1_JOFFSET1        ADC_JOFR1_JOFFSET1_Msk                       /*!<Data offset for injected channel 1 */\r\n\r\n/******************  Bit definition for ADC_JOFR2 register  *******************/\r\n#define ADC_JOFR2_JOFFSET2_Pos    (0U)                                         \r\n#define ADC_JOFR2_JOFFSET2_Msk    (0xFFFU << ADC_JOFR2_JOFFSET2_Pos)           /*!< 0x00000FFF */\r\n#define ADC_JOFR2_JOFFSET2        ADC_JOFR2_JOFFSET2_Msk                       /*!<Data offset for injected channel 2 */\r\n\r\n/******************  Bit definition for ADC_JOFR3 register  *******************/\r\n#define ADC_JOFR3_JOFFSET3_Pos    (0U)                                         \r\n#define ADC_JOFR3_JOFFSET3_Msk    (0xFFFU << ADC_JOFR3_JOFFSET3_Pos)           /*!< 0x00000FFF */\r\n#define ADC_JOFR3_JOFFSET3        ADC_JOFR3_JOFFSET3_Msk                       /*!<Data offset for injected channel 3 */\r\n\r\n/******************  Bit definition for ADC_JOFR4 register  *******************/\r\n#define ADC_JOFR4_JOFFSET4_Pos    (0U)                                         \r\n#define ADC_JOFR4_JOFFSET4_Msk    (0xFFFU << ADC_JOFR4_JOFFSET4_Pos)           /*!< 0x00000FFF */\r\n#define ADC_JOFR4_JOFFSET4        ADC_JOFR4_JOFFSET4_Msk                       /*!<Data offset for injected channel 4 */\r\n\r\n/*******************  Bit definition for ADC_HTR register  ********************/\r\n#define ADC_HTR_HT_Pos            (0U)                                         \r\n#define ADC_HTR_HT_Msk            (0xFFFU << ADC_HTR_HT_Pos)                   /*!< 0x00000FFF */\r\n#define ADC_HTR_HT                ADC_HTR_HT_Msk                               /*!<Analog watchdog high threshold */\r\n\r\n/*******************  Bit definition for ADC_LTR register  ********************/\r\n#define ADC_LTR_LT_Pos            (0U)                                         \r\n#define ADC_LTR_LT_Msk            (0xFFFU << ADC_LTR_LT_Pos)                   /*!< 0x00000FFF */\r\n#define ADC_LTR_LT                ADC_LTR_LT_Msk                               /*!<Analog watchdog low threshold */\r\n\r\n/*******************  Bit definition for ADC_SQR1 register  *******************/\r\n#define ADC_SQR1_SQ13_Pos         (0U)                                         \r\n#define ADC_SQR1_SQ13_Msk         (0x1FU << ADC_SQR1_SQ13_Pos)                 /*!< 0x0000001F */\r\n#define ADC_SQR1_SQ13             ADC_SQR1_SQ13_Msk                            /*!<SQ13[4:0] bits (13th conversion in regular sequence) */\r\n#define ADC_SQR1_SQ13_0           (0x01U << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000001 */\r\n#define ADC_SQR1_SQ13_1           (0x02U << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000002 */\r\n#define ADC_SQR1_SQ13_2           (0x04U << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000004 */\r\n#define ADC_SQR1_SQ13_3           (0x08U << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000008 */\r\n#define ADC_SQR1_SQ13_4           (0x10U << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000010 */\r\n#define ADC_SQR1_SQ14_Pos         (5U)                                         \r\n#define ADC_SQR1_SQ14_Msk         (0x1FU << ADC_SQR1_SQ14_Pos)                 /*!< 0x000003E0 */\r\n#define ADC_SQR1_SQ14             ADC_SQR1_SQ14_Msk                            /*!<SQ14[4:0] bits (14th conversion in regular sequence) */\r\n#define ADC_SQR1_SQ14_0           (0x01U << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000020 */\r\n#define ADC_SQR1_SQ14_1           (0x02U << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000040 */\r\n#define ADC_SQR1_SQ14_2           (0x04U << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000080 */\r\n#define ADC_SQR1_SQ14_3           (0x08U << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000100 */\r\n#define ADC_SQR1_SQ14_4           (0x10U << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000200 */\r\n#define ADC_SQR1_SQ15_Pos         (10U)                                        \r\n#define ADC_SQR1_SQ15_Msk         (0x1FU << ADC_SQR1_SQ15_Pos)                 /*!< 0x00007C00 */\r\n#define ADC_SQR1_SQ15             ADC_SQR1_SQ15_Msk                            /*!<SQ15[4:0] bits (15th conversion in regular sequence) */\r\n#define ADC_SQR1_SQ15_0           (0x01U << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000400 */\r\n#define ADC_SQR1_SQ15_1           (0x02U << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000800 */\r\n#define ADC_SQR1_SQ15_2           (0x04U << ADC_SQR1_SQ15_Pos)                 /*!< 0x00001000 */\r\n#define ADC_SQR1_SQ15_3           (0x08U << ADC_SQR1_SQ15_Pos)                 /*!< 0x00002000 */\r\n#define ADC_SQR1_SQ15_4           (0x10U << ADC_SQR1_SQ15_Pos)                 /*!< 0x00004000 */\r\n#define ADC_SQR1_SQ16_Pos         (15U)                                        \r\n#define ADC_SQR1_SQ16_Msk         (0x1FU << ADC_SQR1_SQ16_Pos)                 /*!< 0x000F8000 */\r\n#define ADC_SQR1_SQ16             ADC_SQR1_SQ16_Msk                            /*!<SQ16[4:0] bits (16th conversion in regular sequence) */\r\n#define ADC_SQR1_SQ16_0           (0x01U << ADC_SQR1_SQ16_Pos)                 /*!< 0x00008000 */\r\n#define ADC_SQR1_SQ16_1           (0x02U << ADC_SQR1_SQ16_Pos)                 /*!< 0x00010000 */\r\n#define ADC_SQR1_SQ16_2           (0x04U << ADC_SQR1_SQ16_Pos)                 /*!< 0x00020000 */\r\n#define ADC_SQR1_SQ16_3           (0x08U << ADC_SQR1_SQ16_Pos)                 /*!< 0x00040000 */\r\n#define ADC_SQR1_SQ16_4           (0x10U << ADC_SQR1_SQ16_Pos)                 /*!< 0x00080000 */\r\n#define ADC_SQR1_L_Pos            (20U)                                        \r\n#define ADC_SQR1_L_Msk            (0xFU << ADC_SQR1_L_Pos)                     /*!< 0x00F00000 */\r\n#define ADC_SQR1_L                ADC_SQR1_L_Msk                               /*!<L[3:0] bits (Regular channel sequence length) */\r\n#define ADC_SQR1_L_0              (0x1U << ADC_SQR1_L_Pos)                     /*!< 0x00100000 */\r\n#define ADC_SQR1_L_1              (0x2U << ADC_SQR1_L_Pos)                     /*!< 0x00200000 */\r\n#define ADC_SQR1_L_2              (0x4U << ADC_SQR1_L_Pos)                     /*!< 0x00400000 */\r\n#define ADC_SQR1_L_3              (0x8U << ADC_SQR1_L_Pos)                     /*!< 0x00800000 */\r\n\r\n/*******************  Bit definition for ADC_SQR2 register  *******************/\r\n#define ADC_SQR2_SQ7_Pos          (0U)                                         \r\n#define ADC_SQR2_SQ7_Msk          (0x1FU << ADC_SQR2_SQ7_Pos)                  /*!< 0x0000001F */\r\n#define ADC_SQR2_SQ7              ADC_SQR2_SQ7_Msk                             /*!<SQ7[4:0] bits (7th conversion in regular sequence) */\r\n#define ADC_SQR2_SQ7_0            (0x01U << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000001 */\r\n#define ADC_SQR2_SQ7_1            (0x02U << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000002 */\r\n#define ADC_SQR2_SQ7_2            (0x04U << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000004 */\r\n#define ADC_SQR2_SQ7_3            (0x08U << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000008 */\r\n#define ADC_SQR2_SQ7_4            (0x10U << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000010 */\r\n#define ADC_SQR2_SQ8_Pos          (5U)                                         \r\n#define ADC_SQR2_SQ8_Msk          (0x1FU << ADC_SQR2_SQ8_Pos)                  /*!< 0x000003E0 */\r\n#define ADC_SQR2_SQ8              ADC_SQR2_SQ8_Msk                             /*!<SQ8[4:0] bits (8th conversion in regular sequence) */\r\n#define ADC_SQR2_SQ8_0            (0x01U << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000020 */\r\n#define ADC_SQR2_SQ8_1            (0x02U << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000040 */\r\n#define ADC_SQR2_SQ8_2            (0x04U << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000080 */\r\n#define ADC_SQR2_SQ8_3            (0x08U << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000100 */\r\n#define ADC_SQR2_SQ8_4            (0x10U << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000200 */\r\n#define ADC_SQR2_SQ9_Pos          (10U)                                        \r\n#define ADC_SQR2_SQ9_Msk          (0x1FU << ADC_SQR2_SQ9_Pos)                  /*!< 0x00007C00 */\r\n#define ADC_SQR2_SQ9              ADC_SQR2_SQ9_Msk                             /*!<SQ9[4:0] bits (9th conversion in regular sequence) */\r\n#define ADC_SQR2_SQ9_0            (0x01U << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000400 */\r\n#define ADC_SQR2_SQ9_1            (0x02U << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000800 */\r\n#define ADC_SQR2_SQ9_2            (0x04U << ADC_SQR2_SQ9_Pos)                  /*!< 0x00001000 */\r\n#define ADC_SQR2_SQ9_3            (0x08U << ADC_SQR2_SQ9_Pos)                  /*!< 0x00002000 */\r\n#define ADC_SQR2_SQ9_4            (0x10U << ADC_SQR2_SQ9_Pos)                  /*!< 0x00004000 */\r\n#define ADC_SQR2_SQ10_Pos         (15U)                                        \r\n#define ADC_SQR2_SQ10_Msk         (0x1FU << ADC_SQR2_SQ10_Pos)                 /*!< 0x000F8000 */\r\n#define ADC_SQR2_SQ10             ADC_SQR2_SQ10_Msk                            /*!<SQ10[4:0] bits (10th conversion in regular sequence) */\r\n#define ADC_SQR2_SQ10_0           (0x01U << ADC_SQR2_SQ10_Pos)                 /*!< 0x00008000 */\r\n#define ADC_SQR2_SQ10_1           (0x02U << ADC_SQR2_SQ10_Pos)                 /*!< 0x00010000 */\r\n#define ADC_SQR2_SQ10_2           (0x04U << ADC_SQR2_SQ10_Pos)                 /*!< 0x00020000 */\r\n#define ADC_SQR2_SQ10_3           (0x08U << ADC_SQR2_SQ10_Pos)                 /*!< 0x00040000 */\r\n#define ADC_SQR2_SQ10_4           (0x10U << ADC_SQR2_SQ10_Pos)                 /*!< 0x00080000 */\r\n#define ADC_SQR2_SQ11_Pos         (20U)                                        \r\n#define ADC_SQR2_SQ11_Msk         (0x1FU << ADC_SQR2_SQ11_Pos)                 /*!< 0x01F00000 */\r\n#define ADC_SQR2_SQ11             ADC_SQR2_SQ11_Msk                            /*!<SQ11[4:0] bits (11th conversion in regular sequence) */\r\n#define ADC_SQR2_SQ11_0           (0x01U << ADC_SQR2_SQ11_Pos)                 /*!< 0x00100000 */\r\n#define ADC_SQR2_SQ11_1           (0x02U << ADC_SQR2_SQ11_Pos)                 /*!< 0x00200000 */\r\n#define ADC_SQR2_SQ11_2           (0x04U << ADC_SQR2_SQ11_Pos)                 /*!< 0x00400000 */\r\n#define ADC_SQR2_SQ11_3           (0x08U << ADC_SQR2_SQ11_Pos)                 /*!< 0x00800000 */\r\n#define ADC_SQR2_SQ11_4           (0x10U << ADC_SQR2_SQ11_Pos)                 /*!< 0x01000000 */\r\n#define ADC_SQR2_SQ12_Pos         (25U)                                        \r\n#define ADC_SQR2_SQ12_Msk         (0x1FU << ADC_SQR2_SQ12_Pos)                 /*!< 0x3E000000 */\r\n#define ADC_SQR2_SQ12             ADC_SQR2_SQ12_Msk                            /*!<SQ12[4:0] bits (12th conversion in regular sequence) */\r\n#define ADC_SQR2_SQ12_0           (0x01U << ADC_SQR2_SQ12_Pos)                 /*!< 0x02000000 */\r\n#define ADC_SQR2_SQ12_1           (0x02U << ADC_SQR2_SQ12_Pos)                 /*!< 0x04000000 */\r\n#define ADC_SQR2_SQ12_2           (0x04U << ADC_SQR2_SQ12_Pos)                 /*!< 0x08000000 */\r\n#define ADC_SQR2_SQ12_3           (0x08U << ADC_SQR2_SQ12_Pos)                 /*!< 0x10000000 */\r\n#define ADC_SQR2_SQ12_4           (0x10U << ADC_SQR2_SQ12_Pos)                 /*!< 0x20000000 */\r\n\r\n/*******************  Bit definition for ADC_SQR3 register  *******************/\r\n#define ADC_SQR3_SQ1_Pos          (0U)                                         \r\n#define ADC_SQR3_SQ1_Msk          (0x1FU << ADC_SQR3_SQ1_Pos)                  /*!< 0x0000001F */\r\n#define ADC_SQR3_SQ1              ADC_SQR3_SQ1_Msk                             /*!<SQ1[4:0] bits (1st conversion in regular sequence) */\r\n#define ADC_SQR3_SQ1_0            (0x01U << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000001 */\r\n#define ADC_SQR3_SQ1_1            (0x02U << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000002 */\r\n#define ADC_SQR3_SQ1_2            (0x04U << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000004 */\r\n#define ADC_SQR3_SQ1_3            (0x08U << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000008 */\r\n#define ADC_SQR3_SQ1_4            (0x10U << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000010 */\r\n#define ADC_SQR3_SQ2_Pos          (5U)                                         \r\n#define ADC_SQR3_SQ2_Msk          (0x1FU << ADC_SQR3_SQ2_Pos)                  /*!< 0x000003E0 */\r\n#define ADC_SQR3_SQ2              ADC_SQR3_SQ2_Msk                             /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */\r\n#define ADC_SQR3_SQ2_0            (0x01U << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000020 */\r\n#define ADC_SQR3_SQ2_1            (0x02U << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000040 */\r\n#define ADC_SQR3_SQ2_2            (0x04U << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000080 */\r\n#define ADC_SQR3_SQ2_3            (0x08U << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000100 */\r\n#define ADC_SQR3_SQ2_4            (0x10U << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000200 */\r\n#define ADC_SQR3_SQ3_Pos          (10U)                                        \r\n#define ADC_SQR3_SQ3_Msk          (0x1FU << ADC_SQR3_SQ3_Pos)                  /*!< 0x00007C00 */\r\n#define ADC_SQR3_SQ3              ADC_SQR3_SQ3_Msk                             /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */\r\n#define ADC_SQR3_SQ3_0            (0x01U << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000400 */\r\n#define ADC_SQR3_SQ3_1            (0x02U << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000800 */\r\n#define ADC_SQR3_SQ3_2            (0x04U << ADC_SQR3_SQ3_Pos)                  /*!< 0x00001000 */\r\n#define ADC_SQR3_SQ3_3            (0x08U << ADC_SQR3_SQ3_Pos)                  /*!< 0x00002000 */\r\n#define ADC_SQR3_SQ3_4            (0x10U << ADC_SQR3_SQ3_Pos)                  /*!< 0x00004000 */\r\n#define ADC_SQR3_SQ4_Pos          (15U)                                        \r\n#define ADC_SQR3_SQ4_Msk          (0x1FU << ADC_SQR3_SQ4_Pos)                  /*!< 0x000F8000 */\r\n#define ADC_SQR3_SQ4              ADC_SQR3_SQ4_Msk                             /*!<SQ4[4:0] bits (4th conversion in regular sequence) */\r\n#define ADC_SQR3_SQ4_0            (0x01U << ADC_SQR3_SQ4_Pos)                  /*!< 0x00008000 */\r\n#define ADC_SQR3_SQ4_1            (0x02U << ADC_SQR3_SQ4_Pos)                  /*!< 0x00010000 */\r\n#define ADC_SQR3_SQ4_2            (0x04U << ADC_SQR3_SQ4_Pos)                  /*!< 0x00020000 */\r\n#define ADC_SQR3_SQ4_3            (0x08U << ADC_SQR3_SQ4_Pos)                  /*!< 0x00040000 */\r\n#define ADC_SQR3_SQ4_4            (0x10U << ADC_SQR3_SQ4_Pos)                  /*!< 0x00080000 */\r\n#define ADC_SQR3_SQ5_Pos          (20U)                                        \r\n#define ADC_SQR3_SQ5_Msk          (0x1FU << ADC_SQR3_SQ5_Pos)                  /*!< 0x01F00000 */\r\n#define ADC_SQR3_SQ5              ADC_SQR3_SQ5_Msk                             /*!<SQ5[4:0] bits (5th conversion in regular sequence) */\r\n#define ADC_SQR3_SQ5_0            (0x01U << ADC_SQR3_SQ5_Pos)                  /*!< 0x00100000 */\r\n#define ADC_SQR3_SQ5_1            (0x02U << ADC_SQR3_SQ5_Pos)                  /*!< 0x00200000 */\r\n#define ADC_SQR3_SQ5_2            (0x04U << ADC_SQR3_SQ5_Pos)                  /*!< 0x00400000 */\r\n#define ADC_SQR3_SQ5_3            (0x08U << ADC_SQR3_SQ5_Pos)                  /*!< 0x00800000 */\r\n#define ADC_SQR3_SQ5_4            (0x10U << ADC_SQR3_SQ5_Pos)                  /*!< 0x01000000 */\r\n#define ADC_SQR3_SQ6_Pos          (25U)                                        \r\n#define ADC_SQR3_SQ6_Msk          (0x1FU << ADC_SQR3_SQ6_Pos)                  /*!< 0x3E000000 */\r\n#define ADC_SQR3_SQ6              ADC_SQR3_SQ6_Msk                             /*!<SQ6[4:0] bits (6th conversion in regular sequence) */\r\n#define ADC_SQR3_SQ6_0            (0x01U << ADC_SQR3_SQ6_Pos)                  /*!< 0x02000000 */\r\n#define ADC_SQR3_SQ6_1            (0x02U << ADC_SQR3_SQ6_Pos)                  /*!< 0x04000000 */\r\n#define ADC_SQR3_SQ6_2            (0x04U << ADC_SQR3_SQ6_Pos)                  /*!< 0x08000000 */\r\n#define ADC_SQR3_SQ6_3            (0x08U << ADC_SQR3_SQ6_Pos)                  /*!< 0x10000000 */\r\n#define ADC_SQR3_SQ6_4            (0x10U << ADC_SQR3_SQ6_Pos)                  /*!< 0x20000000 */\r\n\r\n/*******************  Bit definition for ADC_JSQR register  *******************/\r\n#define ADC_JSQR_JSQ1_Pos         (0U)                                         \r\n#define ADC_JSQR_JSQ1_Msk         (0x1FU << ADC_JSQR_JSQ1_Pos)                 /*!< 0x0000001F */\r\n#define ADC_JSQR_JSQ1             ADC_JSQR_JSQ1_Msk                            /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */\r\n#define ADC_JSQR_JSQ1_0           (0x01U << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000001 */\r\n#define ADC_JSQR_JSQ1_1           (0x02U << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000002 */\r\n#define ADC_JSQR_JSQ1_2           (0x04U << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000004 */\r\n#define ADC_JSQR_JSQ1_3           (0x08U << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000008 */\r\n#define ADC_JSQR_JSQ1_4           (0x10U << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000010 */\r\n#define ADC_JSQR_JSQ2_Pos         (5U)                                         \r\n#define ADC_JSQR_JSQ2_Msk         (0x1FU << ADC_JSQR_JSQ2_Pos)                 /*!< 0x000003E0 */\r\n#define ADC_JSQR_JSQ2             ADC_JSQR_JSQ2_Msk                            /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */\r\n#define ADC_JSQR_JSQ2_0           (0x01U << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000020 */\r\n#define ADC_JSQR_JSQ2_1           (0x02U << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000040 */\r\n#define ADC_JSQR_JSQ2_2           (0x04U << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000080 */\r\n#define ADC_JSQR_JSQ2_3           (0x08U << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000100 */\r\n#define ADC_JSQR_JSQ2_4           (0x10U << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000200 */\r\n#define ADC_JSQR_JSQ3_Pos         (10U)                                        \r\n#define ADC_JSQR_JSQ3_Msk         (0x1FU << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00007C00 */\r\n#define ADC_JSQR_JSQ3             ADC_JSQR_JSQ3_Msk                            /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */\r\n#define ADC_JSQR_JSQ3_0           (0x01U << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000400 */\r\n#define ADC_JSQR_JSQ3_1           (0x02U << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000800 */\r\n#define ADC_JSQR_JSQ3_2           (0x04U << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00001000 */\r\n#define ADC_JSQR_JSQ3_3           (0x08U << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00002000 */\r\n#define ADC_JSQR_JSQ3_4           (0x10U << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00004000 */\r\n#define ADC_JSQR_JSQ4_Pos         (15U)                                        \r\n#define ADC_JSQR_JSQ4_Msk         (0x1FU << ADC_JSQR_JSQ4_Pos)                 /*!< 0x000F8000 */\r\n#define ADC_JSQR_JSQ4             ADC_JSQR_JSQ4_Msk                            /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */\r\n#define ADC_JSQR_JSQ4_0           (0x01U << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00008000 */\r\n#define ADC_JSQR_JSQ4_1           (0x02U << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00010000 */\r\n#define ADC_JSQR_JSQ4_2           (0x04U << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00020000 */\r\n#define ADC_JSQR_JSQ4_3           (0x08U << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00040000 */\r\n#define ADC_JSQR_JSQ4_4           (0x10U << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00080000 */\r\n#define ADC_JSQR_JL_Pos           (20U)                                        \r\n#define ADC_JSQR_JL_Msk           (0x3U << ADC_JSQR_JL_Pos)                    /*!< 0x00300000 */\r\n#define ADC_JSQR_JL               ADC_JSQR_JL_Msk                              /*!<JL[1:0] bits (Injected Sequence length) */\r\n#define ADC_JSQR_JL_0             (0x1U << ADC_JSQR_JL_Pos)                    /*!< 0x00100000 */\r\n#define ADC_JSQR_JL_1             (0x2U << ADC_JSQR_JL_Pos)                    /*!< 0x00200000 */\r\n\r\n/*******************  Bit definition for ADC_JDR1 register  *******************/\r\n#define ADC_JDR1_JDATA            ((uint16_t)0xFFFFU)                          /*!<Injected data */\r\n\r\n/*******************  Bit definition for ADC_JDR2 register  *******************/\r\n#define ADC_JDR2_JDATA            ((uint16_t)0xFFFFU)                          /*!<Injected data */\r\n\r\n/*******************  Bit definition for ADC_JDR3 register  *******************/\r\n#define ADC_JDR3_JDATA            ((uint16_t)0xFFFFU)                          /*!<Injected data */\r\n\r\n/*******************  Bit definition for ADC_JDR4 register  *******************/\r\n#define ADC_JDR4_JDATA            ((uint16_t)0xFFFFU)                          /*!<Injected data */\r\n\r\n/********************  Bit definition for ADC_DR register  ********************/\r\n#define ADC_DR_DATA_Pos           (0U)                                         \r\n#define ADC_DR_DATA_Msk           (0xFFFFU << ADC_DR_DATA_Pos)                 /*!< 0x0000FFFF */\r\n#define ADC_DR_DATA               ADC_DR_DATA_Msk                              /*!<Regular data */\r\n#define ADC_DR_ADC2DATA_Pos       (16U)                                        \r\n#define ADC_DR_ADC2DATA_Msk       (0xFFFFU << ADC_DR_ADC2DATA_Pos)             /*!< 0xFFFF0000 */\r\n#define ADC_DR_ADC2DATA           ADC_DR_ADC2DATA_Msk                          /*!<ADC2 data */\r\n\r\n/*******************  Bit definition for ADC_CSR register  ********************/\r\n#define ADC_CSR_AWD1_Pos          (0U)                                         \r\n#define ADC_CSR_AWD1_Msk          (0x1U << ADC_CSR_AWD1_Pos)                   /*!< 0x00000001 */\r\n#define ADC_CSR_AWD1              ADC_CSR_AWD1_Msk                             /*!<ADC1 Analog watchdog flag               */\r\n#define ADC_CSR_EOC1_Pos          (1U)                                         \r\n#define ADC_CSR_EOC1_Msk          (0x1U << ADC_CSR_EOC1_Pos)                   /*!< 0x00000002 */\r\n#define ADC_CSR_EOC1              ADC_CSR_EOC1_Msk                             /*!<ADC1 End of conversion                  */\r\n#define ADC_CSR_JEOC1_Pos         (2U)                                         \r\n#define ADC_CSR_JEOC1_Msk         (0x1U << ADC_CSR_JEOC1_Pos)                  /*!< 0x00000004 */\r\n#define ADC_CSR_JEOC1             ADC_CSR_JEOC1_Msk                            /*!<ADC1 Injected channel end of conversion */\r\n#define ADC_CSR_JSTRT1_Pos        (3U)                                         \r\n#define ADC_CSR_JSTRT1_Msk        (0x1U << ADC_CSR_JSTRT1_Pos)                 /*!< 0x00000008 */\r\n#define ADC_CSR_JSTRT1            ADC_CSR_JSTRT1_Msk                           /*!<ADC1 Injected channel Start flag        */\r\n#define ADC_CSR_STRT1_Pos         (4U)                                         \r\n#define ADC_CSR_STRT1_Msk         (0x1U << ADC_CSR_STRT1_Pos)                  /*!< 0x00000010 */\r\n#define ADC_CSR_STRT1             ADC_CSR_STRT1_Msk                            /*!<ADC1 Regular channel Start flag         */\r\n#define ADC_CSR_OVR1_Pos          (5U)                                         \r\n#define ADC_CSR_OVR1_Msk          (0x1U << ADC_CSR_OVR1_Pos)                   /*!< 0x00000020 */\r\n#define ADC_CSR_OVR1              ADC_CSR_OVR1_Msk                             /*!<ADC1 Overrun flag                       */\r\n#define ADC_CSR_AWD2_Pos          (8U)                                         \r\n#define ADC_CSR_AWD2_Msk          (0x1U << ADC_CSR_AWD2_Pos)                   /*!< 0x00000100 */\r\n#define ADC_CSR_AWD2              ADC_CSR_AWD2_Msk                             /*!<ADC2 Analog watchdog flag               */\r\n#define ADC_CSR_EOC2_Pos          (9U)                                         \r\n#define ADC_CSR_EOC2_Msk          (0x1U << ADC_CSR_EOC2_Pos)                   /*!< 0x00000200 */\r\n#define ADC_CSR_EOC2              ADC_CSR_EOC2_Msk                             /*!<ADC2 End of conversion                  */\r\n#define ADC_CSR_JEOC2_Pos         (10U)                                        \r\n#define ADC_CSR_JEOC2_Msk         (0x1U << ADC_CSR_JEOC2_Pos)                  /*!< 0x00000400 */\r\n#define ADC_CSR_JEOC2             ADC_CSR_JEOC2_Msk                            /*!<ADC2 Injected channel end of conversion */\r\n#define ADC_CSR_JSTRT2_Pos        (11U)                                        \r\n#define ADC_CSR_JSTRT2_Msk        (0x1U << ADC_CSR_JSTRT2_Pos)                 /*!< 0x00000800 */\r\n#define ADC_CSR_JSTRT2            ADC_CSR_JSTRT2_Msk                           /*!<ADC2 Injected channel Start flag        */\r\n#define ADC_CSR_STRT2_Pos         (12U)                                        \r\n#define ADC_CSR_STRT2_Msk         (0x1U << ADC_CSR_STRT2_Pos)                  /*!< 0x00001000 */\r\n#define ADC_CSR_STRT2             ADC_CSR_STRT2_Msk                            /*!<ADC2 Regular channel Start flag         */\r\n#define ADC_CSR_OVR2_Pos          (13U)                                        \r\n#define ADC_CSR_OVR2_Msk          (0x1U << ADC_CSR_OVR2_Pos)                   /*!< 0x00002000 */\r\n#define ADC_CSR_OVR2              ADC_CSR_OVR2_Msk                             /*!<ADC2 Overrun flag                       */\r\n#define ADC_CSR_AWD3_Pos          (16U)                                        \r\n#define ADC_CSR_AWD3_Msk          (0x1U << ADC_CSR_AWD3_Pos)                   /*!< 0x00010000 */\r\n#define ADC_CSR_AWD3              ADC_CSR_AWD3_Msk                             /*!<ADC3 Analog watchdog flag               */\r\n#define ADC_CSR_EOC3_Pos          (17U)                                        \r\n#define ADC_CSR_EOC3_Msk          (0x1U << ADC_CSR_EOC3_Pos)                   /*!< 0x00020000 */\r\n#define ADC_CSR_EOC3              ADC_CSR_EOC3_Msk                             /*!<ADC3 End of conversion                  */\r\n#define ADC_CSR_JEOC3_Pos         (18U)                                        \r\n#define ADC_CSR_JEOC3_Msk         (0x1U << ADC_CSR_JEOC3_Pos)                  /*!< 0x00040000 */\r\n#define ADC_CSR_JEOC3             ADC_CSR_JEOC3_Msk                            /*!<ADC3 Injected channel end of conversion */\r\n#define ADC_CSR_JSTRT3_Pos        (19U)                                        \r\n#define ADC_CSR_JSTRT3_Msk        (0x1U << ADC_CSR_JSTRT3_Pos)                 /*!< 0x00080000 */\r\n#define ADC_CSR_JSTRT3            ADC_CSR_JSTRT3_Msk                           /*!<ADC3 Injected channel Start flag        */\r\n#define ADC_CSR_STRT3_Pos         (20U)                                        \r\n#define ADC_CSR_STRT3_Msk         (0x1U << ADC_CSR_STRT3_Pos)                  /*!< 0x00100000 */\r\n#define ADC_CSR_STRT3             ADC_CSR_STRT3_Msk                            /*!<ADC3 Regular channel Start flag         */\r\n#define ADC_CSR_OVR3_Pos          (21U)                                        \r\n#define ADC_CSR_OVR3_Msk          (0x1U << ADC_CSR_OVR3_Pos)                   /*!< 0x00200000 */\r\n#define ADC_CSR_OVR3              ADC_CSR_OVR3_Msk                             /*!<ADC3 Overrun flag                       */\r\n\r\n/* Legacy defines */\r\n#define  ADC_CSR_DOVR1                       ADC_CSR_OVR1\r\n#define  ADC_CSR_DOVR2                       ADC_CSR_OVR2\r\n#define  ADC_CSR_DOVR3                       ADC_CSR_OVR3\r\n\r\n\r\n/*******************  Bit definition for ADC_CCR register  ********************/\r\n#define ADC_CCR_MULTI_Pos         (0U)                                         \r\n#define ADC_CCR_MULTI_Msk         (0x1FU << ADC_CCR_MULTI_Pos)                 /*!< 0x0000001F */\r\n#define ADC_CCR_MULTI             ADC_CCR_MULTI_Msk                            /*!<MULTI[4:0] bits (Multi-ADC mode selection) */\r\n#define ADC_CCR_MULTI_0           (0x01U << ADC_CCR_MULTI_Pos)                 /*!< 0x00000001 */\r\n#define ADC_CCR_MULTI_1           (0x02U << ADC_CCR_MULTI_Pos)                 /*!< 0x00000002 */\r\n#define ADC_CCR_MULTI_2           (0x04U << ADC_CCR_MULTI_Pos)                 /*!< 0x00000004 */\r\n#define ADC_CCR_MULTI_3           (0x08U << ADC_CCR_MULTI_Pos)                 /*!< 0x00000008 */\r\n#define ADC_CCR_MULTI_4           (0x10U << ADC_CCR_MULTI_Pos)                 /*!< 0x00000010 */\r\n#define ADC_CCR_DELAY_Pos         (8U)                                         \r\n#define ADC_CCR_DELAY_Msk         (0xFU << ADC_CCR_DELAY_Pos)                  /*!< 0x00000F00 */\r\n#define ADC_CCR_DELAY             ADC_CCR_DELAY_Msk                            /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */\r\n#define ADC_CCR_DELAY_0           (0x1U << ADC_CCR_DELAY_Pos)                  /*!< 0x00000100 */\r\n#define ADC_CCR_DELAY_1           (0x2U << ADC_CCR_DELAY_Pos)                  /*!< 0x00000200 */\r\n#define ADC_CCR_DELAY_2           (0x4U << ADC_CCR_DELAY_Pos)                  /*!< 0x00000400 */\r\n#define ADC_CCR_DELAY_3           (0x8U << ADC_CCR_DELAY_Pos)                  /*!< 0x00000800 */\r\n#define ADC_CCR_DDS_Pos           (13U)                                        \r\n#define ADC_CCR_DDS_Msk           (0x1U << ADC_CCR_DDS_Pos)                    /*!< 0x00002000 */\r\n#define ADC_CCR_DDS               ADC_CCR_DDS_Msk                              /*!<DMA disable selection (Multi-ADC mode) */\r\n#define ADC_CCR_DMA_Pos           (14U)                                        \r\n#define ADC_CCR_DMA_Msk           (0x3U << ADC_CCR_DMA_Pos)                    /*!< 0x0000C000 */\r\n#define ADC_CCR_DMA               ADC_CCR_DMA_Msk                              /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */\r\n#define ADC_CCR_DMA_0             (0x1U << ADC_CCR_DMA_Pos)                    /*!< 0x00004000 */\r\n#define ADC_CCR_DMA_1             (0x2U << ADC_CCR_DMA_Pos)                    /*!< 0x00008000 */\r\n#define ADC_CCR_ADCPRE_Pos        (16U)                                        \r\n#define ADC_CCR_ADCPRE_Msk        (0x3U << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00030000 */\r\n#define ADC_CCR_ADCPRE            ADC_CCR_ADCPRE_Msk                           /*!<ADCPRE[1:0] bits (ADC prescaler) */\r\n#define ADC_CCR_ADCPRE_0          (0x1U << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00010000 */\r\n#define ADC_CCR_ADCPRE_1          (0x2U << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00020000 */\r\n#define ADC_CCR_VBATE_Pos         (22U)                                        \r\n#define ADC_CCR_VBATE_Msk         (0x1U << ADC_CCR_VBATE_Pos)                  /*!< 0x00400000 */\r\n#define ADC_CCR_VBATE             ADC_CCR_VBATE_Msk                            /*!<VBAT Enable */\r\n#define ADC_CCR_TSVREFE_Pos       (23U)                                        \r\n#define ADC_CCR_TSVREFE_Msk       (0x1U << ADC_CCR_TSVREFE_Pos)                /*!< 0x00800000 */\r\n#define ADC_CCR_TSVREFE           ADC_CCR_TSVREFE_Msk                          /*!<Temperature Sensor and VREFINT Enable */\r\n\r\n/*******************  Bit definition for ADC_CDR register  ********************/\r\n#define ADC_CDR_DATA1_Pos         (0U)                                         \r\n#define ADC_CDR_DATA1_Msk         (0xFFFFU << ADC_CDR_DATA1_Pos)               /*!< 0x0000FFFF */\r\n#define ADC_CDR_DATA1             ADC_CDR_DATA1_Msk                            /*!<1st data of a pair of regular conversions */\r\n#define ADC_CDR_DATA2_Pos         (16U)                                        \r\n#define ADC_CDR_DATA2_Msk         (0xFFFFU << ADC_CDR_DATA2_Pos)               /*!< 0xFFFF0000 */\r\n#define ADC_CDR_DATA2             ADC_CDR_DATA2_Msk                            /*!<2nd data of a pair of regular conversions */\r\n\r\n/* Legacy defines */\r\n#define ADC_CDR_RDATA_MST         ADC_CDR_DATA1\r\n#define ADC_CDR_RDATA_SLV         ADC_CDR_DATA2\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                         Controller Area Network                            */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*!<CAN control and status registers */\r\n/*******************  Bit definition for CAN_MCR register  ********************/\r\n#define CAN_MCR_INRQ_Pos       (0U)                                            \r\n#define CAN_MCR_INRQ_Msk       (0x1U << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */\r\n#define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request            */\r\n#define CAN_MCR_SLEEP_Pos      (1U)                                            \r\n#define CAN_MCR_SLEEP_Msk      (0x1U << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */\r\n#define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request                */\r\n#define CAN_MCR_TXFP_Pos       (2U)                                            \r\n#define CAN_MCR_TXFP_Msk       (0x1U << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */\r\n#define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority            */\r\n#define CAN_MCR_RFLM_Pos       (3U)                                            \r\n#define CAN_MCR_RFLM_Msk       (0x1U << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */\r\n#define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode          */\r\n#define CAN_MCR_NART_Pos       (4U)                                            \r\n#define CAN_MCR_NART_Msk       (0x1U << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */\r\n#define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission       */\r\n#define CAN_MCR_AWUM_Pos       (5U)                                            \r\n#define CAN_MCR_AWUM_Msk       (0x1U << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */\r\n#define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode             */\r\n#define CAN_MCR_ABOM_Pos       (6U)                                            \r\n#define CAN_MCR_ABOM_Msk       (0x1U << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */\r\n#define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management      */\r\n#define CAN_MCR_TTCM_Pos       (7U)                                            \r\n#define CAN_MCR_TTCM_Msk       (0x1U << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */\r\n#define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */\r\n#define CAN_MCR_RESET_Pos      (15U)                                           \r\n#define CAN_MCR_RESET_Msk      (0x1U << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */\r\n#define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset       */\r\n\r\n/*******************  Bit definition for CAN_MSR register  ********************/\r\n#define CAN_MSR_INAK_Pos       (0U)                                            \r\n#define CAN_MSR_INAK_Msk       (0x1U << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */\r\n#define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge  */\r\n#define CAN_MSR_SLAK_Pos       (1U)                                            \r\n#define CAN_MSR_SLAK_Msk       (0x1U << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */\r\n#define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge           */\r\n#define CAN_MSR_ERRI_Pos       (2U)                                            \r\n#define CAN_MSR_ERRI_Msk       (0x1U << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */\r\n#define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt             */\r\n#define CAN_MSR_WKUI_Pos       (3U)                                            \r\n#define CAN_MSR_WKUI_Msk       (0x1U << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */\r\n#define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt            */\r\n#define CAN_MSR_SLAKI_Pos      (4U)                                            \r\n#define CAN_MSR_SLAKI_Msk      (0x1U << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */\r\n#define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */\r\n#define CAN_MSR_TXM_Pos        (8U)                                            \r\n#define CAN_MSR_TXM_Msk        (0x1U << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */\r\n#define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode               */\r\n#define CAN_MSR_RXM_Pos        (9U)                                            \r\n#define CAN_MSR_RXM_Msk        (0x1U << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */\r\n#define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode                */\r\n#define CAN_MSR_SAMP_Pos       (10U)                                           \r\n#define CAN_MSR_SAMP_Msk       (0x1U << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */\r\n#define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point           */\r\n#define CAN_MSR_RX_Pos         (11U)                                           \r\n#define CAN_MSR_RX_Msk         (0x1U << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */\r\n#define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal               */\r\n\r\n/*******************  Bit definition for CAN_TSR register  ********************/\r\n#define CAN_TSR_RQCP0_Pos      (0U)                                            \r\n#define CAN_TSR_RQCP0_Msk      (0x1U << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */\r\n#define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0      */\r\n#define CAN_TSR_TXOK0_Pos      (1U)                                            \r\n#define CAN_TSR_TXOK0_Msk      (0x1U << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */\r\n#define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0     */\r\n#define CAN_TSR_ALST0_Pos      (2U)                                            \r\n#define CAN_TSR_ALST0_Msk      (0x1U << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */\r\n#define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0   */\r\n#define CAN_TSR_TERR0_Pos      (3U)                                            \r\n#define CAN_TSR_TERR0_Msk      (0x1U << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */\r\n#define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0  */\r\n#define CAN_TSR_ABRQ0_Pos      (7U)                                            \r\n#define CAN_TSR_ABRQ0_Msk      (0x1U << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */\r\n#define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0      */\r\n#define CAN_TSR_RQCP1_Pos      (8U)                                            \r\n#define CAN_TSR_RQCP1_Msk      (0x1U << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */\r\n#define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1      */\r\n#define CAN_TSR_TXOK1_Pos      (9U)                                            \r\n#define CAN_TSR_TXOK1_Msk      (0x1U << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */\r\n#define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1     */\r\n#define CAN_TSR_ALST1_Pos      (10U)                                           \r\n#define CAN_TSR_ALST1_Msk      (0x1U << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */\r\n#define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1   */\r\n#define CAN_TSR_TERR1_Pos      (11U)                                           \r\n#define CAN_TSR_TERR1_Msk      (0x1U << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */\r\n#define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1  */\r\n#define CAN_TSR_ABRQ1_Pos      (15U)                                           \r\n#define CAN_TSR_ABRQ1_Msk      (0x1U << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */\r\n#define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1     */\r\n#define CAN_TSR_RQCP2_Pos      (16U)                                           \r\n#define CAN_TSR_RQCP2_Msk      (0x1U << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */\r\n#define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2      */\r\n#define CAN_TSR_TXOK2_Pos      (17U)                                           \r\n#define CAN_TSR_TXOK2_Msk      (0x1U << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */\r\n#define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2    */\r\n#define CAN_TSR_ALST2_Pos      (18U)                                           \r\n#define CAN_TSR_ALST2_Msk      (0x1U << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */\r\n#define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2  */\r\n#define CAN_TSR_TERR2_Pos      (19U)                                           \r\n#define CAN_TSR_TERR2_Msk      (0x1U << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */\r\n#define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */\r\n#define CAN_TSR_ABRQ2_Pos      (23U)                                           \r\n#define CAN_TSR_ABRQ2_Msk      (0x1U << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */\r\n#define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2     */\r\n#define CAN_TSR_CODE_Pos       (24U)                                           \r\n#define CAN_TSR_CODE_Msk       (0x3U << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */\r\n#define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code                    */\r\n\r\n#define CAN_TSR_TME_Pos        (26U)                                           \r\n#define CAN_TSR_TME_Msk        (0x7U << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */\r\n#define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */\r\n#define CAN_TSR_TME0_Pos       (26U)                                           \r\n#define CAN_TSR_TME0_Msk       (0x1U << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */\r\n#define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */\r\n#define CAN_TSR_TME1_Pos       (27U)                                           \r\n#define CAN_TSR_TME1_Msk       (0x1U << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */\r\n#define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */\r\n#define CAN_TSR_TME2_Pos       (28U)                                           \r\n#define CAN_TSR_TME2_Msk       (0x1U << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */\r\n#define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */\r\n\r\n#define CAN_TSR_LOW_Pos        (29U)                                           \r\n#define CAN_TSR_LOW_Msk        (0x7U << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */\r\n#define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */\r\n#define CAN_TSR_LOW0_Pos       (29U)                                           \r\n#define CAN_TSR_LOW0_Msk       (0x1U << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */\r\n#define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */\r\n#define CAN_TSR_LOW1_Pos       (30U)                                           \r\n#define CAN_TSR_LOW1_Msk       (0x1U << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */\r\n#define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */\r\n#define CAN_TSR_LOW2_Pos       (31U)                                           \r\n#define CAN_TSR_LOW2_Msk       (0x1U << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */\r\n#define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */\r\n\r\n/*******************  Bit definition for CAN_RF0R register  *******************/\r\n#define CAN_RF0R_FMP0_Pos      (0U)                                            \r\n#define CAN_RF0R_FMP0_Msk      (0x3U << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */\r\n#define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending        */\r\n#define CAN_RF0R_FULL0_Pos     (3U)                                            \r\n#define CAN_RF0R_FULL0_Msk     (0x1U << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */\r\n#define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full                   */\r\n#define CAN_RF0R_FOVR0_Pos     (4U)                                            \r\n#define CAN_RF0R_FOVR0_Msk     (0x1U << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */\r\n#define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun                */\r\n#define CAN_RF0R_RFOM0_Pos     (5U)                                            \r\n#define CAN_RF0R_RFOM0_Msk     (0x1U << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */\r\n#define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */\r\n\r\n/*******************  Bit definition for CAN_RF1R register  *******************/\r\n#define CAN_RF1R_FMP1_Pos      (0U)                                            \r\n#define CAN_RF1R_FMP1_Msk      (0x3U << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */\r\n#define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending        */\r\n#define CAN_RF1R_FULL1_Pos     (3U)                                            \r\n#define CAN_RF1R_FULL1_Msk     (0x1U << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */\r\n#define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full                   */\r\n#define CAN_RF1R_FOVR1_Pos     (4U)                                            \r\n#define CAN_RF1R_FOVR1_Msk     (0x1U << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */\r\n#define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun                */\r\n#define CAN_RF1R_RFOM1_Pos     (5U)                                            \r\n#define CAN_RF1R_RFOM1_Msk     (0x1U << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */\r\n#define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */\r\n\r\n/********************  Bit definition for CAN_IER register  *******************/\r\n#define CAN_IER_TMEIE_Pos      (0U)                                            \r\n#define CAN_IER_TMEIE_Msk      (0x1U << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */\r\n#define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */\r\n#define CAN_IER_FMPIE0_Pos     (1U)                                            \r\n#define CAN_IER_FMPIE0_Msk     (0x1U << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */\r\n#define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable   */\r\n#define CAN_IER_FFIE0_Pos      (2U)                                            \r\n#define CAN_IER_FFIE0_Msk      (0x1U << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */\r\n#define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable              */\r\n#define CAN_IER_FOVIE0_Pos     (3U)                                            \r\n#define CAN_IER_FOVIE0_Msk     (0x1U << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */\r\n#define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable           */\r\n#define CAN_IER_FMPIE1_Pos     (4U)                                            \r\n#define CAN_IER_FMPIE1_Msk     (0x1U << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */\r\n#define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable   */\r\n#define CAN_IER_FFIE1_Pos      (5U)                                            \r\n#define CAN_IER_FFIE1_Msk      (0x1U << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */\r\n#define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable              */\r\n#define CAN_IER_FOVIE1_Pos     (6U)                                            \r\n#define CAN_IER_FOVIE1_Msk     (0x1U << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */\r\n#define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable           */\r\n#define CAN_IER_EWGIE_Pos      (8U)                                            \r\n#define CAN_IER_EWGIE_Msk      (0x1U << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */\r\n#define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable          */\r\n#define CAN_IER_EPVIE_Pos      (9U)                                            \r\n#define CAN_IER_EPVIE_Msk      (0x1U << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */\r\n#define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable          */\r\n#define CAN_IER_BOFIE_Pos      (10U)                                           \r\n#define CAN_IER_BOFIE_Msk      (0x1U << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */\r\n#define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable                */\r\n#define CAN_IER_LECIE_Pos      (11U)                                           \r\n#define CAN_IER_LECIE_Msk      (0x1U << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */\r\n#define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable        */\r\n#define CAN_IER_ERRIE_Pos      (15U)                                           \r\n#define CAN_IER_ERRIE_Msk      (0x1U << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */\r\n#define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable                  */\r\n#define CAN_IER_WKUIE_Pos      (16U)                                           \r\n#define CAN_IER_WKUIE_Msk      (0x1U << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */\r\n#define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable                 */\r\n#define CAN_IER_SLKIE_Pos      (17U)                                           \r\n#define CAN_IER_SLKIE_Msk      (0x1U << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */\r\n#define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable                  */\r\n\r\n/********************  Bit definition for CAN_ESR register  *******************/\r\n#define CAN_ESR_EWGF_Pos       (0U)                                            \r\n#define CAN_ESR_EWGF_Msk       (0x1U << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */\r\n#define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */\r\n#define CAN_ESR_EPVF_Pos       (1U)                                            \r\n#define CAN_ESR_EPVF_Msk       (0x1U << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */\r\n#define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */\r\n#define CAN_ESR_BOFF_Pos       (2U)                                            \r\n#define CAN_ESR_BOFF_Msk       (0x1U << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */\r\n#define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */\r\n\r\n#define CAN_ESR_LEC_Pos        (4U)                                            \r\n#define CAN_ESR_LEC_Msk        (0x7U << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */\r\n#define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */\r\n#define CAN_ESR_LEC_0          (0x1U << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */\r\n#define CAN_ESR_LEC_1          (0x2U << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */\r\n#define CAN_ESR_LEC_2          (0x4U << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */\r\n\r\n#define CAN_ESR_TEC_Pos        (16U)                                           \r\n#define CAN_ESR_TEC_Msk        (0xFFU << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */\r\n#define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */\r\n#define CAN_ESR_REC_Pos        (24U)                                           \r\n#define CAN_ESR_REC_Msk        (0xFFU << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */\r\n#define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */\r\n\r\n/*******************  Bit definition for CAN_BTR register  ********************/\r\n#define CAN_BTR_BRP_Pos        (0U)                                            \r\n#define CAN_BTR_BRP_Msk        (0x3FFU << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */\r\n#define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler           */\r\n#define CAN_BTR_TS1_Pos        (16U)                                           \r\n#define CAN_BTR_TS1_Msk        (0xFU << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */\r\n#define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1                */\r\n#define CAN_BTR_TS1_0          (0x1U << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */\r\n#define CAN_BTR_TS1_1          (0x2U << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */\r\n#define CAN_BTR_TS1_2          (0x4U << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */\r\n#define CAN_BTR_TS1_3          (0x8U << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */\r\n#define CAN_BTR_TS2_Pos        (20U)                                           \r\n#define CAN_BTR_TS2_Msk        (0x7U << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */\r\n#define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2                */\r\n#define CAN_BTR_TS2_0          (0x1U << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */\r\n#define CAN_BTR_TS2_1          (0x2U << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */\r\n#define CAN_BTR_TS2_2          (0x4U << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */\r\n#define CAN_BTR_SJW_Pos        (24U)                                           \r\n#define CAN_BTR_SJW_Msk        (0x3U << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */\r\n#define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width  */\r\n#define CAN_BTR_SJW_0          (0x1U << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */\r\n#define CAN_BTR_SJW_1          (0x2U << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */\r\n#define CAN_BTR_LBKM_Pos       (30U)                                           \r\n#define CAN_BTR_LBKM_Msk       (0x1U << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */\r\n#define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug)        */\r\n#define CAN_BTR_SILM_Pos       (31U)                                           \r\n#define CAN_BTR_SILM_Msk       (0x1U << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */\r\n#define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode                   */\r\n\r\n/*!<Mailbox registers */\r\n/******************  Bit definition for CAN_TI0R register  ********************/\r\n#define CAN_TI0R_TXRQ_Pos      (0U)                                            \r\n#define CAN_TI0R_TXRQ_Msk      (0x1U << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */\r\n#define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request                   */\r\n#define CAN_TI0R_RTR_Pos       (1U)                                            \r\n#define CAN_TI0R_RTR_Msk       (0x1U << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */\r\n#define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request                */\r\n#define CAN_TI0R_IDE_Pos       (2U)                                            \r\n#define CAN_TI0R_IDE_Msk       (0x1U << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */\r\n#define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension                       */\r\n#define CAN_TI0R_EXID_Pos      (3U)                                            \r\n#define CAN_TI0R_EXID_Msk      (0x3FFFFU << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */\r\n#define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier                        */\r\n#define CAN_TI0R_STID_Pos      (21U)                                           \r\n#define CAN_TI0R_STID_Msk      (0x7FFU << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */\r\n#define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\r\n\r\n/******************  Bit definition for CAN_TDT0R register  *******************/\r\n#define CAN_TDT0R_DLC_Pos      (0U)                                            \r\n#define CAN_TDT0R_DLC_Msk      (0xFU << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */\r\n#define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code     */\r\n#define CAN_TDT0R_TGT_Pos      (8U)                                            \r\n#define CAN_TDT0R_TGT_Msk      (0x1U << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */\r\n#define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */\r\n#define CAN_TDT0R_TIME_Pos     (16U)                                           \r\n#define CAN_TDT0R_TIME_Msk     (0xFFFFU << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */\r\n#define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp   */\r\n\r\n/******************  Bit definition for CAN_TDL0R register  *******************/\r\n#define CAN_TDL0R_DATA0_Pos    (0U)                                            \r\n#define CAN_TDL0R_DATA0_Msk    (0xFFU << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */\r\n#define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */\r\n#define CAN_TDL0R_DATA1_Pos    (8U)                                            \r\n#define CAN_TDL0R_DATA1_Msk    (0xFFU << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */\r\n#define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */\r\n#define CAN_TDL0R_DATA2_Pos    (16U)                                           \r\n#define CAN_TDL0R_DATA2_Msk    (0xFFU << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */\r\n#define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */\r\n#define CAN_TDL0R_DATA3_Pos    (24U)                                           \r\n#define CAN_TDL0R_DATA3_Msk    (0xFFU << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */\r\n#define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */\r\n\r\n/******************  Bit definition for CAN_TDH0R register  *******************/\r\n#define CAN_TDH0R_DATA4_Pos    (0U)                                            \r\n#define CAN_TDH0R_DATA4_Msk    (0xFFU << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */\r\n#define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */\r\n#define CAN_TDH0R_DATA5_Pos    (8U)                                            \r\n#define CAN_TDH0R_DATA5_Msk    (0xFFU << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */\r\n#define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */\r\n#define CAN_TDH0R_DATA6_Pos    (16U)                                           \r\n#define CAN_TDH0R_DATA6_Msk    (0xFFU << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */\r\n#define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */\r\n#define CAN_TDH0R_DATA7_Pos    (24U)                                           \r\n#define CAN_TDH0R_DATA7_Msk    (0xFFU << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */\r\n#define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */\r\n\r\n/*******************  Bit definition for CAN_TI1R register  *******************/\r\n#define CAN_TI1R_TXRQ_Pos      (0U)                                            \r\n#define CAN_TI1R_TXRQ_Msk      (0x1U << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */\r\n#define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request                   */\r\n#define CAN_TI1R_RTR_Pos       (1U)                                            \r\n#define CAN_TI1R_RTR_Msk       (0x1U << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */\r\n#define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request                */\r\n#define CAN_TI1R_IDE_Pos       (2U)                                            \r\n#define CAN_TI1R_IDE_Msk       (0x1U << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */\r\n#define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension                       */\r\n#define CAN_TI1R_EXID_Pos      (3U)                                            \r\n#define CAN_TI1R_EXID_Msk      (0x3FFFFU << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */\r\n#define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier                        */\r\n#define CAN_TI1R_STID_Pos      (21U)                                           \r\n#define CAN_TI1R_STID_Msk      (0x7FFU << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */\r\n#define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\r\n\r\n/*******************  Bit definition for CAN_TDT1R register  ******************/\r\n#define CAN_TDT1R_DLC_Pos      (0U)                                            \r\n#define CAN_TDT1R_DLC_Msk      (0xFU << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */\r\n#define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code     */\r\n#define CAN_TDT1R_TGT_Pos      (8U)                                            \r\n#define CAN_TDT1R_TGT_Msk      (0x1U << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */\r\n#define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */\r\n#define CAN_TDT1R_TIME_Pos     (16U)                                           \r\n#define CAN_TDT1R_TIME_Msk     (0xFFFFU << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */\r\n#define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp   */\r\n\r\n/*******************  Bit definition for CAN_TDL1R register  ******************/\r\n#define CAN_TDL1R_DATA0_Pos    (0U)                                            \r\n#define CAN_TDL1R_DATA0_Msk    (0xFFU << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */\r\n#define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */\r\n#define CAN_TDL1R_DATA1_Pos    (8U)                                            \r\n#define CAN_TDL1R_DATA1_Msk    (0xFFU << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */\r\n#define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */\r\n#define CAN_TDL1R_DATA2_Pos    (16U)                                           \r\n#define CAN_TDL1R_DATA2_Msk    (0xFFU << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */\r\n#define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */\r\n#define CAN_TDL1R_DATA3_Pos    (24U)                                           \r\n#define CAN_TDL1R_DATA3_Msk    (0xFFU << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */\r\n#define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */\r\n\r\n/*******************  Bit definition for CAN_TDH1R register  ******************/\r\n#define CAN_TDH1R_DATA4_Pos    (0U)                                            \r\n#define CAN_TDH1R_DATA4_Msk    (0xFFU << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */\r\n#define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */\r\n#define CAN_TDH1R_DATA5_Pos    (8U)                                            \r\n#define CAN_TDH1R_DATA5_Msk    (0xFFU << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */\r\n#define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */\r\n#define CAN_TDH1R_DATA6_Pos    (16U)                                           \r\n#define CAN_TDH1R_DATA6_Msk    (0xFFU << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */\r\n#define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */\r\n#define CAN_TDH1R_DATA7_Pos    (24U)                                           \r\n#define CAN_TDH1R_DATA7_Msk    (0xFFU << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */\r\n#define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */\r\n\r\n/*******************  Bit definition for CAN_TI2R register  *******************/\r\n#define CAN_TI2R_TXRQ_Pos      (0U)                                            \r\n#define CAN_TI2R_TXRQ_Msk      (0x1U << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */\r\n#define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request                   */\r\n#define CAN_TI2R_RTR_Pos       (1U)                                            \r\n#define CAN_TI2R_RTR_Msk       (0x1U << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */\r\n#define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request                */\r\n#define CAN_TI2R_IDE_Pos       (2U)                                            \r\n#define CAN_TI2R_IDE_Msk       (0x1U << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */\r\n#define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension                       */\r\n#define CAN_TI2R_EXID_Pos      (3U)                                            \r\n#define CAN_TI2R_EXID_Msk      (0x3FFFFU << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */\r\n#define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier                        */\r\n#define CAN_TI2R_STID_Pos      (21U)                                           \r\n#define CAN_TI2R_STID_Msk      (0x7FFU << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */\r\n#define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\r\n\r\n/*******************  Bit definition for CAN_TDT2R register  ******************/\r\n#define CAN_TDT2R_DLC_Pos      (0U)                                            \r\n#define CAN_TDT2R_DLC_Msk      (0xFU << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */\r\n#define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code      */\r\n#define CAN_TDT2R_TGT_Pos      (8U)                                            \r\n#define CAN_TDT2R_TGT_Msk      (0x1U << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */\r\n#define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time  */\r\n#define CAN_TDT2R_TIME_Pos     (16U)                                           \r\n#define CAN_TDT2R_TIME_Msk     (0xFFFFU << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */\r\n#define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp    */\r\n\r\n/*******************  Bit definition for CAN_TDL2R register  ******************/\r\n#define CAN_TDL2R_DATA0_Pos    (0U)                                            \r\n#define CAN_TDL2R_DATA0_Msk    (0xFFU << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */\r\n#define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */\r\n#define CAN_TDL2R_DATA1_Pos    (8U)                                            \r\n#define CAN_TDL2R_DATA1_Msk    (0xFFU << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */\r\n#define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */\r\n#define CAN_TDL2R_DATA2_Pos    (16U)                                           \r\n#define CAN_TDL2R_DATA2_Msk    (0xFFU << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */\r\n#define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */\r\n#define CAN_TDL2R_DATA3_Pos    (24U)                                           \r\n#define CAN_TDL2R_DATA3_Msk    (0xFFU << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */\r\n#define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */\r\n\r\n/*******************  Bit definition for CAN_TDH2R register  ******************/\r\n#define CAN_TDH2R_DATA4_Pos    (0U)                                            \r\n#define CAN_TDH2R_DATA4_Msk    (0xFFU << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */\r\n#define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */\r\n#define CAN_TDH2R_DATA5_Pos    (8U)                                            \r\n#define CAN_TDH2R_DATA5_Msk    (0xFFU << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */\r\n#define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */\r\n#define CAN_TDH2R_DATA6_Pos    (16U)                                           \r\n#define CAN_TDH2R_DATA6_Msk    (0xFFU << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */\r\n#define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */\r\n#define CAN_TDH2R_DATA7_Pos    (24U)                                           \r\n#define CAN_TDH2R_DATA7_Msk    (0xFFU << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */\r\n#define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */\r\n\r\n/*******************  Bit definition for CAN_RI0R register  *******************/\r\n#define CAN_RI0R_RTR_Pos       (1U)                                            \r\n#define CAN_RI0R_RTR_Msk       (0x1U << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */\r\n#define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request                */\r\n#define CAN_RI0R_IDE_Pos       (2U)                                            \r\n#define CAN_RI0R_IDE_Msk       (0x1U << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */\r\n#define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension                       */\r\n#define CAN_RI0R_EXID_Pos      (3U)                                            \r\n#define CAN_RI0R_EXID_Msk      (0x3FFFFU << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */\r\n#define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier                        */\r\n#define CAN_RI0R_STID_Pos      (21U)                                           \r\n#define CAN_RI0R_STID_Msk      (0x7FFU << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */\r\n#define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\r\n\r\n/*******************  Bit definition for CAN_RDT0R register  ******************/\r\n#define CAN_RDT0R_DLC_Pos      (0U)                                            \r\n#define CAN_RDT0R_DLC_Msk      (0xFU << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */\r\n#define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */\r\n#define CAN_RDT0R_FMI_Pos      (8U)                                            \r\n#define CAN_RDT0R_FMI_Msk      (0xFFU << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */\r\n#define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */\r\n#define CAN_RDT0R_TIME_Pos     (16U)                                           \r\n#define CAN_RDT0R_TIME_Msk     (0xFFFFU << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */\r\n#define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */\r\n\r\n/*******************  Bit definition for CAN_RDL0R register  ******************/\r\n#define CAN_RDL0R_DATA0_Pos    (0U)                                            \r\n#define CAN_RDL0R_DATA0_Msk    (0xFFU << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */\r\n#define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */\r\n#define CAN_RDL0R_DATA1_Pos    (8U)                                            \r\n#define CAN_RDL0R_DATA1_Msk    (0xFFU << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */\r\n#define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */\r\n#define CAN_RDL0R_DATA2_Pos    (16U)                                           \r\n#define CAN_RDL0R_DATA2_Msk    (0xFFU << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */\r\n#define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */\r\n#define CAN_RDL0R_DATA3_Pos    (24U)                                           \r\n#define CAN_RDL0R_DATA3_Msk    (0xFFU << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */\r\n#define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */\r\n\r\n/*******************  Bit definition for CAN_RDH0R register  ******************/\r\n#define CAN_RDH0R_DATA4_Pos    (0U)                                            \r\n#define CAN_RDH0R_DATA4_Msk    (0xFFU << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */\r\n#define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */\r\n#define CAN_RDH0R_DATA5_Pos    (8U)                                            \r\n#define CAN_RDH0R_DATA5_Msk    (0xFFU << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */\r\n#define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */\r\n#define CAN_RDH0R_DATA6_Pos    (16U)                                           \r\n#define CAN_RDH0R_DATA6_Msk    (0xFFU << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */\r\n#define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */\r\n#define CAN_RDH0R_DATA7_Pos    (24U)                                           \r\n#define CAN_RDH0R_DATA7_Msk    (0xFFU << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */\r\n#define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */\r\n\r\n/*******************  Bit definition for CAN_RI1R register  *******************/\r\n#define CAN_RI1R_RTR_Pos       (1U)                                            \r\n#define CAN_RI1R_RTR_Msk       (0x1U << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */\r\n#define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request                */\r\n#define CAN_RI1R_IDE_Pos       (2U)                                            \r\n#define CAN_RI1R_IDE_Msk       (0x1U << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */\r\n#define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension                       */\r\n#define CAN_RI1R_EXID_Pos      (3U)                                            \r\n#define CAN_RI1R_EXID_Msk      (0x3FFFFU << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */\r\n#define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier                        */\r\n#define CAN_RI1R_STID_Pos      (21U)                                           \r\n#define CAN_RI1R_STID_Msk      (0x7FFU << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */\r\n#define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\r\n\r\n/*******************  Bit definition for CAN_RDT1R register  ******************/\r\n#define CAN_RDT1R_DLC_Pos      (0U)                                            \r\n#define CAN_RDT1R_DLC_Msk      (0xFU << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */\r\n#define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code   */\r\n#define CAN_RDT1R_FMI_Pos      (8U)                                            \r\n#define CAN_RDT1R_FMI_Msk      (0xFFU << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */\r\n#define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */\r\n#define CAN_RDT1R_TIME_Pos     (16U)                                           \r\n#define CAN_RDT1R_TIME_Msk     (0xFFFFU << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */\r\n#define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */\r\n\r\n/*******************  Bit definition for CAN_RDL1R register  ******************/\r\n#define CAN_RDL1R_DATA0_Pos    (0U)                                            \r\n#define CAN_RDL1R_DATA0_Msk    (0xFFU << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */\r\n#define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */\r\n#define CAN_RDL1R_DATA1_Pos    (8U)                                            \r\n#define CAN_RDL1R_DATA1_Msk    (0xFFU << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */\r\n#define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */\r\n#define CAN_RDL1R_DATA2_Pos    (16U)                                           \r\n#define CAN_RDL1R_DATA2_Msk    (0xFFU << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */\r\n#define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */\r\n#define CAN_RDL1R_DATA3_Pos    (24U)                                           \r\n#define CAN_RDL1R_DATA3_Msk    (0xFFU << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */\r\n#define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */\r\n\r\n/*******************  Bit definition for CAN_RDH1R register  ******************/\r\n#define CAN_RDH1R_DATA4_Pos    (0U)                                            \r\n#define CAN_RDH1R_DATA4_Msk    (0xFFU << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */\r\n#define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */\r\n#define CAN_RDH1R_DATA5_Pos    (8U)                                            \r\n#define CAN_RDH1R_DATA5_Msk    (0xFFU << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */\r\n#define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */\r\n#define CAN_RDH1R_DATA6_Pos    (16U)                                           \r\n#define CAN_RDH1R_DATA6_Msk    (0xFFU << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */\r\n#define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */\r\n#define CAN_RDH1R_DATA7_Pos    (24U)                                           \r\n#define CAN_RDH1R_DATA7_Msk    (0xFFU << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */\r\n#define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */\r\n\r\n/*!<CAN filter registers */\r\n/*******************  Bit definition for CAN_FMR register  ********************/\r\n#define CAN_FMR_FINIT          ((uint8_t)0x01U)                                /*!<Filter Init Mode */\r\n#define CAN_FMR_CAN2SB_Pos     (8U)                                            \r\n#define CAN_FMR_CAN2SB_Msk     (0x3FU << CAN_FMR_CAN2SB_Pos)                   /*!< 0x00003F00 */\r\n#define CAN_FMR_CAN2SB         CAN_FMR_CAN2SB_Msk                              /*!<CAN2 start bank */\r\n\r\n/*******************  Bit definition for CAN_FM1R register  *******************/\r\n#define CAN_FM1R_FBM_Pos       (0U)                                            \r\n#define CAN_FM1R_FBM_Msk       (0x3FFFU << CAN_FM1R_FBM_Pos)                   /*!< 0x00003FFF */\r\n#define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */\r\n#define CAN_FM1R_FBM0_Pos      (0U)                                            \r\n#define CAN_FM1R_FBM0_Msk      (0x1U << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */\r\n#define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0  */\r\n#define CAN_FM1R_FBM1_Pos      (1U)                                            \r\n#define CAN_FM1R_FBM1_Msk      (0x1U << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */\r\n#define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1  */\r\n#define CAN_FM1R_FBM2_Pos      (2U)                                            \r\n#define CAN_FM1R_FBM2_Msk      (0x1U << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */\r\n#define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2  */\r\n#define CAN_FM1R_FBM3_Pos      (3U)                                            \r\n#define CAN_FM1R_FBM3_Msk      (0x1U << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */\r\n#define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3  */\r\n#define CAN_FM1R_FBM4_Pos      (4U)                                            \r\n#define CAN_FM1R_FBM4_Msk      (0x1U << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */\r\n#define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4  */\r\n#define CAN_FM1R_FBM5_Pos      (5U)                                            \r\n#define CAN_FM1R_FBM5_Msk      (0x1U << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */\r\n#define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5  */\r\n#define CAN_FM1R_FBM6_Pos      (6U)                                            \r\n#define CAN_FM1R_FBM6_Msk      (0x1U << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */\r\n#define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6  */\r\n#define CAN_FM1R_FBM7_Pos      (7U)                                            \r\n#define CAN_FM1R_FBM7_Msk      (0x1U << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */\r\n#define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7  */\r\n#define CAN_FM1R_FBM8_Pos      (8U)                                            \r\n#define CAN_FM1R_FBM8_Msk      (0x1U << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */\r\n#define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8  */\r\n#define CAN_FM1R_FBM9_Pos      (9U)                                            \r\n#define CAN_FM1R_FBM9_Msk      (0x1U << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */\r\n#define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9  */\r\n#define CAN_FM1R_FBM10_Pos     (10U)                                           \r\n#define CAN_FM1R_FBM10_Msk     (0x1U << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */\r\n#define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */\r\n#define CAN_FM1R_FBM11_Pos     (11U)                                           \r\n#define CAN_FM1R_FBM11_Msk     (0x1U << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */\r\n#define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */\r\n#define CAN_FM1R_FBM12_Pos     (12U)                                           \r\n#define CAN_FM1R_FBM12_Msk     (0x1U << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */\r\n#define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */\r\n#define CAN_FM1R_FBM13_Pos     (13U)                                           \r\n#define CAN_FM1R_FBM13_Msk     (0x1U << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */\r\n#define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */\r\n\r\n/*******************  Bit definition for CAN_FS1R register  *******************/\r\n#define CAN_FS1R_FSC_Pos       (0U)                                            \r\n#define CAN_FS1R_FSC_Msk       (0x3FFFU << CAN_FS1R_FSC_Pos)                   /*!< 0x00003FFF */\r\n#define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration        */\r\n#define CAN_FS1R_FSC0_Pos      (0U)                                            \r\n#define CAN_FS1R_FSC0_Msk      (0x1U << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */\r\n#define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0  */\r\n#define CAN_FS1R_FSC1_Pos      (1U)                                            \r\n#define CAN_FS1R_FSC1_Msk      (0x1U << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */\r\n#define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1  */\r\n#define CAN_FS1R_FSC2_Pos      (2U)                                            \r\n#define CAN_FS1R_FSC2_Msk      (0x1U << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */\r\n#define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2  */\r\n#define CAN_FS1R_FSC3_Pos      (3U)                                            \r\n#define CAN_FS1R_FSC3_Msk      (0x1U << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */\r\n#define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3  */\r\n#define CAN_FS1R_FSC4_Pos      (4U)                                            \r\n#define CAN_FS1R_FSC4_Msk      (0x1U << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */\r\n#define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4  */\r\n#define CAN_FS1R_FSC5_Pos      (5U)                                            \r\n#define CAN_FS1R_FSC5_Msk      (0x1U << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */\r\n#define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5  */\r\n#define CAN_FS1R_FSC6_Pos      (6U)                                            \r\n#define CAN_FS1R_FSC6_Msk      (0x1U << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */\r\n#define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6  */\r\n#define CAN_FS1R_FSC7_Pos      (7U)                                            \r\n#define CAN_FS1R_FSC7_Msk      (0x1U << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */\r\n#define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7  */\r\n#define CAN_FS1R_FSC8_Pos      (8U)                                            \r\n#define CAN_FS1R_FSC8_Msk      (0x1U << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */\r\n#define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8  */\r\n#define CAN_FS1R_FSC9_Pos      (9U)                                            \r\n#define CAN_FS1R_FSC9_Msk      (0x1U << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */\r\n#define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9  */\r\n#define CAN_FS1R_FSC10_Pos     (10U)                                           \r\n#define CAN_FS1R_FSC10_Msk     (0x1U << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */\r\n#define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */\r\n#define CAN_FS1R_FSC11_Pos     (11U)                                           \r\n#define CAN_FS1R_FSC11_Msk     (0x1U << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */\r\n#define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */\r\n#define CAN_FS1R_FSC12_Pos     (12U)                                           \r\n#define CAN_FS1R_FSC12_Msk     (0x1U << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */\r\n#define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */\r\n#define CAN_FS1R_FSC13_Pos     (13U)                                           \r\n#define CAN_FS1R_FSC13_Msk     (0x1U << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */\r\n#define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */\r\n\r\n/******************  Bit definition for CAN_FFA1R register  *******************/\r\n#define CAN_FFA1R_FFA_Pos      (0U)                                            \r\n#define CAN_FFA1R_FFA_Msk      (0x3FFFU << CAN_FFA1R_FFA_Pos)                  /*!< 0x00003FFF */\r\n#define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */\r\n#define CAN_FFA1R_FFA0_Pos     (0U)                                            \r\n#define CAN_FFA1R_FFA0_Msk     (0x1U << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */\r\n#define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment for Filter 0 */\r\n#define CAN_FFA1R_FFA1_Pos     (1U)                                            \r\n#define CAN_FFA1R_FFA1_Msk     (0x1U << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */\r\n#define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment for Filter 1 */\r\n#define CAN_FFA1R_FFA2_Pos     (2U)                                            \r\n#define CAN_FFA1R_FFA2_Msk     (0x1U << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */\r\n#define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment for Filter 2 */\r\n#define CAN_FFA1R_FFA3_Pos     (3U)                                            \r\n#define CAN_FFA1R_FFA3_Msk     (0x1U << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */\r\n#define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment for Filter 3 */\r\n#define CAN_FFA1R_FFA4_Pos     (4U)                                            \r\n#define CAN_FFA1R_FFA4_Msk     (0x1U << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */\r\n#define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment for Filter 4 */\r\n#define CAN_FFA1R_FFA5_Pos     (5U)                                            \r\n#define CAN_FFA1R_FFA5_Msk     (0x1U << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */\r\n#define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment for Filter 5 */\r\n#define CAN_FFA1R_FFA6_Pos     (6U)                                            \r\n#define CAN_FFA1R_FFA6_Msk     (0x1U << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */\r\n#define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment for Filter 6 */\r\n#define CAN_FFA1R_FFA7_Pos     (7U)                                            \r\n#define CAN_FFA1R_FFA7_Msk     (0x1U << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */\r\n#define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment for Filter 7 */\r\n#define CAN_FFA1R_FFA8_Pos     (8U)                                            \r\n#define CAN_FFA1R_FFA8_Msk     (0x1U << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */\r\n#define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment for Filter 8 */\r\n#define CAN_FFA1R_FFA9_Pos     (9U)                                            \r\n#define CAN_FFA1R_FFA9_Msk     (0x1U << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */\r\n#define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment for Filter 9 */\r\n#define CAN_FFA1R_FFA10_Pos    (10U)                                           \r\n#define CAN_FFA1R_FFA10_Msk    (0x1U << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */\r\n#define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment for Filter 10 */\r\n#define CAN_FFA1R_FFA11_Pos    (11U)                                           \r\n#define CAN_FFA1R_FFA11_Msk    (0x1U << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */\r\n#define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment for Filter 11 */\r\n#define CAN_FFA1R_FFA12_Pos    (12U)                                           \r\n#define CAN_FFA1R_FFA12_Msk    (0x1U << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */\r\n#define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment for Filter 12 */\r\n#define CAN_FFA1R_FFA13_Pos    (13U)                                           \r\n#define CAN_FFA1R_FFA13_Msk    (0x1U << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */\r\n#define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment for Filter 13 */\r\n\r\n/*******************  Bit definition for CAN_FA1R register  *******************/\r\n#define CAN_FA1R_FACT_Pos      (0U)                                            \r\n#define CAN_FA1R_FACT_Msk      (0x3FFFU << CAN_FA1R_FACT_Pos)                  /*!< 0x00003FFF */\r\n#define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active    */\r\n#define CAN_FA1R_FACT0_Pos     (0U)                                            \r\n#define CAN_FA1R_FACT0_Msk     (0x1U << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */\r\n#define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter 0 Active  */\r\n#define CAN_FA1R_FACT1_Pos     (1U)                                            \r\n#define CAN_FA1R_FACT1_Msk     (0x1U << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */\r\n#define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter 1 Active  */\r\n#define CAN_FA1R_FACT2_Pos     (2U)                                            \r\n#define CAN_FA1R_FACT2_Msk     (0x1U << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */\r\n#define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter 2 Active  */\r\n#define CAN_FA1R_FACT3_Pos     (3U)                                            \r\n#define CAN_FA1R_FACT3_Msk     (0x1U << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */\r\n#define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter 3 Active  */\r\n#define CAN_FA1R_FACT4_Pos     (4U)                                            \r\n#define CAN_FA1R_FACT4_Msk     (0x1U << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */\r\n#define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter 4 Active  */\r\n#define CAN_FA1R_FACT5_Pos     (5U)                                            \r\n#define CAN_FA1R_FACT5_Msk     (0x1U << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */\r\n#define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter 5 Active  */\r\n#define CAN_FA1R_FACT6_Pos     (6U)                                            \r\n#define CAN_FA1R_FACT6_Msk     (0x1U << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */\r\n#define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter 6 Active  */\r\n#define CAN_FA1R_FACT7_Pos     (7U)                                            \r\n#define CAN_FA1R_FACT7_Msk     (0x1U << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */\r\n#define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter 7 Active  */\r\n#define CAN_FA1R_FACT8_Pos     (8U)                                            \r\n#define CAN_FA1R_FACT8_Msk     (0x1U << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */\r\n#define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter 8 Active  */\r\n#define CAN_FA1R_FACT9_Pos     (9U)                                            \r\n#define CAN_FA1R_FACT9_Msk     (0x1U << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */\r\n#define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter 9 Active  */\r\n#define CAN_FA1R_FACT10_Pos    (10U)                                           \r\n#define CAN_FA1R_FACT10_Msk    (0x1U << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */\r\n#define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter 10 Active */\r\n#define CAN_FA1R_FACT11_Pos    (11U)                                           \r\n#define CAN_FA1R_FACT11_Msk    (0x1U << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */\r\n#define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter 11 Active */\r\n#define CAN_FA1R_FACT12_Pos    (12U)                                           \r\n#define CAN_FA1R_FACT12_Msk    (0x1U << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */\r\n#define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter 12 Active */\r\n#define CAN_FA1R_FACT13_Pos    (13U)                                           \r\n#define CAN_FA1R_FACT13_Msk    (0x1U << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */\r\n#define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter 13 Active */\r\n\r\n/*******************  Bit definition for CAN_F0R1 register  *******************/\r\n#define CAN_F0R1_FB0_Pos       (0U)                                            \r\n#define CAN_F0R1_FB0_Msk       (0x1U << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */\r\n#define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */\r\n#define CAN_F0R1_FB1_Pos       (1U)                                            \r\n#define CAN_F0R1_FB1_Msk       (0x1U << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */\r\n#define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */\r\n#define CAN_F0R1_FB2_Pos       (2U)                                            \r\n#define CAN_F0R1_FB2_Msk       (0x1U << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */\r\n#define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */\r\n#define CAN_F0R1_FB3_Pos       (3U)                                            \r\n#define CAN_F0R1_FB3_Msk       (0x1U << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */\r\n#define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */\r\n#define CAN_F0R1_FB4_Pos       (4U)                                            \r\n#define CAN_F0R1_FB4_Msk       (0x1U << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */\r\n#define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */\r\n#define CAN_F0R1_FB5_Pos       (5U)                                            \r\n#define CAN_F0R1_FB5_Msk       (0x1U << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */\r\n#define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */\r\n#define CAN_F0R1_FB6_Pos       (6U)                                            \r\n#define CAN_F0R1_FB6_Msk       (0x1U << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */\r\n#define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */\r\n#define CAN_F0R1_FB7_Pos       (7U)                                            \r\n#define CAN_F0R1_FB7_Msk       (0x1U << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */\r\n#define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */\r\n#define CAN_F0R1_FB8_Pos       (8U)                                            \r\n#define CAN_F0R1_FB8_Msk       (0x1U << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */\r\n#define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */\r\n#define CAN_F0R1_FB9_Pos       (9U)                                            \r\n#define CAN_F0R1_FB9_Msk       (0x1U << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */\r\n#define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */\r\n#define CAN_F0R1_FB10_Pos      (10U)                                           \r\n#define CAN_F0R1_FB10_Msk      (0x1U << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */\r\n#define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */\r\n#define CAN_F0R1_FB11_Pos      (11U)                                           \r\n#define CAN_F0R1_FB11_Msk      (0x1U << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */\r\n#define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */\r\n#define CAN_F0R1_FB12_Pos      (12U)                                           \r\n#define CAN_F0R1_FB12_Msk      (0x1U << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */\r\n#define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */\r\n#define CAN_F0R1_FB13_Pos      (13U)                                           \r\n#define CAN_F0R1_FB13_Msk      (0x1U << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */\r\n#define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */\r\n#define CAN_F0R1_FB14_Pos      (14U)                                           \r\n#define CAN_F0R1_FB14_Msk      (0x1U << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */\r\n#define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */\r\n#define CAN_F0R1_FB15_Pos      (15U)                                           \r\n#define CAN_F0R1_FB15_Msk      (0x1U << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */\r\n#define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */\r\n#define CAN_F0R1_FB16_Pos      (16U)                                           \r\n#define CAN_F0R1_FB16_Msk      (0x1U << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */\r\n#define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */\r\n#define CAN_F0R1_FB17_Pos      (17U)                                           \r\n#define CAN_F0R1_FB17_Msk      (0x1U << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */\r\n#define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */\r\n#define CAN_F0R1_FB18_Pos      (18U)                                           \r\n#define CAN_F0R1_FB18_Msk      (0x1U << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */\r\n#define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */\r\n#define CAN_F0R1_FB19_Pos      (19U)                                           \r\n#define CAN_F0R1_FB19_Msk      (0x1U << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */\r\n#define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */\r\n#define CAN_F0R1_FB20_Pos      (20U)                                           \r\n#define CAN_F0R1_FB20_Msk      (0x1U << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */\r\n#define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */\r\n#define CAN_F0R1_FB21_Pos      (21U)                                           \r\n#define CAN_F0R1_FB21_Msk      (0x1U << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */\r\n#define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */\r\n#define CAN_F0R1_FB22_Pos      (22U)                                           \r\n#define CAN_F0R1_FB22_Msk      (0x1U << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */\r\n#define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */\r\n#define CAN_F0R1_FB23_Pos      (23U)                                           \r\n#define CAN_F0R1_FB23_Msk      (0x1U << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */\r\n#define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */\r\n#define CAN_F0R1_FB24_Pos      (24U)                                           \r\n#define CAN_F0R1_FB24_Msk      (0x1U << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */\r\n#define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */\r\n#define CAN_F0R1_FB25_Pos      (25U)                                           \r\n#define CAN_F0R1_FB25_Msk      (0x1U << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */\r\n#define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */\r\n#define CAN_F0R1_FB26_Pos      (26U)                                           \r\n#define CAN_F0R1_FB26_Msk      (0x1U << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */\r\n#define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */\r\n#define CAN_F0R1_FB27_Pos      (27U)                                           \r\n#define CAN_F0R1_FB27_Msk      (0x1U << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */\r\n#define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */\r\n#define CAN_F0R1_FB28_Pos      (28U)                                           \r\n#define CAN_F0R1_FB28_Msk      (0x1U << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */\r\n#define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */\r\n#define CAN_F0R1_FB29_Pos      (29U)                                           \r\n#define CAN_F0R1_FB29_Msk      (0x1U << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */\r\n#define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */\r\n#define CAN_F0R1_FB30_Pos      (30U)                                           \r\n#define CAN_F0R1_FB30_Msk      (0x1U << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */\r\n#define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */\r\n#define CAN_F0R1_FB31_Pos      (31U)                                           \r\n#define CAN_F0R1_FB31_Msk      (0x1U << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */\r\n#define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F1R1 register  *******************/\r\n#define CAN_F1R1_FB0_Pos       (0U)                                            \r\n#define CAN_F1R1_FB0_Msk       (0x1U << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */\r\n#define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */\r\n#define CAN_F1R1_FB1_Pos       (1U)                                            \r\n#define CAN_F1R1_FB1_Msk       (0x1U << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */\r\n#define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */\r\n#define CAN_F1R1_FB2_Pos       (2U)                                            \r\n#define CAN_F1R1_FB2_Msk       (0x1U << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */\r\n#define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */\r\n#define CAN_F1R1_FB3_Pos       (3U)                                            \r\n#define CAN_F1R1_FB3_Msk       (0x1U << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */\r\n#define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */\r\n#define CAN_F1R1_FB4_Pos       (4U)                                            \r\n#define CAN_F1R1_FB4_Msk       (0x1U << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */\r\n#define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */\r\n#define CAN_F1R1_FB5_Pos       (5U)                                            \r\n#define CAN_F1R1_FB5_Msk       (0x1U << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */\r\n#define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */\r\n#define CAN_F1R1_FB6_Pos       (6U)                                            \r\n#define CAN_F1R1_FB6_Msk       (0x1U << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */\r\n#define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */\r\n#define CAN_F1R1_FB7_Pos       (7U)                                            \r\n#define CAN_F1R1_FB7_Msk       (0x1U << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */\r\n#define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */\r\n#define CAN_F1R1_FB8_Pos       (8U)                                            \r\n#define CAN_F1R1_FB8_Msk       (0x1U << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */\r\n#define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */\r\n#define CAN_F1R1_FB9_Pos       (9U)                                            \r\n#define CAN_F1R1_FB9_Msk       (0x1U << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */\r\n#define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */\r\n#define CAN_F1R1_FB10_Pos      (10U)                                           \r\n#define CAN_F1R1_FB10_Msk      (0x1U << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */\r\n#define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */\r\n#define CAN_F1R1_FB11_Pos      (11U)                                           \r\n#define CAN_F1R1_FB11_Msk      (0x1U << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */\r\n#define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */\r\n#define CAN_F1R1_FB12_Pos      (12U)                                           \r\n#define CAN_F1R1_FB12_Msk      (0x1U << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */\r\n#define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */\r\n#define CAN_F1R1_FB13_Pos      (13U)                                           \r\n#define CAN_F1R1_FB13_Msk      (0x1U << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */\r\n#define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */\r\n#define CAN_F1R1_FB14_Pos      (14U)                                           \r\n#define CAN_F1R1_FB14_Msk      (0x1U << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */\r\n#define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */\r\n#define CAN_F1R1_FB15_Pos      (15U)                                           \r\n#define CAN_F1R1_FB15_Msk      (0x1U << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */\r\n#define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */\r\n#define CAN_F1R1_FB16_Pos      (16U)                                           \r\n#define CAN_F1R1_FB16_Msk      (0x1U << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */\r\n#define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */\r\n#define CAN_F1R1_FB17_Pos      (17U)                                           \r\n#define CAN_F1R1_FB17_Msk      (0x1U << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */\r\n#define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */\r\n#define CAN_F1R1_FB18_Pos      (18U)                                           \r\n#define CAN_F1R1_FB18_Msk      (0x1U << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */\r\n#define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */\r\n#define CAN_F1R1_FB19_Pos      (19U)                                           \r\n#define CAN_F1R1_FB19_Msk      (0x1U << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */\r\n#define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */\r\n#define CAN_F1R1_FB20_Pos      (20U)                                           \r\n#define CAN_F1R1_FB20_Msk      (0x1U << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */\r\n#define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */\r\n#define CAN_F1R1_FB21_Pos      (21U)                                           \r\n#define CAN_F1R1_FB21_Msk      (0x1U << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */\r\n#define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */\r\n#define CAN_F1R1_FB22_Pos      (22U)                                           \r\n#define CAN_F1R1_FB22_Msk      (0x1U << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */\r\n#define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */\r\n#define CAN_F1R1_FB23_Pos      (23U)                                           \r\n#define CAN_F1R1_FB23_Msk      (0x1U << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */\r\n#define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */\r\n#define CAN_F1R1_FB24_Pos      (24U)                                           \r\n#define CAN_F1R1_FB24_Msk      (0x1U << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */\r\n#define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */\r\n#define CAN_F1R1_FB25_Pos      (25U)                                           \r\n#define CAN_F1R1_FB25_Msk      (0x1U << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */\r\n#define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */\r\n#define CAN_F1R1_FB26_Pos      (26U)                                           \r\n#define CAN_F1R1_FB26_Msk      (0x1U << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */\r\n#define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */\r\n#define CAN_F1R1_FB27_Pos      (27U)                                           \r\n#define CAN_F1R1_FB27_Msk      (0x1U << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */\r\n#define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */\r\n#define CAN_F1R1_FB28_Pos      (28U)                                           \r\n#define CAN_F1R1_FB28_Msk      (0x1U << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */\r\n#define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */\r\n#define CAN_F1R1_FB29_Pos      (29U)                                           \r\n#define CAN_F1R1_FB29_Msk      (0x1U << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */\r\n#define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */\r\n#define CAN_F1R1_FB30_Pos      (30U)                                           \r\n#define CAN_F1R1_FB30_Msk      (0x1U << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */\r\n#define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */\r\n#define CAN_F1R1_FB31_Pos      (31U)                                           \r\n#define CAN_F1R1_FB31_Msk      (0x1U << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */\r\n#define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F2R1 register  *******************/\r\n#define CAN_F2R1_FB0_Pos       (0U)                                            \r\n#define CAN_F2R1_FB0_Msk       (0x1U << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */\r\n#define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */\r\n#define CAN_F2R1_FB1_Pos       (1U)                                            \r\n#define CAN_F2R1_FB1_Msk       (0x1U << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */\r\n#define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */\r\n#define CAN_F2R1_FB2_Pos       (2U)                                            \r\n#define CAN_F2R1_FB2_Msk       (0x1U << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */\r\n#define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */\r\n#define CAN_F2R1_FB3_Pos       (3U)                                            \r\n#define CAN_F2R1_FB3_Msk       (0x1U << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */\r\n#define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */\r\n#define CAN_F2R1_FB4_Pos       (4U)                                            \r\n#define CAN_F2R1_FB4_Msk       (0x1U << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */\r\n#define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */\r\n#define CAN_F2R1_FB5_Pos       (5U)                                            \r\n#define CAN_F2R1_FB5_Msk       (0x1U << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */\r\n#define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */\r\n#define CAN_F2R1_FB6_Pos       (6U)                                            \r\n#define CAN_F2R1_FB6_Msk       (0x1U << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */\r\n#define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */\r\n#define CAN_F2R1_FB7_Pos       (7U)                                            \r\n#define CAN_F2R1_FB7_Msk       (0x1U << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */\r\n#define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */\r\n#define CAN_F2R1_FB8_Pos       (8U)                                            \r\n#define CAN_F2R1_FB8_Msk       (0x1U << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */\r\n#define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */\r\n#define CAN_F2R1_FB9_Pos       (9U)                                            \r\n#define CAN_F2R1_FB9_Msk       (0x1U << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */\r\n#define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */\r\n#define CAN_F2R1_FB10_Pos      (10U)                                           \r\n#define CAN_F2R1_FB10_Msk      (0x1U << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */\r\n#define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */\r\n#define CAN_F2R1_FB11_Pos      (11U)                                           \r\n#define CAN_F2R1_FB11_Msk      (0x1U << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */\r\n#define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */\r\n#define CAN_F2R1_FB12_Pos      (12U)                                           \r\n#define CAN_F2R1_FB12_Msk      (0x1U << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */\r\n#define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */\r\n#define CAN_F2R1_FB13_Pos      (13U)                                           \r\n#define CAN_F2R1_FB13_Msk      (0x1U << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */\r\n#define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */\r\n#define CAN_F2R1_FB14_Pos      (14U)                                           \r\n#define CAN_F2R1_FB14_Msk      (0x1U << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */\r\n#define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */\r\n#define CAN_F2R1_FB15_Pos      (15U)                                           \r\n#define CAN_F2R1_FB15_Msk      (0x1U << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */\r\n#define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */\r\n#define CAN_F2R1_FB16_Pos      (16U)                                           \r\n#define CAN_F2R1_FB16_Msk      (0x1U << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */\r\n#define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */\r\n#define CAN_F2R1_FB17_Pos      (17U)                                           \r\n#define CAN_F2R1_FB17_Msk      (0x1U << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */\r\n#define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */\r\n#define CAN_F2R1_FB18_Pos      (18U)                                           \r\n#define CAN_F2R1_FB18_Msk      (0x1U << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */\r\n#define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */\r\n#define CAN_F2R1_FB19_Pos      (19U)                                           \r\n#define CAN_F2R1_FB19_Msk      (0x1U << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */\r\n#define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */\r\n#define CAN_F2R1_FB20_Pos      (20U)                                           \r\n#define CAN_F2R1_FB20_Msk      (0x1U << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */\r\n#define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */\r\n#define CAN_F2R1_FB21_Pos      (21U)                                           \r\n#define CAN_F2R1_FB21_Msk      (0x1U << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */\r\n#define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */\r\n#define CAN_F2R1_FB22_Pos      (22U)                                           \r\n#define CAN_F2R1_FB22_Msk      (0x1U << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */\r\n#define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */\r\n#define CAN_F2R1_FB23_Pos      (23U)                                           \r\n#define CAN_F2R1_FB23_Msk      (0x1U << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */\r\n#define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */\r\n#define CAN_F2R1_FB24_Pos      (24U)                                           \r\n#define CAN_F2R1_FB24_Msk      (0x1U << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */\r\n#define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */\r\n#define CAN_F2R1_FB25_Pos      (25U)                                           \r\n#define CAN_F2R1_FB25_Msk      (0x1U << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */\r\n#define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */\r\n#define CAN_F2R1_FB26_Pos      (26U)                                           \r\n#define CAN_F2R1_FB26_Msk      (0x1U << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */\r\n#define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */\r\n#define CAN_F2R1_FB27_Pos      (27U)                                           \r\n#define CAN_F2R1_FB27_Msk      (0x1U << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */\r\n#define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */\r\n#define CAN_F2R1_FB28_Pos      (28U)                                           \r\n#define CAN_F2R1_FB28_Msk      (0x1U << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */\r\n#define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */\r\n#define CAN_F2R1_FB29_Pos      (29U)                                           \r\n#define CAN_F2R1_FB29_Msk      (0x1U << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */\r\n#define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */\r\n#define CAN_F2R1_FB30_Pos      (30U)                                           \r\n#define CAN_F2R1_FB30_Msk      (0x1U << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */\r\n#define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */\r\n#define CAN_F2R1_FB31_Pos      (31U)                                           \r\n#define CAN_F2R1_FB31_Msk      (0x1U << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */\r\n#define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F3R1 register  *******************/\r\n#define CAN_F3R1_FB0_Pos       (0U)                                            \r\n#define CAN_F3R1_FB0_Msk       (0x1U << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */\r\n#define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */\r\n#define CAN_F3R1_FB1_Pos       (1U)                                            \r\n#define CAN_F3R1_FB1_Msk       (0x1U << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */\r\n#define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */\r\n#define CAN_F3R1_FB2_Pos       (2U)                                            \r\n#define CAN_F3R1_FB2_Msk       (0x1U << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */\r\n#define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */\r\n#define CAN_F3R1_FB3_Pos       (3U)                                            \r\n#define CAN_F3R1_FB3_Msk       (0x1U << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */\r\n#define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */\r\n#define CAN_F3R1_FB4_Pos       (4U)                                            \r\n#define CAN_F3R1_FB4_Msk       (0x1U << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */\r\n#define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */\r\n#define CAN_F3R1_FB5_Pos       (5U)                                            \r\n#define CAN_F3R1_FB5_Msk       (0x1U << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */\r\n#define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */\r\n#define CAN_F3R1_FB6_Pos       (6U)                                            \r\n#define CAN_F3R1_FB6_Msk       (0x1U << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */\r\n#define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */\r\n#define CAN_F3R1_FB7_Pos       (7U)                                            \r\n#define CAN_F3R1_FB7_Msk       (0x1U << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */\r\n#define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */\r\n#define CAN_F3R1_FB8_Pos       (8U)                                            \r\n#define CAN_F3R1_FB8_Msk       (0x1U << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */\r\n#define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */\r\n#define CAN_F3R1_FB9_Pos       (9U)                                            \r\n#define CAN_F3R1_FB9_Msk       (0x1U << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */\r\n#define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */\r\n#define CAN_F3R1_FB10_Pos      (10U)                                           \r\n#define CAN_F3R1_FB10_Msk      (0x1U << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */\r\n#define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */\r\n#define CAN_F3R1_FB11_Pos      (11U)                                           \r\n#define CAN_F3R1_FB11_Msk      (0x1U << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */\r\n#define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */\r\n#define CAN_F3R1_FB12_Pos      (12U)                                           \r\n#define CAN_F3R1_FB12_Msk      (0x1U << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */\r\n#define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */\r\n#define CAN_F3R1_FB13_Pos      (13U)                                           \r\n#define CAN_F3R1_FB13_Msk      (0x1U << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */\r\n#define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */\r\n#define CAN_F3R1_FB14_Pos      (14U)                                           \r\n#define CAN_F3R1_FB14_Msk      (0x1U << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */\r\n#define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */\r\n#define CAN_F3R1_FB15_Pos      (15U)                                           \r\n#define CAN_F3R1_FB15_Msk      (0x1U << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */\r\n#define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */\r\n#define CAN_F3R1_FB16_Pos      (16U)                                           \r\n#define CAN_F3R1_FB16_Msk      (0x1U << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */\r\n#define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */\r\n#define CAN_F3R1_FB17_Pos      (17U)                                           \r\n#define CAN_F3R1_FB17_Msk      (0x1U << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */\r\n#define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */\r\n#define CAN_F3R1_FB18_Pos      (18U)                                           \r\n#define CAN_F3R1_FB18_Msk      (0x1U << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */\r\n#define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */\r\n#define CAN_F3R1_FB19_Pos      (19U)                                           \r\n#define CAN_F3R1_FB19_Msk      (0x1U << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */\r\n#define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */\r\n#define CAN_F3R1_FB20_Pos      (20U)                                           \r\n#define CAN_F3R1_FB20_Msk      (0x1U << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */\r\n#define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */\r\n#define CAN_F3R1_FB21_Pos      (21U)                                           \r\n#define CAN_F3R1_FB21_Msk      (0x1U << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */\r\n#define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */\r\n#define CAN_F3R1_FB22_Pos      (22U)                                           \r\n#define CAN_F3R1_FB22_Msk      (0x1U << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */\r\n#define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */\r\n#define CAN_F3R1_FB23_Pos      (23U)                                           \r\n#define CAN_F3R1_FB23_Msk      (0x1U << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */\r\n#define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */\r\n#define CAN_F3R1_FB24_Pos      (24U)                                           \r\n#define CAN_F3R1_FB24_Msk      (0x1U << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */\r\n#define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */\r\n#define CAN_F3R1_FB25_Pos      (25U)                                           \r\n#define CAN_F3R1_FB25_Msk      (0x1U << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */\r\n#define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */\r\n#define CAN_F3R1_FB26_Pos      (26U)                                           \r\n#define CAN_F3R1_FB26_Msk      (0x1U << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */\r\n#define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */\r\n#define CAN_F3R1_FB27_Pos      (27U)                                           \r\n#define CAN_F3R1_FB27_Msk      (0x1U << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */\r\n#define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */\r\n#define CAN_F3R1_FB28_Pos      (28U)                                           \r\n#define CAN_F3R1_FB28_Msk      (0x1U << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */\r\n#define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */\r\n#define CAN_F3R1_FB29_Pos      (29U)                                           \r\n#define CAN_F3R1_FB29_Msk      (0x1U << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */\r\n#define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */\r\n#define CAN_F3R1_FB30_Pos      (30U)                                           \r\n#define CAN_F3R1_FB30_Msk      (0x1U << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */\r\n#define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */\r\n#define CAN_F3R1_FB31_Pos      (31U)                                           \r\n#define CAN_F3R1_FB31_Msk      (0x1U << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */\r\n#define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F4R1 register  *******************/\r\n#define CAN_F4R1_FB0_Pos       (0U)                                            \r\n#define CAN_F4R1_FB0_Msk       (0x1U << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */\r\n#define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */\r\n#define CAN_F4R1_FB1_Pos       (1U)                                            \r\n#define CAN_F4R1_FB1_Msk       (0x1U << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */\r\n#define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */\r\n#define CAN_F4R1_FB2_Pos       (2U)                                            \r\n#define CAN_F4R1_FB2_Msk       (0x1U << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */\r\n#define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */\r\n#define CAN_F4R1_FB3_Pos       (3U)                                            \r\n#define CAN_F4R1_FB3_Msk       (0x1U << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */\r\n#define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */\r\n#define CAN_F4R1_FB4_Pos       (4U)                                            \r\n#define CAN_F4R1_FB4_Msk       (0x1U << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */\r\n#define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */\r\n#define CAN_F4R1_FB5_Pos       (5U)                                            \r\n#define CAN_F4R1_FB5_Msk       (0x1U << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */\r\n#define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */\r\n#define CAN_F4R1_FB6_Pos       (6U)                                            \r\n#define CAN_F4R1_FB6_Msk       (0x1U << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */\r\n#define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */\r\n#define CAN_F4R1_FB7_Pos       (7U)                                            \r\n#define CAN_F4R1_FB7_Msk       (0x1U << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */\r\n#define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */\r\n#define CAN_F4R1_FB8_Pos       (8U)                                            \r\n#define CAN_F4R1_FB8_Msk       (0x1U << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */\r\n#define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */\r\n#define CAN_F4R1_FB9_Pos       (9U)                                            \r\n#define CAN_F4R1_FB9_Msk       (0x1U << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */\r\n#define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */\r\n#define CAN_F4R1_FB10_Pos      (10U)                                           \r\n#define CAN_F4R1_FB10_Msk      (0x1U << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */\r\n#define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */\r\n#define CAN_F4R1_FB11_Pos      (11U)                                           \r\n#define CAN_F4R1_FB11_Msk      (0x1U << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */\r\n#define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */\r\n#define CAN_F4R1_FB12_Pos      (12U)                                           \r\n#define CAN_F4R1_FB12_Msk      (0x1U << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */\r\n#define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */\r\n#define CAN_F4R1_FB13_Pos      (13U)                                           \r\n#define CAN_F4R1_FB13_Msk      (0x1U << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */\r\n#define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */\r\n#define CAN_F4R1_FB14_Pos      (14U)                                           \r\n#define CAN_F4R1_FB14_Msk      (0x1U << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */\r\n#define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */\r\n#define CAN_F4R1_FB15_Pos      (15U)                                           \r\n#define CAN_F4R1_FB15_Msk      (0x1U << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */\r\n#define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */\r\n#define CAN_F4R1_FB16_Pos      (16U)                                           \r\n#define CAN_F4R1_FB16_Msk      (0x1U << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */\r\n#define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */\r\n#define CAN_F4R1_FB17_Pos      (17U)                                           \r\n#define CAN_F4R1_FB17_Msk      (0x1U << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */\r\n#define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */\r\n#define CAN_F4R1_FB18_Pos      (18U)                                           \r\n#define CAN_F4R1_FB18_Msk      (0x1U << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */\r\n#define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */\r\n#define CAN_F4R1_FB19_Pos      (19U)                                           \r\n#define CAN_F4R1_FB19_Msk      (0x1U << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */\r\n#define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */\r\n#define CAN_F4R1_FB20_Pos      (20U)                                           \r\n#define CAN_F4R1_FB20_Msk      (0x1U << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */\r\n#define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */\r\n#define CAN_F4R1_FB21_Pos      (21U)                                           \r\n#define CAN_F4R1_FB21_Msk      (0x1U << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */\r\n#define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */\r\n#define CAN_F4R1_FB22_Pos      (22U)                                           \r\n#define CAN_F4R1_FB22_Msk      (0x1U << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */\r\n#define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */\r\n#define CAN_F4R1_FB23_Pos      (23U)                                           \r\n#define CAN_F4R1_FB23_Msk      (0x1U << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */\r\n#define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */\r\n#define CAN_F4R1_FB24_Pos      (24U)                                           \r\n#define CAN_F4R1_FB24_Msk      (0x1U << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */\r\n#define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */\r\n#define CAN_F4R1_FB25_Pos      (25U)                                           \r\n#define CAN_F4R1_FB25_Msk      (0x1U << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */\r\n#define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */\r\n#define CAN_F4R1_FB26_Pos      (26U)                                           \r\n#define CAN_F4R1_FB26_Msk      (0x1U << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */\r\n#define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */\r\n#define CAN_F4R1_FB27_Pos      (27U)                                           \r\n#define CAN_F4R1_FB27_Msk      (0x1U << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */\r\n#define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */\r\n#define CAN_F4R1_FB28_Pos      (28U)                                           \r\n#define CAN_F4R1_FB28_Msk      (0x1U << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */\r\n#define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */\r\n#define CAN_F4R1_FB29_Pos      (29U)                                           \r\n#define CAN_F4R1_FB29_Msk      (0x1U << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */\r\n#define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */\r\n#define CAN_F4R1_FB30_Pos      (30U)                                           \r\n#define CAN_F4R1_FB30_Msk      (0x1U << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */\r\n#define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */\r\n#define CAN_F4R1_FB31_Pos      (31U)                                           \r\n#define CAN_F4R1_FB31_Msk      (0x1U << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */\r\n#define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F5R1 register  *******************/\r\n#define CAN_F5R1_FB0_Pos       (0U)                                            \r\n#define CAN_F5R1_FB0_Msk       (0x1U << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */\r\n#define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */\r\n#define CAN_F5R1_FB1_Pos       (1U)                                            \r\n#define CAN_F5R1_FB1_Msk       (0x1U << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */\r\n#define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */\r\n#define CAN_F5R1_FB2_Pos       (2U)                                            \r\n#define CAN_F5R1_FB2_Msk       (0x1U << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */\r\n#define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */\r\n#define CAN_F5R1_FB3_Pos       (3U)                                            \r\n#define CAN_F5R1_FB3_Msk       (0x1U << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */\r\n#define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */\r\n#define CAN_F5R1_FB4_Pos       (4U)                                            \r\n#define CAN_F5R1_FB4_Msk       (0x1U << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */\r\n#define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */\r\n#define CAN_F5R1_FB5_Pos       (5U)                                            \r\n#define CAN_F5R1_FB5_Msk       (0x1U << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */\r\n#define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */\r\n#define CAN_F5R1_FB6_Pos       (6U)                                            \r\n#define CAN_F5R1_FB6_Msk       (0x1U << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */\r\n#define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */\r\n#define CAN_F5R1_FB7_Pos       (7U)                                            \r\n#define CAN_F5R1_FB7_Msk       (0x1U << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */\r\n#define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */\r\n#define CAN_F5R1_FB8_Pos       (8U)                                            \r\n#define CAN_F5R1_FB8_Msk       (0x1U << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */\r\n#define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */\r\n#define CAN_F5R1_FB9_Pos       (9U)                                            \r\n#define CAN_F5R1_FB9_Msk       (0x1U << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */\r\n#define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */\r\n#define CAN_F5R1_FB10_Pos      (10U)                                           \r\n#define CAN_F5R1_FB10_Msk      (0x1U << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */\r\n#define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */\r\n#define CAN_F5R1_FB11_Pos      (11U)                                           \r\n#define CAN_F5R1_FB11_Msk      (0x1U << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */\r\n#define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */\r\n#define CAN_F5R1_FB12_Pos      (12U)                                           \r\n#define CAN_F5R1_FB12_Msk      (0x1U << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */\r\n#define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */\r\n#define CAN_F5R1_FB13_Pos      (13U)                                           \r\n#define CAN_F5R1_FB13_Msk      (0x1U << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */\r\n#define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */\r\n#define CAN_F5R1_FB14_Pos      (14U)                                           \r\n#define CAN_F5R1_FB14_Msk      (0x1U << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */\r\n#define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */\r\n#define CAN_F5R1_FB15_Pos      (15U)                                           \r\n#define CAN_F5R1_FB15_Msk      (0x1U << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */\r\n#define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */\r\n#define CAN_F5R1_FB16_Pos      (16U)                                           \r\n#define CAN_F5R1_FB16_Msk      (0x1U << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */\r\n#define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */\r\n#define CAN_F5R1_FB17_Pos      (17U)                                           \r\n#define CAN_F5R1_FB17_Msk      (0x1U << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */\r\n#define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */\r\n#define CAN_F5R1_FB18_Pos      (18U)                                           \r\n#define CAN_F5R1_FB18_Msk      (0x1U << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */\r\n#define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */\r\n#define CAN_F5R1_FB19_Pos      (19U)                                           \r\n#define CAN_F5R1_FB19_Msk      (0x1U << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */\r\n#define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */\r\n#define CAN_F5R1_FB20_Pos      (20U)                                           \r\n#define CAN_F5R1_FB20_Msk      (0x1U << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */\r\n#define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */\r\n#define CAN_F5R1_FB21_Pos      (21U)                                           \r\n#define CAN_F5R1_FB21_Msk      (0x1U << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */\r\n#define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */\r\n#define CAN_F5R1_FB22_Pos      (22U)                                           \r\n#define CAN_F5R1_FB22_Msk      (0x1U << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */\r\n#define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */\r\n#define CAN_F5R1_FB23_Pos      (23U)                                           \r\n#define CAN_F5R1_FB23_Msk      (0x1U << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */\r\n#define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */\r\n#define CAN_F5R1_FB24_Pos      (24U)                                           \r\n#define CAN_F5R1_FB24_Msk      (0x1U << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */\r\n#define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */\r\n#define CAN_F5R1_FB25_Pos      (25U)                                           \r\n#define CAN_F5R1_FB25_Msk      (0x1U << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */\r\n#define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */\r\n#define CAN_F5R1_FB26_Pos      (26U)                                           \r\n#define CAN_F5R1_FB26_Msk      (0x1U << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */\r\n#define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */\r\n#define CAN_F5R1_FB27_Pos      (27U)                                           \r\n#define CAN_F5R1_FB27_Msk      (0x1U << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */\r\n#define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */\r\n#define CAN_F5R1_FB28_Pos      (28U)                                           \r\n#define CAN_F5R1_FB28_Msk      (0x1U << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */\r\n#define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */\r\n#define CAN_F5R1_FB29_Pos      (29U)                                           \r\n#define CAN_F5R1_FB29_Msk      (0x1U << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */\r\n#define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */\r\n#define CAN_F5R1_FB30_Pos      (30U)                                           \r\n#define CAN_F5R1_FB30_Msk      (0x1U << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */\r\n#define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */\r\n#define CAN_F5R1_FB31_Pos      (31U)                                           \r\n#define CAN_F5R1_FB31_Msk      (0x1U << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */\r\n#define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F6R1 register  *******************/\r\n#define CAN_F6R1_FB0_Pos       (0U)                                            \r\n#define CAN_F6R1_FB0_Msk       (0x1U << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */\r\n#define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */\r\n#define CAN_F6R1_FB1_Pos       (1U)                                            \r\n#define CAN_F6R1_FB1_Msk       (0x1U << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */\r\n#define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */\r\n#define CAN_F6R1_FB2_Pos       (2U)                                            \r\n#define CAN_F6R1_FB2_Msk       (0x1U << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */\r\n#define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */\r\n#define CAN_F6R1_FB3_Pos       (3U)                                            \r\n#define CAN_F6R1_FB3_Msk       (0x1U << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */\r\n#define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */\r\n#define CAN_F6R1_FB4_Pos       (4U)                                            \r\n#define CAN_F6R1_FB4_Msk       (0x1U << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */\r\n#define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */\r\n#define CAN_F6R1_FB5_Pos       (5U)                                            \r\n#define CAN_F6R1_FB5_Msk       (0x1U << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */\r\n#define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */\r\n#define CAN_F6R1_FB6_Pos       (6U)                                            \r\n#define CAN_F6R1_FB6_Msk       (0x1U << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */\r\n#define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */\r\n#define CAN_F6R1_FB7_Pos       (7U)                                            \r\n#define CAN_F6R1_FB7_Msk       (0x1U << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */\r\n#define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */\r\n#define CAN_F6R1_FB8_Pos       (8U)                                            \r\n#define CAN_F6R1_FB8_Msk       (0x1U << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */\r\n#define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */\r\n#define CAN_F6R1_FB9_Pos       (9U)                                            \r\n#define CAN_F6R1_FB9_Msk       (0x1U << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */\r\n#define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */\r\n#define CAN_F6R1_FB10_Pos      (10U)                                           \r\n#define CAN_F6R1_FB10_Msk      (0x1U << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */\r\n#define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */\r\n#define CAN_F6R1_FB11_Pos      (11U)                                           \r\n#define CAN_F6R1_FB11_Msk      (0x1U << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */\r\n#define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */\r\n#define CAN_F6R1_FB12_Pos      (12U)                                           \r\n#define CAN_F6R1_FB12_Msk      (0x1U << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */\r\n#define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */\r\n#define CAN_F6R1_FB13_Pos      (13U)                                           \r\n#define CAN_F6R1_FB13_Msk      (0x1U << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */\r\n#define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */\r\n#define CAN_F6R1_FB14_Pos      (14U)                                           \r\n#define CAN_F6R1_FB14_Msk      (0x1U << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */\r\n#define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */\r\n#define CAN_F6R1_FB15_Pos      (15U)                                           \r\n#define CAN_F6R1_FB15_Msk      (0x1U << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */\r\n#define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */\r\n#define CAN_F6R1_FB16_Pos      (16U)                                           \r\n#define CAN_F6R1_FB16_Msk      (0x1U << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */\r\n#define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */\r\n#define CAN_F6R1_FB17_Pos      (17U)                                           \r\n#define CAN_F6R1_FB17_Msk      (0x1U << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */\r\n#define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */\r\n#define CAN_F6R1_FB18_Pos      (18U)                                           \r\n#define CAN_F6R1_FB18_Msk      (0x1U << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */\r\n#define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */\r\n#define CAN_F6R1_FB19_Pos      (19U)                                           \r\n#define CAN_F6R1_FB19_Msk      (0x1U << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */\r\n#define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */\r\n#define CAN_F6R1_FB20_Pos      (20U)                                           \r\n#define CAN_F6R1_FB20_Msk      (0x1U << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */\r\n#define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */\r\n#define CAN_F6R1_FB21_Pos      (21U)                                           \r\n#define CAN_F6R1_FB21_Msk      (0x1U << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */\r\n#define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */\r\n#define CAN_F6R1_FB22_Pos      (22U)                                           \r\n#define CAN_F6R1_FB22_Msk      (0x1U << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */\r\n#define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */\r\n#define CAN_F6R1_FB23_Pos      (23U)                                           \r\n#define CAN_F6R1_FB23_Msk      (0x1U << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */\r\n#define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */\r\n#define CAN_F6R1_FB24_Pos      (24U)                                           \r\n#define CAN_F6R1_FB24_Msk      (0x1U << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */\r\n#define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */\r\n#define CAN_F6R1_FB25_Pos      (25U)                                           \r\n#define CAN_F6R1_FB25_Msk      (0x1U << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */\r\n#define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */\r\n#define CAN_F6R1_FB26_Pos      (26U)                                           \r\n#define CAN_F6R1_FB26_Msk      (0x1U << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */\r\n#define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */\r\n#define CAN_F6R1_FB27_Pos      (27U)                                           \r\n#define CAN_F6R1_FB27_Msk      (0x1U << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */\r\n#define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */\r\n#define CAN_F6R1_FB28_Pos      (28U)                                           \r\n#define CAN_F6R1_FB28_Msk      (0x1U << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */\r\n#define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */\r\n#define CAN_F6R1_FB29_Pos      (29U)                                           \r\n#define CAN_F6R1_FB29_Msk      (0x1U << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */\r\n#define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */\r\n#define CAN_F6R1_FB30_Pos      (30U)                                           \r\n#define CAN_F6R1_FB30_Msk      (0x1U << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */\r\n#define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */\r\n#define CAN_F6R1_FB31_Pos      (31U)                                           \r\n#define CAN_F6R1_FB31_Msk      (0x1U << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */\r\n#define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F7R1 register  *******************/\r\n#define CAN_F7R1_FB0_Pos       (0U)                                            \r\n#define CAN_F7R1_FB0_Msk       (0x1U << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */\r\n#define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */\r\n#define CAN_F7R1_FB1_Pos       (1U)                                            \r\n#define CAN_F7R1_FB1_Msk       (0x1U << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */\r\n#define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */\r\n#define CAN_F7R1_FB2_Pos       (2U)                                            \r\n#define CAN_F7R1_FB2_Msk       (0x1U << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */\r\n#define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */\r\n#define CAN_F7R1_FB3_Pos       (3U)                                            \r\n#define CAN_F7R1_FB3_Msk       (0x1U << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */\r\n#define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */\r\n#define CAN_F7R1_FB4_Pos       (4U)                                            \r\n#define CAN_F7R1_FB4_Msk       (0x1U << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */\r\n#define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */\r\n#define CAN_F7R1_FB5_Pos       (5U)                                            \r\n#define CAN_F7R1_FB5_Msk       (0x1U << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */\r\n#define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */\r\n#define CAN_F7R1_FB6_Pos       (6U)                                            \r\n#define CAN_F7R1_FB6_Msk       (0x1U << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */\r\n#define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */\r\n#define CAN_F7R1_FB7_Pos       (7U)                                            \r\n#define CAN_F7R1_FB7_Msk       (0x1U << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */\r\n#define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */\r\n#define CAN_F7R1_FB8_Pos       (8U)                                            \r\n#define CAN_F7R1_FB8_Msk       (0x1U << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */\r\n#define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */\r\n#define CAN_F7R1_FB9_Pos       (9U)                                            \r\n#define CAN_F7R1_FB9_Msk       (0x1U << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */\r\n#define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */\r\n#define CAN_F7R1_FB10_Pos      (10U)                                           \r\n#define CAN_F7R1_FB10_Msk      (0x1U << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */\r\n#define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */\r\n#define CAN_F7R1_FB11_Pos      (11U)                                           \r\n#define CAN_F7R1_FB11_Msk      (0x1U << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */\r\n#define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */\r\n#define CAN_F7R1_FB12_Pos      (12U)                                           \r\n#define CAN_F7R1_FB12_Msk      (0x1U << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */\r\n#define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */\r\n#define CAN_F7R1_FB13_Pos      (13U)                                           \r\n#define CAN_F7R1_FB13_Msk      (0x1U << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */\r\n#define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */\r\n#define CAN_F7R1_FB14_Pos      (14U)                                           \r\n#define CAN_F7R1_FB14_Msk      (0x1U << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */\r\n#define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */\r\n#define CAN_F7R1_FB15_Pos      (15U)                                           \r\n#define CAN_F7R1_FB15_Msk      (0x1U << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */\r\n#define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */\r\n#define CAN_F7R1_FB16_Pos      (16U)                                           \r\n#define CAN_F7R1_FB16_Msk      (0x1U << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */\r\n#define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */\r\n#define CAN_F7R1_FB17_Pos      (17U)                                           \r\n#define CAN_F7R1_FB17_Msk      (0x1U << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */\r\n#define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */\r\n#define CAN_F7R1_FB18_Pos      (18U)                                           \r\n#define CAN_F7R1_FB18_Msk      (0x1U << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */\r\n#define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */\r\n#define CAN_F7R1_FB19_Pos      (19U)                                           \r\n#define CAN_F7R1_FB19_Msk      (0x1U << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */\r\n#define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */\r\n#define CAN_F7R1_FB20_Pos      (20U)                                           \r\n#define CAN_F7R1_FB20_Msk      (0x1U << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */\r\n#define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */\r\n#define CAN_F7R1_FB21_Pos      (21U)                                           \r\n#define CAN_F7R1_FB21_Msk      (0x1U << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */\r\n#define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */\r\n#define CAN_F7R1_FB22_Pos      (22U)                                           \r\n#define CAN_F7R1_FB22_Msk      (0x1U << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */\r\n#define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */\r\n#define CAN_F7R1_FB23_Pos      (23U)                                           \r\n#define CAN_F7R1_FB23_Msk      (0x1U << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */\r\n#define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */\r\n#define CAN_F7R1_FB24_Pos      (24U)                                           \r\n#define CAN_F7R1_FB24_Msk      (0x1U << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */\r\n#define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */\r\n#define CAN_F7R1_FB25_Pos      (25U)                                           \r\n#define CAN_F7R1_FB25_Msk      (0x1U << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */\r\n#define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */\r\n#define CAN_F7R1_FB26_Pos      (26U)                                           \r\n#define CAN_F7R1_FB26_Msk      (0x1U << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */\r\n#define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */\r\n#define CAN_F7R1_FB27_Pos      (27U)                                           \r\n#define CAN_F7R1_FB27_Msk      (0x1U << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */\r\n#define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */\r\n#define CAN_F7R1_FB28_Pos      (28U)                                           \r\n#define CAN_F7R1_FB28_Msk      (0x1U << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */\r\n#define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */\r\n#define CAN_F7R1_FB29_Pos      (29U)                                           \r\n#define CAN_F7R1_FB29_Msk      (0x1U << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */\r\n#define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */\r\n#define CAN_F7R1_FB30_Pos      (30U)                                           \r\n#define CAN_F7R1_FB30_Msk      (0x1U << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */\r\n#define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */\r\n#define CAN_F7R1_FB31_Pos      (31U)                                           \r\n#define CAN_F7R1_FB31_Msk      (0x1U << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */\r\n#define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F8R1 register  *******************/\r\n#define CAN_F8R1_FB0_Pos       (0U)                                            \r\n#define CAN_F8R1_FB0_Msk       (0x1U << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */\r\n#define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */\r\n#define CAN_F8R1_FB1_Pos       (1U)                                            \r\n#define CAN_F8R1_FB1_Msk       (0x1U << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */\r\n#define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */\r\n#define CAN_F8R1_FB2_Pos       (2U)                                            \r\n#define CAN_F8R1_FB2_Msk       (0x1U << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */\r\n#define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */\r\n#define CAN_F8R1_FB3_Pos       (3U)                                            \r\n#define CAN_F8R1_FB3_Msk       (0x1U << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */\r\n#define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */\r\n#define CAN_F8R1_FB4_Pos       (4U)                                            \r\n#define CAN_F8R1_FB4_Msk       (0x1U << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */\r\n#define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */\r\n#define CAN_F8R1_FB5_Pos       (5U)                                            \r\n#define CAN_F8R1_FB5_Msk       (0x1U << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */\r\n#define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */\r\n#define CAN_F8R1_FB6_Pos       (6U)                                            \r\n#define CAN_F8R1_FB6_Msk       (0x1U << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */\r\n#define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */\r\n#define CAN_F8R1_FB7_Pos       (7U)                                            \r\n#define CAN_F8R1_FB7_Msk       (0x1U << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */\r\n#define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */\r\n#define CAN_F8R1_FB8_Pos       (8U)                                            \r\n#define CAN_F8R1_FB8_Msk       (0x1U << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */\r\n#define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */\r\n#define CAN_F8R1_FB9_Pos       (9U)                                            \r\n#define CAN_F8R1_FB9_Msk       (0x1U << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */\r\n#define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */\r\n#define CAN_F8R1_FB10_Pos      (10U)                                           \r\n#define CAN_F8R1_FB10_Msk      (0x1U << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */\r\n#define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */\r\n#define CAN_F8R1_FB11_Pos      (11U)                                           \r\n#define CAN_F8R1_FB11_Msk      (0x1U << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */\r\n#define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */\r\n#define CAN_F8R1_FB12_Pos      (12U)                                           \r\n#define CAN_F8R1_FB12_Msk      (0x1U << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */\r\n#define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */\r\n#define CAN_F8R1_FB13_Pos      (13U)                                           \r\n#define CAN_F8R1_FB13_Msk      (0x1U << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */\r\n#define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */\r\n#define CAN_F8R1_FB14_Pos      (14U)                                           \r\n#define CAN_F8R1_FB14_Msk      (0x1U << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */\r\n#define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */\r\n#define CAN_F8R1_FB15_Pos      (15U)                                           \r\n#define CAN_F8R1_FB15_Msk      (0x1U << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */\r\n#define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */\r\n#define CAN_F8R1_FB16_Pos      (16U)                                           \r\n#define CAN_F8R1_FB16_Msk      (0x1U << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */\r\n#define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */\r\n#define CAN_F8R1_FB17_Pos      (17U)                                           \r\n#define CAN_F8R1_FB17_Msk      (0x1U << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */\r\n#define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */\r\n#define CAN_F8R1_FB18_Pos      (18U)                                           \r\n#define CAN_F8R1_FB18_Msk      (0x1U << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */\r\n#define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */\r\n#define CAN_F8R1_FB19_Pos      (19U)                                           \r\n#define CAN_F8R1_FB19_Msk      (0x1U << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */\r\n#define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */\r\n#define CAN_F8R1_FB20_Pos      (20U)                                           \r\n#define CAN_F8R1_FB20_Msk      (0x1U << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */\r\n#define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */\r\n#define CAN_F8R1_FB21_Pos      (21U)                                           \r\n#define CAN_F8R1_FB21_Msk      (0x1U << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */\r\n#define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */\r\n#define CAN_F8R1_FB22_Pos      (22U)                                           \r\n#define CAN_F8R1_FB22_Msk      (0x1U << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */\r\n#define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */\r\n#define CAN_F8R1_FB23_Pos      (23U)                                           \r\n#define CAN_F8R1_FB23_Msk      (0x1U << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */\r\n#define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */\r\n#define CAN_F8R1_FB24_Pos      (24U)                                           \r\n#define CAN_F8R1_FB24_Msk      (0x1U << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */\r\n#define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */\r\n#define CAN_F8R1_FB25_Pos      (25U)                                           \r\n#define CAN_F8R1_FB25_Msk      (0x1U << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */\r\n#define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */\r\n#define CAN_F8R1_FB26_Pos      (26U)                                           \r\n#define CAN_F8R1_FB26_Msk      (0x1U << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */\r\n#define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */\r\n#define CAN_F8R1_FB27_Pos      (27U)                                           \r\n#define CAN_F8R1_FB27_Msk      (0x1U << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */\r\n#define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */\r\n#define CAN_F8R1_FB28_Pos      (28U)                                           \r\n#define CAN_F8R1_FB28_Msk      (0x1U << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */\r\n#define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */\r\n#define CAN_F8R1_FB29_Pos      (29U)                                           \r\n#define CAN_F8R1_FB29_Msk      (0x1U << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */\r\n#define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */\r\n#define CAN_F8R1_FB30_Pos      (30U)                                           \r\n#define CAN_F8R1_FB30_Msk      (0x1U << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */\r\n#define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */\r\n#define CAN_F8R1_FB31_Pos      (31U)                                           \r\n#define CAN_F8R1_FB31_Msk      (0x1U << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */\r\n#define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F9R1 register  *******************/\r\n#define CAN_F9R1_FB0_Pos       (0U)                                            \r\n#define CAN_F9R1_FB0_Msk       (0x1U << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */\r\n#define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */\r\n#define CAN_F9R1_FB1_Pos       (1U)                                            \r\n#define CAN_F9R1_FB1_Msk       (0x1U << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */\r\n#define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */\r\n#define CAN_F9R1_FB2_Pos       (2U)                                            \r\n#define CAN_F9R1_FB2_Msk       (0x1U << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */\r\n#define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */\r\n#define CAN_F9R1_FB3_Pos       (3U)                                            \r\n#define CAN_F9R1_FB3_Msk       (0x1U << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */\r\n#define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */\r\n#define CAN_F9R1_FB4_Pos       (4U)                                            \r\n#define CAN_F9R1_FB4_Msk       (0x1U << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */\r\n#define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */\r\n#define CAN_F9R1_FB5_Pos       (5U)                                            \r\n#define CAN_F9R1_FB5_Msk       (0x1U << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */\r\n#define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */\r\n#define CAN_F9R1_FB6_Pos       (6U)                                            \r\n#define CAN_F9R1_FB6_Msk       (0x1U << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */\r\n#define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */\r\n#define CAN_F9R1_FB7_Pos       (7U)                                            \r\n#define CAN_F9R1_FB7_Msk       (0x1U << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */\r\n#define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */\r\n#define CAN_F9R1_FB8_Pos       (8U)                                            \r\n#define CAN_F9R1_FB8_Msk       (0x1U << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */\r\n#define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */\r\n#define CAN_F9R1_FB9_Pos       (9U)                                            \r\n#define CAN_F9R1_FB9_Msk       (0x1U << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */\r\n#define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */\r\n#define CAN_F9R1_FB10_Pos      (10U)                                           \r\n#define CAN_F9R1_FB10_Msk      (0x1U << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */\r\n#define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */\r\n#define CAN_F9R1_FB11_Pos      (11U)                                           \r\n#define CAN_F9R1_FB11_Msk      (0x1U << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */\r\n#define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */\r\n#define CAN_F9R1_FB12_Pos      (12U)                                           \r\n#define CAN_F9R1_FB12_Msk      (0x1U << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */\r\n#define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */\r\n#define CAN_F9R1_FB13_Pos      (13U)                                           \r\n#define CAN_F9R1_FB13_Msk      (0x1U << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */\r\n#define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */\r\n#define CAN_F9R1_FB14_Pos      (14U)                                           \r\n#define CAN_F9R1_FB14_Msk      (0x1U << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */\r\n#define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */\r\n#define CAN_F9R1_FB15_Pos      (15U)                                           \r\n#define CAN_F9R1_FB15_Msk      (0x1U << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */\r\n#define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */\r\n#define CAN_F9R1_FB16_Pos      (16U)                                           \r\n#define CAN_F9R1_FB16_Msk      (0x1U << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */\r\n#define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */\r\n#define CAN_F9R1_FB17_Pos      (17U)                                           \r\n#define CAN_F9R1_FB17_Msk      (0x1U << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */\r\n#define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */\r\n#define CAN_F9R1_FB18_Pos      (18U)                                           \r\n#define CAN_F9R1_FB18_Msk      (0x1U << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */\r\n#define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */\r\n#define CAN_F9R1_FB19_Pos      (19U)                                           \r\n#define CAN_F9R1_FB19_Msk      (0x1U << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */\r\n#define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */\r\n#define CAN_F9R1_FB20_Pos      (20U)                                           \r\n#define CAN_F9R1_FB20_Msk      (0x1U << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */\r\n#define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */\r\n#define CAN_F9R1_FB21_Pos      (21U)                                           \r\n#define CAN_F9R1_FB21_Msk      (0x1U << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */\r\n#define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */\r\n#define CAN_F9R1_FB22_Pos      (22U)                                           \r\n#define CAN_F9R1_FB22_Msk      (0x1U << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */\r\n#define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */\r\n#define CAN_F9R1_FB23_Pos      (23U)                                           \r\n#define CAN_F9R1_FB23_Msk      (0x1U << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */\r\n#define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */\r\n#define CAN_F9R1_FB24_Pos      (24U)                                           \r\n#define CAN_F9R1_FB24_Msk      (0x1U << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */\r\n#define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */\r\n#define CAN_F9R1_FB25_Pos      (25U)                                           \r\n#define CAN_F9R1_FB25_Msk      (0x1U << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */\r\n#define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */\r\n#define CAN_F9R1_FB26_Pos      (26U)                                           \r\n#define CAN_F9R1_FB26_Msk      (0x1U << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */\r\n#define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */\r\n#define CAN_F9R1_FB27_Pos      (27U)                                           \r\n#define CAN_F9R1_FB27_Msk      (0x1U << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */\r\n#define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */\r\n#define CAN_F9R1_FB28_Pos      (28U)                                           \r\n#define CAN_F9R1_FB28_Msk      (0x1U << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */\r\n#define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */\r\n#define CAN_F9R1_FB29_Pos      (29U)                                           \r\n#define CAN_F9R1_FB29_Msk      (0x1U << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */\r\n#define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */\r\n#define CAN_F9R1_FB30_Pos      (30U)                                           \r\n#define CAN_F9R1_FB30_Msk      (0x1U << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */\r\n#define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */\r\n#define CAN_F9R1_FB31_Pos      (31U)                                           \r\n#define CAN_F9R1_FB31_Msk      (0x1U << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */\r\n#define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F10R1 register  ******************/\r\n#define CAN_F10R1_FB0_Pos      (0U)                                            \r\n#define CAN_F10R1_FB0_Msk      (0x1U << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */\r\n#define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */\r\n#define CAN_F10R1_FB1_Pos      (1U)                                            \r\n#define CAN_F10R1_FB1_Msk      (0x1U << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */\r\n#define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */\r\n#define CAN_F10R1_FB2_Pos      (2U)                                            \r\n#define CAN_F10R1_FB2_Msk      (0x1U << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */\r\n#define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */\r\n#define CAN_F10R1_FB3_Pos      (3U)                                            \r\n#define CAN_F10R1_FB3_Msk      (0x1U << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */\r\n#define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */\r\n#define CAN_F10R1_FB4_Pos      (4U)                                            \r\n#define CAN_F10R1_FB4_Msk      (0x1U << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */\r\n#define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */\r\n#define CAN_F10R1_FB5_Pos      (5U)                                            \r\n#define CAN_F10R1_FB5_Msk      (0x1U << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */\r\n#define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */\r\n#define CAN_F10R1_FB6_Pos      (6U)                                            \r\n#define CAN_F10R1_FB6_Msk      (0x1U << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */\r\n#define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */\r\n#define CAN_F10R1_FB7_Pos      (7U)                                            \r\n#define CAN_F10R1_FB7_Msk      (0x1U << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */\r\n#define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */\r\n#define CAN_F10R1_FB8_Pos      (8U)                                            \r\n#define CAN_F10R1_FB8_Msk      (0x1U << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */\r\n#define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */\r\n#define CAN_F10R1_FB9_Pos      (9U)                                            \r\n#define CAN_F10R1_FB9_Msk      (0x1U << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */\r\n#define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */\r\n#define CAN_F10R1_FB10_Pos     (10U)                                           \r\n#define CAN_F10R1_FB10_Msk     (0x1U << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */\r\n#define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */\r\n#define CAN_F10R1_FB11_Pos     (11U)                                           \r\n#define CAN_F10R1_FB11_Msk     (0x1U << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */\r\n#define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */\r\n#define CAN_F10R1_FB12_Pos     (12U)                                           \r\n#define CAN_F10R1_FB12_Msk     (0x1U << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */\r\n#define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */\r\n#define CAN_F10R1_FB13_Pos     (13U)                                           \r\n#define CAN_F10R1_FB13_Msk     (0x1U << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */\r\n#define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */\r\n#define CAN_F10R1_FB14_Pos     (14U)                                           \r\n#define CAN_F10R1_FB14_Msk     (0x1U << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */\r\n#define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */\r\n#define CAN_F10R1_FB15_Pos     (15U)                                           \r\n#define CAN_F10R1_FB15_Msk     (0x1U << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */\r\n#define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */\r\n#define CAN_F10R1_FB16_Pos     (16U)                                           \r\n#define CAN_F10R1_FB16_Msk     (0x1U << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */\r\n#define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */\r\n#define CAN_F10R1_FB17_Pos     (17U)                                           \r\n#define CAN_F10R1_FB17_Msk     (0x1U << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */\r\n#define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */\r\n#define CAN_F10R1_FB18_Pos     (18U)                                           \r\n#define CAN_F10R1_FB18_Msk     (0x1U << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */\r\n#define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */\r\n#define CAN_F10R1_FB19_Pos     (19U)                                           \r\n#define CAN_F10R1_FB19_Msk     (0x1U << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */\r\n#define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */\r\n#define CAN_F10R1_FB20_Pos     (20U)                                           \r\n#define CAN_F10R1_FB20_Msk     (0x1U << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */\r\n#define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */\r\n#define CAN_F10R1_FB21_Pos     (21U)                                           \r\n#define CAN_F10R1_FB21_Msk     (0x1U << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */\r\n#define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */\r\n#define CAN_F10R1_FB22_Pos     (22U)                                           \r\n#define CAN_F10R1_FB22_Msk     (0x1U << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */\r\n#define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */\r\n#define CAN_F10R1_FB23_Pos     (23U)                                           \r\n#define CAN_F10R1_FB23_Msk     (0x1U << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */\r\n#define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */\r\n#define CAN_F10R1_FB24_Pos     (24U)                                           \r\n#define CAN_F10R1_FB24_Msk     (0x1U << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */\r\n#define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */\r\n#define CAN_F10R1_FB25_Pos     (25U)                                           \r\n#define CAN_F10R1_FB25_Msk     (0x1U << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */\r\n#define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */\r\n#define CAN_F10R1_FB26_Pos     (26U)                                           \r\n#define CAN_F10R1_FB26_Msk     (0x1U << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */\r\n#define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */\r\n#define CAN_F10R1_FB27_Pos     (27U)                                           \r\n#define CAN_F10R1_FB27_Msk     (0x1U << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */\r\n#define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */\r\n#define CAN_F10R1_FB28_Pos     (28U)                                           \r\n#define CAN_F10R1_FB28_Msk     (0x1U << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */\r\n#define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */\r\n#define CAN_F10R1_FB29_Pos     (29U)                                           \r\n#define CAN_F10R1_FB29_Msk     (0x1U << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */\r\n#define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */\r\n#define CAN_F10R1_FB30_Pos     (30U)                                           \r\n#define CAN_F10R1_FB30_Msk     (0x1U << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */\r\n#define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */\r\n#define CAN_F10R1_FB31_Pos     (31U)                                           \r\n#define CAN_F10R1_FB31_Msk     (0x1U << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */\r\n#define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F11R1 register  ******************/\r\n#define CAN_F11R1_FB0_Pos      (0U)                                            \r\n#define CAN_F11R1_FB0_Msk      (0x1U << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */\r\n#define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */\r\n#define CAN_F11R1_FB1_Pos      (1U)                                            \r\n#define CAN_F11R1_FB1_Msk      (0x1U << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */\r\n#define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */\r\n#define CAN_F11R1_FB2_Pos      (2U)                                            \r\n#define CAN_F11R1_FB2_Msk      (0x1U << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */\r\n#define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */\r\n#define CAN_F11R1_FB3_Pos      (3U)                                            \r\n#define CAN_F11R1_FB3_Msk      (0x1U << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */\r\n#define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */\r\n#define CAN_F11R1_FB4_Pos      (4U)                                            \r\n#define CAN_F11R1_FB4_Msk      (0x1U << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */\r\n#define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */\r\n#define CAN_F11R1_FB5_Pos      (5U)                                            \r\n#define CAN_F11R1_FB5_Msk      (0x1U << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */\r\n#define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */\r\n#define CAN_F11R1_FB6_Pos      (6U)                                            \r\n#define CAN_F11R1_FB6_Msk      (0x1U << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */\r\n#define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */\r\n#define CAN_F11R1_FB7_Pos      (7U)                                            \r\n#define CAN_F11R1_FB7_Msk      (0x1U << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */\r\n#define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */\r\n#define CAN_F11R1_FB8_Pos      (8U)                                            \r\n#define CAN_F11R1_FB8_Msk      (0x1U << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */\r\n#define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */\r\n#define CAN_F11R1_FB9_Pos      (9U)                                            \r\n#define CAN_F11R1_FB9_Msk      (0x1U << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */\r\n#define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */\r\n#define CAN_F11R1_FB10_Pos     (10U)                                           \r\n#define CAN_F11R1_FB10_Msk     (0x1U << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */\r\n#define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */\r\n#define CAN_F11R1_FB11_Pos     (11U)                                           \r\n#define CAN_F11R1_FB11_Msk     (0x1U << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */\r\n#define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */\r\n#define CAN_F11R1_FB12_Pos     (12U)                                           \r\n#define CAN_F11R1_FB12_Msk     (0x1U << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */\r\n#define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */\r\n#define CAN_F11R1_FB13_Pos     (13U)                                           \r\n#define CAN_F11R1_FB13_Msk     (0x1U << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */\r\n#define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */\r\n#define CAN_F11R1_FB14_Pos     (14U)                                           \r\n#define CAN_F11R1_FB14_Msk     (0x1U << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */\r\n#define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */\r\n#define CAN_F11R1_FB15_Pos     (15U)                                           \r\n#define CAN_F11R1_FB15_Msk     (0x1U << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */\r\n#define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */\r\n#define CAN_F11R1_FB16_Pos     (16U)                                           \r\n#define CAN_F11R1_FB16_Msk     (0x1U << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */\r\n#define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */\r\n#define CAN_F11R1_FB17_Pos     (17U)                                           \r\n#define CAN_F11R1_FB17_Msk     (0x1U << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */\r\n#define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */\r\n#define CAN_F11R1_FB18_Pos     (18U)                                           \r\n#define CAN_F11R1_FB18_Msk     (0x1U << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */\r\n#define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */\r\n#define CAN_F11R1_FB19_Pos     (19U)                                           \r\n#define CAN_F11R1_FB19_Msk     (0x1U << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */\r\n#define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */\r\n#define CAN_F11R1_FB20_Pos     (20U)                                           \r\n#define CAN_F11R1_FB20_Msk     (0x1U << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */\r\n#define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */\r\n#define CAN_F11R1_FB21_Pos     (21U)                                           \r\n#define CAN_F11R1_FB21_Msk     (0x1U << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */\r\n#define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */\r\n#define CAN_F11R1_FB22_Pos     (22U)                                           \r\n#define CAN_F11R1_FB22_Msk     (0x1U << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */\r\n#define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */\r\n#define CAN_F11R1_FB23_Pos     (23U)                                           \r\n#define CAN_F11R1_FB23_Msk     (0x1U << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */\r\n#define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */\r\n#define CAN_F11R1_FB24_Pos     (24U)                                           \r\n#define CAN_F11R1_FB24_Msk     (0x1U << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */\r\n#define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */\r\n#define CAN_F11R1_FB25_Pos     (25U)                                           \r\n#define CAN_F11R1_FB25_Msk     (0x1U << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */\r\n#define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */\r\n#define CAN_F11R1_FB26_Pos     (26U)                                           \r\n#define CAN_F11R1_FB26_Msk     (0x1U << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */\r\n#define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */\r\n#define CAN_F11R1_FB27_Pos     (27U)                                           \r\n#define CAN_F11R1_FB27_Msk     (0x1U << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */\r\n#define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */\r\n#define CAN_F11R1_FB28_Pos     (28U)                                           \r\n#define CAN_F11R1_FB28_Msk     (0x1U << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */\r\n#define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */\r\n#define CAN_F11R1_FB29_Pos     (29U)                                           \r\n#define CAN_F11R1_FB29_Msk     (0x1U << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */\r\n#define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */\r\n#define CAN_F11R1_FB30_Pos     (30U)                                           \r\n#define CAN_F11R1_FB30_Msk     (0x1U << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */\r\n#define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */\r\n#define CAN_F11R1_FB31_Pos     (31U)                                           \r\n#define CAN_F11R1_FB31_Msk     (0x1U << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */\r\n#define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F12R1 register  ******************/\r\n#define CAN_F12R1_FB0_Pos      (0U)                                            \r\n#define CAN_F12R1_FB0_Msk      (0x1U << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */\r\n#define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */\r\n#define CAN_F12R1_FB1_Pos      (1U)                                            \r\n#define CAN_F12R1_FB1_Msk      (0x1U << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */\r\n#define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */\r\n#define CAN_F12R1_FB2_Pos      (2U)                                            \r\n#define CAN_F12R1_FB2_Msk      (0x1U << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */\r\n#define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */\r\n#define CAN_F12R1_FB3_Pos      (3U)                                            \r\n#define CAN_F12R1_FB3_Msk      (0x1U << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */\r\n#define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */\r\n#define CAN_F12R1_FB4_Pos      (4U)                                            \r\n#define CAN_F12R1_FB4_Msk      (0x1U << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */\r\n#define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */\r\n#define CAN_F12R1_FB5_Pos      (5U)                                            \r\n#define CAN_F12R1_FB5_Msk      (0x1U << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */\r\n#define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */\r\n#define CAN_F12R1_FB6_Pos      (6U)                                            \r\n#define CAN_F12R1_FB6_Msk      (0x1U << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */\r\n#define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */\r\n#define CAN_F12R1_FB7_Pos      (7U)                                            \r\n#define CAN_F12R1_FB7_Msk      (0x1U << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */\r\n#define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */\r\n#define CAN_F12R1_FB8_Pos      (8U)                                            \r\n#define CAN_F12R1_FB8_Msk      (0x1U << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */\r\n#define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */\r\n#define CAN_F12R1_FB9_Pos      (9U)                                            \r\n#define CAN_F12R1_FB9_Msk      (0x1U << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */\r\n#define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */\r\n#define CAN_F12R1_FB10_Pos     (10U)                                           \r\n#define CAN_F12R1_FB10_Msk     (0x1U << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */\r\n#define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */\r\n#define CAN_F12R1_FB11_Pos     (11U)                                           \r\n#define CAN_F12R1_FB11_Msk     (0x1U << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */\r\n#define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */\r\n#define CAN_F12R1_FB12_Pos     (12U)                                           \r\n#define CAN_F12R1_FB12_Msk     (0x1U << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */\r\n#define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */\r\n#define CAN_F12R1_FB13_Pos     (13U)                                           \r\n#define CAN_F12R1_FB13_Msk     (0x1U << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */\r\n#define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */\r\n#define CAN_F12R1_FB14_Pos     (14U)                                           \r\n#define CAN_F12R1_FB14_Msk     (0x1U << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */\r\n#define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */\r\n#define CAN_F12R1_FB15_Pos     (15U)                                           \r\n#define CAN_F12R1_FB15_Msk     (0x1U << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */\r\n#define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */\r\n#define CAN_F12R1_FB16_Pos     (16U)                                           \r\n#define CAN_F12R1_FB16_Msk     (0x1U << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */\r\n#define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */\r\n#define CAN_F12R1_FB17_Pos     (17U)                                           \r\n#define CAN_F12R1_FB17_Msk     (0x1U << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */\r\n#define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */\r\n#define CAN_F12R1_FB18_Pos     (18U)                                           \r\n#define CAN_F12R1_FB18_Msk     (0x1U << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */\r\n#define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */\r\n#define CAN_F12R1_FB19_Pos     (19U)                                           \r\n#define CAN_F12R1_FB19_Msk     (0x1U << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */\r\n#define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */\r\n#define CAN_F12R1_FB20_Pos     (20U)                                           \r\n#define CAN_F12R1_FB20_Msk     (0x1U << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */\r\n#define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */\r\n#define CAN_F12R1_FB21_Pos     (21U)                                           \r\n#define CAN_F12R1_FB21_Msk     (0x1U << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */\r\n#define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */\r\n#define CAN_F12R1_FB22_Pos     (22U)                                           \r\n#define CAN_F12R1_FB22_Msk     (0x1U << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */\r\n#define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */\r\n#define CAN_F12R1_FB23_Pos     (23U)                                           \r\n#define CAN_F12R1_FB23_Msk     (0x1U << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */\r\n#define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */\r\n#define CAN_F12R1_FB24_Pos     (24U)                                           \r\n#define CAN_F12R1_FB24_Msk     (0x1U << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */\r\n#define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */\r\n#define CAN_F12R1_FB25_Pos     (25U)                                           \r\n#define CAN_F12R1_FB25_Msk     (0x1U << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */\r\n#define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */\r\n#define CAN_F12R1_FB26_Pos     (26U)                                           \r\n#define CAN_F12R1_FB26_Msk     (0x1U << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */\r\n#define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */\r\n#define CAN_F12R1_FB27_Pos     (27U)                                           \r\n#define CAN_F12R1_FB27_Msk     (0x1U << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */\r\n#define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */\r\n#define CAN_F12R1_FB28_Pos     (28U)                                           \r\n#define CAN_F12R1_FB28_Msk     (0x1U << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */\r\n#define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */\r\n#define CAN_F12R1_FB29_Pos     (29U)                                           \r\n#define CAN_F12R1_FB29_Msk     (0x1U << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */\r\n#define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */\r\n#define CAN_F12R1_FB30_Pos     (30U)                                           \r\n#define CAN_F12R1_FB30_Msk     (0x1U << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */\r\n#define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */\r\n#define CAN_F12R1_FB31_Pos     (31U)                                           \r\n#define CAN_F12R1_FB31_Msk     (0x1U << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */\r\n#define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F13R1 register  ******************/\r\n#define CAN_F13R1_FB0_Pos      (0U)                                            \r\n#define CAN_F13R1_FB0_Msk      (0x1U << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */\r\n#define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */\r\n#define CAN_F13R1_FB1_Pos      (1U)                                            \r\n#define CAN_F13R1_FB1_Msk      (0x1U << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */\r\n#define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */\r\n#define CAN_F13R1_FB2_Pos      (2U)                                            \r\n#define CAN_F13R1_FB2_Msk      (0x1U << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */\r\n#define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */\r\n#define CAN_F13R1_FB3_Pos      (3U)                                            \r\n#define CAN_F13R1_FB3_Msk      (0x1U << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */\r\n#define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */\r\n#define CAN_F13R1_FB4_Pos      (4U)                                            \r\n#define CAN_F13R1_FB4_Msk      (0x1U << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */\r\n#define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */\r\n#define CAN_F13R1_FB5_Pos      (5U)                                            \r\n#define CAN_F13R1_FB5_Msk      (0x1U << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */\r\n#define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */\r\n#define CAN_F13R1_FB6_Pos      (6U)                                            \r\n#define CAN_F13R1_FB6_Msk      (0x1U << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */\r\n#define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */\r\n#define CAN_F13R1_FB7_Pos      (7U)                                            \r\n#define CAN_F13R1_FB7_Msk      (0x1U << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */\r\n#define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */\r\n#define CAN_F13R1_FB8_Pos      (8U)                                            \r\n#define CAN_F13R1_FB8_Msk      (0x1U << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */\r\n#define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */\r\n#define CAN_F13R1_FB9_Pos      (9U)                                            \r\n#define CAN_F13R1_FB9_Msk      (0x1U << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */\r\n#define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */\r\n#define CAN_F13R1_FB10_Pos     (10U)                                           \r\n#define CAN_F13R1_FB10_Msk     (0x1U << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */\r\n#define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */\r\n#define CAN_F13R1_FB11_Pos     (11U)                                           \r\n#define CAN_F13R1_FB11_Msk     (0x1U << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */\r\n#define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */\r\n#define CAN_F13R1_FB12_Pos     (12U)                                           \r\n#define CAN_F13R1_FB12_Msk     (0x1U << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */\r\n#define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */\r\n#define CAN_F13R1_FB13_Pos     (13U)                                           \r\n#define CAN_F13R1_FB13_Msk     (0x1U << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */\r\n#define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */\r\n#define CAN_F13R1_FB14_Pos     (14U)                                           \r\n#define CAN_F13R1_FB14_Msk     (0x1U << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */\r\n#define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */\r\n#define CAN_F13R1_FB15_Pos     (15U)                                           \r\n#define CAN_F13R1_FB15_Msk     (0x1U << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */\r\n#define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */\r\n#define CAN_F13R1_FB16_Pos     (16U)                                           \r\n#define CAN_F13R1_FB16_Msk     (0x1U << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */\r\n#define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */\r\n#define CAN_F13R1_FB17_Pos     (17U)                                           \r\n#define CAN_F13R1_FB17_Msk     (0x1U << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */\r\n#define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */\r\n#define CAN_F13R1_FB18_Pos     (18U)                                           \r\n#define CAN_F13R1_FB18_Msk     (0x1U << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */\r\n#define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */\r\n#define CAN_F13R1_FB19_Pos     (19U)                                           \r\n#define CAN_F13R1_FB19_Msk     (0x1U << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */\r\n#define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */\r\n#define CAN_F13R1_FB20_Pos     (20U)                                           \r\n#define CAN_F13R1_FB20_Msk     (0x1U << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */\r\n#define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */\r\n#define CAN_F13R1_FB21_Pos     (21U)                                           \r\n#define CAN_F13R1_FB21_Msk     (0x1U << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */\r\n#define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */\r\n#define CAN_F13R1_FB22_Pos     (22U)                                           \r\n#define CAN_F13R1_FB22_Msk     (0x1U << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */\r\n#define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */\r\n#define CAN_F13R1_FB23_Pos     (23U)                                           \r\n#define CAN_F13R1_FB23_Msk     (0x1U << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */\r\n#define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */\r\n#define CAN_F13R1_FB24_Pos     (24U)                                           \r\n#define CAN_F13R1_FB24_Msk     (0x1U << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */\r\n#define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */\r\n#define CAN_F13R1_FB25_Pos     (25U)                                           \r\n#define CAN_F13R1_FB25_Msk     (0x1U << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */\r\n#define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */\r\n#define CAN_F13R1_FB26_Pos     (26U)                                           \r\n#define CAN_F13R1_FB26_Msk     (0x1U << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */\r\n#define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */\r\n#define CAN_F13R1_FB27_Pos     (27U)                                           \r\n#define CAN_F13R1_FB27_Msk     (0x1U << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */\r\n#define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */\r\n#define CAN_F13R1_FB28_Pos     (28U)                                           \r\n#define CAN_F13R1_FB28_Msk     (0x1U << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */\r\n#define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */\r\n#define CAN_F13R1_FB29_Pos     (29U)                                           \r\n#define CAN_F13R1_FB29_Msk     (0x1U << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */\r\n#define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */\r\n#define CAN_F13R1_FB30_Pos     (30U)                                           \r\n#define CAN_F13R1_FB30_Msk     (0x1U << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */\r\n#define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */\r\n#define CAN_F13R1_FB31_Pos     (31U)                                           \r\n#define CAN_F13R1_FB31_Msk     (0x1U << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */\r\n#define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F0R2 register  *******************/\r\n#define CAN_F0R2_FB0_Pos       (0U)                                            \r\n#define CAN_F0R2_FB0_Msk       (0x1U << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */\r\n#define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */\r\n#define CAN_F0R2_FB1_Pos       (1U)                                            \r\n#define CAN_F0R2_FB1_Msk       (0x1U << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */\r\n#define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */\r\n#define CAN_F0R2_FB2_Pos       (2U)                                            \r\n#define CAN_F0R2_FB2_Msk       (0x1U << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */\r\n#define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */\r\n#define CAN_F0R2_FB3_Pos       (3U)                                            \r\n#define CAN_F0R2_FB3_Msk       (0x1U << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */\r\n#define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */\r\n#define CAN_F0R2_FB4_Pos       (4U)                                            \r\n#define CAN_F0R2_FB4_Msk       (0x1U << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */\r\n#define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */\r\n#define CAN_F0R2_FB5_Pos       (5U)                                            \r\n#define CAN_F0R2_FB5_Msk       (0x1U << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */\r\n#define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */\r\n#define CAN_F0R2_FB6_Pos       (6U)                                            \r\n#define CAN_F0R2_FB6_Msk       (0x1U << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */\r\n#define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */\r\n#define CAN_F0R2_FB7_Pos       (7U)                                            \r\n#define CAN_F0R2_FB7_Msk       (0x1U << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */\r\n#define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */\r\n#define CAN_F0R2_FB8_Pos       (8U)                                            \r\n#define CAN_F0R2_FB8_Msk       (0x1U << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */\r\n#define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */\r\n#define CAN_F0R2_FB9_Pos       (9U)                                            \r\n#define CAN_F0R2_FB9_Msk       (0x1U << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */\r\n#define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */\r\n#define CAN_F0R2_FB10_Pos      (10U)                                           \r\n#define CAN_F0R2_FB10_Msk      (0x1U << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */\r\n#define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */\r\n#define CAN_F0R2_FB11_Pos      (11U)                                           \r\n#define CAN_F0R2_FB11_Msk      (0x1U << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */\r\n#define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */\r\n#define CAN_F0R2_FB12_Pos      (12U)                                           \r\n#define CAN_F0R2_FB12_Msk      (0x1U << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */\r\n#define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */\r\n#define CAN_F0R2_FB13_Pos      (13U)                                           \r\n#define CAN_F0R2_FB13_Msk      (0x1U << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */\r\n#define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */\r\n#define CAN_F0R2_FB14_Pos      (14U)                                           \r\n#define CAN_F0R2_FB14_Msk      (0x1U << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */\r\n#define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */\r\n#define CAN_F0R2_FB15_Pos      (15U)                                           \r\n#define CAN_F0R2_FB15_Msk      (0x1U << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */\r\n#define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */\r\n#define CAN_F0R2_FB16_Pos      (16U)                                           \r\n#define CAN_F0R2_FB16_Msk      (0x1U << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */\r\n#define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */\r\n#define CAN_F0R2_FB17_Pos      (17U)                                           \r\n#define CAN_F0R2_FB17_Msk      (0x1U << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */\r\n#define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */\r\n#define CAN_F0R2_FB18_Pos      (18U)                                           \r\n#define CAN_F0R2_FB18_Msk      (0x1U << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */\r\n#define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */\r\n#define CAN_F0R2_FB19_Pos      (19U)                                           \r\n#define CAN_F0R2_FB19_Msk      (0x1U << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */\r\n#define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */\r\n#define CAN_F0R2_FB20_Pos      (20U)                                           \r\n#define CAN_F0R2_FB20_Msk      (0x1U << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */\r\n#define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */\r\n#define CAN_F0R2_FB21_Pos      (21U)                                           \r\n#define CAN_F0R2_FB21_Msk      (0x1U << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */\r\n#define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */\r\n#define CAN_F0R2_FB22_Pos      (22U)                                           \r\n#define CAN_F0R2_FB22_Msk      (0x1U << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */\r\n#define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */\r\n#define CAN_F0R2_FB23_Pos      (23U)                                           \r\n#define CAN_F0R2_FB23_Msk      (0x1U << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */\r\n#define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */\r\n#define CAN_F0R2_FB24_Pos      (24U)                                           \r\n#define CAN_F0R2_FB24_Msk      (0x1U << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */\r\n#define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */\r\n#define CAN_F0R2_FB25_Pos      (25U)                                           \r\n#define CAN_F0R2_FB25_Msk      (0x1U << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */\r\n#define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */\r\n#define CAN_F0R2_FB26_Pos      (26U)                                           \r\n#define CAN_F0R2_FB26_Msk      (0x1U << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */\r\n#define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */\r\n#define CAN_F0R2_FB27_Pos      (27U)                                           \r\n#define CAN_F0R2_FB27_Msk      (0x1U << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */\r\n#define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */\r\n#define CAN_F0R2_FB28_Pos      (28U)                                           \r\n#define CAN_F0R2_FB28_Msk      (0x1U << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */\r\n#define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */\r\n#define CAN_F0R2_FB29_Pos      (29U)                                           \r\n#define CAN_F0R2_FB29_Msk      (0x1U << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */\r\n#define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */\r\n#define CAN_F0R2_FB30_Pos      (30U)                                           \r\n#define CAN_F0R2_FB30_Msk      (0x1U << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */\r\n#define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */\r\n#define CAN_F0R2_FB31_Pos      (31U)                                           \r\n#define CAN_F0R2_FB31_Msk      (0x1U << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */\r\n#define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F1R2 register  *******************/\r\n#define CAN_F1R2_FB0_Pos       (0U)                                            \r\n#define CAN_F1R2_FB0_Msk       (0x1U << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */\r\n#define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */\r\n#define CAN_F1R2_FB1_Pos       (1U)                                            \r\n#define CAN_F1R2_FB1_Msk       (0x1U << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */\r\n#define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */\r\n#define CAN_F1R2_FB2_Pos       (2U)                                            \r\n#define CAN_F1R2_FB2_Msk       (0x1U << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */\r\n#define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */\r\n#define CAN_F1R2_FB3_Pos       (3U)                                            \r\n#define CAN_F1R2_FB3_Msk       (0x1U << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */\r\n#define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */\r\n#define CAN_F1R2_FB4_Pos       (4U)                                            \r\n#define CAN_F1R2_FB4_Msk       (0x1U << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */\r\n#define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */\r\n#define CAN_F1R2_FB5_Pos       (5U)                                            \r\n#define CAN_F1R2_FB5_Msk       (0x1U << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */\r\n#define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */\r\n#define CAN_F1R2_FB6_Pos       (6U)                                            \r\n#define CAN_F1R2_FB6_Msk       (0x1U << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */\r\n#define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */\r\n#define CAN_F1R2_FB7_Pos       (7U)                                            \r\n#define CAN_F1R2_FB7_Msk       (0x1U << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */\r\n#define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */\r\n#define CAN_F1R2_FB8_Pos       (8U)                                            \r\n#define CAN_F1R2_FB8_Msk       (0x1U << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */\r\n#define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */\r\n#define CAN_F1R2_FB9_Pos       (9U)                                            \r\n#define CAN_F1R2_FB9_Msk       (0x1U << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */\r\n#define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */\r\n#define CAN_F1R2_FB10_Pos      (10U)                                           \r\n#define CAN_F1R2_FB10_Msk      (0x1U << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */\r\n#define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */\r\n#define CAN_F1R2_FB11_Pos      (11U)                                           \r\n#define CAN_F1R2_FB11_Msk      (0x1U << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */\r\n#define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */\r\n#define CAN_F1R2_FB12_Pos      (12U)                                           \r\n#define CAN_F1R2_FB12_Msk      (0x1U << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */\r\n#define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */\r\n#define CAN_F1R2_FB13_Pos      (13U)                                           \r\n#define CAN_F1R2_FB13_Msk      (0x1U << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */\r\n#define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */\r\n#define CAN_F1R2_FB14_Pos      (14U)                                           \r\n#define CAN_F1R2_FB14_Msk      (0x1U << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */\r\n#define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */\r\n#define CAN_F1R2_FB15_Pos      (15U)                                           \r\n#define CAN_F1R2_FB15_Msk      (0x1U << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */\r\n#define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */\r\n#define CAN_F1R2_FB16_Pos      (16U)                                           \r\n#define CAN_F1R2_FB16_Msk      (0x1U << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */\r\n#define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */\r\n#define CAN_F1R2_FB17_Pos      (17U)                                           \r\n#define CAN_F1R2_FB17_Msk      (0x1U << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */\r\n#define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */\r\n#define CAN_F1R2_FB18_Pos      (18U)                                           \r\n#define CAN_F1R2_FB18_Msk      (0x1U << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */\r\n#define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */\r\n#define CAN_F1R2_FB19_Pos      (19U)                                           \r\n#define CAN_F1R2_FB19_Msk      (0x1U << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */\r\n#define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */\r\n#define CAN_F1R2_FB20_Pos      (20U)                                           \r\n#define CAN_F1R2_FB20_Msk      (0x1U << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */\r\n#define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */\r\n#define CAN_F1R2_FB21_Pos      (21U)                                           \r\n#define CAN_F1R2_FB21_Msk      (0x1U << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */\r\n#define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */\r\n#define CAN_F1R2_FB22_Pos      (22U)                                           \r\n#define CAN_F1R2_FB22_Msk      (0x1U << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */\r\n#define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */\r\n#define CAN_F1R2_FB23_Pos      (23U)                                           \r\n#define CAN_F1R2_FB23_Msk      (0x1U << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */\r\n#define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */\r\n#define CAN_F1R2_FB24_Pos      (24U)                                           \r\n#define CAN_F1R2_FB24_Msk      (0x1U << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */\r\n#define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */\r\n#define CAN_F1R2_FB25_Pos      (25U)                                           \r\n#define CAN_F1R2_FB25_Msk      (0x1U << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */\r\n#define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */\r\n#define CAN_F1R2_FB26_Pos      (26U)                                           \r\n#define CAN_F1R2_FB26_Msk      (0x1U << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */\r\n#define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */\r\n#define CAN_F1R2_FB27_Pos      (27U)                                           \r\n#define CAN_F1R2_FB27_Msk      (0x1U << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */\r\n#define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */\r\n#define CAN_F1R2_FB28_Pos      (28U)                                           \r\n#define CAN_F1R2_FB28_Msk      (0x1U << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */\r\n#define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */\r\n#define CAN_F1R2_FB29_Pos      (29U)                                           \r\n#define CAN_F1R2_FB29_Msk      (0x1U << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */\r\n#define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */\r\n#define CAN_F1R2_FB30_Pos      (30U)                                           \r\n#define CAN_F1R2_FB30_Msk      (0x1U << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */\r\n#define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */\r\n#define CAN_F1R2_FB31_Pos      (31U)                                           \r\n#define CAN_F1R2_FB31_Msk      (0x1U << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */\r\n#define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F2R2 register  *******************/\r\n#define CAN_F2R2_FB0_Pos       (0U)                                            \r\n#define CAN_F2R2_FB0_Msk       (0x1U << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */\r\n#define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */\r\n#define CAN_F2R2_FB1_Pos       (1U)                                            \r\n#define CAN_F2R2_FB1_Msk       (0x1U << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */\r\n#define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */\r\n#define CAN_F2R2_FB2_Pos       (2U)                                            \r\n#define CAN_F2R2_FB2_Msk       (0x1U << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */\r\n#define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */\r\n#define CAN_F2R2_FB3_Pos       (3U)                                            \r\n#define CAN_F2R2_FB3_Msk       (0x1U << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */\r\n#define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */\r\n#define CAN_F2R2_FB4_Pos       (4U)                                            \r\n#define CAN_F2R2_FB4_Msk       (0x1U << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */\r\n#define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */\r\n#define CAN_F2R2_FB5_Pos       (5U)                                            \r\n#define CAN_F2R2_FB5_Msk       (0x1U << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */\r\n#define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */\r\n#define CAN_F2R2_FB6_Pos       (6U)                                            \r\n#define CAN_F2R2_FB6_Msk       (0x1U << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */\r\n#define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */\r\n#define CAN_F2R2_FB7_Pos       (7U)                                            \r\n#define CAN_F2R2_FB7_Msk       (0x1U << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */\r\n#define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */\r\n#define CAN_F2R2_FB8_Pos       (8U)                                            \r\n#define CAN_F2R2_FB8_Msk       (0x1U << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */\r\n#define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */\r\n#define CAN_F2R2_FB9_Pos       (9U)                                            \r\n#define CAN_F2R2_FB9_Msk       (0x1U << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */\r\n#define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */\r\n#define CAN_F2R2_FB10_Pos      (10U)                                           \r\n#define CAN_F2R2_FB10_Msk      (0x1U << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */\r\n#define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */\r\n#define CAN_F2R2_FB11_Pos      (11U)                                           \r\n#define CAN_F2R2_FB11_Msk      (0x1U << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */\r\n#define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */\r\n#define CAN_F2R2_FB12_Pos      (12U)                                           \r\n#define CAN_F2R2_FB12_Msk      (0x1U << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */\r\n#define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */\r\n#define CAN_F2R2_FB13_Pos      (13U)                                           \r\n#define CAN_F2R2_FB13_Msk      (0x1U << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */\r\n#define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */\r\n#define CAN_F2R2_FB14_Pos      (14U)                                           \r\n#define CAN_F2R2_FB14_Msk      (0x1U << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */\r\n#define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */\r\n#define CAN_F2R2_FB15_Pos      (15U)                                           \r\n#define CAN_F2R2_FB15_Msk      (0x1U << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */\r\n#define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */\r\n#define CAN_F2R2_FB16_Pos      (16U)                                           \r\n#define CAN_F2R2_FB16_Msk      (0x1U << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */\r\n#define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */\r\n#define CAN_F2R2_FB17_Pos      (17U)                                           \r\n#define CAN_F2R2_FB17_Msk      (0x1U << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */\r\n#define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */\r\n#define CAN_F2R2_FB18_Pos      (18U)                                           \r\n#define CAN_F2R2_FB18_Msk      (0x1U << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */\r\n#define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */\r\n#define CAN_F2R2_FB19_Pos      (19U)                                           \r\n#define CAN_F2R2_FB19_Msk      (0x1U << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */\r\n#define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */\r\n#define CAN_F2R2_FB20_Pos      (20U)                                           \r\n#define CAN_F2R2_FB20_Msk      (0x1U << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */\r\n#define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */\r\n#define CAN_F2R2_FB21_Pos      (21U)                                           \r\n#define CAN_F2R2_FB21_Msk      (0x1U << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */\r\n#define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */\r\n#define CAN_F2R2_FB22_Pos      (22U)                                           \r\n#define CAN_F2R2_FB22_Msk      (0x1U << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */\r\n#define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */\r\n#define CAN_F2R2_FB23_Pos      (23U)                                           \r\n#define CAN_F2R2_FB23_Msk      (0x1U << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */\r\n#define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */\r\n#define CAN_F2R2_FB24_Pos      (24U)                                           \r\n#define CAN_F2R2_FB24_Msk      (0x1U << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */\r\n#define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */\r\n#define CAN_F2R2_FB25_Pos      (25U)                                           \r\n#define CAN_F2R2_FB25_Msk      (0x1U << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */\r\n#define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */\r\n#define CAN_F2R2_FB26_Pos      (26U)                                           \r\n#define CAN_F2R2_FB26_Msk      (0x1U << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */\r\n#define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */\r\n#define CAN_F2R2_FB27_Pos      (27U)                                           \r\n#define CAN_F2R2_FB27_Msk      (0x1U << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */\r\n#define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */\r\n#define CAN_F2R2_FB28_Pos      (28U)                                           \r\n#define CAN_F2R2_FB28_Msk      (0x1U << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */\r\n#define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */\r\n#define CAN_F2R2_FB29_Pos      (29U)                                           \r\n#define CAN_F2R2_FB29_Msk      (0x1U << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */\r\n#define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */\r\n#define CAN_F2R2_FB30_Pos      (30U)                                           \r\n#define CAN_F2R2_FB30_Msk      (0x1U << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */\r\n#define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */\r\n#define CAN_F2R2_FB31_Pos      (31U)                                           \r\n#define CAN_F2R2_FB31_Msk      (0x1U << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */\r\n#define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F3R2 register  *******************/\r\n#define CAN_F3R2_FB0_Pos       (0U)                                            \r\n#define CAN_F3R2_FB0_Msk       (0x1U << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */\r\n#define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */\r\n#define CAN_F3R2_FB1_Pos       (1U)                                            \r\n#define CAN_F3R2_FB1_Msk       (0x1U << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */\r\n#define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */\r\n#define CAN_F3R2_FB2_Pos       (2U)                                            \r\n#define CAN_F3R2_FB2_Msk       (0x1U << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */\r\n#define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */\r\n#define CAN_F3R2_FB3_Pos       (3U)                                            \r\n#define CAN_F3R2_FB3_Msk       (0x1U << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */\r\n#define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */\r\n#define CAN_F3R2_FB4_Pos       (4U)                                            \r\n#define CAN_F3R2_FB4_Msk       (0x1U << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */\r\n#define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */\r\n#define CAN_F3R2_FB5_Pos       (5U)                                            \r\n#define CAN_F3R2_FB5_Msk       (0x1U << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */\r\n#define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */\r\n#define CAN_F3R2_FB6_Pos       (6U)                                            \r\n#define CAN_F3R2_FB6_Msk       (0x1U << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */\r\n#define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */\r\n#define CAN_F3R2_FB7_Pos       (7U)                                            \r\n#define CAN_F3R2_FB7_Msk       (0x1U << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */\r\n#define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */\r\n#define CAN_F3R2_FB8_Pos       (8U)                                            \r\n#define CAN_F3R2_FB8_Msk       (0x1U << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */\r\n#define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */\r\n#define CAN_F3R2_FB9_Pos       (9U)                                            \r\n#define CAN_F3R2_FB9_Msk       (0x1U << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */\r\n#define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */\r\n#define CAN_F3R2_FB10_Pos      (10U)                                           \r\n#define CAN_F3R2_FB10_Msk      (0x1U << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */\r\n#define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */\r\n#define CAN_F3R2_FB11_Pos      (11U)                                           \r\n#define CAN_F3R2_FB11_Msk      (0x1U << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */\r\n#define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */\r\n#define CAN_F3R2_FB12_Pos      (12U)                                           \r\n#define CAN_F3R2_FB12_Msk      (0x1U << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */\r\n#define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */\r\n#define CAN_F3R2_FB13_Pos      (13U)                                           \r\n#define CAN_F3R2_FB13_Msk      (0x1U << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */\r\n#define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */\r\n#define CAN_F3R2_FB14_Pos      (14U)                                           \r\n#define CAN_F3R2_FB14_Msk      (0x1U << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */\r\n#define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */\r\n#define CAN_F3R2_FB15_Pos      (15U)                                           \r\n#define CAN_F3R2_FB15_Msk      (0x1U << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */\r\n#define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */\r\n#define CAN_F3R2_FB16_Pos      (16U)                                           \r\n#define CAN_F3R2_FB16_Msk      (0x1U << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */\r\n#define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */\r\n#define CAN_F3R2_FB17_Pos      (17U)                                           \r\n#define CAN_F3R2_FB17_Msk      (0x1U << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */\r\n#define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */\r\n#define CAN_F3R2_FB18_Pos      (18U)                                           \r\n#define CAN_F3R2_FB18_Msk      (0x1U << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */\r\n#define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */\r\n#define CAN_F3R2_FB19_Pos      (19U)                                           \r\n#define CAN_F3R2_FB19_Msk      (0x1U << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */\r\n#define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */\r\n#define CAN_F3R2_FB20_Pos      (20U)                                           \r\n#define CAN_F3R2_FB20_Msk      (0x1U << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */\r\n#define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */\r\n#define CAN_F3R2_FB21_Pos      (21U)                                           \r\n#define CAN_F3R2_FB21_Msk      (0x1U << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */\r\n#define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */\r\n#define CAN_F3R2_FB22_Pos      (22U)                                           \r\n#define CAN_F3R2_FB22_Msk      (0x1U << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */\r\n#define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */\r\n#define CAN_F3R2_FB23_Pos      (23U)                                           \r\n#define CAN_F3R2_FB23_Msk      (0x1U << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */\r\n#define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */\r\n#define CAN_F3R2_FB24_Pos      (24U)                                           \r\n#define CAN_F3R2_FB24_Msk      (0x1U << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */\r\n#define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */\r\n#define CAN_F3R2_FB25_Pos      (25U)                                           \r\n#define CAN_F3R2_FB25_Msk      (0x1U << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */\r\n#define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */\r\n#define CAN_F3R2_FB26_Pos      (26U)                                           \r\n#define CAN_F3R2_FB26_Msk      (0x1U << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */\r\n#define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */\r\n#define CAN_F3R2_FB27_Pos      (27U)                                           \r\n#define CAN_F3R2_FB27_Msk      (0x1U << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */\r\n#define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */\r\n#define CAN_F3R2_FB28_Pos      (28U)                                           \r\n#define CAN_F3R2_FB28_Msk      (0x1U << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */\r\n#define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */\r\n#define CAN_F3R2_FB29_Pos      (29U)                                           \r\n#define CAN_F3R2_FB29_Msk      (0x1U << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */\r\n#define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */\r\n#define CAN_F3R2_FB30_Pos      (30U)                                           \r\n#define CAN_F3R2_FB30_Msk      (0x1U << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */\r\n#define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */\r\n#define CAN_F3R2_FB31_Pos      (31U)                                           \r\n#define CAN_F3R2_FB31_Msk      (0x1U << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */\r\n#define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F4R2 register  *******************/\r\n#define CAN_F4R2_FB0_Pos       (0U)                                            \r\n#define CAN_F4R2_FB0_Msk       (0x1U << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */\r\n#define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */\r\n#define CAN_F4R2_FB1_Pos       (1U)                                            \r\n#define CAN_F4R2_FB1_Msk       (0x1U << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */\r\n#define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */\r\n#define CAN_F4R2_FB2_Pos       (2U)                                            \r\n#define CAN_F4R2_FB2_Msk       (0x1U << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */\r\n#define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */\r\n#define CAN_F4R2_FB3_Pos       (3U)                                            \r\n#define CAN_F4R2_FB3_Msk       (0x1U << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */\r\n#define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */\r\n#define CAN_F4R2_FB4_Pos       (4U)                                            \r\n#define CAN_F4R2_FB4_Msk       (0x1U << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */\r\n#define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */\r\n#define CAN_F4R2_FB5_Pos       (5U)                                            \r\n#define CAN_F4R2_FB5_Msk       (0x1U << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */\r\n#define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */\r\n#define CAN_F4R2_FB6_Pos       (6U)                                            \r\n#define CAN_F4R2_FB6_Msk       (0x1U << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */\r\n#define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */\r\n#define CAN_F4R2_FB7_Pos       (7U)                                            \r\n#define CAN_F4R2_FB7_Msk       (0x1U << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */\r\n#define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */\r\n#define CAN_F4R2_FB8_Pos       (8U)                                            \r\n#define CAN_F4R2_FB8_Msk       (0x1U << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */\r\n#define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */\r\n#define CAN_F4R2_FB9_Pos       (9U)                                            \r\n#define CAN_F4R2_FB9_Msk       (0x1U << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */\r\n#define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */\r\n#define CAN_F4R2_FB10_Pos      (10U)                                           \r\n#define CAN_F4R2_FB10_Msk      (0x1U << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */\r\n#define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */\r\n#define CAN_F4R2_FB11_Pos      (11U)                                           \r\n#define CAN_F4R2_FB11_Msk      (0x1U << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */\r\n#define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */\r\n#define CAN_F4R2_FB12_Pos      (12U)                                           \r\n#define CAN_F4R2_FB12_Msk      (0x1U << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */\r\n#define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */\r\n#define CAN_F4R2_FB13_Pos      (13U)                                           \r\n#define CAN_F4R2_FB13_Msk      (0x1U << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */\r\n#define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */\r\n#define CAN_F4R2_FB14_Pos      (14U)                                           \r\n#define CAN_F4R2_FB14_Msk      (0x1U << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */\r\n#define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */\r\n#define CAN_F4R2_FB15_Pos      (15U)                                           \r\n#define CAN_F4R2_FB15_Msk      (0x1U << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */\r\n#define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */\r\n#define CAN_F4R2_FB16_Pos      (16U)                                           \r\n#define CAN_F4R2_FB16_Msk      (0x1U << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */\r\n#define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */\r\n#define CAN_F4R2_FB17_Pos      (17U)                                           \r\n#define CAN_F4R2_FB17_Msk      (0x1U << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */\r\n#define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */\r\n#define CAN_F4R2_FB18_Pos      (18U)                                           \r\n#define CAN_F4R2_FB18_Msk      (0x1U << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */\r\n#define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */\r\n#define CAN_F4R2_FB19_Pos      (19U)                                           \r\n#define CAN_F4R2_FB19_Msk      (0x1U << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */\r\n#define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */\r\n#define CAN_F4R2_FB20_Pos      (20U)                                           \r\n#define CAN_F4R2_FB20_Msk      (0x1U << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */\r\n#define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */\r\n#define CAN_F4R2_FB21_Pos      (21U)                                           \r\n#define CAN_F4R2_FB21_Msk      (0x1U << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */\r\n#define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */\r\n#define CAN_F4R2_FB22_Pos      (22U)                                           \r\n#define CAN_F4R2_FB22_Msk      (0x1U << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */\r\n#define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */\r\n#define CAN_F4R2_FB23_Pos      (23U)                                           \r\n#define CAN_F4R2_FB23_Msk      (0x1U << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */\r\n#define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */\r\n#define CAN_F4R2_FB24_Pos      (24U)                                           \r\n#define CAN_F4R2_FB24_Msk      (0x1U << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */\r\n#define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */\r\n#define CAN_F4R2_FB25_Pos      (25U)                                           \r\n#define CAN_F4R2_FB25_Msk      (0x1U << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */\r\n#define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */\r\n#define CAN_F4R2_FB26_Pos      (26U)                                           \r\n#define CAN_F4R2_FB26_Msk      (0x1U << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */\r\n#define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */\r\n#define CAN_F4R2_FB27_Pos      (27U)                                           \r\n#define CAN_F4R2_FB27_Msk      (0x1U << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */\r\n#define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */\r\n#define CAN_F4R2_FB28_Pos      (28U)                                           \r\n#define CAN_F4R2_FB28_Msk      (0x1U << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */\r\n#define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */\r\n#define CAN_F4R2_FB29_Pos      (29U)                                           \r\n#define CAN_F4R2_FB29_Msk      (0x1U << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */\r\n#define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */\r\n#define CAN_F4R2_FB30_Pos      (30U)                                           \r\n#define CAN_F4R2_FB30_Msk      (0x1U << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */\r\n#define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */\r\n#define CAN_F4R2_FB31_Pos      (31U)                                           \r\n#define CAN_F4R2_FB31_Msk      (0x1U << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */\r\n#define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F5R2 register  *******************/\r\n#define CAN_F5R2_FB0_Pos       (0U)                                            \r\n#define CAN_F5R2_FB0_Msk       (0x1U << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */\r\n#define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */\r\n#define CAN_F5R2_FB1_Pos       (1U)                                            \r\n#define CAN_F5R2_FB1_Msk       (0x1U << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */\r\n#define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */\r\n#define CAN_F5R2_FB2_Pos       (2U)                                            \r\n#define CAN_F5R2_FB2_Msk       (0x1U << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */\r\n#define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */\r\n#define CAN_F5R2_FB3_Pos       (3U)                                            \r\n#define CAN_F5R2_FB3_Msk       (0x1U << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */\r\n#define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */\r\n#define CAN_F5R2_FB4_Pos       (4U)                                            \r\n#define CAN_F5R2_FB4_Msk       (0x1U << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */\r\n#define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */\r\n#define CAN_F5R2_FB5_Pos       (5U)                                            \r\n#define CAN_F5R2_FB5_Msk       (0x1U << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */\r\n#define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */\r\n#define CAN_F5R2_FB6_Pos       (6U)                                            \r\n#define CAN_F5R2_FB6_Msk       (0x1U << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */\r\n#define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */\r\n#define CAN_F5R2_FB7_Pos       (7U)                                            \r\n#define CAN_F5R2_FB7_Msk       (0x1U << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */\r\n#define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */\r\n#define CAN_F5R2_FB8_Pos       (8U)                                            \r\n#define CAN_F5R2_FB8_Msk       (0x1U << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */\r\n#define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */\r\n#define CAN_F5R2_FB9_Pos       (9U)                                            \r\n#define CAN_F5R2_FB9_Msk       (0x1U << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */\r\n#define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */\r\n#define CAN_F5R2_FB10_Pos      (10U)                                           \r\n#define CAN_F5R2_FB10_Msk      (0x1U << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */\r\n#define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */\r\n#define CAN_F5R2_FB11_Pos      (11U)                                           \r\n#define CAN_F5R2_FB11_Msk      (0x1U << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */\r\n#define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */\r\n#define CAN_F5R2_FB12_Pos      (12U)                                           \r\n#define CAN_F5R2_FB12_Msk      (0x1U << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */\r\n#define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */\r\n#define CAN_F5R2_FB13_Pos      (13U)                                           \r\n#define CAN_F5R2_FB13_Msk      (0x1U << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */\r\n#define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */\r\n#define CAN_F5R2_FB14_Pos      (14U)                                           \r\n#define CAN_F5R2_FB14_Msk      (0x1U << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */\r\n#define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */\r\n#define CAN_F5R2_FB15_Pos      (15U)                                           \r\n#define CAN_F5R2_FB15_Msk      (0x1U << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */\r\n#define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */\r\n#define CAN_F5R2_FB16_Pos      (16U)                                           \r\n#define CAN_F5R2_FB16_Msk      (0x1U << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */\r\n#define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */\r\n#define CAN_F5R2_FB17_Pos      (17U)                                           \r\n#define CAN_F5R2_FB17_Msk      (0x1U << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */\r\n#define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */\r\n#define CAN_F5R2_FB18_Pos      (18U)                                           \r\n#define CAN_F5R2_FB18_Msk      (0x1U << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */\r\n#define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */\r\n#define CAN_F5R2_FB19_Pos      (19U)                                           \r\n#define CAN_F5R2_FB19_Msk      (0x1U << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */\r\n#define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */\r\n#define CAN_F5R2_FB20_Pos      (20U)                                           \r\n#define CAN_F5R2_FB20_Msk      (0x1U << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */\r\n#define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */\r\n#define CAN_F5R2_FB21_Pos      (21U)                                           \r\n#define CAN_F5R2_FB21_Msk      (0x1U << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */\r\n#define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */\r\n#define CAN_F5R2_FB22_Pos      (22U)                                           \r\n#define CAN_F5R2_FB22_Msk      (0x1U << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */\r\n#define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */\r\n#define CAN_F5R2_FB23_Pos      (23U)                                           \r\n#define CAN_F5R2_FB23_Msk      (0x1U << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */\r\n#define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */\r\n#define CAN_F5R2_FB24_Pos      (24U)                                           \r\n#define CAN_F5R2_FB24_Msk      (0x1U << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */\r\n#define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */\r\n#define CAN_F5R2_FB25_Pos      (25U)                                           \r\n#define CAN_F5R2_FB25_Msk      (0x1U << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */\r\n#define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */\r\n#define CAN_F5R2_FB26_Pos      (26U)                                           \r\n#define CAN_F5R2_FB26_Msk      (0x1U << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */\r\n#define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */\r\n#define CAN_F5R2_FB27_Pos      (27U)                                           \r\n#define CAN_F5R2_FB27_Msk      (0x1U << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */\r\n#define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */\r\n#define CAN_F5R2_FB28_Pos      (28U)                                           \r\n#define CAN_F5R2_FB28_Msk      (0x1U << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */\r\n#define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */\r\n#define CAN_F5R2_FB29_Pos      (29U)                                           \r\n#define CAN_F5R2_FB29_Msk      (0x1U << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */\r\n#define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */\r\n#define CAN_F5R2_FB30_Pos      (30U)                                           \r\n#define CAN_F5R2_FB30_Msk      (0x1U << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */\r\n#define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */\r\n#define CAN_F5R2_FB31_Pos      (31U)                                           \r\n#define CAN_F5R2_FB31_Msk      (0x1U << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */\r\n#define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F6R2 register  *******************/\r\n#define CAN_F6R2_FB0_Pos       (0U)                                            \r\n#define CAN_F6R2_FB0_Msk       (0x1U << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */\r\n#define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */\r\n#define CAN_F6R2_FB1_Pos       (1U)                                            \r\n#define CAN_F6R2_FB1_Msk       (0x1U << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */\r\n#define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */\r\n#define CAN_F6R2_FB2_Pos       (2U)                                            \r\n#define CAN_F6R2_FB2_Msk       (0x1U << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */\r\n#define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */\r\n#define CAN_F6R2_FB3_Pos       (3U)                                            \r\n#define CAN_F6R2_FB3_Msk       (0x1U << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */\r\n#define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */\r\n#define CAN_F6R2_FB4_Pos       (4U)                                            \r\n#define CAN_F6R2_FB4_Msk       (0x1U << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */\r\n#define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */\r\n#define CAN_F6R2_FB5_Pos       (5U)                                            \r\n#define CAN_F6R2_FB5_Msk       (0x1U << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */\r\n#define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */\r\n#define CAN_F6R2_FB6_Pos       (6U)                                            \r\n#define CAN_F6R2_FB6_Msk       (0x1U << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */\r\n#define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */\r\n#define CAN_F6R2_FB7_Pos       (7U)                                            \r\n#define CAN_F6R2_FB7_Msk       (0x1U << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */\r\n#define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */\r\n#define CAN_F6R2_FB8_Pos       (8U)                                            \r\n#define CAN_F6R2_FB8_Msk       (0x1U << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */\r\n#define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */\r\n#define CAN_F6R2_FB9_Pos       (9U)                                            \r\n#define CAN_F6R2_FB9_Msk       (0x1U << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */\r\n#define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */\r\n#define CAN_F6R2_FB10_Pos      (10U)                                           \r\n#define CAN_F6R2_FB10_Msk      (0x1U << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */\r\n#define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */\r\n#define CAN_F6R2_FB11_Pos      (11U)                                           \r\n#define CAN_F6R2_FB11_Msk      (0x1U << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */\r\n#define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */\r\n#define CAN_F6R2_FB12_Pos      (12U)                                           \r\n#define CAN_F6R2_FB12_Msk      (0x1U << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */\r\n#define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */\r\n#define CAN_F6R2_FB13_Pos      (13U)                                           \r\n#define CAN_F6R2_FB13_Msk      (0x1U << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */\r\n#define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */\r\n#define CAN_F6R2_FB14_Pos      (14U)                                           \r\n#define CAN_F6R2_FB14_Msk      (0x1U << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */\r\n#define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */\r\n#define CAN_F6R2_FB15_Pos      (15U)                                           \r\n#define CAN_F6R2_FB15_Msk      (0x1U << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */\r\n#define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */\r\n#define CAN_F6R2_FB16_Pos      (16U)                                           \r\n#define CAN_F6R2_FB16_Msk      (0x1U << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */\r\n#define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */\r\n#define CAN_F6R2_FB17_Pos      (17U)                                           \r\n#define CAN_F6R2_FB17_Msk      (0x1U << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */\r\n#define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */\r\n#define CAN_F6R2_FB18_Pos      (18U)                                           \r\n#define CAN_F6R2_FB18_Msk      (0x1U << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */\r\n#define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */\r\n#define CAN_F6R2_FB19_Pos      (19U)                                           \r\n#define CAN_F6R2_FB19_Msk      (0x1U << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */\r\n#define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */\r\n#define CAN_F6R2_FB20_Pos      (20U)                                           \r\n#define CAN_F6R2_FB20_Msk      (0x1U << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */\r\n#define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */\r\n#define CAN_F6R2_FB21_Pos      (21U)                                           \r\n#define CAN_F6R2_FB21_Msk      (0x1U << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */\r\n#define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */\r\n#define CAN_F6R2_FB22_Pos      (22U)                                           \r\n#define CAN_F6R2_FB22_Msk      (0x1U << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */\r\n#define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */\r\n#define CAN_F6R2_FB23_Pos      (23U)                                           \r\n#define CAN_F6R2_FB23_Msk      (0x1U << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */\r\n#define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */\r\n#define CAN_F6R2_FB24_Pos      (24U)                                           \r\n#define CAN_F6R2_FB24_Msk      (0x1U << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */\r\n#define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */\r\n#define CAN_F6R2_FB25_Pos      (25U)                                           \r\n#define CAN_F6R2_FB25_Msk      (0x1U << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */\r\n#define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */\r\n#define CAN_F6R2_FB26_Pos      (26U)                                           \r\n#define CAN_F6R2_FB26_Msk      (0x1U << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */\r\n#define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */\r\n#define CAN_F6R2_FB27_Pos      (27U)                                           \r\n#define CAN_F6R2_FB27_Msk      (0x1U << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */\r\n#define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */\r\n#define CAN_F6R2_FB28_Pos      (28U)                                           \r\n#define CAN_F6R2_FB28_Msk      (0x1U << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */\r\n#define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */\r\n#define CAN_F6R2_FB29_Pos      (29U)                                           \r\n#define CAN_F6R2_FB29_Msk      (0x1U << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */\r\n#define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */\r\n#define CAN_F6R2_FB30_Pos      (30U)                                           \r\n#define CAN_F6R2_FB30_Msk      (0x1U << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */\r\n#define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */\r\n#define CAN_F6R2_FB31_Pos      (31U)                                           \r\n#define CAN_F6R2_FB31_Msk      (0x1U << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */\r\n#define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F7R2 register  *******************/\r\n#define CAN_F7R2_FB0_Pos       (0U)                                            \r\n#define CAN_F7R2_FB0_Msk       (0x1U << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */\r\n#define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */\r\n#define CAN_F7R2_FB1_Pos       (1U)                                            \r\n#define CAN_F7R2_FB1_Msk       (0x1U << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */\r\n#define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */\r\n#define CAN_F7R2_FB2_Pos       (2U)                                            \r\n#define CAN_F7R2_FB2_Msk       (0x1U << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */\r\n#define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */\r\n#define CAN_F7R2_FB3_Pos       (3U)                                            \r\n#define CAN_F7R2_FB3_Msk       (0x1U << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */\r\n#define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */\r\n#define CAN_F7R2_FB4_Pos       (4U)                                            \r\n#define CAN_F7R2_FB4_Msk       (0x1U << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */\r\n#define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */\r\n#define CAN_F7R2_FB5_Pos       (5U)                                            \r\n#define CAN_F7R2_FB5_Msk       (0x1U << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */\r\n#define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */\r\n#define CAN_F7R2_FB6_Pos       (6U)                                            \r\n#define CAN_F7R2_FB6_Msk       (0x1U << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */\r\n#define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */\r\n#define CAN_F7R2_FB7_Pos       (7U)                                            \r\n#define CAN_F7R2_FB7_Msk       (0x1U << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */\r\n#define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */\r\n#define CAN_F7R2_FB8_Pos       (8U)                                            \r\n#define CAN_F7R2_FB8_Msk       (0x1U << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */\r\n#define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */\r\n#define CAN_F7R2_FB9_Pos       (9U)                                            \r\n#define CAN_F7R2_FB9_Msk       (0x1U << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */\r\n#define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */\r\n#define CAN_F7R2_FB10_Pos      (10U)                                           \r\n#define CAN_F7R2_FB10_Msk      (0x1U << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */\r\n#define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */\r\n#define CAN_F7R2_FB11_Pos      (11U)                                           \r\n#define CAN_F7R2_FB11_Msk      (0x1U << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */\r\n#define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */\r\n#define CAN_F7R2_FB12_Pos      (12U)                                           \r\n#define CAN_F7R2_FB12_Msk      (0x1U << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */\r\n#define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */\r\n#define CAN_F7R2_FB13_Pos      (13U)                                           \r\n#define CAN_F7R2_FB13_Msk      (0x1U << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */\r\n#define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */\r\n#define CAN_F7R2_FB14_Pos      (14U)                                           \r\n#define CAN_F7R2_FB14_Msk      (0x1U << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */\r\n#define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */\r\n#define CAN_F7R2_FB15_Pos      (15U)                                           \r\n#define CAN_F7R2_FB15_Msk      (0x1U << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */\r\n#define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */\r\n#define CAN_F7R2_FB16_Pos      (16U)                                           \r\n#define CAN_F7R2_FB16_Msk      (0x1U << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */\r\n#define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */\r\n#define CAN_F7R2_FB17_Pos      (17U)                                           \r\n#define CAN_F7R2_FB17_Msk      (0x1U << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */\r\n#define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */\r\n#define CAN_F7R2_FB18_Pos      (18U)                                           \r\n#define CAN_F7R2_FB18_Msk      (0x1U << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */\r\n#define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */\r\n#define CAN_F7R2_FB19_Pos      (19U)                                           \r\n#define CAN_F7R2_FB19_Msk      (0x1U << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */\r\n#define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */\r\n#define CAN_F7R2_FB20_Pos      (20U)                                           \r\n#define CAN_F7R2_FB20_Msk      (0x1U << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */\r\n#define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */\r\n#define CAN_F7R2_FB21_Pos      (21U)                                           \r\n#define CAN_F7R2_FB21_Msk      (0x1U << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */\r\n#define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */\r\n#define CAN_F7R2_FB22_Pos      (22U)                                           \r\n#define CAN_F7R2_FB22_Msk      (0x1U << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */\r\n#define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */\r\n#define CAN_F7R2_FB23_Pos      (23U)                                           \r\n#define CAN_F7R2_FB23_Msk      (0x1U << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */\r\n#define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */\r\n#define CAN_F7R2_FB24_Pos      (24U)                                           \r\n#define CAN_F7R2_FB24_Msk      (0x1U << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */\r\n#define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */\r\n#define CAN_F7R2_FB25_Pos      (25U)                                           \r\n#define CAN_F7R2_FB25_Msk      (0x1U << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */\r\n#define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */\r\n#define CAN_F7R2_FB26_Pos      (26U)                                           \r\n#define CAN_F7R2_FB26_Msk      (0x1U << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */\r\n#define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */\r\n#define CAN_F7R2_FB27_Pos      (27U)                                           \r\n#define CAN_F7R2_FB27_Msk      (0x1U << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */\r\n#define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */\r\n#define CAN_F7R2_FB28_Pos      (28U)                                           \r\n#define CAN_F7R2_FB28_Msk      (0x1U << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */\r\n#define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */\r\n#define CAN_F7R2_FB29_Pos      (29U)                                           \r\n#define CAN_F7R2_FB29_Msk      (0x1U << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */\r\n#define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */\r\n#define CAN_F7R2_FB30_Pos      (30U)                                           \r\n#define CAN_F7R2_FB30_Msk      (0x1U << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */\r\n#define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */\r\n#define CAN_F7R2_FB31_Pos      (31U)                                           \r\n#define CAN_F7R2_FB31_Msk      (0x1U << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */\r\n#define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F8R2 register  *******************/\r\n#define CAN_F8R2_FB0_Pos       (0U)                                            \r\n#define CAN_F8R2_FB0_Msk       (0x1U << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */\r\n#define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */\r\n#define CAN_F8R2_FB1_Pos       (1U)                                            \r\n#define CAN_F8R2_FB1_Msk       (0x1U << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */\r\n#define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */\r\n#define CAN_F8R2_FB2_Pos       (2U)                                            \r\n#define CAN_F8R2_FB2_Msk       (0x1U << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */\r\n#define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */\r\n#define CAN_F8R2_FB3_Pos       (3U)                                            \r\n#define CAN_F8R2_FB3_Msk       (0x1U << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */\r\n#define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */\r\n#define CAN_F8R2_FB4_Pos       (4U)                                            \r\n#define CAN_F8R2_FB4_Msk       (0x1U << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */\r\n#define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */\r\n#define CAN_F8R2_FB5_Pos       (5U)                                            \r\n#define CAN_F8R2_FB5_Msk       (0x1U << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */\r\n#define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */\r\n#define CAN_F8R2_FB6_Pos       (6U)                                            \r\n#define CAN_F8R2_FB6_Msk       (0x1U << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */\r\n#define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */\r\n#define CAN_F8R2_FB7_Pos       (7U)                                            \r\n#define CAN_F8R2_FB7_Msk       (0x1U << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */\r\n#define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */\r\n#define CAN_F8R2_FB8_Pos       (8U)                                            \r\n#define CAN_F8R2_FB8_Msk       (0x1U << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */\r\n#define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */\r\n#define CAN_F8R2_FB9_Pos       (9U)                                            \r\n#define CAN_F8R2_FB9_Msk       (0x1U << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */\r\n#define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */\r\n#define CAN_F8R2_FB10_Pos      (10U)                                           \r\n#define CAN_F8R2_FB10_Msk      (0x1U << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */\r\n#define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */\r\n#define CAN_F8R2_FB11_Pos      (11U)                                           \r\n#define CAN_F8R2_FB11_Msk      (0x1U << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */\r\n#define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */\r\n#define CAN_F8R2_FB12_Pos      (12U)                                           \r\n#define CAN_F8R2_FB12_Msk      (0x1U << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */\r\n#define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */\r\n#define CAN_F8R2_FB13_Pos      (13U)                                           \r\n#define CAN_F8R2_FB13_Msk      (0x1U << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */\r\n#define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */\r\n#define CAN_F8R2_FB14_Pos      (14U)                                           \r\n#define CAN_F8R2_FB14_Msk      (0x1U << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */\r\n#define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */\r\n#define CAN_F8R2_FB15_Pos      (15U)                                           \r\n#define CAN_F8R2_FB15_Msk      (0x1U << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */\r\n#define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */\r\n#define CAN_F8R2_FB16_Pos      (16U)                                           \r\n#define CAN_F8R2_FB16_Msk      (0x1U << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */\r\n#define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */\r\n#define CAN_F8R2_FB17_Pos      (17U)                                           \r\n#define CAN_F8R2_FB17_Msk      (0x1U << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */\r\n#define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */\r\n#define CAN_F8R2_FB18_Pos      (18U)                                           \r\n#define CAN_F8R2_FB18_Msk      (0x1U << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */\r\n#define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */\r\n#define CAN_F8R2_FB19_Pos      (19U)                                           \r\n#define CAN_F8R2_FB19_Msk      (0x1U << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */\r\n#define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */\r\n#define CAN_F8R2_FB20_Pos      (20U)                                           \r\n#define CAN_F8R2_FB20_Msk      (0x1U << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */\r\n#define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */\r\n#define CAN_F8R2_FB21_Pos      (21U)                                           \r\n#define CAN_F8R2_FB21_Msk      (0x1U << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */\r\n#define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */\r\n#define CAN_F8R2_FB22_Pos      (22U)                                           \r\n#define CAN_F8R2_FB22_Msk      (0x1U << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */\r\n#define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */\r\n#define CAN_F8R2_FB23_Pos      (23U)                                           \r\n#define CAN_F8R2_FB23_Msk      (0x1U << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */\r\n#define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */\r\n#define CAN_F8R2_FB24_Pos      (24U)                                           \r\n#define CAN_F8R2_FB24_Msk      (0x1U << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */\r\n#define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */\r\n#define CAN_F8R2_FB25_Pos      (25U)                                           \r\n#define CAN_F8R2_FB25_Msk      (0x1U << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */\r\n#define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */\r\n#define CAN_F8R2_FB26_Pos      (26U)                                           \r\n#define CAN_F8R2_FB26_Msk      (0x1U << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */\r\n#define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */\r\n#define CAN_F8R2_FB27_Pos      (27U)                                           \r\n#define CAN_F8R2_FB27_Msk      (0x1U << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */\r\n#define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */\r\n#define CAN_F8R2_FB28_Pos      (28U)                                           \r\n#define CAN_F8R2_FB28_Msk      (0x1U << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */\r\n#define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */\r\n#define CAN_F8R2_FB29_Pos      (29U)                                           \r\n#define CAN_F8R2_FB29_Msk      (0x1U << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */\r\n#define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */\r\n#define CAN_F8R2_FB30_Pos      (30U)                                           \r\n#define CAN_F8R2_FB30_Msk      (0x1U << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */\r\n#define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */\r\n#define CAN_F8R2_FB31_Pos      (31U)                                           \r\n#define CAN_F8R2_FB31_Msk      (0x1U << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */\r\n#define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F9R2 register  *******************/\r\n#define CAN_F9R2_FB0_Pos       (0U)                                            \r\n#define CAN_F9R2_FB0_Msk       (0x1U << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */\r\n#define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */\r\n#define CAN_F9R2_FB1_Pos       (1U)                                            \r\n#define CAN_F9R2_FB1_Msk       (0x1U << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */\r\n#define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */\r\n#define CAN_F9R2_FB2_Pos       (2U)                                            \r\n#define CAN_F9R2_FB2_Msk       (0x1U << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */\r\n#define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */\r\n#define CAN_F9R2_FB3_Pos       (3U)                                            \r\n#define CAN_F9R2_FB3_Msk       (0x1U << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */\r\n#define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */\r\n#define CAN_F9R2_FB4_Pos       (4U)                                            \r\n#define CAN_F9R2_FB4_Msk       (0x1U << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */\r\n#define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */\r\n#define CAN_F9R2_FB5_Pos       (5U)                                            \r\n#define CAN_F9R2_FB5_Msk       (0x1U << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */\r\n#define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */\r\n#define CAN_F9R2_FB6_Pos       (6U)                                            \r\n#define CAN_F9R2_FB6_Msk       (0x1U << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */\r\n#define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */\r\n#define CAN_F9R2_FB7_Pos       (7U)                                            \r\n#define CAN_F9R2_FB7_Msk       (0x1U << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */\r\n#define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */\r\n#define CAN_F9R2_FB8_Pos       (8U)                                            \r\n#define CAN_F9R2_FB8_Msk       (0x1U << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */\r\n#define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */\r\n#define CAN_F9R2_FB9_Pos       (9U)                                            \r\n#define CAN_F9R2_FB9_Msk       (0x1U << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */\r\n#define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */\r\n#define CAN_F9R2_FB10_Pos      (10U)                                           \r\n#define CAN_F9R2_FB10_Msk      (0x1U << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */\r\n#define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */\r\n#define CAN_F9R2_FB11_Pos      (11U)                                           \r\n#define CAN_F9R2_FB11_Msk      (0x1U << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */\r\n#define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */\r\n#define CAN_F9R2_FB12_Pos      (12U)                                           \r\n#define CAN_F9R2_FB12_Msk      (0x1U << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */\r\n#define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */\r\n#define CAN_F9R2_FB13_Pos      (13U)                                           \r\n#define CAN_F9R2_FB13_Msk      (0x1U << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */\r\n#define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */\r\n#define CAN_F9R2_FB14_Pos      (14U)                                           \r\n#define CAN_F9R2_FB14_Msk      (0x1U << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */\r\n#define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */\r\n#define CAN_F9R2_FB15_Pos      (15U)                                           \r\n#define CAN_F9R2_FB15_Msk      (0x1U << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */\r\n#define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */\r\n#define CAN_F9R2_FB16_Pos      (16U)                                           \r\n#define CAN_F9R2_FB16_Msk      (0x1U << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */\r\n#define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */\r\n#define CAN_F9R2_FB17_Pos      (17U)                                           \r\n#define CAN_F9R2_FB17_Msk      (0x1U << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */\r\n#define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */\r\n#define CAN_F9R2_FB18_Pos      (18U)                                           \r\n#define CAN_F9R2_FB18_Msk      (0x1U << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */\r\n#define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */\r\n#define CAN_F9R2_FB19_Pos      (19U)                                           \r\n#define CAN_F9R2_FB19_Msk      (0x1U << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */\r\n#define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */\r\n#define CAN_F9R2_FB20_Pos      (20U)                                           \r\n#define CAN_F9R2_FB20_Msk      (0x1U << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */\r\n#define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */\r\n#define CAN_F9R2_FB21_Pos      (21U)                                           \r\n#define CAN_F9R2_FB21_Msk      (0x1U << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */\r\n#define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */\r\n#define CAN_F9R2_FB22_Pos      (22U)                                           \r\n#define CAN_F9R2_FB22_Msk      (0x1U << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */\r\n#define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */\r\n#define CAN_F9R2_FB23_Pos      (23U)                                           \r\n#define CAN_F9R2_FB23_Msk      (0x1U << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */\r\n#define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */\r\n#define CAN_F9R2_FB24_Pos      (24U)                                           \r\n#define CAN_F9R2_FB24_Msk      (0x1U << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */\r\n#define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */\r\n#define CAN_F9R2_FB25_Pos      (25U)                                           \r\n#define CAN_F9R2_FB25_Msk      (0x1U << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */\r\n#define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */\r\n#define CAN_F9R2_FB26_Pos      (26U)                                           \r\n#define CAN_F9R2_FB26_Msk      (0x1U << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */\r\n#define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */\r\n#define CAN_F9R2_FB27_Pos      (27U)                                           \r\n#define CAN_F9R2_FB27_Msk      (0x1U << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */\r\n#define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */\r\n#define CAN_F9R2_FB28_Pos      (28U)                                           \r\n#define CAN_F9R2_FB28_Msk      (0x1U << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */\r\n#define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */\r\n#define CAN_F9R2_FB29_Pos      (29U)                                           \r\n#define CAN_F9R2_FB29_Msk      (0x1U << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */\r\n#define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */\r\n#define CAN_F9R2_FB30_Pos      (30U)                                           \r\n#define CAN_F9R2_FB30_Msk      (0x1U << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */\r\n#define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */\r\n#define CAN_F9R2_FB31_Pos      (31U)                                           \r\n#define CAN_F9R2_FB31_Msk      (0x1U << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */\r\n#define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F10R2 register  ******************/\r\n#define CAN_F10R2_FB0_Pos      (0U)                                            \r\n#define CAN_F10R2_FB0_Msk      (0x1U << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */\r\n#define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */\r\n#define CAN_F10R2_FB1_Pos      (1U)                                            \r\n#define CAN_F10R2_FB1_Msk      (0x1U << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */\r\n#define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */\r\n#define CAN_F10R2_FB2_Pos      (2U)                                            \r\n#define CAN_F10R2_FB2_Msk      (0x1U << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */\r\n#define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */\r\n#define CAN_F10R2_FB3_Pos      (3U)                                            \r\n#define CAN_F10R2_FB3_Msk      (0x1U << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */\r\n#define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */\r\n#define CAN_F10R2_FB4_Pos      (4U)                                            \r\n#define CAN_F10R2_FB4_Msk      (0x1U << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */\r\n#define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */\r\n#define CAN_F10R2_FB5_Pos      (5U)                                            \r\n#define CAN_F10R2_FB5_Msk      (0x1U << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */\r\n#define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */\r\n#define CAN_F10R2_FB6_Pos      (6U)                                            \r\n#define CAN_F10R2_FB6_Msk      (0x1U << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */\r\n#define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */\r\n#define CAN_F10R2_FB7_Pos      (7U)                                            \r\n#define CAN_F10R2_FB7_Msk      (0x1U << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */\r\n#define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */\r\n#define CAN_F10R2_FB8_Pos      (8U)                                            \r\n#define CAN_F10R2_FB8_Msk      (0x1U << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */\r\n#define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */\r\n#define CAN_F10R2_FB9_Pos      (9U)                                            \r\n#define CAN_F10R2_FB9_Msk      (0x1U << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */\r\n#define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */\r\n#define CAN_F10R2_FB10_Pos     (10U)                                           \r\n#define CAN_F10R2_FB10_Msk     (0x1U << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */\r\n#define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */\r\n#define CAN_F10R2_FB11_Pos     (11U)                                           \r\n#define CAN_F10R2_FB11_Msk     (0x1U << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */\r\n#define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */\r\n#define CAN_F10R2_FB12_Pos     (12U)                                           \r\n#define CAN_F10R2_FB12_Msk     (0x1U << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */\r\n#define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */\r\n#define CAN_F10R2_FB13_Pos     (13U)                                           \r\n#define CAN_F10R2_FB13_Msk     (0x1U << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */\r\n#define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */\r\n#define CAN_F10R2_FB14_Pos     (14U)                                           \r\n#define CAN_F10R2_FB14_Msk     (0x1U << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */\r\n#define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */\r\n#define CAN_F10R2_FB15_Pos     (15U)                                           \r\n#define CAN_F10R2_FB15_Msk     (0x1U << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */\r\n#define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */\r\n#define CAN_F10R2_FB16_Pos     (16U)                                           \r\n#define CAN_F10R2_FB16_Msk     (0x1U << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */\r\n#define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */\r\n#define CAN_F10R2_FB17_Pos     (17U)                                           \r\n#define CAN_F10R2_FB17_Msk     (0x1U << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */\r\n#define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */\r\n#define CAN_F10R2_FB18_Pos     (18U)                                           \r\n#define CAN_F10R2_FB18_Msk     (0x1U << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */\r\n#define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */\r\n#define CAN_F10R2_FB19_Pos     (19U)                                           \r\n#define CAN_F10R2_FB19_Msk     (0x1U << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */\r\n#define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */\r\n#define CAN_F10R2_FB20_Pos     (20U)                                           \r\n#define CAN_F10R2_FB20_Msk     (0x1U << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */\r\n#define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */\r\n#define CAN_F10R2_FB21_Pos     (21U)                                           \r\n#define CAN_F10R2_FB21_Msk     (0x1U << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */\r\n#define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */\r\n#define CAN_F10R2_FB22_Pos     (22U)                                           \r\n#define CAN_F10R2_FB22_Msk     (0x1U << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */\r\n#define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */\r\n#define CAN_F10R2_FB23_Pos     (23U)                                           \r\n#define CAN_F10R2_FB23_Msk     (0x1U << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */\r\n#define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */\r\n#define CAN_F10R2_FB24_Pos     (24U)                                           \r\n#define CAN_F10R2_FB24_Msk     (0x1U << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */\r\n#define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */\r\n#define CAN_F10R2_FB25_Pos     (25U)                                           \r\n#define CAN_F10R2_FB25_Msk     (0x1U << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */\r\n#define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */\r\n#define CAN_F10R2_FB26_Pos     (26U)                                           \r\n#define CAN_F10R2_FB26_Msk     (0x1U << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */\r\n#define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */\r\n#define CAN_F10R2_FB27_Pos     (27U)                                           \r\n#define CAN_F10R2_FB27_Msk     (0x1U << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */\r\n#define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */\r\n#define CAN_F10R2_FB28_Pos     (28U)                                           \r\n#define CAN_F10R2_FB28_Msk     (0x1U << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */\r\n#define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */\r\n#define CAN_F10R2_FB29_Pos     (29U)                                           \r\n#define CAN_F10R2_FB29_Msk     (0x1U << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */\r\n#define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */\r\n#define CAN_F10R2_FB30_Pos     (30U)                                           \r\n#define CAN_F10R2_FB30_Msk     (0x1U << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */\r\n#define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */\r\n#define CAN_F10R2_FB31_Pos     (31U)                                           \r\n#define CAN_F10R2_FB31_Msk     (0x1U << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */\r\n#define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F11R2 register  ******************/\r\n#define CAN_F11R2_FB0_Pos      (0U)                                            \r\n#define CAN_F11R2_FB0_Msk      (0x1U << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */\r\n#define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */\r\n#define CAN_F11R2_FB1_Pos      (1U)                                            \r\n#define CAN_F11R2_FB1_Msk      (0x1U << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */\r\n#define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */\r\n#define CAN_F11R2_FB2_Pos      (2U)                                            \r\n#define CAN_F11R2_FB2_Msk      (0x1U << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */\r\n#define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */\r\n#define CAN_F11R2_FB3_Pos      (3U)                                            \r\n#define CAN_F11R2_FB3_Msk      (0x1U << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */\r\n#define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */\r\n#define CAN_F11R2_FB4_Pos      (4U)                                            \r\n#define CAN_F11R2_FB4_Msk      (0x1U << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */\r\n#define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */\r\n#define CAN_F11R2_FB5_Pos      (5U)                                            \r\n#define CAN_F11R2_FB5_Msk      (0x1U << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */\r\n#define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */\r\n#define CAN_F11R2_FB6_Pos      (6U)                                            \r\n#define CAN_F11R2_FB6_Msk      (0x1U << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */\r\n#define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */\r\n#define CAN_F11R2_FB7_Pos      (7U)                                            \r\n#define CAN_F11R2_FB7_Msk      (0x1U << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */\r\n#define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */\r\n#define CAN_F11R2_FB8_Pos      (8U)                                            \r\n#define CAN_F11R2_FB8_Msk      (0x1U << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */\r\n#define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */\r\n#define CAN_F11R2_FB9_Pos      (9U)                                            \r\n#define CAN_F11R2_FB9_Msk      (0x1U << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */\r\n#define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */\r\n#define CAN_F11R2_FB10_Pos     (10U)                                           \r\n#define CAN_F11R2_FB10_Msk     (0x1U << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */\r\n#define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */\r\n#define CAN_F11R2_FB11_Pos     (11U)                                           \r\n#define CAN_F11R2_FB11_Msk     (0x1U << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */\r\n#define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */\r\n#define CAN_F11R2_FB12_Pos     (12U)                                           \r\n#define CAN_F11R2_FB12_Msk     (0x1U << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */\r\n#define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */\r\n#define CAN_F11R2_FB13_Pos     (13U)                                           \r\n#define CAN_F11R2_FB13_Msk     (0x1U << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */\r\n#define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */\r\n#define CAN_F11R2_FB14_Pos     (14U)                                           \r\n#define CAN_F11R2_FB14_Msk     (0x1U << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */\r\n#define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */\r\n#define CAN_F11R2_FB15_Pos     (15U)                                           \r\n#define CAN_F11R2_FB15_Msk     (0x1U << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */\r\n#define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */\r\n#define CAN_F11R2_FB16_Pos     (16U)                                           \r\n#define CAN_F11R2_FB16_Msk     (0x1U << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */\r\n#define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */\r\n#define CAN_F11R2_FB17_Pos     (17U)                                           \r\n#define CAN_F11R2_FB17_Msk     (0x1U << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */\r\n#define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */\r\n#define CAN_F11R2_FB18_Pos     (18U)                                           \r\n#define CAN_F11R2_FB18_Msk     (0x1U << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */\r\n#define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */\r\n#define CAN_F11R2_FB19_Pos     (19U)                                           \r\n#define CAN_F11R2_FB19_Msk     (0x1U << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */\r\n#define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */\r\n#define CAN_F11R2_FB20_Pos     (20U)                                           \r\n#define CAN_F11R2_FB20_Msk     (0x1U << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */\r\n#define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */\r\n#define CAN_F11R2_FB21_Pos     (21U)                                           \r\n#define CAN_F11R2_FB21_Msk     (0x1U << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */\r\n#define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */\r\n#define CAN_F11R2_FB22_Pos     (22U)                                           \r\n#define CAN_F11R2_FB22_Msk     (0x1U << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */\r\n#define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */\r\n#define CAN_F11R2_FB23_Pos     (23U)                                           \r\n#define CAN_F11R2_FB23_Msk     (0x1U << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */\r\n#define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */\r\n#define CAN_F11R2_FB24_Pos     (24U)                                           \r\n#define CAN_F11R2_FB24_Msk     (0x1U << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */\r\n#define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */\r\n#define CAN_F11R2_FB25_Pos     (25U)                                           \r\n#define CAN_F11R2_FB25_Msk     (0x1U << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */\r\n#define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */\r\n#define CAN_F11R2_FB26_Pos     (26U)                                           \r\n#define CAN_F11R2_FB26_Msk     (0x1U << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */\r\n#define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */\r\n#define CAN_F11R2_FB27_Pos     (27U)                                           \r\n#define CAN_F11R2_FB27_Msk     (0x1U << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */\r\n#define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */\r\n#define CAN_F11R2_FB28_Pos     (28U)                                           \r\n#define CAN_F11R2_FB28_Msk     (0x1U << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */\r\n#define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */\r\n#define CAN_F11R2_FB29_Pos     (29U)                                           \r\n#define CAN_F11R2_FB29_Msk     (0x1U << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */\r\n#define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */\r\n#define CAN_F11R2_FB30_Pos     (30U)                                           \r\n#define CAN_F11R2_FB30_Msk     (0x1U << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */\r\n#define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */\r\n#define CAN_F11R2_FB31_Pos     (31U)                                           \r\n#define CAN_F11R2_FB31_Msk     (0x1U << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */\r\n#define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F12R2 register  ******************/\r\n#define CAN_F12R2_FB0_Pos      (0U)                                            \r\n#define CAN_F12R2_FB0_Msk      (0x1U << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */\r\n#define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */\r\n#define CAN_F12R2_FB1_Pos      (1U)                                            \r\n#define CAN_F12R2_FB1_Msk      (0x1U << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */\r\n#define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */\r\n#define CAN_F12R2_FB2_Pos      (2U)                                            \r\n#define CAN_F12R2_FB2_Msk      (0x1U << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */\r\n#define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */\r\n#define CAN_F12R2_FB3_Pos      (3U)                                            \r\n#define CAN_F12R2_FB3_Msk      (0x1U << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */\r\n#define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */\r\n#define CAN_F12R2_FB4_Pos      (4U)                                            \r\n#define CAN_F12R2_FB4_Msk      (0x1U << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */\r\n#define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */\r\n#define CAN_F12R2_FB5_Pos      (5U)                                            \r\n#define CAN_F12R2_FB5_Msk      (0x1U << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */\r\n#define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */\r\n#define CAN_F12R2_FB6_Pos      (6U)                                            \r\n#define CAN_F12R2_FB6_Msk      (0x1U << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */\r\n#define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */\r\n#define CAN_F12R2_FB7_Pos      (7U)                                            \r\n#define CAN_F12R2_FB7_Msk      (0x1U << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */\r\n#define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */\r\n#define CAN_F12R2_FB8_Pos      (8U)                                            \r\n#define CAN_F12R2_FB8_Msk      (0x1U << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */\r\n#define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */\r\n#define CAN_F12R2_FB9_Pos      (9U)                                            \r\n#define CAN_F12R2_FB9_Msk      (0x1U << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */\r\n#define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */\r\n#define CAN_F12R2_FB10_Pos     (10U)                                           \r\n#define CAN_F12R2_FB10_Msk     (0x1U << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */\r\n#define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */\r\n#define CAN_F12R2_FB11_Pos     (11U)                                           \r\n#define CAN_F12R2_FB11_Msk     (0x1U << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */\r\n#define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */\r\n#define CAN_F12R2_FB12_Pos     (12U)                                           \r\n#define CAN_F12R2_FB12_Msk     (0x1U << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */\r\n#define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */\r\n#define CAN_F12R2_FB13_Pos     (13U)                                           \r\n#define CAN_F12R2_FB13_Msk     (0x1U << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */\r\n#define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */\r\n#define CAN_F12R2_FB14_Pos     (14U)                                           \r\n#define CAN_F12R2_FB14_Msk     (0x1U << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */\r\n#define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */\r\n#define CAN_F12R2_FB15_Pos     (15U)                                           \r\n#define CAN_F12R2_FB15_Msk     (0x1U << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */\r\n#define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */\r\n#define CAN_F12R2_FB16_Pos     (16U)                                           \r\n#define CAN_F12R2_FB16_Msk     (0x1U << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */\r\n#define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */\r\n#define CAN_F12R2_FB17_Pos     (17U)                                           \r\n#define CAN_F12R2_FB17_Msk     (0x1U << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */\r\n#define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */\r\n#define CAN_F12R2_FB18_Pos     (18U)                                           \r\n#define CAN_F12R2_FB18_Msk     (0x1U << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */\r\n#define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */\r\n#define CAN_F12R2_FB19_Pos     (19U)                                           \r\n#define CAN_F12R2_FB19_Msk     (0x1U << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */\r\n#define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */\r\n#define CAN_F12R2_FB20_Pos     (20U)                                           \r\n#define CAN_F12R2_FB20_Msk     (0x1U << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */\r\n#define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */\r\n#define CAN_F12R2_FB21_Pos     (21U)                                           \r\n#define CAN_F12R2_FB21_Msk     (0x1U << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */\r\n#define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */\r\n#define CAN_F12R2_FB22_Pos     (22U)                                           \r\n#define CAN_F12R2_FB22_Msk     (0x1U << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */\r\n#define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */\r\n#define CAN_F12R2_FB23_Pos     (23U)                                           \r\n#define CAN_F12R2_FB23_Msk     (0x1U << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */\r\n#define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */\r\n#define CAN_F12R2_FB24_Pos     (24U)                                           \r\n#define CAN_F12R2_FB24_Msk     (0x1U << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */\r\n#define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */\r\n#define CAN_F12R2_FB25_Pos     (25U)                                           \r\n#define CAN_F12R2_FB25_Msk     (0x1U << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */\r\n#define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */\r\n#define CAN_F12R2_FB26_Pos     (26U)                                           \r\n#define CAN_F12R2_FB26_Msk     (0x1U << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */\r\n#define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */\r\n#define CAN_F12R2_FB27_Pos     (27U)                                           \r\n#define CAN_F12R2_FB27_Msk     (0x1U << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */\r\n#define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */\r\n#define CAN_F12R2_FB28_Pos     (28U)                                           \r\n#define CAN_F12R2_FB28_Msk     (0x1U << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */\r\n#define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */\r\n#define CAN_F12R2_FB29_Pos     (29U)                                           \r\n#define CAN_F12R2_FB29_Msk     (0x1U << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */\r\n#define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */\r\n#define CAN_F12R2_FB30_Pos     (30U)                                           \r\n#define CAN_F12R2_FB30_Msk     (0x1U << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */\r\n#define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */\r\n#define CAN_F12R2_FB31_Pos     (31U)                                           \r\n#define CAN_F12R2_FB31_Msk     (0x1U << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */\r\n#define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F13R2 register  ******************/\r\n#define CAN_F13R2_FB0_Pos      (0U)                                            \r\n#define CAN_F13R2_FB0_Msk      (0x1U << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */\r\n#define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */\r\n#define CAN_F13R2_FB1_Pos      (1U)                                            \r\n#define CAN_F13R2_FB1_Msk      (0x1U << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */\r\n#define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */\r\n#define CAN_F13R2_FB2_Pos      (2U)                                            \r\n#define CAN_F13R2_FB2_Msk      (0x1U << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */\r\n#define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */\r\n#define CAN_F13R2_FB3_Pos      (3U)                                            \r\n#define CAN_F13R2_FB3_Msk      (0x1U << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */\r\n#define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */\r\n#define CAN_F13R2_FB4_Pos      (4U)                                            \r\n#define CAN_F13R2_FB4_Msk      (0x1U << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */\r\n#define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */\r\n#define CAN_F13R2_FB5_Pos      (5U)                                            \r\n#define CAN_F13R2_FB5_Msk      (0x1U << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */\r\n#define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */\r\n#define CAN_F13R2_FB6_Pos      (6U)                                            \r\n#define CAN_F13R2_FB6_Msk      (0x1U << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */\r\n#define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */\r\n#define CAN_F13R2_FB7_Pos      (7U)                                            \r\n#define CAN_F13R2_FB7_Msk      (0x1U << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */\r\n#define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */\r\n#define CAN_F13R2_FB8_Pos      (8U)                                            \r\n#define CAN_F13R2_FB8_Msk      (0x1U << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */\r\n#define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */\r\n#define CAN_F13R2_FB9_Pos      (9U)                                            \r\n#define CAN_F13R2_FB9_Msk      (0x1U << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */\r\n#define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */\r\n#define CAN_F13R2_FB10_Pos     (10U)                                           \r\n#define CAN_F13R2_FB10_Msk     (0x1U << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */\r\n#define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */\r\n#define CAN_F13R2_FB11_Pos     (11U)                                           \r\n#define CAN_F13R2_FB11_Msk     (0x1U << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */\r\n#define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */\r\n#define CAN_F13R2_FB12_Pos     (12U)                                           \r\n#define CAN_F13R2_FB12_Msk     (0x1U << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */\r\n#define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */\r\n#define CAN_F13R2_FB13_Pos     (13U)                                           \r\n#define CAN_F13R2_FB13_Msk     (0x1U << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */\r\n#define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */\r\n#define CAN_F13R2_FB14_Pos     (14U)                                           \r\n#define CAN_F13R2_FB14_Msk     (0x1U << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */\r\n#define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */\r\n#define CAN_F13R2_FB15_Pos     (15U)                                           \r\n#define CAN_F13R2_FB15_Msk     (0x1U << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */\r\n#define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */\r\n#define CAN_F13R2_FB16_Pos     (16U)                                           \r\n#define CAN_F13R2_FB16_Msk     (0x1U << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */\r\n#define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */\r\n#define CAN_F13R2_FB17_Pos     (17U)                                           \r\n#define CAN_F13R2_FB17_Msk     (0x1U << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */\r\n#define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */\r\n#define CAN_F13R2_FB18_Pos     (18U)                                           \r\n#define CAN_F13R2_FB18_Msk     (0x1U << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */\r\n#define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */\r\n#define CAN_F13R2_FB19_Pos     (19U)                                           \r\n#define CAN_F13R2_FB19_Msk     (0x1U << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */\r\n#define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */\r\n#define CAN_F13R2_FB20_Pos     (20U)                                           \r\n#define CAN_F13R2_FB20_Msk     (0x1U << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */\r\n#define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */\r\n#define CAN_F13R2_FB21_Pos     (21U)                                           \r\n#define CAN_F13R2_FB21_Msk     (0x1U << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */\r\n#define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */\r\n#define CAN_F13R2_FB22_Pos     (22U)                                           \r\n#define CAN_F13R2_FB22_Msk     (0x1U << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */\r\n#define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */\r\n#define CAN_F13R2_FB23_Pos     (23U)                                           \r\n#define CAN_F13R2_FB23_Msk     (0x1U << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */\r\n#define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */\r\n#define CAN_F13R2_FB24_Pos     (24U)                                           \r\n#define CAN_F13R2_FB24_Msk     (0x1U << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */\r\n#define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */\r\n#define CAN_F13R2_FB25_Pos     (25U)                                           \r\n#define CAN_F13R2_FB25_Msk     (0x1U << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */\r\n#define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */\r\n#define CAN_F13R2_FB26_Pos     (26U)                                           \r\n#define CAN_F13R2_FB26_Msk     (0x1U << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */\r\n#define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */\r\n#define CAN_F13R2_FB27_Pos     (27U)                                           \r\n#define CAN_F13R2_FB27_Msk     (0x1U << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */\r\n#define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */\r\n#define CAN_F13R2_FB28_Pos     (28U)                                           \r\n#define CAN_F13R2_FB28_Msk     (0x1U << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */\r\n#define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */\r\n#define CAN_F13R2_FB29_Pos     (29U)                                           \r\n#define CAN_F13R2_FB29_Msk     (0x1U << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */\r\n#define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */\r\n#define CAN_F13R2_FB30_Pos     (30U)                                           \r\n#define CAN_F13R2_FB30_Msk     (0x1U << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */\r\n#define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */\r\n#define CAN_F13R2_FB31_Pos     (31U)                                           \r\n#define CAN_F13R2_FB31_Msk     (0x1U << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */\r\n#define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                 HDMI-CEC (CEC)                             */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n\r\n/*******************  Bit definition for CEC_CR register  *********************/\r\n#define CEC_CR_CECEN_Pos         (0U)                                          \r\n#define CEC_CR_CECEN_Msk         (0x1U << CEC_CR_CECEN_Pos)                    /*!< 0x00000001 */\r\n#define CEC_CR_CECEN             CEC_CR_CECEN_Msk                              /*!< CEC Enable                         */\r\n#define CEC_CR_TXSOM_Pos         (1U)                                          \r\n#define CEC_CR_TXSOM_Msk         (0x1U << CEC_CR_TXSOM_Pos)                    /*!< 0x00000002 */\r\n#define CEC_CR_TXSOM             CEC_CR_TXSOM_Msk                              /*!< CEC Tx Start Of Message            */\r\n#define CEC_CR_TXEOM_Pos         (2U)                                          \r\n#define CEC_CR_TXEOM_Msk         (0x1U << CEC_CR_TXEOM_Pos)                    /*!< 0x00000004 */\r\n#define CEC_CR_TXEOM             CEC_CR_TXEOM_Msk                              /*!< CEC Tx End Of Message              */\r\n\r\n/*******************  Bit definition for CEC_CFGR register  *******************/\r\n#define CEC_CFGR_SFT_Pos         (0U)                                          \r\n#define CEC_CFGR_SFT_Msk         (0x7U << CEC_CFGR_SFT_Pos)                    /*!< 0x00000007 */\r\n#define CEC_CFGR_SFT             CEC_CFGR_SFT_Msk                              /*!< CEC Signal Free Time               */\r\n#define CEC_CFGR_RXTOL_Pos       (3U)                                          \r\n#define CEC_CFGR_RXTOL_Msk       (0x1U << CEC_CFGR_RXTOL_Pos)                  /*!< 0x00000008 */\r\n#define CEC_CFGR_RXTOL           CEC_CFGR_RXTOL_Msk                            /*!< CEC Tolerance                      */\r\n#define CEC_CFGR_BRESTP_Pos      (4U)                                          \r\n#define CEC_CFGR_BRESTP_Msk      (0x1U << CEC_CFGR_BRESTP_Pos)                 /*!< 0x00000010 */\r\n#define CEC_CFGR_BRESTP          CEC_CFGR_BRESTP_Msk                           /*!< CEC Rx Stop                        */\r\n#define CEC_CFGR_BREGEN_Pos      (5U)                                          \r\n#define CEC_CFGR_BREGEN_Msk      (0x1U << CEC_CFGR_BREGEN_Pos)                 /*!< 0x00000020 */\r\n#define CEC_CFGR_BREGEN          CEC_CFGR_BREGEN_Msk                           /*!< CEC Bit Rising Error generation    */\r\n#define CEC_CFGR_LBPEGEN_Pos     (6U)                                          \r\n#define CEC_CFGR_LBPEGEN_Msk     (0x1U << CEC_CFGR_LBPEGEN_Pos)                /*!< 0x00000040 */\r\n#define CEC_CFGR_LBPEGEN         CEC_CFGR_LBPEGEN_Msk                          /*!< CEC Long Period Error generation   */\r\n#define CEC_CFGR_BRDNOGEN_Pos    (7U)                                          \r\n#define CEC_CFGR_BRDNOGEN_Msk    (0x1U << CEC_CFGR_BRDNOGEN_Pos)               /*!< 0x00000080 */\r\n#define CEC_CFGR_BRDNOGEN        CEC_CFGR_BRDNOGEN_Msk                         /*!< CEC Broadcast no Error generation  */\r\n#define CEC_CFGR_SFTOPT_Pos      (8U)                                          \r\n#define CEC_CFGR_SFTOPT_Msk      (0x1U << CEC_CFGR_SFTOPT_Pos)                 /*!< 0x00000100 */\r\n#define CEC_CFGR_SFTOPT          CEC_CFGR_SFTOPT_Msk                           /*!< CEC Signal Free Time optional      */\r\n#define CEC_CFGR_OAR_Pos         (16U)                                         \r\n#define CEC_CFGR_OAR_Msk         (0x7FFFU << CEC_CFGR_OAR_Pos)                 /*!< 0x7FFF0000 */\r\n#define CEC_CFGR_OAR             CEC_CFGR_OAR_Msk                              /*!< CEC Own Address                    */\r\n#define CEC_CFGR_LSTN_Pos        (31U)                                         \r\n#define CEC_CFGR_LSTN_Msk        (0x1U << CEC_CFGR_LSTN_Pos)                   /*!< 0x80000000 */\r\n#define CEC_CFGR_LSTN            CEC_CFGR_LSTN_Msk                             /*!< CEC Listen mode                    */\r\n\r\n/*******************  Bit definition for CEC_TXDR register  *******************/\r\n#define CEC_TXDR_TXD_Pos         (0U)                                          \r\n#define CEC_TXDR_TXD_Msk         (0xFFU << CEC_TXDR_TXD_Pos)                   /*!< 0x000000FF */\r\n#define CEC_TXDR_TXD             CEC_TXDR_TXD_Msk                              /*!< CEC Tx Data                        */\r\n\r\n/*******************  Bit definition for CEC_RXDR register  *******************/\r\n#define CEC_TXDR_RXD_Pos         (0U)                                          \r\n#define CEC_TXDR_RXD_Msk         (0xFFU << CEC_TXDR_RXD_Pos)                   /*!< 0x000000FF */\r\n#define CEC_TXDR_RXD             CEC_TXDR_RXD_Msk                              /*!< CEC Rx Data                        */\r\n\r\n/*******************  Bit definition for CEC_ISR register  ********************/\r\n#define CEC_ISR_RXBR_Pos         (0U)                                          \r\n#define CEC_ISR_RXBR_Msk         (0x1U << CEC_ISR_RXBR_Pos)                    /*!< 0x00000001 */\r\n#define CEC_ISR_RXBR             CEC_ISR_RXBR_Msk                              /*!< CEC Rx-Byte Received                   */\r\n#define CEC_ISR_RXEND_Pos        (1U)                                          \r\n#define CEC_ISR_RXEND_Msk        (0x1U << CEC_ISR_RXEND_Pos)                   /*!< 0x00000002 */\r\n#define CEC_ISR_RXEND            CEC_ISR_RXEND_Msk                             /*!< CEC End Of Reception                   */\r\n#define CEC_ISR_RXOVR_Pos        (2U)                                          \r\n#define CEC_ISR_RXOVR_Msk        (0x1U << CEC_ISR_RXOVR_Pos)                   /*!< 0x00000004 */\r\n#define CEC_ISR_RXOVR            CEC_ISR_RXOVR_Msk                             /*!< CEC Rx-Overrun                         */\r\n#define CEC_ISR_BRE_Pos          (3U)                                          \r\n#define CEC_ISR_BRE_Msk          (0x1U << CEC_ISR_BRE_Pos)                     /*!< 0x00000008 */\r\n#define CEC_ISR_BRE              CEC_ISR_BRE_Msk                               /*!< CEC Rx Bit Rising Error                */\r\n#define CEC_ISR_SBPE_Pos         (4U)                                          \r\n#define CEC_ISR_SBPE_Msk         (0x1U << CEC_ISR_SBPE_Pos)                    /*!< 0x00000010 */\r\n#define CEC_ISR_SBPE             CEC_ISR_SBPE_Msk                              /*!< CEC Rx Short Bit period Error          */\r\n#define CEC_ISR_LBPE_Pos         (5U)                                          \r\n#define CEC_ISR_LBPE_Msk         (0x1U << CEC_ISR_LBPE_Pos)                    /*!< 0x00000020 */\r\n#define CEC_ISR_LBPE             CEC_ISR_LBPE_Msk                              /*!< CEC Rx Long Bit period Error           */\r\n#define CEC_ISR_RXACKE_Pos       (6U)                                          \r\n#define CEC_ISR_RXACKE_Msk       (0x1U << CEC_ISR_RXACKE_Pos)                  /*!< 0x00000040 */\r\n#define CEC_ISR_RXACKE           CEC_ISR_RXACKE_Msk                            /*!< CEC Rx Missing Acknowledge             */\r\n#define CEC_ISR_ARBLST_Pos       (7U)                                          \r\n#define CEC_ISR_ARBLST_Msk       (0x1U << CEC_ISR_ARBLST_Pos)                  /*!< 0x00000080 */\r\n#define CEC_ISR_ARBLST           CEC_ISR_ARBLST_Msk                            /*!< CEC Arbitration Lost                   */\r\n#define CEC_ISR_TXBR_Pos         (8U)                                          \r\n#define CEC_ISR_TXBR_Msk         (0x1U << CEC_ISR_TXBR_Pos)                    /*!< 0x00000100 */\r\n#define CEC_ISR_TXBR             CEC_ISR_TXBR_Msk                              /*!< CEC Tx Byte Request                    */\r\n#define CEC_ISR_TXEND_Pos        (9U)                                          \r\n#define CEC_ISR_TXEND_Msk        (0x1U << CEC_ISR_TXEND_Pos)                   /*!< 0x00000200 */\r\n#define CEC_ISR_TXEND            CEC_ISR_TXEND_Msk                             /*!< CEC End of Transmission                */\r\n#define CEC_ISR_TXUDR_Pos        (10U)                                         \r\n#define CEC_ISR_TXUDR_Msk        (0x1U << CEC_ISR_TXUDR_Pos)                   /*!< 0x00000400 */\r\n#define CEC_ISR_TXUDR            CEC_ISR_TXUDR_Msk                             /*!< CEC Tx-Buffer Underrun                 */\r\n#define CEC_ISR_TXERR_Pos        (11U)                                         \r\n#define CEC_ISR_TXERR_Msk        (0x1U << CEC_ISR_TXERR_Pos)                   /*!< 0x00000800 */\r\n#define CEC_ISR_TXERR            CEC_ISR_TXERR_Msk                             /*!< CEC Tx-Error                           */\r\n#define CEC_ISR_TXACKE_Pos       (12U)                                         \r\n#define CEC_ISR_TXACKE_Msk       (0x1U << CEC_ISR_TXACKE_Pos)                  /*!< 0x00001000 */\r\n#define CEC_ISR_TXACKE           CEC_ISR_TXACKE_Msk                            /*!< CEC Tx Missing Acknowledge             */\r\n\r\n/*******************  Bit definition for CEC_IER register  ********************/\r\n#define CEC_IER_RXBRIE_Pos       (0U)                                          \r\n#define CEC_IER_RXBRIE_Msk       (0x1U << CEC_IER_RXBRIE_Pos)                  /*!< 0x00000001 */\r\n#define CEC_IER_RXBRIE           CEC_IER_RXBRIE_Msk                            /*!< CEC Rx-Byte Received IT Enable         */\r\n#define CEC_IER_RXENDIE_Pos      (1U)                                          \r\n#define CEC_IER_RXENDIE_Msk      (0x1U << CEC_IER_RXENDIE_Pos)                 /*!< 0x00000002 */\r\n#define CEC_IER_RXENDIE          CEC_IER_RXENDIE_Msk                           /*!< CEC End Of Reception IT Enable         */\r\n#define CEC_IER_RXOVRIE_Pos      (2U)                                          \r\n#define CEC_IER_RXOVRIE_Msk      (0x1U << CEC_IER_RXOVRIE_Pos)                 /*!< 0x00000004 */\r\n#define CEC_IER_RXOVRIE          CEC_IER_RXOVRIE_Msk                           /*!< CEC Rx-Overrun IT Enable               */\r\n#define CEC_IER_BREIE_Pos        (3U)                                          \r\n#define CEC_IER_BREIE_Msk        (0x1U << CEC_IER_BREIE_Pos)                   /*!< 0x00000008 */\r\n#define CEC_IER_BREIE            CEC_IER_BREIE_Msk                             /*!< CEC Rx Bit Rising Error IT Enable      */\r\n#define CEC_IER_SBPEIE_Pos       (4U)                                          \r\n#define CEC_IER_SBPEIE_Msk       (0x1U << CEC_IER_SBPEIE_Pos)                  /*!< 0x00000010 */\r\n#define CEC_IER_SBPEIE           CEC_IER_SBPEIE_Msk                            /*!< CEC Rx Short Bit period Error IT Enable*/\r\n#define CEC_IER_LBPEIE_Pos       (5U)                                          \r\n#define CEC_IER_LBPEIE_Msk       (0x1U << CEC_IER_LBPEIE_Pos)                  /*!< 0x00000020 */\r\n#define CEC_IER_LBPEIE           CEC_IER_LBPEIE_Msk                            /*!< CEC Rx Long Bit period Error IT Enable */\r\n#define CEC_IER_RXACKEIE_Pos     (6U)                                          \r\n#define CEC_IER_RXACKEIE_Msk     (0x1U << CEC_IER_RXACKEIE_Pos)                /*!< 0x00000040 */\r\n#define CEC_IER_RXACKEIE         CEC_IER_RXACKEIE_Msk                          /*!< CEC Rx Missing Acknowledge IT Enable   */\r\n#define CEC_IER_ARBLSTIE_Pos     (7U)                                          \r\n#define CEC_IER_ARBLSTIE_Msk     (0x1U << CEC_IER_ARBLSTIE_Pos)                /*!< 0x00000080 */\r\n#define CEC_IER_ARBLSTIE         CEC_IER_ARBLSTIE_Msk                          /*!< CEC Arbitration Lost IT Enable         */\r\n#define CEC_IER_TXBRIE_Pos       (8U)                                          \r\n#define CEC_IER_TXBRIE_Msk       (0x1U << CEC_IER_TXBRIE_Pos)                  /*!< 0x00000100 */\r\n#define CEC_IER_TXBRIE           CEC_IER_TXBRIE_Msk                            /*!< CEC Tx Byte Request  IT Enable         */\r\n#define CEC_IER_TXENDIE_Pos      (9U)                                          \r\n#define CEC_IER_TXENDIE_Msk      (0x1U << CEC_IER_TXENDIE_Pos)                 /*!< 0x00000200 */\r\n#define CEC_IER_TXENDIE          CEC_IER_TXENDIE_Msk                           /*!< CEC End of Transmission IT Enable      */\r\n#define CEC_IER_TXUDRIE_Pos      (10U)                                         \r\n#define CEC_IER_TXUDRIE_Msk      (0x1U << CEC_IER_TXUDRIE_Pos)                 /*!< 0x00000400 */\r\n#define CEC_IER_TXUDRIE          CEC_IER_TXUDRIE_Msk                           /*!< CEC Tx-Buffer Underrun IT Enable       */\r\n#define CEC_IER_TXERRIE_Pos      (11U)                                         \r\n#define CEC_IER_TXERRIE_Msk      (0x1U << CEC_IER_TXERRIE_Pos)                 /*!< 0x00000800 */\r\n#define CEC_IER_TXERRIE          CEC_IER_TXERRIE_Msk                           /*!< CEC Tx-Error IT Enable                 */\r\n#define CEC_IER_TXACKEIE_Pos     (12U)                                         \r\n#define CEC_IER_TXACKEIE_Msk     (0x1U << CEC_IER_TXACKEIE_Pos)                /*!< 0x00001000 */\r\n#define CEC_IER_TXACKEIE         CEC_IER_TXACKEIE_Msk                          /*!< CEC Tx Missing Acknowledge IT Enable   */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                          CRC calculation unit                              */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************  Bit definition for CRC_DR register  *********************/\r\n#define CRC_DR_DR_Pos            (0U)                                          \r\n#define CRC_DR_DR_Msk            (0xFFFFFFFFU << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */\r\n#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */\r\n\r\n/*******************  Bit definition for CRC_IDR register  ********************/\r\n#define CRC_IDR_IDR_Pos          (0U)                                          \r\n#define CRC_IDR_IDR_Msk          (0xFFU << CRC_IDR_IDR_Pos)                    /*!< 0x000000FF */\r\n#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 8-bit data register bits */\r\n\r\n/********************  Bit definition for CRC_CR register  ********************/\r\n#define CRC_CR_RESET_Pos         (0U)                                          \r\n#define CRC_CR_RESET_Msk         (0x1U << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */\r\n#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */\r\n#define CRC_CR_POLYSIZE_Pos      (3U)                                          \r\n#define CRC_CR_POLYSIZE_Msk      (0x3U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */\r\n#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits               */\r\n#define CRC_CR_POLYSIZE_0        (0x1U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */\r\n#define CRC_CR_POLYSIZE_1        (0x2U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */\r\n#define CRC_CR_REV_IN_Pos        (5U)                                          \r\n#define CRC_CR_REV_IN_Msk        (0x3U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */\r\n#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits     */\r\n#define CRC_CR_REV_IN_0          (0x1U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */\r\n#define CRC_CR_REV_IN_1          (0x2U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */\r\n#define CRC_CR_REV_OUT_Pos       (7U)                                          \r\n#define CRC_CR_REV_OUT_Msk       (0x1U << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */\r\n#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits   */\r\n\r\n/*******************  Bit definition for CRC_INIT register  *******************/\r\n#define CRC_INIT_INIT_Pos        (0U)                                          \r\n#define CRC_INIT_INIT_Msk        (0xFFFFFFFFU << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */\r\n#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits         */\r\n\r\n/*******************  Bit definition for CRC_POL register  ********************/\r\n#define CRC_POL_POL_Pos          (0U)                                          \r\n#define CRC_POL_POL_Msk          (0xFFFFFFFFU << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */\r\n#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */\r\n\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                      Digital to Analog Converter                           */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bit definition for DAC_CR register  ********************/\r\n#define DAC_CR_EN1_Pos              (0U)                                       \r\n#define DAC_CR_EN1_Msk              (0x1U << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */\r\n#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable                         */\r\n#define DAC_CR_BOFF1_Pos            (1U)                                       \r\n#define DAC_CR_BOFF1_Msk            (0x1U << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */\r\n#define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!<DAC channel1 output buffer disable          */\r\n#define DAC_CR_TEN1_Pos             (2U)                                       \r\n#define DAC_CR_TEN1_Msk             (0x1U << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */\r\n#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable                 */\r\n#define DAC_CR_TSEL1_Pos            (3U)                                       \r\n#define DAC_CR_TSEL1_Msk            (0x7U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */\r\n#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\r\n#define DAC_CR_TSEL1_0              (0x1U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */\r\n#define DAC_CR_TSEL1_1              (0x2U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */\r\n#define DAC_CR_TSEL1_2              (0x4U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */\r\n#define DAC_CR_WAVE1_Pos            (6U)                                       \r\n#define DAC_CR_WAVE1_Msk            (0x3U << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */\r\n#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enablEU) */\r\n#define DAC_CR_WAVE1_0              (0x1U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */\r\n#define DAC_CR_WAVE1_1              (0x2U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */\r\n#define DAC_CR_MAMP1_Pos            (8U)                                       \r\n#define DAC_CR_MAMP1_Msk            (0xFU << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */\r\n#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\r\n#define DAC_CR_MAMP1_0              (0x1U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */\r\n#define DAC_CR_MAMP1_1              (0x2U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */\r\n#define DAC_CR_MAMP1_2              (0x4U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */\r\n#define DAC_CR_MAMP1_3              (0x8U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */\r\n#define DAC_CR_DMAEN1_Pos           (12U)                                      \r\n#define DAC_CR_DMAEN1_Msk           (0x1U << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */\r\n#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable                     */\r\n#define DAC_CR_DMAUDRIE1_Pos        (13U)                                      \r\n#define DAC_CR_DMAUDRIE1_Msk        (0x1U << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */\r\n#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel1 DMA underrun interrupt enable  */\r\n#define DAC_CR_EN2_Pos              (16U)                                      \r\n#define DAC_CR_EN2_Msk              (0x1U << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */\r\n#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable                         */\r\n#define DAC_CR_BOFF2_Pos            (17U)                                      \r\n#define DAC_CR_BOFF2_Msk            (0x1U << DAC_CR_BOFF2_Pos)                 /*!< 0x00020000 */\r\n#define DAC_CR_BOFF2                DAC_CR_BOFF2_Msk                           /*!<DAC channel2 output buffer disable          */\r\n#define DAC_CR_TEN2_Pos             (18U)                                      \r\n#define DAC_CR_TEN2_Msk             (0x1U << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */\r\n#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable                 */\r\n#define DAC_CR_TSEL2_Pos            (19U)                                      \r\n#define DAC_CR_TSEL2_Msk            (0x7U << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */\r\n#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */\r\n#define DAC_CR_TSEL2_0              (0x1U << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */\r\n#define DAC_CR_TSEL2_1              (0x2U << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */\r\n#define DAC_CR_TSEL2_2              (0x4U << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */\r\n#define DAC_CR_WAVE2_Pos            (22U)                                      \r\n#define DAC_CR_WAVE2_Msk            (0x3U << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */\r\n#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\r\n#define DAC_CR_WAVE2_0              (0x1U << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */\r\n#define DAC_CR_WAVE2_1              (0x2U << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */\r\n#define DAC_CR_MAMP2_Pos            (24U)                                      \r\n#define DAC_CR_MAMP2_Msk            (0xFU << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */\r\n#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\r\n#define DAC_CR_MAMP2_0              (0x1U << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */\r\n#define DAC_CR_MAMP2_1              (0x2U << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */\r\n#define DAC_CR_MAMP2_2              (0x4U << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */\r\n#define DAC_CR_MAMP2_3              (0x8U << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */\r\n#define DAC_CR_DMAEN2_Pos           (28U)                                      \r\n#define DAC_CR_DMAEN2_Msk           (0x1U << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */\r\n#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enable                    */\r\n#define DAC_CR_DMAUDRIE2_Pos        (29U)                                      \r\n#define DAC_CR_DMAUDRIE2_Msk        (0x1U << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */\r\n#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable */\r\n\r\n/*****************  Bit definition for DAC_SWTRIGR register  ******************/\r\n#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)                                       \r\n#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1U << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */\r\n#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */\r\n#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)                                       \r\n#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1U << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */\r\n#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */\r\n\r\n/*****************  Bit definition for DAC_DHR12R1 register  ******************/\r\n#define DAC_DHR12R1_DACC1DHR_Pos    (0U)                                       \r\n#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */\r\n#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */\r\n\r\n/*****************  Bit definition for DAC_DHR12L1 register  ******************/\r\n#define DAC_DHR12L1_DACC1DHR_Pos    (4U)                                       \r\n#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */\r\n#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */\r\n\r\n/******************  Bit definition for DAC_DHR8R1 register  ******************/\r\n#define DAC_DHR8R1_DACC1DHR_Pos     (0U)                                       \r\n#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFU << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */\r\n#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */\r\n\r\n/*****************  Bit definition for DAC_DHR12R2 register  ******************/\r\n#define DAC_DHR12R2_DACC2DHR_Pos    (0U)                                       \r\n#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */\r\n#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */\r\n\r\n/*****************  Bit definition for DAC_DHR12L2 register  ******************/\r\n#define DAC_DHR12L2_DACC2DHR_Pos    (4U)                                       \r\n#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */\r\n#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */\r\n\r\n/******************  Bit definition for DAC_DHR8R2 register  ******************/\r\n#define DAC_DHR8R2_DACC2DHR_Pos     (0U)                                       \r\n#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFU << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */\r\n#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */\r\n\r\n/*****************  Bit definition for DAC_DHR12RD register  ******************/\r\n#define DAC_DHR12RD_DACC1DHR_Pos    (0U)                                       \r\n#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */\r\n#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */\r\n#define DAC_DHR12RD_DACC2DHR_Pos    (16U)                                      \r\n#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */\r\n#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */\r\n\r\n/*****************  Bit definition for DAC_DHR12LD register  ******************/\r\n#define DAC_DHR12LD_DACC1DHR_Pos    (4U)                                       \r\n#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */\r\n#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */\r\n#define DAC_DHR12LD_DACC2DHR_Pos    (20U)                                      \r\n#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */\r\n#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */\r\n\r\n/******************  Bit definition for DAC_DHR8RD register  ******************/\r\n#define DAC_DHR8RD_DACC1DHR_Pos     (0U)                                       \r\n#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFU << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */\r\n#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */\r\n#define DAC_DHR8RD_DACC2DHR_Pos     (8U)                                       \r\n#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFU << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */\r\n#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */\r\n\r\n/*******************  Bit definition for DAC_DOR1 register  *******************/\r\n#define DAC_DOR1_DACC1DOR_Pos       (0U)                                       \r\n#define DAC_DOR1_DACC1DOR_Msk       (0xFFFU << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */\r\n#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */\r\n\r\n/*******************  Bit definition for DAC_DOR2 register  *******************/\r\n#define DAC_DOR2_DACC2DOR_Pos       (0U)                                       \r\n#define DAC_DOR2_DACC2DOR_Msk       (0xFFFU << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */\r\n#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */\r\n\r\n/********************  Bit definition for DAC_SR register  ********************/\r\n#define DAC_SR_DMAUDR1_Pos          (13U)                                      \r\n#define DAC_SR_DMAUDR1_Msk          (0x1U << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */\r\n#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */\r\n#define DAC_SR_DMAUDR2_Pos          (29U)                                      \r\n#define DAC_SR_DMAUDR2_Msk          (0x1U << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */\r\n#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */\r\n\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                 Debug MCU                                  */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                    DCMI                                    */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bits definition for DCMI_CR register  ******************/\r\n#define DCMI_CR_CAPTURE_Pos        (0U)                                        \r\n#define DCMI_CR_CAPTURE_Msk        (0x1U << DCMI_CR_CAPTURE_Pos)               /*!< 0x00000001 */\r\n#define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk                         \r\n#define DCMI_CR_CM_Pos             (1U)                                        \r\n#define DCMI_CR_CM_Msk             (0x1U << DCMI_CR_CM_Pos)                    /*!< 0x00000002 */\r\n#define DCMI_CR_CM                 DCMI_CR_CM_Msk                              \r\n#define DCMI_CR_CROP_Pos           (2U)                                        \r\n#define DCMI_CR_CROP_Msk           (0x1U << DCMI_CR_CROP_Pos)                  /*!< 0x00000004 */\r\n#define DCMI_CR_CROP               DCMI_CR_CROP_Msk                            \r\n#define DCMI_CR_JPEG_Pos           (3U)                                        \r\n#define DCMI_CR_JPEG_Msk           (0x1U << DCMI_CR_JPEG_Pos)                  /*!< 0x00000008 */\r\n#define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk                            \r\n#define DCMI_CR_ESS_Pos            (4U)                                        \r\n#define DCMI_CR_ESS_Msk            (0x1U << DCMI_CR_ESS_Pos)                   /*!< 0x00000010 */\r\n#define DCMI_CR_ESS                DCMI_CR_ESS_Msk                             \r\n#define DCMI_CR_PCKPOL_Pos         (5U)                                        \r\n#define DCMI_CR_PCKPOL_Msk         (0x1U << DCMI_CR_PCKPOL_Pos)                /*!< 0x00000020 */\r\n#define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk                          \r\n#define DCMI_CR_HSPOL_Pos          (6U)                                        \r\n#define DCMI_CR_HSPOL_Msk          (0x1U << DCMI_CR_HSPOL_Pos)                 /*!< 0x00000040 */\r\n#define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk                           \r\n#define DCMI_CR_VSPOL_Pos          (7U)                                        \r\n#define DCMI_CR_VSPOL_Msk          (0x1U << DCMI_CR_VSPOL_Pos)                 /*!< 0x00000080 */\r\n#define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk                           \r\n#define DCMI_CR_FCRC_0             0x00000100U                                 \r\n#define DCMI_CR_FCRC_1             0x00000200U                                 \r\n#define DCMI_CR_EDM_0              0x00000400U                                 \r\n#define DCMI_CR_EDM_1              0x00000800U                                 \r\n#define DCMI_CR_CRE_Pos            (12U)                                       \r\n#define DCMI_CR_CRE_Msk            (0x1U << DCMI_CR_CRE_Pos)                   /*!< 0x00001000 */\r\n#define DCMI_CR_CRE                DCMI_CR_CRE_Msk                             \r\n#define DCMI_CR_ENABLE_Pos         (14U)                                       \r\n#define DCMI_CR_ENABLE_Msk         (0x1U << DCMI_CR_ENABLE_Pos)                /*!< 0x00004000 */\r\n#define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk                          \r\n#define DCMI_CR_BSM_Pos            (16U)                                       \r\n#define DCMI_CR_BSM_Msk            (0x3U << DCMI_CR_BSM_Pos)                   /*!< 0x00030000 */\r\n#define DCMI_CR_BSM                DCMI_CR_BSM_Msk                             \r\n#define DCMI_CR_BSM_0              (0x1U << DCMI_CR_BSM_Pos)                   /*!< 0x00010000 */\r\n#define DCMI_CR_BSM_1              (0x2U << DCMI_CR_BSM_Pos)                   /*!< 0x00020000 */\r\n#define DCMI_CR_OEBS_Pos           (18U)                                       \r\n#define DCMI_CR_OEBS_Msk           (0x1U << DCMI_CR_OEBS_Pos)                  /*!< 0x00040000 */\r\n#define DCMI_CR_OEBS               DCMI_CR_OEBS_Msk                            \r\n#define DCMI_CR_LSM_Pos            (19U)                                       \r\n#define DCMI_CR_LSM_Msk            (0x1U << DCMI_CR_LSM_Pos)                   /*!< 0x00080000 */\r\n#define DCMI_CR_LSM                DCMI_CR_LSM_Msk                             \r\n#define DCMI_CR_OELS_Pos           (20U)                                       \r\n#define DCMI_CR_OELS_Msk           (0x1U << DCMI_CR_OELS_Pos)                  /*!< 0x00100000 */\r\n#define DCMI_CR_OELS               DCMI_CR_OELS_Msk                            \r\n\r\n/********************  Bits definition for DCMI_SR register  ******************/\r\n#define DCMI_SR_HSYNC_Pos          (0U)                                        \r\n#define DCMI_SR_HSYNC_Msk          (0x1U << DCMI_SR_HSYNC_Pos)                 /*!< 0x00000001 */\r\n#define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk                           \r\n#define DCMI_SR_VSYNC_Pos          (1U)                                        \r\n#define DCMI_SR_VSYNC_Msk          (0x1U << DCMI_SR_VSYNC_Pos)                 /*!< 0x00000002 */\r\n#define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk                           \r\n#define DCMI_SR_FNE_Pos            (2U)                                        \r\n#define DCMI_SR_FNE_Msk            (0x1U << DCMI_SR_FNE_Pos)                   /*!< 0x00000004 */\r\n#define DCMI_SR_FNE                DCMI_SR_FNE_Msk                             \r\n\r\n/********************  Bits definition for DCMI_RIS register   ****************/\r\n#define DCMI_RIS_FRAME_RIS_Pos     (0U)                                        \r\n#define DCMI_RIS_FRAME_RIS_Msk     (0x1U << DCMI_RIS_FRAME_RIS_Pos)            /*!< 0x00000001 */\r\n#define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk                      \r\n#define DCMI_RIS_OVR_RIS_Pos       (1U)                                        \r\n#define DCMI_RIS_OVR_RIS_Msk       (0x1U << DCMI_RIS_OVR_RIS_Pos)              /*!< 0x00000002 */\r\n#define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk                        \r\n#define DCMI_RIS_ERR_RIS_Pos       (2U)                                        \r\n#define DCMI_RIS_ERR_RIS_Msk       (0x1U << DCMI_RIS_ERR_RIS_Pos)              /*!< 0x00000004 */\r\n#define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk                        \r\n#define DCMI_RIS_VSYNC_RIS_Pos     (3U)                                        \r\n#define DCMI_RIS_VSYNC_RIS_Msk     (0x1U << DCMI_RIS_VSYNC_RIS_Pos)            /*!< 0x00000008 */\r\n#define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk                      \r\n#define DCMI_RIS_LINE_RIS_Pos      (4U)                                        \r\n#define DCMI_RIS_LINE_RIS_Msk      (0x1U << DCMI_RIS_LINE_RIS_Pos)             /*!< 0x00000010 */\r\n#define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk                       \r\n\r\n/* Legacy defines */\r\n#define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS\r\n#define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS\r\n#define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS\r\n#define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS\r\n#define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS\r\n\r\n/********************  Bits definition for DCMI_IER register  *****************/\r\n#define DCMI_IER_FRAME_IE_Pos      (0U)                                        \r\n#define DCMI_IER_FRAME_IE_Msk      (0x1U << DCMI_IER_FRAME_IE_Pos)             /*!< 0x00000001 */\r\n#define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk                       \r\n#define DCMI_IER_OVR_IE_Pos        (1U)                                        \r\n#define DCMI_IER_OVR_IE_Msk        (0x1U << DCMI_IER_OVR_IE_Pos)               /*!< 0x00000002 */\r\n#define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk                         \r\n#define DCMI_IER_ERR_IE_Pos        (2U)                                        \r\n#define DCMI_IER_ERR_IE_Msk        (0x1U << DCMI_IER_ERR_IE_Pos)               /*!< 0x00000004 */\r\n#define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk                         \r\n#define DCMI_IER_VSYNC_IE_Pos      (3U)                                        \r\n#define DCMI_IER_VSYNC_IE_Msk      (0x1U << DCMI_IER_VSYNC_IE_Pos)             /*!< 0x00000008 */\r\n#define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk                       \r\n#define DCMI_IER_LINE_IE_Pos       (4U)                                        \r\n#define DCMI_IER_LINE_IE_Msk       (0x1U << DCMI_IER_LINE_IE_Pos)              /*!< 0x00000010 */\r\n#define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk                        \r\n\r\n/* Legacy define */\r\n#define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE\r\n\r\n/********************  Bits definition for DCMI_MIS register  *****************/\r\n#define DCMI_MIS_FRAME_MIS_Pos     (0U)                                        \r\n#define DCMI_MIS_FRAME_MIS_Msk     (0x1U << DCMI_MIS_FRAME_MIS_Pos)            /*!< 0x00000001 */\r\n#define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk                      \r\n#define DCMI_MIS_OVR_MIS_Pos       (1U)                                        \r\n#define DCMI_MIS_OVR_MIS_Msk       (0x1U << DCMI_MIS_OVR_MIS_Pos)              /*!< 0x00000002 */\r\n#define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk                        \r\n#define DCMI_MIS_ERR_MIS_Pos       (2U)                                        \r\n#define DCMI_MIS_ERR_MIS_Msk       (0x1U << DCMI_MIS_ERR_MIS_Pos)              /*!< 0x00000004 */\r\n#define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk                        \r\n#define DCMI_MIS_VSYNC_MIS_Pos     (3U)                                        \r\n#define DCMI_MIS_VSYNC_MIS_Msk     (0x1U << DCMI_MIS_VSYNC_MIS_Pos)            /*!< 0x00000008 */\r\n#define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk                      \r\n#define DCMI_MIS_LINE_MIS_Pos      (4U)                                        \r\n#define DCMI_MIS_LINE_MIS_Msk      (0x1U << DCMI_MIS_LINE_MIS_Pos)             /*!< 0x00000010 */\r\n#define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk                       \r\n\r\n/* Legacy defines */\r\n#define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS\r\n#define DCMI_MISR_OVF_MIS                    DCMI_MIS_OVR_MIS\r\n#define DCMI_MISR_ERR_MIS                    DCMI_MIS_ERR_MIS\r\n#define DCMI_MISR_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS\r\n#define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS\r\n\r\n/********************  Bits definition for DCMI_ICR register  *****************/\r\n#define DCMI_ICR_FRAME_ISC_Pos     (0U)                                        \r\n#define DCMI_ICR_FRAME_ISC_Msk     (0x1U << DCMI_ICR_FRAME_ISC_Pos)            /*!< 0x00000001 */\r\n#define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk                      \r\n#define DCMI_ICR_OVR_ISC_Pos       (1U)                                        \r\n#define DCMI_ICR_OVR_ISC_Msk       (0x1U << DCMI_ICR_OVR_ISC_Pos)              /*!< 0x00000002 */\r\n#define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk                        \r\n#define DCMI_ICR_ERR_ISC_Pos       (2U)                                        \r\n#define DCMI_ICR_ERR_ISC_Msk       (0x1U << DCMI_ICR_ERR_ISC_Pos)              /*!< 0x00000004 */\r\n#define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk                        \r\n#define DCMI_ICR_VSYNC_ISC_Pos     (3U)                                        \r\n#define DCMI_ICR_VSYNC_ISC_Msk     (0x1U << DCMI_ICR_VSYNC_ISC_Pos)            /*!< 0x00000008 */\r\n#define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk                      \r\n#define DCMI_ICR_LINE_ISC_Pos      (4U)                                        \r\n#define DCMI_ICR_LINE_ISC_Msk      (0x1U << DCMI_ICR_LINE_ISC_Pos)             /*!< 0x00000010 */\r\n#define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk                       \r\n\r\n/* Legacy defines */\r\n#define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC\r\n\r\n/********************  Bits definition for DCMI_ESCR register  ******************/\r\n#define DCMI_ESCR_FSC_Pos          (0U)                                        \r\n#define DCMI_ESCR_FSC_Msk          (0xFFU << DCMI_ESCR_FSC_Pos)                /*!< 0x000000FF */\r\n#define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk                           \r\n#define DCMI_ESCR_LSC_Pos          (8U)                                        \r\n#define DCMI_ESCR_LSC_Msk          (0xFFU << DCMI_ESCR_LSC_Pos)                /*!< 0x0000FF00 */\r\n#define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk                           \r\n#define DCMI_ESCR_LEC_Pos          (16U)                                       \r\n#define DCMI_ESCR_LEC_Msk          (0xFFU << DCMI_ESCR_LEC_Pos)                /*!< 0x00FF0000 */\r\n#define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk                           \r\n#define DCMI_ESCR_FEC_Pos          (24U)                                       \r\n#define DCMI_ESCR_FEC_Msk          (0xFFU << DCMI_ESCR_FEC_Pos)                /*!< 0xFF000000 */\r\n#define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk                           \r\n\r\n/********************  Bits definition for DCMI_ESUR register  ******************/\r\n#define DCMI_ESUR_FSU_Pos          (0U)                                        \r\n#define DCMI_ESUR_FSU_Msk          (0xFFU << DCMI_ESUR_FSU_Pos)                /*!< 0x000000FF */\r\n#define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk                           \r\n#define DCMI_ESUR_LSU_Pos          (8U)                                        \r\n#define DCMI_ESUR_LSU_Msk          (0xFFU << DCMI_ESUR_LSU_Pos)                /*!< 0x0000FF00 */\r\n#define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk                           \r\n#define DCMI_ESUR_LEU_Pos          (16U)                                       \r\n#define DCMI_ESUR_LEU_Msk          (0xFFU << DCMI_ESUR_LEU_Pos)                /*!< 0x00FF0000 */\r\n#define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk                           \r\n#define DCMI_ESUR_FEU_Pos          (24U)                                       \r\n#define DCMI_ESUR_FEU_Msk          (0xFFU << DCMI_ESUR_FEU_Pos)                /*!< 0xFF000000 */\r\n#define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk                           \r\n\r\n/********************  Bits definition for DCMI_CWSTRT register  ******************/\r\n#define DCMI_CWSTRT_HOFFCNT_Pos    (0U)                                        \r\n#define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos)        /*!< 0x00003FFF */\r\n#define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk                     \r\n#define DCMI_CWSTRT_VST_Pos        (16U)                                       \r\n#define DCMI_CWSTRT_VST_Msk        (0x1FFFU << DCMI_CWSTRT_VST_Pos)            /*!< 0x1FFF0000 */\r\n#define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk                         \r\n\r\n/********************  Bits definition for DCMI_CWSIZE register  ******************/\r\n#define DCMI_CWSIZE_CAPCNT_Pos     (0U)                                        \r\n#define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos)         /*!< 0x00003FFF */\r\n#define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk                      \r\n#define DCMI_CWSIZE_VLINE_Pos      (16U)                                       \r\n#define DCMI_CWSIZE_VLINE_Msk      (0x3FFFU << DCMI_CWSIZE_VLINE_Pos)          /*!< 0x3FFF0000 */\r\n#define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk                       \r\n\r\n/********************  Bits definition for DCMI_DR register  ******************/\r\n#define DCMI_DR_BYTE0_Pos          (0U)                                        \r\n#define DCMI_DR_BYTE0_Msk          (0xFFU << DCMI_DR_BYTE0_Pos)                /*!< 0x000000FF */\r\n#define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk                           \r\n#define DCMI_DR_BYTE1_Pos          (8U)                                        \r\n#define DCMI_DR_BYTE1_Msk          (0xFFU << DCMI_DR_BYTE1_Pos)                /*!< 0x0000FF00 */\r\n#define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk                           \r\n#define DCMI_DR_BYTE2_Pos          (16U)                                       \r\n#define DCMI_DR_BYTE2_Msk          (0xFFU << DCMI_DR_BYTE2_Pos)                /*!< 0x00FF0000 */\r\n#define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk                           \r\n#define DCMI_DR_BYTE3_Pos          (24U)                                       \r\n#define DCMI_DR_BYTE3_Msk          (0xFFU << DCMI_DR_BYTE3_Pos)                /*!< 0xFF000000 */\r\n#define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk                           \r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                             DMA Controller                                 */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bits definition for DMA_SxCR register  *****************/\r\n#define DMA_SxCR_CHSEL_Pos       (25U)                                         \r\n#define DMA_SxCR_CHSEL_Msk       (0x7U << DMA_SxCR_CHSEL_Pos)                  /*!< 0x0E000000 */\r\n#define DMA_SxCR_CHSEL           DMA_SxCR_CHSEL_Msk                            \r\n#define DMA_SxCR_CHSEL_0         (0x1U << DMA_SxCR_CHSEL_Pos)                  /*!< 0x02000000 */\r\n#define DMA_SxCR_CHSEL_1         (0x2U << DMA_SxCR_CHSEL_Pos)                  /*!< 0x04000000 */\r\n#define DMA_SxCR_CHSEL_2         (0x4U << DMA_SxCR_CHSEL_Pos)                  /*!< 0x08000000 */\r\n#define DMA_SxCR_MBURST_Pos      (23U)                                         \r\n#define DMA_SxCR_MBURST_Msk      (0x3U << DMA_SxCR_MBURST_Pos)                 /*!< 0x01800000 */\r\n#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk                           \r\n#define DMA_SxCR_MBURST_0        (0x1U << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */\r\n#define DMA_SxCR_MBURST_1        (0x2U << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */\r\n#define DMA_SxCR_PBURST_Pos      (21U)                                         \r\n#define DMA_SxCR_PBURST_Msk      (0x3U << DMA_SxCR_PBURST_Pos)                 /*!< 0x00600000 */\r\n#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk                           \r\n#define DMA_SxCR_PBURST_0        (0x1U << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */\r\n#define DMA_SxCR_PBURST_1        (0x2U << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */\r\n#define DMA_SxCR_CT_Pos          (19U)                                         \r\n#define DMA_SxCR_CT_Msk          (0x1U << DMA_SxCR_CT_Pos)                     /*!< 0x00080000 */\r\n#define DMA_SxCR_CT              DMA_SxCR_CT_Msk                               \r\n#define DMA_SxCR_DBM_Pos         (18U)                                         \r\n#define DMA_SxCR_DBM_Msk         (0x1U << DMA_SxCR_DBM_Pos)                    /*!< 0x00040000 */\r\n#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk                              \r\n#define DMA_SxCR_PL_Pos          (16U)                                         \r\n#define DMA_SxCR_PL_Msk          (0x3U << DMA_SxCR_PL_Pos)                     /*!< 0x00030000 */\r\n#define DMA_SxCR_PL              DMA_SxCR_PL_Msk                               \r\n#define DMA_SxCR_PL_0            (0x1U << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */\r\n#define DMA_SxCR_PL_1            (0x2U << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */\r\n#define DMA_SxCR_PINCOS_Pos      (15U)                                         \r\n#define DMA_SxCR_PINCOS_Msk      (0x1U << DMA_SxCR_PINCOS_Pos)                 /*!< 0x00008000 */\r\n#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk                           \r\n#define DMA_SxCR_MSIZE_Pos       (13U)                                         \r\n#define DMA_SxCR_MSIZE_Msk       (0x3U << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00006000 */\r\n#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk                            \r\n#define DMA_SxCR_MSIZE_0         (0x1U << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */\r\n#define DMA_SxCR_MSIZE_1         (0x2U << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */\r\n#define DMA_SxCR_PSIZE_Pos       (11U)                                         \r\n#define DMA_SxCR_PSIZE_Msk       (0x3U << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001800 */\r\n#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk                            \r\n#define DMA_SxCR_PSIZE_0         (0x1U << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */\r\n#define DMA_SxCR_PSIZE_1         (0x2U << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */\r\n#define DMA_SxCR_MINC_Pos        (10U)                                         \r\n#define DMA_SxCR_MINC_Msk        (0x1U << DMA_SxCR_MINC_Pos)                   /*!< 0x00000400 */\r\n#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk                             \r\n#define DMA_SxCR_PINC_Pos        (9U)                                          \r\n#define DMA_SxCR_PINC_Msk        (0x1U << DMA_SxCR_PINC_Pos)                   /*!< 0x00000200 */\r\n#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk                             \r\n#define DMA_SxCR_CIRC_Pos        (8U)                                          \r\n#define DMA_SxCR_CIRC_Msk        (0x1U << DMA_SxCR_CIRC_Pos)                   /*!< 0x00000100 */\r\n#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk                             \r\n#define DMA_SxCR_DIR_Pos         (6U)                                          \r\n#define DMA_SxCR_DIR_Msk         (0x3U << DMA_SxCR_DIR_Pos)                    /*!< 0x000000C0 */\r\n#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk                              \r\n#define DMA_SxCR_DIR_0           (0x1U << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */\r\n#define DMA_SxCR_DIR_1           (0x2U << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */\r\n#define DMA_SxCR_PFCTRL_Pos      (5U)                                          \r\n#define DMA_SxCR_PFCTRL_Msk      (0x1U << DMA_SxCR_PFCTRL_Pos)                 /*!< 0x00000020 */\r\n#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk                           \r\n#define DMA_SxCR_TCIE_Pos        (4U)                                          \r\n#define DMA_SxCR_TCIE_Msk        (0x1U << DMA_SxCR_TCIE_Pos)                   /*!< 0x00000010 */\r\n#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk                             \r\n#define DMA_SxCR_HTIE_Pos        (3U)                                          \r\n#define DMA_SxCR_HTIE_Msk        (0x1U << DMA_SxCR_HTIE_Pos)                   /*!< 0x00000008 */\r\n#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk                             \r\n#define DMA_SxCR_TEIE_Pos        (2U)                                          \r\n#define DMA_SxCR_TEIE_Msk        (0x1U << DMA_SxCR_TEIE_Pos)                   /*!< 0x00000004 */\r\n#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk                             \r\n#define DMA_SxCR_DMEIE_Pos       (1U)                                          \r\n#define DMA_SxCR_DMEIE_Msk       (0x1U << DMA_SxCR_DMEIE_Pos)                  /*!< 0x00000002 */\r\n#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk                            \r\n#define DMA_SxCR_EN_Pos          (0U)                                          \r\n#define DMA_SxCR_EN_Msk          (0x1U << DMA_SxCR_EN_Pos)                     /*!< 0x00000001 */\r\n#define DMA_SxCR_EN              DMA_SxCR_EN_Msk                               \r\n\r\n/********************  Bits definition for DMA_SxCNDTR register  **************/\r\n#define DMA_SxNDT_Pos            (0U)                                          \r\n#define DMA_SxNDT_Msk            (0xFFFFU << DMA_SxNDT_Pos)                    /*!< 0x0000FFFF */\r\n#define DMA_SxNDT                DMA_SxNDT_Msk                                 \r\n#define DMA_SxNDT_0              (0x0001U << DMA_SxNDT_Pos)                    /*!< 0x00000001 */\r\n#define DMA_SxNDT_1              (0x0002U << DMA_SxNDT_Pos)                    /*!< 0x00000002 */\r\n#define DMA_SxNDT_2              (0x0004U << DMA_SxNDT_Pos)                    /*!< 0x00000004 */\r\n#define DMA_SxNDT_3              (0x0008U << DMA_SxNDT_Pos)                    /*!< 0x00000008 */\r\n#define DMA_SxNDT_4              (0x0010U << DMA_SxNDT_Pos)                    /*!< 0x00000010 */\r\n#define DMA_SxNDT_5              (0x0020U << DMA_SxNDT_Pos)                    /*!< 0x00000020 */\r\n#define DMA_SxNDT_6              (0x0040U << DMA_SxNDT_Pos)                    /*!< 0x00000040 */\r\n#define DMA_SxNDT_7              (0x0080U << DMA_SxNDT_Pos)                    /*!< 0x00000080 */\r\n#define DMA_SxNDT_8              (0x0100U << DMA_SxNDT_Pos)                    /*!< 0x00000100 */\r\n#define DMA_SxNDT_9              (0x0200U << DMA_SxNDT_Pos)                    /*!< 0x00000200 */\r\n#define DMA_SxNDT_10             (0x0400U << DMA_SxNDT_Pos)                    /*!< 0x00000400 */\r\n#define DMA_SxNDT_11             (0x0800U << DMA_SxNDT_Pos)                    /*!< 0x00000800 */\r\n#define DMA_SxNDT_12             (0x1000U << DMA_SxNDT_Pos)                    /*!< 0x00001000 */\r\n#define DMA_SxNDT_13             (0x2000U << DMA_SxNDT_Pos)                    /*!< 0x00002000 */\r\n#define DMA_SxNDT_14             (0x4000U << DMA_SxNDT_Pos)                    /*!< 0x00004000 */\r\n#define DMA_SxNDT_15             (0x8000U << DMA_SxNDT_Pos)                    /*!< 0x00008000 */\r\n\r\n/********************  Bits definition for DMA_SxFCR register  ****************/\r\n#define DMA_SxFCR_FEIE_Pos       (7U)                                          \r\n#define DMA_SxFCR_FEIE_Msk       (0x1U << DMA_SxFCR_FEIE_Pos)                  /*!< 0x00000080 */\r\n#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk                            \r\n#define DMA_SxFCR_FS_Pos         (3U)                                          \r\n#define DMA_SxFCR_FS_Msk         (0x7U << DMA_SxFCR_FS_Pos)                    /*!< 0x00000038 */\r\n#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk                              \r\n#define DMA_SxFCR_FS_0           (0x1U << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */\r\n#define DMA_SxFCR_FS_1           (0x2U << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */\r\n#define DMA_SxFCR_FS_2           (0x4U << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */\r\n#define DMA_SxFCR_DMDIS_Pos      (2U)                                          \r\n#define DMA_SxFCR_DMDIS_Msk      (0x1U << DMA_SxFCR_DMDIS_Pos)                 /*!< 0x00000004 */\r\n#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk                           \r\n#define DMA_SxFCR_FTH_Pos        (0U)                                          \r\n#define DMA_SxFCR_FTH_Msk        (0x3U << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000003 */\r\n#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk                             \r\n#define DMA_SxFCR_FTH_0          (0x1U << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */\r\n#define DMA_SxFCR_FTH_1          (0x2U << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */\r\n\r\n/********************  Bits definition for DMA_LISR register  *****************/\r\n#define DMA_LISR_TCIF3_Pos       (27U)                                         \r\n#define DMA_LISR_TCIF3_Msk       (0x1U << DMA_LISR_TCIF3_Pos)                  /*!< 0x08000000 */\r\n#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk                            \r\n#define DMA_LISR_HTIF3_Pos       (26U)                                         \r\n#define DMA_LISR_HTIF3_Msk       (0x1U << DMA_LISR_HTIF3_Pos)                  /*!< 0x04000000 */\r\n#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk                            \r\n#define DMA_LISR_TEIF3_Pos       (25U)                                         \r\n#define DMA_LISR_TEIF3_Msk       (0x1U << DMA_LISR_TEIF3_Pos)                  /*!< 0x02000000 */\r\n#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk                            \r\n#define DMA_LISR_DMEIF3_Pos      (24U)                                         \r\n#define DMA_LISR_DMEIF3_Msk      (0x1U << DMA_LISR_DMEIF3_Pos)                 /*!< 0x01000000 */\r\n#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk                           \r\n#define DMA_LISR_FEIF3_Pos       (22U)                                         \r\n#define DMA_LISR_FEIF3_Msk       (0x1U << DMA_LISR_FEIF3_Pos)                  /*!< 0x00400000 */\r\n#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk                            \r\n#define DMA_LISR_TCIF2_Pos       (21U)                                         \r\n#define DMA_LISR_TCIF2_Msk       (0x1U << DMA_LISR_TCIF2_Pos)                  /*!< 0x00200000 */\r\n#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk                            \r\n#define DMA_LISR_HTIF2_Pos       (20U)                                         \r\n#define DMA_LISR_HTIF2_Msk       (0x1U << DMA_LISR_HTIF2_Pos)                  /*!< 0x00100000 */\r\n#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk                            \r\n#define DMA_LISR_TEIF2_Pos       (19U)                                         \r\n#define DMA_LISR_TEIF2_Msk       (0x1U << DMA_LISR_TEIF2_Pos)                  /*!< 0x00080000 */\r\n#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk                            \r\n#define DMA_LISR_DMEIF2_Pos      (18U)                                         \r\n#define DMA_LISR_DMEIF2_Msk      (0x1U << DMA_LISR_DMEIF2_Pos)                 /*!< 0x00040000 */\r\n#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk                           \r\n#define DMA_LISR_FEIF2_Pos       (16U)                                         \r\n#define DMA_LISR_FEIF2_Msk       (0x1U << DMA_LISR_FEIF2_Pos)                  /*!< 0x00010000 */\r\n#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk                            \r\n#define DMA_LISR_TCIF1_Pos       (11U)                                         \r\n#define DMA_LISR_TCIF1_Msk       (0x1U << DMA_LISR_TCIF1_Pos)                  /*!< 0x00000800 */\r\n#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk                            \r\n#define DMA_LISR_HTIF1_Pos       (10U)                                         \r\n#define DMA_LISR_HTIF1_Msk       (0x1U << DMA_LISR_HTIF1_Pos)                  /*!< 0x00000400 */\r\n#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk                            \r\n#define DMA_LISR_TEIF1_Pos       (9U)                                          \r\n#define DMA_LISR_TEIF1_Msk       (0x1U << DMA_LISR_TEIF1_Pos)                  /*!< 0x00000200 */\r\n#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk                            \r\n#define DMA_LISR_DMEIF1_Pos      (8U)                                          \r\n#define DMA_LISR_DMEIF1_Msk      (0x1U << DMA_LISR_DMEIF1_Pos)                 /*!< 0x00000100 */\r\n#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk                           \r\n#define DMA_LISR_FEIF1_Pos       (6U)                                          \r\n#define DMA_LISR_FEIF1_Msk       (0x1U << DMA_LISR_FEIF1_Pos)                  /*!< 0x00000040 */\r\n#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk                            \r\n#define DMA_LISR_TCIF0_Pos       (5U)                                          \r\n#define DMA_LISR_TCIF0_Msk       (0x1U << DMA_LISR_TCIF0_Pos)                  /*!< 0x00000020 */\r\n#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk                            \r\n#define DMA_LISR_HTIF0_Pos       (4U)                                          \r\n#define DMA_LISR_HTIF0_Msk       (0x1U << DMA_LISR_HTIF0_Pos)                  /*!< 0x00000010 */\r\n#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk                            \r\n#define DMA_LISR_TEIF0_Pos       (3U)                                          \r\n#define DMA_LISR_TEIF0_Msk       (0x1U << DMA_LISR_TEIF0_Pos)                  /*!< 0x00000008 */\r\n#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk                            \r\n#define DMA_LISR_DMEIF0_Pos      (2U)                                          \r\n#define DMA_LISR_DMEIF0_Msk      (0x1U << DMA_LISR_DMEIF0_Pos)                 /*!< 0x00000004 */\r\n#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk                           \r\n#define DMA_LISR_FEIF0_Pos       (0U)                                          \r\n#define DMA_LISR_FEIF0_Msk       (0x1U << DMA_LISR_FEIF0_Pos)                  /*!< 0x00000001 */\r\n#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk                            \r\n\r\n/********************  Bits definition for DMA_HISR register  *****************/\r\n#define DMA_HISR_TCIF7_Pos       (27U)                                         \r\n#define DMA_HISR_TCIF7_Msk       (0x1U << DMA_HISR_TCIF7_Pos)                  /*!< 0x08000000 */\r\n#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk                            \r\n#define DMA_HISR_HTIF7_Pos       (26U)                                         \r\n#define DMA_HISR_HTIF7_Msk       (0x1U << DMA_HISR_HTIF7_Pos)                  /*!< 0x04000000 */\r\n#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk                            \r\n#define DMA_HISR_TEIF7_Pos       (25U)                                         \r\n#define DMA_HISR_TEIF7_Msk       (0x1U << DMA_HISR_TEIF7_Pos)                  /*!< 0x02000000 */\r\n#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk                            \r\n#define DMA_HISR_DMEIF7_Pos      (24U)                                         \r\n#define DMA_HISR_DMEIF7_Msk      (0x1U << DMA_HISR_DMEIF7_Pos)                 /*!< 0x01000000 */\r\n#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk                           \r\n#define DMA_HISR_FEIF7_Pos       (22U)                                         \r\n#define DMA_HISR_FEIF7_Msk       (0x1U << DMA_HISR_FEIF7_Pos)                  /*!< 0x00400000 */\r\n#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk                            \r\n#define DMA_HISR_TCIF6_Pos       (21U)                                         \r\n#define DMA_HISR_TCIF6_Msk       (0x1U << DMA_HISR_TCIF6_Pos)                  /*!< 0x00200000 */\r\n#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk                            \r\n#define DMA_HISR_HTIF6_Pos       (20U)                                         \r\n#define DMA_HISR_HTIF6_Msk       (0x1U << DMA_HISR_HTIF6_Pos)                  /*!< 0x00100000 */\r\n#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk                            \r\n#define DMA_HISR_TEIF6_Pos       (19U)                                         \r\n#define DMA_HISR_TEIF6_Msk       (0x1U << DMA_HISR_TEIF6_Pos)                  /*!< 0x00080000 */\r\n#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk                            \r\n#define DMA_HISR_DMEIF6_Pos      (18U)                                         \r\n#define DMA_HISR_DMEIF6_Msk      (0x1U << DMA_HISR_DMEIF6_Pos)                 /*!< 0x00040000 */\r\n#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk                           \r\n#define DMA_HISR_FEIF6_Pos       (16U)                                         \r\n#define DMA_HISR_FEIF6_Msk       (0x1U << DMA_HISR_FEIF6_Pos)                  /*!< 0x00010000 */\r\n#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk                            \r\n#define DMA_HISR_TCIF5_Pos       (11U)                                         \r\n#define DMA_HISR_TCIF5_Msk       (0x1U << DMA_HISR_TCIF5_Pos)                  /*!< 0x00000800 */\r\n#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk                            \r\n#define DMA_HISR_HTIF5_Pos       (10U)                                         \r\n#define DMA_HISR_HTIF5_Msk       (0x1U << DMA_HISR_HTIF5_Pos)                  /*!< 0x00000400 */\r\n#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk                            \r\n#define DMA_HISR_TEIF5_Pos       (9U)                                          \r\n#define DMA_HISR_TEIF5_Msk       (0x1U << DMA_HISR_TEIF5_Pos)                  /*!< 0x00000200 */\r\n#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk                            \r\n#define DMA_HISR_DMEIF5_Pos      (8U)                                          \r\n#define DMA_HISR_DMEIF5_Msk      (0x1U << DMA_HISR_DMEIF5_Pos)                 /*!< 0x00000100 */\r\n#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk                           \r\n#define DMA_HISR_FEIF5_Pos       (6U)                                          \r\n#define DMA_HISR_FEIF5_Msk       (0x1U << DMA_HISR_FEIF5_Pos)                  /*!< 0x00000040 */\r\n#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk                            \r\n#define DMA_HISR_TCIF4_Pos       (5U)                                          \r\n#define DMA_HISR_TCIF4_Msk       (0x1U << DMA_HISR_TCIF4_Pos)                  /*!< 0x00000020 */\r\n#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk                            \r\n#define DMA_HISR_HTIF4_Pos       (4U)                                          \r\n#define DMA_HISR_HTIF4_Msk       (0x1U << DMA_HISR_HTIF4_Pos)                  /*!< 0x00000010 */\r\n#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk                            \r\n#define DMA_HISR_TEIF4_Pos       (3U)                                          \r\n#define DMA_HISR_TEIF4_Msk       (0x1U << DMA_HISR_TEIF4_Pos)                  /*!< 0x00000008 */\r\n#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk                            \r\n#define DMA_HISR_DMEIF4_Pos      (2U)                                          \r\n#define DMA_HISR_DMEIF4_Msk      (0x1U << DMA_HISR_DMEIF4_Pos)                 /*!< 0x00000004 */\r\n#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk                           \r\n#define DMA_HISR_FEIF4_Pos       (0U)                                          \r\n#define DMA_HISR_FEIF4_Msk       (0x1U << DMA_HISR_FEIF4_Pos)                  /*!< 0x00000001 */\r\n#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk                            \r\n\r\n/********************  Bits definition for DMA_LIFCR register  ****************/\r\n#define DMA_LIFCR_CTCIF3_Pos     (27U)                                         \r\n#define DMA_LIFCR_CTCIF3_Msk     (0x1U << DMA_LIFCR_CTCIF3_Pos)                /*!< 0x08000000 */\r\n#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk                          \r\n#define DMA_LIFCR_CHTIF3_Pos     (26U)                                         \r\n#define DMA_LIFCR_CHTIF3_Msk     (0x1U << DMA_LIFCR_CHTIF3_Pos)                /*!< 0x04000000 */\r\n#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk                          \r\n#define DMA_LIFCR_CTEIF3_Pos     (25U)                                         \r\n#define DMA_LIFCR_CTEIF3_Msk     (0x1U << DMA_LIFCR_CTEIF3_Pos)                /*!< 0x02000000 */\r\n#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk                          \r\n#define DMA_LIFCR_CDMEIF3_Pos    (24U)                                         \r\n#define DMA_LIFCR_CDMEIF3_Msk    (0x1U << DMA_LIFCR_CDMEIF3_Pos)               /*!< 0x01000000 */\r\n#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk                         \r\n#define DMA_LIFCR_CFEIF3_Pos     (22U)                                         \r\n#define DMA_LIFCR_CFEIF3_Msk     (0x1U << DMA_LIFCR_CFEIF3_Pos)                /*!< 0x00400000 */\r\n#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk                          \r\n#define DMA_LIFCR_CTCIF2_Pos     (21U)                                         \r\n#define DMA_LIFCR_CTCIF2_Msk     (0x1U << DMA_LIFCR_CTCIF2_Pos)                /*!< 0x00200000 */\r\n#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk                          \r\n#define DMA_LIFCR_CHTIF2_Pos     (20U)                                         \r\n#define DMA_LIFCR_CHTIF2_Msk     (0x1U << DMA_LIFCR_CHTIF2_Pos)                /*!< 0x00100000 */\r\n#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk                          \r\n#define DMA_LIFCR_CTEIF2_Pos     (19U)                                         \r\n#define DMA_LIFCR_CTEIF2_Msk     (0x1U << DMA_LIFCR_CTEIF2_Pos)                /*!< 0x00080000 */\r\n#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk                          \r\n#define DMA_LIFCR_CDMEIF2_Pos    (18U)                                         \r\n#define DMA_LIFCR_CDMEIF2_Msk    (0x1U << DMA_LIFCR_CDMEIF2_Pos)               /*!< 0x00040000 */\r\n#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk                         \r\n#define DMA_LIFCR_CFEIF2_Pos     (16U)                                         \r\n#define DMA_LIFCR_CFEIF2_Msk     (0x1U << DMA_LIFCR_CFEIF2_Pos)                /*!< 0x00010000 */\r\n#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk                          \r\n#define DMA_LIFCR_CTCIF1_Pos     (11U)                                         \r\n#define DMA_LIFCR_CTCIF1_Msk     (0x1U << DMA_LIFCR_CTCIF1_Pos)                /*!< 0x00000800 */\r\n#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk                          \r\n#define DMA_LIFCR_CHTIF1_Pos     (10U)                                         \r\n#define DMA_LIFCR_CHTIF1_Msk     (0x1U << DMA_LIFCR_CHTIF1_Pos)                /*!< 0x00000400 */\r\n#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk                          \r\n#define DMA_LIFCR_CTEIF1_Pos     (9U)                                          \r\n#define DMA_LIFCR_CTEIF1_Msk     (0x1U << DMA_LIFCR_CTEIF1_Pos)                /*!< 0x00000200 */\r\n#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk                          \r\n#define DMA_LIFCR_CDMEIF1_Pos    (8U)                                          \r\n#define DMA_LIFCR_CDMEIF1_Msk    (0x1U << DMA_LIFCR_CDMEIF1_Pos)               /*!< 0x00000100 */\r\n#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk                         \r\n#define DMA_LIFCR_CFEIF1_Pos     (6U)                                          \r\n#define DMA_LIFCR_CFEIF1_Msk     (0x1U << DMA_LIFCR_CFEIF1_Pos)                /*!< 0x00000040 */\r\n#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk                          \r\n#define DMA_LIFCR_CTCIF0_Pos     (5U)                                          \r\n#define DMA_LIFCR_CTCIF0_Msk     (0x1U << DMA_LIFCR_CTCIF0_Pos)                /*!< 0x00000020 */\r\n#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk                          \r\n#define DMA_LIFCR_CHTIF0_Pos     (4U)                                          \r\n#define DMA_LIFCR_CHTIF0_Msk     (0x1U << DMA_LIFCR_CHTIF0_Pos)                /*!< 0x00000010 */\r\n#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk                          \r\n#define DMA_LIFCR_CTEIF0_Pos     (3U)                                          \r\n#define DMA_LIFCR_CTEIF0_Msk     (0x1U << DMA_LIFCR_CTEIF0_Pos)                /*!< 0x00000008 */\r\n#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk                          \r\n#define DMA_LIFCR_CDMEIF0_Pos    (2U)                                          \r\n#define DMA_LIFCR_CDMEIF0_Msk    (0x1U << DMA_LIFCR_CDMEIF0_Pos)               /*!< 0x00000004 */\r\n#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk                         \r\n#define DMA_LIFCR_CFEIF0_Pos     (0U)                                          \r\n#define DMA_LIFCR_CFEIF0_Msk     (0x1U << DMA_LIFCR_CFEIF0_Pos)                /*!< 0x00000001 */\r\n#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk                          \r\n\r\n/********************  Bits definition for DMA_HIFCR  register  ****************/\r\n#define DMA_HIFCR_CTCIF7_Pos     (27U)                                         \r\n#define DMA_HIFCR_CTCIF7_Msk     (0x1U << DMA_HIFCR_CTCIF7_Pos)                /*!< 0x08000000 */\r\n#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk                          \r\n#define DMA_HIFCR_CHTIF7_Pos     (26U)                                         \r\n#define DMA_HIFCR_CHTIF7_Msk     (0x1U << DMA_HIFCR_CHTIF7_Pos)                /*!< 0x04000000 */\r\n#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk                          \r\n#define DMA_HIFCR_CTEIF7_Pos     (25U)                                         \r\n#define DMA_HIFCR_CTEIF7_Msk     (0x1U << DMA_HIFCR_CTEIF7_Pos)                /*!< 0x02000000 */\r\n#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk                          \r\n#define DMA_HIFCR_CDMEIF7_Pos    (24U)                                         \r\n#define DMA_HIFCR_CDMEIF7_Msk    (0x1U << DMA_HIFCR_CDMEIF7_Pos)               /*!< 0x01000000 */\r\n#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk                         \r\n#define DMA_HIFCR_CFEIF7_Pos     (22U)                                         \r\n#define DMA_HIFCR_CFEIF7_Msk     (0x1U << DMA_HIFCR_CFEIF7_Pos)                /*!< 0x00400000 */\r\n#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk                          \r\n#define DMA_HIFCR_CTCIF6_Pos     (21U)                                         \r\n#define DMA_HIFCR_CTCIF6_Msk     (0x1U << DMA_HIFCR_CTCIF6_Pos)                /*!< 0x00200000 */\r\n#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk                          \r\n#define DMA_HIFCR_CHTIF6_Pos     (20U)                                         \r\n#define DMA_HIFCR_CHTIF6_Msk     (0x1U << DMA_HIFCR_CHTIF6_Pos)                /*!< 0x00100000 */\r\n#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk                          \r\n#define DMA_HIFCR_CTEIF6_Pos     (19U)                                         \r\n#define DMA_HIFCR_CTEIF6_Msk     (0x1U << DMA_HIFCR_CTEIF6_Pos)                /*!< 0x00080000 */\r\n#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk                          \r\n#define DMA_HIFCR_CDMEIF6_Pos    (18U)                                         \r\n#define DMA_HIFCR_CDMEIF6_Msk    (0x1U << DMA_HIFCR_CDMEIF6_Pos)               /*!< 0x00040000 */\r\n#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk                         \r\n#define DMA_HIFCR_CFEIF6_Pos     (16U)                                         \r\n#define DMA_HIFCR_CFEIF6_Msk     (0x1U << DMA_HIFCR_CFEIF6_Pos)                /*!< 0x00010000 */\r\n#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk                          \r\n#define DMA_HIFCR_CTCIF5_Pos     (11U)                                         \r\n#define DMA_HIFCR_CTCIF5_Msk     (0x1U << DMA_HIFCR_CTCIF5_Pos)                /*!< 0x00000800 */\r\n#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk                          \r\n#define DMA_HIFCR_CHTIF5_Pos     (10U)                                         \r\n#define DMA_HIFCR_CHTIF5_Msk     (0x1U << DMA_HIFCR_CHTIF5_Pos)                /*!< 0x00000400 */\r\n#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk                          \r\n#define DMA_HIFCR_CTEIF5_Pos     (9U)                                          \r\n#define DMA_HIFCR_CTEIF5_Msk     (0x1U << DMA_HIFCR_CTEIF5_Pos)                /*!< 0x00000200 */\r\n#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk                          \r\n#define DMA_HIFCR_CDMEIF5_Pos    (8U)                                          \r\n#define DMA_HIFCR_CDMEIF5_Msk    (0x1U << DMA_HIFCR_CDMEIF5_Pos)               /*!< 0x00000100 */\r\n#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk                         \r\n#define DMA_HIFCR_CFEIF5_Pos     (6U)                                          \r\n#define DMA_HIFCR_CFEIF5_Msk     (0x1U << DMA_HIFCR_CFEIF5_Pos)                /*!< 0x00000040 */\r\n#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk                          \r\n#define DMA_HIFCR_CTCIF4_Pos     (5U)                                          \r\n#define DMA_HIFCR_CTCIF4_Msk     (0x1U << DMA_HIFCR_CTCIF4_Pos)                /*!< 0x00000020 */\r\n#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk                          \r\n#define DMA_HIFCR_CHTIF4_Pos     (4U)                                          \r\n#define DMA_HIFCR_CHTIF4_Msk     (0x1U << DMA_HIFCR_CHTIF4_Pos)                /*!< 0x00000010 */\r\n#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk                          \r\n#define DMA_HIFCR_CTEIF4_Pos     (3U)                                          \r\n#define DMA_HIFCR_CTEIF4_Msk     (0x1U << DMA_HIFCR_CTEIF4_Pos)                /*!< 0x00000008 */\r\n#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk                          \r\n#define DMA_HIFCR_CDMEIF4_Pos    (2U)                                          \r\n#define DMA_HIFCR_CDMEIF4_Msk    (0x1U << DMA_HIFCR_CDMEIF4_Pos)               /*!< 0x00000004 */\r\n#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk                         \r\n#define DMA_HIFCR_CFEIF4_Pos     (0U)                                          \r\n#define DMA_HIFCR_CFEIF4_Msk     (0x1U << DMA_HIFCR_CFEIF4_Pos)                /*!< 0x00000001 */\r\n#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk                          \r\n\r\n/******************  Bit definition for DMA_SxPAR register  ********************/\r\n#define DMA_SxPAR_PA_Pos         (0U)                                          \r\n#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFU << DMA_SxPAR_PA_Pos)             /*!< 0xFFFFFFFF */\r\n#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */\r\n\r\n/******************  Bit definition for DMA_SxM0AR register  ********************/\r\n#define DMA_SxM0AR_M0A_Pos       (0U)                                          \r\n#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos)           /*!< 0xFFFFFFFF */\r\n#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory Address */\r\n\r\n/******************  Bit definition for DMA_SxM1AR register  ********************/\r\n#define DMA_SxM1AR_M1A_Pos       (0U)                                          \r\n#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos)           /*!< 0xFFFFFFFF */\r\n#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory Address */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                         AHB Master DMA2D Controller (DMA2D)                */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bit definition for DMA2D_CR register  ******************/\r\n\r\n#define DMA2D_CR_START_Pos         (0U)                                        \r\n#define DMA2D_CR_START_Msk         (0x1U << DMA2D_CR_START_Pos)                /*!< 0x00000001 */\r\n#define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer                          */\r\n#define DMA2D_CR_SUSP_Pos          (1U)                                        \r\n#define DMA2D_CR_SUSP_Msk          (0x1U << DMA2D_CR_SUSP_Pos)                 /*!< 0x00000002 */\r\n#define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer                        */\r\n#define DMA2D_CR_ABORT_Pos         (2U)                                        \r\n#define DMA2D_CR_ABORT_Msk         (0x1U << DMA2D_CR_ABORT_Pos)                /*!< 0x00000004 */\r\n#define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer                          */\r\n#define DMA2D_CR_TEIE_Pos          (8U)                                        \r\n#define DMA2D_CR_TEIE_Msk          (0x1U << DMA2D_CR_TEIE_Pos)                 /*!< 0x00000100 */\r\n#define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable         */\r\n#define DMA2D_CR_TCIE_Pos          (9U)                                        \r\n#define DMA2D_CR_TCIE_Msk          (0x1U << DMA2D_CR_TCIE_Pos)                 /*!< 0x00000200 */\r\n#define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable      */\r\n#define DMA2D_CR_TWIE_Pos          (10U)                                       \r\n#define DMA2D_CR_TWIE_Msk          (0x1U << DMA2D_CR_TWIE_Pos)                 /*!< 0x00000400 */\r\n#define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable     */\r\n#define DMA2D_CR_CAEIE_Pos         (11U)                                       \r\n#define DMA2D_CR_CAEIE_Msk         (0x1U << DMA2D_CR_CAEIE_Pos)                /*!< 0x00000800 */\r\n#define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable      */\r\n#define DMA2D_CR_CTCIE_Pos         (12U)                                       \r\n#define DMA2D_CR_CTCIE_Msk         (0x1U << DMA2D_CR_CTCIE_Pos)                /*!< 0x00001000 */\r\n#define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */\r\n#define DMA2D_CR_CEIE_Pos          (13U)                                       \r\n#define DMA2D_CR_CEIE_Msk          (0x1U << DMA2D_CR_CEIE_Pos)                 /*!< 0x00002000 */\r\n#define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable    */\r\n#define DMA2D_CR_MODE_Pos          (16U)                                       \r\n#define DMA2D_CR_MODE_Msk          (0x3U << DMA2D_CR_MODE_Pos)                 /*!< 0x00030000 */\r\n#define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[1:0]                         */\r\n#define DMA2D_CR_MODE_0            (0x1U << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */\r\n#define DMA2D_CR_MODE_1            (0x2U << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */\r\n\r\n/********************  Bit definition for DMA2D_ISR register  *****************/\r\n\r\n#define DMA2D_ISR_TEIF_Pos         (0U)                                        \r\n#define DMA2D_ISR_TEIF_Msk         (0x1U << DMA2D_ISR_TEIF_Pos)                /*!< 0x00000001 */\r\n#define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag         */\r\n#define DMA2D_ISR_TCIF_Pos         (1U)                                        \r\n#define DMA2D_ISR_TCIF_Msk         (0x1U << DMA2D_ISR_TCIF_Pos)                /*!< 0x00000002 */\r\n#define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag      */\r\n#define DMA2D_ISR_TWIF_Pos         (2U)                                        \r\n#define DMA2D_ISR_TWIF_Msk         (0x1U << DMA2D_ISR_TWIF_Pos)                /*!< 0x00000004 */\r\n#define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag     */\r\n#define DMA2D_ISR_CAEIF_Pos        (3U)                                        \r\n#define DMA2D_ISR_CAEIF_Msk        (0x1U << DMA2D_ISR_CAEIF_Pos)               /*!< 0x00000008 */\r\n#define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag      */\r\n#define DMA2D_ISR_CTCIF_Pos        (4U)                                        \r\n#define DMA2D_ISR_CTCIF_Msk        (0x1U << DMA2D_ISR_CTCIF_Pos)               /*!< 0x00000010 */\r\n#define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */\r\n#define DMA2D_ISR_CEIF_Pos         (5U)                                        \r\n#define DMA2D_ISR_CEIF_Msk         (0x1U << DMA2D_ISR_CEIF_Pos)                /*!< 0x00000020 */\r\n#define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag    */\r\n\r\n/********************  Bit definition for DMA2D_IFCR register  ****************/\r\n\r\n#define DMA2D_IFCR_CTEIF_Pos       (0U)                                        \r\n#define DMA2D_IFCR_CTEIF_Msk       (0x1U << DMA2D_IFCR_CTEIF_Pos)              /*!< 0x00000001 */\r\n#define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag         */\r\n#define DMA2D_IFCR_CTCIF_Pos       (1U)                                        \r\n#define DMA2D_IFCR_CTCIF_Msk       (0x1U << DMA2D_IFCR_CTCIF_Pos)              /*!< 0x00000002 */\r\n#define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag      */\r\n#define DMA2D_IFCR_CTWIF_Pos       (2U)                                        \r\n#define DMA2D_IFCR_CTWIF_Msk       (0x1U << DMA2D_IFCR_CTWIF_Pos)              /*!< 0x00000004 */\r\n#define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag     */\r\n#define DMA2D_IFCR_CAECIF_Pos      (3U)                                        \r\n#define DMA2D_IFCR_CAECIF_Msk      (0x1U << DMA2D_IFCR_CAECIF_Pos)             /*!< 0x00000008 */\r\n#define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag      */\r\n#define DMA2D_IFCR_CCTCIF_Pos      (4U)                                        \r\n#define DMA2D_IFCR_CCTCIF_Msk      (0x1U << DMA2D_IFCR_CCTCIF_Pos)             /*!< 0x00000010 */\r\n#define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */\r\n#define DMA2D_IFCR_CCEIF_Pos       (5U)                                        \r\n#define DMA2D_IFCR_CCEIF_Msk       (0x1U << DMA2D_IFCR_CCEIF_Pos)              /*!< 0x00000020 */\r\n#define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag    */\r\n\r\n/* Legacy defines */\r\n#define DMA2D_IFSR_CTEIF                   DMA2D_IFCR_CTEIF                     /*!< Clears Transfer Error Interrupt Flag         */\r\n#define DMA2D_IFSR_CTCIF                   DMA2D_IFCR_CTCIF                     /*!< Clears Transfer Complete Interrupt Flag      */\r\n#define DMA2D_IFSR_CTWIF                   DMA2D_IFCR_CTWIF                     /*!< Clears Transfer Watermark Interrupt Flag     */\r\n#define DMA2D_IFSR_CCAEIF                  DMA2D_IFCR_CAECIF                    /*!< Clears CLUT Access Error Interrupt Flag      */\r\n#define DMA2D_IFSR_CCTCIF                  DMA2D_IFCR_CCTCIF                    /*!< Clears CLUT Transfer Complete Interrupt Flag */\r\n#define DMA2D_IFSR_CCEIF                   DMA2D_IFCR_CCEIF                     /*!< Clears Configuration Error Interrupt Flag    */\r\n\r\n/********************  Bit definition for DMA2D_FGMAR register  ***************/\r\n\r\n#define DMA2D_FGMAR_MA_Pos         (0U)                                        \r\n#define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFU << DMA2D_FGMAR_MA_Pos)         /*!< 0xFFFFFFFF */\r\n#define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Memory Address */\r\n\r\n/********************  Bit definition for DMA2D_FGOR register  ****************/\r\n\r\n#define DMA2D_FGOR_LO_Pos          (0U)                                        \r\n#define DMA2D_FGOR_LO_Msk          (0x3FFFU << DMA2D_FGOR_LO_Pos)              /*!< 0x00003FFF */\r\n#define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */\r\n\r\n/********************  Bit definition for DMA2D_BGMAR register  ***************/\r\n\r\n#define DMA2D_BGMAR_MA_Pos         (0U)                                        \r\n#define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFU << DMA2D_BGMAR_MA_Pos)         /*!< 0xFFFFFFFF */\r\n#define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Memory Address */\r\n\r\n/********************  Bit definition for DMA2D_BGOR register  ****************/\r\n\r\n#define DMA2D_BGOR_LO_Pos          (0U)                                        \r\n#define DMA2D_BGOR_LO_Msk          (0x3FFFU << DMA2D_BGOR_LO_Pos)              /*!< 0x00003FFF */\r\n#define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */\r\n\r\n/********************  Bit definition for DMA2D_FGPFCCR register  *************/\r\n\r\n#define DMA2D_FGPFCCR_CM_Pos       (0U)                                        \r\n#define DMA2D_FGPFCCR_CM_Msk       (0xFU << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x0000000F */\r\n#define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */\r\n#define DMA2D_FGPFCCR_CM_0         (0x1U << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */\r\n#define DMA2D_FGPFCCR_CM_1         (0x2U << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */\r\n#define DMA2D_FGPFCCR_CM_2         (0x4U << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */\r\n#define DMA2D_FGPFCCR_CM_3         (0x8U << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */\r\n#define DMA2D_FGPFCCR_CCM_Pos      (4U)                                        \r\n#define DMA2D_FGPFCCR_CCM_Msk      (0x1U << DMA2D_FGPFCCR_CCM_Pos)             /*!< 0x00000010 */\r\n#define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */\r\n#define DMA2D_FGPFCCR_START_Pos    (5U)                                        \r\n#define DMA2D_FGPFCCR_START_Msk    (0x1U << DMA2D_FGPFCCR_START_Pos)           /*!< 0x00000020 */\r\n#define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */\r\n#define DMA2D_FGPFCCR_CS_Pos       (8U)                                        \r\n#define DMA2D_FGPFCCR_CS_Msk       (0xFFU << DMA2D_FGPFCCR_CS_Pos)             /*!< 0x0000FF00 */\r\n#define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */\r\n#define DMA2D_FGPFCCR_AM_Pos       (16U)                                       \r\n#define DMA2D_FGPFCCR_AM_Msk       (0x3U << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00030000 */\r\n#define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */\r\n#define DMA2D_FGPFCCR_AM_0         (0x1U << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */\r\n#define DMA2D_FGPFCCR_AM_1         (0x2U << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */\r\n#define DMA2D_FGPFCCR_ALPHA_Pos    (24U)                                       \r\n#define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFU << DMA2D_FGPFCCR_ALPHA_Pos)          /*!< 0xFF000000 */\r\n#define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */\r\n\r\n/********************  Bit definition for DMA2D_FGCOLR register  **************/\r\n\r\n#define DMA2D_FGCOLR_BLUE_Pos      (0U)                                        \r\n#define DMA2D_FGCOLR_BLUE_Msk      (0xFFU << DMA2D_FGCOLR_BLUE_Pos)            /*!< 0x000000FF */\r\n#define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Blue Value */\r\n#define DMA2D_FGCOLR_GREEN_Pos     (8U)                                        \r\n#define DMA2D_FGCOLR_GREEN_Msk     (0xFFU << DMA2D_FGCOLR_GREEN_Pos)           /*!< 0x0000FF00 */\r\n#define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Green Value */\r\n#define DMA2D_FGCOLR_RED_Pos       (16U)                                       \r\n#define DMA2D_FGCOLR_RED_Msk       (0xFFU << DMA2D_FGCOLR_RED_Pos)             /*!< 0x00FF0000 */\r\n#define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Red Value */\r\n\r\n/********************  Bit definition for DMA2D_BGPFCCR register  *************/\r\n\r\n#define DMA2D_BGPFCCR_CM_Pos       (0U)                                        \r\n#define DMA2D_BGPFCCR_CM_Msk       (0xFU << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x0000000F */\r\n#define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */\r\n#define DMA2D_BGPFCCR_CM_0         (0x1U << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */\r\n#define DMA2D_BGPFCCR_CM_1         (0x2U << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */\r\n#define DMA2D_BGPFCCR_CM_2         (0x4U << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */\r\n#define DMA2D_BGPFCCR_CM_3         0x00000008U                                 /*!< Input color mode CM bit 3 */\r\n#define DMA2D_BGPFCCR_CCM_Pos      (4U)                                        \r\n#define DMA2D_BGPFCCR_CCM_Msk      (0x1U << DMA2D_BGPFCCR_CCM_Pos)             /*!< 0x00000010 */\r\n#define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */\r\n#define DMA2D_BGPFCCR_START_Pos    (5U)                                        \r\n#define DMA2D_BGPFCCR_START_Msk    (0x1U << DMA2D_BGPFCCR_START_Pos)           /*!< 0x00000020 */\r\n#define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */\r\n#define DMA2D_BGPFCCR_CS_Pos       (8U)                                        \r\n#define DMA2D_BGPFCCR_CS_Msk       (0xFFU << DMA2D_BGPFCCR_CS_Pos)             /*!< 0x0000FF00 */\r\n#define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */\r\n#define DMA2D_BGPFCCR_AM_Pos       (16U)                                       \r\n#define DMA2D_BGPFCCR_AM_Msk       (0x3U << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00030000 */\r\n#define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */\r\n#define DMA2D_BGPFCCR_AM_0         (0x1U << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */\r\n#define DMA2D_BGPFCCR_AM_1         (0x2U << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */\r\n#define DMA2D_BGPFCCR_ALPHA_Pos    (24U)                                       \r\n#define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFU << DMA2D_BGPFCCR_ALPHA_Pos)          /*!< 0xFF000000 */\r\n#define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< background Input Alpha value */\r\n\r\n/********************  Bit definition for DMA2D_BGCOLR register  **************/\r\n\r\n#define DMA2D_BGCOLR_BLUE_Pos      (0U)                                        \r\n#define DMA2D_BGCOLR_BLUE_Msk      (0xFFU << DMA2D_BGCOLR_BLUE_Pos)            /*!< 0x000000FF */\r\n#define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Blue Value */\r\n#define DMA2D_BGCOLR_GREEN_Pos     (8U)                                        \r\n#define DMA2D_BGCOLR_GREEN_Msk     (0xFFU << DMA2D_BGCOLR_GREEN_Pos)           /*!< 0x0000FF00 */\r\n#define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Green Value */\r\n#define DMA2D_BGCOLR_RED_Pos       (16U)                                       \r\n#define DMA2D_BGCOLR_RED_Msk       (0xFFU << DMA2D_BGCOLR_RED_Pos)             /*!< 0x00FF0000 */\r\n#define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Red Value */\r\n\r\n/********************  Bit definition for DMA2D_FGCMAR register  **************/\r\n\r\n#define DMA2D_FGCMAR_MA_Pos        (0U)                                        \r\n#define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFU << DMA2D_FGCMAR_MA_Pos)        /*!< 0xFFFFFFFF */\r\n#define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Memory Address */\r\n\r\n/********************  Bit definition for DMA2D_BGCMAR register  **************/\r\n\r\n#define DMA2D_BGCMAR_MA_Pos        (0U)                                        \r\n#define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFU << DMA2D_BGCMAR_MA_Pos)        /*!< 0xFFFFFFFF */\r\n#define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Memory Address */\r\n\r\n/********************  Bit definition for DMA2D_OPFCCR register  **************/\r\n\r\n#define DMA2D_OPFCCR_CM_Pos        (0U)                                        \r\n#define DMA2D_OPFCCR_CM_Msk        (0x7U << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000007 */\r\n#define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Color mode CM[2:0] */\r\n#define DMA2D_OPFCCR_CM_0          (0x1U << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000001 */\r\n#define DMA2D_OPFCCR_CM_1          (0x2U << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000002 */\r\n#define DMA2D_OPFCCR_CM_2          (0x4U << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000004 */\r\n\r\n/********************  Bit definition for DMA2D_OCOLR register  ***************/\r\n\r\n/*!<Mode_ARGB8888/RGB888 */\r\n\r\n#define DMA2D_OCOLR_BLUE_1         0x000000FFU                                 /*!< BLUE Value */\r\n#define DMA2D_OCOLR_GREEN_1        0x0000FF00U                                 /*!< GREEN Value  */\r\n#define DMA2D_OCOLR_RED_1          0x00FF0000U                                 /*!< Red Value */\r\n#define DMA2D_OCOLR_ALPHA_1        0xFF000000U                                 /*!< Alpha Channel Value */\r\n\r\n/*!<Mode_RGB565 */\r\n#define DMA2D_OCOLR_BLUE_2         0x0000001FU                                 /*!< BLUE Value */\r\n#define DMA2D_OCOLR_GREEN_2        0x000007E0U                                 /*!< GREEN Value  */\r\n#define DMA2D_OCOLR_RED_2          0x0000F800U                                 /*!< Red Value */\r\n\r\n/*!<Mode_ARGB1555 */\r\n#define DMA2D_OCOLR_BLUE_3         0x0000001FU                                 /*!< BLUE Value */\r\n#define DMA2D_OCOLR_GREEN_3        0x000003E0U                                 /*!< GREEN Value  */\r\n#define DMA2D_OCOLR_RED_3          0x00007C00U                                 /*!< Red Value */\r\n#define DMA2D_OCOLR_ALPHA_3        0x00008000U                                 /*!< Alpha Channel Value */\r\n\r\n/*!<Mode_ARGB4444 */\r\n#define DMA2D_OCOLR_BLUE_4         0x0000000FU                                 /*!< BLUE Value */\r\n#define DMA2D_OCOLR_GREEN_4        0x000000F0U                                 /*!< GREEN Value  */\r\n#define DMA2D_OCOLR_RED_4          0x00000F00U                                 /*!< Red Value */\r\n#define DMA2D_OCOLR_ALPHA_4        0x0000F000U                                 /*!< Alpha Channel Value */\r\n\r\n/********************  Bit definition for DMA2D_OMAR register  ****************/\r\n\r\n#define DMA2D_OMAR_MA_Pos          (0U)                                        \r\n#define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFU << DMA2D_OMAR_MA_Pos)          /*!< 0xFFFFFFFF */\r\n#define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Memory Address */\r\n\r\n/********************  Bit definition for DMA2D_OOR register  *****************/\r\n\r\n#define DMA2D_OOR_LO_Pos           (0U)                                        \r\n#define DMA2D_OOR_LO_Msk           (0x3FFFU << DMA2D_OOR_LO_Pos)               /*!< 0x00003FFF */\r\n#define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Line Offset */\r\n\r\n/********************  Bit definition for DMA2D_NLR register  *****************/\r\n\r\n#define DMA2D_NLR_NL_Pos           (0U)                                        \r\n#define DMA2D_NLR_NL_Msk           (0xFFFFU << DMA2D_NLR_NL_Pos)               /*!< 0x0000FFFF */\r\n#define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */\r\n#define DMA2D_NLR_PL_Pos           (16U)                                       \r\n#define DMA2D_NLR_PL_Msk           (0x3FFFU << DMA2D_NLR_PL_Pos)               /*!< 0x3FFF0000 */\r\n#define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */\r\n\r\n/********************  Bit definition for DMA2D_LWR register  *****************/\r\n\r\n#define DMA2D_LWR_LW_Pos           (0U)                                        \r\n#define DMA2D_LWR_LW_Msk           (0xFFFFU << DMA2D_LWR_LW_Pos)               /*!< 0x0000FFFF */\r\n#define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */\r\n\r\n/********************  Bit definition for DMA2D_AMTCR register  ***************/\r\n\r\n#define DMA2D_AMTCR_EN_Pos         (0U)                                        \r\n#define DMA2D_AMTCR_EN_Msk         (0x1U << DMA2D_AMTCR_EN_Pos)                /*!< 0x00000001 */\r\n#define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */\r\n#define DMA2D_AMTCR_DT_Pos         (8U)                                        \r\n#define DMA2D_AMTCR_DT_Msk         (0xFFU << DMA2D_AMTCR_DT_Pos)               /*!< 0x0000FF00 */\r\n#define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */\r\n\r\n\r\n/********************  Bit definition for DMA2D_FGCLUT register  **************/\r\n\r\n/********************  Bit definition for DMA2D_BGCLUT register  **************/\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                    External Interrupt/Event Controller                     */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************  Bit definition for EXTI_IMR register  *******************/\r\n#define EXTI_IMR_MR0_Pos          (0U)                                         \r\n#define EXTI_IMR_MR0_Msk          (0x1U << EXTI_IMR_MR0_Pos)                   /*!< 0x00000001 */\r\n#define EXTI_IMR_MR0              EXTI_IMR_MR0_Msk                             /*!< Interrupt Mask on line 0 */\r\n#define EXTI_IMR_MR1_Pos          (1U)                                         \r\n#define EXTI_IMR_MR1_Msk          (0x1U << EXTI_IMR_MR1_Pos)                   /*!< 0x00000002 */\r\n#define EXTI_IMR_MR1              EXTI_IMR_MR1_Msk                             /*!< Interrupt Mask on line 1 */\r\n#define EXTI_IMR_MR2_Pos          (2U)                                         \r\n#define EXTI_IMR_MR2_Msk          (0x1U << EXTI_IMR_MR2_Pos)                   /*!< 0x00000004 */\r\n#define EXTI_IMR_MR2              EXTI_IMR_MR2_Msk                             /*!< Interrupt Mask on line 2 */\r\n#define EXTI_IMR_MR3_Pos          (3U)                                         \r\n#define EXTI_IMR_MR3_Msk          (0x1U << EXTI_IMR_MR3_Pos)                   /*!< 0x00000008 */\r\n#define EXTI_IMR_MR3              EXTI_IMR_MR3_Msk                             /*!< Interrupt Mask on line 3 */\r\n#define EXTI_IMR_MR4_Pos          (4U)                                         \r\n#define EXTI_IMR_MR4_Msk          (0x1U << EXTI_IMR_MR4_Pos)                   /*!< 0x00000010 */\r\n#define EXTI_IMR_MR4              EXTI_IMR_MR4_Msk                             /*!< Interrupt Mask on line 4 */\r\n#define EXTI_IMR_MR5_Pos          (5U)                                         \r\n#define EXTI_IMR_MR5_Msk          (0x1U << EXTI_IMR_MR5_Pos)                   /*!< 0x00000020 */\r\n#define EXTI_IMR_MR5              EXTI_IMR_MR5_Msk                             /*!< Interrupt Mask on line 5 */\r\n#define EXTI_IMR_MR6_Pos          (6U)                                         \r\n#define EXTI_IMR_MR6_Msk          (0x1U << EXTI_IMR_MR6_Pos)                   /*!< 0x00000040 */\r\n#define EXTI_IMR_MR6              EXTI_IMR_MR6_Msk                             /*!< Interrupt Mask on line 6 */\r\n#define EXTI_IMR_MR7_Pos          (7U)                                         \r\n#define EXTI_IMR_MR7_Msk          (0x1U << EXTI_IMR_MR7_Pos)                   /*!< 0x00000080 */\r\n#define EXTI_IMR_MR7              EXTI_IMR_MR7_Msk                             /*!< Interrupt Mask on line 7 */\r\n#define EXTI_IMR_MR8_Pos          (8U)                                         \r\n#define EXTI_IMR_MR8_Msk          (0x1U << EXTI_IMR_MR8_Pos)                   /*!< 0x00000100 */\r\n#define EXTI_IMR_MR8              EXTI_IMR_MR8_Msk                             /*!< Interrupt Mask on line 8 */\r\n#define EXTI_IMR_MR9_Pos          (9U)                                         \r\n#define EXTI_IMR_MR9_Msk          (0x1U << EXTI_IMR_MR9_Pos)                   /*!< 0x00000200 */\r\n#define EXTI_IMR_MR9              EXTI_IMR_MR9_Msk                             /*!< Interrupt Mask on line 9 */\r\n#define EXTI_IMR_MR10_Pos         (10U)                                        \r\n#define EXTI_IMR_MR10_Msk         (0x1U << EXTI_IMR_MR10_Pos)                  /*!< 0x00000400 */\r\n#define EXTI_IMR_MR10             EXTI_IMR_MR10_Msk                            /*!< Interrupt Mask on line 10 */\r\n#define EXTI_IMR_MR11_Pos         (11U)                                        \r\n#define EXTI_IMR_MR11_Msk         (0x1U << EXTI_IMR_MR11_Pos)                  /*!< 0x00000800 */\r\n#define EXTI_IMR_MR11             EXTI_IMR_MR11_Msk                            /*!< Interrupt Mask on line 11 */\r\n#define EXTI_IMR_MR12_Pos         (12U)                                        \r\n#define EXTI_IMR_MR12_Msk         (0x1U << EXTI_IMR_MR12_Pos)                  /*!< 0x00001000 */\r\n#define EXTI_IMR_MR12             EXTI_IMR_MR12_Msk                            /*!< Interrupt Mask on line 12 */\r\n#define EXTI_IMR_MR13_Pos         (13U)                                        \r\n#define EXTI_IMR_MR13_Msk         (0x1U << EXTI_IMR_MR13_Pos)                  /*!< 0x00002000 */\r\n#define EXTI_IMR_MR13             EXTI_IMR_MR13_Msk                            /*!< Interrupt Mask on line 13 */\r\n#define EXTI_IMR_MR14_Pos         (14U)                                        \r\n#define EXTI_IMR_MR14_Msk         (0x1U << EXTI_IMR_MR14_Pos)                  /*!< 0x00004000 */\r\n#define EXTI_IMR_MR14             EXTI_IMR_MR14_Msk                            /*!< Interrupt Mask on line 14 */\r\n#define EXTI_IMR_MR15_Pos         (15U)                                        \r\n#define EXTI_IMR_MR15_Msk         (0x1U << EXTI_IMR_MR15_Pos)                  /*!< 0x00008000 */\r\n#define EXTI_IMR_MR15             EXTI_IMR_MR15_Msk                            /*!< Interrupt Mask on line 15 */\r\n#define EXTI_IMR_MR16_Pos         (16U)                                        \r\n#define EXTI_IMR_MR16_Msk         (0x1U << EXTI_IMR_MR16_Pos)                  /*!< 0x00010000 */\r\n#define EXTI_IMR_MR16             EXTI_IMR_MR16_Msk                            /*!< Interrupt Mask on line 16 */\r\n#define EXTI_IMR_MR17_Pos         (17U)                                        \r\n#define EXTI_IMR_MR17_Msk         (0x1U << EXTI_IMR_MR17_Pos)                  /*!< 0x00020000 */\r\n#define EXTI_IMR_MR17             EXTI_IMR_MR17_Msk                            /*!< Interrupt Mask on line 17 */\r\n#define EXTI_IMR_MR18_Pos         (18U)                                        \r\n#define EXTI_IMR_MR18_Msk         (0x1U << EXTI_IMR_MR18_Pos)                  /*!< 0x00040000 */\r\n#define EXTI_IMR_MR18             EXTI_IMR_MR18_Msk                            /*!< Interrupt Mask on line 18 */\r\n#define EXTI_IMR_MR19_Pos         (19U)                                        \r\n#define EXTI_IMR_MR19_Msk         (0x1U << EXTI_IMR_MR19_Pos)                  /*!< 0x00080000 */\r\n#define EXTI_IMR_MR19             EXTI_IMR_MR19_Msk                            /*!< Interrupt Mask on line 19 */\r\n#define EXTI_IMR_MR20_Pos         (20U)                                        \r\n#define EXTI_IMR_MR20_Msk         (0x1U << EXTI_IMR_MR20_Pos)                  /*!< 0x00100000 */\r\n#define EXTI_IMR_MR20             EXTI_IMR_MR20_Msk                            /*!< Interrupt Mask on line 20 */\r\n#define EXTI_IMR_MR21_Pos         (21U)                                        \r\n#define EXTI_IMR_MR21_Msk         (0x1U << EXTI_IMR_MR21_Pos)                  /*!< 0x00200000 */\r\n#define EXTI_IMR_MR21             EXTI_IMR_MR21_Msk                            /*!< Interrupt Mask on line 21 */\r\n#define EXTI_IMR_MR22_Pos         (22U)                                        \r\n#define EXTI_IMR_MR22_Msk         (0x1U << EXTI_IMR_MR22_Pos)                  /*!< 0x00400000 */\r\n#define EXTI_IMR_MR22             EXTI_IMR_MR22_Msk                            /*!< Interrupt Mask on line 22 */\r\n#define EXTI_IMR_MR23_Pos         (23U)                                        \r\n#define EXTI_IMR_MR23_Msk         (0x1U << EXTI_IMR_MR23_Pos)                  /*!< 0x00800000 */\r\n#define EXTI_IMR_MR23             EXTI_IMR_MR23_Msk                            /*!< Interrupt Mask on line 23 */\r\n\r\n/* Reference Defines */\r\n#define  EXTI_IMR_IM0                        EXTI_IMR_MR0\r\n#define  EXTI_IMR_IM1                        EXTI_IMR_MR1\r\n#define  EXTI_IMR_IM2                        EXTI_IMR_MR2\r\n#define  EXTI_IMR_IM3                        EXTI_IMR_MR3\r\n#define  EXTI_IMR_IM4                        EXTI_IMR_MR4\r\n#define  EXTI_IMR_IM5                        EXTI_IMR_MR5\r\n#define  EXTI_IMR_IM6                        EXTI_IMR_MR6\r\n#define  EXTI_IMR_IM7                        EXTI_IMR_MR7\r\n#define  EXTI_IMR_IM8                        EXTI_IMR_MR8\r\n#define  EXTI_IMR_IM9                        EXTI_IMR_MR9\r\n#define  EXTI_IMR_IM10                       EXTI_IMR_MR10\r\n#define  EXTI_IMR_IM11                       EXTI_IMR_MR11\r\n#define  EXTI_IMR_IM12                       EXTI_IMR_MR12\r\n#define  EXTI_IMR_IM13                       EXTI_IMR_MR13\r\n#define  EXTI_IMR_IM14                       EXTI_IMR_MR14\r\n#define  EXTI_IMR_IM15                       EXTI_IMR_MR15\r\n#define  EXTI_IMR_IM16                       EXTI_IMR_MR16\r\n#define  EXTI_IMR_IM17                       EXTI_IMR_MR17\r\n#define  EXTI_IMR_IM18                       EXTI_IMR_MR18\r\n#define  EXTI_IMR_IM19                       EXTI_IMR_MR19\r\n#define  EXTI_IMR_IM20                       EXTI_IMR_MR20\r\n#define  EXTI_IMR_IM21                       EXTI_IMR_MR21\r\n#define  EXTI_IMR_IM22                       EXTI_IMR_MR22\r\n#define  EXTI_IMR_IM23                       EXTI_IMR_MR23\r\n\r\n#define EXTI_IMR_IM_Pos           (0U)                                         \r\n#define EXTI_IMR_IM_Msk           (0xFFFFFFU << EXTI_IMR_IM_Pos)               /*!< 0x00FFFFFF */\r\n#define EXTI_IMR_IM               EXTI_IMR_IM_Msk                              /*!< Interrupt Mask All */\r\n\r\n/*******************  Bit definition for EXTI_EMR register  *******************/\r\n#define EXTI_EMR_MR0_Pos          (0U)                                         \r\n#define EXTI_EMR_MR0_Msk          (0x1U << EXTI_EMR_MR0_Pos)                   /*!< 0x00000001 */\r\n#define EXTI_EMR_MR0              EXTI_EMR_MR0_Msk                             /*!< Event Mask on line 0 */\r\n#define EXTI_EMR_MR1_Pos          (1U)                                         \r\n#define EXTI_EMR_MR1_Msk          (0x1U << EXTI_EMR_MR1_Pos)                   /*!< 0x00000002 */\r\n#define EXTI_EMR_MR1              EXTI_EMR_MR1_Msk                             /*!< Event Mask on line 1 */\r\n#define EXTI_EMR_MR2_Pos          (2U)                                         \r\n#define EXTI_EMR_MR2_Msk          (0x1U << EXTI_EMR_MR2_Pos)                   /*!< 0x00000004 */\r\n#define EXTI_EMR_MR2              EXTI_EMR_MR2_Msk                             /*!< Event Mask on line 2 */\r\n#define EXTI_EMR_MR3_Pos          (3U)                                         \r\n#define EXTI_EMR_MR3_Msk          (0x1U << EXTI_EMR_MR3_Pos)                   /*!< 0x00000008 */\r\n#define EXTI_EMR_MR3              EXTI_EMR_MR3_Msk                             /*!< Event Mask on line 3 */\r\n#define EXTI_EMR_MR4_Pos          (4U)                                         \r\n#define EXTI_EMR_MR4_Msk          (0x1U << EXTI_EMR_MR4_Pos)                   /*!< 0x00000010 */\r\n#define EXTI_EMR_MR4              EXTI_EMR_MR4_Msk                             /*!< Event Mask on line 4 */\r\n#define EXTI_EMR_MR5_Pos          (5U)                                         \r\n#define EXTI_EMR_MR5_Msk          (0x1U << EXTI_EMR_MR5_Pos)                   /*!< 0x00000020 */\r\n#define EXTI_EMR_MR5              EXTI_EMR_MR5_Msk                             /*!< Event Mask on line 5 */\r\n#define EXTI_EMR_MR6_Pos          (6U)                                         \r\n#define EXTI_EMR_MR6_Msk          (0x1U << EXTI_EMR_MR6_Pos)                   /*!< 0x00000040 */\r\n#define EXTI_EMR_MR6              EXTI_EMR_MR6_Msk                             /*!< Event Mask on line 6 */\r\n#define EXTI_EMR_MR7_Pos          (7U)                                         \r\n#define EXTI_EMR_MR7_Msk          (0x1U << EXTI_EMR_MR7_Pos)                   /*!< 0x00000080 */\r\n#define EXTI_EMR_MR7              EXTI_EMR_MR7_Msk                             /*!< Event Mask on line 7 */\r\n#define EXTI_EMR_MR8_Pos          (8U)                                         \r\n#define EXTI_EMR_MR8_Msk          (0x1U << EXTI_EMR_MR8_Pos)                   /*!< 0x00000100 */\r\n#define EXTI_EMR_MR8              EXTI_EMR_MR8_Msk                             /*!< Event Mask on line 8 */\r\n#define EXTI_EMR_MR9_Pos          (9U)                                         \r\n#define EXTI_EMR_MR9_Msk          (0x1U << EXTI_EMR_MR9_Pos)                   /*!< 0x00000200 */\r\n#define EXTI_EMR_MR9              EXTI_EMR_MR9_Msk                             /*!< Event Mask on line 9 */\r\n#define EXTI_EMR_MR10_Pos         (10U)                                        \r\n#define EXTI_EMR_MR10_Msk         (0x1U << EXTI_EMR_MR10_Pos)                  /*!< 0x00000400 */\r\n#define EXTI_EMR_MR10             EXTI_EMR_MR10_Msk                            /*!< Event Mask on line 10 */\r\n#define EXTI_EMR_MR11_Pos         (11U)                                        \r\n#define EXTI_EMR_MR11_Msk         (0x1U << EXTI_EMR_MR11_Pos)                  /*!< 0x00000800 */\r\n#define EXTI_EMR_MR11             EXTI_EMR_MR11_Msk                            /*!< Event Mask on line 11 */\r\n#define EXTI_EMR_MR12_Pos         (12U)                                        \r\n#define EXTI_EMR_MR12_Msk         (0x1U << EXTI_EMR_MR12_Pos)                  /*!< 0x00001000 */\r\n#define EXTI_EMR_MR12             EXTI_EMR_MR12_Msk                            /*!< Event Mask on line 12 */\r\n#define EXTI_EMR_MR13_Pos         (13U)                                        \r\n#define EXTI_EMR_MR13_Msk         (0x1U << EXTI_EMR_MR13_Pos)                  /*!< 0x00002000 */\r\n#define EXTI_EMR_MR13             EXTI_EMR_MR13_Msk                            /*!< Event Mask on line 13 */\r\n#define EXTI_EMR_MR14_Pos         (14U)                                        \r\n#define EXTI_EMR_MR14_Msk         (0x1U << EXTI_EMR_MR14_Pos)                  /*!< 0x00004000 */\r\n#define EXTI_EMR_MR14             EXTI_EMR_MR14_Msk                            /*!< Event Mask on line 14 */\r\n#define EXTI_EMR_MR15_Pos         (15U)                                        \r\n#define EXTI_EMR_MR15_Msk         (0x1U << EXTI_EMR_MR15_Pos)                  /*!< 0x00008000 */\r\n#define EXTI_EMR_MR15             EXTI_EMR_MR15_Msk                            /*!< Event Mask on line 15 */\r\n#define EXTI_EMR_MR16_Pos         (16U)                                        \r\n#define EXTI_EMR_MR16_Msk         (0x1U << EXTI_EMR_MR16_Pos)                  /*!< 0x00010000 */\r\n#define EXTI_EMR_MR16             EXTI_EMR_MR16_Msk                            /*!< Event Mask on line 16 */\r\n#define EXTI_EMR_MR17_Pos         (17U)                                        \r\n#define EXTI_EMR_MR17_Msk         (0x1U << EXTI_EMR_MR17_Pos)                  /*!< 0x00020000 */\r\n#define EXTI_EMR_MR17             EXTI_EMR_MR17_Msk                            /*!< Event Mask on line 17 */\r\n#define EXTI_EMR_MR18_Pos         (18U)                                        \r\n#define EXTI_EMR_MR18_Msk         (0x1U << EXTI_EMR_MR18_Pos)                  /*!< 0x00040000 */\r\n#define EXTI_EMR_MR18             EXTI_EMR_MR18_Msk                            /*!< Event Mask on line 18 */\r\n#define EXTI_EMR_MR19_Pos         (19U)                                        \r\n#define EXTI_EMR_MR19_Msk         (0x1U << EXTI_EMR_MR19_Pos)                  /*!< 0x00080000 */\r\n#define EXTI_EMR_MR19             EXTI_EMR_MR19_Msk                            /*!< Event Mask on line 19 */\r\n#define EXTI_EMR_MR20_Pos         (20U)                                        \r\n#define EXTI_EMR_MR20_Msk         (0x1U << EXTI_EMR_MR20_Pos)                  /*!< 0x00100000 */\r\n#define EXTI_EMR_MR20             EXTI_EMR_MR20_Msk                            /*!< Event Mask on line 20 */\r\n#define EXTI_EMR_MR21_Pos         (21U)                                        \r\n#define EXTI_EMR_MR21_Msk         (0x1U << EXTI_EMR_MR21_Pos)                  /*!< 0x00200000 */\r\n#define EXTI_EMR_MR21             EXTI_EMR_MR21_Msk                            /*!< Event Mask on line 21 */\r\n#define EXTI_EMR_MR22_Pos         (22U)                                        \r\n#define EXTI_EMR_MR22_Msk         (0x1U << EXTI_EMR_MR22_Pos)                  /*!< 0x00400000 */\r\n#define EXTI_EMR_MR22             EXTI_EMR_MR22_Msk                            /*!< Event Mask on line 22 */\r\n#define EXTI_EMR_MR23_Pos         (23U)                                        \r\n#define EXTI_EMR_MR23_Msk         (0x1U << EXTI_EMR_MR23_Pos)                  /*!< 0x00800000 */\r\n#define EXTI_EMR_MR23             EXTI_EMR_MR23_Msk                            /*!< Event Mask on line 23 */\r\n\r\n/* Reference Defines */\r\n#define  EXTI_EMR_EM0                        EXTI_EMR_MR0\r\n#define  EXTI_EMR_EM1                        EXTI_EMR_MR1\r\n#define  EXTI_EMR_EM2                        EXTI_EMR_MR2\r\n#define  EXTI_EMR_EM3                        EXTI_EMR_MR3\r\n#define  EXTI_EMR_EM4                        EXTI_EMR_MR4\r\n#define  EXTI_EMR_EM5                        EXTI_EMR_MR5\r\n#define  EXTI_EMR_EM6                        EXTI_EMR_MR6\r\n#define  EXTI_EMR_EM7                        EXTI_EMR_MR7\r\n#define  EXTI_EMR_EM8                        EXTI_EMR_MR8\r\n#define  EXTI_EMR_EM9                        EXTI_EMR_MR9\r\n#define  EXTI_EMR_EM10                       EXTI_EMR_MR10\r\n#define  EXTI_EMR_EM11                       EXTI_EMR_MR11\r\n#define  EXTI_EMR_EM12                       EXTI_EMR_MR12\r\n#define  EXTI_EMR_EM13                       EXTI_EMR_MR13\r\n#define  EXTI_EMR_EM14                       EXTI_EMR_MR14\r\n#define  EXTI_EMR_EM15                       EXTI_EMR_MR15\r\n#define  EXTI_EMR_EM16                       EXTI_EMR_MR16\r\n#define  EXTI_EMR_EM17                       EXTI_EMR_MR17\r\n#define  EXTI_EMR_EM18                       EXTI_EMR_MR18\r\n#define  EXTI_EMR_EM19                       EXTI_EMR_MR19\r\n#define  EXTI_EMR_EM20                       EXTI_EMR_MR20\r\n#define  EXTI_EMR_EM21                       EXTI_EMR_MR21\r\n#define  EXTI_EMR_EM22                       EXTI_EMR_MR22\r\n#define  EXTI_EMR_EM23                       EXTI_EMR_MR23\r\n\r\n\r\n/******************  Bit definition for EXTI_RTSR register  *******************/\r\n#define EXTI_RTSR_TR0_Pos         (0U)                                         \r\n#define EXTI_RTSR_TR0_Msk         (0x1U << EXTI_RTSR_TR0_Pos)                  /*!< 0x00000001 */\r\n#define EXTI_RTSR_TR0             EXTI_RTSR_TR0_Msk                            /*!< Rising trigger event configuration bit of line 0 */\r\n#define EXTI_RTSR_TR1_Pos         (1U)                                         \r\n#define EXTI_RTSR_TR1_Msk         (0x1U << EXTI_RTSR_TR1_Pos)                  /*!< 0x00000002 */\r\n#define EXTI_RTSR_TR1             EXTI_RTSR_TR1_Msk                            /*!< Rising trigger event configuration bit of line 1 */\r\n#define EXTI_RTSR_TR2_Pos         (2U)                                         \r\n#define EXTI_RTSR_TR2_Msk         (0x1U << EXTI_RTSR_TR2_Pos)                  /*!< 0x00000004 */\r\n#define EXTI_RTSR_TR2             EXTI_RTSR_TR2_Msk                            /*!< Rising trigger event configuration bit of line 2 */\r\n#define EXTI_RTSR_TR3_Pos         (3U)                                         \r\n#define EXTI_RTSR_TR3_Msk         (0x1U << EXTI_RTSR_TR3_Pos)                  /*!< 0x00000008 */\r\n#define EXTI_RTSR_TR3             EXTI_RTSR_TR3_Msk                            /*!< Rising trigger event configuration bit of line 3 */\r\n#define EXTI_RTSR_TR4_Pos         (4U)                                         \r\n#define EXTI_RTSR_TR4_Msk         (0x1U << EXTI_RTSR_TR4_Pos)                  /*!< 0x00000010 */\r\n#define EXTI_RTSR_TR4             EXTI_RTSR_TR4_Msk                            /*!< Rising trigger event configuration bit of line 4 */\r\n#define EXTI_RTSR_TR5_Pos         (5U)                                         \r\n#define EXTI_RTSR_TR5_Msk         (0x1U << EXTI_RTSR_TR5_Pos)                  /*!< 0x00000020 */\r\n#define EXTI_RTSR_TR5             EXTI_RTSR_TR5_Msk                            /*!< Rising trigger event configuration bit of line 5 */\r\n#define EXTI_RTSR_TR6_Pos         (6U)                                         \r\n#define EXTI_RTSR_TR6_Msk         (0x1U << EXTI_RTSR_TR6_Pos)                  /*!< 0x00000040 */\r\n#define EXTI_RTSR_TR6             EXTI_RTSR_TR6_Msk                            /*!< Rising trigger event configuration bit of line 6 */\r\n#define EXTI_RTSR_TR7_Pos         (7U)                                         \r\n#define EXTI_RTSR_TR7_Msk         (0x1U << EXTI_RTSR_TR7_Pos)                  /*!< 0x00000080 */\r\n#define EXTI_RTSR_TR7             EXTI_RTSR_TR7_Msk                            /*!< Rising trigger event configuration bit of line 7 */\r\n#define EXTI_RTSR_TR8_Pos         (8U)                                         \r\n#define EXTI_RTSR_TR8_Msk         (0x1U << EXTI_RTSR_TR8_Pos)                  /*!< 0x00000100 */\r\n#define EXTI_RTSR_TR8             EXTI_RTSR_TR8_Msk                            /*!< Rising trigger event configuration bit of line 8 */\r\n#define EXTI_RTSR_TR9_Pos         (9U)                                         \r\n#define EXTI_RTSR_TR9_Msk         (0x1U << EXTI_RTSR_TR9_Pos)                  /*!< 0x00000200 */\r\n#define EXTI_RTSR_TR9             EXTI_RTSR_TR9_Msk                            /*!< Rising trigger event configuration bit of line 9 */\r\n#define EXTI_RTSR_TR10_Pos        (10U)                                        \r\n#define EXTI_RTSR_TR10_Msk        (0x1U << EXTI_RTSR_TR10_Pos)                 /*!< 0x00000400 */\r\n#define EXTI_RTSR_TR10            EXTI_RTSR_TR10_Msk                           /*!< Rising trigger event configuration bit of line 10 */\r\n#define EXTI_RTSR_TR11_Pos        (11U)                                        \r\n#define EXTI_RTSR_TR11_Msk        (0x1U << EXTI_RTSR_TR11_Pos)                 /*!< 0x00000800 */\r\n#define EXTI_RTSR_TR11            EXTI_RTSR_TR11_Msk                           /*!< Rising trigger event configuration bit of line 11 */\r\n#define EXTI_RTSR_TR12_Pos        (12U)                                        \r\n#define EXTI_RTSR_TR12_Msk        (0x1U << EXTI_RTSR_TR12_Pos)                 /*!< 0x00001000 */\r\n#define EXTI_RTSR_TR12            EXTI_RTSR_TR12_Msk                           /*!< Rising trigger event configuration bit of line 12 */\r\n#define EXTI_RTSR_TR13_Pos        (13U)                                        \r\n#define EXTI_RTSR_TR13_Msk        (0x1U << EXTI_RTSR_TR13_Pos)                 /*!< 0x00002000 */\r\n#define EXTI_RTSR_TR13            EXTI_RTSR_TR13_Msk                           /*!< Rising trigger event configuration bit of line 13 */\r\n#define EXTI_RTSR_TR14_Pos        (14U)                                        \r\n#define EXTI_RTSR_TR14_Msk        (0x1U << EXTI_RTSR_TR14_Pos)                 /*!< 0x00004000 */\r\n#define EXTI_RTSR_TR14            EXTI_RTSR_TR14_Msk                           /*!< Rising trigger event configuration bit of line 14 */\r\n#define EXTI_RTSR_TR15_Pos        (15U)                                        \r\n#define EXTI_RTSR_TR15_Msk        (0x1U << EXTI_RTSR_TR15_Pos)                 /*!< 0x00008000 */\r\n#define EXTI_RTSR_TR15            EXTI_RTSR_TR15_Msk                           /*!< Rising trigger event configuration bit of line 15 */\r\n#define EXTI_RTSR_TR16_Pos        (16U)                                        \r\n#define EXTI_RTSR_TR16_Msk        (0x1U << EXTI_RTSR_TR16_Pos)                 /*!< 0x00010000 */\r\n#define EXTI_RTSR_TR16            EXTI_RTSR_TR16_Msk                           /*!< Rising trigger event configuration bit of line 16 */\r\n#define EXTI_RTSR_TR17_Pos        (17U)                                        \r\n#define EXTI_RTSR_TR17_Msk        (0x1U << EXTI_RTSR_TR17_Pos)                 /*!< 0x00020000 */\r\n#define EXTI_RTSR_TR17            EXTI_RTSR_TR17_Msk                           /*!< Rising trigger event configuration bit of line 17 */\r\n#define EXTI_RTSR_TR18_Pos        (18U)                                        \r\n#define EXTI_RTSR_TR18_Msk        (0x1U << EXTI_RTSR_TR18_Pos)                 /*!< 0x00040000 */\r\n#define EXTI_RTSR_TR18            EXTI_RTSR_TR18_Msk                           /*!< Rising trigger event configuration bit of line 18 */\r\n#define EXTI_RTSR_TR19_Pos        (19U)                                        \r\n#define EXTI_RTSR_TR19_Msk        (0x1U << EXTI_RTSR_TR19_Pos)                 /*!< 0x00080000 */\r\n#define EXTI_RTSR_TR19            EXTI_RTSR_TR19_Msk                           /*!< Rising trigger event configuration bit of line 19 */\r\n#define EXTI_RTSR_TR20_Pos        (20U)                                        \r\n#define EXTI_RTSR_TR20_Msk        (0x1U << EXTI_RTSR_TR20_Pos)                 /*!< 0x00100000 */\r\n#define EXTI_RTSR_TR20            EXTI_RTSR_TR20_Msk                           /*!< Rising trigger event configuration bit of line 20 */\r\n#define EXTI_RTSR_TR21_Pos        (21U)                                        \r\n#define EXTI_RTSR_TR21_Msk        (0x1U << EXTI_RTSR_TR21_Pos)                 /*!< 0x00200000 */\r\n#define EXTI_RTSR_TR21            EXTI_RTSR_TR21_Msk                           /*!< Rising trigger event configuration bit of line 21 */\r\n#define EXTI_RTSR_TR22_Pos        (22U)                                        \r\n#define EXTI_RTSR_TR22_Msk        (0x1U << EXTI_RTSR_TR22_Pos)                 /*!< 0x00400000 */\r\n#define EXTI_RTSR_TR22            EXTI_RTSR_TR22_Msk                           /*!< Rising trigger event configuration bit of line 22 */\r\n#define EXTI_RTSR_TR23_Pos        (23U)                                        \r\n#define EXTI_RTSR_TR23_Msk        (0x1U << EXTI_RTSR_TR23_Pos)                 /*!< 0x00800000 */\r\n#define EXTI_RTSR_TR23            EXTI_RTSR_TR23_Msk                           /*!< Rising trigger event configuration bit of line 23 */\r\n\r\n/******************  Bit definition for EXTI_FTSR register  *******************/\r\n#define EXTI_FTSR_TR0_Pos         (0U)                                         \r\n#define EXTI_FTSR_TR0_Msk         (0x1U << EXTI_FTSR_TR0_Pos)                  /*!< 0x00000001 */\r\n#define EXTI_FTSR_TR0             EXTI_FTSR_TR0_Msk                            /*!< Falling trigger event configuration bit of line 0 */\r\n#define EXTI_FTSR_TR1_Pos         (1U)                                         \r\n#define EXTI_FTSR_TR1_Msk         (0x1U << EXTI_FTSR_TR1_Pos)                  /*!< 0x00000002 */\r\n#define EXTI_FTSR_TR1             EXTI_FTSR_TR1_Msk                            /*!< Falling trigger event configuration bit of line 1 */\r\n#define EXTI_FTSR_TR2_Pos         (2U)                                         \r\n#define EXTI_FTSR_TR2_Msk         (0x1U << EXTI_FTSR_TR2_Pos)                  /*!< 0x00000004 */\r\n#define EXTI_FTSR_TR2             EXTI_FTSR_TR2_Msk                            /*!< Falling trigger event configuration bit of line 2 */\r\n#define EXTI_FTSR_TR3_Pos         (3U)                                         \r\n#define EXTI_FTSR_TR3_Msk         (0x1U << EXTI_FTSR_TR3_Pos)                  /*!< 0x00000008 */\r\n#define EXTI_FTSR_TR3             EXTI_FTSR_TR3_Msk                            /*!< Falling trigger event configuration bit of line 3 */\r\n#define EXTI_FTSR_TR4_Pos         (4U)                                         \r\n#define EXTI_FTSR_TR4_Msk         (0x1U << EXTI_FTSR_TR4_Pos)                  /*!< 0x00000010 */\r\n#define EXTI_FTSR_TR4             EXTI_FTSR_TR4_Msk                            /*!< Falling trigger event configuration bit of line 4 */\r\n#define EXTI_FTSR_TR5_Pos         (5U)                                         \r\n#define EXTI_FTSR_TR5_Msk         (0x1U << EXTI_FTSR_TR5_Pos)                  /*!< 0x00000020 */\r\n#define EXTI_FTSR_TR5             EXTI_FTSR_TR5_Msk                            /*!< Falling trigger event configuration bit of line 5 */\r\n#define EXTI_FTSR_TR6_Pos         (6U)                                         \r\n#define EXTI_FTSR_TR6_Msk         (0x1U << EXTI_FTSR_TR6_Pos)                  /*!< 0x00000040 */\r\n#define EXTI_FTSR_TR6             EXTI_FTSR_TR6_Msk                            /*!< Falling trigger event configuration bit of line 6 */\r\n#define EXTI_FTSR_TR7_Pos         (7U)                                         \r\n#define EXTI_FTSR_TR7_Msk         (0x1U << EXTI_FTSR_TR7_Pos)                  /*!< 0x00000080 */\r\n#define EXTI_FTSR_TR7             EXTI_FTSR_TR7_Msk                            /*!< Falling trigger event configuration bit of line 7 */\r\n#define EXTI_FTSR_TR8_Pos         (8U)                                         \r\n#define EXTI_FTSR_TR8_Msk         (0x1U << EXTI_FTSR_TR8_Pos)                  /*!< 0x00000100 */\r\n#define EXTI_FTSR_TR8             EXTI_FTSR_TR8_Msk                            /*!< Falling trigger event configuration bit of line 8 */\r\n#define EXTI_FTSR_TR9_Pos         (9U)                                         \r\n#define EXTI_FTSR_TR9_Msk         (0x1U << EXTI_FTSR_TR9_Pos)                  /*!< 0x00000200 */\r\n#define EXTI_FTSR_TR9             EXTI_FTSR_TR9_Msk                            /*!< Falling trigger event configuration bit of line 9 */\r\n#define EXTI_FTSR_TR10_Pos        (10U)                                        \r\n#define EXTI_FTSR_TR10_Msk        (0x1U << EXTI_FTSR_TR10_Pos)                 /*!< 0x00000400 */\r\n#define EXTI_FTSR_TR10            EXTI_FTSR_TR10_Msk                           /*!< Falling trigger event configuration bit of line 10 */\r\n#define EXTI_FTSR_TR11_Pos        (11U)                                        \r\n#define EXTI_FTSR_TR11_Msk        (0x1U << EXTI_FTSR_TR11_Pos)                 /*!< 0x00000800 */\r\n#define EXTI_FTSR_TR11            EXTI_FTSR_TR11_Msk                           /*!< Falling trigger event configuration bit of line 11 */\r\n#define EXTI_FTSR_TR12_Pos        (12U)                                        \r\n#define EXTI_FTSR_TR12_Msk        (0x1U << EXTI_FTSR_TR12_Pos)                 /*!< 0x00001000 */\r\n#define EXTI_FTSR_TR12            EXTI_FTSR_TR12_Msk                           /*!< Falling trigger event configuration bit of line 12 */\r\n#define EXTI_FTSR_TR13_Pos        (13U)                                        \r\n#define EXTI_FTSR_TR13_Msk        (0x1U << EXTI_FTSR_TR13_Pos)                 /*!< 0x00002000 */\r\n#define EXTI_FTSR_TR13            EXTI_FTSR_TR13_Msk                           /*!< Falling trigger event configuration bit of line 13 */\r\n#define EXTI_FTSR_TR14_Pos        (14U)                                        \r\n#define EXTI_FTSR_TR14_Msk        (0x1U << EXTI_FTSR_TR14_Pos)                 /*!< 0x00004000 */\r\n#define EXTI_FTSR_TR14            EXTI_FTSR_TR14_Msk                           /*!< Falling trigger event configuration bit of line 14 */\r\n#define EXTI_FTSR_TR15_Pos        (15U)                                        \r\n#define EXTI_FTSR_TR15_Msk        (0x1U << EXTI_FTSR_TR15_Pos)                 /*!< 0x00008000 */\r\n#define EXTI_FTSR_TR15            EXTI_FTSR_TR15_Msk                           /*!< Falling trigger event configuration bit of line 15 */\r\n#define EXTI_FTSR_TR16_Pos        (16U)                                        \r\n#define EXTI_FTSR_TR16_Msk        (0x1U << EXTI_FTSR_TR16_Pos)                 /*!< 0x00010000 */\r\n#define EXTI_FTSR_TR16            EXTI_FTSR_TR16_Msk                           /*!< Falling trigger event configuration bit of line 16 */\r\n#define EXTI_FTSR_TR17_Pos        (17U)                                        \r\n#define EXTI_FTSR_TR17_Msk        (0x1U << EXTI_FTSR_TR17_Pos)                 /*!< 0x00020000 */\r\n#define EXTI_FTSR_TR17            EXTI_FTSR_TR17_Msk                           /*!< Falling trigger event configuration bit of line 17 */\r\n#define EXTI_FTSR_TR18_Pos        (18U)                                        \r\n#define EXTI_FTSR_TR18_Msk        (0x1U << EXTI_FTSR_TR18_Pos)                 /*!< 0x00040000 */\r\n#define EXTI_FTSR_TR18            EXTI_FTSR_TR18_Msk                           /*!< Falling trigger event configuration bit of line 18 */\r\n#define EXTI_FTSR_TR19_Pos        (19U)                                        \r\n#define EXTI_FTSR_TR19_Msk        (0x1U << EXTI_FTSR_TR19_Pos)                 /*!< 0x00080000 */\r\n#define EXTI_FTSR_TR19            EXTI_FTSR_TR19_Msk                           /*!< Falling trigger event configuration bit of line 19 */\r\n#define EXTI_FTSR_TR20_Pos        (20U)                                        \r\n#define EXTI_FTSR_TR20_Msk        (0x1U << EXTI_FTSR_TR20_Pos)                 /*!< 0x00100000 */\r\n#define EXTI_FTSR_TR20            EXTI_FTSR_TR20_Msk                           /*!< Falling trigger event configuration bit of line 20 */\r\n#define EXTI_FTSR_TR21_Pos        (21U)                                        \r\n#define EXTI_FTSR_TR21_Msk        (0x1U << EXTI_FTSR_TR21_Pos)                 /*!< 0x00200000 */\r\n#define EXTI_FTSR_TR21            EXTI_FTSR_TR21_Msk                           /*!< Falling trigger event configuration bit of line 21 */\r\n#define EXTI_FTSR_TR22_Pos        (22U)                                        \r\n#define EXTI_FTSR_TR22_Msk        (0x1U << EXTI_FTSR_TR22_Pos)                 /*!< 0x00400000 */\r\n#define EXTI_FTSR_TR22            EXTI_FTSR_TR22_Msk                           /*!< Falling trigger event configuration bit of line 22 */\r\n#define EXTI_FTSR_TR23_Pos        (23U)                                        \r\n#define EXTI_FTSR_TR23_Msk        (0x1U << EXTI_FTSR_TR23_Pos)                 /*!< 0x00800000 */\r\n#define EXTI_FTSR_TR23            EXTI_FTSR_TR23_Msk                           /*!< Falling trigger event configuration bit of line 23 */\r\n\r\n/******************  Bit definition for EXTI_SWIER register  ******************/\r\n#define EXTI_SWIER_SWIER0_Pos     (0U)                                         \r\n#define EXTI_SWIER_SWIER0_Msk     (0x1U << EXTI_SWIER_SWIER0_Pos)              /*!< 0x00000001 */\r\n#define EXTI_SWIER_SWIER0         EXTI_SWIER_SWIER0_Msk                        /*!< Software Interrupt on line 0 */\r\n#define EXTI_SWIER_SWIER1_Pos     (1U)                                         \r\n#define EXTI_SWIER_SWIER1_Msk     (0x1U << EXTI_SWIER_SWIER1_Pos)              /*!< 0x00000002 */\r\n#define EXTI_SWIER_SWIER1         EXTI_SWIER_SWIER1_Msk                        /*!< Software Interrupt on line 1 */\r\n#define EXTI_SWIER_SWIER2_Pos     (2U)                                         \r\n#define EXTI_SWIER_SWIER2_Msk     (0x1U << EXTI_SWIER_SWIER2_Pos)              /*!< 0x00000004 */\r\n#define EXTI_SWIER_SWIER2         EXTI_SWIER_SWIER2_Msk                        /*!< Software Interrupt on line 2 */\r\n#define EXTI_SWIER_SWIER3_Pos     (3U)                                         \r\n#define EXTI_SWIER_SWIER3_Msk     (0x1U << EXTI_SWIER_SWIER3_Pos)              /*!< 0x00000008 */\r\n#define EXTI_SWIER_SWIER3         EXTI_SWIER_SWIER3_Msk                        /*!< Software Interrupt on line 3 */\r\n#define EXTI_SWIER_SWIER4_Pos     (4U)                                         \r\n#define EXTI_SWIER_SWIER4_Msk     (0x1U << EXTI_SWIER_SWIER4_Pos)              /*!< 0x00000010 */\r\n#define EXTI_SWIER_SWIER4         EXTI_SWIER_SWIER4_Msk                        /*!< Software Interrupt on line 4 */\r\n#define EXTI_SWIER_SWIER5_Pos     (5U)                                         \r\n#define EXTI_SWIER_SWIER5_Msk     (0x1U << EXTI_SWIER_SWIER5_Pos)              /*!< 0x00000020 */\r\n#define EXTI_SWIER_SWIER5         EXTI_SWIER_SWIER5_Msk                        /*!< Software Interrupt on line 5 */\r\n#define EXTI_SWIER_SWIER6_Pos     (6U)                                         \r\n#define EXTI_SWIER_SWIER6_Msk     (0x1U << EXTI_SWIER_SWIER6_Pos)              /*!< 0x00000040 */\r\n#define EXTI_SWIER_SWIER6         EXTI_SWIER_SWIER6_Msk                        /*!< Software Interrupt on line 6 */\r\n#define EXTI_SWIER_SWIER7_Pos     (7U)                                         \r\n#define EXTI_SWIER_SWIER7_Msk     (0x1U << EXTI_SWIER_SWIER7_Pos)              /*!< 0x00000080 */\r\n#define EXTI_SWIER_SWIER7         EXTI_SWIER_SWIER7_Msk                        /*!< Software Interrupt on line 7 */\r\n#define EXTI_SWIER_SWIER8_Pos     (8U)                                         \r\n#define EXTI_SWIER_SWIER8_Msk     (0x1U << EXTI_SWIER_SWIER8_Pos)              /*!< 0x00000100 */\r\n#define EXTI_SWIER_SWIER8         EXTI_SWIER_SWIER8_Msk                        /*!< Software Interrupt on line 8 */\r\n#define EXTI_SWIER_SWIER9_Pos     (9U)                                         \r\n#define EXTI_SWIER_SWIER9_Msk     (0x1U << EXTI_SWIER_SWIER9_Pos)              /*!< 0x00000200 */\r\n#define EXTI_SWIER_SWIER9         EXTI_SWIER_SWIER9_Msk                        /*!< Software Interrupt on line 9 */\r\n#define EXTI_SWIER_SWIER10_Pos    (10U)                                        \r\n#define EXTI_SWIER_SWIER10_Msk    (0x1U << EXTI_SWIER_SWIER10_Pos)             /*!< 0x00000400 */\r\n#define EXTI_SWIER_SWIER10        EXTI_SWIER_SWIER10_Msk                       /*!< Software Interrupt on line 10 */\r\n#define EXTI_SWIER_SWIER11_Pos    (11U)                                        \r\n#define EXTI_SWIER_SWIER11_Msk    (0x1U << EXTI_SWIER_SWIER11_Pos)             /*!< 0x00000800 */\r\n#define EXTI_SWIER_SWIER11        EXTI_SWIER_SWIER11_Msk                       /*!< Software Interrupt on line 11 */\r\n#define EXTI_SWIER_SWIER12_Pos    (12U)                                        \r\n#define EXTI_SWIER_SWIER12_Msk    (0x1U << EXTI_SWIER_SWIER12_Pos)             /*!< 0x00001000 */\r\n#define EXTI_SWIER_SWIER12        EXTI_SWIER_SWIER12_Msk                       /*!< Software Interrupt on line 12 */\r\n#define EXTI_SWIER_SWIER13_Pos    (13U)                                        \r\n#define EXTI_SWIER_SWIER13_Msk    (0x1U << EXTI_SWIER_SWIER13_Pos)             /*!< 0x00002000 */\r\n#define EXTI_SWIER_SWIER13        EXTI_SWIER_SWIER13_Msk                       /*!< Software Interrupt on line 13 */\r\n#define EXTI_SWIER_SWIER14_Pos    (14U)                                        \r\n#define EXTI_SWIER_SWIER14_Msk    (0x1U << EXTI_SWIER_SWIER14_Pos)             /*!< 0x00004000 */\r\n#define EXTI_SWIER_SWIER14        EXTI_SWIER_SWIER14_Msk                       /*!< Software Interrupt on line 14 */\r\n#define EXTI_SWIER_SWIER15_Pos    (15U)                                        \r\n#define EXTI_SWIER_SWIER15_Msk    (0x1U << EXTI_SWIER_SWIER15_Pos)             /*!< 0x00008000 */\r\n#define EXTI_SWIER_SWIER15        EXTI_SWIER_SWIER15_Msk                       /*!< Software Interrupt on line 15 */\r\n#define EXTI_SWIER_SWIER16_Pos    (16U)                                        \r\n#define EXTI_SWIER_SWIER16_Msk    (0x1U << EXTI_SWIER_SWIER16_Pos)             /*!< 0x00010000 */\r\n#define EXTI_SWIER_SWIER16        EXTI_SWIER_SWIER16_Msk                       /*!< Software Interrupt on line 16 */\r\n#define EXTI_SWIER_SWIER17_Pos    (17U)                                        \r\n#define EXTI_SWIER_SWIER17_Msk    (0x1U << EXTI_SWIER_SWIER17_Pos)             /*!< 0x00020000 */\r\n#define EXTI_SWIER_SWIER17        EXTI_SWIER_SWIER17_Msk                       /*!< Software Interrupt on line 17 */\r\n#define EXTI_SWIER_SWIER18_Pos    (18U)                                        \r\n#define EXTI_SWIER_SWIER18_Msk    (0x1U << EXTI_SWIER_SWIER18_Pos)             /*!< 0x00040000 */\r\n#define EXTI_SWIER_SWIER18        EXTI_SWIER_SWIER18_Msk                       /*!< Software Interrupt on line 18 */\r\n#define EXTI_SWIER_SWIER19_Pos    (19U)                                        \r\n#define EXTI_SWIER_SWIER19_Msk    (0x1U << EXTI_SWIER_SWIER19_Pos)             /*!< 0x00080000 */\r\n#define EXTI_SWIER_SWIER19        EXTI_SWIER_SWIER19_Msk                       /*!< Software Interrupt on line 19 */\r\n#define EXTI_SWIER_SWIER20_Pos    (20U)                                        \r\n#define EXTI_SWIER_SWIER20_Msk    (0x1U << EXTI_SWIER_SWIER20_Pos)             /*!< 0x00100000 */\r\n#define EXTI_SWIER_SWIER20        EXTI_SWIER_SWIER20_Msk                       /*!< Software Interrupt on line 20 */\r\n#define EXTI_SWIER_SWIER21_Pos    (21U)                                        \r\n#define EXTI_SWIER_SWIER21_Msk    (0x1U << EXTI_SWIER_SWIER21_Pos)             /*!< 0x00200000 */\r\n#define EXTI_SWIER_SWIER21        EXTI_SWIER_SWIER21_Msk                       /*!< Software Interrupt on line 21 */\r\n#define EXTI_SWIER_SWIER22_Pos    (22U)                                        \r\n#define EXTI_SWIER_SWIER22_Msk    (0x1U << EXTI_SWIER_SWIER22_Pos)             /*!< 0x00400000 */\r\n#define EXTI_SWIER_SWIER22        EXTI_SWIER_SWIER22_Msk                       /*!< Software Interrupt on line 22 */\r\n#define EXTI_SWIER_SWIER23_Pos    (23U)                                        \r\n#define EXTI_SWIER_SWIER23_Msk    (0x1U << EXTI_SWIER_SWIER23_Pos)             /*!< 0x00800000 */\r\n#define EXTI_SWIER_SWIER23        EXTI_SWIER_SWIER23_Msk                       /*!< Software Interrupt on line 23 */\r\n\r\n/*******************  Bit definition for EXTI_PR register  ********************/\r\n#define EXTI_PR_PR0_Pos           (0U)                                         \r\n#define EXTI_PR_PR0_Msk           (0x1U << EXTI_PR_PR0_Pos)                    /*!< 0x00000001 */\r\n#define EXTI_PR_PR0               EXTI_PR_PR0_Msk                              /*!< Pending bit for line 0 */\r\n#define EXTI_PR_PR1_Pos           (1U)                                         \r\n#define EXTI_PR_PR1_Msk           (0x1U << EXTI_PR_PR1_Pos)                    /*!< 0x00000002 */\r\n#define EXTI_PR_PR1               EXTI_PR_PR1_Msk                              /*!< Pending bit for line 1 */\r\n#define EXTI_PR_PR2_Pos           (2U)                                         \r\n#define EXTI_PR_PR2_Msk           (0x1U << EXTI_PR_PR2_Pos)                    /*!< 0x00000004 */\r\n#define EXTI_PR_PR2               EXTI_PR_PR2_Msk                              /*!< Pending bit for line 2 */\r\n#define EXTI_PR_PR3_Pos           (3U)                                         \r\n#define EXTI_PR_PR3_Msk           (0x1U << EXTI_PR_PR3_Pos)                    /*!< 0x00000008 */\r\n#define EXTI_PR_PR3               EXTI_PR_PR3_Msk                              /*!< Pending bit for line 3 */\r\n#define EXTI_PR_PR4_Pos           (4U)                                         \r\n#define EXTI_PR_PR4_Msk           (0x1U << EXTI_PR_PR4_Pos)                    /*!< 0x00000010 */\r\n#define EXTI_PR_PR4               EXTI_PR_PR4_Msk                              /*!< Pending bit for line 4 */\r\n#define EXTI_PR_PR5_Pos           (5U)                                         \r\n#define EXTI_PR_PR5_Msk           (0x1U << EXTI_PR_PR5_Pos)                    /*!< 0x00000020 */\r\n#define EXTI_PR_PR5               EXTI_PR_PR5_Msk                              /*!< Pending bit for line 5 */\r\n#define EXTI_PR_PR6_Pos           (6U)                                         \r\n#define EXTI_PR_PR6_Msk           (0x1U << EXTI_PR_PR6_Pos)                    /*!< 0x00000040 */\r\n#define EXTI_PR_PR6               EXTI_PR_PR6_Msk                              /*!< Pending bit for line 6 */\r\n#define EXTI_PR_PR7_Pos           (7U)                                         \r\n#define EXTI_PR_PR7_Msk           (0x1U << EXTI_PR_PR7_Pos)                    /*!< 0x00000080 */\r\n#define EXTI_PR_PR7               EXTI_PR_PR7_Msk                              /*!< Pending bit for line 7 */\r\n#define EXTI_PR_PR8_Pos           (8U)                                         \r\n#define EXTI_PR_PR8_Msk           (0x1U << EXTI_PR_PR8_Pos)                    /*!< 0x00000100 */\r\n#define EXTI_PR_PR8               EXTI_PR_PR8_Msk                              /*!< Pending bit for line 8 */\r\n#define EXTI_PR_PR9_Pos           (9U)                                         \r\n#define EXTI_PR_PR9_Msk           (0x1U << EXTI_PR_PR9_Pos)                    /*!< 0x00000200 */\r\n#define EXTI_PR_PR9               EXTI_PR_PR9_Msk                              /*!< Pending bit for line 9 */\r\n#define EXTI_PR_PR10_Pos          (10U)                                        \r\n#define EXTI_PR_PR10_Msk          (0x1U << EXTI_PR_PR10_Pos)                   /*!< 0x00000400 */\r\n#define EXTI_PR_PR10              EXTI_PR_PR10_Msk                             /*!< Pending bit for line 10 */\r\n#define EXTI_PR_PR11_Pos          (11U)                                        \r\n#define EXTI_PR_PR11_Msk          (0x1U << EXTI_PR_PR11_Pos)                   /*!< 0x00000800 */\r\n#define EXTI_PR_PR11              EXTI_PR_PR11_Msk                             /*!< Pending bit for line 11 */\r\n#define EXTI_PR_PR12_Pos          (12U)                                        \r\n#define EXTI_PR_PR12_Msk          (0x1U << EXTI_PR_PR12_Pos)                   /*!< 0x00001000 */\r\n#define EXTI_PR_PR12              EXTI_PR_PR12_Msk                             /*!< Pending bit for line 12 */\r\n#define EXTI_PR_PR13_Pos          (13U)                                        \r\n#define EXTI_PR_PR13_Msk          (0x1U << EXTI_PR_PR13_Pos)                   /*!< 0x00002000 */\r\n#define EXTI_PR_PR13              EXTI_PR_PR13_Msk                             /*!< Pending bit for line 13 */\r\n#define EXTI_PR_PR14_Pos          (14U)                                        \r\n#define EXTI_PR_PR14_Msk          (0x1U << EXTI_PR_PR14_Pos)                   /*!< 0x00004000 */\r\n#define EXTI_PR_PR14              EXTI_PR_PR14_Msk                             /*!< Pending bit for line 14 */\r\n#define EXTI_PR_PR15_Pos          (15U)                                        \r\n#define EXTI_PR_PR15_Msk          (0x1U << EXTI_PR_PR15_Pos)                   /*!< 0x00008000 */\r\n#define EXTI_PR_PR15              EXTI_PR_PR15_Msk                             /*!< Pending bit for line 15 */\r\n#define EXTI_PR_PR16_Pos          (16U)                                        \r\n#define EXTI_PR_PR16_Msk          (0x1U << EXTI_PR_PR16_Pos)                   /*!< 0x00010000 */\r\n#define EXTI_PR_PR16              EXTI_PR_PR16_Msk                             /*!< Pending bit for line 16 */\r\n#define EXTI_PR_PR17_Pos          (17U)                                        \r\n#define EXTI_PR_PR17_Msk          (0x1U << EXTI_PR_PR17_Pos)                   /*!< 0x00020000 */\r\n#define EXTI_PR_PR17              EXTI_PR_PR17_Msk                             /*!< Pending bit for line 17 */\r\n#define EXTI_PR_PR18_Pos          (18U)                                        \r\n#define EXTI_PR_PR18_Msk          (0x1U << EXTI_PR_PR18_Pos)                   /*!< 0x00040000 */\r\n#define EXTI_PR_PR18              EXTI_PR_PR18_Msk                             /*!< Pending bit for line 18 */\r\n#define EXTI_PR_PR19_Pos          (19U)                                        \r\n#define EXTI_PR_PR19_Msk          (0x1U << EXTI_PR_PR19_Pos)                   /*!< 0x00080000 */\r\n#define EXTI_PR_PR19              EXTI_PR_PR19_Msk                             /*!< Pending bit for line 19 */\r\n#define EXTI_PR_PR20_Pos          (20U)                                        \r\n#define EXTI_PR_PR20_Msk          (0x1U << EXTI_PR_PR20_Pos)                   /*!< 0x00100000 */\r\n#define EXTI_PR_PR20              EXTI_PR_PR20_Msk                             /*!< Pending bit for line 20 */\r\n#define EXTI_PR_PR21_Pos          (21U)                                        \r\n#define EXTI_PR_PR21_Msk          (0x1U << EXTI_PR_PR21_Pos)                   /*!< 0x00200000 */\r\n#define EXTI_PR_PR21              EXTI_PR_PR21_Msk                             /*!< Pending bit for line 21 */\r\n#define EXTI_PR_PR22_Pos          (22U)                                        \r\n#define EXTI_PR_PR22_Msk          (0x1U << EXTI_PR_PR22_Pos)                   /*!< 0x00400000 */\r\n#define EXTI_PR_PR22              EXTI_PR_PR22_Msk                             /*!< Pending bit for line 22 */\r\n#define EXTI_PR_PR23_Pos          (23U)                                        \r\n#define EXTI_PR_PR23_Msk          (0x1U << EXTI_PR_PR23_Pos)                   /*!< 0x00800000 */\r\n#define EXTI_PR_PR23              EXTI_PR_PR23_Msk                             /*!< Pending bit for line 23 */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                    FLASH                                   */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*\r\n* @brief FLASH Total Sectors Number\r\n*/\r\n#define FLASH_SECTOR_TOTAL  8\r\n\r\n/*******************  Bits definition for FLASH_ACR register  *****************/\r\n#define FLASH_ACR_LATENCY_Pos         (0U)                                     \r\n#define FLASH_ACR_LATENCY_Msk         (0xFU << FLASH_ACR_LATENCY_Pos)          /*!< 0x0000000F */\r\n#define FLASH_ACR_LATENCY             FLASH_ACR_LATENCY_Msk                    \r\n#define FLASH_ACR_LATENCY_0WS         0x00000000U                              \r\n#define FLASH_ACR_LATENCY_1WS         0x00000001U                              \r\n#define FLASH_ACR_LATENCY_2WS         0x00000002U                              \r\n#define FLASH_ACR_LATENCY_3WS         0x00000003U                              \r\n#define FLASH_ACR_LATENCY_4WS         0x00000004U                              \r\n#define FLASH_ACR_LATENCY_5WS         0x00000005U                              \r\n#define FLASH_ACR_LATENCY_6WS         0x00000006U                              \r\n#define FLASH_ACR_LATENCY_7WS         0x00000007U                              \r\n#define FLASH_ACR_LATENCY_8WS         0x00000008U                              \r\n#define FLASH_ACR_LATENCY_9WS         0x00000009U                              \r\n#define FLASH_ACR_LATENCY_10WS        0x0000000AU                              \r\n#define FLASH_ACR_LATENCY_11WS        0x0000000BU                              \r\n#define FLASH_ACR_LATENCY_12WS        0x0000000CU                              \r\n#define FLASH_ACR_LATENCY_13WS        0x0000000DU                              \r\n#define FLASH_ACR_LATENCY_14WS        0x0000000EU                              \r\n#define FLASH_ACR_LATENCY_15WS        0x0000000FU                              \r\n#define FLASH_ACR_PRFTEN_Pos          (8U)                                     \r\n#define FLASH_ACR_PRFTEN_Msk          (0x1U << FLASH_ACR_PRFTEN_Pos)           /*!< 0x00000100 */\r\n#define FLASH_ACR_PRFTEN              FLASH_ACR_PRFTEN_Msk                     \r\n#define FLASH_ACR_ARTEN_Pos           (9U)                                     \r\n#define FLASH_ACR_ARTEN_Msk           (0x1U << FLASH_ACR_ARTEN_Pos)            /*!< 0x00000200 */\r\n#define FLASH_ACR_ARTEN               FLASH_ACR_ARTEN_Msk                      \r\n#define FLASH_ACR_ARTRST_Pos          (11U)                                    \r\n#define FLASH_ACR_ARTRST_Msk          (0x1U << FLASH_ACR_ARTRST_Pos)           /*!< 0x00000800 */\r\n#define FLASH_ACR_ARTRST              FLASH_ACR_ARTRST_Msk                     \r\n\r\n/*******************  Bits definition for FLASH_SR register  ******************/\r\n#define FLASH_SR_EOP_Pos              (0U)                                     \r\n#define FLASH_SR_EOP_Msk              (0x1U << FLASH_SR_EOP_Pos)               /*!< 0x00000001 */\r\n#define FLASH_SR_EOP                  FLASH_SR_EOP_Msk                         \r\n#define FLASH_SR_OPERR_Pos            (1U)                                     \r\n#define FLASH_SR_OPERR_Msk            (0x1U << FLASH_SR_OPERR_Pos)             /*!< 0x00000002 */\r\n#define FLASH_SR_OPERR                FLASH_SR_OPERR_Msk                       \r\n#define FLASH_SR_WRPERR_Pos           (4U)                                     \r\n#define FLASH_SR_WRPERR_Msk           (0x1U << FLASH_SR_WRPERR_Pos)            /*!< 0x00000010 */\r\n#define FLASH_SR_WRPERR               FLASH_SR_WRPERR_Msk                      \r\n#define FLASH_SR_PGAERR_Pos           (5U)                                     \r\n#define FLASH_SR_PGAERR_Msk           (0x1U << FLASH_SR_PGAERR_Pos)            /*!< 0x00000020 */\r\n#define FLASH_SR_PGAERR               FLASH_SR_PGAERR_Msk                      \r\n#define FLASH_SR_PGPERR_Pos           (6U)                                     \r\n#define FLASH_SR_PGPERR_Msk           (0x1U << FLASH_SR_PGPERR_Pos)            /*!< 0x00000040 */\r\n#define FLASH_SR_PGPERR               FLASH_SR_PGPERR_Msk                      \r\n#define FLASH_SR_ERSERR_Pos           (7U)                                     \r\n#define FLASH_SR_ERSERR_Msk           (0x1U << FLASH_SR_ERSERR_Pos)            /*!< 0x00000080 */\r\n#define FLASH_SR_ERSERR               FLASH_SR_ERSERR_Msk                      \r\n#define FLASH_SR_BSY_Pos              (16U)                                    \r\n#define FLASH_SR_BSY_Msk              (0x1U << FLASH_SR_BSY_Pos)               /*!< 0x00010000 */\r\n#define FLASH_SR_BSY                  FLASH_SR_BSY_Msk                         \r\n\r\n/*******************  Bits definition for FLASH_CR register  ******************/\r\n#define FLASH_CR_PG_Pos               (0U)                                     \r\n#define FLASH_CR_PG_Msk               (0x1U << FLASH_CR_PG_Pos)                /*!< 0x00000001 */\r\n#define FLASH_CR_PG                   FLASH_CR_PG_Msk                          \r\n#define FLASH_CR_SER_Pos              (1U)                                     \r\n#define FLASH_CR_SER_Msk              (0x1U << FLASH_CR_SER_Pos)               /*!< 0x00000002 */\r\n#define FLASH_CR_SER                  FLASH_CR_SER_Msk                         \r\n#define FLASH_CR_MER_Pos              (2U)                                     \r\n#define FLASH_CR_MER_Msk              (0x1U << FLASH_CR_MER_Pos)               /*!< 0x00000004 */\r\n#define FLASH_CR_MER                  FLASH_CR_MER_Msk                         \r\n#define FLASH_CR_SNB_Pos              (3U)                                     \r\n#define FLASH_CR_SNB_Msk              (0xFU << FLASH_CR_SNB_Pos)               /*!< 0x00000078 */\r\n#define FLASH_CR_SNB                  FLASH_CR_SNB_Msk                         \r\n#define FLASH_CR_SNB_0                0x00000008U                              \r\n#define FLASH_CR_SNB_1                0x00000010U                              \r\n#define FLASH_CR_SNB_2                0x00000020U                              \r\n#define FLASH_CR_SNB_3                0x00000040U                              \r\n#define FLASH_CR_PSIZE_Pos            (8U)                                     \r\n#define FLASH_CR_PSIZE_Msk            (0x3U << FLASH_CR_PSIZE_Pos)             /*!< 0x00000300 */\r\n#define FLASH_CR_PSIZE                FLASH_CR_PSIZE_Msk                       \r\n#define FLASH_CR_PSIZE_0              (0x1U << FLASH_CR_PSIZE_Pos)             /*!< 0x00000100 */\r\n#define FLASH_CR_PSIZE_1              (0x2U << FLASH_CR_PSIZE_Pos)             /*!< 0x00000200 */\r\n#define FLASH_CR_STRT_Pos             (16U)                                    \r\n#define FLASH_CR_STRT_Msk             (0x1U << FLASH_CR_STRT_Pos)              /*!< 0x00010000 */\r\n#define FLASH_CR_STRT                 FLASH_CR_STRT_Msk                        \r\n#define FLASH_CR_EOPIE_Pos            (24U)                                    \r\n#define FLASH_CR_EOPIE_Msk            (0x1U << FLASH_CR_EOPIE_Pos)             /*!< 0x01000000 */\r\n#define FLASH_CR_EOPIE                FLASH_CR_EOPIE_Msk                       \r\n#define FLASH_CR_ERRIE_Pos            (25U)                                    \r\n#define FLASH_CR_ERRIE_Msk            (0x1U << FLASH_CR_ERRIE_Pos)             /*!< 0x02000000 */\r\n#define FLASH_CR_ERRIE                FLASH_CR_ERRIE_Msk                       \r\n#define FLASH_CR_LOCK_Pos             (31U)                                    \r\n#define FLASH_CR_LOCK_Msk             (0x1U << FLASH_CR_LOCK_Pos)              /*!< 0x80000000 */\r\n#define FLASH_CR_LOCK                 FLASH_CR_LOCK_Msk                        \r\n\r\n/*******************  Bits definition for FLASH_OPTCR register  ***************/\r\n#define FLASH_OPTCR_OPTLOCK_Pos       (0U)                                     \r\n#define FLASH_OPTCR_OPTLOCK_Msk       (0x1U << FLASH_OPTCR_OPTLOCK_Pos)        /*!< 0x00000001 */\r\n#define FLASH_OPTCR_OPTLOCK           FLASH_OPTCR_OPTLOCK_Msk                  \r\n#define FLASH_OPTCR_OPTSTRT_Pos       (1U)                                     \r\n#define FLASH_OPTCR_OPTSTRT_Msk       (0x1U << FLASH_OPTCR_OPTSTRT_Pos)        /*!< 0x00000002 */\r\n#define FLASH_OPTCR_OPTSTRT           FLASH_OPTCR_OPTSTRT_Msk                  \r\n#define FLASH_OPTCR_BOR_LEV_Pos       (2U)                                     \r\n#define FLASH_OPTCR_BOR_LEV_Msk       (0x3U << FLASH_OPTCR_BOR_LEV_Pos)        /*!< 0x0000000C */\r\n#define FLASH_OPTCR_BOR_LEV           FLASH_OPTCR_BOR_LEV_Msk                  \r\n#define FLASH_OPTCR_BOR_LEV_0         (0x1U << FLASH_OPTCR_BOR_LEV_Pos)        /*!< 0x00000004 */\r\n#define FLASH_OPTCR_BOR_LEV_1         (0x2U << FLASH_OPTCR_BOR_LEV_Pos)        /*!< 0x00000008 */\r\n#define FLASH_OPTCR_WWDG_SW_Pos       (4U)                                     \r\n#define FLASH_OPTCR_WWDG_SW_Msk       (0x1U << FLASH_OPTCR_WWDG_SW_Pos)        /*!< 0x00000010 */\r\n#define FLASH_OPTCR_WWDG_SW           FLASH_OPTCR_WWDG_SW_Msk                  \r\n#define FLASH_OPTCR_IWDG_SW_Pos       (5U)                                     \r\n#define FLASH_OPTCR_IWDG_SW_Msk       (0x1U << FLASH_OPTCR_IWDG_SW_Pos)        /*!< 0x00000020 */\r\n#define FLASH_OPTCR_IWDG_SW           FLASH_OPTCR_IWDG_SW_Msk                  \r\n#define FLASH_OPTCR_nRST_STOP_Pos     (6U)                                     \r\n#define FLASH_OPTCR_nRST_STOP_Msk     (0x1U << FLASH_OPTCR_nRST_STOP_Pos)      /*!< 0x00000040 */\r\n#define FLASH_OPTCR_nRST_STOP         FLASH_OPTCR_nRST_STOP_Msk                \r\n#define FLASH_OPTCR_nRST_STDBY_Pos    (7U)                                     \r\n#define FLASH_OPTCR_nRST_STDBY_Msk    (0x1U << FLASH_OPTCR_nRST_STDBY_Pos)     /*!< 0x00000080 */\r\n#define FLASH_OPTCR_nRST_STDBY        FLASH_OPTCR_nRST_STDBY_Msk               \r\n#define FLASH_OPTCR_RDP_Pos           (8U)                                     \r\n#define FLASH_OPTCR_RDP_Msk           (0xFFU << FLASH_OPTCR_RDP_Pos)           /*!< 0x0000FF00 */\r\n#define FLASH_OPTCR_RDP               FLASH_OPTCR_RDP_Msk                      \r\n#define FLASH_OPTCR_RDP_0             (0x01U << FLASH_OPTCR_RDP_Pos)           /*!< 0x00000100 */\r\n#define FLASH_OPTCR_RDP_1             (0x02U << FLASH_OPTCR_RDP_Pos)           /*!< 0x00000200 */\r\n#define FLASH_OPTCR_RDP_2             (0x04U << FLASH_OPTCR_RDP_Pos)           /*!< 0x00000400 */\r\n#define FLASH_OPTCR_RDP_3             (0x08U << FLASH_OPTCR_RDP_Pos)           /*!< 0x00000800 */\r\n#define FLASH_OPTCR_RDP_4             (0x10U << FLASH_OPTCR_RDP_Pos)           /*!< 0x00001000 */\r\n#define FLASH_OPTCR_RDP_5             (0x20U << FLASH_OPTCR_RDP_Pos)           /*!< 0x00002000 */\r\n#define FLASH_OPTCR_RDP_6             (0x40U << FLASH_OPTCR_RDP_Pos)           /*!< 0x00004000 */\r\n#define FLASH_OPTCR_RDP_7             (0x80U << FLASH_OPTCR_RDP_Pos)           /*!< 0x00008000 */\r\n#define FLASH_OPTCR_nWRP_Pos          (16U)                                    \r\n#define FLASH_OPTCR_nWRP_Msk          (0xFFU << FLASH_OPTCR_nWRP_Pos)          /*!< 0x00FF0000 */\r\n#define FLASH_OPTCR_nWRP              FLASH_OPTCR_nWRP_Msk                     \r\n#define FLASH_OPTCR_nWRP_0            0x00010000U                              \r\n#define FLASH_OPTCR_nWRP_1            0x00020000U                              \r\n#define FLASH_OPTCR_nWRP_2            0x00040000U                              \r\n#define FLASH_OPTCR_nWRP_3            0x00080000U                              \r\n#define FLASH_OPTCR_nWRP_4            0x00100000U                              \r\n#define FLASH_OPTCR_nWRP_5            0x00200000U                              \r\n#define FLASH_OPTCR_nWRP_6            0x00400000U                              \r\n#define FLASH_OPTCR_nWRP_7            0x00800000U                              \r\n#define FLASH_OPTCR_IWDG_STDBY_Pos    (30U)                                    \r\n#define FLASH_OPTCR_IWDG_STDBY_Msk    (0x1U << FLASH_OPTCR_IWDG_STDBY_Pos)     /*!< 0x40000000 */\r\n#define FLASH_OPTCR_IWDG_STDBY        FLASH_OPTCR_IWDG_STDBY_Msk               \r\n#define FLASH_OPTCR_IWDG_STOP_Pos     (31U)                                    \r\n#define FLASH_OPTCR_IWDG_STOP_Msk     (0x1U << FLASH_OPTCR_IWDG_STOP_Pos)      /*!< 0x80000000 */\r\n#define FLASH_OPTCR_IWDG_STOP         FLASH_OPTCR_IWDG_STOP_Msk                \r\n\r\n/*******************  Bits definition for FLASH_OPTCR1 register  ***************/\r\n#define FLASH_OPTCR1_BOOT_ADD0_Pos    (0U)                                     \r\n#define FLASH_OPTCR1_BOOT_ADD0_Msk    (0xFFFFU << FLASH_OPTCR1_BOOT_ADD0_Pos)  /*!< 0x0000FFFF */\r\n#define FLASH_OPTCR1_BOOT_ADD0        FLASH_OPTCR1_BOOT_ADD0_Msk               \r\n#define FLASH_OPTCR1_BOOT_ADD1_Pos    (16U)                                    \r\n#define FLASH_OPTCR1_BOOT_ADD1_Msk    (0xFFFFU << FLASH_OPTCR1_BOOT_ADD1_Pos)  /*!< 0xFFFF0000 */\r\n#define FLASH_OPTCR1_BOOT_ADD1        FLASH_OPTCR1_BOOT_ADD1_Msk               \r\n\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                          Flexible Memory Controller                        */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/******************  Bit definition for FMC_BCR1 register  *******************/\r\n#define FMC_BCR1_MBKEN_Pos         (0U)                                        \r\n#define FMC_BCR1_MBKEN_Msk         (0x1U << FMC_BCR1_MBKEN_Pos)                /*!< 0x00000001 */\r\n#define FMC_BCR1_MBKEN             FMC_BCR1_MBKEN_Msk                          /*!<Memory bank enable bit                 */\r\n#define FMC_BCR1_MUXEN_Pos         (1U)                                        \r\n#define FMC_BCR1_MUXEN_Msk         (0x1U << FMC_BCR1_MUXEN_Pos)                /*!< 0x00000002 */\r\n#define FMC_BCR1_MUXEN             FMC_BCR1_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */\r\n#define FMC_BCR1_MTYP_Pos          (2U)                                        \r\n#define FMC_BCR1_MTYP_Msk          (0x3U << FMC_BCR1_MTYP_Pos)                 /*!< 0x0000000C */\r\n#define FMC_BCR1_MTYP              FMC_BCR1_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */\r\n#define FMC_BCR1_MTYP_0            (0x1U << FMC_BCR1_MTYP_Pos)                 /*!< 0x00000004 */\r\n#define FMC_BCR1_MTYP_1            (0x2U << FMC_BCR1_MTYP_Pos)                 /*!< 0x00000008 */\r\n#define FMC_BCR1_MWID_Pos          (4U)                                        \r\n#define FMC_BCR1_MWID_Msk          (0x3U << FMC_BCR1_MWID_Pos)                 /*!< 0x00000030 */\r\n#define FMC_BCR1_MWID              FMC_BCR1_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */\r\n#define FMC_BCR1_MWID_0            (0x1U << FMC_BCR1_MWID_Pos)                 /*!< 0x00000010 */\r\n#define FMC_BCR1_MWID_1            (0x2U << FMC_BCR1_MWID_Pos)                 /*!< 0x00000020 */\r\n#define FMC_BCR1_FACCEN_Pos        (6U)                                        \r\n#define FMC_BCR1_FACCEN_Msk        (0x1U << FMC_BCR1_FACCEN_Pos)               /*!< 0x00000040 */\r\n#define FMC_BCR1_FACCEN            FMC_BCR1_FACCEN_Msk                         /*!<Flash access enable        */\r\n#define FMC_BCR1_BURSTEN_Pos       (8U)                                        \r\n#define FMC_BCR1_BURSTEN_Msk       (0x1U << FMC_BCR1_BURSTEN_Pos)              /*!< 0x00000100 */\r\n#define FMC_BCR1_BURSTEN           FMC_BCR1_BURSTEN_Msk                        /*!<Burst enable bit           */\r\n#define FMC_BCR1_WAITPOL_Pos       (9U)                                        \r\n#define FMC_BCR1_WAITPOL_Msk       (0x1U << FMC_BCR1_WAITPOL_Pos)              /*!< 0x00000200 */\r\n#define FMC_BCR1_WAITPOL           FMC_BCR1_WAITPOL_Msk                        /*!<Wait signal polarity bit   */\r\n#define FMC_BCR1_WRAPMOD_Pos       (10U)                                       \r\n#define FMC_BCR1_WRAPMOD_Msk       (0x1U << FMC_BCR1_WRAPMOD_Pos)              /*!< 0x00000400 */\r\n#define FMC_BCR1_WRAPMOD           FMC_BCR1_WRAPMOD_Msk                        /*!<Wrapped burst mode support */\r\n#define FMC_BCR1_WAITCFG_Pos       (11U)                                       \r\n#define FMC_BCR1_WAITCFG_Msk       (0x1U << FMC_BCR1_WAITCFG_Pos)              /*!< 0x00000800 */\r\n#define FMC_BCR1_WAITCFG           FMC_BCR1_WAITCFG_Msk                        /*!<Wait timing configuration  */\r\n#define FMC_BCR1_WREN_Pos          (12U)                                       \r\n#define FMC_BCR1_WREN_Msk          (0x1U << FMC_BCR1_WREN_Pos)                 /*!< 0x00001000 */\r\n#define FMC_BCR1_WREN              FMC_BCR1_WREN_Msk                           /*!<Write enable bit           */\r\n#define FMC_BCR1_WAITEN_Pos        (13U)                                       \r\n#define FMC_BCR1_WAITEN_Msk        (0x1U << FMC_BCR1_WAITEN_Pos)               /*!< 0x00002000 */\r\n#define FMC_BCR1_WAITEN            FMC_BCR1_WAITEN_Msk                         /*!<Wait enable bit            */\r\n#define FMC_BCR1_EXTMOD_Pos        (14U)                                       \r\n#define FMC_BCR1_EXTMOD_Msk        (0x1U << FMC_BCR1_EXTMOD_Pos)               /*!< 0x00004000 */\r\n#define FMC_BCR1_EXTMOD            FMC_BCR1_EXTMOD_Msk                         /*!<Extended mode enable       */\r\n#define FMC_BCR1_ASYNCWAIT_Pos     (15U)                                       \r\n#define FMC_BCR1_ASYNCWAIT_Msk     (0x1U << FMC_BCR1_ASYNCWAIT_Pos)            /*!< 0x00008000 */\r\n#define FMC_BCR1_ASYNCWAIT         FMC_BCR1_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */\r\n#define FMC_BCR1_CPSIZE_Pos        (16U)                                       \r\n#define FMC_BCR1_CPSIZE_Msk        (0x7U << FMC_BCR1_CPSIZE_Pos)               /*!< 0x00070000 */\r\n#define FMC_BCR1_CPSIZE            FMC_BCR1_CPSIZE_Msk                         /*!<CRAM page size             */\r\n#define FMC_BCR1_CPSIZE_0          (0x1U << FMC_BCR1_CPSIZE_Pos)               /*!< 0x00010000 */\r\n#define FMC_BCR1_CPSIZE_1          (0x2U << FMC_BCR1_CPSIZE_Pos)               /*!< 0x00020000 */\r\n#define FMC_BCR1_CPSIZE_2          (0x4U << FMC_BCR1_CPSIZE_Pos)               /*!< 0x00040000 */\r\n#define FMC_BCR1_CBURSTRW_Pos      (19U)                                       \r\n#define FMC_BCR1_CBURSTRW_Msk      (0x1U << FMC_BCR1_CBURSTRW_Pos)             /*!< 0x00080000 */\r\n#define FMC_BCR1_CBURSTRW          FMC_BCR1_CBURSTRW_Msk                       /*!<Write burst enable         */\r\n#define FMC_BCR1_CCLKEN_Pos        (20U)                                       \r\n#define FMC_BCR1_CCLKEN_Msk        (0x1U << FMC_BCR1_CCLKEN_Pos)               /*!< 0x00100000 */\r\n#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continous clock enable     */\r\n#define FMC_BCR1_WFDIS_Pos         (21U)                                       \r\n#define FMC_BCR1_WFDIS_Msk         (0x1U << FMC_BCR1_WFDIS_Pos)                /*!< 0x00200000 */\r\n#define FMC_BCR1_WFDIS             FMC_BCR1_WFDIS_Msk                          /*!<Write FIFO Disable         */\r\n\r\n/******************  Bit definition for FMC_BCR2 register  *******************/\r\n#define FMC_BCR2_MBKEN_Pos         (0U)                                        \r\n#define FMC_BCR2_MBKEN_Msk         (0x1U << FMC_BCR2_MBKEN_Pos)                /*!< 0x00000001 */\r\n#define FMC_BCR2_MBKEN             FMC_BCR2_MBKEN_Msk                          /*!<Memory bank enable bit                 */\r\n#define FMC_BCR2_MUXEN_Pos         (1U)                                        \r\n#define FMC_BCR2_MUXEN_Msk         (0x1U << FMC_BCR2_MUXEN_Pos)                /*!< 0x00000002 */\r\n#define FMC_BCR2_MUXEN             FMC_BCR2_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */\r\n#define FMC_BCR2_MTYP_Pos          (2U)                                        \r\n#define FMC_BCR2_MTYP_Msk          (0x3U << FMC_BCR2_MTYP_Pos)                 /*!< 0x0000000C */\r\n#define FMC_BCR2_MTYP              FMC_BCR2_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */\r\n#define FMC_BCR2_MTYP_0            (0x1U << FMC_BCR2_MTYP_Pos)                 /*!< 0x00000004 */\r\n#define FMC_BCR2_MTYP_1            (0x2U << FMC_BCR2_MTYP_Pos)                 /*!< 0x00000008 */\r\n#define FMC_BCR2_MWID_Pos          (4U)                                        \r\n#define FMC_BCR2_MWID_Msk          (0x3U << FMC_BCR2_MWID_Pos)                 /*!< 0x00000030 */\r\n#define FMC_BCR2_MWID              FMC_BCR2_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */\r\n#define FMC_BCR2_MWID_0            (0x1U << FMC_BCR2_MWID_Pos)                 /*!< 0x00000010 */\r\n#define FMC_BCR2_MWID_1            (0x2U << FMC_BCR2_MWID_Pos)                 /*!< 0x00000020 */\r\n#define FMC_BCR2_FACCEN_Pos        (6U)                                        \r\n#define FMC_BCR2_FACCEN_Msk        (0x1U << FMC_BCR2_FACCEN_Pos)               /*!< 0x00000040 */\r\n#define FMC_BCR2_FACCEN            FMC_BCR2_FACCEN_Msk                         /*!<Flash access enable        */\r\n#define FMC_BCR2_BURSTEN_Pos       (8U)                                        \r\n#define FMC_BCR2_BURSTEN_Msk       (0x1U << FMC_BCR2_BURSTEN_Pos)              /*!< 0x00000100 */\r\n#define FMC_BCR2_BURSTEN           FMC_BCR2_BURSTEN_Msk                        /*!<Burst enable bit           */\r\n#define FMC_BCR2_WAITPOL_Pos       (9U)                                        \r\n#define FMC_BCR2_WAITPOL_Msk       (0x1U << FMC_BCR2_WAITPOL_Pos)              /*!< 0x00000200 */\r\n#define FMC_BCR2_WAITPOL           FMC_BCR2_WAITPOL_Msk                        /*!<Wait signal polarity bit   */\r\n#define FMC_BCR2_WRAPMOD_Pos       (10U)                                       \r\n#define FMC_BCR2_WRAPMOD_Msk       (0x1U << FMC_BCR2_WRAPMOD_Pos)              /*!< 0x00000400 */\r\n#define FMC_BCR2_WRAPMOD           FMC_BCR2_WRAPMOD_Msk                        /*!<Wrapped burst mode support */\r\n#define FMC_BCR2_WAITCFG_Pos       (11U)                                       \r\n#define FMC_BCR2_WAITCFG_Msk       (0x1U << FMC_BCR2_WAITCFG_Pos)              /*!< 0x00000800 */\r\n#define FMC_BCR2_WAITCFG           FMC_BCR2_WAITCFG_Msk                        /*!<Wait timing configuration  */\r\n#define FMC_BCR2_WREN_Pos          (12U)                                       \r\n#define FMC_BCR2_WREN_Msk          (0x1U << FMC_BCR2_WREN_Pos)                 /*!< 0x00001000 */\r\n#define FMC_BCR2_WREN              FMC_BCR2_WREN_Msk                           /*!<Write enable bit           */\r\n#define FMC_BCR2_WAITEN_Pos        (13U)                                       \r\n#define FMC_BCR2_WAITEN_Msk        (0x1U << FMC_BCR2_WAITEN_Pos)               /*!< 0x00002000 */\r\n#define FMC_BCR2_WAITEN            FMC_BCR2_WAITEN_Msk                         /*!<Wait enable bit            */\r\n#define FMC_BCR2_EXTMOD_Pos        (14U)                                       \r\n#define FMC_BCR2_EXTMOD_Msk        (0x1U << FMC_BCR2_EXTMOD_Pos)               /*!< 0x00004000 */\r\n#define FMC_BCR2_EXTMOD            FMC_BCR2_EXTMOD_Msk                         /*!<Extended mode enable       */\r\n#define FMC_BCR2_ASYNCWAIT_Pos     (15U)                                       \r\n#define FMC_BCR2_ASYNCWAIT_Msk     (0x1U << FMC_BCR2_ASYNCWAIT_Pos)            /*!< 0x00008000 */\r\n#define FMC_BCR2_ASYNCWAIT         FMC_BCR2_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */\r\n#define FMC_BCR2_CPSIZE_Pos        (16U)                                       \r\n#define FMC_BCR2_CPSIZE_Msk        (0x7U << FMC_BCR2_CPSIZE_Pos)               /*!< 0x00070000 */\r\n#define FMC_BCR2_CPSIZE            FMC_BCR2_CPSIZE_Msk                         /*!<CRAM page size             */\r\n#define FMC_BCR2_CPSIZE_0          (0x1U << FMC_BCR2_CPSIZE_Pos)               /*!< 0x00010000 */\r\n#define FMC_BCR2_CPSIZE_1          (0x2U << FMC_BCR2_CPSIZE_Pos)               /*!< 0x00020000 */\r\n#define FMC_BCR2_CPSIZE_2          (0x4U << FMC_BCR2_CPSIZE_Pos)               /*!< 0x00040000 */\r\n#define FMC_BCR2_CBURSTRW_Pos      (19U)                                       \r\n#define FMC_BCR2_CBURSTRW_Msk      (0x1U << FMC_BCR2_CBURSTRW_Pos)             /*!< 0x00080000 */\r\n#define FMC_BCR2_CBURSTRW          FMC_BCR2_CBURSTRW_Msk                       /*!<Write burst enable         */\r\n\r\n/******************  Bit definition for FMC_BCR3 register  *******************/\r\n#define FMC_BCR3_MBKEN_Pos         (0U)                                        \r\n#define FMC_BCR3_MBKEN_Msk         (0x1U << FMC_BCR3_MBKEN_Pos)                /*!< 0x00000001 */\r\n#define FMC_BCR3_MBKEN             FMC_BCR3_MBKEN_Msk                          /*!<Memory bank enable bit                 */\r\n#define FMC_BCR3_MUXEN_Pos         (1U)                                        \r\n#define FMC_BCR3_MUXEN_Msk         (0x1U << FMC_BCR3_MUXEN_Pos)                /*!< 0x00000002 */\r\n#define FMC_BCR3_MUXEN             FMC_BCR3_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */\r\n#define FMC_BCR3_MTYP_Pos          (2U)                                        \r\n#define FMC_BCR3_MTYP_Msk          (0x3U << FMC_BCR3_MTYP_Pos)                 /*!< 0x0000000C */\r\n#define FMC_BCR3_MTYP              FMC_BCR3_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */\r\n#define FMC_BCR3_MTYP_0            (0x1U << FMC_BCR3_MTYP_Pos)                 /*!< 0x00000004 */\r\n#define FMC_BCR3_MTYP_1            (0x2U << FMC_BCR3_MTYP_Pos)                 /*!< 0x00000008 */\r\n#define FMC_BCR3_MWID_Pos          (4U)                                        \r\n#define FMC_BCR3_MWID_Msk          (0x3U << FMC_BCR3_MWID_Pos)                 /*!< 0x00000030 */\r\n#define FMC_BCR3_MWID              FMC_BCR3_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */\r\n#define FMC_BCR3_MWID_0            (0x1U << FMC_BCR3_MWID_Pos)                 /*!< 0x00000010 */\r\n#define FMC_BCR3_MWID_1            (0x2U << FMC_BCR3_MWID_Pos)                 /*!< 0x00000020 */\r\n#define FMC_BCR3_FACCEN_Pos        (6U)                                        \r\n#define FMC_BCR3_FACCEN_Msk        (0x1U << FMC_BCR3_FACCEN_Pos)               /*!< 0x00000040 */\r\n#define FMC_BCR3_FACCEN            FMC_BCR3_FACCEN_Msk                         /*!<Flash access enable        */\r\n#define FMC_BCR3_BURSTEN_Pos       (8U)                                        \r\n#define FMC_BCR3_BURSTEN_Msk       (0x1U << FMC_BCR3_BURSTEN_Pos)              /*!< 0x00000100 */\r\n#define FMC_BCR3_BURSTEN           FMC_BCR3_BURSTEN_Msk                        /*!<Burst enable bit           */\r\n#define FMC_BCR3_WAITPOL_Pos       (9U)                                        \r\n#define FMC_BCR3_WAITPOL_Msk       (0x1U << FMC_BCR3_WAITPOL_Pos)              /*!< 0x00000200 */\r\n#define FMC_BCR3_WAITPOL           FMC_BCR3_WAITPOL_Msk                        /*!<Wait signal polarity bit   */\r\n#define FMC_BCR3_WRAPMOD_Pos       (10U)                                       \r\n#define FMC_BCR3_WRAPMOD_Msk       (0x1U << FMC_BCR3_WRAPMOD_Pos)              /*!< 0x00000400 */\r\n#define FMC_BCR3_WRAPMOD           FMC_BCR3_WRAPMOD_Msk                        /*!<Wrapped burst mode support */\r\n#define FMC_BCR3_WAITCFG_Pos       (11U)                                       \r\n#define FMC_BCR3_WAITCFG_Msk       (0x1U << FMC_BCR3_WAITCFG_Pos)              /*!< 0x00000800 */\r\n#define FMC_BCR3_WAITCFG           FMC_BCR3_WAITCFG_Msk                        /*!<Wait timing configuration  */\r\n#define FMC_BCR3_WREN_Pos          (12U)                                       \r\n#define FMC_BCR3_WREN_Msk          (0x1U << FMC_BCR3_WREN_Pos)                 /*!< 0x00001000 */\r\n#define FMC_BCR3_WREN              FMC_BCR3_WREN_Msk                           /*!<Write enable bit           */\r\n#define FMC_BCR3_WAITEN_Pos        (13U)                                       \r\n#define FMC_BCR3_WAITEN_Msk        (0x1U << FMC_BCR3_WAITEN_Pos)               /*!< 0x00002000 */\r\n#define FMC_BCR3_WAITEN            FMC_BCR3_WAITEN_Msk                         /*!<Wait enable bit            */\r\n#define FMC_BCR3_EXTMOD_Pos        (14U)                                       \r\n#define FMC_BCR3_EXTMOD_Msk        (0x1U << FMC_BCR3_EXTMOD_Pos)               /*!< 0x00004000 */\r\n#define FMC_BCR3_EXTMOD            FMC_BCR3_EXTMOD_Msk                         /*!<Extended mode enable       */\r\n#define FMC_BCR3_ASYNCWAIT_Pos     (15U)                                       \r\n#define FMC_BCR3_ASYNCWAIT_Msk     (0x1U << FMC_BCR3_ASYNCWAIT_Pos)            /*!< 0x00008000 */\r\n#define FMC_BCR3_ASYNCWAIT         FMC_BCR3_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */\r\n#define FMC_BCR3_CPSIZE_Pos        (16U)                                       \r\n#define FMC_BCR3_CPSIZE_Msk        (0x7U << FMC_BCR3_CPSIZE_Pos)               /*!< 0x00070000 */\r\n#define FMC_BCR3_CPSIZE            FMC_BCR3_CPSIZE_Msk                         /*!<CRAM page size             */\r\n#define FMC_BCR3_CPSIZE_0          (0x1U << FMC_BCR3_CPSIZE_Pos)               /*!< 0x00010000 */\r\n#define FMC_BCR3_CPSIZE_1          (0x2U << FMC_BCR3_CPSIZE_Pos)               /*!< 0x00020000 */\r\n#define FMC_BCR3_CPSIZE_2          (0x4U << FMC_BCR3_CPSIZE_Pos)               /*!< 0x00040000 */\r\n#define FMC_BCR3_CBURSTRW_Pos      (19U)                                       \r\n#define FMC_BCR3_CBURSTRW_Msk      (0x1U << FMC_BCR3_CBURSTRW_Pos)             /*!< 0x00080000 */\r\n#define FMC_BCR3_CBURSTRW          FMC_BCR3_CBURSTRW_Msk                       /*!<Write burst enable         */\r\n\r\n/******************  Bit definition for FMC_BCR4 register  *******************/\r\n#define FMC_BCR4_MBKEN_Pos         (0U)                                        \r\n#define FMC_BCR4_MBKEN_Msk         (0x1U << FMC_BCR4_MBKEN_Pos)                /*!< 0x00000001 */\r\n#define FMC_BCR4_MBKEN             FMC_BCR4_MBKEN_Msk                          /*!<Memory bank enable bit                 */\r\n#define FMC_BCR4_MUXEN_Pos         (1U)                                        \r\n#define FMC_BCR4_MUXEN_Msk         (0x1U << FMC_BCR4_MUXEN_Pos)                /*!< 0x00000002 */\r\n#define FMC_BCR4_MUXEN             FMC_BCR4_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */\r\n#define FMC_BCR4_MTYP_Pos          (2U)                                        \r\n#define FMC_BCR4_MTYP_Msk          (0x3U << FMC_BCR4_MTYP_Pos)                 /*!< 0x0000000C */\r\n#define FMC_BCR4_MTYP              FMC_BCR4_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */\r\n#define FMC_BCR4_MTYP_0            (0x1U << FMC_BCR4_MTYP_Pos)                 /*!< 0x00000004 */\r\n#define FMC_BCR4_MTYP_1            (0x2U << FMC_BCR4_MTYP_Pos)                 /*!< 0x00000008 */\r\n#define FMC_BCR4_MWID_Pos          (4U)                                        \r\n#define FMC_BCR4_MWID_Msk          (0x3U << FMC_BCR4_MWID_Pos)                 /*!< 0x00000030 */\r\n#define FMC_BCR4_MWID              FMC_BCR4_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */\r\n#define FMC_BCR4_MWID_0            (0x1U << FMC_BCR4_MWID_Pos)                 /*!< 0x00000010 */\r\n#define FMC_BCR4_MWID_1            (0x2U << FMC_BCR4_MWID_Pos)                 /*!< 0x00000020 */\r\n#define FMC_BCR4_FACCEN_Pos        (6U)                                        \r\n#define FMC_BCR4_FACCEN_Msk        (0x1U << FMC_BCR4_FACCEN_Pos)               /*!< 0x00000040 */\r\n#define FMC_BCR4_FACCEN            FMC_BCR4_FACCEN_Msk                         /*!<Flash access enable        */\r\n#define FMC_BCR4_BURSTEN_Pos       (8U)                                        \r\n#define FMC_BCR4_BURSTEN_Msk       (0x1U << FMC_BCR4_BURSTEN_Pos)              /*!< 0x00000100 */\r\n#define FMC_BCR4_BURSTEN           FMC_BCR4_BURSTEN_Msk                        /*!<Burst enable bit           */\r\n#define FMC_BCR4_WAITPOL_Pos       (9U)                                        \r\n#define FMC_BCR4_WAITPOL_Msk       (0x1U << FMC_BCR4_WAITPOL_Pos)              /*!< 0x00000200 */\r\n#define FMC_BCR4_WAITPOL           FMC_BCR4_WAITPOL_Msk                        /*!<Wait signal polarity bit   */\r\n#define FMC_BCR4_WRAPMOD_Pos       (10U)                                       \r\n#define FMC_BCR4_WRAPMOD_Msk       (0x1U << FMC_BCR4_WRAPMOD_Pos)              /*!< 0x00000400 */\r\n#define FMC_BCR4_WRAPMOD           FMC_BCR4_WRAPMOD_Msk                        /*!<Wrapped burst mode support */\r\n#define FMC_BCR4_WAITCFG_Pos       (11U)                                       \r\n#define FMC_BCR4_WAITCFG_Msk       (0x1U << FMC_BCR4_WAITCFG_Pos)              /*!< 0x00000800 */\r\n#define FMC_BCR4_WAITCFG           FMC_BCR4_WAITCFG_Msk                        /*!<Wait timing configuration  */\r\n#define FMC_BCR4_WREN_Pos          (12U)                                       \r\n#define FMC_BCR4_WREN_Msk          (0x1U << FMC_BCR4_WREN_Pos)                 /*!< 0x00001000 */\r\n#define FMC_BCR4_WREN              FMC_BCR4_WREN_Msk                           /*!<Write enable bit           */\r\n#define FMC_BCR4_WAITEN_Pos        (13U)                                       \r\n#define FMC_BCR4_WAITEN_Msk        (0x1U << FMC_BCR4_WAITEN_Pos)               /*!< 0x00002000 */\r\n#define FMC_BCR4_WAITEN            FMC_BCR4_WAITEN_Msk                         /*!<Wait enable bit            */\r\n#define FMC_BCR4_EXTMOD_Pos        (14U)                                       \r\n#define FMC_BCR4_EXTMOD_Msk        (0x1U << FMC_BCR4_EXTMOD_Pos)               /*!< 0x00004000 */\r\n#define FMC_BCR4_EXTMOD            FMC_BCR4_EXTMOD_Msk                         /*!<Extended mode enable       */\r\n#define FMC_BCR4_ASYNCWAIT_Pos     (15U)                                       \r\n#define FMC_BCR4_ASYNCWAIT_Msk     (0x1U << FMC_BCR4_ASYNCWAIT_Pos)            /*!< 0x00008000 */\r\n#define FMC_BCR4_ASYNCWAIT         FMC_BCR4_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */\r\n#define FMC_BCR4_CPSIZE_Pos        (16U)                                       \r\n#define FMC_BCR4_CPSIZE_Msk        (0x7U << FMC_BCR4_CPSIZE_Pos)               /*!< 0x00070000 */\r\n#define FMC_BCR4_CPSIZE            FMC_BCR4_CPSIZE_Msk                         /*!<CRAM page size             */\r\n#define FMC_BCR4_CPSIZE_0          (0x1U << FMC_BCR4_CPSIZE_Pos)               /*!< 0x00010000 */\r\n#define FMC_BCR4_CPSIZE_1          (0x2U << FMC_BCR4_CPSIZE_Pos)               /*!< 0x00020000 */\r\n#define FMC_BCR4_CPSIZE_2          (0x4U << FMC_BCR4_CPSIZE_Pos)               /*!< 0x00040000 */\r\n#define FMC_BCR4_CBURSTRW_Pos      (19U)                                       \r\n#define FMC_BCR4_CBURSTRW_Msk      (0x1U << FMC_BCR4_CBURSTRW_Pos)             /*!< 0x00080000 */\r\n#define FMC_BCR4_CBURSTRW          FMC_BCR4_CBURSTRW_Msk                       /*!<Write burst enable         */\r\n\r\n/******************  Bit definition for FMC_BTR1 register  ******************/\r\n#define FMC_BTR1_ADDSET_Pos        (0U)                                        \r\n#define FMC_BTR1_ADDSET_Msk        (0xFU << FMC_BTR1_ADDSET_Pos)               /*!< 0x0000000F */\r\n#define FMC_BTR1_ADDSET            FMC_BTR1_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */\r\n#define FMC_BTR1_ADDSET_0          (0x1U << FMC_BTR1_ADDSET_Pos)               /*!< 0x00000001 */\r\n#define FMC_BTR1_ADDSET_1          (0x2U << FMC_BTR1_ADDSET_Pos)               /*!< 0x00000002 */\r\n#define FMC_BTR1_ADDSET_2          (0x4U << FMC_BTR1_ADDSET_Pos)               /*!< 0x00000004 */\r\n#define FMC_BTR1_ADDSET_3          (0x8U << FMC_BTR1_ADDSET_Pos)               /*!< 0x00000008 */\r\n#define FMC_BTR1_ADDHLD_Pos        (4U)                                        \r\n#define FMC_BTR1_ADDHLD_Msk        (0xFU << FMC_BTR1_ADDHLD_Pos)               /*!< 0x000000F0 */\r\n#define FMC_BTR1_ADDHLD            FMC_BTR1_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */\r\n#define FMC_BTR1_ADDHLD_0          (0x1U << FMC_BTR1_ADDHLD_Pos)               /*!< 0x00000010 */\r\n#define FMC_BTR1_ADDHLD_1          (0x2U << FMC_BTR1_ADDHLD_Pos)               /*!< 0x00000020 */\r\n#define FMC_BTR1_ADDHLD_2          (0x4U << FMC_BTR1_ADDHLD_Pos)               /*!< 0x00000040 */\r\n#define FMC_BTR1_ADDHLD_3          (0x8U << FMC_BTR1_ADDHLD_Pos)               /*!< 0x00000080 */\r\n#define FMC_BTR1_DATAST_Pos        (8U)                                        \r\n#define FMC_BTR1_DATAST_Msk        (0xFFU << FMC_BTR1_DATAST_Pos)              /*!< 0x0000FF00 */\r\n#define FMC_BTR1_DATAST            FMC_BTR1_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */\r\n#define FMC_BTR1_DATAST_0          (0x01U << FMC_BTR1_DATAST_Pos)              /*!< 0x00000100 */\r\n#define FMC_BTR1_DATAST_1          (0x02U << FMC_BTR1_DATAST_Pos)              /*!< 0x00000200 */\r\n#define FMC_BTR1_DATAST_2          (0x04U << FMC_BTR1_DATAST_Pos)              /*!< 0x00000400 */\r\n#define FMC_BTR1_DATAST_3          (0x08U << FMC_BTR1_DATAST_Pos)              /*!< 0x00000800 */\r\n#define FMC_BTR1_DATAST_4          (0x10U << FMC_BTR1_DATAST_Pos)              /*!< 0x00001000 */\r\n#define FMC_BTR1_DATAST_5          (0x20U << FMC_BTR1_DATAST_Pos)              /*!< 0x00002000 */\r\n#define FMC_BTR1_DATAST_6          (0x40U << FMC_BTR1_DATAST_Pos)              /*!< 0x00004000 */\r\n#define FMC_BTR1_DATAST_7          (0x80U << FMC_BTR1_DATAST_Pos)              /*!< 0x00008000 */\r\n#define FMC_BTR1_BUSTURN_Pos       (16U)                                       \r\n#define FMC_BTR1_BUSTURN_Msk       (0xFU << FMC_BTR1_BUSTURN_Pos)              /*!< 0x000F0000 */\r\n#define FMC_BTR1_BUSTURN           FMC_BTR1_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r\n#define FMC_BTR1_BUSTURN_0         (0x1U << FMC_BTR1_BUSTURN_Pos)              /*!< 0x00010000 */\r\n#define FMC_BTR1_BUSTURN_1         (0x2U << FMC_BTR1_BUSTURN_Pos)              /*!< 0x00020000 */\r\n#define FMC_BTR1_BUSTURN_2         (0x4U << FMC_BTR1_BUSTURN_Pos)              /*!< 0x00040000 */\r\n#define FMC_BTR1_BUSTURN_3         (0x8U << FMC_BTR1_BUSTURN_Pos)              /*!< 0x00080000 */\r\n#define FMC_BTR1_CLKDIV_Pos        (20U)                                       \r\n#define FMC_BTR1_CLKDIV_Msk        (0xFU << FMC_BTR1_CLKDIV_Pos)               /*!< 0x00F00000 */\r\n#define FMC_BTR1_CLKDIV            FMC_BTR1_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r\n#define FMC_BTR1_CLKDIV_0          (0x1U << FMC_BTR1_CLKDIV_Pos)               /*!< 0x00100000 */\r\n#define FMC_BTR1_CLKDIV_1          (0x2U << FMC_BTR1_CLKDIV_Pos)               /*!< 0x00200000 */\r\n#define FMC_BTR1_CLKDIV_2          (0x4U << FMC_BTR1_CLKDIV_Pos)               /*!< 0x00400000 */\r\n#define FMC_BTR1_CLKDIV_3          (0x8U << FMC_BTR1_CLKDIV_Pos)               /*!< 0x00800000 */\r\n#define FMC_BTR1_DATLAT_Pos        (24U)                                       \r\n#define FMC_BTR1_DATLAT_Msk        (0xFU << FMC_BTR1_DATLAT_Pos)               /*!< 0x0F000000 */\r\n#define FMC_BTR1_DATLAT            FMC_BTR1_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */\r\n#define FMC_BTR1_DATLAT_0          (0x1U << FMC_BTR1_DATLAT_Pos)               /*!< 0x01000000 */\r\n#define FMC_BTR1_DATLAT_1          (0x2U << FMC_BTR1_DATLAT_Pos)               /*!< 0x02000000 */\r\n#define FMC_BTR1_DATLAT_2          (0x4U << FMC_BTR1_DATLAT_Pos)               /*!< 0x04000000 */\r\n#define FMC_BTR1_DATLAT_3          (0x8U << FMC_BTR1_DATLAT_Pos)               /*!< 0x08000000 */\r\n#define FMC_BTR1_ACCMOD_Pos        (28U)                                       \r\n#define FMC_BTR1_ACCMOD_Msk        (0x3U << FMC_BTR1_ACCMOD_Pos)               /*!< 0x30000000 */\r\n#define FMC_BTR1_ACCMOD            FMC_BTR1_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */\r\n#define FMC_BTR1_ACCMOD_0          (0x1U << FMC_BTR1_ACCMOD_Pos)               /*!< 0x10000000 */\r\n#define FMC_BTR1_ACCMOD_1          (0x2U << FMC_BTR1_ACCMOD_Pos)               /*!< 0x20000000 */\r\n\r\n/******************  Bit definition for FMC_BTR2 register  *******************/\r\n#define FMC_BTR2_ADDSET_Pos        (0U)                                        \r\n#define FMC_BTR2_ADDSET_Msk        (0xFU << FMC_BTR2_ADDSET_Pos)               /*!< 0x0000000F */\r\n#define FMC_BTR2_ADDSET            FMC_BTR2_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */\r\n#define FMC_BTR2_ADDSET_0          (0x1U << FMC_BTR2_ADDSET_Pos)               /*!< 0x00000001 */\r\n#define FMC_BTR2_ADDSET_1          (0x2U << FMC_BTR2_ADDSET_Pos)               /*!< 0x00000002 */\r\n#define FMC_BTR2_ADDSET_2          (0x4U << FMC_BTR2_ADDSET_Pos)               /*!< 0x00000004 */\r\n#define FMC_BTR2_ADDSET_3          (0x8U << FMC_BTR2_ADDSET_Pos)               /*!< 0x00000008 */\r\n#define FMC_BTR2_ADDHLD_Pos        (4U)                                        \r\n#define FMC_BTR2_ADDHLD_Msk        (0xFU << FMC_BTR2_ADDHLD_Pos)               /*!< 0x000000F0 */\r\n#define FMC_BTR2_ADDHLD            FMC_BTR2_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r\n#define FMC_BTR2_ADDHLD_0          (0x1U << FMC_BTR2_ADDHLD_Pos)               /*!< 0x00000010 */\r\n#define FMC_BTR2_ADDHLD_1          (0x2U << FMC_BTR2_ADDHLD_Pos)               /*!< 0x00000020 */\r\n#define FMC_BTR2_ADDHLD_2          (0x4U << FMC_BTR2_ADDHLD_Pos)               /*!< 0x00000040 */\r\n#define FMC_BTR2_ADDHLD_3          (0x8U << FMC_BTR2_ADDHLD_Pos)               /*!< 0x00000080 */\r\n#define FMC_BTR2_DATAST_Pos        (8U)                                        \r\n#define FMC_BTR2_DATAST_Msk        (0xFFU << FMC_BTR2_DATAST_Pos)              /*!< 0x0000FF00 */\r\n#define FMC_BTR2_DATAST            FMC_BTR2_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */\r\n#define FMC_BTR2_DATAST_0          (0x01U << FMC_BTR2_DATAST_Pos)              /*!< 0x00000100 */\r\n#define FMC_BTR2_DATAST_1          (0x02U << FMC_BTR2_DATAST_Pos)              /*!< 0x00000200 */\r\n#define FMC_BTR2_DATAST_2          (0x04U << FMC_BTR2_DATAST_Pos)              /*!< 0x00000400 */\r\n#define FMC_BTR2_DATAST_3          (0x08U << FMC_BTR2_DATAST_Pos)              /*!< 0x00000800 */\r\n#define FMC_BTR2_DATAST_4          (0x10U << FMC_BTR2_DATAST_Pos)              /*!< 0x00001000 */\r\n#define FMC_BTR2_DATAST_5          (0x20U << FMC_BTR2_DATAST_Pos)              /*!< 0x00002000 */\r\n#define FMC_BTR2_DATAST_6          (0x40U << FMC_BTR2_DATAST_Pos)              /*!< 0x00004000 */\r\n#define FMC_BTR2_DATAST_7          (0x80U << FMC_BTR2_DATAST_Pos)              /*!< 0x00008000 */\r\n#define FMC_BTR2_BUSTURN_Pos       (16U)                                       \r\n#define FMC_BTR2_BUSTURN_Msk       (0xFU << FMC_BTR2_BUSTURN_Pos)              /*!< 0x000F0000 */\r\n#define FMC_BTR2_BUSTURN           FMC_BTR2_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r\n#define FMC_BTR2_BUSTURN_0         (0x1U << FMC_BTR2_BUSTURN_Pos)              /*!< 0x00010000 */\r\n#define FMC_BTR2_BUSTURN_1         (0x2U << FMC_BTR2_BUSTURN_Pos)              /*!< 0x00020000 */\r\n#define FMC_BTR2_BUSTURN_2         (0x4U << FMC_BTR2_BUSTURN_Pos)              /*!< 0x00040000 */\r\n#define FMC_BTR2_BUSTURN_3         (0x8U << FMC_BTR2_BUSTURN_Pos)              /*!< 0x00080000 */\r\n#define FMC_BTR2_CLKDIV_Pos        (20U)                                       \r\n#define FMC_BTR2_CLKDIV_Msk        (0xFU << FMC_BTR2_CLKDIV_Pos)               /*!< 0x00F00000 */\r\n#define FMC_BTR2_CLKDIV            FMC_BTR2_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r\n#define FMC_BTR2_CLKDIV_0          (0x1U << FMC_BTR2_CLKDIV_Pos)               /*!< 0x00100000 */\r\n#define FMC_BTR2_CLKDIV_1          (0x2U << FMC_BTR2_CLKDIV_Pos)               /*!< 0x00200000 */\r\n#define FMC_BTR2_CLKDIV_2          (0x4U << FMC_BTR2_CLKDIV_Pos)               /*!< 0x00400000 */\r\n#define FMC_BTR2_CLKDIV_3          (0x8U << FMC_BTR2_CLKDIV_Pos)               /*!< 0x00800000 */\r\n#define FMC_BTR2_DATLAT_Pos        (24U)                                       \r\n#define FMC_BTR2_DATLAT_Msk        (0xFU << FMC_BTR2_DATLAT_Pos)               /*!< 0x0F000000 */\r\n#define FMC_BTR2_DATLAT            FMC_BTR2_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */\r\n#define FMC_BTR2_DATLAT_0          (0x1U << FMC_BTR2_DATLAT_Pos)               /*!< 0x01000000 */\r\n#define FMC_BTR2_DATLAT_1          (0x2U << FMC_BTR2_DATLAT_Pos)               /*!< 0x02000000 */\r\n#define FMC_BTR2_DATLAT_2          (0x4U << FMC_BTR2_DATLAT_Pos)               /*!< 0x04000000 */\r\n#define FMC_BTR2_DATLAT_3          (0x8U << FMC_BTR2_DATLAT_Pos)               /*!< 0x08000000 */\r\n#define FMC_BTR2_ACCMOD_Pos        (28U)                                       \r\n#define FMC_BTR2_ACCMOD_Msk        (0x3U << FMC_BTR2_ACCMOD_Pos)               /*!< 0x30000000 */\r\n#define FMC_BTR2_ACCMOD            FMC_BTR2_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */\r\n#define FMC_BTR2_ACCMOD_0          (0x1U << FMC_BTR2_ACCMOD_Pos)               /*!< 0x10000000 */\r\n#define FMC_BTR2_ACCMOD_1          (0x2U << FMC_BTR2_ACCMOD_Pos)               /*!< 0x20000000 */\r\n\r\n/*******************  Bit definition for FMC_BTR3 register  *******************/\r\n#define FMC_BTR3_ADDSET_Pos        (0U)                                        \r\n#define FMC_BTR3_ADDSET_Msk        (0xFU << FMC_BTR3_ADDSET_Pos)               /*!< 0x0000000F */\r\n#define FMC_BTR3_ADDSET            FMC_BTR3_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */\r\n#define FMC_BTR3_ADDSET_0          (0x1U << FMC_BTR3_ADDSET_Pos)               /*!< 0x00000001 */\r\n#define FMC_BTR3_ADDSET_1          (0x2U << FMC_BTR3_ADDSET_Pos)               /*!< 0x00000002 */\r\n#define FMC_BTR3_ADDSET_2          (0x4U << FMC_BTR3_ADDSET_Pos)               /*!< 0x00000004 */\r\n#define FMC_BTR3_ADDSET_3          (0x8U << FMC_BTR3_ADDSET_Pos)               /*!< 0x00000008 */\r\n#define FMC_BTR3_ADDHLD_Pos        (4U)                                        \r\n#define FMC_BTR3_ADDHLD_Msk        (0xFU << FMC_BTR3_ADDHLD_Pos)               /*!< 0x000000F0 */\r\n#define FMC_BTR3_ADDHLD            FMC_BTR3_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r\n#define FMC_BTR3_ADDHLD_0          (0x1U << FMC_BTR3_ADDHLD_Pos)               /*!< 0x00000010 */\r\n#define FMC_BTR3_ADDHLD_1          (0x2U << FMC_BTR3_ADDHLD_Pos)               /*!< 0x00000020 */\r\n#define FMC_BTR3_ADDHLD_2          (0x4U << FMC_BTR3_ADDHLD_Pos)               /*!< 0x00000040 */\r\n#define FMC_BTR3_ADDHLD_3          (0x8U << FMC_BTR3_ADDHLD_Pos)               /*!< 0x00000080 */\r\n#define FMC_BTR3_DATAST_Pos        (8U)                                        \r\n#define FMC_BTR3_DATAST_Msk        (0xFFU << FMC_BTR3_DATAST_Pos)              /*!< 0x0000FF00 */\r\n#define FMC_BTR3_DATAST            FMC_BTR3_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */\r\n#define FMC_BTR3_DATAST_0          (0x01U << FMC_BTR3_DATAST_Pos)              /*!< 0x00000100 */\r\n#define FMC_BTR3_DATAST_1          (0x02U << FMC_BTR3_DATAST_Pos)              /*!< 0x00000200 */\r\n#define FMC_BTR3_DATAST_2          (0x04U << FMC_BTR3_DATAST_Pos)              /*!< 0x00000400 */\r\n#define FMC_BTR3_DATAST_3          (0x08U << FMC_BTR3_DATAST_Pos)              /*!< 0x00000800 */\r\n#define FMC_BTR3_DATAST_4          (0x10U << FMC_BTR3_DATAST_Pos)              /*!< 0x00001000 */\r\n#define FMC_BTR3_DATAST_5          (0x20U << FMC_BTR3_DATAST_Pos)              /*!< 0x00002000 */\r\n#define FMC_BTR3_DATAST_6          (0x40U << FMC_BTR3_DATAST_Pos)              /*!< 0x00004000 */\r\n#define FMC_BTR3_DATAST_7          (0x80U << FMC_BTR3_DATAST_Pos)              /*!< 0x00008000 */\r\n#define FMC_BTR3_BUSTURN_Pos       (16U)                                       \r\n#define FMC_BTR3_BUSTURN_Msk       (0xFU << FMC_BTR3_BUSTURN_Pos)              /*!< 0x000F0000 */\r\n#define FMC_BTR3_BUSTURN           FMC_BTR3_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r\n#define FMC_BTR3_BUSTURN_0         (0x1U << FMC_BTR3_BUSTURN_Pos)              /*!< 0x00010000 */\r\n#define FMC_BTR3_BUSTURN_1         (0x2U << FMC_BTR3_BUSTURN_Pos)              /*!< 0x00020000 */\r\n#define FMC_BTR3_BUSTURN_2         (0x4U << FMC_BTR3_BUSTURN_Pos)              /*!< 0x00040000 */\r\n#define FMC_BTR3_BUSTURN_3         (0x8U << FMC_BTR3_BUSTURN_Pos)              /*!< 0x00080000 */\r\n#define FMC_BTR3_CLKDIV_Pos        (20U)                                       \r\n#define FMC_BTR3_CLKDIV_Msk        (0xFU << FMC_BTR3_CLKDIV_Pos)               /*!< 0x00F00000 */\r\n#define FMC_BTR3_CLKDIV            FMC_BTR3_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r\n#define FMC_BTR3_CLKDIV_0          (0x1U << FMC_BTR3_CLKDIV_Pos)               /*!< 0x00100000 */\r\n#define FMC_BTR3_CLKDIV_1          (0x2U << FMC_BTR3_CLKDIV_Pos)               /*!< 0x00200000 */\r\n#define FMC_BTR3_CLKDIV_2          (0x4U << FMC_BTR3_CLKDIV_Pos)               /*!< 0x00400000 */\r\n#define FMC_BTR3_CLKDIV_3          (0x8U << FMC_BTR3_CLKDIV_Pos)               /*!< 0x00800000 */\r\n#define FMC_BTR3_DATLAT_Pos        (24U)                                       \r\n#define FMC_BTR3_DATLAT_Msk        (0xFU << FMC_BTR3_DATLAT_Pos)               /*!< 0x0F000000 */\r\n#define FMC_BTR3_DATLAT            FMC_BTR3_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */\r\n#define FMC_BTR3_DATLAT_0          (0x1U << FMC_BTR3_DATLAT_Pos)               /*!< 0x01000000 */\r\n#define FMC_BTR3_DATLAT_1          (0x2U << FMC_BTR3_DATLAT_Pos)               /*!< 0x02000000 */\r\n#define FMC_BTR3_DATLAT_2          (0x4U << FMC_BTR3_DATLAT_Pos)               /*!< 0x04000000 */\r\n#define FMC_BTR3_DATLAT_3          (0x8U << FMC_BTR3_DATLAT_Pos)               /*!< 0x08000000 */\r\n#define FMC_BTR3_ACCMOD_Pos        (28U)                                       \r\n#define FMC_BTR3_ACCMOD_Msk        (0x3U << FMC_BTR3_ACCMOD_Pos)               /*!< 0x30000000 */\r\n#define FMC_BTR3_ACCMOD            FMC_BTR3_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */\r\n#define FMC_BTR3_ACCMOD_0          (0x1U << FMC_BTR3_ACCMOD_Pos)               /*!< 0x10000000 */\r\n#define FMC_BTR3_ACCMOD_1          (0x2U << FMC_BTR3_ACCMOD_Pos)               /*!< 0x20000000 */\r\n\r\n/******************  Bit definition for FMC_BTR4 register  *******************/\r\n#define FMC_BTR4_ADDSET_Pos        (0U)                                        \r\n#define FMC_BTR4_ADDSET_Msk        (0xFU << FMC_BTR4_ADDSET_Pos)               /*!< 0x0000000F */\r\n#define FMC_BTR4_ADDSET            FMC_BTR4_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */\r\n#define FMC_BTR4_ADDSET_0          (0x1U << FMC_BTR4_ADDSET_Pos)               /*!< 0x00000001 */\r\n#define FMC_BTR4_ADDSET_1          (0x2U << FMC_BTR4_ADDSET_Pos)               /*!< 0x00000002 */\r\n#define FMC_BTR4_ADDSET_2          (0x4U << FMC_BTR4_ADDSET_Pos)               /*!< 0x00000004 */\r\n#define FMC_BTR4_ADDSET_3          (0x8U << FMC_BTR4_ADDSET_Pos)               /*!< 0x00000008 */\r\n#define FMC_BTR4_ADDHLD_Pos        (4U)                                        \r\n#define FMC_BTR4_ADDHLD_Msk        (0xFU << FMC_BTR4_ADDHLD_Pos)               /*!< 0x000000F0 */\r\n#define FMC_BTR4_ADDHLD            FMC_BTR4_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r\n#define FMC_BTR4_ADDHLD_0          (0x1U << FMC_BTR4_ADDHLD_Pos)               /*!< 0x00000010 */\r\n#define FMC_BTR4_ADDHLD_1          (0x2U << FMC_BTR4_ADDHLD_Pos)               /*!< 0x00000020 */\r\n#define FMC_BTR4_ADDHLD_2          (0x4U << FMC_BTR4_ADDHLD_Pos)               /*!< 0x00000040 */\r\n#define FMC_BTR4_ADDHLD_3          (0x8U << FMC_BTR4_ADDHLD_Pos)               /*!< 0x00000080 */\r\n#define FMC_BTR4_DATAST_Pos        (8U)                                        \r\n#define FMC_BTR4_DATAST_Msk        (0xFFU << FMC_BTR4_DATAST_Pos)              /*!< 0x0000FF00 */\r\n#define FMC_BTR4_DATAST            FMC_BTR4_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */\r\n#define FMC_BTR4_DATAST_0          (0x01U << FMC_BTR4_DATAST_Pos)              /*!< 0x00000100 */\r\n#define FMC_BTR4_DATAST_1          (0x02U << FMC_BTR4_DATAST_Pos)              /*!< 0x00000200 */\r\n#define FMC_BTR4_DATAST_2          (0x04U << FMC_BTR4_DATAST_Pos)              /*!< 0x00000400 */\r\n#define FMC_BTR4_DATAST_3          (0x08U << FMC_BTR4_DATAST_Pos)              /*!< 0x00000800 */\r\n#define FMC_BTR4_DATAST_4          (0x10U << FMC_BTR4_DATAST_Pos)              /*!< 0x00001000 */\r\n#define FMC_BTR4_DATAST_5          (0x20U << FMC_BTR4_DATAST_Pos)              /*!< 0x00002000 */\r\n#define FMC_BTR4_DATAST_6          (0x40U << FMC_BTR4_DATAST_Pos)              /*!< 0x00004000 */\r\n#define FMC_BTR4_DATAST_7          (0x80U << FMC_BTR4_DATAST_Pos)              /*!< 0x00008000 */\r\n#define FMC_BTR4_BUSTURN_Pos       (16U)                                       \r\n#define FMC_BTR4_BUSTURN_Msk       (0xFU << FMC_BTR4_BUSTURN_Pos)              /*!< 0x000F0000 */\r\n#define FMC_BTR4_BUSTURN           FMC_BTR4_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r\n#define FMC_BTR4_BUSTURN_0         (0x1U << FMC_BTR4_BUSTURN_Pos)              /*!< 0x00010000 */\r\n#define FMC_BTR4_BUSTURN_1         (0x2U << FMC_BTR4_BUSTURN_Pos)              /*!< 0x00020000 */\r\n#define FMC_BTR4_BUSTURN_2         (0x4U << FMC_BTR4_BUSTURN_Pos)              /*!< 0x00040000 */\r\n#define FMC_BTR4_BUSTURN_3         (0x8U << FMC_BTR4_BUSTURN_Pos)              /*!< 0x00080000 */\r\n#define FMC_BTR4_CLKDIV_Pos        (20U)                                       \r\n#define FMC_BTR4_CLKDIV_Msk        (0xFU << FMC_BTR4_CLKDIV_Pos)               /*!< 0x00F00000 */\r\n#define FMC_BTR4_CLKDIV            FMC_BTR4_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r\n#define FMC_BTR4_CLKDIV_0          (0x1U << FMC_BTR4_CLKDIV_Pos)               /*!< 0x00100000 */\r\n#define FMC_BTR4_CLKDIV_1          (0x2U << FMC_BTR4_CLKDIV_Pos)               /*!< 0x00200000 */\r\n#define FMC_BTR4_CLKDIV_2          (0x4U << FMC_BTR4_CLKDIV_Pos)               /*!< 0x00400000 */\r\n#define FMC_BTR4_CLKDIV_3          (0x8U << FMC_BTR4_CLKDIV_Pos)               /*!< 0x00800000 */\r\n#define FMC_BTR4_DATLAT_Pos        (24U)                                       \r\n#define FMC_BTR4_DATLAT_Msk        (0xFU << FMC_BTR4_DATLAT_Pos)               /*!< 0x0F000000 */\r\n#define FMC_BTR4_DATLAT            FMC_BTR4_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */\r\n#define FMC_BTR4_DATLAT_0          (0x1U << FMC_BTR4_DATLAT_Pos)               /*!< 0x01000000 */\r\n#define FMC_BTR4_DATLAT_1          (0x2U << FMC_BTR4_DATLAT_Pos)               /*!< 0x02000000 */\r\n#define FMC_BTR4_DATLAT_2          (0x4U << FMC_BTR4_DATLAT_Pos)               /*!< 0x04000000 */\r\n#define FMC_BTR4_DATLAT_3          (0x8U << FMC_BTR4_DATLAT_Pos)               /*!< 0x08000000 */\r\n#define FMC_BTR4_ACCMOD_Pos        (28U)                                       \r\n#define FMC_BTR4_ACCMOD_Msk        (0x3U << FMC_BTR4_ACCMOD_Pos)               /*!< 0x30000000 */\r\n#define FMC_BTR4_ACCMOD            FMC_BTR4_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */\r\n#define FMC_BTR4_ACCMOD_0          (0x1U << FMC_BTR4_ACCMOD_Pos)               /*!< 0x10000000 */\r\n#define FMC_BTR4_ACCMOD_1          (0x2U << FMC_BTR4_ACCMOD_Pos)               /*!< 0x20000000 */\r\n\r\n/******************  Bit definition for FMC_BWTR1 register  ******************/\r\n#define FMC_BWTR1_ADDSET_Pos       (0U)                                        \r\n#define FMC_BWTR1_ADDSET_Msk       (0xFU << FMC_BWTR1_ADDSET_Pos)              /*!< 0x0000000F */\r\n#define FMC_BWTR1_ADDSET           FMC_BWTR1_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */\r\n#define FMC_BWTR1_ADDSET_0         (0x1U << FMC_BWTR1_ADDSET_Pos)              /*!< 0x00000001 */\r\n#define FMC_BWTR1_ADDSET_1         (0x2U << FMC_BWTR1_ADDSET_Pos)              /*!< 0x00000002 */\r\n#define FMC_BWTR1_ADDSET_2         (0x4U << FMC_BWTR1_ADDSET_Pos)              /*!< 0x00000004 */\r\n#define FMC_BWTR1_ADDSET_3         (0x8U << FMC_BWTR1_ADDSET_Pos)              /*!< 0x00000008 */\r\n#define FMC_BWTR1_ADDHLD_Pos       (4U)                                        \r\n#define FMC_BWTR1_ADDHLD_Msk       (0xFU << FMC_BWTR1_ADDHLD_Pos)              /*!< 0x000000F0 */\r\n#define FMC_BWTR1_ADDHLD           FMC_BWTR1_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r\n#define FMC_BWTR1_ADDHLD_0         (0x1U << FMC_BWTR1_ADDHLD_Pos)              /*!< 0x00000010 */\r\n#define FMC_BWTR1_ADDHLD_1         (0x2U << FMC_BWTR1_ADDHLD_Pos)              /*!< 0x00000020 */\r\n#define FMC_BWTR1_ADDHLD_2         (0x4U << FMC_BWTR1_ADDHLD_Pos)              /*!< 0x00000040 */\r\n#define FMC_BWTR1_ADDHLD_3         (0x8U << FMC_BWTR1_ADDHLD_Pos)              /*!< 0x00000080 */\r\n#define FMC_BWTR1_DATAST_Pos       (8U)                                        \r\n#define FMC_BWTR1_DATAST_Msk       (0xFFU << FMC_BWTR1_DATAST_Pos)             /*!< 0x0000FF00 */\r\n#define FMC_BWTR1_DATAST           FMC_BWTR1_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */\r\n#define FMC_BWTR1_DATAST_0         (0x01U << FMC_BWTR1_DATAST_Pos)             /*!< 0x00000100 */\r\n#define FMC_BWTR1_DATAST_1         (0x02U << FMC_BWTR1_DATAST_Pos)             /*!< 0x00000200 */\r\n#define FMC_BWTR1_DATAST_2         (0x04U << FMC_BWTR1_DATAST_Pos)             /*!< 0x00000400 */\r\n#define FMC_BWTR1_DATAST_3         (0x08U << FMC_BWTR1_DATAST_Pos)             /*!< 0x00000800 */\r\n#define FMC_BWTR1_DATAST_4         (0x10U << FMC_BWTR1_DATAST_Pos)             /*!< 0x00001000 */\r\n#define FMC_BWTR1_DATAST_5         (0x20U << FMC_BWTR1_DATAST_Pos)             /*!< 0x00002000 */\r\n#define FMC_BWTR1_DATAST_6         (0x40U << FMC_BWTR1_DATAST_Pos)             /*!< 0x00004000 */\r\n#define FMC_BWTR1_DATAST_7         (0x80U << FMC_BWTR1_DATAST_Pos)             /*!< 0x00008000 */\r\n#define FMC_BWTR1_BUSTURN_Pos      (16U)                                       \r\n#define FMC_BWTR1_BUSTURN_Msk      (0xFU << FMC_BWTR1_BUSTURN_Pos)             /*!< 0x000F0000 */\r\n#define FMC_BWTR1_BUSTURN          FMC_BWTR1_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r\n#define FMC_BWTR1_BUSTURN_0        (0x1U << FMC_BWTR1_BUSTURN_Pos)             /*!< 0x00010000 */\r\n#define FMC_BWTR1_BUSTURN_1        (0x2U << FMC_BWTR1_BUSTURN_Pos)             /*!< 0x00020000 */\r\n#define FMC_BWTR1_BUSTURN_2        (0x4U << FMC_BWTR1_BUSTURN_Pos)             /*!< 0x00040000 */\r\n#define FMC_BWTR1_BUSTURN_3        (0x8U << FMC_BWTR1_BUSTURN_Pos)             /*!< 0x00080000 */\r\n#define FMC_BWTR1_ACCMOD_Pos       (28U)                                       \r\n#define FMC_BWTR1_ACCMOD_Msk       (0x3U << FMC_BWTR1_ACCMOD_Pos)              /*!< 0x30000000 */\r\n#define FMC_BWTR1_ACCMOD           FMC_BWTR1_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */\r\n#define FMC_BWTR1_ACCMOD_0         (0x1U << FMC_BWTR1_ACCMOD_Pos)              /*!< 0x10000000 */\r\n#define FMC_BWTR1_ACCMOD_1         (0x2U << FMC_BWTR1_ACCMOD_Pos)              /*!< 0x20000000 */\r\n\r\n/******************  Bit definition for FMC_BWTR2 register  ******************/\r\n#define FMC_BWTR2_ADDSET_Pos       (0U)                                        \r\n#define FMC_BWTR2_ADDSET_Msk       (0xFU << FMC_BWTR2_ADDSET_Pos)              /*!< 0x0000000F */\r\n#define FMC_BWTR2_ADDSET           FMC_BWTR2_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */\r\n#define FMC_BWTR2_ADDSET_0         (0x1U << FMC_BWTR2_ADDSET_Pos)              /*!< 0x00000001 */\r\n#define FMC_BWTR2_ADDSET_1         (0x2U << FMC_BWTR2_ADDSET_Pos)              /*!< 0x00000002 */\r\n#define FMC_BWTR2_ADDSET_2         (0x4U << FMC_BWTR2_ADDSET_Pos)              /*!< 0x00000004 */\r\n#define FMC_BWTR2_ADDSET_3         (0x8U << FMC_BWTR2_ADDSET_Pos)              /*!< 0x00000008 */\r\n#define FMC_BWTR2_ADDHLD_Pos       (4U)                                        \r\n#define FMC_BWTR2_ADDHLD_Msk       (0xFU << FMC_BWTR2_ADDHLD_Pos)              /*!< 0x000000F0 */\r\n#define FMC_BWTR2_ADDHLD           FMC_BWTR2_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r\n#define FMC_BWTR2_ADDHLD_0         (0x1U << FMC_BWTR2_ADDHLD_Pos)              /*!< 0x00000010 */\r\n#define FMC_BWTR2_ADDHLD_1         (0x2U << FMC_BWTR2_ADDHLD_Pos)              /*!< 0x00000020 */\r\n#define FMC_BWTR2_ADDHLD_2         (0x4U << FMC_BWTR2_ADDHLD_Pos)              /*!< 0x00000040 */\r\n#define FMC_BWTR2_ADDHLD_3         (0x8U << FMC_BWTR2_ADDHLD_Pos)              /*!< 0x00000080 */\r\n#define FMC_BWTR2_DATAST_Pos       (8U)                                        \r\n#define FMC_BWTR2_DATAST_Msk       (0xFFU << FMC_BWTR2_DATAST_Pos)             /*!< 0x0000FF00 */\r\n#define FMC_BWTR2_DATAST           FMC_BWTR2_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */\r\n#define FMC_BWTR2_DATAST_0         (0x01U << FMC_BWTR2_DATAST_Pos)             /*!< 0x00000100 */\r\n#define FMC_BWTR2_DATAST_1         (0x02U << FMC_BWTR2_DATAST_Pos)             /*!< 0x00000200 */\r\n#define FMC_BWTR2_DATAST_2         (0x04U << FMC_BWTR2_DATAST_Pos)             /*!< 0x00000400 */\r\n#define FMC_BWTR2_DATAST_3         (0x08U << FMC_BWTR2_DATAST_Pos)             /*!< 0x00000800 */\r\n#define FMC_BWTR2_DATAST_4         (0x10U << FMC_BWTR2_DATAST_Pos)             /*!< 0x00001000 */\r\n#define FMC_BWTR2_DATAST_5         (0x20U << FMC_BWTR2_DATAST_Pos)             /*!< 0x00002000 */\r\n#define FMC_BWTR2_DATAST_6         (0x40U << FMC_BWTR2_DATAST_Pos)             /*!< 0x00004000 */\r\n#define FMC_BWTR2_DATAST_7         (0x80U << FMC_BWTR2_DATAST_Pos)             /*!< 0x00008000 */\r\n#define FMC_BWTR2_BUSTURN_Pos      (16U)                                       \r\n#define FMC_BWTR2_BUSTURN_Msk      (0xFU << FMC_BWTR2_BUSTURN_Pos)             /*!< 0x000F0000 */\r\n#define FMC_BWTR2_BUSTURN          FMC_BWTR2_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r\n#define FMC_BWTR2_BUSTURN_0        (0x1U << FMC_BWTR2_BUSTURN_Pos)             /*!< 0x00010000 */\r\n#define FMC_BWTR2_BUSTURN_1        (0x2U << FMC_BWTR2_BUSTURN_Pos)             /*!< 0x00020000 */\r\n#define FMC_BWTR2_BUSTURN_2        (0x4U << FMC_BWTR2_BUSTURN_Pos)             /*!< 0x00040000 */\r\n#define FMC_BWTR2_BUSTURN_3        (0x8U << FMC_BWTR2_BUSTURN_Pos)             /*!< 0x00080000 */\r\n#define FMC_BWTR2_ACCMOD_Pos       (28U)                                       \r\n#define FMC_BWTR2_ACCMOD_Msk       (0x3U << FMC_BWTR2_ACCMOD_Pos)              /*!< 0x30000000 */\r\n#define FMC_BWTR2_ACCMOD           FMC_BWTR2_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */\r\n#define FMC_BWTR2_ACCMOD_0         (0x1U << FMC_BWTR2_ACCMOD_Pos)              /*!< 0x10000000 */\r\n#define FMC_BWTR2_ACCMOD_1         (0x2U << FMC_BWTR2_ACCMOD_Pos)              /*!< 0x20000000 */\r\n\r\n/******************  Bit definition for FMC_BWTR3 register  ******************/\r\n#define FMC_BWTR3_ADDSET_Pos       (0U)                                        \r\n#define FMC_BWTR3_ADDSET_Msk       (0xFU << FMC_BWTR3_ADDSET_Pos)              /*!< 0x0000000F */\r\n#define FMC_BWTR3_ADDSET           FMC_BWTR3_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */\r\n#define FMC_BWTR3_ADDSET_0         (0x1U << FMC_BWTR3_ADDSET_Pos)              /*!< 0x00000001 */\r\n#define FMC_BWTR3_ADDSET_1         (0x2U << FMC_BWTR3_ADDSET_Pos)              /*!< 0x00000002 */\r\n#define FMC_BWTR3_ADDSET_2         (0x4U << FMC_BWTR3_ADDSET_Pos)              /*!< 0x00000004 */\r\n#define FMC_BWTR3_ADDSET_3         (0x8U << FMC_BWTR3_ADDSET_Pos)              /*!< 0x00000008 */\r\n#define FMC_BWTR3_ADDHLD_Pos       (4U)                                        \r\n#define FMC_BWTR3_ADDHLD_Msk       (0xFU << FMC_BWTR3_ADDHLD_Pos)              /*!< 0x000000F0 */\r\n#define FMC_BWTR3_ADDHLD           FMC_BWTR3_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r\n#define FMC_BWTR3_ADDHLD_0         (0x1U << FMC_BWTR3_ADDHLD_Pos)              /*!< 0x00000010 */\r\n#define FMC_BWTR3_ADDHLD_1         (0x2U << FMC_BWTR3_ADDHLD_Pos)              /*!< 0x00000020 */\r\n#define FMC_BWTR3_ADDHLD_2         (0x4U << FMC_BWTR3_ADDHLD_Pos)              /*!< 0x00000040 */\r\n#define FMC_BWTR3_ADDHLD_3         (0x8U << FMC_BWTR3_ADDHLD_Pos)              /*!< 0x00000080 */\r\n#define FMC_BWTR3_DATAST_Pos       (8U)                                        \r\n#define FMC_BWTR3_DATAST_Msk       (0xFFU << FMC_BWTR3_DATAST_Pos)             /*!< 0x0000FF00 */\r\n#define FMC_BWTR3_DATAST           FMC_BWTR3_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */\r\n#define FMC_BWTR3_DATAST_0         (0x01U << FMC_BWTR3_DATAST_Pos)             /*!< 0x00000100 */\r\n#define FMC_BWTR3_DATAST_1         (0x02U << FMC_BWTR3_DATAST_Pos)             /*!< 0x00000200 */\r\n#define FMC_BWTR3_DATAST_2         (0x04U << FMC_BWTR3_DATAST_Pos)             /*!< 0x00000400 */\r\n#define FMC_BWTR3_DATAST_3         (0x08U << FMC_BWTR3_DATAST_Pos)             /*!< 0x00000800 */\r\n#define FMC_BWTR3_DATAST_4         (0x10U << FMC_BWTR3_DATAST_Pos)             /*!< 0x00001000 */\r\n#define FMC_BWTR3_DATAST_5         (0x20U << FMC_BWTR3_DATAST_Pos)             /*!< 0x00002000 */\r\n#define FMC_BWTR3_DATAST_6         (0x40U << FMC_BWTR3_DATAST_Pos)             /*!< 0x00004000 */\r\n#define FMC_BWTR3_DATAST_7         (0x80U << FMC_BWTR3_DATAST_Pos)             /*!< 0x00008000 */\r\n#define FMC_BWTR3_BUSTURN_Pos      (16U)                                       \r\n#define FMC_BWTR3_BUSTURN_Msk      (0xFU << FMC_BWTR3_BUSTURN_Pos)             /*!< 0x000F0000 */\r\n#define FMC_BWTR3_BUSTURN          FMC_BWTR3_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r\n#define FMC_BWTR3_BUSTURN_0        (0x1U << FMC_BWTR3_BUSTURN_Pos)             /*!< 0x00010000 */\r\n#define FMC_BWTR3_BUSTURN_1        (0x2U << FMC_BWTR3_BUSTURN_Pos)             /*!< 0x00020000 */\r\n#define FMC_BWTR3_BUSTURN_2        (0x4U << FMC_BWTR3_BUSTURN_Pos)             /*!< 0x00040000 */\r\n#define FMC_BWTR3_BUSTURN_3        (0x8U << FMC_BWTR3_BUSTURN_Pos)             /*!< 0x00080000 */\r\n#define FMC_BWTR3_ACCMOD_Pos       (28U)                                       \r\n#define FMC_BWTR3_ACCMOD_Msk       (0x3U << FMC_BWTR3_ACCMOD_Pos)              /*!< 0x30000000 */\r\n#define FMC_BWTR3_ACCMOD           FMC_BWTR3_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */\r\n#define FMC_BWTR3_ACCMOD_0         (0x1U << FMC_BWTR3_ACCMOD_Pos)              /*!< 0x10000000 */\r\n#define FMC_BWTR3_ACCMOD_1         (0x2U << FMC_BWTR3_ACCMOD_Pos)              /*!< 0x20000000 */\r\n\r\n/******************  Bit definition for FMC_BWTR4 register  ******************/\r\n#define FMC_BWTR4_ADDSET_Pos       (0U)                                        \r\n#define FMC_BWTR4_ADDSET_Msk       (0xFU << FMC_BWTR4_ADDSET_Pos)              /*!< 0x0000000F */\r\n#define FMC_BWTR4_ADDSET           FMC_BWTR4_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */\r\n#define FMC_BWTR4_ADDSET_0         (0x1U << FMC_BWTR4_ADDSET_Pos)              /*!< 0x00000001 */\r\n#define FMC_BWTR4_ADDSET_1         (0x2U << FMC_BWTR4_ADDSET_Pos)              /*!< 0x00000002 */\r\n#define FMC_BWTR4_ADDSET_2         (0x4U << FMC_BWTR4_ADDSET_Pos)              /*!< 0x00000004 */\r\n#define FMC_BWTR4_ADDSET_3         (0x8U << FMC_BWTR4_ADDSET_Pos)              /*!< 0x00000008 */\r\n#define FMC_BWTR4_ADDHLD_Pos       (4U)                                        \r\n#define FMC_BWTR4_ADDHLD_Msk       (0xFU << FMC_BWTR4_ADDHLD_Pos)              /*!< 0x000000F0 */\r\n#define FMC_BWTR4_ADDHLD           FMC_BWTR4_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r\n#define FMC_BWTR4_ADDHLD_0         (0x1U << FMC_BWTR4_ADDHLD_Pos)              /*!< 0x00000010 */\r\n#define FMC_BWTR4_ADDHLD_1         (0x2U << FMC_BWTR4_ADDHLD_Pos)              /*!< 0x00000020 */\r\n#define FMC_BWTR4_ADDHLD_2         (0x4U << FMC_BWTR4_ADDHLD_Pos)              /*!< 0x00000040 */\r\n#define FMC_BWTR4_ADDHLD_3         (0x8U << FMC_BWTR4_ADDHLD_Pos)              /*!< 0x00000080 */\r\n#define FMC_BWTR4_DATAST_Pos       (8U)                                        \r\n#define FMC_BWTR4_DATAST_Msk       (0xFFU << FMC_BWTR4_DATAST_Pos)             /*!< 0x0000FF00 */\r\n#define FMC_BWTR4_DATAST           FMC_BWTR4_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */\r\n#define FMC_BWTR4_DATAST_0         (0x01U << FMC_BWTR4_DATAST_Pos)             /*!< 0x00000100 */\r\n#define FMC_BWTR4_DATAST_1         (0x02U << FMC_BWTR4_DATAST_Pos)             /*!< 0x00000200 */\r\n#define FMC_BWTR4_DATAST_2         (0x04U << FMC_BWTR4_DATAST_Pos)             /*!< 0x00000400 */\r\n#define FMC_BWTR4_DATAST_3         (0x08U << FMC_BWTR4_DATAST_Pos)             /*!< 0x00000800 */\r\n#define FMC_BWTR4_DATAST_4         (0x10U << FMC_BWTR4_DATAST_Pos)             /*!< 0x00001000 */\r\n#define FMC_BWTR4_DATAST_5         (0x20U << FMC_BWTR4_DATAST_Pos)             /*!< 0x00002000 */\r\n#define FMC_BWTR4_DATAST_6         (0x40U << FMC_BWTR4_DATAST_Pos)             /*!< 0x00004000 */\r\n#define FMC_BWTR4_DATAST_7         (0x80U << FMC_BWTR4_DATAST_Pos)             /*!< 0x00008000 */\r\n#define FMC_BWTR4_BUSTURN_Pos      (16U)                                       \r\n#define FMC_BWTR4_BUSTURN_Msk      (0xFU << FMC_BWTR4_BUSTURN_Pos)             /*!< 0x000F0000 */\r\n#define FMC_BWTR4_BUSTURN          FMC_BWTR4_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r\n#define FMC_BWTR4_BUSTURN_0        (0x1U << FMC_BWTR4_BUSTURN_Pos)             /*!< 0x00010000 */\r\n#define FMC_BWTR4_BUSTURN_1        (0x2U << FMC_BWTR4_BUSTURN_Pos)             /*!< 0x00020000 */\r\n#define FMC_BWTR4_BUSTURN_2        (0x4U << FMC_BWTR4_BUSTURN_Pos)             /*!< 0x00040000 */\r\n#define FMC_BWTR4_BUSTURN_3        (0x8U << FMC_BWTR4_BUSTURN_Pos)             /*!< 0x00080000 */\r\n#define FMC_BWTR4_ACCMOD_Pos       (28U)                                       \r\n#define FMC_BWTR4_ACCMOD_Msk       (0x3U << FMC_BWTR4_ACCMOD_Pos)              /*!< 0x30000000 */\r\n#define FMC_BWTR4_ACCMOD           FMC_BWTR4_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */\r\n#define FMC_BWTR4_ACCMOD_0         (0x1U << FMC_BWTR4_ACCMOD_Pos)              /*!< 0x10000000 */\r\n#define FMC_BWTR4_ACCMOD_1         (0x2U << FMC_BWTR4_ACCMOD_Pos)              /*!< 0x20000000 */\r\n\r\n/******************  Bit definition for FMC_PCR register  *******************/\r\n#define FMC_PCR_PWAITEN_Pos        (1U)                                        \r\n#define FMC_PCR_PWAITEN_Msk        (0x1U << FMC_PCR_PWAITEN_Pos)               /*!< 0x00000002 */\r\n#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */\r\n#define FMC_PCR_PBKEN_Pos          (2U)                                        \r\n#define FMC_PCR_PBKEN_Msk          (0x1U << FMC_PCR_PBKEN_Pos)                 /*!< 0x00000004 */\r\n#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<PC Card/NAND Flash memory bank enable bit */\r\n#define FMC_PCR_PTYP_Pos           (3U)                                        \r\n#define FMC_PCR_PTYP_Msk           (0x1U << FMC_PCR_PTYP_Pos)                  /*!< 0x00000008 */\r\n#define FMC_PCR_PTYP               FMC_PCR_PTYP_Msk                            /*!<Memory type                               */\r\n#define FMC_PCR_PWID_Pos           (4U)                                        \r\n#define FMC_PCR_PWID_Msk           (0x3U << FMC_PCR_PWID_Pos)                  /*!< 0x00000030 */\r\n#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */\r\n#define FMC_PCR_PWID_0             (0x1U << FMC_PCR_PWID_Pos)                  /*!< 0x00000010 */\r\n#define FMC_PCR_PWID_1             (0x2U << FMC_PCR_PWID_Pos)                  /*!< 0x00000020 */\r\n#define FMC_PCR_ECCEN_Pos          (6U)                                        \r\n#define FMC_PCR_ECCEN_Msk          (0x1U << FMC_PCR_ECCEN_Pos)                 /*!< 0x00000040 */\r\n#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */\r\n#define FMC_PCR_TCLR_Pos           (9U)                                        \r\n#define FMC_PCR_TCLR_Msk           (0xFU << FMC_PCR_TCLR_Pos)                  /*!< 0x00001E00 */\r\n#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */\r\n#define FMC_PCR_TCLR_0             (0x1U << FMC_PCR_TCLR_Pos)                  /*!< 0x00000200 */\r\n#define FMC_PCR_TCLR_1             (0x2U << FMC_PCR_TCLR_Pos)                  /*!< 0x00000400 */\r\n#define FMC_PCR_TCLR_2             (0x4U << FMC_PCR_TCLR_Pos)                  /*!< 0x00000800 */\r\n#define FMC_PCR_TCLR_3             (0x8U << FMC_PCR_TCLR_Pos)                  /*!< 0x00001000 */\r\n#define FMC_PCR_TAR_Pos            (13U)                                       \r\n#define FMC_PCR_TAR_Msk            (0xFU << FMC_PCR_TAR_Pos)                   /*!< 0x0001E000 */\r\n#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */\r\n#define FMC_PCR_TAR_0              (0x1U << FMC_PCR_TAR_Pos)                   /*!< 0x00002000 */\r\n#define FMC_PCR_TAR_1              (0x2U << FMC_PCR_TAR_Pos)                   /*!< 0x00004000 */\r\n#define FMC_PCR_TAR_2              (0x4U << FMC_PCR_TAR_Pos)                   /*!< 0x00008000 */\r\n#define FMC_PCR_TAR_3              (0x8U << FMC_PCR_TAR_Pos)                   /*!< 0x00010000 */\r\n#define FMC_PCR_ECCPS_Pos          (17U)                                       \r\n#define FMC_PCR_ECCPS_Msk          (0x7U << FMC_PCR_ECCPS_Pos)                 /*!< 0x000E0000 */\r\n#define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[2:0] bits (ECC page size)           */\r\n#define FMC_PCR_ECCPS_0            (0x1U << FMC_PCR_ECCPS_Pos)                 /*!< 0x00020000 */\r\n#define FMC_PCR_ECCPS_1            (0x2U << FMC_PCR_ECCPS_Pos)                 /*!< 0x00040000 */\r\n#define FMC_PCR_ECCPS_2            (0x4U << FMC_PCR_ECCPS_Pos)                 /*!< 0x00080000 */\r\n\r\n/*******************  Bit definition for FMC_SR register  *******************/\r\n#define FMC_SR_IRS_Pos             (0U)                                        \r\n#define FMC_SR_IRS_Msk             (0x1U << FMC_SR_IRS_Pos)                    /*!< 0x00000001 */\r\n#define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */\r\n#define FMC_SR_ILS_Pos             (1U)                                        \r\n#define FMC_SR_ILS_Msk             (0x1U << FMC_SR_ILS_Pos)                    /*!< 0x00000002 */\r\n#define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */\r\n#define FMC_SR_IFS_Pos             (2U)                                        \r\n#define FMC_SR_IFS_Msk             (0x1U << FMC_SR_IFS_Pos)                    /*!< 0x00000004 */\r\n#define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */\r\n#define FMC_SR_IREN_Pos            (3U)                                        \r\n#define FMC_SR_IREN_Msk            (0x1U << FMC_SR_IREN_Pos)                   /*!< 0x00000008 */\r\n#define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */\r\n#define FMC_SR_ILEN_Pos            (4U)                                        \r\n#define FMC_SR_ILEN_Msk            (0x1U << FMC_SR_ILEN_Pos)                   /*!< 0x00000010 */\r\n#define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */\r\n#define FMC_SR_IFEN_Pos            (5U)                                        \r\n#define FMC_SR_IFEN_Msk            (0x1U << FMC_SR_IFEN_Pos)                   /*!< 0x00000020 */\r\n#define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */\r\n#define FMC_SR_FEMPT_Pos           (6U)                                        \r\n#define FMC_SR_FEMPT_Msk           (0x1U << FMC_SR_FEMPT_Pos)                  /*!< 0x00000040 */\r\n#define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */\r\n\r\n/******************  Bit definition for FMC_PMEM register  ******************/\r\n#define FMC_PMEM_MEMSET3_Pos       (0U)                                        \r\n#define FMC_PMEM_MEMSET3_Msk       (0xFFU << FMC_PMEM_MEMSET3_Pos)             /*!< 0x000000FF */\r\n#define FMC_PMEM_MEMSET3           FMC_PMEM_MEMSET3_Msk                        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */\r\n#define FMC_PMEM_MEMSET3_0         (0x01U << FMC_PMEM_MEMSET3_Pos)             /*!< 0x00000001 */\r\n#define FMC_PMEM_MEMSET3_1         (0x02U << FMC_PMEM_MEMSET3_Pos)             /*!< 0x00000002 */\r\n#define FMC_PMEM_MEMSET3_2         (0x04U << FMC_PMEM_MEMSET3_Pos)             /*!< 0x00000004 */\r\n#define FMC_PMEM_MEMSET3_3         (0x08U << FMC_PMEM_MEMSET3_Pos)             /*!< 0x00000008 */\r\n#define FMC_PMEM_MEMSET3_4         (0x10U << FMC_PMEM_MEMSET3_Pos)             /*!< 0x00000010 */\r\n#define FMC_PMEM_MEMSET3_5         (0x20U << FMC_PMEM_MEMSET3_Pos)             /*!< 0x00000020 */\r\n#define FMC_PMEM_MEMSET3_6         (0x40U << FMC_PMEM_MEMSET3_Pos)             /*!< 0x00000040 */\r\n#define FMC_PMEM_MEMSET3_7         (0x80U << FMC_PMEM_MEMSET3_Pos)             /*!< 0x00000080 */\r\n#define FMC_PMEM_MEMWAIT3_Pos      (8U)                                        \r\n#define FMC_PMEM_MEMWAIT3_Msk      (0xFFU << FMC_PMEM_MEMWAIT3_Pos)            /*!< 0x0000FF00 */\r\n#define FMC_PMEM_MEMWAIT3          FMC_PMEM_MEMWAIT3_Msk                       /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */\r\n#define FMC_PMEM_MEMWAIT3_0        (0x01U << FMC_PMEM_MEMWAIT3_Pos)            /*!< 0x00000100 */\r\n#define FMC_PMEM_MEMWAIT3_1        (0x02U << FMC_PMEM_MEMWAIT3_Pos)            /*!< 0x00000200 */\r\n#define FMC_PMEM_MEMWAIT3_2        (0x04U << FMC_PMEM_MEMWAIT3_Pos)            /*!< 0x00000400 */\r\n#define FMC_PMEM_MEMWAIT3_3        (0x08U << FMC_PMEM_MEMWAIT3_Pos)            /*!< 0x00000800 */\r\n#define FMC_PMEM_MEMWAIT3_4        (0x10U << FMC_PMEM_MEMWAIT3_Pos)            /*!< 0x00001000 */\r\n#define FMC_PMEM_MEMWAIT3_5        (0x20U << FMC_PMEM_MEMWAIT3_Pos)            /*!< 0x00002000 */\r\n#define FMC_PMEM_MEMWAIT3_6        (0x40U << FMC_PMEM_MEMWAIT3_Pos)            /*!< 0x00004000 */\r\n#define FMC_PMEM_MEMWAIT3_7        (0x80U << FMC_PMEM_MEMWAIT3_Pos)            /*!< 0x00008000 */\r\n#define FMC_PMEM_MEMHOLD3_Pos      (16U)                                       \r\n#define FMC_PMEM_MEMHOLD3_Msk      (0xFFU << FMC_PMEM_MEMHOLD3_Pos)            /*!< 0x00FF0000 */\r\n#define FMC_PMEM_MEMHOLD3          FMC_PMEM_MEMHOLD3_Msk                       /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */\r\n#define FMC_PMEM_MEMHOLD3_0        (0x01U << FMC_PMEM_MEMHOLD3_Pos)            /*!< 0x00010000 */\r\n#define FMC_PMEM_MEMHOLD3_1        (0x02U << FMC_PMEM_MEMHOLD3_Pos)            /*!< 0x00020000 */\r\n#define FMC_PMEM_MEMHOLD3_2        (0x04U << FMC_PMEM_MEMHOLD3_Pos)            /*!< 0x00040000 */\r\n#define FMC_PMEM_MEMHOLD3_3        (0x08U << FMC_PMEM_MEMHOLD3_Pos)            /*!< 0x00080000 */\r\n#define FMC_PMEM_MEMHOLD3_4        (0x10U << FMC_PMEM_MEMHOLD3_Pos)            /*!< 0x00100000 */\r\n#define FMC_PMEM_MEMHOLD3_5        (0x20U << FMC_PMEM_MEMHOLD3_Pos)            /*!< 0x00200000 */\r\n#define FMC_PMEM_MEMHOLD3_6        (0x40U << FMC_PMEM_MEMHOLD3_Pos)            /*!< 0x00400000 */\r\n#define FMC_PMEM_MEMHOLD3_7        (0x80U << FMC_PMEM_MEMHOLD3_Pos)            /*!< 0x00800000 */\r\n#define FMC_PMEM_MEMHIZ3_Pos       (24U)                                       \r\n#define FMC_PMEM_MEMHIZ3_Msk       (0xFFU << FMC_PMEM_MEMHIZ3_Pos)             /*!< 0xFF000000 */\r\n#define FMC_PMEM_MEMHIZ3           FMC_PMEM_MEMHIZ3_Msk                        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */\r\n#define FMC_PMEM_MEMHIZ3_0         (0x01U << FMC_PMEM_MEMHIZ3_Pos)             /*!< 0x01000000 */\r\n#define FMC_PMEM_MEMHIZ3_1         (0x02U << FMC_PMEM_MEMHIZ3_Pos)             /*!< 0x02000000 */\r\n#define FMC_PMEM_MEMHIZ3_2         (0x04U << FMC_PMEM_MEMHIZ3_Pos)             /*!< 0x04000000 */\r\n#define FMC_PMEM_MEMHIZ3_3         (0x08U << FMC_PMEM_MEMHIZ3_Pos)             /*!< 0x08000000 */\r\n#define FMC_PMEM_MEMHIZ3_4         (0x10U << FMC_PMEM_MEMHIZ3_Pos)             /*!< 0x10000000 */\r\n#define FMC_PMEM_MEMHIZ3_5         (0x20U << FMC_PMEM_MEMHIZ3_Pos)             /*!< 0x20000000 */\r\n#define FMC_PMEM_MEMHIZ3_6         (0x40U << FMC_PMEM_MEMHIZ3_Pos)             /*!< 0x40000000 */\r\n#define FMC_PMEM_MEMHIZ3_7         (0x80U << FMC_PMEM_MEMHIZ3_Pos)             /*!< 0x80000000 */\r\n\r\n/******************  Bit definition for FMC_PATT register  ******************/\r\n#define FMC_PATT_ATTSET3_Pos       (0U)                                        \r\n#define FMC_PATT_ATTSET3_Msk       (0xFFU << FMC_PATT_ATTSET3_Pos)             /*!< 0x000000FF */\r\n#define FMC_PATT_ATTSET3           FMC_PATT_ATTSET3_Msk                        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */\r\n#define FMC_PATT_ATTSET3_0         (0x01U << FMC_PATT_ATTSET3_Pos)             /*!< 0x00000001 */\r\n#define FMC_PATT_ATTSET3_1         (0x02U << FMC_PATT_ATTSET3_Pos)             /*!< 0x00000002 */\r\n#define FMC_PATT_ATTSET3_2         (0x04U << FMC_PATT_ATTSET3_Pos)             /*!< 0x00000004 */\r\n#define FMC_PATT_ATTSET3_3         (0x08U << FMC_PATT_ATTSET3_Pos)             /*!< 0x00000008 */\r\n#define FMC_PATT_ATTSET3_4         (0x10U << FMC_PATT_ATTSET3_Pos)             /*!< 0x00000010 */\r\n#define FMC_PATT_ATTSET3_5         (0x20U << FMC_PATT_ATTSET3_Pos)             /*!< 0x00000020 */\r\n#define FMC_PATT_ATTSET3_6         (0x40U << FMC_PATT_ATTSET3_Pos)             /*!< 0x00000040 */\r\n#define FMC_PATT_ATTSET3_7         (0x80U << FMC_PATT_ATTSET3_Pos)             /*!< 0x00000080 */\r\n#define FMC_PATT_ATTWAIT3_Pos      (8U)                                        \r\n#define FMC_PATT_ATTWAIT3_Msk      (0xFFU << FMC_PATT_ATTWAIT3_Pos)            /*!< 0x0000FF00 */\r\n#define FMC_PATT_ATTWAIT3          FMC_PATT_ATTWAIT3_Msk                       /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */\r\n#define FMC_PATT_ATTWAIT3_0        (0x01U << FMC_PATT_ATTWAIT3_Pos)            /*!< 0x00000100 */\r\n#define FMC_PATT_ATTWAIT3_1        (0x02U << FMC_PATT_ATTWAIT3_Pos)            /*!< 0x00000200 */\r\n#define FMC_PATT_ATTWAIT3_2        (0x04U << FMC_PATT_ATTWAIT3_Pos)            /*!< 0x00000400 */\r\n#define FMC_PATT_ATTWAIT3_3        (0x08U << FMC_PATT_ATTWAIT3_Pos)            /*!< 0x00000800 */\r\n#define FMC_PATT_ATTWAIT3_4        (0x10U << FMC_PATT_ATTWAIT3_Pos)            /*!< 0x00001000 */\r\n#define FMC_PATT_ATTWAIT3_5        (0x20U << FMC_PATT_ATTWAIT3_Pos)            /*!< 0x00002000 */\r\n#define FMC_PATT_ATTWAIT3_6        (0x40U << FMC_PATT_ATTWAIT3_Pos)            /*!< 0x00004000 */\r\n#define FMC_PATT_ATTWAIT3_7        (0x80U << FMC_PATT_ATTWAIT3_Pos)            /*!< 0x00008000 */\r\n#define FMC_PATT_ATTHOLD3_Pos      (16U)                                       \r\n#define FMC_PATT_ATTHOLD3_Msk      (0xFFU << FMC_PATT_ATTHOLD3_Pos)            /*!< 0x00FF0000 */\r\n#define FMC_PATT_ATTHOLD3          FMC_PATT_ATTHOLD3_Msk                       /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */\r\n#define FMC_PATT_ATTHOLD3_0        (0x01U << FMC_PATT_ATTHOLD3_Pos)            /*!< 0x00010000 */\r\n#define FMC_PATT_ATTHOLD3_1        (0x02U << FMC_PATT_ATTHOLD3_Pos)            /*!< 0x00020000 */\r\n#define FMC_PATT_ATTHOLD3_2        (0x04U << FMC_PATT_ATTHOLD3_Pos)            /*!< 0x00040000 */\r\n#define FMC_PATT_ATTHOLD3_3        (0x08U << FMC_PATT_ATTHOLD3_Pos)            /*!< 0x00080000 */\r\n#define FMC_PATT_ATTHOLD3_4        (0x10U << FMC_PATT_ATTHOLD3_Pos)            /*!< 0x00100000 */\r\n#define FMC_PATT_ATTHOLD3_5        (0x20U << FMC_PATT_ATTHOLD3_Pos)            /*!< 0x00200000 */\r\n#define FMC_PATT_ATTHOLD3_6        (0x40U << FMC_PATT_ATTHOLD3_Pos)            /*!< 0x00400000 */\r\n#define FMC_PATT_ATTHOLD3_7        (0x80U << FMC_PATT_ATTHOLD3_Pos)            /*!< 0x00800000 */\r\n#define FMC_PATT_ATTHIZ3_Pos       (24U)                                       \r\n#define FMC_PATT_ATTHIZ3_Msk       (0xFFU << FMC_PATT_ATTHIZ3_Pos)             /*!< 0xFF000000 */\r\n#define FMC_PATT_ATTHIZ3           FMC_PATT_ATTHIZ3_Msk                        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */\r\n#define FMC_PATT_ATTHIZ3_0         (0x01U << FMC_PATT_ATTHIZ3_Pos)             /*!< 0x01000000 */\r\n#define FMC_PATT_ATTHIZ3_1         (0x02U << FMC_PATT_ATTHIZ3_Pos)             /*!< 0x02000000 */\r\n#define FMC_PATT_ATTHIZ3_2         (0x04U << FMC_PATT_ATTHIZ3_Pos)             /*!< 0x04000000 */\r\n#define FMC_PATT_ATTHIZ3_3         (0x08U << FMC_PATT_ATTHIZ3_Pos)             /*!< 0x08000000 */\r\n#define FMC_PATT_ATTHIZ3_4         (0x10U << FMC_PATT_ATTHIZ3_Pos)             /*!< 0x10000000 */\r\n#define FMC_PATT_ATTHIZ3_5         (0x20U << FMC_PATT_ATTHIZ3_Pos)             /*!< 0x20000000 */\r\n#define FMC_PATT_ATTHIZ3_6         (0x40U << FMC_PATT_ATTHIZ3_Pos)             /*!< 0x40000000 */\r\n#define FMC_PATT_ATTHIZ3_7         (0x80U << FMC_PATT_ATTHIZ3_Pos)             /*!< 0x80000000 */\r\n\r\n/******************  Bit definition for FMC_ECCR register  ******************/\r\n#define FMC_ECCR_ECC3_Pos          (0U)                                        \r\n#define FMC_ECCR_ECC3_Msk          (0xFFFFFFFFU << FMC_ECCR_ECC3_Pos)          /*!< 0xFFFFFFFF */\r\n#define FMC_ECCR_ECC3              FMC_ECCR_ECC3_Msk                           /*!<ECC result */\r\n\r\n/******************  Bit definition for FMC_SDCR1 register  ******************/\r\n#define FMC_SDCR1_NC_Pos           (0U)                                        \r\n#define FMC_SDCR1_NC_Msk           (0x3U << FMC_SDCR1_NC_Pos)                  /*!< 0x00000003 */\r\n#define FMC_SDCR1_NC               FMC_SDCR1_NC_Msk                            /*!<NC[1:0] bits (Number of column bits) */\r\n#define FMC_SDCR1_NC_0             (0x1U << FMC_SDCR1_NC_Pos)                  /*!< 0x00000001 */\r\n#define FMC_SDCR1_NC_1             (0x2U << FMC_SDCR1_NC_Pos)                  /*!< 0x00000002 */\r\n#define FMC_SDCR1_NR_Pos           (2U)                                        \r\n#define FMC_SDCR1_NR_Msk           (0x3U << FMC_SDCR1_NR_Pos)                  /*!< 0x0000000C */\r\n#define FMC_SDCR1_NR               FMC_SDCR1_NR_Msk                            /*!<NR[1:0] bits (Number of row bits) */\r\n#define FMC_SDCR1_NR_0             (0x1U << FMC_SDCR1_NR_Pos)                  /*!< 0x00000004 */\r\n#define FMC_SDCR1_NR_1             (0x2U << FMC_SDCR1_NR_Pos)                  /*!< 0x00000008 */\r\n#define FMC_SDCR1_MWID_Pos         (4U)                                        \r\n#define FMC_SDCR1_MWID_Msk         (0x3U << FMC_SDCR1_MWID_Pos)                /*!< 0x00000030 */\r\n#define FMC_SDCR1_MWID             FMC_SDCR1_MWID_Msk                          /*!<NR[1:0] bits (Number of row bits) */\r\n#define FMC_SDCR1_MWID_0           (0x1U << FMC_SDCR1_MWID_Pos)                /*!< 0x00000010 */\r\n#define FMC_SDCR1_MWID_1           (0x2U << FMC_SDCR1_MWID_Pos)                /*!< 0x00000020 */\r\n#define FMC_SDCR1_NB_Pos           (6U)                                        \r\n#define FMC_SDCR1_NB_Msk           (0x1U << FMC_SDCR1_NB_Pos)                  /*!< 0x00000040 */\r\n#define FMC_SDCR1_NB               FMC_SDCR1_NB_Msk                            /*!<Number of internal bank */\r\n#define FMC_SDCR1_CAS_Pos          (7U)                                        \r\n#define FMC_SDCR1_CAS_Msk          (0x3U << FMC_SDCR1_CAS_Pos)                 /*!< 0x00000180 */\r\n#define FMC_SDCR1_CAS              FMC_SDCR1_CAS_Msk                           /*!<CAS[1:0] bits (CAS latency) */\r\n#define FMC_SDCR1_CAS_0            (0x1U << FMC_SDCR1_CAS_Pos)                 /*!< 0x00000080 */\r\n#define FMC_SDCR1_CAS_1            (0x2U << FMC_SDCR1_CAS_Pos)                 /*!< 0x00000100 */\r\n#define FMC_SDCR1_WP_Pos           (9U)                                        \r\n#define FMC_SDCR1_WP_Msk           (0x1U << FMC_SDCR1_WP_Pos)                  /*!< 0x00000200 */\r\n#define FMC_SDCR1_WP               FMC_SDCR1_WP_Msk                            /*!<Write protection */\r\n#define FMC_SDCR1_SDCLK_Pos        (10U)                                       \r\n#define FMC_SDCR1_SDCLK_Msk        (0x3U << FMC_SDCR1_SDCLK_Pos)               /*!< 0x00000C00 */\r\n#define FMC_SDCR1_SDCLK            FMC_SDCR1_SDCLK_Msk                         /*!<SDRAM clock configuration */\r\n#define FMC_SDCR1_SDCLK_0          (0x1U << FMC_SDCR1_SDCLK_Pos)               /*!< 0x00000400 */\r\n#define FMC_SDCR1_SDCLK_1          (0x2U << FMC_SDCR1_SDCLK_Pos)               /*!< 0x00000800 */\r\n#define FMC_SDCR1_RBURST_Pos       (12U)                                       \r\n#define FMC_SDCR1_RBURST_Msk       (0x1U << FMC_SDCR1_RBURST_Pos)              /*!< 0x00001000 */\r\n#define FMC_SDCR1_RBURST           FMC_SDCR1_RBURST_Msk                        /*!<Read burst */\r\n#define FMC_SDCR1_RPIPE_Pos        (13U)                                       \r\n#define FMC_SDCR1_RPIPE_Msk        (0x3U << FMC_SDCR1_RPIPE_Pos)               /*!< 0x00006000 */\r\n#define FMC_SDCR1_RPIPE            FMC_SDCR1_RPIPE_Msk                         /*!<Write protection */\r\n#define FMC_SDCR1_RPIPE_0          (0x1U << FMC_SDCR1_RPIPE_Pos)               /*!< 0x00002000 */\r\n#define FMC_SDCR1_RPIPE_1          (0x2U << FMC_SDCR1_RPIPE_Pos)               /*!< 0x00004000 */\r\n\r\n/******************  Bit definition for FMC_SDCR2 register  ******************/\r\n#define FMC_SDCR2_NC_Pos           (0U)                                        \r\n#define FMC_SDCR2_NC_Msk           (0x3U << FMC_SDCR2_NC_Pos)                  /*!< 0x00000003 */\r\n#define FMC_SDCR2_NC               FMC_SDCR2_NC_Msk                            /*!<NC[1:0] bits (Number of column bits) */\r\n#define FMC_SDCR2_NC_0             (0x1U << FMC_SDCR2_NC_Pos)                  /*!< 0x00000001 */\r\n#define FMC_SDCR2_NC_1             (0x2U << FMC_SDCR2_NC_Pos)                  /*!< 0x00000002 */\r\n#define FMC_SDCR2_NR_Pos           (2U)                                        \r\n#define FMC_SDCR2_NR_Msk           (0x3U << FMC_SDCR2_NR_Pos)                  /*!< 0x0000000C */\r\n#define FMC_SDCR2_NR               FMC_SDCR2_NR_Msk                            /*!<NR[1:0] bits (Number of row bits) */\r\n#define FMC_SDCR2_NR_0             (0x1U << FMC_SDCR2_NR_Pos)                  /*!< 0x00000004 */\r\n#define FMC_SDCR2_NR_1             (0x2U << FMC_SDCR2_NR_Pos)                  /*!< 0x00000008 */\r\n#define FMC_SDCR2_MWID_Pos         (4U)                                        \r\n#define FMC_SDCR2_MWID_Msk         (0x3U << FMC_SDCR2_MWID_Pos)                /*!< 0x00000030 */\r\n#define FMC_SDCR2_MWID             FMC_SDCR2_MWID_Msk                          /*!<NR[1:0] bits (Number of row bits) */\r\n#define FMC_SDCR2_MWID_0           (0x1U << FMC_SDCR2_MWID_Pos)                /*!< 0x00000010 */\r\n#define FMC_SDCR2_MWID_1           (0x2U << FMC_SDCR2_MWID_Pos)                /*!< 0x00000020 */\r\n#define FMC_SDCR2_NB_Pos           (6U)                                        \r\n#define FMC_SDCR2_NB_Msk           (0x1U << FMC_SDCR2_NB_Pos)                  /*!< 0x00000040 */\r\n#define FMC_SDCR2_NB               FMC_SDCR2_NB_Msk                            /*!<Number of internal bank */\r\n#define FMC_SDCR2_CAS_Pos          (7U)                                        \r\n#define FMC_SDCR2_CAS_Msk          (0x3U << FMC_SDCR2_CAS_Pos)                 /*!< 0x00000180 */\r\n#define FMC_SDCR2_CAS              FMC_SDCR2_CAS_Msk                           /*!<CAS[1:0] bits (CAS latency) */\r\n#define FMC_SDCR2_CAS_0            (0x1U << FMC_SDCR2_CAS_Pos)                 /*!< 0x00000080 */\r\n#define FMC_SDCR2_CAS_1            (0x2U << FMC_SDCR2_CAS_Pos)                 /*!< 0x00000100 */\r\n#define FMC_SDCR2_WP_Pos           (9U)                                        \r\n#define FMC_SDCR2_WP_Msk           (0x1U << FMC_SDCR2_WP_Pos)                  /*!< 0x00000200 */\r\n#define FMC_SDCR2_WP               FMC_SDCR2_WP_Msk                            /*!<Write protection */\r\n#define FMC_SDCR2_SDCLK_Pos        (10U)                                       \r\n#define FMC_SDCR2_SDCLK_Msk        (0x3U << FMC_SDCR2_SDCLK_Pos)               /*!< 0x00000C00 */\r\n#define FMC_SDCR2_SDCLK            FMC_SDCR2_SDCLK_Msk                         /*!<SDCLK[1:0] (SDRAM clock configuration) */\r\n#define FMC_SDCR2_SDCLK_0          (0x1U << FMC_SDCR2_SDCLK_Pos)               /*!< 0x00000400 */\r\n#define FMC_SDCR2_SDCLK_1          (0x2U << FMC_SDCR2_SDCLK_Pos)               /*!< 0x00000800 */\r\n#define FMC_SDCR2_RBURST_Pos       (12U)                                       \r\n#define FMC_SDCR2_RBURST_Msk       (0x1U << FMC_SDCR2_RBURST_Pos)              /*!< 0x00001000 */\r\n#define FMC_SDCR2_RBURST           FMC_SDCR2_RBURST_Msk                        /*!<Read burst */\r\n#define FMC_SDCR2_RPIPE_Pos        (13U)                                       \r\n#define FMC_SDCR2_RPIPE_Msk        (0x3U << FMC_SDCR2_RPIPE_Pos)               /*!< 0x00006000 */\r\n#define FMC_SDCR2_RPIPE            FMC_SDCR2_RPIPE_Msk                         /*!<RPIPE[1:0](Read pipe) */\r\n#define FMC_SDCR2_RPIPE_0          (0x1U << FMC_SDCR2_RPIPE_Pos)               /*!< 0x00002000 */\r\n#define FMC_SDCR2_RPIPE_1          (0x2U << FMC_SDCR2_RPIPE_Pos)               /*!< 0x00004000 */\r\n\r\n/******************  Bit definition for FMC_SDTR1 register  ******************/\r\n#define FMC_SDTR1_TMRD_Pos         (0U)                                        \r\n#define FMC_SDTR1_TMRD_Msk         (0xFU << FMC_SDTR1_TMRD_Pos)                /*!< 0x0000000F */\r\n#define FMC_SDTR1_TMRD             FMC_SDTR1_TMRD_Msk                          /*!<TMRD[3:0] bits (Load mode register to active) */\r\n#define FMC_SDTR1_TMRD_0           (0x1U << FMC_SDTR1_TMRD_Pos)                /*!< 0x00000001 */\r\n#define FMC_SDTR1_TMRD_1           (0x2U << FMC_SDTR1_TMRD_Pos)                /*!< 0x00000002 */\r\n#define FMC_SDTR1_TMRD_2           (0x4U << FMC_SDTR1_TMRD_Pos)                /*!< 0x00000004 */\r\n#define FMC_SDTR1_TMRD_3           (0x8U << FMC_SDTR1_TMRD_Pos)                /*!< 0x00000008 */\r\n#define FMC_SDTR1_TXSR_Pos         (4U)                                        \r\n#define FMC_SDTR1_TXSR_Msk         (0xFU << FMC_SDTR1_TXSR_Pos)                /*!< 0x000000F0 */\r\n#define FMC_SDTR1_TXSR             FMC_SDTR1_TXSR_Msk                          /*!<TXSR[3:0] bits (Exit self refresh) */\r\n#define FMC_SDTR1_TXSR_0           (0x1U << FMC_SDTR1_TXSR_Pos)                /*!< 0x00000010 */\r\n#define FMC_SDTR1_TXSR_1           (0x2U << FMC_SDTR1_TXSR_Pos)                /*!< 0x00000020 */\r\n#define FMC_SDTR1_TXSR_2           (0x4U << FMC_SDTR1_TXSR_Pos)                /*!< 0x00000040 */\r\n#define FMC_SDTR1_TXSR_3           (0x8U << FMC_SDTR1_TXSR_Pos)                /*!< 0x00000080 */\r\n#define FMC_SDTR1_TRAS_Pos         (8U)                                        \r\n#define FMC_SDTR1_TRAS_Msk         (0xFU << FMC_SDTR1_TRAS_Pos)                /*!< 0x00000F00 */\r\n#define FMC_SDTR1_TRAS             FMC_SDTR1_TRAS_Msk                          /*!<TRAS[3:0] bits (Self refresh time) */\r\n#define FMC_SDTR1_TRAS_0           (0x1U << FMC_SDTR1_TRAS_Pos)                /*!< 0x00000100 */\r\n#define FMC_SDTR1_TRAS_1           (0x2U << FMC_SDTR1_TRAS_Pos)                /*!< 0x00000200 */\r\n#define FMC_SDTR1_TRAS_2           (0x4U << FMC_SDTR1_TRAS_Pos)                /*!< 0x00000400 */\r\n#define FMC_SDTR1_TRAS_3           (0x8U << FMC_SDTR1_TRAS_Pos)                /*!< 0x00000800 */\r\n#define FMC_SDTR1_TRC_Pos          (12U)                                       \r\n#define FMC_SDTR1_TRC_Msk          (0xFU << FMC_SDTR1_TRC_Pos)                 /*!< 0x0000F000 */\r\n#define FMC_SDTR1_TRC              FMC_SDTR1_TRC_Msk                           /*!<TRC[2:0] bits (Row cycle delay) */\r\n#define FMC_SDTR1_TRC_0            (0x1U << FMC_SDTR1_TRC_Pos)                 /*!< 0x00001000 */\r\n#define FMC_SDTR1_TRC_1            (0x2U << FMC_SDTR1_TRC_Pos)                 /*!< 0x00002000 */\r\n#define FMC_SDTR1_TRC_2            (0x4U << FMC_SDTR1_TRC_Pos)                 /*!< 0x00004000 */\r\n#define FMC_SDTR1_TWR_Pos          (16U)                                       \r\n#define FMC_SDTR1_TWR_Msk          (0xFU << FMC_SDTR1_TWR_Pos)                 /*!< 0x000F0000 */\r\n#define FMC_SDTR1_TWR              FMC_SDTR1_TWR_Msk                           /*!<TRC[2:0] bits (Write recovery delay) */\r\n#define FMC_SDTR1_TWR_0            (0x1U << FMC_SDTR1_TWR_Pos)                 /*!< 0x00010000 */\r\n#define FMC_SDTR1_TWR_1            (0x2U << FMC_SDTR1_TWR_Pos)                 /*!< 0x00020000 */\r\n#define FMC_SDTR1_TWR_2            (0x4U << FMC_SDTR1_TWR_Pos)                 /*!< 0x00040000 */\r\n#define FMC_SDTR1_TRP_Pos          (20U)                                       \r\n#define FMC_SDTR1_TRP_Msk          (0xFU << FMC_SDTR1_TRP_Pos)                 /*!< 0x00F00000 */\r\n#define FMC_SDTR1_TRP              FMC_SDTR1_TRP_Msk                           /*!<TRP[2:0] bits (Row precharge delay) */\r\n#define FMC_SDTR1_TRP_0            (0x1U << FMC_SDTR1_TRP_Pos)                 /*!< 0x00100000 */\r\n#define FMC_SDTR1_TRP_1            (0x2U << FMC_SDTR1_TRP_Pos)                 /*!< 0x00200000 */\r\n#define FMC_SDTR1_TRP_2            (0x4U << FMC_SDTR1_TRP_Pos)                 /*!< 0x00400000 */\r\n#define FMC_SDTR1_TRCD_Pos         (24U)                                       \r\n#define FMC_SDTR1_TRCD_Msk         (0xFU << FMC_SDTR1_TRCD_Pos)                /*!< 0x0F000000 */\r\n#define FMC_SDTR1_TRCD             FMC_SDTR1_TRCD_Msk                          /*!<TRP[2:0] bits (Row to column delay) */\r\n#define FMC_SDTR1_TRCD_0           (0x1U << FMC_SDTR1_TRCD_Pos)                /*!< 0x01000000 */\r\n#define FMC_SDTR1_TRCD_1           (0x2U << FMC_SDTR1_TRCD_Pos)                /*!< 0x02000000 */\r\n#define FMC_SDTR1_TRCD_2           (0x4U << FMC_SDTR1_TRCD_Pos)                /*!< 0x04000000 */\r\n\r\n/******************  Bit definition for FMC_SDTR2 register  ******************/\r\n#define FMC_SDTR2_TMRD_Pos         (0U)                                        \r\n#define FMC_SDTR2_TMRD_Msk         (0xFU << FMC_SDTR2_TMRD_Pos)                /*!< 0x0000000F */\r\n#define FMC_SDTR2_TMRD             FMC_SDTR2_TMRD_Msk                          /*!<TMRD[3:0] bits (Load mode register to active) */\r\n#define FMC_SDTR2_TMRD_0           (0x1U << FMC_SDTR2_TMRD_Pos)                /*!< 0x00000001 */\r\n#define FMC_SDTR2_TMRD_1           (0x2U << FMC_SDTR2_TMRD_Pos)                /*!< 0x00000002 */\r\n#define FMC_SDTR2_TMRD_2           (0x4U << FMC_SDTR2_TMRD_Pos)                /*!< 0x00000004 */\r\n#define FMC_SDTR2_TMRD_3           (0x8U << FMC_SDTR2_TMRD_Pos)                /*!< 0x00000008 */\r\n#define FMC_SDTR2_TXSR_Pos         (4U)                                        \r\n#define FMC_SDTR2_TXSR_Msk         (0xFU << FMC_SDTR2_TXSR_Pos)                /*!< 0x000000F0 */\r\n#define FMC_SDTR2_TXSR             FMC_SDTR2_TXSR_Msk                          /*!<TXSR[3:0] bits (Exit self refresh) */\r\n#define FMC_SDTR2_TXSR_0           (0x1U << FMC_SDTR2_TXSR_Pos)                /*!< 0x00000010 */\r\n#define FMC_SDTR2_TXSR_1           (0x2U << FMC_SDTR2_TXSR_Pos)                /*!< 0x00000020 */\r\n#define FMC_SDTR2_TXSR_2           (0x4U << FMC_SDTR2_TXSR_Pos)                /*!< 0x00000040 */\r\n#define FMC_SDTR2_TXSR_3           (0x8U << FMC_SDTR2_TXSR_Pos)                /*!< 0x00000080 */\r\n#define FMC_SDTR2_TRAS_Pos         (8U)                                        \r\n#define FMC_SDTR2_TRAS_Msk         (0xFU << FMC_SDTR2_TRAS_Pos)                /*!< 0x00000F00 */\r\n#define FMC_SDTR2_TRAS             FMC_SDTR2_TRAS_Msk                          /*!<TRAS[3:0] bits (Self refresh time) */\r\n#define FMC_SDTR2_TRAS_0           (0x1U << FMC_SDTR2_TRAS_Pos)                /*!< 0x00000100 */\r\n#define FMC_SDTR2_TRAS_1           (0x2U << FMC_SDTR2_TRAS_Pos)                /*!< 0x00000200 */\r\n#define FMC_SDTR2_TRAS_2           (0x4U << FMC_SDTR2_TRAS_Pos)                /*!< 0x00000400 */\r\n#define FMC_SDTR2_TRAS_3           (0x8U << FMC_SDTR2_TRAS_Pos)                /*!< 0x00000800 */\r\n#define FMC_SDTR2_TRC_Pos          (12U)                                       \r\n#define FMC_SDTR2_TRC_Msk          (0xFU << FMC_SDTR2_TRC_Pos)                 /*!< 0x0000F000 */\r\n#define FMC_SDTR2_TRC              FMC_SDTR2_TRC_Msk                           /*!<TRC[2:0] bits (Row cycle delay) */\r\n#define FMC_SDTR2_TRC_0            (0x1U << FMC_SDTR2_TRC_Pos)                 /*!< 0x00001000 */\r\n#define FMC_SDTR2_TRC_1            (0x2U << FMC_SDTR2_TRC_Pos)                 /*!< 0x00002000 */\r\n#define FMC_SDTR2_TRC_2            (0x4U << FMC_SDTR2_TRC_Pos)                 /*!< 0x00004000 */\r\n#define FMC_SDTR2_TWR_Pos          (16U)                                       \r\n#define FMC_SDTR2_TWR_Msk          (0xFU << FMC_SDTR2_TWR_Pos)                 /*!< 0x000F0000 */\r\n#define FMC_SDTR2_TWR              FMC_SDTR2_TWR_Msk                           /*!<TRC[2:0] bits (Write recovery delay) */\r\n#define FMC_SDTR2_TWR_0            (0x1U << FMC_SDTR2_TWR_Pos)                 /*!< 0x00010000 */\r\n#define FMC_SDTR2_TWR_1            (0x2U << FMC_SDTR2_TWR_Pos)                 /*!< 0x00020000 */\r\n#define FMC_SDTR2_TWR_2            (0x4U << FMC_SDTR2_TWR_Pos)                 /*!< 0x00040000 */\r\n#define FMC_SDTR2_TRP_Pos          (20U)                                       \r\n#define FMC_SDTR2_TRP_Msk          (0xFU << FMC_SDTR2_TRP_Pos)                 /*!< 0x00F00000 */\r\n#define FMC_SDTR2_TRP              FMC_SDTR2_TRP_Msk                           /*!<TRP[2:0] bits (Row precharge delay) */\r\n#define FMC_SDTR2_TRP_0            (0x1U << FMC_SDTR2_TRP_Pos)                 /*!< 0x00100000 */\r\n#define FMC_SDTR2_TRP_1            (0x2U << FMC_SDTR2_TRP_Pos)                 /*!< 0x00200000 */\r\n#define FMC_SDTR2_TRP_2            (0x4U << FMC_SDTR2_TRP_Pos)                 /*!< 0x00400000 */\r\n#define FMC_SDTR2_TRCD_Pos         (24U)                                       \r\n#define FMC_SDTR2_TRCD_Msk         (0xFU << FMC_SDTR2_TRCD_Pos)                /*!< 0x0F000000 */\r\n#define FMC_SDTR2_TRCD             FMC_SDTR2_TRCD_Msk                          /*!<TRP[2:0] bits (Row to column delay) */\r\n#define FMC_SDTR2_TRCD_0           (0x1U << FMC_SDTR2_TRCD_Pos)                /*!< 0x01000000 */\r\n#define FMC_SDTR2_TRCD_1           (0x2U << FMC_SDTR2_TRCD_Pos)                /*!< 0x02000000 */\r\n#define FMC_SDTR2_TRCD_2           (0x4U << FMC_SDTR2_TRCD_Pos)                /*!< 0x04000000 */\r\n\r\n/******************  Bit definition for FMC_SDCMR register  ******************/\r\n#define FMC_SDCMR_MODE_Pos         (0U)                                        \r\n#define FMC_SDCMR_MODE_Msk         (0x7U << FMC_SDCMR_MODE_Pos)                /*!< 0x00000007 */\r\n#define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */\r\n#define FMC_SDCMR_MODE_0           (0x1U << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */\r\n#define FMC_SDCMR_MODE_1           (0x2U << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */\r\n#define FMC_SDCMR_MODE_2           (0x4U << FMC_SDCMR_MODE_Pos)                /*!< 0x00000004 */\r\n#define FMC_SDCMR_CTB2_Pos         (3U)                                        \r\n#define FMC_SDCMR_CTB2_Msk         (0x1U << FMC_SDCMR_CTB2_Pos)                /*!< 0x00000008 */\r\n#define FMC_SDCMR_CTB2             FMC_SDCMR_CTB2_Msk                          /*!<Command target 2 */\r\n#define FMC_SDCMR_CTB1_Pos         (4U)                                        \r\n#define FMC_SDCMR_CTB1_Msk         (0x1U << FMC_SDCMR_CTB1_Pos)                /*!< 0x00000010 */\r\n#define FMC_SDCMR_CTB1             FMC_SDCMR_CTB1_Msk                          /*!<Command target 1 */\r\n#define FMC_SDCMR_NRFS_Pos         (5U)                                        \r\n#define FMC_SDCMR_NRFS_Msk         (0xFU << FMC_SDCMR_NRFS_Pos)                /*!< 0x000001E0 */\r\n#define FMC_SDCMR_NRFS             FMC_SDCMR_NRFS_Msk                          /*!<NRFS[3:0] bits (Number of auto-refresh) */\r\n#define FMC_SDCMR_NRFS_0           (0x1U << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000020 */\r\n#define FMC_SDCMR_NRFS_1           (0x2U << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000040 */\r\n#define FMC_SDCMR_NRFS_2           (0x4U << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000080 */\r\n#define FMC_SDCMR_NRFS_3           (0x8U << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000100 */\r\n#define FMC_SDCMR_MRD_Pos          (9U)                                        \r\n#define FMC_SDCMR_MRD_Msk          (0x1FFFU << FMC_SDCMR_MRD_Pos)              /*!< 0x003FFE00 */\r\n#define FMC_SDCMR_MRD              FMC_SDCMR_MRD_Msk                           /*!<MRD[12:0] bits (Mode register definition) */\r\n\r\n/******************  Bit definition for FMC_SDRTR register  ******************/\r\n#define FMC_SDRTR_CRE_Pos          (0U)                                        \r\n#define FMC_SDRTR_CRE_Msk          (0x1U << FMC_SDRTR_CRE_Pos)                 /*!< 0x00000001 */\r\n#define FMC_SDRTR_CRE              FMC_SDRTR_CRE_Msk                           /*!<Clear refresh error flag */\r\n#define FMC_SDRTR_COUNT_Pos        (1U)                                        \r\n#define FMC_SDRTR_COUNT_Msk        (0x1FFFU << FMC_SDRTR_COUNT_Pos)            /*!< 0x00003FFE */\r\n#define FMC_SDRTR_COUNT            FMC_SDRTR_COUNT_Msk                         /*!<COUNT[12:0] bits (Refresh timer count) */\r\n#define FMC_SDRTR_REIE_Pos         (14U)                                       \r\n#define FMC_SDRTR_REIE_Msk         (0x1U << FMC_SDRTR_REIE_Pos)                /*!< 0x00004000 */\r\n#define FMC_SDRTR_REIE             FMC_SDRTR_REIE_Msk                          /*!<RES interupt enable */\r\n\r\n/******************  Bit definition for FMC_SDSR register  ******************/\r\n#define FMC_SDSR_RE_Pos            (0U)                                        \r\n#define FMC_SDSR_RE_Msk            (0x1U << FMC_SDSR_RE_Pos)                   /*!< 0x00000001 */\r\n#define FMC_SDSR_RE                FMC_SDSR_RE_Msk                             /*!<Refresh error flag */\r\n#define FMC_SDSR_MODES1_Pos        (1U)                                        \r\n#define FMC_SDSR_MODES1_Msk        (0x3U << FMC_SDSR_MODES1_Pos)               /*!< 0x00000006 */\r\n#define FMC_SDSR_MODES1            FMC_SDSR_MODES1_Msk                         /*!<MODES1[1:0]bits (Status mode for bank 1) */\r\n#define FMC_SDSR_MODES1_0          (0x1U << FMC_SDSR_MODES1_Pos)               /*!< 0x00000002 */\r\n#define FMC_SDSR_MODES1_1          (0x2U << FMC_SDSR_MODES1_Pos)               /*!< 0x00000004 */\r\n#define FMC_SDSR_MODES2_Pos        (3U)                                        \r\n#define FMC_SDSR_MODES2_Msk        (0x3U << FMC_SDSR_MODES2_Pos)               /*!< 0x00000018 */\r\n#define FMC_SDSR_MODES2            FMC_SDSR_MODES2_Msk                         /*!<MODES2[1:0]bits (Status mode for bank 2) */\r\n#define FMC_SDSR_MODES2_0          (0x1U << FMC_SDSR_MODES2_Pos)               /*!< 0x00000008 */\r\n#define FMC_SDSR_MODES2_1          (0x2U << FMC_SDSR_MODES2_Pos)               /*!< 0x00000010 */\r\n#define FMC_SDSR_BUSY_Pos          (5U)                                        \r\n#define FMC_SDSR_BUSY_Msk          (0x1U << FMC_SDSR_BUSY_Pos)                 /*!< 0x00000020 */\r\n#define FMC_SDSR_BUSY              FMC_SDSR_BUSY_Msk                           /*!<Busy status */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                            General Purpose I/O                             */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/******************  Bits definition for GPIO_MODER register  *****************/\r\n#define GPIO_MODER_MODER0_Pos            (0U)                                  \r\n#define GPIO_MODER_MODER0_Msk            (0x3U << GPIO_MODER_MODER0_Pos)       /*!< 0x00000003 */\r\n#define GPIO_MODER_MODER0                GPIO_MODER_MODER0_Msk                 \r\n#define GPIO_MODER_MODER0_0              (0x1U << GPIO_MODER_MODER0_Pos)       /*!< 0x00000001 */\r\n#define GPIO_MODER_MODER0_1              (0x2U << GPIO_MODER_MODER0_Pos)       /*!< 0x00000002 */\r\n#define GPIO_MODER_MODER1_Pos            (2U)                                  \r\n#define GPIO_MODER_MODER1_Msk            (0x3U << GPIO_MODER_MODER1_Pos)       /*!< 0x0000000C */\r\n#define GPIO_MODER_MODER1                GPIO_MODER_MODER1_Msk                 \r\n#define GPIO_MODER_MODER1_0              (0x1U << GPIO_MODER_MODER1_Pos)       /*!< 0x00000004 */\r\n#define GPIO_MODER_MODER1_1              (0x2U << GPIO_MODER_MODER1_Pos)       /*!< 0x00000008 */\r\n#define GPIO_MODER_MODER2_Pos            (4U)                                  \r\n#define GPIO_MODER_MODER2_Msk            (0x3U << GPIO_MODER_MODER2_Pos)       /*!< 0x00000030 */\r\n#define GPIO_MODER_MODER2                GPIO_MODER_MODER2_Msk                 \r\n#define GPIO_MODER_MODER2_0              (0x1U << GPIO_MODER_MODER2_Pos)       /*!< 0x00000010 */\r\n#define GPIO_MODER_MODER2_1              (0x2U << GPIO_MODER_MODER2_Pos)       /*!< 0x00000020 */\r\n#define GPIO_MODER_MODER3_Pos            (6U)                                  \r\n#define GPIO_MODER_MODER3_Msk            (0x3U << GPIO_MODER_MODER3_Pos)       /*!< 0x000000C0 */\r\n#define GPIO_MODER_MODER3                GPIO_MODER_MODER3_Msk                 \r\n#define GPIO_MODER_MODER3_0              (0x1U << GPIO_MODER_MODER3_Pos)       /*!< 0x00000040 */\r\n#define GPIO_MODER_MODER3_1              (0x2U << GPIO_MODER_MODER3_Pos)       /*!< 0x00000080 */\r\n#define GPIO_MODER_MODER4_Pos            (8U)                                  \r\n#define GPIO_MODER_MODER4_Msk            (0x3U << GPIO_MODER_MODER4_Pos)       /*!< 0x00000300 */\r\n#define GPIO_MODER_MODER4                GPIO_MODER_MODER4_Msk                 \r\n#define GPIO_MODER_MODER4_0              (0x1U << GPIO_MODER_MODER4_Pos)       /*!< 0x00000100 */\r\n#define GPIO_MODER_MODER4_1              (0x2U << GPIO_MODER_MODER4_Pos)       /*!< 0x00000200 */\r\n#define GPIO_MODER_MODER5_Pos            (10U)                                 \r\n#define GPIO_MODER_MODER5_Msk            (0x3U << GPIO_MODER_MODER5_Pos)       /*!< 0x00000C00 */\r\n#define GPIO_MODER_MODER5                GPIO_MODER_MODER5_Msk                 \r\n#define GPIO_MODER_MODER5_0              (0x1U << GPIO_MODER_MODER5_Pos)       /*!< 0x00000400 */\r\n#define GPIO_MODER_MODER5_1              (0x2U << GPIO_MODER_MODER5_Pos)       /*!< 0x00000800 */\r\n#define GPIO_MODER_MODER6_Pos            (12U)                                 \r\n#define GPIO_MODER_MODER6_Msk            (0x3U << GPIO_MODER_MODER6_Pos)       /*!< 0x00003000 */\r\n#define GPIO_MODER_MODER6                GPIO_MODER_MODER6_Msk                 \r\n#define GPIO_MODER_MODER6_0              (0x1U << GPIO_MODER_MODER6_Pos)       /*!< 0x00001000 */\r\n#define GPIO_MODER_MODER6_1              (0x2U << GPIO_MODER_MODER6_Pos)       /*!< 0x00002000 */\r\n#define GPIO_MODER_MODER7_Pos            (14U)                                 \r\n#define GPIO_MODER_MODER7_Msk            (0x3U << GPIO_MODER_MODER7_Pos)       /*!< 0x0000C000 */\r\n#define GPIO_MODER_MODER7                GPIO_MODER_MODER7_Msk                 \r\n#define GPIO_MODER_MODER7_0              (0x1U << GPIO_MODER_MODER7_Pos)       /*!< 0x00004000 */\r\n#define GPIO_MODER_MODER7_1              (0x2U << GPIO_MODER_MODER7_Pos)       /*!< 0x00008000 */\r\n#define GPIO_MODER_MODER8_Pos            (16U)                                 \r\n#define GPIO_MODER_MODER8_Msk            (0x3U << GPIO_MODER_MODER8_Pos)       /*!< 0x00030000 */\r\n#define GPIO_MODER_MODER8                GPIO_MODER_MODER8_Msk                 \r\n#define GPIO_MODER_MODER8_0              (0x1U << GPIO_MODER_MODER8_Pos)       /*!< 0x00010000 */\r\n#define GPIO_MODER_MODER8_1              (0x2U << GPIO_MODER_MODER8_Pos)       /*!< 0x00020000 */\r\n#define GPIO_MODER_MODER9_Pos            (18U)                                 \r\n#define GPIO_MODER_MODER9_Msk            (0x3U << GPIO_MODER_MODER9_Pos)       /*!< 0x000C0000 */\r\n#define GPIO_MODER_MODER9                GPIO_MODER_MODER9_Msk                 \r\n#define GPIO_MODER_MODER9_0              (0x1U << GPIO_MODER_MODER9_Pos)       /*!< 0x00040000 */\r\n#define GPIO_MODER_MODER9_1              (0x2U << GPIO_MODER_MODER9_Pos)       /*!< 0x00080000 */\r\n#define GPIO_MODER_MODER10_Pos           (20U)                                 \r\n#define GPIO_MODER_MODER10_Msk           (0x3U << GPIO_MODER_MODER10_Pos)      /*!< 0x00300000 */\r\n#define GPIO_MODER_MODER10               GPIO_MODER_MODER10_Msk                \r\n#define GPIO_MODER_MODER10_0             (0x1U << GPIO_MODER_MODER10_Pos)      /*!< 0x00100000 */\r\n#define GPIO_MODER_MODER10_1             (0x2U << GPIO_MODER_MODER10_Pos)      /*!< 0x00200000 */\r\n#define GPIO_MODER_MODER11_Pos           (22U)                                 \r\n#define GPIO_MODER_MODER11_Msk           (0x3U << GPIO_MODER_MODER11_Pos)      /*!< 0x00C00000 */\r\n#define GPIO_MODER_MODER11               GPIO_MODER_MODER11_Msk                \r\n#define GPIO_MODER_MODER11_0             (0x1U << GPIO_MODER_MODER11_Pos)      /*!< 0x00400000 */\r\n#define GPIO_MODER_MODER11_1             (0x2U << GPIO_MODER_MODER11_Pos)      /*!< 0x00800000 */\r\n#define GPIO_MODER_MODER12_Pos           (24U)                                 \r\n#define GPIO_MODER_MODER12_Msk           (0x3U << GPIO_MODER_MODER12_Pos)      /*!< 0x03000000 */\r\n#define GPIO_MODER_MODER12               GPIO_MODER_MODER12_Msk                \r\n#define GPIO_MODER_MODER12_0             (0x1U << GPIO_MODER_MODER12_Pos)      /*!< 0x01000000 */\r\n#define GPIO_MODER_MODER12_1             (0x2U << GPIO_MODER_MODER12_Pos)      /*!< 0x02000000 */\r\n#define GPIO_MODER_MODER13_Pos           (26U)                                 \r\n#define GPIO_MODER_MODER13_Msk           (0x3U << GPIO_MODER_MODER13_Pos)      /*!< 0x0C000000 */\r\n#define GPIO_MODER_MODER13               GPIO_MODER_MODER13_Msk                \r\n#define GPIO_MODER_MODER13_0             (0x1U << GPIO_MODER_MODER13_Pos)      /*!< 0x04000000 */\r\n#define GPIO_MODER_MODER13_1             (0x2U << GPIO_MODER_MODER13_Pos)      /*!< 0x08000000 */\r\n#define GPIO_MODER_MODER14_Pos           (28U)                                 \r\n#define GPIO_MODER_MODER14_Msk           (0x3U << GPIO_MODER_MODER14_Pos)      /*!< 0x30000000 */\r\n#define GPIO_MODER_MODER14               GPIO_MODER_MODER14_Msk                \r\n#define GPIO_MODER_MODER14_0             (0x1U << GPIO_MODER_MODER14_Pos)      /*!< 0x10000000 */\r\n#define GPIO_MODER_MODER14_1             (0x2U << GPIO_MODER_MODER14_Pos)      /*!< 0x20000000 */\r\n#define GPIO_MODER_MODER15_Pos           (30U)                                 \r\n#define GPIO_MODER_MODER15_Msk           (0x3U << GPIO_MODER_MODER15_Pos)      /*!< 0xC0000000 */\r\n#define GPIO_MODER_MODER15               GPIO_MODER_MODER15_Msk                \r\n#define GPIO_MODER_MODER15_0             (0x1U << GPIO_MODER_MODER15_Pos)      /*!< 0x40000000 */\r\n#define GPIO_MODER_MODER15_1             (0x2U << GPIO_MODER_MODER15_Pos)      /*!< 0x80000000 */\r\n\r\n/******************  Bits definition for GPIO_OTYPER register  ****************/\r\n#define GPIO_OTYPER_OT_0                 0x00000001U                           \r\n#define GPIO_OTYPER_OT_1                 0x00000002U                           \r\n#define GPIO_OTYPER_OT_2                 0x00000004U                           \r\n#define GPIO_OTYPER_OT_3                 0x00000008U                           \r\n#define GPIO_OTYPER_OT_4                 0x00000010U                           \r\n#define GPIO_OTYPER_OT_5                 0x00000020U                           \r\n#define GPIO_OTYPER_OT_6                 0x00000040U                           \r\n#define GPIO_OTYPER_OT_7                 0x00000080U                           \r\n#define GPIO_OTYPER_OT_8                 0x00000100U                           \r\n#define GPIO_OTYPER_OT_9                 0x00000200U                           \r\n#define GPIO_OTYPER_OT_10                0x00000400U                           \r\n#define GPIO_OTYPER_OT_11                0x00000800U                           \r\n#define GPIO_OTYPER_OT_12                0x00001000U                           \r\n#define GPIO_OTYPER_OT_13                0x00002000U                           \r\n#define GPIO_OTYPER_OT_14                0x00004000U                           \r\n#define GPIO_OTYPER_OT_15                0x00008000U                           \r\n\r\n/******************  Bits definition for GPIO_OSPEEDR register  ***************/\r\n#define GPIO_OSPEEDER_OSPEEDR0_Pos       (0U)                                  \r\n#define GPIO_OSPEEDER_OSPEEDR0_Msk       (0x3U << GPIO_OSPEEDER_OSPEEDR0_Pos)  /*!< 0x00000003 */\r\n#define GPIO_OSPEEDER_OSPEEDR0           GPIO_OSPEEDER_OSPEEDR0_Msk            \r\n#define GPIO_OSPEEDER_OSPEEDR0_0         (0x1U << GPIO_OSPEEDER_OSPEEDR0_Pos)  /*!< 0x00000001 */\r\n#define GPIO_OSPEEDER_OSPEEDR0_1         (0x2U << GPIO_OSPEEDER_OSPEEDR0_Pos)  /*!< 0x00000002 */\r\n#define GPIO_OSPEEDER_OSPEEDR1_Pos       (2U)                                  \r\n#define GPIO_OSPEEDER_OSPEEDR1_Msk       (0x3U << GPIO_OSPEEDER_OSPEEDR1_Pos)  /*!< 0x0000000C */\r\n#define GPIO_OSPEEDER_OSPEEDR1           GPIO_OSPEEDER_OSPEEDR1_Msk            \r\n#define GPIO_OSPEEDER_OSPEEDR1_0         (0x1U << GPIO_OSPEEDER_OSPEEDR1_Pos)  /*!< 0x00000004 */\r\n#define GPIO_OSPEEDER_OSPEEDR1_1         (0x2U << GPIO_OSPEEDER_OSPEEDR1_Pos)  /*!< 0x00000008 */\r\n#define GPIO_OSPEEDER_OSPEEDR2_Pos       (4U)                                  \r\n#define GPIO_OSPEEDER_OSPEEDR2_Msk       (0x3U << GPIO_OSPEEDER_OSPEEDR2_Pos)  /*!< 0x00000030 */\r\n#define GPIO_OSPEEDER_OSPEEDR2           GPIO_OSPEEDER_OSPEEDR2_Msk            \r\n#define GPIO_OSPEEDER_OSPEEDR2_0         (0x1U << GPIO_OSPEEDER_OSPEEDR2_Pos)  /*!< 0x00000010 */\r\n#define GPIO_OSPEEDER_OSPEEDR2_1         (0x2U << GPIO_OSPEEDER_OSPEEDR2_Pos)  /*!< 0x00000020 */\r\n#define GPIO_OSPEEDER_OSPEEDR3_Pos       (6U)                                  \r\n#define GPIO_OSPEEDER_OSPEEDR3_Msk       (0x3U << GPIO_OSPEEDER_OSPEEDR3_Pos)  /*!< 0x000000C0 */\r\n#define GPIO_OSPEEDER_OSPEEDR3           GPIO_OSPEEDER_OSPEEDR3_Msk            \r\n#define GPIO_OSPEEDER_OSPEEDR3_0         (0x1U << GPIO_OSPEEDER_OSPEEDR3_Pos)  /*!< 0x00000040 */\r\n#define GPIO_OSPEEDER_OSPEEDR3_1         (0x2U << GPIO_OSPEEDER_OSPEEDR3_Pos)  /*!< 0x00000080 */\r\n#define GPIO_OSPEEDER_OSPEEDR4_Pos       (8U)                                  \r\n#define GPIO_OSPEEDER_OSPEEDR4_Msk       (0x3U << GPIO_OSPEEDER_OSPEEDR4_Pos)  /*!< 0x00000300 */\r\n#define GPIO_OSPEEDER_OSPEEDR4           GPIO_OSPEEDER_OSPEEDR4_Msk            \r\n#define GPIO_OSPEEDER_OSPEEDR4_0         (0x1U << GPIO_OSPEEDER_OSPEEDR4_Pos)  /*!< 0x00000100 */\r\n#define GPIO_OSPEEDER_OSPEEDR4_1         (0x2U << GPIO_OSPEEDER_OSPEEDR4_Pos)  /*!< 0x00000200 */\r\n#define GPIO_OSPEEDER_OSPEEDR5_Pos       (10U)                                 \r\n#define GPIO_OSPEEDER_OSPEEDR5_Msk       (0x3U << GPIO_OSPEEDER_OSPEEDR5_Pos)  /*!< 0x00000C00 */\r\n#define GPIO_OSPEEDER_OSPEEDR5           GPIO_OSPEEDER_OSPEEDR5_Msk            \r\n#define GPIO_OSPEEDER_OSPEEDR5_0         (0x1U << GPIO_OSPEEDER_OSPEEDR5_Pos)  /*!< 0x00000400 */\r\n#define GPIO_OSPEEDER_OSPEEDR5_1         (0x2U << GPIO_OSPEEDER_OSPEEDR5_Pos)  /*!< 0x00000800 */\r\n#define GPIO_OSPEEDER_OSPEEDR6_Pos       (12U)                                 \r\n#define GPIO_OSPEEDER_OSPEEDR6_Msk       (0x3U << GPIO_OSPEEDER_OSPEEDR6_Pos)  /*!< 0x00003000 */\r\n#define GPIO_OSPEEDER_OSPEEDR6           GPIO_OSPEEDER_OSPEEDR6_Msk            \r\n#define GPIO_OSPEEDER_OSPEEDR6_0         (0x1U << GPIO_OSPEEDER_OSPEEDR6_Pos)  /*!< 0x00001000 */\r\n#define GPIO_OSPEEDER_OSPEEDR6_1         (0x2U << GPIO_OSPEEDER_OSPEEDR6_Pos)  /*!< 0x00002000 */\r\n#define GPIO_OSPEEDER_OSPEEDR7_Pos       (14U)                                 \r\n#define GPIO_OSPEEDER_OSPEEDR7_Msk       (0x3U << GPIO_OSPEEDER_OSPEEDR7_Pos)  /*!< 0x0000C000 */\r\n#define GPIO_OSPEEDER_OSPEEDR7           GPIO_OSPEEDER_OSPEEDR7_Msk            \r\n#define GPIO_OSPEEDER_OSPEEDR7_0         (0x1U << GPIO_OSPEEDER_OSPEEDR7_Pos)  /*!< 0x00004000 */\r\n#define GPIO_OSPEEDER_OSPEEDR7_1         (0x2U << GPIO_OSPEEDER_OSPEEDR7_Pos)  /*!< 0x00008000 */\r\n#define GPIO_OSPEEDER_OSPEEDR8_Pos       (16U)                                 \r\n#define GPIO_OSPEEDER_OSPEEDR8_Msk       (0x3U << GPIO_OSPEEDER_OSPEEDR8_Pos)  /*!< 0x00030000 */\r\n#define GPIO_OSPEEDER_OSPEEDR8           GPIO_OSPEEDER_OSPEEDR8_Msk            \r\n#define GPIO_OSPEEDER_OSPEEDR8_0         (0x1U << GPIO_OSPEEDER_OSPEEDR8_Pos)  /*!< 0x00010000 */\r\n#define GPIO_OSPEEDER_OSPEEDR8_1         (0x2U << GPIO_OSPEEDER_OSPEEDR8_Pos)  /*!< 0x00020000 */\r\n#define GPIO_OSPEEDER_OSPEEDR9_Pos       (18U)                                 \r\n#define GPIO_OSPEEDER_OSPEEDR9_Msk       (0x3U << GPIO_OSPEEDER_OSPEEDR9_Pos)  /*!< 0x000C0000 */\r\n#define GPIO_OSPEEDER_OSPEEDR9           GPIO_OSPEEDER_OSPEEDR9_Msk            \r\n#define GPIO_OSPEEDER_OSPEEDR9_0         (0x1U << GPIO_OSPEEDER_OSPEEDR9_Pos)  /*!< 0x00040000 */\r\n#define GPIO_OSPEEDER_OSPEEDR9_1         (0x2U << GPIO_OSPEEDER_OSPEEDR9_Pos)  /*!< 0x00080000 */\r\n#define GPIO_OSPEEDER_OSPEEDR10_Pos      (20U)                                 \r\n#define GPIO_OSPEEDER_OSPEEDR10_Msk      (0x3U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */\r\n#define GPIO_OSPEEDER_OSPEEDR10          GPIO_OSPEEDER_OSPEEDR10_Msk           \r\n#define GPIO_OSPEEDER_OSPEEDR10_0        (0x1U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */\r\n#define GPIO_OSPEEDER_OSPEEDR10_1        (0x2U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */\r\n#define GPIO_OSPEEDER_OSPEEDR11_Pos      (22U)                                 \r\n#define GPIO_OSPEEDER_OSPEEDR11_Msk      (0x3U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */\r\n#define GPIO_OSPEEDER_OSPEEDR11          GPIO_OSPEEDER_OSPEEDR11_Msk           \r\n#define GPIO_OSPEEDER_OSPEEDR11_0        (0x1U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */\r\n#define GPIO_OSPEEDER_OSPEEDR11_1        (0x2U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */\r\n#define GPIO_OSPEEDER_OSPEEDR12_Pos      (24U)                                 \r\n#define GPIO_OSPEEDER_OSPEEDR12_Msk      (0x3U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */\r\n#define GPIO_OSPEEDER_OSPEEDR12          GPIO_OSPEEDER_OSPEEDR12_Msk           \r\n#define GPIO_OSPEEDER_OSPEEDR12_0        (0x1U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */\r\n#define GPIO_OSPEEDER_OSPEEDR12_1        (0x2U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */\r\n#define GPIO_OSPEEDER_OSPEEDR13_Pos      (26U)                                 \r\n#define GPIO_OSPEEDER_OSPEEDR13_Msk      (0x3U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */\r\n#define GPIO_OSPEEDER_OSPEEDR13          GPIO_OSPEEDER_OSPEEDR13_Msk           \r\n#define GPIO_OSPEEDER_OSPEEDR13_0        (0x1U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */\r\n#define GPIO_OSPEEDER_OSPEEDR13_1        (0x2U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */\r\n#define GPIO_OSPEEDER_OSPEEDR14_Pos      (28U)                                 \r\n#define GPIO_OSPEEDER_OSPEEDR14_Msk      (0x3U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */\r\n#define GPIO_OSPEEDER_OSPEEDR14          GPIO_OSPEEDER_OSPEEDR14_Msk           \r\n#define GPIO_OSPEEDER_OSPEEDR14_0        (0x1U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */\r\n#define GPIO_OSPEEDER_OSPEEDR14_1        (0x2U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */\r\n#define GPIO_OSPEEDER_OSPEEDR15_Pos      (30U)                                 \r\n#define GPIO_OSPEEDER_OSPEEDR15_Msk      (0x3U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */\r\n#define GPIO_OSPEEDER_OSPEEDR15          GPIO_OSPEEDER_OSPEEDR15_Msk           \r\n#define GPIO_OSPEEDER_OSPEEDR15_0        (0x1U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */\r\n#define GPIO_OSPEEDER_OSPEEDR15_1        (0x2U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */\r\n\r\n/******************  Bits definition for GPIO_PUPDR register  *****************/\r\n#define GPIO_PUPDR_PUPDR0_Pos            (0U)                                  \r\n#define GPIO_PUPDR_PUPDR0_Msk            (0x3U << GPIO_PUPDR_PUPDR0_Pos)       /*!< 0x00000003 */\r\n#define GPIO_PUPDR_PUPDR0                GPIO_PUPDR_PUPDR0_Msk                 \r\n#define GPIO_PUPDR_PUPDR0_0              (0x1U << GPIO_PUPDR_PUPDR0_Pos)       /*!< 0x00000001 */\r\n#define GPIO_PUPDR_PUPDR0_1              (0x2U << GPIO_PUPDR_PUPDR0_Pos)       /*!< 0x00000002 */\r\n#define GPIO_PUPDR_PUPDR1_Pos            (2U)                                  \r\n#define GPIO_PUPDR_PUPDR1_Msk            (0x3U << GPIO_PUPDR_PUPDR1_Pos)       /*!< 0x0000000C */\r\n#define GPIO_PUPDR_PUPDR1                GPIO_PUPDR_PUPDR1_Msk                 \r\n#define GPIO_PUPDR_PUPDR1_0              (0x1U << GPIO_PUPDR_PUPDR1_Pos)       /*!< 0x00000004 */\r\n#define GPIO_PUPDR_PUPDR1_1              (0x2U << GPIO_PUPDR_PUPDR1_Pos)       /*!< 0x00000008 */\r\n#define GPIO_PUPDR_PUPDR2_Pos            (4U)                                  \r\n#define GPIO_PUPDR_PUPDR2_Msk            (0x3U << GPIO_PUPDR_PUPDR2_Pos)       /*!< 0x00000030 */\r\n#define GPIO_PUPDR_PUPDR2                GPIO_PUPDR_PUPDR2_Msk                 \r\n#define GPIO_PUPDR_PUPDR2_0              (0x1U << GPIO_PUPDR_PUPDR2_Pos)       /*!< 0x00000010 */\r\n#define GPIO_PUPDR_PUPDR2_1              (0x2U << GPIO_PUPDR_PUPDR2_Pos)       /*!< 0x00000020 */\r\n#define GPIO_PUPDR_PUPDR3_Pos            (6U)                                  \r\n#define GPIO_PUPDR_PUPDR3_Msk            (0x3U << GPIO_PUPDR_PUPDR3_Pos)       /*!< 0x000000C0 */\r\n#define GPIO_PUPDR_PUPDR3                GPIO_PUPDR_PUPDR3_Msk                 \r\n#define GPIO_PUPDR_PUPDR3_0              (0x1U << GPIO_PUPDR_PUPDR3_Pos)       /*!< 0x00000040 */\r\n#define GPIO_PUPDR_PUPDR3_1              (0x2U << GPIO_PUPDR_PUPDR3_Pos)       /*!< 0x00000080 */\r\n#define GPIO_PUPDR_PUPDR4_Pos            (8U)                                  \r\n#define GPIO_PUPDR_PUPDR4_Msk            (0x3U << GPIO_PUPDR_PUPDR4_Pos)       /*!< 0x00000300 */\r\n#define GPIO_PUPDR_PUPDR4                GPIO_PUPDR_PUPDR4_Msk                 \r\n#define GPIO_PUPDR_PUPDR4_0              (0x1U << GPIO_PUPDR_PUPDR4_Pos)       /*!< 0x00000100 */\r\n#define GPIO_PUPDR_PUPDR4_1              (0x2U << GPIO_PUPDR_PUPDR4_Pos)       /*!< 0x00000200 */\r\n#define GPIO_PUPDR_PUPDR5_Pos            (10U)                                 \r\n#define GPIO_PUPDR_PUPDR5_Msk            (0x3U << GPIO_PUPDR_PUPDR5_Pos)       /*!< 0x00000C00 */\r\n#define GPIO_PUPDR_PUPDR5                GPIO_PUPDR_PUPDR5_Msk                 \r\n#define GPIO_PUPDR_PUPDR5_0              (0x1U << GPIO_PUPDR_PUPDR5_Pos)       /*!< 0x00000400 */\r\n#define GPIO_PUPDR_PUPDR5_1              (0x2U << GPIO_PUPDR_PUPDR5_Pos)       /*!< 0x00000800 */\r\n#define GPIO_PUPDR_PUPDR6_Pos            (12U)                                 \r\n#define GPIO_PUPDR_PUPDR6_Msk            (0x3U << GPIO_PUPDR_PUPDR6_Pos)       /*!< 0x00003000 */\r\n#define GPIO_PUPDR_PUPDR6                GPIO_PUPDR_PUPDR6_Msk                 \r\n#define GPIO_PUPDR_PUPDR6_0              (0x1U << GPIO_PUPDR_PUPDR6_Pos)       /*!< 0x00001000 */\r\n#define GPIO_PUPDR_PUPDR6_1              (0x2U << GPIO_PUPDR_PUPDR6_Pos)       /*!< 0x00002000 */\r\n#define GPIO_PUPDR_PUPDR7_Pos            (14U)                                 \r\n#define GPIO_PUPDR_PUPDR7_Msk            (0x3U << GPIO_PUPDR_PUPDR7_Pos)       /*!< 0x0000C000 */\r\n#define GPIO_PUPDR_PUPDR7                GPIO_PUPDR_PUPDR7_Msk                 \r\n#define GPIO_PUPDR_PUPDR7_0              (0x1U << GPIO_PUPDR_PUPDR7_Pos)       /*!< 0x00004000 */\r\n#define GPIO_PUPDR_PUPDR7_1              (0x2U << GPIO_PUPDR_PUPDR7_Pos)       /*!< 0x00008000 */\r\n#define GPIO_PUPDR_PUPDR8_Pos            (16U)                                 \r\n#define GPIO_PUPDR_PUPDR8_Msk            (0x3U << GPIO_PUPDR_PUPDR8_Pos)       /*!< 0x00030000 */\r\n#define GPIO_PUPDR_PUPDR8                GPIO_PUPDR_PUPDR8_Msk                 \r\n#define GPIO_PUPDR_PUPDR8_0              (0x1U << GPIO_PUPDR_PUPDR8_Pos)       /*!< 0x00010000 */\r\n#define GPIO_PUPDR_PUPDR8_1              (0x2U << GPIO_PUPDR_PUPDR8_Pos)       /*!< 0x00020000 */\r\n#define GPIO_PUPDR_PUPDR9_Pos            (18U)                                 \r\n#define GPIO_PUPDR_PUPDR9_Msk            (0x3U << GPIO_PUPDR_PUPDR9_Pos)       /*!< 0x000C0000 */\r\n#define GPIO_PUPDR_PUPDR9                GPIO_PUPDR_PUPDR9_Msk                 \r\n#define GPIO_PUPDR_PUPDR9_0              (0x1U << GPIO_PUPDR_PUPDR9_Pos)       /*!< 0x00040000 */\r\n#define GPIO_PUPDR_PUPDR9_1              (0x2U << GPIO_PUPDR_PUPDR9_Pos)       /*!< 0x00080000 */\r\n#define GPIO_PUPDR_PUPDR10_Pos           (20U)                                 \r\n#define GPIO_PUPDR_PUPDR10_Msk           (0x3U << GPIO_PUPDR_PUPDR10_Pos)      /*!< 0x00300000 */\r\n#define GPIO_PUPDR_PUPDR10               GPIO_PUPDR_PUPDR10_Msk                \r\n#define GPIO_PUPDR_PUPDR10_0             (0x1U << GPIO_PUPDR_PUPDR10_Pos)      /*!< 0x00100000 */\r\n#define GPIO_PUPDR_PUPDR10_1             (0x2U << GPIO_PUPDR_PUPDR10_Pos)      /*!< 0x00200000 */\r\n#define GPIO_PUPDR_PUPDR11_Pos           (22U)                                 \r\n#define GPIO_PUPDR_PUPDR11_Msk           (0x3U << GPIO_PUPDR_PUPDR11_Pos)      /*!< 0x00C00000 */\r\n#define GPIO_PUPDR_PUPDR11               GPIO_PUPDR_PUPDR11_Msk                \r\n#define GPIO_PUPDR_PUPDR11_0             (0x1U << GPIO_PUPDR_PUPDR11_Pos)      /*!< 0x00400000 */\r\n#define GPIO_PUPDR_PUPDR11_1             (0x2U << GPIO_PUPDR_PUPDR11_Pos)      /*!< 0x00800000 */\r\n#define GPIO_PUPDR_PUPDR12_Pos           (24U)                                 \r\n#define GPIO_PUPDR_PUPDR12_Msk           (0x3U << GPIO_PUPDR_PUPDR12_Pos)      /*!< 0x03000000 */\r\n#define GPIO_PUPDR_PUPDR12               GPIO_PUPDR_PUPDR12_Msk                \r\n#define GPIO_PUPDR_PUPDR12_0             (0x1U << GPIO_PUPDR_PUPDR12_Pos)      /*!< 0x01000000 */\r\n#define GPIO_PUPDR_PUPDR12_1             (0x2U << GPIO_PUPDR_PUPDR12_Pos)      /*!< 0x02000000 */\r\n#define GPIO_PUPDR_PUPDR13_Pos           (26U)                                 \r\n#define GPIO_PUPDR_PUPDR13_Msk           (0x3U << GPIO_PUPDR_PUPDR13_Pos)      /*!< 0x0C000000 */\r\n#define GPIO_PUPDR_PUPDR13               GPIO_PUPDR_PUPDR13_Msk                \r\n#define GPIO_PUPDR_PUPDR13_0             (0x1U << GPIO_PUPDR_PUPDR13_Pos)      /*!< 0x04000000 */\r\n#define GPIO_PUPDR_PUPDR13_1             (0x2U << GPIO_PUPDR_PUPDR13_Pos)      /*!< 0x08000000 */\r\n#define GPIO_PUPDR_PUPDR14_Pos           (28U)                                 \r\n#define GPIO_PUPDR_PUPDR14_Msk           (0x3U << GPIO_PUPDR_PUPDR14_Pos)      /*!< 0x30000000 */\r\n#define GPIO_PUPDR_PUPDR14               GPIO_PUPDR_PUPDR14_Msk                \r\n#define GPIO_PUPDR_PUPDR14_0             (0x1U << GPIO_PUPDR_PUPDR14_Pos)      /*!< 0x10000000 */\r\n#define GPIO_PUPDR_PUPDR14_1             (0x2U << GPIO_PUPDR_PUPDR14_Pos)      /*!< 0x20000000 */\r\n#define GPIO_PUPDR_PUPDR15_Pos           (30U)                                 \r\n#define GPIO_PUPDR_PUPDR15_Msk           (0x3U << GPIO_PUPDR_PUPDR15_Pos)      /*!< 0xC0000000 */\r\n#define GPIO_PUPDR_PUPDR15               GPIO_PUPDR_PUPDR15_Msk                \r\n#define GPIO_PUPDR_PUPDR15_0             (0x1U << GPIO_PUPDR_PUPDR15_Pos)      /*!< 0x40000000 */\r\n#define GPIO_PUPDR_PUPDR15_1             (0x2U << GPIO_PUPDR_PUPDR15_Pos)      /*!< 0x80000000 */\r\n\r\n/******************  Bits definition for GPIO_IDR register  *******************/\r\n#define GPIO_IDR_IDR_0                   0x00000001U                           \r\n#define GPIO_IDR_IDR_1                   0x00000002U                           \r\n#define GPIO_IDR_IDR_2                   0x00000004U                           \r\n#define GPIO_IDR_IDR_3                   0x00000008U                           \r\n#define GPIO_IDR_IDR_4                   0x00000010U                           \r\n#define GPIO_IDR_IDR_5                   0x00000020U                           \r\n#define GPIO_IDR_IDR_6                   0x00000040U                           \r\n#define GPIO_IDR_IDR_7                   0x00000080U                           \r\n#define GPIO_IDR_IDR_8                   0x00000100U                           \r\n#define GPIO_IDR_IDR_9                   0x00000200U                           \r\n#define GPIO_IDR_IDR_10                  0x00000400U                           \r\n#define GPIO_IDR_IDR_11                  0x00000800U                           \r\n#define GPIO_IDR_IDR_12                  0x00001000U                           \r\n#define GPIO_IDR_IDR_13                  0x00002000U                           \r\n#define GPIO_IDR_IDR_14                  0x00004000U                           \r\n#define GPIO_IDR_IDR_15                  0x00008000U                           \r\n\r\n/******************  Bits definition for GPIO_ODR register  *******************/\r\n#define GPIO_ODR_ODR_0                   0x00000001U                           \r\n#define GPIO_ODR_ODR_1                   0x00000002U                           \r\n#define GPIO_ODR_ODR_2                   0x00000004U                           \r\n#define GPIO_ODR_ODR_3                   0x00000008U                           \r\n#define GPIO_ODR_ODR_4                   0x00000010U                           \r\n#define GPIO_ODR_ODR_5                   0x00000020U                           \r\n#define GPIO_ODR_ODR_6                   0x00000040U                           \r\n#define GPIO_ODR_ODR_7                   0x00000080U                           \r\n#define GPIO_ODR_ODR_8                   0x00000100U                           \r\n#define GPIO_ODR_ODR_9                   0x00000200U                           \r\n#define GPIO_ODR_ODR_10                  0x00000400U                           \r\n#define GPIO_ODR_ODR_11                  0x00000800U                           \r\n#define GPIO_ODR_ODR_12                  0x00001000U                           \r\n#define GPIO_ODR_ODR_13                  0x00002000U                           \r\n#define GPIO_ODR_ODR_14                  0x00004000U                           \r\n#define GPIO_ODR_ODR_15                  0x00008000U                           \r\n\r\n/******************  Bits definition for GPIO_BSRR register  ******************/\r\n#define GPIO_BSRR_BS_0                   0x00000001U                           \r\n#define GPIO_BSRR_BS_1                   0x00000002U                           \r\n#define GPIO_BSRR_BS_2                   0x00000004U                           \r\n#define GPIO_BSRR_BS_3                   0x00000008U                           \r\n#define GPIO_BSRR_BS_4                   0x00000010U                           \r\n#define GPIO_BSRR_BS_5                   0x00000020U                           \r\n#define GPIO_BSRR_BS_6                   0x00000040U                           \r\n#define GPIO_BSRR_BS_7                   0x00000080U                           \r\n#define GPIO_BSRR_BS_8                   0x00000100U                           \r\n#define GPIO_BSRR_BS_9                   0x00000200U                           \r\n#define GPIO_BSRR_BS_10                  0x00000400U                           \r\n#define GPIO_BSRR_BS_11                  0x00000800U                           \r\n#define GPIO_BSRR_BS_12                  0x00001000U                           \r\n#define GPIO_BSRR_BS_13                  0x00002000U                           \r\n#define GPIO_BSRR_BS_14                  0x00004000U                           \r\n#define GPIO_BSRR_BS_15                  0x00008000U                           \r\n#define GPIO_BSRR_BR_0                   0x00010000U                           \r\n#define GPIO_BSRR_BR_1                   0x00020000U                           \r\n#define GPIO_BSRR_BR_2                   0x00040000U                           \r\n#define GPIO_BSRR_BR_3                   0x00080000U                           \r\n#define GPIO_BSRR_BR_4                   0x00100000U                           \r\n#define GPIO_BSRR_BR_5                   0x00200000U                           \r\n#define GPIO_BSRR_BR_6                   0x00400000U                           \r\n#define GPIO_BSRR_BR_7                   0x00800000U                           \r\n#define GPIO_BSRR_BR_8                   0x01000000U                           \r\n#define GPIO_BSRR_BR_9                   0x02000000U                           \r\n#define GPIO_BSRR_BR_10                  0x04000000U                           \r\n#define GPIO_BSRR_BR_11                  0x08000000U                           \r\n#define GPIO_BSRR_BR_12                  0x10000000U                           \r\n#define GPIO_BSRR_BR_13                  0x20000000U                           \r\n#define GPIO_BSRR_BR_14                  0x40000000U                           \r\n#define GPIO_BSRR_BR_15                  0x80000000U                           \r\n\r\n/****************** Bit definition for GPIO_LCKR register *********************/\r\n#define GPIO_LCKR_LCK0_Pos               (0U)                                  \r\n#define GPIO_LCKR_LCK0_Msk               (0x1U << GPIO_LCKR_LCK0_Pos)          /*!< 0x00000001 */\r\n#define GPIO_LCKR_LCK0                   GPIO_LCKR_LCK0_Msk                    \r\n#define GPIO_LCKR_LCK1_Pos               (1U)                                  \r\n#define GPIO_LCKR_LCK1_Msk               (0x1U << GPIO_LCKR_LCK1_Pos)          /*!< 0x00000002 */\r\n#define GPIO_LCKR_LCK1                   GPIO_LCKR_LCK1_Msk                    \r\n#define GPIO_LCKR_LCK2_Pos               (2U)                                  \r\n#define GPIO_LCKR_LCK2_Msk               (0x1U << GPIO_LCKR_LCK2_Pos)          /*!< 0x00000004 */\r\n#define GPIO_LCKR_LCK2                   GPIO_LCKR_LCK2_Msk                    \r\n#define GPIO_LCKR_LCK3_Pos               (3U)                                  \r\n#define GPIO_LCKR_LCK3_Msk               (0x1U << GPIO_LCKR_LCK3_Pos)          /*!< 0x00000008 */\r\n#define GPIO_LCKR_LCK3                   GPIO_LCKR_LCK3_Msk                    \r\n#define GPIO_LCKR_LCK4_Pos               (4U)                                  \r\n#define GPIO_LCKR_LCK4_Msk               (0x1U << GPIO_LCKR_LCK4_Pos)          /*!< 0x00000010 */\r\n#define GPIO_LCKR_LCK4                   GPIO_LCKR_LCK4_Msk                    \r\n#define GPIO_LCKR_LCK5_Pos               (5U)                                  \r\n#define GPIO_LCKR_LCK5_Msk               (0x1U << GPIO_LCKR_LCK5_Pos)          /*!< 0x00000020 */\r\n#define GPIO_LCKR_LCK5                   GPIO_LCKR_LCK5_Msk                    \r\n#define GPIO_LCKR_LCK6_Pos               (6U)                                  \r\n#define GPIO_LCKR_LCK6_Msk               (0x1U << GPIO_LCKR_LCK6_Pos)          /*!< 0x00000040 */\r\n#define GPIO_LCKR_LCK6                   GPIO_LCKR_LCK6_Msk                    \r\n#define GPIO_LCKR_LCK7_Pos               (7U)                                  \r\n#define GPIO_LCKR_LCK7_Msk               (0x1U << GPIO_LCKR_LCK7_Pos)          /*!< 0x00000080 */\r\n#define GPIO_LCKR_LCK7                   GPIO_LCKR_LCK7_Msk                    \r\n#define GPIO_LCKR_LCK8_Pos               (8U)                                  \r\n#define GPIO_LCKR_LCK8_Msk               (0x1U << GPIO_LCKR_LCK8_Pos)          /*!< 0x00000100 */\r\n#define GPIO_LCKR_LCK8                   GPIO_LCKR_LCK8_Msk                    \r\n#define GPIO_LCKR_LCK9_Pos               (9U)                                  \r\n#define GPIO_LCKR_LCK9_Msk               (0x1U << GPIO_LCKR_LCK9_Pos)          /*!< 0x00000200 */\r\n#define GPIO_LCKR_LCK9                   GPIO_LCKR_LCK9_Msk                    \r\n#define GPIO_LCKR_LCK10_Pos              (10U)                                 \r\n#define GPIO_LCKR_LCK10_Msk              (0x1U << GPIO_LCKR_LCK10_Pos)         /*!< 0x00000400 */\r\n#define GPIO_LCKR_LCK10                  GPIO_LCKR_LCK10_Msk                   \r\n#define GPIO_LCKR_LCK11_Pos              (11U)                                 \r\n#define GPIO_LCKR_LCK11_Msk              (0x1U << GPIO_LCKR_LCK11_Pos)         /*!< 0x00000800 */\r\n#define GPIO_LCKR_LCK11                  GPIO_LCKR_LCK11_Msk                   \r\n#define GPIO_LCKR_LCK12_Pos              (12U)                                 \r\n#define GPIO_LCKR_LCK12_Msk              (0x1U << GPIO_LCKR_LCK12_Pos)         /*!< 0x00001000 */\r\n#define GPIO_LCKR_LCK12                  GPIO_LCKR_LCK12_Msk                   \r\n#define GPIO_LCKR_LCK13_Pos              (13U)                                 \r\n#define GPIO_LCKR_LCK13_Msk              (0x1U << GPIO_LCKR_LCK13_Pos)         /*!< 0x00002000 */\r\n#define GPIO_LCKR_LCK13                  GPIO_LCKR_LCK13_Msk                   \r\n#define GPIO_LCKR_LCK14_Pos              (14U)                                 \r\n#define GPIO_LCKR_LCK14_Msk              (0x1U << GPIO_LCKR_LCK14_Pos)         /*!< 0x00004000 */\r\n#define GPIO_LCKR_LCK14                  GPIO_LCKR_LCK14_Msk                   \r\n#define GPIO_LCKR_LCK15_Pos              (15U)                                 \r\n#define GPIO_LCKR_LCK15_Msk              (0x1U << GPIO_LCKR_LCK15_Pos)         /*!< 0x00008000 */\r\n#define GPIO_LCKR_LCK15                  GPIO_LCKR_LCK15_Msk                   \r\n#define GPIO_LCKR_LCKK_Pos               (16U)                                 \r\n#define GPIO_LCKR_LCKK_Msk               (0x1U << GPIO_LCKR_LCKK_Pos)          /*!< 0x00010000 */\r\n#define GPIO_LCKR_LCKK                   GPIO_LCKR_LCKK_Msk                    \r\n\r\n/****************** Bit definition for GPIO_AFRL register *********************/\r\n#define GPIO_AFRL_AFRL0_Pos              (0U)                                  \r\n#define GPIO_AFRL_AFRL0_Msk              (0xFU << GPIO_AFRL_AFRL0_Pos)         /*!< 0x0000000F */\r\n#define GPIO_AFRL_AFRL0                  GPIO_AFRL_AFRL0_Msk                   \r\n#define GPIO_AFRL_AFRL0_0                (0x1U << GPIO_AFRL_AFRL0_Pos)         /*!< 0x00000001 */\r\n#define GPIO_AFRL_AFRL0_1                (0x2U << GPIO_AFRL_AFRL0_Pos)         /*!< 0x00000002 */\r\n#define GPIO_AFRL_AFRL0_2                (0x4U << GPIO_AFRL_AFRL0_Pos)         /*!< 0x00000004 */\r\n#define GPIO_AFRL_AFRL0_3                (0x8U << GPIO_AFRL_AFRL0_Pos)         /*!< 0x00000008 */\r\n#define GPIO_AFRL_AFRL1_Pos              (4U)                                  \r\n#define GPIO_AFRL_AFRL1_Msk              (0xFU << GPIO_AFRL_AFRL1_Pos)         /*!< 0x000000F0 */\r\n#define GPIO_AFRL_AFRL1                  GPIO_AFRL_AFRL1_Msk                   \r\n#define GPIO_AFRL_AFRL1_0                (0x1U << GPIO_AFRL_AFRL1_Pos)         /*!< 0x00000010 */\r\n#define GPIO_AFRL_AFRL1_1                (0x2U << GPIO_AFRL_AFRL1_Pos)         /*!< 0x00000020 */\r\n#define GPIO_AFRL_AFRL1_2                (0x4U << GPIO_AFRL_AFRL1_Pos)         /*!< 0x00000040 */\r\n#define GPIO_AFRL_AFRL1_3                (0x8U << GPIO_AFRL_AFRL1_Pos)         /*!< 0x00000080 */\r\n#define GPIO_AFRL_AFRL2_Pos              (8U)                                  \r\n#define GPIO_AFRL_AFRL2_Msk              (0xFU << GPIO_AFRL_AFRL2_Pos)         /*!< 0x00000F00 */\r\n#define GPIO_AFRL_AFRL2                  GPIO_AFRL_AFRL2_Msk                   \r\n#define GPIO_AFRL_AFRL2_0                (0x1U << GPIO_AFRL_AFRL2_Pos)         /*!< 0x00000100 */\r\n#define GPIO_AFRL_AFRL2_1                (0x2U << GPIO_AFRL_AFRL2_Pos)         /*!< 0x00000200 */\r\n#define GPIO_AFRL_AFRL2_2                (0x4U << GPIO_AFRL_AFRL2_Pos)         /*!< 0x00000400 */\r\n#define GPIO_AFRL_AFRL2_3                (0x8U << GPIO_AFRL_AFRL2_Pos)         /*!< 0x00000800 */\r\n#define GPIO_AFRL_AFRL3_Pos              (12U)                                 \r\n#define GPIO_AFRL_AFRL3_Msk              (0xFU << GPIO_AFRL_AFRL3_Pos)         /*!< 0x0000F000 */\r\n#define GPIO_AFRL_AFRL3                  GPIO_AFRL_AFRL3_Msk                   \r\n#define GPIO_AFRL_AFRL3_0                (0x1U << GPIO_AFRL_AFRL3_Pos)         /*!< 0x00001000 */\r\n#define GPIO_AFRL_AFRL3_1                (0x2U << GPIO_AFRL_AFRL3_Pos)         /*!< 0x00002000 */\r\n#define GPIO_AFRL_AFRL3_2                (0x4U << GPIO_AFRL_AFRL3_Pos)         /*!< 0x00004000 */\r\n#define GPIO_AFRL_AFRL3_3                (0x8U << GPIO_AFRL_AFRL3_Pos)         /*!< 0x00008000 */\r\n#define GPIO_AFRL_AFRL4_Pos              (16U)                                 \r\n#define GPIO_AFRL_AFRL4_Msk              (0xFU << GPIO_AFRL_AFRL4_Pos)         /*!< 0x000F0000 */\r\n#define GPIO_AFRL_AFRL4                  GPIO_AFRL_AFRL4_Msk                   \r\n#define GPIO_AFRL_AFRL4_0                (0x1U << GPIO_AFRL_AFRL4_Pos)         /*!< 0x00010000 */\r\n#define GPIO_AFRL_AFRL4_1                (0x2U << GPIO_AFRL_AFRL4_Pos)         /*!< 0x00020000 */\r\n#define GPIO_AFRL_AFRL4_2                (0x4U << GPIO_AFRL_AFRL4_Pos)         /*!< 0x00040000 */\r\n#define GPIO_AFRL_AFRL4_3                (0x8U << GPIO_AFRL_AFRL4_Pos)         /*!< 0x00080000 */\r\n#define GPIO_AFRL_AFRL5_Pos              (20U)                                 \r\n#define GPIO_AFRL_AFRL5_Msk              (0xFU << GPIO_AFRL_AFRL5_Pos)         /*!< 0x00F00000 */\r\n#define GPIO_AFRL_AFRL5                  GPIO_AFRL_AFRL5_Msk                   \r\n#define GPIO_AFRL_AFRL5_0                (0x1U << GPIO_AFRL_AFRL5_Pos)         /*!< 0x00100000 */\r\n#define GPIO_AFRL_AFRL5_1                (0x2U << GPIO_AFRL_AFRL5_Pos)         /*!< 0x00200000 */\r\n#define GPIO_AFRL_AFRL5_2                (0x4U << GPIO_AFRL_AFRL5_Pos)         /*!< 0x00400000 */\r\n#define GPIO_AFRL_AFRL5_3                (0x8U << GPIO_AFRL_AFRL5_Pos)         /*!< 0x00800000 */\r\n#define GPIO_AFRL_AFRL6_Pos              (24U)                                 \r\n#define GPIO_AFRL_AFRL6_Msk              (0xFU << GPIO_AFRL_AFRL6_Pos)         /*!< 0x0F000000 */\r\n#define GPIO_AFRL_AFRL6                  GPIO_AFRL_AFRL6_Msk                   \r\n#define GPIO_AFRL_AFRL6_0                (0x1U << GPIO_AFRL_AFRL6_Pos)         /*!< 0x01000000 */\r\n#define GPIO_AFRL_AFRL6_1                (0x2U << GPIO_AFRL_AFRL6_Pos)         /*!< 0x02000000 */\r\n#define GPIO_AFRL_AFRL6_2                (0x4U << GPIO_AFRL_AFRL6_Pos)         /*!< 0x04000000 */\r\n#define GPIO_AFRL_AFRL6_3                (0x8U << GPIO_AFRL_AFRL6_Pos)         /*!< 0x08000000 */\r\n#define GPIO_AFRL_AFRL7_Pos              (28U)                                 \r\n#define GPIO_AFRL_AFRL7_Msk              (0xFU << GPIO_AFRL_AFRL7_Pos)         /*!< 0xF0000000 */\r\n#define GPIO_AFRL_AFRL7                  GPIO_AFRL_AFRL7_Msk                   \r\n#define GPIO_AFRL_AFRL7_0                (0x1U << GPIO_AFRL_AFRL7_Pos)         /*!< 0x10000000 */\r\n#define GPIO_AFRL_AFRL7_1                (0x2U << GPIO_AFRL_AFRL7_Pos)         /*!< 0x20000000 */\r\n#define GPIO_AFRL_AFRL7_2                (0x4U << GPIO_AFRL_AFRL7_Pos)         /*!< 0x40000000 */\r\n#define GPIO_AFRL_AFRL7_3                (0x8U << GPIO_AFRL_AFRL7_Pos)         /*!< 0x80000000 */\r\n\r\n/****************** Bit definition for GPIO_AFRH register *********************/\r\n#define GPIO_AFRH_AFRH0_Pos              (0U)                                  \r\n#define GPIO_AFRH_AFRH0_Msk              (0xFU << GPIO_AFRH_AFRH0_Pos)         /*!< 0x0000000F */\r\n#define GPIO_AFRH_AFRH0                  GPIO_AFRH_AFRH0_Msk                   \r\n#define GPIO_AFRH_AFRH0_0                (0x1U << GPIO_AFRH_AFRH0_Pos)         /*!< 0x00000001 */\r\n#define GPIO_AFRH_AFRH0_1                (0x2U << GPIO_AFRH_AFRH0_Pos)         /*!< 0x00000002 */\r\n#define GPIO_AFRH_AFRH0_2                (0x4U << GPIO_AFRH_AFRH0_Pos)         /*!< 0x00000004 */\r\n#define GPIO_AFRH_AFRH0_3                (0x8U << GPIO_AFRH_AFRH0_Pos)         /*!< 0x00000008 */\r\n#define GPIO_AFRH_AFRH1_Pos              (4U)                                  \r\n#define GPIO_AFRH_AFRH1_Msk              (0xFU << GPIO_AFRH_AFRH1_Pos)         /*!< 0x000000F0 */\r\n#define GPIO_AFRH_AFRH1                  GPIO_AFRH_AFRH1_Msk                   \r\n#define GPIO_AFRH_AFRH1_0                (0x1U << GPIO_AFRH_AFRH1_Pos)         /*!< 0x00000010 */\r\n#define GPIO_AFRH_AFRH1_1                (0x2U << GPIO_AFRH_AFRH1_Pos)         /*!< 0x00000020 */\r\n#define GPIO_AFRH_AFRH1_2                (0x4U << GPIO_AFRH_AFRH1_Pos)         /*!< 0x00000040 */\r\n#define GPIO_AFRH_AFRH1_3                (0x8U << GPIO_AFRH_AFRH1_Pos)         /*!< 0x00000080 */\r\n#define GPIO_AFRH_AFRH2_Pos              (8U)                                  \r\n#define GPIO_AFRH_AFRH2_Msk              (0xFU << GPIO_AFRH_AFRH2_Pos)         /*!< 0x00000F00 */\r\n#define GPIO_AFRH_AFRH2                  GPIO_AFRH_AFRH2_Msk                   \r\n#define GPIO_AFRH_AFRH2_0                (0x1U << GPIO_AFRH_AFRH2_Pos)         /*!< 0x00000100 */\r\n#define GPIO_AFRH_AFRH2_1                (0x2U << GPIO_AFRH_AFRH2_Pos)         /*!< 0x00000200 */\r\n#define GPIO_AFRH_AFRH2_2                (0x4U << GPIO_AFRH_AFRH2_Pos)         /*!< 0x00000400 */\r\n#define GPIO_AFRH_AFRH2_3                (0x8U << GPIO_AFRH_AFRH2_Pos)         /*!< 0x00000800 */\r\n#define GPIO_AFRH_AFRH3_Pos              (12U)                                 \r\n#define GPIO_AFRH_AFRH3_Msk              (0xFU << GPIO_AFRH_AFRH3_Pos)         /*!< 0x0000F000 */\r\n#define GPIO_AFRH_AFRH3                  GPIO_AFRH_AFRH3_Msk                   \r\n#define GPIO_AFRH_AFRH3_0                (0x1U << GPIO_AFRH_AFRH3_Pos)         /*!< 0x00001000 */\r\n#define GPIO_AFRH_AFRH3_1                (0x2U << GPIO_AFRH_AFRH3_Pos)         /*!< 0x00002000 */\r\n#define GPIO_AFRH_AFRH3_2                (0x4U << GPIO_AFRH_AFRH3_Pos)         /*!< 0x00004000 */\r\n#define GPIO_AFRH_AFRH3_3                (0x8U << GPIO_AFRH_AFRH3_Pos)         /*!< 0x00008000 */\r\n#define GPIO_AFRH_AFRH4_Pos              (16U)                                 \r\n#define GPIO_AFRH_AFRH4_Msk              (0xFU << GPIO_AFRH_AFRH4_Pos)         /*!< 0x000F0000 */\r\n#define GPIO_AFRH_AFRH4                  GPIO_AFRH_AFRH4_Msk                   \r\n#define GPIO_AFRH_AFRH4_0                (0x1U << GPIO_AFRH_AFRH4_Pos)         /*!< 0x00010000 */\r\n#define GPIO_AFRH_AFRH4_1                (0x2U << GPIO_AFRH_AFRH4_Pos)         /*!< 0x00020000 */\r\n#define GPIO_AFRH_AFRH4_2                (0x4U << GPIO_AFRH_AFRH4_Pos)         /*!< 0x00040000 */\r\n#define GPIO_AFRH_AFRH4_3                (0x8U << GPIO_AFRH_AFRH4_Pos)         /*!< 0x00080000 */\r\n#define GPIO_AFRH_AFRH5_Pos              (20U)                                 \r\n#define GPIO_AFRH_AFRH5_Msk              (0xFU << GPIO_AFRH_AFRH5_Pos)         /*!< 0x00F00000 */\r\n#define GPIO_AFRH_AFRH5                  GPIO_AFRH_AFRH5_Msk                   \r\n#define GPIO_AFRH_AFRH5_0                (0x1U << GPIO_AFRH_AFRH5_Pos)         /*!< 0x00100000 */\r\n#define GPIO_AFRH_AFRH5_1                (0x2U << GPIO_AFRH_AFRH5_Pos)         /*!< 0x00200000 */\r\n#define GPIO_AFRH_AFRH5_2                (0x4U << GPIO_AFRH_AFRH5_Pos)         /*!< 0x00400000 */\r\n#define GPIO_AFRH_AFRH5_3                (0x8U << GPIO_AFRH_AFRH5_Pos)         /*!< 0x00800000 */\r\n#define GPIO_AFRH_AFRH6_Pos              (24U)                                 \r\n#define GPIO_AFRH_AFRH6_Msk              (0xFU << GPIO_AFRH_AFRH6_Pos)         /*!< 0x0F000000 */\r\n#define GPIO_AFRH_AFRH6                  GPIO_AFRH_AFRH6_Msk                   \r\n#define GPIO_AFRH_AFRH6_0                (0x1U << GPIO_AFRH_AFRH6_Pos)         /*!< 0x01000000 */\r\n#define GPIO_AFRH_AFRH6_1                (0x2U << GPIO_AFRH_AFRH6_Pos)         /*!< 0x02000000 */\r\n#define GPIO_AFRH_AFRH6_2                (0x4U << GPIO_AFRH_AFRH6_Pos)         /*!< 0x04000000 */\r\n#define GPIO_AFRH_AFRH6_3                (0x8U << GPIO_AFRH_AFRH6_Pos)         /*!< 0x08000000 */\r\n#define GPIO_AFRH_AFRH7_Pos              (28U)                                 \r\n#define GPIO_AFRH_AFRH7_Msk              (0xFU << GPIO_AFRH_AFRH7_Pos)         /*!< 0xF0000000 */\r\n#define GPIO_AFRH_AFRH7                  GPIO_AFRH_AFRH7_Msk                   \r\n#define GPIO_AFRH_AFRH7_0                (0x1U << GPIO_AFRH_AFRH7_Pos)         /*!< 0x10000000 */\r\n#define GPIO_AFRH_AFRH7_1                (0x2U << GPIO_AFRH_AFRH7_Pos)         /*!< 0x20000000 */\r\n#define GPIO_AFRH_AFRH7_2                (0x4U << GPIO_AFRH_AFRH7_Pos)         /*!< 0x40000000 */\r\n#define GPIO_AFRH_AFRH7_3                (0x8U << GPIO_AFRH_AFRH7_Pos)         /*!< 0x80000000 */\r\n\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                      Inter-integrated Circuit Interface (I2C)              */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************  Bit definition for I2C_CR1 register  *******************/\r\n#define I2C_CR1_PE_Pos               (0U)                                      \r\n#define I2C_CR1_PE_Msk               (0x1U << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */\r\n#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable                   */\r\n#define I2C_CR1_TXIE_Pos             (1U)                                      \r\n#define I2C_CR1_TXIE_Msk             (0x1U << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */\r\n#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable                 */\r\n#define I2C_CR1_RXIE_Pos             (2U)                                      \r\n#define I2C_CR1_RXIE_Msk             (0x1U << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */\r\n#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable                 */\r\n#define I2C_CR1_ADDRIE_Pos           (3U)                                      \r\n#define I2C_CR1_ADDRIE_Msk           (0x1U << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */\r\n#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable      */\r\n#define I2C_CR1_NACKIE_Pos           (4U)                                      \r\n#define I2C_CR1_NACKIE_Msk           (0x1U << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */\r\n#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable      */\r\n#define I2C_CR1_STOPIE_Pos           (5U)                                      \r\n#define I2C_CR1_STOPIE_Msk           (0x1U << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */\r\n#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable     */\r\n#define I2C_CR1_TCIE_Pos             (6U)                                      \r\n#define I2C_CR1_TCIE_Msk             (0x1U << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */\r\n#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable  */\r\n#define I2C_CR1_ERRIE_Pos            (7U)                                      \r\n#define I2C_CR1_ERRIE_Msk            (0x1U << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */\r\n#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable             */\r\n#define I2C_CR1_DNF_Pos              (8U)                                      \r\n#define I2C_CR1_DNF_Msk              (0xFU << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */\r\n#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter                */\r\n#define I2C_CR1_ANFOFF_Pos           (12U)                                     \r\n#define I2C_CR1_ANFOFF_Msk           (0x1U << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */\r\n#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF             */\r\n#define I2C_CR1_TXDMAEN_Pos          (14U)                                     \r\n#define I2C_CR1_TXDMAEN_Msk          (0x1U << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */\r\n#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable    */\r\n#define I2C_CR1_RXDMAEN_Pos          (15U)                                     \r\n#define I2C_CR1_RXDMAEN_Msk          (0x1U << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */\r\n#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable       */\r\n#define I2C_CR1_SBC_Pos              (16U)                                     \r\n#define I2C_CR1_SBC_Msk              (0x1U << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */\r\n#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control                  */\r\n#define I2C_CR1_NOSTRETCH_Pos        (17U)                                     \r\n#define I2C_CR1_NOSTRETCH_Msk        (0x1U << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */\r\n#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable            */\r\n#define I2C_CR1_GCEN_Pos             (19U)                                     \r\n#define I2C_CR1_GCEN_Msk             (0x1U << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */\r\n#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable                 */\r\n#define I2C_CR1_SMBHEN_Pos           (20U)                                     \r\n#define I2C_CR1_SMBHEN_Msk           (0x1U << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */\r\n#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable           */\r\n#define I2C_CR1_SMBDEN_Pos           (21U)                                     \r\n#define I2C_CR1_SMBDEN_Msk           (0x1U << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */\r\n#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */\r\n#define I2C_CR1_ALERTEN_Pos          (22U)                                     \r\n#define I2C_CR1_ALERTEN_Msk          (0x1U << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */\r\n#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable                  */\r\n#define I2C_CR1_PECEN_Pos            (23U)                                     \r\n#define I2C_CR1_PECEN_Msk            (0x1U << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */\r\n#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable                          */\r\n\r\n/* Legacy define */\r\n#define  I2C_CR1_DFN                         I2C_CR1_DNF                   /*!< Digital noise filter                */\r\n\r\n/******************  Bit definition for I2C_CR2 register  ********************/\r\n#define I2C_CR2_SADD_Pos             (0U)                                      \r\n#define I2C_CR2_SADD_Msk             (0x3FFU << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */\r\n#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode)                             */\r\n#define I2C_CR2_RD_WRN_Pos           (10U)                                     \r\n#define I2C_CR2_RD_WRN_Msk           (0x1U << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */\r\n#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode)                        */\r\n#define I2C_CR2_ADD10_Pos            (11U)                                     \r\n#define I2C_CR2_ADD10_Msk            (0x1U << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */\r\n#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode)                    */\r\n#define I2C_CR2_HEAD10R_Pos          (12U)                                     \r\n#define I2C_CR2_HEAD10R_Msk          (0x1U << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */\r\n#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */\r\n#define I2C_CR2_START_Pos            (13U)                                     \r\n#define I2C_CR2_START_Msk            (0x1U << I2C_CR2_START_Pos)               /*!< 0x00002000 */\r\n#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation                                        */\r\n#define I2C_CR2_STOP_Pos             (14U)                                     \r\n#define I2C_CR2_STOP_Msk             (0x1U << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */\r\n#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode)                           */\r\n#define I2C_CR2_NACK_Pos             (15U)                                     \r\n#define I2C_CR2_NACK_Msk             (0x1U << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */\r\n#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode)                            */\r\n#define I2C_CR2_NBYTES_Pos           (16U)                                     \r\n#define I2C_CR2_NBYTES_Msk           (0xFFU << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */\r\n#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes                                         */\r\n#define I2C_CR2_RELOAD_Pos           (24U)                                     \r\n#define I2C_CR2_RELOAD_Msk           (0x1U << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */\r\n#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode                                      */\r\n#define I2C_CR2_AUTOEND_Pos          (25U)                                     \r\n#define I2C_CR2_AUTOEND_Msk          (0x1U << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */\r\n#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode)                        */\r\n#define I2C_CR2_PECBYTE_Pos          (26U)                                     \r\n#define I2C_CR2_PECBYTE_Msk          (0x1U << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */\r\n#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte                              */\r\n\r\n/*******************  Bit definition for I2C_OAR1 register  ******************/\r\n#define I2C_OAR1_OA1_Pos             (0U)                                      \r\n#define I2C_OAR1_OA1_Msk             (0x3FFU << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */\r\n#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1   */\r\n#define I2C_OAR1_OA1MODE_Pos         (10U)                                     \r\n#define I2C_OAR1_OA1MODE_Msk         (0x1U << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */\r\n#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */\r\n#define I2C_OAR1_OA1EN_Pos           (15U)                                     \r\n#define I2C_OAR1_OA1EN_Msk           (0x1U << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */\r\n#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable      */\r\n\r\n/*******************  Bit definition for I2C_OAR2 register  ******************/\r\n#define I2C_OAR2_OA2_Pos             (1U)                                      \r\n#define I2C_OAR2_OA2_Msk             (0x7FU << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */\r\n#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */\r\n#define I2C_OAR2_OA2MSK_Pos          (8U)                                      \r\n#define I2C_OAR2_OA2MSK_Msk          (0x7U << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */\r\n#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks     */\r\n#define I2C_OAR2_OA2NOMASK           0x00000000U                               /*!< No mask */\r\n#define I2C_OAR2_OA2MASK01_Pos       (8U)                                      \r\n#define I2C_OAR2_OA2MASK01_Msk       (0x1U << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */\r\n#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared */\r\n#define I2C_OAR2_OA2MASK02_Pos       (9U)                                      \r\n#define I2C_OAR2_OA2MASK02_Msk       (0x1U << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */\r\n#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */\r\n#define I2C_OAR2_OA2MASK03_Pos       (8U)                                      \r\n#define I2C_OAR2_OA2MASK03_Msk       (0x3U << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */\r\n#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */\r\n#define I2C_OAR2_OA2MASK04_Pos       (10U)                                     \r\n#define I2C_OAR2_OA2MASK04_Msk       (0x1U << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */\r\n#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */\r\n#define I2C_OAR2_OA2MASK05_Pos       (8U)                                      \r\n#define I2C_OAR2_OA2MASK05_Msk       (0x5U << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */\r\n#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */\r\n#define I2C_OAR2_OA2MASK06_Pos       (9U)                                      \r\n#define I2C_OAR2_OA2MASK06_Msk       (0x3U << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */\r\n#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared */\r\n#define I2C_OAR2_OA2MASK07_Pos       (8U)                                      \r\n#define I2C_OAR2_OA2MASK07_Msk       (0x7U << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */\r\n#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done */\r\n#define I2C_OAR2_OA2EN_Pos           (15U)                                     \r\n#define I2C_OAR2_OA2EN_Msk           (0x1U << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */\r\n#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable    */\r\n\r\n/*******************  Bit definition for I2C_TIMINGR register *******************/\r\n#define I2C_TIMINGR_SCLL_Pos         (0U)                                      \r\n#define I2C_TIMINGR_SCLL_Msk         (0xFFU << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */\r\n#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode)  */\r\n#define I2C_TIMINGR_SCLH_Pos         (8U)                                      \r\n#define I2C_TIMINGR_SCLH_Msk         (0xFFU << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */\r\n#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */\r\n#define I2C_TIMINGR_SDADEL_Pos       (16U)                                     \r\n#define I2C_TIMINGR_SDADEL_Msk       (0xFU << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */\r\n#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time                */\r\n#define I2C_TIMINGR_SCLDEL_Pos       (20U)                                     \r\n#define I2C_TIMINGR_SCLDEL_Msk       (0xFU << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */\r\n#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time               */\r\n#define I2C_TIMINGR_PRESC_Pos        (28U)                                     \r\n#define I2C_TIMINGR_PRESC_Msk        (0xFU << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */\r\n#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler             */\r\n\r\n/******************* Bit definition for I2C_TIMEOUTR register *******************/\r\n#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)                                      \r\n#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */\r\n#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A                 */\r\n#define I2C_TIMEOUTR_TIDLE_Pos       (12U)                                     \r\n#define I2C_TIMEOUTR_TIDLE_Msk       (0x1U << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */\r\n#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection  */\r\n#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)                                     \r\n#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */\r\n#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable          */\r\n#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)                                     \r\n#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */\r\n#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B                 */\r\n#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)                                     \r\n#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1U << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */\r\n#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */\r\n\r\n/******************  Bit definition for I2C_ISR register  *********************/\r\n#define I2C_ISR_TXE_Pos              (0U)                                      \r\n#define I2C_ISR_TXE_Msk              (0x1U << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */\r\n#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty    */\r\n#define I2C_ISR_TXIS_Pos             (1U)                                      \r\n#define I2C_ISR_TXIS_Msk             (0x1U << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */\r\n#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status       */\r\n#define I2C_ISR_RXNE_Pos             (2U)                                      \r\n#define I2C_ISR_RXNE_Msk             (0x1U << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */\r\n#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */\r\n#define I2C_ISR_ADDR_Pos             (3U)                                      \r\n#define I2C_ISR_ADDR_Msk             (0x1U << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */\r\n#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)    */\r\n#define I2C_ISR_NACKF_Pos            (4U)                                      \r\n#define I2C_ISR_NACKF_Msk            (0x1U << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */\r\n#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag              */\r\n#define I2C_ISR_STOPF_Pos            (5U)                                      \r\n#define I2C_ISR_STOPF_Msk            (0x1U << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */\r\n#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag             */\r\n#define I2C_ISR_TC_Pos               (6U)                                      \r\n#define I2C_ISR_TC_Msk               (0x1U << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */\r\n#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */\r\n#define I2C_ISR_TCR_Pos              (7U)                                      \r\n#define I2C_ISR_TCR_Msk              (0x1U << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */\r\n#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload        */\r\n#define I2C_ISR_BERR_Pos             (8U)                                      \r\n#define I2C_ISR_BERR_Msk             (0x1U << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */\r\n#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error                       */\r\n#define I2C_ISR_ARLO_Pos             (9U)                                      \r\n#define I2C_ISR_ARLO_Msk             (0x1U << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */\r\n#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost                */\r\n#define I2C_ISR_OVR_Pos              (10U)                                     \r\n#define I2C_ISR_OVR_Msk              (0x1U << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */\r\n#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun                */\r\n#define I2C_ISR_PECERR_Pos           (11U)                                     \r\n#define I2C_ISR_PECERR_Msk           (0x1U << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */\r\n#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception          */\r\n#define I2C_ISR_TIMEOUT_Pos          (12U)                                     \r\n#define I2C_ISR_TIMEOUT_Msk          (0x1U << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */\r\n#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag  */\r\n#define I2C_ISR_ALERT_Pos            (13U)                                     \r\n#define I2C_ISR_ALERT_Msk            (0x1U << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */\r\n#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert                     */\r\n#define I2C_ISR_BUSY_Pos             (15U)                                     \r\n#define I2C_ISR_BUSY_Msk             (0x1U << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */\r\n#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy                        */\r\n#define I2C_ISR_DIR_Pos              (16U)                                     \r\n#define I2C_ISR_DIR_Msk              (0x1U << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */\r\n#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */\r\n#define I2C_ISR_ADDCODE_Pos          (17U)                                     \r\n#define I2C_ISR_ADDCODE_Msk          (0x7FU << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */\r\n#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */\r\n\r\n/******************  Bit definition for I2C_ICR register  *********************/\r\n#define I2C_ICR_ADDRCF_Pos           (3U)                                      \r\n#define I2C_ICR_ADDRCF_Msk           (0x1U << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */\r\n#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag      */\r\n#define I2C_ICR_NACKCF_Pos           (4U)                                      \r\n#define I2C_ICR_NACKCF_Msk           (0x1U << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */\r\n#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag                 */\r\n#define I2C_ICR_STOPCF_Pos           (5U)                                      \r\n#define I2C_ICR_STOPCF_Msk           (0x1U << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */\r\n#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag       */\r\n#define I2C_ICR_BERRCF_Pos           (8U)                                      \r\n#define I2C_ICR_BERRCF_Msk           (0x1U << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */\r\n#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag            */\r\n#define I2C_ICR_ARLOCF_Pos           (9U)                                      \r\n#define I2C_ICR_ARLOCF_Msk           (0x1U << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */\r\n#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag     */\r\n#define I2C_ICR_OVRCF_Pos            (10U)                                     \r\n#define I2C_ICR_OVRCF_Msk            (0x1U << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */\r\n#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag     */\r\n#define I2C_ICR_PECCF_Pos            (11U)                                     \r\n#define I2C_ICR_PECCF_Msk            (0x1U << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */\r\n#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag            */\r\n#define I2C_ICR_TIMOUTCF_Pos         (12U)                                     \r\n#define I2C_ICR_TIMOUTCF_Msk         (0x1U << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */\r\n#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag              */\r\n#define I2C_ICR_ALERTCF_Pos          (13U)                                     \r\n#define I2C_ICR_ALERTCF_Msk          (0x1U << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */\r\n#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag                */\r\n\r\n/******************  Bit definition for I2C_PECR register  *********************/\r\n#define I2C_PECR_PEC_Pos             (0U)                                      \r\n#define I2C_PECR_PEC_Msk             (0xFFU << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */\r\n#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register        */\r\n\r\n/******************  Bit definition for I2C_RXDR register  *********************/\r\n#define I2C_RXDR_RXDATA_Pos          (0U)                                      \r\n#define I2C_RXDR_RXDATA_Msk          (0xFFU << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */\r\n#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data  */\r\n\r\n/******************  Bit definition for I2C_TXDR register  *********************/\r\n#define I2C_TXDR_TXDATA_Pos          (0U)                                      \r\n#define I2C_TXDR_TXDATA_Msk          (0xFFU << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */\r\n#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */\r\n\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                           Independent WATCHDOG                             */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************  Bit definition for IWDG_KR register  ********************/\r\n#define IWDG_KR_KEY_Pos      (0U)                                              \r\n#define IWDG_KR_KEY_Msk      (0xFFFFU << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */\r\n#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */\r\n\r\n/*******************  Bit definition for IWDG_PR register  ********************/\r\n#define IWDG_PR_PR_Pos       (0U)                                              \r\n#define IWDG_PR_PR_Msk       (0x7U << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */\r\n#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */\r\n#define IWDG_PR_PR_0         (0x1U << IWDG_PR_PR_Pos)                          /*!< 0x01 */\r\n#define IWDG_PR_PR_1         (0x2U << IWDG_PR_PR_Pos)                          /*!< 0x02 */\r\n#define IWDG_PR_PR_2         (0x4U << IWDG_PR_PR_Pos)                          /*!< 0x04 */\r\n\r\n/*******************  Bit definition for IWDG_RLR register  *******************/\r\n#define IWDG_RLR_RL_Pos      (0U)                                              \r\n#define IWDG_RLR_RL_Msk      (0xFFFU << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */\r\n#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */\r\n\r\n/*******************  Bit definition for IWDG_SR register  ********************/\r\n#define IWDG_SR_PVU_Pos      (0U)                                              \r\n#define IWDG_SR_PVU_Msk      (0x1U << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */\r\n#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */\r\n#define IWDG_SR_RVU_Pos      (1U)                                              \r\n#define IWDG_SR_RVU_Msk      (0x1U << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */\r\n#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */\r\n#define IWDG_SR_WVU_Pos      (2U)                                              \r\n#define IWDG_SR_WVU_Msk      (0x1U << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */\r\n#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */\r\n\r\n/*******************  Bit definition for IWDG_KR register  ********************/\r\n#define IWDG_WINR_WIN_Pos    (0U)                                              \r\n#define IWDG_WINR_WIN_Msk    (0xFFFU << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */\r\n#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                      LCD-TFT Display Controller (LTDC)                     */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n\r\n/********************  Bit definition for LTDC_SSCR register  *****************/\r\n\r\n#define LTDC_SSCR_VSH_Pos            (0U)                                      \r\n#define LTDC_SSCR_VSH_Msk            (0x7FFU << LTDC_SSCR_VSH_Pos)             /*!< 0x000007FF */\r\n#define LTDC_SSCR_VSH                LTDC_SSCR_VSH_Msk                         /*!< Vertical Synchronization Height  */\r\n#define LTDC_SSCR_HSW_Pos            (16U)                                     \r\n#define LTDC_SSCR_HSW_Msk            (0xFFFU << LTDC_SSCR_HSW_Pos)             /*!< 0x0FFF0000 */\r\n#define LTDC_SSCR_HSW                LTDC_SSCR_HSW_Msk                         /*!< Horizontal Synchronization Width */\r\n\r\n/********************  Bit definition for LTDC_BPCR register  *****************/\r\n\r\n#define LTDC_BPCR_AVBP_Pos           (0U)                                      \r\n#define LTDC_BPCR_AVBP_Msk           (0x7FFU << LTDC_BPCR_AVBP_Pos)            /*!< 0x000007FF */\r\n#define LTDC_BPCR_AVBP               LTDC_BPCR_AVBP_Msk                        /*!< Accumulated Vertical Back Porch   */\r\n#define LTDC_BPCR_AHBP_Pos           (16U)                                     \r\n#define LTDC_BPCR_AHBP_Msk           (0xFFFU << LTDC_BPCR_AHBP_Pos)            /*!< 0x0FFF0000 */\r\n#define LTDC_BPCR_AHBP               LTDC_BPCR_AHBP_Msk                        /*!< Accumulated Horizontal Back Porch */\r\n\r\n/********************  Bit definition for LTDC_AWCR register  *****************/\r\n\r\n#define LTDC_AWCR_AAH_Pos            (0U)                                      \r\n#define LTDC_AWCR_AAH_Msk            (0x7FFU << LTDC_AWCR_AAH_Pos)             /*!< 0x000007FF */\r\n#define LTDC_AWCR_AAH                LTDC_AWCR_AAH_Msk                         /*!< Accumulated Active heigh */\r\n#define LTDC_AWCR_AAW_Pos            (16U)                                     \r\n#define LTDC_AWCR_AAW_Msk            (0xFFFU << LTDC_AWCR_AAW_Pos)             /*!< 0x0FFF0000 */\r\n#define LTDC_AWCR_AAW                LTDC_AWCR_AAW_Msk                         /*!< Accumulated Active Width */\r\n\r\n/********************  Bit definition for LTDC_TWCR register  *****************/\r\n\r\n#define LTDC_TWCR_TOTALH_Pos         (0U)                                      \r\n#define LTDC_TWCR_TOTALH_Msk         (0x7FFU << LTDC_TWCR_TOTALH_Pos)          /*!< 0x000007FF */\r\n#define LTDC_TWCR_TOTALH             LTDC_TWCR_TOTALH_Msk                      /*!< Total Heigh */\r\n#define LTDC_TWCR_TOTALW_Pos         (16U)                                     \r\n#define LTDC_TWCR_TOTALW_Msk         (0xFFFU << LTDC_TWCR_TOTALW_Pos)          /*!< 0x0FFF0000 */\r\n#define LTDC_TWCR_TOTALW             LTDC_TWCR_TOTALW_Msk                      /*!< Total Width */\r\n\r\n/********************  Bit definition for LTDC_GCR register  ******************/\r\n\r\n#define LTDC_GCR_LTDCEN_Pos          (0U)                                      \r\n#define LTDC_GCR_LTDCEN_Msk          (0x1U << LTDC_GCR_LTDCEN_Pos)             /*!< 0x00000001 */\r\n#define LTDC_GCR_LTDCEN              LTDC_GCR_LTDCEN_Msk                       /*!< LCD-TFT controller enable bit       */\r\n#define LTDC_GCR_DBW_Pos             (4U)                                      \r\n#define LTDC_GCR_DBW_Msk             (0x7U << LTDC_GCR_DBW_Pos)                /*!< 0x00000070 */\r\n#define LTDC_GCR_DBW                 LTDC_GCR_DBW_Msk                          /*!< Dither Blue Width                   */\r\n#define LTDC_GCR_DGW_Pos             (8U)                                      \r\n#define LTDC_GCR_DGW_Msk             (0x7U << LTDC_GCR_DGW_Pos)                /*!< 0x00000700 */\r\n#define LTDC_GCR_DGW                 LTDC_GCR_DGW_Msk                          /*!< Dither Green Width                  */\r\n#define LTDC_GCR_DRW_Pos             (12U)                                     \r\n#define LTDC_GCR_DRW_Msk             (0x7U << LTDC_GCR_DRW_Pos)                /*!< 0x00007000 */\r\n#define LTDC_GCR_DRW                 LTDC_GCR_DRW_Msk                          /*!< Dither Red Width                    */\r\n#define LTDC_GCR_DEN_Pos             (16U)                                     \r\n#define LTDC_GCR_DEN_Msk             (0x1U << LTDC_GCR_DEN_Pos)                /*!< 0x00010000 */\r\n#define LTDC_GCR_DEN                 LTDC_GCR_DEN_Msk                          /*!< Dither Enable                       */\r\n#define LTDC_GCR_PCPOL_Pos           (28U)                                     \r\n#define LTDC_GCR_PCPOL_Msk           (0x1U << LTDC_GCR_PCPOL_Pos)              /*!< 0x10000000 */\r\n#define LTDC_GCR_PCPOL               LTDC_GCR_PCPOL_Msk                        /*!< Pixel Clock Polarity                */\r\n#define LTDC_GCR_DEPOL_Pos           (29U)                                     \r\n#define LTDC_GCR_DEPOL_Msk           (0x1U << LTDC_GCR_DEPOL_Pos)              /*!< 0x20000000 */\r\n#define LTDC_GCR_DEPOL               LTDC_GCR_DEPOL_Msk                        /*!< Data Enable Polarity                */\r\n#define LTDC_GCR_VSPOL_Pos           (30U)                                     \r\n#define LTDC_GCR_VSPOL_Msk           (0x1U << LTDC_GCR_VSPOL_Pos)              /*!< 0x40000000 */\r\n#define LTDC_GCR_VSPOL               LTDC_GCR_VSPOL_Msk                        /*!< Vertical Synchronization Polarity   */\r\n#define LTDC_GCR_HSPOL_Pos           (31U)                                     \r\n#define LTDC_GCR_HSPOL_Msk           (0x1U << LTDC_GCR_HSPOL_Pos)              /*!< 0x80000000 */\r\n#define LTDC_GCR_HSPOL               LTDC_GCR_HSPOL_Msk                        /*!< Horizontal Synchronization Polarity */\r\n\r\n/* Legacy define */\r\n#define LTDC_GCR_DTEN                       LTDC_GCR_DEN\r\n\r\n/********************  Bit definition for LTDC_SRCR register  *****************/\r\n\r\n#define LTDC_SRCR_IMR_Pos            (0U)                                      \r\n#define LTDC_SRCR_IMR_Msk            (0x1U << LTDC_SRCR_IMR_Pos)               /*!< 0x00000001 */\r\n#define LTDC_SRCR_IMR                LTDC_SRCR_IMR_Msk                         /*!< Immediate Reload         */\r\n#define LTDC_SRCR_VBR_Pos            (1U)                                      \r\n#define LTDC_SRCR_VBR_Msk            (0x1U << LTDC_SRCR_VBR_Pos)               /*!< 0x00000002 */\r\n#define LTDC_SRCR_VBR                LTDC_SRCR_VBR_Msk                         /*!< Vertical Blanking Reload */\r\n\r\n/********************  Bit definition for LTDC_BCCR register  *****************/\r\n\r\n#define LTDC_BCCR_BCBLUE_Pos         (0U)                                      \r\n#define LTDC_BCCR_BCBLUE_Msk         (0xFFU << LTDC_BCCR_BCBLUE_Pos)           /*!< 0x000000FF */\r\n#define LTDC_BCCR_BCBLUE             LTDC_BCCR_BCBLUE_Msk                      /*!< Background Blue value  */\r\n#define LTDC_BCCR_BCGREEN_Pos        (8U)                                      \r\n#define LTDC_BCCR_BCGREEN_Msk        (0xFFU << LTDC_BCCR_BCGREEN_Pos)          /*!< 0x0000FF00 */\r\n#define LTDC_BCCR_BCGREEN            LTDC_BCCR_BCGREEN_Msk                     /*!< Background Green value */\r\n#define LTDC_BCCR_BCRED_Pos          (16U)                                     \r\n#define LTDC_BCCR_BCRED_Msk          (0xFFU << LTDC_BCCR_BCRED_Pos)            /*!< 0x00FF0000 */\r\n#define LTDC_BCCR_BCRED              LTDC_BCCR_BCRED_Msk                       /*!< Background Red value   */\r\n\r\n/********************  Bit definition for LTDC_IER register  ******************/\r\n\r\n#define LTDC_IER_LIE_Pos             (0U)                                      \r\n#define LTDC_IER_LIE_Msk             (0x1U << LTDC_IER_LIE_Pos)                /*!< 0x00000001 */\r\n#define LTDC_IER_LIE                 LTDC_IER_LIE_Msk                          /*!< Line Interrupt Enable            */\r\n#define LTDC_IER_FUIE_Pos            (1U)                                      \r\n#define LTDC_IER_FUIE_Msk            (0x1U << LTDC_IER_FUIE_Pos)               /*!< 0x00000002 */\r\n#define LTDC_IER_FUIE                LTDC_IER_FUIE_Msk                         /*!< FIFO Underrun Interrupt Enable   */\r\n#define LTDC_IER_TERRIE_Pos          (2U)                                      \r\n#define LTDC_IER_TERRIE_Msk          (0x1U << LTDC_IER_TERRIE_Pos)             /*!< 0x00000004 */\r\n#define LTDC_IER_TERRIE              LTDC_IER_TERRIE_Msk                       /*!< Transfer Error Interrupt Enable  */\r\n#define LTDC_IER_RRIE_Pos            (3U)                                      \r\n#define LTDC_IER_RRIE_Msk            (0x1U << LTDC_IER_RRIE_Pos)               /*!< 0x00000008 */\r\n#define LTDC_IER_RRIE                LTDC_IER_RRIE_Msk                         /*!< Register Reload interrupt enable */\r\n\r\n/********************  Bit definition for LTDC_ISR register  ******************/\r\n\r\n#define LTDC_ISR_LIF_Pos             (0U)                                      \r\n#define LTDC_ISR_LIF_Msk             (0x1U << LTDC_ISR_LIF_Pos)                /*!< 0x00000001 */\r\n#define LTDC_ISR_LIF                 LTDC_ISR_LIF_Msk                          /*!< Line Interrupt Flag */\r\n#define LTDC_ISR_FUIF_Pos            (1U)                                      \r\n#define LTDC_ISR_FUIF_Msk            (0x1U << LTDC_ISR_FUIF_Pos)               /*!< 0x00000002 */\r\n#define LTDC_ISR_FUIF                LTDC_ISR_FUIF_Msk                         /*!< FIFO Underrun Interrupt Flag */\r\n#define LTDC_ISR_TERRIF_Pos          (2U)                                      \r\n#define LTDC_ISR_TERRIF_Msk          (0x1U << LTDC_ISR_TERRIF_Pos)             /*!< 0x00000004 */\r\n#define LTDC_ISR_TERRIF              LTDC_ISR_TERRIF_Msk                       /*!< Transfer Error Interrupt Flag */\r\n#define LTDC_ISR_RRIF_Pos            (3U)                                      \r\n#define LTDC_ISR_RRIF_Msk            (0x1U << LTDC_ISR_RRIF_Pos)               /*!< 0x00000008 */\r\n#define LTDC_ISR_RRIF                LTDC_ISR_RRIF_Msk                         /*!< Register Reload interrupt Flag */\r\n\r\n/********************  Bit definition for LTDC_ICR register  ******************/\r\n\r\n#define LTDC_ICR_CLIF_Pos            (0U)                                      \r\n#define LTDC_ICR_CLIF_Msk            (0x1U << LTDC_ICR_CLIF_Pos)               /*!< 0x00000001 */\r\n#define LTDC_ICR_CLIF                LTDC_ICR_CLIF_Msk                         /*!< Clears the Line Interrupt Flag */\r\n#define LTDC_ICR_CFUIF_Pos           (1U)                                      \r\n#define LTDC_ICR_CFUIF_Msk           (0x1U << LTDC_ICR_CFUIF_Pos)              /*!< 0x00000002 */\r\n#define LTDC_ICR_CFUIF               LTDC_ICR_CFUIF_Msk                        /*!< Clears the FIFO Underrun Interrupt Flag */\r\n#define LTDC_ICR_CTERRIF_Pos         (2U)                                      \r\n#define LTDC_ICR_CTERRIF_Msk         (0x1U << LTDC_ICR_CTERRIF_Pos)            /*!< 0x00000004 */\r\n#define LTDC_ICR_CTERRIF             LTDC_ICR_CTERRIF_Msk                      /*!< Clears the Transfer Error Interrupt Flag */\r\n#define LTDC_ICR_CRRIF_Pos           (3U)                                      \r\n#define LTDC_ICR_CRRIF_Msk           (0x1U << LTDC_ICR_CRRIF_Pos)              /*!< 0x00000008 */\r\n#define LTDC_ICR_CRRIF               LTDC_ICR_CRRIF_Msk                        /*!< Clears Register Reload interrupt Flag */\r\n\r\n/********************  Bit definition for LTDC_LIPCR register  ****************/\r\n\r\n#define LTDC_LIPCR_LIPOS_Pos         (0U)                                      \r\n#define LTDC_LIPCR_LIPOS_Msk         (0x7FFU << LTDC_LIPCR_LIPOS_Pos)          /*!< 0x000007FF */\r\n#define LTDC_LIPCR_LIPOS             LTDC_LIPCR_LIPOS_Msk                      /*!< Line Interrupt Position */\r\n\r\n/********************  Bit definition for LTDC_CPSR register  *****************/\r\n\r\n#define LTDC_CPSR_CYPOS_Pos          (0U)                                      \r\n#define LTDC_CPSR_CYPOS_Msk          (0xFFFFU << LTDC_CPSR_CYPOS_Pos)          /*!< 0x0000FFFF */\r\n#define LTDC_CPSR_CYPOS              LTDC_CPSR_CYPOS_Msk                       /*!< Current Y Position */\r\n#define LTDC_CPSR_CXPOS_Pos          (16U)                                     \r\n#define LTDC_CPSR_CXPOS_Msk          (0xFFFFU << LTDC_CPSR_CXPOS_Pos)          /*!< 0xFFFF0000 */\r\n#define LTDC_CPSR_CXPOS              LTDC_CPSR_CXPOS_Msk                       /*!< Current X Position */\r\n\r\n/********************  Bit definition for LTDC_CDSR register  *****************/\r\n\r\n#define LTDC_CDSR_VDES_Pos           (0U)                                      \r\n#define LTDC_CDSR_VDES_Msk           (0x1U << LTDC_CDSR_VDES_Pos)              /*!< 0x00000001 */\r\n#define LTDC_CDSR_VDES               LTDC_CDSR_VDES_Msk                        /*!< Vertical Data Enable Status       */\r\n#define LTDC_CDSR_HDES_Pos           (1U)                                      \r\n#define LTDC_CDSR_HDES_Msk           (0x1U << LTDC_CDSR_HDES_Pos)              /*!< 0x00000002 */\r\n#define LTDC_CDSR_HDES               LTDC_CDSR_HDES_Msk                        /*!< Horizontal Data Enable Status     */\r\n#define LTDC_CDSR_VSYNCS_Pos         (2U)                                      \r\n#define LTDC_CDSR_VSYNCS_Msk         (0x1U << LTDC_CDSR_VSYNCS_Pos)            /*!< 0x00000004 */\r\n#define LTDC_CDSR_VSYNCS             LTDC_CDSR_VSYNCS_Msk                      /*!< Vertical Synchronization Status   */\r\n#define LTDC_CDSR_HSYNCS_Pos         (3U)                                      \r\n#define LTDC_CDSR_HSYNCS_Msk         (0x1U << LTDC_CDSR_HSYNCS_Pos)            /*!< 0x00000008 */\r\n#define LTDC_CDSR_HSYNCS             LTDC_CDSR_HSYNCS_Msk                      /*!< Horizontal Synchronization Status */\r\n\r\n/********************  Bit definition for LTDC_LxCR register  *****************/\r\n\r\n#define LTDC_LxCR_LEN_Pos            (0U)                                      \r\n#define LTDC_LxCR_LEN_Msk            (0x1U << LTDC_LxCR_LEN_Pos)               /*!< 0x00000001 */\r\n#define LTDC_LxCR_LEN                LTDC_LxCR_LEN_Msk                         /*!< Layer Enable              */\r\n#define LTDC_LxCR_COLKEN_Pos         (1U)                                      \r\n#define LTDC_LxCR_COLKEN_Msk         (0x1U << LTDC_LxCR_COLKEN_Pos)            /*!< 0x00000002 */\r\n#define LTDC_LxCR_COLKEN             LTDC_LxCR_COLKEN_Msk                      /*!< Color Keying Enable       */\r\n#define LTDC_LxCR_CLUTEN_Pos         (4U)                                      \r\n#define LTDC_LxCR_CLUTEN_Msk         (0x1U << LTDC_LxCR_CLUTEN_Pos)            /*!< 0x00000010 */\r\n#define LTDC_LxCR_CLUTEN             LTDC_LxCR_CLUTEN_Msk                      /*!< Color Lockup Table Enable */\r\n\r\n/********************  Bit definition for LTDC_LxWHPCR register  **************/\r\n\r\n#define LTDC_LxWHPCR_WHSTPOS_Pos     (0U)                                      \r\n#define LTDC_LxWHPCR_WHSTPOS_Msk     (0xFFFU << LTDC_LxWHPCR_WHSTPOS_Pos)      /*!< 0x00000FFF */\r\n#define LTDC_LxWHPCR_WHSTPOS         LTDC_LxWHPCR_WHSTPOS_Msk                  /*!< Window Horizontal Start Position */\r\n#define LTDC_LxWHPCR_WHSPPOS_Pos     (16U)                                     \r\n#define LTDC_LxWHPCR_WHSPPOS_Msk     (0xFFFFU << LTDC_LxWHPCR_WHSPPOS_Pos)     /*!< 0xFFFF0000 */\r\n#define LTDC_LxWHPCR_WHSPPOS         LTDC_LxWHPCR_WHSPPOS_Msk                  /*!< Window Horizontal Stop Position  */\r\n\r\n/********************  Bit definition for LTDC_LxWVPCR register  **************/\r\n\r\n#define LTDC_LxWVPCR_WVSTPOS_Pos     (0U)                                      \r\n#define LTDC_LxWVPCR_WVSTPOS_Msk     (0xFFFU << LTDC_LxWVPCR_WVSTPOS_Pos)      /*!< 0x00000FFF */\r\n#define LTDC_LxWVPCR_WVSTPOS         LTDC_LxWVPCR_WVSTPOS_Msk                  /*!< Window Vertical Start Position */\r\n#define LTDC_LxWVPCR_WVSPPOS_Pos     (16U)                                     \r\n#define LTDC_LxWVPCR_WVSPPOS_Msk     (0xFFFFU << LTDC_LxWVPCR_WVSPPOS_Pos)     /*!< 0xFFFF0000 */\r\n#define LTDC_LxWVPCR_WVSPPOS         LTDC_LxWVPCR_WVSPPOS_Msk                  /*!< Window Vertical Stop Position  */\r\n\r\n/********************  Bit definition for LTDC_LxCKCR register  ***************/\r\n\r\n#define LTDC_LxCKCR_CKBLUE_Pos       (0U)                                      \r\n#define LTDC_LxCKCR_CKBLUE_Msk       (0xFFU << LTDC_LxCKCR_CKBLUE_Pos)         /*!< 0x000000FF */\r\n#define LTDC_LxCKCR_CKBLUE           LTDC_LxCKCR_CKBLUE_Msk                    /*!< Color Key Blue value  */\r\n#define LTDC_LxCKCR_CKGREEN_Pos      (8U)                                      \r\n#define LTDC_LxCKCR_CKGREEN_Msk      (0xFFU << LTDC_LxCKCR_CKGREEN_Pos)        /*!< 0x0000FF00 */\r\n#define LTDC_LxCKCR_CKGREEN          LTDC_LxCKCR_CKGREEN_Msk                   /*!< Color Key Green value */\r\n#define LTDC_LxCKCR_CKRED_Pos        (16U)                                     \r\n#define LTDC_LxCKCR_CKRED_Msk        (0xFFU << LTDC_LxCKCR_CKRED_Pos)          /*!< 0x00FF0000 */\r\n#define LTDC_LxCKCR_CKRED            LTDC_LxCKCR_CKRED_Msk                     /*!< Color Key Red value   */\r\n\r\n/********************  Bit definition for LTDC_LxPFCR register  ***************/\r\n\r\n#define LTDC_LxPFCR_PF_Pos           (0U)                                      \r\n#define LTDC_LxPFCR_PF_Msk           (0x7U << LTDC_LxPFCR_PF_Pos)              /*!< 0x00000007 */\r\n#define LTDC_LxPFCR_PF               LTDC_LxPFCR_PF_Msk                        /*!< Pixel Format */\r\n\r\n/********************  Bit definition for LTDC_LxCACR register  ***************/\r\n\r\n#define LTDC_LxCACR_CONSTA_Pos       (0U)                                      \r\n#define LTDC_LxCACR_CONSTA_Msk       (0xFFU << LTDC_LxCACR_CONSTA_Pos)         /*!< 0x000000FF */\r\n#define LTDC_LxCACR_CONSTA           LTDC_LxCACR_CONSTA_Msk                    /*!< Constant Alpha */\r\n\r\n/********************  Bit definition for LTDC_LxDCCR register  ***************/\r\n\r\n#define LTDC_LxDCCR_DCBLUE_Pos       (0U)                                      \r\n#define LTDC_LxDCCR_DCBLUE_Msk       (0xFFU << LTDC_LxDCCR_DCBLUE_Pos)         /*!< 0x000000FF */\r\n#define LTDC_LxDCCR_DCBLUE           LTDC_LxDCCR_DCBLUE_Msk                    /*!< Default Color Blue  */\r\n#define LTDC_LxDCCR_DCGREEN_Pos      (8U)                                      \r\n#define LTDC_LxDCCR_DCGREEN_Msk      (0xFFU << LTDC_LxDCCR_DCGREEN_Pos)        /*!< 0x0000FF00 */\r\n#define LTDC_LxDCCR_DCGREEN          LTDC_LxDCCR_DCGREEN_Msk                   /*!< Default Color Green */\r\n#define LTDC_LxDCCR_DCRED_Pos        (16U)                                     \r\n#define LTDC_LxDCCR_DCRED_Msk        (0xFFU << LTDC_LxDCCR_DCRED_Pos)          /*!< 0x00FF0000 */\r\n#define LTDC_LxDCCR_DCRED            LTDC_LxDCCR_DCRED_Msk                     /*!< Default Color Red   */\r\n#define LTDC_LxDCCR_DCALPHA_Pos      (24U)                                     \r\n#define LTDC_LxDCCR_DCALPHA_Msk      (0xFFU << LTDC_LxDCCR_DCALPHA_Pos)        /*!< 0xFF000000 */\r\n#define LTDC_LxDCCR_DCALPHA          LTDC_LxDCCR_DCALPHA_Msk                   /*!< Default Color Alpha */\r\n\r\n/********************  Bit definition for LTDC_LxBFCR register  ***************/\r\n\r\n#define LTDC_LxBFCR_BF2_Pos          (0U)                                      \r\n#define LTDC_LxBFCR_BF2_Msk          (0x7U << LTDC_LxBFCR_BF2_Pos)             /*!< 0x00000007 */\r\n#define LTDC_LxBFCR_BF2              LTDC_LxBFCR_BF2_Msk                       /*!< Blending Factor 2 */\r\n#define LTDC_LxBFCR_BF1_Pos          (8U)                                      \r\n#define LTDC_LxBFCR_BF1_Msk          (0x7U << LTDC_LxBFCR_BF1_Pos)             /*!< 0x00000700 */\r\n#define LTDC_LxBFCR_BF1              LTDC_LxBFCR_BF1_Msk                       /*!< Blending Factor 1 */\r\n\r\n/********************  Bit definition for LTDC_LxCFBAR register  **************/\r\n\r\n#define LTDC_LxCFBAR_CFBADD_Pos      (0U)                                      \r\n#define LTDC_LxCFBAR_CFBADD_Msk      (0xFFFFFFFFU << LTDC_LxCFBAR_CFBADD_Pos)  /*!< 0xFFFFFFFF */\r\n#define LTDC_LxCFBAR_CFBADD          LTDC_LxCFBAR_CFBADD_Msk                   /*!< Color Frame Buffer Start Address */\r\n\r\n/********************  Bit definition for LTDC_LxCFBLR register  **************/\r\n\r\n#define LTDC_LxCFBLR_CFBLL_Pos       (0U)                                      \r\n#define LTDC_LxCFBLR_CFBLL_Msk       (0x1FFFU << LTDC_LxCFBLR_CFBLL_Pos)       /*!< 0x00001FFF */\r\n#define LTDC_LxCFBLR_CFBLL           LTDC_LxCFBLR_CFBLL_Msk                    /*!< Color Frame Buffer Line Length    */\r\n#define LTDC_LxCFBLR_CFBP_Pos        (16U)                                     \r\n#define LTDC_LxCFBLR_CFBP_Msk        (0x1FFFU << LTDC_LxCFBLR_CFBP_Pos)        /*!< 0x1FFF0000 */\r\n#define LTDC_LxCFBLR_CFBP            LTDC_LxCFBLR_CFBP_Msk                     /*!< Color Frame Buffer Pitch in bytes */\r\n\r\n/********************  Bit definition for LTDC_LxCFBLNR register  *************/\r\n\r\n#define LTDC_LxCFBLNR_CFBLNBR_Pos    (0U)                                      \r\n#define LTDC_LxCFBLNR_CFBLNBR_Msk    (0x7FFU << LTDC_LxCFBLNR_CFBLNBR_Pos)     /*!< 0x000007FF */\r\n#define LTDC_LxCFBLNR_CFBLNBR        LTDC_LxCFBLNR_CFBLNBR_Msk                 /*!< Frame Buffer Line Number */\r\n\r\n/********************  Bit definition for LTDC_LxCLUTWR register  *************/\r\n\r\n#define LTDC_LxCLUTWR_BLUE_Pos       (0U)                                      \r\n#define LTDC_LxCLUTWR_BLUE_Msk       (0xFFU << LTDC_LxCLUTWR_BLUE_Pos)         /*!< 0x000000FF */\r\n#define LTDC_LxCLUTWR_BLUE           LTDC_LxCLUTWR_BLUE_Msk                    /*!< Blue value   */\r\n#define LTDC_LxCLUTWR_GREEN_Pos      (8U)                                      \r\n#define LTDC_LxCLUTWR_GREEN_Msk      (0xFFU << LTDC_LxCLUTWR_GREEN_Pos)        /*!< 0x0000FF00 */\r\n#define LTDC_LxCLUTWR_GREEN          LTDC_LxCLUTWR_GREEN_Msk                   /*!< Green value  */\r\n#define LTDC_LxCLUTWR_RED_Pos        (16U)                                     \r\n#define LTDC_LxCLUTWR_RED_Msk        (0xFFU << LTDC_LxCLUTWR_RED_Pos)          /*!< 0x00FF0000 */\r\n#define LTDC_LxCLUTWR_RED            LTDC_LxCLUTWR_RED_Msk                     /*!< Red value    */\r\n#define LTDC_LxCLUTWR_CLUTADD_Pos    (24U)                                     \r\n#define LTDC_LxCLUTWR_CLUTADD_Msk    (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos)      /*!< 0xFF000000 */\r\n#define LTDC_LxCLUTWR_CLUTADD        LTDC_LxCLUTWR_CLUTADD_Msk                 /*!< CLUT address */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                             Power Control                                  */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bit definition for PWR_CR1 register  ********************/\r\n#define PWR_CR1_LPDS_Pos        (0U)                                           \r\n#define PWR_CR1_LPDS_Msk        (0x1U << PWR_CR1_LPDS_Pos)                     /*!< 0x00000001 */\r\n#define PWR_CR1_LPDS            PWR_CR1_LPDS_Msk                               /*!< Low-Power Deepsleep                 */\r\n#define PWR_CR1_PDDS_Pos        (1U)                                           \r\n#define PWR_CR1_PDDS_Msk        (0x1U << PWR_CR1_PDDS_Pos)                     /*!< 0x00000002 */\r\n#define PWR_CR1_PDDS            PWR_CR1_PDDS_Msk                               /*!< Power Down Deepsleep                */\r\n#define PWR_CR1_CSBF_Pos        (3U)                                           \r\n#define PWR_CR1_CSBF_Msk        (0x1U << PWR_CR1_CSBF_Pos)                     /*!< 0x00000008 */\r\n#define PWR_CR1_CSBF            PWR_CR1_CSBF_Msk                               /*!< Clear Standby Flag                  */\r\n#define PWR_CR1_PVDE_Pos        (4U)                                           \r\n#define PWR_CR1_PVDE_Msk        (0x1U << PWR_CR1_PVDE_Pos)                     /*!< 0x00000010 */\r\n#define PWR_CR1_PVDE            PWR_CR1_PVDE_Msk                               /*!< Power Voltage Detector Enable       */\r\n#define PWR_CR1_PLS_Pos         (5U)                                           \r\n#define PWR_CR1_PLS_Msk         (0x7U << PWR_CR1_PLS_Pos)                      /*!< 0x000000E0 */\r\n#define PWR_CR1_PLS             PWR_CR1_PLS_Msk                                /*!< PLS[2:0] bits (PVD Level Selection) */\r\n#define PWR_CR1_PLS_0           (0x1U << PWR_CR1_PLS_Pos)                      /*!< 0x00000020 */\r\n#define PWR_CR1_PLS_1           (0x2U << PWR_CR1_PLS_Pos)                      /*!< 0x00000040 */\r\n#define PWR_CR1_PLS_2           (0x4U << PWR_CR1_PLS_Pos)                      /*!< 0x00000080 */\r\n\r\n/*!< PVD level configuration */\r\n#define PWR_CR1_PLS_LEV0        0x00000000U                                    /*!< PVD level 0 */\r\n#define PWR_CR1_PLS_LEV1_Pos    (5U)                                           \r\n#define PWR_CR1_PLS_LEV1_Msk    (0x1U << PWR_CR1_PLS_LEV1_Pos)                 /*!< 0x00000020 */\r\n#define PWR_CR1_PLS_LEV1        PWR_CR1_PLS_LEV1_Msk                           /*!< PVD level 1 */\r\n#define PWR_CR1_PLS_LEV2_Pos    (6U)                                           \r\n#define PWR_CR1_PLS_LEV2_Msk    (0x1U << PWR_CR1_PLS_LEV2_Pos)                 /*!< 0x00000040 */\r\n#define PWR_CR1_PLS_LEV2        PWR_CR1_PLS_LEV2_Msk                           /*!< PVD level 2 */\r\n#define PWR_CR1_PLS_LEV3_Pos    (5U)                                           \r\n#define PWR_CR1_PLS_LEV3_Msk    (0x3U << PWR_CR1_PLS_LEV3_Pos)                 /*!< 0x00000060 */\r\n#define PWR_CR1_PLS_LEV3        PWR_CR1_PLS_LEV3_Msk                           /*!< PVD level 3 */\r\n#define PWR_CR1_PLS_LEV4_Pos    (7U)                                           \r\n#define PWR_CR1_PLS_LEV4_Msk    (0x1U << PWR_CR1_PLS_LEV4_Pos)                 /*!< 0x00000080 */\r\n#define PWR_CR1_PLS_LEV4        PWR_CR1_PLS_LEV4_Msk                           /*!< PVD level 4 */\r\n#define PWR_CR1_PLS_LEV5_Pos    (5U)                                           \r\n#define PWR_CR1_PLS_LEV5_Msk    (0x5U << PWR_CR1_PLS_LEV5_Pos)                 /*!< 0x000000A0 */\r\n#define PWR_CR1_PLS_LEV5        PWR_CR1_PLS_LEV5_Msk                           /*!< PVD level 5 */\r\n#define PWR_CR1_PLS_LEV6_Pos    (6U)                                           \r\n#define PWR_CR1_PLS_LEV6_Msk    (0x3U << PWR_CR1_PLS_LEV6_Pos)                 /*!< 0x000000C0 */\r\n#define PWR_CR1_PLS_LEV6        PWR_CR1_PLS_LEV6_Msk                           /*!< PVD level 6 */\r\n#define PWR_CR1_PLS_LEV7_Pos    (5U)                                           \r\n#define PWR_CR1_PLS_LEV7_Msk    (0x7U << PWR_CR1_PLS_LEV7_Pos)                 /*!< 0x000000E0 */\r\n#define PWR_CR1_PLS_LEV7        PWR_CR1_PLS_LEV7_Msk                           /*!< PVD level 7 */\r\n#define PWR_CR1_DBP_Pos         (8U)                                           \r\n#define PWR_CR1_DBP_Msk         (0x1U << PWR_CR1_DBP_Pos)                      /*!< 0x00000100 */\r\n#define PWR_CR1_DBP             PWR_CR1_DBP_Msk                                /*!< Disable Backup Domain write protection                     */\r\n#define PWR_CR1_FPDS_Pos        (9U)                                           \r\n#define PWR_CR1_FPDS_Msk        (0x1U << PWR_CR1_FPDS_Pos)                     /*!< 0x00000200 */\r\n#define PWR_CR1_FPDS            PWR_CR1_FPDS_Msk                               /*!< Flash power down in Stop mode                              */\r\n#define PWR_CR1_LPUDS_Pos       (10U)                                          \r\n#define PWR_CR1_LPUDS_Msk       (0x1U << PWR_CR1_LPUDS_Pos)                    /*!< 0x00000400 */\r\n#define PWR_CR1_LPUDS           PWR_CR1_LPUDS_Msk                              /*!< Low-power regulator in deepsleep under-drive mode          */\r\n#define PWR_CR1_MRUDS_Pos       (11U)                                          \r\n#define PWR_CR1_MRUDS_Msk       (0x1U << PWR_CR1_MRUDS_Pos)                    /*!< 0x00000800 */\r\n#define PWR_CR1_MRUDS           PWR_CR1_MRUDS_Msk                              /*!< Main regulator in deepsleep under-drive mode               */\r\n#define PWR_CR1_ADCDC1_Pos      (13U)                                          \r\n#define PWR_CR1_ADCDC1_Msk      (0x1U << PWR_CR1_ADCDC1_Pos)                   /*!< 0x00002000 */\r\n#define PWR_CR1_ADCDC1          PWR_CR1_ADCDC1_Msk                             /*!< Refer to AN4073 on how to use this bit */\r\n#define PWR_CR1_VOS_Pos         (14U)                                          \r\n#define PWR_CR1_VOS_Msk         (0x3U << PWR_CR1_VOS_Pos)                      /*!< 0x0000C000 */\r\n#define PWR_CR1_VOS             PWR_CR1_VOS_Msk                                /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */\r\n#define PWR_CR1_VOS_0           (0x1U << PWR_CR1_VOS_Pos)                      /*!< 0x00004000 */\r\n#define PWR_CR1_VOS_1           (0x2U << PWR_CR1_VOS_Pos)                      /*!< 0x00008000 */\r\n#define PWR_CR1_ODEN_Pos        (16U)                                          \r\n#define PWR_CR1_ODEN_Msk        (0x1U << PWR_CR1_ODEN_Pos)                     /*!< 0x00010000 */\r\n#define PWR_CR1_ODEN            PWR_CR1_ODEN_Msk                               /*!< Over Drive enable                   */\r\n#define PWR_CR1_ODSWEN_Pos      (17U)                                          \r\n#define PWR_CR1_ODSWEN_Msk      (0x1U << PWR_CR1_ODSWEN_Pos)                   /*!< 0x00020000 */\r\n#define PWR_CR1_ODSWEN          PWR_CR1_ODSWEN_Msk                             /*!< Over Drive switch enabled           */\r\n#define PWR_CR1_UDEN_Pos        (18U)                                          \r\n#define PWR_CR1_UDEN_Msk        (0x3U << PWR_CR1_UDEN_Pos)                     /*!< 0x000C0000 */\r\n#define PWR_CR1_UDEN            PWR_CR1_UDEN_Msk                               /*!< Under Drive enable in stop mode     */\r\n#define PWR_CR1_UDEN_0          (0x1U << PWR_CR1_UDEN_Pos)                     /*!< 0x00040000 */\r\n#define PWR_CR1_UDEN_1          (0x2U << PWR_CR1_UDEN_Pos)                     /*!< 0x00080000 */\r\n\r\n/*******************  Bit definition for PWR_CSR1 register  ********************/\r\n#define PWR_CSR1_WUIF_Pos       (0U)                                           \r\n#define PWR_CSR1_WUIF_Msk       (0x1U << PWR_CSR1_WUIF_Pos)                    /*!< 0x00000001 */\r\n#define PWR_CSR1_WUIF           PWR_CSR1_WUIF_Msk                              /*!< Wake up internal Flag                            */\r\n#define PWR_CSR1_SBF_Pos        (1U)                                           \r\n#define PWR_CSR1_SBF_Msk        (0x1U << PWR_CSR1_SBF_Pos)                     /*!< 0x00000002 */\r\n#define PWR_CSR1_SBF            PWR_CSR1_SBF_Msk                               /*!< Standby Flag                                     */\r\n#define PWR_CSR1_PVDO_Pos       (2U)                                           \r\n#define PWR_CSR1_PVDO_Msk       (0x1U << PWR_CSR1_PVDO_Pos)                    /*!< 0x00000004 */\r\n#define PWR_CSR1_PVDO           PWR_CSR1_PVDO_Msk                              /*!< PVD Output                                       */\r\n#define PWR_CSR1_BRR_Pos        (3U)                                           \r\n#define PWR_CSR1_BRR_Msk        (0x1U << PWR_CSR1_BRR_Pos)                     /*!< 0x00000008 */\r\n#define PWR_CSR1_BRR            PWR_CSR1_BRR_Msk                               /*!< Backup regulator ready                           */\r\n#define PWR_CSR1_EIWUP_Pos      (8U)                                           \r\n#define PWR_CSR1_EIWUP_Msk      (0x1U << PWR_CSR1_EIWUP_Pos)                   /*!< 0x00000100 */\r\n#define PWR_CSR1_EIWUP          PWR_CSR1_EIWUP_Msk                             /*!< Enable internal wakeup                           */\r\n#define PWR_CSR1_BRE_Pos        (9U)                                           \r\n#define PWR_CSR1_BRE_Msk        (0x1U << PWR_CSR1_BRE_Pos)                     /*!< 0x00000200 */\r\n#define PWR_CSR1_BRE            PWR_CSR1_BRE_Msk                               /*!< Backup regulator enable                          */\r\n#define PWR_CSR1_VOSRDY_Pos     (14U)                                          \r\n#define PWR_CSR1_VOSRDY_Msk     (0x1U << PWR_CSR1_VOSRDY_Pos)                  /*!< 0x00004000 */\r\n#define PWR_CSR1_VOSRDY         PWR_CSR1_VOSRDY_Msk                            /*!< Regulator voltage scaling output selection ready */\r\n#define PWR_CSR1_ODRDY_Pos      (16U)                                          \r\n#define PWR_CSR1_ODRDY_Msk      (0x1U << PWR_CSR1_ODRDY_Pos)                   /*!< 0x00010000 */\r\n#define PWR_CSR1_ODRDY          PWR_CSR1_ODRDY_Msk                             /*!< Over Drive generator ready                       */\r\n#define PWR_CSR1_ODSWRDY_Pos    (17U)                                          \r\n#define PWR_CSR1_ODSWRDY_Msk    (0x1U << PWR_CSR1_ODSWRDY_Pos)                 /*!< 0x00020000 */\r\n#define PWR_CSR1_ODSWRDY        PWR_CSR1_ODSWRDY_Msk                           /*!< Over Drive Switch ready                          */\r\n#define PWR_CSR1_UDRDY_Pos      (18U)                                          \r\n#define PWR_CSR1_UDRDY_Msk      (0x3U << PWR_CSR1_UDRDY_Pos)                   /*!< 0x000C0000 */\r\n#define PWR_CSR1_UDRDY          PWR_CSR1_UDRDY_Msk                             /*!< Under Drive ready                                */\r\n\r\n/* Legacy define */\r\n#define  PWR_CSR1_UDSWRDY                     PWR_CSR1_UDRDY\r\n\r\n/********************  Bit definition for PWR_CR2 register  ********************/\r\n#define PWR_CR2_CWUPF1_Pos      (0U)                                           \r\n#define PWR_CR2_CWUPF1_Msk      (0x1U << PWR_CR2_CWUPF1_Pos)                   /*!< 0x00000001 */\r\n#define PWR_CR2_CWUPF1          PWR_CR2_CWUPF1_Msk                             /*!< Clear Wakeup Pin Flag for PA0      */\r\n#define PWR_CR2_CWUPF2_Pos      (1U)                                           \r\n#define PWR_CR2_CWUPF2_Msk      (0x1U << PWR_CR2_CWUPF2_Pos)                   /*!< 0x00000002 */\r\n#define PWR_CR2_CWUPF2          PWR_CR2_CWUPF2_Msk                             /*!< Clear Wakeup Pin Flag for PA2      */\r\n#define PWR_CR2_CWUPF3_Pos      (2U)                                           \r\n#define PWR_CR2_CWUPF3_Msk      (0x1U << PWR_CR2_CWUPF3_Pos)                   /*!< 0x00000004 */\r\n#define PWR_CR2_CWUPF3          PWR_CR2_CWUPF3_Msk                             /*!< Clear Wakeup Pin Flag for PC1      */\r\n#define PWR_CR2_CWUPF4_Pos      (3U)                                           \r\n#define PWR_CR2_CWUPF4_Msk      (0x1U << PWR_CR2_CWUPF4_Pos)                   /*!< 0x00000008 */\r\n#define PWR_CR2_CWUPF4          PWR_CR2_CWUPF4_Msk                             /*!< Clear Wakeup Pin Flag for PC13     */\r\n#define PWR_CR2_CWUPF5_Pos      (4U)                                           \r\n#define PWR_CR2_CWUPF5_Msk      (0x1U << PWR_CR2_CWUPF5_Pos)                   /*!< 0x00000010 */\r\n#define PWR_CR2_CWUPF5          PWR_CR2_CWUPF5_Msk                             /*!< Clear Wakeup Pin Flag for PI8      */\r\n#define PWR_CR2_CWUPF6_Pos      (5U)                                           \r\n#define PWR_CR2_CWUPF6_Msk      (0x1U << PWR_CR2_CWUPF6_Pos)                   /*!< 0x00000020 */\r\n#define PWR_CR2_CWUPF6          PWR_CR2_CWUPF6_Msk                             /*!< Clear Wakeup Pin Flag for PI11     */\r\n#define PWR_CR2_WUPP1_Pos       (8U)                                           \r\n#define PWR_CR2_WUPP1_Msk       (0x1U << PWR_CR2_WUPP1_Pos)                    /*!< 0x00000100 */\r\n#define PWR_CR2_WUPP1           PWR_CR2_WUPP1_Msk                              /*!< Wakeup Pin Polarity bit for PA0    */\r\n#define PWR_CR2_WUPP2_Pos       (9U)                                           \r\n#define PWR_CR2_WUPP2_Msk       (0x1U << PWR_CR2_WUPP2_Pos)                    /*!< 0x00000200 */\r\n#define PWR_CR2_WUPP2           PWR_CR2_WUPP2_Msk                              /*!< Wakeup Pin Polarity bit for PA2    */\r\n#define PWR_CR2_WUPP3_Pos       (10U)                                          \r\n#define PWR_CR2_WUPP3_Msk       (0x1U << PWR_CR2_WUPP3_Pos)                    /*!< 0x00000400 */\r\n#define PWR_CR2_WUPP3           PWR_CR2_WUPP3_Msk                              /*!< Wakeup Pin Polarity bit for PC1    */\r\n#define PWR_CR2_WUPP4_Pos       (11U)                                          \r\n#define PWR_CR2_WUPP4_Msk       (0x1U << PWR_CR2_WUPP4_Pos)                    /*!< 0x00000800 */\r\n#define PWR_CR2_WUPP4           PWR_CR2_WUPP4_Msk                              /*!< Wakeup Pin Polarity bit for PC13   */\r\n#define PWR_CR2_WUPP5_Pos       (12U)                                          \r\n#define PWR_CR2_WUPP5_Msk       (0x1U << PWR_CR2_WUPP5_Pos)                    /*!< 0x00001000 */\r\n#define PWR_CR2_WUPP5           PWR_CR2_WUPP5_Msk                              /*!< Wakeup Pin Polarity bit for PI8    */\r\n#define PWR_CR2_WUPP6_Pos       (13U)                                          \r\n#define PWR_CR2_WUPP6_Msk       (0x1U << PWR_CR2_WUPP6_Pos)                    /*!< 0x00002000 */\r\n#define PWR_CR2_WUPP6           PWR_CR2_WUPP6_Msk                              /*!< Wakeup Pin Polarity bit for PI11   */\r\n\r\n/*******************  Bit definition for PWR_CSR2 register  ********************/\r\n#define PWR_CSR2_WUPF1_Pos      (0U)                                           \r\n#define PWR_CSR2_WUPF1_Msk      (0x1U << PWR_CSR2_WUPF1_Pos)                   /*!< 0x00000001 */\r\n#define PWR_CSR2_WUPF1          PWR_CSR2_WUPF1_Msk                             /*!< Wakeup Pin Flag for PA0            */\r\n#define PWR_CSR2_WUPF2_Pos      (1U)                                           \r\n#define PWR_CSR2_WUPF2_Msk      (0x1U << PWR_CSR2_WUPF2_Pos)                   /*!< 0x00000002 */\r\n#define PWR_CSR2_WUPF2          PWR_CSR2_WUPF2_Msk                             /*!< Wakeup Pin Flag for PA2            */\r\n#define PWR_CSR2_WUPF3_Pos      (2U)                                           \r\n#define PWR_CSR2_WUPF3_Msk      (0x1U << PWR_CSR2_WUPF3_Pos)                   /*!< 0x00000004 */\r\n#define PWR_CSR2_WUPF3          PWR_CSR2_WUPF3_Msk                             /*!< Wakeup Pin Flag for PC1            */\r\n#define PWR_CSR2_WUPF4_Pos      (3U)                                           \r\n#define PWR_CSR2_WUPF4_Msk      (0x1U << PWR_CSR2_WUPF4_Pos)                   /*!< 0x00000008 */\r\n#define PWR_CSR2_WUPF4          PWR_CSR2_WUPF4_Msk                             /*!< Wakeup Pin Flag for PC13           */\r\n#define PWR_CSR2_WUPF5_Pos      (4U)                                           \r\n#define PWR_CSR2_WUPF5_Msk      (0x1U << PWR_CSR2_WUPF5_Pos)                   /*!< 0x00000010 */\r\n#define PWR_CSR2_WUPF5          PWR_CSR2_WUPF5_Msk                             /*!< Wakeup Pin Flag for PI8            */\r\n#define PWR_CSR2_WUPF6_Pos      (5U)                                           \r\n#define PWR_CSR2_WUPF6_Msk      (0x1U << PWR_CSR2_WUPF6_Pos)                   /*!< 0x00000020 */\r\n#define PWR_CSR2_WUPF6          PWR_CSR2_WUPF6_Msk                             /*!< Wakeup Pin Flag for PI11           */\r\n#define PWR_CSR2_EWUP1_Pos      (8U)                                           \r\n#define PWR_CSR2_EWUP1_Msk      (0x1U << PWR_CSR2_EWUP1_Pos)                   /*!< 0x00000100 */\r\n#define PWR_CSR2_EWUP1          PWR_CSR2_EWUP1_Msk                             /*!< Enable Wakeup Pin PA0              */\r\n#define PWR_CSR2_EWUP2_Pos      (9U)                                           \r\n#define PWR_CSR2_EWUP2_Msk      (0x1U << PWR_CSR2_EWUP2_Pos)                   /*!< 0x00000200 */\r\n#define PWR_CSR2_EWUP2          PWR_CSR2_EWUP2_Msk                             /*!< Enable Wakeup Pin PA2              */\r\n#define PWR_CSR2_EWUP3_Pos      (10U)                                          \r\n#define PWR_CSR2_EWUP3_Msk      (0x1U << PWR_CSR2_EWUP3_Pos)                   /*!< 0x00000400 */\r\n#define PWR_CSR2_EWUP3          PWR_CSR2_EWUP3_Msk                             /*!< Enable Wakeup Pin PC1              */\r\n#define PWR_CSR2_EWUP4_Pos      (11U)                                          \r\n#define PWR_CSR2_EWUP4_Msk      (0x1U << PWR_CSR2_EWUP4_Pos)                   /*!< 0x00000800 */\r\n#define PWR_CSR2_EWUP4          PWR_CSR2_EWUP4_Msk                             /*!< Enable Wakeup Pin PC13             */\r\n#define PWR_CSR2_EWUP5_Pos      (12U)                                          \r\n#define PWR_CSR2_EWUP5_Msk      (0x1U << PWR_CSR2_EWUP5_Pos)                   /*!< 0x00001000 */\r\n#define PWR_CSR2_EWUP5          PWR_CSR2_EWUP5_Msk                             /*!< Enable Wakeup Pin PI8              */\r\n#define PWR_CSR2_EWUP6_Pos      (13U)                                          \r\n#define PWR_CSR2_EWUP6_Msk      (0x1U << PWR_CSR2_EWUP6_Pos)                   /*!< 0x00002000 */\r\n#define PWR_CSR2_EWUP6          PWR_CSR2_EWUP6_Msk                             /*!< Enable Wakeup Pin PI11             */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                    QUADSPI                                 */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/* QUADSPI IP version */\r\n#define QSPI1_V1_0\r\n/*****************  Bit definition for QUADSPI_CR register  *******************/\r\n#define QUADSPI_CR_EN_Pos                (0U)                                  \r\n#define QUADSPI_CR_EN_Msk                (0x1U << QUADSPI_CR_EN_Pos)           /*!< 0x00000001 */\r\n#define QUADSPI_CR_EN                    QUADSPI_CR_EN_Msk                     /*!< Enable                            */\r\n#define QUADSPI_CR_ABORT_Pos             (1U)                                  \r\n#define QUADSPI_CR_ABORT_Msk             (0x1U << QUADSPI_CR_ABORT_Pos)        /*!< 0x00000002 */\r\n#define QUADSPI_CR_ABORT                 QUADSPI_CR_ABORT_Msk                  /*!< Abort request                     */\r\n#define QUADSPI_CR_DMAEN_Pos             (2U)                                  \r\n#define QUADSPI_CR_DMAEN_Msk             (0x1U << QUADSPI_CR_DMAEN_Pos)        /*!< 0x00000004 */\r\n#define QUADSPI_CR_DMAEN                 QUADSPI_CR_DMAEN_Msk                  /*!< DMA Enable                        */\r\n#define QUADSPI_CR_TCEN_Pos              (3U)                                  \r\n#define QUADSPI_CR_TCEN_Msk              (0x1U << QUADSPI_CR_TCEN_Pos)         /*!< 0x00000008 */\r\n#define QUADSPI_CR_TCEN                  QUADSPI_CR_TCEN_Msk                   /*!< Timeout Counter Enable            */\r\n#define QUADSPI_CR_SSHIFT_Pos            (4U)                                  \r\n#define QUADSPI_CR_SSHIFT_Msk            (0x1U << QUADSPI_CR_SSHIFT_Pos)       /*!< 0x00000010 */\r\n#define QUADSPI_CR_SSHIFT                QUADSPI_CR_SSHIFT_Msk                 /*!< Sample Shift                      */\r\n#define QUADSPI_CR_DFM_Pos               (6U)                                  \r\n#define QUADSPI_CR_DFM_Msk               (0x1U << QUADSPI_CR_DFM_Pos)          /*!< 0x00000040 */\r\n#define QUADSPI_CR_DFM                   QUADSPI_CR_DFM_Msk                    /*!< Dual Flash Mode                   */\r\n#define QUADSPI_CR_FSEL_Pos              (7U)                                  \r\n#define QUADSPI_CR_FSEL_Msk              (0x1U << QUADSPI_CR_FSEL_Pos)         /*!< 0x00000080 */\r\n#define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select                      */\r\n#define QUADSPI_CR_FTHRES_Pos            (8U)                                  \r\n#define QUADSPI_CR_FTHRES_Msk            (0x1FU << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00001F00 */\r\n#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[4:0] FIFO Level            */\r\n#define QUADSPI_CR_FTHRES_0              (0x01U << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000100 */\r\n#define QUADSPI_CR_FTHRES_1              (0x02U << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000200 */\r\n#define QUADSPI_CR_FTHRES_2              (0x04U << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000400 */\r\n#define QUADSPI_CR_FTHRES_3              (0x08U << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000800 */\r\n#define QUADSPI_CR_FTHRES_4              (0x10U << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00001000 */\r\n#define QUADSPI_CR_TEIE_Pos              (16U)                                 \r\n#define QUADSPI_CR_TEIE_Msk              (0x1U << QUADSPI_CR_TEIE_Pos)         /*!< 0x00010000 */\r\n#define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable    */\r\n#define QUADSPI_CR_TCIE_Pos              (17U)                                 \r\n#define QUADSPI_CR_TCIE_Msk              (0x1U << QUADSPI_CR_TCIE_Pos)         /*!< 0x00020000 */\r\n#define QUADSPI_CR_TCIE                  QUADSPI_CR_TCIE_Msk                   /*!< Transfer Complete Interrupt Enable */\r\n#define QUADSPI_CR_FTIE_Pos              (18U)                                 \r\n#define QUADSPI_CR_FTIE_Msk              (0x1U << QUADSPI_CR_FTIE_Pos)         /*!< 0x00040000 */\r\n#define QUADSPI_CR_FTIE                  QUADSPI_CR_FTIE_Msk                   /*!< FIFO Threshold Interrupt Enable    */\r\n#define QUADSPI_CR_SMIE_Pos              (19U)                                 \r\n#define QUADSPI_CR_SMIE_Msk              (0x1U << QUADSPI_CR_SMIE_Pos)         /*!< 0x00080000 */\r\n#define QUADSPI_CR_SMIE                  QUADSPI_CR_SMIE_Msk                   /*!< Status Match Interrupt Enable      */\r\n#define QUADSPI_CR_TOIE_Pos              (20U)                                 \r\n#define QUADSPI_CR_TOIE_Msk              (0x1U << QUADSPI_CR_TOIE_Pos)         /*!< 0x00100000 */\r\n#define QUADSPI_CR_TOIE                  QUADSPI_CR_TOIE_Msk                   /*!< TimeOut Interrupt Enable           */\r\n#define QUADSPI_CR_APMS_Pos              (22U)                                 \r\n#define QUADSPI_CR_APMS_Msk              (0x1U << QUADSPI_CR_APMS_Pos)         /*!< 0x00400000 */\r\n#define QUADSPI_CR_APMS                  QUADSPI_CR_APMS_Msk                   /*!< Bit 1                              */\r\n#define QUADSPI_CR_PMM_Pos               (23U)                                 \r\n#define QUADSPI_CR_PMM_Msk               (0x1U << QUADSPI_CR_PMM_Pos)          /*!< 0x00800000 */\r\n#define QUADSPI_CR_PMM                   QUADSPI_CR_PMM_Msk                    /*!< Polling Match Mode                 */\r\n#define QUADSPI_CR_PRESCALER_Pos         (24U)                                 \r\n#define QUADSPI_CR_PRESCALER_Msk         (0xFFU << QUADSPI_CR_PRESCALER_Pos)   /*!< 0xFF000000 */\r\n#define QUADSPI_CR_PRESCALER             QUADSPI_CR_PRESCALER_Msk              /*!< PRESCALER[7:0] Clock prescaler     */\r\n#define QUADSPI_CR_PRESCALER_0           (0x01U << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x01000000 */\r\n#define QUADSPI_CR_PRESCALER_1           (0x02U << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x02000000 */\r\n#define QUADSPI_CR_PRESCALER_2           (0x04U << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x04000000 */\r\n#define QUADSPI_CR_PRESCALER_3           (0x08U << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x08000000 */\r\n#define QUADSPI_CR_PRESCALER_4           (0x10U << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x10000000 */\r\n#define QUADSPI_CR_PRESCALER_5           (0x20U << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x20000000 */\r\n#define QUADSPI_CR_PRESCALER_6           (0x40U << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x40000000 */\r\n#define QUADSPI_CR_PRESCALER_7           (0x80U << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x80000000 */\r\n\r\n/*****************  Bit definition for QUADSPI_DCR register  ******************/\r\n#define QUADSPI_DCR_CKMODE_Pos           (0U)                                  \r\n#define QUADSPI_DCR_CKMODE_Msk           (0x1U << QUADSPI_DCR_CKMODE_Pos)      /*!< 0x00000001 */\r\n#define QUADSPI_DCR_CKMODE               QUADSPI_DCR_CKMODE_Msk                /*!< Mode 0 / Mode 3                 */\r\n#define QUADSPI_DCR_CSHT_Pos             (8U)                                  \r\n#define QUADSPI_DCR_CSHT_Msk             (0x7U << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000700 */\r\n#define QUADSPI_DCR_CSHT                 QUADSPI_DCR_CSHT_Msk                  /*!< CSHT[2:0]: ChipSelect High Time */\r\n#define QUADSPI_DCR_CSHT_0               (0x1U << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000100 */\r\n#define QUADSPI_DCR_CSHT_1               (0x2U << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000200 */\r\n#define QUADSPI_DCR_CSHT_2               (0x4U << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000400 */\r\n#define QUADSPI_DCR_FSIZE_Pos            (16U)                                 \r\n#define QUADSPI_DCR_FSIZE_Msk            (0x1FU << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x001F0000 */\r\n#define QUADSPI_DCR_FSIZE                QUADSPI_DCR_FSIZE_Msk                 /*!< FSIZE[4:0]: Flash Size          */\r\n#define QUADSPI_DCR_FSIZE_0              (0x01U << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00010000 */\r\n#define QUADSPI_DCR_FSIZE_1              (0x02U << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00020000 */\r\n#define QUADSPI_DCR_FSIZE_2              (0x04U << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00040000 */\r\n#define QUADSPI_DCR_FSIZE_3              (0x08U << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00080000 */\r\n#define QUADSPI_DCR_FSIZE_4              (0x10U << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00100000 */\r\n\r\n/******************  Bit definition for QUADSPI_SR register  *******************/\r\n#define QUADSPI_SR_TEF_Pos               (0U)                                  \r\n#define QUADSPI_SR_TEF_Msk               (0x1U << QUADSPI_SR_TEF_Pos)          /*!< 0x00000001 */\r\n#define QUADSPI_SR_TEF                   QUADSPI_SR_TEF_Msk                    /*!< Transfer Error Flag    */\r\n#define QUADSPI_SR_TCF_Pos               (1U)                                  \r\n#define QUADSPI_SR_TCF_Msk               (0x1U << QUADSPI_SR_TCF_Pos)          /*!< 0x00000002 */\r\n#define QUADSPI_SR_TCF                   QUADSPI_SR_TCF_Msk                    /*!< Transfer Complete Flag */\r\n#define QUADSPI_SR_FTF_Pos               (2U)                                  \r\n#define QUADSPI_SR_FTF_Msk               (0x1U << QUADSPI_SR_FTF_Pos)          /*!< 0x00000004 */\r\n#define QUADSPI_SR_FTF                   QUADSPI_SR_FTF_Msk                    /*!< FIFO Threshlod Flag    */\r\n#define QUADSPI_SR_SMF_Pos               (3U)                                  \r\n#define QUADSPI_SR_SMF_Msk               (0x1U << QUADSPI_SR_SMF_Pos)          /*!< 0x00000008 */\r\n#define QUADSPI_SR_SMF                   QUADSPI_SR_SMF_Msk                    /*!< Status Match Flag      */\r\n#define QUADSPI_SR_TOF_Pos               (4U)                                  \r\n#define QUADSPI_SR_TOF_Msk               (0x1U << QUADSPI_SR_TOF_Pos)          /*!< 0x00000010 */\r\n#define QUADSPI_SR_TOF                   QUADSPI_SR_TOF_Msk                    /*!< Timeout Flag           */\r\n#define QUADSPI_SR_BUSY_Pos              (5U)                                  \r\n#define QUADSPI_SR_BUSY_Msk              (0x1U << QUADSPI_SR_BUSY_Pos)         /*!< 0x00000020 */\r\n#define QUADSPI_SR_BUSY                  QUADSPI_SR_BUSY_Msk                   /*!< Busy                   */\r\n#define QUADSPI_SR_FLEVEL_Pos            (8U)                                  \r\n#define QUADSPI_SR_FLEVEL_Msk            (0x1FU << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00001F00 */\r\n#define QUADSPI_SR_FLEVEL                QUADSPI_SR_FLEVEL_Msk                 /*!< FIFO Threshlod Flag    */\r\n#define QUADSPI_SR_FLEVEL_0              (0x01U << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000100 */\r\n#define QUADSPI_SR_FLEVEL_1              (0x02U << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000200 */\r\n#define QUADSPI_SR_FLEVEL_2              (0x04U << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000400 */\r\n#define QUADSPI_SR_FLEVEL_3              (0x08U << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000800 */\r\n#define QUADSPI_SR_FLEVEL_4              (0x10U << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00001000 */\r\n\r\n/******************  Bit definition for QUADSPI_FCR register  ******************/\r\n#define QUADSPI_FCR_CTEF_Pos             (0U)                                  \r\n#define QUADSPI_FCR_CTEF_Msk             (0x1U << QUADSPI_FCR_CTEF_Pos)        /*!< 0x00000001 */\r\n#define QUADSPI_FCR_CTEF                 QUADSPI_FCR_CTEF_Msk                  /*!< Clear Transfer Error Flag    */\r\n#define QUADSPI_FCR_CTCF_Pos             (1U)                                  \r\n#define QUADSPI_FCR_CTCF_Msk             (0x1U << QUADSPI_FCR_CTCF_Pos)        /*!< 0x00000002 */\r\n#define QUADSPI_FCR_CTCF                 QUADSPI_FCR_CTCF_Msk                  /*!< Clear Transfer Complete Flag */\r\n#define QUADSPI_FCR_CSMF_Pos             (3U)                                  \r\n#define QUADSPI_FCR_CSMF_Msk             (0x1U << QUADSPI_FCR_CSMF_Pos)        /*!< 0x00000008 */\r\n#define QUADSPI_FCR_CSMF                 QUADSPI_FCR_CSMF_Msk                  /*!< Clear Status Match Flag      */\r\n#define QUADSPI_FCR_CTOF_Pos             (4U)                                  \r\n#define QUADSPI_FCR_CTOF_Msk             (0x1U << QUADSPI_FCR_CTOF_Pos)        /*!< 0x00000010 */\r\n#define QUADSPI_FCR_CTOF                 QUADSPI_FCR_CTOF_Msk                  /*!< Clear Timeout Flag           */\r\n\r\n/******************  Bit definition for QUADSPI_DLR register  ******************/\r\n#define QUADSPI_DLR_DL_Pos               (0U)                                  \r\n#define QUADSPI_DLR_DL_Msk               (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos)   /*!< 0xFFFFFFFF */\r\n#define QUADSPI_DLR_DL                   QUADSPI_DLR_DL_Msk                    /*!< DL[31:0]: Data Length */\r\n\r\n/******************  Bit definition for QUADSPI_CCR register  ******************/\r\n#define QUADSPI_CCR_INSTRUCTION_Pos      (0U)                                  \r\n#define QUADSPI_CCR_INSTRUCTION_Msk      (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */\r\n#define QUADSPI_CCR_INSTRUCTION          QUADSPI_CCR_INSTRUCTION_Msk           /*!< INSTRUCTION[7:0]: Instruction    */\r\n#define QUADSPI_CCR_INSTRUCTION_0        (0x01U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */\r\n#define QUADSPI_CCR_INSTRUCTION_1        (0x02U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */\r\n#define QUADSPI_CCR_INSTRUCTION_2        (0x04U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */\r\n#define QUADSPI_CCR_INSTRUCTION_3        (0x08U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */\r\n#define QUADSPI_CCR_INSTRUCTION_4        (0x10U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */\r\n#define QUADSPI_CCR_INSTRUCTION_5        (0x20U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */\r\n#define QUADSPI_CCR_INSTRUCTION_6        (0x40U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */\r\n#define QUADSPI_CCR_INSTRUCTION_7        (0x80U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */\r\n#define QUADSPI_CCR_IMODE_Pos            (8U)                                  \r\n#define QUADSPI_CCR_IMODE_Msk            (0x3U << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000300 */\r\n#define QUADSPI_CCR_IMODE                QUADSPI_CCR_IMODE_Msk                 /*!< IMODE[1:0]: Instruction Mode      */\r\n#define QUADSPI_CCR_IMODE_0              (0x1U << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000100 */\r\n#define QUADSPI_CCR_IMODE_1              (0x2U << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000200 */\r\n#define QUADSPI_CCR_ADMODE_Pos           (10U)                                 \r\n#define QUADSPI_CCR_ADMODE_Msk           (0x3U << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000C00 */\r\n#define QUADSPI_CCR_ADMODE               QUADSPI_CCR_ADMODE_Msk                /*!< ADMODE[1:0]: Address Mode         */\r\n#define QUADSPI_CCR_ADMODE_0             (0x1U << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000400 */\r\n#define QUADSPI_CCR_ADMODE_1             (0x2U << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000800 */\r\n#define QUADSPI_CCR_ADSIZE_Pos           (12U)                                 \r\n#define QUADSPI_CCR_ADSIZE_Msk           (0x3U << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00003000 */\r\n#define QUADSPI_CCR_ADSIZE               QUADSPI_CCR_ADSIZE_Msk                /*!< ADSIZE[1:0]: Address Size         */\r\n#define QUADSPI_CCR_ADSIZE_0             (0x1U << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00001000 */\r\n#define QUADSPI_CCR_ADSIZE_1             (0x2U << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00002000 */\r\n#define QUADSPI_CCR_ABMODE_Pos           (14U)                                 \r\n#define QUADSPI_CCR_ABMODE_Msk           (0x3U << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x0000C000 */\r\n#define QUADSPI_CCR_ABMODE               QUADSPI_CCR_ABMODE_Msk                /*!< ABMODE[1:0]: Alternate Bytes Mode */\r\n#define QUADSPI_CCR_ABMODE_0             (0x1U << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x00004000 */\r\n#define QUADSPI_CCR_ABMODE_1             (0x2U << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x00008000 */\r\n#define QUADSPI_CCR_ABSIZE_Pos           (16U)                                 \r\n#define QUADSPI_CCR_ABSIZE_Msk           (0x3U << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00030000 */\r\n#define QUADSPI_CCR_ABSIZE               QUADSPI_CCR_ABSIZE_Msk                /*!< ABSIZE[1:0]: Instruction Mode     */\r\n#define QUADSPI_CCR_ABSIZE_0             (0x1U << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00010000 */\r\n#define QUADSPI_CCR_ABSIZE_1             (0x2U << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00020000 */\r\n#define QUADSPI_CCR_DCYC_Pos             (18U)                                 \r\n#define QUADSPI_CCR_DCYC_Msk             (0x1FU << QUADSPI_CCR_DCYC_Pos)       /*!< 0x007C0000 */\r\n#define QUADSPI_CCR_DCYC                 QUADSPI_CCR_DCYC_Msk                  /*!< DCYC[4:0]: Dummy Cycles           */\r\n#define QUADSPI_CCR_DCYC_0               (0x01U << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00040000 */\r\n#define QUADSPI_CCR_DCYC_1               (0x02U << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00080000 */\r\n#define QUADSPI_CCR_DCYC_2               (0x04U << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00100000 */\r\n#define QUADSPI_CCR_DCYC_3               (0x08U << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00200000 */\r\n#define QUADSPI_CCR_DCYC_4               (0x10U << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00400000 */\r\n#define QUADSPI_CCR_DMODE_Pos            (24U)                                 \r\n#define QUADSPI_CCR_DMODE_Msk            (0x3U << QUADSPI_CCR_DMODE_Pos)       /*!< 0x03000000 */\r\n#define QUADSPI_CCR_DMODE                QUADSPI_CCR_DMODE_Msk                 /*!< DMODE[1:0]: Data Mode              */\r\n#define QUADSPI_CCR_DMODE_0              (0x1U << QUADSPI_CCR_DMODE_Pos)       /*!< 0x01000000 */\r\n#define QUADSPI_CCR_DMODE_1              (0x2U << QUADSPI_CCR_DMODE_Pos)       /*!< 0x02000000 */\r\n#define QUADSPI_CCR_FMODE_Pos            (26U)                                 \r\n#define QUADSPI_CCR_FMODE_Msk            (0x3U << QUADSPI_CCR_FMODE_Pos)       /*!< 0x0C000000 */\r\n#define QUADSPI_CCR_FMODE                QUADSPI_CCR_FMODE_Msk                 /*!< FMODE[1:0]: Functional Mode        */\r\n#define QUADSPI_CCR_FMODE_0              (0x1U << QUADSPI_CCR_FMODE_Pos)       /*!< 0x04000000 */\r\n#define QUADSPI_CCR_FMODE_1              (0x2U << QUADSPI_CCR_FMODE_Pos)       /*!< 0x08000000 */\r\n#define QUADSPI_CCR_SIOO_Pos             (28U)                                 \r\n#define QUADSPI_CCR_SIOO_Msk             (0x1U << QUADSPI_CCR_SIOO_Pos)        /*!< 0x10000000 */\r\n#define QUADSPI_CCR_SIOO                 QUADSPI_CCR_SIOO_Msk                  /*!< SIOO: Send Instruction Only Once Mode */\r\n#define QUADSPI_CCR_DHHC_Pos             (30U)                                 \r\n#define QUADSPI_CCR_DHHC_Msk             (0x1U << QUADSPI_CCR_DHHC_Pos)        /*!< 0x40000000 */\r\n#define QUADSPI_CCR_DHHC                 QUADSPI_CCR_DHHC_Msk                  /*!< DHHC: Delay Half Hclk Cycle           */\r\n#define QUADSPI_CCR_DDRM_Pos             (31U)                                 \r\n#define QUADSPI_CCR_DDRM_Msk             (0x1U << QUADSPI_CCR_DDRM_Pos)        /*!< 0x80000000 */\r\n#define QUADSPI_CCR_DDRM                 QUADSPI_CCR_DDRM_Msk                  /*!< DDRM: Double Data Rate Mode           */\r\n/******************  Bit definition for QUADSPI_AR register  *******************/\r\n#define QUADSPI_AR_ADDRESS_Pos           (0U)                                  \r\n#define QUADSPI_AR_ADDRESS_Msk           (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */\r\n#define QUADSPI_AR_ADDRESS               QUADSPI_AR_ADDRESS_Msk                /*!< ADDRESS[31:0]: Address */\r\n\r\n/******************  Bit definition for QUADSPI_ABR register  ******************/\r\n#define QUADSPI_ABR_ALTERNATE_Pos        (0U)                                  \r\n#define QUADSPI_ABR_ALTERNATE_Msk        (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */\r\n#define QUADSPI_ABR_ALTERNATE            QUADSPI_ABR_ALTERNATE_Msk             /*!< ALTERNATE[31:0]: Alternate Bytes */\r\n\r\n/******************  Bit definition for QUADSPI_DR register  *******************/\r\n#define QUADSPI_DR_DATA_Pos              (0U)                                  \r\n#define QUADSPI_DR_DATA_Msk              (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos)  /*!< 0xFFFFFFFF */\r\n#define QUADSPI_DR_DATA                  QUADSPI_DR_DATA_Msk                   /*!< DATA[31:0]: Data */\r\n\r\n/******************  Bit definition for QUADSPI_PSMKR register  ****************/\r\n#define QUADSPI_PSMKR_MASK_Pos           (0U)                                  \r\n#define QUADSPI_PSMKR_MASK_Msk           (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */\r\n#define QUADSPI_PSMKR_MASK               QUADSPI_PSMKR_MASK_Msk                /*!< MASK[31:0]: Status Mask */\r\n\r\n/******************  Bit definition for QUADSPI_PSMAR register  ****************/\r\n#define QUADSPI_PSMAR_MATCH_Pos          (0U)                                  \r\n#define QUADSPI_PSMAR_MATCH_Msk          (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */\r\n#define QUADSPI_PSMAR_MATCH              QUADSPI_PSMAR_MATCH_Msk               /*!< MATCH[31:0]: Status Match */\r\n\r\n/******************  Bit definition for QUADSPI_PIR register  *****************/\r\n#define QUADSPI_PIR_INTERVAL_Pos         (0U)                                  \r\n#define QUADSPI_PIR_INTERVAL_Msk         (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */\r\n#define QUADSPI_PIR_INTERVAL             QUADSPI_PIR_INTERVAL_Msk              /*!< INTERVAL[15:0]: Polling Interval */\r\n\r\n/******************  Bit definition for QUADSPI_LPTR register  *****************/\r\n#define QUADSPI_LPTR_TIMEOUT_Pos         (0U)                                  \r\n#define QUADSPI_LPTR_TIMEOUT_Msk         (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */\r\n#define QUADSPI_LPTR_TIMEOUT             QUADSPI_LPTR_TIMEOUT_Msk              /*!< TIMEOUT[15:0]: Timeout period */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                         Reset and Clock Control            */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bit definition for RCC_CR register  ********************/\r\n#define RCC_CR_HSION_Pos                   (0U)                                \r\n#define RCC_CR_HSION_Msk                   (0x1U << RCC_CR_HSION_Pos)          /*!< 0x00000001 */\r\n#define RCC_CR_HSION                       RCC_CR_HSION_Msk                    \r\n#define RCC_CR_HSIRDY_Pos                  (1U)                                \r\n#define RCC_CR_HSIRDY_Msk                  (0x1U << RCC_CR_HSIRDY_Pos)         /*!< 0x00000002 */\r\n#define RCC_CR_HSIRDY                      RCC_CR_HSIRDY_Msk                   \r\n#define RCC_CR_HSITRIM_Pos                 (3U)                                \r\n#define RCC_CR_HSITRIM_Msk                 (0x1FU << RCC_CR_HSITRIM_Pos)       /*!< 0x000000F8 */\r\n#define RCC_CR_HSITRIM                     RCC_CR_HSITRIM_Msk                  \r\n#define RCC_CR_HSITRIM_0                   (0x01U << RCC_CR_HSITRIM_Pos)       /*!< 0x00000008 */\r\n#define RCC_CR_HSITRIM_1                   (0x02U << RCC_CR_HSITRIM_Pos)       /*!< 0x00000010 */\r\n#define RCC_CR_HSITRIM_2                   (0x04U << RCC_CR_HSITRIM_Pos)       /*!< 0x00000020 */\r\n#define RCC_CR_HSITRIM_3                   (0x08U << RCC_CR_HSITRIM_Pos)       /*!< 0x00000040 */\r\n#define RCC_CR_HSITRIM_4                   (0x10U << RCC_CR_HSITRIM_Pos)       /*!< 0x00000080 */\r\n#define RCC_CR_HSICAL_Pos                  (8U)                                \r\n#define RCC_CR_HSICAL_Msk                  (0xFFU << RCC_CR_HSICAL_Pos)        /*!< 0x0000FF00 */\r\n#define RCC_CR_HSICAL                      RCC_CR_HSICAL_Msk                   \r\n#define RCC_CR_HSICAL_0                    (0x01U << RCC_CR_HSICAL_Pos)        /*!< 0x00000100 */\r\n#define RCC_CR_HSICAL_1                    (0x02U << RCC_CR_HSICAL_Pos)        /*!< 0x00000200 */\r\n#define RCC_CR_HSICAL_2                    (0x04U << RCC_CR_HSICAL_Pos)        /*!< 0x00000400 */\r\n#define RCC_CR_HSICAL_3                    (0x08U << RCC_CR_HSICAL_Pos)        /*!< 0x00000800 */\r\n#define RCC_CR_HSICAL_4                    (0x10U << RCC_CR_HSICAL_Pos)        /*!< 0x00001000 */\r\n#define RCC_CR_HSICAL_5                    (0x20U << RCC_CR_HSICAL_Pos)        /*!< 0x00002000 */\r\n#define RCC_CR_HSICAL_6                    (0x40U << RCC_CR_HSICAL_Pos)        /*!< 0x00004000 */\r\n#define RCC_CR_HSICAL_7                    (0x80U << RCC_CR_HSICAL_Pos)        /*!< 0x00008000 */\r\n#define RCC_CR_HSEON_Pos                   (16U)                               \r\n#define RCC_CR_HSEON_Msk                   (0x1U << RCC_CR_HSEON_Pos)          /*!< 0x00010000 */\r\n#define RCC_CR_HSEON                       RCC_CR_HSEON_Msk                    \r\n#define RCC_CR_HSERDY_Pos                  (17U)                               \r\n#define RCC_CR_HSERDY_Msk                  (0x1U << RCC_CR_HSERDY_Pos)         /*!< 0x00020000 */\r\n#define RCC_CR_HSERDY                      RCC_CR_HSERDY_Msk                   \r\n#define RCC_CR_HSEBYP_Pos                  (18U)                               \r\n#define RCC_CR_HSEBYP_Msk                  (0x1U << RCC_CR_HSEBYP_Pos)         /*!< 0x00040000 */\r\n#define RCC_CR_HSEBYP                      RCC_CR_HSEBYP_Msk                   \r\n#define RCC_CR_CSSON_Pos                   (19U)                               \r\n#define RCC_CR_CSSON_Msk                   (0x1U << RCC_CR_CSSON_Pos)          /*!< 0x00080000 */\r\n#define RCC_CR_CSSON                       RCC_CR_CSSON_Msk                    \r\n#define RCC_CR_PLLON_Pos                   (24U)                               \r\n#define RCC_CR_PLLON_Msk                   (0x1U << RCC_CR_PLLON_Pos)          /*!< 0x01000000 */\r\n#define RCC_CR_PLLON                       RCC_CR_PLLON_Msk                    \r\n#define RCC_CR_PLLRDY_Pos                  (25U)                               \r\n#define RCC_CR_PLLRDY_Msk                  (0x1U << RCC_CR_PLLRDY_Pos)         /*!< 0x02000000 */\r\n#define RCC_CR_PLLRDY                      RCC_CR_PLLRDY_Msk                   \r\n#define RCC_CR_PLLI2SON_Pos                (26U)                               \r\n#define RCC_CR_PLLI2SON_Msk                (0x1U << RCC_CR_PLLI2SON_Pos)       /*!< 0x04000000 */\r\n#define RCC_CR_PLLI2SON                    RCC_CR_PLLI2SON_Msk                 \r\n#define RCC_CR_PLLI2SRDY_Pos               (27U)                               \r\n#define RCC_CR_PLLI2SRDY_Msk               (0x1U << RCC_CR_PLLI2SRDY_Pos)      /*!< 0x08000000 */\r\n#define RCC_CR_PLLI2SRDY                   RCC_CR_PLLI2SRDY_Msk                \r\n#define RCC_CR_PLLSAION_Pos                (28U)                               \r\n#define RCC_CR_PLLSAION_Msk                (0x1U << RCC_CR_PLLSAION_Pos)       /*!< 0x10000000 */\r\n#define RCC_CR_PLLSAION                    RCC_CR_PLLSAION_Msk                 \r\n#define RCC_CR_PLLSAIRDY_Pos               (29U)                               \r\n#define RCC_CR_PLLSAIRDY_Msk               (0x1U << RCC_CR_PLLSAIRDY_Pos)      /*!< 0x20000000 */\r\n#define RCC_CR_PLLSAIRDY                   RCC_CR_PLLSAIRDY_Msk                \r\n\r\n/********************  Bit definition for RCC_PLLCFGR register  ***************/\r\n#define RCC_PLLCFGR_PLLM_Pos               (0U)                                \r\n#define RCC_PLLCFGR_PLLM_Msk               (0x3FU << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x0000003F */\r\n#define RCC_PLLCFGR_PLLM                   RCC_PLLCFGR_PLLM_Msk                \r\n#define RCC_PLLCFGR_PLLM_0                 (0x01U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000001 */\r\n#define RCC_PLLCFGR_PLLM_1                 (0x02U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000002 */\r\n#define RCC_PLLCFGR_PLLM_2                 (0x04U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000004 */\r\n#define RCC_PLLCFGR_PLLM_3                 (0x08U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000008 */\r\n#define RCC_PLLCFGR_PLLM_4                 (0x10U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000010 */\r\n#define RCC_PLLCFGR_PLLM_5                 (0x20U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000020 */\r\n#define RCC_PLLCFGR_PLLN_Pos               (6U)                                \r\n#define RCC_PLLCFGR_PLLN_Msk               (0x1FFU << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00007FC0 */\r\n#define RCC_PLLCFGR_PLLN                   RCC_PLLCFGR_PLLN_Msk                \r\n#define RCC_PLLCFGR_PLLN_0                 (0x001U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000040 */\r\n#define RCC_PLLCFGR_PLLN_1                 (0x002U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000080 */\r\n#define RCC_PLLCFGR_PLLN_2                 (0x004U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000100 */\r\n#define RCC_PLLCFGR_PLLN_3                 (0x008U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000200 */\r\n#define RCC_PLLCFGR_PLLN_4                 (0x010U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000400 */\r\n#define RCC_PLLCFGR_PLLN_5                 (0x020U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000800 */\r\n#define RCC_PLLCFGR_PLLN_6                 (0x040U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00001000 */\r\n#define RCC_PLLCFGR_PLLN_7                 (0x080U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00002000 */\r\n#define RCC_PLLCFGR_PLLN_8                 (0x100U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00004000 */\r\n#define RCC_PLLCFGR_PLLP_Pos               (16U)                               \r\n#define RCC_PLLCFGR_PLLP_Msk               (0x3U << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00030000 */\r\n#define RCC_PLLCFGR_PLLP                   RCC_PLLCFGR_PLLP_Msk                \r\n#define RCC_PLLCFGR_PLLP_0                 (0x1U << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00010000 */\r\n#define RCC_PLLCFGR_PLLP_1                 (0x2U << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00020000 */\r\n#define RCC_PLLCFGR_PLLSRC_Pos             (22U)                               \r\n#define RCC_PLLCFGR_PLLSRC_Msk             (0x1U << RCC_PLLCFGR_PLLSRC_Pos)    /*!< 0x00400000 */\r\n#define RCC_PLLCFGR_PLLSRC                 RCC_PLLCFGR_PLLSRC_Msk              \r\n#define RCC_PLLCFGR_PLLSRC_HSE_Pos         (22U)                               \r\n#define RCC_PLLCFGR_PLLSRC_HSE_Msk         (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */\r\n#define RCC_PLLCFGR_PLLSRC_HSE             RCC_PLLCFGR_PLLSRC_HSE_Msk          \r\n#define RCC_PLLCFGR_PLLSRC_HSI             0x00000000U                         \r\n#define RCC_PLLCFGR_PLLQ_Pos               (24U)                               \r\n#define RCC_PLLCFGR_PLLQ_Msk               (0xFU << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x0F000000 */\r\n#define RCC_PLLCFGR_PLLQ                   RCC_PLLCFGR_PLLQ_Msk                \r\n#define RCC_PLLCFGR_PLLQ_0                 (0x1U << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x01000000 */\r\n#define RCC_PLLCFGR_PLLQ_1                 (0x2U << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x02000000 */\r\n#define RCC_PLLCFGR_PLLQ_2                 (0x4U << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x04000000 */\r\n#define RCC_PLLCFGR_PLLQ_3                 (0x8U << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x08000000 */\r\n\r\n\r\n/********************  Bit definition for RCC_CFGR register  ******************/\r\n/*!< SW configuration */\r\n#define RCC_CFGR_SW_Pos                    (0U)                                \r\n#define RCC_CFGR_SW_Msk                    (0x3U << RCC_CFGR_SW_Pos)           /*!< 0x00000003 */\r\n#define RCC_CFGR_SW                        RCC_CFGR_SW_Msk                     /*!< SW[1:0] bits (System clock Switch) */\r\n#define RCC_CFGR_SW_0                      (0x1U << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */\r\n#define RCC_CFGR_SW_1                      (0x2U << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */\r\n#define RCC_CFGR_SW_HSI                    0x00000000U                         /*!< HSI selected as system clock */\r\n#define RCC_CFGR_SW_HSE                    0x00000001U                         /*!< HSE selected as system clock */\r\n#define RCC_CFGR_SW_PLL                    0x00000002U                         /*!< PLL selected as system clock */\r\n\r\n/*!< SWS configuration */\r\n#define RCC_CFGR_SWS_Pos                   (2U)                                \r\n#define RCC_CFGR_SWS_Msk                   (0x3U << RCC_CFGR_SWS_Pos)          /*!< 0x0000000C */\r\n#define RCC_CFGR_SWS                       RCC_CFGR_SWS_Msk                    /*!< SWS[1:0] bits (System Clock Switch Status) */\r\n#define RCC_CFGR_SWS_0                     (0x1U << RCC_CFGR_SWS_Pos)          /*!< 0x00000004 */\r\n#define RCC_CFGR_SWS_1                     (0x2U << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */\r\n#define RCC_CFGR_SWS_HSI                   0x00000000U                         /*!< HSI oscillator used as system clock */\r\n#define RCC_CFGR_SWS_HSE                   0x00000004U                         /*!< HSE oscillator used as system clock */\r\n#define RCC_CFGR_SWS_PLL                   0x00000008U                         /*!< PLL used as system clock */\r\n\r\n/*!< HPRE configuration */\r\n#define RCC_CFGR_HPRE_Pos                  (4U)                                \r\n#define RCC_CFGR_HPRE_Msk                  (0xFU << RCC_CFGR_HPRE_Pos)         /*!< 0x000000F0 */\r\n#define RCC_CFGR_HPRE                      RCC_CFGR_HPRE_Msk                   /*!< HPRE[3:0] bits (AHB prescaler) */\r\n#define RCC_CFGR_HPRE_0                    (0x1U << RCC_CFGR_HPRE_Pos)         /*!< 0x00000010 */\r\n#define RCC_CFGR_HPRE_1                    (0x2U << RCC_CFGR_HPRE_Pos)         /*!< 0x00000020 */\r\n#define RCC_CFGR_HPRE_2                    (0x4U << RCC_CFGR_HPRE_Pos)         /*!< 0x00000040 */\r\n#define RCC_CFGR_HPRE_3                    (0x8U << RCC_CFGR_HPRE_Pos)         /*!< 0x00000080 */\r\n\r\n#define RCC_CFGR_HPRE_DIV1                 0x00000000U                         /*!< SYSCLK not divided */\r\n#define RCC_CFGR_HPRE_DIV2                 0x00000080U                         /*!< SYSCLK divided by 2 */\r\n#define RCC_CFGR_HPRE_DIV4                 0x00000090U                         /*!< SYSCLK divided by 4 */\r\n#define RCC_CFGR_HPRE_DIV8                 0x000000A0U                         /*!< SYSCLK divided by 8 */\r\n#define RCC_CFGR_HPRE_DIV16                0x000000B0U                         /*!< SYSCLK divided by 16 */\r\n#define RCC_CFGR_HPRE_DIV64                0x000000C0U                         /*!< SYSCLK divided by 64 */\r\n#define RCC_CFGR_HPRE_DIV128               0x000000D0U                         /*!< SYSCLK divided by 128 */\r\n#define RCC_CFGR_HPRE_DIV256               0x000000E0U                         /*!< SYSCLK divided by 256 */\r\n#define RCC_CFGR_HPRE_DIV512               0x000000F0U                         /*!< SYSCLK divided by 512 */\r\n\r\n/*!< PPRE1 configuration */\r\n#define RCC_CFGR_PPRE1_Pos                 (10U)                               \r\n#define RCC_CFGR_PPRE1_Msk                 (0x7U << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001C00 */\r\n#define RCC_CFGR_PPRE1                     RCC_CFGR_PPRE1_Msk                  /*!< PRE1[2:0] bits (APB1 prescaler) */\r\n#define RCC_CFGR_PPRE1_0                   (0x1U << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000400 */\r\n#define RCC_CFGR_PPRE1_1                   (0x2U << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000800 */\r\n#define RCC_CFGR_PPRE1_2                   (0x4U << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001000 */\r\n\r\n#define RCC_CFGR_PPRE1_DIV1                0x00000000U                         /*!< HCLK not divided */\r\n#define RCC_CFGR_PPRE1_DIV2                0x00001000U                         /*!< HCLK divided by 2 */\r\n#define RCC_CFGR_PPRE1_DIV4                0x00001400U                         /*!< HCLK divided by 4 */\r\n#define RCC_CFGR_PPRE1_DIV8                0x00001800U                         /*!< HCLK divided by 8 */\r\n#define RCC_CFGR_PPRE1_DIV16               0x00001C00U                         /*!< HCLK divided by 16 */\r\n\r\n/*!< PPRE2 configuration */\r\n#define RCC_CFGR_PPRE2_Pos                 (13U)                               \r\n#define RCC_CFGR_PPRE2_Msk                 (0x7U << RCC_CFGR_PPRE2_Pos)        /*!< 0x0000E000 */\r\n#define RCC_CFGR_PPRE2                     RCC_CFGR_PPRE2_Msk                  /*!< PRE2[2:0] bits (APB2 prescaler) */\r\n#define RCC_CFGR_PPRE2_0                   (0x1U << RCC_CFGR_PPRE2_Pos)        /*!< 0x00002000 */\r\n#define RCC_CFGR_PPRE2_1                   (0x2U << RCC_CFGR_PPRE2_Pos)        /*!< 0x00004000 */\r\n#define RCC_CFGR_PPRE2_2                   (0x4U << RCC_CFGR_PPRE2_Pos)        /*!< 0x00008000 */\r\n\r\n#define RCC_CFGR_PPRE2_DIV1                0x00000000U                         /*!< HCLK not divided */\r\n#define RCC_CFGR_PPRE2_DIV2                0x00008000U                         /*!< HCLK divided by 2 */\r\n#define RCC_CFGR_PPRE2_DIV4                0x0000A000U                         /*!< HCLK divided by 4 */\r\n#define RCC_CFGR_PPRE2_DIV8                0x0000C000U                         /*!< HCLK divided by 8 */\r\n#define RCC_CFGR_PPRE2_DIV16               0x0000E000U                         /*!< HCLK divided by 16 */\r\n\r\n/*!< RTCPRE configuration */\r\n#define RCC_CFGR_RTCPRE_Pos                (16U)                               \r\n#define RCC_CFGR_RTCPRE_Msk                (0x1FU << RCC_CFGR_RTCPRE_Pos)      /*!< 0x001F0000 */\r\n#define RCC_CFGR_RTCPRE                    RCC_CFGR_RTCPRE_Msk                 \r\n#define RCC_CFGR_RTCPRE_0                  (0x01U << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00010000 */\r\n#define RCC_CFGR_RTCPRE_1                  (0x02U << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00020000 */\r\n#define RCC_CFGR_RTCPRE_2                  (0x04U << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00040000 */\r\n#define RCC_CFGR_RTCPRE_3                  (0x08U << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00080000 */\r\n#define RCC_CFGR_RTCPRE_4                  (0x10U << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00100000 */\r\n\r\n/*!< MCO1 configuration */\r\n#define RCC_CFGR_MCO1_Pos                  (21U)                               \r\n#define RCC_CFGR_MCO1_Msk                  (0x3U << RCC_CFGR_MCO1_Pos)         /*!< 0x00600000 */\r\n#define RCC_CFGR_MCO1                      RCC_CFGR_MCO1_Msk                   \r\n#define RCC_CFGR_MCO1_0                    (0x1U << RCC_CFGR_MCO1_Pos)         /*!< 0x00200000 */\r\n#define RCC_CFGR_MCO1_1                    (0x2U << RCC_CFGR_MCO1_Pos)         /*!< 0x00400000 */\r\n\r\n#define RCC_CFGR_I2SSRC_Pos                (23U)                               \r\n#define RCC_CFGR_I2SSRC_Msk                (0x1U << RCC_CFGR_I2SSRC_Pos)       /*!< 0x00800000 */\r\n#define RCC_CFGR_I2SSRC                    RCC_CFGR_I2SSRC_Msk                 \r\n\r\n#define RCC_CFGR_MCO1PRE_Pos               (24U)                               \r\n#define RCC_CFGR_MCO1PRE_Msk               (0x7U << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x07000000 */\r\n#define RCC_CFGR_MCO1PRE                   RCC_CFGR_MCO1PRE_Msk                \r\n#define RCC_CFGR_MCO1PRE_0                 (0x1U << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x01000000 */\r\n#define RCC_CFGR_MCO1PRE_1                 (0x2U << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x02000000 */\r\n#define RCC_CFGR_MCO1PRE_2                 (0x4U << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x04000000 */\r\n\r\n#define RCC_CFGR_MCO2PRE_Pos               (27U)                               \r\n#define RCC_CFGR_MCO2PRE_Msk               (0x7U << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x38000000 */\r\n#define RCC_CFGR_MCO2PRE                   RCC_CFGR_MCO2PRE_Msk                \r\n#define RCC_CFGR_MCO2PRE_0                 (0x1U << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x08000000 */\r\n#define RCC_CFGR_MCO2PRE_1                 (0x2U << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x10000000 */\r\n#define RCC_CFGR_MCO2PRE_2                 (0x4U << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x20000000 */\r\n\r\n#define RCC_CFGR_MCO2_Pos                  (30U)                               \r\n#define RCC_CFGR_MCO2_Msk                  (0x3U << RCC_CFGR_MCO2_Pos)         /*!< 0xC0000000 */\r\n#define RCC_CFGR_MCO2                      RCC_CFGR_MCO2_Msk                   \r\n#define RCC_CFGR_MCO2_0                    (0x1U << RCC_CFGR_MCO2_Pos)         /*!< 0x40000000 */\r\n#define RCC_CFGR_MCO2_1                    (0x2U << RCC_CFGR_MCO2_Pos)         /*!< 0x80000000 */\r\n\r\n/********************  Bit definition for RCC_CIR register  *******************/\r\n#define RCC_CIR_LSIRDYF_Pos                (0U)                                \r\n#define RCC_CIR_LSIRDYF_Msk                (0x1U << RCC_CIR_LSIRDYF_Pos)       /*!< 0x00000001 */\r\n#define RCC_CIR_LSIRDYF                    RCC_CIR_LSIRDYF_Msk                 \r\n#define RCC_CIR_LSERDYF_Pos                (1U)                                \r\n#define RCC_CIR_LSERDYF_Msk                (0x1U << RCC_CIR_LSERDYF_Pos)       /*!< 0x00000002 */\r\n#define RCC_CIR_LSERDYF                    RCC_CIR_LSERDYF_Msk                 \r\n#define RCC_CIR_HSIRDYF_Pos                (2U)                                \r\n#define RCC_CIR_HSIRDYF_Msk                (0x1U << RCC_CIR_HSIRDYF_Pos)       /*!< 0x00000004 */\r\n#define RCC_CIR_HSIRDYF                    RCC_CIR_HSIRDYF_Msk                 \r\n#define RCC_CIR_HSERDYF_Pos                (3U)                                \r\n#define RCC_CIR_HSERDYF_Msk                (0x1U << RCC_CIR_HSERDYF_Pos)       /*!< 0x00000008 */\r\n#define RCC_CIR_HSERDYF                    RCC_CIR_HSERDYF_Msk                 \r\n#define RCC_CIR_PLLRDYF_Pos                (4U)                                \r\n#define RCC_CIR_PLLRDYF_Msk                (0x1U << RCC_CIR_PLLRDYF_Pos)       /*!< 0x00000010 */\r\n#define RCC_CIR_PLLRDYF                    RCC_CIR_PLLRDYF_Msk                 \r\n#define RCC_CIR_PLLI2SRDYF_Pos             (5U)                                \r\n#define RCC_CIR_PLLI2SRDYF_Msk             (0x1U << RCC_CIR_PLLI2SRDYF_Pos)    /*!< 0x00000020 */\r\n#define RCC_CIR_PLLI2SRDYF                 RCC_CIR_PLLI2SRDYF_Msk              \r\n#define RCC_CIR_PLLSAIRDYF_Pos             (6U)                                \r\n#define RCC_CIR_PLLSAIRDYF_Msk             (0x1U << RCC_CIR_PLLSAIRDYF_Pos)    /*!< 0x00000040 */\r\n#define RCC_CIR_PLLSAIRDYF                 RCC_CIR_PLLSAIRDYF_Msk              \r\n#define RCC_CIR_CSSF_Pos                   (7U)                                \r\n#define RCC_CIR_CSSF_Msk                   (0x1U << RCC_CIR_CSSF_Pos)          /*!< 0x00000080 */\r\n#define RCC_CIR_CSSF                       RCC_CIR_CSSF_Msk                    \r\n#define RCC_CIR_LSIRDYIE_Pos               (8U)                                \r\n#define RCC_CIR_LSIRDYIE_Msk               (0x1U << RCC_CIR_LSIRDYIE_Pos)      /*!< 0x00000100 */\r\n#define RCC_CIR_LSIRDYIE                   RCC_CIR_LSIRDYIE_Msk                \r\n#define RCC_CIR_LSERDYIE_Pos               (9U)                                \r\n#define RCC_CIR_LSERDYIE_Msk               (0x1U << RCC_CIR_LSERDYIE_Pos)      /*!< 0x00000200 */\r\n#define RCC_CIR_LSERDYIE                   RCC_CIR_LSERDYIE_Msk                \r\n#define RCC_CIR_HSIRDYIE_Pos               (10U)                               \r\n#define RCC_CIR_HSIRDYIE_Msk               (0x1U << RCC_CIR_HSIRDYIE_Pos)      /*!< 0x00000400 */\r\n#define RCC_CIR_HSIRDYIE                   RCC_CIR_HSIRDYIE_Msk                \r\n#define RCC_CIR_HSERDYIE_Pos               (11U)                               \r\n#define RCC_CIR_HSERDYIE_Msk               (0x1U << RCC_CIR_HSERDYIE_Pos)      /*!< 0x00000800 */\r\n#define RCC_CIR_HSERDYIE                   RCC_CIR_HSERDYIE_Msk                \r\n#define RCC_CIR_PLLRDYIE_Pos               (12U)                               \r\n#define RCC_CIR_PLLRDYIE_Msk               (0x1U << RCC_CIR_PLLRDYIE_Pos)      /*!< 0x00001000 */\r\n#define RCC_CIR_PLLRDYIE                   RCC_CIR_PLLRDYIE_Msk                \r\n#define RCC_CIR_PLLI2SRDYIE_Pos            (13U)                               \r\n#define RCC_CIR_PLLI2SRDYIE_Msk            (0x1U << RCC_CIR_PLLI2SRDYIE_Pos)   /*!< 0x00002000 */\r\n#define RCC_CIR_PLLI2SRDYIE                RCC_CIR_PLLI2SRDYIE_Msk             \r\n#define RCC_CIR_PLLSAIRDYIE_Pos            (14U)                               \r\n#define RCC_CIR_PLLSAIRDYIE_Msk            (0x1U << RCC_CIR_PLLSAIRDYIE_Pos)   /*!< 0x00004000 */\r\n#define RCC_CIR_PLLSAIRDYIE                RCC_CIR_PLLSAIRDYIE_Msk             \r\n#define RCC_CIR_LSIRDYC_Pos                (16U)                               \r\n#define RCC_CIR_LSIRDYC_Msk                (0x1U << RCC_CIR_LSIRDYC_Pos)       /*!< 0x00010000 */\r\n#define RCC_CIR_LSIRDYC                    RCC_CIR_LSIRDYC_Msk                 \r\n#define RCC_CIR_LSERDYC_Pos                (17U)                               \r\n#define RCC_CIR_LSERDYC_Msk                (0x1U << RCC_CIR_LSERDYC_Pos)       /*!< 0x00020000 */\r\n#define RCC_CIR_LSERDYC                    RCC_CIR_LSERDYC_Msk                 \r\n#define RCC_CIR_HSIRDYC_Pos                (18U)                               \r\n#define RCC_CIR_HSIRDYC_Msk                (0x1U << RCC_CIR_HSIRDYC_Pos)       /*!< 0x00040000 */\r\n#define RCC_CIR_HSIRDYC                    RCC_CIR_HSIRDYC_Msk                 \r\n#define RCC_CIR_HSERDYC_Pos                (19U)                               \r\n#define RCC_CIR_HSERDYC_Msk                (0x1U << RCC_CIR_HSERDYC_Pos)       /*!< 0x00080000 */\r\n#define RCC_CIR_HSERDYC                    RCC_CIR_HSERDYC_Msk                 \r\n#define RCC_CIR_PLLRDYC_Pos                (20U)                               \r\n#define RCC_CIR_PLLRDYC_Msk                (0x1U << RCC_CIR_PLLRDYC_Pos)       /*!< 0x00100000 */\r\n#define RCC_CIR_PLLRDYC                    RCC_CIR_PLLRDYC_Msk                 \r\n#define RCC_CIR_PLLI2SRDYC_Pos             (21U)                               \r\n#define RCC_CIR_PLLI2SRDYC_Msk             (0x1U << RCC_CIR_PLLI2SRDYC_Pos)    /*!< 0x00200000 */\r\n#define RCC_CIR_PLLI2SRDYC                 RCC_CIR_PLLI2SRDYC_Msk              \r\n#define RCC_CIR_PLLSAIRDYC_Pos             (22U)                               \r\n#define RCC_CIR_PLLSAIRDYC_Msk             (0x1U << RCC_CIR_PLLSAIRDYC_Pos)    /*!< 0x00400000 */\r\n#define RCC_CIR_PLLSAIRDYC                 RCC_CIR_PLLSAIRDYC_Msk              \r\n#define RCC_CIR_CSSC_Pos                   (23U)                               \r\n#define RCC_CIR_CSSC_Msk                   (0x1U << RCC_CIR_CSSC_Pos)          /*!< 0x00800000 */\r\n#define RCC_CIR_CSSC                       RCC_CIR_CSSC_Msk                    \r\n\r\n/********************  Bit definition for RCC_AHB1RSTR register  **************/\r\n#define RCC_AHB1RSTR_GPIOARST_Pos          (0U)                                \r\n#define RCC_AHB1RSTR_GPIOARST_Msk          (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */\r\n#define RCC_AHB1RSTR_GPIOARST              RCC_AHB1RSTR_GPIOARST_Msk           \r\n#define RCC_AHB1RSTR_GPIOBRST_Pos          (1U)                                \r\n#define RCC_AHB1RSTR_GPIOBRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */\r\n#define RCC_AHB1RSTR_GPIOBRST              RCC_AHB1RSTR_GPIOBRST_Msk           \r\n#define RCC_AHB1RSTR_GPIOCRST_Pos          (2U)                                \r\n#define RCC_AHB1RSTR_GPIOCRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */\r\n#define RCC_AHB1RSTR_GPIOCRST              RCC_AHB1RSTR_GPIOCRST_Msk           \r\n#define RCC_AHB1RSTR_GPIODRST_Pos          (3U)                                \r\n#define RCC_AHB1RSTR_GPIODRST_Msk          (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */\r\n#define RCC_AHB1RSTR_GPIODRST              RCC_AHB1RSTR_GPIODRST_Msk           \r\n#define RCC_AHB1RSTR_GPIOERST_Pos          (4U)                                \r\n#define RCC_AHB1RSTR_GPIOERST_Msk          (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */\r\n#define RCC_AHB1RSTR_GPIOERST              RCC_AHB1RSTR_GPIOERST_Msk           \r\n#define RCC_AHB1RSTR_GPIOFRST_Pos          (5U)                                \r\n#define RCC_AHB1RSTR_GPIOFRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */\r\n#define RCC_AHB1RSTR_GPIOFRST              RCC_AHB1RSTR_GPIOFRST_Msk           \r\n#define RCC_AHB1RSTR_GPIOGRST_Pos          (6U)                                \r\n#define RCC_AHB1RSTR_GPIOGRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */\r\n#define RCC_AHB1RSTR_GPIOGRST              RCC_AHB1RSTR_GPIOGRST_Msk           \r\n#define RCC_AHB1RSTR_GPIOHRST_Pos          (7U)                                \r\n#define RCC_AHB1RSTR_GPIOHRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */\r\n#define RCC_AHB1RSTR_GPIOHRST              RCC_AHB1RSTR_GPIOHRST_Msk           \r\n#define RCC_AHB1RSTR_GPIOIRST_Pos          (8U)                                \r\n#define RCC_AHB1RSTR_GPIOIRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */\r\n#define RCC_AHB1RSTR_GPIOIRST              RCC_AHB1RSTR_GPIOIRST_Msk           \r\n#define RCC_AHB1RSTR_GPIOJRST_Pos          (9U)                                \r\n#define RCC_AHB1RSTR_GPIOJRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOJRST_Pos) /*!< 0x00000200 */\r\n#define RCC_AHB1RSTR_GPIOJRST              RCC_AHB1RSTR_GPIOJRST_Msk           \r\n#define RCC_AHB1RSTR_GPIOKRST_Pos          (10U)                               \r\n#define RCC_AHB1RSTR_GPIOKRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOKRST_Pos) /*!< 0x00000400 */\r\n#define RCC_AHB1RSTR_GPIOKRST              RCC_AHB1RSTR_GPIOKRST_Msk           \r\n#define RCC_AHB1RSTR_CRCRST_Pos            (12U)                               \r\n#define RCC_AHB1RSTR_CRCRST_Msk            (0x1U << RCC_AHB1RSTR_CRCRST_Pos)   /*!< 0x00001000 */\r\n#define RCC_AHB1RSTR_CRCRST                RCC_AHB1RSTR_CRCRST_Msk             \r\n#define RCC_AHB1RSTR_DMA1RST_Pos           (21U)                               \r\n#define RCC_AHB1RSTR_DMA1RST_Msk           (0x1U << RCC_AHB1RSTR_DMA1RST_Pos)  /*!< 0x00200000 */\r\n#define RCC_AHB1RSTR_DMA1RST               RCC_AHB1RSTR_DMA1RST_Msk            \r\n#define RCC_AHB1RSTR_DMA2RST_Pos           (22U)                               \r\n#define RCC_AHB1RSTR_DMA2RST_Msk           (0x1U << RCC_AHB1RSTR_DMA2RST_Pos)  /*!< 0x00400000 */\r\n#define RCC_AHB1RSTR_DMA2RST               RCC_AHB1RSTR_DMA2RST_Msk            \r\n#define RCC_AHB1RSTR_DMA2DRST_Pos          (23U)                               \r\n#define RCC_AHB1RSTR_DMA2DRST_Msk          (0x1U << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00800000 */\r\n#define RCC_AHB1RSTR_DMA2DRST              RCC_AHB1RSTR_DMA2DRST_Msk           \r\n#define RCC_AHB1RSTR_ETHMACRST_Pos         (25U)                               \r\n#define RCC_AHB1RSTR_ETHMACRST_Msk         (0x1U << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */\r\n#define RCC_AHB1RSTR_ETHMACRST             RCC_AHB1RSTR_ETHMACRST_Msk          \r\n#define RCC_AHB1RSTR_OTGHRST_Pos           (29U)                               \r\n#define RCC_AHB1RSTR_OTGHRST_Msk           (0x1U << RCC_AHB1RSTR_OTGHRST_Pos)  /*!< 0x20000000 */\r\n#define RCC_AHB1RSTR_OTGHRST               RCC_AHB1RSTR_OTGHRST_Msk            \r\n\r\n/********************  Bit definition for RCC_AHB2RSTR register  **************/\r\n#define RCC_AHB2RSTR_DCMIRST_Pos           (0U)                                \r\n#define RCC_AHB2RSTR_DCMIRST_Msk           (0x1U << RCC_AHB2RSTR_DCMIRST_Pos)  /*!< 0x00000001 */\r\n#define RCC_AHB2RSTR_DCMIRST               RCC_AHB2RSTR_DCMIRST_Msk            \r\n#define RCC_AHB2RSTR_RNGRST_Pos            (6U)                                \r\n#define RCC_AHB2RSTR_RNGRST_Msk            (0x1U << RCC_AHB2RSTR_RNGRST_Pos)   /*!< 0x00000040 */\r\n#define RCC_AHB2RSTR_RNGRST                RCC_AHB2RSTR_RNGRST_Msk             \r\n#define RCC_AHB2RSTR_OTGFSRST_Pos          (7U)                                \r\n#define RCC_AHB2RSTR_OTGFSRST_Msk          (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */\r\n#define RCC_AHB2RSTR_OTGFSRST              RCC_AHB2RSTR_OTGFSRST_Msk           \r\n\r\n/********************  Bit definition for RCC_AHB3RSTR register  **************/\r\n\r\n#define RCC_AHB3RSTR_FMCRST_Pos            (0U)                                \r\n#define RCC_AHB3RSTR_FMCRST_Msk            (0x1U << RCC_AHB3RSTR_FMCRST_Pos)   /*!< 0x00000001 */\r\n#define RCC_AHB3RSTR_FMCRST                RCC_AHB3RSTR_FMCRST_Msk             \r\n#define RCC_AHB3RSTR_QSPIRST_Pos           (1U)                                \r\n#define RCC_AHB3RSTR_QSPIRST_Msk           (0x1U << RCC_AHB3RSTR_QSPIRST_Pos)  /*!< 0x00000002 */\r\n#define RCC_AHB3RSTR_QSPIRST               RCC_AHB3RSTR_QSPIRST_Msk            \r\n\r\n/********************  Bit definition for RCC_APB1RSTR register  **************/\r\n#define RCC_APB1RSTR_TIM2RST_Pos           (0U)                                \r\n#define RCC_APB1RSTR_TIM2RST_Msk           (0x1U << RCC_APB1RSTR_TIM2RST_Pos)  /*!< 0x00000001 */\r\n#define RCC_APB1RSTR_TIM2RST               RCC_APB1RSTR_TIM2RST_Msk            \r\n#define RCC_APB1RSTR_TIM3RST_Pos           (1U)                                \r\n#define RCC_APB1RSTR_TIM3RST_Msk           (0x1U << RCC_APB1RSTR_TIM3RST_Pos)  /*!< 0x00000002 */\r\n#define RCC_APB1RSTR_TIM3RST               RCC_APB1RSTR_TIM3RST_Msk            \r\n#define RCC_APB1RSTR_TIM4RST_Pos           (2U)                                \r\n#define RCC_APB1RSTR_TIM4RST_Msk           (0x1U << RCC_APB1RSTR_TIM4RST_Pos)  /*!< 0x00000004 */\r\n#define RCC_APB1RSTR_TIM4RST               RCC_APB1RSTR_TIM4RST_Msk            \r\n#define RCC_APB1RSTR_TIM5RST_Pos           (3U)                                \r\n#define RCC_APB1RSTR_TIM5RST_Msk           (0x1U << RCC_APB1RSTR_TIM5RST_Pos)  /*!< 0x00000008 */\r\n#define RCC_APB1RSTR_TIM5RST               RCC_APB1RSTR_TIM5RST_Msk            \r\n#define RCC_APB1RSTR_TIM6RST_Pos           (4U)                                \r\n#define RCC_APB1RSTR_TIM6RST_Msk           (0x1U << RCC_APB1RSTR_TIM6RST_Pos)  /*!< 0x00000010 */\r\n#define RCC_APB1RSTR_TIM6RST               RCC_APB1RSTR_TIM6RST_Msk            \r\n#define RCC_APB1RSTR_TIM7RST_Pos           (5U)                                \r\n#define RCC_APB1RSTR_TIM7RST_Msk           (0x1U << RCC_APB1RSTR_TIM7RST_Pos)  /*!< 0x00000020 */\r\n#define RCC_APB1RSTR_TIM7RST               RCC_APB1RSTR_TIM7RST_Msk            \r\n#define RCC_APB1RSTR_TIM12RST_Pos          (6U)                                \r\n#define RCC_APB1RSTR_TIM12RST_Msk          (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */\r\n#define RCC_APB1RSTR_TIM12RST              RCC_APB1RSTR_TIM12RST_Msk           \r\n#define RCC_APB1RSTR_TIM13RST_Pos          (7U)                                \r\n#define RCC_APB1RSTR_TIM13RST_Msk          (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */\r\n#define RCC_APB1RSTR_TIM13RST              RCC_APB1RSTR_TIM13RST_Msk           \r\n#define RCC_APB1RSTR_TIM14RST_Pos          (8U)                                \r\n#define RCC_APB1RSTR_TIM14RST_Msk          (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */\r\n#define RCC_APB1RSTR_TIM14RST              RCC_APB1RSTR_TIM14RST_Msk           \r\n#define RCC_APB1RSTR_LPTIM1RST_Pos         (9U)                                \r\n#define RCC_APB1RSTR_LPTIM1RST_Msk         (0x1U << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x00000200 */\r\n#define RCC_APB1RSTR_LPTIM1RST             RCC_APB1RSTR_LPTIM1RST_Msk          \r\n#define RCC_APB1RSTR_WWDGRST_Pos           (11U)                               \r\n#define RCC_APB1RSTR_WWDGRST_Msk           (0x1U << RCC_APB1RSTR_WWDGRST_Pos)  /*!< 0x00000800 */\r\n#define RCC_APB1RSTR_WWDGRST               RCC_APB1RSTR_WWDGRST_Msk            \r\n#define RCC_APB1RSTR_SPI2RST_Pos           (14U)                               \r\n#define RCC_APB1RSTR_SPI2RST_Msk           (0x1U << RCC_APB1RSTR_SPI2RST_Pos)  /*!< 0x00004000 */\r\n#define RCC_APB1RSTR_SPI2RST               RCC_APB1RSTR_SPI2RST_Msk            \r\n#define RCC_APB1RSTR_SPI3RST_Pos           (15U)                               \r\n#define RCC_APB1RSTR_SPI3RST_Msk           (0x1U << RCC_APB1RSTR_SPI3RST_Pos)  /*!< 0x00008000 */\r\n#define RCC_APB1RSTR_SPI3RST               RCC_APB1RSTR_SPI3RST_Msk            \r\n#define RCC_APB1RSTR_SPDIFRXRST_Pos        (16U)                               \r\n#define RCC_APB1RSTR_SPDIFRXRST_Msk        (0x1U << RCC_APB1RSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */\r\n#define RCC_APB1RSTR_SPDIFRXRST            RCC_APB1RSTR_SPDIFRXRST_Msk         \r\n#define RCC_APB1RSTR_USART2RST_Pos         (17U)                               \r\n#define RCC_APB1RSTR_USART2RST_Msk         (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */\r\n#define RCC_APB1RSTR_USART2RST             RCC_APB1RSTR_USART2RST_Msk          \r\n#define RCC_APB1RSTR_USART3RST_Pos         (18U)                               \r\n#define RCC_APB1RSTR_USART3RST_Msk         (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */\r\n#define RCC_APB1RSTR_USART3RST             RCC_APB1RSTR_USART3RST_Msk          \r\n#define RCC_APB1RSTR_UART4RST_Pos          (19U)                               \r\n#define RCC_APB1RSTR_UART4RST_Msk          (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */\r\n#define RCC_APB1RSTR_UART4RST              RCC_APB1RSTR_UART4RST_Msk           \r\n#define RCC_APB1RSTR_UART5RST_Pos          (20U)                               \r\n#define RCC_APB1RSTR_UART5RST_Msk          (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */\r\n#define RCC_APB1RSTR_UART5RST              RCC_APB1RSTR_UART5RST_Msk           \r\n#define RCC_APB1RSTR_I2C1RST_Pos           (21U)                               \r\n#define RCC_APB1RSTR_I2C1RST_Msk           (0x1U << RCC_APB1RSTR_I2C1RST_Pos)  /*!< 0x00200000 */\r\n#define RCC_APB1RSTR_I2C1RST               RCC_APB1RSTR_I2C1RST_Msk            \r\n#define RCC_APB1RSTR_I2C2RST_Pos           (22U)                               \r\n#define RCC_APB1RSTR_I2C2RST_Msk           (0x1U << RCC_APB1RSTR_I2C2RST_Pos)  /*!< 0x00400000 */\r\n#define RCC_APB1RSTR_I2C2RST               RCC_APB1RSTR_I2C2RST_Msk            \r\n#define RCC_APB1RSTR_I2C3RST_Pos           (23U)                               \r\n#define RCC_APB1RSTR_I2C3RST_Msk           (0x1U << RCC_APB1RSTR_I2C3RST_Pos)  /*!< 0x00800000 */\r\n#define RCC_APB1RSTR_I2C3RST               RCC_APB1RSTR_I2C3RST_Msk            \r\n#define RCC_APB1RSTR_I2C4RST_Pos           (24U)                               \r\n#define RCC_APB1RSTR_I2C4RST_Msk           (0x1U << RCC_APB1RSTR_I2C4RST_Pos)  /*!< 0x01000000 */\r\n#define RCC_APB1RSTR_I2C4RST               RCC_APB1RSTR_I2C4RST_Msk            \r\n#define RCC_APB1RSTR_CAN1RST_Pos           (25U)                               \r\n#define RCC_APB1RSTR_CAN1RST_Msk           (0x1U << RCC_APB1RSTR_CAN1RST_Pos)  /*!< 0x02000000 */\r\n#define RCC_APB1RSTR_CAN1RST               RCC_APB1RSTR_CAN1RST_Msk            \r\n#define RCC_APB1RSTR_CAN2RST_Pos           (26U)                               \r\n#define RCC_APB1RSTR_CAN2RST_Msk           (0x1U << RCC_APB1RSTR_CAN2RST_Pos)  /*!< 0x04000000 */\r\n#define RCC_APB1RSTR_CAN2RST               RCC_APB1RSTR_CAN2RST_Msk            \r\n#define RCC_APB1RSTR_CECRST_Pos            (27U)                               \r\n#define RCC_APB1RSTR_CECRST_Msk            (0x1U << RCC_APB1RSTR_CECRST_Pos)   /*!< 0x08000000 */\r\n#define RCC_APB1RSTR_CECRST                RCC_APB1RSTR_CECRST_Msk             \r\n#define RCC_APB1RSTR_PWRRST_Pos            (28U)                               \r\n#define RCC_APB1RSTR_PWRRST_Msk            (0x1U << RCC_APB1RSTR_PWRRST_Pos)   /*!< 0x10000000 */\r\n#define RCC_APB1RSTR_PWRRST                RCC_APB1RSTR_PWRRST_Msk             \r\n#define RCC_APB1RSTR_DACRST_Pos            (29U)                               \r\n#define RCC_APB1RSTR_DACRST_Msk            (0x1U << RCC_APB1RSTR_DACRST_Pos)   /*!< 0x20000000 */\r\n#define RCC_APB1RSTR_DACRST                RCC_APB1RSTR_DACRST_Msk             \r\n#define RCC_APB1RSTR_UART7RST_Pos          (30U)                               \r\n#define RCC_APB1RSTR_UART7RST_Msk          (0x1U << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */\r\n#define RCC_APB1RSTR_UART7RST              RCC_APB1RSTR_UART7RST_Msk           \r\n#define RCC_APB1RSTR_UART8RST_Pos          (31U)                               \r\n#define RCC_APB1RSTR_UART8RST_Msk          (0x1U << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */\r\n#define RCC_APB1RSTR_UART8RST              RCC_APB1RSTR_UART8RST_Msk           \r\n\r\n/********************  Bit definition for RCC_APB2RSTR register  **************/\r\n#define RCC_APB2RSTR_TIM1RST_Pos           (0U)                                \r\n#define RCC_APB2RSTR_TIM1RST_Msk           (0x1U << RCC_APB2RSTR_TIM1RST_Pos)  /*!< 0x00000001 */\r\n#define RCC_APB2RSTR_TIM1RST               RCC_APB2RSTR_TIM1RST_Msk            \r\n#define RCC_APB2RSTR_TIM8RST_Pos           (1U)                                \r\n#define RCC_APB2RSTR_TIM8RST_Msk           (0x1U << RCC_APB2RSTR_TIM8RST_Pos)  /*!< 0x00000002 */\r\n#define RCC_APB2RSTR_TIM8RST               RCC_APB2RSTR_TIM8RST_Msk            \r\n#define RCC_APB2RSTR_USART1RST_Pos         (4U)                                \r\n#define RCC_APB2RSTR_USART1RST_Msk         (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */\r\n#define RCC_APB2RSTR_USART1RST             RCC_APB2RSTR_USART1RST_Msk          \r\n#define RCC_APB2RSTR_USART6RST_Pos         (5U)                                \r\n#define RCC_APB2RSTR_USART6RST_Msk         (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */\r\n#define RCC_APB2RSTR_USART6RST             RCC_APB2RSTR_USART6RST_Msk          \r\n#define RCC_APB2RSTR_ADCRST_Pos            (8U)                                \r\n#define RCC_APB2RSTR_ADCRST_Msk            (0x1U << RCC_APB2RSTR_ADCRST_Pos)   /*!< 0x00000100 */\r\n#define RCC_APB2RSTR_ADCRST                RCC_APB2RSTR_ADCRST_Msk             \r\n#define RCC_APB2RSTR_SDMMC1RST_Pos         (11U)                               \r\n#define RCC_APB2RSTR_SDMMC1RST_Msk         (0x1U << RCC_APB2RSTR_SDMMC1RST_Pos) /*!< 0x00000800 */\r\n#define RCC_APB2RSTR_SDMMC1RST             RCC_APB2RSTR_SDMMC1RST_Msk          \r\n#define RCC_APB2RSTR_SPI1RST_Pos           (12U)                               \r\n#define RCC_APB2RSTR_SPI1RST_Msk           (0x1U << RCC_APB2RSTR_SPI1RST_Pos)  /*!< 0x00001000 */\r\n#define RCC_APB2RSTR_SPI1RST               RCC_APB2RSTR_SPI1RST_Msk            \r\n#define RCC_APB2RSTR_SPI4RST_Pos           (13U)                               \r\n#define RCC_APB2RSTR_SPI4RST_Msk           (0x1U << RCC_APB2RSTR_SPI4RST_Pos)  /*!< 0x00002000 */\r\n#define RCC_APB2RSTR_SPI4RST               RCC_APB2RSTR_SPI4RST_Msk            \r\n#define RCC_APB2RSTR_SYSCFGRST_Pos         (14U)                               \r\n#define RCC_APB2RSTR_SYSCFGRST_Msk         (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */\r\n#define RCC_APB2RSTR_SYSCFGRST             RCC_APB2RSTR_SYSCFGRST_Msk          \r\n#define RCC_APB2RSTR_TIM9RST_Pos           (16U)                               \r\n#define RCC_APB2RSTR_TIM9RST_Msk           (0x1U << RCC_APB2RSTR_TIM9RST_Pos)  /*!< 0x00010000 */\r\n#define RCC_APB2RSTR_TIM9RST               RCC_APB2RSTR_TIM9RST_Msk            \r\n#define RCC_APB2RSTR_TIM10RST_Pos          (17U)                               \r\n#define RCC_APB2RSTR_TIM10RST_Msk          (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */\r\n#define RCC_APB2RSTR_TIM10RST              RCC_APB2RSTR_TIM10RST_Msk           \r\n#define RCC_APB2RSTR_TIM11RST_Pos          (18U)                               \r\n#define RCC_APB2RSTR_TIM11RST_Msk          (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */\r\n#define RCC_APB2RSTR_TIM11RST              RCC_APB2RSTR_TIM11RST_Msk           \r\n#define RCC_APB2RSTR_SPI5RST_Pos           (20U)                               \r\n#define RCC_APB2RSTR_SPI5RST_Msk           (0x1U << RCC_APB2RSTR_SPI5RST_Pos)  /*!< 0x00100000 */\r\n#define RCC_APB2RSTR_SPI5RST               RCC_APB2RSTR_SPI5RST_Msk            \r\n#define RCC_APB2RSTR_SPI6RST_Pos           (21U)                               \r\n#define RCC_APB2RSTR_SPI6RST_Msk           (0x1U << RCC_APB2RSTR_SPI6RST_Pos)  /*!< 0x00200000 */\r\n#define RCC_APB2RSTR_SPI6RST               RCC_APB2RSTR_SPI6RST_Msk            \r\n#define RCC_APB2RSTR_SAI1RST_Pos           (22U)                               \r\n#define RCC_APB2RSTR_SAI1RST_Msk           (0x1U << RCC_APB2RSTR_SAI1RST_Pos)  /*!< 0x00400000 */\r\n#define RCC_APB2RSTR_SAI1RST               RCC_APB2RSTR_SAI1RST_Msk            \r\n#define RCC_APB2RSTR_SAI2RST_Pos           (23U)                               \r\n#define RCC_APB2RSTR_SAI2RST_Msk           (0x1U << RCC_APB2RSTR_SAI2RST_Pos)  /*!< 0x00800000 */\r\n#define RCC_APB2RSTR_SAI2RST               RCC_APB2RSTR_SAI2RST_Msk            \r\n#define RCC_APB2RSTR_LTDCRST_Pos           (26U)                               \r\n#define RCC_APB2RSTR_LTDCRST_Msk           (0x1U << RCC_APB2RSTR_LTDCRST_Pos)  /*!< 0x04000000 */\r\n#define RCC_APB2RSTR_LTDCRST               RCC_APB2RSTR_LTDCRST_Msk            \r\n\r\n/********************  Bit definition for RCC_AHB1ENR register  ***************/\r\n#define RCC_AHB1ENR_GPIOAEN_Pos            (0U)                                \r\n#define RCC_AHB1ENR_GPIOAEN_Msk            (0x1U << RCC_AHB1ENR_GPIOAEN_Pos)   /*!< 0x00000001 */\r\n#define RCC_AHB1ENR_GPIOAEN                RCC_AHB1ENR_GPIOAEN_Msk             \r\n#define RCC_AHB1ENR_GPIOBEN_Pos            (1U)                                \r\n#define RCC_AHB1ENR_GPIOBEN_Msk            (0x1U << RCC_AHB1ENR_GPIOBEN_Pos)   /*!< 0x00000002 */\r\n#define RCC_AHB1ENR_GPIOBEN                RCC_AHB1ENR_GPIOBEN_Msk             \r\n#define RCC_AHB1ENR_GPIOCEN_Pos            (2U)                                \r\n#define RCC_AHB1ENR_GPIOCEN_Msk            (0x1U << RCC_AHB1ENR_GPIOCEN_Pos)   /*!< 0x00000004 */\r\n#define RCC_AHB1ENR_GPIOCEN                RCC_AHB1ENR_GPIOCEN_Msk             \r\n#define RCC_AHB1ENR_GPIODEN_Pos            (3U)                                \r\n#define RCC_AHB1ENR_GPIODEN_Msk            (0x1U << RCC_AHB1ENR_GPIODEN_Pos)   /*!< 0x00000008 */\r\n#define RCC_AHB1ENR_GPIODEN                RCC_AHB1ENR_GPIODEN_Msk             \r\n#define RCC_AHB1ENR_GPIOEEN_Pos            (4U)                                \r\n#define RCC_AHB1ENR_GPIOEEN_Msk            (0x1U << RCC_AHB1ENR_GPIOEEN_Pos)   /*!< 0x00000010 */\r\n#define RCC_AHB1ENR_GPIOEEN                RCC_AHB1ENR_GPIOEEN_Msk             \r\n#define RCC_AHB1ENR_GPIOFEN_Pos            (5U)                                \r\n#define RCC_AHB1ENR_GPIOFEN_Msk            (0x1U << RCC_AHB1ENR_GPIOFEN_Pos)   /*!< 0x00000020 */\r\n#define RCC_AHB1ENR_GPIOFEN                RCC_AHB1ENR_GPIOFEN_Msk             \r\n#define RCC_AHB1ENR_GPIOGEN_Pos            (6U)                                \r\n#define RCC_AHB1ENR_GPIOGEN_Msk            (0x1U << RCC_AHB1ENR_GPIOGEN_Pos)   /*!< 0x00000040 */\r\n#define RCC_AHB1ENR_GPIOGEN                RCC_AHB1ENR_GPIOGEN_Msk             \r\n#define RCC_AHB1ENR_GPIOHEN_Pos            (7U)                                \r\n#define RCC_AHB1ENR_GPIOHEN_Msk            (0x1U << RCC_AHB1ENR_GPIOHEN_Pos)   /*!< 0x00000080 */\r\n#define RCC_AHB1ENR_GPIOHEN                RCC_AHB1ENR_GPIOHEN_Msk             \r\n#define RCC_AHB1ENR_GPIOIEN_Pos            (8U)                                \r\n#define RCC_AHB1ENR_GPIOIEN_Msk            (0x1U << RCC_AHB1ENR_GPIOIEN_Pos)   /*!< 0x00000100 */\r\n#define RCC_AHB1ENR_GPIOIEN                RCC_AHB1ENR_GPIOIEN_Msk             \r\n#define RCC_AHB1ENR_GPIOJEN_Pos            (9U)                                \r\n#define RCC_AHB1ENR_GPIOJEN_Msk            (0x1U << RCC_AHB1ENR_GPIOJEN_Pos)   /*!< 0x00000200 */\r\n#define RCC_AHB1ENR_GPIOJEN                RCC_AHB1ENR_GPIOJEN_Msk             \r\n#define RCC_AHB1ENR_GPIOKEN_Pos            (10U)                               \r\n#define RCC_AHB1ENR_GPIOKEN_Msk            (0x1U << RCC_AHB1ENR_GPIOKEN_Pos)   /*!< 0x00000400 */\r\n#define RCC_AHB1ENR_GPIOKEN                RCC_AHB1ENR_GPIOKEN_Msk             \r\n#define RCC_AHB1ENR_CRCEN_Pos              (12U)                               \r\n#define RCC_AHB1ENR_CRCEN_Msk              (0x1U << RCC_AHB1ENR_CRCEN_Pos)     /*!< 0x00001000 */\r\n#define RCC_AHB1ENR_CRCEN                  RCC_AHB1ENR_CRCEN_Msk               \r\n#define RCC_AHB1ENR_BKPSRAMEN_Pos          (18U)                               \r\n#define RCC_AHB1ENR_BKPSRAMEN_Msk          (0x1U << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */\r\n#define RCC_AHB1ENR_BKPSRAMEN              RCC_AHB1ENR_BKPSRAMEN_Msk           \r\n#define RCC_AHB1ENR_DTCMRAMEN_Pos          (20U)                               \r\n#define RCC_AHB1ENR_DTCMRAMEN_Msk          (0x1U << RCC_AHB1ENR_DTCMRAMEN_Pos) /*!< 0x00100000 */\r\n#define RCC_AHB1ENR_DTCMRAMEN              RCC_AHB1ENR_DTCMRAMEN_Msk           \r\n#define RCC_AHB1ENR_DMA1EN_Pos             (21U)                               \r\n#define RCC_AHB1ENR_DMA1EN_Msk             (0x1U << RCC_AHB1ENR_DMA1EN_Pos)    /*!< 0x00200000 */\r\n#define RCC_AHB1ENR_DMA1EN                 RCC_AHB1ENR_DMA1EN_Msk              \r\n#define RCC_AHB1ENR_DMA2EN_Pos             (22U)                               \r\n#define RCC_AHB1ENR_DMA2EN_Msk             (0x1U << RCC_AHB1ENR_DMA2EN_Pos)    /*!< 0x00400000 */\r\n#define RCC_AHB1ENR_DMA2EN                 RCC_AHB1ENR_DMA2EN_Msk              \r\n#define RCC_AHB1ENR_DMA2DEN_Pos            (23U)                               \r\n#define RCC_AHB1ENR_DMA2DEN_Msk            (0x1U << RCC_AHB1ENR_DMA2DEN_Pos)   /*!< 0x00800000 */\r\n#define RCC_AHB1ENR_DMA2DEN                RCC_AHB1ENR_DMA2DEN_Msk             \r\n#define RCC_AHB1ENR_ETHMACEN_Pos           (25U)                               \r\n#define RCC_AHB1ENR_ETHMACEN_Msk           (0x1U << RCC_AHB1ENR_ETHMACEN_Pos)  /*!< 0x02000000 */\r\n#define RCC_AHB1ENR_ETHMACEN               RCC_AHB1ENR_ETHMACEN_Msk            \r\n#define RCC_AHB1ENR_ETHMACTXEN_Pos         (26U)                               \r\n#define RCC_AHB1ENR_ETHMACTXEN_Msk         (0x1U << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */\r\n#define RCC_AHB1ENR_ETHMACTXEN             RCC_AHB1ENR_ETHMACTXEN_Msk          \r\n#define RCC_AHB1ENR_ETHMACRXEN_Pos         (27U)                               \r\n#define RCC_AHB1ENR_ETHMACRXEN_Msk         (0x1U << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */\r\n#define RCC_AHB1ENR_ETHMACRXEN             RCC_AHB1ENR_ETHMACRXEN_Msk          \r\n#define RCC_AHB1ENR_ETHMACPTPEN_Pos        (28U)                               \r\n#define RCC_AHB1ENR_ETHMACPTPEN_Msk        (0x1U << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */\r\n#define RCC_AHB1ENR_ETHMACPTPEN            RCC_AHB1ENR_ETHMACPTPEN_Msk         \r\n#define RCC_AHB1ENR_OTGHSEN_Pos            (29U)                               \r\n#define RCC_AHB1ENR_OTGHSEN_Msk            (0x1U << RCC_AHB1ENR_OTGHSEN_Pos)   /*!< 0x20000000 */\r\n#define RCC_AHB1ENR_OTGHSEN                RCC_AHB1ENR_OTGHSEN_Msk             \r\n#define RCC_AHB1ENR_OTGHSULPIEN_Pos        (30U)                               \r\n#define RCC_AHB1ENR_OTGHSULPIEN_Msk        (0x1U << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */\r\n#define RCC_AHB1ENR_OTGHSULPIEN            RCC_AHB1ENR_OTGHSULPIEN_Msk         \r\n\r\n/********************  Bit definition for RCC_AHB2ENR register  ***************/\r\n#define RCC_AHB2ENR_DCMIEN_Pos             (0U)                                \r\n#define RCC_AHB2ENR_DCMIEN_Msk             (0x1U << RCC_AHB2ENR_DCMIEN_Pos)    /*!< 0x00000001 */\r\n#define RCC_AHB2ENR_DCMIEN                 RCC_AHB2ENR_DCMIEN_Msk              \r\n#define RCC_AHB2ENR_RNGEN_Pos              (6U)                                \r\n#define RCC_AHB2ENR_RNGEN_Msk              (0x1U << RCC_AHB2ENR_RNGEN_Pos)     /*!< 0x00000040 */\r\n#define RCC_AHB2ENR_RNGEN                  RCC_AHB2ENR_RNGEN_Msk               \r\n#define RCC_AHB2ENR_OTGFSEN_Pos            (7U)                                \r\n#define RCC_AHB2ENR_OTGFSEN_Msk            (0x1U << RCC_AHB2ENR_OTGFSEN_Pos)   /*!< 0x00000080 */\r\n#define RCC_AHB2ENR_OTGFSEN                RCC_AHB2ENR_OTGFSEN_Msk             \r\n\r\n/********************  Bit definition for RCC_AHB3ENR register  ***************/\r\n#define RCC_AHB3ENR_FMCEN_Pos              (0U)                                \r\n#define RCC_AHB3ENR_FMCEN_Msk              (0x1U << RCC_AHB3ENR_FMCEN_Pos)     /*!< 0x00000001 */\r\n#define RCC_AHB3ENR_FMCEN                  RCC_AHB3ENR_FMCEN_Msk               \r\n#define RCC_AHB3ENR_QSPIEN_Pos             (1U)                                \r\n#define RCC_AHB3ENR_QSPIEN_Msk             (0x1U << RCC_AHB3ENR_QSPIEN_Pos)    /*!< 0x00000002 */\r\n#define RCC_AHB3ENR_QSPIEN                 RCC_AHB3ENR_QSPIEN_Msk              \r\n\r\n/********************  Bit definition for RCC_APB1ENR register  ***************/\r\n#define RCC_APB1ENR_TIM2EN_Pos             (0U)                                \r\n#define RCC_APB1ENR_TIM2EN_Msk             (0x1U << RCC_APB1ENR_TIM2EN_Pos)    /*!< 0x00000001 */\r\n#define RCC_APB1ENR_TIM2EN                 RCC_APB1ENR_TIM2EN_Msk              \r\n#define RCC_APB1ENR_TIM3EN_Pos             (1U)                                \r\n#define RCC_APB1ENR_TIM3EN_Msk             (0x1U << RCC_APB1ENR_TIM3EN_Pos)    /*!< 0x00000002 */\r\n#define RCC_APB1ENR_TIM3EN                 RCC_APB1ENR_TIM3EN_Msk              \r\n#define RCC_APB1ENR_TIM4EN_Pos             (2U)                                \r\n#define RCC_APB1ENR_TIM4EN_Msk             (0x1U << RCC_APB1ENR_TIM4EN_Pos)    /*!< 0x00000004 */\r\n#define RCC_APB1ENR_TIM4EN                 RCC_APB1ENR_TIM4EN_Msk              \r\n#define RCC_APB1ENR_TIM5EN_Pos             (3U)                                \r\n#define RCC_APB1ENR_TIM5EN_Msk             (0x1U << RCC_APB1ENR_TIM5EN_Pos)    /*!< 0x00000008 */\r\n#define RCC_APB1ENR_TIM5EN                 RCC_APB1ENR_TIM5EN_Msk              \r\n#define RCC_APB1ENR_TIM6EN_Pos             (4U)                                \r\n#define RCC_APB1ENR_TIM6EN_Msk             (0x1U << RCC_APB1ENR_TIM6EN_Pos)    /*!< 0x00000010 */\r\n#define RCC_APB1ENR_TIM6EN                 RCC_APB1ENR_TIM6EN_Msk              \r\n#define RCC_APB1ENR_TIM7EN_Pos             (5U)                                \r\n#define RCC_APB1ENR_TIM7EN_Msk             (0x1U << RCC_APB1ENR_TIM7EN_Pos)    /*!< 0x00000020 */\r\n#define RCC_APB1ENR_TIM7EN                 RCC_APB1ENR_TIM7EN_Msk              \r\n#define RCC_APB1ENR_TIM12EN_Pos            (6U)                                \r\n#define RCC_APB1ENR_TIM12EN_Msk            (0x1U << RCC_APB1ENR_TIM12EN_Pos)   /*!< 0x00000040 */\r\n#define RCC_APB1ENR_TIM12EN                RCC_APB1ENR_TIM12EN_Msk             \r\n#define RCC_APB1ENR_TIM13EN_Pos            (7U)                                \r\n#define RCC_APB1ENR_TIM13EN_Msk            (0x1U << RCC_APB1ENR_TIM13EN_Pos)   /*!< 0x00000080 */\r\n#define RCC_APB1ENR_TIM13EN                RCC_APB1ENR_TIM13EN_Msk             \r\n#define RCC_APB1ENR_TIM14EN_Pos            (8U)                                \r\n#define RCC_APB1ENR_TIM14EN_Msk            (0x1U << RCC_APB1ENR_TIM14EN_Pos)   /*!< 0x00000100 */\r\n#define RCC_APB1ENR_TIM14EN                RCC_APB1ENR_TIM14EN_Msk             \r\n#define RCC_APB1ENR_LPTIM1EN_Pos           (9U)                                \r\n#define RCC_APB1ENR_LPTIM1EN_Msk           (0x1U << RCC_APB1ENR_LPTIM1EN_Pos)  /*!< 0x00000200 */\r\n#define RCC_APB1ENR_LPTIM1EN               RCC_APB1ENR_LPTIM1EN_Msk            \r\n#define RCC_APB1ENR_WWDGEN_Pos             (11U)                               \r\n#define RCC_APB1ENR_WWDGEN_Msk             (0x1U << RCC_APB1ENR_WWDGEN_Pos)    /*!< 0x00000800 */\r\n#define RCC_APB1ENR_WWDGEN                 RCC_APB1ENR_WWDGEN_Msk              \r\n#define RCC_APB1ENR_SPI2EN_Pos             (14U)                               \r\n#define RCC_APB1ENR_SPI2EN_Msk             (0x1U << RCC_APB1ENR_SPI2EN_Pos)    /*!< 0x00004000 */\r\n#define RCC_APB1ENR_SPI2EN                 RCC_APB1ENR_SPI2EN_Msk              \r\n#define RCC_APB1ENR_SPI3EN_Pos             (15U)                               \r\n#define RCC_APB1ENR_SPI3EN_Msk             (0x1U << RCC_APB1ENR_SPI3EN_Pos)    /*!< 0x00008000 */\r\n#define RCC_APB1ENR_SPI3EN                 RCC_APB1ENR_SPI3EN_Msk              \r\n#define RCC_APB1ENR_SPDIFRXEN_Pos          (16U)                               \r\n#define RCC_APB1ENR_SPDIFRXEN_Msk          (0x1U << RCC_APB1ENR_SPDIFRXEN_Pos) /*!< 0x00010000 */\r\n#define RCC_APB1ENR_SPDIFRXEN              RCC_APB1ENR_SPDIFRXEN_Msk           \r\n#define RCC_APB1ENR_USART2EN_Pos           (17U)                               \r\n#define RCC_APB1ENR_USART2EN_Msk           (0x1U << RCC_APB1ENR_USART2EN_Pos)  /*!< 0x00020000 */\r\n#define RCC_APB1ENR_USART2EN               RCC_APB1ENR_USART2EN_Msk            \r\n#define RCC_APB1ENR_USART3EN_Pos           (18U)                               \r\n#define RCC_APB1ENR_USART3EN_Msk           (0x1U << RCC_APB1ENR_USART3EN_Pos)  /*!< 0x00040000 */\r\n#define RCC_APB1ENR_USART3EN               RCC_APB1ENR_USART3EN_Msk            \r\n#define RCC_APB1ENR_UART4EN_Pos            (19U)                               \r\n#define RCC_APB1ENR_UART4EN_Msk            (0x1U << RCC_APB1ENR_UART4EN_Pos)   /*!< 0x00080000 */\r\n#define RCC_APB1ENR_UART4EN                RCC_APB1ENR_UART4EN_Msk             \r\n#define RCC_APB1ENR_UART5EN_Pos            (20U)                               \r\n#define RCC_APB1ENR_UART5EN_Msk            (0x1U << RCC_APB1ENR_UART5EN_Pos)   /*!< 0x00100000 */\r\n#define RCC_APB1ENR_UART5EN                RCC_APB1ENR_UART5EN_Msk             \r\n#define RCC_APB1ENR_I2C1EN_Pos             (21U)                               \r\n#define RCC_APB1ENR_I2C1EN_Msk             (0x1U << RCC_APB1ENR_I2C1EN_Pos)    /*!< 0x00200000 */\r\n#define RCC_APB1ENR_I2C1EN                 RCC_APB1ENR_I2C1EN_Msk              \r\n#define RCC_APB1ENR_I2C2EN_Pos             (22U)                               \r\n#define RCC_APB1ENR_I2C2EN_Msk             (0x1U << RCC_APB1ENR_I2C2EN_Pos)    /*!< 0x00400000 */\r\n#define RCC_APB1ENR_I2C2EN                 RCC_APB1ENR_I2C2EN_Msk              \r\n#define RCC_APB1ENR_I2C3EN_Pos             (23U)                               \r\n#define RCC_APB1ENR_I2C3EN_Msk             (0x1U << RCC_APB1ENR_I2C3EN_Pos)    /*!< 0x00800000 */\r\n#define RCC_APB1ENR_I2C3EN                 RCC_APB1ENR_I2C3EN_Msk              \r\n#define RCC_APB1ENR_I2C4EN_Pos             (24U)                               \r\n#define RCC_APB1ENR_I2C4EN_Msk             (0x1U << RCC_APB1ENR_I2C4EN_Pos)    /*!< 0x01000000 */\r\n#define RCC_APB1ENR_I2C4EN                 RCC_APB1ENR_I2C4EN_Msk              \r\n#define RCC_APB1ENR_CAN1EN_Pos             (25U)                               \r\n#define RCC_APB1ENR_CAN1EN_Msk             (0x1U << RCC_APB1ENR_CAN1EN_Pos)    /*!< 0x02000000 */\r\n#define RCC_APB1ENR_CAN1EN                 RCC_APB1ENR_CAN1EN_Msk              \r\n#define RCC_APB1ENR_CAN2EN_Pos             (26U)                               \r\n#define RCC_APB1ENR_CAN2EN_Msk             (0x1U << RCC_APB1ENR_CAN2EN_Pos)    /*!< 0x04000000 */\r\n#define RCC_APB1ENR_CAN2EN                 RCC_APB1ENR_CAN2EN_Msk              \r\n#define RCC_APB1ENR_CECEN_Pos              (27U)                               \r\n#define RCC_APB1ENR_CECEN_Msk              (0x1U << RCC_APB1ENR_CECEN_Pos)     /*!< 0x08000000 */\r\n#define RCC_APB1ENR_CECEN                  RCC_APB1ENR_CECEN_Msk               \r\n#define RCC_APB1ENR_PWREN_Pos              (28U)                               \r\n#define RCC_APB1ENR_PWREN_Msk              (0x1U << RCC_APB1ENR_PWREN_Pos)     /*!< 0x10000000 */\r\n#define RCC_APB1ENR_PWREN                  RCC_APB1ENR_PWREN_Msk               \r\n#define RCC_APB1ENR_DACEN_Pos              (29U)                               \r\n#define RCC_APB1ENR_DACEN_Msk              (0x1U << RCC_APB1ENR_DACEN_Pos)     /*!< 0x20000000 */\r\n#define RCC_APB1ENR_DACEN                  RCC_APB1ENR_DACEN_Msk               \r\n#define RCC_APB1ENR_UART7EN_Pos            (30U)                               \r\n#define RCC_APB1ENR_UART7EN_Msk            (0x1U << RCC_APB1ENR_UART7EN_Pos)   /*!< 0x40000000 */\r\n#define RCC_APB1ENR_UART7EN                RCC_APB1ENR_UART7EN_Msk             \r\n#define RCC_APB1ENR_UART8EN_Pos            (31U)                               \r\n#define RCC_APB1ENR_UART8EN_Msk            (0x1U << RCC_APB1ENR_UART8EN_Pos)   /*!< 0x80000000 */\r\n#define RCC_APB1ENR_UART8EN                RCC_APB1ENR_UART8EN_Msk             \r\n\r\n/********************  Bit definition for RCC_APB2ENR register  ***************/\r\n#define RCC_APB2ENR_TIM1EN_Pos             (0U)                                \r\n#define RCC_APB2ENR_TIM1EN_Msk             (0x1U << RCC_APB2ENR_TIM1EN_Pos)    /*!< 0x00000001 */\r\n#define RCC_APB2ENR_TIM1EN                 RCC_APB2ENR_TIM1EN_Msk              \r\n#define RCC_APB2ENR_TIM8EN_Pos             (1U)                                \r\n#define RCC_APB2ENR_TIM8EN_Msk             (0x1U << RCC_APB2ENR_TIM8EN_Pos)    /*!< 0x00000002 */\r\n#define RCC_APB2ENR_TIM8EN                 RCC_APB2ENR_TIM8EN_Msk              \r\n#define RCC_APB2ENR_USART1EN_Pos           (4U)                                \r\n#define RCC_APB2ENR_USART1EN_Msk           (0x1U << RCC_APB2ENR_USART1EN_Pos)  /*!< 0x00000010 */\r\n#define RCC_APB2ENR_USART1EN               RCC_APB2ENR_USART1EN_Msk            \r\n#define RCC_APB2ENR_USART6EN_Pos           (5U)                                \r\n#define RCC_APB2ENR_USART6EN_Msk           (0x1U << RCC_APB2ENR_USART6EN_Pos)  /*!< 0x00000020 */\r\n#define RCC_APB2ENR_USART6EN               RCC_APB2ENR_USART6EN_Msk            \r\n#define RCC_APB2ENR_ADC1EN_Pos             (8U)                                \r\n#define RCC_APB2ENR_ADC1EN_Msk             (0x1U << RCC_APB2ENR_ADC1EN_Pos)    /*!< 0x00000100 */\r\n#define RCC_APB2ENR_ADC1EN                 RCC_APB2ENR_ADC1EN_Msk              \r\n#define RCC_APB2ENR_ADC2EN_Pos             (9U)                                \r\n#define RCC_APB2ENR_ADC2EN_Msk             (0x1U << RCC_APB2ENR_ADC2EN_Pos)    /*!< 0x00000200 */\r\n#define RCC_APB2ENR_ADC2EN                 RCC_APB2ENR_ADC2EN_Msk              \r\n#define RCC_APB2ENR_ADC3EN_Pos             (10U)                               \r\n#define RCC_APB2ENR_ADC3EN_Msk             (0x1U << RCC_APB2ENR_ADC3EN_Pos)    /*!< 0x00000400 */\r\n#define RCC_APB2ENR_ADC3EN                 RCC_APB2ENR_ADC3EN_Msk              \r\n#define RCC_APB2ENR_SDMMC1EN_Pos           (11U)                               \r\n#define RCC_APB2ENR_SDMMC1EN_Msk           (0x1U << RCC_APB2ENR_SDMMC1EN_Pos)  /*!< 0x00000800 */\r\n#define RCC_APB2ENR_SDMMC1EN               RCC_APB2ENR_SDMMC1EN_Msk            \r\n#define RCC_APB2ENR_SPI1EN_Pos             (12U)                               \r\n#define RCC_APB2ENR_SPI1EN_Msk             (0x1U << RCC_APB2ENR_SPI1EN_Pos)    /*!< 0x00001000 */\r\n#define RCC_APB2ENR_SPI1EN                 RCC_APB2ENR_SPI1EN_Msk              \r\n#define RCC_APB2ENR_SPI4EN_Pos             (13U)                               \r\n#define RCC_APB2ENR_SPI4EN_Msk             (0x1U << RCC_APB2ENR_SPI4EN_Pos)    /*!< 0x00002000 */\r\n#define RCC_APB2ENR_SPI4EN                 RCC_APB2ENR_SPI4EN_Msk              \r\n#define RCC_APB2ENR_SYSCFGEN_Pos           (14U)                               \r\n#define RCC_APB2ENR_SYSCFGEN_Msk           (0x1U << RCC_APB2ENR_SYSCFGEN_Pos)  /*!< 0x00004000 */\r\n#define RCC_APB2ENR_SYSCFGEN               RCC_APB2ENR_SYSCFGEN_Msk            \r\n#define RCC_APB2ENR_TIM9EN_Pos             (16U)                               \r\n#define RCC_APB2ENR_TIM9EN_Msk             (0x1U << RCC_APB2ENR_TIM9EN_Pos)    /*!< 0x00010000 */\r\n#define RCC_APB2ENR_TIM9EN                 RCC_APB2ENR_TIM9EN_Msk              \r\n#define RCC_APB2ENR_TIM10EN_Pos            (17U)                               \r\n#define RCC_APB2ENR_TIM10EN_Msk            (0x1U << RCC_APB2ENR_TIM10EN_Pos)   /*!< 0x00020000 */\r\n#define RCC_APB2ENR_TIM10EN                RCC_APB2ENR_TIM10EN_Msk             \r\n#define RCC_APB2ENR_TIM11EN_Pos            (18U)                               \r\n#define RCC_APB2ENR_TIM11EN_Msk            (0x1U << RCC_APB2ENR_TIM11EN_Pos)   /*!< 0x00040000 */\r\n#define RCC_APB2ENR_TIM11EN                RCC_APB2ENR_TIM11EN_Msk             \r\n#define RCC_APB2ENR_SPI5EN_Pos             (20U)                               \r\n#define RCC_APB2ENR_SPI5EN_Msk             (0x1U << RCC_APB2ENR_SPI5EN_Pos)    /*!< 0x00100000 */\r\n#define RCC_APB2ENR_SPI5EN                 RCC_APB2ENR_SPI5EN_Msk              \r\n#define RCC_APB2ENR_SPI6EN_Pos             (21U)                               \r\n#define RCC_APB2ENR_SPI6EN_Msk             (0x1U << RCC_APB2ENR_SPI6EN_Pos)    /*!< 0x00200000 */\r\n#define RCC_APB2ENR_SPI6EN                 RCC_APB2ENR_SPI6EN_Msk              \r\n#define RCC_APB2ENR_SAI1EN_Pos             (22U)                               \r\n#define RCC_APB2ENR_SAI1EN_Msk             (0x1U << RCC_APB2ENR_SAI1EN_Pos)    /*!< 0x00400000 */\r\n#define RCC_APB2ENR_SAI1EN                 RCC_APB2ENR_SAI1EN_Msk              \r\n#define RCC_APB2ENR_SAI2EN_Pos             (23U)                               \r\n#define RCC_APB2ENR_SAI2EN_Msk             (0x1U << RCC_APB2ENR_SAI2EN_Pos)    /*!< 0x00800000 */\r\n#define RCC_APB2ENR_SAI2EN                 RCC_APB2ENR_SAI2EN_Msk              \r\n#define RCC_APB2ENR_LTDCEN_Pos             (26U)                               \r\n#define RCC_APB2ENR_LTDCEN_Msk             (0x1U << RCC_APB2ENR_LTDCEN_Pos)    /*!< 0x04000000 */\r\n#define RCC_APB2ENR_LTDCEN                 RCC_APB2ENR_LTDCEN_Msk              \r\n\r\n/********************  Bit definition for RCC_AHB1LPENR register  *************/\r\n#define RCC_AHB1LPENR_GPIOALPEN_Pos        (0U)                                \r\n#define RCC_AHB1LPENR_GPIOALPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */\r\n#define RCC_AHB1LPENR_GPIOALPEN            RCC_AHB1LPENR_GPIOALPEN_Msk         \r\n#define RCC_AHB1LPENR_GPIOBLPEN_Pos        (1U)                                \r\n#define RCC_AHB1LPENR_GPIOBLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */\r\n#define RCC_AHB1LPENR_GPIOBLPEN            RCC_AHB1LPENR_GPIOBLPEN_Msk         \r\n#define RCC_AHB1LPENR_GPIOCLPEN_Pos        (2U)                                \r\n#define RCC_AHB1LPENR_GPIOCLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */\r\n#define RCC_AHB1LPENR_GPIOCLPEN            RCC_AHB1LPENR_GPIOCLPEN_Msk         \r\n#define RCC_AHB1LPENR_GPIODLPEN_Pos        (3U)                                \r\n#define RCC_AHB1LPENR_GPIODLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */\r\n#define RCC_AHB1LPENR_GPIODLPEN            RCC_AHB1LPENR_GPIODLPEN_Msk         \r\n#define RCC_AHB1LPENR_GPIOELPEN_Pos        (4U)                                \r\n#define RCC_AHB1LPENR_GPIOELPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */\r\n#define RCC_AHB1LPENR_GPIOELPEN            RCC_AHB1LPENR_GPIOELPEN_Msk         \r\n#define RCC_AHB1LPENR_GPIOFLPEN_Pos        (5U)                                \r\n#define RCC_AHB1LPENR_GPIOFLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */\r\n#define RCC_AHB1LPENR_GPIOFLPEN            RCC_AHB1LPENR_GPIOFLPEN_Msk         \r\n#define RCC_AHB1LPENR_GPIOGLPEN_Pos        (6U)                                \r\n#define RCC_AHB1LPENR_GPIOGLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */\r\n#define RCC_AHB1LPENR_GPIOGLPEN            RCC_AHB1LPENR_GPIOGLPEN_Msk         \r\n#define RCC_AHB1LPENR_GPIOHLPEN_Pos        (7U)                                \r\n#define RCC_AHB1LPENR_GPIOHLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */\r\n#define RCC_AHB1LPENR_GPIOHLPEN            RCC_AHB1LPENR_GPIOHLPEN_Msk         \r\n#define RCC_AHB1LPENR_GPIOILPEN_Pos        (8U)                                \r\n#define RCC_AHB1LPENR_GPIOILPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */\r\n#define RCC_AHB1LPENR_GPIOILPEN            RCC_AHB1LPENR_GPIOILPEN_Msk         \r\n#define RCC_AHB1LPENR_GPIOJLPEN_Pos        (9U)                                \r\n#define RCC_AHB1LPENR_GPIOJLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */\r\n#define RCC_AHB1LPENR_GPIOJLPEN            RCC_AHB1LPENR_GPIOJLPEN_Msk         \r\n#define RCC_AHB1LPENR_GPIOKLPEN_Pos        (10U)                               \r\n#define RCC_AHB1LPENR_GPIOKLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */\r\n#define RCC_AHB1LPENR_GPIOKLPEN            RCC_AHB1LPENR_GPIOKLPEN_Msk         \r\n#define RCC_AHB1LPENR_CRCLPEN_Pos          (12U)                               \r\n#define RCC_AHB1LPENR_CRCLPEN_Msk          (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */\r\n#define RCC_AHB1LPENR_CRCLPEN              RCC_AHB1LPENR_CRCLPEN_Msk           \r\n#define RCC_AHB1LPENR_AXILPEN_Pos          (13U)                               \r\n#define RCC_AHB1LPENR_AXILPEN_Msk          (0x1U << RCC_AHB1LPENR_AXILPEN_Pos) /*!< 0x00002000 */\r\n#define RCC_AHB1LPENR_AXILPEN              RCC_AHB1LPENR_AXILPEN_Msk           \r\n#define RCC_AHB1LPENR_FLITFLPEN_Pos        (15U)                               \r\n#define RCC_AHB1LPENR_FLITFLPEN_Msk        (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */\r\n#define RCC_AHB1LPENR_FLITFLPEN            RCC_AHB1LPENR_FLITFLPEN_Msk         \r\n#define RCC_AHB1LPENR_SRAM1LPEN_Pos        (16U)                               \r\n#define RCC_AHB1LPENR_SRAM1LPEN_Msk        (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */\r\n#define RCC_AHB1LPENR_SRAM1LPEN            RCC_AHB1LPENR_SRAM1LPEN_Msk         \r\n#define RCC_AHB1LPENR_SRAM2LPEN_Pos        (17U)                               \r\n#define RCC_AHB1LPENR_SRAM2LPEN_Msk        (0x1U << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */\r\n#define RCC_AHB1LPENR_SRAM2LPEN            RCC_AHB1LPENR_SRAM2LPEN_Msk         \r\n#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos      (18U)                               \r\n#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk      (0x1U << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */\r\n#define RCC_AHB1LPENR_BKPSRAMLPEN          RCC_AHB1LPENR_BKPSRAMLPEN_Msk       \r\n#define RCC_AHB1LPENR_DTCMLPEN_Pos         (20U)                               \r\n#define RCC_AHB1LPENR_DTCMLPEN_Msk         (0x1U << RCC_AHB1LPENR_DTCMLPEN_Pos) /*!< 0x00100000 */\r\n#define RCC_AHB1LPENR_DTCMLPEN             RCC_AHB1LPENR_DTCMLPEN_Msk          \r\n#define RCC_AHB1LPENR_DMA1LPEN_Pos         (21U)                               \r\n#define RCC_AHB1LPENR_DMA1LPEN_Msk         (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */\r\n#define RCC_AHB1LPENR_DMA1LPEN             RCC_AHB1LPENR_DMA1LPEN_Msk          \r\n#define RCC_AHB1LPENR_DMA2LPEN_Pos         (22U)                               \r\n#define RCC_AHB1LPENR_DMA2LPEN_Msk         (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */\r\n#define RCC_AHB1LPENR_DMA2LPEN             RCC_AHB1LPENR_DMA2LPEN_Msk          \r\n#define RCC_AHB1LPENR_DMA2DLPEN_Pos        (23U)                               \r\n#define RCC_AHB1LPENR_DMA2DLPEN_Msk        (0x1U << RCC_AHB1LPENR_DMA2DLPEN_Pos) /*!< 0x00800000 */\r\n#define RCC_AHB1LPENR_DMA2DLPEN            RCC_AHB1LPENR_DMA2DLPEN_Msk         \r\n#define RCC_AHB1LPENR_ETHMACLPEN_Pos       (25U)                               \r\n#define RCC_AHB1LPENR_ETHMACLPEN_Msk       (0x1U << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */\r\n#define RCC_AHB1LPENR_ETHMACLPEN           RCC_AHB1LPENR_ETHMACLPEN_Msk        \r\n#define RCC_AHB1LPENR_ETHMACTXLPEN_Pos     (26U)                               \r\n#define RCC_AHB1LPENR_ETHMACTXLPEN_Msk     (0x1U << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */\r\n#define RCC_AHB1LPENR_ETHMACTXLPEN         RCC_AHB1LPENR_ETHMACTXLPEN_Msk      \r\n#define RCC_AHB1LPENR_ETHMACRXLPEN_Pos     (27U)                               \r\n#define RCC_AHB1LPENR_ETHMACRXLPEN_Msk     (0x1U << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */\r\n#define RCC_AHB1LPENR_ETHMACRXLPEN         RCC_AHB1LPENR_ETHMACRXLPEN_Msk      \r\n#define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos    (28U)                               \r\n#define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk    (0x1U << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */\r\n#define RCC_AHB1LPENR_ETHMACPTPLPEN        RCC_AHB1LPENR_ETHMACPTPLPEN_Msk     \r\n#define RCC_AHB1LPENR_OTGHSLPEN_Pos        (29U)                               \r\n#define RCC_AHB1LPENR_OTGHSLPEN_Msk        (0x1U << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */\r\n#define RCC_AHB1LPENR_OTGHSLPEN            RCC_AHB1LPENR_OTGHSLPEN_Msk         \r\n#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos    (30U)                               \r\n#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk    (0x1U << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */\r\n#define RCC_AHB1LPENR_OTGHSULPILPEN        RCC_AHB1LPENR_OTGHSULPILPEN_Msk     \r\n\r\n/********************  Bit definition for RCC_AHB2LPENR register  *************/\r\n#define RCC_AHB2LPENR_DCMILPEN_Pos         (0U)                                \r\n#define RCC_AHB2LPENR_DCMILPEN_Msk         (0x1U << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */\r\n#define RCC_AHB2LPENR_DCMILPEN             RCC_AHB2LPENR_DCMILPEN_Msk          \r\n#define RCC_AHB2LPENR_RNGLPEN_Pos          (6U)                                \r\n#define RCC_AHB2LPENR_RNGLPEN_Msk          (0x1U << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */\r\n#define RCC_AHB2LPENR_RNGLPEN              RCC_AHB2LPENR_RNGLPEN_Msk           \r\n#define RCC_AHB2LPENR_OTGFSLPEN_Pos        (7U)                                \r\n#define RCC_AHB2LPENR_OTGFSLPEN_Msk        (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */\r\n#define RCC_AHB2LPENR_OTGFSLPEN            RCC_AHB2LPENR_OTGFSLPEN_Msk         \r\n\r\n/********************  Bit definition for RCC_AHB3LPENR register  *************/\r\n#define RCC_AHB3LPENR_FMCLPEN_Pos          (0U)                                \r\n#define RCC_AHB3LPENR_FMCLPEN_Msk          (0x1U << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */\r\n#define RCC_AHB3LPENR_FMCLPEN              RCC_AHB3LPENR_FMCLPEN_Msk           \r\n#define RCC_AHB3LPENR_QSPILPEN_Pos         (1U)                                \r\n#define RCC_AHB3LPENR_QSPILPEN_Msk         (0x1U << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00000002 */\r\n#define RCC_AHB3LPENR_QSPILPEN             RCC_AHB3LPENR_QSPILPEN_Msk          \r\n/********************  Bit definition for RCC_APB1LPENR register  *************/\r\n#define RCC_APB1LPENR_TIM2LPEN_Pos         (0U)                                \r\n#define RCC_APB1LPENR_TIM2LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */\r\n#define RCC_APB1LPENR_TIM2LPEN             RCC_APB1LPENR_TIM2LPEN_Msk          \r\n#define RCC_APB1LPENR_TIM3LPEN_Pos         (1U)                                \r\n#define RCC_APB1LPENR_TIM3LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */\r\n#define RCC_APB1LPENR_TIM3LPEN             RCC_APB1LPENR_TIM3LPEN_Msk          \r\n#define RCC_APB1LPENR_TIM4LPEN_Pos         (2U)                                \r\n#define RCC_APB1LPENR_TIM4LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */\r\n#define RCC_APB1LPENR_TIM4LPEN             RCC_APB1LPENR_TIM4LPEN_Msk          \r\n#define RCC_APB1LPENR_TIM5LPEN_Pos         (3U)                                \r\n#define RCC_APB1LPENR_TIM5LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */\r\n#define RCC_APB1LPENR_TIM5LPEN             RCC_APB1LPENR_TIM5LPEN_Msk          \r\n#define RCC_APB1LPENR_TIM6LPEN_Pos         (4U)                                \r\n#define RCC_APB1LPENR_TIM6LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */\r\n#define RCC_APB1LPENR_TIM6LPEN             RCC_APB1LPENR_TIM6LPEN_Msk          \r\n#define RCC_APB1LPENR_TIM7LPEN_Pos         (5U)                                \r\n#define RCC_APB1LPENR_TIM7LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */\r\n#define RCC_APB1LPENR_TIM7LPEN             RCC_APB1LPENR_TIM7LPEN_Msk          \r\n#define RCC_APB1LPENR_TIM12LPEN_Pos        (6U)                                \r\n#define RCC_APB1LPENR_TIM12LPEN_Msk        (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */\r\n#define RCC_APB1LPENR_TIM12LPEN            RCC_APB1LPENR_TIM12LPEN_Msk         \r\n#define RCC_APB1LPENR_TIM13LPEN_Pos        (7U)                                \r\n#define RCC_APB1LPENR_TIM13LPEN_Msk        (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */\r\n#define RCC_APB1LPENR_TIM13LPEN            RCC_APB1LPENR_TIM13LPEN_Msk         \r\n#define RCC_APB1LPENR_TIM14LPEN_Pos        (8U)                                \r\n#define RCC_APB1LPENR_TIM14LPEN_Msk        (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */\r\n#define RCC_APB1LPENR_TIM14LPEN            RCC_APB1LPENR_TIM14LPEN_Msk         \r\n#define RCC_APB1LPENR_LPTIM1LPEN_Pos       (9U)                                \r\n#define RCC_APB1LPENR_LPTIM1LPEN_Msk       (0x1U << RCC_APB1LPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */\r\n#define RCC_APB1LPENR_LPTIM1LPEN           RCC_APB1LPENR_LPTIM1LPEN_Msk        \r\n#define RCC_APB1LPENR_WWDGLPEN_Pos         (11U)                               \r\n#define RCC_APB1LPENR_WWDGLPEN_Msk         (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */\r\n#define RCC_APB1LPENR_WWDGLPEN             RCC_APB1LPENR_WWDGLPEN_Msk          \r\n#define RCC_APB1LPENR_SPI2LPEN_Pos         (14U)                               \r\n#define RCC_APB1LPENR_SPI2LPEN_Msk         (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */\r\n#define RCC_APB1LPENR_SPI2LPEN             RCC_APB1LPENR_SPI2LPEN_Msk          \r\n#define RCC_APB1LPENR_SPI3LPEN_Pos         (15U)                               \r\n#define RCC_APB1LPENR_SPI3LPEN_Msk         (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */\r\n#define RCC_APB1LPENR_SPI3LPEN             RCC_APB1LPENR_SPI3LPEN_Msk          \r\n#define RCC_APB1LPENR_SPDIFRXLPEN_Pos      (16U)                               \r\n#define RCC_APB1LPENR_SPDIFRXLPEN_Msk      (0x1U << RCC_APB1LPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */\r\n#define RCC_APB1LPENR_SPDIFRXLPEN          RCC_APB1LPENR_SPDIFRXLPEN_Msk       \r\n#define RCC_APB1LPENR_USART2LPEN_Pos       (17U)                               \r\n#define RCC_APB1LPENR_USART2LPEN_Msk       (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */\r\n#define RCC_APB1LPENR_USART2LPEN           RCC_APB1LPENR_USART2LPEN_Msk        \r\n#define RCC_APB1LPENR_USART3LPEN_Pos       (18U)                               \r\n#define RCC_APB1LPENR_USART3LPEN_Msk       (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */\r\n#define RCC_APB1LPENR_USART3LPEN           RCC_APB1LPENR_USART3LPEN_Msk        \r\n#define RCC_APB1LPENR_UART4LPEN_Pos        (19U)                               \r\n#define RCC_APB1LPENR_UART4LPEN_Msk        (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */\r\n#define RCC_APB1LPENR_UART4LPEN            RCC_APB1LPENR_UART4LPEN_Msk         \r\n#define RCC_APB1LPENR_UART5LPEN_Pos        (20U)                               \r\n#define RCC_APB1LPENR_UART5LPEN_Msk        (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */\r\n#define RCC_APB1LPENR_UART5LPEN            RCC_APB1LPENR_UART5LPEN_Msk         \r\n#define RCC_APB1LPENR_I2C1LPEN_Pos         (21U)                               \r\n#define RCC_APB1LPENR_I2C1LPEN_Msk         (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */\r\n#define RCC_APB1LPENR_I2C1LPEN             RCC_APB1LPENR_I2C1LPEN_Msk          \r\n#define RCC_APB1LPENR_I2C2LPEN_Pos         (22U)                               \r\n#define RCC_APB1LPENR_I2C2LPEN_Msk         (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */\r\n#define RCC_APB1LPENR_I2C2LPEN             RCC_APB1LPENR_I2C2LPEN_Msk          \r\n#define RCC_APB1LPENR_I2C3LPEN_Pos         (23U)                               \r\n#define RCC_APB1LPENR_I2C3LPEN_Msk         (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */\r\n#define RCC_APB1LPENR_I2C3LPEN             RCC_APB1LPENR_I2C3LPEN_Msk          \r\n#define RCC_APB1LPENR_I2C4LPEN_Pos         (24U)                               \r\n#define RCC_APB1LPENR_I2C4LPEN_Msk         (0x1U << RCC_APB1LPENR_I2C4LPEN_Pos) /*!< 0x01000000 */\r\n#define RCC_APB1LPENR_I2C4LPEN             RCC_APB1LPENR_I2C4LPEN_Msk          \r\n#define RCC_APB1LPENR_CAN1LPEN_Pos         (25U)                               \r\n#define RCC_APB1LPENR_CAN1LPEN_Msk         (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */\r\n#define RCC_APB1LPENR_CAN1LPEN             RCC_APB1LPENR_CAN1LPEN_Msk          \r\n#define RCC_APB1LPENR_CAN2LPEN_Pos         (26U)                               \r\n#define RCC_APB1LPENR_CAN2LPEN_Msk         (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */\r\n#define RCC_APB1LPENR_CAN2LPEN             RCC_APB1LPENR_CAN2LPEN_Msk          \r\n#define RCC_APB1LPENR_CECLPEN_Pos          (27U)                               \r\n#define RCC_APB1LPENR_CECLPEN_Msk          (0x1U << RCC_APB1LPENR_CECLPEN_Pos) /*!< 0x08000000 */\r\n#define RCC_APB1LPENR_CECLPEN              RCC_APB1LPENR_CECLPEN_Msk           \r\n#define RCC_APB1LPENR_PWRLPEN_Pos          (28U)                               \r\n#define RCC_APB1LPENR_PWRLPEN_Msk          (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */\r\n#define RCC_APB1LPENR_PWRLPEN              RCC_APB1LPENR_PWRLPEN_Msk           \r\n#define RCC_APB1LPENR_DACLPEN_Pos          (29U)                               \r\n#define RCC_APB1LPENR_DACLPEN_Msk          (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */\r\n#define RCC_APB1LPENR_DACLPEN              RCC_APB1LPENR_DACLPEN_Msk           \r\n#define RCC_APB1LPENR_UART7LPEN_Pos        (30U)                               \r\n#define RCC_APB1LPENR_UART7LPEN_Msk        (0x1U << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */\r\n#define RCC_APB1LPENR_UART7LPEN            RCC_APB1LPENR_UART7LPEN_Msk         \r\n#define RCC_APB1LPENR_UART8LPEN_Pos        (31U)                               \r\n#define RCC_APB1LPENR_UART8LPEN_Msk        (0x1U << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */\r\n#define RCC_APB1LPENR_UART8LPEN            RCC_APB1LPENR_UART8LPEN_Msk         \r\n\r\n/********************  Bit definition for RCC_APB2LPENR register  *************/\r\n#define RCC_APB2LPENR_TIM1LPEN_Pos         (0U)                                \r\n#define RCC_APB2LPENR_TIM1LPEN_Msk         (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */\r\n#define RCC_APB2LPENR_TIM1LPEN             RCC_APB2LPENR_TIM1LPEN_Msk          \r\n#define RCC_APB2LPENR_TIM8LPEN_Pos         (1U)                                \r\n#define RCC_APB2LPENR_TIM8LPEN_Msk         (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */\r\n#define RCC_APB2LPENR_TIM8LPEN             RCC_APB2LPENR_TIM8LPEN_Msk          \r\n#define RCC_APB2LPENR_USART1LPEN_Pos       (4U)                                \r\n#define RCC_APB2LPENR_USART1LPEN_Msk       (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */\r\n#define RCC_APB2LPENR_USART1LPEN           RCC_APB2LPENR_USART1LPEN_Msk        \r\n#define RCC_APB2LPENR_USART6LPEN_Pos       (5U)                                \r\n#define RCC_APB2LPENR_USART6LPEN_Msk       (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */\r\n#define RCC_APB2LPENR_USART6LPEN           RCC_APB2LPENR_USART6LPEN_Msk        \r\n#define RCC_APB2LPENR_ADC1LPEN_Pos         (8U)                                \r\n#define RCC_APB2LPENR_ADC1LPEN_Msk         (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */\r\n#define RCC_APB2LPENR_ADC1LPEN             RCC_APB2LPENR_ADC1LPEN_Msk          \r\n#define RCC_APB2LPENR_ADC2LPEN_Pos         (9U)                                \r\n#define RCC_APB2LPENR_ADC2LPEN_Msk         (0x1U << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */\r\n#define RCC_APB2LPENR_ADC2LPEN             RCC_APB2LPENR_ADC2LPEN_Msk          \r\n#define RCC_APB2LPENR_ADC3LPEN_Pos         (10U)                               \r\n#define RCC_APB2LPENR_ADC3LPEN_Msk         (0x1U << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */\r\n#define RCC_APB2LPENR_ADC3LPEN             RCC_APB2LPENR_ADC3LPEN_Msk          \r\n#define RCC_APB2LPENR_SDMMC1LPEN_Pos       (11U)                               \r\n#define RCC_APB2LPENR_SDMMC1LPEN_Msk       (0x1U << RCC_APB2LPENR_SDMMC1LPEN_Pos) /*!< 0x00000800 */\r\n#define RCC_APB2LPENR_SDMMC1LPEN           RCC_APB2LPENR_SDMMC1LPEN_Msk        \r\n#define RCC_APB2LPENR_SPI1LPEN_Pos         (12U)                               \r\n#define RCC_APB2LPENR_SPI1LPEN_Msk         (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */\r\n#define RCC_APB2LPENR_SPI1LPEN             RCC_APB2LPENR_SPI1LPEN_Msk          \r\n#define RCC_APB2LPENR_SPI4LPEN_Pos         (13U)                               \r\n#define RCC_APB2LPENR_SPI4LPEN_Msk         (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */\r\n#define RCC_APB2LPENR_SPI4LPEN             RCC_APB2LPENR_SPI4LPEN_Msk          \r\n#define RCC_APB2LPENR_SYSCFGLPEN_Pos       (14U)                               \r\n#define RCC_APB2LPENR_SYSCFGLPEN_Msk       (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */\r\n#define RCC_APB2LPENR_SYSCFGLPEN           RCC_APB2LPENR_SYSCFGLPEN_Msk        \r\n#define RCC_APB2LPENR_TIM9LPEN_Pos         (16U)                               \r\n#define RCC_APB2LPENR_TIM9LPEN_Msk         (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */\r\n#define RCC_APB2LPENR_TIM9LPEN             RCC_APB2LPENR_TIM9LPEN_Msk          \r\n#define RCC_APB2LPENR_TIM10LPEN_Pos        (17U)                               \r\n#define RCC_APB2LPENR_TIM10LPEN_Msk        (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */\r\n#define RCC_APB2LPENR_TIM10LPEN            RCC_APB2LPENR_TIM10LPEN_Msk         \r\n#define RCC_APB2LPENR_TIM11LPEN_Pos        (18U)                               \r\n#define RCC_APB2LPENR_TIM11LPEN_Msk        (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */\r\n#define RCC_APB2LPENR_TIM11LPEN            RCC_APB2LPENR_TIM11LPEN_Msk         \r\n#define RCC_APB2LPENR_SPI5LPEN_Pos         (20U)                               \r\n#define RCC_APB2LPENR_SPI5LPEN_Msk         (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */\r\n#define RCC_APB2LPENR_SPI5LPEN             RCC_APB2LPENR_SPI5LPEN_Msk          \r\n#define RCC_APB2LPENR_SPI6LPEN_Pos         (21U)                               \r\n#define RCC_APB2LPENR_SPI6LPEN_Msk         (0x1U << RCC_APB2LPENR_SPI6LPEN_Pos) /*!< 0x00200000 */\r\n#define RCC_APB2LPENR_SPI6LPEN             RCC_APB2LPENR_SPI6LPEN_Msk          \r\n#define RCC_APB2LPENR_SAI1LPEN_Pos         (22U)                               \r\n#define RCC_APB2LPENR_SAI1LPEN_Msk         (0x1U << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */\r\n#define RCC_APB2LPENR_SAI1LPEN             RCC_APB2LPENR_SAI1LPEN_Msk          \r\n#define RCC_APB2LPENR_SAI2LPEN_Pos         (23U)                               \r\n#define RCC_APB2LPENR_SAI2LPEN_Msk         (0x1U << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */\r\n#define RCC_APB2LPENR_SAI2LPEN             RCC_APB2LPENR_SAI2LPEN_Msk          \r\n#define RCC_APB2LPENR_LTDCLPEN_Pos         (26U)                               \r\n#define RCC_APB2LPENR_LTDCLPEN_Msk         (0x1U << RCC_APB2LPENR_LTDCLPEN_Pos) /*!< 0x04000000 */\r\n#define RCC_APB2LPENR_LTDCLPEN             RCC_APB2LPENR_LTDCLPEN_Msk          \r\n\r\n/********************  Bit definition for RCC_BDCR register  ******************/\r\n#define RCC_BDCR_LSEON_Pos                 (0U)                                \r\n#define RCC_BDCR_LSEON_Msk                 (0x1U << RCC_BDCR_LSEON_Pos)        /*!< 0x00000001 */\r\n#define RCC_BDCR_LSEON                     RCC_BDCR_LSEON_Msk                  \r\n#define RCC_BDCR_LSERDY_Pos                (1U)                                \r\n#define RCC_BDCR_LSERDY_Msk                (0x1U << RCC_BDCR_LSERDY_Pos)       /*!< 0x00000002 */\r\n#define RCC_BDCR_LSERDY                    RCC_BDCR_LSERDY_Msk                 \r\n#define RCC_BDCR_LSEBYP_Pos                (2U)                                \r\n#define RCC_BDCR_LSEBYP_Msk                (0x1U << RCC_BDCR_LSEBYP_Pos)       /*!< 0x00000004 */\r\n#define RCC_BDCR_LSEBYP                    RCC_BDCR_LSEBYP_Msk                 \r\n#define RCC_BDCR_LSEDRV_Pos                (3U)                                \r\n#define RCC_BDCR_LSEDRV_Msk                (0x3U << RCC_BDCR_LSEDRV_Pos)       /*!< 0x00000018 */\r\n#define RCC_BDCR_LSEDRV                    RCC_BDCR_LSEDRV_Msk                 \r\n#define RCC_BDCR_LSEDRV_0                  (0x1U << RCC_BDCR_LSEDRV_Pos)       /*!< 0x00000008 */\r\n#define RCC_BDCR_LSEDRV_1                  (0x2U << RCC_BDCR_LSEDRV_Pos)       /*!< 0x00000010 */\r\n#define RCC_BDCR_RTCSEL_Pos                (8U)                                \r\n#define RCC_BDCR_RTCSEL_Msk                (0x3U << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000300 */\r\n#define RCC_BDCR_RTCSEL                    RCC_BDCR_RTCSEL_Msk                 \r\n#define RCC_BDCR_RTCSEL_0                  (0x1U << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000100 */\r\n#define RCC_BDCR_RTCSEL_1                  (0x2U << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000200 */\r\n#define RCC_BDCR_RTCEN_Pos                 (15U)                               \r\n#define RCC_BDCR_RTCEN_Msk                 (0x1U << RCC_BDCR_RTCEN_Pos)        /*!< 0x00008000 */\r\n#define RCC_BDCR_RTCEN                     RCC_BDCR_RTCEN_Msk                  \r\n#define RCC_BDCR_BDRST_Pos                 (16U)                               \r\n#define RCC_BDCR_BDRST_Msk                 (0x1U << RCC_BDCR_BDRST_Pos)        /*!< 0x00010000 */\r\n#define RCC_BDCR_BDRST                     RCC_BDCR_BDRST_Msk                  \r\n\r\n/********************  Bit definition for RCC_CSR register  *******************/\r\n#define RCC_CSR_LSION_Pos                  (0U)                                \r\n#define RCC_CSR_LSION_Msk                  (0x1U << RCC_CSR_LSION_Pos)         /*!< 0x00000001 */\r\n#define RCC_CSR_LSION                      RCC_CSR_LSION_Msk                   \r\n#define RCC_CSR_LSIRDY_Pos                 (1U)                                \r\n#define RCC_CSR_LSIRDY_Msk                 (0x1U << RCC_CSR_LSIRDY_Pos)        /*!< 0x00000002 */\r\n#define RCC_CSR_LSIRDY                     RCC_CSR_LSIRDY_Msk                  \r\n#define RCC_CSR_RMVF_Pos                   (24U)                               \r\n#define RCC_CSR_RMVF_Msk                   (0x1U << RCC_CSR_RMVF_Pos)          /*!< 0x01000000 */\r\n#define RCC_CSR_RMVF                       RCC_CSR_RMVF_Msk                    \r\n#define RCC_CSR_BORRSTF_Pos                (25U)                               \r\n#define RCC_CSR_BORRSTF_Msk                (0x1U << RCC_CSR_BORRSTF_Pos)       /*!< 0x02000000 */\r\n#define RCC_CSR_BORRSTF                    RCC_CSR_BORRSTF_Msk                 \r\n#define RCC_CSR_PINRSTF_Pos                (26U)                               \r\n#define RCC_CSR_PINRSTF_Msk                (0x1U << RCC_CSR_PINRSTF_Pos)       /*!< 0x04000000 */\r\n#define RCC_CSR_PINRSTF                    RCC_CSR_PINRSTF_Msk                 \r\n#define RCC_CSR_PORRSTF_Pos                (27U)                               \r\n#define RCC_CSR_PORRSTF_Msk                (0x1U << RCC_CSR_PORRSTF_Pos)       /*!< 0x08000000 */\r\n#define RCC_CSR_PORRSTF                    RCC_CSR_PORRSTF_Msk                 \r\n#define RCC_CSR_SFTRSTF_Pos                (28U)                               \r\n#define RCC_CSR_SFTRSTF_Msk                (0x1U << RCC_CSR_SFTRSTF_Pos)       /*!< 0x10000000 */\r\n#define RCC_CSR_SFTRSTF                    RCC_CSR_SFTRSTF_Msk                 \r\n#define RCC_CSR_IWDGRSTF_Pos               (29U)                               \r\n#define RCC_CSR_IWDGRSTF_Msk               (0x1U << RCC_CSR_IWDGRSTF_Pos)      /*!< 0x20000000 */\r\n#define RCC_CSR_IWDGRSTF                   RCC_CSR_IWDGRSTF_Msk                \r\n#define RCC_CSR_WWDGRSTF_Pos               (30U)                               \r\n#define RCC_CSR_WWDGRSTF_Msk               (0x1U << RCC_CSR_WWDGRSTF_Pos)      /*!< 0x40000000 */\r\n#define RCC_CSR_WWDGRSTF                   RCC_CSR_WWDGRSTF_Msk                \r\n#define RCC_CSR_LPWRRSTF_Pos               (31U)                               \r\n#define RCC_CSR_LPWRRSTF_Msk               (0x1U << RCC_CSR_LPWRRSTF_Pos)      /*!< 0x80000000 */\r\n#define RCC_CSR_LPWRRSTF                   RCC_CSR_LPWRRSTF_Msk                \r\n\r\n/********************  Bit definition for RCC_SSCGR register  *****************/\r\n#define RCC_SSCGR_MODPER_Pos               (0U)                                \r\n#define RCC_SSCGR_MODPER_Msk               (0x1FFFU << RCC_SSCGR_MODPER_Pos)   /*!< 0x00001FFF */\r\n#define RCC_SSCGR_MODPER                   RCC_SSCGR_MODPER_Msk                \r\n#define RCC_SSCGR_INCSTEP_Pos              (13U)                               \r\n#define RCC_SSCGR_INCSTEP_Msk              (0x7FFFU << RCC_SSCGR_INCSTEP_Pos)  /*!< 0x0FFFE000 */\r\n#define RCC_SSCGR_INCSTEP                  RCC_SSCGR_INCSTEP_Msk               \r\n#define RCC_SSCGR_SPREADSEL_Pos            (30U)                               \r\n#define RCC_SSCGR_SPREADSEL_Msk            (0x1U << RCC_SSCGR_SPREADSEL_Pos)   /*!< 0x40000000 */\r\n#define RCC_SSCGR_SPREADSEL                RCC_SSCGR_SPREADSEL_Msk             \r\n#define RCC_SSCGR_SSCGEN_Pos               (31U)                               \r\n#define RCC_SSCGR_SSCGEN_Msk               (0x1U << RCC_SSCGR_SSCGEN_Pos)      /*!< 0x80000000 */\r\n#define RCC_SSCGR_SSCGEN                   RCC_SSCGR_SSCGEN_Msk                \r\n\r\n/********************  Bit definition for RCC_PLLI2SCFGR register  ************/\r\n#define RCC_PLLI2SCFGR_PLLI2SN_Pos         (6U)                                \r\n#define RCC_PLLI2SCFGR_PLLI2SN_Msk         (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */\r\n#define RCC_PLLI2SCFGR_PLLI2SN             RCC_PLLI2SCFGR_PLLI2SN_Msk          \r\n#define RCC_PLLI2SCFGR_PLLI2SN_0           (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */\r\n#define RCC_PLLI2SCFGR_PLLI2SN_1           (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */\r\n#define RCC_PLLI2SCFGR_PLLI2SN_2           (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */\r\n#define RCC_PLLI2SCFGR_PLLI2SN_3           (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */\r\n#define RCC_PLLI2SCFGR_PLLI2SN_4           (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */\r\n#define RCC_PLLI2SCFGR_PLLI2SN_5           (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */\r\n#define RCC_PLLI2SCFGR_PLLI2SN_6           (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */\r\n#define RCC_PLLI2SCFGR_PLLI2SN_7           (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */\r\n#define RCC_PLLI2SCFGR_PLLI2SN_8           (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */\r\n#define RCC_PLLI2SCFGR_PLLI2SP_Pos         (16U)                               \r\n#define RCC_PLLI2SCFGR_PLLI2SP_Msk         (0x3U << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00030000 */\r\n#define RCC_PLLI2SCFGR_PLLI2SP             RCC_PLLI2SCFGR_PLLI2SP_Msk          \r\n#define RCC_PLLI2SCFGR_PLLI2SP_0           (0x1U << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00010000 */\r\n#define RCC_PLLI2SCFGR_PLLI2SP_1           (0x2U << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00020000 */\r\n#define RCC_PLLI2SCFGR_PLLI2SQ_Pos         (24U)                               \r\n#define RCC_PLLI2SCFGR_PLLI2SQ_Msk         (0xFU << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */\r\n#define RCC_PLLI2SCFGR_PLLI2SQ             RCC_PLLI2SCFGR_PLLI2SQ_Msk          \r\n#define RCC_PLLI2SCFGR_PLLI2SQ_0           (0x1U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */\r\n#define RCC_PLLI2SCFGR_PLLI2SQ_1           (0x2U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */\r\n#define RCC_PLLI2SCFGR_PLLI2SQ_2           (0x4U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */\r\n#define RCC_PLLI2SCFGR_PLLI2SQ_3           (0x8U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */\r\n#define RCC_PLLI2SCFGR_PLLI2SR_Pos         (28U)                               \r\n#define RCC_PLLI2SCFGR_PLLI2SR_Msk         (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */\r\n#define RCC_PLLI2SCFGR_PLLI2SR             RCC_PLLI2SCFGR_PLLI2SR_Msk          \r\n#define RCC_PLLI2SCFGR_PLLI2SR_0           (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */\r\n#define RCC_PLLI2SCFGR_PLLI2SR_1           (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */\r\n#define RCC_PLLI2SCFGR_PLLI2SR_2           (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */\r\n\r\n/********************  Bit definition for RCC_PLLSAICFGR register  ************/\r\n#define RCC_PLLSAICFGR_PLLSAIN_Pos         (6U)                                \r\n#define RCC_PLLSAICFGR_PLLSAIN_Msk         (0x1FFU << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */\r\n#define RCC_PLLSAICFGR_PLLSAIN             RCC_PLLSAICFGR_PLLSAIN_Msk          \r\n#define RCC_PLLSAICFGR_PLLSAIN_0           (0x001U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */\r\n#define RCC_PLLSAICFGR_PLLSAIN_1           (0x002U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */\r\n#define RCC_PLLSAICFGR_PLLSAIN_2           (0x004U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */\r\n#define RCC_PLLSAICFGR_PLLSAIN_3           (0x008U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */\r\n#define RCC_PLLSAICFGR_PLLSAIN_4           (0x010U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */\r\n#define RCC_PLLSAICFGR_PLLSAIN_5           (0x020U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */\r\n#define RCC_PLLSAICFGR_PLLSAIN_6           (0x040U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */\r\n#define RCC_PLLSAICFGR_PLLSAIN_7           (0x080U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */\r\n#define RCC_PLLSAICFGR_PLLSAIN_8           (0x100U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */\r\n#define RCC_PLLSAICFGR_PLLSAIP_Pos         (16U)                               \r\n#define RCC_PLLSAICFGR_PLLSAIP_Msk         (0x3U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00030000 */\r\n#define RCC_PLLSAICFGR_PLLSAIP             RCC_PLLSAICFGR_PLLSAIP_Msk          \r\n#define RCC_PLLSAICFGR_PLLSAIP_0           (0x1U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00010000 */\r\n#define RCC_PLLSAICFGR_PLLSAIP_1           (0x2U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00020000 */\r\n#define RCC_PLLSAICFGR_PLLSAIQ_Pos         (24U)                               \r\n#define RCC_PLLSAICFGR_PLLSAIQ_Msk         (0xFU << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */\r\n#define RCC_PLLSAICFGR_PLLSAIQ             RCC_PLLSAICFGR_PLLSAIQ_Msk          \r\n#define RCC_PLLSAICFGR_PLLSAIQ_0           (0x1U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */\r\n#define RCC_PLLSAICFGR_PLLSAIQ_1           (0x2U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */\r\n#define RCC_PLLSAICFGR_PLLSAIQ_2           (0x4U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */\r\n#define RCC_PLLSAICFGR_PLLSAIQ_3           (0x8U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */\r\n#define RCC_PLLSAICFGR_PLLSAIR_Pos         (28U)                               \r\n#define RCC_PLLSAICFGR_PLLSAIR_Msk         (0x7U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x70000000 */\r\n#define RCC_PLLSAICFGR_PLLSAIR             RCC_PLLSAICFGR_PLLSAIR_Msk          \r\n#define RCC_PLLSAICFGR_PLLSAIR_0           (0x1U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x10000000 */\r\n#define RCC_PLLSAICFGR_PLLSAIR_1           (0x2U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x20000000 */\r\n#define RCC_PLLSAICFGR_PLLSAIR_2           (0x4U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x40000000 */\r\n\r\n/********************  Bit definition for RCC_DCKCFGR1 register  ***************/\r\n#define RCC_DCKCFGR1_PLLI2SDIVQ_Pos        (0U)                                \r\n#define RCC_DCKCFGR1_PLLI2SDIVQ_Msk        (0x1FU << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x0000001F */\r\n#define RCC_DCKCFGR1_PLLI2SDIVQ            RCC_DCKCFGR1_PLLI2SDIVQ_Msk         \r\n#define RCC_DCKCFGR1_PLLI2SDIVQ_0          (0x01U << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000001 */\r\n#define RCC_DCKCFGR1_PLLI2SDIVQ_1          (0x02U << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000002 */\r\n#define RCC_DCKCFGR1_PLLI2SDIVQ_2          (0x04U << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000004 */\r\n#define RCC_DCKCFGR1_PLLI2SDIVQ_3          (0x08U << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000008 */\r\n#define RCC_DCKCFGR1_PLLI2SDIVQ_4          (0x10U << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000010 */\r\n\r\n#define RCC_DCKCFGR1_PLLSAIDIVQ_Pos        (8U)                                \r\n#define RCC_DCKCFGR1_PLLSAIDIVQ_Msk        (0x1FU << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */\r\n#define RCC_DCKCFGR1_PLLSAIDIVQ            RCC_DCKCFGR1_PLLSAIDIVQ_Msk         \r\n#define RCC_DCKCFGR1_PLLSAIDIVQ_0          (0x01U << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000100 */\r\n#define RCC_DCKCFGR1_PLLSAIDIVQ_1          (0x02U << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000200 */\r\n#define RCC_DCKCFGR1_PLLSAIDIVQ_2          (0x04U << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000400 */\r\n#define RCC_DCKCFGR1_PLLSAIDIVQ_3          (0x08U << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000800 */\r\n#define RCC_DCKCFGR1_PLLSAIDIVQ_4          (0x10U << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00001000 */\r\n\r\n#define RCC_DCKCFGR1_PLLSAIDIVR_Pos        (16U)                               \r\n#define RCC_DCKCFGR1_PLLSAIDIVR_Msk        (0x3U << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00030000 */\r\n#define RCC_DCKCFGR1_PLLSAIDIVR            RCC_DCKCFGR1_PLLSAIDIVR_Msk         \r\n#define RCC_DCKCFGR1_PLLSAIDIVR_0          (0x1U << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00010000 */\r\n#define RCC_DCKCFGR1_PLLSAIDIVR_1          (0x2U << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00020000 */\r\n\r\n#define RCC_DCKCFGR1_SAI1SEL_Pos           (20U)                               \r\n#define RCC_DCKCFGR1_SAI1SEL_Msk           (0x3U << RCC_DCKCFGR1_SAI1SEL_Pos)  /*!< 0x00300000 */\r\n#define RCC_DCKCFGR1_SAI1SEL               RCC_DCKCFGR1_SAI1SEL_Msk            \r\n#define RCC_DCKCFGR1_SAI1SEL_0             (0x1U << RCC_DCKCFGR1_SAI1SEL_Pos)  /*!< 0x00100000 */\r\n#define RCC_DCKCFGR1_SAI1SEL_1             (0x2U << RCC_DCKCFGR1_SAI1SEL_Pos)  /*!< 0x00200000 */\r\n\r\n#define RCC_DCKCFGR1_SAI2SEL_Pos           (22U)                               \r\n#define RCC_DCKCFGR1_SAI2SEL_Msk           (0x3U << RCC_DCKCFGR1_SAI2SEL_Pos)  /*!< 0x00C00000 */\r\n#define RCC_DCKCFGR1_SAI2SEL               RCC_DCKCFGR1_SAI2SEL_Msk            \r\n#define RCC_DCKCFGR1_SAI2SEL_0             (0x1U << RCC_DCKCFGR1_SAI2SEL_Pos)  /*!< 0x00400000 */\r\n#define RCC_DCKCFGR1_SAI2SEL_1             (0x2U << RCC_DCKCFGR1_SAI2SEL_Pos)  /*!< 0x00800000 */\r\n\r\n#define RCC_DCKCFGR1_TIMPRE_Pos            (24U)                               \r\n#define RCC_DCKCFGR1_TIMPRE_Msk            (0x1U << RCC_DCKCFGR1_TIMPRE_Pos)   /*!< 0x01000000 */\r\n#define RCC_DCKCFGR1_TIMPRE                RCC_DCKCFGR1_TIMPRE_Msk             \r\n\r\n/********************  Bit definition for RCC_DCKCFGR2 register  ***************/\r\n#define RCC_DCKCFGR2_USART1SEL_Pos         (0U)                                \r\n#define RCC_DCKCFGR2_USART1SEL_Msk         (0x3U << RCC_DCKCFGR2_USART1SEL_Pos) /*!< 0x00000003 */\r\n#define RCC_DCKCFGR2_USART1SEL             RCC_DCKCFGR2_USART1SEL_Msk          \r\n#define RCC_DCKCFGR2_USART1SEL_0           (0x1U << RCC_DCKCFGR2_USART1SEL_Pos) /*!< 0x00000001 */\r\n#define RCC_DCKCFGR2_USART1SEL_1           (0x2U << RCC_DCKCFGR2_USART1SEL_Pos) /*!< 0x00000002 */\r\n#define RCC_DCKCFGR2_USART2SEL_Pos         (2U)                                \r\n#define RCC_DCKCFGR2_USART2SEL_Msk         (0x3U << RCC_DCKCFGR2_USART2SEL_Pos) /*!< 0x0000000C */\r\n#define RCC_DCKCFGR2_USART2SEL             RCC_DCKCFGR2_USART2SEL_Msk          \r\n#define RCC_DCKCFGR2_USART2SEL_0           (0x1U << RCC_DCKCFGR2_USART2SEL_Pos) /*!< 0x00000004 */\r\n#define RCC_DCKCFGR2_USART2SEL_1           (0x2U << RCC_DCKCFGR2_USART2SEL_Pos) /*!< 0x00000008 */\r\n#define RCC_DCKCFGR2_USART3SEL_Pos         (4U)                                \r\n#define RCC_DCKCFGR2_USART3SEL_Msk         (0x3U << RCC_DCKCFGR2_USART3SEL_Pos) /*!< 0x00000030 */\r\n#define RCC_DCKCFGR2_USART3SEL             RCC_DCKCFGR2_USART3SEL_Msk          \r\n#define RCC_DCKCFGR2_USART3SEL_0           (0x1U << RCC_DCKCFGR2_USART3SEL_Pos) /*!< 0x00000010 */\r\n#define RCC_DCKCFGR2_USART3SEL_1           (0x2U << RCC_DCKCFGR2_USART3SEL_Pos) /*!< 0x00000020 */\r\n#define RCC_DCKCFGR2_UART4SEL_Pos          (6U)                                \r\n#define RCC_DCKCFGR2_UART4SEL_Msk          (0x3U << RCC_DCKCFGR2_UART4SEL_Pos) /*!< 0x000000C0 */\r\n#define RCC_DCKCFGR2_UART4SEL              RCC_DCKCFGR2_UART4SEL_Msk           \r\n#define RCC_DCKCFGR2_UART4SEL_0            (0x1U << RCC_DCKCFGR2_UART4SEL_Pos) /*!< 0x00000040 */\r\n#define RCC_DCKCFGR2_UART4SEL_1            (0x2U << RCC_DCKCFGR2_UART4SEL_Pos) /*!< 0x00000080 */\r\n#define RCC_DCKCFGR2_UART5SEL_Pos          (8U)                                \r\n#define RCC_DCKCFGR2_UART5SEL_Msk          (0x3U << RCC_DCKCFGR2_UART5SEL_Pos) /*!< 0x00000300 */\r\n#define RCC_DCKCFGR2_UART5SEL              RCC_DCKCFGR2_UART5SEL_Msk           \r\n#define RCC_DCKCFGR2_UART5SEL_0            (0x1U << RCC_DCKCFGR2_UART5SEL_Pos) /*!< 0x00000100 */\r\n#define RCC_DCKCFGR2_UART5SEL_1            (0x2U << RCC_DCKCFGR2_UART5SEL_Pos) /*!< 0x00000200 */\r\n#define RCC_DCKCFGR2_USART6SEL_Pos         (10U)                               \r\n#define RCC_DCKCFGR2_USART6SEL_Msk         (0x3U << RCC_DCKCFGR2_USART6SEL_Pos) /*!< 0x00000C00 */\r\n#define RCC_DCKCFGR2_USART6SEL             RCC_DCKCFGR2_USART6SEL_Msk          \r\n#define RCC_DCKCFGR2_USART6SEL_0           (0x1U << RCC_DCKCFGR2_USART6SEL_Pos) /*!< 0x00000400 */\r\n#define RCC_DCKCFGR2_USART6SEL_1           (0x2U << RCC_DCKCFGR2_USART6SEL_Pos) /*!< 0x00000800 */\r\n#define RCC_DCKCFGR2_UART7SEL_Pos          (12U)                               \r\n#define RCC_DCKCFGR2_UART7SEL_Msk          (0x3U << RCC_DCKCFGR2_UART7SEL_Pos) /*!< 0x00003000 */\r\n#define RCC_DCKCFGR2_UART7SEL              RCC_DCKCFGR2_UART7SEL_Msk           \r\n#define RCC_DCKCFGR2_UART7SEL_0            (0x1U << RCC_DCKCFGR2_UART7SEL_Pos) /*!< 0x00001000 */\r\n#define RCC_DCKCFGR2_UART7SEL_1            (0x2U << RCC_DCKCFGR2_UART7SEL_Pos) /*!< 0x00002000 */\r\n#define RCC_DCKCFGR2_UART8SEL_Pos          (14U)                               \r\n#define RCC_DCKCFGR2_UART8SEL_Msk          (0x3U << RCC_DCKCFGR2_UART8SEL_Pos) /*!< 0x0000C000 */\r\n#define RCC_DCKCFGR2_UART8SEL              RCC_DCKCFGR2_UART8SEL_Msk           \r\n#define RCC_DCKCFGR2_UART8SEL_0            (0x1U << RCC_DCKCFGR2_UART8SEL_Pos) /*!< 0x00004000 */\r\n#define RCC_DCKCFGR2_UART8SEL_1            (0x2U << RCC_DCKCFGR2_UART8SEL_Pos) /*!< 0x00008000 */\r\n#define RCC_DCKCFGR2_I2C1SEL_Pos           (16U)                               \r\n#define RCC_DCKCFGR2_I2C1SEL_Msk           (0x3U << RCC_DCKCFGR2_I2C1SEL_Pos)  /*!< 0x00030000 */\r\n#define RCC_DCKCFGR2_I2C1SEL               RCC_DCKCFGR2_I2C1SEL_Msk            \r\n#define RCC_DCKCFGR2_I2C1SEL_0             (0x1U << RCC_DCKCFGR2_I2C1SEL_Pos)  /*!< 0x00010000 */\r\n#define RCC_DCKCFGR2_I2C1SEL_1             (0x2U << RCC_DCKCFGR2_I2C1SEL_Pos)  /*!< 0x00020000 */\r\n#define RCC_DCKCFGR2_I2C2SEL_Pos           (18U)                               \r\n#define RCC_DCKCFGR2_I2C2SEL_Msk           (0x3U << RCC_DCKCFGR2_I2C2SEL_Pos)  /*!< 0x000C0000 */\r\n#define RCC_DCKCFGR2_I2C2SEL               RCC_DCKCFGR2_I2C2SEL_Msk            \r\n#define RCC_DCKCFGR2_I2C2SEL_0             (0x1U << RCC_DCKCFGR2_I2C2SEL_Pos)  /*!< 0x00040000 */\r\n#define RCC_DCKCFGR2_I2C2SEL_1             (0x2U << RCC_DCKCFGR2_I2C2SEL_Pos)  /*!< 0x00080000 */\r\n#define RCC_DCKCFGR2_I2C3SEL_Pos           (20U)                               \r\n#define RCC_DCKCFGR2_I2C3SEL_Msk           (0x3U << RCC_DCKCFGR2_I2C3SEL_Pos)  /*!< 0x00300000 */\r\n#define RCC_DCKCFGR2_I2C3SEL               RCC_DCKCFGR2_I2C3SEL_Msk            \r\n#define RCC_DCKCFGR2_I2C3SEL_0             (0x1U << RCC_DCKCFGR2_I2C3SEL_Pos)  /*!< 0x00100000 */\r\n#define RCC_DCKCFGR2_I2C3SEL_1             (0x2U << RCC_DCKCFGR2_I2C3SEL_Pos)  /*!< 0x00200000 */\r\n#define RCC_DCKCFGR2_I2C4SEL_Pos           (22U)                               \r\n#define RCC_DCKCFGR2_I2C4SEL_Msk           (0x3U << RCC_DCKCFGR2_I2C4SEL_Pos)  /*!< 0x00C00000 */\r\n#define RCC_DCKCFGR2_I2C4SEL               RCC_DCKCFGR2_I2C4SEL_Msk            \r\n#define RCC_DCKCFGR2_I2C4SEL_0             (0x1U << RCC_DCKCFGR2_I2C4SEL_Pos)  /*!< 0x00400000 */\r\n#define RCC_DCKCFGR2_I2C4SEL_1             (0x2U << RCC_DCKCFGR2_I2C4SEL_Pos)  /*!< 0x00800000 */\r\n#define RCC_DCKCFGR2_LPTIM1SEL_Pos         (24U)                               \r\n#define RCC_DCKCFGR2_LPTIM1SEL_Msk         (0x3U << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x03000000 */\r\n#define RCC_DCKCFGR2_LPTIM1SEL             RCC_DCKCFGR2_LPTIM1SEL_Msk          \r\n#define RCC_DCKCFGR2_LPTIM1SEL_0           (0x1U << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x01000000 */\r\n#define RCC_DCKCFGR2_LPTIM1SEL_1           (0x2U << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x02000000 */\r\n#define RCC_DCKCFGR2_CECSEL_Pos            (26U)                               \r\n#define RCC_DCKCFGR2_CECSEL_Msk            (0x1U << RCC_DCKCFGR2_CECSEL_Pos)   /*!< 0x04000000 */\r\n#define RCC_DCKCFGR2_CECSEL                RCC_DCKCFGR2_CECSEL_Msk             \r\n#define RCC_DCKCFGR2_CK48MSEL_Pos          (27U)                               \r\n#define RCC_DCKCFGR2_CK48MSEL_Msk          (0x1U << RCC_DCKCFGR2_CK48MSEL_Pos) /*!< 0x08000000 */\r\n#define RCC_DCKCFGR2_CK48MSEL              RCC_DCKCFGR2_CK48MSEL_Msk           \r\n#define RCC_DCKCFGR2_SDMMC1SEL_Pos         (28U)                               \r\n#define RCC_DCKCFGR2_SDMMC1SEL_Msk         (0x1U << RCC_DCKCFGR2_SDMMC1SEL_Pos) /*!< 0x10000000 */\r\n#define RCC_DCKCFGR2_SDMMC1SEL             RCC_DCKCFGR2_SDMMC1SEL_Msk          \r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                    RNG                                     */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bits definition for RNG_CR register  *******************/\r\n#define RNG_CR_RNGEN_Pos    (2U)                                               \r\n#define RNG_CR_RNGEN_Msk    (0x1U << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */\r\n#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk                                   \r\n#define RNG_CR_IE_Pos       (3U)                                               \r\n#define RNG_CR_IE_Msk       (0x1U << RNG_CR_IE_Pos)                            /*!< 0x00000008 */\r\n#define RNG_CR_IE           RNG_CR_IE_Msk                                      \r\n\r\n/********************  Bits definition for RNG_SR register  *******************/\r\n#define RNG_SR_DRDY_Pos     (0U)                                               \r\n#define RNG_SR_DRDY_Msk     (0x1U << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */\r\n#define RNG_SR_DRDY         RNG_SR_DRDY_Msk                                    \r\n#define RNG_SR_CECS_Pos     (1U)                                               \r\n#define RNG_SR_CECS_Msk     (0x1U << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */\r\n#define RNG_SR_CECS         RNG_SR_CECS_Msk                                    \r\n#define RNG_SR_SECS_Pos     (2U)                                               \r\n#define RNG_SR_SECS_Msk     (0x1U << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */\r\n#define RNG_SR_SECS         RNG_SR_SECS_Msk                                    \r\n#define RNG_SR_CEIS_Pos     (5U)                                               \r\n#define RNG_SR_CEIS_Msk     (0x1U << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */\r\n#define RNG_SR_CEIS         RNG_SR_CEIS_Msk                                    \r\n#define RNG_SR_SEIS_Pos     (6U)                                               \r\n#define RNG_SR_SEIS_Msk     (0x1U << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */\r\n#define RNG_SR_SEIS         RNG_SR_SEIS_Msk                                    \r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                           Real-Time Clock (RTC)                            */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bits definition for RTC_TR register  *******************/\r\n#define RTC_TR_PM_Pos                  (22U)                                   \r\n#define RTC_TR_PM_Msk                  (0x1U << RTC_TR_PM_Pos)                 /*!< 0x00400000 */\r\n#define RTC_TR_PM                      RTC_TR_PM_Msk                           \r\n#define RTC_TR_HT_Pos                  (20U)                                   \r\n#define RTC_TR_HT_Msk                  (0x3U << RTC_TR_HT_Pos)                 /*!< 0x00300000 */\r\n#define RTC_TR_HT                      RTC_TR_HT_Msk                           \r\n#define RTC_TR_HT_0                    (0x1U << RTC_TR_HT_Pos)                 /*!< 0x00100000 */\r\n#define RTC_TR_HT_1                    (0x2U << RTC_TR_HT_Pos)                 /*!< 0x00200000 */\r\n#define RTC_TR_HU_Pos                  (16U)                                   \r\n#define RTC_TR_HU_Msk                  (0xFU << RTC_TR_HU_Pos)                 /*!< 0x000F0000 */\r\n#define RTC_TR_HU                      RTC_TR_HU_Msk                           \r\n#define RTC_TR_HU_0                    (0x1U << RTC_TR_HU_Pos)                 /*!< 0x00010000 */\r\n#define RTC_TR_HU_1                    (0x2U << RTC_TR_HU_Pos)                 /*!< 0x00020000 */\r\n#define RTC_TR_HU_2                    (0x4U << RTC_TR_HU_Pos)                 /*!< 0x00040000 */\r\n#define RTC_TR_HU_3                    (0x8U << RTC_TR_HU_Pos)                 /*!< 0x00080000 */\r\n#define RTC_TR_MNT_Pos                 (12U)                                   \r\n#define RTC_TR_MNT_Msk                 (0x7U << RTC_TR_MNT_Pos)                /*!< 0x00007000 */\r\n#define RTC_TR_MNT                     RTC_TR_MNT_Msk                          \r\n#define RTC_TR_MNT_0                   (0x1U << RTC_TR_MNT_Pos)                /*!< 0x00001000 */\r\n#define RTC_TR_MNT_1                   (0x2U << RTC_TR_MNT_Pos)                /*!< 0x00002000 */\r\n#define RTC_TR_MNT_2                   (0x4U << RTC_TR_MNT_Pos)                /*!< 0x00004000 */\r\n#define RTC_TR_MNU_Pos                 (8U)                                    \r\n#define RTC_TR_MNU_Msk                 (0xFU << RTC_TR_MNU_Pos)                /*!< 0x00000F00 */\r\n#define RTC_TR_MNU                     RTC_TR_MNU_Msk                          \r\n#define RTC_TR_MNU_0                   (0x1U << RTC_TR_MNU_Pos)                /*!< 0x00000100 */\r\n#define RTC_TR_MNU_1                   (0x2U << RTC_TR_MNU_Pos)                /*!< 0x00000200 */\r\n#define RTC_TR_MNU_2                   (0x4U << RTC_TR_MNU_Pos)                /*!< 0x00000400 */\r\n#define RTC_TR_MNU_3                   (0x8U << RTC_TR_MNU_Pos)                /*!< 0x00000800 */\r\n#define RTC_TR_ST_Pos                  (4U)                                    \r\n#define RTC_TR_ST_Msk                  (0x7U << RTC_TR_ST_Pos)                 /*!< 0x00000070 */\r\n#define RTC_TR_ST                      RTC_TR_ST_Msk                           \r\n#define RTC_TR_ST_0                    (0x1U << RTC_TR_ST_Pos)                 /*!< 0x00000010 */\r\n#define RTC_TR_ST_1                    (0x2U << RTC_TR_ST_Pos)                 /*!< 0x00000020 */\r\n#define RTC_TR_ST_2                    (0x4U << RTC_TR_ST_Pos)                 /*!< 0x00000040 */\r\n#define RTC_TR_SU_Pos                  (0U)                                    \r\n#define RTC_TR_SU_Msk                  (0xFU << RTC_TR_SU_Pos)                 /*!< 0x0000000F */\r\n#define RTC_TR_SU                      RTC_TR_SU_Msk                           \r\n#define RTC_TR_SU_0                    (0x1U << RTC_TR_SU_Pos)                 /*!< 0x00000001 */\r\n#define RTC_TR_SU_1                    (0x2U << RTC_TR_SU_Pos)                 /*!< 0x00000002 */\r\n#define RTC_TR_SU_2                    (0x4U << RTC_TR_SU_Pos)                 /*!< 0x00000004 */\r\n#define RTC_TR_SU_3                    (0x8U << RTC_TR_SU_Pos)                 /*!< 0x00000008 */\r\n\r\n/********************  Bits definition for RTC_DR register  *******************/\r\n#define RTC_DR_YT_Pos                  (20U)                                   \r\n#define RTC_DR_YT_Msk                  (0xFU << RTC_DR_YT_Pos)                 /*!< 0x00F00000 */\r\n#define RTC_DR_YT                      RTC_DR_YT_Msk                           \r\n#define RTC_DR_YT_0                    (0x1U << RTC_DR_YT_Pos)                 /*!< 0x00100000 */\r\n#define RTC_DR_YT_1                    (0x2U << RTC_DR_YT_Pos)                 /*!< 0x00200000 */\r\n#define RTC_DR_YT_2                    (0x4U << RTC_DR_YT_Pos)                 /*!< 0x00400000 */\r\n#define RTC_DR_YT_3                    (0x8U << RTC_DR_YT_Pos)                 /*!< 0x00800000 */\r\n#define RTC_DR_YU_Pos                  (16U)                                   \r\n#define RTC_DR_YU_Msk                  (0xFU << RTC_DR_YU_Pos)                 /*!< 0x000F0000 */\r\n#define RTC_DR_YU                      RTC_DR_YU_Msk                           \r\n#define RTC_DR_YU_0                    (0x1U << RTC_DR_YU_Pos)                 /*!< 0x00010000 */\r\n#define RTC_DR_YU_1                    (0x2U << RTC_DR_YU_Pos)                 /*!< 0x00020000 */\r\n#define RTC_DR_YU_2                    (0x4U << RTC_DR_YU_Pos)                 /*!< 0x00040000 */\r\n#define RTC_DR_YU_3                    (0x8U << RTC_DR_YU_Pos)                 /*!< 0x00080000 */\r\n#define RTC_DR_WDU_Pos                 (13U)                                   \r\n#define RTC_DR_WDU_Msk                 (0x7U << RTC_DR_WDU_Pos)                /*!< 0x0000E000 */\r\n#define RTC_DR_WDU                     RTC_DR_WDU_Msk                          \r\n#define RTC_DR_WDU_0                   (0x1U << RTC_DR_WDU_Pos)                /*!< 0x00002000 */\r\n#define RTC_DR_WDU_1                   (0x2U << RTC_DR_WDU_Pos)                /*!< 0x00004000 */\r\n#define RTC_DR_WDU_2                   (0x4U << RTC_DR_WDU_Pos)                /*!< 0x00008000 */\r\n#define RTC_DR_MT_Pos                  (12U)                                   \r\n#define RTC_DR_MT_Msk                  (0x1U << RTC_DR_MT_Pos)                 /*!< 0x00001000 */\r\n#define RTC_DR_MT                      RTC_DR_MT_Msk                           \r\n#define RTC_DR_MU_Pos                  (8U)                                    \r\n#define RTC_DR_MU_Msk                  (0xFU << RTC_DR_MU_Pos)                 /*!< 0x00000F00 */\r\n#define RTC_DR_MU                      RTC_DR_MU_Msk                           \r\n#define RTC_DR_MU_0                    (0x1U << RTC_DR_MU_Pos)                 /*!< 0x00000100 */\r\n#define RTC_DR_MU_1                    (0x2U << RTC_DR_MU_Pos)                 /*!< 0x00000200 */\r\n#define RTC_DR_MU_2                    (0x4U << RTC_DR_MU_Pos)                 /*!< 0x00000400 */\r\n#define RTC_DR_MU_3                    (0x8U << RTC_DR_MU_Pos)                 /*!< 0x00000800 */\r\n#define RTC_DR_DT_Pos                  (4U)                                    \r\n#define RTC_DR_DT_Msk                  (0x3U << RTC_DR_DT_Pos)                 /*!< 0x00000030 */\r\n#define RTC_DR_DT                      RTC_DR_DT_Msk                           \r\n#define RTC_DR_DT_0                    (0x1U << RTC_DR_DT_Pos)                 /*!< 0x00000010 */\r\n#define RTC_DR_DT_1                    (0x2U << RTC_DR_DT_Pos)                 /*!< 0x00000020 */\r\n#define RTC_DR_DU_Pos                  (0U)                                    \r\n#define RTC_DR_DU_Msk                  (0xFU << RTC_DR_DU_Pos)                 /*!< 0x0000000F */\r\n#define RTC_DR_DU                      RTC_DR_DU_Msk                           \r\n#define RTC_DR_DU_0                    (0x1U << RTC_DR_DU_Pos)                 /*!< 0x00000001 */\r\n#define RTC_DR_DU_1                    (0x2U << RTC_DR_DU_Pos)                 /*!< 0x00000002 */\r\n#define RTC_DR_DU_2                    (0x4U << RTC_DR_DU_Pos)                 /*!< 0x00000004 */\r\n#define RTC_DR_DU_3                    (0x8U << RTC_DR_DU_Pos)                 /*!< 0x00000008 */\r\n\r\n/********************  Bits definition for RTC_CR register  *******************/\r\n#define RTC_CR_ITSE_Pos                (24U)                                   \r\n#define RTC_CR_ITSE_Msk                (0x1U << RTC_CR_ITSE_Pos)               /*!< 0x01000000 */\r\n#define RTC_CR_ITSE                    RTC_CR_ITSE_Msk                         \r\n#define RTC_CR_COE_Pos                 (23U)                                   \r\n#define RTC_CR_COE_Msk                 (0x1U << RTC_CR_COE_Pos)                /*!< 0x00800000 */\r\n#define RTC_CR_COE                     RTC_CR_COE_Msk                          \r\n#define RTC_CR_OSEL_Pos                (21U)                                   \r\n#define RTC_CR_OSEL_Msk                (0x3U << RTC_CR_OSEL_Pos)               /*!< 0x00600000 */\r\n#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk                         \r\n#define RTC_CR_OSEL_0                  (0x1U << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */\r\n#define RTC_CR_OSEL_1                  (0x2U << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */\r\n#define RTC_CR_POL_Pos                 (20U)                                   \r\n#define RTC_CR_POL_Msk                 (0x1U << RTC_CR_POL_Pos)                /*!< 0x00100000 */\r\n#define RTC_CR_POL                     RTC_CR_POL_Msk                          \r\n#define RTC_CR_COSEL_Pos               (19U)                                   \r\n#define RTC_CR_COSEL_Msk               (0x1U << RTC_CR_COSEL_Pos)              /*!< 0x00080000 */\r\n#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk                        \r\n#define RTC_CR_BKP_Pos                 (18U)                                   \r\n#define RTC_CR_BKP_Msk                 (0x1U << RTC_CR_BKP_Pos)                /*!< 0x00040000 */\r\n#define RTC_CR_BKP                     RTC_CR_BKP_Msk                          \r\n#define RTC_CR_SUB1H_Pos               (17U)                                   \r\n#define RTC_CR_SUB1H_Msk               (0x1U << RTC_CR_SUB1H_Pos)              /*!< 0x00020000 */\r\n#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk                        \r\n#define RTC_CR_ADD1H_Pos               (16U)                                   \r\n#define RTC_CR_ADD1H_Msk               (0x1U << RTC_CR_ADD1H_Pos)              /*!< 0x00010000 */\r\n#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk                        \r\n#define RTC_CR_TSIE_Pos                (15U)                                   \r\n#define RTC_CR_TSIE_Msk                (0x1U << RTC_CR_TSIE_Pos)               /*!< 0x00008000 */\r\n#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk                         \r\n#define RTC_CR_WUTIE_Pos               (14U)                                   \r\n#define RTC_CR_WUTIE_Msk               (0x1U << RTC_CR_WUTIE_Pos)              /*!< 0x00004000 */\r\n#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk                        \r\n#define RTC_CR_ALRBIE_Pos              (13U)                                   \r\n#define RTC_CR_ALRBIE_Msk              (0x1U << RTC_CR_ALRBIE_Pos)             /*!< 0x00002000 */\r\n#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk                       \r\n#define RTC_CR_ALRAIE_Pos              (12U)                                   \r\n#define RTC_CR_ALRAIE_Msk              (0x1U << RTC_CR_ALRAIE_Pos)             /*!< 0x00001000 */\r\n#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk                       \r\n#define RTC_CR_TSE_Pos                 (11U)                                   \r\n#define RTC_CR_TSE_Msk                 (0x1U << RTC_CR_TSE_Pos)                /*!< 0x00000800 */\r\n#define RTC_CR_TSE                     RTC_CR_TSE_Msk                          \r\n#define RTC_CR_WUTE_Pos                (10U)                                   \r\n#define RTC_CR_WUTE_Msk                (0x1U << RTC_CR_WUTE_Pos)               /*!< 0x00000400 */\r\n#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk                         \r\n#define RTC_CR_ALRBE_Pos               (9U)                                    \r\n#define RTC_CR_ALRBE_Msk               (0x1U << RTC_CR_ALRBE_Pos)              /*!< 0x00000200 */\r\n#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk                        \r\n#define RTC_CR_ALRAE_Pos               (8U)                                    \r\n#define RTC_CR_ALRAE_Msk               (0x1U << RTC_CR_ALRAE_Pos)              /*!< 0x00000100 */\r\n#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk                        \r\n#define RTC_CR_FMT_Pos                 (6U)                                    \r\n#define RTC_CR_FMT_Msk                 (0x1U << RTC_CR_FMT_Pos)                /*!< 0x00000040 */\r\n#define RTC_CR_FMT                     RTC_CR_FMT_Msk                          \r\n#define RTC_CR_BYPSHAD_Pos             (5U)                                    \r\n#define RTC_CR_BYPSHAD_Msk             (0x1U << RTC_CR_BYPSHAD_Pos)            /*!< 0x00000020 */\r\n#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk                      \r\n#define RTC_CR_REFCKON_Pos             (4U)                                    \r\n#define RTC_CR_REFCKON_Msk             (0x1U << RTC_CR_REFCKON_Pos)            /*!< 0x00000010 */\r\n#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk                      \r\n#define RTC_CR_TSEDGE_Pos              (3U)                                    \r\n#define RTC_CR_TSEDGE_Msk              (0x1U << RTC_CR_TSEDGE_Pos)             /*!< 0x00000008 */\r\n#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk                       \r\n#define RTC_CR_WUCKSEL_Pos             (0U)                                    \r\n#define RTC_CR_WUCKSEL_Msk             (0x7U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000007 */\r\n#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk                      \r\n#define RTC_CR_WUCKSEL_0               (0x1U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */\r\n#define RTC_CR_WUCKSEL_1               (0x2U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */\r\n#define RTC_CR_WUCKSEL_2               (0x4U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */\r\n\r\n/* Legacy define */\r\n#define RTC_CR_BCK                           RTC_CR_BKP\r\n\r\n/********************  Bits definition for RTC_ISR register  ******************/\r\n#define RTC_ISR_ITSF_Pos               (17U)                                   \r\n#define RTC_ISR_ITSF_Msk               (0x1U << RTC_ISR_ITSF_Pos)              /*!< 0x00020000 */\r\n#define RTC_ISR_ITSF                   RTC_ISR_ITSF_Msk                        \r\n#define RTC_ISR_RECALPF_Pos            (16U)                                   \r\n#define RTC_ISR_RECALPF_Msk            (0x1U << RTC_ISR_RECALPF_Pos)           /*!< 0x00010000 */\r\n#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk                     \r\n#define RTC_ISR_TAMP3F_Pos             (15U)                                   \r\n#define RTC_ISR_TAMP3F_Msk             (0x1U << RTC_ISR_TAMP3F_Pos)            /*!< 0x00008000 */\r\n#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk                      \r\n#define RTC_ISR_TAMP2F_Pos             (14U)                                   \r\n#define RTC_ISR_TAMP2F_Msk             (0x1U << RTC_ISR_TAMP2F_Pos)            /*!< 0x00004000 */\r\n#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk                      \r\n#define RTC_ISR_TAMP1F_Pos             (13U)                                   \r\n#define RTC_ISR_TAMP1F_Msk             (0x1U << RTC_ISR_TAMP1F_Pos)            /*!< 0x00002000 */\r\n#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk                      \r\n#define RTC_ISR_TSOVF_Pos              (12U)                                   \r\n#define RTC_ISR_TSOVF_Msk              (0x1U << RTC_ISR_TSOVF_Pos)             /*!< 0x00001000 */\r\n#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk                       \r\n#define RTC_ISR_TSF_Pos                (11U)                                   \r\n#define RTC_ISR_TSF_Msk                (0x1U << RTC_ISR_TSF_Pos)               /*!< 0x00000800 */\r\n#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk                         \r\n#define RTC_ISR_WUTF_Pos               (10U)                                   \r\n#define RTC_ISR_WUTF_Msk               (0x1U << RTC_ISR_WUTF_Pos)              /*!< 0x00000400 */\r\n#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk                        \r\n#define RTC_ISR_ALRBF_Pos              (9U)                                    \r\n#define RTC_ISR_ALRBF_Msk              (0x1U << RTC_ISR_ALRBF_Pos)             /*!< 0x00000200 */\r\n#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk                       \r\n#define RTC_ISR_ALRAF_Pos              (8U)                                    \r\n#define RTC_ISR_ALRAF_Msk              (0x1U << RTC_ISR_ALRAF_Pos)             /*!< 0x00000100 */\r\n#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk                       \r\n#define RTC_ISR_INIT_Pos               (7U)                                    \r\n#define RTC_ISR_INIT_Msk               (0x1U << RTC_ISR_INIT_Pos)              /*!< 0x00000080 */\r\n#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk                        \r\n#define RTC_ISR_INITF_Pos              (6U)                                    \r\n#define RTC_ISR_INITF_Msk              (0x1U << RTC_ISR_INITF_Pos)             /*!< 0x00000040 */\r\n#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk                       \r\n#define RTC_ISR_RSF_Pos                (5U)                                    \r\n#define RTC_ISR_RSF_Msk                (0x1U << RTC_ISR_RSF_Pos)               /*!< 0x00000020 */\r\n#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk                         \r\n#define RTC_ISR_INITS_Pos              (4U)                                    \r\n#define RTC_ISR_INITS_Msk              (0x1U << RTC_ISR_INITS_Pos)             /*!< 0x00000010 */\r\n#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk                       \r\n#define RTC_ISR_SHPF_Pos               (3U)                                    \r\n#define RTC_ISR_SHPF_Msk               (0x1U << RTC_ISR_SHPF_Pos)              /*!< 0x00000008 */\r\n#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk                        \r\n#define RTC_ISR_WUTWF_Pos              (2U)                                    \r\n#define RTC_ISR_WUTWF_Msk              (0x1U << RTC_ISR_WUTWF_Pos)             /*!< 0x00000004 */\r\n#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk                       \r\n#define RTC_ISR_ALRBWF_Pos             (1U)                                    \r\n#define RTC_ISR_ALRBWF_Msk             (0x1U << RTC_ISR_ALRBWF_Pos)            /*!< 0x00000002 */\r\n#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk                      \r\n#define RTC_ISR_ALRAWF_Pos             (0U)                                    \r\n#define RTC_ISR_ALRAWF_Msk             (0x1U << RTC_ISR_ALRAWF_Pos)            /*!< 0x00000001 */\r\n#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk                      \r\n\r\n/********************  Bits definition for RTC_PRER register  *****************/\r\n#define RTC_PRER_PREDIV_A_Pos          (16U)                                   \r\n#define RTC_PRER_PREDIV_A_Msk          (0x7FU << RTC_PRER_PREDIV_A_Pos)        /*!< 0x007F0000 */\r\n#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk                   \r\n#define RTC_PRER_PREDIV_S_Pos          (0U)                                    \r\n#define RTC_PRER_PREDIV_S_Msk          (0x7FFFU << RTC_PRER_PREDIV_S_Pos)      /*!< 0x00007FFF */\r\n#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk                   \r\n\r\n/********************  Bits definition for RTC_WUTR register  *****************/\r\n#define RTC_WUTR_WUT_Pos               (0U)                                    \r\n#define RTC_WUTR_WUT_Msk               (0xFFFFU << RTC_WUTR_WUT_Pos)           /*!< 0x0000FFFF */\r\n#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk                        \r\n\r\n/********************  Bits definition for RTC_ALRMAR register  ***************/\r\n#define RTC_ALRMAR_MSK4_Pos            (31U)                                   \r\n#define RTC_ALRMAR_MSK4_Msk            (0x1U << RTC_ALRMAR_MSK4_Pos)           /*!< 0x80000000 */\r\n#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk                     \r\n#define RTC_ALRMAR_WDSEL_Pos           (30U)                                   \r\n#define RTC_ALRMAR_WDSEL_Msk           (0x1U << RTC_ALRMAR_WDSEL_Pos)          /*!< 0x40000000 */\r\n#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk                    \r\n#define RTC_ALRMAR_DT_Pos              (28U)                                   \r\n#define RTC_ALRMAR_DT_Msk              (0x3U << RTC_ALRMAR_DT_Pos)             /*!< 0x30000000 */\r\n#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk                       \r\n#define RTC_ALRMAR_DT_0                (0x1U << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */\r\n#define RTC_ALRMAR_DT_1                (0x2U << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */\r\n#define RTC_ALRMAR_DU_Pos              (24U)                                   \r\n#define RTC_ALRMAR_DU_Msk              (0xFU << RTC_ALRMAR_DU_Pos)             /*!< 0x0F000000 */\r\n#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk                       \r\n#define RTC_ALRMAR_DU_0                (0x1U << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */\r\n#define RTC_ALRMAR_DU_1                (0x2U << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */\r\n#define RTC_ALRMAR_DU_2                (0x4U << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */\r\n#define RTC_ALRMAR_DU_3                (0x8U << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */\r\n#define RTC_ALRMAR_MSK3_Pos            (23U)                                   \r\n#define RTC_ALRMAR_MSK3_Msk            (0x1U << RTC_ALRMAR_MSK3_Pos)           /*!< 0x00800000 */\r\n#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk                     \r\n#define RTC_ALRMAR_PM_Pos              (22U)                                   \r\n#define RTC_ALRMAR_PM_Msk              (0x1U << RTC_ALRMAR_PM_Pos)             /*!< 0x00400000 */\r\n#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk                       \r\n#define RTC_ALRMAR_HT_Pos              (20U)                                   \r\n#define RTC_ALRMAR_HT_Msk              (0x3U << RTC_ALRMAR_HT_Pos)             /*!< 0x00300000 */\r\n#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk                       \r\n#define RTC_ALRMAR_HT_0                (0x1U << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */\r\n#define RTC_ALRMAR_HT_1                (0x2U << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */\r\n#define RTC_ALRMAR_HU_Pos              (16U)                                   \r\n#define RTC_ALRMAR_HU_Msk              (0xFU << RTC_ALRMAR_HU_Pos)             /*!< 0x000F0000 */\r\n#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk                       \r\n#define RTC_ALRMAR_HU_0                (0x1U << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */\r\n#define RTC_ALRMAR_HU_1                (0x2U << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */\r\n#define RTC_ALRMAR_HU_2                (0x4U << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */\r\n#define RTC_ALRMAR_HU_3                (0x8U << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */\r\n#define RTC_ALRMAR_MSK2_Pos            (15U)                                   \r\n#define RTC_ALRMAR_MSK2_Msk            (0x1U << RTC_ALRMAR_MSK2_Pos)           /*!< 0x00008000 */\r\n#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk                     \r\n#define RTC_ALRMAR_MNT_Pos             (12U)                                   \r\n#define RTC_ALRMAR_MNT_Msk             (0x7U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00007000 */\r\n#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk                      \r\n#define RTC_ALRMAR_MNT_0               (0x1U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */\r\n#define RTC_ALRMAR_MNT_1               (0x2U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */\r\n#define RTC_ALRMAR_MNT_2               (0x4U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */\r\n#define RTC_ALRMAR_MNU_Pos             (8U)                                    \r\n#define RTC_ALRMAR_MNU_Msk             (0xFU << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000F00 */\r\n#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk                      \r\n#define RTC_ALRMAR_MNU_0               (0x1U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */\r\n#define RTC_ALRMAR_MNU_1               (0x2U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */\r\n#define RTC_ALRMAR_MNU_2               (0x4U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */\r\n#define RTC_ALRMAR_MNU_3               (0x8U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */\r\n#define RTC_ALRMAR_MSK1_Pos            (7U)                                    \r\n#define RTC_ALRMAR_MSK1_Msk            (0x1U << RTC_ALRMAR_MSK1_Pos)           /*!< 0x00000080 */\r\n#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk                     \r\n#define RTC_ALRMAR_ST_Pos              (4U)                                    \r\n#define RTC_ALRMAR_ST_Msk              (0x7U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000070 */\r\n#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk                       \r\n#define RTC_ALRMAR_ST_0                (0x1U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */\r\n#define RTC_ALRMAR_ST_1                (0x2U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */\r\n#define RTC_ALRMAR_ST_2                (0x4U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */\r\n#define RTC_ALRMAR_SU_Pos              (0U)                                    \r\n#define RTC_ALRMAR_SU_Msk              (0xFU << RTC_ALRMAR_SU_Pos)             /*!< 0x0000000F */\r\n#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk                       \r\n#define RTC_ALRMAR_SU_0                (0x1U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */\r\n#define RTC_ALRMAR_SU_1                (0x2U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */\r\n#define RTC_ALRMAR_SU_2                (0x4U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */\r\n#define RTC_ALRMAR_SU_3                (0x8U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */\r\n\r\n/********************  Bits definition for RTC_ALRMBR register  ***************/\r\n#define RTC_ALRMBR_MSK4_Pos            (31U)                                   \r\n#define RTC_ALRMBR_MSK4_Msk            (0x1U << RTC_ALRMBR_MSK4_Pos)           /*!< 0x80000000 */\r\n#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk                     \r\n#define RTC_ALRMBR_WDSEL_Pos           (30U)                                   \r\n#define RTC_ALRMBR_WDSEL_Msk           (0x1U << RTC_ALRMBR_WDSEL_Pos)          /*!< 0x40000000 */\r\n#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk                    \r\n#define RTC_ALRMBR_DT_Pos              (28U)                                   \r\n#define RTC_ALRMBR_DT_Msk              (0x3U << RTC_ALRMBR_DT_Pos)             /*!< 0x30000000 */\r\n#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk                       \r\n#define RTC_ALRMBR_DT_0                (0x1U << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */\r\n#define RTC_ALRMBR_DT_1                (0x2U << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */\r\n#define RTC_ALRMBR_DU_Pos              (24U)                                   \r\n#define RTC_ALRMBR_DU_Msk              (0xFU << RTC_ALRMBR_DU_Pos)             /*!< 0x0F000000 */\r\n#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk                       \r\n#define RTC_ALRMBR_DU_0                (0x1U << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */\r\n#define RTC_ALRMBR_DU_1                (0x2U << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */\r\n#define RTC_ALRMBR_DU_2                (0x4U << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */\r\n#define RTC_ALRMBR_DU_3                (0x8U << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */\r\n#define RTC_ALRMBR_MSK3_Pos            (23U)                                   \r\n#define RTC_ALRMBR_MSK3_Msk            (0x1U << RTC_ALRMBR_MSK3_Pos)           /*!< 0x00800000 */\r\n#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk                     \r\n#define RTC_ALRMBR_PM_Pos              (22U)                                   \r\n#define RTC_ALRMBR_PM_Msk              (0x1U << RTC_ALRMBR_PM_Pos)             /*!< 0x00400000 */\r\n#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk                       \r\n#define RTC_ALRMBR_HT_Pos              (20U)                                   \r\n#define RTC_ALRMBR_HT_Msk              (0x3U << RTC_ALRMBR_HT_Pos)             /*!< 0x00300000 */\r\n#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk                       \r\n#define RTC_ALRMBR_HT_0                (0x1U << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */\r\n#define RTC_ALRMBR_HT_1                (0x2U << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */\r\n#define RTC_ALRMBR_HU_Pos              (16U)                                   \r\n#define RTC_ALRMBR_HU_Msk              (0xFU << RTC_ALRMBR_HU_Pos)             /*!< 0x000F0000 */\r\n#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk                       \r\n#define RTC_ALRMBR_HU_0                (0x1U << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */\r\n#define RTC_ALRMBR_HU_1                (0x2U << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */\r\n#define RTC_ALRMBR_HU_2                (0x4U << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */\r\n#define RTC_ALRMBR_HU_3                (0x8U << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */\r\n#define RTC_ALRMBR_MSK2_Pos            (15U)                                   \r\n#define RTC_ALRMBR_MSK2_Msk            (0x1U << RTC_ALRMBR_MSK2_Pos)           /*!< 0x00008000 */\r\n#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk                     \r\n#define RTC_ALRMBR_MNT_Pos             (12U)                                   \r\n#define RTC_ALRMBR_MNT_Msk             (0x7U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00007000 */\r\n#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk                      \r\n#define RTC_ALRMBR_MNT_0               (0x1U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */\r\n#define RTC_ALRMBR_MNT_1               (0x2U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */\r\n#define RTC_ALRMBR_MNT_2               (0x4U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */\r\n#define RTC_ALRMBR_MNU_Pos             (8U)                                    \r\n#define RTC_ALRMBR_MNU_Msk             (0xFU << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000F00 */\r\n#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk                      \r\n#define RTC_ALRMBR_MNU_0               (0x1U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */\r\n#define RTC_ALRMBR_MNU_1               (0x2U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */\r\n#define RTC_ALRMBR_MNU_2               (0x4U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */\r\n#define RTC_ALRMBR_MNU_3               (0x8U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */\r\n#define RTC_ALRMBR_MSK1_Pos            (7U)                                    \r\n#define RTC_ALRMBR_MSK1_Msk            (0x1U << RTC_ALRMBR_MSK1_Pos)           /*!< 0x00000080 */\r\n#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk                     \r\n#define RTC_ALRMBR_ST_Pos              (4U)                                    \r\n#define RTC_ALRMBR_ST_Msk              (0x7U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000070 */\r\n#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk                       \r\n#define RTC_ALRMBR_ST_0                (0x1U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */\r\n#define RTC_ALRMBR_ST_1                (0x2U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */\r\n#define RTC_ALRMBR_ST_2                (0x4U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */\r\n#define RTC_ALRMBR_SU_Pos              (0U)                                    \r\n#define RTC_ALRMBR_SU_Msk              (0xFU << RTC_ALRMBR_SU_Pos)             /*!< 0x0000000F */\r\n#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk                       \r\n#define RTC_ALRMBR_SU_0                (0x1U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */\r\n#define RTC_ALRMBR_SU_1                (0x2U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */\r\n#define RTC_ALRMBR_SU_2                (0x4U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */\r\n#define RTC_ALRMBR_SU_3                (0x8U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */\r\n\r\n/********************  Bits definition for RTC_WPR register  ******************/\r\n#define RTC_WPR_KEY_Pos                (0U)                                    \r\n#define RTC_WPR_KEY_Msk                (0xFFU << RTC_WPR_KEY_Pos)              /*!< 0x000000FF */\r\n#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk                         \r\n\r\n/********************  Bits definition for RTC_SSR register  ******************/\r\n#define RTC_SSR_SS_Pos                 (0U)                                    \r\n#define RTC_SSR_SS_Msk                 (0xFFFFU << RTC_SSR_SS_Pos)             /*!< 0x0000FFFF */\r\n#define RTC_SSR_SS                     RTC_SSR_SS_Msk                          \r\n\r\n/********************  Bits definition for RTC_SHIFTR register  ***************/\r\n#define RTC_SHIFTR_SUBFS_Pos           (0U)                                    \r\n#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFU << RTC_SHIFTR_SUBFS_Pos)       /*!< 0x00007FFF */\r\n#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk                    \r\n#define RTC_SHIFTR_ADD1S_Pos           (31U)                                   \r\n#define RTC_SHIFTR_ADD1S_Msk           (0x1U << RTC_SHIFTR_ADD1S_Pos)          /*!< 0x80000000 */\r\n#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk                    \r\n\r\n/********************  Bits definition for RTC_TSTR register  *****************/\r\n#define RTC_TSTR_PM_Pos                (22U)                                   \r\n#define RTC_TSTR_PM_Msk                (0x1U << RTC_TSTR_PM_Pos)               /*!< 0x00400000 */\r\n#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk                         \r\n#define RTC_TSTR_HT_Pos                (20U)                                   \r\n#define RTC_TSTR_HT_Msk                (0x3U << RTC_TSTR_HT_Pos)               /*!< 0x00300000 */\r\n#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk                         \r\n#define RTC_TSTR_HT_0                  (0x1U << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */\r\n#define RTC_TSTR_HT_1                  (0x2U << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */\r\n#define RTC_TSTR_HU_Pos                (16U)                                   \r\n#define RTC_TSTR_HU_Msk                (0xFU << RTC_TSTR_HU_Pos)               /*!< 0x000F0000 */\r\n#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk                         \r\n#define RTC_TSTR_HU_0                  (0x1U << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */\r\n#define RTC_TSTR_HU_1                  (0x2U << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */\r\n#define RTC_TSTR_HU_2                  (0x4U << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */\r\n#define RTC_TSTR_HU_3                  (0x8U << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */\r\n#define RTC_TSTR_MNT_Pos               (12U)                                   \r\n#define RTC_TSTR_MNT_Msk               (0x7U << RTC_TSTR_MNT_Pos)              /*!< 0x00007000 */\r\n#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk                        \r\n#define RTC_TSTR_MNT_0                 (0x1U << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */\r\n#define RTC_TSTR_MNT_1                 (0x2U << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */\r\n#define RTC_TSTR_MNT_2                 (0x4U << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */\r\n#define RTC_TSTR_MNU_Pos               (8U)                                    \r\n#define RTC_TSTR_MNU_Msk               (0xFU << RTC_TSTR_MNU_Pos)              /*!< 0x00000F00 */\r\n#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk                        \r\n#define RTC_TSTR_MNU_0                 (0x1U << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */\r\n#define RTC_TSTR_MNU_1                 (0x2U << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */\r\n#define RTC_TSTR_MNU_2                 (0x4U << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */\r\n#define RTC_TSTR_MNU_3                 (0x8U << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */\r\n#define RTC_TSTR_ST_Pos                (4U)                                    \r\n#define RTC_TSTR_ST_Msk                (0x7U << RTC_TSTR_ST_Pos)               /*!< 0x00000070 */\r\n#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk                         \r\n#define RTC_TSTR_ST_0                  (0x1U << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */\r\n#define RTC_TSTR_ST_1                  (0x2U << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */\r\n#define RTC_TSTR_ST_2                  (0x4U << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */\r\n#define RTC_TSTR_SU_Pos                (0U)                                    \r\n#define RTC_TSTR_SU_Msk                (0xFU << RTC_TSTR_SU_Pos)               /*!< 0x0000000F */\r\n#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk                         \r\n#define RTC_TSTR_SU_0                  (0x1U << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */\r\n#define RTC_TSTR_SU_1                  (0x2U << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */\r\n#define RTC_TSTR_SU_2                  (0x4U << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */\r\n#define RTC_TSTR_SU_3                  (0x8U << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */\r\n\r\n/********************  Bits definition for RTC_TSDR register  *****************/\r\n#define RTC_TSDR_WDU_Pos               (13U)                                   \r\n#define RTC_TSDR_WDU_Msk               (0x7U << RTC_TSDR_WDU_Pos)              /*!< 0x0000E000 */\r\n#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk                        \r\n#define RTC_TSDR_WDU_0                 (0x1U << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */\r\n#define RTC_TSDR_WDU_1                 (0x2U << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */\r\n#define RTC_TSDR_WDU_2                 (0x4U << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */\r\n#define RTC_TSDR_MT_Pos                (12U)                                   \r\n#define RTC_TSDR_MT_Msk                (0x1U << RTC_TSDR_MT_Pos)               /*!< 0x00001000 */\r\n#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk                         \r\n#define RTC_TSDR_MU_Pos                (8U)                                    \r\n#define RTC_TSDR_MU_Msk                (0xFU << RTC_TSDR_MU_Pos)               /*!< 0x00000F00 */\r\n#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk                         \r\n#define RTC_TSDR_MU_0                  (0x1U << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */\r\n#define RTC_TSDR_MU_1                  (0x2U << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */\r\n#define RTC_TSDR_MU_2                  (0x4U << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */\r\n#define RTC_TSDR_MU_3                  (0x8U << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */\r\n#define RTC_TSDR_DT_Pos                (4U)                                    \r\n#define RTC_TSDR_DT_Msk                (0x3U << RTC_TSDR_DT_Pos)               /*!< 0x00000030 */\r\n#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk                         \r\n#define RTC_TSDR_DT_0                  (0x1U << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */\r\n#define RTC_TSDR_DT_1                  (0x2U << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */\r\n#define RTC_TSDR_DU_Pos                (0U)                                    \r\n#define RTC_TSDR_DU_Msk                (0xFU << RTC_TSDR_DU_Pos)               /*!< 0x0000000F */\r\n#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk                         \r\n#define RTC_TSDR_DU_0                  (0x1U << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */\r\n#define RTC_TSDR_DU_1                  (0x2U << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */\r\n#define RTC_TSDR_DU_2                  (0x4U << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */\r\n#define RTC_TSDR_DU_3                  (0x8U << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */\r\n\r\n/********************  Bits definition for RTC_TSSSR register  ****************/\r\n#define RTC_TSSSR_SS_Pos               (0U)                                    \r\n#define RTC_TSSSR_SS_Msk               (0xFFFFU << RTC_TSSSR_SS_Pos)           /*!< 0x0000FFFF */\r\n#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk                        \r\n\r\n/********************  Bits definition for RTC_CAL register  *****************/\r\n#define RTC_CALR_CALP_Pos              (15U)                                   \r\n#define RTC_CALR_CALP_Msk              (0x1U << RTC_CALR_CALP_Pos)             /*!< 0x00008000 */\r\n#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk                       \r\n#define RTC_CALR_CALW8_Pos             (14U)                                   \r\n#define RTC_CALR_CALW8_Msk             (0x1U << RTC_CALR_CALW8_Pos)            /*!< 0x00004000 */\r\n#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk                      \r\n#define RTC_CALR_CALW16_Pos            (13U)                                   \r\n#define RTC_CALR_CALW16_Msk            (0x1U << RTC_CALR_CALW16_Pos)           /*!< 0x00002000 */\r\n#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk                     \r\n#define RTC_CALR_CALM_Pos              (0U)                                    \r\n#define RTC_CALR_CALM_Msk              (0x1FFU << RTC_CALR_CALM_Pos)           /*!< 0x000001FF */\r\n#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk                       \r\n#define RTC_CALR_CALM_0                (0x001U << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */\r\n#define RTC_CALR_CALM_1                (0x002U << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */\r\n#define RTC_CALR_CALM_2                (0x004U << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */\r\n#define RTC_CALR_CALM_3                (0x008U << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */\r\n#define RTC_CALR_CALM_4                (0x010U << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */\r\n#define RTC_CALR_CALM_5                (0x020U << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */\r\n#define RTC_CALR_CALM_6                (0x040U << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */\r\n#define RTC_CALR_CALM_7                (0x080U << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */\r\n#define RTC_CALR_CALM_8                (0x100U << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */\r\n\r\n/********************  Bits definition for RTC_TAMPCR register  ****************/\r\n#define RTC_TAMPCR_TAMP3MF_Pos         (24U)                                   \r\n#define RTC_TAMPCR_TAMP3MF_Msk         (0x1U << RTC_TAMPCR_TAMP3MF_Pos)        /*!< 0x01000000 */\r\n#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk                  \r\n#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)                                   \r\n#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1U << RTC_TAMPCR_TAMP3NOERASE_Pos)   /*!< 0x00800000 */\r\n#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk             \r\n#define RTC_TAMPCR_TAMP3IE_Pos         (22U)                                   \r\n#define RTC_TAMPCR_TAMP3IE_Msk         (0x1U << RTC_TAMPCR_TAMP3IE_Pos)        /*!< 0x00400000 */\r\n#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk                  \r\n#define RTC_TAMPCR_TAMP2MF_Pos         (21U)                                   \r\n#define RTC_TAMPCR_TAMP2MF_Msk         (0x1U << RTC_TAMPCR_TAMP2MF_Pos)        /*!< 0x00200000 */\r\n#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk                  \r\n#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)                                   \r\n#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos)   /*!< 0x00100000 */\r\n#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk             \r\n#define RTC_TAMPCR_TAMP2IE_Pos         (19U)                                   \r\n#define RTC_TAMPCR_TAMP2IE_Msk         (0x1U << RTC_TAMPCR_TAMP2IE_Pos)        /*!< 0x00080000 */\r\n#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk                  \r\n#define RTC_TAMPCR_TAMP1MF_Pos         (18U)                                   \r\n#define RTC_TAMPCR_TAMP1MF_Msk         (0x1U << RTC_TAMPCR_TAMP1MF_Pos)        /*!< 0x00040000 */\r\n#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk                  \r\n#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)                                   \r\n#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1U << RTC_TAMPCR_TAMP1NOERASE_Pos)   /*!< 0x00020000 */\r\n#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk             \r\n#define RTC_TAMPCR_TAMP1IE_Pos         (16U)                                   \r\n#define RTC_TAMPCR_TAMP1IE_Msk         (0x1U << RTC_TAMPCR_TAMP1IE_Pos)        /*!< 0x00010000 */\r\n#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk                  \r\n#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)                                   \r\n#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos)      /*!< 0x00008000 */\r\n#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk                \r\n#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)                                   \r\n#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00006000 */\r\n#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk                 \r\n#define RTC_TAMPCR_TAMPPRCH_0          (0x1U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */\r\n#define RTC_TAMPCR_TAMPPRCH_1          (0x2U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */\r\n#define RTC_TAMPCR_TAMPFLT_Pos         (11U)                                   \r\n#define RTC_TAMPCR_TAMPFLT_Msk         (0x3U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001800 */\r\n#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk                  \r\n#define RTC_TAMPCR_TAMPFLT_0           (0x1U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */\r\n#define RTC_TAMPCR_TAMPFLT_1           (0x2U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */\r\n#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)                                    \r\n#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000700 */\r\n#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk                 \r\n#define RTC_TAMPCR_TAMPFREQ_0          (0x1U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */\r\n#define RTC_TAMPCR_TAMPFREQ_1          (0x2U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */\r\n#define RTC_TAMPCR_TAMPFREQ_2          (0x4U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */\r\n#define RTC_TAMPCR_TAMPTS_Pos          (7U)                                    \r\n#define RTC_TAMPCR_TAMPTS_Msk          (0x1U << RTC_TAMPCR_TAMPTS_Pos)         /*!< 0x00000080 */\r\n#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk                   \r\n#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)                                    \r\n#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1U << RTC_TAMPCR_TAMP3TRG_Pos)       /*!< 0x00000040 */\r\n#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk                 \r\n#define RTC_TAMPCR_TAMP3E_Pos          (5U)                                    \r\n#define RTC_TAMPCR_TAMP3E_Msk          (0x1U << RTC_TAMPCR_TAMP3E_Pos)         /*!< 0x00000020 */\r\n#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk                   \r\n#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)                                    \r\n#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1U << RTC_TAMPCR_TAMP2TRG_Pos)       /*!< 0x00000010 */\r\n#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk                 \r\n#define RTC_TAMPCR_TAMP2E_Pos          (3U)                                    \r\n#define RTC_TAMPCR_TAMP2E_Msk          (0x1U << RTC_TAMPCR_TAMP2E_Pos)         /*!< 0x00000008 */\r\n#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk                   \r\n#define RTC_TAMPCR_TAMPIE_Pos          (2U)                                    \r\n#define RTC_TAMPCR_TAMPIE_Msk          (0x1U << RTC_TAMPCR_TAMPIE_Pos)         /*!< 0x00000004 */\r\n#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk                   \r\n#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)                                    \r\n#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1U << RTC_TAMPCR_TAMP1TRG_Pos)       /*!< 0x00000002 */\r\n#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk                 \r\n#define RTC_TAMPCR_TAMP1E_Pos          (0U)                                    \r\n#define RTC_TAMPCR_TAMP1E_Msk          (0x1U << RTC_TAMPCR_TAMP1E_Pos)         /*!< 0x00000001 */\r\n#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk                   \r\n\r\n/* Legacy defines */\r\n#define RTC_TAMPCR_TAMP3_TRG                  RTC_TAMPCR_TAMP3TRG\r\n#define RTC_TAMPCR_TAMP2_TRG                  RTC_TAMPCR_TAMP2TRG\r\n#define RTC_TAMPCR_TAMP1_TRG                  RTC_TAMPCR_TAMP1TRG\r\n\r\n/********************  Bits definition for RTC_ALRMASSR register  *************/\r\n#define RTC_ALRMASSR_MASKSS_Pos        (24U)                                   \r\n#define RTC_ALRMASSR_MASKSS_Msk        (0xFU << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x0F000000 */\r\n#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk                 \r\n#define RTC_ALRMASSR_MASKSS_0          (0x1U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */\r\n#define RTC_ALRMASSR_MASKSS_1          (0x2U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */\r\n#define RTC_ALRMASSR_MASKSS_2          (0x4U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */\r\n#define RTC_ALRMASSR_MASKSS_3          (0x8U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */\r\n#define RTC_ALRMASSR_SS_Pos            (0U)                                    \r\n#define RTC_ALRMASSR_SS_Msk            (0x7FFFU << RTC_ALRMASSR_SS_Pos)        /*!< 0x00007FFF */\r\n#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk                     \r\n\r\n/********************  Bits definition for RTC_ALRMBSSR register  *************/\r\n#define RTC_ALRMBSSR_MASKSS_Pos        (24U)                                   \r\n#define RTC_ALRMBSSR_MASKSS_Msk        (0xFU << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */\r\n#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk                 \r\n#define RTC_ALRMBSSR_MASKSS_0          (0x1U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */\r\n#define RTC_ALRMBSSR_MASKSS_1          (0x2U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */\r\n#define RTC_ALRMBSSR_MASKSS_2          (0x4U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */\r\n#define RTC_ALRMBSSR_MASKSS_3          (0x8U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */\r\n#define RTC_ALRMBSSR_SS_Pos            (0U)                                    \r\n#define RTC_ALRMBSSR_SS_Msk            (0x7FFFU << RTC_ALRMBSSR_SS_Pos)        /*!< 0x00007FFF */\r\n#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk                     \r\n\r\n/********************  Bits definition for RTC_OR register  ****************/\r\n#define RTC_OR_TSINSEL_Pos             (1U)                                    \r\n#define RTC_OR_TSINSEL_Msk             (0x3U << RTC_OR_TSINSEL_Pos)            /*!< 0x00000006 */\r\n#define RTC_OR_TSINSEL                 RTC_OR_TSINSEL_Msk                      \r\n#define RTC_OR_TSINSEL_0               (0x1U << RTC_OR_TSINSEL_Pos)            /*!< 0x00000002 */\r\n#define RTC_OR_TSINSEL_1               (0x2U << RTC_OR_TSINSEL_Pos)            /*!< 0x00000004 */\r\n#define RTC_OR_ALARMOUTTYPE_Pos        (3U)                                    \r\n#define RTC_OR_ALARMOUTTYPE_Msk        (0x1U << RTC_OR_ALARMOUTTYPE_Pos)       /*!< 0x00000008 */\r\n#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk\r\n/* Legacy defines*/                    \r\n#define RTC_OR_ALARMTYPE               RTC_OR_ALARMOUTTYPE\r\n\r\n/********************  Bits definition for RTC_BKP0R register  ****************/\r\n#define RTC_BKP0R_Pos                  (0U)                                    \r\n#define RTC_BKP0R_Msk                  (0xFFFFFFFFU << RTC_BKP0R_Pos)          /*!< 0xFFFFFFFF */\r\n#define RTC_BKP0R                      RTC_BKP0R_Msk                           \r\n\r\n/********************  Bits definition for RTC_BKP1R register  ****************/\r\n#define RTC_BKP1R_Pos                  (0U)                                    \r\n#define RTC_BKP1R_Msk                  (0xFFFFFFFFU << RTC_BKP1R_Pos)          /*!< 0xFFFFFFFF */\r\n#define RTC_BKP1R                      RTC_BKP1R_Msk                           \r\n\r\n/********************  Bits definition for RTC_BKP2R register  ****************/\r\n#define RTC_BKP2R_Pos                  (0U)                                    \r\n#define RTC_BKP2R_Msk                  (0xFFFFFFFFU << RTC_BKP2R_Pos)          /*!< 0xFFFFFFFF */\r\n#define RTC_BKP2R                      RTC_BKP2R_Msk                           \r\n\r\n/********************  Bits definition for RTC_BKP3R register  ****************/\r\n#define RTC_BKP3R_Pos                  (0U)                                    \r\n#define RTC_BKP3R_Msk                  (0xFFFFFFFFU << RTC_BKP3R_Pos)          /*!< 0xFFFFFFFF */\r\n#define RTC_BKP3R                      RTC_BKP3R_Msk                           \r\n\r\n/********************  Bits definition for RTC_BKP4R register  ****************/\r\n#define RTC_BKP4R_Pos                  (0U)                                    \r\n#define RTC_BKP4R_Msk                  (0xFFFFFFFFU << RTC_BKP4R_Pos)          /*!< 0xFFFFFFFF */\r\n#define RTC_BKP4R                      RTC_BKP4R_Msk                           \r\n\r\n/********************  Bits definition for RTC_BKP5R register  ****************/\r\n#define RTC_BKP5R_Pos                  (0U)                                    \r\n#define RTC_BKP5R_Msk                  (0xFFFFFFFFU << RTC_BKP5R_Pos)          /*!< 0xFFFFFFFF */\r\n#define RTC_BKP5R                      RTC_BKP5R_Msk                           \r\n\r\n/********************  Bits definition for RTC_BKP6R register  ****************/\r\n#define RTC_BKP6R_Pos                  (0U)                                    \r\n#define RTC_BKP6R_Msk                  (0xFFFFFFFFU << RTC_BKP6R_Pos)          /*!< 0xFFFFFFFF */\r\n#define RTC_BKP6R                      RTC_BKP6R_Msk                           \r\n\r\n/********************  Bits definition for RTC_BKP7R register  ****************/\r\n#define RTC_BKP7R_Pos                  (0U)                                    \r\n#define RTC_BKP7R_Msk                  (0xFFFFFFFFU << RTC_BKP7R_Pos)          /*!< 0xFFFFFFFF */\r\n#define RTC_BKP7R                      RTC_BKP7R_Msk                           \r\n\r\n/********************  Bits definition for RTC_BKP8R register  ****************/\r\n#define RTC_BKP8R_Pos                  (0U)                                    \r\n#define RTC_BKP8R_Msk                  (0xFFFFFFFFU << RTC_BKP8R_Pos)          /*!< 0xFFFFFFFF */\r\n#define RTC_BKP8R                      RTC_BKP8R_Msk                           \r\n\r\n/********************  Bits definition for RTC_BKP9R register  ****************/\r\n#define RTC_BKP9R_Pos                  (0U)                                    \r\n#define RTC_BKP9R_Msk                  (0xFFFFFFFFU << RTC_BKP9R_Pos)          /*!< 0xFFFFFFFF */\r\n#define RTC_BKP9R                      RTC_BKP9R_Msk                           \r\n\r\n/********************  Bits definition for RTC_BKP10R register  ***************/\r\n#define RTC_BKP10R_Pos                 (0U)                                    \r\n#define RTC_BKP10R_Msk                 (0xFFFFFFFFU << RTC_BKP10R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP10R                     RTC_BKP10R_Msk                          \r\n\r\n/********************  Bits definition for RTC_BKP11R register  ***************/\r\n#define RTC_BKP11R_Pos                 (0U)                                    \r\n#define RTC_BKP11R_Msk                 (0xFFFFFFFFU << RTC_BKP11R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP11R                     RTC_BKP11R_Msk                          \r\n\r\n/********************  Bits definition for RTC_BKP12R register  ***************/\r\n#define RTC_BKP12R_Pos                 (0U)                                    \r\n#define RTC_BKP12R_Msk                 (0xFFFFFFFFU << RTC_BKP12R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP12R                     RTC_BKP12R_Msk                          \r\n\r\n/********************  Bits definition for RTC_BKP13R register  ***************/\r\n#define RTC_BKP13R_Pos                 (0U)                                    \r\n#define RTC_BKP13R_Msk                 (0xFFFFFFFFU << RTC_BKP13R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP13R                     RTC_BKP13R_Msk                          \r\n\r\n/********************  Bits definition for RTC_BKP14R register  ***************/\r\n#define RTC_BKP14R_Pos                 (0U)                                    \r\n#define RTC_BKP14R_Msk                 (0xFFFFFFFFU << RTC_BKP14R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP14R                     RTC_BKP14R_Msk                          \r\n\r\n/********************  Bits definition for RTC_BKP15R register  ***************/\r\n#define RTC_BKP15R_Pos                 (0U)                                    \r\n#define RTC_BKP15R_Msk                 (0xFFFFFFFFU << RTC_BKP15R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP15R                     RTC_BKP15R_Msk                          \r\n\r\n/********************  Bits definition for RTC_BKP16R register  ***************/\r\n#define RTC_BKP16R_Pos                 (0U)                                    \r\n#define RTC_BKP16R_Msk                 (0xFFFFFFFFU << RTC_BKP16R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP16R                     RTC_BKP16R_Msk                          \r\n\r\n/********************  Bits definition for RTC_BKP17R register  ***************/\r\n#define RTC_BKP17R_Pos                 (0U)                                    \r\n#define RTC_BKP17R_Msk                 (0xFFFFFFFFU << RTC_BKP17R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP17R                     RTC_BKP17R_Msk                          \r\n\r\n/********************  Bits definition for RTC_BKP18R register  ***************/\r\n#define RTC_BKP18R_Pos                 (0U)                                    \r\n#define RTC_BKP18R_Msk                 (0xFFFFFFFFU << RTC_BKP18R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP18R                     RTC_BKP18R_Msk                          \r\n\r\n/********************  Bits definition for RTC_BKP19R register  ***************/\r\n#define RTC_BKP19R_Pos                 (0U)                                    \r\n#define RTC_BKP19R_Msk                 (0xFFFFFFFFU << RTC_BKP19R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP19R                     RTC_BKP19R_Msk                          \r\n\r\n/********************  Bits definition for RTC_BKP20R register  ***************/\r\n#define RTC_BKP20R_Pos                 (0U)                                    \r\n#define RTC_BKP20R_Msk                 (0xFFFFFFFFU << RTC_BKP20R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP20R                     RTC_BKP20R_Msk                          \r\n\r\n/********************  Bits definition for RTC_BKP21R register  ***************/\r\n#define RTC_BKP21R_Pos                 (0U)                                    \r\n#define RTC_BKP21R_Msk                 (0xFFFFFFFFU << RTC_BKP21R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP21R                     RTC_BKP21R_Msk                          \r\n\r\n/********************  Bits definition for RTC_BKP22R register  ***************/\r\n#define RTC_BKP22R_Pos                 (0U)                                    \r\n#define RTC_BKP22R_Msk                 (0xFFFFFFFFU << RTC_BKP22R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP22R                     RTC_BKP22R_Msk                          \r\n\r\n/********************  Bits definition for RTC_BKP23R register  ***************/\r\n#define RTC_BKP23R_Pos                 (0U)                                    \r\n#define RTC_BKP23R_Msk                 (0xFFFFFFFFU << RTC_BKP23R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP23R                     RTC_BKP23R_Msk                          \r\n\r\n/********************  Bits definition for RTC_BKP24R register  ***************/\r\n#define RTC_BKP24R_Pos                 (0U)                                    \r\n#define RTC_BKP24R_Msk                 (0xFFFFFFFFU << RTC_BKP24R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP24R                     RTC_BKP24R_Msk                          \r\n\r\n/********************  Bits definition for RTC_BKP25R register  ***************/\r\n#define RTC_BKP25R_Pos                 (0U)                                    \r\n#define RTC_BKP25R_Msk                 (0xFFFFFFFFU << RTC_BKP25R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP25R                     RTC_BKP25R_Msk                          \r\n\r\n/********************  Bits definition for RTC_BKP26R register  ***************/\r\n#define RTC_BKP26R_Pos                 (0U)                                    \r\n#define RTC_BKP26R_Msk                 (0xFFFFFFFFU << RTC_BKP26R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP26R                     RTC_BKP26R_Msk                          \r\n\r\n/********************  Bits definition for RTC_BKP27R register  ***************/\r\n#define RTC_BKP27R_Pos                 (0U)                                    \r\n#define RTC_BKP27R_Msk                 (0xFFFFFFFFU << RTC_BKP27R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP27R                     RTC_BKP27R_Msk                          \r\n\r\n/********************  Bits definition for RTC_BKP28R register  ***************/\r\n#define RTC_BKP28R_Pos                 (0U)                                    \r\n#define RTC_BKP28R_Msk                 (0xFFFFFFFFU << RTC_BKP28R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP28R                     RTC_BKP28R_Msk                          \r\n\r\n/********************  Bits definition for RTC_BKP29R register  ***************/\r\n#define RTC_BKP29R_Pos                 (0U)                                    \r\n#define RTC_BKP29R_Msk                 (0xFFFFFFFFU << RTC_BKP29R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP29R                     RTC_BKP29R_Msk                          \r\n\r\n/********************  Bits definition for RTC_BKP30R register  ***************/\r\n#define RTC_BKP30R_Pos                 (0U)                                    \r\n#define RTC_BKP30R_Msk                 (0xFFFFFFFFU << RTC_BKP30R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP30R                     RTC_BKP30R_Msk                          \r\n\r\n/********************  Bits definition for RTC_BKP31R register  ***************/\r\n#define RTC_BKP31R_Pos                 (0U)                                    \r\n#define RTC_BKP31R_Msk                 (0xFFFFFFFFU << RTC_BKP31R_Pos)         /*!< 0xFFFFFFFF */\r\n#define RTC_BKP31R                     RTC_BKP31R_Msk                          \r\n\r\n/******************** Number of backup registers ******************************/\r\n#define RTC_BKP_NUMBER                 0x00000020U\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                          Serial Audio Interface                            */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bit definition for SAI_GCR register  *******************/\r\n#define SAI_GCR_SYNCIN_Pos         (0U)                                        \r\n#define SAI_GCR_SYNCIN_Msk         (0x3U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000003 */\r\n#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */\r\n#define SAI_GCR_SYNCIN_0           (0x1U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */\r\n#define SAI_GCR_SYNCIN_1           (0x2U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */\r\n\r\n#define SAI_GCR_SYNCOUT_Pos        (4U)                                        \r\n#define SAI_GCR_SYNCOUT_Msk        (0x3U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000030 */\r\n#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */\r\n#define SAI_GCR_SYNCOUT_0          (0x1U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */\r\n#define SAI_GCR_SYNCOUT_1          (0x2U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */\r\n\r\n/*******************  Bit definition for SAI_xCR1 register  *******************/\r\n#define SAI_xCR1_MODE_Pos          (0U)                                        \r\n#define SAI_xCR1_MODE_Msk          (0x3U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000003 */\r\n#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */\r\n#define SAI_xCR1_MODE_0            (0x1U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */\r\n#define SAI_xCR1_MODE_1            (0x2U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */\r\n\r\n#define SAI_xCR1_PRTCFG_Pos        (2U)                                        \r\n#define SAI_xCR1_PRTCFG_Msk        (0x3U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x0000000C */\r\n#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */\r\n#define SAI_xCR1_PRTCFG_0          (0x1U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */\r\n#define SAI_xCR1_PRTCFG_1          (0x2U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */\r\n\r\n#define SAI_xCR1_DS_Pos            (5U)                                        \r\n#define SAI_xCR1_DS_Msk            (0x7U << SAI_xCR1_DS_Pos)                   /*!< 0x000000E0 */\r\n#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */\r\n#define SAI_xCR1_DS_0              (0x1U << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */\r\n#define SAI_xCR1_DS_1              (0x2U << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */\r\n#define SAI_xCR1_DS_2              (0x4U << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */\r\n\r\n#define SAI_xCR1_LSBFIRST_Pos      (8U)                                        \r\n#define SAI_xCR1_LSBFIRST_Msk      (0x1U << SAI_xCR1_LSBFIRST_Pos)             /*!< 0x00000100 */\r\n#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */\r\n#define SAI_xCR1_CKSTR_Pos         (9U)                                        \r\n#define SAI_xCR1_CKSTR_Msk         (0x1U << SAI_xCR1_CKSTR_Pos)                /*!< 0x00000200 */\r\n#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */\r\n\r\n#define SAI_xCR1_SYNCEN_Pos        (10U)                                       \r\n#define SAI_xCR1_SYNCEN_Msk        (0x3U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000C00 */\r\n#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */\r\n#define SAI_xCR1_SYNCEN_0          (0x1U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */\r\n#define SAI_xCR1_SYNCEN_1          (0x2U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */\r\n\r\n#define SAI_xCR1_MONO_Pos          (12U)                                       \r\n#define SAI_xCR1_MONO_Msk          (0x1U << SAI_xCR1_MONO_Pos)                 /*!< 0x00001000 */\r\n#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */\r\n#define SAI_xCR1_OUTDRIV_Pos       (13U)                                       \r\n#define SAI_xCR1_OUTDRIV_Msk       (0x1U << SAI_xCR1_OUTDRIV_Pos)              /*!< 0x00002000 */\r\n#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */\r\n#define SAI_xCR1_SAIEN_Pos         (16U)                                       \r\n#define SAI_xCR1_SAIEN_Msk         (0x1U << SAI_xCR1_SAIEN_Pos)                /*!< 0x00010000 */\r\n#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */\r\n#define SAI_xCR1_DMAEN_Pos         (17U)                                       \r\n#define SAI_xCR1_DMAEN_Msk         (0x1U << SAI_xCR1_DMAEN_Pos)                /*!< 0x00020000 */\r\n#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */\r\n#define SAI_xCR1_NODIV_Pos         (19U)                                       \r\n#define SAI_xCR1_NODIV_Msk         (0x1U << SAI_xCR1_NODIV_Pos)                /*!< 0x00080000 */\r\n#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */\r\n\r\n#define SAI_xCR1_MCKDIV_Pos        (20U)                                       \r\n#define SAI_xCR1_MCKDIV_Msk        (0xFU << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00F00000 */\r\n#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[3:0] (Master ClocK Divider)  */\r\n#define SAI_xCR1_MCKDIV_0          (0x1U << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00100000 */\r\n#define SAI_xCR1_MCKDIV_1          (0x2U << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00200000 */\r\n#define SAI_xCR1_MCKDIV_2          (0x4U << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00400000 */\r\n#define SAI_xCR1_MCKDIV_3          (0x8U << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00800000 */\r\n\r\n/*******************  Bit definition for SAI_xCR2 register  *******************/\r\n#define SAI_xCR2_FTH_Pos           (0U)                                        \r\n#define SAI_xCR2_FTH_Msk           (0x7U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000007 */\r\n#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */\r\n#define SAI_xCR2_FTH_0             (0x1U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */\r\n#define SAI_xCR2_FTH_1             (0x2U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */\r\n#define SAI_xCR2_FTH_2             (0x4U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */\r\n\r\n#define SAI_xCR2_FFLUSH_Pos        (3U)                                        \r\n#define SAI_xCR2_FFLUSH_Msk        (0x1U << SAI_xCR2_FFLUSH_Pos)               /*!< 0x00000008 */\r\n#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */\r\n#define SAI_xCR2_TRIS_Pos          (4U)                                        \r\n#define SAI_xCR2_TRIS_Msk          (0x1U << SAI_xCR2_TRIS_Pos)                 /*!< 0x00000010 */\r\n#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */\r\n#define SAI_xCR2_MUTE_Pos          (5U)                                        \r\n#define SAI_xCR2_MUTE_Msk          (0x1U << SAI_xCR2_MUTE_Pos)                 /*!< 0x00000020 */\r\n#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */\r\n#define SAI_xCR2_MUTEVAL_Pos       (6U)                                        \r\n#define SAI_xCR2_MUTEVAL_Msk       (0x1U << SAI_xCR2_MUTEVAL_Pos)              /*!< 0x00000040 */\r\n#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */\r\n\r\n#define SAI_xCR2_MUTECNT_Pos       (7U)                                        \r\n#define SAI_xCR2_MUTECNT_Msk       (0x3FU << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001F80 */\r\n#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */\r\n#define SAI_xCR2_MUTECNT_0         (0x01U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */\r\n#define SAI_xCR2_MUTECNT_1         (0x02U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */\r\n#define SAI_xCR2_MUTECNT_2         (0x04U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */\r\n#define SAI_xCR2_MUTECNT_3         (0x08U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */\r\n#define SAI_xCR2_MUTECNT_4         (0x10U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */\r\n#define SAI_xCR2_MUTECNT_5         (0x20U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */\r\n\r\n#define SAI_xCR2_CPL_Pos           (13U)                                       \r\n#define SAI_xCR2_CPL_Msk           (0x1U << SAI_xCR2_CPL_Pos)                  /*!< 0x00002000 */\r\n#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */\r\n\r\n#define SAI_xCR2_COMP_Pos          (14U)                                       \r\n#define SAI_xCR2_COMP_Msk          (0x3U << SAI_xCR2_COMP_Pos)                 /*!< 0x0000C000 */\r\n#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */\r\n#define SAI_xCR2_COMP_0            (0x1U << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */\r\n#define SAI_xCR2_COMP_1            (0x2U << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */\r\n\r\n/******************  Bit definition for SAI_xFRCR register  *******************/\r\n#define SAI_xFRCR_FRL_Pos          (0U)                                        \r\n#define SAI_xFRCR_FRL_Msk          (0xFFU << SAI_xFRCR_FRL_Pos)                /*!< 0x000000FF */\r\n#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[1:0](Frame length)  */\r\n#define SAI_xFRCR_FRL_0            (0x01U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */\r\n#define SAI_xFRCR_FRL_1            (0x02U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */\r\n#define SAI_xFRCR_FRL_2            (0x04U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */\r\n#define SAI_xFRCR_FRL_3            (0x08U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */\r\n#define SAI_xFRCR_FRL_4            (0x10U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */\r\n#define SAI_xFRCR_FRL_5            (0x20U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */\r\n#define SAI_xFRCR_FRL_6            (0x40U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */\r\n#define SAI_xFRCR_FRL_7            (0x80U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */\r\n\r\n#define SAI_xFRCR_FSALL_Pos        (8U)                                        \r\n#define SAI_xFRCR_FSALL_Msk        (0x7FU << SAI_xFRCR_FSALL_Pos)              /*!< 0x00007F00 */\r\n#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FRL[1:0] (Frame synchronization active level length)  */\r\n#define SAI_xFRCR_FSALL_0          (0x01U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */\r\n#define SAI_xFRCR_FSALL_1          (0x02U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */\r\n#define SAI_xFRCR_FSALL_2          (0x04U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */\r\n#define SAI_xFRCR_FSALL_3          (0x08U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */\r\n#define SAI_xFRCR_FSALL_4          (0x10U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */\r\n#define SAI_xFRCR_FSALL_5          (0x20U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */\r\n#define SAI_xFRCR_FSALL_6          (0x40U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */\r\n\r\n#define SAI_xFRCR_FSDEF_Pos        (16U)                                       \r\n#define SAI_xFRCR_FSDEF_Msk        (0x1U << SAI_xFRCR_FSDEF_Pos)               /*!< 0x00010000 */\r\n#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!<Frame Synchronization Definition  */\r\n#define SAI_xFRCR_FSPOL_Pos        (17U)                                       \r\n#define SAI_xFRCR_FSPOL_Msk        (0x1U << SAI_xFRCR_FSPOL_Pos)               /*!< 0x00020000 */\r\n#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */\r\n#define SAI_xFRCR_FSOFF_Pos        (18U)                                       \r\n#define SAI_xFRCR_FSOFF_Msk        (0x1U << SAI_xFRCR_FSOFF_Pos)               /*!< 0x00040000 */\r\n#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */\r\n\r\n/* Legacy define */\r\n#define  SAI_xFRCR_FSPO                      SAI_xFRCR_FSPOL\r\n\r\n/******************  Bit definition for SAI_xSLOTR register  *******************/\r\n#define SAI_xSLOTR_FBOFF_Pos       (0U)                                        \r\n#define SAI_xSLOTR_FBOFF_Msk       (0x1FU << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x0000001F */\r\n#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FRL[4:0](First Bit Offset)  */\r\n#define SAI_xSLOTR_FBOFF_0         (0x01U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */\r\n#define SAI_xSLOTR_FBOFF_1         (0x02U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */\r\n#define SAI_xSLOTR_FBOFF_2         (0x04U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */\r\n#define SAI_xSLOTR_FBOFF_3         (0x08U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */\r\n#define SAI_xSLOTR_FBOFF_4         (0x10U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */\r\n\r\n#define SAI_xSLOTR_SLOTSZ_Pos      (6U)                                        \r\n#define SAI_xSLOTR_SLOTSZ_Msk      (0x3U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x000000C0 */\r\n#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */\r\n#define SAI_xSLOTR_SLOTSZ_0        (0x1U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */\r\n#define SAI_xSLOTR_SLOTSZ_1        (0x2U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */\r\n\r\n#define SAI_xSLOTR_NBSLOT_Pos      (8U)                                        \r\n#define SAI_xSLOTR_NBSLOT_Msk      (0xFU << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000F00 */\r\n#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */\r\n#define SAI_xSLOTR_NBSLOT_0        (0x1U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */\r\n#define SAI_xSLOTR_NBSLOT_1        (0x2U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */\r\n#define SAI_xSLOTR_NBSLOT_2        (0x4U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */\r\n#define SAI_xSLOTR_NBSLOT_3        (0x8U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */\r\n\r\n#define SAI_xSLOTR_SLOTEN_Pos      (16U)                                       \r\n#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos)          /*!< 0xFFFF0000 */\r\n#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */\r\n\r\n/*******************  Bit definition for SAI_xIMR register  *******************/\r\n#define SAI_xIMR_OVRUDRIE_Pos      (0U)                                        \r\n#define SAI_xIMR_OVRUDRIE_Msk      (0x1U << SAI_xIMR_OVRUDRIE_Pos)             /*!< 0x00000001 */\r\n#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */\r\n#define SAI_xIMR_MUTEDETIE_Pos     (1U)                                        \r\n#define SAI_xIMR_MUTEDETIE_Msk     (0x1U << SAI_xIMR_MUTEDETIE_Pos)            /*!< 0x00000002 */\r\n#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */\r\n#define SAI_xIMR_WCKCFGIE_Pos      (2U)                                        \r\n#define SAI_xIMR_WCKCFGIE_Msk      (0x1U << SAI_xIMR_WCKCFGIE_Pos)             /*!< 0x00000004 */\r\n#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */\r\n#define SAI_xIMR_FREQIE_Pos        (3U)                                        \r\n#define SAI_xIMR_FREQIE_Msk        (0x1U << SAI_xIMR_FREQIE_Pos)               /*!< 0x00000008 */\r\n#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */\r\n#define SAI_xIMR_CNRDYIE_Pos       (4U)                                        \r\n#define SAI_xIMR_CNRDYIE_Msk       (0x1U << SAI_xIMR_CNRDYIE_Pos)              /*!< 0x00000010 */\r\n#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */\r\n#define SAI_xIMR_AFSDETIE_Pos      (5U)                                        \r\n#define SAI_xIMR_AFSDETIE_Msk      (0x1U << SAI_xIMR_AFSDETIE_Pos)             /*!< 0x00000020 */\r\n#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */\r\n#define SAI_xIMR_LFSDETIE_Pos      (6U)                                        \r\n#define SAI_xIMR_LFSDETIE_Msk      (0x1U << SAI_xIMR_LFSDETIE_Pos)             /*!< 0x00000040 */\r\n#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */\r\n\r\n/********************  Bit definition for SAI_xSR register  *******************/\r\n#define SAI_xSR_OVRUDR_Pos         (0U)                                        \r\n#define SAI_xSR_OVRUDR_Msk         (0x1U << SAI_xSR_OVRUDR_Pos)                /*!< 0x00000001 */\r\n#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */\r\n#define SAI_xSR_MUTEDET_Pos        (1U)                                        \r\n#define SAI_xSR_MUTEDET_Msk        (0x1U << SAI_xSR_MUTEDET_Pos)               /*!< 0x00000002 */\r\n#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */\r\n#define SAI_xSR_WCKCFG_Pos         (2U)                                        \r\n#define SAI_xSR_WCKCFG_Msk         (0x1U << SAI_xSR_WCKCFG_Pos)                /*!< 0x00000004 */\r\n#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */\r\n#define SAI_xSR_FREQ_Pos           (3U)                                        \r\n#define SAI_xSR_FREQ_Msk           (0x1U << SAI_xSR_FREQ_Pos)                  /*!< 0x00000008 */\r\n#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */\r\n#define SAI_xSR_CNRDY_Pos          (4U)                                        \r\n#define SAI_xSR_CNRDY_Msk          (0x1U << SAI_xSR_CNRDY_Pos)                 /*!< 0x00000010 */\r\n#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */\r\n#define SAI_xSR_AFSDET_Pos         (5U)                                        \r\n#define SAI_xSR_AFSDET_Msk         (0x1U << SAI_xSR_AFSDET_Pos)                /*!< 0x00000020 */\r\n#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */\r\n#define SAI_xSR_LFSDET_Pos         (6U)                                        \r\n#define SAI_xSR_LFSDET_Msk         (0x1U << SAI_xSR_LFSDET_Pos)                /*!< 0x00000040 */\r\n#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */\r\n\r\n#define SAI_xSR_FLVL_Pos           (16U)                                       \r\n#define SAI_xSR_FLVL_Msk           (0x7U << SAI_xSR_FLVL_Pos)                  /*!< 0x00070000 */\r\n#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */\r\n#define SAI_xSR_FLVL_0             (0x1U << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */\r\n#define SAI_xSR_FLVL_1             (0x2U << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */\r\n#define SAI_xSR_FLVL_2             (0x4U << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */\r\n\r\n/******************  Bit definition for SAI_xCLRFR register  ******************/\r\n#define SAI_xCLRFR_COVRUDR_Pos     (0U)                                        \r\n#define SAI_xCLRFR_COVRUDR_Msk     (0x1U << SAI_xCLRFR_COVRUDR_Pos)            /*!< 0x00000001 */\r\n#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */\r\n#define SAI_xCLRFR_CMUTEDET_Pos    (1U)                                        \r\n#define SAI_xCLRFR_CMUTEDET_Msk    (0x1U << SAI_xCLRFR_CMUTEDET_Pos)           /*!< 0x00000002 */\r\n#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */\r\n#define SAI_xCLRFR_CWCKCFG_Pos     (2U)                                        \r\n#define SAI_xCLRFR_CWCKCFG_Msk     (0x1U << SAI_xCLRFR_CWCKCFG_Pos)            /*!< 0x00000004 */\r\n#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */\r\n#define SAI_xCLRFR_CFREQ_Pos       (3U)                                        \r\n#define SAI_xCLRFR_CFREQ_Msk       (0x1U << SAI_xCLRFR_CFREQ_Pos)              /*!< 0x00000008 */\r\n#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */\r\n#define SAI_xCLRFR_CCNRDY_Pos      (4U)                                        \r\n#define SAI_xCLRFR_CCNRDY_Msk      (0x1U << SAI_xCLRFR_CCNRDY_Pos)             /*!< 0x00000010 */\r\n#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */\r\n#define SAI_xCLRFR_CAFSDET_Pos     (5U)                                        \r\n#define SAI_xCLRFR_CAFSDET_Msk     (0x1U << SAI_xCLRFR_CAFSDET_Pos)            /*!< 0x00000020 */\r\n#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */\r\n#define SAI_xCLRFR_CLFSDET_Pos     (6U)                                        \r\n#define SAI_xCLRFR_CLFSDET_Msk     (0x1U << SAI_xCLRFR_CLFSDET_Pos)            /*!< 0x00000040 */\r\n#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */\r\n\r\n/******************  Bit definition for SAI_xDR register  *********************/\r\n#define SAI_xDR_DATA_Pos           (0U)                                        \r\n#define SAI_xDR_DATA_Msk           (0xFFFFFFFFU << SAI_xDR_DATA_Pos)           /*!< 0xFFFFFFFF */\r\n#define SAI_xDR_DATA               SAI_xDR_DATA_Msk                            \r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                              SPDIF-RX Interface                            */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bit definition for SPDIF_CR register  *******************/\r\n#define SPDIFRX_CR_SPDIFEN_Pos      (0U)                                       \r\n#define SPDIFRX_CR_SPDIFEN_Msk      (0x3U << SPDIFRX_CR_SPDIFEN_Pos)           /*!< 0x00000003 */\r\n#define SPDIFRX_CR_SPDIFEN          SPDIFRX_CR_SPDIFEN_Msk                     /*!<Peripheral Block Enable                      */\r\n#define SPDIFRX_CR_RXDMAEN_Pos      (2U)                                       \r\n#define SPDIFRX_CR_RXDMAEN_Msk      (0x1U << SPDIFRX_CR_RXDMAEN_Pos)           /*!< 0x00000004 */\r\n#define SPDIFRX_CR_RXDMAEN          SPDIFRX_CR_RXDMAEN_Msk                     /*!<Receiver DMA Enable for data flow            */\r\n#define SPDIFRX_CR_RXSTEO_Pos       (3U)                                       \r\n#define SPDIFRX_CR_RXSTEO_Msk       (0x1U << SPDIFRX_CR_RXSTEO_Pos)            /*!< 0x00000008 */\r\n#define SPDIFRX_CR_RXSTEO           SPDIFRX_CR_RXSTEO_Msk                      /*!<Stereo Mode                                  */\r\n#define SPDIFRX_CR_DRFMT_Pos        (4U)                                       \r\n#define SPDIFRX_CR_DRFMT_Msk        (0x3U << SPDIFRX_CR_DRFMT_Pos)             /*!< 0x00000030 */\r\n#define SPDIFRX_CR_DRFMT            SPDIFRX_CR_DRFMT_Msk                       /*!<RX Data format                               */\r\n#define SPDIFRX_CR_PMSK_Pos         (6U)                                       \r\n#define SPDIFRX_CR_PMSK_Msk         (0x1U << SPDIFRX_CR_PMSK_Pos)              /*!< 0x00000040 */\r\n#define SPDIFRX_CR_PMSK             SPDIFRX_CR_PMSK_Msk                        /*!<Mask Parity error bit                        */\r\n#define SPDIFRX_CR_VMSK_Pos         (7U)                                       \r\n#define SPDIFRX_CR_VMSK_Msk         (0x1U << SPDIFRX_CR_VMSK_Pos)              /*!< 0x00000080 */\r\n#define SPDIFRX_CR_VMSK             SPDIFRX_CR_VMSK_Msk                        /*!<Mask of Validity bit                         */\r\n#define SPDIFRX_CR_CUMSK_Pos        (8U)                                       \r\n#define SPDIFRX_CR_CUMSK_Msk        (0x1U << SPDIFRX_CR_CUMSK_Pos)             /*!< 0x00000100 */\r\n#define SPDIFRX_CR_CUMSK            SPDIFRX_CR_CUMSK_Msk                       /*!<Mask of channel status and user bits         */\r\n#define SPDIFRX_CR_PTMSK_Pos        (9U)                                       \r\n#define SPDIFRX_CR_PTMSK_Msk        (0x1U << SPDIFRX_CR_PTMSK_Pos)             /*!< 0x00000200 */\r\n#define SPDIFRX_CR_PTMSK            SPDIFRX_CR_PTMSK_Msk                       /*!<Mask of Preamble Type bits                   */\r\n#define SPDIFRX_CR_CBDMAEN_Pos      (10U)                                      \r\n#define SPDIFRX_CR_CBDMAEN_Msk      (0x1U << SPDIFRX_CR_CBDMAEN_Pos)           /*!< 0x00000400 */\r\n#define SPDIFRX_CR_CBDMAEN          SPDIFRX_CR_CBDMAEN_Msk                     /*!<Control Buffer DMA ENable for control flow   */\r\n#define SPDIFRX_CR_CHSEL_Pos        (11U)                                      \r\n#define SPDIFRX_CR_CHSEL_Msk        (0x1U << SPDIFRX_CR_CHSEL_Pos)             /*!< 0x00000800 */\r\n#define SPDIFRX_CR_CHSEL            SPDIFRX_CR_CHSEL_Msk                       /*!<Channel Selection                            */\r\n#define SPDIFRX_CR_NBTR_Pos         (12U)                                      \r\n#define SPDIFRX_CR_NBTR_Msk         (0x3U << SPDIFRX_CR_NBTR_Pos)              /*!< 0x00003000 */\r\n#define SPDIFRX_CR_NBTR             SPDIFRX_CR_NBTR_Msk                        /*!<Maximum allowed re-tries during synchronization phase */\r\n#define SPDIFRX_CR_WFA_Pos          (14U)                                      \r\n#define SPDIFRX_CR_WFA_Msk          (0x1U << SPDIFRX_CR_WFA_Pos)               /*!< 0x00004000 */\r\n#define SPDIFRX_CR_WFA              SPDIFRX_CR_WFA_Msk                         /*!<Wait For Activity     */\r\n#define SPDIFRX_CR_INSEL_Pos        (16U)                                      \r\n#define SPDIFRX_CR_INSEL_Msk        (0x7U << SPDIFRX_CR_INSEL_Pos)             /*!< 0x00070000 */\r\n#define SPDIFRX_CR_INSEL            SPDIFRX_CR_INSEL_Msk                       /*!<SPDIF input selection */\r\n\r\n/*******************  Bit definition for SPDIFRX_IMR register  *******************/\r\n#define SPDIFRX_IMR_RXNEIE_Pos      (0U)                                       \r\n#define SPDIFRX_IMR_RXNEIE_Msk      (0x1U << SPDIFRX_IMR_RXNEIE_Pos)           /*!< 0x00000001 */\r\n#define SPDIFRX_IMR_RXNEIE          SPDIFRX_IMR_RXNEIE_Msk                     /*!<RXNE interrupt enable                              */\r\n#define SPDIFRX_IMR_CSRNEIE_Pos     (1U)                                       \r\n#define SPDIFRX_IMR_CSRNEIE_Msk     (0x1U << SPDIFRX_IMR_CSRNEIE_Pos)          /*!< 0x00000002 */\r\n#define SPDIFRX_IMR_CSRNEIE         SPDIFRX_IMR_CSRNEIE_Msk                    /*!<Control Buffer Ready Interrupt Enable              */\r\n#define SPDIFRX_IMR_PERRIE_Pos      (2U)                                       \r\n#define SPDIFRX_IMR_PERRIE_Msk      (0x1U << SPDIFRX_IMR_PERRIE_Pos)           /*!< 0x00000004 */\r\n#define SPDIFRX_IMR_PERRIE          SPDIFRX_IMR_PERRIE_Msk                     /*!<Parity error interrupt enable                      */\r\n#define SPDIFRX_IMR_OVRIE_Pos       (3U)                                       \r\n#define SPDIFRX_IMR_OVRIE_Msk       (0x1U << SPDIFRX_IMR_OVRIE_Pos)            /*!< 0x00000008 */\r\n#define SPDIFRX_IMR_OVRIE           SPDIFRX_IMR_OVRIE_Msk                      /*!<Overrun error Interrupt Enable                     */\r\n#define SPDIFRX_IMR_SBLKIE_Pos      (4U)                                       \r\n#define SPDIFRX_IMR_SBLKIE_Msk      (0x1U << SPDIFRX_IMR_SBLKIE_Pos)           /*!< 0x00000010 */\r\n#define SPDIFRX_IMR_SBLKIE          SPDIFRX_IMR_SBLKIE_Msk                     /*!<Synchronization Block Detected Interrupt Enable    */\r\n#define SPDIFRX_IMR_SYNCDIE_Pos     (5U)                                       \r\n#define SPDIFRX_IMR_SYNCDIE_Msk     (0x1U << SPDIFRX_IMR_SYNCDIE_Pos)          /*!< 0x00000020 */\r\n#define SPDIFRX_IMR_SYNCDIE         SPDIFRX_IMR_SYNCDIE_Msk                    /*!<Synchronization Done                               */\r\n#define SPDIFRX_IMR_IFEIE_Pos       (6U)                                       \r\n#define SPDIFRX_IMR_IFEIE_Msk       (0x1U << SPDIFRX_IMR_IFEIE_Pos)            /*!< 0x00000040 */\r\n#define SPDIFRX_IMR_IFEIE           SPDIFRX_IMR_IFEIE_Msk                      /*!<Serial Interface Error Interrupt Enable            */\r\n\r\n/*******************  Bit definition for SPDIFRX_SR register  *******************/\r\n#define SPDIFRX_SR_RXNE_Pos         (0U)                                       \r\n#define SPDIFRX_SR_RXNE_Msk         (0x1U << SPDIFRX_SR_RXNE_Pos)              /*!< 0x00000001 */\r\n#define SPDIFRX_SR_RXNE             SPDIFRX_SR_RXNE_Msk                        /*!<Read data register not empty                          */\r\n#define SPDIFRX_SR_CSRNE_Pos        (1U)                                       \r\n#define SPDIFRX_SR_CSRNE_Msk        (0x1U << SPDIFRX_SR_CSRNE_Pos)             /*!< 0x00000002 */\r\n#define SPDIFRX_SR_CSRNE            SPDIFRX_SR_CSRNE_Msk                       /*!<The Control Buffer register is not empty              */\r\n#define SPDIFRX_SR_PERR_Pos         (2U)                                       \r\n#define SPDIFRX_SR_PERR_Msk         (0x1U << SPDIFRX_SR_PERR_Pos)              /*!< 0x00000004 */\r\n#define SPDIFRX_SR_PERR             SPDIFRX_SR_PERR_Msk                        /*!<Parity error                                          */\r\n#define SPDIFRX_SR_OVR_Pos          (3U)                                       \r\n#define SPDIFRX_SR_OVR_Msk          (0x1U << SPDIFRX_SR_OVR_Pos)               /*!< 0x00000008 */\r\n#define SPDIFRX_SR_OVR              SPDIFRX_SR_OVR_Msk                         /*!<Overrun error                                         */\r\n#define SPDIFRX_SR_SBD_Pos          (4U)                                       \r\n#define SPDIFRX_SR_SBD_Msk          (0x1U << SPDIFRX_SR_SBD_Pos)               /*!< 0x00000010 */\r\n#define SPDIFRX_SR_SBD              SPDIFRX_SR_SBD_Msk                         /*!<Synchronization Block Detected                        */\r\n#define SPDIFRX_SR_SYNCD_Pos        (5U)                                       \r\n#define SPDIFRX_SR_SYNCD_Msk        (0x1U << SPDIFRX_SR_SYNCD_Pos)             /*!< 0x00000020 */\r\n#define SPDIFRX_SR_SYNCD            SPDIFRX_SR_SYNCD_Msk                       /*!<Synchronization Done                                  */\r\n#define SPDIFRX_SR_FERR_Pos         (6U)                                       \r\n#define SPDIFRX_SR_FERR_Msk         (0x1U << SPDIFRX_SR_FERR_Pos)              /*!< 0x00000040 */\r\n#define SPDIFRX_SR_FERR             SPDIFRX_SR_FERR_Msk                        /*!<Framing error                                         */\r\n#define SPDIFRX_SR_SERR_Pos         (7U)                                       \r\n#define SPDIFRX_SR_SERR_Msk         (0x1U << SPDIFRX_SR_SERR_Pos)              /*!< 0x00000080 */\r\n#define SPDIFRX_SR_SERR             SPDIFRX_SR_SERR_Msk                        /*!<Synchronization error                                 */\r\n#define SPDIFRX_SR_TERR_Pos         (8U)                                       \r\n#define SPDIFRX_SR_TERR_Msk         (0x1U << SPDIFRX_SR_TERR_Pos)              /*!< 0x00000100 */\r\n#define SPDIFRX_SR_TERR             SPDIFRX_SR_TERR_Msk                        /*!<Time-out error                                        */\r\n#define SPDIFRX_SR_WIDTH5_Pos       (16U)                                      \r\n#define SPDIFRX_SR_WIDTH5_Msk       (0x7FFFU << SPDIFRX_SR_WIDTH5_Pos)         /*!< 0x7FFF0000 */\r\n#define SPDIFRX_SR_WIDTH5           SPDIFRX_SR_WIDTH5_Msk                      /*!<Duration of 5 symbols counted with spdif_clk          */\r\n\r\n/*******************  Bit definition for SPDIFRX_IFCR register  *******************/\r\n#define SPDIFRX_IFCR_PERRCF_Pos     (2U)                                       \r\n#define SPDIFRX_IFCR_PERRCF_Msk     (0x1U << SPDIFRX_IFCR_PERRCF_Pos)          /*!< 0x00000004 */\r\n#define SPDIFRX_IFCR_PERRCF         SPDIFRX_IFCR_PERRCF_Msk                    /*!<Clears the Parity error flag                         */\r\n#define SPDIFRX_IFCR_OVRCF_Pos      (3U)                                       \r\n#define SPDIFRX_IFCR_OVRCF_Msk      (0x1U << SPDIFRX_IFCR_OVRCF_Pos)           /*!< 0x00000008 */\r\n#define SPDIFRX_IFCR_OVRCF          SPDIFRX_IFCR_OVRCF_Msk                     /*!<Clears the Overrun error flag                        */\r\n#define SPDIFRX_IFCR_SBDCF_Pos      (4U)                                       \r\n#define SPDIFRX_IFCR_SBDCF_Msk      (0x1U << SPDIFRX_IFCR_SBDCF_Pos)           /*!< 0x00000010 */\r\n#define SPDIFRX_IFCR_SBDCF          SPDIFRX_IFCR_SBDCF_Msk                     /*!<Clears the Synchronization Block Detected flag       */\r\n#define SPDIFRX_IFCR_SYNCDCF_Pos    (5U)                                       \r\n#define SPDIFRX_IFCR_SYNCDCF_Msk    (0x1U << SPDIFRX_IFCR_SYNCDCF_Pos)         /*!< 0x00000020 */\r\n#define SPDIFRX_IFCR_SYNCDCF        SPDIFRX_IFCR_SYNCDCF_Msk                   /*!<Clears the Synchronization Done flag                 */\r\n\r\n/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/\r\n#define SPDIFRX_DR0_DR_Pos          (0U)                                       \r\n#define SPDIFRX_DR0_DR_Msk          (0xFFFFFFU << SPDIFRX_DR0_DR_Pos)          /*!< 0x00FFFFFF */\r\n#define SPDIFRX_DR0_DR              SPDIFRX_DR0_DR_Msk                         /*!<Data value            */\r\n#define SPDIFRX_DR0_PE_Pos          (24U)                                      \r\n#define SPDIFRX_DR0_PE_Msk          (0x1U << SPDIFRX_DR0_PE_Pos)               /*!< 0x01000000 */\r\n#define SPDIFRX_DR0_PE              SPDIFRX_DR0_PE_Msk                         /*!<Parity Error bit      */\r\n#define SPDIFRX_DR0_V_Pos           (25U)                                      \r\n#define SPDIFRX_DR0_V_Msk           (0x1U << SPDIFRX_DR0_V_Pos)                /*!< 0x02000000 */\r\n#define SPDIFRX_DR0_V               SPDIFRX_DR0_V_Msk                          /*!<Validity bit          */\r\n#define SPDIFRX_DR0_U_Pos           (26U)                                      \r\n#define SPDIFRX_DR0_U_Msk           (0x1U << SPDIFRX_DR0_U_Pos)                /*!< 0x04000000 */\r\n#define SPDIFRX_DR0_U               SPDIFRX_DR0_U_Msk                          /*!<User bit              */\r\n#define SPDIFRX_DR0_C_Pos           (27U)                                      \r\n#define SPDIFRX_DR0_C_Msk           (0x1U << SPDIFRX_DR0_C_Pos)                /*!< 0x08000000 */\r\n#define SPDIFRX_DR0_C               SPDIFRX_DR0_C_Msk                          /*!<Channel Status bit    */\r\n#define SPDIFRX_DR0_PT_Pos          (28U)                                      \r\n#define SPDIFRX_DR0_PT_Msk          (0x3U << SPDIFRX_DR0_PT_Pos)               /*!< 0x30000000 */\r\n#define SPDIFRX_DR0_PT              SPDIFRX_DR0_PT_Msk                         /*!<Preamble Type         */\r\n\r\n/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/\r\n#define SPDIFRX_DR1_DR_Pos          (8U)                                       \r\n#define SPDIFRX_DR1_DR_Msk          (0xFFFFFFU << SPDIFRX_DR1_DR_Pos)          /*!< 0xFFFFFF00 */\r\n#define SPDIFRX_DR1_DR              SPDIFRX_DR1_DR_Msk                         /*!<Data value            */\r\n#define SPDIFRX_DR1_PT_Pos          (4U)                                       \r\n#define SPDIFRX_DR1_PT_Msk          (0x3U << SPDIFRX_DR1_PT_Pos)               /*!< 0x00000030 */\r\n#define SPDIFRX_DR1_PT              SPDIFRX_DR1_PT_Msk                         /*!<Preamble Type         */\r\n#define SPDIFRX_DR1_C_Pos           (3U)                                       \r\n#define SPDIFRX_DR1_C_Msk           (0x1U << SPDIFRX_DR1_C_Pos)                /*!< 0x00000008 */\r\n#define SPDIFRX_DR1_C               SPDIFRX_DR1_C_Msk                          /*!<Channel Status bit    */\r\n#define SPDIFRX_DR1_U_Pos           (2U)                                       \r\n#define SPDIFRX_DR1_U_Msk           (0x1U << SPDIFRX_DR1_U_Pos)                /*!< 0x00000004 */\r\n#define SPDIFRX_DR1_U               SPDIFRX_DR1_U_Msk                          /*!<User bit              */\r\n#define SPDIFRX_DR1_V_Pos           (1U)                                       \r\n#define SPDIFRX_DR1_V_Msk           (0x1U << SPDIFRX_DR1_V_Pos)                /*!< 0x00000002 */\r\n#define SPDIFRX_DR1_V               SPDIFRX_DR1_V_Msk                          /*!<Validity bit          */\r\n#define SPDIFRX_DR1_PE_Pos          (0U)                                       \r\n#define SPDIFRX_DR1_PE_Msk          (0x1U << SPDIFRX_DR1_PE_Pos)               /*!< 0x00000001 */\r\n#define SPDIFRX_DR1_PE              SPDIFRX_DR1_PE_Msk                         /*!<Parity Error bit      */\r\n\r\n/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/\r\n#define SPDIFRX_DR1_DRNL1_Pos       (16U)                                      \r\n#define SPDIFRX_DR1_DRNL1_Msk       (0xFFFFU << SPDIFRX_DR1_DRNL1_Pos)         /*!< 0xFFFF0000 */\r\n#define SPDIFRX_DR1_DRNL1           SPDIFRX_DR1_DRNL1_Msk                      /*!<Data value Channel B      */\r\n#define SPDIFRX_DR1_DRNL2_Pos       (0U)                                       \r\n#define SPDIFRX_DR1_DRNL2_Msk       (0xFFFFU << SPDIFRX_DR1_DRNL2_Pos)         /*!< 0x0000FFFF */\r\n#define SPDIFRX_DR1_DRNL2           SPDIFRX_DR1_DRNL2_Msk                      /*!<Data value Channel A      */\r\n\r\n/*******************  Bit definition for SPDIFRX_CSR register   *******************/\r\n#define SPDIFRX_CSR_USR_Pos         (0U)                                       \r\n#define SPDIFRX_CSR_USR_Msk         (0xFFFFU << SPDIFRX_CSR_USR_Pos)           /*!< 0x0000FFFF */\r\n#define SPDIFRX_CSR_USR             SPDIFRX_CSR_USR_Msk                        /*!<User data information           */\r\n#define SPDIFRX_CSR_CS_Pos          (16U)                                      \r\n#define SPDIFRX_CSR_CS_Msk          (0xFFU << SPDIFRX_CSR_CS_Pos)              /*!< 0x00FF0000 */\r\n#define SPDIFRX_CSR_CS              SPDIFRX_CSR_CS_Msk                         /*!<Channel A status information    */\r\n#define SPDIFRX_CSR_SOB_Pos         (24U)                                      \r\n#define SPDIFRX_CSR_SOB_Msk         (0x1U << SPDIFRX_CSR_SOB_Pos)              /*!< 0x01000000 */\r\n#define SPDIFRX_CSR_SOB             SPDIFRX_CSR_SOB_Msk                        /*!<Start Of Block                  */\r\n\r\n/*******************  Bit definition for SPDIFRX_DIR register    *******************/\r\n#define SPDIFRX_DIR_THI_Pos         (0U)                                       \r\n#define SPDIFRX_DIR_THI_Msk         (0x13FFU << SPDIFRX_DIR_THI_Pos)           /*!< 0x000013FF */\r\n#define SPDIFRX_DIR_THI             SPDIFRX_DIR_THI_Msk                        /*!<Threshold LOW      */\r\n#define SPDIFRX_DIR_TLO_Pos         (16U)                                      \r\n#define SPDIFRX_DIR_TLO_Msk         (0x1FFFU << SPDIFRX_DIR_TLO_Pos)           /*!< 0x1FFF0000 */\r\n#define SPDIFRX_DIR_TLO             SPDIFRX_DIR_TLO_Msk                        /*!<Threshold HIGH     */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                          SD host Interface                                 */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/******************  Bit definition for SDMMC_POWER register  ******************/\r\n#define SDMMC_POWER_PWRCTRL_Pos         (0U)                                   \r\n#define SDMMC_POWER_PWRCTRL_Msk         (0x3U << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000003 */\r\n#define SDMMC_POWER_PWRCTRL             SDMMC_POWER_PWRCTRL_Msk                /*!<PWRCTRL[1:0] bits (Power supply control bits) */\r\n#define SDMMC_POWER_PWRCTRL_0           (0x1U << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x01 */\r\n#define SDMMC_POWER_PWRCTRL_1           (0x2U << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x02 */\r\n\r\n/******************  Bit definition for SDMMC_CLKCR register  ******************/\r\n#define SDMMC_CLKCR_CLKDIV_Pos          (0U)                                   \r\n#define SDMMC_CLKCR_CLKDIV_Msk          (0xFFU << SDMMC_CLKCR_CLKDIV_Pos)      /*!< 0x000000FF */\r\n#define SDMMC_CLKCR_CLKDIV              SDMMC_CLKCR_CLKDIV_Msk                 /*!<Clock divide factor             */\r\n#define SDMMC_CLKCR_CLKEN_Pos           (8U)                                   \r\n#define SDMMC_CLKCR_CLKEN_Msk           (0x1U << SDMMC_CLKCR_CLKEN_Pos)        /*!< 0x00000100 */\r\n#define SDMMC_CLKCR_CLKEN               SDMMC_CLKCR_CLKEN_Msk                  /*!<Clock enable bit                */\r\n#define SDMMC_CLKCR_PWRSAV_Pos          (9U)                                   \r\n#define SDMMC_CLKCR_PWRSAV_Msk          (0x1U << SDMMC_CLKCR_PWRSAV_Pos)       /*!< 0x00000200 */\r\n#define SDMMC_CLKCR_PWRSAV              SDMMC_CLKCR_PWRSAV_Msk                 /*!<Power saving configuration bit  */\r\n#define SDMMC_CLKCR_BYPASS_Pos          (10U)                                  \r\n#define SDMMC_CLKCR_BYPASS_Msk          (0x1U << SDMMC_CLKCR_BYPASS_Pos)       /*!< 0x00000400 */\r\n#define SDMMC_CLKCR_BYPASS              SDMMC_CLKCR_BYPASS_Msk                 /*!<Clock divider bypass enable bit */\r\n\r\n#define SDMMC_CLKCR_WIDBUS_Pos          (11U)                                  \r\n#define SDMMC_CLKCR_WIDBUS_Msk          (0x3U << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00001800 */\r\n#define SDMMC_CLKCR_WIDBUS              SDMMC_CLKCR_WIDBUS_Msk                 /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */\r\n#define SDMMC_CLKCR_WIDBUS_0            (0x1U << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x0800 */\r\n#define SDMMC_CLKCR_WIDBUS_1            (0x2U << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x1000 */\r\n\r\n#define SDMMC_CLKCR_NEGEDGE_Pos         (13U)                                  \r\n#define SDMMC_CLKCR_NEGEDGE_Msk         (0x1U << SDMMC_CLKCR_NEGEDGE_Pos)      /*!< 0x00002000 */\r\n#define SDMMC_CLKCR_NEGEDGE             SDMMC_CLKCR_NEGEDGE_Msk                /*!<SDMMC_CK dephasing selection bit */\r\n#define SDMMC_CLKCR_HWFC_EN_Pos         (14U)                                  \r\n#define SDMMC_CLKCR_HWFC_EN_Msk         (0x1U << SDMMC_CLKCR_HWFC_EN_Pos)      /*!< 0x00004000 */\r\n#define SDMMC_CLKCR_HWFC_EN             SDMMC_CLKCR_HWFC_EN_Msk                /*!<HW Flow Control enable          */\r\n\r\n/*******************  Bit definition for SDMMC_ARG register  *******************/\r\n#define SDMMC_ARG_CMDARG_Pos            (0U)                                   \r\n#define SDMMC_ARG_CMDARG_Msk            (0xFFFFFFFFU << SDMMC_ARG_CMDARG_Pos)  /*!< 0xFFFFFFFF */\r\n#define SDMMC_ARG_CMDARG                SDMMC_ARG_CMDARG_Msk                   /*!<Command argument */\r\n\r\n/*******************  Bit definition for SDMMC_CMD register  *******************/\r\n#define SDMMC_CMD_CMDINDEX_Pos          (0U)                                   \r\n#define SDMMC_CMD_CMDINDEX_Msk          (0x3FU << SDMMC_CMD_CMDINDEX_Pos)      /*!< 0x0000003F */\r\n#define SDMMC_CMD_CMDINDEX              SDMMC_CMD_CMDINDEX_Msk                 /*!<Command Index                               */\r\n\r\n#define SDMMC_CMD_WAITRESP_Pos          (6U)                                   \r\n#define SDMMC_CMD_WAITRESP_Msk          (0x3U << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x000000C0 */\r\n#define SDMMC_CMD_WAITRESP              SDMMC_CMD_WAITRESP_Msk                 /*!<WAITRESP[1:0] bits (Wait for response bits) */\r\n#define SDMMC_CMD_WAITRESP_0            (0x1U << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x0040 */\r\n#define SDMMC_CMD_WAITRESP_1            (0x2U << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x0080 */\r\n\r\n#define SDMMC_CMD_WAITINT_Pos           (8U)                                   \r\n#define SDMMC_CMD_WAITINT_Msk           (0x1U << SDMMC_CMD_WAITINT_Pos)        /*!< 0x00000100 */\r\n#define SDMMC_CMD_WAITINT               SDMMC_CMD_WAITINT_Msk                  /*!<CPSM Waits for Interrupt Request                               */\r\n#define SDMMC_CMD_WAITPEND_Pos          (9U)                                   \r\n#define SDMMC_CMD_WAITPEND_Msk          (0x1U << SDMMC_CMD_WAITPEND_Pos)       /*!< 0x00000200 */\r\n#define SDMMC_CMD_WAITPEND              SDMMC_CMD_WAITPEND_Msk                 /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */\r\n#define SDMMC_CMD_CPSMEN_Pos            (10U)                                  \r\n#define SDMMC_CMD_CPSMEN_Msk            (0x1U << SDMMC_CMD_CPSMEN_Pos)         /*!< 0x00000400 */\r\n#define SDMMC_CMD_CPSMEN                SDMMC_CMD_CPSMEN_Msk                   /*!<Command path state machine (CPSM) Enable bit                   */\r\n#define SDMMC_CMD_SDIOSUSPEND_Pos       (11U)                                  \r\n#define SDMMC_CMD_SDIOSUSPEND_Msk       (0x1U << SDMMC_CMD_SDIOSUSPEND_Pos)    /*!< 0x00000800 */\r\n#define SDMMC_CMD_SDIOSUSPEND           SDMMC_CMD_SDIOSUSPEND_Msk              /*!<SD I/O suspend command                                         */\r\n\r\n/*****************  Bit definition for SDMMC_RESPCMD register  *****************/\r\n#define SDMMC_RESPCMD_RESPCMD_Pos       (0U)                                   \r\n#define SDMMC_RESPCMD_RESPCMD_Msk       (0x3FU << SDMMC_RESPCMD_RESPCMD_Pos)   /*!< 0x0000003F */\r\n#define SDMMC_RESPCMD_RESPCMD           SDMMC_RESPCMD_RESPCMD_Msk              /*!<Response command index */\r\n\r\n/******************  Bit definition for SDMMC_RESP0 register  ******************/\r\n#define SDMMC_RESP0_CARDSTATUS0_Pos     (0U)                                   \r\n#define SDMMC_RESP0_CARDSTATUS0_Msk     (0xFFFFFFFFU << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */\r\n#define SDMMC_RESP0_CARDSTATUS0         SDMMC_RESP0_CARDSTATUS0_Msk            /*!<Card Status */\r\n\r\n/******************  Bit definition for SDMMC_RESP1 register  ******************/\r\n#define SDMMC_RESP1_CARDSTATUS1_Pos     (0U)                                   \r\n#define SDMMC_RESP1_CARDSTATUS1_Msk     (0xFFFFFFFFU << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */\r\n#define SDMMC_RESP1_CARDSTATUS1         SDMMC_RESP1_CARDSTATUS1_Msk            /*!<Card Status */\r\n\r\n/******************  Bit definition for SDMMC_RESP2 register  ******************/\r\n#define SDMMC_RESP2_CARDSTATUS2_Pos     (0U)                                   \r\n#define SDMMC_RESP2_CARDSTATUS2_Msk     (0xFFFFFFFFU << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */\r\n#define SDMMC_RESP2_CARDSTATUS2         SDMMC_RESP2_CARDSTATUS2_Msk            /*!<Card Status */\r\n\r\n/******************  Bit definition for SDMMC_RESP3 register  ******************/\r\n#define SDMMC_RESP3_CARDSTATUS3_Pos     (0U)                                   \r\n#define SDMMC_RESP3_CARDSTATUS3_Msk     (0xFFFFFFFFU << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */\r\n#define SDMMC_RESP3_CARDSTATUS3         SDMMC_RESP3_CARDSTATUS3_Msk            /*!<Card Status */\r\n\r\n/******************  Bit definition for SDMMC_RESP4 register  ******************/\r\n#define SDMMC_RESP4_CARDSTATUS4_Pos     (0U)                                   \r\n#define SDMMC_RESP4_CARDSTATUS4_Msk     (0xFFFFFFFFU << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */\r\n#define SDMMC_RESP4_CARDSTATUS4         SDMMC_RESP4_CARDSTATUS4_Msk            /*!<Card Status */\r\n\r\n/******************  Bit definition for SDMMC_DTIMER register  *****************/\r\n#define SDMMC_DTIMER_DATATIME_Pos       (0U)                                   \r\n#define SDMMC_DTIMER_DATATIME_Msk       (0xFFFFFFFFU << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */\r\n#define SDMMC_DTIMER_DATATIME           SDMMC_DTIMER_DATATIME_Msk              /*!<Data timeout period. */\r\n\r\n/******************  Bit definition for SDMMC_DLEN register  *******************/\r\n#define SDMMC_DLEN_DATALENGTH_Pos       (0U)                                   \r\n#define SDMMC_DLEN_DATALENGTH_Msk       (0x1FFFFFFU << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */\r\n#define SDMMC_DLEN_DATALENGTH           SDMMC_DLEN_DATALENGTH_Msk              /*!<Data length value    */\r\n\r\n/******************  Bit definition for SDMMC_DCTRL register  ******************/\r\n#define SDMMC_DCTRL_DTEN_Pos            (0U)                                   \r\n#define SDMMC_DCTRL_DTEN_Msk            (0x1U << SDMMC_DCTRL_DTEN_Pos)         /*!< 0x00000001 */\r\n#define SDMMC_DCTRL_DTEN                SDMMC_DCTRL_DTEN_Msk                   /*!<Data transfer enabled bit         */\r\n#define SDMMC_DCTRL_DTDIR_Pos           (1U)                                   \r\n#define SDMMC_DCTRL_DTDIR_Msk           (0x1U << SDMMC_DCTRL_DTDIR_Pos)        /*!< 0x00000002 */\r\n#define SDMMC_DCTRL_DTDIR               SDMMC_DCTRL_DTDIR_Msk                  /*!<Data transfer direction selection */\r\n#define SDMMC_DCTRL_DTMODE_Pos          (2U)                                   \r\n#define SDMMC_DCTRL_DTMODE_Msk          (0x1U << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x00000004 */\r\n#define SDMMC_DCTRL_DTMODE              SDMMC_DCTRL_DTMODE_Msk                 /*!<Data transfer mode selection      */\r\n#define SDMMC_DCTRL_DMAEN_Pos           (3U)                                   \r\n#define SDMMC_DCTRL_DMAEN_Msk           (0x1U << SDMMC_DCTRL_DMAEN_Pos)        /*!< 0x00000008 */\r\n#define SDMMC_DCTRL_DMAEN               SDMMC_DCTRL_DMAEN_Msk                  /*!<DMA enabled bit                   */\r\n\r\n#define SDMMC_DCTRL_DBLOCKSIZE_Pos      (4U)                                   \r\n#define SDMMC_DCTRL_DBLOCKSIZE_Msk      (0xFU << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x000000F0 */\r\n#define SDMMC_DCTRL_DBLOCKSIZE          SDMMC_DCTRL_DBLOCKSIZE_Msk             /*!<DBLOCKSIZE[3:0] bits (Data block size) */\r\n#define SDMMC_DCTRL_DBLOCKSIZE_0        (0x1U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x0010 */\r\n#define SDMMC_DCTRL_DBLOCKSIZE_1        (0x2U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x0020 */\r\n#define SDMMC_DCTRL_DBLOCKSIZE_2        (0x4U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x0040 */\r\n#define SDMMC_DCTRL_DBLOCKSIZE_3        (0x8U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x0080 */\r\n\r\n#define SDMMC_DCTRL_RWSTART_Pos         (8U)                                   \r\n#define SDMMC_DCTRL_RWSTART_Msk         (0x1U << SDMMC_DCTRL_RWSTART_Pos)      /*!< 0x00000100 */\r\n#define SDMMC_DCTRL_RWSTART             SDMMC_DCTRL_RWSTART_Msk                /*!<Read wait start         */\r\n#define SDMMC_DCTRL_RWSTOP_Pos          (9U)                                   \r\n#define SDMMC_DCTRL_RWSTOP_Msk          (0x1U << SDMMC_DCTRL_RWSTOP_Pos)       /*!< 0x00000200 */\r\n#define SDMMC_DCTRL_RWSTOP              SDMMC_DCTRL_RWSTOP_Msk                 /*!<Read wait stop          */\r\n#define SDMMC_DCTRL_RWMOD_Pos           (10U)                                  \r\n#define SDMMC_DCTRL_RWMOD_Msk           (0x1U << SDMMC_DCTRL_RWMOD_Pos)        /*!< 0x00000400 */\r\n#define SDMMC_DCTRL_RWMOD               SDMMC_DCTRL_RWMOD_Msk                  /*!<Read wait mode          */\r\n#define SDMMC_DCTRL_SDIOEN_Pos          (11U)                                  \r\n#define SDMMC_DCTRL_SDIOEN_Msk          (0x1U << SDMMC_DCTRL_SDIOEN_Pos)       /*!< 0x00000800 */\r\n#define SDMMC_DCTRL_SDIOEN              SDMMC_DCTRL_SDIOEN_Msk                 /*!<SD I/O enable functions */\r\n\r\n/******************  Bit definition for SDMMC_DCOUNT register  *****************/\r\n#define SDMMC_DCOUNT_DATACOUNT_Pos      (0U)                                   \r\n#define SDMMC_DCOUNT_DATACOUNT_Msk      (0x1FFFFFFU << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */\r\n#define SDMMC_DCOUNT_DATACOUNT          SDMMC_DCOUNT_DATACOUNT_Msk             /*!<Data count value */\r\n\r\n/******************  Bit definition for SDMMC_STA registe  ********************/\r\n#define SDMMC_STA_CCRCFAIL_Pos          (0U)                                   \r\n#define SDMMC_STA_CCRCFAIL_Msk          (0x1U << SDMMC_STA_CCRCFAIL_Pos)       /*!< 0x00000001 */\r\n#define SDMMC_STA_CCRCFAIL              SDMMC_STA_CCRCFAIL_Msk                 /*!<Command response received (CRC check failed)  */\r\n#define SDMMC_STA_DCRCFAIL_Pos          (1U)                                   \r\n#define SDMMC_STA_DCRCFAIL_Msk          (0x1U << SDMMC_STA_DCRCFAIL_Pos)       /*!< 0x00000002 */\r\n#define SDMMC_STA_DCRCFAIL              SDMMC_STA_DCRCFAIL_Msk                 /*!<Data block sent/received (CRC check failed)   */\r\n#define SDMMC_STA_CTIMEOUT_Pos          (2U)                                   \r\n#define SDMMC_STA_CTIMEOUT_Msk          (0x1U << SDMMC_STA_CTIMEOUT_Pos)       /*!< 0x00000004 */\r\n#define SDMMC_STA_CTIMEOUT              SDMMC_STA_CTIMEOUT_Msk                 /*!<Command response timeout                      */\r\n#define SDMMC_STA_DTIMEOUT_Pos          (3U)                                   \r\n#define SDMMC_STA_DTIMEOUT_Msk          (0x1U << SDMMC_STA_DTIMEOUT_Pos)       /*!< 0x00000008 */\r\n#define SDMMC_STA_DTIMEOUT              SDMMC_STA_DTIMEOUT_Msk                 /*!<Data timeout                                  */\r\n#define SDMMC_STA_TXUNDERR_Pos          (4U)                                   \r\n#define SDMMC_STA_TXUNDERR_Msk          (0x1U << SDMMC_STA_TXUNDERR_Pos)       /*!< 0x00000010 */\r\n#define SDMMC_STA_TXUNDERR              SDMMC_STA_TXUNDERR_Msk                 /*!<Transmit FIFO underrun error                  */\r\n#define SDMMC_STA_RXOVERR_Pos           (5U)                                   \r\n#define SDMMC_STA_RXOVERR_Msk           (0x1U << SDMMC_STA_RXOVERR_Pos)        /*!< 0x00000020 */\r\n#define SDMMC_STA_RXOVERR               SDMMC_STA_RXOVERR_Msk                  /*!<Received FIFO overrun error                   */\r\n#define SDMMC_STA_CMDREND_Pos           (6U)                                   \r\n#define SDMMC_STA_CMDREND_Msk           (0x1U << SDMMC_STA_CMDREND_Pos)        /*!< 0x00000040 */\r\n#define SDMMC_STA_CMDREND               SDMMC_STA_CMDREND_Msk                  /*!<Command response received (CRC check passed)  */\r\n#define SDMMC_STA_CMDSENT_Pos           (7U)                                   \r\n#define SDMMC_STA_CMDSENT_Msk           (0x1U << SDMMC_STA_CMDSENT_Pos)        /*!< 0x00000080 */\r\n#define SDMMC_STA_CMDSENT               SDMMC_STA_CMDSENT_Msk                  /*!<Command sent (no response required)           */\r\n#define SDMMC_STA_DATAEND_Pos           (8U)                                   \r\n#define SDMMC_STA_DATAEND_Msk           (0x1U << SDMMC_STA_DATAEND_Pos)        /*!< 0x00000100 */\r\n#define SDMMC_STA_DATAEND               SDMMC_STA_DATAEND_Msk                  /*!<Data end (data counter, SDIDCOUNT, is zero)   */\r\n#define SDMMC_STA_DBCKEND_Pos           (10U)                                  \r\n#define SDMMC_STA_DBCKEND_Msk           (0x1U << SDMMC_STA_DBCKEND_Pos)        /*!< 0x00000400 */\r\n#define SDMMC_STA_DBCKEND               SDMMC_STA_DBCKEND_Msk                  /*!<Data block sent/received (CRC check passed)   */\r\n#define SDMMC_STA_CMDACT_Pos            (11U)                                  \r\n#define SDMMC_STA_CMDACT_Msk            (0x1U << SDMMC_STA_CMDACT_Pos)         /*!< 0x00000800 */\r\n#define SDMMC_STA_CMDACT                SDMMC_STA_CMDACT_Msk                   /*!<Command transfer in progress                  */\r\n#define SDMMC_STA_TXACT_Pos             (12U)                                  \r\n#define SDMMC_STA_TXACT_Msk             (0x1U << SDMMC_STA_TXACT_Pos)          /*!< 0x00001000 */\r\n#define SDMMC_STA_TXACT                 SDMMC_STA_TXACT_Msk                    /*!<Data transmit in progress                     */\r\n#define SDMMC_STA_RXACT_Pos             (13U)                                  \r\n#define SDMMC_STA_RXACT_Msk             (0x1U << SDMMC_STA_RXACT_Pos)          /*!< 0x00002000 */\r\n#define SDMMC_STA_RXACT                 SDMMC_STA_RXACT_Msk                    /*!<Data receive in progress                      */\r\n#define SDMMC_STA_TXFIFOHE_Pos          (14U)                                  \r\n#define SDMMC_STA_TXFIFOHE_Msk          (0x1U << SDMMC_STA_TXFIFOHE_Pos)       /*!< 0x00004000 */\r\n#define SDMMC_STA_TXFIFOHE              SDMMC_STA_TXFIFOHE_Msk                 /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */\r\n#define SDMMC_STA_RXFIFOHF_Pos          (15U)                                  \r\n#define SDMMC_STA_RXFIFOHF_Msk          (0x1U << SDMMC_STA_RXFIFOHF_Pos)       /*!< 0x00008000 */\r\n#define SDMMC_STA_RXFIFOHF              SDMMC_STA_RXFIFOHF_Msk                 /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */\r\n#define SDMMC_STA_TXFIFOF_Pos           (16U)                                  \r\n#define SDMMC_STA_TXFIFOF_Msk           (0x1U << SDMMC_STA_TXFIFOF_Pos)        /*!< 0x00010000 */\r\n#define SDMMC_STA_TXFIFOF               SDMMC_STA_TXFIFOF_Msk                  /*!<Transmit FIFO full                            */\r\n#define SDMMC_STA_RXFIFOF_Pos           (17U)                                  \r\n#define SDMMC_STA_RXFIFOF_Msk           (0x1U << SDMMC_STA_RXFIFOF_Pos)        /*!< 0x00020000 */\r\n#define SDMMC_STA_RXFIFOF               SDMMC_STA_RXFIFOF_Msk                  /*!<Receive FIFO full                             */\r\n#define SDMMC_STA_TXFIFOE_Pos           (18U)                                  \r\n#define SDMMC_STA_TXFIFOE_Msk           (0x1U << SDMMC_STA_TXFIFOE_Pos)        /*!< 0x00040000 */\r\n#define SDMMC_STA_TXFIFOE               SDMMC_STA_TXFIFOE_Msk                  /*!<Transmit FIFO empty                           */\r\n#define SDMMC_STA_RXFIFOE_Pos           (19U)                                  \r\n#define SDMMC_STA_RXFIFOE_Msk           (0x1U << SDMMC_STA_RXFIFOE_Pos)        /*!< 0x00080000 */\r\n#define SDMMC_STA_RXFIFOE               SDMMC_STA_RXFIFOE_Msk                  /*!<Receive FIFO empty                            */\r\n#define SDMMC_STA_TXDAVL_Pos            (20U)                                  \r\n#define SDMMC_STA_TXDAVL_Msk            (0x1U << SDMMC_STA_TXDAVL_Pos)         /*!< 0x00100000 */\r\n#define SDMMC_STA_TXDAVL                SDMMC_STA_TXDAVL_Msk                   /*!<Data available in transmit FIFO               */\r\n#define SDMMC_STA_RXDAVL_Pos            (21U)                                  \r\n#define SDMMC_STA_RXDAVL_Msk            (0x1U << SDMMC_STA_RXDAVL_Pos)         /*!< 0x00200000 */\r\n#define SDMMC_STA_RXDAVL                SDMMC_STA_RXDAVL_Msk                   /*!<Data available in receive FIFO                */\r\n#define SDMMC_STA_SDIOIT_Pos            (22U)                                  \r\n#define SDMMC_STA_SDIOIT_Msk            (0x1U << SDMMC_STA_SDIOIT_Pos)         /*!< 0x00400000 */\r\n#define SDMMC_STA_SDIOIT                SDMMC_STA_SDIOIT_Msk                   /*!<SDMMC interrupt received                       */\r\n\r\n/*******************  Bit definition for SDMMC_ICR register  *******************/\r\n#define SDMMC_ICR_CCRCFAILC_Pos         (0U)                                   \r\n#define SDMMC_ICR_CCRCFAILC_Msk         (0x1U << SDMMC_ICR_CCRCFAILC_Pos)      /*!< 0x00000001 */\r\n#define SDMMC_ICR_CCRCFAILC             SDMMC_ICR_CCRCFAILC_Msk                /*!<CCRCFAIL flag clear bit */\r\n#define SDMMC_ICR_DCRCFAILC_Pos         (1U)                                   \r\n#define SDMMC_ICR_DCRCFAILC_Msk         (0x1U << SDMMC_ICR_DCRCFAILC_Pos)      /*!< 0x00000002 */\r\n#define SDMMC_ICR_DCRCFAILC             SDMMC_ICR_DCRCFAILC_Msk                /*!<DCRCFAIL flag clear bit */\r\n#define SDMMC_ICR_CTIMEOUTC_Pos         (2U)                                   \r\n#define SDMMC_ICR_CTIMEOUTC_Msk         (0x1U << SDMMC_ICR_CTIMEOUTC_Pos)      /*!< 0x00000004 */\r\n#define SDMMC_ICR_CTIMEOUTC             SDMMC_ICR_CTIMEOUTC_Msk                /*!<CTIMEOUT flag clear bit */\r\n#define SDMMC_ICR_DTIMEOUTC_Pos         (3U)                                   \r\n#define SDMMC_ICR_DTIMEOUTC_Msk         (0x1U << SDMMC_ICR_DTIMEOUTC_Pos)      /*!< 0x00000008 */\r\n#define SDMMC_ICR_DTIMEOUTC             SDMMC_ICR_DTIMEOUTC_Msk                /*!<DTIMEOUT flag clear bit */\r\n#define SDMMC_ICR_TXUNDERRC_Pos         (4U)                                   \r\n#define SDMMC_ICR_TXUNDERRC_Msk         (0x1U << SDMMC_ICR_TXUNDERRC_Pos)      /*!< 0x00000010 */\r\n#define SDMMC_ICR_TXUNDERRC             SDMMC_ICR_TXUNDERRC_Msk                /*!<TXUNDERR flag clear bit */\r\n#define SDMMC_ICR_RXOVERRC_Pos          (5U)                                   \r\n#define SDMMC_ICR_RXOVERRC_Msk          (0x1U << SDMMC_ICR_RXOVERRC_Pos)       /*!< 0x00000020 */\r\n#define SDMMC_ICR_RXOVERRC              SDMMC_ICR_RXOVERRC_Msk                 /*!<RXOVERR flag clear bit  */\r\n#define SDMMC_ICR_CMDRENDC_Pos          (6U)                                   \r\n#define SDMMC_ICR_CMDRENDC_Msk          (0x1U << SDMMC_ICR_CMDRENDC_Pos)       /*!< 0x00000040 */\r\n#define SDMMC_ICR_CMDRENDC              SDMMC_ICR_CMDRENDC_Msk                 /*!<CMDREND flag clear bit  */\r\n#define SDMMC_ICR_CMDSENTC_Pos          (7U)                                   \r\n#define SDMMC_ICR_CMDSENTC_Msk          (0x1U << SDMMC_ICR_CMDSENTC_Pos)       /*!< 0x00000080 */\r\n#define SDMMC_ICR_CMDSENTC              SDMMC_ICR_CMDSENTC_Msk                 /*!<CMDSENT flag clear bit  */\r\n#define SDMMC_ICR_DATAENDC_Pos          (8U)                                   \r\n#define SDMMC_ICR_DATAENDC_Msk          (0x1U << SDMMC_ICR_DATAENDC_Pos)       /*!< 0x00000100 */\r\n#define SDMMC_ICR_DATAENDC              SDMMC_ICR_DATAENDC_Msk                 /*!<DATAEND flag clear bit  */\r\n#define SDMMC_ICR_DBCKENDC_Pos          (10U)                                  \r\n#define SDMMC_ICR_DBCKENDC_Msk          (0x1U << SDMMC_ICR_DBCKENDC_Pos)       /*!< 0x00000400 */\r\n#define SDMMC_ICR_DBCKENDC              SDMMC_ICR_DBCKENDC_Msk                 /*!<DBCKEND flag clear bit  */\r\n#define SDMMC_ICR_SDIOITC_Pos           (22U)                                  \r\n#define SDMMC_ICR_SDIOITC_Msk           (0x1U << SDMMC_ICR_SDIOITC_Pos)        /*!< 0x00400000 */\r\n#define SDMMC_ICR_SDIOITC               SDMMC_ICR_SDIOITC_Msk                  /*!<SDMMCIT flag clear bit   */\r\n\r\n/******************  Bit definition for SDMMC_MASK register  *******************/\r\n#define SDMMC_MASK_CCRCFAILIE_Pos       (0U)                                   \r\n#define SDMMC_MASK_CCRCFAILIE_Msk       (0x1U << SDMMC_MASK_CCRCFAILIE_Pos)    /*!< 0x00000001 */\r\n#define SDMMC_MASK_CCRCFAILIE           SDMMC_MASK_CCRCFAILIE_Msk              /*!<Command CRC Fail Interrupt Enable          */\r\n#define SDMMC_MASK_DCRCFAILIE_Pos       (1U)                                   \r\n#define SDMMC_MASK_DCRCFAILIE_Msk       (0x1U << SDMMC_MASK_DCRCFAILIE_Pos)    /*!< 0x00000002 */\r\n#define SDMMC_MASK_DCRCFAILIE           SDMMC_MASK_DCRCFAILIE_Msk              /*!<Data CRC Fail Interrupt Enable             */\r\n#define SDMMC_MASK_CTIMEOUTIE_Pos       (2U)                                   \r\n#define SDMMC_MASK_CTIMEOUTIE_Msk       (0x1U << SDMMC_MASK_CTIMEOUTIE_Pos)    /*!< 0x00000004 */\r\n#define SDMMC_MASK_CTIMEOUTIE           SDMMC_MASK_CTIMEOUTIE_Msk              /*!<Command TimeOut Interrupt Enable           */\r\n#define SDMMC_MASK_DTIMEOUTIE_Pos       (3U)                                   \r\n#define SDMMC_MASK_DTIMEOUTIE_Msk       (0x1U << SDMMC_MASK_DTIMEOUTIE_Pos)    /*!< 0x00000008 */\r\n#define SDMMC_MASK_DTIMEOUTIE           SDMMC_MASK_DTIMEOUTIE_Msk              /*!<Data TimeOut Interrupt Enable              */\r\n#define SDMMC_MASK_TXUNDERRIE_Pos       (4U)                                   \r\n#define SDMMC_MASK_TXUNDERRIE_Msk       (0x1U << SDMMC_MASK_TXUNDERRIE_Pos)    /*!< 0x00000010 */\r\n#define SDMMC_MASK_TXUNDERRIE           SDMMC_MASK_TXUNDERRIE_Msk              /*!<Tx FIFO UnderRun Error Interrupt Enable    */\r\n#define SDMMC_MASK_RXOVERRIE_Pos        (5U)                                   \r\n#define SDMMC_MASK_RXOVERRIE_Msk        (0x1U << SDMMC_MASK_RXOVERRIE_Pos)     /*!< 0x00000020 */\r\n#define SDMMC_MASK_RXOVERRIE            SDMMC_MASK_RXOVERRIE_Msk               /*!<Rx FIFO OverRun Error Interrupt Enable     */\r\n#define SDMMC_MASK_CMDRENDIE_Pos        (6U)                                   \r\n#define SDMMC_MASK_CMDRENDIE_Msk        (0x1U << SDMMC_MASK_CMDRENDIE_Pos)     /*!< 0x00000040 */\r\n#define SDMMC_MASK_CMDRENDIE            SDMMC_MASK_CMDRENDIE_Msk               /*!<Command Response Received Interrupt Enable */\r\n#define SDMMC_MASK_CMDSENTIE_Pos        (7U)                                   \r\n#define SDMMC_MASK_CMDSENTIE_Msk        (0x1U << SDMMC_MASK_CMDSENTIE_Pos)     /*!< 0x00000080 */\r\n#define SDMMC_MASK_CMDSENTIE            SDMMC_MASK_CMDSENTIE_Msk               /*!<Command Sent Interrupt Enable              */\r\n#define SDMMC_MASK_DATAENDIE_Pos        (8U)                                   \r\n#define SDMMC_MASK_DATAENDIE_Msk        (0x1U << SDMMC_MASK_DATAENDIE_Pos)     /*!< 0x00000100 */\r\n#define SDMMC_MASK_DATAENDIE            SDMMC_MASK_DATAENDIE_Msk               /*!<Data End Interrupt Enable                  */\r\n#define SDMMC_MASK_DBCKENDIE_Pos        (10U)                                  \r\n#define SDMMC_MASK_DBCKENDIE_Msk        (0x1U << SDMMC_MASK_DBCKENDIE_Pos)     /*!< 0x00000400 */\r\n#define SDMMC_MASK_DBCKENDIE            SDMMC_MASK_DBCKENDIE_Msk               /*!<Data Block End Interrupt Enable            */\r\n#define SDMMC_MASK_CMDACTIE_Pos         (11U)                                  \r\n#define SDMMC_MASK_CMDACTIE_Msk         (0x1U << SDMMC_MASK_CMDACTIE_Pos)      /*!< 0x00000800 */\r\n#define SDMMC_MASK_CMDACTIE             SDMMC_MASK_CMDACTIE_Msk                /*!<CCommand Acting Interrupt Enable           */\r\n#define SDMMC_MASK_TXACTIE_Pos          (12U)                                  \r\n#define SDMMC_MASK_TXACTIE_Msk          (0x1U << SDMMC_MASK_TXACTIE_Pos)       /*!< 0x00001000 */\r\n#define SDMMC_MASK_TXACTIE              SDMMC_MASK_TXACTIE_Msk                 /*!<Data Transmit Acting Interrupt Enable      */\r\n#define SDMMC_MASK_RXACTIE_Pos          (13U)                                  \r\n#define SDMMC_MASK_RXACTIE_Msk          (0x1U << SDMMC_MASK_RXACTIE_Pos)       /*!< 0x00002000 */\r\n#define SDMMC_MASK_RXACTIE              SDMMC_MASK_RXACTIE_Msk                 /*!<Data receive acting interrupt enabled      */\r\n#define SDMMC_MASK_TXFIFOHEIE_Pos       (14U)                                  \r\n#define SDMMC_MASK_TXFIFOHEIE_Msk       (0x1U << SDMMC_MASK_TXFIFOHEIE_Pos)    /*!< 0x00004000 */\r\n#define SDMMC_MASK_TXFIFOHEIE           SDMMC_MASK_TXFIFOHEIE_Msk              /*!<Tx FIFO Half Empty interrupt Enable        */\r\n#define SDMMC_MASK_RXFIFOHFIE_Pos       (15U)                                  \r\n#define SDMMC_MASK_RXFIFOHFIE_Msk       (0x1U << SDMMC_MASK_RXFIFOHFIE_Pos)    /*!< 0x00008000 */\r\n#define SDMMC_MASK_RXFIFOHFIE           SDMMC_MASK_RXFIFOHFIE_Msk              /*!<Rx FIFO Half Full interrupt Enable         */\r\n#define SDMMC_MASK_TXFIFOFIE_Pos        (16U)                                  \r\n#define SDMMC_MASK_TXFIFOFIE_Msk        (0x1U << SDMMC_MASK_TXFIFOFIE_Pos)     /*!< 0x00010000 */\r\n#define SDMMC_MASK_TXFIFOFIE            SDMMC_MASK_TXFIFOFIE_Msk               /*!<Tx FIFO Full interrupt Enable              */\r\n#define SDMMC_MASK_RXFIFOFIE_Pos        (17U)                                  \r\n#define SDMMC_MASK_RXFIFOFIE_Msk        (0x1U << SDMMC_MASK_RXFIFOFIE_Pos)     /*!< 0x00020000 */\r\n#define SDMMC_MASK_RXFIFOFIE            SDMMC_MASK_RXFIFOFIE_Msk               /*!<Rx FIFO Full interrupt Enable              */\r\n#define SDMMC_MASK_TXFIFOEIE_Pos        (18U)                                  \r\n#define SDMMC_MASK_TXFIFOEIE_Msk        (0x1U << SDMMC_MASK_TXFIFOEIE_Pos)     /*!< 0x00040000 */\r\n#define SDMMC_MASK_TXFIFOEIE            SDMMC_MASK_TXFIFOEIE_Msk               /*!<Tx FIFO Empty interrupt Enable             */\r\n#define SDMMC_MASK_RXFIFOEIE_Pos        (19U)                                  \r\n#define SDMMC_MASK_RXFIFOEIE_Msk        (0x1U << SDMMC_MASK_RXFIFOEIE_Pos)     /*!< 0x00080000 */\r\n#define SDMMC_MASK_RXFIFOEIE            SDMMC_MASK_RXFIFOEIE_Msk               /*!<Rx FIFO Empty interrupt Enable             */\r\n#define SDMMC_MASK_TXDAVLIE_Pos         (20U)                                  \r\n#define SDMMC_MASK_TXDAVLIE_Msk         (0x1U << SDMMC_MASK_TXDAVLIE_Pos)      /*!< 0x00100000 */\r\n#define SDMMC_MASK_TXDAVLIE             SDMMC_MASK_TXDAVLIE_Msk                /*!<Data available in Tx FIFO interrupt Enable */\r\n#define SDMMC_MASK_RXDAVLIE_Pos         (21U)                                  \r\n#define SDMMC_MASK_RXDAVLIE_Msk         (0x1U << SDMMC_MASK_RXDAVLIE_Pos)      /*!< 0x00200000 */\r\n#define SDMMC_MASK_RXDAVLIE             SDMMC_MASK_RXDAVLIE_Msk                /*!<Data available in Rx FIFO interrupt Enable */\r\n#define SDMMC_MASK_SDIOITIE_Pos         (22U)                                  \r\n#define SDMMC_MASK_SDIOITIE_Msk         (0x1U << SDMMC_MASK_SDIOITIE_Pos)      /*!< 0x00400000 */\r\n#define SDMMC_MASK_SDIOITIE             SDMMC_MASK_SDIOITIE_Msk                /*!<SDMMC Mode Interrupt Received interrupt Enable */\r\n\r\n/*****************  Bit definition for SDMMC_FIFOCNT register  *****************/\r\n#define SDMMC_FIFOCNT_FIFOCOUNT_Pos     (0U)                                   \r\n#define SDMMC_FIFOCNT_FIFOCOUNT_Msk     (0xFFFFFFU << SDMMC_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */\r\n#define SDMMC_FIFOCNT_FIFOCOUNT         SDMMC_FIFOCNT_FIFOCOUNT_Msk            /*!<Remaining number of words to be written to or read from the FIFO */\r\n\r\n/******************  Bit definition for SDMMC_FIFO register  *******************/\r\n#define SDMMC_FIFO_FIFODATA_Pos         (0U)                                   \r\n#define SDMMC_FIFO_FIFODATA_Msk         (0xFFFFFFFFU << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */\r\n#define SDMMC_FIFO_FIFODATA             SDMMC_FIFO_FIFODATA_Msk                /*!<Receive and transmit FIFO data */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                        Serial Peripheral Interface (SPI)                   */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************  Bit definition for SPI_CR1 register  ********************/\r\n#define SPI_CR1_CPHA_Pos            (0U)                                       \r\n#define SPI_CR1_CPHA_Msk            (0x1U << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */\r\n#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!< Clock Phase                        */\r\n#define SPI_CR1_CPOL_Pos            (1U)                                       \r\n#define SPI_CR1_CPOL_Msk            (0x1U << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */\r\n#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!< Clock Polarity                     */\r\n#define SPI_CR1_MSTR_Pos            (2U)                                       \r\n#define SPI_CR1_MSTR_Msk            (0x1U << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */\r\n#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!< Master Selection                   */\r\n#define SPI_CR1_BR_Pos              (3U)                                       \r\n#define SPI_CR1_BR_Msk              (0x7U << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */\r\n#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!< BR[2:0] bits (Baud Rate Control)   */\r\n#define SPI_CR1_BR_0                (0x1U << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */\r\n#define SPI_CR1_BR_1                (0x2U << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */\r\n#define SPI_CR1_BR_2                (0x4U << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */\r\n#define SPI_CR1_SPE_Pos             (6U)                                       \r\n#define SPI_CR1_SPE_Msk             (0x1U << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */\r\n#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!< SPI Enable                          */\r\n#define SPI_CR1_LSBFIRST_Pos        (7U)                                       \r\n#define SPI_CR1_LSBFIRST_Msk        (0x1U << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */\r\n#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!< Frame Format                        */\r\n#define SPI_CR1_SSI_Pos             (8U)                                       \r\n#define SPI_CR1_SSI_Msk             (0x1U << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */\r\n#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!< Internal slave select               */\r\n#define SPI_CR1_SSM_Pos             (9U)                                       \r\n#define SPI_CR1_SSM_Msk             (0x1U << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */\r\n#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!< Software slave management           */\r\n#define SPI_CR1_RXONLY_Pos          (10U)                                      \r\n#define SPI_CR1_RXONLY_Msk          (0x1U << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */\r\n#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!< Receive only                        */\r\n#define SPI_CR1_CRCL_Pos            (11U)                                      \r\n#define SPI_CR1_CRCL_Msk            (0x1U << SPI_CR1_CRCL_Pos)                 /*!< 0x00000800 */\r\n#define SPI_CR1_CRCL                SPI_CR1_CRCL_Msk                           /*!< CRC Length                          */\r\n#define SPI_CR1_CRCNEXT_Pos         (12U)                                      \r\n#define SPI_CR1_CRCNEXT_Msk         (0x1U << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */\r\n#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!< Transmit CRC next                   */\r\n#define SPI_CR1_CRCEN_Pos           (13U)                                      \r\n#define SPI_CR1_CRCEN_Msk           (0x1U << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */\r\n#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!< Hardware CRC calculation enable     */\r\n#define SPI_CR1_BIDIOE_Pos          (14U)                                      \r\n#define SPI_CR1_BIDIOE_Msk          (0x1U << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */\r\n#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!< Output enable in bidirectional mode */\r\n#define SPI_CR1_BIDIMODE_Pos        (15U)                                      \r\n#define SPI_CR1_BIDIMODE_Msk        (0x1U << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */\r\n#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!< Bidirectional data mode enable      */\r\n\r\n/*******************  Bit definition for SPI_CR2 register  ********************/\r\n#define SPI_CR2_RXDMAEN_Pos         (0U)                                       \r\n#define SPI_CR2_RXDMAEN_Msk         (0x1U << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */\r\n#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable                 */\r\n#define SPI_CR2_TXDMAEN_Pos         (1U)                                       \r\n#define SPI_CR2_TXDMAEN_Msk         (0x1U << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */\r\n#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable                 */\r\n#define SPI_CR2_SSOE_Pos            (2U)                                       \r\n#define SPI_CR2_SSOE_Msk            (0x1U << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */\r\n#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable                     */\r\n#define SPI_CR2_NSSP_Pos            (3U)                                       \r\n#define SPI_CR2_NSSP_Msk            (0x1U << SPI_CR2_NSSP_Pos)                 /*!< 0x00000008 */\r\n#define SPI_CR2_NSSP                SPI_CR2_NSSP_Msk                           /*!< NSS pulse management Enable          */\r\n#define SPI_CR2_FRF_Pos             (4U)                                       \r\n#define SPI_CR2_FRF_Msk             (0x1U << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */\r\n#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable                  */\r\n#define SPI_CR2_ERRIE_Pos           (5U)                                       \r\n#define SPI_CR2_ERRIE_Msk           (0x1U << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */\r\n#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable               */\r\n#define SPI_CR2_RXNEIE_Pos          (6U)                                       \r\n#define SPI_CR2_RXNEIE_Msk          (0x1U << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */\r\n#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */\r\n#define SPI_CR2_TXEIE_Pos           (7U)                                       \r\n#define SPI_CR2_TXEIE_Msk           (0x1U << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */\r\n#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable     */\r\n#define SPI_CR2_DS_Pos              (8U)                                       \r\n#define SPI_CR2_DS_Msk              (0xFU << SPI_CR2_DS_Pos)                   /*!< 0x00000F00 */\r\n#define SPI_CR2_DS                  SPI_CR2_DS_Msk                             /*!< DS[3:0] Data Size                    */\r\n#define SPI_CR2_DS_0                (0x1U << SPI_CR2_DS_Pos)                   /*!< 0x00000100 */\r\n#define SPI_CR2_DS_1                (0x2U << SPI_CR2_DS_Pos)                   /*!< 0x00000200 */\r\n#define SPI_CR2_DS_2                (0x4U << SPI_CR2_DS_Pos)                   /*!< 0x00000400 */\r\n#define SPI_CR2_DS_3                (0x8U << SPI_CR2_DS_Pos)                   /*!< 0x00000800 */\r\n#define SPI_CR2_FRXTH_Pos           (12U)                                      \r\n#define SPI_CR2_FRXTH_Msk           (0x1U << SPI_CR2_FRXTH_Pos)                /*!< 0x00001000 */\r\n#define SPI_CR2_FRXTH               SPI_CR2_FRXTH_Msk                          /*!< FIFO reception Threshold           */\r\n#define SPI_CR2_LDMARX_Pos          (13U)                                      \r\n#define SPI_CR2_LDMARX_Msk          (0x1U << SPI_CR2_LDMARX_Pos)               /*!< 0x00002000 */\r\n#define SPI_CR2_LDMARX              SPI_CR2_LDMARX_Msk                         /*!< Last DMA transfer for reception    */\r\n#define SPI_CR2_LDMATX_Pos          (14U)                                      \r\n#define SPI_CR2_LDMATX_Msk          (0x1U << SPI_CR2_LDMATX_Pos)               /*!< 0x00004000 */\r\n#define SPI_CR2_LDMATX              SPI_CR2_LDMATX_Msk                         /*!< Last DMA transfer for transmission */\r\n\r\n/********************  Bit definition for SPI_SR register  ********************/\r\n#define SPI_SR_RXNE_Pos             (0U)                                       \r\n#define SPI_SR_RXNE_Msk             (0x1U << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */\r\n#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty  */\r\n#define SPI_SR_TXE_Pos              (1U)                                       \r\n#define SPI_SR_TXE_Msk              (0x1U << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */\r\n#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty     */\r\n#define SPI_SR_CHSIDE_Pos           (2U)                                       \r\n#define SPI_SR_CHSIDE_Msk           (0x1U << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */\r\n#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side              */\r\n#define SPI_SR_UDR_Pos              (3U)                                       \r\n#define SPI_SR_UDR_Msk              (0x1U << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */\r\n#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag             */\r\n#define SPI_SR_CRCERR_Pos           (4U)                                       \r\n#define SPI_SR_CRCERR_Msk           (0x1U << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */\r\n#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag            */\r\n#define SPI_SR_MODF_Pos             (5U)                                       \r\n#define SPI_SR_MODF_Msk             (0x1U << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */\r\n#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault                */\r\n#define SPI_SR_OVR_Pos              (6U)                                       \r\n#define SPI_SR_OVR_Msk              (0x1U << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */\r\n#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag              */\r\n#define SPI_SR_BSY_Pos              (7U)                                       \r\n#define SPI_SR_BSY_Msk              (0x1U << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */\r\n#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag                 */\r\n#define SPI_SR_FRE_Pos              (8U)                                       \r\n#define SPI_SR_FRE_Msk              (0x1U << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */\r\n#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error     */\r\n#define SPI_SR_FRLVL_Pos            (9U)                                       \r\n#define SPI_SR_FRLVL_Msk            (0x3U << SPI_SR_FRLVL_Pos)                 /*!< 0x00000600 */\r\n#define SPI_SR_FRLVL                SPI_SR_FRLVL_Msk                           /*!< FIFO Reception Level      */\r\n#define SPI_SR_FRLVL_0              (0x1U << SPI_SR_FRLVL_Pos)                 /*!< 0x00000200 */\r\n#define SPI_SR_FRLVL_1              (0x2U << SPI_SR_FRLVL_Pos)                 /*!< 0x00000400 */\r\n#define SPI_SR_FTLVL_Pos            (11U)                                      \r\n#define SPI_SR_FTLVL_Msk            (0x3U << SPI_SR_FTLVL_Pos)                 /*!< 0x00001800 */\r\n#define SPI_SR_FTLVL                SPI_SR_FTLVL_Msk                           /*!< FIFO Transmission Level   */\r\n#define SPI_SR_FTLVL_0              (0x1U << SPI_SR_FTLVL_Pos)                 /*!< 0x00000800 */\r\n#define SPI_SR_FTLVL_1              (0x2U << SPI_SR_FTLVL_Pos)                 /*!< 0x00001000 */\r\n\r\n/********************  Bit definition for SPI_DR register  ********************/\r\n#define SPI_DR_DR_Pos               (0U)                                       \r\n#define SPI_DR_DR_Msk               (0xFFFFU << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */\r\n#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!< Data Register */\r\n\r\n/*******************  Bit definition for SPI_CRCPR register  ******************/\r\n#define SPI_CRCPR_CRCPOLY_Pos       (0U)                                       \r\n#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */\r\n#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!< CRC polynomial register */\r\n\r\n/******************  Bit definition for SPI_RXCRCR register  ******************/\r\n#define SPI_RXCRCR_RXCRC_Pos        (0U)                                       \r\n#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFU << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */\r\n#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!< Rx CRC Register */\r\n\r\n/******************  Bit definition for SPI_TXCRCR register  ******************/\r\n#define SPI_TXCRCR_TXCRC_Pos        (0U)                                       \r\n#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFU << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */\r\n#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!< Tx CRC Register */\r\n\r\n/******************  Bit definition for SPI_I2SCFGR register  *****************/\r\n#define SPI_I2SCFGR_CHLEN_Pos       (0U)                                       \r\n#define SPI_I2SCFGR_CHLEN_Msk       (0x1U << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */\r\n#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */\r\n#define SPI_I2SCFGR_DATLEN_Pos      (1U)                                       \r\n#define SPI_I2SCFGR_DATLEN_Msk      (0x3U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */\r\n#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred)  */\r\n#define SPI_I2SCFGR_DATLEN_0        (0x1U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */\r\n#define SPI_I2SCFGR_DATLEN_1        (0x2U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */\r\n#define SPI_I2SCFGR_CKPOL_Pos       (3U)                                       \r\n#define SPI_I2SCFGR_CKPOL_Msk       (0x1U << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */\r\n#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity                       */\r\n#define SPI_I2SCFGR_I2SSTD_Pos      (4U)                                       \r\n#define SPI_I2SCFGR_I2SSTD_Msk      (0x3U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */\r\n#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection)         */\r\n#define SPI_I2SCFGR_I2SSTD_0        (0x1U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */\r\n#define SPI_I2SCFGR_I2SSTD_1        (0x2U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */\r\n#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)                                       \r\n#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1U << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */\r\n#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                         */\r\n#define SPI_I2SCFGR_I2SCFG_Pos      (8U)                                       \r\n#define SPI_I2SCFGR_I2SCFG_Msk      (0x3U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */\r\n#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode)         */\r\n#define SPI_I2SCFGR_I2SCFG_0        (0x1U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */\r\n#define SPI_I2SCFGR_I2SCFG_1        (0x2U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */\r\n#define SPI_I2SCFGR_I2SE_Pos        (10U)                                      \r\n#define SPI_I2SCFGR_I2SE_Msk        (0x1U << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */\r\n#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable                                        */\r\n#define SPI_I2SCFGR_I2SMOD_Pos      (11U)                                      \r\n#define SPI_I2SCFGR_I2SMOD_Msk      (0x1U << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */\r\n#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection                                */\r\n#define SPI_I2SCFGR_ASTRTEN_Pos     (12U)                                      \r\n#define SPI_I2SCFGR_ASTRTEN_Msk     (0x1U << SPI_I2SCFGR_ASTRTEN_Pos)          /*!< 0x00001000 */\r\n#define SPI_I2SCFGR_ASTRTEN         SPI_I2SCFGR_ASTRTEN_Msk                    /*!<Asynchronous start enable                        */\r\n\r\n/******************  Bit definition for SPI_I2SPR register  *******************/\r\n#define SPI_I2SPR_I2SDIV_Pos        (0U)                                       \r\n#define SPI_I2SPR_I2SDIV_Msk        (0xFFU << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */\r\n#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler         */\r\n#define SPI_I2SPR_ODD_Pos           (8U)                                       \r\n#define SPI_I2SPR_ODD_Msk           (0x1U << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */\r\n#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */\r\n#define SPI_I2SPR_MCKOE_Pos         (9U)                                       \r\n#define SPI_I2SPR_MCKOE_Msk         (0x1U << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */\r\n#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable   */\r\n\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                 SYSCFG                                     */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/******************  Bit definition for SYSCFG_MEMRMP register  ***************/\r\n#define SYSCFG_MEMRMP_MEM_BOOT_Pos      (0U)                                   \r\n#define SYSCFG_MEMRMP_MEM_BOOT_Msk      (0x1U << SYSCFG_MEMRMP_MEM_BOOT_Pos)   /*!< 0x00000001 */\r\n#define SYSCFG_MEMRMP_MEM_BOOT          SYSCFG_MEMRMP_MEM_BOOT_Msk             /*!< Boot information after Reset */\r\n\r\n\r\n#define SYSCFG_MEMRMP_SWP_FMC_Pos       (10U)                                  \r\n#define SYSCFG_MEMRMP_SWP_FMC_Msk       (0x3U << SYSCFG_MEMRMP_SWP_FMC_Pos)    /*!< 0x00000C00 */\r\n#define SYSCFG_MEMRMP_SWP_FMC           SYSCFG_MEMRMP_SWP_FMC_Msk              /*!< FMC Memory Mapping swapping */\r\n#define SYSCFG_MEMRMP_SWP_FMC_0         (0x1U << SYSCFG_MEMRMP_SWP_FMC_Pos)    /*!< 0x00000400 */\r\n#define SYSCFG_MEMRMP_SWP_FMC_1         (0x2U << SYSCFG_MEMRMP_SWP_FMC_Pos)    /*!< 0x00000800 */\r\n\r\n/******************  Bit definition for SYSCFG_PMC register  ******************/\r\n\r\n#define SYSCFG_PMC_ADCxDC2_Pos          (16U)                                  \r\n#define SYSCFG_PMC_ADCxDC2_Msk          (0x7U << SYSCFG_PMC_ADCxDC2_Pos)       /*!< 0x00070000 */\r\n#define SYSCFG_PMC_ADCxDC2              SYSCFG_PMC_ADCxDC2_Msk                 /*!< Refer to AN4073 on how to use this bit  */\r\n#define SYSCFG_PMC_ADC1DC2_Pos          (16U)                                  \r\n#define SYSCFG_PMC_ADC1DC2_Msk          (0x1U << SYSCFG_PMC_ADC1DC2_Pos)       /*!< 0x00010000 */\r\n#define SYSCFG_PMC_ADC1DC2              SYSCFG_PMC_ADC1DC2_Msk                 /*!< Refer to AN4073 on how to use this bit  */\r\n#define SYSCFG_PMC_ADC2DC2_Pos          (17U)                                  \r\n#define SYSCFG_PMC_ADC2DC2_Msk          (0x1U << SYSCFG_PMC_ADC2DC2_Pos)       /*!< 0x00020000 */\r\n#define SYSCFG_PMC_ADC2DC2              SYSCFG_PMC_ADC2DC2_Msk                 /*!< Refer to AN4073 on how to use this bit  */\r\n#define SYSCFG_PMC_ADC3DC2_Pos          (18U)                                  \r\n#define SYSCFG_PMC_ADC3DC2_Msk          (0x1U << SYSCFG_PMC_ADC3DC2_Pos)       /*!< 0x00040000 */\r\n#define SYSCFG_PMC_ADC3DC2              SYSCFG_PMC_ADC3DC2_Msk                 /*!< Refer to AN4073 on how to use this bit  */\r\n\r\n#define SYSCFG_PMC_MII_RMII_SEL_Pos     (23U)                                  \r\n#define SYSCFG_PMC_MII_RMII_SEL_Msk     (0x1U << SYSCFG_PMC_MII_RMII_SEL_Pos)  /*!< 0x00800000 */\r\n#define SYSCFG_PMC_MII_RMII_SEL         SYSCFG_PMC_MII_RMII_SEL_Msk            /*!<Ethernet PHY interface selection */\r\n\r\n/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/\r\n#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)                                   \r\n#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFU << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x0000000F */\r\n#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */\r\n#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)                                   \r\n#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFU << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x000000F0 */\r\n#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */\r\n#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)                                   \r\n#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFU << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000F00 */\r\n#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */\r\n#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)                                  \r\n#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFU << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x0000F000 */\r\n#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */\r\n/**\r\n  * @brief   EXTI0 configuration\r\n  */\r\n#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U                                /*!<PA[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U                                /*!<PB[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U                                /*!<PC[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U                                /*!<PD[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U                                /*!<PE[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PF         0x0005U                                /*!<PF[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PG         0x0006U                                /*!<PG[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U                                /*!<PH[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PI         0x0008U                                /*!<PI[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PJ         0x0009U                                /*!<PJ[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PK         0x000AU                                /*!<PK[0] pin */\r\n\r\n/**\r\n  * @brief   EXTI1 configuration\r\n  */\r\n#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U                                /*!<PA[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U                                /*!<PB[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U                                /*!<PC[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U                                /*!<PD[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U                                /*!<PE[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PF         0x0050U                                /*!<PF[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PG         0x0060U                                /*!<PG[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U                                /*!<PH[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PI         0x0080U                                /*!<PI[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PJ         0x0090U                                /*!<PJ[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PK         0x00A0U                                /*!<PK[1] pin */\r\n\r\n/**\r\n  * @brief   EXTI2 configuration\r\n  */\r\n#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U                                /*!<PA[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U                                /*!<PB[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U                                /*!<PC[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U                                /*!<PD[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U                                /*!<PE[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PF         0x0500U                                /*!<PF[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PG         0x0600U                                /*!<PG[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U                                /*!<PH[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PI         0x0800U                                /*!<PI[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PJ         0x0900U                                /*!<PJ[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PK         0x0A00U                                /*!<PK[2] pin */\r\n\r\n/**\r\n  * @brief   EXTI3 configuration\r\n  */\r\n#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U                                /*!<PA[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U                                /*!<PB[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U                                /*!<PC[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U                                /*!<PD[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U                                /*!<PE[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PF         0x5000U                                /*!<PF[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PG         0x6000U                                /*!<PG[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U                                /*!<PH[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PI         0x8000U                                /*!<PI[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PJ         0x9000U                                /*!<PJ[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PK         0xA000U                                /*!<PK[3] pin */\r\n\r\n/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/\r\n#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)                                   \r\n#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFU << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x0000000F */\r\n#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */\r\n#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)                                   \r\n#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFU << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x000000F0 */\r\n#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */\r\n#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)                                   \r\n#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFU << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000F00 */\r\n#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */\r\n#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)                                  \r\n#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFU << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x0000F000 */\r\n#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */\r\n/**\r\n  * @brief   EXTI4 configuration\r\n  */\r\n#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U                                /*!<PA[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U                                /*!<PB[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U                                /*!<PC[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U                                /*!<PD[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U                                /*!<PE[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PF         0x0005U                                /*!<PF[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PG         0x0006U                                /*!<PG[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U                                /*!<PH[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PI         0x0008U                                /*!<PI[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PJ         0x0009U                                /*!<PJ[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PK         0x000AU                                /*!<PK[4] pin */\r\n\r\n/**\r\n  * @brief   EXTI5 configuration\r\n  */\r\n#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U                                /*!<PA[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U                                /*!<PB[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U                                /*!<PC[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U                                /*!<PD[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U                                /*!<PE[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PF         0x0050U                                /*!<PF[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PG         0x0060U                                /*!<PG[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U                                /*!<PH[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PI         0x0080U                                /*!<PI[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PJ         0x0090U                                /*!<PJ[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PK         0x00A0U                                /*!<PK[5] pin */\r\n\r\n/**\r\n  * @brief   EXTI6 configuration\r\n  */\r\n#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U                                /*!<PA[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U                                /*!<PB[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U                                /*!<PC[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U                                /*!<PD[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U                                /*!<PE[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PF         0x0500U                                /*!<PF[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PG         0x0600U                                /*!<PG[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U                                /*!<PH[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PI         0x0800U                                /*!<PI[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PJ         0x0900U                                /*!<PJ[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PK         0x0A00U                                /*!<PK[6] pin */\r\n\r\n/**\r\n  * @brief   EXTI7 configuration\r\n  */\r\n#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U                                /*!<PA[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U                                /*!<PB[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U                                /*!<PC[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U                                /*!<PD[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U                                /*!<PE[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PF         0x5000U                                /*!<PF[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PG         0x6000U                                /*!<PG[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U                                /*!<PH[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PI         0x8000U                                /*!<PI[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PJ         0x9000U                                /*!<PJ[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PK         0xA000U                                /*!<PK[7] pin */\r\n\r\n/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/\r\n#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)                                   \r\n#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFU << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x0000000F */\r\n#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */\r\n#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)                                   \r\n#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFU << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x000000F0 */\r\n#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */\r\n#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)                                   \r\n#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFU << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000F00 */\r\n#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */\r\n#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)                                  \r\n#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFU << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x0000F000 */\r\n#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */\r\n\r\n/**\r\n  * @brief   EXTI8 configuration\r\n  */\r\n#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U                                /*!<PA[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U                                /*!<PB[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U                                /*!<PC[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U                                /*!<PD[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U                                /*!<PE[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PF         0x0005U                                /*!<PF[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PG         0x0006U                                /*!<PG[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U                                /*!<PH[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PI         0x0008U                                /*!<PI[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PJ         0x0009U                                /*!<PJ[8] pin */\r\n\r\n/**\r\n  * @brief   EXTI9 configuration\r\n  */\r\n#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U                                /*!<PA[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U                                /*!<PB[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U                                /*!<PC[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U                                /*!<PD[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U                                /*!<PE[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PF         0x0050U                                /*!<PF[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PG         0x0060U                                /*!<PG[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U                                /*!<PH[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PI         0x0080U                                /*!<PI[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PJ         0x0090U                                /*!<PJ[9] pin */\r\n\r\n/**\r\n  * @brief   EXTI10 configuration\r\n  */\r\n#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U                                /*!<PA[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U                                /*!<PB[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U                                /*!<PC[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U                                /*!<PD[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U                                /*!<PE[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PF        0x0500U                                /*!<PF[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PG        0x0600U                                /*!<PG[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U                                /*!<PH[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PI        0x0800U                                /*!<PI[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PJ        0x0900U                                /*!<PJ[10] pin */\r\n\r\n/**\r\n  * @brief   EXTI11 configuration\r\n  */\r\n#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U                                /*!<PA[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U                                /*!<PB[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U                                /*!<PC[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U                                /*!<PD[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U                                /*!<PE[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PF        0x5000U                                /*!<PF[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PG        0x6000U                                /*!<PG[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U                                /*!<PH[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PI        0x8000U                                /*!<PI[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PJ        0x9000U                                /*!<PJ[11] pin */\r\n\r\n\r\n/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/\r\n#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)                                   \r\n#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFU << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x0000000F */\r\n#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */\r\n#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)                                   \r\n#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFU << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x000000F0 */\r\n#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */\r\n#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)                                   \r\n#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFU << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000F00 */\r\n#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */\r\n#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)                                  \r\n#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFU << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x0000F000 */\r\n#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */\r\n/**\r\n  * @brief   EXTI12 configuration\r\n  */\r\n#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U                                /*!<PA[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U                                /*!<PB[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U                                /*!<PC[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U                                /*!<PD[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U                                /*!<PE[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PF        0x0005U                                /*!<PF[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PG        0x0006U                                /*!<PG[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U                                /*!<PH[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PI        0x0008U                                /*!<PI[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PJ        0x0009U                                /*!<PJ[12] pin */\r\n\r\n/**\r\n  * @brief   EXTI13 configuration\r\n  */\r\n#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U                                /*!<PA[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U                                /*!<PB[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U                                /*!<PC[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U                                /*!<PD[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U                                /*!<PE[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PF        0x0050U                                /*!<PF[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PG        0x0060U                                /*!<PG[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U                                /*!<PH[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PI        0x0080U                                /*!<PI[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PJ        0x0090U                                /*!<PJ[13] pin */\r\n\r\n/**\r\n  * @brief   EXTI14 configuration\r\n  */\r\n#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U                                /*!<PA[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U                                /*!<PB[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U                                /*!<PC[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U                                /*!<PD[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U                                /*!<PE[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PF        0x0500U                                /*!<PF[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PG        0x0600U                                /*!<PG[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U                                /*!<PH[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PI        0x0800U                                /*!<PI[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PJ        0x0900U                                /*!<PJ[14] pin */\r\n\r\n/**\r\n  * @brief   EXTI15 configuration\r\n  */\r\n#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U                                /*!<PA[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U                                /*!<PB[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U                                /*!<PC[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U                                /*!<PD[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U                                /*!<PE[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PF        0x5000U                                /*!<PF[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PG        0x6000U                                /*!<PG[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U                                /*!<PH[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PI        0x8000U                                /*!<PI[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PJ        0x9000U                                /*!<PJ[15] pin */\r\n\r\n\r\n/******************  Bit definition for SYSCFG_CMPCR register  ****************/\r\n#define SYSCFG_CMPCR_CMP_PD_Pos         (0U)                                   \r\n#define SYSCFG_CMPCR_CMP_PD_Msk         (0x1U << SYSCFG_CMPCR_CMP_PD_Pos)      /*!< 0x00000001 */\r\n#define SYSCFG_CMPCR_CMP_PD             SYSCFG_CMPCR_CMP_PD_Msk                /*!<Compensation cell power-down */\r\n#define SYSCFG_CMPCR_READY_Pos          (8U)                                   \r\n#define SYSCFG_CMPCR_READY_Msk          (0x1U << SYSCFG_CMPCR_READY_Pos)       /*!< 0x00000100 */\r\n#define SYSCFG_CMPCR_READY              SYSCFG_CMPCR_READY_Msk                 /*!<Compensation cell ready flag */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                    TIM                                     */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************  Bit definition for TIM_CR1 register  ********************/\r\n#define TIM_CR1_CEN_Pos           (0U)                                         \r\n#define TIM_CR1_CEN_Msk           (0x1U << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */\r\n#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable        */\r\n#define TIM_CR1_UDIS_Pos          (1U)                                         \r\n#define TIM_CR1_UDIS_Msk          (0x1U << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */\r\n#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable        */\r\n#define TIM_CR1_URS_Pos           (2U)                                         \r\n#define TIM_CR1_URS_Msk           (0x1U << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */\r\n#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */\r\n#define TIM_CR1_OPM_Pos           (3U)                                         \r\n#define TIM_CR1_OPM_Msk           (0x1U << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */\r\n#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode        */\r\n#define TIM_CR1_DIR_Pos           (4U)                                         \r\n#define TIM_CR1_DIR_Msk           (0x1U << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */\r\n#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction             */\r\n\r\n#define TIM_CR1_CMS_Pos           (5U)                                         \r\n#define TIM_CR1_CMS_Msk           (0x3U << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */\r\n#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */\r\n#define TIM_CR1_CMS_0             (0x1U << TIM_CR1_CMS_Pos)                    /*!< 0x0020 */\r\n#define TIM_CR1_CMS_1             (0x2U << TIM_CR1_CMS_Pos)                    /*!< 0x0040 */\r\n\r\n#define TIM_CR1_ARPE_Pos          (7U)                                         \r\n#define TIM_CR1_ARPE_Msk          (0x1U << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */\r\n#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable     */\r\n\r\n#define TIM_CR1_CKD_Pos           (8U)                                         \r\n#define TIM_CR1_CKD_Msk           (0x3U << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */\r\n#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */\r\n#define TIM_CR1_CKD_0             (0x1U << TIM_CR1_CKD_Pos)                    /*!< 0x0100 */\r\n#define TIM_CR1_CKD_1             (0x2U << TIM_CR1_CKD_Pos)                    /*!< 0x0200 */\r\n#define TIM_CR1_UIFREMAP_Pos      (11U)                                        \r\n#define TIM_CR1_UIFREMAP_Msk      (0x1U << TIM_CR1_UIFREMAP_Pos)               /*!< 0x00000800 */\r\n#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<UIF status bit */\r\n\r\n/*******************  Bit definition for TIM_CR2 register  ********************/\r\n#define TIM_CR2_CCPC_Pos          (0U)                                         \r\n#define TIM_CR2_CCPC_Msk          (0x1U << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */\r\n#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control        */\r\n#define TIM_CR2_CCUS_Pos          (2U)                                         \r\n#define TIM_CR2_CCUS_Msk          (0x1U << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */\r\n#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */\r\n#define TIM_CR2_CCDS_Pos          (3U)                                         \r\n#define TIM_CR2_CCDS_Msk          (0x1U << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */\r\n#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection            */\r\n\r\n#define TIM_CR2_OIS5_Pos          (16U)                                        \r\n#define TIM_CR2_OIS5_Msk          (0x1U << TIM_CR2_OIS5_Pos)                   /*!< 0x00010000 */\r\n#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */\r\n#define TIM_CR2_OIS6_Pos          (18U)                                        \r\n#define TIM_CR2_OIS6_Msk          (0x1U << TIM_CR2_OIS6_Pos)                   /*!< 0x00040000 */\r\n#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */\r\n\r\n#define TIM_CR2_MMS_Pos           (4U)                                         \r\n#define TIM_CR2_MMS_Msk           (0x7U << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */\r\n#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */\r\n#define TIM_CR2_MMS_0             (0x1U << TIM_CR2_MMS_Pos)                    /*!< 0x0010 */\r\n#define TIM_CR2_MMS_1             (0x2U << TIM_CR2_MMS_Pos)                    /*!< 0x0020 */\r\n#define TIM_CR2_MMS_2             (0x4U << TIM_CR2_MMS_Pos)                    /*!< 0x0040 */\r\n\r\n#define TIM_CR2_MMS2_Pos          (20U)                                        \r\n#define TIM_CR2_MMS2_Msk          (0xFU << TIM_CR2_MMS2_Pos)                   /*!< 0x00F00000 */\r\n#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */\r\n#define TIM_CR2_MMS2_0            (0x1U << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */\r\n#define TIM_CR2_MMS2_1            (0x2U << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */\r\n#define TIM_CR2_MMS2_2            (0x4U << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */\r\n#define TIM_CR2_MMS2_3            (0x8U << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */\r\n\r\n#define TIM_CR2_TI1S_Pos          (7U)                                         \r\n#define TIM_CR2_TI1S_Msk          (0x1U << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */\r\n#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */\r\n#define TIM_CR2_OIS1_Pos          (8U)                                         \r\n#define TIM_CR2_OIS1_Msk          (0x1U << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */\r\n#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output)  */\r\n#define TIM_CR2_OIS1N_Pos         (9U)                                         \r\n#define TIM_CR2_OIS1N_Msk         (0x1U << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */\r\n#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */\r\n#define TIM_CR2_OIS2_Pos          (10U)                                        \r\n#define TIM_CR2_OIS2_Msk          (0x1U << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */\r\n#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output)  */\r\n#define TIM_CR2_OIS2N_Pos         (11U)                                        \r\n#define TIM_CR2_OIS2N_Msk         (0x1U << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */\r\n#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */\r\n#define TIM_CR2_OIS3_Pos          (12U)                                        \r\n#define TIM_CR2_OIS3_Msk          (0x1U << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */\r\n#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output)  */\r\n#define TIM_CR2_OIS3N_Pos         (13U)                                        \r\n#define TIM_CR2_OIS3N_Msk         (0x1U << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */\r\n#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */\r\n#define TIM_CR2_OIS4_Pos          (14U)                                        \r\n#define TIM_CR2_OIS4_Msk          (0x1U << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */\r\n#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output)  */\r\n\r\n/*******************  Bit definition for TIM_SMCR register  *******************/\r\n#define TIM_SMCR_SMS_Pos          (0U)                                         \r\n#define TIM_SMCR_SMS_Msk          (0x10007U << TIM_SMCR_SMS_Pos)               /*!< 0x00010007 */\r\n#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection)    */\r\n#define TIM_SMCR_SMS_0            (0x00001U << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */\r\n#define TIM_SMCR_SMS_1            (0x00002U << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */\r\n#define TIM_SMCR_SMS_2            (0x00004U << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */\r\n#define TIM_SMCR_SMS_3            (0x10000U << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */\r\n\r\n#define TIM_SMCR_TS_Pos           (4U)                                         \r\n#define TIM_SMCR_TS_Msk           (0x7U << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */\r\n#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection)        */\r\n#define TIM_SMCR_TS_0             (0x1U << TIM_SMCR_TS_Pos)                    /*!< 0x0010 */\r\n#define TIM_SMCR_TS_1             (0x2U << TIM_SMCR_TS_Pos)                    /*!< 0x0020 */\r\n#define TIM_SMCR_TS_2             (0x4U << TIM_SMCR_TS_Pos)                    /*!< 0x0040 */\r\n\r\n#define TIM_SMCR_MSM_Pos          (7U)                                         \r\n#define TIM_SMCR_MSM_Msk          (0x1U << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */\r\n#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode                       */\r\n\r\n#define TIM_SMCR_ETF_Pos          (8U)                                         \r\n#define TIM_SMCR_ETF_Msk          (0xFU << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */\r\n#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */\r\n#define TIM_SMCR_ETF_0            (0x1U << TIM_SMCR_ETF_Pos)                   /*!< 0x0100 */\r\n#define TIM_SMCR_ETF_1            (0x2U << TIM_SMCR_ETF_Pos)                   /*!< 0x0200 */\r\n#define TIM_SMCR_ETF_2            (0x4U << TIM_SMCR_ETF_Pos)                   /*!< 0x0400 */\r\n#define TIM_SMCR_ETF_3            (0x8U << TIM_SMCR_ETF_Pos)                   /*!< 0x0800 */\r\n\r\n#define TIM_SMCR_ETPS_Pos         (12U)                                        \r\n#define TIM_SMCR_ETPS_Msk         (0x3U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */\r\n#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */\r\n#define TIM_SMCR_ETPS_0           (0x1U << TIM_SMCR_ETPS_Pos)                  /*!< 0x1000 */\r\n#define TIM_SMCR_ETPS_1           (0x2U << TIM_SMCR_ETPS_Pos)                  /*!< 0x2000 */\r\n\r\n#define TIM_SMCR_ECE_Pos          (14U)                                        \r\n#define TIM_SMCR_ECE_Msk          (0x1U << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */\r\n#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable     */\r\n#define TIM_SMCR_ETP_Pos          (15U)                                        \r\n#define TIM_SMCR_ETP_Msk          (0x1U << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */\r\n#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */\r\n\r\n/*******************  Bit definition for TIM_DIER register  *******************/\r\n#define TIM_DIER_UIE_Pos          (0U)                                         \r\n#define TIM_DIER_UIE_Msk          (0x1U << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */\r\n#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */\r\n#define TIM_DIER_CC1IE_Pos        (1U)                                         \r\n#define TIM_DIER_CC1IE_Msk        (0x1U << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */\r\n#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable   */\r\n#define TIM_DIER_CC2IE_Pos        (2U)                                         \r\n#define TIM_DIER_CC2IE_Msk        (0x1U << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */\r\n#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable   */\r\n#define TIM_DIER_CC3IE_Pos        (3U)                                         \r\n#define TIM_DIER_CC3IE_Msk        (0x1U << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */\r\n#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable   */\r\n#define TIM_DIER_CC4IE_Pos        (4U)                                         \r\n#define TIM_DIER_CC4IE_Msk        (0x1U << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */\r\n#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable   */\r\n#define TIM_DIER_COMIE_Pos        (5U)                                         \r\n#define TIM_DIER_COMIE_Msk        (0x1U << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */\r\n#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable                 */\r\n#define TIM_DIER_TIE_Pos          (6U)                                         \r\n#define TIM_DIER_TIE_Msk          (0x1U << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */\r\n#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable             */\r\n#define TIM_DIER_BIE_Pos          (7U)                                         \r\n#define TIM_DIER_BIE_Msk          (0x1U << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */\r\n#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable               */\r\n#define TIM_DIER_UDE_Pos          (8U)                                         \r\n#define TIM_DIER_UDE_Msk          (0x1U << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */\r\n#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable            */\r\n#define TIM_DIER_CC1DE_Pos        (9U)                                         \r\n#define TIM_DIER_CC1DE_Msk        (0x1U << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */\r\n#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */\r\n#define TIM_DIER_CC2DE_Pos        (10U)                                        \r\n#define TIM_DIER_CC2DE_Msk        (0x1U << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */\r\n#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */\r\n#define TIM_DIER_CC3DE_Pos        (11U)                                        \r\n#define TIM_DIER_CC3DE_Msk        (0x1U << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */\r\n#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */\r\n#define TIM_DIER_CC4DE_Pos        (12U)                                        \r\n#define TIM_DIER_CC4DE_Msk        (0x1U << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */\r\n#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */\r\n#define TIM_DIER_COMDE_Pos        (13U)                                        \r\n#define TIM_DIER_COMDE_Msk        (0x1U << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */\r\n#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable               */\r\n#define TIM_DIER_TDE_Pos          (14U)                                        \r\n#define TIM_DIER_TDE_Msk          (0x1U << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */\r\n#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable           */\r\n\r\n/********************  Bit definition for TIM_SR register  ********************/\r\n#define TIM_SR_UIF_Pos            (0U)                                         \r\n#define TIM_SR_UIF_Msk            (0x1U << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */\r\n#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag              */\r\n#define TIM_SR_CC1IF_Pos          (1U)                                         \r\n#define TIM_SR_CC1IF_Msk          (0x1U << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */\r\n#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag   */\r\n#define TIM_SR_CC2IF_Pos          (2U)                                         \r\n#define TIM_SR_CC2IF_Msk          (0x1U << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */\r\n#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag   */\r\n#define TIM_SR_CC3IF_Pos          (3U)                                         \r\n#define TIM_SR_CC3IF_Msk          (0x1U << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */\r\n#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag   */\r\n#define TIM_SR_CC4IF_Pos          (4U)                                         \r\n#define TIM_SR_CC4IF_Msk          (0x1U << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */\r\n#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag   */\r\n#define TIM_SR_COMIF_Pos          (5U)                                         \r\n#define TIM_SR_COMIF_Msk          (0x1U << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */\r\n#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag                 */\r\n#define TIM_SR_TIF_Pos            (6U)                                         \r\n#define TIM_SR_TIF_Msk            (0x1U << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */\r\n#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag             */\r\n#define TIM_SR_BIF_Pos            (7U)                                         \r\n#define TIM_SR_BIF_Msk            (0x1U << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */\r\n#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag               */\r\n#define TIM_SR_B2IF_Pos           (8U)                                         \r\n#define TIM_SR_B2IF_Msk           (0x1U << TIM_SR_B2IF_Pos)                    /*!< 0x00000100 */\r\n#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break2 interrupt Flag               */\r\n#define TIM_SR_CC1OF_Pos          (9U)                                         \r\n#define TIM_SR_CC1OF_Msk          (0x1U << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */\r\n#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */\r\n#define TIM_SR_CC2OF_Pos          (10U)                                        \r\n#define TIM_SR_CC2OF_Msk          (0x1U << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */\r\n#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */\r\n#define TIM_SR_CC3OF_Pos          (11U)                                        \r\n#define TIM_SR_CC3OF_Msk          (0x1U << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */\r\n#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */\r\n#define TIM_SR_CC4OF_Pos          (12U)                                        \r\n#define TIM_SR_CC4OF_Msk          (0x1U << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */\r\n#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */\r\n#define TIM_SR_SBIF_Pos           (13U)                                        \r\n#define TIM_SR_SBIF_Msk           (0x1U << TIM_SR_SBIF_Pos)                    /*!< 0x00002000 */\r\n#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */\r\n#define TIM_SR_CC5IF_Pos          (16U)                                        \r\n#define TIM_SR_CC5IF_Msk          (0x1U << TIM_SR_CC5IF_Pos)                   /*!< 0x00010000 */\r\n#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */\r\n#define TIM_SR_CC6IF_Pos          (17U)                                        \r\n#define TIM_SR_CC6IF_Msk          (0x1U << TIM_SR_CC6IF_Pos)                   /*!< 0x00020000 */\r\n#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */\r\n\r\n/*******************  Bit definition for TIM_EGR register  ********************/\r\n#define TIM_EGR_UG_Pos            (0U)                                         \r\n#define TIM_EGR_UG_Msk            (0x1U << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */\r\n#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation                         */\r\n#define TIM_EGR_CC1G_Pos          (1U)                                         \r\n#define TIM_EGR_CC1G_Msk          (0x1U << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */\r\n#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation              */\r\n#define TIM_EGR_CC2G_Pos          (2U)                                         \r\n#define TIM_EGR_CC2G_Msk          (0x1U << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */\r\n#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation              */\r\n#define TIM_EGR_CC3G_Pos          (3U)                                         \r\n#define TIM_EGR_CC3G_Msk          (0x1U << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */\r\n#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation              */\r\n#define TIM_EGR_CC4G_Pos          (4U)                                         \r\n#define TIM_EGR_CC4G_Msk          (0x1U << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */\r\n#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation              */\r\n#define TIM_EGR_COMG_Pos          (5U)                                         \r\n#define TIM_EGR_COMG_Msk          (0x1U << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */\r\n#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */\r\n#define TIM_EGR_TG_Pos            (6U)                                         \r\n#define TIM_EGR_TG_Msk            (0x1U << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */\r\n#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation                        */\r\n#define TIM_EGR_BG_Pos            (7U)                                         \r\n#define TIM_EGR_BG_Msk            (0x1U << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */\r\n#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation                          */\r\n#define TIM_EGR_B2G_Pos           (8U)                                         \r\n#define TIM_EGR_B2G_Msk           (0x1U << TIM_EGR_B2G_Pos)                    /*!< 0x00000100 */\r\n#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break2 Generation                          */\r\n\r\n/******************  Bit definition for TIM_CCMR1 register  *******************/\r\n#define TIM_CCMR1_CC1S_Pos        (0U)                                         \r\n#define TIM_CCMR1_CC1S_Msk        (0x3U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */\r\n#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\r\n#define TIM_CCMR1_CC1S_0          (0x1U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */\r\n#define TIM_CCMR1_CC1S_1          (0x2U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */\r\n\r\n#define TIM_CCMR1_OC1FE_Pos       (2U)                                         \r\n#define TIM_CCMR1_OC1FE_Msk       (0x1U << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */\r\n#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable                 */\r\n#define TIM_CCMR1_OC1PE_Pos       (3U)                                         \r\n#define TIM_CCMR1_OC1PE_Msk       (0x1U << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */\r\n#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable              */\r\n\r\n#define TIM_CCMR1_OC1M_Pos        (4U)                                         \r\n#define TIM_CCMR1_OC1M_Msk        (0x1007U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010070 */\r\n#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */\r\n#define TIM_CCMR1_OC1M_0          (0x0001U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */\r\n#define TIM_CCMR1_OC1M_1          (0x0002U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */\r\n#define TIM_CCMR1_OC1M_2          (0x0004U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */\r\n#define TIM_CCMR1_OC1M_3          (0x1000U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */\r\n\r\n#define TIM_CCMR1_OC1CE_Pos       (7U)                                         \r\n#define TIM_CCMR1_OC1CE_Msk       (0x1U << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */\r\n#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable                 */\r\n\r\n#define TIM_CCMR1_CC2S_Pos        (8U)                                         \r\n#define TIM_CCMR1_CC2S_Msk        (0x3U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */\r\n#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\r\n#define TIM_CCMR1_CC2S_0          (0x1U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */\r\n#define TIM_CCMR1_CC2S_1          (0x2U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */\r\n\r\n#define TIM_CCMR1_OC2FE_Pos       (10U)                                        \r\n#define TIM_CCMR1_OC2FE_Msk       (0x1U << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */\r\n#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable                 */\r\n#define TIM_CCMR1_OC2PE_Pos       (11U)                                        \r\n#define TIM_CCMR1_OC2PE_Msk       (0x1U << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */\r\n#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable              */\r\n\r\n#define TIM_CCMR1_OC2M_Pos        (12U)                                        \r\n#define TIM_CCMR1_OC2M_Msk        (0x1007U << TIM_CCMR1_OC2M_Pos)              /*!< 0x01007000 */\r\n#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */\r\n#define TIM_CCMR1_OC2M_0          (0x0001U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */\r\n#define TIM_CCMR1_OC2M_1          (0x0002U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */\r\n#define TIM_CCMR1_OC2M_2          (0x0004U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */\r\n#define TIM_CCMR1_OC2M_3          (0x1000U << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */\r\n\r\n#define TIM_CCMR1_OC2CE_Pos       (15U)                                        \r\n#define TIM_CCMR1_OC2CE_Msk       (0x1U << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */\r\n#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */\r\n\r\n/*----------------------------------------------------------------------------*/\r\n\r\n#define TIM_CCMR1_IC1PSC_Pos      (2U)                                         \r\n#define TIM_CCMR1_IC1PSC_Msk      (0x3U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */\r\n#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\r\n#define TIM_CCMR1_IC1PSC_0        (0x1U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0004 */\r\n#define TIM_CCMR1_IC1PSC_1        (0x2U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0008 */\r\n\r\n#define TIM_CCMR1_IC1F_Pos        (4U)                                         \r\n#define TIM_CCMR1_IC1F_Msk        (0xFU << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */\r\n#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */\r\n#define TIM_CCMR1_IC1F_0          (0x1U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0010 */\r\n#define TIM_CCMR1_IC1F_1          (0x2U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0020 */\r\n#define TIM_CCMR1_IC1F_2          (0x4U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0040 */\r\n#define TIM_CCMR1_IC1F_3          (0x8U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0080 */\r\n\r\n#define TIM_CCMR1_IC2PSC_Pos      (10U)                                        \r\n#define TIM_CCMR1_IC2PSC_Msk      (0x3U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */\r\n#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */\r\n#define TIM_CCMR1_IC2PSC_0        (0x1U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0400 */\r\n#define TIM_CCMR1_IC2PSC_1        (0x2U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0800 */\r\n\r\n#define TIM_CCMR1_IC2F_Pos        (12U)                                        \r\n#define TIM_CCMR1_IC2F_Msk        (0xFU << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */\r\n#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */\r\n#define TIM_CCMR1_IC2F_0          (0x1U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x1000 */\r\n#define TIM_CCMR1_IC2F_1          (0x2U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x2000 */\r\n#define TIM_CCMR1_IC2F_2          (0x4U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x4000 */\r\n#define TIM_CCMR1_IC2F_3          (0x8U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x8000 */\r\n\r\n/******************  Bit definition for TIM_CCMR2 register  *******************/\r\n#define TIM_CCMR2_CC3S_Pos        (0U)                                         \r\n#define TIM_CCMR2_CC3S_Msk        (0x3U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */\r\n#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */\r\n#define TIM_CCMR2_CC3S_0          (0x1U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */\r\n#define TIM_CCMR2_CC3S_1          (0x2U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */\r\n\r\n#define TIM_CCMR2_OC3FE_Pos       (2U)                                         \r\n#define TIM_CCMR2_OC3FE_Msk       (0x1U << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */\r\n#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable           */\r\n#define TIM_CCMR2_OC3PE_Pos       (3U)                                         \r\n#define TIM_CCMR2_OC3PE_Msk       (0x1U << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */\r\n#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable        */\r\n\r\n#define TIM_CCMR2_OC3M_Pos        (4U)                                         \r\n#define TIM_CCMR2_OC3M_Msk        (0x1007U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010070 */\r\n#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\r\n#define TIM_CCMR2_OC3M_0          (0x0001U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000010 */\r\n#define TIM_CCMR2_OC3M_1          (0x0002U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000020 */\r\n#define TIM_CCMR2_OC3M_2          (0x0004U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000040 */\r\n#define TIM_CCMR2_OC3M_3          (0x1000U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */\r\n\r\n\r\n\r\n#define TIM_CCMR2_OC3CE_Pos       (7U)                                         \r\n#define TIM_CCMR2_OC3CE_Msk       (0x1U << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */\r\n#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */\r\n\r\n#define TIM_CCMR2_CC4S_Pos        (8U)                                         \r\n#define TIM_CCMR2_CC4S_Msk        (0x3U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */\r\n#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\r\n#define TIM_CCMR2_CC4S_0          (0x1U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */\r\n#define TIM_CCMR2_CC4S_1          (0x2U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */\r\n\r\n#define TIM_CCMR2_OC4FE_Pos       (10U)                                        \r\n#define TIM_CCMR2_OC4FE_Msk       (0x1U << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */\r\n#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable    */\r\n#define TIM_CCMR2_OC4PE_Pos       (11U)                                        \r\n#define TIM_CCMR2_OC4PE_Msk       (0x1U << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */\r\n#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */\r\n\r\n#define TIM_CCMR2_OC4M_Pos        (12U)                                        \r\n#define TIM_CCMR2_OC4M_Msk        (0x1007U << TIM_CCMR2_OC4M_Pos)              /*!< 0x01007000 */\r\n#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r\n#define TIM_CCMR2_OC4M_0          (0x0001U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00001000 */\r\n#define TIM_CCMR2_OC4M_1          (0x0002U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00002000 */\r\n#define TIM_CCMR2_OC4M_2          (0x0004U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00004000 */\r\n#define TIM_CCMR2_OC4M_3          (0x1000U << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */\r\n\r\n#define TIM_CCMR2_OC4CE_Pos       (15U)                                        \r\n#define TIM_CCMR2_OC4CE_Msk       (0x1U << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */\r\n#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */\r\n\r\n/*----------------------------------------------------------------------------*/\r\n\r\n#define TIM_CCMR2_IC3PSC_Pos      (2U)                                         \r\n#define TIM_CCMR2_IC3PSC_Msk      (0x3U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */\r\n#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\r\n#define TIM_CCMR2_IC3PSC_0        (0x1U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0004 */\r\n#define TIM_CCMR2_IC3PSC_1        (0x2U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0008 */\r\n\r\n#define TIM_CCMR2_IC3F_Pos        (4U)                                         \r\n#define TIM_CCMR2_IC3F_Msk        (0xFU << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */\r\n#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\r\n#define TIM_CCMR2_IC3F_0          (0x1U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0010 */\r\n#define TIM_CCMR2_IC3F_1          (0x2U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0020 */\r\n#define TIM_CCMR2_IC3F_2          (0x4U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0040 */\r\n#define TIM_CCMR2_IC3F_3          (0x8U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0080 */\r\n\r\n#define TIM_CCMR2_IC4PSC_Pos      (10U)                                        \r\n#define TIM_CCMR2_IC4PSC_Msk      (0x3U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */\r\n#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\r\n#define TIM_CCMR2_IC4PSC_0        (0x1U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0400 */\r\n#define TIM_CCMR2_IC4PSC_1        (0x2U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0800 */\r\n\r\n#define TIM_CCMR2_IC4F_Pos        (12U)                                        \r\n#define TIM_CCMR2_IC4F_Msk        (0xFU << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */\r\n#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\r\n#define TIM_CCMR2_IC4F_0          (0x1U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x1000 */\r\n#define TIM_CCMR2_IC4F_1          (0x2U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x2000 */\r\n#define TIM_CCMR2_IC4F_2          (0x4U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x4000 */\r\n#define TIM_CCMR2_IC4F_3          (0x8U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x8000 */\r\n\r\n/*******************  Bit definition for TIM_CCER register  *******************/\r\n#define TIM_CCER_CC1E_Pos         (0U)                                         \r\n#define TIM_CCER_CC1E_Msk         (0x1U << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */\r\n#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */\r\n#define TIM_CCER_CC1P_Pos         (1U)                                         \r\n#define TIM_CCER_CC1P_Msk         (0x1U << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */\r\n#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */\r\n#define TIM_CCER_CC1NE_Pos        (2U)                                         \r\n#define TIM_CCER_CC1NE_Msk        (0x1U << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */\r\n#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */\r\n#define TIM_CCER_CC1NP_Pos        (3U)                                         \r\n#define TIM_CCER_CC1NP_Msk        (0x1U << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */\r\n#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */\r\n#define TIM_CCER_CC2E_Pos         (4U)                                         \r\n#define TIM_CCER_CC2E_Msk         (0x1U << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */\r\n#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */\r\n#define TIM_CCER_CC2P_Pos         (5U)                                         \r\n#define TIM_CCER_CC2P_Msk         (0x1U << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */\r\n#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */\r\n#define TIM_CCER_CC2NE_Pos        (6U)                                         \r\n#define TIM_CCER_CC2NE_Msk        (0x1U << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */\r\n#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */\r\n#define TIM_CCER_CC2NP_Pos        (7U)                                         \r\n#define TIM_CCER_CC2NP_Msk        (0x1U << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */\r\n#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */\r\n#define TIM_CCER_CC3E_Pos         (8U)                                         \r\n#define TIM_CCER_CC3E_Msk         (0x1U << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */\r\n#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */\r\n#define TIM_CCER_CC3P_Pos         (9U)                                         \r\n#define TIM_CCER_CC3P_Msk         (0x1U << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */\r\n#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */\r\n#define TIM_CCER_CC3NE_Pos        (10U)                                        \r\n#define TIM_CCER_CC3NE_Msk        (0x1U << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */\r\n#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */\r\n#define TIM_CCER_CC3NP_Pos        (11U)                                        \r\n#define TIM_CCER_CC3NP_Msk        (0x1U << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */\r\n#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */\r\n#define TIM_CCER_CC4E_Pos         (12U)                                        \r\n#define TIM_CCER_CC4E_Msk         (0x1U << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */\r\n#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */\r\n#define TIM_CCER_CC4P_Pos         (13U)                                        \r\n#define TIM_CCER_CC4P_Msk         (0x1U << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */\r\n#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */\r\n#define TIM_CCER_CC4NP_Pos        (15U)                                        \r\n#define TIM_CCER_CC4NP_Msk        (0x1U << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */\r\n#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */\r\n#define TIM_CCER_CC5E_Pos         (16U)                                        \r\n#define TIM_CCER_CC5E_Msk         (0x1U << TIM_CCER_CC5E_Pos)                  /*!< 0x00010000 */\r\n#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */\r\n#define TIM_CCER_CC5P_Pos         (17U)                                        \r\n#define TIM_CCER_CC5P_Msk         (0x1U << TIM_CCER_CC5P_Pos)                  /*!< 0x00020000 */\r\n#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */\r\n#define TIM_CCER_CC6E_Pos         (20U)                                        \r\n#define TIM_CCER_CC6E_Msk         (0x1U << TIM_CCER_CC6E_Pos)                  /*!< 0x00100000 */\r\n#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */\r\n#define TIM_CCER_CC6P_Pos         (21U)                                        \r\n#define TIM_CCER_CC6P_Msk         (0x1U << TIM_CCER_CC6P_Pos)                  /*!< 0x00200000 */\r\n#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */\r\n\r\n\r\n/*******************  Bit definition for TIM_CNT register  ********************/\r\n#define TIM_CNT_CNT_Pos           (0U)                                         \r\n#define TIM_CNT_CNT_Msk           (0xFFFFFFFFU << TIM_CNT_CNT_Pos)             /*!< 0xFFFFFFFF */\r\n#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value            */\r\n#define TIM_CNT_UIFCPY_Pos        (31U)                                        \r\n#define TIM_CNT_UIFCPY_Msk        (0x1U << TIM_CNT_UIFCPY_Pos)                 /*!< 0x80000000 */\r\n#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */\r\n\r\n/*******************  Bit definition for TIM_PSC register  ********************/\r\n#define TIM_PSC_PSC_Pos           (0U)                                         \r\n#define TIM_PSC_PSC_Msk           (0xFFFFU << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */\r\n#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value          */\r\n\r\n/*******************  Bit definition for TIM_ARR register  ********************/\r\n#define TIM_ARR_ARR_Pos           (0U)                                         \r\n#define TIM_ARR_ARR_Msk           (0xFFFFFFFFU << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */\r\n#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */\r\n\r\n/*******************  Bit definition for TIM_RCR register  ********************/\r\n#define TIM_RCR_REP_Pos           (0U)                                         \r\n#define TIM_RCR_REP_Msk           (0xFFFFU << TIM_RCR_REP_Pos)                 /*!< 0x0000FFFF */\r\n#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */\r\n\r\n/*******************  Bit definition for TIM_CCR1 register  *******************/\r\n#define TIM_CCR1_CCR1_Pos         (0U)                                         \r\n#define TIM_CCR1_CCR1_Msk         (0xFFFFU << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */\r\n#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value  */\r\n\r\n/*******************  Bit definition for TIM_CCR2 register  *******************/\r\n#define TIM_CCR2_CCR2_Pos         (0U)                                         \r\n#define TIM_CCR2_CCR2_Msk         (0xFFFFU << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */\r\n#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value  */\r\n\r\n/*******************  Bit definition for TIM_CCR3 register  *******************/\r\n#define TIM_CCR3_CCR3_Pos         (0U)                                         \r\n#define TIM_CCR3_CCR3_Msk         (0xFFFFU << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */\r\n#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value  */\r\n\r\n/*******************  Bit definition for TIM_CCR4 register  *******************/\r\n#define TIM_CCR4_CCR4_Pos         (0U)                                         \r\n#define TIM_CCR4_CCR4_Msk         (0xFFFFU << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */\r\n#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value  */\r\n\r\n/*******************  Bit definition for TIM_BDTR register  *******************/\r\n#define TIM_BDTR_DTG_Pos          (0U)                                         \r\n#define TIM_BDTR_DTG_Msk          (0xFFU << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */\r\n#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\r\n#define TIM_BDTR_DTG_0            (0x01U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */\r\n#define TIM_BDTR_DTG_1            (0x02U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */\r\n#define TIM_BDTR_DTG_2            (0x04U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */\r\n#define TIM_BDTR_DTG_3            (0x08U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */\r\n#define TIM_BDTR_DTG_4            (0x10U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */\r\n#define TIM_BDTR_DTG_5            (0x20U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */\r\n#define TIM_BDTR_DTG_6            (0x40U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */\r\n#define TIM_BDTR_DTG_7            (0x80U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */\r\n\r\n#define TIM_BDTR_LOCK_Pos         (8U)                                         \r\n#define TIM_BDTR_LOCK_Msk         (0x3U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */\r\n#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */\r\n#define TIM_BDTR_LOCK_0           (0x1U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */\r\n#define TIM_BDTR_LOCK_1           (0x2U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */\r\n\r\n#define TIM_BDTR_OSSI_Pos         (10U)                                        \r\n#define TIM_BDTR_OSSI_Msk         (0x1U << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */\r\n#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */\r\n#define TIM_BDTR_OSSR_Pos         (11U)                                        \r\n#define TIM_BDTR_OSSR_Msk         (0x1U << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */\r\n#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode  */\r\n#define TIM_BDTR_BKE_Pos          (12U)                                        \r\n#define TIM_BDTR_BKE_Msk          (0x1U << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */\r\n#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable                      */\r\n#define TIM_BDTR_BKP_Pos          (13U)                                        \r\n#define TIM_BDTR_BKP_Msk          (0x1U << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */\r\n#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity                    */\r\n#define TIM_BDTR_AOE_Pos          (14U)                                        \r\n#define TIM_BDTR_AOE_Msk          (0x1U << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */\r\n#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable           */\r\n#define TIM_BDTR_MOE_Pos          (15U)                                        \r\n#define TIM_BDTR_MOE_Msk          (0x1U << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */\r\n#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable                */\r\n#define TIM_BDTR_BKF_Pos          (16U)                                        \r\n#define TIM_BDTR_BKF_Msk          (0xFU << TIM_BDTR_BKF_Pos)                   /*!< 0x000F0000 */\r\n#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break1 */\r\n#define TIM_BDTR_BK2F_Pos         (20U)                                        \r\n#define TIM_BDTR_BK2F_Msk         (0xFU << TIM_BDTR_BK2F_Pos)                  /*!< 0x00F00000 */\r\n#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break2 */\r\n#define TIM_BDTR_BK2E_Pos         (24U)                                        \r\n#define TIM_BDTR_BK2E_Msk         (0x1U << TIM_BDTR_BK2E_Pos)                  /*!< 0x01000000 */\r\n#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break2 */\r\n#define TIM_BDTR_BK2P_Pos         (25U)                                        \r\n#define TIM_BDTR_BK2P_Msk         (0x1U << TIM_BDTR_BK2P_Pos)                  /*!< 0x02000000 */\r\n#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */\r\n\r\n/*******************  Bit definition for TIM_DCR register  ********************/\r\n#define TIM_DCR_DBA_Pos           (0U)                                         \r\n#define TIM_DCR_DBA_Msk           (0x1FU << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */\r\n#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */\r\n#define TIM_DCR_DBA_0             (0x01U << TIM_DCR_DBA_Pos)                   /*!< 0x0001 */\r\n#define TIM_DCR_DBA_1             (0x02U << TIM_DCR_DBA_Pos)                   /*!< 0x0002 */\r\n#define TIM_DCR_DBA_2             (0x04U << TIM_DCR_DBA_Pos)                   /*!< 0x0004 */\r\n#define TIM_DCR_DBA_3             (0x08U << TIM_DCR_DBA_Pos)                   /*!< 0x0008 */\r\n#define TIM_DCR_DBA_4             (0x10U << TIM_DCR_DBA_Pos)                   /*!< 0x0010 */\r\n\r\n#define TIM_DCR_DBL_Pos           (8U)                                         \r\n#define TIM_DCR_DBL_Msk           (0x1FU << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */\r\n#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */\r\n#define TIM_DCR_DBL_0             (0x01U << TIM_DCR_DBL_Pos)                   /*!< 0x0100 */\r\n#define TIM_DCR_DBL_1             (0x02U << TIM_DCR_DBL_Pos)                   /*!< 0x0200 */\r\n#define TIM_DCR_DBL_2             (0x04U << TIM_DCR_DBL_Pos)                   /*!< 0x0400 */\r\n#define TIM_DCR_DBL_3             (0x08U << TIM_DCR_DBL_Pos)                   /*!< 0x0800 */\r\n#define TIM_DCR_DBL_4             (0x10U << TIM_DCR_DBL_Pos)                   /*!< 0x1000 */\r\n\r\n/*******************  Bit definition for TIM_DMAR register  *******************/\r\n#define TIM_DMAR_DMAB_Pos         (0U)                                         \r\n#define TIM_DMAR_DMAB_Msk         (0xFFFFU << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */\r\n#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses                    */\r\n\r\n/*******************  Bit definition for TIM_OR regiter  *********************/\r\n#define TIM_OR_TI4_RMP_Pos        (6U)                                         \r\n#define TIM_OR_TI4_RMP_Msk        (0x3U << TIM_OR_TI4_RMP_Pos)                 /*!< 0x000000C0 */\r\n#define TIM_OR_TI4_RMP            TIM_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */\r\n#define TIM_OR_TI4_RMP_0          (0x1U << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0040 */\r\n#define TIM_OR_TI4_RMP_1          (0x2U << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0080 */\r\n#define TIM_OR_ITR1_RMP_Pos       (10U)                                        \r\n#define TIM_OR_ITR1_RMP_Msk       (0x3U << TIM_OR_ITR1_RMP_Pos)                /*!< 0x00000C00 */\r\n#define TIM_OR_ITR1_RMP           TIM_OR_ITR1_RMP_Msk                          /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */\r\n#define TIM_OR_ITR1_RMP_0         (0x1U << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0400 */\r\n#define TIM_OR_ITR1_RMP_1         (0x2U << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0800 */\r\n\r\n/*******************  Bit definition for TIM2_OR register  *******************/\r\n#define TIM2_OR_ITR1_RMP_Pos      (10U)                                        \r\n#define TIM2_OR_ITR1_RMP_Msk      (0x3U << TIM2_OR_ITR1_RMP_Pos)               /*!< 0x00000C00 */\r\n#define TIM2_OR_ITR1_RMP          TIM2_OR_ITR1_RMP_Msk                         /*!<TIM2 Internal trigger 1 remap */\r\n#define TIM2_OR_ITR1_RMP_0        (0x1U << TIM2_OR_ITR1_RMP_Pos)               /*!< 0x00000400 */\r\n#define TIM2_OR_ITR1_RMP_1        (0x2U << TIM2_OR_ITR1_RMP_Pos)               /*!< 0x00000800 */\r\n\r\n/*******************  Bit definition for TIM5_OR register  *******************/\r\n#define TIM5_OR_TI4_RMP_Pos      (6U)                                          \r\n#define TIM5_OR_TI4_RMP_Msk      (0x3U << TIM5_OR_TI4_RMP_Pos)                 /*!< 0x000000C0 */\r\n#define TIM5_OR_TI4_RMP          TIM5_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM5 Input Capture 4 remap) */\r\n#define TIM5_OR_TI4_RMP_0        (0x1U << TIM5_OR_TI4_RMP_Pos)                 /*!< 0x00000040 */\r\n#define TIM5_OR_TI4_RMP_1        (0x2U << TIM5_OR_TI4_RMP_Pos)                 /*!< 0x00000080 */\r\n\r\n/*******************  Bit definition for TIM11_OR register  *******************/\r\n#define TIM11_OR_TI1_RMP_Pos      (0U)                                         \r\n#define TIM11_OR_TI1_RMP_Msk      (0x3U << TIM11_OR_TI1_RMP_Pos)               /*!< 0x00000003 */\r\n#define TIM11_OR_TI1_RMP          TIM11_OR_TI1_RMP_Msk                         /*!<TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */\r\n#define TIM11_OR_TI1_RMP_0        (0x1U << TIM11_OR_TI1_RMP_Pos)               /*!< 0x00000001 */\r\n#define TIM11_OR_TI1_RMP_1        (0x2U << TIM11_OR_TI1_RMP_Pos)               /*!< 0x00000002 */\r\n\r\n/******************  Bit definition for TIM_CCMR3 register  *******************/\r\n#define TIM_CCMR3_OC5FE_Pos       (2U)                                         \r\n#define TIM_CCMR3_OC5FE_Msk       (0x1U << TIM_CCMR3_OC5FE_Pos)                /*!< 0x00000004 */\r\n#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */\r\n#define TIM_CCMR3_OC5PE_Pos       (3U)                                         \r\n#define TIM_CCMR3_OC5PE_Msk       (0x1U << TIM_CCMR3_OC5PE_Pos)                /*!< 0x00000008 */\r\n#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */\r\n\r\n#define TIM_CCMR3_OC5M_Pos        (4U)                                         \r\n#define TIM_CCMR3_OC5M_Msk        (0x1007U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010070 */\r\n#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */\r\n#define TIM_CCMR3_OC5M_0          (0x0001U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000010 */\r\n#define TIM_CCMR3_OC5M_1          (0x0002U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000020 */\r\n#define TIM_CCMR3_OC5M_2          (0x0004U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000040 */\r\n#define TIM_CCMR3_OC5M_3          (0x1000U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */\r\n\r\n#define TIM_CCMR3_OC5CE_Pos       (7U)                                         \r\n#define TIM_CCMR3_OC5CE_Msk       (0x1U << TIM_CCMR3_OC5CE_Pos)                /*!< 0x00000080 */\r\n#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */\r\n\r\n#define TIM_CCMR3_OC6FE_Pos       (10U)                                        \r\n#define TIM_CCMR3_OC6FE_Msk       (0x1U << TIM_CCMR3_OC6FE_Pos)                /*!< 0x00000400 */\r\n#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 4 Fast enable */\r\n#define TIM_CCMR3_OC6PE_Pos       (11U)                                        \r\n#define TIM_CCMR3_OC6PE_Msk       (0x1U << TIM_CCMR3_OC6PE_Pos)                /*!< 0x00000800 */\r\n#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */\r\n\r\n#define TIM_CCMR3_OC6M_Pos        (12U)                                        \r\n#define TIM_CCMR3_OC6M_Msk        (0x1007U << TIM_CCMR3_OC6M_Pos)              /*!< 0x01007000 */\r\n#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r\n#define TIM_CCMR3_OC6M_0          (0x0001U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00001000 */\r\n#define TIM_CCMR3_OC6M_1          (0x0002U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00002000 */\r\n#define TIM_CCMR3_OC6M_2          (0x0004U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00004000 */\r\n#define TIM_CCMR3_OC6M_3          (0x1000U << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */\r\n\r\n#define TIM_CCMR3_OC6CE_Pos       (15U)                                        \r\n#define TIM_CCMR3_OC6CE_Msk       (0x1U << TIM_CCMR3_OC6CE_Pos)                /*!< 0x00008000 */\r\n#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 4 Clear Enable */\r\n\r\n/*******************  Bit definition for TIM_CCR5 register  *******************/\r\n#define TIM_CCR5_CCR5_Pos         (0U)                                         \r\n#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos)           /*!< 0xFFFFFFFF */\r\n#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */\r\n#define TIM_CCR5_GC5C1_Pos        (29U)                                        \r\n#define TIM_CCR5_GC5C1_Msk        (0x1U << TIM_CCR5_GC5C1_Pos)                 /*!< 0x20000000 */\r\n#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */\r\n#define TIM_CCR5_GC5C2_Pos        (30U)                                        \r\n#define TIM_CCR5_GC5C2_Msk        (0x1U << TIM_CCR5_GC5C2_Pos)                 /*!< 0x40000000 */\r\n#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */\r\n#define TIM_CCR5_GC5C3_Pos        (31U)                                        \r\n#define TIM_CCR5_GC5C3_Msk        (0x1U << TIM_CCR5_GC5C3_Pos)                 /*!< 0x80000000 */\r\n#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */\r\n\r\n/*******************  Bit definition for TIM_CCR6 register  *******************/\r\n#define  TIM_CCR6_CCR6           ((uint16_t)0xFFFFU)                           /*!<Capture/Compare 6 Value */\r\n\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                         Low Power Timer (LPTIM)                            */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/******************  Bit definition for LPTIM_ISR register  *******************/\r\n#define LPTIM_ISR_CMPM_Pos          (0U)                                       \r\n#define LPTIM_ISR_CMPM_Msk          (0x1U << LPTIM_ISR_CMPM_Pos)               /*!< 0x00000001 */\r\n#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match                       */\r\n#define LPTIM_ISR_ARRM_Pos          (1U)                                       \r\n#define LPTIM_ISR_ARRM_Msk          (0x1U << LPTIM_ISR_ARRM_Pos)               /*!< 0x00000002 */\r\n#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match                    */\r\n#define LPTIM_ISR_EXTTRIG_Pos       (2U)                                       \r\n#define LPTIM_ISR_EXTTRIG_Msk       (0x1U << LPTIM_ISR_EXTTRIG_Pos)            /*!< 0x00000004 */\r\n#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event         */\r\n#define LPTIM_ISR_CMPOK_Pos         (3U)                                       \r\n#define LPTIM_ISR_CMPOK_Msk         (0x1U << LPTIM_ISR_CMPOK_Pos)              /*!< 0x00000008 */\r\n#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK          */\r\n#define LPTIM_ISR_ARROK_Pos         (4U)                                       \r\n#define LPTIM_ISR_ARROK_Msk         (0x1U << LPTIM_ISR_ARROK_Pos)              /*!< 0x00000010 */\r\n#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK       */\r\n#define LPTIM_ISR_UP_Pos            (5U)                                       \r\n#define LPTIM_ISR_UP_Msk            (0x1U << LPTIM_ISR_UP_Pos)                 /*!< 0x00000020 */\r\n#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */\r\n#define LPTIM_ISR_DOWN_Pos          (6U)                                       \r\n#define LPTIM_ISR_DOWN_Msk          (0x1U << LPTIM_ISR_DOWN_Pos)               /*!< 0x00000040 */\r\n#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */\r\n\r\n/******************  Bit definition for LPTIM_ICR register  *******************/\r\n#define LPTIM_ICR_CMPMCF_Pos        (0U)                                       \r\n#define LPTIM_ICR_CMPMCF_Msk        (0x1U << LPTIM_ICR_CMPMCF_Pos)             /*!< 0x00000001 */\r\n#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag                       */\r\n#define LPTIM_ICR_ARRMCF_Pos        (1U)                                       \r\n#define LPTIM_ICR_ARRMCF_Msk        (0x1U << LPTIM_ICR_ARRMCF_Pos)             /*!< 0x00000002 */\r\n#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag                    */\r\n#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)                                       \r\n#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1U << LPTIM_ICR_EXTTRIGCF_Pos)          /*!< 0x00000004 */\r\n#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag         */\r\n#define LPTIM_ICR_CMPOKCF_Pos       (3U)                                       \r\n#define LPTIM_ICR_CMPOKCF_Msk       (0x1U << LPTIM_ICR_CMPOKCF_Pos)            /*!< 0x00000008 */\r\n#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag          */\r\n#define LPTIM_ICR_ARROKCF_Pos       (4U)                                       \r\n#define LPTIM_ICR_ARROKCF_Msk       (0x1U << LPTIM_ICR_ARROKCF_Pos)            /*!< 0x00000010 */\r\n#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag       */\r\n#define LPTIM_ICR_UPCF_Pos          (5U)                                       \r\n#define LPTIM_ICR_UPCF_Msk          (0x1U << LPTIM_ICR_UPCF_Pos)               /*!< 0x00000020 */\r\n#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */\r\n#define LPTIM_ICR_DOWNCF_Pos        (6U)                                       \r\n#define LPTIM_ICR_DOWNCF_Msk        (0x1U << LPTIM_ICR_DOWNCF_Pos)             /*!< 0x00000040 */\r\n#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */\r\n\r\n/******************  Bit definition for LPTIM_IER register *******************/\r\n#define LPTIM_IER_CMPMIE_Pos        (0U)                                       \r\n#define LPTIM_IER_CMPMIE_Msk        (0x1U << LPTIM_IER_CMPMIE_Pos)             /*!< 0x00000001 */\r\n#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable                       */\r\n#define LPTIM_IER_ARRMIE_Pos        (1U)                                       \r\n#define LPTIM_IER_ARRMIE_Msk        (0x1U << LPTIM_IER_ARRMIE_Pos)             /*!< 0x00000002 */\r\n#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable                    */\r\n#define LPTIM_IER_EXTTRIGIE_Pos     (2U)                                       \r\n#define LPTIM_IER_EXTTRIGIE_Msk     (0x1U << LPTIM_IER_EXTTRIGIE_Pos)          /*!< 0x00000004 */\r\n#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable         */\r\n#define LPTIM_IER_CMPOKIE_Pos       (3U)                                       \r\n#define LPTIM_IER_CMPOKIE_Msk       (0x1U << LPTIM_IER_CMPOKIE_Pos)            /*!< 0x00000008 */\r\n#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable          */\r\n#define LPTIM_IER_ARROKIE_Pos       (4U)                                       \r\n#define LPTIM_IER_ARROKIE_Msk       (0x1U << LPTIM_IER_ARROKIE_Pos)            /*!< 0x00000010 */\r\n#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable       */\r\n#define LPTIM_IER_UPIE_Pos          (5U)                                       \r\n#define LPTIM_IER_UPIE_Msk          (0x1U << LPTIM_IER_UPIE_Pos)               /*!< 0x00000020 */\r\n#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */\r\n#define LPTIM_IER_DOWNIE_Pos        (6U)                                       \r\n#define LPTIM_IER_DOWNIE_Msk        (0x1U << LPTIM_IER_DOWNIE_Pos)             /*!< 0x00000040 */\r\n#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */\r\n\r\n/******************  Bit definition for LPTIM_CFGR register*******************/\r\n#define LPTIM_CFGR_CKSEL_Pos        (0U)                                       \r\n#define LPTIM_CFGR_CKSEL_Msk        (0x1U << LPTIM_CFGR_CKSEL_Pos)             /*!< 0x00000001 */\r\n#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */\r\n\r\n#define LPTIM_CFGR_CKPOL_Pos        (1U)                                       \r\n#define LPTIM_CFGR_CKPOL_Msk        (0x3U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000006 */\r\n#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */\r\n#define LPTIM_CFGR_CKPOL_0          (0x1U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */\r\n#define LPTIM_CFGR_CKPOL_1          (0x2U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */\r\n\r\n#define LPTIM_CFGR_CKFLT_Pos        (3U)                                       \r\n#define LPTIM_CFGR_CKFLT_Msk        (0x3U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000018 */\r\n#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */\r\n#define LPTIM_CFGR_CKFLT_0          (0x1U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */\r\n#define LPTIM_CFGR_CKFLT_1          (0x2U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */\r\n\r\n#define LPTIM_CFGR_TRGFLT_Pos       (6U)                                       \r\n#define LPTIM_CFGR_TRGFLT_Msk       (0x3U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x000000C0 */\r\n#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */\r\n#define LPTIM_CFGR_TRGFLT_0         (0x1U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */\r\n#define LPTIM_CFGR_TRGFLT_1         (0x2U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */\r\n\r\n#define LPTIM_CFGR_PRESC_Pos        (9U)                                       \r\n#define LPTIM_CFGR_PRESC_Msk        (0x7U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000E00 */\r\n#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */\r\n#define LPTIM_CFGR_PRESC_0          (0x1U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */\r\n#define LPTIM_CFGR_PRESC_1          (0x2U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */\r\n#define LPTIM_CFGR_PRESC_2          (0x4U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */\r\n\r\n#define LPTIM_CFGR_TRIGSEL_Pos      (13U)                                      \r\n#define LPTIM_CFGR_TRIGSEL_Msk      (0x7U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x0000E000 */\r\n#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */\r\n#define LPTIM_CFGR_TRIGSEL_0        (0x1U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */\r\n#define LPTIM_CFGR_TRIGSEL_1        (0x2U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */\r\n#define LPTIM_CFGR_TRIGSEL_2        (0x4U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */\r\n\r\n#define LPTIM_CFGR_TRIGEN_Pos       (17U)                                      \r\n#define LPTIM_CFGR_TRIGEN_Msk       (0x3U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00060000 */\r\n#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */\r\n#define LPTIM_CFGR_TRIGEN_0         (0x1U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */\r\n#define LPTIM_CFGR_TRIGEN_1         (0x2U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */\r\n\r\n#define LPTIM_CFGR_TIMOUT_Pos       (19U)                                      \r\n#define LPTIM_CFGR_TIMOUT_Msk       (0x1U << LPTIM_CFGR_TIMOUT_Pos)            /*!< 0x00080000 */\r\n#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable           */\r\n#define LPTIM_CFGR_WAVE_Pos         (20U)                                      \r\n#define LPTIM_CFGR_WAVE_Msk         (0x1U << LPTIM_CFGR_WAVE_Pos)              /*!< 0x00100000 */\r\n#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape          */\r\n#define LPTIM_CFGR_WAVPOL_Pos       (21U)                                      \r\n#define LPTIM_CFGR_WAVPOL_Msk       (0x1U << LPTIM_CFGR_WAVPOL_Pos)            /*!< 0x00200000 */\r\n#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */\r\n#define LPTIM_CFGR_PRELOAD_Pos      (22U)                                      \r\n#define LPTIM_CFGR_PRELOAD_Msk      (0x1U << LPTIM_CFGR_PRELOAD_Pos)           /*!< 0x00400000 */\r\n#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode         */\r\n#define LPTIM_CFGR_COUNTMODE_Pos    (23U)                                      \r\n#define LPTIM_CFGR_COUNTMODE_Msk    (0x1U << LPTIM_CFGR_COUNTMODE_Pos)         /*!< 0x00800000 */\r\n#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable     */\r\n#define LPTIM_CFGR_ENC_Pos          (24U)                                      \r\n#define LPTIM_CFGR_ENC_Msk          (0x1U << LPTIM_CFGR_ENC_Pos)               /*!< 0x01000000 */\r\n#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable     */\r\n\r\n/******************  Bit definition for LPTIM_CR register  ********************/\r\n#define LPTIM_CR_ENABLE_Pos         (0U)                                       \r\n#define LPTIM_CR_ENABLE_Msk         (0x1U << LPTIM_CR_ENABLE_Pos)              /*!< 0x00000001 */\r\n#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable                 */\r\n#define LPTIM_CR_SNGSTRT_Pos        (1U)                                       \r\n#define LPTIM_CR_SNGSTRT_Msk        (0x1U << LPTIM_CR_SNGSTRT_Pos)             /*!< 0x00000002 */\r\n#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode     */\r\n#define LPTIM_CR_CNTSTRT_Pos        (2U)                                       \r\n#define LPTIM_CR_CNTSTRT_Msk        (0x1U << LPTIM_CR_CNTSTRT_Pos)             /*!< 0x00000004 */\r\n#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */\r\n\r\n/******************  Bit definition for LPTIM_CMP register *******************/\r\n#define LPTIM_CMP_CMP_Pos           (0U)                                       \r\n#define LPTIM_CMP_CMP_Msk           (0xFFFFU << LPTIM_CMP_CMP_Pos)             /*!< 0x0000FFFF */\r\n#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register     */\r\n\r\n/******************  Bit definition for LPTIM_ARR register *******************/\r\n#define LPTIM_ARR_ARR_Pos           (0U)                                       \r\n#define LPTIM_ARR_ARR_Msk           (0xFFFFU << LPTIM_ARR_ARR_Pos)             /*!< 0x0000FFFF */\r\n#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */\r\n\r\n/******************  Bit definition for LPTIM_CNT register *******************/\r\n#define LPTIM_CNT_CNT_Pos           (0U)                                       \r\n#define LPTIM_CNT_CNT_Msk           (0xFFFFU << LPTIM_CNT_CNT_Pos)             /*!< 0x0000FFFF */\r\n#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register     */\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/******************  Bit definition for USART_CR1 register  *******************/\r\n#define USART_CR1_UE_Pos              (0U)                                     \r\n#define USART_CR1_UE_Msk              (0x1U << USART_CR1_UE_Pos)               /*!< 0x00000001 */\r\n#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable                                    */\r\n#define USART_CR1_RE_Pos              (2U)                                     \r\n#define USART_CR1_RE_Msk              (0x1U << USART_CR1_RE_Pos)               /*!< 0x00000004 */\r\n#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable                                 */\r\n#define USART_CR1_TE_Pos              (3U)                                     \r\n#define USART_CR1_TE_Msk              (0x1U << USART_CR1_TE_Pos)               /*!< 0x00000008 */\r\n#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable                              */\r\n#define USART_CR1_IDLEIE_Pos          (4U)                                     \r\n#define USART_CR1_IDLEIE_Msk          (0x1U << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */\r\n#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable                           */\r\n#define USART_CR1_RXNEIE_Pos          (5U)                                     \r\n#define USART_CR1_RXNEIE_Msk          (0x1U << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */\r\n#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable                           */\r\n#define USART_CR1_TCIE_Pos            (6U)                                     \r\n#define USART_CR1_TCIE_Msk            (0x1U << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */\r\n#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable          */\r\n#define USART_CR1_TXEIE_Pos           (7U)                                     \r\n#define USART_CR1_TXEIE_Msk           (0x1U << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */\r\n#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable                            */\r\n#define USART_CR1_PEIE_Pos            (8U)                                     \r\n#define USART_CR1_PEIE_Msk            (0x1U << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */\r\n#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable                             */\r\n#define USART_CR1_PS_Pos              (9U)                                     \r\n#define USART_CR1_PS_Msk              (0x1U << USART_CR1_PS_Pos)               /*!< 0x00000200 */\r\n#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection                                */\r\n#define USART_CR1_PCE_Pos             (10U)                                    \r\n#define USART_CR1_PCE_Msk             (0x1U << USART_CR1_PCE_Pos)              /*!< 0x00000400 */\r\n#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable                           */\r\n#define USART_CR1_WAKE_Pos            (11U)                                    \r\n#define USART_CR1_WAKE_Msk            (0x1U << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */\r\n#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method                          */\r\n#define USART_CR1_M_Pos               (12U)                                    \r\n#define USART_CR1_M_Msk               (0x10001U << USART_CR1_M_Pos)            /*!< 0x10001000 */\r\n#define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length                                     */\r\n#define USART_CR1_M0                  (0x00001U << USART_CR1_M_Pos)            /*!< 0x00001000 */\r\n#define USART_CR1_MME_Pos             (13U)                                    \r\n#define USART_CR1_MME_Msk             (0x1U << USART_CR1_MME_Pos)              /*!< 0x00002000 */\r\n#define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable                                */\r\n#define USART_CR1_CMIE_Pos            (14U)                                    \r\n#define USART_CR1_CMIE_Msk            (0x1U << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */\r\n#define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable                */\r\n#define USART_CR1_OVER8_Pos           (15U)                                    \r\n#define USART_CR1_OVER8_Msk           (0x1U << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */\r\n#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode            */\r\n#define USART_CR1_DEDT_Pos            (16U)                                    \r\n#define USART_CR1_DEDT_Msk            (0x1FU << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */\r\n#define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */\r\n#define USART_CR1_DEDT_0              (0x01U << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */\r\n#define USART_CR1_DEDT_1              (0x02U << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */\r\n#define USART_CR1_DEDT_2              (0x04U << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */\r\n#define USART_CR1_DEDT_3              (0x08U << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */\r\n#define USART_CR1_DEDT_4              (0x10U << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */\r\n#define USART_CR1_DEAT_Pos            (21U)                                    \r\n#define USART_CR1_DEAT_Msk            (0x1FU << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */\r\n#define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time)   */\r\n#define USART_CR1_DEAT_0              (0x01U << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */\r\n#define USART_CR1_DEAT_1              (0x02U << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */\r\n#define USART_CR1_DEAT_2              (0x04U << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */\r\n#define USART_CR1_DEAT_3              (0x08U << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */\r\n#define USART_CR1_DEAT_4              (0x10U << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */\r\n#define USART_CR1_RTOIE_Pos           (26U)                                    \r\n#define USART_CR1_RTOIE_Msk           (0x1U << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */\r\n#define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */\r\n#define USART_CR1_EOBIE_Pos           (27U)                                    \r\n#define USART_CR1_EOBIE_Msk           (0x1U << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */\r\n#define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable     */\r\n#define USART_CR1_M1                  0x10000000U                              /*!< Word length - Bit 1               */\r\n\r\n/* Legacy defines */\r\n#define  USART_CR1_M_0                       USART_CR1_M0          /*!< Word length - Bit 0               */\r\n#define  USART_CR1_M_1                       USART_CR1_M1          /*!< Word length - Bit 1               */\r\n\r\n/******************  Bit definition for USART_CR2 register  *******************/\r\n#define USART_CR2_ADDM7_Pos           (4U)                                     \r\n#define USART_CR2_ADDM7_Msk           (0x1U << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */\r\n#define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection       */\r\n#define USART_CR2_LBDL_Pos            (5U)                                     \r\n#define USART_CR2_LBDL_Msk            (0x1U << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */\r\n#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length             */\r\n#define USART_CR2_LBDIE_Pos           (6U)                                     \r\n#define USART_CR2_LBDIE_Msk           (0x1U << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */\r\n#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable   */\r\n#define USART_CR2_LBCL_Pos            (8U)                                     \r\n#define USART_CR2_LBCL_Msk            (0x1U << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */\r\n#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse                   */\r\n#define USART_CR2_CPHA_Pos            (9U)                                     \r\n#define USART_CR2_CPHA_Msk            (0x1U << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */\r\n#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase                            */\r\n#define USART_CR2_CPOL_Pos            (10U)                                    \r\n#define USART_CR2_CPOL_Msk            (0x1U << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */\r\n#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity                         */\r\n#define USART_CR2_CLKEN_Pos           (11U)                                    \r\n#define USART_CR2_CLKEN_Msk           (0x1U << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */\r\n#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable                           */\r\n#define USART_CR2_STOP_Pos            (12U)                                    \r\n#define USART_CR2_STOP_Msk            (0x3U << USART_CR2_STOP_Pos)             /*!< 0x00003000 */\r\n#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits)             */\r\n#define USART_CR2_STOP_0              (0x1U << USART_CR2_STOP_Pos)             /*!< 0x00001000 */\r\n#define USART_CR2_STOP_1              (0x2U << USART_CR2_STOP_Pos)             /*!< 0x00002000 */\r\n#define USART_CR2_LINEN_Pos           (14U)                                    \r\n#define USART_CR2_LINEN_Msk           (0x1U << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */\r\n#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable                        */\r\n#define USART_CR2_SWAP_Pos            (15U)                                    \r\n#define USART_CR2_SWAP_Msk            (0x1U << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */\r\n#define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins                        */\r\n#define USART_CR2_RXINV_Pos           (16U)                                    \r\n#define USART_CR2_RXINV_Msk           (0x1U << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */\r\n#define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion          */\r\n#define USART_CR2_TXINV_Pos           (17U)                                    \r\n#define USART_CR2_TXINV_Msk           (0x1U << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */\r\n#define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion          */\r\n#define USART_CR2_DATAINV_Pos         (18U)                                    \r\n#define USART_CR2_DATAINV_Msk         (0x1U << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */\r\n#define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion                  */\r\n#define USART_CR2_MSBFIRST_Pos        (19U)                                    \r\n#define USART_CR2_MSBFIRST_Msk        (0x1U << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */\r\n#define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First             */\r\n#define USART_CR2_ABREN_Pos           (20U)                                    \r\n#define USART_CR2_ABREN_Msk           (0x1U << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */\r\n#define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable                  */\r\n#define USART_CR2_ABRMODE_Pos         (21U)                                    \r\n#define USART_CR2_ABRMODE_Msk         (0x3U << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */\r\n#define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */\r\n#define USART_CR2_ABRMODE_0           (0x1U << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */\r\n#define USART_CR2_ABRMODE_1           (0x2U << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */\r\n#define USART_CR2_RTOEN_Pos           (23U)                                    \r\n#define USART_CR2_RTOEN_Msk           (0x1U << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */\r\n#define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable  */\r\n#define USART_CR2_ADD_Pos             (24U)                                    \r\n#define USART_CR2_ADD_Msk             (0xFFU << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */\r\n#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */\r\n\r\n/******************  Bit definition for USART_CR3 register  *******************/\r\n#define USART_CR3_EIE_Pos             (0U)                                     \r\n#define USART_CR3_EIE_Msk             (0x1U << USART_CR3_EIE_Pos)              /*!< 0x00000001 */\r\n#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable                         */\r\n#define USART_CR3_IREN_Pos            (1U)                                     \r\n#define USART_CR3_IREN_Msk            (0x1U << USART_CR3_IREN_Pos)             /*!< 0x00000002 */\r\n#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable                               */\r\n#define USART_CR3_IRLP_Pos            (2U)                                     \r\n#define USART_CR3_IRLP_Msk            (0x1U << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */\r\n#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power                                 */\r\n#define USART_CR3_HDSEL_Pos           (3U)                                     \r\n#define USART_CR3_HDSEL_Msk           (0x1U << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */\r\n#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection                          */\r\n#define USART_CR3_NACK_Pos            (4U)                                     \r\n#define USART_CR3_NACK_Msk            (0x1U << USART_CR3_NACK_Pos)             /*!< 0x00000010 */\r\n#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable                          */\r\n#define USART_CR3_SCEN_Pos            (5U)                                     \r\n#define USART_CR3_SCEN_Msk            (0x1U << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */\r\n#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable                          */\r\n#define USART_CR3_DMAR_Pos            (6U)                                     \r\n#define USART_CR3_DMAR_Msk            (0x1U << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */\r\n#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver                            */\r\n#define USART_CR3_DMAT_Pos            (7U)                                     \r\n#define USART_CR3_DMAT_Msk            (0x1U << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */\r\n#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter                         */\r\n#define USART_CR3_RTSE_Pos            (8U)                                     \r\n#define USART_CR3_RTSE_Msk            (0x1U << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */\r\n#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable                                     */\r\n#define USART_CR3_CTSE_Pos            (9U)                                     \r\n#define USART_CR3_CTSE_Msk            (0x1U << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */\r\n#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable                                     */\r\n#define USART_CR3_CTSIE_Pos           (10U)                                    \r\n#define USART_CR3_CTSIE_Msk           (0x1U << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */\r\n#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable                           */\r\n#define USART_CR3_ONEBIT_Pos          (11U)                                    \r\n#define USART_CR3_ONEBIT_Msk          (0x1U << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */\r\n#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable                   */\r\n#define USART_CR3_OVRDIS_Pos          (12U)                                    \r\n#define USART_CR3_OVRDIS_Msk          (0x1U << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */\r\n#define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable                                */\r\n#define USART_CR3_DDRE_Pos            (13U)                                    \r\n#define USART_CR3_DDRE_Msk            (0x1U << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */\r\n#define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error                 */\r\n#define USART_CR3_DEM_Pos             (14U)                                    \r\n#define USART_CR3_DEM_Msk             (0x1U << USART_CR3_DEM_Pos)              /*!< 0x00004000 */\r\n#define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode                             */\r\n#define USART_CR3_DEP_Pos             (15U)                                    \r\n#define USART_CR3_DEP_Msk             (0x1U << USART_CR3_DEP_Pos)              /*!< 0x00008000 */\r\n#define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection               */\r\n#define USART_CR3_SCARCNT_Pos         (17U)                                    \r\n#define USART_CR3_SCARCNT_Msk         (0x7U << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */\r\n#define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */\r\n#define USART_CR3_SCARCNT_0           (0x1U << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */\r\n#define USART_CR3_SCARCNT_1           (0x2U << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */\r\n#define USART_CR3_SCARCNT_2           (0x4U << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */\r\n\r\n/******************  Bit definition for USART_BRR register  *******************/\r\n#define USART_BRR_DIV_FRACTION_Pos    (0U)                                     \r\n#define USART_BRR_DIV_FRACTION_Msk    (0xFU << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */\r\n#define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */\r\n#define USART_BRR_DIV_MANTISSA_Pos    (4U)                                     \r\n#define USART_BRR_DIV_MANTISSA_Msk    (0xFFFU << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */\r\n#define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */\r\n\r\n/******************  Bit definition for USART_GTPR register  ******************/\r\n#define USART_GTPR_PSC_Pos            (0U)                                     \r\n#define USART_GTPR_PSC_Msk            (0xFFU << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */\r\n#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */\r\n#define USART_GTPR_GT_Pos             (8U)                                     \r\n#define USART_GTPR_GT_Msk             (0xFFU << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */\r\n#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */\r\n\r\n\r\n/*******************  Bit definition for USART_RTOR register  *****************/\r\n#define USART_RTOR_RTO_Pos            (0U)                                     \r\n#define USART_RTOR_RTO_Msk            (0xFFFFFFU << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */\r\n#define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */\r\n#define USART_RTOR_BLEN_Pos           (24U)                                    \r\n#define USART_RTOR_BLEN_Msk           (0xFFU << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */\r\n#define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */\r\n\r\n/*******************  Bit definition for USART_RQR register  ******************/\r\n#define USART_RQR_ABRRQ_Pos           (0U)                                     \r\n#define USART_RQR_ABRRQ_Msk           (0x1U << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */\r\n#define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request      */\r\n#define USART_RQR_SBKRQ_Pos           (1U)                                     \r\n#define USART_RQR_SBKRQ_Msk           (0x1U << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */\r\n#define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request          */\r\n#define USART_RQR_MMRQ_Pos            (2U)                                     \r\n#define USART_RQR_MMRQ_Msk            (0x1U << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */\r\n#define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request           */\r\n#define USART_RQR_RXFRQ_Pos           (3U)                                     \r\n#define USART_RQR_RXFRQ_Msk           (0x1U << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */\r\n#define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request  */\r\n#define USART_RQR_TXFRQ_Pos           (4U)                                     \r\n#define USART_RQR_TXFRQ_Msk           (0x1U << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */\r\n#define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */\r\n\r\n/*******************  Bit definition for USART_ISR register  ******************/\r\n#define USART_ISR_PE_Pos              (0U)                                     \r\n#define USART_ISR_PE_Msk              (0x1U << USART_ISR_PE_Pos)               /*!< 0x00000001 */\r\n#define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error                        */\r\n#define USART_ISR_FE_Pos              (1U)                                     \r\n#define USART_ISR_FE_Msk              (0x1U << USART_ISR_FE_Pos)               /*!< 0x00000002 */\r\n#define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error                       */\r\n#define USART_ISR_NE_Pos              (2U)                                     \r\n#define USART_ISR_NE_Msk              (0x1U << USART_ISR_NE_Pos)               /*!< 0x00000004 */\r\n#define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag                 */\r\n#define USART_ISR_ORE_Pos             (3U)                                     \r\n#define USART_ISR_ORE_Msk             (0x1U << USART_ISR_ORE_Pos)              /*!< 0x00000008 */\r\n#define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error                       */\r\n#define USART_ISR_IDLE_Pos            (4U)                                     \r\n#define USART_ISR_IDLE_Msk            (0x1U << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */\r\n#define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected                  */\r\n#define USART_ISR_RXNE_Pos            (5U)                                     \r\n#define USART_ISR_RXNE_Msk            (0x1U << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */\r\n#define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty        */\r\n#define USART_ISR_TC_Pos              (6U)                                     \r\n#define USART_ISR_TC_Msk              (0x1U << USART_ISR_TC_Pos)               /*!< 0x00000040 */\r\n#define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete               */\r\n#define USART_ISR_TXE_Pos             (7U)                                     \r\n#define USART_ISR_TXE_Msk             (0x1U << USART_ISR_TXE_Pos)              /*!< 0x00000080 */\r\n#define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty        */\r\n#define USART_ISR_LBDF_Pos            (8U)                                     \r\n#define USART_ISR_LBDF_Msk            (0x1U << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */\r\n#define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag            */\r\n#define USART_ISR_CTSIF_Pos           (9U)                                     \r\n#define USART_ISR_CTSIF_Msk           (0x1U << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */\r\n#define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag                  */\r\n#define USART_ISR_CTS_Pos             (10U)                                    \r\n#define USART_ISR_CTS_Msk             (0x1U << USART_ISR_CTS_Pos)              /*!< 0x00000400 */\r\n#define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag                            */\r\n#define USART_ISR_RTOF_Pos            (11U)                                    \r\n#define USART_ISR_RTOF_Msk            (0x1U << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */\r\n#define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out                   */\r\n#define USART_ISR_EOBF_Pos            (12U)                                    \r\n#define USART_ISR_EOBF_Msk            (0x1U << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */\r\n#define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag                   */\r\n#define USART_ISR_ABRE_Pos            (14U)                                    \r\n#define USART_ISR_ABRE_Msk            (0x1U << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */\r\n#define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error                */\r\n#define USART_ISR_ABRF_Pos            (15U)                                    \r\n#define USART_ISR_ABRF_Msk            (0x1U << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */\r\n#define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag                 */\r\n#define USART_ISR_BUSY_Pos            (16U)                                    \r\n#define USART_ISR_BUSY_Msk            (0x1U << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */\r\n#define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag                           */\r\n#define USART_ISR_CMF_Pos             (17U)                                    \r\n#define USART_ISR_CMF_Msk             (0x1U << USART_ISR_CMF_Pos)              /*!< 0x00020000 */\r\n#define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag                */\r\n#define USART_ISR_SBKF_Pos            (18U)                                    \r\n#define USART_ISR_SBKF_Msk            (0x1U << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */\r\n#define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag                     */\r\n#define USART_ISR_RWU_Pos             (19U)                                    \r\n#define USART_ISR_RWU_Msk             (0x1U << USART_ISR_RWU_Pos)              /*!< 0x00080000 */\r\n#define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */\r\n#define USART_ISR_TEACK_Pos           (21U)                                    \r\n#define USART_ISR_TEACK_Msk           (0x1U << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */\r\n#define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag    */\r\n/* Legacy define */\r\n#define  USART_ISR_LBD                       USART_ISR_LBDF\r\n\r\n/*******************  Bit definition for USART_ICR register  ******************/\r\n#define USART_ICR_PECF_Pos            (0U)                                     \r\n#define USART_ICR_PECF_Msk            (0x1U << USART_ICR_PECF_Pos)             /*!< 0x00000001 */\r\n#define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag             */\r\n#define USART_ICR_FECF_Pos            (1U)                                     \r\n#define USART_ICR_FECF_Msk            (0x1U << USART_ICR_FECF_Pos)             /*!< 0x00000002 */\r\n#define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag            */\r\n#define USART_ICR_NCF_Pos             (2U)                                     \r\n#define USART_ICR_NCF_Msk             (0x1U << USART_ICR_NCF_Pos)              /*!< 0x00000004 */\r\n#define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag           */\r\n#define USART_ICR_ORECF_Pos           (3U)                                     \r\n#define USART_ICR_ORECF_Msk           (0x1U << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */\r\n#define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag            */\r\n#define USART_ICR_IDLECF_Pos          (4U)                                     \r\n#define USART_ICR_IDLECF_Msk          (0x1U << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */\r\n#define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag       */\r\n#define USART_ICR_TCCF_Pos            (6U)                                     \r\n#define USART_ICR_TCCF_Msk            (0x1U << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */\r\n#define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag    */\r\n#define USART_ICR_LBDCF_Pos           (8U)                                     \r\n#define USART_ICR_LBDCF_Msk           (0x1U << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */\r\n#define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag      */\r\n#define USART_ICR_CTSCF_Pos           (9U)                                     \r\n#define USART_ICR_CTSCF_Msk           (0x1U << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */\r\n#define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag            */\r\n#define USART_ICR_RTOCF_Pos           (11U)                                    \r\n#define USART_ICR_RTOCF_Msk           (0x1U << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */\r\n#define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag        */\r\n#define USART_ICR_EOBCF_Pos           (12U)                                    \r\n#define USART_ICR_EOBCF_Msk           (0x1U << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */\r\n#define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag             */\r\n#define USART_ICR_CMCF_Pos            (17U)                                    \r\n#define USART_ICR_CMCF_Msk            (0x1U << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */\r\n#define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag          */\r\n\r\n/*******************  Bit definition for USART_RDR register  ******************/\r\n#define USART_RDR_RDR_Pos             (0U)                                     \r\n#define USART_RDR_RDR_Msk             (0x1FFU << USART_RDR_RDR_Pos)            /*!< 0x000001FF */\r\n#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */\r\n\r\n/*******************  Bit definition for USART_TDR register  ******************/\r\n#define USART_TDR_TDR_Pos             (0U)                                     \r\n#define USART_TDR_TDR_Msk             (0x1FFU << USART_TDR_TDR_Pos)            /*!< 0x000001FF */\r\n#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                            Window WATCHDOG                                 */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************  Bit definition for WWDG_CR register  ********************/\r\n#define WWDG_CR_T_Pos           (0U)                                           \r\n#define WWDG_CR_T_Msk           (0x7FU << WWDG_CR_T_Pos)                       /*!< 0x0000007F */\r\n#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */\r\n#define WWDG_CR_T_0             (0x01U << WWDG_CR_T_Pos)                       /*!< 0x01 */\r\n#define WWDG_CR_T_1             (0x02U << WWDG_CR_T_Pos)                       /*!< 0x02 */\r\n#define WWDG_CR_T_2             (0x04U << WWDG_CR_T_Pos)                       /*!< 0x04 */\r\n#define WWDG_CR_T_3             (0x08U << WWDG_CR_T_Pos)                       /*!< 0x08 */\r\n#define WWDG_CR_T_4             (0x10U << WWDG_CR_T_Pos)                       /*!< 0x10 */\r\n#define WWDG_CR_T_5             (0x20U << WWDG_CR_T_Pos)                       /*!< 0x20 */\r\n#define WWDG_CR_T_6             (0x40U << WWDG_CR_T_Pos)                       /*!< 0x40 */\r\n\r\n/* Legacy defines */\r\n#define  WWDG_CR_T0                           WWDG_CR_T_0                      /*!<Bit 0 */\r\n#define  WWDG_CR_T1                           WWDG_CR_T_1                      /*!<Bit 1 */\r\n#define  WWDG_CR_T2                           WWDG_CR_T_2                      /*!<Bit 2 */\r\n#define  WWDG_CR_T3                           WWDG_CR_T_3                      /*!<Bit 3 */\r\n#define  WWDG_CR_T4                           WWDG_CR_T_4                      /*!<Bit 4 */\r\n#define  WWDG_CR_T5                           WWDG_CR_T_5                      /*!<Bit 5 */\r\n#define  WWDG_CR_T6                           WWDG_CR_T_6                      /*!<Bit 6 */\r\n\r\n#define WWDG_CR_WDGA_Pos        (7U)                                           \r\n#define WWDG_CR_WDGA_Msk        (0x1U << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */\r\n#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */\r\n\r\n/*******************  Bit definition for WWDG_CFR register  *******************/\r\n#define WWDG_CFR_W_Pos          (0U)                                           \r\n#define WWDG_CFR_W_Msk          (0x7FU << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */\r\n#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */\r\n#define WWDG_CFR_W_0            (0x01U << WWDG_CFR_W_Pos)                      /*!< 0x0001 */\r\n#define WWDG_CFR_W_1            (0x02U << WWDG_CFR_W_Pos)                      /*!< 0x0002 */\r\n#define WWDG_CFR_W_2            (0x04U << WWDG_CFR_W_Pos)                      /*!< 0x0004 */\r\n#define WWDG_CFR_W_3            (0x08U << WWDG_CFR_W_Pos)                      /*!< 0x0008 */\r\n#define WWDG_CFR_W_4            (0x10U << WWDG_CFR_W_Pos)                      /*!< 0x0010 */\r\n#define WWDG_CFR_W_5            (0x20U << WWDG_CFR_W_Pos)                      /*!< 0x0020 */\r\n#define WWDG_CFR_W_6            (0x40U << WWDG_CFR_W_Pos)                      /*!< 0x0040 */\r\n\r\n/* Legacy defines */\r\n#define  WWDG_CFR_W0                         WWDG_CFR_W_0                      /*!<Bit 0 */\r\n#define  WWDG_CFR_W1                         WWDG_CFR_W_1                      /*!<Bit 1 */\r\n#define  WWDG_CFR_W2                         WWDG_CFR_W_2                      /*!<Bit 2 */\r\n#define  WWDG_CFR_W3                         WWDG_CFR_W_3                      /*!<Bit 3 */\r\n#define  WWDG_CFR_W4                         WWDG_CFR_W_4                      /*!<Bit 4 */\r\n#define  WWDG_CFR_W5                         WWDG_CFR_W_5                      /*!<Bit 5 */\r\n#define  WWDG_CFR_W6                         WWDG_CFR_W_6                      /*!<Bit 6 */\r\n\r\n#define WWDG_CFR_WDGTB_Pos      (7U)                                           \r\n#define WWDG_CFR_WDGTB_Msk      (0x3U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */\r\n#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */\r\n#define WWDG_CFR_WDGTB_0        (0x1U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0080 */\r\n#define WWDG_CFR_WDGTB_1        (0x2U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0100 */\r\n\r\n/* Legacy defines */\r\n#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0                  /*!<Bit 0 */\r\n#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1                  /*!<Bit 1 */\r\n\r\n#define WWDG_CFR_EWI_Pos        (9U)                                           \r\n#define WWDG_CFR_EWI_Msk        (0x1U << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */\r\n#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */\r\n\r\n/*******************  Bit definition for WWDG_SR register  ********************/\r\n#define WWDG_SR_EWIF_Pos        (0U)                                           \r\n#define WWDG_SR_EWIF_Msk        (0x1U << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */\r\n#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                DBG                                         */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bit definition for DBGMCU_IDCODE register  *************/\r\n#define DBGMCU_IDCODE_DEV_ID_Pos                     (0U)                      \r\n#define DBGMCU_IDCODE_DEV_ID_Msk                     (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */\r\n#define DBGMCU_IDCODE_DEV_ID                         DBGMCU_IDCODE_DEV_ID_Msk  \r\n#define DBGMCU_IDCODE_REV_ID_Pos                     (16U)                     \r\n#define DBGMCU_IDCODE_REV_ID_Msk                     (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */\r\n#define DBGMCU_IDCODE_REV_ID                         DBGMCU_IDCODE_REV_ID_Msk  \r\n\r\n/********************  Bit definition for DBGMCU_CR register  *****************/\r\n#define DBGMCU_CR_DBG_SLEEP_Pos                      (0U)                      \r\n#define DBGMCU_CR_DBG_SLEEP_Msk                      (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */\r\n#define DBGMCU_CR_DBG_SLEEP                          DBGMCU_CR_DBG_SLEEP_Msk   \r\n#define DBGMCU_CR_DBG_STOP_Pos                       (1U)                      \r\n#define DBGMCU_CR_DBG_STOP_Msk                       (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */\r\n#define DBGMCU_CR_DBG_STOP                           DBGMCU_CR_DBG_STOP_Msk    \r\n#define DBGMCU_CR_DBG_STANDBY_Pos                    (2U)                      \r\n#define DBGMCU_CR_DBG_STANDBY_Msk                    (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */\r\n#define DBGMCU_CR_DBG_STANDBY                        DBGMCU_CR_DBG_STANDBY_Msk \r\n#define DBGMCU_CR_TRACE_IOEN_Pos                     (5U)                      \r\n#define DBGMCU_CR_TRACE_IOEN_Msk                     (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */\r\n#define DBGMCU_CR_TRACE_IOEN                         DBGMCU_CR_TRACE_IOEN_Msk  \r\n\r\n#define DBGMCU_CR_TRACE_MODE_Pos                     (6U)                      \r\n#define DBGMCU_CR_TRACE_MODE_Msk                     (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */\r\n#define DBGMCU_CR_TRACE_MODE                         DBGMCU_CR_TRACE_MODE_Msk  \r\n#define DBGMCU_CR_TRACE_MODE_0                       (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */\r\n#define DBGMCU_CR_TRACE_MODE_1                       (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */\r\n\r\n/********************  Bit definition for DBGMCU_APB1_FZ register  ************/\r\n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos             (0U)                      \r\n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */\r\n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP                 DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk \r\n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos             (1U)                      \r\n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */\r\n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP                 DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk \r\n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos             (2U)                      \r\n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */\r\n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP                 DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk \r\n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos             (3U)                      \r\n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */\r\n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP                 DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk \r\n#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos             (4U)                      \r\n#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */\r\n#define DBGMCU_APB1_FZ_DBG_TIM6_STOP                 DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk \r\n#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos             (5U)                      \r\n#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */\r\n#define DBGMCU_APB1_FZ_DBG_TIM7_STOP                 DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk \r\n#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos            (6U)                      \r\n#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk            (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */\r\n#define DBGMCU_APB1_FZ_DBG_TIM12_STOP                DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk \r\n#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos            (7U)                      \r\n#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk            (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */\r\n#define DBGMCU_APB1_FZ_DBG_TIM13_STOP                DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk \r\n#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos            (8U)                      \r\n#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk            (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */\r\n#define DBGMCU_APB1_FZ_DBG_TIM14_STOP                DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk \r\n#define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Pos           (9U)                      \r\n#define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Msk           (0x1U << DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Pos) /*!< 0x00000200 */\r\n#define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP               DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Msk \r\n#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos              (10U)                     \r\n#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk              (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */\r\n#define DBGMCU_APB1_FZ_DBG_RTC_STOP                  DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk \r\n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos             (11U)                     \r\n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */\r\n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP                 DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk \r\n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos             (12U)                     \r\n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */\r\n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP                 DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk \r\n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos    (21U)                     \r\n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk    (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */\r\n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk \r\n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos    (22U)                     \r\n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk    (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */\r\n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk \r\n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos    (23U)                     \r\n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk    (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */\r\n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk \r\n#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos             (25U)                     \r\n#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */\r\n#define DBGMCU_APB1_FZ_DBG_CAN1_STOP                 DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk \r\n#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos             (26U)                     \r\n#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */\r\n#define DBGMCU_APB1_FZ_DBG_CAN2_STOP                 DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk \r\n\r\n/********************  Bit definition for DBGMCU_APB2_FZ register  ************/\r\n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos             (0U)                      \r\n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk             (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */\r\n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP                 DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk \r\n#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos             (1U)                      \r\n#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk             (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */\r\n#define DBGMCU_APB2_FZ_DBG_TIM8_STOP                 DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk \r\n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos             (16U)                     \r\n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk             (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */\r\n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP                 DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk \r\n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos            (17U)                     \r\n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk            (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */\r\n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP                DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk \r\n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos            (18U)                     \r\n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk            (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */\r\n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP                DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk \r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                Ethernet MAC Registers bits definitions                     */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/* Bit definition for Ethernet MAC Control Register register */\r\n#define ETH_MACCR_WD_Pos                              (23U)                    \r\n#define ETH_MACCR_WD_Msk                              (0x1U << ETH_MACCR_WD_Pos) /*!< 0x00800000 */\r\n#define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */\r\n#define ETH_MACCR_JD_Pos                              (22U)                    \r\n#define ETH_MACCR_JD_Msk                              (0x1U << ETH_MACCR_JD_Pos) /*!< 0x00400000 */\r\n#define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */\r\n#define ETH_MACCR_IFG_Pos                             (17U)                    \r\n#define ETH_MACCR_IFG_Msk                             (0x7U << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */\r\n#define ETH_MACCR_IFG                                 ETH_MACCR_IFG_Msk        /* Inter-frame gap */\r\n#define ETH_MACCR_IFG_96Bit                           0x00000000U              /* Minimum IFG between frames during transmission is 96Bit */\r\n#define ETH_MACCR_IFG_88Bit                           0x00020000U              /* Minimum IFG between frames during transmission is 88Bit */\r\n#define ETH_MACCR_IFG_80Bit                           0x00040000U              /* Minimum IFG between frames during transmission is 80Bit */\r\n#define ETH_MACCR_IFG_72Bit                           0x00060000U              /* Minimum IFG between frames during transmission is 72Bit */\r\n#define ETH_MACCR_IFG_64Bit                           0x00080000U              /* Minimum IFG between frames during transmission is 64Bit */\r\n#define ETH_MACCR_IFG_56Bit                           0x000A0000U              /* Minimum IFG between frames during transmission is 56Bit */\r\n#define ETH_MACCR_IFG_48Bit                           0x000C0000U              /* Minimum IFG between frames during transmission is 48Bit */\r\n#define ETH_MACCR_IFG_40Bit                           0x000E0000U              /* Minimum IFG between frames during transmission is 40Bit */\r\n#define ETH_MACCR_CSD_Pos                             (16U)                    \r\n#define ETH_MACCR_CSD_Msk                             (0x1U << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */\r\n#define ETH_MACCR_CSD                                 ETH_MACCR_CSD_Msk        /* Carrier sense disable (during transmission) */\r\n#define ETH_MACCR_FES_Pos                             (14U)                    \r\n#define ETH_MACCR_FES_Msk                             (0x1U << ETH_MACCR_FES_Pos) /*!< 0x00004000 */\r\n#define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* Fast ethernet speed */\r\n#define ETH_MACCR_ROD_Pos                             (13U)                    \r\n#define ETH_MACCR_ROD_Msk                             (0x1U << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */\r\n#define ETH_MACCR_ROD                                 ETH_MACCR_ROD_Msk        /* Receive own disable */\r\n#define ETH_MACCR_LM_Pos                              (12U)                    \r\n#define ETH_MACCR_LM_Msk                              (0x1U << ETH_MACCR_LM_Pos) /*!< 0x00001000 */\r\n#define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */\r\n#define ETH_MACCR_DM_Pos                              (11U)                    \r\n#define ETH_MACCR_DM_Msk                              (0x1U << ETH_MACCR_DM_Pos) /*!< 0x00000800 */\r\n#define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */\r\n#define ETH_MACCR_IPCO_Pos                            (10U)                    \r\n#define ETH_MACCR_IPCO_Msk                            (0x1U << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */\r\n#define ETH_MACCR_IPCO                                ETH_MACCR_IPCO_Msk       /* IP Checksum offload */\r\n#define ETH_MACCR_RD_Pos                              (9U)                     \r\n#define ETH_MACCR_RD_Msk                              (0x1U << ETH_MACCR_RD_Pos) /*!< 0x00000200 */\r\n#define ETH_MACCR_RD                                  ETH_MACCR_RD_Msk         /* Retry disable */\r\n#define ETH_MACCR_APCS_Pos                            (7U)                     \r\n#define ETH_MACCR_APCS_Msk                            (0x1U << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */\r\n#define ETH_MACCR_APCS                                ETH_MACCR_APCS_Msk       /* Automatic Pad/CRC stripping */\r\n#define ETH_MACCR_BL_Pos                              (5U)                     \r\n#define ETH_MACCR_BL_Msk                              (0x3U << ETH_MACCR_BL_Pos) /*!< 0x00000060 */\r\n#define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit: random integer number (r) of slot time delays before rescheduling\r\n                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */\r\n#define ETH_MACCR_BL_10                               0x00000000U              /* k = min (n, 10) */\r\n#define ETH_MACCR_BL_8                                0x00000020U              /* k = min (n, 8) */\r\n#define ETH_MACCR_BL_4                                0x00000040U              /* k = min (n, 4) */\r\n#define ETH_MACCR_BL_1                                0x00000060U              /* k = min (n, 1) */\r\n#define ETH_MACCR_DC_Pos                              (4U)                     \r\n#define ETH_MACCR_DC_Msk                              (0x1U << ETH_MACCR_DC_Pos) /*!< 0x00000010 */\r\n#define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */\r\n#define ETH_MACCR_TE_Pos                              (3U)                     \r\n#define ETH_MACCR_TE_Msk                              (0x1U << ETH_MACCR_TE_Pos) /*!< 0x00000008 */\r\n#define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */\r\n#define ETH_MACCR_RE_Pos                              (2U)                     \r\n#define ETH_MACCR_RE_Msk                              (0x1U << ETH_MACCR_RE_Pos) /*!< 0x00000004 */\r\n#define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */\r\n\r\n/* Bit definition for Ethernet MAC Frame Filter Register */\r\n#define ETH_MACFFR_RA_Pos                             (31U)                    \r\n#define ETH_MACFFR_RA_Msk                             (0x1U << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */\r\n#define ETH_MACFFR_RA                                 ETH_MACFFR_RA_Msk        /* Receive all */\r\n#define ETH_MACFFR_HPF_Pos                            (10U)                    \r\n#define ETH_MACFFR_HPF_Msk                            (0x1U << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */\r\n#define ETH_MACFFR_HPF                                ETH_MACFFR_HPF_Msk       /* Hash or perfect filter */\r\n#define ETH_MACFFR_SAF_Pos                            (9U)                     \r\n#define ETH_MACFFR_SAF_Msk                            (0x1U << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */\r\n#define ETH_MACFFR_SAF                                ETH_MACFFR_SAF_Msk       /* Source address filter enable */\r\n#define ETH_MACFFR_SAIF_Pos                           (8U)                     \r\n#define ETH_MACFFR_SAIF_Msk                           (0x1U << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */\r\n#define ETH_MACFFR_SAIF                               ETH_MACFFR_SAIF_Msk      /* SA inverse filtering */\r\n#define ETH_MACFFR_PCF_Pos                            (6U)                     \r\n#define ETH_MACFFR_PCF_Msk                            (0x3U << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */\r\n#define ETH_MACFFR_PCF                                ETH_MACFFR_PCF_Msk       /* Pass control frames: 3 cases */\r\n#define ETH_MACFFR_PCF_BlockAll_Pos                   (6U)                     \r\n#define ETH_MACFFR_PCF_BlockAll_Msk                   (0x1U << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */\r\n#define ETH_MACFFR_PCF_BlockAll                       ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */\r\n#define ETH_MACFFR_PCF_ForwardAll_Pos                 (7U)                     \r\n#define ETH_MACFFR_PCF_ForwardAll_Msk                 (0x1U << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */\r\n#define ETH_MACFFR_PCF_ForwardAll                     ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */\r\n#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos    (6U)                     \r\n#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk    (0x3U << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */\r\n#define ETH_MACFFR_PCF_ForwardPassedAddrFilter        ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */\r\n#define ETH_MACFFR_BFD_Pos                            (5U)                     \r\n#define ETH_MACFFR_BFD_Msk                            (0x1U << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */\r\n#define ETH_MACFFR_BFD                                ETH_MACFFR_BFD_Msk       /* Broadcast frame disable */\r\n#define ETH_MACFFR_PAM_Pos                            (4U)                     \r\n#define ETH_MACFFR_PAM_Msk                            (0x1U << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */\r\n#define ETH_MACFFR_PAM                                ETH_MACFFR_PAM_Msk       /* Pass all mutlicast */\r\n#define ETH_MACFFR_DAIF_Pos                           (3U)                     \r\n#define ETH_MACFFR_DAIF_Msk                           (0x1U << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */\r\n#define ETH_MACFFR_DAIF                               ETH_MACFFR_DAIF_Msk      /* DA Inverse filtering */\r\n#define ETH_MACFFR_HM_Pos                             (2U)                     \r\n#define ETH_MACFFR_HM_Msk                             (0x1U << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */\r\n#define ETH_MACFFR_HM                                 ETH_MACFFR_HM_Msk        /* Hash multicast */\r\n#define ETH_MACFFR_HU_Pos                             (1U)                     \r\n#define ETH_MACFFR_HU_Msk                             (0x1U << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */\r\n#define ETH_MACFFR_HU                                 ETH_MACFFR_HU_Msk        /* Hash unicast */\r\n#define ETH_MACFFR_PM_Pos                             (0U)                     \r\n#define ETH_MACFFR_PM_Msk                             (0x1U << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */\r\n#define ETH_MACFFR_PM                                 ETH_MACFFR_PM_Msk        /* Promiscuous mode */\r\n\r\n/* Bit definition for Ethernet MAC Hash Table High Register */\r\n#define ETH_MACHTHR_HTH_Pos                           (0U)                     \r\n#define ETH_MACHTHR_HTH_Msk                           (0xFFFFFFFFU << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACHTHR_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */\r\n\r\n/* Bit definition for Ethernet MAC Hash Table Low Register */\r\n#define ETH_MACHTLR_HTL_Pos                           (0U)                     \r\n#define ETH_MACHTLR_HTL_Msk                           (0xFFFFFFFFU << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACHTLR_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */\r\n\r\n/* Bit definition for Ethernet MAC MII Address Register */\r\n#define ETH_MACMIIAR_PA_Pos                           (11U)                    \r\n#define ETH_MACMIIAR_PA_Msk                           (0x1FU << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */\r\n#define ETH_MACMIIAR_PA                               ETH_MACMIIAR_PA_Msk      /* Physical layer address */\r\n#define ETH_MACMIIAR_MR_Pos                           (6U)                     \r\n#define ETH_MACMIIAR_MR_Msk                           (0x1FU << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */\r\n#define ETH_MACMIIAR_MR                               ETH_MACMIIAR_MR_Msk      /* MII register in the selected PHY */\r\n#define ETH_MACMIIAR_CR_Pos                           (2U)                     \r\n#define ETH_MACMIIAR_CR_Msk                           (0x7U << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */\r\n#define ETH_MACMIIAR_CR                               ETH_MACMIIAR_CR_Msk      /* CR clock range: 6 cases */\r\n#define ETH_MACMIIAR_CR_Div42                         0x00000000U              /* HCLK:60-100 MHz; MDC clock= HCLK/42 */\r\n#define ETH_MACMIIAR_CR_Div62_Pos                     (2U)                     \r\n#define ETH_MACMIIAR_CR_Div62_Msk                     (0x1U << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */\r\n#define ETH_MACMIIAR_CR_Div62                         ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */\r\n#define ETH_MACMIIAR_CR_Div16_Pos                     (3U)                     \r\n#define ETH_MACMIIAR_CR_Div16_Msk                     (0x1U << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */\r\n#define ETH_MACMIIAR_CR_Div16                         ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */\r\n#define ETH_MACMIIAR_CR_Div26_Pos                     (2U)                     \r\n#define ETH_MACMIIAR_CR_Div26_Msk                     (0x3U << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */\r\n#define ETH_MACMIIAR_CR_Div26                         ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */\r\n#define ETH_MACMIIAR_CR_Div102_Pos                    (4U)                     \r\n#define ETH_MACMIIAR_CR_Div102_Msk                    (0x1U << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */\r\n#define ETH_MACMIIAR_CR_Div102                        ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */\r\n#define ETH_MACMIIAR_MW_Pos                           (1U)                     \r\n#define ETH_MACMIIAR_MW_Msk                           (0x1U << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */\r\n#define ETH_MACMIIAR_MW                               ETH_MACMIIAR_MW_Msk      /* MII write */\r\n#define ETH_MACMIIAR_MB_Pos                           (0U)                     \r\n#define ETH_MACMIIAR_MB_Msk                           (0x1U << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */\r\n#define ETH_MACMIIAR_MB                               ETH_MACMIIAR_MB_Msk      /* MII busy */\r\n\r\n/* Bit definition for Ethernet MAC MII Data Register */\r\n#define ETH_MACMIIDR_MD_Pos                           (0U)                     \r\n#define ETH_MACMIIDR_MD_Msk                           (0xFFFFU << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */\r\n#define ETH_MACMIIDR_MD                               ETH_MACMIIDR_MD_Msk      /* MII data: read/write data from/to PHY */\r\n\r\n/* Bit definition for Ethernet MAC Flow Control Register */\r\n#define ETH_MACFCR_PT_Pos                             (16U)                    \r\n#define ETH_MACFCR_PT_Msk                             (0xFFFFU << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */\r\n#define ETH_MACFCR_PT                                 ETH_MACFCR_PT_Msk        /* Pause time */\r\n#define ETH_MACFCR_ZQPD_Pos                           (7U)                     \r\n#define ETH_MACFCR_ZQPD_Msk                           (0x1U << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */\r\n#define ETH_MACFCR_ZQPD                               ETH_MACFCR_ZQPD_Msk      /* Zero-quanta pause disable */\r\n#define ETH_MACFCR_PLT_Pos                            (4U)                     \r\n#define ETH_MACFCR_PLT_Msk                            (0x3U << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */\r\n#define ETH_MACFCR_PLT                                ETH_MACFCR_PLT_Msk       /* Pause low threshold: 4 cases */\r\n#define ETH_MACFCR_PLT_Minus4                         0x00000000U              /* Pause time minus 4 slot times */\r\n#define ETH_MACFCR_PLT_Minus28_Pos                    (4U)                     \r\n#define ETH_MACFCR_PLT_Minus28_Msk                    (0x1U << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */\r\n#define ETH_MACFCR_PLT_Minus28                        ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */\r\n#define ETH_MACFCR_PLT_Minus144_Pos                   (5U)                     \r\n#define ETH_MACFCR_PLT_Minus144_Msk                   (0x1U << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */\r\n#define ETH_MACFCR_PLT_Minus144                       ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */\r\n#define ETH_MACFCR_PLT_Minus256_Pos                   (4U)                     \r\n#define ETH_MACFCR_PLT_Minus256_Msk                   (0x3U << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */\r\n#define ETH_MACFCR_PLT_Minus256                       ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */\r\n#define ETH_MACFCR_UPFD_Pos                           (3U)                     \r\n#define ETH_MACFCR_UPFD_Msk                           (0x1U << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */\r\n#define ETH_MACFCR_UPFD                               ETH_MACFCR_UPFD_Msk      /* Unicast pause frame detect */\r\n#define ETH_MACFCR_RFCE_Pos                           (2U)                     \r\n#define ETH_MACFCR_RFCE_Msk                           (0x1U << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */\r\n#define ETH_MACFCR_RFCE                               ETH_MACFCR_RFCE_Msk      /* Receive flow control enable */\r\n#define ETH_MACFCR_TFCE_Pos                           (1U)                     \r\n#define ETH_MACFCR_TFCE_Msk                           (0x1U << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */\r\n#define ETH_MACFCR_TFCE                               ETH_MACFCR_TFCE_Msk      /* Transmit flow control enable */\r\n#define ETH_MACFCR_FCBBPA_Pos                         (0U)                     \r\n#define ETH_MACFCR_FCBBPA_Msk                         (0x1U << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */\r\n#define ETH_MACFCR_FCBBPA                             ETH_MACFCR_FCBBPA_Msk    /* Flow control busy/backpressure activate */\r\n\r\n/* Bit definition for Ethernet MAC VLAN Tag Register */\r\n#define ETH_MACVLANTR_VLANTC_Pos                      (16U)                    \r\n#define ETH_MACVLANTR_VLANTC_Msk                      (0x1U << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */\r\n#define ETH_MACVLANTR_VLANTC                          ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */\r\n#define ETH_MACVLANTR_VLANTI_Pos                      (0U)                     \r\n#define ETH_MACVLANTR_VLANTI_Msk                      (0xFFFFU << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */\r\n#define ETH_MACVLANTR_VLANTI                          ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */\r\n\r\n/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */\r\n#define ETH_MACRWUFFR_D_Pos                           (0U)                     \r\n#define ETH_MACRWUFFR_D_Msk                           (0xFFFFFFFFU << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACRWUFFR_D                               ETH_MACRWUFFR_D_Msk      /* Wake-up frame filter register data */\r\n/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.\r\n   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */\r\n/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask\r\n   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask\r\n   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask\r\n   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask\r\n   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -\r\n                              RSVD - Filter1 Command - RSVD - Filter0 Command\r\n   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset\r\n   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16\r\n   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */\r\n\r\n/* Bit definition for Ethernet MAC PMT Control and Status Register */\r\n#define ETH_MACPMTCSR_WFFRPR_Pos                      (31U)                    \r\n#define ETH_MACPMTCSR_WFFRPR_Msk                      (0x1U << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */\r\n#define ETH_MACPMTCSR_WFFRPR                          ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */\r\n#define ETH_MACPMTCSR_GU_Pos                          (9U)                     \r\n#define ETH_MACPMTCSR_GU_Msk                          (0x1U << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */\r\n#define ETH_MACPMTCSR_GU                              ETH_MACPMTCSR_GU_Msk     /* Global Unicast */\r\n#define ETH_MACPMTCSR_WFR_Pos                         (6U)                     \r\n#define ETH_MACPMTCSR_WFR_Msk                         (0x1U << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */\r\n#define ETH_MACPMTCSR_WFR                             ETH_MACPMTCSR_WFR_Msk    /* Wake-Up Frame Received */\r\n#define ETH_MACPMTCSR_MPR_Pos                         (5U)                     \r\n#define ETH_MACPMTCSR_MPR_Msk                         (0x1U << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */\r\n#define ETH_MACPMTCSR_MPR                             ETH_MACPMTCSR_MPR_Msk    /* Magic Packet Received */\r\n#define ETH_MACPMTCSR_WFE_Pos                         (2U)                     \r\n#define ETH_MACPMTCSR_WFE_Msk                         (0x1U << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */\r\n#define ETH_MACPMTCSR_WFE                             ETH_MACPMTCSR_WFE_Msk    /* Wake-Up Frame Enable */\r\n#define ETH_MACPMTCSR_MPE_Pos                         (1U)                     \r\n#define ETH_MACPMTCSR_MPE_Msk                         (0x1U << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */\r\n#define ETH_MACPMTCSR_MPE                             ETH_MACPMTCSR_MPE_Msk    /* Magic Packet Enable */\r\n#define ETH_MACPMTCSR_PD_Pos                          (0U)                     \r\n#define ETH_MACPMTCSR_PD_Msk                          (0x1U << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */\r\n#define ETH_MACPMTCSR_PD                              ETH_MACPMTCSR_PD_Msk     /* Power Down */\r\n\r\n/* Bit definition for Ethernet MAC debug Register */\r\n#define ETH_MACDBGR_TFF_Pos                           (25U)                    \r\n#define ETH_MACDBGR_TFF_Msk                           (0x1U << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */\r\n#define ETH_MACDBGR_TFF                               ETH_MACDBGR_TFF_Msk      /* Tx FIFO full                                                            */\r\n#define ETH_MACDBGR_TFNE_Pos                          (24U)                    \r\n#define ETH_MACDBGR_TFNE_Msk                          (0x1U << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */\r\n#define ETH_MACDBGR_TFNE                              ETH_MACDBGR_TFNE_Msk     /* Tx FIFO not empty                                                       */\r\n#define ETH_MACDBGR_TPWA_Pos                          (22U)                    \r\n#define ETH_MACDBGR_TPWA_Msk                          (0x1U << ETH_MACDBGR_TPWA_Pos) /*!< 0x00400000 */\r\n#define ETH_MACDBGR_TPWA                              ETH_MACDBGR_TPWA_Msk     /* Tx FIFO write active                                                    */\r\n#define ETH_MACDBGR_TFRS_Pos                          (20U)                    \r\n#define ETH_MACDBGR_TFRS_Msk                          (0x3U << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */\r\n#define ETH_MACDBGR_TFRS                              ETH_MACDBGR_TFRS_Msk     /* Tx FIFO read status mask                                                */\r\n#define ETH_MACDBGR_TFRS_WRITING_Pos                  (20U)                    \r\n#define ETH_MACDBGR_TFRS_WRITING_Msk                  (0x3U << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */\r\n#define ETH_MACDBGR_TFRS_WRITING                      ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO                    */\r\n#define ETH_MACDBGR_TFRS_WAITING_Pos                  (21U)                    \r\n#define ETH_MACDBGR_TFRS_WAITING_Msk                  (0x1U << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */\r\n#define ETH_MACDBGR_TFRS_WAITING                      ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter                               */\r\n#define ETH_MACDBGR_TFRS_READ_Pos                     (20U)                    \r\n#define ETH_MACDBGR_TFRS_READ_Msk                     (0x1U << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */\r\n#define ETH_MACDBGR_TFRS_READ                         ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter)                   */\r\n#define ETH_MACDBGR_TFRS_IDLE                         0x00000000U              /* Idle state                                                              */\r\n#define ETH_MACDBGR_MTP_Pos                           (19U)                    \r\n#define ETH_MACDBGR_MTP_Msk                           (0x1U << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */\r\n#define ETH_MACDBGR_MTP                               ETH_MACDBGR_MTP_Msk      /* MAC transmitter in pause                                                */\r\n#define ETH_MACDBGR_MTFCS_Pos                         (17U)                    \r\n#define ETH_MACDBGR_MTFCS_Msk                         (0x3U << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */\r\n#define ETH_MACDBGR_MTFCS                             ETH_MACDBGR_MTFCS_Msk    /* MAC transmit frame controller status mask                               */\r\n#define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos            (17U)                    \r\n#define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk            (0x3U << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */\r\n#define ETH_MACDBGR_MTFCS_TRANSFERRING                ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission                               */\r\n#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos           (18U)                    \r\n#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk           (0x1U << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */\r\n#define ETH_MACDBGR_MTFCS_GENERATINGPCF               ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */\r\n#define ETH_MACDBGR_MTFCS_WAITING_Pos                 (17U)                    \r\n#define ETH_MACDBGR_MTFCS_WAITING_Msk                 (0x1U << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */\r\n#define ETH_MACDBGR_MTFCS_WAITING                     ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over   */\r\n#define ETH_MACDBGR_MTFCS_IDLE                        0x00000000U              /* Idle                                                                    */\r\n#define ETH_MACDBGR_MMTEA_Pos                         (16U)                    \r\n#define ETH_MACDBGR_MMTEA_Msk                         (0x1U << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */\r\n#define ETH_MACDBGR_MMTEA                             ETH_MACDBGR_MMTEA_Msk    /* MAC MII transmit engine active                                          */\r\n#define ETH_MACDBGR_RFFL_Pos                          (8U)                     \r\n#define ETH_MACDBGR_RFFL_Msk                          (0x3U << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */\r\n#define ETH_MACDBGR_RFFL                              ETH_MACDBGR_RFFL_Msk     /* Rx FIFO fill level mask                                                 */\r\n#define ETH_MACDBGR_RFFL_FULL_Pos                     (8U)                     \r\n#define ETH_MACDBGR_RFFL_FULL_Msk                     (0x3U << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */\r\n#define ETH_MACDBGR_RFFL_FULL                         ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full                                                             */\r\n#define ETH_MACDBGR_RFFL_ABOVEFCT_Pos                 (9U)                     \r\n#define ETH_MACDBGR_RFFL_ABOVEFCT_Msk                 (0x1U << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */\r\n#define ETH_MACDBGR_RFFL_ABOVEFCT                     ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold                 */\r\n#define ETH_MACDBGR_RFFL_BELOWFCT_Pos                 (8U)                     \r\n#define ETH_MACDBGR_RFFL_BELOWFCT_Msk                 (0x1U << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */\r\n#define ETH_MACDBGR_RFFL_BELOWFCT                     ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold              */\r\n#define ETH_MACDBGR_RFFL_EMPTY                        0x00000000U              /* RxFIFO empty                                                            */\r\n#define ETH_MACDBGR_RFRCS_Pos                         (5U)                     \r\n#define ETH_MACDBGR_RFRCS_Msk                         (0x3U << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */\r\n#define ETH_MACDBGR_RFRCS                             ETH_MACDBGR_RFRCS_Msk    /* Rx FIFO read controller status mask                                     */\r\n#define ETH_MACDBGR_RFRCS_FLUSHING_Pos                (5U)                     \r\n#define ETH_MACDBGR_RFRCS_FLUSHING_Msk                (0x3U << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */\r\n#define ETH_MACDBGR_RFRCS_FLUSHING                    ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status                                      */\r\n#define ETH_MACDBGR_RFRCS_STATUSREADING_Pos           (6U)                     \r\n#define ETH_MACDBGR_RFRCS_STATUSREADING_Msk           (0x1U << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */\r\n#define ETH_MACDBGR_RFRCS_STATUSREADING               ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp)                                    */\r\n#define ETH_MACDBGR_RFRCS_DATAREADING_Pos             (5U)                     \r\n#define ETH_MACDBGR_RFRCS_DATAREADING_Msk             (0x1U << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */\r\n#define ETH_MACDBGR_RFRCS_DATAREADING                 ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data                                                      */\r\n#define ETH_MACDBGR_RFRCS_IDLE                        0x00000000U              /* IDLE state                                                              */\r\n#define ETH_MACDBGR_RFWRA_Pos                         (4U)                     \r\n#define ETH_MACDBGR_RFWRA_Msk                         (0x1U << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */\r\n#define ETH_MACDBGR_RFWRA                             ETH_MACDBGR_RFWRA_Msk    /* Rx FIFO write controller active                                         */\r\n#define ETH_MACDBGR_MSFRWCS_Pos                       (1U)                     \r\n#define ETH_MACDBGR_MSFRWCS_Msk                       (0x3U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */\r\n#define ETH_MACDBGR_MSFRWCS                           ETH_MACDBGR_MSFRWCS_Msk  /* MAC small FIFO read / write controllers status  mask                    */\r\n#define ETH_MACDBGR_MSFRWCS_1                         (0x2U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */\r\n#define ETH_MACDBGR_MSFRWCS_0                         (0x1U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */\r\n#define ETH_MACDBGR_MMRPEA_Pos                        (0U)                     \r\n#define ETH_MACDBGR_MMRPEA_Msk                        (0x1U << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */\r\n#define ETH_MACDBGR_MMRPEA                            ETH_MACDBGR_MMRPEA_Msk   /* MAC MII receive protocol engine active                                  */\r\n\r\n/* Bit definition for Ethernet MAC Status Register */\r\n#define ETH_MACSR_TSTS_Pos                            (9U)                     \r\n#define ETH_MACSR_TSTS_Msk                            (0x1U << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */\r\n#define ETH_MACSR_TSTS                                ETH_MACSR_TSTS_Msk       /* Time stamp trigger status */\r\n#define ETH_MACSR_MMCTS_Pos                           (6U)                     \r\n#define ETH_MACSR_MMCTS_Msk                           (0x1U << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */\r\n#define ETH_MACSR_MMCTS                               ETH_MACSR_MMCTS_Msk      /* MMC transmit status */\r\n#define ETH_MACSR_MMMCRS_Pos                          (5U)                     \r\n#define ETH_MACSR_MMMCRS_Msk                          (0x1U << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */\r\n#define ETH_MACSR_MMMCRS                              ETH_MACSR_MMMCRS_Msk     /* MMC receive status */\r\n#define ETH_MACSR_MMCS_Pos                            (4U)                     \r\n#define ETH_MACSR_MMCS_Msk                            (0x1U << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */\r\n#define ETH_MACSR_MMCS                                ETH_MACSR_MMCS_Msk       /* MMC status */\r\n#define ETH_MACSR_PMTS_Pos                            (3U)                     \r\n#define ETH_MACSR_PMTS_Msk                            (0x1U << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */\r\n#define ETH_MACSR_PMTS                                ETH_MACSR_PMTS_Msk       /* PMT status */\r\n\r\n/* Bit definition for Ethernet MAC Interrupt Mask Register */\r\n#define ETH_MACIMR_TSTIM_Pos                          (9U)                     \r\n#define ETH_MACIMR_TSTIM_Msk                          (0x1U << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */\r\n#define ETH_MACIMR_TSTIM                              ETH_MACIMR_TSTIM_Msk     /* Time stamp trigger interrupt mask */\r\n#define ETH_MACIMR_PMTIM_Pos                          (3U)                     \r\n#define ETH_MACIMR_PMTIM_Msk                          (0x1U << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */\r\n#define ETH_MACIMR_PMTIM                              ETH_MACIMR_PMTIM_Msk     /* PMT interrupt mask */\r\n\r\n/* Bit definition for Ethernet MAC Address0 High Register */\r\n#define ETH_MACA0HR_MACA0H_Pos                        (0U)                     \r\n#define ETH_MACA0HR_MACA0H_Msk                        (0xFFFFU << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */\r\n#define ETH_MACA0HR_MACA0H                            ETH_MACA0HR_MACA0H_Msk   /* MAC address0 high */\r\n\r\n/* Bit definition for Ethernet MAC Address0 Low Register */\r\n#define ETH_MACA0LR_MACA0L_Pos                        (0U)                     \r\n#define ETH_MACA0LR_MACA0L_Msk                        (0xFFFFFFFFU << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACA0LR_MACA0L                            ETH_MACA0LR_MACA0L_Msk   /* MAC address0 low */\r\n\r\n/* Bit definition for Ethernet MAC Address1 High Register */\r\n#define ETH_MACA1HR_AE_Pos                            (31U)                    \r\n#define ETH_MACA1HR_AE_Msk                            (0x1U << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */\r\n#define ETH_MACA1HR_AE                                ETH_MACA1HR_AE_Msk       /* Address enable */\r\n#define ETH_MACA1HR_SA_Pos                            (30U)                    \r\n#define ETH_MACA1HR_SA_Msk                            (0x1U << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */\r\n#define ETH_MACA1HR_SA                                ETH_MACA1HR_SA_Msk       /* Source address */\r\n#define ETH_MACA1HR_MBC_Pos                           (24U)                    \r\n#define ETH_MACA1HR_MBC_Msk                           (0x3FU << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */\r\n#define ETH_MACA1HR_MBC                               ETH_MACA1HR_MBC_Msk      /* Mask byte control: bits to mask for comparison of the MAC Address bytes */\r\n#define ETH_MACA1HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */\r\n#define ETH_MACA1HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0] */\r\n#define ETH_MACA1HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */\r\n#define ETH_MACA1HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */\r\n#define ETH_MACA1HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8] */\r\n#define ETH_MACA1HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [7:0] */\r\n#define ETH_MACA1HR_MACA1H_Pos                        (0U)                     \r\n#define ETH_MACA1HR_MACA1H_Msk                        (0xFFFFU << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */\r\n#define ETH_MACA1HR_MACA1H                            ETH_MACA1HR_MACA1H_Msk   /* MAC address1 high */\r\n\r\n/* Bit definition for Ethernet MAC Address1 Low Register */\r\n#define ETH_MACA1LR_MACA1L_Pos                        (0U)                     \r\n#define ETH_MACA1LR_MACA1L_Msk                        (0xFFFFFFFFU << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACA1LR_MACA1L                            ETH_MACA1LR_MACA1L_Msk   /* MAC address1 low */\r\n\r\n/* Bit definition for Ethernet MAC Address2 High Register */\r\n#define ETH_MACA2HR_AE_Pos                            (31U)                    \r\n#define ETH_MACA2HR_AE_Msk                            (0x1U << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */\r\n#define ETH_MACA2HR_AE                                ETH_MACA2HR_AE_Msk       /* Address enable */\r\n#define ETH_MACA2HR_SA_Pos                            (30U)                    \r\n#define ETH_MACA2HR_SA_Msk                            (0x1U << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */\r\n#define ETH_MACA2HR_SA                                ETH_MACA2HR_SA_Msk       /* Source address */\r\n#define ETH_MACA2HR_MBC_Pos                           (24U)                    \r\n#define ETH_MACA2HR_MBC_Msk                           (0x3FU << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */\r\n#define ETH_MACA2HR_MBC                               ETH_MACA2HR_MBC_Msk      /* Mask byte control */\r\n#define ETH_MACA2HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */\r\n#define ETH_MACA2HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0] */\r\n#define ETH_MACA2HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */\r\n#define ETH_MACA2HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */\r\n#define ETH_MACA2HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8] */\r\n#define ETH_MACA2HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [70] */\r\n#define ETH_MACA2HR_MACA2H_Pos                        (0U)                     \r\n#define ETH_MACA2HR_MACA2H_Msk                        (0xFFFFU << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */\r\n#define ETH_MACA2HR_MACA2H                            ETH_MACA2HR_MACA2H_Msk   /* MAC address1 high */\r\n\r\n/* Bit definition for Ethernet MAC Address2 Low Register */\r\n#define ETH_MACA2LR_MACA2L_Pos                        (0U)                     \r\n#define ETH_MACA2LR_MACA2L_Msk                        (0xFFFFFFFFU << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACA2LR_MACA2L                            ETH_MACA2LR_MACA2L_Msk   /* MAC address2 low */\r\n\r\n/* Bit definition for Ethernet MAC Address3 High Register */\r\n#define ETH_MACA3HR_AE_Pos                            (31U)                    \r\n#define ETH_MACA3HR_AE_Msk                            (0x1U << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */\r\n#define ETH_MACA3HR_AE                                ETH_MACA3HR_AE_Msk       /* Address enable */\r\n#define ETH_MACA3HR_SA_Pos                            (30U)                    \r\n#define ETH_MACA3HR_SA_Msk                            (0x1U << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */\r\n#define ETH_MACA3HR_SA                                ETH_MACA3HR_SA_Msk       /* Source address */\r\n#define ETH_MACA3HR_MBC_Pos                           (24U)                    \r\n#define ETH_MACA3HR_MBC_Msk                           (0x3FU << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */\r\n#define ETH_MACA3HR_MBC                               ETH_MACA3HR_MBC_Msk      /* Mask byte control */\r\n#define ETH_MACA3HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */\r\n#define ETH_MACA3HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0] */\r\n#define ETH_MACA3HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */\r\n#define ETH_MACA3HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */\r\n#define ETH_MACA3HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8] */\r\n#define ETH_MACA3HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [70] */\r\n#define ETH_MACA3HR_MACA3H_Pos                        (0U)                     \r\n#define ETH_MACA3HR_MACA3H_Msk                        (0xFFFFU << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */\r\n#define ETH_MACA3HR_MACA3H                            ETH_MACA3HR_MACA3H_Msk   /* MAC address3 high */\r\n\r\n/* Bit definition for Ethernet MAC Address3 Low Register */\r\n#define ETH_MACA3LR_MACA3L_Pos                        (0U)                     \r\n#define ETH_MACA3LR_MACA3L_Msk                        (0xFFFFFFFFU << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MACA3LR_MACA3L                            ETH_MACA3LR_MACA3L_Msk   /* MAC address3 low */\r\n\r\n/******************************************************************************/\r\n/*                Ethernet MMC Registers bits definition                      */\r\n/******************************************************************************/\r\n\r\n/* Bit definition for Ethernet MMC Contol Register */\r\n#define ETH_MMCCR_MCFHP_Pos                           (5U)                     \r\n#define ETH_MMCCR_MCFHP_Msk                           (0x1U << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */\r\n#define ETH_MMCCR_MCFHP                               ETH_MMCCR_MCFHP_Msk      /* MMC counter Full-Half preset */\r\n#define ETH_MMCCR_MCP_Pos                             (4U)                     \r\n#define ETH_MMCCR_MCP_Msk                             (0x1U << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */\r\n#define ETH_MMCCR_MCP                                 ETH_MMCCR_MCP_Msk        /* MMC counter preset */\r\n#define ETH_MMCCR_MCF_Pos                             (3U)                     \r\n#define ETH_MMCCR_MCF_Msk                             (0x1U << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */\r\n#define ETH_MMCCR_MCF                                 ETH_MMCCR_MCF_Msk        /* MMC Counter Freeze */\r\n#define ETH_MMCCR_ROR_Pos                             (2U)                     \r\n#define ETH_MMCCR_ROR_Msk                             (0x1U << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */\r\n#define ETH_MMCCR_ROR                                 ETH_MMCCR_ROR_Msk        /* Reset on Read */\r\n#define ETH_MMCCR_CSR_Pos                             (1U)                     \r\n#define ETH_MMCCR_CSR_Msk                             (0x1U << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */\r\n#define ETH_MMCCR_CSR                                 ETH_MMCCR_CSR_Msk        /* Counter Stop Rollover */\r\n#define ETH_MMCCR_CR_Pos                              (0U)                     \r\n#define ETH_MMCCR_CR_Msk                              (0x1U << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */\r\n#define ETH_MMCCR_CR                                  ETH_MMCCR_CR_Msk         /* Counters Reset */\r\n\r\n/* Bit definition for Ethernet MMC Receive Interrupt Register */\r\n#define ETH_MMCRIR_RGUFS_Pos                          (17U)                    \r\n#define ETH_MMCRIR_RGUFS_Msk                          (0x1U << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */\r\n#define ETH_MMCRIR_RGUFS                              ETH_MMCRIR_RGUFS_Msk     /* Set when Rx good unicast frames counter reaches half the maximum value */\r\n#define ETH_MMCRIR_RFAES_Pos                          (6U)                     \r\n#define ETH_MMCRIR_RFAES_Msk                          (0x1U << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */\r\n#define ETH_MMCRIR_RFAES                              ETH_MMCRIR_RFAES_Msk     /* Set when Rx alignment error counter reaches half the maximum value */\r\n#define ETH_MMCRIR_RFCES_Pos                          (5U)                     \r\n#define ETH_MMCRIR_RFCES_Msk                          (0x1U << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */\r\n#define ETH_MMCRIR_RFCES                              ETH_MMCRIR_RFCES_Msk     /* Set when Rx crc error counter reaches half the maximum value */\r\n\r\n/* Bit definition for Ethernet MMC Transmit Interrupt Register */\r\n#define ETH_MMCTIR_TGFS_Pos                           (21U)                    \r\n#define ETH_MMCTIR_TGFS_Msk                           (0x1U << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */\r\n#define ETH_MMCTIR_TGFS                               ETH_MMCTIR_TGFS_Msk      /* Set when Tx good frame count counter reaches half the maximum value */\r\n#define ETH_MMCTIR_TGFMSCS_Pos                        (15U)                    \r\n#define ETH_MMCTIR_TGFMSCS_Msk                        (0x1U << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */\r\n#define ETH_MMCTIR_TGFMSCS                            ETH_MMCTIR_TGFMSCS_Msk   /* Set when Tx good multi col counter reaches half the maximum value */\r\n#define ETH_MMCTIR_TGFSCS_Pos                         (14U)                    \r\n#define ETH_MMCTIR_TGFSCS_Msk                         (0x1U << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */\r\n#define ETH_MMCTIR_TGFSCS                             ETH_MMCTIR_TGFSCS_Msk    /* Set when Tx good single col counter reaches half the maximum value */\r\n\r\n/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */\r\n#define ETH_MMCRIMR_RGUFM_Pos                         (17U)                    \r\n#define ETH_MMCRIMR_RGUFM_Msk                         (0x1U << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */\r\n#define ETH_MMCRIMR_RGUFM                             ETH_MMCRIMR_RGUFM_Msk    /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */\r\n#define ETH_MMCRIMR_RFAEM_Pos                         (6U)                     \r\n#define ETH_MMCRIMR_RFAEM_Msk                         (0x1U << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */\r\n#define ETH_MMCRIMR_RFAEM                             ETH_MMCRIMR_RFAEM_Msk    /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */\r\n#define ETH_MMCRIMR_RFCEM_Pos                         (5U)                     \r\n#define ETH_MMCRIMR_RFCEM_Msk                         (0x1U << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */\r\n#define ETH_MMCRIMR_RFCEM                             ETH_MMCRIMR_RFCEM_Msk    /* Mask the interrupt when Rx crc error counter reaches half the maximum value */\r\n\r\n/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */\r\n#define ETH_MMCTIMR_TGFM_Pos                          (21U)                    \r\n#define ETH_MMCTIMR_TGFM_Msk                          (0x1U << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */\r\n#define ETH_MMCTIMR_TGFM                              ETH_MMCTIMR_TGFM_Msk     /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */\r\n#define ETH_MMCTIMR_TGFMSCM_Pos                       (15U)                    \r\n#define ETH_MMCTIMR_TGFMSCM_Msk                       (0x1U << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */\r\n#define ETH_MMCTIMR_TGFMSCM                           ETH_MMCTIMR_TGFMSCM_Msk  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */\r\n#define ETH_MMCTIMR_TGFSCM_Pos                        (14U)                    \r\n#define ETH_MMCTIMR_TGFSCM_Msk                        (0x1U << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */\r\n#define ETH_MMCTIMR_TGFSCM                            ETH_MMCTIMR_TGFSCM_Msk   /* Mask the interrupt when Tx good single col counter reaches half the maximum value */\r\n\r\n/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */\r\n#define ETH_MMCTGFSCCR_TGFSCC_Pos                     (0U)                     \r\n#define ETH_MMCTGFSCCR_TGFSCC_Msk                     (0xFFFFFFFFU << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MMCTGFSCCR_TGFSCC                         ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */\r\n\r\n/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */\r\n#define ETH_MMCTGFMSCCR_TGFMSCC_Pos                   (0U)                     \r\n#define ETH_MMCTGFMSCCR_TGFMSCC_Msk                   (0xFFFFFFFFU << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MMCTGFMSCCR_TGFMSCC                       ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */\r\n\r\n/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */\r\n#define ETH_MMCTGFCR_TGFC_Pos                         (0U)                     \r\n#define ETH_MMCTGFCR_TGFC_Msk                         (0xFFFFFFFFU << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MMCTGFCR_TGFC                             ETH_MMCTGFCR_TGFC_Msk    /* Number of good frames transmitted. */\r\n\r\n/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */\r\n#define ETH_MMCRFCECR_RFCEC_Pos                       (0U)                     \r\n#define ETH_MMCRFCECR_RFCEC_Msk                       (0xFFFFFFFFU << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MMCRFCECR_RFCEC                           ETH_MMCRFCECR_RFCEC_Msk  /* Number of frames received with CRC error. */\r\n\r\n/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */\r\n#define ETH_MMCRFAECR_RFAEC_Pos                       (0U)                     \r\n#define ETH_MMCRFAECR_RFAEC_Msk                       (0xFFFFFFFFU << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MMCRFAECR_RFAEC                           ETH_MMCRFAECR_RFAEC_Msk  /* Number of frames received with alignment (dribble) error */\r\n\r\n/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */\r\n#define ETH_MMCRGUFCR_RGUFC_Pos                       (0U)                     \r\n#define ETH_MMCRGUFCR_RGUFC_Msk                       (0xFFFFFFFFU << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_MMCRGUFCR_RGUFC                           ETH_MMCRGUFCR_RGUFC_Msk  /* Number of good unicast frames received. */\r\n\r\n/******************************************************************************/\r\n/*               Ethernet PTP Registers bits definition                       */\r\n/******************************************************************************/\r\n\r\n/* Bit definition for Ethernet PTP Time Stamp Contol Register */\r\n#define ETH_PTPTSCR_TSCNT_Pos                         (16U)                    \r\n#define ETH_PTPTSCR_TSCNT_Msk                         (0x3U << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */\r\n#define ETH_PTPTSCR_TSCNT                             ETH_PTPTSCR_TSCNT_Msk    /* Time stamp clock node type */\r\n#define ETH_PTPTSSR_TSSMRME_Pos                       (15U)                    \r\n#define ETH_PTPTSSR_TSSMRME_Msk                       (0x1U << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */\r\n#define ETH_PTPTSSR_TSSMRME                           ETH_PTPTSSR_TSSMRME_Msk  /* Time stamp snapshot for message relevant to master enable */\r\n#define ETH_PTPTSSR_TSSEME_Pos                        (14U)                    \r\n#define ETH_PTPTSSR_TSSEME_Msk                        (0x1U << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */\r\n#define ETH_PTPTSSR_TSSEME                            ETH_PTPTSSR_TSSEME_Msk   /* Time stamp snapshot for event message enable */\r\n#define ETH_PTPTSSR_TSSIPV4FE_Pos                     (13U)                    \r\n#define ETH_PTPTSSR_TSSIPV4FE_Msk                     (0x1U << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */\r\n#define ETH_PTPTSSR_TSSIPV4FE                         ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */\r\n#define ETH_PTPTSSR_TSSIPV6FE_Pos                     (12U)                    \r\n#define ETH_PTPTSSR_TSSIPV6FE_Msk                     (0x1U << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */\r\n#define ETH_PTPTSSR_TSSIPV6FE                         ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */\r\n#define ETH_PTPTSSR_TSSPTPOEFE_Pos                    (11U)                    \r\n#define ETH_PTPTSSR_TSSPTPOEFE_Msk                    (0x1U << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */\r\n#define ETH_PTPTSSR_TSSPTPOEFE                        ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */\r\n#define ETH_PTPTSSR_TSPTPPSV2E_Pos                    (10U)                    \r\n#define ETH_PTPTSSR_TSPTPPSV2E_Msk                    (0x1U << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */\r\n#define ETH_PTPTSSR_TSPTPPSV2E                        ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */\r\n#define ETH_PTPTSSR_TSSSR_Pos                         (9U)                     \r\n#define ETH_PTPTSSR_TSSSR_Msk                         (0x1U << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */\r\n#define ETH_PTPTSSR_TSSSR                             ETH_PTPTSSR_TSSSR_Msk    /* Time stamp Sub-seconds rollover */\r\n#define ETH_PTPTSSR_TSSARFE_Pos                       (8U)                     \r\n#define ETH_PTPTSSR_TSSARFE_Msk                       (0x1U << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */\r\n#define ETH_PTPTSSR_TSSARFE                           ETH_PTPTSSR_TSSARFE_Msk  /* Time stamp snapshot for all received frames enable */\r\n\r\n#define ETH_PTPTSCR_TSARU_Pos                         (5U)                     \r\n#define ETH_PTPTSCR_TSARU_Msk                         (0x1U << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */\r\n#define ETH_PTPTSCR_TSARU                             ETH_PTPTSCR_TSARU_Msk    /* Addend register update */\r\n#define ETH_PTPTSCR_TSITE_Pos                         (4U)                     \r\n#define ETH_PTPTSCR_TSITE_Msk                         (0x1U << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */\r\n#define ETH_PTPTSCR_TSITE                             ETH_PTPTSCR_TSITE_Msk    /* Time stamp interrupt trigger enable */\r\n#define ETH_PTPTSCR_TSSTU_Pos                         (3U)                     \r\n#define ETH_PTPTSCR_TSSTU_Msk                         (0x1U << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */\r\n#define ETH_PTPTSCR_TSSTU                             ETH_PTPTSCR_TSSTU_Msk    /* Time stamp update */\r\n#define ETH_PTPTSCR_TSSTI_Pos                         (2U)                     \r\n#define ETH_PTPTSCR_TSSTI_Msk                         (0x1U << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */\r\n#define ETH_PTPTSCR_TSSTI                             ETH_PTPTSCR_TSSTI_Msk    /* Time stamp initialize */\r\n#define ETH_PTPTSCR_TSFCU_Pos                         (1U)                     \r\n#define ETH_PTPTSCR_TSFCU_Msk                         (0x1U << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */\r\n#define ETH_PTPTSCR_TSFCU                             ETH_PTPTSCR_TSFCU_Msk    /* Time stamp fine or coarse update */\r\n#define ETH_PTPTSCR_TSE_Pos                           (0U)                     \r\n#define ETH_PTPTSCR_TSE_Msk                           (0x1U << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */\r\n#define ETH_PTPTSCR_TSE                               ETH_PTPTSCR_TSE_Msk      /* Time stamp enable */\r\n\r\n/* Bit definition for Ethernet PTP Sub-Second Increment Register */\r\n#define ETH_PTPSSIR_STSSI_Pos                         (0U)                     \r\n#define ETH_PTPSSIR_STSSI_Msk                         (0xFFU << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */\r\n#define ETH_PTPSSIR_STSSI                             ETH_PTPSSIR_STSSI_Msk    /* System time Sub-second increment value */\r\n\r\n/* Bit definition for Ethernet PTP Time Stamp High Register */\r\n#define ETH_PTPTSHR_STS_Pos                           (0U)                     \r\n#define ETH_PTPTSHR_STS_Msk                           (0xFFFFFFFFU << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_PTPTSHR_STS                               ETH_PTPTSHR_STS_Msk      /* System Time second */\r\n\r\n/* Bit definition for Ethernet PTP Time Stamp Low Register */\r\n#define ETH_PTPTSLR_STPNS_Pos                         (31U)                    \r\n#define ETH_PTPTSLR_STPNS_Msk                         (0x1U << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */\r\n#define ETH_PTPTSLR_STPNS                             ETH_PTPTSLR_STPNS_Msk    /* System Time Positive or negative time */\r\n#define ETH_PTPTSLR_STSS_Pos                          (0U)                     \r\n#define ETH_PTPTSLR_STSS_Msk                          (0x7FFFFFFFU << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */\r\n#define ETH_PTPTSLR_STSS                              ETH_PTPTSLR_STSS_Msk     /* System Time sub-seconds */\r\n\r\n/* Bit definition for Ethernet PTP Time Stamp High Update Register */\r\n#define ETH_PTPTSHUR_TSUS_Pos                         (0U)                     \r\n#define ETH_PTPTSHUR_TSUS_Msk                         (0xFFFFFFFFU << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_PTPTSHUR_TSUS                             ETH_PTPTSHUR_TSUS_Msk    /* Time stamp update seconds */\r\n\r\n/* Bit definition for Ethernet PTP Time Stamp Low Update Register */\r\n#define ETH_PTPTSLUR_TSUPNS_Pos                       (31U)                    \r\n#define ETH_PTPTSLUR_TSUPNS_Msk                       (0x1U << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */\r\n#define ETH_PTPTSLUR_TSUPNS                           ETH_PTPTSLUR_TSUPNS_Msk  /* Time stamp update Positive or negative time */\r\n#define ETH_PTPTSLUR_TSUSS_Pos                        (0U)                     \r\n#define ETH_PTPTSLUR_TSUSS_Msk                        (0x7FFFFFFFU << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */\r\n#define ETH_PTPTSLUR_TSUSS                            ETH_PTPTSLUR_TSUSS_Msk   /* Time stamp update sub-seconds */\r\n\r\n/* Bit definition for Ethernet PTP Time Stamp Addend Register */\r\n#define ETH_PTPTSAR_TSA_Pos                           (0U)                     \r\n#define ETH_PTPTSAR_TSA_Msk                           (0xFFFFFFFFU << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_PTPTSAR_TSA                               ETH_PTPTSAR_TSA_Msk      /* Time stamp addend */\r\n\r\n/* Bit definition for Ethernet PTP Target Time High Register */\r\n#define ETH_PTPTTHR_TTSH_Pos                          (0U)                     \r\n#define ETH_PTPTTHR_TTSH_Msk                          (0xFFFFFFFFU << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_PTPTTHR_TTSH                              ETH_PTPTTHR_TTSH_Msk     /* Target time stamp high */\r\n\r\n/* Bit definition for Ethernet PTP Target Time Low Register */\r\n#define ETH_PTPTTLR_TTSL_Pos                          (0U)                     \r\n#define ETH_PTPTTLR_TTSL_Msk                          (0xFFFFFFFFU << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_PTPTTLR_TTSL                              ETH_PTPTTLR_TTSL_Msk     /* Target time stamp low */\r\n\r\n/* Bit definition for Ethernet PTP Time Stamp Status Register */\r\n#define ETH_PTPTSSR_TSTTR_Pos                         (5U)                     \r\n#define ETH_PTPTSSR_TSTTR_Msk                         (0x1U << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */\r\n#define ETH_PTPTSSR_TSTTR                             ETH_PTPTSSR_TSTTR_Msk    /* Time stamp target time reached */\r\n#define ETH_PTPTSSR_TSSO_Pos                          (4U)                     \r\n#define ETH_PTPTSSR_TSSO_Msk                          (0x1U << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */\r\n#define ETH_PTPTSSR_TSSO                              ETH_PTPTSSR_TSSO_Msk     /* Time stamp seconds overflow */\r\n\r\n/******************************************************************************/\r\n/*                 Ethernet DMA Registers bits definition                     */\r\n/******************************************************************************/\r\n\r\n/* Bit definition for Ethernet DMA Bus Mode Register */\r\n#define ETH_DMABMR_AAB_Pos                            (25U)                    \r\n#define ETH_DMABMR_AAB_Msk                            (0x1U << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */\r\n#define ETH_DMABMR_AAB                                ETH_DMABMR_AAB_Msk       /* Address-Aligned beats */\r\n#define ETH_DMABMR_FPM_Pos                            (24U)                    \r\n#define ETH_DMABMR_FPM_Msk                            (0x1U << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */\r\n#define ETH_DMABMR_FPM                                ETH_DMABMR_FPM_Msk       /* 4xPBL mode */\r\n#define ETH_DMABMR_USP_Pos                            (23U)                    \r\n#define ETH_DMABMR_USP_Msk                            (0x1U << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */\r\n#define ETH_DMABMR_USP                                ETH_DMABMR_USP_Msk       /* Use separate PBL */\r\n#define ETH_DMABMR_RDP_Pos                            (17U)                    \r\n#define ETH_DMABMR_RDP_Msk                            (0x3FU << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */\r\n#define ETH_DMABMR_RDP                                ETH_DMABMR_RDP_Msk       /* RxDMA PBL */\r\n#define ETH_DMABMR_RDP_1Beat                          0x00020000U              /* maximum number of beats to be transferred in one RxDMA transaction is 1 */\r\n#define ETH_DMABMR_RDP_2Beat                          0x00040000U              /* maximum number of beats to be transferred in one RxDMA transaction is 2 */\r\n#define ETH_DMABMR_RDP_4Beat                          0x00080000U              /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\r\n#define ETH_DMABMR_RDP_8Beat                          0x00100000U              /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\r\n#define ETH_DMABMR_RDP_16Beat                         0x00200000U              /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\r\n#define ETH_DMABMR_RDP_32Beat                         0x00400000U              /* maximum number of beats to be transferred in one RxDMA transaction is 32 */\r\n#define ETH_DMABMR_RDP_4xPBL_4Beat                    0x01020000U              /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\r\n#define ETH_DMABMR_RDP_4xPBL_8Beat                    0x01040000U              /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\r\n#define ETH_DMABMR_RDP_4xPBL_16Beat                   0x01080000U              /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\r\n#define ETH_DMABMR_RDP_4xPBL_32Beat                   0x01100000U              /* maximum number of beats to be transferred in one RxDMA transaction is 32 */\r\n#define ETH_DMABMR_RDP_4xPBL_64Beat                   0x01200000U              /* maximum number of beats to be transferred in one RxDMA transaction is 64 */\r\n#define ETH_DMABMR_RDP_4xPBL_128Beat                  0x01400000U              /* maximum number of beats to be transferred in one RxDMA transaction is 128 */\r\n#define ETH_DMABMR_FB_Pos                             (16U)                    \r\n#define ETH_DMABMR_FB_Msk                             (0x1U << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */\r\n#define ETH_DMABMR_FB                                 ETH_DMABMR_FB_Msk        /* Fixed Burst */\r\n#define ETH_DMABMR_RTPR_Pos                           (14U)                    \r\n#define ETH_DMABMR_RTPR_Msk                           (0x3U << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */\r\n#define ETH_DMABMR_RTPR                               ETH_DMABMR_RTPR_Msk      /* Rx Tx priority ratio */\r\n#define ETH_DMABMR_RTPR_1_1                           0x00000000U              /* Rx Tx priority ratio */\r\n#define ETH_DMABMR_RTPR_2_1                           0x00004000U              /* Rx Tx priority ratio */\r\n#define ETH_DMABMR_RTPR_3_1                           0x00008000U              /* Rx Tx priority ratio */\r\n#define ETH_DMABMR_RTPR_4_1                           0x0000C000U              /* Rx Tx priority ratio */\r\n#define ETH_DMABMR_PBL_Pos                            (8U)                     \r\n#define ETH_DMABMR_PBL_Msk                            (0x3FU << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */\r\n#define ETH_DMABMR_PBL                                ETH_DMABMR_PBL_Msk       /* Programmable burst length */\r\n#define ETH_DMABMR_PBL_1Beat                          0x00000100U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */\r\n#define ETH_DMABMR_PBL_2Beat                          0x00000200U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */\r\n#define ETH_DMABMR_PBL_4Beat                          0x00000400U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r\n#define ETH_DMABMR_PBL_8Beat                          0x00000800U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r\n#define ETH_DMABMR_PBL_16Beat                         0x00001000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r\n#define ETH_DMABMR_PBL_32Beat                         0x00002000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\r\n#define ETH_DMABMR_PBL_4xPBL_4Beat                    0x01000100U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r\n#define ETH_DMABMR_PBL_4xPBL_8Beat                    0x01000200U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r\n#define ETH_DMABMR_PBL_4xPBL_16Beat                   0x01000400U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r\n#define ETH_DMABMR_PBL_4xPBL_32Beat                   0x01000800U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\r\n#define ETH_DMABMR_PBL_4xPBL_64Beat                   0x01001000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */\r\n#define ETH_DMABMR_PBL_4xPBL_128Beat                  0x01002000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */\r\n#define ETH_DMABMR_EDE_Pos                            (7U)                     \r\n#define ETH_DMABMR_EDE_Msk                            (0x1U << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */\r\n#define ETH_DMABMR_EDE                                ETH_DMABMR_EDE_Msk       /* Enhanced Descriptor Enable */\r\n#define ETH_DMABMR_DSL_Pos                            (2U)                     \r\n#define ETH_DMABMR_DSL_Msk                            (0x1FU << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */\r\n#define ETH_DMABMR_DSL                                ETH_DMABMR_DSL_Msk       /* Descriptor Skip Length */\r\n#define ETH_DMABMR_DA_Pos                             (1U)                     \r\n#define ETH_DMABMR_DA_Msk                             (0x1U << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */\r\n#define ETH_DMABMR_DA                                 ETH_DMABMR_DA_Msk        /* DMA arbitration scheme */\r\n#define ETH_DMABMR_SR_Pos                             (0U)                     \r\n#define ETH_DMABMR_SR_Msk                             (0x1U << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */\r\n#define ETH_DMABMR_SR                                 ETH_DMABMR_SR_Msk        /* Software reset */\r\n\r\n/* Bit definition for Ethernet DMA Transmit Poll Demand Register */\r\n#define ETH_DMATPDR_TPD_Pos                           (0U)                     \r\n#define ETH_DMATPDR_TPD_Msk                           (0xFFFFFFFFU << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_DMATPDR_TPD                               ETH_DMATPDR_TPD_Msk      /* Transmit poll demand */\r\n\r\n/* Bit definition for Ethernet DMA Receive Poll Demand Register */\r\n#define ETH_DMARPDR_RPD_Pos                           (0U)                     \r\n#define ETH_DMARPDR_RPD_Msk                           (0xFFFFFFFFU << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_DMARPDR_RPD                               ETH_DMARPDR_RPD_Msk      /* Receive poll demand  */\r\n\r\n/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */\r\n#define ETH_DMARDLAR_SRL_Pos                          (0U)                     \r\n#define ETH_DMARDLAR_SRL_Msk                          (0xFFFFFFFFU << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_DMARDLAR_SRL                              ETH_DMARDLAR_SRL_Msk     /* Start of receive list */\r\n\r\n/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */\r\n#define ETH_DMATDLAR_STL_Pos                          (0U)                     \r\n#define ETH_DMATDLAR_STL_Msk                          (0xFFFFFFFFU << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_DMATDLAR_STL                              ETH_DMATDLAR_STL_Msk     /* Start of transmit list */\r\n\r\n/* Bit definition for Ethernet DMA Status Register */\r\n#define ETH_DMASR_TSTS_Pos                            (29U)                    \r\n#define ETH_DMASR_TSTS_Msk                            (0x1U << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */\r\n#define ETH_DMASR_TSTS                                ETH_DMASR_TSTS_Msk       /* Time-stamp trigger status */\r\n#define ETH_DMASR_PMTS_Pos                            (28U)                    \r\n#define ETH_DMASR_PMTS_Msk                            (0x1U << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */\r\n#define ETH_DMASR_PMTS                                ETH_DMASR_PMTS_Msk       /* PMT status */\r\n#define ETH_DMASR_MMCS_Pos                            (27U)                    \r\n#define ETH_DMASR_MMCS_Msk                            (0x1U << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */\r\n#define ETH_DMASR_MMCS                                ETH_DMASR_MMCS_Msk       /* MMC status */\r\n#define ETH_DMASR_EBS_Pos                             (23U)                    \r\n#define ETH_DMASR_EBS_Msk                             (0x7U << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */\r\n#define ETH_DMASR_EBS                                 ETH_DMASR_EBS_Msk        /* Error bits status */\r\n  /* combination with EBS[2:0] for GetFlagStatus function */\r\n#define ETH_DMASR_EBS_DescAccess_Pos                  (25U)                    \r\n#define ETH_DMASR_EBS_DescAccess_Msk                  (0x1U << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */\r\n#define ETH_DMASR_EBS_DescAccess                      ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */\r\n#define ETH_DMASR_EBS_ReadTransf_Pos                  (24U)                    \r\n#define ETH_DMASR_EBS_ReadTransf_Msk                  (0x1U << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */\r\n#define ETH_DMASR_EBS_ReadTransf                      ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */\r\n#define ETH_DMASR_EBS_DataTransfTx_Pos                (23U)                    \r\n#define ETH_DMASR_EBS_DataTransfTx_Msk                (0x1U << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */\r\n#define ETH_DMASR_EBS_DataTransfTx                    ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */\r\n#define ETH_DMASR_TPS_Pos                             (20U)                    \r\n#define ETH_DMASR_TPS_Msk                             (0x7U << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */\r\n#define ETH_DMASR_TPS                                 ETH_DMASR_TPS_Msk        /* Transmit process state */\r\n#define ETH_DMASR_TPS_Stopped                         0x00000000U              /* Stopped - Reset or Stop Tx Command issued  */\r\n#define ETH_DMASR_TPS_Fetching_Pos                    (20U)                    \r\n#define ETH_DMASR_TPS_Fetching_Msk                    (0x1U << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */\r\n#define ETH_DMASR_TPS_Fetching                        ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */\r\n#define ETH_DMASR_TPS_Waiting_Pos                     (21U)                    \r\n#define ETH_DMASR_TPS_Waiting_Msk                     (0x1U << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */\r\n#define ETH_DMASR_TPS_Waiting                         ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */\r\n#define ETH_DMASR_TPS_Reading_Pos                     (20U)                    \r\n#define ETH_DMASR_TPS_Reading_Msk                     (0x3U << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */\r\n#define ETH_DMASR_TPS_Reading                         ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */\r\n#define ETH_DMASR_TPS_Suspended_Pos                   (21U)                    \r\n#define ETH_DMASR_TPS_Suspended_Msk                   (0x3U << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */\r\n#define ETH_DMASR_TPS_Suspended                       ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */\r\n#define ETH_DMASR_TPS_Closing_Pos                     (20U)                    \r\n#define ETH_DMASR_TPS_Closing_Msk                     (0x7U << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */\r\n#define ETH_DMASR_TPS_Closing                         ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */\r\n#define ETH_DMASR_RPS_Pos                             (17U)                    \r\n#define ETH_DMASR_RPS_Msk                             (0x7U << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */\r\n#define ETH_DMASR_RPS                                 ETH_DMASR_RPS_Msk        /* Receive process state */\r\n#define ETH_DMASR_RPS_Stopped                         0x00000000U              /* Stopped - Reset or Stop Rx Command issued */\r\n#define ETH_DMASR_RPS_Fetching_Pos                    (17U)                    \r\n#define ETH_DMASR_RPS_Fetching_Msk                    (0x1U << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */\r\n#define ETH_DMASR_RPS_Fetching                        ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */\r\n#define ETH_DMASR_RPS_Waiting_Pos                     (17U)                    \r\n#define ETH_DMASR_RPS_Waiting_Msk                     (0x3U << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */\r\n#define ETH_DMASR_RPS_Waiting                         ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */\r\n#define ETH_DMASR_RPS_Suspended_Pos                   (19U)                    \r\n#define ETH_DMASR_RPS_Suspended_Msk                   (0x1U << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */\r\n#define ETH_DMASR_RPS_Suspended                       ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */\r\n#define ETH_DMASR_RPS_Closing_Pos                     (17U)                    \r\n#define ETH_DMASR_RPS_Closing_Msk                     (0x5U << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */\r\n#define ETH_DMASR_RPS_Closing                         ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */\r\n#define ETH_DMASR_RPS_Queuing_Pos                     (17U)                    \r\n#define ETH_DMASR_RPS_Queuing_Msk                     (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */\r\n#define ETH_DMASR_RPS_Queuing                         ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */\r\n#define ETH_DMASR_NIS_Pos                             (16U)                    \r\n#define ETH_DMASR_NIS_Msk                             (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */\r\n#define ETH_DMASR_NIS                                 ETH_DMASR_NIS_Msk        /* Normal interrupt summary */\r\n#define ETH_DMASR_AIS_Pos                             (15U)                    \r\n#define ETH_DMASR_AIS_Msk                             (0x1U << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */\r\n#define ETH_DMASR_AIS                                 ETH_DMASR_AIS_Msk        /* Abnormal interrupt summary */\r\n#define ETH_DMASR_ERS_Pos                             (14U)                    \r\n#define ETH_DMASR_ERS_Msk                             (0x1U << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */\r\n#define ETH_DMASR_ERS                                 ETH_DMASR_ERS_Msk        /* Early receive status */\r\n#define ETH_DMASR_FBES_Pos                            (13U)                    \r\n#define ETH_DMASR_FBES_Msk                            (0x1U << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */\r\n#define ETH_DMASR_FBES                                ETH_DMASR_FBES_Msk       /* Fatal bus error status */\r\n#define ETH_DMASR_ETS_Pos                             (10U)                    \r\n#define ETH_DMASR_ETS_Msk                             (0x1U << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */\r\n#define ETH_DMASR_ETS                                 ETH_DMASR_ETS_Msk        /* Early transmit status */\r\n#define ETH_DMASR_RWTS_Pos                            (9U)                     \r\n#define ETH_DMASR_RWTS_Msk                            (0x1U << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */\r\n#define ETH_DMASR_RWTS                                ETH_DMASR_RWTS_Msk       /* Receive watchdog timeout status */\r\n#define ETH_DMASR_RPSS_Pos                            (8U)                     \r\n#define ETH_DMASR_RPSS_Msk                            (0x1U << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */\r\n#define ETH_DMASR_RPSS                                ETH_DMASR_RPSS_Msk       /* Receive process stopped status */\r\n#define ETH_DMASR_RBUS_Pos                            (7U)                     \r\n#define ETH_DMASR_RBUS_Msk                            (0x1U << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */\r\n#define ETH_DMASR_RBUS                                ETH_DMASR_RBUS_Msk       /* Receive buffer unavailable status */\r\n#define ETH_DMASR_RS_Pos                              (6U)                     \r\n#define ETH_DMASR_RS_Msk                              (0x1U << ETH_DMASR_RS_Pos) /*!< 0x00000040 */\r\n#define ETH_DMASR_RS                                  ETH_DMASR_RS_Msk         /* Receive status */\r\n#define ETH_DMASR_TUS_Pos                             (5U)                     \r\n#define ETH_DMASR_TUS_Msk                             (0x1U << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */\r\n#define ETH_DMASR_TUS                                 ETH_DMASR_TUS_Msk        /* Transmit underflow status */\r\n#define ETH_DMASR_ROS_Pos                             (4U)                     \r\n#define ETH_DMASR_ROS_Msk                             (0x1U << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */\r\n#define ETH_DMASR_ROS                                 ETH_DMASR_ROS_Msk        /* Receive overflow status */\r\n#define ETH_DMASR_TJTS_Pos                            (3U)                     \r\n#define ETH_DMASR_TJTS_Msk                            (0x1U << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */\r\n#define ETH_DMASR_TJTS                                ETH_DMASR_TJTS_Msk       /* Transmit jabber timeout status */\r\n#define ETH_DMASR_TBUS_Pos                            (2U)                     \r\n#define ETH_DMASR_TBUS_Msk                            (0x1U << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */\r\n#define ETH_DMASR_TBUS                                ETH_DMASR_TBUS_Msk       /* Transmit buffer unavailable status */\r\n#define ETH_DMASR_TPSS_Pos                            (1U)                     \r\n#define ETH_DMASR_TPSS_Msk                            (0x1U << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */\r\n#define ETH_DMASR_TPSS                                ETH_DMASR_TPSS_Msk       /* Transmit process stopped status */\r\n#define ETH_DMASR_TS_Pos                              (0U)                     \r\n#define ETH_DMASR_TS_Msk                              (0x1U << ETH_DMASR_TS_Pos) /*!< 0x00000001 */\r\n#define ETH_DMASR_TS                                  ETH_DMASR_TS_Msk         /* Transmit status */\r\n\r\n/* Bit definition for Ethernet DMA Operation Mode Register */\r\n#define ETH_DMAOMR_DTCEFD_Pos                         (26U)                    \r\n#define ETH_DMAOMR_DTCEFD_Msk                         (0x1U << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */\r\n#define ETH_DMAOMR_DTCEFD                             ETH_DMAOMR_DTCEFD_Msk    /* Disable Dropping of TCP/IP checksum error frames */\r\n#define ETH_DMAOMR_RSF_Pos                            (25U)                    \r\n#define ETH_DMAOMR_RSF_Msk                            (0x1U << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */\r\n#define ETH_DMAOMR_RSF                                ETH_DMAOMR_RSF_Msk       /* Receive store and forward */\r\n#define ETH_DMAOMR_DFRF_Pos                           (24U)                    \r\n#define ETH_DMAOMR_DFRF_Msk                           (0x1U << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */\r\n#define ETH_DMAOMR_DFRF                               ETH_DMAOMR_DFRF_Msk      /* Disable flushing of received frames */\r\n#define ETH_DMAOMR_TSF_Pos                            (21U)                    \r\n#define ETH_DMAOMR_TSF_Msk                            (0x1U << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */\r\n#define ETH_DMAOMR_TSF                                ETH_DMAOMR_TSF_Msk       /* Transmit store and forward */\r\n#define ETH_DMAOMR_FTF_Pos                            (20U)                    \r\n#define ETH_DMAOMR_FTF_Msk                            (0x1U << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */\r\n#define ETH_DMAOMR_FTF                                ETH_DMAOMR_FTF_Msk       /* Flush transmit FIFO */\r\n#define ETH_DMAOMR_TTC_Pos                            (14U)                    \r\n#define ETH_DMAOMR_TTC_Msk                            (0x7U << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */\r\n#define ETH_DMAOMR_TTC                                ETH_DMAOMR_TTC_Msk       /* Transmit threshold control */\r\n#define ETH_DMAOMR_TTC_64Bytes                        0x00000000U              /* threshold level of the MTL Transmit FIFO is 64 Bytes */\r\n#define ETH_DMAOMR_TTC_128Bytes                       0x00004000U              /* threshold level of the MTL Transmit FIFO is 128 Bytes */\r\n#define ETH_DMAOMR_TTC_192Bytes                       0x00008000U              /* threshold level of the MTL Transmit FIFO is 192 Bytes */\r\n#define ETH_DMAOMR_TTC_256Bytes                       0x0000C000U              /* threshold level of the MTL Transmit FIFO is 256 Bytes */\r\n#define ETH_DMAOMR_TTC_40Bytes                        0x00010000U              /* threshold level of the MTL Transmit FIFO is 40 Bytes */\r\n#define ETH_DMAOMR_TTC_32Bytes                        0x00014000U              /* threshold level of the MTL Transmit FIFO is 32 Bytes */\r\n#define ETH_DMAOMR_TTC_24Bytes                        0x00018000U              /* threshold level of the MTL Transmit FIFO is 24 Bytes */\r\n#define ETH_DMAOMR_TTC_16Bytes                        0x0001C000U              /* threshold level of the MTL Transmit FIFO is 16 Bytes */\r\n#define ETH_DMAOMR_ST_Pos                             (13U)                    \r\n#define ETH_DMAOMR_ST_Msk                             (0x1U << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */\r\n#define ETH_DMAOMR_ST                                 ETH_DMAOMR_ST_Msk        /* Start/stop transmission command */\r\n#define ETH_DMAOMR_FEF_Pos                            (7U)                     \r\n#define ETH_DMAOMR_FEF_Msk                            (0x1U << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */\r\n#define ETH_DMAOMR_FEF                                ETH_DMAOMR_FEF_Msk       /* Forward error frames */\r\n#define ETH_DMAOMR_FUGF_Pos                           (6U)                     \r\n#define ETH_DMAOMR_FUGF_Msk                           (0x1U << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */\r\n#define ETH_DMAOMR_FUGF                               ETH_DMAOMR_FUGF_Msk      /* Forward undersized good frames */\r\n#define ETH_DMAOMR_RTC_Pos                            (3U)                     \r\n#define ETH_DMAOMR_RTC_Msk                            (0x3U << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */\r\n#define ETH_DMAOMR_RTC                                ETH_DMAOMR_RTC_Msk       /* receive threshold control */\r\n#define ETH_DMAOMR_RTC_64Bytes                        0x00000000U              /* threshold level of the MTL Receive FIFO is 64 Bytes */\r\n#define ETH_DMAOMR_RTC_32Bytes                        0x00000008U              /* threshold level of the MTL Receive FIFO is 32 Bytes */\r\n#define ETH_DMAOMR_RTC_96Bytes                        0x00000010U              /* threshold level of the MTL Receive FIFO is 96 Bytes */\r\n#define ETH_DMAOMR_RTC_128Bytes                       0x00000018U              /* threshold level of the MTL Receive FIFO is 128 Bytes */\r\n#define ETH_DMAOMR_OSF_Pos                            (2U)                     \r\n#define ETH_DMAOMR_OSF_Msk                            (0x1U << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */\r\n#define ETH_DMAOMR_OSF                                ETH_DMAOMR_OSF_Msk       /* operate on second frame */\r\n#define ETH_DMAOMR_SR_Pos                             (1U)                     \r\n#define ETH_DMAOMR_SR_Msk                             (0x1U << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */\r\n#define ETH_DMAOMR_SR                                 ETH_DMAOMR_SR_Msk        /* Start/stop receive */\r\n\r\n/* Bit definition for Ethernet DMA Interrupt Enable Register */\r\n#define ETH_DMAIER_NISE_Pos                           (16U)                    \r\n#define ETH_DMAIER_NISE_Msk                           (0x1U << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */\r\n#define ETH_DMAIER_NISE                               ETH_DMAIER_NISE_Msk      /* Normal interrupt summary enable */\r\n#define ETH_DMAIER_AISE_Pos                           (15U)                    \r\n#define ETH_DMAIER_AISE_Msk                           (0x1U << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */\r\n#define ETH_DMAIER_AISE                               ETH_DMAIER_AISE_Msk      /* Abnormal interrupt summary enable */\r\n#define ETH_DMAIER_ERIE_Pos                           (14U)                    \r\n#define ETH_DMAIER_ERIE_Msk                           (0x1U << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */\r\n#define ETH_DMAIER_ERIE                               ETH_DMAIER_ERIE_Msk      /* Early receive interrupt enable */\r\n#define ETH_DMAIER_FBEIE_Pos                          (13U)                    \r\n#define ETH_DMAIER_FBEIE_Msk                          (0x1U << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */\r\n#define ETH_DMAIER_FBEIE                              ETH_DMAIER_FBEIE_Msk     /* Fatal bus error interrupt enable */\r\n#define ETH_DMAIER_ETIE_Pos                           (10U)                    \r\n#define ETH_DMAIER_ETIE_Msk                           (0x1U << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */\r\n#define ETH_DMAIER_ETIE                               ETH_DMAIER_ETIE_Msk      /* Early transmit interrupt enable */\r\n#define ETH_DMAIER_RWTIE_Pos                          (9U)                     \r\n#define ETH_DMAIER_RWTIE_Msk                          (0x1U << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */\r\n#define ETH_DMAIER_RWTIE                              ETH_DMAIER_RWTIE_Msk     /* Receive watchdog timeout interrupt enable */\r\n#define ETH_DMAIER_RPSIE_Pos                          (8U)                     \r\n#define ETH_DMAIER_RPSIE_Msk                          (0x1U << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */\r\n#define ETH_DMAIER_RPSIE                              ETH_DMAIER_RPSIE_Msk     /* Receive process stopped interrupt enable */\r\n#define ETH_DMAIER_RBUIE_Pos                          (7U)                     \r\n#define ETH_DMAIER_RBUIE_Msk                          (0x1U << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */\r\n#define ETH_DMAIER_RBUIE                              ETH_DMAIER_RBUIE_Msk     /* Receive buffer unavailable interrupt enable */\r\n#define ETH_DMAIER_RIE_Pos                            (6U)                     \r\n#define ETH_DMAIER_RIE_Msk                            (0x1U << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */\r\n#define ETH_DMAIER_RIE                                ETH_DMAIER_RIE_Msk       /* Receive interrupt enable */\r\n#define ETH_DMAIER_TUIE_Pos                           (5U)                     \r\n#define ETH_DMAIER_TUIE_Msk                           (0x1U << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */\r\n#define ETH_DMAIER_TUIE                               ETH_DMAIER_TUIE_Msk      /* Transmit Underflow interrupt enable */\r\n#define ETH_DMAIER_ROIE_Pos                           (4U)                     \r\n#define ETH_DMAIER_ROIE_Msk                           (0x1U << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */\r\n#define ETH_DMAIER_ROIE                               ETH_DMAIER_ROIE_Msk      /* Receive Overflow interrupt enable */\r\n#define ETH_DMAIER_TJTIE_Pos                          (3U)                     \r\n#define ETH_DMAIER_TJTIE_Msk                          (0x1U << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */\r\n#define ETH_DMAIER_TJTIE                              ETH_DMAIER_TJTIE_Msk     /* Transmit jabber timeout interrupt enable */\r\n#define ETH_DMAIER_TBUIE_Pos                          (2U)                     \r\n#define ETH_DMAIER_TBUIE_Msk                          (0x1U << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */\r\n#define ETH_DMAIER_TBUIE                              ETH_DMAIER_TBUIE_Msk     /* Transmit buffer unavailable interrupt enable */\r\n#define ETH_DMAIER_TPSIE_Pos                          (1U)                     \r\n#define ETH_DMAIER_TPSIE_Msk                          (0x1U << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */\r\n#define ETH_DMAIER_TPSIE                              ETH_DMAIER_TPSIE_Msk     /* Transmit process stopped interrupt enable */\r\n#define ETH_DMAIER_TIE_Pos                            (0U)                     \r\n#define ETH_DMAIER_TIE_Msk                            (0x1U << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */\r\n#define ETH_DMAIER_TIE                                ETH_DMAIER_TIE_Msk       /* Transmit interrupt enable */\r\n\r\n/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */\r\n#define ETH_DMAMFBOCR_OFOC_Pos                        (28U)                    \r\n#define ETH_DMAMFBOCR_OFOC_Msk                        (0x1U << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */\r\n#define ETH_DMAMFBOCR_OFOC                            ETH_DMAMFBOCR_OFOC_Msk   /* Overflow bit for FIFO overflow counter */\r\n#define ETH_DMAMFBOCR_MFA_Pos                         (17U)                    \r\n#define ETH_DMAMFBOCR_MFA_Msk                         (0x7FFU << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */\r\n#define ETH_DMAMFBOCR_MFA                             ETH_DMAMFBOCR_MFA_Msk    /* Number of frames missed by the application */\r\n#define ETH_DMAMFBOCR_OMFC_Pos                        (16U)                    \r\n#define ETH_DMAMFBOCR_OMFC_Msk                        (0x1U << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */\r\n#define ETH_DMAMFBOCR_OMFC                            ETH_DMAMFBOCR_OMFC_Msk   /* Overflow bit for missed frame counter */\r\n#define ETH_DMAMFBOCR_MFC_Pos                         (0U)                     \r\n#define ETH_DMAMFBOCR_MFC_Msk                         (0xFFFFU << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */\r\n#define ETH_DMAMFBOCR_MFC                             ETH_DMAMFBOCR_MFC_Msk    /* Number of frames missed by the controller */\r\n\r\n/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */\r\n#define ETH_DMACHTDR_HTDAP_Pos                        (0U)                     \r\n#define ETH_DMACHTDR_HTDAP_Msk                        (0xFFFFFFFFU << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_DMACHTDR_HTDAP                            ETH_DMACHTDR_HTDAP_Msk   /* Host transmit descriptor address pointer */\r\n\r\n/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */\r\n#define ETH_DMACHRDR_HRDAP_Pos                        (0U)                     \r\n#define ETH_DMACHRDR_HRDAP_Msk                        (0xFFFFFFFFU << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_DMACHRDR_HRDAP                            ETH_DMACHRDR_HRDAP_Msk   /* Host receive descriptor address pointer */\r\n\r\n/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */\r\n#define ETH_DMACHTBAR_HTBAP_Pos                       (0U)                     \r\n#define ETH_DMACHTBAR_HTBAP_Msk                       (0xFFFFFFFFU << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_DMACHTBAR_HTBAP                           ETH_DMACHTBAR_HTBAP_Msk  /* Host transmit buffer address pointer */\r\n\r\n/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */\r\n#define ETH_DMACHRBAR_HRBAP_Pos                       (0U)                     \r\n#define ETH_DMACHRBAR_HRBAP_Msk                       (0xFFFFFFFFU << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */\r\n#define ETH_DMACHRBAR_HRBAP                           ETH_DMACHRBAR_HRBAP_Msk  /* Host receive buffer address pointer */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                       USB_OTG                              */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bit definition for USB_OTG_GOTGCTL register  ********************/\r\n#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)                          \r\n#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */\r\n#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)                          \r\n#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */\r\n#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)                          \r\n#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */\r\n#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)                          \r\n#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */\r\n#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)                          \r\n#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */\r\n#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)                          \r\n#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */\r\n#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)                          \r\n#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */\r\n#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)                          \r\n#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */\r\n#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)                          \r\n#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */\r\n#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)                          \r\n#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */\r\n#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)                         \r\n#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */\r\n#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */\r\n#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)                         \r\n#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */\r\n#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */\r\n#define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)                         \r\n#define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */\r\n#define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */\r\n#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)                         \r\n#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */\r\n#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */\r\n#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)                         \r\n#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */\r\n#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)                         \r\n#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */\r\n#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */\r\n#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)                         \r\n#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */\r\n#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */\r\n#define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)                         \r\n#define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */\r\n#define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */\r\n\r\n/********************  Bit definition for USB_OTG_HCFG register  ********************/\r\n#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)                          \r\n#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */\r\n#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */\r\n#define USB_OTG_HCFG_FSLSPCS_0                   (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_HCFG_FSLSPCS_1                   (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_HCFG_FSLSS_Pos                   (2U)                          \r\n#define USB_OTG_HCFG_FSLSS_Msk                   (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */\r\n\r\n/********************  Bit definition for USB_OTG_DCFG register  ********************/\r\n#define USB_OTG_DCFG_DSPD_Pos                    (0U)                          \r\n#define USB_OTG_DCFG_DSPD_Msk                    (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */\r\n#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */\r\n#define USB_OTG_DCFG_DSPD_0                      (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_DCFG_DSPD_1                      (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)                          \r\n#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */\r\n\r\n#define USB_OTG_DCFG_DAD_Pos                     (4U)                          \r\n#define USB_OTG_DCFG_DAD_Msk                     (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */\r\n#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */\r\n#define USB_OTG_DCFG_DAD_0                       (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_DCFG_DAD_1                       (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_DCFG_DAD_2                       (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_DCFG_DAD_3                       (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_DCFG_DAD_4                       (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_DCFG_DAD_5                       (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_DCFG_DAD_6                       (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */\r\n\r\n#define USB_OTG_DCFG_PFIVL_Pos                   (11U)                         \r\n#define USB_OTG_DCFG_PFIVL_Msk                   (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */\r\n#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */\r\n#define USB_OTG_DCFG_PFIVL_0                     (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */\r\n#define USB_OTG_DCFG_PFIVL_1                     (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */\r\n\r\n#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)                         \r\n#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */\r\n#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */\r\n#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */\r\n#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */\r\n\r\n/********************  Bit definition for USB_OTG_PCGCR register  ********************/\r\n#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)                          \r\n#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */\r\n#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)                          \r\n#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */\r\n#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)                          \r\n#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */\r\n\r\n/********************  Bit definition for USB_OTG_GOTGINT register  ********************/\r\n#define USB_OTG_GOTGINT_SEDET_Pos                (2U)                          \r\n#define USB_OTG_GOTGINT_SEDET_Msk                (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */\r\n#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)                          \r\n#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */\r\n#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)                          \r\n#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */\r\n#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)                         \r\n#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */\r\n#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)                         \r\n#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */\r\n#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */\r\n#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)                         \r\n#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */\r\n#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */\r\n#define USB_OTG_GOTGINT_IDCHNG_Pos               (20U)                         \r\n#define USB_OTG_GOTGINT_IDCHNG_Msk               (0x1U << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */\r\n#define USB_OTG_GOTGINT_IDCHNG                   USB_OTG_GOTGINT_IDCHNG_Msk    /*!< Change in ID pin input value           */\r\n\r\n/********************  Bit definition for USB_OTG_DCTL register  ********************/\r\n#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)                          \r\n#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */\r\n#define USB_OTG_DCTL_SDIS_Pos                    (1U)                          \r\n#define USB_OTG_DCTL_SDIS_Msk                    (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */\r\n#define USB_OTG_DCTL_GINSTS_Pos                  (2U)                          \r\n#define USB_OTG_DCTL_GINSTS_Msk                  (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */\r\n#define USB_OTG_DCTL_GONSTS_Pos                  (3U)                          \r\n#define USB_OTG_DCTL_GONSTS_Msk                  (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */\r\n\r\n#define USB_OTG_DCTL_TCTL_Pos                    (4U)                          \r\n#define USB_OTG_DCTL_TCTL_Msk                    (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */\r\n#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */\r\n#define USB_OTG_DCTL_TCTL_0                      (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_DCTL_TCTL_1                      (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_DCTL_TCTL_2                      (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_DCTL_SGINAK_Pos                  (7U)                          \r\n#define USB_OTG_DCTL_SGINAK_Msk                  (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */\r\n#define USB_OTG_DCTL_CGINAK_Pos                  (8U)                          \r\n#define USB_OTG_DCTL_CGINAK_Msk                  (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */\r\n#define USB_OTG_DCTL_SGONAK_Pos                  (9U)                          \r\n#define USB_OTG_DCTL_SGONAK_Msk                  (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */\r\n#define USB_OTG_DCTL_CGONAK_Pos                  (10U)                         \r\n#define USB_OTG_DCTL_CGONAK_Msk                  (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */\r\n#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */\r\n#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)                         \r\n#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */\r\n#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */\r\n\r\n/********************  Bit definition for USB_OTG_HFIR register  ********************/\r\n#define USB_OTG_HFIR_FRIVL_Pos                   (0U)                          \r\n#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */\r\n\r\n/********************  Bit definition for USB_OTG_HFNUM register  ********************/\r\n#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)                          \r\n#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */\r\n#define USB_OTG_HFNUM_FTREM_Pos                  (16U)                         \r\n#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */\r\n#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */\r\n\r\n/********************  Bit definition for USB_OTG_DSTS register  ********************/\r\n#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)                          \r\n#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */\r\n\r\n#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)                          \r\n#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */\r\n#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */\r\n#define USB_OTG_DSTS_ENUMSPD_0                   (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DSTS_ENUMSPD_1                   (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_DSTS_EERR_Pos                    (3U)                          \r\n#define USB_OTG_DSTS_EERR_Msk                    (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */\r\n#define USB_OTG_DSTS_FNSOF_Pos                   (8U)                          \r\n#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */\r\n#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */\r\n\r\n/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/\r\n#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)                          \r\n#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */\r\n#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)                          \r\n#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */\r\n#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */\r\n#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */\r\n#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */\r\n#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */\r\n#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */\r\n#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */\r\n#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)                          \r\n#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */\r\n#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)                          \r\n#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */\r\n#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)                          \r\n#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */\r\n\r\n/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/\r\n#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)                          \r\n#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */\r\n#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */\r\n#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)                          \r\n#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */\r\n#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)                          \r\n#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */\r\n#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)                          \r\n#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */\r\n#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)                         \r\n#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */\r\n#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */\r\n#define USB_OTG_GUSBCFG_TRDT_0                   (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */\r\n#define USB_OTG_GUSBCFG_TRDT_1                   (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */\r\n#define USB_OTG_GUSBCFG_TRDT_2                   (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */\r\n#define USB_OTG_GUSBCFG_TRDT_3                   (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */\r\n#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)                         \r\n#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */\r\n#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */\r\n#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)                         \r\n#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */\r\n#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)                         \r\n#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */\r\n#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */\r\n#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)                         \r\n#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */\r\n#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */\r\n#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)                         \r\n#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */\r\n#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */\r\n#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)                         \r\n#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */\r\n#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */\r\n#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)                         \r\n#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */\r\n#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */\r\n#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)                         \r\n#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */\r\n#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */\r\n#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)                         \r\n#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */\r\n#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */\r\n#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)                         \r\n#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */\r\n#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */\r\n#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)                         \r\n#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */\r\n#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */\r\n#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)                         \r\n#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */\r\n#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */\r\n#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)                         \r\n#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */\r\n#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */\r\n\r\n/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/\r\n#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)                          \r\n#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */\r\n#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)                          \r\n#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */\r\n#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)                          \r\n#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */\r\n#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)                          \r\n#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */\r\n#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)                          \r\n#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */\r\n#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)                          \r\n#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */\r\n#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */\r\n#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */\r\n#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)                         \r\n#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */\r\n#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */\r\n#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)                         \r\n#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */\r\n#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */\r\n\r\n/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/\r\n#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)                          \r\n#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */\r\n#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)                          \r\n#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */\r\n#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)                          \r\n#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */\r\n#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)                          \r\n#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */\r\n#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)                          \r\n#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */\r\n#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)                          \r\n#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */\r\n#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)                          \r\n#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */\r\n#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)                          \r\n#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */\r\n\r\n/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/\r\n#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)                          \r\n#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */\r\n#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)                         \r\n#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */\r\n#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */\r\n#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */\r\n#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */\r\n#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */\r\n#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */\r\n#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */\r\n#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */\r\n#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */\r\n\r\n#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)                         \r\n#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */\r\n#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */\r\n#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */\r\n#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */\r\n#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */\r\n#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */\r\n#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */\r\n#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */\r\n#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */\r\n#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */\r\n\r\n/********************  Bit definition for USB_OTG_HAINT register  ********************/\r\n#define USB_OTG_HAINT_HAINT_Pos                  (0U)                          \r\n#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */\r\n\r\n/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/\r\n#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)                          \r\n#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */\r\n#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)                          \r\n#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */\r\n#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)                          \r\n#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */\r\n#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)                          \r\n#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */\r\n#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)                          \r\n#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1U << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */\r\n#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)                          \r\n#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */\r\n#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)                          \r\n#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */\r\n#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)                          \r\n#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */\r\n\r\n/********************  Bit definition for USB_OTG_GINTSTS register  ********************/\r\n#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)                          \r\n#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */\r\n#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)                          \r\n#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */\r\n#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)                          \r\n#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */\r\n#define USB_OTG_GINTSTS_SOF_Pos                  (3U)                          \r\n#define USB_OTG_GINTSTS_SOF_Msk                  (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */\r\n#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)                          \r\n#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */\r\n#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)                          \r\n#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */\r\n#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)                          \r\n#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */\r\n#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)                          \r\n#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */\r\n#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)                         \r\n#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */\r\n#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */\r\n#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)                         \r\n#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */\r\n#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */\r\n#define USB_OTG_GINTSTS_USBRST_Pos               (12U)                         \r\n#define USB_OTG_GINTSTS_USBRST_Msk               (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */\r\n#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */\r\n#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)                         \r\n#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */\r\n#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */\r\n#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)                         \r\n#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */\r\n#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */\r\n#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)                         \r\n#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */\r\n#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */\r\n#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)                         \r\n#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */\r\n#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */\r\n#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)                         \r\n#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */\r\n#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */\r\n#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)                         \r\n#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */\r\n#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */\r\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)                         \r\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */\r\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */\r\n#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)                         \r\n#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */\r\n#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */\r\n#define USB_OTG_GINTSTS_RSTDET_Pos               (23U)                         \r\n#define USB_OTG_GINTSTS_RSTDET_Msk               (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */\r\n#define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */\r\n#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)                         \r\n#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */\r\n#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */\r\n#define USB_OTG_GINTSTS_HCINT_Pos                (25U)                         \r\n#define USB_OTG_GINTSTS_HCINT_Msk                (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */\r\n#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */\r\n#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)                         \r\n#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */\r\n#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */\r\n#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)                         \r\n#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */\r\n#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */\r\n#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)                         \r\n#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */\r\n#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */\r\n#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)                         \r\n#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */\r\n#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */\r\n#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)                         \r\n#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */\r\n#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */\r\n#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)                         \r\n#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */\r\n#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */\r\n\r\n/********************  Bit definition for USB_OTG_GINTMSK register  ********************/\r\n#define USB_OTG_GINTMSK_MMISM_Pos                (1U)                          \r\n#define USB_OTG_GINTMSK_MMISM_Msk                (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */\r\n#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)                          \r\n#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */\r\n#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)                          \r\n#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */\r\n#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)                          \r\n#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */\r\n#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)                          \r\n#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */\r\n#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)                          \r\n#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */\r\n#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)                          \r\n#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */\r\n#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)                         \r\n#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */\r\n#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */\r\n#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)                         \r\n#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */\r\n#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */\r\n#define USB_OTG_GINTMSK_USBRST_Pos               (12U)                         \r\n#define USB_OTG_GINTMSK_USBRST_Msk               (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */\r\n#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */\r\n#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)                         \r\n#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */\r\n#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */\r\n#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)                         \r\n#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */\r\n#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */\r\n#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)                         \r\n#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */\r\n#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */\r\n#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)                         \r\n#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */\r\n#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)                         \r\n#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */\r\n#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */\r\n#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)                         \r\n#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */\r\n#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */\r\n#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)                         \r\n#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */\r\n#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */\r\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)                         \r\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */\r\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */\r\n#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)                         \r\n#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */\r\n#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */\r\n#define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)                         \r\n#define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1U << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */\r\n#define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                       */\r\n#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)                         \r\n#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */\r\n#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */\r\n#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)                         \r\n#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */\r\n#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */\r\n#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)                         \r\n#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */\r\n#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */\r\n#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)                         \r\n#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */\r\n#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */\r\n#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)                         \r\n#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */\r\n#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */\r\n#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)                         \r\n#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */\r\n#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */\r\n#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)                         \r\n#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */\r\n#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */\r\n#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)                         \r\n#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */\r\n#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */\r\n\r\n/********************  Bit definition for USB_OTG_DAINT register  ********************/\r\n#define USB_OTG_DAINT_IEPINT_Pos                 (0U)                          \r\n#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */\r\n#define USB_OTG_DAINT_OEPINT_Pos                 (16U)                         \r\n#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */\r\n#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */\r\n\r\n/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/\r\n#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)                          \r\n#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */\r\n\r\n/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/\r\n#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)                          \r\n#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */\r\n#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */\r\n#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)                          \r\n#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */\r\n#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */\r\n#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)                         \r\n#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */\r\n#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */\r\n#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)                         \r\n#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */\r\n#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */\r\n\r\n/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/\r\n#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)                          \r\n#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */\r\n#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)                         \r\n#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */\r\n#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */\r\n\r\n/********************  Bit definition for OTG register  ********************/\r\n\r\n#define USB_OTG_CHNUM_Pos                        (0U)                          \r\n#define USB_OTG_CHNUM_Msk                        (0xFU << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */\r\n#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */\r\n#define USB_OTG_CHNUM_0                          (0x1U << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */\r\n#define USB_OTG_CHNUM_1                          (0x2U << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */\r\n#define USB_OTG_CHNUM_2                          (0x4U << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */\r\n#define USB_OTG_CHNUM_3                          (0x8U << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */\r\n#define USB_OTG_BCNT_Pos                         (4U)                          \r\n#define USB_OTG_BCNT_Msk                         (0x7FFU << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */\r\n#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */\r\n\r\n#define USB_OTG_DPID_Pos                         (15U)                         \r\n#define USB_OTG_DPID_Msk                         (0x3U << USB_OTG_DPID_Pos)    /*!< 0x00018000 */\r\n#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */\r\n#define USB_OTG_DPID_0                           (0x1U << USB_OTG_DPID_Pos)    /*!< 0x00008000 */\r\n#define USB_OTG_DPID_1                           (0x2U << USB_OTG_DPID_Pos)    /*!< 0x00010000 */\r\n\r\n#define USB_OTG_PKTSTS_Pos                       (17U)                         \r\n#define USB_OTG_PKTSTS_Msk                       (0xFU << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */\r\n#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */\r\n#define USB_OTG_PKTSTS_0                         (0x1U << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */\r\n#define USB_OTG_PKTSTS_1                         (0x2U << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */\r\n#define USB_OTG_PKTSTS_2                         (0x4U << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */\r\n#define USB_OTG_PKTSTS_3                         (0x8U << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */\r\n\r\n#define USB_OTG_EPNUM_Pos                        (0U)                          \r\n#define USB_OTG_EPNUM_Msk                        (0xFU << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */\r\n#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */\r\n#define USB_OTG_EPNUM_0                          (0x1U << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */\r\n#define USB_OTG_EPNUM_1                          (0x2U << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */\r\n#define USB_OTG_EPNUM_2                          (0x4U << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */\r\n#define USB_OTG_EPNUM_3                          (0x8U << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */\r\n\r\n#define USB_OTG_FRMNUM_Pos                       (21U)                         \r\n#define USB_OTG_FRMNUM_Msk                       (0xFU << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */\r\n#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */\r\n#define USB_OTG_FRMNUM_0                         (0x1U << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */\r\n#define USB_OTG_FRMNUM_1                         (0x2U << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */\r\n#define USB_OTG_FRMNUM_2                         (0x4U << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */\r\n#define USB_OTG_FRMNUM_3                         (0x8U << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */\r\n\r\n/********************  Bit definition for OTG register  ********************/\r\n\r\n#define USB_OTG_CHNUM_Pos                        (0U)                          \r\n#define USB_OTG_CHNUM_Msk                        (0xFU << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */\r\n#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */\r\n#define USB_OTG_CHNUM_0                          (0x1U << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */\r\n#define USB_OTG_CHNUM_1                          (0x2U << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */\r\n#define USB_OTG_CHNUM_2                          (0x4U << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */\r\n#define USB_OTG_CHNUM_3                          (0x8U << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */\r\n#define USB_OTG_BCNT_Pos                         (4U)                          \r\n#define USB_OTG_BCNT_Msk                         (0x7FFU << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */\r\n#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */\r\n\r\n#define USB_OTG_DPID_Pos                         (15U)                         \r\n#define USB_OTG_DPID_Msk                         (0x3U << USB_OTG_DPID_Pos)    /*!< 0x00018000 */\r\n#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */\r\n#define USB_OTG_DPID_0                           (0x1U << USB_OTG_DPID_Pos)    /*!< 0x00008000 */\r\n#define USB_OTG_DPID_1                           (0x2U << USB_OTG_DPID_Pos)    /*!< 0x00010000 */\r\n\r\n#define USB_OTG_PKTSTS_Pos                       (17U)                         \r\n#define USB_OTG_PKTSTS_Msk                       (0xFU << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */\r\n#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */\r\n#define USB_OTG_PKTSTS_0                         (0x1U << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */\r\n#define USB_OTG_PKTSTS_1                         (0x2U << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */\r\n#define USB_OTG_PKTSTS_2                         (0x4U << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */\r\n#define USB_OTG_PKTSTS_3                         (0x8U << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */\r\n\r\n#define USB_OTG_EPNUM_Pos                        (0U)                          \r\n#define USB_OTG_EPNUM_Msk                        (0xFU << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */\r\n#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */\r\n#define USB_OTG_EPNUM_0                          (0x1U << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */\r\n#define USB_OTG_EPNUM_1                          (0x2U << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */\r\n#define USB_OTG_EPNUM_2                          (0x4U << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */\r\n#define USB_OTG_EPNUM_3                          (0x8U << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */\r\n\r\n#define USB_OTG_FRMNUM_Pos                       (21U)                         \r\n#define USB_OTG_FRMNUM_Msk                       (0xFU << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */\r\n#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */\r\n#define USB_OTG_FRMNUM_0                         (0x1U << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */\r\n#define USB_OTG_FRMNUM_1                         (0x2U << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */\r\n#define USB_OTG_FRMNUM_2                         (0x4U << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */\r\n#define USB_OTG_FRMNUM_3                         (0x8U << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */\r\n\r\n/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/\r\n#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)                          \r\n#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */\r\n\r\n/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/\r\n#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)                          \r\n#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */\r\n\r\n/********************  Bit definition for OTG register  ********************/\r\n#define USB_OTG_NPTXFSA_Pos                      (0U)                          \r\n#define USB_OTG_NPTXFSA_Msk                      (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */\r\n#define USB_OTG_NPTXFD_Pos                       (16U)                         \r\n#define USB_OTG_NPTXFD_Msk                       (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */\r\n#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */\r\n#define USB_OTG_TX0FSA_Pos                       (0U)                          \r\n#define USB_OTG_TX0FSA_Msk                       (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */\r\n#define USB_OTG_TX0FD_Pos                        (16U)                         \r\n#define USB_OTG_TX0FD_Msk                        (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */\r\n#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */\r\n\r\n/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/\r\n#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)                          \r\n#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */\r\n#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */\r\n\r\n/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/\r\n#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)                          \r\n#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */\r\n\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)                         \r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */\r\n\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)                         \r\n#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */\r\n\r\n/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/\r\n#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)                          \r\n#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */\r\n#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)                          \r\n#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */\r\n\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)                          \r\n#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */\r\n#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)                         \r\n#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */\r\n#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */\r\n\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)                         \r\n#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */\r\n#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)                         \r\n#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */\r\n#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */\r\n\r\n/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/\r\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)                          \r\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */\r\n\r\n/********************  Bit definition for USB_OTG_DEACHINT register  ********************/\r\n#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)                          \r\n#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */\r\n#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)                         \r\n#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */\r\n\r\n/********************  Bit definition for USB_OTG_GCCFG register  ********************/\r\n#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)                         \r\n#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */\r\n#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */\r\n#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)                         \r\n#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */\r\n#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< USB VBUS Detection Enable */\r\n\r\n/********************  Bit definition for USB_OTG_GPWRDN) register  ********************/\r\n#define USB_OTG_GPWRDN_ADPMEN_Pos                (0U)                          \r\n#define USB_OTG_GPWRDN_ADPMEN_Msk                (0x1U << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_GPWRDN_ADPMEN                    USB_OTG_GPWRDN_ADPMEN_Msk     /*!< ADP module enable */\r\n#define USB_OTG_GPWRDN_ADPIF_Pos                 (23U)                         \r\n#define USB_OTG_GPWRDN_ADPIF_Msk                 (0x1U << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */\r\n#define USB_OTG_GPWRDN_ADPIF                     USB_OTG_GPWRDN_ADPIF_Msk      /*!< ADP Interrupt flag */\r\n\r\n/********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/\r\n#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)                          \r\n#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */\r\n#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)                         \r\n#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */\r\n\r\n/********************  Bit definition for USB_OTG_CID register  ********************/\r\n#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)                          \r\n#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */\r\n#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */\r\n\r\n/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/\r\n#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)                          \r\n#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */\r\n#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)                          \r\n#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */\r\n#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)                          \r\n#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */\r\n#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */\r\n#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)                          \r\n#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */\r\n#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)                          \r\n#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */\r\n#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)                          \r\n#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */\r\n#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */\r\n#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)                         \r\n#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */\r\n#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */\r\n#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)                         \r\n#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */\r\n#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */\r\n#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)                         \r\n#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */\r\n#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */\r\n#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)                         \r\n#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */\r\n#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */\r\n#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)                         \r\n#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */\r\n#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */\r\n#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)                         \r\n#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */\r\n#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */\r\n#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)                         \r\n#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */\r\n#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */\r\n#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)                         \r\n#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */\r\n#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */\r\n#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)                         \r\n#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */\r\n#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */\r\n\r\n/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/\r\n#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)                          \r\n#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */\r\n#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)                          \r\n#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */\r\n#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)                          \r\n#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */\r\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)                          \r\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */\r\n#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)                          \r\n#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */\r\n#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)                          \r\n#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */\r\n#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)                          \r\n#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask                                */\r\n#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)                          \r\n#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                                */\r\n#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)                         \r\n#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\r\n#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                                */\r\n\r\n/********************  Bit definition for USB_OTG_HPRT register  ********************/\r\n#define USB_OTG_HPRT_PCSTS_Pos                   (0U)                          \r\n#define USB_OTG_HPRT_PCSTS_Msk                   (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */\r\n#define USB_OTG_HPRT_PCDET_Pos                   (1U)                          \r\n#define USB_OTG_HPRT_PCDET_Msk                   (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */\r\n#define USB_OTG_HPRT_PENA_Pos                    (2U)                          \r\n#define USB_OTG_HPRT_PENA_Msk                    (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */\r\n#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)                          \r\n#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */\r\n#define USB_OTG_HPRT_POCA_Pos                    (4U)                          \r\n#define USB_OTG_HPRT_POCA_Msk                    (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */\r\n#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)                          \r\n#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */\r\n#define USB_OTG_HPRT_PRES_Pos                    (6U)                          \r\n#define USB_OTG_HPRT_PRES_Msk                    (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume                */\r\n#define USB_OTG_HPRT_PSUSP_Pos                   (7U)                          \r\n#define USB_OTG_HPRT_PSUSP_Msk                   (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend               */\r\n#define USB_OTG_HPRT_PRST_Pos                    (8U)                          \r\n#define USB_OTG_HPRT_PRST_Msk                    (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset                 */\r\n\r\n#define USB_OTG_HPRT_PLSTS_Pos                   (10U)                         \r\n#define USB_OTG_HPRT_PLSTS_Msk                   (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */\r\n#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status           */\r\n#define USB_OTG_HPRT_PLSTS_0                     (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */\r\n#define USB_OTG_HPRT_PLSTS_1                     (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */\r\n#define USB_OTG_HPRT_PPWR_Pos                    (12U)                         \r\n#define USB_OTG_HPRT_PPWR_Msk                    (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */\r\n#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power                 */\r\n\r\n#define USB_OTG_HPRT_PTCTL_Pos                   (13U)                         \r\n#define USB_OTG_HPRT_PTCTL_Msk                   (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */\r\n#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control          */\r\n#define USB_OTG_HPRT_PTCTL_0                     (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */\r\n#define USB_OTG_HPRT_PTCTL_1                     (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */\r\n#define USB_OTG_HPRT_PTCTL_2                     (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */\r\n#define USB_OTG_HPRT_PTCTL_3                     (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */\r\n\r\n#define USB_OTG_HPRT_PSPD_Pos                    (17U)                         \r\n#define USB_OTG_HPRT_PSPD_Msk                    (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */\r\n#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed                 */\r\n#define USB_OTG_HPRT_PSPD_0                      (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_HPRT_PSPD_1                      (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */\r\n\r\n/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/\r\n#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)                          \r\n#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask         */\r\n#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)                          \r\n#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask          */\r\n#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)                          \r\n#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask                    */\r\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)                          \r\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask  */\r\n#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)                          \r\n#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask   */\r\n#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)                          \r\n#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask            */\r\n#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)                          \r\n#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask                     */\r\n#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)                          \r\n#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                        */\r\n#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)                         \r\n#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */\r\n#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask               */\r\n#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)                         \r\n#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\r\n#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                        */\r\n#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)                         \r\n#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */\r\n#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask                       */\r\n\r\n/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/\r\n#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)                          \r\n#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address            */\r\n#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)                         \r\n#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */\r\n#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth                    */\r\n\r\n/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/\r\n#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)                          \r\n#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\r\n#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size              */\r\n#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)                         \r\n#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */\r\n#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint              */\r\n#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)                         \r\n#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */\r\n#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame                   */\r\n#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)                         \r\n#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status                       */\r\n\r\n#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)                         \r\n#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\r\n#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type                    */\r\n#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */\r\n#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */\r\n#define USB_OTG_DIEPCTL_STALL_Pos                (21U)                         \r\n#define USB_OTG_DIEPCTL_STALL_Msk                (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */\r\n#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake                  */\r\n\r\n#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)                         \r\n#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */\r\n#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number                    */\r\n#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */\r\n#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */\r\n#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */\r\n#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */\r\n#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)                         \r\n#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */\r\n#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK                        */\r\n#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)                         \r\n#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */\r\n#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */\r\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)                         \r\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\r\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID                    */\r\n#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)                         \r\n#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\r\n#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame                    */\r\n#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)                         \r\n#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */\r\n#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable                 */\r\n#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)                         \r\n#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */\r\n#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable                  */\r\n\r\n/********************  Bit definition for USB_OTG_HCCHAR register  ********************/\r\n#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)                          \r\n#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */\r\n#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */\r\n\r\n#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)                         \r\n#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */\r\n#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */\r\n#define USB_OTG_HCCHAR_EPNUM_0                   (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */\r\n#define USB_OTG_HCCHAR_EPNUM_1                   (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */\r\n#define USB_OTG_HCCHAR_EPNUM_2                   (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */\r\n#define USB_OTG_HCCHAR_EPNUM_3                   (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */\r\n#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)                         \r\n#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */\r\n#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */\r\n#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)                         \r\n#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */\r\n\r\n#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)                         \r\n#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */\r\n#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */\r\n#define USB_OTG_HCCHAR_EPTYP_0                   (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */\r\n#define USB_OTG_HCCHAR_EPTYP_1                   (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */\r\n\r\n#define USB_OTG_HCCHAR_MC_Pos                    (20U)                         \r\n#define USB_OTG_HCCHAR_MC_Msk                    (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */\r\n#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */\r\n#define USB_OTG_HCCHAR_MC_0                      (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */\r\n#define USB_OTG_HCCHAR_MC_1                      (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */\r\n\r\n#define USB_OTG_HCCHAR_DAD_Pos                   (22U)                         \r\n#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */\r\n#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */\r\n#define USB_OTG_HCCHAR_DAD_0                     (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */\r\n#define USB_OTG_HCCHAR_DAD_1                     (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */\r\n#define USB_OTG_HCCHAR_DAD_2                     (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */\r\n#define USB_OTG_HCCHAR_DAD_3                     (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */\r\n#define USB_OTG_HCCHAR_DAD_4                     (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */\r\n#define USB_OTG_HCCHAR_DAD_5                     (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */\r\n#define USB_OTG_HCCHAR_DAD_6                     (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */\r\n#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)                         \r\n#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */\r\n#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */\r\n#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)                         \r\n#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */\r\n#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */\r\n#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)                         \r\n#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */\r\n#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */\r\n\r\n/********************  Bit definition for USB_OTG_HCSPLT register  ********************/\r\n\r\n#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)                          \r\n#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */\r\n#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */\r\n#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */\r\n\r\n#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)                          \r\n#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */\r\n#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */\r\n#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */\r\n#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */\r\n#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */\r\n#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */\r\n\r\n#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)                         \r\n#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */\r\n#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */\r\n#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */\r\n#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */\r\n#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)                         \r\n#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */\r\n#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */\r\n#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)                         \r\n#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */\r\n#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */\r\n\r\n/********************  Bit definition for USB_OTG_HCINT register  ********************/\r\n#define USB_OTG_HCINT_XFRC_Pos                   (0U)                          \r\n#define USB_OTG_HCINT_XFRC_Msk                   (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */\r\n#define USB_OTG_HCINT_CHH_Pos                    (1U)                          \r\n#define USB_OTG_HCINT_CHH_Msk                    (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */\r\n#define USB_OTG_HCINT_AHBERR_Pos                 (2U)                          \r\n#define USB_OTG_HCINT_AHBERR_Msk                 (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */\r\n#define USB_OTG_HCINT_STALL_Pos                  (3U)                          \r\n#define USB_OTG_HCINT_STALL_Msk                  (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */\r\n#define USB_OTG_HCINT_NAK_Pos                    (4U)                          \r\n#define USB_OTG_HCINT_NAK_Msk                    (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */\r\n#define USB_OTG_HCINT_ACK_Pos                    (5U)                          \r\n#define USB_OTG_HCINT_ACK_Msk                    (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */\r\n#define USB_OTG_HCINT_NYET_Pos                   (6U)                          \r\n#define USB_OTG_HCINT_NYET_Msk                   (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */\r\n#define USB_OTG_HCINT_TXERR_Pos                  (7U)                          \r\n#define USB_OTG_HCINT_TXERR_Msk                  (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */\r\n#define USB_OTG_HCINT_BBERR_Pos                  (8U)                          \r\n#define USB_OTG_HCINT_BBERR_Msk                  (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */\r\n#define USB_OTG_HCINT_FRMOR_Pos                  (9U)                          \r\n#define USB_OTG_HCINT_FRMOR_Msk                  (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */\r\n#define USB_OTG_HCINT_DTERR_Pos                  (10U)                         \r\n#define USB_OTG_HCINT_DTERR_Msk                  (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */\r\n#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */\r\n\r\n/********************  Bit definition for USB_OTG_DIEPINT register  ********************/\r\n#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)                          \r\n#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\r\n#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)                          \r\n#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\r\n#define USB_OTG_DIEPINT_TOC_Pos                  (3U)                          \r\n#define USB_OTG_DIEPINT_TOC_Msk                  (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */\r\n#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)                          \r\n#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */\r\n#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)                          \r\n#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */\r\n#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)                          \r\n#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */\r\n#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)                          \r\n#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */\r\n#define USB_OTG_DIEPINT_BNA_Pos                  (9U)                          \r\n#define USB_OTG_DIEPINT_BNA_Msk                  (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */\r\n#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)                         \r\n#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */\r\n#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */\r\n#define USB_OTG_DIEPINT_BERR_Pos                 (12U)                         \r\n#define USB_OTG_DIEPINT_BERR_Msk                 (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */\r\n#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */\r\n#define USB_OTG_DIEPINT_NAK_Pos                  (13U)                         \r\n#define USB_OTG_DIEPINT_NAK_Msk                  (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */\r\n#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */\r\n\r\n/********************  Bit definition for USB_OTG_HCINTMSK register  ********************/\r\n#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)                          \r\n#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */\r\n#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)                          \r\n#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */\r\n#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)                          \r\n#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */\r\n#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */\r\n#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)                          \r\n#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */\r\n#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)                          \r\n#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */\r\n#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)                          \r\n#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */\r\n#define USB_OTG_HCINTMSK_NYET_Pos                (6U)                          \r\n#define USB_OTG_HCINTMSK_NYET_Msk                (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */\r\n#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)                          \r\n#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */\r\n#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */\r\n#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)                          \r\n#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */\r\n#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */\r\n#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)                          \r\n#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */\r\n#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */\r\n#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)                         \r\n#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */\r\n#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */\r\n\r\n/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/\r\n\r\n#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)                          \r\n#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\r\n#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\r\n#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)                         \r\n#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\r\n#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */\r\n#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)                         \r\n#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */\r\n#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */\r\n/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/\r\n#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)                          \r\n#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\r\n#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */\r\n#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)                         \r\n#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\r\n#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */\r\n#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)                         \r\n#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */\r\n#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */\r\n#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)                         \r\n#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */\r\n#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */\r\n#define USB_OTG_HCTSIZ_DPID_0                    (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */\r\n#define USB_OTG_HCTSIZ_DPID_1                    (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */\r\n\r\n/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/\r\n#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)                          \r\n#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\r\n#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */\r\n\r\n/********************  Bit definition for USB_OTG_HCDMA register  ********************/\r\n#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)                          \r\n#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\r\n#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */\r\n\r\n/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/\r\n#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)                          \r\n#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */\r\n\r\n/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/\r\n#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)                          \r\n#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */\r\n#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */\r\n#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)                         \r\n#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */\r\n#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */\r\n\r\n/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/\r\n#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)                          \r\n#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\r\n#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */\r\n#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)                         \r\n#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */\r\n#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */\r\n#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)                         \r\n#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\r\n#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */\r\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)                         \r\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\r\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */\r\n#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)                         \r\n#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\r\n#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */\r\n#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)                         \r\n#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\r\n#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */\r\n#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */\r\n#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */\r\n#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)                         \r\n#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */\r\n#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */\r\n#define USB_OTG_DOEPCTL_STALL_Pos                (21U)                         \r\n#define USB_OTG_DOEPCTL_STALL_Msk                (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */\r\n#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */\r\n#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)                         \r\n#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */\r\n#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */\r\n#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)                         \r\n#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */\r\n#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */\r\n#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)                         \r\n#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */\r\n#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */\r\n#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)                         \r\n#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */\r\n#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */\r\n\r\n/********************  Bit definition for USB_OTG_DOEPINT register  ********************/\r\n#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)                          \r\n#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\r\n#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)                          \r\n#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\r\n#define USB_OTG_DOEPINT_STUP_Pos                 (3U)                          \r\n#define USB_OTG_DOEPINT_STUP_Msk                 (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */\r\n#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */\r\n#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)                          \r\n#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */\r\n#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)                          \r\n#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1U << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */\r\n#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< Status Phase Received For Control Write */\r\n#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)                          \r\n#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */\r\n#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */\r\n#define USB_OTG_DOEPINT_NYET_Pos                 (14U)                         \r\n#define USB_OTG_DOEPINT_NYET_Msk                 (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */\r\n#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */\r\n\r\n/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/\r\n#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)                          \r\n#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\r\n#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\r\n#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)                         \r\n#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\r\n#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */\r\n\r\n#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)                         \r\n#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */\r\n#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */\r\n#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */\r\n#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */\r\n\r\n/********************  Bit definition for PCGCCTL register  ********************/\r\n#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)                          \r\n#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */\r\n#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */\r\n#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)                          \r\n#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */\r\n#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */\r\n#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)                          \r\n#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */\r\n#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */\r\n\r\n\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup Exported_macros\r\n  * @{\r\n  */\r\n\r\n/******************************* ADC Instances ********************************/\r\n#define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \\\r\n                                       ((__INSTANCE__) == ADC2) || \\\r\n                                       ((__INSTANCE__) == ADC3))\r\n#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)\r\n\r\n#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)\r\n\r\n/******************************* CAN Instances ********************************/\r\n#define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \\\r\n                                           ((__INSTANCE__) == CAN2))\r\n/******************************* CRC Instances ********************************/\r\n#define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)\r\n\r\n/******************************* DAC Instances ********************************/\r\n#define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC1)\r\n\r\n/******************************* DCMI Instances *******************************/\r\n#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)\r\n\r\n\r\n/******************************* DMA2D Instances *******************************/\r\n#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)\r\n\r\n/******************************** DMA Instances *******************************/\r\n#define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \\\r\n                                              ((__INSTANCE__) == DMA1_Stream1) || \\\r\n                                              ((__INSTANCE__) == DMA1_Stream2) || \\\r\n                                              ((__INSTANCE__) == DMA1_Stream3) || \\\r\n                                              ((__INSTANCE__) == DMA1_Stream4) || \\\r\n                                              ((__INSTANCE__) == DMA1_Stream5) || \\\r\n                                              ((__INSTANCE__) == DMA1_Stream6) || \\\r\n                                              ((__INSTANCE__) == DMA1_Stream7) || \\\r\n                                              ((__INSTANCE__) == DMA2_Stream0) || \\\r\n                                              ((__INSTANCE__) == DMA2_Stream1) || \\\r\n                                              ((__INSTANCE__) == DMA2_Stream2) || \\\r\n                                              ((__INSTANCE__) == DMA2_Stream3) || \\\r\n                                              ((__INSTANCE__) == DMA2_Stream4) || \\\r\n                                              ((__INSTANCE__) == DMA2_Stream5) || \\\r\n                                              ((__INSTANCE__) == DMA2_Stream6) || \\\r\n                                              ((__INSTANCE__) == DMA2_Stream7))\r\n\r\n/******************************* GPIO Instances *******************************/\r\n#define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \\\r\n                                            ((__INSTANCE__) == GPIOB) || \\\r\n                                            ((__INSTANCE__) == GPIOC) || \\\r\n                                            ((__INSTANCE__) == GPIOD) || \\\r\n                                            ((__INSTANCE__) == GPIOE) || \\\r\n                                            ((__INSTANCE__) == GPIOF) || \\\r\n                                            ((__INSTANCE__) == GPIOG) || \\\r\n                                            ((__INSTANCE__) == GPIOH) || \\\r\n                                            ((__INSTANCE__) == GPIOI) || \\\r\n                                            ((__INSTANCE__) == GPIOJ) || \\\r\n                                            ((__INSTANCE__) == GPIOK))\r\n\r\n#define IS_GPIO_AF_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == GPIOA) || \\\r\n                                             ((__INSTANCE__) == GPIOB) || \\\r\n                                             ((__INSTANCE__) == GPIOC) || \\\r\n                                             ((__INSTANCE__) == GPIOD) || \\\r\n                                             ((__INSTANCE__) == GPIOE) || \\\r\n                                             ((__INSTANCE__) == GPIOF) || \\\r\n                                             ((__INSTANCE__) == GPIOG) || \\\r\n                                             ((__INSTANCE__) == GPIOH) || \\\r\n                                             ((__INSTANCE__) == GPIOI) || \\\r\n                                             ((__INSTANCE__) == GPIOJ) || \\\r\n                                             ((__INSTANCE__) == GPIOK))\r\n\r\n/****************************** CEC Instances *********************************/\r\n#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)\r\n\r\n/****************************** QSPI Instances *********************************/\r\n#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)\r\n\r\n\r\n/******************************** I2C Instances *******************************/\r\n#define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \\\r\n                                           ((__INSTANCE__) == I2C2) || \\\r\n                                           ((__INSTANCE__) == I2C3) || \\\r\n                                           ((__INSTANCE__) == I2C4))\r\n\r\n/****************************** SMBUS Instances *******************************/\r\n#define IS_SMBUS_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \\\r\n                                             ((__INSTANCE__) == I2C2) || \\\r\n                                             ((__INSTANCE__) == I2C3) || \\\r\n                                             ((__INSTANCE__) == I2C4))\r\n\r\n\r\n/******************************** I2S Instances *******************************/\r\n#define IS_I2S_ALL_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == SPI1) || \\\r\n                                            ((__INSTANCE__) == SPI2) || \\\r\n                                            ((__INSTANCE__) == SPI3))\r\n\r\n/******************************* LPTIM Instances ********************************/\r\n#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)\r\n\r\n/****************************** LTDC Instances ********************************/\r\n#define IS_LTDC_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == LTDC)\r\n\r\n\r\n\r\n\r\n/******************************* RNG Instances ********************************/\r\n#define IS_RNG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == RNG)\r\n\r\n/****************************** RTC Instances *********************************/\r\n#define IS_RTC_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == RTC)\r\n\r\n/******************************* SAI Instances ********************************/\r\n#define IS_SAI_ALL_INSTANCE(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \\\r\n                                         ((__PERIPH__) == SAI1_Block_B) || \\\r\n                                         ((__PERIPH__) == SAI2_Block_A) || \\\r\n                                         ((__PERIPH__) == SAI2_Block_B))\r\n/* Legacy define */\r\n#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE\r\n\r\n/******************************** SDMMC Instances *******************************/\r\n#define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SDMMC1)\r\n\r\n/****************************** SPDIFRX Instances *********************************/\r\n#define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)\r\n\r\n/******************************** SPI Instances *******************************/\r\n#define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \\\r\n                                           ((__INSTANCE__) == SPI2) || \\\r\n                                           ((__INSTANCE__) == SPI3) || \\\r\n                                           ((__INSTANCE__) == SPI4) || \\\r\n                                           ((__INSTANCE__) == SPI5) || \\\r\n                                           ((__INSTANCE__) == SPI6))\r\n\r\n/****************** TIM Instances : All supported instances *******************/\r\n#define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)   || \\\r\n                                   ((__INSTANCE__) == TIM2)   || \\\r\n                                   ((__INSTANCE__) == TIM3)   || \\\r\n                                   ((__INSTANCE__) == TIM4)   || \\\r\n                                   ((__INSTANCE__) == TIM5)   || \\\r\n                                   ((__INSTANCE__) == TIM6)   || \\\r\n                                   ((__INSTANCE__) == TIM7)   || \\\r\n                                   ((__INSTANCE__) == TIM8)   || \\\r\n                                   ((__INSTANCE__) == TIM9)   || \\\r\n                                   ((__INSTANCE__) == TIM10)  || \\\r\n                                   ((__INSTANCE__) == TIM11)  || \\\r\n                                   ((__INSTANCE__) == TIM12)  || \\\r\n                                   ((__INSTANCE__) == TIM13)  || \\\r\n                                   ((__INSTANCE__) == TIM14))\r\n\r\n/****************** TIM Instances : supporting 32 bits counter ****************/\r\n#define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2)   || \\\r\n                                               ((__INSTANCE__) == TIM5))\r\n\r\n/****************** TIM Instances : supporting the break function *************/\r\n#define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \\\r\n                                            ((INSTANCE) == TIM8))\r\n\r\n/************** TIM Instances : supporting Break source selection *************/\r\n#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \\\r\n                                               ((INSTANCE) == TIM8))\r\n\r\n/****************** TIM Instances : supporting 2 break inputs *****************/\r\n#define IS_TIM_BKIN2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \\\r\n                                            ((INSTANCE) == TIM8))\r\n\r\n/************* TIM Instances : at least 1 capture/compare channel *************/\r\n#define IS_TIM_CC1_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1)  || \\\r\n                                         ((__INSTANCE__) == TIM2)  || \\\r\n                                         ((__INSTANCE__) == TIM3)  || \\\r\n                                         ((__INSTANCE__) == TIM4)  || \\\r\n                                         ((__INSTANCE__) == TIM5)  || \\\r\n                                         ((__INSTANCE__) == TIM8)  || \\\r\n                                         ((__INSTANCE__) == TIM9)  || \\\r\n                                         ((__INSTANCE__) == TIM10) || \\\r\n                                         ((__INSTANCE__) == TIM11) || \\\r\n                                         ((__INSTANCE__) == TIM12) || \\\r\n                                         ((__INSTANCE__) == TIM13) || \\\r\n                                         ((__INSTANCE__) == TIM14))\r\n\r\n/************ TIM Instances : at least 2 capture/compare channels *************/\r\n#define IS_TIM_CC2_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1)  || \\\r\n                                         ((__INSTANCE__) == TIM2)  || \\\r\n                                         ((__INSTANCE__) == TIM3)  || \\\r\n                                         ((__INSTANCE__) == TIM4)  || \\\r\n                                         ((__INSTANCE__) == TIM5)  || \\\r\n                                         ((__INSTANCE__) == TIM8)  || \\\r\n                                         ((__INSTANCE__) == TIM9)  || \\\r\n                                         ((__INSTANCE__) == TIM12))\r\n\r\n/************ TIM Instances : at least 3 capture/compare channels *************/\r\n#define IS_TIM_CC3_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1) || \\\r\n                                         ((__INSTANCE__) == TIM2) || \\\r\n                                         ((__INSTANCE__) == TIM3) || \\\r\n                                         ((__INSTANCE__) == TIM4) || \\\r\n                                         ((__INSTANCE__) == TIM5) || \\\r\n                                         ((__INSTANCE__) == TIM8))\r\n\r\n/************ TIM Instances : at least 4 capture/compare channels *************/\r\n#define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\\r\n                                       ((__INSTANCE__) == TIM2) || \\\r\n                                       ((__INSTANCE__) == TIM3) || \\\r\n                                       ((__INSTANCE__) == TIM4) || \\\r\n                                       ((__INSTANCE__) == TIM5) || \\\r\n                                       ((__INSTANCE__) == TIM8))\r\n\r\n/****************** TIM Instances : at least 5 capture/compare channels *******/\r\n#define IS_TIM_CC5_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1)   || \\\r\n                                         ((__INSTANCE__) == TIM8))\r\n\r\n/****************** TIM Instances : at least 6 capture/compare channels *******/\r\n#define IS_TIM_CC6_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1)   || \\\r\n                                         ((__INSTANCE__) == TIM8))\r\n\r\n/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/\r\n#define IS_TIM_CCDMA_INSTANCE(__INSTANCE__)    (((__INSTANCE__) == TIM1)   || \\\r\n                                            ((__INSTANCE__) == TIM8))\r\n\r\n/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/\r\n#define IS_TIM_DMA_INSTANCE(__INSTANCE__)      (((__INSTANCE__) == TIM1)   || \\\r\n                                            ((__INSTANCE__) == TIM8)   || \\\r\n                                            ((__INSTANCE__) == TIM2)   || \\\r\n                                            ((__INSTANCE__) == TIM3)   || \\\r\n                                            ((__INSTANCE__) == TIM4)   || \\\r\n                                            ((__INSTANCE__) == TIM5)   || \\\r\n                                            ((__INSTANCE__) == TIM6)   || \\\r\n                                            ((__INSTANCE__) == TIM7))\r\n\r\n/************ TIM Instances : DMA requests generation (CCxDE) *****************/\r\n#define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\\r\n                                              ((__INSTANCE__) == TIM2) || \\\r\n                                              ((__INSTANCE__) == TIM3) || \\\r\n                                              ((__INSTANCE__) == TIM4) || \\\r\n                                              ((__INSTANCE__) == TIM5) || \\\r\n                                              ((__INSTANCE__) == TIM8))\r\n\r\n/******************** TIM Instances : DMA burst feature ***********************/\r\n#define IS_TIM_DMABURST_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1) || \\\r\n                                             ((__INSTANCE__) == TIM2) || \\\r\n                                             ((__INSTANCE__) == TIM3) || \\\r\n                                             ((__INSTANCE__) == TIM4) || \\\r\n                                             ((__INSTANCE__) == TIM5) || \\\r\n                                             ((__INSTANCE__) == TIM8))\r\n\r\n/****************** TIM Instances : supporting combined 3-phase PWM mode ******/\r\n#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \\\r\n                                       (((__INSTANCE__) == TIM1)    || \\\r\n                                        ((__INSTANCE__) == TIM8))\r\n\r\n/****************** TIM Instances : supporting counting mode selection ********/\r\n#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1) || \\\r\n                                                        ((__INSTANCE__) == TIM2) || \\\r\n                                                        ((__INSTANCE__) == TIM3) || \\\r\n                                                        ((__INSTANCE__) == TIM4) || \\\r\n                                                        ((__INSTANCE__) == TIM5) || \\\r\n                                                        ((__INSTANCE__) == TIM8))\r\n                                                        \r\n/****************** TIM Instances : supporting encoder interface **************/\r\n#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1)  || \\\r\n                                                      ((__INSTANCE__) == TIM2)  || \\\r\n                                                      ((__INSTANCE__) == TIM3)  || \\\r\n                                                      ((__INSTANCE__) == TIM4)  || \\\r\n                                                      ((__INSTANCE__) == TIM5)  || \\\r\n                                                      ((__INSTANCE__) == TIM8))\r\n                                                        \r\n/****************** TIM Instances : supporting OCxREF clear *******************/\r\n#define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\\\r\n                                  (((__INSTANCE__) == TIM2)    || \\\r\n                                   ((__INSTANCE__) == TIM3)    || \\\r\n                                   ((__INSTANCE__) == TIM4)    || \\\r\n                                   ((__INSTANCE__) == TIM5))\r\n\r\n/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/\r\n#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\\\r\n                                                 (((__INSTANCE__) == TIM1)    || \\\r\n                                                  ((__INSTANCE__) == TIM2)    || \\\r\n                                                  ((__INSTANCE__) == TIM3)    || \\\r\n                                                  ((__INSTANCE__) == TIM4)    || \\\r\n                                                  ((__INSTANCE__) == TIM5)    || \\\r\n                                                  ((__INSTANCE__) == TIM8))\r\n\r\n/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/\r\n#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\\\r\n                                                   (((__INSTANCE__) == TIM1)    || \\\r\n                                                    ((__INSTANCE__) == TIM2)    || \\\r\n                                                    ((__INSTANCE__) == TIM3)    || \\\r\n                                                    ((__INSTANCE__) == TIM4)    || \\\r\n                                                    ((__INSTANCE__) == TIM5)    || \\\r\n                                                    ((__INSTANCE__) == TIM8))\r\n\r\n/******************** TIM Instances : Advanced-control timers *****************/\r\n#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\\r\n                                            ((__INSTANCE__) == TIM8))\r\n\r\n/******************* TIM Instances : Timer input XOR function *****************/\r\n#define IS_TIM_XOR_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1) || \\\r\n                                         ((__INSTANCE__) == TIM2) || \\\r\n                                         ((__INSTANCE__) == TIM3) || \\\r\n                                         ((__INSTANCE__) == TIM4) || \\\r\n                                         ((__INSTANCE__) == TIM5) || \\\r\n                                         ((__INSTANCE__) == TIM8))\r\n\r\n/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/\r\n#define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\\r\n                                          ((__INSTANCE__) == TIM2) || \\\r\n                                          ((__INSTANCE__) == TIM3) || \\\r\n                                          ((__INSTANCE__) == TIM4) || \\\r\n                                          ((__INSTANCE__) == TIM5) || \\\r\n                                          ((__INSTANCE__) == TIM6) || \\\r\n                                          ((__INSTANCE__) == TIM7) || \\\r\n                                          ((__INSTANCE__) == TIM8))\r\n\r\n/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/\r\n#define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\\r\n                                         ((__INSTANCE__) == TIM2) || \\\r\n                                         ((__INSTANCE__) == TIM3) || \\\r\n                                         ((__INSTANCE__) == TIM4) || \\\r\n                                         ((__INSTANCE__) == TIM5) || \\\r\n                                         ((__INSTANCE__) == TIM8) || \\\r\n                                         ((__INSTANCE__) == TIM9) || \\\r\n                                         ((__INSTANCE__) == TIM12))\r\n\r\n/***************** TIM Instances : external trigger input available ************/\r\n#define IS_TIM_ETR_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1) || \\\r\n                                        ((__INSTANCE__) == TIM2) || \\\r\n                                        ((__INSTANCE__) == TIM3) || \\\r\n                                        ((__INSTANCE__) == TIM4) || \\\r\n                                        ((__INSTANCE__) == TIM5) || \\\r\n                                        ((__INSTANCE__) == TIM8))\r\n\r\n/****************** TIM Instances : remapping capability **********************/\r\n#define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2)  || \\\r\n                                         ((__INSTANCE__) == TIM5)  || \\\r\n                                         ((__INSTANCE__) == TIM11))\r\n\r\n/******************* TIM Instances : output(s) available **********************/\r\n#define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \\\r\n    ((((__INSTANCE__) == TIM1) &&                  \\\r\n     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_4) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_5) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_6)))           \\\r\n    ||                                         \\\r\n    (((__INSTANCE__) == TIM2) &&                   \\\r\n     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_4)))           \\\r\n    ||                                         \\\r\n    (((__INSTANCE__) == TIM3) &&                   \\\r\n     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_4)))           \\\r\n    ||                                         \\\r\n    (((__INSTANCE__) == TIM4) &&                   \\\r\n     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_4)))           \\\r\n    ||                                         \\\r\n    (((__INSTANCE__) == TIM5) &&                   \\\r\n     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_4)))           \\\r\n    ||                                         \\\r\n    (((__INSTANCE__) == TIM8) &&                   \\\r\n     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_4) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_5) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_6)))           \\\r\n    ||                                         \\\r\n    (((__INSTANCE__) == TIM9) &&                   \\\r\n     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_2)))           \\\r\n    ||                                         \\\r\n    (((__INSTANCE__) == TIM10) &&                  \\\r\n     (((__CHANNEL__) == TIM_CHANNEL_1)))           \\\r\n    ||                                         \\\r\n    (((__INSTANCE__) == TIM11) &&                  \\\r\n     (((__CHANNEL__) == TIM_CHANNEL_1)))           \\\r\n    ||                                         \\\r\n    (((__INSTANCE__) == TIM12) &&                  \\\r\n     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_2)))           \\\r\n    ||                                         \\\r\n    (((__INSTANCE__) == TIM13) &&                  \\\r\n     (((__CHANNEL__) == TIM_CHANNEL_1)))           \\\r\n    ||                                         \\\r\n    (((__INSTANCE__) == TIM14) &&                  \\\r\n     (((__CHANNEL__) == TIM_CHANNEL_1))))\r\n\r\n/************ TIM Instances : complementary output(s) available ***************/\r\n#define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \\\r\n   ((((__INSTANCE__) == TIM1) &&                    \\\r\n     (((__CHANNEL__) == TIM_CHANNEL_1) ||           \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_2) ||           \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_3)))            \\\r\n    ||                                          \\\r\n    (((__INSTANCE__) == TIM8) &&                    \\\r\n     (((__CHANNEL__) == TIM_CHANNEL_1) ||           \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_2) ||           \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_3))))\r\n\r\n/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/\r\n#define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\\\r\n  (((__INSTANCE__) == TIM1)    || \\\r\n   ((__INSTANCE__) == TIM8) )\r\n\r\n/****************** TIM Instances : supporting synchronization ****************/\r\n#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\\\r\n    (((__INSTANCE__) == TIM1)    || \\\r\n     ((__INSTANCE__) == TIM2)    || \\\r\n     ((__INSTANCE__) == TIM3)    || \\\r\n     ((__INSTANCE__) == TIM4)    || \\\r\n     ((__INSTANCE__) == TIM5)    || \\\r\n     ((__INSTANCE__) == TIM6)    || \\\r\n     ((__INSTANCE__) == TIM7)    || \\\r\n     ((__INSTANCE__) == TIM8))\r\n\t \r\n/****************** TIM Instances : supporting clock division *****************/\r\n#define IS_TIM_CLOCK_DIVISION_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1)    || \\\r\n                                                    ((__INSTANCE__) == TIM2)    || \\\r\n                                                    ((__INSTANCE__) == TIM3)    || \\\r\n                                                    ((__INSTANCE__) == TIM4)    || \\\r\n                                                    ((__INSTANCE__) == TIM5)    || \\\r\n                                                    ((__INSTANCE__) == TIM8)    || \\\r\n                                                    ((__INSTANCE__) == TIM9)    || \\\r\n                                                    ((__INSTANCE__) == TIM10)   || \\\r\n                                                    ((__INSTANCE__) == TIM11)   || \\\r\n                                                    ((__INSTANCE__) == TIM12)   || \\\r\n                                                    ((__INSTANCE__) == TIM13)   || \\\r\n                                                    ((__INSTANCE__) == TIM14))\r\n                                                        \r\n/****************** TIM Instances : supporting repetition counter *************/\r\n#define IS_TIM_REPETITION_COUNTER_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1)  || \\\r\n                                                        ((__INSTANCE__) == TIM8))\r\n                                                        \r\n/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/\r\n#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\\r\n                                                        ((__INSTANCE__) == TIM2) || \\\r\n                                                        ((__INSTANCE__) == TIM3) || \\\r\n                                                        ((__INSTANCE__) == TIM4) || \\\r\n                                                        ((__INSTANCE__) == TIM5) || \\\r\n                                                        ((__INSTANCE__) == TIM8) || \\\r\n                                                        ((__INSTANCE__) == TIM9) || \\\r\n                                                        ((__INSTANCE__) == TIM12))\r\n                                                        \r\n/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/\r\n#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\\r\n                                                        ((__INSTANCE__) == TIM2) || \\\r\n                                                        ((__INSTANCE__) == TIM3) || \\\r\n                                                        ((__INSTANCE__) == TIM4) || \\\r\n                                                        ((__INSTANCE__) == TIM5) || \\\r\n                                                        ((__INSTANCE__) == TIM8))\r\n                                                        \r\n/****************** TIM Instances : supporting Hall sensor interface **********/\r\n#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)   || \\\r\n                                                         ((__INSTANCE__) == TIM2)   || \\\r\n                                                         ((__INSTANCE__) == TIM3)   || \\\r\n                                                         ((__INSTANCE__) == TIM4)   || \\\r\n                                                         ((__INSTANCE__) == TIM5)   || \\\r\n                                                         ((__INSTANCE__) == TIM8))\r\n                                                         \r\n/****************** TIM Instances : supporting commutation event generation ***/\r\n#define IS_TIM_COMMUTATION_EVENT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)   || \\\r\n                                                         ((__INSTANCE__) == TIM8)) \t \r\n\r\n/******************** USART Instances : Synchronous mode **********************/\r\n#define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\\r\n                                         ((__INSTANCE__) == USART2) || \\\r\n                                         ((__INSTANCE__) == USART3) || \\\r\n                                         ((__INSTANCE__) == USART6))\r\n\r\n/******************** UART Instances : Asynchronous mode **********************/\r\n#define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\\r\n                                    ((__INSTANCE__) == USART2) || \\\r\n                                    ((__INSTANCE__) == USART3) || \\\r\n                                    ((__INSTANCE__) == UART4)  || \\\r\n                                    ((__INSTANCE__) == UART5)  || \\\r\n                                    ((__INSTANCE__) == USART6) || \\\r\n                                    ((__INSTANCE__) == UART7)  || \\\r\n                                    ((__INSTANCE__) == UART8))\r\n\r\n/****************** UART Instances : Auto Baud Rate detection ****************/\r\n#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\\r\n                                    ((__INSTANCE__) == USART2) || \\\r\n                                    ((__INSTANCE__) == USART3) || \\\r\n                                    ((__INSTANCE__) == USART6))\r\n\r\n/****************** UART Instances : Driver Enable *****************/\r\n#define IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\\r\n                                    ((__INSTANCE__) == USART2) || \\\r\n                                    ((__INSTANCE__) == USART3) || \\\r\n                                    ((__INSTANCE__) == UART4)  || \\\r\n                                    ((__INSTANCE__) == UART5)  || \\\r\n                                    ((__INSTANCE__) == USART6) || \\\r\n                                    ((__INSTANCE__) == UART7)  || \\\r\n                                    ((__INSTANCE__) == UART8))\r\n\r\n/******************** UART Instances : Half-Duplex mode **********************/\r\n#define IS_UART_HALFDUPLEX_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == USART1) || \\\r\n                                    ((__INSTANCE__) == USART2) || \\\r\n                                    ((__INSTANCE__) == USART3) || \\\r\n                                    ((__INSTANCE__) == UART4)  || \\\r\n                                    ((__INSTANCE__) == UART5)  || \\\r\n                                    ((__INSTANCE__) == USART6) || \\\r\n                                    ((__INSTANCE__) == UART7)  || \\\r\n                                    ((__INSTANCE__) == UART8))\r\n\r\n/****************** UART Instances : Hardware Flow control ********************/\r\n#define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\\r\n                                    ((__INSTANCE__) == USART2) || \\\r\n                                    ((__INSTANCE__) == USART3) || \\\r\n                                    ((__INSTANCE__) == UART4)  || \\\r\n                                    ((__INSTANCE__) == UART5)  || \\\r\n                                    ((__INSTANCE__) == USART6) || \\\r\n                                    ((__INSTANCE__) == UART7)  || \\\r\n                                    ((__INSTANCE__) == UART8))\r\n\r\n/******************** UART Instances : LIN mode **********************/\r\n#define IS_UART_LIN_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == USART1) || \\\r\n                                    ((__INSTANCE__) == USART2) || \\\r\n                                    ((__INSTANCE__) == USART3) || \\\r\n                                    ((__INSTANCE__) == UART4)  || \\\r\n                                    ((__INSTANCE__) == UART5)  || \\\r\n                                    ((__INSTANCE__) == USART6) || \\\r\n                                    ((__INSTANCE__) == UART7)  || \\\r\n                                    ((__INSTANCE__) == UART8))\r\n\r\n/********************* UART Instances : Smart card mode ***********************/\r\n#define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\\r\n                                         ((__INSTANCE__) == USART2) || \\\r\n                                         ((__INSTANCE__) == USART3) || \\\r\n                                         ((__INSTANCE__) == USART6))\r\n\r\n/*********************** UART Instances : IRDA mode ***************************/\r\n#define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\\r\n                                    ((__INSTANCE__) == USART2) || \\\r\n                                    ((__INSTANCE__) == USART3) || \\\r\n                                    ((__INSTANCE__) == UART4)  || \\\r\n                                    ((__INSTANCE__) == UART5)  || \\\r\n                                    ((__INSTANCE__) == USART6) || \\\r\n                                    ((__INSTANCE__) == UART7)  || \\\r\n                                    ((__INSTANCE__) == UART8))\r\n\r\n/****************************** IWDG Instances ********************************/\r\n#define IS_IWDG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == IWDG)\r\n\r\n/****************************** WWDG Instances ********************************/\r\n#define IS_WWDG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == WWDG)\r\n\r\n\r\n/******************************************************************************/\r\n/*  For a painless codes migration between the STM32F7xx device product       */\r\n/*  lines, the aliases defined below are put in place to overcome the         */\r\n/*  differences in the interrupt handlers and IRQn definitions.               */\r\n/*  No need to update developed interrupt code when moving across             */\r\n/*  product lines within the same STM32F7 Family                              */\r\n/******************************************************************************/\r\n\r\n/* Aliases for __IRQn */\r\n#define HASH_RNG_IRQn              RNG_IRQn\r\n\r\n/* Aliases for __IRQHandler */\r\n#define HASH_RNG_IRQHandler        RNG_IRQHandler\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif /* __cplusplus */\r\n\r\n#endif /* __STM32F746xx_H */\r\n\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/bsp/opencr/stm32f7xx.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx.h\r\n  * @author  MCD Application Team\r\n  * @brief   CMSIS STM32F7xx Device Peripheral Access Layer Header File.\r\n  *\r\n  *          The file is the unique include file that the application programmer\r\n  *          is using in the C source code, usually in main.c. This file contains:\r\n  *           - Configuration section that allows to select:\r\n  *              - The STM32F7xx device used in the target application\r\n  *              - To use or not the peripherals drivers in application code(i.e.\r\n  *                code will be based on direct access to peripherals registers\r\n  *                rather than drivers API), this option is controlled by\r\n  *                \"#define USE_HAL_DRIVER\"\r\n  *\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/** @addtogroup CMSIS\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup stm32f7xx\r\n  * @{\r\n  */\r\n\r\n#ifndef __STM32F7xx_H\r\n#define __STM32F7xx_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif /* __cplusplus */\r\n\r\n/** @addtogroup Library_configuration_section\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief STM32 Family\r\n  */\r\n#if !defined  (STM32F7)\r\n#define STM32F7\r\n#endif /* STM32F7 */\r\n\r\n/* Uncomment the line below according to the target STM32 device used in your\r\n   application\r\n  */\r\n#if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx) && !defined (STM32F767xx) && \\\r\n    !defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx) && !defined (STM32F722xx) && \\\r\n    !defined (STM32F723xx) && !defined (STM32F732xx) && !defined (STM32F733xx) && !defined (STM32F730xx) && \\\r\n    !defined (STM32F750xx)\r\n\r\n  /* #define STM32F756xx */   /*!< STM32F756VG, STM32F756ZG, STM32F756ZG, STM32F756IG, STM32F756BG,\r\n                                   STM32F756NG Devices */\r\n  /* #define STM32F746xx */   /*!< STM32F746VE, STM32F746VG, STM32F746ZE, STM32F746ZG, STM32F746IE, STM32F746IG,\r\n                                   STM32F746BE, STM32F746BG, STM32F746NE, STM32F746NG Devices */\r\n  /* #define STM32F745xx */   /*!< STM32F745VE, STM32F745VG, STM32F745ZG, STM32F745ZE, STM32F745IE, STM32F745IG Devices */\r\n  /* #define STM32F765xx */   /*!< STM32F765BI, STM32F765BG, STM32F765NI, STM32F765NG, STM32F765II, STM32F765IG,\r\n                                   STM32F765ZI, STM32F765ZG, STM32F765VI, STM32F765VG Devices */\r\n  /* #define STM32F767xx */   /*!< STM32F767BG, STM32F767BI, STM32F767IG, STM32F767II, STM32F767NG, STM32F767NI,\r\n                                   STM32F767VG, STM32F767VI, STM32F767ZG, STM32F767ZI Devices */\r\n  /* #define STM32F769xx */   /*!< STM32F769AG, STM32F769AI, STM32F769BG, STM32F769BI, STM32F769IG, STM32F769II,\r\n                                   STM32F769NG, STM32F769NI, STM32F768AI Devices */\r\n  /* #define STM32F777xx */   /*!< STM32F777VI, STM32F777ZI, STM32F777II, STM32F777BI, STM32F777NI Devices */\r\n  /* #define STM32F779xx */   /*!< STM32F779II, STM32F779BI, STM32F779NI, STM32F779AI, STM32F778AI Devices */\r\n  /* #define STM32F722xx */   /*!< STM32F722IE, STM32F722ZE, STM32F722VE, STM32F722RE, STM32F722IC, STM32F722ZC,\r\n                                   STM32F722VC, STM32F722RC Devices */\r\n  /* #define STM32F723xx */   /*!< STM32F723IE, STM32F723ZE, STM32F723VE, STM32F723IC, STM32F723ZC, STM32F723VC Devices */\r\n  /* #define STM32F732xx */   /*!< STM32F732IE, STM32F732ZE, STM32F732VE, STM32F732RE Devices */\r\n  /* #define STM32F733xx */   /*!< STM32F733IE, STM32F733ZE, STM32F733VE Devices */\r\n  /* #define STM32F730xx */   /*!< STM32F730R, STM32F730V, STM32F730Z, STM32F730I Devices */\r\n  /* #define STM32F750xx */   /*!< STM32F750V, STM32F750Z, STM32F750N Devices */\r\n#endif\r\n\r\n/*  Tip: To avoid modifying this file each time you need to switch between these\r\n        devices, you can define the device in your toolchain compiler preprocessor.\r\n  */\r\n\r\n#if !defined  (USE_HAL_DRIVER)\r\n/**\r\n * @brief Comment the line below if you will not use the peripherals drivers.\r\n   In this case, these drivers will not be included and the application code will\r\n   be based on direct access to peripherals registers\r\n   */\r\n  /*#define USE_HAL_DRIVER */\r\n#endif /* USE_HAL_DRIVER */\r\n\r\n/**\r\n  * @brief CMSIS Device version number V1.2.3\r\n  */\r\n#define __STM32F7_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */\r\n#define __STM32F7_CMSIS_VERSION_SUB1   (0x02) /*!< [23:16] sub1 version */\r\n#define __STM32F7_CMSIS_VERSION_SUB2   (0x03) /*!< [15:8]  sub2 version */\r\n#define __STM32F7_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */\r\n#define __STM32F7_CMSIS_VERSION        ((__STM32F7_CMSIS_VERSION_MAIN << 24)\\\r\n                                       |(__STM32F7_CMSIS_VERSION_SUB1 << 16)\\\r\n                                       |(__STM32F7_CMSIS_VERSION_SUB2 << 8 )\\\r\n                                       |(__STM32F7_CMSIS_VERSION))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup Device_Included\r\n  * @{\r\n  */\r\n#if defined(STM32F722xx)\r\n  #include \"stm32f722xx.h\"\r\n#elif defined(STM32F723xx)\r\n  #include \"stm32f723xx.h\"\r\n#elif defined(STM32F732xx)\r\n  #include \"stm32f732xx.h\"\r\n#elif defined(STM32F733xx)\r\n  #include \"stm32f733xx.h\"\r\n#elif defined(STM32F756xx)\r\n  #include \"stm32f756xx.h\"\r\n#elif defined(STM32F746xx)\r\n  #include \"stm32f746xx.h\"\r\n#elif defined(STM32F745xx)\r\n  #include \"stm32f745xx.h\"\r\n#elif defined(STM32F765xx)\r\n  #include \"stm32f765xx.h\"\r\n#elif defined(STM32F767xx)\r\n  #include \"stm32f767xx.h\"\r\n#elif defined(STM32F769xx)\r\n  #include \"stm32f769xx.h\"\r\n#elif defined(STM32F777xx)\r\n  #include \"stm32f777xx.h\"\r\n#elif defined(STM32F779xx)\r\n  #include \"stm32f779xx.h\"\r\n#elif defined(STM32F730xx)\r\n  #include \"stm32f730xx.h\"\r\n#elif defined(STM32F750xx)\r\n  #include \"stm32f750xx.h\"\r\n#else\r\n #error \"Please select first the target STM32F7xx device used in your application (in stm32f7xx.h file)\"\r\n#endif\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup Exported_types\r\n  * @{\r\n  */\r\ntypedef enum\r\n{\r\n  RESET = 0U,\r\n  SET = !RESET\r\n} FlagStatus, ITStatus;\r\n\r\ntypedef enum\r\n{\r\n  DISABLE = 0U,\r\n  ENABLE = !DISABLE\r\n} FunctionalState;\r\n#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\r\n\r\ntypedef enum\r\n{\r\n  ERROR = 0U,\r\n  SUCCESS = !ERROR\r\n} ErrorStatus;\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup Exported_macro\r\n  * @{\r\n  */\r\n#define SET_BIT(REG, BIT)     ((REG) |= (BIT))\r\n\r\n#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))\r\n\r\n#define READ_BIT(REG, BIT)    ((REG) & (BIT))\r\n\r\n#define CLEAR_REG(REG)        ((REG) = (0x0))\r\n\r\n#define WRITE_REG(REG, VAL)   ((REG) = (VAL))\r\n\r\n#define READ_REG(REG)         ((REG))\r\n\r\n#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))\r\n\r\n#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef USE_HAL_DRIVER\r\n #include \"stm32f7xx_hal.h\"\r\n#endif /* USE_HAL_DRIVER */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif /* __cplusplus */\r\n\r\n#endif /* __STM32F7xx_H */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/bsp/opencr/stm32f7xx_hal_conf.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_conf.h\r\n  * @author  MCD Application Team\r\n  * @brief   HAL configuration file. \r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_CONF_H\r\n#define __STM32F7xx_HAL_CONF_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/* ########################## Module Selection ############################## */\r\n/**\r\n  * @brief This is the list of modules to be used in the HAL driver \r\n  */\r\n#define HAL_MODULE_ENABLED  \r\n#define HAL_ADC_MODULE_ENABLED  \r\n#define HAL_CAN_MODULE_ENABLED\r\n/* #define HAL_CAN_LEGACY_MODULE_ENABLED */\r\n/* #define HAL_CEC_MODULE_ENABLED   */\r\n/* #define HAL_CRC_MODULE_ENABLED   */\r\n/* #define HAL_CRYP_MODULE_ENABLED   */\r\n/* #define HAL_DAC_MODULE_ENABLED   */\r\n/* #define HAL_DCMI_MODULE_ENABLED  */\r\n#define HAL_DMA_MODULE_ENABLED\r\n/* #define HAL_DMA2D_MODULE_ENABLED  */\r\n/* #define HAL_ETH_MODULE_ENABLED  */\r\n#define HAL_FLASH_MODULE_ENABLED \r\n/* #define HAL_NAND_MODULE_ENABLED */\r\n/* #define HAL_NOR_MODULE_ENABLED */\r\n/* #define HAL_SRAM_MODULE_ENABLED */\r\n/* #define HAL_SDRAM_MODULE_ENABLED */\r\n/* #define HAL_HASH_MODULE_ENABLED   */\r\n#define HAL_GPIO_MODULE_ENABLED\r\n#define HAL_I2C_MODULE_ENABLED\r\n/* #define HAL_I2S_MODULE_ENABLED    */\r\n#define HAL_IWDG_MODULE_ENABLED\r\n/* #define HAL_LPTIM_MODULE_ENABLED */\r\n/* #define HAL_LTDC_MODULE_ENABLED  */\r\n#define HAL_PWR_MODULE_ENABLED\r\n/* #define HAL_QSPI_MODULE_ENABLED    */\r\n#define HAL_RCC_MODULE_ENABLED \r\n/* #define HAL_RNG_MODULE_ENABLED    */\r\n#define HAL_RTC_MODULE_ENABLED\r\n/* #define HAL_SAI_MODULE_ENABLED    */\r\n/* #define HAL_SD_MODULE_ENABLED   */\r\n/* #define HAL_SPDIFRX_MODULE_ENABLED */\r\n#define HAL_SPI_MODULE_ENABLED\r\n#define HAL_TIM_MODULE_ENABLED\r\n#define HAL_UART_MODULE_ENABLED \r\n#define HAL_USART_MODULE_ENABLED\r\n/* #define HAL_IRDA_MODULE_ENABLED  */\r\n/* #define HAL_SMARTCARD_MODULE_ENABLED  */\r\n/* #define HAL_WWDG_MODULE_ENABLED   */\r\n#define HAL_CORTEX_MODULE_ENABLED\r\n#define HAL_PCD_MODULE_ENABLED\r\n/* #define HAL_HCD_MODULE_ENABLED */\r\n\r\n\r\n/* ########################## HSE/HSI Values adaptation ##################### */\r\n/**\r\n  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.\r\n  *        This value is used by the RCC HAL module to compute the system frequency\r\n  *        (when HSE is used as system clock source, directly or through the PLL).  \r\n  */\r\n#if !defined  (HSE_VALUE) \r\n  #define HSE_VALUE    ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */\r\n#endif /* HSE_VALUE */\r\n\r\n#if !defined  (HSE_STARTUP_TIMEOUT)\r\n  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */\r\n#endif /* HSE_STARTUP_TIMEOUT */\r\n\r\n/**\r\n  * @brief Internal High Speed oscillator (HSI) value.\r\n  *        This value is used by the RCC HAL module to compute the system frequency\r\n  *        (when HSI is used as system clock source, directly or through the PLL). \r\n  */\r\n#if !defined  (HSI_VALUE)\r\n  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/\r\n#endif /* HSI_VALUE */\r\n\r\n/**\r\n  * @brief Internal Low Speed oscillator (LSI) value.\r\n  */\r\n#if !defined  (LSI_VALUE) \r\n #define LSI_VALUE  ((uint32_t)32000U)       /*!< LSI Typical Value in Hz*/    \r\n#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz\r\n                                             The real value may vary depending on the variations\r\n                                             in voltage and temperature.  */\r\n/**\r\n  * @brief External Low Speed oscillator (LSE) value.\r\n  */\r\n#if !defined  (LSE_VALUE)\r\n #define LSE_VALUE  ((uint32_t)32768U)    /*!< Value of the External Low Speed oscillator in Hz */\r\n#endif /* LSE_VALUE */\r\n\r\n#if !defined  (LSE_STARTUP_TIMEOUT)\r\n  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */\r\n#endif /* LSE_STARTUP_TIMEOUT */\r\n\r\n/**\r\n  * @brief External clock source for I2S peripheral\r\n  *        This value is used by the I2S HAL module to compute the I2S clock source \r\n  *        frequency, this source is inserted directly through I2S_CKIN pad. \r\n  */\r\n#if !defined  (EXTERNAL_CLOCK_VALUE)\r\n  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/\r\n#endif /* EXTERNAL_CLOCK_VALUE */\r\n\r\n/* Tip: To avoid modifying this file each time you need to use different HSE,\r\n   ===  you can define the HSE value in your toolchain compiler preprocessor. */\r\n\r\n/* ########################### System Configuration ######################### */\r\n/**\r\n  * @brief This is the HAL system configuration section\r\n  */     \r\n#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */\r\n#define  TICK_INT_PRIORITY            ((uint32_t)0x0FU) /*!< tick interrupt priority */\r\n#define  USE_RTOS                     0U\r\n#define  PREFETCH_ENABLE              1U\r\n#define  ART_ACCLERATOR_ENABLE        1U /* To enable instruction cache and prefetch */\r\n\r\n/* ########################## Assert Selection ############################## */\r\n/**\r\n  * @brief Uncomment the line below to expanse the \"assert_param\" macro in the \r\n  *        HAL drivers code\r\n  */\r\n/* #define USE_FULL_ASSERT    1 */\r\n\r\n/* ################## Ethernet peripheral configuration ##################### */\r\n\r\n/* Section 1 : Ethernet peripheral configuration */\r\n\r\n/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */\r\n#define MAC_ADDR0   2U\r\n#define MAC_ADDR1   0U\r\n#define MAC_ADDR2   0U\r\n#define MAC_ADDR3   0U\r\n#define MAC_ADDR4   0U\r\n#define MAC_ADDR5   0U\r\n\r\n/* Definition of the Ethernet driver buffers size and count */   \r\n#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */\r\n#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */\r\n#define ETH_RXBUFNB                    ((uint32_t)5U)       /* 5 Rx buffers of size ETH_RX_BUF_SIZE  */\r\n#define ETH_TXBUFNB                    ((uint32_t)5U)       /* 5 Tx buffers of size ETH_TX_BUF_SIZE  */\r\n\r\n/* Section 2: PHY configuration section */\r\n/* LAN8742A PHY Address*/\r\n#define LAN8742A_PHY_ADDRESS            0x00U\r\n/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ \r\n#define PHY_RESET_DELAY                 ((uint32_t)0x00000FFFU)\r\n/* PHY Configuration delay */\r\n#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFFU)\r\n\r\n#define PHY_READ_TO                     ((uint32_t)0x0000FFFFU)\r\n#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFFU)\r\n\r\n/* Section 3: Common PHY Registers */\r\n\r\n#define PHY_BCR                         ((uint16_t)0x00U)    /*!< Transceiver Basic Control Register   */\r\n#define PHY_BSR                         ((uint16_t)0x01U)    /*!< Transceiver Basic Status Register    */\r\n \r\n#define PHY_RESET                       ((uint16_t)0x8000U)  /*!< PHY Reset */\r\n#define PHY_LOOPBACK                    ((uint16_t)0x4000U)  /*!< Select loop-back mode */\r\n#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100U)  /*!< Set the full-duplex mode at 100 Mb/s */\r\n#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000U)  /*!< Set the half-duplex mode at 100 Mb/s */\r\n#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100U)  /*!< Set the full-duplex mode at 10 Mb/s  */\r\n#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000U)  /*!< Set the half-duplex mode at 10 Mb/s  */\r\n#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000U)  /*!< Enable auto-negotiation function     */\r\n#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200U)  /*!< Restart auto-negotiation function    */\r\n#define PHY_POWERDOWN                   ((uint16_t)0x0800U)  /*!< Select the power down mode           */\r\n#define PHY_ISOLATE                     ((uint16_t)0x0400U)  /*!< Isolate PHY from MII                 */\r\n\r\n#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020U)  /*!< Auto-Negotiation process completed   */\r\n#define PHY_LINKED_STATUS               ((uint16_t)0x0004U)  /*!< Valid link established               */\r\n#define PHY_JABBER_DETECTION            ((uint16_t)0x0002U)  /*!< Jabber condition detected            */\r\n  \r\n/* Section 4: Extended PHY Registers */\r\n\r\n#define PHY_SR                          ((uint16_t)0x1FU)    /*!< PHY special control/ status register Offset     */\r\n\r\n#define PHY_SPEED_STATUS                ((uint16_t)0x0004U)  /*!< PHY Speed mask                                  */\r\n#define PHY_DUPLEX_STATUS               ((uint16_t)0x0010U)  /*!< PHY Duplex mask                                 */\r\n\r\n\r\n#define PHY_ISFR                        ((uint16_t)0x1DU)    /*!< PHY Interrupt Source Flag register Offset       */\r\n#define PHY_ISFR_INT4                   ((uint16_t)0x0010U)  /*!< PHY Link down inturrupt                         */   \r\n\r\n/* ################## SPI peripheral configuration ########################## */\r\n\r\n/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver\r\n* Activated: CRC code is present inside driver\r\n* Deactivated: CRC code cleaned from driver\r\n*/\r\n\r\n#define USE_SPI_CRC                     1U\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n/**\r\n  * @brief Include module's header file \r\n  */\r\n\r\n#ifdef HAL_RCC_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_rcc.h\"\r\n#endif /* HAL_RCC_MODULE_ENABLED */\r\n\r\n#ifdef HAL_GPIO_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_gpio.h\"\r\n#endif /* HAL_GPIO_MODULE_ENABLED */\r\n\r\n#ifdef HAL_DMA_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_dma.h\"\r\n#endif /* HAL_DMA_MODULE_ENABLED */\r\n   \r\n#ifdef HAL_CORTEX_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_cortex.h\"\r\n#endif /* HAL_CORTEX_MODULE_ENABLED */\r\n\r\n#ifdef HAL_ADC_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_adc.h\"\r\n#endif /* HAL_ADC_MODULE_ENABLED */\r\n\r\n#ifdef HAL_CAN_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_can.h\"\r\n#endif /* HAL_CAN_MODULE_ENABLED */\r\n\r\n#ifdef HAL_CAN_LEGACY_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_can_legacy.h\"\r\n#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */\r\n\r\n#ifdef HAL_CEC_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_cec.h\"\r\n#endif /* HAL_CEC_MODULE_ENABLED */\r\n\r\n#ifdef HAL_CRC_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_crc.h\"\r\n#endif /* HAL_CRC_MODULE_ENABLED */\r\n\r\n#ifdef HAL_CRYP_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_cryp.h\" \r\n#endif /* HAL_CRYP_MODULE_ENABLED */\r\n\r\n#ifdef HAL_DMA2D_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_dma2d.h\"\r\n#endif /* HAL_DMA2D_MODULE_ENABLED */\r\n\r\n#ifdef HAL_DAC_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_dac.h\"\r\n#endif /* HAL_DAC_MODULE_ENABLED */\r\n\r\n#ifdef HAL_DCMI_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_dcmi.h\"\r\n#endif /* HAL_DCMI_MODULE_ENABLED */\r\n\r\n#ifdef HAL_ETH_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_eth.h\"\r\n#endif /* HAL_ETH_MODULE_ENABLED */\r\n\r\n#ifdef HAL_FLASH_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_flash.h\"\r\n#endif /* HAL_FLASH_MODULE_ENABLED */\r\n \r\n#ifdef HAL_SRAM_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_sram.h\"\r\n#endif /* HAL_SRAM_MODULE_ENABLED */\r\n\r\n#ifdef HAL_NOR_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_nor.h\"\r\n#endif /* HAL_NOR_MODULE_ENABLED */\r\n\r\n#ifdef HAL_NAND_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_nand.h\"\r\n#endif /* HAL_NAND_MODULE_ENABLED */\r\n\r\n#ifdef HAL_SDRAM_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_sdram.h\"\r\n#endif /* HAL_SDRAM_MODULE_ENABLED */      \r\n\r\n#ifdef HAL_HASH_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_hash.h\"\r\n#endif /* HAL_HASH_MODULE_ENABLED */\r\n\r\n#ifdef HAL_I2C_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_i2c.h\"\r\n#endif /* HAL_I2C_MODULE_ENABLED */\r\n\r\n#ifdef HAL_I2S_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_i2s.h\"\r\n#endif /* HAL_I2S_MODULE_ENABLED */\r\n\r\n#ifdef HAL_IWDG_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_iwdg.h\"\r\n#endif /* HAL_IWDG_MODULE_ENABLED */\r\n\r\n#ifdef HAL_LPTIM_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_lptim.h\"\r\n#endif /* HAL_LPTIM_MODULE_ENABLED */\r\n\r\n#ifdef HAL_LTDC_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_ltdc.h\"\r\n#endif /* HAL_LTDC_MODULE_ENABLED */\r\n\r\n#ifdef HAL_PWR_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_pwr.h\"\r\n#endif /* HAL_PWR_MODULE_ENABLED */\r\n\r\n#ifdef HAL_QSPI_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_qspi.h\"\r\n#endif /* HAL_QSPI_MODULE_ENABLED */\r\n\r\n#ifdef HAL_RNG_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_rng.h\"\r\n#endif /* HAL_RNG_MODULE_ENABLED */\r\n\r\n#ifdef HAL_RTC_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_rtc.h\"\r\n#endif /* HAL_RTC_MODULE_ENABLED */\r\n\r\n#ifdef HAL_SAI_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_sai.h\"\r\n#endif /* HAL_SAI_MODULE_ENABLED */\r\n\r\n#ifdef HAL_SD_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_sd.h\"\r\n#endif /* HAL_SD_MODULE_ENABLED */\r\n\r\n#ifdef HAL_SPDIFRX_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_spdifrx.h\"\r\n#endif /* HAL_SPDIFRX_MODULE_ENABLED */\r\n\r\n#ifdef HAL_SPI_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_spi.h\"\r\n#endif /* HAL_SPI_MODULE_ENABLED */\r\n\r\n#ifdef HAL_TIM_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_tim.h\"\r\n#endif /* HAL_TIM_MODULE_ENABLED */\r\n\r\n#ifdef HAL_UART_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_uart.h\"\r\n#endif /* HAL_UART_MODULE_ENABLED */\r\n\r\n#ifdef HAL_USART_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_usart.h\"\r\n#endif /* HAL_USART_MODULE_ENABLED */\r\n\r\n#ifdef HAL_IRDA_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_irda.h\"\r\n#endif /* HAL_IRDA_MODULE_ENABLED */\r\n\r\n#ifdef HAL_SMARTCARD_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_smartcard.h\"\r\n#endif /* HAL_SMARTCARD_MODULE_ENABLED */\r\n\r\n#ifdef HAL_WWDG_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_wwdg.h\"\r\n#endif /* HAL_WWDG_MODULE_ENABLED */\r\n\r\n#ifdef HAL_PCD_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_pcd.h\"\r\n#endif /* HAL_PCD_MODULE_ENABLED */\r\n\r\n#ifdef HAL_HCD_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_hcd.h\"\r\n#endif /* HAL_HCD_MODULE_ENABLED */\r\n   \r\n/* Exported macro ------------------------------------------------------------*/\r\n#ifdef  USE_FULL_ASSERT\r\n/**\r\n  * @brief  The assert_param macro is used for function's parameters check.\r\n  * @param  expr: If expr is false, it calls assert_failed function\r\n  *         which reports the name of the source file and the source\r\n  *         line number of the call that failed. \r\n  *         If expr is true, it returns no value.\r\n  * @retval None\r\n  */\r\n  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))\r\n/* Exported functions ------------------------------------------------------- */\r\n  void assert_failed(uint8_t* file, uint32_t line);\r\n#else\r\n  #define assert_param(expr) ((void)0U)\r\n#endif /* USE_FULL_ASSERT */\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_CONF_H */\r\n \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/bsp/opencr/stm32f7xx_it.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    USB_Device/CDC_Standalone/Src/stm32f7xx_it.c\r\n  * @author  MCD Application Team\r\n  * @version V1.0.3\r\n  * @date    18-November-2015\r\n  * @brief   Main Interrupt Service Routines.\r\n  *          This file provides template for all exceptions handler and\r\n  *          peripherals interrupt service routine.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software\r\n  * distributed under the License is distributed on an \"AS IS\" BASIS,\r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"bsp.h\"\r\n#include \"stm32f7xx_it.h\"\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\nextern PCD_HandleTypeDef hpcd;\r\n\r\n\r\n\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/******************************************************************************/\r\n/*            Cortex-M7 Processor Exceptions Handlers                         */\r\n/******************************************************************************/\r\n\r\n/**\r\n  * @brief   This function handles NMI exception.\r\n  * @param  None\r\n  * @retval None\r\n  */\r\nvoid NMI_Handler(void)\r\n{\r\n}\r\n\r\n/**\r\n  * @brief  This function handles Hard Fault exception.\r\n  * @param  None\r\n  * @retval None\r\n  */\r\nvoid HardFault_Handler(void)\r\n{\r\n  /* Go to infinite loop when Hard Fault exception occurs */\r\n  while (1)\r\n  {\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  This function handles Memory Manage exception.\r\n  * @param  None\r\n  * @retval None\r\n  */\r\nvoid MemManage_Handler(void)\r\n{\r\n  /* Go to infinite loop when Memory Manage exception occurs */\r\n  while (1)\r\n  {\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  This function handles Bus Fault exception.\r\n  * @param  None\r\n  * @retval None\r\n  */\r\nvoid BusFault_Handler(void)\r\n{\r\n  /* Go to infinite loop when Bus Fault exception occurs */\r\n  while (1)\r\n  {\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  This function handles Usage Fault exception.\r\n  * @param  None\r\n  * @retval None\r\n  */\r\nvoid UsageFault_Handler(void)\r\n{\r\n  /* Go to infinite loop when Usage Fault exception occurs */\r\n  while (1)\r\n  {\r\n  }\r\n}\r\n\r\n#if 0\r\n/**\r\n  * @brief  This function handles SVCall exception.\r\n  * @param  None\r\n  * @retval None\r\n  */\r\nvoid SVC_Handler(void)\r\n{\r\n}\r\n#endif\r\n\r\n/**\r\n  * @brief  This function handles Debug Monitor exception.\r\n  * @param  None\r\n  * @retval None\r\n  */\r\nvoid DebugMon_Handler(void)\r\n{\r\n}\r\n\r\n#if 0\r\n/**\r\n  * @brief  This function handles PendSVC exception.\r\n  * @param  None\r\n  * @retval None\r\n  */\r\nvoid PendSV_Handler(void)\r\n{\r\n}\r\n#endif\r\n\r\n__weak void osSystickHandler(void)\r\n{\r\n}\r\n\r\n/**\r\n  * @brief  This function handles SysTick Handler.\r\n  * @param  None\r\n  * @retval None\r\n  */\r\nvoid SysTick_Handler(void)\r\n{\r\n  osSystickHandler();\r\n  HAL_IncTick();\r\n}\r\n\r\n/******************************************************************************/\r\n/*                 STM32F7xx Peripherals Interrupt Handlers                   */\r\n/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */\r\n/*  available peripheral interrupt handler's name please refer to the startup */\r\n/*  file (startup_stm32f7xx.s).                                               */\r\n/******************************************************************************/\r\n\r\n/**\r\n  * @brief  This function handles USB-On-The-Go FS/HS global interrupt request.\r\n  * @param  None\r\n  * @retval None\r\n  */\r\n#ifdef USE_USB_FS\r\nvoid OTG_FS_IRQHandler(void)\r\n#else\r\nvoid OTG_HS_IRQHandler(void)\r\n#endif\r\n{\r\n  HAL_PCD_IRQHandler(&hpcd);\r\n}\r\n\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/bsp/opencr/stm32f7xx_it.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    UART/UART_TwoBoards_ComIT/Inc/stm32f7xx_it.h \r\n  * @author  MCD Application Team\r\n  * @version V1.0.2\r\n  * @date    18-November-2015 \r\n  * @brief   This file contains the headers of the interrupt handlers.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_IT_H\r\n#define __STM32F7xx_IT_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions ------------------------------------------------------- */\r\n\r\nvoid NMI_Handler(void);\r\nvoid HardFault_Handler(void);\r\nvoid MemManage_Handler(void);\r\nvoid BusFault_Handler(void);\r\nvoid UsageFault_Handler(void);\r\nvoid SVC_Handler(void);\r\nvoid DebugMon_Handler(void);\r\nvoid PendSV_Handler(void);\r\nvoid SysTick_Handler(void);\r\n\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_IT_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/bsp/opencr/syscalls.c",
    "content": "/* Support files for GNU libc.  Files in the system namespace go here.\r\n   Files in the C namespace (ie those that do not start with an\r\n   underscore) go in .c.  */\r\n\r\n#include <_ansi.h>\r\n#include <sys/types.h>\r\n#include <sys/stat.h>\r\n#include <sys/fcntl.h>\r\n#include <stdio.h>\r\n#include <string.h>\r\n#include <time.h>\r\n#include <sys/time.h>\r\n#include <sys/times.h>\r\n#include <errno.h>\r\n#include <reent.h>\r\n#include <unistd.h>\r\n#include <sys/wait.h>\r\n\r\n#undef errno\r\nextern int errno;\r\n\r\n#define FreeRTOS\r\n#define MAX_STACK_SIZE 0x2000\r\n\r\nextern int __io_putchar(int ch) __attribute__((weak));\r\nextern int __io_getchar(void) __attribute__((weak));\r\n\r\n#ifndef FreeRTOS\r\n  register char * stack_ptr asm(\"sp\");\r\n#endif\r\n\r\n\r\n\r\n\r\ncaddr_t _sbrk(int incr)\r\n{\r\n\textern char end asm(\"end\");\r\n\tstatic char *heap_end;\r\n\tchar *prev_heap_end,*min_stack_ptr;\r\n\r\n\tif (heap_end == 0)\r\n\t\theap_end = &end;\r\n\r\n\tprev_heap_end = heap_end;\r\n\r\n#ifdef FreeRTOS\r\n\t/* Use the NVIC offset register to locate the main stack pointer. */\r\n\tmin_stack_ptr = (char*)(*(unsigned int *)*(unsigned int *)0xE000ED08);\r\n\t/* Locate the STACK bottom address */\r\n\tmin_stack_ptr -= MAX_STACK_SIZE;\r\n\r\n\tif (heap_end + incr > min_stack_ptr)\r\n#else\r\n\tif (heap_end + incr > stack_ptr)\r\n#endif\r\n\t{\r\n//\t\twrite(1, \"Heap and stack collision\\n\", 25);\r\n//\t\tabort();\r\n\t\terrno = ENOMEM;\r\n\t\treturn (caddr_t) -1;\r\n\t}\r\n\r\n\theap_end += incr;\r\n\r\n\treturn (caddr_t) prev_heap_end;\r\n}\r\n\r\n/*\r\n * _gettimeofday primitive (Stub function)\r\n * */\r\nint _gettimeofday (struct timeval * tp, struct timezone * tzp)\r\n{\r\n  (void)(tp);\r\n\r\n  /* Return fixed data for the timezone.  */\r\n  if (tzp)\r\n    {\r\n      tzp->tz_minuteswest = 0;\r\n      tzp->tz_dsttime = 0;\r\n    }\r\n\r\n  return 0;\r\n}\r\nvoid initialise_monitor_handles()\r\n{\r\n}\r\n\r\nint _getpid(void)\r\n{\r\n\treturn 1;\r\n}\r\n\r\nint _kill(int pid, int sig)\r\n{\r\n\t(void)(pid);\r\n\t(void)(sig);\r\n\r\n\terrno = EINVAL;\r\n\treturn -1;\r\n}\r\n\r\nvoid _exit (int status)\r\n{\r\n\t_kill(status, -1);\r\n\twhile (1) {}\r\n}\r\n\r\nint _write(int file, char *ptr, int len)\r\n{\r\n\t(void)(file);\r\n\r\n\tint DataIdx;\r\n\r\n\t\tfor (DataIdx = 0; DataIdx < len; DataIdx++)\r\n\t\t{\r\n\t\t   __io_putchar( *ptr++ );\r\n\t\t}\r\n\treturn len;\r\n}\r\n\r\nint _close(int file)\r\n{\r\n\t(void)(file);\r\n\t\r\n\treturn -1;\r\n}\r\n\r\nint _fstat(int file, struct stat *st)\r\n{\r\n\t(void)(file);\r\n\t(void)(st);\r\n\r\n\tst->st_mode = S_IFCHR;\r\n\treturn 0;\r\n}\r\n\r\nint _isatty(int file)\r\n{\r\n\t(void)(file);\r\n\r\n\treturn 1;\r\n}\r\n\r\nint _lseek(int file, int ptr, int dir)\r\n{\r\n\t(void)(file);\r\n\t(void)(ptr);\r\n\t(void)(dir);\r\n\r\n\treturn 0;\r\n}\r\n\r\nint _read(int file, char *ptr, int len)\r\n{\r\n\t(void)(file);\r\n\r\n\tint DataIdx;\r\n\r\n\tfor (DataIdx = 0; DataIdx < len; DataIdx++)\r\n\t{\r\n\t  *ptr++ = __io_getchar();\r\n\t}\r\n\r\n   return len;\r\n}\r\n\r\nint _open(char *path, int flags, ...)\r\n{\r\n\t(void)(path);\r\n\t(void)(flags);\r\n\r\n\t/* Pretend like we always fail */\r\n\treturn -1;\r\n}\r\n\r\nint _wait(int *status)\r\n{\r\n\t(void)(status);\r\n\r\n\terrno = ECHILD;\r\n\treturn -1;\r\n}\r\n\r\nint _unlink(char *name)\r\n{\r\n\t(void)(name);\r\n\r\n\terrno = ENOENT;\r\n\treturn -1;\r\n}\r\n\r\nint _times(struct tms *buf)\r\n{\r\n\t(void)(buf);\r\n\r\n\treturn -1;\r\n}\r\n\r\nint _stat(char *file, struct stat *st)\r\n{\r\n\t(void)(file);\r\n\t(void)(st);\r\n\r\n\tst->st_mode = S_IFCHR;\r\n\treturn 0;\r\n}\r\n\r\nint _link(char *old, char *new)\r\n{\r\n\t(void)(old);\r\n\t(void)(new);\r\n\r\n\terrno = EMLINK;\r\n\treturn -1;\r\n}\r\n\r\nint _fork(void)\r\n{\r\n\terrno = EAGAIN;\r\n\treturn -1;\r\n}\r\n\r\nint _execve(char *name, char **argv, char **env)\r\n{\r\n\t(void)(name);\r\n\t(void)(argv);\r\n\t(void)(env);\r\n\r\n\terrno = ENOMEM;\r\n\treturn -1;\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/bsp/opencr/system_clock.c",
    "content": "#include \"stm32f7xx_hal.h\"\r\n#include \"stm32f7xx.h\"\r\n\r\n\r\n\r\n\r\n\r\n\r\n/**\r\n  * @brief  System Clock Configuration\r\n  *         The system Clock is configured as follow : \r\n  *            System Clock source            = PLL (HSE)\r\n  *            SYSCLK(Hz)                     = 216000000\r\n  *            HCLK(Hz)                       = 216000000\r\n  *            AHB Prescaler                  = 1\r\n  *            APB1 Prescaler                 = 4\r\n  *            APB2 Prescaler                 = 2\r\n  *            HSE Frequency(Hz)              = 25000000\r\n  *            PLL_M                          = 25\r\n  *            PLL_N                          = 432\r\n  *            PLL_P                          = 2\r\n  *            PLL_Q                          = 9\r\n  *            VDD(V)                         = 3.3\r\n  *            Main regulator output voltage  = Scale1 mode\r\n  *            Flash Latency(WS)              = 7\r\n  * @param  None\r\n  * @retval None\r\n  */\r\nvoid SystemClock_Config(void)\r\n{\r\n  RCC_ClkInitTypeDef RCC_ClkInitStruct;\r\n  RCC_OscInitTypeDef RCC_OscInitStruct;\r\n  HAL_StatusTypeDef ret = HAL_OK;\r\n\r\n  /* Enable HSE Oscillator and activate PLL with HSE as source */\r\n  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;\r\n  RCC_OscInitStruct.HSEState = RCC_HSE_ON;\r\n  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;\r\n  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;\r\n  RCC_OscInitStruct.PLL.PLLM = 25;\r\n  RCC_OscInitStruct.PLL.PLLN = 432;\r\n  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;\r\n  RCC_OscInitStruct.PLL.PLLQ = 9;\r\n  \r\n  ret = HAL_RCC_OscConfig(&RCC_OscInitStruct);\r\n  if(ret != HAL_OK)\r\n  {\r\n    while(1) { ; }\r\n  }\r\n  \r\n  /* Activate the OverDrive to reach the 216 MHz Frequency */  \r\n  ret = HAL_PWREx_EnableOverDrive();\r\n  if(ret != HAL_OK)\r\n  {\r\n    while(1) { ; }\r\n  }\r\n  \r\n  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */\r\n  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);\r\n  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;\r\n  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;\r\n  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;  \r\n  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; \r\n  \r\n  ret = HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7);\r\n  if(ret != HAL_OK)\r\n  {\r\n    while(1) { ; }\r\n  }  \r\n\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/bsp/opencr/system_clock.h",
    "content": "#ifndef __SYSTEM_CLOCK_H\r\n#define __SYSTEM_CLOCK_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif \r\n  \r\n\r\nextern void SystemClock_Config(void);\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/bsp/opencr/system_stm32f7xx.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    system_stm32f7xx.c\r\n  * @author  MCD Application Team\r\n  * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.\r\n  *\r\n  *   This file provides two functions and one global variable to be called from \r\n  *   user application:\r\n  *      - SystemInit(): This function is called at startup just after reset and \r\n  *                      before branch to main program. This call is made inside\r\n  *                      the \"startup_stm32f7xx.s\" file.\r\n  *\r\n  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used\r\n  *                                  by the user application to setup the SysTick \r\n  *                                  timer or configure other parameters.\r\n  *                                     \r\n  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must\r\n  *                                 be called whenever the core clock is changed\r\n  *                                 during program execution.\r\n  *\r\n  *\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/** @addtogroup CMSIS\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup stm32f7xx_system\r\n  * @{\r\n  */  \r\n  \r\n/** @addtogroup STM32F7xx_System_Private_Includes\r\n  * @{\r\n  */\r\n\r\n#include \"stm32f7xx.h\"\r\n\r\n#if !defined  (HSE_VALUE) \r\n  #define HSE_VALUE    ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */\r\n#endif /* HSE_VALUE */\r\n\r\n#if !defined  (HSI_VALUE)\r\n  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/\r\n#endif /* HSI_VALUE */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup STM32F7xx_System_Private_TypesDefinitions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup STM32F7xx_System_Private_Defines\r\n  * @{\r\n  */\r\n\r\n/************************* Miscellaneous Configuration ************************/\r\n\r\n/*!< Uncomment the following line if you need to relocate your vector Table in\r\n     Internal SRAM. */\r\n/* #define VECT_TAB_SRAM */\r\n#define VECT_TAB_OFFSET  0x40000 /*!< Vector Table base offset field. \r\n                                   This value must be a multiple of 0x200. */\r\n/******************************************************************************/\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup STM32F7xx_System_Private_Macros\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup STM32F7xx_System_Private_Variables\r\n  * @{\r\n  */\r\n\r\n  /* This variable is updated in three ways:\r\n      1) by calling CMSIS function SystemCoreClockUpdate()\r\n      2) by calling HAL API function HAL_RCC_GetHCLKFreq()\r\n      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency \r\n         Note: If you use this function to configure the system clock; then there\r\n               is no need to call the 2 first functions listed above, since SystemCoreClock\r\n               variable is updated automatically.\r\n  */\r\n  uint32_t SystemCoreClock = 16000000;\r\n  const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};\r\n  const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup STM32F7xx_System_Private_Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Setup the microcontroller system\r\n  *         Initialize the Embedded Flash Interface, the PLL and update the \r\n  *         SystemFrequency variable.\r\n  * @param  None\r\n  * @retval None\r\n  */\r\nvoid SystemInit(void)\r\n{\r\n  /* FPU settings ------------------------------------------------------------*/\r\n  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r\n    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */\r\n  #endif\r\n  /* Reset the RCC clock configuration to the default reset state ------------*/\r\n  /* Set HSION bit */\r\n  RCC->CR |= (uint32_t)0x00000001;\r\n\r\n  /* Reset CFGR register */\r\n  RCC->CFGR = 0x00000000;\r\n\r\n  /* Reset HSEON, CSSON and PLLON bits */\r\n  RCC->CR &= (uint32_t)0xFEF6FFFF;\r\n\r\n  /* Reset PLLCFGR register */\r\n  RCC->PLLCFGR = 0x24003010;\r\n\r\n  /* Reset HSEBYP bit */\r\n  RCC->CR &= (uint32_t)0xFFFBFFFF;\r\n\r\n  /* Disable all interrupts */\r\n  RCC->CIR = 0x00000000;\r\n\r\n  /* Configure the Vector Table location add offset address ------------------*/\r\n#ifdef VECT_TAB_SRAM\r\n  SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */\r\n#else\r\n  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */\r\n#endif\r\n}\r\n\r\n/**\r\n   * @brief  Update SystemCoreClock variable according to Clock Register Values.\r\n  *         The SystemCoreClock variable contains the core clock (HCLK), it can\r\n  *         be used by the user application to setup the SysTick timer or configure\r\n  *         other parameters.\r\n  *           \r\n  * @note   Each time the core clock (HCLK) changes, this function must be called\r\n  *         to update SystemCoreClock variable value. Otherwise, any configuration\r\n  *         based on this variable will be incorrect.         \r\n  *     \r\n  * @note   - The system frequency computed by this function is not the real \r\n  *           frequency in the chip. It is calculated based on the predefined \r\n  *           constant and the selected clock source:\r\n  *             \r\n  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)\r\n  *                                              \r\n  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)\r\n  *                          \r\n  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) \r\n  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.\r\n  *         \r\n  *         (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value\r\n  *             16 MHz) but the real value may vary depending on the variations\r\n  *             in voltage and temperature.   \r\n  *    \r\n  *         (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value\r\n  *              25 MHz), user has to ensure that HSE_VALUE is same as the real\r\n  *              frequency of the crystal used. Otherwise, this function may\r\n  *              have wrong result.\r\n  *                \r\n  *         - The result of this function could be not correct when using fractional\r\n  *           value for HSE crystal.\r\n  *     \r\n  * @param  None\r\n  * @retval None\r\n  */\r\nvoid SystemCoreClockUpdate(void)\r\n{\r\n  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;\r\n  \r\n  /* Get SYSCLK source -------------------------------------------------------*/\r\n  tmp = RCC->CFGR & RCC_CFGR_SWS;\r\n\r\n  switch (tmp)\r\n  {\r\n    case 0x00:  /* HSI used as system clock source */\r\n      SystemCoreClock = HSI_VALUE;\r\n      break;\r\n    case 0x04:  /* HSE used as system clock source */\r\n      SystemCoreClock = HSE_VALUE;\r\n      break;\r\n    case 0x08:  /* PLL used as system clock source */\r\n\r\n      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N\r\n         SYSCLK = PLL_VCO / PLL_P\r\n         */    \r\n      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;\r\n      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;\r\n      \r\n      if (pllsource != 0)\r\n      {\r\n        /* HSE used as PLL clock source */\r\n        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);\r\n      }\r\n      else\r\n      {\r\n        /* HSI used as PLL clock source */\r\n        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      \r\n      }\r\n\r\n      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;\r\n      SystemCoreClock = pllvco/pllp;\r\n      break;\r\n    default:\r\n      SystemCoreClock = HSI_VALUE;\r\n      break;\r\n  }\r\n  /* Compute HCLK frequency --------------------------------------------------*/\r\n  /* Get HCLK prescaler */\r\n  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];\r\n  /* HCLK frequency */\r\n  SystemCoreClock >>= tmp;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */    \r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/bsp/opencr/system_stm32f7xx.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    system_stm32f7xx.h\r\n  * @author  MCD Application Team\r\n  * @brief   CMSIS Cortex-M7 Device System Source File for STM32F7xx devices.       \r\n  ******************************************************************************  \r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************  \r\n  */\r\n\r\n/** @addtogroup CMSIS\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup stm32f7xx_system\r\n  * @{\r\n  */  \r\n  \r\n/**\r\n  * @brief Define to prevent recursive inclusion\r\n  */\r\n#ifndef __SYSTEM_STM32F7XX_H\r\n#define __SYSTEM_STM32F7XX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif \r\n\r\n/** @addtogroup STM32F7xx_System_Includes\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @addtogroup STM32F7xx_System_Exported_Variables\r\n  * @{\r\n  */\r\n  /* The SystemCoreClock variable is updated in three ways:\r\n      1) by calling CMSIS function SystemCoreClockUpdate()\r\n      2) by calling HAL API function HAL_RCC_GetSysClockFreq()\r\n      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency \r\n         Note: If you use this function to configure the system clock; then there\r\n               is no need to call the 2 first functions listed above, since SystemCoreClock\r\n               variable is updated automatically.\r\n    */\r\nextern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */\r\n\r\nextern const uint8_t  AHBPrescTable[16];    /*!< AHB prescalers table values */\r\nextern const uint8_t  APBPrescTable[8];     /*!< APB prescalers table values */\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup STM32F7xx_System_Exported_Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup STM32F7xx_System_Exported_Macros\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup STM32F7xx_System_Exported_Functions\r\n  * @{\r\n  */\r\n  \r\nextern void SystemInit(void);\r\nextern void SystemCoreClockUpdate(void);\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /*__SYSTEM_STM32F7XX_H */\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */  \r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/chip.h",
    "content": "#ifndef _CHIP_OPENCR_F7xx_\n#define _CHIP_OPENCR_F7xx_\n\n#include <stdbool.h>\n#include \"bsp.h\"\n#include \"hw.h\"\n\n\n\n\n\n\n\n#define USE_SPI1\n#define USE_SPI2\n#define USE_SPI4\n\n#define BOARD_NR_I2C  2\n#define HAL_I2C1      I2C1\n#define HAL_I2C2      I2C2\n#define HAL_I2C3      I2C3\n\n\n\n\n#define PIN_SPI_SS              10\n#define PIN_SPI_MOSI            11\n#define PIN_SPI_MISO            12\n#define PIN_SPI_SCK             13\n\nstatic const uint8_t SS   = PIN_SPI_SS;\nstatic const uint8_t MOSI = PIN_SPI_MOSI;\nstatic const uint8_t MISO = PIN_SPI_MISO;\nstatic const uint8_t SCK  = PIN_SPI_SCK;\n\n\n\n\n\n#define BOARD_NR_ADC_PINS       5\n#define BOARD_NR_PWM_PINS       12\n\n#define LED_BUILTIN             13\n\n#define BDPIN_LED_USER_1        22\n#define BDPIN_LED_USER_2        23\n#define BDPIN_LED_USER_3        24\n#define BDPIN_LED_USER_4        25\n#define BDPIN_DIP_SW_1          26\n#define BDPIN_DIP_SW_2          27\n#define BDPIN_SPI_CS_IMU        28\n#define BDPIN_BAT_PWR_ADC       29\n#define BDPIN_BUZZER            31\n#define BDPIN_DXL_PWR_EN        32\n#define BDPIN_PUSH_SW_1         34\n#define BDPIN_PUSH_SW_2         35\n#define BDPIN_LED_STATUS        36\n#define BDPIN_SPI_CLK_IMU       37\n#define BDPIN_SPI_SDO_IMU       38\n#define BDPIN_SPI_SDI_IMU       39\n\n#define BDPIN_GPIO_1            50\n#define BDPIN_GPIO_2            51\n#define BDPIN_GPIO_3            52\n#define BDPIN_GPIO_4            53\n#define BDPIN_GPIO_5            54\n#define BDPIN_GPIO_6            55\n#define BDPIN_GPIO_7            56\n#define BDPIN_GPIO_8            57\n#define BDPIN_GPIO_9            58\n#define BDPIN_GPIO_10           59\n#define BDPIN_GPIO_11           60\n#define BDPIN_GPIO_12           61\n#define BDPIN_GPIO_13           62\n#define BDPIN_GPIO_14           63\n#define BDPIN_GPIO_15           64\n#define BDPIN_GPIO_16           65\n#define BDPIN_GPIO_17           66\n#define BDPIN_GPIO_18           67\n\n#define BDPIN_UART1_RX          80\n#define BDPIN_UART1_TX          81\n#define BDPIN_UART2_RX          82\n#define BDPIN_UART2_TX          83\n\n\n\n\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/def.h",
    "content": "/*\n *  def.h\n *\n *  Created on: 2016. 5. 14.\n *      Author: Baram, PBHP\n */\n\n#ifndef DEF_H\n#define DEF_H\n\n#include <stdint.h>\n#include <stdbool.h>\n\n#ifndef BOOL\n#define BOOL uint8_t\n#endif\n\n#ifndef TRUE\n#define TRUE  1\n#endif\n\n#ifndef FALSE\n#define FALSE 0\n#endif\n\n/*\n#ifndef bool\n#define bool uint8_t\n#endif\n\n#ifndef true\n#define true  1\n#endif\n\n#ifndef false\n#define false 0\n#endif\n\n*/\n\ntypedef void (*voidFuncPtr)(void);\n\n\n#include \"def_err.h\"\n\n\n\n\n#define _DEF_CAN1               0\n#define _DEF_CAN2               1\n#define _DEF_CAN_BAUD_125K      0\n#define _DEF_CAN_BAUD_250K      1\n#define _DEF_CAN_BAUD_500K      2\n#define _DEF_CAN_BAUD_1000K     3\n#define _DEF_CAN_STD            0\n#define _DEF_CAN_EXT            1\n\n\n\n\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/def_err.h",
    "content": "/*\n *  def_err.h\n *\n *  Created on: 2016. 5. 14.\n *      Author: Baram, PBHP\n */\n\n#ifndef DEF_ERR_H\n#define DEF_ERR_H\n\n#include <stdint.h>\n\n\n\ntypedef uint16_t err_code_t;\n\n\n\n\n#define ERR_NONE                            0x0000\n#define ERR_INVALID_CMD                     0x0001\n#define ERR_FLASH_ERROR                     0x0010\n#define ERR_FLASH_BUSY                      0x0011\n#define ERR_FLASH_ERR_TIMEOUT               0x0012\n#define ERR_FLASH_NOT_EMPTY                 0x0013\n#define ERR_FLASH_WRITE                     0x0014\n#define ERR_FLASH_READ                      0x0015\n#define ERR_FLASH_ERASE                     0x0016\n#define ERR_FLASH_PACKET_SIZE               0x0017\n#define ERR_FLASH_SIZE                      0x0018\n#define ERR_FLASH_CRC                       0x0019\n\n#define ERR_MEMORY                          0x0100\n#define ERR_FULL                            0x0101\n#define ERR_EMPTY                           0x0102\n#define ERR_NULL                            0x0103\n#define ERR_INVAILD_INDEX                   0x0104\n\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/delay.c",
    "content": "/*\n *  delay.h\n *\n *  Created on: 2016. 5. 14.\n *      Author: Baram, PBHP\n */\n\n#include \"delay.h\"\n\n\n\nextern void delayMicroseconds(uint32_t usec);\n\n\n\nvoid delay_ns(uint32_t ns)\n{\n  for (volatile uint32_t i = 0; i < ns/10; i++) { }\n}\n\nvoid delay_us(uint32_t us)\n{\n  delayMicroseconds(us);\n}\n\nvoid delay_ms(uint32_t ms)\n{\n  volatile uint32_t t_start = millis();\n\n\n  while (1)\n  {\n    volatile uint32_t t[2];\n    // poll time twice in case we happen to poll during timer wrap glitch\n    t[0] = millis();\n    t[1] = millis();\n    t[0] = t[1] < t[0] ? t[1] : t[0];\n    if (t[0] > t_start + ms)\n      break;\n  }\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/delay.h",
    "content": "/*\n *  delay.h\n *\n *  Created on: 2016. 5. 14.\n *      Author: Baram, PBHP\n */\n\n#ifndef DELAY_H\n#define DELAY_H\n\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n\n#include \"def.h\"\n#include \"bsp.h\"\n\n\n\n#define millis(a1) \tHAL_GetTick(a1)\n#define delay(a2) \tHAL_Delay(a2)\n\n\nvoid delay_ns(uint32_t ns);\nvoid delay_us(uint32_t us);\nvoid delay_ms(uint32_t ms);\n\n//uint32_t millis();\n\n\n#ifdef __cplusplus\n}\n#endif\n\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/dma_stream_handlers.c",
    "content": "/*\n *  dma_stream_handlers.c\n *\n *  Created on: 2018. 9. 22.\n *      Author: Kurt\n */\n#include \"dma_stream_handlers.h\"\n#include \"vcp.h\"\n\n//=============================================================================\n\n//=============================================================================\n\nDMA_HandleTypeDef *DMA1_hdmas[8] = {NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL};\n\nDMALoseStreamHandlerCallbackFunction_t DMA1_loseHandlerCBs[8] = {NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL};  \n\nDMA_HandleTypeDef *DMA2_hdmas[8] = {NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL};\n\nDMALoseStreamHandlerCallbackFunction_t DMA2_loseHandlerCBs[8] = {NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL};  \n\n//=============================================================================\n// Set the handle for one of the DMA1 streams \n// In some cases we allow the handle to overwrite existing set ones\n//=============================================================================\nbool SetDMA1StreamHandlerHandle(uint8_t iStream, DMA_HandleTypeDef *hdma, \n\tbool fOverwrite,DMALoseStreamHandlerCallbackFunction_t loseCB)\n{\n\t//vcp_printf(\"SetDMA1Stream: %d %x %x %x\\n\", iStream, (uint32_t)hdma, fOverwrite, (uint32_t)loseCB);\n\n\tif (iStream >= (sizeof(DMA1_hdmas)/sizeof(DMA1_hdmas[0]))) return false; // out of range\n\tif (!fOverwrite && DMA1_hdmas[iStream] && (DMA1_hdmas[iStream] != hdma)) return false; // Don't overwrite existing one...\n\n\t// See if someone is losing their stream and there is a callback\n\tif (DMA1_hdmas[iStream] && (DMA1_hdmas[iStream] != hdma) && DMA1_loseHandlerCBs[iStream])\n\t{\n\t\t//vcp_printf(\" DMA1 lose handler CB %d %x\\n\", iStream, (uint32_t)DMA1_hdmas[iStream]);\n\t\t(*DMA1_loseHandlerCBs[iStream])(iStream);\n\t}\n\tDMA1_hdmas[iStream] = hdma;\n\tDMA1_loseHandlerCBs[iStream] = loseCB;\n\t//vcp_printf(\"  DMA1 set\\n\");\n\treturn true;\n}\n\n//=============================================================================\n// Set the handle for one of the DMA1 streams \n// In some cases we allow the handle to overwrite existing set ones\n//=============================================================================\nbool SetDMA2StreamHandlerHandle(uint8_t iStream, DMA_HandleTypeDef *hdma, \n\tbool fOverwrite,DMALoseStreamHandlerCallbackFunction_t loseCB)\n{\n\t//vcp_printf(\"SetDMA2Stream: %d %x %x %x\\n\", iStream, (uint32_t)hdma, fOverwrite, (uint32_t)loseCB);\n\n\tif (iStream >= (sizeof(DMA2_hdmas)/sizeof(DMA2_hdmas[0]))) return false; // out of range\n\tif (!fOverwrite && DMA2_hdmas[iStream] && (DMA2_hdmas[iStream] != hdma)) return false; // Don't overwrite existing one...\n\n\t// See if someone is losing their stream and there is a callback\n\tif (DMA2_hdmas[iStream] && (DMA2_hdmas[iStream] != hdma) && DMA2_loseHandlerCBs[iStream])\n\t{\n\t\t//vcp_printf(\" DMA2 lose handler CB %d %x\\n\", iStream, (uint32_t)DMA2_hdmas[iStream]);\n\t\t(*DMA2_loseHandlerCBs[iStream])(iStream);\n\t}\n\tDMA2_hdmas[iStream] = hdma;\n\tDMA2_loseHandlerCBs[iStream] = loseCB;\n\t//vcp_printf(\"  DMA2 set\\n\");\n\treturn true;\n}\n\n\n//=============================================================================\n// Simply call off to the HAL_DMA handler with appropriate handle\n//=============================================================================\nvoid DMA1_Stream0_IRQHandler(void)\n{\n\tif (DMA1_hdmas[0]) \n\t{\n  \t\tHAL_DMA_IRQHandler(DMA1_hdmas[0]);\n\t}\n}\n\nvoid DMA1_Stream1_IRQHandler(void)\n{\n\tif (DMA1_hdmas[1]) \n\t{\n  \t\tHAL_DMA_IRQHandler(DMA1_hdmas[1]);\n\t}\n}\n\nvoid DMA1_Stream2_IRQHandler(void)\n{\n\tif (DMA1_hdmas[2]) \n\t{\n  \t\tHAL_DMA_IRQHandler(DMA1_hdmas[2]);\n\t}\n}\n\nvoid DMA1_Stream3_IRQHandler(void)\n{\n\tif (DMA1_hdmas[3]) \n\t{\n  \t\tHAL_DMA_IRQHandler(DMA1_hdmas[3]);\n\t}\n}\n\nvoid DMA1_Stream4_IRQHandler(void)\n{\n\tif (DMA1_hdmas[4]) \n\t{\n  \t\tHAL_DMA_IRQHandler(DMA1_hdmas[4]);\n\t}\n}\nvoid DMA1_Stream5_IRQHandler(void)\n{\n\tif (DMA1_hdmas[5]) \n\t{\n  \t\tHAL_DMA_IRQHandler(DMA1_hdmas[5]);\n\t}\n}\n\nvoid DMA1_Stream6_IRQHandler(void)\n{\n\tif (DMA1_hdmas[6]) \n\t{\n  \t\tHAL_DMA_IRQHandler(DMA1_hdmas[6]);\n\t}\n}\n\nvoid DMA1_Stream7_IRQHandler(void)\n{\n\tif (DMA1_hdmas[7]) \n\t{\n  \t\tHAL_DMA_IRQHandler(DMA1_hdmas[7]);\n\t}\n}\n\n\n//=============================================================================\n// Simply call off to the HAL_DMA handler with appropriate handle\n//=============================================================================\nvoid DMA2_Stream0_IRQHandler(void)\n{\n\tif (DMA2_hdmas[0]) \n\t{\n  \t\tHAL_DMA_IRQHandler(DMA2_hdmas[0]);\n\t}\n}\n\nvoid DMA2_Stream1_IRQHandler(void)\n{\n\tif (DMA2_hdmas[1]) \n\t{\n  \t\tHAL_DMA_IRQHandler(DMA2_hdmas[1]);\n\t}\n}\n\nvoid DMA2_Stream2_IRQHandler(void)\n{\n\tif (DMA2_hdmas[2]) \n\t{\n  \t\tHAL_DMA_IRQHandler(DMA2_hdmas[2]);\n\t}\n}\n\nvoid DMA2_Stream3_IRQHandler(void)\n{\n\tif (DMA2_hdmas[3]) \n\t{\n  \t\tHAL_DMA_IRQHandler(DMA2_hdmas[3]);\n\t}\n}\n\nvoid DMA2_Stream4_IRQHandler(void)\n{\n\tif (DMA2_hdmas[4]) \n\t{\n  \t\tHAL_DMA_IRQHandler(DMA2_hdmas[4]);\n\t}\n}\n\nvoid DMA2_Stream5_IRQHandler(void)\n{\n\tif (DMA2_hdmas[5]) \n\t{\n  \t\tHAL_DMA_IRQHandler(DMA2_hdmas[5]);\n\t}\n}\n\nvoid DMA2_Stream6_IRQHandler(void)\n{\n\tif (DMA2_hdmas[6]) \n\t{\n  \t\tHAL_DMA_IRQHandler(DMA2_hdmas[6]);\n\t}\n}\n\nvoid DMA2_Stream7_IRQHandler(void)\n{\n\tif (DMA2_hdmas[7]) \n\t{\n  \t\tHAL_DMA_IRQHandler(DMA2_hdmas[7]);\n\t}\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/dma_stream_handlers.h",
    "content": "/*\n  Copyright (c) 2011 Arduino.  All right reserved.\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n  See the GNU Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n#ifndef _DMA_STREAM_HANDLERS_\n#define _DMA_STREAM_HANDLERS_\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n\n#include \"def.h\"\n#include \"bsp.h\"\ntypedef void (*DMALoseStreamHandlerCallbackFunction_t)(uint8_t iStream);  \nextern bool SetDMA1StreamHandlerHandle(uint8_t iStream, DMA_HandleTypeDef *hdma, \n        bool fOverwrite, DMALoseStreamHandlerCallbackFunction_t loseCB);\nextern bool SetDMA2StreamHandlerHandle(uint8_t iStream, DMA_HandleTypeDef *hdma, \n        bool fOverwrite, DMALoseStreamHandlerCallbackFunction_t loseCB);\n#ifdef __cplusplus\n}\n#endif\n\n\n#endif  // _DMA_STREAM_HANDLERS_"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/drv_adc.c",
    "content": "/*\n *  drv_adc.c\n *\n *  Created on: 2016. 5. 14.\n *      Author: Baram, PBHP\n */\n\n#include \"drv_adc.h\"\n#include \"variant.h\"\n\n\nADC_HandleTypeDef hADC1;\nADC_HandleTypeDef hADC3;\n\n\nint drv_adc_init()\n{\n  hADC3.Instance                   = ADC3;\n  hADC3.Init.ClockPrescaler        = ADC_CLOCKPRESCALER_PCLK_DIV4;\n  hADC3.Init.Resolution            = ADC_RESOLUTION_12B;\n  hADC3.Init.ScanConvMode          = DISABLE;\n  hADC3.Init.ContinuousConvMode    = DISABLE;\n  hADC3.Init.DiscontinuousConvMode = DISABLE;\n  hADC3.Init.NbrOfDiscConversion   = 0;\n  hADC3.Init.ExternalTrigConv      = ADC_SOFTWARE_START;\n  hADC3.Init.DataAlign             = ADC_DATAALIGN_RIGHT;\n  hADC3.Init.NbrOfConversion       = 1;\n  hADC3.Init.DMAContinuousRequests = DISABLE;\n  hADC3.Init.EOCSelection          = DISABLE;\n\n  if (HAL_ADC_Init(&hADC3) != HAL_OK)\n  {\n    return -1;\n  }\n\n\n  hADC1.Instance                   = ADC1;\n  hADC1.Init.ClockPrescaler        = ADC_CLOCKPRESCALER_PCLK_DIV4;\n  hADC1.Init.Resolution            = ADC_RESOLUTION_12B;\n  hADC1.Init.ScanConvMode          = DISABLE;\n  hADC1.Init.ContinuousConvMode    = DISABLE;\n  hADC1.Init.DiscontinuousConvMode = DISABLE;\n  hADC1.Init.NbrOfDiscConversion   = 0;\n  hADC1.Init.ExternalTrigConv      = ADC_SOFTWARE_START;\n  hADC1.Init.DataAlign             = ADC_DATAALIGN_RIGHT;\n  hADC1.Init.NbrOfConversion       = 1;\n  hADC1.Init.DMAContinuousRequests = DISABLE;\n  hADC1.Init.EOCSelection          = DISABLE;\n\n  if (HAL_ADC_Init(&hADC1) != HAL_OK)\n  {\n    return -1;\n  }\n\n  return 0;\n}\n\n\nvoid drv_adc_pin_init( uint32_t ulPin )\n{\n  GPIO_InitTypeDef GPIO_InitStruct;\n\n\n  if( g_Pin2PortMapArray[ulPin].GPIOx_Port == NULL ) return;\n\n\n  HAL_GPIO_DeInit(g_Pin2PortMapArray[ulPin].GPIOx_Port, g_Pin2PortMapArray[ulPin].Pin_abstraction);\n\n  GPIO_InitStruct.Pin = g_Pin2PortMapArray[ulPin].Pin_abstraction;\n  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;\n  GPIO_InitStruct.Pull = GPIO_NOPULL;\n  HAL_GPIO_Init(g_Pin2PortMapArray[ulPin].GPIOx_Port, &GPIO_InitStruct);\n}\n\n\nvoid HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)\n{\n  uint8_t i;\n  GPIO_InitTypeDef GPIO_InitStruct;\n\n\n  i = 0;\n  while(1)\n  {\n    if( g_Pin2PortMapArray[i].GPIOx_Port == NULL ) break;\n\n    if( hadc->Instance == ADC3 )\n    {\n      __HAL_RCC_ADC3_CLK_ENABLE();\n    }\n    if( hadc->Instance == ADC1 )\n    {\n      __HAL_RCC_ADC1_CLK_ENABLE();\n    }\n\n    HAL_GPIO_DeInit(g_Pin2PortMapArray[i].GPIOx_Port, g_Pin2PortMapArray[i].Pin_abstraction);\n\n    GPIO_InitStruct.Pin = g_Pin2PortMapArray[i].Pin_abstraction;\n    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\n    HAL_GPIO_Init(g_Pin2PortMapArray[i].GPIOx_Port, &GPIO_InitStruct);\n\n    i++;\n  }\n}\n\nvoid HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)\n{\n  uint8_t i;\n\n\n  i = 0;\n  while(1)\n  {\n    if( g_Pin2PortMapArray[i].GPIOx_Port == NULL ) break;\n\n    if( hadc->Instance == ADC3 )\n    {\n      __HAL_RCC_ADC3_CLK_DISABLE();\n    }\n    if( hadc->Instance == ADC1 )\n    {\n      __HAL_RCC_ADC1_CLK_DISABLE();\n    }\n\n    HAL_GPIO_DeInit(g_Pin2PortMapArray[i].GPIOx_Port, g_Pin2PortMapArray[i].Pin_abstraction);\n\n    i++;\n  }\n}\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/drv_adc.h",
    "content": "/*\n *  drv_adc.h\n *\n *  Created on: 2016. 5. 14.\n *      Author: Baram, PBHP\n */\n\n#ifndef DRV_ADC_H\n#define DRV_ADC_H\n\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n\n#include \"def.h\"\n#include \"bsp.h\"\n\n\n\n\nextern ADC_HandleTypeDef hADC1;\nextern ADC_HandleTypeDef hADC3;\n\n\n\nint drv_adc_init();\nvoid drv_adc_pin_init( uint32_t ulPin );\n\n\n#ifdef __cplusplus\n}\n#endif\n\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/drv_can.c",
    "content": "/*\r\n * drv_can.c\r\n *\r\n *  Created on: 2017. 11. 7.\r\n *      Author: opus\r\n */\r\n\r\n#include <string.h>\r\n#include \"drv_can.h\"\r\n#include \"hw.h\"\r\n#include \"ring.h\"\r\n\r\n\r\n/* a popular industrial application has optional settings of 125 kbps, 250 kbps, or 500 kbps  */\r\n#define _DRV_CAN_58MHZ_1000KBPS_PRE  3\r\n#define _DRV_CAN_58MHZ_1000KBPS_TS1  CAN_BS1_13TQ\r\n#define _DRV_CAN_58MHZ_1000KBPS_TS2  CAN_BS2_4TQ\r\n\r\n#define _DRV_CAN_58MHZ_500KBPS_PRE   6\r\n#define _DRV_CAN_58MHZ_500KBPS_TS1   CAN_BS1_13TQ\r\n#define _DRV_CAN_58MHZ_500KBPS_TS2   CAN_BS2_4TQ\r\n\r\n#define _DRV_CAN_58MHZ_250KBPS_PRE   12\r\n#define _DRV_CAN_58MHZ_250KBPS_TS1   CAN_BS1_13TQ\r\n#define _DRV_CAN_58MHZ_250KBPS_TS2   CAN_BS2_4TQ\r\n\r\n#define _DRV_CAN_58MHZ_125KBPS_PRE   27\r\n#define _DRV_CAN_58MHZ_125KBPS_TS1   CAN_BS1_11TQ\r\n#define _DRV_CAN_58MHZ_125KBPS_TS2   CAN_BS2_4TQ\r\n\r\n#define CAN2_FILTER_BANK_START_NUM   0\r\n\r\n\r\n\r\ntypedef struct \r\n{\r\n  CAN_HandleTypeDef *p_hCANx;\r\n  void (*handler)(void *arg);\r\n  uint8_t rx_fifo;\r\n} drv_can_t;\r\n\r\nstatic CAN_HandleTypeDef   hCAN2;\r\n\r\nstatic ring_node_t ring_msg[DRV_CAN_MAX_CH];\r\nstatic ring_node_t ring_data[DRV_CAN_MAX_CH];\r\n\r\nstatic drv_can_msg_t can_msg[DRV_CAN_MAX_CH][DRV_CAN_MSG_RX_BUF_MAX];\r\nstatic uint8_t can_data[DRV_CAN_MAX_CH][DRV_CAN_DATA_RX_BUF_MAX];\r\n\r\nstatic drv_can_t drv_can_tbl[DRV_CAN_MAX_CH] =\r\n{\r\n  {&hCAN2, NULL, CAN_RX_FIFO0}\r\n};\r\n\r\n\r\nvoid drvCanInit(void)\r\n{\r\n  uint8_t i;\r\n\r\n  for(i = 0; i < DRV_CAN_MAX_CH; i++)\r\n  {\r\n    ringCreate(&ring_msg[i], DRV_CAN_MSG_RX_BUF_MAX);\r\n    ringCreate(&ring_data[i], DRV_CAN_DATA_RX_BUF_MAX);\r\n  }\r\n}\r\n\r\nbool drvCanOpen(uint8_t channel, uint32_t baudrate, uint8_t format)\r\n{\r\n  if(channel > DRV_CAN_MAX_CH)\r\n  {\r\n    return false;\r\n  }\r\n\r\n  CAN_HandleTypeDef *p_hCANx = drv_can_tbl[channel].p_hCANx;\r\n  uint32_t prescale, bs1, bs2;\r\n\r\n  switch(baudrate)\r\n  {\r\n    case _DEF_CAN_BAUD_125K :\r\n      prescale = _DRV_CAN_58MHZ_125KBPS_PRE;\r\n      bs1      = _DRV_CAN_58MHZ_125KBPS_TS1;\r\n      bs2      = _DRV_CAN_58MHZ_125KBPS_TS2;\r\n      break;\r\n\r\n    case _DEF_CAN_BAUD_250K :\r\n      prescale = _DRV_CAN_58MHZ_250KBPS_PRE;\r\n      bs1      = _DRV_CAN_58MHZ_250KBPS_TS1;\r\n      bs2      = _DRV_CAN_58MHZ_250KBPS_TS2;\r\n      break;\r\n\r\n    case _DEF_CAN_BAUD_500K :\r\n      prescale = _DRV_CAN_58MHZ_500KBPS_PRE;\r\n      bs1      = _DRV_CAN_58MHZ_500KBPS_TS1;\r\n      bs2      = _DRV_CAN_58MHZ_500KBPS_TS2;\r\n      break;\r\n\r\n    case _DEF_CAN_BAUD_1000K :\r\n      prescale = _DRV_CAN_58MHZ_1000KBPS_PRE;\r\n      bs1      = _DRV_CAN_58MHZ_1000KBPS_TS1;\r\n      bs2      = _DRV_CAN_58MHZ_1000KBPS_TS2;\r\n      break;\r\n\r\n    default :\r\n      prescale = _DRV_CAN_58MHZ_125KBPS_PRE;\r\n      bs1      = _DRV_CAN_58MHZ_125KBPS_TS1;\r\n      bs2      = _DRV_CAN_58MHZ_125KBPS_TS2;\r\n      break;\r\n  }\r\n\r\n  switch(channel)\r\n  {\r\n    case _DEF_CAN1 :\r\n    case _DEF_CAN2 :\r\n    default :\r\n      p_hCANx->Instance  = CAN2;\r\n\r\n      p_hCANx->Init.Mode = CAN_MODE_NORMAL;\r\n      p_hCANx->Init.SyncJumpWidth  = CAN_SJW_1TQ;\r\n      p_hCANx->Init.Prescaler = prescale;\r\n      p_hCANx->Init.TimeSeg1  = bs1;\r\n      p_hCANx->Init.TimeSeg2  = bs2;\r\n      p_hCANx->Init.AutoBusOff = ENABLE;\r\n      p_hCANx->Init.AutoWakeUp = DISABLE;\r\n      p_hCANx->Init.AutoRetransmission = ENABLE;\r\n      p_hCANx->Init.ReceiveFifoLocked = DISABLE;\r\n      p_hCANx->Init.TransmitFifoPriority = DISABLE;\r\n      break;\r\n  }\r\n\r\n  if (HAL_CAN_Init(p_hCANx) != HAL_OK)\r\n  {\r\n    return false;\r\n  }\r\n\r\n  /* Default Setup Filter */\r\n  drvCanConfigFilter(0, 0x0, 0x0, format);\r\n\r\n  /*##-3- Start the CAN peripheral ###########################################*/\r\n  if (HAL_CAN_Start(p_hCANx) != HAL_OK)\r\n  {\r\n    return false;\r\n  }\r\n\r\n  HAL_CAN_ActivateNotification(p_hCANx, CAN_IT_ERROR);\r\n  HAL_CAN_ActivateNotification(p_hCANx, CAN_IT_LAST_ERROR_CODE);\r\n  HAL_CAN_ActivateNotification(p_hCANx, CAN_IT_BUSOFF);\r\n  HAL_CAN_ActivateNotification(p_hCANx, CAN_IT_ERROR_PASSIVE);\r\n  HAL_CAN_ActivateNotification(p_hCANx, CAN_IT_ERROR_WARNING);\r\n\r\n  drvCanAttachRxInterrupt(channel, NULL);\r\n\r\n  return true;\r\n}\r\n\r\nvoid drvCanClose(uint8_t channel)\r\n{\r\n  if(channel > DRV_CAN_MAX_CH)\r\n  {\r\n    return;\r\n  }\r\n\r\n  CAN_HandleTypeDef *p_hCANx = drv_can_tbl[channel].p_hCANx;\r\n\r\n  drvCanDetachRxInterrupt(channel);\r\n  HAL_CAN_DeactivateNotification(p_hCANx, CAN_IT_LAST_ERROR_CODE);\r\n  HAL_CAN_DeactivateNotification(p_hCANx, CAN_IT_BUSOFF);\r\n  HAL_CAN_DeactivateNotification(p_hCANx, CAN_IT_ERROR_PASSIVE);\r\n  HAL_CAN_DeactivateNotification(p_hCANx, CAN_IT_ERROR_WARNING);\r\n  HAL_CAN_DeactivateNotification(p_hCANx, CAN_IT_ERROR);\r\n\r\n  HAL_CAN_DeInit(p_hCANx);\r\n  HAL_CAN_MspDeInit(p_hCANx);\r\n}\r\n\r\nbool drvCanConfigFilter(uint8_t filter_num, uint32_t id, uint32_t mask, uint8_t format)\r\n{\r\n  CAN_FilterTypeDef  sFilterConfig;\r\n\r\n  uint32_t reserved;\r\n  uint32_t reg_id;\r\n  uint32_t reg_mask;\r\n\r\n  switch(format)\r\n  {\r\n    case _DEF_CAN_STD :\r\n      reserved = _DEF_CAN_STD | CAN_RTR_DATA;\r\n      reg_id   = (id << 21) | reserved;\r\n      reg_mask = (mask << 21) | reserved;\r\n      break;\r\n\r\n    case _DEF_CAN_EXT :\r\n    default :\r\n      reserved = _DEF_CAN_EXT | CAN_RTR_DATA;\r\n      reg_id   = ((id << 3) | reserved);// & 0x1FFFFF;\r\n      reg_mask = ((mask << 3) | reserved);// & 0x1FFFFF;\r\n      break;\r\n  }\r\n\r\n  sFilterConfig.FilterBank = filter_num;\r\n  sFilterConfig.FilterMode   = CAN_FILTERMODE_IDMASK;\r\n  sFilterConfig.FilterScale  = CAN_FILTERSCALE_32BIT;\r\n  sFilterConfig.FilterIdHigh = reg_id >> 16;\r\n  sFilterConfig.FilterIdLow  = reg_id;\r\n  sFilterConfig.FilterMaskIdHigh = reg_mask >> 16;\r\n  sFilterConfig.FilterMaskIdLow  = reg_mask;\r\n  sFilterConfig.FilterFIFOAssignment = CAN_FILTER_FIFO0;\r\n  sFilterConfig.SlaveStartFilterBank   = CAN2_FILTER_BANK_START_NUM;\r\n\r\n  sFilterConfig.FilterActivation = ENABLE;\r\n\r\n  if(HAL_CAN_ConfigFilter(&hCAN2, &sFilterConfig) != HAL_OK)\r\n  {\r\n    return false;\r\n  }   \r\n\r\n  return true;\r\n}\r\n\r\nuint32_t drvCanWrite(uint8_t channel, uint32_t id, uint8_t *p_data, uint32_t length, uint8_t format)\r\n{\r\n  if((channel > DRV_CAN_MAX_CH)||(id > 0x1FFFFFFF))\r\n    return 0;\r\n\r\n  if(p_data == NULL && length > 0)\r\n    return 0;   \r\n\r\n  uint32_t tx_len, sent_len, i;\r\n  CAN_HandleTypeDef *p_hCANx = drv_can_tbl[channel].p_hCANx;\r\n  CAN_TxHeaderTypeDef tx_header;\r\n  uint8_t tx_data[DRV_CAN_MAX_BYTE_IN_MSG];\r\n  uint32_t tx_mailbox;\r\n    \r\n  switch(format)\r\n  {\r\n    case _DEF_CAN_STD :\r\n      tx_header.IDE   = CAN_ID_STD;\r\n      tx_header.StdId = id;\r\n      break;\r\n\r\n    case _DEF_CAN_EXT :\r\n    default :\r\n      tx_header.IDE   = CAN_ID_EXT;\r\n      tx_header.ExtId = id;\r\n      break;\r\n  }\r\n\r\n  tx_header.RTR   = CAN_RTR_DATA;\r\n\r\n  sent_len = 0;\r\n\r\n  while(sent_len < length)\r\n  {\r\n    tx_len = length - sent_len;\r\n    if (tx_len > DRV_CAN_MAX_BYTE_IN_MSG)\r\n    {\r\n      tx_len = DRV_CAN_MAX_BYTE_IN_MSG;\r\n    }\r\n\r\n    for(i = 0; i < tx_len; i++)\r\n    {\r\n      tx_data[i] = p_data[sent_len + i];\r\n    }\r\n\r\n    tx_header.DLC = tx_len;\r\n\r\n    if(HAL_CAN_AddTxMessage(p_hCANx, &tx_header, tx_data, &tx_mailbox) == HAL_OK)\r\n    {\r\n      /* Wait transmission complete */\r\n      while(HAL_CAN_GetTxMailboxesFreeLevel(p_hCANx) != 3);\r\n\r\n      sent_len += tx_len;\r\n    }\r\n  }\r\n\r\n  if(length == 0)\r\n  {\r\n    tx_header.DLC = 0;\r\n\r\n    if(HAL_CAN_AddTxMessage(p_hCANx, &tx_header, tx_data, &tx_mailbox) == HAL_OK)\r\n    {\r\n      /* Wait transmission complete */\r\n      while(HAL_CAN_GetTxMailboxesFreeLevel(p_hCANx) != 3);\r\n    }\r\n  }\r\n\r\n  return sent_len;\r\n}\r\n\r\n\r\nuint8_t drvCanRead(uint8_t channel)\r\n{\r\n  if(channel > DRV_CAN_MAX_CH)\r\n  {\r\n    return 0;\r\n  }\r\n\r\n  uint8_t ret = 0;\r\n\r\n  ret = can_data[channel][ringGetReadIndex(&ring_data[channel])];\r\n\r\n  ringReadUpdate(&ring_data[channel]);\r\n\r\n  return ret;\r\n}\r\n\r\nuint32_t drvCanAvailable(uint8_t channel)\r\n{\r\n  if(channel > DRV_CAN_MAX_CH)\r\n  {\r\n    return 0;\r\n  }\r\n\r\n  return ringReadAvailable(&ring_data[channel]);\r\n}\r\n\r\nuint32_t drvCanWriteMsg(uint8_t channel, drv_can_msg_t *p_msg)\r\n{\r\n  return drvCanWrite(channel, p_msg->id, p_msg->data, p_msg->length, p_msg->format);\r\n}\r\n\r\ndrv_can_msg_t* drvCanReadMsg(uint8_t channel)\r\n{\r\n  if(channel > DRV_CAN_MAX_CH)\r\n  {\r\n    return NULL;\r\n  }\r\n\r\n  drv_can_msg_t* p_ret = &can_msg[channel][ringGetReadIndex(&ring_msg[channel])];\r\n\r\n  ringReadUpdate(&ring_msg[channel]);\r\n\r\n  return p_ret;\r\n}\r\n\r\nuint32_t drvCanAvailableMsg(uint8_t channel)\r\n{\r\n  if(channel > DRV_CAN_MAX_CH)\r\n  {\r\n    return 0;\r\n  }\r\n\r\n  return ringReadAvailable(&ring_msg[channel]);\r\n}\r\n\r\n\r\nuint8_t drvCanGetErrCount(uint8_t channel)\r\n{\r\n  if(channel > DRV_CAN_MAX_CH)\r\n  {\r\n    return 0;\r\n  }\r\n\r\n  return (drv_can_tbl[channel].p_hCANx->Instance->ESR) >> 24;\r\n}\r\n\r\nuint32_t drvCanGetError(uint8_t channel)\r\n{\r\n  if(channel > DRV_CAN_MAX_CH)\r\n  {\r\n    return 0;\r\n  }\r\n\r\n  CAN_HandleTypeDef *p_hCANx = drv_can_tbl[channel].p_hCANx;\r\n\r\n  return HAL_CAN_GetError(p_hCANx);\r\n}\r\n\r\nuint32_t drvCanGetState(uint8_t channel)\r\n{\r\n  if(channel > DRV_CAN_MAX_CH)\r\n  {\r\n    return 0;\r\n  }\r\n\r\n  CAN_HandleTypeDef *p_hCANx = drv_can_tbl[channel].p_hCANx;\r\n\r\n  return HAL_CAN_GetState(p_hCANx);\r\n}\r\n\r\nvoid drvCanAttachRxInterrupt(uint8_t channel, void (*handler)(void *arg))\r\n{\r\n  if(channel > DRV_CAN_MAX_CH)\r\n  {\r\n    return;\r\n  }\r\n\r\n  CAN_HandleTypeDef *p_hCANx = drv_can_tbl[channel].p_hCANx;\r\n\r\n  drv_can_tbl[channel].handler = handler;\r\n\r\n  switch(drv_can_tbl[channel].rx_fifo)\r\n  {\r\n    case CAN_RX_FIFO0:\r\n      HAL_CAN_ActivateNotification(p_hCANx, CAN_IT_RX_FIFO0_MSG_PENDING);\r\n      break;\r\n      \r\n    case CAN_RX_FIFO1:\r\n      HAL_CAN_ActivateNotification(p_hCANx, CAN_IT_RX_FIFO1_MSG_PENDING);\r\n      break;\r\n      \r\n    default:\r\n      break;\r\n  }\r\n}\r\n\r\nvoid drvCanDetachRxInterrupt(uint8_t channel)\r\n{\r\n  if(channel > DRV_CAN_MAX_CH)\r\n  {\r\n    return;\r\n  }\r\n\r\n  CAN_HandleTypeDef *p_hCANx = drv_can_tbl[channel].p_hCANx;\r\n\r\n  drv_can_tbl[channel].handler = NULL;\r\n\r\n  switch(drv_can_tbl[channel].rx_fifo)\r\n  {\r\n    case CAN_RX_FIFO0:\r\n      HAL_CAN_DeactivateNotification(p_hCANx, CAN_IT_RX_FIFO0_MSG_PENDING);\r\n      break;\r\n      \r\n    case CAN_RX_FIFO1:\r\n      HAL_CAN_DeactivateNotification(p_hCANx, CAN_IT_RX_FIFO1_MSG_PENDING);\r\n      break;\r\n      \r\n    default:\r\n      break;\r\n  }\r\n}\r\n\r\n\r\nvoid HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef* hcan)\r\n{\r\n  uint8_t channel, msg_idx, i;\r\n  drv_can_msg_t *rx_buf;\r\n  uint8_t rx_data[DRV_CAN_MAX_BYTE_IN_MSG];\r\n  CAN_RxHeaderTypeDef rx_header;\r\n  \r\n  for( channel = 0; channel<DRV_CAN_MAX_CH; channel++ )\r\n  {\r\n    if( hcan->Instance == drv_can_tbl[channel].p_hCANx->Instance )\r\n    {\r\n      if (HAL_CAN_GetRxMessage(hcan, drv_can_tbl[channel].rx_fifo, &rx_header, rx_data) == HAL_OK)\r\n      {\r\n        msg_idx = ringGetWriteIndex(&ring_msg[channel]);  \r\n        rx_buf  = &can_msg[channel][msg_idx];\r\n\r\n        if(rx_header.IDE == CAN_ID_STD)\r\n        {\r\n          rx_buf->id = rx_header.StdId;  \r\n          rx_buf->format = _DEF_CAN_STD;\r\n        }\r\n        else\r\n        {\r\n          rx_buf->id = rx_header.ExtId;\r\n          rx_buf->format = _DEF_CAN_EXT;\r\n        }\r\n        rx_buf->length = rx_header.DLC;\r\n        memcpy(rx_buf->data, rx_data, rx_buf->length);\r\n        ringWriteUpdate(&ring_msg[channel]);\r\n\r\n        if( drv_can_tbl[channel].handler != NULL )\r\n        {\r\n          (*drv_can_tbl[channel].handler)((void *)rx_buf);\r\n          ringReadUpdate(&ring_msg[channel]);\r\n        }\r\n        else  //store byte data\r\n        {\r\n          for(i = 0; i < rx_buf->length; i++)\r\n          {\r\n            can_data[channel][ringGetWriteIndex(&ring_data[channel])] = rx_buf->data[i];\r\n            ringWriteUpdate(&ring_data[channel]);\r\n          }\r\n        }\r\n      }      \r\n    }\r\n  }\r\n}\r\n\r\nvoid HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)\r\n{\r\n  UNUSED(hcan);\r\n}\r\n\r\nvoid CAN2_RX0_IRQHandler(void)\r\n{\r\n  HAL_CAN_IRQHandler(&hCAN2);\r\n}\r\n\r\nvoid HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)\r\n{\r\n  GPIO_InitTypeDef GPIO_InitStruct;\r\n\r\n  if(hcan->Instance==CAN2)\r\n  {\r\n    /* Peripheral clock enable */\r\n    __HAL_RCC_CAN2_CLK_ENABLE();\r\n    __HAL_RCC_CAN1_CLK_ENABLE();\r\n\r\n    GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13;\r\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\r\n    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\r\n    GPIO_InitStruct.Alternate = GPIO_AF9_CAN2;\r\n    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\r\n\r\n    /* CAN2 interrupt Init */\r\n    HAL_NVIC_SetPriority(CAN2_RX0_IRQn, 4, 1);\r\n    HAL_NVIC_EnableIRQ(CAN2_RX0_IRQn);\r\n  }\r\n}\r\n\r\nvoid HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)\r\n{\r\n  if(hcan->Instance==CAN2)\r\n  {\r\n    __HAL_RCC_CAN1_CLK_DISABLE();\r\n    __HAL_RCC_CAN2_CLK_DISABLE();\r\n\r\n    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_12|GPIO_PIN_13);\r\n\r\n    /* CAN2 interrupt DeInit */\r\n    HAL_NVIC_DisableIRQ(CAN2_RX0_IRQn);\r\n  }\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/drv_can.h",
    "content": "/*\n * drv_can.h\n *\n *  Created on: 2017. 11. 7.\n *      Author: opus\n */\n\n#ifndef DRV_CAN_H_\n#define DRV_CAN_H_\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n#include \"def.h\"\n#include \"bsp.h\"\n\n\n\n#define DRV_CAN_MAX_CH           1\n#define DRV_CAN_MAX_BYTE_IN_MSG  8\n#define DRV_CAN_MSG_RX_BUF_MAX   8\n#define DRV_CAN_DATA_RX_BUF_MAX  128\n\ntypedef struct {\n  uint32_t id;\n  uint32_t length;\n  uint8_t  data[DRV_CAN_MAX_BYTE_IN_MSG];\n  uint8_t  format;\n} drv_can_msg_t;\n\n\nvoid drvCanInit(void);\nbool drvCanOpen(uint8_t channel, uint32_t baudrate, uint8_t format);\nvoid drvCanClose(uint8_t channel);\nbool drvCanConfigFilter(uint8_t filter_num, uint32_t id, uint32_t mask, uint8_t format);\nuint32_t drvCanWrite(uint8_t channel, uint32_t id, uint8_t *p_data, uint32_t length, uint8_t format);\nuint8_t drvCanRead(uint8_t channel);\nuint32_t drvCanAvailable(uint8_t channel);\nuint32_t drvCanWriteMsg(uint8_t channel, drv_can_msg_t *p_msg);\ndrv_can_msg_t* drvCanReadMsg(uint8_t channel);\nuint32_t drvCanAvailableMsg(uint8_t channel);\n\nuint8_t drvCanGetErrCount(uint8_t channel);\nuint32_t drvCanGetError(uint8_t channel);\nuint32_t drvCanGetState(uint8_t channel);\n\nvoid drvCanAttachRxInterrupt(uint8_t channel, void (*handler)(void *arg));\nvoid drvCanDetachRxInterrupt(uint8_t channel);\n\n\n#ifdef __cplusplus\n }\n#endif\n\n#endif /* DRV_CAN_H_ */\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/drv_dxl.c",
    "content": "/*\n *  drv_dxl.c\n *\n *  Created on: 2016. 7. 13.\n *      Author: Baram, PBHP\n */\n\n#include \"drv_dxl.h\"\n#include \"variant.h\"\n\n\n\n\n\nint drv_dxl_init()\n{\n  GPIO_InitTypeDef GPIO_InitStruct;\n\n\n  GPIO_InitStruct.Pin   = GPIO_PIN_9;\n  GPIO_InitStruct.Mode  = GPIO_MODE_OUTPUT_PP;\n  GPIO_InitStruct.Pull  = GPIO_NOPULL;\n  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;\n  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);\n\n  drv_dxl_tx_enable(FALSE);\n\n  return 0;\n}\n\n\nvoid drv_dxl_tx_enable( BOOL enable )\n{\n  if( enable == TRUE )  HAL_GPIO_WritePin(GPIOC, GPIO_PIN_9, GPIO_PIN_SET);\n  else                  HAL_GPIO_WritePin(GPIOC, GPIO_PIN_9, GPIO_PIN_RESET);\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/drv_dxl.h",
    "content": "/*\n *  drv_dxl.h\n *\n *  Created on: 2016. 7.23.\n *      Author: Baram, PBHP\n */\n\n#ifndef DRV_DXL_H\n#define DRV_DXL_H\n\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n\n#include \"def.h\"\n#include \"bsp.h\"\n\n\n\n\n\n\nint drv_dxl_init();\n\nvoid drv_dxl_tx_enable( BOOL enable );\n\n\n#ifdef __cplusplus\n}\n#endif\n\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/drv_eeprom.c",
    "content": "/*\n *  drv_eeprom.c\n *\n *  Created on: 2016. 7. 13.\n *      Author: Baram, PBHP\n */\n\n#include \"drv_eeprom.h\"\n#include \"variant.h\"\n\n\n\n\n\nstatic bool IsInit = false;\n\n\n/* Global variable used to store variable value in read sequence */\nuint16_t DataVar = 0;\n\n\n/* Private function prototypes -----------------------------------------------*/\n/* Private functions ---------------------------------------------------------*/\nstatic uint16_t EE_Init(void);\nstatic uint16_t EE_ReadVariable(uint16_t VirtAddress, uint16_t* Data);\nstatic uint16_t EE_WriteVariable(uint16_t VirtAddress, uint16_t Data);\nstatic HAL_StatusTypeDef EE_Format(void);\nstatic uint16_t EE_FindValidPage(uint8_t Operation);\nstatic uint16_t EE_VerifyPageFullWriteVariable(uint16_t VirtAddress, uint16_t Data);\nstatic uint16_t EE_PageTransfer(uint16_t VirtAddress, uint16_t Data);\nstatic uint16_t EE_VerifyPageFullyErased(uint32_t Address);\n\n\n\n/* Exported constants --------------------------------------------------------*/\n/* EEPROM emulation firmware error codes */\n#define EE_OK      (uint32_t)HAL_OK\n#define EE_ERROR   (uint32_t)HAL_ERROR\n#define EE_BUSY    (uint32_t)HAL_BUSY\n#define EE_TIMEOUT (uint32_t)HAL_TIMEOUT\n\n/* Define the size of the sectors to be used */\n#define PAGE_SIZE             (uint32_t)0x8000  /* Page size */\n\n/* Device voltage range supposed to be [2.7V to 3.6V], the operation will\n   be done by word  */\n#define VOLTAGE_RANGE         (uint8_t)VOLTAGE_RANGE_3\n\n/* EEPROM start address in Flash */\n#define EEPROM_START_ADDRESS  ((uint32_t)0x08010000) /* EEPROM emulation start address */\n\n/* Pages 0 and 1 base and end addresses */\n#define PAGE0_BASE_ADDRESS    ((uint32_t)(EEPROM_START_ADDRESS + 0x0000))\n#define PAGE0_END_ADDRESS     ((uint32_t)(EEPROM_START_ADDRESS + (PAGE_SIZE - 1)))\n#define PAGE0_ID               FLASH_SECTOR_2\n\n#define PAGE1_BASE_ADDRESS    ((uint32_t)(EEPROM_START_ADDRESS + 0x8000))\n#define PAGE1_END_ADDRESS     ((uint32_t)(EEPROM_START_ADDRESS + (2 * PAGE_SIZE - 1)))\n#define PAGE1_ID               FLASH_SECTOR_3\n\n/* Used Flash pages for EEPROM emulation */\n#define PAGE0                 ((uint16_t)0x0000)\n#define PAGE1                 ((uint16_t)0x0001) /* Page nb between PAGE0_BASE_ADDRESS & PAGE1_BASE_ADDRESS*/\n\n/* No valid page define */\n#define NO_VALID_PAGE         ((uint16_t)0x00AB)\n\n/* Page status definitions */\n#define ERASED                ((uint16_t)0xFFFF)     /* Page is empty */\n#define RECEIVE_DATA          ((uint16_t)0xEEEE)     /* Page is marked to receive data */\n#define VALID_PAGE            ((uint16_t)0x0000)     /* Page containing valid data */\n\n/* Valid pages in read and write defines */\n#define READ_FROM_VALID_PAGE  ((uint8_t)0x00)\n#define WRITE_IN_VALID_PAGE   ((uint8_t)0x01)\n\n/* Page full define */\n#define PAGE_FULL             ((uint8_t)0x80)\n\n/* Variables' number */\n#define NB_OF_VAR             (4*1024) //4KB\n\n\n/* Virtual address defined by the user: 0xFFFF value is prohibited */\nstatic uint16_t VirtAddVarTab[NB_OF_VAR];\n\n\n\n\nint drv_eeprom_init()\n{\n  uint16_t i;\n\n\n  for( i=0; i<NB_OF_VAR; i++ )\n  {\n    VirtAddVarTab[i] = i;\n  }\n\n\n  HAL_FLASH_Unlock();\n\n  if( EE_Init() == EE_OK )\n  {\n    IsInit = true;\n  }\n\n  return 0;\n}\n\n\n\nuint8_t drv_eeprom_read_byte(int addr)\n{\n  uint16_t read_value;\n\n\n  if( IsInit == false ) return 0;\n\n  EE_ReadVariable((uint16_t)addr,  &read_value);\n\n  return (uint8_t)read_value;\n}\n\n\nvoid drv_eeprom_write_byte(int index, uint8_t data_in)\n{\n  if( IsInit == false ) return;\n\n  EE_WriteVariable(index, (uint16_t)data_in);\n}\n\n\nuint16_t drv_eeprom_get_length(void)\n{\n  if( IsInit == false ) return 0;\n\n  return NB_OF_VAR;\n}\n\n\n\n\n\n/**\n  * @brief  Restore the pages to a known good state in case of page's status\n  *   corruption after a power loss.\n  * @param  None.\n  * @retval - Flash error code: on write Flash error\n  *         - FLASH_COMPLETE: on success\n  */\nuint16_t EE_Init(void)\n{\n  uint16_t PageStatus0 = 6, PageStatus1 = 6;\n  uint16_t VarIdx = 0;\n  uint16_t EepromStatus = 0, ReadStatus = 0;\n  int16_t x = -1;\n  HAL_StatusTypeDef  FlashStatus;\n  uint32_t SectorError = 0;\n  FLASH_EraseInitTypeDef pEraseInit;\n\n\n  /* Get Page0 status */\n  PageStatus0 = (*(__IO uint16_t*)PAGE0_BASE_ADDRESS);\n  /* Get Page1 status */\n  PageStatus1 = (*(__IO uint16_t*)PAGE1_BASE_ADDRESS);\n\n  pEraseInit.TypeErase = TYPEERASE_SECTORS;\n  pEraseInit.Sector = PAGE0_ID;\n  pEraseInit.NbSectors = 1;\n  pEraseInit.VoltageRange = VOLTAGE_RANGE;\n\n  /* Check for invalid header states and repair if necessary */\n  switch (PageStatus0)\n  {\n    case ERASED:\n      if (PageStatus1 == VALID_PAGE) /* Page0 erased, Page1 valid */\n      {\n          /* Erase Page0 */\n        if(!EE_VerifyPageFullyErased(PAGE0_BASE_ADDRESS))\n        {\n          FlashStatus = HAL_FLASHEx_Erase(&pEraseInit, &SectorError);\n          /* If erase operation was failed, a Flash error code is returned */\n          if (FlashStatus != HAL_OK)\n          {\n            return FlashStatus;\n          }\n        }\n      }\n      else if (PageStatus1 == RECEIVE_DATA) /* Page0 erased, Page1 receive */\n      {\n        /* Erase Page0 */\n        if(!EE_VerifyPageFullyErased(PAGE0_BASE_ADDRESS))\n        {\n          FlashStatus = HAL_FLASHEx_Erase(&pEraseInit, &SectorError);\n          /* If erase operation was failed, a Flash error code is returned */\n          if (FlashStatus != HAL_OK)\n          {\n            return FlashStatus;\n          }\n        }\n        /* Mark Page1 as valid */\n        FlashStatus = HAL_FLASH_Program(TYPEPROGRAM_HALFWORD, PAGE1_BASE_ADDRESS, VALID_PAGE);\n        /* If program operation was failed, a Flash error code is returned */\n        if (FlashStatus != HAL_OK)\n        {\n          return FlashStatus;\n        }\n      }\n      else /* First EEPROM access (Page0&1 are erased) or invalid state -> format EEPROM */\n      {\n        /* Erase both Page0 and Page1 and set Page0 as valid page */\n        FlashStatus = EE_Format();\n        /* If erase/program operation was failed, a Flash error code is returned */\n        if (FlashStatus != HAL_OK)\n        {\n          return FlashStatus;\n        }\n      }\n      break;\n\n    case RECEIVE_DATA:\n      if (PageStatus1 == VALID_PAGE) /* Page0 receive, Page1 valid */\n      {\n        /* Transfer data from Page1 to Page0 */\n        for (VarIdx = 0; VarIdx < NB_OF_VAR; VarIdx++)\n        {\n          if (( *(__IO uint16_t*)(PAGE0_BASE_ADDRESS + 6)) == VirtAddVarTab[VarIdx])\n          {\n            x = VarIdx;\n          }\n          if (VarIdx != x)\n          {\n            /* Read the last variables' updates */\n            ReadStatus = EE_ReadVariable(VirtAddVarTab[VarIdx], &DataVar);\n            /* In case variable corresponding to the virtual address was found */\n            if (ReadStatus != 0x1)\n            {\n              /* Transfer the variable to the Page0 */\n              EepromStatus = EE_VerifyPageFullWriteVariable(VirtAddVarTab[VarIdx], DataVar);\n              /* If program operation was failed, a Flash error code is returned */\n              if (EepromStatus != HAL_OK)\n              {\n                return EepromStatus;\n              }\n            }\n          }\n        }\n        /* Mark Page0 as valid */\n        FlashStatus = HAL_FLASH_Program(TYPEPROGRAM_HALFWORD, PAGE0_BASE_ADDRESS, VALID_PAGE);\n        /* If program operation was failed, a Flash error code is returned */\n        if (FlashStatus != HAL_OK)\n        {\n          return FlashStatus;\n        }\n        pEraseInit.Sector = PAGE1_ID;\n        pEraseInit.NbSectors = 1;\n        pEraseInit.VoltageRange = VOLTAGE_RANGE;\n        /* Erase Page1 */\n        if(!EE_VerifyPageFullyErased(PAGE1_BASE_ADDRESS))\n        {\n          FlashStatus = HAL_FLASHEx_Erase(&pEraseInit, &SectorError);\n          /* If erase operation was failed, a Flash error code is returned */\n          if (FlashStatus != HAL_OK)\n          {\n            return FlashStatus;\n          }\n        }\n      }\n      else if (PageStatus1 == ERASED) /* Page0 receive, Page1 erased */\n      {\n        pEraseInit.Sector = PAGE1_ID;\n        pEraseInit.NbSectors = 1;\n        pEraseInit.VoltageRange = VOLTAGE_RANGE;\n        /* Erase Page1 */\n        if(!EE_VerifyPageFullyErased(PAGE1_BASE_ADDRESS))\n        {\n          FlashStatus = HAL_FLASHEx_Erase(&pEraseInit, &SectorError);\n          /* If erase operation was failed, a Flash error code is returned */\n          if (FlashStatus != HAL_OK)\n          {\n            return FlashStatus;\n          }\n        }\n        /* Mark Page0 as valid */\n        FlashStatus = HAL_FLASH_Program(TYPEPROGRAM_HALFWORD, PAGE0_BASE_ADDRESS, VALID_PAGE);\n        /* If program operation was failed, a Flash error code is returned */\n        if (FlashStatus != HAL_OK)\n        {\n          return FlashStatus;\n        }\n      }\n      else /* Invalid state -> format eeprom */\n      {\n        /* Erase both Page0 and Page1 and set Page0 as valid page */\n        FlashStatus = EE_Format();\n        /* If erase/program operation was failed, a Flash error code is returned */\n        if (FlashStatus != HAL_OK)\n        {\n          return FlashStatus;\n        }\n      }\n      break;\n\n    case VALID_PAGE:\n      if (PageStatus1 == VALID_PAGE) /* Invalid state -> format eeprom */\n      {\n        /* Erase both Page0 and Page1 and set Page0 as valid page */\n        FlashStatus = EE_Format();\n        /* If erase/program operation was failed, a Flash error code is returned */\n        if (FlashStatus != HAL_OK)\n        {\n          return FlashStatus;\n        }\n      }\n      else if (PageStatus1 == ERASED) /* Page0 valid, Page1 erased */\n      {\n        pEraseInit.Sector = PAGE1_ID;\n        pEraseInit.NbSectors = 1;\n        pEraseInit.VoltageRange = VOLTAGE_RANGE;\n        /* Erase Page1 */\n        if(!EE_VerifyPageFullyErased(PAGE1_BASE_ADDRESS))\n        {\n          FlashStatus = HAL_FLASHEx_Erase(&pEraseInit, &SectorError);\n          /* If erase operation was failed, a Flash error code is returned */\n          if (FlashStatus != HAL_OK)\n          {\n            return FlashStatus;\n          }\n        }\n      }\n      else /* Page0 valid, Page1 receive */\n      {\n        /* Transfer data from Page0 to Page1 */\n        for (VarIdx = 0; VarIdx < NB_OF_VAR; VarIdx++)\n        {\n          if ((*(__IO uint16_t*)(PAGE1_BASE_ADDRESS + 6)) == VirtAddVarTab[VarIdx])\n          {\n            x = VarIdx;\n          }\n          if (VarIdx != x)\n          {\n            /* Read the last variables' updates */\n            ReadStatus = EE_ReadVariable(VirtAddVarTab[VarIdx], &DataVar);\n            /* In case variable corresponding to the virtual address was found */\n            if (ReadStatus != 0x1)\n            {\n              /* Transfer the variable to the Page1 */\n              EepromStatus = EE_VerifyPageFullWriteVariable(VirtAddVarTab[VarIdx], DataVar);\n              /* If program operation was failed, a Flash error code is returned */\n              if (EepromStatus != HAL_OK)\n              {\n                return EepromStatus;\n              }\n            }\n          }\n        }\n        /* Mark Page1 as valid */\n        FlashStatus = HAL_FLASH_Program(TYPEPROGRAM_HALFWORD, PAGE1_BASE_ADDRESS, VALID_PAGE);\n        /* If program operation was failed, a Flash error code is returned */\n        if (FlashStatus != HAL_OK)\n        {\n          return FlashStatus;\n        }\n        pEraseInit.Sector = PAGE0_ID;\n        pEraseInit.NbSectors = 1;\n        pEraseInit.VoltageRange = VOLTAGE_RANGE;\n        /* Erase Page0 */\n        if(!EE_VerifyPageFullyErased(PAGE0_BASE_ADDRESS))\n        {\n          FlashStatus = HAL_FLASHEx_Erase(&pEraseInit, &SectorError);\n          /* If erase operation was failed, a Flash error code is returned */\n          if (FlashStatus != HAL_OK)\n          {\n            return FlashStatus;\n          }\n        }\n      }\n      break;\n\n    default:  /* Any other state -> format eeprom */\n      /* Erase both Page0 and Page1 and set Page0 as valid page */\n      FlashStatus = EE_Format();\n      /* If erase/program operation was failed, a Flash error code is returned */\n      if (FlashStatus != HAL_OK)\n      {\n        return FlashStatus;\n      }\n      break;\n  }\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Verify if specified page is fully erased.\n  * @param  Address: page address\n  *   This parameter can be one of the following values:\n  *     @arg PAGE0_BASE_ADDRESS: Page0 base address\n  *     @arg PAGE1_BASE_ADDRESS: Page1 base address\n  * @retval page fully erased status:\n  *           - 0: if Page not erased\n  *           - 1: if Page erased\n  */\nuint16_t EE_VerifyPageFullyErased(uint32_t Address)\n{\n  uint32_t ReadStatus = 1;\n  uint16_t AddressValue = 0x5555;\n\n  /* Check each active page address starting from end */\n  while (Address <= PAGE0_END_ADDRESS)\n  {\n    /* Get the current location content to be compared with virtual address */\n    AddressValue = (*(__IO uint16_t*)Address);\n\n    /* Compare the read address with the virtual address */\n    if (AddressValue != ERASED)\n    {\n\n      /* In case variable value is read, reset ReadStatus flag */\n      ReadStatus = 0;\n\n      break;\n    }\n    /* Next address location */\n    Address = Address + 4;\n  }\n\n  /* Return ReadStatus value: (0: Page not erased, 1: Sector erased) */\n  return ReadStatus;\n}\n\n/**\n  * @brief  Returns the last stored variable data, if found, which correspond to\n  *   the passed virtual address\n  * @param  VirtAddress: Variable virtual address\n  * @param  Data: Global variable contains the read variable value\n  * @retval Success or error status:\n  *           - 0: if variable was found\n  *           - 1: if the variable was not found\n  *           - NO_VALID_PAGE: if no valid page was found.\n  */\nuint16_t EE_ReadVariable(uint16_t VirtAddress, uint16_t* Data)\n{\n  uint16_t ValidPage = PAGE0;\n  uint16_t AddressValue = 0x5555, ReadStatus = 1;\n  uint32_t Address = EEPROM_START_ADDRESS, PageStartAddress = EEPROM_START_ADDRESS;\n\n  /* Get active Page for read operation */\n  ValidPage = EE_FindValidPage(READ_FROM_VALID_PAGE);\n\n  /* Check if there is no valid page */\n  if (ValidPage == NO_VALID_PAGE)\n  {\n    return  NO_VALID_PAGE;\n  }\n\n  /* Get the valid Page start Address */\n  PageStartAddress = (uint32_t)(EEPROM_START_ADDRESS + (uint32_t)(ValidPage * PAGE_SIZE));\n\n  /* Get the valid Page end Address */\n  Address = (uint32_t)((EEPROM_START_ADDRESS - 2) + (uint32_t)((1 + ValidPage) * PAGE_SIZE));\n\n  /* Check each active page address starting from end */\n  while (Address > (PageStartAddress + 2))\n  {\n    /* Get the current location content to be compared with virtual address */\n    AddressValue = (*(__IO uint16_t*)Address);\n\n    /* Compare the read address with the virtual address */\n    if (AddressValue == VirtAddress)\n    {\n      /* Get content of Address-2 which is variable value */\n      *Data = (*(__IO uint16_t*)(Address - 2));\n\n      /* In case variable value is read, reset ReadStatus flag */\n      ReadStatus = 0;\n\n      break;\n    }\n    else\n    {\n      /* Next address location */\n      Address = Address - 4;\n    }\n  }\n\n  /* Return ReadStatus value: (0: variable exist, 1: variable doesn't exist) */\n  return ReadStatus;\n}\n\n/**\n  * @brief  Writes/upadtes variable data in EEPROM.\n  * @param  VirtAddress: Variable virtual address\n  * @param  Data: 16 bit data to be written\n  * @retval Success or error status:\n  *           - FLASH_COMPLETE: on success\n  *           - PAGE_FULL: if valid page is full\n  *           - NO_VALID_PAGE: if no valid page was found\n  *           - Flash error code: on write Flash error\n  */\nuint16_t EE_WriteVariable(uint16_t VirtAddress, uint16_t Data)\n{\n  uint16_t Status = 0;\n\n  /* Write the variable virtual address and value in the EEPROM */\n  Status = EE_VerifyPageFullWriteVariable(VirtAddress, Data);\n\n  /* In case the EEPROM active page is full */\n  if (Status == PAGE_FULL)\n  {\n    /* Perform Page transfer */\n    Status = EE_PageTransfer(VirtAddress, Data);\n  }\n\n  /* Return last operation status */\n  return Status;\n}\n\n/**\n  * @brief  Erases PAGE and PAGE1 and writes VALID_PAGE header to PAGE\n  * @param  None\n  * @retval Status of the last operation (Flash write or erase) done during\n  *         EEPROM formating\n  */\nstatic HAL_StatusTypeDef EE_Format(void)\n{\n  HAL_StatusTypeDef FlashStatus = HAL_OK;\n  uint32_t SectorError = 0;\n  FLASH_EraseInitTypeDef pEraseInit;\n\n  pEraseInit.TypeErase = FLASH_TYPEERASE_SECTORS;\n  pEraseInit.Sector = PAGE0_ID;\n  pEraseInit.NbSectors = 1;\n  pEraseInit.VoltageRange = VOLTAGE_RANGE;\n  /* Erase Page0 */\n  if(!EE_VerifyPageFullyErased(PAGE0_BASE_ADDRESS))\n  {\n    FlashStatus = HAL_FLASHEx_Erase(&pEraseInit, &SectorError);\n    /* If erase operation was failed, a Flash error code is returned */\n    if (FlashStatus != HAL_OK)\n    {\n      return FlashStatus;\n    }\n  }\n  /* Set Page0 as valid page: Write VALID_PAGE at Page0 base address */\n  FlashStatus = HAL_FLASH_Program(TYPEPROGRAM_HALFWORD, PAGE0_BASE_ADDRESS, VALID_PAGE);\n  /* If program operation was failed, a Flash error code is returned */\n  if (FlashStatus != HAL_OK)\n  {\n    return FlashStatus;\n  }\n\n  pEraseInit.Sector = PAGE1_ID;\n  /* Erase Page1 */\n  if(!EE_VerifyPageFullyErased(PAGE1_BASE_ADDRESS))\n  {\n    FlashStatus = HAL_FLASHEx_Erase(&pEraseInit, &SectorError);\n    /* If erase operation was failed, a Flash error code is returned */\n    if (FlashStatus != HAL_OK)\n    {\n      return FlashStatus;\n    }\n  }\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Find valid Page for write or read operation\n  * @param  Operation: operation to achieve on the valid page.\n  *   This parameter can be one of the following values:\n  *     @arg READ_FROM_VALID_PAGE: read operation from valid page\n  *     @arg WRITE_IN_VALID_PAGE: write operation from valid page\n  * @retval Valid page number (PAGE or PAGE1) or NO_VALID_PAGE in case\n  *   of no valid page was found\n  */\nstatic uint16_t EE_FindValidPage(uint8_t Operation)\n{\n  uint16_t PageStatus0 = 6, PageStatus1 = 6;\n\n  /* Get Page0 actual status */\n  PageStatus0 = (*(__IO uint16_t*)PAGE0_BASE_ADDRESS);\n\n  /* Get Page1 actual status */\n  PageStatus1 = (*(__IO uint16_t*)PAGE1_BASE_ADDRESS);\n\n  /* Write or read operation */\n  switch (Operation)\n  {\n    case WRITE_IN_VALID_PAGE:   /* ---- Write operation ---- */\n      if (PageStatus1 == VALID_PAGE)\n      {\n        /* Page0 receiving data */\n        if (PageStatus0 == RECEIVE_DATA)\n        {\n          return PAGE0;         /* Page0 valid */\n        }\n        else\n        {\n          return PAGE1;         /* Page1 valid */\n        }\n      }\n      else if (PageStatus0 == VALID_PAGE)\n      {\n        /* Page1 receiving data */\n        if (PageStatus1 == RECEIVE_DATA)\n        {\n          return PAGE1;         /* Page1 valid */\n        }\n        else\n        {\n          return PAGE0;         /* Page0 valid */\n        }\n      }\n      else\n      {\n        return NO_VALID_PAGE;   /* No valid Page */\n      }\n\n    case READ_FROM_VALID_PAGE:  /* ---- Read operation ---- */\n      if (PageStatus0 == VALID_PAGE)\n      {\n        return PAGE0;           /* Page0 valid */\n      }\n      else if (PageStatus1 == VALID_PAGE)\n      {\n        return PAGE1;           /* Page1 valid */\n      }\n      else\n      {\n        return NO_VALID_PAGE ;  /* No valid Page */\n      }\n\n    default:\n      return PAGE0;             /* Page0 valid */\n  }\n}\n\n/**\n  * @brief  Verify if active page is full and Writes variable in EEPROM.\n  * @param  VirtAddress: 16 bit virtual address of the variable\n  * @param  Data: 16 bit data to be written as variable value\n  * @retval Success or error status:\n  *           - FLASH_COMPLETE: on success\n  *           - PAGE_FULL: if valid page is full\n  *           - NO_VALID_PAGE: if no valid page was found\n  *           - Flash error code: on write Flash error\n  */\nstatic uint16_t EE_VerifyPageFullWriteVariable(uint16_t VirtAddress, uint16_t Data)\n{\n  HAL_StatusTypeDef FlashStatus = HAL_OK;\n  uint16_t ValidPage = PAGE0;\n  uint32_t Address = EEPROM_START_ADDRESS, PageEndAddress = EEPROM_START_ADDRESS+PAGE_SIZE;\n\n  /* Get valid Page for write operation */\n  ValidPage = EE_FindValidPage(WRITE_IN_VALID_PAGE);\n\n  /* Check if there is no valid page */\n  if (ValidPage == NO_VALID_PAGE)\n  {\n    return  NO_VALID_PAGE;\n  }\n\n  /* Get the valid Page start Address */\n  Address = (uint32_t)(EEPROM_START_ADDRESS + (uint32_t)(ValidPage * PAGE_SIZE));\n\n  /* Get the valid Page end Address */\n  PageEndAddress = (uint32_t)((EEPROM_START_ADDRESS - 1) + (uint32_t)((ValidPage + 1) * PAGE_SIZE));\n\n  /* Check each active page address starting from begining */\n  while (Address < PageEndAddress)\n  {\n    /* Verify if Address and Address+2 contents are 0xFFFFFFFF */\n    if ((*(__IO uint32_t*)Address) == 0xFFFFFFFF)\n    {\n      /* Set variable data */\n      FlashStatus = HAL_FLASH_Program(TYPEPROGRAM_HALFWORD, Address, Data);\n      /* If program operation was failed, a Flash error code is returned */\n      if (FlashStatus != HAL_OK)\n      {\n        return FlashStatus;\n      }\n      /* Set variable virtual address */\n      FlashStatus = HAL_FLASH_Program(TYPEPROGRAM_HALFWORD, Address + 2, VirtAddress);\n      /* Return program operation status */\n      return FlashStatus;\n    }\n    else\n    {\n      /* Next address location */\n      Address = Address + 4;\n    }\n  }\n\n  /* Return PAGE_FULL in case the valid page is full */\n  return PAGE_FULL;\n}\n\n/**\n  * @brief  Transfers last updated variables data from the full Page to\n  *   an empty one.\n  * @param  VirtAddress: 16 bit virtual address of the variable\n  * @param  Data: 16 bit data to be written as variable value\n  * @retval Success or error status:\n  *           - FLASH_COMPLETE: on success\n  *           - PAGE_FULL: if valid page is full\n  *           - NO_VALID_PAGE: if no valid page was found\n  *           - Flash error code: on write Flash error\n  */\nstatic uint16_t EE_PageTransfer(uint16_t VirtAddress, uint16_t Data)\n{\n  HAL_StatusTypeDef FlashStatus = HAL_OK;\n  uint32_t NewPageAddress = EEPROM_START_ADDRESS;\n  uint16_t OldPageId=0;\n  uint16_t ValidPage = PAGE0, VarIdx = 0;\n  uint16_t EepromStatus = 0, ReadStatus = 0;\n  uint32_t SectorError = 0;\n  FLASH_EraseInitTypeDef pEraseInit;\n\n  /* Get active Page for read operation */\n  ValidPage = EE_FindValidPage(READ_FROM_VALID_PAGE);\n\n  if (ValidPage == PAGE1)       /* Page1 valid */\n  {\n    /* New page address where variable will be moved to */\n    NewPageAddress = PAGE0_BASE_ADDRESS;\n\n    /* Old page ID where variable will be taken from */\n    OldPageId = PAGE1_ID;\n  }\n  else if (ValidPage == PAGE0)  /* Page0 valid */\n  {\n    /* New page address  where variable will be moved to */\n    NewPageAddress = PAGE1_BASE_ADDRESS;\n\n    /* Old page ID where variable will be taken from */\n    OldPageId = PAGE0_ID;\n  }\n  else\n  {\n    return NO_VALID_PAGE;       /* No valid Page */\n  }\n\n  /* Set the new Page status to RECEIVE_DATA status */\n  FlashStatus = HAL_FLASH_Program(TYPEPROGRAM_HALFWORD, NewPageAddress, RECEIVE_DATA);\n  /* If program operation was failed, a Flash error code is returned */\n  if (FlashStatus != HAL_OK)\n  {\n    return FlashStatus;\n  }\n\n  /* Write the variable passed as parameter in the new active page */\n  EepromStatus = EE_VerifyPageFullWriteVariable(VirtAddress, Data);\n  /* If program operation was failed, a Flash error code is returned */\n  if (EepromStatus != HAL_OK)\n  {\n    return EepromStatus;\n  }\n\n  /* Transfer process: transfer variables from old to the new active page */\n  for (VarIdx = 0; VarIdx < NB_OF_VAR; VarIdx++)\n  {\n    if (VirtAddVarTab[VarIdx] != VirtAddress)  /* Check each variable except the one passed as parameter */\n    {\n      /* Read the other last variable updates */\n      ReadStatus = EE_ReadVariable(VirtAddVarTab[VarIdx], &DataVar);\n      /* In case variable corresponding to the virtual address was found */\n      if (ReadStatus != 0x1)\n      {\n        /* Transfer the variable to the new active page */\n        EepromStatus = EE_VerifyPageFullWriteVariable(VirtAddVarTab[VarIdx], DataVar);\n        /* If program operation was failed, a Flash error code is returned */\n        if (EepromStatus != HAL_OK)\n        {\n          return EepromStatus;\n        }\n      }\n    }\n  }\n\n  pEraseInit.TypeErase = TYPEERASE_SECTORS;\n  pEraseInit.Sector = OldPageId;\n  pEraseInit.NbSectors = 1;\n  pEraseInit.VoltageRange = VOLTAGE_RANGE;\n\n  /* Erase the old Page: Set old Page status to ERASED status */\n  FlashStatus = HAL_FLASHEx_Erase(&pEraseInit, &SectorError);\n  /* If erase operation was failed, a Flash error code is returned */\n  if (FlashStatus != HAL_OK)\n  {\n    return FlashStatus;\n  }\n\n  /* Set new Page status to VALID_PAGE status */\n  FlashStatus = HAL_FLASH_Program(TYPEPROGRAM_HALFWORD, NewPageAddress, VALID_PAGE);\n  /* If program operation was failed, a Flash error code is returned */\n  if (FlashStatus != HAL_OK)\n  {\n    return FlashStatus;\n  }\n\n  /* Return last operation flash status */\n  return FlashStatus;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/drv_eeprom.h",
    "content": "/*\n *  drv_eeprom.h\n *\n *  Created on: 2016. 10.06.\n *      Author: Baram, PBHP\n */\n\n#ifndef DRV_EEPROM_H\n#define DRV_EEPROM_H\n\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n\n#include \"def.h\"\n#include \"bsp.h\"\n\n\n\n\n\n\n\n\nint drv_eeprom_init();\n\nuint8_t  drv_eeprom_read_byte(int addr);\nvoid     drv_eeprom_write_byte(int index, uint8_t data_in);\nuint16_t drv_eeprom_get_length(void);\n\n\n#ifdef __cplusplus\n}\n#endif\n\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/drv_exti.c",
    "content": "/*\r\n *  drv_exti.c\r\n *\r\n *  Created on: 2016. 7. 13.\r\n *      Author: Baram, PBHP\r\n */\r\n\r\n#include \"drv_exti.h\"\r\n#include \"variant.h\"\r\n\r\n\r\n\r\ntypedef struct\r\n{\r\n  uint8_t  exti_enable;\r\n  uint16_t pin_channel;\r\n  uint16_t pin_number;\r\n  void (*exti_callback)(void);\r\n} exti_data_t;\r\n\r\n\r\nvolatile exti_data_t exti_data[EXTI_COUNT];\r\n\r\n\r\nint drv_exti_init()\r\n{\r\n  uint32_t i;\r\n\r\n  for( i=0; i<EXTI_COUNT; i++ )\r\n  {\r\n    exti_data[i].exti_enable   = 0;\r\n    exti_data[i].exti_callback = NULL;\r\n    exti_data[i].pin_channel   = 0;\r\n  }\r\n\r\n  i = 0;\r\n  while(1)\r\n  {\r\n    if( g_Pin2PortMapArray[i].GPIOx_Port == NULL ) break;\r\n\r\n    if(g_Pin2PortMapArray[i].extiChannel != NO_EXTI )\r\n    {\r\n      exti_data[g_Pin2PortMapArray[i].extiChannel].pin_number = i;\r\n    }\r\n\r\n    i++;\r\n  }\r\n  return 0;\r\n}\r\n\r\n\r\nvoid drv_exti_attach( uint32_t int_num, void (*callback)(void), uint32_t mode )\r\n{\r\n  uint32_t ulPin;\r\n  GPIO_InitTypeDef   GPIO_InitStructure;\r\n\r\n\r\n  if( int_num >= EXTI_COUNT ) return;\r\n\r\n  ulPin = exti_data[int_num].pin_number;\r\n\r\n  if( g_Pin2PortMapArray[ulPin].extiChannel == NO_EXTI ) return;\r\n\r\n  exti_data[ g_Pin2PortMapArray[ulPin].extiChannel ].exti_enable   = 1;\r\n  exti_data[ g_Pin2PortMapArray[ulPin].extiChannel ].pin_channel   = g_Pin2PortMapArray[ulPin].Pin_abstraction;\r\n  exti_data[ g_Pin2PortMapArray[ulPin].extiChannel ].exti_callback = callback;\r\n\r\n\r\n  switch( mode )\r\n  {\r\n    case CHANGE:\r\n      GPIO_InitStructure.Mode = GPIO_MODE_IT_RISING_FALLING;\r\n      break;\r\n\r\n    case FALLING:\r\n      GPIO_InitStructure.Mode = GPIO_MODE_IT_FALLING;\r\n      break;\r\n\r\n    case RISING:\r\n      GPIO_InitStructure.Mode = GPIO_MODE_IT_RISING;\r\n      break;\r\n\r\n    default:\r\n      GPIO_InitStructure.Mode = GPIO_MODE_IT_RISING_FALLING;\r\n      return;\r\n  }\r\n\r\n\r\n  //GPIO_InitStructure.Pull = GPIO_NOPULL;\r\n  GPIO_InitStructure.Pin  = g_Pin2PortMapArray[ulPin].Pin_abstraction;\r\n  HAL_GPIO_Init(g_Pin2PortMapArray[ulPin].GPIOx_Port, &GPIO_InitStructure);\r\n\r\n\r\n\r\n  if( g_Pin2PortMapArray[ulPin].Pin_abstraction == GPIO_PIN_0 )\r\n  {\r\n    HAL_NVIC_SetPriority(EXTI0_IRQn, 2, 0);\r\n    HAL_NVIC_EnableIRQ(EXTI0_IRQn);\r\n  }\r\n\r\n  if( g_Pin2PortMapArray[ulPin].Pin_abstraction == GPIO_PIN_1 )\r\n  {\r\n    HAL_NVIC_SetPriority(EXTI1_IRQn, 2, 0);\r\n    HAL_NVIC_EnableIRQ(EXTI1_IRQn);\r\n  }\r\n\r\n  if( g_Pin2PortMapArray[ulPin].Pin_abstraction == GPIO_PIN_2 )\r\n  {\r\n    HAL_NVIC_SetPriority(EXTI2_IRQn, 2, 0);\r\n    HAL_NVIC_EnableIRQ(EXTI2_IRQn);\r\n  }\r\n\r\n  if( g_Pin2PortMapArray[ulPin].Pin_abstraction == GPIO_PIN_3 )\r\n  {\r\n    HAL_NVIC_SetPriority(EXTI3_IRQn, 2, 0);\r\n    HAL_NVIC_EnableIRQ(EXTI3_IRQn);\r\n  }\r\n\r\n  if( g_Pin2PortMapArray[ulPin].Pin_abstraction == GPIO_PIN_4 )\r\n  {\r\n    HAL_NVIC_SetPriority(EXTI4_IRQn, 2, 0);\r\n    HAL_NVIC_EnableIRQ(EXTI4_IRQn);\r\n  }\r\n\r\n  if(    g_Pin2PortMapArray[ulPin].Pin_abstraction == GPIO_PIN_5\r\n      || g_Pin2PortMapArray[ulPin].Pin_abstraction == GPIO_PIN_6\r\n      || g_Pin2PortMapArray[ulPin].Pin_abstraction == GPIO_PIN_7\r\n      || g_Pin2PortMapArray[ulPin].Pin_abstraction == GPIO_PIN_8\r\n      || g_Pin2PortMapArray[ulPin].Pin_abstraction == GPIO_PIN_9 )\r\n  {\r\n    HAL_NVIC_SetPriority(EXTI9_5_IRQn, 2, 0);\r\n    HAL_NVIC_EnableIRQ(EXTI9_5_IRQn);\r\n  }\r\n\r\n  if(    g_Pin2PortMapArray[ulPin].Pin_abstraction == GPIO_PIN_10\r\n      || g_Pin2PortMapArray[ulPin].Pin_abstraction == GPIO_PIN_11\r\n      || g_Pin2PortMapArray[ulPin].Pin_abstraction == GPIO_PIN_12\r\n      || g_Pin2PortMapArray[ulPin].Pin_abstraction == GPIO_PIN_13\r\n      || g_Pin2PortMapArray[ulPin].Pin_abstraction == GPIO_PIN_14\r\n      || g_Pin2PortMapArray[ulPin].Pin_abstraction == GPIO_PIN_15 )\r\n  {\r\n    HAL_NVIC_SetPriority(EXTI15_10_IRQn, 2, 0);\r\n    HAL_NVIC_EnableIRQ(EXTI15_10_IRQn);\r\n  }\r\n}\r\n\r\n\r\nvoid drv_exti_detach( uint32_t int_num )\r\n{\r\n  uint32_t i;\r\n  uint32_t ulPin;\r\n\r\n\r\n  if( int_num >= EXTI_COUNT ) return;\r\n\r\n  ulPin = exti_data[int_num].pin_number;\r\n\r\n\r\n  if( g_Pin2PortMapArray[ulPin].extiChannel == NO_EXTI ) return;\r\n\r\n  exti_data[ g_Pin2PortMapArray[ulPin].extiChannel ].exti_enable   = 0;\r\n  exti_data[ g_Pin2PortMapArray[ulPin].extiChannel ].exti_callback = NULL;\r\n\r\n\r\n  if( g_Pin2PortMapArray[ulPin].Pin_abstraction == GPIO_PIN_0 )\r\n  {\r\n    HAL_NVIC_DisableIRQ(EXTI0_IRQn);\r\n  }\r\n\r\n  if( g_Pin2PortMapArray[ulPin].Pin_abstraction == GPIO_PIN_1 )\r\n  {\r\n    HAL_NVIC_DisableIRQ(EXTI1_IRQn);\r\n  }\r\n\r\n  if( g_Pin2PortMapArray[ulPin].Pin_abstraction == GPIO_PIN_2 )\r\n  {\r\n    HAL_NVIC_DisableIRQ(EXTI2_IRQn);\r\n  }\r\n\r\n  if( g_Pin2PortMapArray[ulPin].Pin_abstraction == GPIO_PIN_3 )\r\n  {\r\n    HAL_NVIC_DisableIRQ(EXTI3_IRQn);\r\n  }\r\n\r\n  if( g_Pin2PortMapArray[ulPin].Pin_abstraction == GPIO_PIN_4 )\r\n  {\r\n    HAL_NVIC_DisableIRQ(EXTI4_IRQn);\r\n  }\r\n\r\n  for( i=0; i<EXTI_COUNT; i++ )\r\n  {\r\n    if( exti_data[i].pin_channel == GPIO_PIN_5 && exti_data[i].exti_enable == 1 ) break;\r\n    if( exti_data[i].pin_channel == GPIO_PIN_6 && exti_data[i].exti_enable == 1 ) break;\r\n    if( exti_data[i].pin_channel == GPIO_PIN_7 && exti_data[i].exti_enable == 1 ) break;\r\n    if( exti_data[i].pin_channel == GPIO_PIN_8 && exti_data[i].exti_enable == 1 ) break;\r\n    if( exti_data[i].pin_channel == GPIO_PIN_9 && exti_data[i].exti_enable == 1 ) break;\r\n  }\r\n  if( i == EXTI_COUNT )\r\n  {\r\n    HAL_NVIC_DisableIRQ(EXTI9_5_IRQn);\r\n  }\r\n\r\n\r\n  for( i=0; i<EXTI_COUNT; i++ )\r\n  {\r\n    if( exti_data[i].pin_channel == GPIO_PIN_10 && exti_data[i].exti_enable == 1 ) break;\r\n    if( exti_data[i].pin_channel == GPIO_PIN_11 && exti_data[i].exti_enable == 1 ) break;\r\n    if( exti_data[i].pin_channel == GPIO_PIN_12 && exti_data[i].exti_enable == 1 ) break;\r\n    if( exti_data[i].pin_channel == GPIO_PIN_13 && exti_data[i].exti_enable == 1 ) break;\r\n    if( exti_data[i].pin_channel == GPIO_PIN_14 && exti_data[i].exti_enable == 1 ) break;\r\n    if( exti_data[i].pin_channel == GPIO_PIN_15 && exti_data[i].exti_enable == 1 ) break;\r\n  }\r\n  if( i == EXTI_COUNT )\r\n  {\r\n    HAL_NVIC_DisableIRQ(EXTI15_10_IRQn);\r\n  }\r\n}\r\n\r\n\r\n\r\nvoid HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)\r\n{\r\n  uint32_t i;\r\n\r\n  for( i=0; i<EXTI_COUNT; i++ )\r\n  {\r\n    if(GPIO_Pin == exti_data[i].pin_channel)\r\n    {\r\n      if(exti_data[i].exti_callback != NULL )\r\n      {\r\n        (*exti_data[i].exti_callback)();\r\n      }\r\n    }\r\n  }\r\n}\r\n\r\n\r\nvoid EXTI0_IRQHandler(void)\r\n{\r\n  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_0);\r\n}\r\n\r\n\r\nvoid EXTI1_IRQHandler(void)\r\n{\r\n  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_1);\r\n}\r\n\r\n\r\nvoid EXTI2_IRQHandler(void)\r\n{\r\n  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_2);\r\n}\r\n\r\n\r\nvoid EXTI3_IRQHandler(void)\r\n{\r\n  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_3);\r\n}\r\n\r\n\r\nvoid EXTI4_IRQHandler(void)\r\n{\r\n  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_4);\r\n}\r\n\r\n\r\nvoid EXTI9_5_IRQHandler(void)\r\n{\r\n  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_5);\r\n  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_6);\r\n  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_7);\r\n  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8);\r\n  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9);\r\n}\r\n\r\nvoid EXTI15_10_IRQHandler(void)\r\n{\r\n  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10);\r\n  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11);\r\n  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12);\r\n  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13);\r\n  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_14);\r\n  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15);\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/drv_exti.h",
    "content": "/*\n *  drv_exti.h\n *\n *  Created on: 2016. 7.13.\n *      Author: Baram, PBHP\n */\n\n#ifndef DRV_EXTI_H\n#define DRV_EXTI_H\n\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n\n#include \"def.h\"\n#include \"bsp.h\"\n\n\n\n\n\n\n\n\nint drv_exti_init();\n\nvoid drv_exti_attach( uint32_t ulPin, void (*callback)(void), uint32_t mode );\nvoid drv_exti_detach( uint32_t ulPin );\n\n\n#ifdef __cplusplus\n}\n#endif\n\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/drv_i2c.c",
    "content": "/*\n *  drv_spi.c\n *\n *  Created on: 2016. 7. 13.\n *      Author: Baram, PBHP\n */\n\n#include \"drv_i2c.h\"\n#include \"variant.h\"\n\n\nI2C_HandleTypeDef drv_i2c_handles[DRV_I2C_CNT];     // If we are doing hardware I2C\nI2C_TypeDef *i2c_instance[DRV_I2C_CNT] = {I2C1, I2C2};\n\nint drv_i2c_init()\n{\n  for (int i=0; i < DRV_I2C_CNT; i++) \n  {\n    drv_i2c_handles[i].Instance = i2c_instance[i];\n  }\n  return 0;\n}\n\n\nvoid HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)\n{\n  GPIO_InitTypeDef  GPIO_InitStruct;\n  RCC_PeriphCLKInitTypeDef  RCC_PeriphCLKInitStruct;\n\n\n  if( hi2c->Instance == I2C1 )\n  {\n    /*##-1- Configure the I2C clock source. The clock is derived from the SYSCLK #*/\n    RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2C1;\n    RCC_PeriphCLKInitStruct.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;\n    HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct);\n\n    /* Enable I2Cx clock */\n    __HAL_RCC_I2C1_CLK_ENABLE();\n\n    /*##-3- Configure peripheral GPIO ##########################################*/\n    /* I2C SCL GPIO pin configuration  */\n    GPIO_InitStruct.Pin       = GPIO_PIN_8;\n    GPIO_InitStruct.Mode      = GPIO_MODE_AF_OD;\n    GPIO_InitStruct.Pull      = GPIO_PULLUP;\n    GPIO_InitStruct.Speed     = GPIO_SPEED_HIGH;\n    GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;\n    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\n\n    /* I2C SDA GPIO pin configuration  */\n    GPIO_InitStruct.Pin       = GPIO_PIN_7;\n    GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;\n    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\n\n    /* Peripheral interrupt init */\n    HAL_NVIC_SetPriority(I2C1_EV_IRQn, 8, 0);\n    HAL_NVIC_EnableIRQ  (I2C1_EV_IRQn);\n    HAL_NVIC_SetPriority(I2C1_ER_IRQn, 8, 0);\n    HAL_NVIC_EnableIRQ  (I2C1_ER_IRQn);\n\n  }\n  if( hi2c->Instance == I2C2 )\n  {\n    /*##-1- Configure the I2C clock source. The clock is derived from the SYSCLK #*/\n    RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2C2;\n    RCC_PeriphCLKInitStruct.I2c2ClockSelection = RCC_I2C2CLKSOURCE_PCLK1;\n    HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct);\n\n    /* Enable I2Cx clock */\n    __HAL_RCC_I2C2_CLK_ENABLE();\n\n    /*##-3- Configure peripheral GPIO ##########################################*/\n    /* I2C SCL GPIO pin configuration  */\n    GPIO_InitStruct.Pin       = GPIO_PIN_10;\n    GPIO_InitStruct.Mode      = GPIO_MODE_AF_OD;\n    GPIO_InitStruct.Pull      = GPIO_PULLUP;\n    GPIO_InitStruct.Speed     = GPIO_SPEED_HIGH;\n    GPIO_InitStruct.Alternate = GPIO_AF4_I2C2;\n    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\n\n    /* I2C SDA GPIO pin configuration  */\n    GPIO_InitStruct.Pin       = GPIO_PIN_11;\n    GPIO_InitStruct.Alternate = GPIO_AF4_I2C2;\n    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\n\n    /* Peripheral interrupt init */\n    HAL_NVIC_SetPriority(I2C2_EV_IRQn, 8, 0);\n    HAL_NVIC_EnableIRQ  (I2C2_EV_IRQn);\n    HAL_NVIC_SetPriority(I2C2_ER_IRQn, 8, 0);\n    HAL_NVIC_EnableIRQ  (I2C2_ER_IRQn);\n  }\n}\n\n/**\n  * @brief I2C MSP De-Initialization\n  *        This function frees the hardware resources used in this example:\n  *          - Disable the Peripheral's clock\n  *          - Revert GPIO, DMA and NVIC configuration to their default state\n  * @param hi2c: I2C handle pointer\n  * @retval None\n  */\nvoid HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)\n{\n  if( hi2c->Instance == I2C1 )\n  {\n    /*##-1- Reset peripherals ##################################################*/\n    __HAL_RCC_I2C1_FORCE_RESET();\n    __HAL_RCC_I2C1_RELEASE_RESET();\n\n    /*##-2- Disable peripherals and GPIO Clocks #################################*/\n    /* Configure I2C SCL as alternate function  */\n    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8);\n    /* Configure I2C SDA as alternate function  */\n    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_7);\n\n    /* Peripheral interrupt Deinit*/\n    HAL_NVIC_DisableIRQ  (I2C1_EV_IRQn);\n    HAL_NVIC_DisableIRQ  (I2C1_ER_IRQn);\n  }\n  if( hi2c->Instance == I2C2 )\n  {\n    /*##-1- Reset peripherals ##################################################*/\n    __HAL_RCC_I2C2_FORCE_RESET();\n    __HAL_RCC_I2C2_RELEASE_RESET();\n\n    /*##-2- Disable peripherals and GPIO Clocks #################################*/\n    /* Configure I2C SCL as alternate function  */\n    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10);\n    /* Configure I2C SDA as alternate function  */\n    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_11);\n\n    /* Peripheral interrupt Deinit*/\n    HAL_NVIC_DisableIRQ  (I2C2_EV_IRQn);\n    HAL_NVIC_DisableIRQ  (I2C2_ER_IRQn);\n  }\n}\n\nvoid I2C1_EV_IRQHandler(void) {\n  HAL_I2C_EV_IRQHandler( &drv_i2c_handles[0]);\n}\n\nvoid I2C2_EV_IRQHandler(void)  {\n  HAL_I2C_EV_IRQHandler( &drv_i2c_handles[1]);\n}\n\nvoid I2C1_ER_IRQHandler(void) {\n  HAL_I2C_ER_IRQHandler( &drv_i2c_handles[0]);\n}\n\nvoid I2C2_ER_IRQHandler(void)  {\n  HAL_I2C_ER_IRQHandler( &drv_i2c_handles[1]);\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/drv_i2c.h",
    "content": "/*\n *  drv_i2c.h\n *\n *  Created on: 2016. 7.13.\n *      Author: Baram, PBHP\n */\n\n#ifndef DRV_I2C_H\n#define DRV_I2C_H\n\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n\n#include \"def.h\"\n#include \"bsp.h\"\n\n\n\n\n#define DRV_I2C_CNT 2\n\nextern I2C_HandleTypeDef drv_i2c_handles[DRV_I2C_CNT];     // If we are doing hardware I2C\n \n\nint drv_i2c_init();\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/drv_micros.c",
    "content": "/*\n *  drv.c\n *\n *  Created on: 2016. 7. 13.\n *      Author: Baram, PBHP\n */\n\n#include \"drv_micros.h\"\n#include \"variant.h\"\n\n\n\n\n\n\nTIM_HandleTypeDef    TimHandle;\n\n\n\n\n\n\nvoid drv_micros_init()\n{\n  uint32_t uwPrescalerValue = 0;\n\n\n  __HAL_RCC_TIM5_CLK_ENABLE();\n\n\n  // Compute the prescaler value to have TIMx counter clock equal to 1Mh\n  uwPrescalerValue = (uint32_t)((SystemCoreClock / 2) / 1000000) - 1;\n\n\n  TimHandle.Instance = TIM5;\n  TimHandle.Init.Period            = 0xFFFFFFFF;\n  TimHandle.Init.Prescaler         = uwPrescalerValue;\n  TimHandle.Init.ClockDivision     = 0;\n  TimHandle.Init.CounterMode       = TIM_COUNTERMODE_UP;\n  TimHandle.Init.RepetitionCounter = 0;\n\n\n  HAL_TIM_Base_Init(&TimHandle);\n  HAL_TIM_Base_Start(&TimHandle);\n}\n\n\nuint32_t drv_micros()\n{\n  return TimHandle.Instance->CNT;\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/drv_micros.h",
    "content": "/*\n *  drv.h\n *\n *  Created on: 2016. 5. 14.\n *      Author: Baram, PBHP\n */\n\n#ifndef DRV_MICROS_H\n#define DRV_MICROS_H\n\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n\n\n#include \"def.h\"\n#include \"bsp.h\"\n\n\nvoid drv_micros_init();\n\nuint32_t drv_micros();\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/drv_pwm.c",
    "content": "/*\n *  drv_pwm.c\n *\n *  Created on: 2016. 7. 14.\n *      Author: Baram, PBHP\n */\n\n#include \"drv_pwm.h\"\n#include \"variant.h\"\n\n\n#define PWM_PERIOD_VALUE  (0xFFFF-1)\n\nTIM_HandleTypeDef         hTIM1;\nTIM_HandleTypeDef         hTIM2;\nTIM_HandleTypeDef         hTIM3;\nTIM_HandleTypeDef         hTIM9;\nTIM_HandleTypeDef         hTIM11;\nTIM_HandleTypeDef         hTIM12;\n\nTIM_OC_InitTypeDef        hOC1;\nTIM_OC_InitTypeDef        hOC2;\nTIM_OC_InitTypeDef        hOC3;\nTIM_OC_InitTypeDef        hOC9;\nTIM_OC_InitTypeDef        hOC11;\nTIM_OC_InitTypeDef        hOC12;\n\n\n\n\nuint32_t pwm_freq[PINS_COUNT];\nbool     pwm_init[PINS_COUNT];\n\nstatic void drv_pwm_HwInit(TIM_HandleTypeDef *htim, uint32_t tim_ch);\n\n\nint drv_pwm_init()\n{\n  uint32_t i;\n\n\n  for( i=0; i<PINS_COUNT; i++ )\n  {\n    pwm_freq[i] = 50000; // 50Khz\n    pwm_init[i] = false;\n  }\n  return 0;\n}\n\n\nstatic long map(long x, long in_min, long in_max, long out_min, long out_max)\n{\n  return (int64_t)(x - in_min) * (int64_t)(out_max - out_min) / (in_max - in_min) + out_min;\n}\n\nvoid drv_pwm_set_freq(uint32_t ulPin, uint32_t freq_data)\n{\n  if(ulPin == BDPIN_GPIO_8)\n  {\n    freq_data = constrain(freq_data, 1, 20000000);  //Increase the maximum frequency constraint for OV7725. (Min 10Mhz)\n    pwm_freq[ulPin] = freq_data;\n  }\n  else\n  {\n    freq_data = constrain(freq_data, 1, 1000000);\n    pwm_freq[ulPin] = freq_data;\n  }\n}\n\n\nuint32_t drv_pwm_get_freq(uint32_t ulPin)\n{\n  return pwm_freq[ulPin];\n}\n\nuint8_t drv_pwm_get_init(uint32_t ulPin)\n{\n  return pwm_init[ulPin];\n}\n\nvoid drv_pwm_release(uint32_t ulPin)\n{\n  pwm_init[ulPin] = false;\n}\n\nuint32_t drv_pwm_get_period(uint32_t ulPin)\n{\n  TIM_HandleTypeDef  *pTIM;\n\n  if( ulPin >= PINS_COUNT )     return 0;\n  if( pwm_init[ulPin] == false ) return 0;\n\n  pTIM = g_Pin2PortMapArray[ulPin].TIMx;\n\n  return (pTIM->Init.Period + 1);\n}\n\n\nvoid drv_pwm_setup(uint32_t ulPin)\n{\n  TIM_HandleTypeDef  *pTIM;\n  TIM_OC_InitTypeDef *pOC;\n  uint32_t tim_ch;\n  uint32_t uwPeriodValue;\n  uint32_t uwPrescalerValue = 1;\n  uint32_t tim_clk;\n  bool is_timer_16bit = true;\n  \n\n  if( ulPin >= PINS_COUNT )     return;\n  if( pwm_init[ulPin] == true ) return;\n\n  pTIM   = g_Pin2PortMapArray[ulPin].TIMx;\n  tim_ch = g_Pin2PortMapArray[ulPin].timerChannel;\n  tim_clk = SystemCoreClock;\n\n  if( pTIM == &hTIM3 )\n  {\n    tim_clk /= 2;\n    pOC = &hOC3;\n    pTIM->Instance = TIM3;\n  }\n  else if( pTIM == &hTIM1 )\n  {\n    pOC = &hOC1;\n    pTIM->Instance = TIM1;\n  }\n  else if( pTIM == &hTIM2 )\n  {\n    is_timer_16bit = false;\n    tim_clk /= 2;\n    pOC = &hOC2;\n    pTIM->Instance = TIM2;\n  }\n  else if( pTIM == &hTIM9 )\n  {\n    pOC = &hOC9;\n    pTIM->Instance = TIM9;\n  }\n  else if( pTIM == &hTIM11 )\n  {\n    pOC = &hOC11;\n    pTIM->Instance = TIM11;\n  }\n  else if( pTIM == &hTIM12 )\n  {\n    tim_clk /= 2;\n    pOC = &hOC12;\n    pTIM->Instance = TIM12;\n  }\n  else\n  {\n    return;\n  }\n\n  uwPeriodValue = (uint32_t) (tim_clk / pwm_freq[ulPin]);\n\n  if(is_timer_16bit == true)\n  {\n    uwPrescalerValue = (uwPeriodValue/0xFFFF) + 1;\n    uwPeriodValue /= uwPrescalerValue;\n  }\n\n  pTIM->Init.Prescaler         = uwPrescalerValue - 1;\n  pTIM->Init.Period            = uwPeriodValue - 1;\n  pTIM->Init.ClockDivision     = TIM_CLOCKDIVISION_DIV1;\n  pTIM->Init.CounterMode       = TIM_COUNTERMODE_UP;\n  pTIM->Init.RepetitionCounter = 0;\n  \n  drv_pwm_HwInit(pTIM, tim_ch);\n  HAL_TIM_PWM_Init(pTIM);\n\n  memset(pOC, 0, sizeof(TIM_OC_InitTypeDef));\n\n  pOC->OCMode       = TIM_OCMODE_PWM1;\n  pOC->OCPolarity   = TIM_OCPOLARITY_HIGH;\n  pOC->OCFastMode   = TIM_OCFAST_DISABLE;\n  pOC->OCNPolarity  = TIM_OCNPOLARITY_HIGH;\n  pOC->OCNIdleState = TIM_OCNIDLESTATE_RESET;\n  pOC->OCIdleState  = TIM_OCIDLESTATE_RESET;\n\n  pOC->Pulse = 0;\n  HAL_TIM_PWM_ConfigChannel(pTIM, pOC, tim_ch);\n  HAL_TIM_PWM_Start(pTIM, tim_ch);\n  pwm_init[ulPin] = true;\n}\n\n\nvoid drv_pwm_set_duty(uint32_t ulPin, uint32_t res, uint32_t ulDuty )\n{\n  TIM_HandleTypeDef  *pTIM;\n  uint32_t tim_ch;\n  uint32_t pulse;\n\n  if( ulPin >= PINS_COUNT )     return;\n  if( pwm_init[ulPin] == false ) return;\n\n  pTIM   = g_Pin2PortMapArray[ulPin].TIMx;\n  tim_ch = g_Pin2PortMapArray[ulPin].timerChannel;\n\n\n  ulDuty = constrain(ulDuty, (uint32_t) 0, (uint32_t) (1<<res)-1);\n  pulse = map( ulDuty, (uint32_t) 0, (uint32_t) (1<<res)-1, (uint32_t) 0, pTIM->Init.Period+1 );\n\n  switch (tim_ch)\n  {\n    case TIM_CHANNEL_1:\n      pTIM->Instance->CCR1 = pulse;\n      break;\n\n    case TIM_CHANNEL_2:\n      pTIM->Instance->CCR2 = pulse;\n      break;\n\n    case TIM_CHANNEL_3:\n      pTIM->Instance->CCR3 = pulse;\n      break;\n\n    case TIM_CHANNEL_4:\n      pTIM->Instance->CCR4 = pulse;\n      break;\n\n    default:\n      break; \n  }  \n}\n\n\nuint32_t drv_pwm_get_pulse(uint32_t ulPin)\n{\n  TIM_HandleTypeDef  *pTIM;\n  uint32_t tim_ch;\n  uint32_t pulse = 0;\n\n  if( ulPin >= PINS_COUNT )      return 0;\n  if( pwm_init[ulPin] == false ) return 0;\n\n  pTIM   = g_Pin2PortMapArray[ulPin].TIMx;\n  tim_ch = g_Pin2PortMapArray[ulPin].timerChannel;\n\n  switch (tim_ch)\n  {\n    case TIM_CHANNEL_1:\n      pulse = pTIM->Instance->CCR1;\n      break;\n\n    case TIM_CHANNEL_2:\n      pulse = pTIM->Instance->CCR2;\n      break;\n\n    case TIM_CHANNEL_3:\n      pulse = pTIM->Instance->CCR3;\n      break;\n\n    case TIM_CHANNEL_4:\n      pulse = pTIM->Instance->CCR4;\n      break;\n\n    default:\n      break; \n  }  \n\n  return pulse;\n}\n\n\nstatic void drv_pwm_HwInit(TIM_HandleTypeDef *htim, uint32_t tim_ch)\n{\n  GPIO_InitTypeDef   GPIO_InitStruct;\n\n  if( htim->Instance == TIM3 )\n  {\n    __HAL_RCC_TIM3_CLK_ENABLE();\n\n    GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;\n    GPIO_InitStruct.Pull      = GPIO_PULLUP;\n    GPIO_InitStruct.Speed     = GPIO_SPEED_LOW;\n    GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;\n    GPIO_InitStruct.Pin       = GPIO_PIN_4;\n    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\n  }\n  if( htim->Instance == TIM1 )\n  {\n      __HAL_RCC_TIM1_CLK_ENABLE();\n      GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;\n      GPIO_InitStruct.Pull      = GPIO_PULLUP;\n      GPIO_InitStruct.Speed     = GPIO_SPEED_LOW;\n      GPIO_InitStruct.Alternate = GPIO_AF1_TIM1;\n    \n    if(tim_ch == TIM_CHANNEL_1)\n    {\n      GPIO_InitStruct.Pin       = GPIO_PIN_8;\n      HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\n    }\n    //For OpenCR-Camera Example OV7725 XCLK PWM configuration\n    if(tim_ch == TIM_CHANNEL_2)\n    {\n      GPIO_InitStruct.Pin       = GPIO_PIN_11;\n      HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);\n    }\n  }\n  if( htim->Instance == TIM2 )\n  {\n    __HAL_RCC_TIM2_CLK_ENABLE();\n\n    GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;\n    GPIO_InitStruct.Pull      = GPIO_PULLUP;\n    GPIO_InitStruct.Speed     = GPIO_SPEED_LOW;\n    GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;\n    GPIO_InitStruct.Pin       = GPIO_PIN_2;\n    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\n  }\n  if( htim->Instance == TIM9 )\n  {\n    __HAL_RCC_TIM9_CLK_ENABLE();\n\n    GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;\n    GPIO_InitStruct.Pull      = GPIO_PULLUP;\n    GPIO_InitStruct.Speed     = GPIO_SPEED_LOW;\n    GPIO_InitStruct.Alternate = GPIO_AF3_TIM9;\n    GPIO_InitStruct.Pin       = GPIO_PIN_3;\n    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\n  }\n  if( htim->Instance == TIM11 )\n  {\n    __HAL_RCC_TIM11_CLK_ENABLE();\n\n    GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;\n    GPIO_InitStruct.Pull      = GPIO_PULLUP;\n    GPIO_InitStruct.Speed     = GPIO_SPEED_LOW;\n    GPIO_InitStruct.Alternate = GPIO_AF3_TIM11;\n    GPIO_InitStruct.Pin       = GPIO_PIN_9;\n    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\n  }\n  if( htim->Instance == TIM12 )\n  {\n    __HAL_RCC_TIM12_CLK_ENABLE();\n\n    GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;\n    GPIO_InitStruct.Pull      = GPIO_PULLUP;\n    GPIO_InitStruct.Speed     = GPIO_SPEED_LOW;\n    GPIO_InitStruct.Alternate = GPIO_AF9_TIM12;\n    GPIO_InitStruct.Pin       = GPIO_PIN_15;\n    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\n  }\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/drv_pwm.h",
    "content": "/*\r\n *  drv_pwm.h\r\n *\r\n *  Created on: 2016. 7.12.\r\n *      Author: Baram, PBHP\r\n */\r\n\r\n#ifndef DRV_PWM_H\r\n#define DRV_PWM_H\r\n\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n\r\n#include \"def.h\"\r\n#include \"bsp.h\"\r\n\r\n\r\n\r\n\r\n\r\n\r\nextern TIM_HandleTypeDef    hTIM1;\r\nextern TIM_HandleTypeDef    hTIM2;\r\nextern TIM_HandleTypeDef    hTIM3;\r\nextern TIM_HandleTypeDef    hTIM9;\r\nextern TIM_HandleTypeDef    hTIM11;\r\nextern TIM_HandleTypeDef    hTIM12;\r\n\r\n\r\nint drv_pwm_init();\r\n\r\nvoid drv_pwm_set_freq(uint32_t ulPin, uint32_t freq_data);\r\nuint32_t drv_pwm_get_freq(uint32_t ulPin);\r\nuint32_t drv_pwm_get_period(uint32_t ulPin);\r\n\r\nvoid drv_pwm_setup(uint32_t ulPin);\r\nvoid drv_pwm_release(uint32_t ulPin);\r\n\r\nvoid drv_pwm_set_duty(uint32_t ulPin, uint32_t res, uint32_t ulDuty );\r\nuint32_t drv_pwm_get_pulse(uint32_t ulPin);\r\nuint8_t drv_pwm_get_init(uint32_t ulPin);\r\n\r\n\r\n\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n\r\n#endif\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/drv_rtc.c",
    "content": "/*\r\n *  drv_rtc.c\r\n *\r\n *  Created on: 2017. 1. 13.\r\n *      Author: Baram\r\n */\r\n\r\n#include \"drv_rtc.h\"\r\n#include \"variant.h\"\r\n\r\n\r\nRTC_HandleTypeDef RtcHandle;\r\n\r\n\r\n\r\n#define RTC_ASYNCH_PREDIV  0x7F   /* LSE as RTC clock */\r\n#define RTC_SYNCH_PREDIV   0x00FF /* LSE as RTC clock */\r\n\r\n#define SECS_PER_MIN  (60UL)\r\n#define SECS_PER_HOUR (3600UL)\r\n#define SECS_PER_DAY  (SECS_PER_HOUR * 24UL)\r\n#define DAYS_PER_WEEK (7UL)\r\n#define SECS_PER_WEEK (SECS_PER_DAY * DAYS_PER_WEEK)\r\n#define SECS_PER_YEAR (SECS_PER_WEEK * 52UL)\r\n#define SECS_YR_2000  (946684800UL) // the time at the start of y2k\r\n\r\n\r\n//#define LEAP_YEAR(Y)     ( ((1970+Y)>0) && !((1970+Y)%4) && ( ((1970+Y)%100) || !((1970+Y)%400) ) )\r\n#define LEAP_YEAR(Y)     ( ((2000+Y)>0) && !((2000+Y)%4) && ( ((2000+Y)%100) || !((2000+Y)%400) ) )\r\n\r\nstatic  const uint8_t monthDays[]={31,28,31,30,31,30,31,31,30,31,30,31}; // API starts months from 1, this array starts from 0\r\n\r\n\r\n\r\n\r\nstatic void RTC_CalendarConfig(void);\r\nvoid   drv_rtc_breakTime(time_t timeInput, RTC_DateTypeDef *p_date, RTC_TimeTypeDef *p_time);\r\ntime_t drv_rtc_makeTime(RTC_DateTypeDef *p_date, RTC_TimeTypeDef *p_time);\r\n\r\n\r\n\r\nint drv_rtc_init()\r\n{\r\n  /*##-1- Configure the RTC peripheral #######################################*/\r\n  /* Configure RTC prescaler and RTC data registers */\r\n  /* RTC configured as follows:\r\n      - Hour Format    = Format 24\r\n      - Asynch Prediv  = Value according to source clock\r\n      - Synch Prediv   = Value according to source clock\r\n      - OutPut         = Output Disable\r\n      - OutPutPolarity = High Polarity\r\n      - OutPutType     = Open Drain */\r\n  RtcHandle.Instance = RTC;\r\n  RtcHandle.Init.HourFormat = RTC_HOURFORMAT_24;\r\n  RtcHandle.Init.AsynchPrediv = RTC_ASYNCH_PREDIV;\r\n  RtcHandle.Init.SynchPrediv = RTC_SYNCH_PREDIV;\r\n  RtcHandle.Init.OutPut = RTC_OUTPUT_DISABLE;\r\n  RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;\r\n  RtcHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;\r\n\r\n  if (HAL_RTC_Init(&RtcHandle) != HAL_OK)\r\n  {\r\n    /* Initialization Error */\r\n    //Error_Handler();\r\n  }\r\n\r\n\r\n  /*##-2- Check if Data stored in BackUp register1: No Need to reconfigure RTC#*/\r\n  /* Read the Back Up Register 1 Data */\r\n  if (HAL_RTCEx_BKUPRead(&RtcHandle, RTC_BKP_DR1) != 0x32F2)\r\n  {\r\n    /* Configure RTC Calendar */\r\n    RTC_CalendarConfig();\r\n  }\r\n\r\n  return 0;\r\n}\r\n\r\ntime_t rtcGetTime()\r\n{\r\n  RTC_DateTypeDef sdatestructureget;\r\n  RTC_TimeTypeDef stimestructureget;\r\n  time_t ret = 0;\r\n\r\n  /* Get the RTC current Time */\r\n  HAL_RTC_GetTime(&RtcHandle, &stimestructureget, RTC_FORMAT_BIN);\r\n  /* Get the RTC current Date */\r\n  HAL_RTC_GetDate(&RtcHandle, &sdatestructureget, RTC_FORMAT_BIN);\r\n\r\n\r\n  ret = drv_rtc_makeTime(&sdatestructureget, &stimestructureget);\r\n\r\n  return ret;\r\n}\r\n\r\nvoid rtcSetTime(time_t time_data)\r\n{\r\n  RTC_DateTypeDef sdatestructure;\r\n  RTC_TimeTypeDef stimestructure;\r\n\r\n\r\n  HAL_RTC_GetTime(&RtcHandle, &stimestructure, RTC_FORMAT_BIN);\r\n  HAL_RTC_GetDate(&RtcHandle, &sdatestructure, RTC_FORMAT_BIN);\r\n\r\n\r\n  drv_rtc_breakTime(time_data, &sdatestructure, &stimestructure);\r\n\r\n  //HAL_RTC_SetDate(&RtcHandle,&sdatestructure,RTC_FORMAT_BCD);\r\n  //HAL_RTC_SetTime(&RtcHandle, &stimestructure, RTC_FORMAT_BCD);\r\n  HAL_RTC_SetDate(&RtcHandle,&sdatestructure,RTC_FORMAT_BIN);\r\n  HAL_RTC_SetTime(&RtcHandle, &stimestructure, RTC_FORMAT_BIN);\r\n\r\n}\r\n\r\n\r\ntime_t drv_rtc_makeTime(RTC_DateTypeDef *p_date, RTC_TimeTypeDef *p_time)\r\n{\r\n// assemble time elements into time_t\r\n// note year argument is offset from 1970 (see macros in time.h to convert to other formats)\r\n// previous version used full four digit year (or digits since 2000),i.e. 2009 was 2009 or 9\r\n\r\n  int i;\r\n  uint32_t seconds;\r\n\r\n  // seconds from 1970 till 1 jan 00:00:00 of the given year\r\n  seconds= p_date->Year*(SECS_PER_DAY * 365);\r\n  for (i = 0; i < p_date->Year; i++) {\r\n    if (LEAP_YEAR(i)) {\r\n      seconds +=  SECS_PER_DAY;   // add extra days for leap years\r\n    }\r\n  }\r\n\r\n  // add days for this year, months start from 1\r\n  for (i = 1; i < p_date->Month; i++) {\r\n    if ( (i == 2) && LEAP_YEAR(p_date->Year)) {\r\n      seconds += SECS_PER_DAY * 29;\r\n    } else {\r\n      seconds += SECS_PER_DAY * monthDays[i-1];  //monthDay array starts from 0\r\n    }\r\n  }\r\n  seconds+= (p_date->Date-1) * SECS_PER_DAY;\r\n  seconds+= p_time->Hours * SECS_PER_HOUR;\r\n  seconds+= p_time->Minutes * SECS_PER_MIN;\r\n  seconds+= p_time->Seconds;\r\n  return (time_t)seconds;\r\n}\r\n\r\nvoid drv_rtc_breakTime(time_t timeInput, RTC_DateTypeDef *p_date, RTC_TimeTypeDef *p_time)\r\n{\r\n// break the given time_t into time components\r\n// this is a more compact version of the C library localtime function\r\n// note that year is offset from 1970 !!!\r\n\r\n  uint8_t year;\r\n  uint8_t month, monthLength;\r\n  uint32_t time;\r\n  unsigned long days;\r\n\r\n  time = (uint32_t)timeInput;\r\n  p_time->Seconds = time % 60;\r\n  time /= 60; // now it is minutes\r\n  p_time->Minutes = time % 60;\r\n  time /= 60; // now it is hours\r\n  p_time->Hours = time % 24;\r\n  time /= 24; // now it is days\r\n\r\n\r\n  year = 0;\r\n  days = 0;\r\n  while((unsigned)(days += (LEAP_YEAR(year) ? 366 : 365)) <= time) {\r\n    year++;\r\n  }\r\n  p_date->Year = year; // year is offset from 1970\r\n\r\n  days -= LEAP_YEAR(year) ? 366 : 365;\r\n  time  -= days; // now it is days in this year, starting at 0\r\n\r\n  days=0;\r\n  month=0;\r\n  monthLength=0;\r\n  for (month=0; month<12; month++) {\r\n    if (month==1) { // february\r\n      if (LEAP_YEAR(year)) {\r\n        monthLength=29;\r\n      } else {\r\n        monthLength=28;\r\n      }\r\n    } else {\r\n      monthLength = monthDays[month];\r\n    }\r\n\r\n    if (time >= monthLength) {\r\n      time -= monthLength;\r\n    } else {\r\n        break;\r\n    }\r\n  }\r\n  p_date->Month = month + 1;  // jan is month 1\r\n  p_date->Date = time + 1;     // day of month\r\n}\r\n\r\n\r\nvoid drv_rtc_write_step(uint32_t step_data)\r\n{\r\n  HAL_RTCEx_BKUPWrite(&RtcHandle, RTC_BKP_DR2, step_data);\r\n}\r\n\r\n\r\nuint32_t drv_rtc_read_step(void)\r\n{\r\n  return HAL_RTCEx_BKUPRead(&RtcHandle, RTC_BKP_DR2);\r\n}\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n/**\r\n  * @brief  Configure the current time and date.\r\n  * @param  None\r\n  * @retval None\r\n  */\r\nstatic void RTC_CalendarConfig(void)\r\n{\r\n  RTC_DateTypeDef sdatestructure;\r\n  RTC_TimeTypeDef stimestructure;\r\n\r\n  /*##-1- Configure the Date #################################################*/\r\n  /* Set Date: Tuesday February 18th 2014 */\r\n  sdatestructure.Year = 0x14;\r\n  sdatestructure.Month = RTC_MONTH_FEBRUARY;\r\n  sdatestructure.Date = 0x18;\r\n  sdatestructure.WeekDay = RTC_WEEKDAY_TUESDAY;\r\n\r\n  if(HAL_RTC_SetDate(&RtcHandle,&sdatestructure,RTC_FORMAT_BCD) != HAL_OK)\r\n  {\r\n    /* Initialization Error */\r\n    //Error_Handler();\r\n  }\r\n\r\n  /*##-2- Configure the Time #################################################*/\r\n  /* Set Time: 02:00:00 */\r\n  stimestructure.Hours = 0x02;\r\n  stimestructure.Minutes = 0x00;\r\n  stimestructure.Seconds = 0x00;\r\n  stimestructure.TimeFormat = RTC_HOURFORMAT12_AM;\r\n  stimestructure.DayLightSaving = RTC_DAYLIGHTSAVING_NONE ;\r\n  stimestructure.StoreOperation = RTC_STOREOPERATION_RESET;\r\n\r\n  if (HAL_RTC_SetTime(&RtcHandle, &stimestructure, RTC_FORMAT_BCD) != HAL_OK)\r\n  {\r\n    /* Initialization Error */\r\n    //Error_Handler();\r\n  }\r\n\r\n  /*##-3- Writes a data in a RTC Backup data Register1 #######################*/\r\n  HAL_RTCEx_BKUPWrite(&RtcHandle, RTC_BKP_DR1, 0x32F2);\r\n}\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\nvoid HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc)\r\n{\r\n  UNUSED(hrtc);\r\n\r\n  RCC_OscInitTypeDef        RCC_OscInitStruct;\r\n  RCC_PeriphCLKInitTypeDef  PeriphClkInitStruct;\r\n\r\n  /*##-1- Enables the PWR Clock and Enables access to the backup domain ###################################*/\r\n  /* To change the source clock of the RTC feature (LSE, LSI), You have to:\r\n     - Enable the power clock using __HAL_RCC_PWR_CLK_ENABLE()\r\n     - Enable write access using HAL_PWR_EnableBkUpAccess() function before to\r\n       configure the RTC clock source (to be done once after reset).\r\n     - Reset the Back up Domain using __HAL_RCC_BACKUPRESET_FORCE() and\r\n       __HAL_RCC_BACKUPRESET_RELEASE().\r\n     - Configure the needed RTc clock source */\r\n  __HAL_RCC_PWR_CLK_ENABLE();\r\n  HAL_PWR_EnableBkUpAccess();\r\n\r\n\r\n  /*##-2- Configure LSE as RTC clock source ###################################*/\r\n  RCC_OscInitStruct.OscillatorType =  RCC_OSCILLATORTYPE_LSE;\r\n  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;\r\n  RCC_OscInitStruct.LSEState = RCC_LSE_ON;\r\n  if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)\r\n  {\r\n    //Error_Handler();\r\n  }\r\n\r\n  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;\r\n  PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;\r\n  if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)\r\n  {\r\n    //Error_Handler();\r\n  }\r\n\r\n  /*##-3- Enable RTC peripheral Clocks #######################################*/\r\n  /* Enable RTC Clock */\r\n  __HAL_RCC_RTC_ENABLE();\r\n}\r\n\r\n/**\r\n  * @brief RTC MSP De-Initialization\r\n  *        This function frees the hardware resources used in this example:\r\n  *          - Disable the Peripheral's clock\r\n  * @param hrtc: RTC handle pointer\r\n  * @retval None\r\n  */\r\nvoid HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc)\r\n{\r\n  UNUSED(hrtc);\r\n\r\n  /*##-1- Reset peripherals ##################################################*/\r\n  __HAL_RCC_RTC_DISABLE();\r\n\r\n  /*##-2- Disables the PWR Clock and Disables access to the backup domain ###################################*/\r\n  HAL_PWR_DisableBkUpAccess();\r\n  __HAL_RCC_PWR_CLK_DISABLE();\r\n\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/drv_rtc.h",
    "content": "/*\n *  drv_rtc.h\n *\n *  Created on: 2017. 1.13.\n *      Author: Baram\n */\n\n#ifndef DRV_RTC_H\n#define DRV_RTC_H\n\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n#include <time.h>\n\n#include \"def.h\"\n#include \"bsp.h\"\n\n\n\n\n\n// interface for arduino\ntime_t rtcGetTime();\nvoid   rtcSetTime(time_t time_data);\n\n\nint drv_rtc_init();\nvoid     drv_rtc_write_step(uint32_t step_data);\nuint32_t drv_rtc_read_step(void);\n\n#ifdef __cplusplus\n}\n#endif\n\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/drv_spi.c",
    "content": "/*\n *  drv_spi.c\n *\n *  Created on: 2016. 7. 13.\n *      Author: Baram, PBHP\n */\n\n#include \"drv_spi.h\"\n#include \"variant.h\"\n#include \"dma_stream_handlers.h\"\n\n\n#define SPI_MAX_CH              3\n#define SPI_TX_DMA_MAX_LENGTH   0xEFFF\n\n\n\ntypedef struct\n{\n  bool    use;\n  bool    init;\n  uint32_t length_left;\n  bool    transfer_done;\n  // TX state variables\n  uint8_t *p_tx_buf;\n  // RX state variables - Maybe some can be combined with TX\n  uint8_t *p_rx_buf;\n  DrvSPIDMACallback dma_callback;    // Optional function to call at DMA completion\n} spi_dma_t;\n\n\nSPI_HandleTypeDef hspi1;\nSPI_HandleTypeDef hspi2;\nSPI_HandleTypeDef hspi4;\n\nstatic DMA_HandleTypeDef hdma2_tx;\nstatic DMA_HandleTypeDef hdma2_rx;\nstatic DMA_HandleTypeDef hdma4_tx;\nstatic DMA_HandleTypeDef hdma4_rx;\n\nvolatile spi_dma_t spi_dma[SPI_MAX_CH];\n\n\ninline volatile spi_dma_t *drv_map_haspi_to_spi_dma(SPI_HandleTypeDef* hspi) \n{\n  if (hspi->Instance == SPI1) return &spi_dma[0];\n  if (hspi->Instance == SPI2) return &spi_dma[1];\n  if (hspi->Instance == SPI4) return &spi_dma[2];\n  return NULL;\n}\n\n\n\n\nint drv_spi_init()\n{\n  uint8_t i;\n\n\n  hspi1.Instance                = SPI1;\n  hspi1.Init.Mode               = SPI_MODE_MASTER;\n  hspi1.Init.Direction          = SPI_DIRECTION_2LINES;\n  hspi1.Init.DataSize           = SPI_DATASIZE_8BIT;\n  hspi1.Init.CLKPolarity        = SPI_POLARITY_LOW;\n  hspi1.Init.CLKPhase           = SPI_PHASE_1EDGE;\n  hspi1.Init.NSS                = SPI_NSS_SOFT;\n  hspi1.Init.BaudRatePrescaler  = SPI_BAUDRATEPRESCALER_16;\n  hspi1.Init.FirstBit           = SPI_FIRSTBIT_MSB;\n  hspi1.Init.TIMode             = SPI_TIMODE_DISABLE;\n  hspi1.Init.CRCCalculation     = SPI_CRCCALCULATION_DISABLE;\n  hspi1.Init.CRCPolynomial      = 10;\n  //HAL_SPI_Init(&hspi1);\n\n  hspi2.Instance                = SPI2;\n  hspi2.Init.Mode               = SPI_MODE_MASTER;\n  hspi2.Init.Direction          = SPI_DIRECTION_2LINES;\n  hspi2.Init.DataSize           = SPI_DATASIZE_8BIT;\n  hspi2.Init.CLKPolarity        = SPI_POLARITY_LOW;\n  hspi2.Init.CLKPhase           = SPI_PHASE_1EDGE;\n  hspi2.Init.NSS                = SPI_NSS_SOFT;\n  hspi2.Init.BaudRatePrescaler  = SPI_BAUDRATEPRESCALER_16;\n  hspi2.Init.FirstBit           = SPI_FIRSTBIT_MSB;\n  hspi2.Init.TIMode             = SPI_TIMODE_DISABLE;\n  hspi2.Init.CRCCalculation     = SPI_CRCCALCULATION_DISABLE;\n  hspi2.Init.CRCPolynomial      = 10;\n  //HAL_SPI_Init(&hspi2);\n\n  hspi4.Instance                = SPI4;\n  hspi4.Init.Mode               = SPI_MODE_MASTER;\n  hspi4.Init.Direction          = SPI_DIRECTION_2LINES;\n  hspi4.Init.DataSize           = SPI_DATASIZE_8BIT;\n  hspi4.Init.CLKPolarity        = SPI_POLARITY_LOW;\n  hspi4.Init.CLKPhase           = SPI_PHASE_1EDGE;\n  hspi4.Init.NSS                = SPI_NSS_SOFT;\n  hspi4.Init.BaudRatePrescaler  = SPI_BAUDRATEPRESCALER_16;\n  hspi4.Init.FirstBit           = SPI_FIRSTBIT_MSB;\n  hspi4.Init.TIMode             = SPI_TIMODE_DISABLE;\n  hspi4.Init.CRCCalculation     = SPI_CRCCALCULATION_DISABLE;\n  hspi4.Init.CRCPolynomial      = 10;\n  //HAL_SPI_Init(&hspi4);\n\n\n  for(i=0; i<SPI_MAX_CH; i++)\n  {\n    spi_dma[i].p_tx_buf         = NULL;\n    spi_dma[i].p_rx_buf         = NULL;\n    spi_dma[i].use              = false;\n    spi_dma[i].init             = false;\n    spi_dma[i].transfer_done    = false;\n    spi_dma[i].length_left      = 0;\n    spi_dma[i].dma_callback     = NULL;\n  }\n\n  return 0;\n}\n\n\nvoid drv_spi_enable_dma(SPI_HandleTypeDef* hspi)\n{\n  if(hspi->Instance==SPI1)\n  {\n  }\n  else if(hspi->Instance==SPI2)\n  {\n    spi_dma[1].use = true;\n  }\n  else if(hspi->Instance==SPI4)\n  {\n    spi_dma[2].use = true;\n  }\n}\n\nbool drv_spi_dma_enabled(SPI_HandleTypeDef* hspi) \n{\n volatile spi_dma_t *pspi_dma = drv_map_haspi_to_spi_dma(hspi);\n return pspi_dma->use;\n}\n\n//=================================================================\n// Support for DMA TX Only\n//=================================================================\n\nuint8_t drv_spi_is_dma_tx_done(SPI_HandleTypeDef* hspi)\n{\n  volatile spi_dma_t *pspi_dma = drv_map_haspi_to_spi_dma(hspi);\n  if (!pspi_dma || (pspi_dma->use != true)) return true;  \n  return pspi_dma->transfer_done;\n}\n\n\nvoid drv_spi_start_dma_tx(SPI_HandleTypeDef* hspi, uint8_t *p_buf, uint32_t length, DrvSPIDMACallback dma_callback)\n{\n volatile spi_dma_t *pspi_dma = drv_map_haspi_to_spi_dma(hspi);\n\n  if ((pspi_dma == NULL) || (pspi_dma->use != true)) return ;\n\n  pspi_dma->transfer_done       = false;\n  pspi_dma->length_left     = length;\n  pspi_dma->p_tx_buf        =  p_buf;\n  pspi_dma->p_rx_buf        = NULL;   // this will funnel through txrx is set to NULL\n  pspi_dma->transfer_done   = false;\n  pspi_dma->dma_callback    = dma_callback;\n  \n  if(length > SPI_TX_DMA_MAX_LENGTH)\n    length = SPI_TX_DMA_MAX_LENGTH;\n\n  pspi_dma->length_left -= length;\n\n  HAL_SPI_TransmitReceive_DMA(hspi, pspi_dma->p_tx_buf, NULL, length);\n  //HAL_SPI_Transmit_DMA(hspi, pspi_dma->p_tx_buf, SPI_TX_DMA_MAX_LENGTH);\n}\n\nvoid HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)\n{\n//  HAL_GPIO_WritePin(GPIOC, GPIO_PIN_7, 1);    // digitalWrite(0, HIGH);\n  volatile spi_dma_t *pspi_dma = drv_map_haspi_to_spi_dma(hspi);\n  volatile uint32_t length;\n  if (pspi_dma && (hspi->Instance != SPI1))\n  {\n    length = pspi_dma->length_left;\n\n    if(length > 0)\n    {\n      pspi_dma->p_tx_buf += SPI_TX_DMA_MAX_LENGTH;\n      if (length > SPI_TX_DMA_MAX_LENGTH)\n      {\n        length = SPI_TX_DMA_MAX_LENGTH;\n      }\n      pspi_dma->length_left -= length;\n      //HAL_SPI_Transmit_DMA(hspi, pspi_dma->p_tx_buf, length);\n      HAL_SPI_TransmitReceive_DMA(hspi, pspi_dma->p_tx_buf, NULL, length);\n    }\n    else\n    {\n      pspi_dma->transfer_done = true;\n      if (pspi_dma->dma_callback) \n      {\n        (*pspi_dma->dma_callback)(hspi);\n      }\n    }\n\n  }\n//  HAL_GPIO_WritePin(GPIOC, GPIO_PIN_7, 0);    // digitalWrite(0, HIGH);\n}\n\n\n// SPIx_DMA_TX_IRQHandler(void)\n//\n#if 0\nvoid DMA1_Stream4_IRQHandler(void)\n{\n  HAL_DMA_IRQHandler(hspi2.hdmatx);\n}\n\nvoid DMA2_Stream1_IRQHandler(void)\n{\n  HAL_DMA_IRQHandler(hspi4.hdmatx);\n}\n\n\n// SPIx_DMA_RX_IRQHandler(void)\n//\nvoid DMA1_Stream3_IRQHandler(void)\n{\n  HAL_DMA_IRQHandler(hspi2.hdmarx);\n}\n\nvoid DMA2_Stream0_IRQHandler(void)\n{\n  HAL_DMA_IRQHandler(hspi4.hdmarx);\n}\n#endif\n\n//=================================================================\n// Support for DMA Transfer\n//=================================================================\nuint8_t drv_spi_is_dma_txrx_done(SPI_HandleTypeDef* hspi)\n{\n  volatile spi_dma_t *pspi_dma = drv_map_haspi_to_spi_dma(hspi);\n  if (!pspi_dma || (pspi_dma->use != true)) return true;  \n  return pspi_dma->transfer_done;\n}\n\n\nvoid drv_spi_start_dma_txrx(SPI_HandleTypeDef* hspi, uint8_t *p_buf, uint8_t *p_rxbuf, uint32_t length, DrvSPIDMACallback dma_callback)\n{\n volatile spi_dma_t *pspi_dma = drv_map_haspi_to_spi_dma(hspi);\n\n  if ((pspi_dma == NULL) || (pspi_dma->use != true)) return ;\n\n  // Assume TX and RX max length are the same\n  pspi_dma->p_tx_buf        =  p_buf;\n  pspi_dma->p_rx_buf        =  p_rxbuf;\n  pspi_dma->length_left     = length;\n  pspi_dma->transfer_done   = false;\n  pspi_dma->dma_callback    = dma_callback;\n\n\n  if (length > SPI_TX_DMA_MAX_LENGTH) \n  {\n    length = SPI_TX_DMA_MAX_LENGTH;\n  }\n  pspi_dma->length_left -= length;\n  HAL_SPI_TransmitReceive_DMA(hspi, pspi_dma->p_tx_buf, pspi_dma->p_rx_buf, length);\n}\n\nvoid HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)\n{\n  volatile spi_dma_t *pspi_dma = drv_map_haspi_to_spi_dma(hspi);\n  //HAL_GPIO_WritePin(GPIOC, GPIO_PIN_7, 1);    // digitalWrite(0, HIGH);\n  if (pspi_dma && (hspi->Instance != SPI1))\n  {\n    volatile uint32_t length = pspi_dma->length_left;\n    if(length > 0)\n    {\n      if (pspi_dma->p_rx_buf)\n      {\n        pspi_dma->p_rx_buf += SPI_TX_DMA_MAX_LENGTH;\n      }\n      if (pspi_dma->p_tx_buf)\n      {\n        pspi_dma->p_tx_buf += SPI_TX_DMA_MAX_LENGTH;\n      }\n\n      if (length > SPI_TX_DMA_MAX_LENGTH)\n      {\n        length = SPI_TX_DMA_MAX_LENGTH;\n      }\n      pspi_dma->length_left -= length;\n      //vcp_printf(\"TxRxCB: %x %x %d\\n\", (uint32_t)pspi_dma->p_tx_buf, (uint32_t)pspi_dma->p_rx_buf, length);\n      HAL_SPI_TransmitReceive_DMA(hspi, pspi_dma->p_tx_buf, pspi_dma->p_rx_buf, length);\n    }\n    else\n    {\n      pspi_dma->transfer_done = true;\n      if (pspi_dma->dma_callback) \n      {\n        (*pspi_dma->dma_callback)(hspi);\n      }\n    }\n\n  }\n  //HAL_GPIO_WritePin(GPIOC, GPIO_PIN_7, 0);    // digitalWrite(0, LOW);\n}\n\n\n\n//=================================================================\n// Init HAL SPI\n//=================================================================\nvoid HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)\n{\n\n  GPIO_InitTypeDef GPIO_InitStruct;\n\n\n  // BUGBUG:: Would be nice to more table drive this!\n\n  if(hspi->Instance==SPI1)\n  {\n    __HAL_RCC_SPI1_CLK_ENABLE();\n\n    GPIO_InitStruct.Pin       = GPIO_PIN_5;\n    GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;\n    GPIO_InitStruct.Pull      = GPIO_PULLUP;\n    GPIO_InitStruct.Speed     = GPIO_SPEED_HIGH;\n    GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;\n    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\n\n    /* SPI MISO GPIO pin configuration  */\n    GPIO_InitStruct.Pin       = GPIO_PIN_6;\n    GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;\n    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\n\n    /* SPI MOSI GPIO pin configuration  */\n    GPIO_InitStruct.Pin       = GPIO_PIN_5;\n    GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;\n    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\n  }\n  if(hspi->Instance==SPI2)\n  {\n    __HAL_RCC_SPI2_CLK_ENABLE();\n\n    GPIO_InitStruct.Pin       = GPIO_PIN_9;\n    GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;\n    GPIO_InitStruct.Pull      = GPIO_PULLUP;\n    GPIO_InitStruct.Speed     = GPIO_SPEED_HIGH;\n    GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;\n    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\n\n    /* SPI MISO GPIO pin configuration  */\n    GPIO_InitStruct.Pin       = GPIO_PIN_14;\n    GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;\n    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\n\n    /* SPI MOSI GPIO pin configuration  */\n    GPIO_InitStruct.Pin       = GPIO_PIN_15;\n    GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;\n    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\n\n\n    if(spi_dma[1].use == true && spi_dma[1].init == false)\n    {\n      spi_dma[1].init = true;\n\n      bsp_mpu_config();\n\n      __HAL_RCC_DMA1_CLK_ENABLE();\n\n      /*##-3- Configure the DMA ##################################################*/\n      /* Configure the DMA handler for Transmission process */\n      hdma2_tx.Instance                 = DMA1_Stream4;\n      hdma2_tx.Init.Channel             = DMA_CHANNEL_0;\n      hdma2_tx.Init.FIFOMode            = DMA_FIFOMODE_DISABLE;\n      hdma2_tx.Init.FIFOThreshold       = DMA_FIFO_THRESHOLD_FULL;\n      hdma2_tx.Init.MemBurst            = DMA_MBURST_INC4;\n      hdma2_tx.Init.PeriphBurst         = DMA_PBURST_INC4;\n      hdma2_tx.Init.Direction           = DMA_MEMORY_TO_PERIPH;\n      hdma2_tx.Init.PeriphInc           = DMA_PINC_DISABLE;\n      hdma2_tx.Init.MemInc              = DMA_MINC_ENABLE;\n      hdma2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;\n      hdma2_tx.Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;\n      hdma2_tx.Init.Mode                = DMA_NORMAL;\n      hdma2_tx.Init.Priority            = DMA_PRIORITY_LOW;\n\n      HAL_DMA_Init(&hdma2_tx);\n\n      /* Associate the initialized DMA handle to the the SPI handle */\n      __HAL_LINKDMA(hspi, hdmatx, hdma2_tx);\n    // TELL DMA ISR handler the handle to use during ISRs...\n    SetDMA1StreamHandlerHandle(4, &hdma2_tx, true, NULL);\n\n\n      HAL_NVIC_SetPriority(DMA1_Stream4_IRQn, 1, 1);\n      HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn);\n\n      /* Configure the DMA handler for receive process */\n      hdma2_rx.Instance                 = DMA1_Stream3;\n      hdma2_rx.Init.Channel             = DMA_CHANNEL_0;\n      hdma2_rx.Init.FIFOMode            = DMA_FIFOMODE_DISABLE;\n      hdma2_rx.Init.FIFOThreshold       = DMA_FIFO_THRESHOLD_FULL;\n      hdma2_rx.Init.MemBurst            = DMA_MBURST_INC4;\n      hdma2_rx.Init.PeriphBurst         = DMA_PBURST_INC4;\n      hdma2_rx.Init.Direction           = DMA_PERIPH_TO_MEMORY;\n      hdma2_rx.Init.PeriphInc           = DMA_PINC_DISABLE;\n      hdma2_rx.Init.MemInc              = DMA_MINC_ENABLE;\n      hdma2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;\n      hdma2_rx.Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;\n      hdma2_rx.Init.Mode                = DMA_NORMAL;\n      hdma2_rx.Init.Priority            = DMA_PRIORITY_LOW;\n\n      HAL_DMA_Init(&hdma2_rx);\n\n      /* Associate the initialized DMA handle to the the SPI handle */\n      __HAL_LINKDMA(hspi, hdmarx, hdma2_rx);\n\n    // TELL DMA ISR handler the handle to use during ISRs...\n    SetDMA1StreamHandlerHandle(3, &hdma2_rx, true, NULL);\n\n      HAL_NVIC_SetPriority(DMA1_Stream3_IRQn, 1, 1);\n      HAL_NVIC_EnableIRQ(DMA1_Stream3_IRQn);\n    }\n  }\n\n  if(hspi->Instance==SPI4)\n  {\n    __HAL_RCC_SPI4_CLK_ENABLE();\n    // SCK - Arduino pin 58\n    GPIO_InitStruct.Pin       = GPIO_PIN_12;\n    GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;\n    GPIO_InitStruct.Pull      = GPIO_PULLUP;\n    GPIO_InitStruct.Speed     = GPIO_SPEED_HIGH;\n    GPIO_InitStruct.Alternate = GPIO_AF5_SPI4;\n    HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);\n\n    /* SPI MISO GPIO pin configuration  59 */\n    GPIO_InitStruct.Pin       = GPIO_PIN_13;\n    GPIO_InitStruct.Alternate = GPIO_AF5_SPI4;\n    HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);\n\n    /* SPI MOSI GPIO pin configuration  60 */\n    GPIO_InitStruct.Pin       = GPIO_PIN_14;\n    GPIO_InitStruct.Alternate = GPIO_AF5_SPI4;\n    HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);\n\n\n    if(spi_dma[2].use == true && spi_dma[2].init == false)\n    {\n      spi_dma[2].init = true;\n\n      bsp_mpu_config();\n\n      __HAL_RCC_DMA2_CLK_ENABLE();\n\n      /* Configure the DMA handler for Transmission process */\n      hdma4_tx.Instance                 = DMA2_Stream1;\n      hdma4_tx.Init.Channel             = DMA_CHANNEL_4;\n      hdma4_tx.Init.FIFOMode            = DMA_FIFOMODE_DISABLE;\n      hdma4_tx.Init.FIFOThreshold       = DMA_FIFO_THRESHOLD_FULL;\n      hdma4_tx.Init.MemBurst            = DMA_MBURST_INC4;\n      hdma4_tx.Init.PeriphBurst         = DMA_PBURST_INC4;\n      hdma4_tx.Init.Direction           = DMA_MEMORY_TO_PERIPH;\n      hdma4_tx.Init.PeriphInc           = DMA_PINC_DISABLE;\n      hdma4_tx.Init.MemInc              = DMA_MINC_ENABLE;\n      hdma4_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;\n      hdma4_tx.Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;\n      hdma4_tx.Init.Mode                = DMA_NORMAL;\n      hdma4_tx.Init.Priority            = DMA_PRIORITY_LOW;\n\n      HAL_DMA_Init(&hdma4_tx);\n\n      /* Associate the initialized DMA handle to the the SPI handle */\n      __HAL_LINKDMA(hspi, hdmatx, hdma4_tx);\n\n      // TELL DMA ISR handler the handle to use during ISRs...\n      SetDMA2StreamHandlerHandle(1, &hdma4_tx, true, NULL);\n\n\n      HAL_NVIC_SetPriority(DMA2_Stream1_IRQn, 1, 1);\n      HAL_NVIC_EnableIRQ(DMA2_Stream1_IRQn);\n\n      /* Configure the DMA handler for receive process */\n      hdma4_rx.Instance                 = DMA2_Stream0;\n      hdma4_rx.Init.Channel             = DMA_CHANNEL_4;\n      hdma4_rx.Init.FIFOMode            = DMA_FIFOMODE_DISABLE;\n      hdma4_rx.Init.FIFOThreshold       = DMA_FIFO_THRESHOLD_FULL;\n      hdma4_rx.Init.MemBurst            = DMA_MBURST_INC4;\n      hdma4_rx.Init.PeriphBurst         = DMA_PBURST_INC4;\n      hdma4_rx.Init.Direction           = DMA_PERIPH_TO_MEMORY;\n      hdma4_rx.Init.PeriphInc           = DMA_PINC_DISABLE;\n      hdma4_rx.Init.MemInc              = DMA_MINC_ENABLE;\n      hdma4_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;\n      hdma4_rx.Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;\n      hdma4_rx.Init.Mode                = DMA_NORMAL;\n      hdma4_rx.Init.Priority            = DMA_PRIORITY_LOW;\n\n      HAL_DMA_Init(&hdma4_rx);\n\n      /* Associate the initialized DMA handle to the the SPI handle */\n      __HAL_LINKDMA(hspi, hdmarx, hdma4_rx);\n\n      // TELL DMA ISR handler the handle to use during ISRs...\n      SetDMA2StreamHandlerHandle(0, &hdma4_rx, true, NULL);\n\n      HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 1, 1);\n      HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn);\n\n    }\n  }\n\n}\n\nvoid HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)\n{\n\n  if(hspi->Instance==SPI1)\n  {\n    __HAL_RCC_SPI1_FORCE_RESET();\n    __HAL_RCC_SPI1_RELEASE_RESET();\n    __HAL_RCC_SPI1_CLK_DISABLE();\n\n\n    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5);\n    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_6);\n    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_5);\n\n    /* Peripheral interrupt Deinit*/\n    HAL_NVIC_DisableIRQ(SPI1_IRQn);\n  }\n\n  else if(hspi->Instance==SPI2)\n  {\n    __HAL_RCC_SPI2_FORCE_RESET();\n    __HAL_RCC_SPI2_RELEASE_RESET();\n    __HAL_RCC_SPI2_CLK_DISABLE();\n\n\n    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9);\n    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_14);\n    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_15);\n\n    /* Peripheral interrupt Deinit*/\n    HAL_NVIC_DisableIRQ(SPI2_IRQn);\n  }\n  else if(hspi->Instance==SPI4)\n  {\n    __HAL_RCC_SPI4_FORCE_RESET();\n    __HAL_RCC_SPI4_RELEASE_RESET();\n    __HAL_RCC_SPI4_CLK_DISABLE();\n\n\n    HAL_GPIO_DeInit(GPIOE, GPIO_PIN_12);\n    HAL_GPIO_DeInit(GPIOE, GPIO_PIN_13);\n    HAL_GPIO_DeInit(GPIOE, GPIO_PIN_14);\n\n    /* Peripheral interrupt Deinit*/\n    HAL_NVIC_DisableIRQ(SPI4_IRQn);\n  }\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/drv_spi.h",
    "content": "/*\n *  drv_spi.h\n *\n *  Created on: 2016. 7.13.\n *      Author: Baram, PBHP\n */\n\n#ifndef DRV_SPI_H\n#define DRV_SPI_H\n\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n\n#include \"def.h\"\n#include \"bsp.h\"\n\n\n\n\ntypedef void (*DrvSPIDMACallback)(SPI_HandleTypeDef* hspi);\n\n\n\nint     drv_spi_init();\nvoid    drv_spi_enable_dma(SPI_HandleTypeDef* hspi);\nbool    drv_spi_dma_enabled(SPI_HandleTypeDef* hspi);\nuint8_t drv_spi_is_dma_tx_done(SPI_HandleTypeDef* hspi);\nvoid    drv_spi_start_dma_tx(SPI_HandleTypeDef* hspi, uint8_t *p_buf, uint32_t length, DrvSPIDMACallback dma_callback);\nvoid    drv_spi_start_dma_txrx(SPI_HandleTypeDef* hspi, uint8_t *p_buf, uint8_t *p_rxbuf, uint32_t length, \n\t\t\tDrvSPIDMACallback dma_callback);\n\n#ifdef __cplusplus\n}\n#endif\n\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/drv_timer.c",
    "content": "/*\r\n *  drv_timer.c\r\n *\r\n *  Created on: 2016. 9. 23.\r\n *      Author: Baram, PBHP\r\n */\r\n#include \"drv_timer.h\"\r\n#include \"variant.h\"\r\n\r\n\r\n/*\r\n TIMER_CH1  TIM4\r\n TIMER_CH2  TIM10\r\n TIMER_CH3  TIM13\r\n TIMER_CH4  TIM14\r\n TIMER_CH5  TIM6    for USB\r\n\r\n TIMER_TONE TIMER_CH4\r\n\r\n */\r\n\r\n\r\ntypedef struct\r\n{\r\n  TIM_HandleTypeDef hTIM;\r\n  uint8_t  enable;\r\n  uint32_t freq;\r\n  uint32_t prescaler_value;\r\n  uint32_t prescaler_value_1M;\r\n  uint32_t prescaler_div;\r\n  uint32_t period;\r\n  voidFuncPtr handler;\r\n} DRV_TIMER_OBJ;\r\n\r\n\r\n\r\nDRV_TIMER_OBJ hDrvTim[TIMER_CH_MAX];\r\n\r\n\r\n\r\nint drv_timer_init()\r\n{\r\n  uint8_t tim_ch;\r\n  uint8_t i;\r\n\r\n\r\n  //-- TIMER_CH1  TIM4\r\n  //\r\n  tim_ch = TIMER_CH1;\r\n  hDrvTim[tim_ch].hTIM.Instance      = TIM4;\r\n  hDrvTim[tim_ch].prescaler_value    = (uint32_t)((SystemCoreClock / 2) / 10000  ) - 1; // 0.01Mhz\r\n  hDrvTim[tim_ch].prescaler_value_1M = (uint32_t)((SystemCoreClock / 2) / 1000000) - 1; // 1.00Mhz\r\n  hDrvTim[tim_ch].prescaler_div      = 100;\r\n  hDrvTim[tim_ch].hTIM.Init.Period        = 10000 - 1;\r\n  hDrvTim[tim_ch].hTIM.Init.Prescaler     = hDrvTim[tim_ch].prescaler_value;\r\n  hDrvTim[tim_ch].hTIM.Init.ClockDivision = 0;\r\n  hDrvTim[tim_ch].hTIM.Init.CounterMode   = TIM_COUNTERMODE_UP;\r\n  hDrvTim[tim_ch].hTIM.Init.RepetitionCounter = 0;\r\n\r\n\r\n  //-- TIMER_CH2  TIM10\r\n  //\r\n  tim_ch = TIMER_CH2;\r\n  hDrvTim[tim_ch].hTIM.Instance      = TIM10;\r\n  hDrvTim[tim_ch].prescaler_value    = (uint32_t)((SystemCoreClock / 1) / 10000  ) - 1; // 0.01Mhz\r\n  hDrvTim[tim_ch].prescaler_value_1M = (uint32_t)((SystemCoreClock / 1) / 1000000) - 1; // 1.00Mhz\r\n  hDrvTim[tim_ch].prescaler_div      = 100;\r\n  hDrvTim[tim_ch].hTIM.Init.Period        = 10000 - 1;\r\n  hDrvTim[tim_ch].hTIM.Init.Prescaler     = hDrvTim[tim_ch].prescaler_value;\r\n  hDrvTim[tim_ch].hTIM.Init.ClockDivision = 0;\r\n  hDrvTim[tim_ch].hTIM.Init.CounterMode   = TIM_COUNTERMODE_UP;\r\n  hDrvTim[tim_ch].hTIM.Init.RepetitionCounter = 0;\r\n\r\n\r\n  //-- TIMER_CH3  TIM13\r\n  //\r\n  tim_ch = TIMER_CH3;\r\n  hDrvTim[tim_ch].hTIM.Instance      = TIM13;\r\n  hDrvTim[tim_ch].prescaler_value    = (uint32_t)((SystemCoreClock / 2) / 10000  ) - 1; // 0.01Mhz\r\n  hDrvTim[tim_ch].prescaler_value_1M = (uint32_t)((SystemCoreClock / 2) / 1000000) - 1; // 1.00Mhz\r\n  hDrvTim[tim_ch].prescaler_div      = 100;\r\n  hDrvTim[tim_ch].hTIM.Init.Period        = 10000 - 1;\r\n  hDrvTim[tim_ch].hTIM.Init.Prescaler     = hDrvTim[tim_ch].prescaler_value;\r\n  hDrvTim[tim_ch].hTIM.Init.ClockDivision = 0;\r\n  hDrvTim[tim_ch].hTIM.Init.CounterMode   = TIM_COUNTERMODE_UP;\r\n  hDrvTim[tim_ch].hTIM.Init.RepetitionCounter = 0;\r\n\r\n\r\n  //-- TIMER_TONE  TIM14\r\n  //\r\n  tim_ch = TIMER_TONE;\r\n  hDrvTim[tim_ch].hTIM.Instance      = TIM14;\r\n  hDrvTim[tim_ch].prescaler_value    = (uint32_t)((SystemCoreClock / 2) / 10000  ) - 1; // 1Mhz\r\n  hDrvTim[tim_ch].prescaler_value_1M = (uint32_t)((SystemCoreClock / 2) / 1000000) - 1; // 1.00Mhz\r\n  hDrvTim[tim_ch].prescaler_div      = 100;\r\n  hDrvTim[tim_ch].hTIM.Init.Period        = 10000 - 1;\r\n  hDrvTim[tim_ch].hTIM.Init.Prescaler     = hDrvTim[tim_ch].prescaler_value;\r\n  hDrvTim[tim_ch].hTIM.Init.ClockDivision = 0;\r\n  hDrvTim[tim_ch].hTIM.Init.CounterMode   = TIM_COUNTERMODE_UP;\r\n  hDrvTim[tim_ch].hTIM.Init.RepetitionCounter = 0;\r\n\r\n\r\n  //-- TIMER_CH5  TIM6\r\n  //\r\n  tim_ch = TIMER_USB;\r\n  hDrvTim[tim_ch].hTIM.Instance      = TIM6;\r\n  hDrvTim[tim_ch].prescaler_value    = (uint32_t)((SystemCoreClock / 2) / 10000  ) - 1; // 0.01Mhz\r\n  hDrvTim[tim_ch].prescaler_value_1M = (uint32_t)((SystemCoreClock / 2) / 1000000) - 1; // 1.00Mhz\r\n  hDrvTim[tim_ch].prescaler_div      = 100;\r\n  hDrvTim[tim_ch].hTIM.Init.Period        = 10000 - 1;\r\n  hDrvTim[tim_ch].hTIM.Init.Prescaler     = hDrvTim[tim_ch].prescaler_value;\r\n  hDrvTim[tim_ch].hTIM.Init.ClockDivision = 0;\r\n  hDrvTim[tim_ch].hTIM.Init.CounterMode   = TIM_COUNTERMODE_UP;\r\n  hDrvTim[tim_ch].hTIM.Init.RepetitionCounter = 0;\r\n\r\n\r\n\r\n  for( i=0; i<TIMER_CH_MAX; i++ )\r\n  {\r\n    hDrvTim[i].handler = NULL;\r\n    hDrvTim[i].enable  = 0;\r\n  }\r\n\r\n  return 0;\r\n}\r\n\r\n\r\nvoid HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)\r\n{\r\n  if( htim->Instance == TIM4 )\r\n  {\r\n    __HAL_RCC_TIM4_CLK_ENABLE();\r\n\r\n    HAL_NVIC_SetPriority(TIM4_IRQn, 10, 0);\r\n    HAL_NVIC_EnableIRQ(TIM4_IRQn);\r\n  }\r\n  if( htim->Instance == TIM10 )\r\n  {\r\n    __HAL_RCC_TIM10_CLK_ENABLE();\r\n\r\n    HAL_NVIC_SetPriority(TIM1_UP_TIM10_IRQn, 10, 0);\r\n    HAL_NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn);\r\n  }\r\n  if( htim->Instance == TIM13 )\r\n  {\r\n    __HAL_RCC_TIM13_CLK_ENABLE();\r\n    HAL_NVIC_SetPriority(TIM8_UP_TIM13_IRQn, 10, 0);\r\n    HAL_NVIC_EnableIRQ(TIM8_UP_TIM13_IRQn);\r\n  }\r\n  if( htim->Instance == TIM14 )\r\n  {\r\n    __HAL_RCC_TIM14_CLK_ENABLE();\r\n    HAL_NVIC_SetPriority(TIM8_TRG_COM_TIM14_IRQn, 10, 0);\r\n    HAL_NVIC_EnableIRQ(TIM8_TRG_COM_TIM14_IRQn);\r\n  }\r\n  if( htim->Instance == TIM6 )\r\n  {\r\n    __HAL_RCC_TIM6_CLK_ENABLE();\r\n    HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 10, 0);\r\n    HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);\r\n  }\r\n\r\n}\r\n\r\n\r\nvoid HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef* htim)\r\n{\r\n  UNUSED(htim);\r\n}\r\n\r\n\r\nvoid HAL_TIMEx_BreakCallback(TIM_HandleTypeDef* htim)\r\n{\r\n  UNUSED(htim);\r\n}\r\n\r\n\r\nvoid TIM4_IRQHandler(void)\r\n{\r\n  HAL_TIM_IRQHandler(&hDrvTim[TIMER_CH1].hTIM);\r\n}\r\nvoid TIM1_UP_TIM10_IRQHandler(void)\r\n{\r\n  HAL_TIM_IRQHandler(&hDrvTim[TIMER_CH2].hTIM);\r\n}\r\nvoid TIM8_UP_TIM13_IRQHandler(void)\r\n{\r\n  HAL_TIM_IRQHandler(&hDrvTim[TIMER_CH3].hTIM);\r\n}\r\nvoid TIM8_TRG_COM_TIM14_IRQHandler(void)\r\n{\r\n  HAL_TIM_IRQHandler(&hDrvTim[TIMER_TONE].hTIM);\r\n}\r\nvoid TIM6_DAC_IRQHandler(void)\r\n{\r\n  HAL_TIM_IRQHandler(&hDrvTim[TIMER_USB].hTIM);\r\n}\r\n\r\nvoid HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)\r\n{\r\n  uint8_t i;\r\n\r\n\r\n  for( i=0; i<TIMER_CH_MAX; i++ )\r\n  {\r\n    if( htim->Instance == hDrvTim[i].hTIM.Instance )\r\n    {\r\n      if( hDrvTim[i].handler != NULL )\r\n      {\r\n        (*hDrvTim[i].handler)();\r\n      }\r\n    }\r\n  }\r\n}\r\n\r\n\r\nvoid HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)\r\n{\r\n  if( htim->Instance == TIM4 )\r\n  {\r\n    HAL_NVIC_DisableIRQ(TIM4_IRQn);\r\n  }\r\n  if( htim->Instance == TIM10 )\r\n  {\r\n    HAL_NVIC_DisableIRQ(TIM1_UP_TIM10_IRQn);\r\n  }\r\n  if( htim->Instance == TIM13 )\r\n  {\r\n    HAL_NVIC_DisableIRQ(TIM8_UP_TIM13_IRQn);\r\n  }\r\n  if( htim->Instance == TIM14 )\r\n  {\r\n    HAL_NVIC_DisableIRQ(TIM8_TRG_COM_TIM14_IRQn);\r\n  }\r\n  if( htim->Instance == TIM6 )\r\n  {\r\n    HAL_NVIC_DisableIRQ(TIM6_DAC_IRQn);\r\n  }\r\n\r\n}\r\n\r\nvoid drv_timer_pause(uint8_t channel)\r\n{\r\n  if( channel >= TIMER_CH_MAX ) return;\r\n\r\n  hDrvTim[channel].enable = 0;\r\n  HAL_TIM_Base_DeInit(&hDrvTim[channel].hTIM);\r\n}\r\n\r\nvoid drv_timer_set_period(uint8_t channel, uint32_t period_data)\r\n{\r\n  if( channel >= TIMER_CH_MAX ) return;\r\n\r\n  if( period_data > 0xFFFF )\r\n  {\r\n    hDrvTim[channel].hTIM.Init.Prescaler = hDrvTim[channel].prescaler_value;\r\n    hDrvTim[channel].hTIM.Init.Period    = (period_data/hDrvTim[channel].prescaler_div) - 1;\r\n  }\r\n  else\r\n  {\r\n    if( period_data > 0 )\r\n    {\r\n      hDrvTim[channel].hTIM.Init.Prescaler = hDrvTim[channel].prescaler_value_1M;\r\n      hDrvTim[channel].hTIM.Init.Period    = period_data - 1;\r\n    }\r\n  }\r\n}\r\n\r\n\r\nvoid drv_timer_attachInterrupt(uint8_t channel, voidFuncPtr handler)\r\n{\r\n  if( channel >= TIMER_CH_MAX ) return;\r\n\r\n  hDrvTim[channel].handler = handler;\r\n}\r\n\r\n\r\nvoid drv_timer_detachInterrupt(uint8_t channel)\r\n{\r\n  if( channel >= TIMER_CH_MAX ) return;\r\n\r\n  hDrvTim[channel].handler = NULL;\r\n}\r\n\r\nvoid drv_timer_refresh(uint8_t channel)\r\n{\r\n  UNUSED(channel);\r\n}\r\n\r\n\r\nvoid drv_timer_resume(uint8_t channel)\r\n{\r\n  if( channel >= TIMER_CH_MAX ) return;\r\n\r\n  HAL_TIM_Base_Init(&hDrvTim[channel].hTIM);\r\n  HAL_TIM_Base_Start_IT(&hDrvTim[channel].hTIM);\r\n\r\n  hDrvTim[channel].enable = 1;\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/drv_timer.h",
    "content": "/*\n *  drv_timer.h\n *\n *  Created on: 2016. 9.23.\n *      Author: Baram, PBHP\n */\n\n#ifndef DRV_TIMER_H\n#define DRV_TIMER_H\n\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n\n#include \"def.h\"\n#include \"bsp.h\"\n\n\n\n\n#define TIMER_CH_MAX  5\n\n#define TIMER_CH1     0\n#define TIMER_CH2     1\n#define TIMER_CH3     2\n#define TIMER_CH4     3\n#define TIMER_TONE    3\n#define TIMER_USB     4\n\n\n\nint drv_timer_init();\n\nvoid drv_timer_pause(uint8_t channel);\nvoid drv_timer_set_period(uint8_t channel, uint32_t period_data);\nvoid drv_timer_attachInterrupt(uint8_t channel, voidFuncPtr handler);\nvoid drv_timer_detachInterrupt(uint8_t channel);\nvoid drv_timer_refresh(uint8_t channel);\nvoid drv_timer_resume(uint8_t channel);\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/drv_uart.c",
    "content": "/*\r\n *  drv_uart.c\r\n *\r\n *  Created on: 2016. 7. 13.\r\n *      Author: Baram, PBHP\r\n */\r\n/*\r\n\r\n  USART6\r\n    - RX : DMA2, Channel 5, Stream 2\r\n    - TX : DMA2, Channel 5, Stream 6\r\n\r\n  USART2\r\n    - RX : DMA1, Channel 4, Stream 5\r\n    - TX : DMA1, Channel 4, Stream 6\r\n\r\n  USART3\r\n    - RX : DMA1, Channel 4, Stream 1\r\n    - TX : DMA1, Channel 4, Stream 3\r\n\r\n  USART8\r\n    - RX : DMA1, Channel 5, Stream 6\r\n    - TX : DMA1, Channel 5, Stream 0\r\n*/\r\n#include \"drv_uart.h\"\r\n#include \"variant.h\"\r\n#include \"dma_stream_handlers.h\"\r\n\r\n\r\n//-- internal definition\r\n//\r\n#define DRV_UART_RX_BUF_LENGTH      1024\r\n\r\n\r\n//-- internal variable\r\n//\r\nstatic uint32_t drv_uart_rx_buf_head[DRV_UART_NUM_MAX];\r\nstatic uint32_t drv_uart_rx_buf_tail[DRV_UART_NUM_MAX];\r\nstatic uint8_t  drv_uart_rx_buf[DRV_UART_NUM_MAX][DRV_UART_RX_BUF_LENGTH] __attribute__((section(\".NoneCacheableMem\")));\r\n\r\n\r\nstatic BOOL is_init[DRV_UART_NUM_MAX];\r\nstatic BOOL is_uart_mode[DRV_UART_NUM_MAX];\r\nstatic BOOL is_uart_write_dma_mode[DRV_UART_NUM_MAX];\r\n\r\nUART_HandleTypeDef huart[DRV_UART_NUM_MAX];\r\nDMA_HandleTypeDef  hdma_rx[DRV_UART_NUM_MAX];\r\nDMA_HandleTypeDef  hdma_tx[DRV_UART_NUM_MAX];\r\nUSART_TypeDef     *huart_inst[DRV_UART_NUM_MAX] = { USART6, USART2, USART3, UART8 };\r\n\r\n\r\n//-- internal functions definition\r\n//\r\nvoid drv_uart_err_handler(uint8_t uart_num);\r\n\r\n\r\n\r\n\r\nint drv_uart_init()\r\n{\r\n  uint8_t i;\r\n\r\n\r\n  for(i=0; i<DRV_UART_NUM_MAX; i++)\r\n  {\r\n    is_init[i]      = FALSE;\r\n    is_uart_mode[i] = DRV_UART_IRQ_MODE;\r\n    is_uart_write_dma_mode[i] = false;  // assume IT mode\r\n\r\n    drv_uart_rx_buf_head[i] = 0;\r\n    drv_uart_rx_buf_tail[i] = 0;\r\n  }\r\n\r\n  return 0;\r\n}\r\n\r\nvoid drv_uart_begin(uint8_t uart_num, uint8_t uart_mode, uint32_t baudrate)\r\n{\r\n  if(uart_num < DRV_UART_NUM_MAX)\r\n  {\r\n    huart[uart_num].Instance          = huart_inst[uart_num];\r\n    huart[uart_num].Init.BaudRate     = baudrate;\r\n    huart[uart_num].Init.WordLength   = UART_WORDLENGTH_8B;\r\n    huart[uart_num].Init.StopBits     = UART_STOPBITS_1;\r\n    huart[uart_num].Init.Parity       = UART_PARITY_NONE;\r\n    huart[uart_num].Init.Mode         = UART_MODE_TX_RX;\r\n    huart[uart_num].Init.HwFlowCtl    = UART_HWCONTROL_NONE;\r\n    huart[uart_num].Init.OverSampling = UART_OVERSAMPLING_16;\r\n    huart[uart_num].AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;\r\n\r\n    is_uart_mode[uart_num] = uart_mode;  // remember if we are DMA or not\r\n    HAL_UART_Init(&huart[uart_num]);\r\n\r\n    is_init[uart_num] = TRUE;\r\n\r\n    drv_uart_start_rx(uart_num);\r\n\r\n    if (hdma_rx[uart_num].Instance) \r\n    {\r\n      // Only set if DMA instance is set, else can leave alone as tail will be set to \r\n      // whatever this one is... \r\n      drv_uart_rx_buf_head[uart_num] = DRV_UART_RX_BUF_LENGTH - hdma_rx[uart_num].Instance->NDTR;\r\n    }\r\n    drv_uart_rx_buf_tail[uart_num] = drv_uart_rx_buf_head[uart_num];\r\n\r\n  }\r\n}\r\n\r\nuint32_t drv_uart_write(uint8_t uart_num, const uint8_t wr_data)\r\n{\r\n  HAL_UART_Transmit(&huart[uart_num], (uint8_t *)&wr_data, 1, 10);\r\n  return 1;\r\n}\r\n\r\nuint32_t drv_uart_write_dma_it(uint8_t uart_num, const uint8_t *wr_data, uint16_t Size)\r\n{\r\n  // call the DMA or IT function depending on if configured for DMA or not.\r\n  if (is_uart_write_dma_mode[uart_num]) \r\n  {\r\n    return (uint32_t)HAL_UART_Transmit_DMA(&huart[uart_num], (uint8_t *)wr_data, Size);  \r\n  }\r\n  return (uint32_t)HAL_UART_Transmit_IT(&huart[uart_num], (uint8_t *)wr_data, Size);  \r\n}\r\n\r\n\r\nvoid drv_uart_flush(uint8_t uart_num)\r\n{\r\n  UNUSED(uart_num);\r\n}\r\n\r\n// Only called in DMA case. \r\nvoid drv_uart_rx_flush(uint8_t uart_num, uint32_t timeout_ms)\r\n{\r\n  uint32_t pre_time_ms = millis();\r\n  while((drv_uart_read(uart_num) != -1) || (millis() - pre_time_ms < timeout_ms))\r\n  {\r\n  }\r\n}\r\n\r\n\r\nvoid drv_uart_start_rx(uint8_t uart_num)\r\n{\r\n#ifdef DRV_UART_RX_DMA_ONLY\r\n  if(is_uart_mode[uart_num] == DRV_UART_IRQ_MODE)\r\n  {\r\n    HAL_UART_Receive_IT(&huart[uart_num], (uint8_t *)drv_uart_rx_buf[uart_num], 1);\r\n  }\r\n  else\r\n  {\r\n    HAL_UART_Receive_DMA(&huart[uart_num], (uint8_t *)drv_uart_rx_buf[uart_num], DRV_UART_RX_BUF_LENGTH );\r\n  }\r\n#else\r\n  HAL_UART_Receive_DMA(&huart[uart_num], (uint8_t *)drv_uart_rx_buf[uart_num], DRV_UART_RX_BUF_LENGTH );\r\n#endif  \r\n}\r\n\r\nuint32_t drv_uart_read_buf(uint8_t uart_num, uint8_t *p_buf, uint32_t length)\r\n{\r\n  uint32_t ret = 0;\r\n#ifdef DRV_UART_RX_DMA_ONLY\r\n  uint32_t i;\r\n\r\n  if(is_uart_mode[uart_num] == DRV_UART_IRQ_MODE)\r\n  {\r\n    for( i=0; i<length; i++)\r\n    {\r\n      p_buf[i] = drv_uart_rx_buf[uart_num][i];\r\n    }\r\n    ret = length;\r\n  }\r\n  else\r\n  {\r\n\r\n  }\r\n#else\r\n  UNUSED(uart_num);\r\n  UNUSED(p_buf);\r\n  UNUSED(length);  \r\n#endif\r\n  return ret;\r\n}\r\n\r\nuint8_t drv_uart_get_mode(uint8_t uart_num)\r\n\r\n{\r\n  return is_uart_mode[uart_num];\r\n}\r\n// Only called in DMA mode\r\nuint32_t  drv_uart_available(uint8_t uart_num)\r\n{\r\n  uint32_t length = 0;\r\n\r\n  drv_uart_rx_buf_head[uart_num] = DRV_UART_RX_BUF_LENGTH - hdma_rx[uart_num].Instance->NDTR;\r\n\r\n  length = (   DRV_UART_RX_BUF_LENGTH\r\n             + drv_uart_rx_buf_head[uart_num]\r\n             - drv_uart_rx_buf_tail[uart_num] ) % DRV_UART_RX_BUF_LENGTH;\r\n\r\n  return length;\r\n}\r\n\r\n// Only called in DMA mode\r\nint drv_uart_read(uint8_t uart_num)\r\n{\r\n    int ret = -1;\r\n    int index;\r\n\r\n    // Need to update head like available does - DMA updates it...\r\n    drv_uart_rx_buf_head[uart_num] = DRV_UART_RX_BUF_LENGTH - hdma_rx[uart_num].Instance->NDTR;\r\n    if (drv_uart_rx_buf_head[uart_num] != drv_uart_rx_buf_tail[uart_num])\r\n    {\r\n      index = drv_uart_rx_buf_tail[uart_num];\r\n      ret = drv_uart_rx_buf[uart_num][index];\r\n      drv_uart_rx_buf_tail[uart_num] = (drv_uart_rx_buf_tail[uart_num] + 1) % DRV_UART_RX_BUF_LENGTH;\r\n    }\r\n    return ret;\r\n}\r\n\r\n// Only called in DMA mode\r\nint drv_uart_peek(uint8_t uart_num)\r\n{\r\n    int ret = -1;\r\n    int index;\r\n\r\n    // Need to update head like available does - DMA updates it...\r\n    drv_uart_rx_buf_head[uart_num] = DRV_UART_RX_BUF_LENGTH - hdma_rx[uart_num].Instance->NDTR;\r\n    if (drv_uart_rx_buf_head[uart_num] != drv_uart_rx_buf_tail[uart_num])\r\n    {\r\n      index = drv_uart_rx_buf_tail[uart_num];\r\n      ret = drv_uart_rx_buf[uart_num][index];\r\n    }\r\n    return ret;\r\n}\r\n\r\nvoid drv_uart_err_handler(uint8_t uart_num)\r\n{\r\n#ifdef DRV_UART_RX_DMA_ONLY\r\n  if(is_uart_mode[uart_num] == DRV_UART_IRQ_MODE)\r\n  {\r\n    drv_uart_start_rx(uart_num);\r\n  }\r\n  else\r\n  {\r\n\r\n  }\r\n#else\r\n  drv_uart_start_rx(uart_num);\r\n#endif  \r\n}\r\n\r\n\r\n\r\n\r\nvoid USART6_IRQHandler(void)\r\n{\r\n  HAL_UART_IRQHandler(&huart[DRV_UART_NUM_1]);\r\n}\r\n\r\n\r\nvoid USART2_IRQHandler(void)\r\n{\r\n  HAL_UART_IRQHandler(&huart[DRV_UART_NUM_2]);\r\n}\r\n\r\nvoid USART3_IRQHandler(void)\r\n{\r\n  HAL_UART_IRQHandler(&huart[DRV_UART_NUM_3]);\r\n}\r\n\r\nvoid UART8_IRQHandler(void)\r\n{\r\n  HAL_UART_IRQHandler(&huart[DRV_UART_NUM_4]);\r\n}\r\n\r\nvoid HAL_UART_TxCpltCallback(UART_HandleTypeDef *UartHandle)\r\n{\r\n  if( UartHandle->Instance == huart_inst[DRV_UART_NUM_1] ) Tx1_Handler();\r\n  if( UartHandle->Instance == huart_inst[DRV_UART_NUM_2] ) Tx2_Handler();\r\n  if( UartHandle->Instance == huart_inst[DRV_UART_NUM_3] ) Tx3_Handler();\r\n  if( UartHandle->Instance == huart_inst[DRV_UART_NUM_4] ) Tx4_Handler();\r\n\r\n}\r\n\r\n\r\nvoid HAL_UART_RxCpltCallback(UART_HandleTypeDef *UartHandle)\r\n{\r\n  __HAL_UART_FLUSH_DRREGISTER(UartHandle);\r\n#ifdef DRV_UART_RX_DMA_ONLY\r\n  if( UartHandle->Instance == huart_inst[DRV_UART_NUM_1] ) Rx1_Handler();\r\n  if( UartHandle->Instance == huart_inst[DRV_UART_NUM_2] ) Rx2_Handler();\r\n  if( UartHandle->Instance == huart_inst[DRV_UART_NUM_3] ) Rx3_Handler();\r\n  if( UartHandle->Instance == huart_inst[DRV_UART_NUM_4] ) Rx4_Handler();\r\n#endif\r\n}\r\n\r\n\r\nvoid HAL_UART_ErrorCallback(UART_HandleTypeDef *UartHandle)\r\n{\r\n  if( UartHandle->Instance == huart_inst[DRV_UART_NUM_1] ) drv_uart_err_handler(DRV_UART_NUM_1);\r\n  if( UartHandle->Instance == huart_inst[DRV_UART_NUM_2] ) drv_uart_err_handler(DRV_UART_NUM_2);\r\n  if( UartHandle->Instance == huart_inst[DRV_UART_NUM_3] ) drv_uart_err_handler(DRV_UART_NUM_3);\r\n  if( UartHandle->Instance == huart_inst[DRV_UART_NUM_4] ) drv_uart_err_handler(DRV_UART_NUM_4);\r\n}\r\n\r\n#if 0\r\n// UART2 DMA IRQ\r\nvoid DMA1_Stream5_IRQHandler(void)\r\n{\r\n  HAL_DMA_IRQHandler(huart[DRV_UART_NUM_2].hdmarx);\r\n}\r\n\r\n// UART3 DMA IRQ\r\nvoid DMA1_Stream1_IRQHandler(void)\r\n{\r\n  HAL_DMA_IRQHandler(huart[DRV_UART_NUM_3].hdmarx);\r\n}\r\n\r\nvoid DMA1_Stream3_IRQHandler(void)\r\n{\r\n  HAL_DMA_IRQHandler(huart[DRV_UART_NUM_3].hdmatx);\r\n}\r\n#endif\r\n\r\n// In case SPI2 wishes to use DMA and we were already\r\n// using it for Serial3.  Downgrade Serial3 to IT mode...\r\nvoid HAL_UART_LoseDMAHandler(uint8_t iStream)\r\n{\r\n  if (iStream == 3)\r\n  {\r\n    drv_uart_flush(DRV_UART_NUM_3); // note does not do anything currently...\r\n    is_uart_write_dma_mode[DRV_UART_NUM_3] = false;\r\n  }\r\n  else if (iStream == 6)\r\n  {\r\n    drv_uart_flush(DRV_UART_NUM_2); // note does not do anything currently...\r\n    is_uart_write_dma_mode[DRV_UART_NUM_2] = false;\r\n  }\r\n\r\n}\r\n\r\nvoid HAL_UART_MspInit(UART_HandleTypeDef* huart)\r\n{\r\n\r\n  GPIO_InitTypeDef GPIO_InitStruct;\r\n  RCC_PeriphCLKInitTypeDef  RCC_PeriphCLKInitStruct;\r\n\r\n\r\n  if(huart->Instance==USART6) // // UART_NUM_1\r\n  {\r\n    RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART6;\r\n    RCC_PeriphCLKInitStruct.Usart6ClockSelection = RCC_USART6CLKSOURCE_SYSCLK;\r\n    HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct);\r\n\r\n    /* Peripheral clock enable */\r\n    __HAL_RCC_USART6_CLK_ENABLE();\r\n\r\n    GPIO_InitStruct.Pin       = GPIO_PIN_6;\r\n    GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;\r\n    GPIO_InitStruct.Pull      = GPIO_PULLUP;\r\n    GPIO_InitStruct.Speed     = GPIO_SPEED_HIGH;\r\n    GPIO_InitStruct.Alternate = GPIO_AF8_USART6;\r\n    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);\r\n\r\n\r\n    GPIO_InitStruct.Pin       = GPIO_PIN_7;\r\n    GPIO_InitStruct.Alternate = GPIO_AF8_USART6;\r\n    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);\r\n\r\n#ifdef DRV_UART_RX_DMA_ONLY\r\n    if(is_uart_mode[DRV_UART_NUM_1] == DRV_UART_DMA_MODE) \r\n#endif\r\n    {\r\n      // DMA Setup\r\n      /* Configure the DMA handler for reception process */\r\n      __HAL_RCC_DMA2_CLK_ENABLE();\r\n      hdma_rx[DRV_UART_NUM_1].Instance                 = DMA2_Stream2;\r\n      hdma_rx[DRV_UART_NUM_1].Init.Channel             = DMA_CHANNEL_5;\r\n      hdma_rx[DRV_UART_NUM_1].Init.Direction           = DMA_PERIPH_TO_MEMORY;\r\n      hdma_rx[DRV_UART_NUM_1].Init.PeriphInc           = DMA_PINC_DISABLE;\r\n      hdma_rx[DRV_UART_NUM_1].Init.MemInc              = DMA_MINC_ENABLE;\r\n      hdma_rx[DRV_UART_NUM_1].Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;\r\n      hdma_rx[DRV_UART_NUM_1].Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;\r\n      hdma_rx[DRV_UART_NUM_1].Init.Mode                = DMA_CIRCULAR;\r\n      hdma_rx[DRV_UART_NUM_1].Init.Priority            = DMA_PRIORITY_HIGH;\r\n\r\n      HAL_DMA_Init(&hdma_rx[DRV_UART_NUM_1]);\r\n\r\n      /* Associate the initialized DMA handle to the the UART handle */\r\n      __HAL_LINKDMA(huart, hdmarx, hdma_rx[DRV_UART_NUM_1]);\r\n\r\n      // TELL DMA ISR handler the handle to use during ISRs...\r\n      SetDMA2StreamHandlerHandle(2, &hdma_rx[DRV_UART_NUM_1], true, NULL);\r\n \r\n      /* NVIC configuration for DMA transfer complete interrupt (USART6_RX) */\r\n      HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 0, 0);\r\n      HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn);\r\n\r\n\r\n#ifndef DRV_UART_RX_DMA_ONLY\r\n      if(is_uart_mode[DRV_UART_NUM_1] == DRV_UART_DMA_MODE) \r\n#endif\r\n      {\r\n        __HAL_RCC_DMA2_CLK_ENABLE();\r\n        hdma_tx[DRV_UART_NUM_1].Instance                 = DMA2_Stream6;\r\n        hdma_tx[DRV_UART_NUM_1].Init.Channel             = DMA_CHANNEL_5;\r\n        hdma_tx[DRV_UART_NUM_1].Init.Direction           = DMA_MEMORY_TO_PERIPH;\r\n        hdma_tx[DRV_UART_NUM_1].Init.PeriphInc           = DMA_PINC_DISABLE;\r\n        hdma_tx[DRV_UART_NUM_1].Init.MemInc              = DMA_MINC_ENABLE;\r\n        hdma_tx[DRV_UART_NUM_1].Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;\r\n        hdma_tx[DRV_UART_NUM_1].Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;\r\n        hdma_tx[DRV_UART_NUM_1].Init.Mode                = DMA_NORMAL;\r\n        hdma_tx[DRV_UART_NUM_1].Init.Priority            = DMA_PRIORITY_MEDIUM;\r\n\r\n        HAL_DMA_Init(&hdma_tx[DRV_UART_NUM_1]);\r\n\r\n        /* Associate the initialized DMA handle to the the UART handle */\r\n        __HAL_LINKDMA(huart, hdmatx, hdma_tx[DRV_UART_NUM_1]);\r\n\r\n        // TELL DMA ISR handler the handle to use during ISRs...\r\n        is_uart_write_dma_mode[DRV_UART_NUM_1] = SetDMA2StreamHandlerHandle(6, &hdma_tx[DRV_UART_NUM_1], false, NULL);\r\n        if (is_uart_write_dma_mode[DRV_UART_NUM_1])\r\n        {\r\n          /* NVIC configuration for DMA transfer complete interrupt (USART8_RX) */\r\n          HAL_NVIC_SetPriority(DMA2_Stream6_IRQn, 0, 0);\r\n          HAL_NVIC_EnableIRQ(DMA2_Stream6_IRQn);\r\n        }\r\n        else \r\n        {\r\n          vcp_printf(\" Serial1 TX not DMA\\n\");\r\n        }\r\n\r\n      }\r\n    }\r\n    /* Peripheral interrupt init */\r\n    HAL_NVIC_SetPriority(USART6_IRQn, 0, 0);\r\n    HAL_NVIC_EnableIRQ  (USART6_IRQn);\r\n\r\n  }\r\n  else if(huart->Instance==USART2)  // // UART_NUM_2\r\n  {\r\n    RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART2;\r\n    RCC_PeriphCLKInitStruct.Usart2ClockSelection = RCC_USART2CLKSOURCE_SYSCLK;\r\n    HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct);\r\n\r\n    /* Peripheral clock enable */\r\n    __HAL_RCC_USART2_CLK_ENABLE();\r\n    __HAL_RCC_DMA1_CLK_ENABLE();\r\n\r\n    GPIO_InitStruct.Pin       = GPIO_PIN_5;\r\n    GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;\r\n    GPIO_InitStruct.Pull      = GPIO_PULLUP;\r\n    GPIO_InitStruct.Speed     = GPIO_SPEED_HIGH;\r\n    GPIO_InitStruct.Alternate = GPIO_AF7_USART2;\r\n    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);\r\n\r\n\r\n    GPIO_InitStruct.Pin       = GPIO_PIN_6;\r\n    GPIO_InitStruct.Alternate = GPIO_AF7_USART2;\r\n    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);\r\n\r\n\r\n    // DMA Setup\r\n    /* Configure the DMA handler for reception process */\r\n    hdma_rx[DRV_UART_NUM_2].Instance                 = DMA1_Stream5;\r\n    hdma_rx[DRV_UART_NUM_2].Init.Channel             = DMA_CHANNEL_4;\r\n    hdma_rx[DRV_UART_NUM_2].Init.Direction           = DMA_PERIPH_TO_MEMORY;\r\n    hdma_rx[DRV_UART_NUM_2].Init.PeriphInc           = DMA_PINC_DISABLE;\r\n    hdma_rx[DRV_UART_NUM_2].Init.MemInc              = DMA_MINC_ENABLE;\r\n    hdma_rx[DRV_UART_NUM_2].Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;\r\n    hdma_rx[DRV_UART_NUM_2].Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;\r\n    hdma_rx[DRV_UART_NUM_2].Init.Mode                = DMA_CIRCULAR;\r\n    hdma_rx[DRV_UART_NUM_2].Init.Priority            = DMA_PRIORITY_HIGH;\r\n\r\n    HAL_DMA_Init(&hdma_rx[DRV_UART_NUM_2]);\r\n\r\n    /* Associate the initialized DMA handle to the the UART handle */\r\n    __HAL_LINKDMA(huart, hdmarx, hdma_rx[DRV_UART_NUM_2]);\r\n\r\n    // TELL DMA ISR handler the handle to use during ISRs...\r\n    SetDMA1StreamHandlerHandle(5, &hdma_rx[DRV_UART_NUM_2], false, NULL);\r\n\r\n    /* NVIC configuration for DMA transfer complete interrupt (USART6_RX) */\r\n    HAL_NVIC_SetPriority(DMA1_Stream5_IRQn, 0, 0);\r\n    HAL_NVIC_EnableIRQ(DMA1_Stream5_IRQn);\r\n\r\n    if(is_uart_mode[DRV_UART_NUM_2] == DRV_UART_DMA_MODE)\r\n    {\r\n      // TELL DMA ISR handler the handle to use during ISRs...\r\n      // If this fails, than someone else is already holding onto it... So let them keep it.\r\n      is_uart_write_dma_mode[DRV_UART_NUM_2] = SetDMA1StreamHandlerHandle(6, &hdma_tx[DRV_UART_NUM_2], false, &HAL_UART_LoseDMAHandler);\r\n\r\n      if (is_uart_write_dma_mode[DRV_UART_NUM_2])\r\n      {\r\n\r\n        hdma_tx[DRV_UART_NUM_2].Instance                 = DMA1_Stream6;\r\n        hdma_tx[DRV_UART_NUM_2].Init.Channel             = DMA_CHANNEL_4;\r\n        hdma_tx[DRV_UART_NUM_2].Init.Direction           = DMA_MEMORY_TO_PERIPH;\r\n        hdma_tx[DRV_UART_NUM_2].Init.PeriphInc           = DMA_PINC_DISABLE;\r\n        hdma_tx[DRV_UART_NUM_2].Init.MemInc              = DMA_MINC_ENABLE;\r\n        hdma_tx[DRV_UART_NUM_2].Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;\r\n        hdma_tx[DRV_UART_NUM_2].Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;\r\n        hdma_tx[DRV_UART_NUM_2].Init.Mode                = DMA_NORMAL;\r\n        hdma_tx[DRV_UART_NUM_2].Init.Priority            = DMA_PRIORITY_MEDIUM;\r\n\r\n        HAL_DMA_Init(&hdma_tx[DRV_UART_NUM_2]);\r\n\r\n        /* Associate the initialized DMA handle to the the UART handle */\r\n        __HAL_LINKDMA(huart, hdmatx, hdma_tx[DRV_UART_NUM_2]);\r\n\r\n        /* NVIC configuration for DMA transfer complete interrupt (USART3_RX) */\r\n        HAL_NVIC_SetPriority(DMA1_Stream6_IRQn, 0, 0);\r\n        HAL_NVIC_EnableIRQ(DMA1_Stream6_IRQn);\r\n      }\r\n      else \r\n      {\r\n        //vcp_printf(\" Serial2 TX not DMA\\n\");\r\n      }\r\n    }\r\n\r\n    /* Peripheral interrupt init */\r\n    HAL_NVIC_SetPriority(USART2_IRQn, 0, 0);\r\n    HAL_NVIC_EnableIRQ  (USART2_IRQn);\r\n  }\r\n  else if(huart->Instance==USART3)  // // UART_NUM_3\r\n  {\r\n    RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART3;\r\n    RCC_PeriphCLKInitStruct.Usart3ClockSelection = RCC_USART3CLKSOURCE_SYSCLK;\r\n    HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct);\r\n\r\n    /* Peripheral clock enable */\r\n    __HAL_RCC_DMA1_CLK_ENABLE();\r\n    __HAL_RCC_USART3_CLK_ENABLE();\r\n\r\n    GPIO_InitStruct.Pin       = GPIO_PIN_10;\r\n    GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;\r\n    GPIO_InitStruct.Pull      = GPIO_PULLUP;\r\n    GPIO_InitStruct.Speed     = GPIO_SPEED_HIGH;\r\n    GPIO_InitStruct.Alternate = GPIO_AF7_USART3;\r\n    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);\r\n\r\n\r\n    GPIO_InitStruct.Pin       = GPIO_PIN_11;\r\n    GPIO_InitStruct.Alternate = GPIO_AF7_USART3;\r\n    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);\r\n\r\n\r\n    // DMA Setup\r\n    /* Configure the DMA handler for reception process */\r\n    hdma_rx[DRV_UART_NUM_3].Instance                 = DMA1_Stream1;\r\n    hdma_rx[DRV_UART_NUM_3].Init.Channel             = DMA_CHANNEL_4;\r\n    hdma_rx[DRV_UART_NUM_3].Init.Direction           = DMA_PERIPH_TO_MEMORY;\r\n    hdma_rx[DRV_UART_NUM_3].Init.PeriphInc           = DMA_PINC_DISABLE;\r\n    hdma_rx[DRV_UART_NUM_3].Init.MemInc              = DMA_MINC_ENABLE;\r\n    hdma_rx[DRV_UART_NUM_3].Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;\r\n    hdma_rx[DRV_UART_NUM_3].Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;\r\n    hdma_rx[DRV_UART_NUM_3].Init.Mode                = DMA_CIRCULAR;\r\n    hdma_rx[DRV_UART_NUM_3].Init.Priority            = DMA_PRIORITY_HIGH;\r\n\r\n    HAL_DMA_Init(&hdma_rx[DRV_UART_NUM_3]);\r\n\r\n    /* Associate the initialized DMA handle to the the UART handle */\r\n    __HAL_LINKDMA(huart, hdmarx, hdma_rx[DRV_UART_NUM_3]);\r\n\r\n    // TELL DMA ISR handler the handle to use during ISRs...\r\n    SetDMA1StreamHandlerHandle(1, &hdma_rx[DRV_UART_NUM_3], false, NULL);\r\n\r\n    /* NVIC configuration for DMA transfer complete interrupt (USART3_RX) */\r\n    HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 0, 0);\r\n    HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn);\r\n\r\n#ifdef DRV_UART_RX_DMA_ONLY\r\n    if(is_uart_mode[DRV_UART_NUM_3] == DRV_UART_DMA_MODE)\r\n#endif\r\n    {\r\n      hdma_tx[DRV_UART_NUM_3].Instance                 = DMA1_Stream3;\r\n      hdma_tx[DRV_UART_NUM_3].Init.Channel             = DMA_CHANNEL_4;\r\n      hdma_tx[DRV_UART_NUM_3].Init.Direction           = DMA_MEMORY_TO_PERIPH;\r\n      hdma_tx[DRV_UART_NUM_3].Init.PeriphInc           = DMA_PINC_DISABLE;\r\n      hdma_tx[DRV_UART_NUM_3].Init.MemInc              = DMA_MINC_ENABLE;\r\n      hdma_tx[DRV_UART_NUM_3].Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;\r\n      hdma_tx[DRV_UART_NUM_3].Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;\r\n      hdma_tx[DRV_UART_NUM_3].Init.Mode                = DMA_NORMAL;\r\n      hdma_tx[DRV_UART_NUM_3].Init.Priority            = DMA_PRIORITY_MEDIUM;\r\n\r\n      HAL_DMA_Init(&hdma_tx[DRV_UART_NUM_3]);\r\n\r\n      /* Associate the initialized DMA handle to the the UART handle */\r\n      __HAL_LINKDMA(huart, hdmatx, hdma_tx[DRV_UART_NUM_3]);\r\n\r\n      // TELL DMA ISR handler the handle to use during ISRs...\r\n      is_uart_write_dma_mode[DRV_UART_NUM_3] = SetDMA1StreamHandlerHandle(3, &hdma_tx[DRV_UART_NUM_3], false, &HAL_UART_LoseDMAHandler);\r\n      if (is_uart_write_dma_mode[DRV_UART_NUM_3])\r\n      {\r\n        /* NVIC configuration for DMA transfer complete interrupt (USART3_RX) */\r\n        HAL_NVIC_SetPriority(DMA1_Stream3_IRQn, 0, 0);\r\n        HAL_NVIC_EnableIRQ(DMA1_Stream3_IRQn);\r\n      }\r\n      else \r\n      {\r\n        //vcp_printf(\" Serial3 TX not DMA\\n\");\r\n      }\r\n    }\r\n\r\n    /* Peripheral interrupt init */\r\n    HAL_NVIC_SetPriority(USART3_IRQn, 0, 0);\r\n    HAL_NVIC_EnableIRQ  (USART3_IRQn);\r\n  }\r\n  else if(huart->Instance==UART8) // // UART_NUM_4\r\n  {\r\n    RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART8;\r\n    RCC_PeriphCLKInitStruct.Uart8ClockSelection  = RCC_UART8CLKSOURCE_SYSCLK;\r\n    HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct);\r\n\r\n    /* Peripheral clock enable */\r\n    __HAL_RCC_UART8_CLK_ENABLE();\r\n\r\n    GPIO_InitStruct.Pin       = GPIO_PIN_1;\r\n    GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;\r\n    GPIO_InitStruct.Pull      = GPIO_PULLUP;\r\n    GPIO_InitStruct.Speed     = GPIO_SPEED_HIGH;\r\n    GPIO_InitStruct.Alternate = GPIO_AF8_UART8;\r\n    HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);\r\n\r\n\r\n    GPIO_InitStruct.Pin       = GPIO_PIN_0;\r\n    GPIO_InitStruct.Alternate = GPIO_AF8_UART8;\r\n    HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);\r\n\r\n#ifdef DRV_UART_RX_DMA_ONLY\r\n    if(is_uart_mode[DRV_UART_NUM_4] == DRV_UART_DMA_MODE) \r\n#endif\r\n    {\r\n      // DMA Setup\r\n      /* Configure the DMA handler for reception process */\r\n      __HAL_RCC_DMA1_CLK_ENABLE();\r\n      hdma_rx[DRV_UART_NUM_4].Instance                 = DMA1_Stream6;\r\n      hdma_rx[DRV_UART_NUM_4].Init.Channel             = DMA_CHANNEL_5;\r\n      hdma_rx[DRV_UART_NUM_4].Init.Direction           = DMA_PERIPH_TO_MEMORY;\r\n      hdma_rx[DRV_UART_NUM_4].Init.PeriphInc           = DMA_PINC_DISABLE;\r\n      hdma_rx[DRV_UART_NUM_4].Init.MemInc              = DMA_MINC_ENABLE;\r\n      hdma_rx[DRV_UART_NUM_4].Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;\r\n      hdma_rx[DRV_UART_NUM_4].Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;\r\n      hdma_rx[DRV_UART_NUM_4].Init.Mode                = DMA_CIRCULAR;\r\n      hdma_rx[DRV_UART_NUM_4].Init.Priority            = DMA_PRIORITY_HIGH;\r\n\r\n      HAL_DMA_Init(&hdma_rx[DRV_UART_NUM_4]);\r\n\r\n      /* Associate the initialized DMA handle to the the UART handle */\r\n      __HAL_LINKDMA(huart, hdmarx, hdma_rx[DRV_UART_NUM_4]);\r\n\r\n      // TELL DMA ISR handler the handle to use during ISRs...\r\n      SetDMA1StreamHandlerHandle(6, &hdma_rx[DRV_UART_NUM_4], true, NULL);\r\n \r\n      /* NVIC configuration for DMA transfer complete interrupt (USART3_RX) */\r\n      HAL_NVIC_SetPriority(DMA1_Stream6_IRQn, 0, 0);\r\n      HAL_NVIC_EnableIRQ(DMA1_Stream6_IRQn);\r\n\r\n#ifndef DRV_UART_RX_DMA_ONLY\r\n      if(is_uart_mode[DRV_UART_NUM_4] == DRV_UART_DMA_MODE) \r\n#endif\r\n      {\r\n        hdma_tx[DRV_UART_NUM_4].Instance                 = DMA1_Stream0;\r\n        hdma_tx[DRV_UART_NUM_4].Init.Channel             = DMA_CHANNEL_5;\r\n        hdma_tx[DRV_UART_NUM_4].Init.Direction           = DMA_MEMORY_TO_PERIPH;\r\n        hdma_tx[DRV_UART_NUM_4].Init.PeriphInc           = DMA_PINC_DISABLE;\r\n        hdma_tx[DRV_UART_NUM_4].Init.MemInc              = DMA_MINC_ENABLE;\r\n        hdma_tx[DRV_UART_NUM_4].Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;\r\n        hdma_tx[DRV_UART_NUM_4].Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;\r\n        hdma_tx[DRV_UART_NUM_4].Init.Mode                = DMA_NORMAL;\r\n        hdma_tx[DRV_UART_NUM_4].Init.Priority            = DMA_PRIORITY_MEDIUM;\r\n\r\n        HAL_DMA_Init(&hdma_tx[DRV_UART_NUM_4]);\r\n\r\n        /* Associate the initialized DMA handle to the the UART handle */\r\n        __HAL_LINKDMA(huart, hdmatx, hdma_tx[DRV_UART_NUM_4]);\r\n\r\n        // TELL DMA ISR handler the handle to use during ISRs...\r\n        is_uart_write_dma_mode[DRV_UART_NUM_4] = SetDMA1StreamHandlerHandle(0, &hdma_tx[DRV_UART_NUM_4], false, &HAL_UART_LoseDMAHandler);\r\n        if (is_uart_write_dma_mode[DRV_UART_NUM_4])\r\n        {\r\n          /* NVIC configuration for DMA transfer complete interrupt (USART3_RX) */\r\n          HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 0, 0);\r\n          HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn);\r\n        }\r\n        else \r\n        {\r\n          //vcp_printf(\" Serial4 TX not DMA\\n\");\r\n        }\r\n      }\r\n\r\n    }\r\n\r\n\r\n\r\n    /* Peripheral interrupt init */\r\n    HAL_NVIC_SetPriority(UART8_IRQn, 0, 0);\r\n    HAL_NVIC_EnableIRQ  (UART8_IRQn);\r\n\r\n  }\r\n\r\n}\r\n\r\n\r\nvoid HAL_UART_MspDeInit(UART_HandleTypeDef* huart)\r\n{\r\n\r\n  if(huart->Instance==USART2)\r\n  {\r\n    __USART2_FORCE_RESET();\r\n    __USART2_RELEASE_RESET();\r\n\r\n    /* Peripheral clock disable */\r\n    __HAL_RCC_USART2_CLK_DISABLE();\r\n\r\n\r\n    HAL_GPIO_DeInit(GPIOD, GPIO_PIN_5);\r\n    HAL_GPIO_DeInit(GPIOD, GPIO_PIN_6);\r\n\r\n    /* Peripheral interrupt Deinit*/\r\n    HAL_NVIC_DisableIRQ(USART2_IRQn);\r\n    HAL_NVIC_DisableIRQ(DMA1_Stream5_IRQn);\r\n  }\r\n  else if(huart->Instance==USART6)\r\n  {\r\n    __USART6_FORCE_RESET();\r\n    __USART6_RELEASE_RESET();\r\n\r\n    /* Peripheral clock disable */\r\n    __HAL_RCC_USART6_CLK_DISABLE();\r\n\r\n\r\n    HAL_GPIO_DeInit(GPIOC, GPIO_PIN_6);\r\n    HAL_GPIO_DeInit(GPIOC, GPIO_PIN_7);\r\n\r\n    /* Peripheral interrupt Deinit*/\r\n    HAL_NVIC_DisableIRQ(USART6_IRQn);\r\n  }\r\n  else if(huart->Instance==USART3)\r\n  {\r\n    __USART3_FORCE_RESET();\r\n    __USART3_RELEASE_RESET();\r\n\r\n    /* Peripheral clock disable */\r\n    __HAL_RCC_USART3_CLK_DISABLE();\r\n\r\n\r\n    HAL_GPIO_DeInit(GPIOC, GPIO_PIN_10);\r\n    HAL_GPIO_DeInit(GPIOC, GPIO_PIN_11);\r\n\r\n    /* Peripheral interrupt Deinit*/\r\n    HAL_NVIC_DisableIRQ(USART3_IRQn);\r\n  }\r\n  else if(huart->Instance==UART8)\r\n  {\r\n    __UART8_FORCE_RESET();\r\n    __UART8_RELEASE_RESET();\r\n\r\n    /* Peripheral clock disable */\r\n    __HAL_RCC_UART8_CLK_DISABLE();\r\n\r\n\r\n    HAL_GPIO_DeInit(GPIOE, GPIO_PIN_0);\r\n    HAL_GPIO_DeInit(GPIOE, GPIO_PIN_1);\r\n\r\n    /* Peripheral interrupt Deinit*/\r\n    HAL_NVIC_DisableIRQ(UART8_IRQn);\r\n  }\r\n\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/drv_uart.h",
    "content": "/*\n *  drv_uart.h\n *\n *  Created on: 2016. 7.13.\n *      Author: Baram, PBHP\n */\n\n#ifndef DRV_UART_H\n#define DRV_UART_H\n\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n\n#include \"def.h\"\n#include \"bsp.h\"\n\n\n\n\n\n#define DRV_UART_NUM_1          0\n#define DRV_UART_NUM_2          1\n#define DRV_UART_NUM_3          2\n#define DRV_UART_NUM_4          3\n#define DRV_UART_NUM_MAX        4\n\n#define DRV_UART_IRQ_MODE       0\n#define DRV_UART_DMA_MODE       1\n\n//#define DRV_UART_RX_DMA_ONLY\t1  \n\nint      drv_uart_init();\nvoid     drv_uart_begin(uint8_t uart_num, uint8_t uart_mode, uint32_t baudrate);\nuint32_t drv_uart_write(uint8_t uart_num, const uint8_t wr_data);\nuint32_t drv_uart_write_dma_it(uint8_t uart_num, const uint8_t *wr_data, uint16_t Size);\nvoid     drv_uart_flush(uint8_t uart_num);\nvoid     drv_uart_rx_flush(uint8_t uart_num, uint32_t timeout_ms);\nvoid     drv_uart_start_rx(uint8_t uart_num);\nuint32_t drv_uart_read_buf(uint8_t uart_num, uint8_t *p_buf, uint32_t length);\nuint8_t  drv_uart_get_mode(uint8_t uart_num);\nuint32_t drv_uart_available(uint8_t uart_num);\nint      drv_uart_read(uint8_t uart_num);\nint      drv_uart_peek(uint8_t uart_num);\n\n#ifdef __cplusplus\n}\n#endif\n\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/flash.c",
    "content": "/*\n *  flash.h\n *\n *  Created on: 2016. 5. 14.\n *      Author: Baram, PBHP\n */\n\n#include \"flash.h\"\n\n\n\n//static void               FLASH_MassErase(uint8_t VoltageRange);\n\nvoid flash_init()\n{\n\n}\n\n\nerr_code_t flash_write(uint32_t addr, uint8_t *p_data, uint32_t length)\n{\n  err_code_t err_code = ERR_NONE;\n  HAL_StatusTypeDef HAL_FLASHStatus = HAL_OK;\n  uint32_t StartAddress = addr;\n  uint32_t WriteSize;\n  uint32_t WriteData;\n  uint32_t i;\n  uint32_t DataIndex;\n\n\n  WriteSize = length / 4; // 32Bit\n\n  if( (WriteSize%4) > 0 ) WriteSize++;\n\n  DataIndex = 0;\n  HAL_FLASH_Unlock();\n  for( i=0; i<WriteSize; i++ )\n  {\n    WriteData  = p_data[ DataIndex++ ] << 0;\n    WriteData |= p_data[ DataIndex++ ] << 8;\n    WriteData |= p_data[ DataIndex++ ] << 16;\n    WriteData |= p_data[ DataIndex++ ] << 24;\n\n    HAL_FLASHStatus = HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, StartAddress+i*4, (uint64_t)WriteData);\n\n    if( HAL_FLASHStatus != HAL_OK )\n    {\n        err_code = ERR_FLASH_WRITE;\n      break;\n    }\n  }\n  HAL_FLASH_Lock();\n\n  return err_code;\n}\n\n\nerr_code_t flash_read(uint32_t addr, uint8_t *p_data, uint32_t length)\n{\n  err_code_t err_code = ERR_NONE;\n  uint32_t Dataindex;\n  uint32_t addr_cnt;\n\n\n  Dataindex = 0;\n  for (addr_cnt=0;addr_cnt<length;addr_cnt++)\n  {\n    p_data[Dataindex++] = *(volatile uint8_t*)(addr+addr_cnt);\n  }\n\n  return err_code;\n}\n\n\nerr_code_t flash_erase_whole_sectors(void)\n{\n\n  err_code_t err_code = ERR_NONE;\n  HAL_StatusTypeDef HAL_FLASHStatus = HAL_OK;\n\n  HAL_FLASH_Unlock();\n\n  //HAL_FLASHStatus = FLASH_MassErase(FLASH_VOLTAGE_RANGE_3);\n  if(HAL_FLASHStatus != HAL_OK)\n  {\n    err_code = ERR_FLASH_ERASE;\n  }\n\n  HAL_FLASH_Lock();\n\n  return err_code;\n}\n\nerr_code_t flash_erase_fw_block( uint32_t length )\n{\n\n  err_code_t err_code = ERR_NONE;\n  HAL_StatusTypeDef HAL_FLASHStatus = HAL_OK;\n  FLASH_EraseInitTypeDef pEraseInit;\n  uint32_t SectorError;\n  uint32_t sector_cnt;\n\n\n  sector_cnt = length/(256*1024);\n  if( length%(256*1024) > 0 )\n  {\n    sector_cnt++;\n  }\n  if( sector_cnt > (FLASH_SECTOR_TOTAL-FLASH_SECTOR_5) )\n  {\n    sector_cnt = (FLASH_SECTOR_TOTAL-FLASH_SECTOR_5);\n  }\n\n  //except user bootloader sectors\n  pEraseInit.TypeErase = FLASH_TYPEERASE_SECTORS;\n  pEraseInit.VoltageRange = FLASH_VOLTAGE_RANGE_3;\n  pEraseInit.Sector = FLASH_SECTOR_5;\n  pEraseInit.NbSectors = sector_cnt;\n\n  HAL_FLASH_Unlock();\n\n  HAL_FLASHStatus = HAL_FLASHEx_Erase(&pEraseInit, &SectorError);\n  if(HAL_FLASHStatus != HAL_OK)\n  {\n    err_code = ERR_FLASH_ERASE;\n  }\n\n  HAL_FLASH_Lock();\n\n  return err_code;\n}\n\n\nerr_code_t flash_erase_sector(uint32_t sector)\n{\n  err_code_t err_code = ERR_NONE;\n  HAL_StatusTypeDef HAL_FLASHStatus = HAL_OK;\n  FLASH_EraseInitTypeDef pEraseInit;\n  uint32_t SectorError;\n\n  pEraseInit.TypeErase = FLASH_TYPEERASE_SECTORS;\n  pEraseInit.VoltageRange = FLASH_VOLTAGE_RANGE_3;\n  pEraseInit.Sector = sector;\n  pEraseInit.NbSectors = 1;\n\n  HAL_FLASH_Unlock();\n\n  HAL_FLASHStatus = HAL_FLASHEx_Erase(&pEraseInit, &SectorError);\n  if(HAL_FLASHStatus != HAL_OK)\n  {\n    err_code = ERR_FLASH_ERASE;\n  }\n\n  HAL_FLASH_Lock();\n\n  return err_code;\n}\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/flash.h",
    "content": "/*\n *  flash.h\n *\n *  Created on: 2016. 5. 14.\n *      Author: Baram, PBHP\n */\n\n#ifndef FLASH_H\n#define FLASH_H\n\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n\n#include \"def.h\"\n#include \"bsp.h\"\n\n\n\n\n\n\n\n\n\nvoid flash_init(void);\n\nerr_code_t flash_write(uint32_t addr, uint8_t *p_data, uint32_t length);\nerr_code_t flash_read(uint32_t addr, uint8_t *p_data, uint32_t length);\nerr_code_t flash_erase_whole_sectors(void);\nerr_code_t flash_erase_sector(uint32_t sector);\nerr_code_t flash_erase_fw_block(uint32_t length);\n\n\n#ifdef __cplusplus\n}\n#endif\n\n\n#endif\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/ring.c",
    "content": "/*\n * ring.c\n *\n *  Created on: 2017. 8. 21.\n *      Author: HanCheol Cho\n */\n#include <stdlib.h>\n\n#include \"def.h\"\n#include \"def_err.h\"\n#include \"ring.h\"\n\n\n\n\n//-- Internal Variables\n//\n\n\n//-- External Variables\n//\n\n\n//-- Internal Functions\n//\n\n\n//-- External Functions\n//\n\n\n\n\n\nbool ringInit(void)\n{\n\n  return true;\n}\n\nerr_code_t ringCreate(ring_node_t *p_node, uint32_t length)\n{\n  err_code_t err_code = ERR_NONE;\n\n\n  p_node->ptr_in  = 0;\n  p_node->ptr_out = 0;\n  p_node->length  = length;\n\n  return err_code;\n}\n\nuint32_t ringReadAvailable(ring_node_t *p_node)\n{\n  uint32_t length;\n\n\n  length = (p_node->length + p_node->ptr_in - p_node->ptr_out) % p_node->length;\n\n  return length;\n}\n\nuint32_t ringWriteAvailable(ring_node_t *p_node)\n{\n  uint32_t length;\n  uint32_t read_length;\n\n  read_length = ringReadAvailable(p_node);\n\n  length = p_node->length - read_length - 1;\n\n  return length;\n}\n\nuint32_t ringGetWriteIndex(ring_node_t *p_node)\n{\n  return p_node->ptr_in;\n}\n\nerr_code_t ringWriteUpdate(ring_node_t *p_node)\n{\n  err_code_t err_code = ERR_NONE;\n  uint32_t next_index;\n\n\n  next_index = p_node->ptr_in + 1;\n\n  if (next_index == p_node->length)\n  {\n    next_index = 0;\n  }\n\n  if (next_index != p_node->ptr_out)\n  {\n    p_node->ptr_in = next_index;\n  }\n  else\n  {\n    //err_code = ERR_FULL;\n    ringReadUpdate(p_node);\n    p_node->ptr_in = next_index;\n  }\n\n  return err_code;\n}\n\nerr_code_t ringReadUpdate(ring_node_t *p_node)\n{\n  err_code_t err_code = ERR_NONE;\n  uint32_t index;\n  uint32_t next_index;\n\n\n  index      = p_node->ptr_out;\n  next_index = p_node->ptr_out + 1;\n\n  if (next_index == p_node->length)\n  {\n    next_index = 0;\n  }\n\n  if (index != p_node->ptr_in)\n  {\n    p_node->ptr_out = next_index;\n  }\n  else\n  {\n    err_code = ERR_EMPTY;\n  }\n\n  return err_code;\n}\n\nuint32_t ringGetReadIndex(ring_node_t *p_node)\n{\n  return p_node->ptr_out;\n}\n\nuint32_t ringGetReadOffsetIndex(ring_node_t *p_node, uint32_t offset)\n{\n  uint32_t index;\n\n\n  index = (p_node->length + p_node->ptr_out + offset) % p_node->length;\n\n  return index;\n}\n\nerr_code_t ringFlush(ring_node_t *p_node)\n{\n  err_code_t err_code = ERR_NONE;\n\n  p_node->ptr_in  = 0;\n  p_node->ptr_out = 0;\n\n  return err_code;\n}\n\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/ring.h",
    "content": "/*\n * ring.h\n *\n *  Created on: 2017. 8. 21.\n *      Author: HanCheol Cho\n */\n\n#ifndef RING_H_\n#define RING_H_\n\n\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n\n#include \"def.h\"\n\n\ntypedef struct\n{\n  err_code_t err_code;\n  uint32_t   ptr_in;\n  uint32_t   ptr_out;\n  uint32_t   length;\n} ring_node_t;\n\n\n\nbool ringInit(void);\n\nerr_code_t ringCreate(ring_node_t *p_node, uint32_t length);\n\nerr_code_t ringWriteUpdate(ring_node_t *p_node);\nuint32_t   ringWriteAvailable(ring_node_t *p_node);\nuint32_t   ringGetWriteIndex(ring_node_t *p_node);\n\nerr_code_t ringReadUpdate(ring_node_t *p_node);\nuint32_t   ringReadAvailable(ring_node_t *p_node);\nuint32_t   ringGetReadIndex(ring_node_t *p_node);\nuint32_t   ringGetReadOffsetIndex(ring_node_t *p_node, uint32_t offset);\n\nerr_code_t ringFlush(ring_node_t *p_node);\n\n#ifdef __cplusplus\n}\n#endif\n\n\n\n#endif /* RING_H_ */\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/vcp.c",
    "content": "/*\r\n *  vcp.c\r\n *\r\n *  virtual_com_port\r\n *\r\n *  Created on: 2016. 5. 14.\r\n *      Author: Baram, PBHP\r\n */\r\n\r\n#include \"vcp.h\"\r\n#include <math.h>\r\n#include <string.h>\r\n#include <stdarg.h>\r\n#include <stdio.h>\r\n\r\n#include \"hw.h\"\r\n#include \"usbd_cdc_interface.h\"\r\n\r\n\r\nextern uint32_t usb_cdc_debug_cnt[];\r\n\r\n\r\nvoid vcp_init(void)\r\n{\r\n\r\n}\r\n\r\n\r\nuint32_t vcp_is_available(void)\r\n{\r\n  return CDC_Itf_Available();\r\n}\r\n\r\n\r\nint32_t vcp_peek(void)\r\n{\r\n  return CDC_Itf_Peek();\r\n}\r\n\r\n\r\nBOOL vcp_is_connected(void)\r\n{\r\n  return CDC_Itf_IsConnected();\r\n}\r\n\r\n\r\nvoid vcp_putch(uint8_t ch)\r\n{\r\n  CDC_Itf_Write( &ch, 1 );\r\n}\r\n\r\n\r\nuint8_t vcp_getch(void)\r\n{\r\n#if 1\r\n  return CDC_Itf_Getch();\r\n#else\r\n  /* for debugging */\r\n  uint8_t ch = CDC_Itf_Getch();\r\n  drv_uart_write(DRV_UART_NUM_4, ch);\r\n  return ch;\r\n#endif\r\n}\r\n\r\n\r\nint32_t vcp_write(uint8_t *p_data, uint32_t length)\r\n{\r\n  int32_t  ret;\r\n\r\n  #if 1\r\n  uint32_t t_time;\r\n\r\n  t_time = millis();\r\n  while(1)\r\n  {\r\n    ret = CDC_Itf_Write( p_data, length );\r\n\r\n    if(ret < 0)\r\n    {\r\n      ret = 0;\r\n      break;\r\n    }\r\n    if(ret == (int32_t) length)\r\n    {\r\n      break;\r\n    }\r\n    if(millis()-t_time > 100)\r\n    {\r\n      usb_cdc_debug_cnt[1]++;\r\n      ret = 0;\r\n      break;\r\n    }\r\n  }\r\n  #else\r\n  ret = CDC_Itf_Write( p_data, length );\r\n\r\n\r\n  if(ret < 0)\r\n  {\r\n    ret = 0;\r\n  }\r\n  #endif\r\n  return ret;\r\n}\r\n\r\n\r\nint32_t vcp_printf( const char *fmt, ...)\r\n{\r\n  int32_t ret = 0;\r\n  va_list arg;\r\n  va_start (arg, fmt);\r\n  int32_t len;\r\n  static char print_buffer[255];\r\n\r\n  len = vsnprintf(print_buffer, 255, fmt, arg);\r\n  va_end (arg);\r\n\r\n\r\n  ret = vcp_write( (uint8_t *) print_buffer, len);\r\n\r\n  return ret;\r\n}\r\n\r\n\r\nBOOL vcp_is_transmitted( void )\r\n{\r\n  return CDC_Itf_IsTxTransmitted();\r\n}"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/vcp.h",
    "content": "/*\n *  vcp.h\n *\n *  virtual_com_port\n *\n *  Created on: 2016. 5. 14.\n *      Author: Baram, PBHP\n */\n\n#ifndef VCP_H\n#define VCP_H\n\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n\n#include \"def.h\"\n#include \"bsp.h\"\n\n\nvoid     vcp_init(void);\nuint32_t vcp_is_available(void);\nint32_t  vcp_peek(void);\nBOOL     vcp_is_connected(void);\nvoid     vcp_putch(uint8_t ch);\nuint8_t  vcp_getch(void);\nint32_t  vcp_write(uint8_t *p_data, uint32_t length);\n\nint32_t  vcp_printf( const char *fmt, ...);\n\nBOOL     vcp_is_transmitted(void);\n\n#ifdef __cplusplus\n}\n#endif\n\n\n#endif\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/wdg.c",
    "content": "/*\r\n *  wdg.c\r\n *\r\n *  Created on: 2016. 7. 7.\r\n *      Author: Baram, PBHP\r\n */\r\n\r\n#include \"wdg.h\"\r\n\r\n\r\n\r\nstatic IWDG_HandleTypeDef IwdgHandle;\r\nstatic BOOL is_setup = FALSE;\r\n\r\n\r\nvoid wdg_init()\r\n{\r\n}\r\n\r\nBOOL wdg_setup(uint32_t reload_time)\r\n{\r\n\r\n  IwdgHandle.Instance \t    = IWDG;\r\n  IwdgHandle.Init.Prescaler = IWDG_PRESCALER_32; // 32Khz/32 = 1Khz(1ms)\r\n  IwdgHandle.Init.Reload    = reload_time;\r\n  IwdgHandle.Init.Window    = IWDG_WINDOW_DISABLE;\r\n\r\n  if (HAL_IWDG_Init(&IwdgHandle) != HAL_OK)\r\n  {\r\n    return FALSE;\r\n  }\r\n\r\n  is_setup = TRUE;\r\n\r\n  return TRUE;\r\n}\r\n\r\nBOOL wdg_start(void)\r\n{\r\n  if (HAL_IWDG_Init(&IwdgHandle) != HAL_OK)\r\n  {\r\n    return FALSE;\r\n  }\r\n\r\n  return TRUE;\r\n}\r\n\r\nBOOL wdg_refresh(void)\r\n{\r\n  if(is_setup == FALSE)\r\n  {\r\n    return FALSE;\r\n  }\r\n\r\n  if(HAL_IWDG_Refresh(&IwdgHandle) != HAL_OK)\r\n  {\r\n    return FALSE;\r\n  }\r\n\r\n  return TRUE;\r\n}\r\n\r\nBOOL wdg_get_reset(void)\r\n{\r\n\r\n  if (__HAL_RCC_GET_FLAG(RCC_FLAG_IWDGRST) != RESET)\r\n  {\r\n    // IWDGRST flag set\r\n    // Clear reset flags\r\n    __HAL_RCC_CLEAR_RESET_FLAGS();\r\n\r\n    return TRUE;\r\n  }\r\n  else\r\n  {\r\n    // IWDGRST flag is not set\r\n    return FALSE;\r\n  }\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/driver/wdg.h",
    "content": "/*\n *  wdg.h\n *\n *  Created on: 2016. 7. 8.\n *      Author: Baram, PBHP\n */\n\n#ifndef WDG_H\n#define WDG_H\n\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n\n#include \"def.h\"\n#include \"bsp.h\"\n\n\nvoid wdg_init(void);\nBOOL wdg_setup(uint32_t reload_time);\nBOOL wdg_start(void);\nBOOL wdg_refresh(void);\nBOOL wdg_get_reset(void);\n\n#ifdef __cplusplus\n}\n#endif\n\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/hw.c",
    "content": "/*\n *  drv.c\n *\n *  Created on: 2016. 7. 13.\n *      Author: Baram, PBHP\n */\n\n#include \"hw.h\"\n#include \"variant.h\"\n\n\n\n\n\nvoid hw_init(void)\n{\n  drv_adc_init();\n  drv_spi_init();\n  drv_micros_init();\n  drv_uart_init();\n  drv_pwm_init();\n  drv_timer_init();\n  drv_i2c_init();\n  drv_exti_init();\n  drv_dxl_init();\n  drv_eeprom_init();\n  drv_rtc_init();\n  \n  drvCanInit();\n\n  flash_init();\n  vcp_init();\n  wdg_init();\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/hw.h",
    "content": "/*\n *  hw.h\n *\n *  Created on: 2016. 5. 14.\n *      Author: Baram, PBHP\n */\n\n#ifndef HW_H\n#define DRV_H\n\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n\n#include \"def.h\"\n#include \"bsp.h\"\n\n\n#include \"drv_adc.h\"\n#include \"drv_pwm.h\"\n#include \"drv_spi.h\"\n#include \"drv_uart.h\"\n#include \"drv_i2c.h\"\n#include \"drv_exti.h\"\n#include \"drv_dxl.h\"\n#include \"drv_timer.h\"\n#include \"drv_eeprom.h\"\n#include \"drv_rtc.h\"\n#include \"drv_micros.h\"\n#include \"drv_can.h\"\n\n#include \"delay.h\"\n#include \"flash.h\"\n#include \"vcp.h\"\n#include \"wdg.h\"\n\n\n\nvoid hw_init(void);\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/usb_cdc/usbd_cdc.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_cdc.c\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   This file provides the high layer firmware functions to manage the\r\n  *          following functionalities of the USB CDC Class:\r\n  *           - Initialization and Configuration of high and low layer\r\n  *           - Enumeration as CDC Device (and enumeration for each implemented memory interface)\r\n  *           - OUT/IN data transfer\r\n  *           - Command IN transfer (class requests management)\r\n  *           - Error management\r\n  *\r\n  *  @verbatim\r\n  *\r\n  *          ===================================================================\r\n  *                                CDC Class Driver Description\r\n  *          ===================================================================\r\n  *           This driver manages the \"Universal Serial Bus Class Definitions for Communications Devices\r\n  *           Revision 1.2 November 16, 2007\" and the sub-protocol specification of \"Universal Serial Bus\r\n  *           Communications Class Subclass Specification for PSTN Devices Revision 1.2 February 9, 2007\"\r\n  *           This driver implements the following aspects of the specification:\r\n  *             - Device descriptor management\r\n  *             - Configuration descriptor management\r\n  *             - Enumeration as CDC device with 2 data endpoints (IN and OUT) and 1 command endpoint (IN)\r\n  *             - Requests management (as described in section 6.2 in specification)\r\n  *             - Abstract Control Model compliant\r\n  *             - Union Functional collection (using 1 IN endpoint for control)\r\n  *             - Data interface class\r\n  *\r\n  *           These aspects may be enriched or modified for a specific user application.\r\n  *\r\n  *            This driver doesn't implement the following aspects of the specification\r\n  *            (but it is possible to manage these features with some modifications on this driver):\r\n  *             - Any class-specific aspect relative to communication classes should be managed by user application.\r\n  *             - All communication classes other than PSTN are not managed\r\n  *\r\n  *  @endverbatim\r\n  *\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software\r\n  * distributed under the License is distributed on an \"AS IS\" BASIS,\r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_cdc.h\"\r\n#include \"usbd_desc.h\"\r\n#include \"usbd_ctlreq.h\"\r\n\r\n\r\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n\r\n\r\n/** @defgroup USBD_CDC\r\n  * @brief usbd core module\r\n  * @{\r\n  */\r\n\r\n/** @defgroup USBD_CDC_Private_TypesDefinitions\r\n  * @{\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup USBD_CDC_Private_Defines\r\n  * @{\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup USBD_CDC_Private_Macros\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup USBD_CDC_Private_FunctionPrototypes\r\n  * @{\r\n  */\r\n\r\n\r\nstatic uint8_t  USBD_CDC_Init (USBD_HandleTypeDef *pdev,\r\n                               uint8_t cfgidx);\r\n\r\nstatic uint8_t  USBD_CDC_DeInit (USBD_HandleTypeDef *pdev,\r\n                                 uint8_t cfgidx);\r\n\r\nstatic uint8_t  USBD_CDC_Setup (USBD_HandleTypeDef *pdev,\r\n                                USBD_SetupReqTypedef *req);\r\n\r\nstatic uint8_t  USBD_CDC_DataIn (USBD_HandleTypeDef *pdev,\r\n                                 uint8_t epnum);\r\n\r\nstatic uint8_t  USBD_CDC_DataOut (USBD_HandleTypeDef *pdev,\r\n                                 uint8_t epnum);\r\n\r\nstatic uint8_t  USBD_CDC_EP0_RxReady (USBD_HandleTypeDef *pdev);\r\n\r\nstatic uint8_t  *USBD_CDC_GetFSCfgDesc (uint16_t *length);\r\n\r\nstatic uint8_t  *USBD_CDC_GetHSCfgDesc (uint16_t *length);\r\n\r\nstatic uint8_t  *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length);\r\n\r\nstatic uint8_t  *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length);\r\n\r\nuint8_t  *USBD_CDC_GetDeviceQualifierDescriptor (uint16_t *length);\r\n\r\n/* USB Standard Device Descriptor */\r\n__ALIGN_BEGIN static uint8_t USBD_CDC_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END =\r\n{\r\n  USB_LEN_DEV_QUALIFIER_DESC,\r\n  USB_DESC_TYPE_DEVICE_QUALIFIER,\r\n  0x00,\r\n  0x02,\r\n  0x00,\r\n  0x00,\r\n  0x00,\r\n  0x40,\r\n  0x01,\r\n  0x00,\r\n};\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USBD_CDC_Private_Variables\r\n  * @{\r\n  */\r\n\r\n\r\n/* CDC interface class callbacks structure */\r\nUSBD_ClassTypeDef  USBD_CDC =\r\n{\r\n  USBD_CDC_Init,\r\n  USBD_CDC_DeInit,\r\n  USBD_CDC_Setup,\r\n  NULL,                 /* EP0_TxSent, */\r\n  USBD_CDC_EP0_RxReady,\r\n  USBD_CDC_DataIn,\r\n  USBD_CDC_DataOut,\r\n  NULL,\r\n  NULL,\r\n  NULL,\r\n  USBD_CDC_GetHSCfgDesc,\r\n  USBD_CDC_GetFSCfgDesc,\r\n  USBD_CDC_GetOtherSpeedCfgDesc,\r\n  USBD_CDC_GetDeviceQualifierDescriptor,\r\n};\r\n\r\n/* USB CDC device Configuration Descriptor */\r\n__ALIGN_BEGIN uint8_t USBD_CDC_CfgHSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END =\r\n{\r\n  /*Configuration Descriptor*/\r\n  0x09,   /* bLength: Configuration Descriptor size */\r\n  USB_DESC_TYPE_CONFIGURATION,      /* bDescriptorType: Configuration */\r\n  USB_CDC_CONFIG_DESC_SIZ,                /* wTotalLength:no of returned bytes */\r\n  0x00,\r\n  0x02,   /* bNumInterfaces: 2 interface */\r\n  0x01,   /* bConfigurationValue: Configuration value */\r\n  0x00,   /* iConfiguration: Index of string descriptor describing the configuration */\r\n  0xC0,   /* bmAttributes: self powered */\r\n  0x32,   /* MaxPower 0 mA */\r\n\r\n  /*---------------------------------------------------------------------------*/\r\n\r\n  /*Interface Descriptor */\r\n  0x09,   /* bLength: Interface Descriptor size */\r\n  USB_DESC_TYPE_INTERFACE,  /* bDescriptorType: Interface */\r\n  /* Interface descriptor type */\r\n  0x00,   /* bInterfaceNumber: Number of Interface */\r\n  0x00,   /* bAlternateSetting: Alternate setting */\r\n  0x01,   /* bNumEndpoints: One endpoints used */\r\n  0x02,   /* bInterfaceClass: Communication Interface Class */\r\n  0x02,   /* bInterfaceSubClass: Abstract Control Model */\r\n  0x01,   /* bInterfaceProtocol: Common AT commands */\r\n  0x00,   /* iInterface: */\r\n\r\n  /*Header Functional Descriptor*/\r\n  0x05,   /* bLength: Endpoint Descriptor size */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x00,   /* bDescriptorSubtype: Header Func Desc */\r\n  0x10,   /* bcdCDC: spec release number */\r\n  0x01,\r\n\r\n  /*Call Management Functional Descriptor*/\r\n  0x05,   /* bFunctionLength */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x01,   /* bDescriptorSubtype: Call Management Func Desc */\r\n  0x00,   /* bmCapabilities: D0+D1 */\r\n  0x01,   /* bDataInterface: 1 */\r\n\r\n  /*ACM Functional Descriptor*/\r\n  0x04,   /* bFunctionLength */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x02,   /* bDescriptorSubtype: Abstract Control Management desc */\r\n  0x02,   /* bmCapabilities */\r\n\r\n  /*Union Functional Descriptor*/\r\n  0x05,   /* bFunctionLength */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x06,   /* bDescriptorSubtype: Union func desc */\r\n  0x00,   /* bMasterInterface: Communication class interface */\r\n  0x01,   /* bSlaveInterface0: Data Class Interface */\r\n\r\n  /*Endpoint 2 Descriptor*/\r\n  0x07,                           /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_ENDPOINT,   /* bDescriptorType: Endpoint */\r\n  CDC_CMD_EP,                     /* bEndpointAddress */\r\n  0x03,                           /* bmAttributes: Interrupt */\r\n  LOBYTE(CDC_CMD_PACKET_SIZE),     /* wMaxPacketSize: */\r\n  HIBYTE(CDC_CMD_PACKET_SIZE),\r\n  0x10,                           /* bInterval: */\r\n  /*---------------------------------------------------------------------------*/\r\n\r\n  /*Data class interface descriptor*/\r\n  0x09,   /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_INTERFACE,  /* bDescriptorType: */\r\n  0x01,   /* bInterfaceNumber: Number of Interface */\r\n  0x00,   /* bAlternateSetting: Alternate setting */\r\n  0x02,   /* bNumEndpoints: Two endpoints used */\r\n  0x0A,   /* bInterfaceClass: CDC */\r\n  0x00,   /* bInterfaceSubClass: */\r\n  0x00,   /* bInterfaceProtocol: */\r\n  0x00,   /* iInterface: */\r\n\r\n  /*Endpoint OUT Descriptor*/\r\n  0x07,   /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_ENDPOINT,      /* bDescriptorType: Endpoint */\r\n  CDC_OUT_EP,                        /* bEndpointAddress */\r\n  0x02,                              /* bmAttributes: Bulk */\r\n  LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE),  /* wMaxPacketSize: */\r\n  HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE),\r\n  0x00,                              /* bInterval: ignore for Bulk transfer */\r\n\r\n  /*Endpoint IN Descriptor*/\r\n  0x07,   /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_ENDPOINT,      /* bDescriptorType: Endpoint */\r\n  CDC_IN_EP,                         /* bEndpointAddress */\r\n  0x02,                              /* bmAttributes: Bulk */\r\n  LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE),  /* wMaxPacketSize: */\r\n  HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE),\r\n  0x00                               /* bInterval: ignore for Bulk transfer */\r\n} ;\r\n\r\n\r\n/* USB CDC device Configuration Descriptor */\r\n__ALIGN_BEGIN uint8_t USBD_CDC_CfgFSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END =\r\n{\r\n  /*Configuration Descriptor*/\r\n  0x09,   /* bLength: Configuration Descriptor size */\r\n  USB_DESC_TYPE_CONFIGURATION,      /* bDescriptorType: Configuration */\r\n  USB_CDC_CONFIG_DESC_SIZ,                /* wTotalLength:no of returned bytes */\r\n  0x00,\r\n  0x02,   /* bNumInterfaces: 2 interface */\r\n  0x01,   /* bConfigurationValue: Configuration value */\r\n  0x00,   /* iConfiguration: Index of string descriptor describing the configuration */\r\n  0xC0,   /* bmAttributes: self powered */\r\n  0x32,   /* MaxPower 0 mA */\r\n\r\n  /*---------------------------------------------------------------------------*/\r\n\r\n  /*Interface Descriptor */\r\n  0x09,   /* bLength: Interface Descriptor size */\r\n  USB_DESC_TYPE_INTERFACE,  /* bDescriptorType: Interface */\r\n  /* Interface descriptor type */\r\n  0x00,   /* bInterfaceNumber: Number of Interface */\r\n  0x00,   /* bAlternateSetting: Alternate setting */\r\n  0x01,   /* bNumEndpoints: One endpoints used */\r\n  0x02,   /* bInterfaceClass: Communication Interface Class */\r\n  0x02,   /* bInterfaceSubClass: Abstract Control Model */\r\n  0x01,   /* bInterfaceProtocol: Common AT commands */\r\n  0x00,   /* iInterface: */\r\n\r\n  /*Header Functional Descriptor*/\r\n  0x05,   /* bLength: Endpoint Descriptor size */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x00,   /* bDescriptorSubtype: Header Func Desc */\r\n  0x10,   /* bcdCDC: spec release number */\r\n  0x01,\r\n\r\n  /*Call Management Functional Descriptor*/\r\n  0x05,   /* bFunctionLength */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x01,   /* bDescriptorSubtype: Call Management Func Desc */\r\n  0x00,   /* bmCapabilities: D0+D1 */\r\n  0x01,   /* bDataInterface: 1 */\r\n\r\n  /*ACM Functional Descriptor*/\r\n  0x04,   /* bFunctionLength */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x02,   /* bDescriptorSubtype: Abstract Control Management desc */\r\n  0x02,   /* bmCapabilities */\r\n\r\n  /*Union Functional Descriptor*/\r\n  0x05,   /* bFunctionLength */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x06,   /* bDescriptorSubtype: Union func desc */\r\n  0x00,   /* bMasterInterface: Communication class interface */\r\n  0x01,   /* bSlaveInterface0: Data Class Interface */\r\n\r\n  /*Endpoint 2 Descriptor*/\r\n  0x07,                           /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_ENDPOINT,   /* bDescriptorType: Endpoint */\r\n  CDC_CMD_EP,                     /* bEndpointAddress */\r\n  0x03,                           /* bmAttributes: Interrupt */\r\n  LOBYTE(CDC_CMD_PACKET_SIZE),     /* wMaxPacketSize: */\r\n  HIBYTE(CDC_CMD_PACKET_SIZE),\r\n  0x10,                           /* bInterval: */\r\n  /*---------------------------------------------------------------------------*/\r\n\r\n  /*Data class interface descriptor*/\r\n  0x09,   /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_INTERFACE,  /* bDescriptorType: */\r\n  0x01,   /* bInterfaceNumber: Number of Interface */\r\n  0x00,   /* bAlternateSetting: Alternate setting */\r\n  0x02,   /* bNumEndpoints: Two endpoints used */\r\n  0x0A,   /* bInterfaceClass: CDC */\r\n  0x00,   /* bInterfaceSubClass: */\r\n  0x00,   /* bInterfaceProtocol: */\r\n  0x00,   /* iInterface: */\r\n\r\n  /*Endpoint OUT Descriptor*/\r\n  0x07,   /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_ENDPOINT,      /* bDescriptorType: Endpoint */\r\n  CDC_OUT_EP,                        /* bEndpointAddress */\r\n  0x02,                              /* bmAttributes: Bulk */\r\n  LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE),  /* wMaxPacketSize: */\r\n  HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE),\r\n  0x00,                              /* bInterval: ignore for Bulk transfer */\r\n\r\n  /*Endpoint IN Descriptor*/\r\n  0x07,   /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_ENDPOINT,      /* bDescriptorType: Endpoint */\r\n  CDC_IN_EP,                         /* bEndpointAddress */\r\n  0x02,                              /* bmAttributes: Bulk */\r\n  LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE),  /* wMaxPacketSize: */\r\n  HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE),\r\n  0x00                               /* bInterval: ignore for Bulk transfer */\r\n} ;\r\n\r\n__ALIGN_BEGIN uint8_t USBD_CDC_OtherSpeedCfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END =\r\n{\r\n  0x09,   /* bLength: Configuation Descriptor size */\r\n  USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION,\r\n  USB_CDC_CONFIG_DESC_SIZ,\r\n  0x00,\r\n  0x02,   /* bNumInterfaces: 2 interfaces */\r\n  0x01,   /* bConfigurationValue: */\r\n  0x04,   /* iConfiguration: */\r\n  0xC0,   /* bmAttributes: */\r\n  0x32,   /* MaxPower 100 mA */\r\n\r\n  /*Interface Descriptor */\r\n  0x09,   /* bLength: Interface Descriptor size */\r\n  USB_DESC_TYPE_INTERFACE,  /* bDescriptorType: Interface */\r\n  /* Interface descriptor type */\r\n  0x00,   /* bInterfaceNumber: Number of Interface */\r\n  0x00,   /* bAlternateSetting: Alternate setting */\r\n  0x01,   /* bNumEndpoints: One endpoints used */\r\n  0x02,   /* bInterfaceClass: Communication Interface Class */\r\n  0x02,   /* bInterfaceSubClass: Abstract Control Model */\r\n  0x01,   /* bInterfaceProtocol: Common AT commands */\r\n  0x00,   /* iInterface: */\r\n\r\n  /*Header Functional Descriptor*/\r\n  0x05,   /* bLength: Endpoint Descriptor size */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x00,   /* bDescriptorSubtype: Header Func Desc */\r\n  0x10,   /* bcdCDC: spec release number */\r\n  0x01,\r\n\r\n  /*Call Management Functional Descriptor*/\r\n  0x05,   /* bFunctionLength */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x01,   /* bDescriptorSubtype: Call Management Func Desc */\r\n  0x00,   /* bmCapabilities: D0+D1 */\r\n  0x01,   /* bDataInterface: 1 */\r\n\r\n  /*ACM Functional Descriptor*/\r\n  0x04,   /* bFunctionLength */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x02,   /* bDescriptorSubtype: Abstract Control Management desc */\r\n  0x02,   /* bmCapabilities */\r\n\r\n  /*Union Functional Descriptor*/\r\n  0x05,   /* bFunctionLength */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x06,   /* bDescriptorSubtype: Union func desc */\r\n  0x00,   /* bMasterInterface: Communication class interface */\r\n  0x01,   /* bSlaveInterface0: Data Class Interface */\r\n\r\n  /*Endpoint 2 Descriptor*/\r\n  0x07,                           /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_ENDPOINT      ,   /* bDescriptorType: Endpoint */\r\n  CDC_CMD_EP,                     /* bEndpointAddress */\r\n  0x03,                           /* bmAttributes: Interrupt */\r\n  LOBYTE(CDC_CMD_PACKET_SIZE),     /* wMaxPacketSize: */\r\n  HIBYTE(CDC_CMD_PACKET_SIZE),\r\n  0xFF,                           /* bInterval: */\r\n\r\n  /*---------------------------------------------------------------------------*/\r\n\r\n  /*Data class interface descriptor*/\r\n  0x09,   /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_INTERFACE,  /* bDescriptorType: */\r\n  0x01,   /* bInterfaceNumber: Number of Interface */\r\n  0x00,   /* bAlternateSetting: Alternate setting */\r\n  0x02,   /* bNumEndpoints: Two endpoints used */\r\n  0x0A,   /* bInterfaceClass: CDC */\r\n  0x00,   /* bInterfaceSubClass: */\r\n  0x00,   /* bInterfaceProtocol: */\r\n  0x00,   /* iInterface: */\r\n\r\n  /*Endpoint OUT Descriptor*/\r\n  0x07,   /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_ENDPOINT,      /* bDescriptorType: Endpoint */\r\n  CDC_OUT_EP,                        /* bEndpointAddress */\r\n  0x02,                              /* bmAttributes: Bulk */\r\n  0x40,                              /* wMaxPacketSize: */\r\n  0x00,\r\n  0x00,                              /* bInterval: ignore for Bulk transfer */\r\n\r\n  /*Endpoint IN Descriptor*/\r\n  0x07,   /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_ENDPOINT,     /* bDescriptorType: Endpoint */\r\n  CDC_IN_EP,                        /* bEndpointAddress */\r\n  0x02,                             /* bmAttributes: Bulk */\r\n  0x40,                             /* wMaxPacketSize: */\r\n  0x00,\r\n  0x00                              /* bInterval */\r\n};\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USBD_CDC_Private_Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  USBD_CDC_Init\r\n  *         Initialize the CDC interface\r\n  * @param  pdev: device instance\r\n  * @param  cfgidx: Configuration index\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_CDC_Init (USBD_HandleTypeDef *pdev,\r\n                               uint8_t cfgidx)\r\n{\r\n  UNUSED(cfgidx);\r\n\r\n  uint8_t ret = 0;\r\n  USBD_CDC_HandleTypeDef   *hcdc;\r\n\r\n  if(pdev->dev_speed == USBD_SPEED_HIGH  )\r\n  {\r\n    /* Open EP IN */\r\n    USBD_LL_OpenEP(pdev,\r\n                   CDC_IN_EP,\r\n                   USBD_EP_TYPE_BULK,\r\n                   CDC_DATA_HS_IN_PACKET_SIZE);\r\n\r\n    /* Open EP OUT */\r\n    USBD_LL_OpenEP(pdev,\r\n                   CDC_OUT_EP,\r\n                   USBD_EP_TYPE_BULK,\r\n                   CDC_DATA_HS_OUT_PACKET_SIZE);\r\n\r\n  }\r\n  else\r\n  {\r\n    /* Open EP IN */\r\n    USBD_LL_OpenEP(pdev,\r\n                   CDC_IN_EP,\r\n                   USBD_EP_TYPE_BULK,\r\n                   CDC_DATA_FS_IN_PACKET_SIZE);\r\n\r\n    /* Open EP OUT */\r\n    USBD_LL_OpenEP(pdev,\r\n                   CDC_OUT_EP,\r\n                   USBD_EP_TYPE_BULK,\r\n                   CDC_DATA_FS_OUT_PACKET_SIZE);\r\n  }\r\n  /* Open Command IN EP */\r\n  USBD_LL_OpenEP(pdev,\r\n                 CDC_CMD_EP,\r\n                 USBD_EP_TYPE_INTR,\r\n                 CDC_CMD_PACKET_SIZE);\r\n\r\n\r\n  pdev->pClassData = USBD_malloc(sizeof (USBD_CDC_HandleTypeDef));\r\n\r\n  if(pdev->pClassData == NULL)\r\n  {\r\n    ret = 1;\r\n  }\r\n  else\r\n  {\r\n    hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\r\n\r\n    /* Init  physical Interface components */\r\n    ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Init();\r\n\r\n    /* Init Xfer states */\r\n    hcdc->TxState =0;\r\n    hcdc->RxState =0;\r\n\r\n    if(pdev->dev_speed == USBD_SPEED_HIGH  )\r\n    {\r\n      /* Prepare Out endpoint to receive next packet */\r\n      USBD_LL_PrepareReceive(pdev,\r\n                             CDC_OUT_EP,\r\n                             hcdc->RxBuffer,\r\n                             CDC_DATA_HS_OUT_PACKET_SIZE);\r\n    }\r\n    else\r\n    {\r\n      /* Prepare Out endpoint to receive next packet */\r\n      USBD_LL_PrepareReceive(pdev,\r\n                             CDC_OUT_EP,\r\n                             hcdc->RxBuffer,\r\n                             CDC_DATA_FS_OUT_PACKET_SIZE);\r\n    }\r\n\r\n\r\n  }\r\n  return ret;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_CDC_Init\r\n  *         DeInitialize the CDC layer\r\n  * @param  pdev: device instance\r\n  * @param  cfgidx: Configuration index\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_CDC_DeInit (USBD_HandleTypeDef *pdev,\r\n                                 uint8_t cfgidx)\r\n{\r\n  UNUSED(cfgidx);\r\n\r\n  uint8_t ret = 0;\r\n\r\n  /* Open EP IN */\r\n  USBD_LL_CloseEP(pdev,\r\n              CDC_IN_EP);\r\n\r\n  /* Open EP OUT */\r\n  USBD_LL_CloseEP(pdev,\r\n              CDC_OUT_EP);\r\n\r\n  /* Open Command IN EP */\r\n  USBD_LL_CloseEP(pdev,\r\n              CDC_CMD_EP);\r\n\r\n\r\n  /* DeInit  physical Interface components */\r\n  if(pdev->pClassData != NULL)\r\n  {\r\n    ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->DeInit();\r\n    USBD_free(pdev->pClassData);\r\n    pdev->pClassData = NULL;\r\n  }\r\n\r\n  return ret;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_CDC_Setup\r\n  *         Handle the CDC specific requests\r\n  * @param  pdev: instance\r\n  * @param  req: usb requests\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_CDC_Setup (USBD_HandleTypeDef *pdev,\r\n                                USBD_SetupReqTypedef *req)\r\n{\r\n  USBD_CDC_HandleTypeDef   *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\r\n  static uint8_t ifalt = 0;\r\n\r\n  switch (req->bmRequest & USB_REQ_TYPE_MASK)\r\n  {\r\n  case USB_REQ_TYPE_CLASS :\r\n    if (req->wLength)\r\n    {\r\n      if (req->bmRequest & 0x80)\r\n      {\r\n        ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,\r\n                                                          (uint8_t *)hcdc->data,\r\n                                                          req->wLength);\r\n          USBD_CtlSendData (pdev,\r\n                            (uint8_t *)hcdc->data,\r\n                            req->wLength);\r\n      }\r\n      else\r\n      {\r\n        hcdc->CmdOpCode = req->bRequest;\r\n        hcdc->CmdLength = req->wLength;\r\n\r\n        USBD_CtlPrepareRx (pdev,\r\n                           (uint8_t *)hcdc->data,\r\n                           req->wLength);\r\n      }\r\n\r\n    }\r\n    else\r\n    {\r\n      ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,\r\n                                                        (uint8_t*)req,\r\n                                                        0);\r\n    }\r\n    break;\r\n\r\n  case USB_REQ_TYPE_STANDARD:\r\n    switch (req->bRequest)\r\n    {\r\n    case USB_REQ_GET_INTERFACE :\r\n      USBD_CtlSendData (pdev,\r\n                        &ifalt,\r\n                        1);\r\n      break;\r\n\r\n    case USB_REQ_SET_INTERFACE :\r\n      break;\r\n    }\r\n\r\n  default:\r\n    break;\r\n  }\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_CDC_DataIn\r\n  *         Data sent on non-control IN endpoint\r\n  * @param  pdev: device instance\r\n  * @param  epnum: endpoint number\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum)\r\n{\r\n  UNUSED(epnum);\r\n\r\n  USBD_CDC_HandleTypeDef   *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\r\n\r\n  if(pdev->pClassData != NULL)\r\n  {\r\n\r\n    hcdc->TxState = 0;\r\n\r\n    return USBD_OK;\r\n  }\r\n  else\r\n  {\r\n    return USBD_FAIL;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  USBD_CDC_DataOut\r\n  *         Data received on non-control Out endpoint\r\n  * @param  pdev: device instance\r\n  * @param  epnum: endpoint number\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_CDC_DataOut (USBD_HandleTypeDef *pdev, uint8_t epnum)\r\n{\r\n  USBD_CDC_HandleTypeDef   *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\r\n\r\n  /* Get the received data length */\r\n  hcdc->RxLength = USBD_LL_GetRxDataSize (pdev, epnum);\r\n\r\n  /* USB data will be immediately processed, this allow next USB traffic being\r\n  NAKed till the end of the application Xfer */\r\n  if(pdev->pClassData != NULL)\r\n  {\r\n    ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hcdc->RxBuffer, &hcdc->RxLength);\r\n\r\n    return USBD_OK;\r\n  }\r\n  else\r\n  {\r\n    return USBD_FAIL;\r\n  }\r\n}\r\n\r\n\r\n\r\n/**\r\n  * @brief  USBD_CDC_DataOut\r\n  *         Data received on non-control Out endpoint\r\n  * @param  pdev: device instance\r\n  * @param  epnum: endpoint number\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_CDC_EP0_RxReady (USBD_HandleTypeDef *pdev)\r\n{\r\n  USBD_CDC_HandleTypeDef   *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\r\n\r\n  if((pdev->pUserData != NULL) && (hcdc->CmdOpCode != 0xFF))\r\n  {\r\n    ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode,\r\n                                                      (uint8_t *)hcdc->data,\r\n                                                      hcdc->CmdLength);\r\n      hcdc->CmdOpCode = 0xFF;\r\n\r\n  }\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_CDC_GetFSCfgDesc\r\n  *         Return configuration descriptor\r\n  * @param  speed : current device speed\r\n  * @param  length : pointer data length\r\n  * @retval pointer to descriptor buffer\r\n  */\r\nstatic uint8_t  *USBD_CDC_GetFSCfgDesc (uint16_t *length)\r\n{\r\n  *length = sizeof (USBD_CDC_CfgFSDesc);\r\n  return USBD_CDC_CfgFSDesc;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_CDC_GetHSCfgDesc\r\n  *         Return configuration descriptor\r\n  * @param  speed : current device speed\r\n  * @param  length : pointer data length\r\n  * @retval pointer to descriptor buffer\r\n  */\r\nstatic uint8_t  *USBD_CDC_GetHSCfgDesc (uint16_t *length)\r\n{\r\n  *length = sizeof (USBD_CDC_CfgHSDesc);\r\n  return USBD_CDC_CfgHSDesc;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_CDC_GetCfgDesc\r\n  *         Return configuration descriptor\r\n  * @param  speed : current device speed\r\n  * @param  length : pointer data length\r\n  * @retval pointer to descriptor buffer\r\n  */\r\nstatic uint8_t  *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length)\r\n{\r\n  *length = sizeof (USBD_CDC_OtherSpeedCfgDesc);\r\n  return USBD_CDC_OtherSpeedCfgDesc;\r\n}\r\n\r\n/**\r\n* @brief  DeviceQualifierDescriptor\r\n*         return Device Qualifier descriptor\r\n* @param  length : pointer data length\r\n* @retval pointer to descriptor buffer\r\n*/\r\nuint8_t  *USBD_CDC_GetDeviceQualifierDescriptor (uint16_t *length)\r\n{\r\n  *length = sizeof (USBD_CDC_DeviceQualifierDesc);\r\n  return USBD_CDC_DeviceQualifierDesc;\r\n}\r\n\r\n/**\r\n* @brief  USBD_CDC_RegisterInterface\r\n  * @param  pdev: device instance\r\n  * @param  fops: CD  Interface callback\r\n  * @retval status\r\n  */\r\nuint8_t  USBD_CDC_RegisterInterface  (USBD_HandleTypeDef   *pdev,\r\n                                      USBD_CDC_ItfTypeDef *fops)\r\n{\r\n  uint8_t  ret = USBD_FAIL;\r\n\r\n  if(fops != NULL)\r\n  {\r\n    pdev->pUserData= fops;\r\n    ret = USBD_OK;\r\n  }\r\n\r\n  return ret;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_CDC_SetTxBuffer\r\n  * @param  pdev: device instance\r\n  * @param  pbuff: Tx Buffer\r\n  * @retval status\r\n  */\r\nuint8_t  USBD_CDC_SetTxBuffer  (USBD_HandleTypeDef   *pdev,\r\n                                uint8_t  *pbuff,\r\n                                uint16_t length)\r\n{\r\n  USBD_CDC_HandleTypeDef   *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\r\n\r\n  hcdc->TxBuffer = pbuff;\r\n  hcdc->TxLength = length;\r\n\r\n  return USBD_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  USBD_CDC_SetRxBuffer\r\n  * @param  pdev: device instance\r\n  * @param  pbuff: Rx Buffer\r\n  * @retval status\r\n  */\r\nuint8_t  USBD_CDC_SetRxBuffer  (USBD_HandleTypeDef   *pdev,\r\n                                   uint8_t  *pbuff)\r\n{\r\n  USBD_CDC_HandleTypeDef   *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\r\n\r\n  hcdc->RxBuffer = pbuff;\r\n\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_CDC_DataOut\r\n  *         Data received on non-control Out endpoint\r\n  * @param  pdev: device instance\r\n  * @param  epnum: endpoint number\r\n  * @retval status\r\n  */\r\nuint8_t  USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev)\r\n{\r\n  USBD_CDC_HandleTypeDef   *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\r\n\r\n  if(pdev->pClassData != NULL)\r\n  {\r\n    if(hcdc->TxState == 0)\r\n    {\r\n      /* Tx Transfer in progress */\r\n      hcdc->TxState = 1;\r\n\r\n      /* Transmit next packet */\r\n      USBD_LL_Transmit(pdev,\r\n                       CDC_IN_EP,\r\n                       hcdc->TxBuffer,\r\n                       hcdc->TxLength);\r\n\r\n      return USBD_OK;\r\n    }\r\n    else\r\n    {\r\n      return USBD_BUSY;\r\n    }\r\n  }\r\n  else\r\n  {\r\n    return USBD_FAIL;\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  * @brief  USBD_CDC_ReceivePacket\r\n  *         prepare OUT Endpoint for reception\r\n  * @param  pdev: device instance\r\n  * @retval status\r\n  */\r\nuint8_t  USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev)\r\n{\r\n  USBD_CDC_HandleTypeDef   *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\r\n\r\n  /* Suspend or Resume USB Out process */\r\n  if(pdev->pClassData != NULL)\r\n  {\r\n    if(pdev->dev_speed == USBD_SPEED_HIGH  )\r\n    {\r\n      /* Prepare Out endpoint to receive next packet */\r\n      USBD_LL_PrepareReceive(pdev,\r\n                             CDC_OUT_EP,\r\n                             hcdc->RxBuffer,\r\n                             CDC_DATA_HS_OUT_PACKET_SIZE);\r\n    }\r\n    else\r\n    {\r\n      /* Prepare Out endpoint to receive next packet */\r\n      USBD_LL_PrepareReceive(pdev,\r\n                             CDC_OUT_EP,\r\n                             hcdc->RxBuffer,\r\n                             CDC_DATA_FS_OUT_PACKET_SIZE);\r\n    }\r\n    return USBD_OK;\r\n  }\r\n  else\r\n  {\r\n    return USBD_FAIL;\r\n  }\r\n}\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/usb_cdc/usbd_cdc.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_cdc.h\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   header file for the usbd_cdc.c file.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n \r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __USB_CDC_H\r\n#define __USB_CDC_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include  \"usbd_ioreq.h\"\r\n\r\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup usbd_cdc\r\n  * @brief This file is the Header file for usbd_cdc.c\r\n  * @{\r\n  */ \r\n\r\n\r\n/** @defgroup usbd_cdc_Exported_Defines\r\n  * @{\r\n  */ \r\n#define CDC_IN_EP                                   0x81  /* EP1 for data IN */\r\n#define CDC_OUT_EP                                  0x01  /* EP1 for data OUT */\r\n#define CDC_CMD_EP                                  0x82  /* EP2 for CDC commands */\r\n\r\n/* CDC Endpoints parameters: you can fine tune these values depending on the needed baudrates and performance. */\r\n#define CDC_DATA_HS_MAX_PACKET_SIZE                 512  /* Endpoint IN & OUT Packet size */\r\n#define CDC_DATA_FS_MAX_PACKET_SIZE                 64  /* Endpoint IN & OUT Packet size */\r\n#define CDC_CMD_PACKET_SIZE                         8  /* Control Endpoint Packet size */ \r\n\r\n#define USB_CDC_CONFIG_DESC_SIZ                     67\r\n#define CDC_DATA_HS_IN_PACKET_SIZE                  CDC_DATA_HS_MAX_PACKET_SIZE\r\n#define CDC_DATA_HS_OUT_PACKET_SIZE                 CDC_DATA_HS_MAX_PACKET_SIZE\r\n\r\n#define CDC_DATA_FS_IN_PACKET_SIZE                  CDC_DATA_FS_MAX_PACKET_SIZE\r\n#define CDC_DATA_FS_OUT_PACKET_SIZE                 CDC_DATA_FS_MAX_PACKET_SIZE\r\n\r\n/*---------------------------------------------------------------------*/\r\n/*  CDC definitions                                                    */\r\n/*---------------------------------------------------------------------*/\r\n#define CDC_SEND_ENCAPSULATED_COMMAND               0x00\r\n#define CDC_GET_ENCAPSULATED_RESPONSE               0x01\r\n#define CDC_SET_COMM_FEATURE                        0x02\r\n#define CDC_GET_COMM_FEATURE                        0x03\r\n#define CDC_CLEAR_COMM_FEATURE                      0x04\r\n#define CDC_SET_LINE_CODING                         0x20\r\n#define CDC_GET_LINE_CODING                         0x21\r\n#define CDC_SET_CONTROL_LINE_STATE                  0x22\r\n#define CDC_SEND_BREAK                              0x23\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_CORE_Exported_TypesDefinitions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\ntypedef struct\r\n{\r\n  uint32_t bitrate;\r\n  uint8_t  format;\r\n  uint8_t  paritytype;\r\n  uint8_t  datatype;\r\n}USBD_CDC_LineCodingTypeDef;\r\n\r\ntypedef struct _USBD_CDC_Itf\r\n{\r\n  int8_t (* Init)          (void);\r\n  int8_t (* DeInit)        (void);\r\n  int8_t (* Control)       (uint8_t, uint8_t * , uint16_t);   \r\n  int8_t (* Receive)       (uint8_t *, uint32_t *);  \r\n\r\n}USBD_CDC_ItfTypeDef;\r\n\r\n\r\ntypedef struct\r\n{\r\n  uint32_t data[CDC_DATA_HS_MAX_PACKET_SIZE/4];      /* Force 32bits alignment */\r\n  uint8_t  CmdOpCode;\r\n  uint8_t  CmdLength;    \r\n  uint8_t  *RxBuffer;  \r\n  uint8_t  *TxBuffer;   \r\n  uint32_t RxLength;\r\n  uint32_t TxLength;    \r\n  \r\n  __IO uint32_t TxState;     \r\n  __IO uint32_t RxState;    \r\n}\r\nUSBD_CDC_HandleTypeDef; \r\n\r\n\r\n\r\n/** @defgroup USBD_CORE_Exported_Macros\r\n  * @{\r\n  */ \r\n  \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_CORE_Exported_Variables\r\n  * @{\r\n  */ \r\n\r\nextern USBD_ClassTypeDef  USBD_CDC;\r\n#define USBD_CDC_CLASS    &USBD_CDC\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USB_CORE_Exported_Functions\r\n  * @{\r\n  */\r\nuint8_t  USBD_CDC_RegisterInterface  (USBD_HandleTypeDef   *pdev, \r\n                                      USBD_CDC_ItfTypeDef *fops);\r\n\r\nuint8_t  USBD_CDC_SetTxBuffer        (USBD_HandleTypeDef   *pdev,\r\n                                      uint8_t  *pbuff,\r\n                                      uint16_t length);\r\n\r\nuint8_t  USBD_CDC_SetRxBuffer        (USBD_HandleTypeDef   *pdev,\r\n                                      uint8_t  *pbuff);\r\n  \r\nuint8_t  USBD_CDC_ReceivePacket      (USBD_HandleTypeDef *pdev);\r\n\r\nuint8_t  USBD_CDC_TransmitPacket     (USBD_HandleTypeDef *pdev);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif  /* __USB_CDC_H */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/usb_cdc/usbd_cdc_interface.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    USB_Device/CDC_Standalone/Src/usbd_cdc_interface.c\r\n  * @author  MCD Application Team\r\n  * @version V1.0.3\r\n  * @date    18-November-2015\r\n  * @brief   Source file for USBD CDC interface\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software\r\n  * distributed under the License is distributed on an \"AS IS\" BASIS,\r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_cdc_interface.h\"\r\n#include \"wdg.h\"\r\n\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n#define APP_RX_BUF_SIZE   (1024*16)\r\n#define APP_RX_DATA_SIZE  (1024*2)\r\n#define APP_TX_DATA_SIZE  (1024*2)\r\n\r\n\r\nconst char *JUMP_BOOT_STR = \"OpenCR 5555AAAA\";\r\n\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\nUSBD_CDC_LineCodingTypeDef LineCoding =\r\n{\r\n  115200, /* baud rate*/\r\n  0x00,   /* stop bits-1*/\r\n  0x00,   /* parity - none*/\r\n  0x08    /* nb. of bits 8*/\r\n};\r\n\r\n\r\nuint8_t CDC_Reset_Status = 0;\r\nuint8_t CDC_Reset_Status_Baud = 0;\r\n\r\nuint8_t UserRxBuffer[APP_RX_DATA_SIZE];/* Received Data over USB are stored in this buffer */\r\nuint8_t UserTxBuffer[APP_TX_DATA_SIZE];/* Received Data over UART (CDC interface) are stored in this buffer */\r\nuint8_t UserTxBufferForUSB[APP_TX_DATA_SIZE];/* Received Data over UART (CDC interface) are stored in this buffer */\r\n\r\nuint32_t BuffLength;\r\nstatic uint32_t UserTxBufPtrIn = 0;/* Increment this pointer or roll it back to\r\n                               start address when data are received over USART */\r\nstatic uint32_t UserTxBufPtrOut = 0; /* Increment this pointer or roll it back to\r\n                                 start address when data are sent over USB */\r\nstatic uint16_t UserTxBufPtrOutShadow = 0; // shadow of above\r\nstatic uint8_t  UserTxBufPtrWaitCount = 0; // used to implement a timeout waiting for low-level USB driver\r\nstatic uint8_t  UserTxNeedEmptyPacket = 0; // used to flush the USB IN endpoint if the last packet was exactly the endpoint packet size\r\n\r\nstatic BOOL is_opened = FALSE;\r\nstatic BOOL is_reopen = FALSE;\r\nvolatile bool usb_rx_full = false;\r\n\r\n\r\nstatic uint8_t  rxd_buffer[APP_RX_BUF_SIZE];\r\nstatic uint32_t rxd_length    = 0;\r\nstatic uint32_t rxd_BufPtrIn  = 0;\r\nstatic uint32_t rxd_BufPtrOut = 0;\r\n\r\nuint32_t usb_cdc_debug_cnt[16] = {0,};\r\n\r\n\r\n/* USB handler declaration */\r\nextern USBD_HandleTypeDef  USBD_Device;\r\n\r\n/* Private function prototypes -----------------------------------------------*/\r\nstatic int8_t CDC_Itf_Init(void);\r\nstatic int8_t CDC_Itf_DeInit(void);\r\nstatic int8_t CDC_Itf_Control(uint8_t cmd, uint8_t* pbuf, uint16_t length);\r\n       void   CDC_Itf_TxISR(void);\r\nstatic int8_t CDC_Itf_Receive(uint8_t* pbuf, uint32_t *Len);\r\nstatic uint32_t CDC_Itf_TxAvailable( void );\r\n\r\n\r\n\r\nUSBD_CDC_ItfTypeDef USBD_CDC_fops =\r\n{\r\n  CDC_Itf_Init,\r\n  CDC_Itf_DeInit,\r\n  CDC_Itf_Control,\r\n  CDC_Itf_Receive\r\n};\r\n\r\nuint32_t usb_cdc_bitrate = 0;\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/**\r\n  * @brief  CDC_Itf_Init\r\n  *         Initializes the CDC media low layer\r\n  * @param  None\r\n  * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL\r\n  */\r\nstatic int8_t CDC_Itf_Init(void)\r\n{\r\n  USBD_CDC_SetTxBuffer(&USBD_Device, UserTxBufferForUSB, 0);\r\n  USBD_CDC_SetRxBuffer(&USBD_Device, UserRxBuffer);\r\n  is_opened = FALSE;\r\n  LineCoding.bitrate = 0;\r\n  usb_cdc_bitrate = 0;\r\n\r\n  BuffLength            = 0;\r\n  UserTxBufPtrIn        = 0;\r\n  UserTxBufPtrOut       = 0;\r\n  UserTxBufPtrOutShadow = 0;\r\n  UserTxBufPtrWaitCount = 0;\r\n  UserTxNeedEmptyPacket = 0;\r\n\r\n  rxd_length            = 0;\r\n  rxd_BufPtrIn          = 0;\r\n  rxd_BufPtrOut         = 0;\r\n\r\n  return (USBD_OK);\r\n}\r\n\r\n/**\r\n  * @brief  CDC_Itf_DeInit\r\n  *         DeInitializes the CDC media low layer\r\n  * @param  None\r\n  * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL\r\n  */\r\nstatic int8_t CDC_Itf_DeInit(void)\r\n{\r\n  is_opened = FALSE;\r\n  return (USBD_OK);\r\n}\r\n\r\n\r\n/**\r\n  * @brief  CDC_Itf_Control\r\n  *         Manage the CDC class requests\r\n  * @param  Cmd: Command code\r\n  * @param  Buf: Buffer containing command data (request parameters)\r\n  * @param  Len: Number of data to be sent (in bytes)\r\n  * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL\r\n  */\r\nstatic int8_t CDC_Itf_Control (uint8_t cmd, uint8_t* pbuf, uint16_t length)\r\n{\r\n  UNUSED(length);\r\n  \r\n  USBD_SetupReqTypedef *req = (USBD_SetupReqTypedef *)pbuf;\r\n\r\n\r\n  switch (cmd)\r\n  {\r\n  case CDC_SEND_ENCAPSULATED_COMMAND:\r\n    /* Add your code here */\r\n    break;\r\n\r\n  case CDC_GET_ENCAPSULATED_RESPONSE:\r\n    /* Add your code here */\r\n    break;\r\n\r\n  case CDC_SET_COMM_FEATURE:\r\n    /* Add your code here */\r\n    break;\r\n\r\n  case CDC_GET_COMM_FEATURE:\r\n    /* Add your code here */\r\n    break;\r\n\r\n  case CDC_CLEAR_COMM_FEATURE:\r\n    /* Add your code here */\r\n    break;\r\n\r\n  case CDC_SET_LINE_CODING:\r\n    LineCoding.bitrate    = (uint32_t)(pbuf[0] | (pbuf[1] << 8) |\\\r\n                            (pbuf[2] << 16) | (pbuf[3] << 24));\r\n    LineCoding.format     = pbuf[4];\r\n    LineCoding.paritytype = pbuf[5];\r\n    LineCoding.datatype   = pbuf[6];\r\n\r\n    usb_cdc_bitrate = LineCoding.bitrate;\r\n\r\n    if( LineCoding.bitrate == 1200 )\r\n    {\r\n        CDC_Reset_Status_Baud = 1;\r\n    }\r\n    break;\r\n\r\n  case CDC_GET_LINE_CODING:\r\n    pbuf[0] = (uint8_t)(LineCoding.bitrate);\r\n    pbuf[1] = (uint8_t)(LineCoding.bitrate >> 8);\r\n    pbuf[2] = (uint8_t)(LineCoding.bitrate >> 16);\r\n    pbuf[3] = (uint8_t)(LineCoding.bitrate >> 24);\r\n    pbuf[4] = LineCoding.format;\r\n    pbuf[5] = LineCoding.paritytype;\r\n    pbuf[6] = LineCoding.datatype;\r\n    break;\r\n\r\n  case CDC_SET_CONTROL_LINE_STATE:\r\n    /* Add your code here */\r\n    if( req->wValue & 0x02 )\r\n    {\r\n      CDC_Reset_Status = 1;\r\n    }\r\n    is_opened = req->wValue&0x01;\r\n    is_reopen = TRUE;\r\n    break;\r\n\r\n  case CDC_SEND_BREAK:\r\n     /* Add your code here */\r\n    break;\r\n\r\n  default:\r\n    break;\r\n  }\r\n\r\n  return (USBD_OK);\r\n}\r\n\r\nvoid CDC_Itf_SofISR(void)\r\n{\r\n  uint32_t rx_buf_length;\r\n\r\n\r\n  rx_buf_length = APP_RX_DATA_SIZE - CDC_Itf_Available() - 1;\r\n\r\n  // 수신버퍼가 USB 전송 패킷 이상 남았을때만 수신하도록 함.\r\n  if (usb_rx_full == true)\r\n  {\r\n    if (rx_buf_length > CDC_DATA_FS_MAX_PACKET_SIZE)\r\n    {\r\n      USBD_CDC_ReceivePacket(&USBD_Device);\r\n      usb_rx_full = false;\r\n    }\r\n  }\r\n  CDC_Itf_TxISR();\r\n}\r\n\r\nvoid CDC_Itf_TxISR(void)\r\n{\r\n  uint32_t buffptr;\r\n  uint32_t buffsize;\r\n  USBD_CDC_HandleTypeDef   *hcdc = USBD_Device.pClassData;\r\n\r\n  if(hcdc == NULL)\r\n  {\r\n    return;\r\n  }\r\n  if(hcdc->TxState != 0)\r\n  {\r\n    return;\r\n  }\r\n\r\n  if(UserTxBufPtrOut != UserTxBufPtrIn)\r\n  {\r\n    if(UserTxBufPtrOut > UserTxBufPtrIn) /* Rollback */\r\n    {\r\n      buffsize = APP_TX_DATA_SIZE - UserTxBufPtrOut;\r\n    }\r\n    else\r\n    {\r\n      buffsize = UserTxBufPtrIn - UserTxBufPtrOut;\r\n    }\r\n\r\n    // TODO: 보낼데이터가 64의 배수이면 제로패킷을 보내야 해서, 64의 배수가 되지 않도록 임식 변경\r\n    if (buffsize%CDC_DATA_FS_MAX_PACKET_SIZE == 0 && buffsize > 0)\r\n    {\r\n      buffsize -= 1;\r\n    }\r\n\r\n    buffptr = UserTxBufPtrOut;\r\n\r\n    memcpy(UserTxBufferForUSB, (uint8_t*)&UserTxBuffer[buffptr], buffsize);\r\n    USBD_CDC_SetTxBuffer(&USBD_Device, UserTxBufferForUSB, buffsize);\r\n\r\n    if(USBD_CDC_TransmitPacket(&USBD_Device) == USBD_OK)\r\n    {\r\n      UserTxBufPtrOut += buffsize;\r\n      if (UserTxBufPtrOut == APP_TX_DATA_SIZE)\r\n      {\r\n        UserTxBufPtrOut = 0;\r\n      }\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  CDC_Itf_DataRx\r\n  *         Data received over USB OUT endpoint are sent over CDC interface\r\n  *         through this function.\r\n  * @param  Buf: Buffer of data to be transmitted\r\n  * @param  Len: Number of data received (in bytes)\r\n  * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL\r\n  */\r\nstatic int8_t CDC_Itf_Receive(uint8_t* Buf, uint32_t *Len)\r\n{\r\n  uint32_t i;\r\n  uint32_t rx_buf_length;\r\n\r\n\r\n  for( i=0; i<*Len; i++ )\r\n  {\r\n    rxd_buffer[rxd_BufPtrIn] = Buf[i];\r\n\r\n    rxd_BufPtrIn++;\r\n\r\n    /* To avoid buffer overflow */\r\n    if(rxd_BufPtrIn == APP_RX_BUF_SIZE)\r\n    {\r\n      rxd_BufPtrIn = 0;\r\n    }\r\n  }\r\n\r\n  if( CDC_Reset_Status == 1 )\r\n  {\r\n    CDC_Reset_Status = 0;\r\n\r\n    if( *Len >= 15 )\r\n    {\r\n      for( i=0; i<15; i++ )\r\n      {\r\n        if( JUMP_BOOT_STR[i] != Buf[i] ) break;\r\n      }\r\n\r\n      if( i == 15 )\r\n      {\r\n        wdg_setup(10);\r\n        wdg_start();\r\n      }\r\n    }\r\n  }\r\n\r\n  if( CDC_Reset_Status_Baud )\r\n  {\r\n    wdg_setup(10);\r\n    wdg_start();\r\n  }\r\n\r\n\r\n  rx_buf_length = APP_RX_DATA_SIZE - CDC_Itf_Available() - 1;\r\n\r\n  // 수신버퍼가 USB 전송 패킷 이상 남았을때만 수신하도록 함.\r\n  if (rx_buf_length > CDC_DATA_FS_MAX_PACKET_SIZE)\r\n  {\r\n    USBD_CDC_ReceivePacket(&USBD_Device);\r\n  }\r\n  else\r\n  {\r\n    usb_rx_full = true;\r\n  }\r\n  return (USBD_OK);\r\n}\r\n\r\n#if 1\r\nint32_t CDC_Itf_Write( uint8_t *p_buf, uint32_t length )\r\n{\r\n  uint32_t i;\r\n  uint32_t ptr_index;\r\n\r\n\r\n  if( USBD_Device.pClassData == NULL )\r\n  {\r\n    return -1;\r\n  }\r\n  if( is_opened == FALSE && is_reopen == FALSE )\r\n  {\r\n    return -1;\r\n  }\r\n  if( USBD_Device.dev_state != USBD_STATE_CONFIGURED )\r\n  {\r\n    return -1;\r\n  }\r\n  if (length >= CDC_Itf_TxAvailable())\r\n  {\r\n    return 0;\r\n  }\r\n\r\n  __disable_irq();\r\n\r\n  ptr_index = UserTxBufPtrIn;\r\n\r\n\r\n  for (i=0; i<length; i++)\r\n  {\r\n    UserTxBuffer[ptr_index] = p_buf[i];\r\n\r\n    ptr_index++;\r\n\r\n    /* To avoid buffer overflow */\r\n    if(ptr_index == APP_TX_DATA_SIZE)\r\n    {\r\n      ptr_index = 0;\r\n    }\r\n  }\r\n  UserTxBufPtrIn = ptr_index;\r\n  __enable_irq();\r\n\r\n  return length;\r\n}\r\n#else\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : CDC_Itf_Write\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nvoid CDC_Itf_Write( uint8_t *p_buf, uint32_t length )\r\n{\r\n  uint32_t timeout = 500;\r\n\r\n\r\n  if( is_opened == FALSE ) return;\r\n\r\n  is_reopen = FALSE;\r\n\r\n  for (uint32_t i = 0; i < length; i++) {\r\n      // Wait until the device is connected and the buffer has space, with a given timeout\r\n      uint32_t start = millis();\r\n      while (is_opened == FALSE || ((UserTxBufPtrIn + 1) & (APP_TX_DATA_SIZE - 1)) == UserTxBufPtrOut) {\r\n          // Wraparound of tick is taken care of by 2's complement arithmetic.\r\n          if (millis() - start >= timeout) {\r\n              // timeout\r\n              if( is_reopen == FALSE )\r\n              {\r\n                is_opened = FALSE;\r\n              }\r\n              usb_cdc_debug_cnt[1]++;\r\n              return;\r\n          }\r\n          __WFI(); // enter sleep mode, waiting for interrupt\r\n      }\r\n\r\n      // Write data to device buffer\r\n      UserTxBuffer[UserTxBufPtrIn] = p_buf[i];\r\n      UserTxBufPtrIn = (UserTxBufPtrIn + 1) & (APP_TX_DATA_SIZE - 1);\r\n  }\r\n}\r\n#endif\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : CDC_Itf_TxAvailable\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nuint32_t CDC_Itf_TxAvailable( void )\r\n{\r\n  uint32_t length = 0;\r\n\r\n  __disable_irq();\r\n  length = (APP_TX_DATA_SIZE + UserTxBufPtrIn - UserTxBufPtrOut) % APP_TX_DATA_SIZE;\r\n  length = APP_TX_DATA_SIZE - length;\r\n  __enable_irq();\r\n\r\n  return length;\r\n}\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : CDC_Itf_IsAvailable\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nBOOL CDC_Itf_IsAvailable( void )\r\n{\r\n  if( rxd_BufPtrIn != rxd_BufPtrOut ) return TRUE;\r\n\r\n  return FALSE;\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : CDC_Itf_Available\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nuint32_t CDC_Itf_Available( void )\r\n{\r\n  uint32_t length;\r\n\r\n  __disable_irq();\r\n  length = (APP_RX_BUF_SIZE + rxd_BufPtrIn - rxd_BufPtrOut) % APP_RX_BUF_SIZE;\r\n  __enable_irq();\r\n\r\n  return length;\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : CDC_Itf_Peek\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nint32_t CDC_Itf_Peek( void )\r\n{\r\n\r\n  if( rxd_BufPtrIn == rxd_BufPtrOut ) return -1;\r\n\r\n\r\n  return rxd_buffer[rxd_BufPtrOut];\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : CDC_Itf_IsConnected\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nBOOL CDC_Itf_IsConnected( void )\r\n{\r\n  if( USBD_Device.dev_config == 0\r\n    || is_opened == FALSE\r\n    || USBD_Device.pClassData == NULL )\r\n  {\r\n    return FALSE;\r\n  }\r\n\r\n  return TRUE;\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : CDC_Itf_Getch\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nuint8_t CDC_Itf_Getch( void )\r\n{\r\n  uint8_t ch = 0;\r\n  uint32_t buffptr;\r\n\r\n\r\n  while(1)\r\n  {\r\n    if( CDC_Itf_IsAvailable() ) break;\r\n  }\r\n\r\n\r\n\r\n  buffptr = rxd_BufPtrOut;\r\n\r\n  ch = rxd_buffer[buffptr];\r\n\r\n  __disable_irq();\r\n  rxd_BufPtrOut += 1;\r\n  if (rxd_BufPtrOut == APP_RX_BUF_SIZE)\r\n  {\r\n    rxd_BufPtrOut = 0;\r\n  }\r\n  __enable_irq();\r\n\r\n  return ch;\r\n}\r\n\r\n\r\nBOOL CDC_Itf_IsTxTransmitted( void )\r\n{\r\n  return (UserTxBufPtrIn == UserTxBufPtrOut) ? TRUE : FALSE;\r\n}\r\n\r\n\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/usb_cdc/usbd_cdc_interface.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    USB_Device/CDC_Standalone/Inc/usbd_cdc_interface.h\r\n  * @author  MCD Application Team\r\n  * @version V1.0.3\r\n  * @date    18-November-2015\r\n  * @brief   Header for usbd_cdc_interface.c file.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software\r\n  * distributed under the License is distributed on an \"AS IS\" BASIS,\r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __USBD_CDC_IF_H\r\n#define __USBD_CDC_IF_H\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"def.h\"\r\n#include \"usbd_cdc.h\"\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n\r\n\r\n\r\nextern USBD_CDC_ItfTypeDef  USBD_CDC_fops;\r\n\r\n\r\n\r\nint32_t  CDC_Itf_Write( uint8_t *p_buf, uint32_t length );\r\nBOOL     CDC_Itf_IsAvailable( void );\r\nuint32_t CDC_Itf_Available( void );\r\nuint8_t  CDC_Itf_Getch( void );\r\nint32_t  CDC_Itf_Peek( void );\r\nBOOL     CDC_Itf_IsConnected( void );\r\nBOOL     CDC_Itf_IsTxTransmitted( void );\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions ------------------------------------------------------- */\r\n#endif /* __USBD_CDC_IF_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/usb_cdc/usbd_conf.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    USB_Device/CDC_Standalone/Src/usbd_conf.c\r\n  * @author  MCD Application Team\r\n  * @version V1.0.3\r\n  * @date    18-November-2015\r\n  * @brief   This file implements the USB Device library callbacks and MSP\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software\r\n  * distributed under the License is distributed on an \"AS IS\" BASIS,\r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"bsp.h\"\r\n#include \"usbd_core.h\"\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\nPCD_HandleTypeDef hpcd;\r\n\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/*******************************************************************************\r\n                       PCD BSP Routines\r\n*******************************************************************************/\r\n\r\n/**\r\n  * @brief  Initializes the PCD MSP.\r\n  * @param  hpcd: PCD handle\r\n  * @retval None\r\n  */\r\nvoid HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)\r\n{\r\n  GPIO_InitTypeDef  GPIO_InitStruct;\r\n\r\n  if(hpcd->Instance == USB_OTG_FS)\r\n  {\r\n    /* Configure USB FS GPIOs */\r\n    __HAL_RCC_GPIOA_CLK_ENABLE();\r\n\r\n    /* Configure DM DP Pins */\r\n    GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);\r\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\r\n    GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;\r\n    GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;\r\n    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\r\n\r\n    if(hpcd->Init.vbus_sensing_enable == 1)\r\n    {\r\n      /* Configure VBUS Pin */\r\n      GPIO_InitStruct.Pin = GPIO_PIN_9;\r\n      GPIO_InitStruct.Mode = GPIO_MODE_INPUT;\r\n      GPIO_InitStruct.Pull = GPIO_NOPULL;\r\n      HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\r\n    }\r\n\r\n    /* Configure ID pin */\r\n    GPIO_InitStruct.Pin = GPIO_PIN_10;\r\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;\r\n    GPIO_InitStruct.Pull = GPIO_PULLUP;\r\n    GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;\r\n    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\r\n\r\n    /* Enable USB FS Clock */\r\n    __HAL_RCC_USB_OTG_FS_CLK_ENABLE();\r\n\r\n    /* Set USBFS Interrupt priority */\r\n    HAL_NVIC_SetPriority(OTG_FS_IRQn, 6, 0);\r\n\r\n    /* Enable USBFS Interrupt */\r\n    HAL_NVIC_EnableIRQ(OTG_FS_IRQn);\r\n  }\r\n  else if(hpcd->Instance == USB_OTG_HS)\r\n  {\r\n#ifdef USE_USB_HS_IN_FS\r\n\r\n    __HAL_RCC_GPIOB_CLK_ENABLE();\r\n\r\n    /*Configure GPIO for HS on FS mode*/\r\n    GPIO_InitStruct.Pin = GPIO_PIN_12 | GPIO_PIN_14 |GPIO_PIN_15;\r\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\r\n    GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;\r\n    GPIO_InitStruct.Alternate = GPIO_AF12_OTG_HS_FS;\r\n    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\r\n\r\n    if(hpcd->Init.vbus_sensing_enable == 1)\r\n    {\r\n      /* Configure VBUS Pin */\r\n      GPIO_InitStruct.Pin = GPIO_PIN_13 ;\r\n      GPIO_InitStruct.Mode = GPIO_MODE_INPUT;\r\n      GPIO_InitStruct.Pull = GPIO_NOPULL;\r\n      HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\r\n    }\r\n#else\r\n    /* Configure USB FS GPIOs */\r\n    __HAL_RCC_GPIOA_CLK_ENABLE();\r\n    __HAL_RCC_GPIOB_CLK_ENABLE();\r\n    __HAL_RCC_GPIOC_CLK_ENABLE();\r\n    __HAL_RCC_GPIOH_CLK_ENABLE();\r\n    __HAL_RCC_GPIOI_CLK_ENABLE();\r\n\r\n    /* CLK */\r\n    GPIO_InitStruct.Pin = GPIO_PIN_5;\r\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\r\n    GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;\r\n    GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;\r\n    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\r\n\r\n    /* D0 */\r\n    GPIO_InitStruct.Pin = GPIO_PIN_3;\r\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\r\n    GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;\r\n    GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;\r\n    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\r\n\r\n    /* D1 D2 D3 D4 D5 D6 D7 */\r\n    GPIO_InitStruct.Pin = GPIO_PIN_0  | GPIO_PIN_1  | GPIO_PIN_5 |\\\r\n      GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13;\r\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\r\n    GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;\r\n    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\r\n\r\n    /* STP */\r\n    GPIO_InitStruct.Pin = GPIO_PIN_0;\r\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\r\n    GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;\r\n    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);\r\n\r\n    /* NXT */\r\n    GPIO_InitStruct.Pin = GPIO_PIN_4;\r\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\r\n    GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;\r\n    HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);\r\n\r\n    /* DIR */\r\n    GPIO_InitStruct.Pin = GPIO_PIN_11;\r\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\r\n    GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;\r\n    HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);\r\n    __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE();\r\n#endif\r\n    /* Enable USB HS Clocks */\r\n    __HAL_RCC_USB_OTG_HS_CLK_ENABLE();\r\n\r\n    /* Set USBHS Interrupt to the lowest priority */\r\n    HAL_NVIC_SetPriority(OTG_HS_IRQn, 6, 0);\r\n\r\n    /* Enable USBHS Interrupt */\r\n    HAL_NVIC_EnableIRQ(OTG_HS_IRQn);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  De-Initializes the PCD MSP.\r\n  * @param  hpcd: PCD handle\r\n  * @retval None\r\n  */\r\nvoid HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)\r\n{\r\n  if(hpcd->Instance == USB_OTG_FS)\r\n  {\r\n    /* Disable USB FS Clock */\r\n    __HAL_RCC_USB_OTG_FS_CLK_DISABLE();\r\n    __HAL_RCC_SYSCFG_CLK_DISABLE();\r\n  }\r\n  else if(hpcd->Instance == USB_OTG_HS)\r\n  {\r\n    /* Disable USB HS Clocks */\r\n    __HAL_RCC_USB_OTG_HS_CLK_DISABLE();\r\n    __HAL_RCC_SYSCFG_CLK_DISABLE();\r\n  }\r\n}\r\n\r\n/*******************************************************************************\r\n                       LL Driver Callbacks (PCD -> USB Device Library)\r\n*******************************************************************************/\r\n\r\n/**\r\n  * @brief  SetupStage callback.\r\n  * @param  hpcd: PCD handle\r\n  * @retval None\r\n  */\r\nvoid HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)\r\n{\r\n  USBD_LL_SetupStage(hpcd->pData, (uint8_t *)hpcd->Setup);\r\n}\r\n\r\n/**\r\n  * @brief  DataOut Stage callback.\r\n  * @param  hpcd: PCD handle\r\n  * @param  epnum: Endpoint Number\r\n  * @retval None\r\n  */\r\nvoid HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\r\n{\r\n  USBD_LL_DataOutStage(hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff);\r\n}\r\n\r\n/**\r\n  * @brief  DataIn Stage callback.\r\n  * @param  hpcd: PCD handle\r\n  * @param  epnum: Endpoint Number\r\n  * @retval None\r\n  */\r\nvoid HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\r\n{\r\n  USBD_LL_DataInStage(hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff);\r\n}\r\n\r\n/**\r\n  * @brief  SOF callback.\r\n  * @param  hpcd: PCD handle\r\n  * @retval None\r\n  */\r\nextern void CDC_Itf_SofISR(void);\r\n\r\nvoid HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)\r\n{\r\n  USBD_LL_SOF(hpcd->pData);\r\n\r\n  // for USB CDC\r\n  CDC_Itf_SofISR();\r\n}\r\n\r\n/**\r\n  * @brief  Reset callback.\r\n  * @param  hpcd: PCD handle\r\n  * @retval None\r\n  */\r\nvoid HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)\r\n{\r\n  USBD_SpeedTypeDef speed = USBD_SPEED_FULL;\r\n\r\n  /* Set USB Current Speed */\r\n  switch(hpcd->Init.speed)\r\n  {\r\n  case PCD_SPEED_HIGH:\r\n    speed = USBD_SPEED_HIGH;\r\n    break;\r\n\r\n  case PCD_SPEED_FULL:\r\n    speed = USBD_SPEED_FULL;\r\n    break;\r\n\r\n  default:\r\n    speed = USBD_SPEED_FULL;\r\n    break;\r\n  }\r\n\r\n  /* Reset Device */\r\n  USBD_LL_Reset(hpcd->pData);\r\n\r\n  USBD_LL_SetSpeed(hpcd->pData, speed);\r\n}\r\n\r\n/**\r\n  * @brief  Suspend callback.\r\n  * @param  hpcd: PCD handle\r\n  * @retval None\r\n  */\r\nvoid HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)\r\n{\r\n  USBD_LL_Suspend(hpcd->pData);\r\n}\r\n\r\n/**\r\n  * @brief  Resume callback.\r\n  * @param  hpcd: PCD handle\r\n  * @retval None\r\n  */\r\nvoid HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)\r\n{\r\n  USBD_LL_Resume(hpcd->pData);\r\n}\r\n\r\n/**\r\n  * @brief  ISOOUTIncomplete callback.\r\n  * @param  hpcd: PCD handle\r\n  * @param  epnum: Endpoint Number\r\n  * @retval None\r\n  */\r\nvoid HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\r\n{\r\n  USBD_LL_IsoOUTIncomplete(hpcd->pData, epnum);\r\n}\r\n\r\n/**\r\n  * @brief  ISOINIncomplete callback.\r\n  * @param  hpcd: PCD handle\r\n  * @param  epnum: Endpoint Number\r\n  * @retval None\r\n  */\r\nvoid HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\r\n{\r\n  USBD_LL_IsoINIncomplete(hpcd->pData, epnum);\r\n}\r\n\r\n/**\r\n  * @brief  ConnectCallback callback.\r\n  * @param  hpcd: PCD handle\r\n  * @retval None\r\n  */\r\nvoid HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)\r\n{\r\n  USBD_LL_DevConnected(hpcd->pData);\r\n}\r\n\r\n/**\r\n  * @brief  Disconnect callback.\r\n  * @param  hpcd: PCD handle\r\n  * @retval None\r\n  */\r\nvoid HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)\r\n{\r\n  USBD_LL_DevDisconnected(hpcd->pData);\r\n}\r\n\r\n\r\n/*******************************************************************************\r\n                       LL Driver Interface (USB Device Library --> PCD)\r\n*******************************************************************************/\r\n\r\n/**\r\n  * @brief  Initializes the Low Level portion of the Device driver.\r\n  * @param  pdev: Device handle\r\n  * @retval USBD Status\r\n  */\r\nUSBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)\r\n{\r\n#ifdef USE_USB_FS\r\n  /* Set LL Driver parameters */\r\n  hpcd.Instance = USB_OTG_FS;\r\n  hpcd.Init.dev_endpoints = 4;\r\n  hpcd.Init.use_dedicated_ep1 = 0;\r\n  hpcd.Init.ep0_mps = 0x40;\r\n  hpcd.Init.dma_enable = 0;\r\n  hpcd.Init.low_power_enable = 0;\r\n  hpcd.Init.phy_itface = PCD_PHY_EMBEDDED;\r\n  hpcd.Init.Sof_enable = 1;\r\n  hpcd.Init.speed = PCD_SPEED_FULL;\r\n  hpcd.Init.vbus_sensing_enable = 0;\r\n  hpcd.Init.lpm_enable = 0;\r\n\r\n  /* Link The driver to the stack */\r\n  hpcd.pData = pdev;\r\n  pdev->pData = &hpcd;\r\n\r\n  /* Initialize LL Driver */\r\n  HAL_PCD_Init(&hpcd);\r\n\r\n  HAL_PCDEx_SetRxFiFo(&hpcd, 0x80);\r\n  HAL_PCDEx_SetTxFiFo(&hpcd, 0, 0x40);\r\n  HAL_PCDEx_SetTxFiFo(&hpcd, 1, 0x80);\r\n#endif\r\n\r\n#ifdef USE_USB_HS\r\n  /* Set LL Driver parameters */\r\n  hpcd.Instance = USB_OTG_HS;\r\n  hpcd.Init.dev_endpoints = 6;\r\n  hpcd.Init.use_dedicated_ep1 = 0;\r\n  hpcd.Init.ep0_mps = 0x40;\r\n\r\n  /* Be aware that enabling DMA mode will result in data being sent only by\r\n  multiple of 4 packet sizes. This is due to the fact that USB DMA does\r\n  not allow sending data from non word-aligned addresses.\r\n  For this specific application, it is advised to not enable this option\r\n  unless required. */\r\n  hpcd.Init.dma_enable = 0;\r\n  hpcd.Init.low_power_enable = 0;\r\n  hpcd.Init.lpm_enable = 0;\r\n\r\n#ifdef USE_USB_HS_IN_FS\r\n  hpcd.Init.phy_itface = PCD_PHY_EMBEDDED;\r\n#else\r\n  hpcd.Init.phy_itface = PCD_PHY_ULPI;\r\n#endif\r\n  hpcd.Init.Sof_enable = 0;\r\n  hpcd.Init.speed = PCD_SPEED_HIGH;\r\n  hpcd.Init.vbus_sensing_enable = 1;\r\n\r\n  /* Link The driver to the stack */\r\n  hpcd.pData = pdev;\r\n  pdev->pData = &hpcd;\r\n\r\n  /* Initialize LL Driver */\r\n  HAL_PCD_Init(&hpcd);\r\n\r\n  HAL_PCDEx_SetRxFiFo(&hpcd, 0x200);\r\n  HAL_PCDEx_SetTxFiFo(&hpcd, 0, 0x80);\r\n  HAL_PCDEx_SetTxFiFo(&hpcd, 1, 0x174);\r\n#endif\r\n\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  De-Initializes the Low Level portion of the Device driver.\r\n  * @param  pdev: Device handle\r\n  * @retval USBD Status\r\n  */\r\nUSBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev)\r\n{\r\n  HAL_PCD_DeInit(pdev->pData);\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the Low Level portion of the Device driver.\r\n  * @param  pdev: Device handle\r\n  * @retval USBD Status\r\n  */\r\nUSBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev)\r\n{\r\n  HAL_PCD_Start(pdev->pData);\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the Low Level portion of the Device driver.\r\n  * @param  pdev: Device handle\r\n  * @retval USBD Status\r\n  */\r\nUSBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev)\r\n{\r\n  HAL_PCD_Stop(pdev->pData);\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Opens an endpoint of the Low Level Driver.\r\n  * @param  pdev: Device handle\r\n  * @param  ep_addr: Endpoint Number\r\n  * @param  ep_type: Endpoint Type\r\n  * @param  ep_mps: Endpoint Max Packet Size\r\n  * @retval USBD Status\r\n  */\r\nUSBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev,\r\n                                  uint8_t ep_addr,\r\n                                  uint8_t ep_type,\r\n                                  uint16_t ep_mps)\r\n{\r\n  HAL_PCD_EP_Open(pdev->pData,\r\n                  ep_addr,\r\n                  ep_mps,\r\n                  ep_type);\r\n\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Closes an endpoint of the Low Level Driver.\r\n  * @param  pdev: Device handle\r\n  * @param  ep_addr: Endpoint Number\r\n  * @retval USBD Status\r\n  */\r\nUSBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)\r\n{\r\n  HAL_PCD_EP_Close(pdev->pData, ep_addr);\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Flushes an endpoint of the Low Level Driver.\r\n  * @param  pdev: Device handle\r\n  * @param  ep_addr: Endpoint Number\r\n  * @retval USBD Status\r\n  */\r\nUSBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)\r\n{\r\n  HAL_PCD_EP_Flush(pdev->pData, ep_addr);\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Sets a Stall condition on an endpoint of the Low Level Driver.\r\n  * @param  pdev: Device handle\r\n  * @param  ep_addr: Endpoint Number\r\n  * @retval USBD Status\r\n  */\r\nUSBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)\r\n{\r\n  HAL_PCD_EP_SetStall(pdev->pData, ep_addr);\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Clears a Stall condition on an endpoint of the Low Level Driver.\r\n  * @param  pdev: Device handle\r\n  * @param  ep_addr: Endpoint Number\r\n  * @retval USBD Status\r\n  */\r\nUSBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)\r\n{\r\n  HAL_PCD_EP_ClrStall(pdev->pData, ep_addr);\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Returns Stall condition.\r\n  * @param  pdev: Device handle\r\n  * @param  ep_addr: Endpoint Number\r\n  * @retval Stall (1: Yes, 0: No)\r\n  */\r\nuint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)\r\n{\r\n  PCD_HandleTypeDef *hpcd = pdev->pData;\r\n\r\n  if((ep_addr & 0x80) == 0x80)\r\n  {\r\n    return hpcd->IN_ep[ep_addr & 0x7F].is_stall;\r\n  }\r\n  else\r\n  {\r\n    return hpcd->OUT_ep[ep_addr & 0x7F].is_stall;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Assigns a USB address to the device.\r\n  * @param  pdev: Device handle\r\n  * @param  ep_addr: Endpoint Number\r\n  * @retval USBD Status\r\n  */\r\nUSBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr)\r\n{\r\n  HAL_PCD_SetAddress(pdev->pData, dev_addr);\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Transmits data over an endpoint.\r\n  * @param  pdev: Device handle\r\n  * @param  ep_addr: Endpoint Number\r\n  * @param  pbuf: Pointer to data to be sent\r\n  * @param  size: Data size\r\n  * @retval USBD Status\r\n  */\r\nUSBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev,\r\n                                    uint8_t ep_addr,\r\n                                    uint8_t *pbuf,\r\n                                    uint16_t size)\r\n{\r\n  HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size);\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Prepares an endpoint for reception.\r\n  * @param  pdev: Device handle\r\n  * @param  ep_addr: Endpoint Number\r\n  * @param  pbuf: Pointer to data to be received\r\n  * @param  size: Data size\r\n  * @retval USBD Status\r\n  */\r\nUSBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev,\r\n                                          uint8_t ep_addr,\r\n                                          uint8_t *pbuf,\r\n                                          uint16_t size)\r\n{\r\n  HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size);\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the last transferred packet size.\r\n  * @param  pdev: Device handle\r\n  * @param  ep_addr: Endpoint Number\r\n  * @retval Received Data Size\r\n  */\r\nuint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr)\r\n{\r\n  return HAL_PCD_EP_GetRxCount(pdev->pData, ep_addr);\r\n}\r\n\r\n/**\r\n  * @brief  Delays routine for the USB Device Library.\r\n  * @param  Delay: Delay in ms\r\n  * @retval None\r\n  */\r\nvoid USBD_LL_Delay(uint32_t Delay)\r\n{\r\n  HAL_Delay(Delay);\r\n}\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/usb_cdc/usbd_conf.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    USB_Device/CDC_Standalone/Inc/usbd_conf.h\r\n  * @author  MCD Application Team\r\n  * @version V1.0.3\r\n  * @date    18-November-2015\r\n  * @brief   General low level driver configuration\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __USBD_CONF_H\r\n#define __USBD_CONF_H\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n#include <stdio.h>\r\n#include <stdlib.h>\r\n#include <string.h>\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n/* Common Config */\r\n#define USBD_MAX_NUM_INTERFACES               1\r\n#define USBD_MAX_NUM_CONFIGURATION            1\r\n#define USBD_MAX_STR_DESC_SIZ                 0x100\r\n#define USBD_SUPPORT_USER_STRING              0 \r\n#define USBD_SELF_POWERED                     1\r\n#define USBD_DEBUG_LEVEL                      0\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Memory management macros */   \r\n#define USBD_malloc               malloc\r\n#define USBD_free                 free\r\n#define USBD_memset               memset\r\n#define USBD_memcpy               memcpy\r\n    \r\n/* DEBUG macros */  \r\n#if (USBD_DEBUG_LEVEL > 0)\r\n#define  USBD_UsrLog(...)   printf(__VA_ARGS__);\\\r\n                            printf(\"\\n\");\r\n#else\r\n#define USBD_UsrLog(...)   \r\n#endif                            \r\n                            \r\n#if (USBD_DEBUG_LEVEL > 1)\r\n\r\n#define  USBD_ErrLog(...)   printf(\"ERROR: \") ;\\\r\n                            printf(__VA_ARGS__);\\\r\n                            printf(\"\\n\");\r\n#else\r\n#define USBD_ErrLog(...)   \r\n#endif \r\n                                                        \r\n#if (USBD_DEBUG_LEVEL > 2)                         \r\n#define  USBD_DbgLog(...)   printf(\"DEBUG : \") ;\\\r\n                            printf(__VA_ARGS__);\\\r\n                            printf(\"\\n\");\r\n#else\r\n#define USBD_DbgLog(...)                         \r\n#endif\r\n\r\n/* Exported functions ------------------------------------------------------- */\r\n\r\n#endif /* __USBD_CONF_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/usb_cdc/usbd_core.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_core.c\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   This file provides all the USBD core functions.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_core.h\"\r\n\r\n/** @addtogroup STM32_USBD_DEVICE_LIBRARY\r\n* @{\r\n*/\r\n\r\n\r\n/** @defgroup USBD_CORE \r\n* @brief usbd core module\r\n* @{\r\n*/ \r\n\r\n/** @defgroup USBD_CORE_Private_TypesDefinitions\r\n* @{\r\n*/ \r\n/**\r\n* @}\r\n*/ \r\n\r\n\r\n/** @defgroup USBD_CORE_Private_Defines\r\n* @{\r\n*/ \r\n\r\n/**\r\n* @}\r\n*/ \r\n\r\n\r\n/** @defgroup USBD_CORE_Private_Macros\r\n* @{\r\n*/ \r\n/**\r\n* @}\r\n*/ \r\n\r\n\r\n\r\n\r\n/** @defgroup USBD_CORE_Private_FunctionPrototypes\r\n* @{\r\n*/ \r\n\r\n/**\r\n* @}\r\n*/ \r\n\r\n/** @defgroup USBD_CORE_Private_Variables\r\n* @{\r\n*/ \r\n\r\n/**\r\n* @}\r\n*/ \r\n\r\n/** @defgroup USBD_CORE_Private_Functions\r\n* @{\r\n*/ \r\n\r\n/**\r\n* @brief  USBD_Init\r\n*         Initializes the device stack and load the class driver\r\n* @param  pdev: device instance\r\n* @param  pdesc: Descriptor structure address\r\n* @param  id: Low level core index\r\n* @retval None\r\n*/\r\nUSBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id)\r\n{\r\n  /* Check whether the USB Host handle is valid */\r\n  if(pdev == NULL)\r\n  {\r\n    USBD_ErrLog(\"Invalid Device handle\");\r\n    return USBD_FAIL; \r\n  }\r\n  \r\n  /* Unlink previous class*/\r\n  if(pdev->pClass != NULL)\r\n  {\r\n    pdev->pClass = NULL;\r\n  }\r\n  \r\n  /* Assign USBD Descriptors */\r\n  if(pdesc != NULL)\r\n  {\r\n    pdev->pDesc = pdesc;\r\n  }\r\n  \r\n  /* Set Device initial State */\r\n  pdev->dev_state  = USBD_STATE_DEFAULT;\r\n  pdev->id = id;\r\n  /* Initialize low level driver */\r\n  USBD_LL_Init(pdev);\r\n  \r\n  return USBD_OK; \r\n}\r\n\r\n/**\r\n* @brief  USBD_DeInit \r\n*         Re-Initialize th device library\r\n* @param  pdev: device instance\r\n* @retval status: status\r\n*/\r\nUSBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev)\r\n{\r\n  /* Set Default State */\r\n  pdev->dev_state  = USBD_STATE_DEFAULT;\r\n  \r\n  /* Free Class Resources */\r\n  pdev->pClass->DeInit(pdev, pdev->dev_config);  \r\n  \r\n    /* Stop the low level driver  */\r\n  USBD_LL_Stop(pdev); \r\n  \r\n  /* Initialize low level driver */\r\n  USBD_LL_DeInit(pdev);\r\n  \r\n  return USBD_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  USBD_RegisterClass \r\n  *         Link class driver to Device Core.\r\n  * @param  pDevice : Device Handle\r\n  * @param  pclass: Class handle\r\n  * @retval USBD Status\r\n  */\r\nUSBD_StatusTypeDef  USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass)\r\n{\r\n  USBD_StatusTypeDef   status = USBD_OK;\r\n  if(pclass != 0)\r\n  {\r\n    /* link the class to the USB Device handle */\r\n    pdev->pClass = pclass;\r\n    status = USBD_OK;\r\n  }\r\n  else\r\n  {\r\n    USBD_ErrLog(\"Invalid Class handle\");\r\n    status = USBD_FAIL; \r\n  }\r\n  \r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_Start \r\n  *         Start the USB Device Core.\r\n  * @param  pdev: Device Handle\r\n  * @retval USBD Status\r\n  */\r\nUSBD_StatusTypeDef  USBD_Start  (USBD_HandleTypeDef *pdev)\r\n{\r\n  \r\n  /* Start the low level driver  */\r\n  USBD_LL_Start(pdev); \r\n  \r\n  return USBD_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  USBD_Stop \r\n  *         Stop the USB Device Core.\r\n  * @param  pdev: Device Handle\r\n  * @retval USBD Status\r\n  */\r\nUSBD_StatusTypeDef  USBD_Stop   (USBD_HandleTypeDef *pdev)\r\n{\r\n  /* Free Class Resources */\r\n  pdev->pClass->DeInit(pdev, pdev->dev_config);  \r\n\r\n  /* Stop the low level driver  */\r\n  USBD_LL_Stop(pdev); \r\n  \r\n  return USBD_OK;  \r\n}\r\n\r\n/**\r\n* @brief  USBD_RunTestMode \r\n*         Launch test mode process\r\n* @param  pdev: device instance\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef  USBD_RunTestMode (USBD_HandleTypeDef  *pdev) \r\n{\r\n  UNUSED(pdev);\r\n\r\n  return USBD_OK;\r\n}\r\n\r\n\r\n/**\r\n* @brief  USBD_SetClassConfig \r\n*        Configure device and start the interface\r\n* @param  pdev: device instance\r\n* @param  cfgidx: configuration index\r\n* @retval status\r\n*/\r\n\r\nUSBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef  *pdev, uint8_t cfgidx)\r\n{\r\n  USBD_StatusTypeDef   ret = USBD_FAIL;\r\n  \r\n  if(pdev->pClass != NULL)\r\n  {\r\n    /* Set configuration  and Start the Class*/\r\n    if(pdev->pClass->Init(pdev, cfgidx) == 0)\r\n    {\r\n      ret = USBD_OK;\r\n    }\r\n  }\r\n  return ret; \r\n}\r\n\r\n/**\r\n* @brief  USBD_ClrClassConfig \r\n*         Clear current configuration\r\n* @param  pdev: device instance\r\n* @param  cfgidx: configuration index\r\n* @retval status: USBD_StatusTypeDef\r\n*/\r\nUSBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef  *pdev, uint8_t cfgidx)\r\n{\r\n  /* Clear configuration  and De-initialize the Class process*/\r\n  pdev->pClass->DeInit(pdev, cfgidx);  \r\n  return USBD_OK;\r\n}\r\n\r\n\r\n/**\r\n* @brief  USBD_SetupStage \r\n*         Handle the setup stage\r\n* @param  pdev: device instance\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup)\r\n{\r\n\r\n  USBD_ParseSetupRequest(&pdev->request, psetup);\r\n  \r\n  pdev->ep0_state = USBD_EP0_SETUP;\r\n  pdev->ep0_data_len = pdev->request.wLength;\r\n  \r\n  switch (pdev->request.bmRequest & 0x1F) \r\n  {\r\n  case USB_REQ_RECIPIENT_DEVICE:   \r\n    USBD_StdDevReq (pdev, &pdev->request);\r\n    break;\r\n    \r\n  case USB_REQ_RECIPIENT_INTERFACE:     \r\n    USBD_StdItfReq(pdev, &pdev->request);\r\n    break;\r\n    \r\n  case USB_REQ_RECIPIENT_ENDPOINT:        \r\n    USBD_StdEPReq(pdev, &pdev->request);   \r\n    break;\r\n    \r\n  default:           \r\n    USBD_LL_StallEP(pdev , pdev->request.bmRequest & 0x80);\r\n    break;\r\n  }  \r\n  return USBD_OK;  \r\n}\r\n\r\n/**\r\n* @brief  USBD_DataOutStage \r\n*         Handle data OUT stage\r\n* @param  pdev: device instance\r\n* @param  epnum: endpoint index\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata)\r\n{\r\n  USBD_EndpointTypeDef    *pep;\r\n  \r\n  if(epnum == 0) \r\n  {\r\n    pep = &pdev->ep_out[0];\r\n    \r\n    if ( pdev->ep0_state == USBD_EP0_DATA_OUT)\r\n    {\r\n      if(pep->rem_length > pep->maxpacket)\r\n      {\r\n        pep->rem_length -=  pep->maxpacket;\r\n       \r\n        USBD_CtlContinueRx (pdev, \r\n                            pdata,\r\n                            MIN(pep->rem_length ,pep->maxpacket));\r\n      }\r\n      else\r\n      {\r\n        if((pdev->pClass->EP0_RxReady != NULL)&&\r\n           (pdev->dev_state == USBD_STATE_CONFIGURED))\r\n        {\r\n          pdev->pClass->EP0_RxReady(pdev); \r\n        }\r\n        USBD_CtlSendStatus(pdev);\r\n      }\r\n    }\r\n  }\r\n  else if((pdev->pClass->DataOut != NULL)&&\r\n          (pdev->dev_state == USBD_STATE_CONFIGURED))\r\n  {\r\n    pdev->pClass->DataOut(pdev, epnum); \r\n  }  \r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n* @brief  USBD_DataInStage \r\n*         Handle data in stage\r\n* @param  pdev: device instance\r\n* @param  epnum: endpoint index\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev ,uint8_t epnum, uint8_t *pdata)\r\n{\r\n  USBD_EndpointTypeDef    *pep;\r\n    \r\n  if(epnum == 0) \r\n  {\r\n    pep = &pdev->ep_in[0];\r\n    \r\n    if ( pdev->ep0_state == USBD_EP0_DATA_IN)\r\n    {\r\n      if(pep->rem_length > pep->maxpacket)\r\n      {\r\n        pep->rem_length -=  pep->maxpacket;\r\n        \r\n        USBD_CtlContinueSendData (pdev, \r\n                                  pdata, \r\n                                  pep->rem_length);\r\n        \r\n        /* Prepare endpoint for premature end of transfer */\r\n        USBD_LL_PrepareReceive (pdev,\r\n                                0,\r\n                                NULL,\r\n                                0);  \r\n      }\r\n      else\r\n      { /* last packet is MPS multiple, so send ZLP packet */\r\n        if((pep->total_length % pep->maxpacket == 0) &&\r\n           (pep->total_length >= pep->maxpacket) &&\r\n             (pep->total_length < pdev->ep0_data_len ))\r\n        {\r\n          \r\n          USBD_CtlContinueSendData(pdev , NULL, 0);\r\n          pdev->ep0_data_len = 0;\r\n          \r\n        /* Prepare endpoint for premature end of transfer */\r\n        USBD_LL_PrepareReceive (pdev,\r\n                                0,\r\n                                NULL,\r\n                                0);\r\n        }\r\n        else\r\n        {\r\n          if((pdev->pClass->EP0_TxSent != NULL)&&\r\n             (pdev->dev_state == USBD_STATE_CONFIGURED))\r\n          {\r\n            pdev->pClass->EP0_TxSent(pdev); \r\n          }          \r\n          USBD_CtlReceiveStatus(pdev);\r\n        }\r\n      }\r\n    }\r\n    if (pdev->dev_test_mode == 1)\r\n    {\r\n      USBD_RunTestMode(pdev); \r\n      pdev->dev_test_mode = 0;\r\n    }\r\n  }\r\n  else if((pdev->pClass->DataIn != NULL)&& \r\n          (pdev->dev_state == USBD_STATE_CONFIGURED))\r\n  {\r\n    pdev->pClass->DataIn(pdev, epnum); \r\n  }  \r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n* @brief  USBD_LL_Reset \r\n*         Handle Reset event\r\n* @param  pdev: device instance\r\n* @retval status\r\n*/\r\n\r\nUSBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef  *pdev)\r\n{\r\n  /* Open EP0 OUT */\r\n  USBD_LL_OpenEP(pdev,\r\n              0x00,\r\n              USBD_EP_TYPE_CTRL,\r\n              USB_MAX_EP0_SIZE);\r\n  \r\n  pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE;\r\n  \r\n  /* Open EP0 IN */\r\n  USBD_LL_OpenEP(pdev,\r\n              0x80,\r\n              USBD_EP_TYPE_CTRL,\r\n              USB_MAX_EP0_SIZE);\r\n  \r\n  pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE;\r\n  /* Upon Reset call user call back */\r\n  pdev->dev_state = USBD_STATE_DEFAULT;\r\n  \r\n  if (pdev->pClassData) \r\n    pdev->pClass->DeInit(pdev, pdev->dev_config);  \r\n \r\n  \r\n  return USBD_OK;\r\n}\r\n\r\n\r\n\r\n\r\n/**\r\n* @brief  USBD_LL_Reset \r\n*         Handle Reset event\r\n* @param  pdev: device instance\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef  *pdev, USBD_SpeedTypeDef speed)\r\n{\r\n  pdev->dev_speed = speed;\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n* @brief  USBD_Suspend \r\n*         Handle Suspend event\r\n* @param  pdev: device instance\r\n* @retval status\r\n*/\r\n\r\nUSBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef  *pdev)\r\n{\r\n  pdev->dev_old_state =  pdev->dev_state;\r\n  pdev->dev_state  = USBD_STATE_SUSPENDED;\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n* @brief  USBD_Resume \r\n*         Handle Resume event\r\n* @param  pdev: device instance\r\n* @retval status\r\n*/\r\n\r\nUSBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef  *pdev)\r\n{\r\n  pdev->dev_state = pdev->dev_old_state;  \r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n* @brief  USBD_SOF \r\n*         Handle SOF event\r\n* @param  pdev: device instance\r\n* @retval status\r\n*/\r\n\r\nUSBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef  *pdev)\r\n{\r\n  if(pdev->dev_state == USBD_STATE_CONFIGURED)\r\n  {\r\n    if(pdev->pClass->SOF != NULL)\r\n    {\r\n      pdev->pClass->SOF(pdev);\r\n    }\r\n  }\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n* @brief  USBD_IsoINIncomplete \r\n*         Handle iso in incomplete event\r\n* @param  pdev: device instance\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef  *pdev, uint8_t epnum)\r\n{\r\n  UNUSED(pdev);\r\n  UNUSED(epnum);\r\n\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n* @brief  USBD_IsoOUTIncomplete \r\n*         Handle iso out incomplete event\r\n* @param  pdev: device instance\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef  *pdev, uint8_t epnum)\r\n{\r\n  UNUSED(pdev);\r\n  UNUSED(epnum);\r\n\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n* @brief  USBD_DevConnected \r\n*         Handle device connection event\r\n* @param  pdev: device instance\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef  *pdev)\r\n{\r\n  UNUSED(pdev);\r\n\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n* @brief  USBD_DevDisconnected \r\n*         Handle device disconnection event\r\n* @param  pdev: device instance\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef  *pdev)\r\n{\r\n  /* Free Class Resources */\r\n  pdev->dev_state = USBD_STATE_DEFAULT;\r\n  pdev->pClass->DeInit(pdev, pdev->dev_config);  \r\n   \r\n  return USBD_OK;\r\n}\r\n/**\r\n* @}\r\n*/ \r\n\r\n\r\n/**\r\n* @}\r\n*/ \r\n\r\n\r\n/**\r\n* @}\r\n*/ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/usb_cdc/usbd_core.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_core.h\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   Header file for usbd_core.c file\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __USBD_CORE_H\r\n#define __USBD_CORE_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_conf.h\"\r\n#include \"usbd_def.h\"\r\n#include \"usbd_ioreq.h\"\r\n#include \"usbd_ctlreq.h\"\r\n\r\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup USBD_CORE\r\n  * @brief This file is the Header file for usbd_core.c file\r\n  * @{\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_CORE_Exported_Defines\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_CORE_Exported_TypesDefinitions\r\n  * @{\r\n  */\r\n \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n\r\n/** @defgroup USBD_CORE_Exported_Macros\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_CORE_Exported_Variables\r\n  * @{\r\n  */ \r\n#define USBD_SOF          USBD_LL_SOF\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_CORE_Exported_FunctionsPrototype\r\n  * @{\r\n  */ \r\nUSBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id);\r\nUSBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev);\r\nUSBD_StatusTypeDef USBD_Start  (USBD_HandleTypeDef *pdev);\r\nUSBD_StatusTypeDef USBD_Stop   (USBD_HandleTypeDef *pdev);\r\nUSBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass);\r\n\r\nUSBD_StatusTypeDef USBD_RunTestMode (USBD_HandleTypeDef  *pdev); \r\nUSBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef  *pdev, uint8_t cfgidx);\r\nUSBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef  *pdev, uint8_t cfgidx);\r\n\r\nUSBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup);\r\nUSBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata);\r\nUSBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata);\r\n\r\nUSBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef  *pdev);\r\nUSBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef  *pdev, USBD_SpeedTypeDef speed);\r\nUSBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef  *pdev);\r\nUSBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef  *pdev);\r\n\r\nUSBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef  *pdev);\r\nUSBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef  *pdev, uint8_t epnum);\r\nUSBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef  *pdev, uint8_t epnum);\r\n\r\nUSBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef  *pdev);\r\nUSBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef  *pdev);\r\n\r\n/* USBD Low Level Driver */\r\nUSBD_StatusTypeDef  USBD_LL_Init (USBD_HandleTypeDef *pdev);\r\nUSBD_StatusTypeDef  USBD_LL_DeInit (USBD_HandleTypeDef *pdev);\r\nUSBD_StatusTypeDef  USBD_LL_Start(USBD_HandleTypeDef *pdev);\r\nUSBD_StatusTypeDef  USBD_LL_Stop (USBD_HandleTypeDef *pdev);\r\nUSBD_StatusTypeDef  USBD_LL_OpenEP  (USBD_HandleTypeDef *pdev, \r\n                                      uint8_t  ep_addr,                                      \r\n                                      uint8_t  ep_type,\r\n                                      uint16_t ep_mps);\r\n\r\nUSBD_StatusTypeDef  USBD_LL_CloseEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr);   \r\nUSBD_StatusTypeDef  USBD_LL_FlushEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr);   \r\nUSBD_StatusTypeDef  USBD_LL_StallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr);   \r\nUSBD_StatusTypeDef  USBD_LL_ClearStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr);   \r\nuint8_t             USBD_LL_IsStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr);   \r\nUSBD_StatusTypeDef  USBD_LL_SetUSBAddress (USBD_HandleTypeDef *pdev, uint8_t dev_addr);   \r\nUSBD_StatusTypeDef  USBD_LL_Transmit (USBD_HandleTypeDef *pdev, \r\n                                      uint8_t  ep_addr,                                      \r\n                                      uint8_t  *pbuf,\r\n                                      uint16_t  size);\r\n\r\nUSBD_StatusTypeDef  USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, \r\n                                           uint8_t  ep_addr,                                      \r\n                                           uint8_t  *pbuf,\r\n                                           uint16_t  size);\r\n\r\nuint32_t USBD_LL_GetRxDataSize  (USBD_HandleTypeDef *pdev, uint8_t  ep_addr);  \r\nvoid  USBD_LL_Delay (uint32_t Delay);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __USBD_CORE_H */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n* @}\r\n*/ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n\r\n\r\n\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/usb_cdc/usbd_ctlreq.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_req.c\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015 \r\n  * @brief   This file provides the standard USB requests following chapter 9.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_ctlreq.h\"\r\n#include \"usbd_ioreq.h\"\r\n\r\n\r\n/** @addtogroup STM32_USBD_STATE_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n\r\n\r\n/** @defgroup USBD_REQ \r\n  * @brief USB standard requests module\r\n  * @{\r\n  */ \r\n\r\n/** @defgroup USBD_REQ_Private_TypesDefinitions\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_REQ_Private_Defines\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_REQ_Private_Macros\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_REQ_Private_Variables\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_REQ_Private_FunctionPrototypes\r\n  * @{\r\n  */ \r\nstatic void USBD_GetDescriptor(USBD_HandleTypeDef *pdev , \r\n                               USBD_SetupReqTypedef *req);\r\n\r\nstatic void USBD_SetAddress(USBD_HandleTypeDef *pdev , \r\n                            USBD_SetupReqTypedef *req);\r\n\r\nstatic void USBD_SetConfig(USBD_HandleTypeDef *pdev , \r\n                           USBD_SetupReqTypedef *req);\r\n\r\nstatic void USBD_GetConfig(USBD_HandleTypeDef *pdev , \r\n                           USBD_SetupReqTypedef *req);\r\n\r\nstatic void USBD_GetStatus(USBD_HandleTypeDef *pdev , \r\n                           USBD_SetupReqTypedef *req);\r\n\r\nstatic void USBD_SetFeature(USBD_HandleTypeDef *pdev , \r\n                            USBD_SetupReqTypedef *req);\r\n\r\nstatic void USBD_ClrFeature(USBD_HandleTypeDef *pdev , \r\n                            USBD_SetupReqTypedef *req);\r\n\r\nstatic uint8_t USBD_GetLen(uint8_t *buf);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_REQ_Private_Functions\r\n  * @{\r\n  */ \r\n\r\n\r\n/**\r\n* @brief  USBD_StdDevReq\r\n*         Handle standard usb device requests\r\n* @param  pdev: device instance\r\n* @param  req: usb request\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef  USBD_StdDevReq (USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef  *req)\r\n{\r\n  USBD_StatusTypeDef ret = USBD_OK;  \r\n  \r\n  switch (req->bRequest) \r\n  {\r\n  case USB_REQ_GET_DESCRIPTOR: \r\n    \r\n    USBD_GetDescriptor (pdev, req) ;\r\n    break;\r\n    \r\n  case USB_REQ_SET_ADDRESS:                      \r\n    USBD_SetAddress(pdev, req);\r\n    break;\r\n    \r\n  case USB_REQ_SET_CONFIGURATION:                    \r\n    USBD_SetConfig (pdev , req);\r\n    break;\r\n    \r\n  case USB_REQ_GET_CONFIGURATION:                 \r\n    USBD_GetConfig (pdev , req);\r\n    break;\r\n    \r\n  case USB_REQ_GET_STATUS:                                  \r\n    USBD_GetStatus (pdev , req);\r\n    break;\r\n    \r\n    \r\n  case USB_REQ_SET_FEATURE:   \r\n    USBD_SetFeature (pdev , req);    \r\n    break;\r\n    \r\n  case USB_REQ_CLEAR_FEATURE:                                   \r\n    USBD_ClrFeature (pdev , req);\r\n    break;\r\n    \r\n  default:  \r\n    USBD_CtlError(pdev , req);\r\n    break;\r\n  }\r\n  \r\n  return ret;\r\n}\r\n\r\n/**\r\n* @brief  USBD_StdItfReq\r\n*         Handle standard usb interface requests\r\n* @param  pdev: device instance\r\n* @param  req: usb request\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef  USBD_StdItfReq (USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef  *req)\r\n{\r\n  USBD_StatusTypeDef ret = USBD_OK; \r\n  \r\n  switch (pdev->dev_state) \r\n  {\r\n  case USBD_STATE_CONFIGURED:\r\n    \r\n    if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES) \r\n    {\r\n      pdev->pClass->Setup (pdev, req); \r\n      \r\n      if((req->wLength == 0)&& (ret == USBD_OK))\r\n      {\r\n         USBD_CtlSendStatus(pdev);\r\n      }\r\n    } \r\n    else \r\n    {                                               \r\n       USBD_CtlError(pdev , req);\r\n    }\r\n    break;\r\n    \r\n  default:\r\n     USBD_CtlError(pdev , req);\r\n    break;\r\n  }\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n* @brief  USBD_StdEPReq\r\n*         Handle standard usb endpoint requests\r\n* @param  pdev: device instance\r\n* @param  req: usb request\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef  USBD_StdEPReq (USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef  *req)\r\n{\r\n  \r\n  uint8_t   ep_addr;\r\n  USBD_StatusTypeDef ret = USBD_OK; \r\n  USBD_EndpointTypeDef   *pep;\r\n  ep_addr  = LOBYTE(req->wIndex);   \r\n  \r\n  /* Check if it is a class request */\r\n  if ((req->bmRequest & 0x60) == 0x20)\r\n  {\r\n    pdev->pClass->Setup (pdev, req);\r\n    \r\n    return USBD_OK;\r\n  }\r\n  \r\n  switch (req->bRequest) \r\n  {\r\n    \r\n  case USB_REQ_SET_FEATURE :\r\n    \r\n    switch (pdev->dev_state) \r\n    {\r\n    case USBD_STATE_ADDRESSED:          \r\n      if ((ep_addr != 0x00) && (ep_addr != 0x80)) \r\n      {\r\n        USBD_LL_StallEP(pdev , ep_addr);\r\n      }\r\n      break;\t\r\n      \r\n    case USBD_STATE_CONFIGURED:   \r\n      if (req->wValue == USB_FEATURE_EP_HALT)\r\n      {\r\n        if ((ep_addr != 0x00) && (ep_addr != 0x80)) \r\n        { \r\n          USBD_LL_StallEP(pdev , ep_addr);\r\n          \r\n        }\r\n      }\r\n      pdev->pClass->Setup (pdev, req);   \r\n      USBD_CtlSendStatus(pdev);\r\n      \r\n      break;\r\n      \r\n    default:                         \r\n      USBD_CtlError(pdev , req);\r\n      break;    \r\n    }\r\n    break;\r\n    \r\n  case USB_REQ_CLEAR_FEATURE :\r\n    \r\n    switch (pdev->dev_state) \r\n    {\r\n    case USBD_STATE_ADDRESSED:          \r\n      if ((ep_addr != 0x00) && (ep_addr != 0x80)) \r\n      {\r\n        USBD_LL_StallEP(pdev , ep_addr);\r\n      }\r\n      break;\t\r\n      \r\n    case USBD_STATE_CONFIGURED:   \r\n      if (req->wValue == USB_FEATURE_EP_HALT)\r\n      {\r\n        if ((ep_addr & 0x7F) != 0x00) \r\n        {        \r\n          USBD_LL_ClearStallEP(pdev , ep_addr);\r\n          pdev->pClass->Setup (pdev, req);\r\n        }\r\n        USBD_CtlSendStatus(pdev);\r\n      }\r\n      break;\r\n      \r\n    default:                         \r\n      USBD_CtlError(pdev , req);\r\n      break;    \r\n    }\r\n    break;\r\n    \r\n  case USB_REQ_GET_STATUS:                  \r\n    switch (pdev->dev_state) \r\n    {\r\n    case USBD_STATE_ADDRESSED:          \r\n      if ((ep_addr & 0x7F) != 0x00) \r\n      {\r\n        USBD_LL_StallEP(pdev , ep_addr);\r\n      }\r\n      break;\t\r\n      \r\n    case USBD_STATE_CONFIGURED:\r\n      pep = ((ep_addr & 0x80) == 0x80) ? &pdev->ep_in[ep_addr & 0x7F]:\\\r\n                                         &pdev->ep_out[ep_addr & 0x7F];\r\n      if(USBD_LL_IsStallEP(pdev, ep_addr))\r\n      {\r\n        pep->status = 0x0001;     \r\n      }\r\n      else\r\n      {\r\n        pep->status = 0x0000;  \r\n      }\r\n      \r\n      USBD_CtlSendData (pdev,\r\n                        (uint8_t *)&pep->status,\r\n                        2);\r\n      break;\r\n      \r\n    default:                         \r\n      USBD_CtlError(pdev , req);\r\n      break;\r\n    }\r\n    break;\r\n    \r\n  default:\r\n    break;\r\n  }\r\n  return ret;\r\n}\r\n/**\r\n* @brief  USBD_GetDescriptor\r\n*         Handle Get Descriptor requests\r\n* @param  pdev: device instance\r\n* @param  req: usb request\r\n* @retval status\r\n*/\r\nstatic void USBD_GetDescriptor(USBD_HandleTypeDef *pdev , \r\n                               USBD_SetupReqTypedef *req)\r\n{\r\n  uint16_t len;\r\n  uint8_t *pbuf;\r\n  \r\n    \r\n  switch (req->wValue >> 8)\r\n  { \r\n#if (USBD_LPM_ENABLED == 1)\r\n  case USB_DESC_TYPE_BOS:\r\n    pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len);\r\n    break;\r\n#endif    \r\n  case USB_DESC_TYPE_DEVICE:\r\n    pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len);\r\n    break;\r\n    \r\n  case USB_DESC_TYPE_CONFIGURATION:     \r\n    if(pdev->dev_speed == USBD_SPEED_HIGH )   \r\n    {\r\n      pbuf   = (uint8_t *)pdev->pClass->GetHSConfigDescriptor(&len);\r\n      pbuf[1] = USB_DESC_TYPE_CONFIGURATION;\r\n    }\r\n    else\r\n    {\r\n      pbuf   = (uint8_t *)pdev->pClass->GetFSConfigDescriptor(&len);\r\n      pbuf[1] = USB_DESC_TYPE_CONFIGURATION;\r\n    }\r\n    break;\r\n    \r\n  case USB_DESC_TYPE_STRING:\r\n    switch ((uint8_t)(req->wValue))\r\n    {\r\n    case USBD_IDX_LANGID_STR:\r\n     pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len);        \r\n      break;\r\n      \r\n    case USBD_IDX_MFC_STR:\r\n      pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len);\r\n      break;\r\n      \r\n    case USBD_IDX_PRODUCT_STR:\r\n      pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len);\r\n      break;\r\n      \r\n    case USBD_IDX_SERIAL_STR:\r\n      pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len);\r\n      break;\r\n      \r\n    case USBD_IDX_CONFIG_STR:\r\n      pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len);\r\n      break;\r\n      \r\n    case USBD_IDX_INTERFACE_STR:\r\n      pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len);\r\n      break;\r\n      \r\n    default:\r\n#if (USBD_SUPPORT_USER_STRING == 1)\r\n      pbuf = pdev->pClass->GetUsrStrDescriptor(pdev, (req->wValue) , &len);\r\n      break;\r\n#else      \r\n       USBD_CtlError(pdev , req);\r\n      return;\r\n#endif   \r\n    }\r\n    break;\r\n  case USB_DESC_TYPE_DEVICE_QUALIFIER:                   \r\n\r\n    if(pdev->dev_speed == USBD_SPEED_HIGH  )   \r\n    {\r\n      pbuf   = (uint8_t *)pdev->pClass->GetDeviceQualifierDescriptor(&len);\r\n      break;\r\n    }\r\n    else\r\n    {\r\n      USBD_CtlError(pdev , req);\r\n      return;\r\n    } \r\n\r\n  case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION:\r\n    if(pdev->dev_speed == USBD_SPEED_HIGH  )   \r\n    {\r\n      pbuf   = (uint8_t *)pdev->pClass->GetOtherSpeedConfigDescriptor(&len);\r\n      pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION;\r\n      break; \r\n    }\r\n    else\r\n    {\r\n      USBD_CtlError(pdev , req);\r\n      return;\r\n    }\r\n\r\n  default: \r\n     USBD_CtlError(pdev , req);\r\n    return;\r\n  }\r\n  \r\n  if((len != 0)&& (req->wLength != 0))\r\n  {\r\n    \r\n    len = MIN(len , req->wLength);\r\n    \r\n    USBD_CtlSendData (pdev, \r\n                      pbuf,\r\n                      len);\r\n  }\r\n  \r\n}\r\n\r\n/**\r\n* @brief  USBD_SetAddress\r\n*         Set device address\r\n* @param  pdev: device instance\r\n* @param  req: usb request\r\n* @retval status\r\n*/\r\nstatic void USBD_SetAddress(USBD_HandleTypeDef *pdev , \r\n                            USBD_SetupReqTypedef *req)\r\n{\r\n  uint8_t  dev_addr; \r\n  \r\n  if ((req->wIndex == 0) && (req->wLength == 0)) \r\n  {\r\n    dev_addr = (uint8_t)(req->wValue) & 0x7F;     \r\n    \r\n    if (pdev->dev_state == USBD_STATE_CONFIGURED) \r\n    {\r\n      USBD_CtlError(pdev , req);\r\n    } \r\n    else \r\n    {\r\n      pdev->dev_address = dev_addr;\r\n      USBD_LL_SetUSBAddress(pdev, dev_addr);               \r\n      USBD_CtlSendStatus(pdev);                         \r\n      \r\n      if (dev_addr != 0) \r\n      {\r\n        pdev->dev_state  = USBD_STATE_ADDRESSED;\r\n      } \r\n      else \r\n      {\r\n        pdev->dev_state  = USBD_STATE_DEFAULT; \r\n      }\r\n    }\r\n  } \r\n  else \r\n  {\r\n     USBD_CtlError(pdev , req);                        \r\n  } \r\n}\r\n\r\n/**\r\n* @brief  USBD_SetConfig\r\n*         Handle Set device configuration request\r\n* @param  pdev: device instance\r\n* @param  req: usb request\r\n* @retval status\r\n*/\r\nstatic void USBD_SetConfig(USBD_HandleTypeDef *pdev , \r\n                           USBD_SetupReqTypedef *req)\r\n{\r\n  \r\n  static uint8_t  cfgidx;\r\n  \r\n  cfgidx = (uint8_t)(req->wValue);                 \r\n  \r\n  if (cfgidx > USBD_MAX_NUM_CONFIGURATION ) \r\n  {            \r\n     USBD_CtlError(pdev , req);                              \r\n  } \r\n  else \r\n  {\r\n    switch (pdev->dev_state) \r\n    {\r\n    case USBD_STATE_ADDRESSED:\r\n      if (cfgidx) \r\n      {                                \t\t\t   \t\t\t\t\t\t\t   \t\t\t\t\t\t\t   \t\t\t\t\r\n        pdev->dev_config = cfgidx;\r\n        pdev->dev_state = USBD_STATE_CONFIGURED;\r\n        if(USBD_SetClassConfig(pdev , cfgidx) == USBD_FAIL)\r\n        {\r\n          USBD_CtlError(pdev , req);  \r\n          return;\r\n        }\r\n        USBD_CtlSendStatus(pdev);\r\n      }\r\n      else \r\n      {\r\n         USBD_CtlSendStatus(pdev);\r\n      }\r\n      break;\r\n      \r\n    case USBD_STATE_CONFIGURED:\r\n      if (cfgidx == 0) \r\n      {                           \r\n        pdev->dev_state = USBD_STATE_ADDRESSED;\r\n        pdev->dev_config = cfgidx;          \r\n        USBD_ClrClassConfig(pdev , cfgidx);\r\n        USBD_CtlSendStatus(pdev);\r\n        \r\n      } \r\n      else  if (cfgidx != pdev->dev_config) \r\n      {\r\n        /* Clear old configuration */\r\n        USBD_ClrClassConfig(pdev , pdev->dev_config);\r\n        \r\n        /* set new configuration */\r\n        pdev->dev_config = cfgidx;\r\n        if(USBD_SetClassConfig(pdev , cfgidx) == USBD_FAIL)\r\n        {\r\n          USBD_CtlError(pdev , req);  \r\n          return;\r\n        }\r\n        USBD_CtlSendStatus(pdev);\r\n      }\r\n      else\r\n      {\r\n        USBD_CtlSendStatus(pdev);\r\n      }\r\n      break;\r\n      \r\n    default:\t\t\t\t\t\r\n       USBD_CtlError(pdev , req);                     \r\n      break;\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n* @brief  USBD_GetConfig\r\n*         Handle Get device configuration request\r\n* @param  pdev: device instance\r\n* @param  req: usb request\r\n* @retval status\r\n*/\r\nstatic void USBD_GetConfig(USBD_HandleTypeDef *pdev , \r\n                           USBD_SetupReqTypedef *req)\r\n{\r\n\r\n  if (req->wLength != 1) \r\n  {                   \r\n     USBD_CtlError(pdev , req);\r\n  }\r\n  else \r\n  {\r\n    switch (pdev->dev_state )  \r\n    {\r\n    case USBD_STATE_ADDRESSED:                     \r\n      pdev->dev_default_config = 0;\r\n      USBD_CtlSendData (pdev, \r\n                        (uint8_t *)&pdev->dev_default_config,\r\n                        1);\r\n      break;\r\n      \r\n    case USBD_STATE_CONFIGURED:   \r\n      \r\n      USBD_CtlSendData (pdev, \r\n                        (uint8_t *)&pdev->dev_config,\r\n                        1);\r\n      break;\r\n      \r\n    default:\r\n       USBD_CtlError(pdev , req);\r\n      break;\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n* @brief  USBD_GetStatus\r\n*         Handle Get Status request\r\n* @param  pdev: device instance\r\n* @param  req: usb request\r\n* @retval status\r\n*/\r\nstatic void USBD_GetStatus(USBD_HandleTypeDef *pdev , \r\n                           USBD_SetupReqTypedef *req)\r\n{\r\n  \r\n    \r\n  switch (pdev->dev_state) \r\n  {\r\n  case USBD_STATE_ADDRESSED:\r\n  case USBD_STATE_CONFIGURED:\r\n    \r\n#if ( USBD_SELF_POWERED == 1)\r\n    pdev->dev_config_status = USB_CONFIG_SELF_POWERED;                                  \r\n#else\r\n    pdev->dev_config_status = 0;                                   \r\n#endif\r\n                      \r\n    if (pdev->dev_remote_wakeup) \r\n    {\r\n       pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP;                                \r\n    }\r\n    \r\n    USBD_CtlSendData (pdev, \r\n                      (uint8_t *)& pdev->dev_config_status,\r\n                      2);\r\n    break;\r\n    \r\n  default :\r\n    USBD_CtlError(pdev , req);                        \r\n    break;\r\n  }\r\n}\r\n\r\n\r\n/**\r\n* @brief  USBD_SetFeature\r\n*         Handle Set device feature request\r\n* @param  pdev: device instance\r\n* @param  req: usb request\r\n* @retval status\r\n*/\r\nstatic void USBD_SetFeature(USBD_HandleTypeDef *pdev , \r\n                            USBD_SetupReqTypedef *req)\r\n{\r\n\r\n  if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)\r\n  {\r\n    pdev->dev_remote_wakeup = 1;  \r\n    pdev->pClass->Setup (pdev, req);   \r\n    USBD_CtlSendStatus(pdev);\r\n  }\r\n\r\n}\r\n\r\n\r\n/**\r\n* @brief  USBD_ClrFeature\r\n*         Handle clear device feature request\r\n* @param  pdev: device instance\r\n* @param  req: usb request\r\n* @retval status\r\n*/\r\nstatic void USBD_ClrFeature(USBD_HandleTypeDef *pdev , \r\n                            USBD_SetupReqTypedef *req)\r\n{\r\n  switch (pdev->dev_state)\r\n  {\r\n  case USBD_STATE_ADDRESSED:\r\n  case USBD_STATE_CONFIGURED:\r\n    if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) \r\n    {\r\n      pdev->dev_remote_wakeup = 0; \r\n      pdev->pClass->Setup (pdev, req);   \r\n      USBD_CtlSendStatus(pdev);\r\n    }\r\n    break;\r\n    \r\n  default :\r\n     USBD_CtlError(pdev , req);\r\n    break;\r\n  }\r\n}\r\n\r\n/**\r\n* @brief  USBD_ParseSetupRequest \r\n*         Copy buffer into setup structure\r\n* @param  pdev: device instance\r\n* @param  req: usb request\r\n* @retval None\r\n*/\r\n\r\nvoid USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata)\r\n{\r\n  req->bmRequest     = *(uint8_t *)  (pdata);\r\n  req->bRequest      = *(uint8_t *)  (pdata +  1);\r\n  req->wValue        = SWAPBYTE      (pdata +  2);\r\n  req->wIndex        = SWAPBYTE      (pdata +  4);\r\n  req->wLength       = SWAPBYTE      (pdata +  6);\r\n\r\n}\r\n\r\n/**\r\n* @brief  USBD_CtlError \r\n*         Handle USB low level Error\r\n* @param  pdev: device instance\r\n* @param  req: usb request\r\n* @retval None\r\n*/\r\n\r\nvoid USBD_CtlError( USBD_HandleTypeDef *pdev ,\r\n                            USBD_SetupReqTypedef *req)\r\n{\r\n  UNUSED(req);\r\n\r\n  USBD_LL_StallEP(pdev , 0x80);\r\n  USBD_LL_StallEP(pdev , 0);\r\n}\r\n\r\n\r\n/**\r\n  * @brief  USBD_GetString\r\n  *         Convert Ascii string into unicode one\r\n  * @param  desc : descriptor buffer\r\n  * @param  unicode : Formatted string buffer (unicode)\r\n  * @param  len : descriptor length\r\n  * @retval None\r\n  */\r\nvoid USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len)\r\n{\r\n  uint8_t idx = 0;\r\n  \r\n  if (desc != NULL) \r\n  {\r\n    *len =  USBD_GetLen(desc) * 2 + 2;    \r\n    unicode[idx++] = *len;\r\n    unicode[idx++] =  USB_DESC_TYPE_STRING;\r\n    \r\n    while (*desc != '\\0') \r\n    {\r\n      unicode[idx++] = *desc++;\r\n      unicode[idx++] =  0x00;\r\n    }\r\n  } \r\n}\r\n\r\n/**\r\n  * @brief  USBD_GetLen\r\n  *         return the string length\r\n   * @param  buf : pointer to the ascii string buffer\r\n  * @retval string length\r\n  */\r\nstatic uint8_t USBD_GetLen(uint8_t *buf)\r\n{\r\n    uint8_t  len = 0;\r\n\r\n    while (*buf != '\\0') \r\n    {\r\n        len++;\r\n        buf++;\r\n    }\r\n\r\n    return len;\r\n}\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/usb_cdc/usbd_ctlreq.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_req.h\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   Header file for the usbd_req.c file\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __USB_REQUEST_H\r\n#define __USB_REQUEST_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include  \"usbd_def.h\"\r\n\r\n\r\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup USBD_REQ\r\n  * @brief header file for the usbd_req.c file\r\n  * @{\r\n  */ \r\n\r\n/** @defgroup USBD_REQ_Exported_Defines\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_REQ_Exported_Types\r\n  * @{\r\n  */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n\r\n/** @defgroup USBD_REQ_Exported_Macros\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_REQ_Exported_Variables\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_REQ_Exported_FunctionsPrototype\r\n  * @{\r\n  */ \r\n\r\nUSBD_StatusTypeDef  USBD_StdDevReq (USBD_HandleTypeDef  *pdev, USBD_SetupReqTypedef  *req);\r\nUSBD_StatusTypeDef  USBD_StdItfReq (USBD_HandleTypeDef  *pdev, USBD_SetupReqTypedef  *req);\r\nUSBD_StatusTypeDef  USBD_StdEPReq  (USBD_HandleTypeDef  *pdev, USBD_SetupReqTypedef  *req);\r\n\r\n\r\nvoid USBD_CtlError  (USBD_HandleTypeDef  *pdev, USBD_SetupReqTypedef *req);\r\n\r\nvoid USBD_ParseSetupRequest (USBD_SetupReqTypedef *req, uint8_t *pdata);\r\n\r\nvoid USBD_GetString         (uint8_t *desc, uint8_t *unicode, uint16_t *len);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __USB_REQUEST_H */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n* @}\r\n*/ \r\n\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/usb_cdc/usbd_def.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_def.h\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   General defines for the usb device library \r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __USBD_DEF_H\r\n#define __USBD_DEF_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_conf.h\"\r\n\r\n/** @addtogroup STM32_USBD_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup USB_DEF\r\n  * @brief general defines for the usb device library file\r\n  * @{\r\n  */ \r\n\r\n/** @defgroup USB_DEF_Exported_Defines\r\n  * @{\r\n  */ \r\n\r\n#ifndef NULL\r\n#define NULL  0\r\n#endif\r\n\r\n\r\n#define  USB_LEN_DEV_QUALIFIER_DESC                     0x0A\r\n#define  USB_LEN_DEV_DESC                               0x12\r\n#define  USB_LEN_CFG_DESC                               0x09\r\n#define  USB_LEN_IF_DESC                                0x09\r\n#define  USB_LEN_EP_DESC                                0x07\r\n#define  USB_LEN_OTG_DESC                               0x03\r\n#define  USB_LEN_LANGID_STR_DESC                        0x04\r\n#define  USB_LEN_OTHER_SPEED_DESC_SIZ                   0x09\r\n\r\n#define  USBD_IDX_LANGID_STR                            0x00 \r\n#define  USBD_IDX_MFC_STR                               0x01 \r\n#define  USBD_IDX_PRODUCT_STR                           0x02\r\n#define  USBD_IDX_SERIAL_STR                            0x03 \r\n#define  USBD_IDX_CONFIG_STR                            0x04 \r\n#define  USBD_IDX_INTERFACE_STR                         0x05 \r\n\r\n#define  USB_REQ_TYPE_STANDARD                          0x00\r\n#define  USB_REQ_TYPE_CLASS                             0x20\r\n#define  USB_REQ_TYPE_VENDOR                            0x40\r\n#define  USB_REQ_TYPE_MASK                              0x60\r\n\r\n#define  USB_REQ_RECIPIENT_DEVICE                       0x00\r\n#define  USB_REQ_RECIPIENT_INTERFACE                    0x01\r\n#define  USB_REQ_RECIPIENT_ENDPOINT                     0x02\r\n#define  USB_REQ_RECIPIENT_MASK                         0x03\r\n\r\n#define  USB_REQ_GET_STATUS                             0x00\r\n#define  USB_REQ_CLEAR_FEATURE                          0x01\r\n#define  USB_REQ_SET_FEATURE                            0x03\r\n#define  USB_REQ_SET_ADDRESS                            0x05\r\n#define  USB_REQ_GET_DESCRIPTOR                         0x06\r\n#define  USB_REQ_SET_DESCRIPTOR                         0x07\r\n#define  USB_REQ_GET_CONFIGURATION                      0x08\r\n#define  USB_REQ_SET_CONFIGURATION                      0x09\r\n#define  USB_REQ_GET_INTERFACE                          0x0A\r\n#define  USB_REQ_SET_INTERFACE                          0x0B\r\n#define  USB_REQ_SYNCH_FRAME                            0x0C\r\n\r\n#define  USB_DESC_TYPE_DEVICE                              1\r\n#define  USB_DESC_TYPE_CONFIGURATION                       2\r\n#define  USB_DESC_TYPE_STRING                              3\r\n#define  USB_DESC_TYPE_INTERFACE                           4\r\n#define  USB_DESC_TYPE_ENDPOINT                            5\r\n#define  USB_DESC_TYPE_DEVICE_QUALIFIER                    6\r\n#define  USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION           7\r\n#define  USB_DESC_TYPE_BOS                                 0x0F\r\n\r\n#define USB_CONFIG_REMOTE_WAKEUP                           2\r\n#define USB_CONFIG_SELF_POWERED                            1\r\n\r\n#define USB_FEATURE_EP_HALT                                0\r\n#define USB_FEATURE_REMOTE_WAKEUP                          1\r\n#define USB_FEATURE_TEST_MODE                              2\r\n\r\n#define USB_DEVICE_CAPABITY_TYPE                           0x10\r\n\r\n#define USB_HS_MAX_PACKET_SIZE                            512\r\n#define USB_FS_MAX_PACKET_SIZE                            64\r\n#define USB_MAX_EP0_SIZE                                  64\r\n\r\n/*  Device Status */\r\n#define USBD_STATE_DEFAULT                                1\r\n#define USBD_STATE_ADDRESSED                              2\r\n#define USBD_STATE_CONFIGURED                             3\r\n#define USBD_STATE_SUSPENDED                              4\r\n\r\n\r\n/*  EP0 State */    \r\n#define USBD_EP0_IDLE                                     0\r\n#define USBD_EP0_SETUP                                    1\r\n#define USBD_EP0_DATA_IN                                  2\r\n#define USBD_EP0_DATA_OUT                                 3\r\n#define USBD_EP0_STATUS_IN                                4\r\n#define USBD_EP0_STATUS_OUT                               5\r\n#define USBD_EP0_STALL                                    6    \r\n\r\n#define USBD_EP_TYPE_CTRL                                 0\r\n#define USBD_EP_TYPE_ISOC                                 1\r\n#define USBD_EP_TYPE_BULK                                 2\r\n#define USBD_EP_TYPE_INTR                                 3\r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_DEF_Exported_TypesDefinitions\r\n  * @{\r\n  */\r\n\r\ntypedef  struct  usb_setup_req \r\n{\r\n    \r\n    uint8_t   bmRequest;                      \r\n    uint8_t   bRequest;                           \r\n    uint16_t  wValue;                             \r\n    uint16_t  wIndex;                             \r\n    uint16_t  wLength;                            \r\n}USBD_SetupReqTypedef;\r\n\r\nstruct _USBD_HandleTypeDef;\r\n    \r\ntypedef struct _Device_cb\r\n{\r\n  uint8_t  (*Init)             (struct _USBD_HandleTypeDef *pdev , uint8_t cfgidx);\r\n  uint8_t  (*DeInit)           (struct _USBD_HandleTypeDef *pdev , uint8_t cfgidx);\r\n /* Control Endpoints*/\r\n  uint8_t  (*Setup)            (struct _USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef  *req);  \r\n  uint8_t  (*EP0_TxSent)       (struct _USBD_HandleTypeDef *pdev );    \r\n  uint8_t  (*EP0_RxReady)      (struct _USBD_HandleTypeDef *pdev );  \r\n  /* Class Specific Endpoints*/\r\n  uint8_t  (*DataIn)           (struct _USBD_HandleTypeDef *pdev , uint8_t epnum);   \r\n  uint8_t  (*DataOut)          (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); \r\n  uint8_t  (*SOF)              (struct _USBD_HandleTypeDef *pdev); \r\n  uint8_t  (*IsoINIncomplete)  (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); \r\n  uint8_t  (*IsoOUTIncomplete) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum);   \r\n\r\n  uint8_t  *(*GetHSConfigDescriptor)(uint16_t *length); \r\n  uint8_t  *(*GetFSConfigDescriptor)(uint16_t *length);   \r\n  uint8_t  *(*GetOtherSpeedConfigDescriptor)(uint16_t *length);\r\n  uint8_t  *(*GetDeviceQualifierDescriptor)(uint16_t *length);\r\n#if (USBD_SUPPORT_USER_STRING == 1)\r\n  uint8_t  *(*GetUsrStrDescriptor)(struct _USBD_HandleTypeDef *pdev ,uint8_t index,  uint16_t *length);   \r\n#endif  \r\n  \r\n} USBD_ClassTypeDef;\r\n\r\n/* Following USB Device Speed */\r\ntypedef enum \r\n{\r\n  USBD_SPEED_HIGH  = 0,\r\n  USBD_SPEED_FULL  = 1,\r\n  USBD_SPEED_LOW   = 2,  \r\n}USBD_SpeedTypeDef;\r\n\r\n/* Following USB Device status */\r\ntypedef enum {\r\n  USBD_OK   = 0,\r\n  USBD_BUSY,\r\n  USBD_FAIL,\r\n}USBD_StatusTypeDef;\r\n\r\n/* USB Device descriptors structure */\r\ntypedef struct\r\n{\r\n  uint8_t  *(*GetDeviceDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length);  \r\n  uint8_t  *(*GetLangIDStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); \r\n  uint8_t  *(*GetManufacturerStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length);  \r\n  uint8_t  *(*GetProductStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length);  \r\n  uint8_t  *(*GetSerialStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length);  \r\n  uint8_t  *(*GetConfigurationStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length);  \r\n  uint8_t  *(*GetInterfaceStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); \r\n#if (USBD_LPM_ENABLED == 1)\r\n  uint8_t  *(*GetBOSDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); \r\n#endif  \r\n} USBD_DescriptorsTypeDef;\r\n\r\n/* USB Device handle structure */\r\ntypedef struct\r\n{ \r\n  uint32_t                status;\r\n  uint32_t                total_length;    \r\n  uint32_t                rem_length; \r\n  uint32_t                maxpacket;   \r\n} USBD_EndpointTypeDef;\r\n\r\n/* USB Device handle structure */\r\ntypedef struct _USBD_HandleTypeDef\r\n{\r\n  uint8_t                 id;\r\n  uint32_t                dev_config;\r\n  uint32_t                dev_default_config;\r\n  uint32_t                dev_config_status; \r\n  USBD_SpeedTypeDef       dev_speed; \r\n  USBD_EndpointTypeDef    ep_in[15];\r\n  USBD_EndpointTypeDef    ep_out[15];  \r\n  uint32_t                ep0_state;  \r\n  uint32_t                ep0_data_len;     \r\n  uint8_t                 dev_state;\r\n  uint8_t                 dev_old_state;\r\n  uint8_t                 dev_address;\r\n  uint8_t                 dev_connection_status;  \r\n  uint8_t                 dev_test_mode;\r\n  uint32_t                dev_remote_wakeup;\r\n\r\n  USBD_SetupReqTypedef    request;\r\n  USBD_DescriptorsTypeDef *pDesc;\r\n  USBD_ClassTypeDef       *pClass;\r\n  void                    *pClassData;  \r\n  void                    *pUserData;    \r\n  void                    *pData;    \r\n} USBD_HandleTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n\r\n/** @defgroup USBD_DEF_Exported_Macros\r\n  * @{\r\n  */ \r\n#define  SWAPBYTE(addr)        (((uint16_t)(*((uint8_t *)(addr)))) + \\\r\n                               (((uint16_t)(*(((uint8_t *)(addr)) + 1))) << 8))\r\n\r\n#define LOBYTE(x)  ((uint8_t)(x & 0x00FF))\r\n#define HIBYTE(x)  ((uint8_t)((x & 0xFF00) >>8))\r\n#define MIN(a, b)  (((a) < (b)) ? (a) : (b))\r\n#define MAX(a, b)  (((a) > (b)) ? (a) : (b))\r\n\r\n\r\n#if  defined ( __GNUC__ )\r\n  #ifndef __weak\r\n    #define __weak   __attribute__((weak))\r\n  #endif /* __weak */\r\n  #ifndef __packed\r\n    #define __packed __attribute__((__packed__))\r\n  #endif /* __packed */\r\n#endif /* __GNUC__ */\r\n\r\n\r\n/* In HS mode and when the DMA is used, all variables and data structures dealing\r\n   with the DMA during the transaction process should be 4-bytes aligned */    \r\n\r\n#if defined   (__GNUC__)        /* GNU Compiler */\r\n  #define __ALIGN_END    __attribute__ ((aligned (4)))\r\n  #define __ALIGN_BEGIN         \r\n#else                           \r\n  #define __ALIGN_END\r\n  #if defined   (__CC_ARM)      /* ARM Compiler */\r\n    #define __ALIGN_BEGIN    __align(4)  \r\n  #elif defined (__ICCARM__)    /* IAR Compiler */\r\n    #define __ALIGN_BEGIN \r\n  #elif defined  (__TASKING__)  /* TASKING Compiler */\r\n    #define __ALIGN_BEGIN    __align(4) \r\n  #endif /* __CC_ARM */  \r\n#endif /* __GNUC__ */ \r\n  \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_DEF_Exported_Variables\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_DEF_Exported_FunctionsPrototype\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __USBD_DEF_H */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n* @}\r\n*/ \r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/usb_cdc/usbd_desc.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    USB_Device/CDC_Standalone/Src/usbd_desc.c\r\n  * @author  MCD Application Team\r\n  * @version V1.0.3\r\n  * @date    18-November-2015\r\n  * @brief   This file provides the USBD descriptors and string formating method.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software\r\n  * distributed under the License is distributed on an \"AS IS\" BASIS,\r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_core.h\"\r\n#include \"usbd_desc.h\"\r\n#include \"usbd_conf.h\"\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n#define USBD_VID                      0x0483\r\n#define USBD_PID                      0x5740\r\n#define USBD_LANGID_STRING            0x409\r\n#define USBD_MANUFACTURER_STRING      \"ROBOTIS\"\r\n#define USBD_PRODUCT_HS_STRING        \"OpenCR Virtual ComPort in HS Mode\"\r\n#define USBD_PRODUCT_FS_STRING        \"OpenCR Virtual ComPort in FS Mode\"\r\n#define USBD_CONFIGURATION_HS_STRING  \"VCP Config\"\r\n#define USBD_INTERFACE_HS_STRING      \"VCP Interface\"\r\n#define USBD_CONFIGURATION_FS_STRING  \"VCP Config\"\r\n#define USBD_INTERFACE_FS_STRING      \"VCP Interface\"\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\nuint8_t *USBD_VCP_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);\r\nuint8_t *USBD_VCP_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);\r\nuint8_t *USBD_VCP_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);\r\nuint8_t *USBD_VCP_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);\r\nuint8_t *USBD_VCP_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);\r\nuint8_t *USBD_VCP_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);\r\nuint8_t *USBD_VCP_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);\r\n#ifdef USB_SUPPORT_USER_STRING_DESC\r\nuint8_t *USBD_VCP_USRStringDesc (USBD_SpeedTypeDef speed, uint8_t idx, uint16_t *length);\r\n#endif /* USB_SUPPORT_USER_STRING_DESC */\r\n\r\n/* Private variables ---------------------------------------------------------*/\r\nUSBD_DescriptorsTypeDef VCP_Desc = {\r\n  USBD_VCP_DeviceDescriptor,\r\n  USBD_VCP_LangIDStrDescriptor,\r\n  USBD_VCP_ManufacturerStrDescriptor,\r\n  USBD_VCP_ProductStrDescriptor,\r\n  USBD_VCP_SerialStrDescriptor,\r\n  USBD_VCP_ConfigStrDescriptor,\r\n  USBD_VCP_InterfaceStrDescriptor,\r\n};\r\n\r\n/* USB Standard Device Descriptor */\r\n#if defined ( __ICCARM__ ) /*!< IAR Compiler */\r\n  #pragma data_alignment=4\r\n#endif\r\n__ALIGN_BEGIN uint8_t USBD_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END = {\r\n  0x12,                       /* bLength */\r\n  USB_DESC_TYPE_DEVICE,       /* bDescriptorType */\r\n  0x00,                       /* bcdUSB */\r\n  0x02,\r\n  0x02,                       /* bDeviceClass */\r\n  0x00,                       /* bDeviceSubClass */\r\n  0x00,                       /* bDeviceProtocol */\r\n  USB_MAX_EP0_SIZE,           /* bMaxPacketSize */\r\n  LOBYTE(USBD_VID),           /* idVendor */\r\n  HIBYTE(USBD_VID),           /* idVendor */\r\n  LOBYTE(USBD_PID),           /* idVendor */\r\n  HIBYTE(USBD_PID),           /* idVendor */\r\n  0x00,                       /* bcdDevice rel. 2.00 */\r\n  0x02,\r\n  USBD_IDX_MFC_STR,           /* Index of manufacturer string */\r\n  USBD_IDX_PRODUCT_STR,       /* Index of product string */\r\n  USBD_IDX_SERIAL_STR,        /* Index of serial number string */\r\n  USBD_MAX_NUM_CONFIGURATION  /* bNumConfigurations */\r\n}; /* USB_DeviceDescriptor */\r\n\r\n/* USB Standard Device Descriptor */\r\n#if defined ( __ICCARM__ ) /*!< IAR Compiler */\r\n  #pragma data_alignment=4\r\n#endif\r\n__ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_LEN_LANGID_STR_DESC] __ALIGN_END = {\r\n  USB_LEN_LANGID_STR_DESC,\r\n  USB_DESC_TYPE_STRING,\r\n  LOBYTE(USBD_LANGID_STRING),\r\n  HIBYTE(USBD_LANGID_STRING),\r\n};\r\n\r\nuint8_t USBD_StringSerial[USB_SIZ_STRING_SERIAL] =\r\n{\r\n  USB_SIZ_STRING_SERIAL,\r\n  USB_DESC_TYPE_STRING,\r\n};\r\n\r\n#if defined ( __ICCARM__ ) /*!< IAR Compiler */\r\n  #pragma data_alignment=4\r\n#endif\r\n__ALIGN_BEGIN uint8_t USBD_StrDesc[USBD_MAX_STR_DESC_SIZ] __ALIGN_END;\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\nstatic void IntToUnicode (uint32_t value , uint8_t *pbuf , uint8_t len);\r\nstatic void Get_SerialNum(void);\r\n\r\n/**\r\n  * @brief  Returns the device descriptor.\r\n  * @param  speed: Current device speed\r\n  * @param  length: Pointer to data length variable\r\n  * @retval Pointer to descriptor buffer\r\n  */\r\nuint8_t *USBD_VCP_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)\r\n{\r\n  UNUSED(speed);\r\n\r\n  *length = sizeof(USBD_DeviceDesc);\r\n  return (uint8_t*)USBD_DeviceDesc;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the LangID string descriptor.\r\n  * @param  speed: Current device speed\r\n  * @param  length: Pointer to data length variable\r\n  * @retval Pointer to descriptor buffer\r\n  */\r\nuint8_t *USBD_VCP_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)\r\n{\r\n  UNUSED(speed);\r\n\r\n  *length = sizeof(USBD_LangIDDesc);\r\n  return (uint8_t*)USBD_LangIDDesc;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the product string descriptor.\r\n  * @param  speed: Current device speed\r\n  * @param  length: Pointer to data length variable\r\n  * @retval Pointer to descriptor buffer\r\n  */\r\nuint8_t *USBD_VCP_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)\r\n{\r\n  if(speed == USBD_SPEED_HIGH)\r\n  {\r\n    USBD_GetString((uint8_t *)USBD_PRODUCT_HS_STRING, USBD_StrDesc, length);\r\n  }\r\n  else\r\n  {\r\n    USBD_GetString((uint8_t *)USBD_PRODUCT_FS_STRING, USBD_StrDesc, length);\r\n  }\r\n  return USBD_StrDesc;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the manufacturer string descriptor.\r\n  * @param  speed: Current device speed\r\n  * @param  length: Pointer to data length variable\r\n  * @retval Pointer to descriptor buffer\r\n  */\r\nuint8_t *USBD_VCP_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)\r\n{\r\n  UNUSED(speed);\r\n\r\n  USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length);\r\n  return USBD_StrDesc;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the serial number string descriptor.\r\n  * @param  speed: Current device speed\r\n  * @param  length: Pointer to data length variable\r\n  * @retval Pointer to descriptor buffer\r\n  */\r\nuint8_t *USBD_VCP_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)\r\n{\r\n  UNUSED(speed);\r\n\r\n  *length = USB_SIZ_STRING_SERIAL;\r\n\r\n  /* Update the serial number string descriptor with the data from the unique ID*/\r\n  Get_SerialNum();\r\n\r\n  return (uint8_t*)USBD_StringSerial;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the configuration string descriptor.\r\n  * @param  speed: Current device speed\r\n  * @param  length: Pointer to data length variable\r\n  * @retval Pointer to descriptor buffer\r\n  */\r\nuint8_t *USBD_VCP_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)\r\n{\r\n  if(speed == USBD_SPEED_HIGH)\r\n  {\r\n    USBD_GetString((uint8_t *)USBD_CONFIGURATION_HS_STRING, USBD_StrDesc, length);\r\n  }\r\n  else\r\n  {\r\n    USBD_GetString((uint8_t *)USBD_CONFIGURATION_FS_STRING, USBD_StrDesc, length);\r\n  }\r\n  return USBD_StrDesc;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the interface string descriptor.\r\n  * @param  speed: Current device speed\r\n  * @param  length: Pointer to data length variable\r\n  * @retval Pointer to descriptor buffer\r\n  */\r\nuint8_t *USBD_VCP_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)\r\n{\r\n  if(speed == USBD_SPEED_HIGH)\r\n  {\r\n    USBD_GetString((uint8_t *)USBD_INTERFACE_HS_STRING, USBD_StrDesc, length);\r\n  }\r\n  else\r\n  {\r\n    USBD_GetString((uint8_t *)USBD_INTERFACE_FS_STRING, USBD_StrDesc, length);\r\n  }\r\n  return USBD_StrDesc;\r\n}\r\n\r\n/**\r\n  * @brief  Create the serial number string descriptor\r\n  * @param  None\r\n  * @retval None\r\n  */\r\nstatic void Get_SerialNum(void)\r\n{\r\n  uint32_t deviceserial0, deviceserial1, deviceserial2;\r\n\r\n  deviceserial0 = *(uint32_t*)DEVICE_ID1;\r\n  deviceserial1 = *(uint32_t*)DEVICE_ID2;\r\n  deviceserial2 = *(uint32_t*)DEVICE_ID3;\r\n\r\n  deviceserial0 += deviceserial2;\r\n\r\n  if (deviceserial0 != 0)\r\n  {\r\n    IntToUnicode (deviceserial0, &USBD_StringSerial[2] ,8);\r\n    IntToUnicode (deviceserial1, &USBD_StringSerial[18] ,4);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Convert Hex 32Bits value into char\r\n  * @param  value: value to convert\r\n  * @param  pbuf: pointer to the buffer\r\n  * @param  len: buffer length\r\n  * @retval None\r\n  */\r\nstatic void IntToUnicode (uint32_t value , uint8_t *pbuf , uint8_t len)\r\n{\r\n  uint8_t idx = 0;\r\n\r\n  for( idx = 0; idx < len; idx ++)\r\n  {\r\n    if( ((value >> 28)) < 0xA )\r\n    {\r\n      pbuf[ 2* idx] = (value >> 28) + '0';\r\n    }\r\n    else\r\n    {\r\n      pbuf[2* idx] = (value >> 28) + 'A' - 10;\r\n    }\r\n\r\n    value = value << 4;\r\n\r\n    pbuf[ 2* idx + 1] = 0;\r\n  }\r\n}\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/usb_cdc/usbd_desc.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    USB_Device/CDC_Standalone/Inc/usbd_desc.h\r\n  * @author  MCD Application Team\r\n  * @version V1.0.3\r\n  * @date    18-November-2015\r\n  * @brief   Header for usbd_desc.c module\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __USBD_DESC_H\r\n#define __USBD_DESC_H\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_def.h\"\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n#define         DEVICE_ID1          (0x1FFF7A10)\r\n#define         DEVICE_ID2          (0x1FFF7A14)\r\n#define         DEVICE_ID3          (0x1FFF7A18)\r\n\r\n#define  USB_SIZ_STRING_SERIAL       0x1A\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions ------------------------------------------------------- */\r\nextern USBD_DescriptorsTypeDef VCP_Desc;\r\n\r\n#endif /* __USBD_DESC_H */\r\n \r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/usb_cdc/usbd_ioreq.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_ioreq.c\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   This file provides the IO requests APIs for control endpoints.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_ioreq.h\"\r\n\r\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n\r\n\r\n/** @defgroup USBD_IOREQ \r\n  * @brief control I/O requests module\r\n  * @{\r\n  */ \r\n\r\n/** @defgroup USBD_IOREQ_Private_TypesDefinitions\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_IOREQ_Private_Defines\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_IOREQ_Private_Macros\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_IOREQ_Private_Variables\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_IOREQ_Private_FunctionPrototypes\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_IOREQ_Private_Functions\r\n  * @{\r\n  */ \r\n\r\n/**\r\n* @brief  USBD_CtlSendData\r\n*         send data on the ctl pipe\r\n* @param  pdev: device instance\r\n* @param  buff: pointer to data buffer\r\n* @param  len: length of data to be sent\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef  USBD_CtlSendData (USBD_HandleTypeDef  *pdev, \r\n                               uint8_t *pbuf,\r\n                               uint16_t len)\r\n{\r\n  /* Set EP0 State */\r\n  pdev->ep0_state          = USBD_EP0_DATA_IN;                                      \r\n  pdev->ep_in[0].total_length = len;\r\n  pdev->ep_in[0].rem_length   = len;\r\n /* Start the transfer */\r\n  USBD_LL_Transmit (pdev, 0x00, pbuf, len);  \r\n  \r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n* @brief  USBD_CtlContinueSendData\r\n*         continue sending data on the ctl pipe\r\n* @param  pdev: device instance\r\n* @param  buff: pointer to data buffer\r\n* @param  len: length of data to be sent\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef  USBD_CtlContinueSendData (USBD_HandleTypeDef  *pdev, \r\n                                       uint8_t *pbuf,\r\n                                       uint16_t len)\r\n{\r\n /* Start the next transfer */\r\n  USBD_LL_Transmit (pdev, 0x00, pbuf, len);   \r\n  \r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n* @brief  USBD_CtlPrepareRx\r\n*         receive data on the ctl pipe\r\n* @param  pdev: device instance\r\n* @param  buff: pointer to data buffer\r\n* @param  len: length of data to be received\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef  USBD_CtlPrepareRx (USBD_HandleTypeDef  *pdev,\r\n                                  uint8_t *pbuf,                                  \r\n                                  uint16_t len)\r\n{\r\n  /* Set EP0 State */\r\n  pdev->ep0_state = USBD_EP0_DATA_OUT; \r\n  pdev->ep_out[0].total_length = len;\r\n  pdev->ep_out[0].rem_length   = len;\r\n  /* Start the transfer */\r\n  USBD_LL_PrepareReceive (pdev,\r\n                          0,\r\n                          pbuf,\r\n                         len);\r\n  \r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n* @brief  USBD_CtlContinueRx\r\n*         continue receive data on the ctl pipe\r\n* @param  pdev: device instance\r\n* @param  buff: pointer to data buffer\r\n* @param  len: length of data to be received\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef  USBD_CtlContinueRx (USBD_HandleTypeDef  *pdev, \r\n                                          uint8_t *pbuf,                                          \r\n                                          uint16_t len)\r\n{\r\n\r\n  USBD_LL_PrepareReceive (pdev,\r\n                          0,                     \r\n                          pbuf,                         \r\n                          len);\r\n  return USBD_OK;\r\n}\r\n/**\r\n* @brief  USBD_CtlSendStatus\r\n*         send zero lzngth packet on the ctl pipe\r\n* @param  pdev: device instance\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef  USBD_CtlSendStatus (USBD_HandleTypeDef  *pdev)\r\n{\r\n\r\n  /* Set EP0 State */\r\n  pdev->ep0_state = USBD_EP0_STATUS_IN;\r\n  \r\n /* Start the transfer */\r\n  USBD_LL_Transmit (pdev, 0x00, NULL, 0);   \r\n  \r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n* @brief  USBD_CtlReceiveStatus\r\n*         receive zero lzngth packet on the ctl pipe\r\n* @param  pdev: device instance\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef  USBD_CtlReceiveStatus (USBD_HandleTypeDef  *pdev)\r\n{\r\n  /* Set EP0 State */\r\n  pdev->ep0_state = USBD_EP0_STATUS_OUT; \r\n  \r\n /* Start the transfer */  \r\n  USBD_LL_PrepareReceive ( pdev,\r\n                    0,\r\n                    NULL,\r\n                    0);  \r\n\r\n  return USBD_OK;\r\n}\r\n\r\n\r\n/**\r\n* @brief  USBD_GetRxCount\r\n*         returns the received data length\r\n* @param  pdev: device instance\r\n* @param  ep_addr: endpoint address\r\n* @retval Rx Data blength\r\n*/\r\nuint16_t  USBD_GetRxCount (USBD_HandleTypeDef  *pdev , uint8_t ep_addr)\r\n{\r\n  return USBD_LL_GetRxDataSize(pdev, ep_addr);\r\n}\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/hw/usb_cdc/usbd_ioreq.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_ioreq.h\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   Header file for the usbd_ioreq.c file\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __USBD_IOREQ_H\r\n#define __USBD_IOREQ_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include  \"usbd_def.h\"\r\n#include  \"usbd_core.h\"\r\n\r\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup USBD_IOREQ\r\n  * @brief header file for the usbd_ioreq.c file\r\n  * @{\r\n  */ \r\n\r\n/** @defgroup USBD_IOREQ_Exported_Defines\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_IOREQ_Exported_Types\r\n  * @{\r\n  */\r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n\r\n/** @defgroup USBD_IOREQ_Exported_Macros\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_IOREQ_Exported_Variables\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_IOREQ_Exported_FunctionsPrototype\r\n  * @{\r\n  */ \r\n\r\nUSBD_StatusTypeDef  USBD_CtlSendData (USBD_HandleTypeDef  *pdev, \r\n                               uint8_t *buf,\r\n                               uint16_t len);\r\n\r\nUSBD_StatusTypeDef  USBD_CtlContinueSendData (USBD_HandleTypeDef  *pdev, \r\n                               uint8_t *pbuf,\r\n                               uint16_t len);\r\n\r\nUSBD_StatusTypeDef USBD_CtlPrepareRx (USBD_HandleTypeDef  *pdev, \r\n                               uint8_t *pbuf,                                 \r\n                               uint16_t len);\r\n\r\nUSBD_StatusTypeDef  USBD_CtlContinueRx (USBD_HandleTypeDef  *pdev, \r\n                              uint8_t *pbuf,                                          \r\n                              uint16_t len);\r\n\r\nUSBD_StatusTypeDef  USBD_CtlSendStatus (USBD_HandleTypeDef  *pdev);\r\n\r\nUSBD_StatusTypeDef  USBD_CtlReceiveStatus (USBD_HandleTypeDef  *pdev);\r\n\r\nuint16_t  USBD_GetRxCount (USBD_HandleTypeDef  *pdev , \r\n                           uint8_t epnum);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __USBD_IOREQ_H */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n* @}\r\n*/ \r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32_hal_legacy.h\r\n  * @author  MCD Application Team\r\n  * @brief   This file contains aliases definition for the STM32Cube HAL constants\r\n  *          macros and functions maintained for legacy purpose.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32_HAL_LEGACY\r\n#define __STM32_HAL_LEGACY\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define AES_FLAG_RDERR                  CRYP_FLAG_RDERR\r\n#define AES_FLAG_WRERR                  CRYP_FLAG_WRERR\r\n#define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF\r\n#define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR\r\n#define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define ADC_RESOLUTION12b               ADC_RESOLUTION_12B\r\n#define ADC_RESOLUTION10b               ADC_RESOLUTION_10B\r\n#define ADC_RESOLUTION8b                ADC_RESOLUTION_8B\r\n#define ADC_RESOLUTION6b                ADC_RESOLUTION_6B\r\n#define OVR_DATA_OVERWRITTEN            ADC_OVR_DATA_OVERWRITTEN\r\n#define OVR_DATA_PRESERVED              ADC_OVR_DATA_PRESERVED\r\n#define EOC_SINGLE_CONV                 ADC_EOC_SINGLE_CONV\r\n#define EOC_SEQ_CONV                    ADC_EOC_SEQ_CONV\r\n#define EOC_SINGLE_SEQ_CONV             ADC_EOC_SINGLE_SEQ_CONV\r\n#define REGULAR_GROUP                   ADC_REGULAR_GROUP\r\n#define INJECTED_GROUP                  ADC_INJECTED_GROUP\r\n#define REGULAR_INJECTED_GROUP          ADC_REGULAR_INJECTED_GROUP\r\n#define AWD_EVENT                       ADC_AWD_EVENT\r\n#define AWD1_EVENT                      ADC_AWD1_EVENT\r\n#define AWD2_EVENT                      ADC_AWD2_EVENT\r\n#define AWD3_EVENT                      ADC_AWD3_EVENT\r\n#define OVR_EVENT                       ADC_OVR_EVENT\r\n#define JQOVF_EVENT                     ADC_JQOVF_EVENT\r\n#define ALL_CHANNELS                    ADC_ALL_CHANNELS\r\n#define REGULAR_CHANNELS                ADC_REGULAR_CHANNELS\r\n#define INJECTED_CHANNELS               ADC_INJECTED_CHANNELS\r\n#define SYSCFG_FLAG_SENSOR_ADC          ADC_FLAG_SENSOR\r\n#define SYSCFG_FLAG_VREF_ADC            ADC_FLAG_VREFINT\r\n#define ADC_CLOCKPRESCALER_PCLK_DIV1    ADC_CLOCK_SYNC_PCLK_DIV1\r\n#define ADC_CLOCKPRESCALER_PCLK_DIV2    ADC_CLOCK_SYNC_PCLK_DIV2\r\n#define ADC_CLOCKPRESCALER_PCLK_DIV4    ADC_CLOCK_SYNC_PCLK_DIV4\r\n#define ADC_CLOCKPRESCALER_PCLK_DIV6    ADC_CLOCK_SYNC_PCLK_DIV6\r\n#define ADC_CLOCKPRESCALER_PCLK_DIV8    ADC_CLOCK_SYNC_PCLK_DIV8\r\n#define ADC_EXTERNALTRIG0_T6_TRGO       ADC_EXTERNALTRIGCONV_T6_TRGO\r\n#define ADC_EXTERNALTRIG1_T21_CC2       ADC_EXTERNALTRIGCONV_T21_CC2\r\n#define ADC_EXTERNALTRIG2_T2_TRGO       ADC_EXTERNALTRIGCONV_T2_TRGO\r\n#define ADC_EXTERNALTRIG3_T2_CC4        ADC_EXTERNALTRIGCONV_T2_CC4\r\n#define ADC_EXTERNALTRIG4_T22_TRGO      ADC_EXTERNALTRIGCONV_T22_TRGO\r\n#define ADC_EXTERNALTRIG7_EXT_IT11      ADC_EXTERNALTRIGCONV_EXT_IT11\r\n#define ADC_CLOCK_ASYNC                 ADC_CLOCK_ASYNC_DIV1\r\n#define ADC_EXTERNALTRIG_EDGE_NONE      ADC_EXTERNALTRIGCONVEDGE_NONE\r\n#define ADC_EXTERNALTRIG_EDGE_RISING    ADC_EXTERNALTRIGCONVEDGE_RISING\r\n#define ADC_EXTERNALTRIG_EDGE_FALLING   ADC_EXTERNALTRIGCONVEDGE_FALLING\r\n#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING\r\n#define ADC_SAMPLETIME_2CYCLE_5         ADC_SAMPLETIME_2CYCLES_5\r\n\r\n#define HAL_ADC_STATE_BUSY_REG          HAL_ADC_STATE_REG_BUSY\r\n#define HAL_ADC_STATE_BUSY_INJ          HAL_ADC_STATE_INJ_BUSY\r\n#define HAL_ADC_STATE_EOC_REG           HAL_ADC_STATE_REG_EOC\r\n#define HAL_ADC_STATE_EOC_INJ           HAL_ADC_STATE_INJ_EOC\r\n#define HAL_ADC_STATE_ERROR             HAL_ADC_STATE_ERROR_INTERNAL\r\n#define HAL_ADC_STATE_BUSY              HAL_ADC_STATE_BUSY_INTERNAL\r\n#define HAL_ADC_STATE_AWD               HAL_ADC_STATE_AWD1\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define COMP_WINDOWMODE_DISABLED       COMP_WINDOWMODE_DISABLE\r\n#define COMP_WINDOWMODE_ENABLED        COMP_WINDOWMODE_ENABLE\r\n#define COMP_EXTI_LINE_COMP1_EVENT     COMP_EXTI_LINE_COMP1\r\n#define COMP_EXTI_LINE_COMP2_EVENT     COMP_EXTI_LINE_COMP2\r\n#define COMP_EXTI_LINE_COMP3_EVENT     COMP_EXTI_LINE_COMP3\r\n#define COMP_EXTI_LINE_COMP4_EVENT     COMP_EXTI_LINE_COMP4\r\n#define COMP_EXTI_LINE_COMP5_EVENT     COMP_EXTI_LINE_COMP5\r\n#define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6\r\n#define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7\r\n#if defined(STM32L0)\r\n#define COMP_LPTIMCONNECTION_ENABLED   ((uint32_t)0x00000003U)    /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */\r\n#endif\r\n#define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR\r\n#if defined(STM32F373xC) || defined(STM32F378xx)\r\n#define COMP_OUTPUT_TIM3IC1            COMP_OUTPUT_COMP1_TIM3IC1\r\n#define COMP_OUTPUT_TIM3OCREFCLR       COMP_OUTPUT_COMP1_TIM3OCREFCLR\r\n#endif /* STM32F373xC || STM32F378xx */\r\n\r\n#if defined(STM32L0) || defined(STM32L4)\r\n#define COMP_WINDOWMODE_ENABLE         COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON\r\n\r\n#define COMP_NONINVERTINGINPUT_IO1      COMP_INPUT_PLUS_IO1\r\n#define COMP_NONINVERTINGINPUT_IO2      COMP_INPUT_PLUS_IO2\r\n#define COMP_NONINVERTINGINPUT_IO3      COMP_INPUT_PLUS_IO3\r\n#define COMP_NONINVERTINGINPUT_IO4      COMP_INPUT_PLUS_IO4\r\n#define COMP_NONINVERTINGINPUT_IO5      COMP_INPUT_PLUS_IO5\r\n#define COMP_NONINVERTINGINPUT_IO6      COMP_INPUT_PLUS_IO6\r\n\r\n#define COMP_INVERTINGINPUT_1_4VREFINT  COMP_INPUT_MINUS_1_4VREFINT\r\n#define COMP_INVERTINGINPUT_1_2VREFINT  COMP_INPUT_MINUS_1_2VREFINT\r\n#define COMP_INVERTINGINPUT_3_4VREFINT  COMP_INPUT_MINUS_3_4VREFINT\r\n#define COMP_INVERTINGINPUT_VREFINT     COMP_INPUT_MINUS_VREFINT\r\n#define COMP_INVERTINGINPUT_DAC1_CH1    COMP_INPUT_MINUS_DAC1_CH1\r\n#define COMP_INVERTINGINPUT_DAC1_CH2    COMP_INPUT_MINUS_DAC1_CH2\r\n#define COMP_INVERTINGINPUT_DAC1        COMP_INPUT_MINUS_DAC1_CH1\r\n#define COMP_INVERTINGINPUT_DAC2        COMP_INPUT_MINUS_DAC1_CH2\r\n#define COMP_INVERTINGINPUT_IO1         COMP_INPUT_MINUS_IO1\r\n#if defined(STM32L0)\r\n/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2),     */\r\n/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding   */\r\n/* to the second dedicated IO (only for COMP2).                               */\r\n#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_DAC1_CH2\r\n#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO2\r\n#else\r\n#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_IO2\r\n#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO3\r\n#endif\r\n#define COMP_INVERTINGINPUT_IO4         COMP_INPUT_MINUS_IO4\r\n#define COMP_INVERTINGINPUT_IO5         COMP_INPUT_MINUS_IO5\r\n\r\n#define COMP_OUTPUTLEVEL_LOW            COMP_OUTPUT_LEVEL_LOW\r\n#define COMP_OUTPUTLEVEL_HIGH           COMP_OUTPUT_LEVEL_HIGH\r\n\r\n/* Note: Literal \"COMP_FLAG_LOCK\" kept for legacy purpose.                    */\r\n/*       To check COMP lock state, use macro \"__HAL_COMP_IS_LOCKED()\".        */\r\n#if defined(COMP_CSR_LOCK)\r\n#define COMP_FLAG_LOCK                 COMP_CSR_LOCK\r\n#elif defined(COMP_CSR_COMP1LOCK)\r\n#define COMP_FLAG_LOCK                 COMP_CSR_COMP1LOCK\r\n#elif defined(COMP_CSR_COMPxLOCK)\r\n#define COMP_FLAG_LOCK                 COMP_CSR_COMPxLOCK\r\n#endif\r\n\r\n#if defined(STM32L4)\r\n#define COMP_BLANKINGSRCE_TIM1OC5        COMP_BLANKINGSRC_TIM1_OC5_COMP1\r\n#define COMP_BLANKINGSRCE_TIM2OC3        COMP_BLANKINGSRC_TIM2_OC3_COMP1\r\n#define COMP_BLANKINGSRCE_TIM3OC3        COMP_BLANKINGSRC_TIM3_OC3_COMP1\r\n#define COMP_BLANKINGSRCE_TIM3OC4        COMP_BLANKINGSRC_TIM3_OC4_COMP2\r\n#define COMP_BLANKINGSRCE_TIM8OC5        COMP_BLANKINGSRC_TIM8_OC5_COMP2\r\n#define COMP_BLANKINGSRCE_TIM15OC1       COMP_BLANKINGSRC_TIM15_OC1_COMP2\r\n#define COMP_BLANKINGSRCE_NONE           COMP_BLANKINGSRC_NONE\r\n#endif\r\n\r\n#if defined(STM32L0)\r\n#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_MEDIUMSPEED\r\n#define COMP_MODE_LOWSPEED               COMP_POWERMODE_ULTRALOWPOWER\r\n#else\r\n#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_HIGHSPEED\r\n#define COMP_MODE_MEDIUMSPEED            COMP_POWERMODE_MEDIUMSPEED\r\n#define COMP_MODE_LOWPOWER               COMP_POWERMODE_LOWPOWER\r\n#define COMP_MODE_ULTRALOWPOWER          COMP_POWERMODE_ULTRALOWPOWER\r\n#endif\r\n\r\n#endif\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define CRC_OUTPUTDATA_INVERSION_DISABLED    CRC_OUTPUTDATA_INVERSION_DISABLE\r\n#define CRC_OUTPUTDATA_INVERSION_ENABLED     CRC_OUTPUTDATA_INVERSION_ENABLE\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define DAC1_CHANNEL_1                                  DAC_CHANNEL_1\r\n#define DAC1_CHANNEL_2                                  DAC_CHANNEL_2\r\n#define DAC2_CHANNEL_1                                  DAC_CHANNEL_1\r\n#define DAC_WAVE_NONE                                   0x00000000U\r\n#define DAC_WAVE_NOISE                                  DAC_CR_WAVE1_0\r\n#define DAC_WAVE_TRIANGLE                               DAC_CR_WAVE1_1\r\n#define DAC_WAVEGENERATION_NONE                         DAC_WAVE_NONE\r\n#define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE\r\n#define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define HAL_REMAPDMA_ADC_DMA_CH2                DMA_REMAP_ADC_DMA_CH2\r\n#define HAL_REMAPDMA_USART1_TX_DMA_CH4          DMA_REMAP_USART1_TX_DMA_CH4\r\n#define HAL_REMAPDMA_USART1_RX_DMA_CH5          DMA_REMAP_USART1_RX_DMA_CH5\r\n#define HAL_REMAPDMA_TIM16_DMA_CH4              DMA_REMAP_TIM16_DMA_CH4\r\n#define HAL_REMAPDMA_TIM17_DMA_CH2              DMA_REMAP_TIM17_DMA_CH2\r\n#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32\r\n#define HAL_REMAPDMA_TIM16_DMA_CH6              DMA_REMAP_TIM16_DMA_CH6\r\n#define HAL_REMAPDMA_TIM17_DMA_CH7              DMA_REMAP_TIM17_DMA_CH7\r\n#define HAL_REMAPDMA_SPI2_DMA_CH67              DMA_REMAP_SPI2_DMA_CH67\r\n#define HAL_REMAPDMA_USART2_DMA_CH67            DMA_REMAP_USART2_DMA_CH67\r\n#define HAL_REMAPDMA_I2C1_DMA_CH76              DMA_REMAP_I2C1_DMA_CH76\r\n#define HAL_REMAPDMA_TIM1_DMA_CH6               DMA_REMAP_TIM1_DMA_CH6\r\n#define HAL_REMAPDMA_TIM2_DMA_CH7               DMA_REMAP_TIM2_DMA_CH7\r\n#define HAL_REMAPDMA_TIM3_DMA_CH6               DMA_REMAP_TIM3_DMA_CH6\r\n\r\n#define IS_HAL_REMAPDMA                          IS_DMA_REMAP\r\n#define __HAL_REMAPDMA_CHANNEL_ENABLE            __HAL_DMA_REMAP_CHANNEL_ENABLE\r\n#define __HAL_REMAPDMA_CHANNEL_DISABLE           __HAL_DMA_REMAP_CHANNEL_DISABLE\r\n\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define TYPEPROGRAM_BYTE              FLASH_TYPEPROGRAM_BYTE\r\n#define TYPEPROGRAM_HALFWORD          FLASH_TYPEPROGRAM_HALFWORD\r\n#define TYPEPROGRAM_WORD              FLASH_TYPEPROGRAM_WORD\r\n#define TYPEPROGRAM_DOUBLEWORD        FLASH_TYPEPROGRAM_DOUBLEWORD\r\n#define TYPEERASE_SECTORS             FLASH_TYPEERASE_SECTORS\r\n#define TYPEERASE_PAGES               FLASH_TYPEERASE_PAGES\r\n#define TYPEERASE_PAGEERASE           FLASH_TYPEERASE_PAGES\r\n#define TYPEERASE_MASSERASE           FLASH_TYPEERASE_MASSERASE\r\n#define WRPSTATE_DISABLE              OB_WRPSTATE_DISABLE\r\n#define WRPSTATE_ENABLE               OB_WRPSTATE_ENABLE\r\n#define HAL_FLASH_TIMEOUT_VALUE       FLASH_TIMEOUT_VALUE\r\n#define OBEX_PCROP                    OPTIONBYTE_PCROP\r\n#define OBEX_BOOTCONFIG               OPTIONBYTE_BOOTCONFIG\r\n#define PCROPSTATE_DISABLE            OB_PCROP_STATE_DISABLE\r\n#define PCROPSTATE_ENABLE             OB_PCROP_STATE_ENABLE\r\n#define TYPEERASEDATA_BYTE            FLASH_TYPEERASEDATA_BYTE\r\n#define TYPEERASEDATA_HALFWORD        FLASH_TYPEERASEDATA_HALFWORD\r\n#define TYPEERASEDATA_WORD            FLASH_TYPEERASEDATA_WORD\r\n#define TYPEPROGRAMDATA_BYTE          FLASH_TYPEPROGRAMDATA_BYTE\r\n#define TYPEPROGRAMDATA_HALFWORD      FLASH_TYPEPROGRAMDATA_HALFWORD\r\n#define TYPEPROGRAMDATA_WORD          FLASH_TYPEPROGRAMDATA_WORD\r\n#define TYPEPROGRAMDATA_FASTBYTE      FLASH_TYPEPROGRAMDATA_FASTBYTE\r\n#define TYPEPROGRAMDATA_FASTHALFWORD  FLASH_TYPEPROGRAMDATA_FASTHALFWORD\r\n#define TYPEPROGRAMDATA_FASTWORD      FLASH_TYPEPROGRAMDATA_FASTWORD\r\n#define PAGESIZE                      FLASH_PAGE_SIZE\r\n#define TYPEPROGRAM_FASTBYTE          FLASH_TYPEPROGRAM_BYTE\r\n#define TYPEPROGRAM_FASTHALFWORD      FLASH_TYPEPROGRAM_HALFWORD\r\n#define TYPEPROGRAM_FASTWORD          FLASH_TYPEPROGRAM_WORD\r\n#define VOLTAGE_RANGE_1               FLASH_VOLTAGE_RANGE_1\r\n#define VOLTAGE_RANGE_2               FLASH_VOLTAGE_RANGE_2\r\n#define VOLTAGE_RANGE_3               FLASH_VOLTAGE_RANGE_3\r\n#define VOLTAGE_RANGE_4               FLASH_VOLTAGE_RANGE_4\r\n#define TYPEPROGRAM_FAST              FLASH_TYPEPROGRAM_FAST\r\n#define TYPEPROGRAM_FAST_AND_LAST     FLASH_TYPEPROGRAM_FAST_AND_LAST\r\n#define WRPAREA_BANK1_AREAA           OB_WRPAREA_BANK1_AREAA\r\n#define WRPAREA_BANK1_AREAB           OB_WRPAREA_BANK1_AREAB\r\n#define WRPAREA_BANK2_AREAA           OB_WRPAREA_BANK2_AREAA\r\n#define WRPAREA_BANK2_AREAB           OB_WRPAREA_BANK2_AREAB\r\n#define IWDG_STDBY_FREEZE             OB_IWDG_STDBY_FREEZE\r\n#define IWDG_STDBY_ACTIVE             OB_IWDG_STDBY_RUN\r\n#define IWDG_STOP_FREEZE              OB_IWDG_STOP_FREEZE\r\n#define IWDG_STOP_ACTIVE              OB_IWDG_STOP_RUN\r\n#define FLASH_ERROR_NONE              HAL_FLASH_ERROR_NONE\r\n#define FLASH_ERROR_RD                HAL_FLASH_ERROR_RD\r\n#define FLASH_ERROR_PG                HAL_FLASH_ERROR_PROG\r\n#define FLASH_ERROR_PGP               HAL_FLASH_ERROR_PGS\r\n#define FLASH_ERROR_WRP               HAL_FLASH_ERROR_WRP\r\n#define FLASH_ERROR_OPTV              HAL_FLASH_ERROR_OPTV\r\n#define FLASH_ERROR_OPTVUSR           HAL_FLASH_ERROR_OPTVUSR\r\n#define FLASH_ERROR_PROG              HAL_FLASH_ERROR_PROG\r\n#define FLASH_ERROR_OP                HAL_FLASH_ERROR_OPERATION\r\n#define FLASH_ERROR_PGA               HAL_FLASH_ERROR_PGA\r\n#define FLASH_ERROR_SIZE              HAL_FLASH_ERROR_SIZE\r\n#define FLASH_ERROR_SIZ               HAL_FLASH_ERROR_SIZE\r\n#define FLASH_ERROR_PGS               HAL_FLASH_ERROR_PGS\r\n#define FLASH_ERROR_MIS               HAL_FLASH_ERROR_MIS\r\n#define FLASH_ERROR_FAST              HAL_FLASH_ERROR_FAST\r\n#define FLASH_ERROR_FWWERR            HAL_FLASH_ERROR_FWWERR\r\n#define FLASH_ERROR_NOTZERO           HAL_FLASH_ERROR_NOTZERO\r\n#define FLASH_ERROR_OPERATION         HAL_FLASH_ERROR_OPERATION\r\n#define FLASH_ERROR_ERS               HAL_FLASH_ERROR_ERS\r\n#define OB_WDG_SW                     OB_IWDG_SW\r\n#define OB_WDG_HW                     OB_IWDG_HW\r\n#define OB_SDADC12_VDD_MONITOR_SET    OB_SDACD_VDD_MONITOR_SET\r\n#define OB_SDADC12_VDD_MONITOR_RESET  OB_SDACD_VDD_MONITOR_RESET\r\n#define OB_RAM_PARITY_CHECK_SET       OB_SRAM_PARITY_SET\r\n#define OB_RAM_PARITY_CHECK_RESET     OB_SRAM_PARITY_RESET\r\n#define IS_OB_SDADC12_VDD_MONITOR     IS_OB_SDACD_VDD_MONITOR\r\n#define OB_RDP_LEVEL0                 OB_RDP_LEVEL_0\r\n#define OB_RDP_LEVEL1                 OB_RDP_LEVEL_1\r\n#define OB_RDP_LEVEL2                 OB_RDP_LEVEL_2\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9    I2C_FASTMODEPLUS_PA9\r\n#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10   I2C_FASTMODEPLUS_PA10\r\n#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6    I2C_FASTMODEPLUS_PB6\r\n#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7    I2C_FASTMODEPLUS_PB7\r\n#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8    I2C_FASTMODEPLUS_PB8\r\n#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9    I2C_FASTMODEPLUS_PB9\r\n#define HAL_SYSCFG_FASTMODEPLUS_I2C1       I2C_FASTMODEPLUS_I2C1\r\n#define HAL_SYSCFG_FASTMODEPLUS_I2C2       I2C_FASTMODEPLUS_I2C2\r\n#define HAL_SYSCFG_FASTMODEPLUS_I2C3       I2C_FASTMODEPLUS_I2C3\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose\r\n  * @{\r\n  */\r\n#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7)\r\n#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE       FMC_NAND_WAIT_FEATURE_DISABLE\r\n#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE        FMC_NAND_WAIT_FEATURE_ENABLE\r\n#define FMC_NAND_PCC_MEM_BUS_WIDTH_8            FMC_NAND_MEM_BUS_WIDTH_8\r\n#define FMC_NAND_PCC_MEM_BUS_WIDTH_16           FMC_NAND_MEM_BUS_WIDTH_16\r\n#else\r\n#define FMC_NAND_WAIT_FEATURE_DISABLE           FMC_NAND_PCC_WAIT_FEATURE_DISABLE\r\n#define FMC_NAND_WAIT_FEATURE_ENABLE            FMC_NAND_PCC_WAIT_FEATURE_ENABLE\r\n#define FMC_NAND_MEM_BUS_WIDTH_8                FMC_NAND_PCC_MEM_BUS_WIDTH_8\r\n#define FMC_NAND_MEM_BUS_WIDTH_16               FMC_NAND_PCC_MEM_BUS_WIDTH_16\r\n#endif\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define FSMC_NORSRAM_TYPEDEF                      FSMC_NORSRAM_TypeDef\r\n#define FSMC_NORSRAM_EXTENDED_TYPEDEF             FSMC_NORSRAM_EXTENDED_TypeDef\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define GET_GPIO_SOURCE                           GPIO_GET_INDEX\r\n#define GET_GPIO_INDEX                            GPIO_GET_INDEX\r\n\r\n#if defined(STM32F4)\r\n#define GPIO_AF12_SDMMC                           GPIO_AF12_SDIO\r\n#define GPIO_AF12_SDMMC1                          GPIO_AF12_SDIO\r\n#endif\r\n\r\n#if defined(STM32F7)\r\n#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1\r\n#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1\r\n#endif\r\n\r\n#if defined(STM32L4)\r\n#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1\r\n#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1\r\n#endif\r\n\r\n#define GPIO_AF0_LPTIM                            GPIO_AF0_LPTIM1\r\n#define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1\r\n#define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1\r\n\r\n#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)\r\n#define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW\r\n#define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM\r\n#define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH\r\n#define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH\r\n#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */\r\n\r\n#if defined(STM32L1)\r\n #define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW\r\n #define  GPIO_SPEED_LOW         GPIO_SPEED_FREQ_MEDIUM\r\n #define  GPIO_SPEED_MEDIUM      GPIO_SPEED_FREQ_HIGH\r\n #define  GPIO_SPEED_HIGH        GPIO_SPEED_FREQ_VERY_HIGH\r\n#endif /* STM32L1 */\r\n\r\n#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)\r\n #define  GPIO_SPEED_LOW    GPIO_SPEED_FREQ_LOW\r\n #define  GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM\r\n #define  GPIO_SPEED_HIGH   GPIO_SPEED_FREQ_HIGH\r\n#endif /* STM32F0 || STM32F3 || STM32F1 */\r\n\r\n#define GPIO_AF6_DFSDM                            GPIO_AF6_DFSDM1\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#if defined(STM32H7)\r\n #define __HAL_RCC_JPEG_CLK_ENABLE               __HAL_RCC_JPGDECEN_CLK_ENABLE\r\n #define __HAL_RCC_JPEG_CLK_DISABLE              __HAL_RCC_JPGDECEN_CLK_DISABLE\r\n #define __HAL_RCC_JPEG_FORCE_RESET              __HAL_RCC_JPGDECRST_FORCE_RESET\r\n #define __HAL_RCC_JPEG_RELEASE_RESET            __HAL_RCC_JPGDECRST_RELEASE_RESET\r\n #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE         __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE\r\n #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE        __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE\r\n\r\n  #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1\r\n  #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2\r\n\r\n #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX\r\n #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX\r\n\r\n #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT\r\n #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT\r\n #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT\r\n #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT\r\n #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT\r\n #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT\r\n #define HAL_DMAMUX1_REQUEST_GEN_EXTI0              HAL_DMAMUX1_REQ_GEN_EXTI0\r\n #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO         HAL_DMAMUX1_REQ_GEN_TIM12_TRGO\r\n\r\n #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT\r\n #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT\r\n #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT\r\n #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT\r\n #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT\r\n #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT\r\n #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT\r\n #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP\r\n #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP\r\n #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP\r\n #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT\r\n #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP\r\n #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT\r\n #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP\r\n #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP\r\n #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP          HAL_DMAMUX2_REQ_GEN_I2C4_WKUP\r\n #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP          HAL_DMAMUX2_REQ_GEN_SPI6_WKUP\r\n #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT          HAL_DMAMUX2_REQ_GEN_COMP1_OUT\r\n #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT          HAL_DMAMUX2_REQ_GEN_COMP2_OUT\r\n #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP           HAL_DMAMUX2_REQ_GEN_RTC_WKUP\r\n #define HAL_DMAMUX2_REQUEST_GEN_EXTI0              HAL_DMAMUX2_REQ_GEN_EXTI0\r\n #define HAL_DMAMUX2_REQUEST_GEN_EXTI2              HAL_DMAMUX2_REQ_GEN_EXTI2\r\n #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT        HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT\r\n #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT            HAL_DMAMUX2_REQ_GEN_SPI6_IT\r\n #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT\r\n #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT\r\n #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT            HAL_DMAMUX2_REQ_GEN_ADC3_IT\r\n #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT      HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT\r\n #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT\r\n #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT\r\n\r\n #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT            HAL_DMAMUX_REQ_GEN_NO_EVENT\r\n #define HAL_DMAMUX_REQUEST_GEN_RISING              HAL_DMAMUX_REQ_GEN_RISING\r\n #define HAL_DMAMUX_REQUEST_GEN_FALLING             HAL_DMAMUX_REQ_GEN_FALLING\r\n #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING      HAL_DMAMUX_REQ_GEN_RISING_FALLING\r\n\r\n\r\n#endif /* STM32H7  */\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define HRTIM_TIMDELAYEDPROTECTION_DISABLED           HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED\r\n#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6\r\n#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6\r\n#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6\r\n#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6\r\n#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7\r\n#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7\r\n#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7\r\n#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7\r\n\r\n#define __HAL_HRTIM_SetCounter        __HAL_HRTIM_SETCOUNTER\r\n#define __HAL_HRTIM_GetCounter        __HAL_HRTIM_GETCOUNTER\r\n#define __HAL_HRTIM_SetPeriod         __HAL_HRTIM_SETPERIOD\r\n#define __HAL_HRTIM_GetPeriod         __HAL_HRTIM_GETPERIOD\r\n#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER\r\n#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER\r\n#define __HAL_HRTIM_SetCompare        __HAL_HRTIM_SETCOMPARE\r\n#define __HAL_HRTIM_GetCompare        __HAL_HRTIM_GETCOMPARE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define I2C_DUALADDRESS_DISABLED                I2C_DUALADDRESS_DISABLE\r\n#define I2C_DUALADDRESS_ENABLED                 I2C_DUALADDRESS_ENABLE\r\n#define I2C_GENERALCALL_DISABLED                I2C_GENERALCALL_DISABLE\r\n#define I2C_GENERALCALL_ENABLED                 I2C_GENERALCALL_ENABLE\r\n#define I2C_NOSTRETCH_DISABLED                  I2C_NOSTRETCH_DISABLE\r\n#define I2C_NOSTRETCH_ENABLED                   I2C_NOSTRETCH_ENABLE\r\n#define I2C_ANALOGFILTER_ENABLED                I2C_ANALOGFILTER_ENABLE\r\n#define I2C_ANALOGFILTER_DISABLED               I2C_ANALOGFILTER_DISABLE\r\n#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)\r\n#define HAL_I2C_STATE_MEM_BUSY_TX               HAL_I2C_STATE_BUSY_TX\r\n#define HAL_I2C_STATE_MEM_BUSY_RX               HAL_I2C_STATE_BUSY_RX\r\n#define HAL_I2C_STATE_MASTER_BUSY_TX            HAL_I2C_STATE_BUSY_TX\r\n#define HAL_I2C_STATE_MASTER_BUSY_RX            HAL_I2C_STATE_BUSY_RX\r\n#define HAL_I2C_STATE_SLAVE_BUSY_TX             HAL_I2C_STATE_BUSY_TX\r\n#define HAL_I2C_STATE_SLAVE_BUSY_RX             HAL_I2C_STATE_BUSY_RX\r\n#endif\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define IRDA_ONE_BIT_SAMPLE_DISABLED            IRDA_ONE_BIT_SAMPLE_DISABLE\r\n#define IRDA_ONE_BIT_SAMPLE_ENABLED             IRDA_ONE_BIT_SAMPLE_ENABLE\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define KR_KEY_RELOAD                   IWDG_KEY_RELOAD\r\n#define KR_KEY_ENABLE                   IWDG_KEY_ENABLE\r\n#define KR_KEY_EWA                      IWDG_KEY_WRITE_ACCESS_ENABLE\r\n#define KR_KEY_DWA                      IWDG_KEY_WRITE_ACCESS_DISABLE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION\r\n#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_2TRANSITIONS\r\n#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_4TRANSITIONS\r\n#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_8TRANSITIONS\r\n\r\n#define LPTIM_CLOCKPOLARITY_RISINGEDGE          LPTIM_CLOCKPOLARITY_RISING\r\n#define LPTIM_CLOCKPOLARITY_FALLINGEDGE         LPTIM_CLOCKPOLARITY_FALLING\r\n#define LPTIM_CLOCKPOLARITY_BOTHEDGES           LPTIM_CLOCKPOLARITY_RISING_FALLING\r\n\r\n#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION  LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION\r\n#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS      LPTIM_TRIGSAMPLETIME_2TRANSITIONS\r\n#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS      LPTIM_TRIGSAMPLETIME_4TRANSITIONS\r\n#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS      LPTIM_TRIGSAMPLETIME_8TRANSITIONS\r\n\r\n/* The following 3 definition have also been present in a temporary version of lptim.h */\r\n/* They need to be renamed also to the right name, just in case */\r\n#define LPTIM_TRIGSAMPLETIME_2TRANSITION        LPTIM_TRIGSAMPLETIME_2TRANSITIONS\r\n#define LPTIM_TRIGSAMPLETIME_4TRANSITION        LPTIM_TRIGSAMPLETIME_4TRANSITIONS\r\n#define LPTIM_TRIGSAMPLETIME_8TRANSITION        LPTIM_TRIGSAMPLETIME_8TRANSITIONS\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define HAL_NAND_Read_Page              HAL_NAND_Read_Page_8b\r\n#define HAL_NAND_Write_Page             HAL_NAND_Write_Page_8b\r\n#define HAL_NAND_Read_SpareArea         HAL_NAND_Read_SpareArea_8b\r\n#define HAL_NAND_Write_SpareArea        HAL_NAND_Write_SpareArea_8b\r\n\r\n#define NAND_AddressTypedef             NAND_AddressTypeDef\r\n\r\n#define __ARRAY_ADDRESS                 ARRAY_ADDRESS\r\n#define __ADDR_1st_CYCLE                ADDR_1ST_CYCLE\r\n#define __ADDR_2nd_CYCLE                ADDR_2ND_CYCLE\r\n#define __ADDR_3rd_CYCLE                ADDR_3RD_CYCLE\r\n#define __ADDR_4th_CYCLE                ADDR_4TH_CYCLE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define NOR_StatusTypedef              HAL_NOR_StatusTypeDef\r\n#define NOR_SUCCESS                    HAL_NOR_STATUS_SUCCESS\r\n#define NOR_ONGOING                    HAL_NOR_STATUS_ONGOING\r\n#define NOR_ERROR                      HAL_NOR_STATUS_ERROR\r\n#define NOR_TIMEOUT                    HAL_NOR_STATUS_TIMEOUT\r\n\r\n#define __NOR_WRITE                    NOR_WRITE\r\n#define __NOR_ADDR_SHIFT               NOR_ADDR_SHIFT\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define OPAMP_NONINVERTINGINPUT_VP0           OPAMP_NONINVERTINGINPUT_IO0\r\n#define OPAMP_NONINVERTINGINPUT_VP1           OPAMP_NONINVERTINGINPUT_IO1\r\n#define OPAMP_NONINVERTINGINPUT_VP2           OPAMP_NONINVERTINGINPUT_IO2\r\n#define OPAMP_NONINVERTINGINPUT_VP3           OPAMP_NONINVERTINGINPUT_IO3\r\n\r\n#define OPAMP_SEC_NONINVERTINGINPUT_VP0       OPAMP_SEC_NONINVERTINGINPUT_IO0\r\n#define OPAMP_SEC_NONINVERTINGINPUT_VP1       OPAMP_SEC_NONINVERTINGINPUT_IO1\r\n#define OPAMP_SEC_NONINVERTINGINPUT_VP2       OPAMP_SEC_NONINVERTINGINPUT_IO2\r\n#define OPAMP_SEC_NONINVERTINGINPUT_VP3       OPAMP_SEC_NONINVERTINGINPUT_IO3\r\n\r\n#define OPAMP_INVERTINGINPUT_VM0              OPAMP_INVERTINGINPUT_IO0\r\n#define OPAMP_INVERTINGINPUT_VM1              OPAMP_INVERTINGINPUT_IO1\r\n\r\n#define IOPAMP_INVERTINGINPUT_VM0             OPAMP_INVERTINGINPUT_IO0\r\n#define IOPAMP_INVERTINGINPUT_VM1             OPAMP_INVERTINGINPUT_IO1\r\n\r\n#define OPAMP_SEC_INVERTINGINPUT_VM0          OPAMP_SEC_INVERTINGINPUT_IO0\r\n#define OPAMP_SEC_INVERTINGINPUT_VM1          OPAMP_SEC_INVERTINGINPUT_IO1\r\n\r\n#define OPAMP_INVERTINGINPUT_VINM             OPAMP_SEC_INVERTINGINPUT_IO1\r\n\r\n#define OPAMP_PGACONNECT_NO                   OPAMP_PGA_CONNECT_INVERTINGINPUT_NO\r\n#define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0\r\n#define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define I2S_STANDARD_PHILLIPS      I2S_STANDARD_PHILIPS\r\n#if defined(STM32F7)\r\n  #define I2S_CLOCK_SYSCLK           I2S_CLOCK_PLL\r\n#endif\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n/* Compact Flash-ATA registers description */\r\n#define CF_DATA                       ATA_DATA\r\n#define CF_SECTOR_COUNT               ATA_SECTOR_COUNT\r\n#define CF_SECTOR_NUMBER              ATA_SECTOR_NUMBER\r\n#define CF_CYLINDER_LOW               ATA_CYLINDER_LOW\r\n#define CF_CYLINDER_HIGH              ATA_CYLINDER_HIGH\r\n#define CF_CARD_HEAD                  ATA_CARD_HEAD\r\n#define CF_STATUS_CMD                 ATA_STATUS_CMD\r\n#define CF_STATUS_CMD_ALTERNATE       ATA_STATUS_CMD_ALTERNATE\r\n#define CF_COMMON_DATA_AREA           ATA_COMMON_DATA_AREA\r\n\r\n/* Compact Flash-ATA commands */\r\n#define CF_READ_SECTOR_CMD            ATA_READ_SECTOR_CMD\r\n#define CF_WRITE_SECTOR_CMD           ATA_WRITE_SECTOR_CMD\r\n#define CF_ERASE_SECTOR_CMD           ATA_ERASE_SECTOR_CMD\r\n#define CF_IDENTIFY_CMD               ATA_IDENTIFY_CMD\r\n\r\n#define PCCARD_StatusTypedef          HAL_PCCARD_StatusTypeDef\r\n#define PCCARD_SUCCESS                HAL_PCCARD_STATUS_SUCCESS\r\n#define PCCARD_ONGOING                HAL_PCCARD_STATUS_ONGOING\r\n#define PCCARD_ERROR                  HAL_PCCARD_STATUS_ERROR\r\n#define PCCARD_TIMEOUT                HAL_PCCARD_STATUS_TIMEOUT\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define FORMAT_BIN                  RTC_FORMAT_BIN\r\n#define FORMAT_BCD                  RTC_FORMAT_BCD\r\n\r\n#define RTC_ALARMSUBSECONDMASK_None     RTC_ALARMSUBSECONDMASK_NONE\r\n#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE\r\n#define RTC_TAMPERMASK_FLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE\r\n#define RTC_TAMPERMASK_FLAG_ENABLED     RTC_TAMPERMASK_FLAG_ENABLE\r\n\r\n#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE\r\n#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE\r\n#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE\r\n#define RTC_TAMPER1_2_INTERRUPT         RTC_ALL_TAMPER_INTERRUPT\r\n#define RTC_TAMPER1_2_3_INTERRUPT       RTC_ALL_TAMPER_INTERRUPT\r\n\r\n#define RTC_TIMESTAMPPIN_PC13  RTC_TIMESTAMPPIN_DEFAULT\r\n#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1\r\n#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1\r\n#define RTC_TIMESTAMPPIN_PC1   RTC_TIMESTAMPPIN_POS2\r\n\r\n#define RTC_OUTPUT_REMAP_PC13  RTC_OUTPUT_REMAP_NONE\r\n#define RTC_OUTPUT_REMAP_PB14  RTC_OUTPUT_REMAP_POS1\r\n#define RTC_OUTPUT_REMAP_PB2   RTC_OUTPUT_REMAP_POS1\r\n\r\n#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT\r\n#define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1\r\n#define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define SMARTCARD_NACK_ENABLED                  SMARTCARD_NACK_ENABLE\r\n#define SMARTCARD_NACK_DISABLED                 SMARTCARD_NACK_DISABLE\r\n\r\n#define SMARTCARD_ONEBIT_SAMPLING_DISABLED      SMARTCARD_ONE_BIT_SAMPLE_DISABLE\r\n#define SMARTCARD_ONEBIT_SAMPLING_ENABLED       SMARTCARD_ONE_BIT_SAMPLE_ENABLE\r\n#define SMARTCARD_ONEBIT_SAMPLING_DISABLE       SMARTCARD_ONE_BIT_SAMPLE_DISABLE\r\n#define SMARTCARD_ONEBIT_SAMPLING_ENABLE        SMARTCARD_ONE_BIT_SAMPLE_ENABLE\r\n\r\n#define SMARTCARD_TIMEOUT_DISABLED              SMARTCARD_TIMEOUT_DISABLE\r\n#define SMARTCARD_TIMEOUT_ENABLED               SMARTCARD_TIMEOUT_ENABLE\r\n\r\n#define SMARTCARD_LASTBIT_DISABLED              SMARTCARD_LASTBIT_DISABLE\r\n#define SMARTCARD_LASTBIT_ENABLED               SMARTCARD_LASTBIT_ENABLE\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define SMBUS_DUALADDRESS_DISABLED      SMBUS_DUALADDRESS_DISABLE\r\n#define SMBUS_DUALADDRESS_ENABLED       SMBUS_DUALADDRESS_ENABLE\r\n#define SMBUS_GENERALCALL_DISABLED      SMBUS_GENERALCALL_DISABLE\r\n#define SMBUS_GENERALCALL_ENABLED       SMBUS_GENERALCALL_ENABLE\r\n#define SMBUS_NOSTRETCH_DISABLED        SMBUS_NOSTRETCH_DISABLE\r\n#define SMBUS_NOSTRETCH_ENABLED         SMBUS_NOSTRETCH_ENABLE\r\n#define SMBUS_ANALOGFILTER_ENABLED      SMBUS_ANALOGFILTER_ENABLE\r\n#define SMBUS_ANALOGFILTER_DISABLED     SMBUS_ANALOGFILTER_DISABLE\r\n#define SMBUS_PEC_DISABLED              SMBUS_PEC_DISABLE\r\n#define SMBUS_PEC_ENABLED               SMBUS_PEC_ENABLE\r\n#define HAL_SMBUS_STATE_SLAVE_LISTEN    HAL_SMBUS_STATE_LISTEN\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define SPI_TIMODE_DISABLED             SPI_TIMODE_DISABLE\r\n#define SPI_TIMODE_ENABLED              SPI_TIMODE_ENABLE\r\n\r\n#define SPI_CRCCALCULATION_DISABLED     SPI_CRCCALCULATION_DISABLE\r\n#define SPI_CRCCALCULATION_ENABLED      SPI_CRCCALCULATION_ENABLE\r\n\r\n#define SPI_NSS_PULSE_DISABLED          SPI_NSS_PULSE_DISABLE\r\n#define SPI_NSS_PULSE_ENABLED           SPI_NSS_PULSE_ENABLE\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define CCER_CCxE_MASK                   TIM_CCER_CCxE_MASK\r\n#define CCER_CCxNE_MASK                  TIM_CCER_CCxNE_MASK\r\n\r\n#define TIM_DMABase_CR1                  TIM_DMABASE_CR1\r\n#define TIM_DMABase_CR2                  TIM_DMABASE_CR2\r\n#define TIM_DMABase_SMCR                 TIM_DMABASE_SMCR\r\n#define TIM_DMABase_DIER                 TIM_DMABASE_DIER\r\n#define TIM_DMABase_SR                   TIM_DMABASE_SR\r\n#define TIM_DMABase_EGR                  TIM_DMABASE_EGR\r\n#define TIM_DMABase_CCMR1                TIM_DMABASE_CCMR1\r\n#define TIM_DMABase_CCMR2                TIM_DMABASE_CCMR2\r\n#define TIM_DMABase_CCER                 TIM_DMABASE_CCER\r\n#define TIM_DMABase_CNT                  TIM_DMABASE_CNT\r\n#define TIM_DMABase_PSC                  TIM_DMABASE_PSC\r\n#define TIM_DMABase_ARR                  TIM_DMABASE_ARR\r\n#define TIM_DMABase_RCR                  TIM_DMABASE_RCR\r\n#define TIM_DMABase_CCR1                 TIM_DMABASE_CCR1\r\n#define TIM_DMABase_CCR2                 TIM_DMABASE_CCR2\r\n#define TIM_DMABase_CCR3                 TIM_DMABASE_CCR3\r\n#define TIM_DMABase_CCR4                 TIM_DMABASE_CCR4\r\n#define TIM_DMABase_BDTR                 TIM_DMABASE_BDTR\r\n#define TIM_DMABase_DCR                  TIM_DMABASE_DCR\r\n#define TIM_DMABase_DMAR                 TIM_DMABASE_DMAR\r\n#define TIM_DMABase_OR1                  TIM_DMABASE_OR1\r\n#define TIM_DMABase_CCMR3                TIM_DMABASE_CCMR3\r\n#define TIM_DMABase_CCR5                 TIM_DMABASE_CCR5\r\n#define TIM_DMABase_CCR6                 TIM_DMABASE_CCR6\r\n#define TIM_DMABase_OR2                  TIM_DMABASE_OR2\r\n#define TIM_DMABase_OR3                  TIM_DMABASE_OR3\r\n#define TIM_DMABase_OR                   TIM_DMABASE_OR\r\n\r\n#define TIM_EventSource_Update           TIM_EVENTSOURCE_UPDATE\r\n#define TIM_EventSource_CC1              TIM_EVENTSOURCE_CC1\r\n#define TIM_EventSource_CC2              TIM_EVENTSOURCE_CC2\r\n#define TIM_EventSource_CC3              TIM_EVENTSOURCE_CC3\r\n#define TIM_EventSource_CC4              TIM_EVENTSOURCE_CC4\r\n#define TIM_EventSource_COM              TIM_EVENTSOURCE_COM\r\n#define TIM_EventSource_Trigger          TIM_EVENTSOURCE_TRIGGER\r\n#define TIM_EventSource_Break            TIM_EVENTSOURCE_BREAK\r\n#define TIM_EventSource_Break2           TIM_EVENTSOURCE_BREAK2\r\n\r\n#define TIM_DMABurstLength_1Transfer     TIM_DMABURSTLENGTH_1TRANSFER\r\n#define TIM_DMABurstLength_2Transfers    TIM_DMABURSTLENGTH_2TRANSFERS\r\n#define TIM_DMABurstLength_3Transfers    TIM_DMABURSTLENGTH_3TRANSFERS\r\n#define TIM_DMABurstLength_4Transfers    TIM_DMABURSTLENGTH_4TRANSFERS\r\n#define TIM_DMABurstLength_5Transfers    TIM_DMABURSTLENGTH_5TRANSFERS\r\n#define TIM_DMABurstLength_6Transfers    TIM_DMABURSTLENGTH_6TRANSFERS\r\n#define TIM_DMABurstLength_7Transfers    TIM_DMABURSTLENGTH_7TRANSFERS\r\n#define TIM_DMABurstLength_8Transfers    TIM_DMABURSTLENGTH_8TRANSFERS\r\n#define TIM_DMABurstLength_9Transfers    TIM_DMABURSTLENGTH_9TRANSFERS\r\n#define TIM_DMABurstLength_10Transfers   TIM_DMABURSTLENGTH_10TRANSFERS\r\n#define TIM_DMABurstLength_11Transfers   TIM_DMABURSTLENGTH_11TRANSFERS\r\n#define TIM_DMABurstLength_12Transfers   TIM_DMABURSTLENGTH_12TRANSFERS\r\n#define TIM_DMABurstLength_13Transfers   TIM_DMABURSTLENGTH_13TRANSFERS\r\n#define TIM_DMABurstLength_14Transfers   TIM_DMABURSTLENGTH_14TRANSFERS\r\n#define TIM_DMABurstLength_15Transfers   TIM_DMABURSTLENGTH_15TRANSFERS\r\n#define TIM_DMABurstLength_16Transfers   TIM_DMABURSTLENGTH_16TRANSFERS\r\n#define TIM_DMABurstLength_17Transfers   TIM_DMABURSTLENGTH_17TRANSFERS\r\n#define TIM_DMABurstLength_18Transfers   TIM_DMABURSTLENGTH_18TRANSFERS\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define TSC_SYNC_POL_FALL        TSC_SYNC_POLARITY_FALLING\r\n#define TSC_SYNC_POL_RISE_HIGH   TSC_SYNC_POLARITY_RISING\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define UART_ONEBIT_SAMPLING_DISABLED   UART_ONE_BIT_SAMPLE_DISABLE\r\n#define UART_ONEBIT_SAMPLING_ENABLED    UART_ONE_BIT_SAMPLE_ENABLE\r\n#define UART_ONE_BIT_SAMPLE_DISABLED    UART_ONE_BIT_SAMPLE_DISABLE\r\n#define UART_ONE_BIT_SAMPLE_ENABLED     UART_ONE_BIT_SAMPLE_ENABLE\r\n\r\n#define __HAL_UART_ONEBIT_ENABLE        __HAL_UART_ONE_BIT_SAMPLE_ENABLE\r\n#define __HAL_UART_ONEBIT_DISABLE       __HAL_UART_ONE_BIT_SAMPLE_DISABLE\r\n\r\n#define __DIV_SAMPLING16                UART_DIV_SAMPLING16\r\n#define __DIVMANT_SAMPLING16            UART_DIVMANT_SAMPLING16\r\n#define __DIVFRAQ_SAMPLING16            UART_DIVFRAQ_SAMPLING16\r\n#define __UART_BRR_SAMPLING16           UART_BRR_SAMPLING16\r\n\r\n#define __DIV_SAMPLING8                 UART_DIV_SAMPLING8\r\n#define __DIVMANT_SAMPLING8             UART_DIVMANT_SAMPLING8\r\n#define __DIVFRAQ_SAMPLING8             UART_DIVFRAQ_SAMPLING8\r\n#define __UART_BRR_SAMPLING8            UART_BRR_SAMPLING8\r\n\r\n#define __DIV_LPUART                    UART_DIV_LPUART\r\n\r\n#define UART_WAKEUPMETHODE_IDLELINE     UART_WAKEUPMETHOD_IDLELINE\r\n#define UART_WAKEUPMETHODE_ADDRESSMARK  UART_WAKEUPMETHOD_ADDRESSMARK\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define USART_CLOCK_DISABLED            USART_CLOCK_DISABLE\r\n#define USART_CLOCK_ENABLED             USART_CLOCK_ENABLE\r\n\r\n#define USARTNACK_ENABLED               USART_NACK_ENABLE\r\n#define USARTNACK_DISABLED              USART_NACK_DISABLE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define CFR_BASE                    WWDG_CFR_BASE\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define CAN_FilterFIFO0             CAN_FILTER_FIFO0\r\n#define CAN_FilterFIFO1             CAN_FILTER_FIFO1\r\n#define CAN_IT_RQCP0                CAN_IT_TME\r\n#define CAN_IT_RQCP1                CAN_IT_TME\r\n#define CAN_IT_RQCP2                CAN_IT_TME\r\n#define INAK_TIMEOUT                CAN_TIMEOUT_VALUE\r\n#define SLAK_TIMEOUT                CAN_TIMEOUT_VALUE\r\n#define CAN_TXSTATUS_FAILED         ((uint8_t)0x00U)\r\n#define CAN_TXSTATUS_OK             ((uint8_t)0x01U)\r\n#define CAN_TXSTATUS_PENDING        ((uint8_t)0x02U)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define VLAN_TAG                ETH_VLAN_TAG\r\n#define MIN_ETH_PAYLOAD         ETH_MIN_ETH_PAYLOAD\r\n#define MAX_ETH_PAYLOAD         ETH_MAX_ETH_PAYLOAD\r\n#define JUMBO_FRAME_PAYLOAD     ETH_JUMBO_FRAME_PAYLOAD\r\n#define MACMIIAR_CR_MASK        ETH_MACMIIAR_CR_MASK\r\n#define MACCR_CLEAR_MASK        ETH_MACCR_CLEAR_MASK\r\n#define MACFCR_CLEAR_MASK       ETH_MACFCR_CLEAR_MASK\r\n#define DMAOMR_CLEAR_MASK       ETH_DMAOMR_CLEAR_MASK\r\n\r\n#define ETH_MMCCR              0x00000100U\r\n#define ETH_MMCRIR             0x00000104U\r\n#define ETH_MMCTIR             0x00000108U\r\n#define ETH_MMCRIMR            0x0000010CU\r\n#define ETH_MMCTIMR            0x00000110U\r\n#define ETH_MMCTGFSCCR         0x0000014CU\r\n#define ETH_MMCTGFMSCCR        0x00000150U\r\n#define ETH_MMCTGFCR           0x00000168U\r\n#define ETH_MMCRFCECR          0x00000194U\r\n#define ETH_MMCRFAECR          0x00000198U\r\n#define ETH_MMCRGUFCR          0x000001C4U\r\n\r\n#define ETH_MAC_TXFIFO_FULL                             0x02000000U  /* Tx FIFO full */\r\n#define ETH_MAC_TXFIFONOT_EMPTY                         0x01000000U  /* Tx FIFO not empty */\r\n#define ETH_MAC_TXFIFO_WRITE_ACTIVE                     0x00400000U  /* Tx FIFO write active */\r\n#define ETH_MAC_TXFIFO_IDLE                             0x00000000U  /* Tx FIFO read status: Idle */\r\n#define ETH_MAC_TXFIFO_READ                             0x00100000U  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */\r\n#define ETH_MAC_TXFIFO_WAITING                          0x00200000U  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */\r\n#define ETH_MAC_TXFIFO_WRITING                          0x00300000U  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */\r\n#define ETH_MAC_TRANSMISSION_PAUSE                      0x00080000U  /* MAC transmitter in pause */\r\n#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE            0x00000000U  /* MAC transmit frame controller: Idle */\r\n#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         0x00020000U  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */\r\n#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   0x00040000U  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */\r\n#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    0x00060000U  /* MAC transmit frame controller: Transferring input frame for transmission */\r\n#define ETH_MAC_MII_TRANSMIT_ACTIVE           0x00010000U  /* MAC MII transmit engine active */\r\n#define ETH_MAC_RXFIFO_EMPTY                  0x00000000U  /* Rx FIFO fill level: empty */\r\n#define ETH_MAC_RXFIFO_BELOW_THRESHOLD        0x00000100U  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */\r\n#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD        0x00000200U  /* Rx FIFO fill level: fill-level above flow-control activate threshold */\r\n#define ETH_MAC_RXFIFO_FULL                   0x00000300U  /* Rx FIFO fill level: full */\r\n#if defined(STM32F1)\r\n#else\r\n#define ETH_MAC_READCONTROLLER_IDLE           0x00000000U  /* Rx FIFO read controller IDLE state */\r\n#define ETH_MAC_READCONTROLLER_READING_DATA   0x00000020U  /* Rx FIFO read controller Reading frame data */\r\n#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U  /* Rx FIFO read controller Reading frame status (or time-stamp) */\r\n#endif\r\n#define ETH_MAC_READCONTROLLER_FLUSHING       0x00000060U  /* Rx FIFO read controller Flushing the frame data and status */\r\n#define ETH_MAC_RXFIFO_WRITE_ACTIVE           0x00000010U  /* Rx FIFO write controller active */\r\n#define ETH_MAC_SMALL_FIFO_NOTACTIVE          0x00000000U  /* MAC small FIFO read / write controllers not active */\r\n#define ETH_MAC_SMALL_FIFO_READ_ACTIVE        0x00000002U  /* MAC small FIFO read controller active */\r\n#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE       0x00000004U  /* MAC small FIFO write controller active */\r\n#define ETH_MAC_SMALL_FIFO_RW_ACTIVE          0x00000006U  /* MAC small FIFO read / write controllers active */\r\n#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   0x00000001U  /* MAC MII receive protocol engine active */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define HAL_DCMI_ERROR_OVF      HAL_DCMI_ERROR_OVR\r\n#define DCMI_IT_OVF             DCMI_IT_OVR\r\n#define DCMI_FLAG_OVFRI         DCMI_FLAG_OVRRI\r\n#define DCMI_FLAG_OVFMI         DCMI_FLAG_OVRMI\r\n\r\n#define HAL_DCMI_ConfigCROP     HAL_DCMI_ConfigCrop\r\n#define HAL_DCMI_EnableCROP     HAL_DCMI_EnableCrop\r\n#define HAL_DCMI_DisableCROP    HAL_DCMI_DisableCrop\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\\\r\n    defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)\r\n/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define DMA2D_ARGB8888          DMA2D_OUTPUT_ARGB8888\r\n#define DMA2D_RGB888            DMA2D_OUTPUT_RGB888\r\n#define DMA2D_RGB565            DMA2D_OUTPUT_RGB565\r\n#define DMA2D_ARGB1555          DMA2D_OUTPUT_ARGB1555\r\n#define DMA2D_ARGB4444          DMA2D_OUTPUT_ARGB4444\r\n\r\n#define CM_ARGB8888             DMA2D_INPUT_ARGB8888\r\n#define CM_RGB888               DMA2D_INPUT_RGB888\r\n#define CM_RGB565               DMA2D_INPUT_RGB565\r\n#define CM_ARGB1555             DMA2D_INPUT_ARGB1555\r\n#define CM_ARGB4444             DMA2D_INPUT_ARGB4444\r\n#define CM_L8                   DMA2D_INPUT_L8\r\n#define CM_AL44                 DMA2D_INPUT_AL44\r\n#define CM_AL88                 DMA2D_INPUT_AL88\r\n#define CM_L4                   DMA2D_INPUT_L4\r\n#define CM_A8                   DMA2D_INPUT_A8\r\n#define CM_A4                   DMA2D_INPUT_A4\r\n/**\r\n  * @}\r\n  */\r\n#endif  /* STM32L4 ||  STM32F7*/\r\n\r\n/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define HAL_CRYP_ComputationCpltCallback     HAL_CRYPEx_ComputationCpltCallback\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define HAL_HASH_STATETypeDef        HAL_HASH_StateTypeDef\r\n#define HAL_HASHPhaseTypeDef         HAL_HASH_PhaseTypeDef\r\n#define HAL_HMAC_MD5_Finish          HAL_HASH_MD5_Finish\r\n#define HAL_HMAC_SHA1_Finish         HAL_HASH_SHA1_Finish\r\n#define HAL_HMAC_SHA224_Finish       HAL_HASH_SHA224_Finish\r\n#define HAL_HMAC_SHA256_Finish       HAL_HASH_SHA256_Finish\r\n\r\n/*HASH Algorithm Selection*/\r\n\r\n#define HASH_AlgoSelection_SHA1      HASH_ALGOSELECTION_SHA1\r\n#define HASH_AlgoSelection_SHA224    HASH_ALGOSELECTION_SHA224\r\n#define HASH_AlgoSelection_SHA256    HASH_ALGOSELECTION_SHA256\r\n#define HASH_AlgoSelection_MD5       HASH_ALGOSELECTION_MD5\r\n\r\n#define HASH_AlgoMode_HASH         HASH_ALGOMODE_HASH\r\n#define HASH_AlgoMode_HMAC         HASH_ALGOMODE_HMAC\r\n\r\n#define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY\r\n#define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode\r\n#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode\r\n#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode\r\n#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode\r\n#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode\r\n#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode\r\n#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))\r\n#define HAL_VREFINT_OutputSelect  HAL_SYSCFG_VREFINT_OutputSelect\r\n#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())\r\n#if defined(STM32L0)\r\n#else\r\n#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())\r\n#endif\r\n#define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())\r\n#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define FLASH_HalfPageProgram      HAL_FLASHEx_HalfPageProgram\r\n#define FLASH_EnableRunPowerDown   HAL_FLASHEx_EnableRunPowerDown\r\n#define FLASH_DisableRunPowerDown  HAL_FLASHEx_DisableRunPowerDown\r\n#define HAL_DATA_EEPROMEx_Unlock   HAL_FLASHEx_DATAEEPROM_Unlock\r\n#define HAL_DATA_EEPROMEx_Lock     HAL_FLASHEx_DATAEEPROM_Lock\r\n#define HAL_DATA_EEPROMEx_Erase    HAL_FLASHEx_DATAEEPROM_Erase\r\n#define HAL_DATA_EEPROMEx_Program  HAL_FLASHEx_DATAEEPROM_Program\r\n\r\n /**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define HAL_I2CEx_AnalogFilter_Config         HAL_I2CEx_ConfigAnalogFilter\r\n#define HAL_I2CEx_DigitalFilter_Config        HAL_I2CEx_ConfigDigitalFilter\r\n#define HAL_FMPI2CEx_AnalogFilter_Config      HAL_FMPI2CEx_ConfigAnalogFilter\r\n#define HAL_FMPI2CEx_DigitalFilter_Config     HAL_FMPI2CEx_ConfigDigitalFilter\r\n\r\n#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))\r\n /**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define HAL_PWR_PVDConfig                             HAL_PWR_ConfigPVD\r\n#define HAL_PWR_DisableBkUpReg                        HAL_PWREx_DisableBkUpReg\r\n#define HAL_PWR_DisableFlashPowerDown                 HAL_PWREx_DisableFlashPowerDown\r\n#define HAL_PWR_DisableVddio2Monitor                  HAL_PWREx_DisableVddio2Monitor\r\n#define HAL_PWR_EnableBkUpReg                         HAL_PWREx_EnableBkUpReg\r\n#define HAL_PWR_EnableFlashPowerDown                  HAL_PWREx_EnableFlashPowerDown\r\n#define HAL_PWR_EnableVddio2Monitor                   HAL_PWREx_EnableVddio2Monitor\r\n#define HAL_PWR_PVD_PVM_IRQHandler                    HAL_PWREx_PVD_PVM_IRQHandler\r\n#define HAL_PWR_PVDLevelConfig                        HAL_PWR_ConfigPVD\r\n#define HAL_PWR_Vddio2Monitor_IRQHandler              HAL_PWREx_Vddio2Monitor_IRQHandler\r\n#define HAL_PWR_Vddio2MonitorCallback                 HAL_PWREx_Vddio2MonitorCallback\r\n#define HAL_PWREx_ActivateOverDrive                   HAL_PWREx_EnableOverDrive\r\n#define HAL_PWREx_DeactivateOverDrive                 HAL_PWREx_DisableOverDrive\r\n#define HAL_PWREx_DisableSDADCAnalog                  HAL_PWREx_DisableSDADC\r\n#define HAL_PWREx_EnableSDADCAnalog                   HAL_PWREx_EnableSDADC\r\n#define HAL_PWREx_PVMConfig                           HAL_PWREx_ConfigPVM\r\n\r\n#define PWR_MODE_NORMAL                               PWR_PVD_MODE_NORMAL\r\n#define PWR_MODE_IT_RISING                            PWR_PVD_MODE_IT_RISING\r\n#define PWR_MODE_IT_FALLING                           PWR_PVD_MODE_IT_FALLING\r\n#define PWR_MODE_IT_RISING_FALLING                    PWR_PVD_MODE_IT_RISING_FALLING\r\n#define PWR_MODE_EVENT_RISING                         PWR_PVD_MODE_EVENT_RISING\r\n#define PWR_MODE_EVENT_FALLING                        PWR_PVD_MODE_EVENT_FALLING\r\n#define PWR_MODE_EVENT_RISING_FALLING                 PWR_PVD_MODE_EVENT_RISING_FALLING\r\n\r\n#define CR_OFFSET_BB                                  PWR_CR_OFFSET_BB\r\n#define CSR_OFFSET_BB                                 PWR_CSR_OFFSET_BB\r\n#define PMODE_BIT_NUMBER                              VOS_BIT_NUMBER\r\n#define CR_PMODE_BB                                   CR_VOS_BB\r\n\r\n#define DBP_BitNumber                                 DBP_BIT_NUMBER\r\n#define PVDE_BitNumber                                PVDE_BIT_NUMBER\r\n#define PMODE_BitNumber                               PMODE_BIT_NUMBER\r\n#define EWUP_BitNumber                                EWUP_BIT_NUMBER\r\n#define FPDS_BitNumber                                FPDS_BIT_NUMBER\r\n#define ODEN_BitNumber                                ODEN_BIT_NUMBER\r\n#define ODSWEN_BitNumber                              ODSWEN_BIT_NUMBER\r\n#define MRLVDS_BitNumber                              MRLVDS_BIT_NUMBER\r\n#define LPLVDS_BitNumber                              LPLVDS_BIT_NUMBER\r\n#define BRE_BitNumber                                 BRE_BIT_NUMBER\r\n\r\n#define PWR_MODE_EVT                                  PWR_PVD_MODE_NORMAL\r\n\r\n /**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define HAL_SMBUS_Slave_Listen_IT          HAL_SMBUS_EnableListen_IT\r\n#define HAL_SMBUS_SlaveAddrCallback        HAL_SMBUS_AddrCallback\r\n#define HAL_SMBUS_SlaveListenCpltCallback  HAL_SMBUS_ListenCpltCallback\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define HAL_SPI_FlushRxFifo                HAL_SPIEx_FlushRxFifo\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define HAL_TIM_DMADelayPulseCplt                       TIM_DMADelayPulseCplt\r\n#define HAL_TIM_DMAError                                TIM_DMAError\r\n#define HAL_TIM_DMACaptureCplt                          TIM_DMACaptureCplt\r\n#define HAL_TIMEx_DMACommutationCplt                    TIMEx_DMACommutationCplt\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback\r\n#define HAL_LTDC_Relaod           HAL_LTDC_Reload\r\n#define HAL_LTDC_StructInitFromVideoConfig  HAL_LTDCEx_StructInitFromVideoConfig\r\n#define HAL_LTDC_StructInitFromAdaptedCommandConfig  HAL_LTDCEx_StructInitFromAdaptedCommandConfig\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macros ------------------------------------------------------------*/\r\n\r\n/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define AES_IT_CC                      CRYP_IT_CC\r\n#define AES_IT_ERR                     CRYP_IT_ERR\r\n#define AES_FLAG_CCF                   CRYP_FLAG_CCF\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define __HAL_GET_BOOT_MODE                   __HAL_SYSCFG_GET_BOOT_MODE\r\n#define __HAL_REMAPMEMORY_FLASH               __HAL_SYSCFG_REMAPMEMORY_FLASH\r\n#define __HAL_REMAPMEMORY_SYSTEMFLASH         __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH\r\n#define __HAL_REMAPMEMORY_SRAM                __HAL_SYSCFG_REMAPMEMORY_SRAM\r\n#define __HAL_REMAPMEMORY_FMC                 __HAL_SYSCFG_REMAPMEMORY_FMC\r\n#define __HAL_REMAPMEMORY_FMC_SDRAM           __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM\r\n#define __HAL_REMAPMEMORY_FSMC                __HAL_SYSCFG_REMAPMEMORY_FSMC\r\n#define __HAL_REMAPMEMORY_QUADSPI             __HAL_SYSCFG_REMAPMEMORY_QUADSPI\r\n#define __HAL_FMC_BANK                        __HAL_SYSCFG_FMC_BANK\r\n#define __HAL_GET_FLAG                        __HAL_SYSCFG_GET_FLAG\r\n#define __HAL_CLEAR_FLAG                      __HAL_SYSCFG_CLEAR_FLAG\r\n#define __HAL_VREFINT_OUT_ENABLE              __HAL_SYSCFG_VREFINT_OUT_ENABLE\r\n#define __HAL_VREFINT_OUT_DISABLE             __HAL_SYSCFG_VREFINT_OUT_DISABLE\r\n#define __HAL_SYSCFG_SRAM2_WRP_ENABLE         __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE\r\n\r\n#define SYSCFG_FLAG_VREF_READY                SYSCFG_FLAG_VREFINT_READY\r\n#define SYSCFG_FLAG_RC48                      RCC_FLAG_HSI48\r\n#define IS_SYSCFG_FASTMODEPLUS_CONFIG         IS_I2C_FASTMODEPLUS\r\n#define UFB_MODE_BitNumber                    UFB_MODE_BIT_NUMBER\r\n#define CMP_PD_BitNumber                      CMP_PD_BIT_NUMBER\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define __ADC_ENABLE                                     __HAL_ADC_ENABLE\r\n#define __ADC_DISABLE                                    __HAL_ADC_DISABLE\r\n#define __HAL_ADC_ENABLING_CONDITIONS                    ADC_ENABLING_CONDITIONS\r\n#define __HAL_ADC_DISABLING_CONDITIONS                   ADC_DISABLING_CONDITIONS\r\n#define __HAL_ADC_IS_ENABLED                             ADC_IS_ENABLE\r\n#define __ADC_IS_ENABLED                                 ADC_IS_ENABLE\r\n#define __HAL_ADC_IS_SOFTWARE_START_REGULAR              ADC_IS_SOFTWARE_START_REGULAR\r\n#define __HAL_ADC_IS_SOFTWARE_START_INJECTED             ADC_IS_SOFTWARE_START_INJECTED\r\n#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED\r\n#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR          ADC_IS_CONVERSION_ONGOING_REGULAR\r\n#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED         ADC_IS_CONVERSION_ONGOING_INJECTED\r\n#define __HAL_ADC_IS_CONVERSION_ONGOING                  ADC_IS_CONVERSION_ONGOING\r\n#define __HAL_ADC_CLEAR_ERRORCODE                        ADC_CLEAR_ERRORCODE\r\n\r\n#define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION\r\n#define __HAL_ADC_JSQR_RK                                ADC_JSQR_RK\r\n#define __HAL_ADC_CFGR_AWD1CH                            ADC_CFGR_AWD1CH_SHIFT\r\n#define __HAL_ADC_CFGR_AWD23CR                           ADC_CFGR_AWD23CR\r\n#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION            ADC_CFGR_INJECT_AUTO_CONVERSION\r\n#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE              ADC_CFGR_INJECT_CONTEXT_QUEUE\r\n#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS             ADC_CFGR_INJECT_DISCCONTINUOUS\r\n#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS                ADC_CFGR_REG_DISCCONTINUOUS\r\n#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM                 ADC_CFGR_DISCONTINUOUS_NUM\r\n#define __HAL_ADC_CFGR_AUTOWAIT                          ADC_CFGR_AUTOWAIT\r\n#define __HAL_ADC_CFGR_CONTINUOUS                        ADC_CFGR_CONTINUOUS\r\n#define __HAL_ADC_CFGR_OVERRUN                           ADC_CFGR_OVERRUN\r\n#define __HAL_ADC_CFGR_DMACONTREQ                        ADC_CFGR_DMACONTREQ\r\n#define __HAL_ADC_CFGR_EXTSEL                            ADC_CFGR_EXTSEL_SET\r\n#define __HAL_ADC_JSQR_JEXTSEL                           ADC_JSQR_JEXTSEL_SET\r\n#define __HAL_ADC_OFR_CHANNEL                            ADC_OFR_CHANNEL\r\n#define __HAL_ADC_DIFSEL_CHANNEL                         ADC_DIFSEL_CHANNEL\r\n#define __HAL_ADC_CALFACT_DIFF_SET                       ADC_CALFACT_DIFF_SET\r\n#define __HAL_ADC_CALFACT_DIFF_GET                       ADC_CALFACT_DIFF_GET\r\n#define __HAL_ADC_TRX_HIGHTHRESHOLD                      ADC_TRX_HIGHTHRESHOLD\r\n\r\n#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION                ADC_OFFSET_SHIFT_RESOLUTION\r\n#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION         ADC_AWD1THRESHOLD_SHIFT_RESOLUTION\r\n#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION        ADC_AWD23THRESHOLD_SHIFT_RESOLUTION\r\n#define __HAL_ADC_COMMON_REGISTER                        ADC_COMMON_REGISTER\r\n#define __HAL_ADC_COMMON_CCR_MULTI                       ADC_COMMON_CCR_MULTI\r\n#define __HAL_ADC_MULTIMODE_IS_ENABLED                   ADC_MULTIMODE_IS_ENABLE\r\n#define __ADC_MULTIMODE_IS_ENABLED                       ADC_MULTIMODE_IS_ENABLE\r\n#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER        ADC_NONMULTIMODE_OR_MULTIMODEMASTER\r\n#define __HAL_ADC_COMMON_ADC_OTHER                       ADC_COMMON_ADC_OTHER\r\n#define __HAL_ADC_MULTI_SLAVE                            ADC_MULTI_SLAVE\r\n\r\n#define __HAL_ADC_SQR1_L                                 ADC_SQR1_L_SHIFT\r\n#define __HAL_ADC_JSQR_JL                                ADC_JSQR_JL_SHIFT\r\n#define __HAL_ADC_JSQR_RK_JL                             ADC_JSQR_RK_JL\r\n#define __HAL_ADC_CR1_DISCONTINUOUS_NUM                  ADC_CR1_DISCONTINUOUS_NUM\r\n#define __HAL_ADC_CR1_SCAN                               ADC_CR1_SCAN_SET\r\n#define __HAL_ADC_CONVCYCLES_MAX_RANGE                   ADC_CONVCYCLES_MAX_RANGE\r\n#define __HAL_ADC_CLOCK_PRESCALER_RANGE                  ADC_CLOCK_PRESCALER_RANGE\r\n#define __HAL_ADC_GET_CLOCK_PRESCALER                    ADC_GET_CLOCK_PRESCALER\r\n\r\n#define __HAL_ADC_SQR1                                   ADC_SQR1\r\n#define __HAL_ADC_SMPR1                                  ADC_SMPR1\r\n#define __HAL_ADC_SMPR2                                  ADC_SMPR2\r\n#define __HAL_ADC_SQR3_RK                                ADC_SQR3_RK\r\n#define __HAL_ADC_SQR2_RK                                ADC_SQR2_RK\r\n#define __HAL_ADC_SQR1_RK                                ADC_SQR1_RK\r\n#define __HAL_ADC_CR2_CONTINUOUS                         ADC_CR2_CONTINUOUS\r\n#define __HAL_ADC_CR1_DISCONTINUOUS                      ADC_CR1_DISCONTINUOUS\r\n#define __HAL_ADC_CR1_SCANCONV                           ADC_CR1_SCANCONV\r\n#define __HAL_ADC_CR2_EOCSelection                       ADC_CR2_EOCSelection\r\n#define __HAL_ADC_CR2_DMAContReq                         ADC_CR2_DMAContReq\r\n#define __HAL_ADC_JSQR                                   ADC_JSQR\r\n\r\n#define __HAL_ADC_CHSELR_CHANNEL                         ADC_CHSELR_CHANNEL\r\n#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS               ADC_CFGR1_REG_DISCCONTINUOUS\r\n#define __HAL_ADC_CFGR1_AUTOOFF                          ADC_CFGR1_AUTOOFF\r\n#define __HAL_ADC_CFGR1_AUTOWAIT                         ADC_CFGR1_AUTOWAIT\r\n#define __HAL_ADC_CFGR1_CONTINUOUS                       ADC_CFGR1_CONTINUOUS\r\n#define __HAL_ADC_CFGR1_OVERRUN                          ADC_CFGR1_OVERRUN\r\n#define __HAL_ADC_CFGR1_SCANDIR                          ADC_CFGR1_SCANDIR\r\n#define __HAL_ADC_CFGR1_DMACONTREQ                       ADC_CFGR1_DMACONTREQ\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define __HAL_DHR12R1_ALIGNEMENT                        DAC_DHR12R1_ALIGNMENT\r\n#define __HAL_DHR12R2_ALIGNEMENT                        DAC_DHR12R2_ALIGNMENT\r\n#define __HAL_DHR12RD_ALIGNEMENT                        DAC_DHR12RD_ALIGNMENT\r\n#define IS_DAC_GENERATE_WAVE                            IS_DAC_WAVE\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1\r\n#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1\r\n#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2\r\n#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2\r\n#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3\r\n#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3\r\n#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4\r\n#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4\r\n#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5\r\n#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5\r\n#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6\r\n#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6\r\n#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7\r\n#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7\r\n#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8\r\n#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8\r\n\r\n#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9\r\n#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9\r\n#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10\r\n#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10\r\n#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11\r\n#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11\r\n#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12\r\n#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12\r\n#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13\r\n#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13\r\n#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14\r\n#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14\r\n#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2\r\n#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2\r\n\r\n\r\n#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15\r\n#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15\r\n#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16\r\n#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16\r\n#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17\r\n#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17\r\n#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC\r\n#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC\r\n#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG\r\n#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG\r\n#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG\r\n#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG\r\n#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT\r\n#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT\r\n#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT\r\n#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT\r\n#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT\r\n#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT\r\n#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1\r\n#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1\r\n#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1\r\n#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1\r\n#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2\r\n#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n#if defined(STM32F3)\r\n#define COMP_START                                       __HAL_COMP_ENABLE\r\n#define COMP_STOP                                        __HAL_COMP_DISABLE\r\n#define COMP_LOCK                                        __HAL_COMP_LOCK\r\n\r\n#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\r\n#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())\r\n#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())\r\n#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())\r\n#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())\r\n#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \\\r\n                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())\r\n#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \\\r\n                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())\r\n#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \\\r\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \\\r\n                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())\r\n#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \\\r\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \\\r\n                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())\r\n# endif\r\n# if defined(STM32F302xE) || defined(STM32F302xC)\r\n#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())\r\n#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())\r\n#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())\r\n#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())\r\n#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \\\r\n                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())\r\n#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \\\r\n                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())\r\n#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\\r\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \\\r\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \\\r\n                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())\r\n#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\\r\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \\\r\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \\\r\n                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())\r\n# endif\r\n# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)\r\n#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())\r\n#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())\r\n#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())\r\n#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())\r\n#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \\\r\n                                                          __HAL_COMP_COMP7_EXTI_ENABLE_IT())\r\n#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \\\r\n                                                          __HAL_COMP_COMP7_EXTI_DISABLE_IT())\r\n#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\\r\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \\\r\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \\\r\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \\\r\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \\\r\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \\\r\n                                                          __HAL_COMP_COMP7_EXTI_GET_FLAG())\r\n#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\\r\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \\\r\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \\\r\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \\\r\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \\\r\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \\\r\n                                                          __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())\r\n# endif\r\n# if defined(STM32F373xC) ||defined(STM32F378xx)\r\n#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())\r\n#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())\r\n#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())\r\n#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())\r\n#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\\r\n                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())\r\n#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\\r\n                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())\r\n#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\\r\n                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())\r\n#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\\r\n                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())\r\n# endif\r\n#else\r\n#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())\r\n#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())\r\n#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())\r\n#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())\r\n#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\\r\n                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())\r\n#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\\r\n                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())\r\n#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\\r\n                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())\r\n#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\\r\n                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())\r\n#endif\r\n\r\n#define __HAL_COMP_GET_EXTI_LINE  COMP_GET_EXTI_LINE\r\n\r\n#if defined(STM32L0) || defined(STM32L4)\r\n/* Note: On these STM32 families, the only argument of this macro             */\r\n/*       is COMP_FLAG_LOCK.                                                   */\r\n/*       This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle  */\r\n/*       argument.                                                            */\r\n#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__)  (__HAL_COMP_IS_LOCKED(__HANDLE__))\r\n#endif\r\n/**\r\n  * @}\r\n  */\r\n\r\n#if defined(STM32L0) || defined(STM32L4)\r\n/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define HAL_COMP_Start_IT       HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */\r\n#define HAL_COMP_Stop_IT        HAL_COMP_Stop  /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */\r\n/**\r\n  * @}\r\n  */\r\n#endif\r\n\r\n/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \\\r\n                          ((WAVE) == DAC_WAVE_NOISE)|| \\\r\n                          ((WAVE) == DAC_WAVE_TRIANGLE))\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define IS_WRPAREA          IS_OB_WRPAREA\r\n#define IS_TYPEPROGRAM      IS_FLASH_TYPEPROGRAM\r\n#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM\r\n#define IS_TYPEERASE        IS_FLASH_TYPEERASE\r\n#define IS_NBSECTORS        IS_FLASH_NBSECTORS\r\n#define IS_OB_WDG_SOURCE    IS_OB_IWDG_SOURCE\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define __HAL_I2C_RESET_CR2             I2C_RESET_CR2\r\n#define __HAL_I2C_GENERATE_START        I2C_GENERATE_START\r\n#if defined(STM32F1)\r\n#define __HAL_I2C_FREQ_RANGE            I2C_FREQRANGE\r\n#else\r\n#define __HAL_I2C_FREQ_RANGE            I2C_FREQ_RANGE\r\n#endif /* STM32F1 */\r\n#define __HAL_I2C_RISE_TIME             I2C_RISE_TIME\r\n#define __HAL_I2C_SPEED_STANDARD        I2C_SPEED_STANDARD\r\n#define __HAL_I2C_SPEED_FAST            I2C_SPEED_FAST\r\n#define __HAL_I2C_SPEED                 I2C_SPEED\r\n#define __HAL_I2C_7BIT_ADD_WRITE        I2C_7BIT_ADD_WRITE\r\n#define __HAL_I2C_7BIT_ADD_READ         I2C_7BIT_ADD_READ\r\n#define __HAL_I2C_10BIT_ADDRESS         I2C_10BIT_ADDRESS\r\n#define __HAL_I2C_10BIT_HEADER_WRITE    I2C_10BIT_HEADER_WRITE\r\n#define __HAL_I2C_10BIT_HEADER_READ     I2C_10BIT_HEADER_READ\r\n#define __HAL_I2C_MEM_ADD_MSB           I2C_MEM_ADD_MSB\r\n#define __HAL_I2C_MEM_ADD_LSB           I2C_MEM_ADD_LSB\r\n#define __HAL_I2C_FREQRANGE             I2C_FREQRANGE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define IS_I2S_INSTANCE                 IS_I2S_ALL_INSTANCE\r\n#define IS_I2S_INSTANCE_EXT             IS_I2S_ALL_INSTANCE_EXT\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define __IRDA_DISABLE                  __HAL_IRDA_DISABLE\r\n#define __IRDA_ENABLE                   __HAL_IRDA_ENABLE\r\n\r\n#define __HAL_IRDA_GETCLOCKSOURCE       IRDA_GETCLOCKSOURCE\r\n#define __HAL_IRDA_MASK_COMPUTATION     IRDA_MASK_COMPUTATION\r\n#define __IRDA_GETCLOCKSOURCE           IRDA_GETCLOCKSOURCE\r\n#define __IRDA_MASK_COMPUTATION         IRDA_MASK_COMPUTATION\r\n\r\n#define IS_IRDA_ONEBIT_SAMPLE           IS_IRDA_ONE_BIT_SAMPLE\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define __HAL_IWDG_ENABLE_WRITE_ACCESS  IWDG_ENABLE_WRITE_ACCESS\r\n#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define __HAL_LPTIM_ENABLE_INTERRUPT    __HAL_LPTIM_ENABLE_IT\r\n#define __HAL_LPTIM_DISABLE_INTERRUPT   __HAL_LPTIM_DISABLE_IT\r\n#define __HAL_LPTIM_GET_ITSTATUS        __HAL_LPTIM_GET_IT_SOURCE\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define __OPAMP_CSR_OPAXPD                OPAMP_CSR_OPAXPD\r\n#define __OPAMP_CSR_S3SELX                OPAMP_CSR_S3SELX\r\n#define __OPAMP_CSR_S4SELX                OPAMP_CSR_S4SELX\r\n#define __OPAMP_CSR_S5SELX                OPAMP_CSR_S5SELX\r\n#define __OPAMP_CSR_S6SELX                OPAMP_CSR_S6SELX\r\n#define __OPAMP_CSR_OPAXCAL_L             OPAMP_CSR_OPAXCAL_L\r\n#define __OPAMP_CSR_OPAXCAL_H             OPAMP_CSR_OPAXCAL_H\r\n#define __OPAMP_CSR_OPAXLPM               OPAMP_CSR_OPAXLPM\r\n#define __OPAMP_CSR_ALL_SWITCHES          OPAMP_CSR_ALL_SWITCHES\r\n#define __OPAMP_CSR_ANAWSELX              OPAMP_CSR_ANAWSELX\r\n#define __OPAMP_CSR_OPAXCALOUT            OPAMP_CSR_OPAXCALOUT\r\n#define __OPAMP_OFFSET_TRIM_BITSPOSITION  OPAMP_OFFSET_TRIM_BITSPOSITION\r\n#define __OPAMP_OFFSET_TRIM_SET           OPAMP_OFFSET_TRIM_SET\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define __HAL_PVD_EVENT_DISABLE                                  __HAL_PWR_PVD_EXTI_DISABLE_EVENT\r\n#define __HAL_PVD_EVENT_ENABLE                                   __HAL_PWR_PVD_EXTI_ENABLE_EVENT\r\n#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE\r\n#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE\r\n#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE\r\n#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE\r\n#define __HAL_PVM_EVENT_DISABLE                                  __HAL_PWR_PVM_EVENT_DISABLE\r\n#define __HAL_PVM_EVENT_ENABLE                                   __HAL_PWR_PVM_EVENT_ENABLE\r\n#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE\r\n#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE\r\n#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE\r\n#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE\r\n#define __HAL_PWR_INTERNALWAKEUP_DISABLE                         HAL_PWREx_DisableInternalWakeUpLine\r\n#define __HAL_PWR_INTERNALWAKEUP_ENABLE                          HAL_PWREx_EnableInternalWakeUpLine\r\n#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE                    HAL_PWREx_DisablePullUpPullDownConfig\r\n#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE                     HAL_PWREx_EnablePullUpPullDownConfig\r\n#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER()                  do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)\r\n#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE                         __HAL_PWR_PVD_EXTI_DISABLE_EVENT\r\n#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE                          __HAL_PWR_PVD_EXTI_ENABLE_EVENT\r\n#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE                __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE\r\n#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE                 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE\r\n#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE                 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE\r\n#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE                  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE\r\n#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER              __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE\r\n#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER               __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE\r\n#define __HAL_PWR_PVM_DISABLE()                                  do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)\r\n#define __HAL_PWR_PVM_ENABLE()                                   do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)\r\n#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE                  HAL_PWREx_DisableSRAM2ContentRetention\r\n#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE                   HAL_PWREx_EnableSRAM2ContentRetention\r\n#define __HAL_PWR_VDDIO2_DISABLE                                 HAL_PWREx_DisableVddIO2\r\n#define __HAL_PWR_VDDIO2_ENABLE                                  HAL_PWREx_EnableVddIO2\r\n#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER                 __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE\r\n#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER           __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE\r\n#define __HAL_PWR_VDDUSB_DISABLE                                 HAL_PWREx_DisableVddUSB\r\n#define __HAL_PWR_VDDUSB_ENABLE                                  HAL_PWREx_EnableVddUSB\r\n\r\n#if defined (STM32F4)\r\n#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD)         __HAL_PWR_PVD_EXTI_ENABLE_IT()\r\n#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_DISABLE_IT()\r\n#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD)          __HAL_PWR_PVD_EXTI_GET_FLAG()\r\n#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_CLEAR_FLAG()\r\n#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD)     __HAL_PWR_PVD_EXTI_GENERATE_SWIT()\r\n#else\r\n#define __HAL_PVD_EXTI_CLEAR_FLAG                                __HAL_PWR_PVD_EXTI_CLEAR_FLAG\r\n#define __HAL_PVD_EXTI_DISABLE_IT                                __HAL_PWR_PVD_EXTI_DISABLE_IT\r\n#define __HAL_PVD_EXTI_ENABLE_IT                                 __HAL_PWR_PVD_EXTI_ENABLE_IT\r\n#define __HAL_PVD_EXTI_GENERATE_SWIT                             __HAL_PWR_PVD_EXTI_GENERATE_SWIT\r\n#define __HAL_PVD_EXTI_GET_FLAG                                  __HAL_PWR_PVD_EXTI_GET_FLAG\r\n#endif /* STM32F4 */\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define RCC_StopWakeUpClock_MSI     RCC_STOP_WAKEUPCLOCK_MSI\r\n#define RCC_StopWakeUpClock_HSI     RCC_STOP_WAKEUPCLOCK_HSI\r\n\r\n#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback\r\n#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())\r\n\r\n#define __ADC_CLK_DISABLE          __HAL_RCC_ADC_CLK_DISABLE\r\n#define __ADC_CLK_ENABLE           __HAL_RCC_ADC_CLK_ENABLE\r\n#define __ADC_CLK_SLEEP_DISABLE    __HAL_RCC_ADC_CLK_SLEEP_DISABLE\r\n#define __ADC_CLK_SLEEP_ENABLE     __HAL_RCC_ADC_CLK_SLEEP_ENABLE\r\n#define __ADC_FORCE_RESET          __HAL_RCC_ADC_FORCE_RESET\r\n#define __ADC_RELEASE_RESET        __HAL_RCC_ADC_RELEASE_RESET\r\n#define __ADC1_CLK_DISABLE         __HAL_RCC_ADC1_CLK_DISABLE\r\n#define __ADC1_CLK_ENABLE          __HAL_RCC_ADC1_CLK_ENABLE\r\n#define __ADC1_FORCE_RESET         __HAL_RCC_ADC1_FORCE_RESET\r\n#define __ADC1_RELEASE_RESET       __HAL_RCC_ADC1_RELEASE_RESET\r\n#define __ADC1_CLK_SLEEP_ENABLE    __HAL_RCC_ADC1_CLK_SLEEP_ENABLE\r\n#define __ADC1_CLK_SLEEP_DISABLE   __HAL_RCC_ADC1_CLK_SLEEP_DISABLE\r\n#define __ADC2_CLK_DISABLE         __HAL_RCC_ADC2_CLK_DISABLE\r\n#define __ADC2_CLK_ENABLE          __HAL_RCC_ADC2_CLK_ENABLE\r\n#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET\r\n#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET\r\n#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE\r\n#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE\r\n#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET\r\n#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET\r\n#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE\r\n#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE\r\n#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE\r\n#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE\r\n#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET\r\n#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET\r\n#define __CRYP_CLK_SLEEP_ENABLE      __HAL_RCC_CRYP_CLK_SLEEP_ENABLE\r\n#define __CRYP_CLK_SLEEP_DISABLE  __HAL_RCC_CRYP_CLK_SLEEP_DISABLE\r\n#define __CRYP_CLK_ENABLE  __HAL_RCC_CRYP_CLK_ENABLE\r\n#define __CRYP_CLK_DISABLE  __HAL_RCC_CRYP_CLK_DISABLE\r\n#define __CRYP_FORCE_RESET       __HAL_RCC_CRYP_FORCE_RESET\r\n#define __CRYP_RELEASE_RESET  __HAL_RCC_CRYP_RELEASE_RESET\r\n#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE\r\n#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE\r\n#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET\r\n#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET\r\n#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET\r\n#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET\r\n#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET\r\n#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET\r\n#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET\r\n#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET\r\n#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET\r\n#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET\r\n#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET\r\n#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET\r\n#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET\r\n#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET\r\n#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE\r\n#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE\r\n#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET\r\n#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET\r\n#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE\r\n#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE\r\n#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE\r\n#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE\r\n#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET\r\n#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET\r\n#define __CAN_CLK_DISABLE         __HAL_RCC_CAN1_CLK_DISABLE\r\n#define __CAN_CLK_ENABLE          __HAL_RCC_CAN1_CLK_ENABLE\r\n#define __CAN_FORCE_RESET         __HAL_RCC_CAN1_FORCE_RESET\r\n#define __CAN_RELEASE_RESET       __HAL_RCC_CAN1_RELEASE_RESET\r\n#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE\r\n#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE\r\n#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET\r\n#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET\r\n#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE\r\n#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE\r\n#define __COMP_CLK_DISABLE        __HAL_RCC_COMP_CLK_DISABLE\r\n#define __COMP_CLK_ENABLE         __HAL_RCC_COMP_CLK_ENABLE\r\n#define __COMP_FORCE_RESET        __HAL_RCC_COMP_FORCE_RESET\r\n#define __COMP_RELEASE_RESET      __HAL_RCC_COMP_RELEASE_RESET\r\n#define __COMP_CLK_SLEEP_ENABLE   __HAL_RCC_COMP_CLK_SLEEP_ENABLE\r\n#define __COMP_CLK_SLEEP_DISABLE  __HAL_RCC_COMP_CLK_SLEEP_DISABLE\r\n#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET\r\n#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET\r\n#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE\r\n#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE\r\n#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE\r\n#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE\r\n#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET\r\n#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET\r\n#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE\r\n#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE\r\n#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET\r\n#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET\r\n#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE\r\n#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE\r\n#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE\r\n#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE\r\n#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET\r\n#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET\r\n#define __DBGMCU_CLK_ENABLE     __HAL_RCC_DBGMCU_CLK_ENABLE\r\n#define __DBGMCU_CLK_DISABLE     __HAL_RCC_DBGMCU_CLK_DISABLE\r\n#define __DBGMCU_FORCE_RESET    __HAL_RCC_DBGMCU_FORCE_RESET\r\n#define __DBGMCU_RELEASE_RESET  __HAL_RCC_DBGMCU_RELEASE_RESET\r\n#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE\r\n#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE\r\n#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE\r\n#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE\r\n#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET\r\n#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET\r\n#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE\r\n#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE\r\n#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE\r\n#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE\r\n#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET\r\n#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET\r\n#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE\r\n#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE\r\n#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE\r\n#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE\r\n#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET\r\n#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET\r\n#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE\r\n#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE\r\n#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET\r\n#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET\r\n#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE\r\n#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE\r\n#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE\r\n#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE\r\n#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE\r\n#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE\r\n#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE\r\n#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE\r\n#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE\r\n#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE\r\n#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET\r\n#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET\r\n#define __FLITF_CLK_DISABLE       __HAL_RCC_FLITF_CLK_DISABLE\r\n#define __FLITF_CLK_ENABLE        __HAL_RCC_FLITF_CLK_ENABLE\r\n#define __FLITF_FORCE_RESET       __HAL_RCC_FLITF_FORCE_RESET\r\n#define __FLITF_RELEASE_RESET     __HAL_RCC_FLITF_RELEASE_RESET\r\n#define __FLITF_CLK_SLEEP_ENABLE  __HAL_RCC_FLITF_CLK_SLEEP_ENABLE\r\n#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE\r\n#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE\r\n#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE\r\n#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE\r\n#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE\r\n#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET\r\n#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET\r\n#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE\r\n#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE\r\n#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE\r\n#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE\r\n#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE\r\n#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE\r\n#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET\r\n#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET\r\n#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE\r\n#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE\r\n#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE\r\n#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE\r\n#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET\r\n#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET\r\n#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE\r\n#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE\r\n#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE\r\n#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE\r\n#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET\r\n#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET\r\n#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE\r\n#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE\r\n#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE\r\n#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE\r\n#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET\r\n#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET\r\n#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE\r\n#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE\r\n#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE\r\n#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE\r\n#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET\r\n#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET\r\n#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE\r\n#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE\r\n#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE\r\n#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE\r\n#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET\r\n#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET\r\n#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE\r\n#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE\r\n#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE\r\n#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE\r\n#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET\r\n#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET\r\n#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE\r\n#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE\r\n#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE\r\n#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE\r\n#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET\r\n#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET\r\n#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE\r\n#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE\r\n#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE\r\n#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE\r\n#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET\r\n#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET\r\n#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE\r\n#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE\r\n#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE\r\n#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE\r\n#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET\r\n#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET\r\n#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE\r\n#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE\r\n#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE\r\n#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE\r\n#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET\r\n#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET\r\n#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE\r\n#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE\r\n#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE\r\n#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE\r\n#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET\r\n#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET\r\n#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE\r\n#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE\r\n#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE\r\n#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE\r\n#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET\r\n#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET\r\n#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE\r\n#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE\r\n#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE\r\n#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE\r\n#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET\r\n#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET\r\n#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE\r\n#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE\r\n#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE\r\n#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE\r\n#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET\r\n#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET\r\n#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE\r\n#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE\r\n#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE\r\n#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE\r\n#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET\r\n#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET\r\n#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE\r\n#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE\r\n#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE\r\n#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE\r\n#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET\r\n#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET\r\n#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE\r\n#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE\r\n#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE\r\n#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE\r\n#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET\r\n#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET\r\n#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE\r\n#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE\r\n#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE\r\n#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE\r\n#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET\r\n#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET\r\n\r\n#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE\r\n#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE\r\n#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE\r\n#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE\r\n#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET\r\n#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET\r\n#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE\r\n#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE\r\n#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE\r\n#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE\r\n#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET\r\n#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET\r\n#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE\r\n#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE\r\n#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE\r\n#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE\r\n#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET\r\n#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET\r\n#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE\r\n#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE\r\n#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE\r\n#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE\r\n#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE\r\n#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE\r\n#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET\r\n#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET\r\n#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE\r\n#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE\r\n#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE\r\n#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE\r\n#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET\r\n#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET\r\n#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE\r\n#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE\r\n#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE\r\n#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE\r\n#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET\r\n#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET\r\n#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE\r\n#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE\r\n#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE\r\n#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE\r\n#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET\r\n#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET\r\n#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE\r\n#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE\r\n#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE\r\n#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE\r\n#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE\r\n#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE\r\n#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE\r\n#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE\r\n#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE\r\n#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE\r\n#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET\r\n#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET\r\n#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE\r\n#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE\r\n#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE\r\n#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE\r\n#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET\r\n#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET\r\n#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE\r\n#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE\r\n#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE\r\n#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE\r\n#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET\r\n#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET\r\n#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE\r\n#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE\r\n#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET\r\n#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET\r\n#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE\r\n#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE\r\n#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET\r\n#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET\r\n#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE\r\n#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE\r\n#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET\r\n#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET\r\n#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE\r\n#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE\r\n#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET\r\n#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET\r\n#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE\r\n#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE\r\n#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET\r\n#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET\r\n#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE\r\n#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE\r\n#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE\r\n#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE\r\n#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET\r\n#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET\r\n#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE\r\n#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE\r\n#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE\r\n#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE\r\n#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET\r\n#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET\r\n#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE\r\n#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE\r\n#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE\r\n#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE\r\n#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET\r\n#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET\r\n#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE\r\n#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE\r\n#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE\r\n#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE\r\n#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET\r\n#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET\r\n#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE\r\n#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE\r\n#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE\r\n#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE\r\n#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET\r\n#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET\r\n#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE\r\n#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE\r\n#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE\r\n#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE\r\n#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET\r\n#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET\r\n#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE\r\n#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE\r\n#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE\r\n#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE\r\n#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET\r\n#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET\r\n#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE\r\n#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE\r\n#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE\r\n#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE\r\n#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET\r\n#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET\r\n#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE\r\n#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE\r\n#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE\r\n#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE\r\n#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET\r\n#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET\r\n#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE\r\n#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE\r\n#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE\r\n#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE\r\n#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET\r\n#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET\r\n#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE\r\n#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE\r\n#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET\r\n#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET\r\n#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE\r\n#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE\r\n#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE\r\n#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE\r\n#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET\r\n#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET\r\n#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE\r\n#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE\r\n#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE\r\n#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE\r\n#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET\r\n#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET\r\n#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE\r\n#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE\r\n#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE\r\n#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE\r\n#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET\r\n#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET\r\n#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE\r\n#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE\r\n#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE\r\n#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE\r\n#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET\r\n#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET\r\n#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE\r\n#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE\r\n#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE\r\n#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE\r\n#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET\r\n#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET\r\n#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE\r\n#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE\r\n#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE\r\n#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE\r\n#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET\r\n#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET\r\n#define __USART4_CLK_DISABLE        __HAL_RCC_UART4_CLK_DISABLE\r\n#define __USART4_CLK_ENABLE         __HAL_RCC_UART4_CLK_ENABLE\r\n#define __USART4_CLK_SLEEP_ENABLE   __HAL_RCC_UART4_CLK_SLEEP_ENABLE\r\n#define __USART4_CLK_SLEEP_DISABLE  __HAL_RCC_UART4_CLK_SLEEP_DISABLE\r\n#define __USART4_FORCE_RESET        __HAL_RCC_UART4_FORCE_RESET\r\n#define __USART4_RELEASE_RESET      __HAL_RCC_UART4_RELEASE_RESET\r\n#define __USART5_CLK_DISABLE        __HAL_RCC_UART5_CLK_DISABLE\r\n#define __USART5_CLK_ENABLE         __HAL_RCC_UART5_CLK_ENABLE\r\n#define __USART5_CLK_SLEEP_ENABLE   __HAL_RCC_UART5_CLK_SLEEP_ENABLE\r\n#define __USART5_CLK_SLEEP_DISABLE  __HAL_RCC_UART5_CLK_SLEEP_DISABLE\r\n#define __USART5_FORCE_RESET        __HAL_RCC_UART5_FORCE_RESET\r\n#define __USART5_RELEASE_RESET      __HAL_RCC_UART5_RELEASE_RESET\r\n#define __USART7_CLK_DISABLE        __HAL_RCC_UART7_CLK_DISABLE\r\n#define __USART7_CLK_ENABLE         __HAL_RCC_UART7_CLK_ENABLE\r\n#define __USART7_FORCE_RESET        __HAL_RCC_UART7_FORCE_RESET\r\n#define __USART7_RELEASE_RESET      __HAL_RCC_UART7_RELEASE_RESET\r\n#define __USART8_CLK_DISABLE        __HAL_RCC_UART8_CLK_DISABLE\r\n#define __USART8_CLK_ENABLE         __HAL_RCC_UART8_CLK_ENABLE\r\n#define __USART8_FORCE_RESET        __HAL_RCC_UART8_FORCE_RESET\r\n#define __USART8_RELEASE_RESET      __HAL_RCC_UART8_RELEASE_RESET\r\n#define __USB_CLK_DISABLE         __HAL_RCC_USB_CLK_DISABLE\r\n#define __USB_CLK_ENABLE          __HAL_RCC_USB_CLK_ENABLE\r\n#define __USB_FORCE_RESET         __HAL_RCC_USB_FORCE_RESET\r\n#define __USB_CLK_SLEEP_ENABLE    __HAL_RCC_USB_CLK_SLEEP_ENABLE\r\n#define __USB_CLK_SLEEP_DISABLE   __HAL_RCC_USB_CLK_SLEEP_DISABLE\r\n#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE\r\n#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE\r\n#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET\r\n#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE\r\n#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE\r\n#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE\r\n#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE\r\n#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET\r\n#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET\r\n#define __TIM21_CLK_ENABLE   __HAL_RCC_TIM21_CLK_ENABLE\r\n#define __TIM21_CLK_DISABLE   __HAL_RCC_TIM21_CLK_DISABLE\r\n#define __TIM21_FORCE_RESET   __HAL_RCC_TIM21_FORCE_RESET\r\n#define __TIM21_RELEASE_RESET  __HAL_RCC_TIM21_RELEASE_RESET\r\n#define __TIM21_CLK_SLEEP_ENABLE   __HAL_RCC_TIM21_CLK_SLEEP_ENABLE\r\n#define __TIM21_CLK_SLEEP_DISABLE   __HAL_RCC_TIM21_CLK_SLEEP_DISABLE\r\n#define __TIM22_CLK_ENABLE   __HAL_RCC_TIM22_CLK_ENABLE\r\n#define __TIM22_CLK_DISABLE   __HAL_RCC_TIM22_CLK_DISABLE\r\n#define __TIM22_FORCE_RESET   __HAL_RCC_TIM22_FORCE_RESET\r\n#define __TIM22_RELEASE_RESET  __HAL_RCC_TIM22_RELEASE_RESET\r\n#define __TIM22_CLK_SLEEP_ENABLE   __HAL_RCC_TIM22_CLK_SLEEP_ENABLE\r\n#define __TIM22_CLK_SLEEP_DISABLE   __HAL_RCC_TIM22_CLK_SLEEP_DISABLE\r\n#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE\r\n#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE\r\n#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE\r\n#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE\r\n#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET\r\n#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET\r\n#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE\r\n#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE\r\n\r\n#define __USB_OTG_FS_FORCE_RESET  __HAL_RCC_USB_OTG_FS_FORCE_RESET\r\n#define __USB_OTG_FS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET\r\n#define __USB_OTG_FS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE\r\n#define __USB_OTG_FS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE\r\n#define __USB_OTG_HS_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_DISABLE\r\n#define __USB_OTG_HS_CLK_ENABLE          __HAL_RCC_USB_OTG_HS_CLK_ENABLE\r\n#define __USB_OTG_HS_ULPI_CLK_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE\r\n#define __USB_OTG_HS_ULPI_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE\r\n#define __TIM9_CLK_SLEEP_ENABLE          __HAL_RCC_TIM9_CLK_SLEEP_ENABLE\r\n#define __TIM9_CLK_SLEEP_DISABLE  __HAL_RCC_TIM9_CLK_SLEEP_DISABLE\r\n#define __TIM10_CLK_SLEEP_ENABLE  __HAL_RCC_TIM10_CLK_SLEEP_ENABLE\r\n#define __TIM10_CLK_SLEEP_DISABLE  __HAL_RCC_TIM10_CLK_SLEEP_DISABLE\r\n#define __TIM11_CLK_SLEEP_ENABLE  __HAL_RCC_TIM11_CLK_SLEEP_ENABLE\r\n#define __TIM11_CLK_SLEEP_DISABLE  __HAL_RCC_TIM11_CLK_SLEEP_DISABLE\r\n#define __ETHMACPTP_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE\r\n#define __ETHMACPTP_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE\r\n#define __ETHMACPTP_CLK_ENABLE          __HAL_RCC_ETHMACPTP_CLK_ENABLE\r\n#define __ETHMACPTP_CLK_DISABLE          __HAL_RCC_ETHMACPTP_CLK_DISABLE\r\n#define __HASH_CLK_ENABLE          __HAL_RCC_HASH_CLK_ENABLE\r\n#define __HASH_FORCE_RESET          __HAL_RCC_HASH_FORCE_RESET\r\n#define __HASH_RELEASE_RESET          __HAL_RCC_HASH_RELEASE_RESET\r\n#define __HASH_CLK_SLEEP_ENABLE          __HAL_RCC_HASH_CLK_SLEEP_ENABLE\r\n#define __HASH_CLK_SLEEP_DISABLE  __HAL_RCC_HASH_CLK_SLEEP_DISABLE\r\n#define __HASH_CLK_DISABLE            __HAL_RCC_HASH_CLK_DISABLE\r\n#define __SPI5_CLK_ENABLE          __HAL_RCC_SPI5_CLK_ENABLE\r\n#define __SPI5_CLK_DISABLE              __HAL_RCC_SPI5_CLK_DISABLE\r\n#define __SPI5_FORCE_RESET          __HAL_RCC_SPI5_FORCE_RESET\r\n#define __SPI5_RELEASE_RESET          __HAL_RCC_SPI5_RELEASE_RESET\r\n#define __SPI5_CLK_SLEEP_ENABLE          __HAL_RCC_SPI5_CLK_SLEEP_ENABLE\r\n#define __SPI5_CLK_SLEEP_DISABLE  __HAL_RCC_SPI5_CLK_SLEEP_DISABLE\r\n#define __SPI6_CLK_ENABLE          __HAL_RCC_SPI6_CLK_ENABLE\r\n#define __SPI6_CLK_DISABLE          __HAL_RCC_SPI6_CLK_DISABLE\r\n#define __SPI6_FORCE_RESET          __HAL_RCC_SPI6_FORCE_RESET\r\n#define __SPI6_RELEASE_RESET         __HAL_RCC_SPI6_RELEASE_RESET\r\n#define __SPI6_CLK_SLEEP_ENABLE          __HAL_RCC_SPI6_CLK_SLEEP_ENABLE\r\n#define __SPI6_CLK_SLEEP_DISABLE  __HAL_RCC_SPI6_CLK_SLEEP_DISABLE\r\n#define __LTDC_CLK_ENABLE          __HAL_RCC_LTDC_CLK_ENABLE\r\n#define __LTDC_CLK_DISABLE          __HAL_RCC_LTDC_CLK_DISABLE\r\n#define __LTDC_FORCE_RESET          __HAL_RCC_LTDC_FORCE_RESET\r\n#define __LTDC_RELEASE_RESET          __HAL_RCC_LTDC_RELEASE_RESET\r\n#define __LTDC_CLK_SLEEP_ENABLE          __HAL_RCC_LTDC_CLK_SLEEP_ENABLE\r\n#define __ETHMAC_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE\r\n#define __ETHMAC_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE\r\n#define __ETHMACTX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE\r\n#define __ETHMACTX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE\r\n#define __ETHMACRX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE\r\n#define __ETHMACRX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE\r\n#define __TIM12_CLK_SLEEP_ENABLE  __HAL_RCC_TIM12_CLK_SLEEP_ENABLE\r\n#define __TIM12_CLK_SLEEP_DISABLE  __HAL_RCC_TIM12_CLK_SLEEP_DISABLE\r\n#define __TIM13_CLK_SLEEP_ENABLE  __HAL_RCC_TIM13_CLK_SLEEP_ENABLE\r\n#define __TIM13_CLK_SLEEP_DISABLE  __HAL_RCC_TIM13_CLK_SLEEP_DISABLE\r\n#define __TIM14_CLK_SLEEP_ENABLE  __HAL_RCC_TIM14_CLK_SLEEP_ENABLE\r\n#define __TIM14_CLK_SLEEP_DISABLE  __HAL_RCC_TIM14_CLK_SLEEP_DISABLE\r\n#define __BKPSRAM_CLK_ENABLE          __HAL_RCC_BKPSRAM_CLK_ENABLE\r\n#define __BKPSRAM_CLK_DISABLE          __HAL_RCC_BKPSRAM_CLK_DISABLE\r\n#define __BKPSRAM_CLK_SLEEP_ENABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE\r\n#define __BKPSRAM_CLK_SLEEP_DISABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE\r\n#define __CCMDATARAMEN_CLK_ENABLE  __HAL_RCC_CCMDATARAMEN_CLK_ENABLE\r\n#define __CCMDATARAMEN_CLK_DISABLE  __HAL_RCC_CCMDATARAMEN_CLK_DISABLE\r\n#define __USART6_CLK_ENABLE          __HAL_RCC_USART6_CLK_ENABLE\r\n#define __USART6_CLK_DISABLE          __HAL_RCC_USART6_CLK_DISABLE\r\n#define __USART6_FORCE_RESET        __HAL_RCC_USART6_FORCE_RESET\r\n#define __USART6_RELEASE_RESET        __HAL_RCC_USART6_RELEASE_RESET\r\n#define __USART6_CLK_SLEEP_ENABLE  __HAL_RCC_USART6_CLK_SLEEP_ENABLE\r\n#define __USART6_CLK_SLEEP_DISABLE  __HAL_RCC_USART6_CLK_SLEEP_DISABLE\r\n#define __SPI4_CLK_ENABLE          __HAL_RCC_SPI4_CLK_ENABLE\r\n#define __SPI4_CLK_DISABLE          __HAL_RCC_SPI4_CLK_DISABLE\r\n#define __SPI4_FORCE_RESET          __HAL_RCC_SPI4_FORCE_RESET\r\n#define __SPI4_RELEASE_RESET        __HAL_RCC_SPI4_RELEASE_RESET\r\n#define __SPI4_CLK_SLEEP_ENABLE   __HAL_RCC_SPI4_CLK_SLEEP_ENABLE\r\n#define __SPI4_CLK_SLEEP_DISABLE  __HAL_RCC_SPI4_CLK_SLEEP_DISABLE\r\n#define __GPIOI_CLK_ENABLE          __HAL_RCC_GPIOI_CLK_ENABLE\r\n#define __GPIOI_CLK_DISABLE          __HAL_RCC_GPIOI_CLK_DISABLE\r\n#define __GPIOI_FORCE_RESET          __HAL_RCC_GPIOI_FORCE_RESET\r\n#define __GPIOI_RELEASE_RESET          __HAL_RCC_GPIOI_RELEASE_RESET\r\n#define __GPIOI_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE\r\n#define __GPIOI_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE\r\n#define __GPIOJ_CLK_ENABLE          __HAL_RCC_GPIOJ_CLK_ENABLE\r\n#define __GPIOJ_CLK_DISABLE          __HAL_RCC_GPIOJ_CLK_DISABLE\r\n#define __GPIOJ_FORCE_RESET         __HAL_RCC_GPIOJ_FORCE_RESET\r\n#define __GPIOJ_RELEASE_RESET          __HAL_RCC_GPIOJ_RELEASE_RESET\r\n#define __GPIOJ_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE\r\n#define __GPIOJ_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE\r\n#define __GPIOK_CLK_ENABLE          __HAL_RCC_GPIOK_CLK_ENABLE\r\n#define __GPIOK_CLK_DISABLE          __HAL_RCC_GPIOK_CLK_DISABLE\r\n#define __GPIOK_RELEASE_RESET          __HAL_RCC_GPIOK_RELEASE_RESET\r\n#define __GPIOK_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE\r\n#define __GPIOK_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE\r\n#define __ETH_CLK_ENABLE          __HAL_RCC_ETH_CLK_ENABLE\r\n#define __ETH_CLK_DISABLE          __HAL_RCC_ETH_CLK_DISABLE\r\n#define __DCMI_CLK_ENABLE          __HAL_RCC_DCMI_CLK_ENABLE\r\n#define __DCMI_CLK_DISABLE          __HAL_RCC_DCMI_CLK_DISABLE\r\n#define __DCMI_FORCE_RESET          __HAL_RCC_DCMI_FORCE_RESET\r\n#define __DCMI_RELEASE_RESET          __HAL_RCC_DCMI_RELEASE_RESET\r\n#define __DCMI_CLK_SLEEP_ENABLE   __HAL_RCC_DCMI_CLK_SLEEP_ENABLE\r\n#define __DCMI_CLK_SLEEP_DISABLE  __HAL_RCC_DCMI_CLK_SLEEP_DISABLE\r\n#define __UART7_CLK_ENABLE          __HAL_RCC_UART7_CLK_ENABLE\r\n#define __UART7_CLK_DISABLE          __HAL_RCC_UART7_CLK_DISABLE\r\n#define __UART7_RELEASE_RESET       __HAL_RCC_UART7_RELEASE_RESET\r\n#define __UART7_FORCE_RESET       __HAL_RCC_UART7_FORCE_RESET\r\n#define __UART7_CLK_SLEEP_ENABLE  __HAL_RCC_UART7_CLK_SLEEP_ENABLE\r\n#define __UART7_CLK_SLEEP_DISABLE  __HAL_RCC_UART7_CLK_SLEEP_DISABLE\r\n#define __UART8_CLK_ENABLE          __HAL_RCC_UART8_CLK_ENABLE\r\n#define __UART8_CLK_DISABLE          __HAL_RCC_UART8_CLK_DISABLE\r\n#define __UART8_FORCE_RESET          __HAL_RCC_UART8_FORCE_RESET\r\n#define __UART8_RELEASE_RESET          __HAL_RCC_UART8_RELEASE_RESET\r\n#define __UART8_CLK_SLEEP_ENABLE  __HAL_RCC_UART8_CLK_SLEEP_ENABLE\r\n#define __UART8_CLK_SLEEP_DISABLE  __HAL_RCC_UART8_CLK_SLEEP_DISABLE\r\n#define __OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE\r\n#define __OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE\r\n#define __OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET\r\n#define __OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET\r\n#define __OTGHSULPI_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE\r\n#define __OTGHSULPI_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE\r\n#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE\r\n#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE\r\n#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED\r\n#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED\r\n#define __HAL_RCC_OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET\r\n#define __HAL_RCC_OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET\r\n#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE      __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE\r\n#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE     __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE\r\n#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED  __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED\r\n#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED\r\n#define __SRAM3_CLK_SLEEP_ENABLE       __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE\r\n#define __CAN2_CLK_SLEEP_ENABLE        __HAL_RCC_CAN2_CLK_SLEEP_ENABLE\r\n#define __CAN2_CLK_SLEEP_DISABLE       __HAL_RCC_CAN2_CLK_SLEEP_DISABLE\r\n#define __DAC_CLK_SLEEP_ENABLE         __HAL_RCC_DAC_CLK_SLEEP_ENABLE\r\n#define __DAC_CLK_SLEEP_DISABLE        __HAL_RCC_DAC_CLK_SLEEP_DISABLE\r\n#define __ADC2_CLK_SLEEP_ENABLE        __HAL_RCC_ADC2_CLK_SLEEP_ENABLE\r\n#define __ADC2_CLK_SLEEP_DISABLE       __HAL_RCC_ADC2_CLK_SLEEP_DISABLE\r\n#define __ADC3_CLK_SLEEP_ENABLE        __HAL_RCC_ADC3_CLK_SLEEP_ENABLE\r\n#define __ADC3_CLK_SLEEP_DISABLE       __HAL_RCC_ADC3_CLK_SLEEP_DISABLE\r\n#define __FSMC_FORCE_RESET             __HAL_RCC_FSMC_FORCE_RESET\r\n#define __FSMC_RELEASE_RESET           __HAL_RCC_FSMC_RELEASE_RESET\r\n#define __FSMC_CLK_SLEEP_ENABLE        __HAL_RCC_FSMC_CLK_SLEEP_ENABLE\r\n#define __FSMC_CLK_SLEEP_DISABLE       __HAL_RCC_FSMC_CLK_SLEEP_DISABLE\r\n#define __SDIO_FORCE_RESET             __HAL_RCC_SDIO_FORCE_RESET\r\n#define __SDIO_RELEASE_RESET           __HAL_RCC_SDIO_RELEASE_RESET\r\n#define __SDIO_CLK_SLEEP_DISABLE       __HAL_RCC_SDIO_CLK_SLEEP_DISABLE\r\n#define __SDIO_CLK_SLEEP_ENABLE        __HAL_RCC_SDIO_CLK_SLEEP_ENABLE\r\n#define __DMA2D_CLK_ENABLE             __HAL_RCC_DMA2D_CLK_ENABLE\r\n#define __DMA2D_CLK_DISABLE            __HAL_RCC_DMA2D_CLK_DISABLE\r\n#define __DMA2D_FORCE_RESET            __HAL_RCC_DMA2D_FORCE_RESET\r\n#define __DMA2D_RELEASE_RESET          __HAL_RCC_DMA2D_RELEASE_RESET\r\n#define __DMA2D_CLK_SLEEP_ENABLE       __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE\r\n#define __DMA2D_CLK_SLEEP_DISABLE      __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE\r\n\r\n/* alias define maintained for legacy */\r\n#define __HAL_RCC_OTGFS_FORCE_RESET    __HAL_RCC_USB_OTG_FS_FORCE_RESET\r\n#define __HAL_RCC_OTGFS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET\r\n\r\n#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE\r\n#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE\r\n#define __ADC34_CLK_ENABLE          __HAL_RCC_ADC34_CLK_ENABLE\r\n#define __ADC34_CLK_DISABLE         __HAL_RCC_ADC34_CLK_DISABLE\r\n#define __DAC2_CLK_ENABLE           __HAL_RCC_DAC2_CLK_ENABLE\r\n#define __DAC2_CLK_DISABLE          __HAL_RCC_DAC2_CLK_DISABLE\r\n#define __TIM18_CLK_ENABLE          __HAL_RCC_TIM18_CLK_ENABLE\r\n#define __TIM18_CLK_DISABLE         __HAL_RCC_TIM18_CLK_DISABLE\r\n#define __TIM19_CLK_ENABLE          __HAL_RCC_TIM19_CLK_ENABLE\r\n#define __TIM19_CLK_DISABLE         __HAL_RCC_TIM19_CLK_DISABLE\r\n#define __TIM20_CLK_ENABLE          __HAL_RCC_TIM20_CLK_ENABLE\r\n#define __TIM20_CLK_DISABLE         __HAL_RCC_TIM20_CLK_DISABLE\r\n#define __HRTIM1_CLK_ENABLE         __HAL_RCC_HRTIM1_CLK_ENABLE\r\n#define __HRTIM1_CLK_DISABLE        __HAL_RCC_HRTIM1_CLK_DISABLE\r\n#define __SDADC1_CLK_ENABLE         __HAL_RCC_SDADC1_CLK_ENABLE\r\n#define __SDADC2_CLK_ENABLE         __HAL_RCC_SDADC2_CLK_ENABLE\r\n#define __SDADC3_CLK_ENABLE         __HAL_RCC_SDADC3_CLK_ENABLE\r\n#define __SDADC1_CLK_DISABLE        __HAL_RCC_SDADC1_CLK_DISABLE\r\n#define __SDADC2_CLK_DISABLE        __HAL_RCC_SDADC2_CLK_DISABLE\r\n#define __SDADC3_CLK_DISABLE        __HAL_RCC_SDADC3_CLK_DISABLE\r\n\r\n#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET\r\n#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET\r\n#define __ADC34_FORCE_RESET         __HAL_RCC_ADC34_FORCE_RESET\r\n#define __ADC34_RELEASE_RESET       __HAL_RCC_ADC34_RELEASE_RESET\r\n#define __DAC2_FORCE_RESET          __HAL_RCC_DAC2_FORCE_RESET\r\n#define __DAC2_RELEASE_RESET        __HAL_RCC_DAC2_RELEASE_RESET\r\n#define __TIM18_FORCE_RESET         __HAL_RCC_TIM18_FORCE_RESET\r\n#define __TIM18_RELEASE_RESET       __HAL_RCC_TIM18_RELEASE_RESET\r\n#define __TIM19_FORCE_RESET         __HAL_RCC_TIM19_FORCE_RESET\r\n#define __TIM19_RELEASE_RESET       __HAL_RCC_TIM19_RELEASE_RESET\r\n#define __TIM20_FORCE_RESET         __HAL_RCC_TIM20_FORCE_RESET\r\n#define __TIM20_RELEASE_RESET       __HAL_RCC_TIM20_RELEASE_RESET\r\n#define __HRTIM1_FORCE_RESET        __HAL_RCC_HRTIM1_FORCE_RESET\r\n#define __HRTIM1_RELEASE_RESET      __HAL_RCC_HRTIM1_RELEASE_RESET\r\n#define __SDADC1_FORCE_RESET        __HAL_RCC_SDADC1_FORCE_RESET\r\n#define __SDADC2_FORCE_RESET        __HAL_RCC_SDADC2_FORCE_RESET\r\n#define __SDADC3_FORCE_RESET        __HAL_RCC_SDADC3_FORCE_RESET\r\n#define __SDADC1_RELEASE_RESET      __HAL_RCC_SDADC1_RELEASE_RESET\r\n#define __SDADC2_RELEASE_RESET      __HAL_RCC_SDADC2_RELEASE_RESET\r\n#define __SDADC3_RELEASE_RESET      __HAL_RCC_SDADC3_RELEASE_RESET\r\n\r\n#define __ADC1_IS_CLK_ENABLED       __HAL_RCC_ADC1_IS_CLK_ENABLED\r\n#define __ADC1_IS_CLK_DISABLED      __HAL_RCC_ADC1_IS_CLK_DISABLED\r\n#define __ADC12_IS_CLK_ENABLED      __HAL_RCC_ADC12_IS_CLK_ENABLED\r\n#define __ADC12_IS_CLK_DISABLED     __HAL_RCC_ADC12_IS_CLK_DISABLED\r\n#define __ADC34_IS_CLK_ENABLED      __HAL_RCC_ADC34_IS_CLK_ENABLED\r\n#define __ADC34_IS_CLK_DISABLED     __HAL_RCC_ADC34_IS_CLK_DISABLED\r\n#define __CEC_IS_CLK_ENABLED        __HAL_RCC_CEC_IS_CLK_ENABLED\r\n#define __CEC_IS_CLK_DISABLED       __HAL_RCC_CEC_IS_CLK_DISABLED\r\n#define __CRC_IS_CLK_ENABLED        __HAL_RCC_CRC_IS_CLK_ENABLED\r\n#define __CRC_IS_CLK_DISABLED       __HAL_RCC_CRC_IS_CLK_DISABLED\r\n#define __DAC1_IS_CLK_ENABLED       __HAL_RCC_DAC1_IS_CLK_ENABLED\r\n#define __DAC1_IS_CLK_DISABLED      __HAL_RCC_DAC1_IS_CLK_DISABLED\r\n#define __DAC2_IS_CLK_ENABLED       __HAL_RCC_DAC2_IS_CLK_ENABLED\r\n#define __DAC2_IS_CLK_DISABLED      __HAL_RCC_DAC2_IS_CLK_DISABLED\r\n#define __DMA1_IS_CLK_ENABLED       __HAL_RCC_DMA1_IS_CLK_ENABLED\r\n#define __DMA1_IS_CLK_DISABLED      __HAL_RCC_DMA1_IS_CLK_DISABLED\r\n#define __DMA2_IS_CLK_ENABLED       __HAL_RCC_DMA2_IS_CLK_ENABLED\r\n#define __DMA2_IS_CLK_DISABLED      __HAL_RCC_DMA2_IS_CLK_DISABLED\r\n#define __FLITF_IS_CLK_ENABLED      __HAL_RCC_FLITF_IS_CLK_ENABLED\r\n#define __FLITF_IS_CLK_DISABLED     __HAL_RCC_FLITF_IS_CLK_DISABLED\r\n#define __FMC_IS_CLK_ENABLED        __HAL_RCC_FMC_IS_CLK_ENABLED\r\n#define __FMC_IS_CLK_DISABLED       __HAL_RCC_FMC_IS_CLK_DISABLED\r\n#define __GPIOA_IS_CLK_ENABLED      __HAL_RCC_GPIOA_IS_CLK_ENABLED\r\n#define __GPIOA_IS_CLK_DISABLED     __HAL_RCC_GPIOA_IS_CLK_DISABLED\r\n#define __GPIOB_IS_CLK_ENABLED      __HAL_RCC_GPIOB_IS_CLK_ENABLED\r\n#define __GPIOB_IS_CLK_DISABLED     __HAL_RCC_GPIOB_IS_CLK_DISABLED\r\n#define __GPIOC_IS_CLK_ENABLED      __HAL_RCC_GPIOC_IS_CLK_ENABLED\r\n#define __GPIOC_IS_CLK_DISABLED     __HAL_RCC_GPIOC_IS_CLK_DISABLED\r\n#define __GPIOD_IS_CLK_ENABLED      __HAL_RCC_GPIOD_IS_CLK_ENABLED\r\n#define __GPIOD_IS_CLK_DISABLED     __HAL_RCC_GPIOD_IS_CLK_DISABLED\r\n#define __GPIOE_IS_CLK_ENABLED      __HAL_RCC_GPIOE_IS_CLK_ENABLED\r\n#define __GPIOE_IS_CLK_DISABLED     __HAL_RCC_GPIOE_IS_CLK_DISABLED\r\n#define __GPIOF_IS_CLK_ENABLED      __HAL_RCC_GPIOF_IS_CLK_ENABLED\r\n#define __GPIOF_IS_CLK_DISABLED     __HAL_RCC_GPIOF_IS_CLK_DISABLED\r\n#define __GPIOG_IS_CLK_ENABLED      __HAL_RCC_GPIOG_IS_CLK_ENABLED\r\n#define __GPIOG_IS_CLK_DISABLED     __HAL_RCC_GPIOG_IS_CLK_DISABLED\r\n#define __GPIOH_IS_CLK_ENABLED      __HAL_RCC_GPIOH_IS_CLK_ENABLED\r\n#define __GPIOH_IS_CLK_DISABLED     __HAL_RCC_GPIOH_IS_CLK_DISABLED\r\n#define __HRTIM1_IS_CLK_ENABLED     __HAL_RCC_HRTIM1_IS_CLK_ENABLED\r\n#define __HRTIM1_IS_CLK_DISABLED    __HAL_RCC_HRTIM1_IS_CLK_DISABLED\r\n#define __I2C1_IS_CLK_ENABLED       __HAL_RCC_I2C1_IS_CLK_ENABLED\r\n#define __I2C1_IS_CLK_DISABLED      __HAL_RCC_I2C1_IS_CLK_DISABLED\r\n#define __I2C2_IS_CLK_ENABLED       __HAL_RCC_I2C2_IS_CLK_ENABLED\r\n#define __I2C2_IS_CLK_DISABLED      __HAL_RCC_I2C2_IS_CLK_DISABLED\r\n#define __I2C3_IS_CLK_ENABLED       __HAL_RCC_I2C3_IS_CLK_ENABLED\r\n#define __I2C3_IS_CLK_DISABLED      __HAL_RCC_I2C3_IS_CLK_DISABLED\r\n#define __PWR_IS_CLK_ENABLED        __HAL_RCC_PWR_IS_CLK_ENABLED\r\n#define __PWR_IS_CLK_DISABLED       __HAL_RCC_PWR_IS_CLK_DISABLED\r\n#define __SYSCFG_IS_CLK_ENABLED     __HAL_RCC_SYSCFG_IS_CLK_ENABLED\r\n#define __SYSCFG_IS_CLK_DISABLED    __HAL_RCC_SYSCFG_IS_CLK_DISABLED\r\n#define __SPI1_IS_CLK_ENABLED       __HAL_RCC_SPI1_IS_CLK_ENABLED\r\n#define __SPI1_IS_CLK_DISABLED      __HAL_RCC_SPI1_IS_CLK_DISABLED\r\n#define __SPI2_IS_CLK_ENABLED       __HAL_RCC_SPI2_IS_CLK_ENABLED\r\n#define __SPI2_IS_CLK_DISABLED      __HAL_RCC_SPI2_IS_CLK_DISABLED\r\n#define __SPI3_IS_CLK_ENABLED       __HAL_RCC_SPI3_IS_CLK_ENABLED\r\n#define __SPI3_IS_CLK_DISABLED      __HAL_RCC_SPI3_IS_CLK_DISABLED\r\n#define __SPI4_IS_CLK_ENABLED       __HAL_RCC_SPI4_IS_CLK_ENABLED\r\n#define __SPI4_IS_CLK_DISABLED      __HAL_RCC_SPI4_IS_CLK_DISABLED\r\n#define __SDADC1_IS_CLK_ENABLED     __HAL_RCC_SDADC1_IS_CLK_ENABLED\r\n#define __SDADC1_IS_CLK_DISABLED    __HAL_RCC_SDADC1_IS_CLK_DISABLED\r\n#define __SDADC2_IS_CLK_ENABLED     __HAL_RCC_SDADC2_IS_CLK_ENABLED\r\n#define __SDADC2_IS_CLK_DISABLED    __HAL_RCC_SDADC2_IS_CLK_DISABLED\r\n#define __SDADC3_IS_CLK_ENABLED     __HAL_RCC_SDADC3_IS_CLK_ENABLED\r\n#define __SDADC3_IS_CLK_DISABLED    __HAL_RCC_SDADC3_IS_CLK_DISABLED\r\n#define __SRAM_IS_CLK_ENABLED       __HAL_RCC_SRAM_IS_CLK_ENABLED\r\n#define __SRAM_IS_CLK_DISABLED      __HAL_RCC_SRAM_IS_CLK_DISABLED\r\n#define __TIM1_IS_CLK_ENABLED       __HAL_RCC_TIM1_IS_CLK_ENABLED\r\n#define __TIM1_IS_CLK_DISABLED      __HAL_RCC_TIM1_IS_CLK_DISABLED\r\n#define __TIM2_IS_CLK_ENABLED       __HAL_RCC_TIM2_IS_CLK_ENABLED\r\n#define __TIM2_IS_CLK_DISABLED      __HAL_RCC_TIM2_IS_CLK_DISABLED\r\n#define __TIM3_IS_CLK_ENABLED       __HAL_RCC_TIM3_IS_CLK_ENABLED\r\n#define __TIM3_IS_CLK_DISABLED      __HAL_RCC_TIM3_IS_CLK_DISABLED\r\n#define __TIM4_IS_CLK_ENABLED       __HAL_RCC_TIM4_IS_CLK_ENABLED\r\n#define __TIM4_IS_CLK_DISABLED      __HAL_RCC_TIM4_IS_CLK_DISABLED\r\n#define __TIM5_IS_CLK_ENABLED       __HAL_RCC_TIM5_IS_CLK_ENABLED\r\n#define __TIM5_IS_CLK_DISABLED      __HAL_RCC_TIM5_IS_CLK_DISABLED\r\n#define __TIM6_IS_CLK_ENABLED       __HAL_RCC_TIM6_IS_CLK_ENABLED\r\n#define __TIM6_IS_CLK_DISABLED      __HAL_RCC_TIM6_IS_CLK_DISABLED\r\n#define __TIM7_IS_CLK_ENABLED       __HAL_RCC_TIM7_IS_CLK_ENABLED\r\n#define __TIM7_IS_CLK_DISABLED      __HAL_RCC_TIM7_IS_CLK_DISABLED\r\n#define __TIM8_IS_CLK_ENABLED       __HAL_RCC_TIM8_IS_CLK_ENABLED\r\n#define __TIM8_IS_CLK_DISABLED      __HAL_RCC_TIM8_IS_CLK_DISABLED\r\n#define __TIM12_IS_CLK_ENABLED      __HAL_RCC_TIM12_IS_CLK_ENABLED\r\n#define __TIM12_IS_CLK_DISABLED     __HAL_RCC_TIM12_IS_CLK_DISABLED\r\n#define __TIM13_IS_CLK_ENABLED      __HAL_RCC_TIM13_IS_CLK_ENABLED\r\n#define __TIM13_IS_CLK_DISABLED     __HAL_RCC_TIM13_IS_CLK_DISABLED\r\n#define __TIM14_IS_CLK_ENABLED      __HAL_RCC_TIM14_IS_CLK_ENABLED\r\n#define __TIM14_IS_CLK_DISABLED     __HAL_RCC_TIM14_IS_CLK_DISABLED\r\n#define __TIM15_IS_CLK_ENABLED      __HAL_RCC_TIM15_IS_CLK_ENABLED\r\n#define __TIM15_IS_CLK_DISABLED     __HAL_RCC_TIM15_IS_CLK_DISABLED\r\n#define __TIM16_IS_CLK_ENABLED      __HAL_RCC_TIM16_IS_CLK_ENABLED\r\n#define __TIM16_IS_CLK_DISABLED     __HAL_RCC_TIM16_IS_CLK_DISABLED\r\n#define __TIM17_IS_CLK_ENABLED      __HAL_RCC_TIM17_IS_CLK_ENABLED\r\n#define __TIM17_IS_CLK_DISABLED     __HAL_RCC_TIM17_IS_CLK_DISABLED\r\n#define __TIM18_IS_CLK_ENABLED      __HAL_RCC_TIM18_IS_CLK_ENABLED\r\n#define __TIM18_IS_CLK_DISABLED     __HAL_RCC_TIM18_IS_CLK_DISABLED\r\n#define __TIM19_IS_CLK_ENABLED      __HAL_RCC_TIM19_IS_CLK_ENABLED\r\n#define __TIM19_IS_CLK_DISABLED     __HAL_RCC_TIM19_IS_CLK_DISABLED\r\n#define __TIM20_IS_CLK_ENABLED      __HAL_RCC_TIM20_IS_CLK_ENABLED\r\n#define __TIM20_IS_CLK_DISABLED     __HAL_RCC_TIM20_IS_CLK_DISABLED\r\n#define __TSC_IS_CLK_ENABLED        __HAL_RCC_TSC_IS_CLK_ENABLED\r\n#define __TSC_IS_CLK_DISABLED       __HAL_RCC_TSC_IS_CLK_DISABLED\r\n#define __UART4_IS_CLK_ENABLED      __HAL_RCC_UART4_IS_CLK_ENABLED\r\n#define __UART4_IS_CLK_DISABLED     __HAL_RCC_UART4_IS_CLK_DISABLED\r\n#define __UART5_IS_CLK_ENABLED      __HAL_RCC_UART5_IS_CLK_ENABLED\r\n#define __UART5_IS_CLK_DISABLED     __HAL_RCC_UART5_IS_CLK_DISABLED\r\n#define __USART1_IS_CLK_ENABLED     __HAL_RCC_USART1_IS_CLK_ENABLED\r\n#define __USART1_IS_CLK_DISABLED    __HAL_RCC_USART1_IS_CLK_DISABLED\r\n#define __USART2_IS_CLK_ENABLED     __HAL_RCC_USART2_IS_CLK_ENABLED\r\n#define __USART2_IS_CLK_DISABLED    __HAL_RCC_USART2_IS_CLK_DISABLED\r\n#define __USART3_IS_CLK_ENABLED     __HAL_RCC_USART3_IS_CLK_ENABLED\r\n#define __USART3_IS_CLK_DISABLED    __HAL_RCC_USART3_IS_CLK_DISABLED\r\n#define __USB_IS_CLK_ENABLED        __HAL_RCC_USB_IS_CLK_ENABLED\r\n#define __USB_IS_CLK_DISABLED       __HAL_RCC_USB_IS_CLK_DISABLED\r\n#define __WWDG_IS_CLK_ENABLED       __HAL_RCC_WWDG_IS_CLK_ENABLED\r\n#define __WWDG_IS_CLK_DISABLED      __HAL_RCC_WWDG_IS_CLK_DISABLED\r\n\r\n#if defined(STM32F4)\r\n#define __HAL_RCC_SDMMC1_FORCE_RESET       __HAL_RCC_SDIO_FORCE_RESET\r\n#define __HAL_RCC_SDMMC1_RELEASE_RESET     __HAL_RCC_SDIO_RELEASE_RESET\r\n#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE  __HAL_RCC_SDIO_CLK_SLEEP_ENABLE\r\n#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE\r\n#define __HAL_RCC_SDMMC1_CLK_ENABLE        __HAL_RCC_SDIO_CLK_ENABLE\r\n#define __HAL_RCC_SDMMC1_CLK_DISABLE       __HAL_RCC_SDIO_CLK_DISABLE\r\n#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED    __HAL_RCC_SDIO_IS_CLK_ENABLED\r\n#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED   __HAL_RCC_SDIO_IS_CLK_DISABLED\r\n#define Sdmmc1ClockSelection               SdioClockSelection\r\n#define RCC_PERIPHCLK_SDMMC1               RCC_PERIPHCLK_SDIO\r\n#define RCC_SDMMC1CLKSOURCE_CLK48          RCC_SDIOCLKSOURCE_CK48\r\n#define RCC_SDMMC1CLKSOURCE_SYSCLK         RCC_SDIOCLKSOURCE_SYSCLK\r\n#define __HAL_RCC_SDMMC1_CONFIG            __HAL_RCC_SDIO_CONFIG\r\n#define __HAL_RCC_GET_SDMMC1_SOURCE        __HAL_RCC_GET_SDIO_SOURCE\r\n#endif\r\n\r\n#if defined(STM32F7) || defined(STM32L4)\r\n#define __HAL_RCC_SDIO_FORCE_RESET         __HAL_RCC_SDMMC1_FORCE_RESET\r\n#define __HAL_RCC_SDIO_RELEASE_RESET       __HAL_RCC_SDMMC1_RELEASE_RESET\r\n#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE    __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE\r\n#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE   __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE\r\n#define __HAL_RCC_SDIO_CLK_ENABLE          __HAL_RCC_SDMMC1_CLK_ENABLE\r\n#define __HAL_RCC_SDIO_CLK_DISABLE         __HAL_RCC_SDMMC1_CLK_DISABLE\r\n#define __HAL_RCC_SDIO_IS_CLK_ENABLED      __HAL_RCC_SDMMC1_IS_CLK_ENABLED\r\n#define __HAL_RCC_SDIO_IS_CLK_DISABLED     __HAL_RCC_SDMMC1_IS_CLK_DISABLED\r\n#define SdioClockSelection                 Sdmmc1ClockSelection\r\n#define RCC_PERIPHCLK_SDIO                 RCC_PERIPHCLK_SDMMC1\r\n#define __HAL_RCC_SDIO_CONFIG              __HAL_RCC_SDMMC1_CONFIG\r\n#define __HAL_RCC_GET_SDIO_SOURCE          __HAL_RCC_GET_SDMMC1_SOURCE\r\n#endif\r\n\r\n#if defined(STM32F7)\r\n#define RCC_SDIOCLKSOURCE_CLK48             RCC_SDMMC1CLKSOURCE_CLK48\r\n#define RCC_SDIOCLKSOURCE_SYSCLK           RCC_SDMMC1CLKSOURCE_SYSCLK\r\n#endif\r\n\r\n#if defined(STM32H7)\r\n#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()              __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()\r\n#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()         __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()\r\n#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()             __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()\r\n#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE()        __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()\r\n#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()             __HAL_RCC_USB1_OTG_HS_FORCE_RESET()\r\n#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()           __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()\r\n#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()        __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()\r\n#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()   __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()\r\n#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()       __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()\r\n#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE()  __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()\r\n\r\n#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()             __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()\r\n#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE()        __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()\r\n#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE()            __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()\r\n#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE()       __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()\r\n#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()            __HAL_RCC_USB2_OTG_FS_FORCE_RESET()\r\n#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET()          __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()\r\n#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()       __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()\r\n#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE()  __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()\r\n#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()      __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()\r\n#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()\r\n#endif\r\n\r\n#define __HAL_RCC_I2SCLK            __HAL_RCC_I2S_CONFIG\r\n#define __HAL_RCC_I2SCLK_CONFIG     __HAL_RCC_I2S_CONFIG\r\n\r\n#define __RCC_PLLSRC                RCC_GET_PLL_OSCSOURCE\r\n\r\n#define IS_RCC_MSIRANGE             IS_RCC_MSI_CLOCK_RANGE\r\n#define IS_RCC_RTCCLK_SOURCE        IS_RCC_RTCCLKSOURCE\r\n#define IS_RCC_SYSCLK_DIV           IS_RCC_HCLK\r\n#define IS_RCC_HCLK_DIV             IS_RCC_PCLK\r\n#define IS_RCC_PERIPHCLK            IS_RCC_PERIPHCLOCK\r\n\r\n#define RCC_IT_HSI14                RCC_IT_HSI14RDY\r\n\r\n#define RCC_IT_CSSLSE               RCC_IT_LSECSS\r\n#define RCC_IT_CSSHSE               RCC_IT_CSS\r\n\r\n#define RCC_PLLMUL_3                RCC_PLL_MUL3\r\n#define RCC_PLLMUL_4                RCC_PLL_MUL4\r\n#define RCC_PLLMUL_6                RCC_PLL_MUL6\r\n#define RCC_PLLMUL_8                RCC_PLL_MUL8\r\n#define RCC_PLLMUL_12               RCC_PLL_MUL12\r\n#define RCC_PLLMUL_16               RCC_PLL_MUL16\r\n#define RCC_PLLMUL_24               RCC_PLL_MUL24\r\n#define RCC_PLLMUL_32               RCC_PLL_MUL32\r\n#define RCC_PLLMUL_48               RCC_PLL_MUL48\r\n\r\n#define RCC_PLLDIV_2                RCC_PLL_DIV2\r\n#define RCC_PLLDIV_3                RCC_PLL_DIV3\r\n#define RCC_PLLDIV_4                RCC_PLL_DIV4\r\n\r\n#define IS_RCC_MCOSOURCE            IS_RCC_MCO1SOURCE\r\n#define __HAL_RCC_MCO_CONFIG        __HAL_RCC_MCO1_CONFIG\r\n#define RCC_MCO_NODIV               RCC_MCODIV_1\r\n#define RCC_MCO_DIV1                RCC_MCODIV_1\r\n#define RCC_MCO_DIV2                RCC_MCODIV_2\r\n#define RCC_MCO_DIV4                RCC_MCODIV_4\r\n#define RCC_MCO_DIV8                RCC_MCODIV_8\r\n#define RCC_MCO_DIV16               RCC_MCODIV_16\r\n#define RCC_MCO_DIV32               RCC_MCODIV_32\r\n#define RCC_MCO_DIV64               RCC_MCODIV_64\r\n#define RCC_MCO_DIV128              RCC_MCODIV_128\r\n#define RCC_MCOSOURCE_NONE          RCC_MCO1SOURCE_NOCLOCK\r\n#define RCC_MCOSOURCE_LSI           RCC_MCO1SOURCE_LSI\r\n#define RCC_MCOSOURCE_LSE           RCC_MCO1SOURCE_LSE\r\n#define RCC_MCOSOURCE_SYSCLK        RCC_MCO1SOURCE_SYSCLK\r\n#define RCC_MCOSOURCE_HSI           RCC_MCO1SOURCE_HSI\r\n#define RCC_MCOSOURCE_HSI14         RCC_MCO1SOURCE_HSI14\r\n#define RCC_MCOSOURCE_HSI48         RCC_MCO1SOURCE_HSI48\r\n#define RCC_MCOSOURCE_HSE           RCC_MCO1SOURCE_HSE\r\n#define RCC_MCOSOURCE_PLLCLK_DIV1   RCC_MCO1SOURCE_PLLCLK\r\n#define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK\r\n#define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2\r\n\r\n#if defined(STM32L4)\r\n#define RCC_RTCCLKSOURCE_NO_CLK     RCC_RTCCLKSOURCE_NONE\r\n#else\r\n#define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK\r\n#endif\r\n\r\n#define RCC_USBCLK_PLLSAI1          RCC_USBCLKSOURCE_PLLSAI1\r\n#define RCC_USBCLK_PLL              RCC_USBCLKSOURCE_PLL\r\n#define RCC_USBCLK_MSI              RCC_USBCLKSOURCE_MSI\r\n#define RCC_USBCLKSOURCE_PLLCLK     RCC_USBCLKSOURCE_PLL\r\n#define RCC_USBPLLCLK_DIV1          RCC_USBCLKSOURCE_PLL\r\n#define RCC_USBPLLCLK_DIV1_5        RCC_USBCLKSOURCE_PLL_DIV1_5\r\n#define RCC_USBPLLCLK_DIV2          RCC_USBCLKSOURCE_PLL_DIV2\r\n#define RCC_USBPLLCLK_DIV3          RCC_USBCLKSOURCE_PLL_DIV3\r\n\r\n#define HSION_BitNumber        RCC_HSION_BIT_NUMBER\r\n#define HSION_BITNUMBER        RCC_HSION_BIT_NUMBER\r\n#define HSEON_BitNumber        RCC_HSEON_BIT_NUMBER\r\n#define HSEON_BITNUMBER        RCC_HSEON_BIT_NUMBER\r\n#define MSION_BITNUMBER        RCC_MSION_BIT_NUMBER\r\n#define CSSON_BitNumber        RCC_CSSON_BIT_NUMBER\r\n#define CSSON_BITNUMBER        RCC_CSSON_BIT_NUMBER\r\n#define PLLON_BitNumber        RCC_PLLON_BIT_NUMBER\r\n#define PLLON_BITNUMBER        RCC_PLLON_BIT_NUMBER\r\n#define PLLI2SON_BitNumber     RCC_PLLI2SON_BIT_NUMBER\r\n#define I2SSRC_BitNumber       RCC_I2SSRC_BIT_NUMBER\r\n#define RTCEN_BitNumber        RCC_RTCEN_BIT_NUMBER\r\n#define RTCEN_BITNUMBER        RCC_RTCEN_BIT_NUMBER\r\n#define BDRST_BitNumber        RCC_BDRST_BIT_NUMBER\r\n#define BDRST_BITNUMBER        RCC_BDRST_BIT_NUMBER\r\n#define RTCRST_BITNUMBER       RCC_RTCRST_BIT_NUMBER\r\n#define LSION_BitNumber        RCC_LSION_BIT_NUMBER\r\n#define LSION_BITNUMBER        RCC_LSION_BIT_NUMBER\r\n#define LSEON_BitNumber        RCC_LSEON_BIT_NUMBER\r\n#define LSEON_BITNUMBER        RCC_LSEON_BIT_NUMBER\r\n#define LSEBYP_BITNUMBER       RCC_LSEBYP_BIT_NUMBER\r\n#define PLLSAION_BitNumber     RCC_PLLSAION_BIT_NUMBER\r\n#define TIMPRE_BitNumber       RCC_TIMPRE_BIT_NUMBER\r\n#define RMVF_BitNumber         RCC_RMVF_BIT_NUMBER\r\n#define RMVF_BITNUMBER         RCC_RMVF_BIT_NUMBER\r\n#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER\r\n#define CR_BYTE2_ADDRESS       RCC_CR_BYTE2_ADDRESS\r\n#define CIR_BYTE1_ADDRESS      RCC_CIR_BYTE1_ADDRESS\r\n#define CIR_BYTE2_ADDRESS      RCC_CIR_BYTE2_ADDRESS\r\n#define BDCR_BYTE0_ADDRESS     RCC_BDCR_BYTE0_ADDRESS\r\n#define DBP_TIMEOUT_VALUE      RCC_DBP_TIMEOUT_VALUE\r\n#define LSE_TIMEOUT_VALUE      RCC_LSE_TIMEOUT_VALUE\r\n\r\n#define CR_HSION_BB            RCC_CR_HSION_BB\r\n#define CR_CSSON_BB            RCC_CR_CSSON_BB\r\n#define CR_PLLON_BB            RCC_CR_PLLON_BB\r\n#define CR_PLLI2SON_BB         RCC_CR_PLLI2SON_BB\r\n#define CR_MSION_BB            RCC_CR_MSION_BB\r\n#define CSR_LSION_BB           RCC_CSR_LSION_BB\r\n#define CSR_LSEON_BB           RCC_CSR_LSEON_BB\r\n#define CSR_LSEBYP_BB          RCC_CSR_LSEBYP_BB\r\n#define CSR_RTCEN_BB           RCC_CSR_RTCEN_BB\r\n#define CSR_RTCRST_BB          RCC_CSR_RTCRST_BB\r\n#define CFGR_I2SSRC_BB         RCC_CFGR_I2SSRC_BB\r\n#define BDCR_RTCEN_BB          RCC_BDCR_RTCEN_BB\r\n#define BDCR_BDRST_BB          RCC_BDCR_BDRST_BB\r\n#define CR_HSEON_BB            RCC_CR_HSEON_BB\r\n#define CSR_RMVF_BB            RCC_CSR_RMVF_BB\r\n#define CR_PLLSAION_BB         RCC_CR_PLLSAION_BB\r\n#define DCKCFGR_TIMPRE_BB      RCC_DCKCFGR_TIMPRE_BB\r\n\r\n#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER     __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE\r\n#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER    __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE\r\n#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB        __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE\r\n#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB       __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE\r\n#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE         __HAL_RCC_CRS_RELOADVALUE_CALCULATE\r\n\r\n#define __HAL_RCC_GET_IT_SOURCE                     __HAL_RCC_GET_IT\r\n\r\n#define RCC_CRS_SYNCWARM       RCC_CRS_SYNCWARN\r\n#define RCC_CRS_TRIMOV         RCC_CRS_TRIMOVF\r\n\r\n#define RCC_PERIPHCLK_CK48               RCC_PERIPHCLK_CLK48\r\n#define RCC_CK48CLKSOURCE_PLLQ           RCC_CLK48CLKSOURCE_PLLQ\r\n#define RCC_CK48CLKSOURCE_PLLSAIP        RCC_CLK48CLKSOURCE_PLLSAIP\r\n#define RCC_CK48CLKSOURCE_PLLI2SQ        RCC_CLK48CLKSOURCE_PLLI2SQ\r\n#define IS_RCC_CK48CLKSOURCE             IS_RCC_CLK48CLKSOURCE\r\n#define RCC_SDIOCLKSOURCE_CK48           RCC_SDIOCLKSOURCE_CLK48\r\n\r\n#define __HAL_RCC_DFSDM_CLK_ENABLE             __HAL_RCC_DFSDM1_CLK_ENABLE\r\n#define __HAL_RCC_DFSDM_CLK_DISABLE            __HAL_RCC_DFSDM1_CLK_DISABLE\r\n#define __HAL_RCC_DFSDM_IS_CLK_ENABLED         __HAL_RCC_DFSDM1_IS_CLK_ENABLED\r\n#define __HAL_RCC_DFSDM_IS_CLK_DISABLED        __HAL_RCC_DFSDM1_IS_CLK_DISABLED\r\n#define __HAL_RCC_DFSDM_FORCE_RESET            __HAL_RCC_DFSDM1_FORCE_RESET\r\n#define __HAL_RCC_DFSDM_RELEASE_RESET          __HAL_RCC_DFSDM1_RELEASE_RESET\r\n#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE       __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE\r\n#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE      __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE\r\n#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED   __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED\r\n#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED  __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED\r\n#define DfsdmClockSelection         Dfsdm1ClockSelection\r\n#define RCC_PERIPHCLK_DFSDM         RCC_PERIPHCLK_DFSDM1\r\n#define RCC_DFSDMCLKSOURCE_PCLK     RCC_DFSDM1CLKSOURCE_PCLK2\r\n#define RCC_DFSDMCLKSOURCE_SYSCLK   RCC_DFSDM1CLKSOURCE_SYSCLK\r\n#define __HAL_RCC_DFSDM_CONFIG      __HAL_RCC_DFSDM1_CONFIG\r\n#define __HAL_RCC_GET_DFSDM_SOURCE  __HAL_RCC_GET_DFSDM1_SOURCE\r\n#define RCC_DFSDM1CLKSOURCE_PCLK    RCC_DFSDM1CLKSOURCE_PCLK2\r\n#define RCC_SWPMI1CLKSOURCE_PCLK    RCC_SWPMI1CLKSOURCE_PCLK1\r\n#define RCC_LPTIM1CLKSOURCE_PCLK    RCC_LPTIM1CLKSOURCE_PCLK1\r\n#define RCC_LPTIM2CLKSOURCE_PCLK    RCC_LPTIM2CLKSOURCE_PCLK1\r\n\r\n#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM1AUDIOCLKSOURCE_I2S1\r\n#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM1AUDIOCLKSOURCE_I2S2\r\n#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM2AUDIOCLKSOURCE_I2S1\r\n#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM2AUDIOCLKSOURCE_I2S2\r\n#define RCC_DFSDM1CLKSOURCE_APB2            RCC_DFSDM1CLKSOURCE_PCLK2\r\n#define RCC_DFSDM2CLKSOURCE_APB2            RCC_DFSDM2CLKSOURCE_PCLK2\r\n#define RCC_FMPI2C1CLKSOURCE_APB            RCC_FMPI2C1CLKSOURCE_PCLK1\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define  HAL_RNG_ReadyCallback(__HANDLE__)  HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG\r\n#define __HAL_RTC_DISABLE_IT                      __HAL_RTC_EXTI_DISABLE_IT\r\n#define __HAL_RTC_ENABLE_IT                       __HAL_RTC_EXTI_ENABLE_IT\r\n\r\n#if defined (STM32F1)\r\n#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()\r\n\r\n#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_ENABLE_IT()\r\n\r\n#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_DISABLE_IT()\r\n\r\n#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT)    __HAL_RTC_ALARM_EXTI_GET_FLAG()\r\n\r\n#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()\r\n#else\r\n#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \\\r\n                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \\\r\n                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))\r\n#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__)   (((__EXTI_LINE__)  == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \\\r\n                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \\\r\n                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))\r\n#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \\\r\n                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \\\r\n                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))\r\n#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__)    (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \\\r\n                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \\\r\n                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))\r\n#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__)   (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \\\r\n                                                      (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() :  \\\r\n                                                          __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))\r\n#endif   /* STM32F1 */\r\n\r\n#define IS_ALARM                                  IS_RTC_ALARM\r\n#define IS_ALARM_MASK                             IS_RTC_ALARM_MASK\r\n#define IS_TAMPER                                 IS_RTC_TAMPER\r\n#define IS_TAMPER_ERASE_MODE                      IS_RTC_TAMPER_ERASE_MODE\r\n#define IS_TAMPER_FILTER                          IS_RTC_TAMPER_FILTER\r\n#define IS_TAMPER_INTERRUPT                       IS_RTC_TAMPER_INTERRUPT\r\n#define IS_TAMPER_MASKFLAG_STATE                  IS_RTC_TAMPER_MASKFLAG_STATE\r\n#define IS_TAMPER_PRECHARGE_DURATION              IS_RTC_TAMPER_PRECHARGE_DURATION\r\n#define IS_TAMPER_PULLUP_STATE                    IS_RTC_TAMPER_PULLUP_STATE\r\n#define IS_TAMPER_SAMPLING_FREQ                   IS_RTC_TAMPER_SAMPLING_FREQ\r\n#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION     IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION\r\n#define IS_TAMPER_TRIGGER                         IS_RTC_TAMPER_TRIGGER\r\n#define IS_WAKEUP_CLOCK                           IS_RTC_WAKEUP_CLOCK\r\n#define IS_WAKEUP_COUNTER                         IS_RTC_WAKEUP_COUNTER\r\n\r\n#define __RTC_WRITEPROTECTION_ENABLE  __HAL_RTC_WRITEPROTECTION_ENABLE\r\n#define __RTC_WRITEPROTECTION_DISABLE  __HAL_RTC_WRITEPROTECTION_DISABLE\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define SD_OCR_CID_CSD_OVERWRIETE   SD_OCR_CID_CSD_OVERWRITE\r\n#define SD_CMD_SD_APP_STAUS         SD_CMD_SD_APP_STATUS\r\n\r\n#if defined(STM32F4) || defined(STM32F2)\r\n#define  SD_SDMMC_DISABLED          SD_SDIO_DISABLED\r\n#define  SD_SDMMC_FUNCTION_BUSY     SD_SDIO_FUNCTION_BUSY\r\n#define  SD_SDMMC_FUNCTION_FAILED   SD_SDIO_FUNCTION_FAILED\r\n#define  SD_SDMMC_UNKNOWN_FUNCTION  SD_SDIO_UNKNOWN_FUNCTION\r\n#define  SD_CMD_SDMMC_SEN_OP_COND   SD_CMD_SDIO_SEN_OP_COND\r\n#define  SD_CMD_SDMMC_RW_DIRECT     SD_CMD_SDIO_RW_DIRECT\r\n#define  SD_CMD_SDMMC_RW_EXTENDED   SD_CMD_SDIO_RW_EXTENDED\r\n#define  __HAL_SD_SDMMC_ENABLE      __HAL_SD_SDIO_ENABLE\r\n#define  __HAL_SD_SDMMC_DISABLE     __HAL_SD_SDIO_DISABLE\r\n#define  __HAL_SD_SDMMC_DMA_ENABLE  __HAL_SD_SDIO_DMA_ENABLE\r\n#define  __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL\r\n#define  __HAL_SD_SDMMC_ENABLE_IT   __HAL_SD_SDIO_ENABLE_IT\r\n#define  __HAL_SD_SDMMC_DISABLE_IT  __HAL_SD_SDIO_DISABLE_IT\r\n#define  __HAL_SD_SDMMC_GET_FLAG    __HAL_SD_SDIO_GET_FLAG\r\n#define  __HAL_SD_SDMMC_CLEAR_FLAG  __HAL_SD_SDIO_CLEAR_FLAG\r\n#define  __HAL_SD_SDMMC_GET_IT      __HAL_SD_SDIO_GET_IT\r\n#define  __HAL_SD_SDMMC_CLEAR_IT    __HAL_SD_SDIO_CLEAR_IT\r\n#define  SDMMC_STATIC_FLAGS         SDIO_STATIC_FLAGS\r\n#define  SDMMC_CMD0TIMEOUT          SDIO_CMD0TIMEOUT\r\n#define  SD_SDMMC_SEND_IF_COND      SD_SDIO_SEND_IF_COND\r\n/* alias CMSIS */\r\n#define  SDMMC1_IRQn                SDIO_IRQn\r\n#define  SDMMC1_IRQHandler          SDIO_IRQHandler\r\n#endif\r\n\r\n#if defined(STM32F7) || defined(STM32L4)\r\n#define  SD_SDIO_DISABLED           SD_SDMMC_DISABLED\r\n#define  SD_SDIO_FUNCTION_BUSY      SD_SDMMC_FUNCTION_BUSY\r\n#define  SD_SDIO_FUNCTION_FAILED    SD_SDMMC_FUNCTION_FAILED\r\n#define  SD_SDIO_UNKNOWN_FUNCTION   SD_SDMMC_UNKNOWN_FUNCTION\r\n#define  SD_CMD_SDIO_SEN_OP_COND    SD_CMD_SDMMC_SEN_OP_COND\r\n#define  SD_CMD_SDIO_RW_DIRECT      SD_CMD_SDMMC_RW_DIRECT\r\n#define  SD_CMD_SDIO_RW_EXTENDED    SD_CMD_SDMMC_RW_EXTENDED\r\n#define  __HAL_SD_SDIO_ENABLE       __HAL_SD_SDMMC_ENABLE\r\n#define  __HAL_SD_SDIO_DISABLE      __HAL_SD_SDMMC_DISABLE\r\n#define  __HAL_SD_SDIO_DMA_ENABLE   __HAL_SD_SDMMC_DMA_ENABLE\r\n#define  __HAL_SD_SDIO_DMA_DISABL   __HAL_SD_SDMMC_DMA_DISABLE\r\n#define  __HAL_SD_SDIO_ENABLE_IT    __HAL_SD_SDMMC_ENABLE_IT\r\n#define  __HAL_SD_SDIO_DISABLE_IT   __HAL_SD_SDMMC_DISABLE_IT\r\n#define  __HAL_SD_SDIO_GET_FLAG     __HAL_SD_SDMMC_GET_FLAG\r\n#define  __HAL_SD_SDIO_CLEAR_FLAG   __HAL_SD_SDMMC_CLEAR_FLAG\r\n#define  __HAL_SD_SDIO_GET_IT       __HAL_SD_SDMMC_GET_IT\r\n#define  __HAL_SD_SDIO_CLEAR_IT     __HAL_SD_SDMMC_CLEAR_IT\r\n#define  SDIO_STATIC_FLAGS\t        SDMMC_STATIC_FLAGS\r\n#define  SDIO_CMD0TIMEOUT\t          SDMMC_CMD0TIMEOUT\r\n#define  SD_SDIO_SEND_IF_COND\t      SD_SDMMC_SEND_IF_COND\r\n/* alias CMSIS for compatibilities */\r\n#define  SDIO_IRQn                  SDMMC1_IRQn\r\n#define  SDIO_IRQHandler            SDMMC1_IRQHandler\r\n#endif\r\n\r\n#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2)\r\n#define  HAL_SD_CardCIDTypedef       HAL_SD_CardCIDTypeDef\r\n#define  HAL_SD_CardCSDTypedef       HAL_SD_CardCSDTypeDef\r\n#define  HAL_SD_CardStatusTypedef    HAL_SD_CardStatusTypeDef\r\n#define  HAL_SD_CardStateTypedef     HAL_SD_CardStateTypeDef\r\n#endif\r\n\r\n#if defined(STM32H7)\r\n#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback   HAL_MMCEx_Read_DMADoubleBuf0CpltCallback\r\n#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback   HAL_MMCEx_Read_DMADoubleBuf1CpltCallback\r\n#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback  HAL_MMCEx_Write_DMADoubleBuf0CpltCallback\r\n#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback  HAL_MMCEx_Write_DMADoubleBuf1CpltCallback\r\n#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback    HAL_SDEx_Read_DMADoubleBuf0CpltCallback\r\n#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback    HAL_SDEx_Read_DMADoubleBuf1CpltCallback\r\n#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback   HAL_SDEx_Write_DMADoubleBuf0CpltCallback\r\n#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback   HAL_SDEx_Write_DMADoubleBuf1CpltCallback\r\n#endif\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define __SMARTCARD_ENABLE_IT           __HAL_SMARTCARD_ENABLE_IT\r\n#define __SMARTCARD_DISABLE_IT          __HAL_SMARTCARD_DISABLE_IT\r\n#define __SMARTCARD_ENABLE              __HAL_SMARTCARD_ENABLE\r\n#define __SMARTCARD_DISABLE             __HAL_SMARTCARD_DISABLE\r\n#define __SMARTCARD_DMA_REQUEST_ENABLE  __HAL_SMARTCARD_DMA_REQUEST_ENABLE\r\n#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE\r\n\r\n#define __HAL_SMARTCARD_GETCLOCKSOURCE  SMARTCARD_GETCLOCKSOURCE\r\n#define __SMARTCARD_GETCLOCKSOURCE      SMARTCARD_GETCLOCKSOURCE\r\n\r\n#define IS_SMARTCARD_ONEBIT_SAMPLING    IS_SMARTCARD_ONE_BIT_SAMPLE\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define __HAL_SMBUS_RESET_CR1           SMBUS_RESET_CR1\r\n#define __HAL_SMBUS_RESET_CR2           SMBUS_RESET_CR2\r\n#define __HAL_SMBUS_GENERATE_START      SMBUS_GENERATE_START\r\n#define __HAL_SMBUS_GET_ADDR_MATCH      SMBUS_GET_ADDR_MATCH\r\n#define __HAL_SMBUS_GET_DIR             SMBUS_GET_DIR\r\n#define __HAL_SMBUS_GET_STOP_MODE       SMBUS_GET_STOP_MODE\r\n#define __HAL_SMBUS_GET_PEC_MODE        SMBUS_GET_PEC_MODE\r\n#define __HAL_SMBUS_GET_ALERT_ENABLED   SMBUS_GET_ALERT_ENABLED\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define __HAL_SPI_1LINE_TX              SPI_1LINE_TX\r\n#define __HAL_SPI_1LINE_RX              SPI_1LINE_RX\r\n#define __HAL_SPI_RESET_CRC             SPI_RESET_CRC\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define __HAL_UART_GETCLOCKSOURCE       UART_GETCLOCKSOURCE\r\n#define __HAL_UART_MASK_COMPUTATION     UART_MASK_COMPUTATION\r\n#define __UART_GETCLOCKSOURCE           UART_GETCLOCKSOURCE\r\n#define __UART_MASK_COMPUTATION         UART_MASK_COMPUTATION\r\n\r\n#define IS_UART_WAKEUPMETHODE           IS_UART_WAKEUPMETHOD\r\n\r\n#define IS_UART_ONEBIT_SAMPLE           IS_UART_ONE_BIT_SAMPLE\r\n#define IS_UART_ONEBIT_SAMPLING         IS_UART_ONE_BIT_SAMPLE\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define __USART_ENABLE_IT               __HAL_USART_ENABLE_IT\r\n#define __USART_DISABLE_IT              __HAL_USART_DISABLE_IT\r\n#define __USART_ENABLE                  __HAL_USART_ENABLE\r\n#define __USART_DISABLE                 __HAL_USART_DISABLE\r\n\r\n#define __HAL_USART_GETCLOCKSOURCE      USART_GETCLOCKSOURCE\r\n#define __USART_GETCLOCKSOURCE          USART_GETCLOCKSOURCE\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define USB_EXTI_LINE_WAKEUP                               USB_WAKEUP_EXTI_LINE\r\n\r\n#define USB_FS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE\r\n#define USB_FS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE\r\n#define USB_FS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE\r\n#define USB_FS_EXTI_LINE_WAKEUP                            USB_OTG_FS_WAKEUP_EXTI_LINE\r\n\r\n#define USB_HS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE\r\n#define USB_HS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE\r\n#define USB_HS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE\r\n#define USB_HS_EXTI_LINE_WAKEUP                            USB_OTG_HS_WAKEUP_EXTI_LINE\r\n\r\n#define __HAL_USB_EXTI_ENABLE_IT                           __HAL_USB_WAKEUP_EXTI_ENABLE_IT\r\n#define __HAL_USB_EXTI_DISABLE_IT                          __HAL_USB_WAKEUP_EXTI_DISABLE_IT\r\n#define __HAL_USB_EXTI_GET_FLAG                            __HAL_USB_WAKEUP_EXTI_GET_FLAG\r\n#define __HAL_USB_EXTI_CLEAR_FLAG                          __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG\r\n#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER             __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE\r\n#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER            __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE\r\n#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER           __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE\r\n\r\n#define __HAL_USB_FS_EXTI_ENABLE_IT                        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT\r\n#define __HAL_USB_FS_EXTI_DISABLE_IT                       __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT\r\n#define __HAL_USB_FS_EXTI_GET_FLAG                         __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG\r\n#define __HAL_USB_FS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG\r\n#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE\r\n#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE\r\n#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE\r\n#define __HAL_USB_FS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT\r\n\r\n#define __HAL_USB_HS_EXTI_ENABLE_IT                        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT\r\n#define __HAL_USB_HS_EXTI_DISABLE_IT                       __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT\r\n#define __HAL_USB_HS_EXTI_GET_FLAG                         __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG\r\n#define __HAL_USB_HS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG\r\n#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE\r\n#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE\r\n#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE\r\n#define __HAL_USB_HS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT\r\n\r\n#define HAL_PCD_ActiveRemoteWakeup                         HAL_PCD_ActivateRemoteWakeup\r\n#define HAL_PCD_DeActiveRemoteWakeup                       HAL_PCD_DeActivateRemoteWakeup\r\n\r\n#define HAL_PCD_SetTxFiFo                                  HAL_PCDEx_SetTxFiFo\r\n#define HAL_PCD_SetRxFiFo                                  HAL_PCDEx_SetRxFiFo\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define __HAL_TIM_SetICPrescalerValue   TIM_SET_ICPRESCALERVALUE\r\n#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE\r\n\r\n#define TIM_GET_ITSTATUS                __HAL_TIM_GET_IT_SOURCE\r\n#define TIM_GET_CLEAR_IT                __HAL_TIM_CLEAR_IT\r\n\r\n#define __HAL_TIM_GET_ITSTATUS          __HAL_TIM_GET_IT_SOURCE\r\n\r\n#define __HAL_TIM_DIRECTION_STATUS      __HAL_TIM_IS_TIM_COUNTING_DOWN\r\n#define __HAL_TIM_PRESCALER             __HAL_TIM_SET_PRESCALER\r\n#define __HAL_TIM_SetCounter            __HAL_TIM_SET_COUNTER\r\n#define __HAL_TIM_GetCounter            __HAL_TIM_GET_COUNTER\r\n#define __HAL_TIM_SetAutoreload         __HAL_TIM_SET_AUTORELOAD\r\n#define __HAL_TIM_GetAutoreload         __HAL_TIM_GET_AUTORELOAD\r\n#define __HAL_TIM_SetClockDivision      __HAL_TIM_SET_CLOCKDIVISION\r\n#define __HAL_TIM_GetClockDivision      __HAL_TIM_GET_CLOCKDIVISION\r\n#define __HAL_TIM_SetICPrescaler        __HAL_TIM_SET_ICPRESCALER\r\n#define __HAL_TIM_GetICPrescaler        __HAL_TIM_GET_ICPRESCALER\r\n#define __HAL_TIM_SetCompare            __HAL_TIM_SET_COMPARE\r\n#define __HAL_TIM_GetCompare            __HAL_TIM_GET_COMPARE\r\n\r\n#define TIM_BREAKINPUTSOURCE_DFSDM  TIM_BREAKINPUTSOURCE_DFSDM1\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define __HAL_ETH_EXTI_ENABLE_IT                   __HAL_ETH_WAKEUP_EXTI_ENABLE_IT\r\n#define __HAL_ETH_EXTI_DISABLE_IT                  __HAL_ETH_WAKEUP_EXTI_DISABLE_IT\r\n#define __HAL_ETH_EXTI_GET_FLAG                    __HAL_ETH_WAKEUP_EXTI_GET_FLAG\r\n#define __HAL_ETH_EXTI_CLEAR_FLAG                  __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG\r\n#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER     __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER\r\n#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER    __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER\r\n#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER   __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER\r\n\r\n#define ETH_PROMISCIOUSMODE_ENABLE   ETH_PROMISCUOUS_MODE_ENABLE\r\n#define ETH_PROMISCIOUSMODE_DISABLE  ETH_PROMISCUOUS_MODE_DISABLE\r\n#define IS_ETH_PROMISCIOUS_MODE      IS_ETH_PROMISCUOUS_MODE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define __HAL_LTDC_LAYER LTDC_LAYER\r\n#if defined(STM32F7)\r\n#else\r\n#define __HAL_LTDC_RELOAD_CONFIG  __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG\r\n#endif\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define SAI_OUTPUTDRIVE_DISABLED          SAI_OUTPUTDRIVE_DISABLE\r\n#define SAI_OUTPUTDRIVE_ENABLED           SAI_OUTPUTDRIVE_ENABLE\r\n#define SAI_MASTERDIVIDER_ENABLED         SAI_MASTERDIVIDER_ENABLE\r\n#define SAI_MASTERDIVIDER_DISABLED        SAI_MASTERDIVIDER_DISABLE\r\n#define SAI_STREOMODE                     SAI_STEREOMODE\r\n#define SAI_FIFOStatus_Empty              SAI_FIFOSTATUS_EMPTY\r\n#define SAI_FIFOStatus_Less1QuarterFull   SAI_FIFOSTATUS_LESS1QUARTERFULL\r\n#define SAI_FIFOStatus_1QuarterFull       SAI_FIFOSTATUS_1QUARTERFULL\r\n#define SAI_FIFOStatus_HalfFull           SAI_FIFOSTATUS_HALFFULL\r\n#define SAI_FIFOStatus_3QuartersFull      SAI_FIFOSTATUS_3QUARTERFULL\r\n#define SAI_FIFOStatus_Full               SAI_FIFOSTATUS_FULL\r\n#define IS_SAI_BLOCK_MONO_STREO_MODE      IS_SAI_BLOCK_MONO_STEREO_MODE\r\n#define SAI_SYNCHRONOUS_EXT               SAI_SYNCHRONOUS_EXT_SAI1\r\n#define SAI_SYNCEXT_IN_ENABLE             SAI_SYNCEXT_OUTBLOCKA_ENABLE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n#if defined(STM32H7)\r\n#define HAL_SPDIFRX_ReceiveControlFlow      HAL_SPDIFRX_ReceiveCtrlFlow\r\n#define HAL_SPDIFRX_ReceiveControlFlow_IT   HAL_SPDIFRX_ReceiveCtrlFlow_IT\r\n#define HAL_SPDIFRX_ReceiveControlFlow_DMA  HAL_SPDIFRX_ReceiveCtrlFlow_DMA\r\n#endif\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* ___STM32_HAL_LEGACY */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal.h\r\n  * @author  MCD Application Team\r\n  * @brief   This file contains all the functions prototypes for the HAL \r\n  *          module driver.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_H\r\n#define __STM32F7xx_HAL_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_conf.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup HAL\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup HAL_Exported_Constants HAL Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup HAL_TICK_FREQ Tick Frequency\r\n  * @{\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_TICK_FREQ_10HZ         = 100U,\r\n  HAL_TICK_FREQ_100HZ        = 10U,\r\n  HAL_TICK_FREQ_1KHZ         = 1U,\r\n  HAL_TICK_FREQ_DEFAULT      = HAL_TICK_FREQ_1KHZ\r\n} HAL_TickFreqTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SYSCFG_BootMode Boot Mode\r\n  * @{\r\n  */\r\n#define SYSCFG_MEM_BOOT_ADD0          ((uint32_t)0x00000000U)\r\n#define SYSCFG_MEM_BOOT_ADD1          SYSCFG_MEMRMP_MEM_BOOT\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n   \r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup HAL_Exported_Macros HAL Exported Macros\r\n  * @{\r\n  */\r\n  \r\n/** @brief  Freeze/Unfreeze Peripherals in Debug mode \r\n  */\r\n#define __HAL_DBGMCU_FREEZE_TIM2()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))\r\n#define __HAL_DBGMCU_FREEZE_TIM3()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))\r\n#define __HAL_DBGMCU_FREEZE_TIM4()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))\r\n#define __HAL_DBGMCU_FREEZE_TIM5()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))\r\n#define __HAL_DBGMCU_FREEZE_TIM6()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))\r\n#define __HAL_DBGMCU_FREEZE_TIM7()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))\r\n#define __HAL_DBGMCU_FREEZE_TIM12()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))\r\n#define __HAL_DBGMCU_FREEZE_TIM13()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))\r\n#define __HAL_DBGMCU_FREEZE_TIM14()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))\r\n#define __HAL_DBGMCU_FREEZE_LPTIM1()         (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_LPTIM1_STOP))\r\n#define __HAL_DBGMCU_FREEZE_RTC()            (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))\r\n#define __HAL_DBGMCU_FREEZE_WWDG()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))\r\n#define __HAL_DBGMCU_FREEZE_IWDG()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))\r\n#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))\r\n#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))\r\n#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))\r\n#define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT))\r\n#define __HAL_DBGMCU_FREEZE_CAN1()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))\r\n#define __HAL_DBGMCU_FREEZE_CAN2()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))\r\n#define __HAL_DBGMCU_FREEZE_TIM1()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))\r\n#define __HAL_DBGMCU_FREEZE_TIM8()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))\r\n#define __HAL_DBGMCU_FREEZE_TIM9()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))\r\n#define __HAL_DBGMCU_FREEZE_TIM10()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))\r\n#define __HAL_DBGMCU_FREEZE_TIM11()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))\r\n\r\n#define __HAL_DBGMCU_UNFREEZE_TIM2()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_TIM3()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_TIM4()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_TIM5()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_TIM6()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_TIM7()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_TIM12()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_TIM13()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_TIM14()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_LPTIM1()         (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_LPTIM1_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_RTC()            (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_WWDG()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_IWDG()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))\r\n#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))\r\n#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))\r\n#define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT))\r\n#define __HAL_DBGMCU_UNFREEZE_CAN1()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_CAN2()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_TIM1()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_TIM8()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_TIM9()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_TIM10()          (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_TIM11()          (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))\r\n\r\n\r\n/** @brief  FMC (NOR/RAM) mapped at 0x60000000 and SDRAM mapped at 0xC0000000\r\n  */\r\n#define __HAL_SYSCFG_REMAPMEMORY_FMC()          (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC))\r\n                                       \r\n\r\n/** @brief  FMC/SDRAM  mapped at 0x60000000 (NOR/RAM) mapped at 0xC0000000\r\n  */\r\n#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC);\\\r\n                                          SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_SWP_FMC_0);\\\r\n                                         }while(0);\r\n/**\r\n  * @brief  Return the memory boot mapping as configured by user.\r\n  * @retval The boot mode as configured by user. The returned value can be one\r\n  *         of the following values:\r\n  *           @arg @ref SYSCFG_MEM_BOOT_ADD0\r\n  *           @arg @ref SYSCFG_MEM_BOOT_ADD1\r\n  */\r\n#define __HAL_SYSCFG_GET_BOOT_MODE()           READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_BOOT)\r\n\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n/** @brief  SYSCFG Break Cortex-M7 Lockup lock.\r\n  *         Enable and lock the connection of Cortex-M7 LOCKUP (Hardfault) output to TIM1/8 Break input.\r\n  * @note   The selected configuration is locked and can be unlocked only by system reset.\r\n  */\r\n#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()     SET_BIT(SYSCFG->CBR, SYSCFG_CBR_CLL)\r\n\r\n/** @brief  SYSCFG Break PVD lock.\r\n  *         Enable and lock the PVD connection to Timer1/8 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR1 register.\r\n  * @note   The selected configuration is locked and can be unlocked only by system reset.\r\n  */\r\n#define __HAL_SYSCFG_BREAK_PVD_LOCK()        SET_BIT(SYSCFG->CBR, SYSCFG_CBR_PVDL)\r\n#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup HAL_Private_Macros HAL Private Macros\r\n  * @{\r\n  */\r\n#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ)  || \\\r\n                           ((FREQ) == HAL_TICK_FREQ_100HZ) || \\\r\n                           ((FREQ) == HAL_TICK_FREQ_1KHZ))\r\n/**\r\n  * @}\r\n  */\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup HAL_Exported_Functions\r\n  * @{\r\n  */\r\n/** @addtogroup HAL_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n/* Initialization and Configuration functions  ******************************/\r\nHAL_StatusTypeDef HAL_Init(void);\r\nHAL_StatusTypeDef HAL_DeInit(void);\r\nvoid HAL_MspInit(void);\r\nvoid HAL_MspDeInit(void);\r\nHAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);\r\n/**\r\n  * @}\r\n  */\r\n \r\n/** @addtogroup HAL_Exported_Functions_Group2\r\n  * @{\r\n  */ \r\n/* Peripheral Control functions  ************************************************/\r\nvoid HAL_IncTick(void);\r\nvoid HAL_Delay(uint32_t Delay);\r\nuint32_t HAL_GetTick(void);\r\nuint32_t HAL_GetTickPrio(void);\r\nHAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);\r\nHAL_TickFreqTypeDef HAL_GetTickFreq(void);\r\nvoid HAL_SuspendTick(void);\r\nvoid HAL_ResumeTick(void);\r\nuint32_t HAL_GetHalVersion(void);\r\nuint32_t HAL_GetREVID(void);\r\nuint32_t HAL_GetDEVID(void);\r\nuint32_t HAL_GetUIDw0(void);\r\nuint32_t HAL_GetUIDw1(void);\r\nuint32_t HAL_GetUIDw2(void);\r\nvoid HAL_DBGMCU_EnableDBGSleepMode(void);\r\nvoid HAL_DBGMCU_DisableDBGSleepMode(void);\r\nvoid HAL_DBGMCU_EnableDBGStopMode(void);\r\nvoid HAL_DBGMCU_DisableDBGStopMode(void);\r\nvoid HAL_DBGMCU_EnableDBGStandbyMode(void);\r\nvoid HAL_DBGMCU_DisableDBGStandbyMode(void);\r\nvoid HAL_EnableCompensationCell(void);\r\nvoid HAL_DisableCompensationCell(void);\r\nvoid HAL_EnableFMCMemorySwapping(void);\r\nvoid HAL_DisableFMCMemorySwapping(void);\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\nvoid HAL_EnableMemorySwappingBank(void);\r\nvoid HAL_DisableMemorySwappingBank(void);\r\n#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */  \r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @defgroup HAL_Private_Variables HAL Private Variables\r\n  * @{\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup HAL_Private_Constants HAL Private Constants\r\n  * @{\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n/* Private macros ------------------------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_adc.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of ADC HAL extension module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_ADC_H\r\n#define __STM32F7xx_ADC_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup ADC\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup ADC_Exported_Types ADC Exported Types\r\n  * @{\r\n  */\r\n\r\n/** \r\n  * @brief  Structure definition of ADC and regular group initialization \r\n  * @note   Parameters of this structure are shared within 2 scopes:\r\n  *          - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.\r\n  *          - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.\r\n  * @note   The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.\r\n  *         ADC state can be either:\r\n  *          - For all parameters: ADC disabled\r\n  *          - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.\r\n  *          - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.\r\n  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed\r\n  *         without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly).\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t ClockPrescaler;        /*!< Select ADC clock prescaler. The clock is common for \r\n                                       all the ADCs.\r\n                                       This parameter can be a value of @ref ADC_ClockPrescaler */\r\n  uint32_t Resolution;            /*!< Configures the ADC resolution.\r\n                                       This parameter can be a value of @ref ADC_Resolution */\r\n  uint32_t DataAlign;             /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)\r\n                                       or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).\r\n                                       This parameter can be a value of @ref ADC_Data_Align */\r\n  uint32_t ScanConvMode;          /*!< Configures the sequencer of regular and injected groups.\r\n                                       This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.\r\n                                       If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).\r\n                                                    Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).\r\n                                       If enabled:  Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).\r\n                                                    Scan direction is upward: from rank1 to rank 'n'.\r\n                                       This parameter can be a value of @ref ADC_Scan_mode.\r\n                                       This parameter can be set to ENABLE or DISABLE */\r\n  uint32_t EOCSelection;          /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.\r\n                                       This parameter can be a value of @ref ADC_EOCSelection.\r\n                                       Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.\r\n                                             Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)\r\n                                             or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.\r\n                                       Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).\r\n                                             If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */\r\n  uint32_t ContinuousConvMode;    /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,\r\n                                       after the selected trigger occurred (software start or external trigger).\r\n                                       This parameter can be set to ENABLE or DISABLE. */\r\n  uint32_t NbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the regular group sequencer.\r\n                                       To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.\r\n                                       This parameter must be a number between Min_Data = 1 and Max_Data = 16. */\r\n  uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).\r\n                                       Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.\r\n                                       Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.\r\n                                       This parameter can be set to ENABLE or DISABLE. */\r\n  uint32_t NbrOfDiscConversion;   /*!< Specifies the number of discontinuous conversions in which the  main sequence of regular group (parameter NbrOfConversion) will be subdivided.\r\n                                       If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.\r\n                                       This parameter must be a number between Min_Data = 1 and Max_Data = 8. */\r\n  uint32_t ExternalTrigConv;      /*!< Selects the external event used to trigger the conversion start of regular group.\r\n                                       If set to ADC_SOFTWARE_START, external triggers are disabled.\r\n                                       If set to external trigger source, triggering is on event rising edge by default.\r\n                                       This parameter can be a value of @ref ADC_External_trigger_Source_Regular */\r\n  uint32_t ExternalTrigConvEdge;  /*!< Selects the external trigger edge of regular group.\r\n                                       If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.\r\n                                       This parameter can be a value of @ref ADC_External_trigger_edge_Regular */\r\n  uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)\r\n                                       or in Continuous mode (DMA transfer unlimited, whatever number of conversions).\r\n                                       Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.\r\n                                       Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).\r\n                                       This parameter can be set to ENABLE or DISABLE. */\r\n}ADC_InitTypeDef;\r\n\r\n\r\n\r\n/** \r\n  * @brief  Structure definition of ADC channel for regular group   \r\n  * @note   The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.\r\n  *         ADC can be either disabled or enabled without conversion on going on regular group.\r\n  */ \r\ntypedef struct \r\n{\r\n  uint32_t Channel;                /*!< Specifies the channel to configure into ADC regular group.\r\n                                        This parameter can be a value of @ref ADC_channels */\r\n  uint32_t Rank;                   /*!< Specifies the rank in the regular group sequencer.\r\n                                        This parameter must be a number between Min_Data = 1 and Max_Data = 16 \r\n                                        This parameter can be a value of @ref ADC_regular_rank */\r\n  uint32_t SamplingTime;           /*!< Sampling time value to be set for the selected channel.\r\n                                        Unit: ADC clock cycles\r\n                                        Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).\r\n                                        This parameter can be a value of @ref ADC_sampling_times\r\n                                        Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.\r\n                                                 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.\r\n                                        Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),\r\n                                              sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)\r\n                                              Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */\r\n  uint32_t Offset;                 /*!< Reserved for future use, can be set to 0 */\r\n}ADC_ChannelConfTypeDef;\r\n\r\n/** \r\n  * @brief ADC Configuration multi-mode structure definition  \r\n  */ \r\ntypedef struct\r\n{\r\n  uint32_t WatchdogMode;      /*!< Configures the ADC analog watchdog mode.\r\n                                   This parameter can be a value of @ref ADC_analog_watchdog_selection */\r\n  uint32_t HighThreshold;     /*!< Configures the ADC analog watchdog High threshold value.\r\n                                   This parameter must be a 12-bit value. */     \r\n  uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog High threshold value.\r\n                                   This parameter must be a 12-bit value. */\r\n  uint32_t Channel;           /*!< Configures ADC channel for the analog watchdog. \r\n                                   This parameter has an effect only if watchdog mode is configured on single channel \r\n                                   This parameter can be a value of @ref ADC_channels */      \r\n  uint32_t ITMode;            /*!< Specifies whether the analog watchdog is configured\r\n                                   is interrupt mode or in polling mode.\r\n                                   This parameter can be set to ENABLE or DISABLE */\r\n  uint32_t WatchdogNumber;    /*!< Reserved for future use, can be set to 0 */\r\n}ADC_AnalogWDGConfTypeDef;\r\n\r\n/** \r\n  * @brief  HAL ADC state machine: ADC states definition (bitfields)\r\n  */ \r\n/* States of ADC global scope */\r\n#define HAL_ADC_STATE_RESET             ((uint32_t)0x00000000U)    /*!< ADC not yet initialized or disabled */\r\n#define HAL_ADC_STATE_READY             ((uint32_t)0x00000001U)    /*!< ADC peripheral ready for use */\r\n#define HAL_ADC_STATE_BUSY_INTERNAL     ((uint32_t)0x00000002U)    /*!< ADC is busy to internal process (initialization, calibration) */\r\n#define HAL_ADC_STATE_TIMEOUT           ((uint32_t)0x00000004U)    /*!< TimeOut occurrence */\r\n\r\n/* States of ADC errors */\r\n#define HAL_ADC_STATE_ERROR_INTERNAL    ((uint32_t)0x00000010U)    /*!< Internal error occurrence */\r\n#define HAL_ADC_STATE_ERROR_CONFIG      ((uint32_t)0x00000020U)    /*!< Configuration error occurrence */\r\n#define HAL_ADC_STATE_ERROR_DMA         ((uint32_t)0x00000040U)    /*!< DMA error occurrence */\r\n\r\n/* States of ADC group regular */\r\n#define HAL_ADC_STATE_REG_BUSY          ((uint32_t)0x00000100U)    /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,\r\n                                                                       external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */\r\n#define HAL_ADC_STATE_REG_EOC           ((uint32_t)0x00000200U)    /*!< Conversion data available on group regular */\r\n#define HAL_ADC_STATE_REG_OVR           ((uint32_t)0x00000400U)    /*!< Overrun occurrence */\r\n\r\n/* States of ADC group injected */\r\n#define HAL_ADC_STATE_INJ_BUSY          ((uint32_t)0x00001000U)    /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,\r\n                                                                       external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */\r\n#define HAL_ADC_STATE_INJ_EOC           ((uint32_t)0x00002000U)    /*!< Conversion data available on group injected */\r\n\r\n/* States of ADC analog watchdogs */\r\n#define HAL_ADC_STATE_AWD1              ((uint32_t)0x00010000U)    /*!< Out-of-window occurrence of analog watchdog 1 */\r\n#define HAL_ADC_STATE_AWD2              ((uint32_t)0x00020000U)    /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 2 */\r\n#define HAL_ADC_STATE_AWD3              ((uint32_t)0x00040000U)    /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 3 */\r\n\r\n/* States of ADC multi-mode */\r\n#define HAL_ADC_STATE_MULTIMODE_SLAVE   ((uint32_t)0x00100000U)    /*!< Not available on STM32F7 device: ADC in multimode slave state, controlled by another ADC master ( */\r\n\r\n\r\n/** \r\n  * @brief  ADC handle Structure definition\r\n  */ \r\ntypedef struct\r\n{\r\n  ADC_TypeDef                   *Instance;                   /*!< Register base address */\r\n\r\n  ADC_InitTypeDef               Init;                        /*!< ADC required parameters */\r\n\r\n  __IO uint32_t                 NbrOfCurrentConversionRank;  /*!< ADC number of current conversion rank */\r\n\r\n  DMA_HandleTypeDef             *DMA_Handle;                 /*!< Pointer DMA Handler */\r\n\r\n  HAL_LockTypeDef               Lock;                        /*!< ADC locking object */\r\n\r\n  __IO uint32_t                 State;                       /*!< ADC communication state */\r\n\r\n  __IO uint32_t                 ErrorCode;                   /*!< ADC Error code */\r\n}ADC_HandleTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup ADC_Exported_Constants ADC Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup ADC_Error_Code ADC Error Code\r\n  * @{\r\n  */\r\n#define HAL_ADC_ERROR_NONE        ((uint32_t)0x00U)   /*!< No error                                              */\r\n#define HAL_ADC_ERROR_INTERNAL    ((uint32_t)0x01U)   /*!< ADC IP internal error: if problem of clocking, \r\n                                                          enable/disable, erroneous state                       */\r\n#define HAL_ADC_ERROR_OVR         ((uint32_t)0x02U)   /*!< Overrun error                                         */\r\n#define HAL_ADC_ERROR_DMA         ((uint32_t)0x04U)   /*!< DMA transfer error                                    */\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup ADC_ClockPrescaler  ADC Clock Prescaler\r\n  * @{\r\n  */ \r\n#define ADC_CLOCK_SYNC_PCLK_DIV2    ((uint32_t)0x00000000U)\r\n#define ADC_CLOCK_SYNC_PCLK_DIV4    ((uint32_t)ADC_CCR_ADCPRE_0)\r\n#define ADC_CLOCK_SYNC_PCLK_DIV6    ((uint32_t)ADC_CCR_ADCPRE_1)\r\n#define ADC_CLOCK_SYNC_PCLK_DIV8    ((uint32_t)ADC_CCR_ADCPRE)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases\r\n  * @{\r\n  */ \r\n#define ADC_TWOSAMPLINGDELAY_5CYCLES    ((uint32_t)0x00000000U)\r\n#define ADC_TWOSAMPLINGDELAY_6CYCLES    ((uint32_t)ADC_CCR_DELAY_0)\r\n#define ADC_TWOSAMPLINGDELAY_7CYCLES    ((uint32_t)ADC_CCR_DELAY_1)\r\n#define ADC_TWOSAMPLINGDELAY_8CYCLES    ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))\r\n#define ADC_TWOSAMPLINGDELAY_9CYCLES    ((uint32_t)ADC_CCR_DELAY_2)\r\n#define ADC_TWOSAMPLINGDELAY_10CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))\r\n#define ADC_TWOSAMPLINGDELAY_11CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))\r\n#define ADC_TWOSAMPLINGDELAY_12CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))\r\n#define ADC_TWOSAMPLINGDELAY_13CYCLES   ((uint32_t)ADC_CCR_DELAY_3)\r\n#define ADC_TWOSAMPLINGDELAY_14CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))\r\n#define ADC_TWOSAMPLINGDELAY_15CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))\r\n#define ADC_TWOSAMPLINGDELAY_16CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))\r\n#define ADC_TWOSAMPLINGDELAY_17CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))\r\n#define ADC_TWOSAMPLINGDELAY_18CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))\r\n#define ADC_TWOSAMPLINGDELAY_19CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))\r\n#define ADC_TWOSAMPLINGDELAY_20CYCLES   ((uint32_t)ADC_CCR_DELAY)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup ADC_Resolution ADC Resolution\r\n  * @{\r\n  */ \r\n#define ADC_RESOLUTION_12B  ((uint32_t)0x00000000U)\r\n#define ADC_RESOLUTION_10B  ((uint32_t)ADC_CR1_RES_0)\r\n#define ADC_RESOLUTION_8B   ((uint32_t)ADC_CR1_RES_1)\r\n#define ADC_RESOLUTION_6B   ((uint32_t)ADC_CR1_RES)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular\r\n  * @{\r\n  */ \r\n#define ADC_EXTERNALTRIGCONVEDGE_NONE           ((uint32_t)0x00000000U)\r\n#define ADC_EXTERNALTRIGCONVEDGE_RISING         ((uint32_t)ADC_CR2_EXTEN_0)\r\n#define ADC_EXTERNALTRIGCONVEDGE_FALLING        ((uint32_t)ADC_CR2_EXTEN_1)\r\n#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CR2_EXTEN)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular\r\n  * @{\r\n  */\r\n/* Note: Parameter ADC_SOFTWARE_START is a software parameter used for        */\r\n/*       compatibility with other STM32 devices.                              */\r\n\r\n\r\n#define ADC_EXTERNALTRIGCONV_T1_CC1    ((uint32_t)0x00000000U)\r\n#define ADC_EXTERNALTRIGCONV_T1_CC2    ((uint32_t)ADC_CR2_EXTSEL_0)\r\n#define ADC_EXTERNALTRIGCONV_T1_CC3    ((uint32_t)ADC_CR2_EXTSEL_1)\r\n#define ADC_EXTERNALTRIGCONV_T2_CC2    ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))\r\n#define ADC_EXTERNALTRIGCONV_T5_TRGO   ((uint32_t)ADC_CR2_EXTSEL_2)\r\n#define ADC_EXTERNALTRIGCONV_T4_CC4    ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))\r\n#define ADC_EXTERNALTRIGCONV_T3_CC4    ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))\r\n#define ADC_EXTERNALTRIGCONV_T8_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))\r\n#define ADC_EXTERNALTRIGCONV_T8_TRGO2  ((uint32_t)ADC_CR2_EXTSEL_3)\r\n#define ADC_EXTERNALTRIGCONV_T1_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))\r\n#define ADC_EXTERNALTRIGCONV_T1_TRGO2  ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))\r\n#define ADC_EXTERNALTRIGCONV_T2_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))\r\n#define ADC_EXTERNALTRIGCONV_T4_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))\r\n#define ADC_EXTERNALTRIGCONV_T6_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))\r\n\r\n#define ADC_EXTERNALTRIGCONV_EXT_IT11  ((uint32_t)ADC_CR2_EXTSEL)\r\n#define ADC_SOFTWARE_START             ((uint32_t)ADC_CR2_EXTSEL + 1)\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup ADC_Data_Align ADC Data Align\r\n  * @{\r\n  */ \r\n#define ADC_DATAALIGN_RIGHT      ((uint32_t)0x00000000U)\r\n#define ADC_DATAALIGN_LEFT       ((uint32_t)ADC_CR2_ALIGN)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup ADC_Scan_mode ADC sequencer scan mode\r\n  * @{\r\n  */\r\n#define ADC_SCAN_DISABLE         ((uint32_t)0x00000000)        /*!< Scan mode disabled */\r\n#define ADC_SCAN_ENABLE          ((uint32_t)0x00000001)        /*!< Scan mode enabled  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ADC_regular_rank ADC group regular sequencer rank\r\n  * @{\r\n  */\r\n#define ADC_REGULAR_RANK_1    ((uint32_t)0x00000001)       /*!< ADC regular conversion rank 1  */\r\n#define ADC_REGULAR_RANK_2    ((uint32_t)0x00000002)       /*!< ADC regular conversion rank 2  */\r\n#define ADC_REGULAR_RANK_3    ((uint32_t)0x00000003)       /*!< ADC regular conversion rank 3  */\r\n#define ADC_REGULAR_RANK_4    ((uint32_t)0x00000004)       /*!< ADC regular conversion rank 4  */\r\n#define ADC_REGULAR_RANK_5    ((uint32_t)0x00000005)       /*!< ADC regular conversion rank 5  */\r\n#define ADC_REGULAR_RANK_6    ((uint32_t)0x00000006)       /*!< ADC regular conversion rank 6  */\r\n#define ADC_REGULAR_RANK_7    ((uint32_t)0x00000007)       /*!< ADC regular conversion rank 7  */\r\n#define ADC_REGULAR_RANK_8    ((uint32_t)0x00000008)       /*!< ADC regular conversion rank 8  */\r\n#define ADC_REGULAR_RANK_9    ((uint32_t)0x00000009)       /*!< ADC regular conversion rank 9  */\r\n#define ADC_REGULAR_RANK_10   ((uint32_t)0x0000000A)       /*!< ADC regular conversion rank 10 */\r\n#define ADC_REGULAR_RANK_11   ((uint32_t)0x0000000B)       /*!< ADC regular conversion rank 11 */\r\n#define ADC_REGULAR_RANK_12   ((uint32_t)0x0000000C)       /*!< ADC regular conversion rank 12 */\r\n#define ADC_REGULAR_RANK_13   ((uint32_t)0x0000000D)       /*!< ADC regular conversion rank 13 */\r\n#define ADC_REGULAR_RANK_14   ((uint32_t)0x0000000E)       /*!< ADC regular conversion rank 14 */\r\n#define ADC_REGULAR_RANK_15   ((uint32_t)0x0000000F)       /*!< ADC regular conversion rank 15 */\r\n#define ADC_REGULAR_RANK_16   ((uint32_t)0x00000010)       /*!< ADC regular conversion rank 16 */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ADC_channels ADC Common Channels\r\n  * @{\r\n  */ \r\n#define ADC_CHANNEL_0           ((uint32_t)0x00000000U)\r\n#define ADC_CHANNEL_1           ((uint32_t)ADC_CR1_AWDCH_0)\r\n#define ADC_CHANNEL_2           ((uint32_t)ADC_CR1_AWDCH_1)\r\n#define ADC_CHANNEL_3           ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))\r\n#define ADC_CHANNEL_4           ((uint32_t)ADC_CR1_AWDCH_2)\r\n#define ADC_CHANNEL_5           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))\r\n#define ADC_CHANNEL_6           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))\r\n#define ADC_CHANNEL_7           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))\r\n#define ADC_CHANNEL_8           ((uint32_t)ADC_CR1_AWDCH_3)\r\n#define ADC_CHANNEL_9           ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))\r\n#define ADC_CHANNEL_10          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))\r\n#define ADC_CHANNEL_11          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))\r\n#define ADC_CHANNEL_12          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))\r\n#define ADC_CHANNEL_13          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))\r\n#define ADC_CHANNEL_14          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))\r\n#define ADC_CHANNEL_15          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))\r\n#define ADC_CHANNEL_16          ((uint32_t)ADC_CR1_AWDCH_4)\r\n#define ADC_CHANNEL_17          ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))\r\n#define ADC_CHANNEL_18          ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))\r\n\r\n#define ADC_CHANNEL_VREFINT     ((uint32_t)ADC_CHANNEL_17)\r\n#define ADC_CHANNEL_VBAT        ((uint32_t)ADC_CHANNEL_18)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup ADC_sampling_times ADC Sampling Times\r\n  * @{\r\n  */ \r\n#define ADC_SAMPLETIME_3CYCLES    ((uint32_t)0x00000000U)\r\n#define ADC_SAMPLETIME_15CYCLES   ((uint32_t)ADC_SMPR1_SMP10_0)\r\n#define ADC_SAMPLETIME_28CYCLES   ((uint32_t)ADC_SMPR1_SMP10_1)\r\n#define ADC_SAMPLETIME_56CYCLES   ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))\r\n#define ADC_SAMPLETIME_84CYCLES   ((uint32_t)ADC_SMPR1_SMP10_2)\r\n#define ADC_SAMPLETIME_112CYCLES  ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))\r\n#define ADC_SAMPLETIME_144CYCLES  ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))\r\n#define ADC_SAMPLETIME_480CYCLES  ((uint32_t)ADC_SMPR1_SMP10)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n  /** @defgroup ADC_EOCSelection ADC EOC Selection\r\n  * @{\r\n  */ \r\n#define ADC_EOC_SEQ_CONV              ((uint32_t)0x00000000U)\r\n#define ADC_EOC_SINGLE_CONV           ((uint32_t)0x00000001U)\r\n#define ADC_EOC_SINGLE_SEQ_CONV       ((uint32_t)0x00000002U)  /*!< reserved for future use */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup ADC_Event_type ADC Event Type\r\n  * @{\r\n  */ \r\n#define ADC_AWD_EVENT             ((uint32_t)ADC_FLAG_AWD)\r\n#define ADC_OVR_EVENT             ((uint32_t)ADC_FLAG_OVR)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection\r\n  * @{\r\n  */ \r\n#define ADC_ANALOGWATCHDOG_SINGLE_REG         ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))\r\n#define ADC_ANALOGWATCHDOG_SINGLE_INJEC       ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))\r\n#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC    ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))\r\n#define ADC_ANALOGWATCHDOG_ALL_REG            ((uint32_t)ADC_CR1_AWDEN)\r\n#define ADC_ANALOGWATCHDOG_ALL_INJEC          ((uint32_t)ADC_CR1_JAWDEN)\r\n#define ADC_ANALOGWATCHDOG_ALL_REGINJEC       ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))\r\n#define ADC_ANALOGWATCHDOG_NONE               ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */ \r\n    \r\n/** @defgroup ADC_interrupts_definition ADC Interrupts Definition\r\n  * @{\r\n  */ \r\n#define ADC_IT_EOC      ((uint32_t)ADC_CR1_EOCIE)  \r\n#define ADC_IT_AWD      ((uint32_t)ADC_CR1_AWDIE) \r\n#define ADC_IT_JEOC     ((uint32_t)ADC_CR1_JEOCIE)\r\n#define ADC_IT_OVR      ((uint32_t)ADC_CR1_OVRIE) \r\n/**\r\n  * @}\r\n  */ \r\n    \r\n/** @defgroup ADC_flags_definition ADC Flags Definition\r\n  * @{\r\n  */ \r\n#define ADC_FLAG_AWD    ((uint32_t)ADC_SR_AWD)\r\n#define ADC_FLAG_EOC    ((uint32_t)ADC_SR_EOC)\r\n#define ADC_FLAG_JEOC   ((uint32_t)ADC_SR_JEOC)\r\n#define ADC_FLAG_JSTRT  ((uint32_t)ADC_SR_JSTRT)\r\n#define ADC_FLAG_STRT   ((uint32_t)ADC_SR_STRT)\r\n#define ADC_FLAG_OVR    ((uint32_t)ADC_SR_OVR)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup ADC_channels_type ADC Channels Type\r\n  * @{\r\n  */ \r\n#define ADC_ALL_CHANNELS      ((uint32_t)0x00000001U)\r\n#define ADC_REGULAR_CHANNELS  ((uint32_t)0x00000002U) /*!< reserved for future use */\r\n#define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003U) /*!< reserved for future use */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup ADC_Exported_Macros ADC Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief Reset ADC handle state\r\n  * @param  __HANDLE__ ADC handle\r\n  * @retval None\r\n  */\r\n#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)\r\n\r\n/**\r\n  * @brief  Enable the ADC peripheral.\r\n  * @param  __HANDLE__ ADC handle\r\n  * @retval None\r\n  */\r\n#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |=  ADC_CR2_ADON)\r\n\r\n/**\r\n  * @brief  Disable the ADC peripheral.\r\n  * @param  __HANDLE__ ADC handle\r\n  * @retval None\r\n  */\r\n#define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &=  ~ADC_CR2_ADON)\r\n\r\n/**\r\n  * @brief  Enable the ADC end of conversion interrupt.\r\n  * @param  __HANDLE__ specifies the ADC Handle.\r\n  * @param  __INTERRUPT__ ADC Interrupt.\r\n  * @retval None\r\n  */\r\n#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disable the ADC end of conversion interrupt.\r\n  * @param  __HANDLE__ specifies the ADC Handle.\r\n  * @param  __INTERRUPT__ ADC interrupt.\r\n  * @retval None\r\n  */\r\n#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))\r\n\r\n/** @brief  Check if the specified ADC interrupt source is enabled or disabled.\r\n  * @param  __HANDLE__ specifies the ADC Handle.\r\n  * @param  __INTERRUPT__ specifies the ADC interrupt source to check.\r\n  * @retval The new state of __IT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Clear the ADC's pending flags.\r\n  * @param  __HANDLE__ specifies the ADC Handle.\r\n  * @param  __FLAG__ ADC flag.\r\n  * @retval None\r\n  */\r\n#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))\r\n\r\n/**\r\n  * @brief  Get the selected ADC's flag status.\r\n  * @param  __HANDLE__ specifies the ADC Handle.\r\n  * @param  __FLAG__ ADC flag.\r\n  * @retval None\r\n  */\r\n#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Include ADC HAL Extension module */\r\n#include \"stm32f7xx_hal_adc_ex.h\"\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup ADC_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup ADC_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n/* Initialization/de-initialization functions ***********************************/\r\nHAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);\r\nHAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);\r\nvoid       HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);\r\nvoid       HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup ADC_Exported_Functions_Group2\r\n  * @{\r\n  */\r\n/* I/O operation functions ******************************************************/\r\nHAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);\r\nHAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);\r\nHAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);\r\n\r\nHAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);\r\n\r\nHAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);\r\nHAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);\r\n\r\nvoid              HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);\r\n\r\nHAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);\r\nHAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);\r\n\r\nuint32_t          HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);\r\n\r\nvoid       HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);\r\nvoid       HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);\r\nvoid       HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);\r\nvoid       HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup ADC_Exported_Functions_Group3\r\n  * @{\r\n  */\r\n/* Peripheral Control functions *************************************************/\r\nHAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);\r\nHAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup ADC_Exported_Functions_Group4\r\n  * @{\r\n  */\r\n/* Peripheral State functions ***************************************************/\r\nuint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);\r\nuint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup ADC_Private_Constants ADC Private Constants\r\n  * @{\r\n  */\r\n/* Delay for ADC stabilization time.                                        */\r\n/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB).       */\r\n/* Unit: us                                                                 */\r\n#define ADC_STAB_DELAY_US               ((uint32_t) 3U)\r\n/* Delay for temperature sensor stabilization time.                         */\r\n/* Maximum delay is 10us (refer to device datasheet, parameter tSTART).     */\r\n/* Unit: us                                                                 */\r\n#define ADC_TEMPSENSOR_DELAY_US         ((uint32_t) 10U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup ADC_Private_Macros ADC Private Macros\r\n  * @{\r\n  */\r\n/* Macro reserved for internal HAL driver usage, not intended to be used in\r\n   code of final user */\r\n\r\n/**\r\n  * @brief Verification of ADC state: enabled or disabled\r\n  * @param __HANDLE__ ADC handle\r\n  * @retval SET (ADC enabled) or RESET (ADC disabled)\r\n  */\r\n#define ADC_IS_ENABLE(__HANDLE__)                                              \\\r\n  ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS )            \\\r\n  ) ? SET : RESET)\r\n\r\n/**\r\n  * @brief Test if conversion trigger of regular group is software start\r\n  *        or external trigger.\r\n  * @param __HANDLE__ ADC handle\r\n  * @retval SET (software start) or RESET (external trigger)\r\n  */\r\n#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__)                              \\\r\n  (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)\r\n\r\n/**\r\n  * @brief Test if conversion trigger of injected group is software start\r\n  *        or external trigger.\r\n  * @param __HANDLE__ ADC handle\r\n  * @retval SET (software start) or RESET (external trigger)\r\n  */\r\n#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)                             \\\r\n  (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)\r\n\r\n/**\r\n  * @brief Simultaneously clears and sets specific bits of the handle State\r\n  * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),\r\n  *        the first parameter is the ADC handle State, the second parameter is the\r\n  *        bit field to clear, the third and last parameter is the bit field to set.\r\n  * @retval None\r\n  */\r\n#define ADC_STATE_CLR_SET MODIFY_REG\r\n\r\n/**\r\n  * @brief Clear ADC error code (set it to error code: \"no error\")\r\n  * @param __HANDLE__ ADC handle\r\n  * @retval None\r\n  */\r\n#define ADC_CLEAR_ERRORCODE(__HANDLE__)                                        \\\r\n  ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)\r\n#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__)     (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \\\r\n                                                  ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \\\r\n                                                  ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV6) || \\\r\n                                                  ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV8))\r\n#define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES)  || \\\r\n                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES)  || \\\r\n                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES)  || \\\r\n                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES)  || \\\r\n                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES)  || \\\r\n                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \\\r\n                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \\\r\n                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \\\r\n                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \\\r\n                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \\\r\n                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \\\r\n                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \\\r\n                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \\\r\n                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \\\r\n                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \\\r\n                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_20CYCLES))\r\n#define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \\\r\n                                           ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \\\r\n                                           ((__RESOLUTION__) == ADC_RESOLUTION_8B)  || \\\r\n                                           ((__RESOLUTION__) == ADC_RESOLUTION_6B))\t\t\t\r\n#define IS_ADC_EXT_TRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE)    || \\\r\n                                        ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING)  || \\\r\n                                        ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \\\r\n                                        ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))\r\n#define IS_ADC_EXT_TRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC1)   || \\\r\n                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC2)   || \\\r\n                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC3)   || \\\r\n                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_CC2)   || \\\r\n                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T5_TRGO)  || \\\r\n                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_CC4)   || \\\r\n                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T3_CC4) || \\\r\n                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO)  || \\\r\n                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \\\r\n                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO)  || \\\r\n                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \\\r\n                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_TRGO)  || \\\r\n                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_TRGO)  || \\\r\n                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T6_TRGO)  || \\\r\n                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \\\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((__REGTRIG__) == ADC_SOFTWARE_START))\r\n#define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \\\r\n                                      ((__ALIGN__) == ADC_DATAALIGN_LEFT))\r\n\t\t\r\n                                      \t\t\t\t\t\t\t\t\t\r\n#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_3CYCLES)   || \\\r\n                                      ((__TIME__) == ADC_SAMPLETIME_15CYCLES)  || \\\r\n                                      ((__TIME__) == ADC_SAMPLETIME_28CYCLES)  || \\\r\n                                      ((__TIME__) == ADC_SAMPLETIME_56CYCLES)  || \\\r\n                                      ((__TIME__) == ADC_SAMPLETIME_84CYCLES)  || \\\r\n                                      ((__TIME__) == ADC_SAMPLETIME_112CYCLES) || \\\r\n                                      ((__TIME__) == ADC_SAMPLETIME_144CYCLES) || \\\r\n                                      ((__TIME__) == ADC_SAMPLETIME_480CYCLES))\t\r\n#define IS_ADC_EOCSelection(__EOCSelection__) (((__EOCSelection__) == ADC_EOC_SINGLE_CONV)   || \\\r\n                                               ((__EOCSelection__) == ADC_EOC_SEQ_CONV)  || \\\r\n                                               ((__EOCSelection__) == ADC_EOC_SINGLE_SEQ_CONV))\t\r\n#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_AWD_EVENT) || \\\r\n                                      ((__EVENT__) == ADC_OVR_EVENT))\t\t\r\n#define IS_ADC_ANALOG_WATCHDOG(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REG)        || \\\r\n                                              ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)      || \\\r\n                                              ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)   || \\\r\n                                              ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REG)           || \\\r\n                                              ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_INJEC)         || \\\r\n                                              ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)      || \\\r\n                                              ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_NONE))\r\n#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \\\r\n                                            ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \\\r\n                                            ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))\r\n\r\n#define IS_ADC_REGULAR_RANK(__RANK__) (((__RANK__) == ADC_REGULAR_RANK_1 ) || \\\r\n                                       ((__RANK__) == ADC_REGULAR_RANK_2 ) || \\\r\n                                       ((__RANK__) == ADC_REGULAR_RANK_3 ) || \\\r\n                                       ((__RANK__) == ADC_REGULAR_RANK_4 ) || \\\r\n                                       ((__RANK__) == ADC_REGULAR_RANK_5 ) || \\\r\n                                       ((__RANK__) == ADC_REGULAR_RANK_6 ) || \\\r\n                                       ((__RANK__) == ADC_REGULAR_RANK_7 ) || \\\r\n                                       ((__RANK__) == ADC_REGULAR_RANK_8 ) || \\\r\n                                       ((__RANK__) == ADC_REGULAR_RANK_9 ) || \\\r\n                                       ((__RANK__) == ADC_REGULAR_RANK_10) || \\\r\n                                       ((__RANK__) == ADC_REGULAR_RANK_11) || \\\r\n                                       ((__RANK__) == ADC_REGULAR_RANK_12) || \\\r\n                                       ((__RANK__) == ADC_REGULAR_RANK_13) || \\\r\n                                       ((__RANK__) == ADC_REGULAR_RANK_14) || \\\r\n                                       ((__RANK__) == ADC_REGULAR_RANK_15) || \\\r\n                                       ((__RANK__) == ADC_REGULAR_RANK_16))\r\n\r\n#define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \\\r\n                                         ((__SCAN_MODE__) == ADC_SCAN_ENABLE))\r\n\r\n#define IS_ADC_THRESHOLD(__THRESHOLD__) ((__THRESHOLD__) <= ((uint32_t)0xFFF))\r\n#define IS_ADC_REGULAR_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16)))\r\n#define IS_ADC_REGULAR_DISC_NUMBER(__NUMBER__) (((__NUMBER__) >= ((uint32_t)1)) && ((__NUMBER__) <= ((uint32_t)8)))\r\n#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__)                                     \\\r\n   ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= ((uint32_t)0x0FFF))) || \\\r\n    (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= ((uint32_t)0x03FF))) || \\\r\n    (((__RESOLUTION__) == ADC_RESOLUTION_8B)  && ((__ADC_VALUE__) <= ((uint32_t)0x00FF))) || \\\r\n    (((__RESOLUTION__) == ADC_RESOLUTION_6B)  && ((__ADC_VALUE__) <= ((uint32_t)0x003F))))\r\n\r\n/**\r\n  * @brief  Set ADC Regular channel sequence length.\r\n  * @param  _NbrOfConversion_ Regular channel sequence length. \r\n  * @retval None\r\n  */\r\n#define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20)\r\n\r\n/**\r\n  * @brief  Set the ADC's sample time for channel numbers between 10 and 18.\r\n  * @param  _SAMPLETIME_ Sample time parameter.\r\n  * @param  _CHANNELNB_ Channel number.  \r\n  * @retval None\r\n  */\r\n#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10)))\r\n\r\n/**\r\n  * @brief  Set the ADC's sample time for channel numbers between 0 and 9.\r\n  * @param  _SAMPLETIME_ Sample time parameter.\r\n  * @param  _CHANNELNB_ Channel number.  \r\n  * @retval None\r\n  */\r\n#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((uint32_t)((uint16_t)(_CHANNELNB_)))))\r\n\r\n/**\r\n  * @brief  Set the selected regular channel rank for rank between 1 and 6.\r\n  * @param  _CHANNELNB_ Channel number.\r\n  * @param  _RANKNB_ Rank number.    \r\n  * @retval None\r\n  */\r\n#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 1)))\r\n\r\n/**\r\n  * @brief  Set the selected regular channel rank for rank between 7 and 12.\r\n  * @param  _CHANNELNB_ Channel number.\r\n  * @param  _RANKNB_ Rank number.    \r\n  * @retval None\r\n  */\r\n#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 7)))\r\n\r\n/**\r\n  * @brief  Set the selected regular channel rank for rank between 13 and 16.\r\n  * @param  _CHANNELNB_ Channel number.\r\n  * @param  _RANKNB_ Rank number.    \r\n  * @retval None\r\n  */\r\n#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 13)))\r\n\r\n/**\r\n  * @brief  Enable ADC continuous conversion mode.\r\n  * @param  _CONTINUOUS_MODE_ Continuous mode.\r\n  * @retval None\r\n  */\r\n#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1)\r\n\r\n/**\r\n  * @brief  Configures the number of discontinuous conversions for the regular group channels.\r\n  * @param  _NBR_DISCONTINUOUSCONV_ Number of discontinuous conversions.\r\n  * @retval None\r\n  */\r\n#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << ADC_CR1_DISCNUM_Pos)\r\n\r\n/**\r\n  * @brief  Enable ADC scan mode.\r\n  * @param  _SCANCONV_MODE_ Scan conversion mode.\r\n  * @retval None\r\n  */\r\n#define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8)\r\n\r\n/**\r\n  * @brief  Enable the ADC end of conversion selection.\r\n  * @param  _EOCSelection_MODE_ End of conversion selection mode.\r\n  * @retval None\r\n  */\r\n#define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10)\r\n\r\n/**\r\n  * @brief  Enable the ADC DMA continuous request.\r\n  * @param  _DMAContReq_MODE_ DMA continuous request mode.\r\n  * @retval None\r\n  */\r\n#define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9)\r\n\r\n/**\r\n  * @brief Return resolution bits in CR1 register.\r\n  * @param __HANDLE__ ADC handle\r\n  * @retval None\r\n  */\r\n#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\r\n/**\r\n  * @}\r\n  */\r\n\t\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup ADC_Private_Functions ADC Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\t\r\n/**\r\n  * @}\r\n  */\r\n\t\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /*__STM32F7xx_ADC_H */\r\n\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_adc.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of ADC HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_ADC_EX_H\r\n#define __STM32F7xx_ADC_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup ADCEx\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup ADCEx_Exported_Types ADC Exported Types\r\n  * @{\r\n  */\r\n   \r\n/** \r\n  * @brief  ADC Configuration injected Channel structure definition\r\n  * @note   Parameters of this structure are shared within 2 scopes:\r\n  *          - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset\r\n  *          - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,\r\n  *            AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.\r\n  * @note   The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.\r\n  *         ADC state can be either:\r\n  *          - For all parameters: ADC disabled\r\n  *          - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group.\r\n  *          - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group.\r\n  */\r\ntypedef struct \r\n{\r\n  uint32_t InjectedChannel;               /*!< Selection of ADC channel to configure\r\n                                               This parameter can be a value of @ref ADC_channels\r\n                                               Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */\r\n  uint32_t InjectedRank;                  /*!< Rank in the injected group sequencer\r\n                                               This parameter must be a value of @ref ADCEx_injected_rank\r\n                                               Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */\r\n  uint32_t InjectedSamplingTime;          /*!< Sampling time value to be set for the selected channel.\r\n                                               Unit: ADC clock cycles\r\n                                               Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).\r\n                                               This parameter can be a value of @ref ADC_sampling_times\r\n                                               Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.\r\n                                                        If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.\r\n                                               Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),\r\n                                                     sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)\r\n                                                     Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */\r\n  uint32_t InjectedOffset;                /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).\r\n                                               Offset value must be a positive number.\r\n                                               Depending of ADC resolution selected (12, 10, 8 or 6 bits),\r\n                                               this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */\r\n  uint32_t InjectedNbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the injected group sequencer.\r\n                                               To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.\r\n                                               This parameter must be a number between Min_Data = 1 and Max_Data = 4.\r\n                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to \r\n                                                        configure a channel on injected group can impact the configuration of other channels previously set. */\r\n  uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).\r\n                                               Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.\r\n                                               Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.\r\n                                               This parameter can be set to ENABLE or DISABLE.\r\n                                               Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.\r\n                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to \r\n                                                        configure a channel on injected group can impact the configuration of other channels previously set. */\r\n  uint32_t AutoInjectedConv;              /*!< Enables or disables the selected ADC automatic injected group conversion after regular one\r\n                                               This parameter can be set to ENABLE or DISABLE.      \r\n                                               Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)\r\n                                               Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)\r\n                                               Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.\r\n                                                     To maintain JAUTO always enabled, DMA must be configured in circular mode.\r\n                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to\r\n                                                        configure a channel on injected group can impact the configuration of other channels previously set. */\r\n  uint32_t ExternalTrigInjecConv;         /*!< Selects the external event used to trigger the conversion start of injected group.\r\n                                               If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.\r\n                                               If set to external trigger source, triggering is on event rising edge.\r\n                                               This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected\r\n                                               Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).\r\n                                                     If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)\r\n                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to\r\n                                                        configure a channel on injected group can impact the configuration of other channels previously set. */\r\n  uint32_t ExternalTrigInjecConvEdge;     /*!< Selects the external trigger edge of injected group.\r\n                                               This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected.\r\n                                               If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.\r\n                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to \r\n                                                        configure a channel on injected group can impact the configuration of other channels previously set. */\r\n}ADC_InjectionConfTypeDef; \r\n\r\n/** \r\n  * @brief ADC Configuration multi-mode structure definition  \r\n  */ \r\ntypedef struct\r\n{\r\n  uint32_t Mode;              /*!< Configures the ADC to operate in independent or multi mode. \r\n                                   This parameter can be a value of @ref ADCEx_Common_mode */\r\n  uint32_t DMAAccessMode;     /*!< Configures the Direct memory access mode for multi ADC mode.\r\n                                   This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multi_mode */\r\n  uint32_t TwoSamplingDelay;  /*!< Configures the Delay between 2 sampling phases.\r\n                                   This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */\r\n}ADC_MultiModeTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup ADCEx_Exported_Constants ADC Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup ADCEx_Common_mode ADC Common Mode\r\n  * @{\r\n  */\r\n#define ADC_MODE_INDEPENDENT                  ((uint32_t)0x00000000U)      \r\n#define ADC_DUALMODE_REGSIMULT_INJECSIMULT    ((uint32_t)ADC_CCR_MULTI_0)\r\n#define ADC_DUALMODE_REGSIMULT_ALTERTRIG      ((uint32_t)ADC_CCR_MULTI_1)\r\n#define ADC_DUALMODE_INJECSIMULT              ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))\r\n#define ADC_DUALMODE_REGSIMULT                ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))\r\n#define ADC_DUALMODE_INTERL                   ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))\r\n#define ADC_DUALMODE_ALTERTRIG                ((uint32_t)(ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))\r\n#define ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT  ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0))\r\n#define ADC_TRIPLEMODE_REGSIMULT_AlterTrig    ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1))\r\n#define ADC_TRIPLEMODE_INJECSIMULT            ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))\r\n#define ADC_TRIPLEMODE_REGSIMULT              ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))\r\n#define ADC_TRIPLEMODE_INTERL                 ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))\r\n#define ADC_TRIPLEMODE_ALTERTRIG              ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode ADC Direct Memory Access Mode For Multi Mode\r\n  * @{\r\n  */ \r\n#define ADC_DMAACCESSMODE_DISABLED  ((uint32_t)0x00000000U)     /*!< DMA mode disabled */\r\n#define ADC_DMAACCESSMODE_1         ((uint32_t)ADC_CCR_DMA_0)  /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/\r\n#define ADC_DMAACCESSMODE_2         ((uint32_t)ADC_CCR_DMA_1)  /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/\r\n#define ADC_DMAACCESSMODE_3         ((uint32_t)ADC_CCR_DMA)    /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup ADCEx_External_trigger_edge_Injected ADC External Trigger Edge Injected\r\n  * @{\r\n  */\r\n#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE           ((uint32_t)0x00000000U)\r\n#define ADC_EXTERNALTRIGINJECCONVEDGE_RISING         ((uint32_t)ADC_CR2_JEXTEN_0)\r\n#define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING        ((uint32_t)ADC_CR2_JEXTEN_1)\r\n#define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CR2_JEXTEN)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup ADCEx_External_trigger_Source_Injected ADC External Trigger Source Injected\r\n  * @{\r\n  */\r\n#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO         ((uint32_t)0x00000000U)\r\n#define ADC_EXTERNALTRIGINJECCONV_T1_CC4          ((uint32_t)ADC_CR2_JEXTSEL_0)\r\n#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO         ((uint32_t)ADC_CR2_JEXTSEL_1)\r\n#define ADC_EXTERNALTRIGINJECCONV_T2_CC1          ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))\r\n#define ADC_EXTERNALTRIGINJECCONV_T3_CC4          ((uint32_t)ADC_CR2_JEXTSEL_2)\r\n#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO         ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))\r\n\r\n#define ADC_EXTERNALTRIGINJECCONV_T8_CC4          ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))\r\n#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2        ((uint32_t)ADC_CR2_JEXTSEL_3)\r\n#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO         ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0))\r\n#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO2        ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1))\r\n#define ADC_EXTERNALTRIGINJECCONV_T3_CC3          ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))\r\n#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO         ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2))\r\n#define ADC_EXTERNALTRIGINJECCONV_T3_CC1          ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))\r\n#define ADC_EXTERNALTRIGINJECCONV_T6_TRGO         ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))\r\n#define ADC_INJECTED_SOFTWARE_START                ((uint32_t)ADC_CR2_JEXTSEL + 1)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup ADCEx_injected_rank ADC Injected Channel Rank\r\n  * @{\r\n  */ \r\n#define ADC_INJECTED_RANK_1    ((uint32_t)0x00000001U)\r\n#define ADC_INJECTED_RANK_2    ((uint32_t)0x00000002U)\r\n#define ADC_INJECTED_RANK_3    ((uint32_t)0x00000003U)\r\n#define ADC_INJECTED_RANK_4    ((uint32_t)0x00000004U)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup ADCEx_channels  ADC Specific Channels\r\n  * @{\r\n  */\r\n#define ADC_CHANNEL_TEMPSENSOR  ((uint32_t)ADC_CHANNEL_18 | 0x10000000U)    \r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup ADC_Exported_Macros ADC Exported Macros\r\n  * @{\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup ADCEx_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup ADCEx_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n\r\n/* I/O operation functions ******************************************************/\r\nHAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);\r\nHAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);\r\nHAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);\r\nHAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);\r\nuint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);\r\nHAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);\r\nHAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc);\r\nuint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc);\r\nvoid HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);\r\n\r\n/* Peripheral Control functions *************************************************/\r\nHAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);\r\nHAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup ADCEx_Private_Constants ADC Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup ADCEx_Private_Macros ADC Private Macros\r\n  * @{\r\n  */\r\n#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18)  || \\\r\n                                 ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR))\r\n                                     \r\n#define IS_ADC_MODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT)                 || \\\r\n                               ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT)   || \\\r\n                               ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG)     || \\\r\n                               ((__MODE__) == ADC_DUALMODE_INJECSIMULT)             || \\\r\n                               ((__MODE__) == ADC_DUALMODE_REGSIMULT)               || \\\r\n                               ((__MODE__) == ADC_DUALMODE_INTERL)                  || \\\r\n                               ((__MODE__) == ADC_DUALMODE_ALTERTRIG)               || \\\r\n                               ((__MODE__) == ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT) || \\\r\n                               ((__MODE__) == ADC_TRIPLEMODE_REGSIMULT_AlterTrig)   || \\\r\n                               ((__MODE__) == ADC_TRIPLEMODE_INJECSIMULT)           || \\\r\n                               ((__MODE__) == ADC_TRIPLEMODE_REGSIMULT)             || \\\r\n                               ((__MODE__) == ADC_TRIPLEMODE_INTERL)                || \\\r\n                               ((__MODE__) == ADC_TRIPLEMODE_ALTERTRIG))\r\n#define IS_ADC_DMA_ACCESS_MODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || \\\r\n                                          ((__MODE__) == ADC_DMAACCESSMODE_1)        || \\\r\n                                          ((__MODE__) == ADC_DMAACCESSMODE_2)        || \\\r\n                                          ((__MODE__) == ADC_DMAACCESSMODE_3))\r\n#define IS_ADC_EXT_INJEC_TRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_NONE)    || \\\r\n                                              ((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_RISING)  || \\\r\n                                              ((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_FALLING) || \\\r\n                                              ((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING))\r\n#define IS_ADC_EXT_INJEC_TRIG(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO)  || \\\r\n                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_CC4)   || \\\r\n                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO)  || \\\r\n                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)   || \\\r\n                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)   || \\\r\n                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO)  || \\\r\n                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4)   || \\\r\n                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \\\r\n                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO)  || \\\r\n                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \\\r\n                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC3)   || \\\r\n                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO)  || \\\r\n                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC1)   || \\\r\n                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO)  || \\\r\n                                            ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START))\r\n#define IS_ADC_INJECTED_RANK(__RANK__) (((__RANK__) == ADC_INJECTED_RANK_1) || \\\r\n                                       ((__RANK__) == ADC_INJECTED_RANK_2) || \\\r\n                                       ((__RANK__) == ADC_INJECTED_RANK_3) || \\\r\n                                       ((__RANK__) == ADC_INJECTED_RANK_4))\r\n#define IS_ADC_INJECTED_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)4)))\r\n\r\n/**\r\n  * @brief  Set the selected injected Channel rank.\r\n  * @param  _CHANNELNB_ Channel number.\r\n  * @param  _RANKNB_ Rank number. \r\n  * @param  _JSQR_JL_ Sequence length.     \r\n  * @retval None\r\n  */\r\n#define   ADC_JSQR(_CHANNELNB_, _RANKNB_,_JSQR_JL_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * (uint8_t)(((_RANKNB_) + 3) - (_JSQR_JL_))))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup ADCEx_Private_Functions ADC Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /*__STM32F7xx_ADC_EX_H */\r\n\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_can.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_can.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of CAN HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef STM32F7xx_HAL_CAN_H\r\n#define STM32F7xx_HAL_CAN_H\r\n\r\n#ifdef __cplusplus\r\nextern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n#if defined (CAN1)\r\n/** @addtogroup CAN\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup CAN_Exported_Types CAN Exported Types\r\n  * @{\r\n  */\r\n/**\r\n  * @brief  HAL State structures definition\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_CAN_STATE_RESET             = 0x00U,  /*!< CAN not yet initialized or disabled */\r\n  HAL_CAN_STATE_READY             = 0x01U,  /*!< CAN initialized and ready for use   */\r\n  HAL_CAN_STATE_LISTENING         = 0x02U,  /*!< CAN receive process is ongoing      */\r\n  HAL_CAN_STATE_SLEEP_PENDING     = 0x03U,  /*!< CAN sleep request is pending        */\r\n  HAL_CAN_STATE_SLEEP_ACTIVE      = 0x04U,  /*!< CAN sleep mode is active            */\r\n  HAL_CAN_STATE_ERROR             = 0x05U   /*!< CAN error state                     */\r\n\r\n} HAL_CAN_StateTypeDef;\r\n\r\n/**\r\n  * @brief  CAN init structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t Prescaler;                  /*!< Specifies the length of a time quantum.\r\n                                            This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */\r\n\r\n  uint32_t Mode;                       /*!< Specifies the CAN operating mode.\r\n                                            This parameter can be a value of @ref CAN_operating_mode */\r\n\r\n  uint32_t SyncJumpWidth;              /*!< Specifies the maximum number of time quanta the CAN hardware\r\n                                            is allowed to lengthen or shorten a bit to perform resynchronization.\r\n                                            This parameter can be a value of @ref CAN_synchronisation_jump_width */\r\n\r\n  uint32_t TimeSeg1;                   /*!< Specifies the number of time quanta in Bit Segment 1.\r\n                                            This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */\r\n\r\n  uint32_t TimeSeg2;                   /*!< Specifies the number of time quanta in Bit Segment 2.\r\n                                            This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */\r\n\r\n  FunctionalState TimeTriggeredMode;   /*!< Enable or disable the time triggered communication mode.\r\n                                            This parameter can be set to ENABLE or DISABLE. */\r\n\r\n  FunctionalState AutoBusOff;          /*!< Enable or disable the automatic bus-off management.\r\n                                            This parameter can be set to ENABLE or DISABLE. */\r\n\r\n  FunctionalState AutoWakeUp;          /*!< Enable or disable the automatic wake-up mode.\r\n                                            This parameter can be set to ENABLE or DISABLE. */\r\n\r\n  FunctionalState AutoRetransmission;  /*!< Enable or disable the non-automatic retransmission mode.\r\n                                            This parameter can be set to ENABLE or DISABLE. */\r\n\r\n  FunctionalState ReceiveFifoLocked;   /*!< Enable or disable the Receive FIFO Locked mode.\r\n                                            This parameter can be set to ENABLE or DISABLE. */\r\n\r\n  FunctionalState TransmitFifoPriority;/*!< Enable or disable the transmit FIFO priority.\r\n                                            This parameter can be set to ENABLE or DISABLE. */\r\n\r\n} CAN_InitTypeDef;\r\n\r\n/**\r\n  * @brief  CAN filter configuration structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t FilterIdHigh;          /*!< Specifies the filter identification number (MSBs for a 32-bit\r\n                                       configuration, first one for a 16-bit configuration).\r\n                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */\r\n\r\n  uint32_t FilterIdLow;           /*!< Specifies the filter identification number (LSBs for a 32-bit\r\n                                       configuration, second one for a 16-bit configuration).\r\n                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */\r\n\r\n  uint32_t FilterMaskIdHigh;      /*!< Specifies the filter mask number or identification number,\r\n                                       according to the mode (MSBs for a 32-bit configuration,\r\n                                       first one for a 16-bit configuration).\r\n                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */\r\n\r\n  uint32_t FilterMaskIdLow;       /*!< Specifies the filter mask number or identification number,\r\n                                       according to the mode (LSBs for a 32-bit configuration,\r\n                                       second one for a 16-bit configuration).\r\n                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */\r\n\r\n  uint32_t FilterFIFOAssignment;  /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter.\r\n                                       This parameter can be a value of @ref CAN_filter_FIFO */\r\n\r\n  uint32_t FilterBank;            /*!< Specifies the filter bank which will be initialized.\r\n                                       For single CAN instance(14 dedicated filter banks),\r\n                                       this parameter must be a number between Min_Data = 0 and Max_Data = 13.\r\n                                       For dual CAN instances(28 filter banks shared),\r\n                                       this parameter must be a number between Min_Data = 0 and Max_Data = 27. */\r\n\r\n  uint32_t FilterMode;            /*!< Specifies the filter mode to be initialized.\r\n                                       This parameter can be a value of @ref CAN_filter_mode */\r\n\r\n  uint32_t FilterScale;           /*!< Specifies the filter scale.\r\n                                       This parameter can be a value of @ref CAN_filter_scale */\r\n\r\n  uint32_t FilterActivation;      /*!< Enable or disable the filter.\r\n                                       This parameter can be set to ENABLE or DISABLE. */\r\n\r\n  uint32_t SlaveStartFilterBank;  /*!< Select the start filter bank for the slave CAN instance.\r\n                                       For single CAN instances, this parameter is meaningless.\r\n                                       For dual CAN instances, all filter banks with lower index are assigned to master\r\n                                       CAN instance, whereas all filter banks with greater index are assigned to slave\r\n                                       CAN instance.\r\n                                       This parameter must be a number between Min_Data = 0 and Max_Data = 27. */\r\n\r\n} CAN_FilterTypeDef;\r\n\r\n/**\r\n  * @brief  CAN Tx message header structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t StdId;    /*!< Specifies the standard identifier.\r\n                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */\r\n\r\n  uint32_t ExtId;    /*!< Specifies the extended identifier.\r\n                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */\r\n\r\n  uint32_t IDE;      /*!< Specifies the type of identifier for the message that will be transmitted.\r\n                          This parameter can be a value of @ref CAN_identifier_type */\r\n\r\n  uint32_t RTR;      /*!< Specifies the type of frame for the message that will be transmitted.\r\n                          This parameter can be a value of @ref CAN_remote_transmission_request */\r\n\r\n  uint32_t DLC;      /*!< Specifies the length of the frame that will be transmitted.\r\n                          This parameter must be a number between Min_Data = 0 and Max_Data = 8. */\r\n\r\n  FunctionalState TransmitGlobalTime; /*!< Specifies whether the timestamp counter value captured on start\r\n                          of frame transmission, is sent in DATA6 and DATA7 replacing pData[6] and pData[7].\r\n                          @note: Time Triggered Communication Mode must be enabled.\r\n                          @note: DLC must be programmed as 8 bytes, in order these 2 bytes are sent.\r\n                          This parameter can be set to ENABLE or DISABLE. */\r\n\r\n} CAN_TxHeaderTypeDef;\r\n\r\n/**\r\n  * @brief  CAN Rx message header structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t StdId;    /*!< Specifies the standard identifier.\r\n                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */\r\n\r\n  uint32_t ExtId;    /*!< Specifies the extended identifier.\r\n                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */\r\n\r\n  uint32_t IDE;      /*!< Specifies the type of identifier for the message that will be transmitted.\r\n                          This parameter can be a value of @ref CAN_identifier_type */\r\n\r\n  uint32_t RTR;      /*!< Specifies the type of frame for the message that will be transmitted.\r\n                          This parameter can be a value of @ref CAN_remote_transmission_request */\r\n\r\n  uint32_t DLC;      /*!< Specifies the length of the frame that will be transmitted.\r\n                          This parameter must be a number between Min_Data = 0 and Max_Data = 8. */\r\n\r\n  uint32_t Timestamp; /*!< Specifies the timestamp counter value captured on start of frame reception.\r\n                          @note: Time Triggered Communication Mode must be enabled.\r\n                          This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF. */\r\n\r\n  uint32_t FilterMatchIndex; /*!< Specifies the index of matching acceptance filter element.\r\n                          This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */\r\n\r\n} CAN_RxHeaderTypeDef;\r\n\r\n/**\r\n  * @brief  CAN handle Structure definition\r\n  */\r\ntypedef struct __CAN_HandleTypeDef\r\n{\r\n  CAN_TypeDef                 *Instance;                 /*!< Register base address */\r\n\r\n  CAN_InitTypeDef             Init;                      /*!< CAN required parameters */\r\n\r\n  __IO HAL_CAN_StateTypeDef   State;                     /*!< CAN communication state */\r\n\r\n  __IO uint32_t               ErrorCode;                 /*!< CAN Error code.\r\n                                                              This parameter can be a value of @ref CAN_Error_Code */\r\n\r\n} CAN_HandleTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup CAN_Exported_Constants CAN Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CAN_Error_Code CAN Error Code\r\n  * @{\r\n  */\r\n#define HAL_CAN_ERROR_NONE            (0x00000000U)  /*!< No error                                             */\r\n#define HAL_CAN_ERROR_EWG             (0x00000001U)  /*!< Protocol Error Warning                               */\r\n#define HAL_CAN_ERROR_EPV             (0x00000002U)  /*!< Error Passive                                        */\r\n#define HAL_CAN_ERROR_BOF             (0x00000004U)  /*!< Bus-off error                                        */\r\n#define HAL_CAN_ERROR_STF             (0x00000008U)  /*!< Stuff error                                          */\r\n#define HAL_CAN_ERROR_FOR             (0x00000010U)  /*!< Form error                                           */\r\n#define HAL_CAN_ERROR_ACK             (0x00000020U)  /*!< Acknowledgment error                                 */\r\n#define HAL_CAN_ERROR_BR              (0x00000040U)  /*!< Bit recessive error                                  */\r\n#define HAL_CAN_ERROR_BD              (0x00000080U)  /*!< Bit dominant error                                   */\r\n#define HAL_CAN_ERROR_CRC             (0x00000100U)  /*!< CRC error                                            */\r\n#define HAL_CAN_ERROR_RX_FOV0         (0x00000200U)  /*!< Rx FIFO0 overrun error                               */\r\n#define HAL_CAN_ERROR_RX_FOV1         (0x00000400U)  /*!< Rx FIFO1 overrun error                               */\r\n#define HAL_CAN_ERROR_TX_ALST0        (0x00000800U)  /*!< TxMailbox 0 transmit failure due to arbitration lost */\r\n#define HAL_CAN_ERROR_TX_TERR0        (0x00001000U)  /*!< TxMailbox 1 transmit failure due to tranmit error    */\r\n#define HAL_CAN_ERROR_TX_ALST1        (0x00002000U)  /*!< TxMailbox 0 transmit failure due to arbitration lost */\r\n#define HAL_CAN_ERROR_TX_TERR1        (0x00004000U)  /*!< TxMailbox 1 transmit failure due to tranmit error    */\r\n#define HAL_CAN_ERROR_TX_ALST2        (0x00008000U)  /*!< TxMailbox 0 transmit failure due to arbitration lost */\r\n#define HAL_CAN_ERROR_TX_TERR2        (0x00010000U)  /*!< TxMailbox 1 transmit failure due to tranmit error    */\r\n#define HAL_CAN_ERROR_TIMEOUT         (0x00020000U)  /*!< Timeout error                                        */\r\n#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U)  /*!< Peripheral not initialized                           */\r\n#define HAL_CAN_ERROR_NOT_READY       (0x00080000U)  /*!< Peripheral not ready                                 */\r\n#define HAL_CAN_ERROR_NOT_STARTED     (0x00100000U)  /*!< Peripheral not started                               */\r\n#define HAL_CAN_ERROR_PARAM           (0x00200000U)  /*!< Parameter error                                      */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CAN_InitStatus CAN InitStatus\r\n  * @{\r\n  */\r\n#define CAN_INITSTATUS_FAILED       (0x00000000U)  /*!< CAN initialization failed */\r\n#define CAN_INITSTATUS_SUCCESS      (0x00000001U)  /*!< CAN initialization OK     */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CAN_operating_mode CAN Operating Mode\r\n  * @{\r\n  */\r\n#define CAN_MODE_NORMAL             (0x00000000U)                              /*!< Normal mode   */\r\n#define CAN_MODE_LOOPBACK           ((uint32_t)CAN_BTR_LBKM)                   /*!< Loopback mode */\r\n#define CAN_MODE_SILENT             ((uint32_t)CAN_BTR_SILM)                   /*!< Silent mode   */\r\n#define CAN_MODE_SILENT_LOOPBACK    ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM))  /*!< Loopback combined with silent mode */\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width\r\n  * @{\r\n  */\r\n#define CAN_SJW_1TQ                 (0x00000000U)              /*!< 1 time quantum */\r\n#define CAN_SJW_2TQ                 ((uint32_t)CAN_BTR_SJW_0)  /*!< 2 time quantum */\r\n#define CAN_SJW_3TQ                 ((uint32_t)CAN_BTR_SJW_1)  /*!< 3 time quantum */\r\n#define CAN_SJW_4TQ                 ((uint32_t)CAN_BTR_SJW)    /*!< 4 time quantum */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1\r\n  * @{\r\n  */\r\n#define CAN_BS1_1TQ                 (0x00000000U)                                                /*!< 1 time quantum  */\r\n#define CAN_BS1_2TQ                 ((uint32_t)CAN_BTR_TS1_0)                                    /*!< 2 time quantum  */\r\n#define CAN_BS1_3TQ                 ((uint32_t)CAN_BTR_TS1_1)                                    /*!< 3 time quantum  */\r\n#define CAN_BS1_4TQ                 ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0))                  /*!< 4 time quantum  */\r\n#define CAN_BS1_5TQ                 ((uint32_t)CAN_BTR_TS1_2)                                    /*!< 5 time quantum  */\r\n#define CAN_BS1_6TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0))                  /*!< 6 time quantum  */\r\n#define CAN_BS1_7TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1))                  /*!< 7 time quantum  */\r\n#define CAN_BS1_8TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 8 time quantum  */\r\n#define CAN_BS1_9TQ                 ((uint32_t)CAN_BTR_TS1_3)                                    /*!< 9 time quantum  */\r\n#define CAN_BS1_10TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0))                  /*!< 10 time quantum */\r\n#define CAN_BS1_11TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1))                  /*!< 11 time quantum */\r\n#define CAN_BS1_12TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 12 time quantum */\r\n#define CAN_BS1_13TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2))                  /*!< 13 time quantum */\r\n#define CAN_BS1_14TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0))  /*!< 14 time quantum */\r\n#define CAN_BS1_15TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1))  /*!< 15 time quantum */\r\n#define CAN_BS1_16TQ                ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2\r\n  * @{\r\n  */\r\n#define CAN_BS2_1TQ                 (0x00000000U)                                /*!< 1 time quantum */\r\n#define CAN_BS2_2TQ                 ((uint32_t)CAN_BTR_TS2_0)                    /*!< 2 time quantum */\r\n#define CAN_BS2_3TQ                 ((uint32_t)CAN_BTR_TS2_1)                    /*!< 3 time quantum */\r\n#define CAN_BS2_4TQ                 ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0))  /*!< 4 time quantum */\r\n#define CAN_BS2_5TQ                 ((uint32_t)CAN_BTR_TS2_2)                    /*!< 5 time quantum */\r\n#define CAN_BS2_6TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0))  /*!< 6 time quantum */\r\n#define CAN_BS2_7TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1))  /*!< 7 time quantum */\r\n#define CAN_BS2_8TQ                 ((uint32_t)CAN_BTR_TS2)                      /*!< 8 time quantum */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CAN_filter_mode CAN Filter Mode\r\n  * @{\r\n  */\r\n#define CAN_FILTERMODE_IDMASK       (0x00000000U)  /*!< Identifier mask mode */\r\n#define CAN_FILTERMODE_IDLIST       (0x00000001U)  /*!< Identifier list mode */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CAN_filter_scale CAN Filter Scale\r\n  * @{\r\n  */\r\n#define CAN_FILTERSCALE_16BIT       (0x00000000U)  /*!< Two 16-bit filters */\r\n#define CAN_FILTERSCALE_32BIT       (0x00000001U)  /*!< One 32-bit filter  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CAN_filter_FIFO CAN Filter FIFO\r\n  * @{\r\n  */\r\n#define CAN_FILTER_FIFO0            (0x00000000U)  /*!< Filter FIFO 0 assignment for filter x */\r\n#define CAN_FILTER_FIFO1            (0x00000001U)  /*!< Filter FIFO 1 assignment for filter x */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CAN_identifier_type CAN Identifier Type\r\n  * @{\r\n  */\r\n#define CAN_ID_STD                  (0x00000000U)  /*!< Standard Id */\r\n#define CAN_ID_EXT                  (0x00000004U)  /*!< Extended Id */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request\r\n  * @{\r\n  */\r\n#define CAN_RTR_DATA                (0x00000000U)  /*!< Data frame   */\r\n#define CAN_RTR_REMOTE              (0x00000002U)  /*!< Remote frame */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number\r\n  * @{\r\n  */\r\n#define CAN_RX_FIFO0                (0x00000000U)  /*!< CAN receive FIFO 0 */\r\n#define CAN_RX_FIFO1                (0x00000001U)  /*!< CAN receive FIFO 1 */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CAN_Tx_Mailboxes CAN Tx Mailboxes\r\n  * @{\r\n  */\r\n#define CAN_TX_MAILBOX0             (0x00000001U)  /*!< Tx Mailbox 0  */\r\n#define CAN_TX_MAILBOX1             (0x00000002U)  /*!< Tx Mailbox 1  */\r\n#define CAN_TX_MAILBOX2             (0x00000004U)  /*!< Tx Mailbox 2  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CAN_flags CAN Flags\r\n  * @{\r\n  */\r\n/* Transmit Flags */\r\n#define CAN_FLAG_RQCP0              (0x00000500U)  /*!< Request complete MailBox 0 flag   */\r\n#define CAN_FLAG_TXOK0              (0x00000501U)  /*!< Transmission OK MailBox 0 flag    */\r\n#define CAN_FLAG_ALST0              (0x00000502U)  /*!< Arbitration Lost MailBox 0 flag   */\r\n#define CAN_FLAG_TERR0              (0x00000503U)  /*!< Transmission error MailBox 0 flag */\r\n#define CAN_FLAG_RQCP1              (0x00000508U)  /*!< Request complete MailBox1 flag    */\r\n#define CAN_FLAG_TXOK1              (0x00000509U)  /*!< Transmission OK MailBox 1 flag    */\r\n#define CAN_FLAG_ALST1              (0x0000050AU)  /*!< Arbitration Lost MailBox 1 flag   */\r\n#define CAN_FLAG_TERR1              (0x0000050BU)  /*!< Transmission error MailBox 1 flag */\r\n#define CAN_FLAG_RQCP2              (0x00000510U)  /*!< Request complete MailBox2 flag    */\r\n#define CAN_FLAG_TXOK2              (0x00000511U)  /*!< Transmission OK MailBox 2 flag    */\r\n#define CAN_FLAG_ALST2              (0x00000512U)  /*!< Arbitration Lost MailBox 2 flag   */\r\n#define CAN_FLAG_TERR2              (0x00000513U)  /*!< Transmission error MailBox 2 flag */\r\n#define CAN_FLAG_TME0               (0x0000051AU)  /*!< Transmit mailbox 0 empty flag     */\r\n#define CAN_FLAG_TME1               (0x0000051BU)  /*!< Transmit mailbox 1 empty flag     */\r\n#define CAN_FLAG_TME2               (0x0000051CU)  /*!< Transmit mailbox 2 empty flag     */\r\n#define CAN_FLAG_LOW0               (0x0000051DU)  /*!< Lowest priority mailbox 0 flag    */\r\n#define CAN_FLAG_LOW1               (0x0000051EU)  /*!< Lowest priority mailbox 1 flag    */\r\n#define CAN_FLAG_LOW2               (0x0000051FU)  /*!< Lowest priority mailbox 2 flag    */\r\n\r\n/* Receive Flags */\r\n#define CAN_FLAG_FF0                (0x00000203U)  /*!< RX FIFO 0 Full flag               */\r\n#define CAN_FLAG_FOV0               (0x00000204U)  /*!< RX FIFO 0 Overrun flag            */\r\n#define CAN_FLAG_FF1                (0x00000403U)  /*!< RX FIFO 1 Full flag               */\r\n#define CAN_FLAG_FOV1               (0x00000404U)  /*!< RX FIFO 1 Overrun flag            */\r\n\r\n/* Operating Mode Flags */\r\n#define CAN_FLAG_INAK               (0x00000100U)  /*!< Initialization acknowledge flag   */\r\n#define CAN_FLAG_SLAK               (0x00000101U)  /*!< Sleep acknowledge flag            */\r\n#define CAN_FLAG_ERRI               (0x00000102U)  /*!< Error flag                        */\r\n#define CAN_FLAG_WKU                (0x00000103U)  /*!< Wake up interrupt flag            */\r\n#define CAN_FLAG_SLAKI              (0x00000104U)  /*!< Sleep acknowledge interrupt flag  */\r\n\r\n/* Error Flags */\r\n#define CAN_FLAG_EWG                (0x00000300U)  /*!< Error warning flag                */\r\n#define CAN_FLAG_EPV                (0x00000301U)  /*!< Error passive flag                */\r\n#define CAN_FLAG_BOF                (0x00000302U)  /*!< Bus-Off flag                      */\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup CAN_Interrupts CAN Interrupts\r\n  * @{\r\n  */\r\n/* Transmit Interrupt */\r\n#define CAN_IT_TX_MAILBOX_EMPTY     ((uint32_t)CAN_IER_TMEIE)   /*!< Transmit mailbox empty interrupt */\r\n\r\n/* Receive Interrupts */\r\n#define CAN_IT_RX_FIFO0_MSG_PENDING ((uint32_t)CAN_IER_FMPIE0)  /*!< FIFO 0 message pending interrupt */\r\n#define CAN_IT_RX_FIFO0_FULL        ((uint32_t)CAN_IER_FFIE0)   /*!< FIFO 0 full interrupt            */\r\n#define CAN_IT_RX_FIFO0_OVERRUN     ((uint32_t)CAN_IER_FOVIE0)  /*!< FIFO 0 overrun interrupt         */\r\n#define CAN_IT_RX_FIFO1_MSG_PENDING ((uint32_t)CAN_IER_FMPIE1)  /*!< FIFO 1 message pending interrupt */\r\n#define CAN_IT_RX_FIFO1_FULL        ((uint32_t)CAN_IER_FFIE1)   /*!< FIFO 1 full interrupt            */\r\n#define CAN_IT_RX_FIFO1_OVERRUN     ((uint32_t)CAN_IER_FOVIE1)  /*!< FIFO 1 overrun interrupt         */\r\n\r\n/* Operating Mode Interrupts */\r\n#define CAN_IT_WAKEUP               ((uint32_t)CAN_IER_WKUIE)   /*!< Wake-up interrupt                */\r\n#define CAN_IT_SLEEP_ACK            ((uint32_t)CAN_IER_SLKIE)   /*!< Sleep acknowledge interrupt      */\r\n\r\n/* Error Interrupts */\r\n#define CAN_IT_ERROR_WARNING        ((uint32_t)CAN_IER_EWGIE)   /*!< Error warning interrupt          */\r\n#define CAN_IT_ERROR_PASSIVE        ((uint32_t)CAN_IER_EPVIE)   /*!< Error passive interrupt          */\r\n#define CAN_IT_BUSOFF               ((uint32_t)CAN_IER_BOFIE)   /*!< Bus-off interrupt                */\r\n#define CAN_IT_LAST_ERROR_CODE      ((uint32_t)CAN_IER_LECIE)   /*!< Last error code interrupt        */\r\n#define CAN_IT_ERROR                ((uint32_t)CAN_IER_ERRIE)   /*!< Error Interrupt                  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macros -----------------------------------------------------------*/\r\n/** @defgroup CAN_Exported_Macros CAN Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief  Reset CAN handle state\r\n  * @param  __HANDLE__ CAN handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)\r\n\r\n/**\r\n  * @brief  Enable the specified CAN interrupts.\r\n  * @param  __HANDLE__ CAN handle.\r\n  * @param  __INTERRUPT__ CAN Interrupt sources to enable.\r\n  *           This parameter can be any combination of @arg CAN_Interrupts\r\n  * @retval None\r\n  */\r\n#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disable the specified CAN interrupts.\r\n  * @param  __HANDLE__ CAN handle.\r\n  * @param  __INTERRUPT__ CAN Interrupt sources to disable.\r\n  *           This parameter can be any combination of @arg CAN_Interrupts\r\n  * @retval None\r\n  */\r\n#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))\r\n\r\n/** @brief  Check if the specified CAN interrupt source is enabled or disabled.\r\n  * @param  __HANDLE__ specifies the CAN Handle.\r\n  * @param  __INTERRUPT__ specifies the CAN interrupt source to check.\r\n  *           This parameter can be a value of @arg CAN_Interrupts\r\n  * @retval The state of __IT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) & (__INTERRUPT__))\r\n\r\n/** @brief  Check whether the specified CAN flag is set or not.\r\n  * @param  __HANDLE__ specifies the CAN Handle.\r\n  * @param  __FLAG__ specifies the flag to check.\r\n  *         This parameter can be one of @arg CAN_flags\r\n  * @retval The state of __FLAG__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \\\r\n  ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \\\r\n   (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \\\r\n   (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \\\r\n   (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \\\r\n   (((__FLAG__) >> 8U) == 3U)? ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)\r\n\r\n/** @brief  Clear the specified CAN pending flag.\r\n  * @param  __HANDLE__ specifies the CAN Handle.\r\n  * @param  __FLAG__ specifies the flag to check.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg CAN_FLAG_RQCP0: Request complete MailBox 0 Flag\r\n  *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox 0 Flag\r\n  *            @arg CAN_FLAG_ALST0: Arbitration Lost MailBox 0 Flag\r\n  *            @arg CAN_FLAG_TERR0: Transmission error MailBox 0 Flag\r\n  *            @arg CAN_FLAG_RQCP1: Request complete MailBox 1 Flag\r\n  *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox 1 Flag\r\n  *            @arg CAN_FLAG_ALST1: Arbitration Lost MailBox 1 Flag\r\n  *            @arg CAN_FLAG_TERR1: Transmission error MailBox 1 Flag\r\n  *            @arg CAN_FLAG_RQCP2: Request complete MailBox 2 Flag\r\n  *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox 2 Flag\r\n  *            @arg CAN_FLAG_ALST2: Arbitration Lost MailBox 2 Flag\r\n  *            @arg CAN_FLAG_TERR2: Transmission error MailBox 2 Flag\r\n  *            @arg CAN_FLAG_FF0:   RX FIFO 0 Full Flag\r\n  *            @arg CAN_FLAG_FOV0:  RX FIFO 0 Overrun Flag\r\n  *            @arg CAN_FLAG_FF1:   RX FIFO 1 Full Flag\r\n  *            @arg CAN_FLAG_FOV1:  RX FIFO 1 Overrun Flag\r\n  *            @arg CAN_FLAG_WKUI:  Wake up Interrupt Flag\r\n  *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Interrupt Flag\r\n  * @retval None\r\n  */\r\n#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \\\r\n  ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \\\r\n   (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \\\r\n   (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \\\r\n   (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup CAN_Exported_Functions CAN Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions\r\n *  @brief    Initialization and Configuration functions\r\n * @{\r\n */\r\n\r\n/* Initialization and de-initialization functions *****************************/\r\nHAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan);\r\nHAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan);\r\nvoid HAL_CAN_MspInit(CAN_HandleTypeDef *hcan);\r\nvoid HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan);\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @addtogroup CAN_Exported_Functions_Group2 Configuration functions\r\n *  @brief    Configuration functions\r\n * @{\r\n */\r\n\r\n/* Configuration functions ****************************************************/\r\nHAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig);\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @addtogroup CAN_Exported_Functions_Group3 Control functions\r\n *  @brief    Control functions\r\n * @{\r\n */\r\n\r\n/* Control functions **********************************************************/\r\nHAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan);\r\nHAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan);\r\nHAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan);\r\nHAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);\r\nuint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan);\r\nHAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox);\r\nHAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);\r\nuint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan);\r\nuint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);\r\nuint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox);\r\nHAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]);\r\nuint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo);\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @addtogroup CAN_Exported_Functions_Group4 Interrupts management\r\n *  @brief    Interrupts management\r\n * @{\r\n */\r\n/* Interrupts management ******************************************************/\r\nHAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs);\r\nHAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs);\r\nvoid HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan);\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @addtogroup CAN_Exported_Functions_Group5 Callback functions\r\n *  @brief    Callback functions\r\n * @{\r\n */\r\n/* Callbacks functions ********************************************************/\r\n\r\nvoid HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan);\r\nvoid HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan);\r\nvoid HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan);\r\nvoid HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan);\r\nvoid HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan);\r\nvoid HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan);\r\nvoid HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan);\r\nvoid HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan);\r\nvoid HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan);\r\nvoid HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan);\r\nvoid HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan);\r\nvoid HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan);\r\nvoid HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @addtogroup CAN_Exported_Functions_Group6 Peripheral State and Error functions\r\n *  @brief   CAN Peripheral State functions\r\n * @{\r\n */\r\n/* Peripheral State and Error functions ***************************************/\r\nHAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan);\r\nuint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);\r\nHAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan);\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/** @defgroup CAN_Private_Types CAN Private Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @defgroup CAN_Private_Variables CAN Private Variables\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup CAN_Private_Constants CAN Private Constants\r\n  * @{\r\n  */\r\n#define CAN_FLAG_MASK  (0x000000FFU)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private Macros -----------------------------------------------------------*/\r\n/** @defgroup CAN_Private_Macros CAN Private Macros\r\n  * @{\r\n  */\r\n\r\n#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \\\r\n                           ((MODE) == CAN_MODE_LOOPBACK)|| \\\r\n                           ((MODE) == CAN_MODE_SILENT) || \\\r\n                           ((MODE) == CAN_MODE_SILENT_LOOPBACK))\r\n#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ) || \\\r\n                         ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))\r\n#define IS_CAN_BS1(BS1) (((BS1) == CAN_BS1_1TQ) || ((BS1) == CAN_BS1_2TQ) || \\\r\n                         ((BS1) == CAN_BS1_3TQ) || ((BS1) == CAN_BS1_4TQ) || \\\r\n                         ((BS1) == CAN_BS1_5TQ) || ((BS1) == CAN_BS1_6TQ) || \\\r\n                         ((BS1) == CAN_BS1_7TQ) || ((BS1) == CAN_BS1_8TQ) || \\\r\n                         ((BS1) == CAN_BS1_9TQ) || ((BS1) == CAN_BS1_10TQ)|| \\\r\n                         ((BS1) == CAN_BS1_11TQ)|| ((BS1) == CAN_BS1_12TQ)|| \\\r\n                         ((BS1) == CAN_BS1_13TQ)|| ((BS1) == CAN_BS1_14TQ)|| \\\r\n                         ((BS1) == CAN_BS1_15TQ)|| ((BS1) == CAN_BS1_16TQ))\r\n#define IS_CAN_BS2(BS2) (((BS2) == CAN_BS2_1TQ) || ((BS2) == CAN_BS2_2TQ) || \\\r\n                         ((BS2) == CAN_BS2_3TQ) || ((BS2) == CAN_BS2_4TQ) || \\\r\n                         ((BS2) == CAN_BS2_5TQ) || ((BS2) == CAN_BS2_6TQ) || \\\r\n                         ((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ))\r\n#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))\r\n#define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU)\r\n#define IS_CAN_FILTER_BANK_DUAL(BANK) ((BANK) <= 27U)\r\n#define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U)\r\n#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \\\r\n                                  ((MODE) == CAN_FILTERMODE_IDLIST))\r\n#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \\\r\n                                    ((SCALE) == CAN_FILTERSCALE_32BIT))\r\n#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \\\r\n                                  ((FIFO) == CAN_FILTER_FIFO1))\r\n#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \\\r\n                                            ((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \\\r\n                                            ((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 ))\r\n#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2))\r\n#define IS_CAN_STDID(STDID)   ((STDID) <= 0x7FFU)\r\n#define IS_CAN_EXTID(EXTID)   ((EXTID) <= 0x1FFFFFFFU)\r\n#define IS_CAN_DLC(DLC)       ((DLC) <= 8U)\r\n#define IS_CAN_IDTYPE(IDTYPE)  (((IDTYPE) == CAN_ID_STD) || \\\r\n                                ((IDTYPE) == CAN_ID_EXT))\r\n#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))\r\n#define IS_CAN_RX_FIFO(FIFO) (((FIFO) == CAN_RX_FIFO0) || ((FIFO) == CAN_RX_FIFO1))\r\n#define IS_CAN_IT(IT) ((IT) <= (CAN_IT_TX_MAILBOX_EMPTY     | CAN_IT_RX_FIFO0_MSG_PENDING      | \\\r\n                                CAN_IT_RX_FIFO0_FULL        | CAN_IT_RX_FIFO0_OVERRUN          | \\\r\n                                CAN_IT_RX_FIFO1_MSG_PENDING | CAN_IT_RX_FIFO1_FULL             | \\\r\n                                CAN_IT_RX_FIFO1_OVERRUN     | CAN_IT_WAKEUP                    | \\\r\n                                CAN_IT_SLEEP_ACK            | CAN_IT_ERROR_WARNING             | \\\r\n                                CAN_IT_ERROR_PASSIVE        | CAN_IT_BUSOFF                    | \\\r\n                                CAN_IT_LAST_ERROR_CODE      | CAN_IT_ERROR))\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* End of private macros -----------------------------------------------------*/\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n#endif /* CAN1 */\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* STM32F7xx_HAL_CAN_H */\r\n\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cec.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_cec.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of CEC HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************  \r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_CEC_H\r\n#define __STM32F7xx_HAL_CEC_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n#if defined (CEC)\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup CEC\r\n  * @{\r\n  */\r\n  \r\n/* Exported types ------------------------------------------------------------*/ \r\n/** @defgroup CEC_Exported_Types CEC Exported Types\r\n  * @{\r\n  */\r\n  \r\n/** \r\n  * @brief CEC Init Structure definition  \r\n  */ \r\ntypedef struct\r\n{\r\n  uint32_t SignalFreeTime;               /*!< Set SFT field, specifies the Signal Free Time.\r\n                                              It can be one of @ref CEC_Signal_Free_Time \r\n                                              and belongs to the set {0,...,7} where  \r\n                                              0x0 is the default configuration \r\n                                              else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */\r\n\r\n  uint32_t Tolerance;                    /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,\r\n                                              it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE \r\n                                              or CEC_EXTENDED_TOLERANCE */\r\n\r\n  uint32_t BRERxStop;                    /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception. \r\n                                              CEC_NO_RX_STOP_ON_BRE: reception is not stopped. \r\n                                              CEC_RX_STOP_ON_BRE:    reception is stopped. */\r\n\r\n  uint32_t BREErrorBitGen;               /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the\r\n                                              CEC line upon Bit Rising Error detection.\r\n                                              CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.\r\n                                              CEC_BRE_ERRORBIT_GENERATION:    error-bit generation if BRESTP is set. */\r\n                                              \r\n  uint32_t LBPEErrorBitGen;              /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the\r\n                                              CEC line upon Long Bit Period Error detection.\r\n                                              CEC_LBPE_ERRORBIT_NO_GENERATION:  no error-bit generation. \r\n                                              CEC_LBPE_ERRORBIT_GENERATION:     error-bit generation. */  \r\n                                              \r\n  uint32_t BroadcastMsgNoErrorBitGen;    /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line\r\n                                              upon an error detected on a broadcast message. \r\n                                              \r\n                                              It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:\r\n                                              \r\n                                              1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.\r\n                                                 a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE \r\n                                                    and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.\r\n                                                 b) LBPE detection: error-bit generation on the CEC line \r\n                                                    if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.\r\n                                                    \r\n                                              2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.\r\n                                                 no error-bit generation in case neither a) nor b) are satisfied. Additionally,\r\n                                                 there is no error-bit generation in case of Short Bit Period Error detection in \r\n                                                 a broadcast message while LSTN bit is set. */\r\n \r\n  uint32_t SignalFreeTimeOption;         /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.\r\n                                              CEC_SFT_START_ON_TXSOM SFT:    timer starts when TXSOM is set by software.\r\n                                              CEC_SFT_START_ON_TX_RX_END:  SFT timer starts automatically at the end of message transmission/reception. */\r\n  \r\n  uint32_t ListenMode;                   /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:\r\n  \r\n                                              CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its \r\n                                                own address (OAR). Messages addressed to different destination are ignored. \r\n                                                Broadcast messages are always received.\r\n                                                \r\n                                              CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own \r\n                                                address (OAR) with positive acknowledge. Messages addressed to different destination \r\n                                                are received, but without interfering with the CEC bus: no acknowledge sent.  */\r\n\r\n  uint16_t  OwnAddress;                 /*!< Own addresses configuration\r\n                                             This parameter can be a value of @ref CEC_OWN_ADDRESS */\r\n  \r\n  uint8_t  *RxBuffer;                    /*!< CEC Rx buffer pointeur */\r\n  \r\n\r\n}CEC_InitTypeDef;\r\n\r\n/** \r\n  * @brief HAL CEC State structures definition \r\n  * @note  HAL CEC State value is a combination of 2 different substates: gState and RxState.\r\n  *        - gState contains CEC state information related to global Handle management \r\n  *          and also information related to Tx operations.\r\n  *          gState value coding follow below described bitmap :\r\n  *          b7 (not used)\r\n  *             x  : Should be set to 0\r\n  *          b6  Error information \r\n  *             0  : No Error\r\n  *             1  : Error\r\n  *          b5     IP initilisation status\r\n  *             0  : Reset (IP not initialized)\r\n  *             1  : Init done (IP initialized. HAL CEC Init function already called)\r\n  *          b4-b3  (not used)\r\n  *             xx : Should be set to 00\r\n  *          b2     Intrinsic process state\r\n  *             0  : Ready\r\n  *             1  : Busy (IP busy with some configuration or internal operations)\r\n  *          b1     (not used)\r\n  *             x  : Should be set to 0\r\n  *          b0     Tx state\r\n  *             0  : Ready (no Tx operation ongoing)\r\n  *             1  : Busy (Tx operation ongoing)\r\n  *        - RxState contains information related to Rx operations.\r\n  *          RxState value coding follow below described bitmap :\r\n  *          b7-b6  (not used)\r\n  *             xx : Should be set to 00\r\n  *          b5     IP initilisation status\r\n  *             0  : Reset (IP not initialized)\r\n  *             1  : Init done (IP initialized)\r\n  *          b4-b2  (not used)\r\n  *            xxx : Should be set to 000\r\n  *          b1     Rx state\r\n  *             0  : Ready (no Rx operation ongoing)\r\n  *             1  : Busy (Rx operation ongoing)\r\n  *          b0     (not used)\r\n  *             x  : Should be set to 0.  \r\n  */ \r\ntypedef enum\r\n{\r\n  HAL_CEC_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized \r\n                                                   Value is allowed for gState and RxState             */\r\n  HAL_CEC_STATE_READY             = 0x20U,    /*!< Peripheral Initialized and ready for use\r\n                                                   Value is allowed for gState and RxState             */\r\n  HAL_CEC_STATE_BUSY              = 0x24U,    /*!< an internal process is ongoing\r\n                                                   Value is allowed for gState only                    */\r\n  HAL_CEC_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing\r\n                                                   Value is allowed for RxState only                   */\r\n  HAL_CEC_STATE_BUSY_TX           = 0x21U,    /*!< Data Transmission process is ongoing \r\n                                                   Value is allowed for gState only                    */                                                  \r\n  HAL_CEC_STATE_BUSY_RX_TX        = 0x23U,    /*!< an internal process is ongoing\r\n                                                   Value is allowed for gState only                    */\r\n  HAL_CEC_STATE_ERROR             = 0x60U     /*!< Error Value is allowed for gState only              */\r\n}HAL_CEC_StateTypeDef;\r\n\r\n/** \r\n  * @brief  CEC handle Structure definition  \r\n  */  \r\ntypedef struct\r\n{\r\n  CEC_TypeDef             *Instance;      /*!< CEC registers base address */\r\n  \r\n  CEC_InitTypeDef         Init;           /*!< CEC communication parameters */\r\n  \r\n  uint8_t                 *pTxBuffPtr;    /*!< Pointer to CEC Tx transfer Buffer */\r\n  \r\n  uint16_t                TxXferCount;    /*!< CEC Tx Transfer Counter */\r\n  \r\n  uint16_t                RxXferSize;     /*!< CEC Rx Transfer size, 0: header received only */\r\n  \r\n  HAL_LockTypeDef         Lock;           /*!< Locking object */\r\n\r\n  HAL_CEC_StateTypeDef    gState;         /*!< CEC state information related to global Handle management \r\n                                               and also related to Tx operations.\r\n                                               This parameter can be a value of @ref HAL_CEC_StateTypeDef */\r\n  \r\n  HAL_CEC_StateTypeDef    RxState;        /*!< CEC state information related to Rx operations.\r\n                                               This parameter can be a value of @ref HAL_CEC_StateTypeDef */\r\n  \r\n  uint32_t                ErrorCode;      /*!< For errors handling purposes, copy of ISR register \r\n                                               in case error is reported */    \r\n}CEC_HandleTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup CEC_Exported_Constants CEC Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CEC_Error_Code CEC Error Code\r\n  * @{\r\n  */ \r\n#define HAL_CEC_ERROR_NONE    (uint32_t) 0x0000U     /*!< no error                      */\r\n#define HAL_CEC_ERROR_RXOVR   CEC_ISR_RXOVR          /*!< CEC Rx-Overrun                */\r\n#define HAL_CEC_ERROR_BRE     CEC_ISR_BRE            /*!< CEC Rx Bit Rising Error       */\r\n#define HAL_CEC_ERROR_SBPE    CEC_ISR_SBPE           /*!< CEC Rx Short Bit period Error */\r\n#define HAL_CEC_ERROR_LBPE    CEC_ISR_LBPE           /*!< CEC Rx Long Bit period Error  */\r\n#define HAL_CEC_ERROR_RXACKE  CEC_ISR_RXACKE         /*!< CEC Rx Missing Acknowledge    */\r\n#define HAL_CEC_ERROR_ARBLST  CEC_ISR_ARBLST         /*!< CEC Arbitration Lost          */\r\n#define HAL_CEC_ERROR_TXUDR   CEC_ISR_TXUDR          /*!< CEC Tx-Buffer Underrun        */\r\n#define HAL_CEC_ERROR_TXERR   CEC_ISR_TXERR          /*!< CEC Tx-Error                  */\r\n#define HAL_CEC_ERROR_TXACKE  CEC_ISR_TXACKE         /*!< CEC Tx Missing Acknowledge    */\r\n/**\r\n  * @}\r\n  */\r\n       \r\n/** @defgroup CEC_Signal_Free_Time  CEC Signal Free Time setting parameter\r\n  * @{\r\n  */\r\n#define CEC_DEFAULT_SFT                    ((uint32_t)0x00000000U)\r\n#define CEC_0_5_BITPERIOD_SFT              ((uint32_t)0x00000001U)\r\n#define CEC_1_5_BITPERIOD_SFT              ((uint32_t)0x00000002U)\r\n#define CEC_2_5_BITPERIOD_SFT              ((uint32_t)0x00000003U)\r\n#define CEC_3_5_BITPERIOD_SFT              ((uint32_t)0x00000004U)\r\n#define CEC_4_5_BITPERIOD_SFT              ((uint32_t)0x00000005U)\r\n#define CEC_5_5_BITPERIOD_SFT              ((uint32_t)0x00000006U)\r\n#define CEC_6_5_BITPERIOD_SFT              ((uint32_t)0x00000007U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CEC_Tolerance CEC Receiver Tolerance\r\n  * @{\r\n  */\r\n#define CEC_STANDARD_TOLERANCE             ((uint32_t)0x00000000U)\r\n#define CEC_EXTENDED_TOLERANCE             ((uint32_t)CEC_CFGR_RXTOL)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup CEC_BRERxStop CEC Reception Stop on Error\r\n  * @{\r\n  */\r\n#define CEC_NO_RX_STOP_ON_BRE             ((uint32_t)0x00000000U)\r\n#define CEC_RX_STOP_ON_BRE                ((uint32_t)CEC_CFGR_BRESTP)\r\n/**\r\n  * @}\r\n  */            \r\n             \r\n/** @defgroup CEC_BREErrorBitGen  CEC Error Bit Generation if Bit Rise Error reported\r\n  * @{\r\n  */ \r\n#define CEC_BRE_ERRORBIT_NO_GENERATION     ((uint32_t)0x00000000U)\r\n#define CEC_BRE_ERRORBIT_GENERATION        ((uint32_t)CEC_CFGR_BREGEN)\r\n/**\r\n  * @}\r\n  */ \r\n                        \r\n/** @defgroup CEC_LBPEErrorBitGen  CEC Error Bit Generation if Long Bit Period Error reported\r\n  * @{\r\n  */ \r\n#define CEC_LBPE_ERRORBIT_NO_GENERATION     ((uint32_t)0x00000000U)\r\n#define CEC_LBPE_ERRORBIT_GENERATION        ((uint32_t)CEC_CFGR_LBPEGEN)\r\n/**\r\n  * @}\r\n  */    \r\n\r\n/** @defgroup CEC_BroadCastMsgErrorBitGen  CEC Error Bit Generation on Broadcast message\r\n  * @{\r\n  */ \r\n#define CEC_BROADCASTERROR_ERRORBIT_GENERATION     ((uint32_t)0x00000000U)\r\n#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION  ((uint32_t)CEC_CFGR_BRDNOGEN)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup CEC_SFT_Option     CEC Signal Free Time start option\r\n  * @{\r\n  */ \r\n#define CEC_SFT_START_ON_TXSOM           ((uint32_t)0x00000000U)\r\n#define CEC_SFT_START_ON_TX_RX_END       ((uint32_t)CEC_CFGR_SFTOPT)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup CEC_Listening_Mode    CEC Listening mode option\r\n  * @{\r\n  */ \r\n#define CEC_REDUCED_LISTENING_MODE          ((uint32_t)0x00000000U)\r\n#define CEC_FULL_LISTENING_MODE             ((uint32_t)CEC_CFGR_LSTN)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup CEC_OAR_Position   CEC Device Own Address position in CEC CFGR register     \r\n  * @{\r\n  */\r\n#define CEC_CFGR_OAR_LSB_POS            ((uint32_t) 16U)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup CEC_Initiator_Position   CEC Initiator logical address position in message header     \r\n  * @{\r\n  */\r\n#define CEC_INITIATOR_LSB_POS           ((uint32_t) 4U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CEC_OWN_ADDRESS   CEC Own Address    \r\n  * @{\r\n  */\r\n#define CEC_OWN_ADDRESS_NONE           ((uint16_t) 0x0000U)   /* Reset value */\r\n#define CEC_OWN_ADDRESS_0              ((uint16_t) 0x0001U)   /* Logical Address 0 */\r\n#define CEC_OWN_ADDRESS_1              ((uint16_t) 0x0002U)   /* Logical Address 1 */\r\n#define CEC_OWN_ADDRESS_2              ((uint16_t) 0x0004U)   /* Logical Address 2 */\r\n#define CEC_OWN_ADDRESS_3              ((uint16_t) 0x0008U)   /* Logical Address 3 */\r\n#define CEC_OWN_ADDRESS_4              ((uint16_t) 0x0010U)   /* Logical Address 4 */\r\n#define CEC_OWN_ADDRESS_5              ((uint16_t) 0x0020U)   /* Logical Address 5 */\r\n#define CEC_OWN_ADDRESS_6              ((uint16_t) 0x0040U)   /* Logical Address 6 */\r\n#define CEC_OWN_ADDRESS_7              ((uint16_t) 0x0080U)   /* Logical Address 7 */\r\n#define CEC_OWN_ADDRESS_8              ((uint16_t) 0x0100U)   /* Logical Address 9 */\r\n#define CEC_OWN_ADDRESS_9              ((uint16_t) 0x0200U)   /* Logical Address 10 */\r\n#define CEC_OWN_ADDRESS_10             ((uint16_t) 0x0400U)   /* Logical Address 11 */\r\n#define CEC_OWN_ADDRESS_11             ((uint16_t) 0x0800U)   /* Logical Address 12 */\r\n#define CEC_OWN_ADDRESS_12             ((uint16_t) 0x1000U)   /* Logical Address 13 */\r\n#define CEC_OWN_ADDRESS_13             ((uint16_t) 0x2000U)   /* Logical Address 14 */\r\n#define CEC_OWN_ADDRESS_14             ((uint16_t) 0x4000U)   /* Logical Address 15 */\r\n/**\r\n  * @}\r\n  */\r\n    \r\n/** @defgroup CEC_Interrupts_Definitions  CEC Interrupts definition\r\n  * @{\r\n  */\r\n#define CEC_IT_TXACKE                   CEC_IER_TXACKEIE\r\n#define CEC_IT_TXERR                    CEC_IER_TXERRIE\r\n#define CEC_IT_TXUDR                    CEC_IER_TXUDRIE\r\n#define CEC_IT_TXEND                    CEC_IER_TXENDIE\r\n#define CEC_IT_TXBR                     CEC_IER_TXBRIE\r\n#define CEC_IT_ARBLST                   CEC_IER_ARBLSTIE\r\n#define CEC_IT_RXACKE                   CEC_IER_RXACKEIE\r\n#define CEC_IT_LBPE                     CEC_IER_LBPEIE\r\n#define CEC_IT_SBPE                     CEC_IER_SBPEIE\r\n#define CEC_IT_BRE                      CEC_IER_BREIE\r\n#define CEC_IT_RXOVR                    CEC_IER_RXOVRIE\r\n#define CEC_IT_RXEND                    CEC_IER_RXENDIE\r\n#define CEC_IT_RXBR                     CEC_IER_RXBRIE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CEC_Flags_Definitions  CEC Flags definition\r\n  * @{\r\n  */\r\n#define CEC_FLAG_TXACKE                 CEC_ISR_TXACKE\r\n#define CEC_FLAG_TXERR                  CEC_ISR_TXERR\r\n#define CEC_FLAG_TXUDR                  CEC_ISR_TXUDR\r\n#define CEC_FLAG_TXEND                  CEC_ISR_TXEND\r\n#define CEC_FLAG_TXBR                   CEC_ISR_TXBR\r\n#define CEC_FLAG_ARBLST                 CEC_ISR_ARBLST\r\n#define CEC_FLAG_RXACKE                 CEC_ISR_RXACKE\r\n#define CEC_FLAG_LBPE                   CEC_ISR_LBPE\r\n#define CEC_FLAG_SBPE                   CEC_ISR_SBPE\r\n#define CEC_FLAG_BRE                    CEC_ISR_BRE\r\n#define CEC_FLAG_RXOVR                  CEC_ISR_RXOVR\r\n#define CEC_FLAG_RXEND                  CEC_ISR_RXEND\r\n#define CEC_FLAG_RXBR                   CEC_ISR_RXBR\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags \r\n  * @{\r\n  */\r\n#define CEC_ISR_ALL_ERROR              ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\\\r\n                                                  CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag \r\n  * @{\r\n  */\r\n#define CEC_IER_RX_ALL_ERR              ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag \r\n  * @{\r\n  */\r\n#define CEC_IER_TX_ALL_ERR              ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */  \r\n  \r\n/* Exported macros -----------------------------------------------------------*/\r\n/** @defgroup CEC_Exported_Macros CEC Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief  Reset CEC handle gstate & RxState\r\n  * @param  __HANDLE__ CEC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{                                                   \\\r\n                                                       (__HANDLE__)->gState = HAL_CEC_STATE_RESET;     \\\r\n                                                       (__HANDLE__)->RxState = HAL_CEC_STATE_RESET;    \\\r\n                                                     } while(0)\r\n\r\n/** @brief  Checks whether or not the specified CEC interrupt flag is set.\r\n  * @param  __HANDLE__ specifies the CEC Handle.\r\n  * @param  __FLAG__ specifies the flag to check.\r\n  *            @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error\r\n  *            @arg CEC_FLAG_TXERR: Tx Error.\r\n  *            @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.\r\n  *            @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).\r\n  *            @arg CEC_FLAG_TXBR: Tx-Byte Request.\r\n  *            @arg CEC_FLAG_ARBLST: Arbitration Lost\r\n  *            @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge \r\n  *            @arg CEC_FLAG_LBPE: Rx Long period Error\r\n  *            @arg CEC_FLAG_SBPE: Rx Short period Error\r\n  *            @arg CEC_FLAG_BRE: Rx Bit Rising Error\r\n  *            @arg CEC_FLAG_RXOVR: Rx Overrun.\r\n  *            @arg CEC_FLAG_RXEND: End Of Reception.\r\n  *            @arg CEC_FLAG_RXBR: Rx-Byte Received.      \r\n  * @retval ITStatus\r\n  */\r\n#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->ISR & (__FLAG__)) \r\n\r\n/** @brief  Clears the interrupt or status flag when raised (write at 1)\r\n  * @param  __HANDLE__ specifies the CEC Handle.\r\n  * @param  __FLAG__ specifies the interrupt/status flag to clear.\r\n  *        This parameter can be one of the following values:\r\n  *            @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error\r\n  *            @arg CEC_FLAG_TXERR: Tx Error.\r\n  *            @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.\r\n  *            @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).\r\n  *            @arg CEC_FLAG_TXBR: Tx-Byte Request.\r\n  *            @arg CEC_FLAG_ARBLST: Arbitration Lost\r\n  *            @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge \r\n  *            @arg CEC_FLAG_LBPE: Rx Long period Error\r\n  *            @arg CEC_FLAG_SBPE: Rx Short period Error\r\n  *            @arg CEC_FLAG_BRE: Rx Bit Rising Error\r\n  *            @arg CEC_FLAG_RXOVR: Rx Overrun.\r\n  *            @arg CEC_FLAG_RXEND: End Of Reception.\r\n  *            @arg CEC_FLAG_RXBR: Rx-Byte Received. \r\n  * @retval none  \r\n  */\r\n#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \r\n\r\n/** @brief  Enables the specified CEC interrupt.\r\n  * @param  __HANDLE__ specifies the CEC Handle.\r\n  * @param  __INTERRUPT__ specifies the CEC interrupt to enable.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable \r\n  *            @arg CEC_IT_TXERR: Tx Error IT Enable \r\n  *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable \r\n  *            @arg CEC_IT_TXEND: End of transmission IT Enable \r\n  *            @arg CEC_IT_TXBR: Tx-Byte Request IT Enable \r\n  *            @arg CEC_IT_ARBLST: Arbitration Lost IT Enable \r\n  *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable \r\n  *            @arg CEC_IT_LBPE: Rx Long period Error IT Enable \r\n  *            @arg CEC_IT_SBPE: Rx Short period Error IT Enable \r\n  *            @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable \r\n  *            @arg CEC_IT_RXOVR: Rx Overrun IT Enable \r\n  *            @arg CEC_IT_RXEND: End Of Reception IT Enable \r\n  *            @arg CEC_IT_RXBR: Rx-Byte Received IT Enable                          \r\n  * @retval none\r\n  */\r\n#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))  \r\n\r\n/** @brief  Disables the specified CEC interrupt.\r\n  * @param  __HANDLE__ specifies the CEC Handle.\r\n  * @param  __INTERRUPT__ specifies the CEC interrupt to disable.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable \r\n  *            @arg CEC_IT_TXERR: Tx Error IT Enable \r\n  *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable \r\n  *            @arg CEC_IT_TXEND: End of transmission IT Enable \r\n  *            @arg CEC_IT_TXBR: Tx-Byte Request IT Enable \r\n  *            @arg CEC_IT_ARBLST: Arbitration Lost IT Enable \r\n  *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable \r\n  *            @arg CEC_IT_LBPE: Rx Long period Error IT Enable \r\n  *            @arg CEC_IT_SBPE: Rx Short period Error IT Enable \r\n  *            @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable \r\n  *            @arg CEC_IT_RXOVR: Rx Overrun IT Enable \r\n  *            @arg CEC_IT_RXEND: End Of Reception IT Enable \r\n  *            @arg CEC_IT_RXBR: Rx-Byte Received IT Enable                   \r\n  * @retval none\r\n  */   \r\n#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))  \r\n\r\n/** @brief  Checks whether or not the specified CEC interrupt is enabled.\r\n  * @param  __HANDLE__ specifies the CEC Handle.\r\n  * @param  __INTERRUPT__ specifies the CEC interrupt to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable \r\n  *            @arg CEC_IT_TXERR: Tx Error IT Enable \r\n  *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable \r\n  *            @arg CEC_IT_TXEND: End of transmission IT Enable \r\n  *            @arg CEC_IT_TXBR: Tx-Byte Request IT Enable \r\n  *            @arg CEC_IT_ARBLST: Arbitration Lost IT Enable \r\n  *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable \r\n  *            @arg CEC_IT_LBPE: Rx Long period Error IT Enable \r\n  *            @arg CEC_IT_SBPE: Rx Short period Error IT Enable \r\n  *            @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable \r\n  *            @arg CEC_IT_RXOVR: Rx Overrun IT Enable \r\n  *            @arg CEC_IT_RXEND: End Of Reception IT Enable \r\n  *            @arg CEC_IT_RXBR: Rx-Byte Received IT Enable                  \r\n  * @retval FlagStatus  \r\n  */\r\n#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))\r\n\r\n/** @brief  Enables the CEC device\r\n  * @param  __HANDLE__ specifies the CEC Handle.               \r\n  * @retval none \r\n  */\r\n#define __HAL_CEC_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR |=  CEC_CR_CECEN)\r\n\r\n/** @brief  Disables the CEC device\r\n  * @param  __HANDLE__ specifies the CEC Handle.               \r\n  * @retval none \r\n  */\r\n#define __HAL_CEC_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR &=  ~CEC_CR_CECEN)\r\n\r\n/** @brief  Set Transmission Start flag\r\n  * @param  __HANDLE__ specifies the CEC Handle.               \r\n  * @retval none \r\n  */\r\n#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__)        ((__HANDLE__)->Instance->CR |=  CEC_CR_TXSOM)\r\n\r\n/** @brief  Set Transmission End flag\r\n  * @param  __HANDLE__ specifies the CEC Handle.               \r\n  * @retval none \r\n  * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.  \r\n  */\r\n#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__)         ((__HANDLE__)->Instance->CR |=  CEC_CR_TXEOM)\r\n\r\n/** @brief  Get Transmission Start flag\r\n  * @param  __HANDLE__ specifies the CEC Handle.               \r\n  * @retval FlagStatus \r\n  */\r\n#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)\r\n\r\n/** @brief  Get Transmission End flag\r\n  * @param  __HANDLE__ specifies the CEC Handle.               \r\n  * @retval FlagStatus \r\n  */\r\n#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__)   ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)   \r\n\r\n/** @brief  Clear OAR register\r\n  * @param  __HANDLE__ specifies the CEC Handle.               \r\n  * @retval none \r\n  */\r\n#define __HAL_CEC_CLEAR_OAR(__HANDLE__)   CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)\r\n\r\n/** @brief  Set OAR register (without resetting previously set address in case of multi-address mode)\r\n  *          To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand\r\n  * @param  __HANDLE__ specifies the CEC Handle. \r\n  * @param  __ADDRESS__ Own Address value (CEC logical address is identified by bit position)                   \r\n  * @retval none \r\n  */\r\n#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__)   SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)\r\n\r\n/**\r\n  * @}\r\n  */                       \r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup CEC_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup CEC_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n/* Initialization and de-initialization functions  ****************************/\r\nHAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);\r\nHAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);\r\nHAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);\r\nvoid HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);\r\nvoid HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup CEC_Exported_Functions_Group2\r\n  * @{\r\n  */\r\n/* I/O operation functions  ***************************************************/\r\nHAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);\r\nuint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);\r\nvoid HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer);\r\nvoid HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);\r\nvoid HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);\r\nvoid HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);\r\nvoid HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup CEC_Exported_Functions_Group3\r\n  * @{\r\n  */\r\n/* Peripheral State functions  ************************************************/\r\nHAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);\r\nuint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Private types -------------------------------------------------------------*/\r\n/** @defgroup CEC_Private_Types CEC Private Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @defgroup CEC_Private_Variables CEC Private Variables\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup CEC_Private_Constants CEC Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup CEC_Private_Macros CEC Private Macros\r\n  * @{\r\n  */\r\n  \r\n#define IS_CEC_SIGNALFREETIME(__SFT__)     ((__SFT__) <= CEC_CFGR_SFT)  \r\n\r\n#define IS_CEC_TOLERANCE(__RXTOL__)        (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \\\r\n                                            ((__RXTOL__) == CEC_EXTENDED_TOLERANCE))\r\n                                            \r\n#define IS_CEC_BRERXSTOP(__BRERXSTOP__)   (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \\\r\n                                           ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))\r\n                                           \r\n#define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \\\r\n                                                ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))\r\n\r\n#define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \\\r\n                                                 ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))\r\n                                                 \r\n#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \\\r\n                                                                       ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))\r\n                                                                       \r\n#define IS_CEC_SFTOP(__SFTOP__)          (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \\\r\n                                          ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))\r\n                                          \r\n#define IS_CEC_LISTENING_MODE(__MODE__)     (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \\\r\n                                             ((__MODE__) == CEC_FULL_LISTENING_MODE))\r\n\r\n/** @brief Check CEC message size.\r\n  *       The message size is the payload size: without counting the header, \r\n  *       it varies from 0 byte (ping operation, one header only, no payload) to \r\n  *       15 bytes (1 opcode and up to 14 operands following the header). \r\n  * @param  __SIZE__ CEC message size.               \r\n  * @retval Test result (TRUE or FALSE).\r\n  */\r\n#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10)  \r\n                                                 \r\n/** @brief Check CEC device Own Address Register (OAR) setting.\r\n  *        OAR address is written in a 15-bit field within CEC_CFGR register. \r\n  * @param  __ADDRESS__ CEC own address.               \r\n  * @retval Test result (TRUE or FALSE).\r\n  */\r\n#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFF)\r\n\r\n/** @brief Check CEC initiator or destination logical address setting.\r\n  *        Initiator and destination addresses are coded over 4 bits. \r\n  * @param  __ADDRESS__ CEC initiator or logical address.               \r\n  * @retval Test result (TRUE or FALSE).\r\n  */\r\n#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF) \r\n/**\r\n  * @}\r\n  */\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup CEC_Private_Functions CEC Private Functions\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n#endif /* CEC */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_CEC_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_cortex.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of CORTEX HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_CORTEX_H\r\n#define __STM32F7xx_HAL_CORTEX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup CORTEX\r\n  * @{\r\n  */ \r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup CORTEX_Exported_Types Cortex Exported Types\r\n  * @{\r\n  */\r\n\r\n#if (__MPU_PRESENT == 1)\r\n/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition\r\n  * @brief  MPU Region initialization structure \r\n  * @{\r\n  */\r\ntypedef struct\r\n{\r\n  uint8_t                Enable;                /*!< Specifies the status of the region. \r\n                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */\r\n  uint8_t                Number;                /*!< Specifies the number of the region to protect. \r\n                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */\r\n  uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */\r\n  uint8_t                Size;                  /*!< Specifies the size of the region to protect. \r\n                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */\r\n  uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable. \r\n                                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */         \r\n  uint8_t                TypeExtField;          /*!< Specifies the TEX field level.\r\n                                                     This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */                 \r\n  uint8_t                AccessPermission;      /*!< Specifies the region access permission type. \r\n                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */\r\n  uint8_t                DisableExec;           /*!< Specifies the instruction access status. \r\n                                                     This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */\r\n  uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region. \r\n                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */\r\n  uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected. \r\n                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */\r\n  uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region. \r\n                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */\r\n}MPU_Region_InitTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n#endif /* __MPU_PRESENT */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group\r\n  * @{\r\n  */\r\n#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007U) /*!< 0 bits for pre-emption priority\r\n                                                                 4 bits for subpriority */\r\n#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006U) /*!< 1 bits for pre-emption priority\r\n                                                                 3 bits for subpriority */\r\n#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005U) /*!< 2 bits for pre-emption priority\r\n                                                                 2 bits for subpriority */\r\n#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004U) /*!< 3 bits for pre-emption priority\r\n                                                                 1 bits for subpriority */\r\n#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003U) /*!< 4 bits for pre-emption priority\r\n                                                                 0 bits for subpriority */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source \r\n  * @{\r\n  */\r\n#define SYSTICK_CLKSOURCE_HCLK_DIV8    ((uint32_t)0x00000000U)\r\n#define SYSTICK_CLKSOURCE_HCLK         ((uint32_t)0x00000004U)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#if (__MPU_PRESENT == 1)\r\n/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control\r\n  * @{\r\n  */\r\n#define  MPU_HFNMI_PRIVDEF_NONE      ((uint32_t)0x00000000U)  \r\n#define  MPU_HARDFAULT_NMI           ((uint32_t)0x00000002U)\r\n#define  MPU_PRIVILEGED_DEFAULT      ((uint32_t)0x00000004U)\r\n#define  MPU_HFNMI_PRIVDEF           ((uint32_t)0x00000006U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable\r\n  * @{\r\n  */\r\n#define  MPU_REGION_ENABLE     ((uint8_t)0x01U)\r\n#define  MPU_REGION_DISABLE    ((uint8_t)0x00U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access\r\n  * @{\r\n  */\r\n#define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00U)\r\n#define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable\r\n  * @{\r\n  */\r\n#define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01U)\r\n#define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable\r\n  * @{\r\n  */\r\n#define  MPU_ACCESS_CACHEABLE         ((uint8_t)0x01U)\r\n#define  MPU_ACCESS_NOT_CACHEABLE     ((uint8_t)0x00U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable\r\n  * @{\r\n  */\r\n#define  MPU_ACCESS_BUFFERABLE         ((uint8_t)0x01U)\r\n#define  MPU_ACCESS_NOT_BUFFERABLE     ((uint8_t)0x00U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels\r\n  * @{\r\n  */\r\n#define  MPU_TEX_LEVEL0    ((uint8_t)0x00U)\r\n#define  MPU_TEX_LEVEL1    ((uint8_t)0x01U)\r\n#define  MPU_TEX_LEVEL2    ((uint8_t)0x02U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size\r\n  * @{\r\n  */\r\n#define   MPU_REGION_SIZE_32B      ((uint8_t)0x04U)\r\n#define   MPU_REGION_SIZE_64B      ((uint8_t)0x05U)\r\n#define   MPU_REGION_SIZE_128B     ((uint8_t)0x06U) \r\n#define   MPU_REGION_SIZE_256B     ((uint8_t)0x07U) \r\n#define   MPU_REGION_SIZE_512B     ((uint8_t)0x08U) \r\n#define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09U)  \r\n#define   MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU)\r\n#define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) \r\n#define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) \r\n#define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) \r\n#define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) \r\n#define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) \r\n#define   MPU_REGION_SIZE_128KB    ((uint8_t)0x10U)\r\n#define   MPU_REGION_SIZE_256KB    ((uint8_t)0x11U)\r\n#define   MPU_REGION_SIZE_512KB    ((uint8_t)0x12U)\r\n#define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) \r\n#define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) \r\n#define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) \r\n#define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) \r\n#define   MPU_REGION_SIZE_16MB     ((uint8_t)0x17U)\r\n#define   MPU_REGION_SIZE_32MB     ((uint8_t)0x18U)\r\n#define   MPU_REGION_SIZE_64MB     ((uint8_t)0x19U)\r\n#define   MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU)\r\n#define   MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU)\r\n#define   MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU)\r\n#define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) \r\n#define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) \r\n#define   MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU)\r\n/**                                \r\n  * @}\r\n  */\r\n   \r\n/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes \r\n  * @{\r\n  */\r\n#define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00U)  \r\n#define  MPU_REGION_PRIV_RW        ((uint8_t)0x01U) \r\n#define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02U)  \r\n#define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03U)  \r\n#define  MPU_REGION_PRIV_RO        ((uint8_t)0x05U) \r\n#define  MPU_REGION_PRIV_RO_URO    ((uint8_t)0x06U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number\r\n  * @{\r\n  */\r\n#define  MPU_REGION_NUMBER0    ((uint8_t)0x00U)  \r\n#define  MPU_REGION_NUMBER1    ((uint8_t)0x01U) \r\n#define  MPU_REGION_NUMBER2    ((uint8_t)0x02U)  \r\n#define  MPU_REGION_NUMBER3    ((uint8_t)0x03U)  \r\n#define  MPU_REGION_NUMBER4    ((uint8_t)0x04U) \r\n#define  MPU_REGION_NUMBER5    ((uint8_t)0x05U)\r\n#define  MPU_REGION_NUMBER6    ((uint8_t)0x06U)\r\n#define  MPU_REGION_NUMBER7    ((uint8_t)0x07U)\r\n/**\r\n  * @}\r\n  */\r\n#endif /* __MPU_PRESENT */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/* Exported Macros -----------------------------------------------------------*/\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup CORTEX_Exported_Functions\r\n  * @{\r\n  */\r\n  \r\n/** @addtogroup CORTEX_Exported_Functions_Group1\r\n * @{\r\n */\r\n/* Initialization and de-initialization functions *****************************/\r\nvoid HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);\r\nvoid HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);\r\nvoid HAL_NVIC_EnableIRQ(IRQn_Type IRQn);\r\nvoid HAL_NVIC_DisableIRQ(IRQn_Type IRQn);\r\nvoid HAL_NVIC_SystemReset(void);\r\nuint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup CORTEX_Exported_Functions_Group2\r\n * @{\r\n */\r\n/* Peripheral Control functions ***********************************************/\r\n#if (__MPU_PRESENT == 1)\r\nvoid HAL_MPU_Enable(uint32_t MPU_Control);\r\nvoid HAL_MPU_Disable(void);\r\nvoid HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);\r\n#endif /* __MPU_PRESENT */\r\nuint32_t HAL_NVIC_GetPriorityGrouping(void);\r\nvoid HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);\r\nuint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);\r\nvoid HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);\r\nvoid HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);\r\nuint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);\r\nvoid HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);\r\nvoid HAL_SYSTICK_IRQHandler(void);\r\nvoid HAL_SYSTICK_Callback(void);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private types -------------------------------------------------------------*/ \r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup CORTEX_Private_Macros CORTEX Private Macros\r\n  * @{\r\n  */\r\n#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \\\r\n                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \\\r\n                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \\\r\n                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \\\r\n                                       ((GROUP) == NVIC_PRIORITYGROUP_4))\r\n\r\n#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10U)\r\n\r\n#define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10U)\r\n\r\n#define IS_NVIC_DEVICE_IRQ(IRQ)                ((IRQ) >= 0x00)\r\n\r\n#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \\\r\n                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))\r\n\r\n#if (__MPU_PRESENT == 1)\r\n#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \\\r\n                                     ((STATE) == MPU_REGION_DISABLE))\r\n\r\n#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \\\r\n                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))\r\n\r\n#define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \\\r\n                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))\r\n\r\n#define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \\\r\n                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))\r\n\r\n#define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \\\r\n                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))\r\n\r\n#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \\\r\n                                ((TYPE) == MPU_TEX_LEVEL1)  || \\\r\n                                ((TYPE) == MPU_TEX_LEVEL2))\r\n\r\n#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \\\r\n                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \\\r\n                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \\\r\n                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \\\r\n                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \\\r\n                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))\r\n\r\n#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \\\r\n                                         ((NUMBER) == MPU_REGION_NUMBER1) || \\\r\n                                         ((NUMBER) == MPU_REGION_NUMBER2) || \\\r\n                                         ((NUMBER) == MPU_REGION_NUMBER3) || \\\r\n                                         ((NUMBER) == MPU_REGION_NUMBER4) || \\\r\n                                         ((NUMBER) == MPU_REGION_NUMBER5) || \\\r\n                                         ((NUMBER) == MPU_REGION_NUMBER6) || \\\r\n                                         ((NUMBER) == MPU_REGION_NUMBER7))\r\n\r\n#define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_64B)   || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_128B)  || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_256B)  || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_4GB))\r\n\r\n#define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FFU)\r\n#endif /* __MPU_PRESENT */\r\n\r\n/**                                                                          \r\n  * @}\r\n  */                                                                            \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_CORTEX_H */\r\n \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_crc.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_crc.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of CRC HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_CRC_H\r\n#define __STM32F7xx_HAL_CRC_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CRC CRC\r\n  * @brief CRC HAL module driver\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup CRC_Exported_Types CRC Exported Types\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CRC_Exported_Types_Group1 CRC State Structure definition \r\n  * @{\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_CRC_STATE_RESET     = 0x00U,  /*!< CRC not yet initialized or disabled */\r\n  HAL_CRC_STATE_READY     = 0x01U,  /*!< CRC initialized and ready for use   */\r\n  HAL_CRC_STATE_BUSY      = 0x02U,  /*!< CRC internal process is ongoing     */\r\n  HAL_CRC_STATE_TIMEOUT   = 0x03U,  /*!< CRC timeout state                   */\r\n  HAL_CRC_STATE_ERROR     = 0x04U   /*!< CRC error state                     */\r\n}HAL_CRC_StateTypeDef;\r\n/** \r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRC_Exported_Types_Group2 CRC Init Structure definition  \r\n  * @{\r\n  */\r\ntypedef struct\r\n{\r\n  uint8_t DefaultPolynomialUse;       /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.  \r\n                                            If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default \r\n                                            X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1. \r\n                                            In that case, there is no need to set GeneratingPolynomial field.\r\n                                            If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set */\r\n\r\n  uint8_t DefaultInitValueUse;        /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used. \r\n                                           If set to DEFAULT_INIT_VALUE_ENABLE, resort to default\r\n                                           0xFFFFFFFF value. In that case, there is no need to set InitValue field.   \r\n                                           If otherwise set to DEFAULT_INIT_VALUE_DISABLE,  InitValue field must be set */\r\n\r\n  uint32_t GeneratingPolynomial;      /*!< Set CRC generating polynomial. 7, 8, 16 or 32-bit long value for a polynomial degree\r\n                                           respectively equal to 7, 8, 16 or 32. This field is written in normal representation, \r\n                                           e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65.\r\n                                           No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE   */                                                \r\n\r\n  uint32_t CRCLength;                 /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.\r\n                                           Value can be either one of\r\n                                           CRC_POLYLENGTH_32B                  (32-bit CRC)\r\n                                           CRC_POLYLENGTH_16B                  (16-bit CRC)\r\n                                           CRC_POLYLENGTH_8B                   (8-bit CRC)\r\n                                           CRC_POLYLENGTH_7B                   (7-bit CRC) */\r\n                                              \r\n  uint32_t InitValue;                 /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse \r\n                                           is set to DEFAULT_INIT_VALUE_ENABLE   */                                                \r\n  \r\n  uint32_t InputDataInversionMode;    /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode. \r\n                                           Can be either one of the following values \r\n                                           CRC_INPUTDATA_INVERSION_NONE      no input data inversion\r\n                                           CRC_INPUTDATA_INVERSION_BYTE      byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2\r\n                                           CRC_INPUTDATA_INVERSION_HALFWORD  halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C\r\n                                           CRC_INPUTDATA_INVERSION_WORD      word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */  \r\n                                              \r\n  uint32_t OutputDataInversionMode;   /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.\r\n                                            Can be either \r\n                                            CRC_OUTPUTDATA_INVERSION_DISABLE   no CRC inversion, or\r\n                                            CRC_OUTPUTDATA_INVERSION_ENABLE    CRC 0x11223344 is converted into 0x22CC4488 */\r\n}CRC_InitTypeDef;\r\n/** \r\n  * @}\r\n  */\r\n  \r\n/** @defgroup CRC_Exported_Types_Group3 CRC Handle Structure definition   \r\n  * @{\r\n  */\r\ntypedef struct\r\n{\r\n  CRC_TypeDef                 *Instance;   /*!< Register base address        */ \r\n  \r\n  CRC_InitTypeDef             Init;        /*!< CRC configuration parameters */\r\n  \r\n  HAL_LockTypeDef             Lock;        /*!< CRC Locking object           */\r\n    \r\n  __IO HAL_CRC_StateTypeDef   State;       /*!< CRC communication state      */\r\n  \r\n  uint32_t InputDataFormat;                /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format. \r\n                                            Can be either \r\n                                            CRC_INPUTDATA_FORMAT_BYTES       input data is a stream of bytes (8-bit data)\r\n                                            CRC_INPUTDATA_FORMAT_HALFWORDS   input data is a stream of half-words (16-bit data)\r\n                                            CRC_INPUTDATA_FORMAT_WORDS       input data is a stream of words (32-bits data)                                                                                        \r\n                                           Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error\r\n                                           must occur if InputBufferFormat is not one of the three values listed above  */ \r\n}CRC_HandleTypeDef;\r\n/** \r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup CRC_Exported_Constants   CRC exported constants\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup CRC_Default_Polynomial_Value    Default CRC generating polynomial\r\n  * @{\r\n  */\r\n#define DEFAULT_CRC32_POLY      0x04C11DB7U\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRC_Default_InitValue    Default CRC computation initialization value\r\n  * @{\r\n  */\r\n#define DEFAULT_CRC_INITVALUE   0xFFFFFFFFU\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRC_Default_Polynomial    Indicates whether or not default polynomial is used\r\n  * @{\r\n  */\r\n#define DEFAULT_POLYNOMIAL_ENABLE       ((uint8_t)0x00U)\r\n#define DEFAULT_POLYNOMIAL_DISABLE      ((uint8_t)0x01U)\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n \r\n/** @defgroup CRC_Default_InitValue_Use    Indicates whether or not default init value is used\r\n  * @{\r\n  */                                      \r\n#define DEFAULT_INIT_VALUE_ENABLE      ((uint8_t)0x00U)\r\n#define DEFAULT_INIT_VALUE_DISABLE     ((uint8_t)0x01U)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP\r\n  * @{\r\n  */\r\n#define CRC_POLYLENGTH_32B                  ((uint32_t)0x00000000U)\r\n#define CRC_POLYLENGTH_16B                  ((uint32_t)CRC_CR_POLYSIZE_0)\r\n#define CRC_POLYLENGTH_8B                   ((uint32_t)CRC_CR_POLYSIZE_1)\r\n#define CRC_POLYLENGTH_7B                   ((uint32_t)CRC_CR_POLYSIZE)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions\r\n  * @{\r\n  */\r\n#define HAL_CRC_LENGTH_32B     32U\r\n#define HAL_CRC_LENGTH_16B     16U\r\n#define HAL_CRC_LENGTH_8B       8U\r\n#define HAL_CRC_LENGTH_7B       7U\r\n\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup CRC_Input_Buffer_Format CRC input buffer format\r\n  * @{\r\n  */\r\n/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but\r\n * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set \r\n * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for \r\n * the CRC APIs to provide a correct result */   \r\n#define CRC_INPUTDATA_FORMAT_UNDEFINED             ((uint32_t)0x00000000U)\r\n#define CRC_INPUTDATA_FORMAT_BYTES                 ((uint32_t)0x00000001U)\r\n#define CRC_INPUTDATA_FORMAT_HALFWORDS             ((uint32_t)0x00000002U)\r\n#define CRC_INPUTDATA_FORMAT_WORDS                 ((uint32_t)0x00000003U)\r\n/** \r\n  * @}\r\n  */   \r\n\r\n/** \r\n  * @}\r\n  */ \r\n/* Exported macros -----------------------------------------------------------*/\r\n\r\n/** @defgroup CRC_Exported_Macros CRC exported macros\r\n  * @{\r\n  */\r\n\r\n/** @brief Reset CRC handle state\r\n  * @param  __HANDLE__ CRC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)\r\n\r\n/**\r\n  * @brief  Reset CRC Data Register.\r\n  * @param  __HANDLE__ CRC handle\r\n  * @retval None.\r\n  */\r\n#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)\r\n\r\n/**\r\n  * @brief  Set CRC INIT non-default value\r\n  * @param  __HANDLE__     CRC handle\r\n  * @param  __INIT__       32-bit initial value  \r\n  * @retval None.\r\n  */\r\n#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))    \r\n\r\n/**\r\n  * @brief Stores a 8-bit data in the Independent Data(ID) register.\r\n  * @param __HANDLE__ CRC handle\r\n  * @param __VALUE__ 8-bit value to be stored in the ID register\r\n  * @retval None\r\n  */\r\n#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, CRC_IDR_IDR, (__VALUE__)))\r\n\r\n/**\r\n  * @brief Returns the 8-bit data stored in the Independent Data(ID) register.\r\n  * @param __HANDLE__ CRC handle\r\n  * @retval 8-bit value of the ID register \r\n  */\r\n#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Include CRC HAL Extension module */\r\n#include \"stm32f7xx_hal_crc_ex.h\"\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup CRC_Exported_Functions CRC Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CRC_Exported_Functions_Group1 Initialization/de-initialization functions\r\n  * @{\r\n  */\r\n/* Initialization and de-initialization functions  ****************************/\r\nHAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);\r\nHAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);\r\nvoid HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);\r\nvoid HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Aliases for inter STM32 series compatibility */\r\n#define HAL_CRC_Input_Data_Reverse   HAL_CRCEx_Input_Data_Reverse\r\n#define HAL_CRC_Output_Data_Reverse  HAL_CRCEx_Output_Data_Reverse\r\n\r\n/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions\r\n  * @{\r\n  */\r\n/* Peripheral Control functions ***********************************************/\r\nuint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);\r\nuint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions\r\n  * @{\r\n  */\r\n/* Peripheral State and Error functions ***************************************/\r\nHAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/** @defgroup CRC_Private_Types CRC Private Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private defines -----------------------------------------------------------*/\r\n/** @defgroup CRC_Private_Defines CRC Private Defines\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @defgroup CRC_Private_Variables CRC Private Variables\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup CRC_Private_Constants CRC Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup CRC_Private_Macros CRC Private Macros\r\n  * @{\r\n  */\r\n#define IS_DEFAULT_POLYNOMIAL(__DEFAULT__) (((__DEFAULT__) == DEFAULT_POLYNOMIAL_ENABLE) || \\\r\n                                            ((__DEFAULT__) == DEFAULT_POLYNOMIAL_DISABLE))\r\n#define IS_DEFAULT_INIT_VALUE(__VALUE__)  (((__VALUE__) == DEFAULT_INIT_VALUE_ENABLE) || \\\r\n                                           ((__VALUE__) == DEFAULT_INIT_VALUE_DISABLE))\r\n#define IS_CRC_POL_LENGTH(__LENGTH__)     (((__LENGTH__) == CRC_POLYLENGTH_32B) || \\\r\n                                           ((__LENGTH__) == CRC_POLYLENGTH_16B) || \\\r\n                                           ((__LENGTH__) == CRC_POLYLENGTH_8B)  || \\\r\n                                           ((__LENGTH__) == CRC_POLYLENGTH_7B))\r\n#define IS_CRC_INPUTDATA_FORMAT(__FORMAT__)       (((__FORMAT__) == CRC_INPUTDATA_FORMAT_BYTES) || \\\r\n                                                   ((__FORMAT__) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \\\r\n                                                   ((__FORMAT__) == CRC_INPUTDATA_FORMAT_WORDS))\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions prototypes ----------------------------------------------*/\r\n/** @defgroup CRC_Private_Functions_Prototypes CRC Private Functions Prototypes\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup CRC_Private_Functions CRC Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_CRC_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_crc_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_crc_ex.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of CRC HAL extension module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_CRC_EX_H\r\n#define __STM32F7xx_HAL_CRC_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CRCEx CRCEx\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/ \r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup CRCEx_Exported_Constants CRC Extended exported constants\r\n * @{\r\n */\r\n\r\n/** @defgroup CRCEx_Input_Data_Inversion CRC Extended input data inversion modes\r\n  * @{\r\n  */\r\n#define CRC_INPUTDATA_INVERSION_NONE              ((uint32_t)0x00000000U)\r\n#define CRC_INPUTDATA_INVERSION_BYTE              ((uint32_t)CRC_CR_REV_IN_0)\r\n#define CRC_INPUTDATA_INVERSION_HALFWORD          ((uint32_t)CRC_CR_REV_IN_1)\r\n#define CRC_INPUTDATA_INVERSION_WORD              ((uint32_t)CRC_CR_REV_IN)\r\n\r\n#define IS_CRC_INPUTDATA_INVERSION_MODE(__MODE__)     (((__MODE__) == CRC_INPUTDATA_INVERSION_NONE) || \\\r\n                                                       ((__MODE__) == CRC_INPUTDATA_INVERSION_BYTE) || \\\r\n                                                       ((__MODE__) == CRC_INPUTDATA_INVERSION_HALFWORD) || \\\r\n                                                       ((__MODE__) == CRC_INPUTDATA_INVERSION_WORD))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRCEx_Output_Data_Inversion CRC Extended output data inversion modes\r\n  * @{\r\n  */\r\n#define CRC_OUTPUTDATA_INVERSION_DISABLE         ((uint32_t)0x00000000U)\r\n#define CRC_OUTPUTDATA_INVERSION_ENABLE          ((uint32_t)CRC_CR_REV_OUT)\r\n\r\n#define IS_CRC_OUTPUTDATA_INVERSION_MODE(__MODE__)    (((__MODE__) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \\\r\n                                                       ((__MODE__) == CRC_OUTPUTDATA_INVERSION_ENABLE))\r\n/**                                               \r\n  * @}\r\n  */\r\n\r\n\r\n/**\r\n * @}\r\n */\r\n/* Exported macro ------------------------------------------------------------*/\r\n\r\n/** @defgroup CRCEx_Exported_Macros CRC Extended exported macros\r\n  * @{\r\n  */\r\n    \r\n/**\r\n  * @brief  Set CRC output reversal\r\n  * @param  __HANDLE__     CRC handle\r\n  * @retval None.\r\n  */\r\n#define  __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)   \r\n\r\n/**\r\n  * @brief  Unset CRC output reversal\r\n  * @param  __HANDLE__     CRC handle\r\n  * @retval None.\r\n  */\r\n#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))   \r\n\r\n/**\r\n  * @brief  Set CRC non-default polynomial\r\n  * @param  __HANDLE__     CRC handle\r\n  * @param  __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial  \r\n  * @retval None.\r\n  */\r\n#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CRCEx_Exported_Functions_Group1 Extended CRC features functions\r\n  * @{\r\n  */\r\n/* Exported functions --------------------------------------------------------*/\r\n/* Initialization and de-initialization functions  ****************************/\r\nHAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);\r\nHAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);\r\nHAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);\r\n\r\n/* Peripheral Control functions ***********************************************/\r\n/* Peripheral State and Error functions ***************************************/\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_CRC_EX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cryp.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_cryp.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of CRYP HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_CRYP_H\r\n#define __STM32F7xx_HAL_CRYP_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n#if defined (CRYP)\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup CRYP\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n\r\n/** @defgroup CRYP_Exported_Types CRYP Exported Types\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CRYP_Exported_Types_Group1 CRYP Configuration Structure definition\r\n  * @{\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  uint32_t DataType;    /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.\r\n                             This parameter can be a value of @ref CRYP_Data_Type */\r\n\r\n  uint32_t KeySize;     /*!< Used only in AES mode only : 128, 192 or 256 bit key length. \r\n                             This parameter can be a value of @ref CRYP_Key_Size */\r\n\r\n  uint8_t* pKey;        /*!< The key used for encryption/decryption */\r\n\r\n  uint8_t* pInitVect;   /*!< The initialization vector used also as initialization\r\n                             counter in CTR mode */\r\n\r\n  uint8_t IVSize;       /*!< The size of initialization vector. \r\n                             This parameter (called nonce size in CCM) is used only \r\n                             in AES-128/192/256 encryption/decryption CCM mode */\r\n\r\n  uint8_t TagSize;      /*!< The size of returned authentication TAG. \r\n                             This parameter is used only in AES-128/192/256 \r\n                             encryption/decryption CCM mode */\r\n\r\n  uint8_t* Header;      /*!< The header used in GCM and CCM modes */\r\n\r\n  uint32_t HeaderSize;  /*!< The size of header buffer in bytes */\r\n\r\n  uint8_t* pScratch;    /*!< Scratch buffer used to append the header. It's size must be equal to header size + 21 bytes.\r\n                             This parameter is used only in AES-128/192/256 encryption/decryption CCM mode */\r\n}CRYP_InitTypeDef;\r\n\r\n/** \r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRYP_Exported_Types_Group2 CRYP State structures definition\r\n  * @{\r\n  */\r\n    \r\n\r\ntypedef enum\r\n{\r\n  HAL_CRYP_STATE_RESET             = 0x00U,  /*!< CRYP not yet initialized or disabled  */\r\n  HAL_CRYP_STATE_READY             = 0x01U,  /*!< CRYP initialized and ready for use    */\r\n  HAL_CRYP_STATE_BUSY              = 0x02U,  /*!< CRYP internal processing is ongoing   */\r\n  HAL_CRYP_STATE_TIMEOUT           = 0x03U,  /*!< CRYP timeout state                    */\r\n  HAL_CRYP_STATE_ERROR             = 0x04U   /*!< CRYP error state                      */\r\n}HAL_CRYP_STATETypeDef;\r\n\r\n/** \r\n  * @}\r\n  */\r\n  \r\n/** @defgroup CRYP_Exported_Types_Group3 CRYP phase structures definition\r\n  * @{\r\n  */\r\n    \r\n\r\ntypedef enum\r\n{\r\n  HAL_CRYP_PHASE_READY             = 0x01U,    /*!< CRYP peripheral is ready for initialization. */\r\n  HAL_CRYP_PHASE_PROCESS           = 0x02U,    /*!< CRYP peripheral is in processing phase */\r\n  HAL_CRYP_PHASE_FINAL             = 0x03U     /*!< CRYP peripheral is in final phase\r\n                                                   This is relevant only with CCM and GCM modes */\r\n}HAL_PhaseTypeDef;\r\n\r\n/** \r\n  * @}\r\n  */\r\n  \r\n/** @defgroup CRYP_Exported_Types_Group4 CRYP handle Structure definition\r\n  * @{\r\n  */\r\n  \r\ntypedef struct\r\n{\r\n      CRYP_TypeDef             *Instance;        /*!< CRYP registers base address */\r\n\r\n      CRYP_InitTypeDef         Init;             /*!< CRYP required parameters */\r\n\r\n      uint8_t                  *pCrypInBuffPtr;  /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */\r\n\r\n      uint8_t                  *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */\r\n\r\n      __IO uint16_t            CrypInCount;      /*!< Counter of input data */\r\n\r\n      __IO uint16_t            CrypOutCount;     /*!< Counter of output data */\r\n\r\n      HAL_StatusTypeDef        Status;           /*!< CRYP peripheral status */\r\n\r\n      HAL_PhaseTypeDef         Phase;            /*!< CRYP peripheral phase */\r\n\r\n      DMA_HandleTypeDef        *hdmain;          /*!< CRYP In DMA handle parameters */\r\n\r\n      DMA_HandleTypeDef        *hdmaout;         /*!< CRYP Out DMA handle parameters */\r\n\r\n      HAL_LockTypeDef          Lock;             /*!< CRYP locking object */\r\n\r\n   __IO  HAL_CRYP_STATETypeDef State;            /*!< CRYP peripheral state */\r\n}CRYP_HandleTypeDef;\r\n\r\n/** \r\n  * @}\r\n  */\r\n\r\n/** \r\n  * @}\r\n  */\r\n    \r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup CRYP_Exported_Constants CRYP Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CRYP_Key_Size CRYP Key Size\r\n  * @{\r\n  */\r\n#define CRYP_KEYSIZE_128B         ((uint32_t)0x00000000U)\r\n#define CRYP_KEYSIZE_192B         CRYP_CR_KEYSIZE_0\r\n#define CRYP_KEYSIZE_256B         CRYP_CR_KEYSIZE_1\r\n/**                                \r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRYP_Data_Type CRYP Data Type\r\n  * @{\r\n  */\r\n#define CRYP_DATATYPE_32B         ((uint32_t)0x00000000U)\r\n#define CRYP_DATATYPE_16B         CRYP_CR_DATATYPE_0\r\n#define CRYP_DATATYPE_8B          CRYP_CR_DATATYPE_1\r\n#define CRYP_DATATYPE_1B          CRYP_CR_DATATYPE\r\n/**                                \r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRYP_Exported_Constants_Group3 CRYP CRYP_AlgoModeDirection\r\n  * @{\r\n  */\r\n#define CRYP_CR_ALGOMODE_DIRECTION         ((uint32_t)0x0008003CU)\r\n#define CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT  ((uint32_t)0x00000000U)\r\n#define CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT  ((uint32_t)0x00000004U)\r\n#define CRYP_CR_ALGOMODE_TDES_CBC_ENCRYPT  ((uint32_t)0x00000008U)\r\n#define CRYP_CR_ALGOMODE_TDES_CBC_DECRYPT  ((uint32_t)0x0000000CU)\r\n#define CRYP_CR_ALGOMODE_DES_ECB_ENCRYPT   ((uint32_t)0x00000010U)\r\n#define CRYP_CR_ALGOMODE_DES_ECB_DECRYPT   ((uint32_t)0x00000014U)\r\n#define CRYP_CR_ALGOMODE_DES_CBC_ENCRYPT   ((uint32_t)0x00000018U)\r\n#define CRYP_CR_ALGOMODE_DES_CBC_DECRYPT   ((uint32_t)0x0000001CU)\r\n#define CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT   ((uint32_t)0x00000020U)\r\n#define CRYP_CR_ALGOMODE_AES_ECB_DECRYPT   ((uint32_t)0x00000024U)\r\n#define CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT   ((uint32_t)0x00000028U)\r\n#define CRYP_CR_ALGOMODE_AES_CBC_DECRYPT   ((uint32_t)0x0000002CU)\r\n#define CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT   ((uint32_t)0x00000030U)\r\n#define CRYP_CR_ALGOMODE_AES_CTR_DECRYPT   ((uint32_t)0x00000034U)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup CRYP_Exported_Constants_Group4 CRYP CRYP_Interrupt\r\n  * @{\r\n  */\r\n#define CRYP_IT_INI               ((uint32_t)CRYP_IMSCR_INIM)   /*!< Input FIFO Interrupt */\r\n#define CRYP_IT_OUTI              ((uint32_t)CRYP_IMSCR_OUTIM)  /*!< Output FIFO Interrupt */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRYP_Exported_Constants_Group5 CRYP CRYP_Flags\r\n  * @{\r\n  */\r\n#define CRYP_FLAG_BUSY   ((uint32_t)0x00000010U)  /*!< The CRYP core is currently \r\n                                                     processing a block of data \r\n                                                     or a key preparation (for \r\n                                                     AES decryption). */\r\n#define CRYP_FLAG_IFEM   ((uint32_t)0x00000001U)  /*!< Input FIFO is empty */\r\n#define CRYP_FLAG_IFNF   ((uint32_t)0x00000002U)  /*!< Input FIFO is not Full */\r\n#define CRYP_FLAG_OFNE   ((uint32_t)0x00000004U)  /*!< Output FIFO is not empty */\r\n#define CRYP_FLAG_OFFU   ((uint32_t)0x00000008U)  /*!< Output FIFO is Full */\r\n#define CRYP_FLAG_OUTRIS ((uint32_t)0x01000002U)  /*!< Output FIFO service raw \r\n                                                      interrupt status */\r\n#define CRYP_FLAG_INRIS  ((uint32_t)0x01000001U)  /*!< Input FIFO service raw \r\n                                                      interrupt status */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup CRYP_Exported_Macros CRYP Exported Macros\r\n  * @{\r\n  */\r\n  \r\n/** @brief Reset CRYP handle state\r\n  * @param  __HANDLE__ specifies the CRYP handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)\r\n\r\n/**\r\n  * @brief  Enable/Disable the CRYP peripheral.\r\n  * @param  __HANDLE__ specifies the CRYP handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_CRYP_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  CRYP_CR_CRYPEN)\r\n#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &=  ~CRYP_CR_CRYPEN)\r\n\r\n/**\r\n  * @brief  Flush the data FIFO.\r\n  * @param  __HANDLE__ specifies the CRYP handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |=  CRYP_CR_FFLUSH)\r\n\r\n/**\r\n  * @brief  Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC.\r\n  * @param  __HANDLE__ specifies the CRYP handle.\r\n  * @param  MODE The algorithm mode.\r\n  * @retval None\r\n  */\r\n#define __HAL_CRYP_SET_MODE(__HANDLE__, MODE)  ((__HANDLE__)->Instance->CR |= (uint32_t)(MODE))\r\n\r\n/** @brief  Check whether the specified CRYP flag is set or not.\r\n  * @param  __HANDLE__ specifies the CRYP handle.\r\n  * @param  __FLAG__ specifies the flag to check.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data \r\n  *                                 or a key preparation (for AES decryption). \r\n  *            @arg CRYP_FLAG_IFEM: Input FIFO is empty\r\n  *            @arg CRYP_FLAG_IFNF: Input FIFO is not full\r\n  *            @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending\r\n  *            @arg CRYP_FLAG_OFNE: Output FIFO is not empty\r\n  *            @arg CRYP_FLAG_OFFU: Output FIFO is full\r\n  *            @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending\r\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\r\n  */\r\n\r\n#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \\\r\n                                                 ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))\r\n\r\n/** @brief  Check whether the specified CRYP interrupt is set or not.\r\n  * @param  __HANDLE__ specifies the CRYP handle.\r\n  * @param  __INTERRUPT__ specifies the interrupt to check.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg CRYP_IT_INRIS: Input FIFO service raw interrupt is pending\r\n  *            @arg CRYP_IT_OUTRIS: Output FIFO service raw interrupt is pending\r\n  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Enable the CRYP interrupt.\r\n  * @param  __HANDLE__ specifies the CRYP handle.\r\n  * @param  __INTERRUPT__ CRYP Interrupt.\r\n  * @retval None\r\n  */\r\n#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disable the CRYP interrupt.\r\n  * @param  __HANDLE__ specifies the CRYP handle.\r\n  * @param  __INTERRUPT__ CRYP interrupt.\r\n  * @retval None\r\n  */\r\n#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__))\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/* Include CRYP HAL Extension module */\r\n#include \"stm32f7xx_hal_cryp_ex.h\"\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup CRYP_Exported_Functions CRYP Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup CRYP_Exported_Functions_Group1\r\n  * @{\r\n  */    \r\nHAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);\r\nHAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);\r\nvoid HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);\r\nvoid HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @addtogroup CRYP_Exported_Functions_Group2\r\n  * @{\r\n  */  \r\n/* AES encryption/decryption using polling  ***********************************/\r\nHAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);\r\n\r\n/* AES encryption/decryption using interrupt  *********************************/\r\nHAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\nHAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\nHAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\n\r\n/* AES encryption/decryption using DMA  ***************************************/\r\nHAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\nHAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\nHAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @addtogroup CRYP_Exported_Functions_Group3\r\n  * @{\r\n  */  \r\n/* DES encryption/decryption using polling  ***********************************/\r\nHAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);\r\n\r\n/* DES encryption/decryption using interrupt  *********************************/\r\nHAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\nHAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\n\r\n/* DES encryption/decryption using DMA  ***************************************/\r\nHAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\nHAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @addtogroup CRYP_Exported_Functions_Group4\r\n  * @{\r\n  */  \r\n/* TDES encryption/decryption using polling  **********************************/\r\nHAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);\r\n\r\n/* TDES encryption/decryption using interrupt  ********************************/\r\nHAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\nHAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\n\r\n/* TDES encryption/decryption using DMA  **************************************/\r\nHAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\nHAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @addtogroup CRYP_Exported_Functions_Group5\r\n  * @{\r\n  */  \r\nvoid HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);\r\nvoid HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);\r\nvoid HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @addtogroup CRYP_Exported_Functions_Group6\r\n  * @{\r\n  */  \r\nvoid HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @addtogroup CRYP_Exported_Functions_Group7\r\n  * @{\r\n  */  \r\nHAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/** @defgroup CRYP_Private_Types CRYP Private Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @defgroup CRYP_Private_Variables CRYP Private Variables\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup CRYP_Private_Constants CRYP Private Constants\r\n  * @{\r\n  */\r\n#define CRYP_FLAG_MASK  ((uint32_t)0x0000001F)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup CRYP_Private_Macros CRYP Private Macros\r\n  * @{\r\n  */\r\n\r\n#define IS_CRYP_KEYSIZE(__KEYSIZE__)  (((__KEYSIZE__) == CRYP_KEYSIZE_128B)  || \\\r\n                                       ((__KEYSIZE__) == CRYP_KEYSIZE_192B)  || \\\r\n                                       ((__KEYSIZE__) == CRYP_KEYSIZE_256B))\r\n\r\n\r\n#define IS_CRYP_DATATYPE(__DATATYPE__) (((__DATATYPE__) == CRYP_DATATYPE_32B) || \\\r\n                                        ((__DATATYPE__) == CRYP_DATATYPE_16B) || \\\r\n                                        ((__DATATYPE__) == CRYP_DATATYPE_8B)  || \\\r\n                                        ((__DATATYPE__) == CRYP_DATATYPE_1B))  \r\n\r\n\r\n /**\r\n  * @}\r\n  */ \r\n  \r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup CRYP_Private_Functions CRYP Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n     \r\n/**\r\n  * @}\r\n  */ \r\n\r\n#endif /* CRYP */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n#if defined (AES)\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup CRYP\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup CRYP_Exported_Types CRYP Exported Types\r\n  * @{\r\n  */\r\n\r\n/** \r\n  * @brief  CRYP Configuration Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t DataType;       /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.\r\n                             This parameter can be a value of @ref CRYP_Data_Type */\r\n\r\n  uint32_t KeySize;        /*!< 128 or 256-bit key length. \r\n                             This parameter can be a value of @ref CRYP_Key_Size */\r\n                             \r\n  uint32_t OperatingMode;  /*!< AES operating mode. \r\n                             This parameter can be a value of @ref CRYP_AES_OperatingMode */\r\n                             \r\n  uint32_t ChainingMode;   /*!< AES chaining mode. \r\n                             This parameter can be a value of @ref CRYP_AES_ChainingMode */\r\n                             \r\n  uint32_t KeyWriteFlag;   /*!< Allows to bypass or not key write-up before decryption. \r\n                             This parameter can be a value of @ref CRYP_Key_Write */                             \r\n                             \r\n  uint32_t GCMCMACPhase;   /*!< Indicates the processing phase of the Galois Counter Mode (GCM), \r\n                             Galois Message Authentication Code (GMAC) or Cipher Message \r\n                             Authentication Code (CMAC) or Counter with Cipher Mode (CCM) when\r\n                             the latter is applicable.\r\n                             This parameter can be a value of @ref CRYP_GCM_CMAC_Phase */                                                                                          \r\n\r\n  uint8_t* pKey;           /*!< Encryption/Decryption Key */\r\n\r\n  uint8_t* pInitVect;      /*!< Initialization Vector used for CTR, CBC, GCM/GMAC, CMAC, \r\n                                (and CCM when applicable) modes */\r\n\r\n  uint8_t* Header;         /*!< Header used in GCM/GMAC, CMAC (and CCM when applicable) modes */\r\n\r\n  uint64_t HeaderSize;     /*!< Header size in bytes */\r\n                                                     \r\n}CRYP_InitTypeDef;\r\n\r\n/** \r\n  * @brief HAL CRYP State structures definition\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_CRYP_STATE_RESET             = 0x00,  /*!< CRYP not yet initialized or disabled  */\r\n  HAL_CRYP_STATE_READY             = 0x01,  /*!< CRYP initialized and ready for use    */\r\n  HAL_CRYP_STATE_BUSY              = 0x02,  /*!< CRYP internal processing is ongoing   */\r\n  HAL_CRYP_STATE_TIMEOUT           = 0x03,  /*!< CRYP timeout state                    */\r\n  HAL_CRYP_STATE_ERROR             = 0x04,  /*!< CRYP error state                      */\r\n  HAL_CRYP_STATE_SUSPENDED         = 0x05   /*!< CRYP suspended                        */\r\n}HAL_CRYP_STATETypeDef;\r\n\r\n/** \r\n  * @brief HAL CRYP phase structures definition\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_CRYP_PHASE_READY             = 0x01,    /*!< CRYP peripheral is ready for initialization.           */\r\n  HAL_CRYP_PHASE_PROCESS           = 0x02,    /*!< CRYP peripheral is in processing phase                 */\r\n  HAL_CRYP_PHASE_START             = 0x03,    /*!< CRYP peripheral has been initialized but \r\n                                                 GCM/GMAC/CMAC(/CCM) initialization phase has not started */\r\n  HAL_CRYP_PHASE_INIT_OVER         = 0x04,    /*!< GCM/GMAC/CMAC(/CCM) init phase has been carried out    */ \r\n  HAL_CRYP_PHASE_HEADER_OVER       = 0x05,    /*!< GCM/GMAC/CMAC(/CCM) header phase has been carried out  */ \r\n  HAL_CRYP_PHASE_PAYLOAD_OVER      = 0x06,    /*!< GCM(/CCM) payload phase has been carried out           */ \r\n  HAL_CRYP_PHASE_FINAL_OVER        = 0x07,    /*!< GCM/GMAC/CMAC(/CCM) final phase has been carried out   */\r\n  HAL_CRYP_PHASE_HEADER_SUSPENDED  = 0x08,    /*!< GCM/GMAC/CMAC(/CCM) header phase has been suspended    */\r\n  HAL_CRYP_PHASE_PAYLOAD_SUSPENDED = 0x09,    /*!< GCM(/CCM) payload phase has been suspended             */  \r\n  HAL_CRYP_PHASE_NOT_USED          = 0x0a     /*!< Phase is irrelevant to the current chaining mode       */                                                                                                                                                                                                                                                                   \r\n}HAL_PhaseTypeDef;\r\n\r\n/** \r\n  * @brief HAL CRYP mode suspend definitions\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_CRYP_SUSPEND_NONE            = 0x00,    /*!< CRYP peripheral suspension not requested */\r\n  HAL_CRYP_SUSPEND                 = 0x01     /*!< CRYP peripheral suspension requested     */                                                                                                                                                                                                                                                                  \r\n}HAL_SuspendTypeDef;\r\n\r\n\r\n/** \r\n  * @brief  HAL CRYP Error Codes definition  \r\n  */ \r\n#define HAL_CRYP_ERROR_NONE      ((uint32_t)0x00000000)  /*!< No error        */\r\n#define HAL_CRYP_WRITE_ERROR     ((uint32_t)0x00000001)  /*!< Write error     */\r\n#define HAL_CRYP_READ_ERROR      ((uint32_t)0x00000002)  /*!< Read error      */\r\n#define HAL_CRYP_DMA_ERROR       ((uint32_t)0x00000004)  /*!< DMA error       */  \r\n#define HAL_CRYP_BUSY_ERROR      ((uint32_t)0x00000008)  /*!< Busy flag error */  \r\n\r\n/** \r\n  * @brief  CRYP handle Structure definition\r\n  */ \r\ntypedef struct\r\n{\r\n      AES_TypeDef              *Instance;        /*!< Register base address        */\r\n\r\n      CRYP_InitTypeDef         Init;             /*!< CRYP initialization parameters */\r\n\r\n      uint8_t                  *pCrypInBuffPtr;  /*!< Pointer to CRYP processing (encryption, decryption,...) input buffer */\r\n\r\n      uint8_t                  *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) output buffer */\r\n\r\n      uint32_t                 CrypInCount;      /*!< Input data size in bytes or, after suspension, the remaining \r\n                                                       number of bytes to process */\r\n\r\n      uint32_t                 CrypOutCount;     /*!< Output data size in bytes */\r\n\r\n      HAL_PhaseTypeDef         Phase;            /*!< CRYP peripheral processing phase for GCM, GMAC, CMAC \r\n                                                    (or CCM when applicable) modes.\r\n                                                     Indicates the last phase carried out to ease\r\n                                                     phase transitions  */\r\n\r\n      DMA_HandleTypeDef        *hdmain;          /*!< CRYP peripheral Input DMA handle parameters */\r\n\r\n      DMA_HandleTypeDef        *hdmaout;         /*!< CRYP peripheral Output DMA handle parameters */\r\n\r\n      HAL_LockTypeDef          Lock;             /*!< CRYP locking object */\r\n\r\n   __IO  HAL_CRYP_STATETypeDef State;            /*!< CRYP peripheral state */\r\n   \r\n    __IO uint32_t              ErrorCode;        /*!< CRYP peripheral error code */\r\n     \r\n     HAL_SuspendTypeDef        SuspendRequest;   /*!< CRYP peripheral suspension request flag */     \r\n}CRYP_HandleTypeDef;\r\n\r\n/** \r\n  * @}\r\n  */\r\n\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup CRYP_Exported_Constants CRYP Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CRYP_Key_Size  Key size selection\r\n  * @{\r\n  */\r\n#define CRYP_KEYSIZE_128B         ((uint32_t)0x00000000)  /*!< 128-bit long key */ \r\n#define CRYP_KEYSIZE_256B         AES_CR_KEYSIZE          /*!< 256-bit long key */ \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRYP_Data_Type  AES Data Type selection\r\n  * @{\r\n  */\r\n#define CRYP_DATATYPE_32B         ((uint32_t)0x00000000)  /*!< 32-bit data type (no swapping)        */\r\n#define CRYP_DATATYPE_16B         AES_CR_DATATYPE_0       /*!< 16-bit data type (half-word swapping) */\r\n#define CRYP_DATATYPE_8B          AES_CR_DATATYPE_1       /*!< 8-bit data type (byte swapping)       */\r\n#define CRYP_DATATYPE_1B          AES_CR_DATATYPE         /*!< 1-bit data type (bit swapping)        */\r\n/**\r\n  * @}\r\n  */\r\n  \r\n /** @defgroup CRYP_AES_State  AES Enable state\r\n  * @{\r\n  */ \r\n#define CRYP_AES_DISABLE                 ((uint32_t)0x00000000)   /*!< Disable AES */\r\n#define CRYP_AES_ENABLE                   AES_CR_EN               /*!< Enable AES  */\r\n/**\r\n  * @}\r\n  */            \r\n  \r\n/** @defgroup CRYP_AES_OperatingMode AES operating mode\r\n  * @{\r\n  */ \r\n#define CRYP_ALGOMODE_ENCRYPT                   ((uint32_t)0x00000000)  /*!< Encryption mode                            */\r\n#define CRYP_ALGOMODE_KEYDERIVATION             AES_CR_MODE_0           /*!< Key derivation mode                        */\r\n#define CRYP_ALGOMODE_DECRYPT                   AES_CR_MODE_1           /*!< Decryption                                 */\r\n#define CRYP_ALGOMODE_KEYDERIVATION_DECRYPT     AES_CR_MODE             /*!< Key derivation and decryption              */\r\n#define CRYP_ALGOMODE_TAG_GENERATION            ((uint32_t)0x00000000)  /*!< GMAC or CMAC authentication tag generation */\r\n/**\r\n  * @}\r\n  */                   \r\n\r\n/** @defgroup CRYP_AES_ChainingMode AES chaining mode\r\n  * @{\r\n  */                                                                \r\n#define CRYP_CHAINMODE_AES_ECB            ((uint32_t)0x00000000)            /*!< Electronic codebook chaining algorithm                   */\r\n#define CRYP_CHAINMODE_AES_CBC            AES_CR_CHMOD_0                    /*!< Cipher block chaining algorithm                          */\r\n#define CRYP_CHAINMODE_AES_CTR            AES_CR_CHMOD_1                    /*!< Counter mode chaining algorithm                          */\r\n#define CRYP_CHAINMODE_AES_GCM_GMAC       (AES_CR_CHMOD_0 | AES_CR_CHMOD_1) /*!< Galois counter mode - Galois message authentication code */\r\n#define CRYP_CHAINMODE_AES_CMAC           AES_CR_CHMOD_2                    /*!< Cipher message authentication code                       */\r\n#if defined(AES_CR_NPBLB)\r\n#define CRYP_CHAINMODE_AES_CCM_CMAC       AES_CR_CHMOD_2                    /*!< Counter with Cipher Mode - Cipher message authentication code */  \r\n#endif\r\n/**         \r\n  * @}\r\n  */\r\n  \r\n/** @defgroup CRYP_Key_Write AES decryption key write-up flag\r\n  * @{\r\n  */ \r\n#define CRYP_KEY_WRITE_ENABLE            ((uint32_t)0x00000000)  /*!< Enable decryption key writing  */ \r\n#define CRYP_KEY_WRITE_DISABLE           ((uint32_t)0x00000001)  /*!< Disable decryption key writing */ \r\n/**\r\n  * @}\r\n  */  \r\n  \r\n/** @defgroup CRYP_DMAIN DMA Input phase management enable state\r\n  * @{\r\n  */\r\n#define CRYP_DMAIN_DISABLE             ((uint32_t)0x00000000)    /*!< Disable DMA Input phase management */\r\n#define CRYP_DMAIN_ENABLE              AES_CR_DMAINEN            /*!< Enable DMA Input phase management  */\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup CRYP_DMAOUT DMA Output phase management enable state\r\n  * @{\r\n  */\r\n#define CRYP_DMAOUT_DISABLE             ((uint32_t)0x00000000)   /*!< Disable DMA Output phase management */\r\n#define CRYP_DMAOUT_ENABLE              AES_CR_DMAOUTEN          /*!< Enable DMA Output phase management  */\r\n/**\r\n  * @}\r\n  */  \r\n  \r\n  \r\n/** @defgroup CRYP_GCM_CMAC_Phase GCM/GMAC and CMAC processing phase selection\r\n  * @{\r\n  */\r\n#define CRYP_GCM_INIT_PHASE             ((uint32_t)0x00000000)  /*!< GCM/GMAC (or CCM) init phase        */ \r\n#define CRYP_GCMCMAC_HEADER_PHASE       AES_CR_GCMPH_0          /*!< GCM/GMAC or (CCM/)CMAC header phase */ \r\n#define CRYP_GCM_PAYLOAD_PHASE          AES_CR_GCMPH_1          /*!< GCM(/CCM) payload phase             */ \r\n#define CRYP_GCMCMAC_FINAL_PHASE        AES_CR_GCMPH            /*!< GCM/GMAC or (CCM/)CMAC final phase  */ \r\n/* Definitions duplication for code readibility's sake: \r\n   supported or not supported chain modes are not specified for each phase */\r\n#define CRYP_INIT_PHASE                 ((uint32_t)0x00000000)  /*!< Init phase    */ \r\n#define CRYP_HEADER_PHASE               AES_CR_GCMPH_0          /*!< Header phase  */ \r\n#define CRYP_PAYLOAD_PHASE              AES_CR_GCMPH_1          /*!< Payload phase */ \r\n#define CRYP_FINAL_PHASE                AES_CR_GCMPH            /*!< Final phase   */ \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRYP_Flags   AES status flags\r\n  * @{\r\n  */\r\n\r\n#define CRYP_FLAG_BUSY    AES_SR_BUSY   /*!< GCM process suspension forbidden */\r\n#define CRYP_FLAG_WRERR   AES_SR_WRERR  /*!< Write Error                      */\r\n#define CRYP_FLAG_RDERR   AES_SR_RDERR  /*!< Read error                       */\r\n#define CRYP_FLAG_CCF     AES_SR_CCF    /*!< Computation completed            */\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup CRYP_Clear_Flags   AES clearing flags\r\n  * @{\r\n  */\r\n\r\n#define CRYP_CCF_CLEAR    AES_CR_CCFC   /*!< Computation Complete Flag Clear */\r\n#define CRYP_ERR_CLEAR    AES_CR_ERRC   /*!< Error Flag Clear                */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup AES_Interrupts_Enable AES Interrupts Enable bits\r\n  * @{\r\n  */ \r\n#define CRYP_IT_CCFIE                         AES_CR_CCFIE /*!< Computation Complete interrupt enable */\r\n#define CRYP_IT_ERRIE                         AES_CR_ERRIE /*!< Error interrupt enable                */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRYP_Interrupts_Flags   AES Interrupts flags\r\n  * @{\r\n  */\r\n#define CRYP_IT_WRERR   AES_SR_WRERR  /*!< Write Error           */\r\n#define CRYP_IT_RDERR   AES_SR_RDERR  /*!< Read Error            */\r\n#define CRYP_IT_CCF     AES_SR_CCF    /*!< Computation completed */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macros -----------------------------------------------------------*/\r\n/** @defgroup CRYP_Exported_Macros CRYP Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief Reset CRYP handle state.\r\n  * @param  __HANDLE__ specifies the CRYP handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)\r\n\r\n/**\r\n  * @brief  Enable the CRYP AES peripheral.\r\n  * @retval None\r\n  */\r\n#define __HAL_CRYP_ENABLE()  (AES->CR |=  AES_CR_EN)\r\n\r\n/**\r\n  * @brief  Disable the CRYP AES peripheral.\r\n  * @retval None\r\n  */\r\n#define __HAL_CRYP_DISABLE() (AES->CR &=  ~AES_CR_EN)\r\n\r\n/**\r\n  * @brief  Set the algorithm operating mode.\r\n  * @param  __OPERATING_MODE__ specifies the operating mode\r\n  *          This parameter can be one of the following values:\r\n  *            @arg @ref CRYP_ALGOMODE_ENCRYPT encryption     \r\n  *            @arg @ref CRYP_ALGOMODE_KEYDERIVATION key derivation        \r\n  *            @arg @ref CRYP_ALGOMODE_DECRYPT decryption \r\n  *            @arg @ref CRYP_ALGOMODE_KEYDERIVATION_DECRYPT key derivation and decryption  \r\n  * @retval None\r\n  */\r\n#define __HAL_CRYP_SET_OPERATINGMODE(__OPERATING_MODE__) MODIFY_REG(AES->CR, AES_CR_MODE, (__OPERATING_MODE__))  \r\n\r\n\r\n/**\r\n  * @brief  Set the algorithm chaining mode.\r\n  * @param  __CHAINING_MODE__ specifies the chaining mode\r\n  *          This parameter can be one of the following values:\r\n  *            @arg @ref CRYP_CHAINMODE_AES_ECB Electronic CodeBook     \r\n  *            @arg @ref CRYP_CHAINMODE_AES_CBC Cipher Block Chaining        \r\n  *            @arg @ref CRYP_CHAINMODE_AES_CTR CounTeR mode\r\n  *            @arg @ref CRYP_CHAINMODE_AES_GCM_GMAC Galois Counter Mode or Galois Message Authentication Code     \r\n  *            @arg @ref CRYP_CHAINMODE_AES_CMAC Cipher Message Authentication Code (or Counter with Cipher Mode when applicable)\r\n  * @retval None\r\n  */\r\n#define __HAL_CRYP_SET_CHAININGMODE(__CHAINING_MODE__) MODIFY_REG(AES->CR, AES_CR_CHMOD, (__CHAINING_MODE__))  \r\n\r\n\r\n\r\n/** @brief  Check whether the specified CRYP status flag is set or not.\r\n  * @param  __FLAG__ specifies the flag to check.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden  \r\n  *            @arg @ref CRYP_IT_WRERR Write Error \r\n  *            @arg @ref CRYP_IT_RDERR Read Error \r\n  *            @arg @ref CRYP_IT_CCF Computation Complete                 \r\n  * @retval The state of __FLAG__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_CRYP_GET_FLAG(__FLAG__) ((AES->SR & (__FLAG__)) == (__FLAG__))\r\n\r\n\r\n/** @brief  Clear the CRYP pending status flag.\r\n  * @param  __FLAG__ specifies the flag to clear.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear\r\n  *            @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear  \r\n  * @retval None\r\n  */\r\n#define __HAL_CRYP_CLEAR_FLAG(__FLAG__) SET_BIT(AES->CR, (__FLAG__))\r\n\r\n\r\n\r\n/** @brief  Check whether the specified CRYP interrupt source is enabled or not.\r\n  * @param __INTERRUPT__ CRYP interrupt source to check\r\n  *         This parameter can be one of the following values:\r\n  *            @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)\r\n  *            @arg @ref CRYP_IT_CCFIE Computation Complete interrupt  \r\n  * @retval State of interruption (TRUE or FALSE).\r\n  */\r\n#define __HAL_CRYP_GET_IT_SOURCE(__INTERRUPT__) ((AES->CR & (__INTERRUPT__)) == (__INTERRUPT__))\r\n\r\n\r\n/** @brief  Check whether the specified CRYP interrupt is set or not.\r\n  * @param  __INTERRUPT__ specifies the interrupt to check.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg @ref CRYP_IT_WRERR Write Error \r\n  *            @arg @ref CRYP_IT_RDERR Read Error \r\n  *            @arg @ref CRYP_IT_CCF  Computation Complete                 \r\n  * @retval The state of __INTERRUPT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_CRYP_GET_IT(__INTERRUPT__) ((AES->SR & (__INTERRUPT__)) == (__INTERRUPT__))\r\n\r\n\r\n\r\n/** @brief  Clear the CRYP pending interrupt.\r\n  * @param  __INTERRUPT__ specifies the IT to clear.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear\r\n  *            @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear    \r\n  * @retval None\r\n  */\r\n#define __HAL_CRYP_CLEAR_IT(__INTERRUPT__) SET_BIT(AES->CR, (__INTERRUPT__))\r\n\r\n\r\n/**\r\n  * @brief  Enable the CRYP interrupt.  \r\n  * @param  __INTERRUPT__ CRYP Interrupt.\r\n  *         This parameter can be one of the following values:  \r\n  *            @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)\r\n  *            @arg @ref CRYP_IT_CCFIE Computation Complete interrupt    \r\n  * @retval None\r\n  */\r\n#define __HAL_CRYP_ENABLE_IT(__INTERRUPT__) ((AES->CR) |= (__INTERRUPT__))\r\n\r\n\r\n/**\r\n  * @brief  Disable the CRYP interrupt.\r\n  * @param  __INTERRUPT__ CRYP Interrupt.\r\n  *         This parameter can be one of the following values:  \r\n  *            @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)\r\n  *            @arg @ref CRYP_IT_CCFIE Computation Complete interrupt    \r\n  * @retval None\r\n  */\r\n#define __HAL_CRYP_DISABLE_IT(__INTERRUPT__) ((AES->CR) &= ~(__INTERRUPT__))\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros --------------------------------------------------------*/\r\n/** @addtogroup  CRYP_Private_Macros   CRYP Private Macros\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief Verify the key size length.\r\n  * @param __KEYSIZE__ Ciphering/deciphering algorithm key size. \r\n  * @retval SET (__KEYSIZE__ is a valid value) or RESET (__KEYSIZE__ is invalid)\r\n  */  \r\n#define IS_CRYP_KEYSIZE(__KEYSIZE__)  (((__KEYSIZE__) == CRYP_KEYSIZE_128B)  || \\\r\n                                       ((__KEYSIZE__) == CRYP_KEYSIZE_256B))\r\n\r\n/**\r\n  * @brief Verify the input data type.\r\n  * @param __DATATYPE__ Ciphering/deciphering algorithm input data type.\r\n  * @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)\r\n  */  \r\n#define IS_CRYP_DATATYPE(__DATATYPE__) (((__DATATYPE__) == CRYP_DATATYPE_32B) || \\\r\n                                        ((__DATATYPE__) == CRYP_DATATYPE_16B) || \\\r\n                                        ((__DATATYPE__) == CRYP_DATATYPE_8B)  || \\\r\n                                        ((__DATATYPE__) == CRYP_DATATYPE_1B))\r\n\r\n/**\r\n  * @brief Verify the CRYP AES IP running mode.\r\n  * @param __MODE__ CRYP AES IP running mode.\r\n  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)\r\n  */                                     \r\n#define IS_CRYP_AES(__MODE__) (((__MODE__) == CRYP_AES_DISABLE) || \\\r\n                               ((__MODE__) == CRYP_AES_ENABLE)) \r\n\r\n/**\r\n  * @brief Verify the selected CRYP algorithm.\r\n  * @param __ALGOMODE__ Selected CRYP algorithm (ciphering, deciphering, key derivation or a combination of the latter).\r\n  * @retval SET (__ALGOMODE__ is valid) or RESET (__ALGOMODE__ is invalid)\r\n  */                            \r\n#define IS_CRYP_ALGOMODE(__ALGOMODE__) (((__ALGOMODE__) == CRYP_ALGOMODE_ENCRYPT)        || \\\r\n                                        ((__ALGOMODE__) == CRYP_ALGOMODE_KEYDERIVATION)  || \\\r\n                                        ((__ALGOMODE__) == CRYP_ALGOMODE_DECRYPT)        || \\\r\n                                        ((__ALGOMODE__) == CRYP_ALGOMODE_TAG_GENERATION) || \\\r\n                                        ((__ALGOMODE__) == CRYP_ALGOMODE_KEYDERIVATION_DECRYPT))  \r\n\r\n/**\r\n  * @brief Verify the selected CRYP chaining algorithm.\r\n  * @param __CHAINMODE__ Selected CRYP chaining algorithm.\r\n  * @retval SET (__CHAINMODE__ is valid) or RESET (__CHAINMODE__ is invalid)\r\n  */   \r\n#if defined(AES_CR_NPBLB)\r\n#define IS_CRYP_CHAINMODE(__CHAINMODE__) (((__CHAINMODE__) == CRYP_CHAINMODE_AES_ECB)     || \\\r\n                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CBC)      || \\\r\n                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CTR)      || \\\r\n                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_GCM_GMAC) || \\\r\n                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CCM_CMAC))   \r\n#else\r\n#define IS_CRYP_CHAINMODE(__CHAINMODE__) (((__CHAINMODE__) == CRYP_CHAINMODE_AES_ECB)     || \\\r\n                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CBC)      || \\\r\n                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CTR)      || \\\r\n                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_GCM_GMAC) || \\\r\n                                         ((__CHAINMODE__) == CRYP_CHAINMODE_AES_CMAC))    \r\n#endif                                \r\n\r\n/**\r\n  * @brief Verify the deciphering key write option.\r\n  * @param __WRITE__ deciphering key write option.\r\n  * @retval SET (__WRITE__ is valid) or RESET (__WRITE__ is invalid)\r\n  */                                   \r\n#define IS_CRYP_WRITE(__WRITE__)   (((__WRITE__) == CRYP_KEY_WRITE_ENABLE)      || \\\r\n                                    ((__WRITE__) == CRYP_KEY_WRITE_DISABLE))\r\n\r\n/**\r\n  * @brief Verify the CRYP input data DMA mode.\r\n  * @param __MODE__ CRYP input data DMA mode.\r\n  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)\r\n  */  \r\n#define IS_CRYP_DMAIN(__MODE__) (((__MODE__) == CRYP_DMAIN_DISABLE) || \\\r\n                                 ((__MODE__) == CRYP_DMAIN_ENABLE)) \r\n\r\n/**\r\n  * @brief Verify the CRYP output data DMA mode.\r\n  * @param __MODE__ CRYP output data DMA mode.\r\n  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)\r\n  */                             \r\n#define IS_CRYP_DMAOUT(__MODE__) (((__MODE__) == CRYP_DMAOUT_DISABLE) || \\\r\n                                  ((__MODE__) == CRYP_DMAOUT_ENABLE)) \r\n\r\n/**\r\n  * @brief Verify the CRYP AES ciphering/deciphering/authentication algorithm phase.\r\n  * @param __PHASE__ CRYP AES ciphering/deciphering/authentication algorithm phase.\r\n  * @retval SET (__PHASE__ is valid) or RESET (__PHASE__ is invalid)\r\n  */                               \r\n#define IS_CRYP_GCMCMAC_PHASE(__PHASE__) (((__PHASE__) == CRYP_GCM_INIT_PHASE)       || \\\r\n                                          ((__PHASE__) == CRYP_GCMCMAC_HEADER_PHASE) || \\\r\n                                          ((__PHASE__) == CRYP_GCM_PAYLOAD_PHASE)    || \\\r\n                                          ((__PHASE__) == CRYP_GCMCMAC_FINAL_PHASE))\r\n                                      \r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Include CRYP HAL Extended module */\r\n#include \"stm32f7xx_hal_cryp_ex.h\"\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup CRYP_Exported_Functions CRYP Exported Functions\r\n  * @{\r\n  */\r\n  \r\n/** @addtogroup CRYP_Exported_Functions_Group1 Initialization and deinitialization functions\r\n  * @{\r\n  */\r\n    \r\n/* Initialization/de-initialization functions  ********************************/\r\nHAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);\r\nHAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);\r\n\r\n/* MSP initialization/de-initialization functions  ****************************/\r\nvoid HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);\r\nvoid HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @addtogroup CRYP_Exported_Functions_Group2 AES processing functions \r\n  * @{\r\n  */  \r\n\r\n/* AES encryption/decryption processing functions  ****************************/\r\n\r\n/* AES encryption/decryption using polling  ***********************************/\r\nHAL_StatusTypeDef     HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);\r\nHAL_StatusTypeDef     HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);\r\nHAL_StatusTypeDef     HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);\r\nHAL_StatusTypeDef     HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);\r\nHAL_StatusTypeDef     HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);\r\nHAL_StatusTypeDef     HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);\r\n\r\n/* AES encryption/decryption using interrupt  *********************************/\r\nHAL_StatusTypeDef     HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef     HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef     HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef     HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\nHAL_StatusTypeDef     HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\nHAL_StatusTypeDef     HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\n\r\n/* AES encryption/decryption using DMA  ***************************************/\r\nHAL_StatusTypeDef     HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef     HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\nHAL_StatusTypeDef     HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef     HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\nHAL_StatusTypeDef     HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef     HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @addtogroup CRYP_Exported_Functions_Group3 Callback functions\r\n  * @{\r\n  */ \r\n/* CallBack functions  ********************************************************/\r\nvoid HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);\r\nvoid HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);\r\nvoid HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);  \r\n  \r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @addtogroup CRYP_Exported_Functions_Group4 CRYP IRQ handler \r\n  * @{\r\n  */    \r\n\r\n/* AES interrupt handling function  *******************************************/\r\nvoid HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @addtogroup CRYP_Exported_Functions_Group5 Peripheral State functions \r\n  * @{\r\n  */\r\n\r\n/* Peripheral State functions  ************************************************/\r\nHAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);\r\nuint32_t              HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n#endif /* AES */  \r\n\r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_CRYP_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cryp_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_cryp_ex.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of CRYP HAL Extension module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_CRYP_EX_H\r\n#define __STM32F7xx_HAL_CRYP_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n#if defined (CRYP)\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup CRYPEx\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/ \r\n/* Exported constants --------------------------------------------------------*/\r\n   \r\n/** @defgroup CRYPEx_Exported_Constants   CRYPEx Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CRYPEx_Exported_Constants_Group1 CRYP AlgoModeDirection\r\n  * @{\r\n  */ \r\n#define CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT   ((uint32_t)0x00080000U)\r\n#define CRYP_CR_ALGOMODE_AES_GCM_DECRYPT   ((uint32_t)0x00080004U)\r\n#define CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT   ((uint32_t)0x00080008U)\r\n#define CRYP_CR_ALGOMODE_AES_CCM_DECRYPT   ((uint32_t)0x0008000CU)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRYPEx_Exported_Constants_Group3 CRYP PhaseConfig\r\n  * @brief    The phases are relevant only to AES-GCM and AES-CCM\r\n  * @{\r\n  */ \r\n#define CRYP_PHASE_INIT           ((uint32_t)0x00000000U)\r\n#define CRYP_PHASE_HEADER         CRYP_CR_GCM_CCMPH_0\r\n#define CRYP_PHASE_PAYLOAD        CRYP_CR_GCM_CCMPH_1\r\n#define CRYP_PHASE_FINAL          CRYP_CR_GCM_CCMPH\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup CRYPEx_Exported_Macros CRYP Exported Macros\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @brief  Set the phase: Init, header, payload, final. \r\n  *         This is relevant only for GCM and CCM modes.\r\n  * @param  __HANDLE__ specifies the CRYP handle.\r\n  * @param  __PHASE__ The phase.\r\n  * @retval None\r\n  */\r\n#define __HAL_CRYP_SET_PHASE(__HANDLE__, __PHASE__)  do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\\\r\n                                                        (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\\\r\n                                                       }while(0)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup CRYPEx_Exported_Functions_Group1\r\n  * @{\r\n  */  \r\n    \r\n/* AES encryption/decryption using polling  ***********************************/\r\nHAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint32_t Size, uint8_t *AuthTag, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *AuthTag, uint32_t Timeout);\r\n\r\n/* AES encryption/decryption using interrupt  *********************************/\r\nHAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\nHAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\n\r\n/* AES encryption/decryption using DMA  ***************************************/\r\nHAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\nHAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/** @addtogroup CRYPEx_Exported_Functions_Group2\r\n  * @{\r\n  */  \r\n    \r\nvoid HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n \r\n /**\r\n  * @}\r\n  */ \r\n \r\n\r\n /* Private types -------------------------------------------------------------*/\r\n/** @defgroup CRYPEx_Private_Types CRYPEx Private Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros\r\n  * @{\r\n  */\r\n\r\n /**\r\n  * @}\r\n  */ \r\n  \r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n   \r\n/**\r\n  * @}\r\n  */ \r\n\r\n#endif /* CRYP */\r\n\r\n#if defined (AES)\r\n\r\n/** @addtogroup CRYPEx_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup CRYPEx_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n\r\n/* CallBack functions  ********************************************************/\r\nvoid HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @addtogroup CRYPEx_Exported_Functions_Group2\r\n  * @{\r\n  */\r\n\r\n/* AES encryption/decryption processing functions  ****************************/\r\nHAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CRYPEx_AES_IT(CRYP_HandleTypeDef *hcryp,  uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData);\r\nHAL_StatusTypeDef HAL_CRYPEx_AES_DMA(CRYP_HandleTypeDef *hcryp,  uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData);\r\n\r\n/* AES encryption/decryption/authentication processing functions  *************/\r\nHAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData);\r\nHAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @addtogroup CRYPEx_Exported_Functions_Group3\r\n  * @{\r\n  */\r\n\r\n/* AES suspension/resumption functions  ***************************************/\r\nvoid HAL_CRYPEx_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output);\r\nvoid HAL_CRYPEx_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input);\r\nvoid HAL_CRYPEx_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output);\r\nvoid HAL_CRYPEx_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input);\r\nvoid HAL_CRYPEx_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t KeySize);\r\nvoid HAL_CRYPEx_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint32_t KeySize);\r\nvoid HAL_CRYPEx_Read_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Output);\r\nvoid HAL_CRYPEx_Write_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Input);\r\nvoid HAL_CRYPEx_ProcessSuspend(CRYP_HandleTypeDef *hcryp);\r\n\r\n/**\r\n  * @}\r\n  */  \r\n  \r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/* Private functions -----------------------------------------------------------*/\r\n/** @addtogroup CRYPEx_Private_Functions CRYPEx Private Functions\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp);\r\n\r\n/**\r\n  * @}\r\n  */\r\n \r\n#endif /* AES */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_CRYP_EX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_dac.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of DAC HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_DAC_H\r\n#define __STM32F7xx_HAL_DAC_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup DAC\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup DAC_Exported_Types DAC Exported Types\r\n  * @{\r\n  */\r\n\r\n/** \r\n  * @brief HAL State structures definition\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_DAC_STATE_RESET             = 0x00U,  /*!< DAC not yet initialized or disabled  */\r\n  HAL_DAC_STATE_READY             = 0x01U,  /*!< DAC initialized and ready for use    */\r\n  HAL_DAC_STATE_BUSY              = 0x02U,  /*!< DAC internal processing is ongoing   */\r\n  HAL_DAC_STATE_TIMEOUT           = 0x03U,  /*!< DAC timeout state                    */\r\n  HAL_DAC_STATE_ERROR             = 0x04U   /*!< DAC error state                      */\r\n}HAL_DAC_StateTypeDef;\r\n \r\n/** \r\n  * @brief DAC handle Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  DAC_TypeDef                 *Instance;     /*!< Register base address             */\r\n\r\n  __IO HAL_DAC_StateTypeDef   State;         /*!< DAC communication state           */\r\n\r\n  HAL_LockTypeDef             Lock;          /*!< DAC locking object                */\r\n\r\n  DMA_HandleTypeDef           *DMA_Handle1;  /*!< Pointer DMA handler for channel 1 */\r\n\r\n  DMA_HandleTypeDef           *DMA_Handle2;  /*!< Pointer DMA handler for channel 2 */\r\n\r\n  __IO uint32_t               ErrorCode;     /*!< DAC Error code                    */\r\n\r\n}DAC_HandleTypeDef;\r\n\r\n/** \r\n  * @brief DAC Configuration regular Channel structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t DAC_Trigger;       /*!< Specifies the external trigger for the selected DAC channel.\r\n                                   This parameter can be a value of @ref DAC_trigger_selection */\r\n\r\n  uint32_t DAC_OutputBuffer;  /*!< Specifies whether the DAC channel output buffer is enabled or disabled.\r\n                                   This parameter can be a value of @ref DAC_output_buffer */\r\n}DAC_ChannelConfTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup DAC_Exported_Constants DAC Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup DAC_Error_Code DAC Error Code\r\n  * @{\r\n  */\r\n#define  HAL_DAC_ERROR_NONE              0x00U    /*!< No error                          */\r\n#define  HAL_DAC_ERROR_DMAUNDERRUNCH1    0x01U    /*!< DAC channel1 DAM underrun error   */\r\n#define  HAL_DAC_ERROR_DMAUNDERRUNCH2    0x02U    /*!< DAC channel2 DAM underrun error   */\r\n#define  HAL_DAC_ERROR_DMA               0x04U    /*!< DMA error                         */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DAC_trigger_selection DAC Trigger Selection\r\n  * @{\r\n  */\r\n\r\n#define DAC_TRIGGER_NONE                   ((uint32_t)0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register \r\n                                                                       has been loaded, and not by external trigger */\r\n#define DAC_TRIGGER_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */\r\n#define DAC_TRIGGER_T4_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */\r\n#define DAC_TRIGGER_T5_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */\r\n#define DAC_TRIGGER_T6_TRGO                ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */\r\n#define DAC_TRIGGER_T7_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */\r\n#define DAC_TRIGGER_T8_TRGO                ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */                                                                       \r\n\r\n#define DAC_TRIGGER_EXT_IT9                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */\r\n#define DAC_TRIGGER_SOFTWARE               ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DAC_output_buffer  DAC Output Buffer\r\n  * @{\r\n  */\r\n#define DAC_OUTPUTBUFFER_ENABLE            ((uint32_t)0x00000000U)\r\n#define DAC_OUTPUTBUFFER_DISABLE           ((uint32_t)DAC_CR_BOFF1)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DAC_Channel_selection DAC Channel Selection\r\n  * @{\r\n  */\r\n#define DAC_CHANNEL_1                      ((uint32_t)0x00000000U)\r\n#define DAC_CHANNEL_2                      ((uint32_t)0x00000010U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DAC_data_alignment DAC Data Alignment\r\n  * @{\r\n  */\r\n#define DAC_ALIGN_12B_R                    ((uint32_t)0x00000000U)\r\n#define DAC_ALIGN_12B_L                    ((uint32_t)0x00000004U)\r\n#define DAC_ALIGN_8B_R                     ((uint32_t)0x00000008U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DAC_flags_definition DAC Flags Definition\r\n  * @{\r\n  */ \r\n#define DAC_FLAG_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)\r\n#define DAC_FLAG_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DAC_IT_definition DAC IT Definition\r\n  * @{\r\n  */ \r\n#define DAC_IT_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)\r\n#define DAC_IT_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup DAC_Exported_Macros DAC Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief Reset DAC handle state\r\n  * @param  __HANDLE__ specifies the DAC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)\r\n\r\n/** @brief Enable the DAC channel\r\n  * @param  __HANDLE__ specifies the DAC handle.\r\n  * @param  __DAC_CHANNEL__ specifies the DAC channel\r\n  * @retval None\r\n  */\r\n#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_CHANNEL__) \\\r\n((__HANDLE__)->Instance->CR |=  (DAC_CR_EN1 << (__DAC_CHANNEL__)))\r\n\r\n/** @brief Disable the DAC channel\r\n  * @param  __HANDLE__ specifies the DAC handle\r\n  * @param  __DAC_CHANNEL__ specifies the DAC channel.\r\n  * @retval None\r\n  */\r\n#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_CHANNEL__) \\\r\n((__HANDLE__)->Instance->CR &=  ~(DAC_CR_EN1 << (__DAC_CHANNEL__)))\r\n\r\n\r\n/** @brief Enable the DAC interrupt\r\n  * @param  __HANDLE__ specifies the DAC handle\r\n  * @param  __INTERRUPT__ specifies the DAC interrupt.\r\n  * @retval None\r\n  */\r\n#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))\r\n\r\n/** @brief Disable the DAC interrupt\r\n  * @param  __HANDLE__ specifies the DAC handle\r\n  * @param  __INTERRUPT__ specifies the DAC interrupt.\r\n  * @retval None\r\n  */\r\n#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))\r\n\r\n/** @brief  Checks if the specified DAC interrupt source is enabled or disabled.\r\n  * @param __HANDLE__ DAC handle\r\n  * @param __INTERRUPT__ DAC interrupt source to check\r\n  *          This parameter can be any combination of the following values:\r\n  *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt\r\n  *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt\r\n  * @retval State of interruption (SET or RESET)\r\n  */\r\n#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))\r\n\r\n/** @brief  Get the selected DAC's flag status.\r\n  * @param  __HANDLE__ specifies the DAC handle.\r\n  * @param  __FLAG__ specifies the flag to clear.\r\n  *         This parameter can be any combination of the following values:\r\n  *            @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag\r\n  *            @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag\r\n  * @retval None\r\n  */\r\n#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))\r\n\r\n/** @brief  Clear the DAC's flag.\r\n  * @param  __HANDLE__ specifies the DAC handle.\r\n  * @param  __FLAG__ specifies the flag to clear.\r\n  *         This parameter can be any combination of the following values:\r\n  *            @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag\r\n  *            @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag\r\n  * @retval None\r\n  */\r\n#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Include DAC HAL Extension module */\r\n#include \"stm32f7xx_hal_dac_ex.h\"\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup DAC_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup DAC_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n/* Initialization/de-initialization functions *********************************/\r\nHAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);\r\nHAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);\r\nvoid HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);\r\nvoid HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup DAC_Exported_Functions_Group2\r\n  * @{\r\n  */\r\n/* I/O operation functions ****************************************************/\r\nHAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);\r\nHAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);\r\nuint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup DAC_Exported_Functions_Group3\r\n  * @{\r\n  */\r\n/* Peripheral Control functions ***********************************************/\r\nHAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup DAC_Exported_Functions_Group4\r\n  * @{\r\n  */\r\n/* Peripheral State functions *************************************************/\r\nHAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);\r\nvoid HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);\r\nuint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);\r\n\r\nvoid HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);\r\nvoid HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);\r\nvoid HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);\r\nvoid HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup DAC_Private_Constants DAC Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup DAC_Private_Macros DAC Private Macros\r\n  * @{\r\n  */\r\n#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)\r\n#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \\\r\n                             ((ALIGN) == DAC_ALIGN_12B_L) || \\\r\n                             ((ALIGN) == DAC_ALIGN_8B_R))\r\n#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \\\r\n                                 ((CHANNEL) == DAC_CHANNEL_2))\r\n#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \\\r\n                                           ((STATE) == DAC_OUTPUTBUFFER_DISABLE))\r\n\r\n#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \\\r\n                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \\\r\n                                 ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \\\r\n                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \\\r\n                                 ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \\\r\n                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \\\r\n                                 ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \\\r\n                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \\\r\n                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))\r\n\r\n/** @brief Set DHR12R1 alignment\r\n  * @param  __ALIGNMENT__ specifies the DAC alignment\r\n  * @retval None\r\n  */\r\n#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008U) + (__ALIGNMENT__))\r\n\r\n/** @brief  Set DHR12R2 alignment\r\n  * @param  __ALIGNMENT__ specifies the DAC alignment\r\n  * @retval None\r\n  */\r\n#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014U) + (__ALIGNMENT__))\r\n\r\n/** @brief  Set DHR12RD alignment\r\n  * @param  __ALIGNMENT__ specifies the DAC alignment\r\n  * @retval None\r\n  */\r\n#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020U) + (__ALIGNMENT__))\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup DAC_Private_Functions DAC Private Functions\r\n  * @{\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /*__STM32F7xx_HAL_DAC_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_dac.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of DAC HAL Extension module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_DAC_EX_H\r\n#define __STM32F7xx_HAL_DAC_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup DACEx\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup DACEx_Exported_Constants DAC Exported Constants\r\n  * @{\r\n  */\r\n   \r\n/** @defgroup DACEx_lfsrunmask_triangleamplitude DAC LFS Run Mask Triangle Amplitude\r\n  * @{\r\n  */\r\n#define DAC_LFSRUNMASK_BIT0                ((uint32_t)0x00000000U) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */\r\n#define DAC_LFSRUNMASK_BITS1_0             ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */\r\n#define DAC_LFSRUNMASK_BITS2_0             ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */\r\n#define DAC_LFSRUNMASK_BITS3_0             ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */\r\n#define DAC_LFSRUNMASK_BITS4_0             ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */\r\n#define DAC_LFSRUNMASK_BITS5_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */\r\n#define DAC_LFSRUNMASK_BITS6_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */\r\n#define DAC_LFSRUNMASK_BITS7_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */\r\n#define DAC_LFSRUNMASK_BITS8_0             ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */\r\n#define DAC_LFSRUNMASK_BITS9_0             ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */\r\n#define DAC_LFSRUNMASK_BITS10_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */\r\n#define DAC_LFSRUNMASK_BITS11_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */\r\n#define DAC_TRIANGLEAMPLITUDE_1            ((uint32_t)0x00000000U) /*!< Select max triangle amplitude of 1 */\r\n#define DAC_TRIANGLEAMPLITUDE_3            ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */\r\n#define DAC_TRIANGLEAMPLITUDE_7            ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */\r\n#define DAC_TRIANGLEAMPLITUDE_15           ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */\r\n#define DAC_TRIANGLEAMPLITUDE_31           ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */\r\n#define DAC_TRIANGLEAMPLITUDE_63           ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */\r\n#define DAC_TRIANGLEAMPLITUDE_127          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */\r\n#define DAC_TRIANGLEAMPLITUDE_255          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */\r\n#define DAC_TRIANGLEAMPLITUDE_511          ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */\r\n#define DAC_TRIANGLEAMPLITUDE_1023         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */\r\n#define DAC_TRIANGLEAMPLITUDE_2047         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */\r\n#define DAC_TRIANGLEAMPLITUDE_4095         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup DACEx_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup DACEx_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n/* Extension features functions ***********************************************/\r\nuint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);\r\nHAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);\r\nHAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);\r\nHAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);\r\n\r\nvoid HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);\r\nvoid HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);\r\nvoid HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);\r\nvoid HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup DACEx_Private_Constants DAC Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup DACEx_Private_Macros DAC Private Macros\r\n  * @{\r\n  */\r\n#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \\\r\n                                                      ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \\\r\n                                                      ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \\\r\n                                                      ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \\\r\n                                                      ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \\\r\n                                                      ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \\\r\n                                                      ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \\\r\n                                                      ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \\\r\n                                                      ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \\\r\n                                                      ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \\\r\n                                                      ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \\\r\n                                                      ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \\\r\n                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \\\r\n                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \\\r\n                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \\\r\n                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \\\r\n                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \\\r\n                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \\\r\n                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \\\r\n                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \\\r\n                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \\\r\n                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \\\r\n                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \\\r\n                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup DACEx_Private_Functions DAC Private Functions\r\n  * @{\r\n  */\r\nvoid DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);\r\nvoid DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);\r\nvoid DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); \r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /*__STM32F7xx_HAL_DAC_EX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dcmi.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_dcmi.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of DCMI HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_DCMI_H\r\n#define __STM32F7xx_HAL_DCMI_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n#if defined (DCMI)\r\n \r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup DCMI DCMI\r\n  * @brief DCMI HAL module driver\r\n  * @{\r\n  */  \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup DCMI_Exported_Types DCMI Exported Types\r\n  * @{\r\n  */\r\n/** \r\n  * @brief  HAL DCMI State structures definition\r\n  */ \r\ntypedef enum\r\n{\r\n  HAL_DCMI_STATE_RESET             = 0x00U,  /*!< DCMI not yet initialized or disabled  */\r\n  HAL_DCMI_STATE_READY             = 0x01U,  /*!< DCMI initialized and ready for use    */\r\n  HAL_DCMI_STATE_BUSY              = 0x02U,  /*!< DCMI internal processing is ongoing   */\r\n  HAL_DCMI_STATE_TIMEOUT           = 0x03U,  /*!< DCMI timeout state                    */\r\n  HAL_DCMI_STATE_ERROR             = 0x04U,  /*!< DCMI error state                      */\r\n  HAL_DCMI_STATE_SUSPENDED         = 0x05U   /*!< DCMI suspend state                    */    \r\n}HAL_DCMI_StateTypeDef;\r\n\r\n/** \r\n  * @brief   DCMIEx Embedded Synchronisation CODE Init structure definition\r\n  */ \r\ntypedef struct\r\n{\r\n  uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */\r\n  uint8_t LineStartCode;  /*!< Specifies the code of the line start delimiter.  */\r\n  uint8_t LineEndCode;    /*!< Specifies the code of the line end delimiter.    */\r\n  uint8_t FrameEndCode;   /*!< Specifies the code of the frame end delimiter.   */\r\n}DCMI_CodesInitTypeDef;\r\n\r\n/** \r\n  * @brief   DCMI Init structure definition\r\n  */  \r\ntypedef struct\r\n{\r\n  uint32_t  SynchroMode;                /*!< Specifies the Synchronization Mode: Hardware or Embedded.\r\n                                             This parameter can be a value of @ref DCMI_Synchronization_Mode */\r\n\r\n  uint32_t  PCKPolarity;                /*!< Specifies the Pixel clock polarity: Falling or Rising.\r\n                                             This parameter can be a value of @ref DCMI_PIXCK_Polarity       */\r\n\r\n  uint32_t  VSPolarity;                 /*!< Specifies the Vertical synchronization polarity: High or Low.\r\n                                             This parameter can be a value of @ref DCMI_VSYNC_Polarity       */\r\n\r\n  uint32_t  HSPolarity;                 /*!< Specifies the Horizontal synchronization polarity: High or Low.\r\n                                             This parameter can be a value of @ref DCMI_HSYNC_Polarity       */\r\n\r\n  uint32_t  CaptureRate;                /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.\r\n                                             This parameter can be a value of @ref DCMI_Capture_Rate         */\r\n\r\n  uint32_t  ExtendedDataMode;           /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.\r\n                                             This parameter can be a value of @ref DCMI_Extended_Data_Mode   */\r\n\r\n  DCMI_CodesInitTypeDef SyncroCode;     /*!< Specifies the code of the line/frame start delimiter and the\r\n                                             line/frame end delimiter */\r\n\r\n  uint32_t JPEGMode;                    /*!< Enable or Disable the JPEG mode.                                \r\n                                             This parameter can be a value of @ref DCMI_MODE_JPEG            */\r\n\r\n  uint32_t ByteSelectMode;              /*!< Specifies the data to be captured by the interface \r\n                                            This parameter can be a value of @ref DCMI_Byte_Select_Mode      */\r\n                                            \r\n  uint32_t ByteSelectStart;             /*!< Specifies if the data to be captured by the interface is even or odd\r\n                                            This parameter can be a value of @ref DCMI_Byte_Select_Start     */\r\n\r\n  uint32_t LineSelectMode;              /*!< Specifies the line of data to be captured by the interface \r\n                                            This parameter can be a value of @ref DCMI_Line_Select_Mode      */\r\n                                            \r\n  uint32_t LineSelectStart;             /*!< Specifies if the line of data to be captured by the interface is even or odd\r\n                                            This parameter can be a value of @ref DCMI_Line_Select_Start     */\r\n}DCMI_InitTypeDef;\r\n\r\n/** \r\n  * @brief  DCMI handle Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  DCMI_TypeDef                  *Instance;           /*!< DCMI Register base address   */\r\n\r\n  DCMI_InitTypeDef              Init;                /*!< DCMI parameters              */\r\n\r\n  HAL_LockTypeDef               Lock;                /*!< DCMI locking object          */\r\n\r\n  __IO HAL_DCMI_StateTypeDef    State;               /*!< DCMI state                   */\r\n\r\n  __IO uint32_t                 XferCount;           /*!< DMA transfer counter         */\r\n\r\n  __IO uint32_t                 XferSize;            /*!< DMA transfer size            */\r\n\r\n  uint32_t                      XferTransferNumber;  /*!< DMA transfer number          */\r\n\r\n  uint32_t                      pBuffPtr;            /*!< Pointer to DMA output buffer */\r\n\r\n  DMA_HandleTypeDef             *DMA_Handle;         /*!< Pointer to the DMA handler   */\r\n\r\n  __IO uint32_t                 ErrorCode;           /*!< DCMI Error code              */\r\n\r\n}DCMI_HandleTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup DCMI_Exported_Constants DCMI Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup DCMI_Error_Code DCMI Error Code\r\n  * @{\r\n  */\r\n#define HAL_DCMI_ERROR_NONE      ((uint32_t)0x00000000U)    /*!< No error              */\r\n#define HAL_DCMI_ERROR_OVR       ((uint32_t)0x00000001U)    /*!< Overrun error         */\r\n#define HAL_DCMI_ERROR_SYNC      ((uint32_t)0x00000002U)    /*!< Synchronization error */\r\n#define HAL_DCMI_ERROR_TIMEOUT   ((uint32_t)0x00000020U)    /*!< Timeout error         */\r\n#define HAL_DCMI_ERROR_DMA       ((uint32_t)0x00000040U)    /*!< DMA error             */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DCMI_Capture_Mode DCMI Capture Mode\r\n  * @{\r\n  */ \r\n#define DCMI_MODE_CONTINUOUS           ((uint32_t)0x00000000U)  /*!< The received data are transferred continuously \r\n                                                                    into the destination memory through the DMA             */\r\n#define DCMI_MODE_SNAPSHOT             ((uint32_t)DCMI_CR_CM)  /*!< Once activated, the interface waits for the start of \r\n                                                                    frame and then transfers a single frame through the DMA */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode\r\n  * @{\r\n  */ \r\n#define DCMI_SYNCHRO_HARDWARE        ((uint32_t)0x00000000U)   /*!< Hardware synchronization data capture (frame/line start/stop)\r\n                                                                   is synchronized with the HSYNC/VSYNC signals                  */\r\n#define DCMI_SYNCHRO_EMBEDDED        ((uint32_t)DCMI_CR_ESS)  /*!< Embedded synchronization data capture is synchronized with \r\n                                                                   synchronization codes embedded in the data flow               */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DCMI_PIXCK_Polarity DCMI PIXCK Polarity\r\n  * @{\r\n  */\r\n#define DCMI_PCKPOLARITY_FALLING    ((uint32_t)0x00000000U)      /*!< Pixel clock active on Falling edge */\r\n#define DCMI_PCKPOLARITY_RISING     ((uint32_t)DCMI_CR_PCKPOL)  /*!< Pixel clock active on Rising edge  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity\r\n  * @{\r\n  */\r\n#define DCMI_VSPOLARITY_LOW     ((uint32_t)0x00000000U)     /*!< Vertical synchronization active Low  */\r\n#define DCMI_VSPOLARITY_HIGH    ((uint32_t)DCMI_CR_VSPOL)  /*!< Vertical synchronization active High */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity\r\n  * @{\r\n  */ \r\n#define DCMI_HSPOLARITY_LOW     ((uint32_t)0x00000000U)     /*!< Horizontal synchronization active Low  */\r\n#define DCMI_HSPOLARITY_HIGH    ((uint32_t)DCMI_CR_HSPOL)  /*!< Horizontal synchronization active High */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DCMI_MODE_JPEG DCMI MODE JPEG\r\n  * @{\r\n  */\r\n#define DCMI_JPEG_DISABLE   ((uint32_t)0x00000000U)    /*!< Mode JPEG Disabled  */\r\n#define DCMI_JPEG_ENABLE    ((uint32_t)DCMI_CR_JPEG)  /*!< Mode JPEG Enabled   */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DCMI_Capture_Rate DCMI Capture Rate\r\n  * @{\r\n  */\r\n#define DCMI_CR_ALL_FRAME            ((uint32_t)0x00000000U)      /*!< All frames are captured        */\r\n#define DCMI_CR_ALTERNATE_2_FRAME    ((uint32_t)DCMI_CR_FCRC_0)  /*!< Every alternate frame captured */\r\n#define DCMI_CR_ALTERNATE_4_FRAME    ((uint32_t)DCMI_CR_FCRC_1)  /*!< One frame in 4 frames captured */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode\r\n  * @{\r\n  */\r\n#define DCMI_EXTEND_DATA_8B     ((uint32_t)0x00000000U)                       /*!< Interface captures 8-bit data on every pixel clock  */\r\n#define DCMI_EXTEND_DATA_10B    ((uint32_t)DCMI_CR_EDM_0)                    /*!< Interface captures 10-bit data on every pixel clock */\r\n#define DCMI_EXTEND_DATA_12B    ((uint32_t)DCMI_CR_EDM_1)                    /*!< Interface captures 12-bit data on every pixel clock */\r\n#define DCMI_EXTEND_DATA_14B    ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1))  /*!< Interface captures 14-bit data on every pixel clock */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate \r\n  * @{\r\n  */\r\n#define DCMI_WINDOW_COORDINATE    ((uint32_t)0x3FFFU)  /*!< Window coordinate */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DCMI_Window_Height DCMI Window Height\r\n  * @{\r\n  */ \r\n#define DCMI_WINDOW_HEIGHT    ((uint32_t)0x1FFFU)  /*!< Window Height */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DCMI_interrupt_sources  DCMI interrupt sources\r\n  * @{\r\n  */\r\n#define DCMI_IT_FRAME    ((uint32_t)DCMI_IER_FRAME_IE)    /*!< Capture complete interrupt      */\r\n#define DCMI_IT_OVR      ((uint32_t)DCMI_IER_OVR_IE)      /*!< Overrun interrupt               */\r\n#define DCMI_IT_ERR      ((uint32_t)DCMI_IER_ERR_IE)      /*!< Synchronization error interrupt */\r\n#define DCMI_IT_VSYNC    ((uint32_t)DCMI_IER_VSYNC_IE)    /*!< VSYNC interrupt                 */\r\n#define DCMI_IT_LINE     ((uint32_t)DCMI_IER_LINE_IE)     /*!< Line interrupt                  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DCMI_Flags DCMI Flags\r\n  * @{\r\n  */\r\n\r\n/** \r\n  * @brief   DCMI SR register\r\n  */ \r\n#define DCMI_FLAG_HSYNC     ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC) /*!< HSYNC pin state (active line / synchronization between lines)   */\r\n#define DCMI_FLAG_VSYNC     ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC) /*!< VSYNC pin state (active frame / synchronization between frames) */\r\n#define DCMI_FLAG_FNE       ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE)   /*!< FIFO not empty flag                                                 */\r\n/** \r\n  * @brief   DCMI RIS register  \r\n  */ \r\n#define DCMI_FLAG_FRAMERI    ((uint32_t)DCMI_RIS_FRAME_RIS)  /*!< Frame capture complete interrupt flag */ \r\n#define DCMI_FLAG_OVRRI      ((uint32_t)DCMI_RIS_OVR_RIS)    /*!< Overrun interrupt flag                */ \r\n#define DCMI_FLAG_ERRRI      ((uint32_t)DCMI_RIS_ERR_RIS)    /*!< Synchronization error interrupt flag  */ \r\n#define DCMI_FLAG_VSYNCRI    ((uint32_t)DCMI_RIS_VSYNC_RIS)  /*!< VSYNC interrupt flag                  */ \r\n#define DCMI_FLAG_LINERI     ((uint32_t)DCMI_RIS_LINE_RIS)   /*!< Line interrupt flag                   */ \r\n/** \r\n  * @brief   DCMI MIS register  \r\n  */ \r\n#define DCMI_FLAG_FRAMEMI    ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS)  /*!< DCMI Frame capture complete masked interrupt status */      \r\n#define DCMI_FLAG_OVRMI      ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS  )  /*!< DCMI Overrun masked interrupt status                */               \r\n#define DCMI_FLAG_ERRMI      ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS  )  /*!< DCMI Synchronization error masked interrupt status  */ \r\n#define DCMI_FLAG_VSYNCMI    ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS)  /*!< DCMI VSYNC masked interrupt status                  */                 \r\n#define DCMI_FLAG_LINEMI     ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS )  /*!< DCMI Line masked interrupt status                   */                  \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup DCMI_Byte_Select_Mode DCMI Byte Select Mode\r\n  * @{\r\n  */\r\n#define DCMI_BSM_ALL                 ((uint32_t)0x00000000U) /*!< Interface captures all received data */\r\n#define DCMI_BSM_OTHER               ((uint32_t)DCMI_CR_BSM_0) /*!< Interface captures every other byte from the received data */\r\n#define DCMI_BSM_ALTERNATE_4         ((uint32_t)DCMI_CR_BSM_1) /*!< Interface captures one byte out of four */\r\n#define DCMI_BSM_ALTERNATE_2         ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1)) /*!< Interface captures two bytes out of four */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DCMI_Byte_Select_Start DCMI Byte Select Start\r\n  * @{\r\n  */ \r\n#define DCMI_OEBS_ODD               ((uint32_t)0x00000000U) /*!< Interface captures first data from the frame/line start, second one being dropped */\r\n#define DCMI_OEBS_EVEN              ((uint32_t)DCMI_CR_OEBS) /*!< Interface captures second data from the frame/line start, first one being dropped */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DCMI_Line_Select_Mode DCMI Line Select Mode\r\n  * @{\r\n  */\r\n#define DCMI_LSM_ALL                 ((uint32_t)0x00000000U) /*!< Interface captures all received lines */\r\n#define DCMI_LSM_ALTERNATE_2         ((uint32_t)DCMI_CR_LSM) /*!< Interface captures one line out of two */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DCMI_Line_Select_Start DCMI Line Select Start\r\n  * @{\r\n  */ \r\n#define DCMI_OELS_ODD               ((uint32_t)0x00000000U) /*!< Interface captures first line from the frame start, second one being dropped */\r\n#define DCMI_OELS_EVEN              ((uint32_t)DCMI_CR_OELS) /*!< Interface captures second line from the frame start, first one being dropped */\r\n\r\n/**\r\n  * @}\r\n  */\r\n    \r\n/**\r\n  * @}\r\n  */\r\n \r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup DCMI_Exported_Macros DCMI Exported Macros\r\n  * @{\r\n  */\r\n  \r\n/** @brief Reset DCMI handle state\r\n  * @param  __HANDLE__ specifies the DCMI handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)\r\n\r\n/**\r\n  * @brief  Enable the DCMI.\r\n  * @param  __HANDLE__ DCMI handle\r\n  * @retval None\r\n  */\r\n#define __HAL_DCMI_ENABLE(__HANDLE__)    ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)\r\n\r\n/**\r\n  * @brief  Disable the DCMI.\r\n  * @param  __HANDLE__ DCMI handle\r\n  * @retval None\r\n  */\r\n#define __HAL_DCMI_DISABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))\r\n\r\n/* Interrupt & Flag management */\r\n/**\r\n  * @brief  Get the DCMI pending flag.\r\n  * @param  __HANDLE__ DCMI handle\r\n  * @param  __FLAG__ Get the specified flag.\r\n  *         This parameter can be one of the following values (no combination allowed)\r\n  *            @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines)   \r\n  *            @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames) \r\n  *            @arg DCMI_FLAG_FNE: FIFO empty flag                                                  \r\n  *            @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask\r\n  *            @arg DCMI_FLAG_OVRRI: Overrun flag mask\r\n  *            @arg DCMI_FLAG_ERRRI: Synchronization error flag mask\r\n  *            @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask\r\n  *            @arg DCMI_FLAG_LINERI: Line flag mask\r\n  *            @arg DCMI_FLAG_FRAMEMI: DCMI Capture complete masked interrupt status      \r\n  *            @arg DCMI_FLAG_OVRMI: DCMI Overrun masked interrupt status               \r\n  *            @arg DCMI_FLAG_ERRMI: DCMI Synchronization error masked interrupt status \r\n  *            @arg DCMI_FLAG_VSYNCMI: DCMI VSYNC masked interrupt status                 \r\n  *            @arg DCMI_FLAG_LINEMI: DCMI Line masked interrupt status                  \r\n  * @retval The state of FLAG.\r\n  */\r\n#define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\\\r\n((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0)? ((__HANDLE__)->Instance->RIS & (__FLAG__)) :\\\r\n (((__FLAG__) & DCMI_SR_INDEX) == 0x0)? ((__HANDLE__)->Instance->MIS & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__)))\r\n\r\n/**\r\n  * @brief  Clear the DCMI pending flags.\r\n  * @param  __HANDLE__ DCMI handle\r\n  * @param  __FLAG__ specifies the flag to clear.\r\n  *         This parameter can be any combination of the following values:\r\n  *            @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask\r\n  *            @arg DCMI_FLAG_OVFRI: Overflow flag mask\r\n  *            @arg DCMI_FLAG_ERRRI: Synchronization error flag mask\r\n  *            @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask\r\n  *            @arg DCMI_FLAG_LINERI: Line flag mask\r\n  * @retval None\r\n  */\r\n#define __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))\r\n\r\n/**\r\n  * @brief  Enable the specified DCMI interrupts.\r\n  * @param  __HANDLE__    DCMI handle\r\n  * @param  __INTERRUPT__ specifies the DCMI interrupt sources to be enabled. \r\n  *         This parameter can be any combination of the following values:\r\n  *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask\r\n  *            @arg DCMI_IT_OVF: Overflow interrupt mask\r\n  *            @arg DCMI_IT_ERR: Synchronization error interrupt mask\r\n  *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask\r\n  *            @arg DCMI_IT_LINE: Line interrupt mask\r\n  * @retval None\r\n  */\r\n#define __HAL_DCMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disable the specified DCMI interrupts.\r\n  * @param  __HANDLE__ DCMI handle\r\n  * @param  __INTERRUPT__ specifies the DCMI interrupt sources to be enabled. \r\n  *         This parameter can be any combination of the following values:\r\n  *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask\r\n  *            @arg DCMI_IT_OVF: Overflow interrupt mask\r\n  *            @arg DCMI_IT_ERR: Synchronization error interrupt mask\r\n  *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask\r\n  *            @arg DCMI_IT_LINE: Line interrupt mask\r\n  * @retval None\r\n  */\r\n#define __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Check whether the specified DCMI interrupt has occurred or not.\r\n  * @param  __HANDLE__ DCMI handle\r\n  * @param  __INTERRUPT__ specifies the DCMI interrupt source to check.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask\r\n  *            @arg DCMI_IT_OVF: Overflow interrupt mask\r\n  *            @arg DCMI_IT_ERR: Synchronization error interrupt mask\r\n  *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask\r\n  *            @arg DCMI_IT_LINE: Line interrupt mask\r\n  * @retval The state of INTERRUPT.\r\n  */\r\n#define __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__))\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup DCMI_Exported_Functions DCMI Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions\r\n * @{\r\n */\r\n/* Initialization and de-initialization functions *****************************/\r\nHAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);\r\nHAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);\r\nvoid       HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi);\r\nvoid       HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi);\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @addtogroup DCMI_Exported_Functions_Group2 IO operation functions\r\n * @{\r\n */\r\n/* IO operation functions *****************************************************/\r\nHAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);\r\nHAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi);\r\nHAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi);\r\nHAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi);\r\nvoid       HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi);\r\nvoid       HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi);\r\nvoid       HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi);\r\nvoid       HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi);\r\nvoid       HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @addtogroup DCMI_Exported_Functions_Group3 Peripheral Control functions\r\n * @{\r\n */\r\n/* Peripheral Control functions ***********************************************/\r\nHAL_StatusTypeDef     HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);\r\nHAL_StatusTypeDef     HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi);\r\nHAL_StatusTypeDef     HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi);\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @addtogroup DCMI_Exported_Functions_Group4 Peripheral State functions\r\n * @{\r\n */\r\n/* Peripheral State functions *************************************************/\r\nHAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi);\r\nuint32_t              HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup DCMI_Private_Constants DCMI Private Constants\r\n  * @{\r\n  */\r\n#define DCMI_MIS_INDEX        ((uint32_t)0x1000) /*!< DCMI MIS register index */\r\n#define DCMI_SR_INDEX         ((uint32_t)0x2000) /*!< DCMI SR register index  */   \r\n/**\r\n  * @}\r\n  */   \r\n/* Private macro -------------------------------------------------------------*/\r\n/** @defgroup DCMI_Private_Macros DCMI Private Macros\r\n  * @{\r\n  */\r\n#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \\\r\n                                   ((MODE) == DCMI_MODE_SNAPSHOT))\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t \r\n#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \\\r\n                              ((MODE) == DCMI_SYNCHRO_EMBEDDED))\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\r\n#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \\\r\n                                      ((POLARITY) == DCMI_PCKPOLARITY_RISING))\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\r\n#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \\\r\n                                     ((POLARITY) == DCMI_VSPOLARITY_HIGH))\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t \r\n#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \\\r\n                                     ((POLARITY) == DCMI_HSPOLARITY_HIGH))\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t \r\n#define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \\\r\n                                     ((JPEG_MODE) == DCMI_JPEG_ENABLE))\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t \r\n#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME)         || \\\r\n                                    ((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \\\r\n                                    ((RATE) == DCMI_CR_ALTERNATE_4_FRAME))\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\r\n#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B)  || \\\r\n                                    ((DATA) == DCMI_EXTEND_DATA_10B) || \\\r\n                                    ((DATA) == DCMI_EXTEND_DATA_12B) || \\\r\n                                    ((DATA) == DCMI_EXTEND_DATA_14B))\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\r\n#define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)\r\n\r\n#define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)\r\n\r\n#define IS_DCMI_BYTE_SELECT_MODE(MODE)(((MODE) == DCMI_BSM_ALL) || \\\r\n                                       ((MODE) == DCMI_BSM_OTHER) || \\\r\n                                       ((MODE) == DCMI_BSM_ALTERNATE_4) || \\\r\n                                       ((MODE) == DCMI_BSM_ALTERNATE_2))\r\n                                                                                                \r\n#define IS_DCMI_BYTE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OEBS_ODD) || \\\r\n                                            ((POLARITY) == DCMI_OEBS_EVEN))\r\n                              \r\n#define IS_DCMI_LINE_SELECT_MODE(MODE)(((MODE) == DCMI_LSM_ALL) || \\\r\n                                       ((MODE) == DCMI_LSM_ALTERNATE_2))\r\n                                      \r\n#define IS_DCMI_LINE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OELS_ODD) || \\\r\n                                            ((POLARITY) == DCMI_OELS_EVEN))\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @addtogroup DCMI_Private_Functions DCMI Private Functions\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */\r\n      \r\n/**\r\n  * @}\r\n  */\r\n/**\r\n  * @}\r\n  */ \r\n#endif /* DCMI */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_DCMI_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dcmi_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_dcmi_ex.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of DCMI Extension HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_DCMI_EX_H\r\n#define __STM32F7xx_HAL_DCMI_EX_H\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n/* Exported macro ------------------------------------------------------------*/      \r\n/* Exported functions --------------------------------------------------------*/\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/   \r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n#endif /* __STM32F7xx_HAL_DCMI_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_def.h\r\n  * @author  MCD Application Team\r\n  * @brief   This file contains HAL common defines, enumeration, macros and \r\n  *          structures definitions. \r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_DEF\r\n#define __STM32F7xx_HAL_DEF\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx.h\"\r\n#include \"Legacy/stm32_hal_legacy.h\"\r\n#include <stdio.h>\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n\r\n/** \r\n  * @brief  HAL Status structures definition  \r\n  */  \r\ntypedef enum \r\n{\r\n  HAL_OK       = 0x00U,\r\n  HAL_ERROR    = 0x01U,\r\n  HAL_BUSY     = 0x02U,\r\n  HAL_TIMEOUT  = 0x03U\r\n} HAL_StatusTypeDef;\r\n\r\n/** \r\n  * @brief  HAL Lock structures definition  \r\n  */\r\ntypedef enum \r\n{\r\n  HAL_UNLOCKED = 0x00U,\r\n  HAL_LOCKED   = 0x01U  \r\n} HAL_LockTypeDef;\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n\r\n#define UNUSED(X) (void)X      /* To avoid gcc/g++ warnings */\r\n\r\n#define HAL_MAX_DELAY      0xFFFFFFFFU\r\n\r\n#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) != RESET)\r\n#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == RESET)\r\n\r\n#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__)               \\\r\n                        do{                                                      \\\r\n                              (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \\\r\n                              (__DMA_HANDLE__).Parent = (__HANDLE__);             \\\r\n                          } while(0)\r\n\r\n/** @brief Reset the Handle's State field.\r\n  * @param __HANDLE__ specifies the Peripheral Handle.\r\n  * @note  This macro can be used for the following purpose: \r\n  *          - When the Handle is declared as local variable; before passing it as parameter\r\n  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro \r\n  *            to set to 0 the Handle's \"State\" field.\r\n  *            Otherwise, \"State\" field may have any random value and the first time the function \r\n  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed\r\n  *            (i.e. HAL_PPP_MspInit() will not be executed).\r\n  *          - When there is a need to reconfigure the low level hardware: instead of calling\r\n  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().\r\n  *            In this later function, when the Handle's \"State\" field is set to 0, it will execute the function\r\n  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.\r\n  * @retval None\r\n  */\r\n#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)\r\n\r\n#if (USE_RTOS == 1U)\r\n  /* Reserved for future use */\r\n  #error \"USE_RTOS should be 0 in the current HAL release\"\r\n#else\r\n  #define __HAL_LOCK(__HANDLE__)                                           \\\r\n                                do{                                        \\\r\n                                    if((__HANDLE__)->Lock == HAL_LOCKED)   \\\r\n                                    {                                      \\\r\n                                       return HAL_BUSY;                    \\\r\n                                    }                                      \\\r\n                                    else                                   \\\r\n                                    {                                      \\\r\n                                       (__HANDLE__)->Lock = HAL_LOCKED;    \\\r\n                                    }                                      \\\r\n                                  }while (0U)\r\n\r\n  #define __HAL_UNLOCK(__HANDLE__)                                          \\\r\n                                  do{                                       \\\r\n                                      (__HANDLE__)->Lock = HAL_UNLOCKED;    \\\r\n                                    }while (0U)\r\n#endif /* USE_RTOS */\r\n\r\n#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */\r\n  #ifndef __weak\r\n    #define __weak   __attribute__((weak))\r\n  #endif /* __weak */\r\n  #ifndef __packed\r\n    #define __packed __attribute__((__packed__))\r\n  #endif /* __packed */\r\n#endif /* __GNUC__ */\r\n\r\n\r\n/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive \"#pragma data_alignment=4\" must be used instead */\r\n#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */\r\n  #ifndef __ALIGN_END\r\n    #define __ALIGN_END    __attribute__ ((aligned (4)))\r\n  #endif /* __ALIGN_END */\r\n  #ifndef __ALIGN_BEGIN  \r\n    #define __ALIGN_BEGIN\r\n  #endif /* __ALIGN_BEGIN */\r\n#else\r\n  #ifndef __ALIGN_END\r\n    #define __ALIGN_END\r\n  #endif /* __ALIGN_END */\r\n  #ifndef __ALIGN_BEGIN      \r\n    #if defined   (__CC_ARM)      /* ARM Compiler */\r\n      #define __ALIGN_BEGIN    __align(4)\r\n    #elif defined (__ICCARM__)    /* IAR Compiler */\r\n      #define __ALIGN_BEGIN \r\n    #endif /* __CC_ARM */\r\n  #endif /* __ALIGN_BEGIN */\r\n#endif /* __GNUC__ */\r\n\r\n/* Macro to get variable aligned on 32-bytes,needed for cache maintenance purpose */\r\n#if defined   (__GNUC__)      /* GNU Compiler */\r\n  #define ALIGN_32BYTES(buf)  buf __attribute__ ((aligned (32)))\r\n#elif defined (__ICCARM__)    /* IAR Compiler */\r\n  #define ALIGN_32BYTES(buf) _Pragma(\"data_alignment=32\") buf\r\n#elif defined (__CC_ARM)      /* ARM Compiler */\r\n  #define ALIGN_32BYTES(buf) __align(32) buf\r\n#endif\r\n\r\n/**\r\n  * @brief  __RAM_FUNC definition\r\n  */ \r\n#if defined ( __CC_ARM   )\r\n/* ARM Compiler\r\n   ------------\r\n   RAM functions are defined using the toolchain options. \r\n   Functions that are executed in RAM should reside in a separate source module.\r\n   Using the 'Options for File' dialog you can simply change the 'Code / Const' \r\n   area of a module to a memory space in physical RAM.\r\n   Available memory areas are declared in the 'Target' tab of the 'Options for Target'\r\n   dialog. \r\n*/\r\n#define __RAM_FUNC \r\n\r\n#elif defined ( __ICCARM__ )\r\n/* ICCARM Compiler\r\n   ---------------\r\n   RAM functions are defined using a specific toolchain keyword \"__ramfunc\". \r\n*/\r\n#define __RAM_FUNC __ramfunc\r\n\r\n#elif defined   (  __GNUC__  )\r\n/* GNU Compiler\r\n   ------------\r\n  RAM functions are defined using a specific toolchain attribute \r\n   \"__attribute__((section(\".RamFunc\")))\".\r\n*/\r\n#define __RAM_FUNC __attribute__((section(\".RamFunc\")))\r\n\r\n#endif\r\n\r\n/** \r\n  * @brief  __NOINLINE definition\r\n  */ \r\n#if defined ( __CC_ARM   ) || defined   (  __GNUC__  )\r\n/* ARM & GNUCompiler \r\n   ---------------- \r\n*/\r\n#define __NOINLINE __attribute__ ( (noinline) )\r\n\r\n#elif defined ( __ICCARM__ )\r\n/* ICCARM Compiler\r\n   ---------------\r\n*/\r\n#define __NOINLINE _Pragma(\"optimize = no_inline\")\r\n\r\n#endif\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* ___STM32F7xx_HAL_DEF */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_dma.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of DMA HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_DMA_H\r\n#define __STM32F7xx_HAL_DMA_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup DMA\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n\r\n/** @defgroup DMA_Exported_Types DMA Exported Types\r\n  * @brief    DMA Exported Types \r\n  * @{\r\n  */\r\n   \r\n/** \r\n  * @brief  DMA Configuration Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t Channel;              /*!< Specifies the channel used for the specified stream. \r\n                                      This parameter can be a value of @ref DMAEx_Channel_selection                  */\r\n\r\n  uint32_t Direction;            /*!< Specifies if the data will be transferred from memory to peripheral, \r\n                                      from memory to memory or from peripheral to memory.\r\n                                      This parameter can be a value of @ref DMA_Data_transfer_direction              */\r\n\r\n  uint32_t PeriphInc;            /*!< Specifies whether the Peripheral address register should be incremented or not.\r\n                                      This parameter can be a value of @ref DMA_Peripheral_incremented_mode          */\r\n\r\n  uint32_t MemInc;               /*!< Specifies whether the memory address register should be incremented or not.\r\n                                      This parameter can be a value of @ref DMA_Memory_incremented_mode              */\r\n\r\n  uint32_t PeriphDataAlignment;  /*!< Specifies the Peripheral data width.\r\n                                      This parameter can be a value of @ref DMA_Peripheral_data_size                 */\r\n\r\n  uint32_t MemDataAlignment;     /*!< Specifies the Memory data width.\r\n                                      This parameter can be a value of @ref DMA_Memory_data_size                     */\r\n\r\n  uint32_t Mode;                 /*!< Specifies the operation mode of the DMAy Streamx.\r\n                                      This parameter can be a value of @ref DMA_mode\r\n                                      @note The circular buffer mode cannot be used if the memory-to-memory\r\n                                            data transfer is configured on the selected Stream                        */\r\n\r\n  uint32_t Priority;             /*!< Specifies the software priority for the DMAy Streamx.\r\n                                      This parameter can be a value of @ref DMA_Priority_level                       */\r\n\r\n  uint32_t FIFOMode;             /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.\r\n                                      This parameter can be a value of @ref DMA_FIFO_direct_mode\r\n                                      @note The Direct mode (FIFO mode disabled) cannot be used if the \r\n                                            memory-to-memory data transfer is configured on the selected stream       */\r\n\r\n  uint32_t FIFOThreshold;        /*!< Specifies the FIFO threshold level.\r\n                                      This parameter can be a value of @ref DMA_FIFO_threshold_level                  */\r\n\r\n  uint32_t MemBurst;             /*!< Specifies the Burst transfer configuration for the memory transfers. \r\n                                      It specifies the amount of data to be transferred in a single non interruptible \r\n                                      transaction.\r\n                                      This parameter can be a value of @ref DMA_Memory_burst \r\n                                      @note The burst mode is possible only if the address Increment mode is enabled. */\r\n\r\n  uint32_t PeriphBurst;          /*!< Specifies the Burst transfer configuration for the peripheral transfers. \r\n                                      It specifies the amount of data to be transferred in a single non interruptible \r\n                                      transaction. \r\n                                      This parameter can be a value of @ref DMA_Peripheral_burst\r\n                                      @note The burst mode is possible only if the address Increment mode is enabled. */\r\n}DMA_InitTypeDef;\r\n\r\n/** \r\n  * @brief  HAL DMA State structures definition\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled */\r\n  HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use   */\r\n  HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing              */\r\n  HAL_DMA_STATE_TIMEOUT           = 0x03U,  /*!< DMA timeout state                   */\r\n  HAL_DMA_STATE_ERROR             = 0x04U,  /*!< DMA error state                     */\r\n  HAL_DMA_STATE_ABORT             = 0x05U,  /*!< DMA Abort state                     */\r\n}HAL_DMA_StateTypeDef;\r\n\r\n/** \r\n  * @brief  HAL DMA Error Code structure definition\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_DMA_FULL_TRANSFER      = 0x00U,    /*!< Full transfer     */\r\n  HAL_DMA_HALF_TRANSFER      = 0x01U,    /*!< Half Transfer     */\r\n}HAL_DMA_LevelCompleteTypeDef;\r\n\r\n/** \r\n  * @brief  HAL DMA Error Code structure definition\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer     */\r\n  HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,    /*!< Half Transfer     */\r\n  HAL_DMA_XFER_M1CPLT_CB_ID        = 0x02U,    /*!< M1 Full Transfer  */\r\n  HAL_DMA_XFER_M1HALFCPLT_CB_ID    = 0x03U,    /*!< M1 Half Transfer  */\r\n  HAL_DMA_XFER_ERROR_CB_ID         = 0x04U,    /*!< Error             */\r\n  HAL_DMA_XFER_ABORT_CB_ID         = 0x05U,    /*!< Abort             */\r\n  HAL_DMA_XFER_ALL_CB_ID           = 0x06U     /*!< All               */\r\n}HAL_DMA_CallbackIDTypeDef;\r\n\r\n/** \r\n  * @brief  DMA handle Structure definition\r\n  */\r\ntypedef struct __DMA_HandleTypeDef\r\n{\r\n  DMA_Stream_TypeDef         *Instance;                                                    /*!< Register base address                  */\r\n\r\n  DMA_InitTypeDef            Init;                                                         /*!< DMA communication parameters           */ \r\n\r\n  HAL_LockTypeDef            Lock;                                                         /*!< DMA locking object                     */  \r\n\r\n  __IO HAL_DMA_StateTypeDef  State;                                                        /*!< DMA transfer state                     */\r\n\r\n  void                       *Parent;                                                      /*!< Parent object state                    */ \r\n\r\n  void                       (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback         */\r\n\r\n  void                       (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback    */\r\n\r\n  void                       (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer complete Memory1 callback */\r\n  \r\n  void                       (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer Half complete Memory1 callback */\r\n  \r\n  void                       (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback            */\r\n  \r\n  void                       (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer Abort callback            */  \r\n\r\n __IO uint32_t               ErrorCode;                                                    /*!< DMA Error code                          */\r\n  \r\n uint32_t                    StreamBaseAddress;                                            /*!< DMA Stream Base Address                */\r\n\r\n uint32_t                    StreamIndex;                                                  /*!< DMA Stream Index                       */\r\n \r\n}DMA_HandleTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup DMA_Exported_Constants DMA Exported Constants\r\n  * @brief    DMA Exported constants \r\n  * @{\r\n  */\r\n\r\n/** @defgroup DMA_Error_Code DMA Error Code\r\n  * @brief    DMA Error Code \r\n  * @{\r\n  */ \r\n#define HAL_DMA_ERROR_NONE                       0x00000000U    /*!< No error                               */\r\n#define HAL_DMA_ERROR_TE                         0x00000001U    /*!< Transfer error                         */\r\n#define HAL_DMA_ERROR_FE                         0x00000002U    /*!< FIFO error                             */\r\n#define HAL_DMA_ERROR_DME                        0x00000004U    /*!< Direct Mode error                      */\r\n#define HAL_DMA_ERROR_TIMEOUT                    0x00000020U    /*!< Timeout error                          */\r\n#define HAL_DMA_ERROR_PARAM                      0x00000040U    /*!< Parameter error                        */\r\n#define HAL_DMA_ERROR_NO_XFER                    0x00000080U    /*!< Abort requested with no Xfer ongoing   */\r\n#define HAL_DMA_ERROR_NOT_SUPPORTED              0x00000100U    /*!< Not supported mode                     */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction\r\n  * @brief    DMA data transfer direction \r\n  * @{\r\n  */ \r\n#define DMA_PERIPH_TO_MEMORY                     0x00000000U      /*!< Peripheral to memory direction */\r\n#define DMA_MEMORY_TO_PERIPH                     DMA_SxCR_DIR_0   /*!< Memory to peripheral direction */\r\n#define DMA_MEMORY_TO_MEMORY                     DMA_SxCR_DIR_1   /*!< Memory to memory direction     */\r\n/**\r\n  * @}\r\n  */\r\n        \r\n/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode\r\n  * @brief    DMA peripheral incremented mode \r\n  * @{\r\n  */ \r\n#define DMA_PINC_ENABLE                          DMA_SxCR_PINC    /*!< Peripheral increment mode enable  */\r\n#define DMA_PINC_DISABLE                         0x00000000U      /*!< Peripheral increment mode disable */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode\r\n  * @brief    DMA memory incremented mode \r\n  * @{\r\n  */ \r\n#define DMA_MINC_ENABLE                          DMA_SxCR_MINC    /*!< Memory increment mode enable  */\r\n#define DMA_MINC_DISABLE                         0x00000000U      /*!< Memory increment mode disable */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size\r\n  * @brief    DMA peripheral data size \r\n  * @{\r\n  */ \r\n#define DMA_PDATAALIGN_BYTE                      0x00000000U        /*!< Peripheral data alignment: Byte     */\r\n#define DMA_PDATAALIGN_HALFWORD                  DMA_SxCR_PSIZE_0   /*!< Peripheral data alignment: HalfWord */\r\n#define DMA_PDATAALIGN_WORD                      DMA_SxCR_PSIZE_1   /*!< Peripheral data alignment: Word     */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup DMA_Memory_data_size DMA Memory data size\r\n  * @brief    DMA memory data size \r\n  * @{ \r\n  */\r\n#define DMA_MDATAALIGN_BYTE                      0x00000000U        /*!< Memory data alignment: Byte     */\r\n#define DMA_MDATAALIGN_HALFWORD                  DMA_SxCR_MSIZE_0   /*!< Memory data alignment: HalfWord */\r\n#define DMA_MDATAALIGN_WORD                      DMA_SxCR_MSIZE_1   /*!< Memory data alignment: Word     */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DMA_mode DMA mode\r\n  * @brief    DMA mode \r\n  * @{\r\n  */ \r\n#define DMA_NORMAL                               0x00000000U       /*!< Normal mode                  */\r\n#define DMA_CIRCULAR                             DMA_SxCR_CIRC     /*!< Circular mode                */\r\n#define DMA_PFCTRL                               DMA_SxCR_PFCTRL   /*!< Peripheral flow control mode */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DMA_Priority_level DMA Priority level\r\n  * @brief    DMA priority levels \r\n  * @{\r\n  */\r\n#define DMA_PRIORITY_LOW                         0x00000000U    /*!< Priority level: Low       */\r\n#define DMA_PRIORITY_MEDIUM                      DMA_SxCR_PL_0  /*!< Priority level: Medium    */\r\n#define DMA_PRIORITY_HIGH                        DMA_SxCR_PL_1  /*!< Priority level: High      */\r\n#define DMA_PRIORITY_VERY_HIGH                   DMA_SxCR_PL    /*!< Priority level: Very High */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode\r\n  * @brief    DMA FIFO direct mode\r\n  * @{\r\n  */\r\n#define DMA_FIFOMODE_DISABLE                     0x00000000U       /*!< FIFO mode disable */\r\n#define DMA_FIFOMODE_ENABLE                      DMA_SxFCR_DMDIS   /*!< FIFO mode enable  */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level\r\n  * @brief    DMA FIFO level \r\n  * @{\r\n  */\r\n#define DMA_FIFO_THRESHOLD_1QUARTERFULL          0x00000000U       /*!< FIFO threshold 1 quart full configuration  */\r\n#define DMA_FIFO_THRESHOLD_HALFFULL              DMA_SxFCR_FTH_0   /*!< FIFO threshold half full configuration     */\r\n#define DMA_FIFO_THRESHOLD_3QUARTERSFULL         DMA_SxFCR_FTH_1   /*!< FIFO threshold 3 quarts full configuration */\r\n#define DMA_FIFO_THRESHOLD_FULL                  DMA_SxFCR_FTH     /*!< FIFO threshold full configuration          */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup DMA_Memory_burst DMA Memory burst\r\n  * @brief    DMA memory burst \r\n  * @{\r\n  */ \r\n#define DMA_MBURST_SINGLE                        0x00000000U\r\n#define DMA_MBURST_INC4                          DMA_SxCR_MBURST_0\r\n#define DMA_MBURST_INC8                          DMA_SxCR_MBURST_1\r\n#define DMA_MBURST_INC16                         DMA_SxCR_MBURST\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup DMA_Peripheral_burst DMA Peripheral burst\r\n  * @brief    DMA peripheral burst \r\n  * @{\r\n  */ \r\n#define DMA_PBURST_SINGLE                        0x00000000U\r\n#define DMA_PBURST_INC4                          DMA_SxCR_PBURST_0\r\n#define DMA_PBURST_INC8                          DMA_SxCR_PBURST_1\r\n#define DMA_PBURST_INC16                         DMA_SxCR_PBURST\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions\r\n  * @brief    DMA interrupts definition \r\n  * @{\r\n  */\r\n#define DMA_IT_TC                                DMA_SxCR_TCIE\r\n#define DMA_IT_HT                                DMA_SxCR_HTIE\r\n#define DMA_IT_TE                                DMA_SxCR_TEIE\r\n#define DMA_IT_DME                               DMA_SxCR_DMEIE\r\n#define DMA_IT_FE                                0x00000080U\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DMA_flag_definitions DMA flag definitions\r\n  * @brief    DMA flag definitions \r\n  * @{\r\n  */ \r\n#define DMA_FLAG_FEIF0_4                         0x00000001U\r\n#define DMA_FLAG_DMEIF0_4                        0x00000004U\r\n#define DMA_FLAG_TEIF0_4                         0x00000008U\r\n#define DMA_FLAG_HTIF0_4                         0x00000010U\r\n#define DMA_FLAG_TCIF0_4                         0x00000020U\r\n#define DMA_FLAG_FEIF1_5                         0x00000040U\r\n#define DMA_FLAG_DMEIF1_5                        0x00000100U\r\n#define DMA_FLAG_TEIF1_5                         0x00000200U\r\n#define DMA_FLAG_HTIF1_5                         0x00000400U\r\n#define DMA_FLAG_TCIF1_5                         0x00000800U\r\n#define DMA_FLAG_FEIF2_6                         0x00010000U\r\n#define DMA_FLAG_DMEIF2_6                        0x00040000U\r\n#define DMA_FLAG_TEIF2_6                         0x00080000U\r\n#define DMA_FLAG_HTIF2_6                         0x00100000U\r\n#define DMA_FLAG_TCIF2_6                         0x00200000U\r\n#define DMA_FLAG_FEIF3_7                         0x00400000U\r\n#define DMA_FLAG_DMEIF3_7                        0x01000000U\r\n#define DMA_FLAG_TEIF3_7                         0x02000000U\r\n#define DMA_FLAG_HTIF3_7                         0x04000000U\r\n#define DMA_FLAG_TCIF3_7                         0x08000000U\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n \r\n/* Exported macro ------------------------------------------------------------*/\r\n\r\n/** @brief Reset DMA handle state\r\n  * @param  __HANDLE__ specifies the DMA handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)\r\n\r\n/**\r\n  * @brief  Return the current DMA Stream FIFO filled level.\r\n  * @param  __HANDLE__ DMA handle\r\n  * @retval The FIFO filling state.\r\n  *           - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full \r\n  *                                              and not empty.\r\n  *           - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.\r\n  *           - DMA_FIFOStatus_HalfFull: if more than 1 half-full.\r\n  *           - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.\r\n  *           - DMA_FIFOStatus_Empty: when FIFO is empty\r\n  *           - DMA_FIFOStatus_Full: when FIFO is full\r\n  */\r\n#define __HAL_DMA_GET_FS(__HANDLE__)      (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))\r\n\r\n/**\r\n  * @brief  Enable the specified DMA Stream.\r\n  * @param  __HANDLE__ DMA handle\r\n  * @retval None\r\n  */\r\n#define __HAL_DMA_ENABLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  DMA_SxCR_EN)\r\n\r\n/**\r\n  * @brief  Disable the specified DMA Stream.\r\n  * @param  __HANDLE__ DMA handle\r\n  * @retval None\r\n  */\r\n#define __HAL_DMA_DISABLE(__HANDLE__)     ((__HANDLE__)->Instance->CR &=  ~DMA_SxCR_EN)\r\n\r\n/* Interrupt & Flag management */\r\n\r\n/**\r\n  * @brief  Return the current DMA Stream transfer complete flag.\r\n  * @param  __HANDLE__ DMA handle\r\n  * @retval The specified transfer complete flag index.\r\n  */\r\n#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \\\r\n(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\\\r\n   DMA_FLAG_TCIF3_7)\r\n\r\n/**\r\n  * @brief  Return the current DMA Stream half transfer complete flag.\r\n  * @param  __HANDLE__ DMA handle\r\n  * @retval The specified half transfer complete flag index.\r\n  */      \r\n#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\\\r\n(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\\\r\n   DMA_FLAG_HTIF3_7)\r\n\r\n/**\r\n  * @brief  Return the current DMA Stream transfer error flag.\r\n  * @param  __HANDLE__ DMA handle\r\n  * @retval The specified transfer error flag index.\r\n  */\r\n#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\\\r\n(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\\\r\n   DMA_FLAG_TEIF3_7)\r\n\r\n/**\r\n  * @brief  Return the current DMA Stream FIFO error flag.\r\n  * @param  __HANDLE__ DMA handle\r\n  * @retval The specified FIFO error flag index.\r\n  */\r\n#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\\\r\n(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\\\r\n   DMA_FLAG_FEIF3_7)\r\n\r\n/**\r\n  * @brief  Return the current DMA Stream direct mode error flag.\r\n  * @param  __HANDLE__ DMA handle\r\n  * @retval The specified direct mode error flag index.\r\n  */\r\n#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\\\r\n(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\\\r\n   DMA_FLAG_DMEIF3_7)\r\n\r\n/**\r\n  * @brief  Get the DMA Stream pending flags.\r\n  * @param  __HANDLE__ DMA handle\r\n  * @param  __FLAG__ Get the specified flag.\r\n  *          This parameter can be any combination of the following values:\r\n  *            @arg DMA_FLAG_TCIFx: Transfer complete flag.\r\n  *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.\r\n  *            @arg DMA_FLAG_TEIFx: Transfer error flag.\r\n  *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.\r\n  *            @arg DMA_FLAG_FEIFx: FIFO error flag.\r\n  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.   \r\n  * @retval The state of FLAG (SET or RESET).\r\n  */\r\n#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\\\r\n(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\\\r\n ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\\\r\n ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))\r\n\r\n/**\r\n  * @brief  Clear the DMA Stream pending flags.\r\n  * @param  __HANDLE__ DMA handle\r\n  * @param  __FLAG__ specifies the flag to clear.\r\n  *          This parameter can be any combination of the following values:\r\n  *            @arg DMA_FLAG_TCIFx: Transfer complete flag.\r\n  *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.\r\n  *            @arg DMA_FLAG_TEIFx: Transfer error flag.\r\n  *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.\r\n  *            @arg DMA_FLAG_FEIFx: FIFO error flag.\r\n  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.   \r\n  * @retval None\r\n  */\r\n#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \\\r\n(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\\\r\n ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\\\r\n ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))\r\n\r\n/**\r\n  * @brief  Enable the specified DMA Stream interrupts.\r\n  * @param  __HANDLE__ DMA handle\r\n  * @param  __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. \r\n  *        This parameter can be one of the following values:\r\n  *           @arg DMA_IT_TC: Transfer complete interrupt mask.\r\n  *           @arg DMA_IT_HT: Half transfer complete interrupt mask.\r\n  *           @arg DMA_IT_TE: Transfer error interrupt mask.\r\n  *           @arg DMA_IT_FE: FIFO error interrupt mask.\r\n  *           @arg DMA_IT_DME: Direct mode error interrupt.\r\n  * @retval None\r\n  */\r\n#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((__INTERRUPT__) != DMA_IT_FE)? \\\r\n((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))\r\n\r\n/**\r\n  * @brief  Disable the specified DMA Stream interrupts.\r\n  * @param  __HANDLE__ DMA handle\r\n  * @param  __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. \r\n  *         This parameter can be one of the following values:\r\n  *            @arg DMA_IT_TC: Transfer complete interrupt mask.\r\n  *            @arg DMA_IT_HT: Half transfer complete interrupt mask.\r\n  *            @arg DMA_IT_TE: Transfer error interrupt mask.\r\n  *            @arg DMA_IT_FE: FIFO error interrupt mask.\r\n  *            @arg DMA_IT_DME: Direct mode error interrupt.\r\n  * @retval None\r\n  */\r\n#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \\\r\n((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))\r\n\r\n/**\r\n  * @brief  Check whether the specified DMA Stream interrupt is enabled or not.\r\n  * @param  __HANDLE__ DMA handle\r\n  * @param  __INTERRUPT__ specifies the DMA interrupt source to check.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg DMA_IT_TC: Transfer complete interrupt mask.\r\n  *            @arg DMA_IT_HT: Half transfer complete interrupt mask.\r\n  *            @arg DMA_IT_TE: Transfer error interrupt mask.\r\n  *            @arg DMA_IT_FE: FIFO error interrupt mask.\r\n  *            @arg DMA_IT_DME: Direct mode error interrupt.\r\n  * @retval The state of DMA_IT.\r\n  */\r\n#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \\\r\n                                                        ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \\\r\n                                                        ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))\r\n\r\n/**\r\n  * @brief  Writes the number of data units to be transferred on the DMA Stream.\r\n  * @param  __HANDLE__ DMA handle\r\n  * @param  __COUNTER__ Number of data units to be transferred (from 0 to 65535) \r\n  *          Number of data items depends only on the Peripheral data format.\r\n  *            \r\n  * @note   If Peripheral data format is Bytes: number of data units is equal \r\n  *         to total number of bytes to be transferred.\r\n  *           \r\n  * @note   If Peripheral data format is Half-Word: number of data units is  \r\n  *         equal to total number of bytes to be transferred / 2.\r\n  *           \r\n  * @note   If Peripheral data format is Word: number of data units is equal \r\n  *         to total  number of bytes to be transferred / 4.\r\n  *      \r\n  * @retval The number of remaining data units in the current DMAy Streamx transfer.\r\n  */\r\n#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))\r\n\r\n/**\r\n  * @brief  Returns the number of remaining data units in the current DMAy Streamx transfer.\r\n  * @param  __HANDLE__ DMA handle\r\n  *   \r\n  * @retval The number of remaining data units in the current DMA Stream transfer.\r\n  */\r\n#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)\r\n\r\n\r\n/* Include DMA HAL Extension module */\r\n#include \"stm32f7xx_hal_dma_ex.h\"   \r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @defgroup DMA_Exported_Functions DMA Exported Functions\r\n  * @brief    DMA Exported functions \r\n  * @{\r\n  */\r\n\r\n/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions\r\n  * @brief   Initialization and de-initialization functions \r\n  * @{\r\n  */\r\nHAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); \r\nHAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions\r\n  * @brief   I/O operation functions  \r\n  * @{\r\n  */\r\nHAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r\nHAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r\nHAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);\r\nHAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);\r\nHAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);\r\nvoid              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);\r\nHAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));\r\nHAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions\r\n  * @brief    Peripheral State functions \r\n  * @{\r\n  */\r\nHAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);\r\nuint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);\r\n/**\r\n  * @}\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n/* Private Constants -------------------------------------------------------------*/\r\n/** @defgroup DMA_Private_Constants DMA Private Constants\r\n  * @brief    DMA private defines and constants \r\n  * @{\r\n  */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup DMA_Private_Macros DMA Private Macros\r\n  * @brief    DMA private macros \r\n  * @{\r\n  */\r\n#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \\\r\n                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \\\r\n                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) \r\n\r\n#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))\r\n\r\n#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \\\r\n                                            ((STATE) == DMA_PINC_DISABLE))\r\n\r\n#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \\\r\n                                        ((STATE) == DMA_MINC_DISABLE))\r\n\r\n#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \\\r\n                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \\\r\n                                           ((SIZE) == DMA_PDATAALIGN_WORD))\r\n\r\n#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \\\r\n                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \\\r\n                                       ((SIZE) == DMA_MDATAALIGN_WORD ))\r\n\r\n#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \\\r\n                           ((MODE) == DMA_CIRCULAR) || \\\r\n                           ((MODE) == DMA_PFCTRL)) \r\n\r\n#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \\\r\n                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \\\r\n                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \\\r\n                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) \r\n\r\n#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \\\r\n                                       ((STATE) == DMA_FIFOMODE_ENABLE))\r\n\r\n#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \\\r\n                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL)      || \\\r\n                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \\\r\n                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))\r\n\r\n#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \\\r\n                                    ((BURST) == DMA_MBURST_INC4)   || \\\r\n                                    ((BURST) == DMA_MBURST_INC8)   || \\\r\n                                    ((BURST) == DMA_MBURST_INC16))\r\n\r\n#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \\\r\n                                        ((BURST) == DMA_PBURST_INC4)   || \\\r\n                                        ((BURST) == DMA_PBURST_INC8)   || \\\r\n                                        ((BURST) == DMA_PBURST_INC16))\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup DMA_Private_Functions DMA Private Functions\r\n  * @brief    DMA private  functions \r\n  * @{\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_DMA_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_dma2d.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of DMA2D HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_DMA2D_H\r\n#define __STM32F7xx_HAL_DMA2D_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n#if defined (DMA2D)\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup DMA2D DMA2D\r\n  * @brief DMA2D HAL module driver\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup DMA2D_Exported_Types DMA2D Exported Types\r\n  * @{\r\n  */\r\n#define MAX_DMA2D_LAYER  2\r\n\r\n/** \r\n  * @brief DMA2D color Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t Blue;               /*!< Configures the blue value.\r\n                                    This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */\r\n\r\n  uint32_t Green;              /*!< Configures the green value.\r\n                                    This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */\r\n\r\n  uint32_t Red;                /*!< Configures the red value.\r\n                                    This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */\r\n} DMA2D_ColorTypeDef;\r\n\r\n/** \r\n  * @brief DMA2D CLUT Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t *pCLUT;                  /*!< Configures the DMA2D CLUT memory address.*/\r\n\r\n  uint32_t CLUTColorMode;           /*!< Configures the DMA2D CLUT color mode.\r\n                                         This parameter can be one value of @ref DMA2D_CLUT_CM. */\r\n\r\n  uint32_t Size;                    /*!< Configures the DMA2D CLUT size. \r\n                                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/\r\n} DMA2D_CLUTCfgTypeDef;\r\n\r\n/** \r\n  * @brief DMA2D Init structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t             Mode;               /*!< Configures the DMA2D transfer mode.\r\n                                                This parameter can be one value of @ref DMA2D_Mode. */\r\n\r\n  uint32_t             ColorMode;          /*!< Configures the color format of the output image.\r\n                                                This parameter can be one value of @ref DMA2D_Output_Color_Mode. */\r\n\r\n  uint32_t             OutputOffset;       /*!< Specifies the Offset value. \r\n                                                This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */\r\n#if defined (DMA2D_OPFCCR_AI)\r\n  uint32_t             AlphaInverted;     /*!< Select regular or inverted alpha value for the output pixel format converter.\r\n                                               This parameter can be one value of @ref DMA2D_Alpha_Inverted. */\r\n#endif /* DMA2D_OPFCCR_AI */  \r\n\r\n#if defined (DMA2D_OPFCCR_RBS) \r\n  uint32_t             RedBlueSwap;       /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR)\r\n                                               for the output pixel format converter.\r\n                                               This parameter can be one value of @ref DMA2D_RB_Swap. */ \r\n#endif /* DMA2D_OPFCCR_RBS */\r\n  \r\n} DMA2D_InitTypeDef;\r\n\r\n\r\n/** \r\n  * @brief DMA2D Layer structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t             InputOffset;       /*!< Configures the DMA2D foreground or background offset.\r\n                                               This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */\r\n\r\n  uint32_t             InputColorMode;    /*!< Configures the DMA2D foreground or background color mode. \r\n                                               This parameter can be one value of @ref DMA2D_Input_Color_Mode. */\r\n\r\n  uint32_t             AlphaMode;         /*!< Configures the DMA2D foreground or background alpha mode. \r\n                                               This parameter can be one value of @ref DMA2D_Alpha_Mode. */\r\n\r\n  uint32_t             InputAlpha;        /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode. \r\n                                               This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below.\r\n                                               @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between \r\n                                               Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where \r\n                                               - InputAlpha[24:31] is the alpha value ALPHA[0:7]\r\n                                               - InputAlpha[16:23] is the red value RED[0:7]\r\n                                               - InputAlpha[8:15] is the green value GREEN[0:7]\r\n                                               - InputAlpha[0:7] is the blue value BLUE[0:7]. */\r\n\r\n#if defined (DMA2D_FGPFCCR_AI) && defined (DMA2D_BGPFCCR_AI) \r\n  uint32_t             AlphaInverted;     /*!< Select regular or inverted alpha value.\r\n                                               This parameter can be one value of @ref DMA2D_Alpha_Inverted. \r\n                                               This feature is only available on devices :\r\n                                               STM32F756xx, STM32F767xx, STM32F769xx, STM32F777xx and STM32F779xx.*/\r\n  \r\n#endif /* (DMA2D_FGPFCCR_AI) && (DMA2D_BGPFCCR_AI)  */   \r\n\r\n#if defined (DMA2D_FGPFCCR_RBS) && defined (DMA2D_BGPFCCR_RBS)   \r\n  uint32_t             RedBlueSwap;       /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR).\r\n                                               This parameter can be one value of @ref DMA2D_RB_Swap\r\n                                               This feature is only available on devices :\r\n                                               STM32F756xx, STM32F767xx, STM32F769xx, STM32F777xx and STM32F779xx.*/  \r\n\r\n#endif /* (DMA2D_FGPFCCR_RBS) && (DMA2D_BGPFCCR_RBS)  */\r\n  \r\n} DMA2D_LayerCfgTypeDef;\r\n\r\n/** \r\n  * @brief  HAL DMA2D State structures definition\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_DMA2D_STATE_RESET             = 0x00U,    /*!< DMA2D not yet initialized or disabled       */\r\n  HAL_DMA2D_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */\r\n  HAL_DMA2D_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */\r\n  HAL_DMA2D_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */\r\n  HAL_DMA2D_STATE_ERROR             = 0x04U,    /*!< DMA2D state error                           */\r\n  HAL_DMA2D_STATE_SUSPEND           = 0x05U     /*!< DMA2D process is suspended                  */\r\n}HAL_DMA2D_StateTypeDef;\r\n\r\n/** \r\n  * @brief  DMA2D handle Structure definition\r\n  */\r\ntypedef struct __DMA2D_HandleTypeDef\r\n{\r\n  DMA2D_TypeDef               *Instance;                                                    /*!< DMA2D register base address.               */\r\n                                                                                                                                          \r\n  DMA2D_InitTypeDef           Init;                                                         /*!< DMA2D communication parameters.            */\r\n\r\n  void                        (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d);  /*!< DMA2D transfer complete callback.          */\r\n                                                                                                                                           \r\n  void                        (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback.             */                                                                                                                                             \r\n\r\n  DMA2D_LayerCfgTypeDef       LayerCfg[MAX_DMA2D_LAYER];                                    /*!< DMA2D Layers parameters           */  \r\n\r\n  HAL_LockTypeDef             Lock;                                                         /*!< DMA2D lock.                                */  \r\n                                                                                                                                           \r\n  __IO HAL_DMA2D_StateTypeDef State;                                                        /*!< DMA2D transfer state.                      */\r\n                                                                                                                                           \r\n  __IO uint32_t               ErrorCode;                                                    /*!< DMA2D error code.                          */  \r\n} DMA2D_HandleTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup DMA2D_Error_Code DMA2D Error Code\r\n  * @{\r\n  */\r\n#define HAL_DMA2D_ERROR_NONE        ((uint32_t)0x00000000U)  /*!< No error             */\r\n#define HAL_DMA2D_ERROR_TE          ((uint32_t)0x00000001U)  /*!< Transfer error       */\r\n#define HAL_DMA2D_ERROR_CE          ((uint32_t)0x00000002U)  /*!< Configuration error  */\r\n#define HAL_DMA2D_ERROR_CAE         ((uint32_t)0x00000004U)  /*!< CLUT access error    */\r\n#define HAL_DMA2D_ERROR_TIMEOUT     ((uint32_t)0x00000020U)  /*!< Timeout error        */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DMA2D_Mode DMA2D Mode \r\n  * @{\r\n  */\r\n#define DMA2D_M2M                   ((uint32_t)0x00000000U)  /*!< DMA2D memory to memory transfer mode */\r\n#define DMA2D_M2M_PFC               DMA2D_CR_MODE_0          /*!< DMA2D memory to memory with pixel format conversion transfer mode */\r\n#define DMA2D_M2M_BLEND             DMA2D_CR_MODE_1          /*!< DMA2D memory to memory with blending transfer mode */\r\n#define DMA2D_R2M                   DMA2D_CR_MODE            /*!< DMA2D register to memory transfer mode */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode \r\n  * @{\r\n  */\r\n#define DMA2D_OUTPUT_ARGB8888       ((uint32_t)0x00000000U)               /*!< ARGB8888 DMA2D color mode */\r\n#define DMA2D_OUTPUT_RGB888         DMA2D_OPFCCR_CM_0                     /*!< RGB888 DMA2D color mode   */\r\n#define DMA2D_OUTPUT_RGB565         DMA2D_OPFCCR_CM_1                     /*!< RGB565 DMA2D color mode   */\r\n#define DMA2D_OUTPUT_ARGB1555       (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */\r\n#define DMA2D_OUTPUT_ARGB4444       DMA2D_OPFCCR_CM_2                     /*!< ARGB4444 DMA2D color mode */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode\r\n  * @{\r\n  */\r\n#define DMA2D_INPUT_ARGB8888        ((uint32_t)0x00000000U)  /*!< ARGB8888 color mode */\r\n#define DMA2D_INPUT_RGB888          ((uint32_t)0x00000001U)  /*!< RGB888 color mode   */\r\n#define DMA2D_INPUT_RGB565          ((uint32_t)0x00000002U)  /*!< RGB565 color mode   */\r\n#define DMA2D_INPUT_ARGB1555        ((uint32_t)0x00000003U)  /*!< ARGB1555 color mode */\r\n#define DMA2D_INPUT_ARGB4444        ((uint32_t)0x00000004U)  /*!< ARGB4444 color mode */\r\n#define DMA2D_INPUT_L8              ((uint32_t)0x00000005U)  /*!< L8 color mode       */\r\n#define DMA2D_INPUT_AL44            ((uint32_t)0x00000006U)  /*!< AL44 color mode     */\r\n#define DMA2D_INPUT_AL88            ((uint32_t)0x00000007U)  /*!< AL88 color mode     */\r\n#define DMA2D_INPUT_L4              ((uint32_t)0x00000008U)  /*!< L4 color mode       */\r\n#define DMA2D_INPUT_A8              ((uint32_t)0x00000009U)  /*!< A8 color mode       */\r\n#define DMA2D_INPUT_A4              ((uint32_t)0x0000000AU)  /*!< A4 color mode       */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode\r\n  * @{\r\n  */\r\n#define DMA2D_NO_MODIF_ALPHA        ((uint32_t)0x00000000U)  /*!< No modification of the alpha channel value */\r\n#define DMA2D_REPLACE_ALPHA         ((uint32_t)0x00000001U)  /*!< Replace original alpha channel value by programmed alpha value */\r\n#define DMA2D_COMBINE_ALPHA         ((uint32_t)0x00000002U)  /*!< Replace original alpha channel value by programmed alpha value\r\n                                                                with original alpha channel value                              */\r\n/**\r\n  * @}\r\n  */    \r\n\r\n#if defined (DMA2D_FGPFCCR_AI) && defined (DMA2D_BGPFCCR_AI)    \r\n/** @defgroup DMA2D_Alpha_Inverted DMA2D ALPHA Inversion\r\n  * @{\r\n  */\r\n#define DMA2D_REGULAR_ALPHA         ((uint32_t)0x00000000U)  /*!< No modification of the alpha channel value */\r\n#define DMA2D_INVERTED_ALPHA        ((uint32_t)0x00000001U)  /*!< Invert the alpha channel value */                                  \r\n/**\r\n  * @}\r\n  */\r\n#endif /* (DMA2D_FGPFCCR_AI) && (DMA2D_BGPFCCR_AI)  */\r\n\r\n#if defined (DMA2D_FGPFCCR_RBS) && defined (DMA2D_BGPFCCR_RBS)  \r\n/** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap\r\n  * @{\r\n  */\r\n#define DMA2D_RB_REGULAR            ((uint32_t)0x00000000U)  /*!< Select regular mode (RGB or ARGB) */\r\n#define DMA2D_RB_SWAP               ((uint32_t)0x00000001U)  /*!< Select swap mode (BGR or ABGR) */\r\n/**\r\n  * @}\r\n  */ \r\n#endif /* (DMA2D_FGPFCCR_RBS) && (DMA2D_BGPFCCR_RBS)  */     \r\n\r\n/** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode\r\n  * @{\r\n  */\r\n#define DMA2D_CCM_ARGB8888          ((uint32_t)0x00000000U)  /*!< ARGB8888 DMA2D CLUT color mode */\r\n#define DMA2D_CCM_RGB888            ((uint32_t)0x00000001U)  /*!< RGB888 DMA2D CLUT color mode   */\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup DMA2D_Interrupts DMA2D Interrupts \r\n  * @{\r\n  */\r\n#define DMA2D_IT_CE                 DMA2D_CR_CEIE            /*!< Configuration Error Interrupt */\r\n#define DMA2D_IT_CTC                DMA2D_CR_CTCIE           /*!< CLUT Transfer Complete Interrupt */\r\n#define DMA2D_IT_CAE                DMA2D_CR_CAEIE           /*!< CLUT Access Error Interrupt */\r\n#define DMA2D_IT_TW                 DMA2D_CR_TWIE            /*!< Transfer Watermark Interrupt */\r\n#define DMA2D_IT_TC                 DMA2D_CR_TCIE            /*!< Transfer Complete Interrupt */\r\n#define DMA2D_IT_TE                 DMA2D_CR_TEIE            /*!< Transfer Error Interrupt */\r\n/**                                                         \r\n  * @}                                                      \r\n  */                                                        \r\n                                                            \r\n/** @defgroup DMA2D_Flags DMA2D Flags                       \r\n  * @{                                                      \r\n  */                                                        \r\n#define DMA2D_FLAG_CE               DMA2D_ISR_CEIF           /*!< Configuration Error Interrupt Flag */\r\n#define DMA2D_FLAG_CTC              DMA2D_ISR_CTCIF          /*!< CLUT Transfer Complete Interrupt Flag */\r\n#define DMA2D_FLAG_CAE              DMA2D_ISR_CAEIF          /*!< CLUT Access Error Interrupt Flag */\r\n#define DMA2D_FLAG_TW               DMA2D_ISR_TWIF           /*!< Transfer Watermark Interrupt Flag */\r\n#define DMA2D_FLAG_TC               DMA2D_ISR_TCIF           /*!< Transfer Complete Interrupt Flag */\r\n#define DMA2D_FLAG_TE               DMA2D_ISR_TEIF           /*!< Transfer Error Interrupt Flag */\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup DMA2D_Aliases DMA2D API Aliases\r\n  * @{\r\n  */\r\n#define HAL_DMA2D_DisableCLUT       HAL_DMA2D_CLUTLoading_Abort    /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */\r\n/**\r\n  * @}\r\n  */\r\n  \r\n  \r\n/**\r\n  * @}\r\n  */\r\n/* Exported macros ------------------------------------------------------------*/\r\n/** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief Reset DMA2D handle state\r\n  * @param  __HANDLE__ specifies the DMA2D handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)\r\n\r\n/**\r\n  * @brief  Enable the DMA2D.\r\n  * @param  __HANDLE__ DMA2D handle\r\n  * @retval None.\r\n  */\r\n#define __HAL_DMA2D_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)\r\n\r\n\r\n/* Interrupt & Flag management */\r\n/**\r\n  * @brief  Get the DMA2D pending flags.\r\n  * @param  __HANDLE__ DMA2D handle\r\n  * @param  __FLAG__ flag to check.\r\n  *          This parameter can be any combination of the following values:\r\n  *            @arg DMA2D_FLAG_CE:  Configuration error flag\r\n  *            @arg DMA2D_FLAG_CTC: CLUT transfer complete flag\r\n  *            @arg DMA2D_FLAG_CAE: CLUT access error flag\r\n  *            @arg DMA2D_FLAG_TW:  Transfer Watermark flag\r\n  *            @arg DMA2D_FLAG_TC:  Transfer complete flag\r\n  *            @arg DMA2D_FLAG_TE:  Transfer error flag   \r\n  * @retval The state of FLAG.\r\n  */\r\n#define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))\r\n\r\n/**\r\n  * @brief  Clear the DMA2D pending flags.\r\n  * @param  __HANDLE__ DMA2D handle\r\n  * @param  __FLAG__ specifies the flag to clear.\r\n  *          This parameter can be any combination of the following values:\r\n  *            @arg DMA2D_FLAG_CE:  Configuration error flag\r\n  *            @arg DMA2D_FLAG_CTC: CLUT transfer complete flag\r\n  *            @arg DMA2D_FLAG_CAE: CLUT access error flag\r\n  *            @arg DMA2D_FLAG_TW:  Transfer Watermark flag\r\n  *            @arg DMA2D_FLAG_TC:  Transfer complete flag\r\n  *            @arg DMA2D_FLAG_TE:  Transfer error flag    \r\n  * @retval None\r\n  */\r\n#define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))\r\n\r\n/**\r\n  * @brief  Enable the specified DMA2D interrupts.\r\n  * @param  __HANDLE__ DMA2D handle\r\n  * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled. \r\n  *          This parameter can be any combination of the following values:\r\n  *            @arg DMA2D_IT_CE:  Configuration error interrupt mask\r\n  *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask\r\n  *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask\r\n  *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask\r\n  *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask\r\n  *            @arg DMA2D_IT_TE:  Transfer error interrupt mask\r\n  * @retval None\r\n  */\r\n#define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disable the specified DMA2D interrupts.\r\n  * @param  __HANDLE__ DMA2D handle\r\n  * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled. \r\n  *          This parameter can be any combination of the following values:\r\n  *            @arg DMA2D_IT_CE:  Configuration error interrupt mask\r\n  *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask\r\n  *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask\r\n  *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask\r\n  *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask\r\n  *            @arg DMA2D_IT_TE:  Transfer error interrupt mask\r\n  * @retval None\r\n  */\r\n#define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Check whether the specified DMA2D interrupt source is enabled or not.\r\n  * @param  __HANDLE__ DMA2D handle\r\n  * @param  __INTERRUPT__ specifies the DMA2D interrupt source to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg DMA2D_IT_CE:  Configuration error interrupt mask\r\n  *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask\r\n  *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask\r\n  *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask\r\n  *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask\r\n  *            @arg DMA2D_IT_TE:  Transfer error interrupt mask\r\n  * @retval The state of INTERRUPT source.\r\n  */\r\n#define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))\r\n     \r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/  \r\n/** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions\r\n  * @{\r\n  */  \r\n  \r\n/* Initialization and de-initialization functions *******************************/\r\nHAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); \r\nHAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);\r\nvoid              HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);\r\nvoid              HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions\r\n  * @{\r\n  */\r\n  \r\n/* IO operation functions *******************************************************/\r\nHAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);\r\nHAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width,  uint32_t Height);\r\nHAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);\r\nHAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);\r\nHAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);\r\nHAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);\r\nHAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);\r\nHAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);\r\nvoid              HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);\r\nvoid              HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d);\r\nvoid              HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions\r\n  * @{\r\n  */\r\n\r\n/* Peripheral Control functions *************************************************/\r\nHAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);\r\nHAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d);\r\nHAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d);\r\nHAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions\r\n  * @{\r\n  */\r\n\r\n/* Peripheral State functions ***************************************************/\r\nHAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);\r\nuint32_t               HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private constants ---------------------------------------------------------*/  \r\n  \r\n/** @addtogroup DMA2D_Private_Constants DMA2D Private Constants\r\n  * @{\r\n  */                         \r\n\r\n/** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark \r\n  * @{\r\n  */\r\n#define DMA2D_LINE_WATERMARK_MAX            DMA2D_LWR_LW       /*!< DMA2D maximum line watermark */\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup DMA2D_Color_Value DMA2D Color Value\r\n  * @{\r\n  */\r\n#define DMA2D_COLOR_VALUE                 ((uint32_t)0x000000FFU)  /*!< Color value mask */\r\n/**\r\n  * @}\r\n  */      \r\n\r\n/** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers\r\n  * @{\r\n  */  \r\n#define DMA2D_MAX_LAYER         2         /*!< DMA2D maximum number of layers */  \r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/** @defgroup DMA2D_Offset DMA2D Offset \r\n  * @{\r\n  */\r\n#define DMA2D_OFFSET                DMA2D_FGOR_LO            /*!< Line Offset */\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/** @defgroup DMA2D_Size DMA2D Size \r\n  * @{\r\n  */\r\n#define DMA2D_PIXEL                 (DMA2D_NLR_PL >> 16U)    /*!< DMA2D number of pixels per line */\r\n#define DMA2D_LINE                  DMA2D_NLR_NL             /*!< DMA2D number of lines           */\r\n/**\r\n  * @}\r\n  */    \r\n  \r\n/** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size\r\n  * @{\r\n  */\r\n#define DMA2D_CLUT_SIZE             (DMA2D_FGPFCCR_CS >> 8)  /*!< DMA2D CLUT size */\r\n/**\r\n  * @}\r\n  */   \r\n    \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup DMA2D_Private_Macros DMA2D Private Macros\r\n  * @{\r\n  */\r\n#define IS_DMA2D_LAYER(LAYER)                 ((LAYER) <= DMA2D_MAX_LAYER)\r\n#define IS_DMA2D_MODE(MODE)                   (((MODE) == DMA2D_M2M)       || ((MODE) == DMA2D_M2M_PFC) || \\\r\n                                               ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))\r\n#define IS_DMA2D_CMODE(MODE_ARGB)             (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888)   || \\\r\n                                               ((MODE_ARGB) == DMA2D_OUTPUT_RGB565)   || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \\\r\n                                               ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))\r\n#define IS_DMA2D_COLOR(COLOR)                 ((COLOR) <= DMA2D_COLOR_VALUE)\r\n#define IS_DMA2D_LINE(LINE)                   ((LINE) <= DMA2D_LINE)\r\n#define IS_DMA2D_PIXEL(PIXEL)                 ((PIXEL) <= DMA2D_PIXEL)\r\n#define IS_DMA2D_OFFSET(OOFFSET)              ((OOFFSET) <= DMA2D_OFFSET)\r\n#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM)   (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888)   || \\\r\n                                               ((INPUT_CM) == DMA2D_INPUT_RGB565)   || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \\\r\n                                               ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8)       || \\\r\n                                               ((INPUT_CM) == DMA2D_INPUT_AL44)     || ((INPUT_CM) == DMA2D_INPUT_AL88)     || \\\r\n                                               ((INPUT_CM) == DMA2D_INPUT_L4)       || ((INPUT_CM) == DMA2D_INPUT_A8)       || \\\r\n                                               ((INPUT_CM) == DMA2D_INPUT_A4))\r\n#define IS_DMA2D_ALPHA_MODE(AlphaMode)        (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \\\r\n                                               ((AlphaMode) == DMA2D_REPLACE_ALPHA)  || \\\r\n                                               ((AlphaMode) == DMA2D_COMBINE_ALPHA))\r\n\r\n#define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \\\r\n                                                 ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA))\r\n\r\n#define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \\\r\n                                   ((RB_Swap) == DMA2D_RB_SWAP))\r\n\r\n#define IS_DMA2D_CLUT_CM(CLUT_CM)             (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))\r\n#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE)         ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)\r\n#define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)\r\n#define IS_DMA2D_IT(IT)                       (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \\\r\n                                               ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \\\r\n                                               ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))\r\n#define IS_DMA2D_GET_FLAG(FLAG)               (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \\\r\n                                               ((FLAG) == DMA2D_FLAG_TW)   || ((FLAG) == DMA2D_FLAG_TC)  || \\\r\n                                               ((FLAG) == DMA2D_FLAG_TE)   || ((FLAG) == DMA2D_FLAG_CE))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* DMA2D */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_DMA2D_H */\r\n \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_dma_ex.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of DMA HAL extension module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_DMA_EX_H\r\n#define __STM32F7xx_HAL_DMA_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup DMAEx\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup DMAEx_Exported_Types DMAEx Exported Types\r\n  * @brief DMAEx Exported types\r\n  * @{\r\n  */\r\n   \r\n/** \r\n  * @brief  HAL DMA Memory definition  \r\n  */ \r\ntypedef enum\r\n{\r\n  MEMORY0      = 0x00U,    /*!< Memory 0     */\r\n  MEMORY1      = 0x01U,    /*!< Memory 1     */\r\n\r\n}HAL_DMA_MemoryTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup DMA_Exported_Constants DMA Exported Constants\r\n  * @brief    DMA Exported constants \r\n  * @{\r\n  */\r\n\r\n/** @defgroup DMAEx_Channel_selection DMA Channel selection\r\n  * @brief    DMAEx channel selection \r\n  * @{\r\n  */ \r\n#define DMA_CHANNEL_0                     0x00000000U  /*!< DMA Channel 0 */\r\n#define DMA_CHANNEL_1                     0x02000000U  /*!< DMA Channel 1 */\r\n#define DMA_CHANNEL_2                     0x04000000U  /*!< DMA Channel 2 */\r\n#define DMA_CHANNEL_3                     0x06000000U  /*!< DMA Channel 3 */\r\n#define DMA_CHANNEL_4                     0x08000000U  /*!< DMA Channel 4 */\r\n#define DMA_CHANNEL_5                     0x0A000000U  /*!< DMA Channel 5 */\r\n#define DMA_CHANNEL_6                     0x0C000000U  /*!< DMA Channel 6 */\r\n#define DMA_CHANNEL_7                     0x0E000000U  /*!< DMA Channel 7 */\r\n#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\\\r\n    defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\\\r\n    defined (STM32F779xx) || defined (STM32F730xx)\r\n#define DMA_CHANNEL_8                     0x10000000U  /*!< DMA Channel 8 */\r\n#define DMA_CHANNEL_9                     0x12000000U  /*!< DMA Channel 9 */\r\n#define DMA_CHANNEL_10                    0x14000000U  /*!< DMA Channel 10*/\r\n#define DMA_CHANNEL_11                    0x16000000U  /*!< DMA Channel 11*/\r\n#define DMA_CHANNEL_12                    0x18000000U  /*!< DMA Channel 12*/\r\n#define DMA_CHANNEL_13                    0x1A000000U  /*!< DMA Channel 13*/\r\n#define DMA_CHANNEL_14                    0x1C000000U  /*!< DMA Channel 14*/\r\n#define DMA_CHANNEL_15                    0x1E000000U  /*!< DMA Channel 15*/\r\n#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||\r\n          STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */  \r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions\r\n  * @brief   DMAEx Exported functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions\r\n  * @brief   Extended features functions\r\n  * @{\r\n  */\r\n\r\n/* IO operation functions *******************************************************/\r\nHAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);\r\nHAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);\r\nHAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);\r\n\r\n/**\r\n  * @}\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup DMAEx_Private_Macros DMA Private Macros\r\n  * @brief    DMAEx private macros \r\n  * @{\r\n  */\r\n#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\\\r\n    defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\\\r\n    defined (STM32F779xx) || defined (STM32F730xx)\r\n#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0)  || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_1)  || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_2)  || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_3)  || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_4)  || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_5)  || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_6)  || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_7)  || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_8)  || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_9)  || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_10) || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_11) || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_12) || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_13) || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_14) || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_15)) \r\n#else\r\n#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_1) || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_2) || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_3) || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_4) || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_5) || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_6) || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_7))\r\n#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||\r\n          STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx*/\r\n/**\r\n  * @}\r\n  */  \r\n         \r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup DMAEx_Private_Functions DMAEx Private Functions\r\n  * @brief DMAEx Private functions\r\n  * @{\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_DMA_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_eth.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of ETH HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_ETH_H\r\n#define __STM32F7xx_HAL_ETH_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n#if defined (ETH)\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup ETH\r\n  * @{\r\n  */ \r\n  \r\n/** @addtogroup ETH_Private_Macros\r\n  * @{\r\n  */\r\n#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)\r\n#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \\\r\n                                     ((CMD) == ETH_AUTONEGOTIATION_DISABLE))\r\n#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \\\r\n                             ((SPEED) == ETH_SPEED_100M))\r\n#define IS_ETH_DUPLEX_MODE(MODE)  (((MODE) == ETH_MODE_FULLDUPLEX) || \\\r\n                                  ((MODE) == ETH_MODE_HALFDUPLEX))\r\n#define IS_ETH_RX_MODE(MODE)    (((MODE) == ETH_RXPOLLING_MODE) || \\\r\n                                 ((MODE) == ETH_RXINTERRUPT_MODE)) \r\n#define IS_ETH_CHECKSUM_MODE(MODE)    (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \\\r\n                                      ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))\r\n#define IS_ETH_MEDIA_INTERFACE(MODE)         (((MODE) == ETH_MEDIA_INTERFACE_MII) || \\\r\n                                              ((MODE) == ETH_MEDIA_INTERFACE_RMII))\r\n#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \\\r\n                              ((CMD) == ETH_WATCHDOG_DISABLE))\r\n#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \\\r\n                            ((CMD) == ETH_JABBER_DISABLE))\r\n#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \\\r\n                                     ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \\\r\n                                     ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \\\r\n                                     ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \\\r\n                                     ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \\\r\n                                     ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \\\r\n                                     ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \\\r\n                                     ((GAP) == ETH_INTERFRAMEGAP_40BIT))\r\n#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \\\r\n                                   ((CMD) == ETH_CARRIERSENCE_DISABLE))\r\n#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \\\r\n                                 ((CMD) == ETH_RECEIVEOWN_DISABLE))\r\n#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \\\r\n                                   ((CMD) == ETH_LOOPBACKMODE_DISABLE))\r\n#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \\\r\n                                      ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))\r\n#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \\\r\n                                        ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))\r\n#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \\\r\n                                            ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))\r\n#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \\\r\n                                     ((LIMIT) == ETH_BACKOFFLIMIT_8) || \\\r\n                                     ((LIMIT) == ETH_BACKOFFLIMIT_4) || \\\r\n                                     ((LIMIT) == ETH_BACKOFFLIMIT_1))\r\n#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \\\r\n                                    ((CMD) == ETH_DEFFERRALCHECK_DISABLE))\r\n#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \\\r\n                                 ((CMD) == ETH_RECEIVEAll_DISABLE))\r\n#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \\\r\n                                        ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \\\r\n                                        ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))\r\n#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \\\r\n                                     ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \\\r\n                                     ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))\r\n#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \\\r\n                                                ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))\r\n#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \\\r\n                                                ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))\r\n#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \\\r\n                                      ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))\r\n#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \\\r\n                                                ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \\\r\n                                                ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \\\r\n                                                ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))\r\n#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \\\r\n                                              ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \\\r\n                                              ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))\r\n#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)\r\n#define IS_ETH_ZEROQUANTA_PAUSE(CMD)   (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \\\r\n                                        ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))\r\n#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \\\r\n                                               ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \\\r\n                                               ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \\\r\n                                               ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))\r\n#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \\\r\n                                                ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))\r\n#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \\\r\n                                         ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))\r\n#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \\\r\n                                          ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))\r\n#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \\\r\n                                                ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))\r\n#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)\r\n#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \\\r\n                                         ((ADDRESS) == ETH_MAC_ADDRESS1) || \\\r\n                                         ((ADDRESS) == ETH_MAC_ADDRESS2) || \\\r\n                                         ((ADDRESS) == ETH_MAC_ADDRESS3))\r\n#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \\\r\n                                        ((ADDRESS) == ETH_MAC_ADDRESS2) || \\\r\n                                        ((ADDRESS) == ETH_MAC_ADDRESS3))\r\n#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \\\r\n                                           ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))\r\n#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \\\r\n                                       ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \\\r\n                                       ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \\\r\n                                       ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \\\r\n                                       ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \\\r\n                                       ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))\r\n#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \\\r\n                                               ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))\r\n#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \\\r\n                                           ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))\r\n#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \\\r\n                                         ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))\r\n#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \\\r\n                                            ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))\r\n#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \\\r\n                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \\\r\n                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \\\r\n                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \\\r\n                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \\\r\n                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \\\r\n                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \\\r\n                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))\r\n#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \\\r\n                                          ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))\r\n#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \\\r\n                                                    ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))\r\n#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \\\r\n                                                     ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \\\r\n                                                     ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \\\r\n                                                     ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))\r\n#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \\\r\n                                          ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))\r\n#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \\\r\n                                           ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))\r\n#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \\\r\n                                 ((CMD) == ETH_FIXEDBURST_DISABLE))\r\n#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \\\r\n                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \\\r\n                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \\\r\n                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \\\r\n                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \\\r\n                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \\\r\n                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \\\r\n                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \\\r\n                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \\\r\n                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \\\r\n                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \\\r\n                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))\r\n#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \\\r\n                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \\\r\n                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \\\r\n                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \\\r\n                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \\\r\n                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \\\r\n                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \\\r\n                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \\\r\n                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \\\r\n                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \\\r\n                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \\\r\n                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))\r\n#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)\r\n#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \\\r\n                                                       ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \\\r\n                                                       ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \\\r\n                                                       ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \\\r\n                                                       ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))\r\n#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_IC) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_LS) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_FS) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_DC) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_DP) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_TTSE) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_TER) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_TCH) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_TTSS) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_IHE) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_ES) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_JT) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_FF) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_PCE) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_LCA) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_NC) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_LCO) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_EC) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_VF) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_CC) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_ED) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_UF) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_DB))\r\n#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \\\r\n                                            ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))\r\n#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \\\r\n                                              ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \\\r\n                                              ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \\\r\n                                              ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))\r\n#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)\r\n#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \\\r\n                                         ((FLAG) == ETH_DMARXDESC_AFM) || \\\r\n                                         ((FLAG) == ETH_DMARXDESC_ES) || \\\r\n                                         ((FLAG) == ETH_DMARXDESC_DE) || \\\r\n                                         ((FLAG) == ETH_DMARXDESC_SAF) || \\\r\n                                         ((FLAG) == ETH_DMARXDESC_LE) || \\\r\n                                         ((FLAG) == ETH_DMARXDESC_OE) || \\\r\n                                         ((FLAG) == ETH_DMARXDESC_VLAN) || \\\r\n                                         ((FLAG) == ETH_DMARXDESC_FS) || \\\r\n                                         ((FLAG) == ETH_DMARXDESC_LS) || \\\r\n                                         ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \\\r\n                                         ((FLAG) == ETH_DMARXDESC_LC) || \\\r\n                                         ((FLAG) == ETH_DMARXDESC_FT) || \\\r\n                                         ((FLAG) == ETH_DMARXDESC_RWT) || \\\r\n                                         ((FLAG) == ETH_DMARXDESC_RE) || \\\r\n                                         ((FLAG) == ETH_DMARXDESC_DBE) || \\\r\n                                         ((FLAG) == ETH_DMARXDESC_CE) || \\\r\n                                         ((FLAG) == ETH_DMARXDESC_MAMPCE))\r\n#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \\\r\n                                          ((BUFFER) == ETH_DMARXDESC_BUFFER2))\r\n#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \\\r\n                                   ((FLAG) == ETH_PMT_FLAG_MPR))\r\n#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00)) \r\n#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \\\r\n                                   ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \\\r\n                                   ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \\\r\n                                   ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \\\r\n                                   ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \\\r\n                                   ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \\\r\n                                   ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \\\r\n                                   ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \\\r\n                                   ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \\\r\n                                   ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \\\r\n                                   ((FLAG) == ETH_DMA_FLAG_T))\r\n#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF1) == 0x00) && ((IT) != 0x00))\r\n#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \\\r\n                               ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \\\r\n                               ((IT) == ETH_MAC_IT_PMT))\r\n#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \\\r\n                                   ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \\\r\n                                   ((FLAG) == ETH_MAC_FLAG_PMT))\r\n#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))\r\n#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \\\r\n                               ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \\\r\n                               ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \\\r\n                               ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \\\r\n                               ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \\\r\n                               ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \\\r\n                               ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \\\r\n                               ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \\\r\n                               ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))\r\n#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \\\r\n                                           ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))\r\n#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \\\r\n                           ((IT) != 0x00))\r\n#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \\\r\n                               ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \\\r\n                               ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))\r\n#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \\\r\n                                                ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup ETH_Private_Defines\r\n  * @{\r\n  */\r\n/* Delay to wait when writing to some Ethernet registers */\r\n#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001U)\r\n\r\n/* Ethernet Errors */\r\n#define  ETH_SUCCESS            ((uint32_t)0U)\r\n#define  ETH_ERROR              ((uint32_t)1U)\r\n\r\n/* Ethernet DMA Tx descriptors Collision Count Shift */\r\n#define  ETH_DMATXDESC_COLLISION_COUNTSHIFT         ((uint32_t)3U)\r\n\r\n/* Ethernet DMA Tx descriptors Buffer2 Size Shift */\r\n#define  ETH_DMATXDESC_BUFFER2_SIZESHIFT           ((uint32_t)16U)\r\n\r\n/* Ethernet DMA Rx descriptors Frame Length Shift */\r\n#define  ETH_DMARXDESC_FRAME_LENGTHSHIFT           ((uint32_t)16U)\r\n\r\n/* Ethernet DMA Rx descriptors Buffer2 Size Shift */\r\n#define  ETH_DMARXDESC_BUFFER2_SIZESHIFT           ((uint32_t)16U)\r\n\r\n/* Ethernet DMA Rx descriptors Frame length Shift */\r\n#define  ETH_DMARXDESC_FRAMELENGTHSHIFT            ((uint32_t)16)\r\n\r\n/* Ethernet MAC address offsets */\r\n#define ETH_MAC_ADDR_HBASE    (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40U)  /* Ethernet MAC address high offset */\r\n#define ETH_MAC_ADDR_LBASE    (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44U)  /* Ethernet MAC address low offset */\r\n\r\n/* Ethernet MACMIIAR register Mask */\r\n#define ETH_MACMIIAR_CR_MASK    ((uint32_t)0xFFFFFFE3U)\r\n\r\n/* Ethernet MACCR register Mask */\r\n#define ETH_MACCR_CLEAR_MASK    ((uint32_t)0xFF20810FU)  \r\n\r\n/* Ethernet MACFCR register Mask */\r\n#define ETH_MACFCR_CLEAR_MASK   ((uint32_t)0x0000FF41U)\r\n\r\n/* Ethernet DMAOMR register Mask */\r\n#define ETH_DMAOMR_CLEAR_MASK   ((uint32_t)0xF8DE3F23U)\r\n\r\n/* Ethernet Remote Wake-up frame register length */\r\n#define ETH_WAKEUP_REGISTER_LENGTH      8U\r\n\r\n/* Ethernet Missed frames counter Shift */\r\n#define  ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT     17U\r\n /**\r\n  * @}\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/ \r\n/** @defgroup ETH_Exported_Types ETH Exported Types\r\n  * @{\r\n  */\r\n\r\n/** \r\n  * @brief  HAL State structures definition  \r\n  */ \r\ntypedef enum\r\n{\r\n  HAL_ETH_STATE_RESET             = 0x00U,    /*!< Peripheral not yet Initialized or disabled         */\r\n  HAL_ETH_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use           */\r\n  HAL_ETH_STATE_BUSY              = 0x02U,    /*!< an internal process is ongoing                     */\r\n  HAL_ETH_STATE_BUSY_TX           = 0x12U,    /*!< Data Transmission process is ongoing               */\r\n  HAL_ETH_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing                  */\r\n  HAL_ETH_STATE_BUSY_TX_RX        = 0x32U,    /*!< Data Transmission and Reception process is ongoing */\r\n  HAL_ETH_STATE_BUSY_WR           = 0x42U,    /*!< Write process is ongoing                           */\r\n  HAL_ETH_STATE_BUSY_RD           = 0x82U,    /*!< Read process is ongoing                            */\r\n  HAL_ETH_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                                      */\r\n  HAL_ETH_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                       */\r\n}HAL_ETH_StateTypeDef;\r\n\r\n/** \r\n  * @brief  ETH Init Structure definition  \r\n  */\r\n\r\ntypedef struct\r\n{\r\n  uint32_t             AutoNegotiation;           /*!< Selects or not the AutoNegotiation mode for the external PHY\r\n                                                           The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)\r\n                                                           and the mode (half/full-duplex).\r\n                                                           This parameter can be a value of @ref ETH_AutoNegotiation */\r\n\r\n  uint32_t             Speed;                     /*!< Sets the Ethernet speed: 10/100 Mbps.\r\n                                                           This parameter can be a value of @ref ETH_Speed */\r\n\r\n  uint32_t             DuplexMode;                /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode\r\n                                                           This parameter can be a value of @ref ETH_Duplex_Mode */\r\n  \r\n  uint16_t             PhyAddress;                /*!< Ethernet PHY address.\r\n                                                           This parameter must be a number between Min_Data = 0 and Max_Data = 32 */\r\n  \r\n  uint8_t             *MACAddr;                   /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */\r\n  \r\n  uint32_t             RxMode;                    /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.\r\n                                                           This parameter can be a value of @ref ETH_Rx_Mode */\r\n  \r\n  uint32_t             ChecksumMode;              /*!< Selects if the checksum is check by hardware or by software. \r\n                                                         This parameter can be a value of @ref ETH_Checksum_Mode */\r\n  \r\n  uint32_t             MediaInterface    ;               /*!< Selects the media-independent interface or the reduced media-independent interface. \r\n                                                         This parameter can be a value of @ref ETH_Media_Interface */\r\n\r\n} ETH_InitTypeDef;\r\n\r\n\r\n /** \r\n  * @brief  ETH MAC Configuration Structure definition  \r\n  */\r\n\r\ntypedef struct\r\n{\r\n  uint32_t             Watchdog;                  /*!< Selects or not the Watchdog timer\r\n                                                           When enabled, the MAC allows no more then 2048 bytes to be received.\r\n                                                           When disabled, the MAC can receive up to 16384 bytes.\r\n                                                           This parameter can be a value of @ref ETH_Watchdog */  \r\n\r\n  uint32_t             Jabber;                    /*!< Selects or not Jabber timer\r\n                                                           When enabled, the MAC allows no more then 2048 bytes to be sent.\r\n                                                           When disabled, the MAC can send up to 16384 bytes.\r\n                                                           This parameter can be a value of @ref ETH_Jabber */\r\n\r\n  uint32_t             InterFrameGap;             /*!< Selects the minimum IFG between frames during transmission.\r\n                                                           This parameter can be a value of @ref ETH_Inter_Frame_Gap */   \r\n\r\n  uint32_t             CarrierSense;              /*!< Selects or not the Carrier Sense.\r\n                                                           This parameter can be a value of @ref ETH_Carrier_Sense */\r\n\r\n  uint32_t             ReceiveOwn;                /*!< Selects or not the ReceiveOwn,\r\n                                                           ReceiveOwn allows the reception of frames when the TX_EN signal is asserted\r\n                                                           in Half-Duplex mode.\r\n                                                           This parameter can be a value of @ref ETH_Receive_Own */  \r\n\r\n  uint32_t             LoopbackMode;              /*!< Selects or not the internal MAC MII Loopback mode.\r\n                                                           This parameter can be a value of @ref ETH_Loop_Back_Mode */  \r\n\r\n  uint32_t             ChecksumOffload;           /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.\r\n                                                           This parameter can be a value of @ref ETH_Checksum_Offload */    \r\n\r\n  uint32_t             RetryTransmission;         /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,\r\n                                                           when a collision occurs (Half-Duplex mode).\r\n                                                           This parameter can be a value of @ref ETH_Retry_Transmission */\r\n\r\n  uint32_t             AutomaticPadCRCStrip;      /*!< Selects or not the Automatic MAC Pad/CRC Stripping.\r\n                                                           This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ \r\n\r\n  uint32_t             BackOffLimit;              /*!< Selects the BackOff limit value.\r\n                                                           This parameter can be a value of @ref ETH_Back_Off_Limit */\r\n\r\n  uint32_t             DeferralCheck;             /*!< Selects or not the deferral check function (Half-Duplex mode).\r\n                                                           This parameter can be a value of @ref ETH_Deferral_Check */                                                                                                        \r\n\r\n  uint32_t             ReceiveAll;                /*!< Selects or not all frames reception by the MAC (No filtering).\r\n                                                           This parameter can be a value of @ref ETH_Receive_All */   \r\n\r\n  uint32_t             SourceAddrFilter;          /*!< Selects the Source Address Filter mode.                                                           \r\n                                                           This parameter can be a value of @ref ETH_Source_Addr_Filter */                  \r\n\r\n  uint32_t             PassControlFrames;         /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)                                                          \r\n                                                           This parameter can be a value of @ref ETH_Pass_Control_Frames */ \r\n\r\n  uint32_t             BroadcastFramesReception;  /*!< Selects or not the reception of Broadcast Frames.\r\n                                                           This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */\r\n\r\n  uint32_t             DestinationAddrFilter;     /*!< Sets the destination filter mode for both unicast and multicast frames.\r\n                                                           This parameter can be a value of @ref ETH_Destination_Addr_Filter */ \r\n\r\n  uint32_t             PromiscuousMode;           /*!< Selects or not the Promiscuous Mode\r\n                                                           This parameter can be a value of @ref ETH_Promiscuous_Mode */\r\n\r\n  uint32_t             MulticastFramesFilter;     /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.\r\n                                                           This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ \r\n\r\n  uint32_t             UnicastFramesFilter;       /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.\r\n                                                           This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ \r\n\r\n  uint32_t             HashTableHigh;             /*!< This field holds the higher 32 bits of Hash table.\r\n                                                           This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */\r\n\r\n  uint32_t             HashTableLow;              /*!< This field holds the lower 32 bits of Hash table.\r\n                                                           This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF  */    \r\n\r\n  uint32_t             PauseTime;                 /*!< This field holds the value to be used in the Pause Time field in the transmit control frame. \r\n                                                           This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */\r\n\r\n  uint32_t             ZeroQuantaPause;           /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.\r\n                                                           This parameter can be a value of @ref ETH_Zero_Quanta_Pause */  \r\n\r\n  uint32_t             PauseLowThreshold;         /*!< This field configures the threshold of the PAUSE to be checked for\r\n                                                           automatic retransmission of PAUSE Frame.\r\n                                                           This parameter can be a value of @ref ETH_Pause_Low_Threshold */\r\n                                                           \r\n  uint32_t             UnicastPauseFrameDetect;   /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0\r\n                                                           unicast address and unique multicast address).\r\n                                                           This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */  \r\n\r\n  uint32_t             ReceiveFlowControl;        /*!< Enables or disables the MAC to decode the received Pause frame and\r\n                                                           disable its transmitter for a specified time (Pause Time)\r\n                                                           This parameter can be a value of @ref ETH_Receive_Flow_Control */\r\n\r\n  uint32_t             TransmitFlowControl;       /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)\r\n                                                           or the MAC back-pressure operation (Half-Duplex mode)\r\n                                                           This parameter can be a value of @ref ETH_Transmit_Flow_Control */     \r\n\r\n  uint32_t             VLANTagComparison;         /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for\r\n                                                           comparison and filtering.\r\n                                                           This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ \r\n\r\n  uint32_t             VLANTagIdentifier;         /*!< Holds the VLAN tag identifier for receive frames */\r\n\r\n} ETH_MACInitTypeDef;\r\n\r\n\r\n/** \r\n  * @brief  ETH DMA Configuration Structure definition  \r\n  */\r\n\r\ntypedef struct\r\n{\r\n uint32_t              DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.\r\n                                                             This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ \r\n\r\n  uint32_t             ReceiveStoreForward;         /*!< Enables or disables the Receive store and forward mode.\r\n                                                             This parameter can be a value of @ref ETH_Receive_Store_Forward */ \r\n\r\n  uint32_t             FlushReceivedFrame;          /*!< Enables or disables the flushing of received frames.\r\n                                                             This parameter can be a value of @ref ETH_Flush_Received_Frame */ \r\n\r\n  uint32_t             TransmitStoreForward;        /*!< Enables or disables Transmit store and forward mode.\r\n                                                             This parameter can be a value of @ref ETH_Transmit_Store_Forward */ \r\n\r\n  uint32_t             TransmitThresholdControl;    /*!< Selects or not the Transmit Threshold Control.\r\n                                                             This parameter can be a value of @ref ETH_Transmit_Threshold_Control */\r\n\r\n  uint32_t             ForwardErrorFrames;          /*!< Selects or not the forward to the DMA of erroneous frames.\r\n                                                             This parameter can be a value of @ref ETH_Forward_Error_Frames */\r\n\r\n  uint32_t             ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error\r\n                                                             and length less than 64 bytes) including pad-bytes and CRC)\r\n                                                             This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */\r\n\r\n  uint32_t             ReceiveThresholdControl;     /*!< Selects the threshold level of the Receive FIFO.\r\n                                                             This parameter can be a value of @ref ETH_Receive_Threshold_Control */\r\n\r\n  uint32_t             SecondFrameOperate;          /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second\r\n                                                             frame of Transmit data even before obtaining the status for the first frame.\r\n                                                             This parameter can be a value of @ref ETH_Second_Frame_Operate */\r\n\r\n  uint32_t             AddressAlignedBeats;         /*!< Enables or disables the Address Aligned Beats.\r\n                                                             This parameter can be a value of @ref ETH_Address_Aligned_Beats */\r\n\r\n  uint32_t             FixedBurst;                  /*!< Enables or disables the AHB Master interface fixed burst transfers.\r\n                                                             This parameter can be a value of @ref ETH_Fixed_Burst */\r\n                       \r\n  uint32_t             RxDMABurstLength;            /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.\r\n                                                             This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ \r\n\r\n  uint32_t             TxDMABurstLength;            /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.\r\n                                                             This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */\r\n  \r\n  uint32_t             EnhancedDescriptorFormat;    /*!< Enables the enhanced descriptor format.\r\n                                                             This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */\r\n\r\n  uint32_t             DescriptorSkipLength;        /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)\r\n                                                             This parameter must be a number between Min_Data = 0 and Max_Data = 32 */                                                             \r\n\r\n  uint32_t             DMAArbitration;              /*!< Selects the DMA Tx/Rx arbitration.\r\n                                                             This parameter can be a value of @ref ETH_DMA_Arbitration */  \r\n} ETH_DMAInitTypeDef;\r\n\r\n\r\n/** \r\n  * @brief  ETH DMA Descriptors data structure definition\r\n  */ \r\n\r\ntypedef struct  \r\n{\r\n  __IO uint32_t   Status;           /*!< Status */\r\n  \r\n  uint32_t   ControlBufferSize;     /*!< Control and Buffer1, Buffer2 lengths */\r\n  \r\n  uint32_t   Buffer1Addr;           /*!< Buffer1 address pointer */\r\n  \r\n  uint32_t   Buffer2NextDescAddr;   /*!< Buffer2 or next descriptor address pointer */\r\n  \r\n  /*!< Enhanced Ethernet DMA PTP Descriptors */\r\n  uint32_t   ExtendedStatus;        /*!< Extended status for PTP receive descriptor */\r\n  \r\n  uint32_t   Reserved1;             /*!< Reserved */\r\n  \r\n  uint32_t   TimeStampLow;          /*!< Time Stamp Low value for transmit and receive */\r\n  \r\n  uint32_t   TimeStampHigh;         /*!< Time Stamp High value for transmit and receive */\r\n\r\n} ETH_DMADescTypeDef;\r\n\r\n\r\n/** \r\n  * @brief  Received Frame Informations structure definition\r\n  */ \r\ntypedef struct  \r\n{\r\n  ETH_DMADescTypeDef *FSRxDesc;          /*!< First Segment Rx Desc */\r\n  \r\n  ETH_DMADescTypeDef *LSRxDesc;          /*!< Last Segment Rx Desc */\r\n  \r\n  uint32_t  SegCount;                    /*!< Segment count */\r\n  \r\n  uint32_t length;                       /*!< Frame length */\r\n  \r\n  uint32_t buffer;                       /*!< Frame buffer */\r\n\r\n} ETH_DMARxFrameInfos;\r\n\r\n\r\n/** \r\n  * @brief  ETH Handle Structure definition  \r\n  */\r\n  \r\ntypedef struct\r\n{\r\n  ETH_TypeDef                *Instance;     /*!< Register base address       */\r\n  \r\n  ETH_InitTypeDef            Init;          /*!< Ethernet Init Configuration */\r\n  \r\n  uint32_t                   LinkStatus;    /*!< Ethernet link status        */\r\n  \r\n  ETH_DMADescTypeDef         *RxDesc;       /*!< Rx descriptor to Get        */\r\n  \r\n  ETH_DMADescTypeDef         *TxDesc;       /*!< Tx descriptor to Set        */\r\n  \r\n  ETH_DMARxFrameInfos        RxFrameInfos;  /*!< last Rx frame infos         */\r\n  \r\n  __IO HAL_ETH_StateTypeDef  State;         /*!< ETH communication state     */\r\n  \r\n  HAL_LockTypeDef            Lock;          /*!< ETH Lock                    */\r\n\r\n} ETH_HandleTypeDef;\r\n\r\n /**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup ETH_Exported_Constants ETH Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup ETH_Buffers_setting ETH Buffers setting\r\n  * @{\r\n  */ \r\n#define ETH_MAX_PACKET_SIZE    ((uint32_t)1524U)    /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */\r\n#define ETH_HEADER               ((uint32_t)14U)    /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */\r\n#define ETH_CRC                   ((uint32_t)4U)    /*!< Ethernet CRC */\r\n#define ETH_EXTRA                 ((uint32_t)2U)    /*!< Extra bytes in some cases */   \r\n#define ETH_VLAN_TAG              ((uint32_t)4U)    /*!< optional 802.1q VLAN Tag */\r\n#define ETH_MIN_ETH_PAYLOAD       ((uint32_t)46U)    /*!< Minimum Ethernet payload size */\r\n#define ETH_MAX_ETH_PAYLOAD       ((uint32_t)1500U)    /*!< Maximum Ethernet payload size */\r\n#define ETH_JUMBO_FRAME_PAYLOAD   ((uint32_t)9000U)    /*!< Jumbo frame payload size */      \r\n\r\n /* Ethernet driver receive buffers are organized in a chained linked-list, when\r\n    an Ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO\r\n    to the driver receive buffers memory.\r\n\r\n    Depending on the size of the received Ethernet packet and the size of \r\n    each Ethernet driver receive buffer, the received packet can take one or more\r\n    Ethernet driver receive buffer. \r\n\r\n    In below are defined the size of one Ethernet driver receive buffer ETH_RX_BUF_SIZE \r\n    and the total count of the driver receive buffers ETH_RXBUFNB.\r\n\r\n    The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as \r\n    example, they can be reconfigured in the application layer to fit the application \r\n    needs */ \r\n\r\n/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet\r\n   packet */\r\n#ifndef ETH_RX_BUF_SIZE\r\n #define ETH_RX_BUF_SIZE         ETH_MAX_PACKET_SIZE \r\n#endif\r\n\r\n/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/ \r\n#ifndef ETH_RXBUFNB\r\n #define ETH_RXBUFNB             ((uint32_t)5U)     /*  5 Rx buffers of size ETH_RX_BUF_SIZE */\r\n#endif\r\n\r\n\r\n /* Ethernet driver transmit buffers are organized in a chained linked-list, when\r\n    an Ethernet packet is transmitted, Tx-DMA will transfer the packet from the \r\n    driver transmit buffers memory to the TxFIFO.\r\n\r\n    Depending on the size of the Ethernet packet to be transmitted and the size of \r\n    each Ethernet driver transmit buffer, the packet to be transmitted can take \r\n    one or more Ethernet driver transmit buffer. \r\n\r\n    In below are defined the size of one Ethernet driver transmit buffer ETH_TX_BUF_SIZE \r\n    and the total count of the driver transmit buffers ETH_TXBUFNB.\r\n\r\n    The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as \r\n    example, they can be reconfigured in the application layer to fit the application \r\n    needs */ \r\n\r\n/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet\r\n   packet */\r\n#ifndef ETH_TX_BUF_SIZE \r\n #define ETH_TX_BUF_SIZE         ETH_MAX_PACKET_SIZE\r\n#endif\r\n\r\n/* 5 Ethernet driver transmit buffers are used (in a chained linked list)*/ \r\n#ifndef ETH_TXBUFNB\r\n #define ETH_TXBUFNB             ((uint32_t)5U)      /* 5  Tx buffers of size ETH_TX_BUF_SIZE */\r\n#endif\r\n\r\n /**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor\r\n  * @{\r\n  */\r\n\r\n/*\r\n   DMA Tx Descriptor\r\n  -----------------------------------------------------------------------------------------------\r\n  TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |\r\n  -----------------------------------------------------------------------------------------------\r\n  TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |\r\n  -----------------------------------------------------------------------------------------------\r\n  TDES2 |                         Buffer1 Address [31:0]                                         |\r\n  -----------------------------------------------------------------------------------------------\r\n  TDES3 |                   Buffer2 Address [31:0] / Next Descriptor Address [31:0]              |\r\n  -----------------------------------------------------------------------------------------------\r\n*/\r\n\r\n/** \r\n  * @brief  Bit definition of TDES0 register: DMA Tx descriptor status register\r\n  */ \r\n#define ETH_DMATXDESC_OWN                     ((uint32_t)0x80000000U)  /*!< OWN bit: descriptor is owned by DMA engine */\r\n#define ETH_DMATXDESC_IC                      ((uint32_t)0x40000000U)  /*!< Interrupt on Completion */\r\n#define ETH_DMATXDESC_LS                      ((uint32_t)0x20000000U)  /*!< Last Segment */\r\n#define ETH_DMATXDESC_FS                      ((uint32_t)0x10000000U)  /*!< First Segment */\r\n#define ETH_DMATXDESC_DC                      ((uint32_t)0x08000000U)  /*!< Disable CRC */\r\n#define ETH_DMATXDESC_DP                      ((uint32_t)0x04000000U)  /*!< Disable Padding */\r\n#define ETH_DMATXDESC_TTSE                    ((uint32_t)0x02000000U)  /*!< Transmit Time Stamp Enable */\r\n#define ETH_DMATXDESC_CIC                     ((uint32_t)0x00C00000U)  /*!< Checksum Insertion Control: 4 cases */\r\n#define ETH_DMATXDESC_CIC_BYPASS              ((uint32_t)0x00000000U)  /*!< Do Nothing: Checksum Engine is bypassed */ \r\n#define ETH_DMATXDESC_CIC_IPV4HEADER          ((uint32_t)0x00400000U)  /*!< IPV4 header Checksum Insertion */ \r\n#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT  ((uint32_t)0x00800000U)  /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ \r\n#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL     ((uint32_t)0x00C00000U)  /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ \r\n#define ETH_DMATXDESC_TER                     ((uint32_t)0x00200000U)  /*!< Transmit End of Ring */\r\n#define ETH_DMATXDESC_TCH                     ((uint32_t)0x00100000U)  /*!< Second Address Chained */\r\n#define ETH_DMATXDESC_TTSS                    ((uint32_t)0x00020000U)  /*!< Tx Time Stamp Status */\r\n#define ETH_DMATXDESC_IHE                     ((uint32_t)0x00010000U)  /*!< IP Header Error */\r\n#define ETH_DMATXDESC_ES                      ((uint32_t)0x00008000U)  /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */\r\n#define ETH_DMATXDESC_JT                      ((uint32_t)0x00004000U)  /*!< Jabber Timeout */\r\n#define ETH_DMATXDESC_FF                      ((uint32_t)0x00002000U)  /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */\r\n#define ETH_DMATXDESC_PCE                     ((uint32_t)0x00001000U)  /*!< Payload Checksum Error */\r\n#define ETH_DMATXDESC_LCA                     ((uint32_t)0x00000800U)  /*!< Loss of Carrier: carrier lost during transmission */\r\n#define ETH_DMATXDESC_NC                      ((uint32_t)0x00000400U)  /*!< No Carrier: no carrier signal from the transceiver */\r\n#define ETH_DMATXDESC_LCO                     ((uint32_t)0x00000200U)  /*!< Late Collision: transmission aborted due to collision */\r\n#define ETH_DMATXDESC_EC                      ((uint32_t)0x00000100U)  /*!< Excessive Collision: transmission aborted after 16 collisions */\r\n#define ETH_DMATXDESC_VF                      ((uint32_t)0x00000080U)  /*!< VLAN Frame */\r\n#define ETH_DMATXDESC_CC                      ((uint32_t)0x00000078U)  /*!< Collision Count */\r\n#define ETH_DMATXDESC_ED                      ((uint32_t)0x00000004U)  /*!< Excessive Deferral */\r\n#define ETH_DMATXDESC_UF                      ((uint32_t)0x00000002U)  /*!< Underflow Error: late data arrival from the memory */\r\n#define ETH_DMATXDESC_DB                      ((uint32_t)0x00000001U)  /*!< Deferred Bit */\r\n\r\n/** \r\n  * @brief  Bit definition of TDES1 register\r\n  */ \r\n#define ETH_DMATXDESC_TBS2  ((uint32_t)0x1FFF0000U)  /*!< Transmit Buffer2 Size */\r\n#define ETH_DMATXDESC_TBS1  ((uint32_t)0x00001FFFU)  /*!< Transmit Buffer1 Size */\r\n\r\n/** \r\n  * @brief  Bit definition of TDES2 register\r\n  */ \r\n#define ETH_DMATXDESC_B1AP  ((uint32_t)0xFFFFFFFFU)  /*!< Buffer1 Address Pointer */\r\n\r\n/** \r\n  * @brief  Bit definition of TDES3 register\r\n  */ \r\n#define ETH_DMATXDESC_B2AP  ((uint32_t)0xFFFFFFFFU)  /*!< Buffer2 Address Pointer */\r\n\r\n  /*---------------------------------------------------------------------------------------------\r\n  TDES6 |                         Transmit Time Stamp Low [31:0]                                 |\r\n  -----------------------------------------------------------------------------------------------\r\n  TDES7 |                         Transmit Time Stamp High [31:0]                                |\r\n  ----------------------------------------------------------------------------------------------*/\r\n\r\n/* Bit definition of TDES6 register */\r\n #define ETH_DMAPTPTXDESC_TTSL  ((uint32_t)0xFFFFFFFFU)  /* Transmit Time Stamp Low */\r\n\r\n/* Bit definition of TDES7 register */\r\n #define ETH_DMAPTPTXDESC_TTSH  ((uint32_t)0xFFFFFFFFU)  /* Transmit Time Stamp High */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor\r\n  * @{\r\n  */\r\n\r\n/*\r\n  DMA Rx Descriptor\r\n  --------------------------------------------------------------------------------------------------------------------\r\n  RDES0 | OWN(31) |                                             Status [30:0]                                          |\r\n  ---------------------------------------------------------------------------------------------------------------------\r\n  RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |\r\n  ---------------------------------------------------------------------------------------------------------------------\r\n  RDES2 |                                       Buffer1 Address [31:0]                                                 |\r\n  ---------------------------------------------------------------------------------------------------------------------\r\n  RDES3 |                          Buffer2 Address [31:0] / Next Descriptor Address [31:0]                             |\r\n  ---------------------------------------------------------------------------------------------------------------------\r\n*/\r\n\r\n/** \r\n  * @brief  Bit definition of RDES0 register: DMA Rx descriptor status register\r\n  */ \r\n#define ETH_DMARXDESC_OWN         ((uint32_t)0x80000000U)  /*!< OWN bit: descriptor is owned by DMA engine  */\r\n#define ETH_DMARXDESC_AFM         ((uint32_t)0x40000000U)  /*!< DA Filter Fail for the rx frame  */\r\n#define ETH_DMARXDESC_FL          ((uint32_t)0x3FFF0000U)  /*!< Receive descriptor frame length  */\r\n#define ETH_DMARXDESC_ES          ((uint32_t)0x00008000U)  /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */\r\n#define ETH_DMARXDESC_DE          ((uint32_t)0x00004000U)  /*!< Descriptor error: no more descriptors for receive frame  */\r\n#define ETH_DMARXDESC_SAF         ((uint32_t)0x00002000U)  /*!< SA Filter Fail for the received frame */\r\n#define ETH_DMARXDESC_LE          ((uint32_t)0x00001000U)  /*!< Frame size not matching with length field */\r\n#define ETH_DMARXDESC_OE          ((uint32_t)0x00000800U)  /*!< Overflow Error: Frame was damaged due to buffer overflow */\r\n#define ETH_DMARXDESC_VLAN        ((uint32_t)0x00000400U)  /*!< VLAN Tag: received frame is a VLAN frame */\r\n#define ETH_DMARXDESC_FS          ((uint32_t)0x00000200U)  /*!< First descriptor of the frame  */\r\n#define ETH_DMARXDESC_LS          ((uint32_t)0x00000100U)  /*!< Last descriptor of the frame  */ \r\n#define ETH_DMARXDESC_IPV4HCE     ((uint32_t)0x00000080U)  /*!< IPC Checksum Error: Rx Ipv4 header checksum error   */    \r\n#define ETH_DMARXDESC_LC          ((uint32_t)0x00000040U)  /*!< Late collision occurred during reception   */\r\n#define ETH_DMARXDESC_FT          ((uint32_t)0x00000020U)  /*!< Frame type - Ethernet, otherwise 802.3    */\r\n#define ETH_DMARXDESC_RWT         ((uint32_t)0x00000010U)  /*!< Receive Watchdog Timeout: watchdog timer expired during reception    */\r\n#define ETH_DMARXDESC_RE          ((uint32_t)0x00000008U)  /*!< Receive error: error reported by MII interface  */\r\n#define ETH_DMARXDESC_DBE         ((uint32_t)0x00000004U)  /*!< Dribble bit error: frame contains non int multiple of 8 bits  */\r\n#define ETH_DMARXDESC_CE          ((uint32_t)0x00000002U)  /*!< CRC error */\r\n#define ETH_DMARXDESC_MAMPCE      ((uint32_t)0x00000001U)  /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */\r\n\r\n/** \r\n  * @brief  Bit definition of RDES1 register\r\n  */ \r\n#define ETH_DMARXDESC_DIC   ((uint32_t)0x80000000U)  /*!< Disable Interrupt on Completion */\r\n#define ETH_DMARXDESC_RBS2  ((uint32_t)0x1FFF0000U)  /*!< Receive Buffer2 Size */\r\n#define ETH_DMARXDESC_RER   ((uint32_t)0x00008000U)  /*!< Receive End of Ring */\r\n#define ETH_DMARXDESC_RCH   ((uint32_t)0x00004000U)  /*!< Second Address Chained */\r\n#define ETH_DMARXDESC_RBS1  ((uint32_t)0x00001FFFU)  /*!< Receive Buffer1 Size */\r\n\r\n/** \r\n  * @brief  Bit definition of RDES2 register  \r\n  */ \r\n#define ETH_DMARXDESC_B1AP  ((uint32_t)0xFFFFFFFFU)  /*!< Buffer1 Address Pointer */\r\n\r\n/** \r\n  * @brief  Bit definition of RDES3 register  \r\n  */ \r\n#define ETH_DMARXDESC_B2AP  ((uint32_t)0xFFFFFFFFU)  /*!< Buffer2 Address Pointer */\r\n\r\n/*---------------------------------------------------------------------------------------------------------------------\r\n  RDES4 |                   Reserved[31:15]              |             Extended Status [14:0]                          |\r\n  ---------------------------------------------------------------------------------------------------------------------\r\n  RDES5 |                                            Reserved[31:0]                                                    |\r\n  ---------------------------------------------------------------------------------------------------------------------\r\n  RDES6 |                                       Receive Time Stamp Low [31:0]                                          |\r\n  ---------------------------------------------------------------------------------------------------------------------\r\n  RDES7 |                                       Receive Time Stamp High [31:0]                                         |\r\n  --------------------------------------------------------------------------------------------------------------------*/\r\n\r\n/* Bit definition of RDES4 register */\r\n#define ETH_DMAPTPRXDESC_PTPV                            ((uint32_t)0x00002000U)  /* PTP Version */\r\n#define ETH_DMAPTPRXDESC_PTPFT                           ((uint32_t)0x00001000U)  /* PTP Frame Type */\r\n#define ETH_DMAPTPRXDESC_PTPMT                           ((uint32_t)0x00000F00U)  /* PTP Message Type */\r\n#define ETH_DMAPTPRXDESC_PTPMT_SYNC                      ((uint32_t)0x00000100U)  /* SYNC message (all clock types) */\r\n#define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP                  ((uint32_t)0x00000200U)  /* FollowUp message (all clock types) */ \r\n#define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ                  ((uint32_t)0x00000300U)  /* DelayReq message (all clock types) */ \r\n#define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP                 ((uint32_t)0x00000400U)  /* DelayResp message (all clock types) */ \r\n#define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE        ((uint32_t)0x00000500U)  /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */ \r\n#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG          ((uint32_t)0x00000600U)  /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock)  */ \r\n#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700U)  /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */           \r\n#define ETH_DMAPTPRXDESC_IPV6PR                          ((uint32_t)0x00000080U)  /* IPv6 Packet Received */\r\n#define ETH_DMAPTPRXDESC_IPV4PR                          ((uint32_t)0x00000040U)  /* IPv4 Packet Received */\r\n#define ETH_DMAPTPRXDESC_IPCB                            ((uint32_t)0x00000020U)  /* IP Checksum Bypassed */\r\n#define ETH_DMAPTPRXDESC_IPPE                            ((uint32_t)0x00000010U)  /* IP Payload Error */\r\n#define ETH_DMAPTPRXDESC_IPHE                            ((uint32_t)0x00000008U)  /* IP Header Error */\r\n#define ETH_DMAPTPRXDESC_IPPT                            ((uint32_t)0x00000007U)  /* IP Payload Type */\r\n#define ETH_DMAPTPRXDESC_IPPT_UDP                        ((uint32_t)0x00000001U)  /* UDP payload encapsulated in the IP datagram */\r\n#define ETH_DMAPTPRXDESC_IPPT_TCP                        ((uint32_t)0x00000002U)  /* TCP payload encapsulated in the IP datagram */ \r\n#define ETH_DMAPTPRXDESC_IPPT_ICMP                       ((uint32_t)0x00000003U)  /* ICMP payload encapsulated in the IP datagram */\r\n\r\n/* Bit definition of RDES6 register */\r\n#define ETH_DMAPTPRXDESC_RTSL  ((uint32_t)0xFFFFFFFFU)  /* Receive Time Stamp Low */\r\n\r\n/* Bit definition of RDES7 register */\r\n#define ETH_DMAPTPRXDESC_RTSH  ((uint32_t)0xFFFFFFFFU)  /* Receive Time Stamp High */\r\n/**\r\n  * @}\r\n  */\r\n /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation \r\n  * @{\r\n  */ \r\n#define ETH_AUTONEGOTIATION_ENABLE     ((uint32_t)0x00000001U)\r\n#define ETH_AUTONEGOTIATION_DISABLE    ((uint32_t)0x00000000U)\r\n\r\n/**\r\n  * @}\r\n  */\r\n/** @defgroup ETH_Speed ETH Speed \r\n  * @{\r\n  */ \r\n#define ETH_SPEED_10M        ((uint32_t)0x00000000U)\r\n#define ETH_SPEED_100M       ((uint32_t)0x00004000U)\r\n\r\n/**\r\n  * @}\r\n  */\r\n/** @defgroup ETH_Duplex_Mode ETH Duplex Mode\r\n  * @{\r\n  */ \r\n#define ETH_MODE_FULLDUPLEX       ((uint32_t)0x00000800U)\r\n#define ETH_MODE_HALFDUPLEX       ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n/** @defgroup ETH_Rx_Mode ETH Rx Mode\r\n  * @{\r\n  */ \r\n#define ETH_RXPOLLING_MODE      ((uint32_t)0x00000000U)\r\n#define ETH_RXINTERRUPT_MODE    ((uint32_t)0x00000001U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Checksum_Mode ETH Checksum Mode\r\n  * @{\r\n  */ \r\n#define ETH_CHECKSUM_BY_HARDWARE      ((uint32_t)0x00000000U)\r\n#define ETH_CHECKSUM_BY_SOFTWARE      ((uint32_t)0x00000001U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Media_Interface ETH Media Interface\r\n  * @{\r\n  */ \r\n#define ETH_MEDIA_INTERFACE_MII       ((uint32_t)0x00000000U)\r\n#define ETH_MEDIA_INTERFACE_RMII      ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Watchdog ETH Watchdog \r\n  * @{\r\n  */ \r\n#define ETH_WATCHDOG_ENABLE       ((uint32_t)0x00000000U)\r\n#define ETH_WATCHDOG_DISABLE      ((uint32_t)0x00800000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Jabber ETH Jabber\r\n  * @{\r\n  */ \r\n#define ETH_JABBER_ENABLE    ((uint32_t)0x00000000U)\r\n#define ETH_JABBER_DISABLE   ((uint32_t)0x00400000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap \r\n  * @{\r\n  */ \r\n#define ETH_INTERFRAMEGAP_96BIT   ((uint32_t)0x00000000U)  /*!< minimum IFG between frames during transmission is 96Bit */\r\n#define ETH_INTERFRAMEGAP_88BIT   ((uint32_t)0x00020000U)  /*!< minimum IFG between frames during transmission is 88Bit */\r\n#define ETH_INTERFRAMEGAP_80BIT   ((uint32_t)0x00040000U)  /*!< minimum IFG between frames during transmission is 80Bit */\r\n#define ETH_INTERFRAMEGAP_72BIT   ((uint32_t)0x00060000U)  /*!< minimum IFG between frames during transmission is 72Bit */\r\n#define ETH_INTERFRAMEGAP_64BIT   ((uint32_t)0x00080000U)  /*!< minimum IFG between frames during transmission is 64Bit */\r\n#define ETH_INTERFRAMEGAP_56BIT   ((uint32_t)0x000A0000U)  /*!< minimum IFG between frames during transmission is 56Bit */\r\n#define ETH_INTERFRAMEGAP_48BIT   ((uint32_t)0x000C0000U)  /*!< minimum IFG between frames during transmission is 48Bit */\r\n#define ETH_INTERFRAMEGAP_40BIT   ((uint32_t)0x000E0000U)  /*!< minimum IFG between frames during transmission is 40Bit */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Carrier_Sense ETH Carrier Sense\r\n  * @{\r\n  */ \r\n#define ETH_CARRIERSENCE_ENABLE   ((uint32_t)0x00000000U)\r\n#define ETH_CARRIERSENCE_DISABLE  ((uint32_t)0x00010000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Receive_Own ETH Receive Own \r\n  * @{\r\n  */ \r\n#define ETH_RECEIVEOWN_ENABLE     ((uint32_t)0x00000000U)\r\n#define ETH_RECEIVEOWN_DISABLE    ((uint32_t)0x00002000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode \r\n  * @{\r\n  */ \r\n#define ETH_LOOPBACKMODE_ENABLE        ((uint32_t)0x00001000U)\r\n#define ETH_LOOPBACKMODE_DISABLE       ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Checksum_Offload ETH Checksum Offload\r\n  * @{\r\n  */ \r\n#define ETH_CHECKSUMOFFLAOD_ENABLE     ((uint32_t)0x00000400U)\r\n#define ETH_CHECKSUMOFFLAOD_DISABLE    ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Retry_Transmission ETH Retry Transmission\r\n  * @{\r\n  */ \r\n#define ETH_RETRYTRANSMISSION_ENABLE   ((uint32_t)0x00000000U)\r\n#define ETH_RETRYTRANSMISSION_DISABLE  ((uint32_t)0x00000200U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip\r\n  * @{\r\n  */ \r\n#define ETH_AUTOMATICPADCRCSTRIP_ENABLE     ((uint32_t)0x00000080U)\r\n#define ETH_AUTOMATICPADCRCSTRIP_DISABLE    ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit\r\n  * @{\r\n  */ \r\n#define ETH_BACKOFFLIMIT_10  ((uint32_t)0x00000000U)\r\n#define ETH_BACKOFFLIMIT_8   ((uint32_t)0x00000020U)\r\n#define ETH_BACKOFFLIMIT_4   ((uint32_t)0x00000040U)\r\n#define ETH_BACKOFFLIMIT_1   ((uint32_t)0x00000060U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Deferral_Check ETH Deferral Check\r\n  * @{\r\n  */\r\n#define ETH_DEFFERRALCHECK_ENABLE       ((uint32_t)0x00000010U)\r\n#define ETH_DEFFERRALCHECK_DISABLE      ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Receive_All ETH Receive All\r\n  * @{\r\n  */ \r\n#define ETH_RECEIVEALL_ENABLE     ((uint32_t)0x80000000U)\r\n#define ETH_RECEIVEAll_DISABLE    ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter\r\n  * @{\r\n  */ \r\n#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE       ((uint32_t)0x00000200U)\r\n#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE      ((uint32_t)0x00000300U)\r\n#define ETH_SOURCEADDRFILTER_DISABLE             ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames\r\n  * @{\r\n  */ \r\n#define ETH_PASSCONTROLFRAMES_BLOCKALL                ((uint32_t)0x00000040U)  /*!< MAC filters all control frames from reaching the application */\r\n#define ETH_PASSCONTROLFRAMES_FORWARDALL              ((uint32_t)0x00000080U)  /*!< MAC forwards all control frames to application even if they fail the Address Filter */\r\n#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0U)  /*!< MAC forwards control frames that pass the Address Filter. */ \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception\r\n  * @{\r\n  */ \r\n#define ETH_BROADCASTFRAMESRECEPTION_ENABLE     ((uint32_t)0x00000000U)\r\n#define ETH_BROADCASTFRAMESRECEPTION_DISABLE    ((uint32_t)0x00000020U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter\r\n  * @{\r\n  */ \r\n#define ETH_DESTINATIONADDRFILTER_NORMAL    ((uint32_t)0x00000000U)\r\n#define ETH_DESTINATIONADDRFILTER_INVERSE   ((uint32_t)0x00000008U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode\r\n  * @{\r\n  */ \r\n#define ETH_PROMISCUOUS_MODE_ENABLE     ((uint32_t)0x00000001U)\r\n#define ETH_PROMISCUOUS_MODE_DISABLE    ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter\r\n  * @{\r\n  */ \r\n#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE    ((uint32_t)0x00000404U)\r\n#define ETH_MULTICASTFRAMESFILTER_HASHTABLE           ((uint32_t)0x00000004U)\r\n#define ETH_MULTICASTFRAMESFILTER_PERFECT             ((uint32_t)0x00000000U)\r\n#define ETH_MULTICASTFRAMESFILTER_NONE                ((uint32_t)0x00000010U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter\r\n  * @{\r\n  */ \r\n#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402U)\r\n#define ETH_UNICASTFRAMESFILTER_HASHTABLE        ((uint32_t)0x00000002U)\r\n#define ETH_UNICASTFRAMESFILTER_PERFECT          ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause \r\n  * @{\r\n  */ \r\n#define ETH_ZEROQUANTAPAUSE_ENABLE     ((uint32_t)0x00000000U)\r\n#define ETH_ZEROQUANTAPAUSE_DISABLE    ((uint32_t)0x00000080U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold\r\n  * @{\r\n  */ \r\n#define ETH_PAUSELOWTHRESHOLD_MINUS4        ((uint32_t)0x00000000U)  /*!< Pause time minus 4 slot times */\r\n#define ETH_PAUSELOWTHRESHOLD_MINUS28       ((uint32_t)0x00000010U)  /*!< Pause time minus 28 slot times */\r\n#define ETH_PAUSELOWTHRESHOLD_MINUS144      ((uint32_t)0x00000020U)  /*!< Pause time minus 144 slot times */\r\n#define ETH_PAUSELOWTHRESHOLD_MINUS256      ((uint32_t)0x00000030U)  /*!< Pause time minus 256 slot times */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect\r\n  * @{\r\n  */ \r\n#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE  ((uint32_t)0x00000008U)\r\n#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control\r\n  * @{\r\n  */ \r\n#define ETH_RECEIVEFLOWCONTROL_ENABLE       ((uint32_t)0x00000004U)\r\n#define ETH_RECEIVEFLOWCONTROL_DISABLE      ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control\r\n  * @{\r\n  */ \r\n#define ETH_TRANSMITFLOWCONTROL_ENABLE      ((uint32_t)0x00000002U)\r\n#define ETH_TRANSMITFLOWCONTROL_DISABLE     ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison\r\n  * @{\r\n  */ \r\n#define ETH_VLANTAGCOMPARISON_12BIT    ((uint32_t)0x00010000U)\r\n#define ETH_VLANTAGCOMPARISON_16BIT    ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_MAC_addresses ETH MAC addresses\r\n  * @{\r\n  */ \r\n#define ETH_MAC_ADDRESS0     ((uint32_t)0x00000000U)\r\n#define ETH_MAC_ADDRESS1     ((uint32_t)0x00000008U)\r\n#define ETH_MAC_ADDRESS2     ((uint32_t)0x00000010U)\r\n#define ETH_MAC_ADDRESS3     ((uint32_t)0x00000018U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA \r\n  * @{\r\n  */ \r\n#define ETH_MAC_ADDRESSFILTER_SA       ((uint32_t)0x00000000U)\r\n#define ETH_MAC_ADDRESSFILTER_DA       ((uint32_t)0x00000008U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes\r\n  * @{\r\n  */ \r\n#define ETH_MAC_ADDRESSMASK_BYTE6      ((uint32_t)0x20000000U)  /*!< Mask MAC Address high reg bits [15:8] */\r\n#define ETH_MAC_ADDRESSMASK_BYTE5      ((uint32_t)0x10000000U)  /*!< Mask MAC Address high reg bits [7:0] */\r\n#define ETH_MAC_ADDRESSMASK_BYTE4      ((uint32_t)0x08000000U)  /*!< Mask MAC Address low reg bits [31:24] */\r\n#define ETH_MAC_ADDRESSMASK_BYTE3      ((uint32_t)0x04000000U)  /*!< Mask MAC Address low reg bits [23:16] */\r\n#define ETH_MAC_ADDRESSMASK_BYTE2      ((uint32_t)0x02000000U)  /*!< Mask MAC Address low reg bits [15:8] */\r\n#define ETH_MAC_ADDRESSMASK_BYTE1      ((uint32_t)0x01000000U)  /*!< Mask MAC Address low reg bits [70] */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame\r\n  * @{\r\n  */ \r\n#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE   ((uint32_t)0x00000000U)\r\n#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE  ((uint32_t)0x04000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward\r\n  * @{\r\n  */ \r\n#define ETH_RECEIVESTOREFORWARD_ENABLE      ((uint32_t)0x02000000U)\r\n#define ETH_RECEIVESTOREFORWARD_DISABLE     ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame\r\n  * @{\r\n  */ \r\n#define ETH_FLUSHRECEIVEDFRAME_ENABLE       ((uint32_t)0x00000000U)\r\n#define ETH_FLUSHRECEIVEDFRAME_DISABLE      ((uint32_t)0x01000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward\r\n  * @{\r\n  */ \r\n#define ETH_TRANSMITSTOREFORWARD_ENABLE     ((uint32_t)0x00200000U)\r\n#define ETH_TRANSMITSTOREFORWARD_DISABLE    ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control\r\n  * @{\r\n  */ \r\n#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES     ((uint32_t)0x00000000U)  /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */\r\n#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES    ((uint32_t)0x00004000U)  /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */\r\n#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES    ((uint32_t)0x00008000U)  /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */\r\n#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES    ((uint32_t)0x0000C000U)  /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */\r\n#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES     ((uint32_t)0x00010000U)  /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */\r\n#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES     ((uint32_t)0x00014000U)  /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */\r\n#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES     ((uint32_t)0x00018000U)  /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */\r\n#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES     ((uint32_t)0x0001C000U)  /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames\r\n  * @{\r\n  */ \r\n#define ETH_FORWARDERRORFRAMES_ENABLE       ((uint32_t)0x00000080U)\r\n#define ETH_FORWARDERRORFRAMES_DISABLE      ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames\r\n  * @{\r\n  */ \r\n#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE   ((uint32_t)0x00000040U)\r\n#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE  ((uint32_t)0x00000000U)     \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control\r\n  * @{\r\n  */ \r\n#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES      ((uint32_t)0x00000000U)  /*!< threshold level of the MTL Receive FIFO is 64 Bytes */\r\n#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES      ((uint32_t)0x00000008U)  /*!< threshold level of the MTL Receive FIFO is 32 Bytes */\r\n#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES      ((uint32_t)0x00000010U)  /*!< threshold level of the MTL Receive FIFO is 96 Bytes */\r\n#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES     ((uint32_t)0x00000018U)  /*!< threshold level of the MTL Receive FIFO is 128 Bytes */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate\r\n  * @{\r\n  */ \r\n#define ETH_SECONDFRAMEOPERARTE_ENABLE       ((uint32_t)0x00000004U)\r\n#define ETH_SECONDFRAMEOPERARTE_DISABLE      ((uint32_t)0x00000000U)  \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats \r\n  * @{\r\n  */ \r\n#define ETH_ADDRESSALIGNEDBEATS_ENABLE      ((uint32_t)0x02000000U)\r\n#define ETH_ADDRESSALIGNEDBEATS_DISABLE     ((uint32_t)0x00000000U) \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Fixed_Burst ETH Fixed Burst\r\n  * @{\r\n  */ \r\n#define ETH_FIXEDBURST_ENABLE     ((uint32_t)0x00010000U)\r\n#define ETH_FIXEDBURST_DISABLE    ((uint32_t)0x00000000U) \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length\r\n  * @{\r\n  */ \r\n#define ETH_RXDMABURSTLENGTH_1BEAT          ((uint32_t)0x00020000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */\r\n#define ETH_RXDMABURSTLENGTH_2BEAT          ((uint32_t)0x00040000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */\r\n#define ETH_RXDMABURSTLENGTH_4BEAT          ((uint32_t)0x00080000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */\r\n#define ETH_RXDMABURSTLENGTH_8BEAT          ((uint32_t)0x00100000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */\r\n#define ETH_RXDMABURSTLENGTH_16BEAT         ((uint32_t)0x00200000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */\r\n#define ETH_RXDMABURSTLENGTH_32BEAT         ((uint32_t)0x00400000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */                \r\n#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT    ((uint32_t)0x01020000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */\r\n#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT    ((uint32_t)0x01040000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */\r\n#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT   ((uint32_t)0x01080000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */\r\n#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT   ((uint32_t)0x01100000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */\r\n#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT   ((uint32_t)0x01200000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */\r\n#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT  ((uint32_t)0x01400000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length\r\n  * @{\r\n  */ \r\n#define ETH_TXDMABURSTLENGTH_1BEAT          ((uint32_t)0x00000100U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */\r\n#define ETH_TXDMABURSTLENGTH_2BEAT          ((uint32_t)0x00000200U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */\r\n#define ETH_TXDMABURSTLENGTH_4BEAT          ((uint32_t)0x00000400U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r\n#define ETH_TXDMABURSTLENGTH_8BEAT          ((uint32_t)0x00000800U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r\n#define ETH_TXDMABURSTLENGTH_16BEAT         ((uint32_t)0x00001000U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r\n#define ETH_TXDMABURSTLENGTH_32BEAT         ((uint32_t)0x00002000U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                \r\n#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT    ((uint32_t)0x01000100U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r\n#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT    ((uint32_t)0x01000200U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r\n#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT   ((uint32_t)0x01000400U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r\n#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT   ((uint32_t)0x01000800U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\r\n#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT   ((uint32_t)0x01001000U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */\r\n#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT  ((uint32_t)0x01002000U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format\r\n  * @{\r\n  */  \r\n#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE              ((uint32_t)0x00000080U)\r\n#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE             ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration\r\n  * @{\r\n  */ \r\n#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1   ((uint32_t)0x00000000U)\r\n#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1   ((uint32_t)0x00004000U)\r\n#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1   ((uint32_t)0x00008000U)\r\n#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1   ((uint32_t)0x0000C000U)\r\n#define ETH_DMAARBITRATION_RXPRIORTX             ((uint32_t)0x00000002U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment\r\n  * @{\r\n  */ \r\n#define ETH_DMATXDESC_LASTSEGMENTS      ((uint32_t)0x40000000U)  /*!< Last Segment */\r\n#define ETH_DMATXDESC_FIRSTSEGMENT      ((uint32_t)0x20000000U)  /*!< First Segment */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control\r\n  * @{\r\n  */ \r\n#define ETH_DMATXDESC_CHECKSUMBYPASS             ((uint32_t)0x00000000U)   /*!< Checksum engine bypass */\r\n#define ETH_DMATXDESC_CHECKSUMIPV4HEADER         ((uint32_t)0x00400000U)   /*!< IPv4 header checksum insertion  */\r\n#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT  ((uint32_t)0x00800000U)   /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */\r\n#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL     ((uint32_t)0x00C00000U)   /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers \r\n  * @{\r\n  */ \r\n#define ETH_DMARXDESC_BUFFER1     ((uint32_t)0x00000000U)  /*!< DMA Rx Desc Buffer1 */\r\n#define ETH_DMARXDESC_BUFFER2     ((uint32_t)0x00000001U)  /*!< DMA Rx Desc Buffer2 */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_PMT_Flags ETH PMT Flags\r\n  * @{\r\n  */ \r\n#define ETH_PMT_FLAG_WUFFRPR      ((uint32_t)0x80000000U)  /*!< Wake-Up Frame Filter Register Pointer Reset */\r\n#define ETH_PMT_FLAG_WUFR         ((uint32_t)0x00000040U)  /*!< Wake-Up Frame Received */\r\n#define ETH_PMT_FLAG_MPR          ((uint32_t)0x00000020U)  /*!< Magic Packet Received */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts\r\n  * @{\r\n  */ \r\n#define ETH_MMC_IT_TGF       ((uint32_t)0x00200000U)  /*!< When Tx good frame counter reaches half the maximum value */\r\n#define ETH_MMC_IT_TGFMSC    ((uint32_t)0x00008000U)  /*!< When Tx good multi col counter reaches half the maximum value */\r\n#define ETH_MMC_IT_TGFSC     ((uint32_t)0x00004000U)  /*!< When Tx good single col counter reaches half the maximum value */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts\r\n  * @{\r\n  */\r\n#define ETH_MMC_IT_RGUF      ((uint32_t)0x10020000U)  /*!< When Rx good unicast frames counter reaches half the maximum value */\r\n#define ETH_MMC_IT_RFAE      ((uint32_t)0x10000040U)  /*!< When Rx alignment error counter reaches half the maximum value */\r\n#define ETH_MMC_IT_RFCE      ((uint32_t)0x10000020U)  /*!< When Rx crc error counter reaches half the maximum value */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_MAC_Flags ETH MAC Flags\r\n  * @{\r\n  */ \r\n#define ETH_MAC_FLAG_TST     ((uint32_t)0x00000200U)  /*!< Time stamp trigger flag (on MAC) */\r\n#define ETH_MAC_FLAG_MMCT    ((uint32_t)0x00000040U)  /*!< MMC transmit flag  */\r\n#define ETH_MAC_FLAG_MMCR    ((uint32_t)0x00000020U)  /*!< MMC receive flag */\r\n#define ETH_MAC_FLAG_MMC     ((uint32_t)0x00000010U)  /*!< MMC flag (on MAC) */\r\n#define ETH_MAC_FLAG_PMT     ((uint32_t)0x00000008U)  /*!< PMT flag (on MAC) */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_DMA_Flags ETH DMA Flags\r\n  * @{\r\n  */ \r\n#define ETH_DMA_FLAG_TST               ((uint32_t)0x20000000U)  /*!< Time-stamp trigger interrupt (on DMA) */\r\n#define ETH_DMA_FLAG_PMT               ((uint32_t)0x10000000U)  /*!< PMT interrupt (on DMA) */\r\n#define ETH_DMA_FLAG_MMC               ((uint32_t)0x08000000U)  /*!< MMC interrupt (on DMA) */\r\n#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000U)  /*!< Error bits 0-Rx DMA, 1-Tx DMA */\r\n#define ETH_DMA_FLAG_READWRITEERROR    ((uint32_t)0x01000000U)  /*!< Error bits 0-write transfer, 1-read transfer */\r\n#define ETH_DMA_FLAG_ACCESSERROR       ((uint32_t)0x02000000U)  /*!< Error bits 0-data buffer, 1-desc. access */\r\n#define ETH_DMA_FLAG_NIS               ((uint32_t)0x00010000U)  /*!< Normal interrupt summary flag */\r\n#define ETH_DMA_FLAG_AIS               ((uint32_t)0x00008000U)  /*!< Abnormal interrupt summary flag */\r\n#define ETH_DMA_FLAG_ER                ((uint32_t)0x00004000U)  /*!< Early receive flag */\r\n#define ETH_DMA_FLAG_FBE               ((uint32_t)0x00002000U)  /*!< Fatal bus error flag */\r\n#define ETH_DMA_FLAG_ET                ((uint32_t)0x00000400U)  /*!< Early transmit flag */\r\n#define ETH_DMA_FLAG_RWT               ((uint32_t)0x00000200U)  /*!< Receive watchdog timeout flag */\r\n#define ETH_DMA_FLAG_RPS               ((uint32_t)0x00000100U)  /*!< Receive process stopped flag */\r\n#define ETH_DMA_FLAG_RBU               ((uint32_t)0x00000080U)  /*!< Receive buffer unavailable flag */\r\n#define ETH_DMA_FLAG_R                 ((uint32_t)0x00000040U)  /*!< Receive flag */\r\n#define ETH_DMA_FLAG_TU                ((uint32_t)0x00000020U)  /*!< Underflow flag */\r\n#define ETH_DMA_FLAG_RO                ((uint32_t)0x00000010U)  /*!< Overflow flag */\r\n#define ETH_DMA_FLAG_TJT               ((uint32_t)0x00000008U)  /*!< Transmit jabber timeout flag */\r\n#define ETH_DMA_FLAG_TBU               ((uint32_t)0x00000004U)  /*!< Transmit buffer unavailable flag */\r\n#define ETH_DMA_FLAG_TPS               ((uint32_t)0x00000002U)  /*!< Transmit process stopped flag */\r\n#define ETH_DMA_FLAG_T                 ((uint32_t)0x00000001U)  /*!< Transmit flag */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts \r\n  * @{\r\n  */ \r\n#define ETH_MAC_IT_TST       ((uint32_t)0x00000200U)  /*!< Time stamp trigger interrupt (on MAC) */\r\n#define ETH_MAC_IT_MMCT      ((uint32_t)0x00000040U)  /*!< MMC transmit interrupt */\r\n#define ETH_MAC_IT_MMCR      ((uint32_t)0x00000020U)  /*!< MMC receive interrupt */\r\n#define ETH_MAC_IT_MMC       ((uint32_t)0x00000010U)  /*!< MMC interrupt (on MAC) */\r\n#define ETH_MAC_IT_PMT       ((uint32_t)0x00000008U)  /*!< PMT interrupt (on MAC) */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts \r\n  * @{\r\n  */ \r\n#define ETH_DMA_IT_TST       ((uint32_t)0x20000000U)  /*!< Time-stamp trigger interrupt (on DMA) */\r\n#define ETH_DMA_IT_PMT       ((uint32_t)0x10000000U)  /*!< PMT interrupt (on DMA) */\r\n#define ETH_DMA_IT_MMC       ((uint32_t)0x08000000U)  /*!< MMC interrupt (on DMA) */\r\n#define ETH_DMA_IT_NIS       ((uint32_t)0x00010000U)  /*!< Normal interrupt summary */\r\n#define ETH_DMA_IT_AIS       ((uint32_t)0x00008000U)  /*!< Abnormal interrupt summary */\r\n#define ETH_DMA_IT_ER        ((uint32_t)0x00004000U)  /*!< Early receive interrupt */\r\n#define ETH_DMA_IT_FBE       ((uint32_t)0x00002000U)  /*!< Fatal bus error interrupt */\r\n#define ETH_DMA_IT_ET        ((uint32_t)0x00000400U)  /*!< Early transmit interrupt */\r\n#define ETH_DMA_IT_RWT       ((uint32_t)0x00000200U)  /*!< Receive watchdog timeout interrupt */\r\n#define ETH_DMA_IT_RPS       ((uint32_t)0x00000100U)  /*!< Receive process stopped interrupt */\r\n#define ETH_DMA_IT_RBU       ((uint32_t)0x00000080U)  /*!< Receive buffer unavailable interrupt */\r\n#define ETH_DMA_IT_R         ((uint32_t)0x00000040U)  /*!< Receive interrupt */\r\n#define ETH_DMA_IT_TU        ((uint32_t)0x00000020U)  /*!< Underflow interrupt */\r\n#define ETH_DMA_IT_RO        ((uint32_t)0x00000010U)  /*!< Overflow interrupt */\r\n#define ETH_DMA_IT_TJT       ((uint32_t)0x00000008U)  /*!< Transmit jabber timeout interrupt */\r\n#define ETH_DMA_IT_TBU       ((uint32_t)0x00000004U)  /*!< Transmit buffer unavailable interrupt */\r\n#define ETH_DMA_IT_TPS       ((uint32_t)0x00000002U)  /*!< Transmit process stopped interrupt */\r\n#define ETH_DMA_IT_T         ((uint32_t)0x00000001U)  /*!< Transmit interrupt */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state \r\n  * @{\r\n  */ \r\n#define ETH_DMA_TRANSMITPROCESS_STOPPED     ((uint32_t)0x00000000U)  /*!< Stopped - Reset or Stop Tx Command issued */\r\n#define ETH_DMA_TRANSMITPROCESS_FETCHING    ((uint32_t)0x00100000U)  /*!< Running - fetching the Tx descriptor */\r\n#define ETH_DMA_TRANSMITPROCESS_WAITING     ((uint32_t)0x00200000U)  /*!< Running - waiting for status */\r\n#define ETH_DMA_TRANSMITPROCESS_READING     ((uint32_t)0x00300000U)  /*!< Running - reading the data from host memory */\r\n#define ETH_DMA_TRANSMITPROCESS_SUSPENDED   ((uint32_t)0x00600000U)  /*!< Suspended - Tx Descriptor unavailable */\r\n#define ETH_DMA_TRANSMITPROCESS_CLOSING     ((uint32_t)0x00700000U)  /*!< Running - closing Rx descriptor */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state \r\n  * @{\r\n  */ \r\n#define ETH_DMA_RECEIVEPROCESS_STOPPED      ((uint32_t)0x00000000U)  /*!< Stopped - Reset or Stop Rx Command issued */\r\n#define ETH_DMA_RECEIVEPROCESS_FETCHING     ((uint32_t)0x00020000U)  /*!< Running - fetching the Rx descriptor */\r\n#define ETH_DMA_RECEIVEPROCESS_WAITING      ((uint32_t)0x00060000U)  /*!< Running - waiting for packet */\r\n#define ETH_DMA_RECEIVEPROCESS_SUSPENDED    ((uint32_t)0x00080000U)  /*!< Suspended - Rx Descriptor unavailable */\r\n#define ETH_DMA_RECEIVEPROCESS_CLOSING      ((uint32_t)0x000A0000U)  /*!< Running - closing descriptor */\r\n#define ETH_DMA_RECEIVEPROCESS_QUEUING      ((uint32_t)0x000E0000U)  /*!< Running - queuing the receive frame into host memory */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_DMA_overflow ETH DMA overflow\r\n  * @{\r\n  */ \r\n#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER      ((uint32_t)0x10000000U)  /*!< Overflow bit for FIFO overflow counter */\r\n#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000U)  /*!< Overflow bit for missed frame counter */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP\r\n  * @{\r\n  */ \r\n#define ETH_EXTI_LINE_WAKEUP              ((uint32_t)0x00080000U)  /*!< External interrupt line 19 Connected to the ETH EXTI Line */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup ETH_Exported_Macros ETH Exported Macros\r\n *  @brief macros to handle interrupts and specific clock configurations\r\n * @{\r\n */\r\n \r\n/** @brief Reset ETH handle state\r\n  * @param  __HANDLE__ specifies the ETH handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)\r\n\r\n/** \r\n  * @brief  Checks whether the specified Ethernet DMA Tx Desc flag is set or not.\r\n  * @param  __HANDLE__ ETH Handle\r\n  * @param  __FLAG__ specifies the flag of TDES0 to check.\r\n  * @retval the ETH_DMATxDescFlag (SET or RESET).\r\n  */\r\n#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__)             ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))\r\n\r\n/**\r\n  * @brief  Checks whether the specified Ethernet DMA Rx Desc flag is set or not.\r\n  * @param  __HANDLE__ ETH Handle\r\n  * @param  __FLAG__ specifies the flag of RDES0 to check.\r\n  * @retval the ETH_DMATxDescFlag (SET or RESET).\r\n  */\r\n#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__)             ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))\r\n\r\n/**\r\n  * @brief  Enables the specified DMA Rx Desc receive interrupt.\r\n  * @param  __HANDLE__ ETH Handle\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__)                          ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))\r\n\r\n/**\r\n  * @brief  Disables the specified DMA Rx Desc receive interrupt.\r\n  * @param  __HANDLE__ ETH Handle\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__)                         ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)\r\n\r\n/**\r\n  * @brief  Set the specified DMA Rx Desc Own bit.\r\n  * @param  __HANDLE__ ETH Handle\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__)                           ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)\r\n\r\n/**\r\n  * @brief  Returns the specified Ethernet DMA Tx Desc collision count.\r\n  * @param  __HANDLE__ ETH Handle                     \r\n  * @retval The Transmit descriptor collision counter value.\r\n  */\r\n#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__)                   (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)\r\n\r\n/**\r\n  * @brief  Set the specified DMA Tx Desc Own bit.\r\n  * @param  __HANDLE__ ETH Handle\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__)                       ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)\r\n\r\n/**\r\n  * @brief  Enables the specified DMA Tx Desc Transmit interrupt.\r\n  * @param  __HANDLE__ ETH Handle                   \r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__)                          ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)\r\n\r\n/**\r\n  * @brief  Disables the specified DMA Tx Desc Transmit interrupt.\r\n  * @param  __HANDLE__ ETH Handle             \r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__)                          ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)\r\n\r\n/**\r\n  * @brief  Selects the specified Ethernet DMA Tx Desc Checksum Insertion.\r\n  * @param  __HANDLE__ ETH Handle  \r\n  * @param  __CHECKSUM__ specifies is the DMA Tx desc checksum insertion.\r\n  *   This parameter can be one of the following values:\r\n  *     @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass\r\n  *     @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum\r\n  *     @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present\r\n  *     @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header                                                                \r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__)     ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))\r\n\r\n/**\r\n  * @brief  Enables the DMA Tx Desc CRC.\r\n  * @param  __HANDLE__ ETH Handle \r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__)                          ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)\r\n\r\n/**\r\n  * @brief  Disables the DMA Tx Desc CRC.\r\n  * @param  __HANDLE__ ETH Handle \r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__)                         ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)\r\n\r\n/**\r\n  * @brief  Enables the DMA Tx Desc padding for frame shorter than 64 bytes.\r\n  * @param  __HANDLE__ ETH Handle \r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__)            ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)\r\n\r\n/**\r\n  * @brief  Disables the DMA Tx Desc padding for frame shorter than 64 bytes.\r\n  * @param  __HANDLE__ ETH Handle \r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__)           ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)\r\n\r\n/** \r\n * @brief  Enables the specified Ethernet MAC interrupts.\r\n  * @param  __HANDLE__    ETH Handle\r\n  * @param  __INTERRUPT__ specifies the Ethernet MAC interrupt sources to be\r\n  *   enabled or disabled.\r\n  *   This parameter can be any combination of the following values:\r\n  *     @arg ETH_MAC_IT_TST : Time stamp trigger interrupt \r\n  *     @arg ETH_MAC_IT_PMT : PMT interrupt \r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                 ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disables the specified Ethernet MAC interrupts.\r\n  * @param  __HANDLE__    ETH Handle\r\n  * @param  __INTERRUPT__ specifies the Ethernet MAC interrupt sources to be\r\n  *   enabled or disabled.\r\n  *   This parameter can be any combination of the following values:\r\n  *     @arg ETH_MAC_IT_TST : Time stamp trigger interrupt \r\n  *     @arg ETH_MAC_IT_PMT : PMT interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__)                ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Initiate a Pause Control Frame (Full-duplex only).\r\n  * @param  __HANDLE__ ETH Handle\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__)              ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)\r\n\r\n/**\r\n  * @brief  Checks whether the Ethernet flow control busy bit is set or not.\r\n  * @param  __HANDLE__ ETH Handle\r\n  * @retval The new state of flow control busy status bit (SET or RESET).\r\n  */\r\n#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__)               (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)\r\n\r\n/**\r\n  * @brief  Enables the MAC Back Pressure operation activation (Half-duplex only).\r\n  * @param  __HANDLE__ ETH Handle\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__)          ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)\r\n\r\n/**\r\n  * @brief  Disables the MAC BackPressure operation activation (Half-duplex only).\r\n  * @param  __HANDLE__ ETH Handle\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__)         ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)\r\n\r\n/**\r\n  * @brief  Checks whether the specified Ethernet MAC flag is set or not.\r\n  * @param  __HANDLE__ ETH Handle\r\n  * @param  __FLAG__ specifies the flag to check.\r\n  *   This parameter can be one of the following values:\r\n  *     @arg ETH_MAC_FLAG_TST  : Time stamp trigger flag   \r\n  *     @arg ETH_MAC_FLAG_MMCT : MMC transmit flag  \r\n  *     @arg ETH_MAC_FLAG_MMCR : MMC receive flag   \r\n  *     @arg ETH_MAC_FLAG_MMC  : MMC flag  \r\n  *     @arg ETH_MAC_FLAG_PMT  : PMT flag  \r\n  * @retval The state of Ethernet MAC flag.\r\n  */\r\n#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__)                   (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))\r\n\r\n/** \r\n  * @brief  Enables the specified Ethernet DMA interrupts.\r\n  * @param  __HANDLE__    ETH Handle\r\n  * @param  __INTERRUPT__ specifies the Ethernet DMA interrupt sources to be\r\n  *   enabled @ref ETH_DMA_Interrupts\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)                 ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disables the specified Ethernet DMA interrupts.\r\n  * @param  __HANDLE__    ETH Handle\r\n  * @param  __INTERRUPT__ specifies the Ethernet DMA interrupt sources to be\r\n  *   disabled. @ref ETH_DMA_Interrupts\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)                ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Clears the Ethernet DMA IT pending bit.\r\n  * @param  __HANDLE__    ETH Handle\r\n  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Checks whether the specified Ethernet DMA flag is set or not.\r\n* @param  __HANDLE__ ETH Handle\r\n  * @param  __FLAG__ specifies the flag to check. @ref ETH_DMA_Flags\r\n  * @retval The new state of ETH_DMA_FLAG (SET or RESET).\r\n  */\r\n#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__)                   (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))\r\n\r\n/**\r\n  * @brief  Checks whether the specified Ethernet DMA flag is set or not.\r\n  * @param  __HANDLE__ ETH Handle\r\n  * @param  __FLAG__ specifies the flag to clear. @ref ETH_DMA_Flags\r\n  * @retval The new state of ETH_DMA_FLAG (SET or RESET).\r\n  */\r\n#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)                 ((__HANDLE__)->Instance->DMASR = (__FLAG__))\r\n\r\n/**\r\n  * @brief  Checks whether the specified Ethernet DMA overflow flag is set or not.\r\n  * @param  __HANDLE__ ETH Handle\r\n  * @param  __OVERFLOW__ specifies the DMA overflow flag to check.\r\n  *   This parameter can be one of the following values:\r\n  *     @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter\r\n  *     @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter\r\n  * @retval The state of Ethernet DMA overflow Flag (SET or RESET).\r\n  */\r\n#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__)       (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))\r\n\r\n/**\r\n  * @brief  Set the DMA Receive status watchdog timer register value\r\n  * @param  __HANDLE__ ETH Handle\r\n  * @param  __VALUE__ DMA Receive status watchdog timer register value   \r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__)       ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))\r\n\r\n/** \r\n  * @brief  Enables any unicast packet filtered by the MAC address\r\n  *   recognition to be a wake-up frame.\r\n  * @param  __HANDLE__ ETH Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)\r\n\r\n/**\r\n  * @brief  Disables any unicast packet filtered by the MAC address\r\n  *   recognition to be a wake-up frame.\r\n  * @param  __HANDLE__ ETH Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)\r\n\r\n/**\r\n  * @brief  Enables the MAC Wake-Up Frame Detection.\r\n  * @param  __HANDLE__ ETH Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__)              ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)\r\n\r\n/**\r\n  * @brief  Disables the MAC Wake-Up Frame Detection.\r\n  * @param  __HANDLE__ ETH Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__)             ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)\r\n\r\n/**\r\n  * @brief  Enables the MAC Magic Packet Detection.\r\n  * @param  __HANDLE__ ETH Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__)              ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)\r\n\r\n/**\r\n  * @brief  Disables the MAC Magic Packet Detection.\r\n  * @param  __HANDLE__ ETH Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__)             ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)\r\n\r\n/**\r\n  * @brief  Enables the MAC Power Down.\r\n  * @param  __HANDLE__ ETH Handle\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)\r\n\r\n/**\r\n  * @brief  Disables the MAC Power Down.\r\n  * @param  __HANDLE__ ETH Handle\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)\r\n\r\n/**\r\n  * @brief  Checks whether the specified Ethernet PMT flag is set or not.\r\n  * @param  __HANDLE__ ETH Handle.\r\n  * @param  __FLAG__ specifies the flag to check.\r\n  *   This parameter can be one of the following values:\r\n  *     @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset \r\n  *     @arg ETH_PMT_FLAG_WUFR    : Wake-Up Frame Received \r\n  *     @arg ETH_PMT_FLAG_MPR     : Magic Packet Received\r\n  * @retval The new state of Ethernet PMT Flag (SET or RESET).\r\n  */\r\n#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__)               (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))\r\n\r\n/** \r\n  * @brief  Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)\r\n  * @param   __HANDLE__ ETH Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__)                     ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))\r\n\r\n/**\r\n  * @brief  Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)\r\n  * @param  __HANDLE__ ETH Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__)                     do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\\\r\n                                                                          (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)\r\n\r\n/**\r\n  * @brief  Enables the MMC Counter Freeze.\r\n  * @param  __HANDLE__ ETH Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__)                  ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)\r\n\r\n/**\r\n  * @brief  Disables the MMC Counter Freeze.\r\n  * @param  __HANDLE__ ETH Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__)                 ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)\r\n\r\n/**\r\n  * @brief  Enables the MMC Reset On Read.\r\n  * @param  __HANDLE__ ETH Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)\r\n\r\n/**\r\n  * @brief  Disables the MMC Reset On Read.\r\n  * @param  __HANDLE__ ETH Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)\r\n\r\n/**\r\n  * @brief  Enables the MMC Counter Stop Rollover.\r\n  * @param  __HANDLE__ ETH Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__)            ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)\r\n\r\n/**\r\n  * @brief  Disables the MMC Counter Stop Rollover.\r\n  * @param  __HANDLE__ ETH Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__)           ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)\r\n\r\n/**\r\n  * @brief  Resets the MMC Counters.\r\n  * @param   __HANDLE__ ETH Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__)                         ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)\r\n\r\n/**\r\n  * @brief  Enables the specified Ethernet MMC Rx interrupts.\r\n  * @param   __HANDLE__ ETH Handle.\r\n  * @param  __INTERRUPT__ specifies the Ethernet MMC interrupt sources to be enabled or disabled.\r\n  *   This parameter can be one of the following values:  \r\n  *     @arg ETH_MMC_IT_RGUF  : When Rx good unicast frames counter reaches half the maximum value \r\n  *     @arg ETH_MMC_IT_RFAE  : When Rx alignment error counter reaches half the maximum value \r\n  *     @arg ETH_MMC_IT_RFCE  : When Rx crc error counter reaches half the maximum value\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__)               (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)\r\n/**\r\n  * @brief  Disables the specified Ethernet MMC Rx interrupts.\r\n  * @param   __HANDLE__ ETH Handle.\r\n  * @param  __INTERRUPT__ specifies the Ethernet MMC interrupt sources to be enabled or disabled.\r\n  *   This parameter can be one of the following values: \r\n  *     @arg ETH_MMC_IT_RGUF  : When Rx good unicast frames counter reaches half the maximum value \r\n  *     @arg ETH_MMC_IT_RFAE  : When Rx alignment error counter reaches half the maximum value \r\n  *     @arg ETH_MMC_IT_RFCE  : When Rx crc error counter reaches half the maximum value\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__)              (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF)\r\n/**\r\n  * @brief  Enables the specified Ethernet MMC Tx interrupts.\r\n  * @param   __HANDLE__ ETH Handle.\r\n  * @param  __INTERRUPT__ specifies the Ethernet MMC interrupt sources to be enabled or disabled.\r\n  *   This parameter can be one of the following values:  \r\n  *     @arg ETH_MMC_IT_TGF   : When Tx good frame counter reaches half the maximum value \r\n  *     @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value \r\n  *     @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value \r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__)            ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disables the specified Ethernet MMC Tx interrupts.\r\n  * @param   __HANDLE__ ETH Handle.\r\n  * @param  __INTERRUPT__ specifies the Ethernet MMC interrupt sources to be enabled or disabled.\r\n  *   This parameter can be one of the following values:  \r\n  *     @arg ETH_MMC_IT_TGF   : When Tx good frame counter reaches half the maximum value \r\n  *     @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value \r\n  *     @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value \r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__)           ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Enables the ETH External interrupt line.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT()    EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)\r\n\r\n/**\r\n  * @brief  Disables the ETH External interrupt line.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT()   EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)\r\n\r\n/**\r\n  * @brief Enable event on ETH External event line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT()  EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)\r\n\r\n/**\r\n  * @brief Disable event on ETH External event line\r\n  * @retval None.\r\n  */\r\n#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)\r\n\r\n/**\r\n  * @brief  Get flag of the ETH External interrupt line.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG()     EXTI->PR & (ETH_EXTI_LINE_WAKEUP)\r\n\r\n/**\r\n  * @brief  Clear flag of the ETH External interrupt line.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG()   EXTI->PR = (ETH_EXTI_LINE_WAKEUP)\r\n\r\n/**\r\n  * @brief  Enables rising edge trigger to the ETH External interrupt line.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER()  EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP\r\n                                                            \r\n/**\r\n  * @brief  Disables the rising edge trigger to the ETH External interrupt line.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER()  EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)                                                          \r\n\r\n/**\r\n  * @brief  Enables falling edge trigger to the ETH External interrupt line.\r\n  * @retval None\r\n  */                                                      \r\n#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER()  EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)\r\n\r\n/**\r\n  * @brief  Disables falling edge trigger to the ETH External interrupt line.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER()  EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)\r\n\r\n/**\r\n  * @brief  Enables rising/falling edge trigger to the ETH External interrupt line.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER()  do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\\\r\n                                                                 EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\\\r\n                                                                 }while(0)\r\n\r\n/**\r\n  * @brief  Disables rising/falling edge trigger to the ETH External interrupt line.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER()  do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\\\r\n                                                                  EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\\\r\n                                                                  }while(0)\r\n\r\n/**\r\n  * @brief Generate a Software interrupt on selected EXTI line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT()                  EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @addtogroup ETH_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/* Initialization and de-initialization functions  ****************************/\r\n\r\n/** @addtogroup ETH_Exported_Functions_Group1\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);\r\nHAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);\r\nvoid HAL_ETH_MspInit(ETH_HandleTypeDef *heth);\r\nvoid HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);\r\nHAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);\r\nHAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* IO operation functions  ****************************************************/\r\n\r\n/** @addtogroup ETH_Exported_Functions_Group2\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);\r\nHAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);\r\n/* Communication with PHY functions*/\r\nHAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);\r\nHAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);\r\nvoid HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);\r\n/* Callback in non blocking modes (Interrupt) */\r\nvoid HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);\r\nvoid HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);\r\nvoid HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Peripheral Control functions  **********************************************/\r\n\r\n/** @addtogroup ETH_Exported_Functions_Group3\r\n  * @{\r\n  */\r\n\r\nHAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);\r\nHAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);\r\nHAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);\r\nHAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Peripheral State functions  ************************************************/\r\n\r\n/** @addtogroup ETH_Exported_Functions_Group4\r\n  * @{\r\n  */\r\nHAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n#endif /* ETH */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_ETH_H */\r\n\r\n\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_flash.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of FLASH HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_FLASH_H\r\n#define __STM32F7xx_HAL_FLASH_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup FLASH\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup FLASH_Exported_Types FLASH Exported Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  FLASH Procedure structure definition\r\n  */\r\ntypedef enum\r\n{\r\n  FLASH_PROC_NONE = 0U,\r\n  FLASH_PROC_SECTERASE,\r\n  FLASH_PROC_MASSERASE,\r\n  FLASH_PROC_PROGRAM\r\n} FLASH_ProcedureTypeDef;\r\n\r\n\r\n/**\r\n  * @brief  FLASH handle Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  __IO FLASH_ProcedureTypeDef ProcedureOnGoing;   /* Internal variable to indicate which procedure is ongoing or not in IT context */\r\n\r\n  __IO uint32_t               NbSectorsToErase;   /* Internal variable to save the remaining sectors to erase in IT context        */\r\n\r\n  __IO uint8_t                VoltageForErase;    /* Internal variable to provide voltage range selected by user in IT context     */\r\n\r\n  __IO uint32_t               Sector;             /* Internal variable to define the current sector which is erasing               */\r\n\r\n  __IO uint32_t               Address;            /* Internal variable to save address selected for program                        */\r\n\r\n  HAL_LockTypeDef             Lock;               /* FLASH locking object                                                          */\r\n\r\n  __IO uint32_t               ErrorCode;          /* FLASH error code                                                              */\r\n\r\n}FLASH_ProcessTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup FLASH_Exported_Constants FLASH Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup FLASH_Error_Code FLASH Error Code\r\n  * @brief    FLASH Error Code\r\n  * @{\r\n  */\r\n#define HAL_FLASH_ERROR_NONE         ((uint32_t)0x00000000U)    /*!< No error                      */\r\n#define HAL_FLASH_ERROR_ERS          ((uint32_t)0x00000002U)    /*!< Programming Sequence error    */\r\n#define HAL_FLASH_ERROR_PGP          ((uint32_t)0x00000004U)    /*!< Programming Parallelism error */\r\n#define HAL_FLASH_ERROR_PGA          ((uint32_t)0x00000008U)    /*!< Programming Alignment error   */\r\n#define HAL_FLASH_ERROR_WRP          ((uint32_t)0x00000010U)    /*!< Write protection error        */\r\n#define HAL_FLASH_ERROR_OPERATION    ((uint32_t)0x00000020U)    /*!< Operation Error               */\r\n#define HAL_FLASH_ERROR_RD           ((uint32_t)0x00000040U)    /*!< Read Protection Error         */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FLASH_Type_Program FLASH Type Program\r\n  * @{\r\n  */\r\n#define FLASH_TYPEPROGRAM_BYTE        ((uint32_t)0x00U)  /*!< Program byte (8-bit) at a specified address           */\r\n#define FLASH_TYPEPROGRAM_HALFWORD    ((uint32_t)0x01U)  /*!< Program a half-word (16-bit) at a specified address   */\r\n#define FLASH_TYPEPROGRAM_WORD        ((uint32_t)0x02U)  /*!< Program a word (32-bit) at a specified address        */\r\n#define FLASH_TYPEPROGRAM_DOUBLEWORD  ((uint32_t)0x03U)  /*!< Program a double word (64-bit) at a specified address */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FLASH_Flag_definition FLASH Flag definition\r\n  * @brief Flag definition\r\n  * @{\r\n  */\r\n#define FLASH_FLAG_EOP                 FLASH_SR_EOP            /*!< FLASH End of Operation flag               */\r\n#define FLASH_FLAG_OPERR               FLASH_SR_OPERR          /*!< FLASH operation Error flag                */\r\n#define FLASH_FLAG_WRPERR              FLASH_SR_WRPERR         /*!< FLASH Write protected error flag          */\r\n#define FLASH_FLAG_PGAERR              FLASH_SR_PGAERR         /*!< FLASH Programming Alignment error flag    */\r\n#define FLASH_FLAG_PGPERR              FLASH_SR_PGPERR         /*!< FLASH Programming Parallelism error flag  */\r\n#define FLASH_FLAG_ERSERR              FLASH_SR_ERSERR         /*!< FLASH Erasing Sequence error flag         */\r\n#define FLASH_FLAG_BSY                 FLASH_SR_BSY            /*!< FLASH Busy flag                           */\r\n\r\n#if defined (FLASH_OPTCR2_PCROP)\r\n#define FLASH_FLAG_RDERR               FLASH_SR_RDERR          /*!< FLASH Read protection error flag          */\r\n#define FLASH_FLAG_ALL_ERRORS     (FLASH_FLAG_OPERR   | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \\\r\n                                   FLASH_FLAG_PGPERR  | FLASH_FLAG_ERSERR | FLASH_FLAG_RDERR)\r\n#else\r\n#define FLASH_FLAG_ALL_ERRORS     (FLASH_FLAG_OPERR   | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \\\r\n                                   FLASH_FLAG_PGPERR  | FLASH_FLAG_ERSERR)\r\n#endif /* FLASH_OPTCR2_PCROP */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition\r\n  * @brief FLASH Interrupt definition\r\n  * @{\r\n  */\r\n#define FLASH_IT_EOP                   FLASH_CR_EOPIE          /*!< End of FLASH Operation Interrupt source */\r\n#define FLASH_IT_ERR                   ((uint32_t)0x02000000U)  /*!< Error Interrupt source                  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism\r\n  * @{\r\n  */\r\n#define FLASH_PSIZE_BYTE           ((uint32_t)0x00000000U)\r\n#define FLASH_PSIZE_HALF_WORD      ((uint32_t)FLASH_CR_PSIZE_0)\r\n#define FLASH_PSIZE_WORD           ((uint32_t)FLASH_CR_PSIZE_1)\r\n#define FLASH_PSIZE_DOUBLE_WORD    ((uint32_t)FLASH_CR_PSIZE)\r\n#define CR_PSIZE_MASK              ((uint32_t)0xFFFFFCFFU)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FLASH_Keys FLASH Keys\r\n  * @{\r\n  */\r\n#define FLASH_KEY1               ((uint32_t)0x45670123U)\r\n#define FLASH_KEY2               ((uint32_t)0xCDEF89ABU)\r\n#define FLASH_OPT_KEY1           ((uint32_t)0x08192A3BU)\r\n#define FLASH_OPT_KEY2           ((uint32_t)0x4C5D6E7FU)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FLASH_Sectors FLASH Sectors\r\n  * @{\r\n  */\r\n#if (FLASH_SECTOR_TOTAL == 2)\r\n#define FLASH_SECTOR_0           ((uint32_t)0U) /*!< Sector Number 0   */\r\n#define FLASH_SECTOR_1           ((uint32_t)1U) /*!< Sector Number 1   */\r\n#elif (FLASH_SECTOR_TOTAL == 4)\r\n#define FLASH_SECTOR_0           ((uint32_t)0U) /*!< Sector Number 0   */\r\n#define FLASH_SECTOR_1           ((uint32_t)1U) /*!< Sector Number 1   */\r\n#define FLASH_SECTOR_2           ((uint32_t)2U) /*!< Sector Number 2   */\r\n#define FLASH_SECTOR_3           ((uint32_t)3U) /*!< Sector Number 3   */\r\n#else\r\n#define FLASH_SECTOR_0           ((uint32_t)0U) /*!< Sector Number 0   */\r\n#define FLASH_SECTOR_1           ((uint32_t)1U) /*!< Sector Number 1   */\r\n#define FLASH_SECTOR_2           ((uint32_t)2U) /*!< Sector Number 2   */\r\n#define FLASH_SECTOR_3           ((uint32_t)3U) /*!< Sector Number 3   */\r\n#define FLASH_SECTOR_4           ((uint32_t)4U) /*!< Sector Number 4   */\r\n#define FLASH_SECTOR_5           ((uint32_t)5U) /*!< Sector Number 5   */\r\n#define FLASH_SECTOR_6           ((uint32_t)6U) /*!< Sector Number 6   */\r\n#define FLASH_SECTOR_7           ((uint32_t)7U) /*!< Sector Number 7   */\r\n#endif /* FLASH_SECTOR_TOTAL */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup FLASH_Exported_Macros FLASH Exported Macros\r\n  * @{\r\n  */\r\n/**\r\n  * @brief  Set the FLASH Latency.\r\n  * @param  __LATENCY__ FLASH Latency\r\n  *         The value of this parameter depend on device used within the same series\r\n  * @retval none\r\n  */\r\n#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \\\r\n                  MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))\r\n\r\n/**\r\n  * @brief  Get the FLASH Latency.\r\n  * @retval FLASH Latency\r\n  *          The value of this parameter depend on device used within the same series\r\n  */\r\n#define __HAL_FLASH_GET_LATENCY()     (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))\r\n\r\n/**\r\n  * @brief  Enable the FLASH prefetch buffer.\r\n  * @retval none\r\n  */\r\n#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE()  (FLASH->ACR |= FLASH_ACR_PRFTEN)\r\n\r\n/**\r\n  * @brief  Disable the FLASH prefetch buffer.\r\n  * @retval none\r\n  */\r\n#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE()   (FLASH->ACR &= (~FLASH_ACR_PRFTEN))\r\n\r\n/**\r\n  * @brief  Enable the FLASH Adaptive Real-Time memory accelerator.\r\n  * @note   The ART accelerator is available only for flash access on ITCM interface.\r\n  * @retval none\r\n  */\r\n#define __HAL_FLASH_ART_ENABLE()  SET_BIT(FLASH->ACR, FLASH_ACR_ARTEN)\r\n\r\n/**\r\n  * @brief  Disable the FLASH Adaptive Real-Time memory accelerator.\r\n  * @retval none\r\n  */\r\n#define __HAL_FLASH_ART_DISABLE()   CLEAR_BIT(FLASH->ACR, FLASH_ACR_ARTEN)\r\n\r\n/**\r\n  * @brief  Resets the FLASH Adaptive Real-Time memory accelerator.\r\n  * @note   This function must be used only when the Adaptive Real-Time memory accelerator\r\n  *         is disabled.\r\n  * @retval None\r\n  */\r\n#define __HAL_FLASH_ART_RESET()  (FLASH->ACR |= FLASH_ACR_ARTRST)\r\n\r\n/**\r\n  * @brief  Enable the specified FLASH interrupt.\r\n  * @param  __INTERRUPT__  FLASH interrupt\r\n  *         This parameter can be any combination of the following values:\r\n  *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt\r\n  *     @arg FLASH_IT_ERR: Error Interrupt\r\n  * @retval none\r\n  */\r\n#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)  (FLASH->CR |= (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disable the specified FLASH interrupt.\r\n  * @param  __INTERRUPT__  FLASH interrupt\r\n  *         This parameter can be any combination of the following values:\r\n  *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt\r\n  *     @arg FLASH_IT_ERR: Error Interrupt\r\n  * @retval none\r\n  */\r\n#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)  (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Get the specified FLASH flag status.\r\n  * @param  __FLAG__ specifies the FLASH flag to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg FLASH_FLAG_EOP   : FLASH End of Operation flag\r\n  *            @arg FLASH_FLAG_OPERR : FLASH operation Error flag\r\n  *            @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag\r\n  *            @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag\r\n  *            @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag\r\n  *            @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag\r\n  *            @arg FLASH_FLAG_BSY   : FLASH Busy flag\r\n  * @retval The new state of __FLAG__ (SET or RESET).\r\n  */\r\n#define __HAL_FLASH_GET_FLAG(__FLAG__)   ((FLASH->SR & (__FLAG__)))\r\n\r\n/**\r\n  * @brief  Clear the specified FLASH flag.\r\n  * @param  __FLAG__ specifies the FLASH flags to clear.\r\n  *          This parameter can be any combination of the following values:\r\n  *            @arg FLASH_FLAG_EOP   : FLASH End of Operation flag\r\n  *            @arg FLASH_FLAG_OPERR : FLASH operation Error flag\r\n  *            @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag\r\n  *            @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag\r\n  *            @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag\r\n  *            @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag\r\n  * @retval none\r\n  */\r\n#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)   (FLASH->SR = (__FLAG__))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Include FLASH HAL Extension module */\r\n#include \"stm32f7xx_hal_flash_ex.h\"\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup FLASH_Exported_Functions\r\n  * @{\r\n  */\r\n/** @addtogroup FLASH_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n/* Program operation functions  ***********************************************/\r\nHAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);\r\nHAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);\r\n/* FLASH IRQ handler method */\r\nvoid HAL_FLASH_IRQHandler(void);\r\n/* Callbacks in non blocking modes */\r\nvoid HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);\r\nvoid HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup FLASH_Exported_Functions_Group2\r\n  * @{\r\n  */\r\n/* Peripheral Control functions  **********************************************/\r\nHAL_StatusTypeDef HAL_FLASH_Unlock(void);\r\nHAL_StatusTypeDef HAL_FLASH_Lock(void);\r\nHAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);\r\nHAL_StatusTypeDef HAL_FLASH_OB_Lock(void);\r\n/* Option bytes control */\r\nHAL_StatusTypeDef HAL_FLASH_OB_Launch(void);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup FLASH_Exported_Functions_Group3\r\n  * @{\r\n  */\r\n/* Peripheral State functions  ************************************************/\r\nuint32_t HAL_FLASH_GetError(void);\r\nHAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @defgroup FLASH_Private_Variables FLASH Private Variables\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup FLASH_Private_Constants FLASH Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief   OPTCR register byte 1 (Bits[15:8]) base address\r\n  */\r\n#define OPTCR_BYTE1_ADDRESS         ((uint32_t)0x40023C15)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup FLASH_Private_Macros FLASH Private Macros\r\n  * @{\r\n  */\r\n\r\n/** @defgroup FLASH_IS_FLASH_Definitions FLASH Private macros to check input parameters\r\n  * @{\r\n  */\r\n#define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \\\r\n                                    ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \\\r\n                                    ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \\\r\n                                    ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup FLASH_Private_Functions FLASH Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_FLASH_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_flash_ex.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of FLASH HAL Extension module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_FLASH_EX_H\r\n#define __STM32F7xx_HAL_FLASH_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup FLASHEx\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup FLASHEx_Exported_Types FLASH Exported Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  FLASH Erase structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t TypeErase;   /*!< Mass erase or sector Erase.\r\n                             This parameter can be a value of @ref FLASHEx_Type_Erase */\r\n\r\n#if defined (FLASH_OPTCR_nDBANK)\r\n  uint32_t Banks;       /*!< Select banks to erase when Mass erase is enabled.\r\n                             This parameter must be a value of @ref FLASHEx_Banks */\r\n#endif /* FLASH_OPTCR_nDBANK */\r\n\r\n  uint32_t Sector;      /*!< Initial FLASH sector to erase when Mass erase is disabled\r\n                             This parameter must be a value of @ref FLASHEx_Sectors */\r\n\r\n  uint32_t NbSectors;   /*!< Number of sectors to be erased.\r\n                             This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/\r\n\r\n  uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism\r\n                             This parameter must be a value of @ref FLASHEx_Voltage_Range */\r\n\r\n} FLASH_EraseInitTypeDef;\r\n\r\n/**\r\n  * @brief  FLASH Option Bytes Program structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t OptionType;   /*!< Option byte to be configured.\r\n                              This parameter can be a value of @ref FLASHEx_Option_Type */\r\n\r\n  uint32_t WRPState;     /*!< Write protection activation or deactivation.\r\n                              This parameter can be a value of @ref FLASHEx_WRP_State */\r\n\r\n  uint32_t WRPSector;    /*!< Specifies the sector(s) to be write protected.\r\n                              The value of this parameter depend on device used within the same series */\r\n\r\n  uint32_t RDPLevel;     /*!< Set the read protection level.\r\n                              This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */\r\n\r\n  uint32_t BORLevel;     /*!< Set the BOR Level.\r\n                              This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */\r\n\r\n  uint32_t USERConfig;   /*!< Program the FLASH User Option Byte: WWDG_SW / IWDG_SW / RST_STOP / RST_STDBY /\r\n                              IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / nDBANK / nDBOOT.\r\n                              nDBANK / nDBOOT are only available for STM32F76xxx/STM32F77xxx devices */\r\n\r\n  uint32_t BootAddr0;    /*!< Boot base address when Boot pin = 0.\r\n                              This parameter can be a value of @ref FLASHEx_Boot_Address */\r\n\r\n  uint32_t BootAddr1;    /*!< Boot base address when Boot pin = 1.\r\n                              This parameter can be a value of @ref FLASHEx_Boot_Address */\r\n\r\n#if defined (FLASH_OPTCR2_PCROP)\r\n  uint32_t PCROPSector;  /*!< Set the PCROP sector.\r\n                              This parameter can be a value of @ref FLASHEx_Option_Bytes_PCROP_Sectors */\r\n\r\n  uint32_t PCROPRdp;    /*!< Set the PCROP_RDP option.\r\n                              This parameter can be a value of @ref FLASHEx_Option_Bytes_PCROP_RDP */\r\n#endif /* FLASH_OPTCR2_PCROP */\r\n\r\n} FLASH_OBProgramInitTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup FLASHEx_Type_Erase FLASH Type Erase\r\n  * @{\r\n  */\r\n#define FLASH_TYPEERASE_SECTORS         ((uint32_t)0x00U)  /*!< Sectors erase only          */\r\n#define FLASH_TYPEERASE_MASSERASE       ((uint32_t)0x01U)  /*!< Flash Mass erase activation */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range\r\n  * @{\r\n  */\r\n#define FLASH_VOLTAGE_RANGE_1        ((uint32_t)0x00U)  /*!< Device operating range: 1.8V to 2.1V                */\r\n#define FLASH_VOLTAGE_RANGE_2        ((uint32_t)0x01U)  /*!< Device operating range: 2.1V to 2.7V                */\r\n#define FLASH_VOLTAGE_RANGE_3        ((uint32_t)0x02U)  /*!< Device operating range: 2.7V to 3.6V                */\r\n#define FLASH_VOLTAGE_RANGE_4        ((uint32_t)0x03U)  /*!< Device operating range: 2.7V to 3.6V + External Vpp */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FLASHEx_WRP_State FLASH WRP State\r\n  * @{\r\n  */\r\n#define OB_WRPSTATE_DISABLE       ((uint32_t)0x00U)  /*!< Disable the write protection of the desired bank 1 sectors */\r\n#define OB_WRPSTATE_ENABLE        ((uint32_t)0x01U)  /*!< Enable the write protection of the desired bank 1 sectors  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FLASHEx_Option_Type FLASH Option Type\r\n  * @{\r\n  */\r\n#define OPTIONBYTE_WRP         ((uint32_t)0x01U)  /*!< WRP option byte configuration  */\r\n#define OPTIONBYTE_RDP         ((uint32_t)0x02U)  /*!< RDP option byte configuration  */\r\n#define OPTIONBYTE_USER        ((uint32_t)0x04U)  /*!< USER option byte configuration */\r\n#define OPTIONBYTE_BOR         ((uint32_t)0x08U)  /*!< BOR option byte configuration  */\r\n#define OPTIONBYTE_BOOTADDR_0  ((uint32_t)0x10U)  /*!< Boot 0 Address configuration   */\r\n#define OPTIONBYTE_BOOTADDR_1  ((uint32_t)0x20U)  /*!< Boot 1 Address configuration   */\r\n#if defined (FLASH_OPTCR2_PCROP)\r\n#define OPTIONBYTE_PCROP       ((uint32_t)0x40U)  /*!< PCROP configuration            */\r\n#define OPTIONBYTE_PCROP_RDP   ((uint32_t)0x80U)  /*!< PCROP_RDP configuration        */\r\n#endif /* FLASH_OPTCR2_PCROP */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection\r\n  * @{\r\n  */\r\n#define OB_RDP_LEVEL_0       ((uint8_t)0xAAU)\r\n#define OB_RDP_LEVEL_1       ((uint8_t)0x55U)\r\n#define OB_RDP_LEVEL_2       ((uint8_t)0xCCU)   /*!< Warning: When enabling read protection level 2\r\n                                                  it s no more possible to go back to level 1 or 0 */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog\r\n  * @{\r\n  */\r\n#define OB_WWDG_SW           ((uint32_t)0x10U)  /*!< Software WWDG selected */\r\n#define OB_WWDG_HW           ((uint32_t)0x00U)  /*!< Hardware WWDG selected */\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog\r\n  * @{\r\n  */\r\n#define OB_IWDG_SW           ((uint32_t)0x20U)  /*!< Software IWDG selected */\r\n#define OB_IWDG_HW           ((uint32_t)0x00U)  /*!< Hardware IWDG selected */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP\r\n  * @{\r\n  */\r\n#define OB_STOP_NO_RST       ((uint32_t)0x40U) /*!< No reset generated when entering in STOP */\r\n#define OB_STOP_RST          ((uint32_t)0x00U) /*!< Reset generated when entering in STOP    */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY\r\n  * @{\r\n  */\r\n#define OB_STDBY_NO_RST      ((uint32_t)0x80U) /*!< No reset generated when entering in STANDBY */\r\n#define OB_STDBY_RST         ((uint32_t)0x00U) /*!< Reset generated when entering in STANDBY    */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP\r\n  * @{\r\n  */\r\n#define OB_IWDG_STOP_FREEZE      ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STOP mode */\r\n#define OB_IWDG_STOP_ACTIVE      ((uint32_t)0x80000000U) /*!< IWDG counter active in STOP mode */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY\r\n  * @{\r\n  */\r\n#define OB_IWDG_STDBY_FREEZE      ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STANDBY mode */\r\n#define OB_IWDG_STDBY_ACTIVE      ((uint32_t)0x40000000U) /*!< IWDG counter active in STANDBY mode */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level\r\n  * @{\r\n  */\r\n#define OB_BOR_LEVEL3          ((uint32_t)0x00U)  /*!< Supply voltage ranges from 2.70 to 3.60 V */\r\n#define OB_BOR_LEVEL2          ((uint32_t)0x04U)  /*!< Supply voltage ranges from 2.40 to 2.70 V */\r\n#define OB_BOR_LEVEL1          ((uint32_t)0x08U)  /*!< Supply voltage ranges from 2.10 to 2.40 V */\r\n#define OB_BOR_OFF             ((uint32_t)0x0CU)  /*!< Supply voltage ranges from 1.62 to 2.10 V */\r\n/**\r\n  * @}\r\n  */\r\n\r\n#if defined (FLASH_OPTCR_nDBOOT)\r\n/** @defgroup FLASHEx_Option_Bytes_nDBOOT FLASH Option Bytes nDBOOT\r\n  * @{\r\n  */\r\n#define OB_DUAL_BOOT_DISABLE      ((uint32_t)0x10000000U) /* !< Dual Boot disable. Boot according to boot address option */\r\n#define OB_DUAL_BOOT_ENABLE       ((uint32_t)0x00000000U) /* !< Dual Boot enable. Boot always from system memory if boot address in flash\r\n                                                              (Dual bank Boot mode), or RAM if Boot address option in RAM    */\r\n/**\r\n  * @}\r\n  */\r\n#endif /* FLASH_OPTCR_nDBOOT */\r\n\r\n#if defined (FLASH_OPTCR_nDBANK)\r\n/** @defgroup FLASHEx_Option_Bytes_nDBank FLASH Single Bank or Dual Bank\r\n  * @{\r\n  */\r\n#define OB_NDBANK_SINGLE_BANK      ((uint32_t)0x20000000U) /*!< NDBANK bit is set : Single Bank mode */\r\n#define OB_NDBANK_DUAL_BANK        ((uint32_t)0x00000000U) /*!< NDBANK bit is reset : Dual Bank mode */\r\n/**\r\n  * @}\r\n  */\r\n#endif /* FLASH_OPTCR_nDBANK */\r\n\r\n/** @defgroup FLASHEx_Boot_Address FLASH Boot Address\r\n  * @{\r\n  */\r\n#define OB_BOOTADDR_ITCM_RAM         ((uint32_t)0x0000U)  /*!< Boot from ITCM RAM (0x00000000)                 */\r\n#define OB_BOOTADDR_SYSTEM           ((uint32_t)0x0040U)  /*!< Boot from System memory bootloader (0x00100000) */\r\n#define OB_BOOTADDR_ITCM_FLASH       ((uint32_t)0x0080U)  /*!< Boot from Flash on ITCM interface (0x00200000)  */\r\n#define OB_BOOTADDR_AXIM_FLASH       ((uint32_t)0x2000U)  /*!< Boot from Flash on AXIM interface (0x08000000)  */\r\n#define OB_BOOTADDR_DTCM_RAM         ((uint32_t)0x8000U)  /*!< Boot from DTCM RAM (0x20000000)                 */\r\n#define OB_BOOTADDR_SRAM1            ((uint32_t)0x8004U)  /*!< Boot from SRAM1 (0x20010000)                    */\r\n#if (SRAM2_BASE == 0x2003C000U)\r\n#define OB_BOOTADDR_SRAM2            ((uint32_t)0x800FU)  /*!< Boot from SRAM2 (0x2003C000)                    */\r\n#else\r\n#define OB_BOOTADDR_SRAM2            ((uint32_t)0x8013U)  /*!< Boot from SRAM2 (0x2004C000)                    */\r\n#endif /* SRAM2_BASE == 0x2003C000U */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FLASH_Latency FLASH Latency\r\n  * @{\r\n  */\r\n#define FLASH_LATENCY_0                FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero Latency cycle      */\r\n#define FLASH_LATENCY_1                FLASH_ACR_LATENCY_1WS   /*!< FLASH One Latency cycle       */\r\n#define FLASH_LATENCY_2                FLASH_ACR_LATENCY_2WS   /*!< FLASH Two Latency cycles      */\r\n#define FLASH_LATENCY_3                FLASH_ACR_LATENCY_3WS   /*!< FLASH Three Latency cycles    */\r\n#define FLASH_LATENCY_4                FLASH_ACR_LATENCY_4WS   /*!< FLASH Four Latency cycles     */\r\n#define FLASH_LATENCY_5                FLASH_ACR_LATENCY_5WS   /*!< FLASH Five Latency cycles     */\r\n#define FLASH_LATENCY_6                FLASH_ACR_LATENCY_6WS   /*!< FLASH Six Latency cycles      */\r\n#define FLASH_LATENCY_7                FLASH_ACR_LATENCY_7WS   /*!< FLASH Seven Latency cycles    */\r\n#define FLASH_LATENCY_8                FLASH_ACR_LATENCY_8WS   /*!< FLASH Eight Latency cycles    */\r\n#define FLASH_LATENCY_9                FLASH_ACR_LATENCY_9WS   /*!< FLASH Nine Latency cycles     */\r\n#define FLASH_LATENCY_10               FLASH_ACR_LATENCY_10WS  /*!< FLASH Ten Latency cycles      */\r\n#define FLASH_LATENCY_11               FLASH_ACR_LATENCY_11WS  /*!< FLASH Eleven Latency cycles   */\r\n#define FLASH_LATENCY_12               FLASH_ACR_LATENCY_12WS  /*!< FLASH Twelve Latency cycles   */\r\n#define FLASH_LATENCY_13               FLASH_ACR_LATENCY_13WS  /*!< FLASH Thirteen Latency cycles */\r\n#define FLASH_LATENCY_14               FLASH_ACR_LATENCY_14WS  /*!< FLASH Fourteen Latency cycles */\r\n#define FLASH_LATENCY_15               FLASH_ACR_LATENCY_15WS  /*!< FLASH Fifteen Latency cycles  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n#if defined (FLASH_OPTCR_nDBANK)\r\n/** @defgroup FLASHEx_Banks FLASH Banks\r\n  * @{\r\n  */\r\n#define FLASH_BANK_1                       ((uint32_t)0x01U)                          /*!< Bank 1   */\r\n#define FLASH_BANK_2                       ((uint32_t)0x02U)                          /*!< Bank 2   */\r\n#define FLASH_BANK_BOTH                    ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2  */\r\n/**\r\n  * @}\r\n  */\r\n#endif /* FLASH_OPTCR_nDBANK */\r\n\r\n/** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit\r\n  * @{\r\n  */\r\n#if defined (FLASH_OPTCR_nDBANK)\r\n#define FLASH_MER_BIT     (FLASH_CR_MER1 | FLASH_CR_MER2) /*!< 2 MER bits */\r\n#else\r\n#define FLASH_MER_BIT     (FLASH_CR_MER) /*!< only 1 MER bit */\r\n#endif /* FLASH_OPTCR_nDBANK */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FLASHEx_Sectors FLASH Sectors\r\n  * @{\r\n  */\r\n#if (FLASH_SECTOR_TOTAL == 24)\r\n#define FLASH_SECTOR_8     ((uint32_t)8U)  /*!< Sector Number 8   */\r\n#define FLASH_SECTOR_9     ((uint32_t)9U)  /*!< Sector Number 9   */\r\n#define FLASH_SECTOR_10    ((uint32_t)10U) /*!< Sector Number 10  */\r\n#define FLASH_SECTOR_11    ((uint32_t)11U) /*!< Sector Number 11  */\r\n#define FLASH_SECTOR_12    ((uint32_t)12U) /*!< Sector Number 12  */\r\n#define FLASH_SECTOR_13    ((uint32_t)13U) /*!< Sector Number 13  */\r\n#define FLASH_SECTOR_14    ((uint32_t)14U) /*!< Sector Number 14  */\r\n#define FLASH_SECTOR_15    ((uint32_t)15U) /*!< Sector Number 15  */\r\n#define FLASH_SECTOR_16    ((uint32_t)16U) /*!< Sector Number 16  */\r\n#define FLASH_SECTOR_17    ((uint32_t)17U) /*!< Sector Number 17  */\r\n#define FLASH_SECTOR_18    ((uint32_t)18U) /*!< Sector Number 18  */\r\n#define FLASH_SECTOR_19    ((uint32_t)19U) /*!< Sector Number 19  */\r\n#define FLASH_SECTOR_20    ((uint32_t)20U) /*!< Sector Number 20  */\r\n#define FLASH_SECTOR_21    ((uint32_t)21U) /*!< Sector Number 21  */\r\n#define FLASH_SECTOR_22    ((uint32_t)22U) /*!< Sector Number 22  */\r\n#define FLASH_SECTOR_23    ((uint32_t)23U) /*!< Sector Number 23  */\r\n#endif /* FLASH_SECTOR_TOTAL == 24 */\r\n/**\r\n  * @}\r\n  */\r\n\r\n#if (FLASH_SECTOR_TOTAL == 24)\r\n/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection\r\n  * @note For Single Bank mode, use OB_WRP_SECTOR_x defines: In fact, in FLASH_OPTCR register,\r\n  *       nWRP[11:0] bits contain the value of the write-protection option bytes for sectors 0 to 11.\r\n  *       For Dual Bank mode, use OB_WRP_DB_SECTOR_x defines: In fact, in FLASH_OPTCR register,\r\n  *       nWRP[11:0] bits are divided on two groups, one group dedicated for bank 1 and\r\n  *       a second one dedicated for bank 2 (nWRP[i] activates Write protection on sector 2*i and 2*i+1).\r\n  *       This behavior is applicable only for STM32F76xxx / STM32F77xxx devices.\r\n  * @{\r\n  */\r\n/* Single Bank Sectors */\r\n#define OB_WRP_SECTOR_0       ((uint32_t)0x00010000U) /*!< Write protection of Single Bank Sector0   */\r\n#define OB_WRP_SECTOR_1       ((uint32_t)0x00020000U) /*!< Write protection of Single Bank Sector1   */\r\n#define OB_WRP_SECTOR_2       ((uint32_t)0x00040000U) /*!< Write protection of Single Bank Sector2   */\r\n#define OB_WRP_SECTOR_3       ((uint32_t)0x00080000U) /*!< Write protection of Single Bank Sector3   */\r\n#define OB_WRP_SECTOR_4       ((uint32_t)0x00100000U) /*!< Write protection of Single Bank Sector4   */\r\n#define OB_WRP_SECTOR_5       ((uint32_t)0x00200000U) /*!< Write protection of Single Bank Sector5   */\r\n#define OB_WRP_SECTOR_6       ((uint32_t)0x00400000U) /*!< Write protection of Single Bank Sector6   */\r\n#define OB_WRP_SECTOR_7       ((uint32_t)0x00800000U) /*!< Write protection of Single Bank Sector7   */\r\n#define OB_WRP_SECTOR_8       ((uint32_t)0x01000000U) /*!< Write protection of Single Bank Sector8   */\r\n#define OB_WRP_SECTOR_9       ((uint32_t)0x02000000U) /*!< Write protection of Single Bank Sector9   */\r\n#define OB_WRP_SECTOR_10      ((uint32_t)0x04000000U) /*!< Write protection of Single Bank Sector10  */\r\n#define OB_WRP_SECTOR_11      ((uint32_t)0x08000000U) /*!< Write protection of Single Bank Sector11  */\r\n#define OB_WRP_SECTOR_All     ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Single Bank Flash */\r\n\r\n/* Dual Bank Sectors */\r\n#define OB_WRP_DB_SECTOR_0    ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector0     */\r\n#define OB_WRP_DB_SECTOR_1    ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector1     */\r\n#define OB_WRP_DB_SECTOR_2    ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector2     */\r\n#define OB_WRP_DB_SECTOR_3    ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector3     */\r\n#define OB_WRP_DB_SECTOR_4    ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector4     */\r\n#define OB_WRP_DB_SECTOR_5    ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector5     */\r\n#define OB_WRP_DB_SECTOR_6    ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector6     */\r\n#define OB_WRP_DB_SECTOR_7    ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector7     */\r\n#define OB_WRP_DB_SECTOR_8    ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector8     */\r\n#define OB_WRP_DB_SECTOR_9    ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector9     */\r\n#define OB_WRP_DB_SECTOR_10   ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector10    */\r\n#define OB_WRP_DB_SECTOR_11   ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector11    */\r\n#define OB_WRP_DB_SECTOR_12   ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector12    */\r\n#define OB_WRP_DB_SECTOR_13   ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector13    */\r\n#define OB_WRP_DB_SECTOR_14   ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector14    */\r\n#define OB_WRP_DB_SECTOR_15   ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector15    */\r\n#define OB_WRP_DB_SECTOR_16   ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector16    */\r\n#define OB_WRP_DB_SECTOR_17   ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector17    */\r\n#define OB_WRP_DB_SECTOR_18   ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector18    */\r\n#define OB_WRP_DB_SECTOR_19   ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector19    */\r\n#define OB_WRP_DB_SECTOR_20   ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector20    */\r\n#define OB_WRP_DB_SECTOR_21   ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector21    */\r\n#define OB_WRP_DB_SECTOR_22   ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector22    */\r\n#define OB_WRP_DB_SECTOR_23   ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector23    */\r\n#define OB_WRP_DB_SECTOR_All  ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Dual Bank Flash */\r\n/**\r\n  * @}\r\n  */\r\n#endif /* FLASH_SECTOR_TOTAL == 24 */\r\n\r\n#if (FLASH_SECTOR_TOTAL == 8)\r\n/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection\r\n  * @{\r\n  */\r\n#define OB_WRP_SECTOR_0       ((uint32_t)0x00010000U) /*!< Write protection of Sector0     */\r\n#define OB_WRP_SECTOR_1       ((uint32_t)0x00020000U) /*!< Write protection of Sector1     */\r\n#define OB_WRP_SECTOR_2       ((uint32_t)0x00040000U) /*!< Write protection of Sector2     */\r\n#define OB_WRP_SECTOR_3       ((uint32_t)0x00080000U) /*!< Write protection of Sector3     */\r\n#define OB_WRP_SECTOR_4       ((uint32_t)0x00100000U) /*!< Write protection of Sector4     */\r\n#define OB_WRP_SECTOR_5       ((uint32_t)0x00200000U) /*!< Write protection of Sector5     */\r\n#define OB_WRP_SECTOR_6       ((uint32_t)0x00400000U) /*!< Write protection of Sector6     */\r\n#define OB_WRP_SECTOR_7       ((uint32_t)0x00800000U) /*!< Write protection of Sector7     */\r\n#define OB_WRP_SECTOR_All     ((uint32_t)0x00FF0000U) /*!< Write protection of all Sectors */\r\n/**\r\n  * @}\r\n  */\r\n#endif /* FLASH_SECTOR_TOTAL == 8 */\r\n\r\n#if (FLASH_SECTOR_TOTAL == 4)\r\n/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection\r\n  * @{\r\n  */\r\n#define OB_WRP_SECTOR_0       ((uint32_t)0x00010000U) /*!< Write protection of Sector0     */\r\n#define OB_WRP_SECTOR_1       ((uint32_t)0x00020000U) /*!< Write protection of Sector1     */\r\n#define OB_WRP_SECTOR_2       ((uint32_t)0x00040000U) /*!< Write protection of Sector2     */\r\n#define OB_WRP_SECTOR_3       ((uint32_t)0x00080000U) /*!< Write protection of Sector3     */\r\n#define OB_WRP_SECTOR_All     ((uint32_t)0x000F0000U) /*!< Write protection of all Sectors */\r\n/**\r\n  * @}\r\n  */\r\n#endif /* FLASH_SECTOR_TOTAL == 4 */\r\n\r\n#if (FLASH_SECTOR_TOTAL == 2)\r\n/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection\r\n  * @{\r\n  */\r\n#define OB_WRP_SECTOR_0       ((uint32_t)0x00010000U) /*!< Write protection of Sector0     */\r\n#define OB_WRP_SECTOR_1       ((uint32_t)0x00020000U) /*!< Write protection of Sector1     */\r\n#define OB_WRP_SECTOR_All     ((uint32_t)0x00030000U) /*!< Write protection of all Sectors */\r\n/**\r\n  * @}\r\n  */\r\n#endif /* FLASH_SECTOR_TOTAL == 2 */\r\n\r\n#if defined (FLASH_OPTCR2_PCROP)\r\n#if (FLASH_SECTOR_TOTAL == 8)\r\n/** @defgroup FLASHEx_Option_Bytes_PCROP_Sectors FLASH Option Bytes PCROP Sectors\r\n  * @{\r\n  */\r\n#define OB_PCROP_SECTOR_0     ((uint32_t)0x00000001U) /*!< PC Readout protection of Sector0      */\r\n#define OB_PCROP_SECTOR_1     ((uint32_t)0x00000002U) /*!< PC Readout protection of Sector1      */\r\n#define OB_PCROP_SECTOR_2     ((uint32_t)0x00000004U) /*!< PC Readout protection of Sector2      */\r\n#define OB_PCROP_SECTOR_3     ((uint32_t)0x00000008U) /*!< PC Readout protection of Sector3      */\r\n#define OB_PCROP_SECTOR_4     ((uint32_t)0x00000010U) /*!< PC Readout protection of Sector4      */\r\n#define OB_PCROP_SECTOR_5     ((uint32_t)0x00000020U) /*!< PC Readout protection of Sector5      */\r\n#define OB_PCROP_SECTOR_6     ((uint32_t)0x00000040U) /*!< PC Readout protection of Sector6      */\r\n#define OB_PCROP_SECTOR_7     ((uint32_t)0x00000080U) /*!< PC Readout protection of Sector7      */\r\n#define OB_PCROP_SECTOR_All   ((uint32_t)0x000000FFU) /*!< PC Readout protection of all Sectors  */\r\n/**\r\n  * @}\r\n  */\r\n#endif /* FLASH_SECTOR_TOTAL == 8 */\r\n\r\n#if (FLASH_SECTOR_TOTAL == 4)\r\n/** @defgroup FLASHEx_Option_Bytes_PCROP_Sectors FLASH Option Bytes PCROP Sectors\r\n  * @{\r\n  */\r\n#define OB_PCROP_SECTOR_0     ((uint32_t)0x00000001U) /*!< PC Readout protection of Sector0      */\r\n#define OB_PCROP_SECTOR_1     ((uint32_t)0x00000002U) /*!< PC Readout protection of Sector1      */\r\n#define OB_PCROP_SECTOR_2     ((uint32_t)0x00000004U) /*!< PC Readout protection of Sector2      */\r\n#define OB_PCROP_SECTOR_3     ((uint32_t)0x00000008U) /*!< PC Readout protection of Sector3      */\r\n#define OB_PCROP_SECTOR_All   ((uint32_t)0x0000000FU) /*!< PC Readout protection of all Sectors  */\r\n/**\r\n  * @}\r\n  */\r\n#endif /* FLASH_SECTOR_TOTAL == 4 */\r\n\r\n/** @defgroup FLASHEx_Option_Bytes_PCROP_RDP FLASH Option Bytes PCROP_RDP Bit\r\n  * @{\r\n  */\r\n#define OB_PCROP_RDP_ENABLE   ((uint32_t)0x80000000U) /*!< PCROP_RDP Enable      */\r\n#define OB_PCROP_RDP_DISABLE  ((uint32_t)0x00000000U) /*!< PCROP_RDP Disable     */\r\n/**\r\n  * @}\r\n  */\r\n#endif /* FLASH_OPTCR2_PCROP */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup FLASH_Exported_Macros FLASH Exported Macros\r\n  * @{\r\n  */\r\n/**\r\n  * @brief  Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1)\r\n  * @note   Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14].\r\n  * @param  __ADDRESS__ FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB)\r\n  * @retval The FLASH Boot Base Adress\r\n  */\r\n#define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14)\r\n /**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup FLASHEx_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup FLASHEx_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n/* Extension Program operation functions  *************************************/\r\nHAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);\r\nHAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);\r\nHAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);\r\nvoid              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup FLASHEx_Private_Macros FLASH Private Macros\r\n  * @{\r\n  */\r\n\r\n/** @defgroup FLASHEx_IS_FLASH_Definitions FLASH Private macros to check input parameters\r\n  * @{\r\n  */\r\n\r\n#define IS_FLASH_TYPEERASE(VALUE)(((VALUE) == FLASH_TYPEERASE_SECTORS) || \\\r\n                                  ((VALUE) == FLASH_TYPEERASE_MASSERASE))\r\n\r\n#define IS_VOLTAGERANGE(RANGE)(((RANGE) == FLASH_VOLTAGE_RANGE_1) || \\\r\n                               ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \\\r\n                               ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \\\r\n                               ((RANGE) == FLASH_VOLTAGE_RANGE_4))\r\n\r\n#define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \\\r\n                           ((VALUE) == OB_WRPSTATE_ENABLE))\r\n\r\n#if defined (FLASH_OPTCR2_PCROP)\r\n#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP        | OPTIONBYTE_USER |\\\r\n                                          OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1 |\\\r\n                                          OPTIONBYTE_PCROP | OPTIONBYTE_PCROP_RDP)))\r\n#else\r\n#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP        | OPTIONBYTE_USER |\\\r\n                                          OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1)))\r\n#endif /* FLASH_OPTCR2_PCROP */\r\n\r\n#define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013)\r\n\r\n#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0)   ||\\\r\n                                ((LEVEL) == OB_RDP_LEVEL_1)   ||\\\r\n                                ((LEVEL) == OB_RDP_LEVEL_2))\r\n\r\n#define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))\r\n\r\n#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))\r\n\r\n#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))\r\n\r\n#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))\r\n\r\n#define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))\r\n\r\n#define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))\r\n\r\n#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\\\r\n                                ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))\r\n\r\n#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0)  || \\\r\n                                   ((LATENCY) == FLASH_LATENCY_1)  || \\\r\n                                   ((LATENCY) == FLASH_LATENCY_2)  || \\\r\n                                   ((LATENCY) == FLASH_LATENCY_3)  || \\\r\n                                   ((LATENCY) == FLASH_LATENCY_4)  || \\\r\n                                   ((LATENCY) == FLASH_LATENCY_5)  || \\\r\n                                   ((LATENCY) == FLASH_LATENCY_6)  || \\\r\n                                   ((LATENCY) == FLASH_LATENCY_7)  || \\\r\n                                   ((LATENCY) == FLASH_LATENCY_8)  || \\\r\n                                   ((LATENCY) == FLASH_LATENCY_9)  || \\\r\n                                   ((LATENCY) == FLASH_LATENCY_10) || \\\r\n                                   ((LATENCY) == FLASH_LATENCY_11) || \\\r\n                                   ((LATENCY) == FLASH_LATENCY_12) || \\\r\n                                   ((LATENCY) == FLASH_LATENCY_13) || \\\r\n                                   ((LATENCY) == FLASH_LATENCY_14) || \\\r\n                                   ((LATENCY) == FLASH_LATENCY_15))\r\n\r\n#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) || \\\r\n                                   (((ADDRESS) >= FLASH_OTP_BASE) && ((ADDRESS) <= FLASH_OTP_END)))\r\n#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))\r\n\r\n#if (FLASH_SECTOR_TOTAL == 8)\r\n#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\\\r\n                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\\\r\n                                 ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\\\r\n                                 ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7))\r\n\r\n#define IS_OB_WRP_SECTOR(SECTOR)  ((((SECTOR) & 0xFF00FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U))\r\n#endif /* FLASH_SECTOR_TOTAL == 8 */\r\n\r\n#if (FLASH_SECTOR_TOTAL == 24)\r\n#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\\\r\n                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\\\r\n                                 ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\\\r\n                                 ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7)   ||\\\r\n                                 ((SECTOR) == FLASH_SECTOR_8)   || ((SECTOR) == FLASH_SECTOR_9)   ||\\\r\n                                 ((SECTOR) == FLASH_SECTOR_10)  || ((SECTOR) == FLASH_SECTOR_11)  ||\\\r\n                                 ((SECTOR) == FLASH_SECTOR_12)  || ((SECTOR) == FLASH_SECTOR_13)  ||\\\r\n                                 ((SECTOR) == FLASH_SECTOR_14)  || ((SECTOR) == FLASH_SECTOR_15)  ||\\\r\n                                 ((SECTOR) == FLASH_SECTOR_16)  || ((SECTOR) == FLASH_SECTOR_17)  ||\\\r\n                                 ((SECTOR) == FLASH_SECTOR_18)  || ((SECTOR) == FLASH_SECTOR_19)  ||\\\r\n                                 ((SECTOR) == FLASH_SECTOR_20)  || ((SECTOR) == FLASH_SECTOR_21)  ||\\\r\n                                 ((SECTOR) == FLASH_SECTOR_22)  || ((SECTOR) == FLASH_SECTOR_23))\r\n\r\n#define IS_OB_WRP_SECTOR(SECTOR)  ((((SECTOR) & 0xF000FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U))\r\n#endif /* FLASH_SECTOR_TOTAL == 24 */\r\n\r\n#if (FLASH_SECTOR_TOTAL == 4)\r\n#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\\\r\n                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3))\r\n\r\n#define IS_OB_WRP_SECTOR(SECTOR)  ((((SECTOR) & 0xFFF0FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U))\r\n#endif /* FLASH_SECTOR_TOTAL == 4 */\r\n\r\n#if (FLASH_SECTOR_TOTAL == 2)\r\n#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1))\r\n\r\n#define IS_OB_WRP_SECTOR(SECTOR)  ((((SECTOR) & 0xFFFCFFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U))\r\n#endif /* FLASH_SECTOR_TOTAL == 2 */\r\n\r\n#if defined (FLASH_OPTCR_nDBANK)\r\n#define IS_OB_NDBANK(VALUE)        (((VALUE) == OB_NDBANK_SINGLE_BANK) || \\\r\n                                    ((VALUE) == OB_NDBANK_DUAL_BANK))\r\n\r\n#define IS_FLASH_BANK(BANK)        (((BANK) == FLASH_BANK_1)  || \\\r\n                                    ((BANK) == FLASH_BANK_2)  || \\\r\n                                    ((BANK) == FLASH_BANK_BOTH))\r\n#endif /* FLASH_OPTCR_nDBANK */\r\n\r\n#if defined (FLASH_OPTCR_nDBOOT)\r\n#define IS_OB_NDBOOT(VALUE)        (((VALUE) == OB_DUAL_BOOT_DISABLE) || \\\r\n                                    ((VALUE) == OB_DUAL_BOOT_ENABLE))\r\n#endif /* FLASH_OPTCR_nDBOOT */\r\n\r\n#if defined (FLASH_OPTCR2_PCROP)\r\n#define IS_OB_PCROP_SECTOR(SECTOR)   (((SECTOR) & (uint32_t)0xFFFFFF00U) == 0x00000000U)\r\n#define IS_OB_PCROP_RDP_VALUE(VALUE) (((VALUE) == OB_PCROP_RDP_DISABLE) || \\\r\n                                      ((VALUE) == OB_PCROP_RDP_ENABLE))\r\n#endif /* FLASH_OPTCR2_PCROP */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup FLASHEx_Private_Functions FLASH Private Functions\r\n  * @{\r\n  */\r\nvoid FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_FLASH_EX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_gpio.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of GPIO HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_GPIO_H\r\n#define __STM32F7xx_HAL_GPIO_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup GPIO\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup GPIO_Exported_Types GPIO Exported Types\r\n  * @{\r\n  */\r\n\r\n/** \r\n  * @brief GPIO Init structure definition  \r\n  */ \r\ntypedef struct\r\n{\r\n  uint32_t Pin;       /*!< Specifies the GPIO pins to be configured.\r\n                           This parameter can be any value of @ref GPIO_pins_define */\r\n\r\n  uint32_t Mode;      /*!< Specifies the operating mode for the selected pins.\r\n                           This parameter can be a value of @ref GPIO_mode_define */\r\n\r\n  uint32_t Pull;      /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.\r\n                           This parameter can be a value of @ref GPIO_pull_define */\r\n\r\n  uint32_t Speed;     /*!< Specifies the speed for the selected pins.\r\n                           This parameter can be a value of @ref GPIO_speed_define */\r\n\r\n  uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins. \r\n                            This parameter can be a value of @ref GPIO_Alternate_function_selection */\r\n}GPIO_InitTypeDef;\r\n\r\n/** \r\n  * @brief  GPIO Bit SET and Bit RESET enumeration \r\n  */\r\ntypedef enum\r\n{\r\n  GPIO_PIN_RESET = 0,\r\n  GPIO_PIN_SET\r\n}GPIO_PinState;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup GPIO_Exported_Constants GPIO Exported Constants\r\n  * @{\r\n  */ \r\n\r\n/** @defgroup GPIO_pins_define GPIO pins define\r\n  * @{\r\n  */\r\n#define GPIO_PIN_0                 ((uint16_t)0x0001U)  /* Pin 0 selected    */\r\n#define GPIO_PIN_1                 ((uint16_t)0x0002U)  /* Pin 1 selected    */\r\n#define GPIO_PIN_2                 ((uint16_t)0x0004U)  /* Pin 2 selected    */\r\n#define GPIO_PIN_3                 ((uint16_t)0x0008U)  /* Pin 3 selected    */\r\n#define GPIO_PIN_4                 ((uint16_t)0x0010U)  /* Pin 4 selected    */\r\n#define GPIO_PIN_5                 ((uint16_t)0x0020U)  /* Pin 5 selected    */\r\n#define GPIO_PIN_6                 ((uint16_t)0x0040U)  /* Pin 6 selected    */\r\n#define GPIO_PIN_7                 ((uint16_t)0x0080U)  /* Pin 7 selected    */\r\n#define GPIO_PIN_8                 ((uint16_t)0x0100U)  /* Pin 8 selected    */\r\n#define GPIO_PIN_9                 ((uint16_t)0x0200U)  /* Pin 9 selected    */\r\n#define GPIO_PIN_10                ((uint16_t)0x0400U)  /* Pin 10 selected   */\r\n#define GPIO_PIN_11                ((uint16_t)0x0800U)  /* Pin 11 selected   */\r\n#define GPIO_PIN_12                ((uint16_t)0x1000U)  /* Pin 12 selected   */\r\n#define GPIO_PIN_13                ((uint16_t)0x2000U)  /* Pin 13 selected   */\r\n#define GPIO_PIN_14                ((uint16_t)0x4000U)  /* Pin 14 selected   */\r\n#define GPIO_PIN_15                ((uint16_t)0x8000U)  /* Pin 15 selected   */\r\n#define GPIO_PIN_All               ((uint16_t)0xFFFFU)  /* All pins selected */\r\n\r\n#define GPIO_PIN_MASK              ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup GPIO_mode_define GPIO mode define\r\n  * @brief GPIO Configuration Mode \r\n  *        Elements values convention: 0xX0yz00YZ\r\n  *           - X  : GPIO mode or EXTI Mode\r\n  *           - y  : External IT or Event trigger detection \r\n  *           - z  : IO configuration on External IT or Event\r\n  *           - Y  : Output type (Push Pull or Open Drain)\r\n  *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)\r\n  * @{\r\n  */ \r\n#define  GPIO_MODE_INPUT                        ((uint32_t)0x00000000U)   /*!< Input Floating Mode                   */\r\n#define  GPIO_MODE_OUTPUT_PP                    ((uint32_t)0x00000001U)   /*!< Output Push Pull Mode                 */\r\n#define  GPIO_MODE_OUTPUT_OD                    ((uint32_t)0x00000011U)   /*!< Output Open Drain Mode                */\r\n#define  GPIO_MODE_AF_PP                        ((uint32_t)0x00000002U)   /*!< Alternate Function Push Pull Mode     */\r\n#define  GPIO_MODE_AF_OD                        ((uint32_t)0x00000012U)   /*!< Alternate Function Open Drain Mode    */\r\n\r\n#define  GPIO_MODE_ANALOG                       ((uint32_t)0x00000003U)   /*!< Analog Mode  */\r\n    \r\n#define  GPIO_MODE_IT_RISING                    ((uint32_t)0x10110000U)   /*!< External Interrupt Mode with Rising edge trigger detection          */\r\n#define  GPIO_MODE_IT_FALLING                   ((uint32_t)0x10210000U)   /*!< External Interrupt Mode with Falling edge trigger detection         */\r\n#define  GPIO_MODE_IT_RISING_FALLING            ((uint32_t)0x10310000U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */\r\n \r\n#define  GPIO_MODE_EVT_RISING                   ((uint32_t)0x10120000U)   /*!< External Event Mode with Rising edge trigger detection               */\r\n#define  GPIO_MODE_EVT_FALLING                  ((uint32_t)0x10220000U)   /*!< External Event Mode with Falling edge trigger detection              */\r\n#define  GPIO_MODE_EVT_RISING_FALLING           ((uint32_t)0x10320000U)   /*!< External Event Mode with Rising/Falling edge trigger detection       */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup GPIO_speed_define  GPIO speed define\r\n  * @brief GPIO Output Maximum frequency\r\n  * @{\r\n  */  \r\n#define  GPIO_SPEED_FREQ_LOW         ((uint32_t)0x00000000U)  /*!< Low speed     */\r\n#define  GPIO_SPEED_FREQ_MEDIUM      ((uint32_t)0x00000001U)  /*!< Medium speed  */\r\n#define  GPIO_SPEED_FREQ_HIGH        ((uint32_t)0x00000002U)  /*!< Fast speed    */\r\n#define  GPIO_SPEED_FREQ_VERY_HIGH   ((uint32_t)0x00000003U)  /*!< High speed    */\r\n/**\r\n  * @}\r\n  */\r\n\r\n /** @defgroup GPIO_pull_define GPIO pull define\r\n   * @brief GPIO Pull-Up or Pull-Down Activation\r\n   * @{\r\n   */  \r\n#define  GPIO_NOPULL        ((uint32_t)0x00000000U)   /*!< No Pull-up or Pull-down activation  */\r\n#define  GPIO_PULLUP        ((uint32_t)0x00000001U)   /*!< Pull-up activation                  */\r\n#define  GPIO_PULLDOWN      ((uint32_t)0x00000002U)   /*!< Pull-down activation                */\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup GPIO_Exported_Macros GPIO Exported Macros\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Checks whether the specified EXTI line flag is set or not.\r\n  * @param  __EXTI_LINE__ specifies the EXTI line flag to check.\r\n  *         This parameter can be GPIO_PIN_x where x can be(0..15)\r\n  * @retval The new state of __EXTI_LINE__ (SET or RESET).\r\n  */\r\n#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))\r\n\r\n/**\r\n  * @brief  Clears the EXTI's line pending flags.\r\n  * @param  __EXTI_LINE__ specifies the EXTI lines flags to clear.\r\n  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)\r\n  * @retval None\r\n  */\r\n#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))\r\n\r\n/**\r\n  * @brief  Checks whether the specified EXTI line is asserted or not.\r\n  * @param  __EXTI_LINE__ specifies the EXTI line to check.\r\n  *          This parameter can be GPIO_PIN_x where x can be(0..15)\r\n  * @retval The new state of __EXTI_LINE__ (SET or RESET).\r\n  */\r\n#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))\r\n\r\n/**\r\n  * @brief  Clears the EXTI's line pending bits.\r\n  * @param  __EXTI_LINE__ specifies the EXTI lines to clear.\r\n  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)\r\n  * @retval None\r\n  */\r\n#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))\r\n\r\n/**\r\n  * @brief  Generates a Software interrupt on selected EXTI line.\r\n  * @param  __EXTI_LINE__ specifies the EXTI line to check.\r\n  *          This parameter can be GPIO_PIN_x where x can be(0..15)\r\n  * @retval None\r\n  */\r\n#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Include GPIO HAL Extension module */\r\n#include \"stm32f7xx_hal_gpio_ex.h\"\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup GPIO_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup GPIO_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n/* Initialization and de-initialization functions *****************************/\r\nvoid  HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);\r\nvoid  HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup GPIO_Exported_Functions_Group2\r\n  * @{\r\n  */\r\n/* IO operation functions *****************************************************/\r\nGPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r\nvoid HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);\r\nvoid HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r\nHAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r\nvoid HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);\r\nvoid HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup GPIO_Private_Constants GPIO Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup GPIO_Private_Macros GPIO Private Macros\r\n  * @{\r\n  */\r\n#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))\r\n#define IS_GPIO_PIN(__PIN__)        ((((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00))\r\n#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT)              ||\\\r\n                            ((MODE) == GPIO_MODE_OUTPUT_PP)          ||\\\r\n                            ((MODE) == GPIO_MODE_OUTPUT_OD)          ||\\\r\n                            ((MODE) == GPIO_MODE_AF_PP)              ||\\\r\n                            ((MODE) == GPIO_MODE_AF_OD)              ||\\\r\n                            ((MODE) == GPIO_MODE_IT_RISING)          ||\\\r\n                            ((MODE) == GPIO_MODE_IT_FALLING)         ||\\\r\n                            ((MODE) == GPIO_MODE_IT_RISING_FALLING)  ||\\\r\n                            ((MODE) == GPIO_MODE_EVT_RISING)         ||\\\r\n                            ((MODE) == GPIO_MODE_EVT_FALLING)        ||\\\r\n                            ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\\\r\n                            ((MODE) == GPIO_MODE_ANALOG))\r\n#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_LOW)  || ((SPEED) == GPIO_SPEED_MEDIUM) || \\\r\n                              ((SPEED) == GPIO_SPEED_FAST) || ((SPEED) == GPIO_SPEED_HIGH))\r\n#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \\\r\n                            ((PULL) == GPIO_PULLDOWN))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup GPIO_Private_Functions GPIO Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_GPIO_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_gpio_ex.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of GPIO HAL Extension module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_GPIO_EX_H\r\n#define __STM32F7xx_HAL_GPIO_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup GPIOEx GPIOEx\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection\r\n  * @{\r\n  */  \r\n/*--------------- STM32F74xxx/STM32F75xxx/STM32F76xxx/STM32F77xxx -------------*/\r\n#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) ||\\\r\n    defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)   \r\n/** \r\n  * @brief   AF 0 selection  \r\n  */ \r\n#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */\r\n#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\r\n#define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\r\n#define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */\r\n\r\n/** \r\n  * @brief   AF 1 selection  \r\n  */ \r\n#define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */\r\n#define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */\r\n#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r\n#define GPIO_AF1_UART5         ((uint8_t)0x01U)  /* UART5 Alternate Function mapping */\r\n#define GPIO_AF1_I2C4          ((uint8_t)0x01U)  /* I2C4 Alternate Function mapping  */   \r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n/** \r\n  * @brief   AF 2 selection  \r\n  */ \r\n#define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */\r\n#define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */\r\n#define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */\r\n\r\n/** \r\n  * @brief   AF 3 selection  \r\n  */ \r\n#define GPIO_AF3_TIM8          ((uint8_t)0x03U)  /* TIM8 Alternate Function mapping  */\r\n#define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */\r\n#define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */\r\n#define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */\r\n#define GPIO_AF3_LPTIM1        ((uint8_t)0x03U)  /* LPTIM1 Alternate Function mapping */\r\n#define GPIO_AF3_CEC           ((uint8_t)0x03U)  /* CEC Alternate Function mapping */\r\n#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r\n#define GPIO_AF3_DFSDM1         ((uint8_t)0x03U)  /* DFSDM1 Alternate Function mapping */\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n/** \r\n  * @brief   AF 4 selection  \r\n  */ \r\n#define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */\r\n#define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */\r\n#define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping */\r\n#define GPIO_AF4_I2C4          ((uint8_t)0x04U)  /* I2C4 Alternate Function mapping */\r\n#define GPIO_AF4_CEC           ((uint8_t)0x04U)  /* CEC Alternate Function mapping */\r\n#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r\n#define GPIO_AF4_USART1        ((uint8_t)0x04)  /* USART1 Alternate Function mapping */\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */   \r\n\r\n/** \r\n  * @brief   AF 5 selection  \r\n  */ \r\n#define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1 Alternate Function mapping        */\r\n#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */\r\n#define GPIO_AF5_SPI3          ((uint8_t)0x05U)  /* SPI3/I2S3 Alternate Function mapping   */\r\n#define GPIO_AF5_SPI4          ((uint8_t)0x05U)  /* SPI4 Alternate Function mapping        */\r\n#define GPIO_AF5_SPI5          ((uint8_t)0x05U)  /* SPI5 Alternate Function mapping        */\r\n#define GPIO_AF5_SPI6          ((uint8_t)0x05U)  /* SPI6 Alternate Function mapping        */\r\n\r\n/** \r\n  * @brief   AF 6 selection  \r\n  */ \r\n#define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */\r\n#define GPIO_AF6_SAI1          ((uint8_t)0x06U)  /* SAI1 Alternate Function mapping       */\r\n#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r\n#define GPIO_AF6_UART4         ((uint8_t)0x06U)   /* UART4 Alternate Function mapping     */   \r\n#define GPIO_AF6_DFSDM1        ((uint8_t)0x06U)  /* DFSDM1 Alternate Function mapping     */\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */   \r\n\r\n/** \r\n  * @brief   AF 7 selection  \r\n  */ \r\n#define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */\r\n#define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */\r\n#define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping     */\r\n#define GPIO_AF7_UART5         ((uint8_t)0x07U)  /* UART5 Alternate Function mapping      */\r\n#define GPIO_AF7_SPDIFRX       ((uint8_t)0x07U)  /* SPDIF-RX Alternate Function mapping   */\r\n#define GPIO_AF7_SPI2          ((uint8_t)0x07U)  /* SPI2 Alternate Function mapping       */\r\n#define GPIO_AF7_SPI3          ((uint8_t)0x07U)  /* SPI3 Alternate Function mapping       */\r\n#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r\n#define GPIO_AF7_SPI6          ((uint8_t)0x07U)  /* SPI6 Alternate Function mapping       */\r\n#define GPIO_AF7_DFSDM1         ((uint8_t)0x07U) /* DFSDM1 Alternate Function mapping      */\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */  \r\n\r\n/** \r\n  * @brief   AF 8 selection  \r\n  */ \r\n#define GPIO_AF8_UART4         ((uint8_t)0x08U)  /* UART4 Alternate Function mapping  */\r\n#define GPIO_AF8_UART5         ((uint8_t)0x08U)  /* UART5 Alternate Function mapping  */\r\n#define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */\r\n#define GPIO_AF8_UART7         ((uint8_t)0x08U)  /* UART7 Alternate Function mapping  */\r\n#define GPIO_AF8_UART8         ((uint8_t)0x08U)  /* UART8 Alternate Function mapping  */\r\n#define GPIO_AF8_SPDIFRX       ((uint8_t)0x08U)  /* SPIDIF-RX Alternate Function mapping */\r\n#define GPIO_AF8_SAI2          ((uint8_t)0x08U)  /* SAI2 Alternate Function mapping   */\r\n#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r\n#define GPIO_AF8_SPI6          ((uint8_t)0x08U)  /* SPI6 Alternate Function mapping   */  \r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */    \r\n\r\n\r\n/** \r\n  * @brief   AF 9 selection \r\n  */ \r\n#define GPIO_AF9_CAN1          ((uint8_t)0x09U)  /* CAN1 Alternate Function mapping    */\r\n#define GPIO_AF9_CAN2          ((uint8_t)0x09U)  /* CAN2 Alternate Function mapping    */\r\n#define GPIO_AF9_TIM12         ((uint8_t)0x09U)  /* TIM12 Alternate Function mapping   */\r\n#define GPIO_AF9_TIM13         ((uint8_t)0x09U)  /* TIM13 Alternate Function mapping   */\r\n#define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping   */\r\n#define GPIO_AF9_QUADSPI       ((uint8_t)0x09U)  /* QUADSPI Alternate Function mapping */\r\n#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F750xx)\r\n#define GPIO_AF9_LTDC          ((uint8_t)0x09U)  /* LCD-TFT Alternate Function mapping */\r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F765xx) || defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F750xx)\r\n#define GPIO_AF9_FMC           ((uint8_t)0x09U)   /* FMC Alternate Function mapping     */\r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n/** \r\n  * @brief   AF 10 selection  \r\n  */ \r\n#define GPIO_AF10_OTG_FS        ((uint8_t)0xAU)  /* OTG_FS Alternate Function mapping */\r\n#define GPIO_AF10_OTG_HS        ((uint8_t)0xAU)  /* OTG_HS Alternate Function mapping */\r\n#define GPIO_AF10_QUADSPI       ((uint8_t)0xAU)  /* QUADSPI Alternate Function mapping */\r\n#define GPIO_AF10_SAI2          ((uint8_t)0xAU)  /* SAI2 Alternate Function mapping */\r\n#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r\n#define GPIO_AF10_DFSDM1         ((uint8_t)0x0AU)  /* DFSDM1 Alternate Function mapping  */\r\n#define GPIO_AF10_SDMMC2         ((uint8_t)0x0AU)  /* SDMMC2 Alternate Function mapping */   \r\n#define GPIO_AF10_LTDC           ((uint8_t)0x0AU)  /* LCD-TFT Alternate Function mapping */\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */   \r\n\r\n/** \r\n  * @brief   AF 11 selection  \r\n  */ \r\n#define GPIO_AF11_ETH           ((uint8_t)0x0BU)  /* ETHERNET Alternate Function mapping */\r\n#if defined(STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define GPIO_AF11_CAN3          ((uint8_t)0x0BU)  /* CAN3 Alternate Function mapping     */\r\n#define GPIO_AF11_SDMMC2        ((uint8_t)0x0BU)  /* SDMMC2 Alternate Function mapping   */\r\n#define GPIO_AF11_I2C4          ((uint8_t)0x0BU)  /* I2C4 Alternate Function mapping     */   \r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n   \r\n/** \r\n  * @brief   AF 12 selection  \r\n  */ \r\n#define GPIO_AF12_FMC           ((uint8_t)0xCU)  /* FMC Alternate Function mapping                      */\r\n#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0xCU)  /* OTG HS configured in FS, Alternate Function mapping */\r\n#define GPIO_AF12_SDMMC1        ((uint8_t)0xCU)  /* SDMMC1 Alternate Function mapping                   */\r\n#if defined(STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)   \r\n#define GPIO_AF12_MDIOS        ((uint8_t)0xCU)  /* SDMMC1 Alternate Function mapping                    */\r\n#define GPIO_AF12_UART7        ((uint8_t)0xCU)  /* UART7 Alternate Function mapping                     */   \r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n   \r\n/** \r\n  * @brief   AF 13 selection  \r\n  */ \r\n#define GPIO_AF13_DCMI          ((uint8_t)0x0DU)  /* DCMI Alternate Function mapping */\r\n#if defined (STM32F769xx) || defined (STM32F779xx)   \r\n#define GPIO_AF13_DSI           ((uint8_t)0x0DU)  /* DSI Alternate Function mapping  */\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */   \r\n#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F750xx)\r\n#define GPIO_AF13_LTDC          ((uint8_t)0x0DU)  /* LTDC Alternate Function mapping */   \r\n   \r\n/** \r\n  * @brief   AF 14 selection  \r\n  */\r\n#define GPIO_AF14_LTDC          ((uint8_t)0x0EU)  /* LCD-TFT Alternate Function mapping */\r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n/** \r\n  * @brief   AF 15 selection  \r\n  */ \r\n#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */\r\n#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n/*----------------------------------------------------------------------------*/\r\n\r\n/*---------------------------- STM32F72xxx/STM32F73xxx -----------------------*/      \r\n#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F732xx) || defined(STM32F733xx) || defined(STM32F730xx)\r\n /** \r\n  * @brief   AF 0 selection  \r\n  */ \r\n#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */\r\n#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\r\n#define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\r\n#define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */\r\n\r\n/** \r\n  * @brief   AF 1 selection  \r\n  */ \r\n#define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */\r\n#define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */\r\n\r\n/** \r\n  * @brief   AF 2 selection  \r\n  */ \r\n#define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */\r\n#define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */\r\n#define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */\r\n\r\n/** \r\n  * @brief   AF 3 selection  \r\n  */ \r\n#define GPIO_AF3_TIM8          ((uint8_t)0x03U)  /* TIM8 Alternate Function mapping  */\r\n#define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */\r\n#define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */\r\n#define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */\r\n#define GPIO_AF3_LPTIM1        ((uint8_t)0x03U)  /* LPTIM1 Alternate Function mapping */\r\n\r\n/** \r\n  * @brief   AF 4 selection  \r\n  */ \r\n#define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */\r\n#define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */\r\n#define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping */ \r\n\r\n/** \r\n  * @brief   AF 5 selection  \r\n  */ \r\n#define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1 Alternate Function mapping        */\r\n#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */\r\n#define GPIO_AF5_SPI3          ((uint8_t)0x05U)  /* SPI3/I2S3 Alternate Function mapping   */\r\n#define GPIO_AF5_SPI4          ((uint8_t)0x05U)  /* SPI4 Alternate Function mapping        */\r\n#define GPIO_AF5_SPI5          ((uint8_t)0x05U)  /* SPI5 Alternate Function mapping        */\r\n\r\n/** \r\n  * @brief   AF 6 selection  \r\n  */ \r\n#define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */\r\n#define GPIO_AF6_SAI1          ((uint8_t)0x06U)  /* SAI1 Alternate Function mapping       */\r\n\r\n/** \r\n  * @brief   AF 7 selection  \r\n  */ \r\n#define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */\r\n#define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */\r\n#define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping     */\r\n#define GPIO_AF7_UART5         ((uint8_t)0x07U)  /* UART5 Alternate Function mapping      */\r\n#define GPIO_AF7_SPI2          ((uint8_t)0x07U)  /* SPI2 Alternate Function mapping       */\r\n#define GPIO_AF7_SPI3          ((uint8_t)0x07U)  /* SPI3 Alternate Function mapping       */ \r\n\r\n/** \r\n  * @brief   AF 8 selection  \r\n  */ \r\n#define GPIO_AF8_UART4         ((uint8_t)0x08U)  /* UART4 Alternate Function mapping  */\r\n#define GPIO_AF8_UART5         ((uint8_t)0x08U)  /* UART5 Alternate Function mapping  */\r\n#define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */\r\n#define GPIO_AF8_UART7         ((uint8_t)0x08U)  /* UART7 Alternate Function mapping  */\r\n#define GPIO_AF8_UART8         ((uint8_t)0x08U)  /* UART8 Alternate Function mapping  */\r\n#define GPIO_AF8_SAI2          ((uint8_t)0x08U)  /* SAI2 Alternate Function mapping   */\r\n\r\n/** \r\n  * @brief   AF 9 selection \r\n  */ \r\n#define GPIO_AF9_CAN1          ((uint8_t)0x09U)  /* CAN1 Alternate Function mapping    */\r\n#define GPIO_AF9_TIM12         ((uint8_t)0x09U)  /* TIM12 Alternate Function mapping   */\r\n#define GPIO_AF9_TIM13         ((uint8_t)0x09U)  /* TIM13 Alternate Function mapping   */\r\n#define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping   */\r\n#define GPIO_AF9_QUADSPI       ((uint8_t)0x09U)  /* QUADSPI Alternate Function mapping */\r\n\r\n/** \r\n  * @brief   AF 10 selection  \r\n  */ \r\n#define GPIO_AF10_OTG_FS        ((uint8_t)0xAU)  /* OTG_FS Alternate Function mapping */\r\n#define GPIO_AF10_OTG_HS        ((uint8_t)0xAU)  /* OTG_HS Alternate Function mapping */\r\n#define GPIO_AF10_QUADSPI       ((uint8_t)0xAU)  /* QUADSPI Alternate Function mapping */\r\n#define GPIO_AF10_SAI2          ((uint8_t)0xAU)  /* SAI2 Alternate Function mapping */\r\n#define GPIO_AF10_SDMMC2        ((uint8_t)0x0AU) /* SDMMC2 Alternate Function mapping */   \r\n\r\n/** \r\n  * @brief   AF 11 selection  \r\n  */ \r\n#define GPIO_AF11_SDMMC2        ((uint8_t)0x0BU) /* SDMMC2 Alternate Function mapping   */\r\n   \r\n/** \r\n  * @brief   AF 12 selection  \r\n  */ \r\n#define GPIO_AF12_FMC           ((uint8_t)0xCU)  /* FMC Alternate Function mapping                      */\r\n#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0xCU)  /* OTG HS configured in FS, Alternate Function mapping */\r\n#define GPIO_AF12_SDMMC1        ((uint8_t)0xCU)  /* SDMMC1 Alternate Function mapping                   */\r\n   \r\n/** \r\n  * @brief   AF 13 selection  \r\n  */ \r\n#define GPIO_AF13_RNG           ((uint8_t)0x0DU)  /* RNG Alternate Function mapping */   \r\n   \r\n/** \r\n  * @brief   AF 15 selection  \r\n  */ \r\n#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */     \r\n#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */\r\n/*----------------------------------------------------------------------------*/\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros\r\n  * @{\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/ \r\n/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions\r\n  * @{\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup GPIOEx_Private_Constants GPIO Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief   GPIO pin available on the platform\r\n  */\r\n/* Defines the available pins per GPIOs */\r\n#define GPIOA_PIN_AVAILABLE  GPIO_PIN_All\r\n#define GPIOB_PIN_AVAILABLE  GPIO_PIN_All\r\n#define GPIOC_PIN_AVAILABLE  GPIO_PIN_All\r\n#define GPIOD_PIN_AVAILABLE  GPIO_PIN_All\r\n#define GPIOE_PIN_AVAILABLE  GPIO_PIN_All\r\n#define GPIOF_PIN_AVAILABLE  GPIO_PIN_All\r\n#define GPIOG_PIN_AVAILABLE  GPIO_PIN_All\r\n#define GPIOI_PIN_AVAILABLE  GPIO_PIN_All\r\n#define GPIOJ_PIN_AVAILABLE  GPIO_PIN_All\r\n#define GPIOH_PIN_AVAILABLE  GPIO_PIN_All\r\n#define GPIOK_PIN_AVAILABLE  (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | \\\r\n                              GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup GPIOEx_Private_Macros GPIO Private Macros\r\n  * @{\r\n  */\r\n/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index\r\n  * @{\r\n  */\r\n#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\\r\n    defined (STM32F750xx)\r\n#define GPIO_GET_INDEX(__GPIOx__)   (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\\\r\n                                              ((__GPIOx__) == (GPIOB))? 1U :\\\r\n                                              ((__GPIOx__) == (GPIOC))? 2U :\\\r\n                                              ((__GPIOx__) == (GPIOD))? 3U :\\\r\n                                              ((__GPIOx__) == (GPIOE))? 4U :\\\r\n                                              ((__GPIOx__) == (GPIOF))? 5U :\\\r\n                                              ((__GPIOx__) == (GPIOG))? 6U :\\\r\n                                              ((__GPIOx__) == (GPIOH))? 7U :\\\r\n                                              ((__GPIOx__) == (GPIOI))? 8U :\\\r\n                                              ((__GPIOx__) == (GPIOJ))? 9U : 10U)\r\n#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n\r\n#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)\r\n#define GPIO_GET_INDEX(__GPIOx__)   (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\\\r\n                                              ((__GPIOx__) == (GPIOB))? 1U :\\\r\n                                              ((__GPIOx__) == (GPIOC))? 2U :\\\r\n                                              ((__GPIOx__) == (GPIOD))? 3U :\\\r\n                                              ((__GPIOx__) == (GPIOE))? 4U :\\\r\n                                              ((__GPIOx__) == (GPIOF))? 5U :\\\r\n                                              ((__GPIOx__) == (GPIOG))? 6U :\\\r\n                                              ((__GPIOx__) == (GPIOH))? 7U : 8U)\r\n#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */\r\n/**\r\n  * @}\r\n  */\r\n\r\n#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__)  \\\r\n           ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \\\r\n            (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \\\r\n            (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \\\r\n            (((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))) || \\\r\n            (((__INSTANCE__) == GPIOE) && (((__PIN__) & (GPIOE_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOE_PIN_AVAILABLE)) == (GPIOE_PIN_AVAILABLE))) || \\\r\n            (((__INSTANCE__) == GPIOF) && (((__PIN__) & (GPIOF_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOF_PIN_AVAILABLE)) == (GPIOF_PIN_AVAILABLE))) || \\\r\n\t\t\t(((__INSTANCE__) == GPIOG) && (((__PIN__) & (GPIOG_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOG_PIN_AVAILABLE)) == (GPIOG_PIN_AVAILABLE))) || \\\r\n\t\t\t(((__INSTANCE__) == GPIOI) && (((__PIN__) & (GPIOI_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOI_PIN_AVAILABLE)) == (GPIOI_PIN_AVAILABLE))) || \\\r\n\t\t\t(((__INSTANCE__) == GPIOJ) && (((__PIN__) & (GPIOJ_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOJ_PIN_AVAILABLE)) == (GPIOJ_PIN_AVAILABLE))) || \\\r\n\t\t\t(((__INSTANCE__) == GPIOK) && (((__PIN__) & (GPIOK_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOK_PIN_AVAILABLE)) == (GPIOK_PIN_AVAILABLE))) || \\\r\n\t\t\t(((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE))))\r\n/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function\r\n  * @{\r\n  */\r\n#if defined(STM32F756xx) || defined(STM32F746xx)  || defined(STM32F750xx)\r\n#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF1_TIM1)        || \\\r\n                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \\\r\n                          ((AF) == GPIO_AF0_MCO)       || ((AF) == GPIO_AF1_TIM2)       || \\\r\n                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \\\r\n                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \\\r\n                          ((AF) == GPIO_AF3_TIM9)       || ((AF) == GPIO_AF3_TIM10)      || \\\r\n                          ((AF) == GPIO_AF3_TIM11)      || ((AF) == GPIO_AF3_LPTIM1)     || \\\r\n                          ((AF) == GPIO_AF3_CEC)        || ((AF) == GPIO_AF4_CEC)        || \\\r\n                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \\\r\n                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF4_I2C4)       || \\\r\n                          ((AF) == GPIO_AF5_SPI1)       || ((AF) == GPIO_AF5_SPI2)       || \\\r\n                          ((AF) == GPIO_AF5_SPI3)       || ((AF) == GPIO_AF5_SPI4)       || \\\r\n                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \\\r\n                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF6_SAI1)       || \\\r\n                          ((AF) == GPIO_AF7_SPI3)       || ((AF) == GPIO_AF7_SPI2)        || \\\r\n                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)      || \\\r\n                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF7_UART5)       || \\\r\n                          ((AF) == GPIO_AF7_SPDIFRX)    || ((AF) == GPIO_AF8_SPDIFRX)     || \\\r\n                          ((AF) == GPIO_AF8_SAI2)       || ((AF) == GPIO_AF8_USART6)      || \\\r\n                          ((AF) == GPIO_AF8_UART4)      || ((AF) == GPIO_AF8_UART5)       || \\\r\n                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)       || \\\r\n                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)        || \\\r\n                          ((AF) == GPIO_AF9_TIM12)      || ((AF) == GPIO_AF9_TIM12)      || \\\r\n                          ((AF) == GPIO_AF9_TIM14)      || ((AF) == GPIO_AF9_QUADSPI)    || \\\r\n                          ((AF) == GPIO_AF9_LTDC)       || ((AF) == GPIO_AF10_OTG_FS)    || \\\r\n                          ((AF) == GPIO_AF10_OTG_HS)    || ((AF) == GPIO_AF10_SAI2)      || \\\r\n                          ((AF) == GPIO_AF10_QUADSPI)   || ((AF) == GPIO_AF11_ETH)       || \\\r\n                          ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1)     || \\\r\n                          ((AF) == GPIO_AF12_FMC)       || ((AF) == GPIO_AF15_EVENTOUT)  || \\\r\n                          ((AF) == GPIO_AF13_DCMI)      || ((AF) == GPIO_AF14_LTDC))\r\n#elif defined(STM32F745xx)\r\n#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF1_TIM1)       || \\\r\n                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \\\r\n                          ((AF) == GPIO_AF0_MCO)       || ((AF) == GPIO_AF1_TIM2)        || \\\r\n                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \\\r\n                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \\\r\n                          ((AF) == GPIO_AF3_TIM9)       || ((AF) == GPIO_AF3_TIM10)      || \\\r\n                          ((AF) == GPIO_AF3_TIM11)      || ((AF) == GPIO_AF3_LPTIM1)     || \\\r\n                          ((AF) == GPIO_AF3_CEC)        || ((AF) == GPIO_AF4_CEC)        || \\\r\n                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \\\r\n                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF4_I2C4)       || \\\r\n                          ((AF) == GPIO_AF5_SPI1)       || ((AF) == GPIO_AF5_SPI2)       || \\\r\n                          ((AF) == GPIO_AF5_SPI3)       || ((AF) == GPIO_AF5_SPI4)       || \\\r\n                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \\\r\n                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF6_SAI1)       || \\\r\n                          ((AF) == GPIO_AF7_SPI3)       || ((AF) == GPIO_AF7_SPI2)        || \\\r\n                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)      || \\\r\n                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF7_UART5)       || \\\r\n                          ((AF) == GPIO_AF7_SPDIFRX)    || ((AF) == GPIO_AF8_SPDIFRX)     || \\\r\n                          ((AF) == GPIO_AF8_SAI2)       || ((AF) == GPIO_AF8_USART6)      || \\\r\n                          ((AF) == GPIO_AF8_UART4)      || ((AF) == GPIO_AF8_UART5)       || \\\r\n                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)       || \\\r\n                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)        || \\\r\n                          ((AF) == GPIO_AF9_TIM12)      || ((AF) == GPIO_AF9_TIM12)      || \\\r\n                          ((AF) == GPIO_AF9_TIM14)      || ((AF) == GPIO_AF9_QUADSPI)    || \\\r\n                          ((AF) == GPIO_AF13_DCMI)      || ((AF) == GPIO_AF10_OTG_FS)    || \\\r\n                          ((AF) == GPIO_AF10_OTG_HS)    || ((AF) == GPIO_AF10_SAI2)      || \\\r\n                          ((AF) == GPIO_AF10_QUADSPI)   || ((AF) == GPIO_AF11_ETH)       || \\\r\n                          ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1)    || \\\r\n                          ((AF) == GPIO_AF12_FMC)       || ((AF) == GPIO_AF15_EVENTOUT))\r\n#elif defined(STM32F767xx) || defined(STM32F777xx)\r\n#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF1_TIM1)        || \\\r\n                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \\\r\n                          ((AF) == GPIO_AF0_MCO)       || ((AF) == GPIO_AF1_TIM2)       || \\\r\n                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \\\r\n                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \\\r\n                          ((AF) == GPIO_AF3_TIM9)       || ((AF) == GPIO_AF3_TIM10)      || \\\r\n                          ((AF) == GPIO_AF3_TIM11)      || ((AF) == GPIO_AF3_LPTIM1)     || \\\r\n                          ((AF) == GPIO_AF3_CEC)        || ((AF) == GPIO_AF4_CEC)        || \\\r\n                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \\\r\n                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF4_I2C4)       || \\\r\n                          ((AF) == GPIO_AF5_SPI1)       || ((AF) == GPIO_AF5_SPI2)       || \\\r\n                          ((AF) == GPIO_AF5_SPI3)       || ((AF) == GPIO_AF5_SPI4)       || \\\r\n                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \\\r\n                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF6_SAI1)       || \\\r\n                          ((AF) == GPIO_AF7_SPI3)       || ((AF) == GPIO_AF7_SPI2)       || \\\r\n                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \\\r\n                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF7_UART5)      || \\\r\n                          ((AF) == GPIO_AF7_SPDIFRX)    || ((AF) == GPIO_AF8_SPDIFRX)    || \\\r\n                          ((AF) == GPIO_AF8_SAI2)       || ((AF) == GPIO_AF8_USART6)     || \\\r\n                          ((AF) == GPIO_AF8_UART4)      || ((AF) == GPIO_AF8_UART5)      || \\\r\n                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \\\r\n                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \\\r\n                          ((AF) == GPIO_AF9_TIM12)      || ((AF) == GPIO_AF9_TIM12)      || \\\r\n                          ((AF) == GPIO_AF9_TIM14)      || ((AF) == GPIO_AF9_QUADSPI)    || \\\r\n                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF9_LTDC)       || \\\r\n                          ((AF) == GPIO_AF10_OTG_HS)    || ((AF) == GPIO_AF10_SAI2)      || \\\r\n                          ((AF) == GPIO_AF10_QUADSPI)   || ((AF) == GPIO_AF11_ETH)       || \\\r\n                          ((AF) == GPIO_AF10_SDMMC2)    || ((AF) == GPIO_AF11_SDMMC2)    || \\\r\n                          ((AF) == GPIO_AF11_CAN3)      || ((AF) == GPIO_AF12_OTG_HS_FS) || \\\r\n                          ((AF) == GPIO_AF12_SDMMC1)    || ((AF) == GPIO_AF12_FMC)       || \\\r\n                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF13_DCMI)      || \\\r\n\t\t                  ((AF) == GPIO_AF14_LTDC))\r\n#elif defined(STM32F769xx) || defined(STM32F779xx)\r\n#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF1_TIM1)        || \\\r\n                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \\\r\n                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF1_TIM2)       || \\\r\n                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \\\r\n                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \\\r\n                          ((AF) == GPIO_AF3_TIM9)       || ((AF) == GPIO_AF3_TIM10)      || \\\r\n                          ((AF) == GPIO_AF3_TIM11)      || ((AF) == GPIO_AF3_LPTIM1)     || \\\r\n                          ((AF) == GPIO_AF3_CEC)        || ((AF) == GPIO_AF4_CEC)        || \\\r\n                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \\\r\n                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF4_I2C4)       || \\\r\n                          ((AF) == GPIO_AF5_SPI1)       || ((AF) == GPIO_AF5_SPI2)       || \\\r\n                          ((AF) == GPIO_AF5_SPI3)       || ((AF) == GPIO_AF5_SPI4)       || \\\r\n                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \\\r\n                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF6_SAI1)       || \\\r\n                          ((AF) == GPIO_AF7_SPI3)       || ((AF) == GPIO_AF7_SPI2)       || \\\r\n                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \\\r\n                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF7_UART5)      || \\\r\n                          ((AF) == GPIO_AF7_SPDIFRX)    || ((AF) == GPIO_AF8_SPDIFRX)    || \\\r\n                          ((AF) == GPIO_AF8_SAI2)       || ((AF) == GPIO_AF8_USART6)     || \\\r\n                          ((AF) == GPIO_AF8_UART4)      || ((AF) == GPIO_AF8_UART5)      || \\\r\n                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \\\r\n                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \\\r\n                          ((AF) == GPIO_AF9_TIM12)      || ((AF) == GPIO_AF9_TIM12)      || \\\r\n                          ((AF) == GPIO_AF9_TIM14)      || ((AF) == GPIO_AF9_QUADSPI)    || \\\r\n                          ((AF) == GPIO_AF9_LTDC)       || ((AF) == GPIO_AF10_OTG_FS)    || \\\r\n                          ((AF) == GPIO_AF10_OTG_HS)    || ((AF) == GPIO_AF10_SAI2)      || \\\r\n                          ((AF) == GPIO_AF10_QUADSPI)   || ((AF) == GPIO_AF11_ETH)       || \\\r\n                          ((AF) == GPIO_AF10_SDMMC2)    || ((AF) == GPIO_AF11_SDMMC2)    || \\\r\n                          ((AF) == GPIO_AF11_CAN3)      || ((AF) == GPIO_AF12_OTG_HS_FS) || \\\r\n                          ((AF) == GPIO_AF12_SDMMC1)    || ((AF) == GPIO_AF12_FMC)       || \\\r\n                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF13_DCMI)      || \\\r\n                          ((AF) == GPIO_AF14_LTDC)      || ((AF) == GPIO_AF13_DSI))\r\n#elif defined(STM32F765xx)\r\n#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF1_TIM1)        || \\\r\n                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \\\r\n                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF1_TIM2)       || \\\r\n                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \\\r\n                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \\\r\n                          ((AF) == GPIO_AF3_TIM9)       || ((AF) == GPIO_AF3_TIM10)      || \\\r\n                          ((AF) == GPIO_AF3_TIM11)      || ((AF) == GPIO_AF3_LPTIM1)     || \\\r\n                          ((AF) == GPIO_AF3_CEC)        || ((AF) == GPIO_AF4_CEC)        || \\\r\n                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \\\r\n                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF4_I2C4)       || \\\r\n                          ((AF) == GPIO_AF5_SPI1)       || ((AF) == GPIO_AF5_SPI2)       || \\\r\n                          ((AF) == GPIO_AF5_SPI3)       || ((AF) == GPIO_AF5_SPI4)       || \\\r\n                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \\\r\n                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF6_SAI1)       || \\\r\n                          ((AF) == GPIO_AF7_SPI3)       || ((AF) == GPIO_AF7_SPI2)       || \\\r\n                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \\\r\n                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF7_UART5)      || \\\r\n                          ((AF) == GPIO_AF7_SPDIFRX)    || ((AF) == GPIO_AF8_SPDIFRX)    || \\\r\n                          ((AF) == GPIO_AF8_SAI2)       || ((AF) == GPIO_AF8_USART6)     || \\\r\n                          ((AF) == GPIO_AF8_UART4)      || ((AF) == GPIO_AF8_UART5)      || \\\r\n                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \\\r\n                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \\\r\n                          ((AF) == GPIO_AF9_TIM12)      || ((AF) == GPIO_AF9_TIM12)      || \\\r\n                          ((AF) == GPIO_AF9_TIM14)      || ((AF) == GPIO_AF9_QUADSPI)    || \\\r\n                          ((AF) == GPIO_AF10_OTG_HS)    || ((AF) == GPIO_AF10_SAI2)      || \\\r\n                          ((AF) == GPIO_AF10_QUADSPI)   || ((AF) == GPIO_AF11_ETH)       || \\\r\n                          ((AF) == GPIO_AF10_SDMMC2)    || ((AF) == GPIO_AF11_SDMMC2)    || \\\r\n                          ((AF) == GPIO_AF11_CAN3)      || ((AF) == GPIO_AF12_OTG_HS_FS) || \\\r\n                          ((AF) == GPIO_AF12_SDMMC1)    || ((AF) == GPIO_AF12_FMC)       || \\\r\n                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF13_DCMI)      || \\\r\n                          ((AF) == GPIO_AF10_OTG_FS))\r\n#elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)\r\n#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF1_TIM1)        || \\\r\n                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \\\r\n                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF1_TIM2)       || \\\r\n                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \\\r\n                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \\\r\n                          ((AF) == GPIO_AF3_TIM9)       || ((AF) == GPIO_AF3_TIM10)      || \\\r\n                          ((AF) == GPIO_AF3_TIM11)      || ((AF) == GPIO_AF3_LPTIM1)     || \\\r\n                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \\\r\n                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \\\r\n                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF5_SPI3)       || \\\r\n                          ((AF) == GPIO_AF5_SPI4)       || ((AF) == GPIO_AF5_SPI5)       || \\\r\n                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF6_SAI1)       || \\\r\n                          ((AF) == GPIO_AF7_SPI3)       || ((AF) == GPIO_AF7_SPI2)       || \\\r\n                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \\\r\n                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF7_UART5)      || \\\r\n                          ((AF) == GPIO_AF8_SAI2)       || ((AF) == GPIO_AF8_USART6)     || \\\r\n                          ((AF) == GPIO_AF8_UART4)      || ((AF) == GPIO_AF8_UART5)      || \\\r\n                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \\\r\n                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_TIM12)      || \\\r\n                          ((AF) == GPIO_AF9_TIM12)      || ((AF) == GPIO_AF9_TIM14)      || \\\r\n                          ((AF) == GPIO_AF9_QUADSPI)    || ((AF) == GPIO_AF10_OTG_HS)    || \\\r\n                          ((AF) == GPIO_AF10_SAI2)      || ((AF) == GPIO_AF10_QUADSPI)   || \\\r\n                          ((AF) == GPIO_AF10_SDMMC2)    || ((AF) == GPIO_AF11_SDMMC2)    || \\\r\n                          ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1)    || \\\r\n                          ((AF) == GPIO_AF12_FMC)       || ((AF) == GPIO_AF15_EVENTOUT)  || \\\r\n                          ((AF) == GPIO_AF10_OTG_FS))\r\n#endif /* STM32F756xx || STM32F746xx || STM32F750xx */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup GPIOEx_Private_Functions GPIO Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_GPIO_EX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_hash.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of HASH HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_HASH_H\r\n#define __STM32F7xx_HAL_HASH_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup HASH    \r\n  * @brief HASH HAL module driver \r\n  *  @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup HASH_Exported_Types HASH Exported Types\r\n  * @{\r\n  */\r\n\r\n/** @defgroup HASH_Exported_Types_Group1 HASH Configuration Structure definition\r\n  * @{\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  uint32_t DataType;  /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.\r\n                           This parameter can be a value of @ref HASH_Data_Type */\r\n\r\n  uint32_t KeySize;   /*!< The key size is used only in HMAC operation          */\r\n\r\n  uint8_t* pKey;      /*!< The key is used only in HMAC operation               */\r\n}HASH_InitTypeDef;\r\n\r\n/** \r\n  * @}\r\n  */\r\n\r\n/** @defgroup HASH_Exported_Types_Group2 HASH State structures definition\r\n  * @{\r\n  */\r\n\r\ntypedef enum\r\n{\r\n  HAL_HASH_STATE_RESET     = 0x00U,  /*!< HASH not yet initialized or disabled */\r\n  HAL_HASH_STATE_READY     = 0x01U,  /*!< HASH initialized and ready for use   */\r\n  HAL_HASH_STATE_BUSY      = 0x02U,  /*!< HASH internal process is ongoing     */\r\n  HAL_HASH_STATE_TIMEOUT   = 0x03U,  /*!< HASH timeout state                   */\r\n  HAL_HASH_STATE_ERROR     = 0x04U   /*!< HASH error state                     */\r\n}HAL_HASH_StateTypeDef;\r\n\r\n/** \r\n  * @}\r\n  */\r\n  \r\n/** @defgroup HASH_Exported_Types_Group3 HASH phase structures definition\r\n  * @{\r\n  */\r\n  \r\ntypedef enum\r\n{\r\n  HAL_HASH_PHASE_READY     = 0x01U,  /*!< HASH peripheral is ready for initialization */\r\n  HAL_HASH_PHASE_PROCESS   = 0x02U,  /*!< HASH peripheral is in processing phase      */\r\n}HAL_HASHPhaseTypeDef;\r\n\r\n/** \r\n  * @}\r\n  */\r\n \r\n/** @defgroup HASH_Exported_Types_Group4 HASH Handle structures definition\r\n  * @{\r\n  */ \r\n  \r\ntypedef struct\r\n{\r\n      HASH_InitTypeDef           Init;              /*!< HASH required parameters       */\r\n\r\n      uint8_t                    *pHashInBuffPtr;   /*!< Pointer to input buffer        */\r\n\r\n      uint8_t                    *pHashOutBuffPtr;  /*!< Pointer to input buffer        */\r\n\r\n     __IO uint32_t               HashBuffSize;      /*!< Size of buffer to be processed */\r\n\r\n     __IO uint32_t               HashInCount;       /*!< Counter of inputed data        */\r\n\r\n     __IO uint32_t               HashITCounter;     /*!< Counter of issued interrupts   */\r\n\r\n      HAL_StatusTypeDef          Status;            /*!< HASH peripheral status         */\r\n\r\n      HAL_HASH_PhaseTypeDef       Phase;             /*!< HASH peripheral phase          */\r\n\r\n      DMA_HandleTypeDef          *hdmain;           /*!< HASH In DMA handle parameters  */\r\n\r\n      HAL_LockTypeDef            Lock;              /*!< HASH locking object            */\r\n\r\n     __IO HAL_HASH_StateTypeDef  State;             /*!< HASH peripheral state          */\r\n} HASH_HandleTypeDef;\r\n\r\n/** \r\n  * @}\r\n  */\r\n  \r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup HASH_Exported_Constants HASH Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup HASH_Exported_Constants_Group1 HASH Algorithm Selection\r\n  * @{\r\n  */\r\n#define HASH_ALGOSELECTION_SHA1      ((uint32_t)0x0000U)  /*!< HASH function is SHA1   */\r\n#define HASH_ALGOSELECTION_SHA224    HASH_CR_ALGO_1      /*!< HASH function is SHA224 */\r\n#define HASH_ALGOSELECTION_SHA256    HASH_CR_ALGO        /*!< HASH function is SHA256 */\r\n#define HASH_ALGOSELECTION_MD5       HASH_CR_ALGO_0      /*!< HASH function is MD5    */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HASH_Exported_Constants_Group2 HASH Algorithm Mode\r\n  * @{\r\n  */\r\n#define HASH_ALGOMODE_HASH         ((uint32_t)0x00000000U)  /*!< Algorithm is HASH */ \r\n#define HASH_ALGOMODE_HMAC         HASH_CR_MODE            /*!< Algorithm is HMAC */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HASH_Data_Type HASH Data Type\r\n  * @{\r\n  */\r\n#define HASH_DATATYPE_32B          ((uint32_t)0x0000U) /*!< 32-bit data. No swapping                     */\r\n#define HASH_DATATYPE_16B          HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped       */\r\n#define HASH_DATATYPE_8B           HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped            */\r\n#define HASH_DATATYPE_1B           HASH_CR_DATATYPE   /*!< 1-bit data. In the word all bits are swapped */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HASH_Exported_Constants_Group4 HASH HMAC Long key \r\n  * @brief HASH HMAC Long key used only for HMAC mode\r\n  * @{\r\n  */\r\n#define HASH_HMAC_KEYTYPE_SHORTKEY      ((uint32_t)0x00000000U)  /*!< HMAC Key is <= 64 bytes */\r\n#define HASH_HMAC_KEYTYPE_LONGKEY       HASH_CR_LKEY            /*!< HMAC Key is > 64 bytes  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HASH_Exported_Constants_Group5 HASH Flags definition \r\n  * @{\r\n  */\r\n#define HASH_FLAG_DINIS            HASH_SR_DINIS  /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer */\r\n#define HASH_FLAG_DCIS             HASH_SR_DCIS   /*!< Digest calculation complete                                                         */\r\n#define HASH_FLAG_DMAS             HASH_SR_DMAS   /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing                          */\r\n#define HASH_FLAG_BUSY             HASH_SR_BUSY   /*!< The hash core is Busy : processing a block of data                                  */\r\n#define HASH_FLAG_DINNE            HASH_CR_DINNE  /*!< DIN not empty : The input buffer contains at least one word of data                 */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HASH_Exported_Constants_Group6 HASH Interrupts definition \r\n  * @{\r\n  */\r\n#define HASH_IT_DINI               HASH_IMR_DINIE  /*!< A new block can be entered into the input buffer (DIN) */\r\n#define HASH_IT_DCI                HASH_IMR_DCIE   /*!< Digest calculation complete                            */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup HASH_Exported_Macros HASH Exported Macros\r\n  * @{\r\n  */\r\n  \r\n/** @brief Reset HASH handle state\r\n  * @param  __HANDLE__ specifies the HASH handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)\r\n\r\n/** @brief  Check whether the specified HASH flag is set or not.\r\n  * @param  __FLAG__ specifies the flag to check.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg HASH_FLAG_DINIS: A new block can be entered into the input buffer. \r\n  *            @arg HASH_FLAG_DCIS: Digest calculation complete\r\n  *            @arg HASH_FLAG_DMAS: DMA interface is enabled (DMAE=1) or a transfer is ongoing\r\n  *            @arg HASH_FLAG_BUSY: The hash core is Busy : processing a block of data\r\n  *            @arg HASH_FLAG_DINNE: DIN not empty : The input buffer contains at least one word of data\r\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\\\r\n                                                           ((HASH->SR & (__FLAG__)) == (__FLAG__)))\r\n\r\n/**\r\n  * @brief  Enable the multiple DMA mode. \r\n  *         This feature is available only in STM32F429x and STM32F439x devices.\r\n  * @retval None\r\n  */\r\n#define __HAL_HASH_SET_MDMAT()          HASH->CR |= HASH_CR_MDMAT\r\n\r\n/**\r\n  * @brief  Disable the multiple DMA mode.\r\n  * @retval None\r\n  */\r\n#define __HAL_HASH_RESET_MDMAT()        HASH->CR &= (uint32_t)(~HASH_CR_MDMAT)\r\n\r\n/**\r\n  * @brief  Start the digest computation\r\n  * @retval None\r\n  */\r\n#define __HAL_HASH_START_DIGEST()       HASH->STR |= HASH_STR_DCAL\r\n\r\n/**\r\n  * @brief Set the number of valid bits in last word written in Data register\r\n  * @param  SIZE size in byte of last data written in Data register.\r\n  * @retval None\r\n*/\r\n#define __HAL_HASH_SET_NBVALIDBITS(SIZE) do{HASH->STR &= ~(HASH_STR_NBW);\\\r\n                                            HASH->STR |= 8 * ((SIZE) % 4);\\\r\n                                           }while(0)\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Include HASH HAL Extension module */\r\n#include \"stm32f7xx_hal_hash_ex.h\"\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @defgroup HASH_Exported_Functions HASH Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup HASH_Exported_Functions_Group1\r\n  * @{\r\n  */  \r\nHAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash);\r\nHAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @addtogroup HASH_Exported_Functions_Group2\r\n  * @{\r\n  */  \r\nHAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r\nHAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/** @addtogroup HASH_Exported_Functions_Group3\r\n  * @{\r\n  */  \r\nHAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @addtogroup HASH_Exported_Functions_Group4\r\n  * @{\r\n  */  \r\nHAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);\r\nHAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @addtogroup HASH_Exported_Functions_Group5\r\n  * @{\r\n  */    \r\nHAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r\nHAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r\nHAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @addtogroup HASH_Exported_Functions_Group6\r\n  * @{\r\n  */  \r\nHAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r\nHAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @addtogroup HASH_Exported_Functions_Group7\r\n  * @{\r\n  */  \r\nvoid HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @addtogroup HASH_Exported_Functions_Group8\r\n  * @{\r\n  */\r\nHAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);\r\nvoid HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);\r\nvoid HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);\r\nvoid HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);\r\nvoid HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);\r\nvoid HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n /**\r\n  * @}\r\n  */ \r\n \r\n /* Private types -------------------------------------------------------------*/\r\n/** @defgroup HASH_Private_Types HASH Private Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @defgroup HASH_Private_Variables HASH Private Variables\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup HASH_Private_Constants HASH Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup HASH_Private_Macros HASH Private Macros\r\n  * @{\r\n  */\r\n#define IS_HASH_ALGOSELECTION(__ALGOSELECTION__) (((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA1)   || \\\r\n                                                  ((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA224) || \\\r\n                                                  ((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA256) || \\\r\n                                                  ((__ALGOSELECTION__) == HASH_ALGOSELECTION_MD5))\r\n\r\n\r\n#define IS_HASH_ALGOMODE(__ALGOMODE__) (((__ALGOMODE__) == HASH_ALGOMODE_HASH) || \\\r\n                                        ((__ALGOMODE__) == HASH_ALGOMODE_HMAC))\r\n\r\n\r\n#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \\\r\n                                        ((__DATATYPE__) == HASH_DATATYPE_16B)|| \\\r\n                                        ((__DATATYPE__) == HASH_DATATYPE_8B) || \\\r\n                                        ((__DATATYPE__) == HASH_DATATYPE_1B))\r\n\r\n\r\n#define IS_HASH_HMAC_KEYTYPE(__KEYTYPE__) (((__KEYTYPE__) == HASH_HMAC_KEYTYPE_SHORTKEY) || \\\r\n                                           ((__KEYTYPE__) == HASH_HMAC_KEYTYPE_LONGKEY))\r\n                                           \r\n#define IS_HASH_SHA1_BUFFER_SIZE(__SIZE__) ((((__SIZE__)%4) != 0)? 0U: 1U)\r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup HASH_Private_Functions HASH Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n \r\n/**\r\n  * @}\r\n  */ \r\n#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n/**\r\n  * @}\r\n  */\r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n\r\n#endif /* __STM32F7xx_HAL_HASH_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_hash_ex.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of HASH HAL Extension module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_HASH_EX_H\r\n#define __STM32F7xx_HAL_HASH_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup HASHEx    \r\n  * @brief HASHEx HAL Extension module driver \r\n  *  @{\r\n  */ \r\n  \r\n/* Exported types ------------------------------------------------------------*/ \r\n/* Exported constants --------------------------------------------------------*/\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @defgroup HASHEx_Exported_Functions HASHEx Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup HASHEx_Exported_Functions_Group1 HASHEx processing using polling functions\r\n  * @{\r\n  */  \r\n\r\nHAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r\nHAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/** @defgroup HASHEx_Exported_Functions_Group2 HMAC processing using polling functions\r\n  * @{\r\n  */ \r\n  \r\nHAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/** @defgroup HASHEx_Exported_Functions_Group3 HASHEx processing using  functions\r\n  * @{\r\n  */ \r\n  \r\nHAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);\r\nHAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/** @defgroup HASHEx_Exported_Functions_Group4 HASHEx processing using DMA\r\n  * @{\r\n  */\r\n  \r\nHAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r\nHAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r\nHAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/** @defgroup HASHEx_Exported_Functions_Group5 HMAC processing using DMA\r\n  * @{\r\n  */\r\n  \r\nHAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r\nHAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/** @defgroup HASHEx_Exported_Functions_Group6 HASHEx processing functions\r\n  * @{\r\n  */\r\n  \r\nvoid HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n \r\n /* Private types -------------------------------------------------------------*/\r\n/** @defgroup HASHEx_Private_Types HASHEx Private Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @defgroup HASHEx_Private_Variables HASHEx Private Variables\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup HASHEx_Private_Constants HASHEx Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup HASHEx_Private_Macros HASHEx Private Macros\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup HASHEx_Private_Functions HASHEx Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n   \r\n/**\r\n  * @}\r\n  */ \r\n#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_HASH_EX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hcd.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_hcd.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of HCD HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_HCD_H\r\n#define __STM32F7xx_HAL_HCD_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_ll_usb.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup HCD\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup HCD_Exported_Types HCD Exported Types\r\n  * @{\r\n  */\r\n\r\n/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition\r\n  * @{\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_HCD_STATE_RESET    = 0x00,\r\n  HAL_HCD_STATE_READY    = 0x01,\r\n  HAL_HCD_STATE_ERROR    = 0x02,\r\n  HAL_HCD_STATE_BUSY     = 0x03,\r\n  HAL_HCD_STATE_TIMEOUT  = 0x04\r\n} HCD_StateTypeDef;\r\n\r\ntypedef USB_OTG_GlobalTypeDef   HCD_TypeDef;\r\ntypedef USB_OTG_CfgTypeDef      HCD_InitTypeDef;\r\ntypedef USB_OTG_HCTypeDef       HCD_HCTypeDef;\r\ntypedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef;\r\ntypedef USB_OTG_HCStateTypeDef  HCD_HCStateTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition\r\n  * @{\r\n  */\r\ntypedef struct\r\n{\r\n  HCD_TypeDef               *Instance;  /*!< Register base address    */\r\n  HCD_InitTypeDef           Init;       /*!< HCD required parameters  */\r\n  HCD_HCTypeDef             hc[16];     /*!< Host channels parameters */\r\n  HAL_LockTypeDef           Lock;       /*!< HCD peripheral status    */\r\n  __IO HCD_StateTypeDef     State;      /*!< HCD communication state  */\r\n  void                      *pData;     /*!< Pointer Stack Handler    */\r\n} HCD_HandleTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup HCD_Exported_Constants HCD Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup HCD_Speed HCD Speed\r\n  * @{\r\n  */\r\n#define HCD_SPEED_HIGH               0U\r\n#define HCD_SPEED_LOW                2U\r\n#define HCD_SPEED_FULL               3U\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HCD_PHY_Module HCD PHY Module\r\n  * @{\r\n  */\r\n#define HCD_PHY_ULPI                 1U\r\n#define HCD_PHY_EMBEDDED             2U\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup HCD_Exported_Macros HCD Exported Macros\r\n *  @brief macros to handle interrupts and specific clock configurations\r\n * @{\r\n */\r\n#define __HAL_HCD_ENABLE(__HANDLE__)                   (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)\r\n#define __HAL_HCD_DISABLE(__HANDLE__)                  (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)\r\n\r\n#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))\r\n#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))\r\n#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)\r\n\r\n#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__)  (USBx_HC(chnum)->HCINT = (__INTERRUPT__))\r\n#define __HAL_HCD_MASK_HALT_HC_INT(chnum)             (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)\r\n#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum)           (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)\r\n#define __HAL_HCD_MASK_ACK_HC_INT(chnum)              (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)\r\n#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum)            (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup HCD_Exported_Functions HCD Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef      HAL_HCD_Init(HCD_HandleTypeDef *hhcd);\r\nHAL_StatusTypeDef      HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd);\r\nHAL_StatusTypeDef      HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,\r\n                                  uint8_t ch_num,\r\n                                  uint8_t epnum,\r\n                                  uint8_t dev_address,\r\n                                  uint8_t speed,\r\n                                  uint8_t ep_type,\r\n                                  uint16_t mps);\r\n\r\nHAL_StatusTypeDef     HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);\r\nvoid                  HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);\r\nvoid                  HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* I/O operation functions  ***************************************************/\r\n/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef       HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,\r\n                                                 uint8_t pipe,\r\n                                                 uint8_t direction ,\r\n                                                 uint8_t ep_type,\r\n                                                 uint8_t token,\r\n                                                 uint8_t* pbuff,\r\n                                                 uint16_t length,\r\n                                                 uint8_t do_ping);\r\n\r\n /* Non-Blocking mode: Interrupt */\r\nvoid             HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);\r\nvoid             HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);\r\nvoid             HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);\r\nvoid             HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);\r\nvoid             HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);\r\nvoid             HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);\r\nvoid             HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,\r\n                                                            uint8_t chnum,\r\n                                                            HCD_URBStateTypeDef urb_state);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Peripheral Control functions  **********************************************/\r\n/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef       HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);\r\nHAL_StatusTypeDef       HAL_HCD_Start(HCD_HandleTypeDef *hhcd);\r\nHAL_StatusTypeDef       HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Peripheral State functions  ************************************************/\r\n/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions\r\n  * @{\r\n  */\r\nHCD_StateTypeDef        HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);\r\nHCD_URBStateTypeDef     HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);\r\nuint32_t                HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);\r\nHCD_HCStateTypeDef      HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);\r\nuint32_t                HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);\r\nuint32_t                HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup HCD_Private_Macros HCD Private Macros\r\n * @{\r\n */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions prototypes ----------------------------------------------*/\r\n/** @defgroup HCD_Private_Functions_Prototypes HCD Private Functions Prototypes\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup HCD_Private_Functions HCD Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_HCD_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_i2c.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of I2C HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_I2C_H\r\n#define __STM32F7xx_HAL_I2C_H\r\n\r\n#ifdef __cplusplus\r\nextern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup I2C\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup I2C_Exported_Types I2C Exported Types\r\n  * @{\r\n  */\r\n\r\n/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition\r\n  * @brief  I2C Configuration Structure definition\r\n  * @{\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t Timing;              /*!< Specifies the I2C_TIMINGR_register value.\r\n                                  This parameter calculated by referring to I2C initialization\r\n                                         section in Reference manual */\r\n\r\n  uint32_t OwnAddress1;         /*!< Specifies the first device own address.\r\n                                  This parameter can be a 7-bit or 10-bit address. */\r\n\r\n  uint32_t AddressingMode;      /*!< Specifies if 7-bit or 10-bit addressing mode is selected.\r\n                                  This parameter can be a value of @ref I2C_ADDRESSING_MODE */\r\n\r\n  uint32_t DualAddressMode;     /*!< Specifies if dual addressing mode is selected.\r\n                                  This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */\r\n\r\n  uint32_t OwnAddress2;         /*!< Specifies the second device own address if dual addressing mode is selected\r\n                                  This parameter can be a 7-bit address. */\r\n\r\n  uint32_t OwnAddress2Masks;    /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected\r\n                                  This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */\r\n\r\n  uint32_t GeneralCallMode;     /*!< Specifies if general call mode is selected.\r\n                                  This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */\r\n\r\n  uint32_t NoStretchMode;       /*!< Specifies if nostretch mode is selected.\r\n                                  This parameter can be a value of @ref I2C_NOSTRETCH_MODE */\r\n\r\n} I2C_InitTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_state_structure_definition HAL state structure definition\r\n  * @brief  HAL State structure definition\r\n  * @note  HAL I2C State value coding follow below described bitmap :\\n\r\n  *          b7-b6  Error information\\n\r\n  *             00 : No Error\\n\r\n  *             01 : Abort (Abort user request on going)\\n\r\n  *             10 : Timeout\\n\r\n  *             11 : Error\\n\r\n  *          b5     IP initilisation status\\n\r\n  *             0  : Reset (IP not initialized)\\n\r\n  *             1  : Init done (IP initialized and ready to use. HAL I2C Init function called)\\n\r\n  *          b4     (not used)\\n\r\n  *             x  : Should be set to 0\\n\r\n  *          b3\\n\r\n  *             0  : Ready or Busy (No Listen mode ongoing)\\n\r\n  *             1  : Listen (IP in Address Listen Mode)\\n\r\n  *          b2     Intrinsic process state\\n\r\n  *             0  : Ready\\n\r\n  *             1  : Busy (IP busy with some configuration or internal operations)\\n\r\n  *          b1     Rx state\\n\r\n  *             0  : Ready (no Rx operation ongoing)\\n\r\n  *             1  : Busy (Rx operation ongoing)\\n\r\n  *          b0     Tx state\\n\r\n  *             0  : Ready (no Tx operation ongoing)\\n\r\n  *             1  : Busy (Tx operation ongoing)\r\n  * @{\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */\r\n  HAL_I2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */\r\n  HAL_I2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */\r\n  HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */\r\n  HAL_I2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */\r\n  HAL_I2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */\r\n  HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission\r\n                                                 process is ongoing                         */\r\n  HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception\r\n                                                 process is ongoing                         */\r\n  HAL_I2C_STATE_ABORT             = 0x60U,   /*!< Abort user request ongoing                */\r\n  HAL_I2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */\r\n  HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */\r\n\r\n} HAL_I2C_StateTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_mode_structure_definition HAL mode structure definition\r\n  * @brief  HAL Mode structure definition\r\n  * @note  HAL I2C Mode value coding follow below described bitmap :\\n\r\n  *          b7     (not used)\\n\r\n  *             x  : Should be set to 0\\n\r\n  *          b6\\n\r\n  *             0  : None\\n\r\n  *             1  : Memory (HAL I2C communication is in Memory Mode)\\n\r\n  *          b5\\n\r\n  *             0  : None\\n\r\n  *             1  : Slave (HAL I2C communication is in Slave Mode)\\n\r\n  *          b4\\n\r\n  *             0  : None\\n\r\n  *             1  : Master (HAL I2C communication is in Master Mode)\\n\r\n  *          b3-b2-b1-b0  (not used)\\n\r\n  *             xxxx : Should be set to 0000\r\n  * @{\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_I2C_MODE_NONE               = 0x00U,   /*!< No I2C communication on going             */\r\n  HAL_I2C_MODE_MASTER             = 0x10U,   /*!< I2C communication is in Master Mode       */\r\n  HAL_I2C_MODE_SLAVE              = 0x20U,   /*!< I2C communication is in Slave Mode        */\r\n  HAL_I2C_MODE_MEM                = 0x40U    /*!< I2C communication is in Memory Mode       */\r\n\r\n} HAL_I2C_ModeTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2C_Error_Code_definition I2C Error Code definition\r\n  * @brief  I2C Error Code definition\r\n  * @{\r\n  */\r\n#define HAL_I2C_ERROR_NONE      (0x00000000U)    /*!< No error              */\r\n#define HAL_I2C_ERROR_BERR      (0x00000001U)    /*!< BERR error            */\r\n#define HAL_I2C_ERROR_ARLO      (0x00000002U)    /*!< ARLO error            */\r\n#define HAL_I2C_ERROR_AF        (0x00000004U)    /*!< ACKF error            */\r\n#define HAL_I2C_ERROR_OVR       (0x00000008U)    /*!< OVR error             */\r\n#define HAL_I2C_ERROR_DMA       (0x00000010U)    /*!< DMA transfer error    */\r\n#define HAL_I2C_ERROR_TIMEOUT   (0x00000020U)    /*!< Timeout error         */\r\n#define HAL_I2C_ERROR_SIZE      (0x00000040U)    /*!< Size Management error */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition\r\n  * @brief  I2C handle Structure definition\r\n  * @{\r\n  */\r\ntypedef struct __I2C_HandleTypeDef\r\n{\r\n  I2C_TypeDef                *Instance;      /*!< I2C registers base address                */\r\n\r\n  I2C_InitTypeDef            Init;           /*!< I2C communication parameters              */\r\n\r\n  uint8_t                    *pBuffPtr;      /*!< Pointer to I2C transfer buffer            */\r\n\r\n  uint16_t                   XferSize;       /*!< I2C transfer size                         */\r\n\r\n  __IO uint16_t              XferCount;      /*!< I2C transfer counter                      */\r\n\r\n  __IO uint32_t              XferOptions;    /*!< I2C sequantial transfer options, this parameter can\r\n                                                  be a value of @ref I2C_XFEROPTIONS */\r\n\r\n  __IO uint32_t              PreviousState;  /*!< I2C communication Previous state          */\r\n\r\n  HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);  /*!< I2C transfer IRQ handler function pointer */\r\n\r\n  DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters              */\r\n\r\n  DMA_HandleTypeDef          *hdmarx;        /*!< I2C Rx DMA handle parameters              */\r\n\r\n  HAL_LockTypeDef            Lock;           /*!< I2C locking object                        */\r\n\r\n  __IO HAL_I2C_StateTypeDef  State;          /*!< I2C communication state                   */\r\n\r\n  __IO HAL_I2C_ModeTypeDef   Mode;           /*!< I2C communication mode                    */\r\n\r\n  __IO uint32_t              ErrorCode;      /*!< I2C Error code                            */\r\n\r\n  __IO uint32_t              AddrEventCount; /*!< I2C Address Event counter                 */\r\n} I2C_HandleTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup I2C_Exported_Constants I2C Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup I2C_XFEROPTIONS  I2C Sequential Transfer Options\r\n  * @{\r\n  */\r\n#define I2C_FIRST_FRAME                 ((uint32_t)I2C_SOFTEND_MODE)\r\n#define I2C_FIRST_AND_NEXT_FRAME        ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))\r\n#define I2C_NEXT_FRAME                  ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))\r\n#define I2C_FIRST_AND_LAST_FRAME        ((uint32_t)I2C_AUTOEND_MODE)\r\n#define I2C_LAST_FRAME                  ((uint32_t)I2C_AUTOEND_MODE)\r\n#define I2C_LAST_FRAME_NO_STOP          ((uint32_t)I2C_SOFTEND_MODE)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode\r\n  * @{\r\n  */\r\n#define I2C_ADDRESSINGMODE_7BIT         (0x00000001U)\r\n#define I2C_ADDRESSINGMODE_10BIT        (0x00000002U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode\r\n  * @{\r\n  */\r\n#define I2C_DUALADDRESS_DISABLE         (0x00000000U)\r\n#define I2C_DUALADDRESS_ENABLE          I2C_OAR2_OA2EN\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks\r\n  * @{\r\n  */\r\n#define I2C_OA2_NOMASK                  ((uint8_t)0x00U)\r\n#define I2C_OA2_MASK01                  ((uint8_t)0x01U)\r\n#define I2C_OA2_MASK02                  ((uint8_t)0x02U)\r\n#define I2C_OA2_MASK03                  ((uint8_t)0x03U)\r\n#define I2C_OA2_MASK04                  ((uint8_t)0x04U)\r\n#define I2C_OA2_MASK05                  ((uint8_t)0x05U)\r\n#define I2C_OA2_MASK06                  ((uint8_t)0x06U)\r\n#define I2C_OA2_MASK07                  ((uint8_t)0x07U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode\r\n  * @{\r\n  */\r\n#define I2C_GENERALCALL_DISABLE         (0x00000000U)\r\n#define I2C_GENERALCALL_ENABLE          I2C_CR1_GCEN\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode\r\n  * @{\r\n  */\r\n#define I2C_NOSTRETCH_DISABLE           (0x00000000U)\r\n#define I2C_NOSTRETCH_ENABLE            I2C_CR1_NOSTRETCH\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size\r\n  * @{\r\n  */\r\n#define I2C_MEMADD_SIZE_8BIT            (0x00000001U)\r\n#define I2C_MEMADD_SIZE_16BIT           (0x00000002U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View\r\n  * @{\r\n  */\r\n#define I2C_DIRECTION_TRANSMIT          (0x00000000U)\r\n#define I2C_DIRECTION_RECEIVE           (0x00000001U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode\r\n  * @{\r\n  */\r\n#define  I2C_RELOAD_MODE                I2C_CR2_RELOAD\r\n#define  I2C_AUTOEND_MODE               I2C_CR2_AUTOEND\r\n#define  I2C_SOFTEND_MODE               (0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode\r\n  * @{\r\n  */\r\n#define  I2C_NO_STARTSTOP               (0x00000000U)\r\n#define  I2C_GENERATE_STOP              (uint32_t)(0x80000000U | I2C_CR2_STOP)\r\n#define  I2C_GENERATE_START_READ        (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)\r\n#define  I2C_GENERATE_START_WRITE       (uint32_t)(0x80000000U | I2C_CR2_START)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition\r\n  * @brief I2C Interrupt definition\r\n  *        Elements values convention: 0xXXXXXXXX\r\n  *           - XXXXXXXX  : Interrupt control mask\r\n  * @{\r\n  */\r\n#define I2C_IT_ERRI                     I2C_CR1_ERRIE\r\n#define I2C_IT_TCI                      I2C_CR1_TCIE\r\n#define I2C_IT_STOPI                    I2C_CR1_STOPIE\r\n#define I2C_IT_NACKI                    I2C_CR1_NACKIE\r\n#define I2C_IT_ADDRI                    I2C_CR1_ADDRIE\r\n#define I2C_IT_RXI                      I2C_CR1_RXIE\r\n#define I2C_IT_TXI                      I2C_CR1_TXIE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2C_Flag_definition I2C Flag definition\r\n  * @{\r\n  */\r\n#define I2C_FLAG_TXE                    I2C_ISR_TXE\r\n#define I2C_FLAG_TXIS                   I2C_ISR_TXIS\r\n#define I2C_FLAG_RXNE                   I2C_ISR_RXNE\r\n#define I2C_FLAG_ADDR                   I2C_ISR_ADDR\r\n#define I2C_FLAG_AF                     I2C_ISR_NACKF\r\n#define I2C_FLAG_STOPF                  I2C_ISR_STOPF\r\n#define I2C_FLAG_TC                     I2C_ISR_TC\r\n#define I2C_FLAG_TCR                    I2C_ISR_TCR\r\n#define I2C_FLAG_BERR                   I2C_ISR_BERR\r\n#define I2C_FLAG_ARLO                   I2C_ISR_ARLO\r\n#define I2C_FLAG_OVR                    I2C_ISR_OVR\r\n#define I2C_FLAG_PECERR                 I2C_ISR_PECERR\r\n#define I2C_FLAG_TIMEOUT                I2C_ISR_TIMEOUT\r\n#define I2C_FLAG_ALERT                  I2C_ISR_ALERT\r\n#define I2C_FLAG_BUSY                   I2C_ISR_BUSY\r\n#define I2C_FLAG_DIR                    I2C_ISR_DIR\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macros -----------------------------------------------------------*/\r\n\r\n/** @defgroup I2C_Exported_Macros I2C Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief Reset I2C handle state.\r\n  * @param  __HANDLE__ specifies the I2C Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_I2C_STATE_RESET)\r\n\r\n/** @brief  Enable the specified I2C interrupt.\r\n  * @param  __HANDLE__ specifies the I2C Handle.\r\n  * @param  __INTERRUPT__ specifies the interrupt source to enable.\r\n  *        This parameter can be one of the following values:\r\n  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable\r\n  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable\r\n  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable\r\n  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable\r\n  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable\r\n  *            @arg @ref I2C_IT_RXI   RX interrupt enable\r\n  *            @arg @ref I2C_IT_TXI   TX interrupt enable\r\n  *\r\n  * @retval None\r\n  */\r\n#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))\r\n\r\n/** @brief  Disable the specified I2C interrupt.\r\n  * @param  __HANDLE__ specifies the I2C Handle.\r\n  * @param  __INTERRUPT__ specifies the interrupt source to disable.\r\n  *        This parameter can be one of the following values:\r\n  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable\r\n  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable\r\n  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable\r\n  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable\r\n  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable\r\n  *            @arg @ref I2C_IT_RXI   RX interrupt enable\r\n  *            @arg @ref I2C_IT_TXI   TX interrupt enable\r\n  *\r\n  * @retval None\r\n  */\r\n#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))\r\n\r\n/** @brief  Check whether the specified I2C interrupt source is enabled or not.\r\n  * @param  __HANDLE__ specifies the I2C Handle.\r\n  * @param  __INTERRUPT__ specifies the I2C interrupt source to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable\r\n  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable\r\n  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable\r\n  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable\r\n  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable\r\n  *            @arg @ref I2C_IT_RXI   RX interrupt enable\r\n  *            @arg @ref I2C_IT_TXI   TX interrupt enable\r\n  *\r\n  * @retval The new state of __INTERRUPT__ (SET or RESET).\r\n  */\r\n#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r\n\r\n/** @brief  Check whether the specified I2C flag is set or not.\r\n  * @param  __HANDLE__ specifies the I2C Handle.\r\n  * @param  __FLAG__ specifies the flag to check.\r\n  *        This parameter can be one of the following values:\r\n  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty\r\n  *            @arg @ref I2C_FLAG_TXIS    Transmit interrupt status\r\n  *            @arg @ref I2C_FLAG_RXNE    Receive data register not empty\r\n  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)\r\n  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag\r\n  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag\r\n  *            @arg @ref I2C_FLAG_TC      Transfer complete (master mode)\r\n  *            @arg @ref I2C_FLAG_TCR     Transfer complete reload\r\n  *            @arg @ref I2C_FLAG_BERR    Bus error\r\n  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost\r\n  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun\r\n  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception\r\n  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag\r\n  *            @arg @ref I2C_FLAG_ALERT   SMBus alert\r\n  *            @arg @ref I2C_FLAG_BUSY    Bus busy\r\n  *            @arg @ref I2C_FLAG_DIR     Transfer direction (slave mode)\r\n  *\r\n  * @retval The new state of __FLAG__ (SET or RESET).\r\n  */\r\n#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)\r\n\r\n/** @brief  Clear the I2C pending flags which are cleared by writing 1 in a specific bit.\r\n  * @param  __HANDLE__ specifies the I2C Handle.\r\n  * @param  __FLAG__ specifies the flag to clear.\r\n  *          This parameter can be any combination of the following values:\r\n  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty\r\n  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)\r\n  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag\r\n  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag\r\n  *            @arg @ref I2C_FLAG_BERR    Bus error\r\n  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost\r\n  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun\r\n  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception\r\n  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag\r\n  *            @arg @ref I2C_FLAG_ALERT   SMBus alert\r\n  *\r\n  * @retval None\r\n  */\r\n#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \\\r\n                                                                                 : ((__HANDLE__)->Instance->ICR = (__FLAG__)))\r\n\r\n/** @brief  Enable the specified I2C peripheral.\r\n  * @param  __HANDLE__ specifies the I2C Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_I2C_ENABLE(__HANDLE__)                            (SET_BIT((__HANDLE__)->Instance->CR1,  I2C_CR1_PE))\r\n\r\n/** @brief  Disable the specified I2C peripheral.\r\n  * @param  __HANDLE__ specifies the I2C Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_I2C_DISABLE(__HANDLE__)                           (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))\r\n\r\n/** @brief  Generate a Non-Acknowledge I2C peripheral in Slave mode.\r\n  * @param  __HANDLE__ specifies the I2C Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_I2C_GENERATE_NACK(__HANDLE__)                     (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Include I2C HAL Extended module */\r\n#include \"stm32f7xx_hal_i2c_ex.h\"\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup I2C_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions\r\n  * @{\r\n  */\r\n/* Initialization and de-initialization functions******************************/\r\nHAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);\r\nHAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);\r\nvoid HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);\r\nvoid HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions\r\n  * @{\r\n  */\r\n/* IO operation functions  ****************************************************/\r\n/******* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);\r\n\r\n/******* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\r\n\r\nHAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r\nHAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r\nHAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r\nHAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r\nHAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);\r\nHAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);\r\nHAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);\r\n\r\n/******* Non-Blocking mode: DMA */\r\nHAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks\r\n * @{\r\n */\r\n/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */\r\nvoid HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);\r\nvoid HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);\r\nvoid HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);\r\nvoid HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);\r\nvoid HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);\r\nvoid HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);\r\nvoid HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);\r\nvoid HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);\r\nvoid HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);\r\nvoid HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);\r\nvoid HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);\r\nvoid HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions\r\n  * @{\r\n  */\r\n/* Peripheral State, Mode and Error functions  *********************************/\r\nHAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);\r\nHAL_I2C_ModeTypeDef  HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);\r\nuint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup I2C_Private_Constants I2C Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup I2C_Private_Macro I2C Private Macros\r\n  * @{\r\n  */\r\n\r\n#define IS_I2C_ADDRESSING_MODE(MODE)    (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \\\r\n                                         ((MODE) == I2C_ADDRESSINGMODE_10BIT))\r\n\r\n#define IS_I2C_DUAL_ADDRESS(ADDRESS)    (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \\\r\n                                         ((ADDRESS) == I2C_DUALADDRESS_ENABLE))\r\n\r\n#define IS_I2C_OWN_ADDRESS2_MASK(MASK)  (((MASK) == I2C_OA2_NOMASK)  || \\\r\n                                         ((MASK) == I2C_OA2_MASK01) || \\\r\n                                         ((MASK) == I2C_OA2_MASK02) || \\\r\n                                         ((MASK) == I2C_OA2_MASK03) || \\\r\n                                         ((MASK) == I2C_OA2_MASK04) || \\\r\n                                         ((MASK) == I2C_OA2_MASK05) || \\\r\n                                         ((MASK) == I2C_OA2_MASK06) || \\\r\n                                         ((MASK) == I2C_OA2_MASK07))\r\n\r\n#define IS_I2C_GENERAL_CALL(CALL)       (((CALL) == I2C_GENERALCALL_DISABLE) || \\\r\n                                         ((CALL) == I2C_GENERALCALL_ENABLE))\r\n\r\n#define IS_I2C_NO_STRETCH(STRETCH)      (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \\\r\n                                         ((STRETCH) == I2C_NOSTRETCH_ENABLE))\r\n\r\n#define IS_I2C_MEMADD_SIZE(SIZE)        (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \\\r\n                                         ((SIZE) == I2C_MEMADD_SIZE_16BIT))\r\n\r\n#define IS_TRANSFER_MODE(MODE)          (((MODE) == I2C_RELOAD_MODE)   || \\\r\n                                         ((MODE) == I2C_AUTOEND_MODE) || \\\r\n                                         ((MODE) == I2C_SOFTEND_MODE))\r\n\r\n#define IS_TRANSFER_REQUEST(REQUEST)    (((REQUEST) == I2C_GENERATE_STOP)        || \\\r\n                                         ((REQUEST) == I2C_GENERATE_START_READ)  || \\\r\n                                         ((REQUEST) == I2C_GENERATE_START_WRITE) || \\\r\n                                         ((REQUEST) == I2C_NO_STARTSTOP))\r\n\r\n#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)  (((REQUEST) == I2C_FIRST_FRAME)          || \\\r\n                                                   ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \\\r\n                                                   ((REQUEST) == I2C_NEXT_FRAME)           || \\\r\n                                                   ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \\\r\n                                                   ((REQUEST) == I2C_LAST_FRAME)           || \\\r\n                                                   ((REQUEST) == I2C_LAST_FRAME_NO_STOP))\r\n\r\n#define I2C_RESET_CR2(__HANDLE__)                 ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))\r\n\r\n#define I2C_GET_ADDR_MATCH(__HANDLE__)            (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)\r\n#define I2C_GET_DIR(__HANDLE__)                   (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)\r\n#define I2C_GET_STOP_MODE(__HANDLE__)             ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)\r\n#define I2C_GET_OWN_ADDRESS1(__HANDLE__)          ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)\r\n#define I2C_GET_OWN_ADDRESS2(__HANDLE__)          ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)\r\n\r\n#define IS_I2C_OWN_ADDRESS1(ADDRESS1)             ((ADDRESS1) <= 0x000003FFU)\r\n#define IS_I2C_OWN_ADDRESS2(ADDRESS2)             ((ADDRESS2) <= (uint16_t)0x00FFU)\r\n\r\n#define I2C_MEM_ADD_MSB(__ADDRESS__)              ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))\r\n#define I2C_MEM_ADD_LSB(__ADDRESS__)              ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))\r\n\r\n#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \\\r\n                                                          (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private Functions ---------------------------------------------------------*/\r\n/** @defgroup I2C_Private_Functions I2C Private Functions\r\n  * @{\r\n  */\r\n/* Private functions are defined in stm32f7xx_hal_i2c.c file */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n\r\n#endif /* __STM32F7xx_HAL_I2C_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_i2c_ex.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of I2C HAL Extended module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_I2C_EX_H\r\n#define __STM32F7xx_HAL_I2C_EX_H\r\n\r\n#ifdef __cplusplus\r\nextern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup I2CEx\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter\r\n  * @{\r\n  */\r\n#define I2C_ANALOGFILTER_ENABLE         0x00000000U\r\n#define I2C_ANALOGFILTER_DISABLE        I2C_CR1_ANFOFF\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus\r\n  * @{\r\n  */\r\n#define I2C_FMP_NOT_SUPPORTED           0xAAAA0000U                                     /*!< Fast Mode Plus not supported       */\r\n#if defined(SYSCFG_PMC_I2C_PB6_FMP)\r\n#define I2C_FASTMODEPLUS_PB6            SYSCFG_PMC_I2C_PB6_FMP                        /*!< Enable Fast Mode Plus on PB6       */\r\n#define I2C_FASTMODEPLUS_PB7            SYSCFG_PMC_I2C_PB7_FMP                        /*!< Enable Fast Mode Plus on PB7       */\r\n#else\r\n#define I2C_FASTMODEPLUS_PB6            (uint32_t)(0x00000004U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB6 not supported   */\r\n#define I2C_FASTMODEPLUS_PB7            (uint32_t)(0x00000008U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB7 not supported   */\r\n#endif\r\n#if defined(SYSCFG_PMC_I2C_PB8_FMP)\r\n#define I2C_FASTMODEPLUS_PB8            SYSCFG_PMC_I2C_PB8_FMP                        /*!< Enable Fast Mode Plus on PB8       */\r\n#define I2C_FASTMODEPLUS_PB9            SYSCFG_PMC_I2C_PB9_FMP                        /*!< Enable Fast Mode Plus on PB9       */\r\n#else\r\n#define I2C_FASTMODEPLUS_PB8            (uint32_t)(0x00000010U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB8 not supported   */\r\n#define I2C_FASTMODEPLUS_PB9            (uint32_t)(0x00000012U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB9 not supported   */\r\n#endif\r\n#if defined(SYSCFG_PMC_I2C1_FMP)\r\n#define I2C_FASTMODEPLUS_I2C1           SYSCFG_PMC_I2C1_FMP                           /*!< Enable Fast Mode Plus on I2C1 pins */\r\n#else\r\n#define I2C_FASTMODEPLUS_I2C1           (uint32_t)(0x00000100U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C1 not supported  */\r\n#endif\r\n#if defined(SYSCFG_PMC_I2C2_FMP)\r\n#define I2C_FASTMODEPLUS_I2C2           SYSCFG_PMC_I2C2_FMP                           /*!< Enable Fast Mode Plus on I2C2 pins */\r\n#else\r\n#define I2C_FASTMODEPLUS_I2C2           (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported  */\r\n#endif\r\n#if defined(SYSCFG_PMC_I2C3_FMP)\r\n#define I2C_FASTMODEPLUS_I2C3           SYSCFG_PMC_I2C3_FMP                           /*!< Enable Fast Mode Plus on I2C3 pins */\r\n#else\r\n#define I2C_FASTMODEPLUS_I2C3           (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported  */\r\n#endif\r\n#if defined(SYSCFG_PMC_I2C4_FMP)\r\n#define I2C_FASTMODEPLUS_I2C4           SYSCFG_PMC_I2C4_FMP                           /*!< Enable Fast Mode Plus on I2C4 pins */\r\n#else\r\n#define I2C_FASTMODEPLUS_I2C4           (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported  */\r\n#endif\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions\r\n  * @brief    Extended features functions\r\n  * @{\r\n  */\r\n\r\n/* Peripheral Control functions  ************************************************/\r\nHAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);\r\nHAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);\r\n#if  (defined(SYSCFG_PMC_I2C_PB6_FMP) || defined(SYSCFG_PMC_I2C_PB7_FMP)) || (defined(SYSCFG_PMC_I2C_PB8_FMP) || defined(SYSCFG_PMC_I2C_PB9_FMP)) || (defined(SYSCFG_PMC_I2C1_FMP)) || (defined(SYSCFG_PMC_I2C2_FMP)) || defined(SYSCFG_PMC_I2C3_FMP) || defined(SYSCFG_PMC_I2C4_FMP)\r\nvoid HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);\r\nvoid HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);\r\n#endif\r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros\r\n  * @{\r\n  */\r\n#define IS_I2C_ANALOG_FILTER(FILTER)    (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \\\r\n                                          ((FILTER) == I2C_ANALOGFILTER_DISABLE))\r\n\r\n#define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000FU)\r\n\r\n#if defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) && defined(SYSCFG_PMC_I2C3_FMP) && defined(SYSCFG_PMC_I2C4_FMP)\r\n#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4))\r\n#elif defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) && defined(SYSCFG_PMC_I2C3_FMP)\r\n#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3))\r\n#elif defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP)\r\n#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2))\r\n#elif defined(SYSCFG_PMC_I2C1_FMP)\r\n#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1))\r\n#endif /* SYSCFG_PMC_I2C1_FMP && SYSCFG_PMC_I2C2_FMP && SYSCFG_PMC_I2C3_FMP && SYSCFG_PMC_I2C4_FMP */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private Functions ---------------------------------------------------------*/\r\n/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions\r\n  * @{\r\n  */\r\n/* Private functions are defined in stm32f7xx_hal_i2c_ex.c file */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_I2C_EX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2s.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_i2s.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of I2S HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_I2S_H\r\n#define __STM32F7xx_HAL_I2S_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"  \r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup I2S\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/ \r\n/** @defgroup I2S_Exported_Types I2S Exported Types\r\n  * @{\r\n  */\r\n\r\n/** \r\n  * @brief I2S Init structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t Mode;                /*!< Specifies the I2S operating mode.\r\n                                     This parameter can be a value of @ref I2S_Mode */\r\n\r\n  uint32_t Standard;            /*!< Specifies the standard used for the I2S communication.\r\n                                     This parameter can be a value of @ref I2S_Standard */\r\n\r\n  uint32_t DataFormat;          /*!< Specifies the data format for the I2S communication.\r\n                                     This parameter can be a value of @ref I2S_Data_Format */\r\n\r\n  uint32_t MCLKOutput;          /*!< Specifies whether the I2S MCLK output is enabled or not.\r\n                                     This parameter can be a value of @ref I2S_MCLK_Output */\r\n\r\n  uint32_t AudioFreq;           /*!< Specifies the frequency selected for the I2S communication.\r\n                                     This parameter can be a value of @ref I2S_Audio_Frequency */\r\n\r\n  uint32_t CPOL;                /*!< Specifies the idle state of the I2S clock.\r\n                                     This parameter can be a value of @ref I2S_Clock_Polarity */\r\n   \r\n  uint32_t ClockSource;         /*!< Specifies the I2S Clock Source.\r\n                                     This parameter can be a value of @ref I2S_Clock_Source */\r\n}I2S_InitTypeDef;\r\n\r\n/** \r\n  * @brief  HAL State structures definition  \r\n  */ \r\ntypedef enum\r\n{\r\n  HAL_I2S_STATE_RESET      = 0x00U,  /*!< I2S not yet initialized or disabled                */\r\n  HAL_I2S_STATE_READY      = 0x01U,  /*!< I2S initialized and ready for use                  */\r\n  HAL_I2S_STATE_BUSY       = 0x02U,  /*!< I2S internal process is ongoing                    */   \r\n  HAL_I2S_STATE_BUSY_TX    = 0x03U,  /*!< Data Transmission process is ongoing               */ \r\n  HAL_I2S_STATE_BUSY_RX    = 0x04U,  /*!< Data Reception process is ongoing                  */\r\n  HAL_I2S_STATE_BUSY_TX_RX = 0x05U,  /*!< Data Transmission and Reception process is ongoing */\r\n  HAL_I2S_STATE_TIMEOUT    = 0x06U,  /*!< I2S timeout state                                  */  \r\n  HAL_I2S_STATE_ERROR      = 0x07U   /*!< I2S error state                                    */      \r\n                                                                        \r\n}HAL_I2S_StateTypeDef;\r\n\r\n/** \r\n  * @brief I2S handle Structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  SPI_TypeDef                *Instance;    /* I2S registers base address */\r\n\r\n  I2S_InitTypeDef            Init;         /* I2S communication parameters */\r\n  \r\n  uint16_t                   *pTxBuffPtr;  /* Pointer to I2S Tx transfer buffer */\r\n  \r\n  __IO uint16_t              TxXferSize;   /* I2S Tx transfer size */\r\n  \r\n  __IO uint16_t              TxXferCount;  /* I2S Tx transfer Counter */\r\n  \r\n  uint16_t                   *pRxBuffPtr;  /* Pointer to I2S Rx transfer buffer */\r\n  \r\n  __IO uint16_t              RxXferSize;   /* I2S Rx transfer size */\r\n  \r\n  __IO uint16_t              RxXferCount;  /* I2S Rx transfer counter \r\n                                              (This field is initialized at the \r\n                                               same value as transfer size at the \r\n                                               beginning of the transfer and \r\n                                               decremented when a sample is received. \r\n                                               NbSamplesReceived = RxBufferSize-RxBufferCount) */\r\n\r\n  DMA_HandleTypeDef          *hdmatx;      /* I2S Tx DMA handle parameters */\r\n\r\n  DMA_HandleTypeDef          *hdmarx;      /* I2S Rx DMA handle parameters */\r\n  \r\n  __IO HAL_LockTypeDef       Lock;         /* I2S locking object */\r\n  \r\n  __IO HAL_I2S_StateTypeDef  State;        /* I2S communication state */\r\n\r\n  __IO uint32_t  ErrorCode;                /* I2S Error code                 */\r\n\r\n}I2S_HandleTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup I2S_Exported_Constants I2S Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup I2S_Error_Defintion I2S_Error_Defintion\r\n  *@brief     I2S Error Code\r\n  * @{\r\n  */\r\n#define HAL_I2S_ERROR_NONE      ((uint32_t)0x00000000U)  /*!< No error           */\r\n#define HAL_I2S_ERROR_TIMEOUT   ((uint32_t)0x00000001U)  /*!< Timeout error      */\r\n#define HAL_I2S_ERROR_OVR       ((uint32_t)0x00000002U)  /*!< OVR error          */\r\n#define HAL_I2S_ERROR_UDR       ((uint32_t)0x00000004U)  /*!< UDR error          */\r\n#define HAL_I2S_ERROR_DMA       ((uint32_t)0x00000008U)  /*!< DMA transfer error */\r\n#define HAL_I2S_ERROR_UNKNOW    ((uint32_t)0x00000010U)  /*!< Unknow Error error */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/** @defgroup I2S_Clock_Source I2S Clock Source\r\n  * @{\r\n  */\r\n#define I2S_CLOCK_EXTERNAL                ((uint32_t)0x00000001U)\r\n#define I2S_CLOCK_PLL                     ((uint32_t)0x00000002U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2S_Mode I2S Mode\r\n  * @{\r\n  */\r\n#define I2S_MODE_SLAVE_TX                ((uint32_t)0x00000000U)\r\n#define I2S_MODE_SLAVE_RX                ((uint32_t)0x00000100U)\r\n#define I2S_MODE_MASTER_TX               ((uint32_t)0x00000200U)\r\n#define I2S_MODE_MASTER_RX               ((uint32_t)0x00000300U)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup I2S_Standard I2S Standard\r\n  * @{\r\n  */\r\n#define I2S_STANDARD_PHILIPS             ((uint32_t)0x00000000U)\r\n#define I2S_STANDARD_MSB                 ((uint32_t)0x00000010U)\r\n#define I2S_STANDARD_LSB                 ((uint32_t)0x00000020U)\r\n#define I2S_STANDARD_PCM_SHORT           ((uint32_t)0x00000030U)\r\n#define I2S_STANDARD_PCM_LONG            ((uint32_t)0x000000B0U)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup I2S_Data_Format I2S Data Format\r\n  * @{\r\n  */\r\n#define I2S_DATAFORMAT_16B               ((uint32_t)0x00000000U)\r\n#define I2S_DATAFORMAT_16B_EXTENDED      ((uint32_t)0x00000001U)\r\n#define I2S_DATAFORMAT_24B               ((uint32_t)0x00000003U)\r\n#define I2S_DATAFORMAT_32B               ((uint32_t)0x00000005U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2S_MCLK_Output I2S Mclk Output\r\n  * @{\r\n  */\r\n#define I2S_MCLKOUTPUT_ENABLE           ((uint32_t)SPI_I2SPR_MCKOE)\r\n#define I2S_MCLKOUTPUT_DISABLE          ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2S_Audio_Frequency I2S Audio Frequency\r\n  * @{\r\n  */\r\n#define I2S_AUDIOFREQ_192K               ((uint32_t)192000U)\r\n#define I2S_AUDIOFREQ_96K                ((uint32_t)96000U)\r\n#define I2S_AUDIOFREQ_48K                ((uint32_t)48000U)\r\n#define I2S_AUDIOFREQ_44K                ((uint32_t)44100U)\r\n#define I2S_AUDIOFREQ_32K                ((uint32_t)32000U)\r\n#define I2S_AUDIOFREQ_22K                ((uint32_t)22050U)\r\n#define I2S_AUDIOFREQ_16K                ((uint32_t)16000U)\r\n#define I2S_AUDIOFREQ_11K                ((uint32_t)11025U)\r\n#define I2S_AUDIOFREQ_8K                 ((uint32_t)8000U)\r\n#define I2S_AUDIOFREQ_DEFAULT            ((uint32_t)2U)\r\n/**\r\n  * @}\r\n  */\r\n            \r\n\r\n/** @defgroup I2S_Clock_Polarity I2S Clock Polarity\r\n  * @{\r\n  */\r\n#define I2S_CPOL_LOW                    ((uint32_t)0x00000000U)\r\n#define I2S_CPOL_HIGH                   ((uint32_t)SPI_I2SCFGR_CKPOL)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition\r\n  * @{\r\n  */\r\n#define I2S_IT_TXE                      SPI_CR2_TXEIE\r\n#define I2S_IT_RXNE                     SPI_CR2_RXNEIE\r\n#define I2S_IT_ERR                      SPI_CR2_ERRIE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2S_Flags_Definition I2S Flags Definition\r\n  * @{\r\n  */ \r\n#define I2S_FLAG_TXE                    SPI_SR_TXE\r\n#define I2S_FLAG_RXNE                   SPI_SR_RXNE\r\n\r\n#define I2S_FLAG_UDR                    SPI_SR_UDR\r\n#define I2S_FLAG_OVR                    SPI_SR_OVR\r\n#define I2S_FLAG_FRE                    SPI_SR_FRE\r\n\r\n#define I2S_FLAG_CHSIDE                 SPI_SR_CHSIDE\r\n#define I2S_FLAG_BSY                    SPI_SR_BSY\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/* Exported macros -----------------------------------------------------------*/\r\n/** @defgroup I2S_Exported_Macros I2S Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief  Reset I2S handle state\r\n  * @param  __HANDLE__ specifies the I2S handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)\r\n\r\n/** @brief  Enable or disable the specified SPI peripheral (in I2S mode).\r\n  * @param  __HANDLE__ specifies the I2S Handle. \r\n  * @retval None\r\n  */\r\n#define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)\r\n#define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= ~SPI_I2SCFGR_I2SE)\r\n\r\n/** @brief  Enable or disable the specified I2S interrupts.\r\n  * @param  __HANDLE__ specifies the I2S Handle.\r\n  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.\r\n  *        This parameter can be one of the following values:\r\n  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable\r\n  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable\r\n  *            @arg I2S_IT_ERR: Error interrupt enable\r\n  * @retval None\r\n  */  \r\n#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))\r\n#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= ~(__INTERRUPT__))\r\n \r\n/** @brief  Checks if the specified I2S interrupt source is enabled or disabled.\r\n  * @param  __HANDLE__ specifies the I2S Handle.\r\n  *         This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.\r\n  * @param  __INTERRUPT__ specifies the I2S interrupt source to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable\r\n  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable\r\n  *            @arg I2S_IT_ERR: Error interrupt enable\r\n  * @retval The new state of __IT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r\n\r\n/** @brief  Checks whether the specified I2S flag is set or not.\r\n  * @param  __HANDLE__ specifies the I2S Handle.\r\n  * @param  __FLAG__ specifies the flag to check.\r\n  *        This parameter can be one of the following values:\r\n  *            @arg I2S_FLAG_RXNE: Receive buffer not empty flag\r\n  *            @arg I2S_FLAG_TXE: Transmit buffer empty flag\r\n  *            @arg I2S_FLAG_UDR: Underrun flag\r\n  *            @arg I2S_FLAG_OVR: Overrun flag\r\n  *            @arg I2S_FLAG_FRE: Frame error flag\r\n  *            @arg I2S_FLAG_CHSIDE: Channel Side flag\r\n  *            @arg I2S_FLAG_BSY: Busy flag\r\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))\r\n\r\n/** @brief Clears the I2S OVR pending flag.\r\n  * @param  __HANDLE__ specifies the I2S Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__)     \\\r\n  do{                                           \\\r\n    __IO uint32_t tmpreg;                       \\\r\n    tmpreg = (__HANDLE__)->Instance->DR;        \\\r\n    tmpreg = (__HANDLE__)->Instance->SR;        \\\r\n    UNUSED(tmpreg);                             \\\r\n  } while(0)\r\n    \r\n/** @brief Clears the I2S UDR pending flag.\r\n  * @param  __HANDLE__ specifies the I2S Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)     \\\r\n  do{                                             \\\r\n  __IO uint32_t tmpreg;                         \\\r\n  tmpreg = (__HANDLE__)->Instance->SR;          \\\r\n  UNUSED(tmpreg);                               \\\r\n  } while(0)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup I2S_Exported_Functions  I2S Exported Functions\r\n  * @{\r\n  */\r\n                                                \r\n/** @addtogroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions \r\n  * @{\r\n  */\r\n\r\n/* Initialization and de-initialization functions *****************************/\r\nHAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);\r\nHAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);\r\nvoid HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);\r\nvoid HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup I2S_Exported_Functions_Group2 Input and Output operation functions \r\n  * @{\r\n  */\r\n/* I/O operation functions  ***************************************************/\r\n /* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);\r\n\r\n /* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);\r\nvoid HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);\r\n\r\n/* Non-Blocking mode: DMA */\r\nHAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);\r\n\r\nHAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);\r\nHAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);\r\nHAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);\r\n\r\n/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/\r\nvoid HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);\r\nvoid HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);\r\nvoid HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);\r\nvoid HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);\r\nvoid HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions\r\n  * @{\r\n  */\r\n/* Peripheral Control and State functions  ************************************/\r\nHAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);\r\nuint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup I2S_Private_Constants I2S Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup I2S_Private_Macros I2S Private Macros\r\n  * @{\r\n  */\r\n#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \\\r\n                                   ((CLOCK) == I2S_CLOCK_PLL))\r\n\t\t\t\t\t\t\t\t   \r\n#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \\\r\n                           ((MODE) == I2S_MODE_SLAVE_RX) || \\\r\n                           ((MODE) == I2S_MODE_MASTER_TX)|| \\\r\n                           ((MODE) == I2S_MODE_MASTER_RX))\r\n                           \r\n#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS)   || \\\r\n                                   ((STANDARD) == I2S_STANDARD_MSB)       || \\\r\n                                   ((STANDARD) == I2S_STANDARD_LSB)       || \\\r\n                                   ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \\\r\n                                   ((STANDARD) == I2S_STANDARD_PCM_LONG))\r\n\r\n#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B)          || \\\r\n                                    ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \\\r\n                                    ((FORMAT) == I2S_DATAFORMAT_24B)          || \\\r\n                                    ((FORMAT) == I2S_DATAFORMAT_32B))\r\n\r\n#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \\\r\n                                    ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))\r\n                                    \r\n#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \\\r\n                                 ((FREQ) <= I2S_AUDIOFREQ_192K)) || \\\r\n                                 ((FREQ) == I2S_AUDIOFREQ_DEFAULT))\r\n\t\t\t\t\t\t\t\t \r\n#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \\\r\n                           ((CPOL) == I2S_CPOL_HIGH))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */  \r\n\t\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n\r\n#endif /* __STM32F7xx_HAL_I2S_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_irda.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_irda.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of IRDA HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_IRDA_H\r\n#define __STM32F7xx_HAL_IRDA_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup IRDA\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/ \r\n/** @defgroup IRDA_Exported_Types IRDA Exported Types\r\n  * @{\r\n  */\r\n/** \r\n  * @brief IRDA Init Structure definition  \r\n  */ \r\ntypedef struct\r\n{\r\n  uint32_t BaudRate;                  /*!< This member configures the IRDA communication baud rate.\r\n                                           The baud rate register is computed using the following formula:\r\n                                              Baud Rate Register = ((PCLKx) / ((hirda->Init.BaudRate))) */\r\n\r\n  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.\r\n                                           This parameter can be a value of @ref IRDAEx_Word_Length */\r\n\r\n  uint32_t Parity;                    /*!< Specifies the parity mode.\r\n                                           This parameter can be a value of @ref IRDA_Parity\r\n                                           @note When parity is enabled, the computed parity is inserted\r\n                                                 at the MSB position of the transmitted data (9th bit when\r\n                                                 the word length is set to 9 data bits; 8th bit when the\r\n                                                 word length is set to 8 data bits). */\r\n \r\n  uint16_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.\r\n                                           This parameter can be a value of @ref IRDA_Transfer_Mode */\r\n  \r\n  uint8_t  Prescaler;                 /*!< Specifies the Prescaler value for dividing the UART/USART source clock\r\n                                           to achieve low-power frequency.\r\n                                           @note Prescaler value 0 is forbidden */\r\n  \r\n  uint16_t PowerMode;                 /*!< Specifies the IRDA power mode.\r\n                                           This parameter can be a value of @ref IRDA_Low_Power */\r\n}IRDA_InitTypeDef;\r\n\r\n/** \r\n  * @brief HAL IRDA State structures definition \r\n  * @note  HAL IRDA State value is a combination of 2 different substates: gState and RxState.\r\n  *        - gState contains IRDA state information related to global Handle management \r\n  *          and also information related to Tx operations.\r\n  *          gState value coding follow below described bitmap :\r\n  *          b7-b6  Error information \r\n  *             00 : No Error\r\n  *             01 : (Not Used)\r\n  *             10 : Timeout\r\n  *             11 : Error\r\n  *          b5     IP initilisation status\r\n  *             0  : Reset (IP not initialized)\r\n  *             1  : Init done (IP not initialized. HAL IRDA Init function already called)\r\n  *          b4-b3  (not used)\r\n  *             xx : Should be set to 00\r\n  *          b2     Intrinsic process state\r\n  *             0  : Ready\r\n  *             1  : Busy (IP busy with some configuration or internal operations)\r\n  *          b1     (not used)\r\n  *             x  : Should be set to 0\r\n  *          b0     Tx state\r\n  *             0  : Ready (no Tx operation ongoing)\r\n  *             1  : Busy (Tx operation ongoing)\r\n  *        - RxState contains information related to Rx operations.\r\n  *          RxState value coding follow below described bitmap :\r\n  *          b7-b6  (not used)\r\n  *             xx : Should be set to 00\r\n  *          b5     IP initilisation status\r\n  *             0  : Reset (IP not initialized)\r\n  *             1  : Init done (IP not initialized)\r\n  *          b4-b2  (not used)\r\n  *            xxx : Should be set to 000\r\n  *          b1     Rx state\r\n  *             0  : Ready (no Rx operation ongoing)\r\n  *             1  : Busy (Rx operation ongoing)\r\n  *          b0     (not used)\r\n  *             x  : Should be set to 0.\r\n  */ \r\ntypedef enum\r\n{\r\n  HAL_IRDA_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized \r\n                                                   Value is allowed for gState and RxState */\r\n  HAL_IRDA_STATE_READY             = 0x20U,    /*!< Peripheral Initialized and ready for use \r\n                                                   Value is allowed for gState and RxState */\r\n  HAL_IRDA_STATE_BUSY              = 0x24U,    /*!< An internal process is ongoing \r\n                                                   Value is allowed for gState only */\r\n  HAL_IRDA_STATE_BUSY_TX           = 0x21U,    /*!< Data Transmission process is ongoing \r\n                                                   Value is allowed for gState only */\r\n  HAL_IRDA_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing \r\n                                                   Value is allowed for RxState only */\r\n  HAL_IRDA_STATE_BUSY_TX_RX        = 0x23U,    /*!< Data Transmission and Reception process is ongoing \r\n                                                   Not to be used for neither gState nor RxState.\r\n                                                   Value is result of combination (Or) between gState and RxState values */\r\n  HAL_IRDA_STATE_TIMEOUT           = 0xA0U,    /*!< Timeout state \r\n                                                   Value is allowed for gState only */\r\n  HAL_IRDA_STATE_ERROR             = 0xE0U     /*!< Error \r\n                                                   Value is allowed for gState only */\r\n}HAL_IRDA_StateTypeDef;\r\n\r\n/**\r\n  * @brief IRDA clock sources definition\r\n  */\r\ntypedef enum\r\n{\r\n  IRDA_CLOCKSOURCE_PCLK1      = 0x00U,    /*!< PCLK1 clock source  */\r\n  IRDA_CLOCKSOURCE_PCLK2      = 0x01U,    /*!< PCLK2 clock source  */\r\n  IRDA_CLOCKSOURCE_HSI        = 0x02U,    /*!< HSI clock source    */\r\n  IRDA_CLOCKSOURCE_SYSCLK     = 0x04U,    /*!< SYSCLK clock source */\r\n  IRDA_CLOCKSOURCE_LSE        = 0x08U,    /*!< LSE clock source     */\r\n  IRDA_CLOCKSOURCE_UNDEFINED  = 0x10      /*!< Undefined clock source */\r\n}IRDA_ClockSourceTypeDef;\r\n\r\n/** \r\n  * @brief  IRDA handle Structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  USART_TypeDef            *Instance;        /* IRDA registers base address        */\r\n\r\n  IRDA_InitTypeDef         Init;             /* IRDA communication parameters      */\r\n\r\n  uint8_t                  *pTxBuffPtr;      /* Pointer to IRDA Tx transfer Buffer */\r\n\r\n  uint16_t                 TxXferSize;       /* IRDA Tx Transfer size              */\r\n\r\n  __IO uint16_t            TxXferCount;      /* IRDA Tx Transfer Counter           */\r\n\r\n  uint8_t                  *pRxBuffPtr;      /* Pointer to IRDA Rx transfer Buffer */\r\n\r\n  uint16_t                 RxXferSize;       /* IRDA Rx Transfer size              */\r\n\r\n  __IO uint16_t            RxXferCount;      /* IRDA Rx Transfer Counter           */\r\n\r\n  uint16_t                 Mask;             /* IRDA RX RDR register mask         */\r\n\r\n  DMA_HandleTypeDef        *hdmatx;          /* IRDA Tx DMA Handle parameters      */\r\n\r\n  DMA_HandleTypeDef        *hdmarx;          /* IRDA Rx DMA Handle parameters      */\r\n\r\n  HAL_LockTypeDef          Lock;             /* Locking object                     */\r\n\r\n  __IO HAL_IRDA_StateTypeDef  gState;           /* IRDA state information related to global Handle management \r\n                                                   and also related to Tx operations.\r\n                                                   This parameter can be a value of @ref HAL_IRDA_StateTypeDef */\r\n\r\n  __IO HAL_IRDA_StateTypeDef  RxState;          /* IRDA state information related to Rx operations.\r\n                                                   This parameter can be a value of @ref HAL_IRDA_StateTypeDef */\r\n\r\n  __IO uint32_t    ErrorCode;   /* IRDA Error code                    */\r\n\r\n}IRDA_HandleTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** \r\n  * @brief  IRDA Configuration enumeration values definition  \r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup IRDA_Exported_Constants IRDA Exported constants\r\n  * @{\r\n  */\r\n/** @defgroup IRDA_Error_Code IRDA Error Code\r\n  * @brief    IRDA Error Code \r\n  * @{\r\n  */ \r\n\r\n#define HAL_IRDA_ERROR_NONE      ((uint32_t)0x00000000U)    /*!< No error            */\r\n#define HAL_IRDA_ERROR_PE        ((uint32_t)0x00000001U)    /*!< Parity error        */\r\n#define HAL_IRDA_ERROR_NE        ((uint32_t)0x00000002U)    /*!< Noise error         */\r\n#define HAL_IRDA_ERROR_FE        ((uint32_t)0x00000004U)    /*!< frame error         */\r\n#define HAL_IRDA_ERROR_ORE       ((uint32_t)0x00000008U)    /*!< Overrun error       */\r\n#define HAL_IRDA_ERROR_DMA       ((uint32_t)0x00000010U)    /*!< DMA transfer error  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup IRDA_Parity IRDA Parity\r\n  * @{\r\n  */ \r\n#define IRDA_PARITY_NONE                    ((uint32_t)0x0000U)\r\n#define IRDA_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)\r\n#define IRDA_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode\r\n  * @{\r\n  */ \r\n#define IRDA_MODE_RX                        ((uint32_t)USART_CR1_RE)\r\n#define IRDA_MODE_TX                        ((uint32_t)USART_CR1_TE)\r\n#define IRDA_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup IRDA_Low_Power IRDA Low Power\r\n  * @{\r\n  */\r\n#define IRDA_POWERMODE_NORMAL                    ((uint32_t)0x0000U)\r\n#define IRDA_POWERMODE_LOWPOWER                  ((uint32_t)USART_CR3_IRLP)\r\n/**\r\n  * @}\r\n  */\r\n    \r\n /** @defgroup IRDA_State IRDA State\r\n  * @{\r\n  */ \r\n#define IRDA_STATE_DISABLE                  ((uint32_t)0x0000U)\r\n#define IRDA_STATE_ENABLE                   ((uint32_t)USART_CR1_UE)\r\n/**\r\n  * @}\r\n  */\r\n\r\n /** @defgroup IRDA_Mode IRDA Mode\r\n  * @{\r\n  */ \r\n#define IRDA_MODE_DISABLE                  ((uint32_t)0x0000U)\r\n#define IRDA_MODE_ENABLE                   ((uint32_t)USART_CR3_IREN)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup IRDA_One_Bit IRDA One Bit\r\n  * @{\r\n  */\r\n#define IRDA_ONE_BIT_SAMPLE_DISABLE          ((uint32_t)0x00000000U)\r\n#define IRDA_ONE_BIT_SAMPLE_ENABLE           ((uint32_t)USART_CR3_ONEBIT)\r\n/**\r\n  * @}\r\n  */  \r\n  \r\n/** @defgroup IRDA_DMA_Tx IRDA DMA Tx\r\n  * @{\r\n  */\r\n#define IRDA_DMA_TX_DISABLE          ((uint32_t)0x00000000U)\r\n#define IRDA_DMA_TX_ENABLE           ((uint32_t)USART_CR3_DMAT)\r\n/**\r\n  * @}\r\n  */  \r\n  \r\n/** @defgroup IRDA_DMA_Rx IRDA DMA Rx\r\n  * @{\r\n  */\r\n#define IRDA_DMA_RX_DISABLE           ((uint32_t)0x0000U)\r\n#define IRDA_DMA_RX_ENABLE            ((uint32_t)USART_CR3_DMAR)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup IRDA_Flags IRDA Flags\r\n  *        Elements values convention: 0xXXXX\r\n  *           - 0xXXXX  : Flag mask in the ISR register\r\n  * @{\r\n  */\r\n#define IRDA_FLAG_REACK                     ((uint32_t)0x00400000U)\r\n#define IRDA_FLAG_TEACK                     ((uint32_t)0x00200000U)  \r\n#define IRDA_FLAG_BUSY                      ((uint32_t)0x00010000U)\r\n#define IRDA_FLAG_ABRF                      ((uint32_t)0x00008000U)  \r\n#define IRDA_FLAG_ABRE                      ((uint32_t)0x00004000U)\r\n#define IRDA_FLAG_TXE                       ((uint32_t)0x00000080U)\r\n#define IRDA_FLAG_TC                        ((uint32_t)0x00000040U)\r\n#define IRDA_FLAG_RXNE                      ((uint32_t)0x00000020U)\r\n#define IRDA_FLAG_ORE                       ((uint32_t)0x00000008U)\r\n#define IRDA_FLAG_NE                        ((uint32_t)0x00000004U)\r\n#define IRDA_FLAG_FE                        ((uint32_t)0x00000002U)\r\n#define IRDA_FLAG_PE                        ((uint32_t)0x00000001U)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup IRDA_Interrupt_definition IRDA Interrupt definition\r\n  *        Elements values convention: 0000ZZZZ0XXYYYYYb\r\n  *           - YYYYY  : Interrupt source position in the XX register (5bits)\r\n  *           - XX  : Interrupt source register (2bits)\r\n  *                 - 01: CR1 register\r\n  *                 - 10: CR2 register\r\n  *                 - 11: CR3 register\r\n  *           - ZZZZ  : Flag position in the ISR register(4bits)\r\n  * @{   \r\n  */  \r\n#define IRDA_IT_PE                          ((uint16_t)0x0028U)\r\n#define IRDA_IT_TXE                         ((uint16_t)0x0727U)\r\n#define IRDA_IT_TC                          ((uint16_t)0x0626U)\r\n#define IRDA_IT_RXNE                        ((uint16_t)0x0525U)\r\n#define IRDA_IT_IDLE                        ((uint16_t)0x0424U)\r\n\r\n\r\n                                \r\n/**       Elements values convention: 000000000XXYYYYYb\r\n  *           - YYYYY  : Interrupt source position in the XX register (5bits)\r\n  *           - XX  : Interrupt source register (2bits)\r\n  *                 - 01: CR1 register\r\n  *                 - 10: CR2 register\r\n  *                 - 11: CR3 register\r\n  */\r\n#define IRDA_IT_ERR                         ((uint16_t)0x0060U)\r\n\r\n/**       Elements values convention: 0000ZZZZ00000000b\r\n  *           - ZZZZ  : Flag position in the ISR register(4bits)\r\n  */\r\n#define IRDA_IT_ORE                         ((uint16_t)0x0300U)\r\n#define IRDA_IT_NE                          ((uint16_t)0x0200U)\r\n#define IRDA_IT_FE                          ((uint16_t)0x0100U)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup IRDA_IT_CLEAR_Flags IRDA IT CLEAR Flags\r\n  * @{\r\n  */\r\n#define IRDA_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag */          \r\n#define IRDA_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag */         \r\n#define IRDA_CLEAR_NEF                       USART_ICR_NCF             /*!< Noise detected Clear Flag */        \r\n#define IRDA_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag */         \r\n#define IRDA_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n\r\n/** @defgroup IRDA_Request_Parameters IRDA Request Parameters\r\n  * @{\r\n  */\r\n#define IRDA_AUTOBAUD_REQUEST            ((uint16_t)USART_RQR_ABRRQ)        /*!< Auto-Baud Rate Request */     \r\n#define IRDA_RXDATA_FLUSH_REQUEST        ((uint16_t)USART_RQR_RXFRQ)        /*!< Receive Data flush Request */ \r\n#define IRDA_TXDATA_FLUSH_REQUEST        ((uint16_t)USART_RQR_TXFRQ)        /*!< Transmit data flush Request */\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n * @}\r\n */\r\n\r\n  \r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup IRDA_Exported_Macros IRDA Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief Reset IRDA handle state\r\n  * @param  __HANDLE__ specifies the IRDA Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @retval None\r\n  */\r\n#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET)\r\n\r\n/** @brief  Flush the IRDA DR register.\r\n  * @param  __HANDLE__ specifies the IRDA Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__)                            \\\r\n    do{                                                                    \\\r\n         SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \\\r\n         SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \\\r\n      } while(0)\r\n\r\n/** @brief  Clear the specified IRDA pending flag.\r\n  * @param  __HANDLE__ specifies the IRDA Handle.\r\n  * @param  __FLAG__ specifies the flag to check.\r\n  *          This parameter can be any combination of the following values:\r\n  *            @arg @ref IRDA_CLEAR_PEF\r\n  *            @arg @ref IRDA_CLEAR_FEF\r\n  *            @arg @ref IRDA_CLEAR_NEF\r\n  *            @arg @ref IRDA_CLEAR_OREF\r\n  *            @arg @ref IRDA_CLEAR_TCF\r\n  * @retval None\r\n  */\r\n#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))\r\n\r\n/** @brief  Clear the IRDA PE pending flag.\r\n  * @param  __HANDLE__ specifies the IRDA Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)\r\n\r\n\r\n/** @brief  Clear the IRDA FE pending flag.\r\n  * @param  __HANDLE__ specifies the IRDA Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)\r\n\r\n/** @brief  Clear the IRDA NE pending flag.\r\n  * @param  __HANDLE__ specifies the IRDA Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)\r\n\r\n/** @brief  Clear the IRDA ORE pending flag.\r\n  * @param  __HANDLE__ specifies the IRDA Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)\r\n\r\n/** @brief  Clear the IRDA IDLE pending flag.\r\n  * @param  __HANDLE__ specifies the IRDA Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)\r\n\r\n/** @brief  Check whether the specified IRDA flag is set or not.\r\n  * @param  __HANDLE__ specifies the IRDA Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  *         UART peripheral\r\n  * @param  __FLAG__ specifies the flag to check.\r\n  *        This parameter can be one of the following values:\r\n  *            @arg IRDA_FLAG_REACK: Receive enable acknowledge flag\r\n  *            @arg IRDA_FLAG_TEACK: Transmit enable acknowledge flag\r\n  *            @arg IRDA_FLAG_BUSY:  Busy flag\r\n  *            @arg IRDA_FLAG_ABRF:  Auto Baud rate detection flag\r\n  *            @arg IRDA_FLAG_ABRE:  Auto Baud rate detection error flag\r\n  *            @arg IRDA_FLAG_TXE:   Transmit data register empty flag\r\n  *            @arg IRDA_FLAG_TC:    Transmission Complete flag\r\n  *            @arg IRDA_FLAG_RXNE:  Receive data register not empty flag\r\n  *            @arg IRDA_FLAG_IDLE:  Idle Line detection flag\r\n  *            @arg IRDA_FLAG_ORE:   OverRun Error flag\r\n  *            @arg IRDA_FLAG_NE:    Noise Error flag\r\n  *            @arg IRDA_FLAG_FE:    Framing Error flag\r\n  *            @arg IRDA_FLAG_PE:    Parity Error flag\r\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))   \r\n\r\n/** @brief  Enable the specified IRDA interrupt.\r\n  * @param  __HANDLE__ specifies the IRDA Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  *         UART peripheral\r\n  * @param  __INTERRUPT__ specifies the IRDA interrupt source to enable.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg IRDA_IT_TXE:  Transmit Data Register empty interrupt\r\n  *            @arg IRDA_IT_TC:   Transmission complete interrupt\r\n  *            @arg IRDA_IT_RXNE: Receive Data register not empty interrupt\r\n  *            @arg IRDA_IT_IDLE: Idle line detection interrupt\r\n  *            @arg IRDA_IT_PE:   Parity Error interrupt\r\n  *            @arg IRDA_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)\r\n  * @retval None\r\n  */\r\n#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 |= (1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \\\r\n                                                          ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 |= (1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \\\r\n                                                          ((__HANDLE__)->Instance->CR3 |= (1 << ((__INTERRUPT__) & IRDA_IT_MASK))))\r\n\r\n/** @brief  Disable the specified IRDA interrupt.\r\n  * @param  __HANDLE__ specifies the IRDA Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @param  __INTERRUPT__ specifies the IRDA interrupt source to disable.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg IRDA_IT_TXE:  Transmit Data Register empty interrupt\r\n  *            @arg IRDA_IT_TC:   Transmission complete interrupt\r\n  *            @arg IRDA_IT_RXNE: Receive Data register not empty interrupt\r\n  *            @arg IRDA_IT_IDLE: Idle line detection interrupt\r\n  *            @arg IRDA_IT_PE:   Parity Error interrupt\r\n  *            @arg IRDA_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)\r\n  * @retval None\r\n  */\r\n#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \\\r\n                                                           ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \\\r\n                                                           ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & IRDA_IT_MASK))))\r\n\r\n/** @brief  Check whether the specified IRDA interrupt has occurred or not.\r\n  * @param  __HANDLE__ specifies the IRDA Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @param  __IT__ specifies the IRDA interrupt source to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg IRDA_IT_TXE: Transmit Data Register empty interrupt\r\n  *            @arg IRDA_IT_TC:  Transmission complete interrupt\r\n  *            @arg IRDA_IT_RXNE: Receive Data register not empty interrupt\r\n  *            @arg IRDA_IT_IDLE: Idle line detection interrupt\r\n  *            @arg IRDA_IT_ORE: OverRun Error interrupt\r\n  *            @arg IRDA_IT_NE: Noise Error interrupt\r\n  *            @arg IRDA_IT_FE: Framing Error interrupt\r\n  *            @arg IRDA_IT_PE: Parity Error interrupt  \r\n  * @retval The new state of __IT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) \r\n\r\n/** @brief  Check whether the specified IRDA interrupt source is enabled.\r\n  * @param  __HANDLE__ specifies the IRDA Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @param  __IT__ specifies the IRDA interrupt source to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg IRDA_IT_TXE: Transmit Data Register empty interrupt\r\n  *            @arg IRDA_IT_TC:  Transmission complete interrupt\r\n  *            @arg IRDA_IT_RXNE: Receive Data register not empty interrupt\r\n  *            @arg IRDA_IT_IDLE: Idle line detection interrupt\r\n  *            @arg IRDA_IT_ORE: OverRun Error interrupt\r\n  *            @arg IRDA_IT_NE: Noise Error interrupt\r\n  *            @arg IRDA_IT_FE: Framing Error interrupt\r\n  *            @arg IRDA_IT_PE: Parity Error interrupt  \r\n  * @retval The new state of __IT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \\\r\n                                                          (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & IRDA_IT_MASK)))\r\n\r\n/** @brief  Clear the specified IRDA ISR flag, in setting the proper ICR register flag.\r\n  * @param  __HANDLE__ specifies the IRDA Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set\r\n  *                       to clear the corresponding interrupt\r\n  *          This parameter can be one of the following values:\r\n  *            @arg IRDA_CLEAR_PEF: Parity Error Clear Flag\r\n  *            @arg IRDA_CLEAR_FEF: Framing Error Clear Flag\r\n  *            @arg IRDA_CLEAR_NEF: Noise detected Clear Flag\r\n  *            @arg IRDA_CLEAR_OREF: OverRun Error Clear Flag\r\n  *            @arg IRDA_CLEAR_TCF: Transmission Complete Clear Flag \r\n  * @retval None\r\n  */\r\n#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))\r\n\r\n/** @brief  Set a specific IRDA request flag.\r\n  * @param  __HANDLE__ specifies the IRDA Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @param  __REQ__ specifies the request flag to set\r\n  *          This parameter can be one of the following values:\r\n  *            @arg IRDA_AUTOBAUD_REQUEST: Auto-Baud Rate Request     \r\n  *            @arg IRDA_RXDATA_FLUSH_REQUEST: Receive Data flush Request \r\n  *            @arg IRDA_TXDATA_FLUSH_REQUEST: Transmit data flush Request \r\n  *\r\n  * @retval None\r\n  */\r\n#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) \r\n\r\n/** @brief  Enable UART/USART associated to IRDA Handle\r\n  * @param  __HANDLE__ specifies the IRDA Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @retval None\r\n  */\r\n#define __HAL_IRDA_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)\r\n\r\n/** @brief  Disable UART/USART associated to IRDA Handle\r\n  * @param  __HANDLE__ specifies the IRDA Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @retval None\r\n  */\r\n#define __HAL_IRDA_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Include IRDA HAL Extension module */\r\n#include \"stm32f7xx_hal_irda_ex.h\"  \r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions\r\n  * @{\r\n  */\r\n\r\n/* Initialization and de-initialization functions  ****************************/\r\nHAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);\r\nHAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);\r\nvoid HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);\r\nvoid HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions\r\n  * @{\r\n  */\r\n\r\n/* IO operation functions *****************************************************/\r\nHAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);\r\nHAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);\r\nHAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);\r\n/* Transfer Abort functions */\r\nHAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);\r\nHAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);\r\nHAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);\r\nHAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);\r\nHAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);\r\nHAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);\r\n\r\nvoid HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);\r\nvoid HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);\r\nvoid HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);\r\nvoid HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);\r\nvoid HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);\r\nvoid HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);\r\nvoid HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda);\r\nvoid HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda);\r\nvoid HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda);\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n/** @addtogroup IRDA_Exported_Functions_Group3 Peripheral Control functions\r\n * @{\r\n */\r\n/* Peripheral State methods  **************************************************/\r\nHAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);\r\nuint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup IRDA_Private_Constants IRDA Private Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup IRDA_Interruption_Mask IRDA Interruption Mask\r\n  * @{\r\n  */ \r\n#define IRDA_IT_MASK  ((uint16_t)0x001FU)\r\n/**\r\n  * @}\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros --------------------------------------------------------*/\r\n/** @defgroup IRDA_Private_Macros   IRDA Private Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief  Ensure that IRDA Baud rate is less or equal to maximum value\r\n  * @param  __BAUDRATE__ specifies the IRDA Baudrate set by the user.\r\n  * @retval True or False\r\n  */   \r\n#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201)\r\n\r\n/** @brief  Ensure that IRDA prescaler value is strictly larger than 0\r\n  * @param  __PRESCALER__ specifies the IRDA prescaler value set by the user.\r\n  * @retval True or False\r\n  */  \r\n#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0)\r\n\r\n#define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \\\r\n                                    ((__PARITY__) == IRDA_PARITY_EVEN) || \\\r\n                                    ((__PARITY__) == IRDA_PARITY_ODD))\r\n\t\t\t\t\t\t\t\t\r\n#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00U))\r\n\r\n#define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \\\r\n                                     ((__MODE__) == IRDA_POWERMODE_NORMAL))\r\n\t\t\t\t\t\t\t\t\t \r\n#define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \\\r\n                                  ((__STATE__) == IRDA_STATE_ENABLE))\r\n\t\t\t\t\t\t\t\t  \r\n#define IS_IRDA_MODE(__STATE__)  (((__STATE__) == IRDA_MODE_DISABLE) || \\\r\n                                  ((__STATE__) == IRDA_MODE_ENABLE))\r\n\t\t\t\t\t\t\t\t  \r\n#define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__)     (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \\\r\n                                               ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))\r\n\r\n#define IS_IRDA_DMA_TX(__DMATX__)     (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \\\r\n                                       ((__DMATX__) == IRDA_DMA_TX_ENABLE))\t\t\r\n\r\n#define IS_IRDA_DMA_RX(__DMARX__)     (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \\\r\n                                       ((__DMARX__) == IRDA_DMA_RX_ENABLE))\r\n\r\n#define IS_IRDA_REQUEST_PARAMETER(PARAM) (((PARAM) == IRDA_AUTOBAUD_REQUEST) || \\\r\n                                          ((PARAM) == IRDA_SENDBREAK_REQUEST) || \\\r\n                                          ((PARAM) == IRDA_MUTE_MODE_REQUEST) || \\\r\n                                          ((PARAM) == IRDA_RXDATA_FLUSH_REQUEST) || \\\r\n                                          ((PARAM) == IRDA_TXDATA_FLUSH_REQUEST))\t\t\t\t\t\t\t\t\t   \r\n/**\r\n * @}\r\n */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup IRDA_Private_Functions IRDA Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_IRDA_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_irda_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_irda_ex.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of IRDA HAL Extension module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *                               \r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************  \r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_IRDA_EX_H\r\n#define __STM32F7xx_HAL_IRDA_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup IRDAEx\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup IRDAEx_Extended_Exported_Constants IRDAEx Extended Exported Constants\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup IRDAEx_Word_Length IRDAEx Word Length\r\n  * @{\r\n  */\r\n#define IRDA_WORDLENGTH_7B                  ((uint32_t)USART_CR1_M_1)\r\n#define IRDA_WORDLENGTH_8B                  ((uint32_t)0x00000000U)\r\n#define IRDA_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M_0)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n  \r\n/**\r\n  * @}\r\n  */  \r\n  \r\n/* Exported macro ------------------------------------------------------------*/\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n\r\n/** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros\r\n  * @{\r\n  */\r\n/** @brief  Reports the IRDA clock source.\r\n  * @param  __HANDLE__ specifies the IRDA Handle\r\n  * @param  __CLOCKSOURCE__  output variable\r\n  * @retval IRDA clocking source, written in __CLOCKSOURCE__.\r\n  */\r\n#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \\\r\n  do {                                                        \\\r\n    if((__HANDLE__)->Instance == USART1)                      \\\r\n    {                                                         \\\r\n       switch(__HAL_RCC_GET_USART1_SOURCE())                  \\\r\n       {                                                      \\\r\n        case RCC_USART1CLKSOURCE_PCLK2:                       \\\r\n          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2;         \\\r\n          break;                                              \\\r\n        case RCC_USART1CLKSOURCE_HSI:                         \\\r\n          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \\\r\n          break;                                              \\\r\n        case RCC_USART1CLKSOURCE_SYSCLK:                      \\\r\n          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                              \\\r\n        case RCC_USART1CLKSOURCE_LSE:                         \\\r\n          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \\\r\n          break;                                              \\\r\n        default:                                              \\\r\n          break;                                              \\\r\n       }                                                      \\\r\n    }                                                         \\\r\n    else if((__HANDLE__)->Instance == USART2)                 \\\r\n    {                                                         \\\r\n       switch(__HAL_RCC_GET_USART2_SOURCE())                  \\\r\n       {                                                      \\\r\n        case RCC_USART2CLKSOURCE_PCLK1:                       \\\r\n          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \\\r\n          break;                                              \\\r\n        case RCC_USART2CLKSOURCE_HSI:                         \\\r\n          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \\\r\n          break;                                              \\\r\n        case RCC_USART2CLKSOURCE_SYSCLK:                      \\\r\n          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                              \\\r\n        case RCC_USART2CLKSOURCE_LSE:                         \\\r\n          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \\\r\n          break;                                              \\\r\n        default:                                              \\\r\n          break;                                              \\\r\n       }                                                      \\\r\n    }                                                         \\\r\n    else if((__HANDLE__)->Instance == USART3)                 \\\r\n    {                                                         \\\r\n       switch(__HAL_RCC_GET_USART3_SOURCE())                  \\\r\n       {                                                      \\\r\n        case RCC_USART3CLKSOURCE_PCLK1:                       \\\r\n          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \\\r\n          break;                                              \\\r\n        case RCC_USART3CLKSOURCE_HSI:                         \\\r\n          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \\\r\n          break;                                              \\\r\n        case RCC_USART3CLKSOURCE_SYSCLK:                      \\\r\n          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                              \\\r\n        case RCC_USART3CLKSOURCE_LSE:                         \\\r\n          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \\\r\n          break;                                              \\\r\n        default:                                              \\\r\n          break;                                              \\\r\n       }                                                      \\\r\n    }                                                         \\\r\n    else if((__HANDLE__)->Instance == USART6)                 \\\r\n    {                                                         \\\r\n       switch(__HAL_RCC_GET_USART6_SOURCE())                  \\\r\n       {                                                      \\\r\n        case RCC_USART6CLKSOURCE_PCLK2:                       \\\r\n          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2;         \\\r\n          break;                                              \\\r\n        case RCC_USART6CLKSOURCE_HSI:                         \\\r\n          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \\\r\n          break;                                              \\\r\n        case RCC_USART6CLKSOURCE_SYSCLK:                      \\\r\n          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                              \\\r\n        case RCC_USART6CLKSOURCE_LSE:                         \\\r\n          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \\\r\n          break;                                              \\\r\n        default:                                              \\\r\n          break;                                              \\\r\n       }                                                      \\\r\n    }                                                         \\\r\n\t} while(0)\r\n\r\n/** @brief  Reports the mask to apply to retrieve the received data\r\n  *         according to the word length and to the parity bits activation.\r\n  * @param  __HANDLE__ specifies the IRDA Handle\r\n  * @retval mask to apply to USART RDR register value.\r\n  */    \r\n#define IRDA_MASK_COMPUTATION(__HANDLE__)                       \\\r\n  do {                                                                \\\r\n  if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B)            \\\r\n  {                                                                   \\\r\n     if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x01FF ;                                 \\\r\n     }                                                                \\\r\n     else                                                             \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x00FF ;                                 \\\r\n     }                                                                \\\r\n  }                                                                   \\\r\n  else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B)       \\\r\n  {                                                                   \\\r\n     if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x00FF ;                                 \\\r\n     }                                                                \\\r\n     else                                                             \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x007F ;                                 \\\r\n     }                                                                \\\r\n  }                                                                   \\\r\n  else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B)       \\\r\n  {                                                                   \\\r\n     if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x007F ;                                 \\\r\n     }                                                                \\\r\n     else                                                             \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x003F ;                                 \\\r\n     }                                                                \\\r\n  }                                                                   \\\r\n} while(0)\r\n\r\n#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_7B) || \\\r\n                                     ((LENGTH) == IRDA_WORDLENGTH_8B) || \\\r\n                                     ((LENGTH) == IRDA_WORDLENGTH_9B))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_IRDA_EX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_iwdg.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_iwdg.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of IWDG HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_IWDG_H\r\n#define __STM32F7xx_HAL_IWDG_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup IWDG IWDG\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup IWDG_Exported_Types IWDG Exported Types\r\n  * @{\r\n  */\r\n\r\n/** \r\n  * @brief  IWDG Init structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t Prescaler;  /*!< Select the prescaler of the IWDG.\r\n                            This parameter can be a value of @ref IWDG_Prescaler */\r\n\r\n  uint32_t Reload;     /*!< Specifies the IWDG down-counter reload value.\r\n                            This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */\r\n\r\n  uint32_t Window;     /*!< Specifies the window value to be compared to the down-counter.\r\n                            This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */\r\n\r\n} IWDG_InitTypeDef;\r\n\r\n/** \r\n  * @brief  IWDG Handle Structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  IWDG_TypeDef                 *Instance;  /*!< Register base address    */\r\n\r\n  IWDG_InitTypeDef             Init;       /*!< IWDG required parameters */\r\n\r\n}IWDG_HandleTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup IWDG_Exported_Constants IWDG Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup IWDG_Prescaler IWDG Prescaler\r\n  * @{\r\n  */\r\n#define IWDG_PRESCALER_4                0x00000000u                   /*!< IWDG prescaler set to 4   */\r\n#define IWDG_PRESCALER_8                IWDG_PR_PR_0                  /*!< IWDG prescaler set to 8   */\r\n#define IWDG_PRESCALER_16               IWDG_PR_PR_1                  /*!< IWDG prescaler set to 16  */\r\n#define IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32  */\r\n#define IWDG_PRESCALER_64               IWDG_PR_PR_2                  /*!< IWDG prescaler set to 64  */\r\n#define IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */\r\n#define IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup IWDG_Window_option IWDG Window option\r\n  * @{\r\n  */\r\n#define IWDG_WINDOW_DISABLE             IWDG_WINR_WIN\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macros -----------------------------------------------------------*/\r\n/** @defgroup IWDG_Exported_Macros IWDG Exported Macros\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Enable the IWDG peripheral.\r\n  * @param  __HANDLE__ IWDG handle\r\n  * @retval None\r\n  */\r\n#define __HAL_IWDG_START(__HANDLE__)                WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)\r\n\r\n/**\r\n  * @brief  Reload IWDG counter with value defined in the reload register\r\n  *         (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled).\r\n  * @param  __HANDLE__  IWDG handle\r\n  * @retval None\r\n  */\r\n#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__)       WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup IWDG_Exported_Functions  IWDG Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions\r\n  * @{\r\n  */\r\n/* Initialization/Start functions  ********************************************/\r\nHAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions\r\n  * @{\r\n  */\r\n/* I/O operation functions ****************************************************/\r\nHAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup IWDG_Private_Constants IWDG Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  IWDG Key Register BitMask\r\n  */\r\n#define IWDG_KEY_RELOAD                 0x0000AAAAu  /*!< IWDG Reload Counter Enable   */\r\n#define IWDG_KEY_ENABLE                 0x0000CCCCu  /*!< IWDG Peripheral Enable       */\r\n#define IWDG_KEY_WRITE_ACCESS_ENABLE    0x00005555u  /*!< IWDG KR Write Access Enable  */\r\n#define IWDG_KEY_WRITE_ACCESS_DISABLE   0x00000000u  /*!< IWDG KR Write Access Disable */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup IWDG_Private_Macros IWDG Private Macros\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.\r\n  * @param  __HANDLE__ IWDG handle\r\n  * @retval None\r\n  */\r\n#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__)  WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)\r\n\r\n/**\r\n  * @brief  Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.\r\n  * @param  __HANDLE__ IWDG handle\r\n  * @retval None\r\n  */\r\n#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)\r\n\r\n/**\r\n  * @brief  Check IWDG prescaler value.\r\n  * @param  __PRESCALER__ IWDG prescaler value\r\n  * @retval None\r\n  */\r\n#define IS_IWDG_PRESCALER(__PRESCALER__)      (((__PRESCALER__) == IWDG_PRESCALER_4)  || \\\r\n                                               ((__PRESCALER__) == IWDG_PRESCALER_8)  || \\\r\n                                               ((__PRESCALER__) == IWDG_PRESCALER_16) || \\\r\n                                               ((__PRESCALER__) == IWDG_PRESCALER_32) || \\\r\n                                               ((__PRESCALER__) == IWDG_PRESCALER_64) || \\\r\n                                               ((__PRESCALER__) == IWDG_PRESCALER_128)|| \\\r\n                                               ((__PRESCALER__) == IWDG_PRESCALER_256))\r\n\r\n/**\r\n  * @brief  Check IWDG reload value.\r\n  * @param  __RELOAD__ IWDG reload value\r\n  * @retval None\r\n  */\r\n#define IS_IWDG_RELOAD(__RELOAD__)            ((__RELOAD__) <= IWDG_RLR_RL)\r\n\r\n/**\r\n  * @brief  Check IWDG window value.\r\n  * @param  __WINDOW__ IWDG window value\r\n  * @retval None\r\n  */\r\n#define IS_IWDG_WINDOW(__WINDOW__)            ((__WINDOW__) <= IWDG_WINR_WIN)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_IWDG_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_lptim.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_lptim.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of LPTIM HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_LPTIM_H\r\n#define __STM32F7xx_HAL_LPTIM_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup LPTIM LPTIM\r\n  * @brief LPTIM HAL module driver\r\n  * @{\r\n  */\r\n  \r\n/* Exported types ------------------------------------------------------------*/ \r\n/** @defgroup LPTIM_Exported_Types LPTIM Exported Types\r\n  * @{\r\n  */\r\n\r\n/** @defgroup LPTIM_WAKEUPTIMER_EXTILINE LPTIM WAKEUP Timer EXTI Line\r\n  * @{\r\n  */\r\n#define LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT  ((uint32_t)EXTI_IMR_MR23)  /*!< External interrupt line 23 Connected to the LPTIM EXTI Line */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** \r\n  * @brief  LPTIM Clock configuration definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t Source;         /*!< Selects the clock source.\r\n                           This parameter can be a value of @ref LPTIM_Clock_Source   */\r\n\r\n  uint32_t Prescaler;      /*!< Specifies the counter clock Prescaler.\r\n                           This parameter can be a value of @ref LPTIM_Clock_Prescaler */\r\n  \r\n}LPTIM_ClockConfigTypeDef;\r\n\r\n/** \r\n  * @brief  LPTIM Clock configuration definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t Polarity;      /*!< Selects the polarity of the active edge for the counter unit\r\n                           if the ULPTIM input is selected.\r\n                           Note: This parameter is used only when Ultra low power clock source is used.\r\n                           Note: If the polarity is configured on 'both edges', an auxiliary clock\r\n                           (one of the Low power oscillator) must be active.\r\n                           This parameter can be a value of @ref LPTIM_Clock_Polarity */ \r\n  \r\n  uint32_t SampleTime;     /*!< Selects the clock sampling time to configure the clock glitch filter.\r\n                           Note: This parameter is used only when Ultra low power clock source is used.\r\n                           This parameter can be a value of @ref LPTIM_Clock_Sample_Time */  \r\n  \r\n}LPTIM_ULPClockConfigTypeDef;\r\n\r\n/** \r\n  * @brief  LPTIM Trigger configuration definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t Source;        /*!< Selects the Trigger source.\r\n                          This parameter can be a value of @ref LPTIM_Trigger_Source */\r\n  \r\n  uint32_t ActiveEdge;    /*!< Selects the Trigger active edge.\r\n                          Note: This parameter is used only when an external trigger is used.\r\n                          This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */\r\n  \r\n  uint32_t SampleTime;    /*!< Selects the trigger sampling time to configure the clock glitch filter.\r\n                          Note: This parameter is used only when an external trigger is used.\r\n                          This parameter can be a value of @ref LPTIM_Trigger_Sample_Time  */  \r\n}LPTIM_TriggerConfigTypeDef;\r\n\r\n/** \r\n  * @brief  LPTIM Initialization Structure definition  \r\n  */\r\ntypedef struct\r\n{                                                    \r\n  LPTIM_ClockConfigTypeDef     Clock;               /*!< Specifies the clock parameters */\r\n                                                    \r\n  LPTIM_ULPClockConfigTypeDef  UltraLowPowerClock;  /*!< Specifies the Ultra Low Power clock parameters */\r\n                                                    \r\n  LPTIM_TriggerConfigTypeDef   Trigger;             /*!< Specifies the Trigger parameters */\r\n                                                    \r\n  uint32_t                     OutputPolarity;      /*!< Specifies the Output polarity.\r\n                                                    This parameter can be a value of @ref LPTIM_Output_Polarity */\r\n                                                    \r\n  uint32_t                     UpdateMode;          /*!< Specifies whether the update of the autorelaod and the compare\r\n                                                    values is done immediately or after the end of current period.\r\n                                                    This parameter can be a value of @ref LPTIM_Updating_Mode */\r\n\r\n  uint32_t                     CounterSource;       /*!< Specifies whether the counter is incremented each internal event\r\n                                                    or each external event.\r\n                                                    This parameter can be a value of @ref LPTIM_Counter_Source */  \r\n  \r\n}LPTIM_InitTypeDef;\r\n\r\n/** \r\n  * @brief  HAL LPTIM State structure definition  \r\n  */ \r\ntypedef enum __HAL_LPTIM_StateTypeDef\r\n{\r\n  HAL_LPTIM_STATE_RESET            = 0x00U,    /*!< Peripheral not yet initialized or disabled  */\r\n  HAL_LPTIM_STATE_READY            = 0x01U,    /*!< Peripheral Initialized and ready for use    */\r\n  HAL_LPTIM_STATE_BUSY             = 0x02U,    /*!< An internal process is ongoing              */    \r\n  HAL_LPTIM_STATE_TIMEOUT          = 0x03U,    /*!< Timeout state                               */  \r\n  HAL_LPTIM_STATE_ERROR            = 0x04U     /*!< Internal Process is ongoing                */                                                                             \r\n}HAL_LPTIM_StateTypeDef;\r\n\r\n/** \r\n  * @brief  LPTIM handle Structure definition  \r\n  */ \r\ntypedef struct __LPTIM_HandleTypeDef\r\n{\r\n  LPTIM_TypeDef                 *Instance;      /*!< Register base address     */\r\n  LPTIM_InitTypeDef              Init;          /*!< LPTIM required parameters */\r\n  HAL_StatusTypeDef              Status;        /*!< LPTIM peripheral status   */\r\n  HAL_LockTypeDef                Lock;          /*!< LPTIM locking object      */\r\n  __IO  HAL_LPTIM_StateTypeDef   State;         /*!< LPTIM peripheral state    */\r\n\r\n#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)\r\n  void  (* MspInitCallback)         (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Msp Init Callback          */\r\n  void  (* MspDeInitCallback)       (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Msp DeInit Callback        */\r\n\r\n  void  (* CompareMatchCallback)    (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Compare Match Callback     */\r\n  void  (* AutoReloadMatchCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Auto Reload Match Callback */\r\n  void  (* TriggerCallback)         (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Trigger Callback           */\r\n  void  (* CompareWriteCallback)    (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Compare Write Callback     */\r\n  void  (* AutoReloadWriteCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Auto Reload Write Callback */\r\n  void  (* DirectionUpCallback)     (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Direction Up Callback      */\r\n  void  (* DirectionDownCallback)   (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Direction Down Callback    */\r\n#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */\r\n\r\n}LPTIM_HandleTypeDef;\r\n\r\n#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)\r\n/**\r\n  * @brief  HAL LPTIM Callback ID enumeration definition\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_LPTIM_MSPINIT_CB_ID           = 0x00U,    /*!< LPTIM MspInit Callback ID           */\r\n  HAL_LPTIM_MSPDEINIT_CB_ID         = 0x01U,    /*!< LPTIM MspDeInit Callback ID         */\r\n\r\n  HAL_LPTIM_COMPARE_MATCH_CB_ID     = 0x02U,    /*!< LPTIM Compare Match Callback ID     */\r\n  HAL_LPTIM_AUTO_RELOAD_MATCH_CB_ID = 0x03U,    /*!< LPTIM Auto Reload Match Callback ID */\r\n  HAL_LPTIM_TRIGGER_CB_ID           = 0x04U,    /*!< LPTIM Trigger Callback ID           */\r\n  HAL_LPTIM_COMPARE_WRITE_CB_ID     = 0x05U,    /*!< LPTIM Compare Write Callback ID     */\r\n  HAL_LPTIM_AUTO_RELOAD_WRITE_CB_ID = 0x06U,    /*!< LPTIM Auto Reload Write Callback ID */\r\n  HAL_LPTIM_DIRECTION_UP_CB_ID      = 0x07U,    /*!< LPTIM Direction Up Callback ID      */\r\n  HAL_LPTIM_DIRECTION_DOWN_CB_ID    = 0x08U,    /*!< LPTIM Direction Down Callback ID    */\r\n}HAL_LPTIM_CallbackIDTypeDef;\r\n\r\n/**\r\n  * @brief  HAL LPTIM Callback pointer definition\r\n  */\r\ntypedef  void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< pointer to the LPTIM callback function */\r\n\r\n#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup LPTIM_Clock_Source LPTIM Clock Source\r\n  * @{\r\n  */\r\n#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC        ((uint32_t)0x00U)\r\n#define LPTIM_CLOCKSOURCE_ULPTIM                LPTIM_CFGR_CKSEL                                           \r\n/**                                             \r\n  * @}\r\n  */\r\n\r\n/** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler\r\n  * @{\r\n  */\r\n#define LPTIM_PRESCALER_DIV1                    ((uint32_t)0x000000U)\r\n#define LPTIM_PRESCALER_DIV2                    LPTIM_CFGR_PRESC_0\r\n#define LPTIM_PRESCALER_DIV4                    LPTIM_CFGR_PRESC_1\r\n#define LPTIM_PRESCALER_DIV8                    ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1))\r\n#define LPTIM_PRESCALER_DIV16                   LPTIM_CFGR_PRESC_2\r\n#define LPTIM_PRESCALER_DIV32                   ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2))\r\n#define LPTIM_PRESCALER_DIV64                   ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2))\r\n#define LPTIM_PRESCALER_DIV128                  ((uint32_t)LPTIM_CFGR_PRESC)                                             \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity\r\n  * @{\r\n  */\r\n\r\n#define LPTIM_OUTPUTPOLARITY_HIGH               ((uint32_t)0x00000000U)\r\n#define LPTIM_OUTPUTPOLARITY_LOW                (LPTIM_CFGR_WAVPOL)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time\r\n  * @{\r\n  */\r\n#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U)\r\n#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS     LPTIM_CFGR_CKFLT_0\r\n#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS     LPTIM_CFGR_CKFLT_1\r\n#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS     LPTIM_CFGR_CKFLT\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity\r\n  * @{\r\n  */\r\n\r\n#define LPTIM_CLOCKPOLARITY_RISING                ((uint32_t)0x00000000U)\r\n#define LPTIM_CLOCKPOLARITY_FALLING               LPTIM_CFGR_CKPOL_0\r\n#define LPTIM_CLOCKPOLARITY_RISING_FALLING        LPTIM_CFGR_CKPOL_1\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source\r\n  * @{\r\n  */\r\n#define LPTIM_TRIGSOURCE_SOFTWARE               ((uint32_t)0x0000FFFFU)\r\n#define LPTIM_TRIGSOURCE_0                      ((uint32_t)0x00000000U)\r\n#define LPTIM_TRIGSOURCE_1                      ((uint32_t)LPTIM_CFGR_TRIGSEL_0)\r\n#define LPTIM_TRIGSOURCE_2                      LPTIM_CFGR_TRIGSEL_1\r\n#define LPTIM_TRIGSOURCE_3                      ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)\r\n#define LPTIM_TRIGSOURCE_4                      LPTIM_CFGR_TRIGSEL_2\r\n#define LPTIM_TRIGSOURCE_5                      ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity\r\n  * @{\r\n  */\r\n#define LPTIM_ACTIVEEDGE_RISING                LPTIM_CFGR_TRIGEN_0\r\n#define LPTIM_ACTIVEEDGE_FALLING               LPTIM_CFGR_TRIGEN_1\r\n#define LPTIM_ACTIVEEDGE_RISING_FALLING        LPTIM_CFGR_TRIGEN\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time\r\n  * @{\r\n  */\r\n#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION  ((uint32_t)0x00000000U)\r\n#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS      LPTIM_CFGR_TRGFLT_0\r\n#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS      LPTIM_CFGR_TRGFLT_1\r\n#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS      LPTIM_CFGR_TRGFLT\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode\r\n  * @{\r\n  */\r\n\r\n#define LPTIM_UPDATE_IMMEDIATE                  ((uint32_t)0x00000000U)\r\n#define LPTIM_UPDATE_ENDOFPERIOD                LPTIM_CFGR_PRELOAD\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LPTIM_Counter_Source LPTIM Counter Source\r\n  * @{\r\n  */\r\n\r\n#define LPTIM_COUNTERSOURCE_INTERNAL            ((uint32_t)0x00000000U)\r\n#define LPTIM_COUNTERSOURCE_EXTERNAL            LPTIM_CFGR_COUNTMODE\r\n/**\r\n  * @}\r\n  */\r\n \r\n/** @defgroup LPTIM_Flag_Definition LPTIM Flag Definition\r\n  * @{\r\n  */\r\n\r\n#define LPTIM_FLAG_DOWN                          LPTIM_ISR_DOWN\r\n#define LPTIM_FLAG_UP                            LPTIM_ISR_UP\r\n#define LPTIM_FLAG_ARROK                         LPTIM_ISR_ARROK\r\n#define LPTIM_FLAG_CMPOK                         LPTIM_ISR_CMPOK\r\n#define LPTIM_FLAG_EXTTRIG                       LPTIM_ISR_EXTTRIG\r\n#define LPTIM_FLAG_ARRM                          LPTIM_ISR_ARRM\r\n#define LPTIM_FLAG_CMPM                          LPTIM_ISR_CMPM\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition\r\n  * @{\r\n  */\r\n\r\n#define LPTIM_IT_DOWN                            LPTIM_IER_DOWNIE\r\n#define LPTIM_IT_UP                              LPTIM_IER_UPIE\r\n#define LPTIM_IT_ARROK                           LPTIM_IER_ARROKIE\r\n#define LPTIM_IT_CMPOK                           LPTIM_IER_CMPOKIE\r\n#define LPTIM_IT_EXTTRIG                         LPTIM_IER_EXTTRIGIE\r\n#define LPTIM_IT_ARRM                            LPTIM_IER_ARRMIE\r\n#define LPTIM_IT_CMPM                            LPTIM_IER_CMPMIE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief Reset LPTIM handle state\r\n  * @param  __HANDLE__ LPTIM handle\r\n  * @retval None\r\n  */\r\n#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)\r\n\r\n/**\r\n  * @brief  Enable/Disable the LPTIM peripheral.\r\n  * @param  __HANDLE__ LPTIM handle\r\n  * @retval None\r\n  */\r\n#define __HAL_LPTIM_ENABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR |=  (LPTIM_CR_ENABLE))\r\n#define __HAL_LPTIM_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR &=  ~(LPTIM_CR_ENABLE))\r\n\r\n/**\r\n  * @brief  Starts the LPTIM peripheral in Continuous or in single mode.\r\n  * @param  __HANDLE__ DMA handle\r\n  * @retval None\r\n  */\r\n#define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  LPTIM_CR_CNTSTRT)\r\n#define __HAL_LPTIM_START_SINGLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  LPTIM_CR_SNGSTRT)\r\n \r\n    \r\n/**\r\n  * @brief  Writes the passed parameter in the Autoreload register.\r\n  * @param  __HANDLE__ LPTIM handle\r\n  * @param  __VALUE__  Autoreload value\r\n  * @retval None\r\n  */\r\n#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__)  ((__HANDLE__)->Instance->ARR =  (__VALUE__))\r\n\r\n/**\r\n  * @brief  Writes the passed parameter in the Compare register.\r\n  * @param  __HANDLE__ LPTIM handle\r\n  * @param  __VALUE__  Compare value\r\n  * @retval None\r\n  */\r\n#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__)     ((__HANDLE__)->Instance->CMP =  (__VALUE__))\r\n\r\n/**\r\n  * @brief  Checks whether the specified LPTIM flag is set or not.\r\n  * @param  __HANDLE__ LPTIM handle\r\n  * @param  __FLAG__   LPTIM flag to check\r\n  *            This parameter can be a value of:\r\n  *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.\r\n  *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.\r\n  *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.\r\n  *            @arg LPTIM_FLAG_CMPOK   : Compare register update OK Flag.\r\n  *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.\r\n  *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.\r\n  *            @arg LPTIM_FLAG_CMPM    : Compare match Flag.\r\n  * @retval The state of the specified flag (SET or RESET).\r\n  */\r\n#define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))\r\n\r\n/**\r\n  * @brief  Clears the specified LPTIM flag.\r\n  * @param  __HANDLE__ LPTIM handle.\r\n  * @param  __FLAG__   LPTIM flag to clear.\r\n  *            This parameter can be a value of:\r\n  *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.\r\n  *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.\r\n  *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.\r\n  *            @arg LPTIM_FLAG_CMPOK   : Compare register update OK Flag.\r\n  *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.\r\n  *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.\r\n  *            @arg LPTIM_FLAG_CMPM    : Compare match Flag.\r\n  * @retval None.\r\n  */\r\n#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->ICR  = (__FLAG__))\r\n\r\n/**\r\n  * @brief  Enable the specified LPTIM interrupt.\r\n  * @param  __HANDLE__     LPTIM handle.\r\n  * @param  __INTERRUPT__  LPTIM interrupt to set.\r\n  *            This parameter can be a value of:\r\n  *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.\r\n  *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.\r\n  *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.\r\n  *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.\r\n  *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.\r\n  *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.\r\n  *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.\r\n  * @retval None.\r\n  */\r\n#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->IER  |= (__INTERRUPT__))\r\n\r\n /**\r\n  * @brief  Disable the specified LPTIM interrupt.\r\n  * @param  __HANDLE__     LPTIM handle.\r\n  * @param  __INTERRUPT__  LPTIM interrupt to set.\r\n  *            This parameter can be a value of:\r\n  *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.\r\n  *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.\r\n  *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.\r\n  *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.\r\n  *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.\r\n  *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.\r\n  *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.\r\n  * @retval None.\r\n  */\r\n#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->IER  &= (~(__INTERRUPT__)))\r\n\r\n    /**\r\n  * @brief  Checks whether the specified LPTIM interrupt is set or not.\r\n  * @param  __HANDLE__     LPTIM handle.\r\n  * @param  __INTERRUPT__  LPTIM interrupt to check.\r\n  *            This parameter can be a value of:\r\n  *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.\r\n  *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.\r\n  *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.\r\n  *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.\r\n  *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.\r\n  *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.\r\n  *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.\r\n  * @retval Interrupt status.\r\n  */\r\n    \r\n#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r\n\r\n/**\r\n  * @brief  Enable interrupt on the LPTIM Wake-up Timer associated Exti line.\r\n  * @retval None\r\n  */\r\n#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT()       (EXTI->IMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)\r\n\r\n/**\r\n  * @brief  Disable interrupt on the LPTIM Wake-up Timer associated Exti line.\r\n  * @retval None\r\n  */\r\n#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT()      (EXTI->IMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))\r\n\r\n/**\r\n  * @brief  Enable event on the LPTIM Wake-up Timer associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT()    (EXTI->EMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)\r\n\r\n/**\r\n  * @brief  Disable event on the LPTIM Wake-up Timer associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT()   (EXTI->EMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))\r\n\r\n/**\r\n  * @brief  Enable falling edge trigger on the LPTIM Wake-up Timer associated Exti line. \r\n  * @retval None.\r\n  */\r\n#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)\r\n\r\n/**\r\n  * @brief  Disable falling edge trigger on the LPTIM Wake-up Timer associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))\r\n\r\n/**\r\n  * @brief  Enable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)\r\n\r\n/**\r\n  * @brief  Disable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))\r\n\r\n/**\r\n  * @brief  Enable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();\\\r\n                                                                     __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();\\\r\n                                                                    }while(0)\r\n\r\n/**\r\n  * @brief  Disable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.\r\n  * This parameter can be:\r\n  * @retval None.\r\n  */\r\n#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\\\r\n                                                                      __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\\\r\n                                                                     }while(0)\r\n\r\n/**\r\n  * @brief Check whether the LPTIM Wake-up Timer associated Exti line interrupt flag is set or not.\r\n  * @retval Line Status.\r\n  */\r\n#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG()              (EXTI->PR & LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)\r\n\r\n/**\r\n  * @brief Clear the LPTIM Wake-up Timer associated Exti line flag.\r\n  * @retval None.\r\n  */\r\n#define __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG()            (EXTI->PR = LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)\r\n\r\n/**\r\n  * @brief Generate a Software interrupt on the LPTIM Wake-up Timer associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT()         (EXTI->SWIER |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)\r\n\r\n/**\r\n  * @}\r\n  */\r\n   \r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions\r\n  * @{\r\n  */\r\n\r\n/* Initialization/de-initialization functions  ********************************/\r\nHAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);\r\nHAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);\r\n\r\n/* MSP functions  *************************************************************/\r\nvoid HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);\r\nvoid HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);\r\n\r\n/* Start/Stop operation functions  *********************************************/\r\n/* ################################# PWM Mode ################################*/\r\n/* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);\r\nHAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim);\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);\r\nHAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim);\r\n\r\n/* ############################# One Pulse Mode ##############################*/\r\n/* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);\r\nHAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim);\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);\r\nHAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim);\r\n\r\n/* ############################## Set once Mode ##############################*/\r\n/* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);\r\nHAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim);\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);\r\nHAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim);\r\n\r\n/* ############################### Encoder Mode ##############################*/\r\n/* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);\r\nHAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim);\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);\r\nHAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim);\r\n\r\n/* ############################# Time out  Mode ##############################*/\r\n/* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim);\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim);\r\n\r\n/* ############################## Counter Mode ###############################*/\r\n/* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);\r\nHAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);\r\nHAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);\r\n\r\n/* Reading operation functions ************************************************/\r\nuint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);\r\nuint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);\r\nuint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);\r\n\r\n/* LPTIM IRQ functions  *******************************************************/\r\nvoid HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);\r\n\r\n/* CallBack functions  ********************************************************/\r\nvoid HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim);\r\nvoid HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim);\r\nvoid HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim);\r\nvoid HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim);\r\nvoid HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim);\r\nvoid HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim);\r\nvoid HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);\r\n\r\n/* Callbacks Register/UnRegister functions  ***********************************/\r\n#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)\r\nHAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback);\r\nHAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID);\r\n#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */\r\n\r\n/* Peripheral State functions  ************************************************/\r\nHAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Private types -------------------------------------------------------------*/\r\n/** @defgroup LPTIM_Private_Types LPTIM Private Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @defgroup LPTIM_Private_Variables LPTIM Private Variables\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup LPTIM_Private_Constants LPTIM Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup LPTIM_Private_Macros LPTIM Private Macros\r\n  * @{\r\n  */\r\n  \r\n#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__)           (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \\\r\n                                                     ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t \r\n#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__)     (((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1  ) || \\\r\n                                                     ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV2  ) || \\\r\n                                                     ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV4  ) || \\\r\n                                                     ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV8  ) || \\\r\n                                                     ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV16 ) || \\\r\n                                                     ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV32 ) || \\\r\n                                                     ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV64 ) || \\\r\n                                                     ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV128))\r\n#define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1)\t\t\t\t\t\t\t\t\t\t\t\t\t \r\n\r\n#define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__)      (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \\\r\n                                                     ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t \r\n#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__)  (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \\\r\n                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS)     || \\\r\n                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS)     || \\\r\n                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))\r\n\r\n#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__)       (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING)  || \\\r\n                                                     ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \\\r\n                                                     ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))\r\n\r\n#define IS_LPTIM_TRG_SOURCE(__TRIG__)               (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \\\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \\\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \\\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \\\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \\\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \\\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t ((__TRIG__) == LPTIM_TRIGSOURCE_5))\r\n\r\n#define IS_LPTIM_EXT_TRG_POLARITY(__POLAR__)        (((__POLAR__) == LPTIM_ACTIVEEDGE_RISING         ) || \\\r\n                                                     ((__POLAR__) == LPTIM_ACTIVEEDGE_FALLING        ) || \\\r\n                                                     ((__POLAR__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))\r\n\r\n#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__)   (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \\\r\n                                                     ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS    ) || \\\r\n                                                     ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS    ) || \\\r\n                                                     ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS    ))\t\t\r\n\r\n#define IS_LPTIM_UPDATE_MODE(__MODE__)              (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \\\r\n                                                     ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))\r\n\r\n#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__)         (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \\\r\n                                                     ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))\r\n\r\n#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__)         ((__AUTORELOAD__) <= 0x0000FFFFU)\r\n\r\n#define IS_LPTIM_COMPARE(__COMPARE__)               ((__COMPARE__) <= 0x0000FFFFU)\r\n  \r\n#define IS_LPTIM_PERIOD(PERIOD)               ((PERIOD) <= 0x0000FFFFU)\r\n\r\n#define IS_LPTIM_PULSE(PULSE)                 ((PULSE) <= 0x0000FFFFU)\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup LPTIM_Private_Functions LPTIM Private Functions\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_LPTIM_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_ltdc.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of LTDC HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_LTDC_H\r\n#define __STM32F7xx_HAL_LTDC_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup LTDC LTDC\r\n  * @brief LTDC HAL module driver\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup LTDC_Exported_Types LTDC Exported Types\r\n  * @{\r\n  */\r\n#define MAX_LAYER  2\r\n\r\n/** \r\n  * @brief  LTDC color structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint8_t Blue;                    /*!< Configures the blue value.\r\n                                        This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */\r\n\r\n  uint8_t Green;                   /*!< Configures the green value.\r\n                                        This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */\r\n\r\n  uint8_t Red;                     /*!< Configures the red value. \r\n                                        This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */\r\n\r\n  uint8_t Reserved;                /*!< Reserved 0xFF */\r\n} LTDC_ColorTypeDef;\r\n\r\n/** \r\n  * @brief  LTDC Init structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t            HSPolarity;                /*!< configures the horizontal synchronization polarity.\r\n                                                      This parameter can be one value of @ref LTDC_HS_POLARITY */\r\n\r\n  uint32_t            VSPolarity;                /*!< configures the vertical synchronization polarity.\r\n                                                      This parameter can be one value of @ref LTDC_VS_POLARITY */\r\n\r\n  uint32_t            DEPolarity;                /*!< configures the data enable polarity. \r\n                                                      This parameter can be one of value of @ref LTDC_DE_POLARITY */\r\n\r\n  uint32_t            PCPolarity;                /*!< configures the pixel clock polarity. \r\n                                                      This parameter can be one of value of @ref LTDC_PC_POLARITY */\r\n\r\n  uint32_t            HorizontalSync;            /*!< configures the number of Horizontal synchronization width.\r\n                                                      This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */\r\n\r\n  uint32_t            VerticalSync;              /*!< configures the number of Vertical synchronization height. \r\n                                                      This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */\r\n\r\n  uint32_t            AccumulatedHBP;            /*!< configures the accumulated horizontal back porch width.\r\n                                                      This parameter must be a number between Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */\r\n\r\n  uint32_t            AccumulatedVBP;            /*!< configures the accumulated vertical back porch height.\r\n                                                      This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */\r\n\r\n  uint32_t            AccumulatedActiveW;        /*!< configures the accumulated active width. \r\n                                                      This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */\r\n\r\n  uint32_t            AccumulatedActiveH;        /*!< configures the accumulated active height.\r\n                                                      This parameter must be a number between Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */\r\n\r\n  uint32_t            TotalWidth;                /*!< configures the total width.\r\n                                                      This parameter must be a number between Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */\r\n\r\n  uint32_t            TotalHeigh;                /*!< configures the total height.\r\n                                                      This parameter must be a number between Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */\r\n\r\n  LTDC_ColorTypeDef   Backcolor;                 /*!< Configures the background color. */\r\n} LTDC_InitTypeDef;\r\n\r\n/** \r\n  * @brief  LTDC Layer structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t WindowX0;                   /*!< Configures the Window Horizontal Start Position.\r\n                                            This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */\r\n\r\n  uint32_t WindowX1;                   /*!< Configures the Window Horizontal Stop Position.\r\n                                            This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */\r\n\r\n  uint32_t WindowY0;                   /*!< Configures the Window vertical Start Position.\r\n                                            This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */\r\n\r\n  uint32_t WindowY1;                   /*!< Configures the Window vertical Stop Position.\r\n                                            This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FF. */\r\n\r\n  uint32_t PixelFormat;                /*!< Specifies the pixel format. \r\n                                            This parameter can be one of value of @ref LTDC_Pixelformat */\r\n\r\n  uint32_t Alpha;                      /*!< Specifies the constant alpha used for blending.\r\n                                            This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */\r\n\r\n  uint32_t Alpha0;                     /*!< Configures the default alpha value.\r\n                                            This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */\r\n\r\n  uint32_t BlendingFactor1;            /*!< Select the blending factor 1. \r\n                                            This parameter can be one of value of @ref LTDC_BlendingFactor1 */\r\n\r\n  uint32_t BlendingFactor2;            /*!< Select the blending factor 2. \r\n                                            This parameter can be one of value of @ref LTDC_BlendingFactor2 */\r\n\r\n  uint32_t FBStartAdress;              /*!< Configures the color frame buffer address */\r\n\r\n  uint32_t ImageWidth;                 /*!< Configures the color frame buffer line length. \r\n                                            This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x1FFF. */\r\n\r\n  uint32_t ImageHeight;                /*!< Specifies the number of line in frame buffer. \r\n                                            This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */\r\n\r\n  LTDC_ColorTypeDef   Backcolor;       /*!< Configures the layer background color. */\r\n} LTDC_LayerCfgTypeDef;\r\n\r\n/** \r\n  * @brief  HAL LTDC State structures definition\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_LTDC_STATE_RESET             = 0x00U,    /*!< LTDC not yet initialized or disabled */\r\n  HAL_LTDC_STATE_READY             = 0x01U,    /*!< LTDC initialized and ready for use   */\r\n  HAL_LTDC_STATE_BUSY              = 0x02U,    /*!< LTDC internal process is ongoing     */\r\n  HAL_LTDC_STATE_TIMEOUT           = 0x03U,    /*!< LTDC Timeout state                   */\r\n  HAL_LTDC_STATE_ERROR             = 0x04U     /*!< LTDC state error                     */\r\n}HAL_LTDC_StateTypeDef;\r\n\r\n/** \r\n  * @brief  LTDC handle Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  LTDC_TypeDef                *Instance;                /*!< LTDC Register base address                */\r\n\r\n  LTDC_InitTypeDef            Init;                     /*!< LTDC parameters                           */\r\n\r\n  LTDC_LayerCfgTypeDef        LayerCfg[MAX_LAYER];      /*!< LTDC Layers parameters                    */\r\n\r\n  HAL_LockTypeDef             Lock;                     /*!< LTDC Lock                                 */\r\n\r\n  __IO HAL_LTDC_StateTypeDef  State;                    /*!< LTDC state                                */\r\n\r\n  __IO uint32_t               ErrorCode;                /*!< LTDC Error code                           */\r\n\r\n} LTDC_HandleTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup LTDC_Exported_Constants LTDC Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup LTDC_Error_Code LTDC Error Code\r\n  * @{\r\n  */\r\n#define HAL_LTDC_ERROR_NONE      ((uint32_t)0x00000000U)    /*!< LTDC No error             */\r\n#define HAL_LTDC_ERROR_TE        ((uint32_t)0x00000001U)    /*!< LTDC Transfer error       */\r\n#define HAL_LTDC_ERROR_FU        ((uint32_t)0x00000002U)    /*!< LTDC FIFO Underrun        */\r\n#define HAL_LTDC_ERROR_TIMEOUT   ((uint32_t)0x00000020U)    /*!< LTDC Timeout error        */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LTDC_HS_POLARITY LTDC HS POLARITY\r\n  * @{\r\n  */\r\n#define LTDC_HSPOLARITY_AL                ((uint32_t)0x00000000U)                /*!< Horizontal Synchronization is active low. */\r\n#define LTDC_HSPOLARITY_AH                LTDC_GCR_HSPOL                        /*!< Horizontal Synchronization is active high. */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LTDC_VS_POLARITY LTDC VS POLARITY\r\n  * @{\r\n  */\r\n#define LTDC_VSPOLARITY_AL                ((uint32_t)0x00000000U)                /*!< Vertical Synchronization is active low. */\r\n#define LTDC_VSPOLARITY_AH                LTDC_GCR_VSPOL                        /*!< Vertical Synchronization is active high. */\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup LTDC_DE_POLARITY LTDC DE POLARITY\r\n  * @{\r\n  */\r\n#define LTDC_DEPOLARITY_AL                ((uint32_t)0x00000000U)                /*!< Data Enable, is active low. */\r\n#define LTDC_DEPOLARITY_AH                LTDC_GCR_DEPOL                        /*!< Data Enable, is active high. */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LTDC_PC_POLARITY LTDC PC POLARITY\r\n  * @{\r\n  */\r\n#define LTDC_PCPOLARITY_IPC               ((uint32_t)0x00000000U)                /*!< input pixel clock. */\r\n#define LTDC_PCPOLARITY_IIPC              LTDC_GCR_PCPOL                        /*!< inverted input pixel clock. */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LTDC_SYNC LTDC SYNC\r\n  * @{\r\n  */\r\n#define LTDC_HORIZONTALSYNC               (LTDC_SSCR_HSW >> 16)                 /*!< Horizontal synchronization width. */ \r\n#define LTDC_VERTICALSYNC                 LTDC_SSCR_VSH                         /*!< Vertical synchronization height. */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LTDC_BACK_COLOR LTDC BACK COLOR\r\n  * @{\r\n  */\r\n#define LTDC_COLOR                   ((uint32_t)0x000000FFU)                     /*!< Color mask */ \r\n/**\r\n  * @}\r\n  */\r\n      \r\n/** @defgroup LTDC_BlendingFactor1 LTDC Blending Factor1\r\n  * @{\r\n  */\r\n#define LTDC_BLENDING_FACTOR1_CA                       ((uint32_t)0x00000400U)   /*!< Blending factor : Cte Alpha */\r\n#define LTDC_BLENDING_FACTOR1_PAxCA                    ((uint32_t)0x00000600U)   /*!< Blending factor : Cte Alpha x Pixel Alpha*/\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LTDC_BlendingFactor2 LTDC Blending Factor2\r\n  * @{\r\n  */\r\n#define LTDC_BLENDING_FACTOR2_CA                       ((uint32_t)0x00000005U)   /*!< Blending factor : Cte Alpha */\r\n#define LTDC_BLENDING_FACTOR2_PAxCA                    ((uint32_t)0x00000007U)   /*!< Blending factor : Cte Alpha x Pixel Alpha*/\r\n/**\r\n  * @}\r\n  */\r\n      \r\n/** @defgroup LTDC_Pixelformat LTDC Pixel format\r\n  * @{\r\n  */\r\n#define LTDC_PIXEL_FORMAT_ARGB8888                  ((uint32_t)0x00000000U)      /*!< ARGB8888 LTDC pixel format */\r\n#define LTDC_PIXEL_FORMAT_RGB888                    ((uint32_t)0x00000001U)      /*!< RGB888 LTDC pixel format   */\r\n#define LTDC_PIXEL_FORMAT_RGB565                    ((uint32_t)0x00000002U)      /*!< RGB565 LTDC pixel format   */\r\n#define LTDC_PIXEL_FORMAT_ARGB1555                  ((uint32_t)0x00000003U)      /*!< ARGB1555 LTDC pixel format */\r\n#define LTDC_PIXEL_FORMAT_ARGB4444                  ((uint32_t)0x00000004U)      /*!< ARGB4444 LTDC pixel format */\r\n#define LTDC_PIXEL_FORMAT_L8                        ((uint32_t)0x00000005U)      /*!< L8 LTDC pixel format       */\r\n#define LTDC_PIXEL_FORMAT_AL44                      ((uint32_t)0x00000006U)      /*!< AL44 LTDC pixel format     */\r\n#define LTDC_PIXEL_FORMAT_AL88                      ((uint32_t)0x00000007U)      /*!< AL88 LTDC pixel format     */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LTDC_Alpha LTDC Alpha\r\n  * @{\r\n  */\r\n#define LTDC_ALPHA               LTDC_LxCACR_CONSTA                             /*!< LTDC Cte Alpha mask */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LTDC_LAYER_Config LTDC LAYER Config\r\n  * @{\r\n  */\r\n#define LTDC_STOPPOSITION                 (LTDC_LxWHPCR_WHSPPOS >> 16)          /*!< LTDC Layer stop position  */\r\n#define LTDC_STARTPOSITION                LTDC_LxWHPCR_WHSTPOS                  /*!< LTDC Layer start position */\r\n\r\n#define LTDC_COLOR_FRAME_BUFFER           LTDC_LxCFBLR_CFBLL                    /*!< LTDC Layer Line length    */ \r\n#define LTDC_LINE_NUMBER                  LTDC_LxCFBLNR_CFBLNBR                 /*!< LTDC Layer Line number    */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LTDC_Interrupts LTDC Interrupts\r\n  * @{\r\n  */\r\n#define LTDC_IT_LI                      LTDC_IER_LIE\r\n#define LTDC_IT_FU                      LTDC_IER_FUIE\r\n#define LTDC_IT_TE                      LTDC_IER_TERRIE\r\n#define LTDC_IT_RR                      LTDC_IER_RRIE\r\n/**\r\n  * @}\r\n  */\r\n      \r\n/** @defgroup LTDC_Flag LTDC Flag\r\n  * @{\r\n  */\r\n#define LTDC_FLAG_LI                     LTDC_ISR_LIF\r\n#define LTDC_FLAG_FU                     LTDC_ISR_FUIF\r\n#define LTDC_FLAG_TE                     LTDC_ISR_TERRIF\r\n#define LTDC_FLAG_RR                     LTDC_ISR_RRIF\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LTDC_Reload_Type LTDC Reload Type\r\n  * @{\r\n  */\r\n#define LTDC_RELOAD_IMMEDIATE            LTDC_SRCR_IMR       /*!< Immediate Reload */\r\n#define LTDC_RELOAD_VERTICAL_BLANKING    LTDC_SRCR_VBR       /*!< Vertical Blanking Reload */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup LTDC_Exported_Macros LTDC Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief Reset LTDC handle state\r\n  * @param  __HANDLE__ specifies the LTDC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET)\r\n\r\n/**\r\n  * @brief  Enable the LTDC.\r\n  * @param  __HANDLE__ LTDC handle\r\n  * @retval None.\r\n  */\r\n#define __HAL_LTDC_ENABLE(__HANDLE__)    ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN)\r\n\r\n/**\r\n  * @brief  Disable the LTDC.\r\n  * @param  __HANDLE__ LTDC handle\r\n  * @retval None.\r\n  */\r\n#define __HAL_LTDC_DISABLE(__HANDLE__)   ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN))\r\n\r\n/**\r\n  * @brief  Enable the LTDC Layer.\r\n  * @param  __HANDLE__ LTDC handle\r\n  * @param  __LAYER__ Specify the layer to be enabled\r\n  *                     This parameter can be 0 or 1\r\n  * @retval None.\r\n  */\r\n#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__)  ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN)\r\n\r\n/**\r\n  * @brief  Disable the LTDC Layer.\r\n  * @param  __HANDLE__ LTDC handle\r\n  * @param  __LAYER__ Specify the layer to be disabled\r\n  *                     This parameter can be 0 or 1\r\n  * @retval None.\r\n  */\r\n#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN)\r\n\r\n/**\r\n  * @brief  Reload  Layer Configuration.\r\n  * @param  __HANDLE__ LTDC handle\r\n  * @retval None.\r\n  */\r\n#define __HAL_LTDC_RELOAD_CONFIG(__HANDLE__)   ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR)\r\n\r\n/* Interrupt & Flag management */\r\n/**\r\n  * @brief  Get the LTDC pending flags.\r\n  * @param  __HANDLE__ LTDC handle\r\n  * @param  __FLAG__ Get the specified flag.\r\n  *          This parameter can be any combination of the following values:\r\n  *            @arg LTDC_FLAG_LI: Line Interrupt flag \r\n  *            @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag\r\n  *            @arg LTDC_FLAG_TE: Transfer Error interrupt flag\r\n  *            @arg LTDC_FLAG_RR: Register Reload Interrupt Flag \r\n  * @retval The state of FLAG (SET or RESET).\r\n  */\r\n#define __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))\r\n\r\n/**\r\n  * @brief  Clears the LTDC pending flags.\r\n  * @param  __HANDLE__ LTDC handle\r\n  * @param  __FLAG__ specifies the flag to clear.\r\n  *          This parameter can be any combination of the following values:\r\n  *            @arg LTDC_FLAG_LI: Line Interrupt flag \r\n  *            @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag\r\n  *            @arg LTDC_FLAG_TE: Transfer Error interrupt flag\r\n  *            @arg LTDC_FLAG_RR: Register Reload Interrupt Flag \r\n  * @retval None\r\n  */\r\n#define __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))\r\n\r\n/**\r\n  * @brief  Enables the specified LTDC interrupts.\r\n  * @param  __HANDLE__ LTDC handle\r\n  * @param __INTERRUPT__ specifies the LTDC interrupt sources to be enabled. \r\n  *          This parameter can be any combination of the following values:\r\n  *            @arg LTDC_IT_LI: Line Interrupt flag \r\n  *            @arg LTDC_IT_FU: FIFO Underrun Interrupt flag\r\n  *            @arg LTDC_IT_TE: Transfer Error interrupt flag\r\n  *            @arg LTDC_IT_RR: Register Reload Interrupt Flag\r\n  * @retval None\r\n  */\r\n#define __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disables the specified LTDC interrupts.\r\n  * @param  __HANDLE__ LTDC handle\r\n  * @param __INTERRUPT__ specifies the LTDC interrupt sources to be disabled. \r\n  *          This parameter can be any combination of the following values:\r\n  *            @arg LTDC_IT_LI: Line Interrupt flag \r\n  *            @arg LTDC_IT_FU: FIFO Underrun Interrupt flag\r\n  *            @arg LTDC_IT_TE: Transfer Error interrupt flag\r\n  *            @arg LTDC_IT_RR: Register Reload Interrupt Flag\r\n  * @retval None\r\n  */\r\n#define __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Checks whether the specified LTDC interrupt has occurred or not.\r\n  * @param  __HANDLE__ LTDC handle\r\n  * @param  __INTERRUPT__ specifies the LTDC interrupt source to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg LTDC_IT_LI: Line Interrupt flag \r\n  *            @arg LTDC_IT_FU: FIFO Underrun Interrupt flag\r\n  *            @arg LTDC_IT_TE: Transfer Error interrupt flag\r\n  *            @arg LTDC_IT_RR: Register Reload Interrupt Flag\r\n  * @retval The state of INTERRUPT (SET or RESET).\r\n  */\r\n#define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->ISR & (__INTERRUPT__))\r\n/**\r\n  * @}\r\n  */\r\n\r\n#if defined (STM32F769xx) || defined (STM32F779xx)  \r\n/* Include LTDC HAL Extension module */\r\n#include \"stm32f7xx_hal_ltdc_ex.h\"\r\n#endif /* STM32F769xx) | STM32F779xx */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup LTDC_Exported_Functions\r\n  * @{\r\n  */\r\n/** @addtogroup LTDC_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n/* Initialization and de-initialization functions *****************************/\r\nHAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc);\r\nHAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc);\r\nvoid HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc);\r\nvoid HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc);\r\nvoid HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc);\r\nvoid HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc);\r\nvoid HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup LTDC_Exported_Functions_Group2\r\n  * @{\r\n  */\r\n/* IO operation functions *****************************************************/\r\nvoid  HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup LTDC_Exported_Functions_Group3\r\n  * @{\r\n  */\r\n/* Peripheral Control functions ***********************************************/\r\nHAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line);\r\nHAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc);\r\nHAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc);\r\nHAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType);\r\nHAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup LTDC_Exported_Functions_Group4\r\n  * @{\r\n  */\r\n/* Peripheral State functions *************************************************/\r\nHAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc);\r\nuint32_t              HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Private types -------------------------------------------------------------*/\r\n/** @defgroup LTDC_Private_Types LTDC Private Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @defgroup LTDC_Private_Variables LTDC Private Variables\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup LTDC_Private_Constants LTDC Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup LTDC_Private_Macros LTDC Private Macros\r\n  * @{\r\n  */\r\n#define LTDC_LAYER(__HANDLE__, __LAYER__)         ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84 + (0x80*(__LAYER__)))))\r\n#define IS_LTDC_LAYER(LAYER)                      ((LAYER) <= MAX_LAYER)\r\n#define IS_LTDC_HSPOL(HSPOL)                      (((HSPOL) == LTDC_HSPOLARITY_AL) || \\\r\n                                                   ((HSPOL) == LTDC_HSPOLARITY_AH))\r\n#define IS_LTDC_VSPOL(VSPOL)                      (((VSPOL) == LTDC_VSPOLARITY_AL) || \\\r\n                                                   ((VSPOL) == LTDC_VSPOLARITY_AH))\r\n#define IS_LTDC_DEPOL(DEPOL)                      (((DEPOL) ==  LTDC_DEPOLARITY_AL) || \\\r\n                                                   ((DEPOL) ==  LTDC_DEPOLARITY_AH))\r\n#define IS_LTDC_PCPOL(PCPOL)                      (((PCPOL) ==  LTDC_PCPOLARITY_IPC) || \\\r\n                                                   ((PCPOL) ==  LTDC_PCPOLARITY_IIPC))\r\n#define IS_LTDC_HSYNC(HSYNC)                      ((HSYNC)  <= LTDC_HORIZONTALSYNC)\r\n#define IS_LTDC_VSYNC(VSYNC)                      ((VSYNC)  <= LTDC_VERTICALSYNC)\r\n#define IS_LTDC_AHBP(AHBP)                        ((AHBP)   <= LTDC_HORIZONTALSYNC)\r\n#define IS_LTDC_AVBP(AVBP)                        ((AVBP)   <= LTDC_VERTICALSYNC)\r\n#define IS_LTDC_AAW(AAW)                          ((AAW)    <= LTDC_HORIZONTALSYNC)\r\n#define IS_LTDC_AAH(AAH)                          ((AAH)    <= LTDC_VERTICALSYNC)\r\n#define IS_LTDC_TOTALW(TOTALW)                    ((TOTALW) <= LTDC_HORIZONTALSYNC)\r\n#define IS_LTDC_TOTALH(TOTALH)                    ((TOTALH) <= LTDC_VERTICALSYNC)\r\n#define IS_LTDC_BLUEVALUE(BBLUE)                  ((BBLUE)  <= LTDC_COLOR)\r\n#define IS_LTDC_GREENVALUE(BGREEN)                ((BGREEN) <= LTDC_COLOR)\r\n#define IS_LTDC_REDVALUE(BRED)                    ((BRED)   <= LTDC_COLOR)\r\n#define IS_LTDC_BLENDING_FACTOR1(BlendingFactor1) (((BlendingFactor1) == LTDC_BLENDING_FACTOR1_CA) || \\\r\n                                                   ((BlendingFactor1) == LTDC_BLENDING_FACTOR1_PAxCA))\r\n#define IS_LTDC_BLENDING_FACTOR2(BlendingFactor2) (((BlendingFactor2) == LTDC_BLENDING_FACTOR2_CA) || \\\r\n                                                   ((BlendingFactor2) == LTDC_BLENDING_FACTOR2_PAxCA))\r\n#define IS_LTDC_PIXEL_FORMAT(Pixelformat)         (((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB8888) || ((Pixelformat) == LTDC_PIXEL_FORMAT_RGB888)   || \\\r\n                                                   ((Pixelformat) == LTDC_PIXEL_FORMAT_RGB565)   || ((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB1555) || \\\r\n                                                   ((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB4444) || ((Pixelformat) == LTDC_PIXEL_FORMAT_L8)       || \\\r\n                                                   ((Pixelformat) == LTDC_PIXEL_FORMAT_AL44)     || ((Pixelformat) == LTDC_PIXEL_FORMAT_AL88))\r\n#define IS_LTDC_ALPHA(ALPHA)                      ((ALPHA) <= LTDC_ALPHA)\r\n#define IS_LTDC_HCONFIGST(HCONFIGST)              ((HCONFIGST) <= LTDC_STARTPOSITION)\r\n#define IS_LTDC_HCONFIGSP(HCONFIGSP)              ((HCONFIGSP) <= LTDC_STOPPOSITION)\r\n#define IS_LTDC_VCONFIGST(VCONFIGST)              ((VCONFIGST) <= LTDC_STARTPOSITION)\r\n#define IS_LTDC_VCONFIGSP(VCONFIGSP)              ((VCONFIGSP) <= LTDC_STOPPOSITION)\r\n#define IS_LTDC_CFBP(CFBP)                        ((CFBP) <= LTDC_COLOR_FRAME_BUFFER)\r\n#define IS_LTDC_CFBLL(CFBLL)                      ((CFBLL) <= LTDC_COLOR_FRAME_BUFFER)\r\n#define IS_LTDC_CFBLNBR(CFBLNBR)                  ((CFBLNBR) <= LTDC_LINE_NUMBER)\r\n#define IS_LTDC_LIPOS(LIPOS)                      ((LIPOS) <= 0x7FF)\r\n#define IS_LTDC_RELAOD(RELOADTYPE)                (((RELOADTYPE) == LTDC_RELOAD_IMMEDIATE) || ((RELOADTYPE) == LTDC_SRCR_VBR))\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup LTDC_Private_Functions LTDC Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_LTDC_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_nand.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_nand.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of NAND HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_NAND_H\r\n#define __STM32F7xx_HAL_NAND_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_ll_fmc.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup NAND\r\n  * @{\r\n  */ \r\n\r\n/* Exported typedef ----------------------------------------------------------*/\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup NAND_Exported_Types NAND Exported Types\r\n  * @{\r\n  */\r\n\r\n/** \r\n  * @brief  HAL NAND State structures definition\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_NAND_STATE_RESET     = 0x00U,  /*!< NAND not yet initialized or disabled */\r\n  HAL_NAND_STATE_READY     = 0x01U,  /*!< NAND initialized and ready for use   */\r\n  HAL_NAND_STATE_BUSY      = 0x02U,  /*!< NAND internal process is ongoing     */\r\n  HAL_NAND_STATE_ERROR     = 0x03U   /*!< NAND error state                     */\r\n}HAL_NAND_StateTypeDef;\r\n   \r\n/** \r\n  * @brief  NAND Memory electronic signature Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  /*<! NAND memory electronic signature maker and device IDs */\r\n\r\n  uint8_t Maker_Id; \r\n\r\n  uint8_t Device_Id;\r\n\r\n  uint8_t Third_Id;\r\n\r\n  uint8_t Fourth_Id;\r\n}NAND_IDTypeDef;\r\n\r\n/** \r\n  * @brief  NAND Memory address Structure definition\r\n  */\r\ntypedef struct \r\n{\r\n  uint16_t Page;   /*!< NAND memory Page address  */\r\n\r\n  uint16_t Plane;   /*!< NAND memory Zone address  */\r\n\r\n  uint16_t Block;  /*!< NAND memory Block address */\r\n\r\n}NAND_AddressTypeDef;\r\n\r\n/** \r\n  * @brief  NAND Memory info Structure definition\r\n  */ \r\ntypedef struct\r\n{\r\n  uint32_t        PageSize;              /*!< NAND memory page (without spare area) size measured in bytes \r\n                                              for 8 bits adressing or words for 16 bits addressing             */\r\n\r\n  uint32_t        SpareAreaSize;         /*!< NAND memory spare area size measured in bytes \r\n                                              for 8 bits adressing or words for 16 bits addressing             */\r\n  \r\n  uint32_t        BlockSize;             /*!< NAND memory block size measured in number of pages               */\r\n\r\n  uint32_t        BlockNbr;              /*!< NAND memory number of total blocks                               */\r\n     \r\n  uint32_t        PlaneNbr;              /*!< NAND memory number of planes                                     */\r\n\r\n  uint32_t        PlaneSize;             /*!< NAND memory zone size measured in number of blocks               */\r\n\r\n  FunctionalState ExtraCommandEnable;    /*!< NAND extra command needed for Page reading mode. This \r\n                                              parameter is mandatory for some NAND parts after the read \r\n                                              command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence. \r\n                                              Example: Toshiba THTH58BYG3S0HBAI6.\r\n                                              This parameter could be ENABLE or DISABLE\r\n                                              Please check the Read Mode sequnece in the NAND device datasheet */\r\n}NAND_DeviceConfigTypeDef; \r\n\r\n/** \r\n  * @brief  NAND handle Structure definition\r\n  */   \r\ntypedef struct\r\n{\r\n  FMC_NAND_TypeDef               *Instance;  /*!< Register base address                                 */\r\n  \r\n  FMC_NAND_InitTypeDef           Init;       /*!< NAND device control configuration parameters          */\r\n\r\n  HAL_LockTypeDef                Lock;       /*!< NAND locking object                                   */\r\n\r\n  __IO HAL_NAND_StateTypeDef     State;      /*!< NAND device access state                              */\r\n\r\n  NAND_DeviceConfigTypeDef       Config;     /*!< NAND phusical characteristic information structure    */\r\n\r\n}NAND_HandleTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup NAND_Exported_Macros NAND Exported Macros\r\n * @{\r\n */ \r\n\r\n/** @brief Reset NAND handle state\r\n  * @param  __HANDLE__ specifies the NAND handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup NAND_Exported_Functions NAND Exported Functions\r\n  * @{\r\n  */\r\n    \r\n/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions \r\n  * @{\r\n  */\r\n\r\n/* Initialization/de-initialization functions  ********************************/\r\nHAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);\r\nHAL_StatusTypeDef  HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);\r\n\r\nHAL_StatusTypeDef  HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);\r\n\r\nHAL_StatusTypeDef  HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);\r\n\r\nvoid               HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);\r\nvoid               HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);\r\nvoid               HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);\r\nvoid               HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions \r\n  * @{\r\n  */\r\n\r\n/* IO operation functions  ****************************************************/\r\n\r\nHAL_StatusTypeDef  HAL_NAND_Reset(NAND_HandleTypeDef *hnand);\r\n\r\nHAL_StatusTypeDef  HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);\r\nHAL_StatusTypeDef  HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);\r\nHAL_StatusTypeDef  HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);\r\nHAL_StatusTypeDef  HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);\r\n\r\nHAL_StatusTypeDef  HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);\r\nHAL_StatusTypeDef  HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);\r\nHAL_StatusTypeDef  HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);\r\nHAL_StatusTypeDef  HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);\r\n\r\nHAL_StatusTypeDef  HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);\r\n\r\nuint32_t           HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions \r\n  * @{\r\n  */\r\n\r\n/* NAND Control functions  ****************************************************/\r\nHAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);\r\nHAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);\r\nHAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);\r\n\r\n/**\r\n  * @}\r\n  */\r\n    \r\n/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions \r\n  * @{\r\n  */\r\n/* NAND State functions *******************************************************/\r\nHAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);\r\nuint32_t              HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup NAND_Private_Constants NAND Private Constants\r\n  * @{\r\n  */\r\n#define NAND_DEVICE                ((uint32_t)0x80000000U) \r\n#define NAND_WRITE_TIMEOUT         ((uint32_t)0x01000000U)\r\n\r\n#define CMD_AREA                   ((uint32_t)(1<<16))  /* A16 = CLE high */\r\n#define ADDR_AREA                  ((uint32_t)(1<<17))  /* A17 = ALE high */\r\n\r\n#define NAND_CMD_AREA_A            ((uint8_t)0x00U)\r\n#define NAND_CMD_AREA_B            ((uint8_t)0x01U)\r\n#define NAND_CMD_AREA_C            ((uint8_t)0x50U)\r\n#define NAND_CMD_AREA_TRUE1        ((uint8_t)0x30U)\r\n\r\n#define NAND_CMD_WRITE0            ((uint8_t)0x80U)\r\n#define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10U)\r\n#define NAND_CMD_ERASE0            ((uint8_t)0x60U)\r\n#define NAND_CMD_ERASE1            ((uint8_t)0xD0U)\r\n#define NAND_CMD_READID            ((uint8_t)0x90U)\r\n#define NAND_CMD_STATUS            ((uint8_t)0x70U)\r\n#define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7AU)\r\n#define NAND_CMD_RESET             ((uint8_t)0xFFU)\r\n\r\n/* NAND memory status */\r\n#define NAND_VALID_ADDRESS         ((uint32_t)0x00000100U)\r\n#define NAND_INVALID_ADDRESS       ((uint32_t)0x00000200U)\r\n#define NAND_TIMEOUT_ERROR         ((uint32_t)0x00000400U)\r\n#define NAND_BUSY                  ((uint32_t)0x00000000U)\r\n#define NAND_ERROR                 ((uint32_t)0x00000001U)\r\n#define NAND_READY                 ((uint32_t)0x00000040U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup NAND_Private_Macros NAND Private Macros\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  NAND memory address computation.\r\n  * @param  __ADDRESS__ NAND memory address.\r\n  * @param  __HANDLE__  NAND handle.\r\n  * @retval NAND Raw address value\r\n  */\r\n#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \\\r\n                         (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))\r\n\r\n#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)\r\n\r\n/**\r\n  * @brief  NAND memory address cycling.\r\n  * @param  __ADDRESS__ NAND memory address.\r\n  * @retval NAND address cycling value.\r\n  */\r\n#define ADDR_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st addressing cycle */\r\n#define ADDR_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd addressing cycle */\r\n#define ADDR_3RD_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 16)      /* 3rd addressing cycle */\r\n#define ADDR_4TH_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 24)      /* 4th addressing cycle */\r\n\r\n/**\r\n  * @brief  NAND memory Columns cycling.\r\n  * @param  __ADDRESS__ NAND memory address.\r\n  * @retval NAND Column address cycling value.\r\n  */\r\n#define COLUMN_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st Column addressing cycle */\r\n#define COLUMN_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd Column addressing cycle */\r\n\r\n/**\r\n  * @}\r\n  */\r\n    \r\n/**\r\n  * @}\r\n  */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_NAND_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_nor.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_nor.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of NOR HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_NOR_H\r\n#define __STM32F7xx_HAL_NOR_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_ll_fmc.h\"\r\n\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup NOR\r\n  * @{\r\n  */ \r\n\r\n/* Exported typedef ----------------------------------------------------------*/\r\n/** @defgroup NOR_Exported_Types NOR Exported Types\r\n  * @{\r\n  */\r\n\r\n/** \r\n  * @brief  HAL SRAM State structures definition  \r\n  */ \r\ntypedef enum\r\n{  \r\n  HAL_NOR_STATE_RESET             = 0x00U,  /*!< NOR not yet initialized or disabled  */\r\n  HAL_NOR_STATE_READY             = 0x01U,  /*!< NOR initialized and ready for use    */\r\n  HAL_NOR_STATE_BUSY              = 0x02U,  /*!< NOR internal processing is ongoing   */\r\n  HAL_NOR_STATE_ERROR             = 0x03U,  /*!< NOR error state                      */\r\n  HAL_NOR_STATE_PROTECTED         = 0x04U   /*!< NOR NORSRAM device write protected   */\r\n}HAL_NOR_StateTypeDef;\r\n\r\n/**\r\n  * @brief  FMC NOR Status typedef\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_NOR_STATUS_SUCCESS  = 0U,\r\n  HAL_NOR_STATUS_ONGOING,\r\n  HAL_NOR_STATUS_ERROR,\r\n  HAL_NOR_STATUS_TIMEOUT\r\n}HAL_NOR_StatusTypeDef;\r\n\r\n/**\r\n  * @brief  FMC NOR ID typedef\r\n  */\r\ntypedef struct\r\n{\r\n  uint16_t Manufacturer_Code;  /*!< Defines the device's manufacturer code used to identify the memory       */\r\n\r\n  uint16_t Device_Code1;\r\n\r\n  uint16_t Device_Code2;\r\n\r\n  uint16_t Device_Code3;       /*!< Defines the device's codes used to identify the memory. \r\n                                    These codes can be accessed by performing read operations with specific \r\n                                    control signals and addresses set.They can also be accessed by issuing \r\n                                    an Auto Select command                                                   */\r\n}NOR_IDTypeDef;\r\n\r\n/**\r\n  * @brief  FMC NOR CFI typedef\r\n  */\r\ntypedef struct\r\n{\r\n  /*!< Defines the information stored in the memory's Common flash interface\r\n       which contains a description of various electrical and timing parameters, \r\n       density information and functions supported by the memory                   */\r\n\r\n  uint16_t CFI_1;\r\n\r\n  uint16_t CFI_2;\r\n\r\n  uint16_t CFI_3;\r\n\r\n  uint16_t CFI_4;\r\n}NOR_CFITypeDef;\r\n\r\n/** \r\n  * @brief  NOR handle Structure definition\r\n  */ \r\ntypedef struct\r\n{\r\n  FMC_NORSRAM_TypeDef           *Instance;    /*!< Register base address                        */\r\n\r\n  FMC_NORSRAM_EXTENDED_TypeDef  *Extended;    /*!< Extended mode register base address          */\r\n\r\n  FMC_NORSRAM_InitTypeDef       Init;         /*!< NOR device control configuration parameters  */\r\n\r\n  HAL_LockTypeDef               Lock;         /*!< NOR locking object                           */\r\n\r\n  __IO HAL_NOR_StateTypeDef     State;        /*!< NOR device access state                      */\r\n\r\n}NOR_HandleTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Exported constants --------------------------------------------------------*/\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup NOR_Exported_Macros NOR Exported Macros\r\n  * @{\r\n  */\r\n/** @brief Reset NOR handle state\r\n  * @param  __HANDLE__ specifies the NOR handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup NOR_Exported_Functions NOR Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions \r\n  * @{\r\n  */\r\n\r\n/* Initialization/de-initialization functions  ********************************/\r\nHAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);\r\nHAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);\r\nvoid HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);\r\nvoid HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);\r\nvoid HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions \r\n  * @{\r\n  */\r\n\r\n/* I/O operation functions  ***************************************************/\r\nHAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);\r\nHAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);\r\nHAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);\r\nHAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);\r\n\r\nHAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);\r\nHAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);\r\n\r\nHAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);\r\nHAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);\r\nHAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions \r\n  * @{\r\n  */\r\n\r\n/* NOR Control functions  *****************************************************/\r\nHAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);\r\nHAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @addtogroup NOR_Exported_Functions_Group4 NOR State functions \r\n  * @{\r\n  */\r\n\r\n/* NOR State functions ********************************************************/\r\nHAL_NOR_StateTypeDef  HAL_NOR_GetState(NOR_HandleTypeDef *hnor);\r\nHAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);\r\n/**\r\n  * @}\r\n  */\r\n    \r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup NOR_Private_Constants NOR Private Constants\r\n  * @{\r\n  */\r\n/* NOR device IDs addresses */\r\n#define MC_ADDRESS               ((uint16_t)0x0000U)\r\n#define DEVICE_CODE1_ADDR        ((uint16_t)0x0001U)\r\n#define DEVICE_CODE2_ADDR        ((uint16_t)0x000EU)\r\n#define DEVICE_CODE3_ADDR        ((uint16_t)0x000FU)\r\n\r\n/* NOR CFI IDs addresses */\r\n#define CFI1_ADDRESS             ((uint16_t)0x61U)\r\n#define CFI2_ADDRESS             ((uint16_t)0x62U)\r\n#define CFI3_ADDRESS             ((uint16_t)0x63U)\r\n#define CFI4_ADDRESS             ((uint16_t)0x64U)\r\n\r\n/* NOR operation wait timeout */\r\n#define NOR_TMEOUT               ((uint16_t)0xFFFFU)\r\n   \r\n/* NOR memory data width */\r\n#define NOR_MEMORY_8B            ((uint8_t)0x0U)\r\n#define NOR_MEMORY_16B           ((uint8_t)0x1U)\r\n\r\n/* NOR memory device read/write start address */\r\n#define NOR_MEMORY_ADRESS1       ((uint32_t)0x60000000U)\r\n#define NOR_MEMORY_ADRESS2       ((uint32_t)0x64000000U)\r\n#define NOR_MEMORY_ADRESS3       ((uint32_t)0x68000000U)\r\n#define NOR_MEMORY_ADRESS4       ((uint32_t)0x6C000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup NOR_Private_Macros NOR Private Macros\r\n  * @{\r\n  */\r\n/**\r\n  * @brief  NOR memory address shifting.\r\n  * @param  __NOR_ADDRESS NOR base address \r\n  * @param  __NOR_MEMORY_WIDTH_ NOR memory width\r\n  * @param  __ADDRESS__ NOR memory address \r\n  * @retval NOR shifted address value\r\n  */\r\n#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)       \\\r\n            ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)?              \\\r\n              ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))):              \\\r\n              ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))\r\n \r\n/**\r\n  * @brief  NOR memory write data to specified address.\r\n  * @param  __ADDRESS__ NOR memory address \r\n  * @param  __DATA__ Data to write\r\n  * @retval None\r\n  */\r\n#define NOR_WRITE(__ADDRESS__, __DATA__)   do{                                                             \\\r\n                                                 (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \\\r\n                                                 __DSB();                                                    \\\r\n                                               } while(0)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_NOR_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_pcd.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of PCD HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_PCD_H\r\n#define __STM32F7xx_HAL_PCD_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_ll_usb.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup PCD\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup PCD_Exported_Types PCD Exported Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  PCD State structure definition\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_PCD_STATE_RESET   = 0x00,\r\n  HAL_PCD_STATE_READY   = 0x01,\r\n  HAL_PCD_STATE_ERROR   = 0x02,\r\n  HAL_PCD_STATE_BUSY    = 0x03,\r\n  HAL_PCD_STATE_TIMEOUT = 0x04\r\n} PCD_StateTypeDef;\r\n\r\n/* Device LPM suspend state */\r\ntypedef enum\r\n{\r\n  LPM_L0 = 0x00, /* on */\r\n  LPM_L1 = 0x01, /* LPM L1 sleep */\r\n  LPM_L2 = 0x02, /* suspend */\r\n  LPM_L3 = 0x03, /* off */\r\n}PCD_LPM_StateTypeDef;\r\n\r\n\r\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\r\ntypedef USB_OTG_GlobalTypeDef  PCD_TypeDef;\r\ntypedef USB_OTG_CfgTypeDef     PCD_InitTypeDef;\r\ntypedef USB_OTG_EPTypeDef      PCD_EPTypeDef;\r\n#endif /* USB_OTG_FS || USB_OTG_HS */\r\n\r\n\r\n/**\r\n  * @brief  PCD Handle Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  PCD_TypeDef             *Instance;   /*!< Register base address              */\r\n  PCD_InitTypeDef         Init;        /*!< PCD required parameters            */\r\n  __IO uint8_t            USB_Address; /*!< USB Address                        */\r\n  PCD_EPTypeDef           IN_ep[16];   /*!< IN endpoint parameters             */\r\n  PCD_EPTypeDef           OUT_ep[16];  /*!< OUT endpoint parameters            */\r\n  HAL_LockTypeDef         Lock;        /*!< PCD peripheral status              */\r\n  __IO PCD_StateTypeDef   State;       /*!< PCD communication state            */\r\n  uint32_t                Setup[12];   /*!< Setup packet buffer                */\r\n  PCD_LPM_StateTypeDef    LPM_State;   /*!< LPM State                          */\r\n  uint32_t                BESL;\r\n\r\n  uint32_t lpm_active;                 /*!< Enable or disable the Link Power Management .\r\n                                       This parameter can be set to ENABLE or DISABLE                      */\r\n  void                    *pData;      /*!< Pointer to upper stack Handler */\r\n} PCD_HandleTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Include PCD HAL Extended module */\r\n#include \"stm32f7xx_hal_pcd_ex.h\"\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup PCD_Exported_Constants PCD Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup PCD_Speed PCD Speed\r\n  * @{\r\n  */\r\n#if defined (USB_OTG_HS)\r\n#define PCD_SPEED_HIGH               0U\r\n#define PCD_SPEED_HIGH_IN_FULL       1U\r\n#endif\r\n#define PCD_SPEED_FULL               2U\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup PCD_PHY_Module PCD PHY Module\r\n  * @{\r\n  */\r\n#define PCD_PHY_ULPI                 1U\r\n#define PCD_PHY_EMBEDDED             2U\r\n#define PCD_PHY_UTMI                 3U\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup PCD_Turnaround_Timeout Turnaround Timeout Value\r\n  * @{\r\n  */\r\n#ifndef USBD_HS_TRDT_VALUE\r\n #define USBD_HS_TRDT_VALUE           9U\r\n#endif /* USBD_HS_TRDT_VALUE */\r\n#ifndef USBD_FS_TRDT_VALUE\r\n #define USBD_FS_TRDT_VALUE           5U\r\n#endif /* USBD_HS_TRDT_VALUE */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macros -----------------------------------------------------------*/\r\n/** @defgroup PCD_Exported_Macros PCD Exported Macros\r\n *  @brief macros to handle interrupts and specific clock configurations\r\n * @{\r\n */\r\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\r\n#define __HAL_PCD_ENABLE(__HANDLE__)                       (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)\r\n#define __HAL_PCD_DISABLE(__HANDLE__)                      (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)\r\n\r\n#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))\r\n#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) &=  (__INTERRUPT__))\r\n#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)\r\n\r\n\r\n#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)             *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \\\r\n                                                          ~(USB_OTG_PCGCCTL_STOPCLK)\r\n\r\n#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__)               *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK\r\n\r\n#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__)            ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)\r\n\r\n#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT()    EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE)\r\n#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT()   EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)\r\n#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG()     EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE)\r\n#define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG()   EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE)\r\n\r\n#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE()                 \\\r\n                        do {                                        \\\r\n                             EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE); \\\r\n                             EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;    \\\r\n                           } while(0U)\r\n#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT()    EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE\r\n#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT()   EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)\r\n#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG()     EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)\r\n#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG()   EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE\r\n\r\n#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE()                 \\\r\n                        do {                                        \\\r\n                             EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \\\r\n                             EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;    \\\r\n                           } while(0U)\r\n#endif /* USB_OTG_FS || USB_OTG_HS */\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup PCD_Exported_Functions PCD Exported Functions\r\n  * @{\r\n  */\r\n\r\n/* Initialization/de-initialization functions  ********************************/\r\n/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);\r\nHAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);\r\nvoid HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);\r\nvoid HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* I/O operation functions  ***************************************************/\r\n/* Non-Blocking mode: Interrupt */\r\n/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);\r\nHAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);\r\nvoid HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);\r\n\r\nvoid HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);\r\nvoid HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);\r\nvoid HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);\r\nvoid HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);\r\nvoid HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);\r\nvoid HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);\r\nvoid HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);\r\nvoid HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);\r\nvoid HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);\r\nvoid HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);\r\nvoid HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Peripheral Control functions  **********************************************/\r\n/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);\r\nHAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);\r\nHAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);\r\nHAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);\r\nHAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);\r\nHAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);\r\nHAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);\r\nuint16_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);\r\nHAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);\r\nHAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);\r\nHAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);\r\nHAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);\r\nHAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Peripheral State functions  ************************************************/\r\n/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions\r\n  * @{\r\n  */\r\nPCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup PCD_Private_Constants PCD Private Constants\r\n  * @{\r\n  */\r\n/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt\r\n  * @{\r\n  */\r\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\r\n#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE                            0x08U\r\n#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE                           0x0CU\r\n#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE                    0x10U\r\n\r\n#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE                            0x08U\r\n#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE                           0x0CU\r\n#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE                    0x10U\r\n\r\n#ifndef LL_EXTI_LINE_18\r\n#define LL_EXTI_LINE_18                                               0x00040000U\r\n#endif\r\n\r\n#ifndef LL_EXTI_LINE_20\r\n#define LL_EXTI_LINE_20                                               0x00100000U\r\n#endif\r\n\r\n#define USB_OTG_FS_WAKEUP_EXTI_LINE                                   LL_EXTI_LINE_18  /*!< External interrupt line 17 Connected to the USB EXTI Line */\r\n#define USB_OTG_HS_WAKEUP_EXTI_LINE                                   LL_EXTI_LINE_20  /*!< External interrupt line 20 Connected to the USB HS EXTI Line */\r\n#endif /* USB_OTG_FS || USB_OTG_HS */\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup PCD_Private_Macros PCD Private Macros\r\n * @{\r\n */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_PCD_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_pcd_ex.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of PCD HAL Extension module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_PCD_EX_H\r\n#define __STM32F7xx_HAL_PCD_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup PCDEx\r\n  * @{\r\n  */\r\n/* Exported types ------------------------------------------------------------*/\r\ntypedef enum\r\n{\r\n  PCD_LPM_L0_ACTIVE = 0x00, /* on */\r\n  PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */\r\n}PCD_LPM_MsgTypeDef;\r\n\r\ntypedef enum\r\n{\r\n  PCD_BCD_ERROR                     = 0xFF,\r\n  PCD_BCD_CONTACT_DETECTION         = 0xFE,\r\n  PCD_BCD_STD_DOWNSTREAM_PORT       = 0xFD,\r\n  PCD_BCD_CHARGING_DOWNSTREAM_PORT  = 0xFC,\r\n  PCD_BCD_DEDICATED_CHARGING_PORT   = 0xFB,\r\n  PCD_BCD_DISCOVERY_COMPLETED       = 0x00,\r\n\r\n}PCD_BCD_MsgTypeDef;\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/* Exported macros -----------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions\r\n  * @{\r\n  */\r\n/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions\r\n  * @{\r\n  */\r\n\r\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\r\nHAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);\r\nHAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);\r\n#endif /* USB_OTG_FS || USB_OTG_HS */\r\n\r\nHAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);\r\nHAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);\r\nvoid HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);\r\nvoid HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n\r\n#endif /* __STM32F7xx_HAL_PCD_EX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_pwr.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of PWR HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_PWR_H\r\n#define __STM32F7xx_HAL_PWR_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup PWR\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n\r\n/** @defgroup PWR_Exported_Types PWR Exported Types\r\n  * @{\r\n  */\r\n   \r\n/**\r\n  * @brief  PWR PVD configuration structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t PVDLevel;   /*!< PVDLevel: Specifies the PVD detection level.\r\n                            This parameter can be a value of @ref PWR_PVD_detection_level */\r\n\r\n  uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.\r\n                           This parameter can be a value of @ref PWR_PVD_Mode */\r\n}PWR_PVDTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup PWR_Exported_Constants PWR Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup PWR_PVD_detection_level PWR PVD detection level\r\n  * @{\r\n  */ \r\n#define PWR_PVDLEVEL_0                  PWR_CR1_PLS_LEV0\r\n#define PWR_PVDLEVEL_1                  PWR_CR1_PLS_LEV1\r\n#define PWR_PVDLEVEL_2                  PWR_CR1_PLS_LEV2\r\n#define PWR_PVDLEVEL_3                  PWR_CR1_PLS_LEV3\r\n#define PWR_PVDLEVEL_4                  PWR_CR1_PLS_LEV4\r\n#define PWR_PVDLEVEL_5                  PWR_CR1_PLS_LEV5\r\n#define PWR_PVDLEVEL_6                  PWR_CR1_PLS_LEV6\r\n#define PWR_PVDLEVEL_7                  PWR_CR1_PLS_LEV7/* External input analog voltage \r\n                                                          (Compare internally to VREFINT) */\r\n\r\n/**\r\n  * @}\r\n  */   \r\n \r\n/** @defgroup PWR_PVD_Mode PWR PVD Mode\r\n  * @{\r\n  */\r\n#define PWR_PVD_MODE_NORMAL                 ((uint32_t)0x00000000U)   /*!< basic mode is used */\r\n#define PWR_PVD_MODE_IT_RISING              ((uint32_t)0x00010001U)   /*!< External Interrupt Mode with Rising edge trigger detection */\r\n#define PWR_PVD_MODE_IT_FALLING             ((uint32_t)0x00010002U)   /*!< External Interrupt Mode with Falling edge trigger detection */\r\n#define PWR_PVD_MODE_IT_RISING_FALLING      ((uint32_t)0x00010003U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */\r\n#define PWR_PVD_MODE_EVENT_RISING           ((uint32_t)0x00020001U)   /*!< Event Mode with Rising edge trigger detection */\r\n#define PWR_PVD_MODE_EVENT_FALLING          ((uint32_t)0x00020002U)   /*!< Event Mode with Falling edge trigger detection */\r\n#define PWR_PVD_MODE_EVENT_RISING_FALLING   ((uint32_t)0x00020003U)   /*!< Event Mode with Rising/Falling edge trigger detection */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode\r\n  * @{\r\n  */\r\n#define PWR_MAINREGULATOR_ON                        ((uint32_t)0x00000000U)\r\n#define PWR_LOWPOWERREGULATOR_ON                    PWR_CR1_LPDS\r\n/**\r\n  * @}\r\n  */\r\n    \r\n/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry\r\n  * @{\r\n  */\r\n#define PWR_SLEEPENTRY_WFI              ((uint8_t)0x01U)\r\n#define PWR_SLEEPENTRY_WFE              ((uint8_t)0x02U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry\r\n  * @{\r\n  */\r\n#define PWR_STOPENTRY_WFI               ((uint8_t)0x01U)\r\n#define PWR_STOPENTRY_WFE               ((uint8_t)0x02U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale\r\n  * @{\r\n  */\r\n#define PWR_REGULATOR_VOLTAGE_SCALE1         PWR_CR1_VOS\r\n#define PWR_REGULATOR_VOLTAGE_SCALE2         PWR_CR1_VOS_1\r\n#define PWR_REGULATOR_VOLTAGE_SCALE3         PWR_CR1_VOS_0\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup PWR_Flag PWR Flag\r\n  * @{\r\n  */\r\n#define PWR_FLAG_WU                     PWR_CSR1_WUIF\r\n#define PWR_FLAG_SB                     PWR_CSR1_SBF\r\n#define PWR_FLAG_PVDO                   PWR_CSR1_PVDO\r\n#define PWR_FLAG_BRR                    PWR_CSR1_BRR\r\n#define PWR_FLAG_VOSRDY                 PWR_CSR1_VOSRDY\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup PWR_Exported_Macro PWR Exported Macro\r\n  * @{\r\n  */\r\n\r\n/** @brief  macros configure the main internal regulator output voltage.\r\n  * @param  __REGULATOR__ specifies the regulator output voltage to achieve\r\n  *         a tradeoff between performance and power consumption when the device does\r\n  *         not operate at the maximum frequency (refer to the datasheets for more details).\r\n  *          This parameter can be one of the following values:\r\n  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode\r\n  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode\r\n  *            @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode\r\n  * @retval None\r\n  */\r\n#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do {                                                     \\\r\n                                                            __IO uint32_t tmpreg;                               \\\r\n                                                            MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \\\r\n                                                            /* Delay after an RCC peripheral clock enabling */  \\\r\n                                                            tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS);           \\\r\n                                                            UNUSED(tmpreg);                                     \\\r\n\t\t\t\t                                                \t} while(0)\r\n\r\n/** @brief  Check PWR flag is set or not.\r\n  * @param  __FLAG__ specifies the flag to check.\r\n  *           This parameter can be one of the following values:\r\n  *            @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event \r\n  *                  was received on the internal wakeup line in standby mode (RTC alarm (Alarm A or Alarm B),\r\n  *                  RTC Tamper event, RTC TimeStamp event or RTC Wakeup)).\r\n  *            @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was\r\n  *                  resumed from StandBy mode.    \r\n  *            @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled \r\n  *                  by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode \r\n  *                  For this reason, this bit is equal to 0 after Standby or reset\r\n  *                  until the PVDE bit is set.\r\n  *            @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset \r\n  *                  when the device wakes up from Standby mode or by a system reset \r\n  *                  or power reset.  \r\n  *            @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage \r\n  *                 scaling output selection is ready.\r\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__))\r\n\r\n/** @brief  Clear the PWR's pending flags.\r\n  * @param  __FLAG__ specifies the flag to clear.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg PWR_FLAG_SB: StandBy flag\r\n  */\r\n#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR1 |=  (__FLAG__) << 2)\r\n\r\n/**\r\n  * @brief Enable the PVD Exti Line 16.\r\n  * @retval None.\r\n  */\r\n#define __HAL_PWR_PVD_EXTI_ENABLE_IT()   (EXTI->IMR |= (PWR_EXTI_LINE_PVD))\r\n\r\n/**\r\n  * @brief Disable the PVD EXTI Line 16.\r\n  * @retval None.\r\n  */\r\n#define __HAL_PWR_PVD_EXTI_DISABLE_IT()  (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))\r\n\r\n/**\r\n  * @brief Enable event on PVD Exti Line 16.\r\n  * @retval None.\r\n  */\r\n#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT()   (EXTI->EMR |= (PWR_EXTI_LINE_PVD))\r\n\r\n/**\r\n  * @brief Disable event on PVD Exti Line 16.\r\n  * @retval None.\r\n  */\r\n#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT()  (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))\r\n\r\n/**\r\n  * @brief Enable the PVD Extended Interrupt Rising Trigger.\r\n  * @retval None.\r\n  */\r\n#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)\r\n\r\n/**\r\n  * @brief Disable the PVD Extended Interrupt Rising Trigger.\r\n  * @retval None.\r\n  */\r\n#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)\r\n\r\n/**\r\n  * @brief Enable the PVD Extended Interrupt Falling Trigger.\r\n  * @retval None.\r\n  */\r\n#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)\r\n\r\n\r\n/**\r\n  * @brief Disable the PVD Extended Interrupt Falling Trigger.\r\n  * @retval None.\r\n  */\r\n#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)\r\n\r\n\r\n/**\r\n  * @brief  PVD EXTI line configuration: set rising & falling edge trigger.\r\n  * @retval None.\r\n  */\r\n#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()   __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\r\n\r\n/**\r\n  * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.\r\n  * @retval None.\r\n  */\r\n#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\r\n\r\n/**\r\n  * @brief checks whether the specified PVD Exti interrupt flag is set or not.\r\n  * @retval EXTI PVD Line Status.\r\n  */\r\n#define __HAL_PWR_PVD_EXTI_GET_FLAG()  (EXTI->PR & (PWR_EXTI_LINE_PVD))\r\n\r\n/**\r\n  * @brief Clear the PVD Exti flag.\r\n  * @retval None.\r\n  */\r\n#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG()  (EXTI->PR = (PWR_EXTI_LINE_PVD))\r\n\r\n/**\r\n  * @brief  Generates a Software interrupt on PVD EXTI line.\r\n  * @retval None\r\n  */\r\n#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Include PWR HAL Extension module */\r\n#include \"stm32f7xx_hal_pwr_ex.h\"\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup PWR_Exported_Functions PWR Exported Functions\r\n  * @{\r\n  */\r\n  \r\n/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions \r\n  * @{\r\n  */\r\n/* Initialization and de-initialization functions *****************************/\r\nvoid HAL_PWR_DeInit(void);\r\nvoid HAL_PWR_EnableBkUpAccess(void);\r\nvoid HAL_PWR_DisableBkUpAccess(void);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions \r\n  * @{\r\n  */\r\n/* Peripheral Control functions  **********************************************/\r\n/* PVD configuration */\r\nvoid HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);\r\nvoid HAL_PWR_EnablePVD(void);\r\nvoid HAL_PWR_DisablePVD(void);\r\n\r\n/* WakeUp pins configuration */\r\nvoid HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);\r\nvoid HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);\r\n\r\n/* Low Power modes entry */\r\nvoid HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);\r\nvoid HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);\r\nvoid HAL_PWR_EnterSTANDBYMode(void);\r\n\r\n/* Power PVD IRQ Handler */\r\nvoid HAL_PWR_PVD_IRQHandler(void);\r\nvoid HAL_PWR_PVDCallback(void);\r\n\r\n/* Cortex System Control functions  *******************************************/\r\nvoid HAL_PWR_EnableSleepOnExit(void);\r\nvoid HAL_PWR_DisableSleepOnExit(void);\r\nvoid HAL_PWR_EnableSEVOnPend(void);\r\nvoid HAL_PWR_DisableSEVOnPend(void);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup PWR_Private_Constants PWR Private Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line\r\n  * @{\r\n  */\r\n#define PWR_EXTI_LINE_PVD  ((uint32_t)EXTI_IMR_IM16)  /*!< External interrupt line 16 Connected to the PVD EXTI Line */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup PWR_Private_Macros PWR Private Macros\r\n  * @{\r\n  */\r\n\r\n/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters\r\n  * @{\r\n  */\r\n#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \\\r\n                                 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \\\r\n                                 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \\\r\n                                 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))\r\n#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \\\r\n                              ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \\\r\n                              ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \\\r\n                              ((MODE) == PWR_PVD_MODE_NORMAL))\r\n#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \\\r\n                                     ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))\r\n#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))\r\n#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))\r\n#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \\\r\n                                           ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \\\r\n                                           ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n\r\n#endif /* __STM32F7xx_HAL_PWR_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_pwr_ex.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of PWR HAL Extension module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_PWR_EX_H\r\n#define __STM32F7xx_HAL_PWR_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup PWREx\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/ \r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup PWREx_Exported_Constants PWREx Exported Constants\r\n  * @{\r\n  */\r\n/** @defgroup PWREx_WakeUp_Pins PWREx Wake Up Pins\r\n  * @{\r\n  */\r\n#define PWR_WAKEUP_PIN1                PWR_CSR2_EWUP1\r\n#define PWR_WAKEUP_PIN2                PWR_CSR2_EWUP2\r\n#define PWR_WAKEUP_PIN3                PWR_CSR2_EWUP3\r\n#define PWR_WAKEUP_PIN4                PWR_CSR2_EWUP4\r\n#define PWR_WAKEUP_PIN5                PWR_CSR2_EWUP5\r\n#define PWR_WAKEUP_PIN6                PWR_CSR2_EWUP6\r\n#define PWR_WAKEUP_PIN1_HIGH           PWR_CSR2_EWUP1\r\n#define PWR_WAKEUP_PIN2_HIGH           PWR_CSR2_EWUP2\r\n#define PWR_WAKEUP_PIN3_HIGH           PWR_CSR2_EWUP3\r\n#define PWR_WAKEUP_PIN4_HIGH           PWR_CSR2_EWUP4\r\n#define PWR_WAKEUP_PIN5_HIGH           PWR_CSR2_EWUP5\r\n#define PWR_WAKEUP_PIN6_HIGH           PWR_CSR2_EWUP6\r\n#define PWR_WAKEUP_PIN1_LOW            (uint32_t)((PWR_CR2_WUPP1<<6) | PWR_CSR2_EWUP1)\r\n#define PWR_WAKEUP_PIN2_LOW            (uint32_t)((PWR_CR2_WUPP2<<6) | PWR_CSR2_EWUP2)\r\n#define PWR_WAKEUP_PIN3_LOW            (uint32_t)((PWR_CR2_WUPP3<<6) | PWR_CSR2_EWUP3)\r\n#define PWR_WAKEUP_PIN4_LOW            (uint32_t)((PWR_CR2_WUPP4<<6) | PWR_CSR2_EWUP4)\r\n#define PWR_WAKEUP_PIN5_LOW            (uint32_t)((PWR_CR2_WUPP5<<6) | PWR_CSR2_EWUP5)\r\n#define PWR_WAKEUP_PIN6_LOW            (uint32_t)((PWR_CR2_WUPP6<<6) | PWR_CSR2_EWUP6)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\t\r\n/** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode\r\n  * @{\r\n  */\r\n#define PWR_MAINREGULATOR_UNDERDRIVE_ON                       PWR_CR1_MRUDS\r\n#define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON                   ((uint32_t)(PWR_CR1_LPDS | PWR_CR1_LPUDS))\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag\r\n  * @{\r\n  */\r\n#define PWR_FLAG_ODRDY                  PWR_CSR1_ODRDY\r\n#define PWR_FLAG_ODSWRDY                PWR_CSR1_ODSWRDY\r\n#define PWR_FLAG_UDRDY                  PWR_CSR1_UDRDY\r\n/**\r\n  * @}\r\n  */\r\n\t\r\n/** @defgroup PWREx_Wakeup_Pins_Flag PWREx Wake Up Pin Flags\r\n  * @{\r\n  */\r\n#define PWR_WAKEUP_PIN_FLAG1            PWR_CSR2_WUPF1\r\n#define PWR_WAKEUP_PIN_FLAG2            PWR_CSR2_WUPF2\r\n#define PWR_WAKEUP_PIN_FLAG3            PWR_CSR2_WUPF3\r\n#define PWR_WAKEUP_PIN_FLAG4            PWR_CSR2_WUPF4\r\n#define PWR_WAKEUP_PIN_FLAG5            PWR_CSR2_WUPF5\r\n#define PWR_WAKEUP_PIN_FLAG6            PWR_CSR2_WUPF6\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup PWREx_Exported_Macro PWREx Exported Macro\r\n  *  @{\r\n  */\r\n/** @brief Macros to enable or disable the Over drive mode.\r\n  */\r\n#define __HAL_PWR_OVERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODEN)\r\n#define __HAL_PWR_OVERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODEN))\r\n\r\n/** @brief Macros to enable or disable the Over drive switching.\r\n  */\r\n#define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODSWEN)\r\n#define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODSWEN))\r\n\r\n/** @brief Macros to enable or disable the Under drive mode.\r\n  * @note  This mode is enabled only with STOP low power mode.\r\n  *        In this mode, the 1.2V domain is preserved in reduced leakage mode. This \r\n  *        mode is only available when the main regulator or the low power regulator \r\n  *        is in low voltage mode.      \r\n  * @note  If the Under-drive mode was enabled, it is automatically disabled after \r\n  *        exiting Stop mode. \r\n  *        When the voltage regulator operates in Under-drive mode, an additional  \r\n  *        startup delay is induced when waking up from Stop mode.\r\n  */\r\n#define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_UDEN)\r\n#define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_UDEN))\r\n\r\n/** @brief  Check PWR flag is set or not.\r\n  * @param  __FLAG__ specifies the flag to check.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode\r\n  *                                 is ready \r\n  *            @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode\r\n  *                                   switching is ready  \r\n  *            @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode\r\n  *                                 is enabled in Stop mode\r\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__))\r\n\r\n/** @brief Clear the Under-Drive Ready flag.\r\n  */\r\n#define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR1 |= PWR_FLAG_UDRDY)\r\n\r\n/** @brief  Check Wake Up flag is set or not.\r\n  * @param  __WUFLAG__ specifies the Wake Up flag to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0\r\n  *            @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2\r\n  *            @arg PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag for PC1\r\n  *            @arg PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag for PC13\r\n  *            @arg PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag for PI8\r\n  *            @arg PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag for PI11          \r\n  */\r\n#define __HAL_PWR_GET_WAKEUP_FLAG(__WUFLAG__) (PWR->CSR2 & (__WUFLAG__))\r\n\r\n/** @brief  Clear the WakeUp pins flags.\r\n  * @param  __WUFLAG__ specifies the Wake Up pin flag to clear.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0\r\n  *            @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2\r\n  *            @arg PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag for PC1\r\n  *            @arg PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag for PC13\r\n  *            @arg PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag for PI8\r\n  *            @arg PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag for PI11          \r\n  */\r\n#define __HAL_PWR_CLEAR_WAKEUP_FLAG(__WUFLAG__) (PWR->CR2 |=  (__WUFLAG__))\r\n/**\r\n  * @}\r\n  */\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions\r\n  *  @{\r\n  */\r\n \r\n/** @addtogroup PWREx_Exported_Functions_Group1\r\n  * @{\r\n  */\r\nuint32_t HAL_PWREx_GetVoltageRange(void);\r\nHAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);\r\n\r\nvoid HAL_PWREx_EnableFlashPowerDown(void);\r\nvoid HAL_PWREx_DisableFlashPowerDown(void); \r\nHAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);\r\nHAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void); \r\n\r\nvoid HAL_PWREx_EnableMainRegulatorLowVoltage(void);\r\nvoid HAL_PWREx_DisableMainRegulatorLowVoltage(void);\r\nvoid HAL_PWREx_EnableLowRegulatorLowVoltage(void);\r\nvoid HAL_PWREx_DisableLowRegulatorLowVoltage(void);\r\n\r\nHAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void);\r\nHAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void);\r\nHAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup PWREx_Private_Macros PWREx Private Macros\r\n  * @{\r\n  */\r\n\r\n/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters\r\n  * @{\r\n  */\r\n#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \\\r\n                                                ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON))\r\n#define IS_PWR_WAKEUP_PIN(__PIN__)         (((__PIN__) == PWR_WAKEUP_PIN1)       || \\\r\n                                            ((__PIN__) == PWR_WAKEUP_PIN2)       || \\\r\n                                            ((__PIN__) == PWR_WAKEUP_PIN3)       || \\\r\n                                            ((__PIN__) == PWR_WAKEUP_PIN4)       || \\\r\n                                            ((__PIN__) == PWR_WAKEUP_PIN5)       || \\\r\n                                            ((__PIN__) == PWR_WAKEUP_PIN6)  \t\t || \\\r\n                                            ((__PIN__) == PWR_WAKEUP_PIN1_HIGH)  || \\\r\n                                            ((__PIN__) == PWR_WAKEUP_PIN2_HIGH)  || \\\r\n                                            ((__PIN__) == PWR_WAKEUP_PIN3_HIGH)  || \\\r\n                                            ((__PIN__) == PWR_WAKEUP_PIN4_HIGH)  || \\\r\n                                            ((__PIN__) == PWR_WAKEUP_PIN5_HIGH)  || \\\r\n                                            ((__PIN__) == PWR_WAKEUP_PIN6_HIGH)  || \\\r\n                                            ((__PIN__) == PWR_WAKEUP_PIN1_LOW)   || \\\r\n                                            ((__PIN__) == PWR_WAKEUP_PIN2_LOW)   || \\\r\n                                            ((__PIN__) == PWR_WAKEUP_PIN3_LOW)   || \\\r\n                                            ((__PIN__) == PWR_WAKEUP_PIN4_LOW)   || \\\r\n                                            ((__PIN__) == PWR_WAKEUP_PIN5_LOW)\t || \\\r\n                                            ((__PIN__) == PWR_WAKEUP_PIN6_LOW))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n\r\n#endif /* __STM32F7xx_HAL_PWR_EX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_qspi.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_qspi.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of QSPI HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************  \r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_QSPI_H\r\n#define __STM32F7xx_HAL_QSPI_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup QSPI\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/ \r\n/** @defgroup QSPI_Exported_Types QSPI Exported Types\r\n  * @{\r\n  */\r\n  \r\n/** \r\n  * @brief  QSPI Init structure definition  \r\n  */\r\n\r\ntypedef struct\r\n{\r\n  uint32_t ClockPrescaler;     /* Specifies the prescaler factor for generating clock based on the AHB clock.\r\n                                  This parameter can be a number between 0 and 255 */ \r\n                                  \r\n  uint32_t FifoThreshold;      /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)\r\n                                  This parameter can be a value between 1 and 32 */\r\n                                  \r\n  uint32_t SampleShifting;     /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to \r\n                                  take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)\r\n                                  This parameter can be a value of @ref QSPI_SampleShifting */\r\n                                  \r\n  uint32_t FlashSize;          /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits \r\n                                  required to address the flash memory. The flash capacity can be up to 4GB \r\n                                  (addressed using 32 bits) in indirect mode, but the addressable space in \r\n                                  memory-mapped mode is limited to 256MB\r\n                                  This parameter can be a number between 0 and 31 */\r\n                                  \r\n  uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number \r\n                                  of clock cycles which the chip select must remain high between commands.\r\n                                  This parameter can be a value of @ref QSPI_ChipSelectHighTime */ \r\n                                    \r\n  uint32_t ClockMode;          /* Specifies the Clock Mode. It indicates the level that clock takes between commands.\r\n                                  This parameter can be a value of @ref QSPI_ClockMode */\r\n                                 \r\n  uint32_t FlashID;            /* Specifies the Flash which will be used,\r\n                                  This parameter can be a value of @ref QSPI_Flash_Select */\r\n                                 \r\n  uint32_t DualFlash;          /* Specifies the Dual Flash Mode State\r\n                                  This parameter can be a value of @ref QSPI_DualFlash_Mode */                                               \r\n}QSPI_InitTypeDef;\r\n\r\n/** \r\n  * @brief HAL QSPI State structures definition  \r\n  */ \r\ntypedef enum\r\n{\r\n  HAL_QSPI_STATE_RESET             = 0x00U,    /*!< Peripheral not initialized                            */\r\n  HAL_QSPI_STATE_READY             = 0x01U,    /*!< Peripheral initialized and ready for use              */\r\n  HAL_QSPI_STATE_BUSY              = 0x02U,    /*!< Peripheral in indirect mode and busy                  */ \r\n  HAL_QSPI_STATE_BUSY_INDIRECT_TX  = 0x12U,    /*!< Peripheral in indirect mode with transmission ongoing */ \r\n  HAL_QSPI_STATE_BUSY_INDIRECT_RX  = 0x22U,    /*!< Peripheral in indirect mode with reception ongoing    */\r\n  HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U,    /*!< Peripheral in auto polling mode ongoing               */\r\n  HAL_QSPI_STATE_BUSY_MEM_MAPPED   = 0x82U,    /*!< Peripheral in memory mapped mode ongoing              */\r\n  HAL_QSPI_STATE_ABORT             = 0x08U,    /*!< Peripheral with abort request ongoing                 */\r\n  HAL_QSPI_STATE_ERROR             = 0x04U     /*!< Peripheral in error                                   */\r\n}HAL_QSPI_StateTypeDef;\r\n\r\n/** \r\n  * @brief  QSPI Handle Structure definition  \r\n  */  \r\ntypedef struct\r\n{\r\n  QUADSPI_TypeDef            *Instance;        /* QSPI registers base address        */\r\n  QSPI_InitTypeDef           Init;             /* QSPI communication parameters      */\r\n  uint8_t                    *pTxBuffPtr;      /* Pointer to QSPI Tx transfer Buffer */\r\n  __IO uint32_t              TxXferSize;       /* QSPI Tx Transfer size              */\r\n  __IO uint32_t              TxXferCount;      /* QSPI Tx Transfer Counter           */\r\n  uint8_t                    *pRxBuffPtr;      /* Pointer to QSPI Rx transfer Buffer */\r\n  __IO uint32_t              RxXferSize;       /* QSPI Rx Transfer size              */\r\n  __IO uint32_t              RxXferCount;      /* QSPI Rx Transfer Counter           */\r\n  DMA_HandleTypeDef          *hdma;            /* QSPI Rx/Tx DMA Handle parameters   */\r\n  __IO HAL_LockTypeDef       Lock;             /* Locking object                     */\r\n  __IO HAL_QSPI_StateTypeDef State;            /* QSPI communication state           */\r\n  __IO uint32_t              ErrorCode;        /* QSPI Error code                    */\r\n  uint32_t                   Timeout;          /* Timeout for the QSPI memory access */ \r\n}QSPI_HandleTypeDef;\r\n\r\n/** \r\n  * @brief  QSPI Command structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t Instruction;        /* Specifies the Instruction to be sent\r\n                                  This parameter can be a value (8-bit) between 0x00 and 0xFF */\r\n  uint32_t Address;            /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)\r\n                                  This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */\r\n  uint32_t AlternateBytes;     /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)\r\n                                  This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */\r\n  uint32_t AddressSize;        /* Specifies the Address Size\r\n                                  This parameter can be a value of @ref QSPI_AddressSize */\r\n  uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size\r\n                                  This parameter can be a value of @ref QSPI_AlternateBytesSize */\r\n  uint32_t DummyCycles;        /* Specifies the Number of Dummy Cycles.\r\n                                  This parameter can be a number between 0 and 31 */\r\n  uint32_t InstructionMode;    /* Specifies the Instruction Mode\r\n                                  This parameter can be a value of @ref QSPI_InstructionMode */\r\n  uint32_t AddressMode;        /* Specifies the Address Mode\r\n                                  This parameter can be a value of @ref QSPI_AddressMode */\r\n  uint32_t AlternateByteMode;  /* Specifies the Alternate Bytes Mode\r\n                                  This parameter can be a value of @ref QSPI_AlternateBytesMode */\r\n  uint32_t DataMode;           /* Specifies the Data Mode (used for dummy cycles and data phases)\r\n                                  This parameter can be a value of @ref QSPI_DataMode */\r\n  uint32_t NbData;             /* Specifies the number of data to transfer. \r\n                                  This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length \r\n                                  until end of memory)*/\r\n  uint32_t DdrMode;            /* Specifies the double data rate mode for address, alternate byte and data phase\r\n                                  This parameter can be a value of @ref QSPI_DdrMode */\r\n  uint32_t DdrHoldHalfCycle;   /* Specifies the DDR hold half cycle. It delays the data output by one half of \r\n                                  system clock in DDR mode.\r\n                                  This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */\r\n  uint32_t SIOOMode;          /* Specifies the send instruction only once mode\r\n                                  This parameter can be a value of @ref QSPI_SIOOMode */\r\n}QSPI_CommandTypeDef;\r\n\r\n/** \r\n  * @brief  QSPI Auto Polling mode configuration structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t Match;              /* Specifies the value to be compared with the masked status register to get a match.\r\n                                  This parameter can be any value between 0 and 0xFFFFFFFF */\r\n  uint32_t Mask;               /* Specifies the mask to be applied to the status bytes received. \r\n                                  This parameter can be any value between 0 and 0xFFFFFFFF */\r\n  uint32_t Interval;           /* Specifies the number of clock cycles between two read during automatic polling phases.\r\n                                  This parameter can be any value between 0 and 0xFFFF */\r\n  uint32_t StatusBytesSize;    /* Specifies the size of the status bytes received.\r\n                                  This parameter can be any value between 1 and 4 */\r\n  uint32_t MatchMode;          /* Specifies the method used for determining a match.\r\n                                  This parameter can be a value of @ref QSPI_MatchMode */\r\n  uint32_t AutomaticStop;      /* Specifies if automatic polling is stopped after a match.\r\n                                  This parameter can be a value of @ref QSPI_AutomaticStop */\r\n}QSPI_AutoPollingTypeDef;\r\n                           \r\n/** \r\n  * @brief  QSPI Memory Mapped mode configuration structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t TimeOutPeriod;      /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.\r\n                                  This parameter can be any value between 0 and 0xFFFF */\r\n  uint32_t TimeOutActivation;  /* Specifies if the time out counter is enabled to release the chip select. \r\n                                  This parameter can be a value of @ref QSPI_TimeOutActivation */\r\n}QSPI_MemoryMappedTypeDef;                                     \r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup QSPI_Exported_Constants QSPI Exported Constants\r\n  * @{\r\n  */\r\n/** @defgroup QSPI_ErrorCode QSPI Error Code\r\n  * @{\r\n  */ \r\n#define HAL_QSPI_ERROR_NONE            ((uint32_t)0x00000000U) /*!< No error           */\r\n#define HAL_QSPI_ERROR_TIMEOUT         ((uint32_t)0x00000001U) /*!< Timeout error      */\r\n#define HAL_QSPI_ERROR_TRANSFER        ((uint32_t)0x00000002U) /*!< Transfer error     */\r\n#define HAL_QSPI_ERROR_DMA             ((uint32_t)0x00000004U) /*!< DMA transfer error */\r\n#define HAL_QSPI_ERROR_INVALID_PARAM   ((uint32_t)0x00000008U) /*!< Invalid parameters error */\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/** @defgroup QSPI_SampleShifting QSPI Sample Shifting\r\n  * @{\r\n  */\r\n#define QSPI_SAMPLE_SHIFTING_NONE           ((uint32_t)0x00000000U)        /*!<No clock cycle shift to sample data*/\r\n#define QSPI_SAMPLE_SHIFTING_HALFCYCLE      ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup QSPI_ChipSelectHighTime QSPI Chip Select High Time\r\n  * @{\r\n  */\r\n#define QSPI_CS_HIGH_TIME_1_CYCLE           ((uint32_t)0x00000000U)                              /*!<nCS stay high for at least 1 clock cycle between commands*/\r\n#define QSPI_CS_HIGH_TIME_2_CYCLE           ((uint32_t)QUADSPI_DCR_CSHT_0)                      /*!<nCS stay high for at least 2 clock cycles between commands*/\r\n#define QSPI_CS_HIGH_TIME_3_CYCLE           ((uint32_t)QUADSPI_DCR_CSHT_1)                      /*!<nCS stay high for at least 3 clock cycles between commands*/\r\n#define QSPI_CS_HIGH_TIME_4_CYCLE           ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/\r\n#define QSPI_CS_HIGH_TIME_5_CYCLE           ((uint32_t)QUADSPI_DCR_CSHT_2)                      /*!<nCS stay high for at least 5 clock cycles between commands*/\r\n#define QSPI_CS_HIGH_TIME_6_CYCLE           ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/\r\n#define QSPI_CS_HIGH_TIME_7_CYCLE           ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/\r\n#define QSPI_CS_HIGH_TIME_8_CYCLE           ((uint32_t)QUADSPI_DCR_CSHT)                        /*!<nCS stay high for at least 8 clock cycles between commands*/\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup QSPI_ClockMode QSPI Clock Mode\r\n  * @{\r\n  */\r\n#define QSPI_CLOCK_MODE_0                   ((uint32_t)0x00000000U)         /*!<Clk stays low while nCS is released*/\r\n#define QSPI_CLOCK_MODE_3                   ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup QSPI_Flash_Select QSPI Flash Select\r\n  * @{\r\n  */\r\n#define QSPI_FLASH_ID_1           ((uint32_t)0x00000000U)\r\n#define QSPI_FLASH_ID_2           ((uint32_t)QUADSPI_CR_FSEL)\r\n/**\r\n  * @}\r\n  */  \r\n\r\n  /** @defgroup QSPI_DualFlash_Mode  QSPI Dual Flash Mode\r\n  * @{\r\n  */\r\n#define QSPI_DUALFLASH_ENABLE            ((uint32_t)QUADSPI_CR_DFM)\r\n#define QSPI_DUALFLASH_DISABLE           ((uint32_t)0x00000000U) \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup QSPI_AddressSize QSPI Address Size \r\n  * @{\r\n  */\r\n#define QSPI_ADDRESS_8_BITS            ((uint32_t)0x00000000U)           /*!<8-bit address*/\r\n#define QSPI_ADDRESS_16_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/\r\n#define QSPI_ADDRESS_24_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/\r\n#define QSPI_ADDRESS_32_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE)   /*!<32-bit address*/\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size\r\n  * @{\r\n  */\r\n#define QSPI_ALTERNATE_BYTES_8_BITS    ((uint32_t)0x00000000U)           /*!<8-bit alternate bytes*/\r\n#define QSPI_ALTERNATE_BYTES_16_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/\r\n#define QSPI_ALTERNATE_BYTES_24_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/\r\n#define QSPI_ALTERNATE_BYTES_32_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE)   /*!<32-bit alternate bytes*/\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup QSPI_InstructionMode QSPI Instruction Mode\r\n* @{\r\n*/\r\n#define QSPI_INSTRUCTION_NONE          ((uint32_t)0x00000000U)          /*!<No instruction*/\r\n#define QSPI_INSTRUCTION_1_LINE        ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/\r\n#define QSPI_INSTRUCTION_2_LINES       ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/\r\n#define QSPI_INSTRUCTION_4_LINES       ((uint32_t)QUADSPI_CCR_IMODE)   /*!<Instruction on four lines*/\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup QSPI_AddressMode QSPI Address Mode\r\n* @{\r\n*/\r\n#define QSPI_ADDRESS_NONE              ((uint32_t)0x00000000U)           /*!<No address*/\r\n#define QSPI_ADDRESS_1_LINE            ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/\r\n#define QSPI_ADDRESS_2_LINES           ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/\r\n#define QSPI_ADDRESS_4_LINES           ((uint32_t)QUADSPI_CCR_ADMODE)   /*!<Address on four lines*/\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup QSPI_AlternateBytesMode  QSPI Alternate Bytes Mode\r\n* @{                                  \r\n*/\r\n#define QSPI_ALTERNATE_BYTES_NONE      ((uint32_t)0x00000000U)           /*!<No alternate bytes*/\r\n#define QSPI_ALTERNATE_BYTES_1_LINE    ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/\r\n#define QSPI_ALTERNATE_BYTES_2_LINES   ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/\r\n#define QSPI_ALTERNATE_BYTES_4_LINES   ((uint32_t)QUADSPI_CCR_ABMODE)   /*!<Alternate bytes on four lines*/\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup QSPI_DataMode QSPI Data Mode\r\n  * @{\r\n  */\r\n#define QSPI_DATA_NONE                 ((uint32_t)0X00000000)           /*!<No data*/\r\n#define QSPI_DATA_1_LINE               ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/\r\n#define QSPI_DATA_2_LINES              ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/\r\n#define QSPI_DATA_4_LINES              ((uint32_t)QUADSPI_CCR_DMODE)   /*!<Data on four lines*/\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup QSPI_DdrMode QSPI Ddr Mode\r\n  * @{\r\n  */\r\n#define QSPI_DDR_MODE_DISABLE              ((uint32_t)0x00000000U)       /*!<Double data rate mode disabled*/\r\n#define QSPI_DDR_MODE_ENABLE               ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup QSPI_DdrHoldHalfCycle QSPI Ddr HoldHalfCycle\r\n  * @{\r\n  */\r\n#define QSPI_DDR_HHC_ANALOG_DELAY           ((uint32_t)0x00000000U)       /*!<Delay the data output using analog delay in DDR mode*/\r\n#define QSPI_DDR_HHC_HALF_CLK_DELAY         ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup QSPI_SIOOMode QSPI SIOO Mode\r\n  * @{\r\n  */\r\n#define QSPI_SIOO_INST_EVERY_CMD       ((uint32_t)0x00000000U)       /*!<Send instruction on every transaction*/\r\n#define QSPI_SIOO_INST_ONLY_FIRST_CMD  ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup QSPI_MatchMode QSPI Match Mode\r\n  * @{\r\n  */\r\n#define QSPI_MATCH_MODE_AND                 ((uint32_t)0x00000000U)     /*!<AND match mode between unmasked bits*/\r\n#define QSPI_MATCH_MODE_OR                  ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop\r\n  * @{\r\n  */\r\n#define QSPI_AUTOMATIC_STOP_DISABLE        ((uint32_t)0x00000000U)      /*!<AutoPolling stops only with abort or QSPI disabling*/\r\n#define QSPI_AUTOMATIC_STOP_ENABLE         ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup QSPI_TimeOutActivation QSPI TimeOut Activation\r\n  * @{\r\n  */\r\n#define QSPI_TIMEOUT_COUNTER_DISABLE       ((uint32_t)0x00000000U)      /*!<Timeout counter disabled, nCS remains active*/\r\n#define QSPI_TIMEOUT_COUNTER_ENABLE        ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup QSPI_Flags  QSPI Flags\r\n  * @{\r\n  */\r\n#define QSPI_FLAG_BUSY                 QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/\r\n#define QSPI_FLAG_TO                   QUADSPI_SR_TOF  /*!<Timeout flag: timeout occurs in memory-mapped mode*/\r\n#define QSPI_FLAG_SM                   QUADSPI_SR_SMF  /*!<Status match flag: received data matches in autopolling mode*/\r\n#define QSPI_FLAG_FT                   QUADSPI_SR_FTF  /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/\r\n#define QSPI_FLAG_TC                   QUADSPI_SR_TCF  /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/\r\n#define QSPI_FLAG_TE                   QUADSPI_SR_TEF  /*!<Transfer error flag: invalid address is being accessed*/\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup QSPI_Interrupts  QSPI Interrupts\r\n  * @{\r\n  */  \r\n#define QSPI_IT_TO                          QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/\r\n#define QSPI_IT_SM                          QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/\r\n#define QSPI_IT_FT                          QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/\r\n#define QSPI_IT_TC                          QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/\r\n#define QSPI_IT_TE                          QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup QSPI_Timeout_definition QSPI Timeout definition\r\n  * @{\r\n  */ \r\n#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */\r\n/**\r\n  * @}\r\n  */  \r\n    \r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macros -----------------------------------------------------------*/\r\n/** @defgroup QSPI_Exported_Macros QSPI Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief Reset QSPI handle state\r\n  * @param  __HANDLE__ QSPI handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)\r\n\r\n/** @brief  Enable QSPI\r\n  * @param  __HANDLE__ specifies the QSPI Handle.\r\n  * @retval None\r\n  */ \r\n#define __HAL_QSPI_ENABLE(__HANDLE__)                       SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)\r\n\r\n/** @brief  Disable QSPI\r\n  * @param  __HANDLE__ specifies the QSPI Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_QSPI_DISABLE(__HANDLE__)                      CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)\r\n\r\n/** @brief  Enables the specified QSPI interrupt.\r\n  * @param  __HANDLE__ specifies the QSPI Handle.\r\n  * @param  __INTERRUPT__ specifies the QSPI interrupt source to enable.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg QSPI_IT_TO: QSPI Time out interrupt\r\n  *            @arg QSPI_IT_SM: QSPI Status match interrupt\r\n  *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt\r\n  *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt\r\n  *            @arg QSPI_IT_TE: QSPI Transfer error interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)     SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\r\n\r\n\r\n/** @brief  Disables the specified QSPI interrupt.\r\n  * @param  __HANDLE__ specifies the QSPI Handle.\r\n  * @param  __INTERRUPT__ specifies the QSPI interrupt source to disable.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg QSPI_IT_TO: QSPI Timeout interrupt\r\n  *            @arg QSPI_IT_SM: QSPI Status match interrupt\r\n  *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt\r\n  *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt\r\n  *            @arg QSPI_IT_TE: QSPI Transfer error interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)    CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\r\n\r\n/** @brief  Checks whether the specified QSPI interrupt source is enabled.\r\n  * @param  __HANDLE__ specifies the QSPI Handle.\r\n  * @param  __INTERRUPT__ specifies the QSPI interrupt source to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg QSPI_IT_TO: QSPI Time out interrupt\r\n  *            @arg QSPI_IT_SM: QSPI Status match interrupt\r\n  *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt\r\n  *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt\r\n  *            @arg QSPI_IT_TE: QSPI Transfer error interrupt\r\n  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) \r\n\r\n/**\r\n  * @brief  Get the selected QSPI's flag status.\r\n  * @param  __HANDLE__ specifies the QSPI Handle.\r\n  * @param  __FLAG__ specifies the QSPI flag to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg QSPI_FLAG_BUSY: QSPI Busy flag\r\n  *            @arg QSPI_FLAG_TO:   QSPI Time out flag\r\n  *            @arg QSPI_FLAG_SM:   QSPI Status match flag\r\n  *            @arg QSPI_FLAG_FT:   QSPI FIFO threshold flag\r\n  *            @arg QSPI_FLAG_TC:   QSPI Transfer complete flag\r\n  *            @arg QSPI_FLAG_TE:   QSPI Transfer error flag\r\n  * @retval None\r\n  */\r\n#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__)           (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0)\r\n\r\n/** @brief  Clears the specified QSPI's flag status.\r\n  * @param  __HANDLE__ specifies the QSPI Handle.\r\n  * @param  __FLAG__ specifies the QSPI clear register flag that needs to be set\r\n  *          This parameter can be one of the following values:\r\n  *            @arg QSPI_FLAG_TO: QSPI Time out flag\r\n  *            @arg QSPI_FLAG_SM: QSPI Status match flag\r\n  *            @arg QSPI_FLAG_TC: QSPI Transfer complete flag\r\n  *            @arg QSPI_FLAG_TE: QSPI Transfer error flag\r\n  * @retval None\r\n  */\r\n#define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__)         WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup QSPI_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup QSPI_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n/* Initialization/de-initialization functions  ********************************/\r\nHAL_StatusTypeDef     HAL_QSPI_Init     (QSPI_HandleTypeDef *hqspi);\r\nHAL_StatusTypeDef     HAL_QSPI_DeInit   (QSPI_HandleTypeDef *hqspi);\r\nvoid                  HAL_QSPI_MspInit  (QSPI_HandleTypeDef *hqspi);\r\nvoid                  HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup QSPI_Exported_Functions_Group2\r\n  * @{\r\n  */  \r\n/* IO operation functions *****************************************************/\r\n/* QSPI IRQ handler method */\r\nvoid                  HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);\r\n\r\n/* QSPI indirect mode */\r\nHAL_StatusTypeDef     HAL_QSPI_Command      (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);\r\nHAL_StatusTypeDef     HAL_QSPI_Transmit     (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);\r\nHAL_StatusTypeDef     HAL_QSPI_Receive      (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);\r\nHAL_StatusTypeDef     HAL_QSPI_Command_IT   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);\r\nHAL_StatusTypeDef     HAL_QSPI_Transmit_IT  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);\r\nHAL_StatusTypeDef     HAL_QSPI_Receive_IT   (QSPI_HandleTypeDef *hqspi, uint8_t *pData);\r\nHAL_StatusTypeDef     HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);\r\nHAL_StatusTypeDef     HAL_QSPI_Receive_DMA  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);\r\n\r\n/* QSPI status flag polling mode */\r\nHAL_StatusTypeDef     HAL_QSPI_AutoPolling   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);\r\nHAL_StatusTypeDef     HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);\r\n\r\n/* QSPI memory-mapped mode */\r\nHAL_StatusTypeDef     HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup QSPI_Exported_Functions_Group3\r\n  * @{\r\n  */  \r\n/* Callback functions in non-blocking modes ***********************************/\r\nvoid                  HAL_QSPI_ErrorCallback        (QSPI_HandleTypeDef *hqspi);\r\nvoid                  HAL_QSPI_AbortCpltCallback    (QSPI_HandleTypeDef *hqspi);\r\nvoid                  HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);\r\n\r\n/* QSPI indirect mode */\r\nvoid                  HAL_QSPI_CmdCpltCallback      (QSPI_HandleTypeDef *hqspi);\r\nvoid                  HAL_QSPI_RxCpltCallback       (QSPI_HandleTypeDef *hqspi);\r\nvoid                  HAL_QSPI_TxCpltCallback       (QSPI_HandleTypeDef *hqspi);\r\nvoid                  HAL_QSPI_RxHalfCpltCallback   (QSPI_HandleTypeDef *hqspi);\r\nvoid                  HAL_QSPI_TxHalfCpltCallback   (QSPI_HandleTypeDef *hqspi);\r\n\r\n/* QSPI status flag polling mode */\r\nvoid                  HAL_QSPI_StatusMatchCallback  (QSPI_HandleTypeDef *hqspi);\r\n\r\n/* QSPI memory-mapped mode */\r\nvoid                  HAL_QSPI_TimeOutCallback      (QSPI_HandleTypeDef *hqspi);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup QSPI_Exported_Functions_Group4\r\n  * @{\r\n  */  \r\n/* Peripheral Control and State functions  ************************************/\r\nHAL_QSPI_StateTypeDef HAL_QSPI_GetState        (QSPI_HandleTypeDef *hqspi);\r\nuint32_t              HAL_QSPI_GetError        (QSPI_HandleTypeDef *hqspi);\r\nHAL_StatusTypeDef     HAL_QSPI_Abort           (QSPI_HandleTypeDef *hqspi);\r\nHAL_StatusTypeDef     HAL_QSPI_Abort_IT        (QSPI_HandleTypeDef *hqspi);\r\nvoid                  HAL_QSPI_SetTimeout      (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);\r\nHAL_StatusTypeDef     HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);\r\nuint32_t              HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup QSPI_Private_Macros QSPI Private Macros\r\n  * @{\r\n  */\r\n/** @defgroup QSPI_ClockPrescaler QSPI Clock Prescaler\r\n  * @{\r\n  */ \r\n#define IS_QSPI_CLOCK_PRESCALER(PRESCALER)  ((PRESCALER) <= 0xFF)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup QSPI_FifoThreshold  QSPI Fifo Threshold \r\n  * @{\r\n  */\r\n#define IS_QSPI_FIFO_THRESHOLD(THR)         (((THR) > 0) && ((THR) <= 32))\r\n/**\r\n  * @}\r\n  */\r\n  \r\n#define IS_QSPI_SSHIFT(SSHIFT)              (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \\\r\n                                             ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE)) \r\n\r\n/** @defgroup QSPI_FlashSize QSPI Flash Size\r\n  * @{\r\n  */\r\n#define IS_QSPI_FLASH_SIZE(FSIZE)           (((FSIZE) <= 31))\r\n/**\r\n  * @}\r\n  */\r\n  \r\n#define IS_QSPI_CS_HIGH_TIME(CSHTIME)       (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \\\r\n                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \\\r\n                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \\\r\n                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \\\r\n                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \\\r\n                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \\\r\n                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \\\r\n                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))   \r\n\r\n#define IS_QSPI_CLOCK_MODE(CLKMODE)         (((CLKMODE) == QSPI_CLOCK_MODE_0) || \\\r\n                                             ((CLKMODE) == QSPI_CLOCK_MODE_3))\r\n\r\n#define IS_QSPI_FLASH_ID(FLA)    (((FLA) == QSPI_FLASH_ID_1) || \\\r\n                                  ((FLA) == QSPI_FLASH_ID_2)) \r\n                                  \r\n#define IS_QSPI_DUAL_FLASH_MODE(MODE)    (((MODE) == QSPI_DUALFLASH_ENABLE) || \\\r\n                                          ((MODE) == QSPI_DUALFLASH_DISABLE))\r\n                                          \r\n  \r\n/** @defgroup QSPI_Instruction QSPI Instruction\r\n  * @{\r\n  */\r\n#define IS_QSPI_INSTRUCTION(INSTRUCTION)    ((INSTRUCTION) <= 0xFF) \r\n/**\r\n  * @}\r\n  */ \r\n\r\n#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE)     (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS)  || \\\r\n                                             ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \\\r\n                                             ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \\\r\n                                             ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))\r\n\r\n#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE)  (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS)  || \\\r\n                                             ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \\\r\n                                             ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \\\r\n                                             ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))                                               \r\n\r\n\r\n/** @defgroup QSPI_DummyCycles QSPI Dummy Cycles\r\n  * @{\r\n  */\r\n#define IS_QSPI_DUMMY_CYCLES(DCY)           ((DCY) <= 31) \r\n/**\r\n  * @}\r\n  */\r\n\r\n#define IS_QSPI_INSTRUCTION_MODE(MODE)      (((MODE) == QSPI_INSTRUCTION_NONE)    || \\\r\n                                             ((MODE) == QSPI_INSTRUCTION_1_LINE)  || \\\r\n                                             ((MODE) == QSPI_INSTRUCTION_2_LINES) || \\\r\n                                             ((MODE) == QSPI_INSTRUCTION_4_LINES))  \r\n\r\n#define IS_QSPI_ADDRESS_MODE(MODE)          (((MODE) == QSPI_ADDRESS_NONE)    || \\\r\n                                             ((MODE) == QSPI_ADDRESS_1_LINE)  || \\\r\n                                             ((MODE) == QSPI_ADDRESS_2_LINES) || \\\r\n                                             ((MODE) == QSPI_ADDRESS_4_LINES))\r\n\r\n#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE)  (((MODE) == QSPI_ALTERNATE_BYTES_NONE)    || \\\r\n                                             ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE)  || \\\r\n                                             ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \\\r\n                                             ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))\r\n\r\n#define IS_QSPI_DATA_MODE(MODE)             (((MODE) == QSPI_DATA_NONE)    || \\\r\n                                             ((MODE) == QSPI_DATA_1_LINE)  || \\\r\n                                             ((MODE) == QSPI_DATA_2_LINES) || \\\r\n                                             ((MODE) == QSPI_DATA_4_LINES))\r\n\r\n#define IS_QSPI_DDR_MODE(DDR_MODE)          (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \\\r\n                                             ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))\r\n\r\n#define IS_QSPI_DDR_HHC(DDR_HHC)            (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \\\r\n                                             ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))\r\n\r\n#define IS_QSPI_SIOO_MODE(SIOO_MODE)      (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \\\r\n                                             ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))\r\n\r\n/** @defgroup QSPI_Interval QSPI Interval \r\n  * @{\r\n  */\r\n#define IS_QSPI_INTERVAL(INTERVAL)        ((INTERVAL) <= QUADSPI_PIR_INTERVAL) \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup QSPI_StatusBytesSize QSPI Status Bytes Size\r\n  * @{\r\n  */\r\n#define IS_QSPI_STATUS_BYTES_SIZE(SIZE)   (((SIZE) >= 1) && ((SIZE) <= 4)) \r\n/**\r\n  * @}\r\n  */\r\n#define IS_QSPI_MATCH_MODE(MODE)            (((MODE) == QSPI_MATCH_MODE_AND) || \\\r\n                                             ((MODE) == QSPI_MATCH_MODE_OR)) \r\n                                             \r\n#define IS_QSPI_AUTOMATIC_STOP(APMS)        (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \\\r\n                                             ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))                                                                                                                                                                                                                                    \r\n\r\n#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN)    (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \\\r\n                                             ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) \r\n\r\n/** @defgroup QSPI_TimeOutPeriod  QSPI TimeOut Period\r\n  * @{\r\n  */\r\n#define IS_QSPI_TIMEOUT_PERIOD(PERIOD)      ((PERIOD) <= 0xFFFF) \r\n/**\r\n  * @}\r\n  */\r\n\r\n#define IS_QSPI_GET_FLAG(FLAG)              (((FLAG) == QSPI_FLAG_BUSY) || \\\r\n                                             ((FLAG) == QSPI_FLAG_TO)   || \\\r\n                                             ((FLAG) == QSPI_FLAG_SM)   || \\\r\n                                             ((FLAG) == QSPI_FLAG_FT)   || \\\r\n                                             ((FLAG) == QSPI_FLAG_TC)   || \\\r\n                                             ((FLAG) == QSPI_FLAG_TE))    \r\n\r\n#define IS_QSPI_IT(IT)                      ((((IT) & (uint32_t)0xFFE0FFFFU) == 0x00000000U) && ((IT) != 0x00000000U))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup QSPI_Private_Functions QSPI Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_QSPI_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_rcc.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of RCC HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_RCC_H\r\n#define __STM32F7xx_HAL_RCC_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n   \r\n/* Include RCC HAL Extended module */\r\n/* (include on top of file since RCC structures are defined in extended file) */\r\n#include \"stm32f7xx_hal_rcc_ex.h\"   \r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup RCC\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/ \r\n\r\n/** @defgroup RCC_Exported_Types RCC Exported Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t OscillatorType;       /*!< The oscillators to be configured.\r\n                                      This parameter can be a value of @ref RCC_Oscillator_Type                   */\r\n\r\n  uint32_t HSEState;             /*!< The new state of the HSE.\r\n                                      This parameter can be a value of @ref RCC_HSE_Config                        */\r\n\r\n  uint32_t LSEState;             /*!< The new state of the LSE.\r\n                                      This parameter can be a value of @ref RCC_LSE_Config                        */\r\n                                          \r\n  uint32_t HSIState;             /*!< The new state of the HSI.\r\n                                      This parameter can be a value of @ref RCC_HSI_Config                        */\r\n\r\n  uint32_t HSICalibrationValue;   /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).\r\n                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */\r\n                               \r\n  uint32_t LSIState;             /*!< The new state of the LSI.\r\n                                      This parameter can be a value of @ref RCC_LSI_Config                        */\r\n\r\n  RCC_PLLInitTypeDef PLL;        /*!< PLL structure parameters                                                    */      \r\n\r\n}RCC_OscInitTypeDef;\r\n\r\n/**\r\n  * @brief  RCC System, AHB and APB busses clock configuration structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t ClockType;             /*!< The clock to be configured.\r\n                                       This parameter can be a value of @ref RCC_System_Clock_Type */\r\n  \r\n  uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.\r\n                                       This parameter can be a value of @ref RCC_System_Clock_Source    */\r\n\r\n  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).\r\n                                       This parameter can be a value of @ref RCC_AHB_Clock_Source       */\r\n\r\n  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).\r\n                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */\r\n\r\n  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).\r\n                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */\r\n\r\n}RCC_ClkInitTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup RCC_Exported_Constants RCC Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup RCC_Oscillator_Type Oscillator Type\r\n  * @{\r\n  */\r\n#define RCC_OSCILLATORTYPE_NONE            ((uint32_t)0x00000000U)\r\n#define RCC_OSCILLATORTYPE_HSE             ((uint32_t)0x00000001U)\r\n#define RCC_OSCILLATORTYPE_HSI             ((uint32_t)0x00000002U)\r\n#define RCC_OSCILLATORTYPE_LSE             ((uint32_t)0x00000004U)\r\n#define RCC_OSCILLATORTYPE_LSI             ((uint32_t)0x00000008U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_HSE_Config RCC HSE Config\r\n  * @{\r\n  */\r\n#define RCC_HSE_OFF                      ((uint32_t)0x00000000U)\r\n#define RCC_HSE_ON                       RCC_CR_HSEON\r\n#define RCC_HSE_BYPASS                   ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_LSE_Config RCC LSE Config\r\n  * @{\r\n  */\r\n#define RCC_LSE_OFF                    ((uint32_t)0x00000000U)\r\n#define RCC_LSE_ON                     RCC_BDCR_LSEON\r\n#define RCC_LSE_BYPASS                 ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_HSI_Config RCC HSI Config\r\n  * @{\r\n  */\r\n#define RCC_HSI_OFF                    ((uint32_t)0x00000000U)\r\n#define RCC_HSI_ON                     RCC_CR_HSION\r\n\r\n#define RCC_HSICALIBRATION_DEFAULT     ((uint32_t)0x10U)         /* Default HSI calibration trimming value */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_LSI_Config RCC LSI Config\r\n  * @{\r\n  */\r\n#define RCC_LSI_OFF                    ((uint32_t)0x00000000U)\r\n#define RCC_LSI_ON                     RCC_CSR_LSION\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_PLL_Config RCC PLL Config\r\n  * @{\r\n  */\r\n#define RCC_PLL_NONE                   ((uint32_t)0x00000000U)\r\n#define RCC_PLL_OFF                    ((uint32_t)0x00000001U)\r\n#define RCC_PLL_ON                     ((uint32_t)0x00000002U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider\r\n  * @{\r\n  */\r\n#define RCC_PLLP_DIV2                  ((uint32_t)0x00000002U)\r\n#define RCC_PLLP_DIV4                  ((uint32_t)0x00000004U)\r\n#define RCC_PLLP_DIV6                  ((uint32_t)0x00000006U)\r\n#define RCC_PLLP_DIV8                  ((uint32_t)0x00000008U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_PLL_Clock_Source PLL Clock Source\r\n  * @{\r\n  */\r\n#define RCC_PLLSOURCE_HSI                RCC_PLLCFGR_PLLSRC_HSI\r\n#define RCC_PLLSOURCE_HSE                RCC_PLLCFGR_PLLSRC_HSE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_System_Clock_Type RCC System Clock Type\r\n  * @{\r\n  */\r\n#define RCC_CLOCKTYPE_SYSCLK             ((uint32_t)0x00000001U)\r\n#define RCC_CLOCKTYPE_HCLK               ((uint32_t)0x00000002U)\r\n#define RCC_CLOCKTYPE_PCLK1              ((uint32_t)0x00000004U)\r\n#define RCC_CLOCKTYPE_PCLK2              ((uint32_t)0x00000008U)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup RCC_System_Clock_Source RCC System Clock Source\r\n  * @{\r\n  */\r\n#define RCC_SYSCLKSOURCE_HSI             RCC_CFGR_SW_HSI\r\n#define RCC_SYSCLKSOURCE_HSE             RCC_CFGR_SW_HSE\r\n#define RCC_SYSCLKSOURCE_PLLCLK          RCC_CFGR_SW_PLL\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status\r\n  * @{\r\n  */\r\n#define RCC_SYSCLKSOURCE_STATUS_HSI      RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */\r\n#define RCC_SYSCLKSOURCE_STATUS_HSE      RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */\r\n#define RCC_SYSCLKSOURCE_STATUS_PLLCLK   RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source\r\n  * @{\r\n  */\r\n#define RCC_SYSCLK_DIV1                  RCC_CFGR_HPRE_DIV1\r\n#define RCC_SYSCLK_DIV2                  RCC_CFGR_HPRE_DIV2\r\n#define RCC_SYSCLK_DIV4                  RCC_CFGR_HPRE_DIV4\r\n#define RCC_SYSCLK_DIV8                  RCC_CFGR_HPRE_DIV8\r\n#define RCC_SYSCLK_DIV16                 RCC_CFGR_HPRE_DIV16\r\n#define RCC_SYSCLK_DIV64                 RCC_CFGR_HPRE_DIV64\r\n#define RCC_SYSCLK_DIV128                RCC_CFGR_HPRE_DIV128\r\n#define RCC_SYSCLK_DIV256                RCC_CFGR_HPRE_DIV256\r\n#define RCC_SYSCLK_DIV512                RCC_CFGR_HPRE_DIV512\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1/APB2 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_HCLK_DIV1                    RCC_CFGR_PPRE1_DIV1\r\n#define RCC_HCLK_DIV2                    RCC_CFGR_PPRE1_DIV2\r\n#define RCC_HCLK_DIV4                    RCC_CFGR_PPRE1_DIV4\r\n#define RCC_HCLK_DIV8                    RCC_CFGR_PPRE1_DIV8\r\n#define RCC_HCLK_DIV16                   RCC_CFGR_PPRE1_DIV16\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source\r\n  * @{\r\n  */\r\n#define RCC_RTCCLKSOURCE_NO_CLK          ((uint32_t)0x00000000U)\r\n#define RCC_RTCCLKSOURCE_LSE             ((uint32_t)0x00000100U)\r\n#define RCC_RTCCLKSOURCE_LSI             ((uint32_t)0x00000200U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIVX        ((uint32_t)0x00000300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV2        ((uint32_t)0x00020300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV3        ((uint32_t)0x00030300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV4        ((uint32_t)0x00040300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV5        ((uint32_t)0x00050300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV6        ((uint32_t)0x00060300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV7        ((uint32_t)0x00070300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV8        ((uint32_t)0x00080300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV9        ((uint32_t)0x00090300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV10       ((uint32_t)0x000A0300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV11       ((uint32_t)0x000B0300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV12       ((uint32_t)0x000C0300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV13       ((uint32_t)0x000D0300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV14       ((uint32_t)0x000E0300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV15       ((uint32_t)0x000F0300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV16       ((uint32_t)0x00100300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV17       ((uint32_t)0x00110300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV18       ((uint32_t)0x00120300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV19       ((uint32_t)0x00130300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV20       ((uint32_t)0x00140300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV21       ((uint32_t)0x00150300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV22       ((uint32_t)0x00160300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV23       ((uint32_t)0x00170300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV24       ((uint32_t)0x00180300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV25       ((uint32_t)0x00190300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV26       ((uint32_t)0x001A0300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV27       ((uint32_t)0x001B0300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV28       ((uint32_t)0x001C0300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV29       ((uint32_t)0x001D0300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV30       ((uint32_t)0x001E0300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV31       ((uint32_t)0x001F0300U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n\r\n/** @defgroup RCC_MCO_Index RCC MCO Index\r\n  * @{\r\n  */\r\n#define RCC_MCO1                         ((uint32_t)0x00000000U)\r\n#define RCC_MCO2                         ((uint32_t)0x00000001U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_MCO1SOURCE_HSI               ((uint32_t)0x00000000U)\r\n#define RCC_MCO1SOURCE_LSE               RCC_CFGR_MCO1_0\r\n#define RCC_MCO1SOURCE_HSE               RCC_CFGR_MCO1_1\r\n#define RCC_MCO1SOURCE_PLLCLK            RCC_CFGR_MCO1\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_MCO2SOURCE_SYSCLK            ((uint32_t)0x00000000U)\r\n#define RCC_MCO2SOURCE_PLLI2SCLK         RCC_CFGR_MCO2_0\r\n#define RCC_MCO2SOURCE_HSE               RCC_CFGR_MCO2_1\r\n#define RCC_MCO2SOURCE_PLLCLK            RCC_CFGR_MCO2\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler\r\n  * @{\r\n  */\r\n#define RCC_MCODIV_1                    ((uint32_t)0x00000000U)\r\n#define RCC_MCODIV_2                    RCC_CFGR_MCO1PRE_2\r\n#define RCC_MCODIV_3                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)\r\n#define RCC_MCODIV_4                    ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)\r\n#define RCC_MCODIV_5                    RCC_CFGR_MCO1PRE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_Interrupt RCC Interrupt \r\n  * @{\r\n  */\r\n#define RCC_IT_LSIRDY                    ((uint8_t)0x01U)\r\n#define RCC_IT_LSERDY                    ((uint8_t)0x02U)\r\n#define RCC_IT_HSIRDY                    ((uint8_t)0x04U)\r\n#define RCC_IT_HSERDY                    ((uint8_t)0x08U)\r\n#define RCC_IT_PLLRDY                    ((uint8_t)0x10U)\r\n#define RCC_IT_PLLI2SRDY                 ((uint8_t)0x20U)\r\n#define RCC_IT_PLLSAIRDY                 ((uint8_t)0x40U)\r\n#define RCC_IT_CSS                       ((uint8_t)0x80U)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup RCC_Flag RCC Flags\r\n  *        Elements values convention: 0XXYYYYYb\r\n  *           - YYYYY  : Flag position in the register\r\n  *           - 0XX  : Register index\r\n  *                 - 01: CR register\r\n  *                 - 10: BDCR register\r\n  *                 - 11: CSR register\r\n  * @{\r\n  */\r\n/* Flags in the CR register */\r\n#define RCC_FLAG_HSIRDY                  ((uint8_t)0x21U)\r\n#define RCC_FLAG_HSERDY                  ((uint8_t)0x31U)\r\n#define RCC_FLAG_PLLRDY                  ((uint8_t)0x39U)\r\n#define RCC_FLAG_PLLI2SRDY               ((uint8_t)0x3BU)\r\n#define RCC_FLAG_PLLSAIRDY               ((uint8_t)0x3CU)\r\n\r\n/* Flags in the BDCR register */\r\n#define RCC_FLAG_LSERDY                  ((uint8_t)0x41U)\r\n\r\n/* Flags in the CSR register */\r\n#define RCC_FLAG_LSIRDY                  ((uint8_t)0x61U)\r\n#define RCC_FLAG_BORRST                  ((uint8_t)0x79U)\r\n#define RCC_FLAG_PINRST                  ((uint8_t)0x7AU)\r\n#define RCC_FLAG_PORRST                  ((uint8_t)0x7BU)\r\n#define RCC_FLAG_SFTRST                  ((uint8_t)0x7CU)\r\n#define RCC_FLAG_IWDGRST                 ((uint8_t)0x7DU)\r\n#define RCC_FLAG_WWDGRST                 ((uint8_t)0x7EU)\r\n#define RCC_FLAG_LPWRRST                 ((uint8_t)0x7FU)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup RCC_LSEDrive_Configuration RCC LSE Drive configurations\r\n  * @{\r\n  */\r\n#define RCC_LSEDRIVE_LOW                 ((uint32_t)0x00000000U)\r\n#define RCC_LSEDRIVE_MEDIUMLOW           RCC_BDCR_LSEDRV_1\r\n#define RCC_LSEDRIVE_MEDIUMHIGH          RCC_BDCR_LSEDRV_0\r\n#define RCC_LSEDRIVE_HIGH                RCC_BDCR_LSEDRV\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */\r\n   \r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup RCC_Exported_Macros RCC Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable\r\n  * @brief  Enable or disable the AHB1 peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before \r\n  *         using it.   \r\n  * @{\r\n  */\r\n#define __HAL_RCC_CRC_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\t\t\t\t\t\t\t\t\t  \r\n#define __HAL_RCC_DMA1_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_CRC_CLK_DISABLE()          (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))\r\n#define __HAL_RCC_DMA1_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable\r\n  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before\r\n  *         using it.\r\n  * @{\r\n  */\r\n#define __HAL_RCC_WWDG_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\t\t\t\t\t\t\t\t\t  \r\n#define __HAL_RCC_PWR_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\t\t\t\t\t\t\t\t\t  \r\n\r\n#define __HAL_RCC_WWDG_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))\r\n#define __HAL_RCC_PWR_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable                                      \r\n  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before \r\n  *         using it.\r\n  * @{\r\n  */\r\n#define __HAL_RCC_SYSCFG_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\t\t\t\t\t\t\t\t\t  \r\n#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status\r\n  * @brief  Get the enable or disable status of the AHB1 peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before\r\n  *         using it.\r\n  * @{\r\n  */\r\n#define __HAL_RCC_CRC_IS_CLK_ENABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)  \r\n#define __HAL_RCC_DMA1_IS_CLK_ENABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) != RESET)\r\n\r\n#define __HAL_RCC_CRC_IS_CLK_DISABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)\r\n#define __HAL_RCC_DMA1_IS_CLK_DISABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) == RESET)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable  Status\r\n  * @brief  Get the enable or disable status of the APB1 peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before\r\n  *         using it.\r\n  * @{\r\n  */\r\n#define __HAL_RCC_WWDG_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)\r\n#define __HAL_RCC_PWR_IS_CLK_ENABLED()         ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)\r\n\r\n#define __HAL_RCC_WWDG_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)\r\n#define __HAL_RCC_PWR_IS_CLK_DISABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status\r\n  * @brief  EGet the enable or disable status of the APB2 peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before\r\n  *         using it.\r\n  * @{\r\n  */\r\n#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)\r\n#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)\r\n/**\r\n  * @}\r\n  */  \r\n  \r\n/** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release\r\n  * @brief  Force or release AHB peripheral reset.\r\n  * @{\r\n  */  \r\n#define __HAL_RCC_AHB1_FORCE_RESET()    (RCC->AHB1RSTR = 0xFFFFFFFFU)\r\n#define __HAL_RCC_CRC_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))\r\n#define __HAL_RCC_DMA1_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))\r\n\r\n#define __HAL_RCC_AHB1_RELEASE_RESET()  (RCC->AHB1RSTR = 0x00U)\r\n#define __HAL_RCC_CRC_RELEASE_RESET()   (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))\r\n#define __HAL_RCC_DMA1_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset \r\n  * @brief  Force or release APB1 peripheral reset.\r\n  * @{\r\n  */\r\n#define __HAL_RCC_APB1_FORCE_RESET()     (RCC->APB1RSTR = 0xFFFFFFFFU)  \r\n#define __HAL_RCC_WWDG_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))\r\n#define __HAL_RCC_PWR_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))\r\n\r\n#define __HAL_RCC_APB1_RELEASE_RESET()   (RCC->APB1RSTR = 0x00U) \r\n#define __HAL_RCC_WWDG_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))\r\n#define __HAL_RCC_PWR_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset \r\n  * @brief  Force or release APB2 peripheral reset.\r\n  * @{\r\n  */\r\n#define __HAL_RCC_APB2_FORCE_RESET()     (RCC->APB2RSTR = 0xFFFFFFFFU)  \r\n#define __HAL_RCC_SYSCFG_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))\r\n\r\n#define __HAL_RCC_APB2_RELEASE_RESET()   (RCC->APB2RSTR = 0x00U)\r\n#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable\r\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r\n  *         power consumption.\r\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r\n  * @{\r\n  */\r\n#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))\r\n#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))\r\n\r\n#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))\r\n#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))\r\n\r\n/** @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.\r\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r\n  *         power consumption.\r\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r\n  */\r\n#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))\r\n#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))\r\n\r\n#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))\r\n#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))\r\n\r\n/** @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.\r\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r\n  *         power consumption.\r\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r\n  */\r\n#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))\r\n#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enable Disable Status\r\n  * @brief  Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.\r\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r\n  *         power consumption.\r\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r\n  * @{\r\n  */\r\n#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != RESET)\r\n#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != RESET)\r\n\r\n#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == RESET)\r\n#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED()   ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == RESET)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status\r\n  * @brief  Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.\r\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r\n  *         power consumption.\r\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r\n  * @{\r\n  */\r\n#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED()      ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET)\r\n#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET)\r\n\r\n#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED()     ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET)\r\n#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED()      ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status\r\n  * @brief  Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.\r\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r\n  *         power consumption.\r\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r\n  * @{\r\n  */\r\n#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET)\r\n#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET)\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup RCC_HSI_Configuration HSI Configuration\r\n  * @{   \r\n  */ \r\n                                      \r\n/** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).\r\n  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.\r\n  *         It is used (enabled by hardware) as system clock source after startup\r\n  *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure\r\n  *         of the HSE used directly or indirectly as system clock (if the Clock\r\n  *         Security System CSS is enabled).             \r\n  * @note   HSI can not be stopped if it is used as system clock source. In this case,\r\n  *         you have to select another source of the system clock then stop the HSI.  \r\n  * @note   After enabling the HSI, the application software should wait on HSIRDY\r\n  *         flag to be set indicating that HSI clock is stable and can be used as\r\n  *         system clock source.  \r\n  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator\r\n  *         clock cycles.  \r\n  */\r\n#define __HAL_RCC_HSI_ENABLE() (RCC->CR |= (RCC_CR_HSION))\r\n#define __HAL_RCC_HSI_DISABLE() (RCC->CR &= ~(RCC_CR_HSION))\r\n\r\n/** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.\r\n  * @note   The calibration is used to compensate for the variations in voltage\r\n  *         and temperature that influence the frequency of the internal HSI RC.\r\n  * @param  __HSICALIBRATIONVALUE__ specifies the calibration trimming value.\r\n  *         (default is RCC_HSICALIBRATION_DEFAULT).\r\n  */\r\n#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) (MODIFY_REG(RCC->CR,\\\r\n        RCC_CR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_CR_HSITRIM_Pos))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_LSI_Configuration LSI Configuration\r\n  * @{   \r\n  */ \r\n\r\n/** @brief  Macros to enable or disable the Internal Low Speed oscillator (LSI).\r\n  * @note   After enabling the LSI, the application software should wait on \r\n  *         LSIRDY flag to be set indicating that LSI clock is stable and can\r\n  *         be used to clock the IWDG and/or the RTC.\r\n  * @note   LSI can not be disabled if the IWDG is running.\r\n  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator\r\n  *         clock cycles. \r\n  */\r\n#define __HAL_RCC_LSI_ENABLE()  (RCC->CSR |= (RCC_CSR_LSION))\r\n#define __HAL_RCC_LSI_DISABLE() (RCC->CSR &= ~(RCC_CSR_LSION))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_HSE_Configuration HSE Configuration\r\n  * @{   \r\n  */ \r\n/**\r\n  * @brief  Macro to configure the External High Speed oscillator (HSE).\r\n  * @note   Transitions HSE Bypass to HSE On and HSE On to HSE Bypass are not\r\n  *         supported by this macro. User should request a transition to HSE Off\r\n  *         first and then HSE On or HSE Bypass.\r\n  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application\r\n  *         software should wait on HSERDY flag to be set indicating that HSE clock\r\n  *         is stable and can be used to clock the PLL and/or system clock.\r\n  * @note   HSE state can not be changed if it is used directly or through the\r\n  *         PLL as system clock. In this case, you have to select another source\r\n  *         of the system clock then change the HSE state (ex. disable it).\r\n  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.\r\n  * @note   This function reset the CSSON bit, so if the clock security system(CSS)\r\n  *         was previously enabled you have to enable it again after calling this\r\n  *         function.\r\n  * @param  __STATE__ specifies the new state of the HSE.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after\r\n  *                              6 HSE oscillator clock cycles.\r\n  *            @arg RCC_HSE_ON: turn ON the HSE oscillator.\r\n  *            @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.\r\n  */\r\n#define __HAL_RCC_HSE_CONFIG(__STATE__)                         \\\r\n                    do {                                        \\\r\n                      if ((__STATE__) == RCC_HSE_ON)            \\\r\n                      {                                         \\\r\n                        SET_BIT(RCC->CR, RCC_CR_HSEON);         \\\r\n                      }                                         \\\r\n                      else if ((__STATE__) == RCC_HSE_OFF)      \\\r\n                      {                                         \\\r\n                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);       \\\r\n                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);      \\\r\n                      }                                         \\\r\n                      else if ((__STATE__) == RCC_HSE_BYPASS)   \\\r\n                      {                                         \\\r\n                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);        \\\r\n                        SET_BIT(RCC->CR, RCC_CR_HSEON);         \\\r\n                      }                                         \\\r\n                      else                                      \\\r\n                      {                                         \\\r\n                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);       \\\r\n                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);      \\\r\n                      }                                         \\\r\n                    } while(0)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_LSE_Configuration LSE Configuration\r\n  * @{   \r\n  */\r\n\r\n/**\r\n  * @brief  Macro to configure the External Low Speed oscillator (LSE).\r\n  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. \r\n  *         User should request a transition to LSE Off first and then LSE On or LSE Bypass.  \r\n  * @note   As the LSE is in the Backup domain and write access is denied to\r\n  *         this domain after reset, you have to enable write access using \r\n  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE\r\n  *         (to be done once after reset).  \r\n  * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application\r\n  *         software should wait on LSERDY flag to be set indicating that LSE clock\r\n  *         is stable and can be used to clock the RTC.\r\n  * @param  __STATE__ specifies the new state of the LSE.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after\r\n  *                              6 LSE oscillator clock cycles.\r\n  *            @arg RCC_LSE_ON: turn ON the LSE oscillator.\r\n  *            @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.\r\n  */\r\n#define __HAL_RCC_LSE_CONFIG(__STATE__) \\\r\n                    do {                                       \\\r\n                      if((__STATE__) == RCC_LSE_ON)            \\\r\n                      {                                        \\\r\n                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \\\r\n                      }                                        \\\r\n                      else if((__STATE__) == RCC_LSE_OFF)      \\\r\n                      {                                        \\\r\n                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \\\r\n                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \\\r\n                      }                                        \\\r\n                      else if((__STATE__) == RCC_LSE_BYPASS)   \\\r\n                      {                                        \\\r\n                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);   \\\r\n                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \\\r\n                      }                                        \\\r\n                      else                                     \\\r\n                      {                                        \\\r\n                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \\\r\n                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \\\r\n                      }                                        \\\r\n                    } while(0)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration\r\n  * @{   \r\n  */\r\n\r\n/** @brief  Macros to enable or disable the RTC clock.\r\n  * @note   These macros must be used only after the RTC clock source was selected.\r\n  */\r\n#define __HAL_RCC_RTC_ENABLE()  (RCC->BDCR |= (RCC_BDCR_RTCEN))\r\n#define __HAL_RCC_RTC_DISABLE() (RCC->BDCR &= ~(RCC_BDCR_RTCEN))\r\n\r\n/** @brief  Macros to configure the RTC clock (RTCCLK).\r\n  * @note   As the RTC clock configuration bits are in the Backup domain and write\r\n  *         access is denied to this domain after reset, you have to enable write\r\n  *         access using the Power Backup Access macro before to configure\r\n  *         the RTC clock source (to be done once after reset).    \r\n  * @note   Once the RTC clock is configured it can't be changed unless the  \r\n  *         Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by\r\n  *         a Power On Reset (POR).\r\n  * @param  __RTCCLKSource__ specifies the RTC clock source.\r\n  *         This parameter can be one of the following values:\r\n               @arg @ref RCC_RTCCLKSOURCE_NO_CLK:  No clock selected as RTC clock.\r\n  *            @arg @ref RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.\r\n  *            @arg @ref RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.\r\n  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected\r\n  *                                                 as RTC clock, where x:[2,31]\r\n  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to\r\n  *         work in STOP and STANDBY modes, and can be used as wakeup source.\r\n  *         However, when the HSE clock is used as RTC clock source, the RTC\r\n  *         cannot be used in STOP and STANDBY modes.    \r\n  * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as\r\n  *         RTC clock source).\r\n  */\r\n#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ?    \\\r\n                                                     MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)\r\n                                                   \r\n#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__);    \\\r\n                                                    RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF);  \\\r\n                                                  } while (0)\r\n\r\n/** @brief Macro to get the RTC clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock\r\n  *            @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock\r\n  *            @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock\r\n  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()\r\n  */\r\n#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))\r\n\r\n/**\r\n  * @brief   Get the RTC and HSE clock divider (RTCPRE).\r\n  * @retval Returned value can be one of the following values:\r\n  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected\r\n  *                                                 as RTC clock, where x:[2,31]\r\n  */\r\n#define  __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL)\r\n\r\n/** @brief  Macros to force or release the Backup domain reset.\r\n  * @note   This function resets the RTC peripheral (including the backup registers)\r\n  *         and the RTC clock source selection in RCC_CSR register.\r\n  * @note   The BKPSRAM is not affected by this reset.   \r\n  */\r\n#define __HAL_RCC_BACKUPRESET_FORCE()   (RCC->BDCR |= (RCC_BDCR_BDRST))\r\n#define __HAL_RCC_BACKUPRESET_RELEASE() (RCC->BDCR &= ~(RCC_BDCR_BDRST))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_PLL_Configuration PLL Configuration\r\n  * @{   \r\n  */\r\n\r\n/** @brief  Macros to enable or disable the main PLL.\r\n  * @note   After enabling the main PLL, the application software should wait on \r\n  *         PLLRDY flag to be set indicating that PLL clock is stable and can\r\n  *         be used as system clock source.\r\n  * @note   The main PLL can not be disabled if it is used as system clock source\r\n  * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.\r\n  */\r\n#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)\r\n#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)\r\n                            \r\n/** @brief  Macro to configure the PLL clock source.\r\n  * @note   This function must be used only when the main PLL is disabled.\r\n  * @param  __PLLSOURCE__ specifies the PLL entry clock source.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry\r\n  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry\r\n  *      \r\n  */\r\n#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))\r\n\r\n/** @brief  Macro to configure the PLL multiplication factor.\r\n  * @note   This function must be used only when the main PLL is disabled.\r\n  * @param  __PLLM__ specifies the division factor for PLL VCO input clock\r\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.\r\n  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input\r\n  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency\r\n  *         of 2 MHz to limit PLL jitter.\r\n  *      \r\n  */\r\n#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration\r\n  * @{   \r\n  */\r\n\r\n/** @brief  Macro to configure the I2S clock source (I2SCLK).\r\n  * @note   This function must be called before enabling the I2S APB clock.\r\n  * @param  __SOURCE__ specifies the I2S clock source.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.\r\n  *            @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin\r\n  *                                       used as I2S clock source.\r\n  */\r\n#define __HAL_RCC_I2S_CONFIG(__SOURCE__) do {RCC->CFGR &= ~(RCC_CFGR_I2SSRC); \\\r\n                                             RCC->CFGR |= (__SOURCE__);       \\\r\n                                            }while(0)\r\n\r\n/** @brief Macros to enable or disable the PLLI2S. \r\n  * @note  The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.\r\n  */\r\n#define __HAL_RCC_PLLI2S_ENABLE() (RCC->CR |= (RCC_CR_PLLI2SON))\r\n#define __HAL_RCC_PLLI2S_DISABLE() (RCC->CR &= ~(RCC_CR_PLLI2SON))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_Get_Clock_source Get Clock source\r\n  * @{   \r\n  */\r\n/**\r\n  * @brief Macro to configure the system clock source.\r\n  * @param __RCC_SYSCLKSOURCE__ specifies the system clock source.\r\n  * This parameter can be one of the following values:\r\n  *              - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.\r\n  *              - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.\r\n  *              - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.\r\n  */\r\n#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))\r\n\r\n/** @brief  Macro to get the clock source used as system clock.\r\n  * @retval The clock source used as system clock. The returned value can be one\r\n  *         of the following:\r\n  *              - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.\r\n  *              - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.\r\n  *              - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.\r\n  */\r\n#define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS)\r\n\r\n/**\r\n  * @brief  Macro to configures the External Low Speed oscillator (LSE) drive capability.\r\n  * @note   As the LSE is in the Backup domain and write access is denied to\r\n  *         this domain after reset, you have to enable write access using\r\n  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE\r\n  *         (to be done once after reset).\r\n  * @param  __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.\r\n  *            @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.\r\n  *            @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.\r\n  *            @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.\r\n  * @retval None\r\n  */\r\n#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) \\\r\n                  (MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))\r\n\r\n/** @brief  Macro to get the oscillator used as PLL clock source.\r\n  * @retval The oscillator used as PLL clock source. The returned value can be one\r\n  *         of the following:\r\n  *              - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.\r\n  *              - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.\r\n  */\r\n#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config\r\n  * @{   \r\n  */ \r\n  \r\n/** @brief  Macro to configure the MCO1 clock.\r\n  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source\r\n  *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source\r\n  *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source\r\n  *            @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source\r\n  * @param  __MCODIV__ specifies the MCO clock prescaler.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_MCODIV_1: no division applied to MCOx clock\r\n  *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock\r\n  *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock\r\n  *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock\r\n  *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock\r\n  */\r\n\r\n#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \\\r\n        MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))\r\n                \r\n/** @brief  Macro to configure the MCO2 clock.\r\n  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source\r\n  *            @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source \r\n  *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source\r\n  *            @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source\r\n  * @param  __MCODIV__ specifies the MCO clock prescaler.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_MCODIV_1: no division applied to MCOx clock\r\n  *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock\r\n  *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock\r\n  *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock\r\n  *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock\r\n  */\r\n\r\n#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \\\r\n        MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3)));\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management\r\n  * @brief macros to manage the specified RCC Flags and interrupts.\r\n  * @{\r\n  */\r\n\r\n/** @brief  Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable\r\n  *         the selected interrupts).\r\n  * @param  __INTERRUPT__ specifies the RCC interrupt sources to be enabled.\r\n  *         This parameter can be any combination of the following values:\r\n  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.\r\n  *            @arg RCC_IT_LSERDY: LSE ready interrupt.\r\n  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.\r\n  *            @arg RCC_IT_HSERDY: HSE ready interrupt.\r\n  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.\r\n  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.\r\n  */\r\n#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))\r\n\r\n/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable \r\n  *        the selected interrupts).\r\n  * @param  __INTERRUPT__ specifies the RCC interrupt sources to be disabled.\r\n  *         This parameter can be any combination of the following values:\r\n  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.\r\n  *            @arg RCC_IT_LSERDY: LSE ready interrupt.\r\n  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.\r\n  *            @arg RCC_IT_HSERDY: HSE ready interrupt.\r\n  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.\r\n  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.\r\n  */\r\n#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))\r\n\r\n/** @brief  Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]\r\n  *         bits to clear the selected interrupt pending bits.\r\n  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.\r\n  *         This parameter can be any combination of the following values:\r\n  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.\r\n  *            @arg RCC_IT_LSERDY: LSE ready interrupt.\r\n  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.\r\n  *            @arg RCC_IT_HSERDY: HSE ready interrupt.\r\n  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.\r\n  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.  \r\n  *            @arg RCC_IT_CSS: Clock Security System interrupt\r\n  */\r\n#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))\r\n\r\n/** @brief  Check the RCC's interrupt has occurred or not.\r\n  * @param  __INTERRUPT__ specifies the RCC interrupt source to check.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.\r\n  *            @arg RCC_IT_LSERDY: LSE ready interrupt.\r\n  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.\r\n  *            @arg RCC_IT_HSERDY: HSE ready interrupt.\r\n  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.\r\n  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.\r\n  *            @arg RCC_IT_CSS: Clock Security System interrupt\r\n  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))\r\n\r\n/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, \r\n  *        RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.\r\n  */\r\n#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)\r\n\r\n/** @brief  Check RCC flag is set or not.\r\n  * @param  __FLAG__ specifies the flag to check.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.\r\n  *            @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.\r\n  *            @arg RCC_FLAG_PLLRDY: Main PLL clock ready.\r\n  *            @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.\r\n  *            @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.\r\n  *            @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.\r\n  *            @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.\r\n  *            @arg RCC_FLAG_PINRST: Pin reset.\r\n  *            @arg RCC_FLAG_PORRST: POR/PDR reset.\r\n  *            @arg RCC_FLAG_SFTRST: Software reset.\r\n  *            @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.\r\n  *            @arg RCC_FLAG_WWDGRST: Window Watchdog reset.\r\n  *            @arg RCC_FLAG_LPWRRST: Low Power reset.\r\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\r\n  */\r\n#define RCC_FLAG_MASK  ((uint8_t)0x1F)\r\n#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)\r\n\r\n/**\r\n  * @}\r\n  */\r\n     \r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Include RCC HAL Extension module */\r\n#include \"stm32f7xx_hal_rcc_ex.h\"\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n /** @addtogroup RCC_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup RCC_Exported_Functions_Group1\r\n  * @{\r\n  */                             \r\n/* Initialization and de-initialization functions  ******************************/\r\nHAL_StatusTypeDef HAL_RCC_DeInit(void);\r\nHAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);\r\nHAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup RCC_Exported_Functions_Group2\r\n  * @{\r\n  */\r\n/* Peripheral Control functions  ************************************************/\r\nvoid     HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);\r\nvoid     HAL_RCC_EnableCSS(void);\r\nvoid     HAL_RCC_DisableCSS(void);\r\nuint32_t HAL_RCC_GetSysClockFreq(void);\r\nuint32_t HAL_RCC_GetHCLKFreq(void);\r\nuint32_t HAL_RCC_GetPCLK1Freq(void);\r\nuint32_t HAL_RCC_GetPCLK2Freq(void);\r\nvoid     HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);\r\nvoid     HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);\r\n\r\n/* CSS NMI IRQ handler */\r\nvoid HAL_RCC_NMI_IRQHandler(void);\r\n\r\n/* User Callbacks in non blocking mode (IT mode) */ \r\nvoid HAL_RCC_CSSCallback(void);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup RCC_Private_Constants RCC Private Constants\r\n  * @{\r\n  */\r\n#define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT\r\n#define HSI_TIMEOUT_VALUE          ((uint32_t)2)    /* 2 ms */\r\n#define LSI_TIMEOUT_VALUE          ((uint32_t)2)    /* 2 ms */\r\n#define PLL_TIMEOUT_VALUE          ((uint32_t)2)    /* 2 ms */\r\n#define CLOCKSWITCH_TIMEOUT_VALUE  ((uint32_t)5000) /* 5 s */\r\n#define PLLI2S_TIMEOUT_VALUE       100U             /* Timeout value fixed to 100 ms */\r\n#define PLLSAI_TIMEOUT_VALUE       100U             /* Timeout value fixed to 100 ms */\r\n\r\n/** @defgroup RCC_BitAddress_Alias RCC BitAddress Alias\r\n  * @brief RCC registers bit address alias\r\n  * @{\r\n  */\r\n/* CIR register byte 2 (Bits[15:8]) base address */\r\n#define RCC_CIR_BYTE1_ADDRESS         ((uint32_t)(RCC_BASE + 0x0C + 0x01))\r\n\r\n/* CIR register byte 3 (Bits[23:16]) base address */\r\n#define RCC_CIR_BYTE2_ADDRESS         ((uint32_t)(RCC_BASE + 0x0C + 0x02))\r\n\r\n#define RCC_DBP_TIMEOUT_VALUE      ((uint32_t)100)\r\n#define RCC_LSE_TIMEOUT_VALUE      LSE_STARTUP_TIMEOUT\r\n/**\r\n  * @}\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @addtogroup RCC_Private_Macros RCC Private Macros\r\n  * @{\r\n  */\r\n    \r\n/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters\r\n  * @{\r\n  */  \r\n#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)\r\n\r\n#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \\\r\n                         ((HSE) == RCC_HSE_BYPASS))\r\n\r\n#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \\\r\n                         ((LSE) == RCC_LSE_BYPASS))\r\n\r\n#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))\r\n\r\n#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))\r\n\r\n#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))\r\n\r\n#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \\\r\n                                  ((SOURCE) == RCC_PLLSOURCE_HSE))\r\n\r\n#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \\\r\n                                     ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \\\r\n                                     ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))\r\n#define IS_RCC_PLLM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63))\r\n\r\n#define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))\r\n\r\n#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == RCC_PLLP_DIV2) || ((VALUE) == RCC_PLLP_DIV4) || \\\r\n                                  ((VALUE) == RCC_PLLP_DIV6) || ((VALUE) == RCC_PLLP_DIV8))\r\n#define IS_RCC_PLLQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))\r\n\r\n#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1)   || ((HCLK) == RCC_SYSCLK_DIV2)   || \\\r\n                           ((HCLK) == RCC_SYSCLK_DIV4)   || ((HCLK) == RCC_SYSCLK_DIV8)   || \\\r\n                           ((HCLK) == RCC_SYSCLK_DIV16)  || ((HCLK) == RCC_SYSCLK_DIV64)  || \\\r\n                           ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \\\r\n                           ((HCLK) == RCC_SYSCLK_DIV512))\r\n\r\n#define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))\r\n\r\n#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \\\r\n                           ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \\\r\n                           ((PCLK) == RCC_HCLK_DIV16))\r\n\r\n#define IS_RCC_MCO(MCOX) (((MCOX) == RCC_MCO1) || ((MCOX) == RCC_MCO2))\r\n\r\n\r\n#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \\\r\n                                   ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))\r\n\r\n#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \\\r\n                                   ((SOURCE) == RCC_MCO2SOURCE_HSE)    || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))\r\n\r\n#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1)  || ((DIV) == RCC_MCODIV_2) || \\\r\n                             ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \\\r\n                             ((DIV) == RCC_MCODIV_5)) \r\n#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)\r\n\r\n#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \\\r\n                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \\\r\n                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \\\r\n                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \\\r\n                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \\\r\n                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \\\r\n                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \\\r\n                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \\\r\n                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \\\r\n                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \\\r\n                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \\\r\n                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \\\r\n                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \\\r\n                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \\\r\n                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \\\r\n                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31))\r\n\r\n\r\n#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDRIVE_LOW)        || \\\r\n                                 ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW)  || \\\r\n                                 ((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) || \\\r\n                                 ((DRIVE) == RCC_LSEDRIVE_HIGH))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_RCC_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_rcc_ex.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of RCC HAL Extension module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_RCC_EX_H\r\n#define __STM32F7xx_HAL_RCC_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup RCCEx\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup RCCEx_Exported_Types RCCEx Exported Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  RCC PLL configuration structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t PLLState;   /*!< The new state of the PLL.\r\n                            This parameter can be a value of @ref RCC_PLL_Config                      */\r\n\r\n  uint32_t PLLSource;  /*!< RCC_PLLSource: PLL entry clock source.\r\n                            This parameter must be a value of @ref RCC_PLL_Clock_Source               */\r\n\r\n  uint32_t PLLM;       /*!< PLLM: Division factor for PLL VCO input clock.\r\n                            This parameter must be a number between Min_Data = 2 and Max_Data = 63    */\r\n\r\n  uint32_t PLLN;       /*!< PLLN: Multiplication factor for PLL VCO output clock.\r\n                            This parameter must be a number between Min_Data = 50 and Max_Data = 432  */\r\n\r\n  uint32_t PLLP;       /*!< PLLP: Division factor for main system clock (SYSCLK).\r\n                            This parameter must be a value of @ref RCC_PLLP_Clock_Divider             */\r\n\r\n  uint32_t PLLQ;       /*!< PLLQ: Division factor for OTG FS, SDMMC and RNG clocks.\r\n                            This parameter must be a number between Min_Data = 2 and Max_Data = 15    */\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n  uint32_t PLLR;       /*!< PLLR: Division factor for DSI clock.\r\n                            This parameter must be a number between Min_Data = 2 and Max_Data = 7    */\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n}RCC_PLLInitTypeDef;\r\n\r\n/**\r\n  * @brief  PLLI2S Clock structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t PLLI2SN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.\r\n                            This parameter must be a number between Min_Data = 50 and Max_Data = 432.\r\n                            This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */\r\n\r\n  uint32_t PLLI2SR;    /*!< Specifies the division factor for I2S clock.\r\n                            This parameter must be a number between Min_Data = 2 and Max_Data = 7.\r\n                            This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */\r\n\r\n  uint32_t PLLI2SQ;    /*!< Specifies the division factor for SAI1 clock.\r\n                            This parameter must be a number between Min_Data = 2 and Max_Data = 15.\r\n                            This parameter will be used only when PLLI2S is selected as Clock Source SAI */\r\n\r\n#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \\\r\n    defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r\n  uint32_t PLLI2SP;    /*!< Specifies the division factor for SPDIF-RX clock.\r\n                            This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider.\r\n                            This parameter will be used only when PLLI2S is selected as Clock Source SPDIF-RX */\r\n#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n}RCC_PLLI2SInitTypeDef;\r\n\r\n/**\r\n  * @brief  PLLSAI Clock structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t PLLSAIN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.\r\n                            This parameter must be a number between Min_Data = 50 and Max_Data = 432.\r\n                            This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */\r\n\r\n  uint32_t PLLSAIQ;    /*!< Specifies the division factor for SAI1 clock.\r\n                            This parameter must be a number between Min_Data = 2 and Max_Data = 15.\r\n                            This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */\r\n\r\n#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \\\r\n    defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r\n  uint32_t PLLSAIR;    /*!< specifies the division factor for LTDC clock\r\n                            This parameter must be a number between Min_Data = 2 and Max_Data = 7.\r\n                            This parameter will be used only when PLLSAI is selected as Clock Source LTDC */\r\n#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n\r\n  uint32_t PLLSAIP;    /*!< Specifies the division factor for 48MHz clock.\r\n                            This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider\r\n                            This parameter will be used only when PLLSAI is disabled */\r\n}RCC_PLLSAIInitTypeDef;\r\n\r\n/**\r\n  * @brief  RCC extended clocks structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.\r\n                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */\r\n\r\n  RCC_PLLI2SInitTypeDef PLLI2S;  /*!< PLL I2S structure parameters.\r\n                                      This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */\r\n\r\n  RCC_PLLSAIInitTypeDef PLLSAI;  /*!< PLL SAI structure parameters.\r\n                                      This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */\r\n\r\n  uint32_t PLLI2SDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.\r\n                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32\r\n                                      This parameter will be used only when PLLI2S is selected as Clock Source SAI */\r\n\r\n  uint32_t PLLSAIDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.\r\n                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32\r\n                                      This parameter will be used only when PLLSAI is selected as Clock Source SAI */\r\n\r\n  uint32_t PLLSAIDivR;           /*!< Specifies the PLLSAI division factor for LTDC clock.\r\n                                      This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */\r\n\r\n  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock source Selection.\r\n                                        This parameter can be a value of @ref RCC_RTC_Clock_Source */\r\n\r\n  uint32_t I2sClockSelection;      /*!< Specifies I2S Clock source Selection.\r\n                                        This parameter can be a value of @ref RCCEx_I2S_Clock_Source */\r\n\r\n  uint32_t TIMPresSelection;      /*!< Specifies TIM Clock Prescalers Selection.\r\n                                       This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */\r\n\r\n  uint32_t Sai1ClockSelection;     /*!< Specifies SAI1 Clock Prescalers Selection\r\n                                        This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */\r\n\r\n  uint32_t Sai2ClockSelection;     /*!< Specifies SAI2 Clock Prescalers Selection\r\n                                        This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */\r\n\r\n  uint32_t Usart1ClockSelection; /*!< USART1 clock source\r\n                                      This parameter can be a value of @ref RCCEx_USART1_Clock_Source */\r\n\r\n  uint32_t Usart2ClockSelection; /*!< USART2 clock source\r\n                                      This parameter can be a value of @ref RCCEx_USART2_Clock_Source */\r\n\r\n  uint32_t Usart3ClockSelection; /*!< USART3 clock source\r\n                                      This parameter can be a value of @ref RCCEx_USART3_Clock_Source */\r\n\r\n  uint32_t Uart4ClockSelection;  /*!< UART4 clock source\r\n                                      This parameter can be a value of @ref RCCEx_UART4_Clock_Source */\r\n\r\n  uint32_t Uart5ClockSelection;  /*!< UART5 clock source\r\n                                      This parameter can be a value of @ref RCCEx_UART5_Clock_Source */\r\n\r\n  uint32_t Usart6ClockSelection;  /*!< USART6 clock source\r\n                                      This parameter can be a value of @ref RCCEx_USART6_Clock_Source */\r\n\r\n  uint32_t Uart7ClockSelection;  /*!< UART7 clock source\r\n                                      This parameter can be a value of @ref RCCEx_UART7_Clock_Source */\r\n\r\n  uint32_t Uart8ClockSelection;  /*!< UART8 clock source\r\n                                      This parameter can be a value of @ref RCCEx_UART8_Clock_Source */\r\n\r\n  uint32_t I2c1ClockSelection;   /*!< I2C1 clock source\r\n                                      This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */\r\n\r\n  uint32_t I2c2ClockSelection;   /*!< I2C2 clock source\r\n                                      This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */\r\n\r\n  uint32_t I2c3ClockSelection;   /*!< I2C3 clock source\r\n                                      This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */\r\n\r\n  uint32_t I2c4ClockSelection;   /*!< I2C4 clock source\r\n                                      This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */\r\n\r\n  uint32_t Lptim1ClockSelection;   /*!< Specifies LPTIM1 clock source\r\n                                        This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */\r\n\r\n  uint32_t CecClockSelection;      /*!< CEC clock source\r\n                                        This parameter can be a value of @ref RCCEx_CEC_Clock_Source */\r\n\r\n  uint32_t Clk48ClockSelection;    /*!< Specifies 48Mhz clock source used by USB OTG FS, RNG and SDMMC\r\n                                        This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */\r\n\r\n  uint32_t Sdmmc1ClockSelection;     /*!< SDMMC1 clock source\r\n                                        This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */\r\n\r\n#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)\r\n  uint32_t Sdmmc2ClockSelection;     /*!< SDMMC2 clock source\r\n                                        This parameter can be a value of @ref RCCEx_SDMMC2_Clock_Source */\r\n#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r\n\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n  uint32_t Dfsdm1ClockSelection;     /*!< DFSDM1 clock source\r\n                                        This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */\r\n\r\n  uint32_t Dfsdm1AudioClockSelection; /*!< DFSDM1 clock source\r\n                                        This parameter can be a value of @ref RCCEx_DFSDM1_AUDIO_Clock_Source */\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n}RCC_PeriphCLKInitTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection\r\n  * @{\r\n  */\r\n#define RCC_PERIPHCLK_I2S             ((uint32_t)0x00000001U)\r\n#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r\n#define RCC_PERIPHCLK_LTDC            ((uint32_t)0x00000008U)\r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n#define RCC_PERIPHCLK_TIM             ((uint32_t)0x00000010U)\r\n#define RCC_PERIPHCLK_RTC             ((uint32_t)0x00000020U)\r\n#define RCC_PERIPHCLK_USART1          ((uint32_t)0x00000040U)\r\n#define RCC_PERIPHCLK_USART2          ((uint32_t)0x00000080U)\r\n#define RCC_PERIPHCLK_USART3          ((uint32_t)0x00000100U)\r\n#define RCC_PERIPHCLK_UART4           ((uint32_t)0x00000200U)\r\n#define RCC_PERIPHCLK_UART5           ((uint32_t)0x00000400U)\r\n#define RCC_PERIPHCLK_USART6          ((uint32_t)0x00000800U)\r\n#define RCC_PERIPHCLK_UART7           ((uint32_t)0x00001000U)\r\n#define RCC_PERIPHCLK_UART8           ((uint32_t)0x00002000U)\r\n#define RCC_PERIPHCLK_I2C1            ((uint32_t)0x00004000U)\r\n#define RCC_PERIPHCLK_I2C2            ((uint32_t)0x00008000U)\r\n#define RCC_PERIPHCLK_I2C3            ((uint32_t)0x00010000U)\r\n#define RCC_PERIPHCLK_I2C4            ((uint32_t)0x00020000U)\r\n#define RCC_PERIPHCLK_LPTIM1          ((uint32_t)0x00040000U)\r\n#define RCC_PERIPHCLK_SAI1            ((uint32_t)0x00080000U)\r\n#define RCC_PERIPHCLK_SAI2            ((uint32_t)0x00100000U)\r\n#define RCC_PERIPHCLK_CLK48           ((uint32_t)0x00200000U)\r\n#define RCC_PERIPHCLK_CEC             ((uint32_t)0x00400000U)\r\n#define RCC_PERIPHCLK_SDMMC1          ((uint32_t)0x00800000U)\r\n#define RCC_PERIPHCLK_SPDIFRX         ((uint32_t)0x01000000U)\r\n#define RCC_PERIPHCLK_PLLI2S          ((uint32_t)0x02000000U)\r\n#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)\r\n#define RCC_PERIPHCLK_SDMMC2          ((uint32_t)0x04000000U)\r\n#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define RCC_PERIPHCLK_DFSDM1           ((uint32_t)0x08000000U)\r\n#define RCC_PERIPHCLK_DFSDM1_AUDIO     ((uint32_t)0x10000000U)\r\n#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \\\r\n    defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r\n/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCCEx PLLI2SP Clock Divider\r\n  * @{\r\n  */\r\n#define RCC_PLLI2SP_DIV2                  ((uint32_t)0x00000000U)\r\n#define RCC_PLLI2SP_DIV4                  ((uint32_t)0x00000001U)\r\n#define RCC_PLLI2SP_DIV6                  ((uint32_t)0x00000002U)\r\n#define RCC_PLLI2SP_DIV8                  ((uint32_t)0x00000003U)\r\n/**\r\n  * @}\r\n  */\r\n#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n\r\n/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider\r\n  * @{\r\n  */\r\n#define RCC_PLLSAIP_DIV2                  ((uint32_t)0x00000000U)\r\n#define RCC_PLLSAIP_DIV4                  ((uint32_t)0x00000001U)\r\n#define RCC_PLLSAIP_DIV6                  ((uint32_t)0x00000002U)\r\n#define RCC_PLLSAIP_DIV8                  ((uint32_t)0x00000003U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_PLLSAI_DIVR RCCEx PLLSAI DIVR\r\n  * @{\r\n  */\r\n#define RCC_PLLSAIDIVR_2                ((uint32_t)0x00000000U)\r\n#define RCC_PLLSAIDIVR_4                RCC_DCKCFGR1_PLLSAIDIVR_0\r\n#define RCC_PLLSAIDIVR_8                RCC_DCKCFGR1_PLLSAIDIVR_1\r\n#define RCC_PLLSAIDIVR_16               RCC_DCKCFGR1_PLLSAIDIVR\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_I2S_Clock_Source RCCEx I2S Clock Source\r\n  * @{\r\n  */\r\n#define RCC_I2SCLKSOURCE_PLLI2S             ((uint32_t)0x00000000U)\r\n#define RCC_I2SCLKSOURCE_EXT                RCC_CFGR_I2SSRC\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_SAI1CLKSOURCE_PLLSAI             ((uint32_t)0x00000000U)\r\n#define RCC_SAI1CLKSOURCE_PLLI2S             RCC_DCKCFGR1_SAI1SEL_0\r\n#define RCC_SAI1CLKSOURCE_PIN                RCC_DCKCFGR1_SAI1SEL_1\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define RCC_SAI1CLKSOURCE_PLLSRC             RCC_DCKCFGR1_SAI1SEL\r\n#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_SAI2_Clock_Source RCCEx SAI2 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_SAI2CLKSOURCE_PLLSAI             ((uint32_t)0x00000000U)\r\n#define RCC_SAI2CLKSOURCE_PLLI2S             RCC_DCKCFGR1_SAI2SEL_0\r\n#define RCC_SAI2CLKSOURCE_PIN                RCC_DCKCFGR1_SAI2SEL_1\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define RCC_SAI2CLKSOURCE_PLLSRC             RCC_DCKCFGR1_SAI2SEL\r\n#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source\r\n  * @{\r\n  */\r\n#define RCC_CECCLKSOURCE_LSE             ((uint32_t)0x00000000U)\r\n#define RCC_CECCLKSOURCE_HSI             RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_USART1CLKSOURCE_PCLK2      ((uint32_t)0x00000000U)\r\n#define RCC_USART1CLKSOURCE_SYSCLK     RCC_DCKCFGR2_USART1SEL_0\r\n#define RCC_USART1CLKSOURCE_HSI        RCC_DCKCFGR2_USART1SEL_1\r\n#define RCC_USART1CLKSOURCE_LSE        RCC_DCKCFGR2_USART1SEL\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_USART2CLKSOURCE_PCLK1       ((uint32_t)0x00000000U)\r\n#define RCC_USART2CLKSOURCE_SYSCLK     RCC_DCKCFGR2_USART2SEL_0\r\n#define RCC_USART2CLKSOURCE_HSI        RCC_DCKCFGR2_USART2SEL_1\r\n#define RCC_USART2CLKSOURCE_LSE        RCC_DCKCFGR2_USART2SEL\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_USART3CLKSOURCE_PCLK1       ((uint32_t)0x00000000U)\r\n#define RCC_USART3CLKSOURCE_SYSCLK     RCC_DCKCFGR2_USART3SEL_0\r\n#define RCC_USART3CLKSOURCE_HSI        RCC_DCKCFGR2_USART3SEL_1\r\n#define RCC_USART3CLKSOURCE_LSE        RCC_DCKCFGR2_USART3SEL\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_UART4CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)\r\n#define RCC_UART4CLKSOURCE_SYSCLK       RCC_DCKCFGR2_UART4SEL_0\r\n#define RCC_UART4CLKSOURCE_HSI          RCC_DCKCFGR2_UART4SEL_1\r\n#define RCC_UART4CLKSOURCE_LSE          RCC_DCKCFGR2_UART4SEL\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_UART5CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)\r\n#define RCC_UART5CLKSOURCE_SYSCLK       RCC_DCKCFGR2_UART5SEL_0\r\n#define RCC_UART5CLKSOURCE_HSI          RCC_DCKCFGR2_UART5SEL_1\r\n#define RCC_UART5CLKSOURCE_LSE          RCC_DCKCFGR2_UART5SEL\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_USART6CLKSOURCE_PCLK2       ((uint32_t)0x00000000U)\r\n#define RCC_USART6CLKSOURCE_SYSCLK      RCC_DCKCFGR2_USART6SEL_0\r\n#define RCC_USART6CLKSOURCE_HSI         RCC_DCKCFGR2_USART6SEL_1\r\n#define RCC_USART6CLKSOURCE_LSE         RCC_DCKCFGR2_USART6SEL\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_UART7CLKSOURCE_PCLK1       ((uint32_t)0x00000000U)\r\n#define RCC_UART7CLKSOURCE_SYSCLK      RCC_DCKCFGR2_UART7SEL_0\r\n#define RCC_UART7CLKSOURCE_HSI         RCC_DCKCFGR2_UART7SEL_1\r\n#define RCC_UART7CLKSOURCE_LSE         RCC_DCKCFGR2_UART7SEL\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_UART8CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)\r\n#define RCC_UART8CLKSOURCE_SYSCLK      RCC_DCKCFGR2_UART8SEL_0\r\n#define RCC_UART8CLKSOURCE_HSI         RCC_DCKCFGR2_UART8SEL_1\r\n#define RCC_UART8CLKSOURCE_LSE         RCC_DCKCFGR2_UART8SEL\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_I2C1CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)\r\n#define RCC_I2C1CLKSOURCE_SYSCLK       RCC_DCKCFGR2_I2C1SEL_0\r\n#define RCC_I2C1CLKSOURCE_HSI          RCC_DCKCFGR2_I2C1SEL_1\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_I2C2CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)\r\n#define RCC_I2C2CLKSOURCE_SYSCLK       RCC_DCKCFGR2_I2C2SEL_0\r\n#define RCC_I2C2CLKSOURCE_HSI          RCC_DCKCFGR2_I2C2SEL_1\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_I2C3CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)\r\n#define RCC_I2C3CLKSOURCE_SYSCLK       RCC_DCKCFGR2_I2C3SEL_0\r\n#define RCC_I2C3CLKSOURCE_HSI          RCC_DCKCFGR2_I2C3SEL_1\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_I2C4CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)\r\n#define RCC_I2C4CLKSOURCE_SYSCLK       RCC_DCKCFGR2_I2C4SEL_0\r\n#define RCC_I2C4CLKSOURCE_HSI          RCC_DCKCFGR2_I2C4SEL_1\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_LPTIM1CLKSOURCE_PCLK1       ((uint32_t)0x00000000U)\r\n#define RCC_LPTIM1CLKSOURCE_LSI        RCC_DCKCFGR2_LPTIM1SEL_0\r\n#define RCC_LPTIM1CLKSOURCE_HSI        RCC_DCKCFGR2_LPTIM1SEL_1\r\n#define RCC_LPTIM1CLKSOURCE_LSE        RCC_DCKCFGR2_LPTIM1SEL\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_CLK48_Clock_Source RCCEx CLK48 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_CLK48SOURCE_PLL         ((uint32_t)0x00000000U)\r\n#define RCC_CLK48SOURCE_PLLSAIP     RCC_DCKCFGR2_CK48MSEL\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection\r\n  * @{\r\n  */\r\n#define RCC_TIMPRES_DESACTIVATED        ((uint32_t)0x00000000U)\r\n#define RCC_TIMPRES_ACTIVATED           RCC_DCKCFGR1_TIMPRE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_SDMMC1CLKSOURCE_CLK48              ((uint32_t)0x00000000U)\r\n#define RCC_SDMMC1CLKSOURCE_SYSCLK             RCC_DCKCFGR2_SDMMC1SEL\r\n/**\r\n  * @}\r\n  */\r\n\r\n#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)\r\n/** @defgroup RCCEx_SDMMC2_Clock_Source RCCEx SDMMC2 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_SDMMC2CLKSOURCE_CLK48              ((uint32_t)0x00000000U)\r\n#define RCC_SDMMC2CLKSOURCE_SYSCLK             RCC_DCKCFGR2_SDMMC2SEL\r\n/**\r\n  * @}\r\n  */\r\n#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r\n\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source  RCCEx DFSDM1 Kernel Clock Source\r\n  * @{\r\n  */\r\n#define RCC_DFSDM1CLKSOURCE_PCLK2             ((uint32_t)0x00000000U)\r\n#define RCC_DFSDM1CLKSOURCE_SYSCLK           RCC_DCKCFGR1_DFSDM1SEL\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_DFSDM1_AUDIO_Clock_Source RCCEx DFSDM1 AUDIO Clock Source\r\n  * @{\r\n  */\r\n#define RCC_DFSDM1AUDIOCLKSOURCE_SAI1        ((uint32_t)0x00000000U)\r\n#define RCC_DFSDM1AUDIOCLKSOURCE_SAI2        RCC_DCKCFGR1_ADFSDM1SEL\r\n/**\r\n  * @}\r\n  */\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n#if defined (STM32F769xx) || defined (STM32F779xx)\r\n/** @defgroup RCCEx_DSI_Clock_Source  RCC DSI Clock Source\r\n  * @{\r\n  */\r\n#define RCC_DSICLKSOURCE_DSIPHY             ((uint32_t)0x00000000U)\r\n#define RCC_DSICLKSOURCE_PLLR               ((uint32_t)RCC_DCKCFGR2_DSISEL)\r\n/**\r\n  * @}\r\n  */\r\n#endif /* STM32F769xx || STM32F779xx */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros\r\n  * @{\r\n  */\r\n/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable\r\n  * @brief  Enables or disables the AHB/APB peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before\r\n  *         using it.\r\n  * @{\r\n  */\r\n\r\n/** @brief  Enables or disables the AHB1 peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before\r\n  *         using it.\r\n  */\r\n#define __HAL_RCC_BKPSRAM_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_DTCMRAMEN_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_DMA2_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_GPIOC_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_GPIOF_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_GPIOG_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_GPIOH_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_GPIOI_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\\r\n    defined (STM32F750xx)\r\n#define __HAL_RCC_GPIOJ_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_GPIOK_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_DMA2D_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n\r\n#define __HAL_RCC_BKPSRAM_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))\r\n#define __HAL_RCC_DTCMRAMEN_CLK_DISABLE()       (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN))\r\n#define __HAL_RCC_DMA2_CLK_DISABLE()            (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))\r\n#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()      (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))\r\n#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))\r\n#define __HAL_RCC_GPIOA_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))\r\n#define __HAL_RCC_GPIOB_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))\r\n#define __HAL_RCC_GPIOC_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))\r\n#define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))\r\n#define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))\r\n#define __HAL_RCC_GPIOF_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))\r\n#define __HAL_RCC_GPIOG_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))\r\n#define __HAL_RCC_GPIOH_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))\r\n#define __HAL_RCC_GPIOI_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))\r\n#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\\r\n    defined (STM32F750xx)\r\n#define __HAL_RCC_GPIOJ_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))\r\n#define __HAL_RCC_GPIOK_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))\r\n#define __HAL_RCC_DMA2D_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))\r\n#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n\r\n#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\\r\n    defined (STM32F750xx)\r\n/**\r\n  * @brief  Enable ETHERNET clock.\r\n  */\r\n#define __HAL_RCC_ETHMAC_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_ETHMACTX_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_ETHMACRX_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_ETHMACPTP_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_ETH_CLK_ENABLE()       do {                            \\\r\n                                     __HAL_RCC_ETHMAC_CLK_ENABLE();      \\\r\n                                     __HAL_RCC_ETHMACTX_CLK_ENABLE();    \\\r\n                                     __HAL_RCC_ETHMACRX_CLK_ENABLE();    \\\r\n                                    } while(0)\r\n/**\r\n  * @brief  Disable ETHERNET clock.\r\n  */\r\n#define __HAL_RCC_ETHMAC_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))\r\n#define __HAL_RCC_ETHMACTX_CLK_DISABLE()  (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))\r\n#define __HAL_RCC_ETHMACRX_CLK_DISABLE()  (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))\r\n#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))\r\n#define __HAL_RCC_ETH_CLK_DISABLE()       do {                             \\\r\n                                      __HAL_RCC_ETHMACTX_CLK_DISABLE();    \\\r\n                                      __HAL_RCC_ETHMACRX_CLK_DISABLE();    \\\r\n                                      __HAL_RCC_ETHMAC_CLK_DISABLE();      \\\r\n                                     } while(0)\r\n#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n\r\n/** @brief  Enable or disable the AHB2 peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before\r\n  *         using it.\r\n  */\r\n#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\\r\n    defined (STM32F750xx)\r\n#define __HAL_RCC_DCMI_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n#define __HAL_RCC_DCMI_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))\r\n#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n\r\n#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_JPEG_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n#define __HAL_RCC_JPEG_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_JPEGEN))\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n#define __HAL_RCC_RNG_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                        __HAL_RCC_SYSCFG_CLK_ENABLE();\\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_RNG_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))\r\n\r\n#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))\r\n#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r\n#define __HAL_RCC_CRYP_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_HASH_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_CRYP_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))\r\n#define __HAL_RCC_HASH_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))\r\n#endif /* STM32F756x || STM32F777xx || STM32F779xx || STM32F750xx */\r\n\r\n#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)\r\n#define __HAL_RCC_AES_CLK_ENABLE()    do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_AES_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN))\r\n#endif /* STM32F732xx || STM32F733xx || STM32F730xx */\r\n\r\n/** @brief  Enables or disables the AHB3 peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before\r\n  *         using it.\r\n  */\r\n#define __HAL_RCC_FMC_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_QSPI_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_FMC_CLK_DISABLE()   (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))\r\n#define __HAL_RCC_QSPI_CLK_DISABLE()  (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))\r\n\r\n/** @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before\r\n  *         using it.\r\n  */\r\n#define __HAL_RCC_TIM2_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_TIM3_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_TIM4_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_TIM5_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_TIM12_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_TIM13_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_TIM14_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_LPTIM1_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\\\r\n    defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\\\r\n    defined (STM32F779xx) || defined (STM32F730xx)\r\n#define __HAL_RCC_RTC_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||\r\n          STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r\n\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_CAN3_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n#define __HAL_RCC_SPI2_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_SPI3_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_USART2_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_USART3_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_UART4_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_UART5_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_I2C1_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_I2C2_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_I2C3_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_CAN1_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_DAC_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_UART7_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_UART8_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\\r\n    defined (STM32F750xx)\r\n#define __HAL_RCC_SPDIFRX_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_I2C4_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_CAN2_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_CEC_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n\r\n#define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))\r\n#define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))\r\n#define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))\r\n#define __HAL_RCC_TIM5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))\r\n#define __HAL_RCC_TIM6_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))\r\n#define __HAL_RCC_TIM7_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))\r\n#define __HAL_RCC_TIM12_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))\r\n#define __HAL_RCC_TIM13_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))\r\n#define __HAL_RCC_TIM14_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))\r\n#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))\r\n#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\\\r\n    defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\\\r\n    defined (STM32F779xx) || defined (STM32F730xx)\r\n#define __HAL_RCC_RTC_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCEN))\r\n#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||\r\n          STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_CAN3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN))\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n#define __HAL_RCC_SPI2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))\r\n#define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))\r\n#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))\r\n#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))\r\n#define __HAL_RCC_UART4_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))\r\n#define __HAL_RCC_UART5_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))\r\n#define __HAL_RCC_I2C1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))\r\n#define __HAL_RCC_I2C2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))\r\n#define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))\r\n#define __HAL_RCC_CAN1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))\r\n#define __HAL_RCC_DAC_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))\r\n#define __HAL_RCC_UART7_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))\r\n#define __HAL_RCC_UART8_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))\r\n#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\\r\n    defined (STM32F750xx)\r\n#define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))\r\n#define __HAL_RCC_I2C4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN))\r\n#define __HAL_RCC_CAN2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))\r\n#define __HAL_RCC_CEC_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))\r\n#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || || STM32F750xx */\r\n\r\n/** @brief  Enable or disable the High Speed APB (APB2) peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before\r\n  *         using it.\r\n  */\r\n#define __HAL_RCC_TIM1_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_TIM8_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_USART1_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_USART6_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)\r\n#define __HAL_RCC_SDMMC2_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || || STM32F730xx */\r\n\r\n#define __HAL_RCC_ADC1_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_ADC2_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_ADC3_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_SDMMC1_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_SPI1_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_SPI4_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_TIM9_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_TIM10_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_TIM11_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_SPI5_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_SPI6_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_SAI1_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_SAI2_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r\n#define __HAL_RCC_LTDC_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n\r\n#if defined (STM32F769xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_DSI_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n#endif /* STM32F769xx || STM32F779xx */\r\n\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_DFSDM1_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_MDIO_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx)\r\n#define __HAL_RCC_OTGPHYC_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_OTGPHYCEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_OTGPHYCEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n#endif /* STM32F723xx || STM32F733xx || STM32F730xx */\r\n\r\n#define __HAL_RCC_TIM1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))\r\n#define __HAL_RCC_TIM8_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))\r\n#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))\r\n#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))\r\n#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)\r\n#define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC2EN))\r\n#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r\n#define __HAL_RCC_ADC1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))\r\n#define __HAL_RCC_ADC2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))\r\n#define __HAL_RCC_ADC3_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))\r\n#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN))\r\n#define __HAL_RCC_SPI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))\r\n#define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))\r\n#define __HAL_RCC_TIM9_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))\r\n#define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))\r\n#define __HAL_RCC_TIM11_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))\r\n#define __HAL_RCC_SPI5_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))\r\n#define __HAL_RCC_SPI6_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))\r\n#define __HAL_RCC_SAI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))\r\n#define __HAL_RCC_SAI2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))\r\n#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r\n#define __HAL_RCC_LTDC_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))\r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n#if defined (STM32F769xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_DSI_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))\r\n#endif /* STM32F769xx || STM32F779xx */\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN))\r\n#define __HAL_RCC_MDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_MDIOEN))\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx)\r\n#define __HAL_RCC_OTGPHYC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_OTGPHYCEN))\r\n#endif /* STM32F723xx || STM32F733xx || STM32F730xx */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status\r\n  * @brief  Get the enable or disable status of the AHB/APB peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before\r\n  *         using it.\r\n  * @{\r\n  */\r\n\r\n/** @brief  Get the enable or disable status of the AHB1 peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before\r\n  *         using it.\r\n  */\r\n#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)\r\n#define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET)\r\n#define __HAL_RCC_DMA2_IS_CLK_ENABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET)\r\n#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)\r\n#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)\r\n#define __HAL_RCC_GPIOA_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET)\r\n#define __HAL_RCC_GPIOB_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET)\r\n#define __HAL_RCC_GPIOC_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET)\r\n#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)\r\n#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)\r\n#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)\r\n#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)\r\n#define __HAL_RCC_GPIOH_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET)\r\n#define __HAL_RCC_GPIOI_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)\r\n#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\\r\n    defined (STM32F750xx)\r\n#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)\r\n#define __HAL_RCC_GPIOK_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)\r\n#define __HAL_RCC_DMA2D_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)\r\n#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n\r\n#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)\r\n#define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET)\r\n#define __HAL_RCC_DMA2_IS_CLK_DISABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET)\r\n#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)\r\n#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)\r\n#define __HAL_RCC_GPIOA_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET)\r\n#define __HAL_RCC_GPIOB_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET)\r\n#define __HAL_RCC_GPIOC_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET)\r\n#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)\r\n#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)\r\n#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)\r\n#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)\r\n#define __HAL_RCC_GPIOH_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET)\r\n#define __HAL_RCC_GPIOI_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)\r\n#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\\r\n    defined (STM32F750xx)\r\n#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)\r\n#define __HAL_RCC_GPIOK_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)\r\n#define __HAL_RCC_DMA2D_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)\r\n#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n\r\n#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\\r\n    defined (STM32F750xx)\r\n/**\r\n  * @brief  Enable ETHERNET clock.\r\n  */\r\n#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)\r\n#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)\r\n#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)\r\n#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)\r\n#define __HAL_RCC_ETH_IS_CLK_ENABLED()        (__HAL_RCC_ETHMAC_IS_CLK_ENABLED()   && \\\r\n                                               __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \\\r\n                                               __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())\r\n\r\n/**\r\n  * @brief  Disable ETHERNET clock.\r\n  */\r\n#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)\r\n#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)\r\n#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)\r\n#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)\r\n#define __HAL_RCC_ETH_IS_CLK_DISABLED()        (__HAL_RCC_ETHMAC_IS_CLK_DISABLED()   && \\\r\n                                                __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \\\r\n                                                __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())\r\n#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n\r\n/** @brief  Get the enable or disable status of the AHB2 peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before\r\n  *         using it.\r\n  */\r\n#define __HAL_RCC_RNG_IS_CLK_ENABLED()         ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)\r\n#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)\r\n\r\n#define __HAL_RCC_RNG_IS_CLK_DISABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)\r\n#define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)\r\n\r\n#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r\n#define __HAL_RCC_CRYP_IS_CLK_ENABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)\r\n#define __HAL_RCC_HASH_IS_CLK_ENABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)\r\n#define __HAL_RCC_CRYP_IS_CLK_DISABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)\r\n#define __HAL_RCC_HASH_IS_CLK_DISABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)\r\n#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n\r\n#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)\r\n#define __HAL_RCC_AES_IS_CLK_ENABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET)\r\n#define __HAL_RCC_AES_IS_CLK_DISABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET)\r\n#endif /* STM32F732xx || STM32F733xx || STM32F730xx */\r\n\r\n#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\\r\n    defined (STM32F750xx)\r\n#define __HAL_RCC_DCMI_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)\r\n#define __HAL_RCC_DCMI_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)\r\n#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n\r\n#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_JPEG_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) != RESET)\r\n#define __HAL_RCC_JPEG_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) == RESET)\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n/** @brief  Get the enable or disable status of the AHB3 peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before\r\n  *         using it.\r\n  */\r\n#define __HAL_RCC_FMC_IS_CLK_ENABLED()   ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)\r\n#define __HAL_RCC_QSPI_IS_CLK_ENABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)\r\n\r\n#define __HAL_RCC_FMC_IS_CLK_DISABLED()   ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)\r\n#define __HAL_RCC_QSPI_IS_CLK_DISABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)\r\n\r\n/** @brief  Get the enable or disable status of the APB1 peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before\r\n  *         using it.\r\n  */\r\n#define __HAL_RCC_TIM2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)\r\n#define __HAL_RCC_TIM3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)\r\n#define __HAL_RCC_TIM4_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)\r\n#define __HAL_RCC_TIM5_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)\r\n#define __HAL_RCC_TIM6_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)\r\n#define __HAL_RCC_TIM7_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)\r\n#define __HAL_RCC_TIM12_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)\r\n#define __HAL_RCC_TIM13_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)\r\n#define __HAL_RCC_TIM14_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)\r\n#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_CAN3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET)\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n#define __HAL_RCC_SPI2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)\r\n#define __HAL_RCC_SPI3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)\r\n#define __HAL_RCC_USART2_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)\r\n#define __HAL_RCC_USART3_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)\r\n#define __HAL_RCC_UART4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)\r\n#define __HAL_RCC_UART5_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)\r\n#define __HAL_RCC_I2C1_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)\r\n#define __HAL_RCC_I2C2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)\r\n#define __HAL_RCC_I2C3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)\r\n#define __HAL_RCC_CAN1_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)\r\n#define __HAL_RCC_DAC_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)\r\n#define __HAL_RCC_UART7_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)\r\n#define __HAL_RCC_UART8_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)\r\n\r\n#define __HAL_RCC_TIM2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)\r\n#define __HAL_RCC_TIM3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)\r\n#define __HAL_RCC_TIM4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)\r\n#define __HAL_RCC_TIM5_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)\r\n#define __HAL_RCC_TIM6_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)\r\n#define __HAL_RCC_TIM7_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)\r\n#define __HAL_RCC_TIM12_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)\r\n#define __HAL_RCC_TIM13_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)\r\n#define __HAL_RCC_TIM14_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)\r\n#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_CAN3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET)\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n#define __HAL_RCC_SPI2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)\r\n#define __HAL_RCC_SPI3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)\r\n#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)\r\n#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)\r\n#define __HAL_RCC_UART4_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)\r\n#define __HAL_RCC_UART5_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)\r\n#define __HAL_RCC_I2C1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)\r\n#define __HAL_RCC_I2C2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)\r\n#define __HAL_RCC_I2C3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)\r\n#define __HAL_RCC_CAN1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)\r\n#define __HAL_RCC_DAC_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)\r\n#define __HAL_RCC_UART7_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)\r\n#define __HAL_RCC_UART8_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)\r\n#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\\r\n    defined (STM32F750xx)\r\n#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)\r\n#define __HAL_RCC_CAN2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)\r\n#define __HAL_RCC_CEC_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)\r\n#define __HAL_RCC_I2C4_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET)\r\n\r\n#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)\r\n#define __HAL_RCC_CAN2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)\r\n#define __HAL_RCC_CEC_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)\r\n#define __HAL_RCC_I2C4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET)\r\n#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n\r\n#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\\\r\n    defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\\\r\n    defined (STM32F779xx) || defined (STM32F730xx)\r\n#define __HAL_RCC_RTC_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) != RESET)\r\n#define __HAL_RCC_RTC_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) == RESET)\r\n#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||\r\n          STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r\n\r\n/** @brief  Get the enable or disable status of the APB2 peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before\r\n  *         using it.\r\n  */\r\n#define __HAL_RCC_TIM1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)\r\n#define __HAL_RCC_TIM8_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)\r\n#define __HAL_RCC_USART1_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)\r\n#define __HAL_RCC_USART6_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)\r\n#define __HAL_RCC_ADC1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)\r\n#define __HAL_RCC_ADC2_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)\r\n#define __HAL_RCC_ADC3_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)\r\n#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET)\r\n#define __HAL_RCC_SPI1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)\r\n#define __HAL_RCC_SPI4_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)\r\n#define __HAL_RCC_TIM9_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)\r\n#define __HAL_RCC_TIM10_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)\r\n#define __HAL_RCC_TIM11_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)\r\n#define __HAL_RCC_SPI5_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)\r\n#define __HAL_RCC_SPI6_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)\r\n#define __HAL_RCC_SAI1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)\r\n#define __HAL_RCC_SAI2_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)\r\n#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r\n#define __HAL_RCC_LTDC_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)\r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n#if defined (STM32F769xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_DSI_IS_CLK_ENABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET)\r\n#endif /* STM32F769xx || STM32F779xx */\r\n#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)\r\n#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) != RESET)\r\n#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET)\r\n#define __HAL_RCC_MDIO_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) != RESET)\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx)\r\n#define __HAL_RCC_OTGPHYC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) != RESET)\r\n#endif /* STM32F723xx || STM32F733xx || STM32F730xx */\r\n\r\n#define __HAL_RCC_TIM1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)\r\n#define __HAL_RCC_TIM8_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)\r\n#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)\r\n#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)\r\n#define __HAL_RCC_ADC1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)\r\n#define __HAL_RCC_ADC2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)\r\n#define __HAL_RCC_ADC3_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)\r\n#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET)\r\n#define __HAL_RCC_SPI1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)\r\n#define __HAL_RCC_SPI4_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)\r\n#define __HAL_RCC_TIM9_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)\r\n#define __HAL_RCC_TIM10_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)\r\n#define __HAL_RCC_TIM11_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)\r\n#define __HAL_RCC_SPI5_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)\r\n#define __HAL_RCC_SPI6_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)\r\n#define __HAL_RCC_SAI1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)\r\n#define __HAL_RCC_SAI2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)\r\n#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r\n#define __HAL_RCC_LTDC_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)\r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n#if defined (STM32F769xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_DSI_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET)\r\n#endif /* STM32F769xx || STM32F779xx */\r\n#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)\r\n#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) == RESET)\r\n#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET)\r\n#define __HAL_RCC_MDIO_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) == RESET)\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx)\r\n#define __HAL_RCC_OTGPHYC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) == RESET)\r\n#endif /* STM32F723xx || STM32F733xx || STM32F730xx */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset\r\n  * @brief  Forces or releases AHB/APB peripheral reset.\r\n  * @{\r\n  */\r\n\r\n/** @brief  Force or release AHB1 peripheral reset.\r\n  */\r\n#define __HAL_RCC_DMA2_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))\r\n#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))\r\n#define __HAL_RCC_GPIOA_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))\r\n#define __HAL_RCC_GPIOB_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))\r\n#define __HAL_RCC_GPIOC_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))\r\n#define __HAL_RCC_GPIOD_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))\r\n#define __HAL_RCC_GPIOE_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))\r\n#define __HAL_RCC_GPIOF_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))\r\n#define __HAL_RCC_GPIOG_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))\r\n#define __HAL_RCC_GPIOH_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))\r\n#define __HAL_RCC_GPIOI_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))\r\n\r\n#define __HAL_RCC_DMA2_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))\r\n#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))\r\n#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))\r\n#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))\r\n#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))\r\n#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))\r\n#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))\r\n#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))\r\n#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))\r\n#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))\r\n#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))\r\n\r\n#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\\r\n    defined (STM32F750xx)\r\n#define __HAL_RCC_DMA2D_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))\r\n#define __HAL_RCC_ETHMAC_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))\r\n#define __HAL_RCC_GPIOJ_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))\r\n#define __HAL_RCC_GPIOK_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))\r\n\r\n#define __HAL_RCC_DMA2D_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))\r\n#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))\r\n#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))\r\n#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))\r\n#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n\r\n/** @brief  Force or release AHB2 peripheral reset.\r\n  */\r\n#define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFFU)\r\n#define __HAL_RCC_RNG_FORCE_RESET()    (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))\r\n#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))\r\n\r\n#define __HAL_RCC_AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00U)\r\n#define __HAL_RCC_RNG_RELEASE_RESET()  (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))\r\n#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))\r\n\r\n#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_JPEG_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_JPEGRST))\r\n#define __HAL_RCC_JPEG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_JPEGRST))\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r\n#define __HAL_RCC_CRYP_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))\r\n#define __HAL_RCC_HASH_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))\r\n#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))\r\n#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))\r\n#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n\r\n#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)\r\n#define __HAL_RCC_AES_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_AESRST))\r\n#define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST))\r\n#endif /* STM32F732xx || STM32F733xx || STM32F730xx */\r\n\r\n#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\\r\n    defined (STM32F750xx)\r\n#define __HAL_RCC_DCMI_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))\r\n#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))\r\n#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n\r\n/** @brief  Force or release AHB3 peripheral reset\r\n  */\r\n#define __HAL_RCC_AHB3_FORCE_RESET()   (RCC->AHB3RSTR = 0xFFFFFFFFU)\r\n#define __HAL_RCC_FMC_FORCE_RESET()    (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))\r\n#define __HAL_RCC_QSPI_FORCE_RESET()   (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))\r\n\r\n#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)\r\n#define __HAL_RCC_FMC_RELEASE_RESET()  (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))\r\n#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))\r\n\r\n/** @brief  Force or release APB1 peripheral reset.\r\n  */\r\n#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))\r\n#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))\r\n#define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))\r\n#define __HAL_RCC_TIM5_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))\r\n#define __HAL_RCC_TIM6_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))\r\n#define __HAL_RCC_TIM7_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))\r\n#define __HAL_RCC_TIM12_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))\r\n#define __HAL_RCC_TIM13_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))\r\n#define __HAL_RCC_TIM14_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))\r\n#define __HAL_RCC_LPTIM1_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_CAN3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST))\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n#define __HAL_RCC_SPI2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))\r\n#define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))\r\n#define __HAL_RCC_USART2_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))\r\n#define __HAL_RCC_USART3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))\r\n#define __HAL_RCC_UART4_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))\r\n#define __HAL_RCC_UART5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))\r\n#define __HAL_RCC_I2C1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))\r\n#define __HAL_RCC_I2C2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))\r\n#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))\r\n#define __HAL_RCC_CAN1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))\r\n#define __HAL_RCC_DAC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))\r\n#define __HAL_RCC_UART7_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))\r\n#define __HAL_RCC_UART8_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))\r\n\r\n#define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))\r\n#define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))\r\n#define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))\r\n#define __HAL_RCC_TIM5_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))\r\n#define __HAL_RCC_TIM6_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))\r\n#define __HAL_RCC_TIM7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))\r\n#define __HAL_RCC_TIM12_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))\r\n#define __HAL_RCC_TIM13_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))\r\n#define __HAL_RCC_TIM14_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))\r\n#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_CAN3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST))\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n#define __HAL_RCC_SPI2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))\r\n#define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))\r\n#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))\r\n#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))\r\n#define __HAL_RCC_UART4_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))\r\n#define __HAL_RCC_UART5_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))\r\n#define __HAL_RCC_I2C1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))\r\n#define __HAL_RCC_I2C2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))\r\n#define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))\r\n#define __HAL_RCC_CAN1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))\r\n#define __HAL_RCC_DAC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))\r\n#define __HAL_RCC_UART7_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))\r\n#define __HAL_RCC_UART8_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))\r\n\r\n#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\\r\n    defined (STM32F750xx)\r\n#define __HAL_RCC_SPDIFRX_FORCE_RESET()  (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST))\r\n#define __HAL_RCC_I2C4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST))\r\n#define __HAL_RCC_CAN2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))\r\n#define __HAL_RCC_CEC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))\r\n\r\n#define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))\r\n#define __HAL_RCC_I2C4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST))\r\n#define __HAL_RCC_CAN2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))\r\n#define __HAL_RCC_CEC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))\r\n#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n\r\n/** @brief  Force or release APB2 peripheral reset.\r\n  */\r\n#define __HAL_RCC_TIM1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))\r\n#define __HAL_RCC_TIM8_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))\r\n#define __HAL_RCC_USART1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))\r\n#define __HAL_RCC_USART6_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))\r\n#define __HAL_RCC_ADC_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))\r\n#define __HAL_RCC_SDMMC1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC1RST))\r\n#define __HAL_RCC_SPI1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))\r\n#define __HAL_RCC_SPI4_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))\r\n#define __HAL_RCC_TIM9_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))\r\n#define __HAL_RCC_TIM10_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))\r\n#define __HAL_RCC_TIM11_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))\r\n#define __HAL_RCC_SPI5_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))\r\n#define __HAL_RCC_SPI6_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))\r\n#define __HAL_RCC_SAI1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))\r\n#define __HAL_RCC_SAI2_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))\r\n#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r\n#define __HAL_RCC_LTDC_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))\r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx)\r\n#define __HAL_RCC_OTGPHYC_FORCE_RESET()  (RCC->APB2RSTR |= (RCC_APB2RSTR_OTGPHYCRST))\r\n#endif /* STM32F723xx || STM32F733xx || STM32F730xx */\r\n\r\n#define __HAL_RCC_TIM1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))\r\n#define __HAL_RCC_TIM8_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))\r\n#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))\r\n#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))\r\n#define __HAL_RCC_ADC_RELEASE_RESET()    (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))\r\n#define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC1RST))\r\n#define __HAL_RCC_SPI1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))\r\n#define __HAL_RCC_SPI4_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))\r\n#define __HAL_RCC_TIM9_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))\r\n#define __HAL_RCC_TIM10_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))\r\n#define __HAL_RCC_TIM11_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))\r\n#define __HAL_RCC_SPI5_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))\r\n#define __HAL_RCC_SPI6_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))\r\n#define __HAL_RCC_SAI1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))\r\n#define __HAL_RCC_SAI2_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))\r\n#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r\n#define __HAL_RCC_LTDC_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))\r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx)\r\n#define __HAL_RCC_OTGPHYC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_OTGPHYCRST))\r\n#endif /* STM32F723xx || STM32F733xx || STM32F730xx */\r\n\r\n#if defined (STM32F769xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_DSI_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST))\r\n#define __HAL_RCC_DSI_RELEASE_RESET()    (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST))\r\n#endif /* STM32F769xx || STM32F779xx */\r\n\r\n#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)\r\n#define __HAL_RCC_SDMMC2_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC2RST))\r\n#define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC2RST))\r\n#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r\n\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_DFSDM1_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST))\r\n#define __HAL_RCC_MDIO_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_MDIORST))\r\n#define __HAL_RCC_DFSDM1_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST))\r\n#define __HAL_RCC_MDIO_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_MDIORST))\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable\r\n  * @brief  Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode.\r\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r\n  *         power consumption.\r\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r\n  * @{\r\n  */\r\n\r\n/** @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.\r\n  */\r\n#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))\r\n#define __HAL_RCC_AXI_CLK_SLEEP_ENABLE()        (RCC->AHB1LPENR |= (RCC_AHB1LPENR_AXILPEN))\r\n#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))\r\n#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))\r\n#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))\r\n#define __HAL_RCC_DTCM_CLK_SLEEP_ENABLE()       (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DTCMLPEN))\r\n#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE()       (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))\r\n#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))\r\n#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))\r\n#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))\r\n#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))\r\n#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))\r\n#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))\r\n#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))\r\n#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))\r\n#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))\r\n#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))\r\n#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))\r\n\r\n#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))\r\n#define __HAL_RCC_AXI_CLK_SLEEP_DISABLE()       (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_AXILPEN))\r\n#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))\r\n#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))\r\n#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))\r\n#define __HAL_RCC_DTCM_CLK_SLEEP_DISABLE()      (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DTCMLPEN))\r\n#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE()      (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))\r\n#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()      (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))\r\n#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))\r\n#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))\r\n#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))\r\n#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))\r\n#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))\r\n#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))\r\n#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))\r\n#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))\r\n#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))\r\n#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))\r\n\r\n#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\\r\n    defined (STM32F750xx)\r\n#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))\r\n#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))\r\n#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))\r\n#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))\r\n#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))\r\n#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))\r\n#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))\r\n\r\n#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))\r\n#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))\r\n#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))\r\n#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))\r\n#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))\r\n#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))\r\n#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))\r\n#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n\r\n/** @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.\r\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r\n  *         power consumption.\r\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r\n  */\r\n#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\\r\n    defined (STM32F750xx)\r\n#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()        (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))\r\n#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE()       (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))\r\n#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n\r\n#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE()        (RCC->AHB2LPENR |= (RCC_AHB2LPENR_JPEGLPEN))\r\n#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE()       (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_JPEGLPEN))\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()         (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))\r\n#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()        (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))\r\n\r\n#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))\r\n#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))\r\n\r\n#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r\n#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE()        (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))\r\n#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE()        (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))\r\n\r\n#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE()       (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))\r\n#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE()       (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))\r\n#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n\r\n#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)\r\n#define __HAL_RCC_AES_CLK_SLEEP_ENABLE()        (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AESLPEN))\r\n#define __HAL_RCC_AES_CLK_SLEEP_DISABLE()       (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN))\r\n#endif /* STM32F732xx || STM32F733xx || STM32F730xx */\r\n\r\n/** @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.\r\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r\n  *         power consumption.\r\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r\n  */\r\n#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))\r\n#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))\r\n\r\n#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))\r\n#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))\r\n\r\n/** @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.\r\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r\n  *         power consumption.\r\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r\n  */\r\n#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))\r\n#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))\r\n#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))\r\n#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))\r\n#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))\r\n#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))\r\n#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))\r\n#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))\r\n#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))\r\n#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN))\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))\r\n#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))\r\n#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))\r\n#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))\r\n#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))\r\n#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))\r\n#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))\r\n#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))\r\n#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))\r\n#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))\r\n#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))\r\n#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))\r\n#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))\r\n\r\n#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))\r\n#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))\r\n#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))\r\n#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))\r\n#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))\r\n#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))\r\n#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))\r\n#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))\r\n#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))\r\n#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN))\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))\r\n#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))\r\n#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))\r\n#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))\r\n#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))\r\n#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))\r\n#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))\r\n#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))\r\n#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))\r\n#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))\r\n#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))\r\n#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))\r\n#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))\r\n\r\n#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\\\r\n    defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\\\r\n    defined (STM32F779xx) || defined (STM32F730xx)\r\n#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCLPEN))\r\n#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCLPEN))\r\n#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||\r\n          STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r\n\r\n#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\\r\n    defined (STM32F750xx)\r\n#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN))\r\n#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN))\r\n#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))\r\n#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN))\r\n\r\n#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))\r\n#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN))\r\n#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))\r\n#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))\r\n#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n\r\n/** @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.\r\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r\n  *         power consumption.\r\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r\n  */\r\n#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))\r\n#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))\r\n#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))\r\n#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))\r\n#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))\r\n#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))\r\n#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))\r\n#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC1LPEN))\r\n#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))\r\n#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))\r\n#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))\r\n#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))\r\n#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))\r\n#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))\r\n#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))\r\n#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))\r\n#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r\n#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))\r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n\r\n#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))\r\n#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))\r\n#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))\r\n#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))\r\n#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))\r\n#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))\r\n#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))\r\n#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC1LPEN))\r\n#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))\r\n#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))\r\n#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))\r\n#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))\r\n#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))\r\n#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))\r\n#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))\r\n#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))\r\n#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)|| defined (STM32F750xx)\r\n#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))\r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx  */\r\n#if defined (STM32F769xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE()     (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN))\r\n#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN))\r\n#endif /* STM32F769xx || STM32F779xx */\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN))\r\n#define __HAL_RCC_MDIO_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_MDIOLPEN))\r\n#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN))\r\n#define __HAL_RCC_MDIO_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_MDIOLPEN))\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)\r\n#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC2LPEN))\r\n#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC2LPEN))\r\n#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r\n\r\n#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\\r\n    defined (STM32F750xx)\r\n#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))\r\n#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))\r\n#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_Clock_Sleep_Enable_Disable_Status AHB/APB Peripheral Clock Sleep Enable Disable Status\r\n  * @brief  Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode.\r\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r\n  *         power consumption.\r\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r\n  * @{\r\n  */\r\n\r\n/** @brief  Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.\r\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r\n  *         power consumption.\r\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r\n  */\r\n#define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET)\r\n#define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED()        ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET)\r\n#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET)\r\n#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET)\r\n#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET)\r\n#define __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED()       ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET)\r\n#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED()       ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET)\r\n#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET)\r\n#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET)\r\n#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET)\r\n#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET)\r\n#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET)\r\n#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET)\r\n#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET)\r\n#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET)\r\n#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET)\r\n#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET)\r\n#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET)\r\n\r\n#define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET)\r\n#define __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED()       ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET)\r\n#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET)\r\n#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET)\r\n#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED()   ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET)\r\n#define __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET)\r\n#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET)\r\n#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET)\r\n#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET)\r\n#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET)\r\n#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET)\r\n#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET)\r\n#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET)\r\n#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET)\r\n#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET)\r\n#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET)\r\n#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET)\r\n#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET)\r\n\r\n#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\\r\n    defined (STM32F750xx)\r\n#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET)\r\n#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET)\r\n#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED()   ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET)\r\n#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED()   ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET)\r\n#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED()  ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET)\r\n#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET)\r\n#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET)\r\n\r\n#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET)\r\n#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET)\r\n#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED()  ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET)\r\n#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED()  ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET)\r\n#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET)\r\n#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET)\r\n#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET)\r\n#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n\r\n/** @brief  Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode.\r\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r\n  *         power consumption.\r\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r\n  */\r\n#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\\r\n    defined (STM32F750xx)\r\n#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED()        ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET)\r\n#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED()       ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET)\r\n#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n\r\n#if defined(STM32F767xx) || defined(STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED()        ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) != RESET)\r\n#define __HAL_RCC_JPEG_IS_CLK_SLEEP_DISABLED()       ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) == RESET)\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED()         ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET)\r\n#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED()        ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET)\r\n\r\n#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED()  ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET)\r\n#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET)\r\n\r\n#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r\n#define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED()        ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET)\r\n#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED()        ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET)\r\n\r\n#define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED()       ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET)\r\n#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED()       ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET)\r\n#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n\r\n#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)\r\n#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED()        ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AESLPEN)) != RESET)\r\n#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED()       ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AESLPEN)) == RESET)\r\n#endif /* STM32F732xx || STM32F733xx || STM32F730xx */\r\n\r\n/** @brief  Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode.\r\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r\n  *         power consumption.\r\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r\n  */\r\n#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED()  ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET)\r\n#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET)\r\n\r\n#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED()  ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET)\r\n#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET)\r\n\r\n/** @brief  Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.\r\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r\n  *         power consumption.\r\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r\n  */\r\n#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET)\r\n#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET)\r\n#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET)\r\n#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET)\r\n#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET)\r\n#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET)\r\n#define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET)\r\n#define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET)\r\n#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET)\r\n#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET)\r\n#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\\\r\n    defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\\\r\n    defined (STM32F779xx) || defined (STM32F730xx)\r\n#define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED()     ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) != RESET)\r\n#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||\r\n          STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_CAN3_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) != RESET)\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET)\r\n#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET)\r\n#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET)\r\n#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET)\r\n#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET)\r\n#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET)\r\n#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET)\r\n#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET)\r\n#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET)\r\n#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET)\r\n#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED()     ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET)\r\n#define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET)\r\n#define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET)\r\n\r\n#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET)\r\n#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET)\r\n#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET)\r\n#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET)\r\n#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET)\r\n#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET)\r\n#define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET)\r\n#define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET)\r\n#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET)\r\n#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET)\r\n#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\\\r\n    defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\\\r\n    defined (STM32F779xx) || defined (STM32F730xx)\r\n#define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) == RESET)\r\n#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||\r\n          STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_CAN3_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) == RESET)\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET)\r\n#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET)\r\n#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET)\r\n#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET)\r\n#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET)\r\n#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET)\r\n#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET)\r\n#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET)\r\n#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET)\r\n#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET)\r\n#define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET)\r\n#define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET)\r\n#define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET)\r\n\r\n#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\\r\n    defined (STM32F750xx)\r\n#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET)\r\n#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET)\r\n#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET)\r\n#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED()     ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET)\r\n\r\n#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET)\r\n#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET)\r\n#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET)\r\n#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET)\r\n#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n\r\n/** @brief  Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.\r\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r\n  *         power consumption.\r\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r\n  */\r\n#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET)\r\n#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET)\r\n#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED()  ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET)\r\n#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED()  ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET)\r\n#define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET)\r\n#define __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET)\r\n#define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET)\r\n#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED()  ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET)\r\n#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET)\r\n#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET)\r\n#define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET)\r\n#define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET)\r\n#define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET)\r\n#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET)\r\n#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET)\r\n#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET)\r\n#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r\n#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET)\r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n#if defined (STM32F769xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED()     ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) != RESET)\r\n#endif /* STM32F769xx || STM32F779xx */\r\n#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)\r\n#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED()  ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) != RESET)\r\n#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != RESET)\r\n#define __HAL_RCC_MDIO_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) != RESET)\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET)\r\n#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET)\r\n#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET)\r\n#define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET)\r\n#define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET)\r\n#define __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET)\r\n#define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET)\r\n#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET)\r\n#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET)\r\n#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET)\r\n#define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET)\r\n#define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED()  ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET)\r\n#define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED()  ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET)\r\n#define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET)\r\n#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET)\r\n#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET)\r\n#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r\n#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET)\r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n#if defined (STM32F769xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED()     ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) == RESET)\r\n#endif /* STM32F769xx || STM32F779xx */\r\n#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)\r\n#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED()  ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) == RESET)\r\n#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == RESET)\r\n#define __HAL_RCC_MDIO_IS_CLK_SLEEP_DISABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) == RESET)\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\\r\n    defined (STM32F750xx)\r\n#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET)\r\n#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET)\r\n#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/*------------------------------- PLL Configuration --------------------------*/\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n/** @brief  Macro to configure the main PLL clock source, multiplication and division factors.\r\n  * @note   This function must be used only when the main PLL is disabled.\r\n  * @param  __RCC_PLLSource__ specifies the PLL entry clock source.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry\r\n  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry\r\n  * @note   This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.\r\n  * @param  __PLLM__ specifies the division factor for PLL VCO input clock\r\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.\r\n  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input\r\n  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency\r\n  *         of 2 MHz to limit PLL jitter.\r\n  * @param  __PLLN__ specifies the multiplication factor for PLL VCO output clock\r\n  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.\r\n  * @note   You have to set the PLLN parameter correctly to ensure that the VCO\r\n  *         output frequency is between 100 and 432 MHz.\r\n  * @param  __PLLP__ specifies the division factor for main system clock (SYSCLK)\r\n  *         This parameter must be a number in the range {2, 4, 6, or 8}.\r\n  * @note   You have to set the PLLP parameter correctly to not exceed 216 MHz on\r\n  *         the System clock frequency.\r\n  * @param  __PLLQ__ specifies the division factor for OTG FS, SDMMC and RNG clocks\r\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.\r\n  * @note   If the USB OTG FS is used in your application, you have to set the\r\n  *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,\r\n  *         the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work\r\n  *         correctly.\r\n  * @param  __PLLR__ specifies the division factor for DSI clock\r\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.\r\n  */\r\n#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__)  \\\r\n                            (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__)                   | \\\r\n                            ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos)                      | \\\r\n                            ((((__PLLP__) >> 1) -1) << RCC_PLLCFGR_PLLP_Pos)          | \\\r\n                            ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos)                      | \\\r\n                            ((__PLLR__) << RCC_PLLCFGR_PLLR_Pos)))\r\n#else\r\n/** @brief  Macro to configure the main PLL clock source, multiplication and division factors.\r\n  * @note   This function must be used only when the main PLL is disabled.\r\n  * @param  __RCC_PLLSource__ specifies the PLL entry clock source.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry\r\n  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry\r\n  * @note   This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.\r\n  * @param  __PLLM__ specifies the division factor for PLL VCO input clock\r\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.\r\n  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input\r\n  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency\r\n  *         of 2 MHz to limit PLL jitter.\r\n  * @param  __PLLN__ specifies the multiplication factor for PLL VCO output clock\r\n  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.\r\n  * @note   You have to set the PLLN parameter correctly to ensure that the VCO\r\n  *         output frequency is between 100 and 432 MHz.\r\n  * @param  __PLLP__ specifies the division factor for main system clock (SYSCLK)\r\n  *         This parameter must be a number in the range {2, 4, 6, or 8}.\r\n  * @note   You have to set the PLLP parameter correctly to not exceed 216 MHz on\r\n  *         the System clock frequency.\r\n  * @param  __PLLQ__ specifies the division factor for OTG FS, SDMMC and RNG clocks\r\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.\r\n  * @note   If the USB OTG FS is used in your application, you have to set the\r\n  *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,\r\n  *         the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work\r\n  *         correctly.\r\n  */\r\n#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)     \\\r\n                            (RCC->PLLCFGR = (0x20000000 | (__RCC_PLLSource__) | (__PLLM__)| \\\r\n                            ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos)                          | \\\r\n                            ((((__PLLP__) >> 1) -1) << RCC_PLLCFGR_PLLP_Pos)              | \\\r\n                            ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos)))\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n/*---------------------------------------------------------------------------------------------*/\r\n\r\n/** @brief  Macro to configure the Timers clocks prescalers\r\n  * @param  __PRESC__  specifies the Timers clocks prescalers selection\r\n  *         This parameter can be one of the following values:\r\n  *            @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is\r\n  *                 equal to HPRE if PPREx is corresponding to division by 1 or 2,\r\n  *                 else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to\r\n  *                 division by 4 or more.\r\n  *            @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is\r\n  *                 equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,\r\n  *                 else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding\r\n  *                 to division by 8 or more.\r\n  */\r\n#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\\\r\n                                                 RCC->DCKCFGR1 |= (__PRESC__);           \\\r\n                                                }while(0)\r\n\r\n/** @brief Macros to Enable or Disable the PLLISAI.\r\n  * @note  The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.\r\n  */\r\n#define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR |= (RCC_CR_PLLSAION))\r\n#define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION))\r\n\r\n#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)\r\n/** @brief  Macro to configure the PLLSAI clock multiplication and division factors.\r\n  * @note   This function must be used only when the PLLSAI is disabled.\r\n  * @note   PLLSAI clock source is common with the main PLL (configured in\r\n  *         RCC_PLLConfig function )\r\n  * @param  __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.\r\n  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.\r\n  * @note   You have to set the PLLSAIN parameter correctly to ensure that the VCO\r\n  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.\r\n  * @param  __PLLSAIP__ specifies the division factor for USB, RNG, SDMMC clocks\r\n  *         This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider.\r\n  * @param  __PLLSAIQ__ specifies the division factor for SAI clock\r\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.\r\n  */\r\n#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__)                        \\\r\n                               (RCC->PLLSAICFGR = ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\\\r\n                               ((__PLLSAIP__) << RCC_PLLSAICFGR_PLLSAIP_Pos)                    |\\\r\n                               ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos))\r\n\r\n/** @brief  Macro to configure the PLLI2S clock multiplication and division factors.\r\n  * @note   This macro must be used only when the PLLI2S is disabled.\r\n  * @note   PLLI2S clock source is common with the main PLL (configured in\r\n  *         HAL_RCC_ClockConfig() API)\r\n  * @param  __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock.\r\n  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.\r\n  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO\r\n  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.\r\n  * @param  __PLLI2SQ__ specifies the division factor for SAI clock.\r\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.\r\n  * @param  __PLLI2SR__ specifies the division factor for I2S clock\r\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.\r\n  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz\r\n  *         on the I2S clock frequency.\r\n  */\r\n#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__)                        \\\r\n                               (RCC->PLLI2SCFGR = ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\\\r\n                               ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos)                    |\\\r\n                               ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))\r\n#else\r\n/** @brief  Macro to configure the PLLSAI clock multiplication and division factors.\r\n  * @note   This function must be used only when the PLLSAI is disabled.\r\n  * @note   PLLSAI clock source is common with the main PLL (configured in\r\n  *         RCC_PLLConfig function )\r\n  * @param  __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.\r\n  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.\r\n  * @note   You have to set the PLLSAIN parameter correctly to ensure that the VCO\r\n  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.\r\n  * @param  __PLLSAIP__ specifies the division factor for USB, RNG, SDMMC clocks\r\n  *         This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider.\r\n  * @param  __PLLSAIQ__ specifies the division factor for SAI clock\r\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.\r\n  * @param  __PLLSAIR__ specifies the division factor for LTDC clock\r\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.\r\n  */\r\n#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__)              \\\r\n                               (RCC->PLLSAICFGR = ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\\\r\n                               ((__PLLSAIP__) << RCC_PLLSAICFGR_PLLSAIP_Pos)                    |\\\r\n                               ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos)                    |\\\r\n                               ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos))\r\n\r\n/** @brief  Macro to configure the PLLI2S clock multiplication and division factors.\r\n  * @note   This macro must be used only when the PLLI2S is disabled.\r\n  * @note   PLLI2S clock source is common with the main PLL (configured in\r\n  *         HAL_RCC_ClockConfig() API)\r\n  * @param  __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock.\r\n  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.\r\n  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO\r\n  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.\r\n  * @param  __PLLI2SP__ specifies the division factor for SPDDIF-RX clock.\r\n  *         This parameter can be a value of @ref RCCEx_PLLI2SP_Clock_Divider.\r\n  * @param  __PLLI2SQ__ specifies the division factor for SAI clock.\r\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.\r\n  * @param  __PLLI2SR__ specifies the division factor for I2S clock\r\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.\r\n  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz\r\n  *         on the I2S clock frequency.\r\n  */\r\n#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__)              \\\r\n                               (RCC->PLLI2SCFGR = ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\\\r\n                               ((__PLLI2SP__) << RCC_PLLI2SCFGR_PLLI2SP_Pos)                    |\\\r\n                               ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos)                    |\\\r\n                               ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))\r\n#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */\r\n\r\n/** @brief  Macro to configure the SAI clock Divider coming from PLLI2S.\r\n  * @note   This function must be called before enabling the PLLI2S.\r\n  * @param  __PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock .\r\n  *          This parameter must be a number between 1 and 32.\r\n  *          SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__\r\n  */\r\n#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))\r\n\r\n/** @brief  Macro to configure the SAI clock Divider coming from PLLSAI.\r\n  * @note   This function must be called before enabling the PLLSAI.\r\n  * @param  __PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock .\r\n  *         This parameter must be a number between Min_Data = 1 and Max_Data = 32.\r\n  *         SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__\r\n  */\r\n#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))\r\n\r\n#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\\\r\n    defined (STM32F750xx)\r\n/** @brief  Macro to configure the LTDC clock Divider coming from PLLSAI.\r\n  * @note   This function must be called before enabling the PLLSAI.\r\n  * @param  __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock .\r\n  *          This parameter can be a value of @ref RCCEx_PLLSAI_DIVR.\r\n  *          LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__\r\n  */\r\n#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\\\r\n                            MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__))\r\n#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n\r\n/** @brief  Macro to configure SAI1 clock source selection.\r\n  * @note   This function must be called before enabling PLLSAI, PLLI2S and\r\n  *         the SAI clock.\r\n  * @param  __SOURCE__ specifies the SAI1 clock source.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used\r\n  *                                           as SAI1 clock.\r\n  *            @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used\r\n  *                                           as SAI1 clock.\r\n  *            @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin\r\n  *                                        used as SAI1 clock.\r\n  *            @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock\r\n  *                                           used as SAI1 clock.\r\n  * @note      The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices\r\n  */\r\n#define __HAL_RCC_SAI1_CONFIG(__SOURCE__)\\\r\n                             MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__))\r\n\r\n/** @brief  Macro to get the SAI1 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used\r\n  *                                           as SAI1 clock.\r\n  *            @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used\r\n  *                                           as SAI1 clock.\r\n  *            @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin\r\n  *                                        used as SAI1 clock.\r\n  *            @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock\r\n  *                                           used as SAI1 clock.\r\n  * @note      The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices\r\n  */\r\n#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL)))\r\n\r\n/** @brief  Macro to configure SAI2 clock source selection.\r\n  * @note   This function must be called before enabling PLLSAI, PLLI2S and\r\n  *         the SAI clock.\r\n  * @param  __SOURCE__ specifies the SAI2 clock source.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used\r\n  *                                           as SAI2 clock.\r\n  *            @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used\r\n  *                                           as SAI2 clock.\r\n  *            @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin\r\n  *                                        used as SAI2 clock.\r\n  *            @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock\r\n  *                                           used as SAI2 clock.\r\n  * @note      The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices\r\n  */\r\n#define __HAL_RCC_SAI2_CONFIG(__SOURCE__)\\\r\n                            MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__))\r\n\r\n\r\n/** @brief  Macro to get the SAI2 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used\r\n  *                                           as SAI2 clock.\r\n  *            @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used\r\n  *                                           as SAI2 clock.\r\n  *            @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin\r\n  *                                        used as SAI2 clock.\r\n  *            @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock\r\n  *                                           used as SAI2 clock.\r\n  * @note      The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices\r\n  */\r\n#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL)))\r\n\r\n\r\n/** @brief Enable PLLSAI_RDY interrupt.\r\n  */\r\n#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))\r\n\r\n/** @brief Disable PLLSAI_RDY interrupt.\r\n  */\r\n#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))\r\n\r\n/** @brief Clear the PLLSAI RDY interrupt pending bits.\r\n  */\r\n#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))\r\n\r\n/** @brief Check the PLLSAI RDY interrupt has occurred or not.\r\n  * @retval The new state (TRUE or FALSE).\r\n  */\r\n#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))\r\n\r\n/** @brief  Check PLLSAI RDY flag is set or not.\r\n  * @retval The new state (TRUE or FALSE).\r\n  */\r\n#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))\r\n\r\n/** @brief  Macro to Get I2S clock source selection.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.\r\n  *            @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source\r\n  */\r\n#define __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))\r\n\r\n/** @brief  Macro to configure the I2C1 clock (I2C1CLK).\r\n  *\r\n  * @param  __I2C1_CLKSOURCE__ specifies the I2C1 clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock\r\n  *            @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock\r\n  *            @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock\r\n  */\r\n#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))\r\n\r\n/** @brief  Macro to get the I2C1 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock\r\n  *            @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock\r\n  *            @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock\r\n  */\r\n#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL)))\r\n\r\n/** @brief  Macro to configure the I2C2 clock (I2C2CLK).\r\n  *\r\n  * @param  __I2C2_CLKSOURCE__ specifies the I2C2 clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock\r\n  *            @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock\r\n  *            @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock\r\n  */\r\n#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))\r\n\r\n/** @brief  Macro to get the I2C2 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock\r\n  *            @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock\r\n  *            @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock\r\n  */\r\n#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL)))\r\n\r\n/** @brief  Macro to configure the I2C3 clock (I2C3CLK).\r\n  *\r\n  * @param  __I2C3_CLKSOURCE__ specifies the I2C3 clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock\r\n  *            @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock\r\n  *            @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock\r\n  */\r\n#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))\r\n\r\n/** @brief  macro to get the I2C3 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock\r\n  *            @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock\r\n  *            @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock\r\n  */\r\n#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL)))\r\n\r\n/** @brief  Macro to configure the I2C4 clock (I2C4CLK).\r\n  *\r\n  * @param  __I2C4_CLKSOURCE__ specifies the I2C4 clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock\r\n  *            @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock\r\n  *            @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock\r\n  */\r\n#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__))\r\n\r\n/** @brief  macro to get the I2C4 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock\r\n  *            @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock\r\n  *            @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock\r\n  */\r\n#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL)))\r\n\r\n/** @brief  Macro to configure the USART1 clock (USART1CLK).\r\n  *\r\n  * @param  __USART1_CLKSOURCE__ specifies the USART1 clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock\r\n  *            @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock\r\n  *            @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock\r\n  *            @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock\r\n  */\r\n#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))\r\n\r\n/** @brief  macro to get the USART1 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock\r\n  *            @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock\r\n  *            @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock\r\n  *            @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock\r\n  */\r\n#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL)))\r\n\r\n/** @brief  Macro to configure the USART2 clock (USART2CLK).\r\n  *\r\n  * @param  __USART2_CLKSOURCE__ specifies the USART2 clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock\r\n  *            @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock\r\n  *            @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock\r\n  *            @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock\r\n  */\r\n#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))\r\n\r\n/** @brief  macro to get the USART2 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock\r\n  *            @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock\r\n  *            @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock\r\n  *            @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock\r\n  */\r\n#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL)))\r\n\r\n/** @brief  Macro to configure the USART3 clock (USART3CLK).\r\n  *\r\n  * @param  __USART3_CLKSOURCE__ specifies the USART3 clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock\r\n  *            @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock\r\n  *            @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock\r\n  *            @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock\r\n  */\r\n#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))\r\n\r\n/** @brief  macro to get the USART3 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock\r\n  *            @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock\r\n  *            @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock\r\n  *            @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock\r\n  */\r\n#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL)))\r\n\r\n /** @brief  Macro to configure the UART4 clock (UART4CLK).\r\n  *\r\n  * @param  __UART4_CLKSOURCE__ specifies the UART4 clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock\r\n  *            @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock\r\n  *            @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock\r\n  *            @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock\r\n  */\r\n#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))\r\n\r\n/** @brief  macro to get the UART4 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock\r\n  *            @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock\r\n  *            @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock\r\n  *            @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock\r\n  */\r\n#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL)))\r\n\r\n /** @brief  Macro to configure the UART5 clock (UART5CLK).\r\n  *\r\n  * @param  __UART5_CLKSOURCE__ specifies the UART5 clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock\r\n  *            @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock\r\n  *            @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock\r\n  *            @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock\r\n  */\r\n#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))\r\n\r\n/** @brief  macro to get the UART5 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock\r\n  *            @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock\r\n  *            @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock\r\n  *            @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock\r\n  */\r\n#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL)))\r\n\r\n /** @brief  Macro to configure the USART6 clock (USART6CLK).\r\n  *\r\n  * @param  __USART6_CLKSOURCE__ specifies the USART6 clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock\r\n  *            @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock\r\n  *            @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock\r\n  *            @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock\r\n  */\r\n#define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__))\r\n\r\n/** @brief  macro to get the USART6 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock\r\n  *            @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock\r\n  *            @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock\r\n  *            @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock\r\n  */\r\n#define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL)))\r\n\r\n /** @brief  Macro to configure the UART7 clock (UART7CLK).\r\n  *\r\n  * @param  __UART7_CLKSOURCE__ specifies the UART7 clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock\r\n  *            @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock\r\n  *            @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock\r\n  *            @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock\r\n  */\r\n#define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__))\r\n\r\n/** @brief  macro to get the UART7 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock\r\n  *            @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock\r\n  *            @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock\r\n  *            @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock\r\n  */\r\n#define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL)))\r\n\r\n/** @brief  Macro to configure the UART8 clock (UART8CLK).\r\n  *\r\n  * @param  __UART8_CLKSOURCE__ specifies the UART8 clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock\r\n  *            @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock\r\n  *            @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock\r\n  *            @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock\r\n  */\r\n#define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__))\r\n\r\n/** @brief  macro to get the UART8 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock\r\n  *            @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock\r\n  *            @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock\r\n  *            @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock\r\n  */\r\n#define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL)))\r\n\r\n/** @brief  Macro to configure the LPTIM1 clock (LPTIM1CLK).\r\n  *\r\n  * @param  __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock\r\n  *            @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock\r\n  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock\r\n  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock\r\n  */\r\n#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))\r\n\r\n/** @brief  macro to get the LPTIM1 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock\r\n  *            @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock\r\n  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock\r\n  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock\r\n  */\r\n#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)))\r\n\r\n/** @brief  Macro to configure the CEC clock (CECCLK).\r\n  *\r\n  * @param  __CEC_CLKSOURCE__ specifies the CEC clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock\r\n  *            @arg RCC_CECCLKSOURCE_HSI: HSI divided by 488 selected as CEC clock\r\n  */\r\n#define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__))\r\n\r\n/** @brief  macro to get the CEC clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock\r\n  *            @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock\r\n  */\r\n#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)))\r\n\r\n/** @brief  Macro to configure the CLK48 source (CLK48CLK).\r\n  *\r\n  * @param  __CLK48_SOURCE__ specifies the CLK48 clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source\r\n  *            @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP selected as CLK48 source\r\n  */\r\n#define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__))\r\n\r\n/** @brief  macro to get the CLK48 source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_CLK48SOURCE_PLL: PLL used as CLK48 source\r\n  *            @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP used as CLK48 source\r\n  */\r\n#define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)))\r\n\r\n/** @brief  Macro to configure the SDMMC1 clock (SDMMC1CLK).\r\n  *\r\n  * @param  __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC clock\r\n  *            @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC clock\r\n  */\r\n#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))\r\n\r\n/** @brief  macro to get the SDMMC1 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC1 clock\r\n  *            @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC1 clock\r\n  */\r\n#define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL)))\r\n\r\n#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)\r\n/** @brief  Macro to configure the SDMMC2 clock (SDMMC2CLK).\r\n  * @param  __SDMMC2_CLKSOURCE__ specifies the SDMMC2 clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock\r\n  *            @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock\r\n  */\r\n#define __HAL_RCC_SDMMC2_CONFIG(__SDMMC2_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL, (uint32_t)(__SDMMC2_CLKSOURCE__))\r\n\r\n/** @brief  macro to get the SDMMC2 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock\r\n  *            @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock\r\n  */\r\n#define __HAL_RCC_GET_SDMMC2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL)))\r\n#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx  || STM32F730xx */\r\n\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n/** @brief  Macro to configure the DFSDM1 clock\r\n  * @param  __DFSDM1_CLKSOURCE__ specifies the DFSDM1  clock source.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 Clock selected as DFSDM clock\r\n  *            @arg RCC_DFSDMCLKSOURCE_SYSCLK: System Clock selected as DFSDM clock\r\n  */\r\n#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__))\r\n\r\n/** @brief  Macro to get the DFSDM1 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_DFSDM1CLKSOURCE_PCLK2:  PCLK2 Clock selected as DFSDM1 clock\r\n  *            @arg RCC_DFSDM1CLKSOURCE_SYSCLK:   System Clock selected as DFSDM1 clock\r\n  */\r\n#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL)))\r\n\r\n/** @brief  Macro to configure the DFSDM1 Audio clock\r\n  * @param  __DFSDM1AUDIO_CLKSOURCE__ specifies the DFSDM1 Audio clock source.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1:  SAI1 Clock selected as DFSDM1 Audio clock\r\n  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2:  SAI2 Clock selected as DFSDM1 Audio clock\r\n  */\r\n#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, (uint32_t)(__DFSDM1AUDIO_CLKSOURCE__))\r\n\r\n/** @brief  Macro to get the DFSDM1 Audio clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1:  SAI1 Clock selected as DFSDM1 Audio clock\r\n  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2:  SAI2 Clock selected as DFSDM1 Audio clock\r\n  */\r\n#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL)))\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n#if defined (STM32F769xx) || defined (STM32F779xx)\r\n/** @brief  Macro to configure the DSI clock.\r\n  * @param  __DSI_CLKSOURCE__ specifies the DSI clock source.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.\r\n  *            @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.\r\n  */\r\n#define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, (uint32_t)(__DSI_CLKSOURCE__)))\r\n\r\n/** @brief  Macro to Get the DSI clock.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.\r\n  *            @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.\r\n  */\r\n#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL))\r\n#endif /* STM32F769xx || STM32F779xx */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup RCCEx_Exported_Functions_Group1\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);\r\nvoid HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);\r\nuint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);\r\nHAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef  *PLLI2SInit);\r\nHAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void);\r\nHAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef  *PLLSAIInit);\r\nHAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void);\r\n/**\r\n  * @}\r\n  */\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros\r\n  * @{\r\n  */\r\n/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters\r\n  * @{\r\n  */\r\n#if defined(STM32F756xx) || defined(STM32F746xx) || defined(STM32F750xx)\r\n#define IS_RCC_PERIPHCLOCK(SELECTION)  \\\r\n               ((((SELECTION) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_LTDC)        == RCC_PERIPHCLK_LTDC)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_TIM)         == RCC_PERIPHCLK_TIM)     || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART6)      == RCC_PERIPHCLK_USART6)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART7)       == RCC_PERIPHCLK_UART7)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART8)       == RCC_PERIPHCLK_UART8)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_I2C4)        == RCC_PERIPHCLK_I2C4)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SAI2)        == RCC_PERIPHCLK_SAI2)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_CLK48)       == RCC_PERIPHCLK_CLK48)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_CEC)         == RCC_PERIPHCLK_CEC)     || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SDMMC1)      == RCC_PERIPHCLK_SDMMC1)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SPDIFRX)     == RCC_PERIPHCLK_SPDIFRX) || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC))\r\n#elif defined(STM32F745xx)\r\n#define IS_RCC_PERIPHCLOCK(SELECTION)  \\\r\n               ((((SELECTION) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_TIM)         == RCC_PERIPHCLK_TIM)     || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART6)      == RCC_PERIPHCLK_USART6)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART7)       == RCC_PERIPHCLK_UART7)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART8)       == RCC_PERIPHCLK_UART8)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_I2C4)        == RCC_PERIPHCLK_I2C4)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SAI2)        == RCC_PERIPHCLK_SAI2)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_CLK48)       == RCC_PERIPHCLK_CLK48)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_CEC)         == RCC_PERIPHCLK_CEC)     || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SDMMC1)      == RCC_PERIPHCLK_SDMMC1)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SPDIFRX)     == RCC_PERIPHCLK_SPDIFRX) || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC))\r\n#elif defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define IS_RCC_PERIPHCLOCK(SELECTION)  \\\r\n               ((((SELECTION) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_LTDC)        == RCC_PERIPHCLK_LTDC)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_TIM)         == RCC_PERIPHCLK_TIM)     || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART6)      == RCC_PERIPHCLK_USART6)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART7)       == RCC_PERIPHCLK_UART7)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART8)       == RCC_PERIPHCLK_UART8)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_I2C4)        == RCC_PERIPHCLK_I2C4)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SAI2)        == RCC_PERIPHCLK_SAI2)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_CLK48)       == RCC_PERIPHCLK_CLK48)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_CEC)         == RCC_PERIPHCLK_CEC)     || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SDMMC1)      == RCC_PERIPHCLK_SDMMC1)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SDMMC2)      == RCC_PERIPHCLK_SDMMC2)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_DFSDM1)       == RCC_PERIPHCLK_DFSDM1)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SPDIFRX)     == RCC_PERIPHCLK_SPDIFRX) || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC))\r\n#elif defined (STM32F765xx)\r\n#define IS_RCC_PERIPHCLOCK(SELECTION)  \\\r\n               ((((SELECTION) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_TIM)         == RCC_PERIPHCLK_TIM)     || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART6)      == RCC_PERIPHCLK_USART6)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART7)       == RCC_PERIPHCLK_UART7)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART8)       == RCC_PERIPHCLK_UART8)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_I2C4)        == RCC_PERIPHCLK_I2C4)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SAI2)        == RCC_PERIPHCLK_SAI2)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_CLK48)       == RCC_PERIPHCLK_CLK48)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_CEC)         == RCC_PERIPHCLK_CEC)     || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SDMMC1)      == RCC_PERIPHCLK_SDMMC1)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SDMMC2)      == RCC_PERIPHCLK_SDMMC2)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_DFSDM1)       == RCC_PERIPHCLK_DFSDM1)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SPDIFRX)     == RCC_PERIPHCLK_SPDIFRX) || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC))\r\n#elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)\r\n#define IS_RCC_PERIPHCLOCK(SELECTION)  \\\r\n               ((((SELECTION) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_TIM)         == RCC_PERIPHCLK_TIM)     || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART6)      == RCC_PERIPHCLK_USART6)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART7)       == RCC_PERIPHCLK_UART7)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART8)       == RCC_PERIPHCLK_UART8)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SAI2)        == RCC_PERIPHCLK_SAI2)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_CLK48)       == RCC_PERIPHCLK_CLK48)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SDMMC1)      == RCC_PERIPHCLK_SDMMC1)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SDMMC2)      == RCC_PERIPHCLK_SDMMC2)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC))\r\n#endif /* STM32F746xx || STM32F756xx || STM32F750xx */\r\n#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))\r\n#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \\\r\n    defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r\n#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\\\r\n                                     ((VALUE) == RCC_PLLI2SP_DIV4) ||\\\r\n                                     ((VALUE) == RCC_PLLI2SP_DIV6) ||\\\r\n                                     ((VALUE) == RCC_PLLI2SP_DIV8))\r\n#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))\r\n#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))\r\n\r\n#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))\r\n#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\\\r\n                                     ((VALUE) == RCC_PLLSAIP_DIV4) ||\\\r\n                                     ((VALUE) == RCC_PLLSAIP_DIV6) ||\\\r\n                                     ((VALUE) == RCC_PLLSAIP_DIV8))\r\n#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))\r\n#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))\r\n\r\n#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))\r\n\r\n#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))\r\n\r\n#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\\\r\n                                         ((VALUE) == RCC_PLLSAIDIVR_4) ||\\\r\n                                         ((VALUE) == RCC_PLLSAIDIVR_8) ||\\\r\n                                         ((VALUE) == RCC_PLLSAIDIVR_16))\r\n#define IS_RCC_I2SCLKSOURCE(SOURCE)  (((SOURCE) == RCC_I2SCLKSOURCE_PLLI2S) || \\\r\n                                      ((SOURCE) == RCC_I2SCLKSOURCE_EXT))\r\n\r\n#define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) || \\\r\n                                        ((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48))\r\n\r\n#define IS_RCC_CECCLKSOURCE(SOURCE)  (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \\\r\n                                      ((SOURCE) == RCC_CECCLKSOURCE_LSE))\r\n#define IS_RCC_USART1CLKSOURCE(SOURCE)  \\\r\n               (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2)  || \\\r\n                ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \\\r\n                ((SOURCE) == RCC_USART1CLKSOURCE_LSE)    || \\\r\n                ((SOURCE) == RCC_USART1CLKSOURCE_HSI))\r\n\r\n#define IS_RCC_USART2CLKSOURCE(SOURCE)  \\\r\n               (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1)  || \\\r\n                ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \\\r\n                ((SOURCE) == RCC_USART2CLKSOURCE_LSE)    || \\\r\n                ((SOURCE) == RCC_USART2CLKSOURCE_HSI))\r\n#define IS_RCC_USART3CLKSOURCE(SOURCE)  \\\r\n               (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1)  || \\\r\n                ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \\\r\n                ((SOURCE) == RCC_USART3CLKSOURCE_LSE)    || \\\r\n                ((SOURCE) == RCC_USART3CLKSOURCE_HSI))\r\n\r\n#define IS_RCC_UART4CLKSOURCE(SOURCE)  \\\r\n               (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1)  || \\\r\n                ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \\\r\n                ((SOURCE) == RCC_UART4CLKSOURCE_LSE)    || \\\r\n                ((SOURCE) == RCC_UART4CLKSOURCE_HSI))\r\n\r\n#define IS_RCC_UART5CLKSOURCE(SOURCE)  \\\r\n               (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1)  || \\\r\n                ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \\\r\n                ((SOURCE) == RCC_UART5CLKSOURCE_LSE)    || \\\r\n                ((SOURCE) == RCC_UART5CLKSOURCE_HSI))\r\n\r\n#define IS_RCC_USART6CLKSOURCE(SOURCE)  \\\r\n               (((SOURCE) == RCC_USART6CLKSOURCE_PCLK2)  || \\\r\n                ((SOURCE) == RCC_USART6CLKSOURCE_SYSCLK) || \\\r\n                ((SOURCE) == RCC_USART6CLKSOURCE_LSE)    || \\\r\n                ((SOURCE) == RCC_USART6CLKSOURCE_HSI))\r\n\r\n#define IS_RCC_UART7CLKSOURCE(SOURCE)  \\\r\n               (((SOURCE) == RCC_UART7CLKSOURCE_PCLK1)  || \\\r\n                ((SOURCE) == RCC_UART7CLKSOURCE_SYSCLK) || \\\r\n                ((SOURCE) == RCC_UART7CLKSOURCE_LSE)    || \\\r\n                ((SOURCE) == RCC_UART7CLKSOURCE_HSI))\r\n\r\n#define IS_RCC_UART8CLKSOURCE(SOURCE)  \\\r\n               (((SOURCE) == RCC_UART8CLKSOURCE_PCLK1)  || \\\r\n                ((SOURCE) == RCC_UART8CLKSOURCE_SYSCLK) || \\\r\n                ((SOURCE) == RCC_UART8CLKSOURCE_LSE)    || \\\r\n                ((SOURCE) == RCC_UART8CLKSOURCE_HSI))\r\n#define IS_RCC_I2C1CLKSOURCE(SOURCE)   \\\r\n               (((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) || \\\r\n                ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)|| \\\r\n                ((SOURCE) == RCC_I2C1CLKSOURCE_HSI))\r\n#define IS_RCC_I2C2CLKSOURCE(SOURCE)   \\\r\n               (((SOURCE) == RCC_I2C2CLKSOURCE_PCLK1) || \\\r\n                ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)|| \\\r\n                ((SOURCE) == RCC_I2C2CLKSOURCE_HSI))\r\n\r\n#define IS_RCC_I2C3CLKSOURCE(SOURCE)   \\\r\n               (((SOURCE) == RCC_I2C3CLKSOURCE_PCLK1) || \\\r\n                ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)|| \\\r\n                ((SOURCE) == RCC_I2C3CLKSOURCE_HSI))\r\n#define IS_RCC_I2C4CLKSOURCE(SOURCE)   \\\r\n               (((SOURCE) == RCC_I2C4CLKSOURCE_PCLK1) || \\\r\n                ((SOURCE) == RCC_I2C4CLKSOURCE_SYSCLK)|| \\\r\n                ((SOURCE) == RCC_I2C4CLKSOURCE_HSI))\r\n#define IS_RCC_LPTIM1CLK(SOURCE)  \\\r\n               (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) || \\\r\n                ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI)  || \\\r\n                ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI)  || \\\r\n                ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))\r\n#define IS_RCC_CLK48SOURCE(SOURCE)  \\\r\n               (((SOURCE) == RCC_CLK48SOURCE_PLLSAIP) || \\\r\n                ((SOURCE) == RCC_CLK48SOURCE_PLL))\r\n#define IS_RCC_TIMPRES(VALUE)  \\\r\n               (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \\\r\n                ((VALUE) == RCC_TIMPRES_ACTIVATED))\r\n\r\n#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F745xx) ||\\\r\n    defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F730xx) || defined (STM32F750xx)\r\n#define IS_RCC_SAI1CLKSOURCE(SOURCE)  (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \\\r\n                                       ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \\\r\n                                       ((SOURCE) == RCC_SAI1CLKSOURCE_PIN))\r\n#define IS_RCC_SAI2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \\\r\n                                       ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \\\r\n                                       ((SOURCE) == RCC_SAI2CLKSOURCE_PIN))\r\n#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F745xx || STM32F746xx || STM32F756xx || STM32F750xx || STM32F730xx */\r\n\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define IS_RCC_PLLR_VALUE(VALUE)            ((2 <= (VALUE)) && ((VALUE) <= 7))\r\n\r\n#define IS_RCC_SAI1CLKSOURCE(SOURCE)  (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \\\r\n                                       ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \\\r\n                                       ((SOURCE) == RCC_SAI1CLKSOURCE_PIN)    || \\\r\n                                       ((SOURCE) == RCC_SAI1CLKSOURCE_PLLSRC))\r\n\r\n#define IS_RCC_SAI2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \\\r\n                                       ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \\\r\n                                       ((SOURCE) == RCC_SAI2CLKSOURCE_PIN)    || \\\r\n                                       ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))\r\n\r\n#define IS_RCC_DFSDM1CLKSOURCE(SOURCE)  (((SOURCE) == RCC_DFSDM1CLKSOURCE_PCLK2) || \\\r\n                                        ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYSCLK))\r\n\r\n#define IS_RCC_DFSDM1AUDIOCLKSOURCE(SOURCE)  (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \\\r\n                                             ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI2))\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx)\r\n#define IS_RCC_SDMMC2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_SDMMC2CLKSOURCE_SYSCLK) || \\\r\n                                         ((SOURCE) == RCC_SDMMC2CLKSOURCE_CLK48))\r\n#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */\r\n\r\n#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR)  ||\\\r\n                                             ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY))\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_RCC_EX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rng.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_rng.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of RNG HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_RNG_H\r\n#define __STM32F7xx_HAL_RNG_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup RNG RNG\r\n  * @brief RNG HAL module driver\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/ \r\n\r\n/** @defgroup RNG_Exported_Types RNG Exported Types\r\n  * @{\r\n  */\r\n\r\n/** @defgroup RNG_Exported_Types_Group1 RNG State Structure definition \r\n  * @{\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_RNG_STATE_RESET     = 0x00U,  /*!< RNG not yet initialized or disabled */\r\n  HAL_RNG_STATE_READY     = 0x01U,  /*!< RNG initialized and ready for use   */\r\n  HAL_RNG_STATE_BUSY      = 0x02U,  /*!< RNG internal process is ongoing     */ \r\n  HAL_RNG_STATE_TIMEOUT   = 0x03U,  /*!< RNG timeout state                   */\r\n  HAL_RNG_STATE_ERROR     = 0x04U   /*!< RNG error state                     */\r\n    \r\n}HAL_RNG_StateTypeDef;\r\n\r\n/** \r\n  * @}\r\n  */\r\n\r\n/** @defgroup RNG_Exported_Types_Group2 RNG Handle Structure definition   \r\n  * @{\r\n  */ \r\ntypedef struct\r\n{\r\n  RNG_TypeDef                 *Instance;    /*!< Register base address   */\r\n\r\n  uint32_t                    RandomNumber; /*!< Last Generated random number */\t\r\n  \r\n  HAL_LockTypeDef             Lock;         /*!< RNG locking object      */\r\n  \r\n  __IO HAL_RNG_StateTypeDef   State;        /*!< RNG communication state */\r\n  \r\n}RNG_HandleTypeDef;\r\n\r\n/** \r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n   \r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup RNG_Exported_Constants RNG Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition\r\n  * @{\r\n  */\r\n#define RNG_IT_DRDY  RNG_SR_DRDY  /*!< Data Ready interrupt  */\r\n#define RNG_IT_CEI   RNG_SR_CEIS  /*!< Clock error interrupt */\r\n#define RNG_IT_SEI   RNG_SR_SEIS  /*!< Seed error interrupt  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition\r\n  * @{\r\n  */\r\n#define RNG_FLAG_DRDY   RNG_SR_DRDY  /*!< Data ready                 */\r\n#define RNG_FLAG_CECS   RNG_SR_CECS  /*!< Clock error current status */\r\n#define RNG_FLAG_SECS   RNG_SR_SECS  /*!< Seed error current status  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/* Exported macros -----------------------------------------------------------*/\r\n\r\n/** @defgroup RNG_Exported_Macros RNG Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief Reset RNG handle state\r\n  * @param  __HANDLE__ RNG Handle\r\n  * @retval None\r\n  */\r\n#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)\r\n\r\n/**\r\n  * @brief  Enables the RNG peripheral.\r\n  * @param  __HANDLE__ RNG Handle\r\n  * @retval None\r\n  */\r\n#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_RNGEN)\r\n\r\n/**\r\n  * @brief  Disables the RNG peripheral.\r\n  * @param  __HANDLE__ RNG Handle\r\n  * @retval None\r\n  */\r\n#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)\r\n\r\n/**\r\n  * @brief  Check the selected RNG flag status.\r\n  * @param  __HANDLE__ RNG Handle\r\n  * @param  __FLAG__ RNG flag\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RNG_FLAG_DRDY: Data ready                \r\n  *            @arg RNG_FLAG_CECS: Clock error current status\r\n  *            @arg RNG_FLAG_SECS: Seed error current status \r\n  * @retval The new state of __FLAG__ (SET or RESET).\r\n  */\r\n#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))\r\n\r\n/**\r\n  * @brief  Clears the selected RNG flag status.\r\n  * @param  __HANDLE__ RNG handle\r\n  * @param  __FLAG__ RNG flag to clear  \r\n  * @note   WARNING: This is a dummy macro for HAL code alignment,\r\n  *         flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.\r\n  * @retval None\r\n  */\r\n#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__)                      /* dummy  macro */\r\n\r\n\r\n\r\n/**\r\n  * @brief  Enables the RNG interrupts.\r\n  * @param  __HANDLE__ RNG Handle\r\n  * @retval None\r\n  */\r\n#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_IE)\r\n    \r\n/**\r\n  * @brief  Disables the RNG interrupts.\r\n  * @param  __HANDLE__ RNG Handle\r\n  * @retval None\r\n  */\r\n#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)\r\n\r\n/**\r\n  * @brief  Checks whether the specified RNG interrupt has occurred or not.\r\n  * @param  __HANDLE__ RNG Handle\r\n  * @param  __INTERRUPT__ specifies the RNG interrupt status flag to check.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg RNG_IT_DRDY: Data ready interrupt              \r\n  *            @arg RNG_IT_CEI: Clock error interrupt\r\n  *            @arg RNG_IT_SEI: Seed error interrupt\r\n  * @retval The new state of __INTERRUPT__ (SET or RESET).\r\n  */\r\n#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))   \r\n\r\n/**\r\n  * @brief  Clear the RNG interrupt status flags.\r\n  * @param  __HANDLE__ RNG Handle\r\n  * @param  __INTERRUPT__ specifies the RNG interrupt status flag to clear.\r\n  *          This parameter can be one of the following values:            \r\n  *            @arg RNG_IT_CEI: Clock error interrupt\r\n  *            @arg RNG_IT_SEI: Seed error interrupt\r\n  * @note   RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.          \r\n  * @retval None\r\n  */\r\n#define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup RNG_Exported_Functions RNG Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup RNG_Exported_Functions_Group1 Initialization and de-initialization functions\r\n  * @{\r\n  */  \r\nHAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);\r\nHAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng);\r\nvoid HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);\r\nvoid HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions\r\n  * @{\r\n  */\r\nuint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng);    /* Obsolete, use HAL_RNG_GenerateRandomNumber() instead    */\r\nuint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */\r\n\r\nHAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);\r\nHAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);\r\nuint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);\r\n\r\nvoid HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);\r\nvoid HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);\r\nvoid HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef* hrng, uint32_t random32bit);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions\r\n  * @{\r\n  */\r\nHAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/** @defgroup RNG_Private_Types RNG Private Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private defines -----------------------------------------------------------*/\r\n/** @defgroup RNG_Private_Defines RNG Private Defines\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n          \r\n/* Private variables ---------------------------------------------------------*/\r\n/** @defgroup RNG_Private_Variables RNG Private Variables\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup RNG_Private_Constants RNG Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup RNG_Private_Macros RNG Private Macros\r\n  * @{\r\n  */\r\n#define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \\\r\n                       ((IT) == RNG_IT_SEI))\r\n\r\n#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \\\r\n                           ((FLAG) == RNG_FLAG_CECS) || \\\r\n                           ((FLAG) == RNG_FLAG_SECS))\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private functions prototypes ----------------------------------------------*/\r\n/** @defgroup RNG_Private_Functions_Prototypes RNG Private Functions Prototypes\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup RNG_Private_Functions RNG Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_RNG_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_rtc.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of RTC HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_RTC_H\r\n#define __STM32F7xx_HAL_RTC_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup RTC\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup RTC_Exported_Types RTC Exported Types\r\n  * @{\r\n  */\r\n\r\n/** \r\n  * @brief  HAL State structures definition  \r\n  */ \r\ntypedef enum\r\n{\r\n  HAL_RTC_STATE_RESET             = 0x00U,  /*!< RTC not yet initialized or disabled */\r\n  HAL_RTC_STATE_READY             = 0x01U,  /*!< RTC initialized and ready for use   */\r\n  HAL_RTC_STATE_BUSY              = 0x02U,  /*!< RTC process is ongoing              */     \r\n  HAL_RTC_STATE_TIMEOUT           = 0x03U,  /*!< RTC timeout state                   */  \r\n  HAL_RTC_STATE_ERROR             = 0x04U   /*!< RTC error state                     */      \r\n                                                                        \r\n}HAL_RTCStateTypeDef;\r\n\r\n/** \r\n  * @brief  RTC Configuration Structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t HourFormat;      /*!< Specifies the RTC Hour Format.\r\n                                 This parameter can be a value of @ref RTC_Hour_Formats */         \r\n\r\n  uint32_t AsynchPrediv;    /*!< Specifies the RTC Asynchronous Predivider value.\r\n                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */        \r\n                               \r\n  uint32_t SynchPrediv;     /*!< Specifies the RTC Synchronous Predivider value.\r\n                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */   \r\n  \r\n  uint32_t OutPut;          /*!< Specifies which signal will be routed to the RTC output.   \r\n                                 This parameter can be a value of @ref RTCEx_Output_selection_Definitions */      \r\n  \r\n  uint32_t OutPutPolarity;  /*!< Specifies the polarity of the output signal.  \r\n                                 This parameter can be a value of @ref RTC_Output_Polarity_Definitions */ \r\n  \r\n  uint32_t OutPutType;      /*!< Specifies the RTC Output Pin mode.   \r\n                                 This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */             \r\n}RTC_InitTypeDef;\r\n\r\n/** \r\n  * @brief  RTC Time structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint8_t Hours;            /*!< Specifies the RTC Time Hour.\r\n                                 This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.\r\n                                 This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected  */\r\n\r\n  uint8_t Minutes;          /*!< Specifies the RTC Time Minutes.\r\n                                 This parameter must be a number between Min_Data = 0 and Max_Data = 59 */\r\n  \r\n  uint8_t Seconds;          /*!< Specifies the RTC Time Seconds.\r\n                                 This parameter must be a number between Min_Data = 0 and Max_Data = 59 */\r\n  \r\n  uint32_t SubSeconds;      /*!< Specifies the RTC_SSR RTC Sub Second register content.\r\n                                 This parameter corresponds to a time unit range between [0-1] Second\r\n                                 with [1 Sec / SecondFraction +1] granularity */\r\n  \r\n  uint32_t SecondFraction;  /*!< Specifies the range or granularity of Sub Second register content\r\n                                 corresponding to Synchronous pre-scaler factor value (PREDIV_S)\r\n                                 This parameter corresponds to a time unit range between [0-1] Second\r\n                                 with [1 Sec / SecondFraction +1] granularity.\r\n                                 This field will be used only by HAL_RTC_GetTime function */\r\n\r\n  uint8_t TimeFormat;       /*!< Specifies the RTC AM/PM Time.\r\n                                 This parameter can be a value of @ref RTC_AM_PM_Definitions */ \r\n  \r\n  uint32_t DayLightSaving;  /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.\r\n                                 This parameter can be a value of @ref RTC_DayLightSaving_Definitions */\r\n  \r\n  uint32_t StoreOperation;  /*!< Specifies RTC_StoreOperation value to be written in the BCK bit \r\n                                 in CR register to store the operation.\r\n                                 This parameter can be a value of @ref RTC_StoreOperation_Definitions */\r\n}RTC_TimeTypeDef; \r\n  \r\n/** \r\n  * @brief  RTC Date structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.\r\n                         This parameter can be a value of @ref RTC_WeekDay_Definitions */\r\n  \r\n  uint8_t Month;    /*!< Specifies the RTC Date Month (in BCD format).\r\n                         This parameter can be a value of @ref RTC_Month_Date_Definitions */\r\n\r\n  uint8_t Date;     /*!< Specifies the RTC Date.\r\n                         This parameter must be a number between Min_Data = 1 and Max_Data = 31 */\r\n  \r\n  uint8_t Year;     /*!< Specifies the RTC Date Year.\r\n                         This parameter must be a number between Min_Data = 0 and Max_Data = 99 */\r\n                        \r\n}RTC_DateTypeDef;\r\n\r\n/** \r\n  * @brief  RTC Alarm structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  RTC_TimeTypeDef AlarmTime;     /*!< Specifies the RTC Alarm Time members */\r\n    \r\n  uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.\r\n                                      This parameter can be a value of @ref RTC_AlarmMask_Definitions */\r\n  \r\n  uint32_t AlarmSubSecondMask;   /*!< Specifies the RTC Alarm SubSeconds Masks.\r\n                                      This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */                                   \r\n\r\n  uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.\r\n                                     This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */\r\n  \r\n  uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.\r\n                                      If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.\r\n                                      If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */\r\n                                                                     \r\n  uint32_t Alarm;                /*!< Specifies the alarm .\r\n                                      This parameter can be a value of @ref RTC_Alarms_Definitions */                            \r\n}RTC_AlarmTypeDef;\r\n\r\n/** \r\n  * @brief  RTC Handle Structure definition  \r\n  */ \r\ntypedef struct\r\n{\r\n  RTC_TypeDef                 *Instance;  /*!< Register base address    */\r\n   \r\n  RTC_InitTypeDef             Init;       /*!< RTC required parameters  */ \r\n  \r\n  HAL_LockTypeDef             Lock;       /*!< RTC locking object       */\r\n  \r\n  __IO HAL_RTCStateTypeDef    State;      /*!< Time communication state */\r\n    \r\n}RTC_HandleTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup RTC_Exported_Constants RTC Exported Constants\r\n  * @{\r\n  */\r\n \r\n/** @defgroup RTC_Hour_Formats RTC Hour Formats\r\n  * @{\r\n  */ \r\n#define RTC_HOURFORMAT_24              0x00000000U\r\n#define RTC_HOURFORMAT_12              0x00000040U\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions \r\n  * @{\r\n  */ \r\n#define RTC_OUTPUT_POLARITY_HIGH       0x00000000U\r\n#define RTC_OUTPUT_POLARITY_LOW        0x00100000U\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT\r\n  * @{\r\n  */ \r\n#define RTC_OUTPUT_TYPE_OPENDRAIN      0x00000000U\r\n#define RTC_OUTPUT_TYPE_PUSHPULL       RTC_OR_ALARMTYPE  /* 0x00000008 */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions\r\n  * @{\r\n  */ \r\n#define RTC_HOURFORMAT12_AM            ((uint8_t)0x00U)\r\n#define RTC_HOURFORMAT12_PM            ((uint8_t)0x40U)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions\r\n  * @{\r\n  */ \r\n#define RTC_DAYLIGHTSAVING_SUB1H       0x00020000U\r\n#define RTC_DAYLIGHTSAVING_ADD1H       0x00010000U\r\n#define RTC_DAYLIGHTSAVING_NONE        0x00000000U\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions\r\n  * @{\r\n  */ \r\n#define RTC_STOREOPERATION_RESET        0x00000000U\r\n#define RTC_STOREOPERATION_SET          0x00040000U\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions\r\n  * @{\r\n  */ \r\n#define RTC_FORMAT_BIN                  0x00000000U\r\n#define RTC_FORMAT_BCD                  0x00000001U\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions\r\n  * @{\r\n  */\r\n/* Coded in BCD format */\r\n#define RTC_MONTH_JANUARY              ((uint8_t)0x01U)\r\n#define RTC_MONTH_FEBRUARY             ((uint8_t)0x02U)\r\n#define RTC_MONTH_MARCH                ((uint8_t)0x03U)\r\n#define RTC_MONTH_APRIL                ((uint8_t)0x04U)\r\n#define RTC_MONTH_MAY                  ((uint8_t)0x05U)\r\n#define RTC_MONTH_JUNE                 ((uint8_t)0x06U)\r\n#define RTC_MONTH_JULY                 ((uint8_t)0x07U)\r\n#define RTC_MONTH_AUGUST               ((uint8_t)0x08U)\r\n#define RTC_MONTH_SEPTEMBER            ((uint8_t)0x09U)\r\n#define RTC_MONTH_OCTOBER              ((uint8_t)0x10U)\r\n#define RTC_MONTH_NOVEMBER             ((uint8_t)0x11U)\r\n#define RTC_MONTH_DECEMBER             ((uint8_t)0x12U)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions\r\n  * @{\r\n  */   \r\n#define RTC_WEEKDAY_MONDAY             ((uint8_t)0x01U)\r\n#define RTC_WEEKDAY_TUESDAY            ((uint8_t)0x02U)\r\n#define RTC_WEEKDAY_WEDNESDAY          ((uint8_t)0x03U)\r\n#define RTC_WEEKDAY_THURSDAY           ((uint8_t)0x04U)\r\n#define RTC_WEEKDAY_FRIDAY             ((uint8_t)0x05U)\r\n#define RTC_WEEKDAY_SATURDAY           ((uint8_t)0x06U)\r\n#define RTC_WEEKDAY_SUNDAY             ((uint8_t)0x07U)\r\n/**\r\n  * @}\r\n  */                                 \r\n\r\n/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions\r\n  * @{\r\n  */ \r\n#define RTC_ALARMDATEWEEKDAYSEL_DATE      0x00000000U\r\n#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY   0x40000000U\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions \r\n  * @{\r\n  */ \r\n#define RTC_ALARMMASK_NONE                0x00000000U\r\n#define RTC_ALARMMASK_DATEWEEKDAY         RTC_ALRMAR_MSK4\r\n#define RTC_ALARMMASK_HOURS               RTC_ALRMAR_MSK3\r\n#define RTC_ALARMMASK_MINUTES             RTC_ALRMAR_MSK2\r\n#define RTC_ALARMMASK_SECONDS             RTC_ALRMAR_MSK1\r\n#define RTC_ALARMMASK_ALL                 0x80808080U\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions \r\n  * @{\r\n  */ \r\n#define RTC_ALARM_A                       RTC_CR_ALRAE\r\n#define RTC_ALARM_B                       RTC_CR_ALRBE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions\r\n  * @{\r\n  */\r\n#define RTC_ALARMSUBSECONDMASK_ALL         0x00000000U  /*!< All Alarm SS fields are masked. \r\n                                                             There is no comparison on sub seconds \r\n                                                             for Alarm                              */\r\n#define RTC_ALARMSUBSECONDMASK_SS14_1      0x01000000U  /*!< SS[14:1] are don't care in Alarm \r\n                                                             comparison. Only SS[0] is compared.    */\r\n#define RTC_ALARMSUBSECONDMASK_SS14_2      0x02000000U  /*!< SS[14:2] are don't care in Alarm \r\n                                                             comparison. Only SS[1:0] are compared  */\r\n#define RTC_ALARMSUBSECONDMASK_SS14_3      0x03000000U  /*!< SS[14:3] are don't care in Alarm \r\n                                                             comparison. Only SS[2:0] are compared  */\r\n#define RTC_ALARMSUBSECONDMASK_SS14_4      0x04000000U  /*!< SS[14:4] are don't care in Alarm \r\n                                                             comparison. Only SS[3:0] are compared  */\r\n#define RTC_ALARMSUBSECONDMASK_SS14_5      0x05000000U  /*!< SS[14:5] are don't care in Alarm \r\n                                                             comparison. Only SS[4:0] are compared  */\r\n#define RTC_ALARMSUBSECONDMASK_SS14_6      0x06000000U  /*!< SS[14:6] are don't care in Alarm \r\n                                                             comparison. Only SS[5:0] are compared  */\r\n#define RTC_ALARMSUBSECONDMASK_SS14_7      0x07000000U  /*!< SS[14:7] are don't care in Alarm \r\n                                                             comparison. Only SS[6:0] are compared  */\r\n#define RTC_ALARMSUBSECONDMASK_SS14_8      0x08000000U  /*!< SS[14:8] are don't care in Alarm \r\n                                                             comparison. Only SS[7:0] are compared  */\r\n#define RTC_ALARMSUBSECONDMASK_SS14_9      0x09000000U  /*!< SS[14:9] are don't care in Alarm \r\n                                                             comparison. Only SS[8:0] are compared  */\r\n#define RTC_ALARMSUBSECONDMASK_SS14_10     0x0A000000U  /*!< SS[14:10] are don't care in Alarm \r\n                                                             comparison. Only SS[9:0] are compared  */\r\n#define RTC_ALARMSUBSECONDMASK_SS14_11     0x0B000000U  /*!< SS[14:11] are don't care in Alarm \r\n                                                             comparison. Only SS[10:0] are compared */\r\n#define RTC_ALARMSUBSECONDMASK_SS14_12     0x0C000000U  /*!< SS[14:12] are don't care in Alarm \r\n                                                             comparison.Only SS[11:0] are compared  */\r\n#define RTC_ALARMSUBSECONDMASK_SS14_13     0x0D000000U  /*!< SS[14:13] are don't care in Alarm \r\n                                                             comparison. Only SS[12:0] are compared */\r\n#define RTC_ALARMSUBSECONDMASK_SS14        0x0E000000U  /*!< SS[14] is don't care in Alarm \r\n                                                             comparison.Only SS[13:0] are compared  */\r\n#define RTC_ALARMSUBSECONDMASK_NONE        0x0F000000U  /*!< SS[14:0] are compared and must match \r\n                                                             to activate alarm. */\r\n/**\r\n  * @}\r\n  */   \r\n\r\n/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions \r\n  * @{\r\n  */ \r\n#define RTC_IT_TS                         RTC_CR_TSIE\r\n#define RTC_IT_WUT                        RTC_CR_WUTIE\r\n#define RTC_IT_ALRA                       RTC_CR_ALRAIE\r\n#define RTC_IT_ALRB                       RTC_CR_ALRBIE\r\n#define RTC_IT_TAMP                       RTC_TAMPCR_TAMPIE /* Used only to Enable the Tamper Interrupt */\r\n#define RTC_IT_TAMP1                      RTC_TAMPCR_TAMP1IE\r\n#define RTC_IT_TAMP2                      RTC_TAMPCR_TAMP2IE\r\n#define RTC_IT_TAMP3                      RTC_TAMPCR_TAMP3IE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RTC_Flags_Definitions RTC Flags Definitions \r\n  * @{\r\n  */ \r\n#define RTC_FLAG_RECALPF                  RTC_ISR_RECALPF\r\n#define RTC_FLAG_TAMP3F                   RTC_ISR_TAMP3F\r\n#define RTC_FLAG_TAMP2F                   RTC_ISR_TAMP2F\r\n#define RTC_FLAG_TAMP1F                   RTC_ISR_TAMP1F\r\n#define RTC_FLAG_TSOVF                    RTC_ISR_TSOVF\r\n#define RTC_FLAG_TSF                      RTC_ISR_TSF\r\n#define RTC_FLAG_ITSF                     RTC_ISR_ITSF\r\n#define RTC_FLAG_WUTF                     RTC_ISR_WUTF\r\n#define RTC_FLAG_ALRBF                    RTC_ISR_ALRBF\r\n#define RTC_FLAG_ALRAF                    RTC_ISR_ALRAF\r\n#define RTC_FLAG_INITF                    RTC_ISR_INITF\r\n#define RTC_FLAG_RSF                      RTC_ISR_RSF\r\n#define RTC_FLAG_INITS                    RTC_ISR_INITS\r\n#define RTC_FLAG_SHPF                     RTC_ISR_SHPF\r\n#define RTC_FLAG_WUTWF                    RTC_ISR_WUTWF\r\n#define RTC_FLAG_ALRBWF                   RTC_ISR_ALRBWF\r\n#define RTC_FLAG_ALRAWF                   RTC_ISR_ALRAWF\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup RTC_Exported_Macros RTC Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief Reset RTC handle state\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)\r\n\r\n/**\r\n  * @brief  Disable the write protection for RTC registers.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)             \\\r\n                        do{                                       \\\r\n                            (__HANDLE__)->Instance->WPR = 0xCAU;   \\\r\n                            (__HANDLE__)->Instance->WPR = 0x53U;   \\\r\n                          } while(0U)\r\n\r\n/**\r\n  * @brief  Enable the write protection for RTC registers.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)              \\\r\n                        do{                                       \\\r\n                            (__HANDLE__)->Instance->WPR = 0xFFU;   \\\r\n                          } while(0U)                            \r\n \r\n/**\r\n  * @brief  Enable the RTC ALARMA peripheral.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__)                           ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))\r\n\r\n/**\r\n  * @brief  Disable the RTC ALARMA peripheral.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))\r\n\r\n/**\r\n  * @brief  Enable the RTC ALARMB peripheral.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__)                           ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))\r\n\r\n/**\r\n  * @brief  Disable the RTC ALARMB peripheral.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))\r\n\r\n/**\r\n  * @brief  Enable the RTC Alarm interrupt.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. \r\n  *          This parameter can be any combination of the following values:\r\n  *             @arg RTC_IT_ALRA: Alarm A interrupt\r\n  *             @arg RTC_IT_ALRB: Alarm B interrupt  \r\n  * @retval None\r\n  */   \r\n#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disable the RTC Alarm interrupt.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. \r\n  *         This parameter can be any combination of the following values:\r\n  *            @arg RTC_IT_ALRA: Alarm A interrupt\r\n  *            @arg RTC_IT_ALRB: Alarm B interrupt  \r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Check whether the specified RTC Alarm interrupt has occurred or not.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt to check.\r\n  *         This parameter can be:\r\n  *            @arg RTC_IT_ALRA: Alarm A interrupt\r\n  *            @arg RTC_IT_ALRB: Alarm B interrupt  \r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__)                  ((((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) & 0x0000FFFFU) != RESET)? SET : RESET)\r\n\r\n/**\r\n  * @brief  Get the selected RTC Alarm's flag status.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @param  __FLAG__ specifies the RTC Alarm Flag to check.\r\n  *         This parameter can be:\r\n  *            @arg RTC_FLAG_ALRAF\r\n  *            @arg RTC_FLAG_ALRBF\r\n  *            @arg RTC_FLAG_ALRAWF     \r\n  *            @arg RTC_FLAG_ALRBWF    \r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)                (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)\r\n\r\n/**\r\n  * @brief  Clear the RTC Alarm's pending flags.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @param  __FLAG__ specifies the RTC Alarm Flag sources to be enabled or disabled.\r\n  *          This parameter can be:\r\n  *             @arg RTC_FLAG_ALRAF\r\n  *             @arg RTC_FLAG_ALRBF \r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)                  ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFFU)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))\r\n                                       \r\n/**\r\n  * @brief  Check whether the specified RTC Alarm interrupt has been enabled or not.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.\r\n  *         This parameter can be:\r\n  *            @arg RTC_IT_ALRA: Alarm A interrupt\r\n  *            @arg RTC_IT_ALRB: Alarm B interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)\r\n\r\n/**\r\n  * @brief  Enable interrupt on the RTC Alarm associated Exti line.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_ALARM_EXTI_ENABLE_IT()            (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)\r\n\r\n/**\r\n  * @brief  Disable interrupt on the RTC Alarm associated Exti line.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_ALARM_EXTI_DISABLE_IT()           (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))\r\n\r\n/**\r\n  * @brief  Enable event on the RTC Alarm associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT()         (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)\r\n\r\n/**\r\n  * @brief  Disable event on the RTC Alarm associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT()         (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))\r\n\r\n/**\r\n  * @brief  Enable falling edge trigger on the RTC Alarm associated Exti line.  \r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)\r\n\r\n/**\r\n  * @brief  Disable falling edge trigger on the RTC Alarm associated Exti line.  \r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))\r\n\r\n/**\r\n  * @brief  Enable rising edge trigger on the RTC Alarm associated Exti line.  \r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)\r\n\r\n/**\r\n  * @brief  Disable rising edge trigger on the RTC Alarm associated Exti line.  \r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))\r\n\r\n/**\r\n  * @brief  Enable rising & falling edge trigger on the RTC Alarm associated Exti line.  \r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();\r\n\r\n/**\r\n  * @brief  Disable rising & falling edge trigger on the RTC Alarm associated Exti line.  \r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();\r\n\r\n/**\r\n  * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.\r\n  * @retval Line Status.\r\n  */\r\n#define __HAL_RTC_ALARM_EXTI_GET_FLAG()              (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)\r\n\r\n/**\r\n  * @brief Clear the RTC Alarm associated Exti line flag.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()            (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)\r\n\r\n/**\r\n  * @brief Generate a Software interrupt on RTC Alarm associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()         (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Include RTC HAL Extension module */\r\n#include \"stm32f7xx_hal_rtc_ex.h\"\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup RTC_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup RTC_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n/* Initialization and de-initialization functions  ****************************/\r\nHAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);\r\nHAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);\r\nvoid       HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);\r\nvoid       HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup RTC_Exported_Functions_Group2\r\n  * @{\r\n  */\r\n/* RTC Time and Date functions ************************************************/\r\nHAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);\r\nHAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);\r\nHAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);\r\nHAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup RTC_Exported_Functions_Group3\r\n  * @{\r\n  */\r\n/* RTC Alarm functions ********************************************************/\r\nHAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);\r\nHAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);\r\nHAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);\r\nHAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);\r\nvoid                HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);\r\nHAL_StatusTypeDef   HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);\r\nvoid         HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup RTC_Exported_Functions_Group4\r\n  * @{\r\n  */\r\n/* Peripheral Control functions ***********************************************/\r\nHAL_StatusTypeDef   HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup RTC_Exported_Functions_Group5\r\n  * @{\r\n  */\r\n/* Peripheral State functions *************************************************/\r\nHAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup RTC_Private_Constants RTC Private Constants\r\n  * @{\r\n  */\r\n/* Masks Definition */\r\n#define RTC_TR_RESERVED_MASK    0x007F7F7FU\r\n#define RTC_DR_RESERVED_MASK    0x00FFFF3FU \r\n#define RTC_INIT_MASK           0xFFFFFFFFU  \r\n#define RTC_RSF_MASK            0xFFFFFF5FU\r\n\r\n#define RTC_TIMEOUT_VALUE       1000U\r\n\r\n#define RTC_EXTI_LINE_ALARM_EVENT             EXTI_IMR_IM17  /*!< External interrupt line 17 Connected to the RTC Alarm event */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup RTC_Private_Macros RTC Private Macros\r\n  * @{\r\n  */\r\n\r\n/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters\r\n  * @{\r\n  */\r\n#define IS_RTC_HOUR_FORMAT(__FORMAT__) (((__FORMAT__) == RTC_HOURFORMAT_12) || \\\r\n                                        ((__FORMAT__) == RTC_HOURFORMAT_24))\r\n#define IS_RTC_OUTPUT_POL(__POL__)     (((__POL__) == RTC_OUTPUT_POLARITY_HIGH) || \\\r\n                                        ((__POL__) == RTC_OUTPUT_POLARITY_LOW))\r\n#define IS_RTC_OUTPUT_TYPE(__TYPE__)   (((__TYPE__) == RTC_OUTPUT_TYPE_OPENDRAIN) || \\\r\n                                        ((__TYPE__) == RTC_OUTPUT_TYPE_PUSHPULL))\r\n#define IS_RTC_ASYNCH_PREDIV(__PREDIV__)   ((__PREDIV__) <= 0x7FU) \r\n#define IS_RTC_SYNCH_PREDIV(__PREDIV__)    ((__PREDIV__) <= 0x7FFFU)\r\n#define IS_RTC_HOUR12(__HOUR__)            (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))\r\n#define IS_RTC_HOUR24(__HOUR__)            ((__HOUR__) <= 23U)\r\n#define IS_RTC_MINUTES(__MINUTES__)        ((__MINUTES__) <= 59U)\r\n#define IS_RTC_SECONDS(__SECONDS__)        ((__SECONDS__) <= 59U)\r\n#define IS_RTC_HOURFORMAT12(__PM__)  (((__PM__) == RTC_HOURFORMAT12_AM) || ((__PM__) == RTC_HOURFORMAT12_PM))\r\n#define IS_RTC_DAYLIGHT_SAVING(__SAVE__) (((__SAVE__) == RTC_DAYLIGHTSAVING_SUB1H) || \\\r\n                                          ((__SAVE__) == RTC_DAYLIGHTSAVING_ADD1H) || \\\r\n                                          ((__SAVE__) == RTC_DAYLIGHTSAVING_NONE))\r\n#define IS_RTC_STORE_OPERATION(__OPERATION__) (((__OPERATION__) == RTC_STOREOPERATION_RESET) || \\\r\n                                               ((__OPERATION__) == RTC_STOREOPERATION_SET))\r\n#define IS_RTC_FORMAT(__FORMAT__) (((__FORMAT__) == RTC_FORMAT_BIN) || ((__FORMAT__) == RTC_FORMAT_BCD))\r\n#define IS_RTC_YEAR(__YEAR__)              ((__YEAR__) <= 99U)\r\n#define IS_RTC_MONTH(__MONTH__)            (((__MONTH__) >= 1U) && ((__MONTH__) <= 12U))\r\n#define IS_RTC_DATE(__DATE__)              (((__DATE__) >= 1U) && ((__DATE__) <= 31U))\r\n#define IS_RTC_WEEKDAY(__WEEKDAY__) (((__WEEKDAY__) == RTC_WEEKDAY_MONDAY)    || \\\r\n                                     ((__WEEKDAY__) == RTC_WEEKDAY_TUESDAY)   || \\\r\n                                     ((__WEEKDAY__) == RTC_WEEKDAY_WEDNESDAY) || \\\r\n                                     ((__WEEKDAY__) == RTC_WEEKDAY_THURSDAY)  || \\\r\n                                     ((__WEEKDAY__) == RTC_WEEKDAY_FRIDAY)    || \\\r\n                                     ((__WEEKDAY__) == RTC_WEEKDAY_SATURDAY)  || \\\r\n                                     ((__WEEKDAY__) == RTC_WEEKDAY_SUNDAY))\r\n\r\n#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(__DATE__) (((__DATE__) >0U) && ((__DATE__) <= 31U))\r\n#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(__WEEKDAY__) (((__WEEKDAY__) == RTC_WEEKDAY_MONDAY)    || \\\r\n                                                        ((__WEEKDAY__) == RTC_WEEKDAY_TUESDAY)   || \\\r\n                                                        ((__WEEKDAY__) == RTC_WEEKDAY_WEDNESDAY) || \\\r\n                                                        ((__WEEKDAY__) == RTC_WEEKDAY_THURSDAY)  || \\\r\n                                                        ((__WEEKDAY__) == RTC_WEEKDAY_FRIDAY)    || \\\r\n                                                        ((__WEEKDAY__) == RTC_WEEKDAY_SATURDAY)  || \\\r\n                                                        ((__WEEKDAY__) == RTC_WEEKDAY_SUNDAY))\r\n#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \\\r\n                                                ((__SEL__) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))\r\n#define IS_RTC_ALARM_MASK(__MASK__)  (((__MASK__) & 0x7F7F7F7FU) == (uint32_t)RESET)\r\n#define IS_RTC_ALARM(__ALARM__)      (((__ALARM__) == RTC_ALARM_A) || ((__ALARM__) == RTC_ALARM_B))\r\n#define IS_RTC_ALARM_SUB_SECOND_VALUE(__VALUE__) ((__VALUE__) <= 0x00007FFFU)\r\n#define IS_RTC_ALARM_SUB_SECOND_MASK(__MASK__)   (((__MASK__) == RTC_ALARMSUBSECONDMASK_ALL) || \\\r\n                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_1) || \\\r\n                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_2) || \\\r\n                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_3) || \\\r\n                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_4) || \\\r\n                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_5) || \\\r\n                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_6) || \\\r\n                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_7) || \\\r\n                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_8) || \\\r\n                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_9) || \\\r\n                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_10) || \\\r\n                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_11) || \\\r\n                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_12) || \\\r\n                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_13) || \\\r\n                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14) || \\\r\n                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_NONE))\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup RTC_Private_Functions RTC Private Functions\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef  RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);\r\nuint8_t            RTC_ByteToBcd2(uint8_t Value);\r\nuint8_t            RTC_Bcd2ToByte(uint8_t Value);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_RTC_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_rtc_ex.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of RTC HAL Extension module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_RTC_EX_H\r\n#define __STM32F7xx_HAL_RTC_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup RTCEx\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/ \r\n/** @defgroup RTCEx_Exported_Types RTCEx Exported Types\r\n  * @{\r\n  */\r\n\r\n/** \r\n  * @brief  RTC Tamper structure definition  \r\n  */\r\ntypedef struct \r\n{\r\n  uint32_t Tamper;                      /*!< Specifies the Tamper Pin.\r\n                                             This parameter can be a value of @ref  RTCEx_Tamper_Pins_Definitions */\r\n  \r\n  uint32_t Interrupt;                   /*!< Specifies the Tamper Interrupt.\r\n                                             This parameter can be a value of @ref  RTCEx_Tamper_Interrupt_Definitions */                                  \r\n                                             \r\n  uint32_t Trigger;                     /*!< Specifies the Tamper Trigger.\r\n                                             This parameter can be a value of @ref  RTCEx_Tamper_Trigger_Definitions */\r\n                                             \r\n  uint32_t NoErase;                     /*!< Specifies the Tamper no erase mode.\r\n                                             This parameter can be a value of @ref  RTCEx_Tamper_EraseBackUp_Definitions */\r\n\r\n  uint32_t MaskFlag;                     /*!< Specifies the Tamper Flag masking.\r\n                                             This parameter can be a value of @ref RTCEx_Tamper_MaskFlag_Definitions   */\r\n\r\n  uint32_t Filter;                      /*!< Specifies the RTC Filter Tamper.\r\n                                             This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */\r\n  \r\n  uint32_t SamplingFrequency;           /*!< Specifies the sampling frequency.\r\n                                             This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */\r\n                                      \r\n  uint32_t PrechargeDuration;           /*!< Specifies the Precharge Duration .\r\n                                             This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */ \r\n \r\n  uint32_t TamperPullUp;                /*!< Specifies the Tamper PullUp .\r\n                                             This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */           \r\n \r\n  uint32_t TimeStampOnTamperDetection;  /*!< Specifies the TimeStampOnTamperDetection.\r\n                                             This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */                      \r\n}RTC_TamperTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup RTCEx_Output_selection_Definitions RTCEx Output selection Definitions \r\n  * @{\r\n  */ \r\n#define RTC_OUTPUT_DISABLE             ((uint32_t)0x00000000U)\r\n#define RTC_OUTPUT_ALARMA              ((uint32_t)0x00200000U)\r\n#define RTC_OUTPUT_ALARMB              ((uint32_t)0x00400000U)\r\n#define RTC_OUTPUT_WAKEUP              ((uint32_t)0x00600000U)\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/** @defgroup RTCEx_Backup_Registers_Definitions RTC Backup Registers Definitions\r\n  * @{\r\n  */\r\n#define RTC_BKP_DR0                       ((uint32_t)0x00000000U)\r\n#define RTC_BKP_DR1                       ((uint32_t)0x00000001U)\r\n#define RTC_BKP_DR2                       ((uint32_t)0x00000002U)\r\n#define RTC_BKP_DR3                       ((uint32_t)0x00000003U)\r\n#define RTC_BKP_DR4                       ((uint32_t)0x00000004U)\r\n#define RTC_BKP_DR5                       ((uint32_t)0x00000005U)\r\n#define RTC_BKP_DR6                       ((uint32_t)0x00000006U)\r\n#define RTC_BKP_DR7                       ((uint32_t)0x00000007U)\r\n#define RTC_BKP_DR8                       ((uint32_t)0x00000008U)\r\n#define RTC_BKP_DR9                       ((uint32_t)0x00000009U)\r\n#define RTC_BKP_DR10                      ((uint32_t)0x0000000AU)\r\n#define RTC_BKP_DR11                      ((uint32_t)0x0000000BU)\r\n#define RTC_BKP_DR12                      ((uint32_t)0x0000000CU)\r\n#define RTC_BKP_DR13                      ((uint32_t)0x0000000DU)\r\n#define RTC_BKP_DR14                      ((uint32_t)0x0000000EU)\r\n#define RTC_BKP_DR15                      ((uint32_t)0x0000000FU)\r\n#define RTC_BKP_DR16                      ((uint32_t)0x00000010U)\r\n#define RTC_BKP_DR17                      ((uint32_t)0x00000011U)\r\n#define RTC_BKP_DR18                      ((uint32_t)0x00000012U)\r\n#define RTC_BKP_DR19                      ((uint32_t)0x00000013U)\r\n#define RTC_BKP_DR20                      ((uint32_t)0x00000014U)\r\n#define RTC_BKP_DR21                      ((uint32_t)0x00000015U)\r\n#define RTC_BKP_DR22                      ((uint32_t)0x00000016U)\r\n#define RTC_BKP_DR23                      ((uint32_t)0x00000017U)\r\n#define RTC_BKP_DR24                      ((uint32_t)0x00000018U)\r\n#define RTC_BKP_DR25                      ((uint32_t)0x00000019U)\r\n#define RTC_BKP_DR26                      ((uint32_t)0x0000001AU)\r\n#define RTC_BKP_DR27                      ((uint32_t)0x0000001BU)\r\n#define RTC_BKP_DR28                      ((uint32_t)0x0000001CU)\r\n#define RTC_BKP_DR29                      ((uint32_t)0x0000001DU)\r\n#define RTC_BKP_DR30                      ((uint32_t)0x0000001EU)\r\n#define RTC_BKP_DR31                      ((uint32_t)0x0000001FU)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges definitions \r\n  * @{\r\n  */ \r\n#define RTC_TIMESTAMPEDGE_RISING          ((uint32_t)0x00000000U)\r\n#define RTC_TIMESTAMPEDGE_FALLING         ((uint32_t)0x00000008U)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup RTCEx_Tamper_Pins_Definitions RTCEx Tamper Pins Definitions \r\n  * @{\r\n  */ \r\n#define RTC_TAMPER_1                    RTC_TAMPCR_TAMP1E\r\n#define RTC_TAMPER_2                    RTC_TAMPCR_TAMP2E\r\n#define RTC_TAMPER_3                    RTC_TAMPCR_TAMP3E\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RTCEx_Tamper_Interrupt_Definitions RTCEx Tamper Interrupt Definitions\r\n  * @{\r\n  */\r\n#define RTC_TAMPER1_INTERRUPT                RTC_TAMPCR_TAMP1IE\r\n#define RTC_TAMPER2_INTERRUPT                RTC_TAMPCR_TAMP2IE\r\n#define RTC_TAMPER3_INTERRUPT                RTC_TAMPCR_TAMP3IE\r\n#define RTC_ALL_TAMPER_INTERRUPT             RTC_TAMPCR_TAMPIE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RTCEx_TimeStamp_Pin_Selection RTCEx TimeStamp Pin Selection\r\n  * @{\r\n  */ \r\n#define RTC_TIMESTAMPPIN_DEFAULT            ((uint32_t)0x00000000U)\r\n#define RTC_TIMESTAMPPIN_POS1               ((uint32_t)0x00000002U)\r\n#define RTC_TIMESTAMPPIN_POS2               ((uint32_t)0x00000004U)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup RTCEx_Tamper_Trigger_Definitions RTCEx Tamper Trigger Definitions \r\n  * @{\r\n  */ \r\n#define RTC_TAMPERTRIGGER_RISINGEDGE       ((uint32_t)0x00000000U)\r\n#define RTC_TAMPERTRIGGER_FALLINGEDGE      ((uint32_t)0x00000002U)\r\n#define RTC_TAMPERTRIGGER_LOWLEVEL         RTC_TAMPERTRIGGER_RISINGEDGE\r\n#define RTC_TAMPERTRIGGER_HIGHLEVEL        RTC_TAMPERTRIGGER_FALLINGEDGE \r\n/**\r\n  * @}\r\n  */  \r\n\r\n  /** @defgroup RTCEx_Tamper_EraseBackUp_Definitions RTCEx Tamper EraseBackUp Definitions\r\n* @{\r\n*/\r\n#define RTC_TAMPER_ERASE_BACKUP_ENABLE               ((uint32_t)0x00000000U)\r\n#define RTC_TAMPER_ERASE_BACKUP_DISABLE              ((uint32_t)0x00020000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RTCEx_Tamper_MaskFlag_Definitions RTCEx Tamper MaskFlag Definitions\r\n  * @{\r\n  */\r\n#define RTC_TAMPERMASK_FLAG_DISABLE                ((uint32_t)0x00000000U)\r\n#define RTC_TAMPERMASK_FLAG_ENABLE                 ((uint32_t)0x00040000U)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup RTCEx_Tamper_Filter_Definitions RTCEx Tamper Filter Definitions \r\n  * @{\r\n  */ \r\n#define RTC_TAMPERFILTER_DISABLE   ((uint32_t)0x00000000U)  /*!< Tamper filter is disabled */\r\n\r\n#define RTC_TAMPERFILTER_2SAMPLE   ((uint32_t)0x00000800U)  /*!< Tamper is activated after 2 \r\n                                                                consecutive samples at the active level */\r\n#define RTC_TAMPERFILTER_4SAMPLE   ((uint32_t)0x00001000U)  /*!< Tamper is activated after 4 \r\n                                                                consecutive samples at the active level */\r\n#define RTC_TAMPERFILTER_8SAMPLE   ((uint32_t)0x00001800U)  /*!< Tamper is activated after 8 \r\n                                                                consecutive samples at the active leve. */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTCEx Tamper Sampling Frequencies Definitions \r\n  * @{\r\n  */\r\n#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768  ((uint32_t)0x00000000U)  /*!< Each of the tamper inputs are sampled\r\n                                                                             with a frequency =  RTCCLK / 32768 */\r\n#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384  ((uint32_t)0x00000100U)  /*!< Each of the tamper inputs are sampled\r\n                                                                             with a frequency =  RTCCLK / 16384 */\r\n#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192   ((uint32_t)0x00000200U)  /*!< Each of the tamper inputs are sampled\r\n                                                                             with a frequency =  RTCCLK / 8192  */\r\n#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096   ((uint32_t)0x00000300U)  /*!< Each of the tamper inputs are sampled\r\n                                                                             with a frequency =  RTCCLK / 4096  */\r\n#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048   ((uint32_t)0x00000400U)  /*!< Each of the tamper inputs are sampled\r\n                                                                             with a frequency =  RTCCLK / 2048  */\r\n#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024   ((uint32_t)0x00000500U)  /*!< Each of the tamper inputs are sampled\r\n                                                                             with a frequency =  RTCCLK / 1024  */\r\n#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512    ((uint32_t)0x00000600U)  /*!< Each of the tamper inputs are sampled\r\n                                                                             with a frequency =  RTCCLK / 512   */\r\n#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256    ((uint32_t)0x00000700U)  /*!< Each of the tamper inputs are sampled\r\n                                                                             with a frequency =  RTCCLK / 256   */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTCEx Tamper Pin Precharge Duration Definitions \r\n  * @{\r\n  */ \r\n#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000U)  /*!< Tamper pins are pre-charged before \r\n                                                                         sampling during 1 RTCCLK cycle */\r\n#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000U)  /*!< Tamper pins are pre-charged before \r\n                                                                         sampling during 2 RTCCLK cycles */\r\n#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000U)  /*!< Tamper pins are pre-charged before \r\n                                                                         sampling during 4 RTCCLK cycles */\r\n#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000U)  /*!< Tamper pins are pre-charged before \r\n                                                                         sampling during 8 RTCCLK cycles */\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTCEx Tamper TimeStampOnTamperDetection Definitions\r\n  * @{\r\n  */ \r\n#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE  ((uint32_t)RTC_TAMPCR_TAMPTS)  /*!< TimeStamp on Tamper Detection event saved        */\r\n#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000U)        /*!< TimeStamp on Tamper Detection event is not saved */                                                                      \r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup  RTCEx_Tamper_Pull_UP_Definitions RTCEx Tamper Pull UP Definitions\r\n  * @{\r\n  */ \r\n#define RTC_TAMPER_PULLUP_ENABLE  ((uint32_t)0x00000000U)            /*!< TimeStamp on Tamper Detection event saved        */\r\n#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAMPCR_TAMPPUDIS)   /*!< TimeStamp on Tamper Detection event is not saved */                                                                  \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definitions \r\n  * @{\r\n  */ \r\n#define RTC_WAKEUPCLOCK_RTCCLK_DIV16        ((uint32_t)0x00000000U)\r\n#define RTC_WAKEUPCLOCK_RTCCLK_DIV8         ((uint32_t)0x00000001U)\r\n#define RTC_WAKEUPCLOCK_RTCCLK_DIV4         ((uint32_t)0x00000002U)\r\n#define RTC_WAKEUPCLOCK_RTCCLK_DIV2         ((uint32_t)0x00000003U)\r\n#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS      ((uint32_t)0x00000004U)\r\n#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS      ((uint32_t)0x00000006U)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth calib period Definitions \r\n  * @{\r\n  */ \r\n#define RTC_SMOOTHCALIB_PERIOD_32SEC   ((uint32_t)0x00000000U)  /*!< If RTCCLK = 32768 Hz, Smooth calibration\r\n                                                                    period is 32s,  else 2exp20 RTCCLK seconds */\r\n#define RTC_SMOOTHCALIB_PERIOD_16SEC   ((uint32_t)0x00002000U)  /*!< If RTCCLK = 32768 Hz, Smooth calibration \r\n                                                                    period is 16s, else 2exp19 RTCCLK seconds */\r\n#define RTC_SMOOTHCALIB_PERIOD_8SEC    ((uint32_t)0x00004000U)  /*!< If RTCCLK = 32768 Hz, Smooth calibration \r\n                                                                    period is 8s, else 2exp18 RTCCLK seconds */                                        \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth calib Plus pulses Definitions \r\n  * @{\r\n  */ \r\n#define RTC_SMOOTHCALIB_PLUSPULSES_SET    ((uint32_t)0x00008000U)  /*!< The number of RTCCLK pulses added  \r\n                                                                       during a X -second window = Y - CALM[8:0] \r\n                                                                       with Y = 512, 256, 128 when X = 32, 16, 8 */\r\n#define RTC_SMOOTHCALIB_PLUSPULSES_RESET  ((uint32_t)0x00000000U)  /*!< The number of RTCCLK pulses subbstited\r\n                                                                       during a 32-second window = CALM[8:0] */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions RTCEx Add 1 Second Parameter Definitions\r\n  * @{\r\n  */ \r\n#define RTC_SHIFTADD1S_RESET      ((uint32_t)0x00000000U)\r\n#define RTC_SHIFTADD1S_SET        ((uint32_t)0x80000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n /** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions\r\n  * @{\r\n  */ \r\n#define RTC_CALIBOUTPUT_512HZ            ((uint32_t)0x00000000U) \r\n#define RTC_CALIBOUTPUT_1HZ              ((uint32_t)0x00080000U)\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/* Exported macros -----------------------------------------------------------*/\r\n/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Enable the RTC WakeUp Timer peripheral.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__)                     ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))\r\n\r\n/**\r\n  * @brief  Disable the RTC WakeUp Timer peripheral.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__)                    ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))\r\n\r\n/**\r\n  * @brief  Enable the RTC WakeUpTimer interrupt.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.\r\n  *         This parameter can be:\r\n  *            @arg RTC_IT_WUT: WakeUpTimer interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disable the RTC WakeUpTimer interrupt.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.\r\n  *         This parameter can be:\r\n  *            @arg RTC_IT_WUT: WakeUpTimer interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Check whether the specified RTC WakeUpTimer interrupt has occurred or not.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to check.\r\n  *         This parameter can be:\r\n  *            @arg RTC_IT_WUT:  WakeUpTimer interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__)       (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)\r\n\r\n/**\r\n  * @brief  Check whether the specified RTC Wake Up timer interrupt has been enabled or not.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @param  __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check.\r\n  *         This parameter can be:\r\n  *            @arg RTC_IT_WUT:  WakeUpTimer interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)   (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)\r\n\r\n/**\r\n  * @brief  Get the selected RTC WakeUpTimer's flag status.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @param  __FLAG__ specifies the RTC WakeUpTimer Flag is pending or not.\r\n  *          This parameter can be:\r\n  *             @arg RTC_FLAG_WUTF\r\n  *             @arg RTC_FLAG_WUTWF\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__)   (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)\r\n\r\n/**\r\n  * @brief  Clear the RTC Wake Up timer's pending flags.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @param  __FLAG__ specifies the RTC WakeUpTimer Flag to clear.\r\n  *         This parameter can be:\r\n  *            @arg RTC_FLAG_WUTF\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))    \r\n\r\n/**\r\n  * @brief  Enable the RTC Tamper1 input detection.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E))\r\n\r\n/**\r\n  * @brief  Disable the RTC Tamper1 input detection.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E))\r\n\r\n/**\r\n  * @brief  Enable the RTC Tamper2 input detection.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E))\r\n\r\n/**\r\n  * @brief  Disable the RTC Tamper2 input detection.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E))\r\n\r\n/**\r\n  * @brief  Enable the RTC Tamper3 input detection.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E))\r\n\r\n/**\r\n  * @brief  Disable the RTC Tamper3 input detection.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E))\r\n\r\n/**\r\n  * @brief  Check whether the specified RTC Tamper interrupt has occurred or not.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt to check.\r\n  *         This parameter can be:\r\n  *            @arg  RTC_IT_TAMP: All tampers interrupts\r\n  *            @arg  RTC_IT_TAMP1: Tamper1 interrupt\r\n  *            @arg  RTC_IT_TAMP2: Tamper2 interrupt\r\n  *            @arg  RTC_IT_TAMP3: Tamper3 interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)           (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3)) != RESET) ? SET : RESET) : \\\r\n                                                                      ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET) : \\\r\n                                                                                                          (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7)) != RESET) ? SET : RESET))\r\n\r\n/**\r\n  * @brief  Check whether the specified RTC Tamper interrupt has been enabled or not.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt source to check.\r\n  *         This parameter can be:\r\n  *            @arg  RTC_IT_TAMP: All tampers interrupts\r\n  *            @arg  RTC_IT_TAMP1: Tamper1 interrupt\r\n  *            @arg  RTC_IT_TAMP2: Tamper2 interrupt\r\n  *            @arg  RTC_IT_TAMP3: Tamper3 interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)    (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)\r\n\r\n/**\r\n  * @brief  Get the selected RTC Tamper's flag status.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @param  __FLAG__ specifies the RTC Tamper Flag is pending or not.\r\n  *          This parameter can be:\r\n  *             @arg RTC_FLAG_TAMP1F: Tamper1 flag\r\n  *             @arg RTC_FLAG_TAMP2F: Tamper2 flag\r\n  *             @arg RTC_FLAG_TAMP3F: Tamper3 flag\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__)        (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)\r\n\r\n/**\r\n  * @brief  Clear the RTC Tamper's pending flags.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @param  __FLAG__ specifies the RTC Tamper Flag sources to clear.\r\n  *          This parameter can be:\r\n  *             @arg RTC_FLAG_TAMP1F: Tamper1 flag\r\n  *             @arg RTC_FLAG_TAMP2F: Tamper2 flag\r\n  *             @arg RTC_FLAG_TAMP3F: Tamper3 flag\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))\r\n\r\n/**\r\n  * @brief  Enable the RTC TimeStamp peripheral.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))\r\n\r\n/**\r\n  * @brief  Disable the RTC TimeStamp peripheral.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))\r\n\r\n/**\r\n  * @brief  Enable the RTC TimeStamp interrupt.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to be enabled or disabled.\r\n  *         This parameter can be:\r\n  *            @arg RTC_IT_TS: TimeStamp interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disable the RTC TimeStamp interrupt.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to be enabled or disabled. \r\n  *         This parameter can be:\r\n  *            @arg RTC_IT_TS: TimeStamp interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Check whether the specified RTC TimeStamp interrupt has occurred or not.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to check.\r\n  *         This parameter can be:\r\n  *            @arg RTC_IT_TS: TimeStamp interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__)        (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)\r\n\r\n/**\r\n  * @brief  Check whether the specified RTC Time Stamp interrupt has been enabled or not.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @param  __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check.\r\n  *         This parameter can be:\r\n  *            @arg RTC_IT_TS: TimeStamp interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)\r\n\r\n/**\r\n  * @brief  Get the selected RTC TimeStamp's flag status.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @param  __FLAG__ specifies the RTC TimeStamp Flag is pending or not.\r\n  *         This parameter can be:\r\n  *            @arg RTC_FLAG_TSF\r\n  *            @arg RTC_FLAG_TSOVF\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)     (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)\r\n\r\n/**\r\n  * @brief  Clear the RTC Time Stamp's pending flags.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @param  __FLAG__ specifies the RTC Alarm Flag sources to clear.\r\n  *          This parameter can be:\r\n  *             @arg RTC_FLAG_TSF\r\n  *             @arg RTC_FLAG_TSOVF\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)   ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))\r\n\r\n/**\r\n  * @brief  Enable the RTC internal TimeStamp peripheral.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))\r\n\r\n/**\r\n  * @brief  Disable the RTC internal TimeStamp peripheral.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))\r\n\r\n/**\r\n  * @brief  Get the selected RTC Internal Time Stamp's flag status.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @param  __FLAG__ specifies the RTC Internal Time Stamp Flag is pending or not.\r\n  *         This parameter can be:\r\n  *            @arg RTC_FLAG_ITSF\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)    (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)\r\n\r\n/**\r\n  * @brief  Clear the RTC Internal Time Stamp's pending flags.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @param  __FLAG__ specifies the RTC Internal Time Stamp Flag source to clear.\r\n  *          This parameter can be:\r\n  *             @arg RTC_FLAG_ITSF\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)  ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0003FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))\r\n\r\n/**\r\n  * @brief  Enable the RTC calibration output.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))\r\n\r\n/**\r\n  * @brief  Disable the calibration output.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))\r\n\r\n/**\r\n  * @brief  Enable the clock reference detection.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))\r\n\r\n/**\r\n  * @brief  Disable the clock reference detection.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))\r\n\r\n/**\r\n  * @brief  Get the selected RTC shift operation's flag status.\r\n  * @param  __HANDLE__ specifies the RTC handle.\r\n  * @param  __FLAG__ specifies the RTC shift operation Flag is pending or not.\r\n  *          This parameter can be:\r\n  *             @arg RTC_FLAG_SHPF\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__)         (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)\r\n\r\n/**\r\n  * @brief  Enable interrupt on the RTC WakeUp Timer associated Exti line.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT()       (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)\r\n\r\n/**\r\n  * @brief  Disable interrupt on the RTC WakeUp Timer associated Exti line.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT()      (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))\r\n\r\n/**\r\n  * @brief  Enable event on the RTC WakeUp Timer associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT()    (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)\r\n\r\n/**\r\n  * @brief  Disable event on the RTC WakeUp Timer associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT()   (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))\r\n\r\n/**\r\n  * @brief  Enable falling edge trigger on the RTC WakeUp Timer associated Exti line. \r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)\r\n\r\n/**\r\n  * @brief  Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))\r\n\r\n/**\r\n  * @brief  Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)\r\n\r\n/**\r\n  * @brief  Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))\r\n\r\n/**\r\n  * @brief  Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();\r\n\r\n/**\r\n  * @brief  Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.\r\n  * This parameter can be:\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\r\n\r\n/**\r\n  * @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.\r\n  * @retval Line Status.\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG()              (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)\r\n\r\n/**\r\n  * @brief Clear the RTC WakeUp Timer associated Exti line flag.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG()            (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)\r\n\r\n/**\r\n  * @brief Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT()         (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)\r\n\r\n/**\r\n  * @brief  Enable interrupt on the RTC Tamper and Timestamp associated Exti line.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()        (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)\r\n\r\n/**\r\n  * @brief  Disable interrupt on the RTC Tamper and Timestamp associated Exti line.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()       (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))\r\n\r\n/**\r\n  * @brief  Enable event on the RTC Tamper and Timestamp associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT()    (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)\r\n\r\n/**\r\n  * @brief  Disable event on the RTC Tamper and Timestamp associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT()   (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))\r\n\r\n/**\r\n  * @brief  Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line. \r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)\r\n\r\n/**\r\n  * @brief  Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))\r\n\r\n/**\r\n  * @brief  Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)\r\n\r\n/**\r\n  * @brief  Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))\r\n\r\n/**\r\n  * @brief  Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE();\r\n\r\n/**\r\n  * @brief  Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.\r\n  * This parameter can be:\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE();\r\n\r\n/**\r\n  * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.\r\n  * @retval Line Status.\r\n  */\r\n#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()         (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)\r\n\r\n/**\r\n  * @brief Clear the RTC Tamper and Timestamp associated Exti line flag.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()       (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)\r\n\r\n/**\r\n  * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()    (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup RTCEx_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n\r\n/* RTC TimeStamp and Tamper functions *****************************************/\r\nHAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);\r\nHAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);\r\nHAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);\r\nHAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc);\r\nHAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc);\r\nHAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);\r\n\r\nHAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);\r\nHAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);\r\nHAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);\r\nvoid              HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);\r\n\r\nvoid              HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);\r\nvoid              HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);\r\nvoid              HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc);\r\nvoid              HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);\r\nHAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup RTCEx_Exported_Functions_Group2\r\n  * @{\r\n  */\r\n/* RTC Wake-up functions ******************************************************/\r\nHAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);\r\nHAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);\r\nuint32_t          HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);\r\nuint32_t          HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);\r\nvoid              HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);\r\nvoid              HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);\r\nHAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup RTCEx_Exported_Functions_Group3\r\n  * @{\r\n  */\r\n/* Extension Control functions ************************************************/\r\nvoid              HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);\r\nuint32_t          HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);\r\n\r\nHAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue);\r\nHAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);\r\nHAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);\r\nHAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);\r\nHAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);\r\nHAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);\r\nHAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);\r\nHAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup RTCEx_Exported_Functions_Group4\r\n  * @{\r\n  */\r\n/* Extension RTC features functions *******************************************/\r\nvoid              HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); \r\nHAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n/* Private types -------------------------------------------------------------*/ \r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup RTCEx_Private_Constants RTCEx Private Constants\r\n  * @{\r\n  */\r\n#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT  ((uint32_t)EXTI_IMR_IM21)  /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */                                               \r\n#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT       ((uint32_t)EXTI_IMR_IM22)  /*!< External interrupt line 22 Connected to the RTC Wake-up event */  \r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup RTCEx_Private_Constants RTCEx Private Constants\r\n  * @{\r\n  */\r\n/* Masks Definition */\r\n#define RTC_TAMPCR_TAMPXE     ((uint32_t) (RTC_TAMPCR_TAMP3E | RTC_TAMPCR_TAMP2E | RTC_TAMPCR_TAMP1E))\r\n#define RTC_TAMPCR_TAMPXIE    ((uint32_t) (RTC_TAMPER1_INTERRUPT | RTC_TAMPER2_INTERRUPT | RTC_TAMPER3_INTERRUPT | RTC_ALL_TAMPER_INTERRUPT))\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Private macros ------------------------------------------------------------*/   \r\n/** @defgroup RTCEx_Private_Macros RTCEx Private Macros\r\n  * @{\r\n  */\r\n\r\n/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters\r\n  * @{\r\n  */\r\n#define IS_RTC_OUTPUT(__OUTPUT__)      (((__OUTPUT__) == RTC_OUTPUT_DISABLE) || \\\r\n                                        ((__OUTPUT__) == RTC_OUTPUT_ALARMA)  || \\\r\n                                        ((__OUTPUT__) == RTC_OUTPUT_ALARMB)  || \\\r\n                                        ((__OUTPUT__) == RTC_OUTPUT_WAKEUP))\r\n#define IS_RTC_BKP(__BKP__)               ((__BKP__) < (uint32_t) RTC_BKP_NUMBER)\r\n#define IS_TIMESTAMP_EDGE(__EDGE__) (((__EDGE__) == RTC_TIMESTAMPEDGE_RISING) || \\\r\n                                     ((__EDGE__) == RTC_TIMESTAMPEDGE_FALLING))\r\n#define IS_RTC_TAMPER(__TAMPER__)   ((((__TAMPER__) & ((uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXE))) == 0x00U) && ((__TAMPER__) != (uint32_t)RESET))\r\n\r\n#define IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__)  ((((__INTERRUPT__) & (uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXIE)) == 0x00U) && ((__INTERRUPT__) != (uint32_t)RESET))\r\n\r\n#define IS_RTC_TIMESTAMP_PIN(__PIN__) (((__PIN__) == RTC_TIMESTAMPPIN_DEFAULT) || \\\r\n                                       ((__PIN__) == RTC_TIMESTAMPPIN_POS1)  || \\\r\n                                       ((__PIN__) == RTC_TIMESTAMPPIN_POS2))\r\n#define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE) || \\\r\n                                        ((__TRIGGER__) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \\\r\n                                        ((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL) || \\\r\n                                        ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL))\r\n#define IS_RTC_TAMPER_ERASE_MODE(__MODE__)             (((__MODE__) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \\\r\n                                                        ((__MODE__) == RTC_TAMPER_ERASE_BACKUP_DISABLE))\r\n#define IS_RTC_TAMPER_MASKFLAG_STATE(__STATE__)     (((__STATE__) == RTC_TAMPERMASK_FLAG_ENABLE) || \\\r\n                                                     ((__STATE__) == RTC_TAMPERMASK_FLAG_DISABLE))\r\n#define IS_RTC_TAMPER_FILTER(__FILTER__)  (((__FILTER__) == RTC_TAMPERFILTER_DISABLE) || \\\r\n                                       ((__FILTER__) == RTC_TAMPERFILTER_2SAMPLE) || \\\r\n                                       ((__FILTER__) == RTC_TAMPERFILTER_4SAMPLE) || \\\r\n                                       ((__FILTER__) == RTC_TAMPERFILTER_8SAMPLE))\r\n#define IS_RTC_TAMPER_SAMPLING_FREQ(__FREQ__) (((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \\\r\n                                           ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \\\r\n                                           ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \\\r\n                                           ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \\\r\n                                           ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \\\r\n                                           ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \\\r\n                                           ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512)  || \\\r\n                                           ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))\r\n#define IS_RTC_TAMPER_PRECHARGE_DURATION(__DURATION__) (((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \\\r\n                                                    ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \\\r\n                                                    ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \\\r\n                                                    ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))\r\n#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(__DETECTION__) (((__DETECTION__) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \\\r\n                                                              ((__DETECTION__) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))\r\n#define IS_RTC_TAMPER_PULLUP_STATE(__STATE__) (((__STATE__) == RTC_TAMPER_PULLUP_ENABLE) || \\\r\n                                       ((__STATE__) == RTC_TAMPER_PULLUP_DISABLE))\r\n#define IS_RTC_WAKEUP_CLOCK(__CLOCK__) (((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV16)       || \\\r\n                                    ((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV8)    || \\\r\n                                    ((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV4)    || \\\r\n                                    ((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV2)    || \\\r\n                                    ((__CLOCK__) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \\\r\n                                    ((__CLOCK__) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))\r\n\r\n#define IS_RTC_WAKEUP_COUNTER(__COUNTER__)  ((__COUNTER__) <= 0xFFFF)\r\n#define IS_RTC_SMOOTH_CALIB_PERIOD(__PERIOD__) (((__PERIOD__) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \\\r\n                                                ((__PERIOD__) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \\\r\n                                                ((__PERIOD__) == RTC_SMOOTHCALIB_PERIOD_8SEC))\r\n#define IS_RTC_SMOOTH_CALIB_PLUS(__PLUS__) (((__PLUS__) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \\\r\n                                            ((__PLUS__) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))\r\n#define  IS_RTC_SMOOTH_CALIB_MINUS(__VALUE__) ((__VALUE__) <= 0x000001FF)\r\n#define IS_RTC_SHIFT_ADD1S(__SEL__) (((__SEL__) == RTC_SHIFTADD1S_RESET) || \\\r\n                                     ((__SEL__) == RTC_SHIFTADD1S_SET))\r\n#define IS_RTC_SHIFT_SUBFS(__FS__) ((__FS__) <= 0x00007FFF)\r\n#define IS_RTC_CALIB_OUTPUT(__OUTPUT__)  (((__OUTPUT__) == RTC_CALIBOUTPUT_512HZ) || \\\r\n                                          ((__OUTPUT__) == RTC_CALIBOUTPUT_1HZ))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_RTC_EX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sai.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_sai.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of SAI HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_SAI_H\r\n#define __STM32F7xx_HAL_SAI_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup SAI\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup SAI_Exported_Types SAI Exported Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  HAL State structures definition\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_SAI_STATE_RESET    = 0x00U,  /*!< SAI not yet initialized or disabled                */\r\n  HAL_SAI_STATE_READY    = 0x01U,  /*!< SAI initialized and ready for use                  */\r\n  HAL_SAI_STATE_BUSY     = 0x02U,  /*!< SAI internal process is ongoing                    */\r\n  HAL_SAI_STATE_BUSY_TX  = 0x12U,  /*!< Data transmission process is ongoing               */\r\n  HAL_SAI_STATE_BUSY_RX  = 0x22U,  /*!< Data reception process is ongoing                  */\r\n}HAL_SAI_StateTypeDef;\r\n\r\n/**\r\n  * @brief  SAI Callback prototype\r\n  */\r\ntypedef void (*SAIcallback)(void);\r\n\r\n/** @defgroup SAI_Init_Structure_definition SAI Init Structure definition\r\n  * @brief  SAI Init Structure definition\r\n  * @{\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t AudioMode;           /*!< Specifies the SAI Block audio Mode.\r\n                                     This parameter can be a value of @ref SAI_Block_Mode */\r\n\r\n  uint32_t Synchro;             /*!< Specifies SAI Block synchronization\r\n                                     This parameter can be a value of @ref SAI_Block_Synchronization */\r\n\r\n  uint32_t SynchroExt;          /*!< Specifies SAI external output synchronization, this setup is common\r\n                                     for BlockA and BlockB\r\n                                     This parameter can be a value of @ref SAI_Block_SyncExt\r\n                                     @note: If both audio blocks of same SAI are used, this parameter has\r\n                                            to be set to the same value for each audio block */\r\n\r\n  uint32_t OutputDrive;         /*!< Specifies when SAI Block outputs are driven.\r\n                                     This parameter can be a value of @ref SAI_Block_Output_Drive\r\n                                     @note this value has to be set before enabling the audio block\r\n                                     but after the audio block configuration. */\r\n\r\n  uint32_t NoDivider;           /*!< Specifies whether master clock will be divided or not.\r\n                                     This parameter can be a value of @ref SAI_Block_NoDivider\r\n                                     @note: If bit NODIV in the SAI_xCR1 register is cleared, the frame length\r\n                                            should be aligned to a number equal to a power of 2, from 8 to 256.\r\n                                            If bit NODIV in the SAI_xCR1 register is set, the frame length can\r\n                                            take any of the values without constraint since the input clock of\r\n                                            the audio block should be equal to the bit clock.\r\n                                            There is no MCLK_x clock which can be output. */\r\n\r\n  uint32_t FIFOThreshold;       /*!< Specifies SAI Block FIFO threshold.\r\n                                     This parameter can be a value of @ref SAI_Block_Fifo_Threshold */\r\n\r\n  uint32_t AudioFrequency;      /*!< Specifies the audio frequency sampling.\r\n                                     This parameter can be a value of @ref SAI_Audio_Frequency */\r\n\r\n  uint32_t Mckdiv;              /*!< Specifies the master clock divider, the parameter will be used if for\r\n                                     AudioFrequency the user choice\r\n                                     This parameter must be a number between Min_Data = 0 and Max_Data = 15 */\r\n\r\n  uint32_t MonoStereoMode;      /*!< Specifies if the mono or stereo mode is selected.\r\n                                     This parameter can be a value of @ref SAI_Mono_Stereo_Mode */\r\n\r\n  uint32_t CompandingMode;      /*!< Specifies the companding mode type.\r\n                                     This parameter can be a value of @ref SAI_Block_Companding_Mode */\r\n\r\n  uint32_t TriState;            /*!< Specifies the companding mode type.\r\n                                     This parameter can be a value of @ref SAI_TRIState_Management */\r\n\r\n  /* This part of the structure is automatically filled if your are using the high level initialisation\r\n     function HAL_SAI_InitProtocol */\r\n\r\n  uint32_t Protocol;        /*!< Specifies the SAI Block protocol.\r\n                                 This parameter can be a value of @ref SAI_Block_Protocol */\r\n\r\n  uint32_t DataSize;        /*!< Specifies the SAI Block data size.\r\n                                 This parameter can be a value of @ref SAI_Block_Data_Size */\r\n\r\n  uint32_t FirstBit;        /*!< Specifies whether data transfers start from MSB or LSB bit.\r\n                                 This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */\r\n\r\n  uint32_t ClockStrobing;   /*!< Specifies the SAI Block clock strobing edge sensitivity.\r\n                                 This parameter can be a value of @ref SAI_Block_Clock_Strobing */\r\n}SAI_InitTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition\r\n  * @brief  SAI Frame Init structure definition\r\n  * @{\r\n  */\r\ntypedef struct\r\n{\r\n\r\n  uint32_t FrameLength;        /*!< Specifies the Frame length, the number of SCK clocks for each audio frame.\r\n                                    This parameter must be a number between Min_Data = 8 and Max_Data = 256.\r\n                                    @note: If master clock MCLK_x pin is declared as an output, the frame length\r\n                                           should be aligned to a number equal to power of 2 in order to keep\r\n                                           in an audio frame, an integer number of MCLK pulses by bit Clock. */\r\n\r\n  uint32_t ActiveFrameLength;  /*!< Specifies the Frame synchronization active level length.\r\n                                    This Parameter specifies the length in number of bit clock (SCK + 1)\r\n                                    of the active level of FS signal in audio frame.\r\n                                    This parameter must be a number between Min_Data = 1 and Max_Data = 128 */\r\n\r\n  uint32_t FSDefinition;       /*!< Specifies the Frame synchronization definition.\r\n                                    This parameter can be a value of @ref SAI_Block_FS_Definition */\r\n\r\n  uint32_t FSPolarity;         /*!< Specifies the Frame synchronization Polarity.\r\n                                    This parameter can be a value of @ref SAI_Block_FS_Polarity */\r\n\r\n  uint32_t FSOffset;           /*!< Specifies the Frame synchronization Offset.\r\n                                    This parameter can be a value of @ref SAI_Block_FS_Offset */\r\n\r\n}SAI_FrameInitTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition\r\n  * @brief   SAI Block Slot Init Structure definition\r\n  * @{\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t FirstBitOffset;  /*!< Specifies the position of first data transfer bit in the slot.\r\n                                 This parameter must be a number between Min_Data = 0 and Max_Data = 24 */\r\n\r\n  uint32_t SlotSize;        /*!< Specifies the Slot Size.\r\n                                 This parameter can be a value of @ref SAI_Block_Slot_Size */\r\n\r\n  uint32_t SlotNumber;      /*!< Specifies the number of slot in the audio frame.\r\n                                 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */\r\n\r\n  uint32_t SlotActive;      /*!< Specifies the slots in audio frame that will be activated.\r\n                                 This parameter can be a value of @ref SAI_Block_Slot_Active */\r\n}SAI_SlotInitTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Handle_Structure_definition SAI Handle Structure definition\r\n  * @brief  SAI handle Structure definition\r\n  * @{\r\n  */\r\ntypedef struct __SAI_HandleTypeDef\r\n{\r\n  SAI_Block_TypeDef         *Instance;    /*!< SAI Blockx registers base address */\r\n\r\n  SAI_InitTypeDef           Init;         /*!< SAI communication parameters */\r\n\r\n  SAI_FrameInitTypeDef      FrameInit;    /*!< SAI Frame configuration parameters */\r\n\r\n  SAI_SlotInitTypeDef       SlotInit;     /*!< SAI Slot configuration parameters */\r\n\r\n  uint8_t                  *pBuffPtr;     /*!< Pointer to SAI transfer Buffer */\r\n\r\n  uint16_t                  XferSize;     /*!< SAI transfer size */\r\n\r\n  uint16_t                  XferCount;    /*!< SAI transfer counter */\r\n\r\n  DMA_HandleTypeDef         *hdmatx;      /*!< SAI Tx DMA handle parameters */\r\n\r\n  DMA_HandleTypeDef         *hdmarx;      /*!< SAI Rx DMA handle parameters */\r\n\r\n  SAIcallback               mutecallback; /*!< SAI mute callback */\r\n\r\n  void (*InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai); /* function pointer for IRQ handler */\r\n\r\n  HAL_LockTypeDef           Lock;         /*!< SAI locking object */\r\n\r\n  __IO HAL_SAI_StateTypeDef State;        /*!< SAI communication state */\r\n\r\n  __IO uint32_t             ErrorCode;    /*!< SAI Error code */\r\n}SAI_HandleTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup SAI_Exported_Constants SAI Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup SAI_Error_Code SAI Error Code\r\n  * @{\r\n  */\r\n#define HAL_SAI_ERROR_NONE    ((uint32_t)0x00000000U)  /*!< No error                                    */\r\n#define HAL_SAI_ERROR_OVR     ((uint32_t)0x00000001U)  /*!< Overrun Error                               */\r\n#define HAL_SAI_ERROR_UDR     ((uint32_t)0x00000002U)  /*!< Underrun error                              */\r\n#define HAL_SAI_ERROR_AFSDET  ((uint32_t)0x00000004U)  /*!< Anticipated Frame synchronisation detection */\r\n#define HAL_SAI_ERROR_LFSDET  ((uint32_t)0x00000008U)  /*!< Late Frame synchronisation detection        */\r\n#define HAL_SAI_ERROR_CNREADY ((uint32_t)0x00000010U)  /*!< codec not ready                             */\r\n#define HAL_SAI_ERROR_WCKCFG  ((uint32_t)0x00000020U)  /*!< Wrong clock configuration                   */\r\n#define HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000040U)  /*!< Timeout error                               */\r\n#define HAL_SAI_ERROR_DMA     ((uint32_t)0x00000080U)  /*!< DMA error                                   */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_SyncExt SAI External synchronisation\r\n  * @{\r\n  */\r\n#define SAI_SYNCEXT_DISABLE          0\r\n#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1\r\n#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Protocol SAI Supported protocol\r\n  * @{\r\n  */\r\n#define SAI_I2S_STANDARD      0\r\n#define SAI_I2S_MSBJUSTIFIED  1\r\n#define SAI_I2S_LSBJUSTIFIED  2\r\n#define SAI_PCM_LONG          3\r\n#define SAI_PCM_SHORT         4\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Protocol_DataSize SAI protocol data size\r\n  * @{\r\n  */\r\n#define SAI_PROTOCOL_DATASIZE_16BIT         0\r\n#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1\r\n#define SAI_PROTOCOL_DATASIZE_24BIT         2\r\n#define SAI_PROTOCOL_DATASIZE_32BIT         3\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Audio_Frequency SAI Audio Frequency\r\n  * @{\r\n  */\r\n#define SAI_AUDIO_FREQUENCY_192K          ((uint32_t)192000U)\r\n#define SAI_AUDIO_FREQUENCY_96K           ((uint32_t)96000U)\r\n#define SAI_AUDIO_FREQUENCY_48K           ((uint32_t)48000U)\r\n#define SAI_AUDIO_FREQUENCY_44K           ((uint32_t)44100U)\r\n#define SAI_AUDIO_FREQUENCY_32K           ((uint32_t)32000U)\r\n#define SAI_AUDIO_FREQUENCY_22K           ((uint32_t)22050U)\r\n#define SAI_AUDIO_FREQUENCY_16K           ((uint32_t)16000U)\r\n#define SAI_AUDIO_FREQUENCY_11K           ((uint32_t)11025U)\r\n#define SAI_AUDIO_FREQUENCY_8K            ((uint32_t)8000U)\r\n#define SAI_AUDIO_FREQUENCY_MCKDIV        ((uint32_t)0U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_Mode SAI Block Mode\r\n  * @{\r\n  */\r\n#define SAI_MODEMASTER_TX         ((uint32_t)0x00000000U)\r\n#define SAI_MODEMASTER_RX         ((uint32_t)SAI_xCR1_MODE_0)\r\n#define SAI_MODESLAVE_TX          ((uint32_t)SAI_xCR1_MODE_1)\r\n#define SAI_MODESLAVE_RX          ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0))\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_Protocol SAI Block Protocol\r\n  * @{\r\n  */\r\n#define SAI_FREE_PROTOCOL                 ((uint32_t)0x00000000U)\r\n#define SAI_SPDIF_PROTOCOL                ((uint32_t)SAI_xCR1_PRTCFG_0)\r\n#define SAI_AC97_PROTOCOL                 ((uint32_t)SAI_xCR1_PRTCFG_1)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_Data_Size SAI Block Data Size\r\n  * @{\r\n  */\r\n#define SAI_DATASIZE_8     ((uint32_t)SAI_xCR1_DS_1)\r\n#define SAI_DATASIZE_10    ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0))\r\n#define SAI_DATASIZE_16    ((uint32_t)SAI_xCR1_DS_2)\r\n#define SAI_DATASIZE_20    ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0))\r\n#define SAI_DATASIZE_24    ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1))\r\n#define SAI_DATASIZE_32    ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission\r\n  * @{\r\n  */\r\n#define SAI_FIRSTBIT_MSB                  ((uint32_t)0x00000000U)\r\n#define SAI_FIRSTBIT_LSB                  ((uint32_t)SAI_xCR1_LSBFIRST)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing\r\n  * @{\r\n  */\r\n#define SAI_CLOCKSTROBING_FALLINGEDGE     0\r\n#define SAI_CLOCKSTROBING_RISINGEDGE      1\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_Synchronization SAI Block Synchronization\r\n  * @{\r\n  */\r\n#define SAI_ASYNCHRONOUS                  0 /*!< Asynchronous */\r\n#define SAI_SYNCHRONOUS                   1 /*!< Synchronous with other block of same SAI */\r\n#define SAI_SYNCHRONOUS_EXT_SAI1          2 /*!< Synchronous with other SAI, SAI1 */\r\n#define SAI_SYNCHRONOUS_EXT_SAI2          3 /*!< Synchronous with other SAI, SAI2 */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_Output_Drive SAI Block Output Drive\r\n  * @{\r\n  */\r\n#define SAI_OUTPUTDRIVE_DISABLE          ((uint32_t)0x00000000U)\r\n#define SAI_OUTPUTDRIVE_ENABLE           ((uint32_t)SAI_xCR1_OUTDRIV)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_NoDivider SAI Block NoDivider\r\n  * @{\r\n  */\r\n#define SAI_MASTERDIVIDER_ENABLE         ((uint32_t)0x00000000U)\r\n#define SAI_MASTERDIVIDER_DISABLE        ((uint32_t)SAI_xCR1_NODIV)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n\r\n/** @defgroup SAI_Block_FS_Definition SAI Block FS Definition\r\n  * @{\r\n  */\r\n#define SAI_FS_STARTFRAME                 ((uint32_t)0x00000000U)\r\n#define SAI_FS_CHANNEL_IDENTIFICATION     ((uint32_t)SAI_xFRCR_FSDEF)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity\r\n  * @{\r\n  */\r\n#define SAI_FS_ACTIVE_LOW                  ((uint32_t)0x00000000U)\r\n#define SAI_FS_ACTIVE_HIGH                 ((uint32_t)SAI_xFRCR_FSPOL)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_FS_Offset SAI Block FS Offset\r\n  * @{\r\n  */\r\n#define SAI_FS_FIRSTBIT                   ((uint32_t)0x00000000U)\r\n#define SAI_FS_BEFOREFIRSTBIT             ((uint32_t)SAI_xFRCR_FSOFF)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n\r\n  /** @defgroup SAI_Block_Slot_Size SAI Block Slot Size\r\n  * @{\r\n  */\r\n#define SAI_SLOTSIZE_DATASIZE             ((uint32_t)0x00000000U)\r\n#define SAI_SLOTSIZE_16B                  ((uint32_t)SAI_xSLOTR_SLOTSZ_0)\r\n#define SAI_SLOTSIZE_32B                  ((uint32_t)SAI_xSLOTR_SLOTSZ_1)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_Slot_Active SAI Block Slot Active\r\n  * @{\r\n  */\r\n#define SAI_SLOT_NOTACTIVE           ((uint32_t)0x00000000U)\r\n#define SAI_SLOTACTIVE_0             ((uint32_t)0x00000001U)\r\n#define SAI_SLOTACTIVE_1             ((uint32_t)0x00000002U)\r\n#define SAI_SLOTACTIVE_2             ((uint32_t)0x00000004U)\r\n#define SAI_SLOTACTIVE_3             ((uint32_t)0x00000008U)\r\n#define SAI_SLOTACTIVE_4             ((uint32_t)0x00000010U)\r\n#define SAI_SLOTACTIVE_5             ((uint32_t)0x00000020U)\r\n#define SAI_SLOTACTIVE_6             ((uint32_t)0x00000040U)\r\n#define SAI_SLOTACTIVE_7             ((uint32_t)0x00000080U)\r\n#define SAI_SLOTACTIVE_8             ((uint32_t)0x00000100U)\r\n#define SAI_SLOTACTIVE_9             ((uint32_t)0x00000200U)\r\n#define SAI_SLOTACTIVE_10            ((uint32_t)0x00000400U)\r\n#define SAI_SLOTACTIVE_11            ((uint32_t)0x00000800U)\r\n#define SAI_SLOTACTIVE_12            ((uint32_t)0x00001000U)\r\n#define SAI_SLOTACTIVE_13            ((uint32_t)0x00002000U)\r\n#define SAI_SLOTACTIVE_14            ((uint32_t)0x00004000U)\r\n#define SAI_SLOTACTIVE_15            ((uint32_t)0x00008000U)\r\n#define SAI_SLOTACTIVE_ALL           ((uint32_t)0x0000FFFFU)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode\r\n  * @{\r\n  */\r\n#define SAI_STEREOMODE               ((uint32_t)0x00000000U)\r\n#define SAI_MONOMODE                 ((uint32_t)SAI_xCR1_MONO)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_TRIState_Management SAI TRIState Management\r\n  * @{\r\n  */\r\n#define SAI_OUTPUT_NOTRELEASED        ((uint32_t)0x00000000U)\r\n#define SAI_OUTPUT_RELEASED           ((uint32_t)SAI_xCR2_TRIS)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold\r\n  * @{\r\n  */\r\n#define SAI_FIFOTHRESHOLD_EMPTY  ((uint32_t)0x00000000U)\r\n#define SAI_FIFOTHRESHOLD_1QF    ((uint32_t)(SAI_xCR2_FTH_0))\r\n#define SAI_FIFOTHRESHOLD_HF     ((uint32_t)(SAI_xCR2_FTH_1))\r\n#define SAI_FIFOTHRESHOLD_3QF    ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0))\r\n#define SAI_FIFOTHRESHOLD_FULL   ((uint32_t)(SAI_xCR2_FTH_2))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode\r\n  * @{\r\n  */\r\n#define SAI_NOCOMPANDING                 ((uint32_t)0x00000000U)\r\n#define SAI_ULAW_1CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1))\r\n#define SAI_ALAW_1CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0))\r\n#define SAI_ULAW_2CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL))\r\n#define SAI_ALAW_2CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_Mute_Value SAI Block Mute Value\r\n  * @{\r\n  */\r\n#define SAI_ZERO_VALUE                   ((uint32_t)0x00000000U)\r\n#define SAI_LAST_SENT_VALUE              ((uint32_t)SAI_xCR2_MUTEVAL)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition\r\n  * @{\r\n  */\r\n#define SAI_IT_OVRUDR                     ((uint32_t)SAI_xIMR_OVRUDRIE)\r\n#define SAI_IT_MUTEDET                    ((uint32_t)SAI_xIMR_MUTEDETIE)\r\n#define SAI_IT_WCKCFG                     ((uint32_t)SAI_xIMR_WCKCFGIE)\r\n#define SAI_IT_FREQ                       ((uint32_t)SAI_xIMR_FREQIE)\r\n#define SAI_IT_CNRDY                      ((uint32_t)SAI_xIMR_CNRDYIE)\r\n#define SAI_IT_AFSDET                     ((uint32_t)SAI_xIMR_AFSDETIE)\r\n#define SAI_IT_LFSDET                     ((uint32_t)SAI_xIMR_LFSDETIE)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_Flags_Definition  SAI Block Flags Definition\r\n  * @{\r\n  */\r\n#define SAI_FLAG_OVRUDR                   ((uint32_t)SAI_xSR_OVRUDR)\r\n#define SAI_FLAG_MUTEDET                  ((uint32_t)SAI_xSR_MUTEDET)\r\n#define SAI_FLAG_WCKCFG                   ((uint32_t)SAI_xSR_WCKCFG)\r\n#define SAI_FLAG_FREQ                     ((uint32_t)SAI_xSR_FREQ)\r\n#define SAI_FLAG_CNRDY                    ((uint32_t)SAI_xSR_CNRDY)\r\n#define SAI_FLAG_AFSDET                   ((uint32_t)SAI_xSR_AFSDET)\r\n#define SAI_FLAG_LFSDET                   ((uint32_t)SAI_xSR_LFSDET)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_Fifo_Status_Level   SAI Block Fifo Status Level\r\n  * @{\r\n  */\r\n#define SAI_FIFOSTATUS_EMPTY              ((uint32_t)0x00000000U)\r\n#define SAI_FIFOSTATUS_LESS1QUARTERFULL   ((uint32_t)0x00010000U)\r\n#define SAI_FIFOSTATUS_1QUARTERFULL       ((uint32_t)0x00020000U)\r\n#define SAI_FIFOSTATUS_HALFFULL           ((uint32_t)0x00030000U)\r\n#define SAI_FIFOSTATUS_3QUARTERFULL       ((uint32_t)0x00040000U)\r\n#define SAI_FIFOSTATUS_FULL               ((uint32_t)0x00050000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n\r\n/** @defgroup SAI_Exported_Macros SAI Exported Macros\r\n *  @brief macros to handle interrupts and specific configurations\r\n * @{\r\n */\r\n\r\n/** @brief Reset SAI handle state.\r\n  * @param  __HANDLE__ specifies the SAI Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)\r\n\r\n/** @brief  Enable or disable the specified SAI interrupts.\r\n  * @param  __HANDLE__ specifies the SAI Handle.\r\n  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable\r\n  *            @arg SAI_IT_MUTEDET: Mute detection interrupt enable\r\n  *            @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable\r\n  *            @arg SAI_IT_FREQ: FIFO request interrupt enable\r\n  *            @arg SAI_IT_CNRDY: Codec not ready interrupt enable\r\n  *            @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable\r\n  *            @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable\r\n  * @retval None\r\n  */\r\n#define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))\r\n#define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))\r\n\r\n/** @brief  Check whether the specified SAI interrupt source is enabled or not.\r\n  * @param  __HANDLE__ specifies the SAI Handle.\r\n  * @param  __INTERRUPT__ specifies the SAI interrupt source to check.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable\r\n  *            @arg SAI_IT_MUTEDET: Mute detection interrupt enable\r\n  *            @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable\r\n  *            @arg SAI_IT_FREQ: FIFO request interrupt enable\r\n  *            @arg SAI_IT_CNRDY: Codec not ready interrupt enable\r\n  *            @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable\r\n  *            @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable\r\n  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r\n\r\n/** @brief  Check whether the specified SAI flag is set or not.\r\n  * @param  __HANDLE__ specifies the SAI Handle.\r\n  * @param  __FLAG__ specifies the flag to check.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg SAI_FLAG_OVRUDR: Overrun underrun flag.\r\n  *            @arg SAI_FLAG_MUTEDET: Mute detection flag.\r\n  *            @arg SAI_FLAG_WCKCFG: Wrong Clock Configuration flag.\r\n  *            @arg SAI_FLAG_FREQ: FIFO request flag.\r\n  *            @arg SAI_FLAG_CNRDY: Codec not ready flag.\r\n  *            @arg SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag.\r\n  *            @arg SAI_FLAG_LFSDET: Late frame synchronization detection flag.\r\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))\r\n\r\n/** @brief  Clear the specified SAI pending flag.\r\n  * @param  __HANDLE__ specifies the SAI Handle.\r\n  * @param  __FLAG__ specifies the flag to check.\r\n  *          This parameter can be any combination of the following values:\r\n  *            @arg SAI_FLAG_OVRUDR: Clear Overrun underrun\r\n  *            @arg SAI_FLAG_MUTEDET: Clear Mute detection\r\n  *            @arg SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration\r\n  *            @arg SAI_FLAG_FREQ: Clear FIFO request\r\n  *            @arg SAI_FLAG_CNRDY: Clear Codec not ready\r\n  *            @arg SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection\r\n  *            @arg SAI_FLAG_LFSDET: Clear Late frame synchronization detection\r\n  *\r\n  * @retval None\r\n  */\r\n#define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))\r\n\r\n#define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |=  SAI_xCR1_SAIEN)\r\n#define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &=  ~SAI_xCR1_SAIEN)\r\n\r\n /**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @addtogroup SAI_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/* Initialization/de-initialization functions  ********************************/\r\n\r\n/** @addtogroup SAI_Exported_Functions_Group1\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);\r\nHAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai);\r\nHAL_StatusTypeDef HAL_SAI_DeInit (SAI_HandleTypeDef *hsai);\r\nvoid HAL_SAI_MspInit(SAI_HandleTypeDef *hsai);\r\nvoid HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* I/O operation functions  ***************************************************/\r\n\r\n/** @addtogroup SAI_Exported_Functions_Group2\r\n  * @{\r\n  */\r\n/* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r\n\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);\r\n\r\n/* Non-Blocking mode: DMA */\r\nHAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai);\r\nHAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai);\r\nHAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai);\r\n\r\n/* Abort function */\r\nHAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai);\r\n\r\n/* Mute management */\r\nHAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val);\r\nHAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai);\r\nHAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter);\r\nHAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai);\r\n\r\n/* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */\r\nvoid HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai);\r\nvoid HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai);\r\nvoid HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai);\r\nvoid HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai);\r\nvoid HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai);\r\nvoid HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup SAI_Exported_Functions_Group3\r\n  * @{\r\n  */\r\n/* Peripheral State functions  ************************************************/\r\nHAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai);\r\nuint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @addtogroup SAI_Private_Macros\r\n  * @{\r\n  */\r\n#define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE)          ||\\\r\n                                     ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\\\r\n                                     ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE))\r\n\r\n#define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL)   (((PROTOCOL) == SAI_I2S_STANDARD)     ||\\\r\n                                               ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\\\r\n                                               ((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\\\r\n                                               ((PROTOCOL) == SAI_PCM_LONG)         ||\\\r\n                                               ((PROTOCOL) == SAI_PCM_SHORT))\r\n\r\n#define IS_SAI_PROTOCOL_DATASIZE(DATASIZE)   (((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT)         ||\\\r\n                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\\\r\n                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT)         ||\\\r\n                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT))\r\n\r\n#define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \\\r\n                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_48K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \\\r\n                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_32K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \\\r\n                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_16K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \\\r\n                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_8K)   || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV))\r\n\r\n#define IS_SAI_BLOCK_MODE(MODE)  (((MODE) == SAI_MODEMASTER_TX) || \\\r\n                                  ((MODE) == SAI_MODEMASTER_RX) || \\\r\n                                  ((MODE) == SAI_MODESLAVE_TX)  || \\\r\n                                  ((MODE) == SAI_MODESLAVE_RX))\r\n\r\n#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL)  || \\\r\n                                         ((PROTOCOL) == SAI_AC97_PROTOCOL)  || \\\r\n                                         ((PROTOCOL) == SAI_SPDIF_PROTOCOL))\r\n\r\n#define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8)  || \\\r\n                                         ((DATASIZE) == SAI_DATASIZE_10) || \\\r\n                                         ((DATASIZE) == SAI_DATASIZE_16) || \\\r\n                                         ((DATASIZE) == SAI_DATASIZE_20) || \\\r\n                                         ((DATASIZE) == SAI_DATASIZE_24) || \\\r\n                                         ((DATASIZE) == SAI_DATASIZE_32))\r\n\r\n#define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || \\\r\n                                     ((BIT) == SAI_FIRSTBIT_LSB))\r\n\r\n#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \\\r\n                                            ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))\r\n\r\n#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS)         || \\\r\n                                       ((SYNCHRO) == SAI_SYNCHRONOUS)          || \\\r\n                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) || \\\r\n                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2))\r\n\r\n#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \\\r\n                                          ((DRIVE) == SAI_OUTPUTDRIVE_ENABLE))\r\n\r\n#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \\\r\n                                           ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE))\r\n\r\n#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63)\r\n\r\n#define IS_SAI_BLOCK_MUTE_VALUE(VALUE)    (((VALUE) == SAI_ZERO_VALUE)     || \\\r\n                                           ((VALUE) == SAI_LAST_SENT_VALUE))\r\n\r\n#define IS_SAI_BLOCK_COMPANDING_MODE(MODE)    (((MODE) == SAI_NOCOMPANDING)         || \\\r\n                                               ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \\\r\n                                               ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \\\r\n                                               ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \\\r\n                                               ((MODE) == SAI_ALAW_2CPL_COMPANDING))\r\n\r\n#define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY)   || \\\r\n                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF)     || \\\r\n                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF)      || \\\r\n                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF)     || \\\r\n                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL))\r\n\r\n#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\\\r\n                                                 ((STATE) == SAI_OUTPUT_RELEASED))\r\n\r\n#define IS_SAI_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\\\r\n                                       ((MODE) == SAI_STEREOMODE))\r\n\r\n#define IS_SAI_SLOT_ACTIVE(ACTIVE)  ((ACTIVE) <= SAI_SLOTACTIVE_ALL)\r\n\r\n#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16))\r\n\r\n#define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \\\r\n                                      ((SIZE) == SAI_SLOTSIZE_16B)      || \\\r\n                                      ((SIZE) == SAI_SLOTSIZE_32B))\r\n\r\n#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24)\r\n\r\n#define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \\\r\n                                        ((OFFSET) == SAI_FS_BEFOREFIRSTBIT))\r\n\r\n#define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \\\r\n                                            ((POLARITY) == SAI_FS_ACTIVE_HIGH))\r\n\r\n#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \\\r\n                                                ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))\r\n\r\n#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15)\r\n\r\n#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256))\r\n\r\n#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128))\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup SAI_Private_Functions SAI Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_SAI_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sai_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_sai_ex.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of SAI Extension HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_SAI_EX_H\r\n#define __STM32F7xx_HAL_SAI_EX_H\r\n\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/    \r\n/* Exported functions --------------------------------------------------------*/\r\n/* Extended features functions ************************************************/\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/* Private macros ------------------------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n#endif /* __STM32F7xx_HAL_SAI_EX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_sd.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of SD HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_SD_H\r\n#define __STM32F7xx_HAL_SD_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_ll_sdmmc.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup SD SD\r\n  * @brief SD HAL module driver\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/ \r\n/** @defgroup SD_Exported_Types SD Exported Types\r\n  * @{\r\n  */\r\n\r\n/** @defgroup SD_Exported_Types_Group1 SD State enumeration structure\r\n  * @{\r\n  */   \r\ntypedef enum\r\n{\r\n  HAL_SD_STATE_RESET                  = ((uint32_t)0x00000000U),  /*!< SD not yet initialized or disabled  */\r\n  HAL_SD_STATE_READY                  = ((uint32_t)0x00000001U),  /*!< SD initialized and ready for use    */\r\n  HAL_SD_STATE_TIMEOUT                = ((uint32_t)0x00000002U),  /*!< SD Timeout state                    */\r\n  HAL_SD_STATE_BUSY                   = ((uint32_t)0x00000003U),  /*!< SD process ongoing                  */\r\n  HAL_SD_STATE_PROGRAMMING            = ((uint32_t)0x00000004U),  /*!< SD Programming State                */\r\n  HAL_SD_STATE_RECEIVING              = ((uint32_t)0x00000005U),  /*!< SD Receinving State                 */\r\n  HAL_SD_STATE_TRANSFER               = ((uint32_t)0x00000006U),  /*!< SD Transfert State                  */\r\n  HAL_SD_STATE_ERROR                  = ((uint32_t)0x0000000FU)   /*!< SD is in error state                */\r\n}HAL_SD_StateTypeDef;\r\n/** \r\n  * @}\r\n  */\r\n\r\n/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure\r\n  * @{\r\n  */   \r\ntypedef enum\r\n{\r\n  HAL_SD_CARD_READY                  = ((uint32_t)0x00000001U),  /*!< Card state is ready                     */\r\n  HAL_SD_CARD_IDENTIFICATION         = ((uint32_t)0x00000002U),  /*!< Card is in identification state         */\r\n  HAL_SD_CARD_STANDBY                = ((uint32_t)0x00000003U),  /*!< Card is in standby state                */\r\n  HAL_SD_CARD_TRANSFER               = ((uint32_t)0x00000004U),  /*!< Card is in transfer state               */  \r\n  HAL_SD_CARD_SENDING                = ((uint32_t)0x00000005U),  /*!< Card is sending an operation            */\r\n  HAL_SD_CARD_RECEIVING              = ((uint32_t)0x00000006U),  /*!< Card is receiving operation information */\r\n  HAL_SD_CARD_PROGRAMMING            = ((uint32_t)0x00000007U),  /*!< Card is in programming state            */\r\n  HAL_SD_CARD_DISCONNECTED           = ((uint32_t)0x00000008U),  /*!< Card is disconnected                    */\r\n  HAL_SD_CARD_ERROR                  = ((uint32_t)0x000000FFU)   /*!< Card response Error                     */\r\n}HAL_SD_CardStateTypeDef;\r\n/** \r\n  * @}\r\n  */\r\n\r\n/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition   \r\n  * @{\r\n  */\r\n#define SD_InitTypeDef      SDMMC_InitTypeDef \r\n#define SD_TypeDef          SDMMC_TypeDef\r\n\r\n/** \r\n  * @brief  SD Card Information Structure definition\r\n  */ \r\ntypedef struct\r\n{\r\n  uint32_t CardType;                     /*!< Specifies the card Type                         */\r\n  \r\n  uint32_t CardVersion;                  /*!< Specifies the card version                      */\r\n\r\n  uint32_t Class;                        /*!< Specifies the class of the card class           */\r\n\r\n  uint32_t RelCardAdd;                   /*!< Specifies the Relative Card Address             */\r\n  \r\n  uint32_t BlockNbr;                     /*!< Specifies the Card Capacity in blocks           */\r\n\r\n  uint32_t BlockSize;                    /*!< Specifies one block size in bytes               */\r\n  \r\n  uint32_t LogBlockNbr;                  /*!< Specifies the Card logical Capacity in blocks   */\r\n\r\n  uint32_t LogBlockSize;                 /*!< Specifies logical block size in bytes           */\r\n\r\n}HAL_SD_CardInfoTypeDef;\r\n\r\n/** \r\n  * @brief  SD handle Structure definition\r\n  */ \r\ntypedef struct\r\n{\r\n  SD_TypeDef                   *Instance;        /*!< SD registers base address           */\r\n  \r\n  SD_InitTypeDef               Init;             /*!< SD required parameters              */\r\n  \r\n  HAL_LockTypeDef              Lock;             /*!< SD locking object                   */\r\n  \r\n  uint32_t                     *pTxBuffPtr;      /*!< Pointer to SD Tx transfer Buffer    */\r\n\r\n  uint32_t                     TxXferSize;       /*!< SD Tx Transfer size                 */\r\n\r\n  uint32_t                     *pRxBuffPtr;      /*!< Pointer to SD Rx transfer Buffer    */\r\n\r\n  uint32_t                     RxXferSize;       /*!< SD Rx Transfer size                 */\r\n  \r\n  __IO uint32_t                Context;          /*!< SD transfer context                 */\r\n \r\n  __IO HAL_SD_StateTypeDef     State;            /*!< SD card State                       */\r\n  \r\n  __IO uint32_t                ErrorCode;        /*!< SD Card Error codes                 */  \r\n \r\n  DMA_HandleTypeDef            *hdmarx;          /*!< SD Rx DMA handle parameters         */\r\n  \r\n  DMA_HandleTypeDef            *hdmatx;          /*!< SD Tx DMA handle parameters         */\r\n  \r\n  HAL_SD_CardInfoTypeDef       SdCard;           /*!< SD Card information                 */\r\n  \r\n  uint32_t                     CSD[4];           /*!< SD card specific data table         */\r\n  \r\n  uint32_t                     CID[4];           /*!< SD card identification number table */\r\n  \r\n}SD_HandleTypeDef;\r\n\r\n/** \r\n  * @}\r\n  */\r\n\r\n/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register \r\n  * @{\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint8_t  CSDStruct;            /*!< CSD structure                         */\r\n  __IO uint8_t  SysSpecVersion;       /*!< System specification version          */\r\n  __IO uint8_t  Reserved1;            /*!< Reserved                              */\r\n  __IO uint8_t  TAAC;                 /*!< Data read access time 1               */\r\n  __IO uint8_t  NSAC;                 /*!< Data read access time 2 in CLK cycles */\r\n  __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency              */\r\n  __IO uint16_t CardComdClasses;      /*!< Card command classes                  */\r\n  __IO uint8_t  RdBlockLen;           /*!< Max. read data block length           */\r\n  __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed       */\r\n  __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment              */\r\n  __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment               */\r\n  __IO uint8_t  DSRImpl;              /*!< DSR implemented                       */\r\n  __IO uint8_t  Reserved2;            /*!< Reserved                              */\r\n  __IO uint32_t DeviceSize;           /*!< Device Size                           */\r\n  __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min           */\r\n  __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max           */\r\n  __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min          */\r\n  __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max          */\r\n  __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier                */\r\n  __IO uint8_t  EraseGrSize;          /*!< Erase group size                      */\r\n  __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier           */\r\n  __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size              */\r\n  __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable            */\r\n  __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC              */\r\n  __IO uint8_t  WrSpeedFact;          /*!< Write speed factor                    */\r\n  __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length          */\r\n  __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed      */\r\n  __IO uint8_t  Reserved3;            /*!< Reserved                              */\r\n  __IO uint8_t  ContentProtectAppli;  /*!< Content protection application        */\r\n  __IO uint8_t  FileFormatGrouop;     /*!< File format group                     */\r\n  __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP)                       */\r\n  __IO uint8_t  PermWrProtect;        /*!< Permanent write protection            */\r\n  __IO uint8_t  TempWrProtect;        /*!< Temporary write protection            */\r\n  __IO uint8_t  FileFormat;           /*!< File format                           */\r\n  __IO uint8_t  ECC;                  /*!< ECC code                              */\r\n  __IO uint8_t  CSD_CRC;              /*!< CSD CRC                               */\r\n  __IO uint8_t  Reserved4;            /*!< Always 1                              */\r\n  \r\n}HAL_SD_CardCSDTypeDef;\r\n/** \r\n  * @}\r\n  */\r\n\r\n/** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register\r\n  * @{\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint8_t  ManufacturerID;  /*!< Manufacturer ID       */\r\n  __IO uint16_t OEM_AppliID;     /*!< OEM/Application ID    */\r\n  __IO uint32_t ProdName1;       /*!< Product Name part1    */\r\n  __IO uint8_t  ProdName2;       /*!< Product Name part2    */\r\n  __IO uint8_t  ProdRev;         /*!< Product Revision      */\r\n  __IO uint32_t ProdSN;          /*!< Product Serial Number */\r\n  __IO uint8_t  Reserved1;       /*!< Reserved1             */\r\n  __IO uint16_t ManufactDate;    /*!< Manufacturing Date    */\r\n  __IO uint8_t  CID_CRC;         /*!< CID CRC               */\r\n  __IO uint8_t  Reserved2;       /*!< Always 1              */\r\n\r\n}HAL_SD_CardCIDTypeDef;\r\n/** \r\n  * @}\r\n  */\r\n\r\n/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13 \r\n  * @{\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint8_t  DataBusWidth;           /*!< Shows the currently defined data bus width                 */\r\n  __IO uint8_t  SecuredMode;            /*!< Card is in secured mode of operation                       */\r\n  __IO uint16_t CardType;               /*!< Carries information about card type                        */\r\n  __IO uint32_t ProtectedAreaSize;      /*!< Carries information about the capacity of protected area   */\r\n  __IO uint8_t  SpeedClass;             /*!< Carries information about the speed class of the card      */\r\n  __IO uint8_t  PerformanceMove;        /*!< Carries information about the card's performance move      */\r\n  __IO uint8_t  AllocationUnitSize;     /*!< Carries information about the card's allocation unit size  */\r\n  __IO uint16_t EraseSize;              /*!< Determines the number of AUs to be erased in one operation */\r\n  __IO uint8_t  EraseTimeout;           /*!< Determines the timeout for any number of AU erase          */\r\n  __IO uint8_t  EraseOffset;            /*!< Carries information about the erase offset                 */\r\n\r\n}HAL_SD_CardStatusTypeDef;\r\n/** \r\n  * @}\r\n  */\r\n\r\n/** \r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup SD_Exported_Constants Exported Constants\r\n  * @{\r\n  */\r\n\r\n#define BLOCKSIZE   ((uint32_t)512U) /*!< Block size is 512 bytes */\r\n\r\n/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition \r\n  * @{\r\n  */  \r\n#define HAL_SD_ERROR_NONE                     SDMMC_ERROR_NONE                    /*!< No error                                                      */\r\n#define HAL_SD_ERROR_CMD_CRC_FAIL             SDMMC_ERROR_CMD_CRC_FAIL            /*!< Command response received (but CRC check failed)              */\r\n#define HAL_SD_ERROR_DATA_CRC_FAIL            SDMMC_ERROR_DATA_CRC_FAIL           /*!< Data block sent/received (CRC check failed)                   */\r\n#define HAL_SD_ERROR_CMD_RSP_TIMEOUT          SDMMC_ERROR_CMD_RSP_TIMEOUT         /*!< Command response timeout                                      */\r\n#define HAL_SD_ERROR_DATA_TIMEOUT             SDMMC_ERROR_DATA_TIMEOUT            /*!< Data timeout                                                  */\r\n#define HAL_SD_ERROR_TX_UNDERRUN              SDMMC_ERROR_TX_UNDERRUN             /*!< Transmit FIFO underrun                                        */\r\n#define HAL_SD_ERROR_RX_OVERRUN               SDMMC_ERROR_RX_OVERRUN              /*!< Receive FIFO overrun                                          */\r\n#define HAL_SD_ERROR_ADDR_MISALIGNED          SDMMC_ERROR_ADDR_MISALIGNED         /*!< Misaligned address                                            */\r\n#define HAL_SD_ERROR_BLOCK_LEN_ERR            SDMMC_ERROR_BLOCK_LEN_ERR           /*!< Transferred block length is not allowed for the card or the \r\n                                                                                       number of transferred bytes does not match the block length   */\r\n#define HAL_SD_ERROR_ERASE_SEQ_ERR            SDMMC_ERROR_ERASE_SEQ_ERR           /*!< An error in the sequence of erase command occurs              */\r\n#define HAL_SD_ERROR_BAD_ERASE_PARAM          SDMMC_ERROR_BAD_ERASE_PARAM         /*!< An invalid selection for erase groups                         */\r\n#define HAL_SD_ERROR_WRITE_PROT_VIOLATION     SDMMC_ERROR_WRITE_PROT_VIOLATION    /*!< Attempt to program a write protect block                      */\r\n#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED       SDMMC_ERROR_LOCK_UNLOCK_FAILED      /*!< Sequence or password error has been detected in unlock \r\n                                                                                       command or if there was an attempt to access a locked card    */\r\n#define HAL_SD_ERROR_COM_CRC_FAILED           SDMMC_ERROR_COM_CRC_FAILED          /*!< CRC check of the previous command failed                      */\r\n#define HAL_SD_ERROR_ILLEGAL_CMD              SDMMC_ERROR_ILLEGAL_CMD             /*!< Command is not legal for the card state                       */\r\n#define HAL_SD_ERROR_CARD_ECC_FAILED          SDMMC_ERROR_CARD_ECC_FAILED         /*!< Card internal ECC was applied but failed to correct the data  */\r\n#define HAL_SD_ERROR_CC_ERR                   SDMMC_ERROR_CC_ERR                  /*!< Internal card controller error                                */\r\n#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR      SDMMC_ERROR_GENERAL_UNKNOWN_ERR     /*!< General or unknown error                                      */\r\n#define HAL_SD_ERROR_STREAM_READ_UNDERRUN     SDMMC_ERROR_STREAM_READ_UNDERRUN    /*!< The card could not sustain data reading in stream rmode       */\r\n#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN     SDMMC_ERROR_STREAM_WRITE_OVERRUN    /*!< The card could not sustain data programming in stream mode    */\r\n#define HAL_SD_ERROR_CID_CSD_OVERWRITE        SDMMC_ERROR_CID_CSD_OVERWRITE       /*!< CID/CSD overwrite error                                       */\r\n#define HAL_SD_ERROR_WP_ERASE_SKIP            SDMMC_ERROR_WP_ERASE_SKIP           /*!< Only partial address space was erased                         */\r\n#define HAL_SD_ERROR_CARD_ECC_DISABLED        SDMMC_ERROR_CARD_ECC_DISABLED       /*!< Command has been executed without using internal ECC          */\r\n#define HAL_SD_ERROR_ERASE_RESET              SDMMC_ERROR_ERASE_RESET             /*!< Erase sequence was cleared before executing because an out \r\n                                                                                       of erase sequence command was received                        */\r\n#define HAL_SD_ERROR_AKE_SEQ_ERR              SDMMC_ERROR_AKE_SEQ_ERR             /*!< Error in sequence of authentication                           */\r\n#define HAL_SD_ERROR_INVALID_VOLTRANGE        SDMMC_ERROR_INVALID_VOLTRANGE       /*!< Error in case of invalid voltage range                        */        \r\n#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE        SDMMC_ERROR_ADDR_OUT_OF_RANGE       /*!< Error when addressed block is out of range                    */        \r\n#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE   SDMMC_ERROR_REQUEST_NOT_APPLICABLE  /*!< Error when command request is not applicable                  */  \r\n#define HAL_SD_ERROR_PARAM                    SDMMC_ERROR_INVALID_PARAMETER       /*!< the used parameter is not valid                               */  \r\n#define HAL_SD_ERROR_UNSUPPORTED_FEATURE      SDMMC_ERROR_UNSUPPORTED_FEATURE     /*!< Error when feature is not insupported                         */\r\n#define HAL_SD_ERROR_BUSY                     SDMMC_ERROR_BUSY                    /*!< Error when transfer process is busy                           */ \r\n#define HAL_SD_ERROR_DMA                      SDMMC_ERROR_DMA                     /*!< Error while DMA transfer                                      */\r\n#define HAL_SD_ERROR_TIMEOUT                  SDMMC_ERROR_TIMEOUT                 /*!< Timeout error                                                 */\r\n                                                \r\n/** \r\n  * @}\r\n  */\r\n \r\n/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration\r\n  * @{\r\n  */ \r\n#define   SD_CONTEXT_NONE                 ((uint32_t)0x00000000U)  /*!< None                             */\r\n#define   SD_CONTEXT_READ_SINGLE_BLOCK    ((uint32_t)0x00000001U)  /*!< Read single block operation      */\r\n#define   SD_CONTEXT_READ_MULTIPLE_BLOCK  ((uint32_t)0x00000002U)  /*!< Read multiple blocks operation   */\r\n#define   SD_CONTEXT_WRITE_SINGLE_BLOCK   ((uint32_t)0x00000010U)  /*!< Write single block operation     */\r\n#define   SD_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U)  /*!< Write multiple blocks operation  */\r\n#define   SD_CONTEXT_IT                   ((uint32_t)0x00000008U)  /*!< Process in Interrupt mode        */\r\n#define   SD_CONTEXT_DMA                  ((uint32_t)0x00000080U)  /*!< Process in DMA mode              */  \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards\r\n  * @{\r\n  */\r\n#define CARD_SDSC                  ((uint32_t)0x00000000U)\r\n#define CARD_SDHC_SDXC             ((uint32_t)0x00000001U)\r\n#define CARD_SECURED               ((uint32_t)0x00000003U)\r\n    \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SD_Exported_Constansts_Group4 SD Supported Version\r\n  * @{\r\n  */\r\n#define CARD_V1_X                  ((uint32_t)0x00000000U)\r\n#define CARD_V2_X                  ((uint32_t)0x00000001U)\r\n/**\r\n  * @}\r\n  */\r\n      \r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup SD_Exported_macros SD Exported Macros\r\n *  @brief macros to handle interrupts and specific clock configurations\r\n * @{\r\n */\r\n \r\n/**\r\n  * @brief  Enable the SD device.\r\n  * @retval None\r\n  */ \r\n#define __HAL_SD_ENABLE(__HANDLE__) __SDMMC_ENABLE((__HANDLE__)->Instance)\r\n\r\n/**\r\n  * @brief  Disable the SD device.\r\n  * @retval None\r\n  */\r\n#define __HAL_SD_DISABLE(__HANDLE__) __SDMMC_DISABLE((__HANDLE__)->Instance)\r\n\r\n/**\r\n  * @brief  Enable the SDMMC DMA transfer.\r\n  * @retval None\r\n  */ \r\n#define __HAL_SD_DMA_ENABLE(__HANDLE__) __SDMMC_DMA_ENABLE((__HANDLE__)->Instance)\r\n\r\n/**\r\n  * @brief  Disable the SDMMC DMA transfer.\r\n  * @retval None\r\n  */\r\n#define __HAL_SD_DMA_DISABLE(__HANDLE__)  __SDMMC_DMA_DISABLE((__HANDLE__)->Instance)\r\n \r\n/**\r\n  * @brief  Enable the SD device interrupt.\r\n  * @param  __HANDLE__ SD Handle  \r\n  * @param  __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled.\r\n  *         This parameter can be one or a combination of the following values:\r\n  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r\n  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r\n  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt\r\n  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt\r\n  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r\n  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt\r\n  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt\r\n  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt\r\n  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt\r\n  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt\r\n  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt\r\n  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt\r\n  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt\r\n  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\r\n  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt\r\n  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt\r\n  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt\r\n  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt\r\n  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt\r\n  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt\r\n  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt\r\n  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disable the SD device interrupt.\r\n  * @param  __HANDLE__ SD Handle   \r\n  * @param  __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled.\r\n  *          This parameter can be one or a combination of the following values:\r\n  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r\n  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r\n  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt\r\n  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt\r\n  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r\n  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt\r\n  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt\r\n  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt\r\n  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt\r\n  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt\r\n  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt\r\n  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt\r\n  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt\r\n  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\r\n  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt\r\n  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt\r\n  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt\r\n  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt\r\n  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt\r\n  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt\r\n  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt\r\n  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt   \r\n  * @retval None\r\n  */\r\n#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Check whether the specified SD flag is set or not. \r\n  * @param  __HANDLE__ SD Handle   \r\n  * @param  __FLAG__ specifies the flag to check. \r\n  *          This parameter can be one of the following values:\r\n  *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)\r\n  *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)\r\n  *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout\r\n  *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout\r\n  *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error\r\n  *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error\r\n  *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)\r\n  *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)\r\n  *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)\r\n  *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)\r\n  *            @arg SDMMC_FLAG_CMDACT:   Command transfer in progress\r\n  *            @arg SDMMC_FLAG_TXACT:    Data transmit in progress\r\n  *            @arg SDMMC_FLAG_RXACT:    Data receive in progress\r\n  *            @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty\r\n  *            @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full\r\n  *            @arg SDMMC_FLAG_TXFIFOF:  Transmit FIFO full\r\n  *            @arg SDMMC_FLAG_RXFIFOF:  Receive FIFO full\r\n  *            @arg SDMMC_FLAG_TXFIFOE:  Transmit FIFO empty\r\n  *            @arg SDMMC_FLAG_RXFIFOE:  Receive FIFO empty\r\n  *            @arg SDMMC_FLAG_TXDAVL:   Data available in transmit FIFO\r\n  *            @arg SDMMC_FLAG_RXDAVL:   Data available in receive FIFO\r\n  *            @arg SDMMC_FLAG_SDIOIT:   SD I/O interrupt received\r\n  * @retval The new state of SD FLAG (SET or RESET).\r\n  */\r\n#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))\r\n\r\n/**\r\n  * @brief  Clear the SD's pending flags.\r\n  * @param  __HANDLE__ SD Handle  \r\n  * @param  __FLAG__ specifies the flag to clear.  \r\n  *          This parameter can be one or a combination of the following values:\r\n  *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)\r\n  *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)\r\n  *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout\r\n  *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout\r\n  *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error\r\n  *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error\r\n  *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)\r\n  *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)\r\n  *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)\r\n  *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)\r\n  *            @arg SDMMC_FLAG_SDIOIT:   SD I/O interrupt received\r\n  * @retval None\r\n  */\r\n#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))\r\n\r\n/**\r\n  * @brief  Check whether the specified SD interrupt has occurred or not.\r\n  * @param  __HANDLE__ SD Handle   \r\n  * @param  __INTERRUPT__ specifies the SDMMC interrupt source to check. \r\n  *          This parameter can be one of the following values:\r\n  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r\n  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r\n  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt\r\n  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt\r\n  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r\n  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt\r\n  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt\r\n  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt\r\n  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt\r\n  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt\r\n  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt\r\n  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt\r\n  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt\r\n  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\r\n  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt\r\n  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt\r\n  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt\r\n  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt\r\n  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt\r\n  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt\r\n  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt\r\n  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt\r\n  * @retval The new state of SD IT (SET or RESET).\r\n  */\r\n#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Clear the SD's interrupt pending bits.\r\n  * @param  __HANDLE__ SD Handle\r\n  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear. \r\n  *          This parameter can be one or a combination of the following values:\r\n  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r\n  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r\n  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt\r\n  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt\r\n  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r\n  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt\r\n  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt\r\n  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt\r\n  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDMMC_DCOUNT, is zero) interrupt\r\n  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup SD_Exported_Functions SD Exported Functions\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd);\r\nHAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd);\r\nHAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);\r\nvoid HAL_SD_MspInit(SD_HandleTypeDef *hsd);\r\nvoid HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions\r\n  * @{\r\n  */\r\n/* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);\r\n/* Non-Blocking mode: IT */\r\nHAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);\r\nHAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);\r\n/* Non-Blocking mode: DMA */\r\nHAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);\r\nHAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);\r\n\r\nvoid HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);\r\n\r\n/* Callback in non blocking modes (DMA) */\r\nvoid HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd);\r\nvoid HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd);\r\nvoid HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd);\r\nvoid HAL_SD_AbortCallback(SD_HandleTypeDef *hsd);\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SD_Exported_Functions_Group4 SD card related functions\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef       HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);\r\nHAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd);\r\nHAL_StatusTypeDef       HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID);\r\nHAL_StatusTypeDef       HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD);\r\nHAL_StatusTypeDef       HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus);\r\nHAL_StatusTypeDef       HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions\r\n  * @{\r\n  */\r\nHAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd);\r\nuint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd);\r\nHAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);\r\n/**\r\n  * @}\r\n  */\r\n    \r\n/* Private types -------------------------------------------------------------*/\r\n/** @defgroup SD_Private_Types SD Private Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private defines -----------------------------------------------------------*/\r\n/** @defgroup SD_Private_Defines SD Private Defines\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n          \r\n/* Private variables ---------------------------------------------------------*/\r\n/** @defgroup SD_Private_Variables SD Private Variables\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup SD_Private_Constants SD Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup SD_Private_Macros SD Private Macros\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions prototypes ----------------------------------------------*/\r\n/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup SD_Private_Functions SD Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n\r\n#endif /* __STM32F7xx_HAL_SD_H */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_sdram.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of SDRAM HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_SDRAM_H\r\n#define __STM32F7xx_HAL_SDRAM_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_ll_fmc.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup SDRAM\r\n  * @{\r\n  */ \r\n\r\n/* Exported typedef ----------------------------------------------------------*/   \r\n\r\n/** @defgroup SDRAM_Exported_Types SDRAM Exported Types\r\n  * @{\r\n  */\r\n\t \r\n/** \r\n  * @brief  HAL SDRAM State structure definition  \r\n  */ \r\ntypedef enum\r\n{\r\n  HAL_SDRAM_STATE_RESET             = 0x00U,  /*!< SDRAM not yet initialized or disabled */\r\n  HAL_SDRAM_STATE_READY             = 0x01U,  /*!< SDRAM initialized and ready for use   */\r\n  HAL_SDRAM_STATE_BUSY              = 0x02U,  /*!< SDRAM internal process is ongoing     */\r\n  HAL_SDRAM_STATE_ERROR             = 0x03U,  /*!< SDRAM error state                     */\r\n  HAL_SDRAM_STATE_WRITE_PROTECTED   = 0x04U,  /*!< SDRAM device write protected          */\r\n  HAL_SDRAM_STATE_PRECHARGED        = 0x05U   /*!< SDRAM device precharged               */\r\n  \r\n}HAL_SDRAM_StateTypeDef;\r\n\r\n/** \r\n  * @brief  SDRAM handle Structure definition  \r\n  */ \r\ntypedef struct\r\n{\r\n  FMC_SDRAM_TypeDef             *Instance;  /*!< Register base address                 */\r\n  \r\n  FMC_SDRAM_InitTypeDef         Init;       /*!< SDRAM device configuration parameters */\r\n  \r\n  __IO HAL_SDRAM_StateTypeDef   State;      /*!< SDRAM access state                    */\r\n  \r\n  HAL_LockTypeDef               Lock;       /*!< SDRAM locking object                  */ \r\n\r\n  DMA_HandleTypeDef             *hdma;      /*!< Pointer DMA handler                   */\r\n  \r\n}SDRAM_HandleTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/* Exported macro ------------------------------------------------------------*/\r\n\r\n/** @defgroup SDRAM_Exported_Macros SDRAM Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief Reset SDRAM handle state\r\n  * @param  __HANDLE__ specifies the SDRAM handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @addtogroup SDRAM_Exported_Functions SDRAM Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup SDRAM_Exported_Functions_Group1 \r\n  * @{\r\n  */\r\n\r\n/* Initialization/de-initialization functions *********************************/\r\nHAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing);\r\nHAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram);\r\nvoid HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram);\r\nvoid HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram);\r\n\r\nvoid HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram);\r\nvoid HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram);\r\nvoid HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);\r\nvoid HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup SDRAM_Exported_Functions_Group2 \r\n  * @{\r\n  */\r\n/* I/O operation functions ****************************************************/\r\nHAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);\r\nHAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);\r\nHAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);\r\nHAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);\r\nHAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);\r\nHAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);\r\n\r\nHAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t * pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);\r\nHAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @addtogroup SDRAM_Exported_Functions_Group3 \r\n  * @{\r\n  */\r\n/* SDRAM Control functions  *****************************************************/\r\nHAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram);\r\nHAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram);\r\nHAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate);\r\nHAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber);\r\nuint32_t          HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup SDRAM_Exported_Functions_Group4 \r\n  * @{\r\n  */\r\n/* SDRAM State functions ********************************************************/\r\nHAL_SDRAM_StateTypeDef  HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_SDRAM_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smartcard.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_smartcard.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of SMARTCARD HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_SMARTCARD_H\r\n#define __STM32F7xx_HAL_SMARTCARD_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup SMARTCARD\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief SMARTCARD Init Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t BaudRate;                  /*!< Configures the SmartCard communication baud rate.\r\n                                           The baud rate register is computed using the following formula:\r\n                                              Baud Rate Register = ((PCLKx) / ((hsmartcard->Init.BaudRate))) */\r\n\r\n  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.\r\n                                           This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */\r\n\r\n  uint32_t StopBits;                  /*!< Specifies the number of stop bits.\r\n                                           This parameter can be a value of @ref SMARTCARD_Stop_Bits. */\r\n\r\n  uint32_t Parity;                    /*!< Specifies the parity mode.\r\n                                           This parameter can be a value of @ref SMARTCARD_Parity\r\n                                           @note The parity is enabled by default (PCE is forced to 1).\r\n                                                 Since the WordLength is forced to 8 bits + parity, M is\r\n                                                 forced to 1 and the parity bit is the 9th bit. */\r\n \r\n  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.\r\n                                           This parameter can be a value of @ref SMARTCARD_Mode */\r\n\r\n  uint32_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.\r\n                                           This parameter can be a value of @ref SMARTCARD_Clock_Polarity */\r\n\r\n  uint32_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.\r\n                                           This parameter can be a value of @ref SMARTCARD_Clock_Phase */\r\n\r\n  uint32_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted\r\n                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.\r\n                                           This parameter can be a value of @ref SMARTCARD_Last_Bit */\r\n                                             \r\n  uint32_t OneBitSampling;            /*!< Specifies  whether a single sample or three samples' majority vote is selected.\r\n                                           Selecting the single sample method increases the receiver tolerance to clock\r\n                                           deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling */\r\n\r\n  uint32_t  Prescaler;                 /*!< Specifies the SmartCard Prescaler */\r\n  \r\n  uint32_t  GuardTime;                 /*!< Specifies the SmartCard Guard Time */\r\n  \r\n  uint16_t NACKEnable;                /*!< Specifies whether the SmartCard NACK transmission is enabled\r\n                                           in case of parity error.\r\n                                           This parameter can be a value of @ref SMARTCARD_NACK_State */\r\n                                           \r\n  uint32_t TimeOutEnable;              /*!< Specifies whether the receiver timeout is enabled. \r\n                                            This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/\r\n  \r\n  uint32_t TimeOutValue;               /*!< Specifies the receiver time out value in number of baud blocks: \r\n                                            it is used to implement the Character Wait Time (CWT) and \r\n                                            Block Wait Time (BWT). It is coded over 24 bits. */ \r\n                                           \r\n  uint32_t BlockLength;                /*!< Specifies the SmartCard Block Length in T=1 Reception mode.\r\n                                            This parameter can be any value from 0x0 to 0xFF */ \r\n                                           \r\n  uint32_t AutoRetryCount;              /*!< Specifies the SmartCard auto-retry count (number of retries in\r\n                                             receive and transmit mode). When set to 0, retransmission is \r\n                                             disabled. Otherwise, its maximum value is 7 (before signalling\r\n                                             an error) */  \r\n\r\n}SMARTCARD_InitTypeDef;\r\n\r\n/**\r\n  * @brief  SMARTCARD advanced features initalization structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t AdvFeatureInit;            /*!< Specifies which advanced SMARTCARD features is initialized. Several\r\n                                           advanced features may be initialized at the same time. This parameter\r\n                                           can be a value of @ref SMARTCARDEx_Advanced_Features_Initialization_Type */\r\n\r\n  uint32_t TxPinLevelInvert;          /*!< Specifies whether the TX pin active level is inverted.\r\n                                           This parameter can be a value of @ref SMARTCARD_Tx_Inv  */\r\n\r\n  uint32_t RxPinLevelInvert;          /*!< Specifies whether the RX pin active level is inverted.\r\n                                           This parameter can be a value of @ref SMARTCARD_Rx_Inv  */\r\n\r\n  uint32_t DataInvert;                /*!< Specifies whether data are inverted (positive/direct logic\r\n                                           vs negative/inverted logic).\r\n                                           This parameter can be a value of @ref SMARTCARD_Data_Inv */\r\n\r\n  uint32_t Swap;                      /*!< Specifies whether TX and RX pins are swapped.\r\n                                           This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */\r\n\r\n  uint32_t OverrunDisable;            /*!< Specifies whether the reception overrun detection is disabled.\r\n                                           This parameter can be a value of @ref SMARTCARD_Overrun_Disable */\r\n\r\n  uint32_t DMADisableonRxError;       /*!< Specifies whether the DMA is disabled in case of reception error.\r\n                                           This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */\r\n\r\n  uint32_t MSBFirst;                  /*!< Specifies whether MSB is sent first on UART line.\r\n                                           This parameter can be a value of @ref SMARTCARD_MSB_First */\r\n                                           \r\n  uint16_t TxCompletionIndication;     /*!< Specifies which transmission completion indication is used: before (when \r\n                                            relevant flag is available) or once guard time period has elapsed.\r\n                                           This parameter can be a value of @ref SMARTCARDEx_Transmission_Completion_Indication. */                                            \r\n}SMARTCARD_AdvFeatureInitTypeDef;\r\n\r\n/**\r\n  * @brief HAL SMARTCARD State structures definition\r\n  * @note  HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState.\r\n  *        - gState contains SMARTCARD state information related to global Handle management \r\n  *          and also information related to Tx operations.\r\n  *          gState value coding follow below described bitmap :\r\n  *          b7-b6  Error information \r\n  *             00 : No Error\r\n  *             01 : (Not Used)\r\n  *             10 : Timeout\r\n  *             11 : Error\r\n  *          b5     IP initilisation status\r\n  *             0  : Reset (IP not initialized)\r\n  *             1  : Init done (IP not initialized. HAL SMARTCARD Init function already called)\r\n  *          b4-b3  (not used)\r\n  *             xx : Should be set to 00\r\n  *          b2     Intrinsic process state\r\n  *             0  : Ready\r\n  *             1  : Busy (IP busy with some configuration or internal operations)\r\n  *          b1     (not used)\r\n  *             x  : Should be set to 0\r\n  *          b0     Tx state\r\n  *             0  : Ready (no Tx operation ongoing)\r\n  *             1  : Busy (Tx operation ongoing)\r\n  *        - RxState contains information related to Rx operations.\r\n  *          RxState value coding follow below described bitmap :\r\n  *          b7-b6  (not used)\r\n  *             xx : Should be set to 00\r\n  *          b5     IP initilisation status\r\n  *             0  : Reset (IP not initialized)\r\n  *             1  : Init done (IP not initialized)\r\n  *          b4-b2  (not used)\r\n  *            xxx : Should be set to 000\r\n  *          b1     Rx state\r\n  *             0  : Ready (no Rx operation ongoing)\r\n  *             1  : Busy (Rx operation ongoing)\r\n  *          b0     (not used)\r\n  *             x  : Should be set to 0.\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_SMARTCARD_STATE_RESET             = 0x00U,   /*!< Peripheral is not initialized\r\n                                                        Value is allowed for gState and RxState */\r\n  HAL_SMARTCARD_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use\r\n                                                        Value is allowed for gState and RxState */\r\n  HAL_SMARTCARD_STATE_BUSY              = 0x24U,   /*!< an internal process is ongoing \r\n                                                        Value is allowed for gState only */\r\n  HAL_SMARTCARD_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing\r\n                                                        Value is allowed for gState only */\r\n  HAL_SMARTCARD_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing\r\n                                                        Value is allowed for RxState only */\r\n  HAL_SMARTCARD_STATE_BUSY_TX_RX        = 0x23U,   /*!< Data Transmission and Reception process is ongoing\r\n                                                        Not to be used for neither gState nor RxState.\r\n                                                        Value is result of combination (Or) between gState and RxState values */\r\n  HAL_SMARTCARD_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state\r\n                                                        Value is allowed for gState only */\r\n  HAL_SMARTCARD_STATE_ERROR             = 0xE0U    /*!< Error\r\n                                                        Value is allowed for gState only */\r\n}HAL_SMARTCARD_StateTypeDef;\r\n\r\n/**\r\n  * @brief  SMARTCARD clock sources definition\r\n  */\r\ntypedef enum\r\n{\r\n  SMARTCARD_CLOCKSOURCE_PCLK1      = 0x00U,    /*!< PCLK1 clock source  */\r\n  SMARTCARD_CLOCKSOURCE_PCLK2      = 0x01U,    /*!< PCLK2 clock source  */\r\n  SMARTCARD_CLOCKSOURCE_HSI        = 0x02U,    /*!< HSI clock source    */\r\n  SMARTCARD_CLOCKSOURCE_SYSCLK     = 0x04U,    /*!< SYSCLK clock source */\r\n  SMARTCARD_CLOCKSOURCE_LSE        = 0x08U,    /*!< LSE clock source    */\r\n  SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10  /*!< undefined clock source */\r\n}SMARTCARD_ClockSourceTypeDef;\r\n\r\n/**\r\n  * @brief  SMARTCARD handle Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  USART_TypeDef                   *Instance;        /*!< USART registers base address                          */\r\n\r\n  SMARTCARD_InitTypeDef           Init;             /*!< SmartCard communication parameters                    */\r\n\r\n  SMARTCARD_AdvFeatureInitTypeDef AdvancedInit;     /*!< SmartCard advanced features initialization parameters */\r\n\r\n  uint8_t                         *pTxBuffPtr;      /*!< Pointer to SmartCard Tx transfer Buffer               */\r\n\r\n  uint16_t                        TxXferSize;       /*!< SmartCard Tx Transfer size                            */\r\n\r\n  __IO uint16_t                   TxXferCount;      /*!< SmartCard Tx Transfer Counter                         */\r\n\r\n  uint8_t                         *pRxBuffPtr;      /*!< Pointer to SmartCard Rx transfer Buffer               */\r\n\r\n  uint16_t                        RxXferSize;       /*!< SmartCard Rx Transfer size                            */\r\n\r\n  __IO uint16_t                   RxXferCount;      /*!< SmartCard Rx Transfer Counter                         */\r\n\r\n  DMA_HandleTypeDef               *hdmatx;          /*!< SmartCard Tx DMA Handle parameters                    */\r\n\r\n  DMA_HandleTypeDef               *hdmarx;          /*!< SmartCard Rx DMA Handle parameters                    */\r\n\r\n  HAL_LockTypeDef                 Lock;             /*!< Locking object                                        */\r\n\r\n  __IO HAL_SMARTCARD_StateTypeDef    gState;        /*!< SmartCard state information related to global Handle management \r\n                                                         and also related to Tx operations.\r\n                                                         This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */\r\n\r\n  __IO HAL_SMARTCARD_StateTypeDef    RxState;       /*!< SmartCard state information related to Rx operations.\r\n                                                         This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */\r\n\r\n  __IO uint32_t                       ErrorCode;        /* SmartCard Error code                           */\r\n\r\n}SMARTCARD_HandleTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup SMARTCARD_Exported_Constants  SMARTCARD Exported constants\r\n  * @{\r\n  */\r\n/** @defgroup SMARTCARD_Error_Code SMARTCARD Error Code\r\n  * @brief    SMARTCARD Error Code \r\n  * @{\r\n  */ \r\n#define HAL_SMARTCARD_ERROR_NONE      ((uint32_t)0x00U)    /*!< No error                */\r\n#define HAL_SMARTCARD_ERROR_PE        ((uint32_t)0x01U)    /*!< Parity error            */\r\n#define HAL_SMARTCARD_ERROR_NE        ((uint32_t)0x02U)    /*!< Noise error             */\r\n#define HAL_SMARTCARD_ERROR_FE        ((uint32_t)0x04U)    /*!< frame error             */\r\n#define HAL_SMARTCARD_ERROR_ORE       ((uint32_t)0x08U)    /*!< Overrun error           */\r\n#define HAL_SMARTCARD_ERROR_DMA       ((uint32_t)0x10U)    /*!< DMA transfer error      */\r\n#define HAL_SMARTCARD_ERROR_RTO       ((uint32_t)0x20U)    /*!< Receiver TimeOut error  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length\r\n  * @{\r\n  */\r\n#define SMARTCARD_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M_0)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits\r\n  * @{\r\n  */\r\n#define SMARTCARD_STOPBITS_1_5                   ((uint32_t)(USART_CR2_STOP))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SMARTCARD_Parity SMARTCARD Parity\r\n  * @{\r\n  */\r\n#define SMARTCARD_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)\r\n#define SMARTCARD_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SMARTCARD_Mode SMARTCARD Mode\r\n  * @{\r\n  */\r\n#define SMARTCARD_MODE_RX                        ((uint32_t)USART_CR1_RE)\r\n#define SMARTCARD_MODE_TX                        ((uint32_t)USART_CR1_TE)\r\n#define SMARTCARD_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity\r\n  * @{\r\n  */\r\n#define SMARTCARD_POLARITY_LOW                   ((uint32_t)0x0000U)\r\n#define SMARTCARD_POLARITY_HIGH                  ((uint32_t)USART_CR2_CPOL)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup SMARTCARD_Clock_Phase  SMARTCARD Clock Phase\r\n  * @{\r\n  */\r\n#define SMARTCARD_PHASE_1EDGE                    ((uint32_t)0x0000U)\r\n#define SMARTCARD_PHASE_2EDGE                    ((uint32_t)USART_CR2_CPHA)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SMARTCARD_Last_Bit  SMARTCARD Last Bit\r\n  * @{\r\n  */\r\n#define SMARTCARD_LASTBIT_DISABLE                ((uint32_t)0x0000U)\r\n#define SMARTCARD_LASTBIT_ENABLE                 ((uint32_t)USART_CR2_LBCL)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD OneBit Sampling\r\n  * @{\r\n  */\r\n#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE   ((uint32_t)0x0000U)\r\n#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE    ((uint32_t)USART_CR3_ONEBIT)\r\n/**\r\n  * @}\r\n  */  \r\n\r\n\r\n/** @defgroup SMARTCARD_NACK_State  SMARTCARD NACK State\r\n  * @{\r\n  */\r\n#define SMARTCARD_NACK_ENABLE           ((uint32_t)USART_CR3_NACK)\r\n#define SMARTCARD_NACK_DISABLE          ((uint32_t)0x0000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable\r\n  * @{\r\n  */\r\n#define SMARTCARD_TIMEOUT_DISABLE      ((uint32_t)0x00000000U)\r\n#define SMARTCARD_TIMEOUT_ENABLE       ((uint32_t)USART_CR2_RTOEN)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup SMARTCARD_DMA_Requests   SMARTCARD DMA requests\r\n  * @{\r\n  */\r\n\r\n#define SMARTCARD_DMAREQ_TX                    ((uint32_t)USART_CR3_DMAT)\r\n#define SMARTCARD_DMAREQ_RX                    ((uint32_t)USART_CR3_DMAR)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SMARTCARD_Advanced_Features_Initialization_Type SMARTCARD Advanced Features Initialization Type\r\n  * @{\r\n  */\r\n#define SMARTCARD_ADVFEATURE_NO_INIT                 ((uint32_t)0x00000000U)\r\n#define SMARTCARD_ADVFEATURE_TXINVERT_INIT           ((uint32_t)0x00000001U)\r\n#define SMARTCARD_ADVFEATURE_RXINVERT_INIT           ((uint32_t)0x00000002U)\r\n#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT         ((uint32_t)0x00000004U)\r\n#define SMARTCARD_ADVFEATURE_SWAP_INIT               ((uint32_t)0x00000008U)\r\n#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT   ((uint32_t)0x00000010U)\r\n#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT  ((uint32_t)0x00000020U)\r\n#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT           ((uint32_t)0x00000080U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SMARTCARD_Tx_Inv SMARTCARD Tx Inv\r\n  * @{\r\n  */\r\n#define SMARTCARD_ADVFEATURE_TXINV_DISABLE   ((uint32_t)0x00000000U)\r\n#define SMARTCARD_ADVFEATURE_TXINV_ENABLE    ((uint32_t)USART_CR2_TXINV)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SMARTCARD_Rx_Inv SMARTCARD Rx Inv\r\n  * @{\r\n  */\r\n#define SMARTCARD_ADVFEATURE_RXINV_DISABLE   ((uint32_t)0x00000000U)\r\n#define SMARTCARD_ADVFEATURE_RXINV_ENABLE    ((uint32_t)USART_CR2_RXINV)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SMARTCARD_Data_Inv SMARTCARD Data Inv\r\n  * @{\r\n  */\r\n#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE     ((uint32_t)0x00000000U)\r\n#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE      ((uint32_t)USART_CR2_DATAINV)\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD Rx Tx Swap\r\n  * @{\r\n  */\r\n#define SMARTCARD_ADVFEATURE_SWAP_DISABLE   ((uint32_t)0x00000000U)\r\n#define SMARTCARD_ADVFEATURE_SWAP_ENABLE    ((uint32_t)USART_CR2_SWAP)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup SMARTCARD_Overrun_Disable SMARTCARD Overrun Disable\r\n  * @{\r\n  */\r\n#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE   ((uint32_t)0x00000000U)\r\n#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE  ((uint32_t)USART_CR3_OVRDIS)\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD DMA Disable on Rx Error\r\n  * @{\r\n  */\r\n#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR       ((uint32_t)0x00000000U)\r\n#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR      ((uint32_t)USART_CR3_DDRE)\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup SMARTCARD_MSB_First SMARTCARD MSB First\r\n  * @{\r\n  */\r\n#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE      ((uint32_t)0x00000000U)\r\n#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE       ((uint32_t)USART_CR2_MSBFIRST)\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup SmartCard_Flags SMARTCARD Flags\r\n  *        Elements values convention: 0xXXXX\r\n  *           - 0xXXXX  : Flag mask in the ISR register\r\n  * @{\r\n  */\r\n#define SMARTCARD_FLAG_REACK                     ((uint32_t)0x00400000U)\r\n#define SMARTCARD_FLAG_TEACK                     ((uint32_t)0x00200000U)\r\n#define SMARTCARD_FLAG_BUSY                      ((uint32_t)0x00010000U)\r\n#define SMARTCARD_FLAG_EOBF                      ((uint32_t)0x00001000U)\r\n#define SMARTCARD_FLAG_RTOF                      ((uint32_t)0x00000800U)\r\n#define SMARTCARD_FLAG_TXE                       ((uint32_t)0x00000080U)\r\n#define SMARTCARD_FLAG_TC                        ((uint32_t)0x00000040U)\r\n#define SMARTCARD_FLAG_RXNE                      ((uint32_t)0x00000020U)\r\n#define SMARTCARD_FLAG_IDLE                      ((uint32_t)0x00000010U)\r\n#define SMARTCARD_FLAG_ORE                       ((uint32_t)0x00000008U)\r\n#define SMARTCARD_FLAG_NE                        ((uint32_t)0x00000004U)\r\n#define SMARTCARD_FLAG_FE                        ((uint32_t)0x00000002U)\r\n#define SMARTCARD_FLAG_PE                        ((uint32_t)0x00000001U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SMARTCARD_Interrupt_definition SMARTCARD Interrupt definition\r\n  *        Elements values convention: 0000ZZZZ0XXYYYYYb\r\n  *           - YYYYY  : Interrupt source position in the XX register (5bits)\r\n  *           - XX  : Interrupt source register (2bits)\r\n  *                 - 01: CR1 register\r\n  *                 - 10: CR2 register\r\n  *                 - 11: CR3 register\r\n  *           - ZZZZ  : Flag position in the ISR register(4bits)\r\n  * @{\r\n  */\r\n  \r\n#define SMARTCARD_IT_PE                          ((uint16_t)0x0028U)\r\n#define SMARTCARD_IT_TXE                         ((uint16_t)0x0727U)\r\n#define SMARTCARD_IT_TC                          ((uint16_t)0x0626U)\r\n#define SMARTCARD_IT_RXNE                        ((uint16_t)0x0525U)\r\n#define SMARTCARD_IT_IDLE                        ((uint16_t)0x0424U)\r\n#define SMARTCARD_IT_ERR                         ((uint16_t)0x0060U)\r\n#define SMARTCARD_IT_ORE                         ((uint16_t)0x0300U)\r\n#define SMARTCARD_IT_NE                          ((uint16_t)0x0200U)\r\n#define SMARTCARD_IT_FE                          ((uint16_t)0x0100U)\r\n\r\n#define SMARTCARD_IT_EOB                         ((uint16_t)0x0C3BU)\r\n#define SMARTCARD_IT_RTO                         ((uint16_t)0x0B3AU)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup SMARTCARD_IT_CLEAR_Flags SMARTCARD IT CLEAR Flags\r\n  * @{\r\n  */\r\n#define SMARTCARD_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag */          \r\n#define SMARTCARD_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag */         \r\n#define SMARTCARD_CLEAR_NEF                       USART_ICR_NCF             /*!< Noise detected Clear Flag */        \r\n#define SMARTCARD_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag */         \r\n#define SMARTCARD_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< Idle line detected clear Flag */\r\n#define SMARTCARD_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag */ \r\n#define SMARTCARD_CLEAR_RTOF                      USART_ICR_RTOCF           /*!< Receiver Time Out Clear Flag */     \r\n#define SMARTCARD_CLEAR_EOBF                      USART_ICR_EOBCF           /*!< End Of Block Clear Flag */          \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters\r\n  * @{\r\n  */        \r\n#define SMARTCARD_RXDATA_FLUSH_REQUEST        ((uint32_t)USART_RQR_RXFRQ)        /*!< Receive Data flush Request */ \r\n#define SMARTCARD_TXDATA_FLUSH_REQUEST        ((uint32_t)USART_RQR_TXFRQ)        /*!< Transmit data flush Request */\r\n/**\r\n  * @}\r\n  */\r\n  \r\n  \r\n/** @defgroup SMARTCARD_CR3_SCAR_CNT_LSB_POS SMARTCARD CR3 SCAR CNT LSB POS\r\n  * @{\r\n  */\r\n#define SMARTCARD_CR3_SCARCNT_LSB_POS            ((uint32_t) 17U)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup SMARTCARD_GTPR_GT_LSBPOS SMARTCARD GTPR GT LSBPOS\r\n  * @{\r\n  */\r\n#define SMARTCARD_GTPR_GT_LSB_POS            ((uint32_t) 8U)\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/** @defgroup SMARTCARD_RTOR_BLEN_LSBPOS SMARTCARD RTOR BLEN LSBPOS\r\n  * @{\r\n  */\r\n#define SMARTCARD_RTOR_BLEN_LSB_POS          ((uint32_t) 24U)\r\n/**\r\n  * @}\r\n  */    \r\n \r\n/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD Interruption Mask\r\n  * @{\r\n  */ \r\n#define SMARTCARD_IT_MASK  ((uint16_t)0x001FU)  \r\n/**\r\n  * @}\r\n  */\r\n    \r\n/**\r\n  * @}\r\n  */    \r\n    \r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief Reset SMARTCARD handle state\r\n  * @param  __HANDLE__ specifies the SMARTCARD Handle.\r\n  *         The Handle Instance which can be USART1 or USART2\r\n  * @retval None\r\n  */\r\n#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMARTCARD_STATE_RESET)\r\n\r\n/** @brief  Flush the Smartcard DR register \r\n  * @param  __HANDLE__ specifies the SMARTCARD Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @retval None\r\n  */\r\n#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) (__HAL_SMARTCARD_SEND_REQ((__HANDLE__), SMARTCARD_RXDATA_FLUSH_REQUEST))\r\n\r\n/** @brief  Checks whether the specified Smartcard flag is set or not.\r\n  * @param  __HANDLE__ specifies the SMARTCARD Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @param  __FLAG__ specifies the flag to check.\r\n  *        This parameter can be one of the following values:\r\n  *            @arg SMARTCARD_FLAG_REACK: Receive enable acknowledge flag\r\n  *            @arg SMARTCARD_FLAG_TEACK: Transmit enable acknowledge flag\r\n  *            @arg SMARTCARD_FLAG_BUSY:  Busy flag\r\n  *            @arg SMARTCARD_FLAG_EOBF:  End of block flag   \r\n  *            @arg SMARTCARD_FLAG_RTOF:  Receiver timeout flag\r\n  *            @arg SMARTCARD_FLAG_TXE:   Transmit data register empty flag\r\n  *            @arg SMARTCARD_FLAG_TC:    Transmission Complete flag\r\n  *            @arg SMARTCARD_FLAG_RXNE:  Receive data register not empty flag\r\n  *            @arg SMARTCARD_FLAG_ORE:   OverRun Error flag\r\n  *            @arg SMARTCARD_FLAG_NE:    Noise Error flag\r\n  *            @arg SMARTCARD_FLAG_FE:    Framing Error flag\r\n  *            @arg SMARTCARD_FLAG_PE:    Parity Error flag\r\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))\r\n\r\n/** @brief  Clear the specified SMARTCARD pending flag.\r\n  * @param  __HANDLE__ specifies the SMARTCARD Handle.\r\n  * @param  __FLAG__ specifies the flag to check.\r\n  *          This parameter can be any combination of the following values:\r\n  *            @arg @ref SMARTCARD_CLEAR_PEF    Parity error clear flag\r\n  *            @arg @ref SMARTCARD_CLEAR_FEF    Framing error clear flag\r\n  *            @arg @ref SMARTCARD_CLEAR_NEF    Noise detected clear flag\r\n  *            @arg @ref SMARTCARD_CLEAR_OREF   OverRun error clear flag\r\n  *            @arg @ref SMARTCARD_CLEAR_IDLEF  Idle line detected clear flag\r\n  *            @arg @ref SMARTCARD_CLEAR_TCF    Transmission complete clear flag\r\n  @if STM32L443xx\r\n  *            @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available)    \r\n  @endif\r\n  *            @arg @ref SMARTCARD_CLEAR_RTOF   Receiver timeout clear flag\r\n  *            @arg @ref SMARTCARD_CLEAR_EOBF   End of block clear flag\r\n  * @retval None\r\n  */\r\n#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))\r\n\r\n/** @brief  Clear the SMARTCARD PE pending flag.\r\n  * @param  __HANDLE__ specifies the SMARTCARD Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)\r\n\r\n\r\n/** @brief  Clear the SMARTCARD FE pending flag.\r\n  * @param  __HANDLE__ specifies the SMARTCARD Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)\r\n\r\n/** @brief  Clear the SMARTCARD NE pending flag.\r\n  * @param  __HANDLE__ specifies the SMARTCARD Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)\r\n\r\n/** @brief  Clear the SMARTCARD ORE pending flag.\r\n  * @param  __HANDLE__ specifies the SMARTCARD Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)\r\n\r\n/** @brief  Clear the SMARTCARD IDLE pending flag.\r\n  * @param  __HANDLE__ specifies the SMARTCARD Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)\r\n\r\n/** @brief  Enables the specified SmartCard interrupt.\r\n  * @param  __HANDLE__ specifies the SMARTCARD Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to enable.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg SMARTCARD_IT_EOBF: End Of Block interrupt\r\n  *            @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt\r\n  *            @arg SMARTCARD_IT_TXE:  Transmit Data Register empty interrupt\r\n  *            @arg SMARTCARD_IT_TC:   Transmission complete interrupt\r\n  *            @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt\r\n  *            @arg SMARTCARD_IT_PE:   Parity Error interrupt\r\n  *            @arg SMARTCARD_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)\r\n  * @retval None\r\n  */\r\n#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \\\r\n                                                        ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \\\r\n                                                        ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))\r\n/** @brief  Disables the specified SmartCard interrupt.\r\n  * @param  __HANDLE__ specifies the SMARTCARD Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to enable.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg SMARTCARD_IT_EOBF: End Of Block interrupt\r\n  *            @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt\r\n  *            @arg SMARTCARD_IT_TXE:  Transmit Data Register empty interrupt\r\n  *            @arg SMARTCARD_IT_TC:   Transmission complete interrupt\r\n  *            @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt\r\n  *            @arg SMARTCARD_IT_PE:   Parity Error interrupt\r\n  *            @arg SMARTCARD_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)\r\n  * @retval None\r\n  */\r\n#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \\\r\n                                                        ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \\\r\n                                                        ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))\r\n\r\n/** @brief  Checks whether the specified SmartCard interrupt has occurred or not.\r\n  * @param  __HANDLE__ specifies the SMARTCARD Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @param  __IT__ specifies the SMARTCARD interrupt to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg SMARTCARD_IT_EOBF: End Of Block interrupt\r\n  *            @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt  \r\n  *            @arg SMARTCARD_IT_TXE:  Transmit Data Register empty interrupt\r\n  *            @arg SMARTCARD_IT_TC:   Transmission complete interrupt\r\n  *            @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt\r\n  *            @arg SMARTCARD_IT_ORE:  OverRun Error interrupt\r\n  *            @arg SMARTCARD_IT_NE:   Noise Error interrupt\r\n  *            @arg SMARTCARD_IT_FE:   Framing Error interrupt\r\n  *            @arg SMARTCARD_IT_PE:   Parity Error interrupt\r\n  * @retval The new state of __IT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08U))) \r\n\r\n/** @brief  Checks whether the specified SmartCard interrupt interrupt source is enabled.\r\n  * @param  __HANDLE__ specifies the SMARTCARD Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @param  __IT__ specifies the SMARTCARD interrupt source to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg SMARTCARD_IT_EOBF: End Of Block interrupt\r\n  *            @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt  \r\n  *            @arg SMARTCARD_IT_TXE:  Transmit Data Register empty interrupt\r\n  *            @arg SMARTCARD_IT_TC:   Transmission complete interrupt\r\n  *            @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt\r\n  *            @arg SMARTCARD_IT_ORE:  OverRun Error interrupt\r\n  *            @arg SMARTCARD_IT_NE:   Noise Error interrupt\r\n  *            @arg SMARTCARD_IT_FE:   Framing Error interrupt\r\n  *            @arg SMARTCARD_IT_PE:   Parity Error interrupt\r\n  * @retval The new state of __IT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \\\r\n                                                               (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << \\\r\n                                                               (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK)))\r\n\r\n\r\n/** @brief  Clears the specified SMARTCARD ISR flag, in setting the proper ICR register flag.\r\n  * @param  __HANDLE__ specifies the SMARTCARD Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set\r\n  *                       to clear the corresponding interrupt\r\n  *          This parameter can be one of the following values:\r\n  *            @arg USART_CLEAR_PEF: Parity Error Clear Flag\r\n  *            @arg USART_CLEAR_FEF: Framing Error Clear Flag\r\n  *            @arg USART_CLEAR_NEF: Noise detected Clear Flag\r\n  *            @arg USART_CLEAR_OREF: OverRun Error Clear Flag\r\n  *            @arg USART_CLEAR_TCF: Transmission Complete Clear Flag\r\n  *            @arg USART_CLEAR_RTOF: Receiver Time Out Clear Flag\r\n  *            @arg USART_CLEAR_EOBF: End Of Block Clear Flag \r\n  * @retval None\r\n  */\r\n#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) \r\n\r\n/** @brief  Set a specific SMARTCARD request flag.\r\n  * @param  __HANDLE__ specifies the SMARTCARD Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @param  __REQ__ specifies the request flag to set\r\n  *          This parameter can be one of the following values:  \r\n  *            @arg SMARTCARD_RXDATA_FLUSH_REQUEST: Receive Data flush Request \r\n  *            @arg SMARTCARD_TXDATA_FLUSH_REQUEST: Transmit data flush Request \r\n  *\r\n  * @retval None\r\n  */ \r\n#define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__)) \r\n\r\n/** @brief  Enable the USART associated to the SMARTCARD Handle\r\n  * @param  __HANDLE__ specifies the SMARTCARD Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @retval None\r\n  */\r\n#define __HAL_SMARTCARD_ENABLE(__HANDLE__)               ( (__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)\r\n\r\n/** @brief  Disable the USART associated to the SMARTCARD Handle\r\n  * @param  __HANDLE__ specifies the SMARTCARD Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @retval None\r\n  */\r\n#define __HAL_SMARTCARD_DISABLE(__HANDLE__)              ( (__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)\r\n\r\n/** @brief  Macros to enable or disable the SmartCard DMA request.\r\n  * @param  __HANDLE__ specifies the SMARTCARD Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @param  __REQUEST__ specifies the SmartCard DMA request.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request\r\n  *            @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request\r\n  */\r\n#define __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__)    ((__HANDLE__)->Instance->CR3 |=  (__REQUEST__))\r\n#define __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__)   ((__HANDLE__)->Instance->CR3 &=  ~(__REQUEST__))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Include SMARTCARD HAL Extension module */\r\n#include \"stm32f7xx_hal_smartcard_ex.h\"\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup SMARTCARD_Exported_Functions\r\n  * @{\r\n  */\r\n  \r\n/** @addtogroup SMARTCARD_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n/* Initialization/de-initialization functions  **********************************/\r\nHAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard);\r\nHAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard);\r\nvoid HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard);\r\nvoid HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup SMARTCARD_Exported_Functions_Group2\r\n  * @{\r\n  */\r\n/* IO operation functions *******************************************************/\r\nHAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);\r\n/* Transfer Abort functions */\r\nHAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard);\r\nHAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard);\r\nHAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard);\r\nHAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard);\r\nHAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);\r\nHAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard);\r\n\r\nvoid HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard);\r\nvoid HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);\r\nvoid HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);\r\nvoid HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard);\r\nvoid HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);\r\nvoid HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);\r\nvoid HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup SMARTCARD_Exported_Functions_Group3\r\n  * @{\r\n  */\r\n/* Peripheral State functions  **************************************************/\r\nHAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard);\r\nuint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants\r\n  * @{\r\n  */\r\n\r\n#define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B) \r\n#define IS_SMARTCARD_STOPBITS(__STOPBITS__) ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5)\r\n#define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \\\r\n                                         ((__PARITY__) == SMARTCARD_PARITY_ODD))\r\n#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFF3) == 0x00) && ((__MODE__) != (uint32_t)0x00))\r\n#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))\r\n#define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))\r\n#define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \\\r\n                                           ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))\r\n#define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \\\r\n                                                  ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))\r\n#define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \\\r\n                                     ((__NACK__) == SMARTCARD_NACK_DISABLE))\r\n#define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \\\r\n                                           ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))\r\n#define IS_SMARTCARD_ADVFEATURE_INIT(INIT)           ((INIT) <= (SMARTCARD_ADVFEATURE_NO_INIT | \\\r\n                                                            SMARTCARD_ADVFEATURE_TXINVERT_INIT | \\\r\n                                                            SMARTCARD_ADVFEATURE_RXINVERT_INIT | \\\r\n                                                            SMARTCARD_ADVFEATURE_DATAINVERT_INIT | \\\r\n                                                            SMARTCARD_ADVFEATURE_SWAP_INIT | \\\r\n                                                            SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT | \\\r\n                                                            SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT   | \\\r\n                                                            SMARTCARD_ADVFEATURE_MSBFIRST_INIT))  \r\n#define IS_SMARTCARD_ADVFEATURE_TXINV(TXINV) (((TXINV) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \\\r\n                                         ((TXINV) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))\r\n#define IS_SMARTCARD_ADVFEATURE_RXINV(RXINV) (((RXINV) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \\\r\n                                         ((RXINV) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))\r\n#define IS_SMARTCARD_ADVFEATURE_DATAINV(DATAINV) (((DATAINV) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \\\r\n                                             ((DATAINV) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))\r\n#define IS_SMARTCARD_ADVFEATURE_SWAP(SWAP) (((SWAP) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \\\r\n                                       ((SWAP) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))\r\n#define IS_SMARTCARD_OVERRUN(OVERRUN)         (((OVERRUN) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \\\r\n                                          ((OVERRUN) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))\r\n#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(DMA)      (((DMA) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \\\r\n                                                   ((DMA) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))\r\n#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001)\r\n#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFF)\r\n#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__)    ((__TIMEOUTVALUE__) <= 0xFFFFFF)\r\n#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__)         ((__COUNT__) <= 0x7)\r\n#define IS_SMARTCARD_ADVFEATURE_MSBFIRST(MSBFIRST) (((MSBFIRST) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \\\r\n                                               ((MSBFIRST) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))\r\n#define IS_SMARTCARD_REQUEST_PARAMETER(PARAM) (((PARAM) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \\\r\n                                               ((PARAM) == SMARTCARD_TXDATA_FLUSH_REQUEST))   \r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_SMARTCARD_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smartcard_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_smartcard_ex.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of SMARTCARD HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_SMARTCARD_EX_H\r\n#define __STM32F7xx_HAL_SMARTCARD_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup SMARTCARDEx\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n   \r\n/** @addtogroup SMARTCARDEx_Exported_Constants  SMARTCARD Extended Exported Constants\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup SMARTCARDEx_Transmission_Completion_Indication SMARTCARD Transmission Completion Indication\r\n  * @{\r\n  */\r\n#if defined(USART_TCBGT_SUPPORT)\r\n#define SMARTCARD_TCBGT      SMARTCARD_IT_TCBGT /*!< SMARTCARD transmission complete before guard time */\r\n#endif /* USART_TCBGT_SUPPORT */  \r\n#define SMARTCARD_TC         SMARTCARD_IT_TC    /*!< SMARTCARD transmission complete (flag raised when guard time has elapsed) */\r\n/**\r\n  * @}\r\n  */    \r\n  \r\n/** @defgroup SMARTCARDEx_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type\r\n  * @{\r\n  */\r\n#if defined(USART_TCBGT_SUPPORT)\r\n#define SMARTCARD_ADVFEATURE_TXCOMPLETION            ((uint32_t)0x00000100)    /*!< TX completion indication before of after guard time */\r\n#endif /* USART_TCBGT_SUPPORT */   \r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n  \r\n  \r\n/** @defgroup SMARTCARDEx_Flags SMARTCARD Flags\r\n  *        Elements values convention: 0xXXXX\r\n  *           - 0xXXXX  : Flag mask in the ISR register\r\n  * @{\r\n  */\r\n#if defined(USART_TCBGT_SUPPORT)\r\n#define SMARTCARD_FLAG_TCBGT          USART_ISR_TCBGT      /*!< SMARTCARD transmission complete before guard time completion */\r\n#endif /* USART_TCBGT_SUPPORT */\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup SMARTCARDEx_Interrupt_definition SMARTCARD Interrupts Definition\r\n  *        Elements values convention: 000ZZZZZ0XXYYYYYb\r\n  *           - YYYYY  : Interrupt source position in the XX register (5 bits)\r\n  *           - XX  : Interrupt source register (2 bits)\r\n  *                 - 01: CR1 register\r\n  *                 - 10: CR2 register\r\n  *                 - 11: CR3 register\r\n  *           - ZZZZZ  : Flag position in the ISR register(5 bits)\r\n  * @{\r\n  */\r\n\r\n#if defined(USART_TCBGT_SUPPORT)\r\n#define SMARTCARD_IT_TCBGT                  ((uint16_t)0x1978)        /*!< SMARTCARD transmission complete before guard time completion interruption */\r\n#endif /* USART_TCBGT_SUPPORT */ \r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup SMARTCARDEx_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags\r\n  * @{\r\n  */\r\n#define SMARTCARD_CLEAR_PEF                 USART_ICR_PECF    /*!< SMARTCARD parity error clear flag          */\r\n#define SMARTCARD_CLEAR_FEF                 USART_ICR_FECF    /*!< SMARTCARD framing error clear flag         */\r\n#define SMARTCARD_CLEAR_NEF                 USART_ICR_NCF     /*!< SMARTCARD noise detected clear flag        */\r\n#define SMARTCARD_CLEAR_OREF                USART_ICR_ORECF   /*!< SMARTCARD overrun error clear flag         */\r\n#define SMARTCARD_CLEAR_IDLEF               USART_ICR_IDLECF  /*!< SMARTCARD idle line detected clear flag    */\r\n#define SMARTCARD_CLEAR_TCF                 USART_ICR_TCCF    /*!< SMARTCARD transmission complete clear flag */\r\n#if defined(USART_TCBGT_SUPPORT)\r\n#define SMARTCARD_CLEAR_TCBGTF              USART_ICR_TCBGTCF /*!< SMARTCARD transmission complete before guard time completion clear flag */\r\n#endif /* USART_TCBGT_SUPPORT */ \r\n#define SMARTCARD_CLEAR_RTOF                USART_ICR_RTOCF   /*!< SMARTCARD receiver time out clear flag     */\r\n#define SMARTCARD_CLEAR_EOBF                USART_ICR_EOBCF   /*!< SMARTCARD end of block clear flag          */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n   \r\n/** @brief  Reports the SMARTCARD clock source.\r\n  * @param  __HANDLE__ specifies the USART Handle\r\n  * @param  __CLOCKSOURCE__  output variable   \r\n  * @retval the USART clocking source, written in __CLOCKSOURCE__.\r\n  */\r\n#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \\\r\n  do {                                                             \\\r\n    if((__HANDLE__)->Instance == USART1)                           \\\r\n    {                                                              \\\r\n       switch(__HAL_RCC_GET_USART1_SOURCE())                       \\\r\n       {                                                           \\\r\n        case RCC_USART1CLKSOURCE_PCLK2:                            \\\r\n          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2;         \\\r\n          break;                                                   \\\r\n        case RCC_USART1CLKSOURCE_HSI:                              \\\r\n          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;           \\\r\n          break;                                                   \\\r\n        case RCC_USART1CLKSOURCE_SYSCLK:                           \\\r\n          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                                   \\\r\n        case RCC_USART1CLKSOURCE_LSE:                              \\\r\n          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;           \\\r\n          break;                                                   \\\r\n        default:                                                   \\\r\n          break;                                                   \\\r\n       }                                                           \\\r\n    }                                                              \\\r\n    else if((__HANDLE__)->Instance == USART2)                      \\\r\n    {                                                              \\\r\n       switch(__HAL_RCC_GET_USART2_SOURCE())                       \\\r\n       {                                                           \\\r\n        case RCC_USART2CLKSOURCE_PCLK1:                            \\\r\n          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1;         \\\r\n          break;                                                   \\\r\n        case RCC_USART2CLKSOURCE_HSI:                              \\\r\n          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;           \\\r\n          break;                                                   \\\r\n        case RCC_USART2CLKSOURCE_SYSCLK:                           \\\r\n          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                                   \\\r\n        case RCC_USART2CLKSOURCE_LSE:                              \\\r\n          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;           \\\r\n          break;                                                   \\\r\n        default:                                                   \\\r\n          break;                                                   \\\r\n       }                                                           \\\r\n    }                                                              \\\r\n    else if((__HANDLE__)->Instance == USART3)                      \\\r\n    {                                                              \\\r\n       switch(__HAL_RCC_GET_USART3_SOURCE())                       \\\r\n       {                                                           \\\r\n        case RCC_USART3CLKSOURCE_PCLK1:                            \\\r\n          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1;         \\\r\n          break;                                                   \\\r\n        case RCC_USART3CLKSOURCE_HSI:                              \\\r\n          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;           \\\r\n          break;                                                   \\\r\n        case RCC_USART3CLKSOURCE_SYSCLK:                           \\\r\n          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                                   \\\r\n        case RCC_USART3CLKSOURCE_LSE:                              \\\r\n          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;           \\\r\n          break;                                                   \\\r\n        default:                                                   \\\r\n          break;                                                   \\\r\n       }                                                           \\\r\n    }                                                              \\\r\n    else if((__HANDLE__)->Instance == USART6)                      \\\r\n    {                                                              \\\r\n       switch(__HAL_RCC_GET_USART6_SOURCE())                       \\\r\n       {                                                           \\\r\n        case RCC_USART6CLKSOURCE_PCLK2:                            \\\r\n          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2;         \\\r\n          break;                                                   \\\r\n        case RCC_USART6CLKSOURCE_HSI:                              \\\r\n          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;           \\\r\n          break;                                                   \\\r\n        case RCC_USART6CLKSOURCE_SYSCLK:                           \\\r\n          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                                   \\\r\n        case RCC_USART6CLKSOURCE_LSE:                              \\\r\n          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;           \\\r\n          break;                                                   \\\r\n        default:                                                   \\\r\n          break;                                                   \\\r\n       }                                                           \\\r\n    }                                                              \\\r\n    } while(0)\r\n\r\n/** @brief  Set the Transmission Completion flag\r\n  * @param  __HANDLE__ specifies the SMARTCARD Handle.\r\n  * @note  If TCBGT (Transmission Complete Before Guard Time) flag is not available or if \r\n  *        AdvancedInit.TxCompletionIndication is not already filled, the latter is forced \r\n  *        to SMARTCARD_TC (transmission completion indication when guard time has elapsed).     \r\n  * @retval None\r\n  */\r\n#if defined(USART_TCBGT_SUPPORT)\r\n#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__)                                                \\\r\n  do {                                                                                                       \\\r\n    if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION))        \\\r\n    {                                                                                                        \\\r\n     (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC;                                       \\\r\n    }                                                                                                        \\\r\n    else                                                                                                     \\\r\n    {                                                                                                        \\\r\n      assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \\\r\n    }                                                                                                        \\\r\n  } while(0)\r\n#else\r\n#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__)         \\\r\n  do {                                                                \\\r\n    (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \\\r\n  } while(0)  \r\n#endif \r\n\r\n/** @brief  Return the transmission completion flag.\r\n  * @param  __HANDLE__ specifies the SMARTCARD Handle.\r\n  * @note  Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag.\r\n  *        When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is\r\n  *        reported.       \r\n  * @retval Transmission completion flag\r\n  */\r\n#if defined(USART_TCBGT_SUPPORT)\r\n#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) \\\r\n  (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) :  (SMARTCARD_FLAG_TCBGT))\r\n#else\r\n#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__)    (SMARTCARD_FLAG_TC)\r\n#endif\r\n  \r\n/**\r\n  * @brief Ensure that SMARTCARD frame transmission completion used flag is valid.\r\n  * @param __TXCOMPLETE__ SMARTCARD frame transmission completion used flag. \r\n  * @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid)\r\n  */ \r\n#if defined(USART_TCBGT_SUPPORT)\r\n#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) (((__TXCOMPLETE__) == SMARTCARD_TCBGT) ||\\\r\n                                                              ((__TXCOMPLETE__) == SMARTCARD_TC))\r\n#else\r\n#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) ((__TXCOMPLETE__) == SMARTCARD_TC)\r\n#endif\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/* Initialization and de-initialization functions  ****************************/\r\n/* IO operation functions *****************************************************/\r\n/* Peripheral Control functions ***********************************************/\r\nvoid HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsc, uint8_t BlockLength);\r\nvoid HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsc, uint32_t TimeOutValue);\r\nHAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsc);\r\nHAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsc);\r\n\r\n/* Peripheral State and Error functions ***************************************/\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_SMARTCARD_EX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spdifrx.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_spdifrx.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of SPDIFRX HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_SPDIFRX_H\r\n#define __STM32F7xx_HAL_SPDIFRX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\" \r\n\r\n#if defined (SPDIFRX) \r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup SPDIFRX\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/ \r\n/** @defgroup SPDIFRX_Exported_Types SPDIFRX Exported Types\r\n  * @{\r\n  */\r\n\r\n/** \r\n  * @brief SPDIFRX Init structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t InputSelection;           /*!< Specifies the SPDIF input selection.\r\n                                          This parameter can be a value of @ref SPDIFRX_Input_Selection */\r\n\r\n  uint32_t Retries;                  /*!< Specifies the Maximum allowed re-tries during synchronization phase.\r\n                                          This parameter can be a value of @ref SPDIFRX_Max_Retries */\r\n\r\n  uint32_t WaitForActivity;          /*!< Specifies the wait for activity on SPDIF selected input.\r\n                                          This parameter can be a value of @ref SPDIFRX_Wait_For_Activity. */\r\n\r\n  uint32_t ChannelSelection;         /*!< Specifies whether the control flow will take the channel status from channel A or B.\r\n                                          This parameter can be a value of @ref SPDIFRX_Channel_Selection */\r\n\r\n  uint32_t DataFormat;               /*!< Specifies the Data samples format (LSB, MSB, ...).\r\n                                          This parameter can be a value of @ref SPDIFRX_Data_Format */\r\n                                               \r\n  uint32_t StereoMode;               /*!< Specifies whether the peripheral is in stereo or mono mode.\r\n                                          This parameter can be a value of @ref SPDIFRX_Stereo_Mode */\r\n\r\n    uint32_t PreambleTypeMask;          /*!< Specifies whether The preamble type bits are copied or not into the received frame.\r\n                                                                                   This parameter can be a value of @ref SPDIFRX_PT_Mask */\r\n\r\n    uint32_t ChannelStatusMask;        /*!< Specifies whether the channel status and user bits are copied or not into the received frame.\r\n                                                                                  This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */\r\n    \r\n    uint32_t ValidityBitMask;          /*!< Specifies whether the validity bit is copied or not into the received frame.\r\n                                                                                  This parameter can be a value of @ref SPDIFRX_V_Mask */                                                                                \r\n                                                                                \r\n    uint32_t ParityErrorMask;          /*!< Specifies whether the parity error bit is copied or not into the received frame.\r\n                                                                                  This parameter can be a value of @ref SPDIFRX_PE_Mask */\r\n    \r\n}SPDIFRX_InitTypeDef;\r\n\r\n/** \r\n  * @brief SPDIFRX SetDataFormat structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t DataFormat;               /*!< Specifies the Data samples format (LSB, MSB, ...).\r\n                                          This parameter can be a value of @ref SPDIFRX_Data_Format */\r\n                                               \r\n  uint32_t StereoMode;               /*!< Specifies whether the peripheral is in stereo or mono mode.\r\n                                          This parameter can be a value of @ref SPDIFRX_Stereo_Mode */\r\n\r\n  uint32_t PreambleTypeMask;          /*!< Specifies whether The preamble type bits are copied or not into the received frame.\r\n                                                                                   This parameter can be a value of @ref SPDIFRX_PT_Mask */\r\n\r\n  uint32_t ChannelStatusMask;        /*!< Specifies whether the channel status and user bits are copied or not into the received frame.\r\n                                                                                  This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */\r\n    \r\n  uint32_t ValidityBitMask;          /*!< Specifies whether the validity bit is copied or not into the received frame.\r\n                                                                                  This parameter can be a value of @ref SPDIFRX_V_Mask */                                                                                \r\n                                                                                \r\n  uint32_t ParityErrorMask;          /*!< Specifies whether the parity error bit is copied or not into the received frame.\r\n                                                                                  This parameter can be a value of @ref SPDIFRX_PE_Mask */\r\n    \r\n}SPDIFRX_SetDataFormatTypeDef;\r\n\r\n/** \r\n  * @brief  HAL State structures definition  \r\n  */ \r\ntypedef enum\r\n{\r\n  HAL_SPDIFRX_STATE_RESET      = 0x00U,  /*!< SPDIFRX not yet initialized or disabled                */\r\n  HAL_SPDIFRX_STATE_READY      = 0x01U,  /*!< SPDIFRX initialized and ready for use                  */\r\n  HAL_SPDIFRX_STATE_BUSY       = 0x02U,  /*!< SPDIFRX internal process is ongoing                    */ \r\n  HAL_SPDIFRX_STATE_BUSY_RX    = 0x03U,  /*!< SPDIFRX internal Data Flow RX process is ongoing       */  \r\n  HAL_SPDIFRX_STATE_BUSY_CX    = 0x04U,  /*!< SPDIFRX internal Control Flow RX process is ongoing    */    \r\n  HAL_SPDIFRX_STATE_ERROR      = 0x07U   /*!< SPDIFRX error state                                    */      \r\n}HAL_SPDIFRX_StateTypeDef;\r\n\r\n/** \r\n  * @brief SPDIFRX handle Structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  SPDIFRX_TypeDef            *Instance;    /* SPDIFRX registers base address */\r\n\r\n  SPDIFRX_InitTypeDef        Init;         /* SPDIFRX communication parameters */\r\n                            \r\n  uint32_t                   *pRxBuffPtr;  /* Pointer to SPDIFRX Rx transfer buffer */\r\n    \r\n    uint32_t                   *pCsBuffPtr;  /* Pointer to SPDIFRX Cx transfer buffer */\r\n  \r\n  __IO uint16_t              RxXferSize;   /* SPDIFRX Rx transfer size */\r\n  \r\n  __IO uint16_t              RxXferCount;  /* SPDIFRX Rx transfer counter \r\n                                              (This field is initialized at the \r\n                                               same value as transfer size at the \r\n                                               beginning of the transfer and \r\n                                               decremented when a sample is received. \r\n                                               NbSamplesReceived = RxBufferSize-RxBufferCount) */\r\n    \r\n  __IO uint16_t              CsXferSize;   /* SPDIFRX Rx transfer size */\r\n  \r\n  __IO uint16_t              CsXferCount;  /* SPDIFRX Rx transfer counter \r\n                                              (This field is initialized at the \r\n                                               same value as transfer size at the \r\n                                               beginning of the transfer and \r\n                                               decremented when a sample is received. \r\n                                               NbSamplesReceived = RxBufferSize-RxBufferCount) */\r\n                                                                                             \r\n  DMA_HandleTypeDef          *hdmaCsRx;    /* SPDIFRX EC60958_channel_status and user_information DMA handle parameters */\r\n\r\n  DMA_HandleTypeDef          *hdmaDrRx;    /* SPDIFRX Rx DMA handle parameters */\r\n  \r\n  __IO HAL_LockTypeDef       Lock;         /* SPDIFRX locking object */\r\n  \r\n  __IO HAL_SPDIFRX_StateTypeDef  State;    /* SPDIFRX communication state */\r\n\r\n  __IO uint32_t  ErrorCode;                /* SPDIFRX Error code                 */\r\n\r\n}SPDIFRX_HandleTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup SPDIFRX_Exported_Constants SPDIFRX Exported Constants\r\n  * @{\r\n  */\r\n/** @defgroup SPDIFRX_ErrorCode SPDIFRX Error Code\r\n  * @{\r\n  */ \r\n#define HAL_SPDIFRX_ERROR_NONE      ((uint32_t)0x00000000U)  /*!< No error           */\r\n#define HAL_SPDIFRX_ERROR_TIMEOUT   ((uint32_t)0x00000001U)  /*!< Timeout error      */  \r\n#define HAL_SPDIFRX_ERROR_OVR       ((uint32_t)0x00000002U)  /*!< OVR error          */\r\n#define HAL_SPDIFRX_ERROR_PE        ((uint32_t)0x00000004U)  /*!< Parity error       */\r\n#define HAL_SPDIFRX_ERROR_DMA       ((uint32_t)0x00000008U)  /*!< DMA transfer error */\r\n#define HAL_SPDIFRX_ERROR_UNKNOWN   ((uint32_t)0x00000010U)  /*!< Unknown Error error */  \r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup SPDIFRX_Input_Selection SPDIFRX Input Selection\r\n  * @{\r\n  */\r\n#define SPDIFRX_INPUT_IN0               ((uint32_t)0x00000000U)\r\n#define SPDIFRX_INPUT_IN1               ((uint32_t)0x00010000U)  \r\n#define SPDIFRX_INPUT_IN2               ((uint32_t)0x00020000U)\r\n#define SPDIFRX_INPUT_IN3               ((uint32_t)0x00030000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPDIFRX_Max_Retries SPDIFRX Maximum Retries\r\n  * @{\r\n  */\r\n#define SPDIFRX_MAXRETRIES_NONE            ((uint32_t)0x00000000U)\r\n#define SPDIFRX_MAXRETRIES_3               ((uint32_t)0x00001000U)  \r\n#define SPDIFRX_MAXRETRIES_15              ((uint32_t)0x00002000U)\r\n#define SPDIFRX_MAXRETRIES_63              ((uint32_t)0x00003000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPDIFRX_Wait_For_Activity SPDIFRX Wait For Activity\r\n  * @{\r\n  */\r\n#define SPDIFRX_WAITFORACTIVITY_OFF                   ((uint32_t)0x00000000U)\r\n#define SPDIFRX_WAITFORACTIVITY_ON                    ((uint32_t)SPDIFRX_CR_WFA)\r\n/**\r\n  * @}\r\n  */\r\n    \r\n/** @defgroup SPDIFRX_PT_Mask SPDIFRX Preamble Type Mask\r\n* @{\r\n*/\r\n#define SPDIFRX_PREAMBLETYPEMASK_OFF                   ((uint32_t)0x00000000U)\r\n#define SPDIFRX_PREAMBLETYPEMASK_ON                    ((uint32_t)SPDIFRX_CR_PTMSK)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPDIFRX_ChannelStatus_Mask  SPDIFRX Channel Status Mask\r\n* @{\r\n*/\r\n#define SPDIFRX_CHANNELSTATUS_OFF                 ((uint32_t)0x00000000U)        /* The channel status and user bits are copied into the SPDIF_DR */\r\n#define SPDIFRX_CHANNELSTATUS_ON                  ((uint32_t)SPDIFRX_CR_CUMSK)  /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPDIFRX_V_Mask SPDIFRX Validity Mask\r\n* @{\r\n*/\r\n#define SPDIFRX_VALIDITYMASK_OFF                   ((uint32_t)0x00000000U)\r\n#define SPDIFRX_VALIDITYMASK_ON                    ((uint32_t)SPDIFRX_CR_VMSK)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPDIFRX_PE_Mask  SPDIFRX Parity Error Mask\r\n* @{\r\n*/\r\n#define SPDIFRX_PARITYERRORMASK_OFF                   ((uint32_t)0x00000000U)\r\n#define SPDIFRX_PARITYERRORMASK_ON                    ((uint32_t)SPDIFRX_CR_PMSK)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPDIFRX_Channel_Selection  SPDIFRX Channel Selection\r\n  * @{\r\n  */\r\n#define SPDIFRX_CHANNEL_A      ((uint32_t)0x00000000U)\r\n#define SPDIFRX_CHANNEL_B      ((uint32_t)SPDIFRX_CR_CHSEL)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPDIFRX_Data_Format SPDIFRX Data Format\r\n  * @{\r\n  */\r\n#define SPDIFRX_DATAFORMAT_LSB                   ((uint32_t)0x00000000U)\r\n#define SPDIFRX_DATAFORMAT_MSB                   ((uint32_t)0x00000010U)\r\n#define SPDIFRX_DATAFORMAT_32BITS                ((uint32_t)0x00000020U)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup SPDIFRX_Stereo_Mode SPDIFRX Stereo Mode\r\n  * @{\r\n  */\r\n#define SPDIFRX_STEREOMODE_DISABLE           ((uint32_t)0x00000000U)\r\n#define SPDIFRX_STEREOMODE_ENABLE           ((uint32_t)SPDIFRX_CR_RXSTEO)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup SPDIFRX_State SPDIFRX State\r\n  * @{\r\n  */\r\n\r\n#define SPDIFRX_STATE_IDLE    ((uint32_t)0xFFFFFFFCU)\r\n#define SPDIFRX_STATE_SYNC    ((uint32_t)0x00000001U)\r\n#define SPDIFRX_STATE_RCV     ((uint32_t)SPDIFRX_CR_SPDIFEN)\r\n/**\r\n  * @}\r\n  */\r\n    \r\n/** @defgroup SPDIFRX_Interrupts_Definition SPDIFRX Interrupts Definition\r\n  * @{\r\n  */\r\n#define SPDIFRX_IT_RXNE                       ((uint32_t)SPDIFRX_IMR_RXNEIE)\r\n#define SPDIFRX_IT_CSRNE                      ((uint32_t)SPDIFRX_IMR_CSRNEIE)\r\n#define SPDIFRX_IT_PERRIE                     ((uint32_t)SPDIFRX_IMR_PERRIE)\r\n#define SPDIFRX_IT_OVRIE                      ((uint32_t)SPDIFRX_IMR_OVRIE)\r\n#define SPDIFRX_IT_SBLKIE                     ((uint32_t)SPDIFRX_IMR_SBLKIE)\r\n#define SPDIFRX_IT_SYNCDIE                    ((uint32_t)SPDIFRX_IMR_SYNCDIE)\r\n#define SPDIFRX_IT_IFEIE                      ((uint32_t)SPDIFRX_IMR_IFEIE )\r\n/**\r\n  * @}\r\n  */\r\n    \r\n/** @defgroup SPDIFRX_Flags_Definition SPDIFRX Flags Definition\r\n  * @{\r\n  */\r\n#define SPDIFRX_FLAG_RXNE                   ((uint32_t)SPDIFRX_SR_RXNE)\r\n#define SPDIFRX_FLAG_CSRNE                  ((uint32_t)SPDIFRX_SR_CSRNE)\r\n#define SPDIFRX_FLAG_PERR                   ((uint32_t)SPDIFRX_SR_PERR)\r\n#define SPDIFRX_FLAG_OVR                    ((uint32_t)SPDIFRX_SR_OVR)\r\n#define SPDIFRX_FLAG_SBD                    ((uint32_t)SPDIFRX_SR_SBD)\r\n#define SPDIFRX_FLAG_SYNCD                  ((uint32_t)SPDIFRX_SR_SYNCD)\r\n#define SPDIFRX_FLAG_FERR                   ((uint32_t)SPDIFRX_SR_FERR)\r\n#define SPDIFRX_FLAG_SERR                   ((uint32_t)SPDIFRX_SR_SERR)\r\n#define SPDIFRX_FLAG_TERR                   ((uint32_t)SPDIFRX_SR_TERR)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/* Exported macros -----------------------------------------------------------*/\r\n/** @defgroup SPDIFRX_Exported_macros SPDIFRX Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief  Reset SPDIFRX handle state\r\n  * @param  __HANDLE__ SPDIFRX handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = (uint16_t)SPDIFRX_CR_SPDIFEN)\r\n\r\n/** @brief  Disable the specified SPDIFRX peripheral (IDLE State).\r\n  * @param  __HANDLE__ specifies the SPDIFRX Handle. \r\n  * @retval None\r\n  */\r\n#define __HAL_SPDIFRX_IDLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE)\r\n\r\n/** @brief  Enable the specified SPDIFRX peripheral (SYNC State).\r\n  * @param  __HANDLE__ specifies the SPDIFRX Handle. \r\n  * @retval None\r\n  */\r\n#define __HAL_SPDIFRX_SYNC(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC)\r\n\r\n\r\n/** @brief  Enable the specified SPDIFRX peripheral (RCV State).\r\n  * @param  __HANDLE__ specifies the SPDIFRX Handle. \r\n  * @retval None\r\n  */\r\n#define __HAL_SPDIFRX_RCV(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV)\r\n\r\n\r\n/** @brief  Enable or disable the specified SPDIFRX interrupts.\r\n  * @param  __HANDLE__ specifies the SPDIFRX Handle.\r\n  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.\r\n  *        This parameter can be one of the following values:\r\n  *            @arg SPDIFRX_IT_RXNE\r\n  *            @arg SPDIFRX_IT_CSRNE\r\n  *            @arg SPDIFRX_IT_PERRIE\r\n  *            @arg SPDIFRX_IT_OVRIE\r\n  *            @arg SPDIFRX_IT_SBLKIE\r\n  *            @arg SPDIFRX_IT_SYNCDIE\r\n  *            @arg SPDIFRX_IT_IFEIE\r\n  * @retval None\r\n  */  \r\n#define __HAL_SPDIFRX_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))\r\n#define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__)))\r\n \r\n/** @brief  Checks if the specified SPDIFRX interrupt source is enabled or disabled.\r\n  * @param  __HANDLE__ specifies the SPDIFRX Handle.\r\n  * @param  __INTERRUPT__ specifies the SPDIFRX interrupt source to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg SPDIFRX_IT_RXNE\r\n  *            @arg SPDIFRX_IT_CSRNE\r\n  *            @arg SPDIFRX_IT_PERRIE\r\n  *            @arg SPDIFRX_IT_OVRIE\r\n  *            @arg SPDIFRX_IT_SBLKIE\r\n  *            @arg SPDIFRX_IT_SYNCDIE\r\n  *            @arg SPDIFRX_IT_IFEIE\r\n  * @retval The new state of __IT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r\n\r\n/** @brief  Checks whether the specified SPDIFRX flag is set or not.\r\n  * @param  __HANDLE__ specifies the SPDIFRX Handle.\r\n  * @param  __FLAG__ specifies the flag to check.\r\n  *        This parameter can be one of the following values:\r\n  *            @arg SPDIFRX_FLAG_RXNE\r\n  *            @arg SPDIFRX_FLAG_CSRNE\r\n  *            @arg SPDIFRX_FLAG_PERR\r\n  *            @arg SPDIFRX_FLAG_OVR\r\n  *            @arg SPDIFRX_FLAG_SBD\r\n  *            @arg SPDIFRX_FLAG_SYNCD \r\n  *            @arg SPDIFRX_FLAG_FERR \r\n  *            @arg SPDIFRX_FLAG_SERR \r\n  *            @arg SPDIFRX_FLAG_TERR \r\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))\r\n\r\n/** @brief  Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit.\r\n  * @param  __HANDLE__ specifies the USART Handle.\r\n  * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set\r\n  *                       to clear the corresponding interrupt\r\n  *          This parameter can be one of the following values:\r\n  *            @arg SPDIFRX_FLAG_PERR\r\n  *            @arg SPDIFRX_FLAG_OVR\r\n  *            @arg SPDIFRX_SR_SBD\r\n  *            @arg SPDIFRX_SR_SYNCD\r\n  * @retval None\r\n  */\r\n#define __HAL_SPDIFRX_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->IFCR = (uint32_t)(__IT_CLEAR__)) \r\n  \r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup SPDIFRX_Exported_Functions\r\n  * @{\r\n  */\r\n                                                \r\n/** @addtogroup SPDIFRX_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n/* Initialization/de-initialization functions  **********************************/\r\nHAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif);\r\nHAL_StatusTypeDef HAL_SPDIFRX_DeInit (SPDIFRX_HandleTypeDef *hspdif);\r\nvoid HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif);\r\nvoid HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif);\r\nHAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef  sDataFormat);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup SPDIFRX_Exported_Functions_Group2\r\n  * @{\r\n  */\r\n/* I/O operation functions  ***************************************************/\r\n /* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);\r\n\r\n /* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);\r\nvoid HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif);\r\n\r\n/* Non-Blocking mode: DMA */\r\nHAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);\r\n\r\nHAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif);\r\n\r\n/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/\r\nvoid HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif);\r\nvoid HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);\r\nvoid HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif);\r\nvoid HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif);\r\nvoid HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup SPDIFRX_Exported_Functions_Group3\r\n  * @{\r\n  */\r\n/* Peripheral Control and State functions  ************************************/\r\nHAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif);\r\nuint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup SPDIFRX_Private_Macros SPDIFRX Private Macros\r\n  * @{\r\n  */\r\n#define IS_SPDIFRX_INPUT_SELECT(INPUT)  (((INPUT) == SPDIFRX_INPUT_IN1) || \\\r\n                                         ((INPUT) == SPDIFRX_INPUT_IN2) || \\\r\n                                         ((INPUT) == SPDIFRX_INPUT_IN3)  || \\\r\n                                         ((INPUT) == SPDIFRX_INPUT_IN0))\r\n#define IS_SPDIFRX_MAX_RETRIES(RET)   (((RET) == SPDIFRX_MAXRETRIES_NONE) || \\\r\n                                      ((RET) == SPDIFRX_MAXRETRIES_3)  || \\\r\n                                      ((RET) == SPDIFRX_MAXRETRIES_15) || \\\r\n                                      ((RET) == SPDIFRX_MAXRETRIES_63))\r\n#define IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL)    (((VAL) == SPDIFRX_WAITFORACTIVITY_ON) || \\\r\n                                               ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF))\r\n#define IS_PREAMBLE_TYPE_MASK(VAL)           (((VAL) == SPDIFRX_PREAMBLETYPEMASK_ON) || \\\r\n                                             ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF))\r\n#define IS_VALIDITY_MASK(VAL)               (((VAL) == SPDIFRX_VALIDITYMASK_OFF) || \\\r\n                                             ((VAL) == SPDIFRX_VALIDITYMASK_ON))\r\n#define IS_PARITY_ERROR_MASK(VAL)            (((VAL) == SPDIFRX_PARITYERRORMASK_OFF) || \\\r\n                                             ((VAL) == SPDIFRX_PARITYERRORMASK_ON))\r\n#define IS_SPDIFRX_CHANNEL(CHANNEL)   (((CHANNEL) == SPDIFRX_CHANNEL_A) || \\\r\n                                       ((CHANNEL) == SPDIFRX_CHANNEL_B))\r\n#define IS_SPDIFRX_DATA_FORMAT(FORMAT)           (((FORMAT) == SPDIFRX_DATAFORMAT_LSB) || \\\r\n                                                 ((FORMAT) == SPDIFRX_DATAFORMAT_MSB) || \\\r\n                                                 ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS))\r\n#define IS_STEREO_MODE(MODE)                 (((MODE) == SPDIFRX_STEREOMODE_DISABLE) || \\\r\n                                             ((MODE) == SPDIFRX_STEREOMODE_ENABLE))\r\n                                             \r\n#define IS_CHANNEL_STATUS_MASK(VAL)          (((VAL) == SPDIFRX_CHANNELSTATUS_ON) || \\\r\n                                              ((VAL) == SPDIFRX_CHANNELSTATUS_OFF))\r\n/**                                                                                    \r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup SPDIFRX_Private_Functions SPDIFRX Private Functions\r\n  * @{\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n \r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* SPDIFRX */\r\n    \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n\r\n#endif /* __STM32F7xx_HAL_SPDIFRX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_spi.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of SPI HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_SPI_H\r\n#define __STM32F7xx_HAL_SPI_H\r\n\r\n#ifdef __cplusplus\r\nextern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup SPI\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup SPI_Exported_Types SPI Exported Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  SPI Configuration Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n    uint32_t Mode;                /*!< Specifies the SPI operating mode.\r\n                                     This parameter can be a value of @ref SPI_Mode */\r\n\r\n    uint32_t Direction;           /*!< Specifies the SPI bidirectional mode state.\r\n                                     This parameter can be a value of @ref SPI_Direction */\r\n\r\n    uint32_t DataSize;            /*!< Specifies the SPI data size.\r\n                                     This parameter can be a value of @ref SPI_Data_Size */\r\n\r\n    uint32_t CLKPolarity;         /*!< Specifies the serial clock steady state.\r\n                                     This parameter can be a value of @ref SPI_Clock_Polarity */\r\n\r\n    uint32_t CLKPhase;            /*!< Specifies the clock active edge for the bit capture.\r\n                                     This parameter can be a value of @ref SPI_Clock_Phase */\r\n\r\n    uint32_t NSS;                 /*!< Specifies whether the NSS signal is managed by\r\n                                     hardware (NSS pin) or by software using the SSI bit.\r\n                                     This parameter can be a value of @ref SPI_Slave_Select_management */\r\n\r\n    uint32_t BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be\r\n                                     used to configure the transmit and receive SCK clock.\r\n                                     This parameter can be a value of @ref SPI_BaudRate_Prescaler\r\n                                     @note The communication clock is derived from the master\r\n                                     clock. The slave clock does not need to be set. */\r\n\r\n    uint32_t FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.\r\n                                     This parameter can be a value of @ref SPI_MSB_LSB_transmission */\r\n\r\n    uint32_t TIMode;              /*!< Specifies if the TI mode is enabled or not.\r\n                                     This parameter can be a value of @ref SPI_TI_mode */\r\n\r\n    uint32_t CRCCalculation;      /*!< Specifies if the CRC calculation is enabled or not.\r\n                                     This parameter can be a value of @ref SPI_CRC_Calculation */\r\n\r\n    uint32_t CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation.\r\n                                     This parameter must be an odd number between Min_Data = 0 and Max_Data = 65535 */\r\n\r\n    uint32_t CRCLength;           /*!< Specifies the CRC Length used for the CRC calculation.\r\n                                     CRC Length is only used with Data8 and Data16, not other data size\r\n                                     This parameter can be a value of @ref SPI_CRC_length */\r\n\r\n    uint32_t NSSPMode;            /*!< Specifies whether the NSSP signal is enabled or not .\r\n                                     This parameter can be a value of @ref SPI_NSSP_Mode\r\n                                     This mode is activated by the NSSP bit in the SPIx_CR2 register and\r\n                                     it takes effect only if the SPI interface is configured as Motorola SPI\r\n                                     master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,\r\n                                     CPOL setting is ignored).. */\r\n} SPI_InitTypeDef;\r\n\r\n/**\r\n  * @brief  HAL SPI State structure definition\r\n  */\r\ntypedef enum\r\n{\r\n    HAL_SPI_STATE_RESET      = 0x00U,    /*!< Peripheral not Initialized                         */\r\n    HAL_SPI_STATE_READY      = 0x01U,    /*!< Peripheral Initialized and ready for use           */\r\n    HAL_SPI_STATE_BUSY       = 0x02U,    /*!< an internal process is ongoing                     */\r\n    HAL_SPI_STATE_BUSY_TX    = 0x03U,    /*!< Data Transmission process is ongoing               */\r\n    HAL_SPI_STATE_BUSY_RX    = 0x04U,    /*!< Data Reception process is ongoing                  */\r\n    HAL_SPI_STATE_BUSY_TX_RX = 0x05U,    /*!< Data Transmission and Reception process is ongoing */\r\n    HAL_SPI_STATE_ERROR      = 0x06U,    /*!< SPI error state                                    */\r\n    HAL_SPI_STATE_ABORT      = 0x07U     /*!< SPI abort is ongoing                               */\r\n} HAL_SPI_StateTypeDef;\r\n\r\n/**\r\n  * @brief  SPI handle Structure definition\r\n  */\r\ntypedef struct __SPI_HandleTypeDef\r\n{\r\n    SPI_TypeDef                *Instance;      /*!< SPI registers base address               */\r\n\r\n    SPI_InitTypeDef            Init;           /*!< SPI communication parameters             */\r\n\r\n    uint8_t                    *pTxBuffPtr;    /*!< Pointer to SPI Tx transfer Buffer        */\r\n\r\n    uint16_t                   TxXferSize;     /*!< SPI Tx Transfer size                     */\r\n\r\n    __IO uint16_t              TxXferCount;    /*!< SPI Tx Transfer Counter                  */\r\n\r\n    uint8_t                    *pRxBuffPtr;    /*!< Pointer to SPI Rx transfer Buffer        */\r\n\r\n    uint16_t                   RxXferSize;     /*!< SPI Rx Transfer size                     */\r\n\r\n    __IO uint16_t              RxXferCount;    /*!< SPI Rx Transfer Counter                  */\r\n\r\n    uint32_t                   CRCSize;        /*!< SPI CRC size used for the transfer       */\r\n\r\n    void (*RxISR)(struct __SPI_HandleTypeDef *hspi);                       /*!< function pointer on Rx ISR */\r\n\r\n    void (*TxISR)(struct __SPI_HandleTypeDef *hspi);                       /*!< function pointer on Tx ISR */\r\n\r\n    DMA_HandleTypeDef          *hdmatx;        /*!< SPI Tx DMA Handle parameters             */\r\n\r\n    DMA_HandleTypeDef          *hdmarx;        /*!< SPI Rx DMA Handle parameters             */\r\n\r\n    HAL_LockTypeDef            Lock;           /*!< Locking object                           */\r\n\r\n    __IO HAL_SPI_StateTypeDef  State;          /*!< SPI communication state                  */\r\n\r\n    __IO uint32_t              ErrorCode;      /*!< SPI Error code                           */\r\n\r\n} SPI_HandleTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup SPI_Exported_Constants SPI Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup SPI_Error_Code SPI Error Code\r\n  * @{\r\n  */\r\n#define HAL_SPI_ERROR_NONE              ((uint32_t)0x00000000U)   /*!< No error                               */\r\n#define HAL_SPI_ERROR_MODF              ((uint32_t)0x00000001U)   /*!< MODF error                             */\r\n#define HAL_SPI_ERROR_CRC               ((uint32_t)0x00000002U)   /*!< CRC error                              */\r\n#define HAL_SPI_ERROR_OVR               ((uint32_t)0x00000004U)   /*!< OVR error                              */\r\n#define HAL_SPI_ERROR_FRE               ((uint32_t)0x00000008U)   /*!< FRE error                              */\r\n#define HAL_SPI_ERROR_DMA               ((uint32_t)0x00000010U)   /*!< DMA transfer error                     */\r\n#define HAL_SPI_ERROR_FLAG              ((uint32_t)0x00000020U)   /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */\r\n#define HAL_SPI_ERROR_ABORT             ((uint32_t)0x00000040U)   /*!< Error during SPI Abort procedure       */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_Mode SPI Mode\r\n  * @{\r\n  */\r\n#define SPI_MODE_SLAVE                  ((uint32_t)0x00000000U)\r\n#define SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_Direction SPI Direction Mode\r\n  * @{\r\n  */\r\n#define SPI_DIRECTION_2LINES            ((uint32_t)0x00000000U)\r\n#define SPI_DIRECTION_2LINES_RXONLY     SPI_CR1_RXONLY\r\n#define SPI_DIRECTION_1LINE             SPI_CR1_BIDIMODE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_Data_Size SPI Data Size\r\n  * @{\r\n  */\r\n#define SPI_DATASIZE_4BIT               ((uint32_t)0x00000300U)\r\n#define SPI_DATASIZE_5BIT               ((uint32_t)0x00000400U)\r\n#define SPI_DATASIZE_6BIT               ((uint32_t)0x00000500U)\r\n#define SPI_DATASIZE_7BIT               ((uint32_t)0x00000600U)\r\n#define SPI_DATASIZE_8BIT               ((uint32_t)0x00000700U)\r\n#define SPI_DATASIZE_9BIT               ((uint32_t)0x00000800U)\r\n#define SPI_DATASIZE_10BIT              ((uint32_t)0x00000900U)\r\n#define SPI_DATASIZE_11BIT              ((uint32_t)0x00000A00U)\r\n#define SPI_DATASIZE_12BIT              ((uint32_t)0x00000B00U)\r\n#define SPI_DATASIZE_13BIT              ((uint32_t)0x00000C00U)\r\n#define SPI_DATASIZE_14BIT              ((uint32_t)0x00000D00U)\r\n#define SPI_DATASIZE_15BIT              ((uint32_t)0x00000E00U)\r\n#define SPI_DATASIZE_16BIT              ((uint32_t)0x00000F00U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_Clock_Polarity SPI Clock Polarity\r\n  * @{\r\n  */\r\n#define SPI_POLARITY_LOW                ((uint32_t)0x00000000U)\r\n#define SPI_POLARITY_HIGH               SPI_CR1_CPOL\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_Clock_Phase SPI Clock Phase\r\n  * @{\r\n  */\r\n#define SPI_PHASE_1EDGE                 ((uint32_t)0x00000000U)\r\n#define SPI_PHASE_2EDGE                 SPI_CR1_CPHA\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_Slave_Select_management SPI Slave Select Management\r\n  * @{\r\n  */\r\n#define SPI_NSS_SOFT                    SPI_CR1_SSM\r\n#define SPI_NSS_HARD_INPUT              ((uint32_t)0x00000000U)\r\n#define SPI_NSS_HARD_OUTPUT             ((uint32_t)0x00040000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode\r\n  * @{\r\n  */\r\n#define SPI_NSS_PULSE_ENABLE            SPI_CR2_NSSP\r\n#define SPI_NSS_PULSE_DISABLE           ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler\r\n  * @{\r\n  */\r\n#define SPI_BAUDRATEPRESCALER_2         ((uint32_t)0x00000000U)\r\n#define SPI_BAUDRATEPRESCALER_4         ((uint32_t)0x00000008U)\r\n#define SPI_BAUDRATEPRESCALER_8         ((uint32_t)0x00000010U)\r\n#define SPI_BAUDRATEPRESCALER_16        ((uint32_t)0x00000018U)\r\n#define SPI_BAUDRATEPRESCALER_32        ((uint32_t)0x00000020U)\r\n#define SPI_BAUDRATEPRESCALER_64        ((uint32_t)0x00000028U)\r\n#define SPI_BAUDRATEPRESCALER_128       ((uint32_t)0x00000030U)\r\n#define SPI_BAUDRATEPRESCALER_256       ((uint32_t)0x00000038U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission\r\n  * @{\r\n  */\r\n#define SPI_FIRSTBIT_MSB                ((uint32_t)0x00000000U)\r\n#define SPI_FIRSTBIT_LSB                SPI_CR1_LSBFIRST\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_TI_mode SPI TI Mode\r\n  * @{\r\n  */\r\n#define SPI_TIMODE_DISABLE              ((uint32_t)0x00000000U)\r\n#define SPI_TIMODE_ENABLE               SPI_CR2_FRF\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_CRC_Calculation SPI CRC Calculation\r\n  * @{\r\n  */\r\n#define SPI_CRCCALCULATION_DISABLE      ((uint32_t)0x00000000U)\r\n#define SPI_CRCCALCULATION_ENABLE       SPI_CR1_CRCEN\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_CRC_length SPI CRC Length\r\n  * @{\r\n  * This parameter can be one of the following values:\r\n  *     SPI_CRC_LENGTH_DATASIZE: aligned with the data size\r\n  *     SPI_CRC_LENGTH_8BIT    : CRC 8bit\r\n  *     SPI_CRC_LENGTH_16BIT   : CRC 16bit\r\n  */\r\n#define SPI_CRC_LENGTH_DATASIZE         ((uint32_t)0x00000000U)\r\n#define SPI_CRC_LENGTH_8BIT             ((uint32_t)0x00000001U)\r\n#define SPI_CRC_LENGTH_16BIT            ((uint32_t)0x00000002U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold\r\n  * @{\r\n  * This parameter can be one of the following values:\r\n  *     SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :\r\n  *          RXNE event is generated if the FIFO\r\n  *          level is greater or equal to 1/2(16-bits).\r\n  *     SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO\r\n  *          level is greater or equal to 1/4(8 bits). */\r\n#define SPI_RXFIFO_THRESHOLD            SPI_CR2_FRXTH\r\n#define SPI_RXFIFO_THRESHOLD_QF         SPI_CR2_FRXTH\r\n#define SPI_RXFIFO_THRESHOLD_HF         ((uint32_t)0x00000000U)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition\r\n  * @{\r\n  */\r\n#define SPI_IT_TXE                      SPI_CR2_TXEIE\r\n#define SPI_IT_RXNE                     SPI_CR2_RXNEIE\r\n#define SPI_IT_ERR                      SPI_CR2_ERRIE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_Flags_definition SPI Flags Definition\r\n  * @{\r\n  */\r\n#define SPI_FLAG_RXNE                   SPI_SR_RXNE   /* SPI status flag: Rx buffer not empty flag       */\r\n#define SPI_FLAG_TXE                    SPI_SR_TXE    /* SPI status flag: Tx buffer empty flag           */\r\n#define SPI_FLAG_BSY                    SPI_SR_BSY    /* SPI status flag: Busy flag                      */\r\n#define SPI_FLAG_CRCERR                 SPI_SR_CRCERR /* SPI Error flag: CRC error flag                  */\r\n#define SPI_FLAG_MODF                   SPI_SR_MODF   /* SPI Error flag: Mode fault flag                 */\r\n#define SPI_FLAG_OVR                    SPI_SR_OVR    /* SPI Error flag: Overrun flag                    */\r\n#define SPI_FLAG_FRE                    SPI_SR_FRE    /* SPI Error flag: TI mode frame format error flag */\r\n#define SPI_FLAG_FTLVL                  SPI_SR_FTLVL  /* SPI fifo transmission level                     */\r\n#define SPI_FLAG_FRLVL                  SPI_SR_FRLVL  /* SPI fifo reception level                        */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level\r\n  * @{\r\n  */\r\n#define SPI_FTLVL_EMPTY           ((uint32_t)0x00000000U)\r\n#define SPI_FTLVL_QUARTER_FULL    ((uint32_t)0x00000800U)\r\n#define SPI_FTLVL_HALF_FULL       ((uint32_t)0x00001000U)\r\n#define SPI_FTLVL_FULL            ((uint32_t)0x00001800U)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level\r\n  * @{\r\n  */\r\n#define SPI_FRLVL_EMPTY           ((uint32_t)0x00000000U)\r\n#define SPI_FRLVL_QUARTER_FULL    ((uint32_t)0x00000200U)\r\n#define SPI_FRLVL_HALF_FULL       ((uint32_t)0x00000400U)\r\n#define SPI_FRLVL_FULL            ((uint32_t)0x00000600U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macros -----------------------------------------------------------*/\r\n/** @defgroup SPI_Exported_Macros SPI Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief  Reset SPI handle state.\r\n  * @param  __HANDLE__ specifies the SPI Handle.\r\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r\n  * @retval None\r\n  */\r\n#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)\r\n\r\n/** @brief  Enable or disable the specified SPI interrupts.\r\n  * @param  __HANDLE__ specifies the SPI Handle.\r\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r\n  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable\r\n  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable\r\n  *            @arg SPI_IT_ERR: Error interrupt enable\r\n  * @retval None\r\n  */\r\n#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))\r\n#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))\r\n\r\n/** @brief  Check whether the specified SPI interrupt source is enabled or not.\r\n  * @param  __HANDLE__ specifies the SPI Handle.\r\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r\n  * @param  __INTERRUPT__ specifies the SPI interrupt source to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable\r\n  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable\r\n  *            @arg SPI_IT_ERR: Error interrupt enable\r\n  * @retval The new state of __IT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r\n\r\n/** @brief  Check whether the specified SPI flag is set or not.\r\n  * @param  __HANDLE__ specifies the SPI Handle.\r\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r\n  * @param  __FLAG__ specifies the flag to check.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag\r\n  *            @arg SPI_FLAG_TXE: Transmit buffer empty flag\r\n  *            @arg SPI_FLAG_CRCERR: CRC error flag\r\n  *            @arg SPI_FLAG_MODF: Mode fault flag\r\n  *            @arg SPI_FLAG_OVR: Overrun flag\r\n  *            @arg SPI_FLAG_BSY: Busy flag\r\n  *            @arg SPI_FLAG_FRE: Frame format error flag\r\n  *            @arg SPI_FLAG_FTLVL: SPI fifo transmission level\r\n  *            @arg SPI_FLAG_FRLVL: SPI fifo reception level\r\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))\r\n\r\n/** @brief  Clear the SPI CRCERR pending flag.\r\n  * @param  __HANDLE__ specifies the SPI Handle.\r\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r\n  * @retval None\r\n  */\r\n#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))\r\n\r\n/** @brief  Clear the SPI MODF pending flag.\r\n  * @param  __HANDLE__ specifies the SPI Handle.\r\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r\n  * @retval None\r\n  */\r\n#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)       \\\r\n  do{                                              \\\r\n    __IO uint32_t tmpreg_modf = 0x00U;             \\\r\n    tmpreg_modf = (__HANDLE__)->Instance->SR;      \\\r\n    (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \\\r\n    UNUSED(tmpreg_modf);                           \\\r\n  } while(0)\r\n\r\n/** @brief  Clear the SPI OVR pending flag.\r\n  * @param  __HANDLE__ specifies the SPI Handle.\r\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r\n  * @retval None\r\n  */\r\n#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)        \\\r\n  do{                                              \\\r\n    __IO uint32_t tmpreg_ovr = 0x00U;              \\\r\n    tmpreg_ovr = (__HANDLE__)->Instance->DR;       \\\r\n    tmpreg_ovr = (__HANDLE__)->Instance->SR;       \\\r\n    UNUSED(tmpreg_ovr);                            \\\r\n  } while(0)\r\n\r\n/** @brief  Clear the SPI FRE pending flag.\r\n  * @param  __HANDLE__ specifies the SPI Handle.\r\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r\n  * @retval None\r\n  */\r\n#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)        \\\r\n  do{                                              \\\r\n  __IO uint32_t tmpreg_fre = 0x00U;                \\\r\n  tmpreg_fre = (__HANDLE__)->Instance->SR;         \\\r\n  UNUSED(tmpreg_fre);                              \\\r\n  }while(0)\r\n\r\n/** @brief  Enable the SPI peripheral.\r\n  * @param  __HANDLE__ specifies the SPI Handle.\r\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r\n  * @retval None\r\n  */\r\n#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |=  SPI_CR1_SPE)\r\n\r\n/** @brief  Disable the SPI peripheral.\r\n  * @param  __HANDLE__ specifies the SPI Handle.\r\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r\n  * @retval None\r\n  */\r\n#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup SPI_Private_Macros SPI Private Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief  Set the SPI transmit-only mode.\r\n  * @param  __HANDLE__ specifies the SPI Handle.\r\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r\n  * @retval None\r\n  */\r\n#define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)\r\n\r\n/** @brief  Set the SPI receive-only mode.\r\n  * @param  __HANDLE__ specifies the SPI Handle.\r\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r\n  * @retval None\r\n  */\r\n#define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))\r\n\r\n/** @brief  Reset the CRC calculation of the SPI.\r\n  * @param  __HANDLE__ specifies the SPI Handle.\r\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r\n  * @retval None\r\n  */\r\n#define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\\\r\n                                     (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)\r\n\r\n#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \\\r\n                           ((MODE) == SPI_MODE_MASTER))\r\n\r\n#define IS_SPI_DIRECTION(MODE)   (((MODE) == SPI_DIRECTION_2LINES)        || \\\r\n                                  ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \\\r\n                                  ((MODE) == SPI_DIRECTION_1LINE))\r\n\r\n#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)\r\n\r\n#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \\\r\n                                                ((MODE) == SPI_DIRECTION_1LINE))\r\n\r\n#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \\\r\n                                   ((DATASIZE) == SPI_DATASIZE_15BIT) || \\\r\n                                   ((DATASIZE) == SPI_DATASIZE_14BIT) || \\\r\n                                   ((DATASIZE) == SPI_DATASIZE_13BIT) || \\\r\n                                   ((DATASIZE) == SPI_DATASIZE_12BIT) || \\\r\n                                   ((DATASIZE) == SPI_DATASIZE_11BIT) || \\\r\n                                   ((DATASIZE) == SPI_DATASIZE_10BIT) || \\\r\n                                   ((DATASIZE) == SPI_DATASIZE_9BIT)  || \\\r\n                                   ((DATASIZE) == SPI_DATASIZE_8BIT)  || \\\r\n                                   ((DATASIZE) == SPI_DATASIZE_7BIT)  || \\\r\n                                   ((DATASIZE) == SPI_DATASIZE_6BIT)  || \\\r\n                                   ((DATASIZE) == SPI_DATASIZE_5BIT)  || \\\r\n                                   ((DATASIZE) == SPI_DATASIZE_4BIT))\r\n\r\n#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \\\r\n                           ((CPOL) == SPI_POLARITY_HIGH))\r\n\r\n#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \\\r\n                           ((CPHA) == SPI_PHASE_2EDGE))\r\n\r\n#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT)       || \\\r\n                         ((NSS) == SPI_NSS_HARD_INPUT) || \\\r\n                         ((NSS) == SPI_NSS_HARD_OUTPUT))\r\n\r\n#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \\\r\n                           ((NSSP) == SPI_NSS_PULSE_DISABLE))\r\n\r\n#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2)   || \\\r\n                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_4)   || \\\r\n                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_8)   || \\\r\n                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_16)  || \\\r\n                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_32)  || \\\r\n                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_64)  || \\\r\n                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \\\r\n                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))\r\n\r\n#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \\\r\n                               ((BIT) == SPI_FIRSTBIT_LSB))\r\n\r\n#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \\\r\n                             ((MODE) == SPI_TIMODE_ENABLE))\r\n\r\n#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \\\r\n                                             ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))\r\n\r\n#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\\\r\n                                   ((LENGTH) == SPI_CRC_LENGTH_8BIT)  ||   \\\r\n                                   ((LENGTH) == SPI_CRC_LENGTH_16BIT))\r\n\r\n#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0))\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup SPI_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions\r\n  * @{\r\n  */\r\n/* Initialization/de-initialization functions  ********************************/\r\nHAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);\r\nHAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);\r\nvoid HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);\r\nvoid HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup SPI_Exported_Functions_Group2 IO operation functions\r\n  * @{\r\n  */\r\n/* I/O operation functions  ***************************************************/\r\nHAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,\r\n        uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,\r\n        uint16_t Size);\r\nHAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,\r\n        uint16_t Size);\r\nHAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);\r\nHAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);\r\nHAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);\r\n/* Transfer Abort functions */\r\nHAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);\r\nHAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);\r\n\r\nvoid HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);\r\nvoid HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);\r\nvoid HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);\r\nvoid HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);\r\nvoid HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);\r\nvoid HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);\r\nvoid HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);\r\nvoid HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);\r\nvoid HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions\r\n  * @{\r\n  */\r\n\r\n/* Peripheral State and Error functions ***************************************/\r\nHAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);\r\nuint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_SPI_H */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sram.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_sram.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of SRAM HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_SRAM_H\r\n#define __STM32F7xx_HAL_SRAM_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_ll_fmc.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n/** @addtogroup SRAM\r\n  * @{\r\n  */ \r\n\r\n/* Exported typedef ----------------------------------------------------------*/\r\n\r\n/** @defgroup SRAM_Exported_Types SRAM Exported Types\r\n  * @{\r\n  */\r\n/** \r\n  * @brief  HAL SRAM State structures definition  \r\n  */ \r\ntypedef enum\r\n{\r\n  HAL_SRAM_STATE_RESET     = 0x00U,  /*!< SRAM not yet initialized or disabled           */\r\n  HAL_SRAM_STATE_READY     = 0x01U,  /*!< SRAM initialized and ready for use             */\r\n  HAL_SRAM_STATE_BUSY      = 0x02U,  /*!< SRAM internal process is ongoing               */\r\n  HAL_SRAM_STATE_ERROR     = 0x03U,  /*!< SRAM error state                               */\r\n  HAL_SRAM_STATE_PROTECTED = 0x04U   /*!< SRAM peripheral NORSRAM device write protected */\r\n  \r\n}HAL_SRAM_StateTypeDef;\r\n\r\n/** \r\n  * @brief  SRAM handle Structure definition  \r\n  */ \r\ntypedef struct\r\n{\r\n  FMC_NORSRAM_TypeDef           *Instance;  /*!< Register base address                        */ \r\n  \r\n  FMC_NORSRAM_EXTENDED_TypeDef  *Extended;  /*!< Extended mode register base address          */\r\n  \r\n  FMC_NORSRAM_InitTypeDef       Init;       /*!< SRAM device control configuration parameters */\r\n\r\n  HAL_LockTypeDef               Lock;       /*!< SRAM locking object                          */ \r\n  \r\n  __IO HAL_SRAM_StateTypeDef    State;      /*!< SRAM device access state                     */\r\n  \r\n  DMA_HandleTypeDef             *hdma;      /*!< Pointer DMA handler                          */\r\n  \r\n}SRAM_HandleTypeDef; \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/* Exported macro ------------------------------------------------------------*/\r\n\r\n/** @defgroup SRAM_Exported_Macros SRAM Exported Macros\r\n * @{\r\n */\r\n\r\n/** @brief Reset SRAM handle state\r\n  * @param  __HANDLE__ SRAM handle\r\n  * @retval None\r\n  */\r\n#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions\r\n * @{\r\n */\r\n\r\n/* Initialization/de-initialization functions  ********************************/\r\nHAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);\r\nHAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);\r\nvoid HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);\r\nvoid HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions\r\n * @{\r\n */\r\n\r\n/* I/O operation functions  ***************************************************/\r\nHAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);\r\nHAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);\r\nHAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);\r\nHAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);\r\nHAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);\r\nHAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);\r\nHAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);\r\nHAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);\r\n\r\nvoid HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);\r\nvoid HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @addtogroup SRAM_Exported_Functions_Group3 Control functions\r\n * @{\r\n */\r\n\r\n/* SRAM Control functions  ****************************************************/\r\nHAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);\r\nHAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions\r\n * @{\r\n */\r\n\r\n/* SRAM  State functions ******************************************************/\r\nHAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_SRAM_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_tim.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of TIM HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_TIM_H\r\n#define __STM32F7xx_HAL_TIM_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup TIM\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup TIM_Exported_Types TIM Exported Types\r\n  * @{\r\n  */\r\n  \r\n/** \r\n  * @brief  TIM Time base Configuration Structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.\r\n                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r\n\r\n  uint32_t CounterMode;       /*!< Specifies the counter mode.\r\n                                   This parameter can be a value of @ref TIM_Counter_Mode */\r\n\r\n  uint32_t Period;            /*!< Specifies the period value to be loaded into the active\r\n                                   Auto-Reload Register at the next update event.\r\n                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */\r\n\r\n  uint32_t ClockDivision;     /*!< Specifies the clock division.\r\n                                   This parameter can be a value of @ref TIM_ClockDivision */\r\n\r\n  uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR down-counter\r\n                                    reaches zero, an update event is generated and counting restarts\r\n                                    from the RCR value (N).\r\n                                    This means in PWM mode that (N+1) corresponds to:\r\n                                        - the number of PWM periods in edge-aligned mode\r\n                                        - the number of half PWM period in center-aligned mode\r\n                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. \r\n                                     @note This parameter is valid only for TIM1 and TIM8. */\r\n\r\n  uint32_t AutoReloadPreload;  /*!< Specifies the auto-reload preload.\r\n                                   This parameter can be a value of @ref TIM_AutoReloadPreload */\r\n\r\n} TIM_Base_InitTypeDef;\r\n\r\n/** \r\n  * @brief  TIM Output Compare Configuration Structure definition  \r\n  */\r\n\r\ntypedef struct\r\n{\r\n  uint32_t OCMode;        /*!< Specifies the TIM mode.\r\n                               This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */\r\n\r\n  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register. \r\n                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r\n\r\n  uint32_t OCPolarity;    /*!< Specifies the output polarity.\r\n                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */\r\n\r\n  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.\r\n                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity\r\n                               @note This parameter is valid only for TIM1 and TIM8. */\r\n  \r\n  uint32_t OCFastMode;   /*!< Specifies the Fast mode state.\r\n                               This parameter can be a value of @ref TIM_Output_Fast_State\r\n                               @note This parameter is valid only in PWM1 and PWM2 mode. */\r\n\r\n\r\n  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.\r\n                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State\r\n                               @note This parameter is valid only for TIM1 and TIM8. */\r\n\r\n  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.\r\n                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State\r\n                               @note This parameter is valid only for TIM1 and TIM8. */\r\n} TIM_OC_InitTypeDef;  \r\n\r\n/** \r\n  * @brief  TIM One Pulse Mode Configuration Structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t OCMode;        /*!< Specifies the TIM mode.\r\n                               This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */\r\n\r\n  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register. \r\n                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r\n\r\n  uint32_t OCPolarity;    /*!< Specifies the output polarity.\r\n                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */\r\n\r\n  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.\r\n                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity\r\n                               @note This parameter is valid only for TIM1 and TIM8. */\r\n\r\n  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.\r\n                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State\r\n                               @note This parameter is valid only for TIM1 and TIM8. */\r\n\r\n  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.\r\n                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State\r\n                               @note This parameter is valid only for TIM1 and TIM8. */\r\n\r\n  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.\r\n                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r\n\r\n  uint32_t ICSelection;   /*!< Specifies the input.\r\n                              This parameter can be a value of @ref TIM_Input_Capture_Selection */\r\n\r\n  uint32_t ICFilter;      /*!< Specifies the input capture filter.\r\n                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */  \r\n} TIM_OnePulse_InitTypeDef;  \r\n\r\n\r\n/** \r\n  * @brief  TIM Input Capture Configuration Structure definition  \r\n  */\r\n\r\ntypedef struct\r\n{\r\n  uint32_t  ICPolarity;   /*!< Specifies the active edge of the input signal.\r\n                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r\n\r\n  uint32_t ICSelection;  /*!< Specifies the input.\r\n                              This parameter can be a value of @ref TIM_Input_Capture_Selection */\r\n\r\n  uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.\r\n                              This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r\n\r\n  uint32_t ICFilter;     /*!< Specifies the input capture filter.\r\n                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r\n} TIM_IC_InitTypeDef;\r\n\r\n/** \r\n  * @brief  TIM Encoder Configuration Structure definition  \r\n  */\r\n\r\ntypedef struct\r\n{\r\n  uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.\r\n                               This parameter can be a value of @ref TIM_Encoder_Mode */\r\n                                  \r\n  uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.\r\n                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r\n\r\n  uint32_t IC1Selection;  /*!< Specifies the input.\r\n                               This parameter can be a value of @ref TIM_Input_Capture_Selection */\r\n\r\n  uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.\r\n                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r\n\r\n  uint32_t IC1Filter;     /*!< Specifies the input capture filter.\r\n                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r\n                                  \r\n  uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.\r\n                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r\n\r\n  uint32_t IC2Selection;  /*!< Specifies the input.\r\n                              This parameter can be a value of @ref TIM_Input_Capture_Selection */\r\n\r\n  uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.\r\n                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r\n\r\n  uint32_t IC2Filter;     /*!< Specifies the input capture filter.\r\n                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r\n} TIM_Encoder_InitTypeDef;\r\n\r\n/** \r\n  * @brief  Clock Configuration Handle Structure definition  \r\n  */ \r\ntypedef struct\r\n{\r\n  uint32_t ClockSource;     /*!< TIM clock sources. \r\n                                 This parameter can be a value of @ref TIM_Clock_Source */ \r\n  uint32_t ClockPolarity;   /*!< TIM clock polarity. \r\n                                 This parameter can be a value of @ref TIM_Clock_Polarity */\r\n  uint32_t ClockPrescaler;  /*!< TIM clock prescaler. \r\n                                 This parameter can be a value of @ref TIM_Clock_Prescaler */\r\n  uint32_t ClockFilter;    /*!< TIM clock filter. \r\n                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r\n}TIM_ClockConfigTypeDef;\r\n\r\n/** \r\n  * @brief  Clear Input Configuration Handle Structure definition  \r\n  */ \r\ntypedef struct\r\n{ \r\n  uint32_t ClearInputState;      /*!< TIM clear Input state. \r\n                                      This parameter can be ENABLE or DISABLE */  \r\n  uint32_t ClearInputSource;     /*!< TIM clear Input sources. \r\n                                      This parameter can be a value of @ref TIMEx_ClearInput_Source */ \r\n  uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity. \r\n                                      This parameter can be a value of @ref TIM_ClearInput_Polarity */\r\n  uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler. \r\n                                      This parameter can be a value of @ref TIM_ClearInput_Prescaler */\r\n  uint32_t ClearInputFilter;    /*!< TIM Clear Input filter. \r\n                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r\n}TIM_ClearInputConfigTypeDef;\r\n\r\n/** \r\n  * @brief  TIM Slave configuration Structure definition  \r\n  */ \r\ntypedef struct {\r\n  uint32_t  SlaveMode;         /*!< Slave mode selection \r\n                                  This parameter can be a value of @ref TIMEx_Slave_Mode */ \r\n  uint32_t  InputTrigger;      /*!< Input Trigger source \r\n                                  This parameter can be a value of @ref TIM_Trigger_Selection */\r\n  uint32_t  TriggerPolarity;   /*!< Input Trigger polarity \r\n                                  This parameter can be a value of @ref TIM_Trigger_Polarity */\r\n  uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler \r\n                                  This parameter can be a value of @ref TIM_Trigger_Prescaler */\r\n  uint32_t  TriggerFilter;     /*!< Input trigger filter \r\n                                  This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */  \r\n\r\n}TIM_SlaveConfigTypeDef;\r\n\r\n/** \r\n  * @brief  HAL State structures definition  \r\n  */ \r\ntypedef enum\r\n{\r\n  HAL_TIM_STATE_RESET             = 0x00U,    /*!< Peripheral not yet initialized or disabled  */\r\n  HAL_TIM_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */\r\n  HAL_TIM_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */\r\n  HAL_TIM_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */\r\n  HAL_TIM_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                */\r\n}HAL_TIM_StateTypeDef;\r\n\r\n/** \r\n  * @brief  HAL Active channel structures definition  \r\n  */ \r\ntypedef enum\r\n{\r\n  HAL_TIM_ACTIVE_CHANNEL_1        = 0x01U,    /*!< The active channel is 1     */\r\n  HAL_TIM_ACTIVE_CHANNEL_2        = 0x02U,    /*!< The active channel is 2     */\r\n  HAL_TIM_ACTIVE_CHANNEL_3        = 0x04U,    /*!< The active channel is 3     */\r\n  HAL_TIM_ACTIVE_CHANNEL_4        = 0x08U,    /*!< The active channel is 4     */\r\n  HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00U     /*!< All active channels cleared */\r\n}HAL_TIM_ActiveChannel;\r\n\r\n/** \r\n  * @brief  TIM Time Base Handle Structure definition  \r\n  */ \r\ntypedef struct __TIM_HandleTypeDef\r\n{\r\n  TIM_TypeDef                 *Instance;     /*!< Register base address             */\r\n  TIM_Base_InitTypeDef        Init;          /*!< TIM Time Base required parameters */\r\n  HAL_TIM_ActiveChannel       Channel;       /*!< Active channel                    */\r\n  DMA_HandleTypeDef           *hdma[7];      /*!< DMA Handlers array\r\n                                             This array is accessed by a @ref DMA_Handle_index */\r\n  HAL_LockTypeDef             Lock;          /*!< Locking object                    */\r\n  __IO HAL_TIM_StateTypeDef   State;         /*!< TIM operation state               */\r\n\r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\n  void  (* Base_MspInitCallback)         (struct __TIM_HandleTypeDef *htim);  /*!< TIM Base Msp Init Callback          */\r\n  void  (* Base_MspDeInitCallback)       (struct __TIM_HandleTypeDef *htim);  /*!< TIM Base Msp DeInit Callback        */\r\n  void  (* IC_MspInitCallback)           (struct __TIM_HandleTypeDef *htim);  /*!< TIM IC Msp Init Callback            */\r\n  void  (* IC_MspDeInitCallback)         (struct __TIM_HandleTypeDef *htim);  /*!< TIM IC Msp DeInit Callback          */\r\n  void  (* OC_MspInitCallback)           (struct __TIM_HandleTypeDef *htim);  /*!< TIM OC Msp Init Callback            */\r\n  void  (* OC_MspDeInitCallback)         (struct __TIM_HandleTypeDef *htim);  /*!< TIM OC Msp DeInit Callback          */\r\n  void  (* PWM_MspInitCallback)          (struct __TIM_HandleTypeDef *htim);  /*!< TIM PWM Msp Init Callback           */\r\n  void  (* PWM_MspDeInitCallback)        (struct __TIM_HandleTypeDef *htim);  /*!< TIM PWM Msp DeInit Callback         */\r\n  void  (* OnePulse_MspInitCallback)     (struct __TIM_HandleTypeDef *htim);  /*!< TIM One Pulse Msp Init Callback     */\r\n  void  (* OnePulse_MspDeInitCallback)   (struct __TIM_HandleTypeDef *htim);  /*!< TIM One Pulse Msp DeInit Callback   */\r\n  void  (* Encoder_MspInitCallback)      (struct __TIM_HandleTypeDef *htim);  /*!< TIM Encoder Msp Init Callback       */\r\n  void  (* Encoder_MspDeInitCallback)    (struct __TIM_HandleTypeDef *htim);  /*!< TIM Encoder Msp DeInit Callback     */\r\n  void  (* HallSensor_MspInitCallback)   (struct __TIM_HandleTypeDef *htim);  /*!< TIM Hall Sensor Msp Init Callback   */\r\n  void  (* HallSensor_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim);  /*!< TIM Hall Sensor Msp DeInit Callback */\r\n\r\n  void  (* PeriodElapsedCallback)        (struct __TIM_HandleTypeDef *htim);  /*!< TIM Period Elapsed Callback               */\r\n  void  (* TriggerCallback)              (struct __TIM_HandleTypeDef *htim);  /*!< TIM Trigger Callback                      */\r\n  void  (* IC_CaptureCallback)           (struct __TIM_HandleTypeDef *htim);  /*!< TIM Input Capture Callback                */\r\n  void  (* OC_DelayElapsedCallback)      (struct __TIM_HandleTypeDef *htim);  /*!< TIM Output Compare Delay Elapsed Callback */\r\n  void  (* PWM_PulseFinishedCallback)    (struct __TIM_HandleTypeDef *htim);  /*!< TIM PWM Pulse Finished Callback           */\r\n  void  (* ErrorCallback)                (struct __TIM_HandleTypeDef *htim);  /*!< TIM Error Callback                        */\r\n  void  (* CommutationCallback)          (struct __TIM_HandleTypeDef *htim);  /*!< TIM Commutation Callback                  */\r\n  void  (* BreakCallback)                (struct __TIM_HandleTypeDef *htim);  /*!< TIM Break Callback                        */\r\n\r\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n\r\n}TIM_HandleTypeDef;\r\n\r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\n/**\r\n  * @brief  HAL TIM Callback ID enumeration definition\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_TIM_BASE_MSPINIT_CB_ID          = 0x00U,    /*!< TIM Base MspInit Callback ID        */\r\n  HAL_TIM_BASE_MSPDEINIT_CB_ID        = 0x01U,    /*!< TIM Base MspDeInit Callback ID      */\r\n  HAL_TIM_IC_MSPINIT_CB_ID            = 0x02U,    /*!< TIM IC MspInit Callback ID          */\r\n  HAL_TIM_IC_MSPDEINIT_CB_ID          = 0x03U,    /*!< TIM IC MspDeInit Callback ID        */\r\n  HAL_TIM_OC_MSPINIT_CB_ID            = 0x04U,    /*!< TIM OC MspInit Callback ID          */\r\n  HAL_TIM_OC_MSPDEINIT_CB_ID          = 0x05U,    /*!< TIM OC MspDeInit Callback ID        */\r\n  HAL_TIM_PWM_MSPINIT_CB_ID           = 0x06U,    /*!< TIM PWM MspInit Callback ID         */\r\n  HAL_TIM_PWM_MSPDEINIT_CB_ID         = 0x07U,    /*!< TIM PWM MspDeInit Callback ID       */\r\n  HAL_TIM_ONE_PULSE_MSPINIT_CB_ID     = 0x08U,    /*!< TIM One Pulse MspInit Callback ID   */\r\n  HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID   = 0x09U,    /*!< TIM One Pulse MspDeInit Callback ID */\r\n  HAL_TIM_ENCODER_MSPINIT_CB_ID       = 0x0AU,    /*!< TIM Encoder MspInit Callback ID     */\r\n  HAL_TIM_ENCODER_MSPDEINIT_CB_ID     = 0x0BU,    /*!< TIM Encoder MspDeInit Callback ID   */\r\n  HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID   = 0x0CU,    /*!< TIM Encoder MspDeInit Callback ID   */\r\n  HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU,    /*!< TIM Encoder MspDeInit Callback ID   */\r\n\r\n  HAL_TIM_PERIOD_ELAPSED_CB_ID        = 0x0EU,    /*!< TIM Period Elapsed Callback ID               */\r\n  HAL_TIM_TRIGGER_CB_ID               = 0x0FU,    /*!< TIM Trigger Callback ID                      */\r\n  HAL_TIM_IC_CAPTURE_CB_ID            = 0x10U,    /*!< TIM Input Capture Callback ID                */\r\n  HAL_TIM_OC_DELAY_ELAPSED_CB_ID      = 0x11U,    /*!< TIM Output Compare Delay Elapsed Callback ID */\r\n  HAL_TIM_PWM_PULSE_FINISHED_CB_ID    = 0x12U,    /*!< TIM PWM Pulse Finished Callback ID           */\r\n  HAL_TIM_ERROR_CB_ID                 = 0x13U,    /*!< TIM Error Callback ID                        */\r\n  HAL_TIM_COMMUTATION_CB_ID           = 0x14U,    /*!< TIM Commutation Callback ID                  */\r\n  HAL_TIM_BREAK_CB_ID                 = 0x15U     /*!< TIM Break Callback ID                        */\r\n\r\n}HAL_TIM_CallbackIDTypeDef;\r\n\r\n/**\r\n  * @brief  HAL TIM Callback pointer definition\r\n  */\r\ntypedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to the TIM callback function */\r\n\r\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup TIM_Exported_Constants  TIM Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity\r\n  * @{\r\n  */\r\n#define  TIM_INPUTCHANNELPOLARITY_RISING      ((uint32_t)0x00000000U)            /*!< Polarity for TIx source */\r\n#define  TIM_INPUTCHANNELPOLARITY_FALLING     (TIM_CCER_CC1P)                   /*!< Polarity for TIx source */\r\n#define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_ETR_Polarity  TIM ETR Polarity\r\n  * @{\r\n  */\r\n#define TIM_ETRPOLARITY_INVERTED              (TIM_SMCR_ETP)                    /*!< Polarity for ETR source */\r\n#define TIM_ETRPOLARITY_NONINVERTED           ((uint32_t)0x0000U)                /*!< Polarity for ETR source */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_ETR_Prescaler  TIM ETR Prescaler\r\n  * @{\r\n  */\r\n#define TIM_ETRPRESCALER_DIV1                 ((uint32_t)0x0000U)                /*!< No prescaler is used */\r\n#define TIM_ETRPRESCALER_DIV2                 (TIM_SMCR_ETPS_0)                 /*!< ETR input source is divided by 2 */\r\n#define TIM_ETRPRESCALER_DIV4                 (TIM_SMCR_ETPS_1)                 /*!< ETR input source is divided by 4 */\r\n#define TIM_ETRPRESCALER_DIV8                 (TIM_SMCR_ETPS)                   /*!< ETR input source is divided by 8 */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Counter_Mode  TIM Counter Mode\r\n  * @{\r\n  */\r\n#define TIM_COUNTERMODE_UP                 ((uint32_t)0x0000U)\r\n#define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR\r\n#define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0\r\n#define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1\r\n#define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_ClockDivision TIM Clock Division\r\n  * @{\r\n  */\r\n#define TIM_CLOCKDIVISION_DIV1                       ((uint32_t)0x0000U)\r\n#define TIM_CLOCKDIVISION_DIV2                       (TIM_CR1_CKD_0)\r\n#define TIM_CLOCKDIVISION_DIV4                       (TIM_CR1_CKD_1)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Output_Compare_State TIM Output Compare State\r\n  * @{\r\n  */\r\n#define TIM_OUTPUTSTATE_DISABLE            ((uint32_t)0x0000U)\r\n#define TIM_OUTPUTSTATE_ENABLE             (TIM_CCER_CC1E)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload\r\n  * @{\r\n  */\r\n#define TIM_AUTORELOAD_PRELOAD_DISABLE                ((uint32_t)0x0000)   /*!< TIMx_ARR register is not buffered */\r\n#define TIM_AUTORELOAD_PRELOAD_ENABLE                 (TIM_CR1_ARPE)       /*!< TIMx_ARR register is buffered */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Output_Fast_State  TIM Output Fast State \r\n  * @{\r\n  */\r\n#define TIM_OCFAST_DISABLE                ((uint32_t)0x0000U)\r\n#define TIM_OCFAST_ENABLE                 (TIM_CCMR1_OC1FE)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State\r\n  * @{\r\n  */\r\n#define TIM_OUTPUTNSTATE_DISABLE            ((uint32_t)0x0000U)\r\n#define TIM_OUTPUTNSTATE_ENABLE             (TIM_CCER_CC1NE)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity \r\n  * @{\r\n  */\r\n#define TIM_OCPOLARITY_HIGH                ((uint32_t)0x0000U)\r\n#define TIM_OCPOLARITY_LOW                 (TIM_CCER_CC1P)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity\r\n  * @{\r\n  */\r\n#define TIM_OCNPOLARITY_HIGH               ((uint32_t)0x0000U)\r\n#define TIM_OCNPOLARITY_LOW                (TIM_CCER_CC1NP)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Output_Compare_Idle_State  TIM Output Compare Idle State\r\n  * @{\r\n  */\r\n#define TIM_OCIDLESTATE_SET                (TIM_CR2_OIS1)\r\n#define TIM_OCIDLESTATE_RESET              ((uint32_t)0x0000U)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup TIM_Output_Compare_N_Idle_State  TIM Output Compare N Idle State\r\n  * @{\r\n  */\r\n#define TIM_OCNIDLESTATE_SET               (TIM_CR2_OIS1N)\r\n#define TIM_OCNIDLESTATE_RESET             ((uint32_t)0x0000U)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup TIM_Input_Capture_Polarity  TIM Input Capture Polarity \r\n  * @{\r\n  */\r\n#define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING\r\n#define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING\r\n#define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Input_Capture_Selection  TIM Input Capture Selection\r\n  * @{\r\n  */\r\n#define TIM_ICSELECTION_DIRECTTI           (TIM_CCMR1_CC1S_0)   /*!< TIM Input 1, 2, 3 or 4 is selected to be \r\n                                                                     connected to IC1, IC2, IC3 or IC4, respectively */\r\n#define TIM_ICSELECTION_INDIRECTTI         (TIM_CCMR1_CC1S_1)   /*!< TIM Input 1, 2, 3 or 4 is selected to be\r\n                                                                     connected to IC2, IC1, IC4 or IC3, respectively */\r\n#define TIM_ICSELECTION_TRC                (TIM_CCMR1_CC1S)     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Input_Capture_Prescaler  TIM Input Capture Prescaler\r\n  * @{\r\n  */\r\n#define TIM_ICPSC_DIV1                     ((uint32_t)0x0000U)       /*!< Capture performed each time an edge is detected on the capture input */\r\n#define TIM_ICPSC_DIV2                     (TIM_CCMR1_IC1PSC_0)     /*!< Capture performed once every 2 events */\r\n#define TIM_ICPSC_DIV4                     (TIM_CCMR1_IC1PSC_1)     /*!< Capture performed once every 4 events */\r\n#define TIM_ICPSC_DIV8                     (TIM_CCMR1_IC1PSC)       /*!< Capture performed once every 8 events */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode\r\n  * @{\r\n  */\r\n#define TIM_OPMODE_SINGLE                  (TIM_CR1_OPM)\r\n#define TIM_OPMODE_REPETITIVE              ((uint32_t)0x0000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Encoder_Mode TIM Encoder Mode\r\n  * @{\r\n  */\r\n#define TIM_ENCODERMODE_TI1                (TIM_SMCR_SMS_0)\r\n#define TIM_ENCODERMODE_TI2                (TIM_SMCR_SMS_1)\r\n#define TIM_ENCODERMODE_TI12               (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Interrupt_definition  TIM Interrupt definition\r\n  * @{\r\n  */ \r\n#define TIM_IT_UPDATE           (TIM_DIER_UIE)\r\n#define TIM_IT_CC1              (TIM_DIER_CC1IE)\r\n#define TIM_IT_CC2              (TIM_DIER_CC2IE)\r\n#define TIM_IT_CC3              (TIM_DIER_CC3IE)\r\n#define TIM_IT_CC4              (TIM_DIER_CC4IE)\r\n#define TIM_IT_COM              (TIM_DIER_COMIE)\r\n#define TIM_IT_TRIGGER          (TIM_DIER_TIE)\r\n#define TIM_IT_BREAK            (TIM_DIER_BIE)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup TIM_Commutation_Source  TIM Commutation Source \r\n  * @{\r\n  */  \r\n#define TIM_COMMUTATION_TRGI              (TIM_CR2_CCUS)\r\n#define TIM_COMMUTATION_SOFTWARE          ((uint32_t)0x0000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_DMA_sources  TIM DMA sources\r\n  * @{\r\n  */\r\n#define TIM_DMA_UPDATE                     (TIM_DIER_UDE)\r\n#define TIM_DMA_CC1                        (TIM_DIER_CC1DE)\r\n#define TIM_DMA_CC2                        (TIM_DIER_CC2DE)\r\n#define TIM_DMA_CC3                        (TIM_DIER_CC3DE)\r\n#define TIM_DMA_CC4                        (TIM_DIER_CC4DE)\r\n#define TIM_DMA_COM                        (TIM_DIER_COMDE)\r\n#define TIM_DMA_TRIGGER                    (TIM_DIER_TDE)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Event_Source  TIM Event Source \r\n  * @{\r\n  */\r\n#define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG  \r\n#define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G\r\n#define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G\r\n#define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G\r\n#define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G\r\n#define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG\r\n#define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG  \r\n#define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG \r\n#define TIM_EVENTSOURCE_BREAK2              TIM_EGR_B2G   \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Flag_definition  TIM Flag definition\r\n  * @{\r\n  */\r\n#define TIM_FLAG_UPDATE                    (TIM_SR_UIF)\r\n#define TIM_FLAG_CC1                       (TIM_SR_CC1IF)\r\n#define TIM_FLAG_CC2                       (TIM_SR_CC2IF)\r\n#define TIM_FLAG_CC3                       (TIM_SR_CC3IF)\r\n#define TIM_FLAG_CC4                       (TIM_SR_CC4IF)\r\n#define TIM_FLAG_COM                       (TIM_SR_COMIF)\r\n#define TIM_FLAG_TRIGGER                   (TIM_SR_TIF)\r\n#define TIM_FLAG_BREAK                     (TIM_SR_BIF)\r\n#define TIM_FLAG_BREAK2                    (TIM_SR_B2IF)\r\n#define TIM_FLAG_CC1OF                     (TIM_SR_CC1OF)\r\n#define TIM_FLAG_CC2OF                     (TIM_SR_CC2OF)\r\n#define TIM_FLAG_CC3OF                     (TIM_SR_CC3OF)\r\n#define TIM_FLAG_CC4OF                     (TIM_SR_CC4OF)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Clock_Source  TIM Clock Source\r\n  * @{\r\n  */\r\n#define\tTIM_CLOCKSOURCE_ETRMODE2    (TIM_SMCR_ETPS_1) \r\n#define\tTIM_CLOCKSOURCE_INTERNAL    (TIM_SMCR_ETPS_0) \r\n#define\tTIM_CLOCKSOURCE_ITR0        ((uint32_t)0x0000U)\r\n#define\tTIM_CLOCKSOURCE_ITR1        (TIM_SMCR_TS_0)\r\n#define\tTIM_CLOCKSOURCE_ITR2        (TIM_SMCR_TS_1)\r\n#define\tTIM_CLOCKSOURCE_ITR3        (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)\r\n#define\tTIM_CLOCKSOURCE_TI1ED       (TIM_SMCR_TS_2)\r\n#define\tTIM_CLOCKSOURCE_TI1         (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)\r\n#define\tTIM_CLOCKSOURCE_TI2         (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)\r\n#define\tTIM_CLOCKSOURCE_ETRMODE1    (TIM_SMCR_TS)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Clock_Polarity  TIM Clock Polarity\r\n  * @{\r\n  */\r\n#define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED          /*!< Polarity for ETRx clock sources */ \r\n#define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED       /*!< Polarity for ETRx clock sources */ \r\n#define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING   /*!< Polarity for TIx clock sources */ \r\n#define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */ \r\n#define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */ \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Clock_Prescaler  TIM Clock Prescaler\r\n  * @{\r\n  */\r\n#define TIM_CLOCKPRESCALER_DIV1              TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */\r\n#define TIM_CLOCKPRESCALER_DIV2              TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */\r\n#define TIM_CLOCKPRESCALER_DIV4              TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */\r\n#define TIM_CLOCKPRESCALER_DIV8              TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_ClearInput_Polarity  TIM Clear Input Polarity\r\n  * @{\r\n  */\r\n#define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED                    /*!< Polarity for ETRx pin */ \r\n#define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED                 /*!< Polarity for ETRx pin */ \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler\r\n  * @{\r\n  */\r\n#define TIM_CLEARINPUTPRESCALER_DIV1                    TIM_ETRPRESCALER_DIV1      /*!< No prescaler is used */\r\n#define TIM_CLEARINPUTPRESCALER_DIV2                    TIM_ETRPRESCALER_DIV2      /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */\r\n#define TIM_CLEARINPUTPRESCALER_DIV4                    TIM_ETRPRESCALER_DIV4      /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */\r\n#define TIM_CLEARINPUTPRESCALER_DIV8                    TIM_ETRPRESCALER_DIV8        /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state\r\n  * @{\r\n  */  \r\n#define TIM_OSSR_ENABLE \t      (TIM_BDTR_OSSR)\r\n#define TIM_OSSR_DISABLE          ((uint32_t)0x0000U)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state\r\n  * @{\r\n  */\r\n#define TIM_OSSI_ENABLE\t \t    (TIM_BDTR_OSSI)\r\n#define TIM_OSSI_DISABLE            ((uint32_t)0x0000U)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup TIM_Lock_level  TIM Lock level\r\n  * @{\r\n  */\r\n#define TIM_LOCKLEVEL_OFF\t   ((uint32_t)0x0000U)\r\n#define TIM_LOCKLEVEL_1            (TIM_BDTR_LOCK_0)\r\n#define TIM_LOCKLEVEL_2            (TIM_BDTR_LOCK_1)\r\n#define TIM_LOCKLEVEL_3            (TIM_BDTR_LOCK)\r\n/**\r\n  * @}\r\n  */  \r\n/** @defgroup TIM_Break_Input_enable_disable  TIM Break Input State\r\n  * @{\r\n  */                         \r\n#define TIM_BREAK_ENABLE          (TIM_BDTR_BKE)\r\n#define TIM_BREAK_DISABLE         ((uint32_t)0x0000U)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup TIM_Break_Polarity  TIM Break Polarity \r\n  * @{\r\n  */\r\n#define TIM_BREAKPOLARITY_LOW        ((uint32_t)0x0000U)\r\n#define TIM_BREAKPOLARITY_HIGH       (TIM_BDTR_BKP)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup TIM_AOE_Bit_Set_Reset  TIM AOE Bit State\r\n  * @{\r\n  */\r\n#define TIM_AUTOMATICOUTPUT_ENABLE           (TIM_BDTR_AOE)\r\n#define\tTIM_AUTOMATICOUTPUT_DISABLE          ((uint32_t)0x0000U)\r\n/**\r\n  * @}\r\n  */  \r\n  \r\n/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection\r\n  * @{\r\n  */  \r\n#define\tTIM_TRGO_RESET            ((uint32_t)0x0000U)             \r\n#define\tTIM_TRGO_ENABLE           (TIM_CR2_MMS_0)           \r\n#define\tTIM_TRGO_UPDATE           (TIM_CR2_MMS_1)             \r\n#define\tTIM_TRGO_OC1              ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))    \r\n#define\tTIM_TRGO_OC1REF           (TIM_CR2_MMS_2)           \r\n#define\tTIM_TRGO_OC2REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))          \r\n#define\tTIM_TRGO_OC3REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))           \r\n#define\tTIM_TRGO_OC4REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))   \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup TIM_Master_Slave_Mode  TIM Master Slave Mode\r\n  * @{\r\n  */\r\n#define TIM_MASTERSLAVEMODE_ENABLE          ((uint32_t)0x0080)\r\n#define TIM_MASTERSLAVEMODE_DISABLE         ((uint32_t)0x0000U)\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/** @defgroup TIM_Trigger_Selection  TIM Trigger Selection\r\n  * @{\r\n  */\r\n#define TIM_TS_ITR0                        ((uint32_t)0x0000U)\r\n#define TIM_TS_ITR1                        ((uint32_t)0x0010U)\r\n#define TIM_TS_ITR2                        ((uint32_t)0x0020U)\r\n#define TIM_TS_ITR3                        ((uint32_t)0x0030U)\r\n#define TIM_TS_TI1F_ED                     ((uint32_t)0x0040U)\r\n#define TIM_TS_TI1FP1                      ((uint32_t)0x0050U)\r\n#define TIM_TS_TI2FP2                      ((uint32_t)0x0060U)\r\n#define TIM_TS_ETRF                        ((uint32_t)0x0070U)\r\n#define TIM_TS_NONE                        ((uint32_t)0xFFFFU)\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity\r\n  * @{\r\n  */\r\n#define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx trigger sources */ \r\n#define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx trigger sources */ \r\n#define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */ \r\n#define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */ \r\n#define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */ \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler\r\n  * @{\r\n  */\r\n#define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */\r\n#define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */\r\n#define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */\r\n#define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup TIM_TI1_Selection TIM TI1 Selection\r\n  * @{\r\n  */\r\n#define TIM_TI1SELECTION_CH1                ((uint32_t)0x0000U)\r\n#define TIM_TI1SELECTION_XORCOMBINATION     (TIM_CR2_TI1S)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup TIM_DMA_Base_address  TIM DMA Base address\r\n  * @{\r\n  */\r\n#define TIM_DMABASE_CR1                    (0x00000000U)\r\n#define TIM_DMABASE_CR2                    (0x00000001U)\r\n#define TIM_DMABASE_SMCR                   (0x00000002U)\r\n#define TIM_DMABASE_DIER                   (0x00000003U)\r\n#define TIM_DMABASE_SR                     (0x00000004U)\r\n#define TIM_DMABASE_EGR                    (0x00000005U)\r\n#define TIM_DMABASE_CCMR1                  (0x00000006U)\r\n#define TIM_DMABASE_CCMR2                  (0x00000007U)\r\n#define TIM_DMABASE_CCER                   (0x00000008U)\r\n#define TIM_DMABASE_CNT                    (0x00000009U)\r\n#define TIM_DMABASE_PSC                    (0x0000000AU)\r\n#define TIM_DMABASE_ARR                    (0x0000000BU)\r\n#define TIM_DMABASE_RCR                    (0x0000000CU)\r\n#define TIM_DMABASE_CCR1                   (0x0000000DU)\r\n#define TIM_DMABASE_CCR2                   (0x0000000EU)\r\n#define TIM_DMABASE_CCR3                   (0x0000000FU)\r\n#define TIM_DMABASE_CCR4                   (0x00000010U)\r\n#define TIM_DMABASE_BDTR                   (0x00000011U)\r\n#define TIM_DMABASE_DCR                    (0x00000012U)\r\n#define TIM_DMABASE_OR                     (0x00000013U)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup TIM_DMA_Burst_Length  TIM DMA Burst Length \r\n  * @{\r\n  */\r\n#define TIM_DMABURSTLENGTH_1TRANSFER           (0x00000000U)\r\n#define TIM_DMABURSTLENGTH_2TRANSFERS          (0x00000100U)\r\n#define TIM_DMABURSTLENGTH_3TRANSFERS          (0x00000200U)\r\n#define TIM_DMABURSTLENGTH_4TRANSFERS          (0x00000300U)\r\n#define TIM_DMABURSTLENGTH_5TRANSFERS          (0x00000400U)\r\n#define TIM_DMABURSTLENGTH_6TRANSFERS          (0x00000500U)\r\n#define TIM_DMABURSTLENGTH_7TRANSFERS          (0x00000600U)\r\n#define TIM_DMABURSTLENGTH_8TRANSFERS          (0x00000700U)\r\n#define TIM_DMABURSTLENGTH_9TRANSFERS          (0x00000800U)\r\n#define TIM_DMABURSTLENGTH_10TRANSFERS         (0x00000900U)\r\n#define TIM_DMABURSTLENGTH_11TRANSFERS         (0x00000A00U)\r\n#define TIM_DMABURSTLENGTH_12TRANSFERS         (0x00000B00U)\r\n#define TIM_DMABURSTLENGTH_13TRANSFERS         (0x00000C00U)\r\n#define TIM_DMABURSTLENGTH_14TRANSFERS         (0x00000D00U)\r\n#define TIM_DMABURSTLENGTH_15TRANSFERS         (0x00000E00U)\r\n#define TIM_DMABURSTLENGTH_16TRANSFERS         (0x00000F00U)\r\n#define TIM_DMABURSTLENGTH_17TRANSFERS         (0x00001000U)\r\n#define TIM_DMABURSTLENGTH_18TRANSFERS         (0x00001100U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DMA_Handle_index  DMA Handle index\r\n  * @{\r\n  */\r\n#define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0U)       /*!< Index of the DMA handle used for Update DMA requests */\r\n#define TIM_DMA_ID_CC1                   ((uint16_t) 0x1U)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */\r\n#define TIM_DMA_ID_CC2                   ((uint16_t) 0x2U)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */\r\n#define TIM_DMA_ID_CC3                   ((uint16_t) 0x3U)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */\r\n#define TIM_DMA_ID_CC4                   ((uint16_t) 0x4U)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */\r\n#define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x5U)       /*!< Index of the DMA handle used for Commutation DMA requests */\r\n#define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x6U)       /*!< Index of the DMA handle used for Trigger DMA requests */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup Channel_CC_State  Channel CC State\r\n  * @{\r\n  */\r\n#define TIM_CCx_ENABLE                   ((uint32_t)0x0001U)\r\n#define TIM_CCx_DISABLE                  ((uint32_t)0x0000U)\r\n#define TIM_CCxN_ENABLE                  ((uint32_t)0x0004U)\r\n#define TIM_CCxN_DISABLE                 ((uint32_t)0x0000U)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */   \r\n  \r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup TIM_Exported_Macros TIM Exported Macros\r\n  * @{\r\n  */\r\n/** @brief Reset TIM handle state\r\n  * @param  __HANDLE__ TIM handle\r\n  * @retval None\r\n  */\r\n#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)\r\n\r\n/**\r\n  * @brief  Enable the TIM peripheral.\r\n  * @param  __HANDLE__ TIM handle\r\n  * @retval None\r\n */\r\n#define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))\r\n\r\n/**\r\n  * @brief  Enable the TIM update source request.\r\n  * @param  __HANDLE__ TIM handle\r\n  * @retval None\r\n */\r\n#define __HAL_TIM_URS_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->CR1|=(TIM_CR1_URS))\r\n\r\n/**\r\n  * @brief  Enable the TIM main Output.\r\n  * @param  __HANDLE__ TIM handle\r\n  * @retval None\r\n  */\r\n#define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))\r\n\r\n/**\r\n  * @brief  Disable the TIM peripheral.\r\n  * @param  __HANDLE__ TIM handle\r\n  * @retval None\r\n  */\r\n#define __HAL_TIM_DISABLE(__HANDLE__) \\\r\n                        do { \\\r\n                          if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \\\r\n                          { \\\r\n                            if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \\\r\n                            { \\\r\n                              (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \\\r\n                            } \\\r\n                          } \\\r\n                        } while(0)\r\n                        \r\n/**\r\n  * @brief  Disable the TIM update source request.\r\n  * @param  __HANDLE__ TIM handle\r\n  * @retval None\r\n  */\r\n#define __HAL_TIM_URS_DISABLE(__HANDLE__)            ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))\r\n\r\n/**\r\n  * @brief  Disable the TIM main Output.\r\n  * @param  __HANDLE__ TIM handle\r\n  * @retval None\r\n  * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled\r\n  */\r\n#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \\\r\n                        do { \\\r\n                          if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \\\r\n                          { \\\r\n                            if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \\\r\n                            { \\\r\n                              (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \\\r\n                            } \\\r\n                          } \\\r\n                        } while(0)\r\n\r\n/** @brief  Enable the specified TIM interrupt.\r\n  * @param  __HANDLE__: specifies the TIM Handle.\r\n  * @param  __INTERRUPT__: specifies the TIM interrupt source to enable.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_IT_UPDATE: Update interrupt\r\n  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt\r\n  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt\r\n  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt\r\n  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt\r\n  *            @arg TIM_IT_COM:   Commutation interrupt\r\n  *            @arg TIM_IT_TRIGGER: Trigger interrupt\r\n  *            @arg TIM_IT_BREAK: Break interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))\r\n\r\n/** @brief  Disable the specified TIM interrupt.\r\n  * @param  __HANDLE__: specifies the TIM Handle.\r\n  * @param  __INTERRUPT__: specifies the TIM interrupt source to disable.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_IT_UPDATE: Update interrupt\r\n  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt\r\n  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt\r\n  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt\r\n  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt\r\n  *            @arg TIM_IT_COM:   Commutation interrupt\r\n  *            @arg TIM_IT_TRIGGER: Trigger interrupt\r\n  *            @arg TIM_IT_BREAK: Break interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))\r\n\r\n/** @brief  Enable the specified DMA request.\r\n  * @param  __HANDLE__: specifies the TIM Handle.\r\n  * @param  __DMA__: specifies the TIM DMA request to enable.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_DMA_UPDATE: Update DMA request\r\n  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request\r\n  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request\r\n  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request\r\n  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request\r\n  *            @arg TIM_DMA_COM:   Commutation DMA request\r\n  *            @arg TIM_DMA_TRIGGER: Trigger DMA request\r\n  * @retval None\r\n  */\r\n#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))\r\n\r\n/** @brief  Disable the specified DMA request.\r\n  * @param  __HANDLE__: specifies the TIM Handle.\r\n  * @param  __DMA__: specifies the TIM DMA request to disable.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_DMA_UPDATE: Update DMA request\r\n  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request\r\n  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request\r\n  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request\r\n  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request\r\n  *            @arg TIM_DMA_COM:   Commutation DMA request\r\n  *            @arg TIM_DMA_TRIGGER: Trigger DMA request\r\n  * @retval None\r\n  */\r\n#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))\r\n\r\n/** @brief  Check whether the specified TIM interrupt flag is set or not.\r\n  * @param  __HANDLE__: specifies the TIM Handle.\r\n  * @param  __FLAG__: specifies the TIM interrupt flag to check.\r\n  *        This parameter can be one of the following values:\r\n  *            @arg TIM_FLAG_UPDATE: Update interrupt flag\r\n  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag\r\n  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag\r\n  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag\r\n  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag\r\n  *            @arg TIM_FLAG_COM:  Commutation interrupt flag\r\n  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag\r\n  *            @arg TIM_FLAG_BREAK: Break interrupt flag\r\n  *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag\r\n  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag\r\n  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag\r\n  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag\r\n  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag\r\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))\r\n\r\n/** @brief  Clear the specified TIM interrupt flag.\r\n  * @param  __HANDLE__: specifies the TIM Handle.\r\n  * @param  __FLAG__: specifies the TIM interrupt flag to clear.\r\n  *        This parameter can be one of the following values:\r\n  *            @arg TIM_FLAG_UPDATE: Update interrupt flag\r\n  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag\r\n  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag\r\n  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag\r\n  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag\r\n  *            @arg TIM_FLAG_COM:  Commutation interrupt flag\r\n  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag\r\n  *            @arg TIM_FLAG_BREAK: Break interrupt flag\r\n  *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag\r\n  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag\r\n  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag\r\n  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag\r\n  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag\r\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))\r\n\r\n/**\r\n  * @brief  Check whether the specified TIM interrupt source is enabled or not.\r\n  * @param  __HANDLE__: TIM handle\r\n  * @param  __INTERRUPT__: specifies the TIM interrupt source to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_IT_UPDATE: Update interrupt\r\n  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt\r\n  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt\r\n  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt\r\n  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt\r\n  *            @arg TIM_IT_COM:   Commutation interrupt\r\n  *            @arg TIM_IT_TRIGGER: Trigger interrupt\r\n  *            @arg TIM_IT_BREAK: Break interrupt\r\n  * @retval The state of TIM_IT (SET or RESET).\r\n  */\r\n#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r\n\r\n/** @brief Clear the TIM interrupt pending bits.\r\n  * @param  __HANDLE__: TIM handle\r\n  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_IT_UPDATE: Update interrupt\r\n  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt\r\n  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt\r\n  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt\r\n  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt\r\n  *            @arg TIM_IT_COM:   Commutation interrupt\r\n  *            @arg TIM_IT_TRIGGER: Trigger interrupt\r\n  *            @arg TIM_IT_BREAK: Break interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Indicates whether or not the TIM Counter is used as downcounter.\r\n  * @param  __HANDLE__: TIM handle.\r\n  * @retval False (Counter used as upcounter) or True (Counter used as downcounter)\r\n  * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder\r\nmode.\r\n  */\r\n#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)            (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))\r\n\r\n/**\r\n  * @brief  Set the TIM Prescaler on runtime.\r\n  * @param  __HANDLE__: TIM handle.\r\n  * @param  __PRESC__: specifies the Prescaler new value.\r\n  * @retval None\r\n  */\r\n#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))\r\n\r\n/**\r\n  * @brief  Set the TIM Counter Register value on runtime.\r\n  * @param  __HANDLE__ TIM handle.\r\n  * @param  __COUNTER__ specifies the Counter register new value.\r\n  * @retval None\r\n  */\r\n#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))\r\n\r\n/**\r\n  * @brief  Get the TIM Counter Register value on runtime.\r\n  * @param  __HANDLE__ TIM handle.\r\n  * @retval 16-bit or 32-bit value of the timer counter register\r\n  */\r\n#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)\r\n\r\n/**\r\n  * @brief  Set the TIM Autoreload Register value on runtime without calling \r\n  *         another time any Init function.\r\n  * @param  __HANDLE__ TIM handle.\r\n  * @param  __AUTORELOAD__ specifies the Counter register new value.\r\n  * @retval 16-bit or 32-bit value of the timer auto-reload\r\n  */\r\n#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__)                  \\\r\n                        do{                                                  \\\r\n                            (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \\\r\n                            (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \\\r\n                          } while(0)\r\n/**\r\n  * @brief  Get the TIM Autoreload Register value on runtime\r\n  * @param  __HANDLE__ TIM handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)\r\n\r\n/**\r\n  * @brief  Set the TIM Clock Division value on runtime without calling \r\n  *         another time any Init function. \r\n  * @param  __HANDLE__ TIM handle.\r\n  * @param  __CKD__ specifies the clock division value.\r\n  *          This parameter can be one of the following value:\r\n  *            @arg TIM_CLOCKDIVISION_DIV1\r\n  *            @arg TIM_CLOCKDIVISION_DIV2\r\n  *            @arg TIM_CLOCKDIVISION_DIV4\r\n  * @retval None\r\n  */\r\n#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \\\r\n                        do{                                                             \\\r\n                              (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD);  \\\r\n                              (__HANDLE__)->Instance->CR1 |= (__CKD__);                 \\\r\n                              (__HANDLE__)->Init.ClockDivision = (__CKD__);             \\\r\n                          } while(0)\r\n/**\r\n  * @brief  Get the TIM Clock Division value on runtime\r\n  * @param  __HANDLE__ TIM handle.\r\n  * @retval The clock division can be one of the following values:\r\n  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT\r\n  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT\r\n  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT\r\n  */\r\n#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)\r\n\r\n/**\r\n  * @brief  Set the TIM Input Capture prescaler on runtime without calling \r\n  *         another time HAL_TIM_IC_ConfigChannel() function.\r\n  * @param  __HANDLE__ TIM handle.\r\n  * @param  __CHANNEL__  TIM Channels to be configured.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @param  __ICPSC__ specifies the Input Capture4 prescaler new value.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_ICPSC_DIV1: no prescaler\r\n  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r\n  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r\n  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r\n  * @retval None\r\n  */\r\n#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \\\r\n                        do{                                                    \\\r\n                              TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \\\r\n                              TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \\\r\n                          } while(0)\r\n\r\n/**\r\n  * @brief  Get the TIM Input Capture prescaler on runtime\r\n  * @param  __HANDLE__ TIM handle.\r\n  * @param  __CHANNEL__  TIM Channels to be configured.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value\r\n  *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value\r\n  *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value\r\n  *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value\r\n  * @retval The input capture prescaler can be one of the following values:\r\n  *            @arg TIM_ICPSC_DIV1: no prescaler\r\n  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r\n  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r\n  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r\n  */\r\n#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \\\r\n  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\\\r\n   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\\\r\n   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\\\r\n   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)\r\n  \r\n/**\r\n  * @brief  Set the TIM Capture x input polarity on runtime.\r\n  * @param  __HANDLE__ TIM handle.\r\n  * @param  __CHANNEL__ TIM Channels to be configured.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @param  __POLARITY__ Polarity for TIx source   \r\n  *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge\r\n  *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge\r\n  *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge\r\n  * @note  The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized  for TIM Channel 4.     \r\n  * @retval None\r\n  */\r\n#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)                          \\\r\n                       do{                                                                            \\\r\n                           TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \\\r\n                           TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \\\r\n                         }while(0)\r\n\t\t\t\t\t\t\t\t\t\t\t \r\n/**\r\n  * @}\r\n  */\r\n/* End of exported macros ----------------------------------------------------*/\r\n\r\n/* Include TIM HAL Extension module */\r\n#include \"stm32f7xx_hal_tim_ex.h\"\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup TIM_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup TIM_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n\r\n/* Time Base functions ********************************************************/\r\nHAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);\r\nHAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);\r\nvoid HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);\r\nvoid HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);\r\n/* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);\r\nHAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);\r\nHAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);\r\n/* Non-Blocking mode: DMA */\r\nHAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);\r\nHAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup TIM_Exported_Functions_Group2\r\n  * @{\r\n  */\r\n/* Timer Output Compare functions **********************************************/\r\nHAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);\r\nHAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);\r\nvoid HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);\r\nvoid HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);\r\n/* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r\n/* Non-Blocking mode: DMA */\r\nHAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r\nHAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup TIM_Exported_Functions_Group3\r\n  * @{\r\n  */\r\n/* Timer PWM functions *********************************************************/\r\nHAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);\r\nHAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);\r\nvoid HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);\r\nvoid HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);\r\n\r\n/* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r\n/* Non-Blocking mode: DMA */\r\nHAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r\nHAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup TIM_Exported_Functions_Group4\r\n  * @{\r\n  */\r\n/* Timer Input Capture functions ***********************************************/\r\nHAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);\r\nHAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);\r\nvoid HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);\r\nvoid HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);\r\n/* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r\n/* Non-Blocking mode: DMA */\r\nHAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r\nHAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup TIM_Exported_Functions_Group5\r\n  * @{\r\n  */\r\n/* Timer One Pulse functions ***************************************************/\r\nHAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);\r\nHAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);\r\nvoid HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);\r\nvoid HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);\r\n/* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r\nHAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r\n\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r\nHAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup TIM_Exported_Functions_Group6\r\n  * @{\r\n  */\r\n/* Timer Encoder functions *****************************************************/\r\nHAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig);\r\nHAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);\r\nvoid HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);\r\nvoid HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);\r\n /* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r\n/* Non-Blocking mode: DMA */\r\nHAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);\r\nHAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup TIM_Exported_Functions_Group7\r\n  * @{\r\n  */\r\n/* Interrupt Handler functions  **********************************************/\r\nvoid HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup TIM_Exported_Functions_Group8\r\n  * @{\r\n  */\r\n/* Control functions  *********************************************************/\r\nHAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel,  uint32_t InputChannel);\r\nHAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);    \r\nHAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);\r\nHAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);\r\nHAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);\r\nHAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \\\r\n                                              uint32_t  *BurstBuffer, uint32_t  BurstLength);\r\nHAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);\r\nHAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \\\r\n                                              uint32_t  *BurstBuffer, uint32_t  BurstLength);\r\nHAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);\r\nHAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);\r\nuint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup TIM_Exported_Functions_Group9\r\n  * @{\r\n  */\r\n/* Callback in non blocking modes (Interrupt and DMA) *************************/\r\nvoid HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);\r\nvoid HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);\r\nvoid HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);\r\nvoid HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);\r\nvoid HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);\r\nvoid HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);\r\n\r\n/* Callbacks Register/UnRegister functions  ***********************************/\r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\nHAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback);\r\nHAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);\r\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup TIM_Exported_Functions_Group10\r\n  * @{\r\n  */\r\n/* Peripheral State functions  **************************************************/\r\nHAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);\r\nHAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);\r\nHAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);\r\nHAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);\r\nHAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);\r\nHAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup TIM_Private_Constants TIM Private Constants\r\n  * @{\r\n  */\r\n/* The counter of a timer instance is disabled only if all the CCx and CCxN\r\n   channels have been disabled */\r\n#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))\r\n#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))\r\n/**\r\n  * @}\r\n  */\r\n/* End of private constants --------------------------------------------------*/\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup TIM_Private_Macros TIM Private Macros\r\n  * @{\r\n  */\r\n\r\n/** @defgroup TIM_IS_TIM_Definitions TIM Private macros to check input parameters\r\n  * @{\r\n  */\r\n#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP)              || \\\r\n                                       ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \\\r\n                                       ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \\\r\n                                       ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \\\r\n                                       ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))\r\n\r\n#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \\\r\n                                           ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \\\r\n                                           ((__DIV__) == TIM_CLOCKDIVISION_DIV4))\r\n\r\n#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \\\r\n                                            ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))\r\n\r\n#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \\\r\n                                      ((__STATE__) == TIM_OCFAST_ENABLE))\r\n\r\n#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \\\r\n                                    ((STATE) == TIM_OUTPUTSTATE_ENABLE))\r\n\r\n#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \\\r\n                                     ((STATE) == TIM_OUTPUTNSTATE_ENABLE))\r\n\r\n#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \\\r\n                                          ((__POLARITY__) == TIM_OCPOLARITY_LOW))\r\n\r\n#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \\\r\n                                           ((__POLARITY__) == TIM_OCNPOLARITY_LOW))\r\n\r\n#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \\\r\n                                        ((__STATE__) == TIM_OCIDLESTATE_RESET))\r\n\r\n#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \\\r\n                                         ((__STATE__) == TIM_OCNIDLESTATE_RESET))\r\n\r\n#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \\\r\n                                          ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \\\r\n                                          ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))\r\n\r\n#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \\\r\n                                            ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \\\r\n                                            ((__SELECTION__) == TIM_ICSELECTION_TRC))\r\n\r\n#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \\\r\n                                            ((__PRESCALER__) == TIM_ICPSC_DIV2) || \\\r\n                                            ((__PRESCALER__) == TIM_ICPSC_DIV4) || \\\r\n                                            ((__PRESCALER__) == TIM_ICPSC_DIV8))\r\n\r\n#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \\\r\n                                   ((__MODE__) == TIM_OPMODE_REPETITIVE))\r\n\r\n#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \\\r\n                                       ((__MODE__) == TIM_ENCODERMODE_TI2) || \\\r\n                                       ((__MODE__) == TIM_ENCODERMODE_TI12))   \r\n\r\n#define IS_TIM_IT(__IT__) ((((__IT__) & 0xFFFFFF00U) == 0x00000000U) && ((__IT__) != 0x00000000U))\r\n\r\n\r\n#define IS_TIM_GET_IT(__IT__) (((__IT__) == TIM_IT_UPDATE)  || \\\r\n                               ((__IT__) == TIM_IT_CC1)     || \\\r\n                               ((__IT__) == TIM_IT_CC2)     || \\\r\n                               ((__IT__) == TIM_IT_CC3)     || \\\r\n                               ((__IT__) == TIM_IT_CC4)     || \\\r\n                               ((__IT__) == TIM_IT_COM)     || \\\r\n                               ((__IT__) == TIM_IT_TRIGGER) || \\\r\n                               ((__IT__) == TIM_IT_BREAK))\r\n\r\n#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))\r\n\r\n#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))\r\n\r\n#define IS_TIM_FLAG(__FLAG__) (((__FLAG__) == TIM_FLAG_UPDATE) || \\\r\n                               ((__FLAG__) == TIM_FLAG_CC1)     || \\\r\n                               ((__FLAG__) == TIM_FLAG_CC2)     || \\\r\n                               ((__FLAG__) == TIM_FLAG_CC3)     || \\\r\n                               ((__FLAG__) == TIM_FLAG_CC4)     || \\\r\n                               ((__FLAG__) == TIM_FLAG_COM)     || \\\r\n                               ((__FLAG__) == TIM_FLAG_TRIGGER) || \\\r\n                               ((__FLAG__) == TIM_FLAG_BREAK)   || \\\r\n                               ((__FLAG__) == TIM_FLAG_BREAK2)  || \\\r\n                               ((__FLAG__) == TIM_FLAG_CC1OF)   || \\\r\n                               ((__FLAG__) == TIM_FLAG_CC2OF)   || \\\r\n                               ((__FLAG__) == TIM_FLAG_CC3OF)   || \\\r\n                               ((__FLAG__) == TIM_FLAG_CC4OF))\r\n\r\n#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \\\r\n                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \\\r\n                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \\\r\n                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \\\r\n                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \\\r\n                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \\\r\n                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \\\r\n                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \\\r\n                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \\\r\n                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))\r\n\r\n#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \\\r\n                                        ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \\\r\n                                        ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \\\r\n                                        ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \\\r\n                                        ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))\r\n\r\n#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \\\r\n                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \\\r\n                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \\\r\n                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) \r\n\r\n#define IS_TIM_CLOCKFILTER(__ICFILTER__)      ((__ICFILTER__) <= 0xF) \r\n\r\n#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \\\r\n                                                    ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))\r\n\r\n#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__)   (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \\\r\n                                                 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \\\r\n                                                 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \\\r\n                                                 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))\r\n\r\n#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) \r\n\r\n#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \\\r\n                                      ((__STATE__) == TIM_OSSR_DISABLE))\r\n\r\n#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \\\r\n                                      ((__STATE__) == TIM_OSSI_DISABLE))\r\n\r\n#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \\\r\n                                      ((__LEVEL__) == TIM_LOCKLEVEL_1) || \\\r\n                                      ((__LEVEL__) == TIM_LOCKLEVEL_2) || \\\r\n                                      ((__LEVEL__) == TIM_LOCKLEVEL_3)) \r\n\r\n#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \\\r\n                                       ((__STATE__) == TIM_BREAK_DISABLE))\r\n\r\n#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \\\r\n                                             ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))\r\n\r\n#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \\\r\n                                                  ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))\r\n\r\n#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \\\r\n                                        ((__SOURCE__) == TIM_TRGO_ENABLE) || \\\r\n                                        ((__SOURCE__) == TIM_TRGO_UPDATE) || \\\r\n                                        ((__SOURCE__) == TIM_TRGO_OC1) || \\\r\n                                        ((__SOURCE__) == TIM_TRGO_OC1REF) || \\\r\n                                        ((__SOURCE__) == TIM_TRGO_OC2REF) || \\\r\n                                        ((__SOURCE__) == TIM_TRGO_OC3REF) || \\\r\n                                        ((__SOURCE__) == TIM_TRGO_OC4REF))\r\n\r\n#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \\\r\n                                     ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))\r\n\r\n#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \\\r\n                                                 ((__SELECTION__) == TIM_TS_ITR1) || \\\r\n                                                 ((__SELECTION__) == TIM_TS_ITR2) || \\\r\n                                                 ((__SELECTION__) == TIM_TS_ITR3) || \\\r\n                                                 ((__SELECTION__) == TIM_TS_TI1F_ED) || \\\r\n                                                 ((__SELECTION__) == TIM_TS_TI1FP1) || \\\r\n                                                 ((__SELECTION__) == TIM_TS_TI2FP2) || \\\r\n                                                 ((__SELECTION__) == TIM_TS_ETRF))\r\n\r\n#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\\r\n                                                      ((SELECTION) == TIM_TS_ITR1) || \\\r\n                                                      ((SELECTION) == TIM_TS_ITR2) || \\\r\n                                                      ((SELECTION) == TIM_TS_ITR3))\r\n\r\n#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \\\r\n                                                               ((__SELECTION__) == TIM_TS_ITR1) || \\\r\n                                                               ((__SELECTION__) == TIM_TS_ITR2) || \\\r\n                                                               ((__SELECTION__) == TIM_TS_ITR3) || \\\r\n                                                               ((__SELECTION__) == TIM_TS_NONE))\r\n\r\n#define IS_TIM_TRIGGERPOLARITY(__POLARITY__)     (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \\\r\n                                                  ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \\\r\n                                                  ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \\\r\n                                                  ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \\\r\n                                                  ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))\r\n\r\n#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__)  (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \\\r\n                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \\\r\n                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \\\r\n                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) \r\n\r\n#define IS_TIM_TRIGGERFILTER(__ICFILTER__)     ((__ICFILTER__) <= 0xF) \r\n\r\n#define IS_TIM_TI1SELECTION(__TI1SELECTION__)   (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \\\r\n                                                 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))\r\n\r\n#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_CR2) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_SMCR) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_DIER) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_SR) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_EGR) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_CCMR1) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_CCMR2) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_CCER) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_CNT) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_PSC) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_ARR) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_RCR) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_CCR1) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_CCR2) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_CCR3) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_CCR4) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_BDTR) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_DCR) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_OR))\r\n\r\n#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \\\r\n                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \\\r\n                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \\\r\n                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \\\r\n                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \\\r\n                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \\\r\n                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \\\r\n                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \\\r\n                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \\\r\n                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \\\r\n                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \\\r\n                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \\\r\n                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \\\r\n                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \\\r\n                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \\\r\n                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \\\r\n                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \\\r\n                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))\r\n\r\n#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_ICPRESCALER TIM Private macros to SET/RESET TIM Input capture value\r\n  * @{\r\n  */\r\n#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \\\r\n(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\\\r\n ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\\\r\n ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\\\r\n ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))\r\n\r\n#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \\\r\n(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\\\r\n ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\\\r\n ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\\\r\n ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_CAPTUREPOLARITY TIM Private macros to SET/RESET TIM capture polarity value\r\n  * @{\r\n  */\r\n#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \\\r\n(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\\\r\n ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\\\r\n ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\\\r\n ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))\r\n\r\n#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \\\r\n(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\\\r\n ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\\\r\n ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\\\r\n ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* End of private macros -----------------------------------------------------*/\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup TIM_Private_Functions TIM Private Functions\r\n  * @{\r\n  */\r\nvoid TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);\r\nvoid TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);\r\nvoid TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r\nvoid TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r\nvoid TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r\nvoid TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r\nvoid TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);\r\n\r\nvoid HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);\r\nvoid HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);\r\nvoid HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);\r\nvoid TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);\r\n\r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\nvoid TIM_ResetCallback(TIM_HandleTypeDef *htim);\r\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n/* End of private functions --------------------------------------------------*/ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_TIM_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_tim_ex.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of TIM HAL Extension module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_TIM_EX_H\r\n#define __STM32F7xx_HAL_TIM_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup TIMEx\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/ \r\n/** @defgroup TIMEx_Exported_Types TIM Exported Types\r\n  * @{\r\n  */\r\n  \r\n/** \r\n  * @brief  TIM Hall sensor Configuration Structure definition  \r\n  */\r\n\r\ntypedef struct\r\n{\r\n                                  \r\n  uint32_t IC1Polarity;            /*!< Specifies the active edge of the input signal.\r\n                                        This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r\n                                                                   \r\n  uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.\r\n                                     This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r\n                                  \r\n  uint32_t IC1Filter;           /*!< Specifies the input capture filter.\r\n                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */  \r\n  uint32_t Commutation_Delay;  /*!< Specifies the pulse value to be loaded into the Capture Compare Register. \r\n                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */                              \r\n} TIM_HallSensor_InitTypeDef;\r\n\r\n/** \r\n  * @brief  TIM Master configuration Structure definition  \r\n  */ \r\ntypedef struct {\r\n  uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection. \r\n                                      This parameter can be a value of @ref TIM_Master_Mode_Selection */ \r\n  uint32_t  MasterOutputTrigger2;  /*!< Trigger output2 (TRGO2) selection \r\n                                      This parameter can be a value of @ref TIMEx_Master_Mode_Selection_2 */\r\n  uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection. \r\n                                      This parameter can be a value of @ref TIM_Master_Slave_Mode */\r\n}TIM_MasterConfigTypeDef;\r\n\r\n/** \r\n  * @brief  TIM Break input(s) and Dead time configuration Structure definition  \r\n  * @note   2 break inputs can be configured (BKIN and BKIN2) with configurable \r\n  *        filter and polarity.\r\n  */ \r\ntypedef struct\r\n{\r\n  uint32_t OffStateRunMode;\t    /*!< TIM off state in run mode.\r\n                                       This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */\r\n  uint32_t OffStateIDLEMode;\t    /*!< TIM off state in IDLE mode.\r\n                                       This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */\r\n  uint32_t LockLevel;\t \t        /*!< TIM Lock level.\r\n                                       This parameter can be a value of @ref TIM_Lock_level */                             \r\n  uint32_t DeadTime;\t \t        /*!< TIM dead Time.\r\n                                       This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */\r\n  uint32_t BreakState;\t \t        /*!< TIM Break State.\r\n                                       This parameter can be a value of @ref TIM_Break_Input_enable_disable */\r\n  uint32_t BreakPolarity;           /*!< TIM Break input polarity.\r\n                                       This parameter can be a value of @ref TIM_Break_Polarity */\r\n  uint32_t BreakFilter;             /*!< Specifies the break input filter.\r\n                                       This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */  \r\n  uint32_t Break2State;\t \t        /*!< TIM Break2 State \r\n                                       This parameter can be a value of @ref TIMEx_Break2_Input_enable_disable */\r\n  uint32_t Break2Polarity;          /*!< TIM Break2 input polarity \r\n                                       This parameter can be a value of @ref TIMEx_Break2_Polarity */\r\n  uint32_t Break2Filter;            /*!< TIM break2 input filter.\r\n                                       This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */  \r\n  uint32_t AutomaticOutput;         /*!< TIM Automatic Output Enable state \r\n                                       This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */           \r\n} TIM_BreakDeadTimeConfigTypeDef;\r\n\r\n#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r\n/** \r\n  * @brief  TIM Break/Break2 input configuration   \r\n  */\r\ntypedef struct {\r\n  uint32_t Source;         /*!< Specifies the source of the timer break input.\r\n                                This parameter can be a value of @ref TIMEx_Break_Input_Source */\r\n  uint32_t Enable;         /*!< Specifies whether or not the break input source is enabled.\r\n                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */\r\n  uint32_t Polarity;       /*!< Specifies the break input source polarity.\r\n                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity\r\n                                Not relevant when analog watchdog output of the DFSDM1 used as break input source */\r\n} TIMEx_BreakInputConfigTypeDef;\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n/**\r\n  * @}\r\n  */  \r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup TIMEx_Exported_Constants  TIMEx Exported Constants\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup TIMEx_Channel TIMEx Channel\r\n  * @{\r\n  */\r\n\r\n#define TIM_CHANNEL_1                      ((uint32_t)0x0000U)\r\n#define TIM_CHANNEL_2                      ((uint32_t)0x0004U)\r\n#define TIM_CHANNEL_3                      ((uint32_t)0x0008U)\r\n#define TIM_CHANNEL_4                      ((uint32_t)0x000CU)\r\n#define TIM_CHANNEL_5                      ((uint32_t)0x0010U)\r\n#define TIM_CHANNEL_6                      ((uint32_t)0x0014U)\r\n#define TIM_CHANNEL_ALL                    ((uint32_t)0x003CU)\r\n\r\n/**\r\n  * @}\r\n  */ \r\n    \r\n/** @defgroup TIMEx_Output_Compare_and_PWM_modes TIMEx Output Compare and PWM Modes\r\n  * @{\r\n  */\r\n#define TIM_OCMODE_TIMING                   ((uint32_t)0x0000U)\r\n#define TIM_OCMODE_ACTIVE                   ((uint32_t)TIM_CCMR1_OC1M_0)\r\n#define TIM_OCMODE_INACTIVE                 ((uint32_t)TIM_CCMR1_OC1M_1)\r\n#define TIM_OCMODE_TOGGLE                   ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)\r\n#define TIM_OCMODE_PWM1                     ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)\r\n#define TIM_OCMODE_PWM2                     ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)\r\n#define TIM_OCMODE_FORCED_ACTIVE            ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)\r\n#define TIM_OCMODE_FORCED_INACTIVE          ((uint32_t)TIM_CCMR1_OC1M_2)\r\n\r\n#define TIM_OCMODE_RETRIGERRABLE_OPM1      ((uint32_t)TIM_CCMR1_OC1M_3)\r\n#define TIM_OCMODE_RETRIGERRABLE_OPM2      ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)\r\n#define TIM_OCMODE_COMBINED_PWM1           ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)\r\n#define TIM_OCMODE_COMBINED_PWM2           ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)\r\n#define TIM_OCMODE_ASSYMETRIC_PWM1         ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)\r\n#define TIM_OCMODE_ASSYMETRIC_PWM2         ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)\r\n/**\r\n  * @}\r\n  */\r\n      \r\n/** @defgroup TIMEx_Remap  TIMEx Remap\r\n  * @{\r\n  */\r\n#define TIM_TIM2_TIM8_TRGO                     (0x00000000U)\r\n#define TIM_TIM2_ETH_PTP                       (0x00000400U)\r\n#define TIM_TIM2_USBFS_SOF                     (0x00000800U)\r\n#define TIM_TIM2_USBHS_SOF                     (0x00000C00U)\r\n#define TIM_TIM5_GPIO                          (0x00000000U)\r\n#define TIM_TIM5_LSI                           (0x00000040U)\r\n#define TIM_TIM5_LSE                           (0x00000080U)\r\n#define TIM_TIM5_RTC                           (0x000000C0U)\r\n#define TIM_TIM11_GPIO                         (0x00000000U)\r\n#define TIM_TIM11_SPDIFRX                      (0x00000001U)\r\n#define TIM_TIM11_HSE                          (0x00000002U)\r\n#define TIM_TIM11_MCO1                         (0x00000003U)\r\n/**\r\n  * @}\r\n  */\t\r\n\r\n/** @defgroup TIMEx_ClearInput_Source TIMEx Clear Input Source\r\n  * @{\r\n  */\r\n#define TIM_CLEARINPUTSOURCE_ETR            ((uint32_t)0x0001U) \r\n#define TIM_CLEARINPUTSOURCE_NONE           ((uint32_t)0x0000U)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup TIMEx_Break2_Input_enable_disable  TIMEx Break input 2 Enable\r\n  * @{\r\n  */                         \r\n#define TIM_BREAK2_DISABLE         ((uint32_t)0x00000000U)\r\n#define TIM_BREAK2_ENABLE          ((uint32_t)TIM_BDTR_BK2E)\r\n/**\r\n  * @}\r\n  */\r\n    \r\n/** @defgroup TIMEx_Break2_Polarity TIMEx Break2 Polarity\r\n  * @{\r\n  */\r\n#define TIM_BREAK2POLARITY_LOW        ((uint32_t)0x00000000U)\r\n#define TIM_BREAK2POLARITY_HIGH       (TIM_BDTR_BK2P)\r\n/**\r\n  * @}\r\n  */\r\n \r\n/** @defgroup TIMEx_Group_Channel5 TIMEx Group Channel 5 and Channel 1, 2 or 3\r\n  * @{\r\n  */\r\n#define TIM_GROUPCH5_NONE       ((uint32_t)0x00000000U)  /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */\r\n#define TIM_GROUPCH5_OC1REFC    (TIM_CCR5_GC5C1)      /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */\r\n#define TIM_GROUPCH5_OC2REFC    (TIM_CCR5_GC5C2)      /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */\r\n#define TIM_GROUPCH5_OC3REFC    (TIM_CCR5_GC5C3)       /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */\r\n/**\r\n  * @}\r\n  */\r\n\t\r\n/** @defgroup TIMEx_Master_Mode_Selection_2 TIMEx Master Mode Selection 2 (TRGO2)\r\n  * @{\r\n  */  \r\n#define\tTIM_TRGO2_RESET                          ((uint32_t)0x00000000U)             \r\n#define\tTIM_TRGO2_ENABLE                         ((uint32_t)(TIM_CR2_MMS2_0))          \r\n#define\tTIM_TRGO2_UPDATE                         ((uint32_t)(TIM_CR2_MMS2_1))\r\n#define\tTIM_TRGO2_OC1                            ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))   \r\n#define\tTIM_TRGO2_OC1REF                         ((uint32_t)(TIM_CR2_MMS2_2))           \r\n#define\tTIM_TRGO2_OC2REF                         ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))          \r\n#define\tTIM_TRGO2_OC3REF                         ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))           \r\n#define\tTIM_TRGO2_OC4REF                         ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))  \r\n#define\tTIM_TRGO2_OC5REF                         ((uint32_t)(TIM_CR2_MMS2_3))   \r\n#define\tTIM_TRGO2_OC6REF                         ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))   \r\n#define\tTIM_TRGO2_OC4REF_RISINGFALLING           ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))   \r\n#define\tTIM_TRGO2_OC6REF_RISINGFALLING           ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))   \r\n#define\tTIM_TRGO2_OC4REF_RISING_OC6REF_RISING    ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))   \r\n#define\tTIM_TRGO2_OC4REF_RISING_OC6REF_FALLING   ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))   \r\n#define\tTIM_TRGO2_OC5REF_RISING_OC6REF_RISING    ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))   \r\n#define\tTIM_TRGO2_OC5REF_RISING_OC6REF_FALLING   ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))   \r\n/**\r\n  * @}\r\n  */ \r\n    \r\n/** @defgroup TIMEx_Slave_Mode TIMEx Slave mode\r\n  * @{\r\n  */\r\n#define TIM_SLAVEMODE_DISABLE                ((uint32_t)0x0000U)\r\n#define TIM_SLAVEMODE_RESET                  ((uint32_t)(TIM_SMCR_SMS_2))\r\n#define TIM_SLAVEMODE_GATED                  ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))\r\n#define TIM_SLAVEMODE_TRIGGER                ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))\r\n#define TIM_SLAVEMODE_EXTERNAL1              ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))\r\n#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER  ((uint32_t)(TIM_SMCR_SMS_3))\r\n/**\r\n  * @}\r\n  */\r\n#if defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r\n/** @defgroup TIMEx_Break_Input TIM  Extended Break input\r\n  * @{\r\n  */\r\n#define TIM_BREAKINPUT_BRK     ((uint32_t)0x00000001U) /* !< Timer break input  */\r\n#define TIM_BREAKINPUT_BRK2    ((uint32_t)0x00000002U) /* !< Timer break2 input */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIMEx_Break_Input_Source TIM  Extended Break input source\r\n  * @{\r\n  */\r\n#define TIM_BREAKINPUTSOURCE_BKIN     ((uint32_t)0x00000001U) /* !< An external source (GPIO) is connected to the BKIN pin  */\r\n#define TIM_BREAKINPUTSOURCE_DFSDM1   ((uint32_t)0x00000008U) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling\r\n  * @{\r\n  */\r\n#define TIM_BREAKINPUTSOURCE_DISABLE     ((uint32_t)0x00000000U) /* !< Break input source is disabled */\r\n#define TIM_BREAKINPUTSOURCE_ENABLE      ((uint32_t)0x00000001U) /* !< Break input source is enabled */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup TIMEx_Break_Input_Source_Polarity TIM  Extended Break input polarity\r\n  * @{\r\n  */\r\n#define TIM_BREAKINPUTSOURCE_POLARITY_LOW     ((uint32_t)(0x00000001)) /* !< Break input source is active low */\r\n#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH    ((uint32_t)(0x00000000)) /* !< Break input source is active_high */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup TIMEx_Exported_Macros TIMEx Exported Macros\r\n  * @{\r\n  */  \r\n\r\n/**\r\n  * @brief  Sets the TIM Capture Compare Register value on runtime without\r\n  *         calling another time ConfigChannel function.\r\n  * @param  __HANDLE__ TIM handle.\r\n  * @param  __CHANNEL__  TIM Channels to be configured.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected\r\n  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected\r\n  * @param  __COMPARE__ specifies the Capture Compare register new value.\r\n  * @retval None\r\n  */\r\n#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \\\r\n(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\\\r\n ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\\\r\n ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\\\r\n ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\\\r\n ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\\\r\n ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))\r\n\r\n/**\r\n  * @brief  Gets the TIM Capture Compare Register value on runtime\r\n  * @param  __HANDLE__ TIM handle.\r\n  * @param  __CHANNEL__  TIM Channel associated with the capture compare register\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: get capture/compare 1 register value\r\n  *            @arg TIM_CHANNEL_2: get capture/compare 2 register value\r\n  *            @arg TIM_CHANNEL_3: get capture/compare 3 register value\r\n  *            @arg TIM_CHANNEL_4: get capture/compare 4 register value\r\n  *            @arg TIM_CHANNEL_5: get capture/compare 5 register value\r\n  *            @arg TIM_CHANNEL_6: get capture/compare 6 register value\r\n  * @retval None\r\n  */\r\n#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \\\r\n(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\\\r\n ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\\\r\n ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\\\r\n ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\\\r\n ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\\\r\n ((__HANDLE__)->Instance->CCR6))\r\n\r\n/**\r\n  * @brief  Sets the TIM Output compare preload.\r\n  * @param  __HANDLE__ TIM handle.\r\n  * @param  __CHANNEL__ TIM Channels to be configured.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected\r\n  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected\r\n  * @retval None\r\n  */\r\n#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \\\r\n        (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\\\r\n         ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\\\r\n         ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\\\r\n         ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\\\r\n         ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\\\r\n         ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))\r\n\r\n/**\r\n  * @brief  Resets the TIM Output compare preload.\r\n  * @param  __HANDLE__ TIM handle.\r\n  * @param  __CHANNEL__ TIM Channels to be configured.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected\r\n  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected\r\n  * @retval None\r\n  */\r\n#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \\\r\n        (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\\\r\n         ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\\\r\n         ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\\\r\n         ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\\\r\n         ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\\\r\n         ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE))\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup TIMEx_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup TIMEx_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n/*  Timer Hall Sensor functions  **********************************************/\r\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef* htim, TIM_HallSensor_InitTypeDef* sConfig);\r\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef* htim);\r\n\r\nvoid HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef* htim);\r\nvoid HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef* htim);\r\n\r\n /* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef* htim);\r\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef* htim);\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef* htim);\r\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef* htim);\r\n/* Non-Blocking mode: DMA */\r\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef* htim, uint32_t *pData, uint16_t Length);\r\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef* htim);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup TIMEx_Exported_Functions_Group2\r\n  * @{\r\n  */\r\n/*  Timer Complementary Output Compare functions  *****************************/\r\n/* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);\r\n\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);\r\n\r\n/* Non-Blocking mode: DMA */\r\nHAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r\nHAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup TIMEx_Exported_Functions_Group3\r\n  * @{\r\n  */\r\n/*  Timer Complementary PWM functions  ****************************************/\r\n/* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);\r\n\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);\r\n/* Non-Blocking mode: DMA */\r\nHAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r\nHAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup TIMEx_Exported_Functions_Group4\r\n  * @{\r\n  */\r\n/*  Timer Complementary One Pulse functions  **********************************/\r\n/* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef* htim, uint32_t OutputChannel);\r\nHAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef* htim, uint32_t OutputChannel);\r\n\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);\r\nHAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup TIMEx_Exported_Functions_Group5\r\n  * @{\r\n  */\r\n/* Extension Control functions  ************************************************/\r\nHAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef* htim, uint32_t  InputTrigger, uint32_t  CommutationSource);\r\nHAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef* htim, uint32_t  InputTrigger, uint32_t  CommutationSource);\r\nHAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef* htim, uint32_t  InputTrigger, uint32_t  CommutationSource);\r\nHAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef* htim, TIM_MasterConfigTypeDef * sMasterConfig);\r\nHAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef* htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);\r\n#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r\nHAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\nHAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef* htim, uint32_t Remap);\r\nHAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRef);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup TIMEx_Exported_Functions_Group6\r\n  * @{\r\n  */ \r\n/* Extension Callback *********************************************************/\r\nvoid HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef* htim);\r\nvoid HAL_TIMEx_BreakCallback(TIM_HandleTypeDef* htim);\r\nvoid HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup TIMEx_Exported_Functions_Group7\r\n  * @{\r\n  */\r\n/* Extension Peripheral State functions  **************************************/\r\nHAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup TIMEx_Private_Macros TIMEx Private Macros\r\n  * @{\r\n  */\r\n#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \\\r\n                                  ((CHANNEL) == TIM_CHANNEL_2) || \\\r\n                                  ((CHANNEL) == TIM_CHANNEL_3) || \\\r\n                                  ((CHANNEL) == TIM_CHANNEL_4) || \\\r\n                                  ((CHANNEL) == TIM_CHANNEL_5) || \\\r\n                                  ((CHANNEL) == TIM_CHANNEL_6) || \\\r\n                                  ((CHANNEL) == TIM_CHANNEL_ALL))\r\n                                 \r\n#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \\\r\n                                       ((CHANNEL) == TIM_CHANNEL_2))\r\n                                      \r\n#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \\\r\n                                      ((CHANNEL) == TIM_CHANNEL_2))                                       \r\n\r\n#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \\\r\n                                                ((CHANNEL) == TIM_CHANNEL_2) || \\\r\n                                                ((CHANNEL) == TIM_CHANNEL_3))\r\n#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1)               || \\\r\n\t                       ((MODE) == TIM_OCMODE_PWM2)               || \\\r\n                               ((MODE) == TIM_OCMODE_COMBINED_PWM1)      || \\\r\n                               ((MODE) == TIM_OCMODE_COMBINED_PWM2)      || \\\r\n                               ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM1)    || \\\r\n                               ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM2))\r\n                              \r\n#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING)             || \\\r\n                             ((MODE) == TIM_OCMODE_ACTIVE)             || \\\r\n                             ((MODE) == TIM_OCMODE_INACTIVE)           || \\\r\n                             ((MODE) == TIM_OCMODE_TOGGLE)             || \\\r\n                             ((MODE) == TIM_OCMODE_FORCED_ACTIVE)      || \\\r\n                             ((MODE) == TIM_OCMODE_FORCED_INACTIVE)    || \\\r\n                             ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \\\r\n                             ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM2))\r\n#define IS_TIM_REMAP(__TIM_REMAP__)\t (((__TIM_REMAP__) == TIM_TIM2_TIM8_TRGO)||\\\r\n                                      ((__TIM_REMAP__) == TIM_TIM2_ETH_PTP)||\\\r\n                                      ((__TIM_REMAP__) == TIM_TIM2_USBFS_SOF)||\\\r\n                                      ((__TIM_REMAP__) == TIM_TIM2_USBHS_SOF)||\\\r\n                                      ((__TIM_REMAP__) == TIM_TIM5_GPIO)||\\\r\n                                      ((__TIM_REMAP__) == TIM_TIM5_LSI)||\\\r\n                                      ((__TIM_REMAP__) == TIM_TIM5_LSE)||\\\r\n                                      ((__TIM_REMAP__) == TIM_TIM5_RTC)||\\\r\n                                      ((__TIM_REMAP__) == TIM_TIM11_GPIO)||\\\r\n                                      ((__TIM_REMAP__) == TIM_TIM11_SPDIFRX)||\\\r\n                                      ((__TIM_REMAP__) == TIM_TIM11_HSE)||\\\r\n                                      ((__TIM_REMAP__) == TIM_TIM11_MCO1))  \r\n#define IS_TIM_DEADTIME(__DEADTIME__)      ((__DEADTIME__) <= 0xFF) \r\n#define IS_TIM_BREAK_FILTER(__FILTER__) ((__FILTER__) <= 0xF)\r\n#define IS_TIM_CLEARINPUT_SOURCE(MODE) (((MODE) == TIM_CLEARINPUTSOURCE_ETR)      || \\\r\n                                        ((MODE) == TIM_CLEARINPUTSOURCE_NONE))\r\n#define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_BREAK2_ENABLE) || \\\r\n                                    ((STATE) == TIM_BREAK2_DISABLE))\r\n#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \\\r\n                                              ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))\r\n#define IS_TIM_GROUPCH5(OCREF) ((((OCREF) & 0x1FFFFFFF) == 0x00000000))\r\n#define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2_RESET)                        || \\\r\n                                     ((SOURCE) == TIM_TRGO2_ENABLE)                       || \\\r\n                                     ((SOURCE) == TIM_TRGO2_UPDATE)                       || \\\r\n                                     ((SOURCE) == TIM_TRGO2_OC1)                          || \\\r\n                                     ((SOURCE) == TIM_TRGO2_OC1REF)                       || \\\r\n                                     ((SOURCE) == TIM_TRGO2_OC2REF)                       || \\\r\n                                     ((SOURCE) == TIM_TRGO2_OC3REF)                       || \\\r\n                                     ((SOURCE) == TIM_TRGO2_OC3REF)                       || \\\r\n                                     ((SOURCE) == TIM_TRGO2_OC4REF)                       || \\\r\n                                     ((SOURCE) == TIM_TRGO2_OC5REF)                       || \\\r\n                                     ((SOURCE) == TIM_TRGO2_OC6REF)                       || \\\r\n                                     ((SOURCE) == TIM_TRGO2_OC4REF_RISINGFALLING)         || \\\r\n                                     ((SOURCE) == TIM_TRGO2_OC6REF_RISINGFALLING)         || \\\r\n                                     ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING)  || \\\r\n                                     ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \\\r\n                                     ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING)  || \\\r\n                                     ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))\r\n#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE)   || \\\r\n                                 ((MODE) == TIM_SLAVEMODE_RESET)     || \\\r\n                                 ((MODE) == TIM_SLAVEMODE_GATED)     || \\\r\n                                 ((MODE) == TIM_SLAVEMODE_TRIGGER)   || \\\r\n                                 ((MODE) == TIM_SLAVEMODE_EXTERNAL1) || \\\r\n                                 ((MODE) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))\r\n\r\n#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r\n#define IS_TIM_BREAKINPUT(__BREAKINPUT__)  (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK)  || \\\r\n                                            ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))\r\n                                            \r\n#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \\\r\n                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM))\r\n\r\n#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)  (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE)  || \\\r\n                                                   ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))\r\n                                   \r\n#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW)  || \\\r\n                                                         ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))\r\n\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup TIMEx_Private_Functions TIMEx Private Functions\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n    \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_TIM_EX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_uart.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of UART HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************  \r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_UART_H\r\n#define __STM32F7xx_HAL_UART_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup UART\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup UART_Exported_Types UART Exported Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief UART Init Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t BaudRate;                  /*!< This member configures the UART communication baud rate.\r\n                                           The baud rate register is computed using the following formula:\r\n                                           - If oversampling is 16 or in LIN mode,\r\n                                              Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate)))\r\n                                           - If oversampling is 8,\r\n                                              Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4]\r\n                                              Baud Rate Register[3] =  0\r\n                                              Baud Rate Register[2:0] =  (((2 * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1      */\r\n\r\n  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.\r\n                                           This parameter can be a value of @ref UARTEx_Word_Length */\r\n\r\n  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.\r\n                                           This parameter can be a value of @ref UART_Stop_Bits */\r\n\r\n  uint32_t Parity;                    /*!< Specifies the parity mode.\r\n                                           This parameter can be a value of @ref UART_Parity\r\n                                           @note When parity is enabled, the computed parity is inserted\r\n                                                 at the MSB position of the transmitted data (9th bit when\r\n                                                 the word length is set to 9 data bits; 8th bit when the\r\n                                                 word length is set to 8 data bits). */\r\n\r\n  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.\r\n                                           This parameter can be a value of @ref UART_Mode */\r\n\r\n  uint32_t HwFlowCtl;                 /*!< Specifies whether the hardware flow control mode is enabled\r\n                                           or disabled.\r\n                                           This parameter can be a value of @ref UART_Hardware_Flow_Control */\r\n\r\n  uint32_t OverSampling;              /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).\r\n                                           This parameter can be a value of @ref UART_Over_Sampling */\r\n\r\n  uint32_t OneBitSampling;            /*!< Specifies whether a single sample or three samples' majority vote is selected.\r\n                                           Selecting the single sample method increases the receiver tolerance to clock\r\n                                           deviations. This parameter can be a value of @ref UART_OneBit_Sampling */\r\n}UART_InitTypeDef;\r\n\r\n/**\r\n  * @brief  UART Advanced Features initialization structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t AdvFeatureInit;        /*!< Specifies which advanced UART features is initialized. Several\r\n                                       Advanced Features may be initialized at the same time .\r\n                                       This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type */\r\n\r\n  uint32_t TxPinLevelInvert;      /*!< Specifies whether the TX pin active level is inverted.\r\n                                       This parameter can be a value of @ref UART_Tx_Inv  */\r\n\r\n  uint32_t RxPinLevelInvert;      /*!< Specifies whether the RX pin active level is inverted.\r\n                                       This parameter can be a value of @ref UART_Rx_Inv  */\r\n\r\n  uint32_t DataInvert;            /*!< Specifies whether data are inverted (positive/direct logic\r\n                                       vs negative/inverted logic).\r\n                                       This parameter can be a value of @ref UART_Data_Inv */\r\n\r\n  uint32_t Swap;                  /*!< Specifies whether TX and RX pins are swapped.\r\n                                       This parameter can be a value of @ref UART_Rx_Tx_Swap */\r\n\r\n  uint32_t OverrunDisable;        /*!< Specifies whether the reception overrun detection is disabled.\r\n                                       This parameter can be a value of @ref UART_Overrun_Disable */\r\n\r\n  uint32_t DMADisableonRxError;   /*!< Specifies whether the DMA is disabled in case of reception error.\r\n                                       This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error */\r\n\r\n  uint32_t AutoBaudRateEnable;    /*!< Specifies whether auto Baud rate detection is enabled.\r\n                                       This parameter can be a value of @ref UART_AutoBaudRate_Enable */\r\n\r\n  uint32_t AutoBaudRateMode;      /*!< If auto Baud rate detection is enabled, specifies how the rate\r\n                                       detection is carried out.\r\n                                       This parameter can be a value of @ref UART_AutoBaud_Rate_Mode */\r\n\r\n  uint32_t MSBFirst;              /*!< Specifies whether MSB is sent first on UART line.\r\n                                       This parameter can be a value of @ref UART_MSB_First */\r\n} UART_AdvFeatureInitTypeDef;\r\n\r\n\r\n\r\n/**\r\n  * @brief HAL UART State structures definition\r\n  * @note  HAL UART State value is a combination of 2 different substates: gState and RxState.\r\n  *        - gState contains UART state information related to global Handle management \r\n  *          and also information related to Tx operations.\r\n  *          gState value coding follow below described bitmap :\r\n  *          b7-b6  Error information \r\n  *             00 : No Error\r\n  *             01 : (Not Used)\r\n  *             10 : Timeout\r\n  *             11 : Error\r\n  *          b5     IP initilisation status\r\n  *             0  : Reset (IP not initialized)\r\n  *             1  : Init done (IP not initialized. HAL UART Init function already called)\r\n  *          b4-b3  (not used)\r\n  *             xx : Should be set to 00\r\n  *          b2     Intrinsic process state\r\n  *             0  : Ready\r\n  *             1  : Busy (IP busy with some configuration or internal operations)\r\n  *          b1     (not used)\r\n  *             x  : Should be set to 0\r\n  *          b0     Tx state\r\n  *             0  : Ready (no Tx operation ongoing)\r\n  *             1  : Busy (Tx operation ongoing)\r\n  *        - RxState contains information related to Rx operations.\r\n  *          RxState value coding follow below described bitmap :\r\n  *          b7-b6  (not used)\r\n  *             xx : Should be set to 00\r\n  *          b5     IP initilisation status\r\n  *             0  : Reset (IP not initialized)\r\n  *             1  : Init done (IP not initialized)\r\n  *          b4-b2  (not used)\r\n  *            xxx : Should be set to 000\r\n  *          b1     Rx state\r\n  *             0  : Ready (no Rx operation ongoing)\r\n  *             1  : Busy (Rx operation ongoing)\r\n  *          b0     (not used)\r\n  *             x  : Should be set to 0.\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_UART_STATE_RESET             = 0x00U,   /*!< Peripheral is not initialized\r\n                                                   Value is allowed for gState and RxState */\r\n  HAL_UART_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use\r\n                                                   Value is allowed for gState and RxState */\r\n  HAL_UART_STATE_BUSY              = 0x24U,   /*!< an internal process is ongoing \r\n                                                   Value is allowed for gState only */\r\n  HAL_UART_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing\r\n                                                   Value is allowed for gState only */\r\n  HAL_UART_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing\r\n                                                   Value is allowed for RxState only */\r\n  HAL_UART_STATE_BUSY_TX_RX        = 0x23U,   /*!< Data Transmission and Reception process is ongoing\r\n                                                   Not to be used for neither gState nor RxState.\r\n                                                   Value is result of combination (Or) between gState and RxState values */\r\n  HAL_UART_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state\r\n                                                   Value is allowed for gState only */\r\n  HAL_UART_STATE_ERROR             = 0xE0U    /*!< Error\r\n                                                   Value is allowed for gState only */\r\n}HAL_UART_StateTypeDef;\r\n\r\n/**\r\n  * @brief UART clock sources definition\r\n  */\r\ntypedef enum\r\n{\r\n  UART_CLOCKSOURCE_PCLK1      = 0x00U,    /*!< PCLK1 clock source  */\r\n  UART_CLOCKSOURCE_PCLK2      = 0x01U,    /*!< PCLK2 clock source  */\r\n  UART_CLOCKSOURCE_HSI        = 0x02U,    /*!< HSI clock source    */\r\n  UART_CLOCKSOURCE_SYSCLK     = 0x04U,    /*!< SYSCLK clock source */\r\n  UART_CLOCKSOURCE_LSE        = 0x08U,    /*!< LSE clock source       */\r\n  UART_CLOCKSOURCE_UNDEFINED  = 0x10U     /*!< Undefined clock source */\r\n}UART_ClockSourceTypeDef;\r\n\r\n/**\r\n  * @brief  UART handle Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  USART_TypeDef            *Instance;        /*!< UART registers base address        */\r\n\r\n  UART_InitTypeDef         Init;             /*!< UART communication parameters      */\r\n\r\n  UART_AdvFeatureInitTypeDef AdvancedInit;   /*!< UART Advanced Features initialization parameters */\r\n\r\n  uint8_t                  *pTxBuffPtr;      /*!< Pointer to UART Tx transfer Buffer */\r\n\r\n  uint16_t                 TxXferSize;       /*!< UART Tx Transfer size              */\r\n\r\n  __IO uint16_t            TxXferCount;      /*!< UART Tx Transfer Counter           */\r\n\r\n  uint8_t                  *pRxBuffPtr;      /*!< Pointer to UART Rx transfer Buffer */\r\n\r\n  uint16_t                 RxXferSize;       /*!< UART Rx Transfer size              */\r\n\r\n  __IO uint16_t            RxXferCount;      /*!< UART Rx Transfer Counter           */\r\n\r\n  uint16_t                 Mask;             /*!< UART Rx RDR register mask          */\r\n\r\n  DMA_HandleTypeDef        *hdmatx;          /*!< UART Tx DMA Handle parameters      */\r\n\r\n  DMA_HandleTypeDef        *hdmarx;          /*!< UART Rx DMA Handle parameters      */\r\n\r\n  HAL_LockTypeDef           Lock;            /*!< Locking object                     */\r\n\r\n  __IO HAL_UART_StateTypeDef    gState;      /*!< UART state information related to global Handle management \r\n                                                  and also related to Tx operations.\r\n                                                  This parameter can be a value of @ref HAL_UART_StateTypeDef */\r\n\r\n  __IO HAL_UART_StateTypeDef    RxState;     /*!< UART state information related to Rx operations.\r\n                                                  This parameter can be a value of @ref HAL_UART_StateTypeDef */\r\n\r\n  __IO uint32_t             ErrorCode;   /*!< UART Error code                    */\r\n\r\n}UART_HandleTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup UART_Exported_Constants UART Exported Constants\r\n  * @{\r\n  */\r\n/** @defgroup UART_Error_Definition   UART Error Definition\r\n  * @{\r\n  */\r\n#define  HAL_UART_ERROR_NONE       ((uint32_t)0x00000000U)    /*!< No error            */\r\n#define  HAL_UART_ERROR_PE         ((uint32_t)0x00000001U)    /*!< Parity error        */\r\n#define  HAL_UART_ERROR_NE         ((uint32_t)0x00000002U)    /*!< Noise error         */\r\n#define  HAL_UART_ERROR_FE         ((uint32_t)0x00000004U)    /*!< frame error         */\r\n#define  HAL_UART_ERROR_ORE        ((uint32_t)0x00000008U)    /*!< Overrun error       */\r\n#define  HAL_UART_ERROR_DMA        ((uint32_t)0x00000010U)    /*!< DMA transfer error  */\r\n/**\r\n  * @}\r\n  */\r\n/** @defgroup UART_Stop_Bits   UART Number of Stop Bits\r\n  * @{\r\n  */\r\n#define UART_STOPBITS_1                     ((uint32_t)0x00000000U)\r\n#define UART_STOPBITS_2                     ((uint32_t)USART_CR2_STOP_1)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Parity  UART Parity\r\n  * @{\r\n  */\r\n#define UART_PARITY_NONE                    ((uint32_t)0x00000000U)\r\n#define UART_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)\r\n#define UART_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control\r\n  * @{\r\n  */\r\n#define UART_HWCONTROL_NONE                  ((uint32_t)0x00000000U)\r\n#define UART_HWCONTROL_RTS                   ((uint32_t)USART_CR3_RTSE)\r\n#define UART_HWCONTROL_CTS                   ((uint32_t)USART_CR3_CTSE)\r\n#define UART_HWCONTROL_RTS_CTS               ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Mode UART Transfer Mode\r\n  * @{\r\n  */\r\n#define UART_MODE_RX                        ((uint32_t)USART_CR1_RE)\r\n#define UART_MODE_TX                        ((uint32_t)USART_CR1_TE)\r\n#define UART_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))\r\n/**\r\n  * @}\r\n  */\r\n\r\n /** @defgroup UART_State  UART State\r\n  * @{\r\n  */\r\n#define UART_STATE_DISABLE                  ((uint32_t)0x00000000U)\r\n#define UART_STATE_ENABLE                   ((uint32_t)USART_CR1_UE)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Over_Sampling UART Over Sampling\r\n  * @{\r\n  */\r\n#define UART_OVERSAMPLING_16                ((uint32_t)0x00000000U)\r\n#define UART_OVERSAMPLING_8                 ((uint32_t)USART_CR1_OVER8)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method\r\n  * @{\r\n  */\r\n#define UART_ONE_BIT_SAMPLE_DISABLE         ((uint32_t)0x00000000U)\r\n#define UART_ONE_BIT_SAMPLE_ENABLE          ((uint32_t)USART_CR3_ONEBIT)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_AutoBaud_Rate_Mode    UART Advanced Feature AutoBaud Rate Mode\r\n  * @{\r\n  */\r\n#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT    ((uint32_t)0x0000U)\r\n#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0)\r\n#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME   ((uint32_t)USART_CR2_ABRMODE_1)\r\n#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME   ((uint32_t)USART_CR2_ABRMODE)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut\r\n  * @{\r\n  */\r\n#define UART_RECEIVER_TIMEOUT_DISABLE       ((uint32_t)0x00000000U)\r\n#define UART_RECEIVER_TIMEOUT_ENABLE        ((uint32_t)USART_CR2_RTOEN)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_LIN    UART Local Interconnection Network mode\r\n  * @{\r\n  */\r\n#define UART_LIN_DISABLE                    ((uint32_t)0x00000000U)\r\n#define UART_LIN_ENABLE                     ((uint32_t)USART_CR2_LINEN)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_LIN_Break_Detection  UART LIN Break Detection\r\n  * @{\r\n  */\r\n#define UART_LINBREAKDETECTLENGTH_10B       ((uint32_t)0x00000000U)\r\n#define UART_LINBREAKDETECTLENGTH_11B       ((uint32_t)USART_CR2_LBDL)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_DMA_Tx    UART DMA Tx\r\n  * @{\r\n  */\r\n#define UART_DMA_TX_DISABLE                 ((uint32_t)0x00000000U)\r\n#define UART_DMA_TX_ENABLE                  ((uint32_t)USART_CR3_DMAT)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_DMA_Rx   UART DMA Rx\r\n  * @{\r\n  */\r\n#define UART_DMA_RX_DISABLE                 ((uint32_t)0x0000U)\r\n#define UART_DMA_RX_ENABLE                  ((uint32_t)USART_CR3_DMAR)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Half_Duplex_Selection  UART Half Duplex Selection\r\n  * @{\r\n  */\r\n#define UART_HALF_DUPLEX_DISABLE            ((uint32_t)0x0000U)\r\n#define UART_HALF_DUPLEX_ENABLE             ((uint32_t)USART_CR3_HDSEL)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_WakeUp_Methods   UART WakeUp Methods\r\n  * @{\r\n  */\r\n#define UART_WAKEUPMETHOD_IDLELINE          ((uint32_t)0x00000000U)\r\n#define UART_WAKEUPMETHOD_ADDRESSMARK       ((uint32_t)USART_CR1_WAKE)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Request_Parameters UART Request Parameters\r\n  * @{\r\n  */\r\n#define UART_AUTOBAUD_REQUEST               ((uint32_t)USART_RQR_ABRRQ)        /*!< Auto-Baud Rate Request */\r\n#define UART_SENDBREAK_REQUEST              ((uint32_t)USART_RQR_SBKRQ)        /*!< Send Break Request */\r\n#define UART_MUTE_MODE_REQUEST              ((uint32_t)USART_RQR_MMRQ)         /*!< Mute Mode Request */\r\n#define UART_RXDATA_FLUSH_REQUEST           ((uint32_t)USART_RQR_RXFRQ)        /*!< Receive Data flush Request */\r\n#define UART_TXDATA_FLUSH_REQUEST           ((uint32_t)USART_RQR_TXFRQ)        /*!< Transmit data flush Request */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Advanced_Features_Initialization_Type  UART Advanced Feature Initialization Type\r\n  * @{\r\n  */\r\n#define UART_ADVFEATURE_NO_INIT                 ((uint32_t)0x00000000U)\r\n#define UART_ADVFEATURE_TXINVERT_INIT           ((uint32_t)0x00000001U)\r\n#define UART_ADVFEATURE_RXINVERT_INIT           ((uint32_t)0x00000002U)\r\n#define UART_ADVFEATURE_DATAINVERT_INIT         ((uint32_t)0x00000004U)\r\n#define UART_ADVFEATURE_SWAP_INIT               ((uint32_t)0x00000008U)\r\n#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT   ((uint32_t)0x00000010U)\r\n#define UART_ADVFEATURE_DMADISABLEONERROR_INIT  ((uint32_t)0x00000020U)\r\n#define UART_ADVFEATURE_AUTOBAUDRATE_INIT       ((uint32_t)0x00000040U)\r\n#define UART_ADVFEATURE_MSBFIRST_INIT           ((uint32_t)0x00000080U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion\r\n  * @{\r\n  */\r\n#define UART_ADVFEATURE_TXINV_DISABLE       ((uint32_t)0x00000000U)\r\n#define UART_ADVFEATURE_TXINV_ENABLE        ((uint32_t)USART_CR2_TXINV)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion\r\n  * @{\r\n  */\r\n#define UART_ADVFEATURE_RXINV_DISABLE       ((uint32_t)0x00000000U)\r\n#define UART_ADVFEATURE_RXINV_ENABLE        ((uint32_t)USART_CR2_RXINV)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Data_Inv  UART Advanced Feature Binary Data Inversion\r\n  * @{\r\n  */\r\n#define UART_ADVFEATURE_DATAINV_DISABLE     ((uint32_t)0x00000000U)\r\n#define UART_ADVFEATURE_DATAINV_ENABLE      ((uint32_t)USART_CR2_DATAINV)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap\r\n  * @{\r\n  */\r\n#define UART_ADVFEATURE_SWAP_DISABLE        ((uint32_t)0x00000000U)\r\n#define UART_ADVFEATURE_SWAP_ENABLE         ((uint32_t)USART_CR2_SWAP)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Overrun_Disable  UART Advanced Feature Overrun Disable\r\n  * @{\r\n  */\r\n#define UART_ADVFEATURE_OVERRUN_ENABLE      ((uint32_t)0x00000000U)\r\n#define UART_ADVFEATURE_OVERRUN_DISABLE     ((uint32_t)USART_CR3_OVRDIS)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_AutoBaudRate_Enable  UART Advanced Feature Auto BaudRate Enable\r\n  * @{\r\n  */\r\n#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE   ((uint32_t)0x00000000U)\r\n#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE    ((uint32_t)USART_CR2_ABREN)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_DMA_Disable_on_Rx_Error   UART Advanced Feature DMA Disable On Rx Error\r\n  * @{\r\n  */\r\n#define UART_ADVFEATURE_DMA_ENABLEONRXERROR    ((uint32_t)0x00000000U)\r\n#define UART_ADVFEATURE_DMA_DISABLEONRXERROR   ((uint32_t)USART_CR3_DDRE)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_MSB_First   UART Advanced Feature MSB First\r\n  * @{\r\n  */\r\n#define UART_ADVFEATURE_MSBFIRST_DISABLE    ((uint32_t)0x00000000U)\r\n#define UART_ADVFEATURE_MSBFIRST_ENABLE     ((uint32_t)USART_CR2_MSBFIRST)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Mute_Mode   UART Advanced Feature Mute Mode Enable\r\n  * @{\r\n  */\r\n#define UART_ADVFEATURE_MUTEMODE_DISABLE    ((uint32_t)0x00000000U)\r\n#define UART_ADVFEATURE_MUTEMODE_ENABLE     ((uint32_t)USART_CR1_MME)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_CR2_ADDRESS_LSB_POS    UART Address-matching LSB Position In CR2 Register\r\n  * @{\r\n  */\r\n#define UART_CR2_ADDRESS_LSB_POS            ((uint32_t) 24U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_DriverEnable_Polarity      UART DriverEnable Polarity\r\n  * @{\r\n  */\r\n#define UART_DE_POLARITY_HIGH               ((uint32_t)0x00000000U)\r\n#define UART_DE_POLARITY_LOW                ((uint32_t)USART_CR3_DEP)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS    UART Driver Enable Assertion Time LSB Position In CR1 Register\r\n  * @{\r\n  */\r\n#define UART_CR1_DEAT_ADDRESS_LSB_POS       ((uint32_t) 21U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS    UART Driver Enable DeAssertion Time LSB Position In CR1 Register\r\n  * @{\r\n  */\r\n#define UART_CR1_DEDT_ADDRESS_LSB_POS       ((uint32_t) 16U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Interruption_Mask    UART Interruptions Flag Mask\r\n  * @{\r\n  */\r\n#define UART_IT_MASK                        ((uint32_t)0x001FU)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_TimeOut_Value    UART polling-based communications time-out value\r\n  * @{\r\n  */\r\n#define HAL_UART_TIMEOUT_VALUE              0x1FFFFFFU\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Flags     UART Status Flags\r\n  *        Elements values convention: 0xXXXX\r\n  *           - 0xXXXX  : Flag mask in the ISR register\r\n  * @{\r\n  */\r\n#define UART_FLAG_TEACK                     ((uint32_t)0x00200000U)\r\n#define UART_FLAG_SBKF                      ((uint32_t)0x00040000U)\r\n#define UART_FLAG_CMF                       ((uint32_t)0x00020000U)\r\n#define UART_FLAG_BUSY                      ((uint32_t)0x00010000U)\r\n#define UART_FLAG_ABRF                      ((uint32_t)0x00008000U)\r\n#define UART_FLAG_ABRE                      ((uint32_t)0x00004000U)\r\n#define UART_FLAG_EOBF                      ((uint32_t)0x00001000U)\r\n#define UART_FLAG_RTOF                      ((uint32_t)0x00000800U)\r\n#define UART_FLAG_CTS                       ((uint32_t)0x00000400U)\r\n#define UART_FLAG_CTSIF                     ((uint32_t)0x00000200U)\r\n#define UART_FLAG_LBDF                      ((uint32_t)0x00000100U)\r\n#define UART_FLAG_TXE                       ((uint32_t)0x00000080U)\r\n#define UART_FLAG_TC                        ((uint32_t)0x00000040U)\r\n#define UART_FLAG_RXNE                      ((uint32_t)0x00000020U)\r\n#define UART_FLAG_IDLE                      ((uint32_t)0x00000010U)\r\n#define UART_FLAG_ORE                       ((uint32_t)0x00000008U)\r\n#define UART_FLAG_NE                        ((uint32_t)0x00000004U)\r\n#define UART_FLAG_FE                        ((uint32_t)0x00000002U)\r\n#define UART_FLAG_PE                        ((uint32_t)0x00000001U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Interrupt_definition   UART Interrupts Definition\r\n  *        Elements values convention: 0000ZZZZ0XXYYYYYb\r\n  *           - YYYYY  : Interrupt source position in the XX register (5bits)\r\n  *           - XX  : Interrupt source register (2bits)\r\n  *                 - 01: CR1 register\r\n  *                 - 10: CR2 register\r\n  *                 - 11: CR3 register\r\n  *           - ZZZZ  : Flag position in the ISR register(4bits)\r\n  * @{\r\n  */\r\n#define UART_IT_PE                          ((uint32_t)0x0028U)\r\n#define UART_IT_TXE                         ((uint32_t)0x0727U)\r\n#define UART_IT_TC                          ((uint32_t)0x0626U)\r\n#define UART_IT_RXNE                        ((uint32_t)0x0525U)\r\n#define UART_IT_IDLE                        ((uint32_t)0x0424U)\r\n#define UART_IT_LBD                         ((uint32_t)0x0846U)\r\n#define UART_IT_CTS                         ((uint32_t)0x096AU)\r\n#define UART_IT_CM                          ((uint32_t)0x112EU)\r\n\r\n/**       Elements values convention: 000000000XXYYYYYb\r\n  *           - YYYYY  : Interrupt source position in the XX register (5bits)\r\n  *           - XX  : Interrupt source register (2bits)\r\n  *                 - 01: CR1 register\r\n  *                 - 10: CR2 register\r\n  *                 - 11: CR3 register\r\n  */\r\n#define UART_IT_ERR                         ((uint32_t)0x0060U)\r\n\r\n/**       Elements values convention: 0000ZZZZ00000000b\r\n  *           - ZZZZ  : Flag position in the ISR register(4bits)\r\n  */\r\n#define UART_IT_ORE                         ((uint32_t)0x0300U)\r\n#define UART_IT_NE                          ((uint32_t)0x0200U)\r\n#define UART_IT_FE                          ((uint32_t)0x0100U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_IT_CLEAR_Flags  UART Interruption Clear Flags\r\n  * @{\r\n  */\r\n#define UART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag */\r\n#define UART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag */\r\n#define UART_CLEAR_NEF                       USART_ICR_NCF             /*!< Noise detected Clear Flag */\r\n#define UART_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag */\r\n#define UART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag */\r\n#define UART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag */\r\n#define UART_CLEAR_LBDF                      USART_ICR_LBDCF           /*!< LIN Break Detection Clear Flag */\r\n#define UART_CLEAR_CTSF                      USART_ICR_CTSCF           /*!< CTS Interrupt Clear Flag */\r\n#define UART_CLEAR_RTOF                      USART_ICR_RTOCF           /*!< Receiver Time Out Clear Flag */\r\n#define UART_CLEAR_EOBF                      USART_ICR_EOBCF           /*!< End Of Block Clear Flag */\r\n#define UART_CLEAR_CMF                       USART_ICR_CMCF            /*!< Character Match Clear Flag */\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macros -----------------------------------------------------------*/\r\n/** @defgroup UART_Exported_Macros UART Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief Reset UART handle state\r\n  * @param  __HANDLE__ UART handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \\\r\n                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \\\r\n                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \\\r\n                                                     } while(0)\r\n\r\n/** @brief  Flush the UART Data registers\r\n  * @param  __HANDLE__ specifies the UART Handle.\r\n  */\r\n#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)  \\\r\n  do{                \\\r\n      SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \\\r\n      SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \\\r\n    }  while(0)\r\n\r\n/** @brief  Clears the specified UART ISR flag, in setting the proper ICR register flag.\r\n  * @param  __HANDLE__ specifies the UART Handle.\r\n  * @param  __FLAG__ specifies the interrupt clear register flag that needs to be set\r\n  *                       to clear the corresponding interrupt\r\n  *          This parameter can be one of the following values:\r\n  *            @arg UART_CLEAR_PEF: Parity Error Clear Flag\r\n  *            @arg UART_CLEAR_FEF: Framing Error Clear Flag\r\n  *            @arg UART_CLEAR_NEF: Noise detected Clear Flag\r\n  *            @arg UART_CLEAR_OREF: OverRun Error Clear Flag\r\n  *            @arg UART_CLEAR_IDLEF: IDLE line detected Clear Flag\r\n  *            @arg UART_CLEAR_TCF: Transmission Complete Clear Flag\r\n  *            @arg UART_CLEAR_LBDF: LIN Break Detection Clear Flag\r\n  *            @arg UART_CLEAR_CTSF: CTS Interrupt Clear Flag\r\n  *            @arg UART_CLEAR_RTOF: Receiver Time Out Clear Flag\r\n  *            @arg UART_CLEAR_EOBF: End Of Block Clear Flag\r\n  *            @arg UART_CLEAR_CMF: Character Match Clear Flag\r\n  * @retval None\r\n  */\r\n#define __HAL_UART_CLEAR_IT(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__FLAG__))\r\n\r\n/** @brief  Clear the UART PE pending flag.\r\n  * @param  __HANDLE__ specifies the UART Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__)   __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_PEF)\r\n\r\n/** @brief  Clear the UART FE pending flag.\r\n  * @param  __HANDLE__ specifies the UART Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__)   __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_FEF)\r\n\r\n/** @brief  Clear the UART NE pending flag.\r\n  * @param  __HANDLE__ specifies the UART Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__)  __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_NEF)\r\n\r\n/** @brief  Clear the UART ORE pending flag.\r\n  * @param  __HANDLE__ specifies the UART Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__)   __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_OREF)\r\n\r\n/** @brief  Clear the UART IDLE pending flag.\r\n  * @param  __HANDLE__ specifies the UART Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_IDLEF)\r\n\r\n/** @brief  Checks whether the specified UART flag is set or not.\r\n  * @param  __HANDLE__ specifies the UART Handle.\r\n  * @param  __FLAG__ specifies the flag to check.\r\n  *        This parameter can be one of the following values:\r\n  *            @arg UART_FLAG_REACK: Receive enable acknowledge flag\r\n  *            @arg UART_FLAG_TEACK: Transmit enable acknowledge flag\r\n  *            @arg UART_FLAG_WUF:   Wake up from stop mode flag\r\n  *            @arg UART_FLAG_RWU:   Receiver wake up flag (is the UART in mute mode)\r\n  *            @arg UART_FLAG_SBKF:  Send Break flag\r\n  *            @arg UART_FLAG_CMF:   Character match flag\r\n  *            @arg UART_FLAG_BUSY:  Busy flag\r\n  *            @arg UART_FLAG_ABRF:  Auto Baud rate detection flag\r\n  *            @arg UART_FLAG_ABRE:  Auto Baud rate detection error flag\r\n  *            @arg UART_FLAG_EOBF:  End of block flag\r\n  *            @arg UART_FLAG_RTOF:  Receiver timeout flag\r\n  *            @arg UART_FLAG_CTS:   CTS Change flag (not available for UART4 and UART5)\r\n  *            @arg UART_FLAG_LBD:   LIN Break detection flag\r\n  *            @arg UART_FLAG_TXE:   Transmit data register empty flag\r\n  *            @arg UART_FLAG_TC:    Transmission Complete flag\r\n  *            @arg UART_FLAG_RXNE:  Receive data register not empty flag\r\n  *            @arg UART_FLAG_IDLE:  Idle Line detection flag\r\n  *            @arg UART_FLAG_ORE:   OverRun Error flag\r\n  *            @arg UART_FLAG_NE:    Noise Error flag\r\n  *            @arg UART_FLAG_FE:    Framing Error flag\r\n  *            @arg UART_FLAG_PE:    Parity Error flag\r\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))\r\n\r\n/** @brief  Enables the specified UART interrupt.\r\n  * @param  __HANDLE__ specifies the UART Handle.\r\n  * @param  __INTERRUPT__ specifies the UART interrupt source to enable.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg UART_IT_WUF:  Wakeup from stop mode interrupt\r\n  *            @arg UART_IT_CM:   Character match interrupt\r\n  *            @arg UART_IT_CTS:  CTS change interrupt\r\n  *            @arg UART_IT_LBD:  LIN Break detection interrupt\r\n  *            @arg UART_IT_TXE:  Transmit Data Register empty interrupt\r\n  *            @arg UART_IT_TC:   Transmission complete interrupt\r\n  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt\r\n  *            @arg UART_IT_IDLE: Idle line detection interrupt\r\n  *            @arg UART_IT_PE:   Parity Error interrupt\r\n  *            @arg UART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)\r\n  * @retval None\r\n  */\r\n#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \\\r\n                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \\\r\n                                                           ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))\r\n\r\n\r\n/** @brief  Disables the specified UART interrupt.\r\n  * @param  __HANDLE__ specifies the UART Handle.\r\n  * @param  __INTERRUPT__ specifies the UART interrupt source to disable.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg UART_IT_CM:   Character match interrupt\r\n  *            @arg UART_IT_CTS:  CTS change interrupt\r\n  *            @arg UART_IT_LBD:  LIN Break detection interrupt\r\n  *            @arg UART_IT_TXE:  Transmit Data Register empty interrupt\r\n  *            @arg UART_IT_TC:   Transmission complete interrupt\r\n  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt\r\n  *            @arg UART_IT_IDLE: Idle line detection interrupt\r\n  *            @arg UART_IT_PE:   Parity Error interrupt\r\n  *            @arg UART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)\r\n  * @retval None\r\n  */\r\n#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \\\r\n                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \\\r\n                                                           ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))\r\n\r\n/** @brief  Checks whether the specified UART interrupt has occurred or not.\r\n  * @param  __HANDLE__ specifies the UART Handle.\r\n  * @param  __IT__ specifies the UART interrupt to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg UART_IT_CM:   Character match interrupt\r\n  *            @arg UART_IT_CTS:  CTS change interrupt (not available for UART4 and UART5)\r\n  *            @arg UART_IT_LBD:  LIN Break detection interrupt\r\n  *            @arg UART_IT_TXE:  Transmit Data Register empty interrupt\r\n  *            @arg UART_IT_TC:   Transmission complete interrupt\r\n  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt\r\n  *            @arg UART_IT_IDLE: Idle line detection interrupt\r\n  *            @arg UART_IT_ORE:  OverRun Error interrupt\r\n  *            @arg UART_IT_NE:   Noise Error interrupt\r\n  *            @arg UART_IT_FE:   Framing Error interrupt\r\n  *            @arg UART_IT_PE:   Parity Error interrupt\r\n  * @retval The new state of __IT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))\r\n\r\n/** @brief  Checks whether the specified UART interrupt source is enabled.\r\n  * @param  __HANDLE__ specifies the UART Handle.\r\n  * @param  __IT__ specifies the UART interrupt source to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)\r\n  *            @arg UART_IT_LBD: LIN Break detection interrupt\r\n  *            @arg UART_IT_TXE: Transmit Data Register empty interrupt\r\n  *            @arg UART_IT_TC:  Transmission complete interrupt\r\n  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt\r\n  *            @arg UART_IT_IDLE: Idle line detection interrupt\r\n  *            @arg UART_IT_ORE: OverRun Error interrupt\r\n  *            @arg UART_IT_NE: Noise Error interrupt\r\n  *            @arg UART_IT_FE: Framing Error interrupt\r\n  *            @arg UART_IT_PE: Parity Error interrupt\r\n  * @retval The new state of __IT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \\\r\n                                                       (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & UART_IT_MASK)))\r\n\r\n/** @brief  Set a specific UART request flag.\r\n  * @param  __HANDLE__ specifies the UART Handle.\r\n  * @param  __REQ__ specifies the request flag to set\r\n  *          This parameter can be one of the following values:\r\n  *            @arg UART_AUTOBAUD_REQUEST: Auto-Baud Rate Request\r\n  *            @arg UART_SENDBREAK_REQUEST: Send Break Request\r\n  *            @arg UART_MUTE_MODE_REQUEST: Mute Mode Request\r\n  *            @arg UART_RXDATA_FLUSH_REQUEST: Receive Data flush Request\r\n  *            @arg UART_TXDATA_FLUSH_REQUEST: Transmit data flush Request\r\n  * @retval None\r\n  */\r\n#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))\r\n\r\n/** @brief  Enables the UART one bit sample method\r\n  * @param  __HANDLE__ specifies the UART Handle.  \r\n  * @retval None\r\n  */     \r\n#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)\r\n\r\n/** @brief  Disables the UART one bit sample method\r\n  * @param  __HANDLE__ specifies the UART Handle.  \r\n  * @retval None\r\n  */      \r\n#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))\r\n\r\n/** @brief  Enable UART\r\n  * @param  __HANDLE__ specifies the UART Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_UART_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)\r\n\r\n/** @brief  Disable UART\r\n  * @param  __HANDLE__ specifies the UART Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_UART_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)\r\n\r\n/** @brief  Enable CTS flow control \r\n  *         This macro allows to enable CTS hardware flow control for a given UART instance, \r\n  *         without need to call HAL_UART_Init() function.\r\n  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\r\n  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need\r\n  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\r\n  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )\r\n  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))\r\n  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).                                                                                                                  \r\n  * @param  __HANDLE__ specifies the UART Handle.\r\n  *         The Handle Instance can be USART1, USART2 or LPUART.\r\n  * @retval None\r\n  */\r\n#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)        \\\r\n  do{                                                      \\\r\n    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \\\r\n    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \\\r\n  } while(0)\r\n\r\n/** @brief  Disable CTS flow control \r\n  *         This macro allows to disable CTS hardware flow control for a given UART instance, \r\n  *         without need to call HAL_UART_Init() function.\r\n  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\r\n  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need\r\n  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\r\n  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )\r\n  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))\r\n  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). \r\n  * @param  __HANDLE__ specifies the UART Handle.\r\n  *         The Handle Instance can be USART1, USART2 or LPUART.\r\n  * @retval None\r\n  */\r\n#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)        \\\r\n  do{                                                       \\\r\n    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \\\r\n    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \\\r\n  } while(0)\r\n\r\n/** @brief  Enable RTS flow control \r\n  *         This macro allows to enable RTS hardware flow control for a given UART instance, \r\n  *         without need to call HAL_UART_Init() function.\r\n  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\r\n  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need\r\n  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\r\n  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )\r\n  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))\r\n  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). \r\n  * @param  __HANDLE__ specifies the UART Handle.\r\n  *         The Handle Instance can be USART1, USART2 or LPUART.\r\n  * @retval None\r\n  */\r\n#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)       \\\r\n  do{                                                     \\\r\n    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \\\r\n    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \\\r\n  } while(0)\r\n\r\n/** @brief  Disable RTS flow control \r\n  *         This macro allows to disable RTS hardware flow control for a given UART instance, \r\n  *         without need to call HAL_UART_Init() function.\r\n  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\r\n  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need\r\n  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\r\n  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )\r\n  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))\r\n  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). \r\n  * @param  __HANDLE__ specifies the UART Handle.\r\n  *         The Handle Instance can be USART1, USART2 or LPUART.\r\n  * @retval None\r\n  */\r\n#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)       \\\r\n  do{                                                      \\\r\n    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\\\r\n    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \\\r\n  } while(0)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros --------------------------------------------------------*/\r\n/** @defgroup UART_Private_Macros   UART Private Macros\r\n  * @{\r\n  */\r\n/** @brief  BRR division operation to set BRR register with LPUART\r\n  * @param  _PCLK_ LPUART clock\r\n  * @param  _BAUD_ Baud rate set by the user\r\n  * @retval Division result\r\n  */\r\n#define UART_DIV_LPUART(_PCLK_, _BAUD_)                ((((_PCLK_)*256)+((_BAUD_)/2))/((_BAUD_)))\r\n\r\n/** @brief  BRR division operation to set BRR register in 8-bit oversampling mode\r\n  * @param  _PCLK_ UART clock\r\n  * @param  _BAUD_ Baud rate set by the user\r\n  * @retval Division result\r\n  */\r\n#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_)             ((((_PCLK_)*2)+((_BAUD_)/2))/((_BAUD_)))\r\n\r\n/** @brief  BRR division operation to set BRR register in 16-bit oversampling mode\r\n  * @param  _PCLK_ UART clock\r\n  * @param  _BAUD_ Baud rate set by the user\r\n  * @retval Division result\r\n  */\r\n#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_)             ((((_PCLK_))+((_BAUD_)/2))/((_BAUD_)))\r\n\r\n/** @brief  Check UART Baud rate\r\n  * @param  BAUDRATE Baudrate specified by the user\r\n  *         The maximum Baud Rate is derived from the maximum clock on F7 (i.e. 216 MHz)\r\n  *         divided by the smallest oversampling used on the USART (i.e. 8)\r\n  * @retval Test result (TRUE or FALSE).\r\n  */\r\n#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 9000001)\r\n\r\n/** @brief  Check UART assertion time\r\n  * @param  TIME 5-bit value assertion time\r\n  * @retval Test result (TRUE or FALSE).\r\n  */\r\n#define IS_UART_ASSERTIONTIME(TIME)    ((TIME) <= 0x1F)\r\n\r\n/** @brief  Check UART deassertion time\r\n  * @param  TIME 5-bit value deassertion time\r\n  * @retval Test result (TRUE or FALSE).\r\n  */\r\n#define IS_UART_DEASSERTIONTIME(TIME) ((TIME) <= 0x1F)\r\n\r\n#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \\\r\n                                    ((STOPBITS) == UART_STOPBITS_2))\r\n\r\n#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \\\r\n                                ((PARITY) == UART_PARITY_EVEN) || \\\r\n                                ((PARITY) == UART_PARITY_ODD))\r\n\r\n#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\\\r\n                              (((CONTROL) == UART_HWCONTROL_NONE) || \\\r\n                               ((CONTROL) == UART_HWCONTROL_RTS) || \\\r\n                               ((CONTROL) == UART_HWCONTROL_CTS) || \\\r\n                               ((CONTROL) == UART_HWCONTROL_RTS_CTS))\r\n\r\n#define IS_UART_MODE(MODE) ((((MODE) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((MODE) != (uint32_t)0x00))\r\n\r\n#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \\\r\n                              ((STATE) == UART_STATE_ENABLE))\r\n\r\n#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \\\r\n                                        ((SAMPLING) == UART_OVERSAMPLING_8))\r\n\r\n#define IS_UART_ONE_BIT_SAMPLE(ONEBIT) (((ONEBIT) == UART_ONE_BIT_SAMPLE_DISABLE) || \\\r\n                                        ((ONEBIT) == UART_ONE_BIT_SAMPLE_ENABLE))\r\n\r\n#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(MODE)  (((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \\\r\n                                                    ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \\\r\n                                                    ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \\\r\n                                                    ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))\r\n\r\n#define IS_UART_RECEIVER_TIMEOUT(TIMEOUT) (((TIMEOUT) == UART_RECEIVER_TIMEOUT_DISABLE) || \\\r\n                                           ((TIMEOUT) == UART_RECEIVER_TIMEOUT_ENABLE))\r\n\r\n#define IS_UART_LIN(LIN)            (((LIN) == UART_LIN_DISABLE) || \\\r\n                                     ((LIN) == UART_LIN_ENABLE))\r\n\r\n#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \\\r\n                                      ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))\r\n\r\n#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \\\r\n                                                 ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))\r\n\r\n#define IS_UART_DMA_TX(DMATX)         (((DMATX) == UART_DMA_TX_DISABLE) || \\\r\n                                       ((DMATX) == UART_DMA_TX_ENABLE))\r\n\r\n#define IS_UART_DMA_RX(DMARX)         (((DMARX) == UART_DMA_RX_DISABLE) || \\\r\n                                       ((DMARX) == UART_DMA_RX_ENABLE))\r\n\r\n#define IS_UART_HALF_DUPLEX(HDSEL)         (((HDSEL) == UART_HALF_DUPLEX_DISABLE) || \\\r\n                                            ((HDSEL) == UART_HALF_DUPLEX_ENABLE))\r\n\r\n#define IS_UART_REQUEST_PARAMETER(PARAM) (((PARAM) == UART_AUTOBAUD_REQUEST) || \\\r\n                                          ((PARAM) == UART_SENDBREAK_REQUEST) || \\\r\n                                          ((PARAM) == UART_MUTE_MODE_REQUEST) || \\\r\n                                          ((PARAM) == UART_RXDATA_FLUSH_REQUEST) || \\\r\n                                          ((PARAM) == UART_TXDATA_FLUSH_REQUEST))\r\n\r\n#define IS_UART_ADVFEATURE_INIT(INIT)           ((INIT) <= (UART_ADVFEATURE_NO_INIT | \\\r\n                                                            UART_ADVFEATURE_TXINVERT_INIT | \\\r\n                                                            UART_ADVFEATURE_RXINVERT_INIT | \\\r\n                                                            UART_ADVFEATURE_DATAINVERT_INIT | \\\r\n                                                            UART_ADVFEATURE_SWAP_INIT | \\\r\n                                                            UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \\\r\n                                                            UART_ADVFEATURE_DMADISABLEONERROR_INIT   | \\\r\n                                                            UART_ADVFEATURE_AUTOBAUDRATE_INIT | \\\r\n                                                            UART_ADVFEATURE_MSBFIRST_INIT))\r\n\r\n#define IS_UART_ADVFEATURE_TXINV(TXINV) (((TXINV) == UART_ADVFEATURE_TXINV_DISABLE) || \\\r\n                                         ((TXINV) == UART_ADVFEATURE_TXINV_ENABLE))\r\n\r\n#define IS_UART_ADVFEATURE_RXINV(RXINV) (((RXINV) == UART_ADVFEATURE_RXINV_DISABLE) || \\\r\n                                         ((RXINV) == UART_ADVFEATURE_RXINV_ENABLE))\r\n\r\n#define IS_UART_ADVFEATURE_DATAINV(DATAINV) (((DATAINV) == UART_ADVFEATURE_DATAINV_DISABLE) || \\\r\n                                             ((DATAINV) == UART_ADVFEATURE_DATAINV_ENABLE))\r\n\r\n#define IS_UART_ADVFEATURE_SWAP(SWAP) (((SWAP) == UART_ADVFEATURE_SWAP_DISABLE) || \\\r\n                                       ((SWAP) == UART_ADVFEATURE_SWAP_ENABLE))\r\n\r\n#define IS_UART_OVERRUN(OVERRUN)         (((OVERRUN) == UART_ADVFEATURE_OVERRUN_ENABLE) || \\\r\n                                          ((OVERRUN) == UART_ADVFEATURE_OVERRUN_DISABLE))\r\n\r\n#define IS_UART_ADVFEATURE_AUTOBAUDRATE(AUTOBAUDRATE)  (((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \\\r\n                                                        ((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))\r\n\r\n#define IS_UART_ADVFEATURE_DMAONRXERROR(DMA)      (((DMA) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \\\r\n                                                   ((DMA) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))\r\n\r\n#define IS_UART_ADVFEATURE_MSBFIRST(MSBFIRST) (((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \\\r\n                                               ((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_ENABLE))\r\n\r\n#define IS_UART_MUTE_MODE(MUTE)           (((MUTE) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \\\r\n                                           ((MUTE) == UART_ADVFEATURE_MUTEMODE_ENABLE))\r\n\r\n#define IS_UART_DE_POLARITY(POLARITY)    (((POLARITY) == UART_DE_POLARITY_HIGH) || \\\r\n                                          ((POLARITY) == UART_DE_POLARITY_LOW))\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Include UART HAL Extension module */\r\n#include \"stm32f7xx_hal_uart_ex.h\"\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup UART_Exported_Functions UART Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions\r\n  * @{\r\n  */\r\n\r\n/* Initialization and de-initialization functions  ****************************/\r\nHAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);\r\nHAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);\r\nHAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);\r\nHAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);\r\nHAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime);\r\nHAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);\r\nvoid HAL_UART_MspInit(UART_HandleTypeDef *huart);\r\nvoid HAL_UART_MspDeInit(UART_HandleTypeDef *huart);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup UART_Exported_Functions_Group2 IO operation functions\r\n  * @{\r\n  */\r\n\r\n/* IO operation functions *****************************************************/\r\nHAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);\r\nHAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);\r\nHAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);\r\n\r\nvoid HAL_UART_IRQHandler(UART_HandleTypeDef *huart);\r\nvoid HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);\r\nvoid HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);\r\nvoid HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);\r\nvoid HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);\r\nvoid HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions\r\n  * @{\r\n  */\r\n\r\n/* Peripheral Control functions  ************************************************/\r\nHAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);\r\nHAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);\r\nHAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);\r\nHAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);\r\nvoid HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);\r\nHAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);\r\nHAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions\r\n  * @{\r\n  */\r\n\r\n/* Peripheral State and Errors functions  **************************************************/\r\nHAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);\r\nuint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions -----------------------------------------------------------*/\r\n/** @addtogroup UART_Private_Functions UART Private Functions\r\n  * @{\r\n  */\r\n\r\nHAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);\r\nHAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);\r\nHAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);\r\nvoid UART_AdvFeatureConfig(UART_HandleTypeDef *huart);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_UART_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_uart_ex.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of UART HAL Extension module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************  \r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_UART_EX_H\r\n#define __STM32F7xx_HAL_UART_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup UARTEx\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup UARTEx_Word_Length UARTEx Word Length\r\n  * @{\r\n  */\r\n#define UART_WORDLENGTH_7B                  ((uint32_t)USART_CR1_M_1)\r\n#define UART_WORDLENGTH_8B                  ((uint32_t)0x0000U)\r\n#define UART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M_0)\r\n#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \\\r\n                                         ((__LENGTH__) == UART_WORDLENGTH_8B) || \\\r\n                                         ((__LENGTH__) == UART_WORDLENGTH_9B))\r\n#define IS_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B))\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t \r\n/**\r\n  * @}\r\n  */\r\n\r\n  \r\n/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length\r\n  * @{\r\n  */\r\n#define UART_ADDRESS_DETECT_4B                ((uint32_t)0x00000000U)\r\n#define UART_ADDRESS_DETECT_7B                ((uint32_t)USART_CR2_ADDM7)\r\n#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \\\r\n                                                   ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))\r\n/**\r\n  * @}\r\n  */  \r\n\r\n  \r\n/**\r\n  * @}\r\n  */  \r\n  \r\n/* Exported macro ------------------------------------------------------------*/\r\n\r\n/** @defgroup UARTEx_Exported_Macros UARTEx Exported Macros\r\n  * @{\r\n  */\r\n           \r\n/** @brief  Reports the UART clock source.\r\n  * @param  __HANDLE__ specifies the UART Handle\r\n  * @param  __CLOCKSOURCE__ output variable   \r\n  * @retval UART clocking source, written in __CLOCKSOURCE__.\r\n  */\r\n#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \\\r\n  do {                                                        \\\r\n    if((__HANDLE__)->Instance == USART1)                      \\\r\n    {                                                         \\\r\n       switch(__HAL_RCC_GET_USART1_SOURCE())                  \\\r\n       {                                                      \\\r\n        case RCC_USART1CLKSOURCE_PCLK2:                       \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \\\r\n          break;                                              \\\r\n        case RCC_USART1CLKSOURCE_HSI:                         \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\\r\n          break;                                              \\\r\n        case RCC_USART1CLKSOURCE_SYSCLK:                      \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                              \\\r\n        case RCC_USART1CLKSOURCE_LSE:                         \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\\r\n          break;                                              \\\r\n        default:                                              \\\r\n          break;                                              \\\r\n       }                                                      \\\r\n    }                                                         \\\r\n    else if((__HANDLE__)->Instance == USART2)                 \\\r\n    {                                                         \\\r\n       switch(__HAL_RCC_GET_USART2_SOURCE())                  \\\r\n       {                                                      \\\r\n        case RCC_USART2CLKSOURCE_PCLK1:                       \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\\r\n          break;                                              \\\r\n        case RCC_USART2CLKSOURCE_HSI:                         \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\\r\n          break;                                              \\\r\n        case RCC_USART2CLKSOURCE_SYSCLK:                      \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                              \\\r\n        case RCC_USART2CLKSOURCE_LSE:                         \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\\r\n          break;                                              \\\r\n        default:                                              \\\r\n          break;                                              \\\r\n       }                                                      \\\r\n    }                                                         \\\r\n    else if((__HANDLE__)->Instance == USART3)                 \\\r\n    {                                                         \\\r\n       switch(__HAL_RCC_GET_USART3_SOURCE())                  \\\r\n       {                                                      \\\r\n        case RCC_USART3CLKSOURCE_PCLK1:                       \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\\r\n          break;                                              \\\r\n        case RCC_USART3CLKSOURCE_HSI:                         \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\\r\n          break;                                              \\\r\n        case RCC_USART3CLKSOURCE_SYSCLK:                      \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                              \\\r\n        case RCC_USART3CLKSOURCE_LSE:                         \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\\r\n          break;                                              \\\r\n        default:                                              \\\r\n          break;                                              \\\r\n       }                                                      \\\r\n    }                                                         \\\r\n    else if((__HANDLE__)->Instance == UART4)                  \\\r\n    {                                                         \\\r\n       switch(__HAL_RCC_GET_UART4_SOURCE())                   \\\r\n       {                                                      \\\r\n        case RCC_UART4CLKSOURCE_PCLK1:                        \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\\r\n          break;                                              \\\r\n        case RCC_UART4CLKSOURCE_HSI:                          \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\\r\n          break;                                              \\\r\n        case RCC_UART4CLKSOURCE_SYSCLK:                       \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                              \\\r\n        case RCC_UART4CLKSOURCE_LSE:                          \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\\r\n          break;                                              \\\r\n        default:                                              \\\r\n          break;                                              \\\r\n       }                                                      \\\r\n    }                                                         \\\r\n    else if ((__HANDLE__)->Instance == UART5)                 \\\r\n    {                                                         \\\r\n       switch(__HAL_RCC_GET_UART5_SOURCE())                   \\\r\n       {                                                      \\\r\n        case RCC_UART5CLKSOURCE_PCLK1:                        \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\\r\n          break;                                              \\\r\n        case RCC_UART5CLKSOURCE_HSI:                          \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\\r\n          break;                                              \\\r\n        case RCC_UART5CLKSOURCE_SYSCLK:                       \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                              \\\r\n        case RCC_UART5CLKSOURCE_LSE:                          \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\\r\n          break;                                              \\\r\n        default:                                              \\\r\n          break;                                              \\\r\n       }                                                      \\\r\n    }                                                         \\\r\n    else if((__HANDLE__)->Instance == USART6)                 \\\r\n    {                                                         \\\r\n       switch(__HAL_RCC_GET_USART6_SOURCE())                  \\\r\n       {                                                      \\\r\n        case RCC_USART6CLKSOURCE_PCLK2:                       \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \\\r\n          break;                                              \\\r\n        case RCC_USART6CLKSOURCE_HSI:                         \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\\r\n          break;                                              \\\r\n        case RCC_USART6CLKSOURCE_SYSCLK:                      \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                              \\\r\n        case RCC_USART6CLKSOURCE_LSE:                         \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\\r\n          break;                                              \\\r\n        default:                                              \\\r\n          break;                                              \\\r\n       }                                                      \\\r\n    }                                                         \\\r\n    else if ((__HANDLE__)->Instance == UART7)                 \\\r\n    {                                                         \\\r\n       switch(__HAL_RCC_GET_UART7_SOURCE())                   \\\r\n       {                                                      \\\r\n        case RCC_UART7CLKSOURCE_PCLK1:                        \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\\r\n          break;                                              \\\r\n        case RCC_UART7CLKSOURCE_HSI:                          \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\\r\n          break;                                              \\\r\n        case RCC_UART7CLKSOURCE_SYSCLK:                       \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                              \\\r\n        case RCC_UART7CLKSOURCE_LSE:                          \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\\r\n          break;                                              \\\r\n        default:                                              \\\r\n          break;                                              \\\r\n       }                                                      \\\r\n    } \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n    else if ((__HANDLE__)->Instance == UART8)                 \\\r\n    {                                                         \\\r\n       switch(__HAL_RCC_GET_UART8_SOURCE())                   \\\r\n       {                                                      \\\r\n        case RCC_UART8CLKSOURCE_PCLK1:                        \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\\r\n          break;                                              \\\r\n        case RCC_UART8CLKSOURCE_HSI:                          \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\\r\n          break;                                              \\\r\n        case RCC_UART8CLKSOURCE_SYSCLK:                       \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                              \\\r\n        case RCC_UART8CLKSOURCE_LSE:                          \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\\r\n          break;                                              \\\r\n        default:                                              \\\r\n          break;                                              \\\r\n       }                                                      \\\r\n    } \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n  } while(0)\r\n\r\n/** @brief  Reports the UART mask to apply to retrieve the received data\r\n  *         according to the word length and to the parity bits activation.\r\n  *         If PCE = 1, the parity bit is not included in the data extracted\r\n  *         by the reception API().\r\n  *         This masking operation is not carried out in the case of\r\n  *         DMA transfers.        \r\n  * @param  __HANDLE__ specifies the UART Handle\r\n  * @retval mask to apply to UART RDR register value.\r\n  */\r\n#define UART_MASK_COMPUTATION(__HANDLE__)                       \\\r\n  do {                                                                \\\r\n  if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B)            \\\r\n  {                                                                   \\\r\n     if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x01FF ;                                 \\\r\n     }                                                                \\\r\n     else                                                             \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x00FF ;                                 \\\r\n     }                                                                \\\r\n  }                                                                   \\\r\n  else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B)       \\\r\n  {                                                                   \\\r\n     if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x00FF ;                                 \\\r\n     }                                                                \\\r\n     else                                                             \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x007F ;                                 \\\r\n     }                                                                \\\r\n  }                                                                   \\\r\n  else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B)       \\\r\n  {                                                                   \\\r\n     if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x007F ;                                 \\\r\n     }                                                                \\\r\n     else                                                             \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x003F ;                                 \\\r\n     }                                                                \\\r\n  }                                                                   \\\r\n} while(0)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @addtogroup UARTEx_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup UARTEx_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n\r\n/* Initialization and de-initialization functions  ****************************/\r\nHAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime);\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @addtogroup UARTEx_Exported_Functions_Group3\r\n  * @{\r\n  */\r\n\r\n/* Peripheral Control functions  **********************************************/\r\nHAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_UART_EX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_usart.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_usart.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of USART HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_USART_H\r\n#define __STM32F7xx_HAL_USART_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup USART\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup USART_Exported_Types USART Exported Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief USART Init Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t BaudRate;                  /*!< This member configures the Usart communication baud rate.\r\n                                           The baud rate is computed using the following formula:\r\n                                              Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate))) */\r\n\r\n  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.\r\n                                           This parameter can be a value of @ref USARTEx_Word_Length */\r\n\r\n  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.\r\n                                           This parameter can be a value of @ref USART_Stop_Bits */\r\n\r\n  uint32_t Parity;                   /*!< Specifies the parity mode.\r\n                                           This parameter can be a value of @ref USART_Parity\r\n                                           @note When parity is enabled, the computed parity is inserted\r\n                                                 at the MSB position of the transmitted data (9th bit when\r\n                                                 the word length is set to 9 data bits; 8th bit when the\r\n                                                 word length is set to 8 data bits). */\r\n\r\n  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.\r\n                                           This parameter can be a value of @ref USART_Mode */\r\n\r\n  uint32_t OverSampling;              /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).\r\n                                           This parameter can be a value of @ref USART_Over_Sampling */                                                                                        \r\n\r\n  uint32_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.\r\n                                           This parameter can be a value of @ref USART_Clock_Polarity */\r\n\r\n  uint32_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.\r\n                                           This parameter can be a value of @ref USART_Clock_Phase */\r\n\r\n  uint32_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted\r\n                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.\r\n                                           This parameter can be a value of @ref USART_Last_Bit */\r\n}USART_InitTypeDef;\r\n\r\n/**\r\n  * @brief HAL USART State structures definition\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_USART_STATE_RESET             = 0x00U,    /*!< Peripheral is not initialized   */\r\n  HAL_USART_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use */\r\n  HAL_USART_STATE_BUSY              = 0x02U,    /*!< an internal process is ongoing */\r\n  HAL_USART_STATE_BUSY_TX           = 0x12U,    /*!< Data Transmission process is ongoing */\r\n  HAL_USART_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing */\r\n  HAL_USART_STATE_BUSY_TX_RX        = 0x32U,    /*!< Data Transmission Reception process is ongoing */\r\n  HAL_USART_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state */\r\n  HAL_USART_STATE_ERROR             = 0x04U     /*!< Error */\r\n}HAL_USART_StateTypeDef;\r\n\r\n\r\n/**\r\n  * @brief  USART clock sources definitions\r\n  */\r\ntypedef enum\r\n{\r\n  USART_CLOCKSOURCE_PCLK1      = 0x00U,    /*!< PCLK1 clock source  */\r\n  USART_CLOCKSOURCE_PCLK2      = 0x01U,    /*!< PCLK2 clock source  */\r\n  USART_CLOCKSOURCE_HSI        = 0x02U,    /*!< HSI clock source    */\r\n  USART_CLOCKSOURCE_SYSCLK     = 0x04U,    /*!< SYSCLK clock source */\r\n  USART_CLOCKSOURCE_LSE        = 0x08U,    /*!< LSE clock source       */\r\n  USART_CLOCKSOURCE_UNDEFINED  = 0x10U     /*!< Undefined clock source */\r\n}USART_ClockSourceTypeDef;\r\n\r\n\r\n/**\r\n  * @brief  USART handle Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  USART_TypeDef                 *Instance;        /*!<  USART registers base address        */\r\n\r\n  USART_InitTypeDef             Init;             /*!< USART communication parameters      */\r\n\r\n  uint8_t                       *pTxBuffPtr;      /*!< Pointer to USART Tx transfer Buffer */\r\n\r\n  uint16_t                      TxXferSize;       /*!< USART Tx Transfer size              */\r\n\r\n  __IO uint16_t                 TxXferCount;      /*!< USART Tx Transfer Counter           */\r\n\r\n  uint8_t                       *pRxBuffPtr;      /*!< Pointer to USART Rx transfer Buffer */\r\n\r\n  uint16_t                      RxXferSize;       /*!< USART Rx Transfer size              */\r\n\r\n  __IO uint16_t                 RxXferCount;      /*!< USART Rx Transfer Counter           */\r\n\r\n  uint16_t                      Mask;             /*!< USART Rx RDR register mask          */\r\n\r\n  DMA_HandleTypeDef             *hdmatx;          /*!< USART Tx DMA Handle parameters      */\r\n\r\n  DMA_HandleTypeDef             *hdmarx;          /*!< USART Rx DMA Handle parameters      */\r\n\r\n  HAL_LockTypeDef               Lock;            /*!<  Locking object                      */\r\n\r\n  HAL_USART_StateTypeDef        State;           /*!< USART communication state           */\r\n\r\n  __IO uint32_t                 ErrorCode;       /*!< USART Error code                    */\r\n\r\n}USART_HandleTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup USART_Exported_Constants USART Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup USART_Error_Code USART Error Code\r\n  * @brief    USART Error Code \r\n  * @{\r\n  */ \r\n#define HAL_USART_ERROR_NONE         ((uint32_t)0x00000000U)   /*!< No error            */\r\n#define HAL_USART_ERROR_PE           ((uint32_t)0x00000001U)   /*!< Parity error        */\r\n#define HAL_USART_ERROR_NE           ((uint32_t)0x00000002U)   /*!< Noise error         */\r\n#define HAL_USART_ERROR_FE           ((uint32_t)0x00000004U)   /*!< Frame error         */\r\n#define HAL_USART_ERROR_ORE          ((uint32_t)0x00000008U)   /*!< Overrun error       */\r\n#define HAL_USART_ERROR_DMA          ((uint32_t)0x00000010U)   /*!< DMA transfer error  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USART_Stop_Bits  USART Number of Stop Bits\r\n  * @{\r\n  */\r\n#define USART_STOPBITS_1                     ((uint32_t)0x0000U)\r\n#define USART_STOPBITS_2                     ((uint32_t)USART_CR2_STOP_1)\r\n#define USART_STOPBITS_1_5                   ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USART_Parity    USART Parity\r\n  * @{\r\n  */\r\n#define USART_PARITY_NONE                   ((uint32_t)0x0000U)\r\n#define USART_PARITY_EVEN                   ((uint32_t)USART_CR1_PCE)\r\n#define USART_PARITY_ODD                    ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USART_Mode   USART Mode\r\n  * @{\r\n  */\r\n#define USART_MODE_RX                       ((uint32_t)USART_CR1_RE)\r\n#define USART_MODE_TX                       ((uint32_t)USART_CR1_TE)\r\n#define USART_MODE_TX_RX                    ((uint32_t)(USART_CR1_TE |USART_CR1_RE))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USART_Over_Sampling USART Over Sampling\r\n  * @{\r\n  */\r\n#define USART_OVERSAMPLING_16               ((uint32_t)0x0000U)\r\n#define USART_OVERSAMPLING_8                ((uint32_t)USART_CR1_OVER8)\r\n/**\r\n  * @}\r\n  */\r\n/** @defgroup USART_Clock  USART Clock\r\n  * @{\r\n  */\r\n#define USART_CLOCK_DISABLE                 ((uint32_t)0x0000U)\r\n#define USART_CLOCK_ENABLE                  ((uint32_t)USART_CR2_CLKEN)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USART_Clock_Polarity  USART Clock Polarity\r\n  * @{\r\n  */\r\n#define USART_POLARITY_LOW                  ((uint32_t)0x0000U)\r\n#define USART_POLARITY_HIGH                 ((uint32_t)USART_CR2_CPOL)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USART_Clock_Phase   USART Clock Phase\r\n  * @{\r\n  */\r\n#define USART_PHASE_1EDGE                   ((uint32_t)0x0000U)\r\n#define USART_PHASE_2EDGE                   ((uint32_t)USART_CR2_CPHA)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USART_Last_Bit  USART Last Bit\r\n  * @{\r\n  */\r\n#define USART_LASTBIT_DISABLE               ((uint32_t)0x0000U)\r\n#define USART_LASTBIT_ENABLE                ((uint32_t)USART_CR2_LBCL)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USART_Request_Parameters  USART Request Parameters\r\n  * @{\r\n  */\r\n#define USART_RXDATA_FLUSH_REQUEST        ((uint32_t)USART_RQR_RXFRQ)        /*!< Receive Data flush Request */ \r\n#define USART_TXDATA_FLUSH_REQUEST        ((uint32_t)USART_RQR_TXFRQ)        /*!< Transmit data flush Request */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USART_Flags      USART Flags\r\n  *        Elements values convention: 0xXXXX\r\n  *           - 0xXXXX  : Flag mask in the ISR register\r\n  * @{\r\n  */\r\n#define USART_FLAG_REACK                     ((uint32_t)0x00400000U)\r\n#define USART_FLAG_TEACK                     ((uint32_t)0x00200000U)  \r\n#define USART_FLAG_BUSY                      ((uint32_t)0x00010000U)\r\n#define USART_FLAG_CTS                       ((uint32_t)0x00000400U)\r\n#define USART_FLAG_CTSIF                     ((uint32_t)0x00000200U)\r\n#define USART_FLAG_LBDF                      ((uint32_t)0x00000100U)\r\n#define USART_FLAG_TXE                       ((uint32_t)0x00000080U)\r\n#define USART_FLAG_TC                        ((uint32_t)0x00000040U)\r\n#define USART_FLAG_RXNE                      ((uint32_t)0x00000020U)\r\n#define USART_FLAG_IDLE                      ((uint32_t)0x00000010U)\r\n#define USART_FLAG_ORE                       ((uint32_t)0x00000008U)\r\n#define USART_FLAG_NE                        ((uint32_t)0x00000004U)\r\n#define USART_FLAG_FE                        ((uint32_t)0x00000002U)\r\n#define USART_FLAG_PE                        ((uint32_t)0x00000001U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USART_Interrupt_definition USART Interrupts Definition\r\n  *        Elements values convention: 0000ZZZZ0XXYYYYYb\r\n  *           - YYYYY  : Interrupt source position in the XX register (5bits)\r\n  *           - XX  : Interrupt source register (2bits)\r\n  *                 - 01: CR1 register\r\n  *                 - 10: CR2 register\r\n  *                 - 11: CR3 register\r\n  *           - ZZZZ  : Flag position in the ISR register(4bits)\r\n  * @{\r\n  */\r\n\r\n#define USART_IT_PE                          ((uint16_t)0x0028U)\r\n#define USART_IT_TXE                         ((uint16_t)0x0727U)\r\n#define USART_IT_TC                          ((uint16_t)0x0626U)\r\n#define USART_IT_RXNE                        ((uint16_t)0x0525U)\r\n#define USART_IT_IDLE                        ((uint16_t)0x0424U)\r\n#define USART_IT_ERR                         ((uint16_t)0x0060U)\r\n\r\n#define USART_IT_ORE                         ((uint16_t)0x0300U)\r\n#define USART_IT_NE                          ((uint16_t)0x0200U)\r\n#define USART_IT_FE                          ((uint16_t)0x0100U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USART_IT_CLEAR_Flags    USART Interruption Clear Flags\r\n  * @{\r\n  */\r\n#define USART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag */\r\n#define USART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag */\r\n#define USART_CLEAR_NEF                       USART_ICR_NCF             /*!< Noise detected Clear Flag */\r\n#define USART_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag */\r\n#define USART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag */\r\n#define USART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag */\r\n#define USART_CLEAR_CTSF                      USART_ICR_CTSCF           /*!< CTS Interrupt Clear Flag */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macros -----------------------------------------------------------*/\r\n/** @defgroup USART_Exported_Macros USART Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief Reset USART handle state\r\n  * @param  __HANDLE__ USART handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)  ((__HANDLE__)->State = HAL_USART_STATE_RESET)\r\n\r\n/** @brief  Checks whether the specified USART flag is set or not.\r\n  * @param  __HANDLE__ specifies the USART Handle\r\n  * @param  __FLAG__ specifies the flag to check.\r\n  *        This parameter can be one of the following values:\r\n  *            @arg USART_FLAG_REACK: Receive enable acknowledge flag\r\n  *            @arg USART_FLAG_TEACK: Transmit enable acknowledge flag\r\n  *            @arg USART_FLAG_BUSY:  Busy flag\r\n  *            @arg USART_FLAG_CTS:   CTS Change flag\r\n  *            @arg USART_FLAG_TXE:   Transmit data register empty flag\r\n  *            @arg USART_FLAG_TC:    Transmission Complete flag\r\n  *            @arg USART_FLAG_RXNE:  Receive data register not empty flag\r\n  *            @arg USART_FLAG_IDLE:  Idle Line detection flag\r\n  *            @arg USART_FLAG_ORE:   OverRun Error flag\r\n  *            @arg USART_FLAG_NE:    Noise Error flag\r\n  *            @arg USART_FLAG_FE:    Framing Error flag\r\n  *            @arg USART_FLAG_PE:    Parity Error flag\r\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))\r\n\r\n\r\n/** @brief  Enables the specified USART interrupt.\r\n  * @param  __HANDLE__ specifies the USART Handle\r\n  * @param  __INTERRUPT__ specifies the USART interrupt source to enable.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg USART_IT_TXE:  Transmit Data Register empty interrupt\r\n  *            @arg USART_IT_TC:   Transmission complete interrupt\r\n  *            @arg USART_IT_RXNE: Receive Data register not empty interrupt\r\n  *            @arg USART_IT_IDLE: Idle line detection interrupt\r\n  *            @arg USART_IT_PE:   Parity Error interrupt\r\n  *            @arg USART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)\r\n  * @retval None\r\n  */\r\n#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \\\r\n                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \\\r\n                                                            ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))\r\n\r\n/** @brief  Disables the specified USART interrupt.\r\n  * @param  __HANDLE__ specifies the USART Handle.\r\n  * @param  __INTERRUPT__ specifies the USART interrupt source to disable.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg USART_IT_TXE:  Transmit Data Register empty interrupt\r\n  *            @arg USART_IT_TC:   Transmission complete interrupt\r\n  *            @arg USART_IT_RXNE: Receive Data register not empty interrupt\r\n  *            @arg USART_IT_IDLE: Idle line detection interrupt\r\n  *            @arg USART_IT_PE:   Parity Error interrupt\r\n  *            @arg USART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)\r\n  * @retval None\r\n  */\r\n#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \\\r\n                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \\\r\n                                                            ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))\r\n\r\n\r\n/** @brief  Checks whether the specified USART interrupt has occurred or not.\r\n  * @param  __HANDLE__ specifies the USART Handle\r\n  * @param  __IT__ specifies the USART interrupt source to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg USART_IT_TXE: Transmit Data Register empty interrupt\r\n  *            @arg USART_IT_TC:  Transmission complete interrupt\r\n  *            @arg USART_IT_RXNE: Receive Data register not empty interrupt\r\n  *            @arg USART_IT_IDLE: Idle line detection interrupt\r\n  *            @arg USART_IT_ORE: OverRun Error interrupt\r\n  *            @arg USART_IT_NE: Noise Error interrupt\r\n  *            @arg USART_IT_FE: Framing Error interrupt\r\n  *            @arg USART_IT_PE: Parity Error interrupt\r\n  * @retval The new state of __IT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))\r\n\r\n/** @brief  Checks whether the specified USART interrupt source is enabled.\r\n  * @param  __HANDLE__ specifies the USART Handle.\r\n  * @param  __IT__ specifies the USART interrupt source to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg USART_IT_TXE: Transmit Data Register empty interrupt\r\n  *            @arg USART_IT_TC:  Transmission complete interrupt\r\n  *            @arg USART_IT_RXNE: Receive Data register not empty interrupt\r\n  *            @arg USART_IT_IDLE: Idle line detection interrupt\r\n  *            @arg USART_IT_ORE: OverRun Error interrupt\r\n  *            @arg USART_IT_NE: Noise Error interrupt\r\n  *            @arg USART_IT_FE: Framing Error interrupt\r\n  *            @arg USART_IT_PE: Parity Error interrupt\r\n  * @retval The new state of __IT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \\\r\n                                                   (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << \\\r\n                                                   (((uint16_t)(__IT__)) & USART_IT_MASK)))\r\n\r\n\r\n/** @brief  Clears the specified USART ISR flag, in setting the proper ICR register flag.\r\n  * @param  __HANDLE__ specifies the USART Handle.\r\n  * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set\r\n  *                       to clear the corresponding interrupt\r\n  *          This parameter can be one of the following values:\r\n  *            @arg USART_CLEAR_PEF: Parity Error Clear Flag\r\n  *            @arg USART_CLEAR_FEF: Framing Error Clear Flag\r\n  *            @arg USART_CLEAR_NEF: Noise detected Clear Flag\r\n  *            @arg USART_CLEAR_OREF: OverRun Error Clear Flag\r\n  *            @arg USART_CLEAR_IDLEF: IDLE line detected Clear Flag\r\n  *            @arg USART_CLEAR_TCF: Transmission Complete Clear Flag\r\n  *            @arg USART_CLEAR_CTSF: CTS Interrupt Clear Flag\r\n  * @retval None\r\n  */\r\n#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))\r\n\r\n/** @brief  Set a specific USART request flag.\r\n  * @param  __HANDLE__ specifies the USART Handle.\r\n  * @param  __REQ__ specifies the request flag to set\r\n  *          This parameter can be one of the following values:\r\n  *            @arg USART_RXDATA_FLUSH_REQUEST: Receive Data flush Request\r\n  *            @arg USART_TXDATA_FLUSH_REQUEST: Transmit data flush Request\r\n  *\r\n  * @retval None\r\n  */\r\n#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) \r\n\r\n/** @brief  Enable USART\r\n  * @param  __HANDLE__ specifies the USART Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_USART_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)\r\n\r\n/** @brief  Disable USART\r\n  * @param  __HANDLE__ specifies the USART Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_USART_DISABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Include UART HAL Extension module */\r\n#include \"stm32f7xx_hal_usart_ex.h\"\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup USART_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup USART_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n/* Initialization/de-initialization functions  **********************************/\r\nHAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);\r\nHAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);\r\nvoid HAL_USART_MspInit(USART_HandleTypeDef *husart);\r\nvoid HAL_USART_MspDeInit(USART_HandleTypeDef *husart);\r\nHAL_StatusTypeDef HAL_USART_CheckIdleState(USART_HandleTypeDef *husart);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup USART_Exported_Functions_Group2\r\n  * @{\r\n  */\r\n/* IO operation functions *******************************************************/\r\nHAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,  uint16_t Size);\r\nHAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);\r\nHAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);\r\nHAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);\r\nvoid HAL_USART_IRQHandler(USART_HandleTypeDef *husart);\r\nvoid HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);\r\nvoid HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);\r\nvoid HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);\r\nvoid HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);\r\nvoid HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);\r\nvoid HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @addtogroup USART_Exported_Functions_Group3\r\n  * @{\r\n  */\r\n/* Peripheral State functions  ************************************************/\r\nHAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);\r\nuint32_t               HAL_USART_GetError(USART_HandleTypeDef *husart);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup USART_Private_Constants USART Private Constants\r\n  * @{\r\n  */\r\n/** @brief USART interruptions flag mask\r\n  * \r\n  */ \r\n#define USART_IT_MASK                             ((uint16_t)0x001FU)\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup USART_Private_Macros USART Private Macros\r\n  * @{\r\n  */\r\n/** @brief  Reports the USART clock source.\r\n  * @param  __HANDLE__ specifies the USART Handle\r\n  * @param  __CLOCKSOURCE__  output variable\r\n  * @retval the USART clocking source, written in __CLOCKSOURCE__.\r\n  */\r\n#define USART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)\\\r\n  do {                                                         \\\r\n    if((__HANDLE__)->Instance == USART1)                       \\\r\n    {                                                          \\\r\n       switch(__HAL_RCC_GET_USART1_SOURCE())                   \\\r\n       {                                                       \\\r\n        case RCC_USART1CLKSOURCE_PCLK2:                        \\\r\n          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2;         \\\r\n          break;                                               \\\r\n        case RCC_USART1CLKSOURCE_HSI:                          \\\r\n          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \\\r\n          break;                                               \\\r\n        case RCC_USART1CLKSOURCE_SYSCLK:                       \\\r\n          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                               \\\r\n        case RCC_USART1CLKSOURCE_LSE:                          \\\r\n          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \\\r\n          break;                                               \\\r\n        default:                                               \\\r\n          break;                                               \\\r\n       }                                                       \\\r\n    }                                                          \\\r\n    else if((__HANDLE__)->Instance == USART2)                  \\\r\n    {                                                          \\\r\n       switch(__HAL_RCC_GET_USART2_SOURCE())                   \\\r\n       {                                                       \\\r\n        case RCC_USART2CLKSOURCE_PCLK1:                        \\\r\n          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;         \\\r\n          break;                                               \\\r\n        case RCC_USART2CLKSOURCE_HSI:                          \\\r\n          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \\\r\n          break;                                               \\\r\n        case RCC_USART2CLKSOURCE_SYSCLK:                       \\\r\n          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                               \\\r\n        case RCC_USART2CLKSOURCE_LSE:                          \\\r\n          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \\\r\n          break;                                               \\\r\n        default:                                               \\\r\n          break;                                               \\\r\n       }                                                       \\\r\n    }                                                          \\\r\n    else if((__HANDLE__)->Instance == USART3)                  \\\r\n    {                                                          \\\r\n       switch(__HAL_RCC_GET_USART3_SOURCE())                   \\\r\n       {                                                       \\\r\n        case RCC_USART3CLKSOURCE_PCLK1:                        \\\r\n          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;         \\\r\n          break;                                               \\\r\n        case RCC_USART3CLKSOURCE_HSI:                          \\\r\n          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \\\r\n          break;                                               \\\r\n        case RCC_USART3CLKSOURCE_SYSCLK:                       \\\r\n          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                               \\\r\n        case RCC_USART3CLKSOURCE_LSE:                          \\\r\n          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \\\r\n          break;                                               \\\r\n        default:                                               \\\r\n          break;                                               \\\r\n       }                                                       \\\r\n    }                                                          \\\r\n    else if((__HANDLE__)->Instance == USART6)                  \\\r\n    {                                                          \\\r\n       switch(__HAL_RCC_GET_USART6_SOURCE())                   \\\r\n       {                                                       \\\r\n        case RCC_USART6CLKSOURCE_PCLK2:                        \\\r\n          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2;         \\\r\n          break;                                               \\\r\n        case RCC_USART6CLKSOURCE_HSI:                          \\\r\n          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \\\r\n          break;                                               \\\r\n        case RCC_USART6CLKSOURCE_SYSCLK:                       \\\r\n          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                               \\\r\n        case RCC_USART6CLKSOURCE_LSE:                          \\\r\n          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \\\r\n          break;                                               \\\r\n        default:                                               \\\r\n          break;                                               \\\r\n       }                                                       \\\r\n    }                                                          \\\r\n } while(0)\r\n  \r\n\r\n#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_1) || \\\r\n                                         ((__STOPBITS__) == USART_STOPBITS_1_5) || \\\r\n                                         ((__STOPBITS__) == USART_STOPBITS_2))\r\n#define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \\\r\n                                     ((__PARITY__) == USART_PARITY_EVEN) || \\\r\n                                     ((__PARITY__) == USART_PARITY_ODD))\r\n#define IS_USART_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFFFFFF3U) == 0x00U) && ((__MODE__) != (uint32_t)0x00U))\r\n#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \\\r\n                                             ((__SAMPLING__) == USART_OVERSAMPLING_8))\r\n#define IS_USART_CLOCK(__CLOCK__)     (((__CLOCK__)== USART_CLOCK_DISABLE) || \\\r\n                                       ((__CLOCK__)== USART_CLOCK_ENABLE))\r\n#define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))\r\n#define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))\r\n#define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \\\r\n                                       ((__LASTBIT__) == USART_LASTBIT_ENABLE))\r\n#define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \\\r\n                                               ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))   \r\n#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup USART_Private_Functions USART Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_USART_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_usart_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_usart_ex.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of USART HAL Extension module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_USART_EX_H\r\n#define __STM32F7xx_HAL_USART_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup USARTEx\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup USARTEx_Word_Length USARTEx Word Length\r\n  * @{\r\n  */\r\n#define USART_WORDLENGTH_7B                  ((uint32_t)USART_CR1_M_1)\r\n#define USART_WORDLENGTH_8B                  ((uint32_t)0x00000000U)\r\n#define USART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M_0)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup USARTEx_Private_Macros USARTEx Private Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief  Computes the USART mask to apply to retrieve the received data\r\n  *         according to the word length and to the parity bits activation.\r\n  *         If PCE = 1, the parity bit is not included in the data extracted\r\n  *         by the reception API().\r\n  *         This masking operation is not carried out in the case of\r\n  *         DMA transfers.\r\n  * @param  __HANDLE__ specifies the USART Handle\r\n  * @retval none\r\n  */\r\n#define __HAL_USART_MASK_COMPUTATION(__HANDLE__)                      \\\r\n  do {                                                                \\\r\n  if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B)           \\\r\n  {                                                                   \\\r\n     if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)              \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x01FF ;                                 \\\r\n     }                                                                \\\r\n     else                                                             \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x00FF ;                                 \\\r\n     }                                                                \\\r\n  }                                                                   \\\r\n  else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B)      \\\r\n  {                                                                   \\\r\n     if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)              \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x00FF ;                                 \\\r\n     }                                                                \\\r\n     else                                                             \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x007F ;                                 \\\r\n     }                                                                \\\r\n  }                                                                   \\\r\n  else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B)      \\\r\n  {                                                                   \\\r\n     if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)              \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x007F ;                                 \\\r\n     }                                                                \\\r\n     else                                                             \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x003F ;                                 \\\r\n     }                                                                \\\r\n  }                                                                   \\\r\n} while(0)\r\n\r\n#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \\\r\n                                          ((__LENGTH__) == USART_WORDLENGTH_8B) || \\\r\n                                          ((__LENGTH__) == USART_WORDLENGTH_9B))                                 \r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/* Initialization/de-initialization methods  **********************************/\r\n/* IO operation methods *******************************************************/\r\n/* Peripheral Control methods  ************************************************/\r\n/* Peripheral State methods  **************************************************/\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_USART_EX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_wwdg.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_wwdg.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of WWDG HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_WWDG_H\r\n#define __STM32F7xx_HAL_WWDG_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup WWDG\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n\r\n/** @defgroup WWDG_Exported_Types WWDG Exported Types\r\n  * @{\r\n  */\r\n\r\n/** \r\n  * @brief  WWDG Init structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t Prescaler;     /*!< Specifies the prescaler value of the WWDG.\r\n                               This parameter can be a value of @ref WWDG_Prescaler */\r\n\r\n  uint32_t Window;        /*!< Specifies the WWDG window value to be compared to the downcounter.\r\n                               This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */\r\n\r\n  uint32_t Counter;       /*!< Specifies the WWDG free-running downcounter  value.\r\n                               This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */\r\n\r\n  uint32_t EWIMode ;      /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.\r\n                               This parameter can be a value of @ref WWDG_EWI_Mode */\r\n\r\n}WWDG_InitTypeDef;\r\n\r\n/**\r\n  * @brief  WWDG handle Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  WWDG_TypeDef                 *Instance;  /*!< Register base address    */\r\n\r\n  WWDG_InitTypeDef             Init;       /*!< WWDG required parameters */\r\n\r\n}WWDG_HandleTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup WWDG_Exported_Constants WWDG Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition\r\n  * @{\r\n  */\r\n#define WWDG_IT_EWI                         WWDG_CFR_EWI  /*!< Early wakeup interrupt */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup WWDG_Flag_definition WWDG Flag definition\r\n  * @brief WWDG Flag definition\r\n  * @{\r\n  */\r\n#define WWDG_FLAG_EWIF                      WWDG_SR_EWIF  /*!< Early wakeup interrupt flag */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup WWDG_Prescaler WWDG Prescaler\r\n  * @{\r\n  */\r\n#define WWDG_PRESCALER_1                    0x00000000U       /*!< WWDG counter clock = (PCLK1/4096)/1 */\r\n#define WWDG_PRESCALER_2                    WWDG_CFR_WDGTB_0  /*!< WWDG counter clock = (PCLK1/4096)/2 */\r\n#define WWDG_PRESCALER_4                    WWDG_CFR_WDGTB_1  /*!< WWDG counter clock = (PCLK1/4096)/4 */\r\n#define WWDG_PRESCALER_8                    WWDG_CFR_WDGTB    /*!< WWDG counter clock = (PCLK1/4096)/8 */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode\r\n  * @{\r\n  */\r\n#define WWDG_EWI_DISABLE                    0x00000000u       /*!< EWI Disable */\r\n#define WWDG_EWI_ENABLE                     WWDG_CFR_EWI      /*!< EWI Enable */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n\r\n/** @defgroup WWDG_Private_Macros WWDG Private Macros\r\n  * @{\r\n  */\r\n#define IS_WWDG_PRESCALER(__PRESCALER__)    (((__PRESCALER__) == WWDG_PRESCALER_1) || \\\r\n                                             ((__PRESCALER__) == WWDG_PRESCALER_2) || \\\r\n                                             ((__PRESCALER__) == WWDG_PRESCALER_4) || \\\r\n                                             ((__PRESCALER__) == WWDG_PRESCALER_8))\r\n\r\n#define IS_WWDG_WINDOW(__WINDOW__)          (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))\r\n\r\n#define IS_WWDG_COUNTER(__COUNTER__)        (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))\r\n\r\n#define IS_WWDG_EWI_MODE(__MODE__)          (((__MODE__) == WWDG_EWI_ENABLE) || \\\r\n                                             ((__MODE__) == WWDG_EWI_DISABLE))\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/* Exported macros ------------------------------------------------------------*/\r\n\r\n/** @defgroup WWDG_Exported_Macros WWDG Exported Macros\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Enable the WWDG peripheral.\r\n  * @param  __HANDLE__  WWDG handle\r\n  * @retval None\r\n  */\r\n#define __HAL_WWDG_ENABLE(__HANDLE__)                         SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)\r\n\r\n/**\r\n  * @brief  Enable the WWDG early wakeup interrupt.\r\n  * @param  __HANDLE__ WWDG handle\r\n  * @param  __INTERRUPT__  specifies the interrupt to enable.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg WWDG_IT_EWI: Early wakeup interrupt\r\n  * @note   Once enabled this interrupt cannot be disabled except by a system reset.\r\n  * @retval None\r\n  */\r\n#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__)       SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Check whether the selected WWDG interrupt has occurred or not.\r\n  * @param  __HANDLE__  WWDG handle\r\n  * @param  __INTERRUPT__  specifies the it to check.\r\n  *        This parameter can be one of the following values:\r\n  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT\r\n  * @retval The new state of WWDG_FLAG (SET or RESET).\r\n  */\r\n#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__)        __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))\r\n\r\n/** @brief  Clear the WWDG interrupt pending bits.\r\n  *         bits to clear the selected interrupt pending bits.\r\n  * @param  __HANDLE__  WWDG handle\r\n  * @param  __INTERRUPT__  specifies the interrupt pending bit to clear.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag\r\n  */\r\n#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__)      __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Check whether the specified WWDG flag is set or not.\r\n  * @param  __HANDLE__  WWDG handle\r\n  * @param  __FLAG__  specifies the flag to check.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag\r\n  * @retval The new state of WWDG_FLAG (SET or RESET).\r\n  */\r\n#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__)           (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))\r\n\r\n/**\r\n  * @brief  Clear the WWDG's pending flags.\r\n  * @param  __HANDLE__  WWDG handle\r\n  * @param  __FLAG__  specifies the flag to clear.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag\r\n  * @retval None\r\n  */\r\n#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->SR = ~(__FLAG__))\r\n\r\n/** @brief  Check whether the specified WWDG interrupt source is enabled or not.\r\n  * @param  __HANDLE__  WWDG Handle.\r\n  * @param  __INTERRUPT__  specifies the WWDG interrupt source to check.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg WWDG_IT_EWI: Early Wakeup Interrupt\r\n  * @retval state of __INTERRUPT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @addtogroup WWDG_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup WWDG_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n/* Initialization/de-initialization functions  **********************************/\r\nHAL_StatusTypeDef     HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);\r\nvoid                  HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup WWDG_Exported_Functions_Group2\r\n  * @{\r\n  */\r\n/* I/O operation functions ******************************************************/\r\nHAL_StatusTypeDef     HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);\r\nvoid                  HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);\r\nvoid                  HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_WWDG_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_ll_fmc.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of FMC HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_LL_FMC_H\r\n#define __STM32F7xx_LL_FMC_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup FMC_LL\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup FMC_LL_Private_Macros\r\n  * @{\r\n  */\r\n#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \\\r\n                                   ((BANK) == FMC_NORSRAM_BANK2) || \\\r\n                                   ((BANK) == FMC_NORSRAM_BANK3) || \\\r\n                                   ((BANK) == FMC_NORSRAM_BANK4))\r\n\r\n#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \\\r\n                              ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))\r\n\r\n#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \\\r\n                                    ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \\\r\n                                    ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))\r\n\r\n#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8)  || \\\r\n                                                 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \\\r\n                                                 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))\r\n\r\n#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \\\r\n                                       ((__MODE__) == FMC_ACCESS_MODE_B) || \\\r\n                                       ((__MODE__) == FMC_ACCESS_MODE_C) || \\\r\n                                       ((__MODE__) == FMC_ACCESS_MODE_D))\r\n\r\n#define IS_FMC_NAND_BANK(BANK) ((BANK) == FMC_NAND_BANK3)\r\n\r\n#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_WAIT_FEATURE_DISABLE) || \\\r\n                                      ((FEATURE) == FMC_NAND_WAIT_FEATURE_ENABLE))\r\n\r\n#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_8) || \\\r\n                                         ((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_16))\r\n\r\n#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \\\r\n                                 ((STATE) == FMC_NAND_ECC_ENABLE))\r\n\r\n#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE)  || \\\r\n                                   ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE)  || \\\r\n                                   ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \\\r\n                                   ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \\\r\n                                   ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \\\r\n                                   ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))\r\n\t\t\t\t\t\t\t\t   \r\n#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8)  || \\\r\n                                      ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \\\r\n                                      ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))\r\n\r\n#define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \\\r\n                                            ((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))\t\t\t\t\t\t\t\t\t  \r\n\r\n#define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE)  || \\\r\n                                           ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \\\r\n                                           ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3))\r\n\t\t\t\t\t\t\t\t\t\t   \r\n#define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \\\r\n                                       ((__RBURST__) == FMC_SDRAM_RBURST_ENABLE))\r\n\t\t\t\t\t\t\t\t\t   \r\n#define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \\\r\n                                          ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \\\r\n                                          ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2))\r\n\r\n#define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE)      || \\\r\n                                          ((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE)       || \\\r\n                                          ((__COMMAND__) == FMC_SDRAM_CMD_PALL)             || \\\r\n                                          ((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \\\r\n                                          ((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE)        || \\\r\n                                          ((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \\\r\n                                          ((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE))\r\n\r\n#define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \\\r\n                                           ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \\\r\n                                           ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2)) \t\t\t\t\t\t\t\t\t\t  \r\n\t\t\t\t\t\t   \r\n/** @defgroup FMC_TCLR_Setup_Time FMC TCLR Setup Time\r\n  * @{\r\n  */\r\n#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_TAR_Setup_Time FMC TAR Setup Time \r\n  * @{\r\n  */\r\n#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_Setup_Time FMC Setup Time \r\n  * @{\r\n  */\r\n#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 254)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_Wait_Setup_Time FMC Wait Setup Time \r\n  * @{\r\n  */\r\n#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 254)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_Hold_Setup_Time FMC Hold Setup Time \r\n  * @{\r\n  */\r\n#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 254)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_HiZ_Setup_Time FMC HiZ Setup Time \r\n  * @{\r\n  */\r\n#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 254)\r\n/**\r\n  * @}\r\n  */\r\n\r\n#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \\\r\n                                      ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))\r\n\r\n#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \\\r\n                                             ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))\r\n\r\n#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \\\r\n                                                ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) \r\n\r\n#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \\\r\n                                                ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))\r\n\r\n#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \\\r\n                                          ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))\r\n\r\n#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \\\r\n                                         ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))\r\n\r\n#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \\\r\n                                     ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))\r\n\r\n/** @defgroup FMC_Data_Latency FMC Data Latency \r\n  * @{\r\n  */\r\n#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))\r\n/**\r\n  * @}\r\n  */\r\n\r\n#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \\\r\n                                        ((__BURST__) == FMC_WRITE_BURST_ENABLE))\r\n\r\n#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \\\r\n                                        ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))\r\n\r\n\r\n/** @defgroup FMC_Address_Setup_Time FMC Address Setup Time\r\n  * @{\r\n  */\r\n#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_Address_Hold_Time FMC Address Hold Time\r\n  * @{\r\n  */\r\n#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_Data_Setup_Time FMC Data Setup Time\r\n  * @{\r\n  */\r\n#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_Bus_Turn_around_Duration FMC Bus Turn around Duration\r\n  * @{\r\n  */\r\n#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_CLK_Division FMC CLK Division \r\n  * @{\r\n  */\r\n#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_SDRAM_LoadToActive_Delay FMC SDRAM LoadToActive Delay\r\n  * @{\r\n  */\r\n#define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup FMC_SDRAM_ExitSelfRefresh_Delay FMC SDRAM ExitSelfRefresh Delay\r\n  * @{\r\n  */\r\n#define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))\r\n/**\r\n  * @}\r\n  */ \r\n     \r\n/** @defgroup FMC_SDRAM_SelfRefresh_Time FMC SDRAM SelfRefresh Time\r\n  * @{\r\n  */  \r\n#define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16))\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup FMC_SDRAM_RowCycle_Delay FMC SDRAM RowCycle Delay\r\n  * @{\r\n  */  \r\n#define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))\r\n/**\r\n  * @}\r\n  */  \r\n  \r\n/** @defgroup FMC_SDRAM_Write_Recovery_Time FMC SDRAM Write Recovery Time\r\n  * @{\r\n  */  \r\n#define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16))\r\n/**\r\n  * @}\r\n  */         \r\n  \r\n/** @defgroup FMC_SDRAM_RP_Delay FMC SDRAM RP Delay\r\n  * @{\r\n  */  \r\n#define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/** @defgroup FMC_SDRAM_RCD_Delay FMC SDRAM RCD Delay\r\n  * @{\r\n  */  \r\n#define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup FMC_SDRAM_AutoRefresh_Number FMC SDRAM AutoRefresh Number\r\n  * @{\r\n  */  \r\n#define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0) && ((__NUMBER__) <= 16))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_SDRAM_ModeRegister_Definition FMC SDRAM ModeRegister Definition\r\n  * @{\r\n  */\r\n#define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_SDRAM_Refresh_rate FMC SDRAM Refresh rate\r\n  * @{\r\n  */\r\n#define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup FMC_NORSRAM_Device_Instance FMC NORSRAM Device Instance\r\n  * @{\r\n  */\r\n#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance FMC NORSRAM EXTENDED Device Instance\r\n  * @{\r\n  */\r\n#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance\r\n  * @{\r\n  */\r\n#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_SDRAM_Device_Instance FMC SDRAM Device Instance\r\n  * @{\r\n  */\r\n#define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE)\r\n/**\r\n  * @}\r\n  */\r\n\r\n#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \\\r\n                                 ((BANK) == FMC_SDRAM_BANK2))\r\n\r\n#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8)  || \\\r\n                                          ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9)  || \\\r\n                                          ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \\\r\n                                          ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))\r\n\r\n#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || \\\r\n                                    ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || \\\r\n                                    ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))\r\n\r\n#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \\\r\n                                            ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))\r\n\r\n\r\n#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \\\r\n                                     ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \\\r\n                                     ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))\r\n\r\n#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \\\r\n                                   ((__SIZE__) == FMC_PAGE_SIZE_128) || \\\r\n                                   ((__SIZE__) == FMC_PAGE_SIZE_256) || \\\r\n                                   ((__SIZE__) == FMC_PAGE_SIZE_512) || \\\r\n                                   ((__SIZE__) == FMC_PAGE_SIZE_1024))\r\n\r\n#define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \\\r\n                                     ((__FIFO__) == FMC_WRITE_FIFO_ENABLE))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported typedef ----------------------------------------------------------*/\r\n/** @defgroup FMC_Exported_typedef FMC Low Layer Exported Types\r\n  * @{\r\n  */\r\n#define FMC_NORSRAM_TypeDef            FMC_Bank1_TypeDef\r\n#define FMC_NORSRAM_EXTENDED_TypeDef   FMC_Bank1E_TypeDef\r\n#define FMC_NAND_TypeDef               FMC_Bank3_TypeDef\r\n#define FMC_SDRAM_TypeDef              FMC_Bank5_6_TypeDef\r\n\r\n#define FMC_NORSRAM_DEVICE             FMC_Bank1\r\n#define FMC_NORSRAM_EXTENDED_DEVICE    FMC_Bank1E\r\n#define FMC_NAND_DEVICE                FMC_Bank3\r\n#define FMC_SDRAM_DEVICE               FMC_Bank5_6\r\n\r\n/** \r\n  * @brief  FMC NORSRAM Configuration Structure definition\r\n  */ \r\ntypedef struct\r\n{\r\n  uint32_t NSBank;                       /*!< Specifies the NORSRAM memory device that will be used.\r\n                                              This parameter can be a value of @ref FMC_NORSRAM_Bank                     */\r\n\r\n  uint32_t DataAddressMux;               /*!< Specifies whether the address and data values are\r\n                                              multiplexed on the data bus or not. \r\n                                              This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing    */\r\n\r\n  uint32_t MemoryType;                   /*!< Specifies the type of external memory attached to\r\n                                              the corresponding memory device.\r\n                                              This parameter can be a value of @ref FMC_Memory_Type                      */\r\n\r\n  uint32_t MemoryDataWidth;              /*!< Specifies the external memory device width.\r\n                                              This parameter can be a value of @ref FMC_NORSRAM_Data_Width               */\r\n\r\n  uint32_t BurstAccessMode;              /*!< Enables or disables the burst access mode for Flash memory,\r\n                                              valid only with synchronous burst Flash memories.\r\n                                              This parameter can be a value of @ref FMC_Burst_Access_Mode                */\r\n\r\n  uint32_t WaitSignalPolarity;           /*!< Specifies the wait signal polarity, valid only when accessing\r\n                                              the Flash memory in burst mode.\r\n                                              This parameter can be a value of @ref FMC_Wait_Signal_Polarity             */\r\n\r\n  uint32_t WaitSignalActive;             /*!< Specifies if the wait signal is asserted by the memory one\r\n                                              clock cycle before the wait state or during the wait state,\r\n                                              valid only when accessing memories in burst mode. \r\n                                              This parameter can be a value of @ref FMC_Wait_Timing                      */\r\n\r\n  uint32_t WriteOperation;               /*!< Enables or disables the write operation in the selected device by the FMC. \r\n                                              This parameter can be a value of @ref FMC_Write_Operation                  */\r\n\r\n  uint32_t WaitSignal;                   /*!< Enables or disables the wait state insertion via wait\r\n                                              signal, valid for Flash memory access in burst mode. \r\n                                              This parameter can be a value of @ref FMC_Wait_Signal                      */\r\n\r\n  uint32_t ExtendedMode;                 /*!< Enables or disables the extended mode.\r\n                                              This parameter can be a value of @ref FMC_Extended_Mode                    */\r\n\r\n  uint32_t AsynchronousWait;             /*!< Enables or disables wait signal during asynchronous transfers,\r\n                                              valid only with asynchronous Flash memories.\r\n                                              This parameter can be a value of @ref FMC_AsynchronousWait                 */\r\n\r\n  uint32_t WriteBurst;                   /*!< Enables or disables the write burst operation.\r\n                                              This parameter can be a value of @ref FMC_Write_Burst                      */\r\n\r\n  uint32_t ContinuousClock;              /*!< Enables or disables the FMC clock output to external memory devices.\r\n                                              This parameter is only enabled through the FMC_BCR1 register, and don't care \r\n                                              through FMC_BCR2..4 registers.\r\n                                              This parameter can be a value of @ref FMC_Continous_Clock                  */\r\n\r\n  uint32_t WriteFifo;                    /*!< Enables or disables the write FIFO used by the FMC controller.\r\n                                              This parameter is only enabled through the FMC_BCR1 register, and don't care \r\n                                              through FMC_BCR2..4 registers.\r\n                                              This parameter can be a value of @ref FMC_Write_FIFO                      */\r\n\r\n  uint32_t PageSize;                     /*!< Specifies the memory page size.\r\n                                              This parameter can be a value of @ref FMC_Page_Size                        */\r\n\r\n}FMC_NORSRAM_InitTypeDef;\r\n\r\n/** \r\n  * @brief  FMC NORSRAM Timing parameters structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t AddressSetupTime;             /*!< Defines the number of HCLK cycles to configure\r\n                                              the duration of the address setup time. \r\n                                              This parameter can be a value between Min_Data = 0 and Max_Data = 15.\r\n                                              @note This parameter is not used with synchronous NOR Flash memories.      */\r\n\r\n  uint32_t AddressHoldTime;              /*!< Defines the number of HCLK cycles to configure\r\n                                              the duration of the address hold time.\r\n                                              This parameter can be a value between Min_Data = 1 and Max_Data = 15. \r\n                                              @note This parameter is not used with synchronous NOR Flash memories.      */\r\n\r\n  uint32_t DataSetupTime;                /*!< Defines the number of HCLK cycles to configure\r\n                                              the duration of the data setup time.\r\n                                              This parameter can be a value between Min_Data = 1 and Max_Data = 255.\r\n                                              @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed \r\n                                              NOR Flash memories.                                                        */\r\n\r\n  uint32_t BusTurnAroundDuration;        /*!< Defines the number of HCLK cycles to configure\r\n                                              the duration of the bus turnaround.\r\n                                              This parameter can be a value between Min_Data = 0 and Max_Data = 15.\r\n                                              @note This parameter is only used for multiplexed NOR Flash memories.      */\r\n\r\n  uint32_t CLKDivision;                  /*!< Defines the period of CLK clock output signal, expressed in number of \r\n                                              HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.\r\n                                              @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM \r\n                                              accesses.                                                                  */\r\n\r\n  uint32_t DataLatency;                  /*!< Defines the number of memory clock cycles to issue\r\n                                              to the memory before getting the first data.\r\n                                              The parameter value depends on the memory type as shown below:\r\n                                              - It must be set to 0 in case of a CRAM\r\n                                              - It is don't care in asynchronous NOR, SRAM or ROM accesses\r\n                                              - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories\r\n                                                with synchronous burst mode enable                                       */\r\n\r\n  uint32_t AccessMode;                   /*!< Specifies the asynchronous access mode. \r\n                                              This parameter can be a value of @ref FMC_Access_Mode                      */\r\n}FMC_NORSRAM_TimingTypeDef;\r\n\r\n/** \r\n  * @brief  FMC NAND Configuration Structure definition  \r\n  */ \r\ntypedef struct\r\n{\r\n  uint32_t NandBank;               /*!< Specifies the NAND memory device that will be used.\r\n                                        This parameter can be a value of @ref FMC_NAND_Bank                    */\r\n\r\n  uint32_t Waitfeature;            /*!< Enables or disables the Wait feature for the NAND Memory device.\r\n                                        This parameter can be any value of @ref FMC_Wait_feature               */\r\n\r\n  uint32_t MemoryDataWidth;        /*!< Specifies the external memory device width.\r\n                                        This parameter can be any value of @ref FMC_NAND_Data_Width            */\r\n\r\n  uint32_t EccComputation;         /*!< Enables or disables the ECC computation.\r\n                                        This parameter can be any value of @ref FMC_ECC                        */\r\n\r\n  uint32_t ECCPageSize;            /*!< Defines the page size for the extended ECC.\r\n                                        This parameter can be any value of @ref FMC_ECC_Page_Size              */\r\n\r\n  uint32_t TCLRSetupTime;          /*!< Defines the number of HCLK cycles to configure the\r\n                                        delay between CLE low and RE low.\r\n                                        This parameter can be a value between Min_Data = 0 and Max_Data = 255  */\r\n\r\n  uint32_t TARSetupTime;           /*!< Defines the number of HCLK cycles to configure the\r\n                                        delay between ALE low and RE low.\r\n                                        This parameter can be a number between Min_Data = 0 and Max_Data = 255 */\r\n}FMC_NAND_InitTypeDef;\r\n\r\n/** \r\n  * @brief  FMC NAND Timing parameters structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t SetupTime;            /*!< Defines the number of HCLK cycles to setup address before\r\n                                      the command assertion for NAND-Flash read or write access\r\n                                      to common/Attribute or I/O memory space (depending on\r\n                                      the memory space timing to be configured).\r\n                                      This parameter can be a value between Min_Data = 0 and Max_Data = 254    */\r\n\r\n  uint32_t WaitSetupTime;        /*!< Defines the minimum number of HCLK cycles to assert the\r\n                                      command for NAND-Flash read or write access to\r\n                                      common/Attribute or I/O memory space (depending on the\r\n                                      memory space timing to be configured). \r\n                                      This parameter can be a number between Min_Data = 0 and Max_Data = 254   */\r\n\r\n  uint32_t HoldSetupTime;        /*!< Defines the number of HCLK clock cycles to hold address\r\n                                      (and data for write access) after the command de-assertion\r\n                                      for NAND-Flash read or write access to common/Attribute\r\n                                      or I/O memory space (depending on the memory space timing\r\n                                      to be configured).\r\n                                      This parameter can be a number between Min_Data = 0 and Max_Data = 254   */\r\n\r\n  uint32_t HiZSetupTime;         /*!< Defines the number of HCLK clock cycles during which the\r\n                                      data bus is kept in HiZ after the start of a NAND-Flash\r\n                                      write access to common/Attribute or I/O memory space (depending\r\n                                      on the memory space timing to be configured).\r\n                                      This parameter can be a number between Min_Data = 0 and Max_Data = 254   */\r\n}FMC_NAND_PCC_TimingTypeDef;\r\n\r\n/** \r\n  * @brief  FMC SDRAM Configuration Structure definition  \r\n  */  \r\ntypedef struct\r\n{\r\n  uint32_t SDBank;                      /*!< Specifies the SDRAM memory device that will be used.\r\n                                             This parameter can be a value of @ref FMC_SDRAM_Bank                */\r\n\r\n  uint32_t ColumnBitsNumber;            /*!< Defines the number of bits of column address.\r\n                                             This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */\r\n\r\n  uint32_t RowBitsNumber;               /*!< Defines the number of bits of column address.\r\n                                             This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number.    */\r\n\r\n  uint32_t MemoryDataWidth;             /*!< Defines the memory device width.\r\n                                             This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width.   */\r\n\r\n  uint32_t InternalBankNumber;          /*!< Defines the number of the device's internal banks.\r\n                                             This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number.      */\r\n\r\n  uint32_t CASLatency;                  /*!< Defines the SDRAM CAS latency in number of memory clock cycles.\r\n                                             This parameter can be a value of @ref FMC_SDRAM_CAS_Latency.        */\r\n\r\n  uint32_t WriteProtection;             /*!< Enables the SDRAM device to be accessed in write mode.\r\n                                             This parameter can be a value of @ref FMC_SDRAM_Write_Protection.   */\r\n\r\n  uint32_t SDClockPeriod;               /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow \r\n                                             to disable the clock before changing frequency.\r\n                                             This parameter can be a value of @ref FMC_SDRAM_Clock_Period.       */\r\n\r\n  uint32_t ReadBurst;                   /*!< This bit enable the SDRAM controller to anticipate the next read \r\n                                             commands during the CAS latency and stores data in the Read FIFO.\r\n                                             This parameter can be a value of @ref FMC_SDRAM_Read_Burst.         */\r\n\r\n  uint32_t ReadPipeDelay;               /*!< Define the delay in system clock cycles on read data path.\r\n                                             This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay.    */\r\n}FMC_SDRAM_InitTypeDef;\r\n\r\n/** \r\n  * @brief FMC SDRAM Timing parameters structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t LoadToActiveDelay;            /*!< Defines the delay between a Load Mode Register command and \r\n                                              an active or Refresh command in number of memory clock cycles.\r\n                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */\r\n\r\n  uint32_t ExitSelfRefreshDelay;         /*!< Defines the delay from releasing the self refresh command to \r\n                                              issuing the Activate command in number of memory clock cycles.\r\n                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */\r\n\r\n  uint32_t SelfRefreshTime;              /*!< Defines the minimum Self Refresh period in number of memory clock \r\n                                              cycles.\r\n                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */\r\n\r\n  uint32_t RowCycleDelay;                /*!< Defines the delay between the Refresh command and the Activate command\r\n                                              and the delay between two consecutive Refresh commands in number of \r\n                                              memory clock cycles.\r\n                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */\r\n\r\n  uint32_t WriteRecoveryTime;            /*!< Defines the Write recovery Time in number of memory clock cycles.\r\n                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */\r\n\r\n  uint32_t RPDelay;                      /*!< Defines the delay between a Precharge Command and an other command \r\n                                              in number of memory clock cycles.\r\n                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */\r\n\r\n  uint32_t RCDDelay;                     /*!< Defines the delay between the Activate Command and a Read/Write \r\n                                              command in number of memory clock cycles.\r\n                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */ \r\n}FMC_SDRAM_TimingTypeDef;\r\n\r\n/** \r\n  * @brief SDRAM command parameters structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t CommandMode;                  /*!< Defines the command issued to the SDRAM device.\r\n                                              This parameter can be a value of @ref FMC_SDRAM_Command_Mode.          */\r\n\r\n  uint32_t CommandTarget;                /*!< Defines which device (1 or 2) the command will be issued to.\r\n                                              This parameter can be a value of @ref FMC_SDRAM_Command_Target.        */\r\n\r\n  uint32_t AutoRefreshNumber;            /*!< Defines the number of consecutive auto refresh command issued\r\n                                              in auto refresh mode.\r\n                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16   */\r\n  uint32_t ModeRegisterDefinition;       /*!< Defines the SDRAM Mode register content                                */\r\n}FMC_SDRAM_CommandTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller \r\n  * @{\r\n  */\r\n\r\n/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank\r\n  * @{\r\n  */\r\n#define FMC_NORSRAM_BANK1                       ((uint32_t)0x00000000U)\r\n#define FMC_NORSRAM_BANK2                       ((uint32_t)0x00000002U)\r\n#define FMC_NORSRAM_BANK3                       ((uint32_t)0x00000004U)\r\n#define FMC_NORSRAM_BANK4                       ((uint32_t)0x00000006U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing\r\n  * @{\r\n  */\r\n#define FMC_DATA_ADDRESS_MUX_DISABLE            ((uint32_t)0x00000000U)\r\n#define FMC_DATA_ADDRESS_MUX_ENABLE             ((uint32_t)0x00000002U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_Memory_Type FMC Memory Type\r\n  * @{\r\n  */\r\n#define FMC_MEMORY_TYPE_SRAM                    ((uint32_t)0x00000000U)\r\n#define FMC_MEMORY_TYPE_PSRAM                   ((uint32_t)0x00000004U)\r\n#define FMC_MEMORY_TYPE_NOR                     ((uint32_t)0x00000008U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width\r\n  * @{\r\n  */\r\n#define FMC_NORSRAM_MEM_BUS_WIDTH_8             ((uint32_t)0x00000000U)\r\n#define FMC_NORSRAM_MEM_BUS_WIDTH_16            ((uint32_t)0x00000010U)\r\n#define FMC_NORSRAM_MEM_BUS_WIDTH_32            ((uint32_t)0x00000020U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access\r\n  * @{\r\n  */\r\n#define FMC_NORSRAM_FLASH_ACCESS_ENABLE         ((uint32_t)0x00000040U)\r\n#define FMC_NORSRAM_FLASH_ACCESS_DISABLE        ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode\r\n  * @{\r\n  */\r\n#define FMC_BURST_ACCESS_MODE_DISABLE           ((uint32_t)0x00000000U) \r\n#define FMC_BURST_ACCESS_MODE_ENABLE            ((uint32_t)0x00000100U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity\r\n  * @{\r\n  */\r\n#define FMC_WAIT_SIGNAL_POLARITY_LOW            ((uint32_t)0x00000000U)\r\n#define FMC_WAIT_SIGNAL_POLARITY_HIGH           ((uint32_t)0x00000200U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_Wait_Timing FMC Wait Timing\r\n  * @{\r\n  */\r\n#define FMC_WAIT_TIMING_BEFORE_WS               ((uint32_t)0x00000000U)\r\n#define FMC_WAIT_TIMING_DURING_WS               ((uint32_t)0x00000800U) \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_Write_Operation FMC Write Operation\r\n  * @{\r\n  */\r\n#define FMC_WRITE_OPERATION_DISABLE             ((uint32_t)0x00000000U)\r\n#define FMC_WRITE_OPERATION_ENABLE              ((uint32_t)0x00001000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_Wait_Signal FMC Wait Signal\r\n  * @{\r\n  */\r\n#define FMC_WAIT_SIGNAL_DISABLE                 ((uint32_t)0x00000000U)\r\n#define FMC_WAIT_SIGNAL_ENABLE                  ((uint32_t)0x00002000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_Extended_Mode FMC Extended Mode\r\n  * @{\r\n  */\r\n#define FMC_EXTENDED_MODE_DISABLE               ((uint32_t)0x00000000U)\r\n#define FMC_EXTENDED_MODE_ENABLE                ((uint32_t)0x00004000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait\r\n  * @{\r\n  */\r\n#define FMC_ASYNCHRONOUS_WAIT_DISABLE           ((uint32_t)0x00000000U)\r\n#define FMC_ASYNCHRONOUS_WAIT_ENABLE            ((uint32_t)0x00008000U)\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup FMC_Page_Size FMC Page Size\r\n  * @{\r\n  */\r\n#define FMC_PAGE_SIZE_NONE           ((uint32_t)0x00000000U)\r\n#define FMC_PAGE_SIZE_128            ((uint32_t)FMC_BCR1_CPSIZE_0)\r\n#define FMC_PAGE_SIZE_256            ((uint32_t)FMC_BCR1_CPSIZE_1)\r\n#define FMC_PAGE_SIZE_512            ((uint32_t)(FMC_BCR1_CPSIZE_0 | FMC_BCR1_CPSIZE_1))\r\n#define FMC_PAGE_SIZE_1024           ((uint32_t)FMC_BCR1_CPSIZE_2)\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup FMC_Write_Burst FMC Write Burst\r\n  * @{\r\n  */\r\n#define FMC_WRITE_BURST_DISABLE                 ((uint32_t)0x00000000U)\r\n#define FMC_WRITE_BURST_ENABLE                  ((uint32_t)0x00080000U) \r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup FMC_Continous_Clock FMC Continuous Clock\r\n  * @{\r\n  */\r\n#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY          ((uint32_t)0x00000000U)\r\n#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC         ((uint32_t)0x00100000U)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup FMC_Write_FIFO FMC Write FIFO \r\n  * @{\r\n  */\r\n#define FMC_WRITE_FIFO_DISABLE           ((uint32_t)FMC_BCR1_WFDIS)\r\n#define FMC_WRITE_FIFO_ENABLE            ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\t\r\n/** @defgroup FMC_Access_Mode FMC Access Mode \r\n  * @{\r\n  */\r\n#define FMC_ACCESS_MODE_A                        ((uint32_t)0x00000000U)\r\n#define FMC_ACCESS_MODE_B                        ((uint32_t)0x10000000U) \r\n#define FMC_ACCESS_MODE_C                        ((uint32_t)0x20000000U)\r\n#define FMC_ACCESS_MODE_D                        ((uint32_t)0x30000000)\r\n/**\r\n  * @}\r\n  */\r\n    \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller \r\n  * @{\r\n  */\r\n/** @defgroup FMC_NAND_Bank FMC NAND Bank \r\n  * @{\r\n  */\r\n#define FMC_NAND_BANK3                          ((uint32_t)0x00000100U) \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_Wait_feature FMC Wait feature\r\n  * @{\r\n  */\r\n#define FMC_NAND_WAIT_FEATURE_DISABLE           ((uint32_t)0x00000000U)\r\n#define FMC_NAND_WAIT_FEATURE_ENABLE            ((uint32_t)0x00000002U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type \r\n  * @{\r\n  */\r\n#define FMC_PCR_MEMORY_TYPE_NAND          ((uint32_t)0x00000008U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width \r\n  * @{\r\n  */\r\n#define FMC_NAND_MEM_BUS_WIDTH_8                ((uint32_t)0x00000000U)\r\n#define FMC_NAND_MEM_BUS_WIDTH_16               ((uint32_t)0x00000010U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_ECC FMC ECC \r\n  * @{\r\n  */\r\n#define FMC_NAND_ECC_DISABLE                    ((uint32_t)0x00000000U)\r\n#define FMC_NAND_ECC_ENABLE                     ((uint32_t)0x00000040U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size \r\n  * @{\r\n  */\r\n#define FMC_NAND_ECC_PAGE_SIZE_256BYTE          ((uint32_t)0x00000000U)\r\n#define FMC_NAND_ECC_PAGE_SIZE_512BYTE          ((uint32_t)0x00020000U)\r\n#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE         ((uint32_t)0x00040000U)\r\n#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE         ((uint32_t)0x00060000U)\r\n#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE         ((uint32_t)0x00080000U)\r\n#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE         ((uint32_t)0x000A0000U)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller \r\n  * @{\r\n  */\r\n/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank\r\n  * @{\r\n  */\r\n#define FMC_SDRAM_BANK1                       ((uint32_t)0x00000000U)\r\n#define FMC_SDRAM_BANK2                       ((uint32_t)0x00000001U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number \r\n  * @{\r\n  */\r\n#define FMC_SDRAM_COLUMN_BITS_NUM_8           ((uint32_t)0x00000000U)\r\n#define FMC_SDRAM_COLUMN_BITS_NUM_9           ((uint32_t)0x00000001U)\r\n#define FMC_SDRAM_COLUMN_BITS_NUM_10          ((uint32_t)0x00000002U)\r\n#define FMC_SDRAM_COLUMN_BITS_NUM_11          ((uint32_t)0x00000003U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number\r\n  * @{\r\n  */\r\n#define FMC_SDRAM_ROW_BITS_NUM_11             ((uint32_t)0x00000000U)\r\n#define FMC_SDRAM_ROW_BITS_NUM_12             ((uint32_t)0x00000004U)\r\n#define FMC_SDRAM_ROW_BITS_NUM_13             ((uint32_t)0x00000008U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width\r\n  * @{\r\n  */\r\n#define FMC_SDRAM_MEM_BUS_WIDTH_8             ((uint32_t)0x00000000U)\r\n#define FMC_SDRAM_MEM_BUS_WIDTH_16            ((uint32_t)0x00000010U)\r\n#define FMC_SDRAM_MEM_BUS_WIDTH_32            ((uint32_t)0x00000020U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number\r\n  * @{\r\n  */\r\n#define FMC_SDRAM_INTERN_BANKS_NUM_2          ((uint32_t)0x00000000U)\r\n#define FMC_SDRAM_INTERN_BANKS_NUM_4          ((uint32_t)0x00000040U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency\r\n  * @{\r\n  */\r\n#define FMC_SDRAM_CAS_LATENCY_1               ((uint32_t)0x00000080U)\r\n#define FMC_SDRAM_CAS_LATENCY_2               ((uint32_t)0x00000100U)\r\n#define FMC_SDRAM_CAS_LATENCY_3               ((uint32_t)0x00000180)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection\r\n  * @{\r\n  */\r\n#define FMC_SDRAM_WRITE_PROTECTION_DISABLE    ((uint32_t)0x00000000U)\r\n#define FMC_SDRAM_WRITE_PROTECTION_ENABLE     ((uint32_t)0x00000200U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period\r\n  * @{\r\n  */\r\n#define FMC_SDRAM_CLOCK_DISABLE               ((uint32_t)0x00000000U)\r\n#define FMC_SDRAM_CLOCK_PERIOD_2              ((uint32_t)0x00000800U)\r\n#define FMC_SDRAM_CLOCK_PERIOD_3              ((uint32_t)0x00000C00)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst\r\n  * @{\r\n  */\r\n#define FMC_SDRAM_RBURST_DISABLE              ((uint32_t)0x00000000U)\r\n#define FMC_SDRAM_RBURST_ENABLE               ((uint32_t)0x00001000U)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay\r\n  * @{\r\n  */\r\n#define FMC_SDRAM_RPIPE_DELAY_0               ((uint32_t)0x00000000U)\r\n#define FMC_SDRAM_RPIPE_DELAY_1               ((uint32_t)0x00002000U)\r\n#define FMC_SDRAM_RPIPE_DELAY_2               ((uint32_t)0x00004000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode\r\n  * @{\r\n  */\r\n#define FMC_SDRAM_CMD_NORMAL_MODE             ((uint32_t)0x00000000U)\r\n#define FMC_SDRAM_CMD_CLK_ENABLE              ((uint32_t)0x00000001U)\r\n#define FMC_SDRAM_CMD_PALL                    ((uint32_t)0x00000002U)\r\n#define FMC_SDRAM_CMD_AUTOREFRESH_MODE        ((uint32_t)0x00000003U)\r\n#define FMC_SDRAM_CMD_LOAD_MODE               ((uint32_t)0x00000004U)\r\n#define FMC_SDRAM_CMD_SELFREFRESH_MODE        ((uint32_t)0x00000005U)\r\n#define FMC_SDRAM_CMD_POWERDOWN_MODE          ((uint32_t)0x00000006U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target\r\n  * @{\r\n  */\r\n#define FMC_SDRAM_CMD_TARGET_BANK2            FMC_SDCMR_CTB2\r\n#define FMC_SDRAM_CMD_TARGET_BANK1            FMC_SDCMR_CTB1\r\n#define FMC_SDRAM_CMD_TARGET_BANK1_2          ((uint32_t)0x00000018U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status \r\n  * @{\r\n  */\r\n#define FMC_SDRAM_NORMAL_MODE                     ((uint32_t)0x00000000U)\r\n#define FMC_SDRAM_SELF_REFRESH_MODE               FMC_SDSR_MODES1_0\r\n#define FMC_SDRAM_POWER_DOWN_MODE                 FMC_SDSR_MODES1_1\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition  \r\n  * @{\r\n  */  \r\n#define FMC_IT_RISING_EDGE                ((uint32_t)0x00000008U)\r\n#define FMC_IT_LEVEL                      ((uint32_t)0x00000010U)\r\n#define FMC_IT_FALLING_EDGE               ((uint32_t)0x00000020U)\r\n#define FMC_IT_REFRESH_ERROR              ((uint32_t)0x00004000U)\r\n/**\r\n  * @}\r\n  */\r\n    \r\n/** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition \r\n  * @{\r\n  */ \r\n#define FMC_FLAG_RISING_EDGE                    ((uint32_t)0x00000001U)\r\n#define FMC_FLAG_LEVEL                          ((uint32_t)0x00000002U)\r\n#define FMC_FLAG_FALLING_EDGE                   ((uint32_t)0x00000004U)\r\n#define FMC_FLAG_FEMPT                          ((uint32_t)0x00000040U)\r\n#define FMC_SDRAM_FLAG_REFRESH_IT               FMC_SDSR_RE\r\n#define FMC_SDRAM_FLAG_BUSY                     FMC_SDSR_BUSY\r\n#define FMC_SDRAM_FLAG_REFRESH_ERROR            FMC_SDRTR_CRE\r\n/**\r\n  * @}\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/** @defgroup FMC_LL_Private_Macros FMC_LL  Private Macros\r\n  * @{\r\n  */\r\n\r\n/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros\r\n *  @brief macros to handle NOR device enable/disable and read/write operations\r\n *  @{\r\n */\r\n \r\n/**\r\n  * @brief  Enable the NORSRAM device access.\r\n  * @param  __INSTANCE__ FMC_NORSRAM Instance\r\n  * @param  __BANK__ FMC_NORSRAM Bank     \r\n  * @retval None\r\n  */ \r\n#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__)  ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN)\r\n\r\n/**\r\n  * @brief  Disable the NORSRAM device access.\r\n  * @param  __INSTANCE__ FMC_NORSRAM Instance\r\n  * @param  __BANK__ FMC_NORSRAM Bank   \r\n  * @retval None\r\n  */ \r\n#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)  \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros\r\n *  @brief macros to handle NAND device enable/disable\r\n *  @{\r\n */\r\n \r\n/**\r\n  * @brief  Enable the NAND device access.\r\n  * @param  __INSTANCE__ FMC_NAND Instance    \r\n  * @retval None\r\n  */  \r\n#define __FMC_NAND_ENABLE(__INSTANCE__)  ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)\r\n\r\n/**\r\n  * @brief  Disable the NAND device access.\r\n  * @param  __INSTANCE__ FMC_NAND Instance  \r\n  * @retval None\r\n  */\r\n#define __FMC_NAND_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)\r\n\r\n/**\r\n  * @}\r\n  */ \r\n    \r\n/** @defgroup FMC_Interrupt FMC Interrupt\r\n *  @brief macros to handle FMC interrupts\r\n * @{\r\n */ \r\n\r\n/**\r\n  * @brief  Enable the NAND device interrupt.\r\n  * @param  __INSTANCE__  FMC_NAND instance     \r\n  * @param  __INTERRUPT__ FMC_NAND interrupt \r\n  *         This parameter can be any combination of the following values:\r\n  *            @arg FMC_IT_RISING_EDGE: Interrupt rising edge.\r\n  *            @arg FMC_IT_LEVEL: Interrupt level.\r\n  *            @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.       \r\n  * @retval None\r\n  */  \r\n#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SR |= (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disable the NAND device interrupt.\r\n  * @param  __INSTANCE__  FMC_NAND Instance\r\n  * @param  __INTERRUPT__ FMC_NAND interrupt\r\n  *         This parameter can be any combination of the following values:\r\n  *            @arg FMC_IT_RISING_EDGE: Interrupt rising edge.\r\n  *            @arg FMC_IT_LEVEL: Interrupt level.\r\n  *            @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.   \r\n  * @retval None\r\n  */\r\n#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SR &= ~(__INTERRUPT__))\r\n                                                                                                                           \r\n/**\r\n  * @brief  Get flag status of the NAND device.\r\n  * @param  __INSTANCE__ FMC_NAND Instance\r\n  * @param  __BANK__     FMC_NAND Bank     \r\n  * @param  __FLAG__ FMC_NAND flag\r\n  *         This parameter can be any combination of the following values:\r\n  *            @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.\r\n  *            @arg FMC_FLAG_LEVEL: Interrupt level edge flag.\r\n  *            @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.\r\n  *            @arg FMC_FLAG_FEMPT: FIFO empty flag.   \r\n  * @retval The state of FLAG (SET or RESET).\r\n  */\r\n#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__)  (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))\r\n\r\n/**\r\n  * @brief  Clear flag status of the NAND device.\r\n  * @param  __INSTANCE__ FMC_NAND Instance   \r\n  * @param  __FLAG__ FMC_NAND flag\r\n  *         This parameter can be any combination of the following values:\r\n  *            @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.\r\n  *            @arg FMC_FLAG_LEVEL: Interrupt level edge flag.\r\n  *            @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.\r\n  *            @arg FMC_FLAG_FEMPT: FIFO empty flag.   \r\n  * @retval None\r\n  */\r\n#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->SR &= ~(__FLAG__))  \r\n\r\n/**\r\n  * @brief  Enable the SDRAM device interrupt.\r\n  * @param  __INSTANCE__ FMC_SDRAM instance  \r\n  * @param  __INTERRUPT__ FMC_SDRAM interrupt \r\n  *         This parameter can be any combination of the following values:\r\n  *            @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error      \r\n  * @retval None\r\n  */\r\n#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SDRTR |= (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disable the SDRAM device interrupt.\r\n  * @param  __INSTANCE__ FMC_SDRAM instance  \r\n  * @param  __INTERRUPT__ FMC_SDRAM interrupt \r\n  *         This parameter can be any combination of the following values:\r\n  *            @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error      \r\n  * @retval None\r\n  */\r\n#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Get flag status of the SDRAM device.\r\n  * @param  __INSTANCE__ FMC_SDRAM instance  \r\n  * @param  __FLAG__ FMC_SDRAM flag\r\n  *         This parameter can be any combination of the following values:\r\n  *            @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.\r\n  *            @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.\r\n  *            @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.\r\n  * @retval The state of FLAG (SET or RESET).\r\n  */\r\n#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))\r\n\r\n/**\r\n  * @brief  Clear flag status of the SDRAM device.\r\n  * @param  __INSTANCE__ FMC_SDRAM instance  \r\n  * @param  __FLAG__ FMC_SDRAM flag\r\n  *         This parameter can be any combination of the following values:\r\n  *           @arg FMC_SDRAM_FLAG_REFRESH_ERROR\r\n  * @retval None\r\n  */\r\n#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->SDRTR |= (__FLAG__))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions\r\n  *  @{\r\n  */\r\n\r\n/** @defgroup FMC_LL_NORSRAM  NOR SRAM\r\n  *  @{\r\n  */\r\n/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions \r\n  *  @{\r\n  */\r\nHAL_StatusTypeDef  FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);\r\nHAL_StatusTypeDef  FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);\r\nHAL_StatusTypeDef  FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);\r\nHAL_StatusTypeDef  FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions \r\n  *  @{\r\n  */\r\nHAL_StatusTypeDef  FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);\r\nHAL_StatusTypeDef  FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);\r\n/**\r\n  * @}\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_LL_NAND NAND\r\n  *  @{\r\n  */\r\n/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions \r\n  *  @{\r\n  */\r\nHAL_StatusTypeDef  FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);\r\nHAL_StatusTypeDef  FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);\r\nHAL_StatusTypeDef  FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);\r\nHAL_StatusTypeDef  FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions \r\n  *  @{\r\n  */\r\nHAL_StatusTypeDef  FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);\r\nHAL_StatusTypeDef  FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);\r\nHAL_StatusTypeDef  FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_LL_SDRAM SDRAM\r\n  *  @{\r\n  */\r\n/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions \r\n  *  @{\r\n  */\r\nHAL_StatusTypeDef  FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);\r\nHAL_StatusTypeDef  FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);\r\nHAL_StatusTypeDef  FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions \r\n  *  @{\r\n  */\r\nHAL_StatusTypeDef  FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);\r\nHAL_StatusTypeDef  FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);\r\nHAL_StatusTypeDef  FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);\r\nHAL_StatusTypeDef  FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);\r\nHAL_StatusTypeDef  FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);\r\nuint32_t           FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_LL_FMC_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_ll_sdmmc.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of SDMMC HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_LL_SDMMC_H\r\n#define __STM32F7xx_LL_SDMMC_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup SDMMC_LL\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/ \r\n/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types\r\n  * @{\r\n  */\r\n  \r\n/** \r\n  * @brief  SDMMC Configuration Structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t ClockEdge;            /*!< Specifies the clock transition on which the bit capture is made.\r\n                                      This parameter can be a value of @ref SDMMC_LL_Clock_Edge                 */\r\n\r\n  uint32_t ClockBypass;          /*!< Specifies whether the SDMMC Clock divider bypass is\r\n                                      enabled or disabled.\r\n                                      This parameter can be a value of @ref SDMMC_LL_Clock_Bypass               */\r\n\r\n  uint32_t ClockPowerSave;       /*!< Specifies whether SDMMC Clock output is enabled or\r\n                                      disabled when the bus is idle.\r\n                                      This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save           */\r\n\r\n  uint32_t BusWide;              /*!< Specifies the SDMMC bus width.\r\n                                      This parameter can be a value of @ref SDMMC_LL_Bus_Wide                   */\r\n\r\n  uint32_t HardwareFlowControl;  /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.\r\n                                      This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control      */\r\n\r\n  uint32_t ClockDiv;             /*!< Specifies the clock frequency of the SDMMC controller.\r\n                                      This parameter can be a value between Min_Data = 0 and Max_Data = 255 */  \r\n  \r\n}SDMMC_InitTypeDef;\r\n  \r\n\r\n/** \r\n  * @brief  SDMMC Command Control structure \r\n  */\r\ntypedef struct                                                                                            \r\n{\r\n  uint32_t Argument;            /*!< Specifies the SDMMC command argument which is sent\r\n                                     to a card as part of a command message. If a command\r\n                                     contains an argument, it must be loaded into this register\r\n                                     before writing the command to the command register.              */\r\n\r\n  uint32_t CmdIndex;            /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and \r\n                                     Max_Data = 64                                                    */\r\n\r\n  uint32_t Response;            /*!< Specifies the SDMMC response type.\r\n                                     This parameter can be a value of @ref SDMMC_LL_Response_Type         */\r\n\r\n  uint32_t WaitForInterrupt;    /*!< Specifies whether SDMMC wait for interrupt request is \r\n                                     enabled or disabled.\r\n                                     This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State  */\r\n\r\n  uint32_t CPSM;                /*!< Specifies whether SDMMC Command path state machine (CPSM)\r\n                                     is enabled or disabled.\r\n                                     This parameter can be a value of @ref SDMMC_LL_CPSM_State            */\r\n}SDMMC_CmdInitTypeDef;\r\n\r\n\r\n/** \r\n  * @brief  SDMMC Data Control structure \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t DataTimeOut;         /*!< Specifies the data timeout period in card bus clock periods.  */\r\n\r\n  uint32_t DataLength;          /*!< Specifies the number of data bytes to be transferred.         */\r\n \r\n  uint32_t DataBlockSize;       /*!< Specifies the data block size for block transfer.\r\n                                     This parameter can be a value of @ref SDMMC_LL_Data_Block_Size    */\r\n \r\n  uint32_t TransferDir;         /*!< Specifies the data transfer direction, whether the transfer\r\n                                     is a read or write.\r\n                                     This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */\r\n \r\n  uint32_t TransferMode;        /*!< Specifies whether data transfer is in stream or block mode.\r\n                                     This parameter can be a value of @ref SDMMC_LL_Transfer_Type      */\r\n \r\n  uint32_t DPSM;                /*!< Specifies whether SDMMC Data path state machine (DPSM)\r\n                                     is enabled or disabled.\r\n                                     This parameter can be a value of @ref SDMMC_LL_DPSM_State         */\r\n}SDMMC_DataInitTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants\r\n  * @{\r\n  */\r\n#define SDMMC_ERROR_NONE                     ((uint32_t)0x00000000U)   /*!< No error                                                      */\r\n#define SDMMC_ERROR_CMD_CRC_FAIL             ((uint32_t)0x00000001U)   /*!< Command response received (but CRC check failed)              */\r\n#define SDMMC_ERROR_DATA_CRC_FAIL            ((uint32_t)0x00000002U)   /*!< Data block sent/received (CRC check failed)                   */\r\n#define SDMMC_ERROR_CMD_RSP_TIMEOUT          ((uint32_t)0x00000004U)   /*!< Command response timeout                                      */\r\n#define SDMMC_ERROR_DATA_TIMEOUT             ((uint32_t)0x00000008U)   /*!< Data timeout                                                  */\r\n#define SDMMC_ERROR_TX_UNDERRUN              ((uint32_t)0x00000010U)   /*!< Transmit FIFO underrun                                        */\r\n#define SDMMC_ERROR_RX_OVERRUN               ((uint32_t)0x00000020U)   /*!< Receive FIFO overrun                                          */\r\n#define SDMMC_ERROR_ADDR_MISALIGNED          ((uint32_t)0x00000040U)   /*!< Misaligned address                                            */\r\n#define SDMMC_ERROR_BLOCK_LEN_ERR            ((uint32_t)0x00000080U)   /*!< Transferred block length is not allowed for the card or the \r\n                                                                            number of transferred bytes does not match the block length   */\r\n#define SDMMC_ERROR_ERASE_SEQ_ERR            ((uint32_t)0x00000100U)   /*!< An error in the sequence of erase command occurs              */\r\n#define SDMMC_ERROR_BAD_ERASE_PARAM          ((uint32_t)0x00000200U)   /*!< An invalid selection for erase groups                         */\r\n#define SDMMC_ERROR_WRITE_PROT_VIOLATION     ((uint32_t)0x00000400U)   /*!< Attempt to program a write protect block                      */\r\n#define SDMMC_ERROR_LOCK_UNLOCK_FAILED       ((uint32_t)0x00000800U)   /*!< Sequence or password error has been detected in unlock \r\n                                                                            command or if there was an attempt to access a locked card    */\r\n#define SDMMC_ERROR_COM_CRC_FAILED           ((uint32_t)0x00001000U)   /*!< CRC check of the previous command failed                      */\r\n#define SDMMC_ERROR_ILLEGAL_CMD              ((uint32_t)0x00002000U)   /*!< Command is not legal for the card state                       */\r\n#define SDMMC_ERROR_CARD_ECC_FAILED          ((uint32_t)0x00004000U)   /*!< Card internal ECC was applied but failed to correct the data  */\r\n#define SDMMC_ERROR_CC_ERR                   ((uint32_t)0x00008000U)   /*!< Internal card controller error                                */\r\n#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR      ((uint32_t)0x00010000U)   /*!< General or unknown error                                      */\r\n#define SDMMC_ERROR_STREAM_READ_UNDERRUN     ((uint32_t)0x00020000U)   /*!< The card could not sustain data reading in stream rmode       */\r\n#define SDMMC_ERROR_STREAM_WRITE_OVERRUN     ((uint32_t)0x00040000U)   /*!< The card could not sustain data programming in stream mode    */\r\n#define SDMMC_ERROR_CID_CSD_OVERWRITE        ((uint32_t)0x00080000U)   /*!< CID/CSD overwrite error                                       */\r\n#define SDMMC_ERROR_WP_ERASE_SKIP            ((uint32_t)0x00100000U)   /*!< Only partial address space was erased                         */\r\n#define SDMMC_ERROR_CARD_ECC_DISABLED        ((uint32_t)0x00200000U)   /*!< Command has been executed without using internal ECC          */\r\n#define SDMMC_ERROR_ERASE_RESET              ((uint32_t)0x00400000U)   /*!< Erase sequence was cleared before executing because an out \r\n                                                                            of erase sequence command was received                        */\r\n#define SDMMC_ERROR_AKE_SEQ_ERR              ((uint32_t)0x00800000U)   /*!< Error in sequence of authentication                           */\r\n#define SDMMC_ERROR_INVALID_VOLTRANGE        ((uint32_t)0x01000000U)   /*!< Error in case of invalid voltage range                        */\r\n#define SDMMC_ERROR_ADDR_OUT_OF_RANGE        ((uint32_t)0x02000000U)   /*!< Error when addressed block is out of range                    */\r\n#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE   ((uint32_t)0x04000000U)   /*!< Error when command request is not applicable                  */\r\n#define SDMMC_ERROR_INVALID_PARAMETER        ((uint32_t)0x08000000U)   /*!< the used parameter is not valid                               */\r\n#define SDMMC_ERROR_UNSUPPORTED_FEATURE      ((uint32_t)0x10000000U)   /*!< Error when feature is not insupported                         */\r\n#define SDMMC_ERROR_BUSY                     ((uint32_t)0x20000000U)   /*!< Error when transfer process is busy                           */\r\n#define SDMMC_ERROR_DMA                      ((uint32_t)0x40000000U)   /*!< Error while DMA transfer                                      */\r\n#define SDMMC_ERROR_TIMEOUT                  ((uint32_t)0x80000000U)   /*!< Timeout error                                                 */\r\n\r\n/** \r\n  * @brief SDMMC Commands Index \r\n  */\r\n#define SDMMC_CMD_GO_IDLE_STATE                       ((uint8_t)0U)   /*!< Resets the SD memory card.                                                               */\r\n#define SDMMC_CMD_SEND_OP_COND                        ((uint8_t)1U)   /*!< Sends host capacity support information and activates the card's initialization process. */\r\n#define SDMMC_CMD_ALL_SEND_CID                        ((uint8_t)2U)   /*!< Asks any card connected to the host to send the CID numbers on the CMD line.             */\r\n#define SDMMC_CMD_SET_REL_ADDR                        ((uint8_t)3U)   /*!< Asks the card to publish a new relative address (RCA).                                   */\r\n#define SDMMC_CMD_SET_DSR                             ((uint8_t)4U)   /*!< Programs the DSR of all cards.                                                           */\r\n#define SDMMC_CMD_SDMMC_SEN_OP_COND                   ((uint8_t)5U)   /*!< Sends host capacity support information (HCS) and asks the accessed card to send its \r\n                                                                       operating condition register (OCR) content in the response on the CMD line.                  */\r\n#define SDMMC_CMD_HS_SWITCH                           ((uint8_t)6U)   /*!< Checks switchable function (mode 0) and switch card function (mode 1).                   */\r\n#define SDMMC_CMD_SEL_DESEL_CARD                      ((uint8_t)7U)   /*!< Selects the card by its own relative address and gets deselected by any other address    */\r\n#define SDMMC_CMD_HS_SEND_EXT_CSD                     ((uint8_t)8U)   /*!< Sends SD Memory Card interface condition, which includes host supply voltage information \r\n                                                                       and asks the card whether card supports voltage.                                             */\r\n#define SDMMC_CMD_SEND_CSD                            ((uint8_t)9U)   /*!< Addressed card sends its card specific data (CSD) on the CMD line.                       */\r\n#define SDMMC_CMD_SEND_CID                            ((uint8_t)10U)  /*!< Addressed card sends its card identification (CID) on the CMD line.                      */\r\n#define SDMMC_CMD_READ_DAT_UNTIL_STOP                 ((uint8_t)11U)  /*!< SD card doesn't support it.                                                              */\r\n#define SDMMC_CMD_STOP_TRANSMISSION                   ((uint8_t)12U)  /*!< Forces the card to stop transmission.                                                    */\r\n#define SDMMC_CMD_SEND_STATUS                         ((uint8_t)13U)  /*!< Addressed card sends its status register.                                                */\r\n#define SDMMC_CMD_HS_BUSTEST_READ                     ((uint8_t)14U)  /*!< Reserved                                                                                 */\r\n#define SDMMC_CMD_GO_INACTIVE_STATE                   ((uint8_t)15U)  /*!< Sends an addressed card into the inactive state.                                         */\r\n#define SDMMC_CMD_SET_BLOCKLEN                        ((uint8_t)16U)  /*!< Sets the block length (in bytes for SDSC) for all following block commands \r\n                                                                           (read, write, lock). Default block length is fixed to 512 Bytes. Not effective \r\n                                                                           for SDHS and SDXC.                                                                       */\r\n#define SDMMC_CMD_READ_SINGLE_BLOCK                   ((uint8_t)17U)  /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of \r\n                                                                           fixed 512 bytes in case of SDHC and SDXC.                                                */\r\n#define SDMMC_CMD_READ_MULT_BLOCK                     ((uint8_t)18U)  /*!< Continuously transfers data blocks from card to host until interrupted by \r\n                                                                           STOP_TRANSMISSION command.                                                               */\r\n#define SDMMC_CMD_HS_BUSTEST_WRITE                    ((uint8_t)19U)  /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104.                                    */\r\n#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP                ((uint8_t)20U)  /*!< Speed class control command.                                                             */\r\n#define SDMMC_CMD_SET_BLOCK_COUNT                     ((uint8_t)23U)  /*!< Specify block count for CMD18 and CMD25.                                                 */\r\n#define SDMMC_CMD_WRITE_SINGLE_BLOCK                  ((uint8_t)24U)  /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of \r\n                                                                           fixed 512 bytes in case of SDHC and SDXC.                                                */\r\n#define SDMMC_CMD_WRITE_MULT_BLOCK                    ((uint8_t)25U)  /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows.                    */\r\n#define SDMMC_CMD_PROG_CID                            ((uint8_t)26U)  /*!< Reserved for manufacturers.                                                              */\r\n#define SDMMC_CMD_PROG_CSD                            ((uint8_t)27U)  /*!< Programming of the programmable bits of the CSD.                                         */\r\n#define SDMMC_CMD_SET_WRITE_PROT                      ((uint8_t)28U)  /*!< Sets the write protection bit of the addressed group.                                    */\r\n#define SDMMC_CMD_CLR_WRITE_PROT                      ((uint8_t)29U)  /*!< Clears the write protection bit of the addressed group.                                  */\r\n#define SDMMC_CMD_SEND_WRITE_PROT                     ((uint8_t)30U)  /*!< Asks the card to send the status of the write protection bits.                           */\r\n#define SDMMC_CMD_SD_ERASE_GRP_START                  ((uint8_t)32U)  /*!< Sets the address of the first write block to be erased. (For SD card only).              */\r\n#define SDMMC_CMD_SD_ERASE_GRP_END                    ((uint8_t)33U)  /*!< Sets the address of the last write block of the continuous range to be erased.           */\r\n#define SDMMC_CMD_ERASE_GRP_START                     ((uint8_t)35U)  /*!< Sets the address of the first write block to be erased. Reserved for each command \r\n                                                                           system set by switch function command (CMD6).                                            */\r\n#define SDMMC_CMD_ERASE_GRP_END                       ((uint8_t)36U)  /*!< Sets the address of the last write block of the continuous range to be erased. \r\n                                                                           Reserved for each command system set by switch function command (CMD6).                  */\r\n#define SDMMC_CMD_ERASE                               ((uint8_t)38U)  /*!< Reserved for SD security applications.                                                   */\r\n#define SDMMC_CMD_FAST_IO                             ((uint8_t)39U)  /*!< SD card doesn't support it (Reserved).                                                   */\r\n#define SDMMC_CMD_GO_IRQ_STATE                        ((uint8_t)40U)  /*!< SD card doesn't support it (Reserved).                                                   */\r\n#define SDMMC_CMD_LOCK_UNLOCK                         ((uint8_t)42U)  /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by \r\n                                                                           the SET_BLOCK_LEN command.                                                               */\r\n#define SDMMC_CMD_APP_CMD                             ((uint8_t)55U)  /*!< Indicates to the card that the next command is an application specific command rather \r\n                                                                           than a standard command.                                                                 */\r\n#define SDMMC_CMD_GEN_CMD                             ((uint8_t)56U)  /*!< Used either to transfer a data block to the card or to get a data block from the card \r\n                                                                           for general purpose/application specific commands.                                       */\r\n#define SDMMC_CMD_NO_CMD                              ((uint8_t)64U)  /*!< No command                                                                               */ \r\n\r\n/** \r\n  * @brief Following commands are SD Card Specific commands.\r\n  *        SDMMC_APP_CMD should be sent before sending these commands. \r\n  */\r\n#define SDMMC_CMD_APP_SD_SET_BUSWIDTH                 ((uint8_t)6U)   /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus \r\n                                                                            widths are given in SCR register.                                                       */\r\n#define SDMMC_CMD_SD_APP_STATUS                       ((uint8_t)13U)  /*!< (ACMD13) Sends the SD status.                                                            */\r\n#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS        ((uint8_t)22U)  /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with \r\n                                                                           32bit+CRC data block.                                                                    */\r\n#define SDMMC_CMD_SD_APP_OP_COND                      ((uint8_t)41U)  /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to \r\n                                                                           send its operating condition register (OCR) content in the response on the CMD line.     */\r\n#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT          ((uint8_t)42U)  /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card  */\r\n#define SDMMC_CMD_SD_APP_SEND_SCR                     ((uint8_t)51U)  /*!< Reads the SD Configuration Register (SCR).                                               */\r\n#define SDMMC_CMD_SDMMC_RW_DIRECT                     ((uint8_t)52U)  /*!< For SD I/O card only, reserved for security specification.                               */\r\n#define SDMMC_CMD_SDMMC_RW_EXTENDED                   ((uint8_t)53U)  /*!< For SD I/O card only, reserved for security specification.                               */\r\n\r\n/** \r\n  * @brief Following commands are SD Card Specific security commands.\r\n  *        SDMMC_CMD_APP_CMD should be sent before sending these commands. \r\n  */\r\n#define SDMMC_CMD_SD_APP_GET_MKB                      ((uint8_t)43U)\r\n#define SDMMC_CMD_SD_APP_GET_MID                      ((uint8_t)44U)\r\n#define SDMMC_CMD_SD_APP_SET_CER_RN1                  ((uint8_t)45U)\r\n#define SDMMC_CMD_SD_APP_GET_CER_RN2                  ((uint8_t)46U)\r\n#define SDMMC_CMD_SD_APP_SET_CER_RES2                 ((uint8_t)47U)\r\n#define SDMMC_CMD_SD_APP_GET_CER_RES1                 ((uint8_t)48U)\r\n#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK   ((uint8_t)18U)\r\n#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK  ((uint8_t)25U)\r\n#define SDMMC_CMD_SD_APP_SECURE_ERASE                 ((uint8_t)38U)\r\n#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA           ((uint8_t)49U)\r\n#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB             ((uint8_t)48U)\r\n\r\n/** \r\n  * @brief  Masks for errors Card Status R1 (OCR Register) \r\n  */\r\n#define SDMMC_OCR_ADDR_OUT_OF_RANGE        ((uint32_t)0x80000000U)\r\n#define SDMMC_OCR_ADDR_MISALIGNED          ((uint32_t)0x40000000U)\r\n#define SDMMC_OCR_BLOCK_LEN_ERR            ((uint32_t)0x20000000U)\r\n#define SDMMC_OCR_ERASE_SEQ_ERR            ((uint32_t)0x10000000U)\r\n#define SDMMC_OCR_BAD_ERASE_PARAM          ((uint32_t)0x08000000U)\r\n#define SDMMC_OCR_WRITE_PROT_VIOLATION     ((uint32_t)0x04000000U)\r\n#define SDMMC_OCR_LOCK_UNLOCK_FAILED       ((uint32_t)0x01000000U)\r\n#define SDMMC_OCR_COM_CRC_FAILED           ((uint32_t)0x00800000U)\r\n#define SDMMC_OCR_ILLEGAL_CMD              ((uint32_t)0x00400000U)\r\n#define SDMMC_OCR_CARD_ECC_FAILED          ((uint32_t)0x00200000U)\r\n#define SDMMC_OCR_CC_ERROR                 ((uint32_t)0x00100000U)\r\n#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR    ((uint32_t)0x00080000U)\r\n#define SDMMC_OCR_STREAM_READ_UNDERRUN     ((uint32_t)0x00040000U)\r\n#define SDMMC_OCR_STREAM_WRITE_OVERRUN     ((uint32_t)0x00020000U)\r\n#define SDMMC_OCR_CID_CSD_OVERWRITE        ((uint32_t)0x00010000U)\r\n#define SDMMC_OCR_WP_ERASE_SKIP            ((uint32_t)0x00008000U)\r\n#define SDMMC_OCR_CARD_ECC_DISABLED        ((uint32_t)0x00004000U)\r\n#define SDMMC_OCR_ERASE_RESET              ((uint32_t)0x00002000U)\r\n#define SDMMC_OCR_AKE_SEQ_ERROR            ((uint32_t)0x00000008U)\r\n#define SDMMC_OCR_ERRORBITS                ((uint32_t)0xFDFFE008U)\r\n\r\n/** \r\n  * @brief  Masks for R6 Response \r\n  */\r\n#define SDMMC_R6_GENERAL_UNKNOWN_ERROR     ((uint32_t)0x00002000U)\r\n#define SDMMC_R6_ILLEGAL_CMD               ((uint32_t)0x00004000U)\r\n#define SDMMC_R6_COM_CRC_FAILED            ((uint32_t)0x00008000U)\r\n\r\n#define SDMMC_VOLTAGE_WINDOW_SD            ((uint32_t)0x80100000U)\r\n#define SDMMC_HIGH_CAPACITY                ((uint32_t)0x40000000U)\r\n#define SDMMC_STD_CAPACITY                 ((uint32_t)0x00000000U)\r\n#define SDMMC_CHECK_PATTERN                ((uint32_t)0x000001AAU)\r\n\r\n#define SDMMC_MAX_VOLT_TRIAL               ((uint32_t)0x0000FFFFU)\r\n\r\n#define SDMMC_MAX_TRIAL                    ((uint32_t)0x0000FFFFU)\r\n\r\n#define SDMMC_ALLZERO                      ((uint32_t)0x00000000U)\r\n\r\n#define SDMMC_WIDE_BUS_SUPPORT             ((uint32_t)0x00040000U)\r\n#define SDMMC_SINGLE_BUS_SUPPORT           ((uint32_t)0x00010000U)\r\n#define SDMMC_CARD_LOCKED                  ((uint32_t)0x02000000U)\r\n\r\n#define SDMMC_DATATIMEOUT                  ((uint32_t)0xFFFFFFFFU)\r\n\r\n#define SDMMC_0TO7BITS                     ((uint32_t)0x000000FFU)\r\n#define SDMMC_8TO15BITS                    ((uint32_t)0x0000FF00U)\r\n#define SDMMC_16TO23BITS                   ((uint32_t)0x00FF0000U)\r\n#define SDMMC_24TO31BITS                   ((uint32_t)0xFF000000U)\r\n#define SDMMC_MAX_DATA_LENGTH              ((uint32_t)0x01FFFFFFU)\r\n\r\n#define SDMMC_HALFFIFO                     ((uint32_t)0x00000008U)\r\n#define SDMMC_HALFFIFOBYTES                ((uint32_t)0x00000020U)\r\n\r\n/** \r\n  * @brief  Command Class supported\r\n  */\r\n#define SDMMC_CCCC_ERASE                   ((uint32_t)0x00000020U)\r\n\r\n#define SDMMC_CMDTIMEOUT                   ((uint32_t)5000U)        /* Command send and response timeout */\r\n#define SDMMC_MAXERASETIMEOUT              ((uint32_t)63000U)       /* Max erase Timeout 63 s            */\r\n\r\n\r\n/** @defgroup SDMMC_LL_Clock_Edge Clock Edge\r\n  * @{\r\n  */\r\n#define SDMMC_CLOCK_EDGE_RISING               ((uint32_t)0x00000000U)\r\n#define SDMMC_CLOCK_EDGE_FALLING              SDMMC_CLKCR_NEGEDGE\r\n\r\n#define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \\\r\n                                   ((EDGE) == SDMMC_CLOCK_EDGE_FALLING))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass\r\n  * @{\r\n  */\r\n#define SDMMC_CLOCK_BYPASS_DISABLE             ((uint32_t)0x00000000U)\r\n#define SDMMC_CLOCK_BYPASS_ENABLE              SDMMC_CLKCR_BYPASS   \r\n\r\n#define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || \\\r\n                                       ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE))\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving\r\n  * @{\r\n  */\r\n#define SDMMC_CLOCK_POWER_SAVE_DISABLE         ((uint32_t)0x00000000U)\r\n#define SDMMC_CLOCK_POWER_SAVE_ENABLE          SDMMC_CLKCR_PWRSAV\r\n\r\n#define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \\\r\n                                         ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SDMMC_LL_Bus_Wide Bus Width\r\n  * @{\r\n  */\r\n#define SDMMC_BUS_WIDE_1B                      ((uint32_t)0x00000000U)\r\n#define SDMMC_BUS_WIDE_4B                      SDMMC_CLKCR_WIDBUS_0\r\n#define SDMMC_BUS_WIDE_8B                      SDMMC_CLKCR_WIDBUS_1\r\n\r\n#define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \\\r\n                                 ((WIDE) == SDMMC_BUS_WIDE_4B) || \\\r\n                                 ((WIDE) == SDMMC_BUS_WIDE_8B))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control\r\n  * @{\r\n  */\r\n#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE    ((uint32_t)0x00000000U)\r\n#define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE     SDMMC_CLKCR_HWFC_EN\r\n\r\n#define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \\\r\n                                                 ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup SDMMC_LL_Clock_Division Clock Division\r\n  * @{\r\n  */\r\n#define IS_SDMMC_CLKDIV(DIV)   ((DIV) <= 0xFF)\r\n/**\r\n  * @}\r\n  */  \r\n    \r\n/** @defgroup SDMMC_LL_Command_Index Command Index\r\n  * @{\r\n  */\r\n#define IS_SDMMC_CMD_INDEX(INDEX)            ((INDEX) < 0x40)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SDMMC_LL_Response_Type Response Type\r\n  * @{\r\n  */\r\n#define SDMMC_RESPONSE_NO                    ((uint32_t)0x00000000U)\r\n#define SDMMC_RESPONSE_SHORT                 SDMMC_CMD_WAITRESP_0\r\n#define SDMMC_RESPONSE_LONG                  SDMMC_CMD_WAITRESP\r\n\r\n#define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO)    || \\\r\n                                     ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \\\r\n                                     ((RESPONSE) == SDMMC_RESPONSE_LONG))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt\r\n  * @{\r\n  */\r\n#define SDMMC_WAIT_NO                        ((uint32_t)0x00000000U)\r\n#define SDMMC_WAIT_IT                        SDMMC_CMD_WAITINT \r\n#define SDMMC_WAIT_PEND                      SDMMC_CMD_WAITPEND\r\n\r\n#define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \\\r\n                             ((WAIT) == SDMMC_WAIT_IT) || \\\r\n                             ((WAIT) == SDMMC_WAIT_PEND))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SDMMC_LL_CPSM_State CPSM State\r\n  * @{\r\n  */\r\n#define SDMMC_CPSM_DISABLE                   ((uint32_t)0x00000000U)\r\n#define SDMMC_CPSM_ENABLE                    SDMMC_CMD_CPSMEN\r\n\r\n#define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \\\r\n                             ((CPSM) == SDMMC_CPSM_ENABLE))\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup SDMMC_LL_Response_Registers Response Register\r\n  * @{\r\n  */\r\n#define SDMMC_RESP1                          ((uint32_t)0x00000000U)\r\n#define SDMMC_RESP2                          ((uint32_t)0x00000004U)\r\n#define SDMMC_RESP3                          ((uint32_t)0x00000008U)\r\n#define SDMMC_RESP4                          ((uint32_t)0x0000000C)\r\n\r\n#define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \\\r\n                             ((RESP) == SDMMC_RESP2) || \\\r\n                             ((RESP) == SDMMC_RESP3) || \\\r\n                             ((RESP) == SDMMC_RESP4))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SDMMC_LL_Data_Length Data Lenght\r\n  * @{\r\n  */\r\n#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SDMMC_LL_Data_Block_Size  Data Block Size\r\n  * @{\r\n  */\r\n#define SDMMC_DATABLOCK_SIZE_1B               ((uint32_t)0x00000000U)\r\n#define SDMMC_DATABLOCK_SIZE_2B               SDMMC_DCTRL_DBLOCKSIZE_0\r\n#define SDMMC_DATABLOCK_SIZE_4B               SDMMC_DCTRL_DBLOCKSIZE_1\r\n#define SDMMC_DATABLOCK_SIZE_8B               (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1)\r\n#define SDMMC_DATABLOCK_SIZE_16B              SDMMC_DCTRL_DBLOCKSIZE_2\r\n#define SDMMC_DATABLOCK_SIZE_32B              (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2)\r\n#define SDMMC_DATABLOCK_SIZE_64B              (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)\r\n#define SDMMC_DATABLOCK_SIZE_128B             (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)\r\n#define SDMMC_DATABLOCK_SIZE_256B             SDMMC_DCTRL_DBLOCKSIZE_3\r\n#define SDMMC_DATABLOCK_SIZE_512B             (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3)\r\n#define SDMMC_DATABLOCK_SIZE_1024B            (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)\r\n#define SDMMC_DATABLOCK_SIZE_2048B            (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) \r\n#define SDMMC_DATABLOCK_SIZE_4096B            (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)\r\n#define SDMMC_DATABLOCK_SIZE_8192B            (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)\r\n#define SDMMC_DATABLOCK_SIZE_16384B           (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)\r\n\r\n#define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B)    || \\\r\n                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_2B)    || \\\r\n                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_4B)    || \\\r\n                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_8B)    || \\\r\n                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_16B)   || \\\r\n                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_32B)   || \\\r\n                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_64B)   || \\\r\n                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_128B)  || \\\r\n                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_256B)  || \\\r\n                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_512B)  || \\\r\n                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \\\r\n                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \\\r\n                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \\\r\n                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \\\r\n                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B)) \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction\r\n  * @{\r\n  */\r\n#define SDMMC_TRANSFER_DIR_TO_CARD            ((uint32_t)0x00000000U)\r\n#define SDMMC_TRANSFER_DIR_TO_SDMMC            SDMMC_DCTRL_DTDIR\r\n\r\n#define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \\\r\n                                    ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SDMMC_LL_Transfer_Type Transfer Type\r\n  * @{\r\n  */\r\n#define SDMMC_TRANSFER_MODE_BLOCK             ((uint32_t)0x00000000U)\r\n#define SDMMC_TRANSFER_MODE_STREAM            SDMMC_DCTRL_DTMODE\r\n\r\n#define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \\\r\n                                      ((MODE) == SDMMC_TRANSFER_MODE_STREAM))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SDMMC_LL_DPSM_State DPSM State\r\n  * @{\r\n  */\r\n#define SDMMC_DPSM_DISABLE                    ((uint32_t)0x00000000U)\r\n#define SDMMC_DPSM_ENABLE                     SDMMC_DCTRL_DTEN\r\n\r\n#define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\\\r\n                             ((DPSM) == SDMMC_DPSM_ENABLE))\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode\r\n  * @{\r\n  */\r\n#define SDMMC_READ_WAIT_MODE_DATA2                ((uint32_t)0x00000000U)\r\n#define SDMMC_READ_WAIT_MODE_CLK                  (SDMMC_DCTRL_RWMOD)\r\n\r\n#define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \\\r\n                                      ((MODE) == SDMMC_READ_WAIT_MODE_DATA2))\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources\r\n  * @{\r\n  */\r\n#define SDMMC_IT_CCRCFAIL                    SDMMC_STA_CCRCFAIL\r\n#define SDMMC_IT_DCRCFAIL                    SDMMC_STA_DCRCFAIL\r\n#define SDMMC_IT_CTIMEOUT                    SDMMC_STA_CTIMEOUT\r\n#define SDMMC_IT_DTIMEOUT                    SDMMC_STA_DTIMEOUT\r\n#define SDMMC_IT_TXUNDERR                    SDMMC_STA_TXUNDERR\r\n#define SDMMC_IT_RXOVERR                     SDMMC_STA_RXOVERR\r\n#define SDMMC_IT_CMDREND                     SDMMC_STA_CMDREND\r\n#define SDMMC_IT_CMDSENT                     SDMMC_STA_CMDSENT\r\n#define SDMMC_IT_DATAEND                     SDMMC_STA_DATAEND\r\n#define SDMMC_IT_DBCKEND                     SDMMC_STA_DBCKEND\r\n#define SDMMC_IT_CMDACT                      SDMMC_STA_CMDACT\r\n#define SDMMC_IT_TXACT                       SDMMC_STA_TXACT\r\n#define SDMMC_IT_RXACT                       SDMMC_STA_RXACT\r\n#define SDMMC_IT_TXFIFOHE                    SDMMC_STA_TXFIFOHE\r\n#define SDMMC_IT_RXFIFOHF                    SDMMC_STA_RXFIFOHF\r\n#define SDMMC_IT_TXFIFOF                     SDMMC_STA_TXFIFOF\r\n#define SDMMC_IT_RXFIFOF                     SDMMC_STA_RXFIFOF\r\n#define SDMMC_IT_TXFIFOE                     SDMMC_STA_TXFIFOE\r\n#define SDMMC_IT_RXFIFOE                     SDMMC_STA_RXFIFOE\r\n#define SDMMC_IT_TXDAVL                      SDMMC_STA_TXDAVL\r\n#define SDMMC_IT_RXDAVL                      SDMMC_STA_RXDAVL\r\n#define SDMMC_IT_SDIOIT                      SDMMC_STA_SDIOIT\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup SDMMC_LL_Flags Flags\r\n  * @{\r\n  */\r\n#define SDMMC_FLAG_CCRCFAIL                  SDMMC_STA_CCRCFAIL\r\n#define SDMMC_FLAG_DCRCFAIL                  SDMMC_STA_DCRCFAIL\r\n#define SDMMC_FLAG_CTIMEOUT                  SDMMC_STA_CTIMEOUT\r\n#define SDMMC_FLAG_DTIMEOUT                  SDMMC_STA_DTIMEOUT\r\n#define SDMMC_FLAG_TXUNDERR                  SDMMC_STA_TXUNDERR\r\n#define SDMMC_FLAG_RXOVERR                   SDMMC_STA_RXOVERR\r\n#define SDMMC_FLAG_CMDREND                   SDMMC_STA_CMDREND\r\n#define SDMMC_FLAG_CMDSENT                   SDMMC_STA_CMDSENT\r\n#define SDMMC_FLAG_DATAEND                   SDMMC_STA_DATAEND\r\n#define SDMMC_FLAG_DBCKEND                   SDMMC_STA_DBCKEND\r\n#define SDMMC_FLAG_CMDACT                    SDMMC_STA_CMDACT\r\n#define SDMMC_FLAG_TXACT                     SDMMC_STA_TXACT\r\n#define SDMMC_FLAG_RXACT                     SDMMC_STA_RXACT\r\n#define SDMMC_FLAG_TXFIFOHE                  SDMMC_STA_TXFIFOHE\r\n#define SDMMC_FLAG_RXFIFOHF                  SDMMC_STA_RXFIFOHF\r\n#define SDMMC_FLAG_TXFIFOF                   SDMMC_STA_TXFIFOF\r\n#define SDMMC_FLAG_RXFIFOF                   SDMMC_STA_RXFIFOF\r\n#define SDMMC_FLAG_TXFIFOE                   SDMMC_STA_TXFIFOE\r\n#define SDMMC_FLAG_RXFIFOE                   SDMMC_STA_RXFIFOE\r\n#define SDMMC_FLAG_TXDAVL                    SDMMC_STA_TXDAVL\r\n#define SDMMC_FLAG_RXDAVL                    SDMMC_STA_RXDAVL\r\n#define SDMMC_FLAG_SDIOIT                    SDMMC_STA_SDIOIT\r\n#define SDMMC_STATIC_FLAGS                   ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\\\r\n                                                         SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR  |\\\r\n                                                         SDMMC_FLAG_CMDREND  | SDMMC_FLAG_CMDSENT  | SDMMC_FLAG_DATAEND  |\\\r\n                                                         SDMMC_FLAG_DBCKEND))  \r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions\r\n  * @brief SDMMC_LL registers bit address in the alias region\r\n  * @{\r\n  */\r\n/* ---------------------- SDMMC registers bit mask --------------------------- */\r\n/* --- CLKCR Register ---*/\r\n/* CLKCR register clear mask */ \r\n#define CLKCR_CLEAR_MASK         ((uint32_t)(SDMMC_CLKCR_CLKDIV  | SDMMC_CLKCR_PWRSAV |\\\r\n                                             SDMMC_CLKCR_BYPASS  | SDMMC_CLKCR_WIDBUS |\\\r\n                                             SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN))\r\n\r\n/* --- DCTRL Register ---*/\r\n/* SDMMC DCTRL Clear Mask */\r\n#define DCTRL_CLEAR_MASK         ((uint32_t)(SDMMC_DCTRL_DTEN    | SDMMC_DCTRL_DTDIR |\\\r\n                                             SDMMC_DCTRL_DTMODE  | SDMMC_DCTRL_DBLOCKSIZE))\r\n\r\n/* --- CMD Register ---*/\r\n/* CMD Register clear mask */\r\n#define CMD_CLEAR_MASK           ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\\\r\n                                             SDMMC_CMD_WAITINT  | SDMMC_CMD_WAITPEND |\\\r\n                                             SDMMC_CMD_CPSMEN   | SDMMC_CMD_SDIOSUSPEND))\r\n\r\n/* SDMMC Initialization Frequency (400KHz max) */\r\n#define SDMMC_INIT_CLK_DIV     ((uint8_t)0x76)\r\n\r\n/* SDMMC Data Transfer Frequency (25MHz max) */\r\n#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration\r\n *  @brief macros to handle interrupts and specific clock configurations\r\n * @{\r\n */\r\n \r\n/**\r\n  * @brief  Enable the SDMMC device.\r\n  * @param  __INSTANCE__ SDMMC Instance  \r\n  * @retval None\r\n  */ \r\n#define __SDMMC_ENABLE(__INSTANCE__)  ((__INSTANCE__)->CLKCR |= SDMMC_CLKCR_CLKEN)\r\n\r\n/**\r\n  * @brief  Disable the SDMMC device.\r\n  * @param  __INSTANCE__ SDMMC Instance  \r\n  * @retval None\r\n  */\r\n#define __SDMMC_DISABLE(__INSTANCE__)  ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN)\r\n\r\n/**\r\n  * @brief  Enable the SDMMC DMA transfer.\r\n  * @param  __INSTANCE__ SDMMC Instance  \r\n  * @retval None\r\n  */ \r\n#define __SDMMC_DMA_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_DMAEN)\r\n/**\r\n  * @brief  Disable the SDMMC DMA transfer.\r\n  * @param  __INSTANCE__ SDMMC Instance   \r\n  * @retval None\r\n  */\r\n#define __SDMMC_DMA_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN)\r\n \r\n/**\r\n  * @brief  Enable the SDMMC device interrupt.\r\n  * @param  __INSTANCE__  Pointer to SDMMC register base  \r\n  * @param  __INTERRUPT__  specifies the SDMMC interrupt sources to be enabled.\r\n  *         This parameter can be one or a combination of the following values:\r\n  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r\n  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r\n  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt\r\n  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt\r\n  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r\n  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt\r\n  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt\r\n  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt\r\n  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt\r\n  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt\r\n  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt\r\n  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt\r\n  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt\r\n  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\r\n  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt\r\n  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt\r\n  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt\r\n  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt\r\n  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt\r\n  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt\r\n  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt\r\n  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt   \r\n  * @retval None\r\n  */\r\n#define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK |= (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disable the SDMMC device interrupt.\r\n  * @param  __INSTANCE__  Pointer to SDMMC register base   \r\n  * @param  __INTERRUPT__  specifies the SDMMC interrupt sources to be disabled.\r\n  *          This parameter can be one or a combination of the following values:\r\n  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r\n  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r\n  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt\r\n  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt\r\n  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r\n  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt\r\n  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt\r\n  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt\r\n  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt\r\n  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt\r\n  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt\r\n  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt\r\n  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt\r\n  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\r\n  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt\r\n  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt\r\n  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt\r\n  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt\r\n  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt\r\n  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt\r\n  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt\r\n  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt   \r\n  * @retval None\r\n  */\r\n#define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Checks whether the specified SDMMC flag is set or not. \r\n  * @param  __INSTANCE__  Pointer to SDMMC register base   \r\n  * @param  __FLAG__ specifies the flag to check. \r\n  *          This parameter can be one of the following values:\r\n  *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)\r\n  *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)\r\n  *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout\r\n  *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout\r\n  *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error\r\n  *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error\r\n  *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)\r\n  *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)\r\n  *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)\r\n  *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)\r\n  *            @arg SDMMC_FLAG_CMDACT:   Command transfer in progress\r\n  *            @arg SDMMC_FLAG_TXACT:    Data transmit in progress\r\n  *            @arg SDMMC_FLAG_RXACT:    Data receive in progress\r\n  *            @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty\r\n  *            @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full\r\n  *            @arg SDMMC_FLAG_TXFIFOF:  Transmit FIFO full\r\n  *            @arg SDMMC_FLAG_RXFIFOF:  Receive FIFO full\r\n  *            @arg SDMMC_FLAG_TXFIFOE:  Transmit FIFO empty\r\n  *            @arg SDMMC_FLAG_RXFIFOE:  Receive FIFO empty\r\n  *            @arg SDMMC_FLAG_TXDAVL:   Data available in transmit FIFO\r\n  *            @arg SDMMC_FLAG_RXDAVL:   Data available in receive FIFO\r\n  *            @arg SDMMC_FLAG_SDMMCIT:   SD I/O interrupt received\r\n  * @retval The new state of SDMMC_FLAG (SET or RESET).\r\n  */\r\n#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->STA &(__FLAG__)) != RESET)\r\n\r\n\r\n/**\r\n  * @brief  Clears the SDMMC pending flags.\r\n  * @param  __INSTANCE__  Pointer to SDMMC register base  \r\n  * @param  __FLAG__ specifies the flag to clear.  \r\n  *          This parameter can be one or a combination of the following values:\r\n  *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)\r\n  *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)\r\n  *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout\r\n  *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout\r\n  *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error\r\n  *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error\r\n  *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)\r\n  *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)\r\n  *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)\r\n  *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)\r\n  *            @arg SDMMC_FLAG_SDMMCIT:   SD I/O interrupt received\r\n  * @retval None\r\n  */\r\n#define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->ICR = (__FLAG__))\r\n\r\n/**\r\n  * @brief  Checks whether the specified SDMMC interrupt has occurred or not.\r\n  * @param  __INSTANCE__  Pointer to SDMMC register base   \r\n  * @param  __INTERRUPT__ specifies the SDMMC interrupt source to check. \r\n  *          This parameter can be one of the following values:\r\n  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r\n  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r\n  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt\r\n  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt\r\n  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r\n  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt\r\n  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt\r\n  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt\r\n  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt\r\n  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt\r\n  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt\r\n  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt\r\n  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt\r\n  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\r\n  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt\r\n  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt\r\n  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt\r\n  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt\r\n  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt\r\n  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt\r\n  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt\r\n  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt\r\n  * @retval The new state of SDMMC_IT (SET or RESET).\r\n  */\r\n#define __SDMMC_GET_IT  (__INSTANCE__, __INTERRUPT__)  (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Clears the SDMMC's interrupt pending bits.\r\n  * @param  __INSTANCE__  Pointer to SDMMC register base \r\n  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear. \r\n  *          This parameter can be one or a combination of the following values:\r\n  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r\n  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r\n  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt\r\n  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt\r\n  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r\n  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt\r\n  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt\r\n  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt\r\n  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDMMC_DCOUNT, is zero) interrupt\r\n  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt\r\n  * @retval None\r\n  */\r\n#define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->ICR = (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Enable Start the SD I/O Read Wait operation.\r\n  * @param  __INSTANCE__  Pointer to SDMMC register base  \r\n  * @retval None\r\n  */  \r\n#define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART)\r\n\r\n/**\r\n  * @brief  Disable Start the SD I/O Read Wait operations.\r\n  * @param  __INSTANCE__  Pointer to SDMMC register base   \r\n  * @retval None\r\n  */  \r\n#define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)\r\n\r\n/**\r\n  * @brief  Enable Start the SD I/O Read Wait operation.\r\n  * @param  __INSTANCE__  Pointer to SDMMC register base   \r\n  * @retval None\r\n  */  \r\n#define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP)\r\n\r\n/**\r\n  * @brief  Disable Stop the SD I/O Read Wait operations.\r\n  * @param  __INSTANCE__  Pointer to SDMMC register base  \r\n  * @retval None\r\n  */  \r\n#define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)\r\n\r\n/**\r\n  * @brief  Enable the SD I/O Mode Operation.\r\n  * @param  __INSTANCE__  Pointer to SDMMC register base   \r\n  * @retval None\r\n  */  \r\n#define __SDMMC_OPERATION_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN) \r\n\r\n/**\r\n  * @brief  Disable the SD I/O Mode Operation.\r\n  * @param  __INSTANCE__  Pointer to SDMMC register base \r\n  * @retval None\r\n  */  \r\n#define __SDMMC_OPERATION_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN) \r\n\r\n/**\r\n  * @brief  Enable the SD I/O Suspend command sending.\r\n  * @param  __INSTANCE__  Pointer to SDMMC register base  \r\n  * @retval None\r\n  */  \r\n#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__)  ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND) \r\n\r\n/**\r\n  * @brief  Disable the SD I/O Suspend command sending.\r\n  * @param  __INSTANCE__  Pointer to SDMMC register base  \r\n  * @retval None\r\n  */  \r\n#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__)  ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND) \r\n      \r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup SDMMC_LL_Exported_Functions\r\n  * @{\r\n  */\r\n  \r\n/* Initialization/de-initialization functions  **********************************/\r\n/** @addtogroup HAL_SDMMC_LL_Group1\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* I/O operation functions  *****************************************************/\r\n/** @addtogroup HAL_SDMMC_LL_Group2\r\n  * @{\r\n  */\r\nuint32_t          SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);\r\nHAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData);\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Peripheral Control functions  ************************************************/\r\n/** @addtogroup HAL_SDMMC_LL_Group3\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx);\r\nHAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);\r\nuint32_t          SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx);\r\n\r\n/* Command path state machine (CPSM) management functions */\r\nHAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command);\r\nuint8_t           SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx);\r\nuint32_t          SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);\r\n\r\n/* Data path state machine (DPSM) management functions */\r\nHAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data);\r\nuint32_t          SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);\r\nuint32_t          SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);\r\n\r\n/* SDMMC Cards mode management functions */\r\nHAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);\r\n\r\n/* SDMMC Commands management functions */\r\nuint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize);\r\nuint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);\r\nuint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);\r\nuint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);\r\nuint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);\r\nuint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);\r\nuint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);\r\nuint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);\r\nuint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);\r\nuint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx);\r\nuint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx);\r\nuint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr);\r\nuint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx);\r\nuint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx);\r\nuint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);\r\nuint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t SdType);\r\nuint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth);\r\nuint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx);\r\nuint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx);\r\nuint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);\r\nuint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA);\r\nuint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument);\r\nuint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx);\r\nuint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument);\r\nuint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument);\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_LL_SDMMC_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usb.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_ll_usb.h\r\n  * @author  MCD Application Team\r\n  * @brief   Header file of USB Low Layer HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_LL_USB_H\r\n#define __STM32F7xx_LL_USB_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup USB_LL\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n\r\n/**\r\n  * @brief  USB Mode definition\r\n  */\r\ntypedef enum\r\n{\r\n   USB_DEVICE_MODE  = 0,\r\n   USB_HOST_MODE    = 1,\r\n   USB_DRD_MODE     = 2\r\n}USB_OTG_ModeTypeDef;\r\n\r\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\r\n/**\r\n  * @brief  URB States definition\r\n  */\r\ntypedef enum {\r\n  URB_IDLE = 0,\r\n  URB_DONE,\r\n  URB_NOTREADY,\r\n  URB_NYET,\r\n  URB_ERROR,\r\n  URB_STALL\r\n}USB_OTG_URBStateTypeDef;\r\n\r\n/**\r\n  * @brief  Host channel States  definition\r\n  */\r\ntypedef enum {\r\n  HC_IDLE = 0,\r\n  HC_XFRC,\r\n  HC_HALTED,\r\n  HC_NAK,\r\n  HC_NYET,\r\n  HC_STALL,\r\n  HC_XACTERR,\r\n  HC_BBLERR,\r\n  HC_DATATGLERR\r\n}USB_OTG_HCStateTypeDef;\r\n\r\n/**\r\n  * @brief  USB OTG Initialization Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t dev_endpoints;        /*!< Device Endpoints number.\r\n                                      This parameter depends on the used USB core.\r\n                                      This parameter must be a number between Min_Data = 1 and Max_Data = 15 */\r\n\r\n  uint32_t Host_channels;        /*!< Host Channels number.\r\n                                      This parameter Depends on the used USB core.\r\n                                      This parameter must be a number between Min_Data = 1 and Max_Data = 15 */\r\n\r\n  uint32_t speed;                /*!< USB Core speed.\r\n                                      This parameter can be any value of @ref USB_Core_Speed_                */\r\n\r\n  uint32_t dma_enable;           /*!< Enable or disable of the USB embedded DMA used only for OTG HS.                             */\r\n\r\n  uint32_t ep0_mps;              /*!< Set the Endpoint 0 Max Packet size.\r\n                                      This parameter can be any value of @ref USB_EP0_MPS_                   */\r\n\r\n  uint32_t phy_itface;           /*!< Select the used PHY interface.\r\n                                      This parameter can be any value of @ref USB_Core_PHY_                  */\r\n\r\n  uint32_t Sof_enable;           /*!< Enable or disable the output of the SOF signal.                        */\r\n\r\n  uint32_t low_power_enable;     /*!< Enable or disable the low power mode.                                  */\r\n\r\n  uint32_t lpm_enable;           /*!< Enable or disable Link Power Management.                               */\r\n\r\n  uint32_t battery_charging_enable; /*!< Enable or disable Battery charging.                                 */\r\n\r\n  uint32_t vbus_sensing_enable;  /*!< Enable or disable the VBUS Sensing feature.                            */\r\n\r\n  uint32_t use_dedicated_ep1;    /*!< Enable or disable the use of the dedicated EP1 interrupt.              */\r\n\r\n  uint32_t use_external_vbus;    /*!< Enable or disable the use of the external VBUS.                        */\r\n}USB_OTG_CfgTypeDef;\r\n\r\ntypedef struct\r\n{\r\n  uint8_t   num;            /*!< Endpoint number\r\n                                This parameter must be a number between Min_Data = 1 and Max_Data = 15    */\r\n\r\n  uint8_t   is_in;          /*!< Endpoint direction\r\n                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */\r\n\r\n  uint8_t   is_stall;       /*!< Endpoint stall condition\r\n                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */\r\n\r\n  uint8_t   type;           /*!< Endpoint type\r\n                                 This parameter can be any value of @ref USB_EP_Type_                     */\r\n\r\n  uint8_t   data_pid_start; /*!< Initial data PID\r\n                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */\r\n\r\n  uint8_t   even_odd_frame; /*!< IFrame parity\r\n                                 This parameter must be a number between Min_Data = 0 and Max_Data = 1    */\r\n\r\n  uint16_t  tx_fifo_num;    /*!< Transmission FIFO number\r\n                                 This parameter must be a number between Min_Data = 1 and Max_Data = 15   */\r\n\r\n  uint32_t  maxpacket;      /*!< Endpoint Max packet size\r\n                                 This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */\r\n\r\n  uint8_t   *xfer_buff;     /*!< Pointer to transfer buffer                                               */\r\n\r\n  uint32_t  dma_addr;       /*!< 32 bits aligned transfer buffer address                                  */\r\n\r\n  uint32_t  xfer_len;       /*!< Current transfer length                                                  */\r\n\r\n  uint32_t  xfer_count;     /*!< Partial transfer length in case of multi packet transfer                 */\r\n}USB_OTG_EPTypeDef;\r\n\r\ntypedef struct\r\n{\r\n  uint8_t   dev_addr ;     /*!< USB device address.\r\n                                This parameter must be a number between Min_Data = 1 and Max_Data = 255    */\r\n\r\n  uint8_t   ch_num;        /*!< Host channel number.\r\n                                This parameter must be a number between Min_Data = 1 and Max_Data = 15     */\r\n\r\n  uint8_t   ep_num;        /*!< Endpoint number.\r\n                                This parameter must be a number between Min_Data = 1 and Max_Data = 15     */\r\n\r\n  uint8_t   ep_is_in;      /*!< Endpoint direction\r\n                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */\r\n\r\n  uint8_t   speed;         /*!< USB Host speed.\r\n                                This parameter can be any value of @ref USB_Core_Speed_                    */\r\n\r\n  uint8_t   do_ping;       /*!< Enable or disable the use of the PING protocol for HS mode.                */\r\n\r\n  uint8_t   process_ping;  /*!< Execute the PING protocol for HS mode.                                     */\r\n\r\n  uint8_t   ep_type;       /*!< Endpoint Type.\r\n                                This parameter can be any value of @ref USB_EP_Type_                       */\r\n\r\n  uint16_t  max_packet;    /*!< Endpoint Max packet size.\r\n                                This parameter must be a number between Min_Data = 0 and Max_Data = 64KB   */\r\n\r\n  uint8_t   data_pid;      /*!< Initial data PID.\r\n                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */\r\n\r\n  uint8_t   *xfer_buff;    /*!< Pointer to transfer buffer.                                                */\r\n\r\n  uint32_t  xfer_len;      /*!< Current transfer length.                                                   */\r\n\r\n  uint32_t  xfer_count;    /*!< Partial transfer length in case of multi packet transfer.                  */\r\n\r\n  uint8_t   toggle_in;     /*!< IN transfer current toggle flag.\r\n                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */\r\n\r\n  uint8_t   toggle_out;    /*!< OUT transfer current toggle flag\r\n                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */\r\n\r\n  uint32_t  dma_addr;      /*!< 32 bits aligned transfer buffer address.                                   */\r\n\r\n  uint32_t  ErrCnt;        /*!< Host channel error count.*/\r\n\r\n  USB_OTG_URBStateTypeDef  urb_state;  /*!< URB state.\r\n                                           This parameter can be any value of @ref USB_OTG_URBStateTypeDef */\r\n\r\n  USB_OTG_HCStateTypeDef   state;     /*!< Host Channel state.\r\n                                           This parameter can be any value of @ref USB_OTG_HCStateTypeDef  */\r\n}USB_OTG_HCTypeDef;\r\n#endif /* defined USB_OTG_FS || USB_OTG_HS */\r\n\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup PCD_Exported_Constants PCD Exported Constants\r\n  * @{\r\n  */\r\n\r\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\r\n/** @defgroup USB_Core_Mode_ USB Core Mode\r\n  * @{\r\n  */\r\n#define USB_OTG_MODE_DEVICE                    0U\r\n#define USB_OTG_MODE_HOST                      1U\r\n#define USB_OTG_MODE_DRD                       2U\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed\r\n  * @{\r\n  */\r\n#define USB_OTG_SPEED_HIGH                     0U\r\n#define USB_OTG_SPEED_HIGH_IN_FULL             1U\r\n#define USB_OTG_SPEED_LOW                      2U\r\n#define USB_OTG_SPEED_FULL                     3U\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY\r\n  * @{\r\n  */\r\n#define USB_OTG_ULPI_PHY                       1U\r\n#define USB_OTG_EMBEDDED_PHY                   2U\r\n#define USB_OTG_HS_EMBEDDED_PHY                3U\r\n\r\n#if !defined  (USB_HS_PHYC_TUNE_VALUE)\r\n  #define USB_HS_PHYC_TUNE_VALUE    0x00000F13U /*!< Value of USB HS PHY Tune */\r\n#endif /* USB_HS_PHYC_TUNE_VALUE */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS\r\n  * @{\r\n  */\r\n#define USB_OTG_HS_MAX_PACKET_SIZE             512U\r\n#define USB_OTG_FS_MAX_PACKET_SIZE             64U\r\n#define USB_OTG_MAX_EP0_SIZE                   64U\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency\r\n  * @{\r\n  */\r\n#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ     (0U << 1)\r\n#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ     (1U << 1)\r\n#define DSTS_ENUMSPD_LS_PHY_6MHZ               (2U << 1)\r\n#define DSTS_ENUMSPD_FS_PHY_48MHZ              (3U << 1)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval\r\n  * @{\r\n  */\r\n#define DCFG_FRAME_INTERVAL_80                 0U\r\n#define DCFG_FRAME_INTERVAL_85                 1U\r\n#define DCFG_FRAME_INTERVAL_90                 2U\r\n#define DCFG_FRAME_INTERVAL_95                 3U\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS\r\n  * @{\r\n  */\r\n#define DEP0CTL_MPS_64                         0U\r\n#define DEP0CTL_MPS_32                         1U\r\n#define DEP0CTL_MPS_16                         2U\r\n#define DEP0CTL_MPS_8                          3U\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed\r\n  * @{\r\n  */\r\n#define EP_SPEED_LOW                           0U\r\n#define EP_SPEED_FULL                          1U\r\n#define EP_SPEED_HIGH                          2U\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USB_LL_EP_Type USB Low Layer EP Type\r\n  * @{\r\n  */\r\n#define EP_TYPE_CTRL                           0U\r\n#define EP_TYPE_ISOC                           1U\r\n#define EP_TYPE_BULK                           2U\r\n#define EP_TYPE_INTR                           3U\r\n#define EP_TYPE_MSK                            3U\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines\r\n  * @{\r\n  */\r\n#define STS_GOUT_NAK                           1U\r\n#define STS_DATA_UPDT                          2U\r\n#define STS_XFER_COMP                          3U\r\n#define STS_SETUP_COMP                         4U\r\n#define STS_SETUP_UPDT                         6U\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines\r\n  * @{\r\n  */\r\n#define HCFG_30_60_MHZ                         0U\r\n#define HCFG_48_MHZ                            1U\r\n#define HCFG_6_MHZ                             2U\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines\r\n  * @{\r\n  */\r\n#define HPRT0_PRTSPD_HIGH_SPEED                0U\r\n#define HPRT0_PRTSPD_FULL_SPEED                1U\r\n#define HPRT0_PRTSPD_LOW_SPEED                 2U\r\n/**\r\n  * @}\r\n  */\r\n\r\n#define HCCHAR_CTRL                            0U\r\n#define HCCHAR_ISOC                            1U\r\n#define HCCHAR_BULK                            2U\r\n#define HCCHAR_INTR                            3U\r\n\r\n#define HC_PID_DATA0                           0U\r\n#define HC_PID_DATA2                           1U\r\n#define HC_PID_DATA1                           2U\r\n#define HC_PID_SETUP                           3U\r\n\r\n#define GRXSTS_PKTSTS_IN                       2U\r\n#define GRXSTS_PKTSTS_IN_XFER_COMP             3U\r\n#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR          5U\r\n#define GRXSTS_PKTSTS_CH_HALTED                7U\r\n\r\n#define USBx_PCGCCTL    *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE)\r\n#define USBx_HPRT0      *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE)\r\n\r\n#define USBx_DEVICE     ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE))\r\n#define USBx_INEP(i)    ((USB_OTG_INEndpointTypeDef *)(USBx_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))\r\n#define USBx_OUTEP(i)   ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))\r\n#define USBx_DFIFO(i)   *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))\r\n\r\n#define USBx_HOST       ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE))\r\n#define USBx_HC(i)      ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE)))\r\n#define USBPHYC         ((USBPHYC_GlobalTypeDef *)((uint32_t )USB_PHY_HS_CONTROLLER_BASE))\r\n#endif /* USB_OTG_FS || USB_OTG_HS */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros\r\n  * @{\r\n  */\r\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\r\n#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)     ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))\r\n#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)   ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))\r\n\r\n#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__)          (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))\r\n#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__)         (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))\r\n#endif /* USB_OTG_FS || USB_OTG_HS */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions\r\n  * @{\r\n  */\r\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\r\nHAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);\r\nHAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);\r\nHAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);\r\nHAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);\r\nHAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode);\r\nHAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed);\r\nHAL_StatusTypeDef USB_FlushRxFifo (USB_OTG_GlobalTypeDef *USBx);\r\nHAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num);\r\nHAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);\r\nHAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);\r\nHAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);\r\nHAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);\r\nHAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);\r\nHAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);\r\nHAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma);\r\nvoid *            USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);\r\nHAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);\r\nHAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);\r\nHAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address);\r\nHAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx);\r\nHAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx);\r\nHAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);\r\nHAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx);\r\nHAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup);\r\nuint8_t           USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);\r\nuint32_t          USB_GetMode(USB_OTG_GlobalTypeDef *USBx);\r\nuint32_t          USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx);\r\nuint32_t          USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx);\r\nuint32_t          USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);\r\nuint32_t          USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx);\r\nuint32_t          USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);\r\nvoid              USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);\r\n\r\nHAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);\r\nHAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq);\r\nHAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);\r\nHAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state);\r\nuint32_t          USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx);\r\nuint32_t          USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx);\r\nHAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,\r\n                              uint8_t ch_num,\r\n                              uint8_t epnum,\r\n                              uint8_t dev_address,\r\n                              uint8_t speed,\r\n                              uint8_t ep_type,\r\n                              uint16_t mps);\r\nHAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma);\r\nuint32_t          USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx);\r\nHAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num);\r\nHAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num);\r\nHAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);\r\nHAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);\r\nHAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);\r\n#endif /* USB_OTG_FS || USB_OTG_HS */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n\r\n#endif /* __STM32F7xx_LL_USB_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
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mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:\"\"; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:\"Times New Roman\",\"serif\";} </style> <![endif]--><!--[if gte mso 9]><xml> <o:shapedefaults v:ext=\"edit\" spidmax=\"7170\"/> </xml><![endif]--><!--[if gte mso 9]><xml> <o:shapelayout v:ext=\"edit\"> <o:idmap v:ext=\"edit\" data=\"1\"/> </o:shapelayout></xml><![endif]-->\r\n<meta content=\"MCD Application Team\" name=\"author\"></head>\r\n<body link=\"blue\" vlink=\"blue\">\r\n<div class=\"WordSection1\">\r\n<p class=\"MsoNormal\"><span style=\"font-family: &quot;Arial&quot;,&quot;sans-serif&quot;;\"><o:p>&nbsp;</o:p></span></p>\r\n<div align=\"center\">\r\n<table class=\"MsoNormalTable\" style=\"width: 675pt;\" border=\"0\" cellpadding=\"0\" cellspacing=\"0\" width=\"900\">\r\n<tbody>\r\n<tr style=\"\">\r\n<td style=\"padding: 0in;\" valign=\"top\">\r\n<table class=\"MsoNormalTable\" style=\"width: 675pt;\" border=\"0\" cellpadding=\"0\" cellspacing=\"0\" width=\"900\">\r\n<tbody>\r\n<tr style=\"\">\r\n<td style=\"padding: 0in 5.4pt;\" valign=\"top\">\r\n<p class=\"MsoNormal\"><span style=\"font-size: 8pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: blue;\"><a href=\"../../Release_Notes.html\">Back to Release page</a></span><span style=\"font-size: 10pt;\"><o:p></o:p></span></p>\r\n</td>\r\n</tr>\r\n<tr style=\"\">\r\n<td style=\"padding: 1.5pt;\">\r\n<h1 style=\"margin-bottom: 0.25in; text-align: center;\" align=\"center\"><span style=\"font-size: 20pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: rgb(51, 102, 255);\">Release\r\nNotes for STM32F7xx HAL Drivers</span><span style=\"font-size: 20pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\"><o:p></o:p></span></h1>\r\n<p class=\"MsoNormal\" style=\"text-align: center;\" align=\"center\"><span style=\"font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;\">Copyright\r\n2017 STMicroelectronics</span><span style=\"color: black;\"><u1:p></u1:p><o:p></o:p></span></p>\r\n<p class=\"MsoNormal\" style=\"text-align: center;\" align=\"center\"><span style=\"font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;\"><img style=\"border: 0px solid ; width: 171px; height: 126px;\" alt=\"\" id=\"_x0000_i1026\" src=\"../../_htmresc/st_logo.png\"></span><span style=\"font-size: 10pt;\"><o:p></o:p></span></p>\r\n</td>\r\n</tr>\r\n</tbody>\r\n</table>\r\n<p class=\"MsoNormal\"><span style=\"font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; display: none;\"><o:p>&nbsp;</o:p></span><span lang=\"fr\"><font face=\"Arial\">The&nbsp;hardware\r\nabstraction layer (HAL) provides low level drivers and the hardware\r\ninterfacing methods to interact with upper layer (application,\r\nlibraries and stacks). &nbsp;It includes a complete set of ready-to-use\r\nAPIs, that are feature-oriented instead of IP-Oriented to simplify user\r\napplication development.</font> </span></p>\r\n<table class=\"MsoNormalTable\" style=\"width: 675pt;\" border=\"0\" cellpadding=\"0\" width=\"900\">\r\n<tbody>\r\n<tr style=\"\">\r\n<td style=\"padding: 0in;\" valign=\"top\">\r\n<h2 style=\"background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;\"><a name=\"History\"></a><span style=\"font-size: 12pt; color: white;\">Update History</span></h2><h3 style=\"background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 241px;\"><span style=\"font-size: 10pt; font-family: Arial; color: white;\">V1.2.6 / 29-June-2018</span></h3><p class=\"MsoNormal\" style=\"margin: 4.5pt 0cm 4.5pt 18pt; font-size: medium; font-family: &quot;Times New Roman&quot;,serif; color: rgb(0, 0, 0); font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;\"><b><u><span style=\"font-size: 10pt; font-family: Verdana; color: black;\">Main Changes</span></u></b></p><ul style=\"margin-bottom: 0in; color: rgb(0, 0, 0); font-family: &quot;Times New Roman&quot;; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; line-height: normal; margin-top: 0cm;\" type=\"square\"><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update to support STM32F730xx and STM32F750xx value lines</span></li><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL DMA<span>&nbsp;</span></span>update</span></li><ul style=\"margin-bottom: 0in;\"><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">DMA_CHANNEL_8 to DMA_CHANNEL_15 are also defined in case of&nbsp;</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">STM32F730xx (</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">same&nbsp;features as STM32F733xx line</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">)</span></li></ul><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL FLASH<span>&nbsp;</span></span>update</span></li><ul style=\"margin-bottom: 0in;\"><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add support of<span>&nbsp;</span></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">STM32F730xx with 4 FLash sectors of 16KB each</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">.</span></li><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add support of<span>&nbsp;</span></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">STM32F750xx with 2 FLash sectors of 32KB each</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">.</span></li></ul><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL GPIO<span>&nbsp;</span></span>update</span></li><ul style=\"margin-bottom: 0in;\"><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add support of&nbsp;</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">STM32F730xx value line : same&nbsp;features as STM32F733xx line</span></li><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add support of&nbsp;</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">STM32F750xx value line : same&nbsp;features as STM32F756xx&nbsp;</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">line</span></li></ul><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL RCC<span>&nbsp;</span></span>update</span></li><ul style=\"margin-bottom: 0in;\"><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add support of&nbsp;</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">STM32F730xx value line : same&nbsp;features as STM32F733xx&nbsp;</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">line</span></li><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add support of&nbsp;</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">STM32F750xx value line : same&nbsp;features as STM32F756xx&nbsp;</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">line</span></li></ul></ul><h3 style=\"background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 241px;\"><span style=\"font-size: 10pt; font-family: Arial; color: white;\">V1.2.5 / 02-February-2018</span></h3>\r\n<p class=\"MsoNormal\" style=\"margin: 4.5pt 0cm 4.5pt 18pt;\"><b style=\"\"><u><span style=\"font-size: 10pt; font-family: Verdana; color: black;\">Main\r\nChanges</span></u></b></p><ul style=\"margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;\" type=\"square\"><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">General updates to fix known defects and enhancements implementation</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL&nbsp;</span>update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Add new macro to get variable aligned on 32-bytes, required for cache maintenance purpose</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update UNUSED() macro implementation to avoid GCC warning</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">The warning is detected when the UNUSED() macro is called from C++ file</span></li></ul></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL SAI </span>update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update HAL_SAI_DMAStop() and HAL_SAI_Abort() process to fix the lock/unlock audio issue </span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL PWR </span>update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update\r\nHAL_PWR_EnterSLEEPMode() and HAL_PWR_EnterSTOPMode() APIs to ensure\r\nthat all instructions finished before entering STOP mode. </span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL HCD </span>update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Add new callback to be used to handle usb device connection/disconnection</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">HAL_HCD_PortEnabled_Callback()</span></li></ul><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">HAL_HCD_PortDisabled_Callback()</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update to prevent reactivate host interrrupt channel<br></span></li></ul></ul><h3 style=\"background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 241px;\"><span style=\"font-size: 10pt; font-family: Arial; color: white;\">V1.2.4 / 22-December-2017</span></h3>\r\n<p class=\"MsoNormal\" style=\"margin: 4.5pt 0cm 4.5pt 18pt;\"><b style=\"\"><u><span style=\"font-size: 10pt; font-family: Verdana; color: black;\">Main\r\nChanges</span></u></b></p><ul style=\"margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;\" type=\"square\"><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">General updates to fix known defects and enhancements implementation</span></li><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-weight: bold;\">The following changes done on the HAL drivers require an update on the application code based on older HAL versions</span></span></li><ul style=\"margin-bottom: 0in;\"><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black; font-weight: bold;\"><span style=\"font-size: 10pt; font-family: Verdana;\">Rework of HAL CAN driver (compatibility break)&nbsp;</span></li><ul style=\"margin-bottom: 0in;\"><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-size: 10pt; font-family: Verdana;\">A\r\nnew HAL CAN driver has been redesigned with new APIs, to bypass\r\nlimitations on CAN Tx/Rx FIFO management present with previous HAL CAN\r\ndriver version.</span></li><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-size: 10pt; font-family: Verdana;\">The\r\nnew HAL CAN driver is the recommended version. It is located as usual\r\nin Drivers/STM32F7xx_HAL_Driver/Src and\r\nDrivers/STM32f7xx_HAL_Driver/Inc folders. It can be enabled through\r\nswitch HAL_CAN_MODULE_ENABLED in stm32f7xx_hal_conf.h</span></li><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-size: 10pt; font-family: Verdana;\">The\r\nlegacy HAL CAN driver is also present in the release in\r\nDrivers/STM32F7xx_HAL_Driver/Src/Legacy and\r\nDrivers/STM32F7xx_HAL_Driver/Inc/Legacy folders for software\r\ncompatibility reasons. Its usage is not recommended as deprecated.&nbsp;It\r\ncan however be enabled through switch HAL_CAN_LEGACY_MODULE_ENABLED in\r\nstm32f7xx_hal_conf.h</span></li></ul></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL&nbsp;</span>update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update HAL driver to allow user to change systick period to 1ms , 10 ms or 100 ms :</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Add the following API's :&nbsp;&nbsp;</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">HAL_GetTickPrio() : Returns a tick priority.</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">HAL_SetTickFreq() : Sets new tick&nbsp;</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">frequency.</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">HAL_GetTickFreq() : Returns tick frequency.</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Add HAL_TickFreqTypeDef enumeration for the different Tick Frequencies : 10 Hz , 100 Hz and 1KHz (default).</span></li></ul></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL CAN </span>update</span></li><ul><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\">Fields of CAN_InitTypeDef structure are reworked:</span></li><ul><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-size: 10pt; font-family: Verdana;\">SJW\r\nto SyncJumpWidth, BS1 to TimeSeg1, BS2 to TimeSeg2, TTCM to\r\nTimeTriggeredMode, ABOM to AutoBusOff, AWUM to AutoWakeUp, NART to\r\nAutoRetransmission (inversed), RFLM to ReceiveFifoLocked and TXFP to\r\nTransmitFifoPriority</span></li></ul><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_CAN_Init() is split into both HAL_CAN_Init() and HAL_CAN_Start() API's</span></li><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_CAN_Transmit()\r\nis replaced by HAL_CAN_AddTxMessage() to place Tx Request, then\r\nHAL_CAN_GetTxMailboxesFreeLevel() for polling until completion.</span></li><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_CAN_Transmit_IT()\r\nis replaced by HAL_CAN_ActivateNotification() to enable transmit IT, then\r\nHAL_CAN_</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\">AddTxMessage</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\">() for place Tx request.</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span></li><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_CAN_Receive()\r\nis replaced by HAL_CAN_GetRxFifoFillLevel() for polling until\r\nreception, then HAL_CAN_GetRxMessage() <br>to get Rx message.</span></li><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_CAN_Receive_IT()\r\nis replaced by HAL_CAN_</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\">ActivateNotification</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\">()&nbsp;</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\">to enable receive IT, then\r\nHAL_CAN</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\">_GetRxMessage()<br></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\"> in the receivecallback to get Rx message</span></li><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_CAN_Slepp() is renamed as HAL_CAN_RequestSleep()</span></li><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_CAN_TxCpltCallback() is split into HAL_CAN_TxMailbox0CompleteCallback(), </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_CAN_TxMailbox1CompleteCallback() and&nbsp;</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_CAN_TxMailbox2CompleteCallback().</span></li><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_CAN_RxCpltCallback is split into HAL_CAN_RxFifo0MsgPendingCallback() and </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_CAN_RxFifo1MsgPendingCallback().</span></li></ul><ul><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\">More complete \"How to use the new driver\" is detailed in the driver header section itself.</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><b><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">HAL RCC&nbsp;</span></b><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">update</span><span style=\"font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif;\" lang=\"EN-US\"><o:p></o:p></span></li><ul style=\"margin-top: 0cm;\" type=\"square\"><ul style=\"margin-top: 0cm;\" type=\"square\"><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">Add new LL macro </span><span style=\"font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif;\" lang=\"EN-US\"><o:p></o:p></span></li><ul style=\"margin-top: 0cm;\" type=\"square\"><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">LL_RCC_PLL_SetMainSource()\r\n        allowing to configure PLL clock source</span><span style=\"font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif;\" lang=\"EN-US\"><o:p></o:p></span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">Add new HAL macros</span><span style=\"font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif;\" lang=\"EN-US\"><o:p></o:p></span></li><ul style=\"margin-top: 0cm;\" type=\"square\"><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">__HAL_RCC_GET_RTC_SOURCE()\r\n        allowing to get the RTC clock source<o:p></o:p></span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">__HAL_RCC_GET_RTC_HSE_PRESCALER()\r\n        allowing to get the HSE clock divider for RTC peripheral<o:p></o:p></span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">Ensure reset of CIR and CSR\r\n       registers when issuing HAL_RCC_DeInit()/LL_RCC_DeInit functions<o:p></o:p></span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">Update HAL_RCC_GetSysClockFreq()\r\n       to avoid risk of rounding error which may leads to a wrong returned\r\n       value.</span><span style=\"font-size: 7pt; font-family: &quot;Times New Roman&quot;,serif;\" lang=\"EN-US\">&nbsp;</span><span style=\"font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif;\" lang=\"EN-US\"><o:p></o:p></span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">Update HAL_RCC_DeInit()\r\n       &nbsp;and LL_RCC_DeInit() APIs to</span><span style=\"font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif;\" lang=\"EN-US\"><o:p></o:p></span></li><ul style=\"margin-top: 0cm;\" type=\"square\"><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">Be able to return HAL/LL\r\n        status</span><span style=\"font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif;\" lang=\"EN-US\"><o:p></o:p></span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">Add checks for HSI, PLL and\r\n        PLLI2S &nbsp;ready before modifying RCC CFGR registers</span><span style=\"font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif;\" lang=\"EN-US\"><o:p></o:p></span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">Clear all interrupt flags</span><span style=\"font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif;\" lang=\"EN-US\"><o:p></o:p></span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">Initialize systick interrupt\r\n        period</span></li></ul></ul></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><b><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">HAL DMA </span></b><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span lang=\"fr\"><font face=\"Courier New\" size=\"2\"></font></span><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">Add clean of callbacks in HAL_DMA_DeInit()&nbsp;API</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">Fix wrong DMA_FLAG_FEIFO_4 and DMA_FLAGDMAEIFO_4 defines values&nbsp;</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><b><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">HAL I2C </span></b><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">update</span></li><ul><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-size: 10pt; font-family: Verdana,sans-serif;\" lang=\"EN-US\">Update Interface APIs headers to remove confusing message about device address</span><span style=\"font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif;\" lang=\"EN-US\"><o:p></o:p></span></li><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-size: 10pt; font-family: Verdana,sans-serif;\" lang=\"EN-US\">Update </span><span style=\"font-size: 10pt; font-family: Verdana,sans-serif;\" lang=\"EN-US\">I2C_WaitOnRXNEFlagUntilTimeout() to resolve a race condition between STOPF and RXNE Flags</span><span style=\"font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif;\" lang=\"EN-US\"><o:p></o:p></span></li><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-size: 10pt; font-family: Verdana,sans-serif;\" lang=\"EN-US\">Update&nbsp;I2C_TransferConfig() to fix wrong bit management</span></li></ul><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-weight: bold;\">LL USART<span>&nbsp;</span></span>update</span></li><ul style=\"margin-bottom: 0in;\"><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add assert macros to check USART BaudRate register</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><b><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">HAL ETH </span></b><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">Do{..} While(0)&nbsp;</span><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">insured </span><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">in&nbsp;</span><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">multi statement macros</span><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\"> :</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">__HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER()&nbsp;</span><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\"></span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">__HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER()</span><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\"> <br></span><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\"></span></li></ul></ul><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL FLASH<span>&nbsp;</span></span>update</span></li><ul style=\"margin-bottom: 0in;\"><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_FLASH_Unlock() update to return state error when the FLASH is already unlocked</span></li></ul><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL GPIO<span> </span></span>update</span></li><ul><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add missing define of GPIO_PIN_2 in GPIOK_PIN_AVAILABLE list</span></li></ul><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL PCD<span> </span></span>update</span></li><ul><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">Do{..} While(0) &nbsp;insured in multi statement macros</span></li></ul><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-weight: bold;\">LL UTILS<span> </span></span>update</span></li><ul style=\"margin-bottom: 0in;\"><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\">stm32f7xx_</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">ll_utils.h : Update LL_GetPackageType command to return uint32_t instead of uint16_t</span></li></ul><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL TIM<span> </span></span>update</span></li><ul><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\">stm32f7xx_hal_tim_ex.c : Update HAL_TIMEx_ConfigBreakDeadTime API to avoid to block timer behavior when <br>remains in the state HAL_TIM_STATE_BUSY.</span></li><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\">&nbsp;</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\">stm32f7xx_hal_tim.h :&nbsp;</span></li><ul><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\">Fix __HAL_TIM_SET_PRESCALER() macro</span></li><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\">Fix typos in some exported macros description&nbsp;</span></li></ul></ul><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-weight: bold;\">LL FMC<span> </span></span>update</span></li><ul style=\"margin-bottom: 0in;\"><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_SDRAM_SendCommand() API: </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Remove the&nbsp;timeout</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"> check</span></li></ul><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL NAND<span> </span></span>update</span></li><ul><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: &quot;Times New Roman&quot;,serif; color: black;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">Fix wrong check for NAND status</span></li></ul></ul>\r\n<h3 style=\"background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;\"><span style=\"font-size: 10pt; font-family: Arial; color: white;\">V1.2.3 / 25-August-2017</span></h3>\r\n<p class=\"MsoNormal\" style=\"margin: 4.5pt 0cm 4.5pt 18pt;\"><b style=\"\"><u><span style=\"font-size: 10pt; font-family: Verdana; color: black;\">Main\r\nChanges</span></u></b></p><ul style=\"margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;\" type=\"square\"><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">General updates \r\nto fix known defects and enhancements implementation</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Remove Date and Version from header files</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update HAL drivers to refer to the new&nbsp;CMSIS bit position defines instead of usage the </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">POSITION_VAL() macro</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL CAN </span>update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">Add missing unlock in HAL_CAN_Receive_IT() process</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL DCMI </span>update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">HAL DCMI driver clean-up: remove non referenced callback APIs: HAL_DCMI_VsyncCallback() and HAL_DCMI_HsyncCallback()</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL&nbsp;DFSDM </span>update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">Fix cast issue on APIs that return signed integer value (uint32_t)&nbsp;</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL DMA </span>update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">HAL DMA driver clean-up: remove non referenced callback APIs: HAL_DMA_CleanCallbacks()</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL FLASH </span>update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">FLASH_Program_DoubleWord() API: Replace 64-bit accesses with 2 double words operations</span></li></ul></ul><ul style=\"margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;\" type=\"square\"><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL Generic </span>update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">Update assert_param() macro definition to be in line with stm32_ll_utils.c driver</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL GPIO </span>update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">GPIOK_PIN_AVAILABLE() assert macro update to allow possibility to configure GPIO_PIN_2</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL LTDC </span>update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">Rename HAL_LTDC_LineEvenCallback() API to&nbsp;</span><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">HAL_LTDC_LineEven<span style=\"font-weight: bold;\">t</span>Callback()</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL PCD </span>update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">Update HAL_PCD_IRQHandler() API to fix&nbsp;transfer issues when </span><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">USB HS is used with DMA&nbsp;enabled</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL RCC </span>update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">Update HAL_RCC_GetOscConfig() API to:</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">set PLLR in the RCC_OscInitStruct</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">check on null pointer<br></span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">Update HAL_RCC_ClockConfig() API to:</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">check on null pointer</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">optimize&nbsp;code size by updating the handling method of the SWS bits</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">update\r\nto use&nbsp; __HAL_FLASH_GET_LATENCY() flash macro instead of using\r\ndirect register access to&nbsp;LATENCY bits in FLASH ACR register</span><span lang=\"fr\">. </span></li></ul></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL SAI </span>update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">Update HAL_SAI_DMAStop() API to flush fifo after disabling&nbsp;SAI</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL TIM </span>update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update HAL_TIMEx_ConfigBreakInput() API to&nbsp;support BKINP/BKIN2P polarity bits.<br></span></li></ul></ul><ul style=\"margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;\" type=\"square\"><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">LL DMA </span>update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">Update\r\nSET_BIT() access to LIFCR and HIFCR registers by WRITE_REG() to avoid\r\nread access that is not allowed when clearing DMA flags</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">LL I2C </span>update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">Update LL_I2C_Init() API to avoid enabling own address1 when OwnAddress1 parameter value in the I2C_InitStruct is equal to 0.</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">LL TIM </span>update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">Update LL_TIM_EnableUpdateEvent() API to clear UDIS bit in CR1 register instead of setting it.</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">Update LL_TIM_DisableUpdateEvent() API </span><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">to set UDIS bit in CR1 register instead of clearing it.</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">LL USB </span>update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">Update USB_EP0StartXfer() API to fix&nbsp;transfer issues when </span><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">USB HS is used with DMA&nbsp;enabled</span></li></ul></ul><h3 style=\"background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;\"><span style=\"font-size: 10pt; font-family: Arial; color: white;\">V1.2.2 / 14-April-2017</span></h3>\r\n<p class=\"MsoNormal\" style=\"margin: 4.5pt 0cm 4.5pt 18pt;\"><b style=\"\"><u><span style=\"font-size: 10pt; font-family: Verdana; color: black;\">Main\r\nChanges</span></u></b></p><ul style=\"margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;\" type=\"square\"><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">General updates \r\nto fix known defects and enhancements implementation</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL CAN </span>update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">Add\r\n      management of&nbsp;overrun error.&nbsp;</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">Allow\r\n      possibility to receive messages from the 2 RX FIFOs in parallel via\r\n      interrupt.</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">Fix&nbsp;message\r\n      lost issue with specific sequence of transmit requests.</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">Handle\r\n      transmission failure with error callback, when NART is enabled.</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif; color: black;\" lang=\"EN-US\">Add __HAL_CAN_CANCEL_TRANSMIT() call to abort transmission when\r\n      timeout is reached</span></li></ul></ul><h3 style=\"background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;\"><span style=\"font-size: 10pt; font-family: Arial; color: white;\">V1.2.1 / 24-March-2017</span></h3>\r\n<p class=\"MsoNormal\" style=\"margin: 4.5pt 0cm 4.5pt 18pt;\"><b style=\"\"><u><span style=\"font-size: 10pt; font-family: Verdana; color: black;\">Main\r\nChanges</span></u></b></p><ul style=\"margin-top: 0cm;\" type=\"square\"><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"color: rgb(0, 0, 0); font-family: Verdana; font-size: 13.3333px; font-style: normal; font-variant: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;\">Update CHM UserManuals to support LL drivers</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">General updates \r\nto fix known defects and enhancements implementation</span></li></ul><ul style=\"margin-top: 0cm;\" type=\"square\"><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL DMA </span>update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update HAL_DMA_Init() function to adjust the compatibility check between FIFO threshold and burst configuration</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL MMC </span>update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update HAL_MMC_InitCard() function with proper initialization sequence adding a delay after MMC clock enable</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update MMC_DMAError() function ignore DMA FIFO error as not impacting the data transfer</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL SD </span>update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update HAL_SD_InitCard() function with proper initialization sequence adding a delay after SD clock enable</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update SD_DMAError() function ignore DMA FIFO error as not impacting the data transfer<br></span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL NAND </span>update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update HAL_NAND_Address_Inc() function implementation for proper plane number check</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\"></span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">LL SDMMC </span>update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update SDMMC_DATATIMEOUT value with appropriate value needed by reading and writing operations of SD and MMC cards</span><span style=\"font-size: 10pt; font-family: 'Segoe UI'; color: rgb(0, 0, 0); direction: ltr;\" dir=\"ltr\"></span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">LL RTC </span>update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">LL_RTC_TIME_Get() and LL_RTC_DATE_Get() inline macros optimization</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">LL ADC </span>update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Fix wrong ADC group injected sequence configuration</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"></span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">LL_ADC_INJ_SetSequencerRanks()\r\nand LL_ADC_INJ_GetSequencerRanks() API's update to take in\r\nconsideration the ADC number of conversions</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update the&nbsp;</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">defined values for</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"> ADC group injected seqencer ranks&nbsp;<br></span></li></ul></ul></ul><h3 style=\"background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;\"><span style=\"font-size: 10pt; font-family: Arial; color: white;\">V1.2.0 / 30-December-2016</span></h3>\r\n<p class=\"MsoNormal\" style=\"margin: 4.5pt 0cm 4.5pt 18pt;\"><b style=\"\"><u><span style=\"font-size: 10pt; font-family: Verdana; color: black;\">Main\r\nChanges</span></u></b></p><ul style=\"margin-top: 0cm;\" type=\"square\"><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Official release to add the support of <span style=\"font-weight: bold;\">STM32F722xx, STM32F723xx, STM32F732xx</span> <span style=\"font-weight: bold;\">and STM32F733xx</span> devices</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"color: rgb(0, 0, 0); font-family: Verdana; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: bold; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;\">Add Low Layer drivers allowing performance and footprint optimization</span></li><ul><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;\"><span style=\"font-size: 10pt; font-family: Verdana;\">Low\r\nLayer drivers APIs provide register level programming: require deep\r\nknowledge of peripherals described in STM32F7xx Reference Manuals</span></li><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;\"><span style=\"color: rgb(0, 0, 0); font-family: Verdana; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;\">Low\r\nLayer drivers are available for: ADC,&nbsp;Cortex, CRC, DAC, DMA,\r\nDMA2D, EXTI, GPIO, I2C, IWDG, LPTIM, PWR, RCC, RNG, RTC, SPI, TIM,\r\nUSART, WWDG peripherals and additionnal Low Level Bus, System and\r\nUtilities APIs.</span></li><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;\"><span style=\"font-size: 10pt; font-family: Verdana;\">Low Layer drivers APIs are implemented as static inline function in new<span class=\"Apple-converted-space\">&nbsp;</span><span style=\"font-style: italic;\">Inc/stm32f7xx_ll_ppp.h</span><span class=\"Apple-converted-space\">&nbsp;</span>files for PPP peripherals, there is no configuration file and each<span class=\"Apple-converted-space\">&nbsp;</span></span><span style=\"font-size: 10pt; font-family: Verdana;\"><span style=\"font-style: italic;\">stm32f7xx_ll_ppp.h</span><span class=\"Apple-converted-space\">&nbsp;</span>file must be included in user code.</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">General updates \r\nto fix known defects and enhancements implementation</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add new HAL <span style=\"font-weight: bold;\">MMC</span> and <span style=\"font-weight: bold;\">SMBUS</span> drivers</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL Cortex</span> update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Move HAL_MPU_Disable() and HAL_MPU_Enable() from stm32f7xx_hal_cortex.h to stm32f7xx_hal_cortex.c</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Clear the whole MPU control register in&nbsp;</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">HAL_MPU_Disable() API</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL CRYP</span> update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Add support of AES</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL DMA</span> update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Add a check on DMA stream instance in HAL_DMA_DeInit() API</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL ETH</span> update&nbsp;</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Fix wrong definitions in driver header file stm32f7_hal_eth.h</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL FLASH</span> update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Support OTP program operation</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Add the support of PCROP feature</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update the clearing of error flags</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL I2C</span> update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Align driver source code with other STM32 families<br></span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL JPEG</span> update&nbsp;</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update the output data management when&nbsp;HAL_JPEG_Pause() is performed during the last data sending</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL RCC </span>update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Enable PWR only if necessary for LSE configuration in HAL_RCC_OscConfig() API</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Rename RCC_LPTIM1CLKSOURCE_PCLK define to RCC_LPTIM1CLKSOURCE_PCLK1</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Rename RCC_DFSDM1CLKSOURCE_PCLK define to RCC_DFSDM1CLKSOURCE_PCLK2<br></span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL SPI</span> update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Clear RX FIFO at the end of each transaction</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL UART</span> update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Remove </span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">USART_CR2_LINEN bit </span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">clearing&nbsp;when initializing in synchronous mode</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL USB</span> update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Add support of embedded USB PHY Controller</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Add support of Battery Charging Detector (BCD) feature</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">LL SDMMC</span> update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Add new SDMMC_CmdSDEraseStartAdd, SDMMC_CmdSDEraseEndAdd, SDMMC_CmdOpCondition and SDMMC_CmdSwitch functions</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">LL USB</span> update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update PENA bit clearing in OTG_HPRT0 register</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-weight: bold;\">The following changes done on the HAL drivers require an update on the \r\napplication code based on older HAL versions</span></span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL SD</span> update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Overall rework of the driver for a more efficient&nbsp;implementation</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Modify initialization API and structures</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Modify Read / Write sequences: separate transfer process and SD Cards state management&nbsp;</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Adding interrupt mode for Read / Write operations</span></li></ul><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Update the HAL_SD_IRQHandler function by optimizing the management of interrupt errors<br></span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Refer to the following example to identify the changes: BSP example and USB_Device/MSC_Standalone application</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL TIM</span> update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Add new AutoReloadPreload field in TIM_Base_InitTypeDef structure</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Refer to the TIM examples to identify the changes</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">&nbsp;</span></span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL NAND</span> update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Modify NAND_AddressTypeDef, NAND_DeviceConfigTypeDef and NAND_HandleTypeDef structures fields</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Add new HAL_NAND_ConfigDevice API<br></span></li></ul></ul></ul><b style=\"color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: 16px; font-style: normal; font-variant: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px;\"><span style=\"font-family: Verdana; color: black; font-size: 10pt;\"></span></b><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"></span><h3 style=\"background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;\"><span style=\"font-size: 10pt; font-family: Arial; color: white;\">V1.1.1 / 01-July-2016</span></h3>\r\n<p class=\"MsoNormal\" style=\"margin: 4.5pt 0cm 4.5pt 18pt;\"><b style=\"\"><u><span style=\"font-size: 10pt; font-family: Verdana; color: black;\">Main\r\nChanges</span></u></b></p><ul style=\"margin-top: 0cm;\" type=\"square\"><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL DMA</span> update&nbsp;</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update HAL_DMA_PollForTransfer() function implementation to&nbsp;avoid early TIMEOUT error.</span> </li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL JPEG</span> update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update HAL_JPEG_ConfigEncoding() function to properly set the ImageHeight and ImageWidth</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL SPI</span> update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update SPI_DMATransmitReceiveCplt() function to properly handle the CRC and avoid conditional statement duplication<br></span></li></ul></ul><h3 style=\"background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;\"><span style=\"font-size: 10pt; font-family: Arial; color: white;\">V1.1.0 / 22-April-2016</span></h3>\r\n<p class=\"MsoNormal\" style=\"margin: 4.5pt 0cm 4.5pt 18pt;\"><b style=\"\"><u><span style=\"font-size: 10pt; font-family: Verdana; color: black;\">Main\r\nChanges</span></u></b></p><ul style=\"margin-top: 0cm;\" type=\"square\"><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Official release to add the support of <span style=\"font-weight: bold;\">STM32F765xx, STM32F767xx, STM32F768xx, STM32F769xx, STM32F777xx, STM32F778xx</span> <span style=\"font-weight: bold;\">and STM32F779xx</span> devices<br></span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">General updates \r\nto fix known defects and enhancements implementation</span></li><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;\"><span style=\"font-size: 10pt; font-family: Verdana,sans-serif;\">Add new HAL drivers for<span class=\"Apple-converted-space\"> </span><span style=\"font-weight: bold;\">DFSDM, DSI<span class=\"Apple-converted-space\">, JPEG </span></span>and<span class=\"Apple-converted-space\"> </span><span style=\"font-weight: bold;\">MDIOS<span class=\"Apple-converted-space\"> </span></span>peripherals</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Enhance HAL delay and timebase implementation</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Add new \r\ndrivers stm32f7xx_hal_timebase_tim_template.c, stm32f7xx_hal_timebase_rtc_alarm_template.c and \r\nstm32f7xx_hal_timebase_rtc_wakeup_template.c which override the native HAL time \r\nbase functions (defined as weak) to either use the TIM or the RTC as time base tick source. For \r\nmore details about the usage of these drivers, please refer to HAL\\HAL_TimeBase \r\nexamples&nbsp;</span><span style=\"color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;\">and FreeRTOS-based applications</span></li></ul></ul><ul style=\"margin-top: 0cm;\" type=\"square\"><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-weight: bold;\">The following changes done on the HAL drivers require an update on the \r\napplication code based on HAL V1.0.4</span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"></span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\">HAL UART, USART, IRDA, SMARTCARD, SPI, I2C,&nbsp;QSPI </span></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\"></span>(referenced as <span style=\"font-style: italic;\">PPP</span> here below)<span style=\"font-style: italic;\"></span></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\"> </span>drivers</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"></span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Add PPP error management during DMA process. This requires the following updates on&nbsp;</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">user application:</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Configure and enable \r\nthe PPP IRQ in HAL_PPP_MspInit() function<br></span></li></ul><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">In </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">stm32f7xx_it.c file, \r\n</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">PPP_IRQHandler() \r\nfunction: </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">add a call to \r\nHAL_PPP_IRQHandler() function</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add and customize \r\nthe Error Callback API: HAL_PPP_ErrorCallback()<br></span></li></ul></ul></ul></ul>\r\n<ul><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\">HAL I2C</span><span style=\"font-style: italic;\"></span></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\"></span> (referenced as <span style=\"font-style: italic;\">PPP</span> here below)<span style=\"font-style: italic;\"></span></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\"> </span>drivers:</span>\r\n<ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update to avoid waiting on </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">STOPF/BTF/AF flag under DMA ISR by using the </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">PPP end of transfer interrupt in the </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">DMA transfer process.</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"> This requires the following updates on&nbsp;</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">user application</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">:</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Configure and enable \r\nthe PPP IRQ in HAL_PPP_MspInit() function<br></span></li></ul></ul>\r\n<ul><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">In </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">stm32f7xx_it.c file, \r\n</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">PPP_IRQHandler() \r\nfunction: </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">add a call to \r\nHAL_PPP_IRQHandler() function</span></li></ul></ul></li></ul></ul>\r\n<ul><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\">HAL IWDG</span></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\"> </span>driver: rework overall driver for better implementation</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Remove&nbsp;</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_IWDG_Start(), </span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_IWDG_MspInit() and </span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_IWDG_GetState()&nbsp;</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">APIs</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\">HAL WWDG</span></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\"> </span>driver: rework overall driver for better implementation</span>\r\n<ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Remove HAL_WWDG_Start(), </span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_WWDG_Start_IT(),</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"> \r\nHAL_WWDG_MspDeInit() and </span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_WWDG_GetState() APIs&nbsp;</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Update the&nbsp;</span><span style=\"font-family: 'Calibri',sans-serif; font-size: 11pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Calibri',sans-serif; font-size: 11pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Calibri',sans-serif; font-size: 11pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Calibri',sans-serif; font-size: 11pt;\" lang=\"EN-US\">HAL_WWDG_Refresh</span><span style=\"font-family: 'Calibri',sans-serif; font-size: 11pt;\" lang=\"EN-US\">(WWDG_HandleTypeDef *hwwdg, uint32_t counter) &nbsp;function and API &nbsp;by removing the &nbsp;\"counter\" parameter</span><span style=\"font-family: 'Calibri',sans-serif; font-size: 11pt;\" lang=\"EN-US\"></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\"></span></span></li></ul></li></ul></ul><ul style=\"margin-top: 0cm;\" type=\"square\"><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\">HAL QSPI driver: </span>&nbsp;Enhance the DMA transmit process by&nbsp;using&nbsp;PPP TC interrupt instead of waiting on TC flag under DMA ISR.&nbsp;</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">This requires the following updates on&nbsp;</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">user application</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">:</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Configure and enable \r\nthe QSPI&nbsp;IRQ in HAL_QSPI_MspInit() function</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">In </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">stm32f7xx_it.c file, </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">QSPI_IRQHandler() \r\nfunction: </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">add a call to \r\nHAL_QSPI_IRQHandler() function</span></li></ul></ul></ul>\r\n<ul style=\"margin-bottom: 0in; list-style-type: square;\"><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\"></span></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\"></span></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\">HAL CEC driver: </span>&nbsp;Overall driver rework with compatibility break versus previous HAL version</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Remove HAL CEC polling Process functions: HAL_CEC_Transmit() and HAL_CEC_Receive()</span><span style=\"font-family: 'Times New Roman',serif; font-size: 12pt;\" lang=\"EN-US\"><o:p></o:p></span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Remove\r\nHAL CEC receive interrupt process function&nbsp;HAL_CEC_Receive_IT()\r\nand enable the \"receive\" &nbsp;mode during the Init phase</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Rename&nbsp;HAL_CEC_GetReceivedFrameSize() funtion to&nbsp;HAL_CEC_GetLastReceivedFrameSize()<br></span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Add new HAL APIs: HAL_CEC_SetDeviceAddress() and  \r\nHAL_CEC_ChangeRxBuffer()</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Remove the&nbsp;<span></span>'InitiatorAddress' field from the&nbsp;CEC_InitTypeDef \r\nstructure&nbsp;and manage it&nbsp;as a parameter in the HAL_CEC_Transmit_IT() function</span><span style=\"font-family: 'Times New Roman',serif; font-size: 12pt;\" lang=\"EN-US\"><o:p></o:p></span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Add new parameter 'RxFrameSize' in HAL_CEC_RxCpltCallback() function</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Move CEC Rx buffer pointer&nbsp;from CEC_HandleTypeDef structure to \r\nCEC_InitTypeDef structure</span></li></ul></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL CAN</span> update&nbsp;</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Add the support of CAN3</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL CEC</span> update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Overall driver rework with&nbsp;break of compatibility with HAL \r\nV1.0.4<br></span></li></ul><ul><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Remove the HAL CEC polling Process: HAL_CEC_Transmit() and HAL_CEC_Receive()</span><span style=\"font-family: 'Times New Roman',serif; font-size: 12pt;\" lang=\"EN-US\"><o:p></o:p></span></li></ul></ul></ul>\r\n<ul style=\"margin-top: 0cm;\" type=\"disc\"><ul style=\"margin-top: 0cm;\" type=\"circle\"><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Remove the HAL CEC receive interrupt process (HAL_CEC_Receive_IT()) and manage the \"Receive\" mode enable within the Init phase</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Rename HAL_CEC_GetReceivedFrameSize() function to&nbsp;HAL_CEC_GetLastReceivedFrameSize() function<br></span></li></ul><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Add new HAL APIs: HAL_CEC_SetDeviceAddress() and  \r\nHAL_CEC_ChangeRxBuffer()</span></li></ul><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Remove the&nbsp;<span></span>'InitiatorAddress' field from the&nbsp;CEC_InitTypeDef \r\nstructure&nbsp;and manage it&nbsp;as a parameter in the HAL_CEC_Transmit_IT() function</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span></li></ul><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Add new parameter 'RxFrameSize' in HAL_CEC_RxCpltCallback() function</span><span style=\"font-family: 'Times New Roman',serif; font-size: 12pt;\" lang=\"EN-US\"><o:p></o:p></span></li></ul><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Move CEC Rx buffer pointer&nbsp;from CEC_HandleTypeDef structure to \r\nCEC_InitTypeDef structure</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"> <o:p></o:p></span></li></ul></ul></ul>\r\n<ul style=\"text-transform: none; margin-top: 0cm; text-indent: 0px; letter-spacing: normal; font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; font-size: medium; line-height: normal; font-size-adjust: none; font-stretch: normal; white-space: normal; margin-bottom: 0in; color: rgb(0, 0, 0); word-spacing: 0px;\" type=\"square\"><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update driver to implement the new CEC state machine: </span></li></ul><ul><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Add new&nbsp;</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">\"rxState\"</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"> field in \r\nCEC_HandleTypeDef structure to provide the </span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">CEC \r\n</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">state \r\ninformation related to Rx Operations</span></li></ul><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Rename \"state\" \r\nfield in CEC_HandleTypeDef structure to \"gstate\": CEC </span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">state information \r\nrelated to global Handle management and Tx Operations</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update CEC process \r\nto manage the new CEC states.</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; color: black; font-size: 10pt;\" lang=\"EN-US\">Update __HAL_CEC_RESET_HANDLE_STATE() macro to handle the new CEC \r\nstate parameters (gState, rxState)</span><br></li></ul></ul></ul><ul style=\"margin-bottom: 0in; list-style-type: square;\"><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL DMA</span> update&nbsp;</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add\r\nnew APIs HAL_DMA_RegisterCallback() and HAL_DMA_UnRegisterCallback to\r\nregister/unregister the different callbacks identified by\r\nthe enum typedef HAL_DMA_CallbackIDTypeDef</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add new API HAL_DMA_Abort_IT() to abort DMA transfer under interrupt context<br></span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">The new registered Abort callback is called when DMA transfer abortion is completed</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add the check of \r\ncompatibility between FIFO threshold level and size of the memory burst in the \r\nHAL_DMA_Init() API</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add new Error Codes: \r\nHAL_DMA_ERROR_PARAM, HAL_DMA_ERROR_NO_XFER and \r\nHAL_DMA_ERROR_NOT_SUPPORTED</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Remove all DMA states \r\nrelated to MEM0/MEM1 in HAL_DMA_StateTypeDef</span><span style=\"font-family: 'Helvetica',sans-serif; color: rgb(98, 98, 98); font-size: 9.5pt;\" lang=\"EN-US\"><o:p></o:p></span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL DMA2D</span> update&nbsp;</span></li><ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update the \r\nHAL_DMA2D_DeInit() function to:</span>\r\n<ul style=\"margin-bottom: 0in;\"><li style=\"margin: 4.5pt 0in; list-style-type: square; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Abort transfer in case \r\nof ongoing DMA2D transfer</span></li></ul>\r\n<ul><li><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Reset DMA2D control \r\nregisters</span></li></ul></li><li><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update \r\nHAL_DMA2D_Abort() to disable DMA2D interrupts after stopping transfer</span></li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Optimize \r\nHAL_DMA2D_IRQHandler() by reading status registers only once</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update \r\nHAL_DMA2D_ProgramLineEvent() function to:</span>\r\n<ul style=\"margin-bottom: 0in;\"><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Return HAL error state \r\nin case of wrong line value</span></li></ul>\r\n<ul style=\"margin-bottom: 0in;\"><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Enable line interrupt \r\nafter setting the line watermark configuration</span></li></ul></li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add new HAL_DMA2D_CLUTLoad() and </span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">HAL_DMA2D_CLUTLoad_IT()</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"> \r\nfunctions to start DMA2D CLUT loading</span></li><ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_DMA2D_CLUTLoading_Abort() \r\nfunction to abort the DMA2D CLUT loading</span></li></ul><ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_DMA2D_CLUTLoading_Suspend() \r\nfunction to suspend the DMA2D CLUT loading</span></li></ul><ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_DMA2D_CLUTLoading_Resume() \r\nfunction to resume the DMA2D CLUT loading</span></li></ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add new DMA2D dead time \r\nmanagement:</span></li><ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_DMA2D_EnableDeadTime() \r\nfunction to enable DMA2D dead time feature</span></li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_DMA2D_DisableDeadTime() \r\nfunction to disable DMA2D dead time feature</span></li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_DMA2D_ConfigDeadTime() \r\nfunction to configure dead time</span></li></ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update the name of \r\nDMA2D Input/Output color mode defines to be more clear for user (DMA2D_INPUT_XXX \r\nfor input layers Colors, DMA2D_OUTPUT_XXX for output framebuffer \r\nColors)</span></li></ul></ul>\r\n\r\n<ul style=\"margin-top: 0cm;\" type=\"square\"><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL DCMI</span> update&nbsp;</span></li><ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Rename DCMI_DMAConvCplt \r\nto DCMI_DMAXferCplt</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_DCMI_Start_DMA() function to&nbsp;</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Enable the DCMI peripheral</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add new timeout \r\nimplementation based on cpu cycles for DCMI stop</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add HAL_DCMI_Suspend() \r\nfunction to suspend DCMI capture</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add HAL_DCMI_Resume() \r\nfunction to resume capture after DCMI suspend</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update lock mechanism \r\nfor DCMI process</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update HAL_DCMI_IRQHandler() function to:</span>\r\n<ul style=\"margin-bottom: 0in;\"><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add error management in \r\ncase DMA errors through XferAbortCallback() and \r\nHAL_DMA_Abort_IT()</span></li></ul>\r\n<ul style=\"margin-bottom: 0in;\"><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Optimize code by using \r\ndirect register read</span></li></ul></li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Move\r\nthe content of the stm32f7xx_hal_dcmi_ex.c/.h files to common driver\r\nfiles (the extension files are kept empty for projects compatibility\r\nreason)</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"></span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL FLASH</span> update&nbsp;</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Add the support of Dual BANK feature</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Add __HAL_FLASH_CALC_BOOT_BASE_ADR() macro to calculate the FLASH Boot Base Adress</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Move Flash total sector define to CMSIS header files</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL FMC</span> update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update FMC_NORSRAM_Init() to remove the Burst access mode configuration</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update FMC_SDRAM_Timing_Init() to fix initialization issue when configuring 2 SDRAM banks<br></span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL HCD</span> update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update HCD_Port_IRQHandler() to be compliant with new Time base implementation</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><b><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL \r\nI2C</span></b><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\"></span></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\"> </span></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">update</span>\r\n<ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Add the support of I2C fast mode plus (FM+)</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"></span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">Update </span><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">Polling management:</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">The Timeout value must be estimated for the overall process duration: the Timeout measurement is cumulative<br></span></li></ul></ul>\r\n<ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add the management of Abort service:&nbsp;Abort DMA transfer through interrupt</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">In the case of Master Abort IT transfer usage:</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add&nbsp;new user HAL_I2C_AbortCpltCallback() to inform user of the end of abort process</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">A new abort state is defined in the </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_I2C_StateTypeDef </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">structure</span></li></ul></ul></ul>\r\n<ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add the management of I2C peripheral errors, ACK\r\nfailure and STOP condition detection during DMA process. This requires the following updates\r\non user application:</span></li><ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Configure and enable the I2C IRQ in HAL_I2C_MspInit() function</span></li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">In stm32f7xx_it.c file, I2C_IRQHandler() function: add a call to HAL_I2C_IRQHandler() function</span></li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add and customize the Error Callback API: HAL_I2C_ErrorCallback()</span></li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Refer to the I2C_EEPROM or I2C_TwoBoards_ComDMA project examples usage of the API<br></span></li></ul></ul><ul><li><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Add the support of&nbsp;I2C repeated start feature:</span>\r\n<ul><li><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">With the following new APIs<br></span></li></ul>\r\n<ul><ul><li><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_I2C_Master_Sequential_Transmit_IT()</span>\r\n</li><li><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">I2C_Master_Sequential_Receive_IT()</span>\r\n</li><li><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">I2C_Master_Abort_IT()</span>\r\n</li><li><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">I2C_Slave_Sequential_Transmit_IT()</span>\r\n</li><li><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">I2C_Slave_Sequential_Receive_IT()</span>\r\n</li><li><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">I2C_EnableListen_IT()</span>\r\n</li><li><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">I2C_DisableListen_IT()</span></li></ul></ul>\r\n<ul><li><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Add new user callbacks:</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"><br></span></li></ul>\r\n<ul><ul><li><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">I2C_ListenCpltCallback()</span></li></ul><ul><li><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">I2C_AddrCallback()</span></li></ul></ul>\r\n</li><li><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Several \r\nupdates on HAL I2C driver to implement the new I2C state machine: </span>\r\n<ul><li><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Add new API to get the&nbsp;</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">I2C mode: \r\nHAL_</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">I2C_GetMode()</span>\r\n</li><li><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update&nbsp;</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">I2C process to \r\nmanage the new&nbsp;</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">I2C states</span></li></ul></li></ul>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL IWDG</span> update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Overall rework of the driver for a more efficient&nbsp;implementation</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Remove the following APIs:</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_IWDG_Start()</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_IWDG_MspInit()</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_IWDG_GetState()</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Update implementation:</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_IWDG_Init() : this function insures the configuration and the start of the IWDG counter</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_IWDG_Refresh() : this function insures the reload of the IWDG counter</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Refer to the following example to identify the changes: IWDG_Example<br></span></li></ul></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL LPTIM </span>update</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\"></span></span></li><ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\">Update </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_LPTIM_TimeOut_Start_IT() and HAL_LPTIM_Counter_Start_IT( ) APIs \r\nto configure WakeUp Timer EXTI interrupt to be able to wakeup MCU from low power \r\nmode by </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\">pressing the EXTI line </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\">Update </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_LPTIM_TimeOut_Stop_IT() and HAL_LPTIM_Counter_Stop_IT( ) APIs to \r\ndisable WakeUp Timer EXTI interrupt </span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL LTDC </span>update</span></li><ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update \r\nHAL_LTDC_IRQHandler() to manage the case of reload interrupt</span></li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Add LTDC extension driver needed with DSI</span></li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Add HAL_LTDC_SetPitch() function for pitch reconfiguration</span></li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add new callback API \r\nHAL_LTDC_ReloadEventCallback()</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add HAL_LTDC_Reload() \r\nto configure LTDC reload feature</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add new No Reload LTDC \r\nvariant APIs<br></span>\r\n<ul style=\"margin-bottom: 0in;\"><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_LTDC_ConfigLayer_NoReload() \r\nto configure the LTDC Layer according to the specified without reloading</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_LTDC_SetWindowSize_NoReload() \r\nto set the LTDC window size without reloading</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_LTDC_SetWindowPosition_NoReload() \r\nto set the LTDC window position without reloading</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_LTDC_SetPixelFormat_NoReload() \r\nto reconfigure the pixel format without reloading</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_LTDC_SetAlpha_NoReload() \r\nto reconfigure the layer alpha value without reloading</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_LTDC_SetAddress_NoReload() \r\nto reconfigure the frame buffer Address without reloading</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_LTDC_SetPitch_NoReload() \r\nto reconfigure the pitch for specific cases</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_LTDC_ConfigColorKeying_NoReload() \r\nto configure the color keying without reloading</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_LTDC_EnableColorKeying_NoReload() \r\nto enable the color keying without reloading</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_LTDC_DisableColorKeying_NoReload() \r\nto disable the color keying without reloading</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_LTDC_EnableCLUT_NoReload() \r\nto enable the color lookup table without reloading</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_LTDC_DisableCLUT_NoReload() \r\nto disable the color lookup table without \r\nreloading</span></li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"text-decoration: underline; font-style: italic;\">Note:</span>\r\nVariant functions with _NoReload post fix allows to set the LTDC\r\nconfiguration/settings without immediate reload. This is useful in case\r\nwhen the program requires to modify several LTDC settings (on one or\r\nboth layers) then applying (reload) these settings in one shot by\r\ncalling the function HAL_LTDC_Reload<br></span></li></ul></li></ul></ul>\r\n<ul style=\"margin-top: 0cm;\" type=\"square\"><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL NOR</span> update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Update NOR_ADDR_SHIFT macro implementation</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL PCD</span> update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update HAL_PCD_IRQHandler() to get HCLK frequency before setting TRDT value</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL QSPI </span>update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update to manage QSPI error management during DMA process</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Improve the DMA transmit process by using QSPI TC interrupt instead of waiting loop on TC flag under DMA ISR</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">These two improvements require the following updates on user application:</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Configure and enable the QSPI IRQ in HAL_QSPI_MspInit() function</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">In stm32f7xx_it.c file, QSPI_IRQHandler() function: add a call to HAL_QSPI_IRQHandler() function</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add and customize the Error Callback API: HAL_QSPI_ErrorCallback()</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add\r\nthe management of non-blocking transfer abort service:&nbsp;HAL_QSPI_Abort_IT(). In\r\nthis case the user must:</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add new callback HAL_QSPI_AbortCpltCallback() to inform user at the end of abort process</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">A new value of State in the HAL_QSPI_StateTypeDef provides the current state during the abort phase</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Polling management update:</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">The Timeout value user must be estimated for the overall process duration: the Timeout measurement is cumulative.&nbsp;</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Refer to the following examples, which describe the changes:</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">QSPI_ReadWrite_DMA</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">QSPI_MemoryMapped</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">QSPI_ExecuteInPlace<br></span></li></ul></ul></ul><ul style=\"margin-top: 0cm;\" type=\"square\"><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Add two new APIs for the QSPI fifo threshold:</span><span style=\"font-family: 'Times New Roman',serif; font-size: 12pt;\" lang=\"EN-US\"><o:p></o:p></span>\r\n<ul style=\"margin-top: 0cm;\" type=\"circle\"><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_QSPI_SetFifoThreshold(): configure the FIFO threshold of \r\nthe QSPI</span><span style=\"font-family: 'Times New Roman',serif; font-size: 12pt;\" lang=\"EN-US\"><o:p></o:p></span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_QSPI_GetFifoThreshold(): give the current FIFO \r\nthreshold</span><span style=\"font-family: 'Times New Roman',serif; font-size: 12pt;\" lang=\"EN-US\"><o:p></o:p></span></li></ul>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Fix wrong data size management in HAL_QSPI_Receive_DMA()</span><span style=\"font-family: 'Times New Roman',serif; font-size: 12pt;\" lang=\"EN-US\"><o:p></o:p></span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL RCC </span>update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update HAL_RCC_PeriphCLKConfig() function to adjust the SystemCoreClock</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Optimize HAL_RCC_ClockConfig() function code</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"></span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">O</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">ptimize internal oscillators and PLL startup times</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL RTC </span>update&nbsp;</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update HAL_RTC_GetTime() with proper 'SubSeconds' and 'SecondFraction' management</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL SAI </span>update&nbsp;</span></li><ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update SAI state in case of TIMEOUT error within the </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_SAI_Transmit() / HAL_SAI_Receive()</span>\r\n</li></ul><ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update HAL_SAI_IRQHandler:</span>\r\n<ul style=\"margin-bottom: 0in;\"><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add error management in \r\ncase DMA errors through XferAbortCallback() and HAL_DMA_Abort_IT()</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add error management in \r\ncase of IT</span></li></ul></li></ul><ul style=\"margin-bottom: 0in;\"><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Move\r\nSAI_BlockSynchroConfig() and SAI_GetInputClock() functions to\r\nstm32f7xx_hal_sai.c/.h files (extension files are kept empty for\r\nprojects compatibility reason)</span></li></ul></ul>\r\n<ul style=\"margin-top: 0cm;\" type=\"square\"><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL SPDIFRX </span>update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Overall driver update for wait on flag management optimization <br></span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL SPI </span>update</span><b><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span></b></li><ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Overall driver optimization to improve performance in polling/interrupt mode to reach maximum peripheral frequency</span></li><ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Polling mode:</span>\r\n</li><ul><li><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Replace the use of SPI_WaitOnFlagUnitTimeout() function by \"if\" \r\nstatement to check on RXNE/TXE flage while transferring \r\ndata</span></li></ul></ul></ul></ul>\r\n<ul style=\"margin-top: 0cm;\" type=\"square\"><ul><ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">&nbsp;Interrupt mode:</span></li><ul><li><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Minimize access on SPI registers</span>\r\n</li></ul></ul><ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">All modes:</span></li><ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add the USE_SPI_CRC switch to minimize the number of statements when CRC calculation is disabled</span></li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update&nbsp;timeout management to check on global processes</span></li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update error code management in all processes</span></li></ul></ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update DMA process:<o:p></o:p></span>\r\n<ul style=\"margin-bottom: 0in;\"><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add the management of SPI peripheral errors during DMA process. This requires the following updates in\r\nthe user application:</span></li><ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Configure and enable the SPI IRQ in HAL_SPI_MspInit() function</span></li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">In stm32f7xx_it.c file, SPI_IRQHandler() function: add a call to HAL_SPI_IRQHandler() function</span></li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add and customize the Error Callback API: HAL_SPI_ErrorCallback()</span></li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Refer to the following example which describe the changes: SPI_FullDuplex_ComDMA<br></span></li></ul></ul>\r\n</li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL TIM </span>update&nbsp;</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update HAL_TIM_ConfigOCrefClear() function for proper configuration of the SMCR register</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Add new function HAL_TIMEx_ConfigBreakInput() to configure the break input source</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><b><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL UART, USART, SMARTCARD and IRDA </span></b><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\"></span></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\"></span>(referenced as <span style=\"font-style: italic;\">PPP</span> here below)<span style=\"font-style: italic;\"></span></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\"> </span></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">update<b><o:p></o:p></b></span> \r\n</li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Update Polling management:</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">The user Timeout value&nbsp;must be estimated for the overall process duration: the Timeout measurement is cumulative</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update DMA process:</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update the m</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">anagement of PPP peripheral errors during DMA process. This requires the following updates in user application:</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Configure and enable the PPP IRQ in HAL_PPP_MspInit() function</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">In stm32f7xx_it.c file, PPP_IRQHandler() function: add a call to HAL_PPP_IRQHandler() function</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Add and customize the Error Callback API: HAL_PPP_ErrorCallback()<br></span></li></ul></ul></ul></ul><ul style=\"margin-top: 0cm;\" type=\"square\"><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL WWDG </span>update&nbsp;</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Overall rework of the driver for more efficient implementation</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Remove the following APIs:</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">HAL_WWDG_Start()</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">HAL_WWDG_Start_IT()</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">HAL_WWDG_MspDeInit()</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">HAL_WWDG_GetState()</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update implementation:</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">HAL_WWDG_Init()</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">A&nbsp;new parameter in the Init Structure:&nbsp;EWIMode</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">HAL_WWDG_MspInit()</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">HAL_WWDG_Refresh()&nbsp;</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">This function insures the reload of the counter</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">The \"counter\" parameter has been removed</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">HAL_WWDG_IRQHandler()</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">HAL_WWDG_EarlyWakeupCallback() is the new prototype of HAL_WWDG_WakeupCallback()<br></span></li></ul></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Refer to the following example to identify the changes: WWDG_Example</span></li></ul></ul><h3 style=\"background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;\"><span style=\"font-size: 10pt; font-family: Arial; color: white;\">V1.0.4 / 09-December-2015</span></h3>\r\n<p class=\"MsoNormal\" style=\"margin: 4.5pt 0cm 4.5pt 18pt;\"><b style=\"\"><u><span style=\"font-size: 10pt; font-family: Verdana; color: black;\">Main\r\nChanges</span></u></b></p><ul style=\"margin-top: 0cm;\" type=\"square\"><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL Generic </span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\">update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update HAL \r\nweak empty callbacks to prevent unused argument compilation warnings with some \r\ncompilers by calling the following line:</span>\r\n</li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">UNUSED(hppp);</span></li></ul></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL ETH</span> update&nbsp;</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update HAL_ETH_Init() function to add timeout on the Software reset management<br></span></li></ul></ul><h3 style=\"background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;\"><span style=\"font-size: 10pt; font-family: Arial; color: white;\">V1.0.3 / 13-November-2015</span></h3>\r\n<p class=\"MsoNormal\" style=\"margin: 4.5pt 0cm 4.5pt 18pt;\"><b style=\"\"><u><span style=\"font-size: 10pt; font-family: Verdana; color: black;\">Main\r\nChanges</span></u></b></p><ul style=\"margin-top: 0cm;\" type=\"square\"><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">General updates \r\nto fix known defects and enhancements implementation</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\"></span></span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-weight: bold;\">One change done on the HAL CRYP requires an update on \r\nthe application code based on HAL V1.0.2</span></span>\r\n</li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update \r\nHAL_CRYP_DESECB_Decrypt() API to invert pPlainData and pCypherData \r\nparameters</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL Generic </span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\">update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update HAL \r\nweak empty callbacks to prevent unused argument compilation warnings with some \r\ncompilers by calling the following line:</span>\r\n</li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">UNUSED(hppp);</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Remove references to STM32CubeMX and MicroXplorer from stm32f7xx_hal_msp_template.c file<br></span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL ADC</span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\"> update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\">Replace ADC_CHANNEL_TEMPSENSOR definition from ADC_CHANNEL_16 to ADC_CHANNEL_18 </span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\">&nbsp;</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\">Update HAL ADC driver state machine for code efficiency</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\" lang=\"EN-US\">Add new literal: ADC_INJECTED_SOFTWARE_START to be used as possible \r\nvalue for the ExternalTrigInjecConvEdge parameter in the ADC_InitTypeDef \r\nstructure to select the ADC software trigger mode.</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL CORTEX </span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update</span>\r\n</li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Remove duplication \r\nfor __HAL_CORTEX_SYSTICKCLK_CONFIG() macro</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL CRYP </span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update HAL_CRYP_DESECB_Decrypt() API to fix the inverted pPlainData and pCypherData parameters issue </span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL FLASH </span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update OB_IWDG_STOP_ACTIVE definition</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update OB_RDP_LEVEL_x definition by proper values</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update FLASH_MassErase() function to consider the voltage range parameter in the mass erase configuration <br></span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL RCC</span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\"> update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update values for LSE Drive capability defines</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update PLLN min value 50 instead of 100</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">add RCC_PLLI2SP_DIVx defines for PLLI2SP clock divider</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"></span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\" lang=\"EN-US\">Update __HAL_RCC_USB_OTG_FS_CLK_DISABLE() macro to remove the disable of the SYSCFG</span><span style=\"font-family: Verdana; font-size: 10pt;\">&nbsp;</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">Update HAL_RCCEx_GetPeriphCLKFreq() function for proper SAI clock configuration<br></span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL SAI </span></span><span style=\"font-weight: bold;\"></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\">update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update for proper management of the external synchronization input selection</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update of&nbsp;HAL_SAI_Init () funciton</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update definition of SAI_Block_SyncExt and SAI_Block_Synchronization groups</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update SAI_SLOTACTIVE_X &nbsp;defines values</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update&nbsp;</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">HAL_SAI_Init() function for proper companding mode management</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update SAI_Transmit_ITxxBit() functions to add the check on transfer counter before writing new data to SAIx_DR registers</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update SAI_FillFifo() function to avoid issue when the number of data to transmit is smaller than the FIFO size</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update HAL_SAI_EnableRxMuteMode() function for proper mute management</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update SAI_InitPCM() function to support 24bits configuration</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL SD </span></span><span style=\"font-weight: bold;\"></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\">update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\">update HAL_SD_Get_CardInfo() to properly support high capacity cards</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\"><br></span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL SPDIFRX </span></span><span style=\"font-weight: bold;\"></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\">update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update SPDIFRX_DMARxCplt() function implementation to&nbsp;check on circular mode before disabling the DMA</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL TIM </span></span><span style=\"font-weight: bold;\"></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\">update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update HAL_TIM_ConfigClockSource() function implementation for proper parameters check</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL UART</span> update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">Update __HAL_UART_CLEAR_IT macro for proper functionning&nbsp;</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\"><span style=\"font-weight: bold;\">ll FMC</span> update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">add FMC_PAGE_SIZE_512 define</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\"><span style=\"font-weight: bold;\">ll SDMMC</span> update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update SDMMC_SetSDMMCReadWaitMode() function for proper functionning</span></li></ul></ul><h3 style=\"background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;\"><span style=\"font-size: 10pt; font-family: Arial; color: white;\">V1.0.2 / 21-September-2015</span></h3>\r\n<p class=\"MsoNormal\" style=\"margin: 4.5pt 0cm 4.5pt 18pt;\"><b style=\"\"><u><span style=\"font-size: 10pt; font-family: Verdana; color: black;\">Main\r\nChanges</span></u></b></p><ul style=\"margin-top: 0cm;\" type=\"square\"><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL Generic </span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\">update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">stm32f7xx_hal.conf_template.h: update&nbsp;</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">HSE_STARTUP_TIMEOUT</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">stm32f7xx_hal_def.h: update the</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"> quotation marks used in #error\"USE_RTOS should be 0 in the current HAL release\"</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL DMA</span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\"> update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Overall \r\ndriver update for code optimization</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"></span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">add \r\nStreamBaseAddress and StreamIndex new fields in the DMA_HandleTypeDef \r\nstructure</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">add \r\nDMA_Base_Registers private structure</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">add static function \r\nDMA_CalcBaseAndBitshift()</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update \r\nHAL_DMA_Init() function to use the new added static function</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update \r\nHAL_DMA_DeInit() function to optimize clear flag operations</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update \r\nHAL_DMA_Start_IT() function to optimize interrupts enable</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update \r\nHAL_DMA_PollForTransfer() function to optimize check on flags</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update \r\nHAL_DMA_IRQHandler() function to optimize interrupt flag management</span></li></ul></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL ETH&nbsp;</span></span><span style=\"font-weight: bold;\"></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\">update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">remove duplicated macro IS_ETH_RX_MODE()</span><small><span style=\"font-style: italic;\"></span></small></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL GPIO </span></span><span style=\"font-weight: bold;\"></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\">update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Rename \r\nGPIO_SPEED_LOW define to GPIO_SPEED_FREQ_LOW</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Rename \r\nGPIO_SPEED_MEDIUM define to GPIO_SPEED_FREQ_MEDIUM</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Rename \r\nGPIO_SPEED_FAST define to GPIO_SPEED_FREQ_HIGH</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Rename \r\nGPIO_SPEED_HIGH define to GPIO_SPEED_FREQ_VERY_HIGH</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL HASH </span></span><span style=\"font-weight: bold;\"></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\">update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Rename \r\nHAL_HASH_STATETypeDef to HAL_HASH_StateTypeDef</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Rename \r\nHAL_HASH_PhaseTypeDef to HAL_HASHPhaseTypeDef</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL RCC </span></span><span style=\"font-weight: bold;\"></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\">update</span><span style=\"font-weight: bold;\"></span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update values for LSE Drive capability defines</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update PLLN/PLLI2SN/PLLSAI VCO min value 100MHz instead of 192MHz</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">add __HAL_RCC_MCO1_CONFIG() and </span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">__HAL_RCC_MCO2_CONFIG() macros</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"></span></li></ul><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update HAL_RCCEx_PeriphCLKConfig() function to reset the Backup domain only if the RTC Clock source selection is modified&nbsp;</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL TIM</span> update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update the implementation of __HAL_TIM_SET_COMPARE() macro</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">remove useless assert() in&nbsp;HAL_TIM_PWM_ConfigChannel(), TIM_OC2_SetConfig() and HAL_TIM_PWM_ConfigChannel() </span><span style=\"font-family: Verdana; font-size: 10pt;\">functions</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL CAN</span> update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">add the clear flag ERRI bit in HAL_CAN_IRQHandler()</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL I2S</span> update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update I2S HAL_I2S_Transmit() API&nbsp;to keep the check on busy flag only for the slave</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL QSPI</span> update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">Add __HAL_QSPI_CLEAR_FLAG() before QSPI_Config()</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL UART</span> update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">Remove\r\nenabling of ERR IT source and PE source from HAL_UART_Transmit_IT() and\r\nremove the corresponding disabling ERR/PE IT from UART_EndTransmit_IT()</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL PCD</span></span><span style=\"font-family: Verdana; font-size: 10pt;\"> update</span><span style=\"font-weight: bold;\">&nbsp;</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">Clean status phase received interrupt when DMA mode enabled&nbsp;</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL HCD </span></span><span style=\"font-family: Verdana; font-size: 10pt;\">update</span><span style=\"font-family: Verdana; font-size: 10pt;\"><span style=\"font-weight: bold;\"></span></span><span style=\"font-weight: bold;\"></span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update to use local \r\nvariable in USB Host channel re-activation</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\"><span style=\"font-weight: bold;\">ll FMC</span> update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update the define FMC Write FIFO Disable/Enable: FMC_WRITE_FIFO_DISABLE and FMC_WRITE_FIFO_ENABLE</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">remove return HAL_ERROR from FMC_SDRAM_SendCommand() function</span></li></ul></ul><span style=\"font-family: Verdana; font-size: 10pt;\"></span><h3 style=\"background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;\"><span style=\"font-size: 10pt; font-family: Arial; color: white;\">V1.0.1 / 25-June-2015</span></h3>\r\n<p class=\"MsoNormal\" style=\"margin: 4.5pt 0cm 4.5pt 18pt;\"><b style=\"\"><u><span style=\"font-size: 10pt; font-family: Verdana; color: black;\">Main\r\nChanges</span></u></b></p><ul style=\"margin-top: 0cm;\" type=\"square\"><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">General updates \r\nto fix known defects and enhancements implementation</span><span style=\"font-family: Verdana; font-size: 10pt;\"></span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL CRC&nbsp;</span>update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update __HAL_CRC_SET_IDR() macro implementation to use WRITE_REG() instead of MODIFY_REG()<br></span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL CEC&nbsp;</span>update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update timeout management in HAL_CEC_Transmit() and HAL_CEC_Receive() functions</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL Cortex </span>update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update HAL_MPU_ConfigRegion() function to be misra compliant</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL ETH </span>update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Remove \r\nduplicated IS_ETH_DUPLEX_MODE() and IS_ETH_RX_MODE() macros</span><span style=\"font-family: Verdana; font-size: 10pt;\"></span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Remove \r\nillegal space ETH_MAC_READCONTROLLER_FLUSHING macro</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update \r\nETH_MAC_READCONTROLLER_XXX defined values (XXX can be IDLE, READING_DATA and \r\nREADING_STATUS)</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL FLASH </span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update FLASH_OB_GetRDP() function to return uint8_t &nbsp;instead of FlagStatus</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update OB_RDP_LEVELx definition</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">add __HAL_FLASH_GET_LATENCY() macro</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL HASH </span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update</span><span style=\"font-family: Verdana; font-size: 10pt;\"></span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update\r\nHASH_DMAXferCplt() and HASHEx_DMAXferCplt() functions to properly\r\nconfigure the number of valid bits in last word of the message</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update HAL_HASH_SHA1_Accumulate() function to check on the length of the input buffer</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update\r\nHAL_HASH_<span style=\"font-weight: bold; font-style: italic;\">MODE</span>_Start_IT() functions (<span style=\"font-style: italic;\"><span style=\"font-weight: bold;\">Mode </span></span><span style=\"font-weight: bold;\"></span>stands for MD5, SHA1, SHA224 and SHA256<span style=\"font-style: italic;\"><span style=\"font-weight: bold;\"> </span></span>) to :</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Fix processing \r\nfail for small input buffers</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">to unlock \r\nthe process and call return HAL_OK at the end of HASH processing to avoid \r\nincorrect repeating software</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">properly to manage \r\nthe HashITCounter efficiency </span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update to call the \r\nHAL_HASH_InCpltCallback() at the end of the complete buffer instead \r\nof</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"> \r\nevery each 512 bits </span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update HASH_IT_DINI and HASH_IT_DCI definition</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update __HAL_HASH_GET_FLAG() macro definition<br></span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL I2S </span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update HAL_I2S_Transmit() function to ensure the waiting on Busy flag in case of slave mode selection</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL RTC </span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update HAL_RTCEx_SetWakeUpTimer() and HAL_RTCEx_SetWakeUpTimer_IT() functions to properly check on WUTWF flag</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">rename RTC_TIMESTAMPPIN_PI8 define to RTC_TIMESTAMPPIN_POS1</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">rename RTC_TIMESTAMPPIN_PC1 define to RTC_TIMESTAMPPIN_POS2</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG() macro definition</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update __HAL_RTC_TAMPER_GET_IT() macro definition</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update __HAL_RTC_TAMPER_CLEAR_FLAG() macro definition</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update __HAL_RTC_TIMESTAMP_CLEAR_FLAG() macro definition</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() macro definition</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">add RTC_TAMPCR_TAMPXE and RTC_TAMPCR_TAMPXIE defines</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL SMARTCARD </span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">add SMARTCARD_FLAG_IDLE, SMARTCARD_IT_IDLE and&nbsp; SMARTCARD_CLEAR_IDLEF defines<br></span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL UART </span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update HAL_UART_DMAResume() function to clear overrun flag before resuming the Rx transfer</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update UART_FLAG_SBKF definition<br></span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL USART </span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update HAL_USART_DMAResume() function to </span><span style=\"font-family: Verdana; font-size: 10pt;\">clear overrun flag before resuming the Rx transfer</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">LL FMC </span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update NAND timing maximum values</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">LL USB </span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update</span>\r\n</li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">USB_FlushTxFifo API: \r\nupdate to flush all Tx FIFO</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update to use local \r\nvariable in USB Host channel re-activation</span></li></ul></ul>\r\n<b><u><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;\"></span></u></b>\r\n<h3 style=\"background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;\"><span style=\"font-size: 10pt; font-family: Arial; color: white;\">V1.0.0 / 12-May-2015</span></h3>\r\n<p class=\"MsoNormal\" style=\"margin: 4.5pt 0cm 4.5pt 18pt;\"><b style=\"\"><u><span style=\"font-size: 10pt; font-family: Verdana; color: black;\">Main\r\nChanges</span></u></b></p><span style=\"font-family: Verdana; font-size: 10pt;\"></span><span style=\"font-family: Verdana; font-size: 10pt;\"></span><ul style=\"margin-top: 0cm;\" type=\"square\"><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\"></span><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\"></span><span style=\"font-family: Verdana; font-size: 10pt;\">First official release for</span><span style=\"font-family: Verdana; font-size: 10pt;\"><span style=\"font-style: italic; font-weight: bold;\"> STM32F756xx/746xx/745xx</span> \r\ndevices</span></li></ul>\r\n<b><u><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;\"></span></u></b>\r\n<h2 style=\"background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;\"><a name=\"License\"></a><span style=\"font-size: 12pt; color: white;\">License<o:p></o:p></span></h2>\r\n<div style=\"text-align: justify;\">\r\n<div style=\"text-align: justify;\"><font size=\"-1\"><span style=\"font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\">Redistribution\r\nand use in source and binary forms, with or without\r\nmodification, are permitted provided that the following conditions are\r\nmet:</span><br>\r\n</font>\r\n<ol>\r\n<li><font size=\"-1\"><span style=\"font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\">Redistributions\r\nof source code must retain the above copyright notice, this list of\r\nconditions and the following disclaimer.</span><span style=\"font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\"></span></font></li>\r\n<li><font size=\"-1\"><span style=\"font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\">Redistributions\r\nin binary form must reproduce the above copyright notice, this list of\r\nconditions and the following disclaimer in </span><span style=\"font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\">the\r\ndocumentation and/or other materials provided with the distribution.</span><span style=\"font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\"></span></font></li>\r\n<li><font size=\"-1\"><span style=\"font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\">Neither the\r\nname of STMicroelectronics nor the names of its contributors may be\r\nused to endorse or promote products derived </span><br>\r\n</font> </li>\r\n</ol>\r\n<font size=\"-1\"><span style=\"font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;\r\nfrom this software without specific prior written permission.</span><br>\r\n<span style=\"font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\"></span><br>\r\n<span style=\"font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\">THIS\r\nSOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\nAND ANY EXPRESS OR IMPLIED</span><span style=\"font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\"> WARRANTIES,\r\nINCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r\nMERCHANTABILITY AND FITNESS FOR A </span><span style=\"font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\">PARTICULAR\r\nPURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR\r\nCONTRIBUTORS BE LIABLE FOR ANY </span><span style=\"font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\">DIRECT,\r\nINDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r\n(INCLUDING, BUT NOT LIMITED TO, </span><span style=\"font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\">PROCUREMENT OF\r\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\r\nBUSINESS INTERRUPTION) HOWEVER</span><span style=\"font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\"> CAUSED AND ON\r\nANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r\n(INCLUDING NEGLIGENCE OR </span><span style=\"font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\">OTHERWISE)\r\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF\r\nTHE POSSIBILITY OF SUCH DAMAGE.</span></font> </div>\r\n<span style=\"font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\"></span></div>\r\n<span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;\"></span>\r\n<div class=\"MsoNormal\" style=\"text-align: center;\" align=\"center\"><span style=\"color: black;\">\r\n<hr align=\"center\" size=\"2\" width=\"100%\"></span></div>\r\n<p class=\"MsoNormal\" style=\"margin: 4.5pt 0in 4.5pt 0.25in; text-align: center;\" align=\"center\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;\">For\r\ncomplete documentation on </span><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\">STM32<span style=\"color: black;\"> Microcontrollers visit </span><u><span style=\"color: blue;\"><a href=\"http://www.st.com/internet/mcu/family/141.jsp\" target=\"_blank\">www.st.com/STM32</a></span></u></span><span style=\"color: black;\"><o:p></o:p></span></p>\r\n</td>\r\n</tr>\r\n<tr><td style=\"padding: 0in;\" valign=\"top\"></td></tr></tbody>\r\n</table>\r\n<p class=\"MsoNormal\"><span style=\"font-size: 10pt;\"><o:p></o:p></span></p>\r\n</td>\r\n</tr>\r\n</tbody>\r\n</table>\r\n</div>\r\n<p class=\"MsoNormal\"><o:p>&nbsp;</o:p></p>\r\n</div>\r\n</body></html>"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal.c\r\n  * @author  MCD Application Team\r\n  * @brief   HAL module driver.\r\n  *          This is the common part of the HAL initialization\r\n  *\r\n  @verbatim\r\n  ==============================================================================\r\n                     ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]\r\n    The common HAL driver contains a set of generic and common APIs that can be\r\n    used by the PPP peripheral drivers and the user to start using the HAL. \r\n    [..]\r\n    The HAL contains two APIs' categories: \r\n         (+) Common HAL APIs\r\n         (+) Services HAL APIs\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup HAL HAL\r\n  * @brief HAL module driver.\r\n  * @{\r\n  */\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @addtogroup HAL_Private_Constants\r\n  * @{\r\n  */\r\n/**\r\n * @brief STM32F7xx HAL Driver version number V1.2.6\r\n   */\r\n#define __STM32F7xx_HAL_VERSION_MAIN   (0x01) /*!< [31:24] main version */\r\n#define __STM32F7xx_HAL_VERSION_SUB1   (0x02) /*!< [23:16] sub1 version */\r\n#define __STM32F7xx_HAL_VERSION_SUB2   (0x06) /*!< [15:8]  sub2 version */\r\n#define __STM32F7xx_HAL_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ \r\n#define __STM32F7xx_HAL_VERSION         ((__STM32F7xx_HAL_VERSION_MAIN << 24)\\\r\n                                        |(__STM32F7xx_HAL_VERSION_SUB1 << 16)\\\r\n                                        |(__STM32F7xx_HAL_VERSION_SUB2 << 8 )\\\r\n                                        |(__STM32F7xx_HAL_VERSION_RC))\r\n                                        \r\n#define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @addtogroup HAL_Private_Variables\r\n  * @{\r\n  */\r\n__IO uint32_t uwTick;\r\nuint32_t uwTickPrio   = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */\r\nHAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT;  /* 1KHz */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup HAL_Exported_Functions HAL Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions \r\n *  @brief    Initialization and de-initialization functions\r\n *\r\n@verbatim    \r\n ===============================================================================\r\n              ##### Initialization and Configuration functions #####\r\n ===============================================================================\r\n    [..]  This section provides functions allowing to:\r\n      (+) Initializes the Flash interface the NVIC allocation and initial clock \r\n          configuration. It initializes the systick also when timeout is needed \r\n          and the backup domain when enabled.\r\n      (+) De-Initializes common part of the HAL.\r\n      (+) Configure the time base source to have 1ms time base with a dedicated \r\n          Tick interrupt priority. \r\n        (++) SysTick timer is used by default as source of time base, but user\r\n             can eventually implement his proper time base source (a general purpose \r\n             timer for example or other time source), keeping in mind that Time base \r\n             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and \r\n             handled in milliseconds basis.\r\n        (++) Time base configuration function (HAL_InitTick ()) is called automatically \r\n             at the beginning of the program after reset by HAL_Init() or at any time \r\n             when clock is configured, by HAL_RCC_ClockConfig(). \r\n        (++) Source of time base is configured  to generate interrupts at regular \r\n             time intervals. Care must be taken if HAL_Delay() is called from a \r\n             peripheral ISR process, the Tick interrupt line must have higher priority \r\n            (numerically lower) than the peripheral interrupt. Otherwise the caller \r\n            ISR process will be blocked. \r\n       (++) functions affecting time base configurations are declared as __weak  \r\n             to make  override possible  in case of other  implementations in user file.\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  This function is used to initialize the HAL Library; it must be the first \r\n  *         instruction to be executed in the main program (before to call any other\r\n  *         HAL function), it performs the following:\r\n  *           Configure the Flash prefetch, and instruction cache through ART accelerator.\r\n  *           Configures the SysTick to generate an interrupt each 1 millisecond,\r\n  *           which is clocked by the HSI (at this stage, the clock is not yet\r\n  *           configured and thus the system is running from the internal HSI at 16 MHz).\r\n  *           Set NVIC Group Priority to 4.\r\n  *           Calls the HAL_MspInit() callback function defined in user file \r\n  *           \"stm32f7xx_hal_msp.c\" to do the global low level hardware initialization \r\n  *            \r\n  * @note   SysTick is used as time base for the HAL_Delay() function, the application\r\n  *         need to ensure that the SysTick time base is always set to 1 millisecond\r\n  *         to have correct HAL operation.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_Init(void)\r\n{\r\n  /* Configure Instruction cache through ART accelerator */ \r\n#if (ART_ACCLERATOR_ENABLE != 0)\r\n   __HAL_FLASH_ART_ENABLE();\r\n#endif /* ART_ACCLERATOR_ENABLE */\r\n\r\n  /* Configure Flash prefetch */\r\n#if (PREFETCH_ENABLE != 0U)\r\n  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();\r\n#endif /* PREFETCH_ENABLE */\r\n\r\n  /* Set Interrupt Group Priority */\r\n  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);\r\n\r\n  /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */\r\n  HAL_InitTick(TICK_INT_PRIORITY);\r\n  \r\n  /* Init the low level hardware */\r\n  HAL_MspInit();\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  This function de-Initializes common part of the HAL and stops the systick.\r\n  *         This function is optional.   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DeInit(void)\r\n{\r\n  /* Reset of all peripherals */\r\n  __HAL_RCC_APB1_FORCE_RESET();\r\n  __HAL_RCC_APB1_RELEASE_RESET();\r\n\r\n  __HAL_RCC_APB2_FORCE_RESET();\r\n  __HAL_RCC_APB2_RELEASE_RESET();\r\n\r\n  __HAL_RCC_AHB1_FORCE_RESET();\r\n  __HAL_RCC_AHB1_RELEASE_RESET();\r\n\r\n  __HAL_RCC_AHB2_FORCE_RESET();\r\n  __HAL_RCC_AHB2_RELEASE_RESET();\r\n\r\n  __HAL_RCC_AHB3_FORCE_RESET();\r\n  __HAL_RCC_AHB3_RELEASE_RESET();\r\n\r\n  /* De-Init the low level hardware */\r\n  HAL_MspDeInit();\r\n    \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initialize the MSP.\r\n  * @retval None\r\n  */\r\n__weak void HAL_MspInit(void)\r\n{\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_MspInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the MSP.\r\n  * @retval None\r\n  */\r\n__weak void HAL_MspDeInit(void)\r\n{\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_MspDeInit could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief This function configures the source of the time base.\r\n  *        The time source is configured  to have 1ms time base with a dedicated \r\n  *        Tick interrupt priority.\r\n  * @note This function is called  automatically at the beginning of program after\r\n  *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().\r\n  * @note In the default implementation, SysTick timer is the source of time base. \r\n  *       It is used to generate interrupts at regular time intervals. \r\n  *       Care must be taken if HAL_Delay() is called from a peripheral ISR process, \r\n  *       The SysTick interrupt must have higher priority (numerically lower)\r\n  *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.\r\n  *       The function is declared as __weak  to be overwritten  in case of other\r\n  *       implementation  in user file.\r\n  * @param TickPriority Tick interrupt priority.\r\n  * @retval HAL status\r\n  */\r\n__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)\r\n{\r\n  /* Configure the SysTick to have interrupt in 1ms time basis*/\r\n  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Configure the SysTick IRQ priority */\r\n  if (TickPriority < (1UL << __NVIC_PRIO_BITS))\r\n  {\r\n    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);\r\n    uwTickPrio = TickPriority;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions \r\n *  @brief    HAL Control functions\r\n *\r\n@verbatim\r\n ===============================================================================\r\n                      ##### HAL Control functions #####\r\n ===============================================================================\r\n    [..]  This section provides functions allowing to:\r\n      (+) Provide a tick value in millisecond\r\n      (+) Provide a blocking delay in millisecond\r\n      (+) Suspend the time base source interrupt\r\n      (+) Resume the time base source interrupt\r\n      (+) Get the HAL API driver version\r\n      (+) Get the device identifier\r\n      (+) Get the device revision identifier\r\n      (+) Enable/Disable Debug module during SLEEP mode\r\n      (+) Enable/Disable Debug module during STOP mode\r\n      (+) Enable/Disable Debug module during STANDBY mode\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief This function is called to increment  a global variable \"uwTick\"\r\n  *        used as application time base.\r\n  * @note In the default implementation, this variable is incremented each 1ms\r\n  *       in SysTick ISR.\r\n * @note This function is declared as __weak to be overwritten in case of other \r\n  *      implementations in user file.\r\n  * @retval None\r\n  */\r\n__weak void HAL_IncTick(void)\r\n{\r\n  uwTick += uwTickFreq;\r\n}\r\n\r\n/**\r\n  * @brief Provides a tick value in millisecond.\r\n  * @note This function is declared as __weak to be overwritten in case of other \r\n  *       implementations in user file.\r\n  * @retval tick value\r\n  */\r\n__weak uint32_t HAL_GetTick(void)\r\n{\r\n  return uwTick;\r\n}\r\n\r\n/**\r\n  * @brief This function returns a tick priority.\r\n  * @retval tick priority\r\n  */\r\nuint32_t HAL_GetTickPrio(void)\r\n{\r\n  return uwTickPrio;\r\n}\r\n\r\n/**\r\n  * @brief Set new tick Freq.\r\n  * @retval Status\r\n  */\r\nHAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)\r\n{\r\n  HAL_StatusTypeDef status  = HAL_OK;\r\n  assert_param(IS_TICKFREQ(Freq));\r\n\r\n  if (uwTickFreq != Freq)\r\n  {\r\n    uwTickFreq = Freq;\r\n\r\n    /* Apply the new tick Freq  */\r\n    status = HAL_InitTick(uwTickPrio);\r\n  }\r\n\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief Return tick frequency.\r\n  * @retval tick period in Hz\r\n  */\r\nHAL_TickFreqTypeDef HAL_GetTickFreq(void)\r\n{\r\n  return uwTickFreq;\r\n}\r\n\r\n/**\r\n  * @brief This function provides minimum delay (in milliseconds) based\r\n  *        on variable incremented.\r\n  * @note In the default implementation , SysTick timer is the source of time base.\r\n  *       It is used to generate interrupts at regular time intervals where uwTick\r\n  *       is incremented.\r\n  * @note This function is declared as __weak to be overwritten in case of other\r\n  *       implementations in user file.\r\n  * @param Delay  specifies the delay time length, in milliseconds.\r\n  * @retval None\r\n  */\r\n__weak void HAL_Delay(uint32_t Delay)\r\n{\r\n  uint32_t tickstart = HAL_GetTick();\r\n  uint32_t wait = Delay;\r\n\r\n  /* Add a freq to guarantee minimum wait */\r\n  if (wait < HAL_MAX_DELAY)\r\n  {\r\n    wait += (uint32_t)(uwTickFreq);\r\n  }\r\n\r\n  while ((HAL_GetTick() - tickstart) < wait)\r\n  {\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Suspend Tick increment.\r\n  * @note In the default implementation , SysTick timer is the source of time base. It is\r\n  *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()\r\n  *       is called, the SysTick interrupt will be disabled and so Tick increment \r\n  *       is suspended.\r\n  * @note This function is declared as __weak to be overwritten in case of other\r\n  *       implementations in user file.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SuspendTick(void)\r\n{\r\n  /* Disable SysTick Interrupt */\r\n  SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;\r\n}\r\n\r\n/**\r\n  * @brief Resume Tick increment.\r\n  * @note In the default implementation , SysTick timer is the source of time base. It is\r\n  *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()\r\n  *       is called, the SysTick interrupt will be enabled and so Tick increment \r\n  *       is resumed.\r\n  * @note This function is declared as __weak to be overwritten in case of other\r\n  *       implementations in user file.\r\n  * @retval None\r\n  */\r\n__weak void HAL_ResumeTick(void)\r\n{\r\n  /* Enable SysTick Interrupt */\r\n  SysTick->CTRL  |= SysTick_CTRL_TICKINT_Msk;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the HAL revision\r\n  * @retval version : 0xXYZR (8bits for each decimal, R for RC)\r\n  */\r\nuint32_t HAL_GetHalVersion(void)\r\n{\r\n return __STM32F7xx_HAL_VERSION;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the device revision identifier.\r\n  * @retval Device revision identifier\r\n  */\r\nuint32_t HAL_GetREVID(void)\r\n{\r\n   return((DBGMCU->IDCODE) >> 16U);\r\n}\r\n\r\n/**\r\n  * @brief  Returns the device identifier.\r\n  * @retval Device identifier\r\n  */\r\nuint32_t HAL_GetDEVID(void)\r\n{\r\n   return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);\r\n}\r\n\r\n/**\r\n  * @brief  Returns first word of the unique device identifier (UID based on 96 bits)\r\n  * @retval Device identifier\r\n  */\r\nuint32_t HAL_GetUIDw0(void)\r\n{\r\n   return(READ_REG(*((uint32_t *)UID_BASE)));\r\n}\r\n\r\n/**\r\n  * @brief  Returns second word of the unique device identifier (UID based on 96 bits)\r\n  * @retval Device identifier\r\n  */\r\nuint32_t HAL_GetUIDw1(void)\r\n{\r\n   return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));\r\n}\r\n\r\n/**\r\n  * @brief  Returns third word of the unique device identifier (UID based on 96 bits)\r\n  * @retval Device identifier\r\n  */\r\nuint32_t HAL_GetUIDw2(void)\r\n{\r\n   return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));\r\n}\r\n\r\n/**\r\n  * @brief  Enable the Debug Module during SLEEP mode\r\n  * @retval None\r\n  */\r\nvoid HAL_DBGMCU_EnableDBGSleepMode(void)\r\n{\r\n  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);\r\n}\r\n\r\n/**\r\n  * @brief  Disable the Debug Module during SLEEP mode\r\n  * @retval None\r\n  */\r\nvoid HAL_DBGMCU_DisableDBGSleepMode(void)\r\n{\r\n  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);\r\n}\r\n\r\n/**\r\n  * @brief  Enable the Debug Module during STOP mode\r\n  * @retval None\r\n  */\r\nvoid HAL_DBGMCU_EnableDBGStopMode(void)\r\n{\r\n  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);\r\n}\r\n\r\n/**\r\n  * @brief  Disable the Debug Module during STOP mode\r\n  * @retval None\r\n  */\r\nvoid HAL_DBGMCU_DisableDBGStopMode(void)\r\n{\r\n  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);\r\n}\r\n\r\n/**\r\n  * @brief  Enable the Debug Module during STANDBY mode\r\n  * @retval None\r\n  */\r\nvoid HAL_DBGMCU_EnableDBGStandbyMode(void)\r\n{\r\n  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);\r\n}\r\n\r\n/**\r\n  * @brief  Disable the Debug Module during STANDBY mode\r\n  * @retval None\r\n  */\r\nvoid HAL_DBGMCU_DisableDBGStandbyMode(void)\r\n{\r\n  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);\r\n}\r\n\r\n/**\r\n  * @brief  Enables the I/O Compensation Cell.\r\n  * @note   The I/O compensation cell can be used only when the device supply\r\n  *         voltage ranges from 2.4 to 3.6 V.  \r\n  * @retval None\r\n  */\r\nvoid HAL_EnableCompensationCell(void)\r\n{\r\n  SYSCFG->CMPCR |= SYSCFG_CMPCR_CMP_PD;\r\n}\r\n\r\n/**\r\n  * @brief  Power-down the I/O Compensation Cell.\r\n  * @note   The I/O compensation cell can be used only when the device supply\r\n  *         voltage ranges from 2.4 to 3.6 V.  \r\n  * @retval None\r\n  */\r\nvoid HAL_DisableCompensationCell(void)\r\n{\r\n  SYSCFG->CMPCR &= (uint32_t)~((uint32_t)SYSCFG_CMPCR_CMP_PD);\r\n}\r\n\r\n/**\r\n  * @brief  Enables the FMC Memory Mapping Swapping.\r\n  *   \r\n  * @note   SDRAM is accessible at 0x60000000 \r\n  *         and NOR/RAM is accessible at 0xC0000000   \r\n  *\r\n  * @retval None\r\n  */\r\nvoid HAL_EnableFMCMemorySwapping(void)\r\n{\r\n  SYSCFG->MEMRMP |= SYSCFG_MEMRMP_SWP_FMC_0;\r\n}\r\n\r\n/**\r\n  * @brief  Disables the FMC Memory Mapping Swapping\r\n  *   \r\n  * @note   SDRAM is accessible at 0xC0000000 (default mapping)  \r\n  *         and NOR/RAM is accessible at 0x60000000 (default mapping)    \r\n  *           \r\n  * @retval None\r\n  */\r\nvoid HAL_DisableFMCMemorySwapping(void)\r\n{\r\n\r\n  SYSCFG->MEMRMP &= (uint32_t)~((uint32_t)SYSCFG_MEMRMP_SWP_FMC);\r\n}\r\n\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n/**\r\n* @brief  Enable the Internal FLASH Bank Swapping.\r\n*   \r\n* @note   This function can be used only for STM32F77xx/STM32F76xx devices. \r\n*\r\n* @note   Flash Bank2 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM)) \r\n*         and Flash Bank1 mapped at 0x08100000 (AXI) (aliased at 0x00300000 (TCM))   \r\n*\r\n* @retval None\r\n*/\r\nvoid HAL_EnableMemorySwappingBank(void)\r\n{\r\n  SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB);\r\n}\r\n\r\n/**\r\n* @brief  Disable the Internal FLASH Bank Swapping.\r\n*   \r\n* @note   This function can be used only for STM32F77xx/STM32F76xx devices. \r\n*\r\n* @note   The default state : Flash Bank1 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM)) \r\n*         and Flash Bank2 mapped at 0x08100000 (AXI)( aliased at 0x00300000 (TCM)) \r\n*           \r\n* @retval None\r\n*/\r\nvoid HAL_DisableMemorySwappingBank(void)\r\n{\r\n  CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB);\r\n}\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_adc.c\r\n  * @author  MCD Application Team\r\n  * @brief   This file provides firmware functions to manage the following \r\n  *          functionalities of the Analog to Digital Convertor (ADC) peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + IO operation functions\r\n  *           + State and errors functions\r\n  *         \r\n  @verbatim\r\n  ==============================================================================\r\n                    ##### ADC Peripheral features #####\r\n  ==============================================================================\r\n  [..] \r\n  (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.\r\n  (#) Interrupt generation at the end of conversion, end of injected conversion,  \r\n      and in case of analog watchdog or overrun events\r\n  (#) Single and continuous conversion modes.\r\n  (#) Scan mode for automatic conversion of channel 0 to channel x.\r\n  (#) Data alignment with in-built data coherency.\r\n  (#) Channel-wise programmable sampling time.\r\n  (#) External trigger option with configurable polarity for both regular and \r\n      injected conversion.\r\n  (#) Dual/Triple mode (on devices with 2 ADCs or more).\r\n  (#) Configurable DMA data storage in Dual/Triple ADC mode. \r\n  (#) Configurable delay between conversions in Dual/Triple interleaved mode.\r\n  (#) ADC conversion type (refer to the datasheets).\r\n  (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at \r\n      slower speed.\r\n  (#) ADC input range: VREF(minus) = VIN = VREF(plus).\r\n  (#) DMA request generation during regular channel conversion.\r\n\r\n\r\n                     ##### How to use this driver #####\r\n  ==============================================================================\r\n  [..]\r\n  (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():\r\n       (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()\r\n       (##) ADC pins configuration\r\n             (+++) Enable the clock for the ADC GPIOs using the following function:\r\n                   __HAL_RCC_GPIOx_CLK_ENABLE()  \r\n             (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init() \r\n       (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())\r\n             (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()\r\n             (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()\r\n             (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()\r\n       (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())\r\n             (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()\r\n             (+++) Configure and enable two DMA streams stream for managing data\r\n                 transfer from peripheral to memory (output stream)\r\n             (+++) Associate the initialized DMA handle to the CRYP DMA handle\r\n                 using  __HAL_LINKDMA()\r\n             (+++) Configure the priority and enable the NVIC for the transfer complete\r\n                 interrupt on the two DMA Streams. The output stream should have higher\r\n                 priority than the input stream.\r\n                       \r\n    *** Configuration of ADC, groups regular/injected, channels parameters ***\r\n  ==============================================================================\r\n  [..]\r\n  (#) Configure the ADC parameters (resolution, data alignment, ...)\r\n      and regular group parameters (conversion trigger, sequencer, ...)\r\n      using function HAL_ADC_Init().\r\n\r\n  (#) Configure the channels for regular group parameters (channel number, \r\n      channel rank into sequencer, ..., into regular group)\r\n      using function HAL_ADC_ConfigChannel().\r\n\r\n  (#) Optionally, configure the injected group parameters (conversion trigger, \r\n      sequencer, ..., of injected group)\r\n      and the channels for injected group parameters (channel number, \r\n      channel rank into sequencer, ..., into injected group)\r\n      using function HAL_ADCEx_InjectedConfigChannel().\r\n\r\n  (#) Optionally, configure the analog watchdog parameters (channels\r\n      monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig().\r\n\r\n  (#) Optionally, for devices with several ADC instances: configure the \r\n      multimode parameters using function HAL_ADCEx_MultiModeConfigChannel().\r\n\r\n                       *** Execution of ADC conversions ***\r\n  ==============================================================================\r\n  [..]  \r\n  (#) ADC driver can be used among three modes: polling, interruption,\r\n      transfer by DMA.    \r\n\r\n     *** Polling mode IO operation ***\r\n     =================================\r\n     [..]    \r\n       (+) Start the ADC peripheral using HAL_ADC_Start() \r\n       (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage\r\n           user can specify the value of timeout according to his end application      \r\n       (+) To read the ADC converted values, use the HAL_ADC_GetValue() function.\r\n       (+) Stop the ADC peripheral using HAL_ADC_Stop()\r\n       \r\n     *** Interrupt mode IO operation ***    \r\n     ===================================\r\n     [..]    \r\n       (+) Start the ADC peripheral using HAL_ADC_Start_IT() \r\n       (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine\r\n       (+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can \r\n           add his own code by customization of function pointer HAL_ADC_ConvCpltCallback \r\n       (+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can \r\n           add his own code by customization of function pointer HAL_ADC_ErrorCallback\r\n       (+) Stop the ADC peripheral using HAL_ADC_Stop_IT()     \r\n\r\n     *** DMA mode IO operation ***    \r\n     ==============================\r\n     [..]    \r\n       (+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length \r\n           of data to be transferred at each end of conversion \r\n       (+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can \r\n           add his own code by customization of function pointer HAL_ADC_ConvCpltCallback \r\n       (+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can \r\n           add his own code by customization of function pointer HAL_ADC_ErrorCallback\r\n       (+) Stop the ADC peripheral using HAL_ADC_Stop_DMA()\r\n                    \r\n     *** ADC HAL driver macros list ***\r\n     ============================================= \r\n     [..]\r\n       Below the list of most used macros in ADC HAL driver.\r\n       \r\n      (+) __HAL_ADC_ENABLE : Enable the ADC peripheral\r\n      (+) __HAL_ADC_DISABLE : Disable the ADC peripheral\r\n      (+) __HAL_ADC_ENABLE_IT: Enable the ADC end of conversion interrupt\r\n      (+) __HAL_ADC_DISABLE_IT: Disable the ADC end of conversion interrupt\r\n      (+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabled\r\n      (+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags\r\n      (+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status\r\n      (+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register \r\n      \r\n     [..] \r\n       (@) You can refer to the ADC HAL driver header file for more useful macros \r\n\r\n                      *** Deinitialization of ADC ***\r\n  ==============================================================================\r\n  [..]\r\n  (#) Disable the ADC interface\r\n     (++) ADC clock can be hard reset and disabled at RCC top level.\r\n     (++) Hard reset of ADC peripherals\r\n          using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET().\r\n     (++) ADC clock disable using the equivalent macro/functions as configuration step.\r\n               (+++) Example:\r\n                   Into HAL_ADC_MspDeInit() (recommended code location) or with\r\n                   other device clock parameters configuration:\r\n               (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure);\r\n               (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;\r\n               (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock)\r\n               (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);\r\n\r\n  (#) ADC pins configuration\r\n     (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE()\r\n\r\n  (#) Optionally, in case of usage of ADC with interruptions:\r\n     (++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn)\r\n\r\n  (#) Optionally, in case of usage of DMA:\r\n        (++) Deinitialize the DMA using function HAL_DMA_DeInit().\r\n        (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn)   \r\n\r\n    @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup ADC ADC\r\n  * @brief ADC driver modules\r\n  * @{\r\n  */ \r\n\r\n#ifdef HAL_ADC_MODULE_ENABLED\r\n    \r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @addtogroup ADC_Private_Functions\r\n  * @{\r\n  */\r\n/* Private function prototypes -----------------------------------------------*/\r\nstatic void ADC_Init(ADC_HandleTypeDef* hadc);\r\nstatic void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);\r\nstatic void ADC_DMAError(DMA_HandleTypeDef *hdma);\r\nstatic void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup ADC_Exported_Functions ADC Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions \r\n *  @brief    Initialization and Configuration functions \r\n *\r\n@verbatim    \r\n ===============================================================================\r\n              ##### Initialization and de-initialization functions #####\r\n ===============================================================================\r\n    [..]  This section provides functions allowing to:\r\n      (+) Initialize and configure the ADC. \r\n      (+) De-initialize the ADC. \r\n         \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the ADCx peripheral according to the specified parameters \r\n  *         in the ADC_InitStruct and initializes the ADC MSP.\r\n  *           \r\n  * @note   This function is used to configure the global features of the ADC ( \r\n  *         ClockPrescaler, Resolution, Data Alignment and number of conversion), however,\r\n  *         the rest of the configuration parameters are specific to the regular\r\n  *         channels group (scan mode activation, continuous mode activation,\r\n  *         External trigger source and edge, DMA continuous request after the  \r\n  *         last transfer and End of conversion selection).\r\n  *             \r\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)\r\n{\r\n  HAL_StatusTypeDef tmp_hal_status = HAL_OK;\r\n  \r\n  /* Check ADC handle */\r\n  if(hadc == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\r\n  assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));\r\n  assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));\r\n  assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));\r\n  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));\r\n  assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv));\r\n  assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));\r\n  assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));\r\n  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));\r\n  assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));\r\n  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));\r\n\r\n  if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)\r\n  {\r\n    assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));\r\n  }\r\n\r\n  if(hadc->State == HAL_ADC_STATE_RESET)\r\n  {\r\n    /* Initialize ADC error code */\r\n    ADC_CLEAR_ERRORCODE(hadc);\r\n    \r\n    /* Allocate lock resource and initialize it */\r\n    hadc->Lock = HAL_UNLOCKED;\r\n    /* Init the low level hardware */\r\n    HAL_ADC_MspInit(hadc);\r\n  }\r\n  \r\n  /* Configuration of ADC parameters if previous preliminary actions are      */ \r\n  /* correctly completed.                                                     */\r\n  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))\r\n  {\r\n    /* Set ADC state */\r\n    ADC_STATE_CLR_SET(hadc->State,\r\n                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,\r\n                      HAL_ADC_STATE_BUSY_INTERNAL);\r\n    \r\n    /* Set ADC parameters */\r\n    ADC_Init(hadc);\r\n    \r\n    /* Set ADC error code to none */\r\n    ADC_CLEAR_ERRORCODE(hadc);\r\n    \r\n    /* Set the ADC state */\r\n    ADC_STATE_CLR_SET(hadc->State,\r\n                      HAL_ADC_STATE_BUSY_INTERNAL,\r\n                      HAL_ADC_STATE_READY);\r\n  }\r\n  else\r\n  {\r\n    tmp_hal_status = HAL_ERROR;\r\n  }\r\n  \r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hadc);\r\n\r\n  /* Return function status */\r\n  return tmp_hal_status;\r\n}\r\n\r\n/**\r\n  * @brief  Deinitializes the ADCx peripheral registers to their default reset values. \r\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)\r\n{\r\n  HAL_StatusTypeDef tmp_hal_status = HAL_OK;\r\n  \r\n  /* Check ADC handle */\r\n  if(hadc == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\r\n  \r\n  /* Set ADC state */\r\n  SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);\r\n  \r\n  /* Stop potential conversion on going, on regular and injected groups */\r\n  /* Disable ADC peripheral */\r\n  __HAL_ADC_DISABLE(hadc);\r\n  \r\n  /* Configuration of ADC parameters if previous preliminary actions are      */ \r\n  /* correctly completed.                                                     */\r\n  if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))\r\n  {\r\n    /* DeInit the low level hardware */\r\n    HAL_ADC_MspDeInit(hadc);\r\n    \r\n    /* Set ADC error code to none */\r\n    ADC_CLEAR_ERRORCODE(hadc);\r\n    \r\n    /* Set ADC state */\r\n    hadc->State = HAL_ADC_STATE_RESET;\r\n  }\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hadc);\r\n  \r\n  /* Return function status */\r\n  return tmp_hal_status;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the ADC MSP.\r\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.  \r\n  * @retval None\r\n  */\r\n__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hadc);\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_ADC_MspInit could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the ADC MSP.\r\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.  \r\n  * @retval None\r\n  */\r\n__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hadc);\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_ADC_MspDeInit could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ADC_Exported_Functions_Group2 IO operation functions\r\n *  @brief    IO operation functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n             ##### IO operation functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Start conversion of regular channel.\r\n      (+) Stop conversion of regular channel.\r\n      (+) Start conversion of regular channel and enable interrupt.\r\n      (+) Stop conversion of regular channel and disable interrupt.\r\n      (+) Start conversion of regular channel and enable DMA transfer.\r\n      (+) Stop conversion of regular channel and disable DMA transfer.\r\n      (+) Handle ADC interrupt request. \r\n               \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Enables ADC and starts conversion of the regular channels.\r\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)\r\n{\r\n  __IO uint32_t counter = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));\r\n  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); \r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hadc);\r\n  \r\n  /* Enable the ADC peripheral */\r\n  /* Check if ADC peripheral is disabled in order to enable it and wait during \r\n  Tstab time the ADC's stabilization */\r\n  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)\r\n  {  \r\n    /* Enable the Peripheral */\r\n    __HAL_ADC_ENABLE(hadc);\r\n    \r\n    /* Delay for ADC stabilization time */\r\n    /* Compute number of CPU cycles to wait for */\r\n    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));\r\n    while(counter != 0)\r\n    {\r\n      counter--;\r\n    }\r\n  }\r\n  \r\n  /* Start conversion if ADC is effectively enabled */\r\n  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))\r\n  {\r\n    /* Set ADC state                                                          */\r\n    /* - Clear state bitfield related to regular group conversion results     */\r\n    /* - Set state bitfield related to regular group operation                */\r\n    ADC_STATE_CLR_SET(hadc->State,\r\n                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,\r\n                      HAL_ADC_STATE_REG_BUSY);\r\n    \r\n    /* If conversions on group regular are also triggering group injected,    */\r\n    /* update ADC state.                                                      */\r\n    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)\r\n    {\r\n      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  \r\n    }\r\n    \r\n    /* State machine update: Check if an injected conversion is ongoing */\r\n    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))\r\n    {\r\n      /* Reset ADC error code fields related to conversions on group regular */\r\n      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         \r\n    }\r\n    else\r\n    {\r\n      /* Reset ADC all error code fields */\r\n      ADC_CLEAR_ERRORCODE(hadc);\r\n    }\r\n    \r\n    /* Process unlocked */\r\n    /* Unlock before starting ADC conversions: in case of potential           */\r\n    /* interruption, to let the process to ADC IRQ Handler.                   */\r\n    __HAL_UNLOCK(hadc);\r\n    \r\n    /* Clear regular group conversion flag and overrun flag */\r\n    /* (To ensure of no unknown state from potential previous ADC operations) */\r\n    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);\r\n    \r\n    /* Check if Multimode enabled */\r\n    if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))\r\n    {\r\n      /* if no external trigger present enable software conversion of regular channels */\r\n      if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) \r\n      {\r\n        /* Enable the selected ADC software conversion for regular group */\r\n        hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* if instance of handle correspond to ADC1 and  no external trigger present enable software conversion of regular channels */\r\n      if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))\r\n      {\r\n        /* Enable the selected ADC software conversion for regular group */\r\n          hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Disables ADC and stop conversion of regular channels.\r\n  * \r\n  * @note   Caution: This function will stop also injected channels.  \r\n  *\r\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  *\r\n  * @retval HAL status.\r\n  */\r\nHAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hadc);\r\n  \r\n  /* Stop potential conversion on going, on regular and injected groups */\r\n  /* Disable ADC peripheral */\r\n  __HAL_ADC_DISABLE(hadc);\r\n  \r\n  /* Check if ADC is effectively disabled */\r\n  if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))\r\n  {\r\n    /* Set ADC state */\r\n    ADC_STATE_CLR_SET(hadc->State,\r\n                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,\r\n                      HAL_ADC_STATE_READY);\r\n  }\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hadc);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Poll for regular conversion complete\r\n  * @note   ADC conversion flags EOS (end of sequence) and EOC (end of\r\n  *         conversion) are cleared by this function.\r\n  * @note   This function cannot be used in a particular setup: ADC configured \r\n  *         in DMA mode and polling for end of each conversion (ADC init\r\n  *         parameter \"EOCSelection\" set to ADC_EOC_SINGLE_CONV).\r\n  *         In this case, DMA resets the flag EOC and polling cannot be\r\n  *         performed on each conversion. Nevertheless, polling can still \r\n  *         be performed on the complete sequence.\r\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @param  Timeout Timeout value in millisecond.  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Verification that ADC configuration is compliant with polling for      */\r\n  /* each conversion:                                                       */\r\n  /* Particular case is ADC configured in DMA mode and ADC sequencer with   */\r\n  /* several ranks and polling for end of each conversion.                  */\r\n  /* For code simplicity sake, this particular case is generalized to       */\r\n  /* ADC configured in DMA mode and polling for end of each conversion.     */\r\n  if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&\r\n      HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)    )\r\n  {\r\n    /* Update ADC state machine to error */\r\n    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);\r\n    \r\n    /* Process unlocked */\r\n    __HAL_UNLOCK(hadc);\r\n    \r\n    return HAL_ERROR;\r\n  }\r\n \r\n  /* Get tick */ \r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Check End of conversion flag */\r\n  while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))\r\n  {\r\n    /* Check if timeout is disabled (set to infinite wait) */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        /* Update ADC state machine to timeout */\r\n        SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);\r\n        \r\n        /* Process unlocked */\r\n        __HAL_UNLOCK(hadc);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Clear regular group conversion flag */\r\n  __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);\r\n  \r\n  /* Update ADC state machine */\r\n  SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);\r\n  \r\n  /* Determine whether any further conversion upcoming on group regular       */\r\n  /* by external trigger, continuous mode or scan sequence on going.          */\r\n  /* Note: On STM32F7, there is no independent flag of end of sequence.       */\r\n  /*       The test of scan sequence on going is done either with scan        */\r\n  /*       sequence disabled or with end of conversion flag set to            */\r\n  /*       of end of sequence.                                                */\r\n  if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&\r\n     (hadc->Init.ContinuousConvMode == DISABLE)            &&\r\n     (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||\r\n      HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )\r\n  {\r\n    /* Set ADC state */\r\n    CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);   \r\n    \r\n    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))\r\n    { \r\n      SET_BIT(hadc->State, HAL_ADC_STATE_READY);\r\n    }\r\n  }\r\n  \r\n  /* Return ADC state */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Poll for conversion event\r\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @param  EventType the ADC event type.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg ADC_AWD_EVENT: ADC Analog watch Dog event.\r\n  *            @arg ADC_OVR_EVENT: ADC Overrun event.\r\n  * @param  Timeout Timeout value in millisecond.   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\r\n  assert_param(IS_ADC_EVENT_TYPE(EventType));\r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Check selected event flag */\r\n  while(!(__HAL_ADC_GET_FLAG(hadc,EventType)))\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        /* Update ADC state machine to timeout */\r\n        SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);\r\n        \r\n        /* Process unlocked */\r\n        __HAL_UNLOCK(hadc);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Analog watchdog (level out of window) event */\r\n  if(EventType == ADC_AWD_EVENT)\r\n  {\r\n    /* Set ADC state */\r\n    SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);\r\n      \r\n    /* Clear ADC analog watchdog flag */\r\n    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);\r\n  }\r\n  /* Overrun event */\r\n  else\r\n  {\r\n    /* Set ADC state */\r\n    SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);\r\n    /* Set ADC error code to overrun */\r\n    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);\r\n    \r\n    /* Clear ADC overrun flag */\r\n    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);\r\n  }\r\n  \r\n  /* Return ADC state */\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Enables the interrupt and starts ADC conversion of regular channels.\r\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @retval HAL status.\r\n  */\r\nHAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)\r\n{\r\n  __IO uint32_t counter = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));\r\n  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); \r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hadc);\r\n  \r\n  /* Enable the ADC peripheral */\r\n  /* Check if ADC peripheral is disabled in order to enable it and wait during \r\n     Tstab time the ADC's stabilization */\r\n  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)\r\n  {  \r\n    /* Enable the Peripheral */\r\n    __HAL_ADC_ENABLE(hadc);\r\n    \r\n    /* Delay for ADC stabilization time */\r\n    /* Compute number of CPU cycles to wait for */\r\n    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));\r\n    while(counter != 0)\r\n    {\r\n      counter--;\r\n    }\r\n  }\r\n  \r\n  /* Start conversion if ADC is effectively enabled */\r\n  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))\r\n  {\r\n    /* Set ADC state                                                          */\r\n    /* - Clear state bitfield related to regular group conversion results     */\r\n    /* - Set state bitfield related to regular group operation                */\r\n    ADC_STATE_CLR_SET(hadc->State,\r\n                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,\r\n                      HAL_ADC_STATE_REG_BUSY);\r\n    \r\n    /* If conversions on group regular are also triggering group injected,    */\r\n    /* update ADC state.                                                      */\r\n    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)\r\n    {\r\n      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  \r\n    }\r\n    \r\n    /* State machine update: Check if an injected conversion is ongoing */\r\n    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))\r\n    {\r\n      /* Reset ADC error code fields related to conversions on group regular */\r\n      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         \r\n    }\r\n    else\r\n    {\r\n      /* Reset ADC all error code fields */\r\n      ADC_CLEAR_ERRORCODE(hadc);\r\n    }\r\n    \r\n    /* Process unlocked */\r\n    /* Unlock before starting ADC conversions: in case of potential           */\r\n    /* interruption, to let the process to ADC IRQ Handler.                   */\r\n    __HAL_UNLOCK(hadc);\r\n    \r\n    /* Clear regular group conversion flag and overrun flag */\r\n    /* (To ensure of no unknown state from potential previous ADC operations) */\r\n    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);\r\n    \r\n    /* Enable end of conversion interrupt for regular group */\r\n    __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));\r\n    \r\n    /* Check if Multimode enabled */\r\n    if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))\r\n    {\r\n      /* if no external trigger present enable software conversion of regular channels */\r\n      if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) \r\n      {\r\n        /* Enable the selected ADC software conversion for regular group */\r\n        hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* if instance of handle correspond to ADC1 and  no external trigger present enable software conversion of regular channels */\r\n      if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))\r\n      {\r\n        /* Enable the selected ADC software conversion for regular group */\r\n          hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Disables the interrupt and stop ADC conversion of regular channels.\r\n  * \r\n  * @note   Caution: This function will stop also injected channels.  \r\n  *\r\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @retval HAL status.\r\n  */\r\nHAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hadc);\r\n  \r\n  /* Stop potential conversion on going, on regular and injected groups */\r\n  /* Disable ADC peripheral */\r\n  __HAL_ADC_DISABLE(hadc);\r\n  \r\n  /* Check if ADC is effectively disabled */\r\n  if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))\r\n  {\r\n  \t/* Disable ADC end of conversion interrupt for regular group */\r\n    __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));\r\n\r\n    /* Set ADC state */\r\n    ADC_STATE_CLR_SET(hadc->State,\r\n                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,\r\n                      HAL_ADC_STATE_READY);\r\n  }\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hadc);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Handles ADC interrupt request  \r\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @retval None\r\n  */\r\nvoid HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)\r\n{\r\n  uint32_t tmp1 = 0, tmp2 = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));\r\n  assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));\r\n  assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));\r\n  \r\n  tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC);\r\n  tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC);\r\n  /* Check End of conversion flag for regular channels */\r\n  if(tmp1 && tmp2)\r\n  {\r\n    /* Update state machine on conversion status if not in error state */\r\n    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))\r\n    {\r\n      /* Set ADC state */\r\n      SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); \r\n    }\r\n    \r\n    /* Determine whether any further conversion upcoming on group regular   */\r\n    /* by external trigger, continuous mode or scan sequence on going.      */\r\n    /* Note: On STM32F7, there is no independent flag of end of sequence.   */\r\n    /*       The test of scan sequence on going is done either with scan    */\r\n    /*       sequence disabled or with end of conversion flag set to        */\r\n    /*       of end of sequence.                                            */\r\n    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&\r\n       (hadc->Init.ContinuousConvMode == DISABLE)            &&\r\n       (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || \r\n        HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )\r\n    {\r\n      /* Disable ADC end of single conversion interrupt on group regular */\r\n      /* Note: Overrun interrupt was enabled with EOC interrupt in          */\r\n      /* HAL_ADC_Start_IT(), but is not disabled here because can be used   */\r\n      /* by overrun IRQ process below.                                      */\r\n      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);\r\n      \r\n      /* Set ADC state */\r\n      CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);\r\n      \r\n      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))\r\n      {\r\n        SET_BIT(hadc->State, HAL_ADC_STATE_READY);\r\n      }\r\n    }\r\n    \r\n    /* Conversion complete callback */ \r\n    HAL_ADC_ConvCpltCallback(hadc);\r\n    \r\n    /* Clear regular group conversion flag */\r\n    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);\r\n  }\r\n  \r\n  tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC);\r\n  tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC);                               \r\n  /* Check End of conversion flag for injected channels */\r\n  if(tmp1 && tmp2)\r\n  {\r\n    /* Update state machine on conversion status if not in error state */\r\n    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))\r\n    {\r\n      /* Set ADC state */\r\n      SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);\r\n    }\r\n\r\n    /* Determine whether any further conversion upcoming on group injected  */\r\n    /* by external trigger, scan sequence on going or by automatic injected */\r\n    /* conversion from group regular (same conditions as group regular      */\r\n    /* interruption disabling above).                                       */\r\n    if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                    &&\r\n       (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||\r\n        HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)) &&\r\n       (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&\r\n       (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&\r\n       (hadc->Init.ContinuousConvMode == DISABLE))))\r\n    {\r\n      /* Disable ADC end of single conversion interrupt on group injected */\r\n      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);\r\n      \r\n      /* Set ADC state */\r\n      CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);   \r\n\r\n      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))\r\n      { \r\n        SET_BIT(hadc->State, HAL_ADC_STATE_READY);\r\n      }\r\n    }\r\n\r\n    /* Conversion complete callback */ \r\n    HAL_ADCEx_InjectedConvCpltCallback(hadc);\r\n    \r\n    /* Clear injected group conversion flag */\r\n    __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));\r\n  }\r\n  \r\n  tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD);\r\n  tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD);                          \r\n  /* Check Analog watchdog flag */\r\n  if(tmp1 && tmp2)\r\n  {\r\n    if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))\r\n    {\r\n      /* Set ADC state */\r\n      SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);\r\n      \r\n      /* Level out of window callback */ \r\n      HAL_ADC_LevelOutOfWindowCallback(hadc);\r\n      \r\n      /* Clear the ADC analog watchdog flag */\r\n      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);\r\n    }\r\n  }\r\n  \r\n  tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR);\r\n  tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR);\r\n  /* Check Overrun flag */\r\n  if(tmp1 && tmp2)\r\n  {\r\n    /* Note: On STM32F7, ADC overrun can be set through other parameters    */\r\n    /*       refer to description of parameter \"EOCSelection\" for more      */\r\n    /*       details.                                                       */\r\n    \r\n    /* Set ADC error code to overrun */\r\n    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);\r\n    \r\n    /* Clear ADC overrun flag */\r\n    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);\r\n    \r\n    /* Error callback */ \r\n    HAL_ADC_ErrorCallback(hadc);\r\n    \r\n    /* Clear the Overrun flag */\r\n    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral  \r\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @param  pData The destination Buffer address.\r\n  * @param  Length The length of data to be transferred from ADC peripheral to memory.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)\r\n{\r\n  __IO uint32_t counter = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));\r\n  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); \r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hadc);\r\n  \r\n  /* Enable the ADC peripheral */\r\n  /* Check if ADC peripheral is disabled in order to enable it and wait during \r\n     Tstab time the ADC's stabilization */\r\n  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)\r\n  {  \r\n    /* Enable the Peripheral */\r\n    __HAL_ADC_ENABLE(hadc);\r\n    \r\n    /* Delay for ADC stabilization time */\r\n    /* Compute number of CPU cycles to wait for */\r\n    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));\r\n    while(counter != 0)\r\n    {\r\n      counter--;\r\n    }\r\n  }\r\n  \r\n  /* Start conversion if ADC is effectively enabled */\r\n  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))\r\n  {\r\n    /* Set ADC state                                                          */\r\n    /* - Clear state bitfield related to regular group conversion results     */\r\n    /* - Set state bitfield related to regular group operation                */\r\n    ADC_STATE_CLR_SET(hadc->State,\r\n                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,\r\n                      HAL_ADC_STATE_REG_BUSY);\r\n    \r\n    /* If conversions on group regular are also triggering group injected,    */\r\n    /* update ADC state.                                                      */\r\n    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)\r\n    {\r\n      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  \r\n    }\r\n    \r\n    /* State machine update: Check if an injected conversion is ongoing */\r\n    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))\r\n    {\r\n      /* Reset ADC error code fields related to conversions on group regular */\r\n      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         \r\n    }\r\n    else\r\n    {\r\n      /* Reset ADC all error code fields */\r\n      ADC_CLEAR_ERRORCODE(hadc);\r\n    }\r\n    \r\n    /* Process unlocked */\r\n    /* Unlock before starting ADC conversions: in case of potential           */\r\n    /* interruption, to let the process to ADC IRQ Handler.                   */\r\n    __HAL_UNLOCK(hadc);   \r\n\r\n    /* Set the DMA transfer complete callback */\r\n    hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;\r\n\r\n    /* Set the DMA half transfer complete callback */\r\n    hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;\r\n    \r\n    /* Set the DMA error callback */\r\n    hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;\r\n\r\n    \r\n    /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */\r\n    /* start (in case of SW start):                                           */\r\n    \r\n    /* Clear regular group conversion flag and overrun flag */\r\n    /* (To ensure of no unknown state from potential previous ADC operations) */\r\n    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);\r\n\r\n    /* Enable ADC overrun interrupt */\r\n    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);\r\n    \r\n    /* Enable ADC DMA mode */\r\n    hadc->Instance->CR2 |= ADC_CR2_DMA;\r\n    \r\n    /* Start the DMA channel */\r\n    HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);\r\n    \r\n    /* Check if Multimode enabled */\r\n    if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))\r\n    {\r\n      /* if no external trigger present enable software conversion of regular channels */\r\n      if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) \r\n      {\r\n        /* Enable the selected ADC software conversion for regular group */\r\n        hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* if instance of handle correspond to ADC1 and  no external trigger present enable software conversion of regular channels */\r\n      if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))\r\n      {\r\n        /* Enable the selected ADC software conversion for regular group */\r\n          hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Disables ADC DMA (Single-ADC mode) and disables ADC peripheral    \r\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)\r\n{\r\n  HAL_StatusTypeDef tmp_hal_status = HAL_OK;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hadc);\r\n  \r\n  /* Stop potential conversion on going, on regular and injected groups */\r\n  /* Disable ADC peripheral */\r\n  __HAL_ADC_DISABLE(hadc);\r\n  \r\n  /* Check if ADC is effectively disabled */\r\n  if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))\r\n  {\r\n    /* Disable the selected ADC DMA mode */\r\n    hadc->Instance->CR2 &= ~ADC_CR2_DMA;\r\n    \r\n    /* Disable the DMA channel (in case of DMA in circular mode or stop while */\r\n    /* DMA transfer is on going)                                              */\r\n    tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);\r\n    \r\n    /* Disable ADC overrun interrupt */\r\n    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);\r\n    \r\n    /* Set ADC state */\r\n    ADC_STATE_CLR_SET(hadc->State,\r\n                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,\r\n                      HAL_ADC_STATE_READY);\r\n  }\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hadc);\r\n  \r\n  /* Return function status */\r\n  return tmp_hal_status;\r\n}\r\n\r\n/**\r\n  * @brief  Gets the converted value from data register of regular channel.\r\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @retval Converted value\r\n  */\r\nuint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)\r\n{       \r\n  /* Return the selected ADC converted value */ \r\n  return hadc->Instance->DR;\r\n}\r\n\r\n/**\r\n  * @brief  Regular conversion complete callback in non blocking mode \r\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hadc);\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_ADC_ConvCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Regular conversion half DMA transfer callback in non blocking mode \r\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hadc);\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Analog watchdog callback in non blocking mode \r\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hadc);\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Error ADC callback.\r\n  * @note   In case of error due to overrun when using ADC with DMA transfer \r\n  *         (HAL ADC handle paramater \"ErrorCode\" to state \"HAL_ADC_ERROR_OVR\"):\r\n  *         - Reinitialize the DMA using function \"HAL_ADC_Stop_DMA()\".\r\n  *         - If needed, restart a new ADC conversion using function\r\n  *           \"HAL_ADC_Start_DMA()\"\r\n  *           (this function is also clearing overrun flag)\r\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hadc);\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_ADC_ErrorCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions\r\n *  @brief   \tPeripheral Control functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n             ##### Peripheral Control functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Configure regular channels. \r\n      (+) Configure injected channels.\r\n      (+) Configure multimode.\r\n      (+) Configure the analog watch dog.\r\n      \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n  /**\r\n  * @brief  Configures for the selected ADC regular channel its corresponding\r\n  *         rank in the sequencer and its sample time.\r\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @param  sConfig ADC configuration structure. \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)\r\n{\r\n  __IO uint32_t counter = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_ADC_CHANNEL(sConfig->Channel));\r\n  assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));\r\n  assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hadc);\r\n\t\t\t\r\n\t/* if ADC_Channel_10 ... ADC_Channel_18 is selected */\r\n\tif (sConfig->Channel > ADC_CHANNEL_9)\r\n\t{\r\n\t\t/* Clear the old sample time */\r\n\t\thadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);\r\n\r\n\t\tif (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)\r\n\t\t{\r\n\t\t\t/* Set the new sample time */\r\n\t\t\thadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, ADC_CHANNEL_18);\r\n\t\t}\r\n\t  else\r\n\t  {\t\r\n\t\t  /* Set the new sample time */\r\n\t\t  hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);\r\n\t  }\r\n  }\r\n  else /* ADC_Channel include in ADC_Channel_[0..9] */\r\n  {\r\n    /* Clear the old sample time */\r\n    hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);\r\n    \r\n    /* Set the new sample time */\r\n    hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);\r\n  }\r\n  \r\n  /* For Rank 1 to 6 */\r\n  if (sConfig->Rank < 7)\r\n  {\r\n    /* Clear the old SQx bits for the selected rank */\r\n    hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);\r\n    \r\n    /* Set the SQx bits for the selected rank */\r\n    hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);\r\n  }\r\n  /* For Rank 7 to 12 */\r\n  else if (sConfig->Rank < 13)\r\n  {\r\n    /* Clear the old SQx bits for the selected rank */\r\n    hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);\r\n    \r\n    /* Set the SQx bits for the selected rank */\r\n    hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);\r\n  }\r\n  /* For Rank 13 to 16 */\r\n  else\r\n  {\r\n    /* Clear the old SQx bits for the selected rank */\r\n    hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);\r\n    \r\n    /* Set the SQx bits for the selected rank */\r\n    hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);\r\n  }\r\n  \r\n  /* if ADC1 Channel_18 is selected enable VBAT Channel */\r\n  if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))\r\n  {\r\n    /* Enable the VBAT channel*/\r\n    ADC->CCR |= ADC_CCR_VBATE;\r\n  }\r\n  \r\n  /* if ADC1 Channel_18 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */\r\n  if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)))\r\n  {\r\n    /* Enable the TSVREFE channel*/\r\n    ADC->CCR |= ADC_CCR_TSVREFE;\r\n\r\n    if(sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)\r\n    {\r\n      /* Delay for temperature sensor stabilization time */\r\n      /* Compute number of CPU cycles to wait for */\r\n      counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));\r\n      while(counter != 0)\r\n      {\r\n        counter--;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hadc);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Configures the analog watchdog.\r\n  * @note   Analog watchdog thresholds can be modified while ADC conversion\r\n  *         is on going.\r\n  *         In this case, some constraints must be taken into account:\r\n  *         the programmed threshold values are effective from the next\r\n  *         ADC EOC (end of unitary conversion).\r\n  *         Considering that registers write delay may happen due to\r\n  *         bus activity, this might cause an uncertainty on the\r\n  *         effective timing of the new programmed threshold values.\r\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @param  AnalogWDGConfig  pointer to an ADC_AnalogWDGConfTypeDef structure \r\n  *         that contains the configuration information of ADC analog watchdog.\r\n  * @retval HAL status\t  \r\n  */\r\nHAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)\r\n{\r\n#ifdef USE_FULL_ASSERT  \r\n  uint32_t tmp = 0;\r\n#endif /* USE_FULL_ASSERT  */  \r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_ADC_ANALOG_WATCHDOG(AnalogWDGConfig->WatchdogMode));\r\n  assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));\r\n  assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));\r\n\r\n#ifdef USE_FULL_ASSERT  \r\n  tmp = ADC_GET_RESOLUTION(hadc);\r\n  assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->HighThreshold));\r\n  assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->LowThreshold));\r\n#endif /* USE_FULL_ASSERT  */\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hadc);\r\n  \r\n  if(AnalogWDGConfig->ITMode == ENABLE)\r\n  {\r\n    /* Enable the ADC Analog watchdog interrupt */\r\n    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);\r\n  }\r\n  else\r\n  {\r\n    /* Disable the ADC Analog watchdog interrupt */\r\n    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);\r\n  }\r\n  \r\n  /* Clear AWDEN, JAWDEN and AWDSGL bits */\r\n  hadc->Instance->CR1 &=  ~(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN);\r\n  \r\n  /* Set the analog watchdog enable mode */\r\n  hadc->Instance->CR1 |= AnalogWDGConfig->WatchdogMode;\r\n  \r\n  /* Set the high threshold */\r\n  hadc->Instance->HTR = AnalogWDGConfig->HighThreshold;\r\n  \r\n  /* Set the low threshold */\r\n  hadc->Instance->LTR = AnalogWDGConfig->LowThreshold;\r\n  \r\n  /* Clear the Analog watchdog channel select bits */\r\n  hadc->Instance->CR1 &= ~ADC_CR1_AWDCH;\r\n  \r\n  /* Set the Analog watchdog channel */\r\n  hadc->Instance->CR1 |= (uint32_t)((uint16_t)(AnalogWDGConfig->Channel));\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hadc);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ADC_Exported_Functions_Group4 ADC Peripheral State functions\r\n *  @brief   ADC Peripheral State functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n            ##### Peripheral State and errors functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides functions allowing to\r\n      (+) Check the ADC state\r\n      (+) Check the ADC Error\r\n         \r\n@endverbatim\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @brief  return the ADC state\r\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @retval HAL state\r\n  */\r\nuint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)\r\n{\r\n  /* Return ADC state */\r\n  return hadc->State;\r\n}\r\n\r\n/**\r\n  * @brief  Return the ADC error code\r\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @retval ADC Error Code\r\n  */\r\nuint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)\r\n{\r\n  return hadc->ErrorCode;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup ADC_Private_Functions ADC Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the ADCx peripheral according to the specified parameters \r\n  *         in the ADC_InitStruct without initializing the ADC MSP.       \r\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.  \r\n  * @retval None\r\n  */\r\nstatic void ADC_Init(ADC_HandleTypeDef* hadc)\r\n{\r\n  /* Set ADC parameters */\r\n  /* Set the ADC clock prescaler */\r\n  ADC->CCR &= ~(ADC_CCR_ADCPRE);\r\n  ADC->CCR |=  hadc->Init.ClockPrescaler;\r\n  \r\n  /* Set ADC scan mode */\r\n  hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);\r\n  hadc->Instance->CR1 |=  ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);\r\n  \r\n  /* Set ADC resolution */\r\n  hadc->Instance->CR1 &= ~(ADC_CR1_RES);\r\n  hadc->Instance->CR1 |=  hadc->Init.Resolution;\r\n  \r\n  /* Set ADC data alignment */\r\n  hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);\r\n  hadc->Instance->CR2 |= hadc->Init.DataAlign;\r\n  \r\n  /* Enable external trigger if trigger selection is different of software  */\r\n  /* start.                                                                 */\r\n  /* Note: This configuration keeps the hardware feature of parameter       */\r\n  /*       ExternalTrigConvEdge \"trigger edge none\" equivalent to           */\r\n  /*       software start.                                                  */\r\n  if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)\r\n  {\r\n    /* Select external trigger to start conversion */\r\n    hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);\r\n    hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;\r\n    \r\n    /* Select external trigger polarity */\r\n    hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);\r\n    hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;\r\n  }\r\n  else\r\n  {\r\n    /* Reset the external trigger */\r\n    hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);\r\n    hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);\r\n  }\r\n  \r\n  /* Enable or disable ADC continuous conversion mode */\r\n  hadc->Instance->CR2 &= ~(ADC_CR2_CONT);\r\n  hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode);\r\n  \r\n  if(hadc->Init.DiscontinuousConvMode != DISABLE)\r\n  {\r\n    assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));\r\n  \r\n    /* Enable the selected ADC regular discontinuous mode */\r\n    hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN;\r\n    \r\n    /* Set the number of channels to be converted in discontinuous mode */\r\n    hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM);\r\n    hadc->Instance->CR1 |=  ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);\r\n  }\r\n  else\r\n  {\r\n    /* Disable the selected ADC regular discontinuous mode */\r\n    hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN);\r\n  }\r\n  \r\n  /* Set ADC number of conversion */\r\n  hadc->Instance->SQR1 &= ~(ADC_SQR1_L);\r\n  hadc->Instance->SQR1 |=  ADC_SQR1(hadc->Init.NbrOfConversion);\r\n  \r\n  /* Enable or disable ADC DMA continuous request */\r\n  hadc->Instance->CR2 &= ~(ADC_CR2_DDS);\r\n  hadc->Instance->CR2 |= ADC_CR2_DMAContReq(hadc->Init.DMAContinuousRequests);\r\n  \r\n  /* Enable or disable ADC end of conversion selection */\r\n  hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);\r\n  hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection);\r\n}\r\n\r\n/**\r\n  * @brief  DMA transfer complete callback. \r\n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)   \r\n{\r\n  /* Retrieve ADC handle corresponding to current DMA handle */\r\n  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  \r\n  /* Update state machine on conversion status if not in error state */\r\n  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))\r\n  {\r\n    /* Update ADC state machine */\r\n    SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);\r\n    \r\n    /* Determine whether any further conversion upcoming on group regular   */\r\n    /* by external trigger, continuous mode or scan sequence on going.      */\r\n    /* Note: On STM32F7, there is no independent flag of end of sequence.   */\r\n    /*       The test of scan sequence on going is done either with scan    */\r\n    /*       sequence disabled or with end of conversion flag set to        */\r\n    /*       of end of sequence.                                            */\r\n    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&\r\n       (hadc->Init.ContinuousConvMode == DISABLE)            &&\r\n       (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || \r\n        HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )\r\n    {\r\n      /* Disable ADC end of single conversion interrupt on group regular */\r\n      /* Note: Overrun interrupt was enabled with EOC interrupt in          */\r\n      /* HAL_ADC_Start_IT(), but is not disabled here because can be used   */\r\n      /* by overrun IRQ process below.                                      */\r\n      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);\r\n      \r\n      /* Set ADC state */\r\n      CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);   \r\n      \r\n      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))\r\n      {\r\n        SET_BIT(hadc->State, HAL_ADC_STATE_READY);\r\n      }\r\n    }\r\n    \r\n    /* Conversion complete callback */\r\n    HAL_ADC_ConvCpltCallback(hadc);\r\n  }\r\n  else\r\n  {\r\n    /* Call DMA error callback */\r\n    hadc->DMA_Handle->XferErrorCallback(hdma);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  DMA half transfer complete callback. \r\n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)   \r\n{\r\n  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  /* Conversion complete callback */\r\n  HAL_ADC_ConvHalfCpltCallback(hadc); \r\n}\r\n\r\n/**\r\n  * @brief  DMA error callback \r\n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void ADC_DMAError(DMA_HandleTypeDef *hdma)   \r\n{\r\n  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  hadc->State= HAL_ADC_STATE_ERROR_DMA;\r\n  /* Set ADC error code to DMA error */\r\n  hadc->ErrorCode |= HAL_ADC_ERROR_DMA;\r\n  HAL_ADC_ErrorCallback(hadc); \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_ADC_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_adc_ex.c\r\n  * @author  MCD Application Team\r\n  * @brief   This file provides firmware functions to manage the following \r\n  *          functionalities of the ADC extension peripheral:\r\n  *           + Extended features functions\r\n  *         \r\n  @verbatim\r\n  ==============================================================================\r\n                    ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]\r\n    (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():\r\n       (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()\r\n       (##) ADC pins configuration\r\n             (+++) Enable the clock for the ADC GPIOs using the following function:\r\n                   __HAL_RCC_GPIOx_CLK_ENABLE()  \r\n             (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init() \r\n       (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())\r\n             (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()\r\n             (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()\r\n             (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()\r\n      (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())\r\n             (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()\r\n             (+++) Configure and enable two DMA streams stream for managing data\r\n                 transfer from peripheral to memory (output stream)\r\n             (+++) Associate the initialized DMA handle to the ADC DMA handle\r\n                 using  __HAL_LINKDMA()\r\n             (+++) Configure the priority and enable the NVIC for the transfer complete\r\n                 interrupt on the two DMA Streams. The output stream should have higher\r\n                 priority than the input stream.                  \r\n     (#) Configure the ADC Prescaler, conversion resolution and data alignment \r\n         using the HAL_ADC_Init() function. \r\n  \r\n     (#) Configure the ADC Injected channels group features, use HAL_ADC_Init()\r\n         and HAL_ADC_ConfigChannel() functions.\r\n         \r\n     (#) Three operation modes are available within this driver :     \r\n  \r\n     *** Polling mode IO operation ***\r\n     =================================\r\n     [..]    \r\n       (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart() \r\n       (+) Wait for end of conversion using HAL_ADCEx_InjectedPollForConversion(), at this stage\r\n           user can specify the value of timeout according to his end application      \r\n       (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue() function.\r\n       (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop()\r\n  \r\n     *** Interrupt mode IO operation ***    \r\n     ===================================\r\n     [..]    \r\n       (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_IT() \r\n       (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine\r\n       (+) At ADC end of conversion HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can \r\n            add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback \r\n       (+) In case of ADC Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can \r\n            add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback\r\n       (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_IT()\r\n       \r\n            \r\n     *** DMA mode IO operation ***    \r\n     ==============================\r\n     [..]    \r\n       (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_DMA(), at this stage the user specify the length \r\n           of data to be transferred at each end of conversion \r\n       (+) At The end of data transfer ba HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can \r\n            add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback \r\n       (+) In case of transfer Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can \r\n            add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback\r\n        (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_DMA()\r\n        \r\n     *** Multi mode ADCs Regular channels configuration ***\r\n     ======================================================\r\n     [..]        \r\n       (+) Select the Multi mode ADC regular channels features (dual or triple mode)  \r\n          and configure the DMA mode using HAL_ADCEx_MultiModeConfigChannel() functions. \r\n       (+) Start the ADC peripheral using HAL_ADCEx_MultiModeStart_DMA(), at this stage the user specify the length \r\n           of data to be transferred at each end of conversion           \r\n       (+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue() function.\r\n  \r\n  \r\n    @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup ADCEx ADCEx\r\n  * @brief ADC Extended driver modules\r\n  * @{\r\n  */ \r\n\r\n#ifdef HAL_ADC_MODULE_ENABLED\r\n    \r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/ \r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @addtogroup ADCEx_Private_Functions\r\n  * @{\r\n  */\r\n/* Private function prototypes -----------------------------------------------*/\r\nstatic void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma);\r\nstatic void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma);\r\nstatic void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma); \r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup ADCEx_Exported_Functions ADC Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup ADCEx_Exported_Functions_Group1  Extended features functions \r\n  *  @brief    Extended features functions  \r\n  *\r\n@verbatim   \r\n ===============================================================================\r\n                 ##### Extended features functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Start conversion of injected channel.\r\n      (+) Stop conversion of injected channel.\r\n      (+) Start multimode and enable DMA transfer.\r\n      (+) Stop multimode and disable DMA transfer.\r\n      (+) Get result of injected channel conversion.\r\n      (+) Get result of multimode conversion.\r\n      (+) Configure injected channels.\r\n      (+) Configure multimode.\r\n               \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Enables the selected ADC software start conversion of the injected channels.\r\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)\r\n{\r\n  __IO uint32_t counter = 0;\r\n  uint32_t tmp1 = 0, tmp2 = 0;\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hadc);\r\n  \r\n  /* Enable the ADC peripheral */\r\n  \r\n  /* Check if ADC peripheral is disabled in order to enable it and wait during \r\n     Tstab time the ADC's stabilization */\r\n  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)\r\n  {  \r\n    /* Enable the Peripheral */\r\n    __HAL_ADC_ENABLE(hadc);\r\n    \r\n    /* Delay for ADC stabilization time */\r\n    /* Compute number of CPU cycles to wait for */\r\n    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));\r\n    while(counter != 0)\r\n    {\r\n      counter--;\r\n    }\r\n  }\r\n  \r\n  /* Start conversion if ADC is effectively enabled */\r\n  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))\r\n  {\r\n    /* Set ADC state                                                          */\r\n    /* - Clear state bitfield related to injected group conversion results    */\r\n    /* - Set state bitfield related to injected operation                     */\r\n    ADC_STATE_CLR_SET(hadc->State,\r\n                      HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,\r\n                      HAL_ADC_STATE_INJ_BUSY);\r\n    \r\n    /* Check if a regular conversion is ongoing */\r\n    /* Note: On this device, there is no ADC error code fields related to     */\r\n    /*       conversions on group injected only. In case of conversion on     */\r\n    /*       going on group regular, no error code is reset.                  */\r\n    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))\r\n    {\r\n      /* Reset ADC all error code fields */\r\n      ADC_CLEAR_ERRORCODE(hadc);\r\n    }\r\n    \r\n    /* Process unlocked */\r\n    /* Unlock before starting ADC conversions: in case of potential           */\r\n    /* interruption, to let the process to ADC IRQ Handler.                   */\r\n    __HAL_UNLOCK(hadc);\r\n    \r\n    /* Clear injected group conversion flag */\r\n    /* (To ensure of no unknown state from potential previous ADC operations) */\r\n    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);\r\n    \r\n    /* Check if Multimode enabled */\r\n    if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))\r\n    {\r\n      tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);\r\n      tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);\r\n      if(tmp1 && tmp2)\r\n      {\r\n        /* Enable the selected ADC software conversion for injected group */\r\n        hadc->Instance->CR2 |= ADC_CR2_JSWSTART;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);\r\n      tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);\r\n      if((hadc->Instance == ADC1) && tmp1 && tmp2)  \r\n      {\r\n        /* Enable the selected ADC software conversion for injected group */\r\n        hadc->Instance->CR2 |= ADC_CR2_JSWSTART;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Enables the interrupt and starts ADC conversion of injected channels.\r\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  *\r\n  * @retval HAL status.\r\n  */\r\nHAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)\r\n{\r\n  __IO uint32_t counter = 0;\r\n  uint32_t tmp1 = 0, tmp2 = 0;\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hadc);\r\n  \r\n  /* Enable the ADC peripheral */\r\n  \r\n  /* Check if ADC peripheral is disabled in order to enable it and wait during \r\n     Tstab time the ADC's stabilization */\r\n  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)\r\n  {  \r\n    /* Enable the Peripheral */\r\n    __HAL_ADC_ENABLE(hadc);\r\n    \r\n    /* Delay for ADC stabilization time */\r\n    /* Compute number of CPU cycles to wait for */\r\n    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));\r\n    while(counter != 0)\r\n    {\r\n      counter--;\r\n    }\r\n  }\r\n  \r\n  /* Start conversion if ADC is effectively enabled */\r\n  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))\r\n  {\r\n    /* Set ADC state                                                          */\r\n    /* - Clear state bitfield related to injected group conversion results    */\r\n    /* - Set state bitfield related to injected operation                     */\r\n    ADC_STATE_CLR_SET(hadc->State,\r\n                      HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,\r\n                      HAL_ADC_STATE_INJ_BUSY);\r\n    \r\n    /* Check if a regular conversion is ongoing */\r\n    /* Note: On this device, there is no ADC error code fields related to     */\r\n    /*       conversions on group injected only. In case of conversion on     */\r\n    /*       going on group regular, no error code is reset.                  */\r\n    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))\r\n    {\r\n      /* Reset ADC all error code fields */\r\n      ADC_CLEAR_ERRORCODE(hadc);\r\n    }\r\n    \r\n    /* Process unlocked */\r\n    /* Unlock before starting ADC conversions: in case of potential           */\r\n    /* interruption, to let the process to ADC IRQ Handler.                   */\r\n    __HAL_UNLOCK(hadc);\r\n    \r\n    /* Clear injected group conversion flag */\r\n    /* (To ensure of no unknown state from potential previous ADC operations) */\r\n    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);\r\n    \r\n    /* Enable end of conversion interrupt for injected channels */\r\n    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);\r\n    \r\n    /* Check if Multimode enabled */\r\n    if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))\r\n    {\r\n      tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);\r\n      tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);\r\n      if(tmp1 && tmp2)\r\n      {\r\n        /* Enable the selected ADC software conversion for injected group */\r\n        hadc->Instance->CR2 |= ADC_CR2_JSWSTART;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);\r\n      tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);\r\n      if((hadc->Instance == ADC1) && tmp1 && tmp2)  \r\n      {\r\n        /* Enable the selected ADC software conversion for injected group */\r\n        hadc->Instance->CR2 |= ADC_CR2_JSWSTART;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stop conversion of injected channels. Disable ADC peripheral if\r\n  *         no regular conversion is on going.\r\n  * @note   If ADC must be disabled and if conversion is on going on \r\n  *         regular group, function HAL_ADC_Stop must be used to stop both\r\n  *         injected and regular groups, and disable the ADC.\r\n  * @note   If injected group mode auto-injection is enabled,\r\n  *         function HAL_ADC_Stop must be used.\r\n  * @note   In case of auto-injection mode, HAL_ADC_Stop must be used.\r\n  * @param  hadc ADC handle\r\n  * @retval None\r\n  */\r\nHAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)\r\n{\r\n  HAL_StatusTypeDef tmp_hal_status = HAL_OK;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hadc);\r\n    \r\n  /* Stop potential conversion and disable ADC peripheral                     */\r\n  /* Conditioned to:                                                          */\r\n  /* - No conversion on the other group (regular group) is intended to        */\r\n  /*   continue (injected and regular groups stop conversion and ADC disable  */\r\n  /*   are common)                                                            */\r\n  /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */\r\n  if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET)  &&\r\n     HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )\r\n  {\r\n    /* Stop potential conversion on going, on regular and injected groups */\r\n    /* Disable ADC peripheral */\r\n    __HAL_ADC_DISABLE(hadc);\r\n    \r\n    /* Check if ADC is effectively disabled */\r\n    if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))\r\n    {\r\n      /* Set ADC state */\r\n      ADC_STATE_CLR_SET(hadc->State,\r\n                        HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,\r\n                        HAL_ADC_STATE_READY);\r\n    }\r\n  }\r\n  else\r\n  {\r\n    /* Update ADC state machine to error */\r\n    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);\r\n      \r\n    tmp_hal_status = HAL_ERROR;\r\n  }\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hadc);\r\n  \r\n  /* Return function status */\r\n  return tmp_hal_status;\r\n}\r\n\r\n/**\r\n  * @brief  Poll for injected conversion complete\r\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @param  Timeout Timeout value in millisecond.  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;\r\n\r\n  /* Get tick */ \r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Check End of conversion flag */\r\n  while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)))\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        hadc->State= HAL_ADC_STATE_TIMEOUT;\r\n        /* Process unlocked */\r\n        __HAL_UNLOCK(hadc);\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Clear injected group conversion flag */\r\n  __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC);\r\n    \r\n  /* Update ADC state machine */\r\n  SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);\r\n  \r\n  /* Determine whether any further conversion upcoming on group injected      */\r\n  /* by external trigger, continuous mode or scan sequence on going.          */\r\n  /* Note: On STM32F7, there is no independent flag of end of sequence.       */\r\n  /*       The test of scan sequence on going is done either with scan        */\r\n  /*       sequence disabled or with end of conversion flag set to            */\r\n  /*       of end of sequence.                                                */\r\n  if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                    &&\r\n     (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL)  ||\r\n      HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)    ) &&\r\n     (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&\r\n      (ADC_IS_SOFTWARE_START_REGULAR(hadc)       &&\r\n      (hadc->Init.ContinuousConvMode == DISABLE)   )       )   )\r\n  {\r\n    /* Set ADC state */\r\n    CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);\r\n    \r\n    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))\r\n    { \r\n      SET_BIT(hadc->State, HAL_ADC_STATE_READY);\r\n    }\r\n  }\r\n  \r\n  /* Return ADC state */\r\n  return HAL_OK;\r\n}      \r\n  \r\n/**\r\n  * @brief  Stop conversion of injected channels, disable interruption of \r\n  *         end-of-conversion. Disable ADC peripheral if no regular conversion\r\n  *         is on going.\r\n  * @note   If ADC must be disabled and if conversion is on going on \r\n  *         regular group, function HAL_ADC_Stop must be used to stop both\r\n  *         injected and regular groups, and disable the ADC.\r\n  * @note   If injected group mode auto-injection is enabled,\r\n  *         function HAL_ADC_Stop must be used.\r\n  * @param  hadc ADC handle\r\n  * @retval None\r\n  */\r\nHAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)\r\n{\r\n  HAL_StatusTypeDef tmp_hal_status = HAL_OK;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hadc);\r\n    \r\n  /* Stop potential conversion and disable ADC peripheral                     */\r\n  /* Conditioned to:                                                          */\r\n  /* - No conversion on the other group (regular group) is intended to        */\r\n  /*   continue (injected and regular groups stop conversion and ADC disable  */\r\n  /*   are common)                                                            */\r\n  /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */ \r\n  if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET)  &&\r\n     HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )\r\n  {\r\n    /* Stop potential conversion on going, on regular and injected groups */\r\n    /* Disable ADC peripheral */\r\n    __HAL_ADC_DISABLE(hadc);\r\n    \r\n    /* Check if ADC is effectively disabled */\r\n    if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))\r\n    {\r\n      /* Disable ADC end of conversion interrupt for injected channels */\r\n      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);\r\n      \r\n      /* Set ADC state */\r\n      ADC_STATE_CLR_SET(hadc->State,\r\n                        HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,\r\n                        HAL_ADC_STATE_READY);\r\n    }\r\n  }\r\n  else\r\n  {\r\n    /* Update ADC state machine to error */\r\n    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);\r\n      \r\n    tmp_hal_status = HAL_ERROR;\r\n  }\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hadc);\r\n  \r\n  /* Return function status */\r\n  return tmp_hal_status;\r\n}\r\n\r\n/**\r\n  * @brief  Gets the converted value from data register of injected channel.\r\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @param  InjectedRank the ADC injected rank.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg ADC_INJECTED_RANK_1: Injected Channel1 selected\r\n  *            @arg ADC_INJECTED_RANK_2: Injected Channel2 selected\r\n  *            @arg ADC_INJECTED_RANK_3: Injected Channel3 selected\r\n  *            @arg ADC_INJECTED_RANK_4: Injected Channel4 selected\r\n  * @retval None\r\n  */\r\nuint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)\r\n{\r\n  __IO uint32_t tmp = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_ADC_INJECTED_RANK(InjectedRank));\r\n  \r\n  /* Clear injected group conversion flag to have similar behaviour as        */\r\n  /* regular group: reading data register also clears end of conversion flag. */\r\n  __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);\r\n  \r\n  /* Return the selected ADC converted value */ \r\n  switch(InjectedRank)\r\n  {  \r\n    case ADC_INJECTED_RANK_4:\r\n    {\r\n      tmp =  hadc->Instance->JDR4;\r\n    }  \r\n    break;\r\n    case ADC_INJECTED_RANK_3: \r\n    {  \r\n      tmp =  hadc->Instance->JDR3;\r\n    }  \r\n    break;\r\n    case ADC_INJECTED_RANK_2: \r\n    {  \r\n      tmp =  hadc->Instance->JDR2;\r\n    }\r\n    break;\r\n    case ADC_INJECTED_RANK_1:\r\n    {\r\n      tmp =  hadc->Instance->JDR1;\r\n    }\r\n    break;\r\n    default:\r\n    break;  \r\n  }\r\n  return tmp;\r\n}\r\n\r\n/**\r\n  * @brief  Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral\r\n  * \r\n  * @note   Caution: This function must be used only with the ADC master.  \r\n  *\r\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @param  pData   Pointer to buffer in which transferred from ADC peripheral to memory will be stored. \r\n  * @param  Length  The length of data to be transferred from ADC peripheral to memory.  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)\r\n{\r\n  __IO uint32_t counter = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));\r\n  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));\r\n  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hadc);\r\n  \r\n  /* Check if ADC peripheral is disabled in order to enable it and wait during \r\n     Tstab time the ADC's stabilization */\r\n  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)\r\n  {  \r\n    /* Enable the Peripheral */\r\n    __HAL_ADC_ENABLE(hadc);\r\n    \r\n    /* Delay for temperature sensor stabilization time */\r\n    /* Compute number of CPU cycles to wait for */\r\n    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));\r\n    while(counter != 0)\r\n    {\r\n      counter--;\r\n    }\r\n  }\r\n  \r\n  /* Start conversion if ADC is effectively enabled */\r\n  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))\r\n  {\r\n    /* Set ADC state                                                          */\r\n    /* - Clear state bitfield related to regular group conversion results     */\r\n    /* - Set state bitfield related to regular group operation                */\r\n    ADC_STATE_CLR_SET(hadc->State,\r\n                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,\r\n                      HAL_ADC_STATE_REG_BUSY);\r\n    \r\n    /* If conversions on group regular are also triggering group injected,    */\r\n    /* update ADC state.                                                      */\r\n    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)\r\n    {\r\n      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  \r\n    }\r\n    \r\n    /* State machine update: Check if an injected conversion is ongoing */\r\n    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))\r\n    {\r\n      /* Reset ADC error code fields related to conversions on group regular */\r\n      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         \r\n    }\r\n    else\r\n    {\r\n      /* Reset ADC all error code fields */\r\n      ADC_CLEAR_ERRORCODE(hadc);\r\n    }\r\n    \r\n    /* Process unlocked */\r\n    /* Unlock before starting ADC conversions: in case of potential           */\r\n    /* interruption, to let the process to ADC IRQ Handler.                   */\r\n    __HAL_UNLOCK(hadc);\r\n    \r\n    /* Set the DMA transfer complete callback */\r\n    hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt;\r\n    \r\n    /* Set the DMA half transfer complete callback */\r\n    hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt;\r\n    \r\n    /* Set the DMA error callback */\r\n    hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ;\r\n    \r\n    /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */\r\n    /* start (in case of SW start):                                           */\r\n    \r\n    /* Clear regular group conversion flag and overrun flag */\r\n    /* (To ensure of no unknown state from potential previous ADC operations) */\r\n    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);\r\n\r\n    /* Enable ADC overrun interrupt */\r\n    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);\r\n    \r\n    if (hadc->Init.DMAContinuousRequests != DISABLE)\r\n    {\r\n      /* Enable the selected ADC DMA request after last transfer */\r\n      ADC->CCR |= ADC_CCR_DDS;\r\n    }\r\n    else\r\n    {\r\n      /* Disable the selected ADC EOC rising on each regular channel conversion */\r\n      ADC->CCR &= ~ADC_CCR_DDS;\r\n    }\r\n    \r\n    /* Enable the DMA Stream */\r\n    HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length);\r\n    \r\n    /* if no external trigger present enable software conversion of regular channels */\r\n    if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) \r\n    {\r\n      /* Enable the selected ADC software conversion for regular group */\r\n      hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Disables ADC DMA (multi-ADC mode) and disables ADC peripheral    \r\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)\r\n{\r\n  HAL_StatusTypeDef tmp_hal_status = HAL_OK;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hadc);\r\n  \r\n  /* Stop potential conversion on going, on regular and injected groups */\r\n  /* Disable ADC peripheral */\r\n  __HAL_ADC_DISABLE(hadc);\r\n  \r\n  /* Check if ADC is effectively disabled */\r\n  if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))\r\n  {\r\n    /* Disable the selected ADC DMA mode for multimode */\r\n    ADC->CCR &= ~ADC_CCR_DDS;\r\n    \r\n    /* Disable the DMA channel (in case of DMA in circular mode or stop while */\r\n    /* DMA transfer is on going)                                              */\r\n    tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);\r\n    \r\n    /* Disable ADC overrun interrupt */\r\n    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);\r\n    \r\n    /* Set ADC state */\r\n    ADC_STATE_CLR_SET(hadc->State,\r\n                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,\r\n                      HAL_ADC_STATE_READY);\r\n  }\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hadc);\r\n  \r\n  /* Return function status */\r\n  return tmp_hal_status;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the last ADC1, ADC2 and ADC3 regular conversions results \r\n  *         data in the selected multi mode.\r\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @retval The converted data value.\r\n  */\r\nuint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)\r\n{\r\n  UNUSED(hadc);\r\n  /* Return the multi mode conversion value */\r\n  return ADC->CDR;\r\n}\r\n\r\n/**\r\n  * @brief  Injected conversion complete callback in non blocking mode \r\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hadc);\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_ADC_InjectedConvCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Configures for the selected ADC injected channel its corresponding\r\n  *         rank in the sequencer and its sample time.\r\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @param  sConfigInjected ADC configuration structure for injected channel. \r\n  * @retval None\r\n  */\r\nHAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)\r\n{\r\n  \r\n#ifdef USE_FULL_ASSERT  \r\n  uint32_t tmp = 0;\r\n#endif /* USE_FULL_ASSERT  */\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));\r\n  assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));\r\n  assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));\r\n  assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv));\r\n  assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion));\r\n  assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));\r\n  assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));\r\n\r\n#ifdef USE_FULL_ASSERT\r\n  tmp = ADC_GET_RESOLUTION(hadc);\r\n  assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset));\r\n#endif /* USE_FULL_ASSERT  */\r\n\r\n  if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)\r\n  {\r\n    assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));\r\n  }\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hadc);\r\n  \r\n  /* if ADC_Channel_10 ... ADC_Channel_18 is selected */\r\n  if (sConfigInjected->InjectedChannel > ADC_CHANNEL_9)\r\n  {\r\n    /* Clear the old sample time */\r\n    hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel);\r\n    \r\n    /* Set the new sample time */\r\n    hadc->Instance->SMPR1 |= ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);\r\n  }\r\n  else /* ADC_Channel include in ADC_Channel_[0..9] */\r\n  {\r\n    /* Clear the old sample time */\r\n    hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel);\r\n    \r\n    /* Set the new sample time */\r\n    hadc->Instance->SMPR2 |= ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);\r\n  }\r\n  \r\n  /*---------------------------- ADCx JSQR Configuration -----------------*/\r\n  hadc->Instance->JSQR &= ~(ADC_JSQR_JL);\r\n  hadc->Instance->JSQR |=  ADC_SQR1(sConfigInjected->InjectedNbrOfConversion);\r\n  \r\n  /* Rank configuration */\r\n  \r\n  /* Clear the old SQx bits for the selected rank */\r\n  hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);\r\n   \r\n  /* Set the SQx bits for the selected rank */\r\n  hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);\r\n\r\n  /* Enable external trigger if trigger selection is different of software  */\r\n  /* start.                                                                 */\r\n  /* Note: This configuration keeps the hardware feature of parameter       */\r\n  /*       ExternalTrigConvEdge \"trigger edge none\" equivalent to           */\r\n  /*       software start.                                                  */ \r\n  if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)\r\n  {  \r\n    /* Select external trigger to start conversion */\r\n    hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);\r\n    hadc->Instance->CR2 |=  sConfigInjected->ExternalTrigInjecConv;\r\n    \r\n    /* Select external trigger polarity */\r\n    hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);\r\n    hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge;\r\n  }\r\n  else\r\n  {\r\n    /* Reset the external trigger */\r\n    hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);\r\n    hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);  \r\n  }\r\n  \r\n  if (sConfigInjected->AutoInjectedConv != DISABLE)\r\n  {\r\n    /* Enable the selected ADC automatic injected group conversion */\r\n    hadc->Instance->CR1 |= ADC_CR1_JAUTO;\r\n  }\r\n  else\r\n  {\r\n    /* Disable the selected ADC automatic injected group conversion */\r\n    hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO);\r\n  }\r\n  \r\n  if (sConfigInjected->InjectedDiscontinuousConvMode != DISABLE)\r\n  {\r\n    /* Enable the selected ADC injected discontinuous mode */\r\n    hadc->Instance->CR1 |= ADC_CR1_JDISCEN;\r\n  }\r\n  else\r\n  {\r\n    /* Disable the selected ADC injected discontinuous mode */\r\n    hadc->Instance->CR1 &= ~(ADC_CR1_JDISCEN);\r\n  }\r\n  \r\n  switch(sConfigInjected->InjectedRank)\r\n  {\r\n    case 1:\r\n      /* Set injected channel 1 offset */\r\n      hadc->Instance->JOFR1 &= ~(ADC_JOFR1_JOFFSET1);\r\n      hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset;\r\n      break;\r\n    case 2:\r\n      /* Set injected channel 2 offset */\r\n      hadc->Instance->JOFR2 &= ~(ADC_JOFR2_JOFFSET2);\r\n      hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset;\r\n      break;\r\n    case 3:\r\n      /* Set injected channel 3 offset */\r\n      hadc->Instance->JOFR3 &= ~(ADC_JOFR3_JOFFSET3);\r\n      hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset;\r\n      break;\r\n    default:\r\n      /* Set injected channel 4 offset */\r\n      hadc->Instance->JOFR4 &= ~(ADC_JOFR4_JOFFSET4);\r\n      hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset;\r\n      break;\r\n  }\r\n  \r\n  /* if ADC1 Channel_18 is selected enable VBAT Channel */\r\n  if ((hadc->Instance == ADC1) && (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT))\r\n  {\r\n    /* Enable the VBAT channel*/\r\n    ADC->CCR |= ADC_CCR_VBATE;\r\n  }\r\n  \r\n  /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */\r\n  if ((hadc->Instance == ADC1) && ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)))\r\n  {\r\n    /* Enable the TSVREFE channel*/\r\n    ADC->CCR |= ADC_CCR_TSVREFE;\r\n  }\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hadc);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Configures the ADC multi-mode \r\n  * @param  hadc       pointer to a ADC_HandleTypeDef structure that contains\r\n  *                     the configuration information for the specified ADC.  \r\n  * @param  multimode  pointer to an ADC_MultiModeTypeDef structure that contains \r\n  *                     the configuration information for  multimode.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_ADC_MODE(multimode->Mode));\r\n  assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode));\r\n  assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hadc);\r\n  \r\n  /* Set ADC mode */\r\n  ADC->CCR &= ~(ADC_CCR_MULTI);\r\n  ADC->CCR |= multimode->Mode;\r\n  \r\n  /* Set the ADC DMA access mode */\r\n  ADC->CCR &= ~(ADC_CCR_DMA);\r\n  ADC->CCR |= multimode->DMAAccessMode;\r\n  \r\n  /* Set delay between two sampling phases */\r\n  ADC->CCR &= ~(ADC_CCR_DELAY);\r\n  ADC->CCR |= multimode->TwoSamplingDelay;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hadc);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n  /**\r\n  * @brief  DMA transfer complete callback. \r\n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma)   \r\n{\r\n  /* Retrieve ADC handle corresponding to current DMA handle */\r\n  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  \r\n  /* Update state machine on conversion status if not in error state */\r\n  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))\r\n  {\r\n    /* Update ADC state machine */\r\n    SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);\r\n    \r\n    /* Determine whether any further conversion upcoming on group regular   */\r\n    /* by external trigger, continuous mode or scan sequence on going.      */\r\n    /* Note: On STM32F7, there is no independent flag of end of sequence.   */\r\n    /*       The test of scan sequence on going is done either with scan    */\r\n    /*       sequence disabled or with end of conversion flag set to        */\r\n    /*       of end of sequence.                                            */\r\n    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&\r\n       (hadc->Init.ContinuousConvMode == DISABLE)            &&\r\n       (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || \r\n        HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )\r\n    {\r\n      /* Disable ADC end of single conversion interrupt on group regular */\r\n      /* Note: Overrun interrupt was enabled with EOC interrupt in          */\r\n      /* HAL_ADC_Start_IT(), but is not disabled here because can be used   */\r\n      /* by overrun IRQ process below.                                      */\r\n      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);\r\n      \r\n      /* Set ADC state */\r\n      CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);   \r\n      \r\n      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))\r\n      {\r\n        SET_BIT(hadc->State, HAL_ADC_STATE_READY);\r\n      }\r\n    }\r\n    \r\n    /* Conversion complete callback */\r\n    HAL_ADC_ConvCpltCallback(hadc);\r\n  }\r\n  else\r\n  {\r\n    /* Call DMA error callback */\r\n    hadc->DMA_Handle->XferErrorCallback(hdma);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  DMA half transfer complete callback. \r\n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma)   \r\n{\r\n    ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n    /* Conversion complete callback */\r\n    HAL_ADC_ConvHalfCpltCallback(hadc); \r\n}\r\n\r\n/**\r\n  * @brief  DMA error callback \r\n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma)   \r\n{\r\n    ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n    hadc->State= HAL_ADC_STATE_ERROR_DMA;\r\n    /* Set ADC error code to DMA error */\r\n    hadc->ErrorCode |= HAL_ADC_ERROR_DMA;\r\n    HAL_ADC_ErrorCallback(hadc); \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_ADC_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_can.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_can.c\r\n  * @author  MCD Application Team\r\n  * @brief   CAN HAL module driver.\r\n  *          This file provides firmware functions to manage the following\r\n  *          functionalities of the Controller Area Network (CAN) peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + Configuration functions\r\n  *           + Control functions\r\n  *           + Interrupts management\r\n  *           + Callbacks functions\r\n  *           + Peripheral State and Error functions\r\n  *\r\n  @verbatim\r\n  ==============================================================================\r\n                        ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]\r\n      (#) Initialize the CAN low level resources by implementing the\r\n          HAL_CAN_MspInit():\r\n         (++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE()\r\n         (++) Configure CAN pins\r\n             (+++) Enable the clock for the CAN GPIOs\r\n             (+++) Configure CAN pins as alternate function open-drain\r\n         (++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification())\r\n             (+++) Configure the CAN interrupt priority using\r\n                   HAL_NVIC_SetPriority()\r\n             (+++) Enable the CAN IRQ handler using HAL_NVIC_EnableIRQ()\r\n             (+++) In CAN IRQ handler, call HAL_CAN_IRQHandler()\r\n\r\n      (#) Initialize the CAN peripheral using HAL_CAN_Init() function. This\r\n          function resorts to HAL_CAN_MspInit() for low-level initialization.\r\n\r\n      (#) Configure the reception filters using the following configuration\r\n          functions:\r\n            (++) HAL_CAN_ConfigFilter()\r\n\r\n      (#) Start the CAN module using HAL_CAN_Start() function. At this level\r\n          the node is active on the bus: it receive messages, and can send\r\n          messages.\r\n\r\n      (#) To manage messages transmission, the following Tx control functions\r\n          can be used:\r\n            (++) HAL_CAN_AddTxMessage() to request transmission of a new\r\n                 message.\r\n            (++) HAL_CAN_AbortTxRequest() to abort transmission of a pending\r\n                 message.\r\n            (++) HAL_CAN_GetTxMailboxesFreeLevel() to get the number of free Tx\r\n                 mailboxes.\r\n            (++) HAL_CAN_IsTxMessagePending() to check if a message is pending\r\n                 in a Tx mailbox.\r\n            (++) HAL_CAN_GetTxTimestamp() to get the timestamp of Tx message\r\n                 sent, if time triggered communication mode is enabled.\r\n\r\n      (#) When a message is received into the CAN Rx FIFOs, it can be retrieved\r\n          using the HAL_CAN_GetRxMessage() function. The function\r\n          HAL_CAN_GetRxFifoFillLevel() allows to know how many Rx message are\r\n          stored in the Rx Fifo.\r\n\r\n      (#) Calling the HAL_CAN_Stop() function stops the CAN module.\r\n\r\n      (#) The deinitialization is achieved with HAL_CAN_DeInit() function.\r\n\r\n\r\n      *** Polling mode operation ***\r\n      ==============================\r\n    [..]\r\n      (#) Reception:\r\n            (++) Monitor reception of message using HAL_CAN_GetRxFifoFillLevel()\r\n                 until at least one message is received.\r\n            (++) Then get the message using HAL_CAN_GetRxMessage().\r\n\r\n      (#) Transmission:\r\n            (++) Monitor the Tx mailboxes availability until at least one Tx\r\n                 mailbox is free, using HAL_CAN_GetTxMailboxesFreeLevel().\r\n            (++) Then request transmission of a message using\r\n                 HAL_CAN_AddTxMessage().\r\n\r\n\r\n      *** Interrupt mode operation ***\r\n      ================================\r\n    [..]\r\n      (#) Notifications are activated using HAL_CAN_ActivateNotification()\r\n          function. Then, the process can be controlled through the\r\n          available user callbacks: HAL_CAN_xxxCallback(), using same APIs\r\n          HAL_CAN_GetRxMessage() and HAL_CAN_AddTxMessage().\r\n\r\n      (#) Notifications can be deactivated using\r\n          HAL_CAN_DeactivateNotification() function.\r\n\r\n      (#) Special care should be taken for CAN_IT_RX_FIFO0_MSG_PENDING and\r\n          CAN_IT_RX_FIFO1_MSG_PENDING notifications. These notifications trig\r\n          the callbacks HAL_CAN_RxFIFO0MsgPendingCallback() and\r\n          HAL_CAN_RxFIFO1MsgPendingCallback(). User has two possible options\r\n          here.\r\n            (++) Directly get the Rx message in the callback, using\r\n                 HAL_CAN_GetRxMessage().\r\n            (++) Or deactivate the notification in the callback without\r\n                 getting the Rx message. The Rx message can then be got later\r\n                 using HAL_CAN_GetRxMessage(). Once the Rx message have been\r\n                 read, the notification can be activated again.\r\n\r\n\r\n      *** Sleep mode ***\r\n      ==================\r\n    [..]\r\n      (#) The CAN peripheral can be put in sleep mode (low power), using\r\n          HAL_CAN_RequestSleep(). The sleep mode will be entered as soon as the\r\n          current CAN activity (transmission or reception of a CAN frame) will\r\n          be completed.\r\n\r\n      (#) A notification can be activated to be informed when the sleep mode\r\n          will be entered.\r\n\r\n      (#) It can be checked if the sleep mode is entered using\r\n          HAL_CAN_IsSleepActive().\r\n          Note that the CAN state (accessible from the API HAL_CAN_GetState())\r\n          is HAL_CAN_STATE_SLEEP_PENDING as soon as the sleep mode request is\r\n          submitted (the sleep mode is not yet entered), and become\r\n          HAL_CAN_STATE_SLEEP_ACTIVE when the sleep mode is effective.\r\n\r\n      (#) The wake-up from sleep mode can be trigged by two ways:\r\n            (++) Using HAL_CAN_WakeUp(). When returning from this function,\r\n                 the sleep mode is exited (if return status is HAL_OK).\r\n            (++) When a start of Rx CAN frame is detected by the CAN peripheral,\r\n                 if automatic wake up mode is enabled.\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n#if defined(CAN1)\r\n\r\n/** @defgroup CAN CAN\r\n  * @brief CAN driver modules\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_CAN_MODULE_ENABLED\r\n\r\n#ifdef HAL_CAN_LEGACY_MODULE_ENABLED\r\n  #error \"The CAN driver cannot be used with its legacy, Please enable only one CAN module at once\"\r\n#endif\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @defgroup CAN_Private_Constants CAN Private Constants\r\n  * @{\r\n  */\r\n#define CAN_TIMEOUT_VALUE 10U\r\n/**\r\n  * @}\r\n  */\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @defgroup CAN_Exported_Functions CAN Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions\r\n *  @brief    Initialization and Configuration functions\r\n *\r\n@verbatim\r\n  ==============================================================================\r\n              ##### Initialization and de-initialization functions #####\r\n  ==============================================================================\r\n    [..]  This section provides functions allowing to:\r\n      (+) HAL_CAN_Init                       : Initialize and configure the CAN.\r\n      (+) HAL_CAN_DeInit                     : De-initialize the CAN.\r\n      (+) HAL_CAN_MspInit                    : Initialize the CAN MSP.\r\n      (+) HAL_CAN_MspDeInit                  : DeInitialize the CAN MSP.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the CAN peripheral according to the specified\r\n  *         parameters in the CAN_InitStruct.\r\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)\r\n{\r\n  uint32_t tickstart = 0U;\r\n\r\n  /* Check CAN handle */\r\n  if (hcan == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));\r\n  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TimeTriggeredMode));\r\n  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoBusOff));\r\n  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoWakeUp));\r\n  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoRetransmission));\r\n  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ReceiveFifoLocked));\r\n  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TransmitFifoPriority));\r\n  assert_param(IS_CAN_MODE(hcan->Init.Mode));\r\n  assert_param(IS_CAN_SJW(hcan->Init.SyncJumpWidth));\r\n  assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1));\r\n  assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2));\r\n  assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));\r\n\r\n  if (hcan->State == HAL_CAN_STATE_RESET)\r\n  {\r\n    /* Init the low level hardware: CLOCK, NVIC */\r\n    HAL_CAN_MspInit(hcan);\r\n  }\r\n\r\n  /* Exit from sleep mode */\r\n  CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);\r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Check Sleep mode leave acknowledge */\r\n  while ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET)\r\n  {\r\n    if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)\r\n    {\r\n      /* Update error code */\r\n      hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;\r\n\r\n      /* Change CAN state */\r\n      hcan->State = HAL_CAN_STATE_ERROR;\r\n\r\n      return HAL_ERROR;\r\n    }\r\n  }\r\n\r\n  /* Request initialisation */\r\n  SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);\r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Wait initialisation acknowledge */\r\n  while ((hcan->Instance->MSR & CAN_MSR_INAK) == RESET)\r\n  {\r\n    if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)\r\n    {\r\n      /* Update error code */\r\n      hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;\r\n\r\n      /* Change CAN state */\r\n      hcan->State = HAL_CAN_STATE_ERROR;\r\n\r\n      return HAL_ERROR;\r\n    }\r\n  }\r\n\r\n  /* Set the time triggered communication mode */\r\n  if (hcan->Init.TimeTriggeredMode == ENABLE)\r\n  {\r\n    SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);\r\n  }\r\n  else\r\n  {\r\n    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);\r\n  }\r\n\r\n  /* Set the automatic bus-off management */\r\n  if (hcan->Init.AutoBusOff == ENABLE)\r\n  {\r\n    SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);\r\n  }\r\n  else\r\n  {\r\n    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);\r\n  }\r\n\r\n  /* Set the automatic wake-up mode */\r\n  if (hcan->Init.AutoWakeUp == ENABLE)\r\n  {\r\n    SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);\r\n  }\r\n  else\r\n  {\r\n    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);\r\n  }\r\n\r\n  /* Set the automatic retransmission */\r\n  if (hcan->Init.AutoRetransmission == ENABLE)\r\n  {\r\n    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART);\r\n  }\r\n  else\r\n  {\r\n    SET_BIT(hcan->Instance->MCR, CAN_MCR_NART);\r\n  }\r\n\r\n  /* Set the receive FIFO locked mode */\r\n  if (hcan->Init.ReceiveFifoLocked == ENABLE)\r\n  {\r\n    SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);\r\n  }\r\n  else\r\n  {\r\n    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);\r\n  }\r\n\r\n  /* Set the transmit FIFO priority */\r\n  if (hcan->Init.TransmitFifoPriority == ENABLE)\r\n  {\r\n    SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);\r\n  }\r\n  else\r\n  {\r\n    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);\r\n  }\r\n\r\n  /* Set the bit timing register */\r\n  WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode           |\r\n                                            hcan->Init.SyncJumpWidth  |\r\n                                            hcan->Init.TimeSeg1       |\r\n                                            hcan->Init.TimeSeg2       |\r\n                                            (hcan->Init.Prescaler - 1U)));\r\n\r\n  /* Initialize the error code */\r\n  hcan->ErrorCode = HAL_CAN_ERROR_NONE;\r\n\r\n  /* Initialize the CAN state */\r\n  hcan->State = HAL_CAN_STATE_READY;\r\n\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Deinitializes the CAN peripheral registers to their default\r\n  *         reset values.\r\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan)\r\n{\r\n  /* Check CAN handle */\r\n  if (hcan == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));\r\n\r\n  /* Stop the CAN module */\r\n  HAL_CAN_Stop(hcan);\r\n\r\n  /* DeInit the low level hardware: CLOCK, NVIC */\r\n  HAL_CAN_MspDeInit(hcan);\r\n\r\n  /* Reset the CAN peripheral */\r\n  SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET);\r\n\r\n  /* Reset the CAN ErrorCode */\r\n  hcan->ErrorCode = HAL_CAN_ERROR_NONE;\r\n\r\n  /* Change CAN state */\r\n  hcan->State = HAL_CAN_STATE_RESET;\r\n\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CAN MSP.\r\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @retval None\r\n  */\r\n__weak void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcan);\r\n\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_CAN_MspInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the CAN MSP.\r\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @retval None\r\n  */\r\n__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcan);\r\n\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_CAN_MspDeInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CAN_Exported_Functions_Group2 Configuration functions\r\n *  @brief    Configuration functions.\r\n *\r\n@verbatim\r\n  ==============================================================================\r\n              ##### Configuration functions #####\r\n  ==============================================================================\r\n    [..]  This section provides functions allowing to:\r\n      (+) HAL_CAN_ConfigFilter            : Configure the CAN reception filters\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Configures the CAN reception filter according to the specified\r\n  *         parameters in the CAN_FilterInitStruct.\r\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @param  sFilterConfig pointer to a CAN_FilterTypeDef structure that\r\n  *         contains the filter configuration information.\r\n  * @retval None\r\n  */\r\nHAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig)\r\n{\r\n  uint32_t filternbrbitpos = 0U;\r\n  CAN_TypeDef *can_ip = hcan->Instance;\r\n\r\n  if ((hcan->State == HAL_CAN_STATE_READY) ||\r\n      (hcan->State == HAL_CAN_STATE_LISTENING))\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh));\r\n    assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdLow));\r\n    assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdHigh));\r\n    assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdLow));\r\n    assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));\r\n    assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));\r\n    assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));\r\n    assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));\r\n\r\n#if defined(CAN3)\r\n    /* Check the CAN instance */\r\n    if (hcan->Instance == CAN3)\r\n    {\r\n      /* CAN3 is single instance with 14 dedicated filters banks */\r\n\r\n      /* Check the parameters */\r\n      assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));\r\n    }\r\n    else\r\n    {\r\n      /* CAN1 and CAN2 are dual instances with 28 common filters banks */\r\n      /* Select master instance to access the filter banks */\r\n      can_ip = CAN1;\r\n\r\n      /* Check the parameters */\r\n      assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank));\r\n      assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank));\r\n    }\r\n#elif defined(CAN2)\r\n    /* CAN1 and CAN2 are dual instances with 28 common filters banks */\r\n    /* Select master instance to access the filter banks */\r\n    can_ip = CAN1;\r\n\r\n    /* Check the parameters */\r\n    assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank));\r\n    assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank));\r\n#else\r\n    /* CAN1 is single instance with 14 dedicated filters banks */\r\n\r\n    /* Check the parameters */\r\n    assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));\r\n#endif\r\n\r\n    /* Initialisation mode for the filter */\r\n    SET_BIT(can_ip->FMR, CAN_FMR_FINIT);\r\n\r\n#if defined(CAN3)\r\n    /* Check the CAN instance */\r\n    if (can_ip == CAN1)\r\n    {\r\n      /* Select the start filter number of CAN2 slave instance */\r\n      CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB);\r\n      SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos);\r\n    }\r\n\r\n#elif defined(CAN2)\r\n    /* Select the start filter number of CAN2 slave instance */\r\n    CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB);\r\n    SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos);\r\n\r\n#endif\r\n    /* Convert filter number into bit position */\r\n    filternbrbitpos = (1U) << sFilterConfig->FilterBank;\r\n\r\n    /* Filter Deactivation */\r\n    CLEAR_BIT(can_ip->FA1R, filternbrbitpos);\r\n\r\n    /* Filter Scale */\r\n    if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)\r\n    {\r\n      /* 16-bit scale for the filter */\r\n      CLEAR_BIT(can_ip->FS1R, filternbrbitpos);\r\n\r\n      /* First 16-bit identifier and First 16-bit mask */\r\n      /* Or First 16-bit identifier and Second 16-bit identifier */\r\n      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =\r\n        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |\r\n        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);\r\n\r\n      /* Second 16-bit identifier and Second 16-bit mask */\r\n      /* Or Third 16-bit identifier and Fourth 16-bit identifier */\r\n      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =\r\n        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |\r\n        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);\r\n    }\r\n\r\n    if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)\r\n    {\r\n      /* 32-bit scale for the filter */\r\n      SET_BIT(can_ip->FS1R, filternbrbitpos);\r\n\r\n      /* 32-bit identifier or First 32-bit identifier */\r\n      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =\r\n        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |\r\n        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);\r\n\r\n      /* 32-bit mask or Second 32-bit identifier */\r\n      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =\r\n        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |\r\n        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);\r\n    }\r\n\r\n    /* Filter Mode */\r\n    if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)\r\n    {\r\n      /* Id/Mask mode for the filter*/\r\n      CLEAR_BIT(can_ip->FM1R, filternbrbitpos);\r\n    }\r\n    else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */\r\n    {\r\n      /* Identifier list mode for the filter*/\r\n      SET_BIT(can_ip->FM1R, filternbrbitpos);\r\n    }\r\n\r\n    /* Filter FIFO assignment */\r\n    if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)\r\n    {\r\n      /* FIFO 0 assignation for the filter */\r\n      CLEAR_BIT(can_ip->FFA1R, filternbrbitpos);\r\n    }\r\n    else\r\n    {\r\n      /* FIFO 1 assignation for the filter */\r\n      SET_BIT(can_ip->FFA1R, filternbrbitpos);\r\n    }\r\n\r\n    /* Filter activation */\r\n    if (sFilterConfig->FilterActivation == ENABLE)\r\n    {\r\n      SET_BIT(can_ip->FA1R, filternbrbitpos);\r\n    }\r\n\r\n    /* Leave the initialisation mode for the filter */\r\n    CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT);\r\n\r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    /* Update error code */\r\n    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;\r\n\r\n    return HAL_ERROR;\r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CAN_Exported_Functions_Group3 Control functions\r\n *  @brief    Control functions\r\n *\r\n@verbatim\r\n  ==============================================================================\r\n                      ##### Control functions #####\r\n  ==============================================================================\r\n    [..]  This section provides functions allowing to:\r\n      (+) HAL_CAN_Start                    : Start the CAN module\r\n      (+) HAL_CAN_Stop                     : Stop the CAN module\r\n      (+) HAL_CAN_RequestSleep             : Request sleep mode entry.\r\n      (+) HAL_CAN_WakeUp                   : Wake up from sleep mode.\r\n      (+) HAL_CAN_IsSleepActive            : Check is sleep mode is active.\r\n      (+) HAL_CAN_AddTxMessage             : Add a message to the Tx mailboxes\r\n                                             and activate the corresponding\r\n                                             transmission request\r\n      (+) HAL_CAN_AbortTxRequest           : Abort transmission request\r\n      (+) HAL_CAN_GetTxMailboxesFreeLevel  : Return Tx mailboxes free level\r\n      (+) HAL_CAN_IsTxMessagePending       : Check if a transmission request is\r\n                                             pending on the selected Tx mailbox\r\n      (+) HAL_CAN_GetRxMessage             : Get a CAN frame from the Rx FIFO\r\n      (+) HAL_CAN_GetRxFifoFillLevel       : Return Rx FIFO fill level\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Start the CAN module.\r\n  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan)\r\n{\r\n  uint32_t tickstart = 0U;\r\n\r\n  if (hcan->State == HAL_CAN_STATE_READY)\r\n  {\r\n    /* Change CAN peripheral state */\r\n    hcan->State = HAL_CAN_STATE_LISTENING;\r\n\r\n    /* Request leave initialisation */\r\n    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);\r\n\r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n    /* Wait the acknowledge */\r\n    while ((hcan->Instance->MSR & CAN_MSR_INAK) != RESET)\r\n    {\r\n      /* Check for the Timeout */\r\n      if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)\r\n      {\r\n        /* Update error code */\r\n        hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;\r\n\r\n        /* Change CAN state */\r\n        hcan->State = HAL_CAN_STATE_ERROR;\r\n\r\n        return HAL_ERROR;\r\n      }\r\n    }\r\n\r\n    /* Reset the CAN ErrorCode */\r\n    hcan->ErrorCode = HAL_CAN_ERROR_NONE;\r\n\r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    /* Update error code */\r\n    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY;\r\n\r\n    return HAL_ERROR;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Stop the CAN module and enable access to configuration registers.\r\n  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan)\r\n{\r\n  uint32_t tickstart = 0U;\r\n\r\n  if (hcan->State == HAL_CAN_STATE_LISTENING)\r\n  {\r\n    /* Request initialisation */\r\n    SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);\r\n\r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n    /* Wait the acknowledge */\r\n    while ((hcan->Instance->MSR & CAN_MSR_INAK) == RESET)\r\n    {\r\n      /* Check for the Timeout */\r\n      if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)\r\n      {\r\n        /* Update error code */\r\n        hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;\r\n\r\n        /* Change CAN state */\r\n        hcan->State = HAL_CAN_STATE_ERROR;\r\n\r\n        return HAL_ERROR;\r\n      }\r\n    }\r\n\r\n    /* Exit from sleep mode */\r\n    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);\r\n\r\n    /* Change CAN peripheral state */\r\n    hcan->State = HAL_CAN_STATE_READY;\r\n\r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    /* Update error code */\r\n    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED;\r\n\r\n    return HAL_ERROR;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Request the sleep mode (low power) entry.\r\n  *         When returning from this function, Sleep mode will be entered\r\n  *         as soon as the current CAN activity (transmission or reception\r\n  *         of a CAN frame) has been completed.\r\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @retval HAL status.\r\n  */\r\nHAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan)\r\n{\r\n  if ((hcan->State == HAL_CAN_STATE_READY) ||\r\n      (hcan->State == HAL_CAN_STATE_LISTENING))\r\n  {\r\n    /* Request Sleep mode */\r\n    SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);\r\n\r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    /* Update error code */\r\n    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;\r\n\r\n    /* Return function status */\r\n    return HAL_ERROR;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Wake up from sleep mode.\r\n  *         When returning with HAL_OK status from this function, Sleep mode\r\n  *         is exited.\r\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @retval HAL status.\r\n  */\r\nHAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)\r\n{\r\n  __IO uint32_t count = 0;\r\n  uint32_t timeout = 1000000U;\r\n\r\n  if ((hcan->State == HAL_CAN_STATE_READY) ||\r\n      (hcan->State == HAL_CAN_STATE_LISTENING))\r\n  {\r\n    /* Wake up request */\r\n    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);\r\n\r\n    /* Wait sleep mode is exited */\r\n    do\r\n    {\r\n      /* Check if timeout is reached */\r\n      if (++count > timeout)\r\n      {\r\n        /* Update error code */\r\n        hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;\r\n\r\n        return HAL_ERROR;\r\n      }\r\n    }\r\n    while ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET);\r\n\r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    /* Update error code */\r\n    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;\r\n\r\n    return HAL_ERROR;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Check is sleep mode is active.\r\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @retval Status\r\n  *          - 0 : Sleep mode is not active.\r\n  *          - 1 : Sleep mode is active.\r\n  */\r\nuint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan)\r\n{\r\n  uint32_t status = 0U;\r\n\r\n  if ((hcan->State == HAL_CAN_STATE_READY) ||\r\n      (hcan->State == HAL_CAN_STATE_LISTENING))\r\n  {\r\n    /* Check Sleep mode */\r\n    if ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET)\r\n    {\r\n      status = 1U;\r\n    }\r\n  }\r\n\r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Add a message to the first free Tx mailbox and activate the\r\n  *         corresponding transmission request.\r\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @param  pHeader pointer to a CAN_TxHeaderTypeDef structure.\r\n  * @param  aData array containing the payload of the Tx frame.\r\n  * @param  pTxMailbox pointer to a variable where the function will return\r\n  *         the TxMailbox used to store the Tx message.\r\n  *         This parameter can be a value of @arg CAN_Tx_Mailboxes.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox)\r\n{\r\n  uint32_t transmitmailbox;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_CAN_IDTYPE(pHeader->IDE));\r\n  assert_param(IS_CAN_RTR(pHeader->RTR));\r\n  assert_param(IS_CAN_DLC(pHeader->DLC));\r\n  if (pHeader->IDE == CAN_ID_STD)\r\n  {\r\n    assert_param(IS_CAN_STDID(pHeader->StdId));\r\n  }\r\n  else\r\n  {\r\n    assert_param(IS_CAN_EXTID(pHeader->ExtId));\r\n  }\r\n  assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime));\r\n\r\n  if ((hcan->State == HAL_CAN_STATE_READY) ||\r\n      (hcan->State == HAL_CAN_STATE_LISTENING))\r\n  {\r\n    /* Check that all the Tx mailboxes are not full */\r\n    if (((hcan->Instance->TSR & CAN_TSR_TME0) != RESET) ||\r\n        ((hcan->Instance->TSR & CAN_TSR_TME1) != RESET) ||\r\n        ((hcan->Instance->TSR & CAN_TSR_TME2) != RESET))\r\n    {\r\n      /* Select an empty transmit mailbox */\r\n      transmitmailbox = (hcan->Instance->TSR & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos;\r\n\r\n      /* Store the Tx mailbox */\r\n      *pTxMailbox = 1U << transmitmailbox;\r\n\r\n      /* Set up the Id */\r\n      if (pHeader->IDE == CAN_ID_STD)\r\n      {\r\n        hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) |\r\n                                                           pHeader->RTR);\r\n      }\r\n      else\r\n      {\r\n        hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |\r\n                                                           pHeader->IDE |\r\n                                                           pHeader->RTR);\r\n      }\r\n\r\n      /* Set up the DLC */\r\n      hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC);\r\n\r\n      /* Set up the Transmit Global Time mode */\r\n      if (pHeader->TransmitGlobalTime == ENABLE)\r\n      {\r\n        SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT);\r\n      }\r\n\r\n      /* Set up the data field */\r\n      WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR,\r\n                ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) |\r\n                ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) |\r\n                ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) |\r\n                ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos));\r\n      WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR,\r\n                ((uint32_t)aData[3] << CAN_TDL0R_DATA3_Pos) |\r\n                ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) |\r\n                ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) |\r\n                ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos));\r\n\r\n      /* Request transmission */\r\n      SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);\r\n\r\n      /* Return function status */\r\n      return HAL_OK;\r\n    }\r\n    else\r\n    {\r\n      /* Update error code */\r\n      hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;\r\n\r\n      return HAL_ERROR;\r\n    }\r\n  }\r\n  else\r\n  {\r\n    /* Update error code */\r\n    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;\r\n\r\n    return HAL_ERROR;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Abort transmission requests\r\n  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @param  TxMailboxes List of the Tx Mailboxes to abort.\r\n  *         This parameter can be any combination of @arg CAN_Tx_Mailboxes.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes)\r\n{\r\n  /* Check function parameters */\r\n  assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes));\r\n\r\n  if ((hcan->State == HAL_CAN_STATE_READY) ||\r\n      (hcan->State == HAL_CAN_STATE_LISTENING))\r\n  {\r\n    /* Check Tx Mailbox 0 */\r\n    if ((TxMailboxes & CAN_TX_MAILBOX0) != RESET)\r\n    {\r\n      /* Add cancellation request for Tx Mailbox 0 */\r\n      SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0);\r\n    }\r\n\r\n    /* Check Tx Mailbox 1 */\r\n    if ((TxMailboxes & CAN_TX_MAILBOX1) != RESET)\r\n    {\r\n      /* Add cancellation request for Tx Mailbox 1 */\r\n      SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1);\r\n    }\r\n\r\n    /* Check Tx Mailbox 2 */\r\n    if ((TxMailboxes & CAN_TX_MAILBOX2) != RESET)\r\n    {\r\n      /* Add cancellation request for Tx Mailbox 2 */\r\n      SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2);\r\n    }\r\n\r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    /* Update error code */\r\n    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;\r\n\r\n    return HAL_ERROR;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Return Tx Mailboxes free level: number of free Tx Mailboxes.\r\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @retval Number of free Tx Mailboxes.\r\n  */\r\nuint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan)\r\n{\r\n  uint32_t freelevel = 0U;\r\n\r\n  if ((hcan->State == HAL_CAN_STATE_READY) ||\r\n      (hcan->State == HAL_CAN_STATE_LISTENING))\r\n  {\r\n    /* Check Tx Mailbox 0 status */\r\n    if ((hcan->Instance->TSR & CAN_TSR_TME0) != RESET)\r\n    {\r\n      freelevel++;\r\n    }\r\n\r\n    /* Check Tx Mailbox 1 status */\r\n    if ((hcan->Instance->TSR & CAN_TSR_TME1) != RESET)\r\n    {\r\n      freelevel++;\r\n    }\r\n\r\n    /* Check Tx Mailbox 2 status */\r\n    if ((hcan->Instance->TSR & CAN_TSR_TME2) != RESET)\r\n    {\r\n      freelevel++;\r\n    }\r\n  }\r\n\r\n  /* Return Tx Mailboxes free level */\r\n  return freelevel;\r\n}\r\n\r\n/**\r\n  * @brief  Check if a transmission request is pending on the selected Tx\r\n  *         Mailboxes.\r\n  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @param  TxMailboxes List of Tx Mailboxes to check.\r\n  *         This parameter can be any combination of @arg CAN_Tx_Mailboxes.\r\n  * @retval Status\r\n  *          - 0 : No pending transmission request on any selected Tx Mailboxes.\r\n  *          - 1 : Pending transmission request on at least one of the selected\r\n  *                Tx Mailbox.\r\n  */\r\nuint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes)\r\n{\r\n  uint32_t status = 0U;\r\n\r\n  /* Check function parameters */\r\n  assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes));\r\n\r\n  if ((hcan->State == HAL_CAN_STATE_READY) ||\r\n      (hcan->State == HAL_CAN_STATE_LISTENING))\r\n  {\r\n    /* Check pending transmission request on the selected Tx Mailboxes */\r\n    if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_Pos))\r\n    {\r\n      status = 1U;\r\n    }\r\n  }\r\n\r\n  /* Return status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Return timestamp of Tx message sent, if time triggered communication\r\n            mode is enabled.\r\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @param  TxMailbox Tx Mailbox where the timestamp of message sent will be\r\n  *         read.\r\n  *         This parameter can be one value of @arg CAN_Tx_Mailboxes.\r\n  * @retval Timestamp of message sent from Tx Mailbox.\r\n  */\r\nuint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox)\r\n{\r\n  uint32_t timestamp = 0U;\r\n  uint32_t transmitmailbox;\r\n\r\n  /* Check function parameters */\r\n  assert_param(IS_CAN_TX_MAILBOX(TxMailbox));\r\n\r\n  if ((hcan->State == HAL_CAN_STATE_READY) ||\r\n      (hcan->State == HAL_CAN_STATE_LISTENING))\r\n  {\r\n    /* Select the Tx mailbox */\r\n    transmitmailbox = POSITION_VAL(TxMailbox);\r\n\r\n    /* Get timestamp */\r\n    timestamp = (hcan->Instance->sTxMailBox[transmitmailbox].TDTR & CAN_TDT0R_TIME) >> CAN_TDT0R_TIME_Pos;\r\n  }\r\n\r\n  /* Return the timestamp */\r\n  return timestamp;\r\n}\r\n\r\n/**\r\n  * @brief  Get an CAN frame from the Rx FIFO zone into the message RAM.\r\n  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @param  RxFifo Fifo number of the received message to be read.\r\n  *         This parameter can be a value of @arg CAN_receive_FIFO_number.\r\n  * @param  pHeader pointer to a CAN_RxHeaderTypeDef structure where the header\r\n  *         of the Rx frame will be stored.\r\n  * @param  aData array where the payload of the Rx frame will be stored.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[])\r\n{\r\n  assert_param(IS_CAN_RX_FIFO(RxFifo));\r\n\r\n  if ((hcan->State == HAL_CAN_STATE_READY) ||\r\n      (hcan->State == HAL_CAN_STATE_LISTENING))\r\n  {\r\n    /* Check the Rx FIFO */\r\n    if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */\r\n    {\r\n      /* Check that the Rx FIFO 0 is not empty */\r\n      if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == RESET)\r\n      {\r\n        /* Update error code */\r\n        hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;\r\n\r\n        return HAL_ERROR;\r\n      }\r\n    }\r\n    else if (RxFifo == CAN_RX_FIFO1) /* Rx element is assigned to Rx FIFO 1 */\r\n    {\r\n      /* Check that the Rx FIFO 1 is not empty */\r\n      if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == RESET)\r\n      {\r\n        /* Update error code */\r\n        hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;\r\n\r\n        return HAL_ERROR;\r\n      }\r\n    }\r\n\r\n    /* Get the header */\r\n    pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR;\r\n    if (pHeader->IDE == CAN_ID_STD)\r\n    {\r\n      pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos;\r\n    }\r\n    else\r\n    {\r\n      pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos;\r\n    }\r\n    pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_RTR_Pos;\r\n    pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;\r\n    pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos;\r\n    pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos;\r\n\r\n    /* Get the data */\r\n    aData[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos;\r\n    aData[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos;\r\n    aData[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos;\r\n    aData[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos;\r\n    aData[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos;\r\n    aData[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos;\r\n    aData[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos;\r\n    aData[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos;\r\n\r\n    /* Release the FIFO */\r\n    if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */\r\n    {\r\n      /* Release RX FIFO 0 */\r\n      SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0);\r\n    }\r\n    else if (RxFifo == CAN_RX_FIFO1) /* Rx element is assigned to Rx FIFO 1 */\r\n    {\r\n      /* Release RX FIFO 1 */\r\n      SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1);\r\n    }\r\n\r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    /* Update error code */\r\n    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;\r\n\r\n    return HAL_ERROR;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Return Rx FIFO fill level.\r\n  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @param  RxFifo Rx FIFO.\r\n  *         This parameter can be a value of @arg CAN_receive_FIFO_number.\r\n  * @retval Number of messages available in Rx FIFO.\r\n  */\r\nuint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo)\r\n{\r\n  uint32_t filllevel = 0U;\r\n\r\n  /* Check function parameters */\r\n  assert_param(IS_CAN_RX_FIFO(RxFifo));\r\n\r\n  if ((hcan->State == HAL_CAN_STATE_READY) ||\r\n      (hcan->State == HAL_CAN_STATE_LISTENING))\r\n  {\r\n    if (RxFifo == CAN_RX_FIFO0)\r\n    {\r\n      filllevel = hcan->Instance->RF0R & CAN_RF0R_FMP0;\r\n    }\r\n    else /* RxFifo == CAN_RX_FIFO1 */\r\n    {\r\n      filllevel = hcan->Instance->RF1R & CAN_RF1R_FMP1;\r\n    }\r\n  }\r\n\r\n  /* Return Rx FIFO fill level */\r\n  return filllevel;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CAN_Exported_Functions_Group4 Interrupts management\r\n *  @brief    Interrupts management\r\n *\r\n@verbatim\r\n  ==============================================================================\r\n                       ##### Interrupts management #####\r\n  ==============================================================================\r\n    [..]  This section provides functions allowing to:\r\n      (+) HAL_CAN_ActivateNotification      : Enable interrupts\r\n      (+) HAL_CAN_DeactivateNotification    : Disable interrupts\r\n      (+) HAL_CAN_IRQHandler                : Handles CAN interrupt request\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Enable interrupts.\r\n  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @param  ActiveITs indicates which interrupts will be enabled.\r\n  *         This parameter can be any combination of @arg CAN_Interrupts.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs)\r\n{\r\n  /* Check function parameters */\r\n  assert_param(IS_CAN_IT(ActiveITs));\r\n\r\n  if ((hcan->State == HAL_CAN_STATE_READY) ||\r\n      (hcan->State == HAL_CAN_STATE_LISTENING))\r\n  {\r\n    /* Enable the selected interrupts */\r\n    __HAL_CAN_ENABLE_IT(hcan, ActiveITs);\r\n\r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    /* Update error code */\r\n    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;\r\n\r\n    return HAL_ERROR;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Disable interrupts.\r\n  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @param  InactiveITs indicates which interrupts will be disabled.\r\n  *         This parameter can be any combination of @arg CAN_Interrupts.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs)\r\n{\r\n  /* Check function parameters */\r\n  assert_param(IS_CAN_IT(InactiveITs));\r\n\r\n  if ((hcan->State == HAL_CAN_STATE_READY) ||\r\n      (hcan->State == HAL_CAN_STATE_LISTENING))\r\n  {\r\n    /* Disable the selected interrupts */\r\n    __HAL_CAN_DISABLE_IT(hcan, InactiveITs);\r\n\r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    /* Update error code */\r\n    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;\r\n\r\n    return HAL_ERROR;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Handles CAN interrupt request\r\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @retval None\r\n  */\r\nvoid HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)\r\n{\r\n  uint32_t errorcode = HAL_CAN_ERROR_NONE;\r\n  uint32_t interrupts = READ_REG(hcan->Instance->IER);\r\n  uint32_t msrflags = READ_REG(hcan->Instance->MSR);\r\n  uint32_t tsrflags = READ_REG(hcan->Instance->TSR);\r\n  uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R);\r\n  uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R);\r\n  uint32_t esrflags = READ_REG(hcan->Instance->ESR);\r\n\r\n  /* Transmit Mailbox empty interrupt management *****************************/\r\n  if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != RESET)\r\n  {\r\n    /* Transmit Mailbox 0 management *****************************************/\r\n    if ((tsrflags & CAN_TSR_RQCP0) != RESET)\r\n    {\r\n      /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */\r\n      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0);\r\n\r\n      if ((tsrflags & CAN_TSR_TXOK0) != RESET)\r\n      {\r\n        /* Transmission Mailbox 0 complete callback */\r\n        /* Call weak (surcharged) callback */\r\n        HAL_CAN_TxMailbox0CompleteCallback(hcan);\r\n      }\r\n      else\r\n      {\r\n        if ((tsrflags & CAN_TSR_ALST0) != RESET)\r\n        {\r\n          /* Update error code */\r\n          errorcode |= HAL_CAN_ERROR_TX_ALST0;\r\n        }\r\n        else if ((tsrflags & CAN_TSR_TERR0) != RESET)\r\n        {\r\n          /* Update error code */\r\n          errorcode |= HAL_CAN_ERROR_TX_TERR0;\r\n        }\r\n        else\r\n        {\r\n          /* Transmission Mailbox 0 abort callback */\r\n          /* Call weak (surcharged) callback */\r\n          HAL_CAN_TxMailbox0AbortCallback(hcan);\r\n        }\r\n      }\r\n    }\r\n\r\n    /* Transmit Mailbox 1 management *****************************************/\r\n    if ((tsrflags & CAN_TSR_RQCP1) != RESET)\r\n    {\r\n      /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */\r\n      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1);\r\n\r\n      if ((tsrflags & CAN_TSR_TXOK1) != RESET)\r\n      {\r\n        /* Transmission Mailbox 1 complete callback */\r\n        /* Call weak (surcharged) callback */\r\n        HAL_CAN_TxMailbox1CompleteCallback(hcan);\r\n      }\r\n      else\r\n      {\r\n        if ((tsrflags & CAN_TSR_ALST1) != RESET)\r\n        {\r\n          /* Update error code */\r\n          errorcode |= HAL_CAN_ERROR_TX_ALST1;\r\n        }\r\n        else if ((tsrflags & CAN_TSR_TERR1) != RESET)\r\n        {\r\n          /* Update error code */\r\n          errorcode |= HAL_CAN_ERROR_TX_TERR1;\r\n        }\r\n        else\r\n        {\r\n          /* Transmission Mailbox 1 abort callback */\r\n          /* Call weak (surcharged) callback */\r\n          HAL_CAN_TxMailbox1AbortCallback(hcan);\r\n        }\r\n      }\r\n    }\r\n\r\n    /* Transmit Mailbox 2 management *****************************************/\r\n    if ((tsrflags & CAN_TSR_RQCP2) != RESET)\r\n    {\r\n      /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */\r\n      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2);\r\n\r\n      if ((tsrflags & CAN_TSR_TXOK2) != RESET)\r\n      {\r\n        /* Transmission Mailbox 2 complete callback */\r\n        /* Call weak (surcharged) callback */\r\n        HAL_CAN_TxMailbox2CompleteCallback(hcan);\r\n      }\r\n      else\r\n      {\r\n        if ((tsrflags & CAN_TSR_ALST2) != RESET)\r\n        {\r\n          /* Update error code */\r\n          errorcode |= HAL_CAN_ERROR_TX_ALST2;\r\n        }\r\n        else if ((tsrflags & CAN_TSR_TERR2) != RESET)\r\n        {\r\n          /* Update error code */\r\n          errorcode |= HAL_CAN_ERROR_TX_TERR2;\r\n        }\r\n        else\r\n        {\r\n          /* Transmission Mailbox 2 abort callback */\r\n          /* Call weak (surcharged) callback */\r\n          HAL_CAN_TxMailbox2AbortCallback(hcan);\r\n        }\r\n      }\r\n    }\r\n  }\r\n\r\n  /* Receive FIFO 0 overrun interrupt management *****************************/\r\n  if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != RESET)\r\n  {\r\n    if ((rf0rflags & CAN_RF0R_FOVR0) != RESET)\r\n    {\r\n      /* Set CAN error code to Rx Fifo 0 overrun error */\r\n      errorcode |= HAL_CAN_ERROR_RX_FOV0;\r\n\r\n      /* Clear FIFO0 Overrun Flag */\r\n      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);\r\n    }\r\n  }\r\n\r\n  /* Receive FIFO 0 full interrupt management ********************************/\r\n  if ((interrupts & CAN_IT_RX_FIFO0_FULL) != RESET)\r\n  {\r\n    if ((rf0rflags & CAN_RF0R_FULL0) != RESET)\r\n    {\r\n      /* Clear FIFO 0 full Flag */\r\n      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0);\r\n\r\n      /* Receive FIFO 0 full Callback */\r\n      /* Call weak (surcharged) callback */\r\n      HAL_CAN_RxFifo0FullCallback(hcan);\r\n    }\r\n  }\r\n\r\n  /* Receive FIFO 0 message pending interrupt management *********************/\r\n  if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != RESET)\r\n  {\r\n    /* Check if message is still pending */\r\n    if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != RESET)\r\n    {\r\n      /* Receive FIFO 0 mesage pending Callback */\r\n      /* Call weak (surcharged) callback */\r\n      HAL_CAN_RxFifo0MsgPendingCallback(hcan);\r\n    }\r\n  }\r\n\r\n  /* Receive FIFO 1 overrun interrupt management *****************************/\r\n  if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != RESET)\r\n  {\r\n    if ((rf1rflags & CAN_RF1R_FOVR1) != RESET)\r\n    {\r\n      /* Set CAN error code to Rx Fifo 1 overrun error */\r\n      errorcode |= HAL_CAN_ERROR_RX_FOV1;\r\n\r\n      /* Clear FIFO1 Overrun Flag */\r\n      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);\r\n    }\r\n  }\r\n\r\n  /* Receive FIFO 1 full interrupt management ********************************/\r\n  if ((interrupts & CAN_IT_RX_FIFO1_FULL) != RESET)\r\n  {\r\n    if ((rf1rflags & CAN_RF1R_FULL1) != RESET)\r\n    {\r\n      /* Clear FIFO 1 full Flag */\r\n      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1);\r\n\r\n      /* Receive FIFO 1 full Callback */\r\n      /* Call weak (surcharged) callback */\r\n      HAL_CAN_RxFifo1FullCallback(hcan);\r\n    }\r\n  }\r\n\r\n  /* Receive FIFO 1 message pending interrupt management *********************/\r\n  if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != RESET)\r\n  {\r\n    /* Check if message is still pending */\r\n    if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != RESET)\r\n    {\r\n      /* Receive FIFO 1 mesage pending Callback */\r\n      /* Call weak (surcharged) callback */\r\n      HAL_CAN_RxFifo1MsgPendingCallback(hcan);\r\n    }\r\n  }\r\n\r\n  /* Sleep interrupt management *********************************************/\r\n  if ((interrupts & CAN_IT_SLEEP_ACK) != RESET)\r\n  {\r\n    if ((msrflags & CAN_MSR_SLAKI) != RESET)\r\n    {\r\n      /* Clear Sleep interrupt Flag */\r\n      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI);\r\n\r\n      /* Sleep Callback */\r\n      /* Call weak (surcharged) callback */\r\n      HAL_CAN_SleepCallback(hcan);\r\n    }\r\n  }\r\n\r\n  /* WakeUp interrupt management *********************************************/\r\n  if ((interrupts & CAN_IT_WAKEUP) != RESET)\r\n  {\r\n    if ((msrflags & CAN_MSR_WKUI) != RESET)\r\n    {\r\n      /* Clear WakeUp Flag */\r\n      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU);\r\n\r\n      /* WakeUp Callback */\r\n      /* Call weak (surcharged) callback */\r\n      HAL_CAN_WakeUpFromRxMsgCallback(hcan);\r\n    }\r\n  }\r\n\r\n  /* Error interrupts management *********************************************/\r\n  if ((interrupts & CAN_IT_ERROR) != RESET)\r\n  {\r\n    if ((msrflags & CAN_MSR_ERRI) != RESET)\r\n    {\r\n      /* Check Error Warning Flag */\r\n      if (((interrupts & CAN_IT_ERROR_WARNING) != RESET) &&\r\n          ((esrflags & CAN_ESR_EWGF) != RESET))\r\n      {\r\n        /* Set CAN error code to Error Warning */\r\n        errorcode |= HAL_CAN_ERROR_EWG;\r\n\r\n        /* No need for clear of Error Warning Flag as read-only */\r\n      }\r\n\r\n      /* Check Error Passive Flag */\r\n      if (((interrupts & CAN_IT_ERROR_PASSIVE) != RESET) &&\r\n          ((esrflags & CAN_ESR_EPVF) != RESET))\r\n      {\r\n        /* Set CAN error code to Error Passive */\r\n        errorcode |= HAL_CAN_ERROR_EPV;\r\n\r\n        /* No need for clear of Error Passive Flag as read-only */\r\n      }\r\n\r\n      /* Check Bus-off Flag */\r\n      if (((interrupts & CAN_IT_BUSOFF) != RESET) &&\r\n          ((esrflags & CAN_ESR_BOFF) != RESET))\r\n      {\r\n        /* Set CAN error code to Bus-Off */\r\n        errorcode |= HAL_CAN_ERROR_BOF;\r\n\r\n        /* No need for clear of Error Bus-Off as read-only */\r\n      }\r\n\r\n      /* Check Last Error Code Flag */\r\n      if (((interrupts & CAN_IT_LAST_ERROR_CODE) != RESET) &&\r\n          ((esrflags & CAN_ESR_LEC) != RESET))\r\n      {\r\n        switch (esrflags & CAN_ESR_LEC)\r\n        {\r\n          case (CAN_ESR_LEC_0):\r\n            /* Set CAN error code to Stuff error */\r\n            errorcode |= HAL_CAN_ERROR_STF;\r\n            break;\r\n          case (CAN_ESR_LEC_1):\r\n            /* Set CAN error code to Form error */\r\n            errorcode |= HAL_CAN_ERROR_FOR;\r\n            break;\r\n          case (CAN_ESR_LEC_1 | CAN_ESR_LEC_0):\r\n            /* Set CAN error code to Acknowledgement error */\r\n            errorcode |= HAL_CAN_ERROR_ACK;\r\n            break;\r\n          case (CAN_ESR_LEC_2):\r\n            /* Set CAN error code to Bit recessive error */\r\n            errorcode |= HAL_CAN_ERROR_BR;\r\n            break;\r\n          case (CAN_ESR_LEC_2 | CAN_ESR_LEC_0):\r\n            /* Set CAN error code to Bit Dominant error */\r\n            errorcode |= HAL_CAN_ERROR_BD;\r\n            break;\r\n          case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1):\r\n            /* Set CAN error code to CRC error */\r\n            errorcode |= HAL_CAN_ERROR_CRC;\r\n            break;\r\n          default:\r\n            break;\r\n        }\r\n\r\n        /* Clear Last error code Flag */\r\n        CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);\r\n      }\r\n    }\r\n\r\n    /* Clear ERRI Flag */\r\n    __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI);\r\n  }\r\n\r\n  /* Call the Error call Back in case of Errors */\r\n  if (errorcode != HAL_CAN_ERROR_NONE)\r\n  {\r\n    /* Update error code in handle */\r\n    hcan->ErrorCode |= errorcode;\r\n\r\n    /* Call Error callback function */\r\n    /* Call weak (surcharged) callback */\r\n    HAL_CAN_ErrorCallback(hcan);\r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CAN_Exported_Functions_Group5 Callback functions\r\n *  @brief   CAN Callback functions\r\n *\r\n@verbatim\r\n  ==============================================================================\r\n                          ##### Callback functions #####\r\n  ==============================================================================\r\n    [..]\r\n    This subsection provides the following callback functions:\r\n      (+) HAL_CAN_TxMailbox0CompleteCallback\r\n      (+) HAL_CAN_TxMailbox1CompleteCallback\r\n      (+) HAL_CAN_TxMailbox2CompleteCallback\r\n      (+) HAL_CAN_TxMailbox0AbortCallback\r\n      (+) HAL_CAN_TxMailbox1AbortCallback\r\n      (+) HAL_CAN_TxMailbox2AbortCallback\r\n      (+) HAL_CAN_RxFifo0MsgPendingCallback\r\n      (+) HAL_CAN_RxFifo0FullCallback\r\n      (+) HAL_CAN_RxFifo1MsgPendingCallback\r\n      (+) HAL_CAN_RxFifo1FullCallback\r\n      (+) HAL_CAN_SleepCallback\r\n      (+) HAL_CAN_WakeUpFromRxMsgCallback\r\n      (+) HAL_CAN_ErrorCallback\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Transmission Mailbox 0 complete callback.\r\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @retval None\r\n  */\r\n__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcan);\r\n\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the\r\n            user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Transmission Mailbox 1 complete callback.\r\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @retval None\r\n  */\r\n__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcan);\r\n\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the\r\n            user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Transmission Mailbox 2 complete callback.\r\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @retval None\r\n  */\r\n__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcan);\r\n\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the\r\n            user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Transmission Mailbox 0 Cancellation callback.\r\n  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @retval None\r\n  */\r\n__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcan);\r\n\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_CAN_TxMailbox0AbortCallback could be implemented in the\r\n            user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Transmission Mailbox 1 Cancellation callback.\r\n  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @retval None\r\n  */\r\n__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcan);\r\n\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_CAN_TxMailbox1AbortCallback could be implemented in the\r\n            user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Transmission Mailbox 2 Cancellation callback.\r\n  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @retval None\r\n  */\r\n__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcan);\r\n\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_CAN_TxMailbox2AbortCallback could be implemented in the\r\n            user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Rx FIFO 0 message pending callback.\r\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @retval None\r\n  */\r\n__weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcan);\r\n\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the\r\n            user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Rx FIFO 0 full callback.\r\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @retval None\r\n  */\r\n__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcan);\r\n\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_CAN_RxFifo0FullCallback could be implemented in the user\r\n            file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Rx FIFO 1 message pending callback.\r\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @retval None\r\n  */\r\n__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcan);\r\n\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the\r\n            user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Rx FIFO 1 full callback.\r\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @retval None\r\n  */\r\n__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcan);\r\n\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_CAN_RxFifo1FullCallback could be implemented in the user\r\n            file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Sleep callback.\r\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @retval None\r\n  */\r\n__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcan);\r\n\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_CAN_SleepCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  WakeUp from Rx message callback.\r\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @retval None\r\n  */\r\n__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcan);\r\n\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the\r\n            user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Error CAN callback.\r\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @retval None\r\n  */\r\n__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcan);\r\n\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_CAN_ErrorCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions\r\n *  @brief   CAN Peripheral State functions\r\n *\r\n@verbatim\r\n  ==============================================================================\r\n            ##### Peripheral State and Error functions #####\r\n  ==============================================================================\r\n    [..]\r\n    This subsection provides functions allowing to :\r\n      (+) HAL_CAN_GetState()  : Return the CAN state.\r\n      (+) HAL_CAN_GetError()  : Return the CAN error codes if any.\r\n      (+) HAL_CAN_ResetError(): Reset the CAN error codes if any.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Return the CAN state.\r\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @retval HAL state\r\n  */\r\nHAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan)\r\n{\r\n  HAL_CAN_StateTypeDef state = hcan->State;\r\n\r\n  if ((hcan->State == HAL_CAN_STATE_READY) ||\r\n      (hcan->State == HAL_CAN_STATE_LISTENING))\r\n  {\r\n    /* Check sleep mode acknowledge flag */\r\n    if ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET)\r\n    {\r\n      /* Sleep mode is active */\r\n      state = HAL_CAN_STATE_SLEEP_ACTIVE;\r\n    }\r\n    /* Check sleep mode request flag */\r\n    else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != RESET)\r\n    {\r\n      /* Sleep mode request is pending */\r\n      state = HAL_CAN_STATE_SLEEP_PENDING;\r\n    }\r\n  }\r\n\r\n  /* Return CAN state */\r\n  return state;\r\n}\r\n\r\n/**\r\n  * @brief  Return the CAN error code.\r\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @retval CAN Error Code\r\n  */\r\nuint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)\r\n{\r\n  /* Return CAN error code */\r\n  return hcan->ErrorCode;\r\n}\r\n\r\n/**\r\n  * @brief  Reset the CAN error code.\r\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  if ((hcan->State == HAL_CAN_STATE_READY) ||\r\n      (hcan->State == HAL_CAN_STATE_LISTENING))\r\n  {\r\n    /* Reset CAN error code */\r\n    hcan->ErrorCode = 0U;\r\n  }\r\n  else\r\n  {\r\n    /* Update error code */\r\n    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;\r\n\r\n    status = HAL_ERROR;\r\n  }\r\n\r\n  /* Return the status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_CAN_MODULE_ENABLED */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* CAN1 */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cec.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_cec.c\r\n  * @author  MCD Application Team\r\n  * @brief   CEC HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the High Definition Multimedia Interface \r\n  *          Consumer Electronics Control Peripheral (CEC).\r\n  *           + Initialization and de-initialization function\r\n  *           + IO operation function\r\n  *           + Peripheral Control function\r\n  *\r\n  *           \r\n  @verbatim       \r\n ===============================================================================\r\n                        ##### How to use this driver #####\r\n ===============================================================================\r\n    [..]\r\n    The CEC HAL driver can be used as follow:\r\n    \r\n    (#) Declare a CEC_HandleTypeDef handle structure.\r\n    (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:\r\n        (##) Enable the CEC interface clock.\r\n        (##) CEC pins configuration:\r\n            (+++) Enable the clock for the CEC GPIOs.\r\n            (+++) Configure these CEC pins as alternate function pull-up.\r\n        (##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()\r\n             and HAL_CEC_Receive_IT() APIs):\r\n            (+++) Configure the CEC interrupt priority.\r\n            (+++) Enable the NVIC CEC IRQ handle.\r\n            (+++) The specific CEC interrupts (Transmission complete interrupt, \r\n                  RXNE interrupt and Error Interrupts) will be managed using the macros\r\n                  __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit \r\n                  and receive process.\r\n\r\n    (#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in\r\n        in case of Bit Rising Error, Error-Bit generation conditions, device logical\r\n        address and Listen mode in the hcec Init structure.\r\n\r\n    (#) Initialize the CEC registers by calling the HAL_CEC_Init() API.\r\n\r\n  [..]        \r\n    (@) This API (HAL_CEC_Init()) configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)\r\n        by calling the customed HAL_CEC_MspInit() API.\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************  \r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CEC CEC \r\n  * @brief HAL CEC module driver\r\n  * @{\r\n  */\r\n#ifdef HAL_CEC_MODULE_ENABLED\r\n#if defined (CEC)\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @defgroup CEC_Private_Constants CEC Private Constants\r\n  * @{\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n \r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/** @defgroup CEC_Private_Functions CEC Private Functions\r\n  * @{\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Exported functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup CEC_Exported_Functions CEC Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions\r\n  *  @brief    Initialization and Configuration functions \r\n  *\r\n@verbatim                                                \r\n===============================================================================\r\n            ##### Initialization and Configuration functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides a set of functions allowing to initialize the CEC\r\n      (+) The following parameters need to be configured: \r\n        (++) SignalFreeTime\r\n        (++) Tolerance \r\n        (++) BRERxStop                 (RX stopped or not upon Bit Rising Error)\r\n        (++) BREErrorBitGen            (Error-Bit generation in case of Bit Rising Error)\r\n        (++) LBPEErrorBitGen           (Error-Bit generation in case of Long Bit Period Error)\r\n        (++) BroadcastMsgNoErrorBitGen (Error-bit generation in case of broadcast message error)\r\n        (++) SignalFreeTimeOption      (SFT Timer start definition)\r\n        (++) OwnAddress                (CEC device address)\r\n        (++) ListenMode\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief Initializes the CEC mode according to the specified\r\n  *         parameters in the CEC_InitTypeDef and creates the associated handle .\r\n  * @param hcec CEC handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)\r\n{  \r\n  /* Check the CEC handle allocation */\r\n  if((hcec == NULL) ||(hcec->Init.RxBuffer == NULL))\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */ \r\n  assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));\r\n  assert_param(IS_CEC_SIGNALFREETIME(hcec->Init.SignalFreeTime));\r\n  assert_param(IS_CEC_TOLERANCE(hcec->Init.Tolerance));  \r\n  assert_param(IS_CEC_BRERXSTOP(hcec->Init.BRERxStop));\r\n  assert_param(IS_CEC_BREERRORBITGEN(hcec->Init.BREErrorBitGen));\r\n  assert_param(IS_CEC_LBPEERRORBITGEN(hcec->Init.LBPEErrorBitGen));\r\n  assert_param(IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(hcec->Init.BroadcastMsgNoErrorBitGen));\r\n  assert_param(IS_CEC_SFTOP(hcec->Init.SignalFreeTimeOption)); \r\n  assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode));\r\n  assert_param(IS_CEC_OWN_ADDRESS(hcec->Init.OwnAddress));  \r\n\r\n  if(hcec->gState == HAL_CEC_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    hcec->Lock = HAL_UNLOCKED;   \r\n    /* Init the low level hardware : GPIO, CLOCK */\r\n    HAL_CEC_MspInit(hcec);\r\n  }\r\n  hcec->gState = HAL_CEC_STATE_BUSY;\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_CEC_DISABLE(hcec);\r\n  \r\n  /* Write to CEC Control Register */\r\n  hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop|\\\r\n                         hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | hcec->Init.BroadcastMsgNoErrorBitGen |\\\r\n\t\t\t hcec->Init.SignalFreeTimeOption |((uint32_t)(hcec->Init.OwnAddress)<<16U) |\\\r\n                         hcec->Init.ListenMode;\r\n  \r\n  /* Enable the following CEC Transmission/Reception interrupts as\r\n   * well as the following CEC Transmission/Reception Errors interrupts \r\n   * Rx Byte Received IT \r\n   * End of Reception IT \r\n   * Rx overrun\r\n   * Rx bit rising error\r\n   * Rx short bit period error\r\n   * Rx long bit period error\r\n   * Rx missing acknowledge\r\n   * Tx Byte Request IT \r\n   * End of Transmission IT\r\n   * Tx Missing Acknowledge IT\r\n   * Tx-Error IT\r\n   * Tx-Buffer Underrun IT \r\n   * Tx arbitration lost   */\r\n __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);\r\n    \r\n  /* Enable the CEC Peripheral */\r\n  __HAL_CEC_ENABLE(hcec);\r\n  \r\n  hcec->ErrorCode = HAL_CEC_ERROR_NONE;\r\n  hcec->gState = HAL_CEC_STATE_READY;\r\n  hcec->RxState = HAL_CEC_STATE_READY;\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief DeInitializes the CEC peripheral \r\n  * @param hcec CEC handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)\r\n{\r\n  /* Check the CEC handle allocation */\r\n  if(hcec == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));\r\n\r\n  hcec->gState = HAL_CEC_STATE_BUSY;\r\n  \r\n  /* DeInit the low level hardware */\r\n  HAL_CEC_MspDeInit(hcec);\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_CEC_DISABLE(hcec);\r\n  \r\n  /* Clear Flags */\r\n  __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXEND|CEC_FLAG_TXBR|CEC_FLAG_RXBR|CEC_FLAG_RXEND|CEC_ISR_ALL_ERROR);\r\n  \r\n  /* Disable the following CEC Transmission/Reception interrupts as\r\n   * well as the following CEC Transmission/Reception Errors interrupts \r\n   * Rx Byte Received IT \r\n   * End of Reception IT \r\n   * Rx overrun\r\n   * Rx bit rising error\r\n   * Rx short bit period error\r\n   * Rx long bit period error\r\n   * Rx missing acknowledge\r\n   * Tx Byte Request IT \r\n   * End of Transmission IT\r\n   * Tx Missing Acknowledge IT\r\n   * Tx-Error IT\r\n   * Tx-Buffer Underrun IT \r\n   * Tx arbitration lost   */\r\n  __HAL_CEC_DISABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);\r\n  \r\n  hcec->ErrorCode = HAL_CEC_ERROR_NONE;\r\n  hcec->gState = HAL_CEC_STATE_RESET;\r\n  hcec->RxState = HAL_CEC_STATE_RESET;\r\n  \r\n  /* Process Unlock */\r\n  __HAL_UNLOCK(hcec);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Initializes the Own Address of the CEC device\r\n  * @param hcec CEC handle\r\n  * @param  CEC_OwnAddress The CEC own address.  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_CEC_OWN_ADDRESS(CEC_OwnAddress));\r\n\r\n  if ((hcec->gState == HAL_CEC_STATE_READY) && (hcec->RxState == HAL_CEC_STATE_READY))\r\n  { \r\n    /* Process Locked */\r\n    __HAL_LOCK(hcec); \r\n    \r\n    hcec->gState = HAL_CEC_STATE_BUSY;\r\n  \r\n    /* Disable the Peripheral */\r\n    __HAL_CEC_DISABLE(hcec);\r\n    \r\n    if(CEC_OwnAddress != CEC_OWN_ADDRESS_NONE)\r\n    {\r\n      hcec->Instance->CFGR |= ((uint32_t)CEC_OwnAddress<<16);\r\n    }\r\n    else\r\n    {\r\n      hcec->Instance->CFGR &= ~(CEC_CFGR_OAR);\r\n    }\r\n        \r\n    hcec->gState = HAL_CEC_STATE_READY;\r\n    hcec->ErrorCode = HAL_CEC_ERROR_NONE;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hcec); \r\n    \r\n    /* Enable the Peripheral */\r\n    __HAL_CEC_ENABLE(hcec);\r\n    \r\n    return  HAL_OK; \r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief CEC MSP Init\r\n  * @param hcec CEC handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcec);\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_CEC_MspInit can be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief CEC MSP DeInit\r\n  * @param hcec CEC handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcec);\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_CEC_MspDeInit can be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CEC_Exported_Functions_Group2 Input and Output operation functions \r\n  *  @brief CEC Transmit/Receive functions \r\n  *\r\n@verbatim     \r\n ===============================================================================\r\n                      ##### IO operation functions ##### \r\n ===============================================================================  \r\n    This subsection provides a set of functions allowing to manage the CEC data transfers.\r\n    \r\n    (#) The CEC handle must contain the initiator (TX side) and the destination (RX side)\r\n        logical addresses (4-bit long addresses, 0xF for broadcast messages destination)\r\n    \r\n    (#) The communication is performed using Interrupts. \r\n           These API's return the HAL status.\r\n           The end of the data processing will be indicated through the \r\n           dedicated CEC IRQ when using Interrupt mode.\r\n           The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks \r\n           will be executed respectively at the end of the transmit or Receive process\r\n           The HAL_CEC_ErrorCallback() user callback will be executed when a communication \r\n           error is detected\r\n        \r\n    (#) API's with Interrupt are :\r\n         (+) HAL_CEC_Transmit_IT()\r\n         (+) HAL_CEC_IRQHandler()\r\n\r\n    (#) A set of User Callbacks are provided:\r\n         (+) HAL_CEC_TxCpltCallback()\r\n         (+) HAL_CEC_RxCpltCallback()\r\n         (+) HAL_CEC_ErrorCallback()\r\n      \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief Send data in interrupt mode \r\n  * @param hcec CEC handle \r\n  * @param InitiatorAddress Initiator address\r\n  * @param DestinationAddress destination logical address      \r\n  * @param pData pointer to input byte data buffer\r\n  * @param Size amount of data to be sent in bytes (without counting the header).\r\n  *              0 means only the header is sent (ping operation).\r\n  *              Maximum TX size is 15 bytes (1 opcode and up to 14 operands).    \r\n  * @retval HAL status\r\n  */  \r\nHAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)\r\n{\r\n  /* if the IP isn't already busy and if there is no previous transmission\r\n     already pending due to arbitration lost */\r\n  if (hcec->gState == HAL_CEC_STATE_READY) \r\n  {    \r\n    if((pData == NULL ) && (Size > 0)) \r\n    {\r\n      return  HAL_ERROR;                                    \r\n    }\r\n\r\n    assert_param(IS_CEC_ADDRESS(DestinationAddress)); \r\n    assert_param(IS_CEC_ADDRESS(InitiatorAddress)); \r\n    assert_param(IS_CEC_MSGSIZE(Size));\r\n    \r\n    /* Process Locked */\r\n    __HAL_LOCK(hcec);\r\n    hcec->pTxBuffPtr = pData;\r\n    hcec->gState = HAL_CEC_STATE_BUSY_TX;\r\n    hcec->ErrorCode = HAL_CEC_ERROR_NONE;\r\n  \r\n    /* initialize the number of bytes to send,\r\n     * 0 means only one header is sent (ping operation) */\r\n    hcec->TxXferCount = Size;\r\n    \r\n    /* in case of no payload (Size = 0), sender is only pinging the system;\r\n       Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */\r\n    if (Size == 0)\r\n    {\r\n      __HAL_CEC_LAST_BYTE_TX_SET(hcec);\r\n    }\r\n    /* send header block */\r\n    hcec->Instance->TXDR = ((uint8_t)(InitiatorAddress << CEC_INITIATOR_LSB_POS) |(uint8_t) DestinationAddress);\r\n    /* Set TX Start of Message  (TXSOM) bit */\r\n    __HAL_CEC_FIRST_BYTE_TX_SET(hcec);\r\n\t    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hcec); \r\n  \r\n    return HAL_OK;\r\n\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Get size of the received frame.\r\n  * @param hcec CEC handle\r\n  * @retval Frame size\r\n  */\r\nuint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec)\r\n{\r\n  return hcec->RxXferSize;\r\n}\r\n\r\n/**\r\n  * @brief Change Rx Buffer.\r\n  * @param hcec CEC handle\r\n  * @param Rxbuffer Rx Buffer\r\n  * @note  This function can be called only inside the HAL_CEC_RxCpltCallback() \r\n  * @retval Frame size\r\n  */\r\nvoid HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer)\r\n{\r\n  hcec->Init.RxBuffer = Rxbuffer; \r\n}\r\n  \r\n/**\r\n  * @brief This function handles CEC interrupt requests.\r\n  * @param hcec CEC handle\r\n  * @retval None\r\n  */\r\nvoid HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)\r\n{\r\n  \r\n  /* save interrupts register for further error or interrupts handling purposes */\r\n  uint32_t reg = 0;\r\n  reg = hcec->Instance->ISR;\r\n\r\n  \r\n  /* ----------------------------Arbitration Lost Management----------------------------------*/     \r\n  /* CEC TX arbitration error interrupt occurred --------------------------------------*/\r\n  if((reg & CEC_FLAG_ARBLST) != RESET) \r\n  { \r\n    hcec->ErrorCode = HAL_CEC_ERROR_ARBLST;\r\n    __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST);\r\n  }\r\n  \r\n  /* ----------------------------Rx Management----------------------------------*/ \r\n  /* CEC RX byte received interrupt  ---------------------------------------------------*/\r\n  if((reg & CEC_FLAG_RXBR) != RESET) \r\n  { \r\n    /* reception is starting */ \r\n    hcec->RxState = HAL_CEC_STATE_BUSY_RX;\r\n    hcec->RxXferSize++;\r\n    /* read received byte */\r\n    *hcec->Init.RxBuffer++ = hcec->Instance->RXDR;\r\n    __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR);  \r\n  }\r\n  \r\n  /* CEC RX end received interrupt  ---------------------------------------------------*/\r\n  if((reg & CEC_FLAG_RXEND) != RESET) \r\n  { \r\n    /* clear IT */\r\n    __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND);\r\n    \r\n    /* Rx process is completed, restore hcec->RxState to Ready */\r\n    hcec->RxState = HAL_CEC_STATE_READY; \r\n    hcec->ErrorCode = HAL_CEC_ERROR_NONE;\r\n    hcec->Init.RxBuffer-=hcec->RxXferSize;\r\n    HAL_CEC_RxCpltCallback(hcec, hcec->RxXferSize); \r\n    hcec->RxXferSize = 0; \r\n  }\r\n  \r\n  /* ----------------------------Tx Management----------------------------------*/  \r\n  /* CEC TX byte request interrupt ------------------------------------------------*/\r\n  if((reg & CEC_FLAG_TXBR) != RESET) \r\n  {\r\n    if (hcec->TxXferCount == 0)\r\n    {\r\n      /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */\r\n      __HAL_CEC_LAST_BYTE_TX_SET(hcec);\r\n      hcec->Instance->TXDR = *hcec->pTxBuffPtr++;\r\n    }\r\n    else\r\n    {\t\r\n      hcec->Instance->TXDR = *hcec->pTxBuffPtr++;\r\n      hcec->TxXferCount--;\r\n    }  \r\n    /* clear Tx-Byte request flag */\r\n    __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR); \r\n  } \r\n  \r\n  /* CEC TX end interrupt ------------------------------------------------*/\r\n  if((reg & CEC_FLAG_TXEND) != RESET) \r\n  {\t\r\n    __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND);\r\n    \r\n    /* Tx process is ended, restore hcec->gState to Ready */     \r\n    hcec->gState = HAL_CEC_STATE_READY;\r\n    /* Call the Process Unlocked before calling the Tx call back API to give the possibility to\r\n    start again the Transmission under the Tx call back API */\r\n    __HAL_UNLOCK(hcec);\r\n    hcec->ErrorCode = HAL_CEC_ERROR_NONE;\r\n    HAL_CEC_TxCpltCallback(hcec);\r\n  } \r\n  \r\n  /* ----------------------------Rx/Tx Error Management----------------------------------*/   \r\n  if ((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != 0)\r\n  {\r\n    hcec->ErrorCode = reg;\r\n    __HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR|HAL_CEC_ERROR_BRE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|HAL_CEC_ERROR_RXACKE|HAL_CEC_ERROR_TXUDR|HAL_CEC_ERROR_TXERR|HAL_CEC_ERROR_TXACKE);\r\n\r\n    \r\n    if((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE)) != RESET)\r\n    {\r\n      hcec->Init.RxBuffer-=hcec->RxXferSize;\t\r\n      hcec->RxXferSize = 0; \r\n      hcec->RxState = HAL_CEC_STATE_READY;\r\n    }\r\n    else if (((reg & (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != RESET) && ((reg & CEC_ISR_ARBLST) == RESET))\r\n    {\t\r\n      /* Set the CEC state ready to be able to start again the process */\r\n      hcec->gState = HAL_CEC_STATE_READY;\r\n    }\t\r\n    \r\n    /* Error  Call Back */    \r\n    HAL_CEC_ErrorCallback(hcec);\r\n  }\r\n  \r\n}\r\n\r\n/**\r\n  * @brief Tx Transfer completed callback\r\n  * @param hcec CEC handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcec);  \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_CEC_TxCpltCallback can be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief Rx Transfer completed callback\r\n  * @param hcec CEC handle\r\n  * @param RxFrameSize Size of frame\r\n  * @retval None\r\n  */\r\n__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcec);\r\n  UNUSED(RxFrameSize);\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_CEC_RxCpltCallback can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief CEC error callbacks\r\n  * @param hcec CEC handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcec);\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_CEC_ErrorCallback can be implemented in the user file\r\n   */ \r\n}\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control function \r\n  *  @brief   CEC control functions \r\n  *\r\n@verbatim   \r\n ===============================================================================\r\n                      ##### Peripheral Control function #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides a set of functions allowing to control the CEC.\r\n     (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral. \r\n\t (+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral. \r\n@endverbatim\r\n  * @{\r\n  */\r\n/**\r\n  * @brief return the CEC state\r\n  * @param hcec pointer to a CEC_HandleTypeDef structure that contains\r\n  *              the configuration information for the specified CEC module.\r\n  * @retval HAL state\r\n  */\r\nHAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)\r\n{\r\n  uint32_t temp1= 0x00U, temp2 = 0x00U;\r\n  temp1 = hcec->gState;\r\n  temp2 = hcec->RxState;\r\n  \r\n  return (HAL_CEC_StateTypeDef)(temp1 | temp2);\r\n}\r\n\r\n/**\r\n* @brief  Return the CEC error code\r\n* @param  hcec  pointer to a CEC_HandleTypeDef structure that contains\r\n  *              the configuration information for the specified CEC.\r\n* @retval CEC Error Code\r\n*/\r\nuint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)\r\n{\r\n  return hcec->ErrorCode;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n#endif /* CEC */\r\n#endif /* HAL_CEC_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_cortex.c\r\n  * @author  MCD Application Team\r\n  * @brief   CORTEX HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the CORTEX:\r\n  *           + Initialization and de-initialization functions\r\n  *           + Peripheral Control functions \r\n  *\r\n  @verbatim  \r\n  ==============================================================================\r\n                        ##### How to use this driver #####\r\n  ==============================================================================\r\n\r\n    [..]  \r\n    *** How to configure Interrupts using CORTEX HAL driver ***\r\n    ===========================================================\r\n    [..]     \r\n    This section provides functions allowing to configure the NVIC interrupts (IRQ).\r\n    The Cortex-M4 exceptions are managed by CMSIS functions.\r\n   \r\n    (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()\r\n        function according to the following table.\r\n    (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). \r\n    (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().\r\n    (#) please refer to programming manual for details in how to configure priority. \r\n      \r\n     -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. \r\n         The pending IRQ priority will be managed only by the sub priority.\r\n   \r\n     -@- IRQ priority order (sorted by highest to lowest priority):\r\n        (+@) Lowest preemption priority\r\n        (+@) Lowest sub priority\r\n        (+@) Lowest hardware priority (IRQ number)\r\n \r\n    [..]  \r\n    *** How to configure Systick using CORTEX HAL driver ***\r\n    ========================================================\r\n    [..]\r\n    Setup SysTick Timer for time base.\r\n           \r\n   (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which\r\n       is a CMSIS function that:\r\n        (++) Configures the SysTick Reload register with value passed as function parameter.\r\n        (++) Configures the SysTick IRQ priority to the lowest value (0x0F).\r\n        (++) Resets the SysTick Counter register.\r\n        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).\r\n        (++) Enables the SysTick Interrupt.\r\n        (++) Starts the SysTick Counter.\r\n    \r\n   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro\r\n       __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the\r\n       HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined\r\n       inside the stm32f7xx_hal_cortex.h file.\r\n\r\n   (+) You can change the SysTick IRQ priority by calling the\r\n       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function \r\n       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.\r\n\r\n   (+) To adjust the SysTick time base, use the following formula:\r\n                            \r\n       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)\r\n       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function\r\n       (++) Reload Value should not exceed 0xFFFFFF\r\n   \r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CORTEX CORTEX\r\n  * @brief CORTEX HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_CORTEX_MODULE_ENABLED\r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/* Private macros ------------------------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions\r\n  * @{\r\n  */\r\n\r\n\r\n/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions\r\n *  @brief    Initialization and Configuration functions \r\n *\r\n@verbatim    \r\n  ==============================================================================\r\n              ##### Initialization and de-initialization functions #####\r\n  ==============================================================================\r\n    [..]\r\n      This section provides the CORTEX HAL driver functions allowing to configure Interrupts\r\n      Systick functionalities \r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n\r\n/**\r\n  * @brief  Sets the priority grouping field (preemption priority and subpriority)\r\n  *         using the required unlock sequence.\r\n  * @param  PriorityGroup The priority grouping bits length. \r\n  *         This parameter can be one of the following values:\r\n  *         @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority\r\n  *                                    4 bits for subpriority\r\n  *         @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority\r\n  *                                    3 bits for subpriority\r\n  *         @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority\r\n  *                                    2 bits for subpriority\r\n  *         @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority\r\n  *                                    1 bits for subpriority\r\n  *         @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority\r\n  *                                    0 bits for subpriority\r\n  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. \r\n  *         The pending IRQ priority will be managed only by the subpriority. \r\n  * @retval None\r\n  */\r\nvoid HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));\r\n  \r\n  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */\r\n  NVIC_SetPriorityGrouping(PriorityGroup);\r\n}\r\n\r\n/**\r\n  * @brief  Sets the priority of an interrupt.\r\n  * @param  IRQn External interrupt number.\r\n  *         This parameter can be an enumerator of IRQn_Type enumeration\r\n  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r\n  * @param  PreemptPriority The preemption priority for the IRQn channel.\r\n  *         This parameter can be a value between 0 and 15\r\n  *         A lower priority value indicates a higher priority \r\n  * @param  SubPriority the subpriority level for the IRQ channel.\r\n  *         This parameter can be a value between 0 and 15\r\n  *         A lower priority value indicates a higher priority.          \r\n  * @retval None\r\n  */\r\nvoid HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)\r\n{ \r\n  uint32_t prioritygroup = 0x00;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));\r\n  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));\r\n  \r\n  prioritygroup = NVIC_GetPriorityGrouping();\r\n  \r\n  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));\r\n}\r\n\r\n/**\r\n  * @brief  Enables a device specific interrupt in the NVIC interrupt controller.\r\n  * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()\r\n  *         function should be called before. \r\n  * @param  IRQn External interrupt number.\r\n  *         This parameter can be an enumerator of IRQn_Type enumeration\r\n  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r\n  * @retval None\r\n  */\r\nvoid HAL_NVIC_EnableIRQ(IRQn_Type IRQn)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r\n  \r\n  /* Enable interrupt */\r\n  NVIC_EnableIRQ(IRQn);\r\n}\r\n\r\n/**\r\n  * @brief  Disables a device specific interrupt in the NVIC interrupt controller.\r\n  * @param  IRQn External interrupt number.\r\n  *         This parameter can be an enumerator of IRQn_Type enumeration\r\n  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r\n  * @retval None\r\n  */\r\nvoid HAL_NVIC_DisableIRQ(IRQn_Type IRQn)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r\n  \r\n  /* Disable interrupt */\r\n  NVIC_DisableIRQ(IRQn);\r\n}\r\n\r\n/**\r\n  * @brief  Initiates a system reset request to reset the MCU.\r\n  * @retval None\r\n  */\r\nvoid HAL_NVIC_SystemReset(void)\r\n{\r\n  /* System Reset */\r\n  NVIC_SystemReset();\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r\n  *         Counter is in free running mode to generate periodic interrupts.\r\n  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.\r\n  * @retval status:  - 0  Function succeeded.\r\n  *                  - 1  Function failed.\r\n  */\r\nuint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)\r\n{\r\n   return SysTick_Config(TicksNumb);\r\n}\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions\r\n *  @brief   Cortex control functions \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                      ##### Peripheral Control functions #####\r\n  ==============================================================================  \r\n    [..]\r\n      This subsection provides a set of functions allowing to control the CORTEX\r\n      (NVIC, SYSTICK, MPU) functionalities. \r\n \r\n      \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n#if (__MPU_PRESENT == 1)\r\n/**\r\n  * @brief  Disables the MPU\r\n  * @retval None\r\n  */\r\nvoid HAL_MPU_Disable(void)\r\n{\r\n  /* Make sure outstanding transfers are done */\r\n  __DMB();\r\n\r\n  /* Disable fault exceptions */\r\n  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\r\n  \r\n  /* Disable the MPU and clear the control register*/\r\n  MPU->CTRL = 0;\r\n}\r\n\r\n/**\r\n  * @brief  Enables the MPU\r\n  * @param  MPU_Control Specifies the control mode of the MPU during hard fault, \r\n  *          NMI, FAULTMASK and privileged access to the default memory \r\n  *          This parameter can be one of the following values:\r\n  *            @arg MPU_HFNMI_PRIVDEF_NONE\r\n  *            @arg MPU_HARDFAULT_NMI\r\n  *            @arg MPU_PRIVILEGED_DEFAULT\r\n  *            @arg MPU_HFNMI_PRIVDEF\r\n  * @retval None\r\n  */\r\nvoid HAL_MPU_Enable(uint32_t MPU_Control)\r\n{\r\n  /* Enable the MPU */\r\n  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\r\n  \r\n  /* Enable fault exceptions */\r\n  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\r\n  \r\n  /* Ensure MPU setting take effects */\r\n  __DSB();\r\n  __ISB();\r\n}\r\n\r\n/**\r\n  * @brief  Initializes and configures the Region and the memory to be protected.\r\n  * @param  MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains\r\n  *                the initialization and configuration information.\r\n  * @retval None\r\n  */\r\nvoid HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));\r\n  assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));\r\n\r\n  /* Set the Region number */\r\n  MPU->RNR = MPU_Init->Number;\r\n\r\n  if ((MPU_Init->Enable) != RESET)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));\r\n    assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));\r\n    assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));\r\n    assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));\r\n    assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));\r\n    assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));\r\n    assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));\r\n    assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));\r\n    \r\n    MPU->RBAR = MPU_Init->BaseAddress;\r\n    MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |\r\n                ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |\r\n                ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |\r\n                ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |\r\n                ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |\r\n                ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |\r\n                ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |\r\n                ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |\r\n                ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);\r\n  }\r\n  else\r\n  {\r\n    MPU->RBAR = 0x00;\r\n    MPU->RASR = 0x00;\r\n  }\r\n}\r\n#endif /* __MPU_PRESENT */\r\n\r\n/**\r\n  * @brief  Gets the priority grouping field from the NVIC Interrupt Controller.\r\n  * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)\r\n  */\r\nuint32_t HAL_NVIC_GetPriorityGrouping(void)\r\n{\r\n  /* Get the PRIGROUP[10:8] field value */\r\n  return NVIC_GetPriorityGrouping();\r\n}\r\n\r\n/**\r\n  * @brief  Gets the priority of an interrupt.\r\n  * @param  IRQn External interrupt number.\r\n  *         This parameter can be an enumerator of IRQn_Type enumeration\r\n  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r\n  * @param   PriorityGroup the priority grouping bits length.\r\n  *         This parameter can be one of the following values:\r\n  *           @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority\r\n  *                                      4 bits for subpriority\r\n  *           @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority\r\n  *                                      3 bits for subpriority\r\n  *           @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority\r\n  *                                      2 bits for subpriority\r\n  *           @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority\r\n  *                                      1 bits for subpriority\r\n  *           @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority\r\n  *                                      0 bits for subpriority\r\n  * @param  pPreemptPriority Pointer on the Preemptive priority value (starting from 0).\r\n  * @param  pSubPriority Pointer on the Subpriority value (starting from 0).\r\n  * @retval None\r\n  */\r\nvoid HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));\r\n /* Get priority for Cortex-M system or device specific interrupts */\r\n  NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);\r\n}\r\n\r\n/**\r\n  * @brief  Sets Pending bit of an external interrupt.\r\n  * @param  IRQn External interrupt number\r\n  *         This parameter can be an enumerator of IRQn_Type enumeration\r\n  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r\n  * @retval None\r\n  */\r\nvoid HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r\n  \r\n  /* Set interrupt pending */\r\n  NVIC_SetPendingIRQ(IRQn);\r\n}\r\n\r\n/**\r\n  * @brief  Gets Pending Interrupt (reads the pending register in the NVIC \r\n  *         and returns the pending bit for the specified interrupt).\r\n  * @param  IRQn External interrupt number.\r\n  *          This parameter can be an enumerator of IRQn_Type enumeration\r\n  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r\n  * @retval status: - 0  Interrupt status is not pending.\r\n  *                 - 1  Interrupt status is pending.\r\n  */\r\nuint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r\n  \r\n  /* Return 1 if pending else 0 */\r\n  return NVIC_GetPendingIRQ(IRQn);\r\n}\r\n\r\n/**\r\n  * @brief  Clears the pending bit of an external interrupt.\r\n  * @param  IRQn External interrupt number.\r\n  *         This parameter can be an enumerator of IRQn_Type enumeration\r\n  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r\n  * @retval None\r\n  */\r\nvoid HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r\n  \r\n  /* Clear pending interrupt */\r\n  NVIC_ClearPendingIRQ(IRQn);\r\n}\r\n\r\n/**\r\n  * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).\r\n  * @param IRQn External interrupt number\r\n  *         This parameter can be an enumerator of IRQn_Type enumeration\r\n  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r\n  * @retval status: - 0  Interrupt status is not pending.\r\n  *                 - 1  Interrupt status is pending.\r\n  */\r\nuint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r\n  \r\n  /* Return 1 if active else 0 */\r\n  return NVIC_GetActive(IRQn);\r\n}\r\n\r\n/**\r\n  * @brief  Configures the SysTick clock source.\r\n  * @param  CLKSource specifies the SysTick clock source.\r\n  *          This parameter can be one of the following values:\r\n  *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.\r\n  *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.\r\n  * @retval None\r\n  */\r\nvoid HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));\r\n  if (CLKSource == SYSTICK_CLKSOURCE_HCLK)\r\n  {\r\n    SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;\r\n  }\r\n  else\r\n  {\r\n    SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  This function handles SYSTICK interrupt request.\r\n  * @retval None\r\n  */\r\nvoid HAL_SYSTICK_IRQHandler(void)\r\n{\r\n  HAL_SYSTICK_Callback();\r\n}\r\n\r\n/**\r\n  * @brief  SYSTICK callback.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SYSTICK_Callback(void)\r\n{\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_SYSTICK_Callback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_CORTEX_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_crc.c\r\n  * @author  MCD Application Team\r\n  * @brief   CRC HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the Cyclic Redundancy Check (CRC) peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + Peripheral Control functions \r\n  *           + Peripheral State functions\r\n  *\r\n  @verbatim\r\n ===============================================================================\r\n                     ##### CRC How to use this driver #####\r\n ===============================================================================\r\n    [..]\r\n\r\n    (#) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();\r\n\r\n    (#) Initialize CRC calculator\r\n         (++) specify generating polynomial (IP default or non-default one)\r\n         (++) specify initialization value (IP default or non-default one)\r\n         (++) specify input data format\r\n         (++) specify input or output data inversion mode if any\r\n\r\n    (#) Use HAL_CRC_Accumulate() function to compute the CRC value of the \r\n        input data buffer starting with the previously computed CRC as \r\n        initialization value\r\n\r\n    (#) Use HAL_CRC_Calculate() function to compute the CRC value of the \r\n        input data buffer starting with the defined initialization value \r\n        (default or non-default) to initiate CRC calculation\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CRC CRC\r\n  * @brief CRC HAL module driver.\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_CRC_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\nstatic uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);\r\nstatic uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @defgroup CRC_Exported_Functions CRC Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup HAL_CRC_Group1 Initialization/de-initialization functions \r\n  *  @brief    Initialization and Configuration functions. \r\n  *\r\n@verbatim    \r\n ===============================================================================\r\n            ##### Initialization and de-initialization functions #####\r\n ===============================================================================\r\n    [..]  This section provides functions allowing to:\r\n      (+) Initialize the CRC according to the specified parameters \r\n          in the CRC_InitTypeDef and create the associated handle\r\n      (+) DeInitialize the CRC peripheral\r\n      (+) Initialize the CRC MSP\r\n      (+) DeInitialize CRC MSP \r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initialize the CRC according to the specified\r\n  *         parameters in the CRC_InitTypeDef and create the associated handle.\r\n  * @param  hcrc CRC handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)\r\n{\r\n  /* Check the CRC handle allocation */\r\n  if(hcrc == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));\r\n\r\n  if(hcrc->State == HAL_CRC_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    hcrc->Lock = HAL_UNLOCKED;\r\n    /* Init the low level hardware */\r\n    HAL_CRC_MspInit(hcrc);\r\n  }\r\n  \r\n  /* Change CRC peripheral state */\r\n  hcrc->State = HAL_CRC_STATE_BUSY;\r\n  \r\n  /* check whether or not non-default generating polynomial has been \r\n   * picked up by user */\r\n  assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse)); \r\n  if(hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)\r\n  {\r\n    /* initialize IP with default generating polynomial */\r\n    WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);  \r\n    MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);\r\n  }\r\n  else\r\n  {\r\n    /* initialize CRC IP with generating polynomial defined by user */\r\n    if(HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n  }\r\n  \r\n  /* check whether or not non-default CRC initial value has been \r\n   * picked up by user */\r\n  assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));\r\n  if(hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)\r\n  {\r\n    WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);  \r\n  }\r\n  else\r\n  {\r\n    WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);\r\n  }\r\n  \r\n\r\n  /* set input data inversion mode */\r\n  assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode)); \r\n  MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode); \r\n  \r\n  /* set output data inversion mode */\r\n  assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode)); \r\n  MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);  \r\n  \r\n  /* makes sure the input data format (bytes, halfwords or words stream)\r\n   * is properly specified by user */\r\n  assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));\r\n\r\n  /* Change CRC peripheral state */\r\n  hcrc->State = HAL_CRC_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  DeInitialize the CRC peripheral.\r\n  * @param  hcrc CRC handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)\r\n{\r\n  /* Check the CRC handle allocation */\r\n  if(hcrc == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));\r\n  \r\n  /* Check the CRC peripheral state */\r\n  if(hcrc->State == HAL_CRC_STATE_BUSY)\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n  \r\n  /* Change CRC peripheral state */\r\n  hcrc->State = HAL_CRC_STATE_BUSY;\r\n  \r\n  /* Reset CRC calculation unit */\r\n  __HAL_CRC_DR_RESET(hcrc);\r\n  \r\n  /* Reset IDR register content */\r\n  CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);\r\n\r\n  /* DeInit the low level hardware */\r\n  HAL_CRC_MspDeInit(hcrc);\r\n\r\n  /* Change CRC peripheral state */\r\n  hcrc->State = HAL_CRC_STATE_RESET;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hcrc);\r\n\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initialize the CRC MSP.\r\n  * @param  hcrc CRC handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcrc);\r\n  \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_CRC_MspInit can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DeInitialize the CRC MSP.\r\n  * @param  hcrc CRC handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcrc);\r\n  \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_CRC_MspDeInit can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_CRC_Group2 Peripheral Control functions \r\n  *  @brief   Peripheral Control functions \r\n  *\r\n@verbatim  \r\n ==============================================================================\r\n                      ##### Peripheral Control functions #####\r\n ==============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer\r\n          using combination of the previous CRC value and the new one.\r\n          \r\n          or\r\n          \r\n      (+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer\r\n          independently of the previous CRC value.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**                  \r\n  * @brief  Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer\r\n  *         starting with the previously computed CRC as initialization value.\r\n  * @param  hcrc CRC handle\r\n  * @param  pBuffer pointer to the input data buffer, exact input data format is\r\n  *         provided by hcrc->InputDataFormat.  \r\n  * @param  BufferLength input data buffer length (number of bytes if pBuffer\r\n  *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,\r\n  *         number of words if pBuffer type is * uint32_t).\r\n  * @note  By default, the API expects a uint32_t pointer as input buffer parameter.\r\n  *        Input buffer pointers with other types simply need to be cast in uint32_t\r\n  *        and the API will internally adjust its input data processing based on the  \r\n  *        handle field hcrc->InputDataFormat.  \r\n  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)\r\n  */\r\nuint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)\r\n{\r\n  uint32_t index = 0; /* CRC input data buffer index */\r\n  uint32_t temp = 0;  /* CRC output (read from hcrc->Instance->DR register) */\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hcrc); \r\n    \r\n  /* Change CRC peripheral state */  \r\n  hcrc->State = HAL_CRC_STATE_BUSY;\r\n  \r\n  switch (hcrc->InputDataFormat)\r\n  {\r\n    case CRC_INPUTDATA_FORMAT_WORDS:  \r\n      /* Enter Data to the CRC calculator */\r\n      for(index = 0; index < BufferLength; index++)\r\n      {\r\n        hcrc->Instance->DR = pBuffer[index];\r\n      }\r\n      temp = hcrc->Instance->DR;\r\n      break;\r\n      \r\n    case CRC_INPUTDATA_FORMAT_BYTES: \r\n      temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);\r\n      break;\r\n      \r\n    case CRC_INPUTDATA_FORMAT_HALFWORDS: \r\n      temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);\r\n      break;\r\n    default:\r\n      break;  \r\n  }\r\n  \r\n  /* Change CRC peripheral state */    \r\n  hcrc->State = HAL_CRC_STATE_READY; \r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hcrc);\r\n  \r\n  /* Return the CRC computed value */ \r\n  return temp;\r\n}\r\n\r\n/**                  \r\n  * @brief  Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer\r\n  *         starting with hcrc->Instance->INIT as initialization value.\r\n  * @param  hcrc CRC handle\r\n  * @param  pBuffer pointer to the input data buffer, exact input data format is\r\n  *         provided by hcrc->InputDataFormat.  \r\n  * @param  BufferLength input data buffer length (number of bytes if pBuffer\r\n  *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,\r\n  *         number of words if pBuffer type is * uint32_t).\r\n  * @note  By default, the API expects a uint32_t pointer as input buffer parameter.\r\n  *        Input buffer pointers with other types simply need to be cast in uint32_t\r\n  *        and the API will internally adjust its input data processing based on the  \r\n  *        handle field hcrc->InputDataFormat.   \r\n  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)\r\n  */  \r\nuint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)\r\n{\r\n  uint32_t index = 0; /* CRC input data buffer index */\r\n  uint32_t temp = 0;  /* CRC output (read from hcrc->Instance->DR register) */\r\n    \r\n  /* Process locked */\r\n  __HAL_LOCK(hcrc); \r\n  \r\n  /* Change CRC peripheral state */  \r\n  hcrc->State = HAL_CRC_STATE_BUSY;\r\n  \r\n  /* Reset CRC Calculation Unit (hcrc->Instance->INIT is \r\n  *  written in hcrc->Instance->DR) */\r\n  __HAL_CRC_DR_RESET(hcrc);\r\n  \r\n  switch (hcrc->InputDataFormat)\r\n  {\r\n    case CRC_INPUTDATA_FORMAT_WORDS:  \r\n      /* Enter 32-bit input data to the CRC calculator */\r\n      for(index = 0; index < BufferLength; index++)\r\n      {\r\n        hcrc->Instance->DR = pBuffer[index];\r\n      }\r\n      temp = hcrc->Instance->DR;\r\n      break;\r\n      \r\n    case CRC_INPUTDATA_FORMAT_BYTES: \r\n      /* Specific 8-bit input data handling  */\r\n      temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);\r\n      break;\r\n      \r\n    case CRC_INPUTDATA_FORMAT_HALFWORDS: \r\n      /* Specific 16-bit input data handling  */\r\n      temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);\r\n      break;\r\n    default:\r\n      break;\r\n  }\r\n\r\n  /* Change CRC peripheral state */\r\n  hcrc->State = HAL_CRC_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hcrc);\r\n  \r\n  /* Return the CRC computed value */ \r\n  return temp;\r\n}\r\n\r\n/**             \r\n  * @brief  Enter 8-bit input data to the CRC calculator.\r\n  *         Specific data handling to optimize processing time.  \r\n  * @param  hcrc CRC handle\r\n  * @param  pBuffer pointer to the input data buffer\r\n  * @param  BufferLength input data buffer length\r\n  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)\r\n  */\r\nstatic uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)\r\n{\r\n  uint32_t i = 0; /* input data buffer index */\r\n  \r\n   /* Processing time optimization: 4 bytes are entered in a row with a single word write,\r\n    * last bytes must be carefully fed to the CRC calculator to ensure a correct type\r\n    * handling by the IP */\r\n   for(i = 0; i < (BufferLength/4); i++)\r\n   {\r\n     hcrc->Instance->DR = (uint32_t)(((uint32_t)(pBuffer[4*i])<<24) | ((uint32_t)(pBuffer[4*i+1])<<16) | ((uint32_t)(pBuffer[4*i+2])<<8) | (uint32_t)(pBuffer[4*i+3]));\r\n   }\r\n   /* last bytes specific handling */\r\n   if((BufferLength%4) != 0)\r\n   {\r\n     if(BufferLength%4 == 1)\r\n     {\r\n       *(__IO uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i];\r\n     }\r\n     if(BufferLength%4 == 2)\r\n     {\r\n       *(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)((uint16_t)((uint16_t)(pBuffer[4*i])<<8) | (uint16_t)(pBuffer[4*i+1]));\r\n     }\r\n     if(BufferLength%4 == 3)\r\n     {\r\n       *(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)((uint16_t)((uint16_t)(pBuffer[4*i])<<8) | (uint16_t)(pBuffer[4*i+1]));\r\n       *(__IO uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i+2];       \r\n     }\r\n   }\r\n  \r\n  /* Return the CRC computed value */ \r\n  return hcrc->Instance->DR;\r\n}\r\n\r\n/**             \r\n  * @brief  Enter 16-bit input data to the CRC calculator.\r\n  *         Specific data handling to optimize processing time.  \r\n  * @param  hcrc CRC handle\r\n  * @param  pBuffer pointer to the input data buffer\r\n  * @param  BufferLength input data buffer length\r\n  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)\r\n  */  \r\nstatic uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)\r\n{\r\n  uint32_t i = 0;  /* input data buffer index */\r\n  \r\n  /* Processing time optimization: 2 HalfWords are entered in a row with a single word write,\r\n   * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure \r\n   * a correct type handling by the IP */\r\n  for(i = 0; i < (BufferLength/2); i++)\r\n  {\r\n    hcrc->Instance->DR = (((uint32_t)(pBuffer[2*i])<<16) | (uint32_t)(pBuffer[2*i+1]));\r\n  }\r\n  if((BufferLength%2) != 0)\r\n  {\r\n     *(__IO uint16_t*) (&hcrc->Instance->DR) = pBuffer[2*i]; \r\n  }\r\n   \r\n  /* Return the CRC computed value */ \r\n  return hcrc->Instance->DR;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_CRC_Group3 Peripheral State functions \r\n  *  @brief    Peripheral State functions. \r\n  *\r\n@verbatim   \r\n ==============================================================================\r\n                      ##### Peripheral State functions #####\r\n ==============================================================================  \r\n    [..]\r\n    This subsection permits to get in run-time the status of the peripheral \r\n    and the data flow.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Return the CRC state.\r\n  * @param  hcrc CRC handle\r\n  * @retval HAL state\r\n  */\r\nHAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)\r\n{\r\n  return hcrc->State;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_CRC_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc_ex.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_crc_ex.c\r\n  * @author  MCD Application Team\r\n  * @brief   Extended CRC HAL module driver.\r\n  *    \r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the CRC peripheral:\r\n  *           + Initialization/de-initialization functions\r\n  *         \r\n  @verbatim\r\n  ==============================================================================\r\n                    ##### CRC specific features #####\r\n  ==============================================================================\r\n  [..] \r\n  (#) Polynomial configuration.\r\n  (#) Input data reverse mode.\r\n  (#) Output data reverse mode.\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************  \r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup CRCEx\r\n  * @brief CRC Extended HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_CRC_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @addtogroup CRCEx_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup CRCEx_Exported_Functions_Group1\r\n *  @brief    Extended CRC features functions\r\n *\r\n@verbatim   \r\n ===============================================================================\r\n            ##### CRC Extended features functions #####\r\n ===============================================================================  \r\n    [..]\r\nThis subsection provides function allowing to:\r\n      (+) Set CRC polynomial if different from default one.\r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n\r\n/**\r\n  * @brief  Initializes the CRC polynomial if different from default one.\r\n  * @param  hcrc CRC handle\r\n  * @param  Pol CRC generating polynomial (7, 8, 16 or 32-bit long)\r\n  *         This parameter is written in normal representation, e.g.\r\n  *         for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 \r\n  *         for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021     \r\n  * @param  PolyLength CRC polynomial length \r\n  *         This parameter can be one of the following values:\r\n  *          @arg CRC_POLYLENGTH_7B: 7-bit long CRC (generating polynomial of degree 7)\r\n  *          @arg CRC_POLYLENGTH_8B: 8-bit long CRC (generating polynomial of degree 8)\r\n  *          @arg CRC_POLYLENGTH_16B: 16-bit long CRC (generating polynomial of degree 16)\r\n  *          @arg CRC_POLYLENGTH_32B: 32-bit long CRC (generating polynomial of degree 32)                \r\n  * @retval HAL status\r\n  */                                   \r\nHAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)\r\n{\r\n  uint32_t msb = 31; /* polynomial degree is 32 at most, so msb is initialized to max value */\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_CRC_POL_LENGTH(PolyLength));\r\n  \r\n  /* check polynomial definition vs polynomial size:\r\n   * polynomial length must be aligned with polynomial\r\n   * definition. HAL_ERROR is reported if Pol degree is \r\n   * larger than that indicated by PolyLength.\r\n   * Look for MSB position: msb will contain the degree of\r\n   *  the second to the largest polynomial member. E.g., for\r\n   *  X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */\r\n  while (((Pol & ((uint32_t)(0x1) << msb)) == 0) && (msb-- > 0))\r\n  {\r\n  }\r\n\r\n  switch (PolyLength)\r\n  {\r\n    case CRC_POLYLENGTH_7B:\r\n      if (msb >= HAL_CRC_LENGTH_7B)\r\n      { \r\n        return  HAL_ERROR;\r\n      }\r\n      break;\r\n    case CRC_POLYLENGTH_8B:\r\n      if (msb >= HAL_CRC_LENGTH_8B)\r\n      {\r\n        return  HAL_ERROR;\r\n      }\r\n      break;\r\n    case CRC_POLYLENGTH_16B:\r\n      if (msb >= HAL_CRC_LENGTH_16B)\r\n      {\r\n        return  HAL_ERROR;\r\n      }\r\n      break;\r\n    case CRC_POLYLENGTH_32B:\r\n      /* no polynomial definition vs. polynomial length issue possible */\r\n      break;\r\n  default:\r\n      break;\r\n  }\r\n\r\n  /* set generating polynomial */\r\n  WRITE_REG(hcrc->Instance->POL, Pol);\r\n  \r\n  /* set generating polynomial size */\r\n  MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);  \r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Set the Reverse Input data mode.\r\n  * @param  hcrc CRC handle\r\n  * @param  InputReverseMode Input Data inversion mode\r\n  *         This parameter can be one of the following values:\r\n  *          @arg CRC_INPUTDATA_INVERSION_NONE: no change in bit order (default value)\r\n  *          @arg CRC_INPUTDATA_INVERSION_BYTE: Byte-wise bit reversal\r\n  *          @arg CRC_INPUTDATA_INVERSION_HALFWORD: HalfWord-wise bit reversal\r\n  *          @arg CRC_INPUTDATA_INVERSION_WORD: Word-wise bit reversal              \r\n  * @retval HAL status\r\n  */                                   \r\nHAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)\r\n{  \r\n  /* Check the parameters */\r\n  assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));\r\n  \r\n  /* Change CRC peripheral state */\r\n  hcrc->State = HAL_CRC_STATE_BUSY;\r\n\r\n  /* set input data inversion mode */\r\n  MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode);    \r\n  /* Change CRC peripheral state */\r\n  hcrc->State = HAL_CRC_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Set the Reverse Output data mode.\r\n  * @param  hcrc CRC handle\r\n  * @param  OutputReverseMode Output Data inversion mode\r\n  *         This parameter can be one of the following values:\r\n  *          @arg CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion (default value)\r\n  *          @arg CRC_OUTPUTDATA_INVERSION_ENABLE: bit-level inversion (e.g for a 8-bit CRC: 0xB5 becomes 0xAD)\r\n  * @retval HAL status\r\n  */                                   \r\nHAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));\r\n  \r\n  /* Change CRC peripheral state */\r\n  hcrc->State = HAL_CRC_STATE_BUSY;\r\n\r\n  /* set output data inversion mode */\r\n  MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode); \r\n      \r\n  /* Change CRC peripheral state */\r\n  hcrc->State = HAL_CRC_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n#endif /* HAL_CRC_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cryp.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_cryp.c\r\n  * @author  MCD Application Team\r\n  * @brief   CRYP HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the Cryptography (CRYP) peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + AES processing functions\r\n  *           + DES processing functions\r\n  *           + TDES processing functions\r\n  *           + DMA callback functions\r\n  *           + CRYP IRQ handler management\r\n  *           + Peripheral State functions\r\n  *\r\n  @verbatim\r\n  ==============================================================================\r\n                     ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]\r\n      The CRYP HAL driver can be used as follows:\r\n\r\n      (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():\r\n         (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()\r\n         (##) In case of using interrupts (e.g. HAL_CRYP_AESECB_Encrypt_IT())\r\n             (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()\r\n             (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()\r\n             (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()\r\n         (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_AESECB_Encrypt_DMA())\r\n             (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()\r\n             (+++) Configure and enable two DMA streams one for managing data transfer from\r\n                 memory to peripheral (input stream) and another stream for managing data\r\n                 transfer from peripheral to memory (output stream)\r\n             (+++) Associate the initialized DMA handle to the CRYP DMA handle\r\n                 using  __HAL_LINKDMA()\r\n             (+++) Configure the priority and enable the NVIC for the transfer complete\r\n                 interrupt on the two DMA Streams. The output stream should have higher\r\n                 priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()\r\n    \r\n      (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:\r\n         (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit\r\n         (##) The key size: 128, 192 and 256. This parameter is relevant only for AES\r\n         (##) The encryption/decryption key. It's size depends on the algorithm\r\n              used for encryption/decryption\r\n         (##) The initialization vector (counter). It is not used ECB mode.\r\n    \r\n      (#)Three processing (encryption/decryption) functions are available:\r\n         (##) Polling mode: encryption and decryption APIs are blocking functions\r\n              i.e. they process the data and wait till the processing is finished,\r\n              e.g. HAL_CRYP_AESCBC_Encrypt()\r\n         (##) Interrupt mode: encryption and decryption APIs are not blocking functions\r\n              i.e. they process the data under interrupt,\r\n              e.g. HAL_CRYP_AESCBC_Encrypt_IT()\r\n         (##) DMA mode: encryption and decryption APIs are not blocking functions\r\n              i.e. the data transfer is ensured by DMA,\r\n              e.g. HAL_CRYP_AESCBC_Encrypt_DMA()\r\n    \r\n      (#)When the processing function is called at first time after HAL_CRYP_Init()\r\n         the CRYP peripheral is initialized and processes the buffer in input.\r\n         At second call, the processing function performs an append of the already\r\n         processed buffer.\r\n         When a new data block is to be processed, call HAL_CRYP_Init() then the\r\n         processing function.\r\n    \r\n       (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n#ifdef HAL_CRYP_MODULE_ENABLED\r\n\r\n#if defined (CRYP)\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n/** @defgroup CRYP CRYP\r\n  * @brief CRYP HAL module driver.\r\n  * @{\r\n  */\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @addtogroup CRYP_Private_define\r\n  * @{\r\n  */\r\n#define CRYP_TIMEOUT_VALUE  1\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/** @addtogroup CRYP_Private_Functions_prototypes\r\n  * @{\r\n  */  \r\nstatic void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize);\r\nstatic void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize);\r\nstatic HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);\r\nstatic HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);\r\nstatic void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);\r\nstatic void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);\r\nstatic void CRYP_DMAError(DMA_HandleTypeDef *hdma);\r\nstatic void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);\r\nstatic void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);\r\nstatic void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);\r\nstatic void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);\r\nstatic void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);\r\n/**\r\n  * @}\r\n  */ \r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @addtogroup CRYP_Private_Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  DMA CRYP Input Data process complete callback.\r\n  * @param  hdma DMA handle\r\n  * @retval None\r\n  */\r\nstatic void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)  \r\n{\r\n  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n  \r\n  /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit\r\n     in the DMACR register */\r\n  hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);\r\n  \r\n  /* Call input data transfer complete callback */\r\n  HAL_CRYP_InCpltCallback(hcryp);\r\n}\r\n\r\n/**\r\n  * @brief  DMA CRYP Output Data process complete callback.\r\n  * @param  hdma DMA handle\r\n  * @retval None\r\n  */\r\nstatic void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n  \r\n  /* Disable the DMA transfer for output FIFO request by resetting the DOEN bit\r\n     in the DMACR register */\r\n  hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);\r\n  \r\n  /* Disable CRYP */\r\n  __HAL_CRYP_DISABLE(hcryp);\r\n  \r\n  /* Change the CRYP state to ready */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Call output data transfer complete callback */\r\n  HAL_CRYP_OutCpltCallback(hcryp);\r\n}\r\n\r\n/**\r\n  * @brief  DMA CRYP communication error callback. \r\n  * @param  hdma DMA handle\r\n  * @retval None\r\n  */\r\nstatic void CRYP_DMAError(DMA_HandleTypeDef *hdma)\r\n{\r\n  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n  hcryp->State= HAL_CRYP_STATE_READY;\r\n  HAL_CRYP_ErrorCallback(hcryp);\r\n}\r\n\r\n/**\r\n  * @brief  Writes the Key in Key registers. \r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  Key Pointer to Key buffer\r\n  * @param  KeySize Size of Key\r\n  * @retval None\r\n  */\r\nstatic void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize)\r\n{\r\n  uint32_t keyaddr = (uint32_t)Key;\r\n  \r\n  switch(KeySize)\r\n  {\r\n  case CRYP_KEYSIZE_256B:\r\n    /* Key Initialisation */\r\n    hcryp->Instance->K0LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K0RR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));\r\n    break;\r\n  case CRYP_KEYSIZE_192B:\r\n    hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));\r\n    break;\r\n  case CRYP_KEYSIZE_128B:       \r\n    hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));\r\n    break;\r\n  default:\r\n    break;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Writes the InitVector/InitCounter in IV registers. \r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  InitVector Pointer to InitVector/InitCounter buffer\r\n  * @param  IVSize Size of the InitVector/InitCounter\r\n  * @retval None\r\n  */\r\nstatic void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize)\r\n{\r\n  uint32_t ivaddr = (uint32_t)InitVector;\r\n  \r\n  switch(IVSize)\r\n  {\r\n  case CRYP_KEYSIZE_128B:\r\n    hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));\r\n    ivaddr+=4;\r\n    hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));\r\n    ivaddr+=4;\r\n    hcryp->Instance->IV1LR = __REV(*(uint32_t*)(ivaddr));\r\n    ivaddr+=4;\r\n    hcryp->Instance->IV1RR = __REV(*(uint32_t*)(ivaddr));\r\n    break;\r\n    /* Whatever key size 192 or 256, Init vector is written in IV0LR and IV0RR */\r\n  case CRYP_KEYSIZE_192B:\r\n    hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));\r\n    ivaddr+=4;\r\n    hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));\r\n    break;\r\n  case CRYP_KEYSIZE_256B:\r\n    hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));\r\n    ivaddr+=4;\r\n    hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));\r\n    break;\r\n  default:\r\n    break;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Process Data: Writes Input data in polling mode and read the output data\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  Input Pointer to the Input buffer\r\n  * @param  Ilength Length of the Input buffer, must be a multiple of 16.\r\n  * @param  Output Pointer to the returned buffer\r\n  * @param  Timeout Timeout value\r\n  * @retval None\r\n  */\r\nstatic HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  uint32_t i = 0;\r\n  uint32_t inputaddr  = (uint32_t)Input;\r\n  uint32_t outputaddr = (uint32_t)Output;\r\n  \r\n  for(i=0; (i < Ilength); i+=16)\r\n  {\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    \r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n    while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))\r\n    {    \r\n      /* Check for the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n        \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n  }\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Process Data: Write Input data in polling mode. \r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  Input Pointer to the Input buffer\r\n  * @param  Ilength Length of the Input buffer, must be a multiple of 8\r\n  * @param  Output Pointer to the returned buffer\r\n  * @param  Timeout Specify Timeout value  \r\n  * @retval None\r\n  */\r\nstatic HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  \r\n  uint32_t i = 0;\r\n  uint32_t inputaddr  = (uint32_t)Input;\r\n  uint32_t outputaddr = (uint32_t)Output;\r\n  \r\n  for(i=0; (i < Ilength); i+=8)\r\n  {\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    \r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n    \r\n    while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))\r\n    {\r\n      /* Check for the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */          \r\n          __HAL_UNLOCK(hcryp);\r\n          \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n  }\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Set the DMA configuration and start the DMA transfer\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  inputaddr address of the Input buffer\r\n  * @param  Size Size of the Input buffer, must be a multiple of 16.\r\n  * @param  outputaddr address of the Output buffer\r\n  * @retval None\r\n  */\r\nstatic void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)\r\n{\r\n  /* Set the CRYP DMA transfer complete callback */\r\n  hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;\r\n  /* Set the DMA error callback */\r\n  hcryp->hdmain->XferErrorCallback = CRYP_DMAError;\r\n  \r\n  /* Set the CRYP DMA transfer complete callback */\r\n  hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;\r\n  /* Set the DMA error callback */\r\n  hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;\r\n  \r\n  /* Enable CRYP */\r\n  __HAL_CRYP_ENABLE(hcryp);\r\n  \r\n  /* Enable the DMA In DMA Stream */\r\n  HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DR, Size/4);\r\n\r\n  /* Enable In DMA request */\r\n  hcryp->Instance->DMACR = (CRYP_DMACR_DIEN);\r\n  \r\n  /* Enable the DMA Out DMA Stream */\r\n  HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size/4);\r\n  \r\n  /* Enable Out DMA request */\r\n  hcryp->Instance->DMACR |= CRYP_DMACR_DOEN;\r\n \r\n}\r\n\r\n/**\r\n  * @brief  Sets the CRYP peripheral in DES ECB mode.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  Direction Encryption or decryption\r\n  * @retval None\r\n  */\r\nstatic void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)\r\n{\r\n  /* Check if initialization phase has already been performed */\r\n  if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n  {\r\n    /* Set the CRYP peripheral in AES ECB mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_DES_ECB | Direction);\r\n    \r\n    /* Set the key */\r\n    hcryp->Instance->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));\r\n    hcryp->Instance->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4));\r\n    \r\n    /* Flush FIFO */\r\n    __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n    /* Set the phase */\r\n    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Sets the CRYP peripheral in DES CBC mode.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  Direction Encryption or decryption\r\n  * @retval None\r\n  */\r\nstatic void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)\r\n{\r\n  /* Check if initialization phase has already been performed */\r\n  if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n  {\r\n    /* Set the CRYP peripheral in AES ECB mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_DES_CBC | Direction);\r\n    \r\n    /* Set the key */\r\n    hcryp->Instance->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));\r\n    hcryp->Instance->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4));\r\n    \r\n    /* Set the Initialization Vector */\r\n    CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);\r\n    \r\n    /* Flush FIFO */\r\n    __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n    /* Set the phase */\r\n    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Sets the CRYP peripheral in TDES ECB mode.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  Direction Encryption or decryption\r\n  * @retval None\r\n  */\r\nstatic void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)\r\n{\r\n  /* Check if initialization phase has already been performed */\r\n  if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n  {\r\n    /* Set the CRYP peripheral in AES ECB mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_TDES_ECB | Direction);\r\n    \r\n    /* Set the key */\r\n    CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);\r\n    \r\n    /* Flush FIFO */\r\n    __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n    /* Set the phase */\r\n    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Sets the CRYP peripheral in TDES CBC mode\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  Direction Encryption or decryption\r\n  * @retval None\r\n  */\r\nstatic void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)\r\n{\r\n  /* Check if initialization phase has already been performed */\r\n  if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n  {\r\n    /* Set the CRYP peripheral in AES CBC mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_TDES_CBC | Direction);\r\n    \r\n    /* Set the key */\r\n    CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);\r\n    \r\n    /* Set the Initialization Vector */\r\n    CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);\r\n    \r\n    /* Flush FIFO */\r\n    __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n    /* Set the phase */\r\n    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n /* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup CRYP_Exported_Functions\r\n  * @{\r\n  */ \r\n  \r\n/** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions \r\n *  @brief    Initialization and Configuration functions. \r\n *\r\n@verbatim    \r\n  ==============================================================================\r\n              ##### Initialization and de-initialization functions #####\r\n  ==============================================================================\r\n    [..]  This section provides functions allowing to:\r\n      (+) Initialize the CRYP according to the specified parameters \r\n          in the CRYP_InitTypeDef and creates the associated handle\r\n      (+) DeInitialize the CRYP peripheral\r\n      (+) Initialize the CRYP MSP\r\n      (+) DeInitialize CRYP MSP \r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the CRYP according to the specified\r\n  *         parameters in the CRYP_InitTypeDef and creates the associated handle.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)\r\n{ \r\n  /* Check the CRYP handle allocation */\r\n  if(hcryp == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));\r\n  assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));\r\n    \r\n  if(hcryp->State == HAL_CRYP_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    hcryp->Lock = HAL_UNLOCKED;\r\n    /* Init the low level hardware */\r\n    HAL_CRYP_MspInit(hcryp);\r\n  }\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Set the key size and data type*/\r\n  CRYP->CR = (uint32_t) (hcryp->Init.KeySize | hcryp->Init.DataType);\r\n  \r\n  /* Reset CrypInCount and CrypOutCount */\r\n  hcryp->CrypInCount = 0;\r\n  hcryp->CrypOutCount = 0;\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Set the default CRYP phase */\r\n  hcryp->Phase = HAL_CRYP_PHASE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the CRYP peripheral. \r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)\r\n{\r\n  /* Check the CRYP handle allocation */\r\n  if(hcryp == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Set the default CRYP phase */\r\n  hcryp->Phase = HAL_CRYP_PHASE_READY;\r\n  \r\n  /* Reset CrypInCount and CrypOutCount */\r\n  hcryp->CrypInCount = 0;\r\n  hcryp->CrypOutCount = 0;\r\n  \r\n  /* Disable the CRYP Peripheral Clock */\r\n  __HAL_CRYP_DISABLE(hcryp);\r\n  \r\n  /* DeInit the low level hardware: CLOCK, NVIC.*/\r\n  HAL_CRYP_MspDeInit(hcryp);\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_RESET;\r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hcryp);\r\n\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP MSP.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @retval None\r\n  */\r\n__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcryp);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_CRYP_MspInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes CRYP MSP.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @retval None\r\n  */\r\n__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcryp);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_CRYP_MspDeInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRYP_Exported_Functions_Group2 AES processing functions \r\n *  @brief   processing functions. \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                      ##### AES processing functions #####\r\n  ==============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Encrypt plaintext using AES-128/192/256 using chaining modes\r\n      (+) Decrypt cyphertext using AES-128/192/256 using chaining modes\r\n    [..]  Three processing functions are available:\r\n      (+) Polling mode\r\n      (+) Interrupt mode\r\n      (+) DMA mode\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES ECB encryption mode\r\n  *         then encrypt pPlainData. The cypher data are available in pCypherData\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 16.\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Timeout Specify Timeout value \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n  {\r\n    /* Set the key */\r\n    CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n    \r\n    /* Set the CRYP peripheral in AES ECB mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);\r\n    \r\n    /* Flush FIFO */\r\n    __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Set the phase */\r\n    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n  }\r\n  \r\n    /* Write Plain Data and Get Cypher Data */\r\n    if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES CBC encryption mode\r\n  *         then encrypt pPlainData. The cypher data are available in pCypherData\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 16.\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Timeout Specify Timeout value  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n  {\r\n    /* Set the key */\r\n    CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n    \r\n    /* Set the CRYP peripheral in AES ECB mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);\r\n    \r\n    /* Set the Initialization Vector */\r\n    CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r\n    \r\n    /* Flush FIFO */\r\n    __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Set the phase */\r\n    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n  }\r\n  \r\n    /* Write Plain Data and Get Cypher Data */\r\n    if(CRYP_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES CTR encryption mode\r\n  *         then encrypt pPlainData. The cypher data are available in pCypherData\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 16.\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Timeout Specify Timeout value  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r\n{  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n  {\r\n    /* Set the key */\r\n    CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n    \r\n    /* Set the CRYP peripheral in AES ECB mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);\r\n    \r\n    /* Set the Initialization Vector */\r\n    CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r\n    \r\n    /* Flush FIFO */\r\n    __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Set the phase */\r\n    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n  }\r\n  \r\n    /* Write Plain Data and Get Cypher Data */\r\n    if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES ECB decryption mode\r\n  *         then decrypted pCypherData. The cypher data are available in pPlainData\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 16.\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Timeout Specify Timeout value  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r\n{\r\n   uint32_t tickstart = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n  {\r\n    /* Set the key */\r\n    CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n    \r\n    /* Set the CRYP peripheral in AES Key mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Get tick */ \r\n    tickstart = HAL_GetTick();\r\n\r\n    while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))\r\n    {\r\n      /* Check for the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */          \r\n          __HAL_UNLOCK(hcryp);\r\n        \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n    \r\n    /* Disable CRYP */\r\n    __HAL_CRYP_DISABLE(hcryp);\r\n    \r\n    /* Reset the ALGOMODE bits*/\r\n    CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);\r\n    \r\n    /* Set the CRYP peripheral in AES ECB decryption mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);\r\n    /* Flush FIFO */\r\n    __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Set the phase */\r\n    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n  }\r\n    \r\n    /* Write Plain Data and Get Cypher Data */\r\n    if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES ECB decryption mode\r\n  *         then decrypted pCypherData. The cypher data are available in pPlainData\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 16.\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Timeout Specify Timeout value  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n  {\r\n    /* Set the key */\r\n    CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n    \r\n    /* Set the CRYP peripheral in AES Key mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Get tick */ \r\n    tickstart = HAL_GetTick();\r\n\r\n    while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))\r\n    {\r\n      /* Check for the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n          \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n    \r\n    /* Reset the ALGOMODE bits*/\r\n    CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);\r\n    \r\n    /* Set the CRYP peripheral in AES CBC decryption mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);\r\n    \r\n    /* Set the Initialization Vector */\r\n    CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r\n    \r\n    /* Flush FIFO */\r\n    __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Set the phase */\r\n    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n  }\r\n  \r\n    /* Write Plain Data and Get Cypher Data */\r\n    if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES CTR decryption mode\r\n  *         then decrypted pCypherData. The cypher data are available in pPlainData\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 16.\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Timeout Specify Timeout value  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r\n{  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n  {\r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Set the key */\r\n    CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n    \r\n    /* Set the CRYP peripheral in AES CTR mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);\r\n    \r\n    /* Set the Initialization Vector */\r\n    CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r\n    \r\n    /* Flush FIFO */\r\n    __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Set the phase */\r\n    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n  }\r\n  \r\n    /* Write Plain Data and Get Cypher Data */\r\n    if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES ECB encryption mode using Interrupt.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 16 bytes\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pPlainData;\r\n    hcryp->pCrypOutBuffPtr = pCypherData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {\r\n      /* Set the key */\r\n      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES ECB mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n     /* Set the phase */\r\n     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n    \r\n    /* Enable Interrupts */\r\n    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    hcryp->pCrypInBuffPtr += 16;\r\n    hcryp->CrypInCount -= 16;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call the Input data transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    hcryp->pCrypOutBuffPtr += 16;\r\n    hcryp->CrypOutCount -= 16;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Process Locked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES CBC encryption mode using Interrupt.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 16 bytes\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pPlainData;\r\n    hcryp->pCrypOutBuffPtr = pCypherData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {      \r\n      /* Set the key */\r\n      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES CBC mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);\r\n      \r\n      /* Set the Initialization Vector */\r\n      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n     /* Set the phase */\r\n     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n    /* Enable Interrupts */\r\n    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    hcryp->pCrypInBuffPtr += 16;\r\n    hcryp->CrypInCount -= 16;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call the Input data transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    hcryp->pCrypOutBuffPtr += 16;\r\n    hcryp->CrypOutCount -= 16;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Process Locked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES CTR encryption mode using Interrupt.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 16 bytes\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pPlainData;\r\n    hcryp->pCrypOutBuffPtr = pCypherData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {\r\n      /* Set the key */\r\n      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES CTR mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);\r\n      \r\n      /* Set the Initialization Vector */\r\n      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n     /* Set the phase */\r\n     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n    /* Enable Interrupts */\r\n    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    hcryp->pCrypInBuffPtr += 16;\r\n    hcryp->CrypInCount -= 16;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call the Input data transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    hcryp->pCrypOutBuffPtr += 16;\r\n    hcryp->CrypOutCount -= 16;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES ECB decryption mode using Interrupt.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 16.\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  uint32_t tickstart = 0;\r\n\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pCypherData;\r\n    hcryp->pCrypOutBuffPtr = pPlainData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n  /* Check if initialization phase has already been performed */\r\n  if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n  {\r\n    /* Set the key */\r\n    CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n    \r\n    /* Set the CRYP peripheral in AES Key mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);\r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Get tick */ \r\n    tickstart = HAL_GetTick();\r\n\r\n    while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))\r\n    {\r\n      /* Check for the Timeout */\r\n      if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)\r\n      {\r\n        /* Change state */\r\n        hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hcryp);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n    \r\n    /* Reset the ALGOMODE bits*/\r\n    CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);\r\n    \r\n    /* Set the CRYP peripheral in AES ECB decryption mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);\r\n    \r\n    /* Flush FIFO */\r\n    __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n     /* Set the phase */\r\n     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n  }\r\n     \r\n    /* Enable Interrupts */\r\n    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    hcryp->pCrypInBuffPtr += 16;\r\n    hcryp->CrypInCount -= 16;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call the Input data transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    hcryp->pCrypOutBuffPtr += 16;\r\n    hcryp->CrypOutCount -= 16;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES CBC decryption mode using IT.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 16\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n\r\n  uint32_t tickstart = 0;   \r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    /* Get the buffer addresses and sizes */    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pCypherData;\r\n    hcryp->pCrypOutBuffPtr = pPlainData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {\r\n      /* Set the key */\r\n      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES Key mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);\r\n      \r\n      /* Enable CRYP */\r\n      __HAL_CRYP_ENABLE(hcryp);\r\n      \r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n    while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))\r\n    {\r\n      /* Check for the Timeout */\r\n      if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)\r\n      {\r\n        /* Change state */\r\n        hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hcryp);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n    \r\n      /* Reset the ALGOMODE bits*/\r\n      CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);\r\n    \r\n      /* Set the CRYP peripheral in AES CBC decryption mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);\r\n    \r\n      /* Set the Initialization Vector */\r\n      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r\n    \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n      /* Enable CRYP */\r\n      __HAL_CRYP_ENABLE(hcryp);\r\n      \r\n      /* Set the phase */\r\n      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n    \r\n    /* Enable Interrupts */\r\n    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    hcryp->pCrypInBuffPtr += 16;\r\n    hcryp->CrypInCount -= 16;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call the Input data transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    hcryp->pCrypOutBuffPtr += 16;\r\n    hcryp->CrypOutCount -= 16;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES CTR decryption mode using Interrupt.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 16\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    /* Get the buffer addresses and sizes */    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pCypherData;\r\n    hcryp->pCrypOutBuffPtr = pPlainData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {\r\n      /* Set the key */\r\n      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES CTR mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);\r\n      \r\n      /* Set the Initialization Vector */\r\n      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n      /* Set the phase */\r\n      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n    \r\n    /* Enable Interrupts */\r\n    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    hcryp->pCrypInBuffPtr += 16;\r\n    hcryp->CrypInCount -= 16;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call the Input data transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    hcryp->pCrypOutBuffPtr += 16;\r\n    hcryp->CrypOutCount -= 16;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES ECB encryption mode using DMA.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 16 bytes\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pPlainData;\r\n    outputaddr = (uint32_t)pCypherData;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {\r\n      /* Set the key */\r\n      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES ECB mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n     /* Set the phase */\r\n     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n    /* Set the input and output addresses and start DMA transfer */ \r\n    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hcryp);\r\n     \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES CBC encryption mode using DMA.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 16.\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pPlainData;\r\n    outputaddr = (uint32_t)pCypherData;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {\r\n      /* Set the key */\r\n      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES ECB mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);\r\n      \r\n      /* Set the Initialization Vector */\r\n      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n       /* Set the phase */\r\n       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n     }\r\n     /* Set the input and output addresses and start DMA transfer */ \r\n     CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n     \r\n     /* Process Unlocked */\r\n     __HAL_UNLOCK(hcryp);\r\n     \r\n     /* Return function status */\r\n     return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES CTR encryption mode using DMA.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 16.\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pPlainData;\r\n    outputaddr = (uint32_t)pCypherData;\r\n    \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {\r\n      /* Set the key */\r\n      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES ECB mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);\r\n      \r\n      /* Set the Initialization Vector */\r\n      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n       /* Set the phase */\r\n       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n    \r\n    /* Set the input and output addresses and start DMA transfer */ \r\n    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES ECB decryption mode using DMA.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 16 bytes\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pCypherData;\r\n    outputaddr = (uint32_t)pPlainData;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {\r\n    /* Set the key */\r\n    CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n    \r\n    /* Set the CRYP peripheral in AES Key mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n    \r\n    while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))\r\n    {\r\n      /* Check for the Timeout */\r\n      if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)\r\n      {\r\n        /* Change state */\r\n        hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hcryp);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n    \r\n    /* Reset the ALGOMODE bits*/\r\n    CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);\r\n    \r\n    /* Set the CRYP peripheral in AES ECB decryption mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);\r\n    \r\n    /* Flush FIFO */\r\n    __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n     /* Set the phase */\r\n     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n     \r\n    /* Set the input and output addresses and start DMA transfer */ \r\n    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n    \r\n     /* Process Unlocked */\r\n     __HAL_UNLOCK(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES CBC encryption mode using DMA.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 16 bytes\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pCypherData;\r\n    outputaddr = (uint32_t)pPlainData;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {\r\n      /* Set the key */\r\n      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES Key mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);\r\n      \r\n      /* Enable CRYP */\r\n      __HAL_CRYP_ENABLE(hcryp);\r\n      \r\n      /* Get tick */\r\n      tickstart = HAL_GetTick();\r\n\r\n      while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))\r\n      {\r\n        /* Check for the Timeout */\r\n        if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n          \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n      \r\n      /* Reset the ALGOMODE bits*/\r\n      CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);\r\n      \r\n      /* Set the CRYP peripheral in AES CBC decryption mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);\r\n      \r\n      /* Set the Initialization Vector */\r\n      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n      /* Set the phase */\r\n      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n    \r\n    /* Set the input and output addresses and start DMA transfer */ \r\n    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES CTR decryption mode using DMA.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 16\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{  \r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pCypherData;\r\n    outputaddr = (uint32_t)pPlainData;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {\r\n      /* Set the key */\r\n      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES CTR mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);\r\n      \r\n      /* Set the Initialization Vector */\r\n      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n      /* Set the phase */\r\n      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n    \r\n    /* Set the input and output addresses and start DMA transfer */ \r\n    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup CRYP_Exported_Functions_Group3 DES processing functions \r\n *  @brief   processing functions. \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                      ##### DES processing functions #####\r\n  ==============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Encrypt plaintext using DES using ECB or CBC chaining modes\r\n      (+) Decrypt cyphertext using ECB or CBC chaining modes\r\n    [..]  Three processing functions are available:\r\n      (+) Polling mode\r\n      (+) Interrupt mode\r\n      (+) DMA mode\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in DES ECB encryption mode.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Timeout Specify Timeout value  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Set CRYP peripheral in DES ECB encryption mode */\r\n  CRYP_SetDESECBMode(hcryp, 0);\r\n  \r\n  /* Enable CRYP */\r\n  __HAL_CRYP_ENABLE(hcryp);\r\n  \r\n  /* Write Plain Data and Get Cypher Data */\r\n  if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r\n  {\r\n    return HAL_TIMEOUT;\r\n  }\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in DES ECB decryption mode.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Timeout Specify Timeout value  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Set CRYP peripheral in DES ECB decryption mode */\r\n  CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);\r\n  \r\n  /* Enable CRYP */\r\n  __HAL_CRYP_ENABLE(hcryp);\r\n  \r\n  /* Write Plain Data and Get Cypher Data */\r\n  if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)\r\n  {\r\n    return HAL_TIMEOUT;\r\n  }\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in DES CBC encryption mode.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Timeout Specify Timeout value  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Set CRYP peripheral in DES CBC encryption mode */\r\n  CRYP_SetDESCBCMode(hcryp, 0);\r\n  \r\n  /* Enable CRYP */\r\n  __HAL_CRYP_ENABLE(hcryp);\r\n  \r\n  /* Write Plain Data and Get Cypher Data */\r\n  if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r\n  {\r\n    return HAL_TIMEOUT;\r\n  }\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in DES ECB decryption mode.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Timeout Specify Timeout value  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Set CRYP peripheral in DES CBC decryption mode */\r\n  CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);\r\n  \r\n  /* Enable CRYP */\r\n  __HAL_CRYP_ENABLE(hcryp);\r\n  \r\n  /* Write Plain Data and Get Cypher Data */\r\n  if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)\r\n  {\r\n    return HAL_TIMEOUT;\r\n  }\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in DES ECB encryption mode using IT.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pPlainData;\r\n    hcryp->pCrypOutBuffPtr = pCypherData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Set CRYP peripheral in DES ECB encryption mode */\r\n    CRYP_SetDESECBMode(hcryp, 0);\r\n    \r\n    /* Enable Interrupts */\r\n    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    \r\n    hcryp->pCrypInBuffPtr += 8;\r\n    hcryp->CrypInCount -= 8;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call the Input data transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    \r\n    hcryp->pCrypOutBuffPtr += 8;\r\n    hcryp->CrypOutCount -= 8;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      /* Disable IT */\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Disable CRYP */\r\n      __HAL_CRYP_DISABLE(hcryp);\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in DES CBC encryption mode using interrupt.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pPlainData;\r\n    hcryp->pCrypOutBuffPtr = pCypherData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Set CRYP peripheral in DES CBC encryption mode */\r\n    CRYP_SetDESCBCMode(hcryp, 0);\r\n    \r\n    /* Enable Interrupts */\r\n    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  \r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n\r\n    hcryp->pCrypInBuffPtr += 8;\r\n    hcryp->CrypInCount -= 8;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call the Input data transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n\r\n    hcryp->pCrypOutBuffPtr += 8;\r\n    hcryp->CrypOutCount -= 8;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      /* Disable IT */\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Disable CRYP */\r\n      __HAL_CRYP_DISABLE(hcryp);\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in DES ECB decryption mode using IT.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pCypherData;\r\n    hcryp->pCrypOutBuffPtr = pPlainData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Set CRYP peripheral in DES ECB decryption mode */\r\n    CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);\r\n    \r\n    /* Enable Interrupts */\r\n    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    \r\n    hcryp->pCrypInBuffPtr += 8;\r\n    hcryp->CrypInCount -= 8;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call the Input data transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n\r\n    hcryp->pCrypOutBuffPtr += 8;\r\n    hcryp->CrypOutCount -= 8;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      /* Disable IT */\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Disable CRYP */\r\n      __HAL_CRYP_DISABLE(hcryp);\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in DES ECB decryption mode using interrupt.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pCypherData;\r\n    hcryp->pCrypOutBuffPtr = pPlainData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Set CRYP peripheral in DES CBC decryption mode */\r\n    CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);\r\n    \r\n    /* Enable Interrupts */\r\n    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n\r\n    hcryp->pCrypInBuffPtr += 8;\r\n    hcryp->CrypInCount -= 8;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call the Input data transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n\r\n    hcryp->pCrypOutBuffPtr += 8;\r\n    hcryp->CrypOutCount -= 8;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      /* Disable IT */\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Disable CRYP */\r\n      __HAL_CRYP_DISABLE(hcryp);\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in DES ECB encryption mode using DMA.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pPlainData;\r\n    outputaddr = (uint32_t)pCypherData;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Set CRYP peripheral in DES ECB encryption mode */\r\n    CRYP_SetDESECBMode(hcryp, 0);\r\n    \r\n    /* Set the input and output addresses and start DMA transfer */ \r\n    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in DES CBC encryption mode using DMA.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pPlainData;\r\n    outputaddr = (uint32_t)pCypherData;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Set CRYP peripheral in DES CBC encryption mode */\r\n    CRYP_SetDESCBCMode(hcryp, 0);\r\n    \r\n    /* Set the input and output addresses and start DMA transfer */ \r\n    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in DES ECB decryption mode using DMA.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pCypherData;\r\n    outputaddr = (uint32_t)pPlainData;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Set CRYP peripheral in DES ECB decryption mode */\r\n    CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);\r\n    \r\n    /* Set the input and output addresses and start DMA transfer */ \r\n    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in DES ECB decryption mode using DMA.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pCypherData;\r\n    outputaddr = (uint32_t)pPlainData;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Set CRYP peripheral in DES CBC decryption mode */\r\n    CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);\r\n    \r\n    /* Set the input and output addresses and start DMA transfer */ \r\n    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRYP_Exported_Functions_Group4 TDES processing functions \r\n *  @brief   processing functions. \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                      ##### TDES processing functions #####\r\n  ==============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Encrypt plaintext using TDES based on ECB or CBC chaining modes\r\n      (+) Decrypt cyphertext using TDES based on ECB or CBC chaining modes\r\n    [..]  Three processing functions are available:\r\n      (+) Polling mode\r\n      (+) Interrupt mode\r\n      (+) DMA mode\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in TDES ECB encryption mode\r\n  *         then encrypt pPlainData. The cypher data are available in pCypherData\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Timeout Specify Timeout value  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Set CRYP peripheral in TDES ECB encryption mode */\r\n  CRYP_SetTDESECBMode(hcryp, 0);\r\n  \r\n  /* Enable CRYP */\r\n  __HAL_CRYP_ENABLE(hcryp);\r\n  \r\n  /* Write Plain Data and Get Cypher Data */\r\n  if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r\n  {\r\n    return HAL_TIMEOUT;\r\n  }\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in TDES ECB decryption mode\r\n  *         then decrypted pCypherData. The cypher data are available in pPlainData\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Timeout Specify Timeout value  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r\n{  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Set CRYP peripheral in TDES ECB decryption mode */\r\n  CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);\r\n  \r\n  /* Enable CRYP */\r\n  __HAL_CRYP_ENABLE(hcryp);\r\n  \r\n  /* Write Cypher Data and Get Plain Data */\r\n  if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)\r\n  {\r\n    return HAL_TIMEOUT;\r\n  }\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in TDES CBC encryption mode\r\n  *         then encrypt pPlainData. The cypher data are available in pCypherData\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Timeout Specify Timeout value  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Set CRYP peripheral in TDES CBC encryption mode */\r\n  CRYP_SetTDESCBCMode(hcryp, 0);\r\n  \r\n  /* Enable CRYP */\r\n  __HAL_CRYP_ENABLE(hcryp);\r\n  \r\n  /* Write Plain Data and Get Cypher Data */\r\n  if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r\n  {\r\n    return HAL_TIMEOUT;\r\n  }\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in TDES CBC decryption mode\r\n  *         then decrypted pCypherData. The cypher data are available in pPlainData\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Timeout Specify Timeout value  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Set CRYP peripheral in TDES CBC decryption mode */\r\n  CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);\r\n  \r\n  /* Enable CRYP */\r\n  __HAL_CRYP_ENABLE(hcryp);\r\n  \r\n  /* Write Cypher Data and Get Plain Data */\r\n  if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)\r\n  {\r\n    return HAL_TIMEOUT;\r\n  }\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in TDES ECB encryption mode using interrupt.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pPlainData;\r\n    hcryp->pCrypOutBuffPtr = pCypherData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Set CRYP peripheral in TDES ECB encryption mode */\r\n    CRYP_SetTDESECBMode(hcryp, 0);\r\n    \r\n    /* Enable Interrupts */\r\n    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n\r\n    hcryp->pCrypInBuffPtr += 8;\r\n    hcryp->CrypInCount -= 8;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call the Input data transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n\r\n    hcryp->pCrypOutBuffPtr += 8;\r\n    hcryp->CrypOutCount -= 8;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      /* Disable IT */\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Disable CRYP */\r\n      __HAL_CRYP_DISABLE(hcryp);\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call the Output data transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in TDES CBC encryption mode.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pPlainData;\r\n    hcryp->pCrypOutBuffPtr = pCypherData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Set CRYP peripheral in TDES CBC encryption mode */\r\n    CRYP_SetTDESCBCMode(hcryp, 0);\r\n    \r\n    /* Enable Interrupts */\r\n    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n\r\n    hcryp->pCrypInBuffPtr += 8;\r\n    hcryp->CrypInCount -= 8;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call the Input data transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n        \r\n    hcryp->pCrypOutBuffPtr += 8;\r\n    hcryp->CrypOutCount -= 8;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Disable CRYP */\r\n      __HAL_CRYP_DISABLE(hcryp);\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in TDES ECB decryption mode.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pCypherData;\r\n    hcryp->pCrypOutBuffPtr = pPlainData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Set CRYP peripheral in TDES ECB decryption mode */\r\n    CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);\r\n    \r\n    /* Enable Interrupts */\r\n    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n\r\n    hcryp->pCrypInBuffPtr += 8;\r\n    hcryp->CrypInCount -= 8;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call the Input data transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n\r\n    hcryp->pCrypOutBuffPtr += 8;\r\n    hcryp->CrypOutCount -= 8;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Disable CRYP */\r\n      __HAL_CRYP_DISABLE(hcryp);\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n} \r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in TDES CBC decryption mode.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pCypherData;\r\n    hcryp->pCrypOutBuffPtr = pPlainData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Set CRYP peripheral in TDES CBC decryption mode */\r\n    CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);\r\n    \r\n    /* Enable Interrupts */\r\n    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n\r\n    hcryp->pCrypInBuffPtr += 8;\r\n    hcryp->CrypInCount -= 8;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call the Input data transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n\r\n    hcryp->pCrypOutBuffPtr += 8;\r\n    hcryp->CrypOutCount -= 8;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Disable CRYP */\r\n      __HAL_CRYP_DISABLE(hcryp);\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in TDES ECB encryption mode using DMA.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pPlainData;\r\n    outputaddr = (uint32_t)pCypherData;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Set CRYP peripheral in TDES ECB encryption mode */\r\n    CRYP_SetTDESECBMode(hcryp, 0);\r\n    \r\n    /* Set the input and output addresses and start DMA transfer */ \r\n    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in TDES CBC encryption mode using DMA.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pPlainData;\r\n    outputaddr = (uint32_t)pCypherData;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Set CRYP peripheral in TDES CBC encryption mode */\r\n    CRYP_SetTDESCBCMode(hcryp, 0);\r\n    \r\n    /* Set the input and output addresses and start DMA transfer */ \r\n    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in TDES ECB decryption mode using DMA.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pCypherData;\r\n    outputaddr = (uint32_t)pPlainData;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Set CRYP peripheral in TDES ECB decryption mode */\r\n    CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);\r\n    \r\n    /* Set the input and output addresses and start DMA transfer */ \r\n    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in TDES CBC decryption mode using DMA.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pCypherData;\r\n    outputaddr = (uint32_t)pPlainData;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Set CRYP peripheral in TDES CBC decryption mode */\r\n    CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);\r\n    \r\n    /* Set the input and output addresses and start DMA transfer */ \r\n    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRYP_Exported_Functions_Group5 DMA callback functions \r\n *  @brief   DMA callback functions. \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                      ##### DMA callback functions  #####\r\n  ==============================================================================  \r\n    [..]  This section provides DMA callback functions:\r\n      (+) DMA Input data transfer complete\r\n      (+) DMA Output data transfer complete\r\n      (+) DMA error\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Input FIFO transfer completed callbacks.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @retval None\r\n  */\r\n__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcryp);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_CRYP_InCpltCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  Output FIFO transfer completed callbacks.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @retval None\r\n  */\r\n__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcryp);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_CRYP_OutCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  CRYP error callbacks.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @retval None\r\n  */\r\n __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcryp);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_CRYP_ErrorCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRYP_Exported_Functions_Group6 CRYP IRQ handler management  \r\n *  @brief   CRYP IRQ handler.\r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                ##### CRYP IRQ handler management #####\r\n  ==============================================================================  \r\n[..]  This section provides CRYP IRQ handler function.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  This function handles CRYP interrupt request.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @retval None\r\n  */\r\nvoid HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)\r\n{\r\n  switch(CRYP->CR & CRYP_CR_ALGOMODE_DIRECTION)\r\n  {\r\n  case CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT:\r\n    HAL_CRYP_TDESECB_Encrypt_IT(hcryp, NULL, 0, NULL);\r\n    break;\r\n    \r\n  case CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT:\r\n    HAL_CRYP_TDESECB_Decrypt_IT(hcryp, NULL, 0, NULL);\r\n    break;\r\n    \r\n  case CRYP_CR_ALGOMODE_TDES_CBC_ENCRYPT:\r\n    HAL_CRYP_TDESCBC_Encrypt_IT(hcryp, NULL, 0, NULL);\r\n    break;\r\n    \r\n  case CRYP_CR_ALGOMODE_TDES_CBC_DECRYPT:\r\n    HAL_CRYP_TDESCBC_Decrypt_IT(hcryp, NULL, 0, NULL);\r\n    break;\r\n    \r\n  case CRYP_CR_ALGOMODE_DES_ECB_ENCRYPT:\r\n    HAL_CRYP_DESECB_Encrypt_IT(hcryp, NULL, 0, NULL);\r\n    break;\r\n    \r\n  case CRYP_CR_ALGOMODE_DES_ECB_DECRYPT:\r\n    HAL_CRYP_DESECB_Decrypt_IT(hcryp, NULL, 0, NULL);\r\n    break;\r\n    \r\n  case CRYP_CR_ALGOMODE_DES_CBC_ENCRYPT:\r\n    HAL_CRYP_DESCBC_Encrypt_IT(hcryp, NULL, 0, NULL);\r\n    break;\r\n    \r\n  case CRYP_CR_ALGOMODE_DES_CBC_DECRYPT:\r\n    HAL_CRYP_DESCBC_Decrypt_IT(hcryp, NULL, 0, NULL);\r\n    break;\r\n    \r\n  case CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT:\r\n    HAL_CRYP_AESECB_Encrypt_IT(hcryp, NULL, 0, NULL);\r\n    break;\r\n    \r\n  case CRYP_CR_ALGOMODE_AES_ECB_DECRYPT:\r\n    HAL_CRYP_AESECB_Decrypt_IT(hcryp, NULL, 0, NULL);\r\n    break;\r\n    \r\n  case CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT:\r\n    HAL_CRYP_AESCBC_Encrypt_IT(hcryp, NULL, 0, NULL);\r\n    break;\r\n    \r\n  case CRYP_CR_ALGOMODE_AES_CBC_DECRYPT:\r\n    HAL_CRYP_AESCBC_Decrypt_IT(hcryp, NULL, 0, NULL);\r\n    break;\r\n    \r\n  case CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT:\r\n    HAL_CRYP_AESCTR_Encrypt_IT(hcryp, NULL, 0, NULL);       \r\n    break;\r\n    \r\n  case CRYP_CR_ALGOMODE_AES_CTR_DECRYPT:\r\n    HAL_CRYP_AESCTR_Decrypt_IT(hcryp, NULL, 0, NULL);        \r\n    break;\r\n    \r\n  default:\r\n    break;\r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRYP_Exported_Functions_Group7 Peripheral State functions \r\n *  @brief   Peripheral State functions. \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                      ##### Peripheral State functions #####\r\n  ==============================================================================  \r\n    [..]\r\n    This subsection permits to get in run-time the status of the peripheral.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Returns the CRYP state.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @retval HAL state\r\n  */\r\nHAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)\r\n{\r\n  return hcryp->State;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n#endif /* CRYP */\r\n  \r\n#if defined (AES)\r\n\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup AES AES\r\n  * @brief AES HAL module driver.\r\n  * @{\r\n  */\r\n\r\n\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private functions --------------------------------------------------------*/\r\n\r\n/** @defgroup CRYP_Private_Functions CRYP Private Functions\r\n  * @{\r\n  */\r\n\r\nstatic HAL_StatusTypeDef CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp);\r\nstatic HAL_StatusTypeDef CRYP_SetKey(CRYP_HandleTypeDef *hcryp);\r\nstatic HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup CRYP_Exported_Functions CRYP Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CRYP_Exported_Functions_Group1 Initialization and deinitialization functions \r\n *  @brief    Initialization and Configuration functions. \r\n *\r\n@verbatim    \r\n  ==============================================================================\r\n              ##### Initialization and deinitialization functions #####\r\n  ==============================================================================\r\n    [..]  This section provides functions allowing to:\r\n      (+) Initialize the CRYP according to the specified parameters \r\n          in the CRYP_InitTypeDef and creates the associated handle\r\n      (+) DeInitialize the CRYP peripheral\r\n      (+) Initialize the CRYP MSP (MCU Specific Package)\r\n      (+) De-Initialize the CRYP MSP\r\n      \r\n    [..]\r\n    (@) Specific care must be taken to format the key and the Initialization Vector IV!\r\n    \r\n   [..] If the key is defined as a 128-bit long array key[127..0] = {b127 ... b0} where \r\n        b127 is the MSB and b0 the LSB, the key must be stored in MCU memory \r\n        (+) as a sequence of words where the MSB word comes first (occupies the\r\n          lowest memory address) \r\n        (+) where each word is byte-swapped:\r\n         (++)   address n+0 : 0b b103 .. b96 b111 .. b104 b119 .. b112 b127 .. b120\r\n         (++)   address n+4 : 0b b71 .. b64 b79 .. b72 b87 .. b80 b95 .. b88\r\n         (++)   address n+8 : 0b b39 .. b32 b47 .. b40 b55 .. b48 b63 .. b56\r\n         (++)   address n+C : 0b b7 .. b0 b15 .. b8 b23 .. b16 b31 .. b24                 \r\n    [..] Hereafter, another illustration when considering a 128-bit long key made of 16 bytes {B15..B0}.\r\n        The 4 32-bit words that make the key must be stored as follows in MCU memory:  \r\n         (+)    address n+0 : 0x B12 B13 B14 B15\r\n         (+)    address n+4 : 0x B8 B9 B10 B11\r\n         (+)    address n+8 : 0x B4 B5 B6 B7\r\n         (+)    address n+C : 0x B0 B1 B2 B3  \r\n    [..]  which leads to the expected setting  \r\n      (+)       AES_KEYR3 = 0x B15 B14 B13 B12   \r\n      (+)       AES_KEYR2 = 0x B11 B10 B9 B8      \r\n      (+)       AES_KEYR1 = 0x B7 B6 B5 B4        \r\n      (+)       AES_KEYR0 = 0x B3 B2 B1 B0      \r\n   \r\n   [..]  Same format must be applied for a 256-bit long key made of 32 bytes {B31..B0}. \r\n         The 8 32-bit words that make the key must be stored as follows in MCU memory:\r\n         (+)    address n+00 : 0x B28 B29 B30 B31\r\n         (+)    address n+04 : 0x B24 B25 B26 B27\r\n         (+)    address n+08 : 0x B20 B21 B22 B23\r\n         (+)    address n+0C : 0x B16 B17 B18 B19            \r\n         (+)    address n+10 : 0x B12 B13 B14 B15\r\n         (+)    address n+14 : 0x B8 B9 B10 B11\r\n         (+)    address n+18 : 0x B4 B5 B6 B7\r\n         (+)    address n+1C : 0x B0 B1 B2 B3 \r\n    [..]  which leads to the expected setting \r\n      (+)       AES_KEYR7 = 0x B31 B30 B29 B28   \r\n      (+)       AES_KEYR6 = 0x B27 B26 B25 B24      \r\n      (+)       AES_KEYR5 = 0x B23 B22 B21 B20        \r\n      (+)       AES_KEYR4 = 0x B19 B18 B17 B16       \r\n      (+)       AES_KEYR3 = 0x B15 B14 B13 B12   \r\n      (+)       AES_KEYR2 = 0x B11 B10 B9 B8      \r\n      (+)       AES_KEYR1 = 0x B7 B6 B5 B4        \r\n      (+)       AES_KEYR0 = 0x B3 B2 B1 B0           \r\n   \r\n   [..] Initialization Vector IV (4 32-bit words) format must follow the same as \r\n        that of a 128-bit long key.   \r\n  \r\n  [..]                 \r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initialize the CRYP according to the specified\r\n  *         parameters in the CRYP_InitTypeDef and initialize the associated handle.                   \r\n  * @note Specific care must be taken to format the key and the Initialization Vector IV \r\n  *       stored in the MCU memory before calling HAL_CRYP_Init(). Refer to explanations \r\n  *       hereabove.              \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)\r\n{   \r\n  /* Check the CRYP handle allocation */\r\n  if(hcryp == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Check the instance */\r\n  assert_param(IS_AES_ALL_INSTANCE(hcryp->Instance));\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));\r\n  assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));\r\n  assert_param(IS_CRYP_ALGOMODE(hcryp->Init.OperatingMode));\r\n  /* ChainingMode parameter is irrelevant when mode is set to Key derivation */\r\n  if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION)\r\n  {\r\n    assert_param(IS_CRYP_CHAINMODE(hcryp->Init.ChainingMode));\r\n  }\r\n  assert_param(IS_CRYP_WRITE(hcryp->Init.KeyWriteFlag));\r\n  \r\n  /*========================================================*/\r\n  /* Check the proper operating/chaining modes combinations */\r\n  /*========================================================*/  \r\n  /* Check the proper chaining when the operating mode is key derivation and decryption */\r\n#if defined(AES_CR_NPBLB)\r\n  if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION_DECRYPT) &&\\\r\n         ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CTR)           \\\r\n       || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)      \\\r\n       || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC)))\r\n#else  \r\n  if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION_DECRYPT) &&\\\r\n         ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CTR)           \\\r\n       || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)      \\\r\n       || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)))\r\n#endif               \r\n  {\r\n    return HAL_ERROR;\r\n  }  \r\n  /* Check that key derivation is not set in CMAC mode or CCM mode when applicable */  \r\n#if defined(AES_CR_NPBLB)\r\n  if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION) \r\n   && (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC))\r\n#else  \r\n  if ((hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION) \r\n   && (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC))\r\n#endif           \r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  \r\n  /*================*/\r\n  /* Initialization */\r\n  /*================*/  \r\n  /* Initialization start */\r\n  if(hcryp->State == HAL_CRYP_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    hcryp->Lock = HAL_UNLOCKED;\r\n\r\n    /* Init the low level hardware */\r\n    HAL_CRYP_MspInit(hcryp);\r\n  }\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;  \r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_CRYP_DISABLE();\r\n  \r\n  /*=============================================================*/\r\n  /* AES initialization common to all operating modes            */ \r\n  /*=============================================================*/\r\n  /* Set the Key size selection */\r\n  MODIFY_REG(hcryp->Instance->CR, AES_CR_KEYSIZE, hcryp->Init.KeySize);\r\n  \r\n  /* Set the default CRYP phase when this parameter is not used.\r\n     Phase is updated below in case of GCM/GMAC/CMAC(/CCM) setting. */\r\n  hcryp->Phase = HAL_CRYP_PHASE_NOT_USED;\r\n  \r\n  \r\n\r\n  /*=============================================================*/\r\n  /* Carry on the initialization based on the AES operating mode */ \r\n  /*=============================================================*/\r\n  /* Key derivation */ \r\n  if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)\r\n  {\r\n    MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_ALGOMODE_KEYDERIVATION);\r\n    \r\n    /* Configure the Key registers */\r\n    if (CRYP_SetKey(hcryp) != HAL_OK)\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n  }\r\n  else\r\n  /* Encryption / Decryption (with or without key derivation) / authentication */\r\n  {    \r\n    /* Set data type, operating and chaining modes.\r\n       In case of GCM or GMAC, data type is forced to 0b00 */\r\n    if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)\r\n    {\r\n      MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_MODE|AES_CR_CHMOD, hcryp->Init.OperatingMode|hcryp->Init.ChainingMode);\r\n    }\r\n    else\r\n    {\r\n      MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_MODE|AES_CR_CHMOD, hcryp->Init.DataType|hcryp->Init.OperatingMode|hcryp->Init.ChainingMode);\r\n    }\r\n\r\n    \r\n   /* Specify the encryption/decryption phase in case of Galois counter mode (GCM), \r\n      Galois message authentication code (GMAC), cipher message authentication code (CMAC) \r\n      or Counter with Cipher Mode (CCM) when applicable */\r\n#if defined(AES_CR_NPBLB)      \r\n   if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)\r\n    || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC))\r\n#else\r\n   if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)\r\n    || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC))\r\n#endif    \r\n    {\r\n      MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, hcryp->Init.GCMCMACPhase);\r\n      hcryp->Phase = HAL_CRYP_PHASE_START;\r\n    }\r\n\r\n    \r\n    /* Configure the Key registers if no need to bypass this step */\r\n    if (hcryp->Init.KeyWriteFlag == CRYP_KEY_WRITE_ENABLE)\r\n    {\r\n      if (CRYP_SetKey(hcryp) != HAL_OK)\r\n      {\r\n        return HAL_ERROR;\r\n      }      \r\n    }\r\n    \r\n    /* If applicable, configure the Initialization Vector */\r\n    if (hcryp->Init.ChainingMode != CRYP_CHAINMODE_AES_ECB)\r\n    {\r\n      if (CRYP_SetInitVector(hcryp) != HAL_OK)\r\n      {\r\n        return HAL_ERROR;\r\n      }\r\n    }\r\n  }\r\n  \r\n#if defined(AES_CR_NPBLB)   \r\n  /* Clear NPBLB field */\r\n  CLEAR_BIT(hcryp->Instance->CR, AES_CR_NPBLB);\r\n#endif  \r\n\r\n  /* Reset CrypInCount and CrypOutCount */\r\n  hcryp->CrypInCount = 0;\r\n  hcryp->CrypOutCount = 0;\r\n  \r\n  /* Reset ErrorCode field */\r\n  hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;\r\n  \r\n  /* Reset Mode suspension request */\r\n  hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_CRYP_ENABLE();\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  DeInitialize the CRYP peripheral. \r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)\r\n{\r\n  /* Check the CRYP handle allocation */\r\n  if(hcryp == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Set the default CRYP phase */\r\n  hcryp->Phase = HAL_CRYP_PHASE_READY;\r\n  \r\n  /* Reset CrypInCount and CrypOutCount */\r\n  hcryp->CrypInCount = 0;\r\n  hcryp->CrypOutCount = 0;\r\n  \r\n  /* Disable the CRYP Peripheral Clock */\r\n  __HAL_CRYP_DISABLE();\r\n  \r\n  /* DeInit the low level hardware: CLOCK, NVIC.*/\r\n  HAL_CRYP_MspDeInit(hcryp);\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_RESET;\r\n  \r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initialize the CRYP MSP.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @retval None\r\n  */\r\n__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcryp);\r\n\r\n  /* NOTE : This function should not be modified; when the callback is needed,\r\n            the HAL_CRYP_MspInit can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DeInitialize CRYP MSP.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @retval None\r\n  */\r\n__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcryp);\r\n\r\n  /* NOTE : This function should not be modified; when the callback is needed,\r\n            the HAL_CRYP_MspDeInit can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRYP_Exported_Functions_Group2 AES processing functions \r\n *  @brief   Processing functions. \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                      ##### AES processing functions #####\r\n  ==============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Encrypt plaintext using AES algorithm in different chaining modes\r\n      (+) Decrypt cyphertext using AES algorithm in different chaining modes\r\n    [..]  Three processing functions are available:\r\n      (+) Polling mode\r\n      (+) Interrupt mode\r\n      (+) DMA mode\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n  \r\n  \r\n/**\r\n  * @brief  Encrypt pPlainData in AES ECB encryption mode. The cypher data are available in pCypherData.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer in bytes, must be a multiple of 16.\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Timeout Specify Timeout value \r\n  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly\r\n  *         resort to generic HAL_CRYPEx_AES() API instead (usage recommended).      \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r\n{\r\n  /* Re-initialize AES IP with proper parameters */\r\n  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;\r\n  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;\r\n  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;\r\n  if (HAL_CRYP_Init(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  return HAL_CRYPEx_AES(hcryp, pPlainData, Size, pCypherData, Timeout);\r\n}\r\n \r\n\r\n/**\r\n  * @brief  Encrypt pPlainData in AES CBC encryption mode with key derivation. The cypher data are available in pCypherData.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer in bytes, must be a multiple of 16.\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Timeout Specify Timeout value\r\n  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly\r\n  *         resort to generic HAL_CRYPEx_AES() API instead (usage recommended).     \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r\n{ \r\n  /* Re-initialize AES IP with proper parameters */\r\n  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;\r\n  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;\r\n  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;\r\n  if (HAL_CRYP_Init(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  return HAL_CRYPEx_AES(hcryp, pPlainData, Size, pCypherData, Timeout);\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Encrypt pPlainData in AES CTR encryption mode. The cypher data are available in pCypherData\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer in bytes, must be a multiple of 16.\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Timeout Specify Timeout value \r\n  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly\r\n  *         resort to generic HAL_CRYPEx_AES() API instead (usage recommended).    \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r\n{\r\n  /* Re-initialize AES IP with proper parameters */\r\n  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;\r\n  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;\r\n  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;\r\n  if (HAL_CRYP_Init(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  return HAL_CRYPEx_AES(hcryp, pPlainData, Size, pCypherData, Timeout);\r\n}\r\n\r\n/**\r\n  * @brief  Decrypt pCypherData in AES ECB decryption mode with key derivation, \r\n  *         the decyphered data are available in pPlainData.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Size Length of the plaintext buffer in bytes, must be a multiple of 16.\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Timeout Specify Timeout value \r\n  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly\r\n  *         resort to generic HAL_CRYPEx_AES() API instead (usage recommended).   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r\n{\r\n  /* Re-initialize AES IP with proper parameters */\r\n  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;\r\n  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;\r\n  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;\r\n  if (HAL_CRYP_Init(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  return HAL_CRYPEx_AES(hcryp, pCypherData, Size, pPlainData, Timeout);\r\n}\r\n\r\n/**\r\n  * @brief  Decrypt pCypherData in AES ECB decryption mode with key derivation, \r\n  *         the decyphered data are available in pPlainData.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Size Length of the plaintext buffer in bytes, must be a multiple of 16.\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Timeout Specify Timeout value \r\n  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly\r\n  *         resort to generic HAL_CRYPEx_AES() API instead (usage recommended).    \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r\n{\r\n  /* Re-initialize AES IP with proper parameters */\r\n  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;\r\n  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;\r\n  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;\r\n  if (HAL_CRYP_Init(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  return HAL_CRYPEx_AES(hcryp, pCypherData, Size, pPlainData, Timeout);\r\n}\r\n\r\n/**\r\n  * @brief  Decrypt pCypherData in AES CTR decryption mode, \r\n  *         the decyphered data are available in pPlainData.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Size Length of the plaintext buffer in bytes, must be a multiple of 16.\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Timeout Specify Timeout value\r\n  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly\r\n  *         resort to generic HAL_CRYPEx_AES() API instead (usage recommended).     \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r\n{\r\n  /* Re-initialize AES IP with proper parameters */\r\n  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  hcryp->Init.OperatingMode = CRYP_ALGOMODE_DECRYPT;\r\n  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;\r\n  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;\r\n  if (HAL_CRYP_Init(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }  \r\n  \r\n  return HAL_CRYPEx_AES(hcryp, pCypherData, Size, pPlainData, Timeout);\r\n}\r\n\r\n/**\r\n  * @brief  Encrypt pPlainData in AES ECB encryption mode using Interrupt,\r\n  *         the cypher data are available in pCypherData.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer in bytes, must be a multiple of 16.\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly\r\n  *         resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  /* Re-initialize AES IP with proper parameters */\r\n  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;\r\n  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;\r\n  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;\r\n  if (HAL_CRYP_Init(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }  \r\n  \r\n  return HAL_CRYPEx_AES_IT(hcryp, pPlainData, Size, pCypherData);\r\n}\r\n\r\n/**\r\n  * @brief  Encrypt pPlainData in AES CBC encryption mode using Interrupt,\r\n  *         the cypher data are available in pCypherData.  \r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer in bytes, must be a multiple of 16.\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly\r\n  *         resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  /* Re-initialize AES IP with proper parameters */\r\n  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;\r\n  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;\r\n  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;\r\n  if (HAL_CRYP_Init(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  return HAL_CRYPEx_AES_IT(hcryp, pPlainData, Size, pCypherData);\r\n}\r\n  \r\n\r\n/**\r\n  * @brief  Encrypt pPlainData in AES CTR encryption mode using Interrupt,\r\n  *         the cypher data are available in pCypherData.  \r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer in bytes, must be a multiple of 16.\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly\r\n  *         resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  /* Re-initialize AES IP with proper parameters */\r\n  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;\r\n  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;\r\n  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;\r\n  if (HAL_CRYP_Init(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  return HAL_CRYPEx_AES_IT(hcryp, pPlainData, Size, pCypherData);\r\n}\r\n\r\n/**\r\n  * @brief  Decrypt pCypherData in AES ECB decryption mode using Interrupt,\r\n  *         the decyphered data are available in pPlainData.   \r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Size Length of the plaintext buffer in bytes, must be a multiple of 16.\r\n  * @param  pPlainData Pointer to the plaintext buffer.\r\n  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly\r\n  *         resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).      \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  /* Re-initialize AES IP with proper parameters */\r\n  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;\r\n  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;\r\n  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;\r\n  if (HAL_CRYP_Init(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  return HAL_CRYPEx_AES_IT(hcryp, pCypherData, Size, pPlainData);\r\n}\r\n\r\n/**\r\n  * @brief  Decrypt pCypherData in AES CBC decryption mode using Interrupt,\r\n  *         the decyphered data are available in pPlainData.  \r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Size Length of the plaintext buffer in bytes, must be a multiple of 16.\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly\r\n  *         resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  /* Re-initialize AES IP with proper parameters */\r\n  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;\r\n  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;\r\n  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;\r\n  if (HAL_CRYP_Init(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  return HAL_CRYPEx_AES_IT(hcryp, pCypherData, Size, pPlainData);\r\n}\r\n\r\n/**\r\n  * @brief  Decrypt pCypherData in AES CTR decryption mode using Interrupt,\r\n  *         the decyphered data are available in pPlainData. \r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Size Length of the plaintext buffer in bytes, must be a multiple of 16.\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly\r\n  *         resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended).    \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  /* Re-initialize AES IP with proper parameters */\r\n  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  hcryp->Init.OperatingMode = CRYP_ALGOMODE_DECRYPT;\r\n  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;\r\n  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;\r\n  if (HAL_CRYP_Init(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }  \r\n  \r\n  return HAL_CRYPEx_AES_IT(hcryp, pCypherData, Size, pPlainData);\r\n}\r\n\r\n/**\r\n  * @brief  Encrypt pPlainData in AES ECB encryption mode using DMA,\r\n  *         the cypher data are available in pCypherData.   \r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer in bytes, must be a multiple of 16.\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly\r\n  *         resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).\r\n  * @note   pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.    \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  /* Re-initialize AES IP with proper parameters */\r\n  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;\r\n  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;\r\n  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;\r\n  if (HAL_CRYP_Init(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  return HAL_CRYPEx_AES_DMA(hcryp, pPlainData, Size, pCypherData);\r\n}\r\n  \r\n \r\n\r\n/**\r\n  * @brief  Encrypt pPlainData in AES CBC encryption mode using DMA,\r\n  *         the cypher data are available in pCypherData.  \r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 16.\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly\r\n  *         resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).\r\n  * @note   pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.       \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  /* Re-initialize AES IP with proper parameters */\r\n  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;\r\n  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;\r\n  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;\r\n  if (HAL_CRYP_Init(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  return HAL_CRYPEx_AES_DMA(hcryp, pPlainData, Size, pCypherData);\r\n}\r\n\r\n/**\r\n  * @brief  Encrypt pPlainData in AES CTR encryption mode using DMA,\r\n  *         the cypher data are available in pCypherData. \r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer in bytes, must be a multiple of 16.\r\n  * @param  pCypherData Pointer to the cyphertext buffer.\r\n  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly\r\n  *         resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).\r\n  * @note   pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.      \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  /* Re-initialize AES IP with proper parameters */\r\n  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  hcryp->Init.OperatingMode = CRYP_ALGOMODE_ENCRYPT;\r\n  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;\r\n  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;\r\n  if (HAL_CRYP_Init(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  return HAL_CRYPEx_AES_DMA(hcryp, pPlainData, Size, pCypherData);\r\n}\r\n\r\n/**\r\n  * @brief  Decrypt pCypherData in AES ECB decryption mode using DMA,\r\n  *         the decyphered data are available in pPlainData.   \r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Size Length of the plaintext buffer in bytes, must be a multiple of 16.\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly\r\n  *         resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). \r\n  * @note   pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.     \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  /* Re-initialize AES IP with proper parameters */\r\n  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;\r\n  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_ECB;\r\n  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;\r\n  if (HAL_CRYP_Init(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  return HAL_CRYPEx_AES_DMA(hcryp, pCypherData, Size, pPlainData);\r\n}\r\n\r\n/**\r\n  * @brief  Decrypt pCypherData in AES CBC decryption mode using DMA,\r\n  *         the decyphered data are available in pPlainData.  \r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Size Length of the plaintext buffer in bytes, must be a multiple of 16.\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly\r\n  *         resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended).\r\n  * @note   pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.      \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  /* Re-initialize AES IP with proper parameters */\r\n  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  hcryp->Init.OperatingMode = CRYP_ALGOMODE_KEYDERIVATION_DECRYPT;\r\n  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;\r\n  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;\r\n  if (HAL_CRYP_Init(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  return HAL_CRYPEx_AES_DMA(hcryp, pCypherData, Size, pPlainData);\r\n}\r\n\r\n/**\r\n  * @brief  Decrypt pCypherData in AES CTR decryption mode using DMA,\r\n  *         the decyphered data are available in pPlainData. \r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Size Length of the plaintext buffer in bytes, must be a multiple of 16.\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @note   This API is provided only to maintain compatibility with legacy software. Users should directly\r\n  *         resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). \r\n  * @note   pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.     \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  /* Re-initialize AES IP with proper parameters */\r\n  if (HAL_CRYP_DeInit(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  hcryp->Init.OperatingMode = CRYP_ALGOMODE_DECRYPT;\r\n  hcryp->Init.ChainingMode = CRYP_CHAINMODE_AES_CTR;\r\n  hcryp->Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;\r\n  if (HAL_CRYP_Init(hcryp) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }  \r\n  \r\n  return HAL_CRYPEx_AES_DMA(hcryp, pCypherData, Size, pPlainData);\r\n}\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRYP_Exported_Functions_Group3 Callback functions \r\n *  @brief   Callback functions. \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                      ##### Callback functions  #####\r\n  ==============================================================================  \r\n    [..]  This section provides Interruption and DMA callback functions:\r\n      (+) DMA Input data transfer complete\r\n      (+) DMA Output data transfer complete\r\n      (+) DMA or Interrupt error\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  CRYP error callback.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @retval None\r\n  */\r\n__weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcryp);\r\n\r\n  /* NOTE : This function should not be modified; when the callback is needed,\r\n            the HAL_CRYP_ErrorCallback can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Input DMA transfer complete callback.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @retval None\r\n  */\r\n__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcryp);\r\n\r\n  /* NOTE : This function should not be modified; when the callback is needed,\r\n            the HAL_CRYP_InCpltCallback can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Output DMA transfer complete callback.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @retval None\r\n  */\r\n__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcryp);\r\n\r\n  /* NOTE : This function should not be modified; when the callback is needed,\r\n            the HAL_CRYP_OutCpltCallback can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRYP_Exported_Functions_Group4 CRYP IRQ handler \r\n *  @brief   AES IRQ handler.\r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                ##### AES IRQ handler management #####\r\n  ==============================================================================  \r\n[..]  This section provides AES IRQ handler function.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Handle AES interrupt request.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @retval None\r\n  */\r\nvoid HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)\r\n{\r\n  /* Check if error occurred */\r\n  if (__HAL_CRYP_GET_IT_SOURCE(CRYP_IT_ERRIE) != RESET)\r\n  {\r\n    /* If Write Error occurred */\r\n    if (__HAL_CRYP_GET_FLAG(CRYP_IT_WRERR) != RESET)\r\n    {\r\n      hcryp->ErrorCode |= HAL_CRYP_WRITE_ERROR;\r\n      hcryp->State = HAL_CRYP_STATE_ERROR;\r\n    }\r\n    /* If Read Error occurred */\r\n    if (__HAL_CRYP_GET_FLAG(CRYP_IT_RDERR) != RESET)\r\n    {\r\n      hcryp->ErrorCode |= HAL_CRYP_READ_ERROR;\r\n      hcryp->State = HAL_CRYP_STATE_ERROR;\r\n    }\r\n    \r\n    /* If an error has been reported */\r\n    if (hcryp->State == HAL_CRYP_STATE_ERROR)\r\n    {  \r\n      /* Disable Error and Computation Complete Interrupts */\r\n      __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);\r\n      /* Clear all Interrupt flags */\r\n      __HAL_CRYP_CLEAR_FLAG(CRYP_ERR_CLEAR|CRYP_CCF_CLEAR);\r\n    \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);  \r\n    \r\n      HAL_CRYP_ErrorCallback(hcryp);\r\n  \r\n      return; \r\n    }\r\n  }\r\n  \r\n  /* Check if computation complete interrupt is enabled \r\n     and if the computation complete flag is raised */\r\n  if((__HAL_CRYP_GET_FLAG(CRYP_IT_CCF) != RESET) && (__HAL_CRYP_GET_IT_SOURCE(CRYP_IT_CCFIE) != RESET))\r\n  { \r\n#if defined(AES_CR_NPBLB)\r\n    if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)\r\n     || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC))\r\n#else     \r\n    if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)\r\n     || (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC))\r\n#endif     \r\n    {\r\n     /* To ensure proper suspension requests management, CCF flag \r\n        is reset in CRYP_AES_Auth_IT() according to the current \r\n        phase under handling */\r\n      CRYP_AES_Auth_IT(hcryp);\r\n    }\r\n    else\r\n    {\r\n      /* Clear Computation Complete Flag */\r\n      __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);\r\n      CRYP_AES_IT(hcryp);\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRYP_Exported_Functions_Group5 Peripheral State functions \r\n *  @brief   Peripheral State functions. \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                      ##### Peripheral State functions #####\r\n  ==============================================================================  \r\n    [..]\r\n    This subsection permits to get in run-time the status of the peripheral.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Return the CRYP handle state.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @retval HAL state\r\n  */\r\nHAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)\r\n{\r\n  /* Return CRYP handle state */\r\n  return hcryp->State;\r\n}\r\n\r\n/**\r\n  * @brief  Return the CRYP peripheral error.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @note   The returned error is a bit-map combination of possible errors          \r\n  * @retval Error bit-map\r\n  */\r\nuint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp)\r\n{\r\n  return hcryp->ErrorCode;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup CRYP_Private_Functions\r\n  * @{\r\n  */\r\n\r\n\r\n/**\r\n  * @brief  Write the Key in KeyRx registers. \r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @retval None\r\n  */\r\nstatic HAL_StatusTypeDef  CRYP_SetKey(CRYP_HandleTypeDef *hcryp)\r\n{  \r\n  uint32_t keyaddr = 0x0;\r\n  \r\n  if ((uint32_t)(hcryp->Init.pKey == NULL))\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  \r\n  keyaddr = (uint32_t)(hcryp->Init.pKey);\r\n  \r\n  if (hcryp->Init.KeySize == CRYP_KEYSIZE_256B)\r\n  {\r\n    hcryp->Instance->KEYR7 = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->KEYR6 = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->KEYR5 = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->KEYR4 = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;      \r\n  }  \r\n  \r\n  hcryp->Instance->KEYR3 = __REV(*(uint32_t*)(keyaddr));\r\n  keyaddr+=4;\r\n  hcryp->Instance->KEYR2 = __REV(*(uint32_t*)(keyaddr));\r\n  keyaddr+=4;\r\n  hcryp->Instance->KEYR1 = __REV(*(uint32_t*)(keyaddr));\r\n  keyaddr+=4;\r\n  hcryp->Instance->KEYR0 = __REV(*(uint32_t*)(keyaddr));  \r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Write the InitVector/InitCounter in IVRx registers. \r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @retval None\r\n  */\r\nstatic HAL_StatusTypeDef CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp)\r\n{\r\n  uint32_t ivaddr = 0x0;\r\n  \r\n#if !defined(AES_CR_NPBLB)\r\n  if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)\r\n  {\r\n    hcryp->Instance->IVR3 = 0;\r\n    hcryp->Instance->IVR2 = 0;\r\n    hcryp->Instance->IVR1 = 0;        \r\n    hcryp->Instance->IVR0 = 0;\r\n  }\r\n  else\r\n#endif\r\n  {\r\n    if (hcryp->Init.pInitVect == NULL)\r\n    {\r\n      return HAL_ERROR;\r\n    } \r\n  \r\n    ivaddr = (uint32_t)(hcryp->Init.pInitVect);\r\n  \r\n    hcryp->Instance->IVR3 = __REV(*(uint32_t*)(ivaddr));\r\n    ivaddr+=4;\r\n    hcryp->Instance->IVR2 = __REV(*(uint32_t*)(ivaddr));\r\n    ivaddr+=4;\r\n    hcryp->Instance->IVR1 = __REV(*(uint32_t*)(ivaddr));\r\n    ivaddr+=4;\r\n    hcryp->Instance->IVR0 = __REV(*(uint32_t*)(ivaddr));\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n\r\n/** \r\n  * @brief  Handle CRYP block input/output data handling under interruption.\r\n  * @note   The function is called under interruption only, once\r\n  *         interruptions have been enabled by HAL_CRYPEx_AES_IT().\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module.\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)\r\n{\r\n  uint32_t inputaddr = 0;\r\n  uint32_t outputaddr = 0;  \r\n\r\n  if(hcryp->State == HAL_CRYP_STATE_BUSY)\r\n  {\r\n    if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION)\r\n    {\r\n      /* Get the output data address */\r\n      outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n      \r\n      /* Read the last available output block from the Data Output Register */\r\n      *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;\r\n      outputaddr+=4;\r\n      *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;\r\n      outputaddr+=4;\r\n      *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;\r\n      outputaddr+=4;\r\n      *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;\r\n      hcryp->pCrypOutBuffPtr += 16;\r\n      hcryp->CrypOutCount -= 16;\r\n    \r\n    }\r\n    else\r\n    {\r\n      /* Read the derived key from the Key registers */\r\n      if (hcryp->Init.KeySize == CRYP_KEYSIZE_256B)\r\n      {   \r\n        *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR7);\r\n        outputaddr+=4;\r\n        *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR6);\r\n        outputaddr+=4;\r\n        *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR5);\r\n        outputaddr+=4;\r\n        *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR4);\r\n        outputaddr+=4;\r\n      }\r\n      \r\n        *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR3);\r\n        outputaddr+=4;\r\n        *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR2);\r\n        outputaddr+=4;\r\n        *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR1);\r\n        outputaddr+=4;\r\n        *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR0);\r\n    }\r\n    \r\n    /* In case of ciphering or deciphering, check if all output text has been retrieved;\r\n       In case of key derivation, stop right there */\r\n    if ((hcryp->CrypOutCount == 0) || (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION))\r\n    {\r\n      /* Disable Computation Complete Flag and Errors Interrupts */\r\n      __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);\r\n      /* Change the CRYP state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      \r\n     /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);\r\n      \r\n      /* Call computation complete callback */\r\n      HAL_CRYPEx_ComputationCpltCallback(hcryp);\r\n      \r\n      return HAL_OK;\r\n    }\r\n    /* If suspension flag has been raised, suspend processing */\r\n    else if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)\r\n    {\r\n      /* reset ModeSuspend */\r\n      hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;\r\n      \r\n      /* Disable Computation Complete Flag and Errors Interrupts */\r\n      __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);\r\n      /* Change the CRYP state */\r\n      hcryp->State = HAL_CRYP_STATE_SUSPENDED;\r\n      \r\n     /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);\r\n      \r\n      return HAL_OK;\r\n    }\r\n    else /* Process the rest of input data */\r\n    {\r\n      /* Get the Intput data address */\r\n      inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n      \r\n      /* Increment/decrement instance pointer/counter */\r\n      hcryp->pCrypInBuffPtr += 16;\r\n      hcryp->CrypInCount -= 16;\r\n      \r\n      /* Write the next input block in the Data Input register */\r\n      hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n      inputaddr+=4;\r\n      hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n      inputaddr+=4;\r\n      hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);\r\n      inputaddr+=4;\r\n      hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n      \r\n      return HAL_OK;      \r\n    }\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY; \r\n  }\r\n}\r\n        \r\n\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* AES */\r\n\r\n#endif /* HAL_CRYP_MODULE_ENABLED */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cryp_ex.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_cryp_ex.c\r\n  * @author  MCD Application Team\r\n  * @brief   Extended CRYP HAL module driver\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of CRYP extension peripheral:\r\n  *           + Extended AES processing functions     \r\n  *  \r\n  @verbatim\r\n  ==============================================================================\r\n                     ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]\r\n    The CRYP Extension HAL driver can be used as follows:\r\n    (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():\r\n        (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()\r\n        (##) In case of using interrupts (e.g. HAL_CRYPEx_AESGCM_Encrypt_IT())\r\n            (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()\r\n            (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()\r\n            (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()\r\n        (##) In case of using DMA to control data transfer (e.g. HAL_AES_ECB_Encrypt_DMA())\r\n            (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()\r\n            (+++) Configure and enable two DMA streams one for managing data transfer from\r\n                memory to peripheral (input stream) and another stream for managing data\r\n                transfer from peripheral to memory (output stream)\r\n            (+++) Associate the initialized DMA handle to the CRYP DMA handle\r\n                using  __HAL_LINKDMA()\r\n            (+++) Configure the priority and enable the NVIC for the transfer complete\r\n                interrupt on the two DMA Streams. The output stream should have higher\r\n                priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()\r\n    (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:\r\n        (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit\r\n        (##) The key size: 128, 192 and 256. This parameter is relevant only for AES\r\n        (##) The encryption/decryption key. Its size depends on the algorithm\r\n                used for encryption/decryption\r\n        (##) The initialization vector (counter). It is not used ECB mode.\r\n    (#)Three processing (encryption/decryption) functions are available:\r\n        (##) Polling mode: encryption and decryption APIs are blocking functions\r\n             i.e. they process the data and wait till the processing is finished\r\n             e.g. HAL_CRYPEx_AESGCM_Encrypt()\r\n        (##) Interrupt mode: encryption and decryption APIs are not blocking functions\r\n                i.e. they process the data under interrupt\r\n                e.g. HAL_CRYPEx_AESGCM_Encrypt_IT()\r\n        (##) DMA mode: encryption and decryption APIs are not blocking functions\r\n                i.e. the data transfer is ensured by DMA\r\n                e.g. HAL_CRYPEx_AESGCM_Encrypt_DMA()\r\n    (#)When the processing function is called at first time after HAL_CRYP_Init()\r\n       the CRYP peripheral is initialized and processes the buffer in input.\r\n       At second call, the processing function performs an append of the already\r\n       processed buffer.\r\n       When a new data block is to be processed, call HAL_CRYP_Init() then the\r\n       processing function.\r\n    (#)In AES-GCM and AES-CCM modes are an authenticated encryption algorithms\r\n       which provide authentication messages.\r\n       HAL_AES_GCM_Finish() and HAL_AES_CCM_Finish() are used to provide those\r\n       authentication messages.\r\n       Call those functions after the processing ones (polling, interrupt or DMA).\r\n       e.g. in AES-CCM mode call HAL_CRYPEx_AESCCM_Encrypt() to encrypt the plain data\r\n            then call HAL_CRYPEx_AESCCM_Finish() to get the authentication message      \r\n    -@- For CCM Encrypt/Decrypt API's, only DataType = 8-bit is supported by this version.       \r\n    -@- The HAL_CRYPEx_AESGCM_xxxx() implementation is limited to 32bits inputs data length \r\n        (Plain/Cyphertext, Header) compared with GCM standards specifications (800-38D).\r\n    (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n/** @defgroup CRYPEx CRYPEx\r\n  * @brief CRYP Extension HAL module driver.\r\n  * @{\r\n  */\r\n\r\n\r\n#ifdef HAL_CRYP_MODULE_ENABLED\r\n\r\n#if defined (CRYP)\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @addtogroup CRYPEx_Private_define\r\n  * @{\r\n  */\r\n#define CRYPEx_TIMEOUT_VALUE  1\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/** @defgroup CRYPEx_Private_Functions_prototypes  CRYP Private Functions Prototypes\r\n  * @{\r\n  */\r\nstatic void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector);\r\nstatic void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize);\r\nstatic HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout);\r\nstatic HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint32_t Timeout);\r\nstatic void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma);\r\nstatic void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma);\r\nstatic void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma);\r\nstatic void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @addtogroup CRYPEx_Private_Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  DMA CRYP Input Data process complete callback. \r\n  * @param  hdma DMA handle\r\n  * @retval None\r\n  */\r\nstatic void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma)  \r\n{\r\n  CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  \r\n  /* Disable the DMA transfer for input Fifo request by resetting the DIEN bit\r\n     in the DMACR register */\r\n  hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);\r\n  \r\n  /* Call input data transfer complete callback */\r\n  HAL_CRYP_InCpltCallback(hcryp);\r\n}\r\n\r\n/**\r\n  * @brief  DMA CRYP Output Data process complete callback.\r\n  * @param  hdma DMA handle\r\n  * @retval None\r\n  */\r\nstatic void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  \r\n  /* Disable the DMA transfer for output Fifo request by resetting the DOEN bit\r\n     in the DMACR register */\r\n  hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);\r\n  \r\n  /* Enable the CRYP peripheral */\r\n  __HAL_CRYP_DISABLE(hcryp);\r\n  \r\n  /* Change the CRYP peripheral state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Call output data transfer complete callback */\r\n  HAL_CRYP_OutCpltCallback(hcryp);\r\n}\r\n\r\n/**\r\n  * @brief  DMA CRYP communication error callback. \r\n  * @param  hdma DMA handle\r\n  * @retval None\r\n  */\r\nstatic void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma)\r\n{\r\n  CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  hcryp->State= HAL_CRYP_STATE_READY;\r\n  HAL_CRYP_ErrorCallback(hcryp);\r\n}\r\n\r\n/**\r\n  * @brief  Writes the Key in Key registers. \r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  Key Pointer to Key buffer\r\n  * @param  KeySize Size of Key\r\n  * @retval None\r\n  */\r\nstatic void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize)\r\n{\r\n  uint32_t keyaddr = (uint32_t)Key;\r\n  \r\n  switch(KeySize)\r\n  {\r\n  case CRYP_KEYSIZE_256B:\r\n    /* Key Initialisation */\r\n    hcryp->Instance->K0LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K0RR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));\r\n    break;\r\n  case CRYP_KEYSIZE_192B:\r\n    hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));\r\n    break;\r\n  case CRYP_KEYSIZE_128B:       \r\n    hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));\r\n    break;\r\n  default:\r\n    break;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Writes the InitVector/InitCounter in IV registers.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  InitVector Pointer to InitVector/InitCounter buffer\r\n  * @retval None\r\n  */\r\nstatic void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector)\r\n{\r\n  uint32_t ivaddr = (uint32_t)InitVector;\r\n  \r\n  hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));\r\n  ivaddr+=4;\r\n  hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));\r\n  ivaddr+=4;\r\n  hcryp->Instance->IV1LR = __REV(*(uint32_t*)(ivaddr));\r\n  ivaddr+=4;\r\n  hcryp->Instance->IV1RR = __REV(*(uint32_t*)(ivaddr));\r\n}\r\n\r\n/**\r\n  * @brief  Process Data: Writes Input data in polling mode and read the Output data.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  Input Pointer to the Input buffer.\r\n  * @param  Ilength Length of the Input buffer, must be a multiple of 16\r\n  * @param  Output Pointer to the returned buffer\r\n  * @param  Timeout Timeout value \r\n  * @retval None\r\n  */\r\nstatic HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  uint32_t i = 0;\r\n  uint32_t inputaddr  = (uint32_t)Input;\r\n  uint32_t outputaddr = (uint32_t)Output;\r\n  \r\n  for(i=0; (i < Ilength); i+=16)\r\n  {\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    \r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n \r\n    while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))\r\n    {\r\n      /* Check for the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n          \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n    /* Read the Output block from the OUT FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n  }\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Sets the header phase\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  Input Pointer to the Input buffer.\r\n  * @param  Ilength Length of the Input buffer, must be a multiple of 16\r\n  * @param  Timeout Timeout value   \r\n  * @retval None\r\n  */\r\nstatic HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  uint32_t loopcounter = 0;\r\n  uint32_t headeraddr = (uint32_t)Input;\r\n  \r\n  /***************************** Header phase *********************************/\r\n  if(hcryp->Init.HeaderSize != 0)\r\n  {\r\n    /* Select header phase */\r\n    __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);\r\n    /* Enable the CRYP peripheral */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    for(loopcounter = 0; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=16)\r\n    {\r\n      /* Get tick */\r\n      tickstart = HAL_GetTick();\r\n      \r\n      while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))\r\n      {\r\n        /* Check for the Timeout */\r\n        if(Timeout != HAL_MAX_DELAY)\r\n        {\r\n          if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n          {\r\n            /* Change state */\r\n            hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n            \r\n            /* Process Unlocked */\r\n            __HAL_UNLOCK(hcryp);\r\n            \r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n      }\r\n      /* Write the Input block in the IN FIFO */\r\n      hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n      headeraddr+=4;\r\n      hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n      headeraddr+=4;\r\n      hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n      headeraddr+=4;\r\n      hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n      headeraddr+=4;\r\n    }\r\n    \r\n    /* Wait until the complete message has been processed */\r\n\r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n    while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)\r\n    {\r\n      /* Check for the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n          \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n  }\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Sets the DMA configuration and start the DMA transfer.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  inputaddr Address of the Input buffer\r\n  * @param  Size Size of the Input buffer, must be a multiple of 16\r\n  * @param  outputaddr Address of the Output buffer\r\n  * @retval None\r\n  */\r\nstatic void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)\r\n{\r\n  /* Set the CRYP DMA transfer complete callback */\r\n  hcryp->hdmain->XferCpltCallback = CRYPEx_GCMCCM_DMAInCplt;\r\n  /* Set the DMA error callback */\r\n  hcryp->hdmain->XferErrorCallback = CRYPEx_GCMCCM_DMAError;\r\n  \r\n  /* Set the CRYP DMA transfer complete callback */\r\n  hcryp->hdmaout->XferCpltCallback = CRYPEx_GCMCCM_DMAOutCplt;\r\n  /* Set the DMA error callback */\r\n  hcryp->hdmaout->XferErrorCallback = CRYPEx_GCMCCM_DMAError;\r\n  \r\n  /* Enable the CRYP peripheral */\r\n  __HAL_CRYP_ENABLE(hcryp);\r\n  \r\n  /* Enable the DMA In DMA Stream */\r\n  HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DR, Size/4);\r\n  \r\n  /* Enable In DMA request */\r\n  hcryp->Instance->DMACR = CRYP_DMACR_DIEN;\r\n  \r\n  /* Enable the DMA Out DMA Stream */\r\n  HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size/4);\r\n  \r\n  /* Enable Out DMA request */\r\n  hcryp->Instance->DMACR |= CRYP_DMACR_DOEN;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions---------------------------------------------------------*/\r\n/** @addtogroup CRYPEx_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions \r\n *  @brief   Extended processing functions. \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n              ##### Extended AES processing functions #####\r\n  ==============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Encrypt plaintext using AES-128/192/256 using GCM and CCM chaining modes\r\n      (+) Decrypt cyphertext using AES-128/192/256 using GCM and CCM chaining modes\r\n      (+) Finish the processing. This function is available only for GCM and CCM\r\n    [..]  Three processing methods are available:\r\n      (+) Polling mode\r\n      (+) Interrupt mode\r\n      (+) DMA mode\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES CCM encryption mode then \r\n  *         encrypt pPlainData. The cypher data are available in pCypherData.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 16\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Timeout Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;\r\n  uint32_t headersize = hcryp->Init.HeaderSize;\r\n  uint32_t headeraddr = (uint32_t)hcryp->Init.Header;\r\n  uint32_t loopcounter = 0;\r\n  uint32_t bufferidx = 0;\r\n  uint8_t blockb0[16] = {0};/* Block B0 */\r\n  uint8_t ctr[16] = {0}; /* Counter */\r\n  uint32_t b0addr = (uint32_t)blockb0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP peripheral state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n  {\r\n    /************************ Formatting the header block *********************/\r\n    if(headersize != 0)\r\n    {\r\n      /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */\r\n      if(headersize < 65280)\r\n      {\r\n        hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);\r\n        hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);\r\n        headersize += 2;\r\n      }\r\n      else\r\n      {\r\n        /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */\r\n        hcryp->Init.pScratch[bufferidx++] = 0xFF;\r\n        hcryp->Init.pScratch[bufferidx++] = 0xFE;\r\n        hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;\r\n        hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;\r\n        hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;\r\n        hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;\r\n        headersize += 6;\r\n      }\r\n      /* Copy the header buffer in internal buffer \"hcryp->Init.pScratch\" */\r\n      for(loopcounter = 0; loopcounter < headersize; loopcounter++)\r\n      {\r\n        hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];\r\n      }\r\n      /* Check if the header size is modulo 16 */\r\n      if ((headersize % 16) != 0)\r\n      {\r\n        /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */\r\n        for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)\r\n        {\r\n          hcryp->Init.pScratch[loopcounter] = 0;\r\n        }\r\n        /* Set the header size to modulo 16 */\r\n        headersize = ((headersize/16) + 1) * 16;\r\n      }\r\n      /* Set the pointer headeraddr to hcryp->Init.pScratch */\r\n      headeraddr = (uint32_t)hcryp->Init.pScratch;\r\n    }\r\n    /*********************** Formatting the block B0 **************************/\r\n    if(headersize != 0)\r\n    {\r\n      blockb0[0] = 0x40;\r\n    }\r\n    /* Flags byte */\r\n    /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */\r\n    blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);\r\n    blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);\r\n \r\n    for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)\r\n    {\r\n      blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];\r\n    }\r\n    for ( ; loopcounter < 13; loopcounter++)\r\n    {\r\n      blockb0[loopcounter+1] = 0;\r\n    }\r\n    \r\n    blockb0[14] = (Size >> 8);\r\n    blockb0[15] = (Size & 0xFF);\r\n    \r\n    /************************* Formatting the initial counter *****************/\r\n    /* Byte 0:\r\n       Bits 7 and 6 are reserved and shall be set to 0\r\n       Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter blocks\r\n       are distinct from B0\r\n       Bits 0, 1, and 2 contain the same encoding of q as in B0\r\n    */\r\n    ctr[0] = blockb0[0] & 0x07;\r\n    /* byte 1 to NonceSize is the IV (Nonce) */\r\n    for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)\r\n    {\r\n      ctr[loopcounter] = blockb0[loopcounter];\r\n    }\r\n    /* Set the LSB to 1 */\r\n    ctr[15] |= 0x01;\r\n    \r\n    /* Set the key */\r\n    CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n    \r\n    /* Set the CRYP peripheral in AES CCM mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);\r\n    \r\n    /* Set the Initialization Vector */\r\n    CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);\r\n    \r\n    /* Select init phase */\r\n    __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);\r\n    \r\n    b0addr = (uint32_t)blockb0;\r\n    /* Write the blockb0 block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n    b0addr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n    b0addr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n    b0addr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n    \r\n    /* Enable the CRYP peripheral */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n    while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r\n    {\r\n      /* Check for the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n        \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n    /***************************** Header phase *******************************/\r\n    if(headersize != 0)\r\n    {\r\n      /* Select header phase */\r\n      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);\r\n      \r\n      /* Enable the CRYP peripheral */\r\n      __HAL_CRYP_ENABLE(hcryp);\r\n      \r\n      for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)\r\n      {\r\n        /* Get tick */\r\n        tickstart = HAL_GetTick();\r\n\r\n        while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))\r\n        {\r\n          {\r\n            /* Check for the Timeout */\r\n            if(Timeout != HAL_MAX_DELAY)\r\n            {\r\n              if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n              {\r\n                /* Change state */\r\n                hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n                \r\n                /* Process Unlocked */\r\n                __HAL_UNLOCK(hcryp);\r\n                \r\n                return HAL_TIMEOUT;\r\n              }\r\n            }\r\n          }\r\n        }\r\n        /* Write the header block in the IN FIFO */\r\n        hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n        headeraddr+=4;\r\n        hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n        headeraddr+=4;\r\n        hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n        headeraddr+=4;\r\n        hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n        headeraddr+=4;\r\n      }\r\n      \r\n      /* Get tick */\r\n      tickstart = HAL_GetTick();\r\n\r\n      while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)\r\n      {\r\n        /* Check for the Timeout */\r\n        if(Timeout != HAL_MAX_DELAY)\r\n        {\r\n          if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n          {\r\n            /* Change state */\r\n            hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n            \r\n            /* Process Unlocked */\r\n            __HAL_UNLOCK(hcryp);\r\n            \r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n      }\r\n    }\r\n    /* Save formatted counter into the scratch buffer pScratch */\r\n    for(loopcounter = 0; (loopcounter < 16); loopcounter++)\r\n    {\r\n      hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];\r\n    }\r\n    /* Reset bit 0 */\r\n    hcryp->Init.pScratch[15] &= 0xfe;\r\n    \r\n    /* Select payload phase once the header phase is performed */\r\n    __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r\n    \r\n    /* Flush FIFO */\r\n    __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n    /* Enable the CRYP peripheral */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Set the phase */\r\n    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n  }\r\n  \r\n  /* Write Plain Data and Get Cypher Data */\r\n  if(CRYPEx_GCMCCM_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r\n  {\r\n    return HAL_TIMEOUT;\r\n  }\r\n  \r\n  /* Change the CRYP peripheral state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES GCM encryption mode then \r\n  *         encrypt pPlainData. The cypher data are available in pCypherData.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 16\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Timeout Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP peripheral state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n  {\r\n    /* Set the key */\r\n    CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n    \r\n    /* Set the CRYP peripheral in AES GCM mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);\r\n    \r\n    /* Set the Initialization Vector */\r\n    CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);\r\n    \r\n    /* Flush FIFO */\r\n    __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n    /* Enable the CRYP peripheral */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n    while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r\n    {\r\n      /* Check for the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n          \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n    \r\n    /* Set the header phase */\r\n    if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, Timeout) != HAL_OK)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n    \r\n    /* Disable the CRYP peripheral */\r\n    __HAL_CRYP_DISABLE(hcryp);\r\n    \r\n    /* Select payload phase once the header phase is performed */\r\n    __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r\n    \r\n    /* Flush FIFO */\r\n    __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n    /* Enable the CRYP peripheral */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Set the phase */\r\n    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n  }\r\n  \r\n  /* Write Plain Data and Get Cypher Data */\r\n  if(CRYPEx_GCMCCM_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r\n  {\r\n    return HAL_TIMEOUT;\r\n  }\r\n  \r\n  /* Change the CRYP peripheral state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES GCM decryption mode then\r\n  *         decrypted pCypherData. The cypher data are available in pPlainData.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Size Length of the cyphertext buffer, must be a multiple of 16\r\n  * @param  pPlainData Pointer to the plaintext buffer \r\n  * @param  Timeout Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP peripheral state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n  {\r\n    /* Set the key */\r\n    CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n    \r\n    /* Set the CRYP peripheral in AES GCM decryption mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);\r\n    \r\n    /* Set the Initialization Vector */\r\n    CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);\r\n    \r\n    /* Flush FIFO */\r\n    __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n    /* Enable the CRYP peripheral */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n    while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r\n    {\r\n      /* Check for the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n          \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n    \r\n    /* Set the header phase */\r\n    if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, Timeout) != HAL_OK)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n    /* Disable the CRYP peripheral */\r\n    __HAL_CRYP_DISABLE(hcryp);\r\n    \r\n    /* Select payload phase once the header phase is performed */\r\n    __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r\n    \r\n    /* Enable the CRYP peripheral */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Set the phase */\r\n    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n  }\r\n  \r\n  /* Write Plain Data and Get Cypher Data */\r\n  if(CRYPEx_GCMCCM_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)\r\n  {\r\n    return HAL_TIMEOUT;\r\n  }\r\n  \r\n  /* Change the CRYP peripheral state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Computes the authentication TAG.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  Size Total length of the plain/cyphertext buffer\r\n  * @param  AuthTag Pointer to the authentication buffer\r\n  * @param  Timeout Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint32_t Size, uint8_t *AuthTag, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  uint64_t headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */\r\n  uint64_t inputlength = Size * 8; /* input length in bits */\r\n  uint32_t tagaddr = (uint32_t)AuthTag;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP peripheral state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hcryp->Phase == HAL_CRYP_PHASE_PROCESS)\r\n  {\r\n    /* Change the CRYP phase */\r\n    hcryp->Phase = HAL_CRYP_PHASE_FINAL;\r\n    \r\n    /* Disable CRYP to start the final phase */\r\n    __HAL_CRYP_DISABLE(hcryp);\r\n    \r\n    /* Select final phase */\r\n    __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_FINAL);\r\n    \r\n    /* Enable the CRYP peripheral */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Write the number of bits in header (64 bits) followed by the number of bits\r\n       in the payload */\r\n    if(hcryp->Init.DataType == CRYP_DATATYPE_1B)\r\n    {\r\n      hcryp->Instance->DR = __RBIT(headerlength >> 32);\r\n      hcryp->Instance->DR = __RBIT(headerlength);\r\n      hcryp->Instance->DR = __RBIT(inputlength >> 32);\r\n      hcryp->Instance->DR = __RBIT(inputlength);\r\n    }\r\n    else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)\r\n    {\r\n      hcryp->Instance->DR = __REV(headerlength >> 32);\r\n      hcryp->Instance->DR = __REV(headerlength);\r\n      hcryp->Instance->DR = __REV(inputlength >> 32);\r\n      hcryp->Instance->DR = __REV(inputlength);\r\n    }\r\n    else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)\r\n    {\r\n      hcryp->Instance->DR = __ROR((uint32_t)(headerlength >> 32), 16);\r\n      hcryp->Instance->DR = __ROR((uint32_t)headerlength, 16);\r\n      hcryp->Instance->DR = __ROR((uint32_t)(inputlength >> 32), 16);\r\n      hcryp->Instance->DR = __ROR((uint32_t)inputlength, 16);\r\n    }\r\n    else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)\r\n    {\r\n      hcryp->Instance->DR = (uint32_t)(headerlength >> 32);\r\n      hcryp->Instance->DR = (uint32_t)(headerlength);\r\n      hcryp->Instance->DR = (uint32_t)(inputlength >> 32);\r\n      hcryp->Instance->DR = (uint32_t)(inputlength);\r\n    }\r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n    while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))\r\n    {\r\n      /* Check for the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n        \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n    \r\n    /* Read the Auth TAG in the IN FIFO */\r\n    *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;\r\n    tagaddr+=4;\r\n    *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;\r\n    tagaddr+=4;\r\n    *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;\r\n    tagaddr+=4;\r\n    *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;\r\n  }\r\n  \r\n  /* Change the CRYP peripheral state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Computes the authentication TAG for AES CCM mode.\r\n  * @note   This API is called after HAL_AES_CCM_Encrypt()/HAL_AES_CCM_Decrypt()   \r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  AuthTag Pointer to the authentication buffer\r\n  * @param  Timeout Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *AuthTag, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  uint32_t tagaddr = (uint32_t)AuthTag;\r\n  uint32_t ctraddr = (uint32_t)hcryp->Init.pScratch;\r\n  uint32_t temptag[4] = {0}; /* Temporary TAG (MAC) */\r\n  uint32_t loopcounter;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP peripheral state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hcryp->Phase == HAL_CRYP_PHASE_PROCESS)\r\n  {\r\n    /* Change the CRYP phase */\r\n    hcryp->Phase = HAL_CRYP_PHASE_FINAL;\r\n    \r\n    /* Disable CRYP to start the final phase */\r\n    __HAL_CRYP_DISABLE(hcryp);\r\n    \r\n    /* Select final phase */\r\n    __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_FINAL);\r\n    \r\n    /* Enable the CRYP peripheral */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Write the counter block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)ctraddr;\r\n    ctraddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)ctraddr;\r\n    ctraddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)ctraddr;\r\n    ctraddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)ctraddr;\r\n    \r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n    while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))\r\n    {\r\n      /* Check for the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n          \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n    \r\n    /* Read the Auth TAG in the IN FIFO */\r\n    temptag[0] = hcryp->Instance->DOUT;\r\n    temptag[1] = hcryp->Instance->DOUT;\r\n    temptag[2] = hcryp->Instance->DOUT;\r\n    temptag[3] = hcryp->Instance->DOUT;\r\n  }\r\n  \r\n  /* Copy temporary authentication TAG in user TAG buffer */\r\n  for(loopcounter = 0; loopcounter < hcryp->Init.TagSize ; loopcounter++)\r\n  {\r\n    /* Set the authentication TAG buffer */\r\n    *((uint8_t*)tagaddr+loopcounter) = *((uint8_t*)temptag+loopcounter);\r\n  }\r\n  \r\n  /* Change the CRYP peripheral state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES CCM decryption mode then\r\n  *         decrypted pCypherData. The cypher data are available in pPlainData.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 16\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Timeout Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  uint32_t headersize = hcryp->Init.HeaderSize;\r\n  uint32_t headeraddr = (uint32_t)hcryp->Init.Header;\r\n  uint32_t loopcounter = 0;\r\n  uint32_t bufferidx = 0;\r\n  uint8_t blockb0[16] = {0};/* Block B0 */\r\n  uint8_t ctr[16] = {0}; /* Counter */\r\n  uint32_t b0addr = (uint32_t)blockb0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP peripheral state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n  {\r\n    /************************ Formatting the header block *********************/\r\n    if(headersize != 0)\r\n    {\r\n      /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */\r\n      if(headersize < 65280)\r\n      {\r\n        hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFFU);\r\n        hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU);\r\n        headersize += 2;\r\n      }\r\n      else\r\n      {\r\n        /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */\r\n        hcryp->Init.pScratch[bufferidx++] = 0xFFU;\r\n        hcryp->Init.pScratch[bufferidx++] = 0xFEU;\r\n        hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;\r\n        hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;\r\n        hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;\r\n        hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;\r\n        headersize += 6;\r\n      }\r\n      /* Copy the header buffer in internal buffer \"hcryp->Init.pScratch\" */\r\n      for(loopcounter = 0; loopcounter < headersize; loopcounter++)\r\n      {\r\n        hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];\r\n      }\r\n      /* Check if the header size is modulo 16 */\r\n      if ((headersize % 16) != 0)\r\n      {\r\n        /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */\r\n        for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)\r\n        {\r\n          hcryp->Init.pScratch[loopcounter] = 0;\r\n        }\r\n        /* Set the header size to modulo 16 */\r\n        headersize = ((headersize/16) + 1) * 16;\r\n      }\r\n      /* Set the pointer headeraddr to hcryp->Init.pScratch */\r\n      headeraddr = (uint32_t)hcryp->Init.pScratch;\r\n    }\r\n    /*********************** Formatting the block B0 **************************/\r\n    if(headersize != 0)\r\n    {\r\n      blockb0[0] = 0x40;\r\n    }\r\n    /* Flags byte */\r\n    /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */\r\n    blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);\r\n    blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);\r\n    \r\n    for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)\r\n    {\r\n      blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];\r\n    }\r\n    for ( ; loopcounter < 13; loopcounter++)\r\n    {\r\n      blockb0[loopcounter+1] = 0;\r\n    }\r\n    \r\n    blockb0[14] = (Size >> 8);\r\n    blockb0[15] = (Size & 0xFF);\r\n    \r\n    /************************* Formatting the initial counter *****************/\r\n    /* Byte 0:\r\n       Bits 7 and 6 are reserved and shall be set to 0\r\n       Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter \r\n       blocks are distinct from B0\r\n       Bits 0, 1, and 2 contain the same encoding of q as in B0\r\n    */\r\n    ctr[0] = blockb0[0] & 0x07;\r\n    /* byte 1 to NonceSize is the IV (Nonce) */\r\n    for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)\r\n    {\r\n      ctr[loopcounter] = blockb0[loopcounter];\r\n    }\r\n    /* Set the LSB to 1 */\r\n    ctr[15] |= 0x01;\r\n    \r\n    /* Set the key */\r\n    CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n    \r\n    /* Set the CRYP peripheral in AES CCM mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);\r\n    \r\n    /* Set the Initialization Vector */\r\n    CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);\r\n    \r\n    /* Select init phase */\r\n    __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);\r\n    \r\n    b0addr = (uint32_t)blockb0;\r\n    /* Write the blockb0 block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n    b0addr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n    b0addr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n    b0addr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n    \r\n    /* Enable the CRYP peripheral */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n \r\n    while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r\n    {\r\n      /* Check for the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n        \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n    /***************************** Header phase *******************************/\r\n    if(headersize != 0)\r\n    {\r\n      /* Select header phase */\r\n      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);\r\n      \r\n      /* Enable Crypto processor */\r\n      __HAL_CRYP_ENABLE(hcryp);\r\n      \r\n      for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)\r\n      {\r\n        /* Get tick */\r\n        tickstart = HAL_GetTick();\r\n\r\n        while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))\r\n        {\r\n          /* Check for the Timeout */\r\n          if(Timeout != HAL_MAX_DELAY)\r\n          {\r\n            if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n            {\r\n              /* Change state */\r\n              hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n              \r\n              /* Process Unlocked */\r\n              __HAL_UNLOCK(hcryp);\r\n              \r\n              return HAL_TIMEOUT;\r\n            }\r\n          }\r\n        }\r\n        /* Write the header block in the IN FIFO */\r\n        hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n        headeraddr+=4;\r\n        hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n        headeraddr+=4;\r\n        hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n        headeraddr+=4;\r\n        hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n        headeraddr+=4;\r\n      }\r\n      \r\n      /* Get tick */\r\n      tickstart = HAL_GetTick();\r\n\r\n      while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)\r\n      {\r\n      /* Check for the Timeout */\r\n        if(Timeout != HAL_MAX_DELAY)\r\n        {\r\n          if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n          {\r\n            /* Change state */\r\n            hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n            \r\n            /* Process Unlocked */\r\n            __HAL_UNLOCK(hcryp);\r\n            \r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n      }\r\n    }\r\n    /* Save formatted counter into the scratch buffer pScratch */\r\n    for(loopcounter = 0; (loopcounter < 16); loopcounter++)\r\n    {\r\n      hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];\r\n    }\r\n    /* Reset bit 0 */\r\n    hcryp->Init.pScratch[15] &= 0xfe;\r\n    /* Select payload phase once the header phase is performed */\r\n    __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r\n    \r\n    /* Flush FIFO */\r\n    __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n    /* Enable the CRYP peripheral */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Set the phase */\r\n    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n  }\r\n  \r\n  /* Write Plain Data and Get Cypher Data */\r\n  if(CRYPEx_GCMCCM_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)\r\n  {\r\n    return HAL_TIMEOUT;\r\n  }\r\n  \r\n  /* Change the CRYP peripheral state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES GCM encryption mode using IT.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 16\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    /* Get the buffer addresses and sizes */    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pPlainData;\r\n    hcryp->pCrypOutBuffPtr = pCypherData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP peripheral state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {\r\n      /* Set the key */\r\n      CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES GCM mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);\r\n      \r\n      /* Set the Initialization Vector */\r\n      CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n      /* Enable CRYP to start the init phase */\r\n      __HAL_CRYP_ENABLE(hcryp);\r\n      \r\n     /* Get tick */\r\n     tickstart = HAL_GetTick();\r\n\r\n      while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r\n      {\r\n        /* Check for the Timeout */\r\n        \r\n        if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n          \r\n          return HAL_TIMEOUT;\r\n          \r\n        }\r\n      }\r\n      \r\n      /* Set the header phase */\r\n      if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n      /* Disable the CRYP peripheral */\r\n      __HAL_CRYP_DISABLE(hcryp);\r\n      \r\n      /* Select payload phase once the header phase is performed */\r\n      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n      /* Set the phase */\r\n      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n    \r\n    if(Size != 0)\r\n    {\r\n      /* Enable Interrupts */\r\n      __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n      /* Enable the CRYP peripheral */\r\n      __HAL_CRYP_ENABLE(hcryp);\r\n    }\r\n    else\r\n    {\r\n      /* Process Locked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP state and phase */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n    }\r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    hcryp->pCrypInBuffPtr += 16;\r\n    hcryp->CrypInCount -= 16;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call the Input data transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    hcryp->pCrypOutBuffPtr += 16;\r\n    hcryp->CrypOutCount -= 16;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP peripheral state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES CCM encryption mode using interrupt.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 16\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  uint32_t headersize = hcryp->Init.HeaderSize;\r\n  uint32_t headeraddr = (uint32_t)hcryp->Init.Header;\r\n  uint32_t loopcounter = 0;\r\n  uint32_t bufferidx = 0;\r\n  uint8_t blockb0[16] = {0};/* Block B0 */\r\n  uint8_t ctr[16] = {0}; /* Counter */\r\n  uint32_t b0addr = (uint32_t)blockb0;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pPlainData;\r\n    hcryp->pCrypOutBuffPtr = pCypherData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP peripheral state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {    \r\n      /************************ Formatting the header block *******************/\r\n      if(headersize != 0)\r\n      {\r\n        /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */\r\n        if(headersize < 65280)\r\n        {\r\n          hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFFU);\r\n          hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU);\r\n          headersize += 2;\r\n        }\r\n        else\r\n        {\r\n          /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */\r\n          hcryp->Init.pScratch[bufferidx++] = 0xFFU;\r\n          hcryp->Init.pScratch[bufferidx++] = 0xFEU;\r\n          hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;\r\n          hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;\r\n          hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;\r\n          hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;\r\n          headersize += 6;\r\n        }\r\n        /* Copy the header buffer in internal buffer \"hcryp->Init.pScratch\" */\r\n        for(loopcounter = 0; loopcounter < headersize; loopcounter++)\r\n        {\r\n          hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];\r\n        }\r\n        /* Check if the header size is modulo 16 */\r\n        if ((headersize % 16) != 0)\r\n        {\r\n          /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */\r\n          for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)\r\n          {\r\n            hcryp->Init.pScratch[loopcounter] = 0;\r\n          }\r\n          /* Set the header size to modulo 16 */\r\n          headersize = ((headersize/16) + 1) * 16;\r\n        }\r\n        /* Set the pointer headeraddr to hcryp->Init.pScratch */\r\n        headeraddr = (uint32_t)hcryp->Init.pScratch;\r\n      }\r\n      /*********************** Formatting the block B0 ************************/\r\n      if(headersize != 0)\r\n      {\r\n        blockb0[0] = 0x40;\r\n      }\r\n      /* Flags byte */\r\n      /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */\r\n      blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);\r\n      blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);\r\n      \r\n      for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)\r\n      {\r\n        blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];\r\n      }\r\n      for ( ; loopcounter < 13; loopcounter++)\r\n      {\r\n        blockb0[loopcounter+1] = 0;\r\n      }\r\n      \r\n      blockb0[14] = (Size >> 8);\r\n      blockb0[15] = (Size & 0xFF);\r\n      \r\n      /************************* Formatting the initial counter ***************/\r\n      /* Byte 0:\r\n         Bits 7 and 6 are reserved and shall be set to 0\r\n         Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter \r\n         blocks are distinct from B0\r\n         Bits 0, 1, and 2 contain the same encoding of q as in B0\r\n      */\r\n      ctr[0] = blockb0[0] & 0x07;\r\n      /* byte 1 to NonceSize is the IV (Nonce) */\r\n      for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)\r\n      {\r\n        ctr[loopcounter] = blockb0[loopcounter];\r\n      }\r\n      /* Set the LSB to 1 */\r\n      ctr[15] |= 0x01;\r\n      \r\n      /* Set the key */\r\n      CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES CCM mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);\r\n      \r\n      /* Set the Initialization Vector */\r\n      CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);\r\n      \r\n      /* Select init phase */\r\n      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);\r\n      \r\n      b0addr = (uint32_t)blockb0;\r\n      /* Write the blockb0 block in the IN FIFO */\r\n      hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n      b0addr+=4;\r\n      hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n      b0addr+=4;\r\n      hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n      b0addr+=4;\r\n      hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n      \r\n      /* Enable the CRYP peripheral */\r\n      __HAL_CRYP_ENABLE(hcryp);\r\n      \r\n     /* Get tick */\r\n     tickstart = HAL_GetTick();\r\n\r\n      while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r\n      {\r\n        /* Check for the Timeout */\r\n        if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n          \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n      /***************************** Header phase *****************************/\r\n      if(headersize != 0)\r\n      {\r\n        /* Select header phase */\r\n        __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);\r\n        \r\n        /* Enable Crypto processor */\r\n        __HAL_CRYP_ENABLE(hcryp);\r\n        \r\n        for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)\r\n        {\r\n         /* Get tick */\r\n         tickstart = HAL_GetTick();\r\n\r\n          while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))\r\n          {\r\n            /* Check for the Timeout */\r\n            if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r\n            {\r\n              /* Change state */\r\n              hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n              \r\n              /* Process Unlocked */\r\n              __HAL_UNLOCK(hcryp);\r\n              \r\n              return HAL_TIMEOUT;\r\n            }\r\n          }\r\n          /* Write the header block in the IN FIFO */\r\n          hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n          headeraddr+=4;\r\n          hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n          headeraddr+=4;\r\n          hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n          headeraddr+=4;\r\n          hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n          headeraddr+=4;\r\n        }\r\n\r\n        /* Get tick */\r\n        tickstart = HAL_GetTick();\r\n\r\n        while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)\r\n        {\r\n          /* Check for the Timeout */\r\n          if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r\n          {\r\n            /* Change state */\r\n            hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n            \r\n            /* Process Unlocked */\r\n            __HAL_UNLOCK(hcryp);\r\n            \r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n      }\r\n      /* Save formatted counter into the scratch buffer pScratch */\r\n      for(loopcounter = 0; (loopcounter < 16); loopcounter++)\r\n      {\r\n        hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];\r\n      }\r\n      /* Reset bit 0 */\r\n      hcryp->Init.pScratch[15] &= 0xfe;\r\n      \r\n      /* Select payload phase once the header phase is performed */\r\n      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n      /* Set the phase */\r\n      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n    \r\n    if(Size != 0)\r\n    {\r\n      /* Enable Interrupts */\r\n      __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n      /* Enable the CRYP peripheral */\r\n      __HAL_CRYP_ENABLE(hcryp);\r\n    }\r\n    else\r\n    {\r\n      /* Change the CRYP state and phase */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n    }\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    hcryp->pCrypInBuffPtr += 16;\r\n    hcryp->CrypInCount -= 16;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    hcryp->pCrypOutBuffPtr += 16;\r\n    hcryp->CrypOutCount -= 16;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP peripheral state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES GCM decryption mode using IT.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @param  Size Length of the cyphertext buffer, must be a multiple of 16\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    /* Get the buffer addresses and sizes */    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pCypherData;\r\n    hcryp->pCrypOutBuffPtr = pPlainData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP peripheral state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {\r\n      /* Set the key */\r\n      CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES GCM decryption mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);\r\n      \r\n      /* Set the Initialization Vector */\r\n      CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n      /* Enable CRYP to start the init phase */\r\n      __HAL_CRYP_ENABLE(hcryp);\r\n\r\n        /* Get tick */\r\n        tickstart = HAL_GetTick();\r\n\r\n      while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r\n      {\r\n        /* Check for the Timeout */\r\n        if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n          \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n      \r\n      /* Set the header phase */\r\n      if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n      /* Disable the CRYP peripheral */\r\n      __HAL_CRYP_DISABLE(hcryp);\r\n      \r\n      /* Select payload phase once the header phase is performed */\r\n      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r\n      \r\n      /* Set the phase */\r\n      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n    \r\n    if(Size != 0)\r\n    {\r\n      /* Enable Interrupts */\r\n      __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n      /* Enable the CRYP peripheral */\r\n      __HAL_CRYP_ENABLE(hcryp);\r\n    }\r\n    else\r\n    {\r\n      /* Process Locked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP state and phase */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n    }\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    hcryp->pCrypInBuffPtr += 16;\r\n    hcryp->CrypInCount -= 16;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call the Input data transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    hcryp->pCrypOutBuffPtr += 16;\r\n    hcryp->CrypOutCount -= 16;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP peripheral state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES CCM decryption mode using interrupt\r\n  *         then decrypted pCypherData. The cypher data are available in pPlainData.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData Pointer to the cyphertext buffer \r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 16\r\n  * @param  pPlainData Pointer to the plaintext buffer  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  uint32_t tickstart = 0;\r\n  uint32_t headersize = hcryp->Init.HeaderSize;\r\n  uint32_t headeraddr = (uint32_t)hcryp->Init.Header;\r\n  uint32_t loopcounter = 0;\r\n  uint32_t bufferidx = 0;\r\n  uint8_t blockb0[16] = {0};/* Block B0 */\r\n  uint8_t ctr[16] = {0}; /* Counter */\r\n  uint32_t b0addr = (uint32_t)blockb0;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pCypherData;\r\n    hcryp->pCrypOutBuffPtr = pPlainData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP peripheral state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {\r\n      /************************ Formatting the header block *******************/\r\n      if(headersize != 0)\r\n      {\r\n        /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */\r\n        if(headersize < 65280)\r\n        {\r\n          hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFFU);\r\n          hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU);\r\n          headersize += 2;\r\n        }\r\n        else\r\n        {\r\n          /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */\r\n          hcryp->Init.pScratch[bufferidx++] = 0xFFU;\r\n          hcryp->Init.pScratch[bufferidx++] = 0xFEU;\r\n          hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;\r\n          hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;\r\n          hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;\r\n          hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;\r\n          headersize += 6;\r\n        }\r\n        /* Copy the header buffer in internal buffer \"hcryp->Init.pScratch\" */\r\n        for(loopcounter = 0; loopcounter < headersize; loopcounter++)\r\n        {\r\n          hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];\r\n        }\r\n        /* Check if the header size is modulo 16 */\r\n        if ((headersize % 16) != 0)\r\n        {\r\n          /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */\r\n          for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)\r\n          {\r\n            hcryp->Init.pScratch[loopcounter] = 0;\r\n          }\r\n          /* Set the header size to modulo 16 */\r\n          headersize = ((headersize/16) + 1) * 16;\r\n        }\r\n        /* Set the pointer headeraddr to hcryp->Init.pScratch */\r\n        headeraddr = (uint32_t)hcryp->Init.pScratch;\r\n      }\r\n      /*********************** Formatting the block B0 ************************/\r\n      if(headersize != 0)\r\n      {\r\n        blockb0[0] = 0x40;\r\n      }\r\n      /* Flags byte */\r\n      /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */\r\n      blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);\r\n      blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);\r\n      \r\n      for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)\r\n      {\r\n        blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];\r\n      }\r\n      for ( ; loopcounter < 13; loopcounter++)\r\n      {\r\n        blockb0[loopcounter+1] = 0;\r\n      }\r\n      \r\n      blockb0[14] = (Size >> 8);\r\n      blockb0[15] = (Size & 0xFF);\r\n      \r\n      /************************* Formatting the initial counter ***************/\r\n      /* Byte 0:\r\n         Bits 7 and 6 are reserved and shall be set to 0\r\n         Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter \r\n         blocks are distinct from B0\r\n         Bits 0, 1, and 2 contain the same encoding of q as in B0\r\n      */\r\n      ctr[0] = blockb0[0] & 0x07;\r\n      /* byte 1 to NonceSize is the IV (Nonce) */\r\n      for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)\r\n      {\r\n        ctr[loopcounter] = blockb0[loopcounter];\r\n      }\r\n      /* Set the LSB to 1 */\r\n      ctr[15] |= 0x01;\r\n      \r\n      /* Set the key */\r\n      CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES CCM mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);\r\n      \r\n      /* Set the Initialization Vector */\r\n      CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);\r\n      \r\n      /* Select init phase */\r\n      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);\r\n      \r\n      b0addr = (uint32_t)blockb0;\r\n      /* Write the blockb0 block in the IN FIFO */\r\n      hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n      b0addr+=4;\r\n      hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n      b0addr+=4;\r\n      hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n      b0addr+=4;\r\n      hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n      \r\n      /* Enable the CRYP peripheral */\r\n      __HAL_CRYP_ENABLE(hcryp);\r\n\r\n      /* Get tick */\r\n      tickstart = HAL_GetTick();\r\n\r\n      while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r\n      {\r\n        /* Check for the Timeout */\r\n        if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n          \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n      /***************************** Header phase *****************************/\r\n      if(headersize != 0)\r\n      {\r\n        /* Select header phase */\r\n        __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);\r\n        \r\n        /* Enable Crypto processor */\r\n        __HAL_CRYP_ENABLE(hcryp);\r\n        \r\n        for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)\r\n        {\r\n         /* Get tick */\r\n         tickstart = HAL_GetTick();\r\n\r\n          while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))\r\n          {\r\n            /* Check for the Timeout */\r\n            if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r\n            {\r\n              /* Change state */\r\n              hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n              \r\n              /* Process Unlocked */\r\n              __HAL_UNLOCK(hcryp);\r\n              \r\n              return HAL_TIMEOUT;\r\n            }\r\n          }\r\n          /* Write the header block in the IN FIFO */\r\n          hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n          headeraddr+=4;\r\n          hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n          headeraddr+=4;\r\n          hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n          headeraddr+=4;\r\n          hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n          headeraddr+=4;\r\n        }\r\n\r\n        /* Get tick */\r\n        tickstart = HAL_GetTick();\r\n\r\n        while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)\r\n        {\r\n          /* Check for the Timeout */\r\n          if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r\n          {\r\n            /* Change state */\r\n            hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n            \r\n            /* Process Unlocked */\r\n            __HAL_UNLOCK(hcryp);\r\n            \r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n      }\r\n      /* Save formatted counter into the scratch buffer pScratch */\r\n      for(loopcounter = 0; (loopcounter < 16); loopcounter++)\r\n      {\r\n        hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];\r\n      }\r\n      /* Reset bit 0 */\r\n      hcryp->Init.pScratch[15] &= 0xfe;\r\n      /* Select payload phase once the header phase is performed */\r\n      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n      /* Set the phase */\r\n      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n    \r\n    /* Enable Interrupts */\r\n    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n    \r\n    /* Enable the CRYP peripheral */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    hcryp->pCrypInBuffPtr += 16;\r\n    hcryp->CrypInCount -= 16;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call the Input data transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    hcryp->pCrypOutBuffPtr += 16;\r\n    hcryp->CrypOutCount -= 16;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP peripheral state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES GCM encryption mode using DMA.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 16\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t tickstart = 0;\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pPlainData;\r\n    outputaddr = (uint32_t)pCypherData;\r\n    \r\n    /* Change the CRYP peripheral state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {\r\n      /* Set the key */\r\n      CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES GCM mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);\r\n      \r\n      /* Set the Initialization Vector */\r\n      CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n      /* Enable CRYP to start the init phase */\r\n      __HAL_CRYP_ENABLE(hcryp);\r\n      \r\n      /* Get tick */\r\n      tickstart = HAL_GetTick();\r\n\r\n      while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r\n      {\r\n        /* Check for the Timeout */\r\n        if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n          \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n      /* Set the header phase */\r\n      if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n      /* Disable the CRYP peripheral */\r\n      __HAL_CRYP_DISABLE(hcryp);\r\n      \r\n      /* Select payload phase once the header phase is performed */\r\n      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n      /* Set the phase */\r\n      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n    \r\n    /* Set the input and output addresses and start DMA transfer */ \r\n    CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n    \r\n    /* Unlock process */\r\n    __HAL_UNLOCK(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES CCM encryption mode using interrupt.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 16\r\n  * @param  pCypherData Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  uint32_t headersize;\r\n  uint32_t headeraddr;\r\n  uint32_t loopcounter = 0;\r\n  uint32_t bufferidx = 0;\r\n  uint8_t blockb0[16] = {0};/* Block B0 */\r\n  uint8_t ctr[16] = {0}; /* Counter */\r\n  uint32_t b0addr = (uint32_t)blockb0;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pPlainData;\r\n    outputaddr = (uint32_t)pCypherData;\r\n    \r\n    headersize = hcryp->Init.HeaderSize;\r\n    headeraddr = (uint32_t)hcryp->Init.Header;\r\n    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pPlainData;\r\n    hcryp->pCrypOutBuffPtr = pCypherData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP peripheral state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {\r\n      /************************ Formatting the header block *******************/\r\n      if(headersize != 0)\r\n      {\r\n        /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */\r\n        if(headersize < 65280)\r\n        {\r\n          hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFFU);\r\n          hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU);\r\n          headersize += 2;\r\n        }\r\n        else\r\n        {\r\n          /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */\r\n          hcryp->Init.pScratch[bufferidx++] = 0xFFU;\r\n          hcryp->Init.pScratch[bufferidx++] = 0xFEU;\r\n          hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;\r\n          hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;\r\n          hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;\r\n          hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;\r\n          headersize += 6;\r\n        }\r\n        /* Copy the header buffer in internal buffer \"hcryp->Init.pScratch\" */\r\n        for(loopcounter = 0; loopcounter < headersize; loopcounter++)\r\n        {\r\n          hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];\r\n        }\r\n        /* Check if the header size is modulo 16 */\r\n        if ((headersize % 16) != 0)\r\n        {\r\n          /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */\r\n          for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)\r\n          {\r\n            hcryp->Init.pScratch[loopcounter] = 0;\r\n          }\r\n          /* Set the header size to modulo 16 */\r\n          headersize = ((headersize/16) + 1) * 16;\r\n        }\r\n        /* Set the pointer headeraddr to hcryp->Init.pScratch */\r\n        headeraddr = (uint32_t)hcryp->Init.pScratch;\r\n      }\r\n      /*********************** Formatting the block B0 ************************/\r\n      if(headersize != 0)\r\n      {\r\n        blockb0[0] = 0x40;\r\n      }\r\n      /* Flags byte */\r\n      /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */\r\n      blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);\r\n      blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);\r\n      \r\n      for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)\r\n      {\r\n        blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];\r\n      }\r\n      for ( ; loopcounter < 13; loopcounter++)\r\n      {\r\n        blockb0[loopcounter+1] = 0;\r\n      }\r\n      \r\n      blockb0[14] = (Size >> 8);\r\n      blockb0[15] = (Size & 0xFF);\r\n      \r\n      /************************* Formatting the initial counter ***************/\r\n      /* Byte 0:\r\n         Bits 7 and 6 are reserved and shall be set to 0\r\n         Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter \r\n         blocks are distinct from B0\r\n         Bits 0, 1, and 2 contain the same encoding of q as in B0\r\n      */\r\n      ctr[0] = blockb0[0] & 0x07;\r\n      /* byte 1 to NonceSize is the IV (Nonce) */\r\n      for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)\r\n      {\r\n        ctr[loopcounter] = blockb0[loopcounter];\r\n      }\r\n      /* Set the LSB to 1 */\r\n      ctr[15] |= 0x01;\r\n      \r\n      /* Set the key */\r\n      CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES CCM mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);\r\n      \r\n      /* Set the Initialization Vector */\r\n      CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);\r\n      \r\n      /* Select init phase */\r\n      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);\r\n      \r\n      b0addr = (uint32_t)blockb0;\r\n      /* Write the blockb0 block in the IN FIFO */\r\n      hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n      b0addr+=4;\r\n      hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n      b0addr+=4;\r\n      hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n      b0addr+=4;\r\n      hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n      \r\n      /* Enable the CRYP peripheral */\r\n      __HAL_CRYP_ENABLE(hcryp);\r\n      \r\n      /* Get tick */\r\n      tickstart = HAL_GetTick();\r\n \r\n      while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r\n      {\r\n        /* Check for the Timeout */\r\n        if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n          \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n      /***************************** Header phase *****************************/\r\n      if(headersize != 0)\r\n      {\r\n        /* Select header phase */\r\n        __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);\r\n        \r\n        /* Enable Crypto processor */\r\n        __HAL_CRYP_ENABLE(hcryp);\r\n        \r\n        for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)\r\n        {\r\n         /* Get tick */\r\n         tickstart = HAL_GetTick();\r\n\r\n          while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))\r\n          {\r\n            /* Check for the Timeout */\r\n            if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r\n            {\r\n              /* Change state */\r\n              hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n              \r\n              /* Process Unlocked */\r\n              __HAL_UNLOCK(hcryp);\r\n              \r\n              return HAL_TIMEOUT;\r\n            }\r\n          }\r\n          /* Write the header block in the IN FIFO */\r\n          hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n          headeraddr+=4;\r\n          hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n          headeraddr+=4;\r\n          hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n          headeraddr+=4;\r\n          hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n          headeraddr+=4;\r\n        }\r\n        \r\n        /* Get tick */\r\n        tickstart = HAL_GetTick();\r\n\r\n        while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)\r\n        {\r\n          /* Check for the Timeout */\r\n          if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r\n          {\r\n            /* Change state */\r\n            hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n            \r\n            /* Process Unlocked */\r\n            __HAL_UNLOCK(hcryp);\r\n            \r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n      }\r\n      /* Save formatted counter into the scratch buffer pScratch */\r\n      for(loopcounter = 0; (loopcounter < 16); loopcounter++)\r\n      {\r\n        hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];\r\n      }\r\n      /* Reset bit 0 */\r\n      hcryp->Init.pScratch[15] &= 0xfe;\r\n      \r\n      /* Select payload phase once the header phase is performed */\r\n      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n      /* Set the phase */\r\n      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n    \r\n    /* Set the input and output addresses and start DMA transfer */ \r\n    CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n    \r\n    /* Unlock process */\r\n    __HAL_UNLOCK(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES GCM decryption mode using DMA.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData Pointer to the cyphertext buffer.\r\n  * @param  Size Length of the cyphertext buffer, must be a multiple of 16\r\n  * @param  pPlainData Pointer to the plaintext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pCypherData;\r\n    outputaddr = (uint32_t)pPlainData;\r\n    \r\n    /* Change the CRYP peripheral state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {\r\n      /* Set the key */\r\n      CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES GCM decryption mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);\r\n      \r\n      /* Set the Initialization Vector */\r\n      CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);\r\n      \r\n      /* Enable CRYP to start the init phase */\r\n      __HAL_CRYP_ENABLE(hcryp);\r\n      \r\n      /* Get tick */\r\n      tickstart = HAL_GetTick();\r\n\r\n      while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r\n      {\r\n        /* Check for the Timeout */\r\n        if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n          \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n      \r\n      /* Set the header phase */\r\n      if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n      /* Disable the CRYP peripheral */\r\n      __HAL_CRYP_DISABLE(hcryp);\r\n      \r\n      /* Select payload phase once the header phase is performed */\r\n      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r\n      \r\n      /* Set the phase */\r\n      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n    \r\n    /* Set the input and output addresses and start DMA transfer */ \r\n    CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n    \r\n    /* Unlock process */\r\n    __HAL_UNLOCK(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES CCM decryption mode using DMA\r\n  *         then decrypted pCypherData. The cypher data are available in pPlainData.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData Pointer to the cyphertext buffer  \r\n  * @param  Size Length of the plaintext buffer, must be a multiple of 16\r\n  * @param  pPlainData Pointer to the plaintext buffer  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  uint32_t headersize;\r\n  uint32_t headeraddr;\r\n  uint32_t loopcounter = 0;\r\n  uint32_t bufferidx = 0;\r\n  uint8_t blockb0[16] = {0};/* Block B0 */\r\n  uint8_t ctr[16] = {0}; /* Counter */\r\n  uint32_t b0addr = (uint32_t)blockb0;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pCypherData;\r\n    outputaddr = (uint32_t)pPlainData;\r\n    \r\n    headersize = hcryp->Init.HeaderSize;\r\n    headeraddr = (uint32_t)hcryp->Init.Header;\r\n    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pCypherData;\r\n    hcryp->pCrypOutBuffPtr = pPlainData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP peripheral state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {\r\n      /************************ Formatting the header block *******************/\r\n      if(headersize != 0)\r\n      {\r\n        /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */\r\n        if(headersize < 65280)\r\n        {\r\n          hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFFU);\r\n          hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU);\r\n          headersize += 2;\r\n        }\r\n        else\r\n        {\r\n          /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */\r\n          hcryp->Init.pScratch[bufferidx++] = 0xFFU;\r\n          hcryp->Init.pScratch[bufferidx++] = 0xFEU;\r\n          hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;\r\n          hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;\r\n          hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;\r\n          hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;\r\n          headersize += 6;\r\n        }\r\n        /* Copy the header buffer in internal buffer \"hcryp->Init.pScratch\" */\r\n        for(loopcounter = 0; loopcounter < headersize; loopcounter++)\r\n        {\r\n          hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];\r\n        }\r\n        /* Check if the header size is modulo 16 */\r\n        if ((headersize % 16) != 0)\r\n        {\r\n          /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */\r\n          for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)\r\n          {\r\n            hcryp->Init.pScratch[loopcounter] = 0;\r\n          }\r\n          /* Set the header size to modulo 16 */\r\n          headersize = ((headersize/16) + 1) * 16;\r\n        }\r\n        /* Set the pointer headeraddr to hcryp->Init.pScratch */\r\n        headeraddr = (uint32_t)hcryp->Init.pScratch;\r\n      }\r\n      /*********************** Formatting the block B0 ************************/\r\n      if(headersize != 0)\r\n      {\r\n        blockb0[0] = 0x40;\r\n      }\r\n      /* Flags byte */\r\n      /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */\r\n      blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);\r\n      blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);\r\n      \r\n      for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)\r\n      {\r\n        blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];\r\n      }\r\n      for ( ; loopcounter < 13; loopcounter++)\r\n      {\r\n        blockb0[loopcounter+1] = 0;\r\n      }\r\n      \r\n      blockb0[14] = (Size >> 8);\r\n      blockb0[15] = (Size & 0xFF);\r\n      \r\n      /************************* Formatting the initial counter ***************/\r\n      /* Byte 0:\r\n         Bits 7 and 6 are reserved and shall be set to 0\r\n         Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter \r\n         blocks are distinct from B0\r\n         Bits 0, 1, and 2 contain the same encoding of q as in B0\r\n      */\r\n      ctr[0] = blockb0[0] & 0x07;\r\n      /* byte 1 to NonceSize is the IV (Nonce) */\r\n      for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)\r\n      {\r\n        ctr[loopcounter] = blockb0[loopcounter];\r\n      }\r\n      /* Set the LSB to 1 */\r\n      ctr[15] |= 0x01;\r\n      \r\n      /* Set the key */\r\n      CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES CCM mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);\r\n      \r\n      /* Set the Initialization Vector */\r\n      CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);\r\n      \r\n      /* Select init phase */\r\n      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);\r\n      \r\n      b0addr = (uint32_t)blockb0;\r\n      /* Write the blockb0 block in the IN FIFO */\r\n      hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n      b0addr+=4;\r\n      hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n      b0addr+=4;\r\n      hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n      b0addr+=4;\r\n      hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n      \r\n      /* Enable the CRYP peripheral */\r\n      __HAL_CRYP_ENABLE(hcryp);\r\n      \r\n      /* Get tick */\r\n      tickstart = HAL_GetTick();\r\n \r\n      while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r\n      {\r\n        /* Check for the Timeout */\r\n        \r\n        if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n          \r\n          return HAL_TIMEOUT;\r\n          \r\n        }\r\n      }\r\n      /***************************** Header phase *****************************/\r\n      if(headersize != 0)\r\n      {\r\n        /* Select header phase */\r\n        __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);\r\n        \r\n        /* Enable Crypto processor */\r\n        __HAL_CRYP_ENABLE(hcryp);\r\n        \r\n        for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)\r\n        {\r\n         /* Get tick */\r\n         tickstart = HAL_GetTick();\r\n \r\n          while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))\r\n          {\r\n            /* Check for the Timeout */\r\n            if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r\n            {\r\n              /* Change state */\r\n              hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n              \r\n              /* Process Unlocked */\r\n              __HAL_UNLOCK(hcryp);\r\n              \r\n              return HAL_TIMEOUT;\r\n            }\r\n          }\r\n          /* Write the header block in the IN FIFO */\r\n          hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n          headeraddr+=4;\r\n          hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n          headeraddr+=4;\r\n          hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n          headeraddr+=4;\r\n          hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n          headeraddr+=4;\r\n        }\r\n        \r\n        /* Get tick */\r\n        tickstart = HAL_GetTick();\r\n\r\n        while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)\r\n        {\r\n          /* Check for the Timeout */\r\n          if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r\n          {\r\n            /* Change state */\r\n            hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n            \r\n            /* Process Unlocked */\r\n            __HAL_UNLOCK(hcryp);\r\n            \r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n      }\r\n      /* Save formatted counter into the scratch buffer pScratch */\r\n      for(loopcounter = 0; (loopcounter < 16); loopcounter++)\r\n      {\r\n        hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];\r\n      }\r\n      /* Reset bit 0 */\r\n      hcryp->Init.pScratch[15] &= 0xfe;\r\n      /* Select payload phase once the header phase is performed */\r\n      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n      /* Set the phase */\r\n      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n    /* Set the input and output addresses and start DMA transfer */ \r\n    CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n    \r\n    /* Unlock process */\r\n    __HAL_UNLOCK(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup CRYPEx_Exported_Functions_Group2 CRYPEx IRQ handler management  \r\n *  @brief   CRYPEx IRQ handler.\r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                ##### CRYPEx IRQ handler management #####\r\n  ==============================================================================  \r\n[..]  This section provides CRYPEx IRQ handler function.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  This function handles CRYPEx interrupt request.\r\n  * @param  hcryp pointer to a CRYPEx_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @retval None\r\n  */\r\nvoid HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp)\r\n{\r\n  switch(CRYP->CR & CRYP_CR_ALGOMODE_DIRECTION)\r\n  {    \r\n  case CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT:\r\n    HAL_CRYPEx_AESGCM_Encrypt_IT(hcryp, NULL, 0, NULL);\r\n    break;\r\n    \r\n  case CRYP_CR_ALGOMODE_AES_GCM_DECRYPT:\r\n    HAL_CRYPEx_AESGCM_Decrypt_IT(hcryp, NULL, 0, NULL);\r\n    break;\r\n    \r\n  case CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT:\r\n    HAL_CRYPEx_AESCCM_Encrypt_IT(hcryp, NULL, 0, NULL);\r\n    break;\r\n    \r\n  case CRYP_CR_ALGOMODE_AES_CCM_DECRYPT:\r\n    HAL_CRYPEx_AESCCM_Decrypt_IT(hcryp, NULL, 0, NULL);\r\n    break;\r\n    \r\n  default:\r\n    break;\r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n#endif /* CRYP */\r\n  \r\n#if defined (AES)\r\n\r\n/** @defgroup AESEx AESEx\r\n  * @brief CRYP Extended HAL module driver\r\n  * @{\r\n  */\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants\r\n  * @{\r\n  */\r\n#define CRYP_CCF_TIMEOUTVALUE                      22000  /*!< CCF flag raising time-out value */\r\n#define CRYP_BUSY_TIMEOUTVALUE                     22000  /*!< BUSY flag reset time-out value  */\r\n\r\n#define CRYP_POLLING_OFF                             0x0  /*!< No polling when padding */\r\n#define CRYP_POLLING_ON                              0x1  /*!< Polling when padding    */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions\r\n * @{\r\n */\r\nstatic HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);\r\nstatic HAL_StatusTypeDef CRYP_ReadKey(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t Timeout);\r\nstatic void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);\r\nstatic void CRYP_GCMCMAC_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);\r\nstatic void CRYP_GCMCMAC_DMAInCplt(DMA_HandleTypeDef *hdma);\r\nstatic void CRYP_GCMCMAC_DMAError(DMA_HandleTypeDef *hdma);\r\nstatic void CRYP_GCMCMAC_DMAOutCplt(DMA_HandleTypeDef *hdma);\r\nstatic HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);\r\nstatic HAL_StatusTypeDef CRYP_WaitOnBusyFlagReset(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);\r\nstatic void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);\r\nstatic void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);\r\nstatic void CRYP_DMAError(DMA_HandleTypeDef *hdma);\r\nstatic void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_t polling);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions\r\n  * @{\r\n  */\r\n\r\n\r\n/** @defgroup CRYPEx_Exported_Functions_Group1 Extended callback function \r\n *  @brief    Extended callback functions. \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                 ##### Extended callback functions #####\r\n =============================================================================== \r\n    [..]  This section provides callback function:\r\n      (+) Computation completed.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n\r\n/**\r\n  * @brief  Computation completed callbacks.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @retval None\r\n  */\r\n__weak void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcryp);\r\n\r\n  /* NOTE : This function should not be modified; when the callback is needed,\r\n            the HAL_CRYPEx_ComputationCpltCallback can be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRYPEx_Exported_Functions_Group2 AES extended processing functions \r\n *  @brief   Extended processing functions. \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                      ##### AES extended processing functions #####\r\n  ==============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Encrypt plaintext or decrypt cipher text using AES algorithm in different chaining modes.\r\n          Functions are generic (handles ECB, CBC and CTR and all modes) and are only differentiated\r\n          based on the processing type. Three processing types are available:\r\n          (++) Polling mode\r\n          (++) Interrupt mode\r\n          (++) DMA mode\r\n      (+) Generate and authentication tag in addition to encrypt/decrypt a plain/cipher text using AES \r\n          algorithm in different chaining modes.\r\n          Functions are generic (handles GCM, GMAC, CMAC and CCM when applicable) and process only one phase \r\n          so that steps can be skipped if so required. Functions are only differentiated based on the processing type. \r\n          Three processing types are available:\r\n          (++) Polling mode\r\n          (++) Interrupt mode\r\n          (++) DMA mode          \r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Carry out in polling mode the ciphering or deciphering operation according to\r\n  *         hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and \r\n  *         chaining modes ECB, CBC and CTR are managed by this function in polling mode.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pInputData Pointer to the plain text in case of encryption or cipher text in case of decryption\r\n  *                     or key derivation+decryption.\r\n  *                     Parameter is meaningless in case of key derivation.      \r\n  * @param  Size Length of the input data buffer in bytes, must be a multiple of 16.\r\n  *               Parameter is meaningless in case of key derivation.  \r\n  * @param  pOutputData Pointer to the cipher text in case of encryption or plain text in case of \r\n  *                     decryption/key derivation+decryption, or pointer to the derivative keys in\r\n  *                     case of key derivation only.   \r\n  * @param  Timeout Specify Timeout value \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData, uint32_t Timeout)\r\n{\r\n\r\n  if (hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Check parameters setting */\r\n    if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)\r\n    {\r\n      if (pOutputData == NULL) \r\n      {\r\n        return  HAL_ERROR;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0))\r\n      {\r\n        return  HAL_ERROR;\r\n      }\r\n    }\r\n    \r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n  \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n    /* Call CRYP_ReadKey() API if the operating mode is set to\r\n       key derivation, CRYP_ProcessData() otherwise  */\r\n    if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)\r\n    {\r\n      if(CRYP_ReadKey(hcryp, pOutputData, Timeout) != HAL_OK)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }    \r\n    }\r\n    else\r\n    {\r\n      if(CRYP_ProcessData(hcryp, pInputData, Size, pOutputData, Timeout) != HAL_OK)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  \r\n    /* If the state has not been set to SUSPENDED, set it to\r\n       READY, otherwise keep it as it is */\r\n    if (hcryp->State != HAL_CRYP_STATE_SUSPENDED)\r\n    {\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n    }\r\n  \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hcryp);\r\n  \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n\r\n\r\n/**\r\n  * @brief  Carry out in interrupt mode the ciphering or deciphering operation according to\r\n  *         hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and \r\n  *         chaining modes ECB, CBC and CTR are managed by this function in interrupt mode.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pInputData Pointer to the plain text in case of encryption or cipher text in case of decryption\r\n  *                     or key derivation+decryption.\r\n  *                     Parameter is meaningless in case of key derivation.      \r\n  * @param  Size Length of the input data buffer in bytes, must be a multiple of 16.\r\n  *               Parameter is meaningless in case of key derivation.  \r\n  * @param  pOutputData Pointer to the cipher text in case of encryption or plain text in case of \r\n  *                     decryption/key derivation+decryption, or pointer to the derivative keys in \r\n  *                     case of key derivation only.    \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYPEx_AES_IT(CRYP_HandleTypeDef *hcryp,  uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData)\r\n{\r\n  uint32_t inputaddr = 0;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Check parameters setting */\r\n    if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)\r\n    {\r\n      if (pOutputData == NULL) \r\n      {\r\n        return  HAL_ERROR;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0))\r\n      {\r\n        return  HAL_ERROR;\r\n      }\r\n    }\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    /* If operating mode is not limited to key derivation only,\r\n       get the buffers addresses and sizes */\r\n    if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION)\r\n    {\r\n\r\n      hcryp->CrypInCount = Size;\r\n      hcryp->pCrypInBuffPtr = pInputData;\r\n      hcryp->pCrypOutBuffPtr = pOutputData;\r\n      hcryp->CrypOutCount = Size;\r\n    }\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n      /* Process Unlocked */\r\n    __HAL_UNLOCK(hcryp);\r\n    \r\n    /* Enable Computation Complete Flag and Error Interrupts */\r\n    __HAL_CRYP_ENABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);\r\n    \r\n    \r\n    /* If operating mode is key derivation only, the input data have \r\n       already been entered during the initialization process. For\r\n       the other operating modes, they are fed to the CRYP hardware \r\n       block at this point. */\r\n    if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION)\r\n    {\r\n      /* Initiate the processing under interrupt in entering \r\n         the first input data */\r\n      inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n      /* Increment/decrement instance pointer/counter */\r\n      hcryp->pCrypInBuffPtr += 16;\r\n      hcryp->CrypInCount -= 16;\r\n      /* Write the first input block in the Data Input register */\r\n      hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n      inputaddr+=4;\r\n      hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n      inputaddr+=4;\r\n      hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);\r\n      inputaddr+=4;\r\n      hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n    }\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;   \r\n  }\r\n}\r\n  \r\n  \r\n  \r\n\r\n\r\n/**\r\n  * @brief  Carry out in DMA mode the ciphering or deciphering operation according to\r\n  *         hcryp->Init structure fields.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pInputData Pointer to the plain text in case of encryption or cipher text in case of decryption\r\n  *                     or key derivation+decryption.    \r\n  * @param  Size Length of the input data buffer in bytes, must be a multiple of 16.\r\n  * @param  pOutputData Pointer to the cipher text in case of encryption or plain text in case of \r\n  *                     decryption/key derivation+decryption.\r\n  * @note   Chaining modes ECB, CBC and CTR are managed by this function in DMA mode.   \r\n  * @note   Supported operating modes are encryption, decryption and key derivation with decryption. \r\n  * @note   No DMA channel is provided for key derivation only and therefore, access to AES_KEYRx \r\n  *         registers must be done by software.   \r\n  * @note   This API is not applicable to key derivation only; for such a mode, access to AES_KEYRx \r\n  *         registers must be done by software thru HAL_CRYPEx_AES() or HAL_CRYPEx_AES_IT() APIs.\r\n  * @note   pInputData and pOutputData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYPEx_AES_DMA(CRYP_HandleTypeDef *hcryp,  uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData)\r\n{\r\n  uint32_t inputaddr = 0;\r\n  uint32_t outputaddr = 0;\r\n  \r\n  if (hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Check parameters setting */\r\n    if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)\r\n    {\r\n      /* no DMA channel is provided for key derivation operating mode, \r\n         access to AES_KEYRx registers must be done by software */\r\n      return  HAL_ERROR;\r\n    }\r\n    else\r\n    {\r\n      if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0))\r\n      {\r\n        return  HAL_ERROR;\r\n      }\r\n    }\r\n    \r\n    \r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pInputData;\r\n    outputaddr = (uint32_t)pOutputData;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Set the input and output addresses and start DMA transfer */ \r\n    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;   \r\n  }\r\n}\r\n  \r\n\r\n\r\n\r\n\r\n\r\n/**\r\n  * @brief  Carry out in polling mode the authentication tag generation as well as the ciphering or deciphering \r\n  *         operation according to hcryp->Init structure fields. \r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pInputData \r\n  *         - pointer to payload data in GCM payload phase, \r\n  *         - pointer to B0 block in CMAC header phase,\r\n  *         - pointer to C block in CMAC final phase. \r\n  *         - Parameter is meaningless in case of GCM/GMAC init, header and final phases.                                       \r\n  * @param  Size \r\n  *         - length of the input payload data buffer in bytes,\r\n  *         - length of B0 block (in bytes) in CMAC header phase,\r\n  *         - length of C block (in bytes) in CMAC final phase.\r\n  *         - Parameter is meaningless in case of GCM/GMAC init and header phases.                                \r\n  * @param  pOutputData \r\n  *         - pointer to plain or cipher text in GCM payload phase, \r\n  *         - pointer to authentication tag in GCM/GMAC and CMAC final phases.\r\n  *         - Parameter is meaningless in case of GCM/GMAC init and header phases\r\n  *           and in case of CMAC header phase.  \r\n  * @param  Timeout Specify Timeout value \r\n  * @note   Supported operating modes are encryption and decryption, supported chaining modes are GCM, GMAC, CMAC and CCM when the latter is applicable.\r\n  * @note   Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes \r\n  *         can be skipped by the user if so required.          \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData, uint32_t Timeout)\r\n{\r\n  uint32_t index          = 0;\r\n  uint32_t inputaddr      = 0;\r\n  uint32_t outputaddr     = 0;\r\n  uint32_t tagaddr        = 0;\r\n  uint64_t headerlength   = 0; \r\n  uint64_t inputlength    = 0;\r\n  uint64_t payloadlength  = 0; \r\n  uint32_t difflength     = 0;\r\n  uint32_t addhoc_process = 0;  \r\n  \r\n  if (hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* input/output parameters check */\r\n    if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)\r\n    {\r\n      if ((hcryp->Init.Header != NULL) && (hcryp->Init.HeaderSize == 0))\r\n      {\r\n        return  HAL_ERROR;\r\n      }\r\n#if defined(AES_CR_NPBLB)\r\n      if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC)\r\n#else      \r\n      if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)\r\n#endif      \r\n      {\r\n        /* In case of CMAC (or CCM) header phase resumption, we can have pInputData = NULL and  Size = 0 */\r\n        if (((pInputData != NULL) && (Size == 0)) || ((pInputData == NULL) && (Size != 0)))\r\n        {\r\n          return  HAL_ERROR;\r\n        }\r\n      }\r\n    }\r\n    else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)\r\n    {   \r\n      if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0))\r\n      {\r\n        return  HAL_ERROR;\r\n      }\r\n    }\r\n    else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE)\r\n    {\r\n      if (pOutputData == NULL)\r\n      {\r\n        return  HAL_ERROR;\r\n      }\r\n#if defined(AES_CR_NPBLB)  \r\n      if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC) && (pInputData == NULL))\r\n#else    \r\n      if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (pInputData == NULL))\r\n#endif      \r\n      {\r\n        return  HAL_ERROR;\r\n      }\r\n    }\r\n      \r\n      \r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n  \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n    /*==============================================*/\r\n    /* GCM/GMAC (or CCM when applicable) init phase */\r\n    /*==============================================*/\r\n    /* In case of init phase, the input data (Key and Initialization Vector) have \r\n       already been entered during the initialization process. Therefore, the\r\n       API just waits for the CCF flag to be set. */\r\n    if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE)\r\n    {\r\n      /* just wait for hash computation */\r\n      if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)  \r\n      { \r\n        hcryp->State = HAL_CRYP_STATE_READY;        \r\n        __HAL_UNLOCK(hcryp);\r\n        return HAL_TIMEOUT;\r\n      }\r\n      \r\n      /* Clear CCF Flag */\r\n      __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);\r\n      /* Mark that the initialization phase is over */\r\n      hcryp->Phase = HAL_CRYP_PHASE_INIT_OVER;\r\n    }\r\n    /*=====================================*/\r\n    /* GCM/GMAC or (CCM/)CMAC header phase */\r\n    /*=====================================*/\r\n    else if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)\r\n    {      \r\n      /* Set header phase; for GCM or GMAC, set data-byte at this point */\r\n      if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)\r\n      {\r\n        MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH|AES_CR_DATATYPE, CRYP_HEADER_PHASE|hcryp->Init.DataType);\r\n      }\r\n      else\r\n      {\r\n        MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_HEADER_PHASE);\r\n      }\r\n         \r\n      /* Enable the Peripheral */\r\n      __HAL_CRYP_ENABLE();\r\n      \r\n#if !defined(AES_CR_NPBLB)       \r\n      /* in case of CMAC, enter B0 block in header phase, before the header itself. */\r\n      /* If Size = 0 (possible case of resumption after CMAC header phase suspension),\r\n         skip these steps and go directly to header buffer feeding to the HW */\r\n      if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (Size != 0))\r\n      {\r\n        inputaddr = (uint32_t)pInputData; \r\n        \r\n        for(index=0; (index < Size); index += 16)\r\n        {\r\n          /* Write the Input block in the Data Input register */\r\n          hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n          inputaddr+=4;\r\n          hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n          inputaddr+=4;\r\n          hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);\r\n          inputaddr+=4;\r\n          hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n          inputaddr+=4;\r\n          \r\n          if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)  \r\n          { \r\n            hcryp->State = HAL_CRYP_STATE_READY;        \r\n            __HAL_UNLOCK(hcryp);\r\n            return HAL_TIMEOUT;\r\n          }\r\n          /* Clear CCF Flag */\r\n          __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);           \r\n\r\n          /* If the suspension flag has been raised and if the processing is not about\r\n           to end, suspend processing */  \r\n          if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16) < Size))        \r\n          {\r\n            /* reset SuspendRequest */\r\n            hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;\r\n            /* Change the CRYP state */\r\n            hcryp->State = HAL_CRYP_STATE_SUSPENDED;\r\n            /* Mark that the header phase is over */\r\n            hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED;\r\n            \r\n           /* Save current reading and writing locations of Input and Output buffers */\r\n           hcryp->pCrypInBuffPtr  =  (uint8_t *)inputaddr;\r\n           /* Save the total number of bytes (B blocks + header) that remain to be \r\n              processed at this point */\r\n           hcryp->CrypInCount     =  hcryp->Init.HeaderSize + Size - (index+16);\r\n        \r\n           /* Process Unlocked */\r\n            __HAL_UNLOCK(hcryp);\r\n        \r\n            return HAL_OK;\r\n          } \r\n        } /* for(index=0; (index < Size); index += 16) */             \r\n      }\r\n#endif /* !defined(AES_CR_NPBLB) */      \r\n      \r\n      /* Enter header */  \r\n      inputaddr = (uint32_t)hcryp->Init.Header; \r\n      /* Local variable headerlength is a number of bytes multiple of 128 bits,\r\n         remaining header data (if any) are handled after this loop */\r\n      headerlength =  (((hcryp->Init.HeaderSize)/16)*16) ; \r\n      if ((hcryp->Init.HeaderSize % 16) != 0)\r\n      {\r\n        difflength = (uint32_t) (hcryp->Init.HeaderSize - headerlength);   \r\n      }\r\n      for(index=0; index < headerlength; index += 16)\r\n      {\r\n        /* Write the Input block in the Data Input register */\r\n        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n        inputaddr+=4;\r\n        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n        inputaddr+=4;\r\n        hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);\r\n        inputaddr+=4;\r\n        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n        inputaddr+=4;\r\n        \r\n        if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)  \r\n        { \r\n          hcryp->State = HAL_CRYP_STATE_READY;        \r\n          __HAL_UNLOCK(hcryp);\r\n          return HAL_TIMEOUT;\r\n        }\r\n        /* Clear CCF Flag */\r\n        __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR); \r\n        \r\n        /* If the suspension flag has been raised and if the processing is not about\r\n         to end, suspend processing */  \r\n        if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16) < headerlength))        \r\n        {\r\n          /* reset SuspendRequest */\r\n          hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;\r\n          /* Change the CRYP state */\r\n          hcryp->State = HAL_CRYP_STATE_SUSPENDED;\r\n          /* Mark that the header phase is over */\r\n          hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED;\r\n          \r\n         /* Save current reading and writing locations of Input and Output buffers */\r\n         hcryp->pCrypInBuffPtr  =  (uint8_t *)inputaddr;\r\n         /* Save the total number of bytes that remain to be processed at this point */\r\n          hcryp->CrypInCount =  hcryp->Init.HeaderSize - (index+16);\r\n      \r\n         /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n      \r\n          return HAL_OK;\r\n        }       \r\n      }\r\n      \r\n      /* Case header length is not a multiple of 16 bytes */\r\n      if (difflength != 0)\r\n      {\r\n        hcryp->pCrypInBuffPtr  =  (uint8_t *)inputaddr;\r\n        CRYP_Padding(hcryp, difflength, CRYP_POLLING_ON);   \r\n      }       \r\n      \r\n      /* Mark that the header phase is over */\r\n      hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER;\r\n    }\r\n    /*============================================*/\r\n    /* GCM (or CCM when applicable) payload phase */\r\n    /*============================================*/\r\n    else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)\r\n    {\r\n      \r\n      MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PAYLOAD_PHASE);\r\n      \r\n      /* if the header phase has been bypassed, AES must be enabled again */\r\n      if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER)\r\n      {\r\n        __HAL_CRYP_ENABLE();  \r\n      }\r\n      \r\n      inputaddr  = (uint32_t)pInputData;\r\n      outputaddr = (uint32_t)pOutputData;\r\n      \r\n      /* Enter payload */\r\n      /* Specific handling to manage payload last block size less than 128 bits */\r\n      if ((Size % 16) != 0)\r\n      {\r\n        payloadlength = (Size/16) * 16;\r\n        difflength = (uint32_t) (Size - payloadlength);\r\n        addhoc_process = 1;\r\n      }\r\n      else\r\n      {\r\n        payloadlength = Size;\r\n        addhoc_process = 0;      \r\n      }\r\n            \r\n      /* Feed payload */  \r\n      for(index=0; index < payloadlength; index += 16)\r\n      {\r\n        /* Write the Input block in the Data Input register */\r\n        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n        inputaddr+=4;\r\n        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n        inputaddr+=4;\r\n        hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);\r\n        inputaddr+=4;\r\n        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n        inputaddr+=4;\r\n        \r\n        if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)  \r\n        { \r\n          hcryp->State = HAL_CRYP_STATE_READY;        \r\n          __HAL_UNLOCK(hcryp);\r\n          return HAL_TIMEOUT;\r\n        }\r\n          \r\n        /* Clear CCF Flag */\r\n        __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);\r\n        \r\n        /* Retrieve output data: read the output block \r\n           from the Data Output Register */\r\n        *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;\r\n        outputaddr+=4;\r\n        *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;\r\n        outputaddr+=4;\r\n        *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;\r\n        outputaddr+=4;\r\n        *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;\r\n        outputaddr+=4;\r\n       \r\n        /* If the suspension flag has been raised and if the processing is not about\r\n         to end, suspend processing */  \r\n        if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16) < payloadlength))\r\n        {\r\n          /* no flag waiting under IRQ handling */\r\n          if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT)\r\n          {\r\n            /* Ensure that Busy flag is reset */\r\n            if(CRYP_WaitOnBusyFlagReset(hcryp, CRYP_BUSY_TIMEOUTVALUE) != HAL_OK)  \r\n            {   \r\n              hcryp->State = HAL_CRYP_STATE_READY;        \r\n              __HAL_UNLOCK(hcryp);\r\n              return HAL_TIMEOUT;\r\n            }\r\n          }               \r\n          /* reset SuspendRequest */\r\n          hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;\r\n          /* Change the CRYP state */\r\n          hcryp->State = HAL_CRYP_STATE_SUSPENDED;\r\n          /* Mark that the header phase is over */\r\n          hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED;\r\n          \r\n          /* Save current reading and writing locations of Input and Output buffers */\r\n          hcryp->pCrypOutBuffPtr =  (uint8_t *)outputaddr;\r\n          hcryp->pCrypInBuffPtr  =  (uint8_t *)inputaddr;\r\n          /* Save the number of bytes that remain to be processed at this point */\r\n          hcryp->CrypInCount     =  Size - (index+16);          \r\n        \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n        \r\n          return HAL_OK;\r\n        }            \r\n        \r\n      }\r\n      \r\n      /* Additional processing to manage GCM(/CCM) encryption and decryption cases when \r\n         payload last block size less than 128 bits */\r\n      if (addhoc_process == 1)\r\n      {\r\n        \r\n        hcryp->pCrypInBuffPtr  =  (uint8_t *)inputaddr;\r\n        hcryp->pCrypOutBuffPtr =  (uint8_t *)outputaddr;        \r\n        CRYP_Padding(hcryp, difflength, CRYP_POLLING_ON); \r\n       \r\n      } /* (addhoc_process == 1) */\r\n         \r\n      /* Mark that the payload phase is over */\r\n      hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER;         \r\n    }\r\n    /*====================================*/\r\n    /* GCM/GMAC or (CCM/)CMAC final phase */\r\n    /*====================================*/\r\n    else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE)\r\n    {    \r\n      tagaddr = (uint32_t)pOutputData;\r\n      \r\n#if defined(AES_CR_NPBLB)   \r\n     /* By default, clear NPBLB field */\r\n      CLEAR_BIT(hcryp->Instance->CR, AES_CR_NPBLB);\r\n#endif        \r\n      \r\n      MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_FINAL_PHASE);\r\n      \r\n      /* if the header and payload phases have been bypassed, AES must be enabled again */\r\n      if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER)\r\n      {\r\n        __HAL_CRYP_ENABLE();  \r\n      }\r\n      \r\n      if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)\r\n      {\r\n        headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */\r\n        inputlength = Size * 8;                    /* input length in bits */ \r\n        \r\n           \r\n        if(hcryp->Init.DataType == CRYP_DATATYPE_1B)\r\n        {\r\n          hcryp->Instance->DINR = __RBIT((headerlength)>>32);\r\n          hcryp->Instance->DINR = __RBIT(headerlength);\r\n          hcryp->Instance->DINR = __RBIT((inputlength)>>32);\r\n          hcryp->Instance->DINR = __RBIT(inputlength);\r\n        }\r\n        else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)\r\n        {\r\n          hcryp->Instance->DINR = __REV((headerlength)>>32);\r\n          hcryp->Instance->DINR = __REV(headerlength);\r\n          hcryp->Instance->DINR = __REV((inputlength)>>32);\r\n          hcryp->Instance->DINR = __REV(inputlength);\r\n        } \r\n        else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)\r\n        {\r\n          hcryp->Instance->DINR = __ROR((headerlength)>>32, 16);\r\n          hcryp->Instance->DINR = __ROR(headerlength, 16);\r\n          hcryp->Instance->DINR = __ROR((inputlength)>>32, 16);\r\n          hcryp->Instance->DINR = __ROR(inputlength, 16);          \r\n        }\r\n        else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)\r\n        {\r\n          hcryp->Instance->DINR = (uint32_t)(headerlength>>32);\r\n          hcryp->Instance->DINR = (uint32_t)(headerlength);\r\n          hcryp->Instance->DINR = (uint32_t)(inputlength>>32);\r\n          hcryp->Instance->DINR = (uint32_t)(inputlength);\r\n        }\r\n      }\r\n#if !defined(AES_CR_NPBLB)             \r\n      else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)     \r\n      {\r\n        inputaddr  = (uint32_t)pInputData;\r\n        /* Enter the last block made of a 128-bit value formatted\r\n           from the original B0 packet. */\r\n        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n        inputaddr+=4;\r\n        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n        inputaddr+=4;\r\n        hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);\r\n        inputaddr+=4;\r\n        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n      }\r\n#endif       \r\n      \r\n      \r\n      if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)  \r\n      { \r\n          hcryp->State = HAL_CRYP_STATE_READY;        \r\n          __HAL_UNLOCK(hcryp);\r\n          return HAL_TIMEOUT;\r\n      }\r\n\r\n      /* Read the Auth TAG in the Data Out register */\r\n      *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;\r\n      tagaddr+=4;\r\n      *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;\r\n      tagaddr+=4;\r\n      *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;\r\n      tagaddr+=4;\r\n      *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; \r\n         \r\n\r\n      /* Clear CCF Flag */\r\n      __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);\r\n      /* Mark that the final phase is over */\r\n      hcryp->Phase = HAL_CRYP_PHASE_FINAL_OVER;\r\n      /* Disable the Peripheral */\r\n      __HAL_CRYP_DISABLE();\r\n    }\r\n    /*=================================================*/\r\n    /* case incorrect hcryp->Init.GCMCMACPhase setting */\r\n    /*=================================================*/\r\n    else\r\n    {\r\n      hcryp->State = HAL_CRYP_STATE_ERROR; \r\n      __HAL_UNLOCK(hcryp); \r\n      return HAL_ERROR;\r\n    }\r\n \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hcryp);\r\n  \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n\r\n\r\n\r\n/**\r\n  * @brief  Carry out in interrupt mode the authentication tag generation as well as the ciphering or deciphering \r\n  *         operation according to hcryp->Init structure fields. \r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pInputData \r\n  *         - pointer to payload data in GCM payload phase,\r\n  *         - pointer to B0 block in CMAC header phase,\r\n  *         - pointer to C block in CMAC final phase.\r\n  *         Parameter is meaningless in case of GCM/GMAC init, header and final phases.         \r\n  * @param  Size \r\n  *         - length of the input payload data buffer in bytes,\r\n  *         - length of B0 block (in bytes) in CMAC header phase,\r\n  *         - length of C block (in bytes) in CMAC final phase.\r\n  *         - Parameter is meaningless in case of GCM/GMAC init and header phases.             \r\n  * @param  pOutputData \r\n  *         - pointer to plain or cipher text in GCM payload phase, \r\n  *         - pointer to authentication tag in GCM/GMAC and CMAC final phases.\r\n  *         - Parameter is meaningless in case of GCM/GMAC init and header phases\r\n  *           and in case of CMAC header phase.\r\n  * @note   Supported operating modes are encryption and decryption, supported chaining modes are GCM, GMAC and CMAC.\r\n  * @note   Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes \r\n  *         can be skipped by the user if so required.                                 \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData)\r\n{\r\n\r\n  uint32_t inputaddr      = 0;\r\n  uint64_t headerlength   = 0;\r\n  uint64_t inputlength    = 0;\r\n  uint32_t index          = 0;\r\n  uint32_t addhoc_process = 0; \r\n  uint32_t difflength     = 0;\r\n  uint32_t difflengthmod4 = 0;\r\n  uint32_t mask[3]        = {0x0FF, 0x0FFFF, 0x0FFFFFF};     \r\n \r\n\r\n  if (hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* input/output parameters check */\r\n    if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)\r\n    {\r\n      if ((hcryp->Init.Header != NULL) && (hcryp->Init.HeaderSize == 0))\r\n      {\r\n        return  HAL_ERROR;\r\n      }\r\n#if defined(AES_CR_NPBLB) \r\n      if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC)\r\n#else       \r\n      if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)\r\n#endif         \r\n      {\r\n        /* In case of CMAC header phase resumption, we can have pInputData = NULL and  Size = 0 */\r\n        if (((pInputData != NULL) && (Size == 0)) || ((pInputData == NULL) && (Size != 0)))\r\n        {\r\n          return  HAL_ERROR;\r\n        }\r\n      }      \r\n    }\r\n    else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)\r\n    {   \r\n      if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0))\r\n      {\r\n        return  HAL_ERROR;\r\n      }\r\n    }\r\n    else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE)\r\n    {\r\n      if (pOutputData == NULL)\r\n      {\r\n        return  HAL_ERROR;\r\n      }\r\n#if defined(AES_CR_NPBLB)  \r\n      if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC) && (pInputData == NULL))\r\n#else    \r\n      if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (pInputData == NULL))\r\n#endif \r\n      {\r\n        return  HAL_ERROR;\r\n      }\r\n    }\r\n    \r\n    \r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hcryp);\r\n                           \r\n    /* Enable Computation Complete Flag and Error Interrupts */\r\n    __HAL_CRYP_ENABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);\r\n\r\n\r\n\r\n    /*==============================================*/\r\n    /* GCM/GMAC (or CCM when applicable) init phase */\r\n    /*==============================================*/\r\n    if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE)\r\n    {    \r\n    /* In case of init phase, the input data (Key and Initialization Vector) have \r\n       already been entered during the initialization process. Therefore, the\r\n       software just waits for the CCF interrupt to be raised and which will\r\n       be handled by CRYP_AES_Auth_IT() API. */\r\n    }\r\n    /*=====================================*/\r\n    /* GCM/GMAC or (CCM/)CMAC header phase */\r\n    /*=====================================*/   \r\n    else if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)\r\n    {\r\n    \r\n#if defined(AES_CR_NPBLB)   \r\n      if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC)\r\n#else    \r\n      if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)\r\n#endif      \r\n      {\r\n        /* In case of CMAC, B blocks are first entered, before the header.\r\n           Therefore, B blocks and the header are entered back-to-back\r\n           as if it was only one single block. \r\n           However, in case of resumption after suspension, if all the\r\n           B blocks have been entered (in that case, Size = 0), only the\r\n           remainder of the non-processed header bytes are entered. */\r\n          if (Size != 0)\r\n          {\r\n            hcryp->CrypInCount = Size + hcryp->Init.HeaderSize;\r\n            hcryp->pCrypInBuffPtr = pInputData;\r\n          }\r\n          else\r\n          {\r\n            hcryp->CrypInCount = hcryp->Init.HeaderSize;\r\n            hcryp->pCrypInBuffPtr = hcryp->Init.Header;\r\n          }\r\n      }\r\n      else\r\n      {\r\n        /* Get the header addresses and sizes */\r\n        hcryp->CrypInCount = hcryp->Init.HeaderSize;\r\n        hcryp->pCrypInBuffPtr = hcryp->Init.Header;\r\n      }    \r\n    \r\n      inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n      \r\n      /* Set header phase; for GCM or GMAC, set data-byte at this point */\r\n      if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)\r\n      {\r\n        MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH|AES_CR_DATATYPE, CRYP_HEADER_PHASE|hcryp->Init.DataType);\r\n      }\r\n      else\r\n      {\r\n        MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_HEADER_PHASE);\r\n      }\r\n       \r\n      /* Enable the Peripheral */\r\n      __HAL_CRYP_ENABLE();\r\n    \r\n      /* Increment/decrement instance pointer/counter */\r\n      if (hcryp->CrypInCount == 0)\r\n      {\r\n        /* Case of no header */\r\n        hcryp->State = HAL_CRYP_STATE_READY; \r\n        return HAL_OK;        \r\n      }\r\n      else if (hcryp->CrypInCount < 16)\r\n      {\r\n        hcryp->CrypInCount = 0;\r\n        addhoc_process = 1;  \r\n        difflength = (uint32_t) (hcryp->Init.HeaderSize);\r\n        difflengthmod4 = difflength%4;              \r\n      }\r\n      else\r\n      {\r\n        hcryp->pCrypInBuffPtr += 16;\r\n        hcryp->CrypInCount -= 16;\r\n      }\r\n      \r\n      \r\n#if defined(AES_CR_NPBLB)    \r\n      if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC)\r\n#else     \r\n      if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)\r\n#endif      \r\n      { \r\n        if (hcryp->CrypInCount == hcryp->Init.HeaderSize)\r\n        {\r\n          /* All B blocks will have been entered after the next\r\n             four DINR writing, so point at header buffer for\r\n             the next iteration */\r\n          hcryp->pCrypInBuffPtr = hcryp->Init.Header;\r\n        }\r\n      }       \r\n    \r\n      /* Enter header first block to initiate the process\r\n         in the Data Input register */\r\n      if (addhoc_process == 0)\r\n      { \r\n        /* Header has size equal or larger than 128 bits */        \r\n        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n        inputaddr+=4;\r\n        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n        inputaddr+=4;\r\n        hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);\r\n        inputaddr+=4;\r\n        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n      }\r\n      else\r\n      {\r\n        /* Header has size less than 128 bits */ \r\n        /* Enter complete words when possible */\r\n        for(index=0; index < (difflength/4); index ++)\r\n        {\r\n          /* Write the Input block in the Data Input register */\r\n          hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n          inputaddr+=4;\r\n        }\r\n        /* Enter incomplete word padded with zeroes if applicable \r\n          (case of header length not a multiple of 32-bits) */\r\n        if (difflengthmod4 != 0)\r\n        {         \r\n          hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]);\r\n        }         \r\n        /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */\r\n        for(index=0; index < (4 - ((difflength+3)/4)); index ++)         \r\n        {\r\n          hcryp->Instance->DINR = 0;\r\n        }                 \r\n      \r\n      }\r\n    }\r\n    /*============================================*/\r\n    /* GCM (or CCM when applicable) payload phase */\r\n    /*============================================*/\r\n    else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)\r\n    {\r\n      /* Get the buffer addresses and sizes */\r\n      hcryp->CrypInCount = Size;\r\n      hcryp->pCrypInBuffPtr = pInputData;\r\n      hcryp->pCrypOutBuffPtr = pOutputData;\r\n      hcryp->CrypOutCount = Size; \r\n    \r\n      inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n      \r\n      MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_GCM_PAYLOAD_PHASE);\r\n       \r\n      /* if the header phase has been bypassed, AES must be enabled again */\r\n      if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER)\r\n      {\r\n        __HAL_CRYP_ENABLE();  \r\n      }\r\n    \r\n     /* Specific handling to manage payload size less than 128 bits */\r\n      if (Size < 16)\r\n      {\r\n#if defined(AES_CR_NPBLB)  \r\n        /* In case of GCM encryption or CCM decryption, specify the number of padding\r\n           bytes in last block of payload */\r\n        if (READ_BIT(hcryp->Instance->CR, AES_CR_GCMPH) == CRYP_PAYLOAD_PHASE)\r\n        {\r\n          if (((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_GCM_GMAC)\r\n               &&  (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_ENCRYPT))   \r\n           ||  ((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_CCM_CMAC)\r\n               &&  (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_DECRYPT)))\r\n          {\r\n            /* Set NPBLB field in writing the number of padding bytes \r\n               for the last block of payload */\r\n            MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 16 - difflength);\r\n          }\r\n        }\r\n#else\r\n        /* Software workaround applied to GCM encryption only */ \r\n        if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT)\r\n        {\r\n          /* Change the mode configured in CHMOD bits of CR register to select CTR mode */   \r\n          __HAL_CRYP_SET_CHAININGMODE(CRYP_CHAINMODE_AES_CTR);\r\n        } \r\n#endif        \r\n\r\n\r\n        /* Set hcryp->CrypInCount to 0 (no more data to enter) */ \r\n        hcryp->CrypInCount = 0;  \r\n\r\n        /*  Insert the last block (which size is inferior to 128 bits) padded with zeroes, \r\n            to have a complete block of 128 bits */              \r\n        difflength = (uint32_t) (Size);\r\n        difflengthmod4 = difflength%4;                 \r\n        /*  Insert the last block (which size is inferior to 128 bits) padded with zeroes \r\n            to have a complete block of 128 bits */\r\n        for(index=0; index < (difflength/4); index ++)\r\n        {\r\n          /* Write the Input block in the Data Input register */\r\n          hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n          inputaddr+=4;\r\n        }\r\n        /* If required, manage input data size not multiple of 32 bits */\r\n        if (difflengthmod4 != 0)\r\n        {         \r\n          hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]);\r\n        }         \r\n        /* Wrap-up in padding with zero-words if applicable */\r\n        for(index=0; index < (4 - ((difflength+3)/4)); index ++)        \r\n        {\r\n          hcryp->Instance->DINR = 0;\r\n        }               \r\n      }\r\n      else\r\n      {        \r\n        /* Increment/decrement instance pointer/counter */\r\n        hcryp->pCrypInBuffPtr += 16;\r\n        hcryp->CrypInCount -= 16;\r\n        \r\n        /* Enter payload first block to initiate the process\r\n           in the Data Input register */\r\n        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n        inputaddr+=4;\r\n        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n        inputaddr+=4;\r\n        hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);\r\n        inputaddr+=4;\r\n        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n      }\r\n    }\r\n    /*====================================*/\r\n    /* GCM/GMAC or (CCM/)CMAC final phase */\r\n    /*====================================*/\r\n    else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE)\r\n    {\r\n       hcryp->pCrypOutBuffPtr = pOutputData;\r\n       \r\n#if defined(AES_CR_NPBLB)   \r\n     /* By default, clear NPBLB field */\r\n      CLEAR_BIT(hcryp->Instance->CR, AES_CR_NPBLB);\r\n#endif         \r\n       \r\n       MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_FINAL_PHASE);\r\n       \r\n      /* if the header and payload phases have been bypassed, AES must be enabled again */\r\n      if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER)\r\n      {\r\n        __HAL_CRYP_ENABLE();  \r\n      }\r\n      \r\n      if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)\r\n      {             \r\n        headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */\r\n        inputlength = Size * 8;                    /* Input length in bits */ \r\n        /* Write the number of bits in the header on 64 bits followed by the number\r\n           of bits in the payload on 64 bits as well */\r\n        if(hcryp->Init.DataType == CRYP_DATATYPE_1B)\r\n        {\r\n          hcryp->Instance->DINR = __RBIT((headerlength)>>32);\r\n          hcryp->Instance->DINR = __RBIT(headerlength);\r\n          hcryp->Instance->DINR = __RBIT((inputlength)>>32);\r\n          hcryp->Instance->DINR = __RBIT(inputlength);\r\n        }\r\n        else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)\r\n        {\r\n          hcryp->Instance->DINR = __REV((headerlength)>>32);\r\n          hcryp->Instance->DINR = __REV(headerlength);\r\n          hcryp->Instance->DINR = __REV((inputlength)>>32);\r\n          hcryp->Instance->DINR = __REV(inputlength);\r\n        }\r\n        else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)\r\n        {\r\n          hcryp->Instance->DINR = __ROR((headerlength)>>32, 16);\r\n          hcryp->Instance->DINR = __ROR(headerlength, 16);\r\n          hcryp->Instance->DINR = __ROR((inputlength)>>32, 16);\r\n          hcryp->Instance->DINR = __ROR(inputlength, 16);             \r\n        }\r\n        else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)\r\n        {\r\n          hcryp->Instance->DINR = (uint32_t)(headerlength>>32);\r\n          hcryp->Instance->DINR = (uint32_t)(headerlength);\r\n          hcryp->Instance->DINR = (uint32_t)(inputlength>>32);\r\n          hcryp->Instance->DINR = (uint32_t)(inputlength);\r\n        }\r\n      }\r\n#if !defined(AES_CR_NPBLB)         \r\n      else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)\r\n      {\r\n        inputaddr  = (uint32_t)pInputData;\r\n        /* Enter the last block made of a 128-bit value formatted\r\n           from the original B0 packet. */\r\n        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n        inputaddr+=4;\r\n        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n        inputaddr+=4;\r\n        hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);\r\n        inputaddr+=4;\r\n        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n        inputaddr+=4;\r\n      }\r\n#endif      \r\n    }\r\n    /*=================================================*/\r\n    /* case incorrect hcryp->Init.GCMCMACPhase setting */\r\n    /*=================================================*/\r\n    else\r\n    {\r\n      hcryp->State = HAL_CRYP_STATE_ERROR; \r\n      return HAL_ERROR;\r\n    }\r\n  \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n\r\n\r\n\r\n/**\r\n  * @brief  Carry out in DMA mode the authentication tag generation as well as the ciphering or deciphering \r\n  *         operation according to hcryp->Init structure fields. \r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pInputData \r\n  *         - pointer to payload data in GCM payload phase,\r\n  *         - pointer to B0 block in CMAC header phase,\r\n  *         - pointer to C block in CMAC final phase.\r\n  *         - Parameter is meaningless in case of GCM/GMAC init, header and final phases.        \r\n  * @param  Size \r\n  *         - length of the input payload data buffer in bytes,\r\n  *         - length of B block (in bytes) in CMAC header phase,\r\n  *         - length of C block (in bytes) in CMAC final phase.   \r\n  *         - Parameter is meaningless in case of GCM/GMAC init and header phases.         \r\n  * @param  pOutputData \r\n  *         - pointer to plain or cipher text in GCM payload phase,   \r\n  *         - pointer to authentication tag in GCM/GMAC and CMAC final phases.\r\n  *         - Parameter is meaningless in case of GCM/GMAC init and header phases\r\n  *           and in case of CMAC header phase.\r\n  * @note   Supported operating modes are encryption and decryption, supported chaining modes are GCM, GMAC and CMAC.\r\n  * @note   Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes \r\n  *         can be skipped by the user if so required.\r\n  * @note   pInputData and pOutputData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP.            \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData)\r\n{\r\n  uint32_t inputaddr      = 0;\r\n  uint32_t outputaddr     = 0;\r\n  uint32_t tagaddr        = 0;\r\n  uint64_t headerlength   = 0;\r\n  uint64_t inputlength    = 0;\r\n  uint64_t payloadlength  = 0;\r\n       \r\n  \r\n  if (hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* input/output parameters check */\r\n    if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)\r\n    {\r\n      if ((hcryp->Init.Header != NULL) && (hcryp->Init.HeaderSize == 0))\r\n      {\r\n        return  HAL_ERROR;\r\n      }\r\n#if defined(AES_CR_NPBLB) \r\n      if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC)\r\n#else       \r\n      if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)\r\n#endif  \r\n      {\r\n        if ((pInputData == NULL) || (Size == 0))\r\n        {\r\n          return  HAL_ERROR;\r\n        }\r\n      }      \r\n    }\r\n    else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)\r\n    {   \r\n      if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0))\r\n      {\r\n        return  HAL_ERROR;\r\n      }\r\n    }\r\n    else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE)\r\n    {\r\n      if (pOutputData == NULL)\r\n      {\r\n        return  HAL_ERROR;\r\n      }\r\n#if defined(AES_CR_NPBLB)  \r\n      if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC) && (pInputData == NULL))\r\n#else    \r\n      if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC) && (pInputData == NULL))\r\n#endif \r\n      {\r\n        return  HAL_ERROR;\r\n      }\r\n    }\r\n    \r\n    \r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n  \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n    /*==============================================*/\r\n    /* GCM/GMAC (or CCM when applicable) init phase */\r\n    /*==============================================*/\r\n    /* In case of init phase, the input data (Key and Initialization Vector) have \r\n       already been entered during the initialization process. No DMA transfer is\r\n       required at that point therefore, the software just waits for the CCF flag \r\n       to be raised. */\r\n    if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE)\r\n    {\r\n      /* just wait for hash computation */\r\n      if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)  \r\n      { \r\n        hcryp->State = HAL_CRYP_STATE_READY;        \r\n        __HAL_UNLOCK(hcryp);\r\n        return HAL_TIMEOUT;\r\n      }\r\n      \r\n      /* Clear CCF Flag */\r\n      __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);\r\n      /* Mark that the initialization phase is over */\r\n      hcryp->Phase = HAL_CRYP_PHASE_INIT_OVER;\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n    }\r\n    /*===============================*/\r\n    /* GCM/GMAC or CMAC header phase */\r\n    /*===============================*/     \r\n    else if (hcryp->Init.GCMCMACPhase == CRYP_GCMCMAC_HEADER_PHASE)\r\n    {\r\n      /* Set header phase; for GCM or GMAC, set data-byte at this point */\r\n      if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)\r\n      {\r\n        MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH|AES_CR_DATATYPE, CRYP_GCMCMAC_HEADER_PHASE|hcryp->Init.DataType);\r\n      }\r\n      else\r\n      {\r\n        MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_GCMCMAC_HEADER_PHASE);\r\n      }\r\n      \r\n#if !defined(AES_CR_NPBLB)         \r\n      /* enter first B0 block in polling mode (no DMA transfer for B0) */\r\n      if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)\r\n      {\r\n         /* Enable the CRYP peripheral */\r\n        __HAL_CRYP_ENABLE();\r\n  \r\n        inputaddr  = (uint32_t)pInputData;\r\n        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n        inputaddr+=4;\r\n        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n        inputaddr+=4;\r\n        hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);\r\n        inputaddr+=4;\r\n        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n      \r\n        if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)  \r\n        { \r\n          hcryp->State = HAL_CRYP_STATE_READY;        \r\n          __HAL_UNLOCK(hcryp);\r\n          return HAL_TIMEOUT;\r\n        }\r\n        /* Clear CCF Flag */\r\n        __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);\r\n      }\r\n#endif      \r\n      \r\n      /* No header case */\r\n      if (hcryp->Init.Header == NULL)\r\n      {\r\n        hcryp->State = HAL_CRYP_STATE_READY;   \r\n        /* Mark that the header phase is over */\r\n        hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER; \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hcryp);\r\n  \r\n        return HAL_OK;             \r\n      }\r\n      \r\n      inputaddr = (uint32_t)hcryp->Init.Header;\r\n      if ((hcryp->Init.HeaderSize % 16) != 0)\r\n      {\r\n\r\n        if (hcryp->Init.HeaderSize < 16)        \r\n        {          \r\n          CRYP_Padding(hcryp, (uint32_t) (hcryp->Init.HeaderSize), CRYP_POLLING_OFF);     \r\n          \r\n          hcryp->State = HAL_CRYP_STATE_READY;   \r\n          /* Mark that the header phase is over */\r\n          hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER;  \r\n          \r\n          /* CCF flag indicating header phase AES processing completion \r\n             will be checked at the start of the next phase:\r\n            - payload phase (GCM / CCM when applicable)\r\n            - final phase (GMAC or CMAC).  */                     \r\n        }\r\n        else\r\n        {\r\n          /* Local variable headerlength is a number of bytes multiple of 128 bits,\r\n            remaining header data (if any) are handled after this loop */\r\n          headerlength =  (((hcryp->Init.HeaderSize)/16)*16) ;         \r\n          /* Store the ending transfer point */\r\n          hcryp->pCrypInBuffPtr = hcryp->Init.Header + headerlength;\r\n          hcryp->CrypInCount = (uint32_t)(hcryp->Init.HeaderSize - headerlength); /* remainder */\r\n        \r\n          /* Set the input and output addresses and start DMA transfer */ \r\n          /* (incomplete DMA transfer, will be wrapped up after completion of\r\n             the first one (initiated here) with data padding */\r\n          CRYP_GCMCMAC_SetDMAConfig(hcryp, inputaddr, headerlength, 0);\r\n        }                          \r\n      }\r\n      else\r\n      {\r\n        hcryp->CrypInCount = 0;\r\n        /* Set the input address and start DMA transfer */ \r\n        CRYP_GCMCMAC_SetDMAConfig(hcryp, inputaddr, hcryp->Init.HeaderSize, 0);            \r\n      }\r\n      \r\n\r\n    }\r\n    /*============================================*/\r\n    /* GCM (or CCM when applicable) payload phase */\r\n    /*============================================*/\r\n    else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)\r\n    {\r\n      /* Coming from header phase, wait for CCF flag to be raised \r\n          if header present and fed to the IP in the previous phase */\r\n      if (hcryp->Init.Header != NULL)\r\n      {\r\n        if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)  \r\n        { \r\n          hcryp->State = HAL_CRYP_STATE_READY;        \r\n          __HAL_UNLOCK(hcryp);\r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n      else\r\n      {\r\n        /* Enable the Peripheral since wasn't in header phase (no header case) */\r\n        __HAL_CRYP_ENABLE();\r\n      }\r\n      /* Clear CCF Flag */\r\n      __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);     \r\n    \r\n      MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PAYLOAD_PHASE);\r\n      \r\n      /* Specific handling to manage payload size less than 128 bits */ \r\n      if ((Size % 16) != 0)\r\n      {\r\n        inputaddr  = (uint32_t)pInputData;\r\n        outputaddr = (uint32_t)pOutputData;      \r\n        if (Size < 16)\r\n        {\r\n          /* Block is now entered in polling mode, no actual gain in resorting to DMA */\r\n          hcryp->pCrypInBuffPtr  =  (uint8_t *)inputaddr;\r\n          hcryp->pCrypOutBuffPtr =  (uint8_t *)outputaddr;\r\n            \r\n          CRYP_Padding(hcryp, (uint32_t)Size, CRYP_POLLING_ON); \r\n          \r\n          /* Change the CRYP state to ready */\r\n          hcryp->State = HAL_CRYP_STATE_READY;\r\n          /* Mark that the payload phase is over */\r\n          hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; \r\n  \r\n          /* Call output data transfer complete callback */\r\n          HAL_CRYP_OutCpltCallback(hcryp);\r\n        }\r\n        else\r\n        {\r\n          payloadlength = (Size/16) * 16;          \r\n          \r\n          /* Store the ending transfer points */\r\n          hcryp->pCrypInBuffPtr = pInputData + payloadlength;\r\n          hcryp->pCrypOutBuffPtr = pOutputData + payloadlength;\r\n          hcryp->CrypInCount = (uint32_t)(Size - payloadlength); /* remainder */\r\n        \r\n          /* Set the input and output addresses and start DMA transfer */ \r\n          /* (incomplete DMA transfer, will be wrapped up with data padding  \r\n             after completion of the one initiated here) */\r\n          CRYP_GCMCMAC_SetDMAConfig(hcryp, inputaddr, payloadlength, outputaddr);                      \r\n        }\r\n      }\r\n      else\r\n      { \r\n        hcryp->CrypInCount = 0;                          \r\n        inputaddr  = (uint32_t)pInputData;\r\n        outputaddr = (uint32_t)pOutputData;\r\n        \r\n        /* Set the input and output addresses and start DMA transfer */ \r\n        CRYP_GCMCMAC_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);         \r\n      }  \r\n    }\r\n    /*====================================*/\r\n    /* GCM/GMAC or (CCM/)CMAC final phase */\r\n    /*====================================*/\r\n    else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE)\r\n    {\r\n      /* If coming from header phase (GMAC or CMAC case), \r\n         wait for CCF flag to be raised */\r\n      if (READ_BIT(hcryp->Instance->CR, AES_CR_GCMPH) == CRYP_HEADER_PHASE)\r\n      {   \r\n        if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)  \r\n        { \r\n          hcryp->State = HAL_CRYP_STATE_READY;        \r\n          __HAL_UNLOCK(hcryp);\r\n          return HAL_TIMEOUT;\r\n        }\r\n        /* Clear CCF Flag */\r\n        __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);\r\n      }        \r\n      \r\n      tagaddr = (uint32_t)pOutputData;\r\n      \r\n      MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_FINAL_PHASE);\r\n      \r\n      /* if the header and payload phases have been bypassed, AES must be enabled again */\r\n      if (hcryp->Phase == HAL_CRYP_PHASE_INIT_OVER)\r\n      {\r\n        __HAL_CRYP_ENABLE();  \r\n      }\r\n      \r\n      if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC)\r\n      {\r\n        headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */\r\n        inputlength = Size * 8;  /* input length in bits */ \r\n        /* Write the number of bits in the header on 64 bits followed by the number\r\n           of bits in the payload on 64 bits as well */\r\n        if(hcryp->Init.DataType == CRYP_DATATYPE_1B)\r\n        {\r\n          hcryp->Instance->DINR = __RBIT((headerlength)>>32);\r\n          hcryp->Instance->DINR = __RBIT(headerlength);\r\n          hcryp->Instance->DINR = __RBIT((inputlength)>>32);\r\n          hcryp->Instance->DINR = __RBIT(inputlength);\r\n        }\r\n        else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)\r\n        {\r\n          hcryp->Instance->DINR = __REV((headerlength)>>32);\r\n          hcryp->Instance->DINR = __REV(headerlength);\r\n          hcryp->Instance->DINR = __REV((inputlength)>>32);\r\n          hcryp->Instance->DINR = __REV(inputlength);\r\n        }\r\n        else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)\r\n        {\r\n          hcryp->Instance->DINR = __ROR((headerlength)>>32, 16);\r\n          hcryp->Instance->DINR = __ROR(headerlength, 16);\r\n          hcryp->Instance->DINR = __ROR((inputlength)>>32, 16);\r\n          hcryp->Instance->DINR = __ROR(inputlength, 16);            \r\n        }\r\n        else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)\r\n        {\r\n          hcryp->Instance->DINR = (uint32_t)(headerlength>>32);\r\n          hcryp->Instance->DINR = (uint32_t)(headerlength);\r\n          hcryp->Instance->DINR = (uint32_t)(inputlength>>32);\r\n          hcryp->Instance->DINR = (uint32_t)(inputlength);\r\n        }\r\n      }\r\n#if !defined(AES_CR_NPBLB)           \r\n      else if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)\r\n      {\r\n        __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);\r\n        \r\n        inputaddr  = (uint32_t)pInputData;\r\n        /* Enter the last block made of a 128-bit value formatted\r\n           from the original B0 packet. */\r\n        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n        inputaddr+=4;\r\n        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n        inputaddr+=4;\r\n        hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);\r\n        inputaddr+=4;\r\n        hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n        inputaddr+=4;\r\n      }\r\n#endif      \r\n      \r\n      /* No DMA transfer is required at that point therefore, the software \r\n         just waits for the CCF flag to be raised. */\r\n      if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)  \r\n      { \r\n          hcryp->State = HAL_CRYP_STATE_READY;        \r\n          __HAL_UNLOCK(hcryp);\r\n          return HAL_TIMEOUT;\r\n      }\r\n      /* Clear CCF Flag */\r\n      __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);\r\n      /* Read the Auth TAG in the IN FIFO */\r\n      *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;\r\n      tagaddr+=4;\r\n      *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;\r\n      tagaddr+=4;\r\n      *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;\r\n      tagaddr+=4;\r\n      *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR;\r\n  \r\n      /* Mark that the final phase is over */\r\n      hcryp->Phase = HAL_CRYP_PHASE_FINAL_OVER;\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Disable the Peripheral */\r\n      __HAL_CRYP_DISABLE();\r\n    }\r\n    /*=================================================*/\r\n    /* case incorrect hcryp->Init.GCMCMACPhase setting */\r\n    /*=================================================*/\r\n    else\r\n    {\r\n      hcryp->State = HAL_CRYP_STATE_ERROR;\r\n      __HAL_UNLOCK(hcryp); \r\n      return HAL_ERROR;\r\n    }    \r\n  \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hcryp);\r\n  \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRYPEx_Exported_Functions_Group3 AES suspension/resumption functions \r\n *  @brief   Extended processing functions. \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                    ##### AES extended suspension and resumption functions #####\r\n  ==============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) save in memory the Initialization Vector, the Key registers, the Control register or\r\n          the Suspend registers when a process is suspended by a higher priority message\r\n      (+) write back in CRYP hardware block the saved values listed above when the suspended\r\n          lower priority message processing is resumed.     \r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n\r\n/**\r\n  * @brief  In case of message processing suspension, read the Initialization Vector. \r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module.    \r\n  * @param  Output Pointer to the buffer containing the saved Initialization Vector.\r\n  * @note   This value has to be stored for reuse by writing the AES_IVRx registers\r\n  *         as soon as the interrupted processing has to be resumed.\r\n  *         Applicable to all chaining modes.    \r\n  * @note   AES must be disabled when reading or resetting the IV values.   \r\n  * @retval None\r\n  */\r\nvoid HAL_CRYPEx_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output)\r\n{\r\n  uint32_t outputaddr = (uint32_t)Output;\r\n    \r\n  *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR3);\r\n  outputaddr+=4;\r\n  *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR2);\r\n  outputaddr+=4;\r\n  *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR1);\r\n  outputaddr+=4;\r\n  *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->IVR0);\r\n}\r\n\r\n/**\r\n  * @brief  In case of message processing resumption, rewrite the Initialization\r\n  *         Vector in the AES_IVRx registers.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module.      \r\n  * @param  Input Pointer to the buffer containing the saved Initialization Vector to\r\n  *         write back in the CRYP hardware block. \r\n  * @note   Applicable to all chaining modes.       \r\n  * @note   AES must be disabled when reading or resetting the IV values.     \r\n  * @retval None\r\n  */\r\nvoid HAL_CRYPEx_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input)\r\n{\r\n  uint32_t ivaddr = (uint32_t)Input;\r\n  \r\n  hcryp->Instance->IVR3 = __REV(*(uint32_t*)(ivaddr));\r\n  ivaddr+=4;\r\n  hcryp->Instance->IVR2 = __REV(*(uint32_t*)(ivaddr));\r\n  ivaddr+=4;\r\n  hcryp->Instance->IVR1 = __REV(*(uint32_t*)(ivaddr));\r\n  ivaddr+=4;\r\n  hcryp->Instance->IVR0 = __REV(*(uint32_t*)(ivaddr));\r\n}\r\n\r\n\r\n/**\r\n  * @brief  In case of message GCM/GMAC or CMAC processing suspension, read the Suspend Registers.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module.  \r\n  * @param  Output Pointer to the buffer containing the saved Suspend Registers.\r\n  * @note   These values have to be stored for reuse by writing back the AES_SUSPxR registers\r\n  *         as soon as the interrupted processing has to be resumed.       \r\n  * @retval None\r\n  */\r\nvoid HAL_CRYPEx_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output)\r\n{\r\n  uint32_t outputaddr = (uint32_t)Output;\r\n  \r\n  /* In case of GCM payload phase encryption, check that suspension can be carried out */\r\n  if (READ_BIT(hcryp->Instance->CR, (AES_CR_GCMPH|AES_CR_MODE)) == (CRYP_GCM_PAYLOAD_PHASE|CRYP_ALGOMODE_ENCRYPT))\r\n  {\r\n    /* Ensure that Busy flag is reset */\r\n    if(CRYP_WaitOnBusyFlagReset(hcryp, CRYP_BUSY_TIMEOUTVALUE) != HAL_OK)  \r\n    { \r\n      hcryp->ErrorCode |= HAL_CRYP_BUSY_ERROR;\r\n      hcryp->State = HAL_CRYP_STATE_ERROR;\r\n              \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);  \r\n    \r\n      HAL_CRYP_ErrorCallback(hcryp);\r\n      return ;\r\n    }\r\n  } \r\n    \r\n  *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP7R);\r\n  outputaddr+=4;\r\n  *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP6R);\r\n  outputaddr+=4;\r\n  *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP5R);\r\n  outputaddr+=4;\r\n  *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP4R);\r\n  outputaddr+=4;\r\n  *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP3R);\r\n  outputaddr+=4;\r\n  *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP2R);\r\n  outputaddr+=4;\r\n  *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP1R); \r\n  outputaddr+=4;\r\n  *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->SUSP0R);   \r\n}\r\n\r\n/**\r\n  * @brief  In case of message GCM/GMAC or CMAC processing resumption, rewrite the Suspend\r\n  *         Registers in the AES_SUSPxR registers.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module.    \r\n  * @param  Input Pointer to the buffer containing the saved suspend registers to\r\n  *         write back in the CRYP hardware block. \r\n  * @retval None\r\n  */\r\nvoid HAL_CRYPEx_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input)\r\n{\r\n  uint32_t ivaddr = (uint32_t)Input;\r\n  \r\n  hcryp->Instance->SUSP7R = __REV(*(uint32_t*)(ivaddr));\r\n  ivaddr+=4;\r\n  hcryp->Instance->SUSP6R = __REV(*(uint32_t*)(ivaddr));\r\n  ivaddr+=4;\r\n  hcryp->Instance->SUSP5R = __REV(*(uint32_t*)(ivaddr));\r\n  ivaddr+=4;\r\n  hcryp->Instance->SUSP4R = __REV(*(uint32_t*)(ivaddr));\r\n  ivaddr+=4;\r\n  hcryp->Instance->SUSP3R = __REV(*(uint32_t*)(ivaddr));\r\n  ivaddr+=4;\r\n  hcryp->Instance->SUSP2R = __REV(*(uint32_t*)(ivaddr));\r\n  ivaddr+=4;\r\n  hcryp->Instance->SUSP1R = __REV(*(uint32_t*)(ivaddr));\r\n  ivaddr+=4;\r\n  hcryp->Instance->SUSP0R = __REV(*(uint32_t*)(ivaddr));  \r\n}\r\n\r\n\r\n/**\r\n  * @brief  In case of message GCM/GMAC or CMAC processing suspension, read the Key Registers.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module.   \r\n  * @param  Output Pointer to the buffer containing the saved Key Registers. \r\n  * @param  KeySize Indicates the key size (128 or 256 bits).\r\n  * @note   These values have to be stored for reuse by writing back the AES_KEYRx registers\r\n  *         as soon as the interrupted processing has to be resumed.           \r\n  * @retval None\r\n  */\r\nvoid HAL_CRYPEx_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t KeySize)\r\n{\r\n  uint32_t keyaddr = (uint32_t)Output;\r\n  \r\n  if (KeySize == CRYP_KEYSIZE_256B)\r\n  {\r\n    *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR7);\r\n    keyaddr+=4;\r\n    *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR6);\r\n    keyaddr+=4;\r\n    *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR5);\r\n    keyaddr+=4;\r\n    *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR4);\r\n    keyaddr+=4;                 \r\n  }  \r\n  \r\n  *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR3);\r\n  keyaddr+=4;\r\n  *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR2);\r\n  keyaddr+=4;\r\n  *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR1);\r\n  keyaddr+=4;\r\n  *(uint32_t*)(keyaddr) = __REV(hcryp->Instance->KEYR0); \r\n}\r\n\r\n/**\r\n  * @brief  In case of message GCM/GMAC or CMAC processing resumption, rewrite the Key\r\n  *         Registers in the AES_KEYRx registers.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module.   \r\n  * @param  Input Pointer to the buffer containing the saved key registers to\r\n  *         write back in the CRYP hardware block. \r\n  * @param  KeySize Indicates the key size (128 or 256 bits)     \r\n  * @retval None\r\n  */\r\nvoid HAL_CRYPEx_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint32_t KeySize)\r\n{  \r\n  uint32_t keyaddr = (uint32_t)Input;\r\n  \r\n  if (KeySize == CRYP_KEYSIZE_256B)\r\n  {\r\n    hcryp->Instance->KEYR7 = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->KEYR6 = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->KEYR5 = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->KEYR4 = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;      \r\n  }  \r\n  \r\n    hcryp->Instance->KEYR3 = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->KEYR2 = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->KEYR1 = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->KEYR0 = __REV(*(uint32_t*)(keyaddr));    \r\n}\r\n\r\n\r\n/**\r\n  * @brief  In case of message GCM/GMAC or CMAC processing suspension, read the Control Register.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module.   \r\n  * @param  Output Pointer to the buffer containing the saved Control Register.\r\n  * @note   This values has to be stored for reuse by writing back the AES_CR register\r\n  *         as soon as the interrupted processing has to be resumed.          \r\n  * @retval None\r\n  */\r\nvoid HAL_CRYPEx_Read_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Output)\r\n{\r\n  *(uint32_t*)(Output) = hcryp->Instance->CR;    \r\n}\r\n\r\n/**\r\n  * @brief  In case of message GCM/GMAC or CMAC processing resumption, rewrite the Control\r\n  *         Registers in the AES_CR register.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module.   \r\n  * @param  Input Pointer to the buffer containing the saved Control Register to\r\n  *         write back in the CRYP hardware block.   \r\n  * @retval None\r\n  */\r\nvoid HAL_CRYPEx_Write_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Input)\r\n{  \r\n  hcryp->Instance->CR = *(uint32_t*)(Input);\r\n  /* At the same time, set handle state back to READY to be able to resume the AES calculations \r\n     without the processing APIs returning HAL_BUSY when called. */\r\n  hcryp->State        = HAL_CRYP_STATE_READY;\r\n}\r\n\r\n/**\r\n  * @brief  Request CRYP processing suspension when in polling or interruption mode.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module. \r\n  * @note   Set the handle field SuspendRequest to the appropriate value so that \r\n  *         the on-going CRYP processing is suspended as soon as the required \r\n  *         conditions are met.\r\n  * @note   It is advised not to suspend the CRYP processing when the DMA controller \r\n  *         is managing the data transfer     \r\n  * @retval None\r\n  */\r\nvoid HAL_CRYPEx_ProcessSuspend(CRYP_HandleTypeDef *hcryp)  \r\n{\r\n  /* Set Handle Suspend Request field */\r\n  hcryp->SuspendRequest = HAL_CRYP_SUSPEND;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup CRYPEx_Private_Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  DMA CRYP Input Data process complete callback\r\n  *         for GCM, GMAC or CMAC chainging modes.\r\n  * @note   Specific setting of hcryp fields are required only\r\n  *         in the case of header phase where no output data DMA\r\n  *         transfer is on-going (only input data transfer is enabled\r\n  *         in such a case).      \r\n  * @param  hdma DMA handle.\r\n  * @retval None\r\n  */\r\nstatic void CRYP_GCMCMAC_DMAInCplt(DMA_HandleTypeDef *hdma)  \r\n{\r\n  uint32_t difflength     = 0;\r\n  \r\n  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n  \r\n  /* Disable the DMA transfer for input request  */\r\n  CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);\r\n\r\n  if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)\r\n  { \r\n  \r\n    if (hcryp->CrypInCount != 0)\r\n    {\r\n      /* Last block is now entered in polling mode, no actual gain in resorting to DMA */\r\n      difflength = hcryp->CrypInCount;\r\n      hcryp->CrypInCount = 0;\r\n      \r\n      CRYP_Padding(hcryp, difflength, CRYP_POLLING_OFF);      \r\n    }\r\n    hcryp->State = HAL_CRYP_STATE_READY;   \r\n    /* Mark that the header phase is over */\r\n    hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER;\r\n  }\r\n  /* CCF flag indicating header phase AES processing completion \r\n     will be checked at the start of the next phase:\r\n     - payload phase (GCM or CCM when applicable)\r\n     - final phase (GMAC or CMAC).\r\n    This allows to avoid the Wait on Flag within the IRQ handling.  */\r\n  \r\n  /* Call input data transfer complete callback */\r\n  HAL_CRYP_InCpltCallback(hcryp);\r\n}\r\n\r\n/**\r\n  * @brief  DMA CRYP Output Data process complete callback\r\n  *         for GCM, GMAC or CMAC chainging modes.\r\n  * @note   This callback is called only in the payload phase.  \r\n  * @param  hdma DMA handle.\r\n  * @retval None\r\n  */\r\nstatic void CRYP_GCMCMAC_DMAOutCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  uint32_t difflength     = 0;\r\n  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n  \r\n  /* Disable the DMA transfer for output request */\r\n  CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);\r\n\r\n  /* Clear CCF Flag */\r\n  __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);\r\n  \r\n  /* Initiate additional transfer to wrap-up data feeding to the IP */\r\n  if (hcryp->CrypInCount != 0)\r\n  {\r\n    /* Last block is now entered in polling mode, no actual gain in resorting to DMA */\r\n    difflength = hcryp->CrypInCount;\r\n    hcryp->CrypInCount = 0;\r\n    \r\n    CRYP_Padding(hcryp, difflength, CRYP_POLLING_ON); \r\n  }  \r\n  \r\n  /* Change the CRYP state to ready */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  /* Mark that the payload phase is over */\r\n  hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; \r\n  \r\n  /* Call output data transfer complete callback */\r\n  HAL_CRYP_OutCpltCallback(hcryp);\r\n}\r\n\r\n/**\r\n  * @brief  DMA CRYP communication error callback\r\n  *         for GCM, GMAC or CMAC chainging modes.\r\n  * @param  hdma DMA handle\r\n  * @retval None\r\n  */\r\nstatic void CRYP_GCMCMAC_DMAError(DMA_HandleTypeDef *hdma)\r\n{\r\n  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n  \r\n  hcryp->State= HAL_CRYP_STATE_ERROR;\r\n  hcryp->ErrorCode |= HAL_CRYP_DMA_ERROR;\r\n  HAL_CRYP_ErrorCallback(hcryp);\r\n  /* Clear Error Flag */\r\n  __HAL_CRYP_CLEAR_FLAG(CRYP_ERR_CLEAR);\r\n}\r\n\r\n\r\n\r\n/** \r\n  * @brief  Handle CRYP block input/output data handling under interruption\r\n  *         for GCM, GMAC or CMAC chaining modes.  \r\n  * @note   The function is called under interruption only, once\r\n  *         interruptions have been enabled by HAL_CRYPEx_AES_Auth_IT().  \r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp)\r\n{\r\n  uint32_t inputaddr   = 0x0;\r\n  uint32_t outputaddr  = 0x0; \r\n  uint32_t index       = 0x0;\r\n  uint32_t addhoc_process = 0; \r\n  uint32_t difflength     = 0;\r\n  uint32_t difflengthmod4 = 0;\r\n  uint32_t mask[3]        = {0x0FF, 0x0FFFF, 0x0FFFFFF};\r\n  uint32_t intermediate_data[4] = {0};        \r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_BUSY)\r\n  {\r\n    /*===========================*/\r\n    /* GCM/GMAC(/CCM) init phase */\r\n    /*===========================*/  \r\n    if (hcryp->Init.GCMCMACPhase == CRYP_INIT_PHASE)\r\n    {\r\n      /* Clear Computation Complete Flag */\r\n      __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);\r\n      /* Disable Computation Complete Flag and Errors Interrupts */\r\n      __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);\r\n      /* Change the CRYP state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n    \r\n      /* Mark that the initialization phase is over */\r\n      hcryp->Phase = HAL_CRYP_PHASE_INIT_OVER;\r\n          \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Call computation complete callback */\r\n      HAL_CRYPEx_ComputationCpltCallback(hcryp);\r\n      return HAL_OK;\r\n    }\r\n    /*=====================================*/\r\n    /* GCM/GMAC or (CCM/)CMAC header phase */\r\n    /*=====================================*/   \r\n    else if (hcryp->Init.GCMCMACPhase == CRYP_HEADER_PHASE)\r\n    {\r\n      /* Check if all input header data have been entered */\r\n      if (hcryp->CrypInCount == 0)\r\n      {\r\n        /* Clear Computation Complete Flag */\r\n        __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);\r\n        /* Disable Computation Complete Flag and Errors Interrupts */\r\n        __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);\r\n        /* Change the CRYP state */\r\n        hcryp->State = HAL_CRYP_STATE_READY;\r\n       /* Mark that the header phase is over */\r\n        hcryp->Phase = HAL_CRYP_PHASE_HEADER_OVER;\r\n      \r\n       /* Process Unlocked */\r\n        __HAL_UNLOCK(hcryp);\r\n      \r\n        /* Call computation complete callback */\r\n        HAL_CRYPEx_ComputationCpltCallback(hcryp);\r\n      \r\n        return HAL_OK;\r\n      }\r\n      /* If suspension flag has been raised, suspend processing */\r\n      else if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)\r\n      {\r\n        /* Clear CCF Flag */\r\n        __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);\r\n       \r\n        /* reset SuspendRequest */\r\n        hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;\r\n        /* Disable Computation Complete Flag and Errors Interrupts */\r\n        __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);\r\n        /* Change the CRYP state */\r\n        hcryp->State = HAL_CRYP_STATE_SUSPENDED;\r\n        /* Mark that the header phase is over */\r\n        hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED;\r\n      \r\n       /* Process Unlocked */\r\n        __HAL_UNLOCK(hcryp);\r\n      \r\n        return HAL_OK;\r\n      }      \r\n      else /* Carry on feeding input data to the CRYP hardware block */\r\n      {\r\n        /* Clear Computation Complete Flag */\r\n        __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);\r\n        /* Get the last Input data address */\r\n        inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n      \r\n        /* Increment/decrement instance pointer/counter */\r\n        if (hcryp->CrypInCount < 16)\r\n        {\r\n          difflength = hcryp->CrypInCount;        \r\n          hcryp->CrypInCount = 0;\r\n          addhoc_process = 1;  \r\n          difflengthmod4 = difflength%4;              \r\n        }\r\n        else\r\n        {\r\n          hcryp->pCrypInBuffPtr += 16;\r\n          hcryp->CrypInCount -= 16;\r\n        }        \r\n        \r\n#if defined(AES_CR_NPBLB)    \r\n        if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM_CMAC)\r\n#else     \r\n        if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)\r\n#endif         \r\n        { \r\n          if (hcryp->CrypInCount == hcryp->Init.HeaderSize)\r\n          {\r\n            /* All B blocks will have been entered after the next\r\n              four DINR writing, so point at header buffer for\r\n              the next iteration */\r\n            hcryp->pCrypInBuffPtr = hcryp->Init.Header;\r\n          }\r\n        }           \r\n      \r\n        /* Write the Input block in the Data Input register */\r\n        if (addhoc_process == 0)\r\n        {         \r\n          hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n          inputaddr+=4;\r\n          hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n          inputaddr+=4;\r\n          hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);\r\n          inputaddr+=4;\r\n          hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n        }\r\n        else\r\n        {\r\n          /* Header remainder has size less than 128 bits */ \r\n          /* Enter complete words when possible */\r\n          for(index=0; index < (difflength/4); index ++)\r\n          {\r\n            /* Write the Input block in the Data Input register */\r\n            hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n            inputaddr+=4;\r\n          }\r\n          /* Enter incomplete word padded with zeroes if applicable \r\n            (case of header length not a multiple of 32-bits) */\r\n          if (difflengthmod4 != 0)\r\n          {         \r\n            hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]);\r\n          }         \r\n          /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */\r\n          for(index=0; index < (4 - ((difflength+3)/4)); index ++)         \r\n          {\r\n            hcryp->Instance->DINR = 0;\r\n          }          \r\n        }\r\n      \r\n        return HAL_OK;      \r\n      }\r\n    }\r\n    /*=======================*/\r\n    /* GCM/CCM payload phase */\r\n    /*=======================*/    \r\n    else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)\r\n    {\r\n      /* Get the last output data address */\r\n      outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n      \r\n     /* Specific handling to manage payload size less than 128 bits\r\n        when GCM (or CCM when applicable) encryption or decryption is selected.\r\n        Check here if the last block output data are read */\r\n#if defined(AES_CR_NPBLB)  \r\n      if ((hcryp->CrypOutCount < 16)                                && \\\r\n          (hcryp->CrypOutCount > 0))\r\n#else    \r\n      if ((hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_GCM_GMAC) && \\\r\n          (hcryp->CrypOutCount < 16)                                && \\\r\n          (hcryp->CrypOutCount > 0))\r\n#endif          \r\n      {\r\n        addhoc_process = 1;\r\n        difflength = hcryp->CrypOutCount;\r\n        difflengthmod4 = difflength%4; \r\n        hcryp->CrypOutCount = 0;   /* mark that no more output data will be needed */       \r\n        /* Retrieve intermediate data */\r\n        for(index=0; index < 4; index ++)\r\n        {\r\n          intermediate_data[index] = hcryp->Instance->DOUTR;                 \r\n        } \r\n        /* Retrieve last words of cyphered data */\r\n        /* First, retrieve complete output words */\r\n        for(index=0; index < (difflength/4); index ++)\r\n        {\r\n          *(uint32_t*)(outputaddr) = intermediate_data[index];\r\n          outputaddr+=4; \r\n        } \r\n        /* Next, retrieve partial output word if applicable;\r\n           at the same time, start masking intermediate data \r\n           with a mask of zeros of same size than the padding\r\n           applied to the last block of payload */ \r\n        if (difflengthmod4 != 0)\r\n        {\r\n          intermediate_data[difflength/4] &= mask[difflengthmod4-1];\r\n          *(uint32_t*)(outputaddr) = intermediate_data[difflength/4];            \r\n        }           \r\n   \r\n#if !defined(AES_CR_NPBLB)       \r\n        if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT)\r\n        { \r\n          /* Change again CHMOD configuration to GCM mode */\r\n          __HAL_CRYP_SET_CHAININGMODE(CRYP_CHAINMODE_AES_GCM_GMAC); \r\n        \r\n          /* Select FINAL phase */\r\n          MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_GCMCMAC_FINAL_PHASE);  \r\n        \r\n          /* Before inserting the intermediate data, carry on masking operation\r\n             with a mask of zeros of same size than the padding applied to the last block of payload */\r\n          for(index=0; index < (4 - ((difflength+3)/4)); index ++)        \r\n          {\r\n            intermediate_data[(difflength+3)/4+index] = 0;\r\n          }  \r\n        \r\n          /* Insert intermediate data to trigger an additional DOUTR reading round */\r\n          /* Clear Computation Complete Flag before entering new block */\r\n          __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);\r\n          for(index=0; index < 4; index ++)\r\n          {\r\n            hcryp->Instance->DINR = intermediate_data[index];          \r\n          }\r\n        }\r\n        else\r\n#endif        \r\n        {\r\n          /* Payload phase is now over */\r\n          /* Clear Computation Complete Flag */\r\n          __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);        \r\n          /* Disable Computation Complete Flag and Errors Interrupts */\r\n          __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);\r\n          /* Change the CRYP state */\r\n          hcryp->State = HAL_CRYP_STATE_READY;\r\n          /* Mark that the payload phase is over */\r\n          hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER;\r\n      \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n      \r\n          /* Call computation complete callback */\r\n          HAL_CRYPEx_ComputationCpltCallback(hcryp);\r\n        }\r\n        return HAL_OK;\r\n      }\r\n      else  \r\n      { \r\n        if (hcryp->CrypOutCount != 0)\r\n        { \r\n          /* Usual case (different than GCM/CCM last block < 128 bits ciphering) */ \r\n          /* Retrieve the last block available from the CRYP hardware block:\r\n            read the output block from the Data Output Register */\r\n          *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;\r\n          outputaddr+=4;\r\n          *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;\r\n          outputaddr+=4;\r\n          *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;\r\n          outputaddr+=4;\r\n          *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;\r\n          \r\n          /* Increment/decrement instance pointer/counter */\r\n          hcryp->pCrypOutBuffPtr += 16;\r\n          hcryp->CrypOutCount -= 16;                    \r\n        }\r\n#if !defined(AES_CR_NPBLB)          \r\n        else\r\n        {          \r\n          /* Software work-around: additional DOUTR reading round to discard the data */\r\n          for(index=0; index < 4; index ++)\r\n          {\r\n            intermediate_data[index] = hcryp->Instance->DOUTR;                 \r\n          }          \r\n        }\r\n#endif         \r\n      }            \r\n      \r\n      /* Check if all output text has been retrieved */\r\n      if (hcryp->CrypOutCount == 0)\r\n      {\r\n#if !defined(AES_CR_NPBLB)       \r\n        /* Make sure that software-work around is not running before disabling\r\n          the interruptions (indeed, if software work-around is running, the \r\n          interruptions must not be disabled to allow the additional DOUTR \r\n          reading round */\r\n        if (addhoc_process == 0)\r\n#endif        \r\n        {\r\n          /* Clear Computation Complete Flag */\r\n          __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);        \r\n          /* Disable Computation Complete Flag and Errors Interrupts */\r\n          __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);\r\n          /* Change the CRYP state */\r\n          hcryp->State = HAL_CRYP_STATE_READY;\r\n         /* Mark that the payload phase is over */\r\n          hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER;\r\n      \r\n         /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n      \r\n          /* Call computation complete callback */\r\n          HAL_CRYPEx_ComputationCpltCallback(hcryp);\r\n        }\r\n      \r\n        return HAL_OK;\r\n      }\r\n      /* If suspension flag has been raised, suspend processing */\r\n      else if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)\r\n      {     \r\n        /* Clear CCF Flag */\r\n        __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);\r\n       \r\n        /* reset SuspendRequest */\r\n        hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;\r\n        /* Disable Computation Complete Flag and Errors Interrupts */\r\n        __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);\r\n        /* Change the CRYP state */\r\n        hcryp->State = HAL_CRYP_STATE_SUSPENDED;\r\n        /* Mark that the header phase is over */\r\n        hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED;\r\n      \r\n       /* Process Unlocked */\r\n        __HAL_UNLOCK(hcryp);\r\n      \r\n        return HAL_OK;\r\n      }            \r\n      else /* Output data are still expected, carry on feeding the CRYP\r\n               hardware block with input data */\r\n      {\r\n        /* Clear Computation Complete Flag */\r\n        __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);          \r\n        /* Get the last Input data address */\r\n        inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n      \r\n        /* Usual input data feeding case */\r\n        if (hcryp->CrypInCount < 16)\r\n        {\r\n          difflength = (uint32_t) (hcryp->CrypInCount);\r\n          difflengthmod4 = difflength%4;\r\n          hcryp->CrypInCount = 0; \r\n          \r\n#if defined(AES_CR_NPBLB)  \r\n          /* In case of GCM encryption or CCM decryption, specify the number of padding\r\n             bytes in last block of payload */\r\n               if (((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_GCM_GMAC)\r\n                    &&  (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_ENCRYPT))   \r\n                ||  ((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_CCM_CMAC)\r\n                    &&  (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_DECRYPT)))\r\n               {\r\n                 /* Set NPBLB field in writing the number of padding bytes \r\n                    for the last block of payload */\r\n                 MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 16 - difflength);\r\n               }\r\n#else          \r\n          /* Software workaround applied to GCM encryption only */ \r\n          if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT)\r\n          {\r\n            /* Change the mode configured in CHMOD bits of CR register to select CTR mode */   \r\n            __HAL_CRYP_SET_CHAININGMODE(CRYP_CHAINMODE_AES_CTR);\r\n          }   \r\n#endif                   \r\n          \r\n          /*  Insert the last block (which size is inferior to 128 bits) padded with zeroes \r\n              to have a complete block of 128 bits */\r\n          for(index=0; index < (difflength/4); index ++)\r\n          {\r\n            /* Write the Input block in the Data Input register */\r\n            hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n            inputaddr+=4;\r\n          }\r\n          /* If required, manage input data size not multiple of 32 bits */\r\n          if (difflengthmod4 != 0)\r\n          {         \r\n            hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]);\r\n          }         \r\n          /* Wrap-up in padding with zero-words if applicable */\r\n          for(index=0; index < (4 - ((difflength+3)/4)); index ++)        \r\n          {\r\n            hcryp->Instance->DINR = 0;\r\n          }                           \r\n                                    \r\n        }\r\n        else\r\n        {\r\n          hcryp->pCrypInBuffPtr += 16;\r\n          hcryp->CrypInCount -= 16;\r\n          \r\n          /* Write the Input block in the Data Input register */\r\n          hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n          inputaddr+=4;\r\n          hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n          inputaddr+=4;\r\n          hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);\r\n          inputaddr+=4;\r\n          hcryp->Instance->DINR = *(uint32_t*)(inputaddr);            \r\n        }            \r\n                  \r\n    \r\n        return HAL_OK;      \r\n      }\r\n    }\r\n    /*====================================*/\r\n    /* GCM/GMAC or (CCM/)CMAC final phase */\r\n    /*====================================*/  \r\n    else if (hcryp->Init.GCMCMACPhase == CRYP_FINAL_PHASE)\r\n    {\r\n      /* Clear Computation Complete Flag */\r\n      __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);  \r\n            \r\n      /* Get the last output data address */\r\n      outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n      \r\n      /* Retrieve the last expected data from the CRYP hardware block:\r\n         read the output block from the Data Output Register */\r\n      *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;\r\n      outputaddr+=4;\r\n      *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;\r\n      outputaddr+=4;\r\n      *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;\r\n      outputaddr+=4;\r\n      *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;\r\n  \r\n      /* Disable Computation Complete Flag and Errors Interrupts */\r\n      __HAL_CRYP_DISABLE_IT(CRYP_IT_CCFIE|CRYP_IT_ERRIE);\r\n      /* Change the CRYP state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Mark that the header phase is over */\r\n      hcryp->Phase = HAL_CRYP_PHASE_FINAL_OVER;\r\n      \r\n      /* Disable the Peripheral */\r\n      __HAL_CRYP_DISABLE();\r\n      /* Process Unlocked */\r\n       __HAL_UNLOCK(hcryp);\r\n      \r\n      /* Call computation complete callback */\r\n      HAL_CRYPEx_ComputationCpltCallback(hcryp);\r\n      \r\n      return HAL_OK;\r\n    }\r\n    else\r\n    {\r\n      /* Clear Computation Complete Flag */\r\n      __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);       \r\n      hcryp->State = HAL_CRYP_STATE_ERROR; \r\n      __HAL_UNLOCK(hcryp); \r\n      return HAL_ERROR; \r\n    }\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY; \r\n  }  \r\n}\r\n    \r\n  \r\n  \r\n/** \r\n  * @brief  Set the DMA configuration and start the DMA transfer\r\n  *         for GCM, GMAC or CMAC chainging modes.   \r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module.\r\n  * @param  inputaddr Address of the Input buffer.\r\n  * @param  Size Size of the Input buffer un bytes, must be a multiple of 16.\r\n  * @param  outputaddr Address of the Output buffer, null pointer when no output DMA stream\r\n  *         has to be configured.  \r\n  * @retval None\r\n  */\r\nstatic void CRYP_GCMCMAC_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)\r\n{\r\n\r\n  /* Set the input CRYP DMA transfer complete callback */\r\n  hcryp->hdmain->XferCpltCallback = CRYP_GCMCMAC_DMAInCplt;\r\n  /* Set the DMA error callback */\r\n  hcryp->hdmain->XferErrorCallback = CRYP_GCMCMAC_DMAError;\r\n  \r\n  if (outputaddr != 0) \r\n  { \r\n    /* Set the output CRYP DMA transfer complete callback */\r\n    hcryp->hdmaout->XferCpltCallback = CRYP_GCMCMAC_DMAOutCplt;\r\n    /* Set the DMA error callback */\r\n    hcryp->hdmaout->XferErrorCallback = CRYP_GCMCMAC_DMAError;\r\n  }\r\n  \r\n  /* Enable the CRYP peripheral */\r\n  __HAL_CRYP_ENABLE();\r\n  \r\n  /* Enable the DMA input stream */\r\n  HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size/4);\r\n  \r\n  /* Enable the DMA input request */\r\n  SET_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);\r\n\r\n  \r\n  if (outputaddr != 0) \r\n  {   \r\n    /* Enable the DMA output stream */\r\n    HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size/4);\r\n  \r\n    /* Enable the DMA output request */\r\n    SET_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);\r\n  }\r\n}  \r\n\r\n\r\n\r\n/**\r\n  * @brief  Write/read input/output data in polling mode.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module.\r\n  * @param  Input Pointer to the Input buffer.\r\n  * @param  Ilength Length of the Input buffer in bytes, must be a multiple of 16.\r\n  * @param  Output Pointer to the returned buffer.\r\n  * @param  Timeout Specify Timeout value.  \r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)\r\n{\r\n  uint32_t index = 0;\r\n  uint32_t inputaddr  = (uint32_t)Input;\r\n  uint32_t outputaddr = (uint32_t)Output;\r\n  \r\n\r\n  for(index=0; (index < Ilength); index += 16)\r\n  {\r\n    /* Write the Input block in the Data Input register */\r\n    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DINR  = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    \r\n    /* Wait for CCF flag to be raised */\r\n    if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)  \r\n    { \r\n      hcryp->State = HAL_CRYP_STATE_READY;        \r\n      __HAL_UNLOCK(hcryp);\r\n      return HAL_TIMEOUT;\r\n    }\r\n      \r\n    /* Clear CCF Flag */\r\n    __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);\r\n    \r\n    /* Read the Output block from the Data Output Register */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR;\r\n    outputaddr+=4;\r\n    \r\n    /* If the suspension flag has been raised and if the processing is not about\r\n       to end, suspend processing */\r\n    if ((hcryp->SuspendRequest == HAL_CRYP_SUSPEND) && ((index+16) < Ilength))\r\n    {\r\n      /* Reset SuspendRequest */\r\n      hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;\r\n      \r\n      /* Save current reading and writing locations of Input and Output buffers */\r\n      hcryp->pCrypOutBuffPtr =  (uint8_t *)outputaddr;\r\n      hcryp->pCrypInBuffPtr  =  (uint8_t *)inputaddr;\r\n      /* Save the number of bytes that remain to be processed at this point */\r\n      hcryp->CrypInCount     =  Ilength - (index+16);\r\n      \r\n      /* Change the CRYP state */\r\n      hcryp->State = HAL_CRYP_STATE_SUSPENDED;\r\n      \r\n      return HAL_OK;\r\n    }\r\n    \r\n    \r\n  }\r\n  /* Return function status */\r\n  return HAL_OK;\r\n\r\n}\r\n\r\n\r\n\r\n\r\n\r\n/**\r\n  * @brief  Read derivative key in polling mode when CRYP hardware block is set\r\n  *         in key derivation operating mode (mode 2).\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module.\r\n  * @param  Output Pointer to the returned buffer.\r\n  * @param  Timeout Specify Timeout value.  \r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef CRYP_ReadKey(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t Timeout)\r\n{\r\n  uint32_t outputaddr = (uint32_t)Output;\r\n  \r\n  /* Wait for CCF flag to be raised */  \r\n  if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)  \r\n  { \r\n    hcryp->State = HAL_CRYP_STATE_READY;        \r\n    __HAL_UNLOCK(hcryp);\r\n    return HAL_TIMEOUT;\r\n  }\r\n  /* Clear CCF Flag */\r\n  __HAL_CRYP_CLEAR_FLAG( CRYP_CCF_CLEAR);\r\n  \r\n    /* Read the derivative key from the AES_KEYRx registers */\r\n  if (hcryp->Init.KeySize == CRYP_KEYSIZE_256B)\r\n  {   \r\n    *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR7);\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR6);\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR5);\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR4);\r\n    outputaddr+=4;\r\n  }\r\n  \r\n    *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR3);\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR2);\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR1);\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = __REV(hcryp->Instance->KEYR0);\r\n\r\n    \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Set the DMA configuration and start the DMA transfer.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module.\r\n  * @param  inputaddr Address of the Input buffer.\r\n  * @param  Size Size of the Input buffer in bytes, must be a multiple of 16.\r\n  * @param  outputaddr Address of the Output buffer.\r\n  * @retval None\r\n  */\r\nstatic void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)\r\n{\r\n  /* Set the CRYP DMA transfer complete callback */\r\n  hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;\r\n  /* Set the DMA error callback */\r\n  hcryp->hdmain->XferErrorCallback = CRYP_DMAError;\r\n  \r\n  /* Set the CRYP DMA transfer complete callback */\r\n  hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;\r\n  /* Set the DMA error callback */\r\n  hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;\r\n\r\n  /* Enable the DMA input stream */\r\n  HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size/4);\r\n\r\n  /* Enable the DMA output stream */\r\n  HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size/4);\r\n\r\n  /* Enable In and Out DMA requests */\r\n  SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN));\r\n  \r\n  /* Enable the CRYP peripheral */\r\n  __HAL_CRYP_ENABLE();\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Handle CRYP hardware block Timeout when waiting for CCF flag to be raised.\r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module.      \r\n  * @param  Timeout Timeout duration.\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Get timeout */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))\r\n  {    \r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > Timeout)\r\n      {    \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  return HAL_OK; \r\n}\r\n\r\n/**\r\n  * @brief  Wait for Busy Flag to be reset during a GCM payload encryption process suspension. \r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module.         \r\n  * @param  Timeout Timeout duration.\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef CRYP_WaitOnBusyFlagReset(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Get timeout */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  while(HAL_IS_BIT_SET(hcryp->Instance->SR, AES_SR_BUSY))\r\n  {    \r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > Timeout)\r\n      {    \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  return HAL_OK; \r\n}\r\n\r\n\r\n/**\r\n  * @brief  DMA CRYP Input Data process complete callback.\r\n  * @param  hdma DMA handle.\r\n  * @retval None\r\n  */\r\nstatic void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)  \r\n{\r\n  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n  \r\n  /* Disable the DMA transfer for input request  */\r\n  CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);\r\n  \r\n  /* Call input data transfer complete callback */\r\n  HAL_CRYP_InCpltCallback(hcryp);\r\n}\r\n\r\n/**\r\n  * @brief  DMA CRYP Output Data process complete callback.\r\n  * @param  hdma DMA handle.\r\n  * @retval None\r\n  */\r\nstatic void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)\r\n{  \r\n  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n  \r\n  /* Disable the DMA transfer for output request */\r\n  CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);\r\n\r\n  /* Clear CCF Flag */\r\n  __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);\r\n  \r\n  /* Disable CRYP */\r\n  __HAL_CRYP_DISABLE();\r\n  \r\n  /* Change the CRYP state to ready */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Call output data transfer complete callback */\r\n  HAL_CRYP_OutCpltCallback(hcryp);\r\n}\r\n\r\n/**\r\n  * @brief  DMA CRYP communication error callback. \r\n  * @param  hdma DMA handle.\r\n  * @retval None\r\n  */\r\nstatic void CRYP_DMAError(DMA_HandleTypeDef *hdma)\r\n{\r\n  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n  \r\n  hcryp->State= HAL_CRYP_STATE_ERROR;\r\n  hcryp->ErrorCode |= HAL_CRYP_DMA_ERROR;  \r\n  HAL_CRYP_ErrorCallback(hcryp);\r\n  /* Clear Error Flag */\r\n  __HAL_CRYP_CLEAR_FLAG(CRYP_ERR_CLEAR);\r\n}\r\n\r\n/**\r\n  * @brief  Last header or payload block padding when size is not a multiple of 128 bits. \r\n  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module.         \r\n  * @param  difflength size remainder after having fed all complete 128-bit blocks.\r\n  * @param  polling specifies whether or not polling on CCF must be done after having\r\n  *                  entered a complete block.     \r\n  * @retval None\r\n  */\r\nstatic void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_t polling)\r\n{\r\n  uint32_t index          = 0;\r\n  uint32_t difflengthmod4 = difflength%4;\r\n  uint32_t inputaddr      = (uint32_t)hcryp->pCrypInBuffPtr; \r\n  uint32_t outputaddr     = (uint32_t)hcryp->pCrypOutBuffPtr;   \r\n  uint32_t mask[3]        = {0x0FF, 0x0FFFF, 0x0FFFFFF};  \r\n  uint32_t intermediate_data[4] = {0};\r\n  \r\n#if defined(AES_CR_NPBLB)  \r\n  /* In case of GCM encryption or CCM decryption, specify the number of padding\r\n     bytes in last block of payload */\r\n     if (READ_BIT(hcryp->Instance->CR,AES_CR_GCMPH) == CRYP_PAYLOAD_PHASE)\r\n     {\r\n       if (((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_GCM_GMAC)\r\n            &&  (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_ENCRYPT))   \r\n        ||  ((READ_BIT(hcryp->Instance->CR, AES_CR_CHMOD) == CRYP_CHAINMODE_AES_CCM_CMAC)\r\n            &&  (READ_BIT(hcryp->Instance->CR, AES_CR_MODE) == CRYP_ALGOMODE_DECRYPT)))\r\n       {\r\n         /* Set NPBLB field in writing the number of padding bytes \r\n            for the last block of payload */\r\n         MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 16 - difflength);\r\n       }\r\n     }\r\n#else\r\n  /* Software workaround applied to GCM encryption only */\r\n  if ((hcryp->Init.GCMCMACPhase == CRYP_GCM_PAYLOAD_PHASE) &&\t\t\r\n      (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT))\r\n  {\r\n    /* Change the mode configured in CHMOD bits of CR register to select CTR mode */   \r\n    __HAL_CRYP_SET_CHAININGMODE(CRYP_CHAINMODE_AES_CTR);\r\n  }  \r\n#endif  \r\n  \r\n  /* Wrap-up entering header or payload data */\r\n  /* Enter complete words when possible */\r\n  for(index=0; index < (difflength/4); index ++)\r\n  {\r\n    /* Write the Input block in the Data Input register */\r\n    hcryp->Instance->DINR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n  }\r\n  /* Enter incomplete word padded with zeroes if applicable \r\n    (case of header length not a multiple of 32-bits) */\r\n  if (difflengthmod4 != 0)\r\n  {         \r\n    hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]);\r\n  }         \r\n  /* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */\r\n  for(index=0; index < (4 - ((difflength+3)/4)); index ++)         \r\n  {\r\n    hcryp->Instance->DINR = 0;\r\n  } \r\n\t\t\r\n  if (polling == CRYP_POLLING_ON)\r\n  {\r\n\t\tif(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)  \r\n    { \r\n        hcryp->State = HAL_CRYP_STATE_READY;        \r\n        __HAL_UNLOCK(hcryp);\r\n       HAL_CRYP_ErrorCallback(hcryp);\r\n      } \r\n\r\n    /* Clear CCF Flag */\r\n    __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);\r\n  }\r\n\t\t\r\n\t/* if payload */\r\n  if (hcryp->Init.GCMCMACPhase == CRYP_GCM_PAYLOAD_PHASE)\r\n\t{\t\t\r\n       \r\n    /* Retrieve intermediate data */\r\n    for(index=0; index < 4; index ++)\r\n    {\r\n      intermediate_data[index] = hcryp->Instance->DOUTR;                 \r\n    }     \r\n    /* Retrieve last words of cyphered data */\r\n    /* First, retrieve complete output words */\r\n    for(index=0; index < (difflength/4); index ++)\r\n    {\r\n      *(uint32_t*)(outputaddr) = intermediate_data[index];\r\n      outputaddr+=4; \r\n    } \r\n    /* Next, retrieve partial output word if applicable;\r\n       at the same time, start masking intermediate data \r\n       with a mask of zeros of same size than the padding\r\n       applied to the last block of payload */ \r\n    if (difflengthmod4 != 0)\r\n    {\r\n      intermediate_data[difflength/4] &= mask[difflengthmod4-1];\r\n      *(uint32_t*)(outputaddr) = intermediate_data[difflength/4];            \r\n    }           \r\n    \r\n    \r\n#if !defined(AES_CR_NPBLB)      \r\n    /* Software workaround applied to GCM encryption only,\r\n       applicable for AES IP v2 version (where NPBLB is not defined) */           \r\n    if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT)\r\n    {\r\n      /* Change again CHMOD configuration to GCM mode */\r\n      __HAL_CRYP_SET_CHAININGMODE(CRYP_CHAINMODE_AES_GCM_GMAC);  \r\n      \r\n      /* Select FINAL phase */\r\n      MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_GCMCMAC_FINAL_PHASE);\r\n      \r\n      /* Before inserting the intermediate data, carry on masking operation\r\n         with a mask of zeros of same size than the padding applied to the last block of payload */\r\n      for(index=0; index < (4 - ((difflength+3)/4)); index ++)        \r\n      {\r\n        intermediate_data[(difflength+3)/4+index] = 0;\r\n      }   \r\n      /* Insert intermediate data */\r\n      for(index=0; index < 4; index ++)\r\n      {\r\n        hcryp->Instance->DINR = intermediate_data[index];          \r\n      } \r\n      \r\n      /*  Wait for completion, and read data on DOUT. This data is to discard. */ \r\n      if(CRYP_WaitOnCCFlag(hcryp, CRYP_CCF_TIMEOUTVALUE) != HAL_OK)  \r\n      { \r\n        hcryp->State = HAL_CRYP_STATE_READY;        \r\n        __HAL_UNLOCK(hcryp);\r\n        HAL_CRYP_ErrorCallback(hcryp);\r\n      } \r\n         \r\n      /* Read data to discard */ \r\n      /* Clear CCF Flag */\r\n      __HAL_CRYP_CLEAR_FLAG(CRYP_CCF_CLEAR);\r\n      for(index=0; index < 4; index ++)\r\n      {\r\n        intermediate_data[index] = hcryp->Instance->DOUTR;        \r\n      }  \r\n\t\t\r\n\t  } /* if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_ENCRYPT) */\r\n#endif  /* !defined(AES_CR_NPBLB) */     \r\n\t}   /* if (hcryp->Init.GCMCMACPhase == CRYP_GCM_PAYLOAD_PHASE) */\r\n\t\t\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* AES */\r\n\r\n#endif /* HAL_CRYP_MODULE_ENABLED */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_dma.c\r\n  * @author  MCD Application Team\r\n  * @brief   DMA HAL module driver.\r\n  *    \r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the Direct Memory Access (DMA) peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + IO operation functions\r\n  *           + Peripheral State and errors functions\r\n  @verbatim     \r\n  ==============================================================================\r\n                        ##### How to use this driver #####\r\n  ==============================================================================\r\n  [..]\r\n   (#) Enable and configure the peripheral to be connected to the DMA Stream\r\n       (except for internal SRAM/FLASH memories: no initialization is \r\n       necessary) please refer to Reference manual for connection between peripherals\r\n       and DMA requests.\r\n\r\n   (#) For a given Stream, program the required configuration through the following parameters:\r\n       Transfer Direction, Source and Destination data formats, \r\n       Circular, Normal or peripheral flow control mode, Stream Priority level, \r\n       Source and Destination Increment mode, FIFO mode and its Threshold (if needed), \r\n       Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.\r\n\r\n   -@-   Prior to HAL_DMA_Init() the clock must be enabled for DMA through the following macros:\r\n         __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE().\r\n\r\n     *** Polling mode IO operation ***\r\n     =================================\r\n    [..]\r\n          (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source \r\n              address and destination address and the Length of data to be transferred.\r\n          (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this  \r\n              case a fixed Timeout can be configured by User depending from his application.\r\n          (+) Use HAL_DMA_Abort() function to abort the current transfer.\r\n\r\n     *** Interrupt mode IO operation ***\r\n     ===================================\r\n    [..]\r\n          (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()\r\n          (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()\r\n          (+) Select Callbacks functions using HAL_DMA_RegisterCallback()\r\n          (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of  \r\n              Source address and destination address and the Length of data to be transferred. In this \r\n              case the DMA interrupt is configured \r\n          (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine\r\n          (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can \r\n              add his own function by customization of function pointer XferCpltCallback and \r\n              XferErrorCallback (i.e a member of DMA handle structure).\r\n    [..]\r\n     (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error \r\n         detection.\r\n\r\n     (#) Use HAL_DMA_Abort_IT() function to abort the current transfer\r\n\r\n     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.\r\n\r\n     -@-   The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is\r\n           possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set\r\n           Half-Word data size for the peripheral to access its data register and set Word data size\r\n           for the Memory to gain in access time. Each two half words will be packed and written in\r\n           a single access to a Word in the Memory).\r\n\r\n     -@-   When FIFO is disabled, it is not allowed to configure different Data Sizes for Source\r\n           and Destination. In this case the Peripheral Data Size will be applied to both Source\r\n           and Destination.\r\n\r\n     *** DMA HAL driver macros list ***\r\n     =============================================\r\n     [..]\r\n       Below the list of most used macros in DMA HAL driver.\r\n       \r\n      (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.\r\n      (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.\r\n      (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not. \r\n\r\n     [..]\r\n      (@) You can refer to the DMA HAL driver header file for more useful macros\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup DMA DMA\r\n  * @brief DMA HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_DMA_MODULE_ENABLED\r\n\r\n/* Private types -------------------------------------------------------------*/\r\ntypedef struct\r\n{\r\n  __IO uint32_t ISR;   /*!< DMA interrupt status register */\r\n  __IO uint32_t Reserved0;\r\n  __IO uint32_t IFCR;  /*!< DMA interrupt flag clear register */\r\n} DMA_Base_Registers;\r\n\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @addtogroup DMA_Private_Constants\r\n * @{\r\n */\r\n #define HAL_TIMEOUT_DMA_ABORT    ((uint32_t)5)  /* 5 ms */\r\n/**\r\n  * @}\r\n  */\r\n/* Private macros ------------------------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @addtogroup DMA_Private_Functions\r\n  * @{\r\n  */\r\nstatic void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r\nstatic uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);\r\nstatic HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);\r\n\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/* Exported functions ---------------------------------------------------------*/\r\n/** @addtogroup DMA_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup DMA_Exported_Functions_Group1\r\n  *\r\n@verbatim\r\n ===============================================================================\r\n             ##### Initialization and de-initialization functions  #####\r\n ===============================================================================\r\n    [..]\r\n    This section provides functions allowing to initialize the DMA Stream source\r\n    and destination addresses, incrementation and data sizes, transfer direction, \r\n    circular/normal mode selection, memory-to-memory mode selection and Stream priority value.\r\n    [..]\r\n    The HAL_DMA_Init() function follows the DMA configuration procedures as described in\r\n    reference manual.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @brief  Initialize the DMA according to the specified\r\n  *         parameters in the DMA_InitTypeDef and create the associated handle.\r\n  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified DMA Stream.  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)\r\n{\r\n  uint32_t tmp = 0U;\r\n  uint32_t tickstart = HAL_GetTick();\r\n  DMA_Base_Registers *regs;\r\n\r\n  /* Check the DMA peripheral state */\r\n  if(hdma == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));\r\n  assert_param(IS_DMA_CHANNEL(hdma->Init.Channel));\r\n  assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));\r\n  assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));\r\n  assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));\r\n  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));\r\n  assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));\r\n  assert_param(IS_DMA_MODE(hdma->Init.Mode));\r\n  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));\r\n  assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));\r\n  /* Check the memory burst, peripheral burst and FIFO threshold parameters only\r\n     when FIFO mode is enabled */\r\n  if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)\r\n  {\r\n    assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));\r\n    assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));\r\n    assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));\r\n  }\r\n  \r\n  /* Allocate lock resource */\r\n  __HAL_UNLOCK(hdma);\r\n\r\n  /* Change DMA peripheral state */\r\n  hdma->State = HAL_DMA_STATE_BUSY;\r\n  \r\n  /* Disable the peripheral */\r\n  __HAL_DMA_DISABLE(hdma);\r\n  \r\n  /* Check if the DMA Stream is effectively disabled */\r\n  while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)\r\n  {\r\n    /* Check for the Timeout */\r\n    if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)\r\n    {\r\n      /* Update error code */\r\n      hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;\r\n      \r\n      /* Change the DMA state */\r\n      hdma->State = HAL_DMA_STATE_TIMEOUT;\r\n      \r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  \r\n  /* Get the CR register value */\r\n  tmp = hdma->Instance->CR;\r\n\r\n  /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */\r\n  tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \\\r\n                      DMA_SxCR_PL    | DMA_SxCR_MSIZE  | DMA_SxCR_PSIZE  | \\\r\n                      DMA_SxCR_MINC  | DMA_SxCR_PINC   | DMA_SxCR_CIRC   | \\\r\n                      DMA_SxCR_DIR   | DMA_SxCR_CT     | DMA_SxCR_DBM));\r\n\r\n  /* Prepare the DMA Stream configuration */\r\n  tmp |=  hdma->Init.Channel             | hdma->Init.Direction        |\r\n          hdma->Init.PeriphInc           | hdma->Init.MemInc           |\r\n          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |\r\n          hdma->Init.Mode                | hdma->Init.Priority;\r\n\r\n  /* the Memory burst and peripheral burst are not used when the FIFO is disabled */\r\n  if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)\r\n  {\r\n    /* Get memory burst and peripheral burst */\r\n    tmp |=  hdma->Init.MemBurst | hdma->Init.PeriphBurst;\r\n  }\r\n  \r\n  /* Write to DMA Stream CR register */\r\n  hdma->Instance->CR = tmp;  \r\n\r\n  /* Get the FCR register value */\r\n  tmp = hdma->Instance->FCR;\r\n\r\n  /* Clear Direct mode and FIFO threshold bits */\r\n  tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);\r\n\r\n  /* Prepare the DMA Stream FIFO configuration */\r\n  tmp |= hdma->Init.FIFOMode;\r\n\r\n  /* The FIFO threshold is not used when the FIFO mode is disabled */\r\n  if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)\r\n  {\r\n    /* Get the FIFO threshold */\r\n    tmp |= hdma->Init.FIFOThreshold;\r\n    \r\n    /* Check compatibility between FIFO threshold level and size of the memory burst */\r\n    /* for INCR4, INCR8, INCR16 bursts */\r\n    if (hdma->Init.MemBurst != DMA_MBURST_SINGLE)\r\n    {\r\n      if (DMA_CheckFifoParam(hdma) != HAL_OK)\r\n      {\r\n        /* Update error code */\r\n        hdma->ErrorCode = HAL_DMA_ERROR_PARAM;\r\n        \r\n        /* Change the DMA state */\r\n        hdma->State = HAL_DMA_STATE_READY;\r\n        \r\n        return HAL_ERROR; \r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Write to DMA Stream FCR */\r\n  hdma->Instance->FCR = tmp;\r\n\r\n  /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate\r\n     DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */\r\n  regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);\r\n  \r\n  /* Clear all interrupt flags */\r\n  regs->IFCR = 0x3FU << hdma->StreamIndex;\r\n\r\n  /* Initialize the error code */\r\n  hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r\n                                                                                     \r\n  /* Initialize the DMA state */\r\n  hdma->State = HAL_DMA_STATE_READY;\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the DMA peripheral \r\n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified DMA Stream.  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)\r\n{\r\n  DMA_Base_Registers *regs;\r\n\r\n  /* Check the DMA peripheral state */\r\n  if(hdma == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Check the DMA peripheral state */\r\n  if(hdma->State == HAL_DMA_STATE_BUSY)\r\n  {\r\n    /* Return error status */\r\n    return HAL_BUSY;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));\r\n\r\n  /* Disable the selected DMA Streamx */\r\n  __HAL_DMA_DISABLE(hdma);\r\n\r\n  /* Reset DMA Streamx control register */\r\n  hdma->Instance->CR   = 0U;\r\n\r\n  /* Reset DMA Streamx number of data to transfer register */\r\n  hdma->Instance->NDTR = 0U;\r\n\r\n  /* Reset DMA Streamx peripheral address register */\r\n  hdma->Instance->PAR  = 0U;\r\n\r\n  /* Reset DMA Streamx memory 0 address register */\r\n  hdma->Instance->M0AR = 0U;\r\n  \r\n  /* Reset DMA Streamx memory 1 address register */\r\n  hdma->Instance->M1AR = 0U;\r\n  \r\n  /* Reset DMA Streamx FIFO control register */\r\n  hdma->Instance->FCR  = (uint32_t)0x00000021U;\r\n  \r\n  /* Get DMA steam Base Address */  \r\n  regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);\r\n  \r\n  /* Clear all interrupt flags at correct offset within the register */\r\n  regs->IFCR = 0x3FU << hdma->StreamIndex;\r\n  \r\n  /* Clean all callbacks */\r\n  hdma->XferCpltCallback = NULL;\r\n  hdma->XferHalfCpltCallback = NULL;\r\n  hdma->XferM1CpltCallback = NULL;\r\n  hdma->XferM1HalfCpltCallback = NULL;\r\n  hdma->XferErrorCallback = NULL;\r\n  hdma->XferAbortCallback = NULL;  \r\n\r\n  /* Reset the error code */\r\n  hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r\n\r\n  /* Reset the DMA state */\r\n  hdma->State = HAL_DMA_STATE_RESET;\r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hdma);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup DMA_Exported_Functions_Group2\r\n  *\r\n@verbatim   \r\n ===============================================================================\r\n                      #####  IO operation functions  #####\r\n ===============================================================================\r\n    [..]  This section provides functions allowing to:\r\n      (+) Configure the source, destination address and data length and Start DMA transfer\r\n      (+) Configure the source, destination address and data length and \r\n          Start DMA transfer with interrupt\r\n      (+) Abort DMA transfer\r\n      (+) Poll for transfer complete\r\n      (+) Handle DMA interrupt request  \r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Starts the DMA Transfer.\r\n  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains\r\n  *                     the configuration information for the specified DMA Stream.\r\n  * @param  SrcAddress The source memory Buffer address\r\n  * @param  DstAddress The destination memory Buffer address\r\n  * @param  DataLength The length of data to be transferred from source to destination\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_DMA_BUFFER_SIZE(DataLength));\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hdma);\r\n\r\n  if(HAL_DMA_STATE_READY == hdma->State)\r\n  {\r\n    /* Change DMA peripheral state */\r\n    hdma->State = HAL_DMA_STATE_BUSY;\r\n    \r\n    /* Initialize the error code */\r\n    hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r\n    \r\n    /* Configure the source, destination address and the data length */\r\n    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);\r\n\r\n    /* Enable the Peripheral */\r\n    __HAL_DMA_ENABLE(hdma);\r\n  }\r\n  else\r\n  {\r\n    /* Process unlocked */\r\n    __HAL_UNLOCK(hdma);\r\n    \r\n    /* Return error status */\r\n    status = HAL_BUSY;\r\n  } \r\n  return status; \r\n}\r\n\r\n/**\r\n  * @brief  Start the DMA Transfer with interrupt enabled.\r\n  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains\r\n  *                     the configuration information for the specified DMA Stream.  \r\n  * @param  SrcAddress The source memory Buffer address\r\n  * @param  DstAddress The destination memory Buffer address\r\n  * @param  DataLength The length of data to be transferred from source to destination\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* calculate DMA base and stream number */\r\n  DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_DMA_BUFFER_SIZE(DataLength));\r\n \r\n  /* Process locked */\r\n  __HAL_LOCK(hdma);\r\n  \r\n  if(HAL_DMA_STATE_READY == hdma->State)\r\n  {\r\n    /* Change DMA peripheral state */\r\n    hdma->State = HAL_DMA_STATE_BUSY;\r\n    \r\n    /* Initialize the error code */\r\n    hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r\n    \r\n    /* Configure the source, destination address and the data length */\r\n    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);\r\n    \r\n    /* Clear all interrupt flags at correct offset within the register */\r\n    regs->IFCR = 0x3FU << hdma->StreamIndex;\r\n    \r\n    /* Enable Common interrupts*/\r\n    hdma->Instance->CR  |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;\r\n    hdma->Instance->FCR |= DMA_IT_FE;\r\n    \r\n    if(hdma->XferHalfCpltCallback != NULL)\r\n    {\r\n      hdma->Instance->CR  |= DMA_IT_HT;\r\n    }\r\n    \r\n    /* Enable the Peripheral */\r\n    __HAL_DMA_ENABLE(hdma);\r\n  }\r\n  else\r\n  {\r\n    /* Process unlocked */\r\n    __HAL_UNLOCK(hdma);\t  \r\n    \r\n    /* Return error status */\r\n    status = HAL_BUSY;\r\n  }\r\n  \r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Aborts the DMA Transfer.\r\n  * @param  hdma   pointer to a DMA_HandleTypeDef structure that contains\r\n  *                 the configuration information for the specified DMA Stream.\r\n  *                   \r\n  * @note  After disabling a DMA Stream, a check for wait until the DMA Stream is \r\n  *        effectively disabled is added. If a Stream is disabled \r\n  *        while a data transfer is ongoing, the current data will be transferred\r\n  *        and the Stream will be effectively disabled only after the transfer of\r\n  *        this single data is finished.  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)\r\n{\r\n  /* calculate DMA base and stream number */\r\n  DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;\r\n  \r\n  uint32_t tickstart = HAL_GetTick();\r\n  \r\n  if(hdma->State != HAL_DMA_STATE_BUSY)\r\n  {\r\n    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hdma);\r\n    \r\n    return HAL_ERROR;\r\n  }\r\n  else\r\n  {\r\n    /* Disable all the transfer interrupts */\r\n    hdma->Instance->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);\r\n    hdma->Instance->FCR &= ~(DMA_IT_FE);\r\n    \r\n    if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))\r\n    {\r\n      hdma->Instance->CR  &= ~(DMA_IT_HT);\r\n    }\r\n    \r\n    /* Disable the stream */\r\n    __HAL_DMA_DISABLE(hdma);\r\n    \r\n    /* Check if the DMA Stream is effectively disabled */\r\n    while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)\r\n    {\r\n      /* Check for the Timeout */\r\n      if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)\r\n      {\r\n        /* Update error code */\r\n        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;\r\n        \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hdma);\r\n        \r\n        /* Change the DMA state */\r\n        hdma->State = HAL_DMA_STATE_TIMEOUT;\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n    \r\n    /* Clear all interrupt flags at correct offset within the register */\r\n    regs->IFCR = 0x3FU << hdma->StreamIndex;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hdma);\r\n    \r\n    /* Change the DMA state*/\r\n    hdma->State = HAL_DMA_STATE_READY;\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Aborts the DMA Transfer in Interrupt mode.\r\n  * @param  hdma   pointer to a DMA_HandleTypeDef structure that contains\r\n  *                 the configuration information for the specified DMA Stream.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)\r\n{\r\n  if(hdma->State != HAL_DMA_STATE_BUSY)\r\n  {\r\n    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;\r\n    return HAL_ERROR;\r\n  }\r\n  else\r\n  {\r\n    /* Set Abort State  */\r\n    hdma->State = HAL_DMA_STATE_ABORT;\r\n    \r\n    /* Disable the stream */\r\n    __HAL_DMA_DISABLE(hdma);\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Polling for transfer complete.\r\n  * @param  hdma          pointer to a DMA_HandleTypeDef structure that contains\r\n  *                        the configuration information for the specified DMA Stream.\r\n  * @param  CompleteLevel Specifies the DMA level complete.\r\n  * @note   The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead.\r\n  *         This model could be used for debug purpose.\r\n  * @note   The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). \r\n  * @param  Timeout       Timeout duration.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK; \r\n  uint32_t mask_cpltlevel;\r\n  uint32_t tickstart = HAL_GetTick(); \r\n  uint32_t tmpisr;\r\n  \r\n  /* calculate DMA base and stream number */\r\n  DMA_Base_Registers *regs;\r\n\r\n  if(HAL_DMA_STATE_BUSY != hdma->State)\r\n  {\r\n    /* No transfer ongoing */\r\n    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;\r\n    __HAL_UNLOCK(hdma);\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Polling mode not supported in circular mode and double buffering mode */\r\n  if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET)\r\n  {\r\n    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Get the level transfer complete flag */\r\n  if(CompleteLevel == HAL_DMA_FULL_TRANSFER)\r\n  {\r\n    /* Transfer Complete flag */\r\n    mask_cpltlevel = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;\r\n  }\r\n  else\r\n  {\r\n    /* Half Transfer Complete flag */\r\n    mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;\r\n  }\r\n  \r\n  regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;\r\n  tmpisr = regs->ISR;\r\n  \r\n  while(((tmpisr & mask_cpltlevel) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET))\r\n  {\r\n    /* Check for the Timeout (Not applicable in circular mode)*/\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        /* Update error code */\r\n        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;\r\n\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hdma);\r\n        \r\n        /* Change the DMA state */\r\n        hdma->State = HAL_DMA_STATE_READY;\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n\r\n    /* Get the ISR register value */\r\n    tmpisr = regs->ISR;\r\n\r\n    if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)\r\n    {\r\n      /* Update error code */\r\n      hdma->ErrorCode |= HAL_DMA_ERROR_TE;\r\n      \r\n      /* Clear the transfer error flag */\r\n      regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;\r\n    }\r\n    \r\n    if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)\r\n    {\r\n      /* Update error code */\r\n      hdma->ErrorCode |= HAL_DMA_ERROR_FE;\r\n      \r\n      /* Clear the FIFO error flag */\r\n      regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;\r\n    }\r\n    \r\n    if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)\r\n    {\r\n      /* Update error code */\r\n      hdma->ErrorCode |= HAL_DMA_ERROR_DME;\r\n      \r\n      /* Clear the Direct Mode error flag */\r\n      regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;\r\n    }\r\n  }\r\n  \r\n  if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)\r\n  {\r\n    if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)\r\n    {\r\n      HAL_DMA_Abort(hdma);\r\n    \r\n      /* Clear the half transfer and transfer complete flags */\r\n      regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;\r\n    \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hdma);\r\n\r\n      /* Change the DMA state */\r\n      hdma->State= HAL_DMA_STATE_READY;\r\n\r\n      return HAL_ERROR;\r\n   }\r\n  }\r\n  \r\n  /* Get the level transfer complete flag */\r\n  if(CompleteLevel == HAL_DMA_FULL_TRANSFER)\r\n  {\r\n    /* Clear the half transfer and transfer complete flags */\r\n    regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hdma);\r\n\r\n    hdma->State = HAL_DMA_STATE_READY;\r\n  }\r\n  else\r\n  {\r\n    /* Clear the half transfer flag */\r\n    regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex;\r\n  }\r\n  \r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Handles DMA interrupt request.\r\n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified DMA Stream.  \r\n  * @retval None\r\n  */\r\nvoid HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)\r\n{\r\n  uint32_t tmpisr;\r\n  __IO uint32_t count = 0;\r\n  uint32_t timeout = SystemCoreClock / 9600;\r\n\r\n  /* calculate DMA base and stream number */\r\n  DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;\r\n\r\n  tmpisr = regs->ISR;\r\n\r\n  /* Transfer Error Interrupt management ***************************************/\r\n  if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)\r\n  {\r\n    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)\r\n    {\r\n      /* Disable the transfer error interrupt */\r\n      hdma->Instance->CR  &= ~(DMA_IT_TE);\r\n      \r\n      /* Clear the transfer error flag */\r\n      regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;\r\n      \r\n      /* Update error code */\r\n      hdma->ErrorCode |= HAL_DMA_ERROR_TE;\r\n    }\r\n  }\r\n  /* FIFO Error Interrupt management ******************************************/\r\n  if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)\r\n  {\r\n    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)\r\n    {\r\n      /* Clear the FIFO error flag */\r\n      regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;\r\n\r\n      /* Update error code */\r\n      hdma->ErrorCode |= HAL_DMA_ERROR_FE;\r\n    }\r\n  }\r\n  /* Direct Mode Error Interrupt management ***********************************/\r\n  if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)\r\n  {\r\n    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)\r\n    {\r\n      /* Clear the direct mode error flag */\r\n      regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;\r\n\r\n      /* Update error code */\r\n      hdma->ErrorCode |= HAL_DMA_ERROR_DME;\r\n    }\r\n  }\r\n  /* Half Transfer Complete Interrupt management ******************************/\r\n  if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)\r\n  {\r\n    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)\r\n    {\r\n      /* Clear the half transfer complete flag */\r\n      regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;\r\n      \r\n      /* Multi_Buffering mode enabled */\r\n      if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)\r\n      {\r\n        /* Current memory buffer used is Memory 0 */\r\n        if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)\r\n        {\r\n          if(hdma->XferHalfCpltCallback != NULL)\r\n          {\r\n            /* Half transfer callback */\r\n            hdma->XferHalfCpltCallback(hdma);\r\n          }\r\n        }\r\n        /* Current memory buffer used is Memory 1 */\r\n        else\r\n        {\r\n          if(hdma->XferM1HalfCpltCallback != NULL)\r\n          {\r\n            /* Half transfer callback */\r\n            hdma->XferM1HalfCpltCallback(hdma);\r\n          }\r\n        }\r\n      }\r\n      else\r\n      {\r\n        /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */\r\n        if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)\r\n        {\r\n          /* Disable the half transfer interrupt */\r\n          hdma->Instance->CR  &= ~(DMA_IT_HT);\r\n        }\r\n        \r\n        if(hdma->XferHalfCpltCallback != NULL)\r\n        {\r\n          /* Half transfer callback */\r\n          hdma->XferHalfCpltCallback(hdma);\r\n        }\r\n      }\r\n    }\r\n  }\r\n  /* Transfer Complete Interrupt management ***********************************/\r\n  if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)\r\n  {\r\n    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)\r\n    {\r\n      /* Clear the transfer complete flag */\r\n      regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;\r\n      \r\n      if(HAL_DMA_STATE_ABORT == hdma->State)\r\n      {\r\n        /* Disable all the transfer interrupts */\r\n        hdma->Instance->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);\r\n        hdma->Instance->FCR &= ~(DMA_IT_FE);\r\n        \r\n        if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))\r\n        {\r\n          hdma->Instance->CR  &= ~(DMA_IT_HT);\r\n        }\r\n\r\n        /* Clear all interrupt flags at correct offset within the register */\r\n        regs->IFCR = 0x3FU << hdma->StreamIndex;\r\n\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hdma);\r\n\r\n        /* Change the DMA state */\r\n        hdma->State = HAL_DMA_STATE_READY;\r\n\r\n        if(hdma->XferAbortCallback != NULL)\r\n        {\r\n          hdma->XferAbortCallback(hdma);\r\n        }\r\n        return;\r\n      }\r\n\r\n      if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)\r\n      {\r\n        /* Current memory buffer used is Memory 0 */\r\n        if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)\r\n        {\r\n          if(hdma->XferM1CpltCallback != NULL)\r\n          {\r\n            /* Transfer complete Callback for memory1 */\r\n            hdma->XferM1CpltCallback(hdma);\r\n          }\r\n        }\r\n        /* Current memory buffer used is Memory 1 */\r\n        else\r\n        {\r\n          if(hdma->XferCpltCallback != NULL)\r\n          {\r\n            /* Transfer complete Callback for memory0 */\r\n            hdma->XferCpltCallback(hdma);\r\n          }\r\n        }\r\n      }\r\n      /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */\r\n      else\r\n      {\r\n        if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)\r\n        {\r\n          /* Disable the transfer complete interrupt */\r\n          hdma->Instance->CR  &= ~(DMA_IT_TC);\r\n\r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hdma);\r\n\r\n          /* Change the DMA state */\r\n          hdma->State = HAL_DMA_STATE_READY;\r\n        }\r\n\r\n        if(hdma->XferCpltCallback != NULL)\r\n        {\r\n          /* Transfer complete callback */\r\n          hdma->XferCpltCallback(hdma);\r\n        }\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* manage error case */\r\n  if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)\r\n  {\r\n    if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)\r\n    {\r\n      hdma->State = HAL_DMA_STATE_ABORT;\r\n\r\n      /* Disable the stream */\r\n      __HAL_DMA_DISABLE(hdma);\r\n\r\n      do\r\n      {\r\n        if (++count > timeout)\r\n        {\r\n          break;\r\n        }\r\n      }\r\n      while((hdma->Instance->CR & DMA_SxCR_EN) != RESET);\r\n\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hdma);\r\n\r\n      /* Change the DMA state */\r\n      hdma->State = HAL_DMA_STATE_READY;\r\n    }\r\n\r\n    if(hdma->XferErrorCallback != NULL)\r\n    {\r\n      /* Transfer error callback */\r\n      hdma->XferErrorCallback(hdma);\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Register callbacks\r\n  * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains\r\n  *                               the configuration information for the specified DMA Stream.\r\n  * @param  CallbackID           User Callback identifer\r\n  *                               a DMA_HandleTypeDef structure as parameter.\r\n  * @param  pCallback            pointer to private callbacsk function which has pointer to \r\n  *                               a DMA_HandleTypeDef structure as parameter.\r\n  * @retval HAL status\r\n  */                      \r\nHAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))\r\n{\r\n\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hdma);\r\n\r\n  if(HAL_DMA_STATE_READY == hdma->State)\r\n  {\r\n    switch (CallbackID)\r\n    {\r\n    case  HAL_DMA_XFER_CPLT_CB_ID:\r\n      hdma->XferCpltCallback = pCallback;\r\n      break;\r\n\r\n    case  HAL_DMA_XFER_HALFCPLT_CB_ID:\r\n      hdma->XferHalfCpltCallback = pCallback;\r\n      break;\r\n\r\n    case  HAL_DMA_XFER_M1CPLT_CB_ID:\r\n      hdma->XferM1CpltCallback = pCallback;\r\n      break;\r\n\r\n    case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:\r\n      hdma->XferM1HalfCpltCallback = pCallback;\r\n      break;\r\n\r\n    case  HAL_DMA_XFER_ERROR_CB_ID:\r\n      hdma->XferErrorCallback = pCallback;\r\n      break;\r\n\r\n    case  HAL_DMA_XFER_ABORT_CB_ID:\r\n      hdma->XferAbortCallback = pCallback;\r\n      break;\r\n\r\n    default:\r\n      break;\r\n    }\r\n  }\r\n  else\r\n  {\r\n    /* Return error status */\r\n    status =  HAL_ERROR;\r\n  }\r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hdma);\r\n  \r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  UnRegister callbacks\r\n  * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains\r\n  *                               the configuration information for the specified DMA Stream.\r\n  * @param  CallbackID           User Callback identifer\r\n  *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.\r\n  * @retval HAL status\r\n  */              \r\nHAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hdma);\r\n  \r\n  if(HAL_DMA_STATE_READY == hdma->State)\r\n  {\r\n    switch (CallbackID)\r\n    {\r\n    case  HAL_DMA_XFER_CPLT_CB_ID:\r\n      hdma->XferCpltCallback = NULL;\r\n      break;\r\n      \r\n    case  HAL_DMA_XFER_HALFCPLT_CB_ID:\r\n      hdma->XferHalfCpltCallback = NULL;\r\n      break;\r\n      \r\n    case  HAL_DMA_XFER_M1CPLT_CB_ID:\r\n      hdma->XferM1CpltCallback = NULL;\r\n      break;\r\n      \r\n    case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:\r\n      hdma->XferM1HalfCpltCallback = NULL;\r\n      break;\r\n      \r\n    case  HAL_DMA_XFER_ERROR_CB_ID:\r\n      hdma->XferErrorCallback = NULL;\r\n      break;\r\n      \r\n    case  HAL_DMA_XFER_ABORT_CB_ID:\r\n      hdma->XferAbortCallback = NULL;\r\n      break; \r\n      \r\n    case   HAL_DMA_XFER_ALL_CB_ID:\r\n      hdma->XferCpltCallback = NULL;\r\n      hdma->XferHalfCpltCallback = NULL;\r\n      hdma->XferM1CpltCallback = NULL;\r\n      hdma->XferM1HalfCpltCallback = NULL;\r\n      hdma->XferErrorCallback = NULL;\r\n      hdma->XferAbortCallback = NULL;\r\n      break; \r\n      \r\n    default:\r\n      status = HAL_ERROR;\r\n      break;\r\n    }\r\n  }\r\n  else\r\n  {\r\n    status = HAL_ERROR;\r\n  }\r\n  \r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hdma);\r\n  \r\n  return status;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup DMA_Exported_Functions_Group3\r\n  *\r\n@verbatim\r\n ===============================================================================\r\n                    ##### State and Errors functions #####\r\n ===============================================================================\r\n    [..]\r\n    This subsection provides functions allowing to\r\n      (+) Check the DMA state\r\n      (+) Get error code\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Returns the DMA state.\r\n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified DMA Stream.\r\n  * @retval HAL state\r\n  */\r\nHAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)\r\n{\r\n  return hdma->State;\r\n}\r\n\r\n/**\r\n  * @brief  Return the DMA error code\r\n  * @param  hdma  pointer to a DMA_HandleTypeDef structure that contains\r\n  *              the configuration information for the specified DMA Stream.\r\n  * @retval DMA Error Code\r\n  */\r\nuint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)\r\n{\r\n  return hdma->ErrorCode;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup DMA_Private_Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Sets the DMA Transfer parameter.\r\n  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains\r\n  *                     the configuration information for the specified DMA Stream.\r\n  * @param  SrcAddress The source memory Buffer address\r\n  * @param  DstAddress The destination memory Buffer address\r\n  * @param  DataLength The length of data to be transferred from source to destination\r\n  * @retval HAL status\r\n  */\r\nstatic void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r\n{\r\n  /* Clear DBM bit */\r\n  hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);\r\n\r\n  /* Configure DMA Stream data length */\r\n  hdma->Instance->NDTR = DataLength;\r\n\r\n  /* Memory to Peripheral */\r\n  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)\r\n  {\r\n    /* Configure DMA Stream destination address */\r\n    hdma->Instance->PAR = DstAddress;\r\n\r\n    /* Configure DMA Stream source address */\r\n    hdma->Instance->M0AR = SrcAddress;\r\n  }\r\n  /* Peripheral to Memory */\r\n  else\r\n  {\r\n    /* Configure DMA Stream source address */\r\n    hdma->Instance->PAR = SrcAddress;\r\n\r\n    /* Configure DMA Stream destination address */\r\n    hdma->Instance->M0AR = DstAddress;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Returns the DMA Stream base address depending on stream number\r\n  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains\r\n  *                     the configuration information for the specified DMA Stream. \r\n  * @retval Stream base address\r\n  */\r\nstatic uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)\r\n{\r\n  uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;\r\n  \r\n  /* lookup table for necessary bitshift of flags within status registers */\r\n  static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};\r\n  hdma->StreamIndex = flagBitshiftOffset[stream_number];\r\n  \r\n  if (stream_number > 3U)\r\n  {\r\n    /* return pointer to HISR and HIFCR */\r\n    hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U);\r\n  }\r\n  else\r\n  {\r\n    /* return pointer to LISR and LIFCR */\r\n    hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU));\r\n  }\r\n  \r\n  return hdma->StreamBaseAddress;\r\n}\r\n\r\n/**\r\n  * @brief  Check compatibility between FIFO threshold level and size of the memory burst\r\n  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains\r\n  *                     the configuration information for the specified DMA Stream. \r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  uint32_t tmp = hdma->Init.FIFOThreshold;\r\n  \r\n  /* Memory Data size equal to Byte */\r\n  if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)\r\n  {\r\n    switch (tmp)\r\n    {\r\n    case DMA_FIFO_THRESHOLD_1QUARTERFULL:\r\n    case DMA_FIFO_THRESHOLD_3QUARTERSFULL:\r\n      if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)\r\n      {\r\n        status = HAL_ERROR;\r\n      }\r\n      break;\r\n    case DMA_FIFO_THRESHOLD_HALFFULL:\r\n      if (hdma->Init.MemBurst == DMA_MBURST_INC16)\r\n      {\r\n        status = HAL_ERROR;\r\n      }\r\n      break;\r\n    case DMA_FIFO_THRESHOLD_FULL:\r\n      break;\r\n    default:\r\n      break;\r\n    }\r\n  }\r\n  \r\n  /* Memory Data size equal to Half-Word */\r\n  else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)\r\n  {\r\n    switch (tmp)\r\n    {\r\n    case DMA_FIFO_THRESHOLD_1QUARTERFULL:\r\n    case DMA_FIFO_THRESHOLD_3QUARTERSFULL:\r\n      status = HAL_ERROR;\r\n      break;\r\n    case DMA_FIFO_THRESHOLD_HALFFULL:\r\n      if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)\r\n      {\r\n        status = HAL_ERROR;\r\n      }\r\n      break;\r\n    case DMA_FIFO_THRESHOLD_FULL:\r\n      if (hdma->Init.MemBurst == DMA_MBURST_INC16)\r\n      {\r\n        status = HAL_ERROR;\r\n      }\r\n      break;   \r\n    default:\r\n      break;\r\n    }\r\n  }\r\n  \r\n  /* Memory Data size equal to Word */\r\n  else\r\n  {\r\n    switch (tmp)\r\n    {\r\n    case DMA_FIFO_THRESHOLD_1QUARTERFULL:\r\n    case DMA_FIFO_THRESHOLD_HALFFULL:\r\n    case DMA_FIFO_THRESHOLD_3QUARTERSFULL:\r\n      status = HAL_ERROR;\r\n      break;\r\n    case DMA_FIFO_THRESHOLD_FULL:\r\n      if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)\r\n      {\r\n        status = HAL_ERROR;\r\n      }\r\n      break;\r\n    default:\r\n      break;\r\n    }\r\n  } \r\n  \r\n  return status; \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_DMA_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_dma2d.c\r\n  * @author  MCD Application Team\r\n  * @brief   DMA2D HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the DMA2D peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + IO operation functions\r\n  *           + Peripheral Control functions \r\n  *           + Peripheral State and Errors functions\r\n  *\r\n  @verbatim\r\n  ==============================================================================\r\n                        ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]\r\n      (#) Program the required configuration through the following parameters:   \r\n          the transfer mode, the output color mode and the output offset using \r\n          HAL_DMA2D_Init() function.\r\n\r\n      (#) Program the required configuration through the following parameters:   \r\n          the input color mode, the input color, the input alpha value, the alpha mode,\r\n          the red/blue swap mode, the inverted alpha mode and the input offset using \r\n          HAL_DMA2D_ConfigLayer() function for foreground or/and background layer.\r\n          \r\n     *** Polling mode IO operation ***\r\n     =================================   \r\n    [..]        \r\n       (#) Configure pdata parameter (explained hereafter), destination and data length \r\n           and enable the transfer using HAL_DMA2D_Start(). \r\n       (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage\r\n           user can specify the value of timeout according to his end application.\r\n               \r\n     *** Interrupt mode IO operation ***    \r\n     ===================================\r\n     [..] \r\n       (#) Configure pdata parameter, destination and data length and enable \r\n           the transfer using HAL_DMA2D_Start_IT(). \r\n       (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine.\r\n       (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can \r\n           add his own function by customization of function pointer XferCpltCallback (member \r\n           of DMA2D handle structure). \r\n       (#) In case of error, the HAL_DMA2D_IRQHandler() function will call the callback \r\n           XferErrorCallback.            \r\n\r\n         -@-   In Register-to-Memory transfer mode, pdata parameter is the register\r\n               color, in Memory-to-memory or Memory-to-Memory with pixel format\r\n               conversion pdata is the source address.\r\n\r\n         -@-   Configure the foreground source address, the background source address, \r\n               the destination and data length then Enable the transfer using \r\n               HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()\r\n               in interrupt mode.\r\n               \r\n         -@-   HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions\r\n               are used if the memory to memory with blending transfer mode is selected.\r\n                   \r\n      (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling\r\n          mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode.\r\n\r\n      (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent()\r\n          \r\n      (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two \r\n          consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime()\r\n          and enable/disable the functionality  with the APIs HAL_DMA2D_EnableDeadTime() or\r\n          HAL_DMA2D_DisableDeadTime().          \r\n   \r\n      (#) The transfer can be suspended, resumed and aborted using the following\r\n          functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().\r\n          \r\n      (#) The CLUT loading can be suspended, resumed and aborted using the following\r\n          functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(), \r\n          HAL_DMA2D_CLUTLoading_Abort().                \r\n                     \r\n      (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState().   \r\n      \r\n      (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError().                         \r\n\r\n     *** DMA2D HAL driver macros list ***\r\n     ============================================= \r\n     [..]\r\n       Below the list of most used macros in DMA2D HAL driver :\r\n       \r\n      (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.\r\n      (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.\r\n      (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.\r\n      (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.\r\n      (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.\r\n      (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not.     \r\n     \r\n     [..] \r\n      (@) You can refer to the DMA2D HAL driver header file for more useful macros\r\n                                  \r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup DMA2D  DMA2D\r\n  * @brief DMA2D HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_DMA2D_MODULE_ENABLED\r\n#if defined (DMA2D)\r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @defgroup DMA2D_Private_Constants DMA2D Private Constants\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup DMA2D_TimeOut DMA2D Time Out \r\n  * @{\r\n  */  \r\n#define DMA2D_TIMEOUT_ABORT           ((uint32_t)1000)  /*!<  1s  */\r\n#define DMA2D_TIMEOUT_SUSPEND         ((uint32_t)1000)  /*!<  1s  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/** @addtogroup DMA2D_Private_Functions_Prototypes\r\n  * @{\r\n  */\r\nstatic void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions\r\n *  @brief   Initialization and Configuration functions\r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                ##### Initialization and Configuration functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Initialize and configure the DMA2D\r\n      (+) De-initialize the DMA2D \r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n    \r\n/**\r\n  * @brief  Initialize the DMA2D according to the specified\r\n  *         parameters in the DMA2D_InitTypeDef and create the associated handle.\r\n  * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                 the configuration information for the DMA2D.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)\r\n{ \r\n  /* Check the DMA2D peripheral state */\r\n  if(hdma2d == NULL)\r\n  {\r\n     return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));\r\n  assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));\r\n  assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));\r\n  assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));\r\n\r\n  if(hdma2d->State == HAL_DMA2D_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    hdma2d->Lock = HAL_UNLOCKED;\r\n    /* Init the low level hardware */\r\n    HAL_DMA2D_MspInit(hdma2d);\r\n  }\r\n  \r\n  /* Change DMA2D peripheral state */\r\n  hdma2d->State = HAL_DMA2D_STATE_BUSY;  \r\n\r\n  /* DMA2D CR register configuration -------------------------------------------*/\r\n  MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);\r\n\r\n  /* DMA2D OPFCCR register configuration ---------------------------------------*/\r\n  MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);\r\n\r\n  /* DMA2D OOR register configuration ------------------------------------------*/  \r\n  MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);  \r\n\r\n#if defined (DMA2D_OPFCCR_AI)\r\n  /* DMA2D OPFCCR AI fields setting (Output Alpha Inversion)*/\r\n  MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_AI, (hdma2d->Init.AlphaInverted << DMA2D_OPFCCR_AI_Pos));\r\n#endif /* DMA2D_OPFCCR_AI */ \r\n  \r\n#if defined (DMA2D_OPFCCR_RBS) \r\n  MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_RBS,(hdma2d->Init.RedBlueSwap << DMA2D_OPFCCR_RBS_Pos));\r\n#endif /* DMA2D_OPFCCR_RBS */\r\n  \r\n\r\n  /* Update error code */\r\n  hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;\r\n\r\n  /* Initialize the DMA2D state*/\r\n  hdma2d->State  = HAL_DMA2D_STATE_READY;\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Deinitializes the DMA2D peripheral registers to their default reset\r\n  *         values.\r\n  * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                 the configuration information for the DMA2D.\r\n  * @retval None\r\n  */\r\n\r\nHAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)\r\n{\r\n  \r\n  /* Check the DMA2D peripheral state */\r\n  if(hdma2d == NULL)\r\n  {\r\n     return HAL_ERROR;\r\n  }\r\n  \r\n  /* Before aborting any DMA2D transfer or CLUT loading, check\r\n     first whether or not DMA2D clock is enabled */\r\n  if (__HAL_RCC_DMA2D_IS_CLK_ENABLED())\r\n  {\r\n    /* Abort DMA2D transfer if any */\r\n    if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)\r\n    {\r\n      if (HAL_DMA2D_Abort(hdma2d) != HAL_OK)\r\n      {\r\n        /* Issue when aborting DMA2D transfer */       \r\n        return HAL_ERROR;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* Abort background CLUT loading if any */\r\n      if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)\r\n      {  \r\n        if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0) != HAL_OK)        \r\n        {\r\n          /* Issue when aborting background CLUT loading */     \r\n          return HAL_ERROR;\r\n        }\r\n      }\r\n      else\r\n      {\r\n        /* Abort foreground CLUT loading if any */\r\n        if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)\r\n        {\r\n          if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1) != HAL_OK)  \r\n          {\r\n            /* Issue when aborting foreground CLUT loading */     \r\n            return HAL_ERROR;\r\n          }        \r\n        }\r\n      }\r\n    }\r\n  }\r\n\r\n            \r\n  /* Carry on with de-initialization of low level hardware */\r\n  HAL_DMA2D_MspDeInit(hdma2d);\r\n  \r\n  /* Reset DMA2D control registers*/\r\n  hdma2d->Instance->CR = 0;\r\n  hdma2d->Instance->FGOR = 0;\r\n  hdma2d->Instance->BGOR = 0;  \r\n  hdma2d->Instance->FGPFCCR = 0;\r\n  hdma2d->Instance->BGPFCCR = 0;  \r\n  hdma2d->Instance->OPFCCR = 0;\r\n\r\n  /* Update error code */\r\n  hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;\r\n  \r\n  /* Initialize the DMA2D state*/\r\n  hdma2d->State  = HAL_DMA2D_STATE_RESET;\r\n  \r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hdma2d);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the DMA2D MSP.\r\n  * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                 the configuration information for the DMA2D.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdma2d);\r\n\r\n  /* NOTE : This function should not be modified; when the callback is needed,\r\n            the HAL_DMA2D_MspInit can be implemented in the user file.\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the DMA2D MSP.\r\n  * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                 the configuration information for the DMA2D.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdma2d);\r\n\r\n  /* NOTE : This function should not be modified; when the callback is needed,\r\n            the HAL_DMA2D_MspDeInit can be implemented in the user file.\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions\r\n *  @brief   IO operation functions  \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                      #####  IO operation functions  #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Configure the pdata, destination address and data size then \r\n          start the DMA2D transfer.\r\n      (+) Configure the source for foreground and background, destination address \r\n          and data size then start a MultiBuffer DMA2D transfer.\r\n      (+) Configure the pdata, destination address and data size then \r\n          start the DMA2D transfer with interrupt.\r\n      (+) Configure the source for foreground and background, destination address \r\n          and data size then start a MultiBuffer DMA2D transfer with interrupt.\r\n      (+) Abort DMA2D transfer.\r\n      (+) Suspend DMA2D transfer.\r\n      (+) Resume DMA2D transfer. \r\n      (+) Enable CLUT transfer.      \r\n      (+) Configure CLUT loading then start transfer in polling mode.\r\n      (+) Configure CLUT loading then start transfer in interrupt mode.\r\n      (+) Abort DMA2D CLUT loading.\r\n      (+) Suspend DMA2D CLUT loading.\r\n      (+) Resume DMA2D CLUT loading. \r\n      (+) Poll for transfer complete.\r\n      (+) handle DMA2D interrupt request.\r\n      (+) Transfer watermark callback.\r\n      (+) CLUT Transfer Complete callback.\r\n        \r\n        \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Start the DMA2D Transfer.\r\n  * @param  hdma2d     Pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                     the configuration information for the DMA2D.  \r\n  * @param  pdata      Configure the source memory Buffer address if \r\n  *                     Memory-to-Memory or Memory-to-Memory with pixel format \r\n  *                     conversion mode is selected, or configure \r\n  *                     the color value if Register-to-Memory mode is selected.\r\n  * @param  DstAddress The destination memory Buffer address.\r\n  * @param  Width      The width of data to be transferred from source to destination (expressed in number of pixels per line).\r\n  * @param  Height     The height of data to be transferred from source to destination (expressed in number of lines).\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,  uint32_t Height)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_DMA2D_LINE(Height));\r\n  assert_param(IS_DMA2D_PIXEL(Width));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hdma2d);\r\n\r\n  /* Change DMA2D peripheral state */\r\n  hdma2d->State = HAL_DMA2D_STATE_BUSY;\r\n  \r\n  /* Configure the source, destination address and the data size */\r\n  DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);\r\n\r\n  /* Enable the Peripheral */\r\n  __HAL_DMA2D_ENABLE(hdma2d);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Start the DMA2D Transfer with interrupt enabled.\r\n  * @param  hdma2d     Pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                     the configuration information for the DMA2D.  \r\n  * @param  pdata      Configure the source memory Buffer address if \r\n  *                     the Memory-to-Memory or Memory-to-Memory with pixel format \r\n  *                     conversion mode is selected, or configure \r\n  *                     the color value if Register-to-Memory mode is selected.\r\n  * @param  DstAddress The destination memory Buffer address.\r\n  * @param  Width      The width of data to be transferred from source to destination (expressed in number of pixels per line).\r\n  * @param  Height     The height of data to be transferred from source to destination (expressed in number of lines).\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,  uint32_t Height)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_DMA2D_LINE(Height));\r\n  assert_param(IS_DMA2D_PIXEL(Width));\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hdma2d);\r\n\r\n  /* Change DMA2D peripheral state */\r\n  hdma2d->State = HAL_DMA2D_STATE_BUSY;\r\n\r\n  /* Configure the source, destination address and the data size */\r\n  DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);\r\n\r\n  /* Enable the transfer complete, transfer error and configuration error interrupts */\r\n  __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);\r\n\r\n  /* Enable the Peripheral */\r\n  __HAL_DMA2D_ENABLE(hdma2d);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Start the multi-source DMA2D Transfer.\r\n  * @param  hdma2d      Pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                      the configuration information for the DMA2D.  \r\n  * @param  SrcAddress1 The source memory Buffer address for the foreground layer.\r\n  * @param  SrcAddress2 The source memory Buffer address for the background layer.\r\n  * @param  DstAddress  The destination memory Buffer address.\r\n  * @param  Width       The width of data to be transferred from source to destination (expressed in number of pixels per line).\r\n  * @param  Height      The height of data to be transferred from source to destination (expressed in number of lines).\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t  SrcAddress2, uint32_t DstAddress, uint32_t Width,  uint32_t Height)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_DMA2D_LINE(Height));\r\n  assert_param(IS_DMA2D_PIXEL(Width));  \r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hdma2d);\r\n\r\n  /* Change DMA2D peripheral state */\r\n  hdma2d->State = HAL_DMA2D_STATE_BUSY; \r\n\r\n  /* Configure DMA2D Stream source2 address */\r\n  WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);\r\n\r\n  /* Configure the source, destination address and the data size */\r\n  DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);\r\n\r\n  /* Enable the Peripheral */\r\n  __HAL_DMA2D_ENABLE(hdma2d);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Start the multi-source DMA2D Transfer with interrupt enabled.\r\n  * @param  hdma2d     Pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                     the configuration information for the DMA2D.  \r\n  * @param  SrcAddress1 The source memory Buffer address for the foreground layer.\r\n  * @param  SrcAddress2 The source memory Buffer address for the background layer.\r\n  * @param  DstAddress  The destination memory Buffer address.\r\n  * @param  Width       The width of data to be transferred from source to destination (expressed in number of pixels per line).\r\n  * @param  Height      The height of data to be transferred from source to destination (expressed in number of lines).         \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t  SrcAddress2, uint32_t DstAddress, uint32_t Width,  uint32_t Height)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_DMA2D_LINE(Height));\r\n  assert_param(IS_DMA2D_PIXEL(Width));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hdma2d);\r\n\r\n  /* Change DMA2D peripheral state */\r\n  hdma2d->State = HAL_DMA2D_STATE_BUSY;\r\n \r\n  /* Configure DMA2D Stream source2 address */\r\n  WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);\r\n\r\n  /* Configure the source, destination address and the data size */\r\n  DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);\r\n  \r\n  /* Enable the transfer complete, transfer error and configuration error interrupts */\r\n  __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);\r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_DMA2D_ENABLE(hdma2d);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Abort the DMA2D Transfer.\r\n  * @param  hdma2d  pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                  the configuration information for the DMA2D.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)\r\n{\r\n  uint32_t tickstart = 0;\r\n\r\n  /* Abort the DMA2D transfer */\r\n  /* START bit is reset to make sure not to set it again, in the event the HW clears it\r\n     between the register read and the register write by the CPU (writing 0 has no \r\n     effect on START bitvalue) */\r\n   MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT);\r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Check if the DMA2D is effectively disabled */\r\n  while((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)\r\n  {\r\n    if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)\r\n    {\r\n      /* Update error code */\r\n      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;\r\n      \r\n      /* Change the DMA2D state */\r\n      hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;\r\n      \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hdma2d);\r\n      \r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n\r\n  /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */\r\n  __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);  \r\n\r\n  /* Change the DMA2D state*/\r\n  hdma2d->State = HAL_DMA2D_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hdma2d);  \r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Suspend the DMA2D Transfer.\r\n  * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                 the configuration information for the DMA2D. \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)\r\n{\r\n  uint32_t tickstart = 0;\r\n\r\n  /* Suspend the DMA2D transfer */\r\n  /* START bit is reset to make sure not to set it again, in the event the HW clears it\r\n     between the register read and the register write by the CPU (writing 0 has no \r\n     effect on START bitvalue). */\r\n  MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP);\r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Check if the DMA2D is effectively suspended */\r\n  while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \\\r\n    && ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START))\r\n  {\r\n    if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)\r\n    {\r\n      /* Update error code */\r\n      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;\r\n      \r\n      /* Change the DMA2D state */\r\n      hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;\r\n      \r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  \r\n   /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */\r\n  if ((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)\r\n  {    \r\n    hdma2d->State = HAL_DMA2D_STATE_SUSPEND;\r\n  }\r\n  else\r\n  {\r\n    /* Make sure SUSP bit is cleared since it is meaningless \r\n       when no tranfer is on-going */\r\n    CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Resume the DMA2D Transfer.\r\n  * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                 the configuration information for the DMA2D.  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)\r\n{\r\n  /* Check the SUSP and START bits */\r\n  if((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))\r\n  {\r\n    /* Ongoing transfer is suspended: change the DMA2D state before resuming */\r\n    hdma2d->State = HAL_DMA2D_STATE_BUSY;\r\n  }\r\n\r\n  /* Resume the DMA2D transfer */\r\n  /* START bit is reset to make sure not to set it again, in the event the HW clears it\r\n     between the register read and the register write by the CPU (writing 0 has no \r\n     effect on START bitvalue). */\r\n  CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START));  \r\n\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Enable the DMA2D CLUT Transfer.\r\n  * @param  hdma2d   Pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                   the configuration information for the DMA2D.\r\n  * @param  LayerIdx DMA2D Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0(background) / 1(foreground)\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)\r\n{  \r\n  /* Check the parameters */\r\n  assert_param(IS_DMA2D_LAYER(LayerIdx));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hdma2d);\r\n  \r\n  /* Change DMA2D peripheral state */\r\n  hdma2d->State = HAL_DMA2D_STATE_BUSY;  \r\n  \r\n  if(LayerIdx == 0)\r\n  {\r\n    /* Enable the background CLUT loading */\r\n    SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);\r\n  }\r\n  else\r\n  {\r\n    /* Enable the foreground CLUT loading */\r\n    SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);    \r\n  }\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Start DMA2D CLUT Loading.\r\n  * @param  hdma2d   Pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                   the configuration information for the DMA2D.\r\n  * @param  CLUTCfg  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains\r\n  *                   the configuration information for the color look up table.\r\n  * @param  LayerIdx DMA2D Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0(background) / 1(foreground)\r\n  * @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT().\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_DMA2D_LAYER(LayerIdx));   \r\n  assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));\r\n  assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hdma2d);\r\n  \r\n  /* Change DMA2D peripheral state */\r\n  hdma2d->State = HAL_DMA2D_STATE_BUSY;   \r\n    \r\n  /* Configure the CLUT of the background DMA2D layer */\r\n  if(LayerIdx == 0)\r\n  {\r\n    /* Write background CLUT memory address */\r\n    WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);\r\n    \r\n    /* Write background CLUT size and CLUT color mode */\r\n    MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), \r\n            ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));\r\n\r\n    /* Enable the CLUT loading for the background */\r\n    SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);\r\n  }\r\n  /* Configure the CLUT of the foreground DMA2D layer */\r\n  else\r\n  {\r\n    /* Write foreground CLUT memory address */\r\n    WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);\r\n    \r\n    /* Write foreground CLUT size and CLUT color mode */\r\n    MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), \r\n            ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));\r\n    \r\n /* Enable the CLUT loading for the foreground */\r\n    SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);  \r\n  }\r\n    \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Start DMA2D CLUT Loading with interrupt enabled.\r\n  * @param  hdma2d   Pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                   the configuration information for the DMA2D.\r\n  * @param  CLUTCfg  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains\r\n  *                   the configuration information for the color look up table.\r\n  * @param  LayerIdx DMA2D Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0(background) / 1(foreground)\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_DMA2D_LAYER(LayerIdx));   \r\n  assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));\r\n  assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hdma2d);\r\n  \r\n  /* Change DMA2D peripheral state */\r\n  hdma2d->State = HAL_DMA2D_STATE_BUSY;   \r\n    \r\n  /* Configure the CLUT of the background DMA2D layer */\r\n  if(LayerIdx == 0)\r\n  {\r\n    /* Write background CLUT memory address */\r\n    WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);\r\n    \r\n    /* Write background CLUT size and CLUT color mode */\r\n    MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), \r\n            ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));\r\n            \r\n    /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */\r\n    __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);            \r\n\r\n    /* Enable the CLUT loading for the background */\r\n    SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);\r\n  }\r\n  /* Configure the CLUT of the foreground DMA2D layer */\r\n  else\r\n  {\r\n    /* Write foreground CLUT memory address */\r\n    WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);\r\n    \r\n    /* Write foreground CLUT size and CLUT color mode */\r\n    MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), \r\n            ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));\r\n            \r\n    /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */\r\n    __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);                   \r\n    \r\n    /* Enable the CLUT loading for the foreground */\r\n    SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);  \r\n  }\r\n    \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Abort the DMA2D CLUT loading.\r\n  * @param  hdma2d  Pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                  the configuration information for the DMA2D.\r\n  * @param  LayerIdx DMA2D Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0(background) / 1(foreground)  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)\r\n{\r\n  uint32_t tickstart  = 0;\r\n  __IO uint32_t * reg =  &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */\r\n\r\n  /* Abort the CLUT loading */\r\n  SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);\r\n  \r\n  /* If foreground CLUT loading is considered, update local variables */ \r\n  if(LayerIdx == 1)\r\n  {\r\n    reg  = &(hdma2d->Instance->FGPFCCR);\r\n  }\r\n\r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n \r\n  /* Check if the CLUT loading is aborted */          \r\n  while((*reg & DMA2D_BGPFCCR_START) != RESET)\r\n  {\r\n    if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)\r\n    {\r\n      /* Update error code */\r\n      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;\r\n      \r\n      /* Change the DMA2D state */\r\n      hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;\r\n      \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hdma2d);\r\n      \r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n\r\n  /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */\r\n  __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);      \r\n   \r\n  /* Change the DMA2D state*/\r\n  hdma2d->State = HAL_DMA2D_STATE_READY;\r\n     \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hdma2d);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Suspend the DMA2D CLUT loading.\r\n  * @param  hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                 the configuration information for the DMA2D. \r\n  * @param  LayerIdx DMA2D Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0(background) / 1(foreground)    \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)\r\n{\r\n  uint32_t tickstart = 0;\r\n  __IO uint32_t * reg =  &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */  \r\n\r\n  /* Suspend the CLUT loading */\r\n  SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); \r\n  \r\n  /* If foreground CLUT loading is considered, update local variables */ \r\n  if(LayerIdx == 1)\r\n  {\r\n    reg  = &(hdma2d->Instance->FGPFCCR);\r\n  }   \r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  /* Check if the CLUT loading is suspended */\r\n  while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \\\r\n    && ((*reg & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))\r\n  {\r\n    if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)\r\n    {\r\n      /* Update error code */\r\n      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;\r\n      \r\n      /* Change the DMA2D state */\r\n      hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;\r\n      \r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  \r\n   /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */\r\n  if ((*reg & DMA2D_BGPFCCR_START) != RESET)\r\n  {    \r\n    hdma2d->State = HAL_DMA2D_STATE_SUSPEND;\r\n  }\r\n  else\r\n  {\r\n    /* Make sure SUSP bit is cleared since it is meaningless \r\n       when no tranfer is on-going */\r\n    CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);\r\n  }  \r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Resume the DMA2D CLUT loading.\r\n  * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                 the configuration information for the DMA2D. \r\n  * @param  LayerIdx DMA2D Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0(background) / 1(foreground)      \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)\r\n{\r\n  /* Check the SUSP and START bits for background or foreground CLUT loading */\r\n  if(LayerIdx == 0)\r\n  {  \r\n    /* Background CLUT loading suspension check */\r\n    if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)\r\n      && ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))\r\n    {\r\n      /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */\r\n      hdma2d->State = HAL_DMA2D_STATE_BUSY;\r\n    }\r\n  }\r\n  else\r\n  {\r\n    /* Foreground CLUT loading suspension check */\r\n    if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)\r\n      && ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START))\r\n    {\r\n      /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */\r\n      hdma2d->State = HAL_DMA2D_STATE_BUSY;\r\n    }  \r\n  }\r\n\r\n  /* Resume the CLUT loading */\r\n  CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);  \r\n\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n\r\n  * @brief  Polling for transfer complete or CLUT loading.\r\n  * @param  hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                 the configuration information for the DMA2D. \r\n  * @param  Timeout Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;\r\n  __IO uint32_t isrflags = 0x0;  \r\n\r\n  /* Polling for DMA2D transfer */\r\n  if((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)\r\n  {\r\n   /* Get tick */\r\n   tickstart = HAL_GetTick();\r\n\r\n    while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET)\r\n    {\r\n      isrflags = READ_REG(hdma2d->Instance->ISR); \r\n      if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET)\r\n      {\r\n        if ((isrflags & DMA2D_FLAG_CE) != RESET)\r\n        {\r\n          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;        \r\n        }\r\n        if ((isrflags & DMA2D_FLAG_TE) != RESET)        \r\n        {\r\n          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;        \r\n        }\r\n        /* Clear the transfer and configuration error flags */\r\n        __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);\r\n\r\n        /* Change DMA2D state */\r\n        hdma2d->State = HAL_DMA2D_STATE_ERROR;\r\n\r\n        /* Process unlocked */\r\n        __HAL_UNLOCK(hdma2d);\r\n        \r\n        return HAL_ERROR;\r\n      }\r\n      /* Check for the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n        {\r\n          /* Update error code */\r\n          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;\r\n\r\n          /* Change the DMA2D state */\r\n          hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;\r\n         \r\n          /* Process unlocked */\r\n          __HAL_UNLOCK(hdma2d);\r\n           \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }        \r\n    }\r\n  }\r\n  /* Polling for CLUT loading (foreground or background) */\r\n  if (((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != RESET)  || \r\n      ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) != RESET))\r\n  {\r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n   \r\n    while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET)\r\n    {\r\n      isrflags = READ_REG(hdma2d->Instance->ISR);   \r\n      if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET)        \r\n      {      \r\n        if ((isrflags & DMA2D_FLAG_CAE) != RESET)\r\n        {\r\n          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;        \r\n        }   \r\n        if ((isrflags & DMA2D_FLAG_CE) != RESET)             \r\n        {\r\n          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;        \r\n        }\r\n        if ((isrflags & DMA2D_FLAG_TE) != RESET)        \r\n        {\r\n          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;        \r\n        }\r\n        /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */\r\n        __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);\r\n        \r\n        /* Change DMA2D state */\r\n        hdma2d->State= HAL_DMA2D_STATE_ERROR;\r\n        \r\n        /* Process unlocked */\r\n        __HAL_UNLOCK(hdma2d);\r\n          \r\n        return HAL_ERROR;      \r\n      }      \r\n      /* Check for the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n        {\r\n          /* Update error code */\r\n          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;\r\n    \r\n          /* Change the DMA2D state */\r\n          hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;\r\n        \r\n          /* Process unlocked */\r\n          __HAL_UNLOCK(hdma2d);\r\n                    \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }      \r\n    }\r\n  }\r\n\r\n  /* Clear the transfer complete and CLUT loading flags */\r\n  __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC);\r\n  \r\n  /* Change DMA2D state */\r\n  hdma2d->State = HAL_DMA2D_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdma2d);\r\n  \r\n  return HAL_OK;\r\n}\r\n/**\r\n  * @brief  Handle DMA2D interrupt request.\r\n  * @param  hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                 the configuration information for the DMA2D.  \r\n  * @retval HAL status\r\n  */\r\nvoid HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)\r\n{\r\n  uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);\r\n  uint32_t crflags = READ_REG(hdma2d->Instance->CR);\r\n        \r\n  /* Transfer Error Interrupt management ***************************************/\r\n  if ((isrflags & DMA2D_FLAG_TE) != RESET)\r\n  {\r\n    if ((crflags & DMA2D_IT_TE) != RESET)    \r\n    {\r\n      /* Disable the transfer Error interrupt */\r\n      __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);  \r\n\r\n      /* Update error code */\r\n      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;\r\n    \r\n      /* Clear the transfer error flag */\r\n      __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);\r\n\r\n      /* Change DMA2D state */\r\n      hdma2d->State = HAL_DMA2D_STATE_ERROR;\r\n\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hdma2d);       \r\n      \r\n      if(hdma2d->XferErrorCallback != NULL)\r\n      {\r\n        /* Transfer error Callback */\r\n        hdma2d->XferErrorCallback(hdma2d);\r\n      }\r\n    }\r\n  }\r\n  /* Configuration Error Interrupt management **********************************/\r\n  if ((isrflags & DMA2D_FLAG_CE) != RESET)\r\n  {\r\n    if ((crflags & DMA2D_IT_CE) != RESET)    \r\n    {  \r\n      /* Disable the Configuration Error interrupt */\r\n      __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);\r\n  \r\n      /* Clear the Configuration error flag */\r\n      __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);\r\n\r\n      /* Update error code */\r\n      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;    \r\n    \r\n      /* Change DMA2D state */\r\n      hdma2d->State = HAL_DMA2D_STATE_ERROR;\r\n\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hdma2d);       \r\n      \r\n      if(hdma2d->XferErrorCallback != NULL)\r\n      {\r\n        /* Transfer error Callback */\r\n        hdma2d->XferErrorCallback(hdma2d);\r\n      }\r\n    }\r\n  }\r\n  /* CLUT access Error Interrupt management ***********************************/\r\n  if ((isrflags & DMA2D_FLAG_CAE) != RESET)\r\n  {\r\n    if ((crflags & DMA2D_IT_CAE) != RESET)    \r\n    {    \r\n      /* Disable the CLUT access error interrupt */\r\n      __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);\r\n  \r\n      /* Clear the CLUT access error flag */\r\n      __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);\r\n\r\n      /* Update error code */\r\n      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;    \r\n    \r\n      /* Change DMA2D state */\r\n      hdma2d->State = HAL_DMA2D_STATE_ERROR;\r\n\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hdma2d);       \r\n      \r\n      if(hdma2d->XferErrorCallback != NULL)\r\n      {\r\n        /* Transfer error Callback */\r\n        hdma2d->XferErrorCallback(hdma2d);\r\n      }\r\n    }\r\n  }  \r\n  /* Transfer watermark Interrupt management **********************************/\r\n  if ((isrflags & DMA2D_FLAG_TW) != RESET)\r\n  {\r\n    if ((crflags & DMA2D_IT_TW) != RESET)    \r\n    {    \r\n      /* Disable the transfer watermark interrupt */\r\n      __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);\r\n  \r\n      /* Clear the transfer watermark flag */  \r\n      __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);\r\n\r\n      /* Transfer watermark Callback */\r\n      HAL_DMA2D_LineEventCallback(hdma2d);\r\n    }\r\n  }  \r\n  /* Transfer Complete Interrupt management ************************************/\r\n  if ((isrflags & DMA2D_FLAG_TC) != RESET)\r\n  {\r\n    if ((crflags & DMA2D_IT_TC) != RESET)    \r\n    {   \r\n      /* Disable the transfer complete interrupt */\r\n      __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);\r\n  \r\n      /* Clear the transfer complete flag */  \r\n      __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);\r\n\r\n      /* Update error code */\r\n      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;    \r\n    \r\n      /* Change DMA2D state */\r\n      hdma2d->State = HAL_DMA2D_STATE_READY;\r\n    \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hdma2d);       \r\n      \r\n      if(hdma2d->XferCpltCallback != NULL)\r\n      {\r\n        /* Transfer complete Callback */\r\n        hdma2d->XferCpltCallback(hdma2d);\r\n      }         \r\n    }\r\n  }\r\n  /* CLUT Transfer Complete Interrupt management ******************************/\r\n  if ((isrflags & DMA2D_FLAG_CTC) != RESET)\r\n  {\r\n    if ((crflags & DMA2D_IT_CTC) != RESET)    \r\n    {    \r\n      /* Disable the CLUT transfer complete interrupt */\r\n      __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);\r\n  \r\n      /* Clear the CLUT transfer complete flag */  \r\n      __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);\r\n\r\n      /* Update error code */\r\n      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;    \r\n    \r\n      /* Change DMA2D state */\r\n      hdma2d->State = HAL_DMA2D_STATE_READY;\r\n    \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hdma2d);       \r\n      \r\n      /* CLUT Transfer complete Callback */\r\n      HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);         \r\n    }\r\n  }  \r\n  \r\n}\r\n\r\n/**\r\n  * @brief  Transfer watermark callback.\r\n  * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                 the configuration information for the DMA2D.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdma2d);\r\n  \r\n  /* NOTE : This function should not be modified; when the callback is needed,\r\n            the HAL_DMA2D_LineEventCallback can be implemented in the user file.\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  CLUT Transfer Complete callback.\r\n  * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                 the configuration information for the DMA2D.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdma2d);\r\n  \r\n  /* NOTE : This function should not be modified; when the callback is needed,\r\n            the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.\r\n   */\r\n} \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions\r\n *  @brief    Peripheral Control functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                    ##### Peripheral Control functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Configure the DMA2D foreground or background layer parameters.\r\n      (+) Configure the DMA2D CLUT transfer.\r\n      (+) Configure the line watermark\r\n      (+) Configure the dead time value.\r\n      (+) Enable or disable the dead time value functionality.      \r\n          \r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Configure the DMA2D Layer according to the specified\r\n  *         parameters in the DMA2D_InitTypeDef and create the associated handle.\r\n  * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                 the configuration information for the DMA2D.\r\n  * @param  LayerIdx DMA2D Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0(background) / 1(foreground)\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)\r\n{ \r\n  DMA2D_LayerCfgTypeDef *pLayerCfg = &hdma2d->LayerCfg[LayerIdx];\r\n  \r\n  uint32_t regMask = 0, regValue = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_DMA2D_LAYER(LayerIdx));  \r\n  assert_param(IS_DMA2D_OFFSET(pLayerCfg->InputOffset));  \r\n  if(hdma2d->Init.Mode != DMA2D_R2M)\r\n  {  \r\n    assert_param(IS_DMA2D_INPUT_COLOR_MODE(pLayerCfg->InputColorMode));\r\n    if(hdma2d->Init.Mode != DMA2D_M2M)\r\n    {\r\n      assert_param(IS_DMA2D_ALPHA_MODE(pLayerCfg->AlphaMode));\r\n    }\r\n  }\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hdma2d);\r\n  \r\n  /* Change DMA2D peripheral state */\r\n  hdma2d->State = HAL_DMA2D_STATE_BUSY;  \r\n\r\n  /* DMA2D BGPFCR register configuration -----------------------------------*/\r\n  /* Prepare the value to be written to the BGPFCCR register */\r\n  \r\n  regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos);\r\n  regMask  = DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA;\r\n  \r\n#if defined (DMA2D_FGPFCCR_AI) && defined (DMA2D_BGPFCCR_AI)\r\n  regValue |= (pLayerCfg->AlphaInverted << DMA2D_BGPFCCR_AI_Pos);\r\n  regMask  |= DMA2D_BGPFCCR_AI;  \r\n#endif /* (DMA2D_FGPFCCR_AI) && (DMA2D_BGPFCCR_AI)  */ \r\n  \r\n#if defined (DMA2D_FGPFCCR_RBS) && defined (DMA2D_BGPFCCR_RBS)\r\n  regValue |= (pLayerCfg->RedBlueSwap << DMA2D_BGPFCCR_RBS_Pos);\r\n  regMask  |= DMA2D_BGPFCCR_RBS;  \r\n#endif  \r\n  \r\n  if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))\r\n  {\r\n    regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);\r\n  }\r\n  else\r\n  {\r\n    regValue |=  (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos);\r\n  }\r\n  \r\n  /* Configure the background DMA2D layer */\r\n  if(LayerIdx == 0)\r\n  {\r\n    /* Write DMA2D BGPFCCR register */\r\n    MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);\r\n              \r\n    /* DMA2D BGOR register configuration -------------------------------------*/  \r\n    WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);\r\n    \r\n    /* DMA2D BGCOLR register configuration -------------------------------------*/ \r\n    if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))\r\n    {    \r\n      WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED));\r\n    }    \r\n  }\r\n  /* Configure the foreground DMA2D layer */\r\n  else\r\n  {\r\n     /* Write DMA2D FGPFCCR register */\r\n    MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);\r\n    \r\n    /* DMA2D FGOR register configuration -------------------------------------*/\r\n    WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);      \r\n   \r\n    /* DMA2D FGCOLR register configuration -------------------------------------*/   \r\n    if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))\r\n    {\r\n      WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED));      \r\n    }   \r\n  }   \r\n  /* Initialize the DMA2D state*/\r\n  hdma2d->State = HAL_DMA2D_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdma2d);  \r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Configure the DMA2D CLUT Transfer.\r\n  * @param  hdma2d   Pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                   the configuration information for the DMA2D.\r\n  * @param  CLUTCfg  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains\r\n  *                   the configuration information for the color look up table.\r\n  * @param  LayerIdx DMA2D Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0(background) / 1(foreground)\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_DMA2D_LAYER(LayerIdx));   \r\n  assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));\r\n  assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hdma2d);\r\n  \r\n  /* Change DMA2D peripheral state */\r\n  hdma2d->State = HAL_DMA2D_STATE_BUSY;     \r\n  \r\n  /* Configure the CLUT of the background DMA2D layer */\r\n  if(LayerIdx == 0)\r\n  {\r\n    /* Write background CLUT memory address */\r\n    WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);\r\n     \r\n    /* Write background CLUT size and CLUT color mode */\r\n    MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), \r\n            ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));       \r\n }\r\n /* Configure the CLUT of the foreground DMA2D layer */\r\n else\r\n {\r\n   /* Write foreground CLUT memory address */\r\n    WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);\r\n     \r\n    /* Write foreground CLUT size and CLUT color mode */\r\n    MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), \r\n            ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));       \r\n  }\r\n  \r\n  /* Set the DMA2D state to Ready*/\r\n  hdma2d->State = HAL_DMA2D_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdma2d); \r\n    \r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Configure the line watermark.\r\n  * @param  hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                 the configuration information for the DMA2D.\r\n  * @param  Line   Line Watermark configuration (maximum 16-bit long value expected).\r\n  * @note   HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt.\r\n  * @note   The transfer watermark interrupt is disabled once it has occurred.\r\n  * @retval HAL status\r\n  */\r\n\r\nHAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_DMA2D_LINEWATERMARK(Line));\r\n  \r\n  if (Line > DMA2D_LWR_LW)\r\n  {\r\n    return HAL_ERROR;  \r\n  }\r\n  else\r\n  {      \r\n    /* Process locked */\r\n    __HAL_LOCK(hdma2d);\r\n    \r\n    /* Change DMA2D peripheral state */\r\n    hdma2d->State = HAL_DMA2D_STATE_BUSY;\r\n  \r\n    /* Sets the Line watermark configuration */\r\n    WRITE_REG(hdma2d->Instance->LWR, Line);\r\n    \r\n    /* Enable the Line interrupt */\r\n    __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW);\r\n        \r\n    /* Initialize the DMA2D state*/\r\n    hdma2d->State = HAL_DMA2D_STATE_READY;\r\n    \r\n    /* Process unlocked */\r\n    __HAL_UNLOCK(hdma2d);  \r\n    \r\n    return HAL_OK;\r\n  }  \r\n}\r\n\r\n/**\r\n  * @brief Enable DMA2D dead time feature.\r\n  * @param hdma2d DMA2D handle.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hdma2d);\r\n\r\n  hdma2d->State = HAL_DMA2D_STATE_BUSY;\r\n\r\n  /* Set DMA2D_AMTCR EN bit */\r\n  SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);\r\n\r\n  hdma2d->State = HAL_DMA2D_STATE_READY;\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hdma2d);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Disable DMA2D dead time feature.\r\n  * @param hdma2d DMA2D handle.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hdma2d);\r\n\r\n  hdma2d->State = HAL_DMA2D_STATE_BUSY;\r\n\r\n  /* Clear DMA2D_AMTCR EN bit */\r\n  CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);\r\n\r\n  hdma2d->State = HAL_DMA2D_STATE_READY;\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hdma2d);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Configure dead time.\r\n  * @note The dead time value represents the guaranteed minimum number of cycles between \r\n  *       two consecutive transactions on the AHB bus.\r\n  * @param hdma2d DMA2D handle.\r\n  * @param DeadTime dead time value.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hdma2d);  \r\n  \r\n  hdma2d->State = HAL_DMA2D_STATE_BUSY;\r\n\r\n  /* Set DMA2D_AMTCR DT field */\r\n  MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_AMTCR_DT_Pos));\r\n\r\n  hdma2d->State = HAL_DMA2D_STATE_READY;\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hdma2d);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n\r\n/** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions\r\n *  @brief    Peripheral State functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                  ##### Peripheral State and Errors functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides functions allowing to :\r\n      (+) Get the DMA2D state\r\n      (+) Get the DMA2D error code  \r\n\r\n@endverbatim\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @brief  Return the DMA2D state\r\n  * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                 the configuration information for the DMA2D.  \r\n  * @retval HAL state\r\n  */\r\nHAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)\r\n{  \r\n  return hdma2d->State;\r\n}\r\n\r\n/**\r\n  * @brief  Return the DMA2D error code\r\n  * @param  hdma2d  pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *               the configuration information for DMA2D.\r\n  * @retval DMA2D Error Code\r\n  */\r\nuint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)\r\n{\r\n  return hdma2d->ErrorCode;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */  \r\n\r\n\r\n/** @defgroup DMA2D_Private_Functions DMA2D Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Set the DMA2D transfer parameters.\r\n  * @param  hdma2d     Pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                     the configuration information for the specified DMA2D.  \r\n  * @param  pdata      The source memory Buffer address\r\n  * @param  DstAddress The destination memory Buffer address\r\n  * @param  Width      The width of data to be transferred from source to destination.\r\n  * @param  Height     The height of data to be transferred from source to destination.\r\n  * @retval HAL status\r\n  */\r\nstatic void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)\r\n{  \r\n  uint32_t tmp = 0;\r\n  uint32_t tmp1 = 0;\r\n  uint32_t tmp2 = 0;\r\n  uint32_t tmp3 = 0;\r\n  uint32_t tmp4 = 0;\r\n    \r\n  /* Configure DMA2D data size */\r\n  MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_NLR_PL_Pos))); \r\n  \r\n  /* Configure DMA2D destination address */\r\n  WRITE_REG(hdma2d->Instance->OMAR, DstAddress);\r\n \r\n  /* Register to memory DMA2D mode selected */\r\n  if (hdma2d->Init.Mode == DMA2D_R2M)\r\n  {    \r\n    tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;\r\n    tmp2 = pdata & DMA2D_OCOLR_RED_1;\r\n    tmp3 = pdata & DMA2D_OCOLR_GREEN_1;\r\n    tmp4 = pdata & DMA2D_OCOLR_BLUE_1;\r\n    \r\n    /* Prepare the value to be written to the OCOLR register according to the color mode */\r\n    if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)\r\n    {\r\n      tmp = (tmp3 | tmp2 | tmp1| tmp4);\r\n    }\r\n    else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)\r\n    {\r\n      tmp = (tmp3 | tmp2 | tmp4);  \r\n    }\r\n    else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)\r\n    {\r\n      tmp2 = (tmp2 >> 19);\r\n      tmp3 = (tmp3 >> 10);\r\n      tmp4 = (tmp4 >> 3 );\r\n      tmp  = ((tmp3 << 5) | (tmp2 << 11) | tmp4); \r\n    }\r\n    else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)\r\n    { \r\n      tmp1 = (tmp1 >> 31);\r\n      tmp2 = (tmp2 >> 19);\r\n      tmp3 = (tmp3 >> 11);\r\n      tmp4 = (tmp4 >> 3 );      \r\n      tmp  = ((tmp3 << 5) | (tmp2 << 10) | (tmp1 << 15) | tmp4);    \r\n    } \r\n    else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */\r\n    {\r\n      tmp1 = (tmp1 >> 28);\r\n      tmp2 = (tmp2 >> 20);\r\n      tmp3 = (tmp3 >> 12);\r\n      tmp4 = (tmp4 >> 4 );\r\n      tmp  = ((tmp3 << 4) | (tmp2 << 8) | (tmp1 << 12) | tmp4);\r\n    }    \r\n    /* Write to DMA2D OCOLR register */\r\n    WRITE_REG(hdma2d->Instance->OCOLR, tmp);    \r\n  } \r\n  else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */\r\n  {\r\n    /* Configure DMA2D source address */\r\n    WRITE_REG(hdma2d->Instance->FGMAR, pdata);\r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n#endif /* DMA2D */\r\n#endif /* HAL_DMA2D_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_dma_ex.c\r\n  * @author  MCD Application Team\r\n  * @brief   DMA Extension HAL module driver\r\n  *         This file provides firmware functions to manage the following \r\n  *         functionalities of the DMA Extension peripheral:\r\n  *           + Extended features functions\r\n  *\r\n  @verbatim\r\n  ==============================================================================\r\n                        ##### How to use this driver #####\r\n  ==============================================================================\r\n  [..]\r\n  The DMA Extension HAL driver can be used as follows:\r\n   (+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function\r\n       for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.\r\n\r\n     -@-  In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.\r\n     -@-  When Multi (Double) Buffer mode is enabled, the transfer is circular by default.\r\n     -@-  In Multi (Double) buffer mode, it is possible to update the base address for \r\n          the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.\r\n  \r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup DMAEx DMAEx\r\n  * @brief DMA Extended HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_DMA_MODULE_ENABLED\r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private Constants ---------------------------------------------------------*/\r\n/* Private macros ------------------------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @addtogroup DMAEx_Private_Functions\r\n  * @{\r\n  */\r\n\r\nstatic void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions ---------------------------------------------------------*/\r\n\r\n/** @addtogroup DMAEx_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n\r\n/** @addtogroup DMAEx_Exported_Functions_Group1\r\n  *\r\n@verbatim\r\n ===============================================================================\r\n                #####  Extended features functions  #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Configure the source, destination address and data length and \r\n          Start MultiBuffer DMA transfer\r\n      (+) Configure the source, destination address and data length and \r\n          Start MultiBuffer DMA transfer with interrupt\r\n      (+) Change on the fly the memory0 or memory1 address.\r\n      \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n\r\n/**\r\n  * @brief  Starts the multi_buffer DMA Transfer.\r\n  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains\r\n  *                     the configuration information for the specified DMA Stream.  \r\n  * @param  SrcAddress The source memory Buffer address\r\n  * @param  DstAddress The destination memory Buffer address\r\n  * @param  SecondMemAddress The second memory Buffer address in case of multi buffer Transfer  \r\n  * @param  DataLength The length of data to be transferred from source to destination\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_DMA_BUFFER_SIZE(DataLength));\r\n  \r\n  /* Memory-to-memory transfer not supported in double buffering mode */\r\n  if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)\r\n  {\r\n    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;\r\n    status = HAL_ERROR;\r\n  }\r\n  else\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hdma);\r\n    \r\n    if(HAL_DMA_STATE_READY == hdma->State)\r\n    {\r\n      /* Change DMA peripheral state */\r\n      hdma->State = HAL_DMA_STATE_BUSY; \r\n      \r\n      /* Enable the double buffer mode */\r\n      hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;\r\n      \r\n      /* Configure DMA Stream destination address */\r\n      hdma->Instance->M1AR = SecondMemAddress;\r\n      \r\n      /* Configure the source, destination address and the data length */\r\n      DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);\r\n      \r\n      /* Enable the peripheral */\r\n      __HAL_DMA_ENABLE(hdma);\r\n    }\r\n    else\r\n    {\r\n      /* Return error status */\r\n      status = HAL_BUSY;\r\n    }\r\n  }\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the multi_buffer DMA Transfer with interrupt enabled.\r\n  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains\r\n  *                     the configuration information for the specified DMA Stream.  \r\n  * @param  SrcAddress The source memory Buffer address\r\n  * @param  DstAddress The destination memory Buffer address\r\n  * @param  SecondMemAddress The second memory Buffer address in case of multi buffer Transfer  \r\n  * @param  DataLength The length of data to be transferred from source to destination\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_DMA_BUFFER_SIZE(DataLength));\r\n  \r\n  /* Memory-to-memory transfer not supported in double buffering mode */\r\n  if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)\r\n  {\r\n    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hdma);\r\n  \r\n  if(HAL_DMA_STATE_READY == hdma->State)\r\n  {\r\n    /* Change DMA peripheral state */\r\n    hdma->State = HAL_DMA_STATE_BUSY;\r\n    \r\n    /* Initialize the error code */\r\n    hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r\n    \r\n    /* Enable the Double buffer mode */\r\n    hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;\r\n    \r\n    /* Configure DMA Stream destination address */\r\n    hdma->Instance->M1AR = SecondMemAddress;\r\n    \r\n    /* Configure the source, destination address and the data length */\r\n    DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); \r\n    \r\n    /* Clear all flags */\r\n    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));\r\n    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));\r\n    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));\r\n    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));\r\n    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));\r\n    \r\n    /* Enable Common interrupts*/\r\n    hdma->Instance->CR  |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;\r\n    hdma->Instance->FCR |= DMA_IT_FE;\r\n    \r\n    if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))\r\n    {\r\n      hdma->Instance->CR  |= DMA_IT_HT;\r\n    }\r\n    \r\n    /* Enable the peripheral */\r\n    __HAL_DMA_ENABLE(hdma); \r\n  }\r\n  else\r\n  {     \r\n    /* Process unlocked */\r\n    __HAL_UNLOCK(hdma);\t  \r\n    \r\n    /* Return error status */\r\n    status = HAL_BUSY;\r\n  }  \r\n  return status; \r\n}\r\n\r\n/**\r\n  * @brief  Change the memory0 or memory1 address on the fly.\r\n  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains\r\n  *                     the configuration information for the specified DMA Stream.  \r\n  * @param  Address    The new address\r\n  * @param  memory     the memory to be changed, This parameter can be one of \r\n  *                     the following values:\r\n  *                      MEMORY0 /\r\n  *                      MEMORY1\r\n  * @note   The MEMORY0 address can be changed only when the current transfer use\r\n  *         MEMORY1 and the MEMORY1 address can be changed only when the current \r\n  *         transfer use MEMORY0.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)\r\n{\r\n  if(memory == MEMORY0)\r\n  {\r\n    /* change the memory0 address */\r\n    hdma->Instance->M0AR = Address;\r\n  }\r\n  else\r\n  {\r\n    /* change the memory1 address */\r\n    hdma->Instance->M1AR = Address;\r\n  }\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup DMAEx_Private_Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Set the DMA Transfer parameter.\r\n  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains\r\n  *                     the configuration information for the specified DMA Stream.  \r\n  * @param  SrcAddress The source memory Buffer address\r\n  * @param  DstAddress The destination memory Buffer address\r\n  * @param  DataLength The length of data to be transferred from source to destination\r\n  * @retval HAL status\r\n  */\r\nstatic void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r\n{\r\n  /* Configure DMA Stream data length */\r\n  hdma->Instance->NDTR = DataLength;\r\n  \r\n  /* Peripheral to Memory */\r\n  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)\r\n  {\r\n    /* Configure DMA Stream destination address */\r\n    hdma->Instance->PAR = DstAddress;\r\n    \r\n    /* Configure DMA Stream source address */\r\n    hdma->Instance->M0AR = SrcAddress;\r\n  }\r\n  /* Memory to Peripheral */\r\n  else\r\n  {\r\n    /* Configure DMA Stream source address */\r\n    hdma->Instance->PAR = SrcAddress;\r\n    \r\n    /* Configure DMA Stream destination address */\r\n    hdma->Instance->M0AR = DstAddress;\r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_DMA_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_flash.c\r\n  * @author  MCD Application Team\r\n  * @brief   FLASH HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the internal FLASH memory:\r\n  *           + Program operations functions\r\n  *           + Memory Control functions \r\n  *           + Peripheral Errors functions\r\n  *         \r\n  @verbatim\r\n  ==============================================================================\r\n                        ##### FLASH peripheral features #####\r\n  ==============================================================================\r\n           \r\n  [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses \r\n       to the Flash memory. It implements the erase and program Flash memory operations \r\n       and the read and write protection mechanisms.\r\n      \r\n  [..] The Flash memory interface accelerates code execution with a system of instruction\r\n       prefetch and cache lines. \r\n\r\n  [..] The FLASH main features are:\r\n      (+) Flash memory read operations\r\n      (+) Flash memory program/erase operations\r\n      (+) Read / write protections\r\n      (+) Prefetch on I-Code\r\n      (+) 64 cache lines of 128 bits on I-Code\r\n      (+) 8 cache lines of 128 bits on D-Code\r\n      \r\n                     ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]                             \r\n      This driver provides functions and macros to configure and program the FLASH \r\n      memory of all STM32F7xx devices.\r\n    \r\n      (#) FLASH Memory IO Programming functions: \r\n           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and \r\n                HAL_FLASH_Lock() functions\r\n           (++) Program functions: byte, half word, word and double word\r\n           (++) There Two modes of programming :\r\n            (+++) Polling mode using HAL_FLASH_Program() function\r\n            (+++) Interrupt mode using HAL_FLASH_Program_IT() function\r\n    \r\n      (#) Interrupts and flags management functions : \r\n           (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()\r\n           (++) Wait for last FLASH operation according to its status\r\n           (++) Get error flag status by calling HAL_SetErrorCode()          \r\n    [..] \r\n      In addition to these functions, this driver includes a set of macros allowing\r\n      to handle the following operations:\r\n       (+) Set the latency\r\n       (+) Enable/Disable the prefetch buffer\r\n       (+) Enable/Disable the Instruction cache and the Data cache\r\n       (+) Reset the Instruction cache and the Data cache\r\n       (+) Enable/Disable the FLASH interrupts\r\n       (+) Monitor the FLASH flags status\r\n    [..]\t   \r\n\t(@) For any Flash memory program operation (erase or program), the CPU clock frequency\r\n        (HCLK) must be at least 1MHz. \r\n\t(@) The contents of the Flash memory are not guaranteed if a device reset occurs during \r\n\t    a Flash memory operation.\r\n    (@) Any attempt to read the Flash memory while it is being written or erased, causes the \r\n\t    bus to stall. Read operations are processed correctly once the program operation has \r\n\t\tcompleted. This means that code or data fetches cannot be performed while a write/erase \r\n\t\toperation is ongoing.\r\n          \r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup FLASH FLASH\r\n  * @brief FLASH HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_FLASH_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @addtogroup FLASH_Private_Constants\r\n  * @{\r\n  */\r\n#define SECTOR_MASK               ((uint32_t)0xFFFFFF07U)\r\n#define FLASH_TIMEOUT_VALUE       ((uint32_t)50000U)/* 50 s */\r\n/**\r\n  * @}\r\n  */         \r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @addtogroup FLASH_Private_Variables\r\n  * @{\r\n  */\r\n/* Variable used for Erase sectors under interruption */\r\nFLASH_ProcessTypeDef pFlash;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private function prototypes -----------------------------------------------*/\r\n/** @addtogroup FLASH_Private_Functions\r\n  * @{\r\n  */\r\n/* Program operations */\r\nstatic void   FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);\r\nstatic void   FLASH_Program_Word(uint32_t Address, uint32_t Data);\r\nstatic void   FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);\r\nstatic void   FLASH_Program_Byte(uint32_t Address, uint8_t Data);\r\nstatic void   FLASH_SetErrorCode(void);\r\n\r\nHAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup FLASH_Exported_Functions FLASH Exported Functions\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions \r\n *  @brief   Programming operation functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                  ##### Programming operation functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides a set of functions allowing to manage the FLASH \r\n    program operations.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Program byte, halfword, word or double word at a specified address\r\n  * @param  TypeProgram  Indicate the way to program at a specified address.\r\n  *                           This parameter can be a value of @ref FLASH_Type_Program\r\n  * @param  Address  specifies the address to be programmed.\r\n  * @param  Data specifies the data to be programmed\r\n  * \r\n  * @retval HAL_StatusTypeDef HAL Status\r\n  */\r\nHAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)\r\n{\r\n  HAL_StatusTypeDef status = HAL_ERROR;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(&pFlash);\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));\r\n\r\n  /* Wait for last operation to be completed */\r\n  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r\n  \r\n  if(status == HAL_OK)\r\n  {\r\n    switch(TypeProgram)\r\n    {\r\n      case FLASH_TYPEPROGRAM_BYTE :\r\n      {\r\n        /*Program byte (8-bit) at a specified address.*/\r\n        FLASH_Program_Byte(Address, (uint8_t) Data);\r\n        break;\r\n      }\r\n      \r\n      case FLASH_TYPEPROGRAM_HALFWORD :\r\n      {\r\n        /*Program halfword (16-bit) at a specified address.*/\r\n        FLASH_Program_HalfWord(Address, (uint16_t) Data);\r\n        break;\r\n      }\r\n      \r\n      case FLASH_TYPEPROGRAM_WORD :\r\n      {\r\n        /*Program word (32-bit) at a specified address.*/\r\n        FLASH_Program_Word(Address, (uint32_t) Data);\r\n        break;\r\n      }\r\n      \r\n      case FLASH_TYPEPROGRAM_DOUBLEWORD :\r\n      {\r\n        /*Program double word (64-bit) at a specified address.*/\r\n        FLASH_Program_DoubleWord(Address, Data);\r\n        break;\r\n      }\r\n      default :\r\n        break;\r\n    }\r\n    /* Wait for last operation to be completed */\r\n    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r\n    \r\n    /* If the program operation is completed, disable the PG Bit */\r\n    FLASH->CR &= (~FLASH_CR_PG);\r\n  }\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(&pFlash);\r\n\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief   Program byte, halfword, word or double word at a specified address  with interrupt enabled.\r\n  * @param  TypeProgram  Indicate the way to program at a specified address.\r\n  *                           This parameter can be a value of @ref FLASH_Type_Program\r\n  * @param  Address  specifies the address to be programmed.\r\n  * @param  Data specifies the data to be programmed\r\n  * \r\n  * @retval HAL Status\r\n  */\r\nHAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(&pFlash);\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));\r\n\r\n  /* Enable End of FLASH Operation interrupt */\r\n  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);\r\n  \r\n  /* Enable Error source interrupt */\r\n  __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);\r\n  \r\n  /* Clear pending flags (if any) */  \r\n  __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP    | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\\\r\n                         FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR);  \r\n\r\n  pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;\r\n  pFlash.Address = Address;\r\n  \r\n  switch(TypeProgram)\r\n  {\r\n    case FLASH_TYPEPROGRAM_BYTE :\r\n    {\r\n      /*Program byte (8-bit) at a specified address.*/\r\n      FLASH_Program_Byte(Address, (uint8_t) Data);\r\n      break;\r\n    }\r\n    \r\n    case FLASH_TYPEPROGRAM_HALFWORD :\r\n    {\r\n      /*Program halfword (16-bit) at a specified address.*/\r\n      FLASH_Program_HalfWord(Address, (uint16_t) Data);\r\n      break;\r\n    }\r\n    \r\n    case FLASH_TYPEPROGRAM_WORD :\r\n    {\r\n      /*Program word (32-bit) at a specified address.*/\r\n      FLASH_Program_Word(Address, (uint32_t) Data);\r\n      break;\r\n    }\r\n    \r\n    case FLASH_TYPEPROGRAM_DOUBLEWORD :\r\n    {\r\n      /*Program double word (64-bit) at a specified address.*/\r\n      FLASH_Program_DoubleWord(Address, Data);\r\n      break;\r\n    }\r\n    default :\r\n      break;\r\n  }\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief This function handles FLASH interrupt request.\r\n  * @retval None\r\n  */\r\nvoid HAL_FLASH_IRQHandler(void)\r\n{\r\n  uint32_t temp = 0;\r\n  \r\n  /* If the program operation is completed, disable the PG Bit */\r\n  FLASH->CR &= (~FLASH_CR_PG);\r\n\r\n  /* If the erase operation is completed, disable the SER Bit */\r\n  FLASH->CR &= (~FLASH_CR_SER);\r\n  FLASH->CR &= SECTOR_MASK; \r\n\r\n  /* if the erase operation is completed, disable the MER Bit */\r\n  FLASH->CR &= (~FLASH_MER_BIT);\r\n\r\n  /* Check FLASH End of Operation flag  */\r\n  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)\r\n  {\r\n    /* Clear FLASH End of Operation pending bit */\r\n    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);\r\n    \r\n    switch (pFlash.ProcedureOnGoing)\r\n    {\r\n      case FLASH_PROC_SECTERASE :\r\n      {\r\n        /* Nb of sector to erased can be decreased */\r\n        pFlash.NbSectorsToErase--;\r\n\r\n        /* Check if there are still sectors to erase */\r\n        if(pFlash.NbSectorsToErase != 0)\r\n        {\r\n          temp = pFlash.Sector;\r\n          /* Indicate user which sector has been erased */\r\n          HAL_FLASH_EndOfOperationCallback(temp);\r\n\r\n          /* Increment sector number */\r\n          temp = ++pFlash.Sector;\r\n          FLASH_Erase_Sector(temp, pFlash.VoltageForErase);\r\n        }\r\n        else\r\n        {\r\n          /* No more sectors to Erase, user callback can be called.*/\r\n          /* Reset Sector and stop Erase sectors procedure */\r\n          pFlash.Sector = temp = 0xFFFFFFFFU;\r\n          /* FLASH EOP interrupt user callback */\r\n          HAL_FLASH_EndOfOperationCallback(temp);\r\n          /* Sector Erase procedure is completed */\r\n          pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r\n        }\r\n        break;\r\n      }\r\n    \r\n      case FLASH_PROC_MASSERASE :\r\n      {\r\n        /* MassErase ended. Return the selected bank : in this product we don't have Banks */\r\n        /* FLASH EOP interrupt user callback */\r\n        HAL_FLASH_EndOfOperationCallback(0);\r\n        /* MAss Erase procedure is completed */\r\n        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r\n        break;\r\n      }\r\n\r\n      case FLASH_PROC_PROGRAM :\r\n      {\r\n        /*Program ended. Return the selected address*/\r\n        /* FLASH EOP interrupt user callback */\r\n        HAL_FLASH_EndOfOperationCallback(pFlash.Address);\r\n        /* Programming procedure is completed */\r\n        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r\n        break;\r\n      }\r\n      default :\r\n        break;\r\n    }\r\n  }\r\n  \r\n  /* Check FLASH operation error flags */\r\n  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ALL_ERRORS) != RESET)\r\n  {\r\n    switch (pFlash.ProcedureOnGoing)\r\n    {\r\n      case FLASH_PROC_SECTERASE :\r\n      {\r\n        /* return the faulty sector */\r\n        temp = pFlash.Sector;\r\n        pFlash.Sector = 0xFFFFFFFFU;\r\n        break;\r\n      }\r\n      case FLASH_PROC_MASSERASE :\r\n      {\r\n        /* No return in case of Mass Erase */\r\n        temp = 0;\r\n        break;\r\n      }\r\n      case FLASH_PROC_PROGRAM :\r\n      {\r\n        /*return the faulty address*/\r\n        temp = pFlash.Address;\r\n        break;\r\n      }\r\n    default :\r\n      break;\r\n    }\r\n    /*Save the Error code*/\r\n    FLASH_SetErrorCode();\r\n\r\n    /* FLASH error interrupt user callback */\r\n    HAL_FLASH_OperationErrorCallback(temp);\r\n\r\n    /*Stop the procedure ongoing */\r\n    pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r\n  }\r\n  \r\n  if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)\r\n  {\r\n    /* Disable End of FLASH Operation interrupt */\r\n    __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP);\r\n\r\n    /* Disable Error source interrupt */\r\n    __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR);\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(&pFlash);\r\n  }\r\n  \r\n}\r\n\r\n/**\r\n  * @brief  FLASH end of operation interrupt callback\r\n  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure\r\n  *                 - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that \r\n  *                                  all the selected sectors have been erased)\r\n  *                 - Program      : Address which was selected for data program\r\n  *                 - Mass Erase   : No return value expected\r\n  * @retval None\r\n  */\r\n__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(ReturnValue);\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n  the HAL_FLASH_EndOfOperationCallback could be implemented in the user file\r\n  */ \r\n}\r\n\r\n/**\r\n  * @brief  FLASH operation error interrupt callback\r\n  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure\r\n  *                 - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that \r\n  *                                  all the selected sectors have been erased)\r\n  *                 - Program      : Address which was selected for data program\r\n  *                 - Mass Erase   : No return value expected\r\n  * @retval None\r\n  */\r\n__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(ReturnValue);\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n  the HAL_FLASH_OperationErrorCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions \r\n *  @brief   management functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                      ##### Peripheral Control functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides a set of functions allowing to control the FLASH \r\n    memory operations.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Unlock the FLASH control register access\r\n  * @retval HAL Status\r\n  */\r\nHAL_StatusTypeDef HAL_FLASH_Unlock(void)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)\r\n  {\r\n    /* Authorize the FLASH Registers access */\r\n    WRITE_REG(FLASH->KEYR, FLASH_KEY1);\r\n    WRITE_REG(FLASH->KEYR, FLASH_KEY2);\r\n\r\n    /* Verify Flash is unlocked */\r\n    if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)\r\n    {\r\n      status = HAL_ERROR;\r\n    }\r\n  }\r\n\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Locks the FLASH control register access\r\n  * @retval HAL Status\r\n  */\r\nHAL_StatusTypeDef HAL_FLASH_Lock(void)\r\n{\r\n  /* Set the LOCK Bit to lock the FLASH Registers access */\r\n  FLASH->CR |= FLASH_CR_LOCK;\r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Unlock the FLASH Option Control Registers access.\r\n  * @retval HAL Status\r\n  */\r\nHAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)\r\n{\r\n  if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)\r\n  {\r\n    /* Authorizes the Option Byte register programming */\r\n    FLASH->OPTKEYR = FLASH_OPT_KEY1;\r\n    FLASH->OPTKEYR = FLASH_OPT_KEY2;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;\r\n  }  \r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Lock the FLASH Option Control Registers access.\r\n  * @retval HAL Status \r\n  */\r\nHAL_StatusTypeDef HAL_FLASH_OB_Lock(void)\r\n{\r\n  /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */\r\n  FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;\r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Launch the option byte loading.\r\n  * @retval HAL Status\r\n  */\r\nHAL_StatusTypeDef HAL_FLASH_OB_Launch(void)\r\n{\r\n  /* Set the OPTSTRT bit in OPTCR register */\r\n  FLASH->OPTCR |= FLASH_OPTCR_OPTSTRT;\r\n\r\n  /* Wait for last operation to be completed */\r\n  return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions \r\n *  @brief   Peripheral Errors functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                ##### Peripheral Errors functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection permits to get in run-time Errors of the FLASH peripheral.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Get the specific FLASH error flag.\r\n  * @retval FLASH_ErrorCode: The returned value can be:\r\n  *            @arg FLASH_ERROR_ERS: FLASH Erasing Sequence error flag \r\n  *            @arg FLASH_ERROR_PGP: FLASH Programming Parallelism error flag  \r\n  *            @arg FLASH_ERROR_PGA: FLASH Programming Alignment error flag\r\n  *            @arg FLASH_ERROR_WRP: FLASH Write protected error flag\r\n  *            @arg FLASH_ERROR_OPERATION: FLASH operation Error flag \r\n  */\r\nuint32_t HAL_FLASH_GetError(void)\r\n{ \r\n   return pFlash.ErrorCode;\r\n}  \r\n  \r\n/**\r\n  * @}\r\n  */    \r\n\r\n/**\r\n  * @brief  Wait for a FLASH operation to complete.\r\n  * @param  Timeout maximum flash operationtimeout\r\n  * @retval HAL Status\r\n  */\r\nHAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)\r\n{ \r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Clear Error Code */\r\n  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r\n  \r\n  /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.\r\n     Even if the FLASH operation fails, the BUSY flag will be reset and an error\r\n     flag will be set */\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET) \r\n  { \r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n    } \r\n  }\r\n  \r\n  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ALL_ERRORS) != RESET)\r\n  {\r\n    /*Save the error code*/\r\n    FLASH_SetErrorCode();\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Check FLASH End of Operation flag  */\r\n  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)\r\n  {\r\n    /* Clear FLASH End of Operation pending bit */\r\n    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);\r\n  }\r\n\r\n  /* If there is an error flag set */\r\n  return HAL_OK;\r\n  \r\n}  \r\n\r\n/**\r\n  * @brief  Program a double word (64-bit) at a specified address.\r\n  * @note   This function must be used when the device voltage range is from\r\n  *         2.7V to 3.6V and an External Vpp is present.\r\n  *\r\n  * @note   If an erase and a program operations are requested simultaneously,    \r\n  *         the erase operation is performed before the program one.\r\n  *  \r\n  * @param  Address specifies the address to be programmed.\r\n  * @param  Data specifies the data to be programmed.\r\n  * @retval None\r\n  */\r\nstatic void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_FLASH_ADDRESS(Address));\r\n  \r\n  /* If the previous operation is completed, proceed to program the new data */\r\n  FLASH->CR &= CR_PSIZE_MASK;\r\n  FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;\r\n  FLASH->CR |= FLASH_CR_PG;\r\n\r\n  /* Program the double-word */\r\n  *(__IO uint32_t*)Address = (uint32_t)Data;\r\n  *(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32);\r\n\r\n  /* Data synchronous Barrier (DSB) Just after the write operation\r\n     This will force the CPU to respect the sequence of instruction (no optimization).*/\r\n  __DSB();\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Program word (32-bit) at a specified address.\r\n  * @note   This function must be used when the device voltage range is from\r\n  *         2.7V to 3.6V.\r\n  *\r\n  * @note   If an erase and a program operations are requested simultaneously,    \r\n  *         the erase operation is performed before the program one.\r\n  *  \r\n  * @param  Address specifies the address to be programmed.\r\n  * @param  Data specifies the data to be programmed.\r\n  * @retval None\r\n  */\r\nstatic void FLASH_Program_Word(uint32_t Address, uint32_t Data)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_FLASH_ADDRESS(Address));\r\n  \r\n  /* If the previous operation is completed, proceed to program the new data */\r\n  FLASH->CR &= CR_PSIZE_MASK;\r\n  FLASH->CR |= FLASH_PSIZE_WORD;\r\n  FLASH->CR |= FLASH_CR_PG;\r\n\r\n  *(__IO uint32_t*)Address = Data;\r\n  \r\n  /* Data synchronous Barrier (DSB) Just after the write operation\r\n     This will force the CPU to respect the sequence of instruction (no optimization).*/\r\n  __DSB();\r\n}\r\n\r\n/**\r\n  * @brief  Program a half-word (16-bit) at a specified address.\r\n  * @note   This function must be used when the device voltage range is from\r\n  *         2.7V to 3.6V.\r\n  *\r\n  * @note   If an erase and a program operations are requested simultaneously,    \r\n  *         the erase operation is performed before the program one.\r\n  *  \r\n  * @param  Address specifies the address to be programmed.\r\n  * @param  Data specifies the data to be programmed.\r\n  * @retval None\r\n  */\r\nstatic void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_FLASH_ADDRESS(Address));\r\n  \r\n  /* If the previous operation is completed, proceed to program the new data */\r\n  FLASH->CR &= CR_PSIZE_MASK;\r\n  FLASH->CR |= FLASH_PSIZE_HALF_WORD;\r\n  FLASH->CR |= FLASH_CR_PG;\r\n\r\n  *(__IO uint16_t*)Address = Data;\r\n\r\n  /* Data synchronous Barrier (DSB) Just after the write operation\r\n     This will force the CPU to respect the sequence of instruction (no optimization).*/\r\n  __DSB();\r\n  \r\n}\r\n\r\n/**\r\n  * @brief  Program byte (8-bit) at a specified address.\r\n  * @note   This function must be used when the device voltage range is from\r\n  *         2.7V to 3.6V.\r\n  *\r\n  * @note   If an erase and a program operations are requested simultaneously,    \r\n  *         the erase operation is performed before the program one.\r\n  *  \r\n  * @param  Address specifies the address to be programmed.\r\n  * @param  Data specifies the data to be programmed.\r\n  * @retval None\r\n  */\r\nstatic void FLASH_Program_Byte(uint32_t Address, uint8_t Data)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_FLASH_ADDRESS(Address));\r\n  \r\n  /* If the previous operation is completed, proceed to program the new data */\r\n  FLASH->CR &= CR_PSIZE_MASK;\r\n  FLASH->CR |= FLASH_PSIZE_BYTE;\r\n  FLASH->CR |= FLASH_CR_PG;\r\n\r\n  *(__IO uint8_t*)Address = Data;\r\n\r\n  /* Data synchronous Barrier (DSB) Just after the write operation\r\n     This will force the CPU to respect the sequence of instruction (no optimization).*/\r\n  __DSB();\r\n}\r\n\r\n/**\r\n  * @brief  Set the specific FLASH error flag.\r\n  * @retval None\r\n  */\r\nstatic void FLASH_SetErrorCode(void)\r\n{\r\n  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET)\r\n  {\r\n    pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION;\r\n  }\r\n  \r\n  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET)\r\n  {\r\n   pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;\r\n  }\r\n  \r\n  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET)\r\n  {\r\n   pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;\r\n  }\r\n  \r\n  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET)\r\n  {\r\n    pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP;\r\n  }\r\n  \r\n  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ERSERR) != RESET)\r\n  {\r\n    pFlash.ErrorCode |= HAL_FLASH_ERROR_ERS;\r\n  }\r\n  \r\n#if defined (FLASH_OPTCR2_PCROP)\r\n  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET)\r\n  { \r\n   pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;\r\n  }  \r\n#endif /* FLASH_OPTCR2_PCROP */\r\n  \r\n  /* Clear error programming flags */\r\n  __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS);\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_FLASH_MODULE_ENABLED */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_flash_ex.c\r\n  * @author  MCD Application Team\r\n  * @brief   Extended FLASH HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the FLASH extension peripheral:\r\n  *           + Extended programming operations functions\r\n  *  \r\n  @verbatim\r\n  ==============================================================================\r\n                   ##### Flash Extension features #####\r\n  ==============================================================================\r\n           \r\n  [..] Comparing to other previous devices, the FLASH interface for STM32F76xx/STM32F77xx \r\n       devices contains the following additional features \r\n       \r\n       (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write\r\n           capability (RWW)\r\n       (+) Dual bank memory organization       \r\n       (+) Dual boot mode\r\n   \r\n                      ##### How to use this driver #####\r\n  ==============================================================================\r\n  [..] This driver provides functions to configure and program the FLASH memory \r\n       of all STM32F7xx devices. It includes\r\n      (#) FLASH Memory Erase functions: \r\n           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and \r\n                HAL_FLASH_Lock() functions\r\n           (++) Erase function: Erase sector, erase all sectors\r\n           (++) There are two modes of erase :\r\n             (+++) Polling Mode using HAL_FLASHEx_Erase()\r\n             (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()\r\n             \r\n      (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to :\r\n           (++) Set/Reset the write protection\r\n           (++) Set the Read protection Level\r\n           (++) Set the BOR level\r\n           (++) Program the user Option Bytes\r\n  \r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup FLASHEx FLASHEx\r\n  * @brief FLASH HAL Extension module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_FLASH_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @addtogroup FLASHEx_Private_Constants\r\n  * @{\r\n  */    \r\n#define SECTOR_MASK               0xFFFFFF07U\r\n#define FLASH_TIMEOUT_VALUE       50000U/* 50 s */\r\n/**\r\n  * @}\r\n  */\r\n    \r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @addtogroup FLASHEx_Private_Variables\r\n  * @{\r\n  */    \r\nextern FLASH_ProcessTypeDef pFlash;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private function prototypes -----------------------------------------------*/\r\n/** @addtogroup FLASHEx_Private_Functions\r\n  * @{\r\n  */\r\n/* Option bytes control */\r\nstatic HAL_StatusTypeDef  FLASH_OB_EnableWRP(uint32_t WRPSector);\r\nstatic HAL_StatusTypeDef  FLASH_OB_DisableWRP(uint32_t WRPSector);\r\nstatic HAL_StatusTypeDef  FLASH_OB_RDP_LevelConfig(uint8_t Level);\r\nstatic HAL_StatusTypeDef  FLASH_OB_BOR_LevelConfig(uint8_t Level);\r\nstatic HAL_StatusTypeDef  FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address);\r\nstatic uint32_t           FLASH_OB_GetUser(void);\r\nstatic uint32_t           FLASH_OB_GetWRP(void);\r\nstatic uint8_t            FLASH_OB_GetRDP(void);\r\nstatic uint32_t           FLASH_OB_GetBOR(void);\r\nstatic uint32_t           FLASH_OB_GetBootAddress(uint32_t BootOption);\r\n\r\n#if defined (FLASH_OPTCR_nDBANK)\r\nstatic void               FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks);\r\nstatic HAL_StatusTypeDef  FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \\\r\n                                              uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot);\r\n#else\r\nstatic void               FLASH_MassErase(uint8_t VoltageRange);\r\nstatic HAL_StatusTypeDef  FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby);\r\n#endif /* FLASH_OPTCR_nDBANK */\r\n\r\n#if defined (FLASH_OPTCR2_PCROP)\r\nstatic HAL_StatusTypeDef  FLASH_OB_PCROP_Config(uint32_t PCROPSector);\r\nstatic HAL_StatusTypeDef  FLASH_OB_PCROP_RDP_Config(uint32_t Pcrop_Rdp);\r\nstatic uint32_t           FLASH_OB_GetPCROP(void);\r\nstatic uint32_t           FLASH_OB_GetPCROPRDP(void);\r\n#endif /* FLASH_OPTCR2_PCROP */\r\n\r\nextern HAL_StatusTypeDef  FLASH_WaitForLastOperation(uint32_t Timeout);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions\r\n *  @brief   Extended IO operation functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                ##### Extended programming operation functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides a set of functions allowing to manage the Extension FLASH \r\n    programming operations Operations.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n/**\r\n  * @brief  Perform a mass erase or erase the specified FLASH memory sectors \r\n  * @param[in]  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that\r\n  *         contains the configuration information for the erasing.\r\n  * \r\n  * @param[out]  SectorError pointer to variable  that\r\n  *         contains the configuration information on faulty sector in case of error \r\n  *         (0xFFFFFFFF means that all the sectors have been correctly erased)\r\n  * \r\n  * @retval HAL Status\r\n  */\r\nHAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)\r\n{\r\n  HAL_StatusTypeDef status = HAL_ERROR;\r\n  uint32_t index = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(&pFlash);\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));\r\n\r\n  /* Wait for last operation to be completed */\r\n  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r\n\r\n  if(status == HAL_OK)\r\n  {\r\n    /*Initialization of SectorError variable*/\r\n    *SectorError = 0xFFFFFFFFU;\r\n    \r\n    if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)\r\n    {\r\n      /*Mass erase to be done*/\r\n#if defined (FLASH_OPTCR_nDBANK)      \r\n      FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);\r\n#else\r\n      FLASH_MassErase((uint8_t) pEraseInit->VoltageRange);      \r\n#endif /* FLASH_OPTCR_nDBANK */\r\n                      \r\n      /* Wait for last operation to be completed */\r\n      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r\n      \r\n      /* if the erase operation is completed, disable the MER Bit */\r\n      FLASH->CR &= (~FLASH_MER_BIT);\r\n    }\r\n    else\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));\r\n\r\n      /* Erase by sector by sector to be done*/\r\n      for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++)\r\n      {\r\n        FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange);\r\n\r\n        /* Wait for last operation to be completed */\r\n        status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r\n        \r\n        /* If the erase operation is completed, disable the SER Bit and SNB Bits */\r\n        CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB)); \r\n\r\n        if(status != HAL_OK) \r\n        {\r\n          /* In case of error, stop erase procedure and return the faulty sector*/\r\n          *SectorError = index;\r\n          break;\r\n        }\r\n      }\r\n    }\r\n  }\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(&pFlash);\r\n\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Perform a mass erase or erase the specified FLASH memory sectors  with interrupt enabled\r\n  * @param  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that\r\n  *         contains the configuration information for the erasing.\r\n  * \r\n  * @retval HAL Status\r\n  */\r\nHAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Process Locked */\r\n  __HAL_LOCK(&pFlash);\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));\r\n\r\n  /* Enable End of FLASH Operation interrupt */\r\n  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);\r\n  \r\n  /* Enable Error source interrupt */\r\n  __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);\r\n  \r\n  /* Clear pending flags (if any) */  \r\n  __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP    | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\\\r\n                         FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR);  \r\n  \r\n  if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)\r\n  {\r\n    /*Mass erase to be done*/\r\n    pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;\r\n#if defined (FLASH_OPTCR_nDBANK)    \r\n    FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);\r\n#else\r\n    FLASH_MassErase((uint8_t) pEraseInit->VoltageRange);      \r\n#endif /* FLASH_OPTCR_nDBANK */    \r\n  }\r\n  else\r\n  {\r\n    /* Erase by sector to be done*/\r\n\r\n    /* Check the parameters */\r\n    assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));\r\n\r\n    pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE;\r\n    pFlash.NbSectorsToErase = pEraseInit->NbSectors;\r\n    pFlash.Sector = pEraseInit->Sector;\r\n    pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange;\r\n\r\n    /*Erase 1st sector and wait for IT*/\r\n    FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->VoltageRange);\r\n  }\r\n\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Program option bytes\r\n  * @param  pOBInit pointer to an FLASH_OBInitStruct structure that\r\n  *         contains the configuration information for the programming.\r\n  * \r\n  * @retval HAL Status\r\n  */\r\nHAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)\r\n{\r\n  HAL_StatusTypeDef status = HAL_ERROR;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(&pFlash);\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_OPTIONBYTE(pOBInit->OptionType));\r\n\r\n  /* Write protection configuration */\r\n  if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)\r\n  {\r\n    assert_param(IS_WRPSTATE(pOBInit->WRPState));\r\n    if(pOBInit->WRPState == OB_WRPSTATE_ENABLE)\r\n    {\r\n      /*Enable of Write protection on the selected Sector*/\r\n      status = FLASH_OB_EnableWRP(pOBInit->WRPSector);\r\n    }\r\n    else\r\n    {\r\n      /*Disable of Write protection on the selected Sector*/\r\n      status = FLASH_OB_DisableWRP(pOBInit->WRPSector);\r\n    }\r\n  }\r\n\r\n  /* Read protection configuration */\r\n  if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)\r\n  {\r\n    status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);\r\n  }\r\n\r\n  /* USER  configuration */\r\n  if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)\r\n  {\r\n#if defined (FLASH_OPTCR_nDBANK)\r\n    status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW, \r\n                                 pOBInit->USERConfig & OB_IWDG_SW,\r\n                                 pOBInit->USERConfig & OB_STOP_NO_RST,\r\n                                 pOBInit->USERConfig & OB_STDBY_NO_RST, \r\n                                 pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE,\r\n                                 pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE,\r\n                                 pOBInit->USERConfig & OB_NDBANK_SINGLE_BANK,\r\n                                 pOBInit->USERConfig & OB_DUAL_BOOT_DISABLE);\r\n#else\r\n    status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW, \r\n                                 pOBInit->USERConfig & OB_IWDG_SW,\r\n                                 pOBInit->USERConfig & OB_STOP_NO_RST,\r\n                                 pOBInit->USERConfig & OB_STDBY_NO_RST, \r\n                                 pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE,\r\n                                 pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE);    \r\n#endif /* FLASH_OPTCR_nDBANK */\r\n  }\r\n  \r\n  /* BOR Level  configuration */\r\n  if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)\r\n  {\r\n    status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel);\r\n  }\r\n  \r\n  /* Boot 0 Address configuration */\r\n  if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_0) == OPTIONBYTE_BOOTADDR_0)\r\n  {\r\n    status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_0, pOBInit->BootAddr0);\r\n  }\r\n  \r\n  /* Boot 1 Address configuration */\r\n  if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_1) == OPTIONBYTE_BOOTADDR_1)\r\n  {\r\n    status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_1, pOBInit->BootAddr1);\r\n  }\r\n  \r\n#if defined (FLASH_OPTCR2_PCROP)\r\n  /* PCROP configuration */\r\n  if((pOBInit->OptionType & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP)\r\n  {\r\n    status = FLASH_OB_PCROP_Config(pOBInit->PCROPSector);\r\n  }\r\n  \r\n  /* PCROP_RDP configuration */\r\n  if((pOBInit->OptionType & OPTIONBYTE_PCROP_RDP) == OPTIONBYTE_PCROP_RDP)\r\n  {\r\n    status = FLASH_OB_PCROP_RDP_Config(pOBInit->PCROPRdp);\r\n  }\r\n#endif /* FLASH_OPTCR2_PCROP */\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(&pFlash);\r\n\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Get the Option byte configuration\r\n  * @param  pOBInit pointer to an FLASH_OBInitStruct structure that\r\n  *         contains the configuration information for the programming.\r\n  * \r\n  * @retval None\r\n  */\r\nvoid HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)\r\n{\r\n  pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\\\r\n\t                OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1;\r\n\r\n  /*Get WRP*/\r\n  pOBInit->WRPSector = FLASH_OB_GetWRP();\r\n\r\n  /*Get RDP Level*/\r\n  pOBInit->RDPLevel = FLASH_OB_GetRDP();\r\n\r\n  /*Get USER*/\r\n  pOBInit->USERConfig = FLASH_OB_GetUser();\r\n\r\n  /*Get BOR Level*/\r\n  pOBInit->BORLevel = FLASH_OB_GetBOR();\r\n  \r\n  /*Get Boot Address when Boot pin = 0 */\r\n  pOBInit->BootAddr0 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_0);\r\n  \r\n  /*Get Boot Address when Boot pin = 1 */\r\n  pOBInit->BootAddr1 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_1);\r\n\r\n#if defined (FLASH_OPTCR2_PCROP)\r\n  /*Get PCROP Sectors */\r\n  pOBInit->PCROPSector = FLASH_OB_GetPCROP();\r\n  \r\n  /*Get PCROP_RDP Value */\r\n  pOBInit->PCROPRdp = FLASH_OB_GetPCROPRDP();\r\n#endif /* FLASH_OPTCR2_PCROP */\r\n}\r\n/**\r\n  * @}\r\n  */\r\n\r\n#if defined (FLASH_OPTCR_nDBANK)\r\n/**\r\n  * @brief  Full erase of FLASH memory sectors \r\n  * @param  VoltageRange The device voltage range which defines the erase parallelism.  \r\n  *          This parameter can be one of the following values:\r\n  *            @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, \r\n  *                                  the operation will be done by byte (8-bit) \r\n  *            @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,\r\n  *                                  the operation will be done by half word (16-bit)\r\n  *            @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,\r\n  *                                  the operation will be done by word (32-bit)\r\n  *            @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, \r\n  *                                  the operation will be done by double word (64-bit)\r\n  * @param  Banks Banks to be erased\r\n  *          This parameter can be one of the following values:\r\n  *            @arg FLASH_BANK_1: Bank1 to be erased\r\n  *            @arg FLASH_BANK_2: Bank2 to be erased\r\n  *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased\r\n  *\r\n  * @retval HAL Status\r\n  */\r\nstatic void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_VOLTAGERANGE(VoltageRange));\r\n  assert_param(IS_FLASH_BANK(Banks));\r\n\r\n  /* if the previous operation is completed, proceed to erase all sectors */\r\n  FLASH->CR &= CR_PSIZE_MASK;\r\n  if(Banks == FLASH_BANK_BOTH)\r\n  {\r\n    /* bank1 & bank2 will be erased*/\r\n    FLASH->CR |= FLASH_MER_BIT;\r\n  }\r\n  else if(Banks == FLASH_BANK_2)\r\n  {\r\n    /*Only bank2 will be erased*/\r\n    FLASH->CR |= FLASH_CR_MER2;\r\n  }\r\n  else\r\n  {\r\n    /*Only bank1 will be erased*/\r\n    FLASH->CR |= FLASH_CR_MER1;    \r\n  }\r\n  FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8);\r\n  /* Data synchronous Barrier (DSB) Just after the write operation\r\n     This will force the CPU to respect the sequence of instruction (no optimization).*/\r\n  __DSB();\r\n}\r\n\r\n/**\r\n  * @brief  Erase the specified FLASH memory sector\r\n  * @param  Sector FLASH sector to erase\r\n  *         The value of this parameter depend on device used within the same series      \r\n  * @param  VoltageRange The device voltage range which defines the erase parallelism.  \r\n  *          This parameter can be one of the following values:\r\n  *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, \r\n  *                                  the operation will be done by byte (8-bit) \r\n  *            @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,\r\n  *                                  the operation will be done by half word (16-bit)\r\n  *            @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,\r\n  *                                  the operation will be done by word (32-bit)\r\n  *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, \r\n  *                                  the operation will be done by double word (64-bit)\r\n  * \r\n  * @retval None\r\n  */\r\nvoid FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)\r\n{\r\n  uint32_t tmp_psize = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_FLASH_SECTOR(Sector));\r\n  assert_param(IS_VOLTAGERANGE(VoltageRange));\r\n  \r\n  if(VoltageRange == FLASH_VOLTAGE_RANGE_1)\r\n  {\r\n     tmp_psize = FLASH_PSIZE_BYTE;\r\n  }\r\n  else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)\r\n  {\r\n    tmp_psize = FLASH_PSIZE_HALF_WORD;\r\n  }\r\n  else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)\r\n  {\r\n    tmp_psize = FLASH_PSIZE_WORD;\r\n  }\r\n  else\r\n  {\r\n    tmp_psize = FLASH_PSIZE_DOUBLE_WORD;\r\n  }\r\n  \r\n  /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */\r\n  if(Sector > FLASH_SECTOR_11) \r\n  {\r\n    Sector += 4;\r\n  }  \r\n\r\n  /* If the previous operation is completed, proceed to erase the sector */\r\n  FLASH->CR &= CR_PSIZE_MASK;\r\n  FLASH->CR |= tmp_psize;\r\n  CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);\r\n  FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos);\r\n  FLASH->CR |= FLASH_CR_STRT;\r\n  \r\n  /* Data synchronous Barrier (DSB) Just after the write operation\r\n     This will force the CPU to respect the sequence of instruction (no optimization).*/\r\n  __DSB();\r\n}\r\n\r\n/**\r\n  * @brief  Return the FLASH Write Protection Option Bytes value.\r\n  * @retval uint32_t FLASH Write Protection Option Bytes value\r\n  */\r\nstatic uint32_t FLASH_OB_GetWRP(void)\r\n{\r\n  /* Return the FLASH write protection Register value */\r\n  return ((uint32_t)(FLASH->OPTCR & 0x0FFF0000));\r\n}\r\n\r\n/**\r\n  * @brief  Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.    \r\n  * @param  Wwdg Selects the IWDG mode\r\n  *          This parameter can be one of the following values:\r\n  *            @arg OB_WWDG_SW: Software WWDG selected\r\n  *            @arg OB_WWDG_HW: Hardware WWDG selected\r\n  * @param  Iwdg Selects the WWDG mode\r\n  *          This parameter can be one of the following values:\r\n  *            @arg OB_IWDG_SW: Software IWDG selected\r\n  *            @arg OB_IWDG_HW: Hardware IWDG selected\r\n  * @param  Stop Reset event when entering STOP mode.\r\n  *          This parameter  can be one of the following values:\r\n  *            @arg OB_STOP_NO_RST: No reset generated when entering in STOP\r\n  *            @arg OB_STOP_RST: Reset generated when entering in STOP\r\n  * @param  Stdby Reset event when entering Standby mode.\r\n  *          This parameter  can be one of the following values:\r\n  *            @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY\r\n  *            @arg OB_STDBY_RST: Reset generated when entering in STANDBY\r\n  * @param  Iwdgstop Independent watchdog counter freeze in Stop mode.\r\n  *          This parameter  can be one of the following values:\r\n  *            @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP\r\n  *            @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP\r\n  * @param  Iwdgstdby Independent watchdog counter freeze in standby mode.\r\n  *          This parameter  can be one of the following values:\r\n  *            @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY\r\n  *            @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY\r\n  * @param  NDBank Flash Single Bank mode enabled.\r\n  *          This parameter  can be one of the following values:\r\n  *            @arg OB_NDBANK_SINGLE_BANK: enable 256 bits mode (Flash is a single bank)\r\n  *            @arg OB_NDBANK_DUAL_BANK: disable 256 bits mode (Flash is a dual bank in 128 bits mode)  \r\n  * @param  NDBoot Flash Dual boot mode disable.\r\n  *          This parameter  can be one of the following values:\r\n  *            @arg OB_DUAL_BOOT_DISABLE: Disable Dual Boot\r\n  *            @arg OB_DUAL_BOOT_ENABLE: Enable Dual Boot\r\n\r\n  * @retval HAL Status\r\n  */\r\nstatic HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \\\r\n                                             uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot)\r\n{\r\n  uint32_t useroptionmask = 0x00;\r\n  uint32_t useroptionvalue = 0x00;\r\n\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_OB_WWDG_SOURCE(Wwdg));\r\n  assert_param(IS_OB_IWDG_SOURCE(Iwdg));\r\n  assert_param(IS_OB_STOP_SOURCE(Stop));\r\n  assert_param(IS_OB_STDBY_SOURCE(Stdby));\r\n  assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop));\r\n  assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby));\r\n  assert_param(IS_OB_NDBANK(NDBank));\r\n  assert_param(IS_OB_NDBOOT(NDBoot));\r\n  \r\n  /* Wait for last operation to be completed */\r\n  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r\n  \r\n  if(status == HAL_OK)\r\n  {\r\n    useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \\\r\n                      FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY | \\\r\n                      FLASH_OPTCR_nDBOOT | FLASH_OPTCR_nDBANK);\r\n                      \r\n    useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby | NDBoot | NDBank);\r\n        \r\n    /* Update User Option Byte */               \r\n    MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue);\r\n  }\r\n  \r\n  return status; \r\n}\r\n\r\n/**\r\n  * @brief  Return the FLASH User Option Byte value.\r\n  * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6), \r\n  *         nRST_STDBY(Bit7), nDBOOT(Bit28), nDBANK(Bit29), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31).\r\n  */\r\nstatic uint32_t FLASH_OB_GetUser(void)\r\n{\r\n  /* Return the User Option Byte */\r\n  return ((uint32_t)(FLASH->OPTCR & 0xF00000F0U));\r\n}\r\n#else\r\n\r\n/**\r\n  * @brief  Full erase of FLASH memory sectors \r\n  * @param  VoltageRange The device voltage range which defines the erase parallelism.  \r\n  *          This parameter can be one of the following values:\r\n  *            @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, \r\n  *                                  the operation will be done by byte (8-bit) \r\n  *            @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,\r\n  *                                  the operation will be done by half word (16-bit)\r\n  *            @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,\r\n  *                                  the operation will be done by word (32-bit)\r\n  *            @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, \r\n  *                                  the operation will be done by double word (64-bit)\r\n  *\r\n  * @retval HAL Status\r\n  */\r\nstatic void FLASH_MassErase(uint8_t VoltageRange)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_VOLTAGERANGE(VoltageRange));\r\n\r\n  /* if the previous operation is completed, proceed to erase all sectors */\r\n  FLASH->CR &= CR_PSIZE_MASK;\r\n  FLASH->CR |= FLASH_CR_MER;\r\n  FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8);\r\n  /* Data synchronous Barrier (DSB) Just after the write operation\r\n     This will force the CPU to respect the sequence of instruction (no optimization).*/\r\n  __DSB();\r\n}\r\n\r\n/**\r\n  * @brief  Erase the specified FLASH memory sector\r\n  * @param  Sector FLASH sector to erase\r\n  *         The value of this parameter depend on device used within the same series      \r\n  * @param  VoltageRange The device voltage range which defines the erase parallelism.  \r\n  *          This parameter can be one of the following values:\r\n  *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, \r\n  *                                  the operation will be done by byte (8-bit) \r\n  *            @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,\r\n  *                                  the operation will be done by half word (16-bit)\r\n  *            @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,\r\n  *                                  the operation will be done by word (32-bit)\r\n  *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, \r\n  *                                  the operation will be done by double word (64-bit)\r\n  * \r\n  * @retval None\r\n  */\r\nvoid FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)\r\n{\r\n  uint32_t tmp_psize = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_FLASH_SECTOR(Sector));\r\n  assert_param(IS_VOLTAGERANGE(VoltageRange));\r\n  \r\n  if(VoltageRange == FLASH_VOLTAGE_RANGE_1)\r\n  {\r\n     tmp_psize = FLASH_PSIZE_BYTE;\r\n  }\r\n  else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)\r\n  {\r\n    tmp_psize = FLASH_PSIZE_HALF_WORD;\r\n  }\r\n  else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)\r\n  {\r\n    tmp_psize = FLASH_PSIZE_WORD;\r\n  }\r\n  else\r\n  {\r\n    tmp_psize = FLASH_PSIZE_DOUBLE_WORD;\r\n  }\r\n\r\n  /* If the previous operation is completed, proceed to erase the sector */\r\n  FLASH->CR &= CR_PSIZE_MASK;\r\n  FLASH->CR |= tmp_psize;\r\n  FLASH->CR &= SECTOR_MASK;\r\n  FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos);\r\n  FLASH->CR |= FLASH_CR_STRT;\r\n  \r\n  /* Data synchronous Barrier (DSB) Just after the write operation\r\n     This will force the CPU to respect the sequence of instruction (no optimization).*/\r\n  __DSB();\r\n}\r\n\r\n/**\r\n  * @brief  Return the FLASH Write Protection Option Bytes value.\r\n  * @retval uint32_t FLASH Write Protection Option Bytes value\r\n  */\r\nstatic uint32_t FLASH_OB_GetWRP(void)\r\n{\r\n  /* Return the FLASH write protection Register value */\r\n  return ((uint32_t)(FLASH->OPTCR & 0x00FF0000));\r\n}\r\n\r\n/**\r\n  * @brief  Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.    \r\n  * @param  Wwdg Selects the IWDG mode\r\n  *          This parameter can be one of the following values:\r\n  *            @arg OB_WWDG_SW: Software WWDG selected\r\n  *            @arg OB_WWDG_HW: Hardware WWDG selected\r\n  * @param  Iwdg Selects the WWDG mode\r\n  *          This parameter can be one of the following values:\r\n  *            @arg OB_IWDG_SW: Software IWDG selected\r\n  *            @arg OB_IWDG_HW: Hardware IWDG selected\r\n  * @param  Stop Reset event when entering STOP mode.\r\n  *          This parameter  can be one of the following values:\r\n  *            @arg OB_STOP_NO_RST: No reset generated when entering in STOP\r\n  *            @arg OB_STOP_RST: Reset generated when entering in STOP\r\n  * @param  Stdby Reset event when entering Standby mode.\r\n  *          This parameter  can be one of the following values:\r\n  *            @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY\r\n  *            @arg OB_STDBY_RST: Reset generated when entering in STANDBY\r\n  * @param  Iwdgstop Independent watchdog counter freeze in Stop mode.\r\n  *          This parameter  can be one of the following values:\r\n  *            @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP\r\n  *            @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP\r\n  * @param  Iwdgstdby Independent watchdog counter freeze in standby mode.\r\n  *          This parameter  can be one of the following values:\r\n  *            @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY\r\n  *            @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY           \r\n  * @retval HAL Status\r\n  */\r\nstatic HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby)\r\n{\r\n  uint32_t useroptionmask = 0x00;\r\n  uint32_t useroptionvalue = 0x00;\r\n\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_OB_WWDG_SOURCE(Wwdg));\r\n  assert_param(IS_OB_IWDG_SOURCE(Iwdg));\r\n  assert_param(IS_OB_STOP_SOURCE(Stop));\r\n  assert_param(IS_OB_STDBY_SOURCE(Stdby));\r\n  assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop));\r\n  assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby));\r\n\r\n  /* Wait for last operation to be completed */\r\n  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r\n  \r\n  if(status == HAL_OK)\r\n  {\r\n    useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \\\r\n                      FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY);\r\n                      \r\n    useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby);\r\n        \r\n    /* Update User Option Byte */               \r\n    MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue);\r\n  }\r\n  \r\n  return status; \r\n\r\n}\r\n\r\n/**\r\n  * @brief  Return the FLASH User Option Byte value.\r\n  * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6), \r\n  *         nRST_STDBY(Bit7), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31).\r\n  */\r\nstatic uint32_t FLASH_OB_GetUser(void)\r\n{\r\n  /* Return the User Option Byte */\r\n  return ((uint32_t)(FLASH->OPTCR & 0xC00000F0U));\r\n}\r\n#endif /* FLASH_OPTCR_nDBANK */\r\n\r\n/**\r\n  * @brief  Enable the write protection of the desired bank1 or bank2 sectors\r\n  *\r\n  * @note   When the memory read protection level is selected (RDP level = 1), \r\n  *         it is not possible to program or erase the flash sector i if CortexM7  \r\n  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1    \r\n  * \r\n  * @param  WRPSector specifies the sector(s) to be write protected.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices)\r\n  *              or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices)\r\n  *              or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices)\r\n  *            @arg OB_WRP_SECTOR_All\r\n  *\r\n  * @retval HAL FLASH State   \r\n  */\r\nstatic HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_OB_WRP_SECTOR(WRPSector));\r\n    \r\n  /* Wait for last operation to be completed */\r\n  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r\n\r\n  if(status == HAL_OK)\r\n  {\r\n    /*Write protection enabled on sectors */\r\n    FLASH->OPTCR &= (~WRPSector);  \r\n  }\r\n  \r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Disable the write protection of the desired bank1 or bank 2 sectors\r\n  *\r\n  * @note   When the memory read protection level is selected (RDP level = 1), \r\n  *         it is not possible to program or erase the flash sector i if CortexM4  \r\n  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1  \r\n  * \r\n  * @param  WRPSector specifies the sector(s) to be write protected.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices)\r\n  *              or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices)\r\n  *              or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices)                      \r\n  *            @arg OB_WRP_Sector_All\r\n  *\r\n  *\r\n  * @retval HAL Status   \r\n  */\r\nstatic HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_OB_WRP_SECTOR(WRPSector));\r\n    \r\n  /* Wait for last operation to be completed */\r\n  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r\n\r\n  if(status == HAL_OK)\r\n  {\r\n    /* Write protection disabled on sectors */\r\n    FLASH->OPTCR |= (WRPSector); \r\n  }\r\n\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Set the read protection level.\r\n  * @param  Level specifies the read protection level.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg OB_RDP_LEVEL_0: No protection\r\n  *            @arg OB_RDP_LEVEL_1: Read protection of the memory\r\n  *            @arg OB_RDP_LEVEL_2: Full chip protection\r\n  *   \r\n  * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0\r\n  *    \r\n  * @retval HAL Status\r\n  */\r\nstatic HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_OB_RDP_LEVEL(Level));\r\n    \r\n  /* Wait for last operation to be completed */\r\n  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r\n\r\n  if(status == HAL_OK)\r\n  { \r\n    *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = Level;\r\n  }\r\n  \r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Set the BOR Level. \r\n  * @param  Level specifies the Option Bytes BOR Reset Level.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V\r\n  *            @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V\r\n  *            @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V\r\n  *            @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V\r\n  * @retval HAL Status\r\n  */\r\nstatic HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_OB_BOR_LEVEL(Level));\r\n\r\n  /* Set the BOR Level */\r\n  MODIFY_REG(FLASH->OPTCR, FLASH_OPTCR_BOR_LEV, Level);\r\n  \r\n  return HAL_OK;\r\n  \r\n}\r\n\r\n/**\r\n  * @brief  Configure Boot base address.\r\n  * \r\n  * @param   BootOption  specifies Boot base address depending from Boot pin = 0 or pin = 1\r\n  *          This parameter can be one of the following values:\r\n  *            @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0                 \r\n  *            @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1  \r\n  * @param   Address specifies Boot base address\r\n  *          This parameter can be one of the following values:\r\n  *            @arg OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000)                 \r\n  *            @arg OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000) \r\n  *            @arg OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000)  \r\n  *            @arg OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000)  \r\n  *            @arg OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000)                 \r\n  *            @arg OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000)                    \r\n  *            @arg OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000)              \r\n  *    \r\n  * @retval HAL Status\r\n  */\r\nstatic HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_OB_BOOT_ADDRESS(Address));\r\n    \r\n  /* Wait for last operation to be completed */\r\n  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r\n  \r\n  if(status == HAL_OK)\r\n  {\r\n    if(BootOption == OPTIONBYTE_BOOTADDR_0)\r\n    {\t\t\t\r\n      MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD0, Address);\r\n    }\r\n    else\r\n    {\r\n      MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD1, (Address << 16));\r\n    }\r\n  }\r\n  \r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the FLASH Read Protection level.\r\n  * @retval FlagStatus FLASH ReadOut Protection Status:\r\n  *         This parameter can be one of the following values:\r\n  *            @arg OB_RDP_LEVEL_0: No protection\r\n  *            @arg OB_RDP_LEVEL_1: Read protection of the memory\r\n  *            @arg OB_RDP_LEVEL_2: Full chip protection\r\n  */\r\nstatic uint8_t FLASH_OB_GetRDP(void)\r\n{\r\n  uint8_t readstatus = OB_RDP_LEVEL_0;\r\n  \r\n  if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_0)\r\n  {\r\n    readstatus = OB_RDP_LEVEL_0;\r\n  }\r\n  else if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_2)\r\n  {\r\n    readstatus = OB_RDP_LEVEL_2;\r\n  }\r\n  else \r\n  {\r\n    readstatus = OB_RDP_LEVEL_1;\r\n  }\r\n\r\n  return readstatus;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the FLASH BOR level.\r\n  * @retval uint32_t The FLASH BOR level:\r\n  *           - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V\r\n  *           - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V\r\n  *           - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V\r\n  *           - OB_BOR_OFF   : Supply voltage ranges from 1.62 to 2.1 V  \r\n  */\r\nstatic uint32_t FLASH_OB_GetBOR(void)\r\n{\r\n  /* Return the FLASH BOR level */\r\n  return ((uint32_t)(FLASH->OPTCR & 0x0C));\r\n}\r\n\r\n/**\r\n  * @brief  Configure Boot base address.\r\n  * \r\n  * @param   BootOption  specifies Boot base address depending from Boot pin = 0 or pin = 1\r\n  *          This parameter can be one of the following values:\r\n  *            @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0                 \r\n  *            @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1       \r\n  *    \r\n  * @retval uint32_t Boot Base Address:\r\n  *            - OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000)                 \r\n  *            - OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000) \r\n  *            - OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000)  \r\n  *            - OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000)  \r\n  *            - OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000)                 \r\n  *            - OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000)                    \r\n  *            - OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000) \r\n  */\r\nstatic uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption)\r\n{  \r\n  uint32_t Address = 0;\r\n    \r\n\t/* Return the Boot base Address */\r\n  if(BootOption == OPTIONBYTE_BOOTADDR_0)\r\n  {\t\t\t\r\n    Address = FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD0;\r\n\t}\r\n  else\r\n\t{\r\n\t\tAddress = ((FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD1) >> 16);\r\n\t}\r\n\r\n  return Address;\r\n}\r\n\r\n#if defined (FLASH_OPTCR2_PCROP)\r\n/**\r\n  * @brief  Set the PCROP protection for sectors.\r\n  * @param  PCROPSector specifies the sector(s) to be PCROP protected.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg OB_PCROP_SECTOR_x: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_7\r\n  *            @arg OB_PCROP_SECTOR_ALL\r\n  *    \r\n  * @retval HAL Status\r\n  */\r\nstatic HAL_StatusTypeDef FLASH_OB_PCROP_Config(uint32_t PCROPSector)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_OB_PCROP_SECTOR(PCROPSector));\r\n    \r\n  /* Wait for last operation to be completed */\r\n  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r\n\r\n  if(status == HAL_OK)\r\n  { \r\n    MODIFY_REG(FLASH->OPTCR2, FLASH_OPTCR2_PCROP, PCROPSector);\r\n  }\r\n  \r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Set the PCROP_RDP value\r\n  * @param  Pcrop_Rdp specifies the PCROP_RDP bit value.\r\n  *    \r\n  * @retval HAL Status\r\n  */\r\nstatic HAL_StatusTypeDef FLASH_OB_PCROP_RDP_Config(uint32_t Pcrop_Rdp)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_OB_PCROP_RDP_VALUE(Pcrop_Rdp));\r\n    \r\n  /* Wait for last operation to be completed */\r\n  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r\n\r\n  if(status == HAL_OK)\r\n  { \r\n    MODIFY_REG(FLASH->OPTCR2, FLASH_OPTCR2_PCROP_RDP, Pcrop_Rdp);\r\n  }\r\n  \r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Return the FLASH PCROP Protection Option Bytes value.\r\n  * @retval uint32_t FLASH PCROP Protection Option Bytes value\r\n  */\r\nstatic uint32_t FLASH_OB_GetPCROP(void)\r\n{\r\n  /* Return the FLASH write protection Register value */\r\n  return ((uint32_t)(FLASH->OPTCR2 & FLASH_OPTCR2_PCROP));\r\n}\r\n\r\n/**\r\n  * @brief  Return the FLASH PCROP_RDP option byte value.\r\n  * @retval uint32_t FLASH PCROP_RDP option byte value\r\n  */\r\nstatic uint32_t FLASH_OB_GetPCROPRDP(void)\r\n{\r\n  /* Return the FLASH write protection Register value */\r\n  return ((uint32_t)(FLASH->OPTCR2 & FLASH_OPTCR2_PCROP_RDP));\r\n}\r\n#endif /* FLASH_OPTCR2_PCROP */\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n#endif /* HAL_FLASH_MODULE_ENABLED */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_gpio.c\r\n  * @author  MCD Application Team\r\n  * @brief   GPIO HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the General Purpose Input/Output (GPIO) peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + IO operation functions\r\n  *\r\n  @verbatim\r\n  ==============================================================================\r\n                    ##### GPIO Peripheral features #####\r\n  ==============================================================================\r\n  [..] \r\n  Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each\r\n  port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software\r\n  in several modes:\r\n  (+) Input mode \r\n  (+) Analog mode\r\n  (+) Output mode\r\n  (+) Alternate function mode\r\n  (+) External interrupt/event lines\r\n\r\n  [..]  \r\n  During and just after reset, the alternate functions and external interrupt  \r\n  lines are not active and the I/O ports are configured in input floating mode.\r\n  \r\n  [..]   \r\n  All GPIO pins have weak internal pull-up and pull-down resistors, which can be \r\n  activated or not.\r\n\r\n  [..]\r\n  In Output or Alternate mode, each IO can be configured on open-drain or push-pull\r\n  type and the IO speed can be selected depending on the VDD value.\r\n\r\n  [..]  \r\n  All ports have external interrupt/event capability. To use external interrupt \r\n  lines, the port must be configured in input mode. All available GPIO pins are \r\n  connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.\r\n  \r\n  [..]\r\n  The external interrupt/event controller consists of up to 23 edge detectors \r\n  (16 lines are connected to GPIO) for generating event/interrupt requests (each \r\n  input line can be independently configured to select the type (interrupt or event) \r\n  and the corresponding trigger event (rising or falling or both). Each line can \r\n  also be masked independently. \r\n\r\n                     ##### How to use this driver #####\r\n  ==============================================================================  \r\n  [..]\r\n    (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). \r\n\r\n    (#) Configure the GPIO pin(s) using HAL_GPIO_Init().\r\n        (++) Configure the IO mode using \"Mode\" member from GPIO_InitTypeDef structure\r\n        (++) Activate Pull-up, Pull-down resistor using \"Pull\" member from GPIO_InitTypeDef \r\n             structure.\r\n        (++) In case of Output or alternate function mode selection: the speed is \r\n             configured through \"Speed\" member from GPIO_InitTypeDef structure.\r\n        (++) In alternate mode is selection, the alternate function connected to the IO\r\n             is configured through \"Alternate\" member from GPIO_InitTypeDef structure.\r\n        (++) Analog mode is required when a pin is to be used as ADC channel \r\n             or DAC output.\r\n        (++) In case of external interrupt/event selection the \"Mode\" member from \r\n             GPIO_InitTypeDef structure select the type (interrupt or event) and \r\n             the corresponding trigger event (rising or falling or both).\r\n\r\n    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority \r\n        mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using\r\n        HAL_NVIC_EnableIRQ().\r\n         \r\n    (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().\r\n            \r\n    (#) To set/reset the level of a pin configured in output mode use \r\n        HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().\r\n    \r\n    (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().\r\n\r\n                 \r\n    (#) During and just after reset, the alternate functions are not \r\n        active and the GPIO pins are configured in input floating mode (except JTAG\r\n        pins).\r\n  \r\n    (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose \r\n        (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has \r\n        priority over the GPIO function.\r\n  \r\n    (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as \r\n        general purpose PH0 and PH1, respectively, when the HSE oscillator is off. \r\n        The HSE has priority over the GPIO function.\r\n  \r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup GPIO GPIO\r\n  * @brief GPIO HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_GPIO_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @addtogroup GPIO_Private_Constants GPIO Private Constants\r\n  * @{\r\n  */\r\n#define GPIO_MODE             ((uint32_t)0x00000003U)\r\n#define EXTI_MODE             ((uint32_t)0x10000000U)\r\n#define GPIO_MODE_IT          ((uint32_t)0x00010000U)\r\n#define GPIO_MODE_EVT         ((uint32_t)0x00020000U)\r\n#define RISING_EDGE           ((uint32_t)0x00100000U)\r\n#define FALLING_EDGE          ((uint32_t)0x00200000U)\r\n#define GPIO_OUTPUT_TYPE      ((uint32_t)0x00000010U)\r\n\r\n#define GPIO_NUMBER           ((uint32_t)16U)\r\n/**\r\n  * @}\r\n  */\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup GPIO_Exported_Functions GPIO Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions\r\n *  @brief    Initialization and Configuration functions\r\n *\r\n@verbatim\r\n ===============================================================================\r\n              ##### Initialization and de-initialization functions #####\r\n ===============================================================================\r\n  [..]\r\n    This section provides functions allowing to initialize and de-initialize the GPIOs\r\n    to be ready for use.\r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.\r\n  * @param  GPIOx where x can be (A..K) to select the GPIO peripheral.\r\n  * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains\r\n  *         the configuration information for the specified GPIO peripheral.\r\n  * @retval None\r\n  */\r\nvoid HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)\r\n{\r\n  uint32_t position = 0x00;\r\n  uint32_t ioposition = 0x00;\r\n  uint32_t iocurrent = 0x00;\r\n  uint32_t temp = 0x00;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));\r\n  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));\r\n  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));\r\n  assert_param(IS_GPIO_PULL(GPIO_Init->Pull));\r\n\r\n  /* Configure the port pins */\r\n  for(position = 0; position < GPIO_NUMBER; position++)\r\n  {\r\n    /* Get the IO position */\r\n    ioposition = ((uint32_t)0x01) << position;\r\n    /* Get the current IO position */\r\n    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;\r\n\r\n    if(iocurrent == ioposition)\r\n    {\r\n      /*--------------------- GPIO Mode Configuration ------------------------*/\r\n      /* In case of Alternate function mode selection */\r\n      if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))\r\n      {\r\n        /* Check the Alternate function parameter */\r\n        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));\r\n        \r\n        /* Configure Alternate function mapped with the current IO */\r\n        temp = GPIOx->AFR[position >> 3];\r\n        temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;\r\n        temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));\r\n        GPIOx->AFR[position >> 3] = temp;\r\n      }\r\n\r\n      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */\r\n      temp = GPIOx->MODER;\r\n      temp &= ~(GPIO_MODER_MODER0 << (position * 2));\r\n      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));\r\n      GPIOx->MODER = temp;\r\n\r\n      /* In case of Output or Alternate function mode selection */\r\n      if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||\r\n         (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))\r\n      {\r\n        /* Check the Speed parameter */\r\n        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));\r\n        /* Configure the IO Speed */\r\n        temp = GPIOx->OSPEEDR; \r\n        temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));\r\n        temp |= (GPIO_Init->Speed << (position * 2));\r\n        GPIOx->OSPEEDR = temp;\r\n\r\n        /* Configure the IO Output Type */\r\n        temp = GPIOx->OTYPER;\r\n        temp &= ~(GPIO_OTYPER_OT_0 << position) ;\r\n        temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);\r\n        GPIOx->OTYPER = temp;\r\n      }\r\n\r\n      /* Activate the Pull-up or Pull down resistor for the current IO */\r\n      temp = GPIOx->PUPDR;\r\n      temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));\r\n      temp |= ((GPIO_Init->Pull) << (position * 2));\r\n      GPIOx->PUPDR = temp;\r\n\r\n      /*--------------------- EXTI Mode Configuration ------------------------*/\r\n      /* Configure the External Interrupt or event for the current IO */\r\n      if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)\r\n      {\r\n        /* Enable SYSCFG Clock */\r\n        __HAL_RCC_SYSCFG_CLK_ENABLE();\r\n\r\n        temp = SYSCFG->EXTICR[position >> 2];\r\n        temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));\r\n        temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));\r\n        SYSCFG->EXTICR[position >> 2] = temp;\r\n\r\n        /* Clear EXTI line configuration */\r\n        temp = EXTI->IMR;\r\n        temp &= ~((uint32_t)iocurrent);\r\n        if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)\r\n        {\r\n          temp |= iocurrent;\r\n        }\r\n        EXTI->IMR = temp;\r\n\r\n        temp = EXTI->EMR;\r\n        temp &= ~((uint32_t)iocurrent);\r\n        if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)\r\n        {\r\n          temp |= iocurrent;\r\n        }\r\n        EXTI->EMR = temp;\r\n\r\n        /* Clear Rising Falling edge configuration */\r\n        temp = EXTI->RTSR;\r\n        temp &= ~((uint32_t)iocurrent);\r\n        if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)\r\n        {\r\n          temp |= iocurrent;\r\n        }\r\n        EXTI->RTSR = temp;\r\n\r\n        temp = EXTI->FTSR;\r\n        temp &= ~((uint32_t)iocurrent);\r\n        if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)\r\n        {\r\n          temp |= iocurrent;\r\n        }\r\n        EXTI->FTSR = temp;\r\n      }\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  De-initializes the GPIOx peripheral registers to their default reset values.\r\n  * @param  GPIOx where x can be (A..K) to select the GPIO peripheral.\r\n  * @param  GPIO_Pin specifies the port bit to be written.\r\n  *          This parameter can be one of GPIO_PIN_x where x can be (0..15).\r\n  * @retval None\r\n  */\r\nvoid HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)\r\n{\r\n  uint32_t position;\r\n  uint32_t ioposition = 0x00;\r\n  uint32_t iocurrent = 0x00;\r\n  uint32_t tmp = 0x00;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));\r\n  \r\n  /* Configure the port pins */\r\n  for(position = 0; position < GPIO_NUMBER; position++)\r\n  {\r\n    /* Get the IO position */\r\n    ioposition = ((uint32_t)0x01) << position;\r\n    /* Get the current IO position */\r\n    iocurrent = (GPIO_Pin) & ioposition;\r\n\r\n    if(iocurrent == ioposition)\r\n    {\r\n      /*------------------------- GPIO Mode Configuration --------------------*/\r\n      /* Configure IO Direction in Input Floating Mode */\r\n      GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2));\r\n\r\n      /* Configure the default Alternate Function in current IO */\r\n      GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;\r\n\r\n      /* Configure the default value for IO Speed */\r\n      GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));\r\n\r\n      /* Configure the default value IO Output Type */\r\n      GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT_0 << position) ;\r\n\r\n      /* Deactivate the Pull-up and Pull-down resistor for the current IO */\r\n      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));\r\n\r\n      /*------------------------- EXTI Mode Configuration --------------------*/\r\n      tmp = SYSCFG->EXTICR[position >> 2];\r\n      tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));\r\n      if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))))\r\n      {\r\n        /* Configure the External Interrupt or event for the current IO */\r\n        tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));\r\n        SYSCFG->EXTICR[position >> 2] &= ~tmp;\r\n\r\n        /* Clear EXTI line configuration */\r\n        EXTI->IMR &= ~((uint32_t)iocurrent);\r\n        EXTI->EMR &= ~((uint32_t)iocurrent);\r\n\r\n        /* Clear Rising Falling edge configuration */\r\n        EXTI->RTSR &= ~((uint32_t)iocurrent);\r\n        EXTI->FTSR &= ~((uint32_t)iocurrent);\r\n\t  }\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions \r\n *  @brief   GPIO Read and Write\r\n *\r\n@verbatim\r\n ===============================================================================\r\n                       ##### IO operation functions #####\r\n ===============================================================================\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Reads the specified input port pin.\r\n  * @param  GPIOx where x can be (A..K) to select the GPIO peripheral.\r\n  * @param  GPIO_Pin specifies the port bit to read.\r\n  *         This parameter can be GPIO_PIN_x where x can be (0..15).\r\n  * @retval The input port pin value.\r\n  */\r\nGPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r\n{\r\n  GPIO_PinState bitstatus;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_GPIO_PIN(GPIO_Pin));\r\n\r\n  if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)\r\n  {\r\n    bitstatus = GPIO_PIN_SET;\r\n  }\r\n  else\r\n  {\r\n    bitstatus = GPIO_PIN_RESET;\r\n  }\r\n  return bitstatus;\r\n}\r\n\r\n/**\r\n  * @brief  Sets or clears the selected data port bit.\r\n  *\r\n  * @note   This function uses GPIOx_BSRR register to allow atomic read/modify\r\n  *         accesses. In this way, there is no risk of an IRQ occurring between\r\n  *         the read and the modify access.\r\n  *\r\n  * @param  GPIOx where x can be (A..K) to select the GPIO peripheral.\r\n  * @param  GPIO_Pin specifies the port bit to be written.\r\n  *          This parameter can be one of GPIO_PIN_x where x can be (0..15).\r\n  * @param  PinState specifies the value to be written to the selected bit.\r\n  *          This parameter can be one of the GPIO_PinState enum values:\r\n  *            @arg GPIO_PIN_RESET: to clear the port pin\r\n  *            @arg GPIO_PIN_SET: to set the port pin\r\n  * @retval None\r\n  */\r\nvoid HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_GPIO_PIN(GPIO_Pin));\r\n  assert_param(IS_GPIO_PIN_ACTION(PinState));\r\n\r\n  if(PinState != GPIO_PIN_RESET)\r\n  {\r\n    GPIOx->BSRR = GPIO_Pin;\r\n  }\r\n  else\r\n  {\r\n    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Toggles the specified GPIO pins.\r\n  * @param  GPIOx Where x can be (A..I) to select the GPIO peripheral.\r\n  * @param  GPIO_Pin Specifies the pins to be toggled.\r\n  * @retval None\r\n  */\r\nvoid HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_GPIO_PIN(GPIO_Pin));\r\n\r\n  GPIOx->ODR ^= GPIO_Pin;\r\n}\r\n\r\n/**\r\n  * @brief  Locks GPIO Pins configuration registers.\r\n  * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,\r\n  *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.\r\n  * @note   The configuration of the locked GPIO pins can no longer be modified\r\n  *         until the next reset.\r\n  * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F7 family\r\n  * @param  GPIO_Pin specifies the port bit to be locked.\r\n  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).\r\n  * @retval None\r\n  */\r\nHAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r\n{\r\n  __IO uint32_t tmp = GPIO_LCKR_LCKK;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_GPIO_PIN(GPIO_Pin));\r\n\r\n  /* Apply lock key write sequence */\r\n  tmp |= GPIO_Pin;\r\n  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */\r\n  GPIOx->LCKR = tmp;\r\n  /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */\r\n  GPIOx->LCKR = GPIO_Pin;\r\n  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */\r\n  GPIOx->LCKR = tmp;\r\n  /* Read LCKK bit*/\r\n  tmp = GPIOx->LCKR;\r\n\r\n if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)\r\n  {\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  This function handles EXTI interrupt request.\r\n  * @param  GPIO_Pin Specifies the pins connected EXTI line\r\n  * @retval None\r\n  */\r\nvoid HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)\r\n{\r\n  /* EXTI line interrupt detected */\r\n  if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)\r\n  {\r\n    __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);\r\n    HAL_GPIO_EXTI_Callback(GPIO_Pin);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  EXTI line detection callbacks.\r\n  * @param  GPIO_Pin Specifies the pins connected EXTI line\r\n  * @retval None\r\n  */\r\n__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(GPIO_Pin);\r\n  \r\n  /* NOTE: This function Should not be modified, when the callback is needed,\r\n           the HAL_GPIO_EXTI_Callback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_GPIO_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_hash.c\r\n  * @author  MCD Application Team\r\n  * @brief   HASH HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the HASH peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + HASH/HMAC Processing functions by algorithm using polling mode\r\n  *           + HASH/HMAC functions by algorithm using interrupt mode\r\n  *           + HASH/HMAC functions by algorithm using DMA mode\r\n  *           + Peripheral State functions\r\n  *         \r\n  @verbatim\r\n  ==============================================================================\r\n                     ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]\r\n    The HASH HAL driver can be used as follows:\r\n    (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():\r\n        (##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE()\r\n        (##) In case of using processing APIs based on interrupts (e.g. HAL_HMAC_SHA1_Start_IT())\r\n            (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()\r\n            (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()\r\n            (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler()\r\n        (##) In case of using DMA to control data transfer (e.g. HAL_HMAC_SHA1_Start_DMA())\r\n            (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()\r\n            (+++) Configure and enable one DMA stream one for managing data transfer from\r\n                memory to peripheral (input stream). Managing data transfer from\r\n                peripheral to memory can be performed only using CPU\r\n            (+++) Associate the initialized DMA handle to the HASH DMA handle\r\n                using  __HAL_LINKDMA()\r\n            (+++) Configure the priority and enable the NVIC for the transfer complete\r\n                interrupt on the DMA Stream using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()\r\n    (#)Initialize the HASH HAL using HAL_HASH_Init(). This function configures mainly:\r\n        (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit.\r\n        (##) For HMAC, the encryption key.\r\n        (##) For HMAC, the key size used for encryption.\r\n    (#)Three processing functions are available:\r\n        (##) Polling mode: processing APIs are blocking functions\r\n             i.e. they process the data and wait till the digest computation is finished\r\n             e.g. HAL_HASH_SHA1_Start()\r\n        (##) Interrupt mode: encryption and decryption APIs are not blocking functions\r\n                i.e. they process the data under interrupt\r\n                e.g. HAL_HASH_SHA1_Start_IT()\r\n        (##) DMA mode: processing APIs are not blocking functions and the CPU is\r\n             not used for data transfer i.e. the data transfer is ensured by DMA\r\n                e.g. HAL_HASH_SHA1_Start_DMA()\r\n    (#)When the processing function is called at first time after HAL_HASH_Init()\r\n       the HASH peripheral is initialized and processes the buffer in input.\r\n       After that, the digest computation is started.\r\n       When processing multi-buffer use the accumulate function to write the\r\n       data in the peripheral without starting the digest computation. In last \r\n       buffer use the start function to input the last buffer ans start the digest\r\n       computation.\r\n       (##) e.g. HAL_HASH_SHA1_Accumulate() : write 1st data buffer in the peripheral without starting the digest computation\r\n       (##) write (n-1)th data buffer in the peripheral without starting the digest computation\r\n       (##) HAL_HASH_SHA1_Start() : write (n)th data buffer in the peripheral and start the digest computation\r\n    (#)In HMAC mode, there is no Accumulate API. Only Start API is available.\r\n    (#)In case of using DMA, call the DMA start processing e.g. HAL_HASH_SHA1_Start_DMA().\r\n       After that, call the finish function in order to get the digest value\r\n       e.g. HAL_HASH_SHA1_Finish()\r\n    (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r\n\r\n/** @defgroup HASH HASH\r\n  * @brief HASH HAL module driver.\r\n  * @{\r\n  */\r\n#ifdef HAL_HASH_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/** @defgroup HASH_Private_Functions HASH Private Functions\r\n  * @{\r\n  */\r\nstatic void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma);\r\nstatic void HASH_DMAError(DMA_HandleTypeDef *hdma);\r\nstatic void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size);\r\nstatic void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size);\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Private functions ---------------------------------------------------------*/\r\n/** @addtogroup HASH_Private_Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  DMA HASH Input Data complete callback. \r\n  * @param  hdma DMA handle\r\n  * @retval None\r\n  */\r\nstatic void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  uint32_t inputaddr = 0;\r\n  uint32_t buffersize = 0;\r\n  \r\n  if((HASH->CR & HASH_CR_MODE) != HASH_CR_MODE)\r\n  {\r\n    /* Disable the DMA transfer */\r\n    HASH->CR &= (uint32_t)(~HASH_CR_DMAE);\r\n    \r\n    /* Change HASH peripheral state */\r\n    hhash->State = HAL_HASH_STATE_READY;\r\n    \r\n    /* Call Input data transfer complete callback */\r\n    HAL_HASH_InCpltCallback(hhash);\r\n  }\r\n  else\r\n  {\r\n    /* Increment Interrupt counter */\r\n    hhash->HashInCount++;\r\n    /* Disable the DMA transfer before starting the next transfer */\r\n    HASH->CR &= (uint32_t)(~HASH_CR_DMAE);\r\n    \r\n    if(hhash->HashInCount <= 2)\r\n    {\r\n      /* In case HashInCount = 1, set the DMA to transfer data to HASH DIN register */\r\n      if(hhash->HashInCount == 1)\r\n      {\r\n        inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r\n        buffersize = hhash->HashBuffSize;\r\n      }\r\n      /* In case HashInCount = 2, set the DMA to transfer key to HASH DIN register */\r\n      else if(hhash->HashInCount == 2)\r\n      {\r\n        inputaddr = (uint32_t)hhash->Init.pKey;\r\n        buffersize = hhash->Init.KeySize;\r\n      }\r\n      /* Configure the number of valid bits in last word of the message */\r\n      MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * (buffersize % 4));\r\n      \r\n      /* Set the HASH DMA transfer complete */\r\n      hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;\r\n      \r\n      /* Enable the DMA In DMA Stream */\r\n      HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4 ? (buffersize+3)/4:buffersize/4));\r\n      \r\n      /* Enable DMA requests */\r\n      HASH->CR |= (HASH_CR_DMAE);\r\n    }\r\n    else\r\n    {\r\n      /* Disable the DMA transfer */\r\n      HASH->CR &= (uint32_t)(~HASH_CR_DMAE);\r\n      \r\n      /* Reset the InCount */\r\n      hhash->HashInCount = 0;\r\n      \r\n      /* Change HASH peripheral state */\r\n      hhash->State = HAL_HASH_STATE_READY;\r\n      \r\n      /* Call Input data transfer complete callback */\r\n      HAL_HASH_InCpltCallback(hhash);\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  DMA HASH communication error callback. \r\n  * @param  hdma DMA handle\r\n  * @retval None\r\n  */\r\nstatic void HASH_DMAError(DMA_HandleTypeDef *hdma)\r\n{\r\n  HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  hhash->State= HAL_HASH_STATE_READY;\r\n  HAL_HASH_ErrorCallback(hhash);\r\n}\r\n\r\n/**\r\n  * @brief  Writes the input buffer in data register.\r\n  * @param  pInBuffer Pointer to input buffer\r\n  * @param  Size The size of input buffer\r\n  * @retval None\r\n  */\r\nstatic void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size)\r\n{\r\n  uint32_t buffercounter;\r\n  uint32_t inputaddr = (uint32_t) pInBuffer;\r\n  \r\n  for(buffercounter = 0; buffercounter < Size; buffercounter+=4)\r\n  {\r\n    HASH->DIN = *(uint32_t*)inputaddr;\r\n    inputaddr+=4;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Provides the message digest result.\r\n  * @param  pMsgDigest Pointer to the message digest\r\n  * @param  Size The size of the message digest in bytes\r\n  * @retval None\r\n  */\r\nstatic void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)\r\n{\r\n  uint32_t msgdigest = (uint32_t)pMsgDigest;\r\n  \r\n  switch(Size)\r\n  {\r\n  case 16:\r\n    /* Read the message digest */\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);\r\n    break;\r\n  case 20:\r\n    /* Read the message digest */\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);\r\n    break;\r\n  case 28:\r\n    /* Read the message digest */\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);\r\n    break;\r\n  case 32:\r\n    /* Read the message digest */\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7]);\r\n    break;\r\n  default:\r\n    break;\r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup HASH_Exported_Functions\r\n  * @{\r\n  */\r\n  \r\n\r\n/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions \r\n *  @brief    Initialization and Configuration functions. \r\n *\r\n@verbatim    \r\n ===============================================================================\r\n              ##### Initialization and de-initialization functions #####\r\n ===============================================================================\r\n    [..]  This section provides functions allowing to:\r\n      (+) Initialize the HASH according to the specified parameters \r\n          in the HASH_InitTypeDef and creates the associated handle.\r\n      (+) DeInitialize the HASH peripheral.\r\n      (+) Initialize the HASH MSP.\r\n      (+) DeInitialize HASH MSP. \r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the HASH according to the specified parameters in the\r\n            HASH_HandleTypeDef and creates the associated handle.\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)\r\n{\r\n  /* Check the hash handle allocation */\r\n  if(hhash == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_HASH_DATATYPE(hhash->Init.DataType));\r\n   \r\n  if(hhash->State == HAL_HASH_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    hhash->Lock = HAL_UNLOCKED;\r\n    /* Init the low level hardware */\r\n    HAL_HASH_MspInit(hhash);\r\n  }\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Reset HashInCount, HashBuffSize and HashITCounter */\r\n  hhash->HashInCount = 0;\r\n  hhash->HashBuffSize = 0;\r\n  hhash->HashITCounter = 0;\r\n  \r\n  /* Set the data type */\r\n  HASH->CR |= (uint32_t) (hhash->Init.DataType);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_READY;\r\n  \r\n  /* Set the default HASH phase */\r\n  hhash->Phase = HAL_HASH_PHASE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the HASH peripheral.\r\n  * @note   This API must be called before starting a new processing. \r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)\r\n{ \r\n  /* Check the HASH handle allocation */\r\n  if(hhash == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Set the default HASH phase */\r\n  hhash->Phase = HAL_HASH_PHASE_READY;\r\n  \r\n  /* Reset HashInCount, HashBuffSize and HashITCounter */\r\n  hhash->HashInCount = 0;\r\n  hhash->HashBuffSize = 0;\r\n  hhash->HashITCounter = 0;\r\n  \r\n  /* DeInit the low level hardware */\r\n  HAL_HASH_MspDeInit(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_RESET;  \r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hhash);\r\n\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the HASH MSP.\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @retval None\r\n  */\r\n__weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hhash);\r\n  \r\n  /* NOTE: This function Should not be modified, when the callback is needed,\r\n           the HAL_HASH_MspInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes HASH MSP.\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @retval None\r\n  */\r\n__weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hhash);\r\n  \r\n  /* NOTE: This function Should not be modified, when the callback is needed,\r\n           the HAL_HASH_MspDeInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Input data transfer complete callback.\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @retval None\r\n  */\r\n __weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hhash);\r\n  \r\n  /* NOTE: This function Should not be modified, when the callback is needed,\r\n           the HAL_HASH_InCpltCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  Data transfer Error callback.\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @retval None\r\n  */\r\n __weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hhash);\r\n  \r\n  /* NOTE: This function Should not be modified, when the callback is needed,\r\n           the HAL_HASH_ErrorCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  Digest computation complete callback. It is used only with interrupt.\r\n  * @note   This callback is not relevant with DMA.\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @retval None\r\n  */\r\n __weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hhash);\r\n  \r\n  /* NOTE: This function Should not be modified, when the callback is needed,\r\n           the HAL_HASH_DgstCpltCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HASH_Exported_Functions_Group2 HASH processing functions using polling mode \r\n *  @brief   processing functions using polling mode \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n              ##### HASH processing using polling mode functions#####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to calculate in polling mode\r\n          the hash value using one of the following algorithms:\r\n      (+) MD5\r\n      (+) SHA1\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in MD5 mode then processes pInBuffer.\r\n            The digest is available in pOutBuffer.\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer Pointer to the input buffer (buffer to be hashed).\r\n  * @param  Size Length of the input buffer in bytes.\r\n  *          If the Size is multiple of 64 bytes, appending the input buffer is possible.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware\r\n  *          and appending the input buffer is no more possible.\r\n  * @param  pOutBuffer Pointer to the computed digest. Its size must be 16 bytes.\r\n  * @param  Timeout Timeout value\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute \r\n       the message digest of a new message */\r\n    HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;\r\n  }\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n  \r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(Size);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASH_WriteData(pInBuffer, Size);\r\n  \r\n  /* Start the digest calculation */\r\n  __HAL_HASH_START_DIGEST();\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Read the message digest */\r\n  HASH_GetDigest(pOutBuffer, 16);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_READY;\r\n   \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in MD5 mode then writes the pInBuffer.\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer Pointer to the input buffer (buffer to be hashed).\r\n  * @param  Size Length of the input buffer in bytes.\r\n  *          If the Size is multiple of 64 bytes, appending the input buffer is possible.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware\r\n  *          and appending the input buffer is no more possible.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r\n{  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute \r\n       the message digest of a new message */\r\n    HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;\r\n  }\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n  \r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(Size);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASH_WriteData(pInBuffer, Size);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.\r\n            The digest is available in pOutBuffer.\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer Pointer to the input buffer (buffer to be hashed).  \r\n  * @param  Size Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @param  pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.\r\n  * @param  Timeout Timeout value  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n\r\n  /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute \r\n       the message digest of a new message */\r\n    HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT;\r\n  }\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n  \r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(Size);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASH_WriteData(pInBuffer, Size);\r\n  \r\n  /* Start the digest calculation */\r\n  __HAL_HASH_START_DIGEST();\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))\r\n    {\r\n      /* Check for the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n        {\r\n          /* Change state */\r\n          hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hhash);\r\n          \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n  \r\n  /* Read the message digest */\r\n  HASH_GetDigest(pOutBuffer, 20);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer Pointer to the input buffer (buffer to be hashed).\r\n  * @param  Size Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @note  Input buffer size in bytes must be a multiple of 4 otherwise the digest computation is corrupted.  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_HASH_SHA1_BUFFER_SIZE(Size));\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute \r\n       the message digest of a new message */\r\n    HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT;\r\n  }\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n  \r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(Size);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASH_WriteData(pInBuffer, Size);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HASH_Exported_Functions_Group3 HASH processing functions using interrupt mode\r\n *  @brief   processing functions using interrupt mode. \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n              ##### HASH processing using interrupt mode functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to calculate in interrupt mode\r\n          the hash value using one of the following algorithms:\r\n      (+) MD5\r\n      (+) SHA1\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in MD5 mode then processes pInBuffer.\r\n  *         The digest is available in pOutBuffer.\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer Pointer to the input buffer (buffer to be hashed).   \r\n  * @param  Size Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @param  pOutBuffer Pointer to the computed digest. Its size must be 16 bytes.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  uint32_t buffercounter;\r\n  uint32_t inputcounter;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n\r\n  if(hhash->State == HAL_HASH_STATE_READY)\r\n  {\r\n    /* Change the HASH state */\r\n    hhash->State = HAL_HASH_STATE_BUSY;\r\n    \r\n    hhash->HashInCount = Size;\r\n    hhash->pHashInBuffPtr = pInBuffer;\r\n    hhash->pHashOutBuffPtr = pOutBuffer;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n    {\r\n      /* Select the SHA1 mode */\r\n      HASH->CR |= HASH_ALGOSELECTION_MD5;\r\n      /* Reset the HASH processor core, so that the HASH will be ready to compute \r\n         the message digest of a new message */\r\n      HASH->CR |= HASH_CR_INIT;\r\n    }\r\n    \r\n    /* Reset interrupt counter */\r\n    hhash->HashITCounter = 0;\r\n    \r\n    /* Set the phase */\r\n    hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hhash);\r\n    \r\n    /* Enable Interrupts */\r\n    HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))\r\n  {\r\n    outputaddr = (uint32_t)hhash->pHashOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = __REV(HASH->HR[0]);\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = __REV(HASH->HR[1]);\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = __REV(HASH->HR[2]);\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = __REV(HASH->HR[3]);\r\n    \r\n    if(hhash->HashInCount == 0)\r\n    {\r\n      /* Disable Interrupts */\r\n      HASH->IMR = 0;\r\n      /* Change the HASH state */\r\n      hhash->State = HAL_HASH_STATE_READY;\r\n      /* Call digest computation complete callback */\r\n      HAL_HASH_DgstCpltCallback(hhash);\r\n      \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hhash);\r\n      \r\n      /* Return function status */\r\n      return HAL_OK;\r\n    }\r\n  }\r\n  \r\n  if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))\r\n  {\r\n    if(hhash->HashInCount >= 68)\r\n    {\r\n      inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r\n      /* Write the Input block in the Data IN register */\r\n      for(buffercounter = 0; buffercounter < 64; buffercounter+=4)\r\n      {\r\n        HASH->DIN = *(uint32_t*)inputaddr;\r\n        inputaddr+=4;\r\n      }\r\n      if(hhash->HashITCounter == 0)\r\n      {\r\n        HASH->DIN = *(uint32_t*)inputaddr;\r\n\r\n        if(hhash->HashInCount >= 68)\r\n        {\r\n          /* Decrement buffer counter */\r\n          hhash->HashInCount -= 68;\r\n          hhash->pHashInBuffPtr+= 68;\r\n        }\r\n        else\r\n        {\r\n          hhash->HashInCount = 0;\r\n          hhash->pHashInBuffPtr+= hhash->HashInCount;\r\n        }\r\n        /* Set Interrupt counter */\r\n        hhash->HashITCounter = 1;\r\n      }\r\n      else\r\n      {\r\n        /* Decrement buffer counter */\r\n        hhash->HashInCount -= 64;\r\n        hhash->pHashInBuffPtr+= 64;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* Get the buffer address */\r\n      inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r\n      /* Get the buffer counter */\r\n      inputcounter = hhash->HashInCount;\r\n      /* Disable Interrupts */\r\n      HASH->IMR &= ~(HASH_IT_DINI);\r\n      /* Configure the number of valid bits in last word of the message */\r\n      __HAL_HASH_SET_NBVALIDBITS(inputcounter);\r\n      \r\n      if((inputcounter > 4) && (inputcounter%4))\r\n      {\r\n        inputcounter = (inputcounter+4-inputcounter%4);\r\n      }\r\n      else if ((inputcounter < 4) && (inputcounter != 0))\r\n      {\r\n        inputcounter = 4;\r\n      }\r\n      \r\n      /* Write the Input block in the Data IN register */\r\n      for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)\r\n      {\r\n        HASH->DIN = *(uint32_t*)inputaddr;\r\n        inputaddr+=4;\r\n      }\r\n      /* Start the digest calculation */\r\n      __HAL_HASH_START_DIGEST();\r\n      /* Reset buffer counter */\r\n      hhash->HashInCount = 0;\r\n      /* Call Input data transfer complete callback */\r\n      HAL_HASH_InCpltCallback(hhash);\r\n    }\r\n  }\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.\r\n  *         The digest is available in pOutBuffer.\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer Pointer to the input buffer (buffer to be hashed). \r\n  * @param  Size Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @param  pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  uint32_t buffercounter;\r\n  uint32_t inputcounter;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  if(hhash->State == HAL_HASH_STATE_READY)\r\n  {\r\n    /* Change the HASH state */\r\n    hhash->State = HAL_HASH_STATE_BUSY;\r\n    \r\n    hhash->HashInCount = Size;\r\n    hhash->pHashInBuffPtr = pInBuffer;\r\n    hhash->pHashOutBuffPtr = pOutBuffer;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n    {\r\n      /* Select the SHA1 mode */\r\n      HASH->CR |= HASH_ALGOSELECTION_SHA1;\r\n      /* Reset the HASH processor core, so that the HASH will be ready to compute \r\n         the message digest of a new message */\r\n      HASH->CR |= HASH_CR_INIT;\r\n    }\r\n    \r\n    /* Reset interrupt counter */\r\n    hhash->HashITCounter = 0;\r\n    \r\n    /* Set the phase */\r\n    hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hhash);\r\n    \r\n    /* Enable Interrupts */\r\n    HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))\r\n  {\r\n    outputaddr = (uint32_t)hhash->pHashOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = __REV(HASH->HR[0]);\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = __REV(HASH->HR[1]);\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = __REV(HASH->HR[2]);\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = __REV(HASH->HR[3]);\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = __REV(HASH->HR[4]);\r\n    if(hhash->HashInCount == 0)\r\n    {\r\n      /* Disable Interrupts */\r\n      HASH->IMR = 0;\r\n      /* Change the HASH state */\r\n      hhash->State = HAL_HASH_STATE_READY;\r\n      /* Call digest computation complete callback */\r\n      HAL_HASH_DgstCpltCallback(hhash);\r\n            \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hhash);\r\n      \r\n      /* Return function status */\r\n      return HAL_OK;\r\n    }\r\n  }\r\n  if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))\r\n  {\r\n    if(hhash->HashInCount >= 68)\r\n    {\r\n      inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r\n      /* Write the Input block in the Data IN register */\r\n      for(buffercounter = 0; buffercounter < 64; buffercounter+=4)\r\n      {\r\n        HASH->DIN = *(uint32_t*)inputaddr;\r\n        inputaddr+=4;\r\n      }\r\n      if(hhash->HashITCounter == 0)\r\n      {\r\n        HASH->DIN = *(uint32_t*)inputaddr;\r\n      \r\n        if(hhash->HashInCount >= 68)\r\n        {\r\n          /* Decrement buffer counter */\r\n          hhash->HashInCount -= 68;\r\n          hhash->pHashInBuffPtr+= 68;\r\n        }\r\n        else\r\n        {\r\n          hhash->HashInCount = 0;\r\n          hhash->pHashInBuffPtr+= hhash->HashInCount;\r\n        }\r\n        /* Set Interrupt counter */\r\n        hhash->HashITCounter = 1;\r\n      }\r\n      else\r\n      {\r\n        /* Decrement buffer counter */\r\n        hhash->HashInCount -= 64;\r\n        hhash->pHashInBuffPtr+= 64;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* Get the buffer address */\r\n      inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r\n      /* Get the buffer counter */\r\n      inputcounter = hhash->HashInCount;\r\n      /* Disable Interrupts */\r\n      HASH->IMR &= ~(HASH_IT_DINI);\r\n      /* Configure the number of valid bits in last word of the message */\r\n      __HAL_HASH_SET_NBVALIDBITS(inputcounter);\r\n      \r\n      if((inputcounter > 4) && (inputcounter%4))\r\n      {\r\n        inputcounter = (inputcounter+4-inputcounter%4);\r\n      }\r\n      else if ((inputcounter < 4) && (inputcounter != 0))\r\n      {\r\n        inputcounter = 4;\r\n      }\r\n      /* Write the Input block in the Data IN register */\r\n      for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)\r\n      {\r\n        HASH->DIN = *(uint32_t*)inputaddr;\r\n        inputaddr+=4;\r\n      }\r\n      /* Start the digest calculation */\r\n      __HAL_HASH_START_DIGEST();\r\n      /* Reset buffer counter */\r\n      hhash->HashInCount = 0;\r\n      /* Call Input data transfer complete callback */\r\n      HAL_HASH_InCpltCallback(hhash);\r\n    }\r\n  }\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief This function handles HASH interrupt request.\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @retval None\r\n  */\r\nvoid HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)\r\n{\r\n  switch(HASH->CR & HASH_CR_ALGO)\r\n  {\r\n    case HASH_ALGOSELECTION_MD5:\r\n       HAL_HASH_MD5_Start_IT(hhash, NULL, 0, NULL);\r\n    break;\r\n    \r\n    case HASH_ALGOSELECTION_SHA1:\r\n      HAL_HASH_SHA1_Start_IT(hhash, NULL, 0, NULL);\r\n    break;\r\n    \r\n    default:\r\n    break;\r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HASH_Exported_Functions_Group4 HASH processing functions using DMA mode\r\n *  @brief   processing functions using DMA mode. \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n              ##### HASH processing using DMA mode functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to calculate in DMA mode\r\n          the hash value using one of the following algorithms:\r\n      (+) MD5\r\n      (+) SHA1\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in MD5 mode then enables DMA to\r\n            control data transfer. Use HAL_HASH_MD5_Finish() to get the digest.\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer Pointer to the input buffer (buffer to be hashed).\r\n  * @param  Size Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r\n{\r\n  uint32_t inputaddr  = (uint32_t)pInBuffer;\r\n  \r\n   /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute \r\n       the message digest of a new message */\r\n    HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;\r\n  }\r\n   \r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(Size);\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n    \r\n  /* Set the HASH DMA transfer complete callback */\r\n  hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;\r\n  /* Set the DMA error callback */\r\n  hhash->hdmain->XferErrorCallback = HASH_DMAError;\r\n  \r\n  /* Enable the DMA In DMA Stream */\r\n  HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));\r\n  \r\n  /* Enable DMA requests */\r\n  HASH->CR |= (HASH_CR_DMAE);\r\n  \r\n   /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the computed digest in MD5 mode\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pOutBuffer Pointer to the computed digest. Its size must be 16 bytes.\r\n  * @param  Timeout Timeout value  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  \r\n   /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change HASH peripheral state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Read the message digest */\r\n  HASH_GetDigest(pOutBuffer, 16);\r\n      \r\n  /* Change HASH peripheral state */\r\n  hhash->State = HAL_HASH_STATE_READY;\r\n  \r\n   /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in SHA1 mode then enables DMA to\r\n            control data transfer. Use HAL_HASH_SHA1_Finish() to get the digest.\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer Pointer to the input buffer (buffer to be hashed).\r\n  * @param  Size Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r\n{\r\n  uint32_t inputaddr  = (uint32_t)pInBuffer;\r\n  \r\n   /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute \r\n       the message digest of a new message */\r\n    HASH->CR |= HASH_ALGOSELECTION_SHA1;\r\n    HASH->CR |= HASH_CR_INIT;\r\n  }\r\n  \r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(Size);\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n  \r\n  /* Set the HASH DMA transfer complete callback */\r\n  hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;\r\n  /* Set the DMA error callback */\r\n  hhash->hdmain->XferErrorCallback = HASH_DMAError;\r\n  \r\n  /* Enable the DMA In DMA Stream */\r\n  HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));\r\n  \r\n  /* Enable DMA requests */\r\n  HASH->CR |= (HASH_CR_DMAE);\r\n  \r\n   /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the computed digest in SHA1 mode.\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.  \r\n  * @param  Timeout Timeout value    \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  \r\n   /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change HASH peripheral state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Read the message digest */\r\n  HASH_GetDigest(pOutBuffer, 20);\r\n  \r\n  /* Change HASH peripheral state */\r\n  hhash->State = HAL_HASH_STATE_READY;\r\n  \r\n   /* Process UnLock */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HASH_Exported_Functions_Group5 HASH-MAC (HMAC) processing functions using polling mode \r\n *  @brief   HMAC processing functions using polling mode . \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n              ##### HMAC processing using polling mode functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to calculate in polling mode\r\n          the HMAC value using one of the following algorithms:\r\n      (+) MD5\r\n      (+) SHA1\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in HMAC MD5 mode\r\n  *         then processes pInBuffer. The digest is available in pOutBuffer\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer Pointer to the input buffer (buffer to be hashed).\r\n  * @param  Size Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @param  pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.\r\n  * @param  Timeout Timeout value  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  \r\n   /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Check if key size is greater than 64 bytes */\r\n    if(hhash->Init.KeySize > 64)\r\n    {\r\n      /* Select the HMAC MD5 mode */\r\n      HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);\r\n    }\r\n    else\r\n    {\r\n      /* Select the HMAC MD5 mode */\r\n      HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);\r\n    }\r\n  }\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n  \r\n  /************************** STEP 1 ******************************************/\r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);\r\n  \r\n  /* Start the digest calculation */\r\n  __HAL_HASH_START_DIGEST();\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  /************************** STEP 2 ******************************************/\r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(Size);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASH_WriteData(pInBuffer, Size);\r\n  \r\n  /* Start the digest calculation */\r\n  __HAL_HASH_START_DIGEST();\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > Timeout)\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  /************************** STEP 3 ******************************************/\r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);\r\n  \r\n  /* Start the digest calculation */\r\n  __HAL_HASH_START_DIGEST();\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > Timeout)\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Read the message digest */\r\n  HASH_GetDigest(pOutBuffer, 16);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in HMAC SHA1 mode\r\n  *         then processes pInBuffer. The digest is available in pOutBuffer.\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer Pointer to the input buffer (buffer to be hashed).\r\n  * @param   Size Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @param  pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.\r\n  * @param  Timeout Timeout value  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Check if key size is greater than 64 bytes */\r\n    if(hhash->Init.KeySize > 64)\r\n    {\r\n      /* Select the HMAC SHA1 mode */\r\n      HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);\r\n    }\r\n    else\r\n    {\r\n      /* Select the HMAC SHA1 mode */\r\n      HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);\r\n    }\r\n  }\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n  \r\n  /************************** STEP 1 ******************************************/\r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);\r\n  \r\n  /* Start the digest calculation */\r\n  __HAL_HASH_START_DIGEST();\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  /************************** STEP 2 ******************************************/\r\n  /* Configure the number of valid bits in last word of the message */  \r\n  __HAL_HASH_SET_NBVALIDBITS(Size);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASH_WriteData(pInBuffer, Size);\r\n  \r\n  /* Start the digest calculation */\r\n  __HAL_HASH_START_DIGEST();\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > Timeout)\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  /************************** STEP 3 ******************************************/\r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);\r\n  \r\n  /* Start the digest calculation */\r\n  __HAL_HASH_START_DIGEST();\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > Timeout)\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  /* Read the message digest */\r\n  HASH_GetDigest(pOutBuffer, 20);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HASH_Exported_Functions_Group6 HASH-MAC (HMAC) processing functions using DMA mode \r\n *  @brief   HMAC processing functions using DMA mode . \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                ##### HMAC processing using DMA mode functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to calculate in DMA mode\r\n          the HMAC value using one of the following algorithms:\r\n      (+) MD5\r\n      (+) SHA1\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in HMAC MD5 mode\r\n  *         then enables DMA to control data transfer.\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer Pointer to the input buffer (buffer to be hashed).\r\n  * @param  Size Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r\n{\r\n  uint32_t inputaddr  = 0;\r\n  \r\n   /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Save buffer pointer and size in handle */\r\n  hhash->pHashInBuffPtr = pInBuffer;\r\n  hhash->HashBuffSize = Size;\r\n  hhash->HashInCount = 0;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Check if key size is greater than 64 bytes */\r\n    if(hhash->Init.KeySize > 64)\r\n    {\r\n      /* Select the HMAC MD5 mode */\r\n      HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);\r\n    }\r\n    else\r\n    {\r\n      /* Select the HMAC MD5 mode */\r\n      HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);\r\n    }\r\n  }\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n  \r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r\n  \r\n  /* Get the key address */\r\n  inputaddr = (uint32_t)(hhash->Init.pKey);\r\n  \r\n  /* Set the HASH DMA transfer complete callback */\r\n  hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;\r\n  /* Set the DMA error callback */\r\n  hhash->hdmain->XferErrorCallback = HASH_DMAError;\r\n  \r\n  /* Enable the DMA In DMA Stream */\r\n  HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));\r\n  /* Enable DMA requests */\r\n  HASH->CR |= (HASH_CR_DMAE);\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in HMAC SHA1 mode\r\n  *         then enables DMA to control data transfer.\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer Pointer to the input buffer (buffer to be hashed).\r\n  * @param  Size Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r\n{\r\n  uint32_t inputaddr  = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Save buffer pointer and size in handle */\r\n  hhash->pHashInBuffPtr = pInBuffer;\r\n  hhash->HashBuffSize = Size;\r\n  hhash->HashInCount = 0;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Check if key size is greater than 64 bytes */\r\n    if(hhash->Init.KeySize > 64)\r\n    {\r\n      /* Select the HMAC SHA1 mode */\r\n      HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);\r\n    }\r\n    else\r\n    {\r\n      /* Select the HMAC SHA1 mode */\r\n      HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);\r\n    }\r\n  }\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n  \r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r\n  \r\n  /* Get the key address */\r\n  inputaddr = (uint32_t)(hhash->Init.pKey);\r\n  \r\n  /* Set the HASH DMA transfer complete callback */\r\n  hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;\r\n  /* Set the DMA error callback */\r\n  hhash->hdmain->XferErrorCallback = HASH_DMAError;\r\n  \r\n  /* Enable the DMA In DMA Stream */\r\n  HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));\r\n  /* Enable DMA requests */\r\n  HASH->CR |= (HASH_CR_DMAE);\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HASH_Exported_Functions_Group7 Peripheral State functions \r\n *  @brief   Peripheral State functions. \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                      ##### Peripheral State functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection permits to get in run-time the status of the peripheral.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief return the HASH state\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @retval HAL state\r\n  */\r\nHAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)\r\n{\r\n  return hhash->State;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_HASH_MODULE_ENABLED */\r\n\r\n/**\r\n  * @}\r\n  */\r\n#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash_ex.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_hash_ex.c\r\n  * @author  MCD Application Team\r\n  * @brief   HASH HAL Extension module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of HASH peripheral:\r\n  *           + Extended HASH processing functions based on SHA224 Algorithm\r\n  *           + Extended HASH processing functions based on SHA256 Algorithm\r\n  *         \r\n  @verbatim\r\n  ==============================================================================\r\n                     ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]\r\n    The HASH HAL driver can be used as follows:\r\n    (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():\r\n        (##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE()\r\n        (##) In case of using processing APIs based on interrupts (e.g. HAL_HMACEx_SHA224_Start())\r\n            (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()\r\n            (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()\r\n            (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler()\r\n        (##) In case of using DMA to control data transfer (e.g. HAL_HMACEx_SH224_Start_DMA())\r\n            (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()\r\n            (+++) Configure and enable one DMA stream one for managing data transfer from\r\n                memory to peripheral (input stream). Managing data transfer from\r\n                peripheral to memory can be performed only using CPU\r\n            (+++) Associate the initialized DMA handle to the HASH DMA handle\r\n                using  __HAL_LINKDMA()\r\n            (+++) Configure the priority and enable the NVIC for the transfer complete\r\n                interrupt on the DMA Stream: HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()\r\n    (#)Initialize the HASH HAL using HAL_HASH_Init(). This function configures mainly:\r\n        (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit.\r\n        (##) For HMAC, the encryption key.\r\n        (##) For HMAC, the key size used for encryption.\r\n    (#)Three processing functions are available:\r\n        (##) Polling mode: processing APIs are blocking functions\r\n             i.e. they process the data and wait till the digest computation is finished\r\n             e.g. HAL_HASHEx_SHA224_Start()\r\n        (##) Interrupt mode: encryption and decryption APIs are not blocking functions\r\n                i.e. they process the data under interrupt\r\n                e.g. HAL_HASHEx_SHA224_Start_IT()\r\n        (##) DMA mode: processing APIs are not blocking functions and the CPU is\r\n             not used for data transfer i.e. the data transfer is ensured by DMA\r\n                e.g. HAL_HASHEx_SHA224_Start_DMA()\r\n    (#)When the processing function is called at first time after HAL_HASH_Init()\r\n       the HASH peripheral is initialized and processes the buffer in input.\r\n       After that, the digest computation is started.\r\n       When processing multi-buffer use the accumulate function to write the\r\n       data in the peripheral without starting the digest computation. In last \r\n       buffer use the start function to input the last buffer ans start the digest\r\n       computation.\r\n       (##) e.g. HAL_HASHEx_SHA224_Accumulate() : write 1st data buffer in the peripheral without starting the digest computation\r\n       (##)  write (n-1)th data buffer in the peripheral without starting the digest computation\r\n       (##)  HAL_HASHEx_SHA224_Start() : write (n)th data buffer in the peripheral and start the digest computation\r\n    (#)In HMAC mode, there is no Accumulate API. Only Start API is available.\r\n    (#)In case of using DMA, call the DMA start processing e.g. HAL_HASHEx_SHA224_Start_DMA().\r\n       After that, call the finish function in order to get the digest value\r\n       e.g. HAL_HASHEx_SHA224_Finish()\r\n    (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n#if defined(STM32F756xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined (STM32F750xx)\r\n\r\n/** @defgroup HASHEx HASHEx\r\n  * @brief HASH Extension HAL module driver.\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_HASH_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/** @addtogroup HASHEx_Private_Functions\r\n  * @{\r\n  */\r\nstatic void HASHEx_DMAXferCplt(DMA_HandleTypeDef *hdma);\r\nstatic void HASHEx_WriteData(uint8_t *pInBuffer, uint32_t Size);\r\nstatic void HASHEx_GetDigest(uint8_t *pMsgDigest, uint8_t Size);\r\nstatic void HASHEx_DMAError(DMA_HandleTypeDef *hdma);\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @addtogroup HASHEx_Private_Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Writes the input buffer in data register.\r\n  * @param  pInBuffer Pointer to input buffer\r\n  * @param  Size The size of input buffer\r\n  * @retval None\r\n  */\r\nstatic void HASHEx_WriteData(uint8_t *pInBuffer, uint32_t Size)\r\n{\r\n  uint32_t buffercounter;\r\n  uint32_t inputaddr = (uint32_t) pInBuffer;\r\n  \r\n  for(buffercounter = 0; buffercounter < Size; buffercounter+=4)\r\n  {\r\n    HASH->DIN = *(uint32_t*)inputaddr;\r\n    inputaddr+=4;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Provides the message digest result.\r\n  * @param  pMsgDigest Pointer to the message digest\r\n  * @param  Size The size of the message digest in bytes\r\n  * @retval None\r\n  */\r\nstatic void HASHEx_GetDigest(uint8_t *pMsgDigest, uint8_t Size)\r\n{\r\n  uint32_t msgdigest = (uint32_t)pMsgDigest;\r\n  \r\n  switch(Size)\r\n  {\r\n  case 16:\r\n    /* Read the message digest */\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);\r\n    break;\r\n  case 20:\r\n    /* Read the message digest */\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);\r\n    break;\r\n  case 28:\r\n    /* Read the message digest */\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);\r\n    break;\r\n  case 32:\r\n    /* Read the message digest */\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7]);\r\n    break;\r\n  default:\r\n    break;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  DMA HASH Input Data complete callback. \r\n  * @param  hdma DMA handle\r\n  * @retval None\r\n  */\r\nstatic void HASHEx_DMAXferCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  uint32_t inputaddr = 0;\r\n  uint32_t buffersize = 0;\r\n  \r\n  if((HASH->CR & HASH_CR_MODE) != HASH_CR_MODE)\r\n  {\r\n    /* Disable the DMA transfer */\r\n    HASH->CR &= (uint32_t)(~HASH_CR_DMAE);\r\n    \r\n    /* Change HASH peripheral state */\r\n    hhash->State = HAL_HASH_STATE_READY;\r\n    \r\n    /* Call Input data transfer complete callback */\r\n    HAL_HASH_InCpltCallback(hhash);\r\n  }\r\n  else\r\n  {\r\n    /* Increment Interrupt counter */\r\n    hhash->HashInCount++;\r\n    /* Disable the DMA transfer before starting the next transfer */\r\n    HASH->CR &= (uint32_t)(~HASH_CR_DMAE);\r\n    \r\n    if(hhash->HashInCount <= 2)\r\n    {\r\n      /* In case HashInCount = 1, set the DMA to transfer data to HASH DIN register */\r\n      if(hhash->HashInCount == 1)\r\n      {\r\n        inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r\n        buffersize = hhash->HashBuffSize;\r\n      }\r\n      /* In case HashInCount = 2, set the DMA to transfer key to HASH DIN register */\r\n      else if(hhash->HashInCount == 2)\r\n      {\r\n        inputaddr = (uint32_t)hhash->Init.pKey;\r\n        buffersize = hhash->Init.KeySize;\r\n      }\r\n      /* Configure the number of valid bits in last word of the message */\r\n      MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * (buffersize % 4));\r\n      \r\n      /* Set the HASH DMA transfer complete */\r\n      hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;\r\n      \r\n      /* Enable the DMA In DMA Stream */\r\n      HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4 ? (buffersize+3)/4:buffersize/4));\r\n      \r\n      /* Enable DMA requests */\r\n      HASH->CR |= (HASH_CR_DMAE);\r\n    }\r\n    else\r\n    {\r\n      /* Disable the DMA transfer */\r\n      HASH->CR &= (uint32_t)(~HASH_CR_DMAE);\r\n      \r\n      /* Reset the InCount */\r\n      hhash->HashInCount = 0;\r\n      \r\n      /* Change HASH peripheral state */\r\n      hhash->State = HAL_HASH_STATE_READY;\r\n      \r\n      /* Call Input data transfer complete callback */\r\n      HAL_HASH_InCpltCallback(hhash);\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  DMA HASH communication error callback. \r\n  * @param  hdma DMA handle\r\n  * @retval None\r\n  */\r\nstatic void HASHEx_DMAError(DMA_HandleTypeDef *hdma)\r\n{\r\n  HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  hhash->State= HAL_HASH_STATE_READY;\r\n  HAL_HASH_ErrorCallback(hhash);\r\n}\r\n\r\n /**\r\n  * @}\r\n  */\r\n  \r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup HASHEx_Exported_Functions\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup  HASHEx_Group1 HASH processing functions  \r\n *  @brief   processing functions using polling mode \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n              ##### HASH processing using polling mode functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to calculate in polling mode\r\n          the hash value using one of the following algorithms:\r\n      (+) SHA224\r\n      (+) SHA256\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in SHA224 mode\r\n  *         then processes pInBuffer. The digest is available in pOutBuffer\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer Pointer to the input buffer (buffer to be hashed).\r\n  * @param  Size Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @param  pOutBuffer Pointer to the computed digest. Its size must be 28 bytes.\r\n  * @param  Timeout Specify Timeout value   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute \r\n       the message digest of a new message */\r\n    HASH->CR |= HASH_ALGOSELECTION_SHA224 | HASH_CR_INIT;\r\n  }\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n  \r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(Size);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASHEx_WriteData(pInBuffer, Size);\r\n  \r\n  /* Start the digest calculation */\r\n  __HAL_HASH_START_DIGEST();\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */          \r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Read the message digest */\r\n  HASHEx_GetDigest(pOutBuffer, 28);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.\r\n            The digest is available in pOutBuffer.\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer Pointer to the input buffer (buffer to be hashed). \r\n  * @param  Size Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @param  pOutBuffer Pointer to the computed digest. Its size must be 32 bytes.\r\n  * @param  Timeout Specify Timeout value   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute \r\n       the message digest of a new message */\r\n    HASH->CR |= HASH_ALGOSELECTION_SHA256 | HASH_CR_INIT;\r\n  }\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n  \r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(Size);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASHEx_WriteData(pInBuffer, Size);\r\n  \r\n  /* Start the digest calculation */\r\n  __HAL_HASH_START_DIGEST();\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */          \r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Read the message digest */\r\n  HASHEx_GetDigest(pOutBuffer, 32);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_READY;\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);  \r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in SHA224 mode\r\n  *         then processes pInBuffer. The digest is available in pOutBuffer\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer Pointer to the input buffer (buffer to be hashed).\r\n  * @param  Size Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute \r\n       the message digest of a new message */\r\n    HASH->CR |= HASH_ALGOSELECTION_SHA224 | HASH_CR_INIT;\r\n  }\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n  \r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(Size);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASHEx_WriteData(pInBuffer, Size);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.\r\n            The digest is available in pOutBuffer.\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer Pointer to the input buffer (buffer to be hashed).\r\n  * @param  Size Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r\n{\r\n   /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute \r\n       the message digest of a new message */\r\n    HASH->CR |= HASH_ALGOSELECTION_SHA256 | HASH_CR_INIT;\r\n  }\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n  \r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(Size);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASHEx_WriteData(pInBuffer, Size);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HASHEx_Group2 HMAC processing functions using polling mode \r\n *  @brief   HMAC processing functions using polling mode . \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n            ##### HMAC processing using polling mode functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to calculate in polling mode\r\n          the HMAC value using one of the following algorithms:\r\n      (+) SHA224\r\n      (+) SHA256\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in HMAC SHA224 mode\r\n  *         then processes pInBuffer. The digest is available in pOutBuffer.\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer Pointer to the input buffer (buffer to be hashed). \r\n  * @param  Size Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @param  pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.\r\n  * @param  Timeout Timeout value \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n                                                  \r\n   /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Check if key size is greater than 64 bytes */\r\n    if(hhash->Init.KeySize > 64)\r\n    {\r\n      /* Select the HMAC SHA224 mode */\r\n      HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);\r\n    }\r\n    else\r\n    {\r\n      /* Select the HMAC SHA224 mode */\r\n      HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);\r\n    }\r\n  }\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n  \r\n  /************************** STEP 1 ******************************************/\r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);\r\n  \r\n  /* Start the digest calculation */\r\n  __HAL_HASH_START_DIGEST();\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */          \r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  /************************** STEP 2 ******************************************/\r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(Size);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASHEx_WriteData(pInBuffer, Size);\r\n  \r\n  /* Start the digest calculation */\r\n  __HAL_HASH_START_DIGEST();\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > Timeout)\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */          \r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  /************************** STEP 3 ******************************************/\r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);\r\n  \r\n  /* Start the digest calculation */\r\n  __HAL_HASH_START_DIGEST();\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > Timeout)\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */          \r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  /* Read the message digest */\r\n  HASHEx_GetDigest(pOutBuffer, 28);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in HMAC SHA256 mode\r\n  *         then processes pInBuffer. The digest is available in pOutBuffer\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer Pointer to the input buffer (buffer to be hashed). \r\n  * @param  Size Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @param  pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.\r\n  * @param  Timeout Timeout value \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Check if key size is greater than 64 bytes */\r\n    if(hhash->Init.KeySize > 64)\r\n    {\r\n      /* Select the HMAC SHA256 mode */\r\n      HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY);\r\n    }\r\n    else\r\n    {\r\n      /* Select the HMAC SHA256 mode */\r\n      HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC);\r\n    }\r\n    /* Reset the HASH processor core, so that the HASH will be ready to compute \r\n       the message digest of a new message */\r\n    HASH->CR |= HASH_CR_INIT;\r\n  }\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n  \r\n  /************************** STEP 1 ******************************************/\r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);\r\n  \r\n  /* Start the digest calculation */\r\n  __HAL_HASH_START_DIGEST();\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */          \r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  /************************** STEP 2 ******************************************/\r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(Size);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASHEx_WriteData(pInBuffer, Size);\r\n  \r\n  /* Start the digest calculation */\r\n  __HAL_HASH_START_DIGEST();\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > Timeout)\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */          \r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  /************************** STEP 3 ******************************************/\r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);\r\n  \r\n  /* Start the digest calculation */\r\n  __HAL_HASH_START_DIGEST();\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > Timeout)\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */          \r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  /* Read the message digest */\r\n  HASHEx_GetDigest(pOutBuffer, 32);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_READY;\r\n  \r\n   /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HASHEx_Group3 HASH processing functions using interrupt mode\r\n *  @brief   processing functions using interrupt mode. \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n              ##### HASH processing using interrupt functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to calculate in interrupt mode\r\n          the hash value using one of the following algorithms:\r\n      (+) SHA224\r\n      (+) SHA256\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in SHA224 mode then processes pInBuffer.\r\n  *         The digest is available in pOutBuffer.\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer Pointer to the input buffer (buffer to be hashed).\r\n  * @param  Size Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @param  pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t buffercounter;\r\n  uint32_t inputcounter;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n\r\n  if(hhash->State == HAL_HASH_STATE_READY)\r\n  {\r\n    /* Change the HASH state */\r\n    hhash->State = HAL_HASH_STATE_BUSY;\r\n    \r\n    hhash->HashInCount = Size;\r\n    hhash->pHashInBuffPtr = pInBuffer;\r\n    hhash->pHashOutBuffPtr = pOutBuffer;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n    {\r\n      /* Select the SHA224 mode */\r\n      HASH->CR |= HASH_ALGOSELECTION_SHA224;\r\n      /* Reset the HASH processor core, so that the HASH will be ready to compute \r\n         the message digest of a new message */\r\n      HASH->CR |= HASH_CR_INIT;\r\n    }\r\n    /* Reset interrupt counter */\r\n    hhash->HashITCounter = 0;\r\n    /* Set the phase */\r\n    hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hhash);\r\n    \r\n    /* Enable Interrupts */\r\n    HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))\r\n  {\r\n    /* Read the message digest */\r\n    HASHEx_GetDigest(hhash->pHashOutBuffPtr, 28);\r\n    if(hhash->HashInCount == 0)\r\n    {\r\n      /* Disable Interrupts */\r\n      HASH->IMR = 0;\r\n      /* Change the HASH state */\r\n      hhash->State = HAL_HASH_STATE_READY;\r\n      /* Call digest computation complete callback */\r\n      HAL_HASH_DgstCpltCallback(hhash);\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hhash);\r\n      \r\n      /* Return function status */\r\n      return HAL_OK;\r\n    }\r\n  }\r\n  if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))\r\n  {\r\n    if(hhash->HashInCount >= 68)\r\n    {\r\n      inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r\n      /* Write the Input block in the Data IN register */\r\n      for(buffercounter = 0; buffercounter < 64; buffercounter+=4)\r\n      {\r\n        HASH->DIN = *(uint32_t*)inputaddr;\r\n        inputaddr+=4;\r\n      }\r\n      if(hhash->HashITCounter == 0)\r\n      {\r\n        HASH->DIN = *(uint32_t*)inputaddr;\r\n        if(hhash->HashInCount >= 68)\r\n        {\r\n          /* Decrement buffer counter */\r\n          hhash->HashInCount -= 68;\r\n          hhash->pHashInBuffPtr+= 68;\r\n        }\r\n        else\r\n        {\r\n           hhash->HashInCount = 0;\r\n          hhash->pHashInBuffPtr+= hhash->HashInCount;\r\n        }\r\n        /* Set Interrupt counter */\r\n        hhash->HashITCounter = 1;\r\n      }\r\n      else\r\n      {\r\n        /* Decrement buffer counter */\r\n        hhash->HashInCount -= 64;\r\n        hhash->pHashInBuffPtr+= 64;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* Get the buffer address */\r\n      inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r\n      /* Get the buffer counter */\r\n      inputcounter = hhash->HashInCount;\r\n      /* Disable Interrupts */\r\n      HASH->IMR &= ~(HASH_IT_DINI);\r\n      /* Configure the number of valid bits in last word of the message */\r\n      __HAL_HASH_SET_NBVALIDBITS(inputcounter);\r\n      \r\n      if((inputcounter > 4) && (inputcounter%4))\r\n      {\r\n        inputcounter = (inputcounter+4-inputcounter%4);\r\n      }\r\n      else if ((inputcounter < 4) && (inputcounter != 0))\r\n      {\r\n        inputcounter = 4;\r\n      }\r\n      /* Write the Input block in the Data IN register */\r\n      for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)\r\n      {\r\n        HASH->DIN = *(uint32_t*)inputaddr;\r\n        inputaddr+=4;\r\n      }\r\n      /* Start the digest calculation */\r\n      __HAL_HASH_START_DIGEST();\r\n      /* Reset buffer counter */\r\n      hhash->HashInCount = 0;\r\n      /* Call Input data transfer complete callback */\r\n      HAL_HASH_InCpltCallback(hhash);\r\n    }\r\n  }\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.\r\n  *         The digest is available in pOutBuffer.\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer Pointer to the input buffer (buffer to be hashed).\r\n  * @param  Size Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @param  pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t buffercounter;\r\n  uint32_t inputcounter;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n\r\n  if(hhash->State == HAL_HASH_STATE_READY)\r\n  {\r\n    /* Change the HASH state */\r\n    hhash->State = HAL_HASH_STATE_BUSY;\r\n    \r\n    hhash->HashInCount = Size;\r\n    hhash->pHashInBuffPtr = pInBuffer;\r\n    hhash->pHashOutBuffPtr = pOutBuffer;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n    {\r\n      /* Select the SHA256 mode */\r\n      HASH->CR |= HASH_ALGOSELECTION_SHA256;\r\n      /* Reset the HASH processor core, so that the HASH will be ready to compute \r\n         the message digest of a new message */\r\n      HASH->CR |= HASH_CR_INIT;\r\n    }\r\n    \r\n    /* Reset interrupt counter */\r\n    hhash->HashITCounter = 0;\r\n    \r\n    /* Set the phase */\r\n    hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hhash);\r\n    \r\n    /* Enable Interrupts */\r\n    HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))\r\n  {\r\n    /* Read the message digest */\r\n    HASHEx_GetDigest(hhash->pHashOutBuffPtr, 32);\r\n    if(hhash->HashInCount == 0)\r\n    {\r\n      /* Disable Interrupts */\r\n      HASH->IMR = 0;\r\n      /* Change the HASH state */\r\n      hhash->State = HAL_HASH_STATE_READY;\r\n      /* Call digest computation complete callback */\r\n      HAL_HASH_DgstCpltCallback(hhash);\r\n      \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hhash);\r\n      \r\n      /* Return function status */\r\n      return HAL_OK;\r\n    }\r\n  }\r\n  if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))\r\n  {\r\n    if(hhash->HashInCount >= 68)\r\n    {\r\n      inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r\n      /* Write the Input block in the Data IN register */\r\n      for(buffercounter = 0; buffercounter < 64; buffercounter+=4)\r\n      {\r\n        HASH->DIN = *(uint32_t*)inputaddr;\r\n        inputaddr+=4;\r\n      }\r\n      if(hhash->HashITCounter == 0)\r\n      {\r\n        HASH->DIN = *(uint32_t*)inputaddr;\r\n        \r\n        if(hhash->HashInCount >= 68)\r\n        {\r\n          /* Decrement buffer counter */\r\n          hhash->HashInCount -= 68;\r\n          hhash->pHashInBuffPtr+= 68;\r\n        }\r\n        else\r\n        {\r\n          hhash->HashInCount = 0;\r\n          hhash->pHashInBuffPtr+= hhash->HashInCount;\r\n        }\r\n        /* Set Interrupt counter */\r\n        hhash->HashITCounter = 1;\r\n      }\r\n      else\r\n      {\r\n        /* Decrement buffer counter */\r\n        hhash->HashInCount -= 64;\r\n        hhash->pHashInBuffPtr+= 64;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* Get the buffer address */\r\n      inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r\n      /* Get the buffer counter */\r\n      inputcounter = hhash->HashInCount;\r\n      /* Disable Interrupts */\r\n      HASH->IMR &= ~(HASH_IT_DINI);\r\n      /* Configure the number of valid bits in last word of the message */\r\n      __HAL_HASH_SET_NBVALIDBITS(inputcounter);\r\n      \r\n      if((inputcounter > 4) && (inputcounter%4))\r\n      {\r\n        inputcounter = (inputcounter+4-inputcounter%4);\r\n      }\r\n      else if ((inputcounter < 4) && (inputcounter != 0))\r\n      {\r\n        inputcounter = 4;\r\n      }\r\n      \r\n      /* Write the Input block in the Data IN register */\r\n      for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)\r\n      {\r\n        HASH->DIN = *(uint32_t*)inputaddr;\r\n        inputaddr+=4;\r\n      }\r\n      /* Start the digest calculation */\r\n      __HAL_HASH_START_DIGEST();\r\n      /* Reset buffer counter */\r\n      hhash->HashInCount = 0;\r\n      /* Call Input data transfer complete callback */\r\n      HAL_HASH_InCpltCallback(hhash);\r\n    }\r\n  }\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief This function handles HASH interrupt request.\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @retval None\r\n  */\r\nvoid HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash)\r\n{\r\n  switch(HASH->CR & HASH_CR_ALGO)\r\n  {\r\n    \r\n    case HASH_ALGOSELECTION_SHA224:\r\n       HAL_HASHEx_SHA224_Start_IT(hhash, NULL, 0, NULL);\r\n    break;\r\n    \r\n    case HASH_ALGOSELECTION_SHA256:\r\n      HAL_HASHEx_SHA256_Start_IT(hhash, NULL, 0, NULL);\r\n    break;\r\n    \r\n    default:\r\n    break;\r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HASHEx_Group4 HASH processing functions using DMA mode\r\n *  @brief   processing functions using DMA mode. \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                ##### HASH processing using DMA functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to calculate in DMA mode\r\n          the hash value using one of the following algorithms:\r\n      (+) SHA224\r\n      (+) SHA256\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in SHA224 mode then enables DMA to\r\n            control data transfer. Use HAL_HASH_SHA224_Finish() to get the digest.\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer Pointer to the input buffer (buffer to be hashed).\r\n  * @param  Size Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r\n{\r\n  uint32_t inputaddr  = (uint32_t)pInBuffer;\r\n  \r\n   /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute \r\n       the message digest of a new message */\r\n    HASH->CR |= HASH_ALGOSELECTION_SHA224 | HASH_CR_INIT;\r\n  }\r\n   \r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(Size);\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n    \r\n  /* Set the HASH DMA transfer complete callback */\r\n  hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;\r\n  /* Set the DMA error callback */\r\n  hhash->hdmain->XferErrorCallback = HASHEx_DMAError;\r\n  \r\n  /* Enable the DMA In DMA Stream */\r\n  HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));\r\n  \r\n  /* Enable DMA requests */\r\n  HASH->CR |= (HASH_CR_DMAE);\r\n  \r\n   /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the computed digest in SHA224\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pOutBuffer Pointer to the computed digest. Its size must be 28 bytes.\r\n  * @param  Timeout Timeout value    \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change HASH peripheral state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */          \r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Read the message digest */\r\n  HASHEx_GetDigest(pOutBuffer, 28);\r\n      \r\n  /* Change HASH peripheral state */\r\n  hhash->State = HAL_HASH_STATE_READY;\r\n  \r\n   /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in SHA256 mode then enables DMA to\r\n            control data transfer. Use HAL_HASH_SHA256_Finish() to get the digest.\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer Pointer to the input buffer (buffer to be hashed).\r\n  * @param  Size Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r\n{\r\n  uint32_t inputaddr  = (uint32_t)pInBuffer;\r\n  \r\n   /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute \r\n       the message digest of a new message */\r\n    HASH->CR |= HASH_ALGOSELECTION_SHA256 | HASH_CR_INIT;\r\n  }\r\n  \r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(Size);\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n    \r\n  /* Set the HASH DMA transfer complete callback */\r\n  hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;\r\n  /* Set the DMA error callback */\r\n  hhash->hdmain->XferErrorCallback = HASHEx_DMAError;\r\n  \r\n  /* Enable the DMA In DMA Stream */\r\n  HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));\r\n  \r\n  /* Enable DMA requests */\r\n  HASH->CR |= (HASH_CR_DMAE);\r\n  \r\n   /* Process UnLock */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the computed digest in SHA256.\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pOutBuffer Pointer to the computed digest. Its size must be 32 bytes.\r\n  * @param  Timeout Timeout value    \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  \r\n   /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change HASH peripheral state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */          \r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Read the message digest */\r\n  HASHEx_GetDigest(pOutBuffer, 32);\r\n  \r\n  /* Change HASH peripheral state */\r\n  hhash->State = HAL_HASH_STATE_READY;\r\n  \r\n   /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n/** @defgroup HASHEx_Group5 HMAC processing functions using DMA mode \r\n *  @brief   HMAC processing functions using DMA mode . \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                ##### HMAC processing using DMA functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to calculate in DMA mode\r\n          the HMAC value using one of the following algorithms:\r\n      (+) SHA224\r\n      (+) SHA256\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in HMAC SHA224 mode\r\n  *         then enables DMA to control data transfer.\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer Pointer to the input buffer (buffer to be hashed).\r\n  * @param  Size Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r\n{\r\n  uint32_t inputaddr;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Save buffer pointer and size in handle */\r\n  hhash->pHashInBuffPtr = pInBuffer;\r\n  hhash->HashBuffSize = Size;\r\n  hhash->HashInCount = 0;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Check if key size is greater than 64 bytes */\r\n    if(hhash->Init.KeySize > 64)\r\n    {\r\n      /* Select the HMAC SHA224 mode */\r\n      HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);\r\n    }\r\n    else\r\n    {\r\n      /* Select the HMAC SHA224 mode */\r\n      HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);\r\n    }\r\n  }\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n  \r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r\n  \r\n  /* Get the key address */\r\n  inputaddr = (uint32_t)(hhash->Init.pKey);\r\n  \r\n  /* Set the HASH DMA transfer complete callback */\r\n  hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;\r\n  /* Set the DMA error callback */\r\n  hhash->hdmain->XferErrorCallback = HASHEx_DMAError;\r\n  \r\n  /* Enable the DMA In DMA Stream */\r\n  HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));\r\n  /* Enable DMA requests */\r\n  HASH->CR |= (HASH_CR_DMAE);\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in HMAC SHA256 mode\r\n  *         then enables DMA to control data transfer.\r\n  * @param  hhash pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer Pointer to the input buffer (buffer to be hashed).\r\n  * @param  Size Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r\n{\r\n  uint32_t inputaddr;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Save buffer pointer and size in handle */\r\n  hhash->pHashInBuffPtr = pInBuffer;\r\n  hhash->HashBuffSize = Size;\r\n  hhash->HashInCount = 0;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Check if key size is greater than 64 bytes */\r\n    if(hhash->Init.KeySize > 64)\r\n    {\r\n      /* Select the HMAC SHA256 mode */\r\n      HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY);\r\n    }\r\n    else\r\n    {\r\n      /* Select the HMAC SHA256 mode */\r\n      HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC);\r\n    }\r\n    /* Reset the HASH processor core, so that the HASH will be ready to compute \r\n       the message digest of a new message */\r\n    HASH->CR |= HASH_CR_INIT;\r\n  }\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n  \r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r\n  \r\n  /* Get the key address */\r\n  inputaddr = (uint32_t)(hhash->Init.pKey);\r\n  \r\n  /* Set the HASH DMA transfer complete callback */\r\n  hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;\r\n  /* Set the DMA error callback */\r\n  hhash->hdmain->XferErrorCallback = HASHEx_DMAError;\r\n  \r\n  /* Enable the DMA In DMA Stream */\r\n  HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));\r\n  /* Enable DMA requests */\r\n  HASH->CR |= (HASH_CR_DMAE);\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n#endif /* HAL_HASH_MODULE_ENABLED */\r\n\r\n/**\r\n  * @}\r\n  */\r\n#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hcd.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_hcd.c\r\n  * @author  MCD Application Team\r\n  * @brief   HCD HAL module driver.\r\n  *          This file provides firmware functions to manage the following\r\n  *          functionalities of the USB Peripheral Controller:\r\n  *           + Initialization and de-initialization functions\r\n  *           + IO operation functions\r\n  *           + Peripheral Control functions\r\n  *           + Peripheral State functions\r\n  *\r\n  @verbatim\r\n  ==============================================================================\r\n                    ##### How to use this driver #####\r\n  ==============================================================================\r\n  [..]\r\n    (#)Declare a HCD_HandleTypeDef handle structure, for example:\r\n       HCD_HandleTypeDef  hhcd;\r\n\r\n    (#)Fill parameters of Init structure in HCD handle\r\n\r\n    (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...)\r\n\r\n    (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:\r\n        (##) Enable the HCD/USB Low Level interface clock using the following macros\r\n             (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();\r\n             (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)\r\n             (+++) __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE(); (For High Speed Mode)\r\n\r\n        (##) Initialize the related GPIO clocks\r\n        (##) Configure HCD pin-out\r\n        (##) Configure HCD NVIC interrupt\r\n\r\n    (#)Associate the Upper USB Host stack to the HAL HCD Driver:\r\n        (##) hhcd.pData = phost;\r\n\r\n    (#)Enable HCD transmission and reception:\r\n        (##) HAL_HCD_Start();\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup HCD HCD\r\n  * @brief HCD HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_HCD_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/** @defgroup HCD_Private_Functions HCD Private Functions\r\n  * @{\r\n  */\r\nstatic void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);\r\nstatic void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);\r\nstatic void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd);\r\nstatic void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup HCD_Exported_Functions HCD Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions\r\n *  @brief    Initialization and Configuration functions\r\n *\r\n@verbatim\r\n ===============================================================================\r\n          ##### Initialization and de-initialization functions #####\r\n ===============================================================================\r\n    [..]  This section provides functions allowing to:\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initialize the host driver.\r\n  * @param  hhcd HCD handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)\r\n{\r\n  /* Check the HCD handle allocation */\r\n  if(hhcd == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));\r\n\r\n  if(hhcd->State == HAL_HCD_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    hhcd->Lock = HAL_UNLOCKED;\r\n\r\n    /* Init the low level hardware : GPIO, CLOCK, NVIC... */\r\n    HAL_HCD_MspInit(hhcd);\r\n  }\r\n\r\n  hhcd->State = HAL_HCD_STATE_BUSY;\r\n\r\n  /* Disable the Interrupts */\r\n  __HAL_HCD_DISABLE(hhcd);\r\n\r\n  /* Init the Core (common init.) */\r\n  (void)USB_CoreInit(hhcd->Instance, hhcd->Init);\r\n\r\n  /* Force Host Mode*/\r\n  (void)USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE);\r\n\r\n  /* Init Host */\r\n  (void)USB_HostInit(hhcd->Instance, hhcd->Init);\r\n\r\n  hhcd->State= HAL_HCD_STATE_READY;\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initialize a host channel.\r\n  * @param  hhcd HCD handle\r\n  * @param  ch_num Channel number.\r\n  *         This parameter can be a value from 1 to 15\r\n  * @param  epnum Endpoint number.\r\n  *          This parameter can be a value from 1 to 15\r\n  * @param  dev_address Current device address\r\n  *          This parameter can be a value from 0 to 255\r\n  * @param  speed Current device speed.\r\n  *          This parameter can be one of these values:\r\n  *            HCD_SPEED_HIGH: High speed mode,\r\n  *            HCD_SPEED_FULL: Full speed mode,\r\n  *            HCD_SPEED_LOW: Low speed mode\r\n  * @param  ep_type Endpoint Type.\r\n  *          This parameter can be one of these values:\r\n  *            EP_TYPE_CTRL: Control type,\r\n  *            EP_TYPE_ISOC: Isochronous type,\r\n  *            EP_TYPE_BULK: Bulk type,\r\n  *            EP_TYPE_INTR: Interrupt type\r\n  * @param  mps Max Packet Size.\r\n  *          This parameter can be a value from 0 to32K\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,\r\n                                  uint8_t ch_num,\r\n                                  uint8_t epnum,\r\n                                  uint8_t dev_address,\r\n                                  uint8_t speed,\r\n                                  uint8_t ep_type,\r\n                                  uint16_t mps)\r\n{\r\n  HAL_StatusTypeDef status;\r\n\r\n  __HAL_LOCK(hhcd);\r\n  hhcd->hc[ch_num].do_ping = 0U;\r\n  hhcd->hc[ch_num].dev_addr = dev_address;\r\n  hhcd->hc[ch_num].max_packet = mps;\r\n  hhcd->hc[ch_num].ch_num = ch_num;\r\n  hhcd->hc[ch_num].ep_type = ep_type;\r\n  hhcd->hc[ch_num].ep_num = epnum & 0x7FU;\r\n\r\n  if ((epnum & 0x80U) == 0x80U)\r\n  {\r\n    hhcd->hc[ch_num].ep_is_in = 1U;\r\n  }\r\n  else\r\n  {\r\n    hhcd->hc[ch_num].ep_is_in = 0U;\r\n  }\r\n\r\n  hhcd->hc[ch_num].speed = speed;\r\n\r\n  status =  USB_HC_Init(hhcd->Instance,\r\n                        ch_num,\r\n                        epnum,\r\n                        dev_address,\r\n                        speed,\r\n                        ep_type,\r\n                        mps);\r\n  __HAL_UNLOCK(hhcd);\r\n\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Halt a host channel.\r\n  * @param  hhcd HCD handle\r\n  * @param  ch_num Channel number.\r\n  *         This parameter can be a value from 1 to 15\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  __HAL_LOCK(hhcd);\r\n  (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);\r\n  __HAL_UNLOCK(hhcd);\r\n\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  DeInitialize the host driver.\r\n  * @param  hhcd HCD handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)\r\n{\r\n  /* Check the HCD handle allocation */\r\n  if(hhcd == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  hhcd->State = HAL_HCD_STATE_BUSY;\r\n\r\n  /* DeInit the low level hardware */\r\n  HAL_HCD_MspDeInit(hhcd);\r\n\r\n  __HAL_HCD_DISABLE(hhcd);\r\n\r\n  hhcd->State = HAL_HCD_STATE_RESET;\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initialize the HCD MSP.\r\n  * @param  hhcd HCD handle\r\n  * @retval None\r\n  */\r\n__weak void  HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hhcd);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_HCD_MspInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DeInitialize the HCD MSP.\r\n  * @param  hhcd HCD handle\r\n  * @retval None\r\n  */\r\n__weak void  HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hhcd);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_HCD_MspDeInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions\r\n  *  @brief   HCD IO operation functions\r\n  *\r\n@verbatim\r\n ===============================================================================\r\n                      ##### IO operation functions #####\r\n ===============================================================================\r\n [..] This subsection provides a set of functions allowing to manage the USB Host Data\r\n    Transfer\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Submit a new URB for processing.\r\n  * @param  hhcd HCD handle\r\n  * @param  ch_num Channel number.\r\n  *         This parameter can be a value from 1 to 15\r\n  * @param  direction Channel number.\r\n  *          This parameter can be one of these values:\r\n  *           0 : Output / 1 : Input\r\n  * @param  ep_type Endpoint Type.\r\n  *          This parameter can be one of these values:\r\n  *            EP_TYPE_CTRL: Control type/\r\n  *            EP_TYPE_ISOC: Isochronous type/\r\n  *            EP_TYPE_BULK: Bulk type/\r\n  *            EP_TYPE_INTR: Interrupt type/\r\n  * @param  token Endpoint Type.\r\n  *          This parameter can be one of these values:\r\n  *            0: HC_PID_SETUP / 1: HC_PID_DATA1\r\n  * @param  pbuff pointer to URB data\r\n  * @param  length Length of URB data\r\n  * @param  do_ping activate do ping protocol (for high speed only).\r\n  *          This parameter can be one of these values:\r\n  *           0 : do ping inactive / 1 : do ping active\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,\r\n                                           uint8_t ch_num,\r\n                                           uint8_t direction,\r\n                                           uint8_t ep_type,\r\n                                           uint8_t token,\r\n                                           uint8_t* pbuff,\r\n                                           uint16_t length,\r\n                                           uint8_t do_ping)\r\n{\r\n  UNUSED(do_ping);\r\n\r\n  hhcd->hc[ch_num].ep_is_in = direction;\r\n  hhcd->hc[ch_num].ep_type  = ep_type;\r\n\r\n  if(token == 0U)\r\n  {\r\n    hhcd->hc[ch_num].data_pid = HC_PID_SETUP;\r\n  }\r\n  else\r\n  {\r\n    hhcd->hc[ch_num].data_pid = HC_PID_DATA1;\r\n  }\r\n\r\n  /* Manage Data Toggle */\r\n  switch(ep_type)\r\n  {\r\n  case EP_TYPE_CTRL:\r\n    if((token == 1U) && (direction == 0U)) /*send data */\r\n    {\r\n      if (length == 0U)\r\n      { /* For Status OUT stage, Length==0, Status Out PID = 1 */\r\n        hhcd->hc[ch_num].toggle_out = 1U;\r\n      }\r\n\r\n      /* Set the Data Toggle bit as per the Flag */\r\n      if (hhcd->hc[ch_num].toggle_out == 0U)\r\n      { /* Put the PID 0 */\r\n        hhcd->hc[ch_num].data_pid = HC_PID_DATA0;\r\n      }\r\n      else\r\n      { /* Put the PID 1 */\r\n        hhcd->hc[ch_num].data_pid = HC_PID_DATA1;\r\n      }\r\n    }\r\n    break;\r\n\r\n  case EP_TYPE_BULK:\r\n    if(direction == 0U)\r\n    {\r\n      /* Set the Data Toggle bit as per the Flag */\r\n      if ( hhcd->hc[ch_num].toggle_out == 0U)\r\n      { /* Put the PID 0 */\r\n        hhcd->hc[ch_num].data_pid = HC_PID_DATA0;\r\n      }\r\n      else\r\n      { /* Put the PID 1 */\r\n        hhcd->hc[ch_num].data_pid = HC_PID_DATA1;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      if( hhcd->hc[ch_num].toggle_in == 0U)\r\n      {\r\n        hhcd->hc[ch_num].data_pid = HC_PID_DATA0;\r\n      }\r\n      else\r\n      {\r\n        hhcd->hc[ch_num].data_pid = HC_PID_DATA1;\r\n      }\r\n    }\r\n\r\n    break;\r\n  case EP_TYPE_INTR:\r\n    if(direction == 0U)\r\n    {\r\n      /* Set the Data Toggle bit as per the Flag */\r\n      if ( hhcd->hc[ch_num].toggle_out == 0U)\r\n      { /* Put the PID 0 */\r\n        hhcd->hc[ch_num].data_pid = HC_PID_DATA0;\r\n      }\r\n      else\r\n      { /* Put the PID 1 */\r\n        hhcd->hc[ch_num].data_pid = HC_PID_DATA1;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      if( hhcd->hc[ch_num].toggle_in == 0U)\r\n      {\r\n        hhcd->hc[ch_num].data_pid = HC_PID_DATA0;\r\n      }\r\n      else\r\n      {\r\n        hhcd->hc[ch_num].data_pid = HC_PID_DATA1;\r\n      }\r\n    }\r\n    break;\r\n\r\n  case EP_TYPE_ISOC:\r\n    hhcd->hc[ch_num].data_pid = HC_PID_DATA0;\r\n    break;\r\n\r\n  default:\r\n    break;\r\n  }\r\n\r\n  hhcd->hc[ch_num].xfer_buff = pbuff;\r\n  hhcd->hc[ch_num].xfer_len  = length;\r\n  hhcd->hc[ch_num].urb_state = URB_IDLE;\r\n  hhcd->hc[ch_num].xfer_count = 0U;\r\n  hhcd->hc[ch_num].ch_num = ch_num;\r\n  hhcd->hc[ch_num].state = HC_IDLE;\r\n\r\n  return USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[ch_num], (uint8_t)hhcd->Init.dma_enable);\r\n}\r\n\r\n/**\r\n  * @brief  Handle HCD interrupt request.\r\n  * @param  hhcd HCD handle\r\n  * @retval None\r\n  */\r\nvoid HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)\r\n{\r\n  USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n  uint32_t i, interrupt;\r\n\r\n  /* Ensure that we are in device mode */\r\n  if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST)\r\n  {\r\n    /* Avoid spurious interrupt */\r\n    if(__HAL_HCD_IS_INVALID_INTERRUPT(hhcd))\r\n    {\r\n      return;\r\n    }\r\n\r\n    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))\r\n    {\r\n      /* Incorrect mode, acknowledge the interrupt */\r\n      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);\r\n    }\r\n\r\n    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR))\r\n    {\r\n      /* Incorrect mode, acknowledge the interrupt */\r\n      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR);\r\n    }\r\n\r\n    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE))\r\n    {\r\n      /* Incorrect mode, acknowledge the interrupt */\r\n      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE);\r\n    }\r\n\r\n    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS))\r\n    {\r\n      /* Incorrect mode, acknowledge the interrupt */\r\n      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS);\r\n    }\r\n\r\n    /* Handle Host Disconnect Interrupts */\r\n    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT))\r\n    {\r\n\r\n      /* Cleanup HPRT */\r\n      USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\\\r\n        USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );\r\n\r\n      /* Handle Host Port Interrupts */\r\n      HAL_HCD_Disconnect_Callback(hhcd);\r\n      (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);\r\n      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);\r\n    }\r\n\r\n    /* Handle Host Port Interrupts */\r\n    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT))\r\n    {\r\n      HCD_Port_IRQHandler (hhcd);\r\n    }\r\n\r\n    /* Handle Host SOF Interrupts */\r\n    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF))\r\n    {\r\n      HAL_HCD_SOF_Callback(hhcd);\r\n      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);\r\n    }\r\n\r\n    /* Handle Host channel Interrupts */\r\n    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))\r\n    {\r\n      interrupt = USB_HC_ReadInterrupt(hhcd->Instance);\r\n      for (i = 0U; i < hhcd->Init.Host_channels; i++)\r\n      {\r\n        if ((interrupt & (1UL << (i & 0xFU))) != 0U)\r\n        {\r\n          if ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_EPDIR) == USB_OTG_HCCHAR_EPDIR)\r\n          {\r\n            HCD_HC_IN_IRQHandler(hhcd, (uint8_t)i);\r\n          }\r\n          else\r\n          {\r\n            HCD_HC_OUT_IRQHandler (hhcd, (uint8_t)i);\r\n          }\r\n        }\r\n      }\r\n      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT);\r\n    }\r\n\r\n    /* Handle Rx Queue Level Interrupts */\r\n    if((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U)\r\n    {\r\n      USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);\r\n\r\n      HCD_RXQLVL_IRQHandler (hhcd);\r\n\r\n      USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  SOF callback.\r\n  * @param  hhcd HCD handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hhcd);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_HCD_SOF_Callback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief Connection Event callback.\r\n  * @param  hhcd HCD handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hhcd);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_HCD_Connect_Callback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Disconnection Event callback.\r\n  * @param  hhcd HCD handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hhcd);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_HCD_Disconnect_Callback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Port Enabled  Event callback.\r\n  * @param  hhcd HCD handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hhcd);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_HCD_Disconnect_Callback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Port Disabled  Event callback.\r\n  * @param  hhcd HCD handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hhcd);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_HCD_Disconnect_Callback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Notify URB state change callback.\r\n  * @param  hhcd HCD handle\r\n  * @param  chnum Channel number.\r\n  *         This parameter can be a value from 1 to 15\r\n  * @param  urb_state:\r\n  *          This parameter can be one of these values:\r\n  *            URB_IDLE/\r\n  *            URB_DONE/\r\n  *            URB_NOTREADY/\r\n  *            URB_NYET/\r\n  *            URB_ERROR/\r\n  *            URB_STALL/\r\n  * @retval None\r\n  */\r\n__weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hhcd);\r\n  UNUSED(chnum);\r\n  UNUSED(urb_state);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions\r\n *  @brief   Management functions\r\n *\r\n@verbatim\r\n ===============================================================================\r\n                      ##### Peripheral Control functions #####\r\n ===============================================================================\r\n    [..]\r\n    This subsection provides a set of functions allowing to control the HCD data\r\n    transfers.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Start the host driver.\r\n  * @param  hhcd HCD handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)\r\n{\r\n  __HAL_LOCK(hhcd);\r\n  __HAL_HCD_ENABLE(hhcd);\r\n  (void)USB_DriveVbus(hhcd->Instance, 1U);\r\n  __HAL_UNLOCK(hhcd);\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stop the host driver.\r\n  * @param  hhcd HCD handle\r\n  * @retval HAL status\r\n  */\r\n\r\nHAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)\r\n{\r\n  __HAL_LOCK(hhcd);\r\n  (void)USB_StopHost(hhcd->Instance);\r\n  __HAL_UNLOCK(hhcd);\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Reset the host port.\r\n  * @param  hhcd HCD handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)\r\n{\r\n  return (USB_ResetPort(hhcd->Instance));\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions\r\n *  @brief   Peripheral State functions\r\n *\r\n@verbatim\r\n ===============================================================================\r\n                      ##### Peripheral State functions #####\r\n ===============================================================================\r\n    [..]\r\n    This subsection permits to get in run-time the status of the peripheral\r\n    and the data flow.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Return the HCD handle state.\r\n  * @param  hhcd HCD handle\r\n  * @retval HAL state\r\n  */\r\nHCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)\r\n{\r\n  return hhcd->State;\r\n}\r\n\r\n/**\r\n  * @brief  Return  URB state for a channel.\r\n  * @param  hhcd HCD handle\r\n  * @param  chnum Channel number.\r\n  *         This parameter can be a value from 1 to 15\r\n  * @retval URB state.\r\n  *          This parameter can be one of these values:\r\n  *            URB_IDLE/\r\n  *            URB_DONE/\r\n  *            URB_NOTREADY/\r\n  *            URB_NYET/\r\n  *            URB_ERROR/\r\n  *            URB_STALL\r\n  */\r\nHCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum)\r\n{\r\n  return hhcd->hc[chnum].urb_state;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Return the last host transfer size.\r\n  * @param  hhcd HCD handle\r\n  * @param  chnum Channel number.\r\n  *         This parameter can be a value from 1 to 15\r\n  * @retval last transfer size in byte\r\n  */\r\nuint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum)\r\n{\r\n  return hhcd->hc[chnum].xfer_count;\r\n}\r\n\r\n/**\r\n  * @brief  Return the Host Channel state.\r\n  * @param  hhcd HCD handle\r\n  * @param  chnum Channel number.\r\n  *         This parameter can be a value from 1 to 15\r\n  * @retval Host channel state\r\n  *          This parameter can be one of these values:\r\n  *            HC_IDLE/\r\n  *            HC_XFRC/\r\n  *            HC_HALTED/\r\n  *            HC_NYET/\r\n  *            HC_NAK/\r\n  *            HC_STALL/\r\n  *            HC_XACTERR/\r\n  *            HC_BBLERR/\r\n  *            HC_DATATGLERR\r\n  */\r\nHCD_HCStateTypeDef  HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)\r\n{\r\n  return hhcd->hc[chnum].state;\r\n}\r\n\r\n/**\r\n  * @brief  Return the current Host frame number.\r\n  * @param  hhcd HCD handle\r\n  * @retval Current Host frame number\r\n  */\r\nuint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)\r\n{\r\n  return (USB_GetCurrentFrame(hhcd->Instance));\r\n}\r\n\r\n/**\r\n  * @brief  Return the Host enumeration speed.\r\n  * @param  hhcd HCD handle\r\n  * @retval Enumeration speed\r\n  */\r\nuint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)\r\n{\r\n  return (USB_GetHostSpeed(hhcd->Instance));\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup HCD_Private_Functions\r\n  * @{\r\n  */\r\n/**\r\n  * @brief  Handle Host Channel IN interrupt requests.\r\n  * @param  hhcd HCD handle\r\n  * @param  chnum Channel number.\r\n  *         This parameter can be a value from 1 to 15\r\n  * @retval none\r\n  */\r\nstatic void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)\r\n{\r\n  USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n  uint32_t ch_num = (uint32_t)chnum;\r\n\r\n  uint32_t tmpreg;\r\n\r\n  if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR)\r\n  {\r\n    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR);\r\n    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);\r\n  }\r\n  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK)\r\n  {\r\n    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK);\r\n  }\r\n  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL)\r\n  {\r\n    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);\r\n    hhcd->hc[ch_num].state = HC_STALL;\r\n    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);\r\n    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL);\r\n    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);\r\n  }\r\n  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR)\r\n  {\r\n    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);\r\n    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);\r\n    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);\r\n    hhcd->hc[ch_num].state = HC_DATATGLERR;\r\n    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR);\r\n  }\r\n  else\r\n  {\r\n    /* ... */\r\n  }\r\n\r\n  if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR)\r\n  {\r\n    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);\r\n    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);\r\n    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR);\r\n  }\r\n  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC)\r\n  {\r\n    if (hhcd->Init.dma_enable != 0U)\r\n    {\r\n      hhcd->hc[ch_num].xfer_count = hhcd->hc[ch_num].xfer_len - \\\r\n                               (USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);\r\n    }\r\n\r\n    hhcd->hc[ch_num].state = HC_XFRC;\r\n    hhcd->hc[ch_num].ErrCnt = 0U;\r\n    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC);\r\n\r\n    if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL)||\r\n        (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK))\r\n    {\r\n      __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);\r\n      (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);\r\n      __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);\r\n    }\r\n    else if(hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)\r\n    {\r\n      USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;\r\n      hhcd->hc[ch_num].urb_state = URB_DONE;\r\n      HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);\r\n    }\r\n    else\r\n    {\r\n      /* ... */\r\n    }\r\n    hhcd->hc[ch_num].toggle_in ^= 1U;\r\n\r\n  }\r\n  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH)\r\n  {\r\n    __HAL_HCD_MASK_HALT_HC_INT(ch_num);\r\n\r\n    if(hhcd->hc[ch_num].state == HC_XFRC)\r\n    {\r\n      hhcd->hc[ch_num].urb_state  = URB_DONE;\r\n    }\r\n    else if (hhcd->hc[ch_num].state == HC_STALL)\r\n    {\r\n      hhcd->hc[ch_num].urb_state  = URB_STALL;\r\n    }\r\n    else if((hhcd->hc[ch_num].state == HC_XACTERR) ||\r\n            (hhcd->hc[ch_num].state == HC_DATATGLERR))\r\n    {\r\n      hhcd->hc[ch_num].ErrCnt++;\r\n      if(hhcd->hc[ch_num].ErrCnt > 3U)\r\n      {\r\n        hhcd->hc[ch_num].ErrCnt = 0U;\r\n        hhcd->hc[ch_num].urb_state = URB_ERROR;\r\n      }\r\n      else\r\n      {\r\n        hhcd->hc[ch_num].urb_state = URB_NOTREADY;\r\n      }\r\n\r\n      /* re-activate the channel  */\r\n      tmpreg = USBx_HC(ch_num)->HCCHAR;\r\n      tmpreg &= ~USB_OTG_HCCHAR_CHDIS;\r\n      tmpreg |= USB_OTG_HCCHAR_CHENA;\r\n      USBx_HC(ch_num)->HCCHAR = tmpreg;\r\n    }\r\n    else if (hhcd->hc[ch_num].state == HC_NAK)\r\n    {\r\n      hhcd->hc[ch_num].urb_state  = URB_NOTREADY;\r\n      /* re-activate the channel  */\r\n      tmpreg = USBx_HC(ch_num)->HCCHAR;\r\n      tmpreg &= ~USB_OTG_HCCHAR_CHDIS;\r\n      tmpreg |= USB_OTG_HCCHAR_CHENA;\r\n      USBx_HC(ch_num)->HCCHAR = tmpreg;\r\n    }\r\n    else\r\n    {\r\n      /* ... */\r\n    }\r\n    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH);\r\n    HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);\r\n  }\r\n  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR)\r\n  {\r\n    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);\r\n    hhcd->hc[ch_num].ErrCnt++;\r\n    hhcd->hc[ch_num].state = HC_XACTERR;\r\n    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);\r\n    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);\r\n  }\r\n  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK)\r\n  {\r\n    if(hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)\r\n    {\r\n      hhcd->hc[ch_num].ErrCnt = 0U;\r\n      __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);\r\n      (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);\r\n    }\r\n    else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL)||\r\n             (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK))\r\n    {\r\n       hhcd->hc[ch_num].ErrCnt = 0U;\r\n       if (hhcd->Init.dma_enable == 0U)\r\n       {\r\n         hhcd->hc[ch_num].state = HC_NAK;\r\n         __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);\r\n         (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);\r\n       }\r\n    }\r\n    else\r\n    {\r\n      /* ... */\r\n    }\r\n    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);\r\n  }\r\n  else\r\n  {\r\n    /* ... */\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Handle Host Channel OUT interrupt requests.\r\n  * @param  hhcd HCD handle\r\n  * @param  chnum Channel number.\r\n  *         This parameter can be a value from 1 to 15\r\n  * @retval none\r\n  */\r\nstatic void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)\r\n{\r\n  USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n  uint32_t ch_num = (uint32_t)chnum;\r\n  uint32_t tmpreg;\r\n\r\n  if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR)\r\n  {\r\n    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR);\r\n    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);\r\n  }\r\n  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK)\r\n  {\r\n    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK);\r\n\r\n    if( hhcd->hc[ch_num].do_ping == 1U)\r\n    {\r\n      hhcd->hc[ch_num].do_ping = 0U;\r\n      hhcd->hc[ch_num].urb_state  = URB_NOTREADY;\r\n      __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);\r\n      (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);\r\n    }\r\n  }\r\n  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET)\r\n  {\r\n    hhcd->hc[ch_num].state = HC_NYET;\r\n    hhcd->hc[ch_num].do_ping = 1U;\r\n    hhcd->hc[ch_num].ErrCnt= 0U;\r\n    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);\r\n    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);\r\n    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET);\r\n  }\r\n  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR)\r\n  {\r\n    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);\r\n    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);\r\n    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR);\r\n  }\r\n  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC)\r\n  {\r\n    hhcd->hc[ch_num].ErrCnt = 0U;\r\n    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);\r\n    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);\r\n    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC);\r\n    hhcd->hc[ch_num].state = HC_XFRC;\r\n  }\r\n  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL)\r\n  {\r\n    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL);\r\n    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);\r\n    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);\r\n    hhcd->hc[ch_num].state = HC_STALL;\r\n  }\r\n  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK)\r\n  {\r\n    hhcd->hc[ch_num].ErrCnt = 0U;\r\n    hhcd->hc[ch_num].state = HC_NAK;\r\n\r\n    if (hhcd->hc[ch_num].do_ping == 0U)\r\n    {\r\n      if (hhcd->hc[ch_num].speed == HCD_SPEED_HIGH)\r\n      {\r\n        hhcd->hc[ch_num].do_ping = 1U;\r\n      }\r\n    }\r\n\r\n    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);\r\n    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);\r\n    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);\r\n  }\r\n  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR)\r\n  {\r\n    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);\r\n    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);\r\n    hhcd->hc[ch_num].state = HC_XACTERR;\r\n     __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);\r\n  }\r\n  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR)\r\n  {\r\n    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);\r\n    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);\r\n    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);\r\n    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR);\r\n    hhcd->hc[ch_num].state = HC_DATATGLERR;\r\n  }\r\n  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH)\r\n  {\r\n    __HAL_HCD_MASK_HALT_HC_INT(ch_num);\r\n\r\n    if (hhcd->hc[ch_num].state == HC_XFRC)\r\n    {\r\n      hhcd->hc[ch_num].urb_state  = URB_DONE;\r\n      if (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK)\r\n      {\r\n        hhcd->hc[ch_num].toggle_out ^= 1U;\r\n      }\r\n    }\r\n    else if (hhcd->hc[ch_num].state == HC_NAK)\r\n    {\r\n      hhcd->hc[ch_num].urb_state = URB_NOTREADY;\r\n    }\r\n    else if (hhcd->hc[ch_num].state == HC_NYET)\r\n    {\r\n      hhcd->hc[ch_num].urb_state  = URB_NOTREADY;\r\n    }\r\n    else if (hhcd->hc[ch_num].state == HC_STALL)\r\n    {\r\n      hhcd->hc[ch_num].urb_state  = URB_STALL;\r\n    }\r\n    else if ((hhcd->hc[ch_num].state == HC_XACTERR) ||\r\n            (hhcd->hc[ch_num].state == HC_DATATGLERR))\r\n    {\r\n      hhcd->hc[ch_num].ErrCnt++;\r\n      if (hhcd->hc[ch_num].ErrCnt > 3U)\r\n      {\r\n        hhcd->hc[ch_num].ErrCnt = 0U;\r\n        hhcd->hc[ch_num].urb_state = URB_ERROR;\r\n      }\r\n      else\r\n      {\r\n        hhcd->hc[ch_num].urb_state = URB_NOTREADY;\r\n      }\r\n\r\n      /* re-activate the channel  */\r\n      tmpreg = USBx_HC(ch_num)->HCCHAR;\r\n      tmpreg &= ~USB_OTG_HCCHAR_CHDIS;\r\n      tmpreg |= USB_OTG_HCCHAR_CHENA;\r\n      USBx_HC(ch_num)->HCCHAR = tmpreg;\r\n    }\r\n    else\r\n    {\r\n      /* ... */\r\n    }\r\n\r\n    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH);\r\n    HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);\r\n  }\r\n  else\r\n  {\r\n     /* ... */\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Handle Rx Queue Level interrupt requests.\r\n  * @param  hhcd HCD handle\r\n  * @retval none\r\n  */\r\nstatic void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd)\r\n{\r\n  USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n  uint32_t pktsts;\r\n  uint32_t pktcnt;\r\n  uint32_t temp;\r\n  uint32_t tmpreg;\r\n  uint32_t ch_num;\r\n\r\n  temp = hhcd->Instance->GRXSTSP;\r\n  ch_num = temp & USB_OTG_GRXSTSP_EPNUM;\r\n  pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17;\r\n  pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4;\r\n\r\n  switch (pktsts)\r\n  {\r\n  case GRXSTS_PKTSTS_IN:\r\n    /* Read the data into the host buffer. */\r\n    if ((pktcnt > 0U) && (hhcd->hc[ch_num].xfer_buff != (void  *)0))\r\n    {\r\n      (void)USB_ReadPacket(hhcd->Instance, hhcd->hc[ch_num].xfer_buff, (uint16_t)pktcnt);\r\n\r\n      /*manage multiple Xfer */\r\n      hhcd->hc[ch_num].xfer_buff += pktcnt;\r\n      hhcd->hc[ch_num].xfer_count  += pktcnt;\r\n\r\n      if((USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0U)\r\n      {\r\n        /* re-activate the channel when more packets are expected */\r\n        tmpreg = USBx_HC(ch_num)->HCCHAR;\r\n        tmpreg &= ~USB_OTG_HCCHAR_CHDIS;\r\n        tmpreg |= USB_OTG_HCCHAR_CHENA;\r\n        USBx_HC(ch_num)->HCCHAR = tmpreg;\r\n        hhcd->hc[ch_num].toggle_in ^= 1U;\r\n      }\r\n    }\r\n    break;\r\n\r\n  case GRXSTS_PKTSTS_DATA_TOGGLE_ERR:\r\n    break;\r\n\r\n  case GRXSTS_PKTSTS_IN_XFER_COMP:\r\n  case GRXSTS_PKTSTS_CH_HALTED:\r\n  default:\r\n    break;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Handle Host Port interrupt requests.\r\n  * @param  hhcd HCD handle\r\n  * @retval None\r\n  */\r\nstatic void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)\r\n{\r\n  USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n  __IO uint32_t hprt0, hprt0_dup;\r\n\r\n  /* Handle Host Port Interrupts */\r\n  hprt0 = USBx_HPRT0;\r\n  hprt0_dup = USBx_HPRT0;\r\n\r\n  hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\\\r\n                 USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);\r\n\r\n  /* Check whether Port Connect detected */\r\n  if((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET)\r\n  {\r\n    if((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)\r\n    {\r\n      USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);\r\n      HAL_HCD_Connect_Callback(hhcd);\r\n    }\r\n    hprt0_dup  |= USB_OTG_HPRT_PCDET;\r\n  }\r\n\r\n  /* Check whether Port Enable Changed */\r\n  if((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG)\r\n  {\r\n    hprt0_dup |= USB_OTG_HPRT_PENCHNG;\r\n\r\n    if((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA)\r\n    {\r\n      if(hhcd->Init.phy_itface  == USB_OTG_EMBEDDED_PHY)\r\n      {\r\n        if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17))\r\n        {\r\n          (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_6_MHZ);\r\n        }\r\n        else\r\n        {\r\n          (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);\r\n        }\r\n      }\r\n      else\r\n      {\r\n        if(hhcd->Init.speed == HCD_SPEED_FULL)\r\n        {\r\n          USBx_HOST->HFIR = 60000U;\r\n        }\r\n      }\r\n\r\n      HAL_HCD_PortEnabled_Callback(hhcd);\r\n      HAL_HCD_Connect_Callback(hhcd);\r\n    }\r\n    else\r\n    {\r\n      HAL_HCD_PortDisabled_Callback(hhcd);\r\n\r\n      /* Cleanup HPRT */\r\n      USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\\\r\n        USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );\r\n\r\n      USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);\r\n    }\r\n  }\r\n\r\n  /* Check for an overcurrent */\r\n  if((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG)\r\n  {\r\n    hprt0_dup |= USB_OTG_HPRT_POCCHNG;\r\n  }\r\n\r\n  /* Clear Port Interrupts */\r\n  USBx_HPRT0 = hprt0_dup;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_HCD_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_i2c.c\r\n  * @author  MCD Application Team\r\n  * @brief   I2C HAL module driver.\r\n  *          This file provides firmware functions to manage the following\r\n  *          functionalities of the Inter Integrated Circuit (I2C) peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + IO operation functions\r\n  *           + Peripheral State and Errors functions\r\n  *\r\n  @verbatim\r\n  ==============================================================================\r\n                        ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]\r\n    The I2C HAL driver can be used as follows:\r\n\r\n    (#) Declare a I2C_HandleTypeDef handle structure, for example:\r\n        I2C_HandleTypeDef  hi2c;\r\n\r\n    (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:\r\n        (##) Enable the I2Cx interface clock\r\n        (##) I2C pins configuration\r\n            (+++) Enable the clock for the I2C GPIOs\r\n            (+++) Configure I2C pins as alternate function open-drain\r\n        (##) NVIC configuration if you need to use interrupt process\r\n            (+++) Configure the I2Cx interrupt priority\r\n            (+++) Enable the NVIC I2C IRQ Channel\r\n        (##) DMA Configuration if you need to use DMA process\r\n            (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream\r\n            (+++) Enable the DMAx interface clock using\r\n            (+++) Configure the DMA handle parameters\r\n            (+++) Configure the DMA Tx or Rx stream\r\n            (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle\r\n            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on\r\n                  the DMA Tx or Rx stream\r\n\r\n    (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,\r\n        Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.\r\n\r\n    (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware\r\n        (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.\r\n\r\n    (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()\r\n\r\n    (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :\r\n\r\n    *** Polling mode IO operation ***\r\n    =================================\r\n    [..]\r\n      (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()\r\n      (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()\r\n      (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()\r\n      (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()\r\n\r\n    *** Polling mode IO MEM operation ***\r\n    =====================================\r\n    [..]\r\n      (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()\r\n      (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()\r\n\r\n\r\n    *** Interrupt mode IO operation ***\r\n    ===================================\r\n    [..]\r\n      (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()\r\n      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()\r\n      (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()\r\n      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()\r\n      (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()\r\n      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()\r\n      (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()\r\n      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()\r\n      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_ErrorCallback()\r\n      (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()\r\n      (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()\r\n      (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.\r\n           This action will inform Master to generate a Stop condition to discard the communication.\r\n\r\n\r\n    *** Interrupt mode IO sequential operation ***\r\n    ==============================================\r\n    [..]\r\n      (@) These interfaces allow to manage a sequential transfer with a repeated start condition\r\n          when a direction change during transfer\r\n    [..]\r\n      (+) A specific option field manage the different steps of a sequential transfer\r\n      (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:\r\n      (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode\r\n      (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address\r\n                            and data to transfer without a final stop condition\r\n      (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address\r\n                            and data to transfer without a final stop condition, an then permit a call the same master sequential interface\r\n                            several times (like HAL_I2C_Master_Sequential_Transmit_IT() then HAL_I2C_Master_Sequential_Transmit_IT())\r\n      (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address\r\n                            and with new data to transfer if the direction change or manage only the new data to transfer\r\n                            if no direction change and without a final stop condition in both cases\r\n      (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address\r\n                            and with new data to transfer if the direction change or manage only the new data to transfer\r\n                            if no direction change and with a final stop condition in both cases\r\n      (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential\r\n                            interface several times (link with option I2C_FIRST_AND_NEXT_FRAME).\r\n                            Usage can, transfer several bytes one by one using HAL_I2C_Master_Sequential_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)\r\n                              or HAL_I2C_Master_Sequential_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).\r\n                            Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit\r\n                              without stopping the communication and so generate a restart condition.\r\n\r\n      (+) Differents sequential I2C interfaces are listed below:\r\n      (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()\r\n      (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()\r\n      (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()\r\n      (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()\r\n      (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()\r\n      (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()\r\n      (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()\r\n      (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can\r\n           add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).\r\n      (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()\r\n      (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()\r\n      (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()\r\n      (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()\r\n      (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()\r\n      (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_ErrorCallback()\r\n      (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()\r\n      (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()\r\n      (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.\r\n           This action will inform Master to generate a Stop condition to discard the communication.\r\n\r\n    *** Interrupt mode IO MEM operation ***\r\n    =======================================\r\n    [..]\r\n      (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using\r\n          HAL_I2C_Mem_Write_IT()\r\n      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()\r\n      (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using\r\n          HAL_I2C_Mem_Read_IT()\r\n      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()\r\n      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_ErrorCallback()\r\n\r\n    *** DMA mode IO operation ***\r\n    ==============================\r\n    [..]\r\n      (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using\r\n          HAL_I2C_Master_Transmit_DMA()\r\n      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()\r\n      (+) Receive in master mode an amount of data in non-blocking mode (DMA) using\r\n          HAL_I2C_Master_Receive_DMA()\r\n      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()\r\n      (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using\r\n          HAL_I2C_Slave_Transmit_DMA()\r\n      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()\r\n      (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using\r\n          HAL_I2C_Slave_Receive_DMA()\r\n      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()\r\n      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_ErrorCallback()\r\n      (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()\r\n      (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()\r\n      (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.\r\n           This action will inform Master to generate a Stop condition to discard the communication.\r\n\r\n    *** DMA mode IO MEM operation ***\r\n    =================================\r\n    [..]\r\n      (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using\r\n          HAL_I2C_Mem_Write_DMA()\r\n      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()\r\n      (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using\r\n          HAL_I2C_Mem_Read_DMA()\r\n      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()\r\n      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_ErrorCallback()\r\n\r\n\r\n     *** I2C HAL driver macros list ***\r\n     ==================================\r\n     [..]\r\n       Below the list of most used macros in I2C HAL driver.\r\n\r\n      (+) __HAL_I2C_ENABLE: Enable the I2C peripheral\r\n      (+) __HAL_I2C_DISABLE: Disable the I2C peripheral\r\n      (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode\r\n      (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not\r\n      (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag\r\n      (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt\r\n      (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt\r\n\r\n     [..]\r\n       (@) You can refer to the I2C HAL driver header file for more useful macros\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup I2C I2C\r\n  * @brief I2C HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_I2C_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n\r\n/** @defgroup I2C_Private_Define I2C Private Define\r\n  * @{\r\n  */\r\n#define TIMING_CLEAR_MASK   (0xF0FFFFFFU)  /*!< I2C TIMING clear register Mask */\r\n#define I2C_TIMEOUT_ADDR    (10000U)       /*!< 10 s  */\r\n#define I2C_TIMEOUT_BUSY    (25U)          /*!< 25 ms */\r\n#define I2C_TIMEOUT_DIR     (25U)          /*!< 25 ms */\r\n#define I2C_TIMEOUT_RXNE    (25U)          /*!< 25 ms */\r\n#define I2C_TIMEOUT_STOPF   (25U)          /*!< 25 ms */\r\n#define I2C_TIMEOUT_TC      (25U)          /*!< 25 ms */\r\n#define I2C_TIMEOUT_TCR     (25U)          /*!< 25 ms */\r\n#define I2C_TIMEOUT_TXIS    (25U)          /*!< 25 ms */\r\n#define I2C_TIMEOUT_FLAG    (25U)          /*!< 25 ms */\r\n\r\n#define MAX_NBYTE_SIZE      255U\r\n#define SlaveAddr_SHIFT     7U\r\n#define SlaveAddr_MSK       0x06U\r\n\r\n/* Private define for @ref PreviousState usage */\r\n#define I2C_STATE_MSK             ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits            */\r\n#define I2C_STATE_NONE            ((uint32_t)(HAL_I2C_MODE_NONE))                                                        /*!< Default Value                                          */\r\n#define I2C_STATE_MASTER_BUSY_TX  ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))            /*!< Master Busy TX, combinaison of State LSB and Mode enum */\r\n#define I2C_STATE_MASTER_BUSY_RX  ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))            /*!< Master Busy RX, combinaison of State LSB and Mode enum */\r\n#define I2C_STATE_SLAVE_BUSY_TX   ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))             /*!< Slave Busy TX, combinaison of State LSB and Mode enum  */\r\n#define I2C_STATE_SLAVE_BUSY_RX   ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))             /*!< Slave Busy RX, combinaison of State LSB and Mode enum  */\r\n#define I2C_STATE_MEM_BUSY_TX     ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))               /*!< Memory Busy TX, combinaison of State LSB and Mode enum */\r\n#define I2C_STATE_MEM_BUSY_RX     ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))               /*!< Memory Busy RX, combinaison of State LSB and Mode enum */\r\n\r\n\r\n/* Private define to centralize the enable/disable of Interrupts */\r\n#define I2C_XFER_TX_IT          (0x00000001U)\r\n#define I2C_XFER_RX_IT          (0x00000002U)\r\n#define I2C_XFER_LISTEN_IT      (0x00000004U)\r\n\r\n#define I2C_XFER_ERROR_IT       (0x00000011U)\r\n#define I2C_XFER_CPLT_IT        (0x00000012U)\r\n#define I2C_XFER_RELOAD_IT      (0x00000012U)\r\n\r\n/* Private define Sequential Transfer Options default/reset value */\r\n#define I2C_NO_OPTION_FRAME     (0xFFFF0000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX)   ? \\\r\n                                              ((uint32_t)(((DMA_Stream_TypeDef *)(__HANDLE__)->hdmatx->Instance)->NDTR)) :  \\\r\n                                              ((uint32_t)(((DMA_Stream_TypeDef *)(__HANDLE__)->hdmarx->Instance)->NDTR)))\r\n\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n\r\n/** @defgroup I2C_Private_Functions I2C Private Functions\r\n  * @{\r\n  */\r\n/* Private functions to handle DMA transfer */\r\nstatic void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);\r\nstatic void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);\r\nstatic void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);\r\nstatic void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);\r\nstatic void I2C_DMAError(DMA_HandleTypeDef *hdma);\r\nstatic void I2C_DMAAbort(DMA_HandleTypeDef *hdma);\r\n\r\n/* Private functions to handle IT transfer */\r\nstatic void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);\r\nstatic void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c);\r\nstatic void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c);\r\nstatic void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);\r\nstatic void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);\r\nstatic void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);\r\nstatic void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);\r\n\r\n/* Private functions to handle IT transfer */\r\nstatic HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);\r\nstatic HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);\r\n\r\n/* Private functions for I2C transfer IRQ handler */\r\nstatic HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);\r\nstatic HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);\r\nstatic HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);\r\nstatic HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);\r\n\r\n/* Private functions to handle flags during polling transfer */\r\nstatic HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);\r\nstatic HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);\r\nstatic HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);\r\nstatic HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);\r\nstatic HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);\r\n\r\n/* Private functions to centralize the enable/disable of Interrupts */\r\nstatic HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);\r\nstatic HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);\r\n\r\n/* Private functions to flush TXDR register */\r\nstatic void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);\r\n\r\n/* Private functions to handle  start, restart or stop a transfer */\r\nstatic void I2C_TransferConfig(I2C_HandleTypeDef *hi2c,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @defgroup I2C_Exported_Functions I2C Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions\r\n *  @brief    Initialization and Configuration functions\r\n *\r\n@verbatim\r\n ===============================================================================\r\n              ##### Initialization and de-initialization functions #####\r\n ===============================================================================\r\n    [..]  This subsection provides a set of functions allowing to initialize and\r\n          deinitialize the I2Cx peripheral:\r\n\r\n      (+) User must Implement HAL_I2C_MspInit() function in which he configures\r\n          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).\r\n\r\n      (+) Call the function HAL_I2C_Init() to configure the selected device with\r\n          the selected configuration:\r\n        (++) Clock Timing\r\n        (++) Own Address 1\r\n        (++) Addressing mode (Master, Slave)\r\n        (++) Dual Addressing mode\r\n        (++) Own Address 2\r\n        (++) Own Address 2 Mask\r\n        (++) General call mode\r\n        (++) Nostretch mode\r\n\r\n      (+) Call the function HAL_I2C_DeInit() to restore the default configuration\r\n          of the selected I2Cx peripheral.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the I2C according to the specified parameters\r\n  *         in the I2C_InitTypeDef and initialize the associated handle.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* Check the I2C handle allocation */\r\n  if (hi2c == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\r\n  assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));\r\n  assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));\r\n  assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));\r\n  assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));\r\n  assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));\r\n  assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));\r\n  assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));\r\n\r\n  if (hi2c->State == HAL_I2C_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    hi2c->Lock = HAL_UNLOCKED;\r\n\r\n    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */\r\n    HAL_I2C_MspInit(hi2c);\r\n  }\r\n\r\n  hi2c->State = HAL_I2C_STATE_BUSY;\r\n\r\n  /* Disable the selected I2C peripheral */\r\n  __HAL_I2C_DISABLE(hi2c);\r\n\r\n  /*---------------------------- I2Cx TIMINGR Configuration ------------------*/\r\n  /* Configure I2Cx: Frequency range */\r\n  hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;\r\n\r\n  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/\r\n  /* Disable Own Address1 before set the Own Address1 configuration */\r\n  hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;\r\n\r\n  /* Configure I2Cx: Own Address1 and ack own address1 mode */\r\n  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)\r\n  {\r\n    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);\r\n  }\r\n  else /* I2C_ADDRESSINGMODE_10BIT */\r\n  {\r\n    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);\r\n  }\r\n\r\n  /*---------------------------- I2Cx CR2 Configuration ----------------------*/\r\n  /* Configure I2Cx: Addressing Master mode */\r\n  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)\r\n  {\r\n    hi2c->Instance->CR2 = (I2C_CR2_ADD10);\r\n  }\r\n  /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */\r\n  hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);\r\n\r\n  /*---------------------------- I2Cx OAR2 Configuration ---------------------*/\r\n  /* Disable Own Address2 before set the Own Address2 configuration */\r\n  hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;\r\n\r\n  /* Configure I2Cx: Dual mode and Own Address2 */\r\n  hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));\r\n\r\n  /*---------------------------- I2Cx CR1 Configuration ----------------------*/\r\n  /* Configure I2Cx: Generalcall and NoStretch mode */\r\n  hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);\r\n\r\n  /* Enable the selected I2C peripheral */\r\n  __HAL_I2C_ENABLE(hi2c);\r\n\r\n  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r\n  hi2c->State = HAL_I2C_STATE_READY;\r\n  hi2c->PreviousState = I2C_STATE_NONE;\r\n  hi2c->Mode = HAL_I2C_MODE_NONE;\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  DeInitialize the I2C peripheral.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* Check the I2C handle allocation */\r\n  if (hi2c == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\r\n\r\n  hi2c->State = HAL_I2C_STATE_BUSY;\r\n\r\n  /* Disable the I2C Peripheral Clock */\r\n  __HAL_I2C_DISABLE(hi2c);\r\n\r\n  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r\n  HAL_I2C_MspDeInit(hi2c);\r\n\r\n  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r\n  hi2c->State = HAL_I2C_STATE_RESET;\r\n  hi2c->PreviousState = I2C_STATE_NONE;\r\n  hi2c->Mode = HAL_I2C_MODE_NONE;\r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hi2c);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Initialize the I2C MSP.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @retval None\r\n  */\r\n__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2c);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_I2C_MspInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief DeInitialize the I2C MSP.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @retval None\r\n  */\r\n__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2c);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_I2C_MspDeInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions\r\n *  @brief   Data transfers functions\r\n *\r\n@verbatim\r\n ===============================================================================\r\n                      ##### IO operation functions #####\r\n ===============================================================================\r\n    [..]\r\n    This subsection provides a set of functions allowing to manage the I2C data\r\n    transfers.\r\n\r\n    (#) There are two modes of transfer:\r\n       (++) Blocking mode : The communication is performed in the polling mode.\r\n            The status of all data processing is returned by the same function\r\n            after finishing transfer.\r\n       (++) No-Blocking mode : The communication is performed using Interrupts\r\n            or DMA. These functions return the status of the transfer startup.\r\n            The end of the data processing will be indicated through the\r\n            dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when\r\n            using DMA mode.\r\n\r\n    (#) Blocking mode functions are :\r\n        (++) HAL_I2C_Master_Transmit()\r\n        (++) HAL_I2C_Master_Receive()\r\n        (++) HAL_I2C_Slave_Transmit()\r\n        (++) HAL_I2C_Slave_Receive()\r\n        (++) HAL_I2C_Mem_Write()\r\n        (++) HAL_I2C_Mem_Read()\r\n        (++) HAL_I2C_IsDeviceReady()\r\n\r\n    (#) No-Blocking mode functions with Interrupt are :\r\n        (++) HAL_I2C_Master_Transmit_IT()\r\n        (++) HAL_I2C_Master_Receive_IT()\r\n        (++) HAL_I2C_Slave_Transmit_IT()\r\n        (++) HAL_I2C_Slave_Receive_IT()\r\n        (++) HAL_I2C_Mem_Write_IT()\r\n        (++) HAL_I2C_Mem_Read_IT()\r\n\r\n    (#) No-Blocking mode functions with DMA are :\r\n        (++) HAL_I2C_Master_Transmit_DMA()\r\n        (++) HAL_I2C_Master_Receive_DMA()\r\n        (++) HAL_I2C_Slave_Transmit_DMA()\r\n        (++) HAL_I2C_Slave_Receive_DMA()\r\n        (++) HAL_I2C_Mem_Write_DMA()\r\n        (++) HAL_I2C_Mem_Read_DMA()\r\n\r\n    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:\r\n        (++) HAL_I2C_MemTxCpltCallback()\r\n        (++) HAL_I2C_MemRxCpltCallback()\r\n        (++) HAL_I2C_MasterTxCpltCallback()\r\n        (++) HAL_I2C_MasterRxCpltCallback()\r\n        (++) HAL_I2C_SlaveTxCpltCallback()\r\n        (++) HAL_I2C_SlaveRxCpltCallback()\r\n        (++) HAL_I2C_ErrorCallback()\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Transmits in master mode an amount of data in blocking mode.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  DevAddress Target device address which contain device 7 or 10 bits address value\r\n  *         in datasheet must be shifted to the left before calling the interface\r\n  * @param  pData Pointer to data buffer\r\n  * @param  Size Amount of data to be sent\r\n  * @param  Timeout Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0U;\r\n\r\n  if (hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n\r\n    /* Init tickstart for timeout management*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n\r\n    hi2c->State     = HAL_I2C_STATE_BUSY_TX;\r\n    hi2c->Mode      = HAL_I2C_MODE_MASTER;\r\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r\n\r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr  = pData;\r\n    hi2c->XferCount = Size;\r\n    hi2c->XferISR   = NULL;\r\n\r\n    /* Send Slave Address */\r\n    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r\n    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r\n    {\r\n      hi2c->XferSize = MAX_NBYTE_SIZE;\r\n      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);\r\n    }\r\n    else\r\n    {\r\n      hi2c->XferSize = hi2c->XferCount;\r\n      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);\r\n    }\r\n\r\n    while (hi2c->XferCount > 0U)\r\n    {\r\n      /* Wait until TXIS flag is set */\r\n      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r\n      {\r\n        if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n        {\r\n          return HAL_ERROR;\r\n        }\r\n        else\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n      /* Write data to TXDR */\r\n      hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);\r\n      hi2c->XferCount--;\r\n      hi2c->XferSize--;\r\n\r\n      if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))\r\n      {\r\n        /* Wait until TCR flag is set */\r\n        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n\r\n        if (hi2c->XferCount > MAX_NBYTE_SIZE)\r\n        {\r\n          hi2c->XferSize = MAX_NBYTE_SIZE;\r\n          I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r\n        }\r\n        else\r\n        {\r\n          hi2c->XferSize = hi2c->XferCount;\r\n          I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r\n        }\r\n      }\r\n    }\r\n\r\n    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r\n    /* Wait until STOPF flag is set */\r\n    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r\n    {\r\n      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n      {\r\n        return HAL_ERROR;\r\n      }\r\n      else\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n\r\n    /* Clear STOP Flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r\n\r\n    /* Clear Configuration Register 2 */\r\n    I2C_RESET_CR2(hi2c);\r\n\r\n    hi2c->State = HAL_I2C_STATE_READY;\r\n    hi2c->Mode  = HAL_I2C_MODE_NONE;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Receives in master mode an amount of data in blocking mode.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  DevAddress Target device address which contain device 7 or 10 bits address value\r\n  *         in datasheet must be shifted to the left before calling the interface\r\n  * @param  pData Pointer to data buffer\r\n  * @param  Size Amount of data to be sent\r\n  * @param  Timeout Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0U;\r\n\r\n  if (hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n\r\n    /* Init tickstart for timeout management*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n\r\n    hi2c->State     = HAL_I2C_STATE_BUSY_RX;\r\n    hi2c->Mode      = HAL_I2C_MODE_MASTER;\r\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r\n\r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr  = pData;\r\n    hi2c->XferCount = Size;\r\n    hi2c->XferISR   = NULL;\r\n\r\n    /* Send Slave Address */\r\n    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r\n    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r\n    {\r\n      hi2c->XferSize = MAX_NBYTE_SIZE;\r\n      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);\r\n    }\r\n    else\r\n    {\r\n      hi2c->XferSize = hi2c->XferCount;\r\n      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);\r\n    }\r\n\r\n    while (hi2c->XferCount > 0U)\r\n    {\r\n      /* Wait until RXNE flag is set */\r\n      if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r\n      {\r\n        if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n        {\r\n          return HAL_ERROR;\r\n        }\r\n        else\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n\r\n      /* Read data from RXDR */\r\n      (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;\r\n      hi2c->XferSize--;\r\n      hi2c->XferCount--;\r\n\r\n      if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))\r\n      {\r\n        /* Wait until TCR flag is set */\r\n        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n\r\n        if (hi2c->XferCount > MAX_NBYTE_SIZE)\r\n        {\r\n          hi2c->XferSize = MAX_NBYTE_SIZE;\r\n          I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r\n        }\r\n        else\r\n        {\r\n          hi2c->XferSize = hi2c->XferCount;\r\n          I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r\n        }\r\n      }\r\n    }\r\n\r\n    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r\n    /* Wait until STOPF flag is set */\r\n    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r\n    {\r\n      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n      {\r\n        return HAL_ERROR;\r\n      }\r\n      else\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n\r\n    /* Clear STOP Flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r\n\r\n    /* Clear Configuration Register 2 */\r\n    I2C_RESET_CR2(hi2c);\r\n\r\n    hi2c->State = HAL_I2C_STATE_READY;\r\n    hi2c->Mode  = HAL_I2C_MODE_NONE;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Transmits in slave mode an amount of data in blocking mode.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  pData Pointer to data buffer\r\n  * @param  Size Amount of data to be sent\r\n  * @param  Timeout Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0U;\r\n\r\n  if (hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    if ((pData == NULL) || (Size == 0U))\r\n    {\r\n      return  HAL_ERROR;\r\n    }\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n\r\n    /* Init tickstart for timeout management*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    hi2c->State     = HAL_I2C_STATE_BUSY_TX;\r\n    hi2c->Mode      = HAL_I2C_MODE_SLAVE;\r\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r\n\r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr  = pData;\r\n    hi2c->XferCount = Size;\r\n    hi2c->XferISR   = NULL;\r\n\r\n    /* Enable Address Acknowledge */\r\n    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r\n\r\n    /* Wait until ADDR flag is set */\r\n    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)\r\n    {\r\n      /* Disable Address Acknowledge */\r\n      hi2c->Instance->CR2 |= I2C_CR2_NACK;\r\n      return HAL_TIMEOUT;\r\n    }\r\n\r\n    /* Clear ADDR flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r\n\r\n    /* If 10bit addressing mode is selected */\r\n    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)\r\n    {\r\n      /* Wait until ADDR flag is set */\r\n      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)\r\n      {\r\n        /* Disable Address Acknowledge */\r\n        hi2c->Instance->CR2 |= I2C_CR2_NACK;\r\n        return HAL_TIMEOUT;\r\n      }\r\n\r\n      /* Clear ADDR flag */\r\n      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r\n    }\r\n\r\n    /* Wait until DIR flag is set Transmitter mode */\r\n    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)\r\n    {\r\n      /* Disable Address Acknowledge */\r\n      hi2c->Instance->CR2 |= I2C_CR2_NACK;\r\n      return HAL_TIMEOUT;\r\n    }\r\n\r\n    while (hi2c->XferCount > 0U)\r\n    {\r\n      /* Wait until TXIS flag is set */\r\n      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r\n      {\r\n        /* Disable Address Acknowledge */\r\n        hi2c->Instance->CR2 |= I2C_CR2_NACK;\r\n\r\n        if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n        {\r\n          return HAL_ERROR;\r\n        }\r\n        else\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n\r\n      /* Write data to TXDR */\r\n      hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);\r\n      hi2c->XferCount--;\r\n    }\r\n\r\n    /* Wait until STOP flag is set */\r\n    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r\n    {\r\n      /* Disable Address Acknowledge */\r\n      hi2c->Instance->CR2 |= I2C_CR2_NACK;\r\n\r\n      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n      {\r\n        /* Normal use case for Transmitter mode */\r\n        /* A NACK is generated to confirm the end of transfer */\r\n        hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r\n      }\r\n      else\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n\r\n    /* Clear STOP flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r\n\r\n    /* Wait until BUSY flag is reset */\r\n    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)\r\n    {\r\n      /* Disable Address Acknowledge */\r\n      hi2c->Instance->CR2 |= I2C_CR2_NACK;\r\n      return HAL_TIMEOUT;\r\n    }\r\n\r\n    /* Disable Address Acknowledge */\r\n    hi2c->Instance->CR2 |= I2C_CR2_NACK;\r\n\r\n    hi2c->State = HAL_I2C_STATE_READY;\r\n    hi2c->Mode  = HAL_I2C_MODE_NONE;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Receive in slave mode an amount of data in blocking mode\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  pData Pointer to data buffer\r\n  * @param  Size Amount of data to be sent\r\n  * @param  Timeout Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0U;\r\n\r\n  if (hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    if ((pData == NULL) || (Size == 0U))\r\n    {\r\n      return  HAL_ERROR;\r\n    }\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n\r\n    /* Init tickstart for timeout management*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    hi2c->State     = HAL_I2C_STATE_BUSY_RX;\r\n    hi2c->Mode      = HAL_I2C_MODE_SLAVE;\r\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r\n\r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr  = pData;\r\n    hi2c->XferCount = Size;\r\n    hi2c->XferISR   = NULL;\r\n\r\n    /* Enable Address Acknowledge */\r\n    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r\n\r\n    /* Wait until ADDR flag is set */\r\n    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)\r\n    {\r\n      /* Disable Address Acknowledge */\r\n      hi2c->Instance->CR2 |= I2C_CR2_NACK;\r\n      return HAL_TIMEOUT;\r\n    }\r\n\r\n    /* Clear ADDR flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r\n\r\n    /* Wait until DIR flag is reset Receiver mode */\r\n    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)\r\n    {\r\n      /* Disable Address Acknowledge */\r\n      hi2c->Instance->CR2 |= I2C_CR2_NACK;\r\n      return HAL_TIMEOUT;\r\n    }\r\n\r\n    while (hi2c->XferCount > 0U)\r\n    {\r\n      /* Wait until RXNE flag is set */\r\n      if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r\n      {\r\n        /* Disable Address Acknowledge */\r\n        hi2c->Instance->CR2 |= I2C_CR2_NACK;\r\n\r\n        /* Store Last receive data if any */\r\n        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)\r\n        {\r\n          /* Read data from RXDR */\r\n          (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;\r\n          hi2c->XferCount--;\r\n        }\r\n\r\n        if (hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n        else\r\n        {\r\n          return HAL_ERROR;\r\n        }\r\n      }\r\n\r\n      /* Read data from RXDR */\r\n      (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;\r\n      hi2c->XferCount--;\r\n    }\r\n\r\n    /* Wait until STOP flag is set */\r\n    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r\n    {\r\n      /* Disable Address Acknowledge */\r\n      hi2c->Instance->CR2 |= I2C_CR2_NACK;\r\n\r\n      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n      {\r\n        return HAL_ERROR;\r\n      }\r\n      else\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n\r\n    /* Clear STOP flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r\n\r\n    /* Wait until BUSY flag is reset */\r\n    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)\r\n    {\r\n      /* Disable Address Acknowledge */\r\n      hi2c->Instance->CR2 |= I2C_CR2_NACK;\r\n      return HAL_TIMEOUT;\r\n    }\r\n\r\n    /* Disable Address Acknowledge */\r\n    hi2c->Instance->CR2 |= I2C_CR2_NACK;\r\n\r\n    hi2c->State = HAL_I2C_STATE_READY;\r\n    hi2c->Mode  = HAL_I2C_MODE_NONE;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Transmit in master mode an amount of data in non-blocking mode with Interrupt\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  DevAddress Target device address which contain device 7 or 10 bits address value\r\n  *         in datasheet must be shifted to the left before calling the interface\r\n  * @param  pData Pointer to data buffer\r\n  * @param  Size Amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)\r\n{\r\n  uint32_t xfermode = 0U;\r\n\r\n  if (hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r\n    {\r\n      return HAL_BUSY;\r\n    }\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n\r\n    hi2c->State       = HAL_I2C_STATE_BUSY_TX;\r\n    hi2c->Mode        = HAL_I2C_MODE_MASTER;\r\n    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r\n\r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr    = pData;\r\n    hi2c->XferCount   = Size;\r\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r\n    hi2c->XferISR     = I2C_Master_ISR_IT;\r\n\r\n    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r\n    {\r\n      hi2c->XferSize = MAX_NBYTE_SIZE;\r\n      xfermode = I2C_RELOAD_MODE;\r\n    }\r\n    else\r\n    {\r\n      hi2c->XferSize = hi2c->XferCount;\r\n      xfermode = I2C_AUTOEND_MODE;\r\n    }\r\n\r\n    /* Send Slave Address */\r\n    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */\r\n    I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    /* Note : The I2C interrupts must be enabled after unlocking current process\r\n              to avoid the risk of I2C interrupt handle execution before current\r\n              process unlock */\r\n\r\n    /* Enable ERR, TC, STOP, NACK, TXI interrupt */\r\n    /* possible to enable all of these */\r\n    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Receive in master mode an amount of data in non-blocking mode with Interrupt\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  DevAddress Target device address which contain device 7 or 10 bits address value\r\n  *         in datasheet must be shifted to the left before calling the interface\r\n  * @param  pData Pointer to data buffer\r\n  * @param  Size Amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)\r\n{\r\n  uint32_t xfermode = 0U;\r\n\r\n  if (hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r\n    {\r\n      return HAL_BUSY;\r\n    }\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n\r\n    hi2c->State       = HAL_I2C_STATE_BUSY_RX;\r\n    hi2c->Mode        = HAL_I2C_MODE_MASTER;\r\n    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r\n\r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr    = pData;\r\n    hi2c->XferCount   = Size;\r\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r\n    hi2c->XferISR     = I2C_Master_ISR_IT;\r\n\r\n    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r\n    {\r\n      hi2c->XferSize = MAX_NBYTE_SIZE;\r\n      xfermode = I2C_RELOAD_MODE;\r\n    }\r\n    else\r\n    {\r\n      hi2c->XferSize = hi2c->XferCount;\r\n      xfermode = I2C_AUTOEND_MODE;\r\n    }\r\n\r\n    /* Send Slave Address */\r\n    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */\r\n    I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    /* Note : The I2C interrupts must be enabled after unlocking current process\r\n              to avoid the risk of I2C interrupt handle execution before current\r\n              process unlock */\r\n\r\n    /* Enable ERR, TC, STOP, NACK, RXI interrupt */\r\n    /* possible to enable all of these */\r\n    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Transmit in slave mode an amount of data in non-blocking mode with Interrupt\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  pData Pointer to data buffer\r\n  * @param  Size Amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)\r\n{\r\n  if (hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n\r\n    hi2c->State       = HAL_I2C_STATE_BUSY_TX;\r\n    hi2c->Mode        = HAL_I2C_MODE_SLAVE;\r\n    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r\n\r\n    /* Enable Address Acknowledge */\r\n    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r\n\r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr    = pData;\r\n    hi2c->XferCount   = Size;\r\n    hi2c->XferSize    = hi2c->XferCount;\r\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r\n    hi2c->XferISR     = I2C_Slave_ISR_IT;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    /* Note : The I2C interrupts must be enabled after unlocking current process\r\n              to avoid the risk of I2C interrupt handle execution before current\r\n              process unlock */\r\n\r\n    /* Enable ERR, TC, STOP, NACK, TXI interrupt */\r\n    /* possible to enable all of these */\r\n    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  pData Pointer to data buffer\r\n  * @param  Size Amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)\r\n{\r\n  if (hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n\r\n    hi2c->State       = HAL_I2C_STATE_BUSY_RX;\r\n    hi2c->Mode        = HAL_I2C_MODE_SLAVE;\r\n    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r\n\r\n    /* Enable Address Acknowledge */\r\n    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r\n\r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr    = pData;\r\n    hi2c->XferCount   = Size;\r\n    hi2c->XferSize    = hi2c->XferCount;\r\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r\n    hi2c->XferISR     = I2C_Slave_ISR_IT;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    /* Note : The I2C interrupts must be enabled after unlocking current process\r\n              to avoid the risk of I2C interrupt handle execution before current\r\n              process unlock */\r\n\r\n    /* Enable ERR, TC, STOP, NACK, RXI interrupt */\r\n    /* possible to enable all of these */\r\n    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Transmit in master mode an amount of data in non-blocking mode with DMA\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  DevAddress Target device address which contain device 7 or 10 bits address value\r\n  *         in datasheet must be shifted to the left before calling the interface\r\n  * @param  pData Pointer to data buffer\r\n  * @param  Size Amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)\r\n{\r\n  uint32_t xfermode = 0U;\r\n\r\n  if (hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r\n    {\r\n      return HAL_BUSY;\r\n    }\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n\r\n    hi2c->State       = HAL_I2C_STATE_BUSY_TX;\r\n    hi2c->Mode        = HAL_I2C_MODE_MASTER;\r\n    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r\n\r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr    = pData;\r\n    hi2c->XferCount   = Size;\r\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r\n    hi2c->XferISR     = I2C_Master_ISR_DMA;\r\n\r\n    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r\n    {\r\n      hi2c->XferSize = MAX_NBYTE_SIZE;\r\n      xfermode = I2C_RELOAD_MODE;\r\n    }\r\n    else\r\n    {\r\n      hi2c->XferSize = hi2c->XferCount;\r\n      xfermode = I2C_AUTOEND_MODE;\r\n    }\r\n\r\n    if (hi2c->XferSize > 0U)\r\n    {\r\n      /* Set the I2C DMA transfer complete callback */\r\n      hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;\r\n\r\n      /* Set the DMA error callback */\r\n      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;\r\n\r\n      /* Set the unused DMA callbacks to NULL */\r\n      hi2c->hdmatx->XferHalfCpltCallback = NULL;\r\n      hi2c->hdmatx->XferAbortCallback = NULL;\r\n\r\n      /* Enable the DMA stream */\r\n      HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);\r\n\r\n      /* Send Slave Address */\r\n      /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r\n      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);\r\n\r\n      /* Update XferCount value */\r\n      hi2c->XferCount -= hi2c->XferSize;\r\n\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hi2c);\r\n\r\n      /* Note : The I2C interrupts must be enabled after unlocking current process\r\n                to avoid the risk of I2C interrupt handle execution before current\r\n                process unlock */\r\n      /* Enable ERR and NACK interrupts */\r\n      I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);\r\n\r\n      /* Enable DMA Request */\r\n      hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;\r\n    }\r\n    else\r\n    {\r\n      /* Update Transfer ISR function pointer */\r\n      hi2c->XferISR = I2C_Master_ISR_IT;\r\n\r\n      /* Send Slave Address */\r\n      /* Set NBYTES to write and generate START condition */\r\n      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);\r\n\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hi2c);\r\n\r\n      /* Note : The I2C interrupts must be enabled after unlocking current process\r\n                to avoid the risk of I2C interrupt handle execution before current\r\n                process unlock */\r\n      /* Enable ERR, TC, STOP, NACK, TXI interrupt */\r\n      /* possible to enable all of these */\r\n      /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r\n      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);\r\n    }\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Receive in master mode an amount of data in non-blocking mode with DMA\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  DevAddress Target device address which contain device 7 or 10 bits address value\r\n  *         in datasheet must be shifted to the left before calling the interface\r\n  * @param  pData Pointer to data buffer\r\n  * @param  Size Amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)\r\n{\r\n  uint32_t xfermode = 0U;\r\n\r\n  if (hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r\n    {\r\n      return HAL_BUSY;\r\n    }\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n\r\n    hi2c->State       = HAL_I2C_STATE_BUSY_RX;\r\n    hi2c->Mode        = HAL_I2C_MODE_MASTER;\r\n    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r\n\r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr    = pData;\r\n    hi2c->XferCount   = Size;\r\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r\n    hi2c->XferISR     = I2C_Master_ISR_DMA;\r\n\r\n    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r\n    {\r\n      hi2c->XferSize = MAX_NBYTE_SIZE;\r\n      xfermode = I2C_RELOAD_MODE;\r\n    }\r\n    else\r\n    {\r\n      hi2c->XferSize = hi2c->XferCount;\r\n      xfermode = I2C_AUTOEND_MODE;\r\n    }\r\n\r\n    if (hi2c->XferSize > 0U)\r\n    {\r\n      /* Set the I2C DMA transfer complete callback */\r\n      hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;\r\n\r\n      /* Set the DMA error callback */\r\n      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;\r\n\r\n      /* Set the unused DMA callbacks to NULL */\r\n      hi2c->hdmarx->XferHalfCpltCallback = NULL;\r\n      hi2c->hdmarx->XferAbortCallback = NULL;\r\n\r\n      /* Enable the DMA stream */\r\n      HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);\r\n\r\n      /* Send Slave Address */\r\n      /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r\n      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);\r\n\r\n      /* Update XferCount value */\r\n      hi2c->XferCount -= hi2c->XferSize;\r\n\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hi2c);\r\n\r\n      /* Note : The I2C interrupts must be enabled after unlocking current process\r\n                to avoid the risk of I2C interrupt handle execution before current\r\n                process unlock */\r\n      /* Enable ERR and NACK interrupts */\r\n      I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);\r\n\r\n      /* Enable DMA Request */\r\n      hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;\r\n    }\r\n    else\r\n    {\r\n      /* Update Transfer ISR function pointer */\r\n      hi2c->XferISR = I2C_Master_ISR_IT;\r\n\r\n      /* Send Slave Address */\r\n      /* Set NBYTES to read and generate START condition */\r\n      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);\r\n\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hi2c);\r\n\r\n      /* Note : The I2C interrupts must be enabled after unlocking current process\r\n                to avoid the risk of I2C interrupt handle execution before current\r\n                process unlock */\r\n      /* Enable ERR, TC, STOP, NACK, TXI interrupt */\r\n      /* possible to enable all of these */\r\n      /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r\n      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);\r\n    }\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Transmit in slave mode an amount of data in non-blocking mode with DMA\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  pData Pointer to data buffer\r\n  * @param  Size Amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)\r\n{\r\n  if (hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    if ((pData == NULL) || (Size == 0U))\r\n    {\r\n      return  HAL_ERROR;\r\n    }\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n\r\n    hi2c->State       = HAL_I2C_STATE_BUSY_TX;\r\n    hi2c->Mode        = HAL_I2C_MODE_SLAVE;\r\n    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r\n\r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr    = pData;\r\n    hi2c->XferCount   = Size;\r\n    hi2c->XferSize    = hi2c->XferCount;\r\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r\n    hi2c->XferISR     = I2C_Slave_ISR_DMA;\r\n\r\n    /* Set the I2C DMA transfer complete callback */\r\n    hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;\r\n\r\n    /* Set the DMA error callback */\r\n    hi2c->hdmatx->XferErrorCallback = I2C_DMAError;\r\n\r\n    /* Set the unused DMA callbacks to NULL */\r\n    hi2c->hdmatx->XferHalfCpltCallback = NULL;\r\n    hi2c->hdmatx->XferAbortCallback = NULL;\r\n\r\n    /* Enable the DMA stream */\r\n    HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);\r\n\r\n    /* Enable Address Acknowledge */\r\n    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    /* Note : The I2C interrupts must be enabled after unlocking current process\r\n              to avoid the risk of I2C interrupt handle execution before current\r\n              process unlock */\r\n    /* Enable ERR, STOP, NACK, ADDR interrupts */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r\n\r\n    /* Enable DMA Request */\r\n    hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Receive in slave mode an amount of data in non-blocking mode with DMA\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  pData Pointer to data buffer\r\n  * @param  Size Amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)\r\n{\r\n  if (hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    if ((pData == NULL) || (Size == 0U))\r\n    {\r\n      return  HAL_ERROR;\r\n    }\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n\r\n    hi2c->State       = HAL_I2C_STATE_BUSY_RX;\r\n    hi2c->Mode        = HAL_I2C_MODE_SLAVE;\r\n    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r\n\r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr    = pData;\r\n    hi2c->XferCount   = Size;\r\n    hi2c->XferSize    = hi2c->XferCount;\r\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r\n    hi2c->XferISR     = I2C_Slave_ISR_DMA;\r\n\r\n    /* Set the I2C DMA transfer complete callback */\r\n    hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;\r\n\r\n    /* Set the DMA error callback */\r\n    hi2c->hdmarx->XferErrorCallback = I2C_DMAError;\r\n\r\n    /* Set the unused DMA callbacks to NULL */\r\n    hi2c->hdmarx->XferHalfCpltCallback = NULL;\r\n    hi2c->hdmarx->XferAbortCallback = NULL;\r\n\r\n    /* Enable the DMA stream */\r\n    HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);\r\n\r\n    /* Enable Address Acknowledge */\r\n    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    /* Note : The I2C interrupts must be enabled after unlocking current process\r\n              to avoid the risk of I2C interrupt handle execution before current\r\n              process unlock */\r\n    /* Enable ERR, STOP, NACK, ADDR interrupts */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r\n\r\n    /* Enable DMA Request */\r\n    hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n/**\r\n  * @brief  Write an amount of data in blocking mode to a specific memory address\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  DevAddress Target device address which contain device 7 or 10 bits address value\r\n  *         in datasheet must be shifted to the left before calling the interface\r\n  * @param  MemAddress Internal memory address\r\n  * @param  MemAddSize Size of internal memory address\r\n  * @param  pData Pointer to data buffer\r\n  * @param  Size Amount of data to be sent\r\n  * @param  Timeout Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0U;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r\n\r\n  if (hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    if ((pData == NULL) || (Size == 0U))\r\n    {\r\n      return  HAL_ERROR;\r\n    }\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n\r\n    /* Init tickstart for timeout management*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n\r\n    hi2c->State     = HAL_I2C_STATE_BUSY_TX;\r\n    hi2c->Mode      = HAL_I2C_MODE_MEM;\r\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r\n\r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr  = pData;\r\n    hi2c->XferCount = Size;\r\n    hi2c->XferISR   = NULL;\r\n\r\n    /* Send Slave Address and Memory Address */\r\n    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)\r\n    {\r\n      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n      {\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2c);\r\n        return HAL_ERROR;\r\n      }\r\n      else\r\n      {\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2c);\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n\r\n    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */\r\n    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r\n    {\r\n      hi2c->XferSize = MAX_NBYTE_SIZE;\r\n      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r\n    }\r\n    else\r\n    {\r\n      hi2c->XferSize = hi2c->XferCount;\r\n      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r\n    }\r\n\r\n    do\r\n    {\r\n      /* Wait until TXIS flag is set */\r\n      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r\n      {\r\n        if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n        {\r\n          return HAL_ERROR;\r\n        }\r\n        else\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n\r\n      /* Write data to TXDR */\r\n      hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);\r\n      hi2c->XferCount--;\r\n      hi2c->XferSize--;\r\n\r\n      if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))\r\n      {\r\n        /* Wait until TCR flag is set */\r\n        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n\r\n        if (hi2c->XferCount > MAX_NBYTE_SIZE)\r\n        {\r\n          hi2c->XferSize = MAX_NBYTE_SIZE;\r\n          I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r\n        }\r\n        else\r\n        {\r\n          hi2c->XferSize = hi2c->XferCount;\r\n          I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r\n        }\r\n      }\r\n\r\n    }\r\n    while (hi2c->XferCount > 0U);\r\n\r\n    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r\n    /* Wait until STOPF flag is reset */\r\n    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r\n    {\r\n      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n      {\r\n        return HAL_ERROR;\r\n      }\r\n      else\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n\r\n    /* Clear STOP Flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r\n\r\n    /* Clear Configuration Register 2 */\r\n    I2C_RESET_CR2(hi2c);\r\n\r\n    hi2c->State = HAL_I2C_STATE_READY;\r\n    hi2c->Mode  = HAL_I2C_MODE_NONE;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Read an amount of data in blocking mode from a specific memory address\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  DevAddress Target device address which contain device 7 or 10 bits address value\r\n  *         in datasheet must be shifted to the left before calling the interface\r\n  * @param  MemAddress Internal memory address\r\n  * @param  MemAddSize Size of internal memory address\r\n  * @param  pData Pointer to data buffer\r\n  * @param  Size Amount of data to be sent\r\n  * @param  Timeout Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0U;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r\n\r\n  if (hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    if ((pData == NULL) || (Size == 0U))\r\n    {\r\n      return  HAL_ERROR;\r\n    }\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n\r\n    /* Init tickstart for timeout management*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n\r\n    hi2c->State     = HAL_I2C_STATE_BUSY_RX;\r\n    hi2c->Mode      = HAL_I2C_MODE_MEM;\r\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r\n\r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr  = pData;\r\n    hi2c->XferCount = Size;\r\n    hi2c->XferISR   = NULL;\r\n\r\n    /* Send Slave Address and Memory Address */\r\n    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)\r\n    {\r\n      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n      {\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2c);\r\n        return HAL_ERROR;\r\n      }\r\n      else\r\n      {\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2c);\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n\r\n    /* Send Slave Address */\r\n    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r\n    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r\n    {\r\n      hi2c->XferSize = MAX_NBYTE_SIZE;\r\n      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);\r\n    }\r\n    else\r\n    {\r\n      hi2c->XferSize = hi2c->XferCount;\r\n      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);\r\n    }\r\n\r\n    do\r\n    {\r\n      /* Wait until RXNE flag is set */\r\n      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n\r\n      /* Read data from RXDR */\r\n      (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;\r\n      hi2c->XferSize--;\r\n      hi2c->XferCount--;\r\n\r\n      if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))\r\n      {\r\n        /* Wait until TCR flag is set */\r\n        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n\r\n        if (hi2c->XferCount > MAX_NBYTE_SIZE)\r\n        {\r\n          hi2c->XferSize = MAX_NBYTE_SIZE;\r\n          I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r\n        }\r\n        else\r\n        {\r\n          hi2c->XferSize = hi2c->XferCount;\r\n          I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r\n        }\r\n      }\r\n    }\r\n    while (hi2c->XferCount > 0U);\r\n\r\n    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r\n    /* Wait until STOPF flag is reset */\r\n    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r\n    {\r\n      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n      {\r\n        return HAL_ERROR;\r\n      }\r\n      else\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n\r\n    /* Clear STOP Flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r\n\r\n    /* Clear Configuration Register 2 */\r\n    I2C_RESET_CR2(hi2c);\r\n\r\n    hi2c->State = HAL_I2C_STATE_READY;\r\n    hi2c->Mode  = HAL_I2C_MODE_NONE;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n/**\r\n  * @brief  Write an amount of data in non-blocking mode with Interrupt to a specific memory address\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  DevAddress Target device address which contain device 7 or 10 bits address value\r\n  *         in datasheet must be shifted to the left before calling the interface\r\n  * @param  MemAddress Internal memory address\r\n  * @param  MemAddSize Size of internal memory address\r\n  * @param  pData Pointer to data buffer\r\n  * @param  Size Amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)\r\n{\r\n  uint32_t tickstart = 0U;\r\n  uint32_t xfermode = 0U;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r\n\r\n  if (hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    if ((pData == NULL) || (Size == 0U))\r\n    {\r\n      return  HAL_ERROR;\r\n    }\r\n\r\n    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r\n    {\r\n      return HAL_BUSY;\r\n    }\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n\r\n    /* Init tickstart for timeout management*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    hi2c->State       = HAL_I2C_STATE_BUSY_TX;\r\n    hi2c->Mode        = HAL_I2C_MODE_MEM;\r\n    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r\n\r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr    = pData;\r\n    hi2c->XferCount   = Size;\r\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r\n    hi2c->XferISR     = I2C_Master_ISR_IT;\r\n\r\n    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r\n    {\r\n      hi2c->XferSize = MAX_NBYTE_SIZE;\r\n      xfermode = I2C_RELOAD_MODE;\r\n    }\r\n    else\r\n    {\r\n      hi2c->XferSize = hi2c->XferCount;\r\n      xfermode = I2C_AUTOEND_MODE;\r\n    }\r\n\r\n    /* Send Slave Address and Memory Address */\r\n    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)\r\n    {\r\n      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n      {\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2c);\r\n        return HAL_ERROR;\r\n      }\r\n      else\r\n      {\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2c);\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n\r\n    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r\n    I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    /* Note : The I2C interrupts must be enabled after unlocking current process\r\n              to avoid the risk of I2C interrupt handle execution before current\r\n              process unlock */\r\n\r\n    /* Enable ERR, TC, STOP, NACK, TXI interrupt */\r\n    /* possible to enable all of these */\r\n    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Read an amount of data in non-blocking mode with Interrupt from a specific memory address\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  DevAddress Target device address which contain device 7 or 10 bits address value\r\n  *         in datasheet must be shifted to the left before calling the interface\r\n  * @param  MemAddress Internal memory address\r\n  * @param  MemAddSize Size of internal memory address\r\n  * @param  pData Pointer to data buffer\r\n  * @param  Size Amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)\r\n{\r\n  uint32_t tickstart = 0U;\r\n  uint32_t xfermode = 0U;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r\n\r\n  if (hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    if ((pData == NULL) || (Size == 0U))\r\n    {\r\n      return  HAL_ERROR;\r\n    }\r\n\r\n    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r\n    {\r\n      return HAL_BUSY;\r\n    }\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n\r\n    /* Init tickstart for timeout management*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    hi2c->State       = HAL_I2C_STATE_BUSY_RX;\r\n    hi2c->Mode        = HAL_I2C_MODE_MEM;\r\n    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r\n\r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr    = pData;\r\n    hi2c->XferCount   = Size;\r\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r\n    hi2c->XferISR     = I2C_Master_ISR_IT;\r\n\r\n    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r\n    {\r\n      hi2c->XferSize = MAX_NBYTE_SIZE;\r\n      xfermode = I2C_RELOAD_MODE;\r\n    }\r\n    else\r\n    {\r\n      hi2c->XferSize = hi2c->XferCount;\r\n      xfermode = I2C_AUTOEND_MODE;\r\n    }\r\n\r\n    /* Send Slave Address and Memory Address */\r\n    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)\r\n    {\r\n      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n      {\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2c);\r\n        return HAL_ERROR;\r\n      }\r\n      else\r\n      {\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2c);\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n\r\n    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r\n    I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    /* Note : The I2C interrupts must be enabled after unlocking current process\r\n              to avoid the risk of I2C interrupt handle execution before current\r\n              process unlock */\r\n\r\n    /* Enable ERR, TC, STOP, NACK, RXI interrupt */\r\n    /* possible to enable all of these */\r\n    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n/**\r\n  * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  DevAddress Target device address which contain device 7 or 10 bits address value\r\n  *         in datasheet must be shifted to the left before calling the interface\r\n  * @param  MemAddress Internal memory address\r\n  * @param  MemAddSize Size of internal memory address\r\n  * @param  pData Pointer to data buffer\r\n  * @param  Size Amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)\r\n{\r\n  uint32_t tickstart = 0U;\r\n  uint32_t xfermode = 0U;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r\n\r\n  if (hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    if ((pData == NULL) || (Size == 0U))\r\n    {\r\n      return  HAL_ERROR;\r\n    }\r\n\r\n    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r\n    {\r\n      return HAL_BUSY;\r\n    }\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n\r\n    /* Init tickstart for timeout management*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    hi2c->State       = HAL_I2C_STATE_BUSY_TX;\r\n    hi2c->Mode        = HAL_I2C_MODE_MEM;\r\n    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r\n\r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr    = pData;\r\n    hi2c->XferCount   = Size;\r\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r\n    hi2c->XferISR     = I2C_Master_ISR_DMA;\r\n\r\n    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r\n    {\r\n      hi2c->XferSize = MAX_NBYTE_SIZE;\r\n      xfermode = I2C_RELOAD_MODE;\r\n    }\r\n    else\r\n    {\r\n      hi2c->XferSize = hi2c->XferCount;\r\n      xfermode = I2C_AUTOEND_MODE;\r\n    }\r\n\r\n    /* Send Slave Address and Memory Address */\r\n    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)\r\n    {\r\n      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n      {\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2c);\r\n        return HAL_ERROR;\r\n      }\r\n      else\r\n      {\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2c);\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n\r\n    /* Set the I2C DMA transfer complete callback */\r\n    hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;\r\n\r\n    /* Set the DMA error callback */\r\n    hi2c->hdmatx->XferErrorCallback = I2C_DMAError;\r\n\r\n    /* Set the unused DMA callbacks to NULL */\r\n    hi2c->hdmatx->XferHalfCpltCallback = NULL;\r\n    hi2c->hdmatx->XferAbortCallback = NULL;\r\n\r\n    /* Enable the DMA stream */\r\n    HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);\r\n\r\n    /* Send Slave Address */\r\n    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r\n    I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);\r\n\r\n    /* Update XferCount value */\r\n    hi2c->XferCount -= hi2c->XferSize;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    /* Note : The I2C interrupts must be enabled after unlocking current process\r\n              to avoid the risk of I2C interrupt handle execution before current\r\n              process unlock */\r\n    /* Enable ERR and NACK interrupts */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);\r\n\r\n    /* Enable DMA Request */\r\n    hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Reads an amount of data in non-blocking mode with DMA from a specific memory address.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  DevAddress Target device address which contain device 7 or 10 bits address value\r\n  *         in datasheet must be shifted to the left before calling the interface\r\n  * @param  MemAddress Internal memory address\r\n  * @param  MemAddSize Size of internal memory address\r\n  * @param  pData Pointer to data buffer\r\n  * @param  Size Amount of data to be read\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)\r\n{\r\n  uint32_t tickstart = 0U;\r\n  uint32_t xfermode = 0U;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r\n\r\n  if (hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    if ((pData == NULL) || (Size == 0U))\r\n    {\r\n      return  HAL_ERROR;\r\n    }\r\n\r\n    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r\n    {\r\n      return HAL_BUSY;\r\n    }\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n\r\n    /* Init tickstart for timeout management*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    hi2c->State       = HAL_I2C_STATE_BUSY_RX;\r\n    hi2c->Mode        = HAL_I2C_MODE_MEM;\r\n    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r\n\r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr    = pData;\r\n    hi2c->XferCount   = Size;\r\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r\n    hi2c->XferISR     = I2C_Master_ISR_DMA;\r\n\r\n    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r\n    {\r\n      hi2c->XferSize = MAX_NBYTE_SIZE;\r\n      xfermode = I2C_RELOAD_MODE;\r\n    }\r\n    else\r\n    {\r\n      hi2c->XferSize = hi2c->XferCount;\r\n      xfermode = I2C_AUTOEND_MODE;\r\n    }\r\n\r\n    /* Send Slave Address and Memory Address */\r\n    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)\r\n    {\r\n      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n      {\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2c);\r\n        return HAL_ERROR;\r\n      }\r\n      else\r\n      {\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2c);\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n\r\n    /* Set the I2C DMA transfer complete callback */\r\n    hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;\r\n\r\n    /* Set the DMA error callback */\r\n    hi2c->hdmarx->XferErrorCallback = I2C_DMAError;\r\n\r\n    /* Set the unused DMA callbacks to NULL */\r\n    hi2c->hdmarx->XferHalfCpltCallback = NULL;\r\n    hi2c->hdmarx->XferAbortCallback = NULL;\r\n\r\n    /* Enable the DMA stream */\r\n    HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);\r\n\r\n    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r\n    I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);\r\n\r\n    /* Update XferCount value */\r\n    hi2c->XferCount -= hi2c->XferSize;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    /* Enable DMA Request */\r\n    hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;\r\n\r\n    /* Note : The I2C interrupts must be enabled after unlocking current process\r\n              to avoid the risk of I2C interrupt handle execution before current\r\n              process unlock */\r\n    /* Enable ERR and NACK interrupts */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Checks if target device is ready for communication.\r\n  * @note   This function is used with Memory devices\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  DevAddress Target device address which contain device 7 or 10 bits address value\r\n  *         in datasheet must be shifted to the left before calling the interface\r\n  * @param  Trials Number of trials\r\n  * @param  Timeout Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0U;\r\n\r\n  __IO uint32_t I2C_Trials = 0U;\r\n\r\n  if (hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r\n    {\r\n      return HAL_BUSY;\r\n    }\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n\r\n    hi2c->State = HAL_I2C_STATE_BUSY;\r\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r\n\r\n    do\r\n    {\r\n      /* Generate Start */\r\n      hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);\r\n\r\n      /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r\n      /* Wait until STOPF flag is set or a NACK flag is set*/\r\n      tickstart = HAL_GetTick();\r\n      while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT))\r\n      {\r\n        if (Timeout != HAL_MAX_DELAY)\r\n        {\r\n          if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))\r\n          {\r\n            /* Device is ready */\r\n            hi2c->State = HAL_I2C_STATE_READY;\r\n            /* Process Unlocked */\r\n            __HAL_UNLOCK(hi2c);\r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n      }\r\n\r\n      /* Check if the NACKF flag has not been set */\r\n      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)\r\n      {\r\n        /* Wait until STOPF flag is reset */\r\n        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n\r\n        /* Clear STOP Flag */\r\n        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r\n\r\n        /* Device is ready */\r\n        hi2c->State = HAL_I2C_STATE_READY;\r\n\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2c);\r\n\r\n        return HAL_OK;\r\n      }\r\n      else\r\n      {\r\n        /* Wait until STOPF flag is reset */\r\n        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n\r\n        /* Clear NACK Flag */\r\n        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r\n\r\n        /* Clear STOP Flag, auto generated with autoend*/\r\n        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r\n      }\r\n\r\n      /* Check if the maximum allowed number of trials has been reached */\r\n      if (I2C_Trials++ == Trials)\r\n      {\r\n        /* Generate Stop */\r\n        hi2c->Instance->CR2 |= I2C_CR2_STOP;\r\n\r\n        /* Wait until STOPF flag is reset */\r\n        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n\r\n        /* Clear STOP Flag */\r\n        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r\n      }\r\n    }\r\n    while (I2C_Trials < Trials);\r\n\r\n    hi2c->State = HAL_I2C_STATE_READY;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    return HAL_TIMEOUT;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.\r\n  * @note   This interface allow to manage repeated start condition when a direction change during transfer\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  DevAddress Target device address which contain device 7 or 10 bits address value\r\n  *         in datasheet must be shifted to the left before calling the interface\r\n  * @param  pData Pointer to data buffer\r\n  * @param  Size Amount of data to be sent\r\n  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r\n{\r\n  uint32_t xfermode = 0U;\r\n  uint32_t xferrequest = I2C_GENERATE_START_WRITE;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r\n\r\n  if (hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n\r\n    hi2c->State     = HAL_I2C_STATE_BUSY_TX;\r\n    hi2c->Mode      = HAL_I2C_MODE_MASTER;\r\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r\n\r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr    = pData;\r\n    hi2c->XferCount   = Size;\r\n    hi2c->XferOptions = XferOptions;\r\n    hi2c->XferISR     = I2C_Master_ISR_IT;\r\n\r\n    /* If size > MAX_NBYTE_SIZE, use reload mode */\r\n    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r\n    {\r\n      hi2c->XferSize = MAX_NBYTE_SIZE;\r\n      xfermode = I2C_RELOAD_MODE;\r\n    }\r\n    else\r\n    {\r\n      hi2c->XferSize = hi2c->XferCount;\r\n      xfermode = hi2c->XferOptions;\r\n    }\r\n\r\n    /* If transfer direction not change, do not generate Restart Condition */\r\n    /* Mean Previous state is same as current state */\r\n    if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)\r\n    {\r\n      xferrequest = I2C_NO_STARTSTOP;\r\n    }\r\n\r\n    /* Send Slave Address and set NBYTES to write */\r\n    I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest);\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    /* Note : The I2C interrupts must be enabled after unlocking current process\r\n              to avoid the risk of I2C interrupt handle execution before current\r\n              process unlock */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt\r\n  * @note   This interface allow to manage repeated start condition when a direction change during transfer\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  DevAddress Target device address which contain device 7 or 10 bits address value\r\n  *         in datasheet must be shifted to the left before calling the interface\r\n  * @param  pData Pointer to data buffer\r\n  * @param  Size Amount of data to be sent\r\n  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r\n{\r\n  uint32_t xfermode = 0U;\r\n  uint32_t xferrequest = I2C_GENERATE_START_READ;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r\n\r\n  if (hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n\r\n    hi2c->State     = HAL_I2C_STATE_BUSY_RX;\r\n    hi2c->Mode      = HAL_I2C_MODE_MASTER;\r\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r\n\r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr    = pData;\r\n    hi2c->XferCount   = Size;\r\n    hi2c->XferOptions = XferOptions;\r\n    hi2c->XferISR     = I2C_Master_ISR_IT;\r\n\r\n    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */\r\n    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r\n    {\r\n      hi2c->XferSize = MAX_NBYTE_SIZE;\r\n      xfermode = I2C_RELOAD_MODE;\r\n    }\r\n    else\r\n    {\r\n      hi2c->XferSize = hi2c->XferCount;\r\n      xfermode = hi2c->XferOptions;\r\n    }\r\n\r\n    /* If transfer direction not change, do not generate Restart Condition */\r\n    /* Mean Previous state is same as current state */\r\n    if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)\r\n    {\r\n      xferrequest = I2C_NO_STARTSTOP;\r\n    }\r\n\r\n    /* Send Slave Address and set NBYTES to read */\r\n    I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest);\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    /* Note : The I2C interrupts must be enabled after unlocking current process\r\n              to avoid the risk of I2C interrupt handle execution before current\r\n              process unlock */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt\r\n  * @note   This interface allow to manage repeated start condition when a direction change during transfer\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  pData Pointer to data buffer\r\n  * @param  Size Amount of data to be sent\r\n  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r\n\r\n  if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)\r\n  {\r\n    if ((pData == NULL) || (Size == 0U))\r\n    {\r\n      return  HAL_ERROR;\r\n    }\r\n\r\n    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */\r\n    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n\r\n    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */\r\n    /* and then toggle the HAL slave RX state to TX state */\r\n    if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)\r\n    {\r\n      /* Disable associated Interrupts */\r\n      I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);\r\n    }\r\n\r\n    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;\r\n    hi2c->Mode      = HAL_I2C_MODE_SLAVE;\r\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r\n\r\n    /* Enable Address Acknowledge */\r\n    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r\n\r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr    = pData;\r\n    hi2c->XferCount   = Size;\r\n    hi2c->XferSize    = hi2c->XferCount;\r\n    hi2c->XferOptions = XferOptions;\r\n    hi2c->XferISR     = I2C_Slave_ISR_IT;\r\n\r\n    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)\r\n    {\r\n      /* Clear ADDR flag after prepare the transfer parameters */\r\n      /* This action will generate an acknowledge to the Master */\r\n      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r\n    }\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    /* Note : The I2C interrupts must be enabled after unlocking current process\r\n    to avoid the risk of I2C interrupt handle execution before current\r\n    process unlock */\r\n    /* REnable ADDR interrupt */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt\r\n  * @note   This interface allow to manage repeated start condition when a direction change during transfer\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  pData Pointer to data buffer\r\n  * @param  Size Amount of data to be sent\r\n  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r\n\r\n  if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)\r\n  {\r\n    if ((pData == NULL) || (Size == 0U))\r\n    {\r\n      return  HAL_ERROR;\r\n    }\r\n\r\n    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */\r\n    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n\r\n    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */\r\n    /* and then toggle the HAL slave TX state to RX state */\r\n    if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)\r\n    {\r\n      /* Disable associated Interrupts */\r\n      I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);\r\n    }\r\n\r\n    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;\r\n    hi2c->Mode      = HAL_I2C_MODE_SLAVE;\r\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r\n\r\n    /* Enable Address Acknowledge */\r\n    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r\n\r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr    = pData;\r\n    hi2c->XferCount   = Size;\r\n    hi2c->XferSize    = hi2c->XferCount;\r\n    hi2c->XferOptions = XferOptions;\r\n    hi2c->XferISR     = I2C_Slave_ISR_IT;\r\n\r\n    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)\r\n    {\r\n      /* Clear ADDR flag after prepare the transfer parameters */\r\n      /* This action will generate an acknowledge to the Master */\r\n      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r\n    }\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    /* Note : The I2C interrupts must be enabled after unlocking current process\r\n    to avoid the risk of I2C interrupt handle execution before current\r\n    process unlock */\r\n    /* REnable ADDR interrupt */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Enable the Address listen mode with Interrupt.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)\r\n{\r\n  if (hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    hi2c->State = HAL_I2C_STATE_LISTEN;\r\n    hi2c->XferISR = I2C_Slave_ISR_IT;\r\n\r\n    /* Enable the Address Match interrupt */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Disable the Address listen mode with Interrupt.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* Declaration of tmp to prevent undefined behavior of volatile usage */\r\n  uint32_t tmp;\r\n\r\n  /* Disable Address listen mode only if a transfer is not ongoing */\r\n  if (hi2c->State == HAL_I2C_STATE_LISTEN)\r\n  {\r\n    tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;\r\n    hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);\r\n    hi2c->State = HAL_I2C_STATE_READY;\r\n    hi2c->Mode = HAL_I2C_MODE_NONE;\r\n    hi2c->XferISR = NULL;\r\n\r\n    /* Disable the Address Match interrupt */\r\n    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Abort a master I2C IT or DMA process communication with Interrupt.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  DevAddress Target device address which contain device 7 or 10 bits address value\r\n  *         in datasheet must be shifted to the left before calling the interface\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)\r\n{\r\n  if (hi2c->Mode == HAL_I2C_MODE_MASTER)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n\r\n    /* Disable Interrupts */\r\n    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);\r\n    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);\r\n\r\n    /* Set State at HAL_I2C_STATE_ABORT */\r\n    hi2c->State = HAL_I2C_STATE_ABORT;\r\n\r\n    /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */\r\n    /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */\r\n    I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    /* Note : The I2C interrupts must be enabled after unlocking current process\r\n              to avoid the risk of I2C interrupt handle execution before current\r\n              process unlock */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    /* Wrong usage of abort function */\r\n    /* This function should be used only in case of abort monitored by master device */\r\n    return HAL_ERROR;\r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks\r\n * @{\r\n */\r\n\r\n/**\r\n  * @brief  This function handles I2C event interrupt request.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @retval None\r\n  */\r\nvoid HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* Get current IT Flags and IT sources value */\r\n  uint32_t itflags   = READ_REG(hi2c->Instance->ISR);\r\n  uint32_t itsources = READ_REG(hi2c->Instance->CR1);\r\n\r\n  /* I2C events treatment -------------------------------------*/\r\n  if (hi2c->XferISR != NULL)\r\n  {\r\n    hi2c->XferISR(hi2c, itflags, itsources);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  This function handles I2C error interrupt request.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @retval None\r\n  */\r\nvoid HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)\r\n{\r\n  uint32_t itflags   = READ_REG(hi2c->Instance->ISR);\r\n  uint32_t itsources = READ_REG(hi2c->Instance->CR1);\r\n\r\n  /* I2C Bus error interrupt occurred ------------------------------------*/\r\n  if (((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))\r\n  {\r\n    hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;\r\n\r\n    /* Clear BERR flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);\r\n  }\r\n\r\n  /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/\r\n  if (((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))\r\n  {\r\n    hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;\r\n\r\n    /* Clear OVR flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);\r\n  }\r\n\r\n  /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/\r\n  if (((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))\r\n  {\r\n    hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;\r\n\r\n    /* Clear ARLO flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);\r\n  }\r\n\r\n  /* Call the Error Callback in case of Error detected */\r\n  if ((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) !=  HAL_I2C_ERROR_NONE)\r\n  {\r\n    I2C_ITError(hi2c, hi2c->ErrorCode);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Master Tx Transfer completed callback.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @retval None\r\n  */\r\n__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2c);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_I2C_MasterTxCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Master Rx Transfer completed callback.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @retval None\r\n  */\r\n__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2c);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_I2C_MasterRxCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/** @brief  Slave Tx Transfer completed callback.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @retval None\r\n  */\r\n__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2c);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Slave Rx Transfer completed callback.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @retval None\r\n  */\r\n__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2c);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Slave Address Match callback.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION\r\n  * @param  AddrMatchCode Address Match Code\r\n  * @retval None\r\n  */\r\n__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2c);\r\n  UNUSED(TransferDirection);\r\n  UNUSED(AddrMatchCode);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_I2C_AddrCallback() could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Listen Complete callback.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @retval None\r\n  */\r\n__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2c);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_I2C_ListenCpltCallback() could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Memory Tx Transfer completed callback.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @retval None\r\n  */\r\n__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2c);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_I2C_MemTxCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Memory Rx Transfer completed callback.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @retval None\r\n  */\r\n__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2c);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_I2C_MemRxCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  I2C error callback.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @retval None\r\n  */\r\n__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2c);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_I2C_ErrorCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  I2C abort callback.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @retval None\r\n  */\r\n__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2c);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_I2C_AbortCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions\r\n *  @brief   Peripheral State, Mode and Error functions\r\n *\r\n@verbatim\r\n ===============================================================================\r\n            ##### Peripheral State, Mode and Error functions #####\r\n ===============================================================================\r\n    [..]\r\n    This subsection permit to get in run-time the status of the peripheral\r\n    and the data flow.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Return the I2C handle state.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @retval HAL state\r\n  */\r\nHAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* Return I2C handle state */\r\n  return hi2c->State;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the I2C Master, Slave, Memory or no mode.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *         the configuration information for I2C module\r\n  * @retval HAL mode\r\n  */\r\nHAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)\r\n{\r\n  return hi2c->Mode;\r\n}\r\n\r\n/**\r\n  * @brief  Return the I2C error code.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *              the configuration information for the specified I2C.\r\n* @retval I2C Error Code\r\n*/\r\nuint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)\r\n{\r\n  return hi2c->ErrorCode;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup I2C_Private_Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  ITFlags Interrupt flags to handle.\r\n  * @param  ITSources Interrupt sources enabled.\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)\r\n{\r\n  uint16_t devaddress = 0U;\r\n\r\n  /* Process Locked */\r\n  __HAL_LOCK(hi2c);\r\n\r\n  if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))\r\n  {\r\n    /* Clear NACK Flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r\n\r\n    /* Set corresponding Error Code */\r\n    /* No need to generate STOP, it is automatically done */\r\n    /* Error callback will be send during stop flag treatment */\r\n    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r\n\r\n    /* Flush TX register */\r\n    I2C_Flush_TXDR(hi2c);\r\n  }\r\n  else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))\r\n  {\r\n    /* Read data from RXDR */\r\n    (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;\r\n    hi2c->XferSize--;\r\n    hi2c->XferCount--;\r\n  }\r\n  else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))\r\n  {\r\n    /* Write data to TXDR */\r\n    hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);\r\n    hi2c->XferSize--;\r\n    hi2c->XferCount--;\r\n  }\r\n  else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))\r\n  {\r\n    if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))\r\n    {\r\n      devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);\r\n\r\n      if (hi2c->XferCount > MAX_NBYTE_SIZE)\r\n      {\r\n        hi2c->XferSize = MAX_NBYTE_SIZE;\r\n        I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r\n      }\r\n      else\r\n      {\r\n        hi2c->XferSize = hi2c->XferCount;\r\n        if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)\r\n        {\r\n          I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);\r\n        }\r\n        else\r\n        {\r\n          I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r\n        }\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* Call TxCpltCallback() if no stop mode is set */\r\n      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)\r\n      {\r\n        /* Call I2C Master Sequential complete process */\r\n        I2C_ITMasterSequentialCplt(hi2c);\r\n      }\r\n      else\r\n      {\r\n        /* Wrong size Status regarding TCR flag event */\r\n        /* Call the corresponding callback to inform upper layer of End of Transfer */\r\n        I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);\r\n      }\r\n    }\r\n  }\r\n  else if (((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))\r\n  {\r\n    if (hi2c->XferCount == 0U)\r\n    {\r\n      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)\r\n      {\r\n        /* Generate a stop condition in case of no transfer option */\r\n        if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)\r\n        {\r\n          /* Generate Stop */\r\n          hi2c->Instance->CR2 |= I2C_CR2_STOP;\r\n        }\r\n        else\r\n        {\r\n          /* Call I2C Master Sequential complete process */\r\n          I2C_ITMasterSequentialCplt(hi2c);\r\n        }\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* Wrong size Status regarding TC flag event */\r\n      /* Call the corresponding callback to inform upper layer of End of Transfer */\r\n      I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);\r\n    }\r\n  }\r\n\r\n  if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))\r\n  {\r\n    /* Call I2C Master complete process */\r\n    I2C_ITMasterCplt(hi2c, ITFlags);\r\n  }\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hi2c);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  ITFlags Interrupt flags to handle.\r\n  * @param  ITSources Interrupt sources enabled.\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hi2c);\r\n\r\n  if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))\r\n  {\r\n    /* Check that I2C transfer finished */\r\n    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */\r\n    /* Mean XferCount == 0*/\r\n    /* So clear Flag NACKF only */\r\n    if (hi2c->XferCount == 0U)\r\n    {\r\n      if (((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \\\r\n          (hi2c->State == HAL_I2C_STATE_LISTEN))\r\n      {\r\n        /* Call I2C Listen complete process */\r\n        I2C_ITListenCplt(hi2c, ITFlags);\r\n      }\r\n      else if ((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN))\r\n      {\r\n        /* Clear NACK Flag */\r\n        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r\n\r\n        /* Flush TX register */\r\n        I2C_Flush_TXDR(hi2c);\r\n\r\n        /* Last Byte is Transmitted */\r\n        /* Call I2C Slave Sequential complete process */\r\n        I2C_ITSlaveSequentialCplt(hi2c);\r\n      }\r\n      else\r\n      {\r\n        /* Clear NACK Flag */\r\n        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/\r\n      /* Clear NACK Flag */\r\n      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r\n\r\n      /* Set ErrorCode corresponding to a Non-Acknowledge */\r\n      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r\n    }\r\n  }\r\n  else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))\r\n  {\r\n    if (hi2c->XferCount > 0U)\r\n    {\r\n      /* Read data from RXDR */\r\n      (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;\r\n      hi2c->XferSize--;\r\n      hi2c->XferCount--;\r\n    }\r\n\r\n    if ((hi2c->XferCount == 0U) && \\\r\n        (hi2c->XferOptions != I2C_NO_OPTION_FRAME))\r\n    {\r\n      /* Call I2C Slave Sequential complete process */\r\n      I2C_ITSlaveSequentialCplt(hi2c);\r\n    }\r\n  }\r\n  else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))\r\n  {\r\n    I2C_ITAddrCplt(hi2c, ITFlags);\r\n  }\r\n  else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))\r\n  {\r\n    /* Write data to TXDR only if XferCount not reach \"0\" */\r\n    /* A TXIS flag can be set, during STOP treatment      */\r\n    /* Check if all Datas have already been sent */\r\n    /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */\r\n    if (hi2c->XferCount > 0U)\r\n    {\r\n      /* Write data to TXDR */\r\n      hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);\r\n      hi2c->XferCount--;\r\n      hi2c->XferSize--;\r\n    }\r\n    else\r\n    {\r\n      if ((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME))\r\n      {\r\n        /* Last Byte is Transmitted */\r\n        /* Call I2C Slave Sequential complete process */\r\n        I2C_ITSlaveSequentialCplt(hi2c);\r\n      }\r\n    }\r\n  }\r\n\r\n  /* Check if STOPF is set */\r\n  if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))\r\n  {\r\n    /* Call I2C Slave complete process */\r\n    I2C_ITSlaveCplt(hi2c, ITFlags);\r\n  }\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hi2c);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  ITFlags Interrupt flags to handle.\r\n  * @param  ITSources Interrupt sources enabled.\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)\r\n{\r\n  uint16_t devaddress = 0U;\r\n  uint32_t xfermode = 0U;\r\n\r\n  /* Process Locked */\r\n  __HAL_LOCK(hi2c);\r\n\r\n  if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))\r\n  {\r\n    /* Clear NACK Flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r\n\r\n    /* Set corresponding Error Code */\r\n    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r\n\r\n    /* No need to generate STOP, it is automatically done */\r\n    /* But enable STOP interrupt, to treat it */\r\n    /* Error callback will be send during stop flag treatment */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);\r\n\r\n    /* Flush TX register */\r\n    I2C_Flush_TXDR(hi2c);\r\n  }\r\n  else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))\r\n  {\r\n    /* Disable TC interrupt */\r\n    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);\r\n\r\n    if (hi2c->XferCount != 0U)\r\n    {\r\n      /* Recover Slave address */\r\n      devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);\r\n\r\n      /* Prepare the new XferSize to transfer */\r\n      if (hi2c->XferCount > MAX_NBYTE_SIZE)\r\n      {\r\n        hi2c->XferSize = MAX_NBYTE_SIZE;\r\n        xfermode = I2C_RELOAD_MODE;\r\n      }\r\n      else\r\n      {\r\n        hi2c->XferSize = hi2c->XferCount;\r\n        xfermode = I2C_AUTOEND_MODE;\r\n      }\r\n\r\n      /* Set the new XferSize in Nbytes register */\r\n      I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);\r\n\r\n      /* Update XferCount value */\r\n      hi2c->XferCount -= hi2c->XferSize;\r\n\r\n      /* Enable DMA Request */\r\n      if (hi2c->State == HAL_I2C_STATE_BUSY_RX)\r\n      {\r\n        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;\r\n      }\r\n      else\r\n      {\r\n        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* Wrong size Status regarding TCR flag event */\r\n      /* Call the corresponding callback to inform upper layer of End of Transfer */\r\n      I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);\r\n    }\r\n  }\r\n  else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))\r\n  {\r\n    /* Call I2C Master complete process */\r\n    I2C_ITMasterCplt(hi2c, ITFlags);\r\n  }\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hi2c);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  ITFlags Interrupt flags to handle.\r\n  * @param  ITSources Interrupt sources enabled.\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hi2c);\r\n\r\n  if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))\r\n  {\r\n    /* Check that I2C transfer finished */\r\n    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */\r\n    /* Mean XferCount == 0 */\r\n    /* So clear Flag NACKF only */\r\n    if (I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U)\r\n    {\r\n      /* Clear NACK Flag */\r\n      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r\n    }\r\n    else\r\n    {\r\n      /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/\r\n      /* Clear NACK Flag */\r\n      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r\n\r\n      /* Set ErrorCode corresponding to a Non-Acknowledge */\r\n      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r\n    }\r\n  }\r\n  else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))\r\n  {\r\n    /* Clear ADDR flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r\n  }\r\n  else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))\r\n  {\r\n    /* Call I2C Slave complete process */\r\n    I2C_ITSlaveCplt(hi2c, ITFlags);\r\n  }\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hi2c);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Master sends target device address followed by internal memory address for write request.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  DevAddress Target device address which contain device 7 or 10 bits address value\r\n  *         in datasheet must be shifted to the left before calling the interface\r\n  * @param  MemAddress Internal memory address\r\n  * @param  MemAddSize Size of internal memory address\r\n  * @param  Timeout Timeout duration\r\n  * @param  Tickstart Tick start value\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)\r\n{\r\n  I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);\r\n\r\n  /* Wait until TXIS flag is set */\r\n  if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)\r\n  {\r\n    if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n    else\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n\r\n  /* If Memory address size is 8Bit */\r\n  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)\r\n  {\r\n    /* Send Memory Address */\r\n    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);\r\n  }\r\n  /* If Memory address size is 16Bit */\r\n  else\r\n  {\r\n    /* Send MSB of Memory Address */\r\n    hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);\r\n\r\n    /* Wait until TXIS flag is set */\r\n    if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)\r\n    {\r\n      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n      {\r\n        return HAL_ERROR;\r\n      }\r\n      else\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n\r\n    /* Send LSB of Memory Address */\r\n    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);\r\n  }\r\n\r\n  /* Wait until TCR flag is set */\r\n  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)\r\n  {\r\n    return HAL_TIMEOUT;\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Master sends target device address followed by internal memory address for read request.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  DevAddress Target device address which contain device 7 or 10 bits address value\r\n  *         in datasheet must be shifted to the left before calling the interface\r\n  * @param  MemAddress Internal memory address\r\n  * @param  MemAddSize Size of internal memory address\r\n  * @param  Timeout Timeout duration\r\n  * @param  Tickstart Tick start value\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)\r\n{\r\n  I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);\r\n\r\n  /* Wait until TXIS flag is set */\r\n  if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)\r\n  {\r\n    if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n    else\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n\r\n  /* If Memory address size is 8Bit */\r\n  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)\r\n  {\r\n    /* Send Memory Address */\r\n    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);\r\n  }\r\n  /* If Memory address size is 16Bit */\r\n  else\r\n  {\r\n    /* Send MSB of Memory Address */\r\n    hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);\r\n\r\n    /* Wait until TXIS flag is set */\r\n    if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)\r\n    {\r\n      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n      {\r\n        return HAL_ERROR;\r\n      }\r\n      else\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n\r\n    /* Send LSB of Memory Address */\r\n    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);\r\n  }\r\n\r\n  /* Wait until TC flag is set */\r\n  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)\r\n  {\r\n    return HAL_TIMEOUT;\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  I2C Address complete process callback.\r\n  * @param  hi2c I2C handle.\r\n  * @param  ITFlags Interrupt flags to handle.\r\n  * @retval None\r\n  */\r\nstatic void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)\r\n{\r\n  uint8_t transferdirection = 0U;\r\n  uint16_t slaveaddrcode = 0U;\r\n  uint16_t ownadd1code = 0U;\r\n  uint16_t ownadd2code = 0U;\r\n\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(ITFlags);\r\n\r\n  /* In case of Listen state, need to inform upper layer of address match code event */\r\n  if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)\r\n  {\r\n    transferdirection = I2C_GET_DIR(hi2c);\r\n    slaveaddrcode     = I2C_GET_ADDR_MATCH(hi2c);\r\n    ownadd1code       = I2C_GET_OWN_ADDRESS1(hi2c);\r\n    ownadd2code       = I2C_GET_OWN_ADDRESS2(hi2c);\r\n\r\n    /* If 10bits addressing mode is selected */\r\n    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)\r\n    {\r\n      if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))\r\n      {\r\n        slaveaddrcode = ownadd1code;\r\n        hi2c->AddrEventCount++;\r\n        if (hi2c->AddrEventCount == 2U)\r\n        {\r\n          /* Reset Address Event counter */\r\n          hi2c->AddrEventCount = 0U;\r\n\r\n          /* Clear ADDR flag */\r\n          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r\n\r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hi2c);\r\n\r\n          /* Call Slave Addr callback */\r\n          HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);\r\n        }\r\n      }\r\n      else\r\n      {\r\n        slaveaddrcode = ownadd2code;\r\n\r\n        /* Disable ADDR Interrupts */\r\n        I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r\n\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2c);\r\n\r\n        /* Call Slave Addr callback */\r\n        HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);\r\n      }\r\n    }\r\n    /* else 7 bits addressing mode is selected */\r\n    else\r\n    {\r\n      /* Disable ADDR Interrupts */\r\n      I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r\n\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hi2c);\r\n\r\n      /* Call Slave Addr callback */\r\n      HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);\r\n    }\r\n  }\r\n  /* Else clear address flag only */\r\n  else\r\n  {\r\n    /* Clear ADDR flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  I2C Master sequential complete process.\r\n  * @param  hi2c I2C handle.\r\n  * @retval None\r\n  */\r\nstatic void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* Reset I2C handle mode */\r\n  hi2c->Mode = HAL_I2C_MODE_NONE;\r\n\r\n  /* No Generate Stop, to permit restart mode */\r\n  /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */\r\n  if (hi2c->State == HAL_I2C_STATE_BUSY_TX)\r\n  {\r\n    hi2c->State         = HAL_I2C_STATE_READY;\r\n    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;\r\n    hi2c->XferISR       = NULL;\r\n\r\n    /* Disable Interrupts */\r\n    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    /* Call the corresponding callback to inform upper layer of End of Transfer */\r\n    HAL_I2C_MasterTxCpltCallback(hi2c);\r\n  }\r\n  /* hi2c->State == HAL_I2C_STATE_BUSY_RX */\r\n  else\r\n  {\r\n    hi2c->State         = HAL_I2C_STATE_READY;\r\n    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;\r\n    hi2c->XferISR       = NULL;\r\n\r\n    /* Disable Interrupts */\r\n    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    /* Call the corresponding callback to inform upper layer of End of Transfer */\r\n    HAL_I2C_MasterRxCpltCallback(hi2c);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  I2C Slave sequential complete process.\r\n  * @param  hi2c I2C handle.\r\n  * @retval None\r\n  */\r\nstatic void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* Reset I2C handle mode */\r\n  hi2c->Mode = HAL_I2C_MODE_NONE;\r\n\r\n  if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)\r\n  {\r\n    /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */\r\n    hi2c->State         = HAL_I2C_STATE_LISTEN;\r\n    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;\r\n\r\n    /* Disable Interrupts */\r\n    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    /* Call the Tx complete callback to inform upper layer of the end of transmit process */\r\n    HAL_I2C_SlaveTxCpltCallback(hi2c);\r\n  }\r\n\r\n  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)\r\n  {\r\n    /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */\r\n    hi2c->State         = HAL_I2C_STATE_LISTEN;\r\n    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;\r\n\r\n    /* Disable Interrupts */\r\n    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    /* Call the Rx complete callback to inform upper layer of the end of receive process */\r\n    HAL_I2C_SlaveRxCpltCallback(hi2c);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  I2C Master complete process.\r\n  * @param  hi2c I2C handle.\r\n  * @param  ITFlags Interrupt flags to handle.\r\n  * @retval None\r\n  */\r\nstatic void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)\r\n{\r\n  /* Clear STOP Flag */\r\n  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r\n\r\n  /* Clear Configuration Register 2 */\r\n  I2C_RESET_CR2(hi2c);\r\n\r\n  /* Reset handle parameters */\r\n  hi2c->PreviousState = I2C_STATE_NONE;\r\n  hi2c->XferISR       = NULL;\r\n  hi2c->XferOptions   = I2C_NO_OPTION_FRAME;\r\n\r\n  if ((ITFlags & I2C_FLAG_AF) != RESET)\r\n  {\r\n    /* Clear NACK Flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r\n\r\n    /* Set acknowledge error code */\r\n    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r\n  }\r\n\r\n  /* Flush TX register */\r\n  I2C_Flush_TXDR(hi2c);\r\n\r\n  /* Disable Interrupts */\r\n  I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT);\r\n\r\n  /* Call the corresponding callback to inform upper layer of End of Transfer */\r\n  if ((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT))\r\n  {\r\n    /* Call the corresponding callback to inform upper layer of End of Transfer */\r\n    I2C_ITError(hi2c, hi2c->ErrorCode);\r\n  }\r\n  /* hi2c->State == HAL_I2C_STATE_BUSY_TX */\r\n  else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)\r\n  {\r\n    hi2c->State = HAL_I2C_STATE_READY;\r\n\r\n    if (hi2c->Mode == HAL_I2C_MODE_MEM)\r\n    {\r\n      hi2c->Mode = HAL_I2C_MODE_NONE;\r\n\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hi2c);\r\n\r\n      /* Call the corresponding callback to inform upper layer of End of Transfer */\r\n      HAL_I2C_MemTxCpltCallback(hi2c);\r\n    }\r\n    else\r\n    {\r\n      hi2c->Mode = HAL_I2C_MODE_NONE;\r\n\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hi2c);\r\n\r\n      /* Call the corresponding callback to inform upper layer of End of Transfer */\r\n      HAL_I2C_MasterTxCpltCallback(hi2c);\r\n    }\r\n  }\r\n  /* hi2c->State == HAL_I2C_STATE_BUSY_RX */\r\n  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)\r\n  {\r\n    hi2c->State = HAL_I2C_STATE_READY;\r\n\r\n    if (hi2c->Mode == HAL_I2C_MODE_MEM)\r\n    {\r\n      hi2c->Mode = HAL_I2C_MODE_NONE;\r\n\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hi2c);\r\n\r\n      HAL_I2C_MemRxCpltCallback(hi2c);\r\n    }\r\n    else\r\n    {\r\n      hi2c->Mode = HAL_I2C_MODE_NONE;\r\n\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hi2c);\r\n\r\n      HAL_I2C_MasterRxCpltCallback(hi2c);\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  I2C Slave complete process.\r\n  * @param  hi2c I2C handle.\r\n  * @param  ITFlags Interrupt flags to handle.\r\n  * @retval None\r\n  */\r\nstatic void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)\r\n{\r\n  /* Clear STOP Flag */\r\n  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r\n\r\n  /* Clear ADDR flag */\r\n  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r\n\r\n  /* Disable all interrupts */\r\n  I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);\r\n\r\n  /* Disable Address Acknowledge */\r\n  hi2c->Instance->CR2 |= I2C_CR2_NACK;\r\n\r\n  /* Clear Configuration Register 2 */\r\n  I2C_RESET_CR2(hi2c);\r\n\r\n  /* Flush TX register */\r\n  I2C_Flush_TXDR(hi2c);\r\n\r\n  /* If a DMA is ongoing, Update handle size context */\r\n  if (((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) ||\r\n      ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN))\r\n  {\r\n    hi2c->XferCount = I2C_GET_DMA_REMAIN_DATA(hi2c);\r\n  }\r\n\r\n  /* All data are not transferred, so set error code accordingly */\r\n  if (hi2c->XferCount != 0U)\r\n  {\r\n    /* Set ErrorCode corresponding to a Non-Acknowledge */\r\n    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r\n  }\r\n\r\n  /* Store Last receive data if any */\r\n  if (((ITFlags & I2C_FLAG_RXNE) != RESET))\r\n  {\r\n    /* Read data from RXDR */\r\n    (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;\r\n\r\n    if ((hi2c->XferSize > 0U))\r\n    {\r\n      hi2c->XferSize--;\r\n      hi2c->XferCount--;\r\n\r\n      /* Set ErrorCode corresponding to a Non-Acknowledge */\r\n      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r\n    }\r\n  }\r\n\r\n  hi2c->PreviousState = I2C_STATE_NONE;\r\n  hi2c->Mode = HAL_I2C_MODE_NONE;\r\n  hi2c->XferISR = NULL;\r\n\r\n  if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)\r\n  {\r\n    /* Call the corresponding callback to inform upper layer of End of Transfer */\r\n    I2C_ITError(hi2c, hi2c->ErrorCode);\r\n\r\n    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */\r\n    if (hi2c->State == HAL_I2C_STATE_LISTEN)\r\n    {\r\n      /* Call I2C Listen complete process */\r\n      I2C_ITListenCplt(hi2c, ITFlags);\r\n    }\r\n  }\r\n  else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)\r\n  {\r\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r\n    hi2c->State = HAL_I2C_STATE_READY;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */\r\n    HAL_I2C_ListenCpltCallback(hi2c);\r\n  }\r\n  /* Call the corresponding callback to inform upper layer of End of Transfer */\r\n  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)\r\n  {\r\n    hi2c->State = HAL_I2C_STATE_READY;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    /* Call the Slave Rx Complete callback */\r\n    HAL_I2C_SlaveRxCpltCallback(hi2c);\r\n  }\r\n  else\r\n  {\r\n    hi2c->State = HAL_I2C_STATE_READY;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    /* Call the Slave Tx Complete callback */\r\n    HAL_I2C_SlaveTxCpltCallback(hi2c);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  I2C Listen complete process.\r\n  * @param  hi2c I2C handle.\r\n  * @param  ITFlags Interrupt flags to handle.\r\n  * @retval None\r\n  */\r\nstatic void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)\r\n{\r\n  /* Reset handle parameters */\r\n  hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r\n  hi2c->PreviousState = I2C_STATE_NONE;\r\n  hi2c->State = HAL_I2C_STATE_READY;\r\n  hi2c->Mode = HAL_I2C_MODE_NONE;\r\n  hi2c->XferISR = NULL;\r\n\r\n  /* Store Last receive data if any */\r\n  if (((ITFlags & I2C_FLAG_RXNE) != RESET))\r\n  {\r\n    /* Read data from RXDR */\r\n    (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;\r\n\r\n    if ((hi2c->XferSize > 0U))\r\n    {\r\n      hi2c->XferSize--;\r\n      hi2c->XferCount--;\r\n\r\n      /* Set ErrorCode corresponding to a Non-Acknowledge */\r\n      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r\n    }\r\n  }\r\n\r\n  /* Disable all Interrupts*/\r\n  I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);\r\n\r\n  /* Clear NACK Flag */\r\n  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hi2c);\r\n\r\n  /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */\r\n  HAL_I2C_ListenCpltCallback(hi2c);\r\n}\r\n\r\n/**\r\n  * @brief  I2C interrupts error process.\r\n  * @param  hi2c I2C handle.\r\n  * @param  ErrorCode Error code to handle.\r\n  * @retval None\r\n  */\r\nstatic void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)\r\n{\r\n  /* Reset handle parameters */\r\n  hi2c->Mode          = HAL_I2C_MODE_NONE;\r\n  hi2c->XferOptions   = I2C_NO_OPTION_FRAME;\r\n  hi2c->XferCount     = 0U;\r\n\r\n  /* Set new error code */\r\n  hi2c->ErrorCode |= ErrorCode;\r\n\r\n  /* Disable Interrupts */\r\n  if ((hi2c->State == HAL_I2C_STATE_LISTEN)         ||\r\n      (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) ||\r\n      (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))\r\n  {\r\n    /* Disable all interrupts, except interrupts related to LISTEN state */\r\n    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);\r\n\r\n    /* keep HAL_I2C_STATE_LISTEN if set */\r\n    hi2c->State         = HAL_I2C_STATE_LISTEN;\r\n    hi2c->PreviousState = I2C_STATE_NONE;\r\n    hi2c->XferISR       = I2C_Slave_ISR_IT;\r\n  }\r\n  else\r\n  {\r\n    /* Disable all interrupts */\r\n    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);\r\n\r\n    /* If state is an abort treatment on goind, don't change state */\r\n    /* This change will be do later */\r\n    if (hi2c->State != HAL_I2C_STATE_ABORT)\r\n    {\r\n      /* Set HAL_I2C_STATE_READY */\r\n      hi2c->State         = HAL_I2C_STATE_READY;\r\n    }\r\n    hi2c->PreviousState = I2C_STATE_NONE;\r\n    hi2c->XferISR       = NULL;\r\n  }\r\n\r\n  /* Abort DMA TX transfer if any */\r\n  if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)\r\n  {\r\n    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;\r\n\r\n    /* Set the I2C DMA Abort callback :\r\n       will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\r\n    hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    /* Abort DMA TX */\r\n    if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)\r\n    {\r\n      /* Call Directly XferAbortCallback function in case of error */\r\n      hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);\r\n    }\r\n  }\r\n  /* Abort DMA RX transfer if any */\r\n  else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)\r\n  {\r\n    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;\r\n\r\n    /* Set the I2C DMA Abort callback :\r\n       will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\r\n    hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    /* Abort DMA RX */\r\n    if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)\r\n    {\r\n      /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */\r\n      hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);\r\n    }\r\n  }\r\n  else if (hi2c->State == HAL_I2C_STATE_ABORT)\r\n  {\r\n    hi2c->State = HAL_I2C_STATE_READY;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    /* Call the corresponding callback to inform upper layer of End of Transfer */\r\n    HAL_I2C_AbortCpltCallback(hi2c);\r\n  }\r\n  else\r\n  {\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    /* Call the corresponding callback to inform upper layer of End of Transfer */\r\n    HAL_I2C_ErrorCallback(hi2c);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  I2C Tx data register flush process.\r\n  * @param  hi2c I2C handle.\r\n  * @retval None\r\n  */\r\nstatic void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* If a pending TXIS flag is set */\r\n  /* Write a dummy data in TXDR to clear it */\r\n  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)\r\n  {\r\n    hi2c->Instance->TXDR = 0x00U;\r\n  }\r\n\r\n  /* Flush TX register if not empty */\r\n  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)\r\n  {\r\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  DMA I2C master transmit process complete callback.\r\n  * @param  hdma DMA handle\r\n  * @retval None\r\n  */\r\nstatic void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r\n\r\n  /* Disable DMA Request */\r\n  hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;\r\n\r\n  /* If last transfer, enable STOP interrupt */\r\n  if (hi2c->XferCount == 0U)\r\n  {\r\n    /* Enable STOP interrupt */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);\r\n  }\r\n  /* else prepare a new DMA transfer and enable TCReload interrupt */\r\n  else\r\n  {\r\n    /* Update Buffer pointer */\r\n    hi2c->pBuffPtr += hi2c->XferSize;\r\n\r\n    /* Set the XferSize to transfer */\r\n    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r\n    {\r\n      hi2c->XferSize = MAX_NBYTE_SIZE;\r\n    }\r\n    else\r\n    {\r\n      hi2c->XferSize = hi2c->XferCount;\r\n    }\r\n\r\n    /* Enable the DMA stream */\r\n    HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);\r\n\r\n    /* Enable TC interrupts */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  DMA I2C slave transmit process complete callback.\r\n  * @param  hdma DMA handle\r\n  * @retval None\r\n  */\r\nstatic void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdma);\r\n\r\n  /* No specific action, Master fully manage the generation of STOP condition */\r\n  /* Mean that this generation can arrive at any time, at the end or during DMA process */\r\n  /* So STOP condition should be manage through Interrupt treatment */\r\n}\r\n\r\n/**\r\n  * @brief DMA I2C master receive process complete callback.\r\n  * @param  hdma DMA handle\r\n  * @retval None\r\n  */\r\nstatic void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r\n\r\n  /* Disable DMA Request */\r\n  hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;\r\n\r\n  /* If last transfer, enable STOP interrupt */\r\n  if (hi2c->XferCount == 0U)\r\n  {\r\n    /* Enable STOP interrupt */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);\r\n  }\r\n  /* else prepare a new DMA transfer and enable TCReload interrupt */\r\n  else\r\n  {\r\n    /* Update Buffer pointer */\r\n    hi2c->pBuffPtr += hi2c->XferSize;\r\n\r\n    /* Set the XferSize to transfer */\r\n    if (hi2c->XferCount > MAX_NBYTE_SIZE)\r\n    {\r\n      hi2c->XferSize = MAX_NBYTE_SIZE;\r\n    }\r\n    else\r\n    {\r\n      hi2c->XferSize = hi2c->XferCount;\r\n    }\r\n\r\n    /* Enable the DMA stream */\r\n    HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);\r\n\r\n    /* Enable TC interrupts */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  DMA I2C slave receive process complete callback.\r\n  * @param  hdma DMA handle\r\n  * @retval None\r\n  */\r\nstatic void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdma);\r\n\r\n  /* No specific action, Master fully manage the generation of STOP condition */\r\n  /* Mean that this generation can arrive at any time, at the end or during DMA process */\r\n  /* So STOP condition should be manage through Interrupt treatment */\r\n}\r\n\r\n/**\r\n  * @brief  DMA I2C communication error callback.\r\n  * @param hdma DMA handle\r\n  * @retval None\r\n  */\r\nstatic void I2C_DMAError(DMA_HandleTypeDef *hdma)\r\n{\r\n  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r\n\r\n  /* Disable Acknowledge */\r\n  hi2c->Instance->CR2 |= I2C_CR2_NACK;\r\n\r\n  /* Call the corresponding callback to inform upper layer of End of Transfer */\r\n  I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);\r\n}\r\n\r\n/**\r\n  * @brief DMA I2C communication abort callback\r\n  *        (To be called at end of DMA Abort procedure).\r\n  * @param hdma DMA handle.\r\n  * @retval None\r\n  */\r\nstatic void I2C_DMAAbort(DMA_HandleTypeDef *hdma)\r\n{\r\n  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r\n\r\n  /* Disable Acknowledge */\r\n  hi2c->Instance->CR2 |= I2C_CR2_NACK;\r\n\r\n  /* Reset AbortCpltCallback */\r\n  hi2c->hdmatx->XferAbortCallback = NULL;\r\n  hi2c->hdmarx->XferAbortCallback = NULL;\r\n\r\n  /* Check if come from abort from user */\r\n  if (hi2c->State == HAL_I2C_STATE_ABORT)\r\n  {\r\n    hi2c->State = HAL_I2C_STATE_READY;\r\n\r\n    /* Call the corresponding callback to inform upper layer of End of Transfer */\r\n    HAL_I2C_AbortCpltCallback(hi2c);\r\n  }\r\n  else\r\n  {\r\n    /* Call the corresponding callback to inform upper layer of End of Transfer */\r\n    HAL_I2C_ErrorCallback(hi2c);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  This function handles I2C Communication Timeout.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  Flag Specifies the I2C flag to check.\r\n  * @param  Status The new Flag status (SET or RESET).\r\n  * @param  Timeout Timeout duration\r\n  * @param  Tickstart Tick start value\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)\r\n{\r\n  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)\r\n  {\r\n    /* Check for the Timeout */\r\n    if (Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))\r\n      {\r\n        hi2c->State = HAL_I2C_STATE_READY;\r\n        hi2c->Mode = HAL_I2C_MODE_NONE;\r\n\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2c);\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  This function handles I2C Communication Timeout for specific usage of TXIS flag.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  Timeout Timeout duration\r\n  * @param  Tickstart Tick start value\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)\r\n{\r\n  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)\r\n  {\r\n    /* Check if a NACK is detected */\r\n    if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n\r\n    /* Check for the Timeout */\r\n    if (Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))\r\n      {\r\n        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r\n        hi2c->State = HAL_I2C_STATE_READY;\r\n        hi2c->Mode = HAL_I2C_MODE_NONE;\r\n\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2c);\r\n\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  Timeout Timeout duration\r\n  * @param  Tickstart Tick start value\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)\r\n{\r\n  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)\r\n  {\r\n    /* Check if a NACK is detected */\r\n    if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n\r\n    /* Check for the Timeout */\r\n    if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))\r\n    {\r\n      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r\n      hi2c->State = HAL_I2C_STATE_READY;\r\n      hi2c->Mode = HAL_I2C_MODE_NONE;\r\n\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hi2c);\r\n\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  Timeout Timeout duration\r\n  * @param  Tickstart Tick start value\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)\r\n{\r\n  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)\r\n  {\r\n    /* Check if a NACK is detected */\r\n    if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n\r\n    /* Check if a STOPF is detected */\r\n    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)\r\n    {\r\n      /* Check if an RXNE is pending */\r\n      /* Store Last receive data if any */\r\n      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))\r\n      {\r\n        /* Return HAL_OK */\r\n        /* The Reading of data from RXDR will be done in caller function */\r\n        return HAL_OK;\r\n      }\r\n      else\r\n      {\r\n        /* Clear STOP Flag */\r\n        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r\n\r\n        /* Clear Configuration Register 2 */\r\n        I2C_RESET_CR2(hi2c);\r\n\r\n        hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r\n        hi2c->State = HAL_I2C_STATE_READY;\r\n        hi2c->Mode = HAL_I2C_MODE_NONE;\r\n\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2c);\r\n\r\n        return HAL_ERROR;\r\n      }\r\n    }\r\n\r\n    /* Check for the Timeout */\r\n    if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))\r\n    {\r\n      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r\n      hi2c->State = HAL_I2C_STATE_READY;\r\n\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hi2c);\r\n\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  This function handles Acknowledge failed detection during an I2C Communication.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  Timeout Timeout duration\r\n  * @param  Tickstart Tick start value\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)\r\n{\r\n  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)\r\n  {\r\n    /* Wait until STOP Flag is reset */\r\n    /* AutoEnd should be initiate after AF */\r\n    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)\r\n    {\r\n      /* Check for the Timeout */\r\n      if (Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))\r\n        {\r\n          hi2c->State = HAL_I2C_STATE_READY;\r\n          hi2c->Mode = HAL_I2C_MODE_NONE;\r\n\r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hi2c);\r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n\r\n    /* Clear NACKF Flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r\n\r\n    /* Clear STOP Flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r\n\r\n    /* Flush TX register */\r\n    I2C_Flush_TXDR(hi2c);\r\n\r\n    /* Clear Configuration Register 2 */\r\n    I2C_RESET_CR2(hi2c);\r\n\r\n    hi2c->ErrorCode = HAL_I2C_ERROR_AF;\r\n    hi2c->State = HAL_I2C_STATE_READY;\r\n    hi2c->Mode = HAL_I2C_MODE_NONE;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    return HAL_ERROR;\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).\r\n  * @param  hi2c I2C handle.\r\n  * @param  DevAddress Specifies the slave address to be programmed.\r\n  * @param  Size Specifies the number of bytes to be programmed.\r\n  *   This parameter must be a value between 0 and 255.\r\n  * @param  Mode New state of the I2C START condition generation.\r\n  *   This parameter can be one of the following values:\r\n  *     @arg @ref I2C_RELOAD_MODE Enable Reload mode .\r\n  *     @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.\r\n  *     @arg @ref I2C_SOFTEND_MODE Enable Software end mode.\r\n  * @param  Request New state of the I2C START condition generation.\r\n  *   This parameter can be one of the following values:\r\n  *     @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.\r\n  *     @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).\r\n  *     @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.\r\n  *     @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.\r\n  * @retval None\r\n  */\r\nstatic void I2C_TransferConfig(I2C_HandleTypeDef *hi2c,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\r\n  assert_param(IS_TRANSFER_MODE(Mode));\r\n  assert_param(IS_TRANSFER_REQUEST(Request));\r\n\r\n  /* update CR2 register */\r\n  MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \\\r\n             (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));\r\n}\r\n\r\n/**\r\n  * @brief  Manage the enabling of Interrupts.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)\r\n{\r\n  uint32_t tmpisr = 0U;\r\n\r\n  if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \\\r\n      (hi2c->XferISR == I2C_Slave_ISR_DMA))\r\n  {\r\n    if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)\r\n    {\r\n      /* Enable ERR, STOP, NACK and ADDR interrupts */\r\n      tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;\r\n    }\r\n\r\n    if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)\r\n    {\r\n      /* Enable ERR and NACK interrupts */\r\n      tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;\r\n    }\r\n\r\n    if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)\r\n    {\r\n      /* Enable STOP interrupts */\r\n      tmpisr |= I2C_IT_STOPI;\r\n    }\r\n\r\n    if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)\r\n    {\r\n      /* Enable TC interrupts */\r\n      tmpisr |= I2C_IT_TCI;\r\n    }\r\n  }\r\n  else\r\n  {\r\n    if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)\r\n    {\r\n      /* Enable ERR, STOP, NACK, and ADDR interrupts */\r\n      tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;\r\n    }\r\n\r\n    if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)\r\n    {\r\n      /* Enable ERR, TC, STOP, NACK and RXI interrupts */\r\n      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;\r\n    }\r\n\r\n    if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)\r\n    {\r\n      /* Enable ERR, TC, STOP, NACK and TXI interrupts */\r\n      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;\r\n    }\r\n\r\n    if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)\r\n    {\r\n      /* Enable STOP interrupts */\r\n      tmpisr |= I2C_IT_STOPI;\r\n    }\r\n  }\r\n\r\n  /* Enable interrupts only at the end */\r\n  /* to avoid the risk of I2C interrupt handle execution before */\r\n  /* all interrupts requested done */\r\n  __HAL_I2C_ENABLE_IT(hi2c, tmpisr);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Manage the disabling of Interrupts.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2C.\r\n  * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)\r\n{\r\n  uint32_t tmpisr = 0U;\r\n\r\n  if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)\r\n  {\r\n    /* Disable TC and TXI interrupts */\r\n    tmpisr |= I2C_IT_TCI | I2C_IT_TXI;\r\n\r\n    if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)\r\n    {\r\n      /* Disable NACK and STOP interrupts */\r\n      tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;\r\n    }\r\n  }\r\n\r\n  if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)\r\n  {\r\n    /* Disable TC and RXI interrupts */\r\n    tmpisr |= I2C_IT_TCI | I2C_IT_RXI;\r\n\r\n    if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)\r\n    {\r\n      /* Disable NACK and STOP interrupts */\r\n      tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;\r\n    }\r\n  }\r\n\r\n  if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)\r\n  {\r\n    /* Disable ADDR, NACK and STOP interrupts */\r\n    tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;\r\n  }\r\n\r\n  if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)\r\n  {\r\n    /* Enable ERR and NACK interrupts */\r\n    tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;\r\n  }\r\n\r\n  if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)\r\n  {\r\n    /* Enable STOP interrupts */\r\n    tmpisr |= I2C_IT_STOPI;\r\n  }\r\n\r\n  if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)\r\n  {\r\n    /* Enable TC interrupts */\r\n    tmpisr |= I2C_IT_TCI;\r\n  }\r\n\r\n  /* Disable interrupts only at the end */\r\n  /* to avoid a breaking situation like at \"t\" time */\r\n  /* all disable interrupts request are not done */\r\n  __HAL_I2C_DISABLE_IT(hi2c, tmpisr);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_I2C_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_i2c_ex.c\r\n  * @author  MCD Application Team\r\n  * @brief   I2C Extended HAL module driver.\r\n  *          This file provides firmware functions to manage the following\r\n  *          functionalities of I2C Extended peripheral:\r\n  *           + Extended features functions\r\n  *\r\n  @verbatim\r\n  ==============================================================================\r\n               ##### I2C peripheral Extended features  #####\r\n  ==============================================================================\r\n\r\n  [..] Comparing to other previous devices, the I2C interface for STM32F7xx\r\n       devices contains the following additional features\r\n\r\n       (+) Possibility to disable or enable Analog Noise Filter\r\n       (+) Use of a configured Digital Noise Filter\r\n       (+) Disable or enable Fast Mode Plus\r\n\r\n                     ##### How to use this driver #####\r\n  ==============================================================================\r\n  [..] This driver provides functions to:\r\n    (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()\r\n    (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()\r\n    (#) Configure the enable or disable of fast mode plus driving capability using the functions :\r\n          (++) HAL_I2CEx_EnableFastModePlus()\r\n          (++) HAL_I2CEx_DisableFastModePlus()\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup I2CEx I2CEx\r\n  * @brief I2C Extended HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_I2C_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions\r\n  * @brief    Extended features functions\r\n *\r\n@verbatim\r\n ===============================================================================\r\n                      ##### Extended features functions #####\r\n ===============================================================================\r\n    [..] This section provides functions allowing to:\r\n      (+) Configure Noise Filters\r\n      (+) Configure Fast Mode Plus\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Configure I2C Analog noise filter.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2Cx peripheral.\r\n  * @param  AnalogFilter New state of the Analog filter.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\r\n  assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));\r\n\r\n  if (hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n\r\n    hi2c->State = HAL_I2C_STATE_BUSY;\r\n\r\n    /* Disable the selected I2C peripheral */\r\n    __HAL_I2C_DISABLE(hi2c);\r\n\r\n    /* Reset I2Cx ANOFF bit */\r\n    hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);\r\n\r\n    /* Set analog filter bit*/\r\n    hi2c->Instance->CR1 |= AnalogFilter;\r\n\r\n    __HAL_I2C_ENABLE(hi2c);\r\n\r\n    hi2c->State = HAL_I2C_STATE_READY;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Configure I2C Digital noise filter.\r\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified I2Cx peripheral.\r\n  * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)\r\n{\r\n  uint32_t tmpreg = 0U;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\r\n  assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));\r\n\r\n  if (hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n\r\n    hi2c->State = HAL_I2C_STATE_BUSY;\r\n\r\n    /* Disable the selected I2C peripheral */\r\n    __HAL_I2C_DISABLE(hi2c);\r\n\r\n    /* Get the old register value */\r\n    tmpreg = hi2c->Instance->CR1;\r\n\r\n    /* Reset I2Cx DNF bits [11:8] */\r\n    tmpreg &= ~(I2C_CR1_DNF);\r\n\r\n    /* Set I2Cx DNF coefficient */\r\n    tmpreg |= DigitalFilter << 8U;\r\n\r\n    /* Store the new register value */\r\n    hi2c->Instance->CR1 = tmpreg;\r\n\r\n    __HAL_I2C_ENABLE(hi2c);\r\n\r\n    hi2c->State = HAL_I2C_STATE_READY;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n#if  (defined(SYSCFG_PMC_I2C_PB6_FMP) || defined(SYSCFG_PMC_I2C_PB7_FMP)) || (defined(SYSCFG_PMC_I2C_PB8_FMP) || defined(SYSCFG_PMC_I2C_PB9_FMP)) || (defined(SYSCFG_PMC_I2C1_FMP)) || (defined(SYSCFG_PMC_I2C2_FMP)) || defined(SYSCFG_PMC_I2C3_FMP) || defined(SYSCFG_PMC_I2C4_FMP)\r\n/**\r\n  * @brief Enable the I2C fast mode plus driving capability.\r\n  * @param ConfigFastModePlus Selects the pin.\r\n  *   This parameter can be one of the @ref I2CEx_FastModePlus values\r\n  * @note  For I2C1, fast mode plus driving capability can be enabled on all selected\r\n  *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently\r\n  *        on each one of the following pins PB6, PB7, PB8 and PB9.\r\n  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability\r\n  *        can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.\r\n  * @note  For all I2C2 pins fast mode plus driving capability can be enabled\r\n  *        only by using I2C_FASTMODEPLUS_I2C2 parameter.\r\n  * @note  For all I2C3 pins fast mode plus driving capability can be enabled\r\n  *        only by using I2C_FASTMODEPLUS_I2C3 parameter.\r\n  * @note  For all I2C4 pins fast mode plus driving capability can be enabled\r\n  *        only by using I2C_FASTMODEPLUS_I2C4 parameter.\r\n  * @retval None\r\n  */\r\nvoid HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)\r\n{\r\n  /* Check the parameter */\r\n  assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));\r\n\r\n  /* Enable SYSCFG clock */\r\n  __HAL_RCC_SYSCFG_CLK_ENABLE();\r\n\r\n  /* Enable fast mode plus driving capability for selected pin */\r\n  SET_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus);\r\n}\r\n\r\n/**\r\n  * @brief Disable the I2C fast mode plus driving capability.\r\n  * @param ConfigFastModePlus Selects the pin.\r\n  *   This parameter can be one of the @ref I2CEx_FastModePlus values\r\n  * @note  For I2C1, fast mode plus driving capability can be disabled on all selected\r\n  *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently\r\n  *        on each one of the following pins PB6, PB7, PB8 and PB9.\r\n  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability\r\n  *        can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.\r\n  * @note  For all I2C2 pins fast mode plus driving capability can be disabled\r\n  *        only by using I2C_FASTMODEPLUS_I2C2 parameter.\r\n  * @note  For all I2C3 pins fast mode plus driving capability can be disabled\r\n  *        only by using I2C_FASTMODEPLUS_I2C3 parameter.\r\n  * @note  For all I2C4 pins fast mode plus driving capability can be disabled\r\n  *        only by using I2C_FASTMODEPLUS_I2C4 parameter.\r\n  * @retval None\r\n  */\r\nvoid HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)\r\n{\r\n  /* Check the parameter */\r\n  assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));\r\n\r\n  /* Enable SYSCFG clock */\r\n  __HAL_RCC_SYSCFG_CLK_ENABLE();\r\n\r\n  /* Disable fast mode plus driving capability for selected pin */\r\n  CLEAR_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus);\r\n}\r\n\r\n#endif\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_I2C_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2s.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_i2s.c\r\n  * @author  MCD Application Team\r\n  * @brief   I2S HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the Integrated Interchip Sound (I2S) peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + IO operation functions\r\n  *           + Peripheral State and Errors functions\r\n  @verbatim\r\n ===============================================================================\r\n                  ##### How to use this driver #####\r\n ===============================================================================\r\n [..]\r\n    The I2S HAL driver can be used as follows:\r\n    \r\n    (#) Declare a I2S_HandleTypeDef handle structure.\r\n    (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:\r\n        (##) Enable the SPIx interface clock.                      \r\n        (##) I2S pins configuration:\r\n            (+++) Enable the clock for the I2S GPIOs.\r\n            (+++) Configure these I2S pins as alternate function pull-up.\r\n        (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()\r\n             and HAL_I2S_Receive_IT() APIs).\r\n            (+++) Configure the I2Sx interrupt priority.\r\n            (+++) Enable the NVIC I2S IRQ handle.\r\n        (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()\r\n             and HAL_I2S_Receive_DMA() APIs:\r\n            (+++) Declare a DMA handle structure for the Tx/Rx channel.\r\n            (+++) Enable the DMAx interface clock.\r\n            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.                \r\n            (+++) Configure the DMA Tx/Rx Channel.\r\n            (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.\r\n            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the \r\n                DMA Tx/Rx Channel.\r\n  \r\n   (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity\r\n       using HAL_I2S_Init() function.\r\n\r\n   -@- The specific I2S interrupts (Transmission complete interrupt, \r\n       RXNE interrupt and Error Interrupts) will be managed using the macros\r\n       __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.\r\n   -@- Make sure that either:\r\n       (+@) I2S clock is configured based on SYSCLK or \r\n       (+@) External clock source is configured after setting correctly \r\n            the define constant EXTERNAL_CLOCK_VALUE in the stm32f3xx_hal_conf.h file. \r\n\r\n   (#) Three mode of operations are available within this driver :     \r\n  \r\n   *** Polling mode IO operation ***\r\n   =================================\r\n   [..]    \r\n     (+) Send an amount of data in blocking mode using HAL_I2S_Transmit() \r\n     (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()\r\n   \r\n   *** Interrupt mode IO operation ***    \r\n   ===================================\r\n   [..]    \r\n     (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT() \r\n     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can \r\n         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback \r\n     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can \r\n         add his own code by customization of function pointer HAL_I2S_TxCpltCallback\r\n     (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT() \r\n     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can \r\n         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback \r\n     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can \r\n         add his own code by customization of function pointer HAL_I2S_RxCpltCallback                                      \r\n     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can \r\n         add his own code by customization of function pointer HAL_I2S_ErrorCallback\r\n\r\n   *** DMA mode IO operation ***    \r\n   ==============================\r\n   [..] \r\n     (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA() \r\n     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can \r\n         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback \r\n     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can \r\n         add his own code by customization of function pointer HAL_I2S_TxCpltCallback\r\n     (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA() \r\n     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can \r\n         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback \r\n     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can \r\n         add his own code by customization of function pointer HAL_I2S_RxCpltCallback                                     \r\n     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can \r\n         add his own code by customization of function pointer HAL_I2S_ErrorCallback\r\n     (+) Pause the DMA Transfer using HAL_I2S_DMAPause()      \r\n     (+) Resume the DMA Transfer using HAL_I2S_DMAResume()  \r\n     (+) Stop the DMA Transfer using HAL_I2S_DMAStop()      \r\n   \r\n   *** I2S HAL driver macros list ***\r\n   ============================================= \r\n   [..]\r\n     Below the list of most used macros in I2S HAL driver.\r\n       \r\n      (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode) \r\n      (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)    \r\n      (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts\r\n      (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts\r\n      (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not\r\n      \r\n    [..]  \r\n      (@) You can refer to the I2S HAL driver header file for more useful macros\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup I2S I2S\r\n  * @brief I2S HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_I2S_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/** @defgroup I2S_Private_Functions I2S Private Functions\r\n  * @{\r\n  */\r\nstatic void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);\r\nstatic void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);\r\nstatic void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);\r\nstatic void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);\r\nstatic void I2S_DMAError(DMA_HandleTypeDef *hdma);\r\nstatic void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);\r\nstatic void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);\r\nstatic uint32_t I2S_GetClockFreq(I2S_HandleTypeDef *hi2s);\r\nstatic HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup I2S_Exported_Functions I2S Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup  I2S_Exported_Functions_Group1 Initialization and de-initialization functions \r\n  *  @brief    Initialization and Configuration functions \r\n  *\r\n@verbatim    \r\n ===============================================================================\r\n              ##### Initialization and de-initialization functions #####\r\n ===============================================================================\r\n    [..]  This subsection provides a set of functions allowing to initialize and \r\n          de-initialize the I2Sx peripheral in simplex mode:\r\n\r\n      (+) User must Implement HAL_I2S_MspInit() function in which he configures \r\n          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).\r\n\r\n      (+) Call the function HAL_I2S_Init() to configure the selected device with \r\n          the selected configuration:\r\n        (++) Mode\r\n        (++) Standard \r\n        (++) Data Format\r\n        (++) MCLK Output\r\n        (++) Audio frequency\r\n        (++) Polarity\r\n        (++) Full duplex mode\r\n\r\n      (+) Call the function HAL_I2S_DeInit() to restore the default configuration \r\n          of the selected I2Sx peripheral. \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief Initializes the I2S according to the specified parameters \r\n  *         in the I2S_InitTypeDef and create the associated handle.\r\n  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)\r\n{\r\n  uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;\r\n  uint32_t tmp = 0, i2sclk = 0;\r\n \r\n  /* Check the I2S handle allocation */\r\n  if(hi2s == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));\r\n  assert_param(IS_I2S_MODE(hi2s->Init.Mode));\r\n  assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));\r\n  assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));\r\n  assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));\r\n  assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));\r\n  assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));  \r\n  assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));\r\n  \r\n  if(hi2s->State == HAL_I2S_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    hi2s->Lock = HAL_UNLOCKED;\r\n    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */\r\n    HAL_I2S_MspInit(hi2s);\r\n  }\r\n  \r\n  hi2s->State = HAL_I2S_STATE_BUSY;\r\n    \r\n  /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/\r\n  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */\r\n  hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \\\r\n                               SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \\\r\n                               SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD); \r\n  hi2s->Instance->I2SPR = 0x0002;\r\n  \r\n  /* Get the I2SCFGR register value */\r\n  tmpreg = hi2s->Instance->I2SCFGR;\r\n  \r\n  /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/\r\n  if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT)\r\n  {\r\n    i2sodd = (uint16_t)0;\r\n    i2sdiv = (uint16_t)2;   \r\n  }\r\n  /* If the requested audio frequency is not the default, compute the prescaler */\r\n  else\r\n  {\r\n    /* Check the frame length (For the Prescaler computing) *******************/\r\n    if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)\r\n    {\r\n      /* Packet length is 16 bits */\r\n      packetlength = 1;\r\n    }\r\n    else\r\n    {\r\n      /* Packet length is 32 bits */\r\n      packetlength = 2;\r\n    }\r\n    \r\n    /* Get I2S source Clock frequency  ****************************************/\r\n\r\n    /* If an external I2S clock has to be used, the specific define should be set  \r\n    in the project configuration or in the stm32f3xx_conf.h file */\r\n    if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)\r\n    {    \r\n      /* Set the I2S clock to the external clock  value */\r\n      i2sclk = EXTERNAL_CLOCK_VALUE;\r\n    }\r\n    else\r\n    {\r\n      /* Get the I2S source clock value */\r\n\t\t\ti2sclk = I2S_GetClockFreq(hi2s);\r\n    }\r\n    \r\n    /* Compute the Real divider depending on the MCLK output state, with a floating point */\r\n    if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)\r\n    {\r\n      /* MCLK output is enabled */\r\n      tmp = (uint16_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5);\r\n    }\r\n    else\r\n    {\r\n      /* MCLK output is disabled */\r\n      tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5);\r\n    }\r\n    \r\n    /* Remove the flatting point */\r\n    tmp = tmp / 10;  \r\n    \r\n    /* Check the parity of the divider */\r\n    i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);\r\n    \r\n    /* Compute the i2sdiv prescaler */\r\n    i2sdiv = (uint16_t)((tmp - i2sodd) / 2);\r\n    \r\n    /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */\r\n    i2sodd = (uint16_t) (i2sodd << 8);\r\n  }\r\n  \r\n  /* Test if the divider is 1 or 0 or greater than 0xFF */\r\n  if((i2sdiv < 2) || (i2sdiv > 0xFF))\r\n  {\r\n    /* Set the default values */\r\n    i2sdiv = 2;\r\n    i2sodd = 0;\r\n  }\r\n  \r\n  /* Write to SPIx I2SPR register the computed value */\r\n  hi2s->Instance->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)hi2s->Init.MCLKOutput));\r\n  \r\n  /* Configure the I2S with the I2S_InitStruct values */\r\n  tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(hi2s->Init.Mode | \\\r\n                       (uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \\\r\n                       (uint16_t)hi2s->Init.CPOL))));\r\n\r\n  /* Write to SPIx I2SCFGR */  \r\n  hi2s->Instance->I2SCFGR = tmpreg;    \r\n\r\n  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;\r\n  hi2s->State= HAL_I2S_STATE_READY;\r\n  \r\n  return HAL_OK;\r\n}\r\n           \r\n/**\r\n  * @brief DeInitializes the I2S peripheral \r\n  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)\r\n{\r\n  /* Check the I2S handle allocation */\r\n  if(hi2s == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));\r\n\r\n  hi2s->State = HAL_I2S_STATE_BUSY;\r\n  \r\n  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */\r\n  HAL_I2S_MspDeInit(hi2s);\r\n  \r\n  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;\r\n  hi2s->State = HAL_I2S_STATE_RESET;\r\n  \r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hi2s);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief I2S MSP Init\r\n  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @retval None\r\n  */\r\n __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2s);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_I2S_MspInit could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief I2S MSP DeInit\r\n  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @retval None\r\n  */\r\n __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2s);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_I2S_MspDeInit could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2S_Exported_Functions_Group2 Input and Output operation functions \r\n  *  @brief Data transfers functions \r\n  *\r\n@verbatim   \r\n ===============================================================================\r\n                      ##### IO operation functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides a set of functions allowing to manage the I2S data \r\n    transfers.\r\n\r\n    (#) There are two modes of transfer:\r\n       (++) Blocking mode : The communication is performed in the polling mode. \r\n            The status of all data processing is returned by the same function \r\n            after finishing transfer.  \r\n       (++) No-Blocking mode : The communication is performed using Interrupts \r\n            or DMA. These functions return the status of the transfer startup.\r\n            The end of the data processing will be indicated through the \r\n            dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when \r\n            using DMA mode.\r\n\r\n    (#) Blocking mode functions are :\r\n        (++) HAL_I2S_Transmit()\r\n        (++) HAL_I2S_Receive()\r\n        \r\n    (#) No-Blocking mode functions with Interrupt are :\r\n        (++) HAL_I2S_Transmit_IT()\r\n        (++) HAL_I2S_Receive_IT()\r\n\r\n    (#) No-Blocking mode functions with DMA are :\r\n        (++) HAL_I2S_Transmit_DMA()\r\n        (++) HAL_I2S_Receive_DMA()\r\n\r\n    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:\r\n        (++) HAL_I2S_TxCpltCallback()\r\n        (++) HAL_I2S_RxCpltCallback()\r\n        (++) HAL_I2S_ErrorCallback()\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief Transmit an amount of data in blocking mode\r\n  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @param pData a 16-bit pointer to data buffer.\r\n  * @param Size number of data sample to be sent:\r\n  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S\r\n  *       configuration phase, the Size parameter means the number of 16-bit data length \r\n  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected \r\n  *       the Size parameter means the number of 16-bit data length. \r\n  * @param  Timeout Timeout duration\r\n  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization \r\n  *       between Master and Slave(example: audio streaming).\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)\r\n{\r\n  if((pData == NULL ) || (Size == 0)) \r\n  {\r\n    return  HAL_ERROR;                                    \r\n  }\r\n  \r\n  if(hi2s->State == HAL_I2S_STATE_READY)\r\n  { \r\n    if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\\\r\n       ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))\r\n    {\r\n      hi2s->TxXferSize = (Size << 1);\r\n      hi2s->TxXferCount = (Size << 1);\r\n    }\r\n    else\r\n    {\r\n      hi2s->TxXferSize = Size;\r\n      hi2s->TxXferCount = Size;\r\n    }\r\n    \r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2s);\r\n    \r\n    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;\r\n    hi2s->State = HAL_I2S_STATE_BUSY_TX;\r\n   \r\n    /* Check if the I2S is already enabled */ \r\n    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)\r\n    {\r\n      /* Enable I2S peripheral */    \r\n      __HAL_I2S_ENABLE(hi2s);\r\n    }\r\n    \r\n    while(hi2s->TxXferCount > 0)\r\n    {\r\n      hi2s->Instance->DR = (*pData++);\r\n      hi2s->TxXferCount--;   \r\n      /* Wait until TXE flag is set */\r\n      if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)\r\n      {\r\n        /* Set the error code and execute error callback*/\r\n        hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;\r\n        HAL_I2S_ErrorCallback(hi2s);\r\n        return HAL_TIMEOUT;\r\n      }\r\n\r\n      /* Check if an underrun occurs */\r\n      if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) \r\n      {\r\n        /* Set the I2S State ready */\r\n        hi2s->State = HAL_I2S_STATE_READY; \r\n\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2s);\r\n\r\n        /* Set the error code and execute error callback*/\r\n        hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;\r\n        HAL_I2S_ErrorCallback(hi2s);\r\n\r\n        return HAL_ERROR;\r\n      }\r\n    }      \r\n    \r\n    /* Check if Slave mode is selected */\r\n    if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))\r\n    {\r\n      /* Wait until Busy flag is reset */\r\n      if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK) \r\n      {\r\n        /* Set the error code and execute error callback*/\r\n        hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;\r\n        HAL_I2S_ErrorCallback(hi2s);\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n    \r\n    hi2s->State = HAL_I2S_STATE_READY; \r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2s);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Receive an amount of data in blocking mode \r\n  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @param pData a 16-bit pointer to data buffer.\r\n  * @param Size number of data sample to be sent:\r\n  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S\r\n  *       configuration phase, the Size parameter means the number of 16-bit data length \r\n  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected \r\n  *       the Size parameter means the number of 16-bit data length. \r\n  * @param Timeout Timeout duration\r\n  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization \r\n  *       between Master and Slave(example: audio streaming).\r\n  * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate\r\n  *       in continuous way and as the I2S is not disabled at the end of the I2S transaction.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)\r\n{\r\n  if((pData == NULL ) || (Size == 0)) \r\n  {\r\n    return  HAL_ERROR;                                    \r\n  }\r\n  \r\n  if(hi2s->State == HAL_I2S_STATE_READY)\r\n  { \r\n    if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\\\r\n       ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))\r\n    {\r\n      hi2s->RxXferSize = (Size << 1);\r\n      hi2s->RxXferCount = (Size << 1);\r\n    }\r\n    else\r\n    {\r\n      hi2s->RxXferSize = Size;\r\n      hi2s->RxXferCount = Size;\r\n    }\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2s);\r\n    \r\n    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;\r\n    hi2s->State = HAL_I2S_STATE_BUSY_RX;\r\n        \r\n    /* Check if the I2S is already enabled */ \r\n    if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)\r\n    {\r\n      /* Enable I2S peripheral */    \r\n      __HAL_I2S_ENABLE(hi2s);\r\n    }\r\n    \r\n    /* Check if Master Receiver mode is selected */\r\n    if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)\r\n    {\r\n      /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read\r\n      access to the SPI_SR register. */ \r\n      __HAL_I2S_CLEAR_OVRFLAG(hi2s);        \r\n    }\r\n    \r\n    /* Receive data */\r\n    while(hi2s->RxXferCount > 0)\r\n    {\r\n      /* Wait until RXNE flag is set */\r\n      if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK) \r\n      {\r\n        /* Set the error code and execute error callback*/\r\n        hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;\r\n        HAL_I2S_ErrorCallback(hi2s);\r\n        return HAL_TIMEOUT;\r\n      }\r\n      \r\n      /* Check if an overrun occurs */\r\n      if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET) \r\n      {\r\n        /* Set the I2S State ready */\r\n        hi2s->State = HAL_I2S_STATE_READY; \r\n\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2s);\r\n\r\n        /* Set the error code and execute error callback*/\r\n        hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;\r\n        HAL_I2S_ErrorCallback(hi2s);\r\n\r\n        return HAL_ERROR;\r\n      }\r\n\r\n      (*pData++) = hi2s->Instance->DR;\r\n      hi2s->RxXferCount--;\r\n    }      \r\n\r\n    hi2s->State = HAL_I2S_STATE_READY; \r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2s);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Transmit an amount of data in non-blocking mode with Interrupt\r\n  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @param pData a 16-bit pointer to data buffer.\r\n  * @param Size number of data sample to be sent:\r\n  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S\r\n  *       configuration phase, the Size parameter means the number of 16-bit data length \r\n  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected \r\n  *       the Size parameter means the number of 16-bit data length. \r\n  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization \r\n  *       between Master and Slave(example: audio streaming).\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)\r\n{\r\n  if(hi2s->State == HAL_I2S_STATE_READY)\r\n  {\r\n    if((pData == NULL) || (Size == 0)) \r\n    {\r\n      return  HAL_ERROR;                                    \r\n    }\r\n    \r\n    hi2s->pTxBuffPtr = pData;\r\n    if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\\\r\n      ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))\r\n    {\r\n      hi2s->TxXferSize = (Size << 1);\r\n      hi2s->TxXferCount = (Size << 1);\r\n    }  \r\n    else\r\n    {\r\n      hi2s->TxXferSize = Size;\r\n      hi2s->TxXferCount = Size;\r\n    }\r\n    \r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2s);\r\n    \r\n    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;\r\n    hi2s->State = HAL_I2S_STATE_BUSY_TX;\r\n\r\n    /* Enable TXE and ERR interrupt */\r\n    __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));\r\n    \r\n    /* Check if the I2S is already enabled */ \r\n    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)\r\n    {\r\n      /* Enable I2S peripheral */    \r\n      __HAL_I2S_ENABLE(hi2s);\r\n    }\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2s);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Receive an amount of data in non-blocking mode with Interrupt\r\n  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @param pData a 16-bit pointer to the Receive data buffer.\r\n  * @param Size number of data sample to be sent:\r\n  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S\r\n  *       configuration phase, the Size parameter means the number of 16-bit data length \r\n  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected \r\n  *       the Size parameter means the number of 16-bit data length. \r\n  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization \r\n  *       between Master and Slave(example: audio streaming).\r\n  * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation \r\n  * between Master and Slave otherwise the I2S interrupt should be optimized. \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)\r\n{\r\n  if(hi2s->State == HAL_I2S_STATE_READY)\r\n  {\r\n    if((pData == NULL) || (Size == 0)) \r\n    {\r\n      return  HAL_ERROR;                                    \r\n    }\r\n    \r\n    hi2s->pRxBuffPtr = pData;\r\n    if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\\\r\n      ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))\r\n    {\r\n      hi2s->RxXferSize = (Size << 1);\r\n      hi2s->RxXferCount = (Size << 1);\r\n    }  \r\n    else\r\n    {\r\n      hi2s->RxXferSize = Size;\r\n      hi2s->RxXferCount = Size;\r\n    }\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2s);\r\n    \r\n    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;\r\n    hi2s->State = HAL_I2S_STATE_BUSY_RX;\r\n\r\n    /* Enable TXE and ERR interrupt */\r\n    __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));\r\n    \r\n    /* Check if the I2S is already enabled */ \r\n    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)\r\n    {\r\n      /* Enable I2S peripheral */    \r\n      __HAL_I2S_ENABLE(hi2s);\r\n    }\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2s);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY; \r\n  } \r\n}\r\n\r\n/**\r\n  * @brief Transmit an amount of data in non-blocking mode with DMA\r\n  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @param pData a 16-bit pointer to the Transmit data buffer.\r\n  * @param Size number of data sample to be sent:\r\n  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S\r\n  *       configuration phase, the Size parameter means the number of 16-bit data length \r\n  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected \r\n  *       the Size parameter means the number of 16-bit data length. \r\n  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization \r\n  *       between Master and Slave(example: audio streaming).\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)\r\n{\r\n  uint32_t *tmp;\r\n  \r\n  if((pData == NULL) || (Size == 0)) \r\n  {\r\n    return  HAL_ERROR;                                    \r\n  }\r\n  \r\n  if(hi2s->State == HAL_I2S_STATE_READY)\r\n  {  \r\n    hi2s->pTxBuffPtr = pData;\r\n    if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\\\r\n      ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))\r\n    {\r\n      hi2s->TxXferSize = (Size << 1);\r\n      hi2s->TxXferCount = (Size << 1);\r\n    }  \r\n    else\r\n    {\r\n      hi2s->TxXferSize = Size;\r\n      hi2s->TxXferCount = Size;\r\n    }  \r\n    \r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2s);\r\n    \r\n    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;\r\n    hi2s->State = HAL_I2S_STATE_BUSY_TX;\r\n\r\n    /* Set the I2S Tx DMA Half transfer complete callback */\r\n    hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;\r\n\r\n    /* Set the I2S TxDMA transfer complete callback */\r\n    hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;\r\n    \r\n    /* Set the DMA error callback */\r\n    hi2s->hdmatx->XferErrorCallback = I2S_DMAError;\r\n    \r\n    /* Enable the Tx DMA Channel */\r\n    tmp = (uint32_t*)&pData;\r\n    HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);\r\n    \r\n    /* Check if the I2S is already enabled */ \r\n    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)\r\n    {\r\n      /* Enable I2S peripheral */    \r\n      __HAL_I2S_ENABLE(hi2s);\r\n    }\r\n    \r\n    /* Enable Tx DMA Request */  \r\n    hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2s);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Receive an amount of data in non-blocking mode with DMA \r\n  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @param pData a 16-bit pointer to the Receive data buffer.\r\n  * @param Size number of data sample to be sent:\r\n  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S\r\n  *       configuration phase, the Size parameter means the number of 16-bit data length \r\n  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected \r\n  *       the Size parameter means the number of 16-bit data length. \r\n  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization \r\n  *       between Master and Slave(example: audio streaming).\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)\r\n{\r\n  uint32_t *tmp;\r\n  \r\n  if((pData == NULL) || (Size == 0)) \r\n  {\r\n    return  HAL_ERROR;                                    \r\n  } \r\n    \r\n  if(hi2s->State == HAL_I2S_STATE_READY)\r\n  {    \r\n    hi2s->pRxBuffPtr = pData;\r\n    if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\\\r\n      ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))\r\n    {\r\n      hi2s->RxXferSize = (Size << 1);\r\n      hi2s->RxXferCount = (Size << 1);\r\n    }  \r\n    else\r\n    {\r\n      hi2s->RxXferSize = Size;\r\n      hi2s->RxXferCount = Size;\r\n    }\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2s);\r\n    \r\n    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;\r\n    hi2s->State = HAL_I2S_STATE_BUSY_RX;\r\n   \r\n    /* Set the I2S Rx DMA Half transfer complete callback */\r\n    hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;\r\n\r\n    /* Set the I2S Rx DMA transfer complete callback */\r\n    hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;\r\n    \r\n    /* Set the DMA error callback */\r\n    hi2s->hdmarx->XferErrorCallback = I2S_DMAError;\r\n    \r\n    /* Check if Master Receiver mode is selected */\r\n    if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)\r\n    {\r\n      /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read\r\n      access to the SPI_SR register. */ \r\n      __HAL_I2S_CLEAR_OVRFLAG(hi2s);        \r\n    }\r\n    \r\n    /* Enable the Rx DMA Channel */\r\n    tmp = (uint32_t*)&pData;        \r\n    HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);\r\n    \r\n    /* Check if the I2S is already enabled */ \r\n    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)\r\n    {\r\n      /* Enable I2S peripheral */    \r\n      __HAL_I2S_ENABLE(hi2s);\r\n    }\r\n    \r\n    /* Enable Rx DMA Request */  \r\n    hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2s);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Pauses the audio stream playing from the Media.\r\n  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hi2s);\r\n\r\n  if(hi2s->State == HAL_I2S_STATE_BUSY_TX)\r\n  {\r\n    /* Disable the I2S DMA Tx request */\r\n    hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);\r\n  }\r\n  else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)\r\n  {\r\n    /* Disable the I2S DMA Rx request */\r\n    hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);\r\n  }\r\n  else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)\r\n  {\r\n    if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))\r\n    {\r\n      /* Disable the I2S DMA Tx request */\r\n      hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);\r\n    }\r\n    else\r\n    {\r\n      /* Disable the I2S DMA Rx request */\r\n      hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);\r\n    }\r\n  }\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hi2s);\r\n  \r\n  return HAL_OK; \r\n}\r\n\r\n/**\r\n  * @brief Resumes the audio stream playing from the Media.\r\n  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hi2s);\r\n  \r\n  if(hi2s->State == HAL_I2S_STATE_BUSY_TX)\r\n  {\r\n    /* Enable the I2S DMA Tx request */\r\n    SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);\r\n  }\r\n  else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)\r\n  {\r\n    /* Enable the I2S DMA Rx request */\r\n    SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);\r\n  }\r\n  \r\n  /* If the I2S peripheral is still not enabled, enable it */\r\n  if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))\r\n  {\r\n    /* Enable I2S peripheral */    \r\n    __HAL_I2S_ENABLE(hi2s);\r\n  }\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hi2s);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Stops the audio stream playing from the Media.\r\n  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hi2s);\r\n  \r\n  /* Disable the I2S Tx/Rx DMA requests */\r\n  CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);\r\n  CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);\r\n  \r\n  /* Abort the I2S DMA Channel tx */\r\n  if(hi2s->hdmatx != NULL)\r\n  {\r\n    /* Disable the I2S DMA channel */\r\n    __HAL_DMA_DISABLE(hi2s->hdmatx);\r\n    HAL_DMA_Abort(hi2s->hdmatx);\r\n  }\r\n  /* Abort the I2S DMA Channel rx */\r\n  if(hi2s->hdmarx != NULL)\r\n  {\r\n    /* Disable the I2S DMA channel */\r\n    __HAL_DMA_DISABLE(hi2s->hdmarx);\r\n    HAL_DMA_Abort(hi2s->hdmarx);\r\n  }\r\n\r\n  /* Disable I2S peripheral */\r\n  __HAL_I2S_DISABLE(hi2s);\r\n  \r\n  hi2s->State = HAL_I2S_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hi2s);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  This function handles I2S interrupt request.\r\n  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @retval HAL status\r\n  */\r\nvoid HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)\r\n{  \r\n  __IO uint32_t i2ssr = hi2s->Instance->SR;\r\n\r\n  if(hi2s->State == HAL_I2S_STATE_BUSY_RX)\r\n  {  \r\n    /* I2S in mode Receiver ----------------------------------------------------*/\r\n    if(((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))\r\n    {\r\n      I2S_Receive_IT(hi2s);\r\n    }\r\n\r\n    /* I2S Overrun error interrupt occurred -------------------------------------*/\r\n    if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))\r\n    {\r\n      /* Disable RXNE and ERR interrupt */\r\n      __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));\r\n\r\n      /* Set the I2S State ready */\r\n      hi2s->State = HAL_I2S_STATE_READY; \r\n\r\n      /* Set the error code and execute error callback*/\r\n      hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;\r\n      HAL_I2S_ErrorCallback(hi2s);\r\n    }  \r\n  }\r\n  else if(hi2s->State == HAL_I2S_STATE_BUSY_TX)\r\n  {  \r\n    /* I2S in mode Transmitter ---------------------------------------------------*/\r\n    if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))\r\n    {     \r\n      I2S_Transmit_IT(hi2s);\r\n    } \r\n    \r\n    /* I2S Underrun error interrupt occurred ------------------------------------*/\r\n    if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))\r\n    {\r\n      /* Disable TXE and ERR interrupt */\r\n      __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));\r\n\r\n      /* Set the I2S State ready */\r\n      hi2s->State = HAL_I2S_STATE_READY; \r\n\r\n      /* Set the error code and execute error callback*/\r\n      hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;\r\n      HAL_I2S_ErrorCallback(hi2s);\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup I2S_Private_Functions I2S Private Functions\r\n  * @{\r\n  */\r\n/**\r\n  * @brief This function handles I2S Communication Timeout.\r\n  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @param Flag Flag checked\r\n  * @param State Value of the flag expected\r\n  * @param Timeout Duration of the timeout\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, \r\n                                                       uint32_t State, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  /* Wait until flag is set */\r\n  if(State == RESET)\r\n  {\r\n    while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)\r\n    {\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n        {\r\n          /* Set the I2S State ready */\r\n          hi2s->State= HAL_I2S_STATE_READY;\r\n\r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hi2s);\r\n\r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n  }\r\n  else\r\n  {\r\n    while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)\r\n    {\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n        {\r\n          /* Set the I2S State ready */\r\n          hi2s->State= HAL_I2S_STATE_READY;\r\n\r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hi2s);\r\n\r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n  }\r\n  return HAL_OK;    \r\n}\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup I2S_Exported_Functions I2S Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup  I2S_Exported_Functions_Group2 Input and Output operation functions \r\n  * @{\r\n  */\r\n/**\r\n  * @brief Tx Transfer Half completed callbacks\r\n  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @retval None\r\n  */\r\n __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2s);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_I2S_TxHalfCpltCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief Tx Transfer completed callbacks\r\n  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @retval None\r\n  */\r\n __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2s);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_I2S_TxCpltCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief Rx Transfer half completed callbacks\r\n  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @retval None\r\n  */\r\n__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2s);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_I2S_RxCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief Rx Transfer completed callbacks\r\n  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @retval None\r\n  */\r\n__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2s);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_I2S_RxCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief I2S error callbacks\r\n  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @retval None\r\n  */\r\n __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2s);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_I2S_ErrorCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions \r\n  *  @brief   Peripheral State functions \r\n  *\r\n@verbatim   \r\n ===============================================================================\r\n                      ##### Peripheral State and Errors functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection permits to get in run-time the status of the peripheral \r\n    and the data flow.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Return the I2S state\r\n  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @retval HAL state\r\n  */\r\nHAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)\r\n{\r\n  return hi2s->State;\r\n}\r\n\r\n/**\r\n  * @brief  Return the I2S error code\r\n  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @retval I2S Error Code\r\n  */\r\nuint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)\r\n{\r\n  return hi2s->ErrorCode;\r\n}\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n  /**\r\n  * @brief  Get I2S Input Clock based on I2S source clock selection\r\n  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains\r\n  *               the configuration information for I2S module.   \r\n  * @retval I2S Clock Input \r\n  */\r\nstatic uint32_t I2S_GetClockFreq(I2S_HandleTypeDef *hi2s)   \r\n{\r\n  uint32_t tmpreg = 0;\r\n  /* This variable used to store the VCO Input (value in Hz) */\r\n  uint32_t vcoinput = 0;\r\n  /* This variable used to store the I2S_CK_x (value in Hz) */\r\n  uint32_t i2sclocksource = 0;\r\n\r\n  /* Configure I2S Clock based on I2S source clock selection */ \r\n  \r\n  /* I2S_CLK_x : I2S Block Clock configuration for different clock sources selected */\r\n  switch(hi2s->Init.ClockSource)\r\n  {\r\n    case I2S_CLOCK_PLL :\r\n    {\r\n      /* Configure the PLLI2S division factor */\r\n      /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */ \r\n      if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)\r\n      {\r\n        /* In Case the PLL Source is HSI (Internal Clock) */\r\n        vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\r\n      }\r\n      else\r\n      {\r\n        /* In Case the PLL Source is HSE (External Clock) */\r\n        vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));\r\n      }\r\n\r\n      /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */\r\n      /* I2S_CLK(first level) = PLLI2S_VCO Output/PLLI2SR */\r\n      tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28;\r\n      i2sclocksource = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);\r\n    \r\n      break;\r\n    }\r\n    case I2S_CLOCK_EXTERNAL :\r\n    {\r\n      i2sclocksource = EXTERNAL_CLOCK_VALUE;\r\n      break;\r\n    }\r\n    default :\r\n    {\r\n      break;\r\n    }\r\n  }\r\n\r\n  /* the return result is the value of I2S clock */\r\n  return i2sclocksource; \r\n}\r\n\r\n/** @addtogroup I2S_Private_Functions I2S Private Functions\r\n  * @{\r\n  */\r\n/**\r\n  * @brief DMA I2S transmit process complete callback \r\n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)   \r\n{\r\n  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n  \r\n  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)\r\n  {\r\n    hi2s->TxXferCount = 0;\r\n\r\n    /* Disable Tx DMA Request */\r\n    hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);\r\n    \r\n    if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)\r\n    {\r\n      if(hi2s->RxXferCount == 0)\r\n      {\r\n        hi2s->State = HAL_I2S_STATE_READY;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      hi2s->State = HAL_I2S_STATE_READY; \r\n    }\r\n  }\r\n  HAL_I2S_TxCpltCallback(hi2s);\r\n}\r\n\r\n/**\r\n  * @brief DMA I2S transmit process half complete callback \r\n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n\r\n  HAL_I2S_TxHalfCpltCallback(hi2s);\r\n}\r\n\r\n/**\r\n  * @brief DMA I2S receive process complete callback \r\n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)   \r\n{\r\n  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n\r\n  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)\r\n  {\r\n    /* Disable Rx DMA Request */\r\n    hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);\r\n\r\n    hi2s->RxXferCount = 0;\r\n    if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)\r\n    {\r\n      if(hi2s->TxXferCount == 0)\r\n      {\r\n        hi2s->State = HAL_I2S_STATE_READY;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      hi2s->State = HAL_I2S_STATE_READY; \r\n    }\r\n  }\r\n  HAL_I2S_RxCpltCallback(hi2s); \r\n}\r\n      \r\n/**\r\n  * @brief DMA I2S receive process half complete callback \r\n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n\r\n  HAL_I2S_RxHalfCpltCallback(hi2s); \r\n}\r\n\r\n/**\r\n  * @brief DMA I2S communication error callback \r\n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void I2S_DMAError(DMA_HandleTypeDef *hdma)   \r\n{\r\n  I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  \r\n  /* Disable Rx and Tx DMA Request */\r\n  hi2s->Instance->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));\r\n  hi2s->TxXferCount = 0;\r\n  hi2s->RxXferCount = 0;\r\n  \r\n  hi2s->State= HAL_I2S_STATE_READY;\r\n\r\n  /* Set the error code and execute error callback*/\r\n  hi2s->ErrorCode |= HAL_I2S_ERROR_DMA;\r\n  HAL_I2S_ErrorCallback(hi2s);\r\n}\r\n\r\n/**\r\n  * @brief Transmit an amount of data in non-blocking mode with Interrupt\r\n  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @retval None\r\n  */\r\nstatic void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)\r\n{\r\n  /* Transmit data */\r\n  hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);\r\n  hi2s->TxXferCount--;\t\r\n\r\n  if(hi2s->TxXferCount == 0)\r\n  {\r\n    /* Disable TXE and ERR interrupt */\r\n    __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));\r\n\r\n    hi2s->State = HAL_I2S_STATE_READY;\r\n    HAL_I2S_TxCpltCallback(hi2s);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Receive an amount of data in non-blocking mode with Interrupt\r\n  * @param hi2s I2S handle\r\n  * @retval None\r\n  */\r\nstatic void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)\r\n{\r\n  /* Receive data */    \r\n  (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;\r\n  hi2s->RxXferCount--;\r\n\r\n  if(hi2s->RxXferCount == 0)\r\n  {    \r\n    /* Disable RXNE and ERR interrupt */\r\n    __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));\r\n\r\n    hi2s->State = HAL_I2S_STATE_READY;     \r\n    HAL_I2S_RxCpltCallback(hi2s); \r\n  }\r\n}\r\n/**\r\n  * @}\r\n  */\r\n  \r\n#endif /* HAL_I2S_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_iwdg.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_iwdg.c\r\n  * @author  MCD Application Team\r\n  * @brief   IWDG HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the Independent Watchdog (IWDG) peripheral:\r\n  *           + Initialization and Start functions\r\n  *           + IO operation functions\r\n  *\r\n  @verbatim\r\n  ==============================================================================\r\n                    ##### IWDG Generic features #####\r\n  ==============================================================================\r\n  [..]\r\n    (+) The IWDG can be started by either software or hardware (configurable\r\n        through option byte).\r\n\r\n    (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even\r\n        if the main clock fails.\r\n\r\n    (+) Once the IWDG is started, the LSI is forced ON and both can not be \r\n        disabled. The counter starts counting down from the reset value (0xFFF).\r\n        When it reaches the end of count value (0x000) a reset signal is \r\n        generated (IWDG reset).\r\n\r\n    (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register, \r\n        the IWDG_RLR value is reloaded in the counter and the watchdog reset is\r\n        prevented.\r\n\r\n    (+) The IWDG is implemented in the VDD voltage domain that is still functional\r\n        in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).\r\n        IWDGRST flag in RCC_CSR register can be used to inform when an IWDG\r\n        reset occurs.\r\n\r\n    (+) Debug mode : When the microcontroller enters debug mode (core halted),\r\n        the IWDG counter either continues to work normally or stops, depending \r\n        on DBG_IWDG_STOP configuration bit in DBG module, accessible through\r\n        __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros\r\n\r\n    [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s\r\n         The IWDG timeout may vary due to LSI frequency dispersion. STM32F7xx\r\n         devices provide the capability to measure the LSI frequency (LSI clock\r\n         connected internally to TIM16 CH1 input capture). The measured value\r\n         can be used to have an IWDG timeout with an acceptable accuracy.\r\n\r\n                     ##### How to use this driver #####\r\n  ==============================================================================\r\n  [..]\r\n    (#) Use IWDG using HAL_IWDG_Init() function to :\r\n      (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI \r\n           clock is forced ON and IWDG counter starts downcounting.\r\n      (++) Enable write access to configuration register: IWDG_PR, IWDG_RLR & \r\n           IWDG_WINR.\r\n      (++) Configure the IWDG prescaler and counter reload value. This reload \r\n           value will be loaded in the IWDG counter each time the watchdog is \r\n           reloaded, then the IWDG will start counting down from this value.\r\n      (++) wait for status flags to be reset\r\n      (++) Depending on window parameter:\r\n         (+++) If Window Init parameter is same as Window register value, \r\n               nothing more is done but reload counter value in order to exit \r\n               function withy exact time base.\r\n         (+++) Else modify Window register. This will automatically reload\r\n               watchdog counter.\r\n\r\n    (#) Then the application program must refresh the IWDG counter at regular\r\n        intervals during normal operation to prevent an MCU reset, using\r\n        HAL_IWDG_Refresh() function.\r\n\r\n     *** IWDG HAL driver macros list ***\r\n     ====================================\r\n     [..]\r\n       Below the list of most used macros in IWDG HAL driver:\r\n      (+) __HAL_IWDG_START: Enable the IWDG peripheral\r\n      (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in\r\n          the reload register\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_IWDG_MODULE_ENABLED\r\n/** @addtogroup IWDG\r\n  * @brief IWDG HAL module driver.\r\n  * @{\r\n  */\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @defgroup IWDG_Private_Defines IWDG Private Defines\r\n  * @{\r\n  */\r\n/* Status register need 5 RC LSI divided by prescaler clock to be updated. With \r\n   higher prescaler (256), and according to LSI variation, we need to wait at \r\n   least 6 cycles so 48 ms. */\r\n#define HAL_IWDG_DEFAULT_TIMEOUT            48u\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @addtogroup IWDG_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup IWDG_Exported_Functions_Group1\r\n *  @brief    Initialization and Start functions.\r\n *\r\n@verbatim\r\n ===============================================================================\r\n          ##### Initialization and Start functions #####\r\n ===============================================================================\r\n [..]  This section provides functions allowing to:\r\n      (+) Initialize the IWDG according to the specified parameters in the \r\n          IWDG_InitTypeDef of associated handle.\r\n      (+) Manage Window option.\r\n      (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog \r\n          is reloaded in order to exit function with correct time base.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initialize the IWDG according to the specified parameters in the \r\n  *         IWDG_InitTypeDef and start watchdog. Before exiting function, \r\n  *         watchdog is refreshed in order to have correct time base.\r\n  * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified IWDG module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)\r\n{\r\n  uint32_t tickstart;\r\n\r\n  /* Check the IWDG handle allocation */\r\n  if(hiwdg == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));\r\n  assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));\r\n  assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));\r\n  assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));\r\n\r\n  /* Enable IWDG. LSI is turned on automaticaly */\r\n  __HAL_IWDG_START(hiwdg);\r\n\r\n  /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing\r\n  0x5555 in KR */\r\n  IWDG_ENABLE_WRITE_ACCESS(hiwdg);\r\n\r\n  /* Write to IWDG registers the Prescaler & Reload values to work with */\r\n  hiwdg->Instance->PR = hiwdg->Init.Prescaler;\r\n  hiwdg->Instance->RLR = hiwdg->Init.Reload;\r\n\r\n  /* Check pending flag, if previous update not done, return timeout */\r\n  tickstart = HAL_GetTick();\r\n\r\n   /* Wait for register to be updated */\r\n  while(hiwdg->Instance->SR != RESET)\r\n  {\r\n    if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n\r\n  /* If window parameter is different than current value, modify window \r\n  register */\r\n  if(hiwdg->Instance->WINR != hiwdg->Init.Window)\r\n  {\r\n    /* Write to IWDG WINR the IWDG_Window value to compare with. In any case,\r\n    even if window feature is disabled, Watchdog will be reloaded by writing \r\n    windows register */\r\n    hiwdg->Instance->WINR = hiwdg->Init.Window;\r\n  }\r\n  else\r\n  {\r\n    /* Reload IWDG counter with value defined in the reload register */\r\n    __HAL_IWDG_RELOAD_COUNTER(hiwdg);\r\n  }\r\n\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @addtogroup IWDG_Exported_Functions_Group2\r\n *  @brief   IO operation functions\r\n *\r\n@verbatim\r\n ===============================================================================\r\n                      ##### IO operation functions #####\r\n ===============================================================================\r\n [..]  This section provides functions allowing to:\r\n      (+) Refresh the IWDG.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n\r\n/**\r\n  * @brief  Refresh the IWDG.\r\n  * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified IWDG module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)\r\n{\r\n  /* Reload IWDG counter with value defined in the reload register */\r\n  __HAL_IWDG_RELOAD_COUNTER(hiwdg);\r\n\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_IWDG_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_lptim.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_lptim.c\r\n  * @author  MCD Application Team\r\n  * @brief   LPTIM HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the Low Power Timer (LPTIM) peripheral:\r\n  *           + Initialization and de-initialization functions.\r\n  *           + Start/Stop operation functions in polling mode.\r\n  *           + Start/Stop operation functions in interrupt mode.\r\n  *           + Reading operation functions.\r\n  *           + Peripheral State functions.\r\n  *         \r\n  @verbatim\r\n  ==============================================================================\r\n                     ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]\r\n      The LPTIM HAL driver can be used as follows:\r\n\r\n      (#)Initialize the LPTIM low level resources by implementing the\r\n        HAL_LPTIM_MspInit():\r\n         (##) Enable the LPTIM interface clock using __LPTIMx_CLK_ENABLE().\r\n         (##) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):\r\n             (+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().\r\n             (+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().\r\n             (+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().\r\n    \r\n      (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function\r\n         configures mainly:\r\n         (##) The instance: LPTIM1.\r\n         (##) Clock: the counter clock.\r\n               (+++) Source: it can be either the ULPTIM input (IN1) or one of\r\n                              the internal clock; (APB, LSE, LSI or MSI).\r\n               (+++) Prescaler: select the clock divider.\r\n         (##)  UltraLowPowerClock : To be used only if the ULPTIM is selected\r\n               as counter clock source.\r\n               (+++) Polarity:   polarity of the active edge for the counter unit\r\n                               if the ULPTIM input is selected.\r\n               (+++) SampleTime: clock sampling time to configure the clock glitch\r\n                               filter.              \r\n         (##) Trigger: How the counter start.\r\n              (+++) Source: trigger can be software or one of the hardware triggers.\r\n              (+++) ActiveEdge: only for hardware trigger.\r\n              (+++) SampleTime: trigger sampling time to configure the trigger\r\n                                glitch filter.\r\n         (##) OutputPolarity: 2 opposite polarities are possibles.\r\n         (##) UpdateMode: specifies whether the update of the autoreload and\r\n              the compare values is done immediately or after the end of current\r\n              period.   \r\n    \r\n      (#)Six modes are available:\r\n      \r\n         (##) PWM Mode: To generate a PWM signal with specified period and pulse,\r\n         call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption\r\n         mode.\r\n         \r\n         (##) One Pulse Mode: To generate pulse with specified width in response\r\n         to a stimulus, call HAL_LPTIM_OnePulse_Start() or\r\n         HAL_LPTIM_OnePulse_Start_IT() for interruption mode.\r\n         \r\n         (##) Set once Mode: In this mode, the output changes the level (from\r\n         low level to high level if the output polarity is configured high, else\r\n         the opposite) when a compare match occurs. To start this mode, call \r\n         HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for\r\n         interruption mode.\r\n         \r\n         (##) Encoder Mode: To use the encoder interface call\r\n         HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for \r\n         interruption mode.\r\n         \r\n         (##) Time out Mode: an active edge on one selected trigger input rests\r\n         the counter. The first trigger event will start the timer, any\r\n         successive trigger event will reset the counter and the timer will\r\n         restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or \r\n         HAL_LPTIM_TimeOut_Start_IT() for interruption mode.\r\n         \r\n         (##) Counter Mode: counter can be used to count external events on\r\n         the LPTIM Input1 or it can be used to count internal clock cycles.\r\n         To start this mode, call HAL_LPTIM_Counter_Start() or \r\n         HAL_LPTIM_Counter_Start_IT() for interruption mode.             \r\n\r\n    \r\n      (#) User can stop any process by calling the corresponding API:\r\n          HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is\r\n          already started in interruption mode.\r\n         \r\n      (#) Call HAL_LPTIM_DeInit() to deinitialize the LPTIM peripheral.\r\n\r\n   *** Callback registration ***\r\n  =============================================\r\n\r\n  The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1\r\n  allows the user to configure dynamically the driver callbacks.\r\n\r\n  Use Function @ref HAL_LPTIM_RegisterCallback() to register a callback.\r\n  @ref HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle,\r\n  the Callback ID and a pointer to the user callback function.\r\n\r\n  Use function @ref HAL_LPTIM_UnRegisterCallback() to reset a callback to the default\r\n  weak function.\r\n  @ref HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle,\r\n  and the Callback ID.\r\n\r\n  These functions allow to register/unregister following callbacks:\r\n    (+) MspInitCallback         : LPTIM Msp Init Callback.\r\n    (+) MspDeInitCallback       : LPTIM Msp DeInit Callback.\r\n    (+) CompareMatchCallback    : LPTIM Compare Match Init Callback.\r\n    (+) AutoReloadMatchCallback : LPTIM Auto Reload Match Callback.\r\n    (+) TriggerCallback         : LPTIM Trigger Callback.\r\n    (+) CompareWriteCallback    : LPTIM Compare Write Callback.\r\n    (+) AutoReloadWriteCallback : LPTIM Auto Reload Write Callback.\r\n    (+) DirectionUpCallback     : LPTIM Direction Up Callback.\r\n    (+) DirectionDownCallback   : LPTIM Direction Down Callback.\r\n\r\n  By default, after the @ref HAL_LPTIM_Init and when the state is HAL_LPTIM_STATE_RESET\r\n  all interrupt callbacks are set to the corresponding weak functions:\r\n  examples @ref HAL_LPTIM_CompareMatchCallback(), @ref HAL_LPTIM_AutoReloadMatchCallback().\r\n\r\n  Exception done for MspInit and MspDeInit functions that are reset to the legacy weak\r\n  functionalities in the @ref HAL_LPTIM_Init/@ref HAL_LPTIM_DeInit only when these\r\n  callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null,\r\n  the @ref HAL_LPTIM_Init/@ref HAL_LPTIM_DeInit keep and use the user MspInit/MspDeInit\r\n  callbacks (registered beforehand)\r\n\r\n  Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only.\r\n  Exception done MspInit/MspDeInit that can be registered/unregistered\r\n  in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state, thus registered (user)\r\n  MspInit/DeInit callbacks can be used during the @ref HAL_LPTIM_Init/@ref HAL_LPTIM_DeInit.\r\n  In that case first register the MspInit/MspDeInit user callbacks using\r\n  @ref HAL_LPTIM_RegisterCallback() before calling DeInit or Init function.\r\n\r\n  When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or\r\n  not defined, the callback registration feature is not available and all callbacks\r\n  are set to the corresponding weak functions.\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************  \r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup LPTIM LPTIM\r\n  * @brief LPTIM HAL module driver.\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_LPTIM_MODULE_ENABLED\r\n/* Private types -------------------------------------------------------------*/\r\n/** @defgroup LPTIM_Private_Types LPTIM Private Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Private defines -----------------------------------------------------------*/\r\n/** @defgroup LPTIM_Private_Defines LPTIM Private Defines\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @addtogroup LPTIM_Private_Variables LPTIM Private Variables\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n \r\n/* Private constants ---------------------------------------------------------*/\r\n/** @addtogroup LPTIM_Private_Constants LPTIM Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Private macros ------------------------------------------------------------*/\r\n/** @addtogroup LPTIM_Private_Macros LPTIM Private Macros\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private function prototypes -----------------------------------------------*/\r\n/** @addtogroup LPTIM_Private_Functions_Prototypes LPTIM Private Functions Prototypes\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @addtogroup LPTIM_Private_Functions LPTIM Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Exported functions ---------------------------------------------------------*/\r\n/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup LPTIM_Group1 Initialization/de-initialization functions \r\n *  @brief    Initialization and Configuration functions. \r\n *\r\n@verbatim    \r\n  ==============================================================================\r\n              ##### Initialization and de-initialization functions #####\r\n  ==============================================================================\r\n    [..]  This section provides functions allowing to:\r\n      (+) Initialize the LPTIM according to the specified parameters in the\r\n          LPTIM_InitTypeDef and creates the associated handle.\r\n      (+) DeInitialize the LPTIM peripheral.\r\n      (+) Initialize the LPTIM MSP.\r\n      (+) DeInitialize LPTIM MSP. \r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the LPTIM according to the specified parameters in the\r\n  *         LPTIM_InitTypeDef and creates the associated handle.\r\n  * @param  hlptim LPTIM handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  uint32_t tmpcfgr = 0;\r\n\r\n  /* Check the LPTIM handle allocation */\r\n  if(hlptim == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  \r\n  assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));\r\n  assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));  \r\n  if ((hlptim->Init.Clock.Source) ==  LPTIM_CLOCKSOURCE_ULPTIM)\r\n  {\r\n    assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));\r\n    assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));\r\n  }  \r\n  assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));\r\n  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)\r\n  {\r\n    assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));\r\n    assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));\r\n  }  \r\n  assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));  \r\n  assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));\r\n  assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource));\r\n\r\n  if(hlptim->State == HAL_LPTIM_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    hlptim->Lock = HAL_UNLOCKED;\r\n\r\n#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)\r\n    /* Reset the LPTIM callback to the legacy weak callbacks */\r\n    hlptim->CompareMatchCallback    = HAL_LPTIM_CompareMatchCallback;\r\n    hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;\r\n    hlptim->TriggerCallback         = HAL_LPTIM_TriggerCallback;\r\n    hlptim->CompareWriteCallback    = HAL_LPTIM_CompareWriteCallback;\r\n    hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;\r\n    hlptim->DirectionUpCallback     = HAL_LPTIM_DirectionUpCallback;\r\n    hlptim->DirectionDownCallback   = HAL_LPTIM_DirectionDownCallback;\r\n\r\n    if(hlptim->MspInitCallback == NULL)\r\n    {\r\n      hlptim->MspInitCallback = HAL_LPTIM_MspInit;\r\n    }\r\n    /* Init the low level hardware : GPIO, CLOCK, NVIC */\r\n    hlptim->MspInitCallback(hlptim);\r\n#else\r\n    /* Init the low level hardware */\r\n    HAL_LPTIM_MspInit(hlptim);\r\n#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */\r\n  }\r\n  /* Change the LPTIM state */\r\n  hlptim->State = HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Get the LPTIMx CFGR value */\r\n  tmpcfgr = hlptim->Instance->CFGR;\r\n  \r\n  if ((hlptim->Init.Clock.Source) ==  LPTIM_CLOCKSOURCE_ULPTIM)\r\n  {\r\n    tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));\r\n  }\r\n  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)\r\n  {\r\n    tmpcfgr &= (uint32_t)(~ (LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));\r\n  }\r\n    \r\n  /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */\r\n  tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |\r\n                          LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE ));\r\n  \r\n  /* Set initialization parameters */\r\n  tmpcfgr |= (hlptim->Init.Clock.Source    |\r\n              hlptim->Init.Clock.Prescaler |\r\n              hlptim->Init.OutputPolarity  |\r\n              hlptim->Init.UpdateMode      |\r\n              hlptim->Init.CounterSource);\r\n  \r\n  if ((hlptim->Init.Clock.Source) ==  LPTIM_CLOCKSOURCE_ULPTIM)\r\n  {\r\n    tmpcfgr |=  (hlptim->Init.UltraLowPowerClock.Polarity |\r\n                hlptim->Init.UltraLowPowerClock.SampleTime);\r\n  } \r\n  \r\n  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)\r\n  {\r\n    /* Enable External trigger and set the trigger source */\r\n    tmpcfgr |= (hlptim->Init.Trigger.Source     |\r\n                hlptim->Init.Trigger.ActiveEdge |\r\n                hlptim->Init.Trigger.SampleTime);\r\n  }\r\n  \r\n  /* Write to LPTIMx CFGR */\r\n  hlptim->Instance->CFGR = tmpcfgr;\r\n\r\n  /* Change the LPTIM state */\r\n  hlptim->State = HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the LPTIM peripheral. \r\n  * @param  hlptim LPTIM handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Check the LPTIM handle allocation */\r\n  if(hlptim == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Change the LPTIM state */\r\n  hlptim->State = HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Disable the LPTIM Peripheral Clock */\r\n  __HAL_LPTIM_DISABLE(hlptim);\r\n\r\n#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)\r\n  if(hlptim->MspDeInitCallback == NULL)\r\n  {\r\n    hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;\r\n  }\r\n  /* DeInit the low level hardware */\r\n  hlptim->MspDeInitCallback(hlptim);\r\n#else\r\n  /* DeInit the low level hardware: CLOCK, NVIC.*/\r\n  HAL_LPTIM_MspDeInit(hlptim);\r\n#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */\r\n\r\n  /* Change the LPTIM state */\r\n  hlptim->State = HAL_LPTIM_STATE_RESET;\r\n  \r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hlptim);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the LPTIM MSP.\r\n  * @param  hlptim LPTIM handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hlptim);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_LPTIM_MspInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes LPTIM MSP.\r\n  * @param  hlptim LPTIM handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hlptim);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_LPTIM_MspDeInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LPTIM_Group2 LPTIM Start-Stop operation functions \r\n *  @brief   Start-Stop operation functions. \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                ##### LPTIM Start Stop operation functions #####\r\n  ==============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Start the PWM mode.\r\n      (+) Stop the PWM mode.\r\n      (+) Start the One pulse mode.\r\n      (+) Stop the One pulse mode.\r\n      (+) Start the Set once mode.\r\n      (+) Stop the Set once mode.\r\n      (+) Start the Encoder mode.\r\n      (+) Stop the Encoder mode.\r\n      (+) Start the Timeout mode.\r\n      (+) Stop the Timeout mode.      \r\n      (+) Start the Counter mode.\r\n      (+) Stop the Counter mode.\r\n      \r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n    \r\n/**\r\n  * @brief  Starts the LPTIM PWM generation.\r\n  * @param  hlptim  LPTIM handle\r\n  * @param  Period  Specifies the Autoreload value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @param  Pulse  Specifies the compare value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  assert_param(IS_LPTIM_PERIOD(Period));\r\n  assert_param(IS_LPTIM_PULSE(Pulse));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n \r\n  /* Reset WAVE bit to set PWM mode */\r\n  hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;\r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_LPTIM_ENABLE(hlptim);\r\n  \r\n  /* Load the period value in the autoreload register */\r\n  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r\n  \r\n  /* Load the pulse value in the compare register */\r\n  __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);\r\n  \r\n  /* Start timer in continuous mode */\r\n  __HAL_LPTIM_START_CONTINUOUS(hlptim);\r\n    \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the LPTIM PWM generation.\r\n  * @param  hlptim  LPTIM handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_LPTIM_DISABLE(hlptim);\r\n\r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the LPTIM PWM generation in interrupt mode.\r\n  * @param  hlptim  LPTIM handle\r\n  * @param  Period  Specifies the Autoreload value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF\r\n  * @param  Pulse  Specifies the compare value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  assert_param(IS_LPTIM_PERIOD(Period));\r\n  assert_param(IS_LPTIM_PULSE(Pulse));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n \r\n  /* Reset WAVE bit to set PWM mode */\r\n  hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;\r\n  \r\n  /* Enable Autoreload write complete interrupt */\r\n  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);\r\n  \r\n  /* Enable Compare write complete interrupt */\r\n  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);\r\n  \r\n  /* Enable Autoreload match interrupt */\r\n  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);\r\n  \r\n  /* Enable Compare match interrupt */\r\n  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);\r\n  \r\n  /* If external trigger source is used, then enable external trigger interrupt */\r\n  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)\r\n  {\r\n    /* Enable external trigger interrupt */\r\n    __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);\r\n  }  \r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_LPTIM_ENABLE(hlptim);\r\n  \r\n  /* Load the period value in the autoreload register */\r\n  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r\n  \r\n  /* Load the pulse value in the compare register */\r\n  __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);\r\n  \r\n  /* Start timer in continuous mode */\r\n  __HAL_LPTIM_START_CONTINUOUS(hlptim);\r\n    \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the LPTIM PWM generation in interrupt mode.\r\n  * @param  hlptim  LPTIM handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_LPTIM_DISABLE(hlptim);\r\n  \r\n    /* Disable Autoreload write complete interrupt */\r\n  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);\r\n  \r\n  /* Disable Compare write complete interrupt */\r\n  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);\r\n  \r\n  /* Disable Autoreload match interrupt */\r\n  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);\r\n  \r\n  /* Disable Compare match interrupt */\r\n  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);\r\n  \r\n  /* If external trigger source is used, then disable external trigger interrupt */\r\n  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)\r\n  {\r\n    /* Disable external trigger interrupt */\r\n    __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);\r\n  }  \r\n\r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the LPTIM One pulse generation.\r\n  * @param  hlptim  LPTIM handle\r\n  * @param  Period  Specifies the Autoreload value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @param  Pulse  Specifies the compare value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  assert_param(IS_LPTIM_PERIOD(Period));\r\n  assert_param(IS_LPTIM_PULSE(Pulse));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Reset WAVE bit to set one pulse mode */\r\n  hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;\r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_LPTIM_ENABLE(hlptim);\r\n  \r\n  /* Load the period value in the autoreload register */\r\n  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r\n  \r\n  /* Load the pulse value in the compare register */\r\n  __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);\r\n  \r\n  /* Start timer in continuous mode */\r\n  __HAL_LPTIM_START_SINGLE(hlptim);\r\n    \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the LPTIM One pulse generation.\r\n  * @param  hlptim  LPTIM handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_LPTIM_DISABLE(hlptim);\r\n\r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the LPTIM One pulse generation in interrupt mode.\r\n  * @param  hlptim  LPTIM handle\r\n  * @param  Period  Specifies the Autoreload value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @param  Pulse  Specifies the compare value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  assert_param(IS_LPTIM_PERIOD(Period));\r\n  assert_param(IS_LPTIM_PULSE(Pulse));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Reset WAVE bit to set one pulse mode */\r\n  hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;\r\n  \r\n  /* Enable Autoreload write complete interrupt */\r\n  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);\r\n  \r\n  /* Enable Compare write complete interrupt */\r\n  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);\r\n  \r\n  /* Enable Autoreload match interrupt */\r\n  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);\r\n  \r\n  /* Enable Compare match interrupt */\r\n  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);\r\n  \r\n  /* If external trigger source is used, then enable external trigger interrupt */\r\n  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)\r\n  {\r\n    /* Enable external trigger interrupt */\r\n    __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);\r\n  }\r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_LPTIM_ENABLE(hlptim);\r\n  \r\n  /* Load the period value in the autoreload register */\r\n  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r\n  \r\n  /* Load the pulse value in the compare register */\r\n  __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);\r\n  \r\n  /* Start timer in continuous mode */\r\n  __HAL_LPTIM_START_SINGLE(hlptim);\r\n    \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the LPTIM One pulse generation in interrupt mode.\r\n  * @param  hlptim  LPTIM handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_LPTIM_DISABLE(hlptim);\r\n  \r\n  /* Disable Autoreload write complete interrupt */\r\n  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);\r\n  \r\n  /* Disable Compare write complete interrupt */\r\n  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);\r\n  \r\n  /* Disable Autoreload match interrupt */\r\n  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);\r\n  \r\n  /* Disable Compare match interrupt */\r\n  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);\r\n  \r\n  /* If external trigger source is used, then disable external trigger interrupt */\r\n  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)\r\n  {\r\n    /* Disable external trigger interrupt */\r\n    __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);\r\n  }\r\n  \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the LPTIM in Set once mode.\r\n  * @param  hlptim  LPTIM handle\r\n  * @param  Period  Specifies the Autoreload value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @param  Pulse  Specifies the compare value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  assert_param(IS_LPTIM_PERIOD(Period));\r\n  assert_param(IS_LPTIM_PULSE(Pulse));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Set WAVE bit to enable the set once mode */\r\n  hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;\r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_LPTIM_ENABLE(hlptim);\r\n  \r\n  /* Load the period value in the autoreload register */\r\n  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r\n  \r\n  /* Load the pulse value in the compare register */\r\n  __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);\r\n  \r\n  /* Start timer in continuous mode */\r\n  __HAL_LPTIM_START_SINGLE(hlptim);\r\n    \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the LPTIM Set once mode.\r\n  * @param  hlptim  LPTIM handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_LPTIM_DISABLE(hlptim);\r\n\r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the LPTIM Set once mode in interrupt mode.\r\n  * @param  hlptim  LPTIM handle\r\n  * @param  Period  Specifies the Autoreload value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @param  Pulse  Specifies the compare value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  assert_param(IS_LPTIM_PERIOD(Period));\r\n  assert_param(IS_LPTIM_PULSE(Pulse));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Set WAVE bit to enable the set once mode */\r\n  hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;\r\n  \r\n  /* Enable Autoreload write complete interrupt */\r\n  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);\r\n  \r\n  /* Enable Compare write complete interrupt */\r\n  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);\r\n  \r\n  /* Enable Autoreload match interrupt */\r\n  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);\r\n  \r\n  /* Enable Compare match interrupt */\r\n  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);\r\n  \r\n  /* If external trigger source is used, then enable external trigger interrupt */\r\n  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)\r\n  {\r\n    /* Enable external trigger interrupt */\r\n    __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);\r\n  }  \r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_LPTIM_ENABLE(hlptim);\r\n  \r\n  /* Load the period value in the autoreload register */\r\n  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r\n  \r\n  /* Load the pulse value in the compare register */\r\n  __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);\r\n  \r\n  /* Start timer in continuous mode */\r\n  __HAL_LPTIM_START_SINGLE(hlptim);\r\n    \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the LPTIM Set once mode in interrupt mode.\r\n  * @param  hlptim  LPTIM handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_LPTIM_DISABLE(hlptim);\r\n\r\n  /* Disable Autoreload write complete interrupt */\r\n  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);\r\n  \r\n  /* Disable Compare write complete interrupt */\r\n  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);\r\n  \r\n  /* Disable Autoreload match interrupt */\r\n  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);\r\n  \r\n  /* Disable Compare match interrupt */\r\n  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);\r\n  \r\n  /* If external trigger source is used, then disable external trigger interrupt */\r\n  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)\r\n  {\r\n    /* Disable external trigger interrupt */\r\n    __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);\r\n  } \r\n  \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the Encoder interface.\r\n  * @param  hlptim  LPTIM handle\r\n  * @param  Period  Specifies the Autoreload value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)\r\n{\r\n  uint32_t tmpcfgr = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  assert_param(IS_LPTIM_PERIOD(Period));\r\n  assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);\r\n  assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);\r\n  assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));\r\n\r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n\r\n  /* Get the LPTIMx CFGR value */\r\n  tmpcfgr = hlptim->Instance->CFGR;\r\n\r\n  /* Clear CKPOL bits */\r\n  tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);\r\n\r\n  /* Set Input polarity */\r\n  tmpcfgr |=  hlptim->Init.UltraLowPowerClock.Polarity;\r\n\r\n  /* Write to LPTIMx CFGR */\r\n  hlptim->Instance->CFGR = tmpcfgr;\r\n\r\n  /* Set ENC bit to enable the encoder interface */\r\n  hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;\r\n\r\n  /* Enable the Peripheral */\r\n  __HAL_LPTIM_ENABLE(hlptim);\r\n\r\n  /* Load the period value in the autoreload register */\r\n  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r\n\r\n  /* Start timer in continuous mode */\r\n  __HAL_LPTIM_START_CONTINUOUS(hlptim);\r\n\r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the Encoder interface.\r\n  * @param  hlptim  LPTIM handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_LPTIM_DISABLE(hlptim);\r\n  \r\n  /* Reset ENC bit to disable the encoder interface */\r\n  hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;\r\n  \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the Encoder interface in interrupt mode.\r\n  * @param  hlptim  LPTIM handle\r\n  * @param  Period  Specifies the Autoreload value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)\r\n{\r\n  uint32_t tmpcfgr = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  assert_param(IS_LPTIM_PERIOD(Period));\r\n  assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);\r\n  assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);\r\n  assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));\r\n\r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Configure edge sensitivity for encoder mode */\r\n  /* Get the LPTIMx CFGR value */\r\n  tmpcfgr = hlptim->Instance->CFGR;\r\n\r\n  /* Clear CKPOL bits */\r\n  tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);\r\n\r\n  /* Set Input polarity */\r\n  tmpcfgr |=  hlptim->Init.UltraLowPowerClock.Polarity;\r\n\r\n  /* Write to LPTIMx CFGR */\r\n  hlptim->Instance->CFGR = tmpcfgr;\r\n\r\n  /* Set ENC bit to enable the encoder interface */\r\n  hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;\r\n\r\n  /* Enable \"switch to down direction\" interrupt */\r\n  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN);\r\n\r\n  /* Enable \"switch to up direction\" interrupt */\r\n  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP);  \r\n\r\n  /* Enable the Peripheral */\r\n  __HAL_LPTIM_ENABLE(hlptim);\r\n\r\n  /* Load the period value in the autoreload register */\r\n  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r\n\r\n  /* Start timer in continuous mode */\r\n  __HAL_LPTIM_START_CONTINUOUS(hlptim);\r\n\r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the Encoder interface in interrupt mode.\r\n  * @param  hlptim  LPTIM handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_LPTIM_DISABLE(hlptim);\r\n  \r\n  /* Reset ENC bit to disable the encoder interface */\r\n  hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;\r\n  \r\n  /* Disable \"switch to down direction\" interrupt */\r\n  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_DOWN);\r\n  \r\n  /* Disable \"switch to up direction\" interrupt */\r\n  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP); \r\n  \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the Timeout function. The first trigger event will start the\r\n  *         timer, any successive trigger event will reset the counter and\r\n  *         the timer restarts.\r\n  * @param  hlptim  LPTIM handle\r\n  * @param  Period  Specifies the Autoreload value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @param  Timeout  Specifies the TimeOut value to rest the counter.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  assert_param(IS_LPTIM_PERIOD(Period));\r\n  assert_param(IS_LPTIM_PULSE(Timeout));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n \r\n  /* Set TIMOUT bit to enable the timeout function */\r\n  hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;\r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_LPTIM_ENABLE(hlptim);\r\n  \r\n  /* Load the period value in the autoreload register */\r\n  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r\n  \r\n  /* Load the Timeout value in the compare register */\r\n  __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);\r\n  \r\n  /* Start timer in continuous mode */\r\n  __HAL_LPTIM_START_CONTINUOUS(hlptim);\r\n    \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the Timeout function.\r\n  * @param  hlptim  LPTIM handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_LPTIM_DISABLE(hlptim);\r\n  \r\n  /* Reset TIMOUT bit to enable the timeout function */\r\n  hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;\r\n  \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the Timeout function in interrupt mode. The first trigger \r\n  *         event will start the timer, any successive trigger event will reset\r\n  *         the counter and the timer restarts.\r\n  * @param  hlptim  LPTIM handle\r\n  * @param  Period  Specifies the Autoreload value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @param  Timeout  Specifies the TimeOut value to rest the counter.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  assert_param(IS_LPTIM_PERIOD(Period));\r\n  assert_param(IS_LPTIM_PULSE(Timeout));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n \r\n  /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */\r\n  __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(); \r\n  \r\n  /* Enable rising edge trigger on the LPTIM Wake-up Timer Exti line */\r\n  __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();\r\n \r\n  /* Set TIMOUT bit to enable the timeout function */\r\n  hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;\r\n  \r\n  /* Enable Compare match interrupt */\r\n  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);\r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_LPTIM_ENABLE(hlptim);\r\n  \r\n  /* Load the period value in the autoreload register */\r\n  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r\n  \r\n  /* Load the Timeout value in the compare register */\r\n  __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);\r\n  \r\n  /* Start timer in continuous mode */\r\n  __HAL_LPTIM_START_CONTINUOUS(hlptim);\r\n    \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the Timeout function in interrupt mode.\r\n  * @param  hlptim  LPTIM handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */ \r\n  __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\r\n  \r\n  /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */\r\n  __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(); \r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_LPTIM_DISABLE(hlptim);\r\n  \r\n  /* Reset TIMOUT bit to enable the timeout function */\r\n  hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;\r\n  \r\n  /* Disable Compare match interrupt */\r\n  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);\r\n  \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the Counter mode.\r\n  * @param  hlptim  LPTIM handle\r\n  * @param  Period  Specifies the Autoreload value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  assert_param(IS_LPTIM_PERIOD(Period));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */\r\n  if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))\r\n  {\r\n    /* Check if clock is prescaled */\r\n    assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));\r\n    /* Set clock prescaler to 0 */\r\n    hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;\r\n  }\r\n\r\n  /* Enable the Peripheral */\r\n  __HAL_LPTIM_ENABLE(hlptim);\r\n  \r\n  /* Load the period value in the autoreload register */\r\n  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r\n  \r\n  /* Start timer in continuous mode */\r\n  __HAL_LPTIM_START_CONTINUOUS(hlptim);\r\n    \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the Counter mode.\r\n  * @param  hlptim  LPTIM handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_LPTIM_DISABLE(hlptim);\r\n  \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the Counter mode in interrupt mode.\r\n  * @param  hlptim  LPTIM handle\r\n  * @param  Period  Specifies the Autoreload value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  assert_param(IS_LPTIM_PERIOD(Period));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n\r\n  /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */\r\n  __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(); \r\n  \r\n  /* Enable rising edge trigger on the LPTIM Wake-up Timer Exti line */\r\n  __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();  \r\n  \r\n  /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */\r\n  if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))\r\n  {\r\n    /* Check if clock is prescaled */\r\n    assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));\r\n    /* Set clock prescaler to 0 */\r\n    hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;\r\n  }\r\n  \r\n  /* Enable Autoreload write complete interrupt */\r\n  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);\r\n  \r\n  /* Enable Autoreload match interrupt */\r\n  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);\r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_LPTIM_ENABLE(hlptim);\r\n  \r\n  /* Load the period value in the autoreload register */\r\n  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r\n  \r\n  /* Start timer in continuous mode */\r\n  __HAL_LPTIM_START_CONTINUOUS(hlptim);\r\n    \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the Counter mode in interrupt mode.\r\n  * @param  hlptim  LPTIM handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */ \r\n  __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\r\n  \r\n  /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */\r\n  __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(); \r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_LPTIM_DISABLE(hlptim);\r\n  \r\n  /* Disable Autoreload write complete interrupt */\r\n  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);\r\n  \r\n  /* Disable Autoreload match interrupt */\r\n  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);\r\n  \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LPTIM_Group3 LPTIM Read operation functions \r\n *  @brief  Read operation functions.\r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                  ##### LPTIM Read operation functions #####\r\n  ==============================================================================  \r\n[..]  This section provides LPTIM Reading functions.\r\n      (+) Read the counter value.\r\n      (+) Read the period (Auto-reload) value.\r\n      (+) Read the pulse (Compare)value.\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  This function returns the current counter value.\r\n  * @param  hlptim LPTIM handle\r\n  * @retval Counter value.\r\n  */\r\nuint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n    /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  \r\n  return (hlptim->Instance->CNT);\r\n}\r\n\r\n/**\r\n  * @brief  This function return the current Autoreload (Period) value.\r\n  * @param  hlptim LPTIM handle\r\n  * @retval Autoreload value.\r\n  */\r\nuint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n    /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  \r\n  return (hlptim->Instance->ARR);\r\n}\r\n\r\n/**\r\n  * @brief  This function return the current Compare (Pulse) value.\r\n  * @param  hlptim LPTIM handle\r\n  * @retval Compare value.\r\n  */\r\nuint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n    /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  \r\n  return (hlptim->Instance->CMP);\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n\r\n/** @defgroup LPTIM_Group4 LPTIM IRQ handler \r\n *  @brief  LPTIM  IRQ handler.\r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                      ##### LPTIM IRQ handler  #####\r\n  ==============================================================================  \r\n[..]  This section provides LPTIM IRQ handler function.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  This function handles LPTIM interrupt request.\r\n  * @param  hlptim LPTIM handle\r\n  * @retval None\r\n  */\r\nvoid HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Compare match interrupt */\r\n  if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPM) != RESET)\r\n\t{\r\n    if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPM) !=RESET)\r\n\t\t{\r\n      /* Clear Compare match flag */\r\n      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPM);\r\n      /* Compare match Callback */\r\n#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)\r\n      hlptim->CompareMatchCallback(hlptim);\r\n#else\r\n      HAL_LPTIM_CompareMatchCallback(hlptim);      \r\n#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */\r\n    }\r\n  }\r\n  \r\n  /* Autoreload match interrupt */\r\n  if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET)\r\n\t{\r\n    if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) !=RESET)\r\n\t\t{\r\n      /* Clear Autoreload match flag */\r\n      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM);\r\n      /* Autoreload match Callback */\r\n#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)\r\n      hlptim->AutoReloadMatchCallback(hlptim);\r\n#else\r\n      HAL_LPTIM_AutoReloadMatchCallback(hlptim);      \r\n#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */\r\n    }\r\n  }\r\n  \r\n  /* Trigger detected interrupt */\r\n  if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET)\r\n\t{\r\n    if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) !=RESET)\r\n\t\t{\r\n      /* Clear Trigger detected flag */\r\n      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG);\r\n      /* Trigger detected callback */\r\n#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)\r\n      hlptim->TriggerCallback(hlptim);\r\n#else\r\n      HAL_LPTIM_TriggerCallback(hlptim);      \r\n#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */\r\n    }\r\n  }\r\n  \r\n  /* Compare write interrupt */\r\n  if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK) != RESET)\r\n\t{\r\n    if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CMPM) !=RESET)\r\n\t\t{\r\n      /* Clear Compare write flag */\r\n      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);\r\n      /* Compare write Callback */\r\n#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)\r\n      hlptim->CompareWriteCallback(hlptim);\r\n#else\r\n      HAL_LPTIM_CompareWriteCallback(hlptim);      \r\n#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */\r\n    }\r\n  }\r\n  \r\n  /* Autoreload write interrupt */\r\n  if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET)\r\n\t{\r\n    if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) !=RESET)\r\n\t\t{\r\n      /* Clear Autoreload write flag */\r\n      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);\r\n      /* Autoreload write Callback */\r\n#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)\r\n      hlptim->AutoReloadWriteCallback(hlptim);\r\n#else\r\n      HAL_LPTIM_AutoReloadWriteCallback(hlptim);      \r\n#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */\r\n    }\r\n  }\r\n  \r\n  /* Direction counter changed from Down to Up interrupt */\r\n  if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET)\r\n\t{\r\n    if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) !=RESET)\r\n\t\t{\r\n      /* Clear Direction counter changed from Down to Up flag */\r\n      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP);\r\n      /* Direction counter changed from Down to Up Callback */\r\n#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)\r\n      hlptim->DirectionUpCallback(hlptim);\r\n#else\r\n      HAL_LPTIM_DirectionUpCallback(hlptim);      \r\n#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */\r\n    }\r\n  }\r\n  \r\n  /* Direction counter changed from Up to Down interrupt */\r\n  if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET)\r\n\t{\r\n    if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) !=RESET)\r\n\t\t{\r\n      /* Clear Direction counter changed from Up to Down flag */\r\n      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN);\r\n      /* Direction counter changed from Up to Down Callback */\r\n#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)\r\n      hlptim->DirectionDownCallback(hlptim);\r\n#else\r\n      HAL_LPTIM_DirectionDownCallback(hlptim);      \r\n#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */\r\n    }\r\n  }\r\n  \r\n  __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG();\r\n}\r\n\r\n/**\r\n  * @brief  Compare match callback in non blocking mode \r\n  * @param  hlptim  LPTIM handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hlptim);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_LPTIM_CompareMatchCallback could be implemented in the user file\r\n   */  \r\n}\r\n\r\n/**\r\n  * @brief  Autoreload match callback in non blocking mode \r\n  * @param  hlptim  LPTIM handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hlptim);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file\r\n   */  \r\n}\r\n\r\n/**\r\n  * @brief  Trigger detected callback in non blocking mode \r\n  * @param  hlptim  LPTIM handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hlptim);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_LPTIM_TriggerCallback could be implemented in the user file\r\n   */  \r\n}\r\n\r\n/**\r\n  * @brief  Compare write callback in non blocking mode \r\n  * @param  hlptim  LPTIM handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hlptim);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_LPTIM_CompareWriteCallback could be implemented in the user file\r\n   */  \r\n}\r\n\r\n/**\r\n  * @brief  Autoreload write callback in non blocking mode \r\n  * @param  hlptim  LPTIM handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hlptim);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file\r\n   */  \r\n}\r\n\r\n/**\r\n  * @brief  Direction counter changed from Down to Up callback in non blocking mode \r\n  * @param  hlptim  LPTIM handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hlptim);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_LPTIM_DirectionUpCallback could be implemented in the user file\r\n   */  \r\n}\r\n\r\n/**\r\n  * @brief  Direction counter changed from Up to Down callback in non blocking mode \r\n  * @param  hlptim  LPTIM handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hlptim);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_LPTIM_DirectionDownCallback could be implemented in the user file\r\n   */  \r\n}\r\n\r\n#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)\r\n/**\r\n  * @brief  Register user LPTIM callback to be used instead of the weak predefined callback\r\n  * @param  hlptim lptim handle\r\n  * @param  CallbackID ID of the callback to be registered\r\n  *         This parameter can be one of the following values:\r\n  *          @arg @ref HAL_LPTIM_MSPINIT_CB_ID MspInit Callback ID\r\n  *          @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID MspDeInit Callback ID\r\n  *          @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare Match Callback ID\r\n  *          @arg @ref HAL_LPTIM_AUTO_RELOAD_MATCH_CB_ID Auto Reload Match Callback ID\r\n  *          @arg @ref HAL_LPTIM_TRIGGER_CB_ID Trigger Callback ID\r\n  *          @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare Write Callback ID\r\n  *          @arg @ref HAL_LPTIM_AUTO_RELOAD_WRITE_CB_ID Auto Reload Write Callback ID\r\n  *          @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Direction UP Callback ID\r\n  *          @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Direction Down Callback ID\r\n  * @param pCallback pointer to the callback function\r\n  * @retval status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  if(pCallback == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  /* Process locked */\r\n  __HAL_LOCK(hlptim);\r\n\r\n  if(hlptim->State == HAL_LPTIM_STATE_READY)\r\n  {\r\n    switch (CallbackID)\r\n    {\r\n    case HAL_LPTIM_MSPINIT_CB_ID :\r\n      hlptim->MspInitCallback         = pCallback;\r\n      break;\r\n\r\n    case HAL_LPTIM_MSPDEINIT_CB_ID :\r\n      hlptim->MspDeInitCallback       = pCallback;\r\n      break;\r\n\r\n    case HAL_LPTIM_COMPARE_MATCH_CB_ID :\r\n      hlptim->CompareMatchCallback    = pCallback;\r\n      break;\r\n\r\n    case HAL_LPTIM_AUTO_RELOAD_MATCH_CB_ID :\r\n      hlptim->AutoReloadMatchCallback = pCallback;\r\n      break;\r\n\r\n    case HAL_LPTIM_TRIGGER_CB_ID :\r\n      hlptim->TriggerCallback         = pCallback;\r\n      break;\r\n\r\n    case HAL_LPTIM_COMPARE_WRITE_CB_ID :\r\n      hlptim->CompareWriteCallback    = pCallback;\r\n      break;\r\n\r\n    case HAL_LPTIM_AUTO_RELOAD_WRITE_CB_ID :\r\n      hlptim->AutoReloadWriteCallback = pCallback;\r\n      break;\r\n\r\n    case HAL_LPTIM_DIRECTION_UP_CB_ID :\r\n      hlptim->DirectionUpCallback     = pCallback;\r\n      break;\r\n\r\n    case HAL_LPTIM_DIRECTION_DOWN_CB_ID :\r\n      hlptim->DirectionDownCallback   = pCallback;\r\n      break;\r\n\r\n    default :\r\n      /* Return error status */\r\n      status =  HAL_ERROR;\r\n      break;\r\n    }\r\n  }\r\n  else if(hlptim->State == HAL_LPTIM_STATE_RESET)\r\n  {\r\n    switch (CallbackID)\r\n    {\r\n    case HAL_LPTIM_MSPINIT_CB_ID :\r\n      hlptim->MspInitCallback         = pCallback;\r\n      break;\r\n\r\n    case HAL_LPTIM_MSPDEINIT_CB_ID :\r\n      hlptim->MspDeInitCallback       = pCallback;\r\n      break;\r\n\r\n    default :\r\n      /* Return error status */\r\n      status =  HAL_ERROR;\r\n      break;\r\n    }\r\n  }\r\n  else\r\n  {\r\n    /* Return error status */\r\n    status =  HAL_ERROR;\r\n  }\r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hlptim);\r\n\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  UnRegister user LPTIM callback\r\n  *         LPTIM callback is redirected to the weak predefined callback\r\n  * @param  hlptim lptim handle\r\n  * @param  CallbackID ID of the callback to be unregistered\r\n+  *         This parameter can be one of the following values:\r\n+  *          @arg @ref HAL_LPTIM_MSPINIT_CB_ID MspInit Callback ID\r\n+  *          @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID MspDeInit Callback ID\r\n+  *          @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare Match Callback ID\r\n+  *          @arg @ref HAL_LPTIM_AUTO_RELOAD_MATCH_CB_ID Auto Reload Match Callback ID\r\n+  *          @arg @ref HAL_LPTIM_TRIGGER_CB_ID Trigger Callback ID\r\n+  *          @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare Write Callback ID\r\n+  *          @arg @ref HAL_LPTIM_AUTO_RELOAD_WRITE_CB_ID Auto Reload Write Callback ID\r\n+  *          @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Direction UP Callback ID\r\n+  *          @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Direction Down Callback ID\r\n  * @retval status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hlptim);\r\n\r\n  if(hlptim->State == HAL_LPTIM_STATE_READY)\r\n  {\r\n    switch (CallbackID)\r\n    {\r\n    case HAL_LPTIM_MSPINIT_CB_ID :\r\n      hlptim->MspInitCallback         = HAL_LPTIM_MspInit;                 /* Legacy weak MspInit Callback */\r\n      break;\r\n\r\n    case HAL_LPTIM_MSPDEINIT_CB_ID :\r\n      hlptim->MspDeInitCallback       = HAL_LPTIM_MspDeInit;               /* Legacy weak MspDeInit Callback */\r\n      break;\r\n\r\n    case HAL_LPTIM_COMPARE_MATCH_CB_ID :\r\n      hlptim->CompareMatchCallback    = HAL_LPTIM_CompareMatchCallback;    /* Legacy weak Compare Match Callback */\r\n      break;\r\n\r\n    case HAL_LPTIM_AUTO_RELOAD_MATCH_CB_ID :\r\n      hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Legacy weak Auto Reload Match Callback */\r\n      break;\r\n\r\n    case HAL_LPTIM_TRIGGER_CB_ID :\r\n      hlptim->TriggerCallback         = HAL_LPTIM_TriggerCallback;         /* Legacy weak Trigger Callback */\r\n      break;\r\n\r\n    case HAL_LPTIM_COMPARE_WRITE_CB_ID :\r\n      hlptim->CompareWriteCallback    = HAL_LPTIM_CompareWriteCallback;    /* Legacy weak Compare Write Callback */\r\n      break;\r\n\r\n    case HAL_LPTIM_AUTO_RELOAD_WRITE_CB_ID :\r\n      hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Legacy weak Auto Reload Write Callback */\r\n      break;\r\n\r\n    case HAL_LPTIM_DIRECTION_UP_CB_ID :\r\n      hlptim->DirectionUpCallback     = HAL_LPTIM_DirectionUpCallback;     /* Legacy weak Direction Up Callback */\r\n      break;\r\n\r\n    case HAL_LPTIM_DIRECTION_DOWN_CB_ID :\r\n      hlptim->DirectionDownCallback   = HAL_LPTIM_DirectionDownCallback;   /* Legacy weak Direction Down Callback */\r\n      break;\r\n\r\n    default :\r\n     /* Return error status */\r\n      status =  HAL_ERROR;\r\n      break;\r\n    }\r\n  }\r\n  else if(hlptim->State == HAL_LPTIM_STATE_RESET)\r\n  {\r\n    switch (CallbackID)\r\n    {\r\n    case HAL_LPTIM_MSPINIT_CB_ID :\r\n      hlptim->MspInitCallback       = HAL_LPTIM_MspInit;                   /* Legacy weak MspInit Callback */\r\n      break;\r\n\r\n    case HAL_LPTIM_MSPDEINIT_CB_ID :\r\n      hlptim->MspDeInitCallback     = HAL_LPTIM_MspDeInit;                 /* Legacy weak MspDeInit Callback */\r\n      break;\r\n\r\n    default :\r\n     /* Return error status */\r\n      status =  HAL_ERROR;\r\n      break;\r\n    }\r\n  }\r\n  else\r\n  {\r\n    /* Return error status */\r\n    status =  HAL_ERROR;\r\n  }\r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hlptim);\r\n\r\n  return status;\r\n}\r\n#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LPTIM_Group5 Peripheral State functions \r\n *  @brief   Peripheral State functions. \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                      ##### Peripheral State functions #####\r\n  ==============================================================================  \r\n    [..]\r\n    This subsection permits to get in run-time the status of the peripheral.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Returns the LPTIM state.\r\n  * @param  hlptim LPTIM handle\r\n  * @retval HAL state\r\n  */\r\nHAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  return hlptim->State;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_LPTIM_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_ltdc.c\r\n  * @author  MCD Application Team\r\n  * @brief   LTDC HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the LTDC peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + IO operation functions\r\n  *           + Peripheral Control functions  \r\n  *           + Peripheral State and Errors functions\r\n  *           \r\n  @verbatim      \r\n  ==============================================================================\r\n                        ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]\r\n     (#) Program the required configuration through the following parameters:   \r\n         the LTDC timing, the horizontal and vertical polarity, \r\n         the pixel clock polarity, Data Enable polarity and the LTDC background color value \r\n         using HAL_LTDC_Init() function\r\n\r\n     (#) Program the required configuration through the following parameters:   \r\n         the pixel format, the blending factors, input alpha value, the window size \r\n         and the image size using HAL_LTDC_ConfigLayer() function for foreground\r\n         or/and background layer.     \r\n  \r\n     (#) Optionally, configure and enable the CLUT using HAL_LTDC_ConfigCLUT() and \r\n         HAL_LTDC_EnableCLUT functions.\r\n       \r\n     (#) Optionally, enable the Dither using HAL_LTDC_EnableDither().       \r\n\r\n     (#) Optionally, configure and enable the Color keying using HAL_LTDC_ConfigColorKeying()\r\n         and HAL_LTDC_EnableColorKeying functions.\r\n\r\n     (#) Optionally, configure LineInterrupt using HAL_LTDC_ProgramLineEvent()\r\n         function\r\n\r\n     (#) If needed, reconfigure and change the pixel format value, the alpha value\r\n         value, the window size, the window position and the layer start address \r\n         for foreground or/and background layer using respectively the following \r\n         functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(),\r\n         HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetAddress.\r\n\r\n     (#) Variant functions with \"_NoReload\" post fix allows to set the LTDC configuration/settings without immediate reload.\r\n         This is useful in case when the program requires to modify serval LTDC settings (on one or both layers) \r\n         then applying(reload) these settings in one shot by calling the function \"HAL_LTDC_Reload\"\r\n\r\n         After calling the \"_NoReload\" functions to set different color/format/layer settings, \r\n         the program can call the function \"HAL_LTDC_Reload\" To apply(Reload) these settings. \r\n         Function \"HAL_LTDC_Reload\" can be called with the parameter \"ReloadType\" \r\n         set to LTDC_RELOAD_IMMEDIATE if an immediate reload is required.\r\n         Function \"HAL_LTDC_Reload\" can be called with the parameter \"ReloadType\" \r\n         set to LTDC_RELOAD_VERTICAL_BLANKING if the reload should be done in the next vertical blanking period, \r\n         this option allows to avoid display flicker by applying the new settings during the vertical blanking period.\r\n           \r\n                     \r\n     (#) To control LTDC state you can use the following function: HAL_LTDC_GetState()               \r\n\r\n     *** LTDC HAL driver macros list ***\r\n     ============================================= \r\n     [..]\r\n       Below the list of most used macros in LTDC HAL driver.\r\n       \r\n      (+) __HAL_LTDC_ENABLE: Enable the LTDC.\r\n      (+) __HAL_LTDC_DISABLE: Disable the LTDC.\r\n      (+) __HAL_LTDC_LAYER_ENABLE: Enable the LTDC Layer.\r\n      (+) __HAL_LTDC_LAYER_DISABLE: Disable the LTDC Layer.\r\n      (+) __HAL_LTDC_RELOAD_CONFIG: Reload  Layer Configuration.\r\n      (+) __HAL_LTDC_GET_FLAG: Get the LTDC pending flags.\r\n      (+) __HAL_LTDC_CLEAR_FLAG: Clear the LTDC pending flags.\r\n      (+) __HAL_LTDC_ENABLE_IT: Enable the specified LTDC interrupts. \r\n      (+) __HAL_LTDC_DISABLE_IT: Disable the specified LTDC interrupts.\r\n      (+) __HAL_LTDC_GET_IT_SOURCE: Check whether the specified LTDC interrupt has occurred or not.\r\n      \r\n     [..] \r\n       (@) You can refer to the LTDC HAL driver header file for more useful macros\r\n  \r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r\n\r\n/** @defgroup LTDC LTDC\r\n  * @brief LTDC HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_LTDC_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/    \r\n/* Private function prototypes -----------------------------------------------*/\r\nstatic void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup LTDC_Exported_Functions LTDC Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup LTDC_Exported_Functions_Group1 Initialization and Configuration functions\r\n *  @brief   Initialization and Configuration functions\r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                ##### Initialization and Configuration functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Initialize and configure the LTDC\r\n      (+) De-initialize the LTDC \r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @brief  Initializes the LTDC according to the specified\r\n  *         parameters in the LTDC_InitTypeDef and create the associated handle.\r\n  * @param  hltdc pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                the configuration information for the LTDC.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)\r\n{\r\n  uint32_t tmp = 0, tmp1 = 0;\r\n\r\n  /* Check the LTDC peripheral state */\r\n  if(hltdc == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check function parameters */\r\n  assert_param(IS_LTDC_ALL_INSTANCE(hltdc->Instance));\r\n  assert_param(IS_LTDC_HSYNC(hltdc->Init.HorizontalSync));\r\n  assert_param(IS_LTDC_VSYNC(hltdc->Init.VerticalSync));\r\n  assert_param(IS_LTDC_AHBP(hltdc->Init.AccumulatedHBP));\r\n  assert_param(IS_LTDC_AVBP(hltdc->Init.AccumulatedVBP));\r\n  assert_param(IS_LTDC_AAH(hltdc->Init.AccumulatedActiveH));\r\n  assert_param(IS_LTDC_AAW(hltdc->Init.AccumulatedActiveW));\r\n  assert_param(IS_LTDC_TOTALH(hltdc->Init.TotalHeigh));\r\n  assert_param(IS_LTDC_TOTALW(hltdc->Init.TotalWidth));\r\n  assert_param(IS_LTDC_HSPOL(hltdc->Init.HSPolarity));\r\n  assert_param(IS_LTDC_VSPOL(hltdc->Init.VSPolarity));\r\n  assert_param(IS_LTDC_DEPOL(hltdc->Init.DEPolarity));\r\n  assert_param(IS_LTDC_PCPOL(hltdc->Init.PCPolarity));\r\n\r\n  if(hltdc->State == HAL_LTDC_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    hltdc->Lock = HAL_UNLOCKED;\r\n    /* Init the low level hardware */\r\n    HAL_LTDC_MspInit(hltdc);\r\n  }\r\n  \r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Configures the HS, VS, DE and PC polarity */\r\n  hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL);\r\n  hltdc->Instance->GCR |=  (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \\\r\n  hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);\r\n\r\n  /* Sets Synchronization size */\r\n  hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW);\r\n  tmp = (hltdc->Init.HorizontalSync << 16);\r\n  hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync);\r\n\r\n  /* Sets Accumulated Back porch */\r\n  hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP);\r\n  tmp = (hltdc->Init.AccumulatedHBP << 16);\r\n  hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP);\r\n\r\n  /* Sets Accumulated Active Width */\r\n  hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW);\r\n  tmp = (hltdc->Init.AccumulatedActiveW << 16);\r\n  hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH);\r\n\r\n  /* Sets Total Width */\r\n  hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW);\r\n  tmp = (hltdc->Init.TotalWidth << 16);\r\n  hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh);\r\n\r\n  /* Sets the background color value */\r\n  tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8);\r\n  tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16);\r\n  hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED);\r\n  hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue);\r\n\r\n  /* Enable the transfer Error interrupt */\r\n  __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE);\r\n\r\n  /* Enable the FIFO underrun interrupt */\r\n  __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_FU);\r\n\r\n  /* Enable LTDC by setting LTDCEN bit */\r\n  __HAL_LTDC_ENABLE(hltdc);\r\n\r\n  /* Initialize the error code */\r\n  hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;  \r\n\r\n  /* Initialize the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Deinitializes the LTDC peripheral registers to their default reset\r\n  *         values.\r\n  * @param  hltdc pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                the configuration information for the LTDC.\r\n  * @retval None\r\n  */\r\n\r\nHAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc)\r\n{\r\n  /* DeInit the low level hardware */\r\n  HAL_LTDC_MspDeInit(hltdc); \r\n\r\n  /* Initialize the error code */\r\n  hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;\r\n\r\n  /* Initialize the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_RESET;\r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the LTDC MSP.\r\n  * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                the configuration information for the LTDC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hltdc);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_LTDC_MspInit could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the LTDC MSP.\r\n  * @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                the configuration information for the LTDC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hltdc);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_LTDC_MspDeInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup LTDC_Exported_Functions_Group2 IO operation functions \r\n *  @brief   IO operation functions  \r\n *\r\n@verbatim\r\n ===============================================================================\r\n                      #####  IO operation functions  #####\r\n ===============================================================================  \r\n    [..]  This section provides function allowing to:\r\n      (+) Handle LTDC interrupt request\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n/**\r\n  * @brief  Handles LTDC interrupt request.\r\n  * @param  hltdc pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                the configuration information for the LTDC.  \r\n  * @retval HAL status\r\n  */\r\nvoid HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc)\r\n{\r\n  /* Transfer Error Interrupt management ***************************************/\r\n  if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_TE) != RESET)\r\n  {\r\n    if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_TE) != RESET)\r\n    {\r\n      /* Disable the transfer Error interrupt */\r\n      __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE);\r\n\r\n      /* Clear the transfer error flag */\r\n      __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE);\r\n\r\n      /* Update error code */\r\n      hltdc->ErrorCode |= HAL_LTDC_ERROR_TE;\r\n\r\n      /* Change LTDC state */\r\n      hltdc->State = HAL_LTDC_STATE_ERROR;\r\n\r\n      /* Process unlocked */\r\n      __HAL_UNLOCK(hltdc);\r\n\r\n      /* Transfer error Callback */\r\n      HAL_LTDC_ErrorCallback(hltdc);\r\n    }\r\n  }\r\n  /* FIFO underrun Interrupt management ***************************************/\r\n  if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_FU) != RESET)\r\n  {\r\n    if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_FU) != RESET)\r\n    {\r\n      /* Disable the FIFO underrun interrupt */\r\n      __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU);\r\n\r\n      /* Clear the FIFO underrun flag */\r\n      __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU);\r\n\r\n      /* Update error code */\r\n      hltdc->ErrorCode |= HAL_LTDC_ERROR_FU;\r\n\r\n      /* Change LTDC state */\r\n      hltdc->State = HAL_LTDC_STATE_ERROR;\r\n\r\n      /* Process unlocked */\r\n      __HAL_UNLOCK(hltdc);\r\n      \r\n      /* Transfer error Callback */\r\n      HAL_LTDC_ErrorCallback(hltdc);\r\n    }\r\n  }\r\n  /* Line Interrupt management ************************************************/\r\n  if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_LI) != RESET)\r\n  {\r\n    if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_LI) != RESET)\r\n    {\r\n      /* Disable the Line interrupt */\r\n      __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI);\r\n\r\n      /* Clear the Line interrupt flag */  \r\n      __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI);\r\n\r\n      /* Change LTDC state */\r\n      hltdc->State = HAL_LTDC_STATE_READY;\r\n\r\n      /* Process unlocked */\r\n      __HAL_UNLOCK(hltdc);\r\n\r\n      /* Line interrupt Callback */\r\n      HAL_LTDC_LineEventCallback(hltdc);\r\n    }\r\n  }\r\n  /* Register reload Interrupt management ***************************************/\r\n  if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_RR) != RESET)\r\n  {\r\n    if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_RR) != RESET)\r\n    {\r\n      /* Disable the register reload interrupt */\r\n      __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR);\r\n      \r\n      /* Clear the register reload flag */\r\n      __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR);\r\n      \r\n      /* Change LTDC state */\r\n      hltdc->State = HAL_LTDC_STATE_READY;\r\n      \r\n      /* Process unlocked */\r\n      __HAL_UNLOCK(hltdc);\r\n      \r\n      /* Register reload interrupt Callback */\r\n      HAL_LTDC_ReloadEventCallback(hltdc);\r\n    }\r\n  }  \r\n}\r\n\r\n/**\r\n  * @brief  Error LTDC callback.\r\n  * @param  hltdc pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                the configuration information for the LTDC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hltdc);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_LTDC_ErrorCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Line Event callback.\r\n  * @param  hltdc pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                the configuration information for the LTDC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hltdc);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_LTDC_LineEventCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Reload Event callback.\r\n  * @param  hltdc pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                the configuration information for the LTDC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hltdc);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_LTDC_ReloadEvenCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LTDC_Exported_Functions_Group3 Peripheral Control functions\r\n *  @brief    Peripheral Control functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                    ##### Peripheral Control functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Configure the LTDC foreground or/and background parameters.\r\n      (+) Set the active layer.\r\n      (+) Configure the color keying.\r\n      (+) Configure the C-LUT.\r\n      (+) Enable / Disable the color keying.\r\n      (+) Enable / Disable the C-LUT.\r\n      (+) Update the layer position.\r\n      (+) Update the layer size.\r\n      (+) Update pixel format on the fly. \r\n      (+) Update transparency on the fly.\r\n      (+) Update address on the fly.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Configure the LTDC Layer according to the specified\r\n  *         parameters in the LTDC_InitTypeDef and create the associated handle.\r\n  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                    the configuration information for the LTDC.\r\n  * @param  pLayerCfg pointer to a LTDC_LayerCfgTypeDef structure that contains\r\n  *                    the configuration information for the Layer.\r\n  * @param  LayerIdx  LTDC Layer index.\r\n  *                    This parameter can be one of the following values:\r\n  *                    0 or 1\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)\r\n{   \r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n  \r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n  assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat));\r\n  assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1));\r\n  assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));\r\n  assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));\r\n  assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));\r\n  assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));\r\n  assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));\r\n  assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0));\r\n  assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));\r\n  assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));\r\n\r\n  /* Copy new layer configuration into handle structure */\r\n  hltdc->LayerCfg[LayerIdx] = *pLayerCfg;  \r\n\r\n  /* Configure the LTDC Layer */  \r\n  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);\r\n\r\n  /* Sets the Reload type */\r\n  hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r\n\r\n  /* Initialize the LTDC state*/\r\n  hltdc->State  = HAL_LTDC_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Configure the color keying.\r\n  * @param  hltdc    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  RGBValue the color key value\r\n  * @param  LayerIdx  LTDC Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0 or 1\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n\r\n  /* Configures the default color values */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CKCR &=  ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED);\r\n  LTDC_LAYER(hltdc, LayerIdx)->CKCR  = RGBValue;\r\n\r\n  /* Sets the Reload type */\r\n  hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Load the color lookup table.\r\n  * @param  hltdc    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  pCLUT    pointer to the color lookup table address.\r\n  * @param  CLUTSize the color lookup table size.  \r\n  * @param  LayerIdx  LTDC Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0 or 1\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx)\r\n{\r\n  uint32_t tmp = 0;\r\n  uint32_t counter = 0;\r\n  uint32_t pcounter = 0;\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;  \r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx)); \r\n\r\n  for(counter = 0; (counter < CLUTSize); counter++)\r\n  {\r\n    if(hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44)\r\n    {\r\n      tmp  = (((counter + 16*counter) << 24) | ((uint32_t)(*pCLUT) & 0xFF) | ((uint32_t)(*pCLUT) & 0xFF00) | ((uint32_t)(*pCLUT) & 0xFF0000));\r\n    }\r\n    else\r\n    { \r\n      tmp  = ((counter << 24) | ((uint32_t)(*pCLUT) & 0xFF) | ((uint32_t)(*pCLUT) & 0xFF00) | ((uint32_t)(*pCLUT) & 0xFF0000));\r\n    }\r\n    pcounter = (uint32_t)pCLUT + sizeof(*pCLUT);\r\n    pCLUT = (uint32_t *)pcounter;\r\n\r\n    /* Specifies the C-LUT address and RGB value */\r\n    LTDC_LAYER(hltdc, LayerIdx)->CLUTWR  = tmp;\r\n  }\r\n  \r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY; \r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);  \r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Enable the color keying.\r\n  * @param  hltdc    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  LayerIdx  LTDC Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0 or 1\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)\r\n{  \r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n\r\n  /* Enable LTDC color keying by setting COLKEN bit */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN;\r\n\r\n  /* Sets the Reload type */\r\n  hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY; \r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;  \r\n}\r\n  \r\n/**\r\n  * @brief  Disable the color keying.\r\n  * @param  hltdc    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  LayerIdx  LTDC Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0 or 1\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n\r\n  /* Disable LTDC color keying by setting COLKEN bit */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN;\r\n\r\n  /* Sets the Reload type */\r\n  hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY; \r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Enable the color lookup table.\r\n  * @param  hltdc    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  LayerIdx  LTDC Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0 or 1\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)\r\n{\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n\r\n  /* Disable LTDC color lookup table by setting CLUTEN bit */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN;\r\n\r\n  /* Sets the Reload type */\r\n  hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY; \r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Disable the color lookup table.\r\n  * @param  hltdc    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  LayerIdx  LTDC Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0 or 1   \r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)\r\n{\r\n \r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n\r\n  /* Disable LTDC color lookup table by setting CLUTEN bit */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN;\r\n\r\n  /* Sets the Reload type */\r\n  hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY; \r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Enables Dither.\r\n  * @param  hltdc pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                the configuration information for the LTDC.\r\n  * @retval  HAL status\r\n  */\r\n\r\nHAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Enable Dither by setting DTEN bit */\r\n  LTDC->GCR |= (uint32_t)LTDC_GCR_DEN;\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY; \r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Disables Dither.\r\n  * @param  hltdc pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                the configuration information for the LTDC.\r\n  * @retval  HAL status\r\n  */\r\n\r\nHAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Disable Dither by setting DTEN bit */\r\n  LTDC->GCR &= ~(uint32_t)LTDC_GCR_DEN;\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Set the LTDC window size.\r\n  * @param  hltdc    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  XSize    LTDC Pixel per line\r\n  * @param  YSize    LTDC Line number\r\n  * @param  LayerIdx  LTDC Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0 or 1\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) \r\n{\r\n  LTDC_LayerCfgTypeDef *pLayerCfg;\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY; \r\n\r\n  /* Get layer configuration from handle structure */\r\n  pLayerCfg = &hltdc->LayerCfg[LayerIdx];\r\n\r\n  /* Check the parameters (Layers parameters)*/\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n  assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));\r\n  assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));\r\n  assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));\r\n  assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));\r\n  assert_param(IS_LTDC_CFBLL(XSize));\r\n  assert_param(IS_LTDC_CFBLNBR(YSize));\r\n\r\n  /* update horizontal start/stop */\r\n  pLayerCfg->WindowX0 = 0;\r\n  pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0;\r\n\r\n  /* update vertical start/stop */  \r\n  pLayerCfg->WindowY0 = 0;\r\n  pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0;\r\n\r\n  /* Reconfigures the color frame buffer pitch in byte */\r\n  pLayerCfg->ImageWidth = XSize;\r\n\r\n  /* Reconfigures the frame buffer line number */\r\n  pLayerCfg->ImageHeight = YSize;\r\n\r\n  /* Set LTDC parameters */\r\n  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);\r\n\r\n  /* Sets the Reload type */\r\n  hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Set the LTDC window position.\r\n  * @param  hltdc    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  X0       LTDC window X offset\r\n  * @param  Y0       LTDC window Y offset\r\n  * @param  LayerIdx  LTDC Layer index.\r\n  *                         This parameter can be one of the following values:\r\n  *                         0 or 1\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)\r\n{\r\n  LTDC_LayerCfgTypeDef *pLayerCfg;\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Get layer configuration from handle structure */\r\n  pLayerCfg = &hltdc->LayerCfg[LayerIdx];\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n  assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));\r\n  assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));\r\n  assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));\r\n  assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));\r\n\r\n  /* update horizontal start/stop */\r\n  pLayerCfg->WindowX0 = X0;\r\n  pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth;\r\n\r\n  /* update vertical start/stop */\r\n  pLayerCfg->WindowY0 = Y0;\r\n  pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight;\r\n\r\n  /* Set LTDC parameters */\r\n  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);\r\n\r\n  /* Sets the Reload type */\r\n  hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Reconfigure the pixel format.\r\n  * @param  hltdc       pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                      the configuration information for the LTDC.\r\n  * @param  Pixelformat new pixel format value.\r\n  * @param  LayerIdx    LTDC Layer index.\r\n  *                      This parameter can be one of the following values:\r\n  *                      0 or 1.\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)\r\n{\r\n  LTDC_LayerCfgTypeDef *pLayerCfg;\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n  assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat));\r\n\r\n  /* Get layer configuration from handle structure */\r\n  pLayerCfg = &hltdc->LayerCfg[LayerIdx];  \r\n\r\n  /* Reconfigure the pixel format */\r\n  pLayerCfg->PixelFormat = Pixelformat;\r\n\r\n  /* Set LTDC parameters */\r\n  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);   \r\n\r\n  /* Sets the Reload type */\r\n  hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Reconfigure the layer alpha value.\r\n  * @param  hltdc    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  Alpha    new alpha value.\r\n  * @param  LayerIdx  LTDC Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0 or 1\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)\r\n{\r\n  LTDC_LayerCfgTypeDef *pLayerCfg;\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_ALPHA(Alpha));\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n\r\n  /* Get layer configuration from handle structure */\r\n  pLayerCfg = &hltdc->LayerCfg[LayerIdx];\r\n\r\n  /* Reconfigure the Alpha value */\r\n  pLayerCfg->Alpha = Alpha;\r\n\r\n  /* Set LTDC parameters */\r\n  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);\r\n\r\n  /* Sets the Reload type */\r\n  hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n/**\r\n  * @brief  Reconfigure the frame buffer Address.\r\n  * @param  hltdc    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  Address  new address value.\r\n  * @param  LayerIdx LTDC Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0 or 1.\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)\r\n{\r\n  LTDC_LayerCfgTypeDef *pLayerCfg;\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n\r\n  /* Get layer configuration from handle structure */\r\n  pLayerCfg = &hltdc->LayerCfg[LayerIdx];\r\n\r\n  /* Reconfigure the Address */\r\n  pLayerCfg->FBStartAdress = Address;\r\n\r\n  /* Set LTDC parameters */\r\n  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);\r\n\r\n  /* Sets the Reload type */\r\n  hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is\r\n  *         larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we \r\n  *         want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels \r\n  *         will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer().\r\n  *         Note : this function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch\r\n  *                configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).\r\n  * @param  hltdc             pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                            the configuration information for the LTDC.\r\n  * @param  LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'.\r\n  * @param  LayerIdx          LTDC layer index concerned by the modification of line pitch.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)\r\n{\r\n  uint32_t tmp = 0;\r\n  uint32_t pitchUpdate = 0;\r\n  uint32_t pixelFormat = 0;\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n  \r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n  \r\n  /* get LayerIdx used pixel format */\r\n  pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat;\r\n  \r\n  if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)\r\n  {\r\n    tmp = 4;\r\n  }\r\n  else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888)\r\n  {\r\n    tmp = 3;\r\n  }\r\n  else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \\\r\n          (pixelFormat == LTDC_PIXEL_FORMAT_RGB565)   || \\\r\n          (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \\\r\n         (pixelFormat == LTDC_PIXEL_FORMAT_AL88))\r\n  {\r\n    tmp = 2;\r\n  }\r\n  else\r\n  {\r\n    tmp = 1;\r\n  }\r\n  \r\n  pitchUpdate = ((LinePitchInPixels * tmp) << 16);\r\n  \r\n  /* Clear previously set standard pitch */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP;\r\n  \r\n  /* Sets the Reload type as immediate update of LTDC pitch configured above */\r\n  LTDC->SRCR |= LTDC_SRCR_IMR;\r\n  \r\n  /* Set new line pitch value */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate;\r\n  \r\n  /* Sets the Reload type as immediate update of LTDC pitch configured above */\r\n  LTDC->SRCR |= LTDC_SRCR_IMR;\r\n  \r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Define the position of the line interrupt.\r\n  * @param  hltdc             pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                            the configuration information for the LTDC.\r\n  * @param  Line   Line Interrupt Position.\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LIPOS(Line));\r\n\r\n  /* Enable the Line interrupt */\r\n  __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_LI);\r\n\r\n  /* Sets the Line Interrupt position */\r\n  LTDC->LIPCR = (uint32_t)Line;\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  LTDC configuration reload.\r\n  * @param  hltdc            pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                           the configuration information for the LTDC.\r\n  * @param  ReloadType       This parameter can be one of the following values :\r\n  *                           LTDC_RELOAD_IMMEDIATE : Immediate Reload\r\n  *                           LTDC_RELOAD_VERTICAL_BLANKING  : Reload in the next Vertical Blanking\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef  HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType)\r\n{\r\n  assert_param(IS_LTDC_RELAOD(ReloadType));\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;  \r\n  \r\n  /* Enable the Reload interrupt */  \r\n  __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_RR);\r\n       \r\n  /* Apply Reload type */\r\n  hltdc->Instance->SRCR = ReloadType;        \r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Configure the LTDC Layer according to the specified without reloading\r\n  *         parameters in the LTDC_InitTypeDef and create the associated handle.\r\n  *         Variant of the function HAL_LTDC_ConfigLayer without immediate reload\r\n  * @param  hltdc     pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                    the configuration information for the LTDC.\r\n  * @param  pLayerCfg pointer to a LTDC_LayerCfgTypeDef structure that contains\r\n  *                    the configuration information for the Layer.\r\n  * @param  LayerIdx  LTDC Layer index.\r\n  *                    This parameter can be one of the following values:\r\n  *                    0 or 1\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)\r\n{   \r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n  \r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n  assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat));\r\n  assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1));\r\n  assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));\r\n  assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));\r\n  assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));\r\n  assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));\r\n  assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));\r\n  assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0));\r\n  assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));\r\n  assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));\r\n\r\n  /* Copy new layer configuration into handle structure */\r\n  hltdc->LayerCfg[LayerIdx] = *pLayerCfg;  \r\n\r\n  /* Configure the LTDC Layer */  \r\n  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);\r\n\r\n  /* Do not Sets the Reload  */\r\n\r\n  /* Initialize the LTDC state*/\r\n  hltdc->State  = HAL_LTDC_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Set the LTDC window size without reloading.\r\n  *         Variant of the function HAL_LTDC_SetWindowSize without immediate reload\r\n  * @param  hltdc    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  XSize    LTDC Pixel per line\r\n  * @param  YSize    LTDC Line number\r\n  * @param  LayerIdx  LTDC Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0 or 1\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) \r\n{\r\n  LTDC_LayerCfgTypeDef *pLayerCfg;\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY; \r\n\r\n  /* Get layer configuration from handle structure */\r\n  pLayerCfg = &hltdc->LayerCfg[LayerIdx];\r\n\r\n  /* Check the parameters (Layers parameters)*/\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n  assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));\r\n  assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));\r\n  assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));\r\n  assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));\r\n  assert_param(IS_LTDC_CFBLL(XSize));\r\n  assert_param(IS_LTDC_CFBLNBR(YSize));\r\n\r\n  /* update horizontal start/stop */\r\n  pLayerCfg->WindowX0 = 0;\r\n  pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0;\r\n\r\n  /* update vertical start/stop */  \r\n  pLayerCfg->WindowY0 = 0;\r\n  pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0;\r\n\r\n  /* Reconfigures the color frame buffer pitch in byte */\r\n  pLayerCfg->ImageWidth = XSize;\r\n\r\n  /* Reconfigures the frame buffer line number */\r\n  pLayerCfg->ImageHeight = YSize;\r\n\r\n  /* Set LTDC parameters */\r\n  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);\r\n\r\n  /* Do not Sets the Reload  */\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Set the LTDC window position without reloading.\r\n  *         Variant of the function HAL_LTDC_SetWindowPosition without immediate reload\r\n  * @param  hltdc    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  X0       LTDC window X offset\r\n  * @param  Y0       LTDC window Y offset\r\n  * @param  LayerIdx  LTDC Layer index.\r\n  *                         This parameter can be one of the following values:\r\n  *                         0 or 1\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)\r\n{\r\n  LTDC_LayerCfgTypeDef *pLayerCfg;\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Get layer configuration from handle structure */\r\n  pLayerCfg = &hltdc->LayerCfg[LayerIdx];\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n  assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));\r\n  assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));\r\n  assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));\r\n  assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));\r\n\r\n  /* update horizontal start/stop */\r\n  pLayerCfg->WindowX0 = X0;\r\n  pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth;\r\n\r\n  /* update vertical start/stop */\r\n  pLayerCfg->WindowY0 = Y0;\r\n  pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight;\r\n\r\n  /* Set LTDC parameters */\r\n  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);\r\n\r\n  /* Do not Sets the Reload  */\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Reconfigure the pixel format without reloading.\r\n  *         Variant of the function HAL_LTDC_SetPixelFormat without immediate reload\r\n  * @param  hltdc       pointer to a LTDC_HandleTypeDfef structure that contains\r\n  *                      the configuration information for the LTDC.\r\n  * @param  Pixelformat new pixel format value.\r\n  * @param  LayerIdx    LTDC Layer index.\r\n  *                      This parameter can be one of the following values:\r\n  *                      0 or 1.\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)\r\n{\r\n  LTDC_LayerCfgTypeDef *pLayerCfg;\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n  assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat));\r\n\r\n  /* Get layer configuration from handle structure */\r\n  pLayerCfg = &hltdc->LayerCfg[LayerIdx];  \r\n\r\n  /* Reconfigure the pixel format */\r\n  pLayerCfg->PixelFormat = Pixelformat;\r\n\r\n  /* Set LTDC parameters */\r\n  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);   \r\n\r\n  /* Do not Sets the Reload  */\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Reconfigure the layer alpha value without reloading.\r\n  *         Variant of the function HAL_LTDC_SetAlpha without immediate reload\r\n  * @param  hltdc    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  Alpha    new alpha value.\r\n  * @param  LayerIdx  LTDC Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0 or 1\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)\r\n{\r\n  LTDC_LayerCfgTypeDef *pLayerCfg;\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_ALPHA(Alpha));\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n\r\n  /* Get layer configuration from handle structure */\r\n  pLayerCfg = &hltdc->LayerCfg[LayerIdx];\r\n\r\n  /* Reconfigure the Alpha value */\r\n  pLayerCfg->Alpha = Alpha;\r\n\r\n  /* Set LTDC parameters */\r\n  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);\r\n\r\n  /* Do not Sets the Reload  */\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Reconfigure the frame buffer Address without reloading.\r\n  *         Variant of the function HAL_LTDC_SetAddress without immediate reload   \r\n  * @param  hltdc    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  Address  new address value.\r\n  * @param  LayerIdx LTDC Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0 or 1.\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)\r\n{\r\n  LTDC_LayerCfgTypeDef *pLayerCfg;\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n\r\n  /* Get layer configuration from handle structure */\r\n  pLayerCfg = &hltdc->LayerCfg[LayerIdx];\r\n\r\n  /* Reconfigure the Address */\r\n  pLayerCfg->FBStartAdress = Address;\r\n\r\n  /* Set LTDC parameters */\r\n  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);\r\n\r\n  /* Do not Sets the Reload  */\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is\r\n  *         larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we \r\n  *         want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels \r\n  *         will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer().\r\n  *         Note : this function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch\r\n  *                configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).\r\n  *         Variant of the function HAL_LTDC_SetPitch without immediate reload    \r\n  * @param  hltdc             pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                            the configuration information for the LTDC.\r\n  * @param  LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'.\r\n  * @param  LayerIdx          LTDC layer index concerned by the modification of line pitch.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)\r\n{\r\n  uint32_t tmp = 0;\r\n  uint32_t pitchUpdate = 0;\r\n  uint32_t pixelFormat = 0;\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n  \r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n  \r\n  /* get LayerIdx used pixel format */\r\n  pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat;\r\n  \r\n  if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)\r\n  {\r\n    tmp = 4;\r\n  }\r\n  else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888)\r\n  {\r\n    tmp = 3;\r\n  }\r\n  else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \\\r\n          (pixelFormat == LTDC_PIXEL_FORMAT_RGB565)   || \\\r\n          (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \\\r\n         (pixelFormat == LTDC_PIXEL_FORMAT_AL88))\r\n  {\r\n    tmp = 2;\r\n  }\r\n  else\r\n  {\r\n    tmp = 1;\r\n  }\r\n  \r\n  pitchUpdate = ((LinePitchInPixels * tmp) << 16);\r\n  \r\n  /* Clear previously set standard pitch */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP;\r\n  \r\n  /* Set new line pitch value */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate;\r\n  \r\n  /* Do not Sets the Reload  */\r\n  \r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n\r\n/**\r\n  * @brief  Configure the color keying without reloading.\r\n  *         Variant of the function HAL_LTDC_ConfigColorKeying without immediate reload\r\n  * @param  hltdc    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  RGBValue the color key value\r\n  * @param  LayerIdx  LTDC Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0 or 1\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n\r\n  /* Configures the default color values */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CKCR &=  ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED);\r\n  LTDC_LAYER(hltdc, LayerIdx)->CKCR  = RGBValue;\r\n\r\n  /* Do not Sets the Reload  */\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Enable the color keying without reloading.\r\n  *         Variant of the function HAL_LTDC_EnableColorKeying without immediate reload\r\n  * @param  hltdc    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  LayerIdx  LTDC Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0 or 1\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)\r\n{  \r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n\r\n  /* Enable LTDC color keying by setting COLKEN bit */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN;\r\n\r\n  /* Do not Sets the Reload  */\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY; \r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Disable the color keying without reloading.\r\n  *         Variant of the function HAL_LTDC_DisableColorKeying without immediate reload\r\n  * @param  hltdc    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  LayerIdx  LTDC Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0 or 1\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n\r\n  /* Disable LTDC color keying by setting COLKEN bit */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN;\r\n\r\n  /* Do not Sets the Reload  */\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY; \r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Enable the color lookup table without reloading.\r\n  *         Variant of the function HAL_LTDC_EnableCLUT without immediate reload\r\n  * @param  hltdc    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  LayerIdx  LTDC Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0 or 1\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)\r\n{\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n\r\n  /* Disable LTDC color lookup table by setting CLUTEN bit */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN;\r\n\r\n  /* Do not Sets the Reload  */\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY; \r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Disable the color lookup table without reloading.\r\n  *         Variant of the function HAL_LTDC_DisableCLUT without immediate reload\r\n  * @param  hltdc    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  LayerIdx  LTDC Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0 or 1   \r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)\r\n{\r\n \r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n\r\n  /* Disable LTDC color lookup table by setting CLUTEN bit */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN;\r\n\r\n  /* Do not Sets the Reload  */\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY; \r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LTDC_Exported_Functions_Group4 Peripheral State and Errors functions\r\n *  @brief    Peripheral State and Errors functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                  ##### Peripheral State and Errors functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides functions allowing to\r\n      (+) Check the LTDC state.\r\n      (+) Get error code.  \r\n\r\n@endverbatim\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @brief  Return the LTDC state\r\n  * @param  hltdc pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                the configuration information for the LTDC.\r\n  * @retval HAL state\r\n  */\r\nHAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc)\r\n{\r\n  return hltdc->State;\r\n}\r\n\r\n/**\r\n* @brief  Return the LTDC error code\r\n* @param  hltdc  pointer to a LTDC_HandleTypeDef structure that contains\r\n  *               the configuration information for the LTDC.\r\n* @retval LTDC Error Code\r\n*/\r\nuint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc)\r\n{\r\n  return hltdc->ErrorCode;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @brief  Configures the LTDC peripheral \r\n  * @param  hltdc     Pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  pLayerCfg Pointer LTDC Layer Configuration structure\r\n  * @param  LayerIdx  LTDC Layer index.\r\n  *                    This parameter can be one of the following values: 0 or 1\r\n  * @retval None\r\n  */\r\nstatic void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)\r\n{\r\n  uint32_t tmp = 0;\r\n  uint32_t tmp1 = 0;\r\n  uint32_t tmp2 = 0;\r\n\r\n  /* Configures the horizontal start and stop position */\r\n  tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16)) << 16);\r\n  LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS);\r\n  LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16) + 1) | tmp);\r\n\r\n  /* Configures the vertical start and stop position */\r\n  tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16);\r\n  LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS);\r\n  LTDC_LAYER(hltdc, LayerIdx)->WVPCR  = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1) | tmp);  \r\n\r\n  /* Specifies the pixel format */\r\n  LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF);\r\n  LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat);\r\n\r\n  /* Configures the default color values */\r\n  tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8);\r\n  tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16);\r\n  tmp2 = (pLayerCfg->Alpha0 << 24);  \r\n  LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA);\r\n  LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2); \r\n\r\n  /* Specifies the constant alpha value */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA);\r\n  LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha);\r\n\r\n  /* Specifies the blending factors */\r\n  LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1);\r\n  LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2);\r\n\r\n  /* Configures the color frame buffer start address */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD);\r\n  LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress);\r\n\r\n  if(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)\r\n  {\r\n    tmp = 4;\r\n  }\r\n  else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888)\r\n  {\r\n    tmp = 3;\r\n  }\r\n  else if((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \\\r\n    (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565)   || \\\r\n      (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \\\r\n        (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88))\r\n  {\r\n    tmp = 2;\r\n  }\r\n  else\r\n  {\r\n    tmp = 1;\r\n  }\r\n\r\n  /* Configures the color frame buffer pitch in byte */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CFBLR  &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP);\r\n  LTDC_LAYER(hltdc, LayerIdx)->CFBLR  = (((pLayerCfg->ImageWidth * tmp) << 16) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp)  + 3));\r\n\r\n  /* Configures the frame buffer line number */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CFBLNR  &= ~(LTDC_LxCFBLNR_CFBLNBR);\r\n  LTDC_LAYER(hltdc, LayerIdx)->CFBLNR  = (pLayerCfg->ImageHeight);\r\n\r\n  /* Enable LTDC_Layer by setting LEN bit */  \r\n  LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_LTDC_MODULE_ENABLED */\r\n\r\n/**\r\n  * @}\r\n  */\r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_pcd.c\r\n  * @author  MCD Application Team\r\n  * @brief   PCD HAL module driver.\r\n  *          This file provides firmware functions to manage the following\r\n  *          functionalities of the USB Peripheral Controller:\r\n  *           + Initialization and de-initialization functions\r\n  *           + IO operation functions\r\n  *           + Peripheral Control functions\r\n  *           + Peripheral State functions\r\n  *\r\n  @verbatim\r\n  ==============================================================================\r\n                    ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]\r\n      The PCD HAL driver can be used as follows:\r\n\r\n     (#) Declare a PCD_HandleTypeDef handle structure, for example:\r\n         PCD_HandleTypeDef  hpcd;\r\n\r\n     (#) Fill parameters of Init structure in HCD handle\r\n\r\n     (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)\r\n\r\n     (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:\r\n         (##) Enable the PCD/USB Low Level interface clock using\r\n              (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();\r\n              (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)\r\n\r\n         (##) Initialize the related GPIO clocks\r\n         (##) Configure PCD pin-out\r\n         (##) Configure PCD NVIC interrupt\r\n\r\n     (#)Associate the Upper USB device stack to the HAL PCD Driver:\r\n         (##) hpcd.pData = pdev;\r\n\r\n     (#)Enable PCD transmission and reception:\r\n         (##) HAL_PCD_Start();\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup PCD\r\n  * @brief PCD HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_PCD_MODULE_ENABLED\r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\r\n/**\r\n  * USB_OTG_CORE VERSION ID\r\n  */\r\n#define USB_OTG_CORE_ID_300A          0x4F54300AU\r\n#define USB_OTG_CORE_ID_310A          0x4F54310AU\r\n#define USB_OTG_CORE_ID_320A          0x4F54320AU\r\n#endif /* USB_OTG_FS || USB_OTG_HS */\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup PCD_Private_Macros PCD Private Macros\r\n  * @{\r\n  */\r\n#define PCD_MIN(a, b)  (((a) < (b)) ? (a) : (b))\r\n#define PCD_MAX(a, b)  (((a) > (b)) ? (a) : (b))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions prototypes ----------------------------------------------*/\r\n/** @defgroup PCD_Private_Functions PCD Private Functions\r\n  * @{\r\n  */\r\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\r\nstatic HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);\r\n#endif /* USB_OTG_FS || USB_OTG_HS */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup PCD_Exported_Functions PCD Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions\r\n *  @brief    Initialization and Configuration functions\r\n *\r\n@verbatim\r\n ===============================================================================\r\n            ##### Initialization and de-initialization functions #####\r\n ===============================================================================\r\n    [..]  This section provides functions allowing to:\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the PCD according to the specified\r\n  *         parameters in the PCD_InitTypeDef and initialize the associated handle.\r\n  * @param  hpcd PCD handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)\r\n{\r\n  uint8_t i;\r\n\r\n  /* Check the PCD handle allocation */\r\n  if(hpcd == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));\r\n\r\n  if(hpcd->State == HAL_PCD_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    hpcd->Lock = HAL_UNLOCKED;\r\n\r\n    /* Init the low level hardware : GPIO, CLOCK, NVIC... */\r\n    HAL_PCD_MspInit(hpcd);\r\n  }\r\n\r\n  hpcd->State = HAL_PCD_STATE_BUSY;\r\n\r\n  /* Disable the Interrupts */\r\n  __HAL_PCD_DISABLE(hpcd);\r\n\r\n  /*Init the Core (common init.) */\r\n  (void)USB_CoreInit(hpcd->Instance, hpcd->Init);\r\n\r\n  /* Force Device Mode*/\r\n  (void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE);\r\n\r\n  /* Init endpoints structures */\r\n  for (i = 0U; i < 15U; i++)\r\n  {\r\n    /* Init ep structure */\r\n    hpcd->IN_ep[i].is_in = 1U;\r\n    hpcd->IN_ep[i].num = i;\r\n    hpcd->IN_ep[i].tx_fifo_num = i;\r\n    /* Control until ep is activated */\r\n    hpcd->IN_ep[i].type = EP_TYPE_CTRL;\r\n    hpcd->IN_ep[i].maxpacket = 0U;\r\n    hpcd->IN_ep[i].xfer_buff = 0U;\r\n    hpcd->IN_ep[i].xfer_len = 0U;\r\n  }\r\n\r\n  for (i = 0U; i < 15U; i++)\r\n  {\r\n    hpcd->OUT_ep[i].is_in = 0U;\r\n    hpcd->OUT_ep[i].num = i;\r\n    /* Control until ep is activated */\r\n    hpcd->OUT_ep[i].type = EP_TYPE_CTRL;\r\n    hpcd->OUT_ep[i].maxpacket = 0U;\r\n    hpcd->OUT_ep[i].xfer_buff = 0U;\r\n    hpcd->OUT_ep[i].xfer_len = 0U;\r\n  }\r\n\r\n  /* Init Device */\r\n  (void)USB_DevInit(hpcd->Instance, hpcd->Init);\r\n\r\n  hpcd->USB_Address = 0U;\r\n  hpcd->State = HAL_PCD_STATE_READY;\r\n\r\n  /* Activate LPM */\r\n  if (hpcd->Init.lpm_enable == 1U)\r\n  {\r\n    (void)HAL_PCDEx_ActivateLPM(hpcd);\r\n  }\r\n\r\n  (void)USB_DevDisconnect (hpcd->Instance);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the PCD peripheral.\r\n  * @param  hpcd PCD handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)\r\n{\r\n  /* Check the PCD handle allocation */\r\n  if(hpcd == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  hpcd->State = HAL_PCD_STATE_BUSY;\r\n\r\n  /* Stop Device */\r\n  (void)HAL_PCD_Stop(hpcd);\r\n\r\n  /* DeInit the low level hardware */\r\n  HAL_PCD_MspDeInit(hpcd);\r\n\r\n  hpcd->State = HAL_PCD_STATE_RESET;\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the PCD MSP.\r\n  * @param  hpcd PCD handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hpcd);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_PCD_MspInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes PCD MSP.\r\n  * @param  hpcd PCD handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hpcd);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_PCD_MspDeInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup PCD_Exported_Functions_Group2 IO operation functions\r\n *  @brief   Data transfers functions\r\n *\r\n@verbatim\r\n ===============================================================================\r\n                      ##### IO operation functions #####\r\n ===============================================================================\r\n    [..]\r\n    This subsection provides a set of functions allowing to manage the PCD data\r\n    transfers.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Start the USB device\r\n  * @param  hpcd PCD handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)\r\n{\r\n  __HAL_LOCK(hpcd);\r\n  (void)USB_DevConnect (hpcd->Instance);\r\n  __HAL_PCD_ENABLE(hpcd);\r\n  __HAL_UNLOCK(hpcd);\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stop the USB device.\r\n  * @param  hpcd PCD handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)\r\n{\r\n  __HAL_LOCK(hpcd);\r\n  __HAL_PCD_DISABLE(hpcd);\r\n  (void)USB_StopDevice(hpcd->Instance);\r\n  (void)USB_DevDisconnect(hpcd->Instance);\r\n  __HAL_UNLOCK(hpcd);\r\n  return HAL_OK;\r\n}\r\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\r\n/**\r\n  * @brief  Handles PCD interrupt request.\r\n  * @param  hpcd PCD handle\r\n  * @retval HAL status\r\n  */\r\nvoid HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)\r\n{\r\n  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n  uint32_t TempReg = USBx_BASE + 0x40U;\r\n  uint32_t gSNPSiD = *(uint32_t *) TempReg;\r\n  uint32_t i, ep_intr, epint, epnum = 0U;\r\n  uint32_t fifoemptymsk, temp;\r\n  USB_OTG_EPTypeDef *ep;\r\n  uint32_t hclk;\r\n\r\n  /* ensure that we are in device mode */\r\n  if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)\r\n  {\r\n    /* avoid spurious interrupt */\r\n    if(__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))\r\n    {\r\n      return;\r\n    }\r\n\r\n    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))\r\n    {\r\n      /* incorrect mode, acknowledge the interrupt */\r\n      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);\r\n    }\r\n\r\n    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))\r\n    {\r\n      epnum = 0U;\r\n\r\n      /* Read in the device interrupt bits */\r\n      ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);\r\n\r\n      while (ep_intr != 0U)\r\n      {\r\n        if ((ep_intr & 0x1U) != 0U)\r\n        {\r\n          epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum);\r\n\r\n          if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)\r\n          {\r\n            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);\r\n\r\n            if (gSNPSiD > USB_OTG_CORE_ID_300A)\r\n            {\r\n              /* setup/out transaction management for Core ID >= 310A */\r\n              if (hpcd->Init.dma_enable == 1U)\r\n              {\r\n                if ((USBx_OUTEP(0U)->DOEPINT & (1U << 15)) != 0U)\r\n                {\r\n                  CLEAR_OUT_EP_INTR(epnum, (1U << 15));\r\n                }\r\n              }\r\n            }\r\n\r\n            if(hpcd->Init.dma_enable == 1U)\r\n            {\r\n              hpcd->OUT_ep[epnum].xfer_count = hpcd->OUT_ep[epnum].maxpacket- (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);\r\n              hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;\r\n            }\r\n\r\n            if (gSNPSiD == USB_OTG_CORE_ID_310A)\r\n            {\r\n              if ((USBx_OUTEP(0U)->DOEPINT & (1U << 15)) != 0U)\r\n              {\r\n                CLEAR_OUT_EP_INTR(epnum, (1U << 15));\r\n              }\r\n              else\r\n              {\r\n                HAL_PCD_DataOutStageCallback(hpcd, epnum);\r\n              }\r\n            }\r\n            else\r\n            {\r\n              HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);\r\n            }\r\n\r\n            if(hpcd->Init.dma_enable == 1U)\r\n            {\r\n              if((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))\r\n              {\r\n                 /* this is ZLP, so prepare EP0 for next setup */\r\n                (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);\r\n              }\r\n            }\r\n          }\r\n\r\n          if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)\r\n          {\r\n            if (gSNPSiD == USB_OTG_CORE_ID_310A)\r\n            {\r\n              if ((USBx_OUTEP(0U)->DOEPINT & (1U << 15)) != 0U)\r\n              {\r\n                CLEAR_OUT_EP_INTR(epnum, (1U << 15));\r\n              }\r\n            }\r\n\r\n            if (gSNPSiD > USB_OTG_CORE_ID_300A)\r\n            {\r\n              /* setup/out transaction management for Core ID >= 310A */\r\n              if (hpcd->Init.dma_enable == 1U)\r\n              {\r\n                if ((USBx_OUTEP(0U)->DOEPINT & (1U << 15)) != 0U)\r\n                {\r\n                  CLEAR_OUT_EP_INTR(epnum, (1U << 15));\r\n                }\r\n              }\r\n            }\r\n\r\n            /* Inform the upper layer that a setup packet is available */\r\n            HAL_PCD_SetupStageCallback(hpcd);\r\n            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);\r\n          }\r\n\r\n          if(( epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)\r\n          {\r\n            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);\r\n          }\r\n\r\n#ifdef USB_OTG_DOEPINT_OTEPSPR\r\n          /* Clear Status Phase Received interrupt */\r\n          if(( epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)\r\n          {\r\n            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);\r\n          }\r\n#endif /* USB_OTG_DOEPINT_OTEPSPR */\r\n        }\r\n        epnum++;\r\n        ep_intr >>= 1U;\r\n      }\r\n    }\r\n\r\n    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))\r\n    {\r\n      /* Read in the device interrupt bits */\r\n      ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);\r\n\r\n      epnum = 0U;\r\n\r\n      while (ep_intr != 0U)\r\n      {\r\n        if ((ep_intr & 0x1U) != 0U) /* In ITR */\r\n        {\r\n          epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum);\r\n\r\n          if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)\r\n          {\r\n            fifoemptymsk = (uint32_t)(0x1UL << (epnum & 0xFU));\r\n            USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;\r\n\r\n            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);\r\n\r\n            if (hpcd->Init.dma_enable == 1U)\r\n            {\r\n              hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket;\r\n            }\r\n\r\n            HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum);\r\n\r\n            if (hpcd->Init.dma_enable == 1U)\r\n            {\r\n              /* this is ZLP, so prepare EP0 for next setup */\r\n              if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U))\r\n              {\r\n                /* prepare to rx more setup packets */\r\n                (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);\r\n              }\r\n            }\r\n          }\r\n          if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)\r\n          {\r\n            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);\r\n          }\r\n          if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)\r\n          {\r\n            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);\r\n          }\r\n          if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)\r\n          {\r\n            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);\r\n          }\r\n          if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)\r\n          {\r\n            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);\r\n          }\r\n          if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)\r\n          {\r\n            (void)PCD_WriteEmptyTxFifo(hpcd, epnum);\r\n          }\r\n        }\r\n        epnum++;\r\n        ep_intr >>= 1U;\r\n      }\r\n    }\r\n\r\n    /* Handle Resume Interrupt */\r\n    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))\r\n    {\r\n      /* Clear the Remote Wake-up Signaling */\r\n      USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;\r\n\r\n      if(hpcd->LPM_State == LPM_L1)\r\n      {\r\n        hpcd->LPM_State = LPM_L0;\r\n        HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);\r\n      }\r\n      else\r\n      {\r\n        HAL_PCD_ResumeCallback(hpcd);\r\n      }\r\n\r\n      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);\r\n    }\r\n\r\n    /* Handle Suspend Interrupt */\r\n    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))\r\n    {\r\n      if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)\r\n      {\r\n\r\n        HAL_PCD_SuspendCallback(hpcd);\r\n      }\r\n      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);\r\n    }\r\n\r\n    /* Handle LPM Interrupt */\r\n    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))\r\n    {\r\n      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);\r\n      if( hpcd->LPM_State == LPM_L0)\r\n      {\r\n        hpcd->LPM_State = LPM_L1;\r\n        hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U;\r\n        HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);\r\n      }\r\n      else\r\n      {\r\n        HAL_PCD_SuspendCallback(hpcd);\r\n      }\r\n    }\r\n\r\n    /* Handle Reset Interrupt */\r\n    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))\r\n    {\r\n      USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;\r\n      (void)USB_FlushTxFifo(hpcd->Instance, 0x10U);\r\n\r\n      for (i = 0U; i < hpcd->Init.dev_endpoints; i++)\r\n      {\r\n        USBx_INEP(i)->DIEPINT = 0xFB7FU;\r\n        USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;\r\n        USBx_OUTEP(i)->DOEPINT = 0xFB7FU;\r\n        USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;\r\n      }\r\n      USBx_DEVICE->DAINTMSK |= 0x10001U;\r\n\r\n      if (hpcd->Init.use_dedicated_ep1 != 0U)\r\n      {\r\n        USBx_DEVICE->DOUTEP1MSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);\r\n        USBx_DEVICE->DINEP1MSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);\r\n      }\r\n      else\r\n      {\r\n#ifdef USB_OTG_DOEPINT_OTEPSPR\r\n        USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM);\r\n#else\r\n        USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);\r\n#endif /* USB_OTG_DOEPINT_OTEPSPR */\r\n        USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);\r\n      }\r\n\r\n      /* Set Default Address to 0 */\r\n      USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;\r\n\r\n      /* setup EP0 to receive SETUP packets */\r\n      (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);\r\n\r\n      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);\r\n    }\r\n\r\n    /* Handle Enumeration done Interrupt */\r\n    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))\r\n    {\r\n      (void)USB_ActivateSetup(hpcd->Instance);\r\n      hpcd->Instance->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;\r\n\r\n      if ( USB_GetDevSpeed(hpcd->Instance) == USB_OTG_SPEED_HIGH)\r\n      {\r\n        hpcd->Init.speed            = USB_OTG_SPEED_HIGH;\r\n        hpcd->Init.ep0_mps          = USB_OTG_HS_MAX_PACKET_SIZE;\r\n        hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_HS_TRDT_VALUE << 10U) & USB_OTG_GUSBCFG_TRDT);\r\n      }\r\n      else\r\n      {\r\n        hpcd->Init.speed            = USB_OTG_SPEED_FULL;\r\n        hpcd->Init.ep0_mps          = USB_OTG_FS_MAX_PACKET_SIZE;\r\n\r\n        /* The USBTRD is configured according to the tables below, depending on AHB frequency\r\n        used by application. In the low AHB frequency range it is used to stretch enough the USB response\r\n        time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access\r\n        latency to the Data FIFO */\r\n\r\n        /* Get hclk frequency value */\r\n        hclk = HAL_RCC_GetHCLKFreq();\r\n\r\n        if((hclk >= 14200000U) && (hclk < 15000000U))\r\n        {\r\n          /* hclk Clock Range between 14.2-15 MHz */\r\n          hpcd->Instance->GUSBCFG |= (uint32_t)((0xFU << 10) & USB_OTG_GUSBCFG_TRDT);\r\n        }\r\n\r\n        else if((hclk >= 15000000U) && (hclk < 16000000U))\r\n        {\r\n          /* hclk Clock Range between 15-16 MHz */\r\n          hpcd->Instance->GUSBCFG |= (uint32_t)((0xEU << 10) & USB_OTG_GUSBCFG_TRDT);\r\n        }\r\n\r\n        else if((hclk >= 16000000U) && (hclk < 17200000U))\r\n        {\r\n          /* hclk Clock Range between 16-17.2 MHz */\r\n          hpcd->Instance->GUSBCFG |= (uint32_t)((0xDU << 10) & USB_OTG_GUSBCFG_TRDT);\r\n        }\r\n\r\n        else if((hclk >= 17200000U) && (hclk < 18500000U))\r\n        {\r\n          /* hclk Clock Range between 17.2-18.5 MHz */\r\n          hpcd->Instance->GUSBCFG |= (uint32_t)((0xCU << 10) & USB_OTG_GUSBCFG_TRDT);\r\n        }\r\n\r\n        else if((hclk >= 18500000U) && (hclk < 20000000U))\r\n        {\r\n          /* hclk Clock Range between 18.5-20 MHz */\r\n          hpcd->Instance->GUSBCFG |= (uint32_t)((0xBU << 10) & USB_OTG_GUSBCFG_TRDT);\r\n        }\r\n\r\n        else if((hclk >= 20000000U) && (hclk < 21800000U))\r\n        {\r\n          /* hclk Clock Range between 20-21.8 MHz */\r\n          hpcd->Instance->GUSBCFG |= (uint32_t)((0xAU << 10) & USB_OTG_GUSBCFG_TRDT);\r\n        }\r\n\r\n        else if((hclk >= 21800000U) && (hclk < 24000000U))\r\n        {\r\n          /* hclk Clock Range between 21.8-24 MHz */\r\n          hpcd->Instance->GUSBCFG |= (uint32_t)((0x9U << 10) & USB_OTG_GUSBCFG_TRDT);\r\n        }\r\n\r\n        else if((hclk >= 24000000U) && (hclk < 27700000U))\r\n        {\r\n          /* hclk Clock Range between 24-27.7 MHz */\r\n          hpcd->Instance->GUSBCFG |= (uint32_t)((0x8U << 10) & USB_OTG_GUSBCFG_TRDT);\r\n        }\r\n\r\n        else if((hclk >= 27700000U) && (hclk < 32000000U))\r\n        {\r\n          /* hclk Clock Range between 27.7-32 MHz */\r\n          hpcd->Instance->GUSBCFG |= (uint32_t)((0x7U << 10) & USB_OTG_GUSBCFG_TRDT);\r\n        }\r\n\r\n        else /* if(hclk >= 32000000) */\r\n        {\r\n          /* hclk Clock Range between 32-200 MHz */\r\n          hpcd->Instance->GUSBCFG |= (uint32_t)((0x6U << 10) & USB_OTG_GUSBCFG_TRDT);\r\n        }\r\n      }\r\n\r\n      HAL_PCD_ResetCallback(hpcd);\r\n\r\n      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);\r\n    }\r\n\r\n    /* Handle RxQLevel Interrupt */\r\n    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))\r\n    {\r\n      USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);\r\n\r\n      temp = USBx->GRXSTSP;\r\n\r\n      ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];\r\n\r\n      if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_DATA_UPDT)\r\n      {\r\n        if((temp & USB_OTG_GRXSTSP_BCNT) != 0U)\r\n        {\r\n          (void)USB_ReadPacket(USBx, ep->xfer_buff, (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4));\r\n          ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;\r\n          ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;\r\n        }\r\n      }\r\n      else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_SETUP_UPDT)\r\n      {\r\n        (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);\r\n        ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;\r\n      }\r\n      else\r\n      {\r\n         /* ... */\r\n      }\r\n      USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);\r\n    }\r\n\r\n    /* Handle SOF Interrupt */\r\n    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))\r\n    {\r\n      HAL_PCD_SOFCallback(hpcd);\r\n      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);\r\n    }\r\n\r\n    /* Handle Incomplete ISO IN Interrupt */\r\n    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))\r\n    {\r\n      HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum);\r\n      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);\r\n    }\r\n\r\n    /* Handle Incomplete ISO OUT Interrupt */\r\n    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))\r\n    {\r\n      HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);\r\n      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);\r\n    }\r\n\r\n    /* Handle Connection event Interrupt */\r\n    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))\r\n    {\r\n      HAL_PCD_ConnectCallback(hpcd);\r\n      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);\r\n    }\r\n\r\n    /* Handle Disconnection event Interrupt */\r\n    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))\r\n    {\r\n      temp = hpcd->Instance->GOTGINT;\r\n\r\n      if((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)\r\n      {\r\n        HAL_PCD_DisconnectCallback(hpcd);\r\n      }\r\n      hpcd->Instance->GOTGINT |= temp;\r\n    }\r\n  }\r\n}\r\n#endif /* USB_OTG_FS || USB_OTG_HS */\r\n\r\n\r\n/**\r\n  * @brief  Data OUT stage callback.\r\n  * @param  hpcd PCD handle\r\n  * @param  epnum endpoint number\r\n  * @retval None\r\n  */\r\n__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hpcd);\r\n  UNUSED(epnum);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_PCD_DataOutStageCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Data IN stage callback\r\n  * @param  hpcd PCD handle\r\n  * @param  epnum endpoint number\r\n  * @retval None\r\n  */\r\n__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hpcd);\r\n  UNUSED(epnum);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_PCD_DataInStageCallback could be implemented in the user file\r\n   */\r\n}\r\n/**\r\n  * @brief  Setup stage callback\r\n  * @param  hpcd PCD handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hpcd);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_PCD_SetupStageCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  USB Start Of Frame callback.\r\n  * @param  hpcd PCD handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hpcd);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_PCD_SOFCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  USB Reset callback.\r\n  * @param  hpcd PCD handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hpcd);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_PCD_ResetCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Suspend event callback.\r\n  * @param  hpcd PCD handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hpcd);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_PCD_SuspendCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Resume event callback.\r\n  * @param  hpcd PCD handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hpcd);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_PCD_ResumeCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Incomplete ISO OUT callback.\r\n  * @param  hpcd PCD handle\r\n  * @param  epnum endpoint number\r\n  * @retval None\r\n  */\r\n__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hpcd);\r\n  UNUSED(epnum);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Incomplete ISO IN callback.\r\n  * @param  hpcd PCD handle\r\n  * @param  epnum endpoint number\r\n  * @retval None\r\n  */\r\n__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hpcd);\r\n  UNUSED(epnum);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Connection event callback.\r\n  * @param  hpcd PCD handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hpcd);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_PCD_ConnectCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Disconnection event callback.\r\n  * @param  hpcd PCD handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hpcd);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_PCD_DisconnectCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions\r\n *  @brief   management functions\r\n *\r\n@verbatim\r\n ===============================================================================\r\n                      ##### Peripheral Control functions #####\r\n ===============================================================================\r\n    [..]\r\n    This subsection provides a set of functions allowing to control the PCD data\r\n    transfers.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Connect the USB device\r\n  * @param  hpcd PCD handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)\r\n{\r\n  __HAL_LOCK(hpcd);\r\n  (void)USB_DevConnect(hpcd->Instance);\r\n  __HAL_UNLOCK(hpcd);\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Disconnect the USB device.\r\n  * @param  hpcd PCD handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)\r\n{\r\n  __HAL_LOCK(hpcd);\r\n  (void)USB_DevDisconnect(hpcd->Instance);\r\n  __HAL_UNLOCK(hpcd);\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Set the USB Device address.\r\n  * @param  hpcd PCD handle\r\n  * @param  address new device address\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)\r\n{\r\n  __HAL_LOCK(hpcd);\r\n  hpcd->USB_Address = address;\r\n  (void)USB_SetDevAddress(hpcd->Instance, address);\r\n  __HAL_UNLOCK(hpcd);\r\n  return HAL_OK;\r\n}\r\n/**\r\n  * @brief  Open and configure an endpoint.\r\n  * @param  hpcd PCD handle\r\n  * @param  ep_addr endpoint address\r\n  * @param  ep_mps endpoint max packet size\r\n  * @param  ep_type endpoint type\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)\r\n{\r\n  HAL_StatusTypeDef  ret = HAL_OK;\r\n  PCD_EPTypeDef *ep;\r\n\r\n  if ((ep_addr & 0x80U) == 0x80U)\r\n  {\r\n    ep = &hpcd->IN_ep[ep_addr & 0xFU];\r\n    ep->is_in = 1U;\r\n  }\r\n  else\r\n  {\r\n    ep = &hpcd->OUT_ep[ep_addr & 0xFU];\r\n    ep->is_in = 0U;\r\n  }\r\n\r\n  ep->num = ep_addr & 0xFU;\r\n  ep->maxpacket = ep_mps;\r\n  ep->type = ep_type;\r\n\r\n  if (ep->is_in != 0U)\r\n  {\r\n    /* Assign a Tx FIFO */\r\n    ep->tx_fifo_num = ep->num;\r\n  }\r\n  /* Set initial data PID. */\r\n  if (ep_type == EP_TYPE_BULK)\r\n  {\r\n    ep->data_pid_start = 0U;\r\n  }\r\n\r\n  __HAL_LOCK(hpcd);\r\n  (void)USB_ActivateEndpoint(hpcd->Instance, ep);\r\n  __HAL_UNLOCK(hpcd);\r\n\r\n  return ret;\r\n}\r\n\r\n/**\r\n  * @brief  Deactivate an endpoint.\r\n  * @param  hpcd PCD handle\r\n  * @param  ep_addr endpoint address\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)\r\n{\r\n  PCD_EPTypeDef *ep;\r\n\r\n  if ((ep_addr & 0x80U) == 0x80U)\r\n  {\r\n    ep = &hpcd->IN_ep[ep_addr & 0xFU];\r\n    ep->is_in = 1U;\r\n  }\r\n  else\r\n  {\r\n    ep = &hpcd->OUT_ep[ep_addr & 0xFU];\r\n    ep->is_in = 0U;\r\n  }\r\n  ep->num   = ep_addr & 0xFU;\r\n\r\n  __HAL_LOCK(hpcd);\r\n  (void)USB_DeactivateEndpoint(hpcd->Instance , ep);\r\n  __HAL_UNLOCK(hpcd);\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Receive an amount of data.\r\n  * @param  hpcd PCD handle\r\n  * @param  ep_addr endpoint address\r\n  * @param  pBuf pointer to the reception buffer\r\n  * @param  len amount of data to be received\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)\r\n{\r\n  PCD_EPTypeDef *ep;\r\n\r\n  ep = &hpcd->OUT_ep[ep_addr & 0xFU];\r\n\r\n  /*setup and start the Xfer */\r\n  ep->xfer_buff = pBuf;\r\n  ep->xfer_len = len;\r\n  ep->xfer_count = 0U;\r\n  ep->is_in = 0U;\r\n  ep->num = ep_addr & 0xFU;\r\n\r\n  if (hpcd->Init.dma_enable == 1U)\r\n  {\r\n    ep->dma_addr = (uint32_t)pBuf;\r\n  }\r\n\r\n  if ((ep_addr & 0xFU) == 0U)\r\n  {\r\n    (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);\r\n  }\r\n  else\r\n  {\r\n    (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Get Received Data Size\r\n  * @param  hpcd PCD handle\r\n  * @param  ep_addr endpoint address\r\n  * @retval Data Size\r\n  */\r\nuint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)\r\n{\r\n  return (uint16_t)hpcd->OUT_ep[ep_addr & 0xFU].xfer_count;\r\n}\r\n/**\r\n  * @brief  Send an amount of data\r\n  * @param  hpcd PCD handle\r\n  * @param  ep_addr endpoint address\r\n  * @param  pBuf pointer to the transmission buffer\r\n  * @param  len amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)\r\n{\r\n  PCD_EPTypeDef *ep;\r\n\r\n  ep = &hpcd->IN_ep[ep_addr & 0xFU];\r\n\r\n  /*setup and start the Xfer */\r\n  ep->xfer_buff = pBuf;\r\n  ep->xfer_len = len;\r\n  ep->xfer_count = 0U;\r\n  ep->is_in = 1U;\r\n  ep->num = ep_addr & 0xFU;\r\n\r\n  if (hpcd->Init.dma_enable == 1U)\r\n  {\r\n    ep->dma_addr = (uint32_t)pBuf;\r\n  }\r\n\r\n  if ((ep_addr & 0xFU) == 0U)\r\n  {\r\n    (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);\r\n  }\r\n  else\r\n  {\r\n    (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Set a STALL condition over an endpoint\r\n  * @param  hpcd PCD handle\r\n  * @param  ep_addr endpoint address\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)\r\n{\r\n  PCD_EPTypeDef *ep;\r\n\r\n  if (((uint32_t)ep_addr & 0xFU) > hpcd->Init.dev_endpoints)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  if ((0x80U & ep_addr) == 0x80U)\r\n  {\r\n    ep = &hpcd->IN_ep[ep_addr & 0xFU];\r\n    ep->is_in = 1U;\r\n  }\r\n  else\r\n  {\r\n    ep = &hpcd->OUT_ep[ep_addr];\r\n    ep->is_in = 0U;\r\n  }\r\n\r\n  ep->is_stall = 1U;\r\n  ep->num = ep_addr & 0xFU;\r\n\r\n  __HAL_LOCK(hpcd);\r\n\r\n  (void)USB_EPSetStall(hpcd->Instance, ep);\r\n  if((ep_addr & 0xFU) == 0U)\r\n  {\r\n    (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);\r\n  }\r\n  __HAL_UNLOCK(hpcd);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Clear a STALL condition over in an endpoint\r\n  * @param  hpcd PCD handle\r\n  * @param  ep_addr endpoint address\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)\r\n{\r\n  PCD_EPTypeDef *ep;\r\n\r\n  if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  if ((0x80U & ep_addr) == 0x80U)\r\n  {\r\n    ep = &hpcd->IN_ep[ep_addr & 0xFU];\r\n    ep->is_in = 1U;\r\n  }\r\n  else\r\n  {\r\n    ep = &hpcd->OUT_ep[ep_addr &0xFU];\r\n    ep->is_in = 0U;\r\n  }\r\n\r\n  ep->is_stall = 0U;\r\n  ep->num = ep_addr & 0xFU;\r\n\r\n  __HAL_LOCK(hpcd);\r\n  (void)USB_EPClearStall(hpcd->Instance, ep);\r\n  __HAL_UNLOCK(hpcd);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Flush an endpoint\r\n  * @param  hpcd PCD handle\r\n  * @param  ep_addr endpoint address\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)\r\n{\r\n  __HAL_LOCK(hpcd);\r\n\r\n  if ((ep_addr & 0x80U) == 0x80U)\r\n  {\r\n    (void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & 0xFU);\r\n  }\r\n  else\r\n  {\r\n    (void)USB_FlushRxFifo(hpcd->Instance);\r\n  }\r\n\r\n  __HAL_UNLOCK(hpcd);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Activate remote wakeup signalling\r\n  * @param  hpcd PCD handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)\r\n{\r\n  return(USB_ActivateRemoteWakeup(hpcd->Instance));\r\n}\r\n\r\n/**\r\n  * @brief  De-activate remote wakeup signalling.\r\n  * @param  hpcd PCD handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)\r\n{\r\n  return(USB_DeActivateRemoteWakeup(hpcd->Instance));\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions\r\n *  @brief   Peripheral State functions\r\n *\r\n@verbatim\r\n ===============================================================================\r\n                      ##### Peripheral State functions #####\r\n ===============================================================================\r\n    [..]\r\n    This subsection permits to get in run-time the status of the peripheral\r\n    and the data flow.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Return the PCD handle state.\r\n  * @param  hpcd PCD handle\r\n  * @retval HAL state\r\n  */\r\nPCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)\r\n{\r\n  return hpcd->State;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @addtogroup PCD_Private_Functions\r\n  * @{\r\n  */\r\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\r\n/**\r\n  * @brief  Check FIFO for the next packet to be loaded.\r\n  * @param  hpcd PCD handle\r\n  * @param  epnum endpoint number\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)\r\n{\r\n  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n  USB_OTG_EPTypeDef *ep;\r\n  uint32_t len;\r\n  uint32_t len32b;\r\n  uint32_t fifoemptymsk;\r\n\r\n  ep = &hpcd->IN_ep[epnum];\r\n  len = ep->xfer_len - ep->xfer_count;\r\n\r\n  if (len > ep->maxpacket)\r\n  {\r\n    len = ep->maxpacket;\r\n  }\r\n\r\n  len32b = (len + 3U) / 4U;\r\n\r\n  while  (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b) &&\r\n          (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))\r\n  {\r\n    /* Write the FIFO */\r\n    len = ep->xfer_len - ep->xfer_count;\r\n\r\n    if (len > ep->maxpacket)\r\n    {\r\n      len = ep->maxpacket;\r\n    }\r\n    len32b = (len + 3U) / 4U;\r\n\r\n    (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, (uint8_t)hpcd->Init.dma_enable);\r\n\r\n    ep->xfer_buff  += len;\r\n    ep->xfer_count += len;\r\n  }\r\n\r\n  if(len <= 0U)\r\n  {\r\n    fifoemptymsk = (uint32_t)(0x1UL << epnum);\r\n    USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n#endif /* USB_OTG_FS || USB_OTG_HS */\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_PCD_MODULE_ENABLED */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd_ex.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_pcd_ex.c\r\n  * @author  MCD Application Team\r\n  * @brief   PCD Extended HAL module driver.\r\n  *          This file provides firmware functions to manage the following\r\n  *          functionalities of the USB Peripheral Controller:\r\n  *           + Extended features functions\r\n  *\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup PCDEx PCDEx\r\n  * @brief PCD Extended HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_PCD_MODULE_ENABLED\r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/* Private macros ------------------------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions\r\n  * @brief    PCDEx control functions\r\n *\r\n@verbatim\r\n ===============================================================================\r\n                 ##### Extended features functions #####\r\n ===============================================================================\r\n    [..]  This section provides functions allowing to:\r\n      (+) Update FIFO configuration\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\r\n/**\r\n  * @brief  Set Tx FIFO\r\n  * @param  hpcd PCD handle\r\n  * @param  fifo The number of Tx fifo\r\n  * @param  size Fifo size\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)\r\n{\r\n  uint8_t i;\r\n  uint32_t Tx_Offset;\r\n\r\n  /*  TXn min size = 16 words. (n  : Transmit FIFO index)\r\n      When a TxFIFO is not used, the Configuration should be as follows:\r\n          case 1 :  n > m    and Txn is not used    (n,m  : Transmit FIFO indexes)\r\n         --> Txm can use the space allocated for Txn.\r\n         case2  :  n < m    and Txn is not used    (n,m  : Transmit FIFO indexes)\r\n         --> Txn should be configured with the minimum space of 16 words\r\n     The FIFO is used optimally when used TxFIFOs are allocated in the top\r\n         of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.\r\n     When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */\r\n\r\n  Tx_Offset = hpcd->Instance->GRXFSIZ;\r\n\r\n  if(fifo == 0U)\r\n  {\r\n    hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset;\r\n  }\r\n  else\r\n  {\r\n    Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;\r\n    for (i = 0U; i < (fifo - 1U); i++)\r\n    {\r\n      Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);\r\n    }\r\n\r\n    /* Multiply Tx_Size by 2 to get higher performance */\r\n    hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset;\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Set Rx FIFO\r\n  * @param  hpcd PCD handle\r\n  * @param  size Size of Rx fifo\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)\r\n{\r\n  hpcd->Instance->GRXFSIZ = size;\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Activate LPM feature.\r\n  * @param  hpcd PCD handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)\r\n{\r\n  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\r\n\r\n  hpcd->lpm_active = 1U;\r\n  hpcd->LPM_State = LPM_L0;\r\n  USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;\r\n  USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Deactivate LPM feature.\r\n  * @param  hpcd PCD handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)\r\n{\r\n  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\r\n\r\n  hpcd->lpm_active = 0U;\r\n  USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;\r\n  USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);\r\n\r\n  return HAL_OK;\r\n}\r\n#endif /* USB_OTG_FS || USB_OTG_HS */\r\n\r\n\r\n/**\r\n  * @brief  Send LPM message to user layer callback.\r\n  * @param  hpcd PCD handle\r\n  * @param  msg LPM message\r\n  * @retval HAL status\r\n  */\r\n__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hpcd);\r\n  UNUSED(msg);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_PCDEx_LPM_Callback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Send BatteryCharging message to user layer callback.\r\n  * @param  hpcd PCD handle\r\n  * @param  msg LPM message\r\n  * @retval HAL status\r\n  */\r\n__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hpcd);\r\n  UNUSED(msg);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_PCDEx_BCD_Callback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_PCD_MODULE_ENABLED */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_pwr.c\r\n  * @author  MCD Application Team\r\n  * @brief   PWR HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the Power Controller (PWR) peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + Peripheral Control functions \r\n  *         \r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup PWR PWR\r\n  * @brief PWR HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_PWR_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @addtogroup PWR_Private_Constants\r\n  * @{\r\n  */\r\n\t\r\n/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask\r\n  * @{\r\n  */     \r\n#define PVD_MODE_IT               ((uint32_t)0x00010000U)\r\n#define PVD_MODE_EVT              ((uint32_t)0x00020000U)\r\n#define PVD_RISING_EDGE           ((uint32_t)0x00000001U)\r\n#define PVD_FALLING_EDGE          ((uint32_t)0x00000002U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask\r\n  * @{\r\n  */  \r\n#define  PWR_EWUP_MASK                          ((uint32_t)0x00003F00)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup PWR_Exported_Functions PWR Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions \r\n  *  @brief    Initialization and de-initialization functions\r\n  *\r\n@verbatim\r\n ===============================================================================\r\n              ##### Initialization and de-initialization functions #####\r\n ===============================================================================\r\n    [..]\r\n      After reset, the backup domain (RTC registers, RTC backup data \r\n      registers and backup SRAM) is protected against possible unwanted \r\n      write accesses. \r\n      To enable access to the RTC Domain and RTC registers, proceed as follows:\r\n        (+) Enable the Power Controller (PWR) APB1 interface clock using the\r\n            __HAL_RCC_PWR_CLK_ENABLE() macro.\r\n        (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.\r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief Deinitializes the HAL PWR peripheral registers to their default reset values.\r\n  * @retval None\r\n  */\r\nvoid HAL_PWR_DeInit(void)\r\n{\r\n  __HAL_RCC_PWR_FORCE_RESET();\r\n  __HAL_RCC_PWR_RELEASE_RESET();\r\n}\r\n\r\n/**\r\n  * @brief Enables access to the backup domain (RTC registers, RTC \r\n  *         backup data registers and backup SRAM).\r\n  * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the \r\n  *         Backup Domain Access should be kept enabled.\r\n  * @retval None\r\n  */\r\nvoid HAL_PWR_EnableBkUpAccess(void)\r\n{\r\n  /* Enable access to RTC and backup registers */\r\n  SET_BIT(PWR->CR1, PWR_CR1_DBP);\r\n}\r\n\r\n/**\r\n  * @brief Disables access to the backup domain (RTC registers, RTC \r\n  *         backup data registers and backup SRAM).\r\n  * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the \r\n  *         Backup Domain Access should be kept enabled.\r\n  * @retval None\r\n  */\r\nvoid HAL_PWR_DisableBkUpAccess(void)\r\n{\r\n  /* Disable access to RTC and backup registers */\r\n\tCLEAR_BIT(PWR->CR1, PWR_CR1_DBP);\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions \r\n  *  @brief Low Power modes configuration functions \r\n  *\r\n@verbatim\r\n\r\n ===============================================================================\r\n                 ##### Peripheral Control functions #####\r\n ===============================================================================\r\n     \r\n    *** PVD configuration ***\r\n    =========================\r\n    [..]\r\n      (+) The PVD is used to monitor the VDD power supply by comparing it to a \r\n          threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).\r\n      (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower \r\n          than the PVD threshold. This event is internally connected to the EXTI \r\n          line16 and can generate an interrupt if enabled. This is done through\r\n          __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.\r\n      (+) The PVD is stopped in Standby mode.\r\n\r\n    *** Wake-up pin configuration ***\r\n    ================================\r\n    [..]\r\n      (+) Wake-up pin is used to wake up the system from Standby mode. This pin is \r\n          forced in input pull-down configuration and is active on rising edges.\r\n      (+) There are up to 6 Wake-up pin in the STM32F7 devices family\r\n\r\n    *** Low Power modes configuration ***\r\n    =====================================\r\n    [..]\r\n      The devices feature 3 low-power modes:\r\n      (+) Sleep mode: Cortex-M7 core stopped, peripherals kept running.\r\n      (+) Stop mode: all clocks are stopped, regulator running, regulator \r\n          in low power mode\r\n      (+) Standby mode: 1.2V domain powered off.\r\n   \r\n   *** Sleep mode ***\r\n   ==================\r\n    [..]\r\n      (+) Entry:\r\n        The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI)\r\n              functions with\r\n          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction\r\n          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction\r\n      \r\n      -@@- The Regulator parameter is not used for the STM32F7 family \r\n              and is kept as parameter just to maintain compatibility with the \r\n              lower power families (STM32L).\r\n      (+) Exit:\r\n        Any peripheral interrupt acknowledged by the nested vectored interrupt \r\n              controller (NVIC) can wake up the device from Sleep mode.\r\n\r\n   *** Stop mode ***\r\n   =================\r\n    [..]\r\n      In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,\r\n      and the HSE RC oscillators are disabled. Internal SRAM and register contents \r\n      are preserved.\r\n      The voltage regulator can be configured either in normal or low-power mode.\r\n      To minimize the consumption In Stop mode, FLASH can be powered off before \r\n      entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.\r\n      It can be switched on again by software after exiting the Stop mode using\r\n      the HAL_PWREx_DisableFlashPowerDown() function. \r\n\r\n      (+) Entry:\r\n         The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON) \r\n             function with:\r\n          (++) Main regulator ON.\r\n          (++) Low Power regulator ON.\r\n      (+) Exit:\r\n        Any EXTI Line (Internal or External) configured in Interrupt/Event mode.\r\n\r\n   *** Standby mode ***\r\n   ====================\r\n    [..]\r\n    (+)\r\n      The Standby mode allows to achieve the lowest power consumption. It is based \r\n      on the Cortex-M7 deep sleep mode, with the voltage regulator disabled. \r\n      The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and \r\n      the HSE oscillator are also switched off. SRAM and register contents are lost \r\n      except for the RTC registers, RTC backup registers, backup SRAM and Standby \r\n      circuitry.\r\n   \r\n      The voltage regulator is OFF.\r\n      \r\n      (++) Entry:\r\n        (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.\r\n      (++) Exit:\r\n        (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC\r\n             wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset.\r\n\r\n   *** Auto-wakeup (AWU) from low-power mode ***\r\n   =============================================\r\n    [..]\r\n    \r\n     (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC \r\n      Wakeup event, a tamper event or a time-stamp event, without depending on \r\n      an external interrupt (Auto-wakeup mode).\r\n\r\n      (+) RTC auto-wakeup (AWU) from the Stop and Standby modes\r\n       \r\n        (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to \r\n              configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.\r\n\r\n        (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it \r\n             is necessary to configure the RTC to detect the tamper or time stamp event using the\r\n                HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.\r\n                  \r\n        (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to\r\n              configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).\r\n  * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration\r\n  *        information for the PVD.\r\n  * @note Refer to the electrical characteristics of your device datasheet for\r\n  *         more details about the voltage threshold corresponding to each \r\n  *         detection level.\r\n  * @retval None\r\n  */\r\nvoid HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));\r\n  assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));\r\n  \r\n  /* Set PLS[7:5] bits according to PVDLevel value */\r\n  MODIFY_REG(PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);\r\n  \r\n  /* Clear any previous config. Keep it clear if no event or IT mode is selected */\r\n  __HAL_PWR_PVD_EXTI_DISABLE_EVENT();\r\n  __HAL_PWR_PVD_EXTI_DISABLE_IT();\r\n  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\r\n  __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \r\n\r\n  /* Configure interrupt mode */\r\n  if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)\r\n  {\r\n    __HAL_PWR_PVD_EXTI_ENABLE_IT();\r\n  }\r\n  \r\n  /* Configure event mode */\r\n  if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)\r\n  {\r\n    __HAL_PWR_PVD_EXTI_ENABLE_EVENT();\r\n  }\r\n  \r\n  /* Configure the edge */\r\n  if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)\r\n  {\r\n    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\r\n  }\r\n  \r\n  if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)\r\n  {\r\n    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Enables the Power Voltage Detector(PVD).\r\n  * @retval None\r\n  */\r\nvoid HAL_PWR_EnablePVD(void)\r\n{\r\n  /* Enable the power voltage detector */\r\n\tSET_BIT(PWR->CR1, PWR_CR1_PVDE);\r\n}\r\n\r\n/**\r\n  * @brief Disables the Power Voltage Detector(PVD).\r\n  * @retval None\r\n  */\r\nvoid HAL_PWR_DisablePVD(void)\r\n{\r\n  /* Disable the power voltage detector */\r\n\tCLEAR_BIT(PWR->CR1, PWR_CR1_PVDE);\r\n}\r\n\r\n/**\r\n  * @brief Enable the WakeUp PINx functionality.\r\n  * @param WakeUpPinPolarity Specifies which Wake-Up pin to enable.\r\n  *         This parameter can be one of the following legacy values, which sets the default polarity: \r\n  *         detection on high level (rising edge):\r\n  *           @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6 \r\n  *         or one of the following value where the user can explicitly states the enabled pin and\r\n  *         the chosen polarity  \r\n  *           @arg PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW \r\n  *           @arg PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW \r\n  *           @arg PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW \r\n  *           @arg PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW\r\n  *           @arg PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW \r\n  *           @arg PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW \r\n  * @note  PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.               \r\n  * @retval None\r\n  */\r\nvoid HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)\r\n{\r\n  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));\r\n  \r\n  /* Enable wake-up pin */\r\n  SET_BIT(PWR->CSR2, (PWR_EWUP_MASK & WakeUpPinPolarity));\r\n\t\r\n  /* Specifies the Wake-Up pin polarity for the event detection\r\n    (rising or falling edge) */\r\n  MODIFY_REG(PWR->CR2, (PWR_EWUP_MASK & WakeUpPinPolarity), (WakeUpPinPolarity >> 0x06));\r\n}\r\n\r\n/**\r\n  * @brief Disables the WakeUp PINx functionality.\r\n  * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.\r\n  *         This parameter can be one of the following values:\r\n  *           @arg PWR_WAKEUP_PIN1\r\n  *           @arg PWR_WAKEUP_PIN2\r\n  *           @arg PWR_WAKEUP_PIN3\r\n  *           @arg PWR_WAKEUP_PIN4\r\n  *           @arg PWR_WAKEUP_PIN5\r\n  *           @arg PWR_WAKEUP_PIN6 \r\n  * @retval None\r\n  */\r\nvoid HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)\r\n{\r\n  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));\r\n\r\n  CLEAR_BIT(PWR->CSR2, WakeUpPinx);\r\n}\r\n  \r\n/**\r\n  * @brief Enters Sleep mode.\r\n  *   \r\n  * @note In Sleep mode, all I/O pins keep the same state as in Run mode.\r\n  * \r\n  * @note In Sleep mode, the systick is stopped to avoid exit from this mode with\r\n  *       systick interrupt when used as time base for Timeout \r\n  *                \r\n  * @param Regulator Specifies the regulator state in SLEEP mode.\r\n  *            This parameter can be one of the following values:\r\n  *            @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON\r\n  *            @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON\r\n  * @note This parameter is not used for the STM32F7 family and is kept as parameter\r\n  *       just to maintain compatibility with the lower power families.\r\n  * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction\r\n  *            @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction\r\n  * @retval None\r\n  */\r\nvoid HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_PWR_REGULATOR(Regulator));\r\n  assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));\r\n\r\n  UNUSED(Regulator);\r\n\r\n  /* Clear SLEEPDEEP bit of Cortex System Control Register */\r\n  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r\n\r\n  /* Ensure that all instructions done before entering SLEEP mode */\r\n  __DSB();\r\n  __ISB();\r\n\r\n  /* Select SLEEP mode entry -------------------------------------------------*/\r\n  if(SLEEPEntry == PWR_SLEEPENTRY_WFI)\r\n  {   \r\n    /* Request Wait For Interrupt */\r\n    __WFI();\r\n  }\r\n  else\r\n  {\r\n    /* Request Wait For Event */\r\n    __SEV();\r\n    __WFE();\r\n    __WFE();\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Enters Stop mode. \r\n  * @note In Stop mode, all I/O pins keep the same state as in Run mode.\r\n  * @note When exiting Stop mode by issuing an interrupt or a wakeup event, \r\n  *         the HSI RC oscillator is selected as system clock.\r\n  * @note When the voltage regulator operates in low power mode, an additional \r\n  *         startup delay is incurred when waking up from Stop mode. \r\n  *         By keeping the internal regulator ON during Stop mode, the consumption \r\n  *         is higher although the startup time is reduced.    \r\n  * @param Regulator Specifies the regulator state in Stop mode.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON\r\n  *            @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON\r\n  * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction\r\n  *            @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction\r\n  * @retval None\r\n  */\r\nvoid HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)\r\n{\r\n  uint32_t tmpreg = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_PWR_REGULATOR(Regulator));\r\n  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));\r\n\r\n  /* Select the regulator state in Stop mode ---------------------------------*/\r\n  tmpreg = PWR->CR1;\r\n  /* Clear PDDS and LPDS bits */\r\n  tmpreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS);\r\n\r\n  /* Set LPDS, MRLVDS and LPLVDS bits according to Regulator value */\r\n  tmpreg |= Regulator;\r\n\r\n  /* Store the new value */\r\n  PWR->CR1 = tmpreg;\r\n\r\n  /* Set SLEEPDEEP bit of Cortex System Control Register */\r\n  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r\n\r\n  /* Ensure that all instructions done before entering STOP mode */\r\n  __DSB();\r\n  __ISB();\r\n\r\n  /* Select Stop mode entry --------------------------------------------------*/\r\n  if(STOPEntry == PWR_STOPENTRY_WFI)\r\n  {   \r\n    /* Request Wait For Interrupt */\r\n    __WFI();\r\n  }\r\n  else\r\n  {\r\n    /* Request Wait For Event */\r\n    __SEV();\r\n    __WFE();\r\n    __WFE();\r\n  }\r\n  /* Reset SLEEPDEEP bit of Cortex System Control Register */\r\n  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);  \r\n}\r\n\r\n/**\r\n  * @brief Enters Standby mode.\r\n  * @note In Standby mode, all I/O pins are high impedance except for:\r\n  *          - Reset pad (still available) \r\n  *          - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC \r\n  *            Alarm out, or RTC clock calibration out.\r\n  *          - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.  \r\n  *          - WKUP pins if enabled.       \r\n  * @retval None\r\n  */\r\nvoid HAL_PWR_EnterSTANDBYMode(void)\r\n{\r\n  /* Select Standby mode */\r\n  PWR->CR1 |= PWR_CR1_PDDS;\r\n  \r\n  /* Set SLEEPDEEP bit of Cortex System Control Register */\r\n  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r\n  \r\n  /* This option is used to ensure that store operations are completed */\r\n#if defined ( __CC_ARM)\r\n  __force_stores();\r\n#endif\r\n  /* Request Wait For Interrupt */\r\n  __WFI();\r\n}\r\n\r\n/**\r\n  * @brief This function handles the PWR PVD interrupt request.\r\n  * @note This API should be called under the PVD_IRQHandler().\r\n  * @retval None\r\n  */\r\nvoid HAL_PWR_PVD_IRQHandler(void)\r\n{\r\n  /* Check PWR Exti flag */\r\n  if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)\r\n  {\r\n    /* PWR PVD interrupt user callback */\r\n    HAL_PWR_PVDCallback();\r\n    \r\n    /* Clear PWR Exti pending bit */\r\n    __HAL_PWR_PVD_EXTI_CLEAR_FLAG();\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  PWR PVD interrupt callback\r\n  * @retval None\r\n  */\r\n__weak void HAL_PWR_PVDCallback(void)\r\n{\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_PWR_PVDCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. \r\n  * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor \r\n  *       re-enters SLEEP mode when an interruption handling is over.\r\n  *       Setting this bit is useful when the processor is expected to run only on\r\n  *       interruptions handling.         \r\n  * @retval None\r\n  */\r\nvoid HAL_PWR_EnableSleepOnExit(void)\r\n{\r\n  /* Set SLEEPONEXIT bit of Cortex System Control Register */\r\n  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));\r\n}\r\n\r\n/**\r\n  * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. \r\n  * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor \r\n  *       re-enters SLEEP mode when an interruption handling is over.          \r\n  * @retval None\r\n  */\r\nvoid HAL_PWR_DisableSleepOnExit(void)\r\n{\r\n  /* Clear SLEEPONEXIT bit of Cortex System Control Register */\r\n  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));\r\n}\r\n\r\n/**\r\n  * @brief Enables CORTEX M4 SEVONPEND bit. \r\n  * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes \r\n  *       WFE to wake up when an interrupt moves from inactive to pended.\r\n  * @retval None\r\n  */\r\nvoid HAL_PWR_EnableSEVOnPend(void)\r\n{\r\n  /* Set SEVONPEND bit of Cortex System Control Register */\r\n  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));\r\n}\r\n\r\n/**\r\n  * @brief Disables CORTEX M4 SEVONPEND bit. \r\n  * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes \r\n  *       WFE to wake up when an interrupt moves from inactive to pended.         \r\n  * @retval None\r\n  */\r\nvoid HAL_PWR_DisableSEVOnPend(void)\r\n{\r\n  /* Clear SEVONPEND bit of Cortex System Control Register */\r\n  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_PWR_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_pwr_ex.c\r\n  * @author  MCD Application Team\r\n  * @brief   Extended PWR HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of PWR extension peripheral:           \r\n  *           + Peripheral Extended features functions\r\n  *         \r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup PWREx PWREx\r\n  * @brief PWR HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_PWR_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @addtogroup PWREx_Private_Constants\r\n  * @{\r\n  */    \r\n#define PWR_OVERDRIVE_TIMEOUT_VALUE  1000\r\n#define PWR_UDERDRIVE_TIMEOUT_VALUE  1000\r\n#define PWR_BKPREG_TIMEOUT_VALUE     1000\r\n#define PWR_VOSRDY_TIMEOUT_VALUE     1000\r\n/**\r\n  * @}\r\n  */\r\n    \r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup PWREx_Exported_Functions PWREx Exported Functions\r\n  *  @{\r\n  */\r\n\r\n/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions \r\n  *  @brief Peripheral Extended features functions \r\n  *\r\n@verbatim   \r\n\r\n ===============================================================================\r\n                 ##### Peripheral extended features functions #####\r\n ===============================================================================\r\n\r\n    *** Main and Backup Regulators configuration ***\r\n    ================================================\r\n    [..] \r\n      (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from \r\n          the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is \r\n          retained even in Standby or VBAT mode when the low power backup regulator\r\n          is enabled. It can be considered as an internal EEPROM when VBAT is \r\n          always present. You can use the HAL_PWREx_EnableBkUpReg() function to \r\n          enable the low power backup regulator. \r\n\r\n      (+) When the backup domain is supplied by VDD (analog switch connected to VDD) \r\n          the backup SRAM is powered from VDD which replaces the VBAT power supply to \r\n          save battery life.\r\n\r\n      (+) The backup SRAM is not mass erased by a tamper event. It is read \r\n          protected to prevent confidential data, such as cryptographic private \r\n          key, from being accessed. The backup SRAM can be erased only through \r\n          the Flash interface when a protection level change from level 1 to \r\n          level 0 is requested. \r\n      -@- Refer to the description of Read protection (RDP) in the Flash \r\n          programming manual.\r\n\r\n      (+) The main internal regulator can be configured to have a tradeoff between \r\n          performance and power consumption when the device does not operate at \r\n          the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG() \r\n          macro which configure VOS bit in PWR_CR register\r\n          \r\n        Refer to the product datasheets for more details.\r\n\r\n    *** FLASH Power Down configuration ****\r\n    =======================================\r\n    [..] \r\n      (+) By setting the FPDS bit in the PWR_CR register by using the \r\n          HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power \r\n          down mode when the device enters Stop mode. When the Flash memory \r\n          is in power down mode, an additional startup delay is incurred when \r\n          waking up from Stop mode.\r\n\r\n    *** Over-Drive and Under-Drive configuration ****\r\n    =================================================\r\n    [..]         \r\n       (+) In Run mode: the main regulator has 2 operating modes available:\r\n        (++) Normal mode: The CPU and core logic operate at maximum frequency at a given \r\n             voltage scaling (scale 1, scale 2 or scale 3)\r\n        (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a \r\n            higher frequency than the normal mode for a given voltage scaling (scale 1,  \r\n            scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and\r\n            disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow \r\n            the sequence described in Reference manual.\r\n             \r\n       (+) In Stop mode: the main regulator or low power regulator supplies a low power \r\n           voltage to the 1.2V domain, thus preserving the content of registers \r\n           and internal SRAM. 2 operating modes are available:\r\n         (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only \r\n              available when the main regulator or the low power regulator is used in Scale 3 or \r\n              low voltage mode.\r\n         (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only\r\n              available when the main regulator or the low power regulator is in low voltage mode.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief Enables the Backup Regulator.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)\r\n{\r\n  uint32_t tickstart = 0;\r\n\r\n  /* Enable Backup regulator */\r\n  PWR->CSR1 |= PWR_CSR1_BRE;\r\n    \r\n  /* Workaround for the following hardware bug: */\r\n  /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */\r\n  PWR->CSR1 |= PWR_CSR1_EIWUP;\r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Wait till Backup regulator ready flag is set */  \r\n  while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET)\r\n  {\r\n    if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    } \r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Disables the Backup Regulator.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Disable Backup regulator */\r\n  PWR->CSR1 &= (uint32_t)~((uint32_t)PWR_CSR1_BRE);\r\n  \r\n  /* Workaround for the following hardware bug: */\r\n  /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */\r\n  PWR->CSR1 |= PWR_CSR1_EIWUP;\r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Wait till Backup regulator ready flag is set */  \r\n  while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)\r\n  {\r\n    if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    } \r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Enables the Flash Power Down in Stop mode.\r\n  * @retval None\r\n  */\r\nvoid HAL_PWREx_EnableFlashPowerDown(void)\r\n{\r\n  /* Enable the Flash Power Down */\r\n  PWR->CR1 |= PWR_CR1_FPDS;\r\n}\r\n\r\n/**\r\n  * @brief Disables the Flash Power Down in Stop mode.\r\n  * @retval None\r\n  */\r\nvoid HAL_PWREx_DisableFlashPowerDown(void)\r\n{\r\n  /* Disable the Flash Power Down */\r\n  PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_FPDS);\r\n}\r\n\r\n/**\r\n  * @brief Enables Main Regulator low voltage mode.\r\n  * @retval None\r\n  */\r\nvoid HAL_PWREx_EnableMainRegulatorLowVoltage(void)\r\n{\r\n  /* Enable Main regulator low voltage */\r\n  PWR->CR1 |= PWR_CR1_MRUDS;\r\n}\r\n\r\n/**\r\n  * @brief Disables Main Regulator low voltage mode.\r\n  * @retval None\r\n  */\r\nvoid HAL_PWREx_DisableMainRegulatorLowVoltage(void)\r\n{  \r\n  /* Disable Main regulator low voltage */\r\n  PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_MRUDS);\r\n}\r\n\r\n/**\r\n  * @brief Enables Low Power Regulator low voltage mode.\r\n  * @retval None\r\n  */\r\nvoid HAL_PWREx_EnableLowRegulatorLowVoltage(void)\r\n{\r\n  /* Enable low power regulator */\r\n  PWR->CR1 |= PWR_CR1_LPUDS;\r\n}\r\n\r\n/**\r\n  * @brief Disables Low Power Regulator low voltage mode.\r\n  * @retval None\r\n  */\r\nvoid HAL_PWREx_DisableLowRegulatorLowVoltage(void)\r\n{\r\n  /* Disable low power regulator */\r\n  PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_LPUDS);\r\n}\r\n\r\n/**\r\n  * @brief  Activates the Over-Drive mode.\r\n  * @note   This mode allows the CPU and the core logic to operate at a higher frequency\r\n  *         than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).   \r\n  * @note   It is recommended to enter or exit Over-drive mode when the application is not running \r\n  *         critical tasks and when the system clock source is either HSI or HSE. \r\n  *         During the Over-drive switch activation, no peripheral clocks should be enabled.   \r\n  *         The peripheral clocks must be enabled once the Over-drive mode is activated.   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)\r\n{\r\n  uint32_t tickstart = 0;\r\n\r\n  __HAL_RCC_PWR_CLK_ENABLE();\r\n  \r\n  /* Enable the Over-drive to extend the clock frequency to 216 MHz */\r\n  __HAL_PWR_OVERDRIVE_ENABLE();\r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))\r\n  {\r\n    if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  \r\n  /* Enable the Over-drive switch */\r\n  __HAL_PWR_OVERDRIVESWITCHING_ENABLE();\r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))\r\n  {\r\n    if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  } \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Deactivates the Over-Drive mode.\r\n  * @note   This mode allows the CPU and the core logic to operate at a higher frequency\r\n  *         than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).    \r\n  * @note   It is recommended to enter or exit Over-drive mode when the application is not running \r\n  *         critical tasks and when the system clock source is either HSI or HSE. \r\n  *         During the Over-drive switch activation, no peripheral clocks should be enabled.   \r\n  *         The peripheral clocks must be enabled once the Over-drive mode is activated.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  __HAL_RCC_PWR_CLK_ENABLE();\r\n    \r\n  /* Disable the Over-drive switch */\r\n  __HAL_PWR_OVERDRIVESWITCHING_DISABLE();\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n \r\n  while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))\r\n  {\r\n    if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  } \r\n  \r\n  /* Disable the Over-drive */\r\n  __HAL_PWR_OVERDRIVE_DISABLE();\r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))\r\n  {\r\n    if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Enters in Under-Drive STOP mode.\r\n  * \r\n  * @note    This mode can be selected only when the Under-Drive is already active \r\n  *   \r\n  * @note    This mode is enabled only with STOP low power mode.\r\n  *          In this mode, the 1.2V domain is preserved in reduced leakage mode. This \r\n  *          mode is only available when the main regulator or the low power regulator \r\n  *          is in low voltage mode\r\n  *        \r\n  * @note   If the Under-drive mode was enabled, it is automatically disabled after \r\n  *         exiting Stop mode. \r\n  *         When the voltage regulator operates in Under-drive mode, an additional  \r\n  *         startup delay is induced when waking up from Stop mode.\r\n  *                    \r\n  * @note   In Stop mode, all I/O pins keep the same state as in Run mode.\r\n  *   \r\n  * @note   When exiting Stop mode by issuing an interrupt or a wakeup event, \r\n  *         the HSI RC oscillator is selected as system clock.\r\n  *           \r\n  * @note   When the voltage regulator operates in low power mode, an additional \r\n  *         startup delay is incurred when waking up from Stop mode. \r\n  *         By keeping the internal regulator ON during Stop mode, the consumption \r\n  *         is higher although the startup time is reduced.\r\n  *     \r\n  * @param  Regulator specifies the regulator state in STOP mode.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg PWR_MAINREGULATOR_UNDERDRIVE_ON:  Main Regulator in under-drive mode \r\n  *                 and Flash memory in power-down when the device is in Stop under-drive mode\r\n  *            @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON:  Low Power Regulator in under-drive mode \r\n  *                and Flash memory in power-down when the device is in Stop under-drive mode\r\n  * @param  STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction\r\n  *            @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction\r\n  * @retval None\r\n  */\r\nHAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry)\r\n{\r\n  uint32_t tempreg = 0;\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator));\r\n  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));\r\n  \r\n  /* Enable Power ctrl clock */\r\n  __HAL_RCC_PWR_CLK_ENABLE();\r\n  /* Enable the Under-drive Mode ---------------------------------------------*/\r\n  /* Clear Under-drive flag */\r\n  __HAL_PWR_CLEAR_ODRUDR_FLAG();\r\n  \r\n  /* Enable the Under-drive */ \r\n  __HAL_PWR_UNDERDRIVE_ENABLE();\r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Wait for UnderDrive mode is ready */\r\n  while(__HAL_PWR_GET_FLAG(PWR_FLAG_UDRDY))\r\n  {\r\n    if((HAL_GetTick() - tickstart ) > PWR_UDERDRIVE_TIMEOUT_VALUE)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  \r\n  /* Select the regulator state in STOP mode ---------------------------------*/\r\n  tempreg = PWR->CR1;\r\n  /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */\r\n  tempreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS);\r\n  \r\n  /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */\r\n  tempreg |= Regulator;\r\n  \r\n  /* Store the new value */\r\n  PWR->CR1 = tempreg;\r\n  \r\n  /* Set SLEEPDEEP bit of Cortex System Control Register */\r\n  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r\n  \r\n  /* Select STOP mode entry --------------------------------------------------*/\r\n  if(STOPEntry == PWR_SLEEPENTRY_WFI)\r\n  {   \r\n    /* Request Wait For Interrupt */\r\n    __WFI();\r\n  }\r\n  else\r\n  {\r\n    /* Request Wait For Event */\r\n    __WFE();\r\n  }\r\n  /* Reset SLEEPDEEP bit of Cortex System Control Register */\r\n  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);\r\n\r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief Returns Voltage Scaling Range.\r\n  * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or \r\n  *            PWR_REGULATOR_VOLTAGE_SCALE3)PWR_REGULATOR_VOLTAGE_SCALE1\r\n  */  \r\nuint32_t HAL_PWREx_GetVoltageRange(void)\r\n{\r\n  return  (PWR->CR1 & PWR_CR1_VOS);\r\n}\r\n\r\n/**\r\n  * @brief Configures the main internal regulator output voltage.\r\n  * @param  VoltageScaling specifies the regulator output voltage to achieve\r\n  *         a tradeoff between performance and power consumption.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,\r\n  *                                                typical output voltage at 1.4 V,  \r\n  *                                                system frequency up to 216 MHz.\r\n  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,\r\n  *                                                typical output voltage at 1.2 V,                \r\n  *                                                system frequency up to 180 MHz.\r\n  *            @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 2 mode,\r\n  *                                                typical output voltage at 1.00 V,                \r\n  *                                                system frequency up to 151 MHz.\r\n  * @note To update the system clock frequency(SYSCLK):\r\n  *        - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig().\r\n  *        - Call the HAL_RCC_OscConfig() to configure the PLL.\r\n  *        - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale.\r\n  *        - Set the new system clock frequency using the HAL_RCC_ClockConfig().\r\n  * @note The scale can be modified only when the HSI or HSE clock source is selected \r\n  *        as system clock source, otherwise the API returns HAL_ERROR.  \r\n  * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits\r\n  *       value in the PWR_CR1 register are not taken in account.\r\n  * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2.\r\n  * @note The new voltage scale is active only when the PLL is ON.  \r\n  * @retval HAL Status\r\n  */\r\nHAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)\r\n{\r\n  uint32_t tickstart = 0;\r\n\r\n  assert_param(IS_PWR_REGULATOR_VOLTAGE(VoltageScaling));\r\n\r\n  /* Enable Power ctrl clock */\r\n  __HAL_RCC_PWR_CLK_ENABLE();\r\n\r\n  /* Check if the PLL is used as system clock or not */\r\n  if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)\r\n  {\r\n    /* Disable the main PLL */\r\n    __HAL_RCC_PLL_DISABLE();\r\n    \r\n    /* Get Start Tick */\r\n    tickstart = HAL_GetTick();    \r\n    /* Wait till PLL is disabled */  \r\n    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n    \r\n    /* Set Range */\r\n    __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);\r\n    \r\n    /* Enable the main PLL */\r\n    __HAL_RCC_PLL_ENABLE();\r\n    \r\n    /* Get Start Tick */\r\n    tickstart = HAL_GetTick();\r\n    /* Wait till PLL is ready */  \r\n    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      } \r\n    }\r\n    \r\n    /* Get Start Tick */\r\n    tickstart = HAL_GetTick();\r\n    while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      } \r\n    }\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_PWR_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_rcc.c\r\n  * @author  MCD Application Team\r\n  * @brief   RCC HAL module driver.\r\n  *          This file provides firmware functions to manage the following\r\n  *          functionalities of the Reset and Clock Control (RCC) peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + Peripheral Control functions\r\n  *\r\n  @verbatim\r\n  ==============================================================================\r\n                      ##### RCC specific features #####\r\n  ==============================================================================\r\n    [..]\r\n      After reset the device is running from Internal High Speed oscillator\r\n      (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache\r\n      and I-Cache are disabled, and all peripherals are off except internal\r\n      SRAM, Flash and JTAG.\r\n      (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;\r\n          all peripherals mapped on these busses are running at HSI speed.\r\n      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.\r\n      (+) All GPIOs are in input floating state, except the JTAG pins which\r\n          are assigned to be used for debug purpose.\r\n\r\n    [..]\r\n      Once the device started from reset, the user application has to:\r\n      (+) Configure the clock source to be used to drive the System clock\r\n          (if the application needs higher frequency/performance)\r\n      (+) Configure the System clock frequency and Flash settings\r\n      (+) Configure the AHB and APB busses prescalers\r\n      (+) Enable the clock for the peripheral(s) to be used\r\n      (+) Configure the clock source(s) for peripherals which clocks are not\r\n          derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)\r\n\r\n                      ##### RCC Limitations #####\r\n  ==============================================================================\r\n    [..]\r\n      A delay between an RCC peripheral clock enable and the effective peripheral\r\n      enabling should be taken into account in order to manage the peripheral read/write\r\n      from/to registers.\r\n      (+) This delay depends on the peripheral mapping.\r\n      (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle\r\n          after the clock enable bit is set on the hardware register\r\n      (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle\r\n          after the clock enable bit is set on the hardware register\r\n\r\n    [..]\r\n      Implemented Workaround:\r\n      (+) For AHB & APB peripherals, a dummy read to the peripheral register has been\r\n          inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup RCC RCC\r\n  * @brief RCC HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_RCC_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/** @defgroup RCC_Private_Macros RCC Private Macros\r\n  * @{\r\n  */\r\n\r\n#define MCO1_CLK_ENABLE()   __HAL_RCC_GPIOA_CLK_ENABLE()\r\n#define MCO1_GPIO_PORT        GPIOA\r\n#define MCO1_PIN              GPIO_PIN_8\r\n\r\n#define MCO2_CLK_ENABLE()   __HAL_RCC_GPIOC_CLK_ENABLE()\r\n#define MCO2_GPIO_PORT         GPIOC\r\n#define MCO2_PIN               GPIO_PIN_9\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @defgroup RCC_Private_Variables RCC Private Variables\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Exported functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup RCC_Exported_Functions RCC Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions\r\n  *  @brief    Initialization and Configuration functions\r\n  *\r\n  @verbatim\r\n  ===============================================================================\r\n##### Initialization and de-initialization functions #####\r\n  ===============================================================================\r\n    [..]\r\n      This section provides functions allowing to configure the internal/external oscillators\r\n      (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1\r\n      and APB2).\r\n\r\n    [..] Internal/external clock and PLL configuration\r\n      (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through\r\n          the PLL as System clock source.\r\n\r\n      (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC\r\n          clock source.\r\n\r\n      (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or\r\n          through the PLL as System clock source. Can be used also as RTC clock source.\r\n\r\n      (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.\r\n\r\n      (#) PLL (clocked by HSI or HSE), featuring two different output clocks:\r\n        (++) The first output is used to generate the high speed system clock (up to 216 MHz)\r\n        (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),\r\n             the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).\r\n\r\n      (#) CSS (Clock security system), once enable using the function HAL_RCC_EnableCSS()\r\n          and if a HSE clock failure occurs(HSE used directly or through PLL as System\r\n          clock source), the System clock is automatically switched to HSI and an interrupt\r\n          is generated if enabled. The interrupt is linked to the Cortex-M7 NMI\r\n          (Non-Maskable Interrupt) exception vector.\r\n\r\n      (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL\r\n          clock (through a configurable prescaler) on PA8 pin.\r\n\r\n      (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S\r\n          clock (through a configurable prescaler) on PC9 pin.\r\n\r\n    [..] System, AHB and APB busses clocks configuration\r\n      (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,\r\n          HSE and PLL.\r\n          The AHB clock (HCLK) is derived from System clock through configurable\r\n          prescaler and used to clock the CPU, memory and peripherals mapped\r\n          on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived\r\n          from AHB clock through configurable prescalers and used to clock\r\n          the peripherals mapped on these busses. You can use\r\n          \"HAL_RCC_GetSysClockFreq()\" function to retrieve the frequencies of these clocks.\r\n\r\n      -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:\r\n          (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or\r\n              from an external clock mapped on the I2S_CKIN pin.\r\n              You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.\r\n          (+@)  SAI: the SAI clock can be derived either from a specific PLL (PLLI2S) or (PLLSAI) or\r\n              from an external clock mapped on the I2S_CKIN pin.\r\n               You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.\r\n          (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock\r\n              divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()\r\n              macros to configure this clock.\r\n          (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz\r\n              to work correctly, while the SDIO require a frequency equal or lower than\r\n              to 48. This clock is derived of the main PLL through PLLQ divider.\r\n          (+@) IWDG clock which is always the LSI clock.\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Resets the RCC clock configuration to the default reset state.\r\n  * @note   The default reset state of the clock configuration is given below:\r\n  *            - HSI ON and used as system clock source\r\n  *            - HSE, PLL, PLLI2S and PLLSAI OFF\r\n  *            - AHB, APB1 and APB2 prescaler set to 1.\r\n  *            - CSS, MCO1 and MCO2 OFF\r\n  *            - All interrupts disabled\r\n  * @note   This function doesn't modify the configuration of the\r\n  *            - Peripheral clocks\r\n  *            - LSI, LSE and RTC clocks\r\n  * @retval None\r\n  */\r\nHAL_StatusTypeDef HAL_RCC_DeInit(void)\r\n{\r\n  uint32_t tickstart;\r\n\r\n  /* Get Start Tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Set HSION bit to the reset value */\r\n  SET_BIT(RCC->CR, RCC_CR_HSION);\r\n\r\n  /* Wait till HSI is ready */\r\n  while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)\r\n  {\r\n    if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n\r\n  /* Set HSITRIM[4:0] bits to the reset value */\r\n  SET_BIT(RCC->CR, RCC_CR_HSITRIM_4);\r\n\r\n  /* Get Start Tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Reset CFGR register */\r\n  CLEAR_REG(RCC->CFGR);\r\n\r\n  /* Wait till clock switch is ready */\r\n  while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET)\r\n  {\r\n    if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n\r\n  /* Get Start Tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Clear HSEON, HSEBYP and CSSON bits */\r\n  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON);\r\n\r\n  /* Wait till HSE is disabled */\r\n  while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET)\r\n  {\r\n    if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n\r\n  /* Get Start Tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Clear PLLON bit */\r\n  CLEAR_BIT(RCC->CR, RCC_CR_PLLON);\r\n\r\n  /* Wait till PLL is disabled */\r\n  while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET)\r\n  {\r\n    if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n\r\n  /* Get Start Tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Reset PLLI2SON bit */\r\n  CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);\r\n\r\n  /* Wait till PLLI2S is disabled */\r\n  while (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET)\r\n  {\r\n    if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n\r\n  /* Get Start Tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Reset PLLSAI bit */\r\n  CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);\r\n\r\n  /* Wait till PLLSAI is disabled */\r\n  while (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) != RESET)\r\n  {\r\n    if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n\r\n  /* Once PLL, PLLI2S and PLLSAI are OFF, reset PLLCFGR register to default value */\r\n  RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | 0x20000000U;\r\n\r\n  /* Reset PLLI2SCFGR register to default value */\r\n  RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1;\r\n\r\n  /* Reset PLLSAICFGR register to default value */\r\n  RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2 | 0x20000000U;\r\n\r\n  /* Disable all interrupts */\r\n  CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE | RCC_CIR_PLLI2SRDYIE | RCC_CIR_PLLSAIRDYIE);\r\n\r\n  /* Clear all interrupt flags */\r\n  SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_PLLI2SRDYC | RCC_CIR_PLLSAIRDYC | RCC_CIR_CSSC);\r\n\r\n  /* Clear LSION bit */\r\n  CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);\r\n\r\n  /* Reset all CSR flags */\r\n  SET_BIT(RCC->CSR, RCC_CSR_RMVF);\r\n\r\n  /* Update the SystemCoreClock global variable */\r\n  SystemCoreClock = HSI_VALUE;\r\n\r\n  /* Adapt Systick interrupt period */\r\n  if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  else\r\n  {\r\n    return HAL_OK;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the RCC Oscillators according to the specified parameters in the\r\n  *         RCC_OscInitTypeDef.\r\n  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that\r\n  *         contains the configuration information for the RCC Oscillators.\r\n  * @note   The PLL is not disabled when used as system clock.\r\n  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not\r\n  *         supported by this function. User should request a transition to LSE Off\r\n  *         first and then LSE On or LSE Bypass.\r\n  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not\r\n  *         supported by this function. User should request a transition to HSE Off\r\n  *         first and then HSE On or HSE Bypass.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)\r\n{\r\n  uint32_t tickstart;\r\n  FlagStatus pwrclkchanged = RESET;\r\n\r\n  /* Check Null pointer */\r\n  if(RCC_OscInitStruct == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));\r\n\r\n  /*------------------------------- HSE Configuration ------------------------*/\r\n  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));\r\n    /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */\r\n    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)\r\n       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))\r\n    {\r\n      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))\r\n      {\r\n        return HAL_ERROR;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* Set the new HSE configuration ---------------------------------------*/\r\n      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);\r\n\r\n      /* Check the HSE State */\r\n      if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)\r\n      {\r\n        /* Get Start Tick*/\r\n        tickstart = HAL_GetTick();\r\n\r\n        /* Wait till HSE is ready */\r\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)\r\n        {\r\n          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)\r\n          {\r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n      }\r\n      else\r\n      {\r\n        /* Get Start Tick*/\r\n        tickstart = HAL_GetTick();\r\n\r\n        /* Wait till HSE is bypassed or disabled */\r\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)\r\n        {\r\n           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)\r\n          {\r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n      }\r\n    }\r\n  }\r\n  /*----------------------------- HSI Configuration --------------------------*/\r\n  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));\r\n    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));\r\n\r\n    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */\r\n    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)\r\n       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))\r\n    {\r\n      /* When HSI is used as system clock it will not disabled */\r\n      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))\r\n      {\r\n        return HAL_ERROR;\r\n      }\r\n      /* Otherwise, just the calibration is allowed */\r\n      else\r\n      {\r\n        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/\r\n        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* Check the HSI State */\r\n      if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)\r\n      {\r\n        /* Enable the Internal High Speed oscillator (HSI). */\r\n        __HAL_RCC_HSI_ENABLE();\r\n\r\n        /* Get Start Tick*/\r\n        tickstart = HAL_GetTick();\r\n\r\n        /* Wait till HSI is ready */\r\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)\r\n        {\r\n          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)\r\n          {\r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n\r\n        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/\r\n        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);\r\n      }\r\n      else\r\n      {\r\n        /* Disable the Internal High Speed oscillator (HSI). */\r\n        __HAL_RCC_HSI_DISABLE();\r\n\r\n        /* Get Start Tick*/\r\n        tickstart = HAL_GetTick();\r\n\r\n        /* Wait till HSI is ready */\r\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)\r\n        {\r\n          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)\r\n          {\r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n      }\r\n    }\r\n  }\r\n  /*------------------------------ LSI Configuration -------------------------*/\r\n  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));\r\n\r\n    /* Check the LSI State */\r\n    if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)\r\n    {\r\n      /* Enable the Internal Low Speed oscillator (LSI). */\r\n      __HAL_RCC_LSI_ENABLE();\r\n\r\n      /* Get Start Tick*/\r\n      tickstart = HAL_GetTick();\r\n\r\n      /* Wait till LSI is ready */\r\n      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)\r\n      {\r\n        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* Disable the Internal Low Speed oscillator (LSI). */\r\n      __HAL_RCC_LSI_DISABLE();\r\n\r\n      /* Get Start Tick*/\r\n      tickstart = HAL_GetTick();\r\n\r\n      /* Wait till LSI is ready */\r\n      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)\r\n      {\r\n        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n  }\r\n  /*------------------------------ LSE Configuration -------------------------*/\r\n  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));\r\n\r\n    /* Update LSE configuration in Backup Domain control register    */\r\n    /* Requires to enable write access to Backup Domain of necessary */\r\n    if(__HAL_RCC_PWR_IS_CLK_DISABLED())\r\n    {\r\n      /* Enable Power Clock*/\r\n      __HAL_RCC_PWR_CLK_ENABLE();\r\n      pwrclkchanged = SET;\r\n    }\r\n\r\n    if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))\r\n    {\r\n      /* Enable write access to Backup domain */\r\n      PWR->CR1 |= PWR_CR1_DBP;\r\n\r\n      /* Wait for Backup domain Write protection disable */\r\n      tickstart = HAL_GetTick();\r\n\r\n      while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))\r\n      {\r\n        if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n\r\n    /* Set the new LSE configuration -----------------------------------------*/\r\n    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);\r\n    /* Check the LSE State */\r\n    if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)\r\n    {\r\n      /* Get Start Tick*/\r\n      tickstart = HAL_GetTick();\r\n\r\n      /* Wait till LSE is ready */\r\n      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)\r\n      {\r\n        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* Get Start Tick*/\r\n      tickstart = HAL_GetTick();\r\n\r\n      /* Wait till LSE is ready */\r\n      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)\r\n      {\r\n        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n\r\n    /* Restore clock configuration if changed */\r\n    if(pwrclkchanged == SET)\r\n    {\r\n      __HAL_RCC_PWR_CLK_DISABLE();\r\n    }\r\n  }\r\n  /*-------------------------------- PLL Configuration -----------------------*/\r\n  /* Check the parameters */\r\n  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));\r\n  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)\r\n  {\r\n    /* Check if the PLL is used as system clock or not */\r\n    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)\r\n    {\r\n      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)\r\n      {\r\n        /* Check the parameters */\r\n        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));\r\n        assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));\r\n        assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));\r\n        assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));\r\n        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));\r\n#if defined (RCC_PLLCFGR_PLLR)\r\n        assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));\r\n#endif\r\n\r\n        /* Disable the main PLL. */\r\n        __HAL_RCC_PLL_DISABLE();\r\n\r\n        /* Get Start Tick*/\r\n        tickstart = HAL_GetTick();\r\n\r\n        /* Wait till PLL is ready */\r\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)\r\n        {\r\n          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r\n          {\r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n\r\n        /* Configure the main PLL clock source, multiplication and division factors. */\r\n#if defined (RCC_PLLCFGR_PLLR)\r\n        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,\r\n                             RCC_OscInitStruct->PLL.PLLM,\r\n                             RCC_OscInitStruct->PLL.PLLN,\r\n                             RCC_OscInitStruct->PLL.PLLP,\r\n                             RCC_OscInitStruct->PLL.PLLQ,\r\n                             RCC_OscInitStruct->PLL.PLLR);\r\n#else\r\n        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,\r\n                             RCC_OscInitStruct->PLL.PLLM,\r\n                             RCC_OscInitStruct->PLL.PLLN,\r\n                             RCC_OscInitStruct->PLL.PLLP,\r\n                             RCC_OscInitStruct->PLL.PLLQ);\r\n#endif\r\n\r\n        /* Enable the main PLL. */\r\n        __HAL_RCC_PLL_ENABLE();\r\n\r\n        /* Get Start Tick*/\r\n        tickstart = HAL_GetTick();\r\n\r\n        /* Wait till PLL is ready */\r\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)\r\n        {\r\n          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r\n          {\r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n      }\r\n      else\r\n      {\r\n        /* Disable the main PLL. */\r\n        __HAL_RCC_PLL_DISABLE();\r\n\r\n        /* Get Start Tick*/\r\n        tickstart = HAL_GetTick();\r\n\r\n        /* Wait till PLL is ready */\r\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)\r\n        {\r\n          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r\n          {\r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n      }\r\n    }\r\n    else\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CPU, AHB and APB busses clocks according to the specified\r\n  *         parameters in the RCC_ClkInitStruct.\r\n  * @param  RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that\r\n  *         contains the configuration information for the RCC peripheral.\r\n  * @param  FLatency FLASH Latency, this parameter depend on device selected\r\n  *\r\n  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency\r\n  *         and updated by HAL_RCC_GetHCLKFreq() function called within this function\r\n  *\r\n  * @note   The HSI is used (enabled by hardware) as system clock source after\r\n  *         startup from Reset, wake-up from STOP and STANDBY mode, or in case\r\n  *         of failure of the HSE used directly or indirectly as system clock\r\n  *         (if the Clock Security System CSS is enabled).\r\n  *\r\n  * @note   A switch from one clock source to another occurs only if the target\r\n  *         clock source is ready (clock stable after startup delay or PLL locked).\r\n  *         If a clock source which is not yet ready is selected, the switch will\r\n  *         occur when the clock source will be ready.\r\n  *         You can use HAL_RCC_GetClockConfig() function to know which clock is\r\n  *         currently used as system clock source.\r\n  * @note   Depending on the device voltage range, the software has to set correctly\r\n  *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency\r\n  *         (for more details refer to section above \"Initialization/de-initialization functions\")\r\n  * @retval None\r\n  */\r\nHAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)\r\n{\r\n  uint32_t tickstart = 0;\r\n\r\n  /* Check Null pointer */\r\n  if(RCC_ClkInitStruct == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));\r\n  assert_param(IS_FLASH_LATENCY(FLatency));\r\n\r\n  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)\r\n     must be correctly programmed according to the frequency of the CPU clock\r\n     (HCLK) and the supply voltage of the device. */\r\n\r\n  /* Increasing the CPU frequency */\r\n  if(FLatency > __HAL_FLASH_GET_LATENCY())\r\n  {\r\n    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */\r\n    __HAL_FLASH_SET_LATENCY(FLatency);\r\n\r\n    /* Check that the new number of wait states is taken into account to access the Flash\r\n    memory by reading the FLASH_ACR register */\r\n    if(__HAL_FLASH_GET_LATENCY() != FLatency)\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n  }\r\n\r\n  /*-------------------------- HCLK Configuration --------------------------*/\r\n  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)\r\n  {\r\n    /* Set the highest APBx dividers in order to ensure that we do not go through\r\n       a non-spec phase whatever we decrease or increase HCLK. */\r\n    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)\r\n    {\r\n      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);\r\n    }\r\n\r\n    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)\r\n    {\r\n      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));\r\n    }\r\n\r\n    /* Set the new HCLK clock divider */\r\n    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));\r\n    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);\r\n  }\r\n\r\n  /*------------------------- SYSCLK Configuration ---------------------------*/\r\n  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)\r\n  {\r\n    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));\r\n\r\n    /* HSE is selected as System Clock Source */\r\n    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)\r\n    {\r\n      /* Check the HSE ready flag */\r\n      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)\r\n      {\r\n        return HAL_ERROR;\r\n      }\r\n    }\r\n    /* PLL is selected as System Clock Source */\r\n    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)\r\n    {\r\n      /* Check the PLL ready flag */\r\n      if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)\r\n      {\r\n        return HAL_ERROR;\r\n      }\r\n    }\r\n    /* HSI is selected as System Clock Source */\r\n    else\r\n    {\r\n      /* Check the HSI ready flag */\r\n      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)\r\n      {\r\n        return HAL_ERROR;\r\n      }\r\n    }\r\n\r\n    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);\r\n\r\n    /* Get Start Tick*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))\r\n    {\r\n      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n\r\n  /* Decreasing the number of wait states because of lower CPU frequency */\r\n  if(FLatency < __HAL_FLASH_GET_LATENCY())\r\n  {\r\n    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */\r\n    __HAL_FLASH_SET_LATENCY(FLatency);\r\n\r\n    /* Check that the new number of wait states is taken into account to access the Flash\r\n    memory by reading the FLASH_ACR register */\r\n    if(__HAL_FLASH_GET_LATENCY() != FLatency)\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n  }\r\n\r\n  /*-------------------------- PCLK1 Configuration ---------------------------*/\r\n  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)\r\n  {\r\n    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));\r\n    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);\r\n  }\r\n\r\n  /*-------------------------- PCLK2 Configuration ---------------------------*/\r\n  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)\r\n  {\r\n    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));\r\n    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));\r\n  }\r\n\r\n  /* Update the SystemCoreClock global variable */\r\n  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];\r\n\r\n  /* Configure the source of time base considering new system clocks settings*/\r\n  HAL_InitTick (TICK_INT_PRIORITY);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions\r\n  *  @brief   RCC clocks control functions\r\n  *\r\n  @verbatim\r\n  ===============================================================================\r\n                  ##### Peripheral Control functions #####\r\n  ===============================================================================\r\n    [..]\r\n    This subsection provides a set of functions allowing to control the RCC Clocks\r\n    frequencies.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).\r\n  * @note   PA8/PC9 should be configured in alternate function mode.\r\n  * @param  RCC_MCOx specifies the output direction for the clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).\r\n  *            @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).\r\n  * @param  RCC_MCOSource specifies the clock source to output.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source\r\n  *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source\r\n  *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source\r\n  *            @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source\r\n  *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source\r\n  *            @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source\r\n  *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source\r\n  *            @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source\r\n  * @param  RCC_MCODiv specifies the MCOx prescaler.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_MCODIV_1: no division applied to MCOx clock\r\n  *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock\r\n  *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock\r\n  *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock\r\n  *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock\r\n  * @retval None\r\n  */\r\nvoid HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)\r\n{\r\n  GPIO_InitTypeDef GPIO_InitStruct;\r\n  /* Check the parameters */\r\n  assert_param(IS_RCC_MCO(RCC_MCOx));\r\n  assert_param(IS_RCC_MCODIV(RCC_MCODiv));\r\n  /* RCC_MCO1 */\r\n  if(RCC_MCOx == RCC_MCO1)\r\n  {\r\n    assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));\r\n\r\n    /* MCO1 Clock Enable */\r\n    MCO1_CLK_ENABLE();\r\n\r\n    /* Configure the MCO1 pin in alternate function mode */\r\n    GPIO_InitStruct.Pin = MCO1_PIN;\r\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r\n    GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;\r\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\r\n    GPIO_InitStruct.Alternate = GPIO_AF0_MCO;\r\n    HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);\r\n\r\n    /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */\r\n    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));\r\n  }\r\n  else\r\n  {\r\n    assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));\r\n\r\n    /* MCO2 Clock Enable */\r\n    MCO2_CLK_ENABLE();\r\n\r\n    /* Configure the MCO2 pin in alternate function mode */\r\n    GPIO_InitStruct.Pin = MCO2_PIN;\r\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r\n    GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;\r\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\r\n    GPIO_InitStruct.Alternate = GPIO_AF0_MCO;\r\n    HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);\r\n\r\n    /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */\r\n    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3)));\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Enables the Clock Security System.\r\n  * @note   If a failure is detected on the HSE oscillator clock, this oscillator\r\n  *         is automatically disabled and an interrupt is generated to inform the\r\n  *         software about the failure (Clock Security System Interrupt, CSSI),\r\n  *         allowing the MCU to perform rescue operations. The CSSI is linked to\r\n  *         the Cortex-M7 NMI (Non-Maskable Interrupt) exception vector.\r\n  * @retval None\r\n  */\r\nvoid HAL_RCC_EnableCSS(void)\r\n{\r\n  SET_BIT(RCC->CR, RCC_CR_CSSON);\r\n}\r\n\r\n/**\r\n  * @brief  Disables the Clock Security System.\r\n  * @retval None\r\n  */\r\nvoid HAL_RCC_DisableCSS(void)\r\n{\r\n  CLEAR_BIT(RCC->CR, RCC_CR_CSSON);\r\n}\r\n\r\n/**\r\n  * @brief  Returns the SYSCLK frequency\r\n  *\r\n  * @note   The system frequency computed by this function is not the real\r\n  *         frequency in the chip. It is calculated based on the predefined\r\n  *         constant and the selected clock source:\r\n  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)\r\n  * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)\r\n  * @note     If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)\r\n  *           or HSI_VALUE(*) multiplied/divided by the PLL factors.\r\n  * @note     (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value\r\n  *               16 MHz) but the real value may vary depending on the variations\r\n  *               in voltage and temperature.\r\n  * @note     (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value\r\n  *                25 MHz), user has to ensure that HSE_VALUE is same as the real\r\n  *                frequency of the crystal used. Otherwise, this function may\r\n  *                have wrong result.\r\n  *\r\n  * @note   The result of this function could be not correct when using fractional\r\n  *         value for HSE crystal.\r\n  *\r\n  * @note   This function can be used by the user application to compute the\r\n  *         baudrate for the communication peripherals or configure other parameters.\r\n  *\r\n  * @note   Each time SYSCLK changes, this function must be called to update the\r\n  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.\r\n  *\r\n  *\r\n  * @retval SYSCLK frequency\r\n  */\r\nuint32_t HAL_RCC_GetSysClockFreq(void)\r\n{\r\n  uint32_t pllm = 0, pllvco = 0, pllp = 0;\r\n  uint32_t sysclockfreq = 0;\r\n\r\n  /* Get SYSCLK source -------------------------------------------------------*/\r\n  switch (RCC->CFGR & RCC_CFGR_SWS)\r\n  {\r\n    case RCC_SYSCLKSOURCE_STATUS_HSI:  /* HSI used as system clock source */\r\n    {\r\n      sysclockfreq = HSI_VALUE;\r\n       break;\r\n    }\r\n    case RCC_SYSCLKSOURCE_STATUS_HSE:  /* HSE used as system clock  source */\r\n    {\r\n      sysclockfreq = HSE_VALUE;\r\n      break;\r\n    }\r\n    case RCC_SYSCLKSOURCE_STATUS_PLLCLK:  /* PLL used as system clock  source */\r\n    {\r\n      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN\r\n      SYSCLK = PLL_VCO / PLLP */\r\n      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;\r\n      if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)\r\n      {\r\n        /* HSE used as PLL clock source */\r\n        pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);\r\n      }\r\n      else\r\n      {\r\n        /* HSI used as PLL clock source */\r\n        pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);\r\n      }\r\n      pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1 ) *2);\r\n\r\n      sysclockfreq = pllvco/pllp;\r\n      break;\r\n    }\r\n    default:\r\n    {\r\n      sysclockfreq = HSI_VALUE;\r\n      break;\r\n    }\r\n  }\r\n  return sysclockfreq;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the HCLK frequency\r\n  * @note   Each time HCLK changes, this function must be called to update the\r\n  *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.\r\n  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency.\r\n  * @retval HCLK frequency\r\n  */\r\nuint32_t HAL_RCC_GetHCLKFreq(void)\r\n{\r\n  return SystemCoreClock;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the PCLK1 frequency\r\n  * @note   Each time PCLK1 changes, this function must be called to update the\r\n  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.\r\n  * @retval PCLK1 frequency\r\n  */\r\nuint32_t HAL_RCC_GetPCLK1Freq(void)\r\n{\r\n  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/\r\n  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);\r\n}\r\n\r\n/**\r\n  * @brief  Returns the PCLK2 frequency\r\n  * @note   Each time PCLK2 changes, this function must be called to update the\r\n  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.\r\n  * @retval PCLK2 frequency\r\n  */\r\nuint32_t HAL_RCC_GetPCLK2Freq(void)\r\n{\r\n  /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/\r\n  return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);\r\n}\r\n\r\n/**\r\n  * @brief  Configures the RCC_OscInitStruct according to the internal\r\n  * RCC configuration registers.\r\n  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that\r\n  * will be configured.\r\n  * @retval None\r\n  */\r\nvoid HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)\r\n{\r\n  /* Set all possible values for the Oscillator type parameter ---------------*/\r\n  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;\r\n\r\n  /* Get the HSE configuration -----------------------------------------------*/\r\n  if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)\r\n  {\r\n    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;\r\n  }\r\n  else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)\r\n  {\r\n    RCC_OscInitStruct->HSEState = RCC_HSE_ON;\r\n  }\r\n  else\r\n  {\r\n    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;\r\n  }\r\n\r\n  /* Get the HSI configuration -----------------------------------------------*/\r\n  if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)\r\n  {\r\n    RCC_OscInitStruct->HSIState = RCC_HSI_ON;\r\n  }\r\n  else\r\n  {\r\n    RCC_OscInitStruct->HSIState = RCC_HSI_OFF;\r\n  }\r\n\r\n  RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);\r\n\r\n  /* Get the LSE configuration -----------------------------------------------*/\r\n  if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)\r\n  {\r\n    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;\r\n  }\r\n  else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)\r\n  {\r\n    RCC_OscInitStruct->LSEState = RCC_LSE_ON;\r\n  }\r\n  else\r\n  {\r\n    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;\r\n  }\r\n\r\n  /* Get the LSI configuration -----------------------------------------------*/\r\n  if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)\r\n  {\r\n    RCC_OscInitStruct->LSIState = RCC_LSI_ON;\r\n  }\r\n  else\r\n  {\r\n    RCC_OscInitStruct->LSIState = RCC_LSI_OFF;\r\n  }\r\n\r\n  /* Get the PLL configuration -----------------------------------------------*/\r\n  if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)\r\n  {\r\n    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;\r\n  }\r\n  else\r\n  {\r\n    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;\r\n  }\r\n  RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);\r\n  RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);\r\n  RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);\r\n  RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> RCC_PLLCFGR_PLLP_Pos);\r\n  RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos);\r\n#if defined (RCC_PLLCFGR_PLLR)\r\n  RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR));\r\n#endif\r\n}\r\n\r\n/**\r\n  * @brief  Configures the RCC_ClkInitStruct according to the internal\r\n  * RCC configuration registers.\r\n  * @param  RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that\r\n  * will be configured.\r\n  * @param  pFLatency Pointer on the Flash Latency.\r\n  * @retval None\r\n  */\r\nvoid HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)\r\n{\r\n  /* Set all possible values for the Clock type parameter --------------------*/\r\n  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;\r\n\r\n  /* Get the SYSCLK configuration --------------------------------------------*/\r\n  RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);\r\n\r\n  /* Get the HCLK configuration ----------------------------------------------*/\r\n  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);\r\n\r\n  /* Get the APB1 configuration ----------------------------------------------*/\r\n  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);\r\n\r\n  /* Get the APB2 configuration ----------------------------------------------*/\r\n  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);\r\n\r\n  /* Get the Flash Wait State (Latency) configuration ------------------------*/\r\n  *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);\r\n}\r\n\r\n/**\r\n  * @brief This function handles the RCC CSS interrupt request.\r\n  * @note This API should be called under the NMI_Handler().\r\n  * @retval None\r\n  */\r\nvoid HAL_RCC_NMI_IRQHandler(void)\r\n{\r\n  /* Check RCC CSSF flag  */\r\n  if(__HAL_RCC_GET_IT(RCC_IT_CSS))\r\n  {\r\n    /* RCC Clock Security System interrupt user callback */\r\n    HAL_RCC_CSSCallback();\r\n\r\n    /* Clear RCC CSS pending bit */\r\n    __HAL_RCC_CLEAR_IT(RCC_IT_CSS);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  RCC Clock Security System interrupt callback\r\n  * @retval None\r\n  */\r\n__weak void HAL_RCC_CSSCallback(void)\r\n{\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_RCC_CSSCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_RCC_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_rcc_ex.c\r\n  * @author  MCD Application Team\r\n  * @brief   Extension RCC HAL module driver.\r\n  *          This file provides firmware functions to manage the following\r\n  *          functionalities RCC extension peripheral:\r\n  *           + Extended Peripheral Control functions\r\n  *\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup RCCEx RCCEx\r\n  * @brief RCCEx HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_RCC_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @defgroup RCCEx_Private_Defines RCCEx Private Defines\r\n  * @{\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n/* Private macro -------------------------------------------------------------*/\r\n/** @defgroup RCCEx_Private_Macros RCCEx Private Macros\r\n * @{\r\n */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_Private_Macros RCCEx Private Macros\r\n * @{\r\n */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions\r\n *  @brief  Extended Peripheral Control functions\r\n *\r\n@verbatim\r\n ===============================================================================\r\n                ##### Extended Peripheral Control functions  #####\r\n ===============================================================================\r\n    [..]\r\n    This subsection provides a set of functions allowing to control the RCC Clocks\r\n    frequencies.\r\n    [..]\r\n    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to\r\n        select the RTC clock source; in this case the Backup domain will be reset in\r\n        order to modify the RTC Clock source, as consequence RTC registers (including\r\n        the backup registers) and RCC_BDCR register will be set to their reset values.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || \\\r\n    defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || \\\r\n    defined (STM32F750xx)\r\n/**\r\n  * @brief  Initializes the RCC extended peripherals clocks according to the specified\r\n  *         parameters in the RCC_PeriphCLKInitTypeDef.\r\n  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that\r\n  *         contains the configuration information for the Extended Peripherals\r\n  *         clocks(I2S, SAI, LTDC, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...).\r\n  *\r\n  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select\r\n  *         the RTC clock source; in this case the Backup domain will be reset in\r\n  *         order to modify the RTC Clock source, as consequence RTC registers (including\r\n  *         the backup registers) are set to their reset values.\r\n  *\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)\r\n{\r\n  uint32_t tickstart = 0;\r\n  uint32_t tmpreg0 = 0;\r\n  uint32_t tmpreg1 = 0;\r\n  uint32_t plli2sused = 0;\r\n  uint32_t pllsaiused = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));\r\n\r\n  /*----------------------------------- I2S configuration ----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));\r\n\r\n    /* Configure I2S Clock source */\r\n    __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);\r\n\r\n    /* Enable the PLLI2S when it's used as clock source for I2S */\r\n    if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)\r\n    {\r\n      plli2sused = 1;\r\n    }\r\n  }\r\n\r\n  /*------------------------------------ SAI1 configuration --------------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));\r\n\r\n    /* Configure SAI1 Clock source */\r\n    __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);\r\n    /* Enable the PLLI2S when it's used as clock source for SAI */\r\n    if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)\r\n    {\r\n      plli2sused = 1;\r\n    }\r\n    /* Enable the PLLSAI when it's used as clock source for SAI */\r\n    if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)\r\n    {\r\n      pllsaiused = 1;\r\n    }\r\n  }\r\n\r\n  /*------------------------------------ SAI2 configuration --------------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));\r\n\r\n    /* Configure SAI2 Clock source */\r\n    __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);\r\n\r\n    /* Enable the PLLI2S when it's used as clock source for SAI */\r\n    if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)\r\n    {\r\n      plli2sused = 1;\r\n    }\r\n    /* Enable the PLLSAI when it's used as clock source for SAI */\r\n    if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)\r\n    {\r\n      pllsaiused = 1;\r\n    }\r\n  }\r\n\r\n  /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)\r\n  {\r\n      plli2sused = 1;\r\n  }\r\n\r\n  /*------------------------------------ RTC configuration --------------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))\r\n  {\r\n    /* Check for RTC Parameters used to output RTCCLK */\r\n    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));\r\n\r\n    /* Enable Power Clock*/\r\n    __HAL_RCC_PWR_CLK_ENABLE();\r\n\r\n    /* Enable write access to Backup domain */\r\n    PWR->CR1 |= PWR_CR1_DBP;\r\n\r\n    /* Get Start Tick*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    /* Wait for Backup domain Write protection disable */\r\n    while((PWR->CR1 & PWR_CR1_DBP) == RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n\r\n    /* Reset the Backup domain only if the RTC Clock source selection is modified */\r\n    tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);\r\n\r\n    if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))\r\n    {\r\n      /* Store the content of BDCR register before the reset of Backup Domain */\r\n      tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));\r\n\r\n      /* RTC Clock selection can be changed only if the Backup Domain is reset */\r\n      __HAL_RCC_BACKUPRESET_FORCE();\r\n      __HAL_RCC_BACKUPRESET_RELEASE();\r\n\r\n      /* Restore the Content of BDCR register */\r\n      RCC->BDCR = tmpreg0;\r\n\r\n      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */\r\n      if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))\r\n      {\r\n        /* Get Start Tick*/\r\n        tickstart = HAL_GetTick();\r\n\r\n        /* Wait till LSE is ready */\r\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)\r\n        {\r\n          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\r\n          {\r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n      }\r\n    }\r\n    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);\r\n  }\r\n\r\n  /*------------------------------------ TIM configuration --------------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));\r\n\r\n    /* Configure Timer Prescaler */\r\n    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);\r\n  }\r\n\r\n  /*-------------------------------------- I2C1 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));\r\n\r\n    /* Configure the I2C1 clock source */\r\n    __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);\r\n  }\r\n\r\n  /*-------------------------------------- I2C2 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));\r\n\r\n    /* Configure the I2C2 clock source */\r\n    __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);\r\n  }\r\n\r\n  /*-------------------------------------- I2C3 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));\r\n\r\n    /* Configure the I2C3 clock source */\r\n    __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);\r\n  }\r\n\r\n  /*-------------------------------------- I2C4 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));\r\n\r\n    /* Configure the I2C4 clock source */\r\n    __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);\r\n  }\r\n\r\n  /*-------------------------------------- USART1 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));\r\n\r\n    /* Configure the USART1 clock source */\r\n    __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);\r\n  }\r\n\r\n  /*-------------------------------------- USART2 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));\r\n\r\n    /* Configure the USART2 clock source */\r\n    __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);\r\n  }\r\n\r\n  /*-------------------------------------- USART3 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));\r\n\r\n    /* Configure the USART3 clock source */\r\n    __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);\r\n  }\r\n\r\n  /*-------------------------------------- UART4 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));\r\n\r\n    /* Configure the UART4 clock source */\r\n    __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);\r\n  }\r\n\r\n  /*-------------------------------------- UART5 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));\r\n\r\n    /* Configure the UART5 clock source */\r\n    __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);\r\n  }\r\n\r\n  /*-------------------------------------- USART6 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));\r\n\r\n    /* Configure the USART6 clock source */\r\n    __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);\r\n  }\r\n\r\n  /*-------------------------------------- UART7 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));\r\n\r\n    /* Configure the UART7 clock source */\r\n    __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);\r\n  }\r\n\r\n  /*-------------------------------------- UART8 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));\r\n\r\n    /* Configure the UART8 clock source */\r\n    __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);\r\n  }\r\n\r\n  /*--------------------------------------- CEC Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));\r\n\r\n    /* Configure the CEC clock source */\r\n    __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);\r\n  }\r\n\r\n  /*-------------------------------------- CK48 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));\r\n\r\n    /* Configure the CLK48 source */\r\n    __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);\r\n\r\n    /* Enable the PLLSAI when it's used as clock source for CK48 */\r\n    if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)\r\n    {\r\n      pllsaiused = 1;\r\n    }\r\n  }\r\n\r\n  /*-------------------------------------- LTDC Configuration -----------------------------------*/\r\n#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)\r\n  {\r\n    pllsaiused = 1;\r\n  }\r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n\r\n  /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));\r\n\r\n    /* Configure the LTPIM1 clock source */\r\n    __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);\r\n   }\r\n\r\n  /*------------------------------------- SDMMC1 Configuration ------------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));\r\n\r\n    /* Configure the SDMMC1 clock source */\r\n    __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);\r\n  }\r\n\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n  /*------------------------------------- SDMMC2 Configuration ------------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection));\r\n\r\n    /* Configure the SDMMC2 clock source */\r\n    __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection);\r\n  }\r\n\r\n  /*------------------------------------- DFSDM1 Configuration -------------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));\r\n\r\n    /* Configure the DFSDM1 interface clock source */\r\n    __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);\r\n  }\r\n\r\n  /*------------------------------------- DFSDM AUDIO Configuration -------------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));\r\n\r\n    /* Configure the DFSDM interface clock source */\r\n    __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);\r\n  }\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n  /*-------------------------------------- PLLI2S Configuration ---------------------------------*/\r\n  /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */\r\n  if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))\r\n  {\r\n    /* Disable the PLLI2S */\r\n    __HAL_RCC_PLLI2S_DISABLE();\r\n\r\n    /* Get Start Tick*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    /* Wait till PLLI2S is disabled */\r\n    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)\r\n      {\r\n        /* return in case of Timeout detected */\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n\r\n    /* check for common PLLI2S Parameters */\r\n    assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));\r\n\r\n    /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/\r\n    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))\r\n    {\r\n      /* check for Parameters */\r\n      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));\r\n\r\n      /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */\r\n      tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);\r\n      tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);\r\n      /* Configure the PLLI2S division factors */\r\n      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */\r\n      /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */\r\n      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR);\r\n    }\r\n\r\n    /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/\r\n    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||\r\n       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))\r\n    {\r\n      /* Check for PLLI2S Parameters */\r\n      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));\r\n      /* Check for PLLI2S/DIVQ parameters */\r\n      assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));\r\n\r\n      /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */\r\n      tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);\r\n      tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);\r\n      /* Configure the PLLI2S division factors */\r\n      /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */\r\n      /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */\r\n      /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */\r\n      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1);\r\n\r\n      /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */\r\n      __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);\r\n    }\r\n\r\n    /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/\r\n    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)\r\n    {\r\n      /* check for Parameters */\r\n      assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));\r\n\r\n     /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */\r\n      tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);\r\n      tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);\r\n      /* Configure the PLLI2S division factors */\r\n      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */\r\n      /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */\r\n      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1);\r\n    }\r\n\r\n    /*----------------- In Case of PLLI2S is just selected  -----------------*/\r\n    if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)\r\n    {\r\n      /* Check for Parameters */\r\n      assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));\r\n      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));\r\n      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));\r\n\r\n      /* Configure the PLLI2S division factors */\r\n      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */\r\n      /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */\r\n      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);\r\n    }\r\n\r\n    /* Enable the PLLI2S */\r\n    __HAL_RCC_PLLI2S_ENABLE();\r\n\r\n    /* Get Start Tick*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    /* Wait till PLLI2S is ready */\r\n    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)\r\n      {\r\n        /* return in case of Timeout detected */\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n\r\n  /*-------------------------------------- PLLSAI Configuration ---------------------------------*/\r\n  /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */\r\n  if(pllsaiused == 1)\r\n  {\r\n    /* Disable PLLSAI Clock */\r\n    __HAL_RCC_PLLSAI_DISABLE();\r\n\r\n    /* Get Start Tick*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    /* Wait till PLLSAI is disabled */\r\n    while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)\r\n      {\r\n        /* return in case of Timeout detected */\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n\r\n    /* Check the PLLSAI division factors */\r\n    assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));\r\n\r\n    /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/\r\n    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\\\r\n       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))\r\n    {\r\n      /* check for PLLSAIQ Parameter */\r\n      assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));\r\n      /* check for PLLSAI/DIVQ Parameter */\r\n      assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));\r\n\r\n      /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */\r\n      tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);\r\n      tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);\r\n      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */\r\n      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */\r\n      /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */\r\n      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);\r\n\r\n      /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */\r\n      __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);\r\n    }\r\n\r\n    /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/\r\n    /* In Case of PLLI2S is selected as source clock for CK48 */\r\n    if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))\r\n    {\r\n      /* check for Parameters */\r\n      assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));\r\n      /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */\r\n      tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);\r\n      tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);\r\n\r\n      /* Configure the PLLSAI division factors */\r\n      /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */\r\n      /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */\r\n      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1);\r\n    }\r\n\r\n#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)\r\n    /*---------------------------- LTDC configuration -------------------------------*/\r\n    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))\r\n    {\r\n      assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));\r\n      assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));\r\n\r\n      /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */\r\n      tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);\r\n      tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);\r\n\r\n      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */\r\n      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */\r\n      /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */\r\n      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR);\r\n\r\n      /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */\r\n      __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);\r\n    }\r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx  */\r\n\r\n    /* Enable PLLSAI Clock */\r\n    __HAL_RCC_PLLSAI_ENABLE();\r\n\r\n    /* Get Start Tick*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    /* Wait till PLLSAI is ready */\r\n    while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)\r\n      {\r\n        /* return in case of Timeout detected */\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Get the RCC_PeriphCLKInitTypeDef according to the internal\r\n  *         RCC configuration registers.\r\n  * @param  PeriphClkInit pointer to the configured RCC_PeriphCLKInitTypeDef structure\r\n  * @retval None\r\n  */\r\nvoid HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)\r\n{\r\n  uint32_t tempreg = 0;\r\n\r\n  /* Set all possible values for the extended clock type parameter------------*/\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S      | RCC_PERIPHCLK_LPTIM1   |\\\r\n                                        RCC_PERIPHCLK_SAI1     | RCC_PERIPHCLK_SAI2     |\\\r\n                                        RCC_PERIPHCLK_TIM      | RCC_PERIPHCLK_RTC      |\\\r\n                                        RCC_PERIPHCLK_CEC      | RCC_PERIPHCLK_I2C4     |\\\r\n                                        RCC_PERIPHCLK_I2C1     | RCC_PERIPHCLK_I2C2     |\\\r\n                                        RCC_PERIPHCLK_I2C3     | RCC_PERIPHCLK_USART1   |\\\r\n                                        RCC_PERIPHCLK_USART2   | RCC_PERIPHCLK_USART3   |\\\r\n                                        RCC_PERIPHCLK_UART4    | RCC_PERIPHCLK_UART5    |\\\r\n                                        RCC_PERIPHCLK_USART6   | RCC_PERIPHCLK_UART7    |\\\r\n                                        RCC_PERIPHCLK_UART8    | RCC_PERIPHCLK_SDMMC1   |\\\r\n                                        RCC_PERIPHCLK_CLK48    | RCC_PERIPHCLK_SDMMC2   |\\\r\n                                        RCC_PERIPHCLK_DFSDM1   | RCC_PERIPHCLK_DFSDM1_AUDIO;\r\n#else\r\n  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S      | RCC_PERIPHCLK_LPTIM1   |\\\r\n                                        RCC_PERIPHCLK_SAI1     | RCC_PERIPHCLK_SAI2     |\\\r\n                                        RCC_PERIPHCLK_TIM      | RCC_PERIPHCLK_RTC      |\\\r\n                                        RCC_PERIPHCLK_CEC      | RCC_PERIPHCLK_I2C4     |\\\r\n                                        RCC_PERIPHCLK_I2C1     | RCC_PERIPHCLK_I2C2     |\\\r\n                                        RCC_PERIPHCLK_I2C3     | RCC_PERIPHCLK_USART1   |\\\r\n                                        RCC_PERIPHCLK_USART2   | RCC_PERIPHCLK_USART3   |\\\r\n                                        RCC_PERIPHCLK_UART4    | RCC_PERIPHCLK_UART5    |\\\r\n                                        RCC_PERIPHCLK_USART6   | RCC_PERIPHCLK_UART7    |\\\r\n                                        RCC_PERIPHCLK_UART8    | RCC_PERIPHCLK_SDMMC1   |\\\r\n                                        RCC_PERIPHCLK_CLK48;\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n  /* Get the PLLI2S Clock configuration -----------------------------------------------*/\r\n  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);\r\n  PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);\r\n  PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);\r\n  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);\r\n\r\n  /* Get the PLLSAI Clock configuration -----------------------------------------------*/\r\n  PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);\r\n  PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);\r\n  PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);\r\n  PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);\r\n\r\n  /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/\r\n  PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> RCC_DCKCFGR1_PLLI2SDIVQ_Pos);\r\n  PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> RCC_DCKCFGR1_PLLSAIDIVQ_Pos);\r\n  PeriphClkInit->PLLSAIDivR = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVR) >> RCC_DCKCFGR1_PLLSAIDIVR_Pos);\r\n\r\n  /* Get the SAI1 clock configuration ----------------------------------------------*/\r\n  PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();\r\n\r\n  /* Get the SAI2 clock configuration ----------------------------------------------*/\r\n  PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();\r\n\r\n  /* Get the I2S clock configuration ------------------------------------------*/\r\n  PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE();\r\n\r\n  /* Get the I2C1 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();\r\n\r\n  /* Get the I2C2 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();\r\n\r\n  /* Get the I2C3 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();\r\n\r\n  /* Get the I2C4 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE();\r\n\r\n  /* Get the USART1 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();\r\n\r\n  /* Get the USART2 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();\r\n\r\n  /* Get the USART3 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();\r\n\r\n  /* Get the UART4 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();\r\n\r\n  /* Get the UART5 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();\r\n\r\n  /* Get the USART6 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE();\r\n\r\n  /* Get the UART7 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE();\r\n\r\n  /* Get the UART8 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE();\r\n\r\n  /* Get the LPTIM1 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();\r\n\r\n  /* Get the CEC clock configuration -----------------------------------------------*/\r\n  PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();\r\n\r\n  /* Get the CK48 clock configuration -----------------------------------------------*/\r\n  PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();\r\n\r\n  /* Get the SDMMC1 clock configuration -----------------------------------------------*/\r\n  PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE();\r\n\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n  /* Get the SDMMC2 clock configuration -----------------------------------------------*/\r\n  PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE();\r\n\r\n  /* Get the DFSDM clock configuration -----------------------------------------------*/\r\n  PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE();\r\n\r\n  /* Get the DFSDM AUDIO clock configuration -----------------------------------------------*/\r\n  PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE();\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n  /* Get the RTC Clock configuration -----------------------------------------------*/\r\n  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);\r\n  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));\r\n\r\n  /* Get the TIM Prescaler configuration --------------------------------------------*/\r\n  if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET)\r\n  {\r\n    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;\r\n  }\r\n  else\r\n  {\r\n    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;\r\n  }\r\n}\r\n#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */\r\n\r\n#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)\r\n/**\r\n  * @brief  Initializes the RCC extended peripherals clocks according to the specified\r\n  *         parameters in the RCC_PeriphCLKInitTypeDef.\r\n  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that\r\n  *         contains the configuration information for the Extended Peripherals\r\n  *         clocks(I2S, SAI, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...).\r\n  *\r\n  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select\r\n  *         the RTC clock source; in this case the Backup domain will be reset in\r\n  *         order to modify the RTC Clock source, as consequence RTC registers (including\r\n  *         the backup registers) are set to their reset values.\r\n  *\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)\r\n{\r\n  uint32_t tickstart = 0;\r\n  uint32_t tmpreg0 = 0;\r\n  uint32_t plli2sused = 0;\r\n  uint32_t pllsaiused = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));\r\n\r\n  /*----------------------------------- I2S configuration ----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));\r\n\r\n    /* Configure I2S Clock source */\r\n    __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);\r\n\r\n    /* Enable the PLLI2S when it's used as clock source for I2S */\r\n    if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)\r\n    {\r\n      plli2sused = 1;\r\n    }\r\n  }\r\n\r\n  /*------------------------------------ SAI1 configuration --------------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));\r\n\r\n    /* Configure SAI1 Clock source */\r\n    __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);\r\n    /* Enable the PLLI2S when it's used as clock source for SAI */\r\n    if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)\r\n    {\r\n      plli2sused = 1;\r\n    }\r\n    /* Enable the PLLSAI when it's used as clock source for SAI */\r\n    if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)\r\n    {\r\n      pllsaiused = 1;\r\n    }\r\n  }\r\n\r\n  /*------------------------------------ SAI2 configuration --------------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));\r\n\r\n    /* Configure SAI2 Clock source */\r\n    __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);\r\n\r\n    /* Enable the PLLI2S when it's used as clock source for SAI */\r\n    if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)\r\n    {\r\n      plli2sused = 1;\r\n    }\r\n    /* Enable the PLLSAI when it's used as clock source for SAI */\r\n    if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)\r\n    {\r\n      pllsaiused = 1;\r\n    }\r\n  }\r\n\r\n  /*------------------------------------ RTC configuration --------------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))\r\n  {\r\n    /* Check for RTC Parameters used to output RTCCLK */\r\n    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));\r\n\r\n    /* Enable Power Clock*/\r\n    __HAL_RCC_PWR_CLK_ENABLE();\r\n\r\n    /* Enable write access to Backup domain */\r\n    PWR->CR1 |= PWR_CR1_DBP;\r\n\r\n    /* Get Start Tick*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    /* Wait for Backup domain Write protection disable */\r\n    while((PWR->CR1 & PWR_CR1_DBP) == RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n\r\n    /* Reset the Backup domain only if the RTC Clock source selection is modified */\r\n    tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);\r\n\r\n    if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))\r\n    {\r\n      /* Store the content of BDCR register before the reset of Backup Domain */\r\n      tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));\r\n\r\n      /* RTC Clock selection can be changed only if the Backup Domain is reset */\r\n      __HAL_RCC_BACKUPRESET_FORCE();\r\n      __HAL_RCC_BACKUPRESET_RELEASE();\r\n\r\n      /* Restore the Content of BDCR register */\r\n      RCC->BDCR = tmpreg0;\r\n\r\n      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */\r\n      if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))\r\n      {\r\n        /* Get Start Tick*/\r\n        tickstart = HAL_GetTick();\r\n\r\n        /* Wait till LSE is ready */\r\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)\r\n        {\r\n          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\r\n          {\r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n      }\r\n    }\r\n    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);\r\n  }\r\n\r\n  /*------------------------------------ TIM configuration --------------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));\r\n\r\n    /* Configure Timer Prescaler */\r\n    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);\r\n  }\r\n\r\n  /*-------------------------------------- I2C1 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));\r\n\r\n    /* Configure the I2C1 clock source */\r\n    __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);\r\n  }\r\n\r\n  /*-------------------------------------- I2C2 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));\r\n\r\n    /* Configure the I2C2 clock source */\r\n    __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);\r\n  }\r\n\r\n  /*-------------------------------------- I2C3 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));\r\n\r\n    /* Configure the I2C3 clock source */\r\n    __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);\r\n  }\r\n\r\n  /*-------------------------------------- USART1 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));\r\n\r\n    /* Configure the USART1 clock source */\r\n    __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);\r\n  }\r\n\r\n  /*-------------------------------------- USART2 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));\r\n\r\n    /* Configure the USART2 clock source */\r\n    __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);\r\n  }\r\n\r\n  /*-------------------------------------- USART3 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));\r\n\r\n    /* Configure the USART3 clock source */\r\n    __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);\r\n  }\r\n\r\n  /*-------------------------------------- UART4 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));\r\n\r\n    /* Configure the UART4 clock source */\r\n    __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);\r\n  }\r\n\r\n  /*-------------------------------------- UART5 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));\r\n\r\n    /* Configure the UART5 clock source */\r\n    __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);\r\n  }\r\n\r\n  /*-------------------------------------- USART6 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));\r\n\r\n    /* Configure the USART6 clock source */\r\n    __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);\r\n  }\r\n\r\n  /*-------------------------------------- UART7 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));\r\n\r\n    /* Configure the UART7 clock source */\r\n    __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);\r\n  }\r\n\r\n  /*-------------------------------------- UART8 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));\r\n\r\n    /* Configure the UART8 clock source */\r\n    __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);\r\n  }\r\n\r\n  /*-------------------------------------- CK48 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));\r\n\r\n    /* Configure the CLK48 source */\r\n    __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);\r\n\r\n    /* Enable the PLLSAI when it's used as clock source for CK48 */\r\n    if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)\r\n    {\r\n      pllsaiused = 1;\r\n    }\r\n  }\r\n\r\n  /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));\r\n\r\n    /* Configure the LTPIM1 clock source */\r\n    __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);\r\n   }\r\n\r\n  /*------------------------------------- SDMMC1 Configuration ------------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));\r\n\r\n    /* Configure the SDMMC1 clock source */\r\n    __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);\r\n  }\r\n\r\n  /*------------------------------------- SDMMC2 Configuration ------------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection));\r\n\r\n    /* Configure the SDMMC2 clock source */\r\n    __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection);\r\n  }\r\n\r\n  /*-------------------------------------- PLLI2S Configuration ---------------------------------*/\r\n  /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2 or I2S */\r\n  if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))\r\n  {\r\n    /* Disable the PLLI2S */\r\n    __HAL_RCC_PLLI2S_DISABLE();\r\n\r\n    /* Get Start Tick*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    /* Wait till PLLI2S is disabled */\r\n    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)\r\n      {\r\n        /* return in case of Timeout detected */\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n\r\n    /* check for common PLLI2S Parameters */\r\n    assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));\r\n\r\n    /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/\r\n    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))\r\n    {\r\n      /* check for Parameters */\r\n      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));\r\n\r\n      /* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */\r\n      tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);\r\n      /* Configure the PLLI2S division factors */\r\n      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */\r\n      /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */\r\n      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, PeriphClkInit->PLLI2S.PLLI2SR);\r\n    }\r\n\r\n    /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/\r\n    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||\r\n       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))\r\n    {\r\n      /* Check for PLLI2S Parameters */\r\n      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));\r\n      /* Check for PLLI2S/DIVQ parameters */\r\n      assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));\r\n\r\n      /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */\r\n      tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);\r\n      /* Configure the PLLI2S division factors */\r\n      /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */\r\n      /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */\r\n      /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */\r\n      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg0);\r\n\r\n      /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */\r\n      __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);\r\n    }\r\n\r\n    /*----------------- In Case of PLLI2S is just selected  -----------------*/\r\n    if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)\r\n    {\r\n      /* Check for Parameters */\r\n      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));\r\n      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));\r\n\r\n      /* Configure the PLLI2S division factors */\r\n      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */\r\n      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);\r\n    }\r\n\r\n    /* Enable the PLLI2S */\r\n    __HAL_RCC_PLLI2S_ENABLE();\r\n\r\n    /* Get Start Tick*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    /* Wait till PLLI2S is ready */\r\n    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)\r\n      {\r\n        /* return in case of Timeout detected */\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n\r\n  /*-------------------------------------- PLLSAI Configuration ---------------------------------*/\r\n  /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */\r\n  if(pllsaiused == 1)\r\n  {\r\n    /* Disable PLLSAI Clock */\r\n    __HAL_RCC_PLLSAI_DISABLE();\r\n\r\n    /* Get Start Tick*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    /* Wait till PLLSAI is disabled */\r\n    while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)\r\n      {\r\n        /* return in case of Timeout detected */\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n\r\n    /* Check the PLLSAI division factors */\r\n    assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));\r\n\r\n    /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/\r\n    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\\\r\n       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))\r\n    {\r\n      /* check for PLLSAIQ Parameter */\r\n      assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));\r\n      /* check for PLLSAI/DIVQ Parameter */\r\n      assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));\r\n\r\n      /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */\r\n      tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);\r\n      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */\r\n      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */\r\n      /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */\r\n      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ);\r\n\r\n      /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */\r\n      __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);\r\n    }\r\n\r\n    /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/\r\n    /* In Case of PLLI2S is selected as source clock for CK48 */\r\n    if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))\r\n    {\r\n      /* check for Parameters */\r\n      assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));\r\n      /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */\r\n      tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);\r\n\r\n      /* Configure the PLLSAI division factors */\r\n      /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */\r\n      /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */\r\n      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0);\r\n    }\r\n\r\n    /* Enable PLLSAI Clock */\r\n    __HAL_RCC_PLLSAI_ENABLE();\r\n\r\n    /* Get Start Tick*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    /* Wait till PLLSAI is ready */\r\n    while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)\r\n      {\r\n        /* return in case of Timeout detected */\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Get the RCC_PeriphCLKInitTypeDef according to the internal\r\n  *         RCC configuration registers.\r\n  * @param  PeriphClkInit pointer to the configured RCC_PeriphCLKInitTypeDef structure\r\n  * @retval None\r\n  */\r\nvoid HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)\r\n{\r\n  uint32_t tempreg = 0;\r\n\r\n  /* Set all possible values for the extended clock type parameter------------*/\r\n  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S      | RCC_PERIPHCLK_LPTIM1   |\\\r\n                                        RCC_PERIPHCLK_SAI1     | RCC_PERIPHCLK_SAI2     |\\\r\n                                        RCC_PERIPHCLK_TIM      | RCC_PERIPHCLK_RTC      |\\\r\n                                        RCC_PERIPHCLK_I2C1     | RCC_PERIPHCLK_I2C2     |\\\r\n                                        RCC_PERIPHCLK_I2C3     | RCC_PERIPHCLK_USART1   |\\\r\n                                        RCC_PERIPHCLK_USART2   | RCC_PERIPHCLK_USART3   |\\\r\n                                        RCC_PERIPHCLK_UART4    | RCC_PERIPHCLK_UART5    |\\\r\n                                        RCC_PERIPHCLK_USART6   | RCC_PERIPHCLK_UART7    |\\\r\n                                        RCC_PERIPHCLK_UART8    | RCC_PERIPHCLK_SDMMC1   |\\\r\n                                        RCC_PERIPHCLK_CLK48    | RCC_PERIPHCLK_SDMMC2;\r\n\r\n  /* Get the PLLI2S Clock configuration -----------------------------------------------*/\r\n  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);\r\n  PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);\r\n  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);\r\n\r\n  /* Get the PLLSAI Clock configuration -----------------------------------------------*/\r\n  PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);\r\n  PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);\r\n  PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);\r\n\r\n  /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/\r\n  PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> RCC_DCKCFGR1_PLLI2SDIVQ_Pos);\r\n  PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> RCC_DCKCFGR1_PLLSAIDIVQ_Pos);\r\n\r\n  /* Get the SAI1 clock configuration ----------------------------------------------*/\r\n  PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();\r\n\r\n  /* Get the SAI2 clock configuration ----------------------------------------------*/\r\n  PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();\r\n\r\n  /* Get the I2S clock configuration ------------------------------------------*/\r\n  PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE();\r\n\r\n  /* Get the I2C1 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();\r\n\r\n  /* Get the I2C2 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();\r\n\r\n  /* Get the I2C3 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();\r\n\r\n  /* Get the USART1 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();\r\n\r\n  /* Get the USART2 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();\r\n\r\n  /* Get the USART3 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();\r\n\r\n  /* Get the UART4 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();\r\n\r\n  /* Get the UART5 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();\r\n\r\n  /* Get the USART6 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE();\r\n\r\n  /* Get the UART7 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE();\r\n\r\n  /* Get the UART8 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE();\r\n\r\n  /* Get the LPTIM1 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();\r\n\r\n  /* Get the CK48 clock configuration -----------------------------------------------*/\r\n  PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();\r\n\r\n  /* Get the SDMMC1 clock configuration -----------------------------------------------*/\r\n  PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE();\r\n\r\n  /* Get the SDMMC2 clock configuration -----------------------------------------------*/\r\n  PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE();\r\n\r\n  /* Get the RTC Clock configuration -----------------------------------------------*/\r\n  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);\r\n  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));\r\n\r\n  /* Get the TIM Prescaler configuration --------------------------------------------*/\r\n  if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET)\r\n  {\r\n    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;\r\n  }\r\n  else\r\n  {\r\n    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;\r\n  }\r\n}\r\n#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */\r\n\r\n/**\r\n  * @brief  Return the peripheral clock frequency for a given peripheral(SAI..)\r\n  * @note   Return 0 if peripheral clock identifier not managed by this API\r\n  * @param  PeriphClk Peripheral clock identifier\r\n  *         This parameter can be one of the following values:\r\n  *            @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock\r\n  *            @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock\r\n  * @retval Frequency in KHz\r\n  */\r\nuint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)\r\n{\r\n  uint32_t tmpreg = 0;\r\n  /* This variable is used to store the SAI clock frequency (value in Hz) */\r\n  uint32_t frequency = 0;\r\n  /* This variable is used to store the VCO Input (value in Hz) */\r\n  uint32_t vcoinput = 0;\r\n  /* This variable is used to store the SAI clock source */\r\n  uint32_t saiclocksource = 0;\r\n\r\n  if (PeriphClk == RCC_PERIPHCLK_SAI1)\r\n  {\r\n    saiclocksource = RCC->DCKCFGR1;\r\n    saiclocksource &= RCC_DCKCFGR1_SAI1SEL;\r\n    switch (saiclocksource)\r\n    {\r\n    case 0: /* PLLSAI is the clock source for SAI1 */\r\n      {\r\n        /* Configure the PLLSAI division factor */\r\n        /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */\r\n        if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)\r\n        {\r\n          /* In Case the PLL Source is HSI (Internal Clock) */\r\n          vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\r\n        }\r\n        else\r\n        {\r\n          /* In Case the PLL Source is HSE (External Clock) */\r\n          vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));\r\n        }\r\n        /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */\r\n        /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */\r\n        tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;\r\n        frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);\r\n\r\n        /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */\r\n        tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1);\r\n        frequency = frequency/(tmpreg);\r\n        break;\r\n      }\r\n    case RCC_DCKCFGR1_SAI1SEL_0: /* PLLI2S is the clock source for SAI1 */\r\n      {\r\n        /* Configure the PLLI2S division factor */\r\n        /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */\r\n        if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)\r\n        {\r\n          /* In Case the PLL Source is HSI (Internal Clock) */\r\n          vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\r\n        }\r\n        else\r\n        {\r\n          /* In Case the PLL Source is HSE (External Clock) */\r\n          vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));\r\n        }\r\n\r\n        /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */\r\n        /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */\r\n        tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;\r\n        frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);\r\n\r\n        /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */\r\n        tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1);\r\n        frequency = frequency/(tmpreg);\r\n        break;\r\n      }\r\n    case RCC_DCKCFGR1_SAI1SEL_1: /* External clock is the clock source for SAI1 */\r\n      {\r\n        frequency = EXTERNAL_CLOCK_VALUE;\r\n        break;\r\n      }\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n    case RCC_DCKCFGR1_SAI1SEL: /* HSI or HSE is the clock source for SAI*/\r\n      {\r\n        if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)\r\n        {\r\n          /* In Case the main PLL Source is HSI */\r\n          frequency = HSI_VALUE;\r\n        }\r\n        else\r\n        {\r\n          /* In Case the main PLL Source is HSE */\r\n          frequency = HSE_VALUE;\r\n        }\r\n        break;\r\n      }\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n    default :\r\n      {\r\n        break;\r\n      }\r\n    }\r\n  }\r\n\r\n  if (PeriphClk == RCC_PERIPHCLK_SAI2)\r\n  {\r\n    saiclocksource = RCC->DCKCFGR1;\r\n    saiclocksource &= RCC_DCKCFGR1_SAI2SEL;\r\n    switch (saiclocksource)\r\n    {\r\n    case 0: /* PLLSAI is the clock source for SAI*/\r\n      {\r\n        /* Configure the PLLSAI division factor */\r\n        /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */\r\n        if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)\r\n        {\r\n          /* In Case the PLL Source is HSI (Internal Clock) */\r\n          vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\r\n        }\r\n        else\r\n        {\r\n          /* In Case the PLL Source is HSE (External Clock) */\r\n          vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));\r\n        }\r\n        /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */\r\n        /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */\r\n        tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;\r\n        frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);\r\n\r\n        /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */\r\n        tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1);\r\n        frequency = frequency/(tmpreg);\r\n        break;\r\n      }\r\n    case RCC_DCKCFGR1_SAI2SEL_0: /* PLLI2S is the clock source for SAI2 */\r\n      {\r\n        /* Configure the PLLI2S division factor */\r\n        /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */\r\n        if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)\r\n        {\r\n          /* In Case the PLL Source is HSI (Internal Clock) */\r\n          vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\r\n        }\r\n        else\r\n        {\r\n          /* In Case the PLL Source is HSE (External Clock) */\r\n          vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));\r\n        }\r\n\r\n        /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */\r\n        /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */\r\n        tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;\r\n        frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);\r\n\r\n        /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */\r\n        tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1);\r\n        frequency = frequency/(tmpreg);\r\n        break;\r\n      }\r\n    case RCC_DCKCFGR1_SAI2SEL_1: /* External clock is the clock source for SAI2 */\r\n      {\r\n        frequency = EXTERNAL_CLOCK_VALUE;\r\n        break;\r\n      }\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n    case RCC_DCKCFGR1_SAI2SEL: /* HSI or HSE is the clock source for SAI2 */\r\n      {\r\n        if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)\r\n        {\r\n          /* In Case the main PLL Source is HSI */\r\n          frequency = HSI_VALUE;\r\n        }\r\n        else\r\n        {\r\n          /* In Case the main PLL Source is HSE */\r\n          frequency = HSE_VALUE;\r\n        }\r\n        break;\r\n      }\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n    default :\r\n      {\r\n        break;\r\n      }\r\n    }\r\n  }\r\n\r\n  return frequency;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions\r\n *  @brief  Extended Clock management functions\r\n *\r\n@verbatim\r\n ===============================================================================\r\n                ##### Extended clock management functions  #####\r\n ===============================================================================\r\n    [..]\r\n    This subsection provides a set of functions allowing to control the\r\n    activation or deactivation of PLLI2S, PLLSAI.\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Enable PLLI2S.\r\n  * @param  PLLI2SInit  pointer to an RCC_PLLI2SInitTypeDef structure that\r\n  *         contains the configuration information for the PLLI2S\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef  *PLLI2SInit)\r\n{\r\n  uint32_t tickstart;\r\n\r\n  /* Check for parameters */\r\n  assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SInit->PLLI2SN));\r\n  assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SInit->PLLI2SR));\r\n  assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SInit->PLLI2SQ));\r\n#if defined(RCC_PLLI2SCFGR_PLLI2SP)\r\n  assert_param(IS_RCC_PLLI2SP_VALUE(PLLI2SInit->PLLI2SP));\r\n#endif /* RCC_PLLI2SCFGR_PLLI2SP */\r\n\r\n  /* Disable the PLLI2S */\r\n  __HAL_RCC_PLLI2S_DISABLE();\r\n\r\n  /* Wait till PLLI2S is disabled */\r\n  tickstart = HAL_GetTick();\r\n  while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)\r\n  {\r\n    if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)\r\n    {\r\n      /* return in case of Timeout detected */\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n\r\n  /* Configure the PLLI2S division factors */\r\n#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)\r\n  /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */\r\n  /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */\r\n  /* I2SRCLK = PLLI2S_VCO / PLLI2SR */\r\n  __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR);\r\n#else\r\n  /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */\r\n  /* I2SPCLK = PLLI2S_VCO / PLLI2SP */\r\n  /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */\r\n  /* I2SRCLK = PLLI2S_VCO / PLLI2SR */\r\n  __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SP, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR);\r\n#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */\r\n\r\n  /* Enable the PLLI2S */\r\n  __HAL_RCC_PLLI2S_ENABLE();\r\n\r\n  /* Wait till PLLI2S is ready */\r\n  tickstart = HAL_GetTick();\r\n  while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)\r\n  {\r\n    if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)\r\n    {\r\n      /* return in case of Timeout detected */\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n\r\n return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Disable PLLI2S.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)\r\n{\r\n  uint32_t tickstart;\r\n\r\n  /* Disable the PLLI2S */\r\n  __HAL_RCC_PLLI2S_DISABLE();\r\n\r\n  /* Wait till PLLI2S is disabled */\r\n  tickstart = HAL_GetTick();\r\n  while(READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET)\r\n  {\r\n    if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)\r\n    {\r\n      /* return in case of Timeout detected */\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Enable PLLSAI.\r\n  * @param  PLLSAIInit  pointer to an RCC_PLLSAIInitTypeDef structure that\r\n  *         contains the configuration information for the PLLSAI\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef  *PLLSAIInit)\r\n{\r\n  uint32_t tickstart;\r\n\r\n  /* Check for parameters */\r\n  assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIInit->PLLSAIN));\r\n  assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIInit->PLLSAIQ));\r\n  assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIInit->PLLSAIP));\r\n#if defined(RCC_PLLSAICFGR_PLLSAIR)\r\n  assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIInit->PLLSAIR));\r\n#endif /* RCC_PLLSAICFGR_PLLSAIR */\r\n\r\n  /* Disable the PLLSAI */\r\n  __HAL_RCC_PLLSAI_DISABLE();\r\n\r\n  /* Wait till PLLSAI is disabled */\r\n  tickstart = HAL_GetTick();\r\n  while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)\r\n  {\r\n    if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)\r\n    {\r\n      /* return in case of Timeout detected */\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n\r\n  /* Configure the PLLSAI division factors */\r\n#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)\r\n  /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */\r\n  /* SAIPCLK = PLLSAI_VCO / PLLSAIP */\r\n  /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */\r\n  __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, PLLSAIInit->PLLSAIQ);\r\n#else\r\n  /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */\r\n  /* SAIPCLK = PLLSAI_VCO / PLLSAIP */\r\n  /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */\r\n  /* SAIRCLK = PLLSAI_VCO / PLLSAIR */\r\n  __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, \\\r\n                          PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR);\r\n#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */\r\n\r\n  /* Enable the PLLSAI */\r\n  __HAL_RCC_PLLSAI_ENABLE();\r\n\r\n  /* Wait till PLLSAI is ready */\r\n  tickstart = HAL_GetTick();\r\n  while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)\r\n  {\r\n    if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)\r\n    {\r\n      /* return in case of Timeout detected */\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n\r\n return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Disable PLLSAI.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void)\r\n{\r\n  uint32_t tickstart;\r\n\r\n  /* Disable the PLLSAI */\r\n  __HAL_RCC_PLLSAI_DISABLE();\r\n\r\n  /* Wait till PLLSAI is disabled */\r\n  tickstart = HAL_GetTick();\r\n  while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)\r\n  {\r\n    if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)\r\n    {\r\n      /* return in case of Timeout detected */\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_RCC_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rng.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_rng.c\r\n  * @author  MCD Application Team\r\n  * @brief   RNG HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the Random Number Generator (RNG) peripheral:\r\n  *           + Initialization/de-initialization functions\r\n  *           + Peripheral Control functions \r\n  *           + Peripheral State functions\r\n  *         \r\n  @verbatim\r\n  ==============================================================================\r\n                     ##### How to use this driver #####\r\n  ==============================================================================\r\n  [..]\r\n      The RNG HAL driver can be used as follows:\r\n\r\n      (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro \r\n          in HAL_RNG_MspInit().\r\n      (#) Activate the RNG peripheral using HAL_RNG_Init() function.\r\n      (#) Wait until the 32 bit Random Number Generator contains a valid \r\n          random data using (polling/interrupt) mode.   \r\n      (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.\r\n  \r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup RNG \r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_RNG_MODULE_ENABLED\r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private defines -----------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @addtogroup RNG_Private_Constants\r\n  * @{\r\n  */\r\n#define RNG_TIMEOUT_VALUE     2U\r\n/**\r\n  * @}\r\n  */ \r\n/* Private macros ------------------------------------------------------------*/\r\n/* Private functions prototypes ----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @addtogroup RNG_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup RNG_Exported_Functions_Group1\r\n *  @brief   Initialization and de-initialization functions\r\n *\r\n@verbatim\r\n ===============================================================================\r\n          ##### Initialization and de-initialization functions #####\r\n ===============================================================================\r\n    [..]  This section provides functions allowing to:\r\n      (+) Initialize the RNG according to the specified parameters \r\n          in the RNG_InitTypeDef and create the associated handle\r\n      (+) DeInitialize the RNG peripheral\r\n      (+) Initialize the RNG MSP\r\n      (+) DeInitialize RNG MSP \r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @brief  Initializes the RNG peripheral and creates the associated handle.\r\n  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains\r\n  *                the configuration information for RNG.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)\r\n{ \r\n  /* Check the RNG handle allocation */\r\n  if(hrng == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  if(hrng->State == HAL_RNG_STATE_RESET)\r\n  {  \r\n    /* Allocate lock resource and initialize it */\r\n    hrng->Lock = HAL_UNLOCKED;\r\n    /* Init the low level hardware */\r\n    HAL_RNG_MspInit(hrng);\r\n  }\r\n  \r\n  /* Change RNG peripheral state */\r\n  hrng->State = HAL_RNG_STATE_BUSY;\r\n\r\n  /* Enable the RNG Peripheral */\r\n  __HAL_RNG_ENABLE(hrng);\r\n\r\n  /* Initialize the RNG state */\r\n  hrng->State = HAL_RNG_STATE_READY;\r\n\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the RNG peripheral. \r\n  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains\r\n  *                the configuration information for RNG.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)\r\n{ \r\n  /* Check the RNG handle allocation */\r\n  if(hrng == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  /* Disable the RNG Peripheral */\r\n  CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN);\r\n  \r\n  /* Clear RNG interrupt status flags */\r\n  CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS);\r\n  \r\n  /* DeInit the low level hardware */\r\n  HAL_RNG_MspDeInit(hrng);\r\n  \r\n  /* Update the RNG state */\r\n  hrng->State = HAL_RNG_STATE_RESET; \r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hrng);\r\n  \r\n  /* Return the function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the RNG MSP.\r\n  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains\r\n  *                the configuration information for RNG.\r\n  * @retval None\r\n  */\r\n__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hrng);\r\n  /* NOTE : This function should not be modified. When the callback is needed,\r\n            function HAL_RNG_MspInit must be implemented in the user file.\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the RNG MSP.\r\n  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains\r\n  *                the configuration information for RNG.\r\n  * @retval None\r\n  */\r\n__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hrng);\r\n  /* NOTE : This function should not be modified. When the callback is needed,\r\n            function HAL_RNG_MspDeInit must be implemented in the user file.\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup RNG_Exported_Functions_Group2\r\n *  @brief   Peripheral Control functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                      ##### Peripheral Control functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Get the 32 bit Random number\r\n      (+) Get the 32 bit Random number with interrupt enabled\r\n      (+) Handle RNG interrupt request \r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n   \r\n/**\r\n  * @brief  Generates a 32-bit random number.\r\n  * @note   Each time the random number data is read the RNG_FLAG_DRDY flag \r\n  *         is automatically cleared.\r\n  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains\r\n  *                the configuration information for RNG.\r\n  * @param  random32bit pointer to generated random number variable if successful.\r\n  * @retval HAL status\r\n  */\r\n\r\nHAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)\r\n{\r\n  uint32_t tickstart = 0U;    \r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Process Locked */\r\n  __HAL_LOCK(hrng); \r\n  \r\n  /* Check RNG peripheral state */\r\n  if(hrng->State == HAL_RNG_STATE_READY)\r\n  {\r\n    /* Change RNG peripheral state */  \r\n    hrng->State = HAL_RNG_STATE_BUSY;  \r\n\r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n  \r\n    /* Check if data register contains valid random data */\r\n    while(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE)\r\n      {    \r\n        hrng->State = HAL_RNG_STATE_ERROR;\r\n\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hrng);\r\n      \r\n        return HAL_TIMEOUT;\r\n      } \r\n    }\r\n  \r\n    /* Get a 32bit Random number */\r\n    hrng->RandomNumber = hrng->Instance->DR;\r\n    *random32bit = hrng->RandomNumber;\r\n  \r\n    hrng->State = HAL_RNG_STATE_READY;\r\n  }\r\n  else\r\n  {\r\n    status = HAL_ERROR;\r\n  }\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hrng);\r\n  \r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Generates a 32-bit random number in interrupt mode.\r\n  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains\r\n  *                the configuration information for RNG.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hrng);\r\n  \r\n  /* Check RNG peripheral state */\r\n  if(hrng->State == HAL_RNG_STATE_READY)\r\n  {\r\n    /* Change RNG peripheral state */  \r\n    hrng->State = HAL_RNG_STATE_BUSY;  \r\n  \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hrng);\r\n    \r\n    /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ \r\n    __HAL_RNG_ENABLE_IT(hrng);\r\n  }\r\n  else\r\n  {\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hrng);\r\n    \r\n    status = HAL_ERROR;\r\n  }\r\n  \r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Handles RNG interrupt request.\r\n  * @note   In the case of a clock error, the RNG is no more able to generate \r\n  *         random numbers because the PLL48CLK clock is not correct. User has \r\n  *         to check that the clock controller is correctly configured to provide\r\n  *         the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT(). \r\n  *         The clock error has no impact on the previously generated \r\n  *         random numbers, and the RNG_DR register contents can be used.\r\n  * @note   In the case of a seed error, the generation of random numbers is \r\n  *         interrupted as long as the SECS bit is '1'. If a number is \r\n  *         available in the RNG_DR register, it must not be used because it may \r\n  *         not have enough entropy. In this case, it is recommended to clear the \r\n  *         SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable \r\n  *         the RNG peripheral to reinitialize and restart the RNG.\r\n  * @note   User-written HAL_RNG_ErrorCallback() API is called once whether SEIS\r\n  *         or CEIS are set.  \r\n  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains\r\n  *                the configuration information for RNG.\r\n  * @retval None\r\n\r\n  */\r\nvoid HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)\r\n{\r\n  /* RNG clock error interrupt occurred */\r\n  if((__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) ||  (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET))\r\n  { \r\n    /* Change RNG peripheral state */\r\n    hrng->State = HAL_RNG_STATE_ERROR;\r\n  \r\n    HAL_RNG_ErrorCallback(hrng);\r\n    \r\n    /* Clear the clock error flag */\r\n    __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI|RNG_IT_SEI);\r\n    \r\n  }\r\n  \r\n  /* Check RNG data ready interrupt occurred */    \r\n  if(__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)\r\n  {\r\n    /* Generate random number once, so disable the IT */\r\n    __HAL_RNG_DISABLE_IT(hrng);\r\n    \r\n    /* Get the 32bit Random number (DRDY flag automatically cleared) */ \r\n    hrng->RandomNumber = hrng->Instance->DR;\r\n    \r\n    if(hrng->State != HAL_RNG_STATE_ERROR)\r\n    {\r\n      /* Change RNG peripheral state */\r\n      hrng->State = HAL_RNG_STATE_READY; \r\n      \r\n      /* Data Ready callback */ \r\n      HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);\r\n    } \r\n  }\r\n} \r\n\r\n/**\r\n  * @brief  Returns generated random number in polling mode (Obsolete)\r\n  *         Use HAL_RNG_GenerateRandomNumber() API instead.\r\n  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains\r\n  *                the configuration information for RNG.\r\n  * @retval Random value\r\n  */\r\nuint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng)\r\n{\r\n  if(HAL_RNG_GenerateRandomNumber(hrng, &(hrng->RandomNumber)) == HAL_OK)\r\n  {\r\n    return hrng->RandomNumber; \r\n  }\r\n  else\r\n  {\r\n    return 0U;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Returns a 32-bit random number with interrupt enabled (Obsolete),\r\n  *         Use HAL_RNG_GenerateRandomNumber_IT() API instead.\r\n  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains\r\n  *                the configuration information for RNG.\r\n  * @retval 32-bit random number\r\n  */\r\nuint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)\r\n{\r\n  uint32_t random32bit = 0U;\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hrng);\r\n  \r\n  /* Change RNG peripheral state */  \r\n  hrng->State = HAL_RNG_STATE_BUSY;  \r\n  \r\n  /* Get a 32bit Random number */ \r\n  random32bit = hrng->Instance->DR;\r\n  \r\n  /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ \r\n  __HAL_RNG_ENABLE_IT(hrng); \r\n  \r\n  /* Return the 32 bit random number */   \r\n  return random32bit;\r\n}\r\n\r\n/**\r\n  * @brief  Read latest generated random number. \r\n  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains\r\n  *                the configuration information for RNG.\r\n  * @retval random value\r\n  */\r\nuint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)\r\n{\r\n  return(hrng->RandomNumber);\r\n}\r\n\r\n/**\r\n  * @brief  Data Ready callback in non-blocking mode. \r\n  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains\r\n  *                the configuration information for RNG.\r\n  * @param  random32bit generated random number.\r\n  * @retval None\r\n  */\r\n__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hrng);\r\n  UNUSED(random32bit);\r\n  /* NOTE : This function should not be modified. When the callback is needed,\r\n            function HAL_RNG_ReadyDataCallback must be implemented in the user file.\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  RNG error callbacks.\r\n  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains\r\n  *                the configuration information for RNG.\r\n  * @retval None\r\n  */\r\n__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hrng);\r\n  /* NOTE : This function should not be modified. When the callback is needed,\r\n            function HAL_RNG_ErrorCallback must be implemented in the user file.\r\n   */\r\n}\r\n/**\r\n  * @}\r\n  */ \r\n\r\n  \r\n/** @addtogroup RNG_Exported_Functions_Group3\r\n *  @brief   Peripheral State functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                      ##### Peripheral State functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection permits to get in run-time the status of the peripheral \r\n    and the data flow.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @brief  Returns the RNG state.\r\n  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains\r\n  *                the configuration information for RNG.\r\n  * @retval HAL state\r\n  */\r\nHAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)\r\n{\r\n  return hrng->State;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_RNG_MODULE_ENABLED */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_rtc.c\r\n  * @author  MCD Application Team\r\n  * @brief   RTC HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the Real Time Clock (RTC) peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + RTC Time and Date functions\r\n  *           + RTC Alarm functions\r\n  *           + Peripheral Control functions   \r\n  *           + Peripheral State functions\r\n  *         \r\n  @verbatim\r\n  ==============================================================================\r\n              ##### Backup Domain Operating Condition #####\r\n  ==============================================================================\r\n  [..] The real-time clock (RTC), the RTC backup registers, and the backup \r\n       SRAM (BKP SRAM) can be powered from the VBAT voltage when the main \r\n       VDD supply is powered off.\r\n       To retain the content of the RTC backup registers, backup SRAM, and supply \r\n       the RTC when VDD is turned off, VBAT pin can be connected to an optional \r\n       standby voltage supplied by a battery or by another source.\r\n\r\n  [..] To allow the RTC operating even when the main digital supply (VDD) is turned\r\n       off, the VBAT pin powers the following blocks:\r\n    (#) The RTC\r\n    (#) The LSE oscillator\r\n    (#) The backup SRAM when the low power backup regulator is enabled\r\n    (#) PC13 to PC15 I/Os, plus PI8 I/O (when available)\r\n  \r\n  [..] When the backup domain is supplied by VDD (analog switch connected to VDD),\r\n       the following pins are available:\r\n    (#) PC14 and PC15 can be used as either GPIO or LSE pins\r\n    (#) PC13 can be used as a GPIO or as the RTC_AF1 pin\r\n    (#) PI8 can be used as a GPIO or as the RTC_AF2 pin\r\n  \r\n  [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT \r\n       because VDD is not present), the following pins are available:\r\n    (#) PC14 and PC15 can be used as LSE pins only\r\n    (#) PC13 can be used as the RTC_AF1 pin \r\n    (#) PI8 can be used as the RTC_AF2 pin\r\n    (#) PC1 can be used as the RTC_AF3 pin\r\n             \r\n                   ##### Backup Domain Reset #####\r\n  ==================================================================\r\n  [..] The backup domain reset sets all RTC registers and the RCC_BDCR register \r\n       to their reset values. The BKPSRAM is not affected by this reset. The only\r\n       way to reset the BKPSRAM is through the Flash interface by requesting \r\n       a protection level change from 1 to 0.\r\n  [..] A backup domain reset is generated when one of the following events occurs:\r\n    (#) Software reset, triggered by setting the BDRST bit in the \r\n        RCC Backup domain control register (RCC_BDCR). \r\n    (#) VDD or VBAT power on, if both supplies have previously been powered off.  \r\n\r\n                   ##### Backup Domain Access #####\r\n  ==================================================================\r\n  [..] After reset, the backup domain (RTC registers, RTC backup data \r\n       registers and backup SRAM) is protected against possible unwanted write \r\n       accesses. \r\n  [..] To enable access to the RTC Domain and RTC registers, proceed as follows:\r\n    (+) Enable the Power Controller (PWR) APB1 interface clock using the\r\n        __HAL_RCC_PWR_CLK_ENABLE() function.\r\n    (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.\r\n    (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.\r\n    (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.\r\n  \r\n  \r\n                  ##### How to use this driver #####\r\n  ==================================================================\r\n  [..] \r\n    (+) Enable the RTC domain access (see description in the section above).\r\n    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour \r\n        format using the HAL_RTC_Init() function.\r\n  \r\n  *** Time and Date configuration ***\r\n  ===================================\r\n  [..] \r\n    (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime() \r\n        and HAL_RTC_SetDate() functions.\r\n    (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions. \r\n  \r\n  *** Alarm configuration ***\r\n  ===========================\r\n  [..]\r\n    (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function. \r\n        You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function.\r\n    (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.\r\n  \r\n                  ##### RTC and low power modes #####\r\n  ==================================================================\r\n  [..] The MCU can be woken up from a low power mode by an RTC alternate \r\n       function.\r\n  [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), \r\n       RTC wakeup, RTC tamper event detection and RTC time stamp event detection.\r\n       These RTC alternate functions can wake up the system from the Stop and \r\n       Standby low power modes.\r\n  [..] The system can also wake up from low power modes without depending \r\n       on an external interrupt (Auto-wakeup mode), by using the RTC alarm \r\n       or the RTC wakeup events.\r\n  [..] The RTC provides a programmable time base for waking up from the \r\n       Stop or Standby mode at regular intervals.\r\n       Wakeup from STOP and STANDBY modes is possible only when the RTC clock source\r\n       is LSE or LSI.\r\n     \r\n   @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup RTC RTC\r\n  * @brief RTC HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_RTC_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup RTC_Exported_Functions RTC Exported Functions\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup RTC_Group1 Initialization and de-initialization functions \r\n *  @brief    Initialization and Configuration functions \r\n *\r\n@verbatim    \r\n ===============================================================================\r\n              ##### Initialization and de-initialization functions #####\r\n ===============================================================================\r\n   [..] This section provides functions allowing to initialize and configure the \r\n         RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable \r\n         RTC registers Write protection, enter and exit the RTC initialization mode, \r\n         RTC registers synchronization check and reference clock detection enable.\r\n         (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. \r\n             It is split into 2 programmable prescalers to minimize power consumption.\r\n             (++) A 7-bit asynchronous prescaler and a 13-bit synchronous prescaler.\r\n             (++) When both prescalers are used, it is recommended to configure the \r\n                 asynchronous prescaler to a high value to minimize power consumption.\r\n         (#) All RTC registers are Write protected. Writing to the RTC registers\r\n             is enabled by writing a key into the Write Protection register, RTC_WPR.\r\n         (#) To configure the RTC Calendar, user application should enter \r\n             initialization mode. In this mode, the calendar counter is stopped \r\n             and its value can be updated. When the initialization sequence is \r\n             complete, the calendar restarts counting after 4 RTCCLK cycles.\r\n         (#) To read the calendar through the shadow registers after Calendar \r\n             initialization, calendar update or after wakeup from low power modes \r\n             the software must first clear the RSF flag. The software must then \r\n             wait until it is set again before reading the calendar, which means \r\n             that the calendar registers have been correctly copied into the \r\n             RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function \r\n             implements the above software sequence (RSF clear and RSF check).\r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the RTC peripheral \r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)\r\n{\r\n  /* Check the RTC peripheral state */\r\n  if(hrtc == NULL)\r\n  {\r\n     return HAL_ERROR;\r\n  }\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));\r\n  assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));\r\n  assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));\r\n  assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv));\r\n  assert_param (IS_RTC_OUTPUT(hrtc->Init.OutPut));\r\n  assert_param (IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));\r\n  assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));\r\n    \r\n  if(hrtc->State == HAL_RTC_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    hrtc->Lock = HAL_UNLOCKED;\r\n    /* Initialize RTC MSP */\r\n    HAL_RTC_MspInit(hrtc);\r\n  }\r\n  \r\n  /* Set RTC state */  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;  \r\n       \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n\r\n  /* Set Initialization mode */\r\n  if(RTC_EnterInitMode(hrtc) != HAL_OK)\r\n  {\r\n    /* Enable the write protection for RTC registers */\r\n    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r\n    \r\n    /* Set RTC state */\r\n    hrtc->State = HAL_RTC_STATE_ERROR;\r\n    \r\n    return HAL_ERROR;\r\n  } \r\n  else\r\n  { \r\n    /* Clear RTC_CR FMT, OSEL and POL Bits */\r\n    hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));\r\n    /* Set RTC_CR register */\r\n    hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);\r\n    \r\n    /* Configure the RTC PRER */\r\n    hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);\r\n    hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16);\r\n    \r\n    /* Exit Initialization mode */\r\n    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; \r\n    \r\n    hrtc->Instance->OR &= (uint32_t)~RTC_OR_ALARMTYPE;\r\n    hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType); \r\n    \r\n    /* Enable the write protection for RTC registers */\r\n    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r\n    \r\n    /* Set RTC state */\r\n    hrtc->State = HAL_RTC_STATE_READY;\r\n    \r\n    return HAL_OK;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the RTC peripheral \r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @note   This function doesn't reset the RTC Backup Data registers.   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));\r\n\r\n  /* Set RTC state */\r\n  hrtc->State = HAL_RTC_STATE_BUSY; \r\n  \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  /* Set Initialization mode */\r\n  if(RTC_EnterInitMode(hrtc) != HAL_OK)\r\n  {\r\n    /* Enable the write protection for RTC registers */\r\n    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r\n    \r\n    /* Set RTC state */\r\n    hrtc->State = HAL_RTC_STATE_ERROR;\r\n    \r\n    return HAL_ERROR;\r\n  }  \r\n  else\r\n  {\r\n    /* Reset TR, DR and CR registers */\r\n    hrtc->Instance->TR = (uint32_t)0x00000000;\r\n    hrtc->Instance->DR = (uint32_t)0x00002101;\r\n    /* Reset All CR bits except CR[2:0] */\r\n    hrtc->Instance->CR &= (uint32_t)0x00000007;\r\n\r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n    /* Wait till WUTWF flag is set and if Time out is reached exit */\r\n    while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r\n      { \r\n        /* Enable the write protection for RTC registers */\r\n        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r\n        \r\n        /* Set RTC state */\r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT;\r\n        \r\n        return HAL_TIMEOUT;\r\n      }      \r\n    }\r\n    \r\n    /* Reset all RTC CR register bits */\r\n    hrtc->Instance->CR &= (uint32_t)0x00000000;\r\n    hrtc->Instance->WUTR = (uint32_t)0x0000FFFF;\r\n    hrtc->Instance->PRER = (uint32_t)0x007F00FF;\r\n    hrtc->Instance->ALRMAR = (uint32_t)0x00000000;\r\n    hrtc->Instance->ALRMBR = (uint32_t)0x00000000;\r\n    hrtc->Instance->SHIFTR = (uint32_t)0x00000000;\r\n    hrtc->Instance->CALR = (uint32_t)0x00000000;\r\n    hrtc->Instance->ALRMASSR = (uint32_t)0x00000000;\r\n    hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000;\r\n    \r\n    /* Reset ISR register and exit initialization mode */\r\n    hrtc->Instance->ISR = (uint32_t)0x00000000;\r\n    \r\n    /* Reset Tamper and alternate functions configuration register */\r\n    hrtc->Instance->TAMPCR = 0x00000000;\r\n    \r\n    /* Reset Option register */\r\n    hrtc->Instance->OR = 0x00000000;\r\n    \r\n    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */\r\n    if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)\r\n    {\r\n      if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)\r\n      {\r\n        /* Enable the write protection for RTC registers */\r\n        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  \r\n        \r\n        hrtc->State = HAL_RTC_STATE_ERROR;\r\n        \r\n        return HAL_ERROR;\r\n      }\r\n    }    \r\n  }\r\n  \r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n  \r\n  /* De-Initialize RTC MSP */\r\n  HAL_RTC_MspDeInit(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_RESET; \r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hrtc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the RTC MSP.\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.  \r\n  * @retval None\r\n  */\r\n__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hrtc);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_RTC_MspInit could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the RTC MSP.\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC. \r\n  * @retval None\r\n  */\r\n__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hrtc);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_RTC_MspDeInit could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RTC_Group2 RTC Time and Date functions\r\n *  @brief   RTC Time and Date functions\r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                 ##### RTC Time and Date functions #####\r\n ===============================================================================  \r\n \r\n [..] This section provides functions allowing to configure Time and Date features\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Sets RTC current time.\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  sTime Pointer to Time structure\r\n  * @param  Format Specifies the format of the entered parameters.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg FORMAT_BIN: Binary data format \r\n  *            @arg FORMAT_BCD: BCD data format\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)\r\n{\r\n  uint32_t tmpreg = 0;\r\n  \r\n /* Check the parameters */\r\n  assert_param(IS_RTC_FORMAT(Format));\r\n  assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));\r\n  assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));\r\n  \r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n  if(Format == RTC_FORMAT_BIN)\r\n  {\r\n    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)\r\n    {\r\n      assert_param(IS_RTC_HOUR12(sTime->Hours));\r\n      assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));\r\n    } \r\n    else\r\n    {\r\n      sTime->TimeFormat = 0x00;\r\n      assert_param(IS_RTC_HOUR24(sTime->Hours));\r\n    }\r\n    assert_param(IS_RTC_MINUTES(sTime->Minutes));\r\n    assert_param(IS_RTC_SECONDS(sTime->Seconds));\r\n    \r\n    tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \\\r\n                        ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \\\r\n                        ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \\\r\n                        (((uint32_t)sTime->TimeFormat) << 16));  \r\n  }\r\n  else\r\n  {\r\n    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)\r\n    {\r\n      tmpreg = RTC_Bcd2ToByte(sTime->Hours);\r\n      assert_param(IS_RTC_HOUR12(tmpreg));\r\n      assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); \r\n    } \r\n    else\r\n    {\r\n      sTime->TimeFormat = 0x00;\r\n      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));\r\n    }\r\n    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));\r\n    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));\r\n    tmpreg = (((uint32_t)(sTime->Hours) << 16) | \\\r\n              ((uint32_t)(sTime->Minutes) << 8) | \\\r\n              ((uint32_t)sTime->Seconds) | \\\r\n              ((uint32_t)(sTime->TimeFormat) << 16));   \r\n  }\r\n  \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  /* Set Initialization mode */\r\n  if(RTC_EnterInitMode(hrtc) != HAL_OK)\r\n  {\r\n    /* Enable the write protection for RTC registers */\r\n    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r\n    \r\n    /* Set RTC state */\r\n    hrtc->State = HAL_RTC_STATE_ERROR;\r\n    \r\n    /* Process Unlocked */ \r\n    __HAL_UNLOCK(hrtc);\r\n    \r\n    return HAL_ERROR;\r\n  } \r\n  else\r\n  {\r\n    /* Set the RTC_TR register */\r\n    hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);\r\n     \r\n    /* Clear the bits to be configured */\r\n    hrtc->Instance->CR &= (uint32_t)~RTC_CR_BKP;\r\n    \r\n    /* Configure the RTC_CR register */\r\n    hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);\r\n    \r\n    /* Exit Initialization mode */\r\n    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;  \r\n    \r\n    /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */\r\n    if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)\r\n    {\r\n      if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)\r\n      {        \r\n        /* Enable the write protection for RTC registers */\r\n        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  \r\n        \r\n        hrtc->State = HAL_RTC_STATE_ERROR;\r\n        \r\n        /* Process Unlocked */ \r\n        __HAL_UNLOCK(hrtc);\r\n        \r\n        return HAL_ERROR;\r\n      }\r\n    }\r\n    \r\n    /* Enable the write protection for RTC registers */\r\n    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n    \r\n   hrtc->State = HAL_RTC_STATE_READY;\r\n  \r\n   __HAL_UNLOCK(hrtc); \r\n     \r\n   return HAL_OK;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Gets RTC current time.\r\n  * @param  hrtc RTC handle\r\n  * @param  sTime Pointer to Time structure with Hours, Minutes and Seconds fields returned \r\n  *                with input format (BIN or BCD), also SubSeconds field returning the\r\n  *                RTC_SSR register content and SecondFraction field the Synchronous pre-scaler\r\n  *                factor to be used for second fraction ratio computation.\r\n  * @param  Format Specifies the format of the entered parameters.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RTC_FORMAT_BIN: Binary data format \r\n  *            @arg RTC_FORMAT_BCD: BCD data format\r\n  * @note  You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds\r\n  *        value in second fraction ratio with time unit following generic formula:\r\n  *        Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit\r\n  *        This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS\r\n  * @note  You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values \r\n  *        in the higher-order calendar shadow registers to ensure consistency between the time and date values.\r\n  *        Reading RTC current time locks the values in calendar shadow registers until Current date is read\r\n  *        to ensure consistency between the time and date values.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)\r\n{\r\n  uint32_t tmpreg = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_FORMAT(Format));\r\n  \r\n  /* Get subseconds values from the correspondent registers*/\r\n  sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR);\r\n  \r\n  /* Get SecondFraction structure field from the corresponding register field*/\r\n  sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S);\r\n\r\n  /* Get the TR register */\r\n  tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK); \r\n  \r\n  /* Fill the structure fields with the read parameters */\r\n  sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);\r\n  sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);\r\n  sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));\r\n  sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); \r\n  \r\n  /* Check the input parameters format */\r\n  if(Format == RTC_FORMAT_BIN)\r\n  {\r\n    /* Convert the time structure parameters to Binary format */\r\n    sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);\r\n    sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes);\r\n    sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);  \r\n  }\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Sets RTC current date.\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  sDate Pointer to date structure\r\n  * @param  Format specifies the format of the entered parameters.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RTC_FORMAT_BIN: Binary data format \r\n  *            @arg RTC_FORMAT_BCD: BCD data format\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)\r\n{\r\n  uint32_t datetmpreg = 0;\r\n  \r\n /* Check the parameters */\r\n  assert_param(IS_RTC_FORMAT(Format));\r\n  \r\n /* Process Locked */ \r\n __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY; \r\n  \r\n  if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U))\r\n  {\r\n    sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU);\r\n  }\r\n  \r\n  assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));\r\n  \r\n  if(Format == RTC_FORMAT_BIN)\r\n  {   \r\n    assert_param(IS_RTC_YEAR(sDate->Year));\r\n    assert_param(IS_RTC_MONTH(sDate->Month));\r\n    assert_param(IS_RTC_DATE(sDate->Date)); \r\n    \r\n   datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \\\r\n                 ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \\\r\n                 ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \\\r\n                 ((uint32_t)sDate->WeekDay << 13));   \r\n  }\r\n  else\r\n  {   \r\n    assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));\r\n    assert_param(IS_RTC_MONTH(sDate->Month));\r\n    assert_param(IS_RTC_DATE(sDate->Date));\r\n    \r\n    datetmpreg = ((((uint32_t)sDate->Year) << 16) | \\\r\n                  (((uint32_t)sDate->Month) << 8) | \\\r\n                  ((uint32_t)sDate->Date) | \\\r\n                  (((uint32_t)sDate->WeekDay) << 13));  \r\n  }\r\n\r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  /* Set Initialization mode */\r\n  if(RTC_EnterInitMode(hrtc) != HAL_OK)\r\n  {\r\n    /* Enable the write protection for RTC registers */\r\n    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r\n    \r\n    /* Set RTC state*/\r\n    hrtc->State = HAL_RTC_STATE_ERROR;\r\n    \r\n    /* Process Unlocked */ \r\n    __HAL_UNLOCK(hrtc);\r\n    \r\n    return HAL_ERROR;\r\n  } \r\n  else\r\n  {\r\n    /* Set the RTC_DR register */\r\n    hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);\r\n    \r\n    /* Exit Initialization mode */\r\n    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;  \r\n    \r\n    /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */\r\n    if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)\r\n    {\r\n      if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)\r\n      { \r\n        /* Enable the write protection for RTC registers */\r\n        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  \r\n        \r\n        hrtc->State = HAL_RTC_STATE_ERROR;\r\n        \r\n        /* Process Unlocked */ \r\n        __HAL_UNLOCK(hrtc);\r\n        \r\n        return HAL_ERROR;\r\n      }\r\n    }\r\n    \r\n    /* Enable the write protection for RTC registers */\r\n    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  \r\n    \r\n    hrtc->State = HAL_RTC_STATE_READY ;\r\n    \r\n    /* Process Unlocked */ \r\n    __HAL_UNLOCK(hrtc);\r\n    \r\n    return HAL_OK;    \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Gets RTC current date.\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  sDate Pointer to Date structure\r\n  * @param  Format Specifies the format of the entered parameters.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RTC_FORMAT_BIN:  Binary data format \r\n  *            @arg RTC_FORMAT_BCD:  BCD data format\r\n  * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values \r\n  * in the higher-order calendar shadow registers to ensure consistency between the time and date values.\r\n  * Reading RTC current time locks the values in calendar shadow registers until Current date is read.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)\r\n{\r\n  uint32_t datetmpreg = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_FORMAT(Format));\r\n          \r\n  /* Get the DR register */\r\n  datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK); \r\n\r\n  /* Fill the structure fields with the read parameters */\r\n  sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);\r\n  sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);\r\n  sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU));\r\n  sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13); \r\n\r\n  /* Check the input parameters format */\r\n  if(Format == RTC_FORMAT_BIN)\r\n  {    \r\n    /* Convert the date structure parameters to Binary format */\r\n    sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);\r\n    sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);\r\n    sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);  \r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RTC_Group3 RTC Alarm functions\r\n *  @brief   RTC Alarm functions\r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                 ##### RTC Alarm functions #####\r\n ===============================================================================  \r\n \r\n [..] This section provides functions allowing to configure Alarm feature\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n/**\r\n  * @brief  Sets the specified RTC Alarm.\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  sAlarm Pointer to Alarm structure\r\n  * @param  Format Specifies the format of the entered parameters.\r\n  *          This parameter can be one of the following values:\r\n  *             @arg FORMAT_BIN: Binary data format \r\n  *             @arg FORMAT_BCD: BCD data format\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)\r\n{\r\n  uint32_t tickstart = 0;\r\n  uint32_t tmpreg = 0, subsecondtmpreg = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_FORMAT(Format));\r\n  assert_param(IS_RTC_ALARM(sAlarm->Alarm));\r\n  assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));\r\n  assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));\r\n  assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));\r\n  assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));\r\n  \r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n  if(Format == RTC_FORMAT_BIN)\r\n  {\r\n    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)\r\n    {\r\n      assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));\r\n      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));\r\n    } \r\n    else\r\n    {\r\n      sAlarm->AlarmTime.TimeFormat = 0x00;\r\n      assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));\r\n    }\r\n    assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));\r\n    assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));\r\n    \r\n    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)\r\n    {\r\n      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));\r\n    }\r\n    else\r\n    {\r\n      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));\r\n    }\r\n    \r\n    tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \\\r\n              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \\\r\n              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \\\r\n              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \\\r\n              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \\\r\n              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \\\r\n              ((uint32_t)sAlarm->AlarmMask)); \r\n  }\r\n  else\r\n  {\r\n    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)\r\n    {\r\n      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);\r\n      assert_param(IS_RTC_HOUR12(tmpreg));\r\n      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));\r\n    } \r\n    else\r\n    {\r\n      sAlarm->AlarmTime.TimeFormat = 0x00;\r\n      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));\r\n    }\r\n    \r\n    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));\r\n    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));\r\n    \r\n    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)\r\n    {\r\n      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);\r\n      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));    \r\n    }\r\n    else\r\n    {\r\n      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);\r\n      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));      \r\n    }  \r\n    \r\n    tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \\\r\n              ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \\\r\n              ((uint32_t) sAlarm->AlarmTime.Seconds) | \\\r\n              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \\\r\n              ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \\\r\n              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \\\r\n              ((uint32_t)sAlarm->AlarmMask));   \r\n  }\r\n  \r\n  /* Configure the Alarm A or Alarm B Sub Second registers */\r\n  subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));\r\n  \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n\r\n  /* Configure the Alarm register */\r\n  if(sAlarm->Alarm == RTC_ALARM_A)\r\n  {\r\n    /* Disable the Alarm A interrupt */\r\n    __HAL_RTC_ALARMA_DISABLE(hrtc);\r\n    \r\n    /* In case of interrupt mode is used, the interrupt source must disabled */ \r\n    __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);\r\n\r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n    /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */\r\n    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r\n      {\r\n        /* Enable the write protection for RTC registers */\r\n        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n        \r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT; \r\n        \r\n        /* Process Unlocked */ \r\n        __HAL_UNLOCK(hrtc);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }   \r\n    }\r\n    \r\n    hrtc->Instance->ALRMAR = (uint32_t)tmpreg;\r\n    /* Configure the Alarm A Sub Second register */\r\n    hrtc->Instance->ALRMASSR = subsecondtmpreg;\r\n    /* Configure the Alarm state: Enable Alarm */\r\n    __HAL_RTC_ALARMA_ENABLE(hrtc);\r\n  }\r\n  else\r\n  {\r\n    /* Disable the Alarm B interrupt */\r\n    __HAL_RTC_ALARMB_DISABLE(hrtc);\r\n    \r\n    /* In case of interrupt mode is used, the interrupt source must disabled */ \r\n    __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);\r\n\r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n    /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */\r\n    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r\n      {\r\n        /* Enable the write protection for RTC registers */\r\n        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n        \r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT; \r\n        \r\n        /* Process Unlocked */ \r\n        __HAL_UNLOCK(hrtc);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }  \r\n    }    \r\n    \r\n    hrtc->Instance->ALRMBR = (uint32_t)tmpreg;\r\n    /* Configure the Alarm B Sub Second register */\r\n    hrtc->Instance->ALRMBSSR = subsecondtmpreg;\r\n    /* Configure the Alarm state: Enable Alarm */\r\n    __HAL_RTC_ALARMB_ENABLE(hrtc); \r\n  }\r\n  \r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);   \r\n  \r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY; \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Sets the specified RTC Alarm with Interrupt \r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  sAlarm Pointer to Alarm structure\r\n  * @param  Format Specifies the format of the entered parameters.\r\n  *          This parameter can be one of the following values:\r\n  *             @arg FORMAT_BIN: Binary data format \r\n  *             @arg FORMAT_BCD: BCD data format\r\n  * @note   The Alarm register can only be written when the corresponding Alarm\r\n  *         is disabled (Use the HAL_RTC_DeactivateAlarm()).   \r\n  * @note   The HAL_RTC_SetTime() must be called before enabling the Alarm feature.   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)\r\n{\r\n  uint32_t tmpreg = 0U, subsecondtmpreg = 0U;\r\n  __IO uint32_t count = RTC_TIMEOUT_VALUE  * (SystemCoreClock / 32U / 1000U) ;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_FORMAT(Format));\r\n  assert_param(IS_RTC_ALARM(sAlarm->Alarm));\r\n  assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));\r\n  assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));\r\n  assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));\r\n  assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));\r\n      \r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n  if(Format == RTC_FORMAT_BIN)\r\n  {\r\n    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)\r\n    {\r\n      assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));\r\n      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));\r\n    } \r\n    else\r\n    {\r\n      sAlarm->AlarmTime.TimeFormat = 0x00U;\r\n      assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));\r\n    }\r\n    assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));\r\n    assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));\r\n    \r\n    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)\r\n    {\r\n      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));\r\n    }\r\n    else\r\n    {\r\n      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));\r\n    }\r\n    tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \\\r\n              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \\\r\n              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \\\r\n              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \\\r\n              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \\\r\n              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \\\r\n              ((uint32_t)sAlarm->AlarmMask)); \r\n  }\r\n  else\r\n  {\r\n    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)\r\n    {\r\n      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);\r\n      assert_param(IS_RTC_HOUR12(tmpreg));\r\n      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));\r\n    } \r\n    else\r\n    {\r\n      sAlarm->AlarmTime.TimeFormat = 0x00U;\r\n      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));\r\n    }\r\n    \r\n    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));\r\n    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));\r\n    \r\n    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)\r\n    {\r\n      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);\r\n      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));    \r\n    }\r\n    else\r\n    {\r\n      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);\r\n      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));      \r\n    }\r\n    tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \\\r\n              ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \\\r\n              ((uint32_t) sAlarm->AlarmTime.Seconds) | \\\r\n              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \\\r\n              ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \\\r\n              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \\\r\n              ((uint32_t)sAlarm->AlarmMask));     \r\n  }\r\n  /* Configure the Alarm A or Alarm B Sub Second registers */\r\n  subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));\r\n  \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  /* Configure the Alarm register */\r\n  if(sAlarm->Alarm == RTC_ALARM_A)\r\n  {\r\n    /* Disable the Alarm A interrupt */\r\n    __HAL_RTC_ALARMA_DISABLE(hrtc);\r\n\r\n    /* Clear flag alarm A */\r\n    __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);\r\n\r\n    /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */\r\n    do\r\n    {\r\n      if (count-- == 0U)\r\n      {\r\n        /* Enable the write protection for RTC registers */\r\n        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n\r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT;\r\n\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hrtc);\r\n\r\n        return HAL_TIMEOUT;\r\n      }\r\n    } \r\n    while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET);\r\n\r\n    hrtc->Instance->ALRMAR = (uint32_t)tmpreg;\r\n    /* Configure the Alarm A Sub Second register */\r\n    hrtc->Instance->ALRMASSR = subsecondtmpreg;\r\n    /* Configure the Alarm state: Enable Alarm */\r\n    __HAL_RTC_ALARMA_ENABLE(hrtc);\r\n    /* Configure the Alarm interrupt */\r\n    __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA);\r\n  }\r\n  else\r\n  {\r\n    /* Disable the Alarm B interrupt */\r\n    __HAL_RTC_ALARMB_DISABLE(hrtc);\r\n\r\n    /* Clear flag alarm B */\r\n    __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);\r\n\r\n    /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */\r\n    do\r\n    {\r\n      if (count-- == 0U)\r\n      {\r\n        /* Enable the write protection for RTC registers */\r\n        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n\r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT;\r\n\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hrtc);\r\n\r\n        return HAL_TIMEOUT;\r\n      }\r\n    } \r\n    while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET);\r\n    \r\n    hrtc->Instance->ALRMBR = (uint32_t)tmpreg;\r\n    /* Configure the Alarm B Sub Second register */\r\n    hrtc->Instance->ALRMBSSR = subsecondtmpreg;\r\n    /* Configure the Alarm state: Enable Alarm */\r\n    __HAL_RTC_ALARMB_ENABLE(hrtc);\r\n    /* Configure the Alarm interrupt */\r\n    __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB);\r\n  }\r\n\r\n  /* RTC Alarm Interrupt Configuration: EXTI configuration */\r\n  __HAL_RTC_ALARM_EXTI_ENABLE_IT();\r\n  \r\n  EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT;\r\n  \r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  \r\n  \r\n  hrtc->State = HAL_RTC_STATE_READY; \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);  \r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Deactive the specified RTC Alarm \r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  Alarm Specifies the Alarm.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RTC_ALARM_A:  AlarmA\r\n  *            @arg RTC_ALARM_B:  AlarmB\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_ALARM(Alarm));\r\n  \r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  if(Alarm == RTC_ALARM_A)\r\n  {\r\n    /* AlarmA */\r\n    __HAL_RTC_ALARMA_DISABLE(hrtc);\r\n    \r\n    /* In case of interrupt mode is used, the interrupt source must disabled */ \r\n    __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);\r\n\r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n    /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */\r\n    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r\n      { \r\n        /* Enable the write protection for RTC registers */\r\n        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n        \r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT; \r\n        \r\n        /* Process Unlocked */ \r\n        __HAL_UNLOCK(hrtc);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }      \r\n    }\r\n  }\r\n  else\r\n  {\r\n    /* AlarmB */\r\n    __HAL_RTC_ALARMB_DISABLE(hrtc);\r\n    \r\n    /* In case of interrupt mode is used, the interrupt source must disabled */ \r\n    __HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB);\r\n\r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n    /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */\r\n    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r\n      {\r\n        /* Enable the write protection for RTC registers */\r\n        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n        \r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT; \r\n        \r\n        /* Process Unlocked */ \r\n        __HAL_UNLOCK(hrtc);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }    \r\n    }\r\n  }\r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_READY; \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);  \r\n  \r\n  return HAL_OK; \r\n}\r\n           \r\n/**\r\n  * @brief  Gets the RTC Alarm value and masks.\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  sAlarm Pointer to Date structure\r\n  * @param  Alarm Specifies the Alarm.\r\n  *          This parameter can be one of the following values:\r\n  *             @arg RTC_ALARM_A: AlarmA\r\n  *             @arg RTC_ALARM_B: AlarmB  \r\n  * @param  Format Specifies the format of the entered parameters.\r\n  *          This parameter can be one of the following values:\r\n  *             @arg RTC_FORMAT_BIN: Binary data format \r\n  *             @arg RTC_FORMAT_BCD: BCD data format\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)\r\n{\r\n  uint32_t tmpreg = 0, subsecondtmpreg = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_FORMAT(Format));\r\n  assert_param(IS_RTC_ALARM(Alarm));\r\n  \r\n  if(Alarm == RTC_ALARM_A)\r\n  {\r\n    /* AlarmA */\r\n    sAlarm->Alarm = RTC_ALARM_A;\r\n    \r\n    tmpreg = (uint32_t)(hrtc->Instance->ALRMAR);\r\n    subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS);\r\n  }\r\n  else\r\n  {\r\n    sAlarm->Alarm = RTC_ALARM_B;\r\n    \r\n    tmpreg = (uint32_t)(hrtc->Instance->ALRMBR);\r\n    subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS);\r\n  }\r\n    \r\n  /* Fill the structure with the read parameters */\r\n  sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16);\r\n  sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8);\r\n  sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU));\r\n  sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);\r\n  sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;\r\n  sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);\r\n  sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);\r\n  sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);\r\n    \r\n  if(Format == RTC_FORMAT_BIN)\r\n  {\r\n    sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);\r\n    sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);\r\n    sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);\r\n    sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);\r\n  }  \r\n    \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  This function handles Alarm interrupt request.\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @retval None\r\n  */\r\nvoid HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)\r\n{  \r\n  if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRA))\r\n  {\r\n    /* Get the status of the Interrupt */\r\n    if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRA) != (uint32_t)RESET)\r\n    {\r\n      /* AlarmA callback */ \r\n      HAL_RTC_AlarmAEventCallback(hrtc);\r\n      \r\n      /* Clear the Alarm interrupt pending bit */\r\n      __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF);\r\n    }\r\n  }\r\n  \r\n  if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRB))\r\n  {\r\n    /* Get the status of the Interrupt */\r\n    if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRB) != (uint32_t)RESET)\r\n    {\r\n      /* AlarmB callback */ \r\n      HAL_RTCEx_AlarmBEventCallback(hrtc);\r\n      \r\n      /* Clear the Alarm interrupt pending bit */\r\n      __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRBF);\r\n    }\r\n  }\r\n  \r\n  /* Clear the EXTI's line Flag for RTC Alarm */\r\n  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();\r\n  \r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY;\r\n}\r\n\r\n/**\r\n  * @brief  Alarm A callback.\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hrtc);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_RTC_AlarmAEventCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  This function handles AlarmA Polling request.\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  Timeout Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0; \r\n\r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n  while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET)\r\n  {\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT;\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Clear the Alarm interrupt pending bit */\r\n  __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);\r\n  \r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY; \r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RTC_Group4 Peripheral Control functions \r\n *  @brief   Peripheral Control functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                     ##### Peripheral Control functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides functions allowing to\r\n      (+) Wait for RTC Time and Date Synchronization\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are \r\n  *         synchronized with RTC APB clock.\r\n  * @note   The RTC Resynchronization mode is write protected, use the \r\n  *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. \r\n  * @note   To read the calendar through the shadow registers after Calendar \r\n  *         initialization, calendar update or after wakeup from low power modes \r\n  *         the software must first clear the RSF flag. \r\n  *         The software must then wait until it is set again before reading \r\n  *         the calendar, which means that the calendar registers have been \r\n  *         correctly copied into the RTC_TR and RTC_DR shadow registers.   \r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)\r\n{\r\n  uint32_t tickstart = 0;\r\n\r\n  /* Clear RSF flag */\r\n  hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;\r\n\r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n  /* Wait the registers to be synchronised */\r\n  while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET)\r\n  {\r\n    if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r\n    {       \r\n      return HAL_TIMEOUT;\r\n    } \r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup RTC_Group5 Peripheral State functions \r\n *  @brief   Peripheral State functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                     ##### Peripheral State functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides functions allowing to\r\n      (+) Get RTC state\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n/**\r\n  * @brief  Returns the RTC state.\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @retval HAL state\r\n  */\r\nHAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)\r\n{\r\n  return hrtc->State;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @brief  Enters the RTC Initialization mode.\r\n  * @note   The RTC Initialization mode is write protected, use the\r\n  *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)\r\n{\r\n  uint32_t tickstart = 0; \r\n  \r\n  /* Check if the Initialization mode is set */\r\n  if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)\r\n  {\r\n    /* Set the Initialization mode */\r\n    hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;\r\n\r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n    /* Wait till RTC is in INIT state and if Time out is reached exit */\r\n    while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r\n      {       \r\n        return HAL_TIMEOUT;\r\n      } \r\n    }\r\n  }\r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n\r\n/**\r\n  * @brief  Converts a 2 digit decimal to BCD format.\r\n  * @param  Value Byte to be converted\r\n  * @retval Converted byte\r\n  */\r\nuint8_t RTC_ByteToBcd2(uint8_t Value)\r\n{\r\n  uint32_t bcdhigh = 0;\r\n  \r\n  while(Value >= 10)\r\n  {\r\n    bcdhigh++;\r\n    Value -= 10;\r\n  }\r\n  \r\n  return  ((uint8_t)(bcdhigh << 4) | Value);\r\n}\r\n\r\n/**\r\n  * @brief  Converts from 2 digit BCD to Binary.\r\n  * @param  Value BCD value to be converted\r\n  * @retval Converted word\r\n  */\r\nuint8_t RTC_Bcd2ToByte(uint8_t Value)\r\n{\r\n  uint32_t tmp = 0;\r\n  tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;\r\n  return (tmp + (Value & (uint8_t)0x0F));\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_RTC_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_rtc_ex.c\r\n  * @author  MCD Application Team\r\n  * @brief   RTC HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the Real Time Clock (RTC) Extension peripheral:\r\n  *           + RTC Time Stamp functions\r\n  *           + RTC Tamper functions \r\n  *           + RTC Wake-up functions\r\n  *           + Extension Control functions\r\n  *           + Extension RTC features functions    \r\n  *         \r\n  @verbatim\r\n  ==============================================================================\r\n                  ##### How to use this driver #####\r\n  ==============================================================================\r\n  [..] \r\n    (+) Enable the RTC domain access.\r\n    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour \r\n        format using the HAL_RTC_Init() function.\r\n  \r\n  *** RTC Wakeup configuration ***\r\n  ================================\r\n  [..] \r\n    (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTC_SetWakeUpTimer()\r\n        function. You can also configure the RTC Wakeup timer in interrupt mode \r\n        using the HAL_RTC_SetWakeUpTimer_IT() function.\r\n    (+) To read the RTC WakeUp Counter register, use the HAL_RTC_GetWakeUpTimer() \r\n        function.\r\n  \r\n  *** TimeStamp configuration ***\r\n  ===============================\r\n  [..]\r\n    (+) Enables the RTC TimeStamp using the HAL_RTC_SetTimeStamp() function.\r\n        You can also configure the RTC TimeStamp with interrupt mode using the\r\n        HAL_RTC_SetTimeStamp_IT() function.\r\n    (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp()\r\n        function.\r\n\r\n  *** Internal TimeStamp configuration ***\r\n  ===============================\r\n  [..]\r\n    (+) Enables the RTC internal TimeStamp using the HAL_RTC_SetInternalTimeStamp() function.\r\n    (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp()\r\n        function.\r\n  \r\n  *** Tamper configuration ***\r\n  ============================\r\n  [..]\r\n    (+) Enable the RTC Tamper and Configure the Tamper filter count, trigger Edge \r\n        or Level according to the Tamper filter (if equal to 0 Edge else Level) \r\n        value, sampling frequency, NoErase, MaskFlag,  precharge or discharge and\r\n        Pull-UP using the HAL_RTC_SetTamper() function. You can configure RTC Tamper\r\n        with interrupt mode using HAL_RTC_SetTamper_IT() function.\r\n    (+) The default configuration of the Tamper erases the backup registers. To avoid\r\n        erase, enable the NoErase field on the RTC_TAMPCR register.\r\n  \r\n  *** Backup Data Registers configuration ***\r\n  ===========================================\r\n  [..]\r\n    (+) To write to the RTC Backup Data registers, use the HAL_RTC_BKUPWrite()\r\n        function.  \r\n    (+) To read the RTC Backup Data registers, use the HAL_RTC_BKUPRead()\r\n        function.\r\n     \r\n   @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup RTCEx RTCEx \r\n  * @brief RTC Extended HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_RTC_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions\r\n  * @{\r\n  */\r\n  \r\n\r\n/** @defgroup RTCEx_Group1 RTC TimeStamp and Tamper functions\r\n *  @brief   RTC TimeStamp and Tamper functions\r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                 ##### RTC TimeStamp and Tamper functions #####\r\n ===============================================================================  \r\n \r\n [..] This section provides functions allowing to configure TimeStamp feature\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Sets TimeStamp.\r\n  * @note   This API must be called before enabling the TimeStamp feature. \r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  TimeStampEdge Specifies the pin edge on which the TimeStamp is \r\n  *         activated.\r\n  *          This parameter can be one of the following values:\r\n  *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the  \r\n  *                                        rising edge of the related pin.\r\n  *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the \r\n  *                                         falling edge of the related pin.\r\n  * @param  RTC_TimeStampPin specifies the RTC TimeStamp Pin.\r\n  *          This parameter can be one of the following values:\r\n  *             @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.\r\n  *             @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin.  \r\n  *             @arg RTC_TIMESTAMPPIN_PC1: PC1 is selected as RTC TimeStamp Pin.   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)\r\n{\r\n  uint32_t tmpreg = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));\r\n  assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));\r\n  \r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n  /* Get the RTC_CR register and clear the bits to be configured */\r\n  tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));\r\n    \r\n  tmpreg|= TimeStampEdge;\r\n  \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  hrtc->Instance->OR &= (uint32_t)~RTC_OR_TSINSEL;\r\n  hrtc->Instance->OR |= (uint32_t)(RTC_TimeStampPin); \r\n  \r\n  /* Configure the Time Stamp TSEDGE and Enable bits */\r\n  hrtc->Instance->CR = (uint32_t)tmpreg;\r\n  \r\n  __HAL_RTC_TIMESTAMP_ENABLE(hrtc);\r\n  \r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);    \r\n  \r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY; \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Sets TimeStamp with Interrupt. \r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @note   This API must be called before enabling the TimeStamp feature.\r\n  * @param  TimeStampEdge Specifies the pin edge on which the TimeStamp is \r\n  *         activated.\r\n  *          This parameter can be one of the following values:\r\n  *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the  \r\n  *                                        rising edge of the related pin.\r\n  *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the \r\n  *                                         falling edge of the related pin.\r\n  * @param  RTC_TimeStampPin Specifies the RTC TimeStamp Pin.\r\n  *          This parameter can be one of the following values:\r\n  *             @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.\r\n  *             @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin.  \r\n  *             @arg RTC_TIMESTAMPPIN_PC1: PC1 is selected as RTC TimeStamp Pin.   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)\r\n{\r\n  uint32_t tmpreg = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));\r\n  assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));\r\n  \r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n  /* Get the RTC_CR register and clear the bits to be configured */\r\n  tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));\r\n  \r\n  tmpreg |= TimeStampEdge;\r\n  \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  /* Configure the Time Stamp TSEDGE and Enable bits */\r\n  hrtc->Instance->CR = (uint32_t)tmpreg;\r\n  \r\n  hrtc->Instance->OR &= (uint32_t)~RTC_OR_TSINSEL;\r\n  hrtc->Instance->OR |= (uint32_t)(RTC_TimeStampPin);\r\n  \r\n  /* Clear RTC Timestamp flag */\r\n  __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);\r\n  \r\n  __HAL_RTC_TIMESTAMP_ENABLE(hrtc);\r\n  \r\n  /* Enable IT timestamp */ \r\n  __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS);\r\n  \r\n  /* RTC timestamp Interrupt Configuration: EXTI configuration */\r\n  __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();\r\n  \r\n  EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;\r\n  \r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  \r\n  \r\n  hrtc->State = HAL_RTC_STATE_READY;  \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Deactivates TimeStamp. \r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)\r\n{\r\n  uint32_t tmpreg = 0U;\r\n  \r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  /* In case of interrupt mode is used, the interrupt source must disabled */ \r\n  __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS);\r\n  \r\n  /* Get the RTC_CR register and clear the bits to be configured */\r\n  tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));\r\n  \r\n  /* Configure the Time Stamp TSEDGE and Enable bits */\r\n  hrtc->Instance->CR = (uint32_t)tmpreg;\r\n  \r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n \r\n  hrtc->State = HAL_RTC_STATE_READY;  \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Sets Internal TimeStamp.\r\n  * @note   This API must be called before enabling the internal TimeStamp feature.\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hrtc);\r\n\r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n\r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n\r\n  /* Configure the internal Time Stamp Enable bits */\r\n  __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(hrtc);\r\n\r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n\r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY;\r\n\r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Deactivates internal TimeStamp.\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hrtc);\r\n\r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n\r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n\r\n  /* Configure the internal Time Stamp Enable bits */\r\n  __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(hrtc);\r\n\r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n\r\n  hrtc->State = HAL_RTC_STATE_READY;\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hrtc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Gets the RTC TimeStamp value.\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  sTimeStamp Pointer to Time structure\r\n  * @param  sTimeStampDate Pointer to Date structure  \r\n  * @param  Format specifies the format of the entered parameters.\r\n  *          This parameter can be one of the following values:\r\n  *             FORMAT_BIN: Binary data format \r\n  *             FORMAT_BCD: BCD data format\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)\r\n{\r\n  uint32_t tmptime = 0U, tmpdate = 0U;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_FORMAT(Format));\r\n\r\n  /* Get the TimeStamp time and date registers values */\r\n  tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK);\r\n  tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK);\r\n\r\n  /* Fill the Time structure fields with the read parameters */\r\n  sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16U);\r\n  sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U);\r\n  sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));\r\n  sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16U);  \r\n  sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR;\r\n  \r\n  /* Fill the Date structure fields with the read parameters */\r\n  sTimeStampDate->Year = 0U;\r\n  sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8U);\r\n  sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));\r\n  sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13U);\r\n\r\n  /* Check the input parameters format */\r\n  if(Format == RTC_FORMAT_BIN)\r\n  {\r\n    /* Convert the TimeStamp structure parameters to Binary format */\r\n    sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);\r\n    sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes);\r\n    sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds);\r\n    \r\n    /* Convert the DateTimeStamp structure parameters to Binary format */\r\n    sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);\r\n    sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);\r\n    sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay);\r\n  }\r\n  \r\n  /* Clear the TIMESTAMP Flag */\r\n  __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);\r\n    \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Sets Tamper\r\n  * @note   By calling this API we disable the tamper interrupt for all tampers. \r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  sTamper Pointer to Tamper Structure.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)\r\n{\r\n  uint32_t tmpreg = 0U;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_TAMPER(sTamper->Tamper)); \r\n  assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));\r\n  assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));\r\n  assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));\r\n  assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));\r\n  assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));         \r\n  assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));\r\n  assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));\r\n  assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));\r\n \r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n    \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n\r\n  if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)\r\n  { \r\n    sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1U); \r\n  } \r\n  \r\n  if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)\r\n  { \r\n    sTamper->NoErase = 0;\r\n    if((sTamper->Tamper & RTC_TAMPER_1) != 0U)\r\n    {\r\n      sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE;\r\n    }\r\n    if((sTamper->Tamper & RTC_TAMPER_2) != 0U)\r\n    {\r\n      sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE;\r\n    }\r\n    if((sTamper->Tamper & RTC_TAMPER_3) != 0U)\r\n    {\r\n      sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE;\r\n    }\r\n  }\r\n\r\n  if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)\r\n  {\r\n    sTamper->MaskFlag = 0;\r\n    if((sTamper->Tamper & RTC_TAMPER_1) != 0U)\r\n    {\r\n      sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF;\r\n    }\r\n    if((sTamper->Tamper & RTC_TAMPER_2) != 0U)\r\n    {\r\n      sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF;\r\n    }\r\n    if((sTamper->Tamper & RTC_TAMPER_3) != 0U)\r\n    {\r\n      sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF;\r\n    }\r\n  }\r\n  \r\n  tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger  | (uint32_t)sTamper->NoErase |\\\r\n            (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\\\r\n            (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);\r\n\r\n  hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAMPCR_TAMPTS |\\\r\n                                       (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\\\r\n                                       (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE | (uint32_t)RTC_TAMPCR_TAMP1IE |\\\r\n                                       (uint32_t)RTC_TAMPCR_TAMP2IE | (uint32_t)RTC_TAMPCR_TAMP3IE | (uint32_t)RTC_TAMPCR_TAMP1NOERASE |\\\r\n                                       (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF |\\\r\n                                       (uint32_t)RTC_TAMPCR_TAMP2MF | (uint32_t)RTC_TAMPCR_TAMP3MF);\r\n\r\n  hrtc->Instance->TAMPCR |= tmpreg;      \r\n      \r\n  hrtc->State = HAL_RTC_STATE_READY; \r\n\r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n    \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Sets Tamper with interrupt.\r\n  * @note   By calling this API we force the tamper interrupt for all tampers.\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  sTamper Pointer to RTC Tamper.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)\r\n{\r\n  uint32_t tmpreg = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_TAMPER(sTamper->Tamper)); \r\n  assert_param(IS_RTC_TAMPER_INTERRUPT(sTamper->Interrupt));\r\n  assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));\r\n  assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));\r\n  assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));\r\n  assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));\r\n  assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));         \r\n  assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));\r\n  assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));\r\n  assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));\r\n \r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n      \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n  /* Configure the tamper trigger */\r\n  if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)\r\n  { \r\n    sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); \r\n  } \r\n  \r\n  if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)\r\n  { \r\n    sTamper->NoErase = 0;\r\n    if((sTamper->Tamper & RTC_TAMPER_1) != 0)\r\n    {\r\n      sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE;\r\n    }\r\n    if((sTamper->Tamper & RTC_TAMPER_2) != 0)\r\n    {\r\n      sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE;\r\n    }\r\n    if((sTamper->Tamper & RTC_TAMPER_3) != 0)\r\n    {\r\n      sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE;\r\n    }\r\n  }\r\n\r\n  if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)\r\n  {\r\n    sTamper->MaskFlag = 0;\r\n    if((sTamper->Tamper & RTC_TAMPER_1) != 0)\r\n    {\r\n      sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF;\r\n    }\r\n    if((sTamper->Tamper & RTC_TAMPER_2) != 0)\r\n    {\r\n      sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF;\r\n    }\r\n    if((sTamper->Tamper & RTC_TAMPER_3) != 0)\r\n    {\r\n      sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF;\r\n    }\r\n  }\r\n  \r\n  tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Interrupt | (uint32_t)sTamper->Trigger  | (uint32_t)sTamper->NoErase |\\\r\n            (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\\\r\n            (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);\r\n  \r\n  hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAMPCR_TAMPTS |\\\r\n                                       (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\\\r\n                                       (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE | (uint32_t)RTC_TAMPCR_TAMP1IE |\\\r\n                                       (uint32_t)RTC_TAMPCR_TAMP2IE | (uint32_t)RTC_TAMPCR_TAMP3IE | (uint32_t)RTC_TAMPCR_TAMP1NOERASE |\\\r\n                                       (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF |\\\r\n                                       (uint32_t)RTC_TAMPCR_TAMP2MF | (uint32_t)RTC_TAMPCR_TAMP3MF);\r\n\r\n  hrtc->Instance->TAMPCR |= tmpreg;\r\n  \r\n  if(sTamper->Tamper == RTC_TAMPER_1)\r\n  {\r\n    /* Clear RTC Tamper 1 flag */\r\n    __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);\r\n  }\r\n  else if(sTamper->Tamper == RTC_TAMPER_2)\r\n  {\r\n    /* Clear RTC Tamper 2 flag */\r\n    __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);    \r\n  }\r\n  else\r\n  {\r\n    /* Clear RTC Tamper 3 flag */\r\n    __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);  \r\n  }\r\n\r\n  /* RTC Tamper Interrupt Configuration: EXTI configuration */\r\n  __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();\r\n\r\n  EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;\r\n  \r\n  hrtc->State = HAL_RTC_STATE_READY;   \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Deactivates Tamper.\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  Tamper Selected tamper pin.\r\n  *          This parameter can be RTC_Tamper_1 and/or RTC_TAMPER_2.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)\r\n{\r\n  assert_param(IS_RTC_TAMPER(Tamper)); \r\n  \r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n      \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n/* Disable the selected Tamper pin */\r\n  hrtc->Instance->TAMPCR &= (uint32_t)~Tamper;\r\n\r\n  if ((Tamper & RTC_TAMPER_1) != 0)\r\n  {\r\n    /* Disable the Tamper1 interrupt */\r\n    hrtc->Instance->TAMPCR &= (uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP1);\r\n  }\r\n  if ((Tamper & RTC_TAMPER_2) != 0)\r\n  {\r\n    /* Disable the Tamper2 interrupt */\r\n    hrtc->Instance->TAMPCR &= (uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP2);\r\n  }\r\n  if ((Tamper & RTC_TAMPER_3) != 0)\r\n  {\r\n    /* Disable the Tamper2 interrupt */\r\n    hrtc->Instance->TAMPCR &= (uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP3);\r\n  } \r\n  \r\n  hrtc->State = HAL_RTC_STATE_READY;   \r\n  \r\n  /* Process Unlocked */  \r\n  __HAL_UNLOCK(hrtc);\r\n  \r\n  return HAL_OK; \r\n}\r\n\r\n/**\r\n  * @brief  This function handles TimeStamp interrupt request.\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @retval None\r\n  */\r\nvoid HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)\r\n{  \r\n  if(__HAL_RTC_TIMESTAMP_GET_IT(hrtc, RTC_IT_TS))\r\n  {\r\n    /* Get the status of the Interrupt */\r\n    if((uint32_t)(hrtc->Instance->CR & RTC_IT_TS) != (uint32_t)RESET)\r\n    {\r\n       /* TIMESTAMP callback */ \r\n        HAL_RTCEx_TimeStampEventCallback(hrtc);\r\n\r\n      /* Clear the TIMESTAMP interrupt pending bit */\r\n      __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc,RTC_FLAG_TSF);\r\n    }\r\n  }\r\n\r\n  /* Get the status of the Interrupt */\r\n  if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== SET)\r\n  {\r\n    /* Get the TAMPER Interrupt enable bit and pending bit */\r\n    if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \\\r\n       (((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP1IE)) != (uint32_t)RESET))\r\n    {\r\n      /* Tamper callback */\r\n      HAL_RTCEx_Tamper1EventCallback(hrtc);\r\n\r\n      /* Clear the Tamper interrupt pending bit */\r\n      __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);\r\n    }\r\n  }\r\n\r\n  /* Get the status of the Interrupt */\r\n  if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F)== SET)\r\n  {\r\n    /* Get the TAMPER Interrupt enable bit and pending bit */\r\n    if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \\\r\n       (((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP2IE)) != (uint32_t)RESET))\r\n    {\r\n      /* Tamper callback */\r\n      HAL_RTCEx_Tamper2EventCallback(hrtc);\r\n\r\n      /* Clear the Tamper interrupt pending bit */\r\n      __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);\r\n    }\r\n  }\r\n\r\n  /* Get the status of the Interrupt */\r\n  if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F)== SET)\r\n  {\r\n    /* Get the TAMPER Interrupt enable bit and pending bit */\r\n    if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \\\r\n       (((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP3IE)) != (uint32_t)RESET))\r\n    {\r\n      /* Tamper callback */\r\n      HAL_RTCEx_Tamper3EventCallback(hrtc);\r\n\r\n      /* Clear the Tamper interrupt pending bit */\r\n      __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);\r\n    }\r\n  }\r\n  \r\n  /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */\r\n  __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();\r\n\r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY;\r\n}\r\n\r\n/**\r\n  * @brief  TimeStamp callback. \r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hrtc);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_RTC_TimeStampEventCallback could be implemented in the user file\r\n  */\r\n}\r\n\r\n/**\r\n  * @brief  Tamper 1 callback. \r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hrtc);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_RTC_Tamper1EventCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Tamper 2 callback. \r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hrtc);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_RTC_Tamper2EventCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Tamper 3 callback. \r\n  * @param  hrtc RTC handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hrtc);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  This function handles TimeStamp polling request.\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  Timeout Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)\r\n{ \r\n  uint32_t tickstart = 0; \r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET)\r\n  {\t        \r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT;\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n\t\r\n  if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET)\r\n  {\r\n    /* Clear the TIMESTAMP OverRun Flag */\r\n    __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);\r\n      \r\n    /* Change TIMESTAMP state */\r\n    hrtc->State = HAL_RTC_STATE_ERROR; \r\n      \r\n    return HAL_ERROR; \r\n   }\r\n\t\r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY; \r\n  \r\n  return HAL_OK; \r\n}\r\n  \r\n/**\r\n  * @brief  This function handles Tamper1 Polling.\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  Timeout Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)\r\n{  \r\n  uint32_t tickstart = 0U; \r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  /* Get the status of the Interrupt */\r\n  while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== RESET)\r\n  {\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT;\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Clear the Tamper Flag */\r\n  __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);\r\n  \r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY;\r\n  \r\n  return HAL_OK; \r\n}\r\n\r\n/**\r\n  * @brief  This function handles Tamper2 Polling.\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  Timeout Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)\r\n{  \r\n  uint32_t tickstart = 0; \r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  /* Get the status of the Interrupt */\r\n  while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == RESET)\r\n  {\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT;\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Clear the Tamper Flag */\r\n  __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP2F);\r\n  \r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY;\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  This function handles Tamper3 Polling.\r\n  * @param  hrtc RTC handle\r\n  * @param  Timeout Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = HAL_GetTick();\r\n\r\n  /* Get the status of the Interrupt */\r\n  while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) == RESET)\r\n  {\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT;\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n\r\n  /* Clear the Tamper Flag */\r\n  __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP3F);\r\n\r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY;\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup RTCEx_Group2 RTC Wake-up functions\r\n *  @brief   RTC Wake-up functions\r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                        ##### RTC Wake-up functions #####\r\n ===============================================================================  \r\n \r\n [..] This section provides functions allowing to configure Wake-up feature\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Sets wake up timer. \r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  WakeUpCounter Wake up counter\r\n  * @param  WakeUpClock Wake up clock  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)\r\n{\r\n  uint32_t tickstart = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));\r\n  assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));\r\n \r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n    \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);\r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  /*Check RTC WUTWF flag is reset only when wake up timer enabled*/\r\n  if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)\r\n  {\r\n    /* Wait till RTC WUTWF flag is set and if Time out is reached exit */\r\n    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r\n      {\r\n        /* Enable the write protection for RTC registers */\r\n        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n      \r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT; \r\n      \r\n        /* Process Unlocked */ \r\n        __HAL_UNLOCK(hrtc);\r\n      \r\n        return HAL_TIMEOUT;\r\n      }  \r\n    }\r\n  }\r\n  \r\n  /* Clear the Wakeup Timer clock source bits in CR register */\r\n  hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;\r\n  \r\n  /* Configure the clock source */\r\n  hrtc->Instance->CR |= (uint32_t)WakeUpClock;\r\n  \r\n  /* Configure the Wakeup Timer counter */\r\n  hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;\r\n  \r\n   /* Enable the Wakeup Timer */\r\n  __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);   \r\n  \r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r\n  \r\n  hrtc->State = HAL_RTC_STATE_READY;   \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Sets wake up timer with interrupt\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  WakeUpCounter Wake up counter\r\n  * @param  WakeUpClock Wake up clock  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)\r\n{\r\n  __IO uint32_t count;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));\r\n  assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));\r\n  \r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);\r\n\r\n  /* Check RTC WUTWF flag is reset only when wake up timer enabled */\r\n  if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)\r\n  {\r\n    /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */\r\n    count = RTC_TIMEOUT_VALUE  * (SystemCoreClock / 32U / 1000U);\r\n    do\r\n    {\r\n      if(count-- == 0U)\r\n      {\r\n        /* Enable the write protection for RTC registers */\r\n        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n\r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT;\r\n\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hrtc);\r\n\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET);\r\n  }\r\n\r\n  __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);\r\n\r\n  /* Wait till RTC WUTWF flag is set and if Time out is reached exit */\r\n  count = RTC_TIMEOUT_VALUE  * (SystemCoreClock / 32U / 1000U);\r\n  do\r\n  {\r\n    if(count-- == 0U)\r\n    {\r\n      /* Enable the write protection for RTC registers */\r\n      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n\r\n      hrtc->State = HAL_RTC_STATE_TIMEOUT;\r\n\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hrtc);\r\n\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET);\r\n        \r\n  /* Configure the Wake-up Timer counter */\r\n  hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;\r\n\r\n  /* Clear the Wakeup Timer clock source bits in CR register */\r\n  hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;\r\n\r\n  /* Configure the clock source */\r\n  hrtc->Instance->CR |= (uint32_t)WakeUpClock;\r\n  \r\n  /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */\r\n  __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();\r\n  \r\n  EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT;\r\n  \r\n  /* Clear RTC Wake Up timer Flag */\r\n  __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);\r\n  \r\n  /* Configure the Interrupt in the RTC_CR register */\r\n  __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);\r\n  \r\n  /* Enable the Wakeup Timer */\r\n  __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);\r\n    \r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r\n  \r\n  hrtc->State = HAL_RTC_STATE_READY;   \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Deactivates wake up timer counter.\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC. \r\n  * @retval HAL status\r\n  */\r\nuint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)\r\n{\r\n  uint32_t tickstart = 0U;\r\n  \r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  /* Disable the Wakeup Timer */\r\n  __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);\r\n  \r\n  /* In case of interrupt mode is used, the interrupt source must disabled */ \r\n  __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT);\r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Wait till RTC WUTWF flag is set and if Time out is reached exit */\r\n  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)\r\n  {\r\n    if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r\n    {\r\n      /* Enable the write protection for RTC registers */\r\n      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n      \r\n      hrtc->State = HAL_RTC_STATE_TIMEOUT; \r\n      \r\n      /* Process Unlocked */ \r\n      __HAL_UNLOCK(hrtc);\r\n      \r\n      return HAL_TIMEOUT;\r\n    }   \r\n  }\r\n  \r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_READY;   \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Gets wake up timer counter.\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC. \r\n  * @retval Counter value\r\n  */\r\nuint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)\r\n{\r\n  /* Get the counter value */\r\n  return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT)); \r\n}\r\n\r\n/**\r\n  * @brief  This function handles Wake Up Timer interrupt request.\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @retval None\r\n  */\r\nvoid HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)\r\n{  \r\n  if(__HAL_RTC_WAKEUPTIMER_GET_IT(hrtc, RTC_IT_WUT))\r\n  {\r\n    /* Get the status of the Interrupt */\r\n    if((uint32_t)(hrtc->Instance->CR & RTC_IT_WUT) != (uint32_t)RESET)\r\n    {\r\n      /* WAKEUPTIMER callback */ \r\n      HAL_RTCEx_WakeUpTimerEventCallback(hrtc);\r\n      \r\n      /* Clear the WAKEUPTIMER interrupt pending bit */\r\n      __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);\r\n    }\r\n  }\r\n  \r\n  /* Clear the EXTI's line Flag for RTC WakeUpTimer */\r\n  __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();\r\n  \r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY;\r\n}\r\n\r\n/**\r\n  * @brief  Wake Up Timer callback.\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hrtc);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_RTC_WakeUpTimerEventCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  This function handles Wake Up Timer Polling.\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  Timeout Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)\r\n{  \r\n  uint32_t tickstart = 0; \r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET)\r\n  {\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT;\r\n      \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Clear the WAKEUPTIMER Flag */\r\n  __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);\r\n  \r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY;\r\n  \r\n  return HAL_OK; \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup RTCEx_Group3 Extension Peripheral Control functions \r\n *  @brief   Extension Peripheral Control functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n              ##### Extension Peripheral Control functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides functions allowing to\r\n      (+) Write a data in a specified RTC Backup data register\r\n      (+) Read a data in a specified RTC Backup data register\r\n      (+) Set the Coarse calibration parameters.\r\n      (+) Deactivate the Coarse calibration parameters\r\n      (+) Set the Smooth calibration parameters.\r\n      (+) Configure the Synchronization Shift Control Settings.\r\n      (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).\r\n      (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).\r\n      (+) Enable the RTC reference clock detection.\r\n      (+) Disable the RTC reference clock detection.\r\n      (+) Enable the Bypass Shadow feature.\r\n      (+) Disable the Bypass Shadow feature.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Writes a data in a specified RTC Backup data register.\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC. \r\n  * @param  BackupRegister RTC Backup data Register number.\r\n  *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to \r\n  *                                 specify the register.\r\n  * @param  Data Data to be written in the specified RTC Backup data register.                     \r\n  * @retval None\r\n  */\r\nvoid HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)\r\n{\r\n  uint32_t tmp = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_BKP(BackupRegister));\r\n  \r\n  tmp = (uint32_t)&(hrtc->Instance->BKP0R);\r\n  tmp += (BackupRegister * 4);\r\n  \r\n  /* Write the specified register */\r\n  *(__IO uint32_t *)tmp = (uint32_t)Data;\r\n}\r\n\r\n/**\r\n  * @brief  Reads data from the specified RTC Backup data Register.\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC. \r\n  * @param  BackupRegister RTC Backup data Register number.\r\n  *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to \r\n  *                                 specify the register.                   \r\n  * @retval Read value\r\n  */\r\nuint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)\r\n{\r\n  uint32_t tmp = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_BKP(BackupRegister));\r\n\r\n  tmp = (uint32_t)&(hrtc->Instance->BKP0R);\r\n  tmp += (BackupRegister * 4);\r\n  \r\n  /* Read the specified register */\r\n  return (*(__IO uint32_t *)tmp);\r\n}\r\n\r\n/**\r\n  * @brief  Sets the Smooth calibration parameters.\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.  \r\n  * @param  SmoothCalibPeriod Select the Smooth Calibration Period.\r\n  *          This parameter can be can be one of the following values :\r\n  *             @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.\r\n  *             @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.\r\n  *             @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.\r\n  * @param  SmoothCalibPlusPulses Select to Set or reset the CALP bit.\r\n  *          This parameter can be one of the following values:\r\n  *             @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulses every 2*11 pulses.\r\n  *             @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.\r\n  * @param  SmouthCalibMinusPulsesValue Select the value of CALM[80] bits.\r\n  *          This parameter can be one any value from 0 to 0x000001FF.\r\n  * @note   To deactivate the smooth calibration, the field SmoothCalibPlusPulses \r\n  *         must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field \r\n  *         SmouthCalibMinusPulsesValue must be equal to 0.  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod));\r\n  assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses));\r\n  assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmouthCalibMinusPulsesValue));\r\n  \r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  /* check if a calibration is pending*/\r\n  if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)\r\n  {\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n    /* check if a calibration is pending*/\r\n    while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r\n      {\r\n        /* Enable the write protection for RTC registers */\r\n        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n        \r\n        /* Change RTC state */\r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT; \r\n        \r\n        /* Process Unlocked */ \r\n        __HAL_UNLOCK(hrtc);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Configure the Smooth calibration settings */\r\n  hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmouthCalibMinusPulsesValue);\r\n  \r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n  \r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY; \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Configures the Synchronization Shift Control Settings.\r\n  * @note   When REFCKON is set, firmware must not write to Shift control register. \r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.    \r\n  * @param  ShiftAdd1S Select to add or not 1 second to the time calendar.\r\n  *          This parameter can be one of the following values :\r\n  *             @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. \r\n  *             @arg RTC_SHIFTADD1S_RESET: No effect.\r\n  * @param  ShiftSubFS Select the number of Second Fractions to substitute.\r\n  *          This parameter can be one any value from 0 to 0x7FFF.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)\r\n{\r\n  uint32_t tickstart = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S));\r\n  assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS));\r\n\r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n\r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n    /* Wait until the shift is completed*/\r\n    while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r\n      {  \r\n        /* Enable the write protection for RTC registers */\r\n        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  \r\n        \r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */ \r\n        __HAL_UNLOCK(hrtc);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  \r\n    /* Check if the reference clock detection is disabled */\r\n    if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET)\r\n    {\r\n      /* Configure the Shift settings */\r\n      hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S);\r\n      \r\n      /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */\r\n      if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)\r\n      {\r\n        if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)\r\n        {\r\n          /* Enable the write protection for RTC registers */\r\n          __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  \r\n          \r\n          hrtc->State = HAL_RTC_STATE_ERROR;\r\n          \r\n          /* Process Unlocked */ \r\n          __HAL_UNLOCK(hrtc);\r\n          \r\n          return HAL_ERROR;\r\n        }\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* Enable the write protection for RTC registers */\r\n      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n      \r\n      /* Change RTC state */\r\n      hrtc->State = HAL_RTC_STATE_ERROR; \r\n      \r\n      /* Process Unlocked */ \r\n      __HAL_UNLOCK(hrtc);\r\n      \r\n      return HAL_ERROR;\r\n    }\r\n  \r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n  \r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY; \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.    \r\n  * @param  CalibOutput Select the Calibration output Selection .\r\n  *          This parameter can be one of the following values:\r\n  *             @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz. \r\n  *             @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput));\r\n  \r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n\r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  /* Clear flags before config */\r\n  hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL;\r\n  \r\n  /* Configure the RTC_CR register */\r\n  hrtc->Instance->CR |= (uint32_t)CalibOutput;\r\n  \r\n  __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc);\r\n  \r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n  \r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY; \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.    \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc)\r\n{\r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc);\r\n    \r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n  \r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY; \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Enables the RTC reference clock detection.\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.    \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)\r\n{\r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  /* Set Initialization mode */\r\n  if(RTC_EnterInitMode(hrtc) != HAL_OK)\r\n  {\r\n    /* Enable the write protection for RTC registers */\r\n    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r\n    \r\n    /* Set RTC state*/\r\n    hrtc->State = HAL_RTC_STATE_ERROR;\r\n    \r\n    /* Process Unlocked */ \r\n    __HAL_UNLOCK(hrtc);\r\n    \r\n    return HAL_ERROR;\r\n  } \r\n  else\r\n  {\r\n    __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc);\r\n\r\n    /* Exit Initialization mode */\r\n    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; \r\n  }\r\n  \r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n  \r\n   /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY; \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Disable the RTC reference clock detection.\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.    \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)\r\n{ \r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  /* Set Initialization mode */\r\n  if(RTC_EnterInitMode(hrtc) != HAL_OK)\r\n  {\r\n    /* Enable the write protection for RTC registers */\r\n    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r\n    \r\n    /* Set RTC state*/\r\n    hrtc->State = HAL_RTC_STATE_ERROR;\r\n    \r\n    /* Process Unlocked */ \r\n    __HAL_UNLOCK(hrtc);\r\n    \r\n    return HAL_ERROR;\r\n  } \r\n  else\r\n  {\r\n    __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc);\r\n    \r\n    /* Exit Initialization mode */\r\n    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; \r\n  }\r\n  \r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n  \r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY; \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Enables the Bypass Shadow feature.\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.  \r\n  * @note   When the Bypass Shadow is enabled the calendar value are taken \r\n  *         directly from the Calendar counter.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc)\r\n{\r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  /* Set the BYPSHAD bit */\r\n  hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD;\r\n  \r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n  \r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY; \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Disables the Bypass Shadow feature.\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.  \r\n  * @note   When the Bypass Shadow is enabled the calendar value are taken \r\n  *         directly from the Calendar counter.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc)\r\n{\r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  /* Reset the BYPSHAD bit */\r\n  hrtc->Instance->CR &= (uint8_t)~RTC_CR_BYPSHAD;\r\n  \r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n  \r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY; \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n  /** @defgroup RTCEx_Group4 Extended features functions \r\n *  @brief    Extended features functions  \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                 ##### Extended features functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) RTC Alram B callback\r\n      (+) RTC Poll for Alarm B request\r\n               \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Alarm B callback.\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hrtc);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_RTC_AlarmBEventCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  This function handles AlarmB Polling request.\r\n  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  Timeout Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)\r\n{  \r\n  uint32_t tickstart = 0; \r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET)\r\n  {\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT;\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Clear the Alarm Flag */\r\n  __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);\r\n  \r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY; \r\n  \r\n  return HAL_OK; \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_RTC_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_sd.c\r\n  * @author  MCD Application Team\r\n  * @brief   SD card HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the Secure Digital (SD) peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + IO operation functions\r\n  *           + Peripheral Control functions \r\n  *           + SD card Control functions\r\n  *         \r\n  @verbatim\r\n  ==============================================================================\r\n                        ##### How to use this driver #####\r\n  ==============================================================================\r\n  [..]\r\n    This driver implements a high level communication layer for read and write from/to \r\n    this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by \r\n    the user in HAL_SD_MspInit() function (MSP layer).                             \r\n    Basically, the MSP layer configuration should be the same as we provide in the \r\n    examples.\r\n    You can easily tailor this configuration according to hardware resources.\r\n\r\n  [..]\r\n    This driver is a generic layered driver for SDMMC memories which uses the HAL \r\n    SDMMC driver functions to interface with SD and uSD cards devices. \r\n    It is used as follows:\r\n \r\n    (#)Initialize the SDMMC low level resources by implement the HAL_SD_MspInit() API:\r\n        (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE(); \r\n        (##) SDMMC pins configuration for SD card\r\n            (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();   \r\n            (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()\r\n                  and according to your pin assignment;\r\n        (##) DMA Configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()\r\n             and HAL_SD_WriteBlocks_DMA() APIs).\r\n            (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE(); \r\n            (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled. \r\n        (##) NVIC configuration if you need to use interrupt process when using DMA transfer.\r\n            (+++) Configure the SDMMC and DMA interrupt priorities using functions\r\n                  HAL_NVIC_SetPriority(); DMA priority is superior to SDMMC's priority\r\n            (+++) Enable the NVIC DMA and SDMMC IRQs using function HAL_NVIC_EnableIRQ()\r\n            (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT() \r\n                  and __HAL_SD_DISABLE_IT() inside the communication process.\r\n            (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_GET_IT()\r\n                  and __HAL_SD_CLEAR_IT()\r\n        (##) NVIC configuration if you need to use interrupt process (HAL_SD_ReadBlocks_IT()\r\n             and HAL_SD_WriteBlocks_IT() APIs).\r\n            (+++) Configure the SDMMC interrupt priorities using function\r\n                  HAL_NVIC_SetPriority();\r\n            (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ()\r\n            (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT() \r\n                  and __HAL_SD_DISABLE_IT() inside the communication process.\r\n            (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_GET_IT()\r\n                  and __HAL_SD_CLEAR_IT()\r\n    (#) At this stage, you can perform SD read/write/erase operations after SD card initialization  \r\n\r\n         \r\n  *** SD Card Initialization and configuration ***\r\n  ================================================    \r\n  [..]\r\n    To initialize the SD Card, use the HAL_SD_Init() function. It Initializes \r\n    SDMMC IP (STM32 side) and the SD Card, and put it into StandBy State (Ready for data transfer). \r\n    This function provide the following operations:\r\n\r\n    (#) Initialize the SDMMC peripheral interface with defaullt configuration.\r\n        The initialization process is done at 400KHz. You can change or adapt \r\n        this frequency by adjusting the \"ClockDiv\" field. \r\n        The SD Card frequency (SDMMC_CK) is computed as follows:\r\n  \r\n           SDMMC_CK = SDMMCCLK / (ClockDiv + 2)\r\n  \r\n        In initialization mode and according to the SD Card standard, \r\n        make sure that the SDMMC_CK frequency doesn't exceed 400KHz.\r\n\r\n        This phase of initialization is done through SDMMC_Init() and \r\n        SDMMC_PowerState_ON() SDMMC low level APIs.\r\n\r\n    (#) Initialize the SD card. The API used is HAL_SD_InitCard().\r\n        This phase allows the card initialization and identification \r\n        and check the SD Card type (Standard Capacity or High Capacity)\r\n        The initialization flow is compatible with SD standard.\r\n\r\n        This API (HAL_SD_InitCard()) could be used also to reinitialize the card in case \r\n        of plug-off plug-in.\r\n  \r\n    (#) Configure the SD Card Data transfer frequency. By Default, the card transfer \r\n        frequency is set to 24MHz. You can change or adapt this frequency by adjusting \r\n        the \"ClockDiv\" field.\r\n        In transfer mode and according to the SD Card standard, make sure that the \r\n        SDMMC_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.\r\n        To be able to use a frequency higher than 24MHz, you should use the SDMMC \r\n        peripheral in bypass mode. Refer to the corresponding reference manual \r\n        for more details.\r\n  \r\n    (#) Select the corresponding SD Card according to the address read with the step 2.\r\n    \r\n    (#) Configure the SD Card in wide bus mode: 4-bits data.\r\n  \r\n  *** SD Card Read operation ***\r\n  ==============================\r\n  [..] \r\n    (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks(). \r\n        This function allows the read of 512 bytes blocks.\r\n        You can choose either one block read operation or multiple block read operation \r\n        by adjusting the \"NumberOfBlocks\" parameter.\r\n        After this, you have to ensure that the transfer is done correctly. The check is done\r\n        through HAL_SD_GetCardState() function for SD card state.\r\n\r\n    (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().\r\n        This function allows the read of 512 bytes blocks.\r\n        You can choose either one block read operation or multiple block read operation \r\n        by adjusting the \"NumberOfBlocks\" parameter.\r\n        After this, you have to ensure that the transfer is done correctly. The check is done\r\n        through HAL_SD_GetCardState() function for SD card state.\r\n        You could also check the DMA transfer process through the SD Rx interrupt event.\r\n\r\n    (+) You can read from SD card in Interrupt mode by using function HAL_SD_ReadBlocks_IT().\r\n        This function allows the read of 512 bytes blocks.\r\n        You can choose either one block read operation or multiple block read operation \r\n        by adjusting the \"NumberOfBlocks\" parameter.\r\n        After this, you have to ensure that the transfer is done correctly. The check is done\r\n        through HAL_SD_GetCardState() function for SD card state.\r\n        You could also check the IT transfer process through the SD Rx interrupt event.\r\n  \r\n  *** SD Card Write operation ***\r\n  =============================== \r\n  [..] \r\n    (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks(). \r\n        This function allows the read of 512 bytes blocks.\r\n        You can choose either one block read operation or multiple block read operation \r\n        by adjusting the \"NumberOfBlocks\" parameter.\r\n        After this, you have to ensure that the transfer is done correctly. The check is done\r\n        through HAL_SD_GetCardState() function for SD card state.\r\n\r\n    (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().\r\n        This function allows the read of 512 bytes blocks.\r\n        You can choose either one block read operation or multiple block read operation \r\n        by adjusting the \"NumberOfBlocks\" parameter.\r\n        After this, you have to ensure that the transfer is done correctly. The check is done\r\n        through HAL_SD_GetCardState() function for SD card state.\r\n        You could also check the DMA transfer process through the SD Tx interrupt event.  \r\n\r\n    (+) You can write to SD card in Interrupt mode by using function HAL_SD_WriteBlocks_IT().\r\n        This function allows the read of 512 bytes blocks.\r\n        You can choose either one block read operation or multiple block read operation \r\n        by adjusting the \"NumberOfBlocks\" parameter.\r\n        After this, you have to ensure that the transfer is done correctly. The check is done\r\n        through HAL_SD_GetCardState() function for SD card state.\r\n        You could also check the IT transfer process through the SD Tx interrupt event.\r\n  \r\n  *** SD card status ***\r\n  ====================== \r\n  [..]\r\n    (+) The SD Status contains status bits that are related to the SD Memory \r\n        Card proprietary features. To get SD card status use the HAL_SD_GetCardStatus().\r\n\r\n  *** SD card information ***\r\n  =========================== \r\n  [..]\r\n    (+) To get SD card information, you can use the function HAL_SD_GetCardInfo().\r\n        It returns useful information about the SD card such as block size, card type,\r\n        block number ...\r\n\r\n  *** SD card CSD register ***\r\n  ============================\r\n  [..]\r\n    (+) The HAL_SD_GetCardCSD() API allows to get the parameters of the CSD register.\r\n        Some of the CSD parameters are useful for card initialization and identification.\r\n\r\n  *** SD card CID register ***\r\n  ============================\r\n  [..]\r\n    (+) The HAL_SD_GetCardCID() API allows to get the parameters of the CID register.\r\n        Some of the CSD parameters are useful for card initialization and identification.\r\n\r\n  *** SD HAL driver macros list ***\r\n  ==================================\r\n  [..]\r\n    Below the list of most used macros in SD HAL driver.\r\n       \r\n    (+) __HAL_SD_ENABLE : Enable the SD device\r\n    (+) __HAL_SD_DISABLE : Disable the SD device\r\n    (+) __HAL_SD_DMA_ENABLE: Enable the SDMMC DMA transfer\r\n    (+) __HAL_SD_DMA_DISABLE: Disable the SDMMC DMA transfer\r\n    (+) __HAL_SD_ENABLE_IT: Enable the SD device interrupt\r\n    (+) __HAL_SD_DISABLE_IT: Disable the SD device interrupt\r\n    (+) __HAL_SD_GET_FLAG:Check whether the specified SD flag is set or not\r\n    (+) __HAL_SD_CLEAR_FLAG: Clear the SD's pending flags\r\n\r\n  [..]\r\n    (@) You can refer to the SD HAL driver header file for more useful macros \r\n      \r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup SD \r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_SD_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @addtogroup SD_Private_Defines\r\n  * @{\r\n  */\r\n    \r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup SD_Private_Functions SD Private Functions\r\n  * @{\r\n  */\r\nstatic uint32_t SD_InitCard(SD_HandleTypeDef *hsd);\r\nstatic uint32_t SD_PowerON(SD_HandleTypeDef *hsd);                      \r\nstatic uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);\r\nstatic uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus);\r\nstatic uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd);\r\nstatic uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd);\r\nstatic uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR);\r\nstatic HAL_StatusTypeDef SD_PowerOFF(SD_HandleTypeDef *hsd);\r\nstatic HAL_StatusTypeDef SD_Write_IT(SD_HandleTypeDef *hsd);\r\nstatic HAL_StatusTypeDef SD_Read_IT(SD_HandleTypeDef *hsd);\r\nstatic void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma);\r\nstatic void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);\r\nstatic void SD_DMAError(DMA_HandleTypeDef *hdma);\r\nstatic void SD_DMATxAbort(DMA_HandleTypeDef *hdma);\r\nstatic void SD_DMARxAbort(DMA_HandleTypeDef *hdma);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup SD_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup SD_Exported_Functions_Group1\r\n *  @brief   Initialization and de-initialization functions \r\n *\r\n@verbatim    \r\n  ==============================================================================\r\n          ##### Initialization and de-initialization functions #####\r\n  ==============================================================================\r\n  [..]  \r\n    This section provides functions allowing to initialize/de-initialize the SD\r\n    card device to be ready for use.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the SD according to the specified parameters in the \r\n            SD_HandleTypeDef and create the associated handle.\r\n  * @param  hsd Pointer to the SD handle  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)\r\n{\r\n  /* Check the SD handle allocation */\r\n  if(hsd == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_SDMMC_ALL_INSTANCE(hsd->Instance));\r\n  assert_param(IS_SDMMC_CLOCK_EDGE(hsd->Init.ClockEdge));\r\n  assert_param(IS_SDMMC_CLOCK_BYPASS(hsd->Init.ClockBypass));\r\n  assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave));\r\n  assert_param(IS_SDMMC_BUS_WIDE(hsd->Init.BusWide));\r\n  assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl));\r\n  assert_param(IS_SDMMC_CLKDIV(hsd->Init.ClockDiv));\r\n\r\n  if(hsd->State == HAL_SD_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    hsd->Lock = HAL_UNLOCKED;\r\n    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */\r\n    HAL_SD_MspInit(hsd);\r\n  }\r\n\r\n  hsd->State = HAL_SD_STATE_BUSY;\r\n\r\n  /* Initialize the Card parameters */\r\n  HAL_SD_InitCard(hsd);\r\n\r\n  /* Initialize the error code */\r\n  hsd->ErrorCode = HAL_DMA_ERROR_NONE;\r\n  \r\n  /* Initialize the SD operation */\r\n  hsd->Context = SD_CONTEXT_NONE;\r\n                                                                                     \r\n  /* Initialize the SD state */\r\n  hsd->State = HAL_SD_STATE_READY;\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the SD Card.\r\n  * @param  hsd Pointer to SD handle\r\n  * @note   This function initializes the SD card. It could be used when a card \r\n            re-initialization is needed.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)\r\n{\r\n  uint32_t errorstate = HAL_SD_ERROR_NONE;\r\n  SD_InitTypeDef Init;\r\n  \r\n  /* Default SDMMC peripheral configuration for SD card initialization */\r\n  Init.ClockEdge           = SDMMC_CLOCK_EDGE_RISING;\r\n  Init.ClockBypass         = SDMMC_CLOCK_BYPASS_DISABLE;\r\n  Init.ClockPowerSave      = SDMMC_CLOCK_POWER_SAVE_DISABLE;\r\n  Init.BusWide             = SDMMC_BUS_WIDE_1B;\r\n  Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;\r\n  Init.ClockDiv            = SDMMC_INIT_CLK_DIV;\r\n\r\n  /* Initialize SDMMC peripheral interface with default configuration */\r\n  SDMMC_Init(hsd->Instance, Init);\r\n\r\n  /* Disable SDMMC Clock */\r\n  __HAL_SD_DISABLE(hsd); \r\n  \r\n  /* Set Power State to ON */\r\n  SDMMC_PowerState_ON(hsd->Instance);\r\n  \r\n  /* Enable SDMMC Clock */\r\n  __HAL_SD_ENABLE(hsd);\r\n  \r\n  /* Required power up waiting time before starting the SD initialization sequence */\r\n  HAL_Delay(2);\r\n  \r\n  /* Identify card operating voltage */\r\n  errorstate = SD_PowerON(hsd);\r\n  if(errorstate != HAL_SD_ERROR_NONE)\r\n  {\r\n    hsd->State = HAL_SD_STATE_READY;\r\n    hsd->ErrorCode |= errorstate;\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Card initialization */\r\n  errorstate = SD_InitCard(hsd);\r\n  if(errorstate != HAL_SD_ERROR_NONE)\r\n  {\r\n    hsd->State = HAL_SD_STATE_READY;\r\n    hsd->ErrorCode |= errorstate;\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  De-Initializes the SD card.\r\n  * @param  hsd Pointer to SD handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)\r\n{\r\n  /* Check the SD handle allocation */\r\n  if(hsd == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_SDMMC_ALL_INSTANCE(hsd->Instance));\r\n\r\n  hsd->State = HAL_SD_STATE_BUSY;\r\n  \r\n  /* Set SD power state to off */ \r\n  SD_PowerOFF(hsd);\r\n  \r\n  /* De-Initialize the MSP layer */\r\n  HAL_SD_MspDeInit(hsd);\r\n  \r\n  hsd->ErrorCode = HAL_SD_ERROR_NONE;\r\n  hsd->State = HAL_SD_STATE_RESET;\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Initializes the SD MSP.\r\n  * @param  hsd Pointer to SD handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hsd);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_SD_MspInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  De-Initialize SD MSP.\r\n  * @param  hsd Pointer to SD handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hsd);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_SD_MspDeInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup SD_Exported_Functions_Group2\r\n *  @brief   Data transfer functions \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                        ##### IO operation functions #####\r\n  ==============================================================================  \r\n  [..]\r\n    This subsection provides a set of functions allowing to manage the data \r\n    transfer from/to SD card.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Reads block(s) from a specified address in a card. The Data transfer \r\n  *         is managed by polling mode.\r\n  * @note   This API should be followed by a check on the card state through\r\n  *         HAL_SD_GetCardState().\r\n  * @param  hsd Pointer to SD handle\r\n  * @param  pData pointer to the buffer that will contain the received data\r\n  * @param  BlockAdd Block Address from where data is to be read \r\n  * @param  NumberOfBlocks Number of SD blocks to read\r\n  * @param  Timeout Specify timeout value\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)\r\n{\r\n  SDMMC_DataInitTypeDef config;\r\n  uint32_t errorstate = HAL_SD_ERROR_NONE;\r\n  uint32_t tickstart = HAL_GetTick();\r\n  uint32_t count = 0, *tempbuff = (uint32_t *)pData;\r\n  \r\n  if(NULL == pData)\r\n  {\r\n    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;\r\n    return HAL_ERROR;\r\n  }\r\n \r\n  if(hsd->State == HAL_SD_STATE_READY)\r\n  {\r\n    hsd->ErrorCode = HAL_DMA_ERROR_NONE;\r\n    \r\n    if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))\r\n    {\r\n      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;\r\n      return HAL_ERROR;\r\n    }\r\n    \r\n    hsd->State = HAL_SD_STATE_BUSY;\r\n    \r\n    /* Initialize data control register */\r\n    hsd->Instance->DCTRL = 0;\r\n    \r\n    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)\r\n    {\r\n      BlockAdd *= 512;\r\n    }\r\n      \r\n    /* Set Block Size for Card */\r\n    errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);\r\n    if(errorstate != HAL_SD_ERROR_NONE)\r\n    {\r\n      /* Clear all the static flags */\r\n      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);      \r\n      hsd->ErrorCode |= errorstate;\r\n      hsd->State = HAL_SD_STATE_READY;\r\n      return HAL_ERROR;\r\n    }\r\n    \r\n    /* Configure the SD DPSM (Data Path State Machine) */\r\n    config.DataTimeOut   = SDMMC_DATATIMEOUT;\r\n    config.DataLength    = NumberOfBlocks * BLOCKSIZE;\r\n    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;\r\n    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;\r\n    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;\r\n    config.DPSM          = SDMMC_DPSM_ENABLE;\r\n    SDMMC_ConfigData(hsd->Instance, &config);\r\n    \r\n    /* Read block(s) in polling mode */\r\n    if(NumberOfBlocks > 1)\r\n    {\r\n      hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK;\r\n      \r\n      /* Read Multi Block command */ \r\n      errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd);\r\n    }\r\n    else\r\n    {\r\n      hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK;\r\n      \r\n      /* Read Single Block command */\r\n      errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd);\r\n    }\r\n    if(errorstate != HAL_SD_ERROR_NONE)\r\n    {\r\n      /* Clear all the static flags */\r\n      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r\n      hsd->ErrorCode |= errorstate;\r\n      hsd->State = HAL_SD_STATE_READY;\r\n      return HAL_ERROR;\r\n    }\r\n      \r\n    /* Poll on SDMMC flags */\r\n    while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))\r\n    {\r\n      if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))\r\n      {\r\n        /* Read data from SDMMC Rx FIFO */\r\n        for(count = 0U; count < 8U; count++)\r\n        {\r\n          *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance);\r\n        }\r\n        tempbuff += 8U;\r\n      }\r\n      \r\n      if((Timeout == 0U)||((HAL_GetTick()-tickstart) >=  Timeout))\r\n      {\r\n        /* Clear all the static flags */\r\n        __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r\n        hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;\r\n        hsd->State= HAL_SD_STATE_READY;\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n    \r\n    /* Send stop transmission command in case of multiblock read */\r\n    if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))\r\n    {    \r\n      if(hsd->SdCard.CardType != CARD_SECURED)\r\n      {\r\n        /* Send stop transmission command */\r\n        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);\r\n        if(errorstate != HAL_SD_ERROR_NONE)\r\n        {\r\n          /* Clear all the static flags */\r\n          __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r\n          hsd->ErrorCode |= errorstate;\r\n          hsd->State = HAL_SD_STATE_READY;\r\n          return HAL_ERROR;\r\n        }\r\n      }\r\n    }\r\n    \r\n    /* Get error state */\r\n    if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))\r\n    {\r\n      /* Clear all the static flags */\r\n      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r\n      hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;\r\n      hsd->State = HAL_SD_STATE_READY;\r\n      return HAL_ERROR;\r\n    }\r\n    else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))\r\n    {\r\n      /* Clear all the static flags */\r\n      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r\n      hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;\r\n      hsd->State = HAL_SD_STATE_READY;\r\n      return HAL_ERROR;\r\n    }\r\n    else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))\r\n    {\r\n      /* Clear all the static flags */\r\n      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r\n      hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;\r\n      hsd->State = HAL_SD_STATE_READY;\r\n      return HAL_ERROR;\r\n    }\r\n    \r\n    /* Empty FIFO if there is still any data */\r\n    while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)))\r\n    {\r\n      *tempbuff = SDMMC_ReadFIFO(hsd->Instance);\r\n      tempbuff++;\r\n      \r\n      if((Timeout == 0U)||((HAL_GetTick()-tickstart) >=  Timeout))\r\n      {\r\n        /* Clear all the static flags */\r\n        __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);        \r\n        hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;\r\n        hsd->State= HAL_SD_STATE_READY;\r\n        return HAL_ERROR;\r\n      }\r\n    }\r\n    \r\n    /* Clear all the static flags */\r\n    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r\n    \r\n    hsd->State = HAL_SD_STATE_READY;\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    hsd->ErrorCode |= HAL_SD_ERROR_BUSY;\r\n    return HAL_ERROR;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Allows to write block(s) to a specified address in a card. The Data\r\n  *         transfer is managed by polling mode.\r\n  * @note   This API should be followed by a check on the card state through\r\n  *         HAL_SD_GetCardState().\r\n  * @param  hsd Pointer to SD handle\r\n  * @param  pData pointer to the buffer that will contain the data to transmit\r\n  * @param  BlockAdd Block Address where data will be written  \r\n  * @param  NumberOfBlocks Number of SD blocks to write\r\n  * @param  Timeout Specify timeout value\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)\r\n{\r\n  SDMMC_DataInitTypeDef config;\r\n  uint32_t errorstate = HAL_SD_ERROR_NONE;\r\n  uint32_t tickstart = HAL_GetTick();\r\n  uint32_t count = 0;\r\n  uint32_t *tempbuff = (uint32_t *)pData;\r\n  \r\n  if(NULL == pData)\r\n  {\r\n    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  if(hsd->State == HAL_SD_STATE_READY)\r\n  {\r\n    hsd->ErrorCode = HAL_DMA_ERROR_NONE;\r\n    \r\n    if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))\r\n    {\r\n      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;\r\n      return HAL_ERROR;\r\n    }\r\n    \r\n    hsd->State = HAL_SD_STATE_BUSY;\r\n    \r\n    /* Initialize data control register */\r\n    hsd->Instance->DCTRL = 0;\r\n     \r\n    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)\r\n    {\r\n      BlockAdd *= 512;\r\n    }\r\n    \r\n    /* Set Block Size for Card */ \r\n    errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);\r\n    if(errorstate != HAL_SD_ERROR_NONE)\r\n    {\r\n      /* Clear all the static flags */\r\n      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);  \r\n      hsd->ErrorCode |= errorstate;\r\n      hsd->State = HAL_SD_STATE_READY;\r\n      return HAL_ERROR;\r\n    }\r\n    \r\n    /* Write Blocks in Polling mode */\r\n    if(NumberOfBlocks > 1U)\r\n    {\r\n      hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK;\r\n      \r\n      /* Write Multi Block command */ \r\n      errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd);\r\n    }\r\n    else\r\n    {\r\n      hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK;\r\n      \r\n      /* Write Single Block command */\r\n      errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd);\r\n    }\r\n    if(errorstate != HAL_SD_ERROR_NONE)\r\n    {\r\n      /* Clear all the static flags */\r\n      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);  \r\n      hsd->ErrorCode |= errorstate;\r\n      hsd->State = HAL_SD_STATE_READY;\r\n      return HAL_ERROR;\r\n    }\r\n    \r\n    /* Configure the SD DPSM (Data Path State Machine) */ \r\n    config.DataTimeOut   = SDMMC_DATATIMEOUT;\r\n    config.DataLength    = NumberOfBlocks * BLOCKSIZE;\r\n    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;\r\n    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;\r\n    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;\r\n    config.DPSM          = SDMMC_DPSM_ENABLE;\r\n    SDMMC_ConfigData(hsd->Instance, &config);\r\n    \r\n    /* Write block(s) in polling mode */\r\n    while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))\r\n    {\r\n      if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE))\r\n      {\r\n        /* Write data to SDMMC Tx FIFO */\r\n        for(count = 0U; count < 8U; count++)\r\n        {\r\n          SDMMC_WriteFIFO(hsd->Instance, (tempbuff + count));\r\n        }\r\n        tempbuff += 8U;\r\n      }\r\n      \r\n      if((Timeout == 0U)||((HAL_GetTick()-tickstart) >=  Timeout))\r\n      {\r\n        /* Clear all the static flags */\r\n        __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);  \r\n        hsd->ErrorCode |= errorstate;\r\n        hsd->State = HAL_SD_STATE_READY;\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n    \r\n    /* Send stop transmission command in case of multiblock write */\r\n    if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))\r\n    { \r\n      if(hsd->SdCard.CardType != CARD_SECURED)\r\n      {\r\n        /* Send stop transmission command */\r\n        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);\r\n        if(errorstate != HAL_SD_ERROR_NONE)\r\n        {\r\n          /* Clear all the static flags */\r\n          __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);  \r\n          hsd->ErrorCode |= errorstate;\r\n          hsd->State = HAL_SD_STATE_READY;\r\n          return HAL_ERROR;\r\n        }\r\n      }\r\n    }\r\n    \r\n    /* Get error state */\r\n    if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))\r\n    {\r\n      /* Clear all the static flags */\r\n      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r\n      hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;\r\n      hsd->State = HAL_SD_STATE_READY;\r\n      return HAL_ERROR;\r\n    }\r\n    else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))\r\n    {\r\n      /* Clear all the static flags */\r\n      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r\n      hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;      \r\n      hsd->State = HAL_SD_STATE_READY;\r\n      return HAL_ERROR;\r\n    }\r\n    else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR))\r\n    {\r\n      /* Clear all the static flags */\r\n      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r\n      hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;\r\n      hsd->State = HAL_SD_STATE_READY;\r\n      return HAL_ERROR;\r\n    }\r\n    \r\n    /* Clear all the static flags */\r\n    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r\n    \r\n    hsd->State = HAL_SD_STATE_READY;\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    hsd->ErrorCode |= HAL_SD_ERROR_BUSY;\r\n    return HAL_ERROR;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Reads block(s) from a specified address in a card. The Data transfer \r\n  *         is managed in interrupt mode. \r\n  * @note   This API should be followed by a check on the card state through\r\n  *         HAL_SD_GetCardState().\r\n  * @note   You could also check the IT transfer process through the SD Rx \r\n  *         interrupt event.\r\n  * @param  hsd Pointer to SD handle                 \r\n  * @param  pData Pointer to the buffer that will contain the received data\r\n  * @param  BlockAdd Block Address from where data is to be read \r\n  * @param  NumberOfBlocks Number of blocks to read.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)\r\n{\r\n  SDMMC_DataInitTypeDef config;\r\n  uint32_t errorstate = HAL_SD_ERROR_NONE;\r\n  \r\n  if(NULL == pData)\r\n  {\r\n    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  if(hsd->State == HAL_SD_STATE_READY)\r\n  {\r\n    hsd->ErrorCode = HAL_DMA_ERROR_NONE;\r\n    \r\n    if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))\r\n    {\r\n      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;\r\n      return HAL_ERROR;\r\n    }\r\n    \r\n    hsd->State = HAL_SD_STATE_BUSY;\r\n    \r\n    /* Initialize data control register */\r\n    hsd->Instance->DCTRL = 0U;\r\n    \r\n    hsd->pRxBuffPtr = (uint32_t *)pData;\r\n    hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;\r\n    \r\n    __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_RXFIFOHF));\r\n    \r\n    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)\r\n    {\r\n      BlockAdd *= 512U;\r\n    }\r\n    \r\n    /* Configure the SD DPSM (Data Path State Machine) */ \r\n    config.DataTimeOut   = SDMMC_DATATIMEOUT;\r\n    config.DataLength    = BLOCKSIZE * NumberOfBlocks;\r\n    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;\r\n    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;\r\n    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;\r\n    config.DPSM          = SDMMC_DPSM_ENABLE;\r\n    SDMMC_ConfigData(hsd->Instance, &config);\r\n    \r\n    /* Set Block Size for Card */ \r\n    errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);\r\n    if(errorstate != HAL_SD_ERROR_NONE)\r\n    {\r\n      /* Clear all the static flags */\r\n      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); \r\n      hsd->ErrorCode |= errorstate;\r\n      hsd->State = HAL_SD_STATE_READY;\r\n      return HAL_ERROR;\r\n    }\r\n\r\n    /* Read Blocks in IT mode */\r\n    if(NumberOfBlocks > 1U)\r\n    {\r\n      hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT);\r\n      \r\n      /* Read Multi Block command */\r\n      errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd);\r\n    }\r\n    else\r\n    {\r\n      hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_IT);\r\n      \r\n      /* Read Single Block command */\r\n      errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd);\r\n    }\r\n    if(errorstate != HAL_SD_ERROR_NONE)\r\n    {\r\n      /* Clear all the static flags */\r\n      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); \r\n      hsd->ErrorCode |= errorstate;\r\n      hsd->State = HAL_SD_STATE_READY;\r\n      return HAL_ERROR;\r\n    }\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Writes block(s) to a specified address in a card. The Data transfer \r\n  *         is managed in interrupt mode. \r\n  * @note   This API should be followed by a check on the card state through\r\n  *         HAL_SD_GetCardState().\r\n  * @note   You could also check the IT transfer process through the SD Tx \r\n  *         interrupt event. \r\n  * @param  hsd Pointer to SD handle\r\n  * @param  pData Pointer to the buffer that will contain the data to transmit\r\n  * @param  BlockAdd Block Address where data will be written    \r\n  * @param  NumberOfBlocks Number of blocks to write\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)\r\n{\r\n  SDMMC_DataInitTypeDef config;\r\n  uint32_t errorstate = HAL_SD_ERROR_NONE;\r\n  \r\n  if(NULL == pData)\r\n  {\r\n    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  if(hsd->State == HAL_SD_STATE_READY)\r\n  {\r\n    hsd->ErrorCode = HAL_DMA_ERROR_NONE;\r\n    \r\n    if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))\r\n    {\r\n      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;\r\n      return HAL_ERROR;\r\n    }\r\n    \r\n    hsd->State = HAL_SD_STATE_BUSY;\r\n    \r\n    /* Initialize data control register */\r\n    hsd->Instance->DCTRL = 0U;\r\n    \r\n    hsd->pTxBuffPtr = (uint32_t *)pData;\r\n    hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;\r\n    \r\n    /* Enable transfer interrupts */\r\n    __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_TXFIFOHE)); \r\n    \r\n    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)\r\n    {\r\n      BlockAdd *= 512U;\r\n    }\r\n    \r\n    /* Set Block Size for Card */ \r\n    errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);\r\n    if(errorstate != HAL_SD_ERROR_NONE)\r\n    {\r\n      /* Clear all the static flags */\r\n      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); \r\n      hsd->ErrorCode |= errorstate;\r\n      hsd->State = HAL_SD_STATE_READY;\r\n      return HAL_ERROR;\r\n    }\r\n    \r\n    /* Write Blocks in Polling mode */\r\n    if(NumberOfBlocks > 1U)\r\n    {\r\n      hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK| SD_CONTEXT_IT);\r\n      \r\n      /* Write Multi Block command */ \r\n      errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd);\r\n    }\r\n    else\r\n    {\r\n      hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_IT);\r\n      \r\n      /* Write Single Block command */ \r\n      errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd);\r\n    }\r\n    if(errorstate != HAL_SD_ERROR_NONE)\r\n    {\r\n      /* Clear all the static flags */\r\n      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); \r\n      hsd->ErrorCode |= errorstate;\r\n      hsd->State = HAL_SD_STATE_READY;\r\n      return HAL_ERROR;\r\n    }\r\n    \r\n    /* Configure the SD DPSM (Data Path State Machine) */ \r\n    config.DataTimeOut   = SDMMC_DATATIMEOUT;\r\n    config.DataLength    = BLOCKSIZE * NumberOfBlocks;\r\n    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;\r\n    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;\r\n    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;\r\n    config.DPSM          = SDMMC_DPSM_ENABLE;\r\n    SDMMC_ConfigData(hsd->Instance, &config);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Reads block(s) from a specified address in a card. The Data transfer \r\n  *         is managed by DMA mode. \r\n  * @note   This API should be followed by a check on the card state through\r\n  *         HAL_SD_GetCardState().\r\n  * @note   You could also check the DMA transfer process through the SD Rx \r\n  *         interrupt event.\r\n  * @param  hsd Pointer SD handle                 \r\n  * @param  pData Pointer to the buffer that will contain the received data\r\n  * @param  BlockAdd Block Address from where data is to be read  \r\n  * @param  NumberOfBlocks Number of blocks to read.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)\r\n{\r\n  SDMMC_DataInitTypeDef config;\r\n  uint32_t errorstate = HAL_SD_ERROR_NONE;\r\n  \r\n  if(NULL == pData)\r\n  {\r\n    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  if(hsd->State == HAL_SD_STATE_READY)\r\n  {\r\n    hsd->ErrorCode = HAL_DMA_ERROR_NONE;\r\n    \r\n    if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))\r\n    {\r\n      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;\r\n      return HAL_ERROR;\r\n    }\r\n    \r\n    hsd->State = HAL_SD_STATE_BUSY;\r\n    \r\n    /* Initialize data control register */\r\n    hsd->Instance->DCTRL = 0U;\r\n    \r\n    __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND));\r\n    \r\n    /* Set the DMA transfer complete callback */\r\n    hsd->hdmarx->XferCpltCallback = SD_DMAReceiveCplt;\r\n    \r\n    /* Set the DMA error callback */\r\n    hsd->hdmarx->XferErrorCallback = SD_DMAError;\r\n    \r\n    /* Set the DMA Abort callback */\r\n    hsd->hdmarx->XferAbortCallback = NULL;\r\n    \r\n    /* Enable the DMA Channel */\r\n    HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4);\r\n    \r\n    /* Enable SD DMA transfer */\r\n    __HAL_SD_DMA_ENABLE(hsd);\r\n    \r\n    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)\r\n    {\r\n      BlockAdd *= 512U;\r\n    }\r\n    \r\n    /* Configure the SD DPSM (Data Path State Machine) */ \r\n    config.DataTimeOut   = SDMMC_DATATIMEOUT;\r\n    config.DataLength    = BLOCKSIZE * NumberOfBlocks;\r\n    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;\r\n    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;\r\n    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;\r\n    config.DPSM          = SDMMC_DPSM_ENABLE;\r\n    SDMMC_ConfigData(hsd->Instance, &config);\r\n\r\n    /* Set Block Size for Card */ \r\n    errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);\r\n    if(errorstate != HAL_SD_ERROR_NONE)\r\n    {\r\n      /* Clear all the static flags */\r\n      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); \r\n      hsd->ErrorCode |= errorstate;\r\n      hsd->State = HAL_SD_STATE_READY;\r\n      return HAL_ERROR;\r\n    }\r\n        \r\n    /* Read Blocks in DMA mode */\r\n    if(NumberOfBlocks > 1U)\r\n    {\r\n      hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);\r\n      \r\n      /* Read Multi Block command */ \r\n      errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd);\r\n    }\r\n    else\r\n    {\r\n      hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA);\r\n      \r\n      /* Read Single Block command */ \r\n      errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd);\r\n    }\r\n    if(errorstate != HAL_SD_ERROR_NONE)\r\n    {\r\n      /* Clear all the static flags */\r\n      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); \r\n      hsd->ErrorCode |= errorstate;\r\n      hsd->State = HAL_SD_STATE_READY;\r\n      return HAL_ERROR;\r\n    }\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Writes block(s) to a specified address in a card. The Data transfer \r\n  *         is managed by DMA mode. \r\n  * @note   This API should be followed by a check on the card state through\r\n  *         HAL_SD_GetCardState().\r\n  * @note   You could also check the DMA transfer process through the SD Tx \r\n  *         interrupt event.\r\n  * @param  hsd Pointer to SD handle\r\n  * @param  pData Pointer to the buffer that will contain the data to transmit\r\n  * @param  BlockAdd Block Address where data will be written  \r\n  * @param  NumberOfBlocks Number of blocks to write\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)\r\n{\r\n  SDMMC_DataInitTypeDef config;\r\n  uint32_t errorstate = HAL_SD_ERROR_NONE;\r\n  \r\n  if(NULL == pData)\r\n  {\r\n    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  if(hsd->State == HAL_SD_STATE_READY)\r\n  {\r\n    hsd->ErrorCode = HAL_DMA_ERROR_NONE;\r\n    \r\n    if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))\r\n    {\r\n      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;\r\n      return HAL_ERROR;\r\n    }\r\n    \r\n    hsd->State = HAL_SD_STATE_BUSY;\r\n    \r\n    /* Initialize data control register */\r\n    hsd->Instance->DCTRL = 0U;\r\n    \r\n    /* Enable SD Error interrupts */\r\n    __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR));    \r\n    \r\n    /* Set the DMA transfer complete callback */\r\n    hsd->hdmatx->XferCpltCallback = SD_DMATransmitCplt;\r\n    \r\n    /* Set the DMA error callback */\r\n    hsd->hdmatx->XferErrorCallback = SD_DMAError;\r\n    \r\n    /* Set the DMA Abort callback */\r\n    hsd->hdmatx->XferAbortCallback = NULL;\r\n    \r\n    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)\r\n    {\r\n      BlockAdd *= 512U;\r\n    }\r\n    \r\n    /* Set Block Size for Card */ \r\n    errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);\r\n    if(errorstate != HAL_SD_ERROR_NONE)\r\n    {\r\n      /* Clear all the static flags */\r\n      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); \r\n      hsd->ErrorCode |= errorstate;\r\n      hsd->State = HAL_SD_STATE_READY;\r\n      return HAL_ERROR;\r\n    }\r\n    \r\n    /* Write Blocks in Polling mode */\r\n    if(NumberOfBlocks > 1U)\r\n    {\r\n      hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);\r\n      \r\n      /* Write Multi Block command */ \r\n      errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd);\r\n    }\r\n    else\r\n    {\r\n      hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_DMA);\r\n      \r\n      /* Write Single Block command */\r\n      errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd);\r\n    }\r\n    if(errorstate != HAL_SD_ERROR_NONE)\r\n    {\r\n      /* Clear all the static flags */\r\n      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); \r\n      hsd->ErrorCode |= errorstate;\r\n      hsd->State = HAL_SD_STATE_READY;\r\n      return HAL_ERROR;\r\n    }\r\n    \r\n    /* Enable SDMMC DMA transfer */\r\n    __HAL_SD_DMA_ENABLE(hsd);\r\n    \r\n    /* Enable the DMA Channel */\r\n    HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4);\r\n    \r\n    /* Configure the SD DPSM (Data Path State Machine) */ \r\n    config.DataTimeOut   = SDMMC_DATATIMEOUT;\r\n    config.DataLength    = BLOCKSIZE * NumberOfBlocks;\r\n    config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;\r\n    config.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;\r\n    config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;\r\n    config.DPSM          = SDMMC_DPSM_ENABLE;\r\n    SDMMC_ConfigData(hsd->Instance, &config);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Erases the specified memory area of the given SD card.\r\n  * @note   This API should be followed by a check on the card state through\r\n  *         HAL_SD_GetCardState().\r\n  * @param  hsd Pointer to SD handle \r\n  * @param  BlockStartAdd Start Block address\r\n  * @param  BlockEndAdd End Block address\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd)\r\n{\r\n  uint32_t errorstate = HAL_SD_ERROR_NONE;\r\n  \r\n  if(hsd->State == HAL_SD_STATE_READY)\r\n  {\r\n    hsd->ErrorCode = HAL_DMA_ERROR_NONE;\r\n    \r\n    if(BlockEndAdd < BlockStartAdd)\r\n    {\r\n      hsd->ErrorCode |= HAL_SD_ERROR_PARAM;\r\n      return HAL_ERROR;\r\n    }\r\n    \r\n    if(BlockEndAdd > (hsd->SdCard.LogBlockNbr))\r\n    {\r\n      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;\r\n      return HAL_ERROR;\r\n    }\r\n    \r\n    hsd->State = HAL_SD_STATE_BUSY;\r\n    \r\n    /* Check if the card command class supports erase command */\r\n    if(((hsd->SdCard.Class) & SDMMC_CCCC_ERASE) == 0U)\r\n    {\r\n      /* Clear all the static flags */\r\n      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r\n      hsd->ErrorCode |= HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;\r\n      hsd->State = HAL_SD_STATE_READY;\r\n      return HAL_ERROR;\r\n    }\r\n    \r\n    if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)\r\n    {\r\n      /* Clear all the static flags */\r\n      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);  \r\n      hsd->ErrorCode |= HAL_SD_ERROR_LOCK_UNLOCK_FAILED;\r\n      hsd->State = HAL_SD_STATE_READY;\r\n      return HAL_ERROR;\r\n    }\r\n    \r\n    /* Get start and end block for high capacity cards */\r\n    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)\r\n    {\r\n      BlockStartAdd *= 512U;\r\n      BlockEndAdd   *= 512U;\r\n    }\r\n    \r\n    /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */\r\n    if(hsd->SdCard.CardType != CARD_SECURED)\r\n    {\r\n      /* Send CMD32 SD_ERASE_GRP_START with argument as addr  */\r\n      errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, BlockStartAdd);\r\n      if(errorstate != HAL_SD_ERROR_NONE)\r\n      {\r\n        /* Clear all the static flags */\r\n        __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); \r\n        hsd->ErrorCode |= errorstate;\r\n        hsd->State = HAL_SD_STATE_READY;\r\n        return HAL_ERROR;\r\n      }\r\n      \r\n      /* Send CMD33 SD_ERASE_GRP_END with argument as addr  */\r\n      errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, BlockEndAdd);\r\n      if(errorstate != HAL_SD_ERROR_NONE)\r\n      {\r\n        /* Clear all the static flags */\r\n        __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); \r\n        hsd->ErrorCode |= errorstate;\r\n        hsd->State = HAL_SD_STATE_READY;\r\n        return HAL_ERROR;\r\n      }\r\n    }\r\n    \r\n    /* Send CMD38 ERASE */\r\n    errorstate = SDMMC_CmdErase(hsd->Instance);\r\n    if(errorstate != HAL_SD_ERROR_NONE)\r\n    {\r\n      /* Clear all the static flags */\r\n      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); \r\n      hsd->ErrorCode |= errorstate;\r\n      hsd->State = HAL_SD_STATE_READY;\r\n      return HAL_ERROR;\r\n    }\r\n    \r\n    hsd->State = HAL_SD_STATE_READY;\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  This function handles SD card interrupt request.\r\n  * @param  hsd Pointer to SD handle\r\n  * @retval None\r\n  */\r\nvoid HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)\r\n{\r\n  uint32_t errorstate = HAL_SD_ERROR_NONE;\r\n  \r\n  /* Check for SDMMC interrupt flags */\r\n  if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DATAEND) != RESET)\r\n  {\r\n    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DATAEND); \r\n    \r\n    __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\\\r\n                             SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);\r\n    \r\n    if((hsd->Context & SD_CONTEXT_IT) != RESET)\r\n    {\r\n      if(((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET))\r\n      {\r\n        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);\r\n        if(errorstate != HAL_SD_ERROR_NONE)\r\n        {\r\n          hsd->ErrorCode |= errorstate;\r\n          HAL_SD_ErrorCallback(hsd);\r\n        }\r\n      }\r\n      \r\n      /* Clear all the static flags */\r\n      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r\n      \r\n      hsd->State = HAL_SD_STATE_READY;\r\n      if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET))\r\n      {\r\n        HAL_SD_RxCpltCallback(hsd);\r\n      }\r\n      else\r\n      {\r\n        HAL_SD_TxCpltCallback(hsd);\r\n      }\r\n    }\r\n    else if((hsd->Context & SD_CONTEXT_DMA) != RESET)\r\n    {\r\n      if((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET)\r\n      {\r\n        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);\r\n        if(errorstate != HAL_SD_ERROR_NONE)\r\n        {\r\n          hsd->ErrorCode |= errorstate;\r\n          HAL_SD_ErrorCallback(hsd);\r\n        }\r\n      }\r\n      if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) == RESET) && ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) == RESET))\r\n      {\r\n        /* Disable the DMA transfer for transmit request by setting the DMAEN bit\r\n        in the SD DCTRL register */\r\n        hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN);\r\n        \r\n        hsd->State = HAL_SD_STATE_READY;\r\n        \r\n        HAL_SD_TxCpltCallback(hsd);\r\n      }\r\n    }\r\n  }\r\n  \r\n  else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXFIFOHE) != RESET)\r\n  {\r\n    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_TXFIFOHE);\r\n    \r\n    SD_Write_IT(hsd);\r\n  }\r\n  \r\n  else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXFIFOHF) != RESET)\r\n  {\r\n    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXFIFOHF);\r\n    \r\n    SD_Read_IT(hsd);\r\n  }\r\n  \r\n  else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_TXUNDERR) != RESET)\r\n  {\r\n    /* Set Error code */\r\n    if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL) != RESET)\r\n    {\r\n      hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; \r\n    }\r\n    if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DTIMEOUT) != RESET)\r\n    {\r\n      hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; \r\n    }\r\n    if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXOVERR) != RESET)\r\n    {\r\n      hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN; \r\n    }\r\n    if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXUNDERR) != RESET)\r\n    {\r\n      hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN; \r\n    }\r\n\r\n    /* Clear All flags */\r\n    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r\n    \r\n    /* Disable all interrupts */\r\n    __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\\\r\n                             SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);\r\n    \r\n    if((hsd->Context & SD_CONTEXT_DMA) != RESET)\r\n    {\r\n      /* Abort the SD DMA Streams */\r\n      if(hsd->hdmatx != NULL)\r\n      {\r\n        /* Set the DMA Tx abort callback */\r\n        hsd->hdmatx->XferAbortCallback = SD_DMATxAbort;\r\n        /* Abort DMA in IT mode */\r\n        if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK)\r\n        {\r\n          SD_DMATxAbort(hsd->hdmatx);\r\n        }\r\n      }\r\n      else if(hsd->hdmarx != NULL)\r\n      {\r\n        /* Set the DMA Rx abort callback */\r\n        hsd->hdmarx->XferAbortCallback = SD_DMARxAbort;\r\n        /* Abort DMA in IT mode */\r\n        if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK)\r\n        {\r\n          SD_DMARxAbort(hsd->hdmarx);\r\n        }\r\n      }\r\n      else\r\n      {\r\n        hsd->ErrorCode = HAL_SD_ERROR_NONE;\r\n        hsd->State = HAL_SD_STATE_READY;\r\n        HAL_SD_AbortCallback(hsd);\r\n      }\r\n    }\r\n    else if((hsd->Context & SD_CONTEXT_IT) != RESET)\r\n    {\r\n      /* Set the SD state to ready to be able to start again the process */\r\n      hsd->State = HAL_SD_STATE_READY;\r\n      HAL_SD_ErrorCallback(hsd);\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief return the SD state\r\n  * @param hsd Pointer to sd handle\r\n  * @retval HAL state\r\n  */\r\nHAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd)\r\n{\r\n  return hsd->State;\r\n}\r\n\r\n/**\r\n* @brief  Return the SD error code\r\n* @param  hsd  Pointer to a SD_HandleTypeDef structure that contains\r\n  *              the configuration information.\r\n* @retval SD Error Code\r\n*/\r\nuint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd)\r\n{\r\n  return hsd->ErrorCode;\r\n}\r\n\r\n/**\r\n  * @brief Tx Transfer completed callbacks\r\n  * @param hsd Pointer to SD handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hsd);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_SD_TxCpltCallback can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief Rx Transfer completed callbacks\r\n  * @param hsd Pointer SD handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hsd);\r\n \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_SD_RxCpltCallback can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief SD error callbacks\r\n  * @param hsd Pointer SD handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hsd);\r\n \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_SD_ErrorCallback can be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief SD Abort callbacks\r\n  * @param hsd Pointer SD handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hsd);\r\n \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_SD_ErrorCallback can be implemented in the user file\r\n   */ \r\n}\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup SD_Exported_Functions_Group3\r\n *  @brief   management functions \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                      ##### Peripheral Control functions #####\r\n  ==============================================================================  \r\n  [..]\r\n    This subsection provides a set of functions allowing to control the SD card \r\n    operations and get the related information\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Returns information the information of the card which are stored on\r\n  *         the CID register.\r\n  * @param  hsd Pointer to SD handle\r\n  * @param  pCID Pointer to a HAL_SD_CardCIDTypeDef structure that  \r\n  *         contains all CID register parameters \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID)\r\n{\r\n  uint32_t tmp = 0;\r\n  \r\n  /* Byte 0 */\r\n  tmp = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24);\r\n  pCID->ManufacturerID = tmp;\r\n  \r\n  /* Byte 1 */\r\n  tmp = (uint8_t)((hsd->CID[0] & 0x00FF0000) >> 16);\r\n  pCID->OEM_AppliID = tmp << 8;\r\n  \r\n  /* Byte 2 */\r\n  tmp = (uint8_t)((hsd->CID[0] & 0x000000FF00) >> 8);\r\n  pCID->OEM_AppliID |= tmp;\r\n  \r\n  /* Byte 3 */\r\n  tmp = (uint8_t)(hsd->CID[0] & 0x000000FF);\r\n  pCID->ProdName1 = tmp << 24;\r\n  \r\n  /* Byte 4 */\r\n  tmp = (uint8_t)((hsd->CID[1] & 0xFF000000U) >> 24);\r\n  pCID->ProdName1 |= tmp << 16;\r\n  \r\n  /* Byte 5 */\r\n  tmp = (uint8_t)((hsd->CID[1] & 0x00FF0000) >> 16);\r\n  pCID->ProdName1 |= tmp << 8;\r\n  \r\n  /* Byte 6 */\r\n  tmp = (uint8_t)((hsd->CID[1] & 0x0000FF00) >> 8);\r\n  pCID->ProdName1 |= tmp;\r\n  \r\n  /* Byte 7 */\r\n  tmp = (uint8_t)(hsd->CID[1] & 0x000000FF);\r\n  pCID->ProdName2 = tmp;\r\n  \r\n  /* Byte 8 */\r\n  tmp = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24);\r\n  pCID->ProdRev = tmp;\r\n  \r\n  /* Byte 9 */\r\n  tmp = (uint8_t)((hsd->CID[2] & 0x00FF0000) >> 16);\r\n  pCID->ProdSN = tmp << 24;\r\n  \r\n  /* Byte 10 */\r\n  tmp = (uint8_t)((hsd->CID[2] & 0x0000FF00) >> 8);\r\n  pCID->ProdSN |= tmp << 16;\r\n  \r\n  /* Byte 11 */\r\n  tmp = (uint8_t)(hsd->CID[2] & 0x000000FF);\r\n  pCID->ProdSN |= tmp << 8;\r\n  \r\n  /* Byte 12 */\r\n  tmp = (uint8_t)((hsd->CID[3] & 0xFF000000U) >> 24);\r\n  pCID->ProdSN |= tmp;\r\n  \r\n  /* Byte 13 */\r\n  tmp = (uint8_t)((hsd->CID[3] & 0x00FF0000) >> 16);\r\n  pCID->Reserved1   |= (tmp & 0xF0) >> 4;\r\n  pCID->ManufactDate = (tmp & 0x0F) << 8;\r\n  \r\n  /* Byte 14 */\r\n  tmp = (uint8_t)((hsd->CID[3] & 0x0000FF00) >> 8);\r\n  pCID->ManufactDate |= tmp;\r\n  \r\n  /* Byte 15 */\r\n  tmp = (uint8_t)(hsd->CID[3] & 0x000000FF);\r\n  pCID->CID_CRC   = (tmp & 0xFE) >> 1;\r\n  pCID->Reserved2 = 1;\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Returns information the information of the card which are stored on\r\n  *         the CSD register.\r\n  * @param  hsd Pointer to SD handle\r\n  * @param  pCSD Pointer to a HAL_SD_CardCSDTypeDef structure that  \r\n  *         contains all CSD register parameters  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD)\r\n{\r\n  uint32_t tmp = 0;\r\n  \r\n  /* Byte 0 */\r\n  tmp = (hsd->CSD[0] & 0xFF000000U) >> 24;\r\n  pCSD->CSDStruct      = (uint8_t)((tmp & 0xC0) >> 6);\r\n  pCSD->SysSpecVersion = (uint8_t)((tmp & 0x3C) >> 2);\r\n  pCSD->Reserved1      = tmp & 0x03;\r\n  \r\n  /* Byte 1 */\r\n  tmp = (hsd->CSD[0] & 0x00FF0000) >> 16;\r\n  pCSD->TAAC = (uint8_t)tmp;\r\n  \r\n  /* Byte 2 */\r\n  tmp = (hsd->CSD[0] & 0x0000FF00) >> 8;\r\n  pCSD->NSAC = (uint8_t)tmp;\r\n  \r\n  /* Byte 3 */\r\n  tmp = hsd->CSD[0] & 0x000000FF;\r\n  pCSD->MaxBusClkFrec = (uint8_t)tmp;\r\n  \r\n  /* Byte 4 */\r\n  tmp = (hsd->CSD[1] & 0xFF000000U) >> 24;\r\n  pCSD->CardComdClasses = (uint16_t)(tmp << 4);\r\n  \r\n  /* Byte 5 */\r\n  tmp = (hsd->CSD[1] & 0x00FF0000U) >> 16;\r\n  pCSD->CardComdClasses |= (uint16_t)((tmp & 0xF0) >> 4);\r\n  pCSD->RdBlockLen       = (uint8_t)(tmp & 0x0F);\r\n  \r\n  /* Byte 6 */\r\n  tmp = (hsd->CSD[1] & 0x0000FF00U) >> 8;\r\n  pCSD->PartBlockRead   = (uint8_t)((tmp & 0x80) >> 7);\r\n  pCSD->WrBlockMisalign = (uint8_t)((tmp & 0x40) >> 6);\r\n  pCSD->RdBlockMisalign = (uint8_t)((tmp & 0x20) >> 5);\r\n  pCSD->DSRImpl         = (uint8_t)((tmp & 0x10) >> 4);\r\n  pCSD->Reserved2       = 0; /*!< Reserved */\r\n       \r\n  if(hsd->SdCard.CardType == CARD_SDSC)\r\n  {\r\n    pCSD->DeviceSize = (tmp & 0x03) << 10;\r\n    \r\n    /* Byte 7 */\r\n    tmp = (uint8_t)(hsd->CSD[1] & 0x000000FFU);\r\n    pCSD->DeviceSize |= (tmp) << 2;\r\n    \r\n    /* Byte 8 */\r\n    tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000U) >> 24);\r\n    pCSD->DeviceSize |= (tmp & 0xC0) >> 6;\r\n    \r\n    pCSD->MaxRdCurrentVDDMin = (tmp & 0x38) >> 3;\r\n    pCSD->MaxRdCurrentVDDMax = (tmp & 0x07);\r\n    \r\n    /* Byte 9 */\r\n    tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000U) >> 16);\r\n    pCSD->MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5;\r\n    pCSD->MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2;\r\n    pCSD->DeviceSizeMul      = (tmp & 0x03) << 1;\r\n    /* Byte 10 */\r\n    tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00U) >> 8);\r\n    pCSD->DeviceSizeMul |= (tmp & 0x80) >> 7;\r\n    \r\n    hsd->SdCard.BlockNbr  = (pCSD->DeviceSize + 1) ;\r\n    hsd->SdCard.BlockNbr *= (1 << (pCSD->DeviceSizeMul + 2));\r\n    hsd->SdCard.BlockSize = 1 << (pCSD->RdBlockLen);\r\n\r\n    hsd->SdCard.LogBlockNbr =  (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512); \r\n    hsd->SdCard.LogBlockSize = 512;\r\n  }\r\n  else if(hsd->SdCard.CardType == CARD_SDHC_SDXC)\r\n  {\r\n    /* Byte 7 */\r\n    tmp = (uint8_t)(hsd->CSD[1] & 0x000000FFU);\r\n    pCSD->DeviceSize = (tmp & 0x3F) << 16;\r\n    \r\n    /* Byte 8 */\r\n    tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000U) >> 24);\r\n    \r\n    pCSD->DeviceSize |= (tmp << 8);\r\n    \r\n    /* Byte 9 */\r\n    tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000U) >> 16);\r\n    \r\n    pCSD->DeviceSize |= (tmp);\r\n    \r\n    /* Byte 10 */\r\n    tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00U) >> 8);\r\n    \r\n    hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr = (((uint64_t)pCSD->DeviceSize + 1) * 1024);\r\n    hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize = 512;\r\n  }\r\n  else\r\n  {\r\n    /* Clear all the static flags */\r\n    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);   \r\n    hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;\r\n    hsd->State = HAL_SD_STATE_READY;\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  pCSD->EraseGrSize = (tmp & 0x40) >> 6;\r\n  pCSD->EraseGrMul  = (tmp & 0x3F) << 1;\r\n  \r\n  /* Byte 11 */\r\n  tmp = (uint8_t)(hsd->CSD[2] & 0x000000FF);\r\n  pCSD->EraseGrMul     |= (tmp & 0x80) >> 7;\r\n  pCSD->WrProtectGrSize = (tmp & 0x7F);\r\n  \r\n  /* Byte 12 */\r\n  tmp = (uint8_t)((hsd->CSD[3] & 0xFF000000U) >> 24);\r\n  pCSD->WrProtectGrEnable = (tmp & 0x80) >> 7;\r\n  pCSD->ManDeflECC        = (tmp & 0x60) >> 5;\r\n  pCSD->WrSpeedFact       = (tmp & 0x1C) >> 2;\r\n  pCSD->MaxWrBlockLen     = (tmp & 0x03) << 2;\r\n  \r\n  /* Byte 13 */\r\n  tmp = (uint8_t)((hsd->CSD[3] & 0x00FF0000) >> 16);\r\n  pCSD->MaxWrBlockLen      |= (tmp & 0xC0) >> 6;\r\n  pCSD->WriteBlockPaPartial = (tmp & 0x20) >> 5;\r\n  pCSD->Reserved3           = 0;\r\n  pCSD->ContentProtectAppli = (tmp & 0x01);\r\n  \r\n  /* Byte 14 */\r\n  tmp = (uint8_t)((hsd->CSD[3] & 0x0000FF00) >> 8);\r\n  pCSD->FileFormatGrouop = (tmp & 0x80) >> 7;\r\n  pCSD->CopyFlag         = (tmp & 0x40) >> 6;\r\n  pCSD->PermWrProtect    = (tmp & 0x20) >> 5;\r\n  pCSD->TempWrProtect    = (tmp & 0x10) >> 4;\r\n  pCSD->FileFormat       = (tmp & 0x0C) >> 2;\r\n  pCSD->ECC              = (tmp & 0x03);\r\n  \r\n  /* Byte 15 */\r\n  tmp = (uint8_t)(hsd->CSD[3] & 0x000000FF);\r\n  pCSD->CSD_CRC   = (tmp & 0xFE) >> 1;\r\n  pCSD->Reserved4 = 1;\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Gets the SD status info.\r\n  * @param  hsd Pointer to SD handle      \r\n  * @param  pStatus Pointer to the HAL_SD_CardStatusTypeDef structure that \r\n  *         will contain the SD card status information \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus)\r\n{\r\n  uint32_t tmp = 0;\r\n  uint32_t sd_status[16];\r\n  uint32_t errorstate = HAL_SD_ERROR_NONE;\r\n  \r\n  errorstate = SD_SendSDStatus(hsd, sd_status);\r\n  if(errorstate != HAL_OK)\r\n  {\r\n    /* Clear all the static flags */\r\n    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);   \r\n    hsd->ErrorCode |= errorstate;\r\n    hsd->State = HAL_SD_STATE_READY;\r\n    return HAL_ERROR;\r\n  }\r\n  else\r\n  {\r\n    /* Byte 0 */\r\n    tmp = (sd_status[0] & 0xC0) >> 6;\r\n    pStatus->DataBusWidth = (uint8_t)tmp;\r\n    \r\n    /* Byte 0 */\r\n    tmp = (sd_status[0] & 0x20) >> 5;\r\n    pStatus->SecuredMode = (uint8_t)tmp;\r\n    \r\n    /* Byte 2 */\r\n    tmp = (sd_status[0] & 0x00FF0000U) >> 16;\r\n    pStatus->CardType = (uint16_t)(tmp << 8);\r\n    \r\n    /* Byte 3 */\r\n    tmp = (sd_status[0] & 0xFF000000U) >> 24;\r\n    pStatus->CardType |= (uint16_t)tmp;\r\n    \r\n    /* Byte 4 */\r\n    tmp = (sd_status[1] & 0xFF);\r\n    pStatus->ProtectedAreaSize = (uint32_t)(tmp << 24);\r\n    \r\n    /* Byte 5 */\r\n    tmp = (sd_status[1] & 0xFF00) >> 8;\r\n    pStatus->ProtectedAreaSize |= (uint32_t)(tmp << 16);\r\n    \r\n    /* Byte 6 */\r\n    tmp = (sd_status[1] & 0xFF0000) >> 16;\r\n    pStatus->ProtectedAreaSize |= (uint32_t)(tmp << 8);\r\n    \r\n    /* Byte 7 */\r\n    tmp = (sd_status[1] & 0xFF000000U) >> 24;\r\n    pStatus->ProtectedAreaSize |= (uint32_t)tmp;\r\n    \r\n    /* Byte 8 */\r\n    tmp = (sd_status[2] & 0xFF);\r\n    pStatus->SpeedClass = (uint8_t)tmp;\r\n    \r\n    /* Byte 9 */\r\n    tmp = (sd_status[2] & 0xFF00) >> 8;\r\n    pStatus->PerformanceMove = (uint8_t)tmp;\r\n    \r\n    /* Byte 10 */\r\n    tmp = (sd_status[2] & 0xF00000) >> 20;\r\n    pStatus->AllocationUnitSize = (uint8_t)tmp;\r\n    \r\n    /* Byte 11 */\r\n    tmp = (sd_status[2] & 0xFF000000U) >> 24;\r\n    pStatus->EraseSize = (uint16_t)(tmp << 8);\r\n    \r\n    /* Byte 12 */\r\n    tmp = (sd_status[3] & 0xFF);\r\n    pStatus->EraseSize |= (uint16_t)tmp;\r\n    \r\n    /* Byte 13 */\r\n    tmp = (sd_status[3] & 0xFC00) >> 10;\r\n    pStatus->EraseTimeout = (uint8_t)tmp;\r\n    \r\n    /* Byte 13 */\r\n    tmp = (sd_status[3] & 0x0300) >> 8;\r\n    pStatus->EraseOffset = (uint8_t)tmp;\r\n  }\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Gets the SD card info.\r\n  * @param  hsd Pointer to SD handle      \r\n  * @param  pCardInfo Pointer to the HAL_SD_CardInfoTypeDef structure that \r\n  *         will contain the SD card status information \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo)\r\n{\r\n  pCardInfo->CardType     = (uint32_t)(hsd->SdCard.CardType);\r\n  pCardInfo->CardVersion  = (uint32_t)(hsd->SdCard.CardVersion);\r\n  pCardInfo->Class        = (uint32_t)(hsd->SdCard.Class);\r\n  pCardInfo->RelCardAdd   = (uint32_t)(hsd->SdCard.RelCardAdd);\r\n  pCardInfo->BlockNbr     = (uint32_t)(hsd->SdCard.BlockNbr);\r\n  pCardInfo->BlockSize    = (uint32_t)(hsd->SdCard.BlockSize);\r\n  pCardInfo->LogBlockNbr  = (uint32_t)(hsd->SdCard.LogBlockNbr);\r\n  pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Enables wide bus operation for the requested card if supported by \r\n  *         card.\r\n  * @param  hsd Pointer to SD handle       \r\n  * @param  WideMode Specifies the SD card wide bus mode \r\n  *          This parameter can be one of the following values:\r\n  *            @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer\r\n  *            @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer\r\n  *            @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode)\r\n{\r\n  SDMMC_InitTypeDef Init;\r\n  uint32_t errorstate = HAL_SD_ERROR_NONE;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_SDMMC_BUS_WIDE(WideMode));\r\n  \r\n  /* Chnage Satte */\r\n  hsd->State = HAL_SD_STATE_BUSY;\r\n  \r\n  if(hsd->SdCard.CardType != CARD_SECURED) \r\n  {\r\n    if(WideMode == SDMMC_BUS_WIDE_8B)\r\n    {\r\n      hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;\r\n    }\r\n    else if(WideMode == SDMMC_BUS_WIDE_4B)\r\n    {\r\n      errorstate = SD_WideBus_Enable(hsd);\r\n      \r\n      hsd->ErrorCode |= errorstate;\r\n    }\r\n    else if(WideMode == SDMMC_BUS_WIDE_1B)\r\n    {\r\n      errorstate = SD_WideBus_Disable(hsd);\r\n      \r\n      hsd->ErrorCode |= errorstate;\r\n    }\r\n    else\r\n    {\r\n      /* WideMode is not a valid argument*/\r\n      hsd->ErrorCode |= HAL_SD_ERROR_PARAM;\r\n    }\r\n  }  \r\n  else\r\n  {\r\n    /* MMC Card does not support this feature */\r\n    hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;\r\n  }\r\n  \r\n  if(hsd->ErrorCode != HAL_SD_ERROR_NONE)\r\n  {\r\n    /* Clear all the static flags */\r\n    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r\n    hsd->State = HAL_SD_STATE_READY;\r\n    return HAL_ERROR;\r\n  }\r\n  else\r\n  {\r\n    /* Configure the SDMMC peripheral */\r\n    Init.ClockEdge           = hsd->Init.ClockEdge;\r\n    Init.ClockBypass         = hsd->Init.ClockBypass;\r\n    Init.ClockPowerSave      = hsd->Init.ClockPowerSave;\r\n    Init.BusWide             = WideMode;\r\n    Init.HardwareFlowControl = hsd->Init.HardwareFlowControl;\r\n    Init.ClockDiv            = hsd->Init.ClockDiv;\r\n    SDMMC_Init(hsd->Instance, Init);\r\n  }\r\n\r\n  /* Change State */\r\n  hsd->State = HAL_SD_STATE_READY;\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Gets the current sd card data state.\r\n  * @param  hsd pointer to SD handle\r\n  * @retval Card state\r\n  */\r\nHAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd)\r\n{\r\n  HAL_SD_CardStateTypeDef cardstate =  HAL_SD_CARD_TRANSFER;\r\n  uint32_t errorstate = HAL_SD_ERROR_NONE;\r\n  uint32_t resp1 = 0;\r\n  \r\n  errorstate = SD_SendStatus(hsd, &resp1);\r\n  if(errorstate != HAL_OK)\r\n  {\r\n    hsd->ErrorCode |= errorstate;\r\n  }\r\n\r\n  cardstate = (HAL_SD_CardStateTypeDef)((resp1 >> 9) & 0x0F);\r\n  \r\n  return cardstate;\r\n}\r\n\r\n/**\r\n  * @brief  Abort the current transfer and disable the SD.\r\n  * @param  hsd pointer to a SD_HandleTypeDef structure that contains\r\n  *                the configuration information for SD module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd)\r\n{\r\n  HAL_SD_CardStateTypeDef CardState;\r\n  \r\n  /* DIsable All interrupts */\r\n  __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\\\r\n                           SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);\r\n  \r\n  /* Clear All flags */\r\n  __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r\n  \r\n  if((hsd->hdmatx != NULL) || (hsd->hdmarx != NULL))\r\n  {\r\n    /* Disable the SD DMA request */\r\n    hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN);\r\n    \r\n    /* Abort the SD DMA Tx Stream */\r\n    if(hsd->hdmatx != NULL)\r\n    {\r\n      HAL_DMA_Abort(hsd->hdmatx);\r\n    }\r\n    /* Abort the SD DMA Rx Stream */\r\n    if(hsd->hdmarx != NULL)\r\n    {\r\n      HAL_DMA_Abort(hsd->hdmarx);\r\n    }\r\n  }\r\n  \r\n  hsd->State = HAL_SD_STATE_READY;\r\n  CardState = HAL_SD_GetCardState(hsd);\r\n  if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))\r\n  {\r\n    hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);\r\n  }\r\n  if(hsd->ErrorCode != HAL_SD_ERROR_NONE)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Abort the current transfer and disable the SD (IT mode).\r\n  * @param  hsd pointer to a SD_HandleTypeDef structure that contains\r\n  *                the configuration information for SD module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd)\r\n{\r\n  HAL_SD_CardStateTypeDef CardState;\r\n    \r\n  /* DIsable All interrupts */\r\n  __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\\\r\n                           SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);\r\n  \r\n  /* Clear All flags */\r\n  __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r\n  \r\n  if((hsd->hdmatx != NULL) || (hsd->hdmarx != NULL))\r\n  {\r\n    /* Disable the SD DMA request */\r\n    hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN);\r\n    \r\n    /* Abort the SD DMA Tx Stream */\r\n    if(hsd->hdmatx != NULL)\r\n    {\r\n      hsd->hdmatx->XferAbortCallback =  SD_DMATxAbort;\r\n      if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK)\r\n      {\r\n        hsd->hdmatx = NULL;\r\n      }\r\n    }\r\n    /* Abort the SD DMA Rx Stream */\r\n    if(hsd->hdmarx != NULL)\r\n    {\r\n      hsd->hdmarx->XferAbortCallback =  SD_DMARxAbort;\r\n      if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK)\r\n      {\r\n        hsd->hdmarx = NULL;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* No transfer ongoing on both DMA channels*/\r\n  if((hsd->hdmatx == NULL) && (hsd->hdmarx == NULL))\r\n  {\r\n    CardState = HAL_SD_GetCardState(hsd);\r\n    hsd->State = HAL_SD_STATE_READY;\r\n    if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))\r\n    {\r\n      hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);\r\n    }\r\n    if(hsd->ErrorCode != HAL_SD_ERROR_NONE)\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n    else\r\n    {\r\n      HAL_SD_AbortCallback(hsd);\r\n    }\r\n  }\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Private function ----------------------------------------------------------*/  \r\n/** @addtogroup SD_Private_Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  DMA SD transmit process complete callback \r\n  * @param  hdma DMA handle\r\n  * @retval None\r\n  */\r\nstatic void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma)     \r\n{\r\n  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);\r\n  \r\n  /* Enable DATAEND Interrupt */\r\n  __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DATAEND));\r\n}\r\n\r\n/**\r\n  * @brief  DMA SD receive process complete callback \r\n  * @param  hdma DMA handle\r\n  * @retval None\r\n  */\r\nstatic void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)  \r\n{\r\n  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);\r\n  uint32_t errorstate = HAL_SD_ERROR_NONE;\r\n  \r\n  /* Send stop command in multiblock write */\r\n  if(hsd->Context == (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA))\r\n  {\r\n    errorstate = SDMMC_CmdStopTransfer(hsd->Instance);\r\n    if(errorstate != HAL_SD_ERROR_NONE)\r\n    {\r\n      hsd->ErrorCode |= errorstate;\r\n      HAL_SD_ErrorCallback(hsd);\r\n    }\r\n  }\r\n  \r\n  /* Disable the DMA transfer for transmit request by setting the DMAEN bit\r\n  in the SD DCTRL register */\r\n  hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN);\r\n  \r\n  /* Clear all the static flags */\r\n  __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r\n  \r\n  hsd->State = HAL_SD_STATE_READY;\r\n\r\n  HAL_SD_RxCpltCallback(hsd);\r\n}\r\n\r\n/**\r\n* @brief  DMA SD communication error callback \r\n* @param  hdma DMA handle\r\n* @retval None\r\n*/\r\nstatic void SD_DMAError(DMA_HandleTypeDef *hdma)   \r\n{\r\n  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);\r\n  HAL_SD_CardStateTypeDef CardState;\r\n  \r\n  /* if DMA error is FIFO error ignore it */\r\n  if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)\r\n  {\r\n    if((hsd->hdmarx->ErrorCode == HAL_DMA_ERROR_TE) || (hsd->hdmatx->ErrorCode == HAL_DMA_ERROR_TE))\r\n    {\r\n      /* Clear All flags */\r\n      __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r\n      \r\n      /* Disable All interrupts */\r\n      __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\\\r\n        SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);\r\n      \r\n      hsd->ErrorCode |= HAL_SD_ERROR_DMA;\r\n      CardState = HAL_SD_GetCardState(hsd);\r\n      if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))\r\n      {\r\n        hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);\r\n      }\r\n      \r\n      hsd->State= HAL_SD_STATE_READY;\r\n    }\r\n    HAL_SD_ErrorCallback(hsd);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  DMA SD Tx Abort callback \r\n  * @param  hdma DMA handle\r\n  * @retval None\r\n  */\r\nstatic void SD_DMATxAbort(DMA_HandleTypeDef *hdma)   \r\n{\r\n  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);\r\n  HAL_SD_CardStateTypeDef CardState;\r\n  \r\n  if(hsd->hdmatx != NULL)\r\n  {\r\n    hsd->hdmatx = NULL;\r\n  }\r\n  \r\n  /* All DMA channels are aborted */\r\n  if(hsd->hdmarx == NULL)\r\n  {\r\n    CardState = HAL_SD_GetCardState(hsd);\r\n    hsd->ErrorCode = HAL_SD_ERROR_NONE;\r\n    hsd->State = HAL_SD_STATE_READY;\r\n    if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))\r\n    {\r\n      hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);\r\n      \r\n      if(hsd->ErrorCode != HAL_SD_ERROR_NONE)\r\n      {\r\n        HAL_SD_AbortCallback(hsd);\r\n      }\r\n      else\r\n      {\r\n        HAL_SD_ErrorCallback(hsd);\r\n      }\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  DMA SD Rx Abort callback \r\n  * @param  hdma DMA handle\r\n  * @retval None\r\n  */\r\nstatic void SD_DMARxAbort(DMA_HandleTypeDef *hdma)   \r\n{\r\n  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);\r\n  HAL_SD_CardStateTypeDef CardState;\r\n  \r\n  if(hsd->hdmarx != NULL)\r\n  {\r\n    hsd->hdmarx = NULL;\r\n  }\r\n  \r\n  /* All DMA channels are aborted */\r\n  if(hsd->hdmatx == NULL)\r\n  {\r\n    CardState = HAL_SD_GetCardState(hsd);\r\n    hsd->ErrorCode = HAL_SD_ERROR_NONE;\r\n    hsd->State = HAL_SD_STATE_READY;\r\n    if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))\r\n    {\r\n      hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);\r\n      \r\n      if(hsd->ErrorCode != HAL_SD_ERROR_NONE)\r\n      {\r\n        HAL_SD_AbortCallback(hsd);\r\n      }\r\n      else\r\n      {\r\n        HAL_SD_ErrorCallback(hsd);\r\n      }\r\n    }\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Initializes the sd card.\r\n  * @param  hsd Pointer to SD handle\r\n  * @retval SD Card error state\r\n  */\r\nstatic uint32_t SD_InitCard(SD_HandleTypeDef *hsd)\r\n{\r\n  HAL_SD_CardCSDTypeDef CSD;\r\n  uint32_t errorstate = HAL_SD_ERROR_NONE;\r\n  uint16_t sd_rca = 1;\r\n  \r\n  /* Check the power State */\r\n  if(SDMMC_GetPowerState(hsd->Instance) == 0) \r\n  {\r\n    /* Power off */\r\n    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;\r\n  }\r\n  \r\n  if(hsd->SdCard.CardType != CARD_SECURED) \r\n  {\r\n    /* Send CMD2 ALL_SEND_CID */\r\n    errorstate = SDMMC_CmdSendCID(hsd->Instance);\r\n    if(errorstate != HAL_SD_ERROR_NONE)\r\n    {\r\n      return errorstate;\r\n    }\r\n    else\r\n    {\r\n      /* Get Card identification number data */\r\n      hsd->CID[0] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);\r\n      hsd->CID[1] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);\r\n      hsd->CID[2] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);\r\n      hsd->CID[3] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);\r\n    }\r\n  }\r\n  \r\n  if(hsd->SdCard.CardType != CARD_SECURED) \r\n  {\r\n    /* Send CMD3 SET_REL_ADDR with argument 0 */\r\n    /* SD Card publishes its RCA. */\r\n    errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca);\r\n    if(errorstate != HAL_SD_ERROR_NONE)\r\n    {\r\n      return errorstate;\r\n    }\r\n  }\r\n  if(hsd->SdCard.CardType != CARD_SECURED) \r\n  {\r\n    /* Get the SD card RCA */\r\n    hsd->SdCard.RelCardAdd = sd_rca;\r\n    \r\n    /* Send CMD9 SEND_CSD with argument as card's RCA */\r\n    errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));\r\n    if(errorstate != HAL_SD_ERROR_NONE)\r\n    {\r\n      return errorstate;\r\n    }\r\n    else\r\n    {\r\n      /* Get Card Specific Data */\r\n      hsd->CSD[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);\r\n      hsd->CSD[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);\r\n      hsd->CSD[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);\r\n      hsd->CSD[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);\r\n    }\r\n  }\r\n  \r\n  /* Get the Card Class */\r\n  hsd->SdCard.Class = (SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2) >> 20);\r\n  \r\n  /* Get CSD parameters */\r\n  HAL_SD_GetCardCSD(hsd, &CSD);\r\n\r\n  /* Select the Card */\r\n  errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16));\r\n  if(errorstate != HAL_SD_ERROR_NONE)\r\n  {\r\n    return errorstate;\r\n  }\r\n\r\n  /* Configure SDMMC peripheral interface */     \r\n  SDMMC_Init(hsd->Instance, hsd->Init);\r\n\r\n  /* All cards are initialized */\r\n  return HAL_SD_ERROR_NONE;\r\n}\r\n\r\n/**\r\n  * @brief  Enquires cards about their operating voltage and configures clock\r\n  *         controls and stores SD information that will be needed in future\r\n  *         in the SD handle.\r\n  * @param  hsd Pointer to SD handle\r\n  * @retval error state\r\n  */\r\nstatic uint32_t SD_PowerON(SD_HandleTypeDef *hsd)\r\n{\r\n  __IO uint32_t count = 0;\r\n  uint32_t response = 0, validvoltage = 0;\r\n  uint32_t errorstate = HAL_SD_ERROR_NONE;\r\n  \r\n  /* CMD0: GO_IDLE_STATE */\r\n  errorstate = SDMMC_CmdGoIdleState(hsd->Instance);\r\n  if(errorstate != HAL_SD_ERROR_NONE)\r\n  {\r\n    return errorstate;\r\n  }\r\n  \r\n  /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */\r\n  errorstate = SDMMC_CmdOperCond(hsd->Instance);\r\n  if(errorstate != HAL_SD_ERROR_NONE)\r\n  {\r\n    hsd->SdCard.CardVersion = CARD_V1_X;\r\n      \r\n    /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */\r\n    while(validvoltage == 0)\r\n    {\r\n      if(count++ == SDMMC_MAX_VOLT_TRIAL)\r\n      {\r\n        return HAL_SD_ERROR_INVALID_VOLTRANGE;\r\n      }\r\n      \r\n      /* SEND CMD55 APP_CMD with RCA as 0 */\r\n      errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);\r\n      if(errorstate != HAL_SD_ERROR_NONE)\r\n      {\r\n        return HAL_SD_ERROR_UNSUPPORTED_FEATURE;\r\n      }\r\n      \r\n      /* Send CMD41 */\r\n      errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_STD_CAPACITY);\r\n      if(errorstate != HAL_SD_ERROR_NONE)\r\n      {\r\n        return HAL_SD_ERROR_UNSUPPORTED_FEATURE;\r\n      }\r\n      \r\n      /* Get command response */\r\n      response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);\r\n      \r\n      /* Get operating voltage*/\r\n      validvoltage = (((response >> 31) == 1) ? 1 : 0);\r\n    }\r\n    /* Card type is SDSC */\r\n    hsd->SdCard.CardType = CARD_SDSC;\r\n  }\r\n  else\r\n  {\r\n    hsd->SdCard.CardVersion = CARD_V2_X;\r\n        \r\n    /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */\r\n    while(validvoltage == 0)\r\n    {\r\n      if(count++ == SDMMC_MAX_VOLT_TRIAL)\r\n      {\r\n        return HAL_SD_ERROR_INVALID_VOLTRANGE;\r\n      }\r\n      \r\n      /* SEND CMD55 APP_CMD with RCA as 0 */\r\n      errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);\r\n      if(errorstate != HAL_SD_ERROR_NONE)\r\n      {\r\n        return errorstate;\r\n      }\r\n      \r\n      /* Send CMD41 */\r\n      errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_HIGH_CAPACITY);\r\n      if(errorstate != HAL_SD_ERROR_NONE)\r\n      {\r\n        return errorstate;\r\n      }\r\n      \r\n      /* Get command response */\r\n      response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);\r\n      \r\n      /* Get operating voltage*/\r\n      validvoltage = (((response >> 31) == 1) ? 1 : 0);\r\n    }\r\n    \r\n    if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */\r\n    {\r\n      hsd->SdCard.CardType = CARD_SDHC_SDXC;\r\n    }\r\n    else\r\n    {\r\n      hsd->SdCard.CardType = CARD_SDSC;\r\n    }\r\n  }\r\n  \r\n  return HAL_SD_ERROR_NONE;\r\n}\r\n\r\n/**\r\n  * @brief  Turns the SDMMC output signals off.\r\n  * @param  hsd Pointer to SD handle\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef SD_PowerOFF(SD_HandleTypeDef *hsd)\r\n{\r\n  /* Set Power State to OFF */\r\n  SDMMC_PowerState_OFF(hsd->Instance);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Send Status info command.\r\n  * @param  hsd pointer to SD handle\r\n  * @param  pSDstatus Pointer to the buffer that will contain the SD card status \r\n  *         SD Status register)\r\n  * @retval error state\r\n  */\r\nstatic uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)\r\n{\r\n  SDMMC_DataInitTypeDef config;\r\n  uint32_t errorstate = HAL_SD_ERROR_NONE;\r\n  uint32_t tickstart = HAL_GetTick();\r\n  uint32_t count = 0;\r\n  \r\n  /* Check SD response */\r\n  if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)\r\n  {\r\n    return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;\r\n  }\r\n  \r\n  /* Set block size for card if it is not equal to current block size for card */\r\n  errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64);\r\n  if(errorstate != HAL_SD_ERROR_NONE)\r\n  {\r\n    hsd->ErrorCode |= HAL_SD_ERROR_NONE;\r\n    return errorstate;\r\n  }\r\n  \r\n  /* Send CMD55 */\r\n  errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16));\r\n  if(errorstate != HAL_SD_ERROR_NONE)\r\n  {\r\n    hsd->ErrorCode |= HAL_SD_ERROR_NONE;\r\n    return errorstate;\r\n  }\r\n  \r\n  /* Configure the SD DPSM (Data Path State Machine) */ \r\n  config.DataTimeOut   = SDMMC_DATATIMEOUT;\r\n  config.DataLength    = 64;\r\n  config.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B;\r\n  config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;\r\n  config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;\r\n  config.DPSM          = SDMMC_DPSM_ENABLE;\r\n  SDMMC_ConfigData(hsd->Instance, &config);\r\n  \r\n  /* Send ACMD13 (SD_APP_STAUS)  with argument as card's RCA */\r\n  errorstate = SDMMC_CmdStatusRegister(hsd->Instance);\r\n  if(errorstate != HAL_SD_ERROR_NONE)\r\n  {\r\n    hsd->ErrorCode |= HAL_SD_ERROR_NONE;\r\n    return errorstate;\r\n  }\r\n  \r\n  /* Get status data */\r\n  while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))\r\n  {\r\n    if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))\r\n    {\r\n      for(count = 0; count < 8; count++)\r\n      {\r\n        *(pSDstatus + count) = SDMMC_ReadFIFO(hsd->Instance);\r\n      }\r\n      \r\n      pSDstatus += 8;\r\n    }\r\n    \r\n    if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)\r\n    {\r\n      return HAL_SD_ERROR_TIMEOUT;\r\n    }\r\n  }\r\n  \r\n  if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))\r\n  {\r\n    return HAL_SD_ERROR_DATA_TIMEOUT;\r\n  }\r\n  else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))\r\n  {\r\n    return HAL_SD_ERROR_DATA_CRC_FAIL;\r\n  }\r\n  else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))\r\n  {\r\n    return HAL_SD_ERROR_RX_OVERRUN;\r\n  }\r\n\r\n  while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)))\r\n  {\r\n    *pSDstatus = SDMMC_ReadFIFO(hsd->Instance);\r\n    pSDstatus++;\r\n    \r\n    if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)\r\n    {\r\n      return HAL_SD_ERROR_TIMEOUT;\r\n    }\r\n  }\r\n  \r\n  /* Clear all the static status flags*/\r\n  __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r\n  \r\n  return HAL_SD_ERROR_NONE;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the current card's status.\r\n  * @param  hsd Pointer to SD handle\r\n  * @param  pCardStatus pointer to the buffer that will contain the SD card \r\n  *         status (Card Status register)  \r\n  * @retval error state\r\n  */\r\nstatic uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)\r\n{\r\n  uint32_t errorstate = HAL_SD_ERROR_NONE;\r\n  \r\n  if(pCardStatus == NULL)\r\n  {\r\n    return HAL_SD_ERROR_PARAM;\r\n  }\r\n  \r\n  /* Send Status command */\r\n  errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16));\r\n  if(errorstate != HAL_OK)\r\n  {\r\n    return errorstate;\r\n  }\r\n  \r\n  /* Get SD card status */\r\n  *pCardStatus = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);\r\n  \r\n  return HAL_SD_ERROR_NONE;\r\n}\r\n\r\n/**\r\n  * @brief  Enables the SDMMC wide bus mode.\r\n  * @param  hsd pointer to SD handle\r\n  * @retval error state\r\n  */\r\nstatic uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd)\r\n{\r\n  uint32_t scr[2] = {0, 0};\r\n  uint32_t errorstate = HAL_SD_ERROR_NONE;\r\n  \r\n  if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)\r\n  {\r\n    return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;\r\n  }\r\n  \r\n  /* Get SCR Register */\r\n  errorstate = SD_FindSCR(hsd, scr);\r\n  if(errorstate != HAL_OK)\r\n  {\r\n    return errorstate;\r\n  }\r\n  \r\n  /* If requested card supports wide bus operation */\r\n  if((scr[1] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO)\r\n  {\r\n    /* Send CMD55 APP_CMD with argument as card's RCA.*/\r\n    errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16));\r\n    if(errorstate != HAL_OK)\r\n    {\r\n      return errorstate;\r\n    }\r\n    \r\n    /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */\r\n    errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2);\r\n    if(errorstate != HAL_OK)\r\n    {\r\n      return errorstate;\r\n    }\r\n\r\n    return HAL_SD_ERROR_NONE;\r\n  }\r\n  else\r\n  {\r\n    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Disables the SDMMC wide bus mode.\r\n  * @param  hsd Pointer to SD handle\r\n  * @retval error state\r\n  */\r\nstatic uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd)\r\n{\r\n  uint32_t scr[2] = {0, 0};\r\n  uint32_t errorstate = HAL_SD_ERROR_NONE;\r\n  \r\n  if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)\r\n  {\r\n    return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;\r\n  }\r\n  \r\n  /* Get SCR Register */\r\n  errorstate = SD_FindSCR(hsd, scr);\r\n  if(errorstate != HAL_OK)\r\n  {\r\n    return errorstate;\r\n  }\r\n  \r\n  /* If requested card supports 1 bit mode operation */\r\n  if((scr[1] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO)\r\n  {\r\n    /* Send CMD55 APP_CMD with argument as card's RCA */\r\n    errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16));\r\n    if(errorstate != HAL_OK)\r\n    {\r\n      return errorstate;\r\n    }\r\n    \r\n    /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */\r\n    errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0);\r\n    if(errorstate != HAL_OK)\r\n    {\r\n      return errorstate;\r\n    }\r\n    \r\n    return HAL_SD_ERROR_NONE;\r\n  }\r\n  else\r\n  {\r\n    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;\r\n  }\r\n}\r\n  \r\n  \r\n/**\r\n  * @brief  Finds the SD card SCR register value.\r\n  * @param  hsd Pointer to SD handle\r\n  * @param  pSCR pointer to the buffer that will contain the SCR value  \r\n  * @retval error state\r\n  */\r\nstatic uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)\r\n{\r\n  SDMMC_DataInitTypeDef config;\r\n  uint32_t errorstate = HAL_SD_ERROR_NONE;\r\n  uint32_t tickstart = HAL_GetTick();\r\n  uint32_t index = 0;\r\n  uint32_t tempscr[2] = {0, 0};\r\n  \r\n  /* Set Block Size To 8 Bytes */\r\n  errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8);\r\n  if(errorstate != HAL_OK)\r\n  {\r\n    return errorstate;\r\n  }\r\n\r\n  /* Send CMD55 APP_CMD with argument as card's RCA */\r\n  errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16));\r\n  if(errorstate != HAL_OK)\r\n  {\r\n    return errorstate;\r\n  }\r\n\r\n  config.DataTimeOut   = SDMMC_DATATIMEOUT;\r\n  config.DataLength    = 8;\r\n  config.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B;\r\n  config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;\r\n  config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;\r\n  config.DPSM          = SDMMC_DPSM_ENABLE;\r\n  SDMMC_ConfigData(hsd->Instance, &config);\r\n  \r\n  /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */\r\n  errorstate = SDMMC_CmdSendSCR(hsd->Instance);\r\n  if(errorstate != HAL_OK)\r\n  {\r\n    return errorstate;\r\n  }\r\n  \r\n  while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))\r\n  {\r\n    if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL))\r\n    {\r\n      *(tempscr + index) = SDMMC_ReadFIFO(hsd->Instance);\r\n      index++;\r\n    }\r\n    \r\n    if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)\r\n    {\r\n      return HAL_SD_ERROR_TIMEOUT;\r\n    }\r\n  }\r\n  \r\n  if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))\r\n  {\r\n    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);\r\n    \r\n    return HAL_SD_ERROR_DATA_TIMEOUT;\r\n  }\r\n  else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))\r\n  {\r\n    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);\r\n    \r\n    return HAL_SD_ERROR_DATA_CRC_FAIL;\r\n  }\r\n  else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))\r\n  {\r\n    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);\r\n    \r\n    return HAL_SD_ERROR_RX_OVERRUN;\r\n  }\r\n  else\r\n  {\r\n    /* No error flag set */\r\n    /* Clear all the static flags */\r\n    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r\n    \r\n    *(pSCR + 1) = ((tempscr[0] & SDMMC_0TO7BITS) << 24)  | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\\\r\n      ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24);\r\n    \r\n    *(pSCR) = ((tempscr[1] & SDMMC_0TO7BITS) << 24)  | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\\\r\n      ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24);\r\n  }\r\n\r\n  return HAL_SD_ERROR_NONE;\r\n}\r\n\r\n/**\r\n  * @brief  Wrap up reading in non-blocking mode.\r\n  * @param  hsd pointer to a SD_HandleTypeDef structure that contains\r\n  *              the configuration information.\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef SD_Read_IT(SD_HandleTypeDef *hsd)\r\n{\r\n  uint32_t count = 0;\r\n  uint32_t* tmp;\r\n\r\n  tmp = (uint32_t*)hsd->pRxBuffPtr;\r\n  \r\n  /* Read data from SDMMC Rx FIFO */\r\n  for(count = 0; count < 8; count++)\r\n  {\r\n    *(tmp + count) = SDMMC_ReadFIFO(hsd->Instance);\r\n  }\r\n  \r\n  hsd->pRxBuffPtr += 8;\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Wrap up writing in non-blocking mode.\r\n  * @param  hsd pointer to a SD_HandleTypeDef structure that contains\r\n  *              the configuration information.\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef SD_Write_IT(SD_HandleTypeDef *hsd)\r\n{\r\n  uint32_t count = 0;\r\n  uint32_t* tmp;\r\n  \r\n  tmp = (uint32_t*)hsd->pTxBuffPtr;\r\n  \r\n  /* Write data to SDMMC Tx FIFO */\r\n  for(count = 0; count < 8; count++)\r\n  {\r\n    SDMMC_WriteFIFO(hsd->Instance, (tmp + count));\r\n  }\r\n  \r\n  hsd->pTxBuffPtr += 8;\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_SD_MODULE_ENABLED */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_spi.c\r\n  * @author  MCD Application Team\r\n  * @brief   SPI HAL module driver.\r\n  *          This file provides firmware functions to manage the following\r\n  *          functionalities of the Serial Peripheral Interface (SPI) peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + IO operation functions\r\n  *           + Peripheral Control functions\r\n  *           + Peripheral State functions\r\n  *\r\n  @verbatim\r\n  ==============================================================================\r\n                        ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]\r\n      The SPI HAL driver can be used as follows:\r\n\r\n      (#) Declare a SPI_HandleTypeDef handle structure, for example:\r\n          SPI_HandleTypeDef  hspi;\r\n\r\n      (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:\r\n          (##) Enable the SPIx interface clock\r\n          (##) SPI pins configuration\r\n              (+++) Enable the clock for the SPI GPIOs\r\n              (+++) Configure these SPI pins as alternate function push-pull\r\n          (##) NVIC configuration if you need to use interrupt process\r\n              (+++) Configure the SPIx interrupt priority\r\n              (+++) Enable the NVIC SPI IRQ handle\r\n          (##) DMA Configuration if you need to use DMA process\r\n              (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel\r\n              (+++) Enable the DMAx clock\r\n              (+++) Configure the DMA handle parameters\r\n              (+++) Configure the DMA Tx or Rx Stream/Channel\r\n              (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle\r\n              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel\r\n\r\n      (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS\r\n          management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.\r\n\r\n      (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:\r\n          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)\r\n              by calling the customized HAL_SPI_MspInit() API.\r\n     [..]\r\n       Circular mode restriction:\r\n      (#) The DMA circular mode cannot be used when the SPI is configured in these modes:\r\n          (##) Master 2Lines RxOnly\r\n          (##) Master 1Line Rx\r\n      (#) The CRC feature is not managed when the DMA circular mode is enabled\r\n      (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs\r\n          the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks\r\n\r\n     [..]\r\n       (@) The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),\r\n           SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).\r\n       (@)\r\n           (+@) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()\r\n           (+@) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()\r\n           (+@) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()\r\n\r\n  @endverbatim\r\n\r\n       Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,\r\n       the following table resume the max SPI frequency reached with data size 8bits/16bits,\r\n       according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :\r\n\r\n       DataSize = SPI_DATASIZE_8BIT:\r\n       +----------------------------------------------------------------------------------------------+\r\n       |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |\r\n       | Process | Tranfert mode  |---------------------|----------------------|----------------------|\r\n       |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |\r\n       |==============================================================================================|\r\n       |    T    |     Polling    | Fpclk/4  | Fpclk/8  |    NA     |    NA    |    NA     |   NA     |\r\n       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|\r\n       |    /    |     Interrupt  | Fpclk/4  | Fpclk/16 |    NA     |    NA    |    NA     |   NA     |\r\n       |    R    |----------------|----------|----------|-----------|----------|-----------|----------|\r\n       |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |\r\n       |=========|================|==========|==========|===========|==========|===========|==========|\r\n       |         |     Polling    | Fpclk/4  | Fpclk/8  | Fpclk/16  | Fpclk/8  | Fpclk/8   | Fpclk/8  |\r\n       |         |----------------|----------|----------|-----------|----------|-----------|----------|\r\n       |    R    |     Interrupt  | Fpclk/8  | Fpclk/16 | Fpclk/8   | Fpclk/8  | Fpclk/8   | Fpclk/4  |\r\n       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|\r\n       |         |       DMA      | Fpclk/4  | Fpclk/2  | Fpclk/2   | Fpclk/16 | Fpclk/2   | Fpclk/16 |\r\n       |=========|================|==========|==========|===========|==========|===========|==========|\r\n       |         |     Polling    | Fpclk/8  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/8  |\r\n       |         |----------------|----------|----------|-----------|----------|-----------|----------|\r\n       |    T    |     Interrupt  | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/16  | Fpclk/8  |\r\n       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|\r\n       |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/16 |\r\n       +----------------------------------------------------------------------------------------------+\r\n\r\n       DataSize = SPI_DATASIZE_16BIT:\r\n       +----------------------------------------------------------------------------------------------+\r\n       |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |\r\n       | Process | Tranfert mode  |---------------------|----------------------|----------------------|\r\n       |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |\r\n       |==============================================================================================|\r\n       |    T    |     Polling    | Fpclk/4  | Fpclk/8  |    NA     |    NA    |    NA     |   NA     |\r\n       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|\r\n       |    /    |     Interrupt  | Fpclk/4  | Fpclk/16 |    NA     |    NA    |    NA     |   NA     |\r\n       |    R    |----------------|----------|----------|-----------|----------|-----------|----------|\r\n       |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |\r\n       |=========|================|==========|==========|===========|==========|===========|==========|\r\n       |         |     Polling    | Fpclk/4  | Fpclk/8  | Fpclk/16  | Fpclk/8  | Fpclk/8   | Fpclk/8  |\r\n       |         |----------------|----------|----------|-----------|----------|-----------|----------|\r\n       |    R    |     Interrupt  | Fpclk/8  | Fpclk/16 | Fpclk/8   | Fpclk/8  | Fpclk/8   | Fpclk/4  |\r\n       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|\r\n       |         |       DMA      | Fpclk/4  | Fpclk/2  | Fpclk/2   | Fpclk/16 | Fpclk/2   | Fpclk/16 |\r\n       |=========|================|==========|==========|===========|==========|===========|==========|\r\n       |         |     Polling    | Fpclk/8  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/8  |\r\n       |         |----------------|----------|----------|-----------|----------|-----------|----------|\r\n       |    T    |     Interrupt  | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/16  | Fpclk/8  |\r\n       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|\r\n       |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/8   | Fpclk/16 |\r\n       +----------------------------------------------------------------------------------------------+\r\n\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup SPI SPI\r\n  * @brief SPI HAL module driver\r\n  * @{\r\n  */\r\n#ifdef HAL_SPI_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private defines -----------------------------------------------------------*/\r\n/** @defgroup SPI_Private_Constants SPI Private Constants\r\n  * @{\r\n  */\r\n#define SPI_DEFAULT_TIMEOUT 100U\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/** @defgroup SPI_Private_Functions SPI Private Functions\r\n  * @{\r\n  */\r\nstatic void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);\r\nstatic void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);\r\nstatic void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);\r\nstatic void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);\r\nstatic void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);\r\nstatic void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);\r\nstatic void SPI_DMAError(DMA_HandleTypeDef *hdma);\r\nstatic void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);\r\nstatic void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);\r\nstatic void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);\r\nstatic HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,\r\n                                                       uint32_t Timeout, uint32_t Tickstart);\r\nstatic HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,\r\n                                                       uint32_t Timeout, uint32_t Tickstart);\r\nstatic void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\r\nstatic void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\r\nstatic void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\r\nstatic void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\r\nstatic void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\r\nstatic void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\r\nstatic void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\r\nstatic void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\r\n#if (USE_SPI_CRC != 0U)\r\nstatic void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);\r\nstatic void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);\r\nstatic void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);\r\nstatic void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);\r\n#endif /* USE_SPI_CRC */\r\nstatic void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);\r\nstatic void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);\r\nstatic void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);\r\nstatic void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);\r\nstatic void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);\r\nstatic HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);\r\nstatic HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup SPI_Exported_Functions SPI Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions\r\n *  @brief    Initialization and Configuration functions\r\n *\r\n@verbatim\r\n ===============================================================================\r\n              ##### Initialization and de-initialization functions #####\r\n ===============================================================================\r\n    [..]  This subsection provides a set of functions allowing to initialize and\r\n          de-initialize the SPIx peripheral:\r\n\r\n      (+) User must implement HAL_SPI_MspInit() function in which he configures\r\n          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).\r\n\r\n      (+) Call the function HAL_SPI_Init() to configure the selected device with\r\n          the selected configuration:\r\n        (++) Mode\r\n        (++) Direction\r\n        (++) Data Size\r\n        (++) Clock Polarity and Phase\r\n        (++) NSS Management\r\n        (++) BaudRate Prescaler\r\n        (++) FirstBit\r\n        (++) TIMode\r\n        (++) CRC Calculation\r\n        (++) CRC Polynomial if CRC enabled\r\n        (++) CRC Length, used only with Data8 and Data16\r\n        (++) FIFO reception threshold\r\n\r\n      (+) Call the function HAL_SPI_DeInit() to restore the default configuration\r\n          of the selected SPIx peripheral.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initialize the SPI according to the specified parameters\r\n  *         in the SPI_InitTypeDef and initialize the associated handle.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)\r\n{\r\n  uint32_t frxth;\r\n\r\n  /* Check the SPI handle allocation */\r\n  if (hspi == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));\r\n  assert_param(IS_SPI_MODE(hspi->Init.Mode));\r\n  assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));\r\n  assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));\r\n  assert_param(IS_SPI_NSS(hspi->Init.NSS));\r\n  assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));\r\n  assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));\r\n  assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));\r\n  assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));\r\n  if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)\r\n  {\r\n    assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));\r\n    assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));\r\n  }\r\n#if (USE_SPI_CRC != 0U)\r\n  assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));\r\n  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n  {\r\n    assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));\r\n    assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));\r\n  }\r\n#else\r\n  hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;\r\n#endif /* USE_SPI_CRC */\r\n\r\n  if (hspi->State == HAL_SPI_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    hspi->Lock = HAL_UNLOCKED;\r\n\r\n    /* Init the low level hardware : GPIO, CLOCK, NVIC... */\r\n    HAL_SPI_MspInit(hspi);\r\n  }\r\n\r\n  hspi->State = HAL_SPI_STATE_BUSY;\r\n\r\n  /* Disable the selected SPI peripheral */\r\n  __HAL_SPI_DISABLE(hspi);\r\n\r\n  /* Align by default the rs fifo threshold on the data size */\r\n  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r\n  {\r\n    frxth = SPI_RXFIFO_THRESHOLD_HF;\r\n  }\r\n  else\r\n  {\r\n    frxth = SPI_RXFIFO_THRESHOLD_QF;\r\n  }\r\n\r\n  /* CRC calculation is valid only for 16Bit and 8 Bit */\r\n  if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))\r\n  {\r\n    /* CRC must be disabled */\r\n    hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;\r\n  }\r\n\r\n  /* Align the CRC Length on the data size */\r\n  if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)\r\n  {\r\n    /* CRC Length aligned on the data size : value set by default */\r\n    if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r\n    {\r\n      hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;\r\n    }\r\n    else\r\n    {\r\n      hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;\r\n    }\r\n  }\r\n\r\n  /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/\r\n  /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,\r\n  Communication speed, First bit, CRC calculation state */\r\n  WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction |\r\n                                  hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |\r\n                                  hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit  | hspi->Init.CRCCalculation));\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Configure : CRC Length */\r\n  if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)\r\n  {\r\n    hspi->Instance->CR1 |= SPI_CR1_CRCL;\r\n  }\r\n#endif /* USE_SPI_CRC */\r\n\r\n  /* Configure : NSS management, TI Mode and Rx Fifo Threshold */\r\n  WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode |\r\n                                  hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth);\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n  /*---------------------------- SPIx CRCPOLY Configuration ------------------*/\r\n  /* Configure : CRC Polynomial */\r\n  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n  {\r\n    WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);\r\n  }\r\n#endif /* USE_SPI_CRC */\r\n\r\n#if defined(SPI_I2SCFGR_I2SMOD)\r\n  /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */\r\n  CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);\r\n#endif /* SPI_I2SCFGR_I2SMOD */\r\n\r\n  hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r\n  hspi->State     = HAL_SPI_STATE_READY;\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  De-Initialize the SPI peripheral.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Check the SPI handle allocation */\r\n  if (hspi == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check SPI Instance parameter */\r\n  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));\r\n\r\n  hspi->State = HAL_SPI_STATE_BUSY;\r\n\r\n  /* Disable the SPI Peripheral Clock */\r\n  __HAL_SPI_DISABLE(hspi);\r\n\r\n  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */\r\n  HAL_SPI_MspDeInit(hspi);\r\n\r\n  hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r\n  hspi->State = HAL_SPI_STATE_RESET;\r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hspi);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initialize the SPI MSP.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hspi);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_SPI_MspInit should be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  De-Initialize the SPI MSP.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hspi);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_SPI_MspDeInit should be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_Exported_Functions_Group2 IO operation functions\r\n *  @brief   Data transfers functions\r\n *\r\n@verbatim\r\n  ==============================================================================\r\n                      ##### IO operation functions #####\r\n ===============================================================================\r\n [..]\r\n    This subsection provides a set of functions allowing to manage the SPI\r\n    data transfers.\r\n\r\n    [..] The SPI supports master and slave mode :\r\n\r\n    (#) There are two modes of transfer:\r\n       (++) Blocking mode: The communication is performed in polling mode.\r\n            The HAL status of all data processing is returned by the same function\r\n            after finishing transfer.\r\n       (++) No-Blocking mode: The communication is performed using Interrupts\r\n            or DMA, These APIs return the HAL status.\r\n            The end of the data processing will be indicated through the\r\n            dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when\r\n            using DMA mode.\r\n            The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks\r\n            will be executed respectively at the end of the transmit or Receive process\r\n            The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected\r\n\r\n    (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)\r\n        exist for 1Line (simplex) and 2Lines (full duplex) modes.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Transmit an amount of data in blocking mode.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @param  pData pointer to data buffer\r\n  * @param  Size amount of data to be sent\r\n  * @param  Timeout Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0U;\r\n  HAL_StatusTypeDef errorcode = HAL_OK;\r\n\r\n  /* Check Direction parameter */\r\n  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));\r\n\r\n  /* Process Locked */\r\n  __HAL_LOCK(hspi);\r\n\r\n  /* Init tickstart for timeout management*/\r\n  tickstart = HAL_GetTick();\r\n\r\n  if (hspi->State != HAL_SPI_STATE_READY)\r\n  {\r\n    errorcode = HAL_BUSY;\r\n    goto error;\r\n  }\r\n\r\n  if ((pData == NULL) || (Size == 0U))\r\n  {\r\n    errorcode = HAL_ERROR;\r\n    goto error;\r\n  }\r\n\r\n  /* Set the transaction information */\r\n  hspi->State       = HAL_SPI_STATE_BUSY_TX;\r\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r\n  hspi->pTxBuffPtr  = (uint8_t *)pData;\r\n  hspi->TxXferSize  = Size;\r\n  hspi->TxXferCount = Size;\r\n\r\n  /*Init field not used in handle to zero */\r\n  hspi->pRxBuffPtr  = (uint8_t *)NULL;\r\n  hspi->RxXferSize  = 0U;\r\n  hspi->RxXferCount = 0U;\r\n  hspi->TxISR       = NULL;\r\n  hspi->RxISR       = NULL;\r\n\r\n  /* Configure communication direction : 1Line */\r\n  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)\r\n  {\r\n    SPI_1LINE_TX(hspi);\r\n  }\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Reset CRC Calculation */\r\n  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n  {\r\n    SPI_RESET_CRC(hspi);\r\n  }\r\n#endif /* USE_SPI_CRC */\r\n\r\n  /* Check if the SPI is already enabled */\r\n  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r\n  {\r\n    /* Enable SPI peripheral */\r\n    __HAL_SPI_ENABLE(hspi);\r\n  }\r\n\r\n  /* Transmit data in 16 Bit mode */\r\n  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r\n  {\r\n    /* Transmit data in 16 Bit mode */\r\n    while (hspi->TxXferCount > 0U)\r\n    {\r\n      /* Wait until TXE flag is set to send data */\r\n      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))\r\n      {\r\n        hspi->Instance->DR = *((uint16_t *)pData);\r\n        pData += sizeof(uint16_t);\r\n        hspi->TxXferCount--;\r\n      }\r\n      else\r\n      {\r\n        /* Timeout management */\r\n        if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout)))\r\n        {\r\n          errorcode = HAL_TIMEOUT;\r\n          goto error;\r\n        }\r\n      }\r\n    }\r\n  }\r\n  /* Transmit data in 8 Bit mode */\r\n  else\r\n  {\r\n    while (hspi->TxXferCount > 0U)\r\n    {\r\n      /* Wait until TXE flag is set to send data */\r\n      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))\r\n      {\r\n        if (hspi->TxXferCount > 1U)\r\n        {\r\n          /* write on the data register in packing mode */\r\n          hspi->Instance->DR = *((uint16_t *)pData);\r\n          pData += sizeof(uint16_t);\r\n          hspi->TxXferCount -= 2U;\r\n        }\r\n        else\r\n        {\r\n          *((__IO uint8_t *)&hspi->Instance->DR) = (*pData++);\r\n          hspi->TxXferCount--;\r\n        }\r\n      }\r\n      else\r\n      {\r\n        /* Timeout management */\r\n        if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout)))\r\n        {\r\n          errorcode = HAL_TIMEOUT;\r\n          goto error;\r\n        }\r\n      }\r\n    }\r\n  }\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Enable CRC Transmission */\r\n  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n  {\r\n    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r\n  }\r\n#endif /* USE_SPI_CRC */\r\n\r\n  /* Check the end of the transaction */\r\n  if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)\r\n  {\r\n    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;\r\n  }\r\n\r\n  /* Clear overrun flag in 2 Lines communication mode because received is not read */\r\n  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)\r\n  {\r\n    __HAL_SPI_CLEAR_OVRFLAG(hspi);\r\n  }\r\n\r\n  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r\n  {\r\n    errorcode = HAL_ERROR;\r\n  }\r\n\r\nerror:\r\n  hspi->State = HAL_SPI_STATE_READY;\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hspi);\r\n  return errorcode;\r\n}\r\n\r\n/**\r\n  * @brief  Receive an amount of data in blocking mode.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @param  pData pointer to data buffer\r\n  * @param  Size amount of data to be received\r\n  * @param  Timeout Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r\n{\r\n#if (USE_SPI_CRC != 0U)\r\n  __IO uint16_t tmpreg = 0U;\r\n#endif /* USE_SPI_CRC */\r\n  uint32_t tickstart = 0U;\r\n  HAL_StatusTypeDef errorcode = HAL_OK;\r\n\r\n  if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))\r\n  {\r\n    hspi->State = HAL_SPI_STATE_BUSY_RX;\r\n    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */\r\n    return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);\r\n  }\r\n\r\n  /* Process Locked */\r\n  __HAL_LOCK(hspi);\r\n\r\n  /* Init tickstart for timeout management*/\r\n  tickstart = HAL_GetTick();\r\n\r\n  if (hspi->State != HAL_SPI_STATE_READY)\r\n  {\r\n    errorcode = HAL_BUSY;\r\n    goto error;\r\n  }\r\n\r\n  if ((pData == NULL) || (Size == 0U))\r\n  {\r\n    errorcode = HAL_ERROR;\r\n    goto error;\r\n  }\r\n\r\n  /* Set the transaction information */\r\n  hspi->State       = HAL_SPI_STATE_BUSY_RX;\r\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r\n  hspi->pRxBuffPtr  = (uint8_t *)pData;\r\n  hspi->RxXferSize  = Size;\r\n  hspi->RxXferCount = Size;\r\n\r\n  /*Init field not used in handle to zero */\r\n  hspi->pTxBuffPtr  = (uint8_t *)NULL;\r\n  hspi->TxXferSize  = 0U;\r\n  hspi->TxXferCount = 0U;\r\n  hspi->RxISR       = NULL;\r\n  hspi->TxISR       = NULL;\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Reset CRC Calculation */\r\n  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n  {\r\n    SPI_RESET_CRC(hspi);\r\n    /* this is done to handle the CRCNEXT before the latest data */\r\n    hspi->RxXferCount--;\r\n  }\r\n#endif /* USE_SPI_CRC */\r\n\r\n  /* Set the Rx Fifo threshold */\r\n  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r\n  {\r\n    /* set fiforxthreshold according the reception data length: 16bit */\r\n    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r\n  }\r\n  else\r\n  {\r\n    /* set fiforxthreshold according the reception data length: 8bit */\r\n    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r\n  }\r\n\r\n  /* Configure communication direction: 1Line */\r\n  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)\r\n  {\r\n    SPI_1LINE_RX(hspi);\r\n  }\r\n\r\n  /* Check if the SPI is already enabled */\r\n  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r\n  {\r\n    /* Enable SPI peripheral */\r\n    __HAL_SPI_ENABLE(hspi);\r\n  }\r\n\r\n  /* Receive data in 8 Bit mode */\r\n  if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)\r\n  {\r\n    /* Transfer loop */\r\n    while (hspi->RxXferCount > 0U)\r\n    {\r\n      /* Check the RXNE flag */\r\n      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))\r\n      {\r\n        /* read the received data */\r\n        (*pData) = *(__IO uint8_t *)&hspi->Instance->DR;\r\n        pData += sizeof(uint8_t);\r\n        hspi->RxXferCount--;\r\n      }\r\n      else\r\n      {\r\n        /* Timeout management */\r\n        if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout)))\r\n        {\r\n          errorcode = HAL_TIMEOUT;\r\n          goto error;\r\n        }\r\n      }\r\n    }\r\n  }\r\n  else\r\n  {\r\n    /* Transfer loop */\r\n    while (hspi->RxXferCount > 0U)\r\n    {\r\n      /* Check the RXNE flag */\r\n      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))\r\n      {\r\n        *((uint16_t *)pData) = hspi->Instance->DR;\r\n        pData += sizeof(uint16_t);\r\n        hspi->RxXferCount--;\r\n      }\r\n      else\r\n      {\r\n        /* Timeout management */\r\n        if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout)))\r\n        {\r\n          errorcode = HAL_TIMEOUT;\r\n          goto error;\r\n        }\r\n      }\r\n    }\r\n  }\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Handle the CRC Transmission */\r\n  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n  {\r\n    /* freeze the CRC before the latest data */\r\n    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r\n\r\n    /* Read the latest data */\r\n    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)\r\n    {\r\n      /* the latest data has not been received */\r\n      errorcode = HAL_TIMEOUT;\r\n      goto error;\r\n    }\r\n\r\n    /* Receive last data in 16 Bit mode */\r\n    if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r\n    {\r\n      *((uint16_t *)pData) = hspi->Instance->DR;\r\n    }\r\n    /* Receive last data in 8 Bit mode */\r\n    else\r\n    {\r\n      (*pData) = *(__IO uint8_t *)&hspi->Instance->DR;\r\n    }\r\n\r\n    /* Wait the CRC data */\r\n    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)\r\n    {\r\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r\n      errorcode = HAL_TIMEOUT;\r\n      goto error;\r\n    }\r\n\r\n    /* Read CRC to Flush DR and RXNE flag */\r\n    if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)\r\n    {\r\n      tmpreg = hspi->Instance->DR;\r\n      /* To avoid GCC warning */\r\n      UNUSED(tmpreg);\r\n    }\r\n    else\r\n    {\r\n      tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;\r\n      /* To avoid GCC warning */\r\n      UNUSED(tmpreg);\r\n\r\n      if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))\r\n      {\r\n        if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout, tickstart) != HAL_OK)\r\n        {\r\n          /* Error on the CRC reception */\r\n          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r\n          errorcode = HAL_TIMEOUT;\r\n          goto error;\r\n        }\r\n        tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;\r\n        /* To avoid GCC warning */\r\n        UNUSED(tmpreg);\r\n      }\r\n    }\r\n  }\r\n#endif /* USE_SPI_CRC */\r\n\r\n  /* Check the end of the transaction */\r\n  if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)\r\n  {\r\n    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;\r\n  }\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Check if CRC error occurred */\r\n  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))\r\n  {\r\n    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r\n    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r\n  }\r\n#endif /* USE_SPI_CRC */\r\n\r\n  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r\n  {\r\n    errorcode = HAL_ERROR;\r\n  }\r\n\r\nerror :\r\n  hspi->State = HAL_SPI_STATE_READY;\r\n  __HAL_UNLOCK(hspi);\r\n  return errorcode;\r\n}\r\n\r\n/**\r\n  * @brief  Transmit and Receive an amount of data in blocking mode.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @param  pTxData pointer to transmission data buffer\r\n  * @param  pRxData pointer to reception data buffer\r\n  * @param  Size amount of data to be sent and received\r\n  * @param  Timeout Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,\r\n                                          uint32_t Timeout)\r\n{\r\n  uint32_t tmp = 0U, tmp1 = 0U;\r\n#if (USE_SPI_CRC != 0U)\r\n  __IO uint16_t tmpreg = 0U;\r\n#endif /* USE_SPI_CRC */\r\n  uint32_t tickstart = 0U;\r\n  /* Variable used to alternate Rx and Tx during transfer */\r\n  uint32_t txallowed = 1U;\r\n  HAL_StatusTypeDef errorcode = HAL_OK;\r\n\r\n  /* Check Direction parameter */\r\n  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));\r\n\r\n  /* Process Locked */\r\n  __HAL_LOCK(hspi);\r\n\r\n  /* Init tickstart for timeout management*/\r\n  tickstart = HAL_GetTick();\r\n\r\n  tmp  = hspi->State;\r\n  tmp1 = hspi->Init.Mode;\r\n\r\n  if (!((tmp == HAL_SPI_STATE_READY) || \\\r\n        ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))\r\n  {\r\n    errorcode = HAL_BUSY;\r\n    goto error;\r\n  }\r\n\r\n  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))\r\n  {\r\n    errorcode = HAL_ERROR;\r\n    goto error;\r\n  }\r\n\r\n  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */\r\n  if (hspi->State != HAL_SPI_STATE_BUSY_RX)\r\n  {\r\n    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;\r\n  }\r\n\r\n  /* Set the transaction information */\r\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r\n  hspi->pRxBuffPtr  = (uint8_t *)pRxData;\r\n  hspi->RxXferCount = Size;\r\n  hspi->RxXferSize  = Size;\r\n  hspi->pTxBuffPtr  = (uint8_t *)pTxData;\r\n  hspi->TxXferCount = Size;\r\n  hspi->TxXferSize  = Size;\r\n\r\n  /*Init field not used in handle to zero */\r\n  hspi->RxISR       = NULL;\r\n  hspi->TxISR       = NULL;\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Reset CRC Calculation */\r\n  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n  {\r\n    SPI_RESET_CRC(hspi);\r\n  }\r\n#endif /* USE_SPI_CRC */\r\n\r\n  /* Set the Rx Fifo threshold */\r\n  if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1))\r\n  {\r\n    /* set fiforxthreshold according the reception data length: 16bit */\r\n    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r\n  }\r\n  else\r\n  {\r\n    /* set fiforxthreshold according the reception data length: 8bit */\r\n    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r\n  }\r\n\r\n  /* Check if the SPI is already enabled */\r\n  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r\n  {\r\n    /* Enable SPI peripheral */\r\n    __HAL_SPI_ENABLE(hspi);\r\n  }\r\n\r\n  /* Transmit and Receive data in 16 Bit mode */\r\n  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r\n  {\r\n    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))\r\n    {\r\n      hspi->Instance->DR = *((uint16_t *)pTxData);\r\n      pTxData += sizeof(uint16_t);\r\n      hspi->TxXferCount--;\r\n    }\r\n    while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))\r\n    {\r\n      /* Check TXE flag */\r\n      if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))\r\n      {\r\n        hspi->Instance->DR = *((uint16_t *)pTxData);\r\n        pTxData += sizeof(uint16_t);\r\n        hspi->TxXferCount--;\r\n        /* Next Data is a reception (Rx). Tx not allowed */\r\n        txallowed = 0U;\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n        /* Enable CRC Transmission */\r\n        if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\r\n        {\r\n          /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */\r\n          if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))\r\n          {\r\n            SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);\r\n          }\r\n          SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r\n        }\r\n#endif /* USE_SPI_CRC */\r\n      }\r\n\r\n      /* Check RXNE flag */\r\n      if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))\r\n      {\r\n        *((uint16_t *)pRxData) = hspi->Instance->DR;\r\n        pRxData += sizeof(uint16_t);\r\n        hspi->RxXferCount--;\r\n        /* Next Data is a Transmission (Tx). Tx is allowed */\r\n        txallowed = 1U;\r\n      }\r\n      if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout))\r\n      {\r\n        errorcode = HAL_TIMEOUT;\r\n        goto error;\r\n      }\r\n    }\r\n  }\r\n  /* Transmit and Receive data in 8 Bit mode */\r\n  else\r\n  {\r\n    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))\r\n    {\r\n      *((__IO uint8_t *)&hspi->Instance->DR) = (*pTxData);\r\n      pTxData += sizeof(uint8_t);\r\n      hspi->TxXferCount--;\r\n    }\r\n    while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))\r\n    {\r\n      /* check TXE flag */\r\n      if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))\r\n      {\r\n        if (hspi->TxXferCount > 1U)\r\n        {\r\n          hspi->Instance->DR = *((uint16_t *)pTxData);\r\n          pTxData += sizeof(uint16_t);\r\n          hspi->TxXferCount -= 2U;\r\n        }\r\n        else\r\n        {\r\n          *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);\r\n          hspi->TxXferCount--;\r\n        }\r\n        /* Next Data is a reception (Rx). Tx not allowed */\r\n        txallowed = 0U;\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n        /* Enable CRC Transmission */\r\n        if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\r\n        {\r\n          /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */\r\n          if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))\r\n          {\r\n            SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);\r\n          }\r\n          SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r\n        }\r\n#endif /* USE_SPI_CRC */\r\n      }\r\n\r\n      /* Wait until RXNE flag is reset */\r\n      if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))\r\n      {\r\n        if (hspi->RxXferCount > 1U)\r\n        {\r\n          *((uint16_t *)pRxData) = hspi->Instance->DR;\r\n          pRxData += sizeof(uint16_t);\r\n          hspi->RxXferCount -= 2U;\r\n          if (hspi->RxXferCount <= 1U)\r\n          {\r\n            /* set fiforxthreshold before to switch on 8 bit data size */\r\n            SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r\n          }\r\n        }\r\n        else\r\n        {\r\n          (*pRxData++) = *(__IO uint8_t *)&hspi->Instance->DR;\r\n          hspi->RxXferCount--;\r\n        }\r\n        /* Next Data is a Transmission (Tx). Tx is allowed */\r\n        txallowed = 1U;\r\n      }\r\n      if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >=  Timeout))\r\n      {\r\n        errorcode = HAL_TIMEOUT;\r\n        goto error;\r\n      }\r\n    }\r\n  }\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Read CRC from DR to close CRC calculation process */\r\n  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n  {\r\n    /* Wait until TXE flag */\r\n    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)\r\n    {\r\n      /* Error on the CRC reception */\r\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r\n      errorcode = HAL_TIMEOUT;\r\n      goto error;\r\n    }\r\n    /* Read CRC */\r\n    if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)\r\n    {\r\n      tmpreg = hspi->Instance->DR;\r\n      /* To avoid GCC warning */\r\n      UNUSED(tmpreg);\r\n    }\r\n    else\r\n    {\r\n      tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;\r\n      /* To avoid GCC warning */\r\n      UNUSED(tmpreg);\r\n\r\n      if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)\r\n      {\r\n        if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)\r\n        {\r\n          /* Error on the CRC reception */\r\n          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r\n          errorcode = HAL_TIMEOUT;\r\n          goto error;\r\n        }\r\n        tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;\r\n        /* To avoid GCC warning */\r\n        UNUSED(tmpreg);\r\n      }\r\n    }\r\n  }\r\n\r\n  /* Check if CRC error occurred */\r\n  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))\r\n  {\r\n    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r\n    /* Clear CRC Flag */\r\n    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r\n\r\n    errorcode = HAL_ERROR;\r\n  }\r\n#endif /* USE_SPI_CRC */\r\n\r\n  /* Check the end of the transaction */\r\n  if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)\r\n  {\r\n    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;\r\n  }\r\n\r\n  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r\n  {\r\n    errorcode = HAL_ERROR;\r\n  }\r\n\r\nerror :\r\n  hspi->State = HAL_SPI_STATE_READY;\r\n  __HAL_UNLOCK(hspi);\r\n  return errorcode;\r\n}\r\n\r\n/**\r\n  * @brief  Transmit an amount of data in non-blocking mode with Interrupt.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @param  pData pointer to data buffer\r\n  * @param  Size amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\r\n{\r\n  HAL_StatusTypeDef errorcode = HAL_OK;\r\n\r\n  /* Check Direction parameter */\r\n  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));\r\n\r\n  /* Process Locked */\r\n  __HAL_LOCK(hspi);\r\n\r\n  if ((pData == NULL) || (Size == 0U))\r\n  {\r\n    errorcode = HAL_ERROR;\r\n    goto error;\r\n  }\r\n\r\n  if (hspi->State != HAL_SPI_STATE_READY)\r\n  {\r\n    errorcode = HAL_BUSY;\r\n    goto error;\r\n  }\r\n\r\n  /* Set the transaction information */\r\n  hspi->State       = HAL_SPI_STATE_BUSY_TX;\r\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r\n  hspi->pTxBuffPtr  = (uint8_t *)pData;\r\n  hspi->TxXferSize  = Size;\r\n  hspi->TxXferCount = Size;\r\n\r\n  /* Init field not used in handle to zero */\r\n  hspi->pRxBuffPtr  = (uint8_t *)NULL;\r\n  hspi->RxXferSize  = 0U;\r\n  hspi->RxXferCount = 0U;\r\n  hspi->RxISR       = NULL;\r\n\r\n  /* Set the function for IT treatment */\r\n  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r\n  {\r\n    hspi->TxISR = SPI_TxISR_16BIT;\r\n  }\r\n  else\r\n  {\r\n    hspi->TxISR = SPI_TxISR_8BIT;\r\n  }\r\n\r\n  /* Configure communication direction : 1Line */\r\n  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)\r\n  {\r\n    SPI_1LINE_TX(hspi);\r\n  }\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Reset CRC Calculation */\r\n  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n  {\r\n    SPI_RESET_CRC(hspi);\r\n  }\r\n#endif /* USE_SPI_CRC */\r\n\r\n  /* Enable TXE and ERR interrupt */\r\n  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));\r\n\r\n\r\n  /* Check if the SPI is already enabled */\r\n  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r\n  {\r\n    /* Enable SPI peripheral */\r\n    __HAL_SPI_ENABLE(hspi);\r\n  }\r\n\r\nerror :\r\n  __HAL_UNLOCK(hspi);\r\n  return errorcode;\r\n}\r\n\r\n/**\r\n  * @brief  Receive an amount of data in non-blocking mode with Interrupt.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @param  pData pointer to data buffer\r\n  * @param  Size amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\r\n{\r\n  HAL_StatusTypeDef errorcode = HAL_OK;\r\n\r\n  if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))\r\n  {\r\n    hspi->State = HAL_SPI_STATE_BUSY_RX;\r\n    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */\r\n    return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);\r\n  }\r\n\r\n  /* Process Locked */\r\n  __HAL_LOCK(hspi);\r\n\r\n  if (hspi->State != HAL_SPI_STATE_READY)\r\n  {\r\n    errorcode = HAL_BUSY;\r\n    goto error;\r\n  }\r\n\r\n  if ((pData == NULL) || (Size == 0U))\r\n  {\r\n    errorcode = HAL_ERROR;\r\n    goto error;\r\n  }\r\n\r\n  /* Set the transaction information */\r\n  hspi->State       = HAL_SPI_STATE_BUSY_RX;\r\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r\n  hspi->pRxBuffPtr  = (uint8_t *)pData;\r\n  hspi->RxXferSize  = Size;\r\n  hspi->RxXferCount = Size;\r\n\r\n  /* Init field not used in handle to zero */\r\n  hspi->pTxBuffPtr  = (uint8_t *)NULL;\r\n  hspi->TxXferSize  = 0U;\r\n  hspi->TxXferCount = 0U;\r\n  hspi->TxISR       = NULL;\r\n\r\n  /* check the data size to adapt Rx threshold and the set the function for IT treatment */\r\n  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r\n  {\r\n    /* set fiforxthreshold according the reception data length: 16 bit */\r\n    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r\n    hspi->RxISR = SPI_RxISR_16BIT;\r\n  }\r\n  else\r\n  {\r\n    /* set fiforxthreshold according the reception data length: 8 bit */\r\n    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r\n    hspi->RxISR = SPI_RxISR_8BIT;\r\n  }\r\n\r\n  /* Configure communication direction : 1Line */\r\n  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)\r\n  {\r\n    SPI_1LINE_RX(hspi);\r\n  }\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Reset CRC Calculation */\r\n  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n  {\r\n    hspi->CRCSize = 1U;\r\n    if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))\r\n    {\r\n      hspi->CRCSize = 2U;\r\n    }\r\n    SPI_RESET_CRC(hspi);\r\n  }\r\n  else\r\n  {\r\n    hspi->CRCSize = 0U;\r\n  }\r\n#endif /* USE_SPI_CRC */\r\n\r\n  /* Enable TXE and ERR interrupt */\r\n  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\r\n\r\n  /* Note : The SPI must be enabled after unlocking current process\r\n            to avoid the risk of SPI interrupt handle execution before current\r\n            process unlock */\r\n\r\n  /* Check if the SPI is already enabled */\r\n  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r\n  {\r\n    /* Enable SPI peripheral */\r\n    __HAL_SPI_ENABLE(hspi);\r\n  }\r\n\r\nerror :\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hspi);\r\n  return errorcode;\r\n}\r\n\r\n/**\r\n  * @brief  Transmit and Receive an amount of data in non-blocking mode with Interrupt.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @param  pTxData pointer to transmission data buffer\r\n  * @param  pRxData pointer to reception data buffer\r\n  * @param  Size amount of data to be sent and received\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)\r\n{\r\n  uint32_t tmp = 0U, tmp1 = 0U;\r\n  HAL_StatusTypeDef errorcode = HAL_OK;\r\n\r\n  /* Check Direction parameter */\r\n  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hspi);\r\n\r\n  tmp  = hspi->State;\r\n  tmp1 = hspi->Init.Mode;\r\n\r\n  if (!((tmp == HAL_SPI_STATE_READY) || \\\r\n        ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))\r\n  {\r\n    errorcode = HAL_BUSY;\r\n    goto error;\r\n  }\r\n\r\n  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))\r\n  {\r\n    errorcode = HAL_ERROR;\r\n    goto error;\r\n  }\r\n\r\n  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */\r\n  if (hspi->State != HAL_SPI_STATE_BUSY_RX)\r\n  {\r\n    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;\r\n  }\r\n\r\n  /* Set the transaction information */\r\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r\n  hspi->pTxBuffPtr  = (uint8_t *)pTxData;\r\n  hspi->TxXferSize  = Size;\r\n  hspi->TxXferCount = Size;\r\n  hspi->pRxBuffPtr  = (uint8_t *)pRxData;\r\n  hspi->RxXferSize  = Size;\r\n  hspi->RxXferCount = Size;\r\n\r\n  /* Set the function for IT treatment */\r\n  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r\n  {\r\n    hspi->RxISR     = SPI_2linesRxISR_16BIT;\r\n    hspi->TxISR     = SPI_2linesTxISR_16BIT;\r\n  }\r\n  else\r\n  {\r\n    hspi->RxISR     = SPI_2linesRxISR_8BIT;\r\n    hspi->TxISR     = SPI_2linesTxISR_8BIT;\r\n  }\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Reset CRC Calculation */\r\n  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n  {\r\n    hspi->CRCSize = 1U;\r\n    if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))\r\n    {\r\n      hspi->CRCSize = 2U;\r\n    }\r\n    SPI_RESET_CRC(hspi);\r\n  }\r\n  else\r\n  {\r\n    hspi->CRCSize = 0U;\r\n  }\r\n#endif /* USE_SPI_CRC */\r\n\r\n  /* check if packing mode is enabled and if there is more than 2 data to receive */\r\n  if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2U))\r\n  {\r\n    /* set fiforxthreshold according the reception data length: 16 bit */\r\n    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r\n  }\r\n  else\r\n  {\r\n    /* set fiforxthreshold according the reception data length: 8 bit */\r\n    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r\n  }\r\n\r\n  /* Enable TXE, RXNE and ERR interrupt */\r\n  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));\r\n\r\n  /* Check if the SPI is already enabled */\r\n  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r\n  {\r\n    /* Enable SPI peripheral */\r\n    __HAL_SPI_ENABLE(hspi);\r\n  }\r\n\r\nerror :\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hspi);\r\n  return errorcode;\r\n}\r\n\r\n/**\r\n  * @brief  Transmit an amount of data in non-blocking mode with DMA.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @param  pData pointer to data buffer\r\n  * @param  Size amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\r\n{\r\n  HAL_StatusTypeDef errorcode = HAL_OK;\r\n\r\n  /* Check Direction parameter */\r\n  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));\r\n\r\n  /* Process Locked */\r\n  __HAL_LOCK(hspi);\r\n\r\n  if (hspi->State != HAL_SPI_STATE_READY)\r\n  {\r\n    errorcode = HAL_BUSY;\r\n    goto error;\r\n  }\r\n\r\n  if ((pData == NULL) || (Size == 0U))\r\n  {\r\n    errorcode = HAL_ERROR;\r\n    goto error;\r\n  }\r\n\r\n  /* Set the transaction information */\r\n  hspi->State       = HAL_SPI_STATE_BUSY_TX;\r\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r\n  hspi->pTxBuffPtr  = (uint8_t *)pData;\r\n  hspi->TxXferSize  = Size;\r\n  hspi->TxXferCount = Size;\r\n\r\n  /* Init field not used in handle to zero */\r\n  hspi->pRxBuffPtr  = (uint8_t *)NULL;\r\n  hspi->TxISR       = NULL;\r\n  hspi->RxISR       = NULL;\r\n  hspi->RxXferSize  = 0U;\r\n  hspi->RxXferCount = 0U;\r\n\r\n  /* Configure communication direction : 1Line */\r\n  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)\r\n  {\r\n    SPI_1LINE_TX(hspi);\r\n  }\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Reset CRC Calculation */\r\n  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n  {\r\n    SPI_RESET_CRC(hspi);\r\n  }\r\n#endif /* USE_SPI_CRC */\r\n\r\n  /* Set the SPI TxDMA Half transfer complete callback */\r\n  hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;\r\n\r\n  /* Set the SPI TxDMA transfer complete callback */\r\n  hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;\r\n\r\n  /* Set the DMA error callback */\r\n  hspi->hdmatx->XferErrorCallback = SPI_DMAError;\r\n\r\n  /* Set the DMA AbortCpltCallback */\r\n  hspi->hdmatx->XferAbortCallback = NULL;\r\n\r\n  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r\n  /* packing mode is enabled only if the DMA setting is HALWORD */\r\n  if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))\r\n  {\r\n    /* Check the even/odd of the data size + crc if enabled */\r\n    if ((hspi->TxXferCount & 0x1U) == 0U)\r\n    {\r\n      CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r\n      hspi->TxXferCount = (hspi->TxXferCount >> 1U);\r\n    }\r\n    else\r\n    {\r\n      SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r\n      hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;\r\n    }\r\n  }\r\n\r\n  /* Enable the Tx DMA Stream/Channel */\r\n  HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);\r\n\r\n  /* Check if the SPI is already enabled */\r\n  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r\n  {\r\n    /* Enable SPI peripheral */\r\n    __HAL_SPI_ENABLE(hspi);\r\n  }\r\n\r\n  /* Enable the SPI Error Interrupt Bit */\r\n  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));\r\n\r\n  /* Enable Tx DMA Request */\r\n  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);\r\n\r\nerror :\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hspi);\r\n  return errorcode;\r\n}\r\n\r\n/**\r\n  * @brief  Receive an amount of data in non-blocking mode with DMA.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @param  pData pointer to data buffer\r\n  * @note   When the CRC feature is enabled the pData Length must be Size + 1.\r\n  * @param  Size amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\r\n{\r\n  HAL_StatusTypeDef errorcode = HAL_OK;\r\n\r\n  if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))\r\n  {\r\n    hspi->State = HAL_SPI_STATE_BUSY_RX;\r\n    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */\r\n    return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);\r\n  }\r\n\r\n  /* Process Locked */\r\n  __HAL_LOCK(hspi);\r\n\r\n  if (hspi->State != HAL_SPI_STATE_READY)\r\n  {\r\n    errorcode = HAL_BUSY;\r\n    goto error;\r\n  }\r\n\r\n  if ((pData == NULL) || (Size == 0U))\r\n  {\r\n    errorcode = HAL_ERROR;\r\n    goto error;\r\n  }\r\n\r\n  /* Set the transaction information */\r\n  hspi->State       = HAL_SPI_STATE_BUSY_RX;\r\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r\n  hspi->pRxBuffPtr  = (uint8_t *)pData;\r\n  hspi->RxXferSize  = Size;\r\n  hspi->RxXferCount = Size;\r\n\r\n  /*Init field not used in handle to zero */\r\n  hspi->RxISR       = NULL;\r\n  hspi->TxISR       = NULL;\r\n  hspi->TxXferSize  = 0U;\r\n  hspi->TxXferCount = 0U;\r\n\r\n  /* Configure communication direction : 1Line */\r\n  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)\r\n  {\r\n    SPI_1LINE_RX(hspi);\r\n  }\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Reset CRC Calculation */\r\n  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n  {\r\n    SPI_RESET_CRC(hspi);\r\n  }\r\n#endif /* USE_SPI_CRC */\r\n\r\n  /* packing mode management is enabled by the DMA settings */\r\n  if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))\r\n  {\r\n    /* Restriction the DMA data received is not allowed in this mode */\r\n    errorcode = HAL_ERROR;\r\n    goto error;\r\n  }\r\n\r\n  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);\r\n  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r\n  {\r\n    /* set fiforxthreshold according the reception data length: 16bit */\r\n    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r\n  }\r\n  else\r\n  {\r\n    /* set fiforxthreshold according the reception data length: 8bit */\r\n    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r\n  }\r\n\r\n  /* Set the SPI RxDMA Half transfer complete callback */\r\n  hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;\r\n\r\n  /* Set the SPI Rx DMA transfer complete callback */\r\n  hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;\r\n\r\n  /* Set the DMA error callback */\r\n  hspi->hdmarx->XferErrorCallback = SPI_DMAError;\r\n\r\n  /* Set the DMA AbortCpltCallback */\r\n  hspi->hdmarx->XferAbortCallback = NULL;\r\n\r\n  /* Enable the Rx DMA Stream/Channel  */\r\n  HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);\r\n\r\n  /* Check if the SPI is already enabled */\r\n  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r\n  {\r\n    /* Enable SPI peripheral */\r\n    __HAL_SPI_ENABLE(hspi);\r\n  }\r\n\r\n  /* Enable the SPI Error Interrupt Bit */\r\n  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));\r\n\r\n  /* Enable Rx DMA Request */\r\n  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);\r\n\r\nerror:\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hspi);\r\n  return errorcode;\r\n}\r\n\r\n/**\r\n  * @brief  Transmit and Receive an amount of data in non-blocking mode with DMA.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @param  pTxData pointer to transmission data buffer\r\n  * @param  pRxData pointer to reception data buffer\r\n  * @note   When the CRC feature is enabled the pRxData Length must be Size + 1\r\n  * @param  Size amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,\r\n                                              uint16_t Size)\r\n{\r\n  uint32_t tmp = 0U, tmp1 = 0U;\r\n  HAL_StatusTypeDef errorcode = HAL_OK;\r\n\r\n  /* Check Direction parameter */\r\n  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hspi);\r\n\r\n  tmp  = hspi->State;\r\n  tmp1 = hspi->Init.Mode;\r\n  if (!((tmp == HAL_SPI_STATE_READY) ||\r\n        ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))\r\n  {\r\n    errorcode = HAL_BUSY;\r\n    goto error;\r\n  }\r\n\r\n  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))\r\n  {\r\n    errorcode = HAL_ERROR;\r\n    goto error;\r\n  }\r\n\r\n  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */\r\n  if (hspi->State != HAL_SPI_STATE_BUSY_RX)\r\n  {\r\n    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;\r\n  }\r\n\r\n  /* Set the transaction information */\r\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r\n  hspi->pTxBuffPtr  = (uint8_t *)pTxData;\r\n  hspi->TxXferSize  = Size;\r\n  hspi->TxXferCount = Size;\r\n  hspi->pRxBuffPtr  = (uint8_t *)pRxData;\r\n  hspi->RxXferSize  = Size;\r\n  hspi->RxXferCount = Size;\r\n\r\n  /* Init field not used in handle to zero */\r\n  hspi->RxISR       = NULL;\r\n  hspi->TxISR       = NULL;\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Reset CRC Calculation */\r\n  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n  {\r\n    SPI_RESET_CRC(hspi);\r\n  }\r\n#endif /* USE_SPI_CRC */\r\n\r\n  /* Reset the threshold bit */\r\n  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);\r\n\r\n  /* the packing mode management is enabled by the DMA settings according the spi data size */\r\n  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r\n  {\r\n    /* set fiforxthreshold according the reception data length: 16bit */\r\n    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r\n  }\r\n  else\r\n  {\r\n    /* set fiforxthreshold according the reception data length: 8bit */\r\n    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r\n\r\n    if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)\r\n    {\r\n      if ((hspi->TxXferSize & 0x1U) == 0x0U)\r\n      {\r\n        CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r\n        hspi->TxXferCount = hspi->TxXferCount >> 1U;\r\n      }\r\n      else\r\n      {\r\n        SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r\n        hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;\r\n      }\r\n    }\r\n\r\n    if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)\r\n    {\r\n      /* set fiforxthreshold according the reception data length: 16bit */\r\n      CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r\n\r\n      if ((hspi->RxXferCount & 0x1U) == 0x0U)\r\n      {\r\n        CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);\r\n        hspi->RxXferCount = hspi->RxXferCount >> 1U;\r\n      }\r\n      else\r\n      {\r\n        SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);\r\n        hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;\r\n      }\r\n    }\r\n  }\r\n\r\n  /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */\r\n  if (hspi->State == HAL_SPI_STATE_BUSY_RX)\r\n  {\r\n    /* Set the SPI Rx DMA Half transfer complete callback */\r\n    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;\r\n    hspi->hdmarx->XferCpltCallback     = SPI_DMAReceiveCplt;\r\n  }\r\n  else\r\n  {\r\n    /* Set the SPI Tx/Rx DMA Half transfer complete callback */\r\n    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;\r\n    hspi->hdmarx->XferCpltCallback     = SPI_DMATransmitReceiveCplt;\r\n  }\r\n\r\n  /* Set the DMA error callback */\r\n  hspi->hdmarx->XferErrorCallback = SPI_DMAError;\r\n\r\n  /* Set the DMA AbortCpltCallback */\r\n  hspi->hdmarx->XferAbortCallback = NULL;\r\n\r\n  /* Enable the Rx DMA Stream/Channel  */\r\n  HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);\r\n\r\n  /* Enable Rx DMA Request */\r\n  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);\r\n\r\n  /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing\r\n  is performed in DMA reception complete callback  */\r\n  hspi->hdmatx->XferHalfCpltCallback = NULL;\r\n  hspi->hdmatx->XferCpltCallback     = NULL;\r\n  hspi->hdmatx->XferErrorCallback    = NULL;\r\n  hspi->hdmatx->XferAbortCallback    = NULL;\r\n\r\n  /* Enable the Tx DMA Stream/Channel  */\r\n  HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);\r\n\r\n  /* Check if the SPI is already enabled */\r\n  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r\n  {\r\n    /* Enable SPI peripheral */\r\n    __HAL_SPI_ENABLE(hspi);\r\n  }\r\n  /* Enable the SPI Error Interrupt Bit */\r\n  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));\r\n\r\n  /* Enable Tx DMA Request */\r\n  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);\r\n\r\nerror :\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hspi);\r\n  return errorcode;\r\n}\r\n\r\n/**\r\n  * @brief  Abort ongoing transfer (blocking mode).\r\n  * @param  hspi SPI handle.\r\n  * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),\r\n  *         started in Interrupt or DMA mode.\r\n  *         This procedure performs following operations :\r\n  *           - Disable SPI Interrupts (depending of transfer direction)\r\n  *           - Disable the DMA transfer in the peripheral register (if enabled)\r\n  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)\r\n  *           - Set handle State to READY\r\n  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.\r\n  * @retval HAL status\r\n*/\r\nHAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)\r\n{\r\n  HAL_StatusTypeDef errorcode;\r\n  uint32_t tickstart = 0U;\r\n\r\n  /* Initialized local variable  */\r\n  errorcode = HAL_OK;\r\n\r\n  /* Init tickstart for timeout managment*/\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */\r\n  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))\r\n  {\r\n    hspi->TxISR = SPI_AbortTx_ISR;\r\n  }\r\n\r\n  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))\r\n  {\r\n    hspi->RxISR = SPI_AbortRx_ISR;\r\n  }\r\n\r\n  while (hspi->State != HAL_SPI_STATE_ABORT)\r\n  {\r\n    if ((HAL_GetTick() - tickstart) >=  HAL_MAX_DELAY)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n\r\n  /* Clear ERRIE interrupts in case of DMA Mode */\r\n  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);\r\n\r\n  /* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */\r\n  if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))\r\n  {\r\n    /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */\r\n    if (hspi->hdmatx != NULL)\r\n    {\r\n      /* Set the SPI DMA Abort callback :\r\n      will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */\r\n      hspi->hdmatx->XferAbortCallback = NULL;\r\n\r\n      /* Abort DMA Tx Handle linked to SPI Peripheral */\r\n      if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)\r\n      {\r\n        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r\n      }\r\n\r\n      /* Disable Tx DMA Request */\r\n      CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));\r\n\r\n      if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r\n      {\r\n        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r\n      }\r\n\r\n      /* Disable SPI Peripheral */\r\n      __HAL_SPI_DISABLE(hspi);\r\n\r\n      /* Empty the FRLVL fifo */\r\n      if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r\n      {\r\n        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r\n      }\r\n    }\r\n    /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */\r\n    if (hspi->hdmarx != NULL)\r\n    {\r\n      /* Set the SPI DMA Abort callback :\r\n      will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */\r\n      hspi->hdmarx->XferAbortCallback = NULL;\r\n\r\n      /* Abort DMA Rx Handle linked to SPI Peripheral */\r\n      if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)\r\n      {\r\n        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r\n      }\r\n\r\n      /* Disable peripheral */\r\n      __HAL_SPI_DISABLE(hspi);\r\n\r\n      /* Control the BSY flag */\r\n      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r\n      {\r\n        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r\n      }\r\n\r\n      /* Empty the FRLVL fifo */\r\n      if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r\n      {\r\n        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r\n      }\r\n\r\n      /* Disable Rx DMA Request */\r\n      CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));\r\n    }\r\n  }\r\n  /* Reset Tx and Rx transfer counters */\r\n  hspi->RxXferCount = 0U;\r\n  hspi->TxXferCount = 0U;\r\n\r\n  /* Check error during Abort procedure */\r\n  if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)\r\n  {\r\n    /* return HAL_Error in case of error during Abort procedure */\r\n    errorcode = HAL_ERROR;\r\n  }\r\n  else\r\n  {\r\n    /* Reset errorCode */\r\n    hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r\n  }\r\n\r\n  /* Clear the Error flags in the SR register */\r\n  __HAL_SPI_CLEAR_OVRFLAG(hspi);\r\n  __HAL_SPI_CLEAR_FREFLAG(hspi);\r\n\r\n  /* Restore hspi->state to ready */\r\n  hspi->State = HAL_SPI_STATE_READY;\r\n\r\n  return errorcode;\r\n}\r\n\r\n/**\r\n  * @brief  Abort ongoing transfer (Interrupt mode).\r\n  * @param  hspi SPI handle.\r\n  * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),\r\n  *         started in Interrupt or DMA mode.\r\n  *         This procedure performs following operations :\r\n  *           - Disable SPI Interrupts (depending of transfer direction)\r\n  *           - Disable the DMA transfer in the peripheral register (if enabled)\r\n  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)\r\n  *           - Set handle State to READY\r\n  *           - At abort completion, call user abort complete callback\r\n  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be\r\n  *         considered as completed only when user abort complete callback is executed (not when exiting function).\r\n  * @retval HAL status\r\n*/\r\nHAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)\r\n{\r\n  HAL_StatusTypeDef errorcode;\r\n  uint32_t tickstart = 0U;\r\n  uint32_t abortcplt ;\r\n\r\n  /* Initialized local variable  */\r\n  errorcode = HAL_OK;\r\n  abortcplt = 1U;\r\n\r\n  /* Init tickstart for timeout managment*/\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */\r\n  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))\r\n  {\r\n    hspi->TxISR = SPI_AbortTx_ISR;\r\n  }\r\n\r\n  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))\r\n  {\r\n    hspi->RxISR = SPI_AbortRx_ISR;\r\n  }\r\n  \r\n  while (hspi->State != HAL_SPI_STATE_ABORT)\r\n  {\r\n    if ((HAL_GetTick() - tickstart) >=  HAL_MAX_DELAY)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n\r\n  /* Clear ERRIE interrupts in case of DMA Mode */\r\n  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);\r\n\r\n  /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised\r\n     before any call to DMA Abort functions */\r\n  /* DMA Tx Handle is valid */\r\n  if (hspi->hdmatx != NULL)\r\n  {\r\n    /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.\r\n       Otherwise, set it to NULL */\r\n    if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))\r\n    {\r\n      hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;\r\n    }\r\n    else\r\n    {\r\n      hspi->hdmatx->XferAbortCallback = NULL;\r\n    }\r\n  }\r\n  /* DMA Rx Handle is valid */\r\n  if (hspi->hdmarx != NULL)\r\n  {\r\n    /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.\r\n       Otherwise, set it to NULL */\r\n    if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))\r\n    {\r\n      hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;\r\n    }\r\n    else\r\n    {\r\n      hspi->hdmarx->XferAbortCallback = NULL;\r\n    }\r\n  }\r\n\r\n  /* Disable the SPI DMA Tx or the SPI Rx request if enabled */\r\n  if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) && (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))\r\n  {\r\n    /* Abort the SPI DMA Tx Stream/Channel */\r\n    if (hspi->hdmatx != NULL)\r\n    {\r\n      /* Abort DMA Tx Handle linked to SPI Peripheral */\r\n      if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)\r\n      {\r\n        hspi->hdmatx->XferAbortCallback = NULL;\r\n        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r\n      }\r\n      else\r\n      {\r\n        abortcplt = 0U;\r\n      }\r\n    }\r\n    /* Abort the SPI DMA Rx Stream/Channel */\r\n    if (hspi->hdmarx != NULL)\r\n    {\r\n      /* Abort DMA Rx Handle linked to SPI Peripheral */\r\n      if (HAL_DMA_Abort_IT(hspi->hdmarx) !=  HAL_OK)\r\n      {\r\n        hspi->hdmarx->XferAbortCallback = NULL;\r\n        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r\n        abortcplt = 1U;\r\n      }\r\n      else\r\n      {\r\n        abortcplt = 0U;\r\n      }\r\n    }\r\n  }\r\n\r\n  /* Disable the SPI DMA Tx or the SPI Rx request if enabled */\r\n  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))\r\n  {\r\n    /* Abort the SPI DMA Tx Stream/Channel */\r\n    if (hspi->hdmatx != NULL)\r\n    {\r\n      /* Abort DMA Tx Handle linked to SPI Peripheral */\r\n      if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)\r\n      {\r\n        hspi->hdmatx->XferAbortCallback = NULL;\r\n        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r\n      }\r\n      else\r\n      {\r\n        abortcplt = 0U;\r\n      }\r\n    }\r\n  }\r\n  /* Disable the SPI DMA Tx or the SPI Rx request if enabled */\r\n  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))\r\n  {\r\n    /* Abort the SPI DMA Rx Stream/Channel */\r\n    if (hspi->hdmarx != NULL)\r\n    {\r\n      /* Abort DMA Rx Handle linked to SPI Peripheral */\r\n      if (HAL_DMA_Abort_IT(hspi->hdmarx) !=  HAL_OK)\r\n      {\r\n        hspi->hdmarx->XferAbortCallback = NULL;\r\n        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r\n      }\r\n      else\r\n      {\r\n        abortcplt = 0U;\r\n      }\r\n    }\r\n  }\r\n\r\n  if (abortcplt == 1U)\r\n  {\r\n    /* Reset Tx and Rx transfer counters */\r\n    hspi->RxXferCount = 0U;\r\n    hspi->TxXferCount = 0U;\r\n\r\n    /* Check error during Abort procedure */\r\n    if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)\r\n    {\r\n      /* return HAL_Error in case of error during Abort procedure */\r\n      errorcode = HAL_ERROR;\r\n    }\r\n    else\r\n    {\r\n      /* Reset errorCode */\r\n      hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r\n    }\r\n\r\n    /* Clear the Error flags in the SR register */\r\n    __HAL_SPI_CLEAR_OVRFLAG(hspi);\r\n    __HAL_SPI_CLEAR_FREFLAG(hspi);\r\n\r\n    /* Restore hspi->State to Ready */\r\n    hspi->State = HAL_SPI_STATE_READY;\r\n\r\n    /* As no DMA to be aborted, call directly user Abort complete callback */\r\n    HAL_SPI_AbortCpltCallback(hspi);\r\n  }\r\n\r\n  return errorcode;\r\n}\r\n\r\n/**\r\n  * @brief  Pause the DMA Transfer.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified SPI module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hspi);\r\n\r\n  /* Disable the SPI DMA Tx & Rx requests */\r\n  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hspi);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Resume the DMA Transfer.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified SPI module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hspi);\r\n\r\n  /* Enable the SPI DMA Tx & Rx requests */\r\n  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hspi);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Stop the DMA Transfer.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified SPI module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)\r\n{\r\n  /* The Lock is not implemented on this API to allow the user application\r\n     to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():\r\n     when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated\r\n     and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()\r\n     */\r\n\r\n  /* Abort the SPI DMA tx Stream/Channel  */\r\n  if (hspi->hdmatx != NULL)\r\n  {\r\n    HAL_DMA_Abort(hspi->hdmatx);\r\n  }\r\n  /* Abort the SPI DMA rx Stream/Channel  */\r\n  if (hspi->hdmarx != NULL)\r\n  {\r\n    HAL_DMA_Abort(hspi->hdmarx);\r\n  }\r\n\r\n  /* Disable the SPI DMA Tx & Rx requests */\r\n  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r\n  hspi->State = HAL_SPI_STATE_READY;\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Handle SPI interrupt request.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified SPI module.\r\n  * @retval None\r\n  */\r\nvoid HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)\r\n{\r\n  uint32_t itsource = hspi->Instance->CR2;\r\n  uint32_t itflag   = hspi->Instance->SR;\r\n\r\n  /* SPI in mode Receiver ----------------------------------------------------*/\r\n  if (((itflag & SPI_FLAG_OVR) == RESET) &&\r\n      ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))\r\n  {\r\n    hspi->RxISR(hspi);\r\n    return;\r\n  }\r\n\r\n  /* SPI in mode Transmitter -------------------------------------------------*/\r\n  if (((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))\r\n  {\r\n    hspi->TxISR(hspi);\r\n    return;\r\n  }\r\n\r\n  /* SPI in Error Treatment --------------------------------------------------*/\r\n  if (((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) && ((itsource & SPI_IT_ERR) != RESET))\r\n  {\r\n    /* SPI Overrun error interrupt occurred ----------------------------------*/\r\n    if ((itflag & SPI_FLAG_OVR) != RESET)\r\n    {\r\n      if (hspi->State != HAL_SPI_STATE_BUSY_TX)\r\n      {\r\n        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);\r\n        __HAL_SPI_CLEAR_OVRFLAG(hspi);\r\n      }\r\n      else\r\n      {\r\n        __HAL_SPI_CLEAR_OVRFLAG(hspi);\r\n        return;\r\n      }\r\n    }\r\n\r\n    /* SPI Mode Fault error interrupt occurred -------------------------------*/\r\n    if ((itflag & SPI_FLAG_MODF) != RESET)\r\n    {\r\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);\r\n      __HAL_SPI_CLEAR_MODFFLAG(hspi);\r\n    }\r\n\r\n    /* SPI Frame error interrupt occurred ------------------------------------*/\r\n    if ((itflag & SPI_FLAG_FRE) != RESET)\r\n    {\r\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);\r\n      __HAL_SPI_CLEAR_FREFLAG(hspi);\r\n    }\r\n\r\n    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r\n    {\r\n      /* Disable all interrupts */\r\n      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);\r\n\r\n      hspi->State = HAL_SPI_STATE_READY;\r\n      /* Disable the SPI DMA requests if enabled */\r\n      if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))\r\n      {\r\n        CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));\r\n\r\n        /* Abort the SPI DMA Rx channel */\r\n        if (hspi->hdmarx != NULL)\r\n        {\r\n          /* Set the SPI DMA Abort callback :\r\n          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */\r\n          hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;\r\n          HAL_DMA_Abort_IT(hspi->hdmarx);\r\n        }\r\n        /* Abort the SPI DMA Tx channel */\r\n        if (hspi->hdmatx != NULL)\r\n        {\r\n          /* Set the SPI DMA Abort callback :\r\n          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */\r\n          hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;\r\n          HAL_DMA_Abort_IT(hspi->hdmatx);\r\n        }\r\n      }\r\n      else\r\n      {\r\n        /* Call user error callback */\r\n        HAL_SPI_ErrorCallback(hspi);\r\n      }\r\n    }\r\n    return;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Tx Transfer completed callback.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hspi);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_SPI_TxCpltCallback should be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief Rx Transfer completed callback.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hspi);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_SPI_RxCpltCallback should be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief Tx and Rx Transfer completed callback.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hspi);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_SPI_TxRxCpltCallback should be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief Tx Half Transfer completed callback.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hspi);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_SPI_TxHalfCpltCallback should be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief Rx Half Transfer completed callback.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hspi);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief Tx and Rx Half Transfer callback.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hspi);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief SPI error callback.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hspi);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_SPI_ErrorCallback should be implemented in the user file\r\n   */\r\n  /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes\r\n            and user can use HAL_SPI_GetError() API to check the latest error occurred\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  SPI Abort Complete callback.\r\n  * @param  hspi SPI handle.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hspi);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_SPI_AbortCpltCallback can be implemented in the user file.\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions\r\n  * @brief   SPI control functions\r\n  *\r\n@verbatim\r\n ===============================================================================\r\n                      ##### Peripheral State and Errors functions #####\r\n ===============================================================================\r\n    [..]\r\n    This subsection provides a set of functions allowing to control the SPI.\r\n     (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral\r\n     (+) HAL_SPI_GetError() check in run-time Errors occurring during communication\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Return the SPI handle state.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval SPI state\r\n  */\r\nHAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Return SPI handle state */\r\n  return hspi->State;\r\n}\r\n\r\n/**\r\n  * @brief  Return the SPI error code.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval SPI error code in bitmap format\r\n  */\r\nuint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Return SPI ErrorCode */\r\n  return hspi->ErrorCode;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup SPI_Private_Functions\r\n  * @brief   Private functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief DMA SPI transmit process complete callback.\r\n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r\n  uint32_t tickstart = 0U;\r\n\r\n  /* Init tickstart for timeout managment*/\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* DMA Normal Mode */\r\n  if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)\r\n  {\r\n    /* Disable ERR interrupt */\r\n    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);\r\n\r\n    /* Disable Tx DMA Request */\r\n    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);\r\n\r\n    /* Check the end of the transaction */\r\n    if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\r\n    {\r\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r\n    }\r\n\r\n    /* Clear overrun flag in 2 Lines communication mode because received data is not read */\r\n    if (hspi->Init.Direction == SPI_DIRECTION_2LINES)\r\n    {\r\n      __HAL_SPI_CLEAR_OVRFLAG(hspi);\r\n    }\r\n\r\n    hspi->TxXferCount = 0U;\r\n    hspi->State = HAL_SPI_STATE_READY;\r\n\r\n    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r\n    {\r\n      HAL_SPI_ErrorCallback(hspi);\r\n      return;\r\n    }\r\n  }\r\n  HAL_SPI_TxCpltCallback(hspi);\r\n}\r\n\r\n/**\r\n  * @brief DMA SPI receive process complete callback.\r\n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r\n  uint32_t tickstart = 0U;\r\n#if (USE_SPI_CRC != 0U)\r\n  __IO uint16_t tmpreg = 0U;\r\n#endif /* USE_SPI_CRC */\r\n\r\n  /* Init tickstart for timeout management*/\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* DMA Normal Mode */\r\n  if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)\r\n  {\r\n    /* Disable ERR interrupt */\r\n    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n    /* CRC handling */\r\n    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n    {\r\n      /* Wait until RXNE flag */\r\n      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\r\n      {\r\n        /* Error on the CRC reception */\r\n        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r\n      }\r\n      /* Read CRC */\r\n      if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r\n      {\r\n        tmpreg = hspi->Instance->DR;\r\n        /* To avoid GCC warning */\r\n        UNUSED(tmpreg);\r\n      }\r\n      else\r\n      {\r\n        tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;\r\n        /* To avoid GCC warning */\r\n        UNUSED(tmpreg);\r\n\r\n        if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)\r\n        {\r\n          if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\r\n          {\r\n            /* Error on the CRC reception */\r\n            SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r\n          }\r\n          tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;\r\n          /* To avoid GCC warning */\r\n          UNUSED(tmpreg);\r\n        }\r\n      }\r\n    }\r\n#endif /* USE_SPI_CRC */\r\n\r\n    /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */\r\n    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r\n\r\n    /* Check the end of the transaction */\r\n    if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\r\n    {\r\n      hspi->ErrorCode = HAL_SPI_ERROR_FLAG;\r\n    }\r\n\r\n    hspi->RxXferCount = 0U;\r\n    hspi->State = HAL_SPI_STATE_READY;\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n    /* Check if CRC error occurred */\r\n    if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))\r\n    {\r\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r\n      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r\n    }\r\n#endif /* USE_SPI_CRC */\r\n\r\n    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r\n    {\r\n      HAL_SPI_ErrorCallback(hspi);\r\n      return;\r\n    }\r\n  }\r\n  HAL_SPI_RxCpltCallback(hspi);\r\n}\r\n\r\n/**\r\n  * @brief  DMA SPI transmit receive process complete callback.\r\n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r\n  uint32_t tickstart = 0U;\r\n#if (USE_SPI_CRC != 0U)\r\n  __IO int16_t tmpreg = 0U;\r\n#endif /* USE_SPI_CRC */\r\n  /* Init tickstart for timeout management*/\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* DMA Normal Mode */\r\n  if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)\r\n  {\r\n    /* Disable ERR interrupt */\r\n    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n    /* CRC handling */\r\n    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n    {\r\n      if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))\r\n      {\r\n        if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,\r\n                                          tickstart) != HAL_OK)\r\n        {\r\n          /* Error on the CRC reception */\r\n          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r\n        }\r\n        /* Read CRC to Flush DR and RXNE flag */\r\n        tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;\r\n        /* To avoid GCC warning */\r\n        UNUSED(tmpreg);\r\n      }\r\n      else\r\n      {\r\n        if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\r\n        {\r\n          /* Error on the CRC reception */\r\n          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r\n        }\r\n        /* Read CRC to Flush DR and RXNE flag */\r\n        tmpreg = hspi->Instance->DR;\r\n        /* To avoid GCC warning */\r\n        UNUSED(tmpreg);\r\n      }\r\n    }\r\n#endif /* USE_SPI_CRC */\r\n\r\n    /* Check the end of the transaction */\r\n    if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\r\n    {\r\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r\n    }\r\n\r\n    /* Disable Rx/Tx DMA Request */\r\n    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r\n\r\n    hspi->TxXferCount = 0U;\r\n    hspi->RxXferCount = 0U;\r\n    hspi->State = HAL_SPI_STATE_READY;\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n    /* Check if CRC error occurred */\r\n    if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))\r\n    {\r\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r\n      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r\n    }\r\n#endif /* USE_SPI_CRC */\r\n\r\n    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r\n    {\r\n      HAL_SPI_ErrorCallback(hspi);\r\n      return;\r\n    }\r\n  }\r\n  HAL_SPI_TxRxCpltCallback(hspi);\r\n}\r\n\r\n/**\r\n  * @brief  DMA SPI half transmit process complete callback.\r\n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r\n\r\n  HAL_SPI_TxHalfCpltCallback(hspi);\r\n}\r\n\r\n/**\r\n  * @brief  DMA SPI half receive process complete callback\r\n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r\n\r\n  HAL_SPI_RxHalfCpltCallback(hspi);\r\n}\r\n\r\n/**\r\n  * @brief  DMA SPI half transmit receive process complete callback.\r\n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r\n\r\n  HAL_SPI_TxRxHalfCpltCallback(hspi);\r\n}\r\n\r\n/**\r\n  * @brief  DMA SPI communication error callback.\r\n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_DMAError(DMA_HandleTypeDef *hdma)\r\n{\r\n  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r\n\r\n  /* Stop the disable DMA transfer on SPI side */\r\n  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r\n\r\n  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);\r\n  hspi->State = HAL_SPI_STATE_READY;\r\n  HAL_SPI_ErrorCallback(hspi);\r\n}\r\n\r\n/**\r\n  * @brief  DMA SPI communication abort callback, when initiated by HAL services on Error\r\n  *         (To be called at end of DMA Abort procedure following error occurrence).\r\n  * @param  hdma DMA handle.\r\n  * @retval None\r\n  */\r\nstatic void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)\r\n{\r\n  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r\n  hspi->RxXferCount = 0U;\r\n  hspi->TxXferCount = 0U;\r\n\r\n  HAL_SPI_ErrorCallback(hspi);\r\n}\r\n\r\n/**\r\n  * @brief  DMA SPI Tx communication abort callback, when initiated by user\r\n  *         (To be called at end of DMA Tx Abort procedure following user abort request).\r\n  * @note   When this callback is executed, User Abort complete call back is called only if no\r\n  *         Abort still ongoing for Rx DMA Handle.\r\n  * @param  hdma DMA handle.\r\n  * @retval None\r\n  */\r\nstatic void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)\r\n{\r\n  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r\n\r\n  hspi->hdmatx->XferAbortCallback = NULL;\r\n\r\n  /* Disable Tx DMA Request */\r\n  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);\r\n\r\n  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r\n  {\r\n    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r\n  }\r\n\r\n  /* Disable SPI Peripheral */\r\n  __HAL_SPI_DISABLE(hspi);\r\n\r\n  /* Empty the FRLVL fifo */\r\n  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r\n  {\r\n    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r\n  }\r\n\r\n  /* Check if an Abort process is still ongoing */\r\n  if (hspi->hdmarx != NULL)\r\n  {\r\n    if (hspi->hdmarx->XferAbortCallback != NULL)\r\n    {\r\n      return;\r\n    }\r\n  }\r\n\r\n  /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */\r\n  hspi->RxXferCount = 0U;\r\n  hspi->TxXferCount = 0U;\r\n\r\n  /* Check no error during Abort procedure */\r\n  if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)\r\n  {\r\n    /* Reset errorCode */\r\n    hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r\n  }\r\n\r\n  /* Clear the Error flags in the SR register */\r\n  __HAL_SPI_CLEAR_OVRFLAG(hspi);\r\n  __HAL_SPI_CLEAR_FREFLAG(hspi);\r\n\r\n  /* Restore hspi->State to Ready */\r\n  hspi->State  = HAL_SPI_STATE_READY;\r\n\r\n  /* Call user Abort complete callback */\r\n  HAL_SPI_AbortCpltCallback(hspi);\r\n}\r\n\r\n/**\r\n  * @brief  DMA SPI Rx communication abort callback, when initiated by user\r\n  *         (To be called at end of DMA Rx Abort procedure following user abort request).\r\n  * @note   When this callback is executed, User Abort complete call back is called only if no\r\n  *         Abort still ongoing for Tx DMA Handle.\r\n  * @param  hdma DMA handle.\r\n  * @retval None\r\n  */\r\nstatic void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)\r\n{\r\n  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\r\n\r\n  /* Disable SPI Peripheral */\r\n  __HAL_SPI_DISABLE(hspi);\r\n\r\n  hspi->hdmarx->XferAbortCallback = NULL;\r\n\r\n  /* Disable Rx DMA Request */\r\n  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);\r\n\r\n  /* Control the BSY flag */\r\n  if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r\n  {\r\n    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r\n  }\r\n\r\n  /* Empty the FRLVL fifo */\r\n  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r\n  {\r\n    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r\n  }\r\n\r\n  /* Check if an Abort process is still ongoing */\r\n  if (hspi->hdmatx != NULL)\r\n  {\r\n    if (hspi->hdmatx->XferAbortCallback != NULL)\r\n    {\r\n      return;\r\n    }\r\n  }\r\n\r\n  /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */\r\n  hspi->RxXferCount = 0U;\r\n  hspi->TxXferCount = 0U;\r\n\r\n  /* Check no error during Abort procedure */\r\n  if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)\r\n  {\r\n    /* Reset errorCode */\r\n    hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r\n  }\r\n\r\n  /* Clear the Error flags in the SR register */\r\n  __HAL_SPI_CLEAR_OVRFLAG(hspi);\r\n  __HAL_SPI_CLEAR_FREFLAG(hspi);\r\n\r\n  /* Restore hspi->State to Ready */\r\n  hspi->State  = HAL_SPI_STATE_READY;\r\n\r\n  /* Call user Abort complete callback */\r\n  HAL_SPI_AbortCpltCallback(hspi);\r\n}\r\n\r\n/**\r\n  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Receive data in packing mode */\r\n  if (hspi->RxXferCount > 1U)\r\n  {\r\n    *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;\r\n    hspi->pRxBuffPtr += sizeof(uint16_t);\r\n    hspi->RxXferCount -= 2U;\r\n    if (hspi->RxXferCount == 1U)\r\n    {\r\n      /* set fiforxthreshold according the reception data length: 8bit */\r\n      SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r\n    }\r\n  }\r\n  /* Receive data in 8 Bit mode */\r\n  else\r\n  {\r\n    *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);\r\n    hspi->RxXferCount--;\r\n  }\r\n\r\n  /* check end of the reception */\r\n  if (hspi->RxXferCount == 0U)\r\n  {\r\n#if (USE_SPI_CRC != 0U)\r\n    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n    {\r\n      SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r\n      hspi->RxISR =  SPI_2linesRxISR_8BITCRC;\r\n      return;\r\n    }\r\n#endif /* USE_SPI_CRC */\r\n\r\n    /* Disable RXNE  and ERR interrupt */\r\n    __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\r\n\r\n    if (hspi->TxXferCount == 0U)\r\n    {\r\n      SPI_CloseRxTx_ISR(hspi);\r\n    }\r\n  }\r\n}\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n/**\r\n  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)\r\n{\r\n  __IO uint8_t tmpreg = 0U;\r\n\r\n  /* Read data register to flush CRC */\r\n  tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);\r\n\r\n  /* To avoid GCC warning */\r\n  UNUSED(tmpreg);\r\n\r\n  hspi->CRCSize--;\r\n\r\n  /* check end of the reception */\r\n  if (hspi->CRCSize == 0U)\r\n  {\r\n    /* Disable RXNE and ERR interrupt */\r\n    __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\r\n\r\n    if (hspi->TxXferCount == 0U)\r\n    {\r\n      SPI_CloseRxTx_ISR(hspi);\r\n    }\r\n  }\r\n}\r\n#endif /* USE_SPI_CRC */\r\n\r\n/**\r\n  * @brief  Tx 8-bit handler for Transmit and Receive in Interrupt mode.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Transmit data in packing Bit mode */\r\n  if (hspi->TxXferCount >= 2U)\r\n  {\r\n    hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r\n    hspi->pTxBuffPtr += sizeof(uint16_t);\r\n    hspi->TxXferCount -= 2U;\r\n  }\r\n  /* Transmit data in 8 Bit mode */\r\n  else\r\n  {\r\n    *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);\r\n    hspi->TxXferCount--;\r\n  }\r\n\r\n  /* check the end of the transmission */\r\n  if (hspi->TxXferCount == 0U)\r\n  {\r\n#if (USE_SPI_CRC != 0U)\r\n    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n    {\r\n      /* Set CRC Next Bit to send CRC */\r\n      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r\n      /* Disable TXE interrupt */\r\n      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);\r\n      return;\r\n    }\r\n#endif /* USE_SPI_CRC */\r\n\r\n    /* Disable TXE interrupt */\r\n    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);\r\n\r\n    if (hspi->RxXferCount == 0U)\r\n    {\r\n      SPI_CloseRxTx_ISR(hspi);\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Rx 16-bit handler for Transmit and Receive in Interrupt mode.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Receive data in 16 Bit mode */\r\n  *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;\r\n  hspi->pRxBuffPtr += sizeof(uint16_t);\r\n  hspi->RxXferCount--;\r\n\r\n  if (hspi->RxXferCount == 0U)\r\n  {\r\n#if (USE_SPI_CRC != 0U)\r\n    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n    {\r\n      hspi->RxISR =  SPI_2linesRxISR_16BITCRC;\r\n      return;\r\n    }\r\n#endif /* USE_SPI_CRC */\r\n\r\n    /* Disable RXNE interrupt */\r\n    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);\r\n\r\n    if (hspi->TxXferCount == 0U)\r\n    {\r\n      SPI_CloseRxTx_ISR(hspi);\r\n    }\r\n  }\r\n}\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n/**\r\n  * @brief  Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Receive data in 16 Bit mode */\r\n  __IO uint16_t tmpreg = 0U;\r\n\r\n  /* Read data register to flush CRC */\r\n  tmpreg = hspi->Instance->DR;\r\n\r\n  /* To avoid GCC warning */\r\n  UNUSED(tmpreg);\r\n\r\n  /* Disable RXNE interrupt */\r\n  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);\r\n\r\n  SPI_CloseRxTx_ISR(hspi);\r\n}\r\n#endif /* USE_SPI_CRC */\r\n\r\n/**\r\n  * @brief  Tx 16-bit handler for Transmit and Receive in Interrupt mode.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Transmit data in 16 Bit mode */\r\n  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r\n  hspi->pTxBuffPtr += sizeof(uint16_t);\r\n  hspi->TxXferCount--;\r\n\r\n  /* Enable CRC Transmission */\r\n  if (hspi->TxXferCount == 0U)\r\n  {\r\n#if (USE_SPI_CRC != 0U)\r\n    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n    {\r\n      /* Set CRC Next Bit to send CRC */\r\n      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r\n      /* Disable TXE interrupt */\r\n      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);\r\n      return;\r\n    }\r\n#endif /* USE_SPI_CRC */\r\n\r\n    /* Disable TXE interrupt */\r\n    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);\r\n\r\n    if (hspi->RxXferCount == 0U)\r\n    {\r\n      SPI_CloseRxTx_ISR(hspi);\r\n    }\r\n  }\r\n}\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n/**\r\n  * @brief  Manage the CRC 8-bit receive in Interrupt context.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)\r\n{\r\n  __IO uint8_t tmpreg = 0U;\r\n\r\n  /* Read data register to flush CRC */\r\n  tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);\r\n\r\n  /* To avoid GCC warning */\r\n  UNUSED(tmpreg);\r\n\r\n  hspi->CRCSize--;\r\n\r\n  if (hspi->CRCSize == 0U)\r\n  {\r\n    SPI_CloseRx_ISR(hspi);\r\n  }\r\n}\r\n#endif /* USE_SPI_CRC */\r\n\r\n/**\r\n  * @brief  Manage the receive 8-bit in Interrupt context.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\r\n{\r\n  *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);\r\n  hspi->RxXferCount--;\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Enable CRC Transmission */\r\n  if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\r\n  {\r\n    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r\n  }\r\n#endif /* USE_SPI_CRC */\r\n\r\n  if (hspi->RxXferCount == 0U)\r\n  {\r\n#if (USE_SPI_CRC != 0U)\r\n    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n    {\r\n      hspi->RxISR =  SPI_RxISR_8BITCRC;\r\n      return;\r\n    }\r\n#endif /* USE_SPI_CRC */\r\n    SPI_CloseRx_ISR(hspi);\r\n  }\r\n}\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n/**\r\n  * @brief  Manage the CRC 16-bit receive in Interrupt context.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)\r\n{\r\n  __IO uint16_t tmpreg = 0U;\r\n\r\n  /* Read data register to flush CRC */\r\n  tmpreg = hspi->Instance->DR;\r\n\r\n  /* To avoid GCC warning */\r\n  UNUSED(tmpreg);\r\n\r\n  /* Disable RXNE and ERR interrupt */\r\n  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\r\n\r\n  SPI_CloseRx_ISR(hspi);\r\n}\r\n#endif /* USE_SPI_CRC */\r\n\r\n/**\r\n  * @brief  Manage the 16-bit receive in Interrupt context.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\r\n{\r\n  *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;\r\n  hspi->pRxBuffPtr += sizeof(uint16_t);\r\n  hspi->RxXferCount--;\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Enable CRC Transmission */\r\n  if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\r\n  {\r\n    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r\n  }\r\n#endif /* USE_SPI_CRC */\r\n\r\n  if (hspi->RxXferCount == 0U)\r\n  {\r\n#if (USE_SPI_CRC != 0U)\r\n    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n    {\r\n      hspi->RxISR = SPI_RxISR_16BITCRC;\r\n      return;\r\n    }\r\n#endif /* USE_SPI_CRC */\r\n    SPI_CloseRx_ISR(hspi);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Handle the data 8-bit transmit in Interrupt mode.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\r\n{\r\n  *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);\r\n  hspi->TxXferCount--;\r\n\r\n  if (hspi->TxXferCount == 0U)\r\n  {\r\n#if (USE_SPI_CRC != 0U)\r\n    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n    {\r\n      /* Enable CRC Transmission */\r\n      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r\n    }\r\n#endif /* USE_SPI_CRC */\r\n    SPI_CloseTx_ISR(hspi);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Handle the data 16-bit transmit in Interrupt mode.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Transmit data in 16 Bit mode */\r\n  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r\n  hspi->pTxBuffPtr += sizeof(uint16_t);\r\n  hspi->TxXferCount--;\r\n\r\n  if (hspi->TxXferCount == 0U)\r\n  {\r\n#if (USE_SPI_CRC != 0U)\r\n    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n    {\r\n      /* Enable CRC Transmission */\r\n      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r\n    }\r\n#endif /* USE_SPI_CRC */\r\n    SPI_CloseTx_ISR(hspi);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Handle SPI Communication Timeout.\r\n  * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *              the configuration information for SPI module.\r\n  * @param Flag SPI flag to check\r\n  * @param State flag state to check\r\n  * @param Timeout Timeout duration\r\n  * @param Tickstart tick start value\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,\r\n                                                       uint32_t Timeout, uint32_t Tickstart)\r\n{\r\n  while ((hspi->Instance->SR & Flag) != State)\r\n  {\r\n    if (Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) >= Timeout))\r\n      {\r\n        /* Disable the SPI and reset the CRC: the CRC value should be cleared\r\n        on both master and slave sides in order to resynchronize the master\r\n        and slave for their respective CRC calculation */\r\n\r\n        /* Disable TXE, RXNE and ERR interrupts for the interrupt process */\r\n        __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));\r\n\r\n        if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)\r\n                                                     || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))\r\n        {\r\n          /* Disable SPI peripheral */\r\n          __HAL_SPI_DISABLE(hspi);\r\n        }\r\n\r\n        /* Reset CRC Calculation */\r\n        if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n        {\r\n          SPI_RESET_CRC(hspi);\r\n        }\r\n\r\n        hspi->State = HAL_SPI_STATE_READY;\r\n\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hspi);\r\n\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Handle SPI FIFO Communication Timeout.\r\n  * @param hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *              the configuration information for SPI module.\r\n  * @param Fifo Fifo to check\r\n  * @param State Fifo state to check\r\n  * @param Timeout Timeout duration\r\n  * @param Tickstart tick start value\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,\r\n                                                       uint32_t Timeout, uint32_t Tickstart)\r\n{\r\n  __IO uint8_t tmpreg;\r\n\r\n  while ((hspi->Instance->SR & Fifo) != State)\r\n  {\r\n    if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))\r\n    {\r\n      tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);\r\n      /* To avoid GCC warning */\r\n      UNUSED(tmpreg);\r\n    }\r\n\r\n    if (Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if ((Timeout == 0) || ((HAL_GetTick() - Tickstart) >= Timeout))\r\n      {\r\n        /* Disable the SPI and reset the CRC: the CRC value should be cleared\r\n           on both master and slave sides in order to resynchronize the master\r\n           and slave for their respective CRC calculation */\r\n\r\n        /* Disable TXE, RXNE and ERR interrupts for the interrupt process */\r\n        __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));\r\n\r\n        if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)\r\n                                                     || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))\r\n        {\r\n          /* Disable SPI peripheral */\r\n          __HAL_SPI_DISABLE(hspi);\r\n        }\r\n\r\n        /* Reset CRC Calculation */\r\n        if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n        {\r\n          SPI_RESET_CRC(hspi);\r\n        }\r\n\r\n        hspi->State = HAL_SPI_STATE_READY;\r\n\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hspi);\r\n\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Handle the check of the RX transaction complete.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @param  Timeout Timeout duration\r\n  * @param  Tickstart tick start value\r\n  * @retval None.\r\n  */\r\nstatic HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi,  uint32_t Timeout, uint32_t Tickstart)\r\n{\r\n  if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)\r\n                                               || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))\r\n  {\r\n    /* Disable SPI peripheral */\r\n    __HAL_SPI_DISABLE(hspi);\r\n  }\r\n\r\n  /* Control the BSY flag */\r\n  if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)\r\n  {\r\n    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r\n    return HAL_TIMEOUT;\r\n  }\r\n\r\n  if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)\r\n                                               || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))\r\n  {\r\n    /* Empty the FRLVL fifo */\r\n    if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)\r\n    {\r\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Handle the check of the RXTX or TX transaction complete.\r\n  * @param hspi SPI handle\r\n  * @param Timeout Timeout duration\r\n  * @param Tickstart tick start value\r\n  */\r\nstatic HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)\r\n{\r\n  /* Control if the TX fifo is empty */\r\n  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)\r\n  {\r\n    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r\n    return HAL_TIMEOUT;\r\n  }\r\n  /* Control the BSY flag */\r\n  if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)\r\n  {\r\n    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r\n    return HAL_TIMEOUT;\r\n  }\r\n  /* Control if the RX fifo is empty */\r\n  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)\r\n  {\r\n    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r\n    return HAL_TIMEOUT;\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Handle the end of the RXTX transaction.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)\r\n{\r\n  uint32_t tickstart = 0U;\r\n\r\n  /* Init tickstart for timeout managment*/\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Disable ERR interrupt */\r\n  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);\r\n\r\n  /* Check the end of the transaction */\r\n  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\r\n  {\r\n    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r\n  }\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Check if CRC error occurred */\r\n  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)\r\n  {\r\n    hspi->State = HAL_SPI_STATE_READY;\r\n    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r\n    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r\n    HAL_SPI_ErrorCallback(hspi);\r\n  }\r\n  else\r\n  {\r\n#endif /* USE_SPI_CRC */\r\n    if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)\r\n    {\r\n      if (hspi->State == HAL_SPI_STATE_BUSY_RX)\r\n      {\r\n        hspi->State = HAL_SPI_STATE_READY;\r\n        HAL_SPI_RxCpltCallback(hspi);\r\n      }\r\n      else\r\n      {\r\n        hspi->State = HAL_SPI_STATE_READY;\r\n        HAL_SPI_TxRxCpltCallback(hspi);\r\n      }\r\n    }\r\n    else\r\n    {\r\n      hspi->State = HAL_SPI_STATE_READY;\r\n      HAL_SPI_ErrorCallback(hspi);\r\n    }\r\n#if (USE_SPI_CRC != 0U)\r\n  }\r\n#endif /* USE_SPI_CRC */\r\n}\r\n\r\n/**\r\n  * @brief  Handle the end of the RX transaction.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Disable RXNE and ERR interrupt */\r\n  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\r\n\r\n  /* Check the end of the transaction */\r\n  if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r\n  {\r\n    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r\n  }\r\n  hspi->State = HAL_SPI_STATE_READY;\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Check if CRC error occurred */\r\n  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)\r\n  {\r\n    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\r\n    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r\n    HAL_SPI_ErrorCallback(hspi);\r\n  }\r\n  else\r\n  {\r\n#endif /* USE_SPI_CRC */\r\n    if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)\r\n    {\r\n      HAL_SPI_RxCpltCallback(hspi);\r\n    }\r\n    else\r\n    {\r\n      HAL_SPI_ErrorCallback(hspi);\r\n    }\r\n#if (USE_SPI_CRC != 0U)\r\n  }\r\n#endif /* USE_SPI_CRC */\r\n}\r\n\r\n/**\r\n  * @brief  Handle the end of the TX transaction.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)\r\n{\r\n  uint32_t tickstart = 0U;\r\n\r\n  /* Init tickstart for timeout management*/\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Disable TXE and ERR interrupt */\r\n  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));\r\n\r\n  /* Check the end of the transaction */\r\n  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\r\n  {\r\n    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\r\n  }\r\n\r\n  /* Clear overrun flag in 2 Lines communication mode because received is not read */\r\n  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)\r\n  {\r\n    __HAL_SPI_CLEAR_OVRFLAG(hspi);\r\n  }\r\n\r\n  hspi->State = HAL_SPI_STATE_READY;\r\n  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r\n  {\r\n    HAL_SPI_ErrorCallback(hspi);\r\n  }\r\n  else\r\n  {\r\n    HAL_SPI_TxCpltCallback(hspi);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Handle abort a Rx transaction.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)\r\n{\r\n  uint32_t tickstart = 0U;\r\n\r\n  /* Init tickstart for timeout managment*/\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Disable SPI Peripheral */\r\n  __HAL_SPI_DISABLE(hspi);\r\n\r\n  /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */\r\n  CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));\r\n\r\n  while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))\r\n  {\r\n    if ((HAL_GetTick() - tickstart) >=  HAL_MAX_DELAY)\r\n    {\r\n      hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r\n    }\r\n  }\r\n\r\n  /* Control the BSY flag */\r\n  if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r\n  {\r\n    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r\n  }\r\n\r\n  /* Empty the FRLVL fifo */\r\n  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r\n  {\r\n    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r\n  }\r\n\r\n  hspi->State = HAL_SPI_STATE_ABORT;\r\n}\r\n\r\n/**\r\n  * @brief  Handle abort a Tx or Rx/Tx transaction.\r\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)\r\n{\r\n  uint32_t tickstart = 0U;\r\n\r\n  /* Init tickstart for timeout managment*/\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */\r\n  CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));\r\n\r\n  while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))\r\n  {\r\n    if ((HAL_GetTick() - tickstart) >=  HAL_MAX_DELAY)\r\n    {\r\n      hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r\n    }\r\n  }\r\n\r\n  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r\n  {\r\n    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r\n  }\r\n\r\n  /* Disable SPI Peripheral */\r\n  __HAL_SPI_DISABLE(hspi);\r\n\r\n  /* Empty the FRLVL fifo */\r\n  if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\r\n  {\r\n    hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\r\n  }\r\n\r\n  hspi->State = HAL_SPI_STATE_ABORT;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_SPI_MODULE_ENABLED */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_tim.c\r\n  * @author  MCD Application Team\r\n  * @brief   TIM HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the Timer (TIM) peripheral:\r\n  *           + Time Base Initialization\r\n  *           + Time Base Start\r\n  *           + Time Base Start Interruption\r\n  *           + Time Base Start DMA\r\n  *           + Time Output Compare/PWM Initialization\r\n  *           + Time Output Compare/PWM Channel Configuration\r\n  *           + Time Output Compare/PWM  Start\r\n  *           + Time Output Compare/PWM  Start Interruption\r\n  *           + Time Output Compare/PWM Start DMA\r\n  *           + Time Input Capture Initialization\r\n  *           + Time Input Capture Channel Configuration\r\n  *           + Time Input Capture Start\r\n  *           + Time Input Capture Start Interruption \r\n  *           + Time Input Capture Start DMA\r\n  *           + Time One Pulse Initialization\r\n  *           + Time One Pulse Channel Configuration\r\n  *           + Time One Pulse Start \r\n  *           + Time Encoder Interface Initialization\r\n  *           + Time Encoder Interface Start\r\n  *           + Time Encoder Interface Start Interruption\r\n  *           + Time Encoder Interface Start DMA\r\n  *           + Commutation Event configuration with Interruption and DMA\r\n  *           + Time OCRef clear configuration\r\n  *           + Time External Clock configuration\r\n  @verbatim \r\n  ==============================================================================\r\n                      ##### TIMER Generic features #####\r\n  ==============================================================================\r\n  [..] The Timer features include: \r\n       (#) 16-bit up, down, up/down auto-reload counter.\r\n       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the \r\n           counter clock frequency either by any factor between 1 and 65536.\r\n       (#) Up to 4 independent channels for:\r\n           (++) Input Capture\r\n           (++) Output Compare\r\n           (++) PWM generation (Edge and Center-aligned Mode)\r\n           (++) One-pulse mode output               \r\n   \r\n                        ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]\r\n     (#) Initialize the TIM low level resources by implementing the following functions \r\n         depending from feature used :\r\n           (++) Time Base : HAL_TIM_Base_MspInit() \r\n           (++) Input Capture : HAL_TIM_IC_MspInit()\r\n           (++) Output Compare : HAL_TIM_OC_MspInit()\r\n           (++) PWM generation : HAL_TIM_PWM_MspInit()\r\n           (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()\r\n           (++) Encoder mode output : HAL_TIM_Encoder_MspInit()\r\n           \r\n     (#) Initialize the TIM low level resources :\r\n        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); \r\n        (##) TIM pins configuration\r\n            (+++) Enable the clock for the TIM GPIOs using the following function:\r\n                 __HAL_RCC_GPIOx_CLK_ENABLE();   \r\n            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();  \r\n\r\n     (#) The external Clock can be configured, if needed (the default clock is the \r\n         internal clock from the APBx), using the following function:\r\n         HAL_TIM_ConfigClockSource, the clock configuration should be done before \r\n         any start function.\r\n  \r\n     (#) Configure the TIM in the desired functioning mode using one of the \r\n         initialization function of this driver:\r\n         (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base\r\n         (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an \r\n              Output Compare signal.\r\n         (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a \r\n              PWM signal.\r\n         (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an \r\n              external signal.\r\n         (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer \r\n              in One Pulse Mode.\r\n         (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.\r\n         \r\n     (#) Activate the TIM peripheral using one of the start functions depending from the feature used: \r\n           (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()\r\n           (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()\r\n           (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()\r\n           (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()\r\n           (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()\r\n           (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().\r\n\r\n     (#) The DMA Burst is managed with the two following functions:\r\n         HAL_TIM_DMABurst_WriteStart()\r\n         HAL_TIM_DMABurst_ReadStart()\r\n  \r\n    *** Callback registration ***\r\n  =============================================\r\n\r\n  The compilation define  USE_HAL_TIM_REGISTER_CALLBACKS when set to 1\r\n  allows the user to configure dynamically the driver callbacks.\r\n\r\n  Use Function @ref HAL_TIM_RegisterCallback() to register a callback.\r\n  @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,\r\n  the Callback ID and a pointer to the user callback function.\r\n\r\n  Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default\r\n  weak function.\r\n  @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,\r\n  and the Callback ID.\r\n\r\n  These functions allow to register/unregister following callbacks:\r\n    (+) Base_MspInitCallback       : TIM Base Msp Init Callback.\r\n    (+) Base_MspDeInitCallback     : TIM Base Msp DeInit Callback.\r\n    (+) IC_MspInitCallback         : TIM IC Msp Init Callback.\r\n    (+) IC_MspDeInitCallback       : TIM IC Msp DeInit Callback.\r\n    (+) OC_MspInitCallback         : TIM OC Msp Init Callback.\r\n    (+) OC_MspDeInitCallback       : TIM OC Msp DeInit Callback.\r\n    (+) PWM_MspInitCallback        : TIM PWM Msp Init Callback.\r\n    (+) PWM_MspDeInitCallback      : TIM PWM Msp DeInit Callback.\r\n    (+) OnePulse_MspInitCallback   : TIM One Pulse Msp Init Callback.\r\n    (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.\r\n    (+) Encoder_MspInitCallback    : TIM Encoder Msp Init Callback.\r\n    (+) Encoder_MspDeInitCallback  : TIM Encoder Msp DeInit Callback.\r\n    (+) PeriodElapsedCallback      : TIM Period Elapsed Callback.\r\n    (+) TriggerCallback            : TIM Trigger Callback.\r\n    (+) IC_CaptureCallback         : TIM Input Capture Callback.\r\n    (+) OC_DelayElapsedCallback    : TIM Output Compare Delay Elapsed Callback.\r\n    (+) PWM_PulseFinishedCallback  : TIM PWM Pulse Finished Callback.\r\n    (+) ErrorCallback              : TIM Error Callback.\r\n    (+) CommutationCallback        : TIM Commutation Callback.\r\n    (+) BreakCallback              : TIM Break Callback.\r\n\r\n  By default, after the Init and when the state is HAL_TIM_STATE_RESET\r\n  all interrupt callbacks are set to the corresponding weak functions:\r\n  examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().\r\n\r\n  Exception done for MspInit and MspDeInit functions that are reset to the legacy weak\r\n  functionalities in the Init/DeInit only when these callbacks are null\r\n  (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit\r\n  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)\r\n\r\n  Callbacks can be registered/unregistered in HAL_TIM_STATE_READY state only.\r\n  Exception done MspInit/MspDeInit that can be registered/unregistered\r\n  in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,\r\n  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.\r\n  In that case first register the MspInit/MspDeInit user callbacks\r\n  using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.\r\n\r\n  When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or\r\n  not defined, the callback registration feature is not available and all callbacks\r\n  are set to the corresponding weak functions.\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup TIM TIM\r\n  * @brief TIM HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_TIM_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @addtogroup TIM_Private_Functions\r\n  * @{\r\n  */\r\n/* Private function prototypes -----------------------------------------------*/\r\nstatic void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);\r\nstatic void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r\n                       uint32_t TIM_ICFilter);\r\nstatic void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);\r\nstatic void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r\n                       uint32_t TIM_ICFilter);\r\nstatic void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r\n                       uint32_t TIM_ICFilter);\r\n\r\nstatic void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx);\r\nstatic void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);\r\nstatic void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);\r\nstatic void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,\r\n                                     TIM_SlaveConfigTypeDef * sSlaveConfig);\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup TIM_Exported_Functions TIM Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup TIM_Exported_Functions_Group1 Time Base functions \r\n *  @brief    Time Base functions \r\n *\r\n@verbatim    \r\n  ==============================================================================\r\n              ##### Time Base functions #####\r\n  ==============================================================================\r\n  [..]  \r\n    This section provides functions allowing to:\r\n    (+) Initialize and configure the TIM base. \r\n    (+) De-initialize the TIM base.\r\n    (+) Start the Time Base.\r\n    (+) Stop the Time Base.\r\n    (+) Start the Time Base and enable interrupt.\r\n    (+) Stop the Time Base and disable interrupt.\r\n    (+) Start the Time Base and enable DMA transfer.\r\n    (+) Stop the Time Base and disable DMA transfer.\r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n/**\r\n  * @brief  Initializes the TIM Time base Unit according to the specified\r\n  *         parameters in the TIM_HandleTypeDef and create the associated handle.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)\r\n{ \r\n  /* Check the TIM handle allocation */\r\n  if(htim == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_INSTANCE(htim->Instance)); \r\n  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r\n  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r\n  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r\n\r\n  if(htim->State == HAL_TIM_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    htim->Lock = HAL_UNLOCKED;\r\n\r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\n    /* Reset interrupt callbacks to legacy week callbacks */\r\n    TIM_ResetCallback(htim);\r\n\r\n    if(htim->Base_MspInitCallback == NULL)\r\n    {\r\n      htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;\r\n    }\r\n    /* Init the low level hardware : GPIO, CLOCK, NVIC */\r\n    htim->Base_MspInitCallback(htim);\r\n#else\r\n    /* Init the low level hardware : GPIO, CLOCK, NVIC */\r\n    HAL_TIM_Base_MspInit(htim);\r\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n  }\r\n  /* Set the TIM state */\r\n  htim->State= HAL_TIM_STATE_BUSY;\r\n  \r\n  /* Set the Time Base configuration */\r\n  TIM_Base_SetConfig(htim->Instance, &htim->Init); \r\n  \r\n  /* Initialize the TIM state*/\r\n  htim->State= HAL_TIM_STATE_READY;\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the TIM Base peripheral \r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)\r\n{  \r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\r\n\r\n  htim->State = HAL_TIM_STATE_BUSY;\r\n   \r\n  /* Disable the TIM Peripheral Clock */\r\n  __HAL_TIM_DISABLE(htim);\r\n\r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\n  if(htim->Base_MspDeInitCallback == NULL)\r\n  {\r\n    htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;\r\n  }\r\n  /* DeInit the low level hardware */\r\n  htim->Base_MspDeInitCallback(htim);\r\n#else\r\n  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r\n  HAL_TIM_Base_MspDeInit(htim);\r\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n  \r\n  /* Change TIM state */  \r\n  htim->State = HAL_TIM_STATE_RESET; \r\n  \r\n  /* Release Lock */\r\n  __HAL_UNLOCK(htim);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the TIM Base MSP.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_TIM_Base_MspInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes TIM Base MSP.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_TIM_Base_MspDeInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Starts the TIM Base generation.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\r\n  \r\n  /* Set the TIM state */\r\n  htim->State= HAL_TIM_STATE_BUSY;\r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim);\r\n  \r\n  /* Change the TIM state*/\r\n  htim->State= HAL_TIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the TIM Base generation.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\r\n  \r\n  /* Set the TIM state */\r\n  htim->State= HAL_TIM_STATE_BUSY;\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim);\r\n  \r\n  /* Change the TIM state*/\r\n  htim->State= HAL_TIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the TIM Base generation in interrupt mode.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\r\n  \r\n  /* Enable the TIM Update interrupt */\r\n  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);\r\n      \r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim);\r\n      \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the TIM Base generation in interrupt mode.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\r\n  /* Disable the TIM Update interrupt */\r\n  __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);\r\n      \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim);\r\n    \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the TIM Base generation in DMA mode.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  pData The source Buffer address.\r\n  * @param  Length The length of data to be transferred from memory to peripheral.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); \r\n  \r\n  if((htim->State == HAL_TIM_STATE_BUSY))\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  else if((htim->State == HAL_TIM_STATE_READY))\r\n  {\r\n    if((pData == 0 ) && (Length > 0)) \r\n    {\r\n      return HAL_ERROR;                                    \r\n    }\r\n    else\r\n    {\r\n      htim->State = HAL_TIM_STATE_BUSY;\r\n    }\r\n  }  \r\n  /* Set the DMA Period elapsed callback */\r\n  htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;\r\n     \r\n  /* Set the DMA error callback */\r\n  htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;\r\n  \r\n  /* Enable the DMA Stream */\r\n  HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);\r\n  \r\n  /* Enable the TIM Update DMA request */\r\n  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);\r\n\r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim);  \r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the TIM Base generation in DMA mode.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));\r\n  \r\n  /* Disable the TIM Update DMA request */\r\n  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);\r\n      \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim);\r\n    \r\n  /* Change the htim state */\r\n  htim->State = HAL_TIM_STATE_READY;\r\n      \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions \r\n *  @brief    Time Output Compare functions \r\n *\r\n@verbatim    \r\n  ==============================================================================\r\n                  ##### Time Output Compare functions #####\r\n  ==============================================================================\r\n  [..]\r\n    This section provides functions allowing to:\r\n    (+) Initialize and configure the TIM Output Compare. \r\n    (+) De-initialize the TIM Output Compare.\r\n    (+) Start the Time Output Compare.\r\n    (+) Stop the Time Output Compare.\r\n    (+) Start the Time Output Compare and enable interrupt.\r\n    (+) Stop the Time Output Compare and disable interrupt.\r\n    (+) Start the Time Output Compare and enable DMA transfer.\r\n    (+) Stop the Time Output Compare and disable DMA transfer.\r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n/**\r\n  * @brief  Initializes the TIM Output Compare according to the specified\r\n  *         parameters in the TIM_HandleTypeDef and create the associated handle.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)\r\n{\r\n  /* Check the TIM handle allocation */\r\n  if(htim == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\r\n  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r\n  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r\n  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r\n\r\n  if(htim->State == HAL_TIM_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    htim->Lock = HAL_UNLOCKED;\r\n\r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\n    /* Reset interrupt callbacks to legacy week callbacks */\r\n    TIM_ResetCallback(htim);\r\n\r\n    if(htim->OC_MspInitCallback == NULL)\r\n    {\r\n      htim->OC_MspInitCallback = HAL_TIM_OC_MspDeInit;\r\n    }\r\n    /* Init the low level hardware : GPIO, CLOCK, NVIC */\r\n    htim->OC_MspInitCallback(htim);\r\n#else\r\n    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r\n    HAL_TIM_OC_MspInit(htim);\r\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n  }\r\n  /* Set the TIM state */\r\n  htim->State= HAL_TIM_STATE_BUSY;\r\n  \r\n  /* Init the base time for the Output Compare */  \r\n  TIM_Base_SetConfig(htim->Instance,  &htim->Init); \r\n  \r\n  /* Initialize the TIM state*/\r\n  htim->State= HAL_TIM_STATE_READY;\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the TIM peripheral \r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\r\n  \r\n   htim->State = HAL_TIM_STATE_BUSY;\r\n   \r\n  /* Disable the TIM Peripheral Clock */\r\n  __HAL_TIM_DISABLE(htim);\r\n\r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\n  if(htim->OC_MspDeInitCallback == NULL)\r\n  {\r\n    htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;\r\n  }\r\n  /* DeInit the low level hardware */\r\n  htim->OC_MspDeInitCallback(htim);\r\n#else\r\n  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\r\n  HAL_TIM_OC_MspDeInit(htim);\r\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n\r\n  /* Change TIM state */  \r\n  htim->State = HAL_TIM_STATE_RESET; \r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(htim);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the TIM Output Compare MSP.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_TIM_OC_MspInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes TIM Output Compare MSP.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_TIM_OC_MspDeInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Starts the TIM Output Compare signal generation.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.  \r\n  * @param  Channel TIM Channel to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n  \r\n  /* Enable the Output compare channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r\n  \r\n  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  \r\n  {\r\n    /* Enable the main output */\r\n    __HAL_TIM_MOE_ENABLE(htim);\r\n  }\r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim); \r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the TIM Output Compare signal generation.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel TIM Channel to be disabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n  \r\n  /* Disable the Output compare channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r\n  \r\n  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  \r\n  {\r\n    /* Disable the Main Output */\r\n    __HAL_TIM_MOE_DISABLE(htim);\r\n  }  \r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim);  \r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}  \r\n\r\n/**\r\n  * @brief  Starts the TIM Output Compare signal generation in interrupt mode.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel TIM Channel to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n  \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {       \r\n      /* Enable the TIM Capture/Compare 1 interrupt */\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Enable the TIM Capture/Compare 2 interrupt */\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      /* Enable the TIM Capture/Compare 3 interrupt */\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n      /* Enable the TIM Capture/Compare 4 interrupt */\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break;\r\n  } \r\n\r\n  /* Enable the Output compare channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r\n  \r\n  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  \r\n  {\r\n    /* Enable the main output */\r\n    __HAL_TIM_MOE_ENABLE(htim);\r\n  }\r\n\r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the TIM Output Compare signal generation in interrupt mode.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel TIM Channel to be disabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n  \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {       \r\n      /* Disable the TIM Capture/Compare 1 interrupt */\r\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Disable the TIM Capture/Compare 2 interrupt */\r\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      /* Disable the TIM Capture/Compare 3 interrupt */\r\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n      /* Disable the TIM Capture/Compare 4 interrupt */\r\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break; \r\n  } \r\n  \r\n  /* Disable the Output compare channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); \r\n  \r\n  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  \r\n  {\r\n    /* Disable the Main Output */\r\n    __HAL_TIM_MOE_DISABLE(htim);\r\n  }\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim);  \r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the TIM Output Compare signal generation in DMA mode.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel TIM Channel to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @param  pData The source Buffer address.\r\n  * @param  Length The length of data to be transferred from memory to TIM peripheral\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n  \r\n  if((htim->State == HAL_TIM_STATE_BUSY))\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  else if((htim->State == HAL_TIM_STATE_READY))\r\n  {\r\n    if(((uint32_t)pData == 0 ) && (Length > 0)) \r\n    {\r\n      return HAL_ERROR;                                    \r\n    }\r\n    else\r\n    {\r\n      htim->State = HAL_TIM_STATE_BUSY;\r\n    }\r\n  }    \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {      \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);\r\n      \r\n      /* Enable the TIM Capture/Compare 1 DMA request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);\r\n      \r\n      /* Enable the TIM Capture/Compare 2 DMA request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);\r\n      \r\n      /* Enable the TIM Capture/Compare 3 DMA request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n     /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);\r\n      \r\n      /* Enable the TIM Capture/Compare 4 DMA request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break;\r\n  }\r\n\r\n  /* Enable the Output compare channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r\n  \r\n  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  \r\n  {\r\n    /* Enable the main output */\r\n    __HAL_TIM_MOE_ENABLE(htim);\r\n  }  \r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim); \r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the TIM Output Compare signal generation in DMA mode.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel TIM Channel to be disabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n  \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {       \r\n      /* Disable the TIM Capture/Compare 1 DMA request */\r\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Disable the TIM Capture/Compare 2 DMA request */\r\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      /* Disable the TIM Capture/Compare 3 DMA request */\r\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n      /* Disable the TIM Capture/Compare 4 interrupt */\r\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break;\r\n  } \r\n  \r\n  /* Disable the Output compare channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r\n  \r\n  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  \r\n  {\r\n    /* Disable the Main Output */\r\n    __HAL_TIM_MOE_DISABLE(htim);\r\n  }\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim);\r\n  \r\n  /* Change the htim state */\r\n  htim->State = HAL_TIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions \r\n *  @brief    Time PWM functions \r\n *\r\n@verbatim    \r\n  ==============================================================================\r\n                          ##### Time PWM functions #####\r\n  ==============================================================================\r\n  [..]  \r\n    This section provides functions allowing to:\r\n    (+) Initialize and configure the TIM OPWM. \r\n    (+) De-initialize the TIM PWM.\r\n    (+) Start the Time PWM.\r\n    (+) Stop the Time PWM.\r\n    (+) Start the Time PWM and enable interrupt.\r\n    (+) Stop the Time PWM and disable interrupt.\r\n    (+) Start the Time PWM and enable DMA transfer.\r\n    (+) Stop the Time PWM and disable DMA transfer.\r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n/**\r\n  * @brief  Initializes the TIM PWM Time Base according to the specified\r\n  *         parameters in the TIM_HandleTypeDef and create the associated handle.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Check the TIM handle allocation */\r\n  if(htim == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\r\n  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r\n  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r\n  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r\n\r\n  if(htim->State == HAL_TIM_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    htim->Lock = HAL_UNLOCKED;\r\n\r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\n    /* Reset interrupt callbacks to legacy week callbacks */\r\n    TIM_ResetCallback(htim);\r\n\r\n    if(htim->PWM_MspInitCallback == NULL)\r\n    {\r\n      htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;\r\n    }\r\n    /* Init the low level hardware : GPIO, CLOCK, NVIC */\r\n    htim->PWM_MspInitCallback(htim);\r\n#else\r\n    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r\n    HAL_TIM_PWM_MspInit(htim);\r\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n  }\r\n  /* Set the TIM state */\r\n  htim->State= HAL_TIM_STATE_BUSY;  \r\n  \r\n  /* Init the base time for the PWM */  \r\n  TIM_Base_SetConfig(htim->Instance, &htim->Init); \r\n   \r\n  /* Initialize the TIM state*/\r\n  htim->State= HAL_TIM_STATE_READY;\r\n  \r\n  return HAL_OK;\r\n}  \r\n\r\n/**\r\n  * @brief  DeInitializes the TIM peripheral \r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\r\n  \r\n  htim->State = HAL_TIM_STATE_BUSY;\r\n  \r\n  /* Disable the TIM Peripheral Clock */\r\n  __HAL_TIM_DISABLE(htim);\r\n\r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\n  if(htim->PWM_MspDeInitCallback == NULL)\r\n  {\r\n    htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;\r\n  }\r\n  /* DeInit the low level hardware */\r\n  htim->PWM_MspDeInitCallback(htim);\r\n#else\r\n  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\r\n  HAL_TIM_PWM_MspDeInit(htim);\r\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n\r\n  /* Change TIM state */  \r\n  htim->State = HAL_TIM_STATE_RESET; \r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(htim);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the TIM PWM MSP.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_TIM_PWM_MspInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes TIM PWM MSP.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_TIM_PWM_MspDeInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Starts the PWM signal generation.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n\r\n  /* Enable the Capture compare channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r\n  \r\n  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  \r\n  {\r\n    /* Enable the main output */\r\n    __HAL_TIM_MOE_ENABLE(htim);\r\n  }\r\n    \r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n} \r\n\r\n/**\r\n  * @brief  Stops the PWM signal generation.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel TIM Channels to be disabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{ \r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n    \r\n  /* Disable the Capture compare channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r\n  \r\n  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  \r\n  {\r\n    /* Disable the Main Output */\r\n    __HAL_TIM_MOE_DISABLE(htim);\r\n  }\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim);\r\n  \r\n  /* Change the htim state */\r\n  htim->State = HAL_TIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n} \r\n\r\n/**\r\n  * @brief  Starts the PWM signal generation in interrupt mode.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel TIM Channel to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n  \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {       \r\n      /* Enable the TIM Capture/Compare 1 interrupt */\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Enable the TIM Capture/Compare 2 interrupt */\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      /* Enable the TIM Capture/Compare 3 interrupt */\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n      /* Enable the TIM Capture/Compare 4 interrupt */\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break;\r\n  } \r\n  \r\n  /* Enable the Capture compare channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r\n  \r\n  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  \r\n  {\r\n    /* Enable the main output */\r\n    __HAL_TIM_MOE_ENABLE(htim);\r\n  }\r\n\r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n} \r\n\r\n/**\r\n  * @brief  Stops the PWM signal generation in interrupt mode.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel TIM Channels to be disabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n  \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {       \r\n      /* Disable the TIM Capture/Compare 1 interrupt */\r\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Disable the TIM Capture/Compare 2 interrupt */\r\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      /* Disable the TIM Capture/Compare 3 interrupt */\r\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n      /* Disable the TIM Capture/Compare 4 interrupt */\r\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break; \r\n  }\r\n  \r\n  /* Disable the Capture compare channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r\n  \r\n  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  \r\n  {\r\n    /* Disable the Main Output */\r\n    __HAL_TIM_MOE_DISABLE(htim);\r\n  }\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n} \r\n\r\n/**\r\n  * @brief  Starts the TIM PWM signal generation in DMA mode.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @param  pData The source Buffer address.\r\n  * @param  Length The length of data to be transferred from memory to TIM peripheral\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n  \r\n  if((htim->State == HAL_TIM_STATE_BUSY))\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  else if((htim->State == HAL_TIM_STATE_READY))\r\n  {\r\n    if(((uint32_t)pData == 0 ) && (Length > 0)) \r\n    {\r\n      return HAL_ERROR;                                    \r\n    }\r\n    else\r\n    {\r\n      htim->State = HAL_TIM_STATE_BUSY;\r\n    }\r\n  }    \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {      \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);\r\n      \r\n      /* Enable the TIM Capture/Compare 1 DMA request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);\r\n      \r\n      /* Enable the TIM Capture/Compare 2 DMA request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);\r\n      \r\n      /* Enable the TIM Output Capture/Compare 3 request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n     /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);\r\n      \r\n      /* Enable the TIM Capture/Compare 4 DMA request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break;\r\n  }\r\n\r\n  /* Enable the Capture compare channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r\n    \r\n  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  \r\n  {\r\n    /* Enable the main output */\r\n    __HAL_TIM_MOE_ENABLE(htim);\r\n  }\r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim); \r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the TIM PWM signal generation in DMA mode.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel TIM Channels to be disabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n  \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {       \r\n      /* Disable the TIM Capture/Compare 1 DMA request */\r\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Disable the TIM Capture/Compare 2 DMA request */\r\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      /* Disable the TIM Capture/Compare 3 DMA request */\r\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n      /* Disable the TIM Capture/Compare 4 interrupt */\r\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break;\r\n  } \r\n  \r\n  /* Disable the Capture compare channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r\n  \r\n  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  \r\n  {\r\n    /* Disable the Main Output */\r\n    __HAL_TIM_MOE_DISABLE(htim);\r\n  }\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim);\r\n  \r\n  /* Change the htim state */\r\n  htim->State = HAL_TIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions \r\n *  @brief    Time Input Capture functions \r\n *\r\n@verbatim    \r\n  ==============================================================================\r\n              ##### Time Input Capture functions #####\r\n  ==============================================================================\r\n [..]  \r\n   This section provides functions allowing to:\r\n   (+) Initialize and configure the TIM Input Capture. \r\n   (+) De-initialize the TIM Input Capture.\r\n   (+) Start the Time Input Capture.\r\n   (+) Stop the Time Input Capture.\r\n   (+) Start the Time Input Capture and enable interrupt.\r\n   (+) Stop the Time Input Capture and disable interrupt.\r\n   (+) Start the Time Input Capture and enable DMA transfer.\r\n   (+) Stop the Time Input Capture and disable DMA transfer.\r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n/**\r\n  * @brief  Initializes the TIM Input Capture Time base according to the specified\r\n  *         parameters in the TIM_HandleTypeDef and create the associated handle.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Check the TIM handle allocation */\r\n  if(htim == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\r\n  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r\n  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); \r\n  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r\n\r\n  if(htim->State == HAL_TIM_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    htim->Lock = HAL_UNLOCKED;\r\n\r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\n    /* Reset interrupt callbacks to legacy week callbacks */\r\n    TIM_ResetCallback(htim);\r\n\r\n    if(htim->IC_MspInitCallback == NULL)\r\n    {\r\n      htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;\r\n    }\r\n    /* Init the low level hardware : GPIO, CLOCK, NVIC */\r\n    htim->IC_MspInitCallback(htim);\r\n#else\r\n    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r\n    HAL_TIM_IC_MspInit(htim);\r\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n  }\r\n\r\n  /* Set the TIM state */\r\n  htim->State= HAL_TIM_STATE_BUSY;   \r\n  \r\n  /* Init the base time for the input capture */  \r\n  TIM_Base_SetConfig(htim->Instance, &htim->Init); \r\n   \r\n  /* Initialize the TIM state*/\r\n  htim->State= HAL_TIM_STATE_READY;\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the TIM peripheral \r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\r\n\r\n  htim->State = HAL_TIM_STATE_BUSY;\r\n  \r\n  /* Disable the TIM Peripheral Clock */\r\n  __HAL_TIM_DISABLE(htim);\r\n\r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\n  if(htim->IC_MspDeInitCallback == NULL)\r\n  {\r\n    htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;\r\n  }\r\n  /* DeInit the low level hardware */\r\n  htim->IC_MspDeInitCallback(htim);\r\n#else\r\n  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\r\n  HAL_TIM_IC_MspDeInit(htim);\r\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n\r\n  /* Change TIM state */  \r\n  htim->State = HAL_TIM_STATE_RESET;\r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(htim);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the TIM INput Capture MSP.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_TIM_IC_MspInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes TIM Input Capture MSP.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n   \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_TIM_IC_MspDeInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Starts the TIM Input Capture measurement.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n  \r\n  /* Enable the Input Capture channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r\n    \r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim);  \r\n\r\n  /* Return function status */\r\n  return HAL_OK;  \r\n} \r\n\r\n/**\r\n  * @brief  Stops the TIM Input Capture measurement.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel TIM Channels to be disabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{ \r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n  \r\n  /* Disable the Input Capture channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim); \r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the TIM Input Capture measurement in interrupt mode.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n  \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {       \r\n      /* Enable the TIM Capture/Compare 1 interrupt */\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Enable the TIM Capture/Compare 2 interrupt */\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      /* Enable the TIM Capture/Compare 3 interrupt */\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n      /* Enable the TIM Capture/Compare 4 interrupt */\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break;\r\n  }  \r\n  /* Enable the Input Capture channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r\n    \r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim);  \r\n\r\n  /* Return function status */\r\n  return HAL_OK;  \r\n} \r\n\r\n/**\r\n  * @brief  Stops the TIM Input Capture measurement in interrupt mode.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel TIM Channels to be disabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n  \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {       \r\n      /* Disable the TIM Capture/Compare 1 interrupt */\r\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Disable the TIM Capture/Compare 2 interrupt */\r\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      /* Disable the TIM Capture/Compare 3 interrupt */\r\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n      /* Disable the TIM Capture/Compare 4 interrupt */\r\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break; \r\n  } \r\n  \r\n  /* Disable the Input Capture channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); \r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim); \r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the TIM Input Capture measurement on in DMA mode.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @param  pData The destination Buffer address.\r\n  * @param  Length The length of data to be transferred from TIM peripheral to memory.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r\n  \r\n  if((htim->State == HAL_TIM_STATE_BUSY))\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  else if((htim->State == HAL_TIM_STATE_READY))\r\n  {\r\n    if((pData == 0 ) && (Length > 0)) \r\n    {\r\n      return HAL_ERROR;                                    \r\n    }\r\n    else\r\n    {\r\n      htim->State = HAL_TIM_STATE_BUSY;\r\n    }\r\n  }  \r\n   \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {\r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); \r\n      \r\n      /* Enable the TIM Capture/Compare 1 DMA request */      \r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);\r\n      \r\n      /* Enable the TIM Capture/Compare 2  DMA request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);\r\n      \r\n      /* Enable the TIM Capture/Compare 3  DMA request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);\r\n      \r\n      /* Enable the TIM Capture/Compare 4  DMA request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break;\r\n  }\r\n\r\n  /* Enable the Input Capture channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r\n   \r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim); \r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the TIM Input Capture measurement on in DMA mode.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel TIM Channels to be disabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r\n  \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {       \r\n      /* Disable the TIM Capture/Compare 1 DMA request */\r\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Disable the TIM Capture/Compare 2 DMA request */\r\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      /* Disable the TIM Capture/Compare 3  DMA request */\r\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n      /* Disable the TIM Capture/Compare 4  DMA request */\r\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break;\r\n  }\r\n\r\n  /* Disable the Input Capture channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim); \r\n  \r\n  /* Change the htim state */\r\n  htim->State = HAL_TIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}  \r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions \r\n *  @brief    Time One Pulse functions \r\n *\r\n@verbatim    \r\n  ==============================================================================\r\n                        ##### Time One Pulse functions #####\r\n  ==============================================================================\r\n  [..]  \r\n    This section provides functions allowing to:\r\n    (+) Initialize and configure the TIM One Pulse. \r\n    (+) De-initialize the TIM One Pulse.\r\n    (+) Start the Time One Pulse.\r\n    (+) Stop the Time One Pulse.\r\n    (+) Start the Time One Pulse and enable interrupt.\r\n    (+) Stop the Time One Pulse and disable interrupt.\r\n    (+) Start the Time One Pulse and enable DMA transfer.\r\n    (+) Stop the Time One Pulse and disable DMA transfer.\r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n/**\r\n  * @brief  Initializes the TIM One Pulse Time Base according to the specified\r\n  *         parameters in the TIM_HandleTypeDef and create the associated handle.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  OnePulseMode Select the One pulse mode.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.\r\n  *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)\r\n{\r\n  /* Check the TIM handle allocation */\r\n  if(htim == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\r\n  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r\n  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r\n  assert_param(IS_TIM_OPM_MODE(OnePulseMode));\r\n  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r\n\r\n  if(htim->State == HAL_TIM_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    htim->Lock = HAL_UNLOCKED;\r\n\r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\n    /* Reset interrupt callbacks to legacy week callbacks */\r\n    TIM_ResetCallback(htim);\r\n\r\n    if(htim->OnePulse_MspDeInitCallback == NULL)\r\n    {\r\n      htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspInit;\r\n    }\r\n    /* Init the low level hardware : GPIO, CLOCK, NVIC */\r\n    htim->OnePulse_MspDeInitCallback(htim);\r\n#else\r\n    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r\n    HAL_TIM_OnePulse_MspInit(htim);\r\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n  }\r\n\r\n  /* Set the TIM state */\r\n  htim->State= HAL_TIM_STATE_BUSY;  \r\n  \r\n  /* Configure the Time base in the One Pulse Mode */\r\n  TIM_Base_SetConfig(htim->Instance, &htim->Init);\r\n  \r\n  /* Reset the OPM Bit */\r\n  htim->Instance->CR1 &= ~TIM_CR1_OPM;\r\n\r\n  /* Configure the OPM Mode */\r\n  htim->Instance->CR1 |= OnePulseMode;\r\n   \r\n  /* Initialize the TIM state*/\r\n  htim->State= HAL_TIM_STATE_READY;\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the TIM One Pulse  \r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\r\n  \r\n  htim->State = HAL_TIM_STATE_BUSY;\r\n  \r\n  /* Disable the TIM Peripheral Clock */\r\n  __HAL_TIM_DISABLE(htim);\r\n\r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\n  if(htim->OnePulse_MspDeInitCallback == NULL)\r\n  {\r\n    htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;\r\n  }\r\n  /* DeInit the low level hardware */\r\n  htim->OnePulse_MspDeInitCallback(htim);\r\n#else\r\n  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r\n  HAL_TIM_OnePulse_MspDeInit(htim);\r\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n\r\n  /* Change TIM state */  \r\n  htim->State = HAL_TIM_STATE_RESET;\r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(htim);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the TIM One Pulse MSP.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_TIM_OnePulse_MspInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes TIM One Pulse MSP.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Starts the TIM One Pulse signal generation.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  OutputChannel  TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(OutputChannel);\r\n\r\n  /* Enable the Capture compare and the Input Capture channels \r\n    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r\n    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r\n    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output \r\n    in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together \r\n    \r\n    No need to enable the counter, it's enabled automatically by hardware \r\n    (the counter starts in response to a stimulus and generate a pulse */\r\n  \r\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); \r\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); \r\n  \r\n  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  \r\n  {\r\n    /* Enable the main output */\r\n    __HAL_TIM_MOE_ENABLE(htim);\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the TIM One Pulse signal generation.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  OutputChannel  TIM Channels to be disable.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(OutputChannel);\r\n\r\n  /* Disable the Capture compare and the Input Capture channels \r\n  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r\n  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r\n  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output \r\n  in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */\r\n  \r\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); \r\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); \r\n    \r\n  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  \r\n  {\r\n    /* Disable the Main Output */\r\n    __HAL_TIM_MOE_DISABLE(htim);\r\n  }\r\n    \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim); \r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the TIM One Pulse signal generation in interrupt mode.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  OutputChannel  TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r\n{\r\n  /* Enable the Capture compare and the Input Capture channels \r\n    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r\n    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r\n    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output \r\n    in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together \r\n    \r\n    No need to enable the counter, it's enabled automatically by hardware \r\n    (the counter starts in response to a stimulus and generate a pulse */\r\n\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(OutputChannel);\r\n\r\n  /* Enable the TIM Capture/Compare 1 interrupt */\r\n  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r\n  \r\n  /* Enable the TIM Capture/Compare 2 interrupt */\r\n  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r\n  \r\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); \r\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); \r\n  \r\n  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  \r\n  {\r\n    /* Enable the main output */\r\n    __HAL_TIM_MOE_ENABLE(htim);\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the TIM One Pulse signal generation in interrupt mode.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  OutputChannel  TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(OutputChannel);\r\n  \r\n  /* Disable the TIM Capture/Compare 1 interrupt */\r\n  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);  \r\n  \r\n  /* Disable the TIM Capture/Compare 2 interrupt */\r\n  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r\n  \r\n  /* Disable the Capture compare and the Input Capture channels \r\n  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r\n  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r\n  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output \r\n  in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */  \r\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); \r\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); \r\n    \r\n  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  \r\n  {\r\n    /* Disable the Main Output */\r\n    __HAL_TIM_MOE_DISABLE(htim);\r\n  }\r\n    \r\n  /* Disable the Peripheral */\r\n   __HAL_TIM_DISABLE(htim);  \r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions \r\n *  @brief    Time Encoder functions \r\n *\r\n@verbatim    \r\n  ==============================================================================\r\n                          ##### Time Encoder functions #####\r\n  ==============================================================================\r\n  [..]\r\n    This section provides functions allowing to:\r\n    (+) Initialize and configure the TIM Encoder. \r\n    (+) De-initialize the TIM Encoder.\r\n    (+) Start the Time Encoder.\r\n    (+) Stop the Time Encoder.\r\n    (+) Start the Time Encoder and enable interrupt.\r\n    (+) Stop the Time Encoder and disable interrupt.\r\n    (+) Start the Time Encoder and enable DMA transfer.\r\n    (+) Stop the Time Encoder and disable DMA transfer.\r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n/**\r\n  * @brief  Initializes the TIM Encoder Interface and create the associated handle.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  sConfig TIM Encoder Interface configuration structure\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig)\r\n{\r\n  uint32_t tmpsmcr = 0;\r\n  uint32_t tmpccmr1 = 0;\r\n  uint32_t tmpccer = 0;\r\n  \r\n  /* Check the TIM handle allocation */\r\n  if(htim == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n   \r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r\n  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r\n  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\r\n  assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));\r\n  assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));\r\n  assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));\r\n  assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));\r\n  assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));\r\n  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));\r\n  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));\r\n  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));\r\n  assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));\r\n\r\n  if(htim->State == HAL_TIM_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    htim->Lock = HAL_UNLOCKED;\r\n\r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\n    /* Reset interrupt callbacks to legacy week callbacks */\r\n    TIM_ResetCallback(htim);\r\n\r\n    if(htim->Encoder_MspInitCallback == NULL)\r\n    {\r\n      htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;\r\n    }\r\n    /* Init the low level hardware : GPIO, CLOCK, NVIC */\r\n    htim->Encoder_MspInitCallback(htim);\r\n#else\r\n    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r\n    HAL_TIM_Encoder_MspInit(htim);\r\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n  }\r\n\r\n  /* Set the TIM state */\r\n  htim->State= HAL_TIM_STATE_BUSY;   \r\n    \r\n  /* Reset the SMS bits */\r\n  htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r\n  \r\n  /* Configure the Time base in the Encoder Mode */\r\n  TIM_Base_SetConfig(htim->Instance, &htim->Init);  \r\n  \r\n  /* Get the TIMx SMCR register value */\r\n  tmpsmcr = htim->Instance->SMCR;\r\n\r\n  /* Get the TIMx CCMR1 register value */\r\n  tmpccmr1 = htim->Instance->CCMR1;\r\n\r\n  /* Get the TIMx CCER register value */\r\n  tmpccer = htim->Instance->CCER;\r\n\r\n  /* Set the encoder Mode */\r\n  tmpsmcr |= sConfig->EncoderMode;\r\n\r\n  /* Select the Capture Compare 1 and the Capture Compare 2 as input */\r\n  tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);\r\n  tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));\r\n  \r\n  /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */\r\n  tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);\r\n  tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);\r\n  tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);\r\n  tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);\r\n\r\n  /* Set the TI1 and the TI2 Polarities */\r\n  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);\r\n  tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);\r\n  tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);\r\n  \r\n  /* Write to TIMx SMCR */\r\n  htim->Instance->SMCR = tmpsmcr;\r\n\r\n  /* Write to TIMx CCMR1 */\r\n  htim->Instance->CCMR1 = tmpccmr1;\r\n\r\n  /* Write to TIMx CCER */\r\n  htim->Instance->CCER = tmpccer;\r\n  \r\n  /* Initialize the TIM state*/\r\n  htim->State= HAL_TIM_STATE_READY;\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the TIM Encoder interface  \r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\r\n  \r\n  htim->State = HAL_TIM_STATE_BUSY;\r\n  \r\n  /* Disable the TIM Peripheral Clock */\r\n  __HAL_TIM_DISABLE(htim);\r\n\r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\n  if(htim->Encoder_MspDeInitCallback == NULL)\r\n  {\r\n    htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;\r\n  }\r\n  /* DeInit the low level hardware */\r\n  htim->Encoder_MspDeInitCallback(htim);\r\n#else\r\n  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r\n  HAL_TIM_Encoder_MspDeInit(htim);\r\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n\r\n  /* Change TIM state */  \r\n  htim->State = HAL_TIM_STATE_RESET;\r\n \r\n  /* Release Lock */\r\n  __HAL_UNLOCK(htim);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the TIM Encoder Interface MSP.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_TIM_Encoder_MspInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes TIM Encoder Interface MSP.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_TIM_Encoder_MspDeInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Starts the TIM Encoder Interface.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n  \r\n  /* Enable the encoder interface channels */\r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {\r\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r\n      break; \r\n    }\r\n    case TIM_CHANNEL_2:\r\n    { \r\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); \r\n      break;\r\n    }  \r\n    default :\r\n    {\r\n     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r\n     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r\n     break; \r\n    }\r\n  }  \r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the TIM Encoder Interface.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel TIM Channels to be disabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n    \r\n   /* Disable the Input Capture channels 1 and 2\r\n    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {\r\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r\n      break; \r\n    }\r\n    case TIM_CHANNEL_2:\r\n    { \r\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); \r\n      break;\r\n    }  \r\n    default :\r\n    {\r\n     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r\n     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r\n     break; \r\n    }\r\n  }  \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the TIM Encoder Interface in interrupt mode.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n  \r\n  /* Enable the encoder interface channels */\r\n  /* Enable the capture compare Interrupts 1 and/or 2 */\r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {\r\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r\n      break; \r\n    }\r\n    case TIM_CHANNEL_2:\r\n    { \r\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); \r\n      break;\r\n    }  \r\n    default :\r\n    {\r\n     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r\n     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r\n     __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r\n     __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r\n     break; \r\n    }\r\n  }\r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the TIM Encoder Interface in interrupt mode.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel TIM Channels to be disabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n    \r\n  /* Disable the Input Capture channels 1 and 2\r\n    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ \r\n  if(Channel == TIM_CHANNEL_1)\r\n  {\r\n    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); \r\n    \r\n    /* Disable the capture compare Interrupts 1 */\r\n  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r\n  }  \r\n  else if(Channel == TIM_CHANNEL_2)\r\n  {  \r\n    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); \r\n    \r\n    /* Disable the capture compare Interrupts 2 */\r\n  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r\n  }  \r\n  else\r\n  {\r\n    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); \r\n    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); \r\n    \r\n    /* Disable the capture compare Interrupts 1 and 2 */\r\n    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r\n    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r\n  }\r\n    \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim);\r\n  \r\n  /* Change the htim state */\r\n  htim->State = HAL_TIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the TIM Encoder Interface in DMA mode.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r\n  * @param  pData1 The destination Buffer address for IC1.\r\n  * @param  pData2 The destination Buffer address for IC2.\r\n  * @param  Length The length of data to be transferred from TIM peripheral to memory.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r\n  \r\n  if((htim->State == HAL_TIM_STATE_BUSY))\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  else if((htim->State == HAL_TIM_STATE_READY))\r\n  {\r\n    if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0)) \r\n    {\r\n      return HAL_ERROR;                                    \r\n    }\r\n    else\r\n    {\r\n      htim->State = HAL_TIM_STATE_BUSY;\r\n    }\r\n  }  \r\n   \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {\r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length); \r\n      \r\n      /* Enable the TIM Input Capture DMA request */      \r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r\n            \r\n      /* Enable the Peripheral */\r\n      __HAL_TIM_ENABLE(htim);\r\n      \r\n      /* Enable the Capture compare channel */\r\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError;\r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);\r\n      \r\n      /* Enable the TIM Input Capture  DMA request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r\n     \r\n      /* Enable the Peripheral */\r\n      __HAL_TIM_ENABLE(htim);\r\n      \r\n      /* Enable the Capture compare channel */\r\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_ALL:\r\n    {\r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);\r\n      \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);\r\n          \r\n     /* Enable the Peripheral */\r\n      __HAL_TIM_ENABLE(htim);\r\n      \r\n      /* Enable the Capture compare channel */\r\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r\n      \r\n      /* Enable the TIM Input Capture  DMA request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r\n      /* Enable the TIM Input Capture  DMA request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break;\r\n  }  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the TIM Encoder Interface in DMA mode.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r\n  \r\n  /* Disable the Input Capture channels 1 and 2\r\n    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ \r\n  if(Channel == TIM_CHANNEL_1)\r\n  {\r\n    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); \r\n    \r\n    /* Disable the capture compare DMA Request 1 */\r\n    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r\n  }  \r\n  else if(Channel == TIM_CHANNEL_2)\r\n  {  \r\n    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); \r\n    \r\n    /* Disable the capture compare DMA Request 2 */\r\n    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r\n  }  \r\n  else\r\n  {\r\n    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); \r\n    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); \r\n    \r\n    /* Disable the capture compare DMA Request 1 and 2 */\r\n    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r\n    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r\n  }\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim);\r\n  \r\n  /* Change the htim state */\r\n  htim->State = HAL_TIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management \r\n *  @brief    IRQ handler management \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                        ##### IRQ handler management #####\r\n  ==============================================================================  \r\n  [..]  \r\n    This section provides Timer IRQ handler function.\r\n               \r\n@endverbatim\r\n  * @{\r\n  */\r\n/**\r\n  * @brief  This function handles TIM interrupts requests.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\nvoid HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Capture compare 1 event */\r\n  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)\r\n  {\r\n    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)\r\n    {\r\n      {\r\n        __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);\r\n        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r\n        \r\n        /* Input capture event */\r\n        if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)\r\n        {\r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\n          htim->IC_CaptureCallback(htim);\r\n#else\r\n          HAL_TIM_IC_CaptureCallback(htim);\r\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n        }\r\n        /* Output compare event */\r\n        else\r\n        {\r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\n          htim->OC_DelayElapsedCallback(htim);\r\n          htim->PWM_PulseFinishedCallback(htim);\r\n#else\r\n          HAL_TIM_OC_DelayElapsedCallback(htim);\r\n          HAL_TIM_PWM_PulseFinishedCallback(htim);\r\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n        }\r\n        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r\n      }\r\n    }\r\n  }\r\n  /* Capture compare 2 event */\r\n  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)\r\n  {\r\n    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)\r\n    {\r\n      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);\r\n      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r\n      /* Input capture event */\r\n      if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)\r\n      {\r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\n        htim->IC_CaptureCallback(htim);\r\n#else\r\n        HAL_TIM_IC_CaptureCallback(htim);\r\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n      }\r\n      /* Output compare event */\r\n      else\r\n      {\r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\n        htim->OC_DelayElapsedCallback(htim);\r\n        htim->PWM_PulseFinishedCallback(htim);\r\n#else\r\n        HAL_TIM_OC_DelayElapsedCallback(htim);\r\n        HAL_TIM_PWM_PulseFinishedCallback(htim);\r\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n      }\r\n      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r\n    }\r\n  }\r\n  /* Capture compare 3 event */\r\n  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)\r\n  {\r\n    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)\r\n    {\r\n      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);\r\n      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r\n      /* Input capture event */\r\n      if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)\r\n      {          \r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\n        htim->IC_CaptureCallback(htim);\r\n#else\r\n        HAL_TIM_IC_CaptureCallback(htim);\r\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n      }\r\n      /* Output compare event */\r\n      else\r\n      {\r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\n        htim->OC_DelayElapsedCallback(htim);\r\n        htim->PWM_PulseFinishedCallback(htim);\r\n#else\r\n        HAL_TIM_OC_DelayElapsedCallback(htim);\r\n        HAL_TIM_PWM_PulseFinishedCallback(htim);\r\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n      }\r\n      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r\n    }\r\n  }\r\n  /* Capture compare 4 event */\r\n  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)\r\n  {\r\n    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)\r\n    {\r\n      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);\r\n      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r\n      /* Input capture event */\r\n      if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)\r\n      {          \r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\n        htim->IC_CaptureCallback(htim);\r\n#else\r\n        HAL_TIM_IC_CaptureCallback(htim);\r\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n      }\r\n      /* Output compare event */\r\n      else\r\n      {\r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\n        htim->OC_DelayElapsedCallback(htim);\r\n        htim->PWM_PulseFinishedCallback(htim);\r\n#else\r\n        HAL_TIM_OC_DelayElapsedCallback(htim);\r\n        HAL_TIM_PWM_PulseFinishedCallback(htim);\r\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n      }\r\n      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r\n    }\r\n  }\r\n  /* TIM Update event */\r\n  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)\r\n  {\r\n    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)\r\n    {\r\n      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);\r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\n      htim->PeriodElapsedCallback(htim);\r\n#else\r\n      HAL_TIM_PeriodElapsedCallback(htim);\r\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n    }\r\n  }\r\n  /* TIM Break input event */\r\n  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)\r\n  {\r\n    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)\r\n    {\r\n      __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);\r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\n      htim->BreakCallback(htim);\r\n#else\r\n      HAL_TIMEx_BreakCallback(htim);\r\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n\r\n    }\r\n  }\r\n  \r\n    /* TIM Break input event */\r\n  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)\r\n  {\r\n    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)\r\n    {\r\n      __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);\r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\n      htim->BreakCallback(htim);\r\n#else\r\n      HAL_TIMEx_BreakCallback(htim);\r\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n    }\r\n  }\r\n\r\n  /* TIM Trigger detection event */\r\n  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)\r\n  {\r\n    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)\r\n    {\r\n      __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);\r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\n      htim->TriggerCallback(htim);\r\n#else\r\n      HAL_TIM_TriggerCallback(htim);\r\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n    }\r\n  }\r\n  /* TIM commutation event */\r\n  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)\r\n  {\r\n    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)\r\n    {\r\n      __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);\r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\n      htim->CommutationCallback(htim);\r\n#else\r\n      HAL_TIMEx_CommutationCallback(htim);\r\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions\r\n *  @brief   \tPeripheral Control functions \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                   ##### Peripheral Control functions #####\r\n  ==============================================================================  \r\n [..] \r\n   This section provides functions allowing to:\r\n   (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. \r\n   (+) Configure External Clock source.\r\n   (+) Configure Complementary channels, break features and dead time.\r\n   (+) Configure Master and the Slave synchronization.\r\n   (+) Configure the DMA Burst Mode.\r\n      \r\n@endverbatim\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @brief  Initializes the TIM Output Compare Channels according to the specified\r\n  *         parameters in the TIM_OC_InitTypeDef.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  sConfig TIM Output Compare configuration structure\r\n  * @param  Channel TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected \r\n  * @retval HAL status\r\n  */\r\n__weak HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)\r\n{\r\n  /* Check the parameters */ \r\n  assert_param(IS_TIM_CHANNELS(Channel)); \r\n  assert_param(IS_TIM_OC_MODE(sConfig->OCMode));\r\n  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));\r\n  \r\n  /* Check input state */\r\n  __HAL_LOCK(htim); \r\n  \r\n  htim->State = HAL_TIM_STATE_BUSY;\r\n  \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {\r\n      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r\n      /* Configure the TIM Channel 1 in Output Compare */\r\n      TIM_OC1_SetConfig(htim->Instance, sConfig);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n      /* Configure the TIM Channel 2 in Output Compare */\r\n      TIM_OC2_SetConfig(htim->Instance, sConfig);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r\n      /* Configure the TIM Channel 3 in Output Compare */\r\n      TIM_OC3_SetConfig(htim->Instance, sConfig);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r\n      /* Configure the TIM Channel 4 in Output Compare */\r\n      TIM_OC4_SetConfig(htim->Instance, sConfig);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break;    \r\n  }\r\n  htim->State = HAL_TIM_STATE_READY;\r\n  \r\n  __HAL_UNLOCK(htim); \r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the TIM Input Capture Channels according to the specified\r\n  *         parameters in the TIM_IC_InitTypeDef.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  sConfig TIM Input Capture configuration structure\r\n  * @param  Channel TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r\n  assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));\r\n  assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));\r\n  assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));\r\n  assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));\r\n  \r\n  __HAL_LOCK(htim);\r\n  \r\n  htim->State = HAL_TIM_STATE_BUSY;\r\n  \r\n  if (Channel == TIM_CHANNEL_1)\r\n  {\r\n    /* TI1 Configuration */\r\n    TIM_TI1_SetConfig(htim->Instance,\r\n               sConfig->ICPolarity,\r\n               sConfig->ICSelection,\r\n               sConfig->ICFilter);\r\n               \r\n    /* Reset the IC1PSC Bits */\r\n    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;\r\n\r\n    /* Set the IC1PSC value */\r\n    htim->Instance->CCMR1 |= sConfig->ICPrescaler;\r\n  }\r\n  else if (Channel == TIM_CHANNEL_2)\r\n  {\r\n    /* TI2 Configuration */\r\n    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n    \r\n    TIM_TI2_SetConfig(htim->Instance, \r\n                      sConfig->ICPolarity,\r\n                      sConfig->ICSelection,\r\n                      sConfig->ICFilter);\r\n               \r\n    /* Reset the IC2PSC Bits */\r\n    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;\r\n\r\n    /* Set the IC2PSC value */\r\n    htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);\r\n  }\r\n  else if (Channel == TIM_CHANNEL_3)\r\n  {\r\n    /* TI3 Configuration */\r\n    assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r\n    \r\n    TIM_TI3_SetConfig(htim->Instance,  \r\n               sConfig->ICPolarity,\r\n               sConfig->ICSelection,\r\n               sConfig->ICFilter);\r\n               \r\n    /* Reset the IC3PSC Bits */\r\n    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;\r\n\r\n    /* Set the IC3PSC value */\r\n    htim->Instance->CCMR2 |= sConfig->ICPrescaler;\r\n  }\r\n  else\r\n  {\r\n    /* TI4 Configuration */\r\n    assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r\n    \r\n    TIM_TI4_SetConfig(htim->Instance, \r\n               sConfig->ICPolarity,\r\n               sConfig->ICSelection,\r\n               sConfig->ICFilter);\r\n               \r\n    /* Reset the IC4PSC Bits */\r\n    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;\r\n\r\n    /* Set the IC4PSC value */\r\n    htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);\r\n  }\r\n  \r\n  htim->State = HAL_TIM_STATE_READY;\r\n    \r\n  __HAL_UNLOCK(htim);\r\n  \r\n  return HAL_OK; \r\n}\r\n\r\n/**\r\n  * @brief  Initializes the TIM PWM  channels according to the specified\r\n  *         parameters in the TIM_OC_InitTypeDef.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  sConfig TIM PWM configuration structure\r\n  * @param  Channel TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\n__weak HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)\r\n{\r\n  __HAL_LOCK(htim);\r\n  \r\n  /* Check the parameters */ \r\n  assert_param(IS_TIM_CHANNELS(Channel)); \r\n  assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));\r\n  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));\r\n  assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); \r\n  \r\n  htim->State = HAL_TIM_STATE_BUSY;\r\n    \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {\r\n      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r\n      /* Configure the Channel 1 in PWM mode */\r\n      TIM_OC1_SetConfig(htim->Instance, sConfig);\r\n      \r\n      /* Set the Preload enable bit for channel1 */\r\n      htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;\r\n      \r\n      /* Configure the Output Fast mode */\r\n      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;\r\n      htim->Instance->CCMR1 |= sConfig->OCFastMode;\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n      /* Configure the Channel 2 in PWM mode */\r\n      TIM_OC2_SetConfig(htim->Instance, sConfig);\r\n      \r\n      /* Set the Preload enable bit for channel2 */\r\n      htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;\r\n      \r\n      /* Configure the Output Fast mode */\r\n      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;\r\n      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r\n      /* Configure the Channel 3 in PWM mode */\r\n      TIM_OC3_SetConfig(htim->Instance, sConfig);\r\n      \r\n      /* Set the Preload enable bit for channel3 */\r\n      htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;\r\n      \r\n     /* Configure the Output Fast mode */\r\n      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;\r\n      htim->Instance->CCMR2 |= sConfig->OCFastMode;  \r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r\n      /* Configure the Channel 4 in PWM mode */\r\n      TIM_OC4_SetConfig(htim->Instance, sConfig);\r\n      \r\n      /* Set the Preload enable bit for channel4 */\r\n      htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;\r\n      \r\n     /* Configure the Output Fast mode */\r\n      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;\r\n      htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;  \r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break;    \r\n  }\r\n  \r\n  htim->State = HAL_TIM_STATE_READY;\r\n    \r\n  __HAL_UNLOCK(htim);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the TIM One Pulse Channels according to the specified\r\n  *         parameters in the TIM_OnePulse_InitTypeDef.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  sConfig TIM One Pulse configuration structure\r\n  * @param  OutputChannel TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  * @param  InputChannel TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel,  uint32_t InputChannel)\r\n{\r\n  TIM_OC_InitTypeDef temp1;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));\r\n  assert_param(IS_TIM_OPM_CHANNELS(InputChannel));\r\n\r\n  if(OutputChannel != InputChannel)  \r\n  {\r\n    __HAL_LOCK(htim);\r\n  \r\n    htim->State = HAL_TIM_STATE_BUSY;\r\n\r\n    /* Extract the Output compare configuration from sConfig structure */  \r\n    temp1.OCMode = sConfig->OCMode;\r\n    temp1.Pulse = sConfig->Pulse;\r\n    temp1.OCPolarity = sConfig->OCPolarity;\r\n    temp1.OCNPolarity = sConfig->OCNPolarity;\r\n    temp1.OCIdleState = sConfig->OCIdleState;\r\n    temp1.OCNIdleState = sConfig->OCNIdleState; \r\n    \r\n    switch (OutputChannel)\r\n    {\r\n      case TIM_CHANNEL_1:\r\n      {\r\n        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r\n      \r\n        TIM_OC1_SetConfig(htim->Instance, &temp1); \r\n      }\r\n      break;\r\n      case TIM_CHANNEL_2:\r\n      {\r\n        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n      \r\n        TIM_OC2_SetConfig(htim->Instance, &temp1);\r\n      }\r\n      break;\r\n      default:\r\n      break;  \r\n    } \r\n    switch (InputChannel)\r\n    {\r\n      case TIM_CHANNEL_1:\r\n      {\r\n        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r\n      \r\n        TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,\r\n                        sConfig->ICSelection, sConfig->ICFilter);\r\n               \r\n        /* Reset the IC1PSC Bits */\r\n        htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;\r\n\r\n        /* Select the Trigger source */\r\n        htim->Instance->SMCR &= ~TIM_SMCR_TS;\r\n        htim->Instance->SMCR |= TIM_TS_TI1FP1;\r\n      \r\n        /* Select the Slave Mode */      \r\n        htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r\n        htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;\r\n      }\r\n      break;\r\n      case TIM_CHANNEL_2:\r\n      {\r\n        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n      \r\n        TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,\r\n                 sConfig->ICSelection, sConfig->ICFilter);\r\n               \r\n        /* Reset the IC2PSC Bits */\r\n        htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;\r\n\r\n        /* Select the Trigger source */\r\n        htim->Instance->SMCR &= ~TIM_SMCR_TS;\r\n        htim->Instance->SMCR |= TIM_TS_TI2FP2;\r\n      \r\n        /* Select the Slave Mode */      \r\n        htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r\n        htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;\r\n      }\r\n      break;\r\n    \r\n      default:\r\n      break;  \r\n    }\r\n  \r\n    htim->State = HAL_TIM_STATE_READY;\r\n    \r\n    __HAL_UNLOCK(htim);\r\n  \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n} \r\n\r\n/**\r\n  * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral  \r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  BurstBaseAddress TIM Base address from when the DMA will starts the Data write.\r\n  *         This parameters can be on of the following values:\r\n  *            @arg TIM_DMABASE_CR1  \r\n  *            @arg TIM_DMABASE_CR2\r\n  *            @arg TIM_DMABASE_SMCR\r\n  *            @arg TIM_DMABASE_DIER\r\n  *            @arg TIM_DMABASE_SR\r\n  *            @arg TIM_DMABASE_EGR\r\n  *            @arg TIM_DMABASE_CCMR1\r\n  *            @arg TIM_DMABASE_CCMR2\r\n  *            @arg TIM_DMABASE_CCER\r\n  *            @arg TIM_DMABASE_CNT   \r\n  *            @arg TIM_DMABASE_PSC   \r\n  *            @arg TIM_DMABASE_ARR\r\n  *            @arg TIM_DMABASE_RCR\r\n  *            @arg TIM_DMABASE_CCR1\r\n  *            @arg TIM_DMABASE_CCR2\r\n  *            @arg TIM_DMABASE_CCR3  \r\n  *            @arg TIM_DMABASE_CCR4\r\n  *            @arg TIM_DMABASE_BDTR\r\n  *            @arg TIM_DMABASE_DCR\r\n  * @param  BurstRequestSrc TIM DMA Request sources.\r\n  *         This parameters can be on of the following values:\r\n  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source\r\n  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\r\n  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\r\n  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\r\n  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\r\n  *            @arg TIM_DMA_COM: TIM Commutation DMA source\r\n  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source\r\n  * @param  BurstBuffer The Buffer address.\r\n  * @param  BurstLength DMA Burst length. This parameter can be one value\r\n  *         between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,\r\n                                              uint32_t* BurstBuffer, uint32_t  BurstLength)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));\r\n  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));\r\n  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r\n  assert_param(IS_TIM_DMA_LENGTH(BurstLength));\r\n  \r\n  if((htim->State == HAL_TIM_STATE_BUSY))\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  else if((htim->State == HAL_TIM_STATE_READY))\r\n  {\r\n    if((BurstBuffer == 0 ) && (BurstLength > 0)) \r\n    {\r\n      return HAL_ERROR;                                    \r\n    }\r\n    else\r\n    {\r\n      htim->State = HAL_TIM_STATE_BUSY;\r\n    }\r\n  }\r\n  switch(BurstRequestSrc)\r\n  {\r\n    case TIM_DMA_UPDATE:\r\n    {  \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;\r\n  \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); \r\n    }\r\n    break;\r\n    case TIM_DMA_CC1:\r\n    {  \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r\n  \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);     \r\n    }\r\n    break;\r\n    case TIM_DMA_CC2:\r\n    {  \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;\r\n  \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);     \r\n    }\r\n    break;\r\n    case TIM_DMA_CC3:\r\n    {  \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;\r\n  \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);     \r\n    }\r\n    break;\r\n    case TIM_DMA_CC4:\r\n    {  \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;\r\n  \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);     \r\n    }\r\n    break;\r\n    case TIM_DMA_COM:\r\n    {  \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;\r\n  \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);     \r\n    }\r\n    break;\r\n    case TIM_DMA_TRIGGER:\r\n    {  \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;\r\n  \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);     \r\n    }\r\n    break;\r\n    default:\r\n    break;  \r\n  }\r\n   /* configure the DMA Burst Mode */\r\n   htim->Instance->DCR = BurstBaseAddress | BurstLength;  \r\n   \r\n   /* Enable the TIM DMA Request */\r\n   __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);  \r\n   \r\n   htim->State = HAL_TIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the TIM DMA Burst mode \r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  BurstRequestSrc TIM DMA Request sources to disable\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r\n  \r\n  /* Abort the DMA transfer (at least disable the DMA channel) */\r\n  switch(BurstRequestSrc)\r\n  {\r\n    case TIM_DMA_UPDATE:\r\n    {  \r\n      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);\r\n    }\r\n    break;\r\n    case TIM_DMA_CC1:\r\n    {  \r\n      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);\r\n    }\r\n    break;\r\n    case TIM_DMA_CC2:\r\n    {  \r\n      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);\r\n    }\r\n    break;\r\n    case TIM_DMA_CC3:\r\n    {  \r\n      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);\r\n    }\r\n    break;\r\n    case TIM_DMA_CC4:\r\n    {  \r\n      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);\r\n    }\r\n    break;\r\n    case TIM_DMA_COM:\r\n    {  \r\n      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);\r\n    }\r\n    break;\r\n    case TIM_DMA_TRIGGER:\r\n    {  \r\n      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);\r\n    }\r\n    break;\r\n    default:\r\n    break;\r\n  }\r\n\r\n  /* Disable the TIM Update DMA request */\r\n  __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);\r\n      \r\n  /* Return function status */\r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory \r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  BurstBaseAddress TIM Base address from when the DMA will starts the Data read.\r\n  *         This parameters can be on of the following values:\r\n  *            @arg TIM_DMABASE_CR1  \r\n  *            @arg TIM_DMABASE_CR2\r\n  *            @arg TIM_DMABASE_SMCR\r\n  *            @arg TIM_DMABASE_DIER\r\n  *            @arg TIM_DMABASE_SR\r\n  *            @arg TIM_DMABASE_EGR\r\n  *            @arg TIM_DMABASE_CCMR1\r\n  *            @arg TIM_DMABASE_CCMR2\r\n  *            @arg TIM_DMABASE_CCER\r\n  *            @arg TIM_DMABASE_CNT   \r\n  *            @arg TIM_DMABASE_PSC   \r\n  *            @arg TIM_DMABASE_ARR\r\n  *            @arg TIM_DMABASE_RCR\r\n  *            @arg TIM_DMABASE_CCR1\r\n  *            @arg TIM_DMABASE_CCR2\r\n  *            @arg TIM_DMABASE_CCR3  \r\n  *            @arg TIM_DMABASE_CCR4\r\n  *            @arg TIM_DMABASE_BDTR\r\n  *            @arg TIM_DMABASE_DCR\r\n  * @param  BurstRequestSrc TIM DMA Request sources.\r\n  *         This parameters can be on of the following values:\r\n  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source\r\n  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\r\n  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\r\n  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\r\n  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\r\n  *            @arg TIM_DMA_COM: TIM Commutation DMA source\r\n  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source\r\n  * @param  BurstBuffer The Buffer address.\r\n  * @param  BurstLength DMA Burst length. This parameter can be one value\r\n  *         between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,\r\n                                             uint32_t  *BurstBuffer, uint32_t  BurstLength)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));\r\n  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));\r\n  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r\n  assert_param(IS_TIM_DMA_LENGTH(BurstLength));\r\n  \r\n  if((htim->State == HAL_TIM_STATE_BUSY))\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  else if((htim->State == HAL_TIM_STATE_READY))\r\n  {\r\n    if((BurstBuffer == 0 ) && (BurstLength > 0)) \r\n    {\r\n      return HAL_ERROR;                                    \r\n    }\r\n    else\r\n    {\r\n      htim->State = HAL_TIM_STATE_BUSY;\r\n    }\r\n  }  \r\n  switch(BurstRequestSrc)\r\n  {\r\n    case TIM_DMA_UPDATE:\r\n    {  \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;\r\n  \r\n      /* Enable the DMA Stream */\r\n       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);     \r\n    }\r\n    break;\r\n    case TIM_DMA_CC1:\r\n    {  \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r\n  \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);      \r\n    }\r\n    break;\r\n    case TIM_DMA_CC2:\r\n    {  \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;\r\n  \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);     \r\n    }\r\n    break;\r\n    case TIM_DMA_CC3:\r\n    {  \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;\r\n  \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);      \r\n    }\r\n    break;\r\n    case TIM_DMA_CC4:\r\n    {  \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;\r\n  \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);      \r\n    }\r\n    break;\r\n    case TIM_DMA_COM:\r\n    {  \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;\r\n  \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);      \r\n    }\r\n    break;\r\n    case TIM_DMA_TRIGGER:\r\n    {  \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;\r\n  \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);      \r\n    }\r\n    break;\r\n    default:\r\n    break;  \r\n  }\r\n\r\n  /* configure the DMA Burst Mode */\r\n  htim->Instance->DCR = BurstBaseAddress | BurstLength;  \r\n  \r\n  /* Enable the TIM DMA Request */\r\n  __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);\r\n  \r\n  htim->State = HAL_TIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stop the DMA burst reading \r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  BurstRequestSrc TIM DMA Request sources to disable.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r\n  \r\n  /* Abort the DMA transfer (at least disable the DMA channel) */\r\n  switch(BurstRequestSrc)\r\n  {\r\n    case TIM_DMA_UPDATE:\r\n    {  \r\n      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);\r\n    }\r\n    break;\r\n    case TIM_DMA_CC1:\r\n    {  \r\n      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);\r\n    }\r\n    break;\r\n    case TIM_DMA_CC2:\r\n    {  \r\n      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);\r\n    }\r\n    break;\r\n    case TIM_DMA_CC3:\r\n    {  \r\n      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);\r\n    }\r\n    break;\r\n    case TIM_DMA_CC4:\r\n    {  \r\n      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);\r\n    }\r\n    break;\r\n    case TIM_DMA_COM:\r\n    {  \r\n      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);\r\n    }\r\n    break;\r\n    case TIM_DMA_TRIGGER:\r\n    {  \r\n      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);\r\n    }\r\n    break;\r\n    default:\r\n    break;  \r\n  }\r\n  \r\n  /* Disable the TIM Update DMA request */\r\n  __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);\r\n      \r\n  /* Return function status */\r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Generate a software event\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  EventSource specifies the event source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source\r\n  *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source\r\n  *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source\r\n  *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source\r\n  *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source\r\n  *            @arg TIM_EVENTSOURCE_COM: Timer COM event source  \r\n  *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source\r\n  *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source\r\n  *            @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source  \r\n  * @note   TIM6 and TIM7 can only generate an update event. \r\n  * @note   TIM_EVENTSOURCE_COM, TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are used only with TIM1 and TIM8.\r\n  * @retval HAL status\r\n  */ \r\n\r\nHAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\r\n  assert_param(IS_TIM_EVENT_SOURCE(EventSource));\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(htim);\r\n  \r\n  /* Change the TIM state */\r\n  htim->State = HAL_TIM_STATE_BUSY;\r\n  \r\n  /* Set the event sources */\r\n  htim->Instance->EGR = EventSource;\r\n  \r\n  /* Change the TIM state */\r\n  htim->State = HAL_TIM_STATE_READY;\r\n  \r\n  __HAL_UNLOCK(htim);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Configures the OCRef clear feature\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that\r\n  *         contains the OCREF clear feature and parameters for the TIM peripheral. \r\n  * @param  Channel specifies the TIM Channel.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */ \r\n__weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)\r\n{ \r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r\n  assert_param(IS_TIM_CHANNELS(Channel));\r\n  assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));\r\n   \r\n  /* Process Locked */\r\n  __HAL_LOCK(htim);\r\n  \r\n  htim->State = HAL_TIM_STATE_BUSY;\r\n  \r\n  if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)\r\n  {\r\n    assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));\r\n    assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));\r\n    assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));\r\n  \r\n    TIM_ETR_SetConfig(htim->Instance, \r\n                      sClearInputConfig->ClearInputPrescaler,\r\n                      sClearInputConfig->ClearInputPolarity,\r\n                      sClearInputConfig->ClearInputFilter);\r\n  }\r\n  \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {        \r\n      if(sClearInputConfig->ClearInputState != RESET)  \r\n      {\r\n        /* Enable the Ocref clear feature for Channel 1 */\r\n        htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;\r\n      }\r\n      else\r\n      {\r\n        /* Disable the Ocref clear feature for Channel 1 */\r\n        htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;      \r\n      }\r\n    }    \r\n    break;\r\n    case TIM_CHANNEL_2:    \r\n    { \r\n      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); \r\n      if(sClearInputConfig->ClearInputState != RESET)  \r\n      {\r\n        /* Enable the Ocref clear feature for Channel 2 */\r\n        htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;\r\n      }\r\n      else\r\n      {\r\n        /* Disable the Ocref clear feature for Channel 2 */\r\n        htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;      \r\n      }\r\n    } \r\n    break;\r\n    case TIM_CHANNEL_3:   \r\n    {  \r\n      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r\n      if(sClearInputConfig->ClearInputState != RESET)  \r\n      {\r\n        /* Enable the Ocref clear feature for Channel 3 */\r\n        htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;\r\n      }\r\n      else\r\n      {\r\n        /* Disable the Ocref clear feature for Channel 3 */\r\n        htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;      \r\n      }\r\n    } \r\n    break;\r\n    case TIM_CHANNEL_4:    \r\n    {  \r\n      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r\n      if(sClearInputConfig->ClearInputState != RESET)  \r\n      {\r\n        /* Enable the Ocref clear feature for Channel 4 */\r\n        htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;\r\n      }\r\n      else\r\n      {\r\n        /* Disable the Ocref clear feature for Channel 4 */\r\n        htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;      \r\n      }\r\n    } \r\n    break;\r\n    default:  \r\n    break;\r\n  } \r\n\r\n  htim->State = HAL_TIM_STATE_READY;\r\n  \r\n  __HAL_UNLOCK(htim);\r\n  \r\n  return HAL_OK;  \r\n}  \r\n\r\n/**\r\n  * @brief   Configures the clock source to be used\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that\r\n  *         contains the clock source information for the TIM peripheral. \r\n  * @retval HAL status\r\n  */ \r\nHAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)    \r\n{\r\n  uint32_t tmpsmcr = 0;\r\n    \r\n  /* Process Locked */\r\n  __HAL_LOCK(htim);\r\n  \r\n  htim->State = HAL_TIM_STATE_BUSY;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));\r\n  \r\n  /* Reset the SMS, TS, ECE, ETPS and ETRF bits */\r\n  tmpsmcr = htim->Instance->SMCR;\r\n  tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);\r\n  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);\r\n  htim->Instance->SMCR = tmpsmcr;\r\n  \r\n  switch (sClockSourceConfig->ClockSource)\r\n  {\r\n    case TIM_CLOCKSOURCE_INTERNAL:\r\n    { \r\n      assert_param(IS_TIM_INSTANCE(htim->Instance));      \r\n      /* Disable slave mode to clock the prescaler directly with the internal clock */\r\n      htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r\n    }\r\n    break;\r\n    \r\n    case TIM_CLOCKSOURCE_ETRMODE1:\r\n    {\r\n      assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));\r\n      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r\n      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));\r\n      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r\n      /* Configure the ETR Clock source */\r\n      TIM_ETR_SetConfig(htim->Instance, \r\n                        sClockSourceConfig->ClockPrescaler, \r\n                        sClockSourceConfig->ClockPolarity, \r\n                        sClockSourceConfig->ClockFilter);\r\n      /* Get the TIMx SMCR register value */\r\n      tmpsmcr = htim->Instance->SMCR;\r\n      /* Reset the SMS and TS Bits */\r\n      tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);\r\n      /* Select the External clock mode1 and the ETRF trigger */\r\n      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);\r\n      /* Write to TIMx SMCR */\r\n      htim->Instance->SMCR = tmpsmcr;\r\n    }\r\n    break;\r\n    \r\n    case TIM_CLOCKSOURCE_ETRMODE2:\r\n    {\r\n      assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));\r\n      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r\n      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));\r\n      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r\n      \r\n      /* Configure the ETR Clock source */\r\n      TIM_ETR_SetConfig(htim->Instance, \r\n                        sClockSourceConfig->ClockPrescaler, \r\n                        sClockSourceConfig->ClockPolarity,\r\n                        sClockSourceConfig->ClockFilter);\r\n      /* Enable the External clock mode2 */\r\n      htim->Instance->SMCR |= TIM_SMCR_ECE;\r\n    }\r\n    break;\r\n    \r\n    case TIM_CLOCKSOURCE_TI1:\r\n    {\r\n      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));\r\n  \r\n      /* Check TI1 input conditioning related parameters */\r\n      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r\n      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r\n\r\n      TIM_TI1_ConfigInputStage(htim->Instance, \r\n                        sClockSourceConfig->ClockPolarity, \r\n                        sClockSourceConfig->ClockFilter);\r\n      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);\r\n    }\r\n    break;\r\n    case TIM_CLOCKSOURCE_TI2:\r\n    {\r\n      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));\r\n      \r\n      /* Check TI1 input conditioning related parameters */\r\n      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r\n      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r\n\r\n      TIM_TI2_ConfigInputStage(htim->Instance, \r\n                        sClockSourceConfig->ClockPolarity, \r\n                        sClockSourceConfig->ClockFilter);\r\n      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);\r\n    }\r\n    break;\r\n    case TIM_CLOCKSOURCE_TI1ED:\r\n    {\r\n      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));\r\n      /* Check TI1 input conditioning related parameters */\r\n      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r\n      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r\n  \r\n      TIM_TI1_ConfigInputStage(htim->Instance, \r\n                        sClockSourceConfig->ClockPolarity,\r\n                        sClockSourceConfig->ClockFilter);\r\n      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);\r\n    }\r\n    break;\r\n    case TIM_CLOCKSOURCE_ITR0:\r\n    {\r\n      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));\r\n      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);\r\n    }\r\n    break;\r\n    case TIM_CLOCKSOURCE_ITR1:\r\n    {\r\n      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));\r\n      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);\r\n    }\r\n    break;\r\n    case TIM_CLOCKSOURCE_ITR2:\r\n    {\r\n      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));\r\n      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);\r\n    }\r\n    break;\r\n    case TIM_CLOCKSOURCE_ITR3:\r\n    {\r\n      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));\r\n      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break;    \r\n  }\r\n  htim->State = HAL_TIM_STATE_READY;\r\n  \r\n  __HAL_UNLOCK(htim);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Selects the signal connected to the TI1 input: direct from CH1_input\r\n  *         or a XOR combination between CH1_input, CH2_input & CH3_input\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  TI1_Selection Indicate whether or not channel 1 is connected to the\r\n  *         output of a XOR gate.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input\r\n  *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3\r\n  *            pins are connected to the TI1 input (XOR combination)\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)\r\n{\r\n  uint32_t tmpcr2 = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); \r\n  assert_param(IS_TIM_TI1SELECTION(TI1_Selection));\r\n\r\n  /* Get the TIMx CR2 register value */\r\n  tmpcr2 = htim->Instance->CR2;\r\n\r\n  /* Reset the TI1 selection */\r\n  tmpcr2 &= ~TIM_CR2_TI1S;\r\n\r\n  /* Set the TI1 selection */\r\n  tmpcr2 |= TI1_Selection;\r\n  \r\n  /* Write to TIMxCR2 */\r\n  htim->Instance->CR2 = tmpcr2;\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Configures the TIM in Slave mode\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that\r\n  *         contains the selected trigger (internal trigger input, filtered\r\n  *         timer input or external trigger input) and the ) and the Slave \r\n  *         mode (Disable, Reset, Gated, Trigger, External clock mode 1). \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)\r\n{\r\n  uint32_t tmpsmcr  = 0;\r\n  uint32_t tmpccmr1 = 0;\r\n  uint32_t tmpccer = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));\r\n  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));\r\n  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));\r\n   \r\n  __HAL_LOCK(htim);\r\n  \r\n  htim->State = HAL_TIM_STATE_BUSY;\r\n\r\n  /* Get the TIMx SMCR register value */\r\n  tmpsmcr = htim->Instance->SMCR;\r\n\r\n  /* Reset the Trigger Selection Bits */\r\n  tmpsmcr &= ~TIM_SMCR_TS;\r\n  /* Set the Input Trigger source */\r\n  tmpsmcr |= sSlaveConfig->InputTrigger;\r\n\r\n  /* Reset the slave mode Bits */\r\n  tmpsmcr &= ~TIM_SMCR_SMS;\r\n  /* Set the slave mode */\r\n  tmpsmcr |= sSlaveConfig->SlaveMode;\r\n\r\n  /* Write to TIMx SMCR */\r\n  htim->Instance->SMCR = tmpsmcr;\r\n  \r\n  /* Configure the trigger prescaler, filter, and polarity */\r\n  switch (sSlaveConfig->InputTrigger)\r\n  {\r\n  case TIM_TS_ETRF:\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));\r\n      assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));\r\n      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r\n      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r\n      /* Configure the ETR Trigger source */\r\n      TIM_ETR_SetConfig(htim->Instance, \r\n                        sSlaveConfig->TriggerPrescaler, \r\n                        sSlaveConfig->TriggerPolarity, \r\n                        sSlaveConfig->TriggerFilter);\r\n    }\r\n    break;\r\n    \r\n  case TIM_TS_TI1F_ED:\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r\n      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r\n      \r\n      /* Disable the Channel 1: Reset the CC1E Bit */\r\n      tmpccer = htim->Instance->CCER;\r\n      htim->Instance->CCER &= ~TIM_CCER_CC1E;\r\n      tmpccmr1 = htim->Instance->CCMR1;    \r\n      \r\n      /* Set the filter */\r\n      tmpccmr1 &= ~TIM_CCMR1_IC1F;\r\n      tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);\r\n      \r\n      /* Write to TIMx CCMR1 and CCER registers */\r\n      htim->Instance->CCMR1 = tmpccmr1;\r\n      htim->Instance->CCER = tmpccer;                               \r\n                               \r\n    }\r\n    break;\r\n    \r\n  case TIM_TS_TI1FP1:\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r\n      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r\n      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r\n\r\n      /* Configure TI1 Filter and Polarity */\r\n      TIM_TI1_ConfigInputStage(htim->Instance,\r\n                               sSlaveConfig->TriggerPolarity,\r\n                               sSlaveConfig->TriggerFilter);\r\n    }\r\n    break;\r\n    \r\n  case TIM_TS_TI2FP2:\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r\n      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r\n      \r\n      /* Configure TI2 Filter and Polarity */\r\n      TIM_TI2_ConfigInputStage(htim->Instance,\r\n                                sSlaveConfig->TriggerPolarity,\r\n                                sSlaveConfig->TriggerFilter);\r\n    }\r\n    break;\r\n    \r\n  case TIM_TS_ITR0:\r\n    {\r\n      /* Check the parameter */\r\n      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n    }\r\n    break;\r\n    \r\n  case TIM_TS_ITR1:\r\n    {\r\n      /* Check the parameter */\r\n      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n    }\r\n    break;\r\n    \r\n  case TIM_TS_ITR2:\r\n    {\r\n      /* Check the parameter */\r\n      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n    }\r\n    break;\r\n    \r\n  case TIM_TS_ITR3:\r\n    {\r\n      /* Check the parameter */\r\n      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n    }\r\n    break;\r\n       \r\n  default:\r\n    break;\r\n  }\r\n  \r\n  htim->State = HAL_TIM_STATE_READY;\r\n     \r\n  __HAL_UNLOCK(htim);  \r\n  \r\n  return HAL_OK;\r\n} \r\n\r\n/**\r\n  * @brief  Configures the TIM in Slave mode in interrupt mode\r\n  * @param  htim TIM handle.\r\n  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that\r\n  *         contains the selected trigger (internal trigger input, filtered\r\n  *         timer input or external trigger input) and the ) and the Slave \r\n  *         mode (Disable, Reset, Gated, Trigger, External clock mode 1). \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, \r\n                                                        TIM_SlaveConfigTypeDef * sSlaveConfig)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));\r\n  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));\r\n  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));\r\n  \r\n  __HAL_LOCK(htim);\r\n\r\n  htim->State = HAL_TIM_STATE_BUSY;\r\n  \r\n  TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);\r\n  \r\n  /* Enable Trigger Interrupt */\r\n  __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);\r\n  \r\n  /* Disable Trigger DMA request */\r\n  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);\r\n  \r\n  htim->State = HAL_TIM_STATE_READY;\r\n     \r\n  __HAL_UNLOCK(htim);  \r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Read the captured value from Capture Compare unit\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval Captured value\r\n  */\r\nuint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  uint32_t tmpreg = 0;\r\n  \r\n  __HAL_LOCK(htim);\r\n  \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r\n      \r\n      /* Return the capture 1 value */\r\n      tmpreg = htim->Instance->CCR1;\r\n      \r\n      break;\r\n    }\r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n      \r\n      /* Return the capture 2 value */\r\n      tmpreg = htim->Instance->CCR2;\r\n      \r\n      break;\r\n    }\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r\n      \r\n      /* Return the capture 3 value */\r\n      tmpreg = htim->Instance->CCR3;\r\n      \r\n      break;\r\n    }\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r\n      \r\n      /* Return the capture 4 value */\r\n      tmpreg = htim->Instance->CCR4;\r\n      \r\n      break;\r\n    }\r\n    \r\n    default:\r\n    break;  \r\n  }\r\n     \r\n  __HAL_UNLOCK(htim);  \r\n  return tmpreg;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions\r\n *  @brief    TIM Callbacks functions \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                        ##### TIM Callbacks functions #####\r\n  ==============================================================================  \r\n [..]  \r\n   This section provides TIM callback functions:\r\n   (+) Timer Period elapsed callback\r\n   (+) Timer Output Compare callback\r\n   (+) Timer Input capture callback\r\n   (+) Timer Trigger callback\r\n   (+) Timer Error callback\r\n   (+) Timer_RegisterCallback\r\n   (+) Timer_UnRegisterCallback\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Period elapsed callback in non blocking mode \r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file\r\n   */\r\n  \r\n}\r\n/**\r\n  * @brief  Output Compare callback in non blocking mode \r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file\r\n   */\r\n}\r\n/**\r\n  * @brief  Input Capture callback in non blocking mode \r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the __HAL_TIM_IC_CaptureCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  PWM Pulse finished callback in non blocking mode \r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Hall Trigger detection callback in non blocking mode \r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_TIM_TriggerCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Timer error callback in non blocking mode \r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_TIM_ErrorCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\n/**\r\n  * @brief  Register a User TIM callback to be used instead of the weak predefined callback\r\n  * @param htim tim handle\r\n  * @param CallbackID ID of the callback to be registered\r\n  *        This parameter can be one of the following values:\r\n  *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID\r\n  *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID\r\n  *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID\r\n  *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID\r\n  *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID\r\n  *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID\r\n  *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID\r\n  *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID\r\n  *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID\r\n  *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID\r\n  *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID\r\n  *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID\r\n  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID\r\n  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID\r\n  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID\r\n  *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID\r\n  *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID\r\n  *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID\r\n  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID\r\n  *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID\r\n  *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID\r\n  *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID\r\n  * @param pCallback pointer to the callback function\r\n  * @retval status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  if(pCallback == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  /* Process locked */\r\n  __HAL_LOCK(htim);\r\n\r\n  if(htim->State == HAL_TIM_STATE_READY)\r\n  {\r\n    switch (CallbackID)\r\n    {\r\n    case HAL_TIM_BASE_MSPINIT_CB_ID :\r\n      htim->Base_MspInitCallback         = pCallback;\r\n      break;\r\n\r\n    case HAL_TIM_BASE_MSPDEINIT_CB_ID :\r\n      htim->Base_MspDeInitCallback       = pCallback;\r\n      break;\r\n\r\n    case HAL_TIM_IC_MSPINIT_CB_ID :\r\n      htim->IC_MspInitCallback           = pCallback;\r\n      break;\r\n\r\n    case HAL_TIM_IC_MSPDEINIT_CB_ID :\r\n      htim->IC_MspDeInitCallback         = pCallback;\r\n      break;\r\n\r\n    case HAL_TIM_OC_MSPINIT_CB_ID :\r\n      htim->OC_MspInitCallback           = pCallback;\r\n      break;\r\n\r\n    case HAL_TIM_OC_MSPDEINIT_CB_ID :\r\n      htim->OC_MspDeInitCallback         = pCallback;\r\n      break;\r\n\r\n    case HAL_TIM_PWM_MSPINIT_CB_ID :\r\n      htim->PWM_MspInitCallback          = pCallback;\r\n      break;\r\n\r\n    case HAL_TIM_PWM_MSPDEINIT_CB_ID :\r\n      htim->PWM_MspDeInitCallback        = pCallback;\r\n      break;\r\n\r\n    case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :\r\n      htim->OnePulse_MspInitCallback     = pCallback;\r\n      break;\r\n\r\n    case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :\r\n      htim->OnePulse_MspDeInitCallback   = pCallback;\r\n      break;\r\n\r\n    case HAL_TIM_ENCODER_MSPINIT_CB_ID :\r\n      htim->Encoder_MspInitCallback      = pCallback;\r\n      break;\r\n\r\n    case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :\r\n      htim->Encoder_MspDeInitCallback    = pCallback;\r\n      break;\r\n\r\n    case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :\r\n      htim->HallSensor_MspInitCallback   = pCallback;\r\n      break;\r\n\r\n    case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :\r\n      htim->HallSensor_MspDeInitCallback = pCallback;\r\n      break;\r\n\r\n    case HAL_TIM_PERIOD_ELAPSED_CB_ID :\r\n      htim->PeriodElapsedCallback        = pCallback;\r\n      break;\r\n\r\n    case HAL_TIM_TRIGGER_CB_ID :\r\n      htim->TriggerCallback              = pCallback;\r\n      break;\r\n\r\n    case HAL_TIM_IC_CAPTURE_CB_ID :\r\n      htim->IC_CaptureCallback           = pCallback;\r\n      break;\r\n\r\n    case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :\r\n      htim->OC_DelayElapsedCallback      = pCallback;\r\n      break;\r\n\r\n    case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :\r\n      htim->PWM_PulseFinishedCallback    = pCallback;\r\n      break;\r\n\r\n    case HAL_TIM_ERROR_CB_ID :\r\n      htim->ErrorCallback                = pCallback;\r\n      break;\r\n\r\n    case HAL_TIM_COMMUTATION_CB_ID :\r\n      htim->CommutationCallback          = pCallback;\r\n      break;\r\n\r\n    case HAL_TIM_BREAK_CB_ID :\r\n      htim->BreakCallback                = pCallback;\r\n      break;\r\n\r\n    default :\r\n      /* Return error status */\r\n      status =  HAL_ERROR;\r\n      break;\r\n    }\r\n  }\r\n  else if(htim->State == HAL_TIM_STATE_RESET)\r\n  {\r\n    switch (CallbackID)\r\n    {\r\n    case HAL_TIM_BASE_MSPINIT_CB_ID :\r\n      htim->Base_MspInitCallback         = pCallback;\r\n      break;\r\n\r\n    case HAL_TIM_BASE_MSPDEINIT_CB_ID :\r\n      htim->Base_MspDeInitCallback       = pCallback;\r\n      break;\r\n\r\n    case HAL_TIM_IC_MSPINIT_CB_ID :\r\n      htim->IC_MspInitCallback           = pCallback;\r\n      break;\r\n\r\n    case HAL_TIM_IC_MSPDEINIT_CB_ID :\r\n      htim->IC_MspDeInitCallback         = pCallback;\r\n      break;\r\n\r\n    case HAL_TIM_OC_MSPINIT_CB_ID :\r\n      htim->OC_MspInitCallback           = pCallback;\r\n      break;\r\n\r\n    case HAL_TIM_OC_MSPDEINIT_CB_ID :\r\n      htim->OC_MspDeInitCallback         = pCallback;\r\n      break;\r\n\r\n    case HAL_TIM_PWM_MSPINIT_CB_ID :\r\n      htim->PWM_MspInitCallback          = pCallback;\r\n      break;\r\n\r\n    case HAL_TIM_PWM_MSPDEINIT_CB_ID :\r\n      htim->PWM_MspDeInitCallback        = pCallback;\r\n      break;\r\n\r\n    case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :\r\n      htim->OnePulse_MspInitCallback     = pCallback;\r\n      break;\r\n\r\n    case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :\r\n      htim->OnePulse_MspDeInitCallback   = pCallback;\r\n      break;\r\n\r\n    case HAL_TIM_ENCODER_MSPINIT_CB_ID :\r\n      htim->Encoder_MspInitCallback      = pCallback;\r\n      break;\r\n\r\n    case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :\r\n      htim->Encoder_MspDeInitCallback    = pCallback;\r\n      break;\r\n\r\n    case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :\r\n      htim->HallSensor_MspInitCallback   = pCallback;\r\n      break;\r\n\r\n    case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :\r\n      htim->HallSensor_MspDeInitCallback = pCallback;\r\n      break;\r\n\r\n    default :\r\n      /* Return error status */\r\n      status =  HAL_ERROR;\r\n      break;\r\n    }\r\n  }\r\n  else\r\n  {\r\n    /* Return error status */\r\n    status =  HAL_ERROR;\r\n  }\r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(htim);\r\n\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Unregister a TIM callback\r\n  *         TIM callback is redirected to the weak predefined callback\r\n  * @param htim tim handle\r\n  * @param CallbackID ID of the callback to be unregistered\r\n  *        This parameter can be one of the following values:\r\n  *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID\r\n  *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID\r\n  *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID\r\n  *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID\r\n  *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID\r\n  *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID\r\n  *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID\r\n  *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID\r\n  *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID\r\n  *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID\r\n  *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID\r\n  *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID\r\n  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID\r\n  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID\r\n  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID\r\n  *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID\r\n  *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID\r\n  *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID\r\n  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID\r\n  *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID\r\n  *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID\r\n  *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID\r\n  * @retval status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(htim);\r\n\r\n  if(htim->State == HAL_TIM_STATE_READY)\r\n  {\r\n    switch (CallbackID)\r\n    {\r\n    case HAL_TIM_BASE_MSPINIT_CB_ID :\r\n      htim->Base_MspInitCallback         = HAL_TIM_Base_MspInit;              /* Legacy weak Base MspInit Callback */\r\n      break;\r\n\r\n    case HAL_TIM_BASE_MSPDEINIT_CB_ID :\r\n      htim->Base_MspDeInitCallback       = HAL_TIM_Base_MspDeInit;            /* Legacy weak Base Msp DeInit Callback */\r\n      break;\r\n\r\n    case HAL_TIM_IC_MSPINIT_CB_ID :\r\n      htim->IC_MspInitCallback           = HAL_TIM_IC_MspInit;                /* Legacy weak IC Msp Init Callback */\r\n      break;\r\n\r\n    case HAL_TIM_IC_MSPDEINIT_CB_ID :\r\n      htim->IC_MspDeInitCallback         = HAL_TIM_IC_MspDeInit;              /* Legacy weak IC Msp DeInit Callback */\r\n      break;\r\n\r\n    case HAL_TIM_OC_MSPINIT_CB_ID :\r\n      htim->OC_MspInitCallback           = HAL_TIM_OC_MspInit;                /* Legacy weak OC Msp Init Callback */\r\n      break;\r\n\r\n    case HAL_TIM_OC_MSPDEINIT_CB_ID :\r\n      htim->OC_MspDeInitCallback         = HAL_TIM_OC_MspDeInit;              /* Legacy weak OC Msp DeInit Callback */\r\n      break;\r\n\r\n    case HAL_TIM_PWM_MSPINIT_CB_ID :\r\n      htim->PWM_MspInitCallback          = HAL_TIM_PWM_MspInit;               /* Legacy weak PWM Msp Init Callback */\r\n      break;\r\n\r\n    case HAL_TIM_PWM_MSPDEINIT_CB_ID :\r\n      htim->PWM_MspDeInitCallback        = HAL_TIM_PWM_MspDeInit;             /* Legacy weak PWM Msp DeInit Callback */\r\n      break;\r\n\r\n    case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :\r\n      htim->OnePulse_MspInitCallback     = HAL_TIM_OnePulse_MspInit;          /* Legacy weak One Pulse Msp Init Callback */\r\n      break;\r\n\r\n    case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :\r\n      htim->OnePulse_MspDeInitCallback   = HAL_TIM_OnePulse_MspDeInit;        /* Legacy weak One Pulse Msp DeInit Callback */\r\n      break;\r\n\r\n    case HAL_TIM_ENCODER_MSPINIT_CB_ID :\r\n      htim->Encoder_MspInitCallback      = HAL_TIM_Encoder_MspInit;           /* Legacy weak Encoder Msp Init Callback */\r\n      break;\r\n\r\n    case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :\r\n      htim->Encoder_MspDeInitCallback    = HAL_TIM_Encoder_MspDeInit;         /* Legacy weak Encoder Msp DeInit Callback */\r\n      break;\r\n\r\n    case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :\r\n      htim->HallSensor_MspInitCallback   = HAL_TIMEx_HallSensor_MspInit;      /* Legacy weak Hall Sensor Msp Init Callback */\r\n      break;\r\n\r\n    case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :\r\n      htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;    /* Legacy weak Hall Sensor Msp DeInit Callback */\r\n      break;\r\n\r\n    case HAL_TIM_PERIOD_ELAPSED_CB_ID :\r\n      htim->PeriodElapsedCallback        = HAL_TIM_PeriodElapsedCallback;     /* Legacy weak Period Elapsed Callback */\r\n      break;\r\n\r\n    case HAL_TIM_TRIGGER_CB_ID :\r\n      htim->TriggerCallback              = HAL_TIM_TriggerCallback;           /* Legacy weak Trigger Callback */\r\n      break;\r\n\r\n    case HAL_TIM_IC_CAPTURE_CB_ID :\r\n      htim->IC_CaptureCallback           = HAL_TIM_IC_CaptureCallback;        /* Legacy weak IC Capture Callback */\r\n      break;\r\n\r\n    case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :\r\n      htim->OC_DelayElapsedCallback      = HAL_TIM_OC_DelayElapsedCallback;   /* Legacy weak OC Delay Elapsed Callback */\r\n      break;\r\n\r\n    case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :\r\n      htim->PWM_PulseFinishedCallback    = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */\r\n      break;\r\n\r\n    case HAL_TIM_ERROR_CB_ID :\r\n      htim->ErrorCallback                = HAL_TIM_ErrorCallback;             /* Legacy weak Error Callback */\r\n      break;\r\n\r\n    case HAL_TIM_COMMUTATION_CB_ID :\r\n      htim->CommutationCallback          = HAL_TIMEx_CommutationCallback;     /* Legacy weak Commutation Callback */\r\n      break;\r\n\r\n    case HAL_TIM_BREAK_CB_ID :\r\n      htim->BreakCallback                = HAL_TIMEx_BreakCallback;           /* Legacy weak Break Callback */\r\n      break;\r\n\r\n    default :\r\n     /* Return error status */\r\n      status =  HAL_ERROR;\r\n      break;\r\n    }\r\n  }\r\n  else if(htim->State == HAL_TIM_STATE_RESET)\r\n  {\r\n    switch (CallbackID)\r\n    {\r\n    case HAL_TIM_BASE_MSPINIT_CB_ID :\r\n      htim->Base_MspInitCallback         = HAL_TIM_Base_MspInit;              /* Legacy weak Base MspInit Callback */\r\n      break;\r\n\r\n    case HAL_TIM_BASE_MSPDEINIT_CB_ID :\r\n      htim->Base_MspDeInitCallback       = HAL_TIM_Base_MspDeInit;            /* Legacy weak Base Msp DeInit Callback */\r\n      break;\r\n\r\n    case HAL_TIM_IC_MSPINIT_CB_ID :\r\n      htim->IC_MspInitCallback           = HAL_TIM_IC_MspInit;                /* Legacy weak IC Msp Init Callback */\r\n      break;\r\n\r\n    case HAL_TIM_IC_MSPDEINIT_CB_ID :\r\n      htim->IC_MspDeInitCallback         = HAL_TIM_IC_MspDeInit;              /* Legacy weak IC Msp DeInit Callback */\r\n      break;\r\n\r\n    case HAL_TIM_OC_MSPINIT_CB_ID :\r\n      htim->OC_MspInitCallback           = HAL_TIM_OC_MspInit;                /* Legacy weak OC Msp Init Callback */\r\n      break;\r\n\r\n    case HAL_TIM_OC_MSPDEINIT_CB_ID :\r\n      htim->OC_MspDeInitCallback         = HAL_TIM_OC_MspDeInit;              /* Legacy weak OC Msp DeInit Callback */\r\n      break;\r\n\r\n    case HAL_TIM_PWM_MSPINIT_CB_ID :\r\n      htim->PWM_MspInitCallback          = HAL_TIM_PWM_MspInit;               /* Legacy weak PWM Msp Init Callback */\r\n      break;\r\n\r\n    case HAL_TIM_PWM_MSPDEINIT_CB_ID :\r\n      htim->PWM_MspDeInitCallback        = HAL_TIM_PWM_MspDeInit;             /* Legacy weak PWM Msp DeInit Callback */\r\n      break;\r\n\r\n    case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :\r\n      htim->OnePulse_MspInitCallback     = HAL_TIM_OnePulse_MspInit;          /* Legacy weak One Pulse Msp Init Callback */\r\n      break;\r\n\r\n    case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :\r\n      htim->OnePulse_MspDeInitCallback   = HAL_TIM_OnePulse_MspDeInit;        /* Legacy weak One Pulse Msp DeInit Callback */\r\n      break;\r\n\r\n    case HAL_TIM_ENCODER_MSPINIT_CB_ID :\r\n      htim->Encoder_MspInitCallback      = HAL_TIM_Encoder_MspInit;           /* Legacy weak Encoder Msp Init Callback */\r\n      break;\r\n\r\n    case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :\r\n      htim->Encoder_MspDeInitCallback    = HAL_TIM_Encoder_MspDeInit;         /* Legacy weak Encoder Msp DeInit Callback */\r\n      break;\r\n\r\n    case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :\r\n      htim->HallSensor_MspInitCallback   = HAL_TIMEx_HallSensor_MspInit;      /* Legacy weak Hall Sensor Msp Init Callback */\r\n      break;\r\n\r\n    case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :\r\n      htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;    /* Legacy weak Hall Sensor Msp DeInit Callback */\r\n      break;\r\n\r\n    default :\r\n     /* Return error status */\r\n      status =  HAL_ERROR;\r\n      break;\r\n    }\r\n  }\r\n  else\r\n  {\r\n    /* Return error status */\r\n    status =  HAL_ERROR;\r\n  }\r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(htim);\r\n\r\n  return status;\r\n}\r\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions \r\n *  @brief   Peripheral State functions \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                        ##### Peripheral State functions #####\r\n  ==============================================================================  \r\n  [..]\r\n    This subsection permits to get in run-time the status of the peripheral \r\n    and the data flow.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Return the TIM Base state\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL state\r\n  */\r\nHAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)\r\n{\r\n  return htim->State;\r\n}\r\n\r\n/**\r\n  * @brief  Return the TIM OC state\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL state\r\n  */\r\nHAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)\r\n{\r\n  return htim->State;\r\n}\r\n\r\n/**\r\n  * @brief  Return the TIM PWM state\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL state\r\n  */\r\nHAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)\r\n{\r\n  return htim->State;\r\n}\r\n\r\n/**\r\n  * @brief  Return the TIM Input Capture state\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL state\r\n  */\r\nHAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)\r\n{\r\n  return htim->State;\r\n}\r\n\r\n/**\r\n  * @brief  Return the TIM One Pulse Mode state\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL state\r\n  */\r\nHAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)\r\n{\r\n  return htim->State;\r\n}\r\n\r\n/**\r\n  * @brief  Return the TIM Encoder Mode state\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL state\r\n  */\r\nHAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)\r\n{\r\n  return htim->State;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @brief  TIM DMA error callback \r\n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nvoid HAL_TIM_DMAError(DMA_HandleTypeDef *hdma)\r\n{\r\n  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  \r\n  htim->State= HAL_TIM_STATE_READY;\r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\n   htim->ErrorCallback(htim);\r\n#else\r\n  HAL_TIM_ErrorCallback(htim);\r\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n}\r\n\r\n/**\r\n  * @brief  TIM DMA Delay Pulse complete callback. \r\n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nvoid HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  \r\n  htim->State= HAL_TIM_STATE_READY; \r\n  \r\n  if (hdma == htim->hdma[TIM_DMA_ID_CC1])\r\n  {\r\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r\n  }\r\n  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\r\n  {\r\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r\n  }\r\n  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\r\n  {\r\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r\n  }\r\n  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\r\n  {\r\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r\n  }\r\n\r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\n  htim->PWM_PulseFinishedCallback(htim);\r\n#else\r\n  HAL_TIM_PWM_PulseFinishedCallback(htim);\r\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r\n}\r\n/**\r\n  * @brief  TIM DMA Capture complete callback. \r\n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nvoid HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n    \r\n   htim->State= HAL_TIM_STATE_READY; \r\n    \r\n  if (hdma == htim->hdma[TIM_DMA_ID_CC1])\r\n  {\r\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r\n  }\r\n  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\r\n  {\r\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r\n  }\r\n  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\r\n  {\r\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r\n  }\r\n  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\r\n  {\r\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r\n  }\r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\n  htim->IC_CaptureCallback(htim);\r\n#else\r\n  HAL_TIM_IC_CaptureCallback(htim);\r\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r\n\r\n}\r\n\r\n/**\r\n  * @brief  TIM DMA Period Elapse complete callback. \r\n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n\r\n  htim->State= HAL_TIM_STATE_READY;\r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\n  htim->PeriodElapsedCallback(htim);\r\n#else\r\n  HAL_TIM_PeriodElapsedCallback(htim);\r\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n}\r\n\r\n/**\r\n  * @brief  TIM DMA Trigger callback. \r\n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;  \r\n  \r\n  htim->State= HAL_TIM_STATE_READY; \r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\n  htim->TriggerCallback(htim);\r\n#else\r\n  HAL_TIM_TriggerCallback(htim);\r\n #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n}\r\n\r\n/**\r\n  * @brief  Time Base configuration\r\n  * @param  TIMx TIM peripheral\r\n  * @param  Structure pointer on TIM Time Base required parameters  \r\n  * @retval None\r\n  */\r\nvoid TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)\r\n{\r\n  uint32_t tmpcr1 = 0;\r\n  tmpcr1 = TIMx->CR1;\r\n  \r\n  /* Set TIM Time Base Unit parameters ---------------------------------------*/\r\n  if(IS_TIM_CC3_INSTANCE(TIMx) != RESET)   \r\n  {\r\n    /* Select the Counter Mode */\r\n    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);\r\n    tmpcr1 |= Structure->CounterMode;\r\n  }\r\n \r\n  if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)  \r\n  {\r\n    /* Set the clock division */\r\n    tmpcr1 &= ~TIM_CR1_CKD;\r\n    tmpcr1 |= (uint32_t)Structure->ClockDivision;\r\n  }\r\n\r\n  /* Set the auto-reload preload */\r\n  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);\r\n\r\n  TIMx->CR1 = tmpcr1;\r\n\r\n  /* Set the Auto-reload value */\r\n  TIMx->ARR = (uint32_t)Structure->Period ;\r\n \r\n  /* Set the Prescaler value */\r\n  TIMx->PSC = (uint32_t)Structure->Prescaler;\r\n    \r\n  if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)  \r\n  {\r\n    /* Set the Repetition Counter value */\r\n    TIMx->RCR = Structure->RepetitionCounter;\r\n  }\r\n\r\n  /* Generate an update event to reload the Prescaler \r\n     and the repetition counter(only for TIM1 and TIM8) value immediately */\r\n  TIMx->EGR = TIM_EGR_UG;\r\n}\r\n\r\n/**\r\n  * @brief  Time Output Compare 1 configuration\r\n  * @param  TIMx to select the TIM peripheral\r\n  * @param  OC_Config The output configuration structure\r\n  * @retval None\r\n  */\r\nvoid TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r\n{\r\n  uint32_t tmpccmrx = 0;\r\n  uint32_t tmpccer = 0;\r\n  uint32_t tmpcr2 = 0;  \r\n\r\n  /* Disable the Channel 1: Reset the CC1E Bit */\r\n  TIMx->CCER &= ~TIM_CCER_CC1E;\r\n  \r\n  /* Get the TIMx CCER register value */\r\n  tmpccer = TIMx->CCER;\r\n  /* Get the TIMx CR2 register value */\r\n  tmpcr2 = TIMx->CR2;\r\n  \r\n  /* Get the TIMx CCMR1 register value */\r\n  tmpccmrx = TIMx->CCMR1;\r\n    \r\n  /* Reset the Output Compare Mode Bits */\r\n  tmpccmrx &= ~TIM_CCMR1_OC1M;\r\n  tmpccmrx &= ~TIM_CCMR1_CC1S;\r\n  /* Select the Output Compare Mode */\r\n  tmpccmrx |= OC_Config->OCMode;\r\n  \r\n  /* Reset the Output Polarity level */\r\n  tmpccer &= ~TIM_CCER_CC1P;\r\n  /* Set the Output Compare Polarity */\r\n  tmpccer |= OC_Config->OCPolarity;\r\n\r\n    \r\n  if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)\r\n  {   \r\n    /* Reset the Output N Polarity level */\r\n    tmpccer &= ~TIM_CCER_CC1NP;\r\n    /* Set the Output N Polarity */\r\n    tmpccer |= OC_Config->OCNPolarity;\r\n    /* Reset the Output N State */\r\n    tmpccer &= ~TIM_CCER_CC1NE;\r\n    \r\n    /* Reset the Output Compare and Output Compare N IDLE State */\r\n    tmpcr2 &= ~TIM_CR2_OIS1;\r\n    tmpcr2 &= ~TIM_CR2_OIS1N;\r\n    /* Set the Output Idle state */\r\n    tmpcr2 |= OC_Config->OCIdleState;\r\n    /* Set the Output N Idle state */\r\n    tmpcr2 |= OC_Config->OCNIdleState;\r\n  }\r\n  /* Write to TIMx CR2 */\r\n  TIMx->CR2 = tmpcr2;\r\n  \r\n  /* Write to TIMx CCMR1 */\r\n  TIMx->CCMR1 = tmpccmrx;\r\n  \r\n  /* Set the Capture Compare Register value */\r\n  TIMx->CCR1 = OC_Config->Pulse;\r\n  \r\n  /* Write to TIMx CCER */\r\n  TIMx->CCER = tmpccer;  \r\n} \r\n\r\n/**\r\n  * @brief  Time Output Compare 2 configuration\r\n  * @param  TIMx to select the TIM peripheral\r\n  * @param  OC_Config The output configuration structure\r\n  * @retval None\r\n  */\r\nvoid TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r\n{\r\n  uint32_t tmpccmrx = 0;\r\n  uint32_t tmpccer = 0;\r\n  uint32_t tmpcr2 = 0;\r\n   \r\n  /* Disable the Channel 2: Reset the CC2E Bit */\r\n  TIMx->CCER &= ~TIM_CCER_CC2E;\r\n  \r\n  /* Get the TIMx CCER register value */  \r\n  tmpccer = TIMx->CCER;\r\n  /* Get the TIMx CR2 register value */\r\n  tmpcr2 = TIMx->CR2;\r\n  \r\n  /* Get the TIMx CCMR1 register value */\r\n  tmpccmrx = TIMx->CCMR1;\r\n    \r\n  /* Reset the Output Compare mode and Capture/Compare selection Bits */\r\n  tmpccmrx &= ~TIM_CCMR1_OC2M;\r\n  tmpccmrx &= ~TIM_CCMR1_CC2S;\r\n  \r\n  /* Select the Output Compare Mode */\r\n  tmpccmrx |= (OC_Config->OCMode << 8);\r\n  \r\n  /* Reset the Output Polarity level */\r\n  tmpccer &= ~TIM_CCER_CC2P;\r\n  /* Set the Output Compare Polarity */\r\n  tmpccer |= (OC_Config->OCPolarity << 4);\r\n    \r\n  if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)\r\n  {\r\n    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));\r\n    \r\n    /* Reset the Output N Polarity level */\r\n    tmpccer &= ~TIM_CCER_CC2NP;\r\n    /* Set the Output N Polarity */\r\n    tmpccer |= (OC_Config->OCNPolarity << 4);\r\n    /* Reset the Output N State */\r\n    tmpccer &= ~TIM_CCER_CC2NE;\r\n    \r\n    /* Reset the Output Compare and Output Compare N IDLE State */\r\n    tmpcr2 &= ~TIM_CR2_OIS2;\r\n    tmpcr2 &= ~TIM_CR2_OIS2N;\r\n    /* Set the Output Idle state */\r\n    tmpcr2 |= (OC_Config->OCIdleState << 2);\r\n    /* Set the Output N Idle state */\r\n    tmpcr2 |= (OC_Config->OCNIdleState << 2);\r\n  }\r\n  /* Write to TIMx CR2 */\r\n  TIMx->CR2 = tmpcr2;\r\n  \r\n  /* Write to TIMx CCMR1 */\r\n  TIMx->CCMR1 = tmpccmrx;\r\n  \r\n  /* Set the Capture Compare Register value */\r\n  TIMx->CCR2 = OC_Config->Pulse;\r\n  \r\n  /* Write to TIMx CCER */\r\n  TIMx->CCER = tmpccer;\r\n}\r\n\r\n/**\r\n  * @brief  Time Output Compare 3 configuration\r\n  * @param  TIMx to select the TIM peripheral\r\n  * @param  OC_Config The output configuration structure\r\n  * @retval None\r\n  */\r\nvoid TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r\n{\r\n  uint32_t tmpccmrx = 0;\r\n  uint32_t tmpccer = 0;\r\n  uint32_t tmpcr2 = 0;   \r\n\r\n  /* Disable the Channel 3: Reset the CC2E Bit */\r\n  TIMx->CCER &= ~TIM_CCER_CC3E;\r\n  \r\n  /* Get the TIMx CCER register value */\r\n  tmpccer = TIMx->CCER;\r\n  /* Get the TIMx CR2 register value */\r\n  tmpcr2 = TIMx->CR2;\r\n  \r\n  /* Get the TIMx CCMR2 register value */\r\n  tmpccmrx = TIMx->CCMR2;\r\n    \r\n  /* Reset the Output Compare mode and Capture/Compare selection Bits */\r\n  tmpccmrx &= ~TIM_CCMR2_OC3M;\r\n  tmpccmrx &= ~TIM_CCMR2_CC3S;  \r\n  /* Select the Output Compare Mode */\r\n  tmpccmrx |= OC_Config->OCMode;\r\n  \r\n  /* Reset the Output Polarity level */\r\n  tmpccer &= ~TIM_CCER_CC3P;\r\n  /* Set the Output Compare Polarity */\r\n  tmpccer |= (OC_Config->OCPolarity << 8);\r\n    \r\n  if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)\r\n  {\r\n    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));\r\n    \r\n    /* Reset the Output N Polarity level */\r\n    tmpccer &= ~TIM_CCER_CC3NP;\r\n    /* Set the Output N Polarity */\r\n    tmpccer |= (OC_Config->OCNPolarity << 8);\r\n    /* Reset the Output N State */\r\n    tmpccer &= ~TIM_CCER_CC3NE;\r\n    \r\n    /* Reset the Output Compare and Output Compare N IDLE State */\r\n    tmpcr2 &= ~TIM_CR2_OIS3;\r\n    tmpcr2 &= ~TIM_CR2_OIS3N;\r\n    /* Set the Output Idle state */\r\n    tmpcr2 |= (OC_Config->OCIdleState << 4);\r\n    /* Set the Output N Idle state */\r\n    tmpcr2 |= (OC_Config->OCNIdleState << 4);\r\n  }\r\n  /* Write to TIMx CR2 */\r\n  TIMx->CR2 = tmpcr2;\r\n  \r\n  /* Write to TIMx CCMR2 */\r\n  TIMx->CCMR2 = tmpccmrx;\r\n  \r\n  /* Set the Capture Compare Register value */\r\n  TIMx->CCR3 = OC_Config->Pulse;\r\n  \r\n  /* Write to TIMx CCER */\r\n  TIMx->CCER = tmpccer;\r\n}\r\n\r\n/**\r\n  * @brief  Time Output Compare 4 configuration\r\n  * @param  TIMx to select the TIM peripheral\r\n  * @param  OC_Config The output configuration structure\r\n  * @retval None\r\n  */\r\nvoid TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r\n{\r\n  uint32_t tmpccmrx = 0;\r\n  uint32_t tmpccer = 0;\r\n  uint32_t tmpcr2 = 0;\r\n\r\n  /* Disable the Channel 4: Reset the CC4E Bit */\r\n  TIMx->CCER &= ~TIM_CCER_CC4E;\r\n  \r\n  /* Get the TIMx CCER register value */\r\n  tmpccer = TIMx->CCER;\r\n  /* Get the TIMx CR2 register value */\r\n  tmpcr2 = TIMx->CR2;\r\n  \r\n  /* Get the TIMx CCMR2 register value */\r\n  tmpccmrx = TIMx->CCMR2;\r\n    \r\n  /* Reset the Output Compare mode and Capture/Compare selection Bits */\r\n  tmpccmrx &= ~TIM_CCMR2_OC4M;\r\n  tmpccmrx &= ~TIM_CCMR2_CC4S;\r\n  \r\n  /* Select the Output Compare Mode */\r\n  tmpccmrx |= (OC_Config->OCMode << 8);\r\n  \r\n  /* Reset the Output Polarity level */\r\n  tmpccer &= ~TIM_CCER_CC4P;\r\n  /* Set the Output Compare Polarity */\r\n  tmpccer |= (OC_Config->OCPolarity << 12);\r\n   \r\n  /*if((TIMx == TIM1) || (TIMx == TIM8))*/\r\n  if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)\r\n  {\r\n    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));\r\n    /* Reset the Output Compare IDLE State */\r\n    tmpcr2 &= ~TIM_CR2_OIS4;\r\n    /* Set the Output Idle state */\r\n    tmpcr2 |= (OC_Config->OCIdleState << 6);\r\n  }\r\n  /* Write to TIMx CR2 */\r\n  TIMx->CR2 = tmpcr2;\r\n  \r\n  /* Write to TIMx CCMR2 */  \r\n  TIMx->CCMR2 = tmpccmrx;\r\n    \r\n  /* Set the Capture Compare Register value */\r\n  TIMx->CCR4 = OC_Config->Pulse;\r\n  \r\n  /* Write to TIMx CCER */\r\n  TIMx->CCER = tmpccer;\r\n}\r\n\r\n/**\r\n  * @brief  Time Output Compare 4 configuration\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  sSlaveConfig The slave configuration structure\r\n  * @retval None\r\n  */\r\nstatic void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,\r\n                              TIM_SlaveConfigTypeDef * sSlaveConfig)\r\n{\r\n  uint32_t tmpsmcr = 0;\r\n  uint32_t tmpccmr1 = 0;\r\n  uint32_t tmpccer = 0;\r\n\r\n /* Get the TIMx SMCR register value */\r\n  tmpsmcr = htim->Instance->SMCR;\r\n\r\n  /* Reset the Trigger Selection Bits */\r\n  tmpsmcr &= ~TIM_SMCR_TS;\r\n  /* Set the Input Trigger source */\r\n  tmpsmcr |= sSlaveConfig->InputTrigger;\r\n\r\n  /* Reset the slave mode Bits */\r\n  tmpsmcr &= ~TIM_SMCR_SMS;\r\n  /* Set the slave mode */\r\n  tmpsmcr |= sSlaveConfig->SlaveMode;\r\n\r\n  /* Write to TIMx SMCR */\r\n  htim->Instance->SMCR = tmpsmcr;\r\n \r\n  /* Configure the trigger prescaler, filter, and polarity */\r\n  switch (sSlaveConfig->InputTrigger)\r\n  {\r\n  case TIM_TS_ETRF:\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));\r\n      assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));\r\n      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r\n      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r\n      /* Configure the ETR Trigger source */\r\n      TIM_ETR_SetConfig(htim->Instance, \r\n                        sSlaveConfig->TriggerPrescaler, \r\n                        sSlaveConfig->TriggerPolarity, \r\n                        sSlaveConfig->TriggerFilter);\r\n    }\r\n    break;\r\n    \r\n  case TIM_TS_TI1F_ED:\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r\n      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r\n      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r\n  \r\n      /* Disable the Channel 1: Reset the CC1E Bit */\r\n      tmpccer = htim->Instance->CCER;\r\n      htim->Instance->CCER &= ~TIM_CCER_CC1E;\r\n      tmpccmr1 = htim->Instance->CCMR1;    \r\n      \r\n      /* Set the filter */\r\n      tmpccmr1 &= ~TIM_CCMR1_IC1F;\r\n      tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);\r\n      \r\n      /* Write to TIMx CCMR1 and CCER registers */\r\n      htim->Instance->CCMR1 = tmpccmr1;\r\n      htim->Instance->CCER = tmpccer;                               \r\n                               \r\n    }\r\n    break;\r\n    \r\n  case TIM_TS_TI1FP1:\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r\n      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r\n      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r\n\r\n      /* Configure TI1 Filter and Polarity */\r\n      TIM_TI1_ConfigInputStage(htim->Instance,\r\n                               sSlaveConfig->TriggerPolarity,\r\n                               sSlaveConfig->TriggerFilter);\r\n    }\r\n    break;\r\n    \r\n  case TIM_TS_TI2FP2:\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r\n      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r\n  \r\n      /* Configure TI2 Filter and Polarity */\r\n      TIM_TI2_ConfigInputStage(htim->Instance,\r\n                                sSlaveConfig->TriggerPolarity,\r\n                                sSlaveConfig->TriggerFilter);\r\n    }\r\n    break;\r\n    \r\n  case TIM_TS_ITR0:\r\n    {\r\n      /* Check the parameter */\r\n      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n    }\r\n    break;\r\n    \r\n  case TIM_TS_ITR1:\r\n    {\r\n      /* Check the parameter */\r\n      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n    }\r\n    break;\r\n    \r\n  case TIM_TS_ITR2:\r\n    {\r\n      /* Check the parameter */\r\n      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n    }\r\n    break;\r\n    \r\n  case TIM_TS_ITR3:\r\n    {\r\n      /* Check the parameter */\r\n      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n    }\r\n    break;\r\n       \r\n  default:\r\n    break;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Configure the TI1 as Input.\r\n  * @param  TIMx to select the TIM peripheral.\r\n  * @param  TIM_ICPolarity  The Input Polarity.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_ICPolarity_Rising\r\n  *            @arg TIM_ICPolarity_Falling\r\n  *            @arg TIM_ICPolarity_BothEdge  \r\n  * @param  TIM_ICSelection specifies the input to be used.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.\r\n  *            @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.\r\n  *            @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.\r\n  * @param  TIM_ICFilter Specifies the Input Capture Filter.\r\n  *          This parameter must be a value between 0x00 and 0x0F.\r\n  * @retval None  \r\n  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 \r\n  *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be \r\n  *        protected against un-initialized filter and polarity values.  \r\n  */\r\nvoid TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r\n                       uint32_t TIM_ICFilter)\r\n{\r\n  uint32_t tmpccmr1 = 0;\r\n  uint32_t tmpccer = 0;\r\n\r\n  /* Disable the Channel 1: Reset the CC1E Bit */\r\n  TIMx->CCER &= ~TIM_CCER_CC1E;\r\n  tmpccmr1 = TIMx->CCMR1;\r\n  tmpccer = TIMx->CCER;\r\n\r\n  /* Select the Input */\r\n  if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)\r\n  {\r\n    tmpccmr1 &= ~TIM_CCMR1_CC1S;\r\n    tmpccmr1 |= TIM_ICSelection;\r\n  } \r\n  else\r\n  {\r\n    tmpccmr1 |= TIM_CCMR1_CC1S_0;\r\n  }\r\n  \r\n  /* Set the filter */\r\n  tmpccmr1 &= ~TIM_CCMR1_IC1F;\r\n  tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);\r\n\r\n  /* Select the Polarity and set the CC1E Bit */\r\n  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);\r\n  tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));\r\n\r\n  /* Write to TIMx CCMR1 and CCER registers */\r\n  TIMx->CCMR1 = tmpccmr1;\r\n  TIMx->CCER = tmpccer;\r\n}\r\n\r\n/**\r\n  * @brief  Configure the Polarity and Filter for TI1.\r\n  * @param  TIMx to select the TIM peripheral.\r\n  * @param  TIM_ICPolarity  The Input Polarity.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_ICPolarity_Rising\r\n  *            @arg TIM_ICPolarity_Falling\r\n  *            @arg TIM_ICPolarity_BothEdge\r\n  * @param  TIM_ICFilter Specifies the Input Capture Filter.\r\n  *          This parameter must be a value between 0x00 and 0x0F.\r\n  * @retval None\r\n  */\r\nstatic void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)\r\n{\r\n  uint32_t tmpccmr1 = 0;\r\n  uint32_t tmpccer = 0;\r\n  \r\n  /* Disable the Channel 1: Reset the CC1E Bit */\r\n  tmpccer = TIMx->CCER;\r\n  TIMx->CCER &= ~TIM_CCER_CC1E;\r\n  tmpccmr1 = TIMx->CCMR1;    \r\n  \r\n  /* Set the filter */\r\n  tmpccmr1 &= ~TIM_CCMR1_IC1F;\r\n  tmpccmr1 |= (TIM_ICFilter << 4);\r\n  \r\n  /* Select the Polarity and set the CC1E Bit */\r\n  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);\r\n  tmpccer |= TIM_ICPolarity;\r\n  \r\n  /* Write to TIMx CCMR1 and CCER registers */\r\n  TIMx->CCMR1 = tmpccmr1;\r\n  TIMx->CCER = tmpccer;\r\n}\r\n\r\n/**\r\n  * @brief  Configure the TI2 as Input.\r\n  * @param  TIMx to select the TIM peripheral\r\n  * @param  TIM_ICPolarity  The Input Polarity.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_ICPolarity_Rising\r\n  *            @arg TIM_ICPolarity_Falling\r\n  *            @arg TIM_ICPolarity_BothEdge   \r\n  * @param  TIM_ICSelection specifies the input to be used.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.\r\n  *            @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.\r\n  *            @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.\r\n  * @param  TIM_ICFilter Specifies the Input Capture Filter.\r\n  *          This parameter must be a value between 0x00 and 0x0F.\r\n  * @retval None\r\n  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 \r\n  *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be \r\n  *        protected against un-initialized filter and polarity values.  \r\n  */\r\nstatic void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r\n                       uint32_t TIM_ICFilter)\r\n{\r\n  uint32_t tmpccmr1 = 0;\r\n  uint32_t tmpccer = 0;\r\n\r\n  /* Disable the Channel 2: Reset the CC2E Bit */\r\n  TIMx->CCER &= ~TIM_CCER_CC2E;\r\n  tmpccmr1 = TIMx->CCMR1;\r\n  tmpccer = TIMx->CCER;\r\n\r\n  /* Select the Input */\r\n  tmpccmr1 &= ~TIM_CCMR1_CC2S;\r\n  tmpccmr1 |= (TIM_ICSelection << 8);\r\n\r\n  /* Set the filter */\r\n  tmpccmr1 &= ~TIM_CCMR1_IC2F;\r\n  tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);\r\n\r\n  /* Select the Polarity and set the CC2E Bit */\r\n  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);\r\n  tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));\r\n\r\n  /* Write to TIMx CCMR1 and CCER registers */\r\n  TIMx->CCMR1 = tmpccmr1 ;\r\n  TIMx->CCER = tmpccer;\r\n}\r\n\r\n/**\r\n  * @brief  Configure the Polarity and Filter for TI2.\r\n  * @param  TIMx to select the TIM peripheral.\r\n  * @param  TIM_ICPolarity  The Input Polarity.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_ICPolarity_Rising\r\n  *            @arg TIM_ICPolarity_Falling\r\n  *            @arg TIM_ICPolarity_BothEdge\r\n  * @param  TIM_ICFilter Specifies the Input Capture Filter.\r\n  *          This parameter must be a value between 0x00 and 0x0F.\r\n  * @retval None\r\n  */\r\nstatic void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)\r\n{\r\nuint32_t tmpccmr1 = 0;\r\n  uint32_t tmpccer = 0;\r\n  \r\n  /* Disable the Channel 2: Reset the CC2E Bit */\r\n  TIMx->CCER &= ~TIM_CCER_CC2E;\r\n  tmpccmr1 = TIMx->CCMR1;\r\n  tmpccer = TIMx->CCER;\r\n  \r\n  /* Set the filter */\r\n  tmpccmr1 &= ~TIM_CCMR1_IC2F;\r\n  tmpccmr1 |= (TIM_ICFilter << 12);\r\n\r\n  /* Select the Polarity and set the CC2E Bit */\r\n  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);\r\n  tmpccer |= (TIM_ICPolarity << 4);\r\n\r\n  /* Write to TIMx CCMR1 and CCER registers */\r\n  TIMx->CCMR1 = tmpccmr1 ;\r\n  TIMx->CCER = tmpccer;\r\n}\r\n\r\n/**\r\n  * @brief  Configure the TI3 as Input.\r\n  * @param  TIMx to select the TIM peripheral\r\n  * @param  TIM_ICPolarity  The Input Polarity.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_ICPolarity_Rising\r\n  *            @arg TIM_ICPolarity_Falling\r\n  *            @arg TIM_ICPolarity_BothEdge         \r\n  * @param  TIM_ICSelection specifies the input to be used.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.\r\n  *            @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.\r\n  *            @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.\r\n  * @param  TIM_ICFilter Specifies the Input Capture Filter.\r\n  *          This parameter must be a value between 0x00 and 0x0F.\r\n  * @retval None\r\n  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 \r\n  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be \r\n  *        protected against un-initialized filter and polarity values.  \r\n  */\r\nstatic void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r\n                       uint32_t TIM_ICFilter)\r\n{\r\n  uint32_t tmpccmr2 = 0;\r\n  uint32_t tmpccer = 0;\r\n\r\n  /* Disable the Channel 3: Reset the CC3E Bit */\r\n  TIMx->CCER &= ~TIM_CCER_CC3E;\r\n  tmpccmr2 = TIMx->CCMR2;\r\n  tmpccer = TIMx->CCER;\r\n\r\n  /* Select the Input */\r\n  tmpccmr2 &= ~TIM_CCMR2_CC3S;\r\n  tmpccmr2 |= TIM_ICSelection;\r\n\r\n  /* Set the filter */\r\n  tmpccmr2 &= ~TIM_CCMR2_IC3F;\r\n  tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);\r\n\r\n  /* Select the Polarity and set the CC3E Bit */\r\n  tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);\r\n  tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));\r\n\r\n  /* Write to TIMx CCMR2 and CCER registers */\r\n  TIMx->CCMR2 = tmpccmr2;\r\n  TIMx->CCER = tmpccer;\r\n}\r\n\r\n/**\r\n  * @brief  Configure the TI4 as Input.\r\n  * @param  TIMx to select the TIM peripheral\r\n  * @param  TIM_ICPolarity  The Input Polarity.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_ICPolarity_Rising\r\n  *            @arg TIM_ICPolarity_Falling\r\n  *            @arg TIM_ICPolarity_BothEdge     \r\n  * @param  TIM_ICSelection specifies the input to be used.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.\r\n  *            @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.\r\n  *            @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.\r\n  * @param  TIM_ICFilter Specifies the Input Capture Filter.\r\n  *          This parameter must be a value between 0x00 and 0x0F.\r\n  * @retval None\r\n  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 \r\n  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be \r\n  *        protected against un-initialized filter and polarity values.  \r\n  */\r\nstatic void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r\n                       uint32_t TIM_ICFilter)\r\n{\r\n  uint32_t tmpccmr2 = 0;\r\n  uint32_t tmpccer = 0;\r\n\r\n  /* Disable the Channel 4: Reset the CC4E Bit */\r\n  TIMx->CCER &= ~TIM_CCER_CC4E;\r\n  tmpccmr2 = TIMx->CCMR2;\r\n  tmpccer = TIMx->CCER;\r\n\r\n  /* Select the Input */\r\n  tmpccmr2 &= ~TIM_CCMR2_CC4S;\r\n  tmpccmr2 |= (TIM_ICSelection << 8);\r\n\r\n  /* Set the filter */\r\n  tmpccmr2 &= ~TIM_CCMR2_IC4F;\r\n  tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);\r\n\r\n  /* Select the Polarity and set the CC4E Bit */\r\n  tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);\r\n  tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));\r\n\r\n  /* Write to TIMx CCMR2 and CCER registers */\r\n  TIMx->CCMR2 = tmpccmr2;\r\n  TIMx->CCER = tmpccer ;\r\n}\r\n\r\n/**\r\n  * @brief  Selects the Input Trigger source\r\n  * @param  TIMx to select the TIM peripheral\r\n  * @param  TIM_ITRx The Input Trigger source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_TS_ITR0: Internal Trigger 0\r\n  *            @arg TIM_TS_ITR1: Internal Trigger 1\r\n  *            @arg TIM_TS_ITR2: Internal Trigger 2\r\n  *            @arg TIM_TS_ITR3: Internal Trigger 3\r\n  *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector\r\n  *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1\r\n  *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2\r\n  *            @arg TIM_TS_ETRF: External Trigger input\r\n  * @retval None\r\n  */\r\nstatic void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx)\r\n{\r\n  uint32_t tmpsmcr = 0;\r\n  \r\n   /* Get the TIMx SMCR register value */\r\n   tmpsmcr = TIMx->SMCR;\r\n   /* Reset the TS Bits */\r\n   tmpsmcr &= ~TIM_SMCR_TS;\r\n   /* Set the Input Trigger source and the slave mode*/\r\n   tmpsmcr |= TIM_ITRx | TIM_SLAVEMODE_EXTERNAL1;\r\n   /* Write to TIMx SMCR */\r\n   TIMx->SMCR = tmpsmcr;\r\n}\r\n\r\n/**\r\n  * @brief  Configures the TIMx External Trigger (ETR).\r\n  * @param  TIMx to select the TIM peripheral\r\n  * @param  TIM_ExtTRGPrescaler The external Trigger Prescaler.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.\r\n  *            @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r\n  *            @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r\n  *            @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r\n  * @param  TIM_ExtTRGPolarity The external Trigger Polarity.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r\n  *            @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r\n  * @param  ExtTRGFilter External Trigger Filter.\r\n  *          This parameter must be a value between 0x00 and 0x0F\r\n  * @retval None\r\n  */\r\nvoid TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,\r\n                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)\r\n{\r\n  uint32_t tmpsmcr = 0;\r\n\r\n  tmpsmcr = TIMx->SMCR;\r\n\r\n  /* Reset the ETR Bits */\r\n  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);\r\n\r\n  /* Set the Prescaler, the Filter value and the Polarity */\r\n  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));\r\n\r\n  /* Write to TIMx SMCR */\r\n  TIMx->SMCR = tmpsmcr;\r\n} \r\n\r\n/**\r\n  * @brief  Enables or disables the TIM Capture Compare Channel x.\r\n  * @param  TIMx to select the TIM peripheral\r\n  * @param  Channel specifies the TIM Channel\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_Channel_1: TIM Channel 1\r\n  *            @arg TIM_Channel_2: TIM Channel 2\r\n  *            @arg TIM_Channel_3: TIM Channel 3\r\n  *            @arg TIM_Channel_4: TIM Channel 4\r\n  * @param  ChannelState specifies the TIM Channel CCxE bit new state.\r\n  *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable. \r\n  * @retval None\r\n  */\r\nvoid TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)\r\n{\r\n  uint32_t tmp = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CC1_INSTANCE(TIMx)); \r\n  assert_param(IS_TIM_CHANNELS(Channel));\r\n\r\n  tmp = TIM_CCER_CC1E << Channel;\r\n\r\n  /* Reset the CCxE Bit */\r\n  TIMx->CCER &= ~tmp;\r\n\r\n  /* Set or reset the CCxE Bit */ \r\n  TIMx->CCER |= (uint32_t)(ChannelState << Channel);\r\n}\r\n\r\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\r\n/**\r\n  * @brief  Reset interrupt callbacks to the legacy week callbacks.\r\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\nvoid TIM_ResetCallback(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Reset the TIM callback to the legacy weak callbacks */\r\n  htim->PeriodElapsedCallback     = HAL_TIM_PeriodElapsedCallback;     /* Legacy weak PeriodElapsedCallback     */\r\n  htim->TriggerCallback           = HAL_TIM_TriggerCallback;           /* Legacy weak TriggerCallback           */\r\n  htim->IC_CaptureCallback        = HAL_TIM_IC_CaptureCallback;        /* Legacy weak IC_CaptureCallback        */\r\n  htim->OC_DelayElapsedCallback   = HAL_TIM_OC_DelayElapsedCallback;   /* Legacy weak OC_DelayElapsedCallback   */\r\n  htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */\r\n  htim->ErrorCallback             = HAL_TIM_ErrorCallback;             /* Legacy weak ErrorCallback             */\r\n  htim->CommutationCallback       = HAL_TIMEx_CommutationCallback;     /* Legacy weak CommutationCallback       */\r\n  htim->BreakCallback             = HAL_TIMEx_BreakCallback;           /* Legacy weak BreakCallback             */\r\n}\r\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_TIM_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_uart.c\r\n  * @author  MCD Application Team\r\n  * @brief   UART HAL module driver.\r\n  *          This file provides firmware functions to manage the following\r\n  *          functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + IO operation functions\r\n  *           + Peripheral Control functions\r\n  *           + Peripheral State and Errors functions\r\n  *\r\n  @verbatim\r\n  ==============================================================================\r\n                        ##### How to use this driver #####\r\n  ==============================================================================\r\n  [..]\r\n    The UART HAL driver can be used as follows:\r\n\r\n    (#) Declare a UART_HandleTypeDef handle structure.\r\n\r\n    (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:\r\n        (##) Enable the USARTx interface clock.\r\n        (##) UART pins configuration:\r\n            (+++) Enable the clock for the UART GPIOs.\r\n            (+++) Configure these UART pins as alternate function pull-up.\r\n        (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()\r\n             and HAL_UART_Receive_IT() APIs):\r\n            (+++) Configure the USARTx interrupt priority.\r\n            (+++) Enable the NVIC USART IRQ handle.\r\n        (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()\r\n             and HAL_UART_Receive_DMA() APIs):\r\n            (+++) Declare a DMA handle structure for the Tx/Rx stream.\r\n            (+++) Enable the DMAx interface clock.\r\n            (+++) Configure the declared DMA handle structure with the required\r\n                  Tx/Rx parameters.\r\n            (+++) Configure the DMA Tx/Rx Stream.\r\n            (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.\r\n            (+++) Configure the priority and enable the NVIC for the transfer complete\r\n                  interrupt on the DMA Tx/Rx Stream.\r\n\r\n    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware\r\n        flow control and Mode(Receiver/Transmitter) in the Init structure.\r\n\r\n    (#) For the UART asynchronous mode, initialize the UART registers by calling\r\n        the HAL_UART_Init() API.\r\n\r\n    (#) For the UART Half duplex mode, initialize the UART registers by calling\r\n        the HAL_HalfDuplex_Init() API.\r\n\r\n    (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API.\r\n\r\n    (#) For the Multi-Processor mode, initialize the UART registers by calling\r\n        the HAL_MultiProcessor_Init() API.\r\n\r\n     [..]\r\n       (@) The specific UART interrupts (Transmission complete interrupt,\r\n            RXNE interrupt and Error Interrupts) will be managed using the macros\r\n            __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit\r\n            and receive process.\r\n\r\n     [..]\r\n       (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the\r\n            low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized\r\n            HAL_UART_MspInit() API.\r\n\r\n     [..]\r\n        Three operation modes are available within this driver :\r\n\r\n     *** Polling mode IO operation ***\r\n     =================================\r\n     [..]\r\n       (+) Send an amount of data in blocking mode using HAL_UART_Transmit()\r\n       (+) Receive an amount of data in blocking mode using HAL_UART_Receive()\r\n\r\n     *** Interrupt mode IO operation ***\r\n     ===================================\r\n     [..]\r\n       (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT()\r\n       (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can\r\n            add his own code by customization of function pointer HAL_UART_TxCpltCallback\r\n       (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT()\r\n       (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can\r\n            add his own code by customization of function pointer HAL_UART_RxCpltCallback\r\n       (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can\r\n            add his own code by customization of function pointer HAL_UART_ErrorCallback\r\n\r\n     *** DMA mode IO operation ***\r\n     ==============================\r\n     [..]\r\n       (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA()\r\n       (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can\r\n            add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback\r\n       (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can\r\n            add his own code by customization of function pointer HAL_UART_TxCpltCallback\r\n       (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA()\r\n       (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can\r\n            add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback\r\n       (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can\r\n            add his own code by customization of function pointer HAL_UART_RxCpltCallback\r\n       (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can\r\n            add his own code by customization of function pointer HAL_UART_ErrorCallback\r\n       (+) Pause the DMA Transfer using HAL_UART_DMAPause()\r\n       (+) Resume the DMA Transfer using HAL_UART_DMAResume()\r\n       (+) Stop the DMA Transfer using HAL_UART_DMAStop()\r\n\r\n     *** UART HAL driver macros list ***\r\n     =============================================\r\n     [..]\r\n       Below the list of most used macros in UART HAL driver.\r\n\r\n      (+) __HAL_UART_ENABLE: Enable the UART peripheral\r\n      (+) __HAL_UART_DISABLE: Disable the UART peripheral\r\n      (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not\r\n      (+) __HAL_UART_CLEAR_IT : Clears the specified UART ISR flag\r\n      (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt\r\n      (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt\r\n      (+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not\r\n\r\n     [..]\r\n       (@) You can refer to the UART HAL driver header file for more useful macros\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup UART UART\r\n  * @brief HAL UART module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_UART_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @defgroup UART_Private_Constants UART Private Constants\r\n  * @{\r\n  */\r\n#define UART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \\\r\n                                     USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8))\r\n/**\r\n  * @}\r\n  */\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/** @addtogroup UART_Private_Functions\r\n  * @{\r\n  */\r\nstatic void UART_EndTxTransfer(UART_HandleTypeDef *huart);\r\nstatic void UART_EndRxTransfer(UART_HandleTypeDef *huart);\r\nstatic void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);\r\nstatic void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);\r\nstatic void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);\r\nstatic void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);\r\nstatic void UART_DMAError(DMA_HandleTypeDef *hdma);\r\nstatic void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);\r\nstatic HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);\r\nstatic HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);\r\nstatic HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @defgroup UART_Exported_Functions UART Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions\r\n  *  @brief    Initialization and Configuration functions\r\n  *\r\n@verbatim\r\n===============================================================================\r\n            ##### Initialization and Configuration functions #####\r\n ===============================================================================\r\n    [..]\r\n    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy\r\n    in asynchronous mode.\r\n      (+) For the asynchronous mode only these parameters can be configured:\r\n        (++) Baud Rate\r\n        (++) Word Length\r\n        (++) Stop Bit\r\n        (++) Parity: If the parity is enabled, then the MSB bit of the data written\r\n             in the data register is transmitted but is changed by the parity bit.\r\n             Depending on the frame length defined by the M bit (8-bits or 9-bits),\r\n             please refer to Reference manual for possible UART frame formats.\r\n        (++) Hardware flow control\r\n        (++) Receiver/transmitter modes\r\n        (++) Over Sampling Method\r\n    [..]\r\n    The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs\r\n    follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor\r\n    configuration procedures (details for the procedures are available in reference manual (RM0329)).\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief Initializes the UART mode according to the specified\r\n  *         parameters in the UART_InitTypeDef and creates the associated handle .\r\n  * @param huart uart handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)\r\n{\r\n  /* Check the UART handle allocation */\r\n  if(huart == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));\r\n  }\r\n  else\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_UART_INSTANCE(huart->Instance));\r\n  }\r\n\r\n  if(huart->gState == HAL_UART_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    huart->Lock = HAL_UNLOCKED;\r\n\r\n    /* Init the low level hardware : GPIO, CLOCK */\r\n    HAL_UART_MspInit(huart);\r\n  }\r\n\r\n  huart->gState = HAL_UART_STATE_BUSY;\r\n\r\n  /* Disable the Peripheral */\r\n  __HAL_UART_DISABLE(huart);\r\n\r\n  /* Set the UART Communication parameters */\r\n  if (UART_SetConfig(huart) == HAL_ERROR)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)\r\n  {\r\n    UART_AdvFeatureConfig(huart);\r\n  }\r\n\r\n  /* In asynchronous mode, the following bits must be kept cleared:\r\n  - LINEN and CLKEN bits in the USART_CR2 register,\r\n  - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/\r\n  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\r\n  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));\r\n\r\n  /* Enable the Peripheral */\r\n  __HAL_UART_ENABLE(huart);\r\n\r\n  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */\r\n  return (UART_CheckIdleState(huart));\r\n}\r\n\r\n/**\r\n  * @brief Initializes the half-duplex mode according to the specified\r\n  *         parameters in the UART_InitTypeDef and creates the associated handle .\r\n  * @param huart UART handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)\r\n{\r\n  /* Check the UART handle allocation */\r\n  if(huart == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  if(huart->gState == HAL_UART_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    huart->Lock = HAL_UNLOCKED;\r\n\r\n    /* Init the low level hardware : GPIO, CLOCK */\r\n    HAL_UART_MspInit(huart);\r\n  }\r\n\r\n  huart->gState = HAL_UART_STATE_BUSY;\r\n\r\n  /* Disable the Peripheral */\r\n  __HAL_UART_DISABLE(huart);\r\n\r\n  /* Set the UART Communication parameters */\r\n  if (UART_SetConfig(huart) == HAL_ERROR)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)\r\n  {\r\n    UART_AdvFeatureConfig(huart);\r\n  }\r\n\r\n  /* In half-duplex mode, the following bits must be kept cleared:\r\n  - LINEN and CLKEN bits in the USART_CR2 register,\r\n  - SCEN and IREN bits in the USART_CR3 register.*/\r\n  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\r\n  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));\r\n\r\n  /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */\r\n  SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);\r\n\r\n  /* Enable the Peripheral */\r\n  __HAL_UART_ENABLE(huart);\r\n\r\n  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */\r\n  return (UART_CheckIdleState(huart));\r\n}\r\n\r\n\r\n/**\r\n  * @brief Initialize the LIN mode according to the specified\r\n  *        parameters in the UART_InitTypeDef and creates the associated handle .\r\n  * @param huart UART handle.\r\n  * @param BreakDetectLength specifies the LIN break detection length.\r\n  *        This parameter can be one of the following values:\r\n  *          @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection\r\n  *          @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)\r\n{\r\n  /* Check the UART handle allocation */\r\n  if(huart == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_UART_INSTANCE(huart->Instance));\r\n  assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));\r\n  assert_param(IS_LIN_WORD_LENGTH(huart->Init.WordLength));\r\n\r\n  if(huart->gState == HAL_UART_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    huart->Lock = HAL_UNLOCKED;\r\n\r\n    /* Init the low level hardware : GPIO, CLOCK */\r\n    HAL_UART_MspInit(huart);\r\n  }\r\n\r\n  huart->gState = HAL_UART_STATE_BUSY;\r\n\r\n  /* Disable the Peripheral */\r\n  __HAL_UART_DISABLE(huart);\r\n\r\n  /* Set the UART Communication parameters */\r\n  if (UART_SetConfig(huart) == HAL_ERROR)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)\r\n  {\r\n    UART_AdvFeatureConfig(huart);\r\n  }\r\n\r\n  /* In LIN mode, the following bits must be kept cleared:\r\n  - LINEN and CLKEN bits in the USART_CR2 register,\r\n  - SCEN and IREN bits in the USART_CR3 register.*/\r\n  CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);\r\n  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));\r\n\r\n  /* Enable the LIN mode by setting the LINEN bit in the CR2 register */\r\n  SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);\r\n\r\n  /* Set the USART LIN Break detection length. */\r\n  MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);\r\n\r\n  /* Enable the Peripheral */\r\n  __HAL_UART_ENABLE(huart);\r\n\r\n  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */\r\n  return (UART_CheckIdleState(huart));\r\n}\r\n\r\n\r\n/**\r\n  * @brief Initialize the multiprocessor mode according to the specified\r\n  *        parameters in the UART_InitTypeDef and initialize the associated handle.\r\n  * @param huart UART handle.\r\n  * @param Address UART node address (4-, 6-, 7- or 8-bit long).\r\n  * @param WakeUpMethod specifies the UART wakeup method.\r\n  *        This parameter can be one of the following values:\r\n  *          @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection\r\n  *          @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark\r\n  * @note  If the user resorts to idle line detection wake up, the Address parameter\r\n  *        is useless and ignored by the initialization function.\r\n  * @note  If the user resorts to address mark wake up, the address length detection\r\n  *        is configured by default to 4 bits only. For the UART to be able to\r\n  *        manage 6-, 7- or 8-bit long addresses detection\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)\r\n{\r\n  /* Check the UART handle allocation */\r\n  if(huart == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the wake up method parameter */\r\n  assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));\r\n\r\n  if(huart->gState == HAL_UART_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    huart->Lock = HAL_UNLOCKED;\r\n\r\n    /* Init the low level hardware : GPIO, CLOCK */\r\n    HAL_UART_MspInit(huart);\r\n  }\r\n\r\n  huart->gState = HAL_UART_STATE_BUSY;\r\n\r\n  /* Disable the Peripheral */\r\n  __HAL_UART_DISABLE(huart);\r\n\r\n  /* Set the UART Communication parameters */\r\n  if (UART_SetConfig(huart) == HAL_ERROR)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)\r\n  {\r\n    UART_AdvFeatureConfig(huart);\r\n  }\r\n\r\n  /* In multiprocessor mode, the following bits must be kept cleared:\r\n  - LINEN and CLKEN bits in the USART_CR2 register,\r\n  - SCEN, HDSEL and IREN  bits in the USART_CR3 register. */\r\n  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\r\n  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));\r\n\r\n  if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)\r\n  {\r\n    /* If address mark wake up method is chosen, set the USART address node */\r\n    MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));\r\n  }\r\n\r\n  /* Set the wake up method by setting the WAKE bit in the CR1 register */\r\n  MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);\r\n\r\n  /* Enable the Peripheral */\r\n  __HAL_UART_ENABLE(huart);\r\n\r\n  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */\r\n  return (UART_CheckIdleState(huart));\r\n}\r\n\r\n\r\n/**\r\n  * @brief Initialize the RS485 Driver enable feature according to the specified\r\n  *         parameters in the UART_InitTypeDef and creates the associated handle.\r\n  * @param huart UART handle.\r\n  * @param Polarity select the driver enable polarity.\r\n  *        This parameter can be one of the following values:\r\n  *          @arg @ref UART_DE_POLARITY_HIGH DE signal is active high\r\n  *          @arg @ref UART_DE_POLARITY_LOW  DE signal is active low\r\n  * @param AssertionTime Driver Enable assertion time:\r\n  *                         5-bit value defining the time between the activation of the DE (Driver Enable)\r\n  *                         signal and the beginning of the start bit. It is expressed in sample time\r\n  *                         units (1/8 or 1/16 bit time, depending on the oversampling rate)\r\n  * @param DeassertionTime Driver Enable deassertion time:\r\n  *                         5-bit value defining the time between the end of the last stop bit, in a\r\n  *                         transmitted message, and the de-activation of the DE (Driver Enable) signal.\r\n  *                         It is expressed in sample time units (1/8 or 1/16 bit time, depending on the\r\n  *                         oversampling rate).\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)\r\n{\r\n  uint32_t temp = 0x0;\r\n\r\n  /* Check the UART handle allocation */\r\n  if(huart == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  /* Check the Driver Enable UART instance */\r\n  assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));\r\n\r\n  /* Check the Driver Enable polarity */\r\n  assert_param(IS_UART_DE_POLARITY(Polarity));\r\n\r\n  /* Check the Driver Enable assertion time */\r\n  assert_param(IS_UART_ASSERTIONTIME(AssertionTime));\r\n\r\n  /* Check the Driver Enable deassertion time */\r\n  assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));\r\n\r\n  if(huart->gState == HAL_UART_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    huart->Lock = HAL_UNLOCKED;\r\n\r\n    /* Init the low level hardware : GPIO, CLOCK, CORTEX */\r\n    HAL_UART_MspInit(huart);\r\n  }\r\n\r\n  huart->gState = HAL_UART_STATE_BUSY;\r\n\r\n  /* Disable the Peripheral */\r\n  __HAL_UART_DISABLE(huart);\r\n\r\n  /* Set the UART Communication parameters */\r\n  if (UART_SetConfig(huart) == HAL_ERROR)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  if(huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)\r\n  {\r\n    UART_AdvFeatureConfig(huart);\r\n  }\r\n\r\n  /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */\r\n  SET_BIT(huart->Instance->CR3, USART_CR3_DEM);\r\n\r\n  /* Set the Driver Enable polarity */\r\n  MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);\r\n\r\n  /* Set the Driver Enable assertion and deassertion times */\r\n  temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);\r\n  temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);\r\n  MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT|USART_CR1_DEAT), temp);\r\n\r\n  /* Enable the Peripheral */\r\n  __HAL_UART_ENABLE(huart);\r\n\r\n  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */\r\n  return (UART_CheckIdleState(huart));\r\n}\r\n\r\n/**\r\n  * @brief DeInitializes the UART peripheral\r\n  * @param huart uart handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)\r\n{\r\n  /* Check the UART handle allocation */\r\n  if(huart == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_UART_INSTANCE(huart->Instance));\r\n\r\n  huart->gState = HAL_UART_STATE_BUSY;\r\n\r\n  /* Disable the Peripheral */\r\n  __HAL_UART_DISABLE(huart);\r\n\r\n  huart->Instance->CR1 = 0x0U;\r\n  huart->Instance->CR2 = 0x0U;\r\n  huart->Instance->CR3 = 0x0U;\r\n\r\n  /* DeInit the low level hardware */\r\n  HAL_UART_MspDeInit(huart);\r\n\r\n  huart->ErrorCode = HAL_UART_ERROR_NONE;\r\n  huart->gState    = HAL_UART_STATE_RESET;\r\n  huart->RxState   = HAL_UART_STATE_RESET;\r\n\r\n  /* Process Unlock */\r\n  __HAL_UNLOCK(huart);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief UART MSP Init\r\n  * @param huart uart handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(huart);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_UART_MspInit can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief UART MSP DeInit\r\n  * @param huart uart handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(huart);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_UART_MspDeInit can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Exported_Functions_Group2 IO operation functions\r\n  * @brief UART Transmit/Receive functions\r\n  *\r\n@verbatim\r\n ===============================================================================\r\n                      ##### IO operation functions #####\r\n ===============================================================================\r\n    This subsection provides a set of functions allowing to manage the UART asynchronous\r\n    and Half duplex data transfers.\r\n\r\n    (#) There are two mode of transfer:\r\n       (+) Blocking mode: The communication is performed in polling mode.\r\n           The HAL status of all data processing is returned by the same function\r\n           after finishing transfer.\r\n       (+) Non-Blocking mode: The communication is performed using Interrupts\r\n           or DMA, These API's return the HAL status.\r\n           The end of the data processing will be indicated through the\r\n           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when\r\n           using DMA mode.\r\n           The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks\r\n           will be executed respectively at the end of the transmit or Receive process\r\n           The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected\r\n\r\n    (#) Blocking mode API's are :\r\n        (+) HAL_UART_Transmit()\r\n        (+) HAL_UART_Receive()\r\n\r\n    (#) Non-Blocking mode API's with Interrupt are :\r\n        (+) HAL_UART_Transmit_IT()\r\n        (+) HAL_UART_Receive_IT()\r\n        (+) HAL_UART_IRQHandler()\r\n        (+) UART_Transmit_IT()\r\n        (+) UART_Receive_IT()\r\n\r\n    (#) Non-Blocking mode API's with DMA are :\r\n        (+) HAL_UART_Transmit_DMA()\r\n        (+) HAL_UART_Receive_DMA()\r\n        (+) HAL_UART_DMAPause()\r\n        (+) HAL_UART_DMAResume()\r\n        (+) HAL_UART_DMAStop()\r\n\r\n    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:\r\n        (+) HAL_UART_TxHalfCpltCallback()\r\n        (+) HAL_UART_TxCpltCallback()\r\n        (+) HAL_UART_RxHalfCpltCallback()\r\n        (+) HAL_UART_RxCpltCallback()\r\n        (+) HAL_UART_ErrorCallback()\r\n\r\n\r\n    -@- In the Half duplex communication, it is forbidden to run the transmit\r\n        and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief Send an amount of data in blocking mode.\r\n  * @param huart UART handle.\r\n  * @param pData Pointer to data buffer.\r\n  * @param Size Amount of data to be sent.\r\n  * @param Timeout Timeout duration.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r\n{\r\n  uint16_t* tmp;\r\n  uint32_t tickstart = 0U;\r\n\r\n  /* Check that a Tx process is not already ongoing */\r\n  if(huart->gState == HAL_UART_STATE_READY)\r\n  {\r\n    if((pData == NULL ) || (Size == 0U))\r\n    {\r\n      return  HAL_ERROR;\r\n    }\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(huart);\r\n\r\n    huart->ErrorCode = HAL_UART_ERROR_NONE;\r\n    huart->gState = HAL_UART_STATE_BUSY_TX;\r\n\r\n    /* Init tickstart for timeout managment*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    huart->TxXferSize = Size;\r\n    huart->TxXferCount = Size;\r\n    while(huart->TxXferCount > 0U)\r\n    {\r\n      huart->TxXferCount--;\r\n      if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r\n      {\r\n        tmp = (uint16_t*) pData;\r\n        huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);\r\n        pData += 2;\r\n      }\r\n      else\r\n      {\r\n        huart->Instance->TDR = (*pData++ & (uint8_t)0xFFU);\r\n      }\r\n    }\r\n    if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n\r\n    /* At end of Tx process, restore huart->gState to Ready */\r\n    huart->gState = HAL_UART_STATE_READY;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(huart);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Receive an amount of data in blocking mode.\r\n  * @param huart UART handle.\r\n  * @param pData pointer to data buffer.\r\n  * @param Size amount of data to be received.\r\n  * @param Timeout Timeout duration.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r\n{\r\n  uint16_t* tmp;\r\n  uint16_t uhMask;\r\n  uint32_t tickstart = 0U;\r\n\r\n  /* Check that a Rx process is not already ongoing */\r\n  if(huart->RxState == HAL_UART_STATE_READY)\r\n  {\r\n    if((pData == NULL ) || (Size == 0U))\r\n    {\r\n      return  HAL_ERROR;\r\n    }\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(huart);\r\n\r\n    huart->ErrorCode = HAL_UART_ERROR_NONE;\r\n    huart->RxState = HAL_UART_STATE_BUSY_RX;\r\n\r\n    /* Init tickstart for timeout managment*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    huart->RxXferSize = Size;\r\n    huart->RxXferCount = Size;\r\n\r\n    /* Computation of UART mask to apply to RDR register */\r\n    UART_MASK_COMPUTATION(huart);\r\n    uhMask = huart->Mask;\r\n\r\n    /* as long as data have to be received */\r\n    while(huart->RxXferCount > 0U)\r\n    {\r\n      huart->RxXferCount--;\r\n      if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r\n      {\r\n        tmp = (uint16_t*) pData ;\r\n        *tmp = (uint16_t)(huart->Instance->RDR & uhMask);\r\n        pData +=2U;\r\n      }\r\n      else\r\n      {\r\n        *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);\r\n      }\r\n    }\r\n\r\n    /* At end of Rx process, restore huart->RxState to Ready */\r\n    huart->RxState = HAL_UART_STATE_READY;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(huart);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Send an amount of data in interrupt mode.\r\n  * @param huart UART handle.\r\n  * @param pData pointer to data buffer.\r\n  * @param Size amount of data to be sent.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\r\n{\r\n  /* Check that a Tx process is not already ongoing */\r\n  if(huart->gState == HAL_UART_STATE_READY)\r\n  {\r\n    if((pData == NULL ) || (Size == 0U))\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(huart);\r\n\r\n    huart->pTxBuffPtr = pData;\r\n    huart->TxXferSize = Size;\r\n    huart->TxXferCount = Size;\r\n\r\n    huart->ErrorCode = HAL_UART_ERROR_NONE;\r\n    huart->gState = HAL_UART_STATE_BUSY_TX;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(huart);\r\n\r\n    /* Enable the UART Transmit Data Register Empty Interrupt */\r\n    SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Receive an amount of data in interrupt mode.\r\n  * @param huart UART handle.\r\n  * @param pData pointer to data buffer.\r\n  * @param Size amount of data to be received.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\r\n{\r\n  /* Check that a Rx process is not already ongoing */\r\n  if(huart->RxState == HAL_UART_STATE_READY)\r\n  {\r\n    if((pData == NULL ) || (Size == 0U))\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(huart);\r\n\r\n    huart->pRxBuffPtr = pData;\r\n    huart->RxXferSize = Size;\r\n    huart->RxXferCount = Size;\r\n\r\n    /* Computation of UART mask to apply to RDR register */\r\n    UART_MASK_COMPUTATION(huart);\r\n\r\n    huart->ErrorCode = HAL_UART_ERROR_NONE;\r\n    huart->RxState = HAL_UART_STATE_BUSY_RX;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(huart);\r\n\r\n    /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */\r\n    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);\r\n\r\n    /* Enable the UART Parity Error and Data Register not empty Interrupts */\r\n    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Send an amount of data in DMA mode.\r\n  * @param huart UART handle.\r\n  * @param pData pointer to data buffer.\r\n  * @param Size amount of data to be sent.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\r\n{\r\n  uint32_t *tmp;\r\n\r\n  /* Check that a Tx process is not already ongoing */\r\n  if(huart->gState == HAL_UART_STATE_READY)\r\n  {\r\n    if((pData == NULL ) || (Size == 0U))\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(huart);\r\n\r\n    huart->pTxBuffPtr = pData;\r\n    huart->TxXferSize = Size;\r\n    huart->TxXferCount = Size;\r\n\r\n    huart->ErrorCode = HAL_UART_ERROR_NONE;\r\n    huart->gState = HAL_UART_STATE_BUSY_TX;\r\n\r\n    /* Set the UART DMA transfer complete callback */\r\n    huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;\r\n\r\n    /* Set the UART DMA Half transfer complete callback */\r\n    huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;\r\n\r\n    /* Set the DMA error callback */\r\n    huart->hdmatx->XferErrorCallback = UART_DMAError;\r\n\r\n    /* Set the DMA abort callback */\r\n    huart->hdmatx->XferAbortCallback = NULL;\r\n\r\n    /* Enable the UART transmit DMA channel */\r\n    tmp = (uint32_t*)&pData;\r\n    HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->TDR, Size);\r\n\r\n    /* Clear the TC flag in the SR register by writing 0 to it */\r\n    __HAL_UART_CLEAR_IT(huart, UART_FLAG_TC);\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(huart);\r\n\r\n    /* Enable the DMA transfer for transmit request by setting the DMAT bit\r\n       in the UART CR3 register */\r\n    SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Receive an amount of data in DMA mode.\r\n  * @param huart UART handle.\r\n  * @param pData pointer to data buffer.\r\n  * @param Size amount of data to be received.\r\n  * @note   When the UART parity is enabled (PCE = 1), the received data contain\r\n  *         the parity bit (MSB position).\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\r\n{\r\n  uint32_t *tmp;\r\n\r\n  /* Check that a Rx process is not already ongoing */\r\n  if(huart->RxState == HAL_UART_STATE_READY)\r\n  {\r\n    if((pData == NULL ) || (Size == 0U))\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(huart);\r\n\r\n    huart->pRxBuffPtr = pData;\r\n    huart->RxXferSize = Size;\r\n\r\n    huart->ErrorCode = HAL_UART_ERROR_NONE;\r\n    huart->RxState = HAL_UART_STATE_BUSY_RX;\r\n\r\n    /* Set the UART DMA transfer complete callback */\r\n    huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;\r\n\r\n    /* Set the UART DMA Half transfer complete callback */\r\n    huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;\r\n\r\n    /* Set the DMA error callback */\r\n    huart->hdmarx->XferErrorCallback = UART_DMAError;\r\n\r\n    /* Set the DMA abort callback */\r\n    huart->hdmarx->XferAbortCallback = NULL;\r\n\r\n    /* Enable the DMA channel */\r\n    tmp = (uint32_t*)&pData;\r\n    HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, *(uint32_t*)tmp, Size);\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(huart);\r\n\r\n    /* Enable the UART Parity Error Interrupt */\r\n    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r\n\r\n    /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */\r\n    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);\r\n\r\n    /* Enable the DMA transfer for the receiver request by setting the DMAR bit\r\n    in the UART CR3 register */\r\n    SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Pause the DMA Transfer.\r\n  * @param huart UART handle.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(huart);\r\n\r\n  if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&\r\n      (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))\r\n  {\r\n    /* Disable the UART DMA Tx request */\r\n    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r\n  }\r\n  if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&\r\n      (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))\r\n  {\r\n    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */\r\n    CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r\n    CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r\n\r\n    /* Disable the UART DMA Rx request */\r\n    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r\n  }\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(huart);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Resume the DMA Transfer.\r\n  * @param huart UART handle.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(huart);\r\n\r\n  if(huart->gState == HAL_UART_STATE_BUSY_TX)\r\n  {\r\n    /* Enable the UART DMA Tx request */\r\n    SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r\n  }\r\n  if(huart->RxState == HAL_UART_STATE_BUSY_RX)\r\n  {\r\n    /* Clear the Overrun flag before resuming the Rx transfer*/\r\n    __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);\r\n\r\n    /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */\r\n    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r\n    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);\r\n\r\n    /* Enable the UART DMA Rx request */\r\n    SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r\n  }\r\n\r\n  /* If the UART peripheral is still not enabled, enable it */\r\n  if ((huart->Instance->CR1 & USART_CR1_UE) == 0U)\r\n  {\r\n    /* Enable UART peripheral */\r\n    __HAL_UART_ENABLE(huart);\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Stop the DMA Transfer.\r\n  * @param huart UART handle.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)\r\n{\r\n  /* The Lock is not implemented on this API to allow the user application\r\n     to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /\r\n     HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:\r\n     indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete\r\n     interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of\r\n     the stream and the corresponding call back is executed. */\r\n\r\n  /* Stop UART DMA Tx request if ongoing */\r\n  if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&\r\n      (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))\r\n  {\r\n    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r\n\r\n    /* Abort the UART DMA Tx channel */\r\n    if(huart->hdmatx != NULL)\r\n    {\r\n      HAL_DMA_Abort(huart->hdmatx);\r\n    }\r\n\r\n    UART_EndTxTransfer(huart);\r\n  }\r\n\r\n  /* Stop UART DMA Rx request if ongoing */\r\n  if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&\r\n      (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))\r\n  {\r\n    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r\n\r\n    /* Abort the UART DMA Rx channel */\r\n    if(huart->hdmarx != NULL)\r\n    {\r\n      HAL_DMA_Abort(huart->hdmarx);\r\n    }\r\n\r\n    UART_EndRxTransfer(huart);\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief This function handles UART interrupt request.\r\n  * @param huart uart handle\r\n  * @retval None\r\n  */\r\nvoid HAL_UART_IRQHandler(UART_HandleTypeDef *huart)\r\n{\r\n  uint32_t isrflags   = READ_REG(huart->Instance->ISR);\r\n  uint32_t cr1its     = READ_REG(huart->Instance->CR1);\r\n  uint32_t cr3its     = READ_REG(huart->Instance->CR3);\r\n  uint32_t errorflags;\r\n\r\n  /* If no error occurs */\r\n  errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));\r\n  if (errorflags == RESET)\r\n  {\r\n    /* UART in mode Receiver ---------------------------------------------------*/\r\n    if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))\r\n    {\r\n      UART_Receive_IT(huart);\r\n      return;\r\n    }\r\n  }\r\n\r\n  /* If some errors occur */\r\n  if(   (errorflags != RESET)\r\n     && (   ((cr3its & USART_CR3_EIE) != RESET)\r\n         || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )\r\n  {\r\n\r\n    /* UART parity error interrupt occurred -------------------------------------*/\r\n    if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))\r\n    {\r\n      __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF);\r\n\r\n      huart->ErrorCode |= HAL_UART_ERROR_PE;\r\n    }\r\n\r\n    /* UART frame error interrupt occurred --------------------------------------*/\r\n    if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))\r\n    {\r\n      __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF);\r\n\r\n      huart->ErrorCode |= HAL_UART_ERROR_FE;\r\n    }\r\n\r\n    /* UART noise error interrupt occurred --------------------------------------*/\r\n    if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))\r\n    {\r\n      __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF);\r\n\r\n      huart->ErrorCode |= HAL_UART_ERROR_NE;\r\n    }\r\n    \r\n    /* UART Over-Run interrupt occurred -----------------------------------------*/\r\n    if(((isrflags & USART_ISR_ORE) != RESET) &&\r\n       (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))\r\n    {\r\n      __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);\r\n\r\n      huart->ErrorCode |= HAL_UART_ERROR_ORE;\r\n    }\r\n\r\n    /* Call UART Error Call back function if need be --------------------------*/\r\n    if(huart->ErrorCode != HAL_UART_ERROR_NONE)\r\n    {\r\n      /* UART in mode Receiver ---------------------------------------------------*/\r\n      if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))\r\n      {\r\n        UART_Receive_IT(huart);\r\n      }\r\n\r\n      /* If Overrun error occurs, or if any error occurs in DMA mode reception,\r\n         consider error as blocking */\r\n      if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) ||\r\n          (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))\r\n      {\r\n        /* Blocking error : transfer is aborted\r\n           Set the UART state ready to be able to start again the process,\r\n           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */\r\n        UART_EndRxTransfer(huart);\r\n\r\n        /* Disable the UART DMA Rx request if enabled */\r\n        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))\r\n        {\r\n          CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r\n\r\n          /* Abort the UART DMA Rx channel */\r\n          if(huart->hdmarx != NULL)\r\n          {\r\n            /* Set the UART DMA Abort callback :\r\n            will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */\r\n            huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;\r\n\r\n            /* Abort DMA RX */\r\n            if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)\r\n            {\r\n              /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */\r\n              huart->hdmarx->XferAbortCallback(huart->hdmarx);\r\n            }\r\n          }\r\n          else\r\n          {\r\n            /* Call user error callback */\r\n            HAL_UART_ErrorCallback(huart);\r\n          }\r\n        }\r\n        else\r\n        {\r\n          /* Call user error callback */\r\n          HAL_UART_ErrorCallback(huart);\r\n        }\r\n      }\r\n      else\r\n      {\r\n        /* Non Blocking error : transfer could go on.\r\n           Error is notified to user through user error callback */\r\n        HAL_UART_ErrorCallback(huart);\r\n        huart->ErrorCode = HAL_UART_ERROR_NONE;\r\n      }\r\n    }\r\n    return;\r\n\r\n  } /* End if some error occurs */\r\n\r\n  /* UART in mode Transmitter ------------------------------------------------*/\r\n  if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))\r\n  {\r\n    UART_Transmit_IT(huart);\r\n    return;\r\n  }\r\n\r\n  /* UART in mode Transmitter (transmission end) -----------------------------*/\r\n  if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))\r\n  {\r\n    UART_EndTransmit_IT(huart);\r\n    return;\r\n  }\r\n\r\n}\r\n\r\n/**\r\n  * @brief  This function handles UART Communication Timeout.\r\n  * @param  huart UART handle\r\n  * @param  Flag specifies the UART flag to check.\r\n  * @param  Status The new Flag status (SET or RESET).\r\n  * @param  Tickstart Tick start value\r\n  * @param  Timeout Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)\r\n{\r\n  /* Wait until flag is set */\r\n  while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0U)||((HAL_GetTick()-Tickstart) >=  Timeout))\r\n      {\r\n        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */\r\n        CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));\r\n        CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r\n\r\n        huart->gState = HAL_UART_STATE_READY;\r\n        huart->RxState = HAL_UART_STATE_READY;\r\n\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(huart);\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief DMA UART transmit process complete callback\r\n  * @param hdma DMA handle\r\n  * @retval None\r\n  */\r\nstatic void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n\r\n  /* DMA Normal mode*/\r\n  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)\r\n  {\r\n    huart->TxXferCount = 0U;\r\n\r\n    /* Disable the DMA transfer for transmit request by setting the DMAT bit\r\n       in the UART CR3 register */\r\n    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r\n\r\n    /* Enable the UART Transmit Complete Interrupt */\r\n    SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);\r\n  }\r\n  /* DMA Circular mode */\r\n  else\r\n  {\r\n    HAL_UART_TxCpltCallback(huart);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief DMA UART transmit process half complete callback\r\n  * @param hdma  DMA handle\r\n  * @retval None\r\n  */\r\nstatic void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n\r\n  HAL_UART_TxHalfCpltCallback(huart);\r\n}\r\n\r\n/**\r\n  * @brief DMA UART receive process complete callback\r\n  * @param hdma DMA handle\r\n  * @retval None\r\n  */\r\nstatic void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n\r\n  /* DMA Normal mode */\r\n  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)\r\n  {\r\n    huart->RxXferCount = 0U;\r\n\r\n    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */\r\n    CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r\n    CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r\n\r\n    /* Disable the DMA transfer for the receiver request by setting the DMAR bit\r\n    in the UART CR3 register */\r\n    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r\n\r\n\t/* At end of Rx process, restore huart->RxState to Ready */\r\n    huart->RxState = HAL_UART_STATE_READY;\r\n  }\r\n  HAL_UART_RxCpltCallback(huart);\r\n}\r\n\r\n/**\r\n  * @brief DMA UART receive process half complete callback\r\n  * @param hdma  DMA handle\r\n  * @retval None\r\n  */\r\nstatic void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n\r\n  HAL_UART_RxHalfCpltCallback(huart);\r\n}\r\n\r\n/**\r\n  * @brief DMA UART communication error callback\r\n  * @param hdma DMA handle\r\n  * @retval None\r\n  */\r\nstatic void UART_DMAError(DMA_HandleTypeDef *hdma)\r\n{\r\n  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  huart->RxXferCount = 0U;\r\n  huart->TxXferCount = 0U;\r\n  /* Stop UART DMA Tx request if ongoing */\r\n  if (  (huart->gState == HAL_UART_STATE_BUSY_TX)\r\n      &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) )\r\n  {\r\n    UART_EndTxTransfer(huart);\r\n  }\r\n\r\n  /* Stop UART DMA Rx request if ongoing */\r\n  if (  (huart->RxState == HAL_UART_STATE_BUSY_RX)\r\n      &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) )\r\n  {\r\n    UART_EndRxTransfer(huart);\r\n  }\r\n  SET_BIT(huart->ErrorCode, HAL_UART_ERROR_DMA);\r\n  HAL_UART_ErrorCallback(huart);\r\n}\r\n\r\n/**\r\n  * @brief DMA UART communication abort callback, when call by HAL services on Error\r\n  *        (To be called at end of DMA Abort procedure following error occurrence).\r\n  * @param hdma DMA handle.\r\n  * @retval None\r\n  */\r\nstatic void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)\r\n{\r\n  UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);\r\n  huart->RxXferCount = 0U;\r\n  huart->TxXferCount = 0U;\r\n\r\n  HAL_UART_ErrorCallback(huart);\r\n}\r\n\r\n/**\r\n  * @brief Tx Transfer completed callbacks\r\n  * @param huart uart handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(huart);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_UART_TxCpltCallback can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Tx Half Transfer completed callbacks.\r\n  * @param  huart UART handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(huart);\r\n\r\n  /* NOTE: This function should not be modified, when the callback is needed,\r\n           the HAL_UART_TxHalfCpltCallback can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief Rx Transfer completed callbacks\r\n  * @param huart uart handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(huart);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_UART_RxCpltCallback can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Rx Half Transfer completed callbacks.\r\n  * @param  huart UART handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(huart);\r\n\r\n  /* NOTE: This function should not be modified, when the callback is needed,\r\n           the HAL_UART_RxHalfCpltCallback can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief UART error callbacks\r\n  * @param huart uart handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(huart);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_UART_ErrorCallback can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief Send an amount of data in interrupt mode\r\n  *         Function called under interruption only, once\r\n  *         interruptions have been enabled by HAL_UART_Transmit_IT()\r\n  * @param  huart UART handle\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)\r\n{\r\n  uint16_t* tmp;\r\n\r\n  /* Check that a Tx process is ongoing */\r\n  if (huart->gState == HAL_UART_STATE_BUSY_TX)\r\n  {\r\n\r\n    if(huart->TxXferCount == 0U)\r\n    {\r\n      /* Disable the UART Transmit Data Register Empty Interrupt */\r\n      CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);\r\n\r\n      /* Enable the UART Transmit Complete Interrupt */\r\n      SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);\r\n\r\n      return HAL_OK;\r\n    }\r\n    else\r\n    {\r\n      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r\n      {\r\n        tmp = (uint16_t*) huart->pTxBuffPtr;\r\n        huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);\r\n        huart->pTxBuffPtr += 2U;\r\n      }\r\n      else\r\n      {\r\n        huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFFU);\r\n      }\r\n\r\n      huart->TxXferCount--;\r\n\r\n      return HAL_OK;\r\n    }\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Wrap up transmission in non-blocking mode.\r\n  * @param  huart pointer to a UART_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified UART module.\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)\r\n{\r\n  /* Disable the UART Transmit Complete Interrupt */\r\n  CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);\r\n\r\n  /* Tx process is ended, restore huart->gState to Ready */\r\n  huart->gState = HAL_UART_STATE_READY;\r\n\r\n  HAL_UART_TxCpltCallback(huart);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Receive an amount of data in interrupt mode\r\n  *         Function called under interruption only, once\r\n  *         interruptions have been enabled by HAL_UART_Receive_IT()\r\n  * @param  huart UART handle\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)\r\n{\r\n  uint16_t* tmp;\r\n  uint16_t uhMask = huart->Mask;\r\n\r\n  /* Check that a Rx process is ongoing */\r\n  if(huart->RxState == HAL_UART_STATE_BUSY_RX)\r\n  {\r\n\r\n    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r\n    {\r\n      tmp = (uint16_t*) huart->pRxBuffPtr ;\r\n      *tmp = (uint16_t)(huart->Instance->RDR & uhMask);\r\n      huart->pRxBuffPtr +=2;\r\n    }\r\n    else\r\n    {\r\n      *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);\r\n    }\r\n\r\n    if(--huart->RxXferCount == 0)\r\n    {\r\n      /* Disable the UART Parity Error Interrupt and RXNE interrupt*/\r\n      CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r\n\r\n      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */\r\n      CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r\n\r\n      /* Rx process is completed, restore huart->RxState to Ready */\r\n      huart->RxState = HAL_UART_STATE_READY;\r\n\r\n      HAL_UART_RxCpltCallback(huart);\r\n\r\n      return HAL_OK;\r\n    }\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    /* Clear RXNE interrupt flag */\r\n    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);\r\n\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).\r\n  * @param  huart UART handle.\r\n  * @retval None\r\n  */\r\nstatic void UART_EndTxTransfer(UART_HandleTypeDef *huart)\r\n{\r\n  /* Disable TXEIE and TCIE interrupts */\r\n  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));\r\n\r\n  /* At end of Tx process, restore huart->gState to Ready */\r\n  huart->gState = HAL_UART_STATE_READY;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).\r\n  * @param  huart UART handle.\r\n  * @retval None\r\n  */\r\nstatic void UART_EndRxTransfer(UART_HandleTypeDef *huart)\r\n{\r\n  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\r\n  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r\n  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r\n\r\n  /* At end of Rx process, restore huart->RxState to Ready */\r\n  huart->RxState = HAL_UART_STATE_READY;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions\r\n  *  @brief   UART control functions\r\n  *\r\n@verbatim\r\n ===============================================================================\r\n                      ##### Peripheral Control functions #####\r\n ===============================================================================\r\n    [..]\r\n    This subsection provides a set of functions allowing to control the UART.\r\n     (+) HAL_UART_GetState() API is helpful to check in run-time the state of the UART peripheral.\r\n     (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode\r\n     (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode\r\n     (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode\r\n     (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode\r\n     (+) UART_SetConfig() API configures the UART peripheral\r\n     (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features\r\n     (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization\r\n     (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter\r\n     (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver\r\n     (+) HAL_LIN_SendBreak() API transmits the break characters\r\n\t (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address\r\n         detection length to more than 4 bits for multiprocessor address mark wake up.\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief Enable UART in mute mode (doesn't mean UART enters mute mode;\r\n  * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called)\r\n  * @param huart UART handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(huart);\r\n\r\n  huart->gState = HAL_UART_STATE_BUSY;\r\n\r\n  /* Enable USART mute mode by setting the MME bit in the CR1 register */\r\n  SET_BIT(huart->Instance->CR1, USART_CR1_MME);\r\n\r\n  huart->gState = HAL_UART_STATE_READY;\r\n\r\n  return (UART_CheckIdleState(huart));\r\n}\r\n\r\n/**\r\n  * @brief Disable UART mute mode (doesn't mean it actually wakes up the software,\r\n  * as it may not have been in mute mode at this very moment).\r\n  * @param huart uart handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(huart);\r\n\r\n  huart->gState = HAL_UART_STATE_BUSY;\r\n\r\n   /* Disable USART mute mode by clearing the MME bit in the CR1 register */\r\n  CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);\r\n\r\n  huart->gState = HAL_UART_STATE_READY;\r\n\r\n  return (UART_CheckIdleState(huart));\r\n}\r\n\r\n/**\r\n  * @brief Enter UART mute mode (means UART actually enters mute mode).\r\n  * To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.\r\n  * @param huart uart handle\r\n  * @retval HAL status\r\n  */\r\nvoid HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)\r\n{\r\n  __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);\r\n}\r\n\r\n\r\n\r\n/**\r\n  * @brief return the UART state\r\n  * @param huart uart handle\r\n  * @retval HAL state\r\n  */\r\nHAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)\r\n{\r\n  uint32_t temp1= 0x00U, temp2 = 0x00U;\r\n  temp1 = huart->gState;\r\n  temp2 = huart->RxState;\r\n\r\n  return (HAL_UART_StateTypeDef)(temp1 | temp2);\r\n}\r\n\r\n/**\r\n* @brief  Return the UART error code\r\n* @param  huart  pointer to a UART_HandleTypeDef structure that contains\r\n  *              the configuration information for the specified UART.\r\n* @retval UART Error Code\r\n*/\r\nuint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)\r\n{\r\n  return huart->ErrorCode;\r\n}\r\n\r\n/**\r\n  * @brief Configure the UART peripheral\r\n  * @param huart uart handle\r\n  * @retval None\r\n  */\r\nHAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)\r\n{\r\n  uint32_t tmpreg                     = 0x00000000U;\r\n  UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED;\r\n  uint16_t brrtemp                    = 0x0000U;\r\n  uint16_t usartdiv                   = 0x0000U;\r\n  HAL_StatusTypeDef ret               = HAL_OK;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));\r\n  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));\r\n  assert_param(IS_UART_STOPBITS(huart->Init.StopBits));\r\n  assert_param(IS_UART_PARITY(huart->Init.Parity));\r\n  assert_param(IS_UART_MODE(huart->Init.Mode));\r\n  assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));\r\n  assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));\r\n\r\n\r\n  /*-------------------------- USART CR1 Configuration -----------------------*/\r\n  /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure\r\n   *  the UART Word Length, Parity, Mode and oversampling:\r\n   *  set the M bits according to huart->Init.WordLength value\r\n   *  set PCE and PS bits according to huart->Init.Parity value\r\n   *  set TE and RE bits according to huart->Init.Mode value\r\n   *  set OVER8 bit according to huart->Init.OverSampling value */\r\n  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;\r\n  MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);\r\n\r\n  /*-------------------------- USART CR2 Configuration -----------------------*/\r\n  /* Configure the UART Stop Bits: Set STOP[13:12] bits according\r\n   * to huart->Init.StopBits value */\r\n  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);\r\n\r\n  /*-------------------------- USART CR3 Configuration -----------------------*/\r\n  /* Configure\r\n   * - UART HardWare Flow Control: set CTSE and RTSE bits according\r\n   *   to huart->Init.HwFlowCtl value\r\n   * - one-bit sampling method versus three samples' majority rule according\r\n   *   to huart->Init.OneBitSampling */\r\n  tmpreg = (uint32_t)huart->Init.HwFlowCtl | huart->Init.OneBitSampling ;\r\n  MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg);\r\n\r\n  /*-------------------------- USART BRR Configuration -----------------------*/\r\n  UART_GETCLOCKSOURCE(huart, clocksource);\r\n\r\n  /* Check UART Over Sampling to set Baud Rate Register */\r\n  if (huart->Init.OverSampling == UART_OVERSAMPLING_8)\r\n  {\r\n    switch (clocksource)\r\n    {\r\n    case UART_CLOCKSOURCE_PCLK1:\r\n        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));\r\n      break;\r\n    case UART_CLOCKSOURCE_PCLK2:\r\n        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));\r\n      break;\r\n    case UART_CLOCKSOURCE_HSI:\r\n        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));\r\n      break;\r\n    case UART_CLOCKSOURCE_SYSCLK:\r\n        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));\r\n      break;\r\n    case UART_CLOCKSOURCE_LSE:\r\n        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));\r\n      break;\r\n      case UART_CLOCKSOURCE_UNDEFINED:\r\n    default:\r\n        ret = HAL_ERROR;\r\n      break;\r\n    }\r\n\r\n    brrtemp = usartdiv & 0xFFF0U;\r\n    brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);\r\n    huart->Instance->BRR = brrtemp;\r\n  }\r\n  else\r\n  {\r\n    switch (clocksource)\r\n    {\r\n    case UART_CLOCKSOURCE_PCLK1:\r\n        huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));\r\n      break;\r\n    case UART_CLOCKSOURCE_PCLK2:\r\n        huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));\r\n      break;\r\n    case UART_CLOCKSOURCE_HSI:\r\n        huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));\r\n      break;\r\n    case UART_CLOCKSOURCE_SYSCLK:\r\n        huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));\r\n      break;\r\n    case UART_CLOCKSOURCE_LSE:\r\n        huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));\r\n      break;\r\n      case UART_CLOCKSOURCE_UNDEFINED:\r\n    default:\r\n        ret = HAL_ERROR;\r\n      break;\r\n    }\r\n  }\r\n\r\n  return ret;\r\n\r\n}\r\n\r\n\r\n/**\r\n  * @brief Configure the UART peripheral advanced features\r\n  * @param huart uart handle\r\n  * @retval None\r\n  */\r\nvoid UART_AdvFeatureConfig(UART_HandleTypeDef *huart)\r\n{\r\n  /* Check whether the set of advanced features to configure is properly set */\r\n  assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));\r\n\r\n  /* if required, configure TX pin active level inversion */\r\n  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))\r\n  {\r\n    assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));\r\n    MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);\r\n  }\r\n\r\n  /* if required, configure RX pin active level inversion */\r\n  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))\r\n  {\r\n    assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));\r\n    MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);\r\n  }\r\n\r\n  /* if required, configure data inversion */\r\n  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))\r\n  {\r\n    assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));\r\n    MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);\r\n  }\r\n\r\n  /* if required, configure RX/TX pins swap */\r\n  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))\r\n  {\r\n    assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));\r\n    MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);\r\n  }\r\n\r\n  /* if required, configure RX overrun detection disabling */\r\n  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))\r\n  {\r\n    assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));\r\n    MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);\r\n  }\r\n\r\n  /* if required, configure DMA disabling on reception error */\r\n  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))\r\n  {\r\n    assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));\r\n    MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);\r\n  }\r\n\r\n  /* if required, configure auto Baud rate detection scheme */\r\n  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))\r\n  {\r\n    assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));\r\n    MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);\r\n    /* set auto Baudrate detection parameters if detection is enabled */\r\n    if(huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)\r\n    {\r\n      assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));\r\n      MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);\r\n    }\r\n  }\r\n\r\n  /* if required, configure MSB first on communication line */\r\n  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))\r\n  {\r\n    assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));\r\n    MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);\r\n  }\r\n}\r\n\r\n\r\n\r\n/**\r\n  * @brief Check the UART Idle State\r\n  * @param huart uart handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)\r\n{\r\n  uint32_t tickstart = 0U;\r\n\r\n  /* Initialize the UART ErrorCode */\r\n  huart->ErrorCode = HAL_UART_ERROR_NONE;\r\n\r\n  /* Init tickstart for timeout managment*/\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Check if the Transmitter is enabled */\r\n  if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)\r\n  {\r\n    /* Wait until TEACK flag is set */\r\n    if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)\r\n    {\r\n      /* Timeout Occurred */\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n\r\n  /* Initialize the UART State */\r\n  huart->gState= HAL_UART_STATE_READY;\r\n  huart->RxState= HAL_UART_STATE_READY;\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(huart);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Enables the UART transmitter and disables the UART receiver.\r\n  * @param  huart UART handle\r\n  * @retval HAL status\r\n  * @retval None\r\n  */\r\nHAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(huart);\r\n  huart->gState = HAL_UART_STATE_BUSY;\r\n\r\n  /* Clear TE and RE bits */\r\n  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));\r\n  /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */\r\n  SET_BIT(huart->Instance->CR1, USART_CR1_TE);\r\n\r\n  huart->gState= HAL_UART_STATE_READY;\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(huart);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Enables the UART receiver and disables the UART transmitter.\r\n  * @param  huart UART handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(huart);\r\n  huart->gState = HAL_UART_STATE_BUSY;\r\n\r\n  /* Clear TE and RE bits */\r\n  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));\r\n  /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */\r\n  SET_BIT(huart->Instance->CR1, USART_CR1_RE);\r\n\r\n  huart->gState = HAL_UART_STATE_READY;\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(huart);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Transmits break characters.\r\n  * @param  huart UART handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_UART_INSTANCE(huart->Instance));\r\n\r\n  /* Process Locked */\r\n  __HAL_LOCK(huart);\r\n\r\n  huart->gState = HAL_UART_STATE_BUSY;\r\n\r\n  /* Send break characters */\r\n  SET_BIT(huart->Instance->RQR, UART_SENDBREAK_REQUEST);\r\n\r\n  huart->gState = HAL_UART_STATE_READY;\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(huart);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief By default in multiprocessor mode, when the wake up method is set\r\n  *        to address mark, the UART handles only 4-bit long addresses detection;\r\n  *        this API allows to enable longer addresses detection (6-, 7- or 8-bit\r\n  *        long).\r\n  * @note  Addresses detection lengths are: 6-bit address detection in 7-bit data mode,\r\n  *        7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.\r\n  * @param huart UART handle.\r\n  * @param AddressLength this parameter can be one of the following values:\r\n  *          @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address\r\n  *          @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)\r\n{\r\n  /* Check the UART handle allocation */\r\n  if(huart == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the address length parameter */\r\n  assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));\r\n\r\n  huart->gState = HAL_UART_STATE_BUSY;\r\n\r\n  /* Disable the Peripheral */\r\n  __HAL_UART_DISABLE(huart);\r\n\r\n  /* Set the address length */\r\n  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);\r\n\r\n  /* Enable the Peripheral */\r\n  __HAL_UART_ENABLE(huart);\r\n\r\n  /* TEACK and/or REACK to check before moving huart->gState to Ready */\r\n  return (UART_CheckIdleState(huart));\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_UART_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_usart.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_usart.c\r\n  * @author  MCD Application Team\r\n  * @brief   USART HAL module driver.\r\n  *          This file provides firmware functions to manage the following\r\n  *          functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter\r\n  *          Peripheral (USART).\r\n  *           + Initialization and de-initialization functions\r\n  *           + IO operation functions\r\n  *           + Peripheral Control functions\r\n  *\r\n  @verbatim\r\n  ===============================================================================\r\n                        ##### How to use this driver #####\r\n ===============================================================================\r\n    [..]\r\n      The USART HAL driver can be used as follows:\r\n\r\n      (#) Declare a USART_HandleTypeDef handle structure.\r\n      (#) Initialize the USART low level resources by implement the HAL_USART_MspInit ()API:\r\n          (##) Enable the USARTx interface clock.\r\n          (##) USART pins configuration:\r\n            (+++) Enable the clock for the USART GPIOs.\r\n            (+++) Configure these USART pins as alternate function pull-up.\r\n          (##) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),\r\n                HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):\r\n            (+++) Configure the USARTx interrupt priority.\r\n            (+++) Enable the NVIC USART IRQ handle.\r\n            (+++) The specific USART interrupts (Transmission complete interrupt,\r\n                  RXNE interrupt and Error Interrupts) will be managed using the macros\r\n                  __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.\r\n          (##) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()\r\n               HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):\r\n            (+++) Declare a DMA handle structure for the Tx/Rx stream.\r\n            (+++) Enable the DMAx interface clock.\r\n            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.\r\n            (+++) Configure the DMA Tx/Rx Stream.\r\n            (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.\r\n            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.\r\n\r\n      (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware\r\n          flow control and Mode(Receiver/Transmitter) in the husart Init structure.\r\n\r\n      (#) Initialize the USART registers by calling the HAL_USART_Init() API:\r\n          (++) These API's configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)\r\n               by calling the customed HAL_USART_MspInit(&husart) API.\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup USART USART\r\n  * @brief HAL USART Synchronous module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_USART_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @addtogroup USART_Private_Constants\r\n  * @{\r\n  */\r\n#define DUMMY_DATA                             ((uint16_t) 0xFFFFU)\r\n#define TEACK_REACK_TIMEOUT                    ((uint32_t) 1000U)\r\n#define USART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \\\r\n                                     USART_CR1_TE | USART_CR1_RE  | USART_CR1_OVER8))\r\n#define USART_CR2_FIELDS       ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \\\r\n                            USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP))\r\n/**\r\n  * @}\r\n  */\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @addtogroup USART_Private_Functions\r\n  * @{\r\n  */\r\nstatic void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);\r\nstatic void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);\r\nstatic void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);\r\nstatic void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);\r\nstatic void USART_DMAError(DMA_HandleTypeDef *hdma);\r\nstatic void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);\r\nstatic void USART_EndTxTransfer(USART_HandleTypeDef *husart);\r\nstatic void USART_EndRxTransfer(USART_HandleTypeDef *husart);\r\nstatic HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);\r\nstatic HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);\r\nstatic HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);\r\nstatic HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);\r\nstatic HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);\r\nstatic HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);\r\nstatic HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @defgroup USART_Exported_Functions USART Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup USART_Exported_Functions_Group1 USART Initialization and de-initialization functions\r\n  *  @brief    Initialization and Configuration functions\r\n  *\r\n@verbatim\r\n ===============================================================================\r\n            ##### Initialization and Configuration functions #####\r\n ===============================================================================\r\n    [..]\r\n    This subsection provides a set of functions allowing to initialize the USART\r\n    in asynchronous and in synchronous modes.\r\n      (+) For the asynchronous mode only these parameters can be configured:\r\n        (++) Baud Rate\r\n        (++) Word Length\r\n        (++) Stop Bit\r\n        (++) Parity: If the parity is enabled, then the MSB bit of the data written\r\n             in the data register is transmitted but is changed by the parity bit.\r\n        (++) USART polarity\r\n        (++) USART phase\r\n        (++) USART LastBit\r\n        (++) Receiver/transmitter modes\r\n\r\n    [..]\r\n    The HAL_USART_Init() function follows the USART  synchronous configuration\r\n    procedure (details for the procedure are available in reference manual).\r\n\r\n@endverbatim\r\n\r\n   Depending on the frame length defined by the M1 and M0 bits (7-bit,\r\n   8-bit or 9-bit), the possible USART frame formats are as listed in the\r\n   following table:\r\n\r\n     +---------------------------------------------------------------+\r\n     | M1M0 bits |  PCE bit  |            USART frame                |\r\n     |-----------------------|---------------------------------------|\r\n     |     10    |     0     |    | SB | 7-bit data | STB |          |\r\n     |-----------|-----------|---------------------------------------|\r\n     |     10    |     1     |    | SB | 6-bit data | PB | STB |     |\r\n     +---------------------------------------------------------------+\r\n\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the USART mode according to the specified\r\n  *         parameters in the USART_InitTypeDef and create the associated handle.\r\n  * @param husart USART handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)\r\n{\r\n  /* Check the USART handle allocation */\r\n  if(husart == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_USART_INSTANCE(husart->Instance));\r\n\r\n  if(husart->State == HAL_USART_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    husart->Lock = HAL_UNLOCKED;\r\n    /* Init the low level hardware : GPIO, CLOCK */\r\n    HAL_USART_MspInit(husart);\r\n  }\r\n\r\n  husart->State = HAL_USART_STATE_BUSY;\r\n\r\n  /* Disable the Peripheral */\r\n  __HAL_USART_DISABLE(husart);\r\n\r\n  /* Set the Usart Communication parameters */\r\n  if (USART_SetConfig(husart) == HAL_ERROR)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* In Synchronous mode, the following bits must be kept cleared:\r\n  - LINEN bit in the USART_CR2 register\r\n  - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/\r\n  CLEAR_BIT(husart->Instance->CR2, USART_CR2_LINEN);\r\n  CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));\r\n\r\n  /* Enable the Peripheral */\r\n  __HAL_USART_ENABLE(husart);\r\n\r\n  /* TEACK and/or REACK to check before moving husart->State to Ready */\r\n  return (USART_CheckIdleState(husart));\r\n}\r\n\r\n/**\r\n  * @brief DeInitializes the USART peripheral\r\n  * @param husart USART handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)\r\n{\r\n   /* Check the USART handle allocation */\r\n  if(husart == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_USART_INSTANCE(husart->Instance));\r\n\r\n  husart->State = HAL_USART_STATE_BUSY;\r\n\r\n  husart->Instance->CR1 = 0x0U;\r\n  husart->Instance->CR2 = 0x0U;\r\n  husart->Instance->CR3 = 0x0U;\r\n\r\n  /* DeInit the low level hardware */\r\n  HAL_USART_MspDeInit(husart);\r\n\r\n  husart->ErrorCode = HAL_USART_ERROR_NONE;\r\n  husart->State = HAL_USART_STATE_RESET;\r\n\r\n  /* Process Unlock */\r\n  __HAL_UNLOCK(husart);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief USART MSP Init\r\n  * @param husart USART handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(husart);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_USART_MspInit can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief USART MSP DeInit\r\n  * @param husart USART handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(husart);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_USART_MspDeInit can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USART_Exported_Functions_Group2 IO operation functions\r\n  *  @brief   USART Transmit and Receive functions\r\n  *\r\n@verbatim\r\n ===============================================================================\r\n                      ##### IO operation functions #####\r\n ===============================================================================\r\n    This subsection provides a set of functions allowing to manage the USART synchronous\r\n    data transfers.\r\n\r\n    [..] The USART supports master mode only: it cannot receive or send data related to an input\r\n         clock (SCLK is always an output).\r\n\r\n    (#) There are two mode of transfer:\r\n       (++) Blocking mode: The communication is performed in polling mode.\r\n            The HAL status of all data processing is returned by the same function\r\n            after finishing transfer.\r\n       (++) No-Blocking mode: The communication is performed using Interrupts\r\n           or DMA, These API's return the HAL status.\r\n           The end of the data processing will be indicated through the\r\n           dedicated USART IRQ when using Interrupt mode or the DMA IRQ when\r\n           using DMA mode.\r\n           The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks\r\n           will be executed respectively at the end of the transmit or Receive process\r\n           The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected\r\n\r\n    (#) Blocking mode API's are :\r\n        (++) HAL_USART_Transmit()in simplex mode\r\n        (++) HAL_USART_Receive() in full duplex receive only\r\n        (++) HAL_USART_TransmitReceive() in full duplex mode\r\n\r\n    (#) Non-Blocking mode API's with Interrupt are :\r\n        (++) HAL_USART_Transmit_IT()in simplex mode\r\n        (++) HAL_USART_Receive_IT() in full duplex receive only\r\n        (++) HAL_USART_TransmitReceive_IT()in full duplex mode\r\n        (++) HAL_USART_IRQHandler()\r\n\r\n    (#) No-Blocking mode functions with DMA are :\r\n        (++) HAL_USART_Transmit_DMA()in simplex mode\r\n        (++) HAL_USART_Receive_DMA() in full duplex receive only\r\n        (++) HAL_USART_TransmitReceive_DMA() in full duplex mode\r\n        (++) HAL_USART_DMAPause()\r\n        (++) HAL_USART_DMAResume()\r\n        (++) HAL_USART_DMAStop()\r\n\r\n    (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:\r\n        (++) HAL_USART_TxCpltCallback()\r\n        (++) HAL_USART_RxCpltCallback()\r\n        (++) HAL_USART_TxHalfCpltCallback()\r\n        (++) HAL_USART_RxHalfCpltCallback()\r\n        (++) HAL_USART_ErrorCallback()\r\n        (++) HAL_USART_TxRxCpltCallback()\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Simplex Send an amount of data in blocking mode\r\n  * @param  husart USART handle\r\n  * @param pTxData pointer to data buffer\r\n  * @param Size amount of data to be sent\r\n  * @param Timeout  Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)\r\n{\r\n  uint16_t* tmp;\r\n  uint32_t tickstart = 0U;\r\n\r\n  if(husart->State == HAL_USART_STATE_READY)\r\n  {\r\n    if((pTxData == NULL) || (Size == 0U))\r\n    {\r\n      return  HAL_ERROR;\r\n    }\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(husart);\r\n\r\n    husart->ErrorCode = HAL_USART_ERROR_NONE;\r\n    husart->State = HAL_USART_STATE_BUSY_TX;\r\n\r\n    /* Init tickstart for timeout managment*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    husart->TxXferSize = Size;\r\n    husart->TxXferCount = Size;\r\n\r\n    /* Check the remaining data to be sent */\r\n    while(husart->TxXferCount > 0U)\r\n    {\r\n      husart->TxXferCount--;\r\n      if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n      if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r\n      {\r\n        tmp = (uint16_t*) pTxData;\r\n        husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);\r\n        pTxData += 2;\r\n      }\r\n      else\r\n      {\r\n        husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFFU);\r\n      }\r\n    }\r\n\r\n    if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n\r\n    husart->State = HAL_USART_STATE_READY;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(husart);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Receive an amount of data in blocking mode\r\n  * @note To receive synchronous data, dummy data are simultaneously transmitted\r\n  * @param husart USART handle\r\n  * @param pRxData pointer to data buffer\r\n  * @param Size amount of data to be received\r\n  * @param Timeout  Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)\r\n{\r\n  uint16_t* tmp;\r\n  uint16_t uhMask;\r\n  uint32_t tickstart = 0U;\r\n\r\n  if(husart->State == HAL_USART_STATE_READY)\r\n  {\r\n    if((pRxData == NULL) || (Size == 0U))\r\n    {\r\n      return  HAL_ERROR;\r\n    }\r\n    /* Process Locked */\r\n    __HAL_LOCK(husart);\r\n\r\n    husart->ErrorCode = HAL_USART_ERROR_NONE;\r\n    husart->State = HAL_USART_STATE_BUSY_RX;\r\n\r\n\t/* Init tickstart for timeout managment*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    husart->RxXferSize = Size;\r\n    husart->RxXferCount = Size;\r\n\r\n    /* Computation of USART mask to apply to RDR register */\r\n    __HAL_USART_MASK_COMPUTATION(husart);\r\n    uhMask = husart->Mask;\r\n\r\n    /* as long as data have to be received */\r\n    while(husart->RxXferCount > 0U)\r\n    {\r\n      husart->RxXferCount--;\r\n\r\n      /* Wait until TC flag is set to send dummy byte in order to generate the\r\n      * clock for the slave to send data.\r\n       * Whatever the frame length (7, 8 or 9-bit long), the same dummy value\r\n       * can be written for all the cases. */\r\n      if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n      husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x0FFU);\r\n\r\n      /* Wait for RXNE Flag */\r\n      if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n\r\n      if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r\n      {\r\n        tmp = (uint16_t*) pRxData ;\r\n        *tmp = (uint16_t)(husart->Instance->RDR & uhMask);\r\n        pRxData +=2;\r\n      }\r\n      else\r\n      {\r\n        *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);\r\n      }\r\n    }\r\n\r\n    husart->State = HAL_USART_STATE_READY;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(husart);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Full-Duplex Send and Receive an amount of data in blocking mode\r\n  * @param husart USART handle\r\n  * @param pTxData pointer to TX data buffer\r\n  * @param pRxData pointer to RX data buffer\r\n  * @param Size amount of data to be sent (same amount to be received)\r\n  * @param Timeout  Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)\r\n{\r\n  uint16_t* tmp;\r\n  uint16_t uhMask;\r\n  uint32_t tickstart = 0U;\r\n\r\n  if(husart->State == HAL_USART_STATE_READY)\r\n  {\r\n    if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))\r\n    {\r\n      return  HAL_ERROR;\r\n    }\r\n    /* Process Locked */\r\n    __HAL_LOCK(husart);\r\n\r\n    husart->ErrorCode = HAL_USART_ERROR_NONE;\r\n    husart->State = HAL_USART_STATE_BUSY_RX;\r\n\r\n\t/* Init tickstart for timeout managment*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    husart->RxXferSize = Size;\r\n    husart->TxXferSize = Size;\r\n    husart->TxXferCount = Size;\r\n    husart->RxXferCount = Size;\r\n\r\n    /* Computation of USART mask to apply to RDR register */\r\n    __HAL_USART_MASK_COMPUTATION(husart);\r\n    uhMask = husart->Mask;\r\n\r\n    /* Check the remain data to be sent */\r\n    while(husart->TxXferCount > 0)\r\n    {\r\n      husart->TxXferCount--;\r\n      husart->RxXferCount--;\r\n\r\n      /* Wait until TC flag is set to send data */\r\n      if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n      if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r\n      {\r\n        tmp = (uint16_t*) pTxData;\r\n        husart->Instance->TDR = (*tmp & uhMask);\r\n        pTxData += 2;\r\n      }\r\n      else\r\n      {\r\n        husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask);\r\n      }\r\n\r\n      /* Wait for RXNE Flag */\r\n      if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n\r\n      if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r\n      {\r\n        tmp = (uint16_t*) pRxData ;\r\n        *tmp = (uint16_t)(husart->Instance->RDR & uhMask);\r\n        pRxData +=2U;\r\n      }\r\n      else\r\n      {\r\n        *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);\r\n      }\r\n    }\r\n\r\n    husart->State = HAL_USART_STATE_READY;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(husart);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Send an amount of data in interrupt mode\r\n  * @param  husart USART handle\r\n  * @param pTxData pointer to data buffer\r\n  * @param Size amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)\r\n{\r\n  if(husart->State == HAL_USART_STATE_READY)\r\n  {\r\n    if((pTxData == NULL ) || (Size == 0U))\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(husart);\r\n\r\n    husart->pTxBuffPtr = pTxData;\r\n    husart->TxXferSize = Size;\r\n    husart->TxXferCount = Size;\r\n\r\n    husart->ErrorCode = HAL_USART_ERROR_NONE;\r\n    husart->State = HAL_USART_STATE_BUSY_TX;\r\n\r\n    /* The USART Error Interrupts: (Frame error, noise error, overrun error)\r\n    are not managed by the USART Transmit Process to avoid the overrun interrupt\r\n    when the usart mode is configured for transmit and receive \"USART_MODE_TX_RX\"\r\n    to benefit for the frame error and noise interrupts the usart mode should be\r\n    configured only for transmit \"USART_MODE_TX\" */\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(husart);\r\n\r\n    /* Enable the USART Transmit Data Register Empty Interrupt */\r\n    __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Receive an amount of data in blocking mode\r\n  *        To receive synchronous data, dummy data are simultaneously transmitted\r\n  * @param husart USART handle\r\n  * @param pRxData pointer to data buffer\r\n  * @param Size amount of data to be received\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)\r\n{\r\n  if(husart->State == HAL_USART_STATE_READY)\r\n  {\r\n    if((pRxData == NULL ) || (Size == 0U))\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n    /* Process Locked */\r\n    __HAL_LOCK(husart);\r\n\r\n    husart->pRxBuffPtr = pRxData;\r\n    husart->RxXferSize = Size;\r\n    husart->RxXferCount = Size;\r\n\r\n    __HAL_USART_MASK_COMPUTATION(husart);\r\n\r\n    husart->ErrorCode = HAL_USART_ERROR_NONE;\r\n    husart->State = HAL_USART_STATE_BUSY_RX;\r\n\r\n    /* Enable the USART Parity Error and Data Register not empty Interrupts */\r\n    SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);\r\n\r\n    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r\n    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(husart);\r\n\r\n\r\n    /* Send dummy byte in order to generate the clock for the Slave to send the next data */\r\n    if(husart->Init.WordLength == USART_WORDLENGTH_9B)\r\n    {\r\n      husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x01FFU);\r\n    }\r\n    else\r\n    {\r\n      husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x00FFU);\r\n    }\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Full-Duplex Send and Receive an amount of data in interrupt mode\r\n  * @param husart USART handle\r\n  * @param pTxData pointer to TX data buffer\r\n  * @param pRxData pointer to RX data buffer\r\n  * @param Size amount of data to be sent (same amount to be received)\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,  uint16_t Size)\r\n{\r\n\r\n  if(husart->State == HAL_USART_STATE_READY)\r\n  {\r\n    if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n    /* Process Locked */\r\n    __HAL_LOCK(husart);\r\n\r\n    husart->pRxBuffPtr = pRxData;\r\n    husart->RxXferSize = Size;\r\n    husart->RxXferCount = Size;\r\n    husart->pTxBuffPtr = pTxData;\r\n    husart->TxXferSize = Size;\r\n    husart->TxXferCount = Size;\r\n\r\n    /* Computation of USART mask to apply to RDR register */\r\n    __HAL_USART_MASK_COMPUTATION(husart);\r\n\r\n    husart->ErrorCode = HAL_USART_ERROR_NONE;\r\n    husart->State = HAL_USART_STATE_BUSY_TX_RX;\r\n\r\n    /* Enable the USART Data Register not empty Interrupt */\r\n    SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);\r\n\r\n    /* Enable the USART Parity Error Interrupt */\r\n    SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);\r\n\r\n    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r\n    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(husart);\r\n\r\n    /* Enable the USART Transmit Data Register Empty Interrupt */\r\n    __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Send an amount of data in DMA mode\r\n  * @param husart USART handle\r\n  * @param pTxData pointer to data buffer\r\n  * @param Size amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)\r\n{\r\n  uint32_t *tmp;\r\n\r\n  if(husart->State == HAL_USART_STATE_READY)\r\n  {\r\n    if((pTxData == NULL ) || (Size == 0U))\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n    /* Process Locked */\r\n    __HAL_LOCK(husart);\r\n\r\n    husart->pTxBuffPtr = pTxData;\r\n    husart->TxXferSize = Size;\r\n    husart->TxXferCount = Size;\r\n\r\n    husart->ErrorCode = HAL_USART_ERROR_NONE;\r\n    husart->State = HAL_USART_STATE_BUSY_TX;\r\n\r\n    /* Set the USART DMA transfer complete callback */\r\n    husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;\r\n\r\n    /* Set the USART DMA Half transfer complete callback */\r\n    husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;\r\n\r\n    /* Set the DMA error callback */\r\n    husart->hdmatx->XferErrorCallback = USART_DMAError;\r\n\r\n    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r\n    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);\r\n    SET_BIT(husart->Instance->ISR, (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE | USART_ISR_ORE));\r\n\r\n    /* Enable the USART transmit DMA channel */\r\n    tmp = (uint32_t*)&pTxData;\r\n    HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);\r\n\r\n    /* Clear the TC flag in the SR register by writing 0 to it */\r\n    __HAL_USART_CLEAR_IT(husart, USART_FLAG_TC);\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(husart);\r\n\r\n    /* Enable the DMA transfer for transmit request by setting the DMAT bit\r\n       in the USART CR3 register */\r\n    SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Receive an amount of data in DMA mode\r\n  * @param husart USART handle\r\n  * @param pRxData pointer to data buffer\r\n  * @param Size amount of data to be received\r\n  * @note   When the USART parity is enabled (PCE = 1), the received data contain\r\n  *         the parity bit (MSB position)\r\n  * @retval HAL status\r\n  * @note The USART DMA transmit stream must be configured in order to generate the clock for the slave.\r\n  */\r\nHAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)\r\n{\r\n  uint32_t *tmp;\r\n\r\n  if(husart->State == HAL_USART_STATE_READY)\r\n  {\r\n    if((pRxData == NULL ) || (Size == 0U))\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(husart);\r\n\r\n    husart->pRxBuffPtr = pRxData;\r\n    husart->RxXferSize = Size;\r\n    husart->pTxBuffPtr = pRxData;\r\n    husart->TxXferSize = Size;\r\n\r\n    husart->ErrorCode = HAL_USART_ERROR_NONE;\r\n    husart->State = HAL_USART_STATE_BUSY_RX;\r\n\r\n    /* Set the USART DMA Rx transfer complete callback */\r\n    husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;\r\n\r\n    /* Set the USART DMA Half transfer complete callback */\r\n    husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;\r\n\r\n    /* Set the USART DMA Rx transfer error callback */\r\n    husart->hdmarx->XferErrorCallback = USART_DMAError;\r\n\r\n    /* Set the DMA abort callback */\r\n    husart->hdmatx->XferAbortCallback = NULL;\r\n\r\n\t/* Set the USART Tx DMA transfer complete callback as NULL because the communication closing\r\n    is performed in DMA reception complete callback  */\r\n    husart->hdmatx->XferHalfCpltCallback = NULL;\r\n    husart->hdmatx->XferCpltCallback = NULL;\r\n\r\n    /* Set the DMA error callback */\r\n    husart->hdmatx->XferErrorCallback = USART_DMAError;\r\n\r\n    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r\n    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);\r\n    SET_BIT(husart->Instance->ISR, (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE | USART_ISR_ORE));\r\n\r\n    /* Enable the USART receive DMA channel */\r\n    tmp = (uint32_t*)&pRxData;\r\n    HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);\r\n\r\n    /* Enable the USART transmit DMA channel: the transmit stream is used in order\r\n       to generate in the non-blocking mode the clock to the slave device,\r\n       this mode isn't a simplex receive mode but a full-duplex receive mode */\r\n    HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(husart);\r\n\r\n    /* Enable the USART Parity Error Interrupt */\r\n    SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);\r\n\r\n    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r\n    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);\r\n\r\n    /* Enable the DMA transfer for the receiver request by setting the DMAR bit\r\n       in the USART CR3 register */\r\n    SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);\r\n\r\n    /* Enable the DMA transfer for transmit request by setting the DMAT bit\r\n       in the USART CR3 register */\r\n    SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r\n\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Full-Duplex Transmit Receive an amount of data in non blocking mode\r\n  * @param husart USART handle\r\n  * @param pTxData pointer to TX data buffer\r\n  * @param pRxData pointer to RX data buffer\r\n  * @param Size amount of data to be received/sent\r\n  * @note   When the USART parity is enabled (PCE = 1) the data received contain the parity bit.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)\r\n{\r\n  uint32_t *tmp;\r\n\r\n  if(husart->State == HAL_USART_STATE_READY)\r\n  {\r\n    if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n    /* Process Locked */\r\n    __HAL_LOCK(husart);\r\n\r\n    husart->pRxBuffPtr = pRxData;\r\n    husart->RxXferSize = Size;\r\n    husart->pTxBuffPtr = pTxData;\r\n    husart->TxXferSize = Size;\r\n\r\n    husart->ErrorCode = HAL_USART_ERROR_NONE;\r\n    husart->State = HAL_USART_STATE_BUSY_TX_RX;\r\n\r\n    /* Set the USART DMA Rx transfer complete callback */\r\n    husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;\r\n\r\n    /* Set the USART DMA Half transfer complete callback */\r\n    husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;\r\n\r\n    /* Set the USART DMA Tx transfer complete callback */\r\n    husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;\r\n\r\n    /* Set the USART DMA Half transfer complete callback */\r\n    husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;\r\n\r\n    /* Set the USART DMA Tx transfer error callback */\r\n    husart->hdmatx->XferErrorCallback = USART_DMAError;\r\n\r\n    /* Set the USART DMA Rx transfer error callback */\r\n    husart->hdmarx->XferErrorCallback = USART_DMAError;\r\n\r\n    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r\n    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);\r\n    SET_BIT(husart->Instance->ISR, (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE | USART_ISR_ORE));\r\n\r\n    /* Enable the USART receive DMA channel */\r\n    tmp = (uint32_t*)&pRxData;\r\n    HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);\r\n\r\n    /* Enable the USART transmit DMA channel */\r\n    tmp = (uint32_t*)&pTxData;\r\n    HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);\r\n\r\n    /* Clear the TC flag in the SR register by writing 0 to it */\r\n    __HAL_USART_CLEAR_IT(husart, USART_FLAG_TC);\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(husart);\r\n\r\n    /* Enable the USART Parity Error Interrupt */\r\n    SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);\r\n\r\n    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r\n    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);\r\n\r\n    /* Enable the DMA transfer for the receiver request by setting the DMAR bit\r\n       in the USART CR3 register */\r\n    SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);\r\n\r\n    /* Enable the DMA transfer for transmit request by setting the DMAT bit\r\n       in the USART CR3 register */\r\n    SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Pauses the DMA Transfer.\r\n  * @param husart USART handle\r\n  * @retval None\r\n  */\r\nHAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(husart);\r\n\r\n  if(husart->State == HAL_USART_STATE_BUSY_TX)\r\n  {\r\n    /* Disable the USART DMA Tx request */\r\n    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r\n  }\r\n  else if(husart->State == HAL_USART_STATE_BUSY_RX)\r\n  {\r\n    /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\r\n    CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r\n    CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);\r\n    /* Disable the USART DMA Rx request */\r\n    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);\r\n  }\r\n  else if(husart->State == HAL_USART_STATE_BUSY_TX_RX)\r\n  {\r\n    /* Disable the USART DMA Tx request */\r\n    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);\r\n    /* Disable the USART DMA Rx request */\r\n    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r\n  }\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(husart);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Resumes the DMA Transfer.\r\n  * @param husart USART handle\r\n  * @retval None\r\n  */\r\nHAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(husart);\r\n\r\n  if(husart->State == HAL_USART_STATE_BUSY_TX)\r\n  {\r\n    /* Enable the USART DMA Tx request */\r\n    SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r\n  }\r\n  else if(husart->State == HAL_USART_STATE_BUSY_RX)\r\n  {\r\n    /* Clear the Overrun flag before resuming the Rx transfer*/\r\n    __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);\r\n\r\n    /* Reenable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\r\n    SET_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r\n    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);\r\n\r\n    /* Enable the USART DMA Rx request */\r\n    SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);\r\n  }\r\n  else if(husart->State == HAL_USART_STATE_BUSY_TX_RX)\r\n  {\r\n    /* Clear the Overrun flag before resuming the Rx transfer*/\r\n    __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);\r\n\r\n    /* Enable the USART DMA Rx request  before the DMA Tx request */\r\n    SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);\r\n\r\n    /* Enable the USART DMA Tx request */\r\n    SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r\n  }\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(husart);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Stops the DMA Transfer.\r\n  * @param husart USART handle\r\n  * @retval None\r\n  */\r\nHAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)\r\n{\r\n  /* The Lock is not implemented on this API to allow the user application\r\n     to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() /\r\n     HAL_USART_TxHalfCpltCallback / HAL_USART_RxHalfCpltCallback:\r\n     indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete\r\n     interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of\r\n     the stream and the corresponding call back is executed. */\r\n\r\n  /* Stop USART DMA Tx request if ongoing */\r\n  if ((husart->State == HAL_USART_STATE_BUSY_TX) &&\r\n      (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)))\r\n  {\r\n    USART_EndTxTransfer(husart);\r\n\r\n    /* Abort the USART DMA Tx channel */\r\n    if(husart->hdmatx != NULL)\r\n    {\r\n      HAL_DMA_Abort(husart->hdmatx);\r\n    }\r\n\r\n    /* Disable the USART Tx DMA request */\r\n    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r\n  }\r\n\r\n  /* Stop USART DMA Rx request if ongoing */\r\n  if ((husart->State == HAL_USART_STATE_BUSY_RX) &&\r\n      (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)))\r\n  {\r\n    USART_EndRxTransfer(husart);\r\n\r\n    /* Abort the USART DMA Rx channel */\r\n    if(husart->hdmarx != NULL)\r\n    {\r\n      HAL_DMA_Abort(husart->hdmarx);\r\n    }\r\n\r\n    /* Disable the USART Rx DMA request */\r\n    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  This function handles USART interrupt request.\r\n  * @param  husart USART handle\r\n  * @retval None\r\n  */\r\nvoid HAL_USART_IRQHandler(USART_HandleTypeDef *husart)\r\n{\r\n  uint32_t isrflags = READ_REG(husart->Instance->ISR);\r\n  uint32_t cr1its   = READ_REG(husart->Instance->CR1);\r\n  uint32_t cr3its   = READ_REG(husart->Instance->CR3);\r\n  uint32_t errorflags;\r\n\r\n  /* If no error occurs */\r\n  errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));\r\n  if (errorflags == RESET)\r\n  {\r\n    /* USART in mode Receiver --------------------------------------------------*/\r\n    if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))\r\n    {\r\n      if(husart->State == HAL_USART_STATE_BUSY_RX)\r\n      {\r\n        USART_Receive_IT(husart);\r\n      }\r\n      else\r\n      {\r\n        USART_TransmitReceive_IT(husart);\r\n      }\r\n    }\r\n  }\r\n\r\n  /* If some errors occur */\r\n  if(   (errorflags != RESET)\r\n     && (   ((cr3its & USART_CR3_EIE) != RESET)\r\n         || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )\r\n  {\r\n\r\n    /* USART parity error interrupt occurred ------------------------------------*/\r\n    if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))\r\n    {\r\n      __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF);\r\n      husart->ErrorCode |= HAL_USART_ERROR_PE;\r\n    }\r\n\r\n    /* USART frame error interrupt occurred -------------------------------------*/\r\n    if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))\r\n    {\r\n      __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF);\r\n      husart->ErrorCode |= HAL_USART_ERROR_FE;\r\n    }\r\n\r\n    /* USART noise error interrupt occurred -------------------------------------*/\r\n    if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))\r\n    {\r\n      __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF);\r\n      husart->ErrorCode |= HAL_USART_ERROR_NE;\r\n    }\r\n\r\n    /* USART Over-Run interrupt occurred ----------------------------------------*/\r\n    if(((isrflags & USART_ISR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))\r\n    {\r\n      __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);\r\n      husart->ErrorCode |= HAL_USART_ERROR_ORE;\r\n    }\r\n\r\n    /* Call USART Error Call back function if need be --------------------------*/\r\n    if(husart->ErrorCode != HAL_USART_ERROR_NONE)\r\n    {\r\n      /* USART in mode Receiver ---------------------------------------------------*/\r\n      if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))\r\n      {\r\n        USART_Receive_IT(husart);\r\n      }\r\n\r\n      /* If Overrun error occurs, or if any error occurs in DMA mode reception,\r\n      consider error as blocking */\r\n      if (((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) ||\r\n          (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)))\r\n      {\r\n        /* Blocking error : transfer is aborted\r\n        Set the USART state ready to be able to start again the process,\r\n        Disable Rx Interrupts, and disable Rx DMA request, if ongoing */\r\n        USART_EndRxTransfer(husart);\r\n\r\n        /* Disable the USART DMA Rx request if enabled */\r\n        if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))\r\n        {\r\n          CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);\r\n\r\n          /* Abort the USART DMA Rx channel */\r\n          if(husart->hdmarx != NULL)\r\n          {\r\n            /* Set the USART DMA Abort callback :\r\n            will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */\r\n            husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;\r\n\r\n            /* Abort DMA RX */\r\n            if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)\r\n            {\r\n              /* Call Directly husart->hdmarx->XferAbortCallback function in case of error */\r\n              husart->hdmarx->XferAbortCallback(husart->hdmarx);\r\n            }\r\n          }\r\n          else\r\n          {\r\n            /* Call user error callback */\r\n            HAL_USART_ErrorCallback(husart);\r\n          }\r\n        }\r\n        else\r\n        {\r\n          /* Call user error callback */\r\n          HAL_USART_ErrorCallback(husart);\r\n        }\r\n      }\r\n      else\r\n      {\r\n        /* Non Blocking error : transfer could go on.\r\n        Error is notified to user through user error callback */\r\n        HAL_USART_ErrorCallback(husart);\r\n        husart->ErrorCode = HAL_USART_ERROR_NONE;\r\n      }\r\n    }\r\n    return;\r\n\r\n  } /* End if some error occurs */\r\n\r\n  /* USART in mode Transmitter -----------------------------------------------*/\r\n  if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))\r\n  {\r\n    if(husart->State == HAL_USART_STATE_BUSY_TX)\r\n    {\r\n      USART_Transmit_IT(husart);\r\n    }\r\n    else\r\n    {\r\n      USART_TransmitReceive_IT(husart);\r\n    }\r\n    return;\r\n  }\r\n\r\n  /* USART in mode Transmitter (transmission end) -----------------------------*/\r\n  if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))\r\n  {\r\n    USART_EndTransmit_IT(husart);\r\n    return;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Tx Transfer completed callbacks\r\n  * @param husart USART handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(husart);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_USART_TxCpltCallback can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Tx Half Transfer completed callbacks.\r\n  * @param  husart USART handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(husart);\r\n\r\n  /* NOTE: This function should not be modified, when the callback is needed,\r\n           the HAL_USART_TxHalfCpltCallback can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Rx Transfer completed callbacks.\r\n  * @param  husart USART handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(husart);\r\n\r\n  /* NOTE: This function should not be modified, when the callback is needed,\r\n           the HAL_USART_RxCpltCallback can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief Rx Half Transfer completed callbacks\r\n  * @param husart usart handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(husart);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_USART_RxHalfCpltCallback can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief Tx/Rx Transfers completed callback for the non-blocking process\r\n  * @param husart USART handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(husart);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_USART_TxRxCpltCallback can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief USART error callbacks\r\n  * @param husart USART handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(husart);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_USART_ErrorCallback can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Errors functions\r\n  *  @brief   USART State and Errors functions\r\n  *\r\n@verbatim\r\n  ==============================================================================\r\n                  ##### Peripheral State and Errors functions #####\r\n  ==============================================================================\r\n  [..]\r\n    This subsection provides a set of functions allowing to return the State of\r\n    USART communication\r\n    process, return Peripheral Errors occurred during communication process\r\n     (+) HAL_USART_GetState() API can be helpful to check in run-time the state\r\n         of the USART peripheral.\r\n     (+) HAL_USART_GetError() check in run-time errors that could be occurred during\r\n         communication.\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief return the USART state\r\n  * @param husart USART handle\r\n  * @retval HAL state\r\n  */\r\nHAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)\r\n{\r\n  return husart->State;\r\n}\r\n\r\n/**\r\n  * @brief  Return the USART error code\r\n  * @param  husart  pointer to a USART_HandleTypeDef structure that contains\r\n  *              the configuration information for the specified USART.\r\n  * @retval USART Error Code\r\n  */\r\nuint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)\r\n{\r\n  return husart->ErrorCode;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/**\r\n  * @brief  Simplex Send an amount of data in non-blocking mode.\r\n  * @note   Function called under interruption only, once\r\n  *         interruptions have been enabled by HAL_USART_Transmit_IT().\r\n  * @param  husart USART handle\r\n  * @retval HAL status\r\n  * @note   The USART errors are not managed to avoid the overrun error.\r\n  */\r\nstatic HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)\r\n{\r\n  uint16_t* tmp;\r\n\r\n  if(husart->State == HAL_USART_STATE_BUSY_TX)\r\n  {\r\n\r\n    if(husart->TxXferCount == 0U)\r\n    {\r\n      /* Disable the USART Transmit data register empty interrupt */\r\n      __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);\r\n\r\n      /* Enable the USART Transmit Complete Interrupt */\r\n      __HAL_USART_ENABLE_IT(husart, USART_IT_TC);\r\n\r\n      return HAL_OK;\r\n    }\r\n    else\r\n    {\r\n      if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r\n      {\r\n        tmp = (uint16_t*) husart->pTxBuffPtr;\r\n        husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);\r\n        husart->pTxBuffPtr += 2U;\r\n      }\r\n      else\r\n      {\r\n        husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFF);\r\n      }\r\n\r\n      husart->TxXferCount--;\r\n\r\n      return HAL_OK;\r\n    }\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Wraps up transmission in non-blocking mode.\r\n  * @param  husart pointer to a USART_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified USART module.\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)\r\n{\r\n  /* Disable the USART Transmit Complete Interrupt */\r\n  CLEAR_BIT(husart->Instance->CR1, USART_CR1_TCIE);\r\n\r\n  /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r\n  CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);\r\n\r\n  husart->State = HAL_USART_STATE_READY;\r\n\r\n  HAL_USART_TxCpltCallback(husart);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Simplex Receive an amount of data in non-blocking mode.\r\n  *         Function called under interruption only, once\r\n  *         interruptions have been enabled by HAL_USART_Receive_IT()\r\n  * @param  husart USART handle\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)\r\n{\r\n  uint16_t* tmp;\r\n  uint16_t uhMask = husart->Mask;\r\n\r\n  if(husart->State == HAL_USART_STATE_BUSY_RX)\r\n  {\r\n\r\n    if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r\n    {\r\n      tmp = (uint16_t*) husart->pRxBuffPtr;\r\n      *tmp = (uint16_t)(husart->Instance->RDR & uhMask);\r\n      husart->pRxBuffPtr += 2U;\r\n    }\r\n    else\r\n    {\r\n      *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);\r\n    }\r\n      /* Send dummy byte in order to generate the clock for the Slave to Send the next data */\r\n      husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x00FFU);\r\n\r\n    if(--husart->RxXferCount == 0U)\r\n    {\r\n      CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);\r\n\r\n      /* Disable the USART Parity Error Interrupt */\r\n      CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);\r\n\r\n      /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r\n      CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);\r\n\r\n      husart->State = HAL_USART_STATE_READY;\r\n\r\n      HAL_USART_RxCpltCallback(husart);\r\n\r\n      return HAL_OK;\r\n    }\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).\r\n  *         Function called under interruption only, once\r\n  *         interruptions have been enabled by HAL_USART_TransmitReceive_IT()\r\n  * @param  husart USART handle\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)\r\n{\r\n  uint16_t* tmp;\r\n  uint16_t uhMask = husart->Mask;\r\n\r\n  if(husart->State == HAL_USART_STATE_BUSY_TX_RX)\r\n  {\r\n    if(husart->TxXferCount != 0x00U)\r\n    {\r\n      if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)\r\n      {\r\n        if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r\n        {\r\n          tmp = (uint16_t*) husart->pTxBuffPtr;\r\n          husart->Instance->TDR = (uint16_t)(*tmp & uhMask);\r\n          husart->pTxBuffPtr += 2U;\r\n        }\r\n        else\r\n        {\r\n          husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)uhMask);\r\n        }\r\n        husart->TxXferCount--;\r\n\r\n        /* Check the latest data transmitted */\r\n        if(husart->TxXferCount == 0U)\r\n        {\r\n           CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);\r\n        }\r\n      }\r\n    }\r\n\r\n    if(husart->RxXferCount != 0x00U)\r\n    {\r\n      if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)\r\n      {\r\n        if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r\n        {\r\n          tmp = (uint16_t*) husart->pRxBuffPtr;\r\n          *tmp = (uint16_t)(husart->Instance->RDR & uhMask);\r\n          husart->pRxBuffPtr += 2U;\r\n        }\r\n        else\r\n        {\r\n          *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);\r\n        }\r\n        husart->RxXferCount--;\r\n      }\r\n    }\r\n\r\n    /* Check the latest data received */\r\n    if(husart->RxXferCount == 0U)\r\n    {\r\n      CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);\r\n\r\n      /* Disable the USART Parity Error Interrupt */\r\n      CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);\r\n\r\n      /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r\n      CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);\r\n\r\n      husart->State = HAL_USART_STATE_READY;\r\n\r\n      HAL_USART_TxRxCpltCallback(husart);\r\n\r\n      return HAL_OK;\r\n    }\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  This function handles USART Communication Timeout.\r\n  * @param  husart USART handle\r\n  * @param  Flag specifies the USART flag to check.\r\n  * @param  Status The new Flag status (SET or RESET).\r\n  * @param  Tickstart Tick start value\r\n  * @param  Timeout Timeout duration\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)\r\n{\r\n  /* Wait until flag is set */\r\n  while((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0U)||((HAL_GetTick()-Tickstart) >=  Timeout))\r\n      {\r\n        /* Disable the USART Transmit Complete Interrupt */\r\n        CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);\r\n\r\n        /* Disable the USART RXNE Interrupt */\r\n        CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);\r\n\r\n        /* Disable the USART Parity Error Interrupt */\r\n        CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);\r\n\r\n        /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r\n        CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);\r\n\r\n        husart->State= HAL_USART_STATE_READY;\r\n\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(husart);\r\n\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief DMA USART transmit process complete callback\r\n  * @param  hdma DMA handle\r\n  * @retval None\r\n  */\r\nstatic void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n\r\n  /* DMA Normal mode */\r\n  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)\r\n  {\r\n    husart->TxXferCount = 0U;\r\n\r\n    if(husart->State == HAL_USART_STATE_BUSY_TX)\r\n    {\r\n      /* Disable the DMA transfer for transmit request by resetting the DMAT bit\r\n         in the USART CR3 register */\r\n      CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r\n\r\n      /* Enable the USART Transmit Complete Interrupt */\r\n      SET_BIT(husart->Instance->CR1, USART_CR1_TCIE);\r\n    }\r\n  }\r\n  /* DMA Circular mode */\r\n  else\r\n  {\r\n    if(husart->State == HAL_USART_STATE_BUSY_TX)\r\n    {\r\n    HAL_USART_TxCpltCallback(husart);\r\n   }\r\n }\r\n}\r\n\r\n\r\n/**\r\n  * @brief DMA USART transmit process half complete callback\r\n  * @param hdma  DMA handle\r\n  * @retval None\r\n  */\r\nstatic void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n\r\n  HAL_USART_TxHalfCpltCallback(husart);\r\n}\r\n\r\n/**\r\n  * @brief DMA USART receive process complete callback\r\n  * @param  hdma DMA handle\r\n  * @retval None\r\n  */\r\nstatic void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n\r\n  /* DMA Normal mode */\r\n  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)\r\n  {\r\n    husart->RxXferCount = 0U;\r\n\r\n    /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\r\n    CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r\n    CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);\r\n\r\n    /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit\r\n    in USART CR3 register */\r\n    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);\r\n    /* similarly, disable the DMA TX transfer that was started to provide the\r\n       clock to the slave device */\r\n    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r\n\r\n      if(husart->State == HAL_USART_STATE_BUSY_RX)\r\n      {\r\n        HAL_USART_RxCpltCallback(husart);\r\n      }\r\n      /* The USART state is HAL_USART_STATE_BUSY_TX_RX */\r\n      else\r\n      {\r\n        HAL_USART_TxRxCpltCallback(husart);\r\n      }\r\n    husart->State= HAL_USART_STATE_READY;\r\n  }\r\n  /* DMA circular mode */\r\n  else\r\n  {\r\n    if(husart->State == HAL_USART_STATE_BUSY_RX)\r\n    {\r\n      HAL_USART_RxCpltCallback(husart);\r\n    }\r\n    /* The USART state is HAL_USART_STATE_BUSY_TX_RX */\r\n    else\r\n    {\r\n      HAL_USART_TxRxCpltCallback(husart);\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief DMA USART receive process half complete callback\r\n  * @param hdma  DMA handle\r\n  * @retval None\r\n  */\r\nstatic void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n\r\n  HAL_USART_RxHalfCpltCallback(husart);\r\n}\r\n\r\n/**\r\n  * @brief DMA USART communication error callback\r\n  * @param  hdma DMA handle\r\n  * @retval None\r\n  */\r\nstatic void USART_DMAError(DMA_HandleTypeDef *hdma)\r\n{\r\n  USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n\r\n  husart->RxXferCount = 0U;\r\n  husart->TxXferCount = 0U;\r\n\r\n  /* Stop USART DMA Tx request if ongoing */\r\n  if((husart->State == HAL_USART_STATE_BUSY_TX)\r\n     &&(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)))\r\n  {\r\n    USART_EndTxTransfer(husart);\r\n  }\r\n\r\n  /* Stop USART DMA Rx request if ongoing */\r\n  if((husart->State == HAL_USART_STATE_BUSY_RX)\r\n     &&(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)))\r\n  {\r\n    USART_EndRxTransfer(husart);\r\n  }\r\n\r\n  husart->ErrorCode |= HAL_USART_ERROR_DMA;\r\n  husart->State= HAL_USART_STATE_READY;\r\n\r\n  HAL_USART_ErrorCallback(husart);\r\n}\r\n\r\n/**\r\n  * @brief DMA USART communication abort callback\r\n  *        (To be called at end of DMA Abort procedure).\r\n  * @param hdma DMA handle.\r\n  * @retval None\r\n  */\r\nstatic void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)\r\n{\r\n  USART_HandleTypeDef* husart = (USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  husart->RxXferCount = 0U;\r\n  husart->TxXferCount = 0U;\r\n\r\n  HAL_USART_ErrorCallback(husart);\r\n}\r\n\r\n/**\r\n  * @brief  End ongoing Tx transfer on USART peripheral (following error detection or Transmit completion).\r\n  * @param  husart USART handle.\r\n  * @retval None\r\n  */\r\nstatic void USART_EndTxTransfer(USART_HandleTypeDef *husart)\r\n{\r\n  /* At end of Tx process, restore husart->State to Ready */\r\n  husart->State = HAL_USART_STATE_READY;\r\n\r\n  /* Disable TXEIE and TCIE interrupts */\r\n  CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));\r\n}\r\n\r\n/**\r\n  * @brief  End ongoing Rx transfer on USART peripheral (following error detection or Reception completion).\r\n  * @param  husart USART handle.\r\n  * @retval None\r\n  */\r\nstatic void USART_EndRxTransfer(USART_HandleTypeDef *husart)\r\n{\r\n  /* At end of Rx process, restore husart->RxState to Ready */\r\n  husart->State = HAL_USART_STATE_READY;\r\n\r\n  /* Disable RXNE, PE and ERR interrupts */\r\n  CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r\n  CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);\r\n}\r\n\r\n/**\r\n  * @brief Configure the USART peripheral\r\n  * @param husart USART handle\r\n  * @retval None\r\n  */\r\nstatic HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)\r\n{\r\n  uint32_t tmpreg      = 0x0U;\r\n  USART_ClockSourceTypeDef clocksource = USART_CLOCKSOURCE_UNDEFINED;\r\n  HAL_StatusTypeDef ret                = HAL_OK;\r\n  uint16_t brrtemp                     = 0x0000U;\r\n  uint16_t usartdiv                    = 0x0000U;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));\r\n  assert_param(IS_USART_PHASE(husart->Init.CLKPhase));\r\n  assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));\r\n  assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));\r\n  assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));\r\n  assert_param(IS_USART_STOPBITS(husart->Init.StopBits));\r\n  assert_param(IS_USART_PARITY(husart->Init.Parity));\r\n  assert_param(IS_USART_MODE(husart->Init.Mode));\r\n  assert_param(IS_USART_OVERSAMPLING(husart->Init.OverSampling));\r\n\r\n\r\n  /*-------------------------- USART CR1 Configuration -----------------------*/\r\n   /* Clear M, PCE, PS, TE and RE bits and configure\r\n   *  the USART Word Length, Parity, Mode and OverSampling:\r\n   *  set the M bits according to husart->Init.WordLength value\r\n   *  set PCE and PS bits according to husart->Init.Parity value\r\n   *  set TE and RE bits according to husart->Init.Mode value\r\n   *  force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */\r\n  tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;\r\n  MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg);\r\n\r\n  /*---------------------------- USART CR2 Configuration ---------------------*/\r\n  /* Clear and configure the USART Clock, CPOL, CPHA, LBCL and STOP bits:\r\n   * set CPOL bit according to husart->Init.CLKPolarity value\r\n   * set CPHA bit according to husart->Init.CLKPhase value\r\n   * set LBCL bit according to husart->Init.CLKLastBit value\r\n   * set STOP[13:12] bits according to husart->Init.StopBits value */\r\n  tmpreg = (uint32_t)(USART_CLOCK_ENABLE);\r\n  tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase);\r\n  tmpreg |= ((uint32_t)husart->Init.CLKLastBit | (uint32_t)husart->Init.StopBits);\r\n  MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg);\r\n\r\n  /*-------------------------- USART CR3 Configuration -----------------------*/\r\n  /* no CR3 register configuration                                            */\r\n\r\n  /*-------------------------- USART BRR Configuration -----------------------*/\r\n  /* BRR is filled-up according to OVER8 bit setting which is forced to 1     */\r\n  USART_GETCLOCKSOURCE(husart, clocksource);\r\n  switch (clocksource)\r\n  {\r\n    case USART_CLOCKSOURCE_PCLK1:\r\n      usartdiv = (uint16_t)(((2*HAL_RCC_GetPCLK1Freq()) + (husart->Init.BaudRate/2))/ husart->Init.BaudRate);\r\n      break;\r\n    case USART_CLOCKSOURCE_PCLK2:\r\n      usartdiv = (uint16_t)(((2*HAL_RCC_GetPCLK2Freq()) + (husart->Init.BaudRate/2))/ husart->Init.BaudRate);\r\n      break;\r\n    case USART_CLOCKSOURCE_HSI:\r\n      usartdiv = (uint16_t)(((2*HSI_VALUE) + (husart->Init.BaudRate/2))/ husart->Init.BaudRate);\r\n      break;\r\n    case USART_CLOCKSOURCE_SYSCLK:\r\n      usartdiv = (uint16_t)(((2*HAL_RCC_GetSysClockFreq()) + (husart->Init.BaudRate/2))/ husart->Init.BaudRate);\r\n      break;\r\n    case USART_CLOCKSOURCE_LSE:\r\n      usartdiv = (uint16_t)(((2*LSE_VALUE) + (husart->Init.BaudRate/2))/ husart->Init.BaudRate);\r\n      break;\r\n    case USART_CLOCKSOURCE_UNDEFINED:\r\n    default:\r\n      ret = HAL_ERROR;\r\n      break;\r\n  }\r\n\r\n  brrtemp = usartdiv & 0xFFF0U;\r\n  brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);\r\n  husart->Instance->BRR = brrtemp;\r\n\r\n  return ret;\r\n}\r\n\r\n/**\r\n  * @brief Check the USART Idle State\r\n  * @param husart USART handle\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)\r\n{\r\n  uint32_t tickstart = 0U;\r\n\r\n   /* Initialize the USART ErrorCode */\r\n  husart->ErrorCode = HAL_USART_ERROR_NONE;\r\n\r\n  /* Init tickstart for timeout managment*/\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Check if the Transmitter is enabled */\r\n  if((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)\r\n  {\r\n    /* Wait until TEACK flag is set */\r\n    if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK)\r\n    {\r\n      husart->State= HAL_USART_STATE_TIMEOUT;\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n\r\n  /* Initialize the USART state*/\r\n  husart->State= HAL_USART_STATE_READY;\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(husart);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_USART_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_wwdg.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_wwdg.c\r\n  * @author  MCD Application Team\r\n  * @brief   WWDG HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the Window Watchdog (WWDG) peripheral:\r\n  *           + Initialization and Configuration function\r\n  *           + IO operation functions\r\n  @verbatim\r\n  ==============================================================================\r\n                      ##### WWDG specific features #####\r\n  ==============================================================================\r\n  [..]\r\n    Once enabled the WWDG generates a system reset on expiry of a programmed\r\n    time period, unless the program refreshes the counter (T[6;0] downcounter)\r\n    before reaching 0x3F value (i.e. a reset is generated when the counter\r\n    value rolls over from 0x40 to 0x3F).\r\n\r\n    (+) An MCU reset is also generated if the counter value is refreshed\r\n        before the counter has reached the refresh window value. This\r\n        implies that the counter must be refreshed in a limited window.\r\n\r\n    (+) Once enabled the WWDG cannot be disabled except by a system reset.\r\n\r\n    (+) WWDGRST flag in RCC_CSR register informs when a WWDG reset has \r\n        occurred (check available with __HAL_RCC_GET_FLAG(RCC_FLAG_WWDGRST)).\r\n\r\n    (+) The WWDG downcounter input clock is derived from the APB clock divided\r\n        by a programmable prescaler.\r\n\r\n    (+) WWDG downcounter clock (Hz) = PCLK1 / (4096 * Prescaler)\r\n\r\n    (+) WWDG timeout (ms) = (1000 * (T[5;0] + 1)) / (WWDG downcounter clock)\r\n        where T[5;0] are the lowest 6 bits of downcounter.\r\n\r\n    (+) WWDG Counter refresh is allowed between the following limits :\r\n        (++) min time (ms) = (1000 * (T[5;0] - Window)) / (WWDG downcounter clock)\r\n        (++) max time (ms) = (1000 * (T[5;0] - 0x40)) / (WWDG downcounter clock)\r\n\r\n    (+) Min-max timeout value @80 MHz(PCLK1): ~51.2 us / ~26.22 ms\r\n\r\n    (+) The Early Wakeup Interrupt (EWI) can be used if specific safety \r\n        operations or data logging must be performed before the actual reset is\r\n        generated. When the downcounter reaches the value 0x40, an EWI interrupt\r\n        is generated and the corresponding interrupt service routine (ISR) can \r\n        be used to trigger specific actions (such as communications or data \r\n        logging), before resetting the device.\r\n        In some applications, the EWI interrupt can be used to manage a software\r\n        system check and/or system recovery/graceful degradation, without \r\n        generating a WWDG reset. In this case, the corresponding interrupt \r\n        service routine (ISR) should reload the WWDG counter to avoid the WWDG \r\n        reset, then trigger the required actions.\r\n        Note:When the EWI interrupt cannot be served, e.g. due to a system lock \r\n        in a higher priority task, the WWDG reset will eventually be generated.\r\n\r\n    (+) Debug mode : When the microcontroller enters debug mode (core halted),\r\n        the WWDG counter either continues to work normally or stops, depending \r\n        on DBG_WWDG_STOP configuration bit in DBG module, accessible through\r\n        __HAL_DBGMCU_FREEZE_WWDG() and __HAL_DBGMCU_UNFREEZE_WWDG() macros\r\n\r\n                     ##### How to use this driver #####\r\n  ==============================================================================\r\n  [..]\r\n    (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().\r\n\r\n    (+) Set the WWDG prescaler, refresh window, counter value and Early Wakeup \r\n        Interrupt mode using using HAL_WWDG_Init() function.\r\n        This enables WWDG peripheral and the downcounter starts downcounting \r\n        from given counter value.\r\n        Init function can be called again to modify all watchdog parameters, \r\n        however if EWI mode has been set once, it can't be clear until next \r\n        reset.\r\n\r\n    (+) The application program must refresh the WWDG counter at regular\r\n        intervals during normal operation to prevent an MCU reset using\r\n        HAL_WWDG_Refresh() function. This operation must occur only when\r\n        the counter is lower than the window value already programmed.\r\n\r\n    (+) if Early Wakeup Interrupt mode is enable an interrupt is generated when \r\n        the counter reaches 0x40. User can add his own code in weak function \r\n        HAL_WWDG_EarlyWakeupCallback().\r\n\r\n     *** WWDG HAL driver macros list ***\r\n     ==================================\r\n     [..]\r\n       Below the list of most used macros in WWDG HAL driver.\r\n\r\n      (+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source.\r\n      (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status.\r\n      (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags.\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_WWDG_MODULE_ENABLED\r\n/** @defgroup WWDG WWDG\r\n  * @brief WWDG HAL module driver.\r\n  * @{\r\n  */\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @defgroup WWDG_Exported_Functions WWDG Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions\r\n *  @brief    Initialization and Configuration functions.\r\n *\r\n@verbatim\r\n  ==============================================================================\r\n          ##### Initialization and Configuration functions #####\r\n  ==============================================================================\r\n  [..]  \r\n    This section provides functions allowing to:\r\n      (+) Initialize and start the WWDG according to the specified parameters\r\n          in the WWDG_InitTypeDef of associated handle.\r\n      (+) Initialize the WWDG MSP.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initialize the WWDG according to the specified.\r\n  *         parameters in the WWDG_InitTypeDef of  associated handle.\r\n  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified WWDG module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)\r\n{\r\n  /* Check the WWDG handle allocation */\r\n  if(hwwdg == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));\r\n  assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));\r\n  assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));\r\n  assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));\r\n  assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));\r\n\r\n  /* Init the low level hardware */\r\n  HAL_WWDG_MspInit(hwwdg);\r\n\r\n  /* Set WWDG Counter */\r\n  WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));\r\n\r\n  /* Set WWDG Prescaler and Window */\r\n  WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window));\r\n\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Initialize the WWDG MSP.\r\n  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified WWDG module.\r\n  * @note   When rewriting this function in user file, mechanism may be added\r\n  *         to avoid multiple initialize when HAL_WWDG_Init function is called\r\n  *         again to change parameters.\r\n  * @retval None\r\n  */\r\n__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hwwdg);\r\n\r\n  /* NOTE: This function should not be modified, when the callback is needed,\r\n           the HAL_WWDG_MspInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions\r\n *  @brief    IO operation functions \r\n *\r\n@verbatim\r\n  ==============================================================================\r\n                      ##### IO operation functions #####\r\n  ==============================================================================  \r\n  [..]\r\n    This section provides functions allowing to:\r\n    (+) Refresh the WWDG.\r\n    (+) Handle WWDG interrupt request and associated function callback.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Refresh the WWDG.\r\n  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified WWDG module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg)\r\n{\r\n  /* Write to WWDG CR the WWDG Counter value to refresh with */\r\n  WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter));\r\n\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Handle WWDG interrupt request.\r\n  * @note   The Early Wakeup Interrupt (EWI) can be used if specific safety operations\r\n  *         or data logging must be performed before the actual reset is generated.\r\n  *         The EWI interrupt is enabled by calling HAL_WWDG_Init function with \r\n  *         EWIMode set to WWDG_EWI_ENABLE.\r\n  *         When the downcounter reaches the value 0x40, and EWI interrupt is\r\n  *         generated and the corresponding Interrupt Service Routine (ISR) can\r\n  *         be used to trigger specific actions (such as communications or data\r\n  *         logging), before resetting the device.\r\n  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified WWDG module.\r\n  * @retval None\r\n  */\r\nvoid HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)\r\n{\r\n  /* Check if Early Wakeup Interrupt is enable */\r\n  if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)\r\n  {\r\n    /* Check if WWDG Early Wakeup Interrupt occurred */\r\n    if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)\r\n    {\r\n      /* Clear the WWDG Early Wakeup flag */\r\n      __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);\r\n\r\n      /* Early Wakeup callback */ \r\n      HAL_WWDG_EarlyWakeupCallback(hwwdg);\r\n    }\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  * @brief  WWDG Early Wakeup callback.\r\n  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified WWDG module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hwwdg);\r\n\r\n  /* NOTE: This function should not be modified, when the callback is needed,\r\n           the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_WWDG_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_ll_sdmmc.c\r\n  * @author  MCD Application Team\r\n  * @brief   SDMMC Low Layer HAL module driver.\r\n  *    \r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the SDMMC peripheral:\r\n  *           + Initialization/de-initialization functions\r\n  *           + I/O operation functions\r\n  *           + Peripheral Control functions \r\n  *           + Peripheral State functions\r\n  *         \r\n  @verbatim\r\n  ==============================================================================\r\n                       ##### SDMMC peripheral features #####\r\n  ==============================================================================        \r\n    [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the APB2\r\n         peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA\r\n         devices.\r\n    \r\n    [..] The SDMMC features include the following:\r\n         (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support\r\n             for three different databus modes: 1-bit (default), 4-bit and 8-bit\r\n         (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility)\r\n         (+) Full compliance with SD Memory Card Specifications Version 2.0\r\n         (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two\r\n             different data bus modes: 1-bit (default) and 4-bit\r\n         (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol\r\n             Rev1.1)\r\n         (+) Data transfer up to 48 MHz for the 8 bit mode\r\n         (+) Data and command output enable signals to control external bidirectional drivers.\r\n                 \r\n   \r\n                           ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]\r\n      This driver is a considered as a driver of service for external devices drivers \r\n      that interfaces with the SDMMC peripheral.\r\n      According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs \r\n      is used in the device's driver to perform SDMMC operations and functionalities.\r\n   \r\n      This driver is almost transparent for the final user, it is only used to implement other\r\n      functionalities of the external device.\r\n   \r\n    [..]\r\n      (+) The SDMMC clock (SDMMCCLK = 48 MHz) is coming from a specific output of PLL \r\n          (PLL48CLK). Before start working with SDMMC peripheral make sure that the\r\n          PLL is well configured.\r\n          The SDMMC peripheral uses two clock signals:\r\n          (++) SDMMC adapter clock (SDMMCCLK = 48 MHz)\r\n          (++) APB2 bus clock (PCLK2)\r\n       \r\n          -@@- PCLK2 and SDMMC_CK clock frequencies must respect the following condition:\r\n               Frequency(PCLK2) >= (3 / 8 x Frequency(SDMMC_CK))\r\n  \r\n      (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC\r\n          peripheral.\r\n\r\n      (+) Enable the Power ON State using the SDMMC_PowerState_ON(SDMMCx) \r\n          function and disable it using the function SDMMC_PowerState_OFF(SDMMCx).\r\n                \r\n      (+) Enable/Disable the clock using the __SDMMC_ENABLE()/__SDMMC_DISABLE() macros.\r\n  \r\n      (+) Enable/Disable the peripheral interrupts using the macros __SDMMC_ENABLE_IT(hSDMMC, IT) \r\n          and __SDMMC_DISABLE_IT(hSDMMC, IT) if you need to use interrupt mode. \r\n  \r\n      (+) When using the DMA mode \r\n          (++) Configure the DMA in the MSP layer of the external device\r\n          (++) Active the needed channel Request \r\n          (++) Enable the DMA using __SDMMC_DMA_ENABLE() macro or Disable it using the macro\r\n               __SDMMC_DMA_DISABLE().\r\n  \r\n      (+) To control the CPSM (Command Path State Machine) and send \r\n          commands to the card use the SDMMC_SendCommand(SDMMCx), \r\n          SDMMC_GetCommandResponse() and SDMMC_GetResponse() functions. First, user has\r\n          to fill the command structure (pointer to SDMMC_CmdInitTypeDef) according \r\n          to the selected command to be sent.\r\n          The parameters that should be filled are:\r\n           (++) Command Argument\r\n           (++) Command Index\r\n           (++) Command Response type\r\n           (++) Command Wait\r\n           (++) CPSM Status (Enable or Disable).\r\n  \r\n          -@@- To check if the command is well received, read the SDMMC_CMDRESP\r\n              register using the SDMMC_GetCommandResponse().\r\n              The SDMMC responses registers (SDMMC_RESP1 to SDMMC_RESP2), use the\r\n              SDMMC_GetResponse() function.\r\n  \r\n      (+) To control the DPSM (Data Path State Machine) and send/receive \r\n           data to/from the card use the SDMMC_DataConfig(), SDMMC_GetDataCounter(), \r\n          SDMMC_ReadFIFO(), SDMMC_WriteFIFO() and SDMMC_GetFIFOCount() functions.\r\n  \r\n    *** Read Operations ***\r\n    =======================\r\n    [..]\r\n      (#) First, user has to fill the data structure (pointer to\r\n          SDMMC_DataInitTypeDef) according to the selected data type to be received.\r\n          The parameters that should be filled are:\r\n           (++) Data TimeOut\r\n           (++) Data Length\r\n           (++) Data Block size\r\n           (++) Data Transfer direction: should be from card (To SDMMC)\r\n           (++) Data Transfer mode\r\n           (++) DPSM Status (Enable or Disable)\r\n                                     \r\n      (#) Configure the SDMMC resources to receive the data from the card\r\n          according to selected transfer mode (Refer to Step 8, 9 and 10).\r\n  \r\n      (#) Send the selected Read command (refer to step 11).\r\n                    \r\n      (#) Use the SDMMC flags/interrupts to check the transfer status.\r\n  \r\n    *** Write Operations ***\r\n    ========================\r\n    [..]\r\n     (#) First, user has to fill the data structure (pointer to\r\n         SDMMC_DataInitTypeDef) according to the selected data type to be received.\r\n         The parameters that should be filled are:\r\n          (++) Data TimeOut\r\n          (++) Data Length\r\n          (++) Data Block size\r\n          (++) Data Transfer direction:  should be to card (To CARD)\r\n          (++) Data Transfer mode\r\n          (++) DPSM Status (Enable or Disable)\r\n  \r\n     (#) Configure the SDMMC resources to send the data to the card according to \r\n         selected transfer mode.\r\n                     \r\n     (#) Send the selected Write command.\r\n                    \r\n     (#) Use the SDMMC flags/interrupts to check the transfer status.\r\n       \r\n    *** Command management operations ***\r\n    =====================================\r\n    [..]\r\n     (#) The commands used for Read/Write//Erase operations are managed in \r\n         separate functions. \r\n         Each function allows to send the needed command with the related argument,\r\n         then check the response.\r\n         By the same approach, you could implement a command and check the response.\r\n  \r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup SDMMC_LL SDMMC Low Layer\r\n  * @brief Low layer module for SD\r\n  * @{\r\n  */\r\n\r\n#if defined (HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED)\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\nstatic uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx);\r\nstatic uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout);\r\nstatic uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx);\r\nstatic uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx);\r\nstatic uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx);\r\nstatic uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA);\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions \r\n *  @brief    Initialization and Configuration functions \r\n *\r\n@verbatim    \r\n ===============================================================================\r\n              ##### Initialization/de-initialization functions #####\r\n ===============================================================================\r\n    [..]  This section provides functions allowing to:\r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the SDMMC according to the specified\r\n  *         parameters in the SDMMC_InitTypeDef and create the associated handle.\r\n  * @param  SDMMCx Pointer to SDMMC register base\r\n  * @param  Init SDMMC initialization structure   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init)\r\n{\r\n  uint32_t tmpreg = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_SDMMC_ALL_INSTANCE(SDMMCx));\r\n  assert_param(IS_SDMMC_CLOCK_EDGE(Init.ClockEdge)); \r\n  assert_param(IS_SDMMC_CLOCK_BYPASS(Init.ClockBypass));\r\n  assert_param(IS_SDMMC_CLOCK_POWER_SAVE(Init.ClockPowerSave));\r\n  assert_param(IS_SDMMC_BUS_WIDE(Init.BusWide));\r\n  assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));\r\n  assert_param(IS_SDMMC_CLKDIV(Init.ClockDiv));\r\n  \r\n  /* Set SDMMC configuration parameters */\r\n  tmpreg |= (Init.ClockEdge           |\\\r\n             Init.ClockBypass         |\\\r\n             Init.ClockPowerSave      |\\\r\n             Init.BusWide             |\\\r\n             Init.HardwareFlowControl |\\\r\n             Init.ClockDiv\r\n             ); \r\n  \r\n  /* Write to SDMMC CLKCR */\r\n  MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, tmpreg);  \r\n\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_SDMMC_LL_Group2 IO operation functions \r\n *  @brief   Data transfers functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                      ##### I/O operation functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides a set of functions allowing to manage the SDMMC data \r\n    transfers.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Read data (word) from Rx FIFO in blocking mode (polling) \r\n  * @param  SDMMCx Pointer to SDMMC register base\r\n  * @retval HAL status\r\n  */\r\nuint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx)\r\n{\r\n  /* Read data from Rx FIFO */ \r\n  return (SDMMCx->FIFO);\r\n}\r\n\r\n/**\r\n  * @brief  Write data (word) to Tx FIFO in blocking mode (polling) \r\n  * @param  SDMMCx Pointer to SDMMC register base\r\n  * @param  pWriteData pointer to data to write\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData)\r\n{ \r\n  /* Write data to FIFO */ \r\n  SDMMCx->FIFO = *pWriteData;\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions \r\n *  @brief   management functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                      ##### Peripheral Control functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides a set of functions allowing to control the SDMMC data \r\n    transfers.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Set SDMMC Power state to ON. \r\n  * @param  SDMMCx Pointer to SDMMC register base\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx)\r\n{  \r\n  /* Set power state to ON */ \r\n  SDMMCx->POWER = SDMMC_POWER_PWRCTRL;\r\n  \r\n  return HAL_OK; \r\n}\r\n\r\n/**\r\n  * @brief  Set SDMMC Power state to OFF. \r\n  * @param  SDMMCx Pointer to SDMMC register base\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx)\r\n{\r\n  /* Set power state to OFF */\r\n  SDMMCx->POWER = (uint32_t)0x00000000;\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Get SDMMC Power state. \r\n  * @param  SDMMCx Pointer to SDMMC register base\r\n  * @retval Power status of the controller. The returned value can be one of the \r\n  *         following values:\r\n  *            - 0x00: Power OFF\r\n  *            - 0x02: Power UP\r\n  *            - 0x03: Power ON \r\n  */\r\nuint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx)  \r\n{\r\n  return (SDMMCx->POWER & SDMMC_POWER_PWRCTRL);\r\n}\r\n\r\n/**\r\n  * @brief  Configure the SDMMC command path according to the specified parameters in\r\n  *         SDMMC_CmdInitTypeDef structure and send the command \r\n  * @param  SDMMCx Pointer to SDMMC register base\r\n  * @param  Command pointer to a SDMMC_CmdInitTypeDef structure that contains \r\n  *         the configuration information for the SDMMC command\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command)\r\n{\r\n  uint32_t tmpreg = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_SDMMC_CMD_INDEX(Command->CmdIndex));\r\n  assert_param(IS_SDMMC_RESPONSE(Command->Response));\r\n  assert_param(IS_SDMMC_WAIT(Command->WaitForInterrupt));\r\n  assert_param(IS_SDMMC_CPSM(Command->CPSM));\r\n\r\n  /* Set the SDMMC Argument value */\r\n  SDMMCx->ARG = Command->Argument;\r\n\r\n  /* Set SDMMC command parameters */\r\n  tmpreg |= (uint32_t)(Command->CmdIndex         |\\\r\n                       Command->Response         |\\\r\n                       Command->WaitForInterrupt |\\\r\n                       Command->CPSM);\r\n  \r\n  /* Write to SDMMC CMD register */\r\n  MODIFY_REG(SDMMCx->CMD, CMD_CLEAR_MASK, tmpreg); \r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Return the command index of last command for which response received\r\n  * @param  SDMMCx Pointer to SDMMC register base\r\n  * @retval Command index of the last command response received\r\n  */\r\nuint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx)\r\n{\r\n  return (uint8_t)(SDMMCx->RESPCMD);\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Return the response received from the card for the last command\r\n  * @param  SDMMCx Pointer to SDMMC register base    \r\n  * @param  Response Specifies the SDMMC response register. \r\n  *          This parameter can be one of the following values:\r\n  *            @arg SDMMC_RESP1: Response Register 1\r\n  *            @arg SDMMC_RESP2: Response Register 2\r\n  *            @arg SDMMC_RESP3: Response Register 3\r\n  *            @arg SDMMC_RESP4: Response Register 4  \r\n  * @retval The Corresponding response register value\r\n  */\r\nuint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response)\r\n{\r\n  __IO uint32_t tmp = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_SDMMC_RESP(Response));\r\n  \r\n  /* Get the response */\r\n  tmp = (uint32_t)&(SDMMCx->RESP1) + Response;\r\n  \r\n  return (*(__IO uint32_t *) tmp);\r\n}  \r\n\r\n/**\r\n  * @brief  Configure the SDMMC data path according to the specified \r\n  *         parameters in the SDMMC_DataInitTypeDef.\r\n  * @param  SDMMCx Pointer to SDMMC register base  \r\n  * @param  Data  pointer to a SDMMC_DataInitTypeDef structure \r\n  *         that contains the configuration information for the SDMMC data.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data)\r\n{\r\n  uint32_t tmpreg = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_SDMMC_DATA_LENGTH(Data->DataLength));\r\n  assert_param(IS_SDMMC_BLOCK_SIZE(Data->DataBlockSize));\r\n  assert_param(IS_SDMMC_TRANSFER_DIR(Data->TransferDir));\r\n  assert_param(IS_SDMMC_TRANSFER_MODE(Data->TransferMode));\r\n  assert_param(IS_SDMMC_DPSM(Data->DPSM));\r\n\r\n  /* Set the SDMMC Data TimeOut value */\r\n  SDMMCx->DTIMER = Data->DataTimeOut;\r\n\r\n  /* Set the SDMMC DataLength value */\r\n  SDMMCx->DLEN = Data->DataLength;\r\n\r\n  /* Set the SDMMC data configuration parameters */\r\n  tmpreg |= (uint32_t)(Data->DataBlockSize |\\\r\n                       Data->TransferDir   |\\\r\n                       Data->TransferMode  |\\\r\n                       Data->DPSM);\r\n  \r\n  /* Write to SDMMC DCTRL */\r\n  MODIFY_REG(SDMMCx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);\r\n\r\n  return HAL_OK;\r\n\r\n}\r\n\r\n/**\r\n  * @brief  Returns number of remaining data bytes to be transferred.\r\n  * @param  SDMMCx Pointer to SDMMC register base\r\n  * @retval Number of remaining data bytes to be transferred\r\n  */\r\nuint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx)\r\n{\r\n  return (SDMMCx->DCOUNT);\r\n}\r\n\r\n/**\r\n  * @brief  Get the FIFO data\r\n  * @param  SDMMCx Pointer to SDMMC register base \r\n  * @retval Data received\r\n  */\r\nuint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx)\r\n{\r\n  return (SDMMCx->FIFO);\r\n}\r\n\r\n/**\r\n  * @brief  Sets one of the two options of inserting read wait interval.\r\n  * @param  SDMMCx Pointer to SDMMC register base   \r\n  * @param  SDMMC_ReadWaitMode SDMMC Read Wait operation mode.\r\n  *          This parameter can be:\r\n  *            @arg SDMMC_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK\r\n  *            @arg SDMMC_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2\r\n  * @retval None\r\n  */\r\nHAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_SDMMC_READWAIT_MODE(SDMMC_ReadWaitMode));\r\n\r\n  /* Set SDMMC read wait mode */\r\n  MODIFY_REG(SDMMCx->DCTRL, SDMMC_DCTRL_RWMOD, SDMMC_ReadWaitMode);\r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup HAL_SDMMC_LL_Group4 Command management functions \r\n *  @brief   Data transfers functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                   ##### Commands management functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides a set of functions allowing to manage the needed commands.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Send the Data Block Lenght command and check the response\r\n  * @param  SDMMCx Pointer to SDMMC register base \r\n  * @retval HAL status\r\n  */\r\nuint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize)\r\n{\r\n  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;\r\n  uint32_t errorstate = SDMMC_ERROR_NONE;\r\n  \r\n  /* Set Block Size for Card */ \r\n  sdmmc_cmdinit.Argument         = (uint32_t)BlockSize;\r\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_BLOCKLEN;\r\n  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;\r\n  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_BLOCKLEN, SDMMC_CMDTIMEOUT);\r\n\r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Send the Read Single Block command and check the response\r\n  * @param  SDMMCx Pointer to SDMMC register base \r\n  * @retval HAL status\r\n  */\r\nuint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd)\r\n{\r\n  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;\r\n  uint32_t errorstate = SDMMC_ERROR_NONE;\r\n  \r\n  /* Set Block Size for Card */ \r\n  sdmmc_cmdinit.Argument         = (uint32_t)ReadAdd;\r\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_READ_SINGLE_BLOCK;\r\n  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;\r\n  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_SINGLE_BLOCK, SDMMC_CMDTIMEOUT);\r\n\r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Send the Read Multi Block command and check the response\r\n  * @param  SDMMCx Pointer to SDMMC register base \r\n  * @retval HAL status\r\n  */\r\nuint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd)\r\n{\r\n  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;\r\n  uint32_t errorstate = SDMMC_ERROR_NONE;\r\n  \r\n  /* Set Block Size for Card */ \r\n  sdmmc_cmdinit.Argument         = (uint32_t)ReadAdd;\r\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_READ_MULT_BLOCK;\r\n  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;\r\n  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_MULT_BLOCK, SDMMC_CMDTIMEOUT);\r\n\r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Send the Write Single Block command and check the response\r\n  * @param  SDMMCx Pointer to SDMMC register base \r\n  * @retval HAL status\r\n  */\r\nuint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd)\r\n{\r\n  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;\r\n  uint32_t errorstate = SDMMC_ERROR_NONE;\r\n  \r\n  /* Set Block Size for Card */ \r\n  sdmmc_cmdinit.Argument         = (uint32_t)WriteAdd;\r\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_WRITE_SINGLE_BLOCK;\r\n  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;\r\n  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDMMC_CMDTIMEOUT);\r\n\r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Send the Write Multi Block command and check the response\r\n  * @param  SDMMCx Pointer to SDMMC register base \r\n  * @retval HAL status\r\n  */\r\nuint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd)\r\n{\r\n  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;\r\n  uint32_t errorstate = SDMMC_ERROR_NONE;\r\n  \r\n  /* Set Block Size for Card */ \r\n  sdmmc_cmdinit.Argument         = (uint32_t)WriteAdd;\r\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_WRITE_MULT_BLOCK;\r\n  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;\r\n  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_MULT_BLOCK, SDMMC_CMDTIMEOUT);\r\n\r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Send the Start Address Erase command for SD and check the response\r\n  * @param  SDMMCx Pointer to SDMMC register base \r\n  * @retval HAL status\r\n  */\r\nuint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd)\r\n{\r\n  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;\r\n  uint32_t errorstate = SDMMC_ERROR_NONE;\r\n  \r\n  /* Set Block Size for Card */ \r\n  sdmmc_cmdinit.Argument         = (uint32_t)StartAdd;\r\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_ERASE_GRP_START;\r\n  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;\r\n  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_START, SDMMC_CMDTIMEOUT);\r\n\r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Send the End Address Erase command for SD and check the response\r\n  * @param  SDMMCx Pointer to SDMMC register base \r\n  * @retval HAL status\r\n  */\r\nuint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd)\r\n{\r\n  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;\r\n  uint32_t errorstate = SDMMC_ERROR_NONE;\r\n  \r\n  /* Set Block Size for Card */ \r\n  sdmmc_cmdinit.Argument         = (uint32_t)EndAdd;\r\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_ERASE_GRP_END;\r\n  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;\r\n  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_END, SDMMC_CMDTIMEOUT);\r\n\r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Send the Start Address Erase command and check the response\r\n  * @param  SDMMCx Pointer to SDMMC register base \r\n  * @retval HAL status\r\n  */\r\nuint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd)\r\n{\r\n  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;\r\n  uint32_t errorstate = SDMMC_ERROR_NONE;\r\n  \r\n  /* Set Block Size for Card */ \r\n  sdmmc_cmdinit.Argument         = (uint32_t)StartAdd;\r\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE_GRP_START;\r\n  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;\r\n  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_START, SDMMC_CMDTIMEOUT);\r\n\r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Send the End Address Erase command and check the response\r\n  * @param  SDMMCx Pointer to SDMMC register base \r\n  * @retval HAL status\r\n  */\r\nuint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd)\r\n{\r\n  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;\r\n  uint32_t errorstate = SDMMC_ERROR_NONE;\r\n  \r\n  /* Set Block Size for Card */ \r\n  sdmmc_cmdinit.Argument         = (uint32_t)EndAdd;\r\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE_GRP_END;\r\n  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;\r\n  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_END, SDMMC_CMDTIMEOUT);\r\n\r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Send the Erase command and check the response\r\n  * @param  SDMMCx Pointer to SDMMC register base \r\n  * @retval HAL status\r\n  */\r\nuint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx)\r\n{\r\n  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;\r\n  uint32_t errorstate = SDMMC_ERROR_NONE;\r\n  \r\n  /* Set Block Size for Card */ \r\n  sdmmc_cmdinit.Argument         = 0;\r\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE;\r\n  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;\r\n  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE, SDMMC_MAXERASETIMEOUT);\r\n\r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Send the Stop Transfer command and check the response.\r\n  * @param  SDMMCx Pointer to SDMMC register base \r\n  * @retval HAL status\r\n  */\r\nuint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx)\r\n{\r\n  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;\r\n  uint32_t errorstate = SDMMC_ERROR_NONE;\r\n  \r\n  /* Send CMD12 STOP_TRANSMISSION  */\r\n  sdmmc_cmdinit.Argument         = 0;\r\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_STOP_TRANSMISSION;\r\n  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;\r\n  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_STOP_TRANSMISSION, 100000000/*SDMMC_CMDTIMEOUT*/);\r\n\r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Send the Select Deselect command and check the response.\r\n  * @param  SDMMCx Pointer to SDMMC register base \r\n  * @param  addr Address of the card to be selected  \r\n  * @retval HAL status\r\n  */\r\nuint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr)\r\n{\r\n  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;\r\n  uint32_t errorstate = SDMMC_ERROR_NONE;\r\n  \r\n  /* Send CMD7 SDMMC_SEL_DESEL_CARD */\r\n  sdmmc_cmdinit.Argument         = (uint32_t)Addr;\r\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEL_DESEL_CARD;\r\n  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;\r\n  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEL_DESEL_CARD, SDMMC_CMDTIMEOUT);\r\n\r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Send the Go Idle State command and check the response.\r\n  * @param  SDMMCx Pointer to SDMMC register base \r\n  * @retval HAL status\r\n  */\r\nuint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx)\r\n{\r\n  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;\r\n  uint32_t errorstate = SDMMC_ERROR_NONE;\r\n  \r\n  sdmmc_cmdinit.Argument         = 0;\r\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_GO_IDLE_STATE;\r\n  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_NO;\r\n  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SDMMC_GetCmdError(SDMMCx);\r\n\r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Send the Operating Condition command and check the response.\r\n  * @param  SDMMCx Pointer to SDMMC register base \r\n  * @retval HAL status\r\n  */\r\nuint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx)\r\n{\r\n  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;\r\n  uint32_t errorstate = SDMMC_ERROR_NONE;\r\n  \r\n  /* Send CMD8 to verify SD card interface operating condition */\r\n  /* Argument: - [31:12]: Reserved (shall be set to '0')\r\n  - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)\r\n  - [7:0]: Check Pattern (recommended 0xAA) */\r\n  /* CMD Response: R7 */\r\n  sdmmc_cmdinit.Argument         = SDMMC_CHECK_PATTERN;\r\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_HS_SEND_EXT_CSD;\r\n  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;\r\n  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SDMMC_GetCmdResp7(SDMMCx);\r\n\r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Send the Application command to verify that that the next command \r\n  *         is an application specific com-mand rather than a standard command\r\n  *         and check the response.\r\n  * @param  SDMMCx Pointer to SDMMC register base \r\n  * @retval HAL status\r\n  */\r\nuint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument)\r\n{\r\n  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;\r\n  uint32_t errorstate = SDMMC_ERROR_NONE;\r\n  \r\n  sdmmc_cmdinit.Argument         = (uint32_t)Argument;\r\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_APP_CMD;\r\n  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;\r\n  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);\r\n  \r\n  /* Check for error conditions */\r\n  /* If there is a HAL_ERROR, it is a MMC card, else\r\n  it is a SD card: SD card 2.0 (voltage range mismatch)\r\n     or SD card 1.x */\r\n  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_CMD, SDMMC_CMDTIMEOUT);\r\n\r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Send the command asking the accessed card to send its operating \r\n  *         condition register (OCR)\r\n  * @param  SDMMCx Pointer to SDMMC register base \r\n  * @retval HAL status\r\n  */\r\nuint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t SdType)\r\n{\r\n  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;\r\n  uint32_t errorstate = SDMMC_ERROR_NONE;\r\n  \r\n  sdmmc_cmdinit.Argument         = SDMMC_VOLTAGE_WINDOW_SD | SdType;\r\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_OP_COND;\r\n  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;\r\n  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SDMMC_GetCmdResp3(SDMMCx);\r\n\r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Send the Bus Width command and check the response.\r\n  * @param  SDMMCx Pointer to SDMMC register base \r\n  * @retval HAL status\r\n  */\r\nuint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth)\r\n{\r\n  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;\r\n  uint32_t errorstate = SDMMC_ERROR_NONE;\r\n  \r\n  sdmmc_cmdinit.Argument         = (uint32_t)BusWidth;\r\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_APP_SD_SET_BUSWIDTH;\r\n  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;\r\n  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDMMC_CMDTIMEOUT);\r\n\r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Send the Send SCR command and check the response.\r\n  * @param  SDMMCx Pointer to SDMMC register base \r\n  * @retval HAL status\r\n  */\r\nuint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx)\r\n{\r\n  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;\r\n  uint32_t errorstate = SDMMC_ERROR_NONE;\r\n  \r\n  /* Send CMD51 SD_APP_SEND_SCR */\r\n  sdmmc_cmdinit.Argument         = 0;\r\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_SEND_SCR;\r\n  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;\r\n  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_SEND_SCR, SDMMC_CMDTIMEOUT);\r\n\r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Send the Send CID command and check the response.\r\n  * @param  SDMMCx Pointer to SDMMC register base \r\n  * @retval HAL status\r\n  */\r\nuint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx)\r\n{\r\n  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;\r\n  uint32_t errorstate = SDMMC_ERROR_NONE;\r\n  \r\n  /* Send CMD2 ALL_SEND_CID */\r\n  sdmmc_cmdinit.Argument         = 0;\r\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ALL_SEND_CID;\r\n  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_LONG;\r\n  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SDMMC_GetCmdResp2(SDMMCx);\r\n\r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Send the Send CSD command and check the response.\r\n  * @param  SDMMCx Pointer to SDMMC register base \r\n  * @retval HAL status\r\n  */\r\nuint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument)\r\n{\r\n  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;\r\n  uint32_t errorstate = SDMMC_ERROR_NONE;\r\n  \r\n  /* Send CMD9 SEND_CSD */\r\n  sdmmc_cmdinit.Argument         = (uint32_t)Argument;\r\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_CSD;\r\n  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_LONG;\r\n  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SDMMC_GetCmdResp2(SDMMCx);\r\n\r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Send the Send CSD command and check the response.\r\n  * @param  SDMMCx Pointer to SDMMC register base \r\n  * @retval HAL status\r\n  */\r\nuint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA)\r\n{\r\n  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;\r\n  uint32_t errorstate = SDMMC_ERROR_NONE;\r\n  \r\n  /* Send CMD3 SD_CMD_SET_REL_ADDR */\r\n  sdmmc_cmdinit.Argument         = 0;\r\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_REL_ADDR;\r\n  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;\r\n  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SDMMC_GetCmdResp6(SDMMCx, SDMMC_CMD_SET_REL_ADDR, pRCA);\r\n\r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Send the Status command and check the response.\r\n  * @param  SDMMCx Pointer to SDMMC register base \r\n  * @retval HAL status\r\n  */\r\nuint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument)\r\n{\r\n  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;\r\n  uint32_t errorstate = SDMMC_ERROR_NONE;\r\n  \r\n  sdmmc_cmdinit.Argument         = (uint32_t)Argument;\r\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_STATUS;\r\n  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;\r\n  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEND_STATUS, SDMMC_CMDTIMEOUT);\r\n\r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Send the Status register command and check the response.\r\n  * @param  SDMMCx Pointer to SDMMC register base \r\n  * @retval HAL status\r\n  */\r\nuint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx)\r\n{\r\n  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;\r\n  uint32_t errorstate = SDMMC_ERROR_NONE;\r\n  \r\n  sdmmc_cmdinit.Argument         = 0;\r\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_STATUS;\r\n  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;\r\n  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_STATUS, SDMMC_CMDTIMEOUT);\r\n\r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Sends host capacity support information and activates the card's \r\n  *         initialization process. Send SDMMC_CMD_SEND_OP_COND command\r\n  * @param  SDIOx Pointer to SDIO register base \r\n  * @parame Argument Argument used for the command\r\n  * @retval HAL status\r\n  */\r\nuint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument)\r\n{\r\n  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;\r\n  uint32_t errorstate = SDMMC_ERROR_NONE;\r\n  \r\n  sdmmc_cmdinit.Argument         = Argument;\r\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_OP_COND;\r\n  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;\r\n  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SDMMC_GetCmdResp3(SDMMCx);\r\n\r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH comand\r\n  * @param  SDIOx Pointer to SDIO register base \r\n  * @parame Argument Argument used for the command\r\n  * @retval HAL status\r\n  */\r\nuint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument)\r\n{\r\n  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;\r\n  uint32_t errorstate = SDMMC_ERROR_NONE;\r\n  \r\n  sdmmc_cmdinit.Argument         = Argument;\r\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_HS_SWITCH;\r\n  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;\r\n  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SWITCH, SDMMC_CMDTIMEOUT);\r\n\r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private function ----------------------------------------------------------*/  \r\n/** @addtogroup SD_Private_Functions\r\n  * @{\r\n  */\r\n    \r\n/**\r\n  * @brief  Checks for error conditions for CMD0.\r\n  * @param  hsd SD handle\r\n  * @retval SD Card error state\r\n  */\r\nstatic uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx)\r\n{\r\n  /* 8 is the number of required instructions cycles for the below loop statement.\r\n  The SDMMC_CMDTIMEOUT is expressed in ms */\r\n  register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8 /1000);\r\n  \r\n  do\r\n  {\r\n    if (count-- == 0)\r\n    {\r\n      return SDMMC_ERROR_TIMEOUT;\r\n    }\r\n    \r\n  }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDSENT));\r\n  \r\n  /* Clear all the static flags */\r\n  __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS);\r\n  \r\n  return SDMMC_ERROR_NONE;\r\n}\r\n\r\n/**\r\n  * @brief  Checks for error conditions for R1 response.\r\n  * @param  hsd SD handle\r\n  * @param  SD_CMD The sent command index  \r\n  * @retval SD Card error state\r\n  */\r\nstatic uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout)\r\n{\r\n  uint32_t response_r1;\r\n  \r\n  /* 8 is the number of required instructions cycles for the below loop statement.\r\n  The Timeout is expressed in ms */\r\n  register uint32_t count = Timeout * (SystemCoreClock / 8 /1000);\r\n  \r\n  do\r\n  {\r\n    if (count-- == 0)\r\n    {\r\n      return SDMMC_ERROR_TIMEOUT;\r\n    }\r\n    \r\n  }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT));\r\n  \r\n  if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))\r\n  {\r\n    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);\r\n    \r\n    return SDMMC_ERROR_CMD_RSP_TIMEOUT;\r\n  }\r\n  else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))\r\n  {\r\n    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);\r\n    \r\n    return SDMMC_ERROR_CMD_CRC_FAIL;\r\n  }\r\n  \r\n  /* Check response received is of desired command */\r\n  if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD)\r\n  {\r\n    return SDMMC_ERROR_CMD_CRC_FAIL;\r\n  }\r\n  \r\n  /* Clear all the static flags */\r\n  __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS);\r\n  \r\n  /* We have received response, retrieve it for analysis  */\r\n  response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1);\r\n  \r\n  if((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO)\r\n  {\r\n    return SDMMC_ERROR_NONE;\r\n  }\r\n  else if((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE)\r\n  {\r\n    return SDMMC_ERROR_ADDR_OUT_OF_RANGE;\r\n  }\r\n  else if((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED)\r\n  {\r\n    return SDMMC_ERROR_ADDR_MISALIGNED;\r\n  }\r\n  else if((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR)\r\n  {\r\n    return SDMMC_ERROR_BLOCK_LEN_ERR;\r\n  }\r\n  else if((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR)\r\n  {\r\n    return SDMMC_ERROR_ERASE_SEQ_ERR;\r\n  }\r\n  else if((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM)\r\n  {\r\n    return SDMMC_ERROR_BAD_ERASE_PARAM;\r\n  }\r\n  else if((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION)\r\n  {\r\n    return SDMMC_ERROR_WRITE_PROT_VIOLATION;\r\n  }\r\n  else if((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED)\r\n  {\r\n    return SDMMC_ERROR_LOCK_UNLOCK_FAILED;\r\n  }\r\n  else if((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED)\r\n  {\r\n    return SDMMC_ERROR_COM_CRC_FAILED;\r\n  }\r\n  else if((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD)\r\n  {\r\n    return SDMMC_ERROR_ILLEGAL_CMD;\r\n  }\r\n  else if((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED)\r\n  {\r\n    return SDMMC_ERROR_CARD_ECC_FAILED;\r\n  }\r\n  else if((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR)\r\n  {\r\n    return SDMMC_ERROR_CC_ERR;\r\n  }\r\n  else if((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN)\r\n  {\r\n    return SDMMC_ERROR_STREAM_READ_UNDERRUN;\r\n  }\r\n  else if((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN)\r\n  {\r\n    return SDMMC_ERROR_STREAM_WRITE_OVERRUN;\r\n  }\r\n  else if((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE)\r\n  {\r\n    return SDMMC_ERROR_CID_CSD_OVERWRITE;\r\n  }\r\n  else if((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP)\r\n  {\r\n    return SDMMC_ERROR_WP_ERASE_SKIP;\r\n  }\r\n  else if((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED)\r\n  {\r\n    return SDMMC_ERROR_CARD_ECC_DISABLED;\r\n  }\r\n  else if((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET)\r\n  {\r\n    return SDMMC_ERROR_ERASE_RESET;\r\n  }\r\n  else if((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR)\r\n  {\r\n    return SDMMC_ERROR_AKE_SEQ_ERR;\r\n  }\r\n  else\r\n  {\r\n    return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Checks for error conditions for R2 (CID or CSD) response.\r\n  * @param  hsd SD handle\r\n  * @retval SD Card error state\r\n  */\r\nstatic uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx)\r\n{\r\n  /* 8 is the number of required instructions cycles for the below loop statement.\r\n  The SDMMC_CMDTIMEOUT is expressed in ms */\r\n  register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8 /1000);\r\n  \r\n  do\r\n  {\r\n    if (count-- == 0)\r\n    {\r\n      return SDMMC_ERROR_TIMEOUT;\r\n    }\r\n    \r\n  }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT));\r\n    \r\n  if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))\r\n  {\r\n    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);\r\n    \r\n    return SDMMC_ERROR_CMD_RSP_TIMEOUT;\r\n  }\r\n  else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))\r\n  {\r\n    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);\r\n    \r\n    return SDMMC_ERROR_CMD_CRC_FAIL;\r\n  }\r\n  else\r\n  {\r\n    /* No error flag set */\r\n    /* Clear all the static flags */\r\n    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS);\r\n  }\r\n\r\n  return SDMMC_ERROR_NONE;\r\n}\r\n\r\n/**\r\n  * @brief  Checks for error conditions for R3 (OCR) response.\r\n  * @param  hsd SD handle\r\n  * @retval SD Card error state\r\n  */\r\nstatic uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx)\r\n{\r\n  /* 8 is the number of required instructions cycles for the below loop statement.\r\n  The SDMMC_CMDTIMEOUT is expressed in ms */\r\n  register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8 /1000);\r\n  \r\n  do\r\n  {\r\n    if (count-- == 0)\r\n    {\r\n      return SDMMC_ERROR_TIMEOUT;\r\n    }\r\n    \r\n  }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT));\r\n  \r\n  if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))\r\n  {\r\n    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);\r\n    \r\n    return SDMMC_ERROR_CMD_RSP_TIMEOUT;\r\n  }\r\n  else\r\n \r\n  {  \r\n    /* Clear all the static flags */\r\n    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS);\r\n  }\r\n  \r\n  return SDMMC_ERROR_NONE;\r\n}\r\n\r\n/**\r\n  * @brief  Checks for error conditions for R6 (RCA) response.\r\n  * @param  hsd SD handle\r\n  * @param  SD_CMD The sent command index\r\n  * @param  pRCA Pointer to the variable that will contain the SD card relative \r\n  *         address RCA   \r\n  * @retval SD Card error state\r\n  */\r\nstatic uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA)\r\n{\r\n  uint32_t response_r1;\r\n\r\n  /* 8 is the number of required instructions cycles for the below loop statement.\r\n  The SDMMC_CMDTIMEOUT is expressed in ms */\r\n  register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8 /1000);\r\n  \r\n  do\r\n  {\r\n    if (count-- == 0)\r\n    {\r\n      return SDMMC_ERROR_TIMEOUT;\r\n    }\r\n    \r\n  }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT));\r\n  \r\n  if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))\r\n  {\r\n    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);\r\n    \r\n    return SDMMC_ERROR_CMD_RSP_TIMEOUT;\r\n  }\r\n  else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))\r\n  {\r\n    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);\r\n    \r\n    return SDMMC_ERROR_CMD_CRC_FAIL;\r\n  }\r\n  \r\n  /* Check response received is of desired command */\r\n  if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD)\r\n  {\r\n    return SDMMC_ERROR_CMD_CRC_FAIL;\r\n  }\r\n  \r\n  /* Clear all the static flags */\r\n  __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS);\r\n  \r\n  /* We have received response, retrieve it.  */\r\n  response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1);\r\n  \r\n  if((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO)\r\n  {\r\n    *pRCA = (uint16_t) (response_r1 >> 16);\r\n    \r\n    return SDMMC_ERROR_NONE;\r\n  }\r\n  else if((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD)\r\n  {\r\n    return SDMMC_ERROR_ILLEGAL_CMD;\r\n  }\r\n  else if((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED)\r\n  {\r\n    return SDMMC_ERROR_COM_CRC_FAILED;\r\n  }\r\n  else\r\n  {\r\n    return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Checks for error conditions for R7 response.\r\n  * @param  hsd SD handle\r\n  * @retval SD Card error state\r\n  */\r\nstatic uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx)\r\n{\r\n  /* 8 is the number of required instructions cycles for the below loop statement.\r\n  The SDMMC_CMDTIMEOUT is expressed in ms */\r\n  register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8 /1000);\r\n  \r\n  do\r\n  {\r\n    if (count-- == 0)\r\n    {\r\n      return SDMMC_ERROR_TIMEOUT;\r\n    }\r\n    \r\n  }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT));\r\n\r\n  if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))\r\n  {\r\n    /* Card is SD V2.0 compliant */\r\n    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CMDREND);\r\n    \r\n    return SDMMC_ERROR_CMD_RSP_TIMEOUT;\r\n  }\r\n  \r\n  if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDREND))\r\n  {\r\n    /* Card is SD V2.0 compliant */\r\n    __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CMDREND);\r\n  }\r\n  \r\n  return SDMMC_ERROR_NONE;\r\n  \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* (HAL_SD_MODULE_ENABLED) */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usb.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_ll_usb.c\r\n  * @author  MCD Application Team\r\n  * @brief   USB Low Layer HAL module driver.\r\n  *\r\n  *          This file provides firmware functions to manage the following\r\n  *          functionalities of the USB Peripheral Controller:\r\n  *           + Initialization/de-initialization functions\r\n  *           + I/O operation functions\r\n  *           + Peripheral Control functions\r\n  *           + Peripheral State functions\r\n  *\r\n  @verbatim\r\n  ==============================================================================\r\n                    ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]\r\n      (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.\r\n\r\n      (#) Call USB_CoreInit() API to initialize the USB Core peripheral.\r\n\r\n      (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_LL_USB_DRIVER\r\n  * @{\r\n  */\r\n\r\n#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\r\nstatic HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);\r\n\r\n#ifdef USB_HS_PHYC\r\nstatic HAL_StatusTypeDef USB_HS_PHYCInit(USB_OTG_GlobalTypeDef *USBx);\r\n#endif\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions\r\n *  @brief    Initialization and Configuration functions\r\n *\r\n@verbatim\r\n ===============================================================================\r\n                      ##### Initialization/de-initialization functions #####\r\n ===============================================================================\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the USB Core\r\n  * @param  USBx USB Instance\r\n  * @param  cfg pointer to a USB_OTG_CfgTypeDef structure that contains\r\n  *         the configuration information for the specified USBx peripheral.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)\r\n{\r\n  if (cfg.phy_itface == USB_OTG_ULPI_PHY)\r\n  {\r\n    USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);\r\n\r\n    /* Init The ULPI Interface */\r\n    USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);\r\n\r\n    /* Select vbus source */\r\n    USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);\r\n    if(cfg.use_external_vbus == 1U)\r\n    {\r\n      USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;\r\n    }\r\n    /* Reset after a PHY select  */\r\n    (void)USB_CoreReset(USBx);\r\n  }\r\n#ifdef USB_HS_PHYC\r\n  else if (cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY)\r\n  {\r\n    USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);\r\n\r\n    /* Init The UTMI Interface */\r\n    USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);\r\n\r\n    /* Select vbus source */\r\n    USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);\r\n\r\n    /* Select UTMI Interace */\r\n    USBx->GUSBCFG &= ~ USB_OTG_GUSBCFG_ULPI_UTMI_SEL;\r\n    USBx->GCCFG |= USB_OTG_GCCFG_PHYHSEN;\r\n\r\n    /* Enables control of a High Speed USB PHY */\r\n    USB_HS_PHYCInit(USBx);\r\n\r\n    if(cfg.use_external_vbus == 1)\r\n    {\r\n      USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;\r\n    }\r\n    /* Reset after a PHY select  */\r\n    USB_CoreReset(USBx);\r\n\r\n  }\r\n#endif\r\n  else /* FS interface (embedded Phy) */\r\n  {\r\n    /* Select FS Embedded PHY */\r\n    USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;\r\n\r\n    /* Reset after a PHY select and set Host mode */\r\n    (void)USB_CoreReset(USBx);\r\n\r\n    /* Deactivate the power down*/\r\n    USBx->GCCFG = USB_OTG_GCCFG_PWRDWN;\r\n  }\r\n\r\n  if(cfg.dma_enable == 1U)\r\n  {\r\n    USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2;\r\n    USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USB_EnableGlobalInt\r\n  *         Enables the controller's Global Int in the AHB Config reg\r\n  * @param  USBx  Selected device\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USB_DisableGlobalInt\r\n  *         Disable the controller's Global Int in the AHB Config reg\r\n  * @param  USBx  Selected device\r\n  * @retval HAL status\r\n*/\r\nHAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USB_SetCurrentMode : Set functional mode\r\n  * @param  USBx  Selected device\r\n  * @param  mode   current core mode\r\n  *          This parameter can be one of these values:\r\n  *            @arg USB_DEVICE_MODE: Peripheral mode\r\n  *            @arg USB_HOST_MODE: Host mode\r\n  *            @arg USB_DRD_MODE: Dual Role Device mode\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode)\r\n{\r\n  USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);\r\n\r\n  if (mode == USB_HOST_MODE)\r\n  {\r\n    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;\r\n  }\r\n  else if (mode == USB_DEVICE_MODE)\r\n  {\r\n    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  HAL_Delay(50U);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USB_DevInit : Initializes the USB_OTG controller registers\r\n  *         for device mode\r\n  * @param  USBx  Selected device\r\n  * @param  cfg   pointer to a USB_OTG_CfgTypeDef structure that contains\r\n  *         the configuration information for the specified USBx peripheral.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n  uint32_t i;\r\n\r\n  for (i = 0U; i < 15U; i++)\r\n  {\r\n    USBx->DIEPTXF[i] = 0U;\r\n  }\r\n\r\n  /*Activate VBUS Sensing B */\r\n  USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;\r\n\r\n  if (cfg.vbus_sensing_enable == 0U)\r\n  {\r\n    /* Deactivate VBUS Sensing B */\r\n    USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;\r\n\r\n    /* B-peripheral session valid override enable*/\r\n    USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;\r\n    USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;\r\n  }\r\n\r\n  /* Restart the Phy Clock */\r\n  USBx_PCGCCTL = 0U;\r\n\r\n  /* Device mode configuration */\r\n  USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;\r\n\r\n  if(cfg.phy_itface == USB_OTG_ULPI_PHY)\r\n  {\r\n    if(cfg.speed == USB_OTG_SPEED_HIGH)\r\n    {\r\n      /* Set High speed phy */\r\n      (void)USB_SetDevSpeed (USBx, USB_OTG_SPEED_HIGH);\r\n    }\r\n    else\r\n    {\r\n      /* set High speed phy in Full speed mode */\r\n      (void)USB_SetDevSpeed (USBx, USB_OTG_SPEED_HIGH_IN_FULL);\r\n    }\r\n  }\r\n  else if(cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY)\r\n  {\r\n    if(cfg.speed == USB_OTG_SPEED_HIGH)\r\n    {\r\n      /* Set High speed phy */\r\n      (void)USB_SetDevSpeed (USBx, USB_OTG_SPEED_HIGH);\r\n    }\r\n    else\r\n    {\r\n      /* set High speed phy in Full speed mode */\r\n      (void)USB_SetDevSpeed (USBx, USB_OTG_SPEED_HIGH_IN_FULL);\r\n    }\r\n  }\r\n  else\r\n  {\r\n    /* Set Full speed phy */\r\n    (void)USB_SetDevSpeed (USBx, USB_OTG_SPEED_FULL);\r\n  }\r\n\r\n  /* Flush the FIFOs */\r\n  (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */\r\n  (void)USB_FlushRxFifo(USBx);\r\n\r\n  /* Clear all pending Device Interrupts */\r\n  USBx_DEVICE->DIEPMSK = 0U;\r\n  USBx_DEVICE->DOEPMSK = 0U;\r\n  USBx_DEVICE->DAINTMSK = 0U;\r\n\r\n  for (i = 0U; i < cfg.dev_endpoints; i++)\r\n  {\r\n    if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)\r\n    {\r\n      if (i == 0U)\r\n      {\r\n        USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;\r\n      }\r\n      else\r\n      {\r\n        USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      USBx_INEP(i)->DIEPCTL = 0U;\r\n    }\r\n\r\n    USBx_INEP(i)->DIEPTSIZ = 0U;\r\n    USBx_INEP(i)->DIEPINT  = 0xFB7FU;\r\n  }\r\n\r\n  for (i = 0U; i < cfg.dev_endpoints; i++)\r\n  {\r\n    if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)\r\n    {\r\n      if (i == 0U)\r\n      {\r\n        USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;\r\n      }\r\n      else\r\n      {\r\n        USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      USBx_OUTEP(i)->DOEPCTL = 0U;\r\n    }\r\n\r\n    USBx_OUTEP(i)->DOEPTSIZ = 0U;\r\n    USBx_OUTEP(i)->DOEPINT  = 0xFB7FU;\r\n  }\r\n\r\n  USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);\r\n\r\n  if (cfg.dma_enable == 1U)\r\n  {\r\n    /*Set threshold parameters */\r\n    USBx_DEVICE->DTHRCTL = USB_OTG_DTHRCTL_TXTHRLEN_6 |\r\n                           USB_OTG_DTHRCTL_RXTHRLEN_6;\r\n\r\n    USBx_DEVICE->DTHRCTL |= USB_OTG_DTHRCTL_RXTHREN |\r\n                            USB_OTG_DTHRCTL_ISOTHREN |\r\n                            USB_OTG_DTHRCTL_NONISOTHREN;\r\n  }\r\n\r\n  /* Disable all interrupts. */\r\n  USBx->GINTMSK = 0U;\r\n\r\n  /* Clear any pending interrupts */\r\n  USBx->GINTSTS = 0xBFFFFFFFU;\r\n\r\n  /* Enable the common interrupts */\r\n  if (cfg.dma_enable == 0U)\r\n  {\r\n    USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;\r\n  }\r\n\r\n  /* Enable interrupts matching to the Device mode ONLY */\r\n  USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |\r\n                   USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |\r\n                   USB_OTG_GINTMSK_OEPINT   | USB_OTG_GINTMSK_IISOIXFRM|\r\n                   USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM;\r\n\r\n  if(cfg.Sof_enable != 0U)\r\n  {\r\n    USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;\r\n  }\r\n\r\n  if (cfg.vbus_sensing_enable == 1U)\r\n  {\r\n    USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USB_OTG_FlushTxFifo : Flush a Tx FIFO\r\n  * @param  USBx  Selected device\r\n  * @param  num  FIFO number\r\n  *         This parameter can be a value from 1 to 15\r\n            15 means Flush all Tx FIFOs\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num)\r\n{\r\n  uint32_t count = 0U;\r\n\r\n  USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));\r\n\r\n  do\r\n  {\r\n    if (++count > 200000U)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USB_FlushRxFifo : Flush Rx FIFO\r\n  * @param  USBx  Selected device\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  uint32_t count = 0;\r\n\r\n  USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;\r\n\r\n  do\r\n  {\r\n    if (++count > 200000U)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USB_SetDevSpeed :Initializes the DevSpd field of DCFG register\r\n  *         depending the PHY type and the enumeration speed of the device.\r\n  * @param  USBx  Selected device\r\n  * @param  speed  device speed\r\n  *          This parameter can be one of these values:\r\n  *            @arg USB_OTG_SPEED_HIGH: High speed mode\r\n  *            @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode\r\n  *            @arg USB_OTG_SPEED_FULL: Full speed mode\r\n  *            @arg USB_OTG_SPEED_LOW: Low speed mode\r\n  * @retval  Hal status\r\n  */\r\nHAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n\r\n  USBx_DEVICE->DCFG |= speed;\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USB_GetDevSpeed :Return the  Dev Speed\r\n  * @param  USBx  Selected device\r\n  * @retval speed : device speed\r\n  *          This parameter can be one of these values:\r\n  *            @arg USB_OTG_SPEED_HIGH: High speed mode\r\n  *            @arg USB_OTG_SPEED_FULL: Full speed mode\r\n  *            @arg USB_OTG_SPEED_LOW: Low speed mode\r\n  */\r\nuint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n  uint8_t speed;\r\n  uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD;\r\n\r\n  if(DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)\r\n  {\r\n    speed = USB_OTG_SPEED_HIGH;\r\n  }\r\n  else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) ||\r\n      (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ))\r\n  {\r\n    speed = USB_OTG_SPEED_FULL;\r\n  }\r\n  else if (DevEnumSpeed == DSTS_ENUMSPD_LS_PHY_6MHZ)\r\n  {\r\n    speed = USB_OTG_SPEED_LOW;\r\n  }\r\n  else\r\n  {\r\n    speed = 0U;\r\n  }\r\n\r\n  return speed;\r\n}\r\n\r\n/**\r\n  * @brief  Activate and configure an endpoint\r\n  * @param  USBx  Selected device\r\n  * @param  ep pointer to endpoint structure\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n  uint32_t epnum = (uint32_t)ep->num;\r\n\r\n  if (ep->is_in == 1U)\r\n  {\r\n   USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & 0xFU));\r\n\r\n    if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U)\r\n    {\r\n      USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |\r\n                                    ((uint32_t)ep->type << 18) | (epnum << 22) |\r\n                                     USB_OTG_DIEPCTL_SD0PID_SEVNFRM |\r\n                                     USB_OTG_DIEPCTL_USBAEP;\r\n    }\r\n  }\r\n  else\r\n  {\r\n     USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & 0xFU)) << 16);\r\n\r\n    if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)\r\n    {\r\n      USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |\r\n                                    ((uint32_t)ep->type << 18) |\r\n                                     USB_OTG_DIEPCTL_SD0PID_SEVNFRM |\r\n                                     USB_OTG_DOEPCTL_USBAEP;\r\n    }\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Activate and configure a dedicated endpoint\r\n  * @param  USBx  Selected device\r\n  * @param  ep pointer to endpoint structure\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n  uint32_t epnum = (uint32_t)ep->num;\r\n\r\n  /* Read DEPCTLn register */\r\n  if (ep->is_in == 1U)\r\n  {\r\n    if (((USBx_INEP(epnum)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U)\r\n    {\r\n      USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |\r\n                                   ((uint32_t)ep->type << 18) | (epnum << 22) |\r\n                                    USB_OTG_DIEPCTL_SD0PID_SEVNFRM |\r\n                                    USB_OTG_DIEPCTL_USBAEP;\r\n    }\r\n\r\n   USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & 0xFU));\r\n  }\r\n  else\r\n  {\r\n    if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)\r\n    {\r\n      USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |\r\n                                    ((uint32_t)ep->type << 18) | (epnum << 22) |\r\n                                     USB_OTG_DOEPCTL_USBAEP;\r\n    }\r\n\r\n     USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & 0xFU)) << 16);\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  De-activate and de-initialize an endpoint\r\n  * @param  USBx  Selected device\r\n  * @param  ep pointer to endpoint structure\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n  uint32_t epnum = (uint32_t)ep->num;\r\n\r\n  /* Read DEPCTLn register */\r\n  if (ep->is_in == 1U)\r\n  {\r\n    USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & 0xFU)));\r\n    USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & 0xFU)));\r\n    USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP |\r\n                                   USB_OTG_DIEPCTL_MPSIZ |\r\n                                   USB_OTG_DIEPCTL_TXFNUM |\r\n                                   USB_OTG_DIEPCTL_SD0PID_SEVNFRM |\r\n                                   USB_OTG_DIEPCTL_EPTYP);\r\n  }\r\n  else\r\n  {\r\n    USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & 0xFU)) << 16));\r\n    USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & 0xFU)) << 16));\r\n    USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP |\r\n                                    USB_OTG_DOEPCTL_MPSIZ |\r\n                                    USB_OTG_DOEPCTL_SD0PID_SEVNFRM |\r\n                                    USB_OTG_DOEPCTL_EPTYP);\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  De-activate and de-initialize a dedicated endpoint\r\n  * @param  USBx  Selected device\r\n  * @param  ep pointer to endpoint structure\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n  uint32_t epnum = (uint32_t)ep->num;\r\n\r\n  /* Read DEPCTLn register */\r\n  if (ep->is_in == 1U)\r\n  {\r\n   USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;\r\n   USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & 0xFU)));\r\n  }\r\n  else\r\n  {\r\n     USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;\r\n     USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & 0xFU)) << 16));\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USB_EPStartXfer : setup and starts a transfer over an EP\r\n  * @param  USBx  Selected device\r\n  * @param  ep pointer to endpoint structure\r\n  * @param  dma USB dma enabled or disabled\r\n  *          This parameter can be one of these values:\r\n  *           0 : DMA feature not used\r\n  *           1 : DMA feature used\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n  uint32_t epnum = (uint32_t)ep->num;\r\n  uint16_t pktcnt;\r\n\r\n  /* IN endpoint */\r\n  if (ep->is_in == 1U)\r\n  {\r\n    /* Zero Length Packet? */\r\n    if (ep->xfer_len == 0U)\r\n    {\r\n      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);\r\n      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));\r\n      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);\r\n    }\r\n    else\r\n    {\r\n      /* Program the transfer size and packet count\r\n      * as follows: xfersize = N * maxpacket +\r\n      * short_packet pktcnt = N + (short_packet\r\n      * exist ? 1 : 0)\r\n      */\r\n      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);\r\n      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);\r\n      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19));\r\n      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);\r\n\r\n      if (ep->type == EP_TYPE_ISOC)\r\n      {\r\n        USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);\r\n        USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29));\r\n      }\r\n    }\r\n\r\n    if (dma == 1U)\r\n    {\r\n      USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);\r\n    }\r\n    else\r\n    {\r\n      if (ep->type != EP_TYPE_ISOC)\r\n      {\r\n        /* Enable the Tx FIFO Empty Interrupt for this EP */\r\n        if (ep->xfer_len > 0U)\r\n        {\r\n          USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & 0xFU);\r\n        }\r\n      }\r\n    }\r\n\r\n    if (ep->type == EP_TYPE_ISOC)\r\n    {\r\n      if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)\r\n      {\r\n        USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;\r\n      }\r\n      else\r\n      {\r\n        USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;\r\n      }\r\n    }\r\n\r\n    /* EP enable, IN data in FIFO */\r\n    USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);\r\n\r\n    if (ep->type == EP_TYPE_ISOC)\r\n    {\r\n      (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma);\r\n    }\r\n  }\r\n  else /* OUT endpoint */\r\n  {\r\n    /* Program the transfer size and packet count as follows:\r\n    * pktcnt = N\r\n    * xfersize = N * maxpacket\r\n    */\r\n    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);\r\n    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);\r\n\r\n    if (ep->xfer_len == 0U)\r\n    {\r\n      USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);\r\n      USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));\r\n    }\r\n    else\r\n    {\r\n      pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);\r\n      USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19);\r\n      USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt);\r\n    }\r\n\r\n    if (dma == 1U)\r\n    {\r\n      USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)ep->xfer_buff;\r\n    }\r\n\r\n    if (ep->type == EP_TYPE_ISOC)\r\n    {\r\n      if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)\r\n      {\r\n        USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;\r\n      }\r\n      else\r\n      {\r\n        USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;\r\n      }\r\n    }\r\n    /* EP enable */\r\n    USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USB_EP0StartXfer : setup and starts a transfer over the EP  0\r\n  * @param  USBx  Selected device\r\n  * @param  ep pointer to endpoint structure\r\n  * @param  dma USB dma enabled or disabled\r\n  *          This parameter can be one of these values:\r\n  *           0 : DMA feature not used\r\n  *           1 : DMA feature used\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n  uint32_t epnum = (uint32_t)ep->num;\r\n\r\n  /* IN endpoint */\r\n  if (ep->is_in == 1U)\r\n  {\r\n    /* Zero Length Packet? */\r\n    if (ep->xfer_len == 0U)\r\n    {\r\n      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);\r\n      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));\r\n      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);\r\n    }\r\n    else\r\n    {\r\n      /* Program the transfer size and packet count\r\n      * as follows: xfersize = N * maxpacket +\r\n      * short_packet pktcnt = N + (short_packet\r\n      * exist ? 1 : 0)\r\n      */\r\n      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);\r\n      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);\r\n\r\n      if(ep->xfer_len > ep->maxpacket)\r\n      {\r\n        ep->xfer_len = ep->maxpacket;\r\n      }\r\n      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));\r\n      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);\r\n    }\r\n\r\n    if (dma == 1U)\r\n    {\r\n      USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);\r\n    }\r\n    else\r\n    {\r\n      /* Enable the Tx FIFO Empty Interrupt for this EP */\r\n      if (ep->xfer_len > 0U)\r\n      {\r\n        USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & 0xFU);\r\n      }\r\n    }\r\n\r\n    /* EP enable, IN data in FIFO */\r\n    USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);\r\n  }\r\n  else /* OUT endpoint */\r\n  {\r\n    /* Program the transfer size and packet count as follows:\r\n    * pktcnt = N\r\n    * xfersize = N * maxpacket\r\n    */\r\n    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);\r\n    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);\r\n\r\n    if (ep->xfer_len > 0U)\r\n    {\r\n      ep->xfer_len = ep->maxpacket;\r\n    }\r\n\r\n    USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));\r\n    USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket));\r\n\r\n    if (dma == 1U)\r\n    {\r\n      USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff);\r\n    }\r\n\r\n    /* EP enable */\r\n    USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USB_WritePacket : Writes a packet into the Tx FIFO associated\r\n  *         with the EP/channel\r\n  * @param  USBx  Selected device\r\n  * @param  src   pointer to source buffer\r\n  * @param  ch_ep_num  endpoint or host channel number\r\n  * @param  len  Number of bytes to write\r\n  * @param  dma USB dma enabled or disabled\r\n  *          This parameter can be one of these values:\r\n  *           0 : DMA feature not used\r\n  *           1 : DMA feature used\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n  uint32_t *pSrc = (uint32_t *)src;\r\n  uint32_t count32b, i;\r\n\r\n  if (dma == 0U)\r\n  {\r\n    count32b =  ((uint32_t)len + 3U) / 4U;\r\n    for (i = 0U; i < count32b; i++)\r\n    {\r\n      USBx_DFIFO((uint32_t)ch_ep_num) = *((__packed uint32_t *)pSrc);\r\n      pSrc++;\r\n    }\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USB_ReadPacket : read a packet from the Tx FIFO associated\r\n  *         with the EP/channel\r\n  * @param  USBx  Selected device\r\n  * @param  dest  source pointer\r\n  * @param  len  Number of bytes to read\r\n  * @param  dma USB dma enabled or disabled\r\n  *          This parameter can be one of these values:\r\n  *           0 : DMA feature not used\r\n  *           1 : DMA feature used\r\n  * @retval pointer to destination buffer\r\n  */\r\nvoid *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n  uint32_t *pDest = (uint32_t *)dest;\r\n  uint32_t i;\r\n  uint32_t count32b = ((uint32_t)len + 3U) / 4U;\r\n\r\n  for (i = 0U; i < count32b; i++)\r\n  {\r\n    *(__packed uint32_t *)pDest = USBx_DFIFO(0U);\r\n    pDest++;\r\n  }\r\n\r\n  return ((void *)pDest);\r\n}\r\n\r\n/**\r\n  * @brief  USB_EPSetStall : set a stall condition over an EP\r\n  * @param  USBx  Selected device\r\n  * @param  ep pointer to endpoint structure\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n  uint32_t epnum = (uint32_t)ep->num;\r\n\r\n  if (ep->is_in == 1U)\r\n  {\r\n    if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U))\r\n    {\r\n      USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);\r\n    }\r\n    USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;\r\n  }\r\n  else\r\n  {\r\n    if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U))\r\n    {\r\n      USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);\r\n    }\r\n    USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USB_EPClearStall : Clear a stall condition over an EP\r\n  * @param  USBx  Selected device\r\n  * @param  ep pointer to endpoint structure\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n  uint32_t epnum = (uint32_t)ep->num;\r\n\r\n  if (ep->is_in == 1U)\r\n  {\r\n    USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;\r\n    if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))\r\n    {\r\n       USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */\r\n    }\r\n  }\r\n  else\r\n  {\r\n    USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;\r\n    if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))\r\n    {\r\n      USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */\r\n    }\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USB_StopDevice : Stop the usb device mode\r\n  * @param  USBx  Selected device\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n  uint32_t i;\r\n\r\n  /* Clear Pending interrupt */\r\n  for (i = 0U; i < 15U; i++)\r\n  {\r\n    USBx_INEP(i)->DIEPINT = 0xFB7FU;\r\n    USBx_OUTEP(i)->DOEPINT = 0xFB7FU;\r\n  }\r\n\r\n  /* Clear interrupt masks */\r\n  USBx_DEVICE->DIEPMSK  = 0U;\r\n  USBx_DEVICE->DOEPMSK  = 0U;\r\n  USBx_DEVICE->DAINTMSK = 0U;\r\n\r\n  /* Flush the FIFO */\r\n  (void)USB_FlushRxFifo(USBx);\r\n  (void)USB_FlushTxFifo(USBx ,  0x10U);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USB_SetDevAddress : Stop the usb device mode\r\n  * @param  USBx  Selected device\r\n  * @param  address  new device address to be assigned\r\n  *          This parameter can be a value from 0 to 255\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef  USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n\r\n  USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD);\r\n  USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD;\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down\r\n  * @param  USBx  Selected device\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef  USB_DevConnect (USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n\r\n  USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS;\r\n  HAL_Delay(3U);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down\r\n  * @param  USBx  Selected device\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef  USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n\r\n  USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;\r\n  HAL_Delay(3U);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USB_ReadInterrupts: return the global USB interrupt status\r\n  * @param  USBx  Selected device\r\n  * @retval HAL status\r\n  */\r\nuint32_t  USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  uint32_t tmpreg;\r\n\r\n  tmpreg = USBx->GINTSTS;\r\n  tmpreg &= USBx->GINTMSK;\r\n\r\n  return tmpreg;\r\n}\r\n\r\n/**\r\n  * @brief  USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status\r\n  * @param  USBx  Selected device\r\n  * @retval HAL status\r\n  */\r\nuint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n  uint32_t tmpreg;\r\n\r\n  tmpreg  = USBx_DEVICE->DAINT;\r\n  tmpreg &= USBx_DEVICE->DAINTMSK;\r\n\r\n  return ((tmpreg & 0xffff0000U) >> 16);\r\n}\r\n\r\n/**\r\n  * @brief  USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status\r\n  * @param  USBx  Selected device\r\n  * @retval HAL status\r\n  */\r\nuint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n  uint32_t tmpreg;\r\n\r\n  tmpreg  = USBx_DEVICE->DAINT;\r\n  tmpreg &= USBx_DEVICE->DAINTMSK;\r\n\r\n  return ((tmpreg & 0xFFFFU));\r\n}\r\n\r\n/**\r\n  * @brief  Returns Device OUT EP Interrupt register\r\n  * @param  USBx  Selected device\r\n  * @param  epnum  endpoint number\r\n  *          This parameter can be a value from 0 to 15\r\n  * @retval Device OUT EP Interrupt register\r\n  */\r\nuint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n  uint32_t tmpreg;\r\n\r\n  tmpreg  = USBx_OUTEP((uint32_t)epnum)->DOEPINT;\r\n  tmpreg &= USBx_DEVICE->DOEPMSK;\r\n\r\n  return tmpreg;\r\n}\r\n\r\n/**\r\n  * @brief  Returns Device IN EP Interrupt register\r\n  * @param  USBx  Selected device\r\n  * @param  epnum  endpoint number\r\n  *          This parameter can be a value from 0 to 15\r\n  * @retval Device IN EP Interrupt register\r\n  */\r\nuint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n  uint32_t tmpreg, msk, emp;\r\n\r\n  msk = USBx_DEVICE->DIEPMSK;\r\n  emp = USBx_DEVICE->DIEPEMPMSK;\r\n  msk |= ((emp >> (epnum & 0xFU)) & 0x1U) << 7;\r\n  tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk;\r\n\r\n  return tmpreg;\r\n}\r\n\r\n/**\r\n  * @brief  USB_ClearInterrupts: clear a USB interrupt\r\n  * @param  USBx  Selected device\r\n  * @param  interrupt  interrupt flag\r\n  * @retval None\r\n  */\r\nvoid  USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)\r\n{\r\n  USBx->GINTSTS |= interrupt;\r\n}\r\n\r\n/**\r\n  * @brief  Returns USB core mode\r\n  * @param  USBx  Selected device\r\n  * @retval return core mode : Host or Device\r\n  *          This parameter can be one of these values:\r\n  *           0 : Host\r\n  *           1 : Device\r\n  */\r\nuint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  return ((USBx->GINTSTS ) & 0x1U);\r\n}\r\n\r\n/**\r\n  * @brief  Activate EP0 for Setup transactions\r\n  * @param  USBx  Selected device\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef  USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n\r\n  /* Set the MPS of the IN EP based on the enumeration speed */\r\n  USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;\r\n\r\n  if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)\r\n  {\r\n    USBx_INEP(0U)->DIEPCTL |= 3U;\r\n  }\r\n  USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Prepare the EP0 to start the first control setup\r\n  * @param  USBx  Selected device\r\n  * @param  dma USB dma enabled or disabled\r\n  *          This parameter can be one of these values:\r\n  *           0 : DMA feature not used\r\n  *           1 : DMA feature used\r\n  * @param  psetup  pointer to setup packet\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n\r\n  USBx_OUTEP(0U)->DOEPTSIZ = 0U;\r\n  USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));\r\n  USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U);\r\n  USBx_OUTEP(0U)->DOEPTSIZ |=  USB_OTG_DOEPTSIZ_STUPCNT;\r\n\r\n  if (dma == 1U)\r\n  {\r\n    USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup;\r\n    /* EP enable */\r\n    USBx_OUTEP(0U)->DOEPCTL = 0x80008000U;\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Reset the USB Core (needed after USB clock settings change)\r\n  * @param  USBx  Selected device\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  uint32_t count = 0U;\r\n\r\n  /* Wait for AHB master IDLE state. */\r\n  do\r\n  {\r\n    if (++count > 200000U)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);\r\n\r\n  /* Core Soft Reset */\r\n  count = 0U;\r\n  USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;\r\n\r\n  do\r\n  {\r\n    if (++count > 200000U)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n#ifdef USB_HS_PHYC\r\n/**\r\n  * @brief  Enables control of a High Speed USB PHYs\r\n  *         Init the low level hardware : GPIO, CLOCK, NVIC...\r\n  * @param  USBx  Selected device\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef USB_HS_PHYCInit(USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  uint32_t count = 0U;\r\n\r\n  /* Enable LDO */\r\n  USB_HS_PHYC->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE;\r\n\r\n  /* wait for LDO Ready */\r\n  while((USB_HS_PHYC->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) == RESET)\r\n  {\r\n    if (++count > 200000U)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n\r\n  /* Controls PHY frequency operation selection */\r\n  if (HSE_VALUE == 12000000U) /* HSE = 12MHz */\r\n  {\r\n    USB_HS_PHYC->USB_HS_PHYC_PLL = (0x0U << 1);\r\n  }\r\n  else if (HSE_VALUE == 12500000U) /* HSE = 12.5MHz */\r\n  {\r\n    USB_HS_PHYC->USB_HS_PHYC_PLL = (0x2U << 1);\r\n  }\r\n  else if (HSE_VALUE == 16000000U) /* HSE = 16MHz */\r\n  {\r\n    USB_HS_PHYC->USB_HS_PHYC_PLL = (0x3U << 1);\r\n  }\r\n  else if (HSE_VALUE == 24000000U) /* HSE = 24MHz */\r\n  {\r\n    USB_HS_PHYC->USB_HS_PHYC_PLL = (0x4U << 1);\r\n  }\r\n  else if (HSE_VALUE == 25000000U) /* HSE = 25MHz */\r\n  {\r\n    USB_HS_PHYC->USB_HS_PHYC_PLL = (0x5U << 1);\r\n  }\r\n  else if (HSE_VALUE == 32000000U) /* HSE = 32MHz */\r\n  {\r\n    USB_HS_PHYC->USB_HS_PHYC_PLL = (0x7U << 1);\r\n  }\r\n\r\n  /* Control the tuning interface of the High Speed PHY */\r\n  USB_HS_PHYC->USB_HS_PHYC_TUNE |= USB_HS_PHYC_TUNE_VALUE;\r\n\r\n  /* Enable PLL internal PHY */\r\n  USB_HS_PHYC->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN;\r\n\r\n  /* 2ms Delay required to get internal phy clock stable */\r\n  HAL_Delay(2);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n#endif /* USB_HS_PHYC */\r\n/**\r\n  * @brief  USB_HostInit : Initializes the USB OTG controller registers\r\n  *         for Host mode\r\n  * @param  USBx  Selected device\r\n  * @param  cfg   pointer to a USB_OTG_CfgTypeDef structure that contains\r\n  *         the configuration information for the specified USBx peripheral.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n  uint32_t i;\r\n\r\n  /* Restart the Phy Clock */\r\n  USBx_PCGCCTL = 0U;\r\n\r\n  /* Disable VBUS sensing */\r\n  USBx->GCCFG &= ~(USB_OTG_GCCFG_VBDEN);\r\n\r\n  /* Disable the FS/LS support mode only */\r\n  if ((cfg.speed == USB_OTG_SPEED_FULL) && (USBx != USB_OTG_FS))\r\n  {\r\n    USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS;\r\n  }\r\n  else\r\n  {\r\n    USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);\r\n  }\r\n\r\n  /* Make sure the FIFOs are flushed. */\r\n  (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */\r\n  (void)USB_FlushRxFifo(USBx);\r\n\r\n  /* Clear all pending HC Interrupts */\r\n  for (i = 0U; i < cfg.Host_channels; i++)\r\n  {\r\n    USBx_HC(i)->HCINT = 0xFFFFFFFFU;\r\n    USBx_HC(i)->HCINTMSK = 0U;\r\n  }\r\n\r\n  /* Enable VBUS driving */\r\n  (void)USB_DriveVbus(USBx, 1U);\r\n\r\n  HAL_Delay(200U);\r\n\r\n  /* Disable all interrupts. */\r\n  USBx->GINTMSK = 0U;\r\n\r\n  /* Clear any pending interrupts */\r\n  USBx->GINTSTS = 0xFFFFFFFFU;\r\n\r\n  if(USBx == USB_OTG_FS)\r\n  {\r\n    /* set Rx FIFO size */\r\n    USBx->GRXFSIZ  = 0x80U;\r\n    USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U);\r\n    USBx->HPTXFSIZ = (uint32_t )(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U);\r\n  }\r\n  else\r\n  {\r\n    /* set Rx FIFO size */\r\n    USBx->GRXFSIZ  = 0x200U;\r\n    USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U);\r\n    USBx->HPTXFSIZ = (uint32_t )(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U);\r\n  }\r\n\r\n  /* Enable the common interrupts */\r\n  if (cfg.dma_enable == 0U)\r\n  {\r\n    USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;\r\n  }\r\n\r\n  /* Enable interrupts matching to the Host mode ONLY */\r\n  USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM            | USB_OTG_GINTMSK_HCIM |\\\r\n                    USB_OTG_GINTMSK_SOFM             | USB_OTG_GINTSTS_DISCINT|\\\r\n                    USB_OTG_GINTMSK_PXFRM_IISOOXFRM  | USB_OTG_GINTMSK_WUIM);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the\r\n  *         HCFG register on the PHY type and set the right frame interval\r\n  * @param  USBx  Selected device\r\n  * @param  freq  clock frequency\r\n  *          This parameter can be one of these values:\r\n  *           HCFG_48_MHZ : Full Speed 48 MHz Clock\r\n  *           HCFG_6_MHZ : Low Speed 6 MHz Clock\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n\r\n  USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);\r\n  USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS;\r\n\r\n  if (freq == HCFG_48_MHZ)\r\n  {\r\n    USBx_HOST->HFIR = 48000U;\r\n  }\r\n  else if (freq == HCFG_6_MHZ)\r\n  {\r\n    USBx_HOST->HFIR = 6000U;\r\n  }\r\n  else\r\n  {\r\n     /* ... */\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n* @brief  USB_OTG_ResetPort : Reset Host Port\r\n  * @param  USBx  Selected device\r\n  * @retval HAL status\r\n  * @note (1)The application must wait at least 10 ms\r\n  *   before clearing the reset bit.\r\n  */\r\nHAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n\r\n  __IO uint32_t hprt0 = 0U;\r\n\r\n  hprt0 = USBx_HPRT0;\r\n\r\n  hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\r\n             USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);\r\n\r\n  USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);\r\n  HAL_Delay (100U);                                /* See Note #1 */\r\n  USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0);\r\n  HAL_Delay (10U);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USB_DriveVbus : activate or de-activate vbus\r\n  * @param  state  VBUS state\r\n  *          This parameter can be one of these values:\r\n  *           0 : VBUS Active\r\n  *           1 : VBUS Inactive\r\n  * @retval HAL status\r\n*/\r\nHAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n  __IO uint32_t hprt0 = 0U;\r\n\r\n  hprt0 = USBx_HPRT0;\r\n\r\n  hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\r\n             USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);\r\n\r\n  if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U))\r\n  {\r\n    USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0);\r\n  }\r\n  if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U))\r\n  {\r\n    USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0);\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Return Host Core speed\r\n  * @param  USBx  Selected device\r\n  * @retval speed : Host speed\r\n  *          This parameter can be one of these values:\r\n  *            @arg USB_OTG_SPEED_HIGH: High speed mode\r\n  *            @arg USB_OTG_SPEED_FULL: Full speed mode\r\n  *            @arg USB_OTG_SPEED_LOW: Low speed mode\r\n  */\r\nuint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n  __IO uint32_t hprt0 = 0U;\r\n\r\n  hprt0 = USBx_HPRT0;\r\n  return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17);\r\n}\r\n\r\n/**\r\n  * @brief  Return Host Current Frame number\r\n  * @param  USBx  Selected device\r\n  * @retval current frame number\r\n*/\r\nuint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n\r\n  return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);\r\n}\r\n\r\n/**\r\n  * @brief  Initialize a host channel\r\n  * @param  USBx  Selected device\r\n  * @param  ch_num  Channel number\r\n  *         This parameter can be a value from 1 to 15\r\n  * @param  epnum  Endpoint number\r\n  *          This parameter can be a value from 1 to 15\r\n  * @param  dev_address  Current device address\r\n  *          This parameter can be a value from 0 to 255\r\n  * @param  speed  Current device speed\r\n  *          This parameter can be one of these values:\r\n  *            @arg USB_OTG_SPEED_HIGH: High speed mode\r\n  *            @arg USB_OTG_SPEED_FULL: Full speed mode\r\n  *            @arg USB_OTG_SPEED_LOW: Low speed mode\r\n  * @param  ep_type  Endpoint Type\r\n  *          This parameter can be one of these values:\r\n  *            @arg EP_TYPE_CTRL: Control type\r\n  *            @arg EP_TYPE_ISOC: Isochronous type\r\n  *            @arg EP_TYPE_BULK: Bulk type\r\n  *            @arg EP_TYPE_INTR: Interrupt type\r\n  * @param  mps  Max Packet Size\r\n  *          This parameter can be a value from 0 to32K\r\n  * @retval HAL state\r\n  */\r\nHAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,\r\n                              uint8_t ch_num,\r\n                              uint8_t epnum,\r\n                              uint8_t dev_address,\r\n                              uint8_t speed,\r\n                              uint8_t ep_type,\r\n                              uint16_t mps)\r\n{\r\n  HAL_StatusTypeDef ret = HAL_OK;\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n  uint32_t HCcharEpDir, HCcharLowSpeed;\r\n\r\n  /* Clear old interrupt conditions for this host channel. */\r\n  USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU;\r\n\r\n  /* Enable channel interrupts required for this transfer. */\r\n  switch (ep_type)\r\n  {\r\n  case EP_TYPE_CTRL:\r\n  case EP_TYPE_BULK:\r\n    USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |\r\n                                USB_OTG_HCINTMSK_STALLM |\r\n                                USB_OTG_HCINTMSK_TXERRM |\r\n                                USB_OTG_HCINTMSK_DTERRM |\r\n                                USB_OTG_HCINTMSK_AHBERR |\r\n                                USB_OTG_HCINTMSK_NAKM;\r\n\r\n    if ((epnum & 0x80U) == 0x80U)\r\n    {\r\n      USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;\r\n    }\r\n    else\r\n    {\r\n      if(USBx != USB_OTG_FS)\r\n      {\r\n        USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);\r\n      }\r\n    }\r\n    break;\r\n\r\n  case EP_TYPE_INTR:\r\n    USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |\r\n                                USB_OTG_HCINTMSK_STALLM |\r\n                                USB_OTG_HCINTMSK_TXERRM |\r\n                                USB_OTG_HCINTMSK_DTERRM |\r\n                                USB_OTG_HCINTMSK_NAKM   |\r\n                                USB_OTG_HCINTMSK_AHBERR |\r\n                                USB_OTG_HCINTMSK_FRMORM;\r\n\r\n    if ((epnum & 0x80U) == 0x80U)\r\n    {\r\n      USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;\r\n    }\r\n\r\n    break;\r\n\r\n  case EP_TYPE_ISOC:\r\n    USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |\r\n                                USB_OTG_HCINTMSK_ACKM   |\r\n                                USB_OTG_HCINTMSK_AHBERR |\r\n                                USB_OTG_HCINTMSK_FRMORM;\r\n\r\n    if ((epnum & 0x80U) == 0x80U)\r\n    {\r\n      USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);\r\n    }\r\n    break;\r\n\r\n  default:\r\n    ret = HAL_ERROR;\r\n    break;\r\n  }\r\n\r\n  /* Enable the top level host channel interrupt. */\r\n  USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU);\r\n\r\n  /* Make sure host channel interrupts are enabled. */\r\n  USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;\r\n\r\n  /* Program the HCCHAR register */\r\n  if((epnum & 0x80U) == 0x80U)\r\n  {\r\n    HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR;\r\n  }\r\n  else\r\n  {\r\n    HCcharEpDir = 0U;\r\n  }\r\n\r\n  if(speed == HPRT0_PRTSPD_LOW_SPEED)\r\n  {\r\n    HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV;\r\n  }\r\n  else\r\n  {\r\n    HCcharLowSpeed = 0U;\r\n  }\r\n\r\n  USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) |\r\n                            ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) |\r\n                            (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) |\r\n                            ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed;\r\n\r\n  if (ep_type == EP_TYPE_INTR)\r\n  {\r\n    USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ;\r\n  }\r\n\r\n  return ret;\r\n}\r\n\r\n/**\r\n  * @brief  Start a transfer over a host channel\r\n  * @param  USBx  Selected device\r\n  * @param  hc  pointer to host channel structure\r\n  * @param  dma USB dma enabled or disabled\r\n  *          This parameter can be one of these values:\r\n  *           0 : DMA feature not used\r\n  *           1 : DMA feature used\r\n  * @retval HAL state\r\n  */\r\nHAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n  uint32_t ch_num = (uint32_t)hc->ch_num;\r\n  static __IO uint32_t tmpreg = 0U;\r\n  uint8_t  is_oddframe;\r\n  uint16_t len_words;\r\n  uint16_t num_packets;\r\n  uint16_t max_hc_pkt_count = 256U;\r\n\r\n  if((USBx != USB_OTG_FS) && (hc->speed == USB_OTG_SPEED_HIGH))\r\n  {\r\n    if((dma == 0U) && (hc->do_ping == 1U))\r\n    {\r\n      (void)USB_DoPing(USBx, hc->ch_num);\r\n      return HAL_OK;\r\n    }\r\n    else if(dma == 1U)\r\n    {\r\n      USBx_HC(ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);\r\n      hc->do_ping = 0U;\r\n    }\r\n    else\r\n    {\r\n      /* ... */\r\n    }\r\n  }\r\n\r\n  /* Compute the expected number of packets associated to the transfer */\r\n  if (hc->xfer_len > 0U)\r\n  {\r\n    num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet);\r\n\r\n    if (num_packets > max_hc_pkt_count)\r\n    {\r\n      num_packets = max_hc_pkt_count;\r\n      hc->xfer_len = (uint32_t)num_packets * hc->max_packet;\r\n    }\r\n  }\r\n  else\r\n  {\r\n    num_packets = 1U;\r\n  }\r\n  if (hc->ep_is_in != 0U)\r\n  {\r\n    hc->xfer_len = (uint32_t)num_packets * hc->max_packet;\r\n  }\r\n\r\n  /* Initialize the HCTSIZn register */\r\n  USBx_HC(ch_num)->HCTSIZ = (hc->xfer_len & USB_OTG_HCTSIZ_XFRSIZ) |\r\n                                (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\r\n                                (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID);\r\n\r\n  if (dma != 0U)\r\n  {\r\n    /* xfer_buff MUST be 32-bits aligned */\r\n    USBx_HC(ch_num)->HCDMA = (uint32_t)hc->xfer_buff;\r\n  }\r\n\r\n  is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U;\r\n  USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;\r\n  USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29;\r\n\r\n  /* Set host channel enable */\r\n  tmpreg = USBx_HC(ch_num)->HCCHAR;\r\n  tmpreg &= ~USB_OTG_HCCHAR_CHDIS;\r\n\r\n  /* make sure to set the correct ep direction */\r\n  if (hc->ep_is_in != 0U)\r\n  {\r\n    tmpreg |= USB_OTG_HCCHAR_EPDIR;\r\n  }\r\n  else\r\n  {\r\n     tmpreg &= ~USB_OTG_HCCHAR_EPDIR;\r\n  }\r\n  tmpreg |= USB_OTG_HCCHAR_CHENA;\r\n  USBx_HC(ch_num)->HCCHAR = tmpreg;\r\n\r\n  if (dma == 0U) /* Slave mode */\r\n  {\r\n    if((hc->ep_is_in == 0U) && (hc->xfer_len > 0U))\r\n    {\r\n      switch(hc->ep_type)\r\n      {\r\n        /* Non periodic transfer */\r\n      case EP_TYPE_CTRL:\r\n      case EP_TYPE_BULK:\r\n\r\n        len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);\r\n\r\n        /* check if there is enough space in FIFO space */\r\n        if(len_words > (USBx->HNPTXSTS & 0xFFFFU))\r\n        {\r\n          /* need to process data in nptxfempty interrupt */\r\n          USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;\r\n        }\r\n        break;\r\n\r\n        /* Periodic transfer */\r\n      case EP_TYPE_INTR:\r\n      case EP_TYPE_ISOC:\r\n        len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);\r\n        /* check if there is enough space in FIFO space */\r\n        if(len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */\r\n        {\r\n          /* need to process data in ptxfempty interrupt */\r\n          USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;\r\n        }\r\n        break;\r\n\r\n      default:\r\n        break;\r\n      }\r\n\r\n      /* Write packet into the Tx FIFO. */\r\n      (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0);\r\n    }\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Read all host channel interrupts status\r\n  * @param  USBx  Selected device\r\n  * @retval HAL state\r\n  */\r\nuint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n\r\n  return ((USBx_HOST->HAINT) & 0xFFFFU);\r\n}\r\n\r\n/**\r\n  * @brief  Halt a host channel\r\n  * @param  USBx  Selected device\r\n  * @param  hc_num  Host Channel number\r\n  *         This parameter can be a value from 1 to 15\r\n  * @retval HAL state\r\n  */\r\nHAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n  uint32_t hcnum = (uint32_t)hc_num;\r\n  uint32_t count = 0U;\r\n  uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18;\r\n\r\n  /* Check for space in the request queue to issue the halt. */\r\n  if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK))\r\n  {\r\n    USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;\r\n\r\n    if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U)\r\n    {\r\n      USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;\r\n      USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;\r\n      USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;\r\n      do\r\n      {\r\n        if (++count > 1000U)\r\n        {\r\n          break;\r\n        }\r\n      }\r\n      while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);\r\n    }\r\n    else\r\n    {\r\n      USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;\r\n    }\r\n  }\r\n  else\r\n  {\r\n    USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;\r\n\r\n    if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U)\r\n    {\r\n      USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;\r\n      USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;\r\n      USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;\r\n      do\r\n      {\r\n        if (++count > 1000U)\r\n        {\r\n          break;\r\n        }\r\n      }\r\n      while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);\r\n    }\r\n    else\r\n    {\r\n       USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;\r\n    }\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initiate Do Ping protocol\r\n  * @param  USBx  Selected device\r\n  * @param  hc_num  Host Channel number\r\n  *         This parameter can be a value from 1 to 15\r\n  * @retval HAL state\r\n  */\r\nHAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n  uint32_t chnum = (uint32_t)ch_num;\r\n  uint32_t num_packets = 1U;\r\n  uint32_t tmpreg;\r\n\r\n  USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\r\n                            USB_OTG_HCTSIZ_DOPING;\r\n\r\n  /* Set host channel enable */\r\n  tmpreg = USBx_HC(chnum)->HCCHAR;\r\n  tmpreg &= ~USB_OTG_HCCHAR_CHDIS;\r\n  tmpreg |= USB_OTG_HCCHAR_CHENA;\r\n  USBx_HC(chnum)->HCCHAR = tmpreg;\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stop Host Core\r\n  * @param  USBx  Selected device\r\n  * @retval HAL state\r\n  */\r\nHAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n  uint32_t count = 0U;\r\n  uint32_t value;\r\n  uint32_t i;\r\n\r\n\r\n  (void)USB_DisableGlobalInt(USBx);\r\n\r\n    /* Flush FIFO */\r\n  (void)USB_FlushTxFifo(USBx, 0x10U);\r\n  (void)USB_FlushRxFifo(USBx);\r\n\r\n  /* Flush out any leftover queued requests. */\r\n  for (i = 0U; i <= 15U; i++)\r\n  {\r\n    value = USBx_HC(i)->HCCHAR;\r\n    value |=  USB_OTG_HCCHAR_CHDIS;\r\n    value &= ~USB_OTG_HCCHAR_CHENA;\r\n    value &= ~USB_OTG_HCCHAR_EPDIR;\r\n    USBx_HC(i)->HCCHAR = value;\r\n  }\r\n\r\n  /* Halt all channels to put them into a known state. */\r\n  for (i = 0U; i <= 15U; i++)\r\n  {\r\n    value = USBx_HC(i)->HCCHAR;\r\n    value |= USB_OTG_HCCHAR_CHDIS;\r\n    value |= USB_OTG_HCCHAR_CHENA;\r\n    value &= ~USB_OTG_HCCHAR_EPDIR;\r\n    USBx_HC(i)->HCCHAR = value;\r\n\r\n    do\r\n    {\r\n      if (++count > 1000U)\r\n      {\r\n        break;\r\n      }\r\n    }\r\n    while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);\r\n  }\r\n\r\n  /* Clear any pending Host interrupts */\r\n  USBx_HOST->HAINT = 0xFFFFFFFFU;\r\n  USBx->GINTSTS = 0xFFFFFFFFU;\r\n  (void)USB_EnableGlobalInt(USBx);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USB_ActivateRemoteWakeup active remote wakeup signalling\r\n  * @param  USBx Selected device\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n\r\n  if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)\r\n  {\r\n    /* active Remote wakeup signalling */\r\n    USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USB_DeActivateRemoteWakeup de-active remote wakeup signalling\r\n  * @param  USBx Selected device\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  uint32_t USBx_BASE = (uint32_t)USBx;\r\n\r\n  /* active Remote wakeup signalling */\r\n   USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);\r\n\r\n  return HAL_OK;\r\n}\r\n#endif /* defined USB_OTG_FS || defined USB_OTG_HS */\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/main.cpp",
    "content": "/*\r\n *  main.h\r\n *\r\n *  Created on: 2016. 7. 17.\r\n *      Author: Baram, PBHP\r\n */\r\n\r\n#include <stdio.h>\r\n\r\n#include \"bsp.h\"\r\n#include \"hw.h\"\r\n#include \"variant.h\"\r\n\r\n\r\nvoid setup(void);\r\nvoid loop(void);\r\n\r\n\r\n\r\nint main(void)\r\n{\r\n\r\n\tbsp_init();\r\n\thw_init();\r\n  var_init();\r\n\r\n\tsetup();\r\n\r\n\twhile (1)\r\n\t{\r\n\t\tloop();\r\n\t\tif(serialEventRun) serialEventRun();\r\n\t}\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/pins_arduino.h",
    "content": "/*\n  Copyright (c) 2011 Arduino.  All right reserved.\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n  See the GNU Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n// API compatibility\n#include \"variant.h\"\n\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/variant.cpp",
    "content": "/*\n  Copyright (c) 2011 Arduino.  All right reserved.\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n  See the GNU Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n /*\n *  Modified on: 2016. 7.12.\n *       Author: Baram, PBHP\n */\n#include \"Arduino.h\"\n\n\nstatic uint8_t user_led_tbl[] = { BDPIN_LED_USER_1,\n                                  BDPIN_LED_USER_2,\n                                  BDPIN_LED_USER_3,\n                                  BDPIN_LED_USER_4 };\n\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n\n\nextern const Pin2PortMapArray g_Pin2PortMapArray[]=\n{\n    {GPIOC, GPIO_PIN_7,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 0  UART6_RX\n    {GPIOC, GPIO_PIN_6,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 1  UART6_TX\n    {GPIOG, GPIO_PIN_6,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , 0       },  // 2                         EXTI_0\n    {GPIOB, GPIO_PIN_4,   NULL,     NO_ADC        , &hTIM3 ,   TIM_CHANNEL_1, 1       },  // 3  TIM3_CH1               EXTI_1\n    {GPIOG, GPIO_PIN_7,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , 2       },  // 4                         EXTI_2\n    {GPIOA, GPIO_PIN_8,   NULL,     NO_ADC        , &hTIM1 ,   TIM_CHANNEL_1, NO_EXTI },  // 5  TIM1_CH1\n    {GPIOA, GPIO_PIN_2,   NULL,     NO_ADC        , &hTIM2 ,   TIM_CHANNEL_3, NO_EXTI },  // 6  TIM2_CH3\n    {GPIOC, GPIO_PIN_1,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , 3       },  // 7                         EXTI_3\n    {GPIOC, GPIO_PIN_2,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , 4       },  // 8                         EXTI_4\n    {GPIOA, GPIO_PIN_3,   NULL,     NO_ADC        , &hTIM9 ,   TIM_CHANNEL_2, NO_EXTI },  // 9  TIM9_CH2\n    {GPIOB, GPIO_PIN_9,   NULL,     NO_ADC        , &hTIM11,   TIM_CHANNEL_1, NO_EXTI },  // 10 TIM11_CH1   SPI2_NSS\n    {GPIOB, GPIO_PIN_15,  NULL,     NO_ADC        , &hTIM12,   TIM_CHANNEL_2, NO_EXTI },  // 11 TIM12_CH2   SPI2_MOSI\n    {GPIOB, GPIO_PIN_14,  NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 12             SPI2_MISO\n    {GPIOA, GPIO_PIN_9,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 13 LED         SPI2_SCK\n    {GPIOB, GPIO_PIN_7,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 14             I2C1_SDA\n    {GPIOB, GPIO_PIN_8,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 15             I2C1_SCL\n\n    {GPIOA, GPIO_PIN_0,   &hADC3,   ADC_CHANNEL_0 , NULL   ,   NO_PWM       , NO_EXTI },  // 16 A0\n    {GPIOF, GPIO_PIN_10,  &hADC3,   ADC_CHANNEL_8 , NULL   ,   NO_PWM       , NO_EXTI },  // 17 A1\n    {GPIOF, GPIO_PIN_9,   &hADC3,   ADC_CHANNEL_7 , NULL   ,   NO_PWM       , NO_EXTI },  // 18 A2\n    {GPIOF, GPIO_PIN_8,   &hADC3,   ADC_CHANNEL_6 , NULL   ,   NO_PWM       , NO_EXTI },  // 19 A3\n    {GPIOF, GPIO_PIN_7,   &hADC3,   ADC_CHANNEL_5 , NULL   ,   NO_PWM       , NO_EXTI },  // 20 A4\n    {GPIOF, GPIO_PIN_6,   &hADC3,   ADC_CHANNEL_4 , NULL   ,   NO_PWM       , NO_EXTI },  // 21 A5\n\n    {GPIOG, GPIO_PIN_12,  NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 22 BDPIN_LED_USER_1\n    {GPIOE, GPIO_PIN_5,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 23 BDPIN_LED_USER_2\n    {GPIOE, GPIO_PIN_4,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 24 BDPIN_LED_USER_3\n    {GPIOG, GPIO_PIN_10,  NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 25 BDPIN_LED_USER_4\n    {GPIOG, GPIO_PIN_11,  NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 26 BDPIN_DIP_SW_1\n    {GPIOE, GPIO_PIN_6,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 27 BDPIN_DIP_SW_2\n    {GPIOA, GPIO_PIN_4,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 28 BDPIN_SPI_CS_IMU\n    {GPIOC, GPIO_PIN_0,   &hADC3,   ADC_CHANNEL_10, NULL   ,   NO_PWM       , NO_EXTI },  // 29 BDPIN_BAT_PWR_ADC\n    {GPIOC, GPIO_PIN_3,   &hADC3,   ADC_CHANNEL_13, NULL   ,   NO_PWM       , NO_EXTI },  // 30\n    {GPIOF, GPIO_PIN_14,  NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 31 BDPIN_BUZZER\n    {GPIOF, GPIO_PIN_15,  NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 32 BDPIN_DXL_PWR_EN\n    {GPIOG, GPIO_PIN_14,  NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 33\n    {GPIOG, GPIO_PIN_3,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 34 BDPIN_PUSH_SW_1\n    {GPIOC, GPIO_PIN_12,  NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 35 BDPIN_PUSH_SW_2\n    {GPIOG, GPIO_PIN_9,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 36 BDPIN_LED_STATUS\n    {GPIOA, GPIO_PIN_5,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 37 BDPIN_SPI_CLK_IMU\n    {GPIOA, GPIO_PIN_6,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 38 BDPIN_SPI_SDO_IMU\n    {GPIOB, GPIO_PIN_5,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 39 BDPIN_SPI_SDI_IMU\n\n    {GPIOB, GPIO_PIN_0,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 40 OLLO_P1_SIG1\n    {GPIOC, GPIO_PIN_8,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 41 OLLO_P1_SIG2\n    {GPIOA, GPIO_PIN_7,   &hADC1,   ADC_CHANNEL_7 , NULL   ,   NO_PWM       , 5       },  // 42 OLLO_P1_ADC           EXTI_5\n    {GPIOC, GPIO_PIN_5,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 43 OLLO_P2_SIG1\n    {GPIOB, GPIO_PIN_1,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 44 OLLO_P2_SIG2\n    {GPIOC, GPIO_PIN_4,   &hADC1,   ADC_CHANNEL_14, NULL   ,   NO_PWM       , 6       },  // 45 OLLO_P2_ADC           EXTI_6\n    {GPIOD, GPIO_PIN_10,  NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 46 OLLO_SLEEP\n    {GPIOF, GPIO_PIN_7,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 47\n    {GPIOF, GPIO_PIN_7,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 48\n    {GPIOF, GPIO_PIN_7,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 49\n\n    {GPIOB, GPIO_PIN_10,  NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 50 BDPIN_GPIO_1\n    {GPIOB, GPIO_PIN_11,  NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 51 BDPIN_GPIO_2\n    {GPIOC, GPIO_PIN_13,  NULL,     NO_ADC        , NULL   ,   NO_PWM       , 9       },  // 52 BDPIN_GPIO_3          EXTI_9\n    {GPIOD, GPIO_PIN_2,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 53 BDPIN_GPIO_4\n    {GPIOE, GPIO_PIN_3,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 54 BDPIN_GPIO_5\n    {GPIOG, GPIO_PIN_2,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 55 BDPIN_GPIO_6\n    {GPIOE, GPIO_PIN_10,  NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 56 BDPIN_GPIO_7\n    {GPIOE, GPIO_PIN_11,  NULL,     NO_ADC        , &hTIM1 ,   TIM_CHANNEL_2, NO_EXTI },  // 57 BDPIN_GPIO_8  SPI4_NSS\n    {GPIOE, GPIO_PIN_12,  NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 58 BDPIN_GPIO_9  SPI4_SCK\n    {GPIOE, GPIO_PIN_13,  NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 59 BDPIN_GPIO_10 SPI4_MISO\n    {GPIOE, GPIO_PIN_14,  NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 60 BDPIN_GPIO_11 SPI4_MOSI\n    {GPIOE, GPIO_PIN_15,  NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 61 BDPIN_GPIO_12\n    {GPIOF, GPIO_PIN_0,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 62 BDPIN_GPIO_13\n    {GPIOF, GPIO_PIN_1,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 63 BDPIN_GPIO_14\n    {GPIOF, GPIO_PIN_2,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 64 BDPIN_GPIO_15\n    {GPIOD, GPIO_PIN_8,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 65 BDPIN_GPIO_16\n    {GPIOF, GPIO_PIN_4,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 66 BDPIN_GPIO_17\n    {GPIOD, GPIO_PIN_9,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 67 BDPIN_GPIO_18\n    {GPIOF, GPIO_PIN_7,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 68\n    {GPIOF, GPIO_PIN_7,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 69\n\n    {GPIOF, GPIO_PIN_12,  NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 70 OLLO_P3_SIG1\n    {GPIOF, GPIO_PIN_11,  NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 71 OLLO_P3_SIG2\n    {GPIOF, GPIO_PIN_5,   &hADC3,   ADC_CHANNEL_15, NULL   ,   NO_PWM       , 7       },  // 72 OLLO_P3_ADC           EXTI_7\n    {GPIOE, GPIO_PIN_9,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 73 OLLO_P4_SIG1\n    {GPIOE, GPIO_PIN_8,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 74 OLLO_P4_SIG2\n    {GPIOF, GPIO_PIN_3,   &hADC3,   ADC_CHANNEL_9 , NULL   ,   NO_PWM       , 8       },  // 75 OLLO_P4_ADC           EXTI_8\n    {GPIOF, GPIO_PIN_7,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 76\n    {GPIOF, GPIO_PIN_7,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 77\n    {GPIOF, GPIO_PIN_7,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 78\n    {GPIOF, GPIO_PIN_7,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 79\n\n    {GPIOD, GPIO_PIN_6,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 80 BDPIN_UART1_RX\n    {GPIOD, GPIO_PIN_5,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 81 BDPIN_UART1_TX\n    {GPIOE, GPIO_PIN_0,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 82 BDPIN_UART2_RX\n    {GPIOE, GPIO_PIN_1,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 83 BDPIN_UART2_TX\n\n    {GPIOC, GPIO_PIN_9,   NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI },  // 84 DXL_DIR_PIN\n\n    {NULL , 0          ,  NULL,     NO_ADC        , NULL   ,   NO_PWM       , NO_EXTI }\n};\n\n\n#ifdef __cplusplus\n}\n#endif\n\n\n\n\n/* ----------------------------------------------------------------------------\n *     USART objects\n * ----------------------------------------------------------------------------*/\nvoid serialEvent() __attribute__((weak));\nvoid serialEvent() { }\n\nvoid serialEvent1() __attribute__((weak));\nvoid serialEvent1() { }\n\nvoid serialEvent2() __attribute__((weak));\nvoid serialEvent2() { }\n\nvoid serialEvent3() __attribute__((weak));\nvoid serialEvent3() { }\n\nvoid serialEvent4() __attribute__((weak));\nvoid serialEvent4() { }\n\nUSBSerial Serial;\nuint8_t serial1_tx_buffer[SERIAL_BUFFER_SIZE] __attribute__((section(\".NoneCacheableMem\")));\nuint8_t serial2_tx_buffer[SERIAL_BUFFER_SIZE] __attribute__((section(\".NoneCacheableMem\")));\nuint8_t serial3_tx_buffer[SERIAL_BUFFER_SIZE] __attribute__((section(\".NoneCacheableMem\")));\nuint8_t serial4_tx_buffer[SERIAL_BUFFER_SIZE] __attribute__((section(\".NoneCacheableMem\")));\n\nUARTClass Serial1(DRV_UART_NUM_1, DRV_UART_DMA_MODE, serial1_tx_buffer, sizeof(serial1_tx_buffer));\nUARTClass Serial2(DRV_UART_NUM_2, DRV_UART_DMA_MODE, serial2_tx_buffer, sizeof(serial2_tx_buffer));\nUARTClass Serial3(DRV_UART_NUM_3, DRV_UART_DMA_MODE, serial3_tx_buffer, sizeof(serial3_tx_buffer));\nUARTClass Serial4(DRV_UART_NUM_4, DRV_UART_DMA_MODE, serial4_tx_buffer, sizeof(serial4_tx_buffer));\n\n\nvoid Tx1_Handler(void){ Serial1.TxHandler(); }\nvoid Rx1_Handler(void){ Serial1.RxHandler(); }\nvoid Tx2_Handler(void){ Serial2.TxHandler(); }\nvoid Rx2_Handler(void){ Serial2.RxHandler(); }\nvoid Tx3_Handler(void){ Serial3.TxHandler(); }\nvoid Rx3_Handler(void){ Serial3.RxHandler(); }\nvoid Tx4_Handler(void){ Serial4.TxHandler(); }\nvoid Rx4_Handler(void){ Serial4.RxHandler(); }\n\n\n\nvoid serialEventRun(void)\n{\n  if (Serial.available()) serialEvent();\n  if (Serial1.available()) serialEvent1();\n  if (Serial2.available()) serialEvent2();\n  if (Serial3.available()) serialEvent3();\n  if (Serial4.available()) serialEvent4();\n}\n\n\nvoid var_init(void)\n{\n  pinMode(BDPIN_DIP_SW_1,  INPUT);\n  pinMode(BDPIN_DIP_SW_2,  INPUT);\n  pinMode(BDPIN_PUSH_SW_1, INPUT);\n  pinMode(BDPIN_PUSH_SW_2, INPUT);\n\n  pinMode(BDPIN_LED_USER_1, OUTPUT);\n  pinMode(BDPIN_LED_USER_2, OUTPUT);\n  pinMode(BDPIN_LED_USER_3, OUTPUT);\n  pinMode(BDPIN_LED_USER_4, OUTPUT);\n\n  digitalWrite(BDPIN_LED_USER_1, HIGH);\n  digitalWrite(BDPIN_LED_USER_2, HIGH);\n  digitalWrite(BDPIN_LED_USER_3, HIGH);\n  digitalWrite(BDPIN_LED_USER_4, HIGH);\n\n}\n\n\nfloat getPowerInVoltage(void)\n{\n  int adc_value;\n  float vol_value;\n\n  adc_value = analogRead(BDPIN_BAT_PWR_ADC);\n  vol_value = map(adc_value, 0, 1023, 0, 330*57/10);\n  vol_value = vol_value / 100.;\n\n  return vol_value;\n}\n\n\nuint8_t getDipSwitch(void)\n{\n  uint8_t dip_state;\n\n\n  dip_state  = digitalRead(BDPIN_DIP_SW_1)<<0;\n  dip_state |= digitalRead(BDPIN_DIP_SW_2)<<1;\n\n  return dip_state;\n}\n\n\nuint8_t getPushButton(void)\n{\n  int push_state;\n\n  push_state  = digitalRead(BDPIN_PUSH_SW_1)<<0;\n  push_state |= digitalRead(BDPIN_PUSH_SW_2)<<1;\n\n  return push_state;\n}\n\n\nvoid setLedOn(uint8_t led_num)\n{\n  if(led_num < 4)\n  {\n    digitalWrite(user_led_tbl[led_num], LOW);\n  }\n}\n\n\nvoid setLedOff(uint8_t led_num)\n{\n  if(led_num < 4)\n  {\n    digitalWrite(user_led_tbl[led_num], HIGH);\n  }\n}\n\n\nvoid setLedToggle(uint8_t led_num)\n{\n  if(led_num < 4)\n  {\n    digitalWrite(user_led_tbl[led_num], !digitalRead(user_led_tbl[led_num]));\n  }\n}\n\n\nuint8_t getUsbConnected(void)\n{\n  return vcp_is_connected();\n}\n"
  },
  {
    "path": "arduino/opencr_arduino/opencr/variants/OpenCR/variant.h",
    "content": "/****************************************************************************\n * Copyright (c) 2016 by Vassilis Serasidis <info@serasidis.gr>\n *\n * Variant definition library for Arduino STM32 + HAL + CubeMX (HALMX).\n *\n * This file is free software; you can redistribute it and/or modify\n * it under the terms of either the GNU General Public License version 2\n * or the GNU Lesser General Public License version 2.1, both as\n * published by the Free Software Foundation.\n ****************************************************************************/\n /*\n *  Modified on: 2016. 7.12.\n *       Author: Baram, PBHP\n */\n#ifndef _VARIANT_OPENCR_\n#define _VARIANT_OPENCR_\n\n#include <chip.h>\n\n\n\n#define NO_ADC \t\t0xffff\n#define NO_PWM\t\t0xffff\n#define NO_EXTI   0xffff\n\n\n/*----------------------------------------------------------------------------\n *        Headers\n *----------------------------------------------------------------------------*/\n\n#include \"Arduino.h\"\n#ifdef __cplusplus\n#include \"UARTClass.h\"\n#include \"USBSerial.h\"\n#include \"HardwareTimer.h\"\n#endif\n\n\n#ifdef __cplusplus\nextern \"C\"{\n#endif // __cplusplus\n\n\n\n/*\n * Analog pins\n */\nstatic const uint8_t A0  = 16;\nstatic const uint8_t A1  = 17;\nstatic const uint8_t A2  = 18;\nstatic const uint8_t A3  = 19;\nstatic const uint8_t A4  = 20;\nstatic const uint8_t A5  = 21;\nstatic const uint8_t BAT = 29;\n\n\n\ntypedef struct _Pin2PortMapArray\n{\n  \tGPIO_TypeDef *GPIOx_Port;\n\n  \tuint32_t \tPin_abstraction;\n\n  \tADC_HandleTypeDef *ADCx;\n    uint32_t  adc_channel;\n\n    TIM_HandleTypeDef *TIMx;\n    uint32_t  timerChannel;\n    uint32_t  extiChannel;\n} Pin2PortMapArray ;\n\n\nextern const Pin2PortMapArray g_Pin2PortMapArray[] ;\n\nvoid Rx1_Handler(void);\nvoid Tx1_Handler(void);\nvoid Rx2_Handler(void);\nvoid Tx2_Handler(void);\nvoid Rx3_Handler(void);\nvoid Tx3_Handler(void);\nvoid Rx4_Handler(void);\nvoid Tx4_Handler(void);\n\nvoid Err1_Handler(void);\nvoid Err2_Handler(void);\nvoid Err3_Handler(void);\nvoid Err4_Handler(void);\n\n#ifdef __cplusplus\n}\n#endif\n\n\n/*----------------------------------------------------------------------------\n *        Arduino objects - C++ only\n *----------------------------------------------------------------------------*/\n\n#ifdef __cplusplus\n\nextern USBSerial Serial;    // USB\nextern UARTClass Serial1;   // Arduino Serial\nextern UARTClass Serial2;   // Ext Serial for Bluetooth\nextern UARTClass Serial3;   // Ext Serial for Dynamixel\nextern UARTClass Serial4;   // Ext Serial for Bluetooth\n\n\n#define SerialBT1   Serial2\n#define SerialBT2   Serial4\n\n\n#endif\n\n\n#define digitalPinToInterrupt(P)   ( g_Pin2PortMapArray[P].extiChannel )\n#define analogPinToChannel(p)      ( (p) < 6 ? (p)+A0 : (p) )\n\nvoid  var_init();\nfloat getPowerInVoltage(void);\nuint8_t getDipSwitch(void);\nuint8_t getPushButton(void);\nuint8_t getUsbConnected(void);\n\n\nvoid setLedOn(uint8_t led_num);\nvoid setLedOff(uint8_t led_num);\nvoid setLedToggle(uint8_t led_num);\n\n\n#define WIRE_INTERFACES_COUNT       2\n#define SPI_INTERFACES_COUNT        2\n#define EXTI_COUNT                  10\n#define PINS_COUNT                  85\n\n#endif\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/.cproject",
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    "path": "arduino/opencr_develop/opencr_bootloader/.gitignore",
    "content": ".vscode\n.settings\n"
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    "path": "arduino/opencr_develop/opencr_bootloader/.project",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\r\n<projectDescription>\r\n\t<name>opencr_bootloader</name>\r\n\t<comment></comment>\r\n\t<projects>\r\n\t</projects>\r\n\t<buildSpec>\r\n\t\t<buildCommand>\r\n\t\t\t<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>\r\n\t\t\t<triggers>clean,full,incremental,</triggers>\r\n\t\t\t<arguments>\r\n\t\t\t</arguments>\r\n\t\t</buildCommand>\r\n\t\t<buildCommand>\r\n\t\t\t<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>\r\n\t\t\t<triggers>full,incremental,</triggers>\r\n\t\t\t<arguments>\r\n\t\t\t</arguments>\r\n\t\t</buildCommand>\r\n\t</buildSpec>\r\n\t<natures>\r\n\t\t<nature>org.eclipse.cdt.core.cnature</nature>\r\n\t\t<nature>org.eclipse.cdt.core.ccnature</nature>\r\n\t\t<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>\r\n\t\t<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>\r\n\t</natures>\r\n</projectDescription>\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/Makefile",
    "content": "CC      = arm-none-eabi-gcc\r\nOBJCOPY = arm-none-eabi-objcopy\r\nSIZE    = arm-none-eabi-size\r\n\r\n\r\nBRD_NAME = opencr\r\n\r\nPRJ_NAME = bin/opencr_boot\r\nOBJ_DIR  = bin/obj\r\nBIN_DIR  = bin\r\n\r\n\r\n\r\nINC_DIRS  = src/\r\nINC_DIRS += common/bsp/$(BRD_NAME)/\r\nINC_DIRS += common/bsp/$(BRD_NAME)/include/\r\nINC_DIRS += common/bsp/$(BRD_NAME)/cfg/\r\nINC_DIRS += common/hal/\r\nINC_DIRS += common/lib/STM32F7xx_HAL_Driver/Inc/\r\nINC_DIRS += common/lib/STM32_USB_Device_Library/Core/Inc/\r\n\r\n\r\n\r\n\r\nPRJ_SRC  = src/\r\nBSP_SRC  = common/bsp/$(BRD_NAME)/\r\nCFG_SRC  = common/bsp/$(BRD_NAME)/cfg/\r\nHAL_SRC  = common/hal/\r\nSTM_SRC  = common/lib/STM32F7xx_HAL_Driver/Src/\r\nUSB_SRC  = common/lib/STM32_USB_Device_Library/Core/Src/\r\nLNK_SRC  = common/bsp/$(BRD_NAME)/ld/opencr_flash.ld\r\n\r\n\r\n\r\nvpath %.c $(PRJ_SRC)\r\nvpath %.c $(BSP_SRC)\r\nvpath %.c $(CFG_SRC)\r\nvpath %.c $(HAL_SRC)\r\nvpath %.c $(STM_SRC)\r\nvpath %.c $(USB_SRC)\r\nvpath %.s $(CFG_SRC)\r\n\r\n\r\nPRJ_SRCS = $(notdir $(wildcard $(PRJ_SRC)*.c ))\r\nBSP_SRCS = $(notdir $(wildcard $(BSP_SRC)*.c ))\r\nCFG_SRCS = $(notdir $(wildcard $(CFG_SRC)*.c ))\r\nHAL_SRCS = $(notdir $(wildcard $(HAL_SRC)*.c ))\r\nSTM_SRCS = $(notdir $(wildcard $(STM_SRC)*.c ))\r\nUSB_SRCS = $(notdir $(wildcard $(USB_SRC)*.c ))\r\nSRT_SRCS = $(notdir $(wildcard $(CFG_SRC)*.s ))\r\n\r\n\r\nSRCS  = main.c\r\n\r\n\r\n\r\n\r\nINCLUDE = $(addprefix -I,$(INC_DIRS))\r\n\r\nDEFS = -DSTM32F746xx\r\n\r\nCFLAGS  = -ggdb -O2 -ffunction-sections -fdata-sections -std=gnu99\r\nCFLAGS += -mthumb \r\nCFLAGS += -mcpu=cortex-m7 \r\nCFLAGS += -mfloat-abi=softfp -mfpu=fpv5-sp-d16\r\nCFLAGS += -Wl,--gc-sections\r\nWFLAGS += -Wall -Wextra -Warray-bounds -Wno-unused-parameter\r\nLFLAGS  = -T$(LNK_SRC) -Wl,-Map=$(PRJ_NAME).map\r\n\r\n\r\nTARGET_OBJS\t  = $(addprefix $(OBJ_DIR)/, $(addsuffix .o, $(basename $(PRJ_SRCS))))\r\nTARGET_OBJS\t += $(addprefix $(OBJ_DIR)/, $(addsuffix .o, $(basename $(BSP_SRCS))))\r\nTARGET_OBJS\t += $(addprefix $(OBJ_DIR)/, $(addsuffix .o, $(basename $(CFG_SRCS))))\r\nTARGET_OBJS\t += $(addprefix $(OBJ_DIR)/, $(addsuffix .o, $(basename $(HAL_SRCS))))\r\nTARGET_OBJS\t += $(addprefix $(OBJ_DIR)/, $(addsuffix .o, $(basename $(STM_SRCS))))\r\nTARGET_OBJS\t += $(addprefix $(OBJ_DIR)/, $(addsuffix .o, $(basename $(USB_SRCS))))\r\nTARGET_OBJS\t += $(addprefix $(OBJ_DIR)/, $(addsuffix .o, $(basename $(SRT_SRCS))))\r\n\r\n\r\n\r\nall: $(PRJ_NAME)\r\n\r\n\r\n\r\n$(PRJ_NAME): $(PRJ_NAME).elf\r\n\r\n\r\n\r\n\r\n$(PRJ_NAME).elf: $(SRCS) $(TARGET_OBJS)\r\n\t$(CC) $(INCLUDE) $(DEFS) $(CFLAGS) $(WFLAGS) $(LFLAGS) $^ -o $@\r\n\t$(OBJCOPY) -O ihex $(PRJ_NAME).elf   $(PRJ_NAME).hex\r\n\t$(OBJCOPY) -O binary $(PRJ_NAME).elf $(PRJ_NAME).bin\r\n\t$(SIZE) $(PRJ_NAME).elf\r\n\r\n\r\n\r\n$(OBJ_DIR)/%.o: %.c\r\n\t$(CC) -c -o $@ $(INCLUDE) $(DEFS) $(CFLAGS) $^\r\n\r\n$(OBJ_DIR)/%.o: %.s\r\n\t$(CC) -c -o $@ $(INCLUDE) $(DEFS) $(CFLAGS) $^\r\n\t\t\r\n\r\nclean:\r\n\trm -f $(OBJ_DIR)/*.* $(BIN_DIR)/*.*"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/bin/obj/README",
    "content": "obj\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/bsp.c",
    "content": "#include \"bsp.h\"\r\n\r\n\r\nUSBD_HandleTypeDef USBD_Device;\r\n\r\n\r\n\r\nvoid bsp_init()\r\n{\r\n  // STM32Cube HAL Init\r\n  HAL_Init();\r\n\r\n  // Clock Setup\r\n  // SYSCLK(Hz)    = 216000000\r\n  // HCLK(Hz)      = 216000000\r\n  // HSE(Hz)       = 25000000\r\n  SystemClock_Config();\r\n\r\n\r\n  SCB_EnableDCache();\r\n  SCB_EnableICache();\r\n\r\n\r\n  led_init();\r\n  button_init();\r\n\r\n  HAL_Delay(200);\r\n\r\n\r\n  /* Init Device Library */\r\n  USBD_Init(&USBD_Device, &VCP_Desc, 0);\r\n\r\n  /* Add Supported Class */\r\n  USBD_RegisterClass(&USBD_Device, USBD_CDC_CLASS);\r\n\r\n  /* Add CDC Interface Class */\r\n  USBD_CDC_RegisterInterface(&USBD_Device, &USBD_CDC_fops);\r\n\r\n  /* Start Device Process */\r\n  USBD_Start(&USBD_Device);\r\n}\r\n\r\n\r\nvoid bsp_deinit()\r\n{\r\n  USBD_DeInit(&USBD_Device);\r\n\r\n  HAL_RCC_DeInit();\r\n  HAL_DeInit();\r\n\r\n  //SCB_InvalidateDCache();\r\n  //SCB_InvalidateICache();\r\n  SCB_DisableICache();\r\n  SCB_DisableDCache();\r\n\r\n\r\n  //SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;\r\n  //SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk;\r\n\r\n\r\n  //__disable_irq();\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/bsp.h",
    "content": "#ifndef BSP_H\r\n#define BSP_H\r\n\r\n#include <stdint.h>\r\n\r\n#include \"def.h\"\r\n#include \"stm32f746xx.h\"\r\n#include \"stm32f7xx_hal.h\"\r\n#include \"system_clock.h\"\r\n\r\n#include \"usbd_core.h\"\r\n#include \"usbd_desc.h\"\r\n#include \"usbd_cdc.h\"\r\n#include \"usbd_cdc_interface.h\"\r\n\r\n#include \"led.h\"\r\n#include \"button.h\"\r\n#include \"wdg.h\"\r\n\r\n\r\n#define USE_USB_FS\r\n\r\n\r\n\r\n\r\n\r\nvoid bsp_init();\r\nvoid bsp_deinit();\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/button.c",
    "content": "/*\r\n *  button.c\r\n *\r\n *  Created on: 2016. 5. 14.\r\n *      Author: Baram, PBHP\r\n */\r\n\r\n#include \"button.h\"\r\n\r\n\r\n\r\n\r\nvoid button_init()\r\n{\r\n  GPIO_InitTypeDef GPIO_InitStruct;\r\n\r\n  // GPIO Ports Clock Enable\r\n  __HAL_RCC_GPIOC_CLK_ENABLE();\r\n  __HAL_RCC_GPIOG_CLK_ENABLE();\r\n\r\n\r\n\r\n  // Configure GPIO pin : PC12\r\n  GPIO_InitStruct.Pin = GPIO_PIN_12;\r\n  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;\r\n  GPIO_InitStruct.Pull = GPIO_NOPULL;\r\n  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;\r\n  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);\r\n\r\n\r\n  // Configure GPIO pin : PG3\r\n  GPIO_InitStruct.Pin = GPIO_PIN_3;\r\n  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;\r\n  GPIO_InitStruct.Pull = GPIO_NOPULL;\r\n  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;\r\n  HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);\r\n}\r\n\r\n\r\nuint8_t button_read( uint8_t pin_num )\r\n{\r\n  switch( pin_num )\r\n  {\r\n    case 0:\r\n      if(HAL_GPIO_ReadPin(GPIOC, GPIO_PIN_12) == GPIO_PIN_SET ) return TRUE;\r\n      else                                                           return FALSE;\r\n      break;\r\n\r\n    case 1:\r\n      if(HAL_GPIO_ReadPin(GPIOG, GPIO_PIN_3) == GPIO_PIN_SET )  return TRUE;\r\n      else                                                           return FALSE;\r\n      break;\r\n  }\r\n\r\n  return FALSE;\r\n}\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/button.h",
    "content": "/*\r\n *  button.h\r\n *\r\n *  Created on: 2016. 5. 14.\r\n *      Author: Baram, PBHP\r\n */\r\n\r\n#ifndef BUTTON_H\r\n#define BUTTON_H\r\n\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n\r\n#include \"def.h\"\r\n#include \"bsp.h\"\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\nvoid button_init(void);\r\n\r\nuint8_t button_read( uint8_t pin_num );\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/cfg/startup_stm32f746xx.s",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file      startup_stm32f746xx.s\r\n  * @author    MCD Application Team\r\n  * @version   V1.1.0\r\n  * @date      22-April-2016\r\n  * @brief     STM32F746xx Devices vector table for GCC based toolchain. \r\n  *            This module performs:\r\n  *                - Set the initial SP\r\n  *                - Set the initial PC == Reset_Handler,\r\n  *                - Set the vector table entries with the exceptions ISR address\r\n  *                - Branches to main in the C library (which eventually\r\n  *                  calls main()).\r\n  *            After Reset the Cortex-M7 processor is in Thread mode,\r\n  *            priority is Privileged, and the Stack is set to Main.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n    \r\n  .syntax unified\r\n  .cpu cortex-m7\r\n  .fpu softvfp\r\n  .thumb\r\n\r\n.global  g_pfnVectors\r\n.global  Default_Handler\r\n\r\n/* start address for the initialization values of the .data section. \r\ndefined in linker script */\r\n.word  _sidata\r\n/* start address for the .data section. defined in linker script */  \r\n.word  _sdata\r\n/* end address for the .data section. defined in linker script */\r\n.word  _edata\r\n/* start address for the .bss section. defined in linker script */\r\n.word  _sbss\r\n/* end address for the .bss section. defined in linker script */\r\n.word  _ebss\r\n/* stack used for SystemInit_ExtMemCtl; always internal RAM used */\r\n\r\n/**\r\n * @brief  This is the code that gets called when the processor first\r\n *          starts execution following a reset event. Only the absolutely\r\n *          necessary set is performed, after which the application\r\n *          supplied main() routine is called. \r\n * @param  None\r\n * @retval : None\r\n*/\r\n\r\n    .section  .text.Reset_Handler\r\n  .weak  Reset_Handler\r\n  .type  Reset_Handler, %function\r\nReset_Handler:  \r\n  ldr   sp, =_estack      /* set stack pointer */\r\n\r\n/* Copy the data segment initializers from flash to SRAM */  \r\n  movs  r1, #0\r\n  b  LoopCopyDataInit\r\n\r\nCopyDataInit:\r\n  ldr  r3, =_sidata\r\n  ldr  r3, [r3, r1]\r\n  str  r3, [r0, r1]\r\n  adds  r1, r1, #4\r\n    \r\nLoopCopyDataInit:\r\n  ldr  r0, =_sdata\r\n  ldr  r3, =_edata\r\n  adds  r2, r0, r1\r\n  cmp  r2, r3\r\n  bcc  CopyDataInit\r\n  ldr  r2, =_sbss\r\n  b  LoopFillZerobss\r\n/* Zero fill the bss segment. */  \r\nFillZerobss:\r\n  movs  r3, #0\r\n  str  r3, [r2], #4\r\n    \r\nLoopFillZerobss:\r\n  ldr  r3, = _ebss\r\n  cmp  r2, r3\r\n  bcc  FillZerobss\r\n\r\n/* Call the clock system initialization function.*/\r\n  bl  SystemInit   \r\n/* Call static constructors */\r\n    bl __libc_init_array\r\n/* Call the application's entry point.*/\r\n  bl  main\r\n  bx  lr    \r\n.size  Reset_Handler, .-Reset_Handler\r\n\r\n/**\r\n * @brief  This is the code that gets called when the processor receives an \r\n *         unexpected interrupt.  This simply enters an infinite loop, preserving\r\n *         the system state for examination by a debugger.\r\n * @param  None     \r\n * @retval None       \r\n*/\r\n    .section  .text.Default_Handler,\"ax\",%progbits\r\nDefault_Handler:\r\nInfinite_Loop:\r\n  b  Infinite_Loop\r\n  .size  Default_Handler, .-Default_Handler\r\n/******************************************************************************\r\n*\r\n* The minimal vector table for a Cortex M7. Note that the proper constructs\r\n* must be placed on this to ensure that it ends up at physical address\r\n* 0x0000.0000.\r\n* \r\n*******************************************************************************/\r\n   .section  .isr_vector,\"a\",%progbits\r\n  .type  g_pfnVectors, %object\r\n  .size  g_pfnVectors, .-g_pfnVectors\r\n   \r\n   \r\ng_pfnVectors:\r\n  .word  _estack\r\n  .word  Reset_Handler\r\n\r\n  .word  NMI_Handler\r\n  .word  HardFault_Handler\r\n  .word  MemManage_Handler\r\n  .word  BusFault_Handler\r\n  .word  UsageFault_Handler\r\n  .word  0\r\n  .word  0\r\n  .word  0\r\n  .word  0\r\n  .word  SVC_Handler\r\n  .word  DebugMon_Handler\r\n  .word  0\r\n  .word  PendSV_Handler\r\n  .word  SysTick_Handler\r\n  \r\n  /* External Interrupts */\r\n  .word     WWDG_IRQHandler                   /* Window WatchDog              */                                        \r\n  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */                        \r\n  .word     TAMP_STAMP_IRQHandler             /* Tamper and TimeStamps through the EXTI line */            \r\n  .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI line */                      \r\n  .word     FLASH_IRQHandler                  /* FLASH                        */                                          \r\n  .word     RCC_IRQHandler                    /* RCC                          */                                            \r\n  .word     EXTI0_IRQHandler                  /* EXTI Line0                   */                        \r\n  .word     EXTI1_IRQHandler                  /* EXTI Line1                   */                          \r\n  .word     EXTI2_IRQHandler                  /* EXTI Line2                   */                          \r\n  .word     EXTI3_IRQHandler                  /* EXTI Line3                   */                          \r\n  .word     EXTI4_IRQHandler                  /* EXTI Line4                   */                          \r\n  .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                */                  \r\n  .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                */                   \r\n  .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                */                   \r\n  .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                */                   \r\n  .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                */                   \r\n  .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                */                   \r\n  .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                */                   \r\n  .word     ADC_IRQHandler                    /* ADC1, ADC2 and ADC3s         */                   \r\n  .word     CAN1_TX_IRQHandler                /* CAN1 TX                      */                         \r\n  .word     CAN1_RX0_IRQHandler               /* CAN1 RX0                     */                          \r\n  .word     CAN1_RX1_IRQHandler               /* CAN1 RX1                     */                          \r\n  .word     CAN1_SCE_IRQHandler               /* CAN1 SCE                     */                          \r\n  .word     EXTI9_5_IRQHandler                /* External Line[9:5]s          */                          \r\n  .word     TIM1_BRK_TIM9_IRQHandler          /* TIM1 Break and TIM9          */         \r\n  .word     TIM1_UP_TIM10_IRQHandler          /* TIM1 Update and TIM10        */         \r\n  .word     TIM1_TRG_COM_TIM11_IRQHandler     /* TIM1 Trigger and Commutation and TIM11 */\r\n  .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */                          \r\n  .word     TIM2_IRQHandler                   /* TIM2                         */                   \r\n  .word     TIM3_IRQHandler                   /* TIM3                         */                   \r\n  .word     TIM4_IRQHandler                   /* TIM4                         */                   \r\n  .word     I2C1_EV_IRQHandler                /* I2C1 Event                   */                          \r\n  .word     I2C1_ER_IRQHandler                /* I2C1 Error                   */                          \r\n  .word     I2C2_EV_IRQHandler                /* I2C2 Event                   */                          \r\n  .word     I2C2_ER_IRQHandler                /* I2C2 Error                   */                            \r\n  .word     SPI1_IRQHandler                   /* SPI1                         */                   \r\n  .word     SPI2_IRQHandler                   /* SPI2                         */                   \r\n  .word     USART1_IRQHandler                 /* USART1                       */                   \r\n  .word     USART2_IRQHandler                 /* USART2                       */                   \r\n  .word     USART3_IRQHandler                 /* USART3                       */                   \r\n  .word     EXTI15_10_IRQHandler              /* External Line[15:10]s        */                          \r\n  .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through EXTI Line */                 \r\n  .word     OTG_FS_WKUP_IRQHandler            /* USB OTG FS Wakeup through EXTI line */                       \r\n  .word     TIM8_BRK_TIM12_IRQHandler         /* TIM8 Break and TIM12         */         \r\n  .word     TIM8_UP_TIM13_IRQHandler          /* TIM8 Update and TIM13        */         \r\n  .word     TIM8_TRG_COM_TIM14_IRQHandler     /* TIM8 Trigger and Commutation and TIM14 */\r\n  .word     TIM8_CC_IRQHandler                /* TIM8 Capture Compare         */                          \r\n  .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                 */                          \r\n  .word     FMC_IRQHandler                    /* FMC                          */                   \r\n  .word     SDMMC1_IRQHandler                 /* SDMMC1                       */                   \r\n  .word     TIM5_IRQHandler                   /* TIM5                         */                   \r\n  .word     SPI3_IRQHandler                   /* SPI3                         */                   \r\n  .word     UART4_IRQHandler                  /* UART4                        */                   \r\n  .word     UART5_IRQHandler                  /* UART5                        */                   \r\n  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC1&2 underrun errors */                   \r\n  .word     TIM7_IRQHandler                   /* TIM7                         */\r\n  .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                */                   \r\n  .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                */                   \r\n  .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                */                   \r\n  .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                */                   \r\n  .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */                   \r\n  .word     ETH_IRQHandler                    /* Ethernet                     */                   \r\n  .word     ETH_WKUP_IRQHandler               /* Ethernet Wakeup through EXTI line */                     \r\n  .word     CAN2_TX_IRQHandler                /* CAN2 TX                      */                          \r\n  .word     CAN2_RX0_IRQHandler               /* CAN2 RX0                     */                          \r\n  .word     CAN2_RX1_IRQHandler               /* CAN2 RX1                     */                          \r\n  .word     CAN2_SCE_IRQHandler               /* CAN2 SCE                     */                          \r\n  .word     OTG_FS_IRQHandler                 /* USB OTG FS                   */                   \r\n  .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */                   \r\n  .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */                   \r\n  .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */                   \r\n  .word     USART6_IRQHandler                 /* USART6                       */                    \r\n  .word     I2C3_EV_IRQHandler                /* I2C3 event                   */                          \r\n  .word     I2C3_ER_IRQHandler                /* I2C3 error                   */                          \r\n  .word     OTG_HS_EP1_OUT_IRQHandler         /* USB OTG HS End Point 1 Out   */                   \r\n  .word     OTG_HS_EP1_IN_IRQHandler          /* USB OTG HS End Point 1 In    */                   \r\n  .word     OTG_HS_WKUP_IRQHandler            /* USB OTG HS Wakeup through EXTI */                         \r\n  .word     OTG_HS_IRQHandler                 /* USB OTG HS                   */                   \r\n  .word     DCMI_IRQHandler                   /* DCMI                         */                   \r\n  .word     0                                 /* Reserved                     */                   \r\n  .word     RNG_IRQHandler                    /* Rng                          */\r\n  .word     FPU_IRQHandler                    /* FPU                          */\r\n  .word     UART7_IRQHandler                  /* UART7                        */      \r\n  .word     UART8_IRQHandler                  /* UART8                        */\r\n  .word     SPI4_IRQHandler                   /* SPI4                         */\r\n  .word     SPI5_IRQHandler                   /* SPI5                           */\r\n  .word     SPI6_IRQHandler                   /* SPI6                         */\r\n  .word     SAI1_IRQHandler                   /* SAI1                          */\r\n  .word     LTDC_IRQHandler                   /* LTDC                          */\r\n  .word     LTDC_ER_IRQHandler                /* LTDC error                      */\r\n  .word     DMA2D_IRQHandler                  /* DMA2D                          */\r\n  .word     SAI2_IRQHandler                   /* SAI2                         */\r\n  .word     QUADSPI_IRQHandler                /* QUADSPI                      */\r\n  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */\r\n  .word     CEC_IRQHandler                    /* HDMI_CEC                     */\r\n  .word     I2C4_EV_IRQHandler                /* I2C4 Event                   */\r\n  .word     I2C4_ER_IRQHandler                /* I2C4 Error                   */\r\n  .word     SPDIF_RX_IRQHandler               /* SPDIF_RX                     */  \r\n  \r\n/*******************************************************************************\r\n*\r\n* Provide weak aliases for each Exception handler to the Default_Handler. \r\n* As they are weak aliases, any function with the same name will override \r\n* this definition.\r\n* \r\n*******************************************************************************/\r\n   .weak      NMI_Handler\r\n   .thumb_set NMI_Handler,Default_Handler\r\n  \r\n   .weak      HardFault_Handler\r\n   .thumb_set HardFault_Handler,Default_Handler\r\n  \r\n   .weak      MemManage_Handler\r\n   .thumb_set MemManage_Handler,Default_Handler\r\n  \r\n   .weak      BusFault_Handler\r\n   .thumb_set BusFault_Handler,Default_Handler\r\n\r\n   .weak      UsageFault_Handler\r\n   .thumb_set UsageFault_Handler,Default_Handler\r\n\r\n   .weak      SVC_Handler\r\n   .thumb_set SVC_Handler,Default_Handler\r\n\r\n   .weak      DebugMon_Handler\r\n   .thumb_set DebugMon_Handler,Default_Handler\r\n\r\n   .weak      PendSV_Handler\r\n   .thumb_set PendSV_Handler,Default_Handler\r\n\r\n   .weak      SysTick_Handler\r\n   .thumb_set SysTick_Handler,Default_Handler              \r\n  \r\n   .weak      WWDG_IRQHandler                   \r\n   .thumb_set WWDG_IRQHandler,Default_Handler      \r\n                  \r\n   .weak      PVD_IRQHandler      \r\n   .thumb_set PVD_IRQHandler,Default_Handler\r\n               \r\n   .weak      TAMP_STAMP_IRQHandler            \r\n   .thumb_set TAMP_STAMP_IRQHandler,Default_Handler\r\n            \r\n   .weak      RTC_WKUP_IRQHandler                  \r\n   .thumb_set RTC_WKUP_IRQHandler,Default_Handler\r\n            \r\n   .weak      FLASH_IRQHandler         \r\n   .thumb_set FLASH_IRQHandler,Default_Handler\r\n                  \r\n   .weak      RCC_IRQHandler      \r\n   .thumb_set RCC_IRQHandler,Default_Handler\r\n                  \r\n   .weak      EXTI0_IRQHandler         \r\n   .thumb_set EXTI0_IRQHandler,Default_Handler\r\n                  \r\n   .weak      EXTI1_IRQHandler         \r\n   .thumb_set EXTI1_IRQHandler,Default_Handler\r\n                     \r\n   .weak      EXTI2_IRQHandler         \r\n   .thumb_set EXTI2_IRQHandler,Default_Handler \r\n                 \r\n   .weak      EXTI3_IRQHandler         \r\n   .thumb_set EXTI3_IRQHandler,Default_Handler\r\n                        \r\n   .weak      EXTI4_IRQHandler         \r\n   .thumb_set EXTI4_IRQHandler,Default_Handler\r\n                  \r\n   .weak      DMA1_Stream0_IRQHandler               \r\n   .thumb_set DMA1_Stream0_IRQHandler,Default_Handler\r\n         \r\n   .weak      DMA1_Stream1_IRQHandler               \r\n   .thumb_set DMA1_Stream1_IRQHandler,Default_Handler\r\n                  \r\n   .weak      DMA1_Stream2_IRQHandler               \r\n   .thumb_set DMA1_Stream2_IRQHandler,Default_Handler\r\n                  \r\n   .weak      DMA1_Stream3_IRQHandler               \r\n   .thumb_set DMA1_Stream3_IRQHandler,Default_Handler \r\n                 \r\n   .weak      DMA1_Stream4_IRQHandler              \r\n   .thumb_set DMA1_Stream4_IRQHandler,Default_Handler\r\n                  \r\n   .weak      DMA1_Stream5_IRQHandler               \r\n   .thumb_set DMA1_Stream5_IRQHandler,Default_Handler\r\n                  \r\n   .weak      DMA1_Stream6_IRQHandler               \r\n   .thumb_set DMA1_Stream6_IRQHandler,Default_Handler\r\n                  \r\n   .weak      ADC_IRQHandler      \r\n   .thumb_set ADC_IRQHandler,Default_Handler\r\n               \r\n   .weak      CAN1_TX_IRQHandler   \r\n   .thumb_set CAN1_TX_IRQHandler,Default_Handler\r\n            \r\n   .weak      CAN1_RX0_IRQHandler                  \r\n   .thumb_set CAN1_RX0_IRQHandler,Default_Handler\r\n                           \r\n   .weak      CAN1_RX1_IRQHandler                  \r\n   .thumb_set CAN1_RX1_IRQHandler,Default_Handler\r\n            \r\n   .weak      CAN1_SCE_IRQHandler                  \r\n   .thumb_set CAN1_SCE_IRQHandler,Default_Handler\r\n            \r\n   .weak      EXTI9_5_IRQHandler   \r\n   .thumb_set EXTI9_5_IRQHandler,Default_Handler\r\n            \r\n   .weak      TIM1_BRK_TIM9_IRQHandler            \r\n   .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler\r\n            \r\n   .weak      TIM1_UP_TIM10_IRQHandler            \r\n   .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler\r\n\r\n   .weak      TIM1_TRG_COM_TIM11_IRQHandler      \r\n   .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler\r\n      \r\n   .weak      TIM1_CC_IRQHandler   \r\n   .thumb_set TIM1_CC_IRQHandler,Default_Handler\r\n                  \r\n   .weak      TIM2_IRQHandler            \r\n   .thumb_set TIM2_IRQHandler,Default_Handler\r\n                  \r\n   .weak      TIM3_IRQHandler            \r\n   .thumb_set TIM3_IRQHandler,Default_Handler\r\n                  \r\n   .weak      TIM4_IRQHandler            \r\n   .thumb_set TIM4_IRQHandler,Default_Handler\r\n                  \r\n   .weak      I2C1_EV_IRQHandler   \r\n   .thumb_set I2C1_EV_IRQHandler,Default_Handler\r\n                     \r\n   .weak      I2C1_ER_IRQHandler   \r\n   .thumb_set I2C1_ER_IRQHandler,Default_Handler\r\n                     \r\n   .weak      I2C2_EV_IRQHandler   \r\n   .thumb_set I2C2_EV_IRQHandler,Default_Handler\r\n                  \r\n   .weak      I2C2_ER_IRQHandler   \r\n   .thumb_set I2C2_ER_IRQHandler,Default_Handler\r\n                           \r\n   .weak      SPI1_IRQHandler            \r\n   .thumb_set SPI1_IRQHandler,Default_Handler\r\n                        \r\n   .weak      SPI2_IRQHandler            \r\n   .thumb_set SPI2_IRQHandler,Default_Handler\r\n                  \r\n   .weak      USART1_IRQHandler      \r\n   .thumb_set USART1_IRQHandler,Default_Handler\r\n                     \r\n   .weak      USART2_IRQHandler      \r\n   .thumb_set USART2_IRQHandler,Default_Handler\r\n                     \r\n   .weak      USART3_IRQHandler      \r\n   .thumb_set USART3_IRQHandler,Default_Handler\r\n                  \r\n   .weak      EXTI15_10_IRQHandler               \r\n   .thumb_set EXTI15_10_IRQHandler,Default_Handler\r\n               \r\n   .weak      RTC_Alarm_IRQHandler               \r\n   .thumb_set RTC_Alarm_IRQHandler,Default_Handler\r\n            \r\n   .weak      OTG_FS_WKUP_IRQHandler         \r\n   .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler\r\n            \r\n   .weak      TIM8_BRK_TIM12_IRQHandler         \r\n   .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler\r\n         \r\n   .weak      TIM8_UP_TIM13_IRQHandler            \r\n   .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler\r\n         \r\n   .weak      TIM8_TRG_COM_TIM14_IRQHandler      \r\n   .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler\r\n      \r\n   .weak      TIM8_CC_IRQHandler   \r\n   .thumb_set TIM8_CC_IRQHandler,Default_Handler\r\n                  \r\n   .weak      DMA1_Stream7_IRQHandler               \r\n   .thumb_set DMA1_Stream7_IRQHandler,Default_Handler\r\n                     \r\n   .weak      FMC_IRQHandler            \r\n   .thumb_set FMC_IRQHandler,Default_Handler\r\n                     \r\n   .weak      SDMMC1_IRQHandler            \r\n   .thumb_set SDMMC1_IRQHandler,Default_Handler\r\n                     \r\n   .weak      TIM5_IRQHandler            \r\n   .thumb_set TIM5_IRQHandler,Default_Handler\r\n                     \r\n   .weak      SPI3_IRQHandler            \r\n   .thumb_set SPI3_IRQHandler,Default_Handler\r\n                     \r\n   .weak      UART4_IRQHandler         \r\n   .thumb_set UART4_IRQHandler,Default_Handler\r\n                  \r\n   .weak      UART5_IRQHandler         \r\n   .thumb_set UART5_IRQHandler,Default_Handler\r\n                  \r\n   .weak      TIM6_DAC_IRQHandler                  \r\n   .thumb_set TIM6_DAC_IRQHandler,Default_Handler\r\n               \r\n   .weak      TIM7_IRQHandler            \r\n   .thumb_set TIM7_IRQHandler,Default_Handler\r\n         \r\n   .weak      DMA2_Stream0_IRQHandler               \r\n   .thumb_set DMA2_Stream0_IRQHandler,Default_Handler\r\n               \r\n   .weak      DMA2_Stream1_IRQHandler               \r\n   .thumb_set DMA2_Stream1_IRQHandler,Default_Handler\r\n                  \r\n   .weak      DMA2_Stream2_IRQHandler               \r\n   .thumb_set DMA2_Stream2_IRQHandler,Default_Handler\r\n            \r\n   .weak      DMA2_Stream3_IRQHandler               \r\n   .thumb_set DMA2_Stream3_IRQHandler,Default_Handler\r\n            \r\n   .weak      DMA2_Stream4_IRQHandler               \r\n   .thumb_set DMA2_Stream4_IRQHandler,Default_Handler\r\n   \r\n   .weak      DMA2_Stream4_IRQHandler               \r\n   .thumb_set DMA2_Stream4_IRQHandler,Default_Handler   \r\n\r\n   .weak      ETH_IRQHandler   \r\n   .thumb_set ETH_IRQHandler,Default_Handler\r\n   \r\n   .weak      ETH_WKUP_IRQHandler   \r\n   .thumb_set ETH_WKUP_IRQHandler,Default_Handler\r\n\r\n   .weak      CAN2_TX_IRQHandler   \r\n   .thumb_set CAN2_TX_IRQHandler,Default_Handler   \r\n                           \r\n   .weak      CAN2_RX0_IRQHandler                  \r\n   .thumb_set CAN2_RX0_IRQHandler,Default_Handler\r\n                           \r\n   .weak      CAN2_RX1_IRQHandler                  \r\n   .thumb_set CAN2_RX1_IRQHandler,Default_Handler\r\n                           \r\n   .weak      CAN2_SCE_IRQHandler                  \r\n   .thumb_set CAN2_SCE_IRQHandler,Default_Handler\r\n                           \r\n   .weak      OTG_FS_IRQHandler      \r\n   .thumb_set OTG_FS_IRQHandler,Default_Handler\r\n                     \r\n   .weak      DMA2_Stream5_IRQHandler               \r\n   .thumb_set DMA2_Stream5_IRQHandler,Default_Handler\r\n                  \r\n   .weak      DMA2_Stream6_IRQHandler               \r\n   .thumb_set DMA2_Stream6_IRQHandler,Default_Handler\r\n                  \r\n   .weak      DMA2_Stream7_IRQHandler               \r\n   .thumb_set DMA2_Stream7_IRQHandler,Default_Handler\r\n                  \r\n   .weak      USART6_IRQHandler      \r\n   .thumb_set USART6_IRQHandler,Default_Handler\r\n                        \r\n   .weak      I2C3_EV_IRQHandler   \r\n   .thumb_set I2C3_EV_IRQHandler,Default_Handler\r\n                        \r\n   .weak      I2C3_ER_IRQHandler   \r\n   .thumb_set I2C3_ER_IRQHandler,Default_Handler\r\n                        \r\n   .weak      OTG_HS_EP1_OUT_IRQHandler         \r\n   .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler\r\n               \r\n   .weak      OTG_HS_EP1_IN_IRQHandler            \r\n   .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler\r\n               \r\n   .weak      OTG_HS_WKUP_IRQHandler         \r\n   .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler\r\n            \r\n   .weak      OTG_HS_IRQHandler      \r\n   .thumb_set OTG_HS_IRQHandler,Default_Handler\r\n                  \r\n   .weak      DCMI_IRQHandler            \r\n   .thumb_set DCMI_IRQHandler,Default_Handler\r\n\r\n   .weak      RNG_IRQHandler            \r\n   .thumb_set RNG_IRQHandler,Default_Handler   \r\n\r\n   .weak      FPU_IRQHandler                  \r\n   .thumb_set FPU_IRQHandler,Default_Handler\r\n\r\n   .weak      UART7_IRQHandler                  \r\n   .thumb_set UART7_IRQHandler,Default_Handler\r\n\r\n   .weak      UART8_IRQHandler                  \r\n   .thumb_set UART8_IRQHandler,Default_Handler   \r\n\r\n   .weak      SPI4_IRQHandler            \r\n   .thumb_set SPI4_IRQHandler,Default_Handler\r\n   \r\n   .weak      SPI5_IRQHandler            \r\n   .thumb_set SPI5_IRQHandler,Default_Handler\r\n\r\n   .weak      SPI6_IRQHandler            \r\n   .thumb_set SPI6_IRQHandler,Default_Handler   \r\n\r\n   .weak      SAI1_IRQHandler            \r\n   .thumb_set SAI1_IRQHandler,Default_Handler\r\n   \r\n   .weak      LTDC_IRQHandler            \r\n   .thumb_set LTDC_IRQHandler,Default_Handler\r\n\r\n   .weak      LTDC_ER_IRQHandler            \r\n   .thumb_set LTDC_ER_IRQHandler,Default_Handler\r\n\r\n   .weak      DMA2D_IRQHandler            \r\n   .thumb_set DMA2D_IRQHandler,Default_Handler   \r\n\r\n   .weak      SAI2_IRQHandler            \r\n   .thumb_set SAI2_IRQHandler,Default_Handler\r\n   \r\n   .weak      QUADSPI_IRQHandler            \r\n   .thumb_set QUADSPI_IRQHandler,Default_Handler\r\n \r\n   .weak      LPTIM1_IRQHandler            \r\n   .thumb_set LPTIM1_IRQHandler,Default_Handler\r\n\r\n   .weak      CEC_IRQHandler            \r\n   .thumb_set CEC_IRQHandler,Default_Handler\r\n   \r\n   .weak      I2C4_EV_IRQHandler            \r\n   .thumb_set I2C4_EV_IRQHandler,Default_Handler \r\n \r\n   .weak      I2C4_ER_IRQHandler            \r\n   .thumb_set I2C4_ER_IRQHandler,Default_Handler\r\n   \r\n   .weak      SPDIF_RX_IRQHandler            \r\n   .thumb_set SPDIF_RX_IRQHandler,Default_Handler \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/        \r\n \r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/cfg/stm32f746xx.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f746xx.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer Header File.\r\n  *\r\n  *          This file contains:\r\n  *           - Data structures and the address mapping for all peripherals\r\n  *           - Peripheral's registers declarations and bits definition\r\n  *           - Macros to access peripherals registers hardware\r\n  *\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/** @addtogroup CMSIS_Device\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup stm32f746xx\r\n  * @{\r\n  */\r\n    \r\n#ifndef __STM32F746xx_H\r\n#define __STM32F746xx_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif /* __cplusplus */\r\n  \r\n/** @addtogroup Configuration_section_for_CMSIS\r\n  * @{\r\n  */\r\n\r\n/**\r\n * @brief STM32F7xx Interrupt Number Definition, according to the selected device \r\n *        in @ref Library_configuration_section \r\n */\r\ntypedef enum\r\n{\r\n/******  Cortex-M7 Processor Exceptions Numbers ****************************************************************/\r\n  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */\r\n  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M7 Memory Management Interrupt                           */\r\n  BusFault_IRQn               = -11,    /*!< 5 Cortex-M7 Bus Fault Interrupt                                   */\r\n  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M7 Usage Fault Interrupt                                 */\r\n  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M7 SV Call Interrupt                                    */\r\n  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M7 Debug Monitor Interrupt                              */\r\n  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M7 Pend SV Interrupt                                    */\r\n  SysTick_IRQn                = -1,     /*!< 15 Cortex-M7 System Tick Interrupt                                */\r\n/******  STM32 specific Interrupt Numbers **********************************************************************/\r\n  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */\r\n  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */\r\n  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */\r\n  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */\r\n  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */\r\n  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */\r\n  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */\r\n  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */\r\n  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */\r\n  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */\r\n  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */\r\n  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */\r\n  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */\r\n  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */\r\n  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */\r\n  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */\r\n  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */\r\n  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */\r\n  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */\r\n  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */\r\n  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */\r\n  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */\r\n  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */\r\n  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */\r\n  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */\r\n  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */\r\n  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */\r\n  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */\r\n  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */\r\n  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */\r\n  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */\r\n  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */\r\n  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */\r\n  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */\r\n  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  \r\n  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */\r\n  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */\r\n  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */\r\n  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */\r\n  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */\r\n  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */\r\n  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */\r\n  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */    \r\n  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */\r\n  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */\r\n  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */\r\n  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */\r\n  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */\r\n  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */\r\n  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */\r\n  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */\r\n  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */\r\n  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */\r\n  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */\r\n  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */\r\n  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */\r\n  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */\r\n  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */\r\n  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */\r\n  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */\r\n  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */\r\n  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */\r\n  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */\r\n  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */\r\n  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */\r\n  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */\r\n  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */\r\n  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */\r\n  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */\r\n  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */\r\n  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */\r\n  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */\r\n  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */\r\n  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */\r\n  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */\r\n  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */\r\n  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */\r\n  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */\r\n  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */\r\n  RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */\r\n  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */\r\n  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */\r\n  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */\r\n  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */\r\n  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */\r\n  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */\r\n  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */\r\n  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */\r\n  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */\r\n  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */\r\n  SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */\r\n  QUADSPI_IRQn                = 92,     /*!< Quad SPI global interrupt                                         */\r\n  LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */\r\n  CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */\r\n  I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */\r\n  I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */\r\n  SPDIF_RX_IRQn               = 97,     /*!< SPDIF-RX global Interrupt                                         */\r\n} IRQn_Type;\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n * @brief Configuration of the Cortex-M7 Processor and Core Peripherals \r\n */\r\n#define __CM7_REV                 0x0001U  /*!< Cortex-M7 revision r0p1                       */\r\n#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */\r\n#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */\r\n#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */\r\n#define __FPU_PRESENT             1       /*!< FPU present                                   */\r\n#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */\r\n#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */\r\n#include \"core_cm7.h\"                     /*!< Cortex-M7 processor and core peripherals      */\r\n  \r\n  \r\n#include \"system_stm32f7xx.h\"\r\n#include <stdint.h>\r\n\r\n/** @addtogroup Peripheral_registers_structures\r\n  * @{\r\n  */   \r\n\r\n/** \r\n  * @brief Analog to Digital Converter  \r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */\r\n  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */      \r\n  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */\r\n  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */\r\n  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */\r\n  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */\r\n  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */\r\n  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */\r\n  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */\r\n  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */\r\n  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */\r\n  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */\r\n  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */\r\n  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */\r\n  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/\r\n  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */\r\n  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */\r\n  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */\r\n  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */\r\n  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */\r\n} ADC_TypeDef;\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */\r\n  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */\r\n  __IO uint32_t CDR;    /*!< ADC common regular data register for dual\r\n                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */\r\n} ADC_Common_TypeDef;\r\n\r\n\r\n/** \r\n  * @brief Controller Area Network TxMailBox \r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */\r\n  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */\r\n  __IO uint32_t TDLR; /*!< CAN mailbox data low register */\r\n  __IO uint32_t TDHR; /*!< CAN mailbox data high register */\r\n} CAN_TxMailBox_TypeDef;\r\n\r\n/** \r\n  * @brief Controller Area Network FIFOMailBox \r\n  */\r\n  \r\ntypedef struct\r\n{\r\n  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */\r\n  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */\r\n  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */\r\n  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */\r\n} CAN_FIFOMailBox_TypeDef;\r\n\r\n/** \r\n  * @brief Controller Area Network FilterRegister \r\n  */\r\n  \r\ntypedef struct\r\n{\r\n  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */\r\n  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */\r\n} CAN_FilterRegister_TypeDef;\r\n\r\n/** \r\n  * @brief Controller Area Network \r\n  */\r\n  \r\ntypedef struct\r\n{\r\n  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */\r\n  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */\r\n  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */\r\n  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */\r\n  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */\r\n  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */\r\n  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */\r\n  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */\r\n  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */\r\n  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */\r\n  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */\r\n  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */\r\n  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */\r\n  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */\r\n  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */\r\n  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */\r\n  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */\r\n  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */\r\n  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */\r\n  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */\r\n  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ \r\n  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */\r\n} CAN_TypeDef;\r\n\r\n/** \r\n  * @brief HDMI-CEC \r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;           /*!< CEC control register,                                       Address offset:0x00 */\r\n  __IO uint32_t CFGR;         /*!< CEC configuration register,                                 Address offset:0x04 */\r\n  __IO uint32_t TXDR;         /*!< CEC Tx data register ,                                      Address offset:0x08 */\r\n  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,                                       Address offset:0x0C */\r\n  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register,                          Address offset:0x10 */\r\n  __IO uint32_t IER;          /*!< CEC interrupt enable register,                              Address offset:0x14 */\r\n}CEC_TypeDef;\r\n\r\n\r\n/** \r\n  * @brief CRC calculation unit \r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t  DR;          /*!< CRC Data register,                           Address offset: 0x00 */\r\n  __IO uint8_t   IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */\r\n  uint8_t        RESERVED0;   /*!< Reserved, 0x05                                                    */\r\n  uint16_t       RESERVED1;   /*!< Reserved, 0x06                                                    */\r\n  __IO uint32_t  CR;          /*!< CRC Control register,                        Address offset: 0x08 */\r\n  uint32_t       RESERVED2;   /*!< Reserved,                                                    0x0C */\r\n  __IO uint32_t  INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */\r\n  __IO uint32_t  POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */\r\n} CRC_TypeDef;\r\n\r\n/** \r\n  * @brief Digital to Analog Converter\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */\r\n  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */\r\n  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */\r\n  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */\r\n  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */\r\n  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */\r\n  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */\r\n  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */\r\n  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */\r\n  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */\r\n  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */\r\n  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */\r\n  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */\r\n  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */\r\n} DAC_TypeDef;\r\n\r\n\r\n/** \r\n  * @brief Debug MCU\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */\r\n  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */\r\n  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */\r\n  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */\r\n}DBGMCU_TypeDef;\r\n\r\n/** \r\n  * @brief DCMI\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */\r\n  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */\r\n  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */\r\n  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */\r\n  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */\r\n  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */\r\n  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */\r\n  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */\r\n  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */\r\n  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */\r\n  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */\r\n} DCMI_TypeDef;\r\n\r\n/** \r\n  * @brief DMA Controller\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;     /*!< DMA stream x configuration register      */\r\n  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */\r\n  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */\r\n  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */\r\n  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */\r\n  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */\r\n} DMA_Stream_TypeDef;\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */\r\n  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */\r\n  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */\r\n  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */\r\n} DMA_TypeDef;\r\n\r\n\r\n/** \r\n  * @brief DMA2D Controller\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */\r\n  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */\r\n  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */\r\n  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */\r\n  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */\r\n  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */\r\n  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */\r\n  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */\r\n  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */\r\n  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */\r\n  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */\r\n  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */\r\n  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */\r\n  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */\r\n  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */\r\n  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */\r\n  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */\r\n  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */\r\n  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */\r\n  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */\r\n  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */\r\n  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */\r\n  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */\r\n} DMA2D_TypeDef;\r\n\r\n\r\n/** \r\n  * @brief Ethernet MAC\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t MACCR;\r\n  __IO uint32_t MACFFR;\r\n  __IO uint32_t MACHTHR;\r\n  __IO uint32_t MACHTLR;\r\n  __IO uint32_t MACMIIAR;\r\n  __IO uint32_t MACMIIDR;\r\n  __IO uint32_t MACFCR;\r\n  __IO uint32_t MACVLANTR;             /*    8 */\r\n  uint32_t      RESERVED0[2];\r\n  __IO uint32_t MACRWUFFR;             /*   11 */\r\n  __IO uint32_t MACPMTCSR;\r\n  uint32_t      RESERVED1[2];\r\n  __IO uint32_t MACSR;                 /*   15 */\r\n  __IO uint32_t MACIMR;\r\n  __IO uint32_t MACA0HR;\r\n  __IO uint32_t MACA0LR;\r\n  __IO uint32_t MACA1HR;\r\n  __IO uint32_t MACA1LR;\r\n  __IO uint32_t MACA2HR;\r\n  __IO uint32_t MACA2LR;\r\n  __IO uint32_t MACA3HR;\r\n  __IO uint32_t MACA3LR;               /*   24 */\r\n  uint32_t      RESERVED2[40];\r\n  __IO uint32_t MMCCR;                 /*   65 */\r\n  __IO uint32_t MMCRIR;\r\n  __IO uint32_t MMCTIR;\r\n  __IO uint32_t MMCRIMR;\r\n  __IO uint32_t MMCTIMR;               /*   69 */\r\n  uint32_t      RESERVED3[14];\r\n  __IO uint32_t MMCTGFSCCR;            /*   84 */\r\n  __IO uint32_t MMCTGFMSCCR;\r\n  uint32_t      RESERVED4[5];\r\n  __IO uint32_t MMCTGFCR;\r\n  uint32_t      RESERVED5[10];\r\n  __IO uint32_t MMCRFCECR;\r\n  __IO uint32_t MMCRFAECR;\r\n  uint32_t      RESERVED6[10];\r\n  __IO uint32_t MMCRGUFCR;\r\n  uint32_t      RESERVED7[334];\r\n  __IO uint32_t PTPTSCR;\r\n  __IO uint32_t PTPSSIR;\r\n  __IO uint32_t PTPTSHR;\r\n  __IO uint32_t PTPTSLR;\r\n  __IO uint32_t PTPTSHUR;\r\n  __IO uint32_t PTPTSLUR;\r\n  __IO uint32_t PTPTSAR;\r\n  __IO uint32_t PTPTTHR;\r\n  __IO uint32_t PTPTTLR;\r\n  __IO uint32_t RESERVED8;\r\n  __IO uint32_t PTPTSSR;\r\n  uint32_t      RESERVED9[565];\r\n  __IO uint32_t DMABMR;\r\n  __IO uint32_t DMATPDR;\r\n  __IO uint32_t DMARPDR;\r\n  __IO uint32_t DMARDLAR;\r\n  __IO uint32_t DMATDLAR;\r\n  __IO uint32_t DMASR;\r\n  __IO uint32_t DMAOMR;\r\n  __IO uint32_t DMAIER;\r\n  __IO uint32_t DMAMFBOCR;\r\n  __IO uint32_t DMARSWTR;\r\n  uint32_t      RESERVED10[8];\r\n  __IO uint32_t DMACHTDR;\r\n  __IO uint32_t DMACHRDR;\r\n  __IO uint32_t DMACHTBAR;\r\n  __IO uint32_t DMACHRBAR;\r\n} ETH_TypeDef;\r\n\r\n/** \r\n  * @brief External Interrupt/Event Controller\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */\r\n  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */\r\n  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */\r\n  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */\r\n  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */\r\n  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */\r\n} EXTI_TypeDef;\r\n\r\n/** \r\n  * @brief FLASH Registers\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t ACR;      /*!< FLASH access control register,     Address offset: 0x00 */\r\n  __IO uint32_t KEYR;     /*!< FLASH key register,                Address offset: 0x04 */\r\n  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,         Address offset: 0x08 */\r\n  __IO uint32_t SR;       /*!< FLASH status register,             Address offset: 0x0C */\r\n  __IO uint32_t CR;       /*!< FLASH control register,            Address offset: 0x10 */\r\n  __IO uint32_t OPTCR;    /*!< FLASH option control register ,    Address offset: 0x14 */\r\n  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1 ,  Address offset: 0x18 */\r\n} FLASH_TypeDef;\r\n\r\n\r\n\r\n/** \r\n  * @brief Flexible Memory Controller\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   \r\n} FMC_Bank1_TypeDef; \r\n\r\n/** \r\n  * @brief Flexible Memory Controller Bank1E\r\n  */\r\n  \r\ntypedef struct\r\n{\r\n  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */\r\n} FMC_Bank1E_TypeDef;\r\n\r\n/** \r\n  * @brief Flexible Memory Controller Bank3\r\n  */\r\n  \r\ntypedef struct\r\n{\r\n  __IO uint32_t PCR;        /*!< NAND Flash control register,                       Address offset: 0x80 */\r\n  __IO uint32_t SR;         /*!< NAND Flash FIFO status and interrupt register,     Address offset: 0x84 */\r\n  __IO uint32_t PMEM;       /*!< NAND Flash Common memory space timing register,    Address offset: 0x88 */\r\n  __IO uint32_t PATT;       /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */\r\n  uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                          */\r\n  __IO uint32_t ECCR;       /*!< NAND Flash ECC result registers,                   Address offset: 0x94 */\r\n} FMC_Bank3_TypeDef;\r\n \r\n/** \r\n  * @brief Flexible Memory Controller Bank5_6\r\n  */\r\n  \r\ntypedef struct\r\n{\r\n  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */\r\n  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */\r\n  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */\r\n  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */\r\n  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */\r\n} FMC_Bank5_6_TypeDef; \r\n\r\n\r\n/** \r\n  * @brief General Purpose I/O\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */\r\n  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */\r\n  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */\r\n  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */\r\n  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */\r\n  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */\r\n  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */\r\n  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */\r\n  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */\r\n} GPIO_TypeDef;\r\n\r\n/** \r\n  * @brief System configuration controller\r\n  */\r\n  \r\ntypedef struct\r\n{\r\n  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */\r\n  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */\r\n  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */\r\n  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */\r\n  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */\r\n} SYSCFG_TypeDef;\r\n\r\n/** \r\n  * @brief Inter-integrated Circuit Interface\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */\r\n  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */  \r\n  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */\r\n  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */\r\n  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */\r\n  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */\r\n  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */\r\n  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */\r\n  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */\r\n  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */\r\n  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */  \r\n} I2C_TypeDef;\r\n\r\n/** \r\n  * @brief Independent WATCHDOG\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */\r\n  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */\r\n  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */\r\n  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */\r\n  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */\r\n} IWDG_TypeDef;\r\n\r\n\r\n/** \r\n  * @brief LCD-TFT Display Controller\r\n  */\r\n  \r\ntypedef struct\r\n{\r\n  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04 */\r\n  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */\r\n  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */\r\n  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */\r\n  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */\r\n  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */\r\n  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20 */\r\n  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */\r\n  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28 */\r\n  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */\r\n  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30 */\r\n  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */\r\n  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */\r\n  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */\r\n  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */\r\n  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */\r\n  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */\r\n} LTDC_TypeDef;  \r\n\r\n/** \r\n  * @brief LCD-TFT Display layer x Controller\r\n  */\r\n  \r\ntypedef struct\r\n{  \r\n  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */\r\n  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */\r\n  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */\r\n  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */\r\n  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */\r\n  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */\r\n  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */\r\n  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */\r\n  uint32_t      RESERVED0[2];  /*!< Reserved */\r\n  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */\r\n  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */\r\n  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */\r\n  uint32_t      RESERVED1[3];  /*!< Reserved */\r\n  __IO uint32_t CLUTWR;        /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */\r\n\r\n} LTDC_Layer_TypeDef;\r\n\r\n/** \r\n  * @brief Power Control\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR1;   /*!< PWR power control register 1,        Address offset: 0x00 */\r\n  __IO uint32_t CSR1;  /*!< PWR power control/status register 2, Address offset: 0x04 */\r\n  __IO uint32_t CR2;   /*!< PWR power control register 2,        Address offset: 0x08 */\r\n  __IO uint32_t CSR2;  /*!< PWR power control/status register 2, Address offset: 0x0C */\r\n} PWR_TypeDef;\r\n\r\n\r\n/** \r\n  * @brief Reset and Clock Control\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */\r\n  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */\r\n  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */\r\n  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */\r\n  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */\r\n  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */\r\n  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */\r\n  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */\r\n  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */\r\n  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */\r\n  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */\r\n  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */\r\n  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */\r\n  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */\r\n  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */\r\n  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */\r\n  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */\r\n  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */\r\n  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */\r\n  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */\r\n  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */\r\n  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */\r\n  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */\r\n  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */\r\n  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */\r\n  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */\r\n  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */\r\n  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */\r\n  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */\r\n  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */\r\n  __IO uint32_t PLLSAICFGR;    /*!< RCC PLLSAI configuration register,                           Address offset: 0x88 */\r\n  __IO uint32_t DCKCFGR1;      /*!< RCC Dedicated Clocks configuration register1,                 Address offset: 0x8C */\r\n  __IO uint32_t DCKCFGR2;      /*!< RCC Dedicated Clocks configuration register 2,               Address offset: 0x90 */\r\n\r\n} RCC_TypeDef;\r\n\r\n/** \r\n  * @brief Real-Time Clock\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */\r\n  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */\r\n  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */                                                                                            \r\n  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */\r\n  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */\r\n  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */\r\n       uint32_t reserved;   /*!< Reserved  */\r\n  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */\r\n  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */\r\n  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */\r\n  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */\r\n  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */\r\n  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */\r\n  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */\r\n  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */\r\n  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */\r\n  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */\r\n  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */\r\n  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */\r\n  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset: 0x4C */\r\n  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */\r\n  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */\r\n  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */\r\n  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */\r\n  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */\r\n  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */\r\n  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */\r\n  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */\r\n  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */\r\n  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */\r\n  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */\r\n  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */\r\n  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */\r\n  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */\r\n  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */\r\n  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */\r\n  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */\r\n  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */\r\n  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */\r\n  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */\r\n  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */\r\n  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */\r\n  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */\r\n  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */\r\n  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */\r\n  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */\r\n  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */\r\n  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */\r\n  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */\r\n  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */\r\n  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */\r\n  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */\r\n} RTC_TypeDef;\r\n\r\n\r\n/** \r\n  * @brief Serial Audio Interface\r\n  */\r\n  \r\ntypedef struct\r\n{\r\n  __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */\r\n} SAI_TypeDef;\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */\r\n  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */\r\n  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */\r\n  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */\r\n  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */\r\n  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */\r\n  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */\r\n  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */\r\n} SAI_Block_TypeDef;\r\n\r\n/** \r\n  * @brief SPDIF-RX Interface\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */\r\n  __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */  \r\n  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */\r\n  __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */ \r\n  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */\r\n  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */\r\n  __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */\r\n} SPDIFRX_TypeDef;\r\n\r\n\r\n/** \r\n  * @brief SD host Interface\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t POWER;          /*!< SDMMC power control register,    Address offset: 0x00 */\r\n  __IO uint32_t CLKCR;          /*!< SDMMClock control register,     Address offset: 0x04 */\r\n  __IO uint32_t ARG;            /*!< SDMMC argument register,         Address offset: 0x08 */\r\n  __IO uint32_t CMD;            /*!< SDMMC command register,          Address offset: 0x0C */\r\n  __I uint32_t  RESPCMD;        /*!< SDMMC command response register, Address offset: 0x10 */\r\n  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,       Address offset: 0x14 */\r\n  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,       Address offset: 0x18 */\r\n  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,       Address offset: 0x1C */\r\n  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,       Address offset: 0x20 */\r\n  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,       Address offset: 0x24 */\r\n  __IO uint32_t DLEN;           /*!< SDMMC data length register,      Address offset: 0x28 */\r\n  __IO uint32_t DCTRL;          /*!< SDMMC data control register,     Address offset: 0x2C */\r\n  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,     Address offset: 0x30 */\r\n  __I uint32_t  STA;            /*!< SDMMC status register,           Address offset: 0x34 */\r\n  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,  Address offset: 0x38 */\r\n  __IO uint32_t MASK;           /*!< SDMMC mask register,             Address offset: 0x3C */\r\n  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */\r\n  __I uint32_t  FIFOCNT;        /*!< SDMMC FIFO counter register,     Address offset: 0x48 */\r\n  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */\r\n  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,        Address offset: 0x80 */\r\n} SDMMC_TypeDef;\r\n\r\n/** \r\n  * @brief Serial Peripheral Interface\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */\r\n  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */\r\n  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */\r\n  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */\r\n  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */\r\n  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */\r\n  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */\r\n  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */\r\n  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */\r\n} SPI_TypeDef;\r\n\r\n/** \r\n  * @brief QUAD Serial Peripheral Interface\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */\r\n  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */\r\n  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */\r\n  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */\r\n  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */\r\n  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */\r\n  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */\r\n  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */\r\n  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */\r\n  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */\r\n  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */                  \r\n  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */\r\n  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */    \r\n} QUADSPI_TypeDef;\r\n\r\n/** \r\n  * @brief TIM\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */\r\n  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */\r\n  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */\r\n  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */\r\n  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */\r\n  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */\r\n  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */\r\n  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */\r\n  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */\r\n  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */\r\n  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */\r\n  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */\r\n  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */\r\n  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */\r\n  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */\r\n  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */\r\n  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */\r\n  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */\r\n  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */\r\n  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */\r\n  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */\r\n  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */\r\n  __IO uint32_t CCR5;        /*!< TIM capture/compare mode register5,       Address offset: 0x58 */\r\n  __IO uint32_t CCR6;        /*!< TIM capture/compare mode register6,       Address offset: 0x5C */\r\n\r\n} TIM_TypeDef;\r\n\r\n/** \r\n  * @brief LPTIMIMER\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */\r\n  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */\r\n  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */\r\n  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                       Address offset: 0x0C */\r\n  __IO uint32_t CR;       /*!< LPTIM Control register,                             Address offset: 0x10 */\r\n  __IO uint32_t CMP;      /*!< LPTIM Compare register,                             Address offset: 0x14 */\r\n  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                          Address offset: 0x18 */\r\n  __IO uint32_t CNT;      /*!< LPTIM Counter register,                             Address offset: 0x1C */\r\n} LPTIM_TypeDef;\r\n\r\n\r\n/** \r\n  * @brief Universal Synchronous Asynchronous Receiver Transmitter\r\n  */\r\n \r\ntypedef struct\r\n{\r\n  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ \r\n  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ \r\n  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */\r\n  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */                                               \r\n  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */\r\n  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  \r\n  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */\r\n  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */\r\n  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */\r\n  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */\r\n  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */\r\n} USART_TypeDef;\r\n\r\n\r\n/** \r\n  * @brief Window WATCHDOG\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */\r\n  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */\r\n  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */\r\n} WWDG_TypeDef;\r\n\r\n\r\n/** \r\n  * @brief RNG\r\n  */\r\n  \r\ntypedef struct \r\n{\r\n  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */\r\n  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */\r\n  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */\r\n} RNG_TypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** \r\n  * @brief USB_OTG_Core_Registers\r\n  */\r\ntypedef struct\r\n{\r\n __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */\r\n  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */\r\n  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */\r\n  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */\r\n  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */\r\n  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */\r\n  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */\r\n  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */\r\n  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */\r\n  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */\r\n  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */\r\n  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */\r\n  uint32_t Reserved30[2];             /*!< Reserved                                     030h */\r\n  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */\r\n  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */\r\n  uint32_t  Reserved5[3];             /*!< Reserved                                040h-048h */\r\n  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */\r\n  uint32_t  Reserved6;                /*!< Reserved                                     050h */ \r\n  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */\r\n  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */\r\n  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */\r\n   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */\r\n    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */\r\n  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */\r\n  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */\r\n} USB_OTG_GlobalTypeDef;\r\n\r\n\r\n/** \r\n  * @brief USB_OTG_device_Registers\r\n  */\r\ntypedef struct \r\n{\r\n  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */\r\n  __IO uint32_t DCTL;            /*!< dev Control Register         804h */\r\n  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */\r\n  uint32_t Reserved0C;           /*!< Reserved                     80Ch */\r\n  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */\r\n  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */\r\n  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */\r\n  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */\r\n  uint32_t  Reserved20;          /*!< Reserved                     820h */\r\n  uint32_t Reserved9;            /*!< Reserved                     824h */\r\n  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */\r\n  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */\r\n  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */\r\n  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */\r\n  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */\r\n  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */  \r\n  uint32_t Reserved40;           /*!< dedicated EP mask            840h */\r\n  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */\r\n  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */\r\n  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */   \r\n} USB_OTG_DeviceTypeDef;\r\n\r\n\r\n/** \r\n  * @brief USB_OTG_IN_Endpoint-Specific_Register\r\n  */\r\ntypedef struct \r\n{\r\n  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */\r\n  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */\r\n  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */\r\n  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */\r\n  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */\r\n  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */\r\n  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */\r\n  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */\r\n} USB_OTG_INEndpointTypeDef;\r\n\r\n\r\n/** \r\n  * @brief USB_OTG_OUT_Endpoint-Specific_Registers\r\n  */\r\ntypedef struct \r\n{\r\n  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */\r\n  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */\r\n  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */\r\n  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */\r\n  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */\r\n  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */\r\n  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */\r\n} USB_OTG_OUTEndpointTypeDef;\r\n\r\n\r\n/** \r\n  * @brief USB_OTG_Host_Mode_Register_Structures\r\n  */\r\ntypedef struct \r\n{\r\n  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */\r\n  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */\r\n  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */\r\n  uint32_t Reserved40C;           /*!< Reserved                             40Ch */\r\n  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */\r\n  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */\r\n  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */\r\n} USB_OTG_HostTypeDef;\r\n\r\n/** \r\n  * @brief USB_OTG_Host_Channel_Specific_Registers\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */\r\n  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */\r\n  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */\r\n  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */\r\n  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */\r\n  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */\r\n  uint32_t Reserved[2];           /*!< Reserved                                      */\r\n} USB_OTG_HostChannelTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n\r\n\r\n/** @addtogroup Peripheral_memory_map\r\n  * @{\r\n  */\r\n#define RAMITCM_BASE           0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM  */\r\n#define FLASHITCM_BASE         0x00200000U /*!< Base address of : (up to 1 MB) embedded FLASH memory  accessible over ITCM              */                       \r\n#define FLASHAXI_BASE          0x08000000U /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI                */                       \r\n#define RAMDTCM_BASE           0x20000000U /*!< Base address of : 64KB system data RAM accessible over DTCM                             */\r\n#define PERIPH_BASE            0x40000000U /*!< Base address of : AHB/ABP Peripherals                                                   */\r\n#define BKPSRAM_BASE           0x40024000U /*!< Base address of : Backup SRAM(4 KB)                                                     */\r\n#define QSPI_BASE              0x90000000U /*!< Base address of : QSPI memories  accessible over AXI                                    */\r\n#define FMC_R_BASE             0xA0000000U /*!< Base address of : FMC Control registers                                                 */\r\n#define QSPI_R_BASE            0xA0001000U /*!< Base address of : QSPI Control  registers                                               */\r\n#define SRAM1_BASE             0x20010000U /*!< Base address of : 240KB RAM1 accessible over AXI/AHB                                    */\r\n#define SRAM2_BASE             0x2004C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB                                     */\r\n#define FLASH_END              0x080FFFFFU /*!< FLASH end address */\r\n\r\n/* Legacy define */\r\n#define FLASH_BASE     FLASHAXI_BASE\r\n\r\n/*!< Peripheral memory map */\r\n#define APB1PERIPH_BASE        PERIPH_BASE\r\n#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)\r\n#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)\r\n#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)\r\n\r\n/*!< APB1 peripherals */\r\n#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)\r\n#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)\r\n#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)\r\n#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)\r\n#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)\r\n#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)\r\n#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800U)\r\n#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00U)\r\n#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000U)\r\n#define LPTIM1_BASE           (APB1PERIPH_BASE + 0x2400U)\r\n#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)\r\n#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)\r\n#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)\r\n#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)\r\n#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)\r\n#define SPDIFRX_BASE          (APB1PERIPH_BASE + 0x4000U)\r\n#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)\r\n#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)\r\n#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)\r\n#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)\r\n#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)\r\n#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)\r\n#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)\r\n#define I2C4_BASE             (APB1PERIPH_BASE + 0x6000U)\r\n#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)\r\n#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)\r\n#define CEC_BASE              (APB1PERIPH_BASE + 0x6C00U)\r\n#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)\r\n#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)\r\n#define UART7_BASE            (APB1PERIPH_BASE + 0x7800U)\r\n#define UART8_BASE            (APB1PERIPH_BASE + 0x7C00U)\r\n\r\n/*!< APB2 peripherals */\r\n#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)\r\n#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400U)\r\n#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)\r\n#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)\r\n#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)\r\n#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100U)\r\n#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200U)\r\n#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)\r\n#define SDMMC1_BASE           (APB2PERIPH_BASE + 0x2C00U)\r\n#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)\r\n#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400U)\r\n#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)\r\n#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)\r\n#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)\r\n#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)\r\n#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)\r\n#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000U)\r\n#define SPI6_BASE             (APB2PERIPH_BASE + 0x5400U)\r\n#define SAI1_BASE             (APB2PERIPH_BASE + 0x5800U)\r\n#define SAI2_BASE             (APB2PERIPH_BASE + 0x5C00U)\r\n#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004U)\r\n#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024U)\r\n#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004U)\r\n#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024U)\r\n#define LTDC_BASE             (APB2PERIPH_BASE + 0x6800U)\r\n#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84U)\r\n#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104U)\r\n/*!< AHB1 peripherals */\r\n#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)\r\n#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)\r\n#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)\r\n#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)\r\n#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)\r\n#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400U)\r\n#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800U)\r\n#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)\r\n#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000U)\r\n#define GPIOJ_BASE            (AHB1PERIPH_BASE + 0x2400U)\r\n#define GPIOK_BASE            (AHB1PERIPH_BASE + 0x2800U)\r\n#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)\r\n#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)\r\n#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)\r\n#define UID_BASE              0x1FF0F420U                   /*!< Unique device ID register base address */\r\n#define FLASHSIZE_BASE        0x1FF0F442U                   /*!< FLASH Size register base address */\r\n#define PACKAGESIZE_BASE      0x1FFF7BF0U                   /*!< Package size register base address */\r\n#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)\r\n#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)\r\n#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)\r\n#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)\r\n#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)\r\n#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)\r\n#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)\r\n#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)\r\n#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)\r\n#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)\r\n#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)\r\n#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)\r\n#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)\r\n#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)\r\n#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)\r\n#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)\r\n#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)\r\n#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)\r\n#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000U)\r\n#define ETH_MAC_BASE          (ETH_BASE)\r\n#define ETH_MMC_BASE          (ETH_BASE + 0x0100U)\r\n#define ETH_PTP_BASE          (ETH_BASE + 0x0700U)\r\n#define ETH_DMA_BASE          (ETH_BASE + 0x1000U)\r\n#define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000U)\r\n/*!< AHB2 peripherals */\r\n#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000U)\r\n#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800U)\r\n/*!< FMC Bankx registers base address */\r\n#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000U)\r\n#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104U)\r\n#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080U)\r\n#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140U)\r\n\r\n/* Debug MCU registers base address */\r\n#define DBGMCU_BASE           0xE0042000U\r\n\r\n/*!< USB registers base address */\r\n#define USB_OTG_HS_PERIPH_BASE               0x40040000U\r\n#define USB_OTG_FS_PERIPH_BASE               0x50000000U\r\n\r\n#define USB_OTG_GLOBAL_BASE                  0x000U\r\n#define USB_OTG_DEVICE_BASE                  0x800U\r\n#define USB_OTG_IN_ENDPOINT_BASE             0x900U\r\n#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U\r\n#define USB_OTG_EP_REG_SIZE                  0x20U\r\n#define USB_OTG_HOST_BASE                    0x400U\r\n#define USB_OTG_HOST_PORT_BASE               0x440U\r\n#define USB_OTG_HOST_CHANNEL_BASE            0x500U\r\n#define USB_OTG_HOST_CHANNEL_SIZE            0x20U\r\n#define USB_OTG_PCGCCTL_BASE                 0xE00U\r\n#define USB_OTG_FIFO_BASE                    0x1000U\r\n#define USB_OTG_FIFO_SIZE                    0x1000U\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @addtogroup Peripheral_declaration\r\n  * @{\r\n  */  \r\n#define TIM2                ((TIM_TypeDef *) TIM2_BASE)\r\n#define TIM3                ((TIM_TypeDef *) TIM3_BASE)\r\n#define TIM4                ((TIM_TypeDef *) TIM4_BASE)\r\n#define TIM5                ((TIM_TypeDef *) TIM5_BASE)\r\n#define TIM6                ((TIM_TypeDef *) TIM6_BASE)\r\n#define TIM7                ((TIM_TypeDef *) TIM7_BASE)\r\n#define TIM12               ((TIM_TypeDef *) TIM12_BASE)\r\n#define TIM13               ((TIM_TypeDef *) TIM13_BASE)\r\n#define TIM14               ((TIM_TypeDef *) TIM14_BASE)\r\n#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)\r\n#define RTC                 ((RTC_TypeDef *) RTC_BASE)\r\n#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)\r\n#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)\r\n#define SPI2                ((SPI_TypeDef *) SPI2_BASE)\r\n#define SPI3                ((SPI_TypeDef *) SPI3_BASE)\r\n#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE) \r\n#define USART2              ((USART_TypeDef *) USART2_BASE)\r\n#define USART3              ((USART_TypeDef *) USART3_BASE)\r\n#define UART4               ((USART_TypeDef *) UART4_BASE)\r\n#define UART5               ((USART_TypeDef *) UART5_BASE)\r\n#define I2C1                ((I2C_TypeDef *) I2C1_BASE)\r\n#define I2C2                ((I2C_TypeDef *) I2C2_BASE)\r\n#define I2C3                ((I2C_TypeDef *) I2C3_BASE)\r\n#define I2C4                ((I2C_TypeDef *) I2C4_BASE)\r\n#define CAN1                ((CAN_TypeDef *) CAN1_BASE)\r\n#define CAN2                ((CAN_TypeDef *) CAN2_BASE)\r\n#define CEC                 ((CEC_TypeDef *) CEC_BASE)\r\n#define PWR                 ((PWR_TypeDef *) PWR_BASE)\r\n#define DAC                 ((DAC_TypeDef *) DAC_BASE)\r\n#define UART7               ((USART_TypeDef *) UART7_BASE)\r\n#define UART8               ((USART_TypeDef *) UART8_BASE)\r\n#define TIM1                ((TIM_TypeDef *) TIM1_BASE)\r\n#define TIM8                ((TIM_TypeDef *) TIM8_BASE)\r\n#define USART1              ((USART_TypeDef *) USART1_BASE)\r\n#define USART6              ((USART_TypeDef *) USART6_BASE)\r\n#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)\r\n#define ADC1                ((ADC_TypeDef *) ADC1_BASE)\r\n#define ADC2                ((ADC_TypeDef *) ADC2_BASE)\r\n#define ADC3                ((ADC_TypeDef *) ADC3_BASE)\r\n#define SDMMC1              ((SDMMC_TypeDef *) SDMMC1_BASE)\r\n#define SPI1                ((SPI_TypeDef *) SPI1_BASE) \r\n#define SPI4                ((SPI_TypeDef *) SPI4_BASE)\r\n#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)\r\n#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)\r\n#define TIM9                ((TIM_TypeDef *) TIM9_BASE)\r\n#define TIM10               ((TIM_TypeDef *) TIM10_BASE)\r\n#define TIM11               ((TIM_TypeDef *) TIM11_BASE)\r\n#define SPI5                ((SPI_TypeDef *) SPI5_BASE)\r\n#define SPI6                ((SPI_TypeDef *) SPI6_BASE)\r\n#define SAI1                ((SAI_TypeDef *) SAI1_BASE)\r\n#define SAI2                ((SAI_TypeDef *) SAI2_BASE)\r\n#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)\r\n#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)\r\n#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)\r\n#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)\r\n#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)\r\n#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)\r\n#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)\r\n#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)\r\n#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)\r\n#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)\r\n#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)\r\n#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)\r\n#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)\r\n#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)\r\n#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)\r\n#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)\r\n#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)\r\n#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)\r\n#define CRC                 ((CRC_TypeDef *) CRC_BASE)\r\n#define RCC                 ((RCC_TypeDef *) RCC_BASE)\r\n#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)\r\n#define DMA1                ((DMA_TypeDef *) DMA1_BASE)\r\n#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)\r\n#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)\r\n#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)\r\n#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)\r\n#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)\r\n#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)\r\n#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)\r\n#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)\r\n#define DMA2                ((DMA_TypeDef *) DMA2_BASE)\r\n#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)\r\n#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)\r\n#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)\r\n#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)\r\n#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)\r\n#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)\r\n#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)\r\n#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)\r\n#define ETH                 ((ETH_TypeDef *) ETH_BASE)  \r\n#define DMA2D               ((DMA2D_TypeDef *)DMA2D_BASE)\r\n#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)\r\n#define RNG                 ((RNG_TypeDef *) RNG_BASE)\r\n#define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)\r\n#define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)\r\n#define FMC_Bank3           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)\r\n#define FMC_Bank5_6         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)\r\n#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)\r\n#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)\r\n#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)\r\n#define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup Exported_constants\r\n  * @{\r\n  */\r\n  \r\n  /** @addtogroup Peripheral_Registers_Bits_Definition\r\n  * @{\r\n  */\r\n    \r\n/******************************************************************************/\r\n/*                         Peripheral Registers_Bits_Definition               */\r\n/******************************************************************************/\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                        Analog to Digital Converter                         */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bit definition for ADC_SR register  ********************/\r\n#define  ADC_SR_AWD                          0x00000001U        /*!<Analog watchdog flag                                 */\r\n#define  ADC_SR_EOC                          0x00000002U        /*!<End of conversion                                    */\r\n#define  ADC_SR_JEOC                         0x00000004U        /*!<Injected channel end of conversion                   */\r\n#define  ADC_SR_JSTRT                        0x00000008U        /*!<Injected channel Start flag                          */\r\n#define  ADC_SR_STRT                         0x00000010U        /*!<Regular channel Start flag                           */\r\n#define  ADC_SR_OVR                          0x00000020U        /*!<Overrun flag                                         */\r\n\r\n/*******************  Bit definition for ADC_CR1 register  ********************/\r\n#define  ADC_CR1_AWDCH                       0x0000001FU        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */\r\n#define  ADC_CR1_AWDCH_0                     0x00000001U        /*!<Bit 0 */\r\n#define  ADC_CR1_AWDCH_1                     0x00000002U        /*!<Bit 1 */\r\n#define  ADC_CR1_AWDCH_2                     0x00000004U        /*!<Bit 2 */\r\n#define  ADC_CR1_AWDCH_3                     0x00000008U        /*!<Bit 3 */\r\n#define  ADC_CR1_AWDCH_4                     0x00000010U        /*!<Bit 4 */\r\n#define  ADC_CR1_EOCIE                       0x00000020U        /*!<Interrupt enable for EOC                             */\r\n#define  ADC_CR1_AWDIE                       0x00000040U        /*!<AAnalog Watchdog interrupt enable                    */\r\n#define  ADC_CR1_JEOCIE                      0x00000080U        /*!<Interrupt enable for injected channels               */\r\n#define  ADC_CR1_SCAN                        0x00000100U        /*!<Scan mode */\r\n#define  ADC_CR1_AWDSGL                      0x00000200U        /*!<Enable the watchdog on a single channel in scan mode */\r\n#define  ADC_CR1_JAUTO                       0x00000400U        /*!<Automatic injected group conversion                  */\r\n#define  ADC_CR1_DISCEN                      0x00000800U        /*!<Discontinuous mode on regular channels               */\r\n#define  ADC_CR1_JDISCEN                     0x00001000U        /*!<Discontinuous mode on injected channels              */\r\n#define  ADC_CR1_DISCNUM                     0x0000E000U        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */\r\n#define  ADC_CR1_DISCNUM_0                   0x00002000U        /*!<Bit 0 */\r\n#define  ADC_CR1_DISCNUM_1                   0x00004000U        /*!<Bit 1 */\r\n#define  ADC_CR1_DISCNUM_2                   0x00008000U        /*!<Bit 2 */\r\n#define  ADC_CR1_JAWDEN                      0x00400000U        /*!<Analog watchdog enable on injected channels          */\r\n#define  ADC_CR1_AWDEN                       0x00800000U        /*!<Analog watchdog enable on regular channels           */\r\n#define  ADC_CR1_RES                         0x03000000U        /*!<RES[2:0] bits (Resolution)                           */\r\n#define  ADC_CR1_RES_0                       0x01000000U        /*!<Bit 0 */\r\n#define  ADC_CR1_RES_1                       0x02000000U        /*!<Bit 1 */\r\n#define  ADC_CR1_OVRIE                       0x04000000U         /*!<overrun interrupt enable */\r\n  \r\n/*******************  Bit definition for ADC_CR2 register  ********************/\r\n#define  ADC_CR2_ADON                        0x00000001U        /*!<A/D Converter ON / OFF                                       */\r\n#define  ADC_CR2_CONT                        0x00000002U        /*!<Continuous Conversion                                        */\r\n#define  ADC_CR2_DMA                         0x00000100U        /*!<Direct Memory access mode                                    */\r\n#define  ADC_CR2_DDS                         0x00000200U        /*!<DMA disable selection (Single ADC)                           */\r\n#define  ADC_CR2_EOCS                        0x00000400U        /*!<End of conversion selection                                  */\r\n#define  ADC_CR2_ALIGN                       0x00000800U        /*!<Data Alignment                                               */\r\n#define  ADC_CR2_JEXTSEL                     0x000F0000U        /*!<JEXTSEL[3:0] bits (External event select for injected group) */\r\n#define  ADC_CR2_JEXTSEL_0                   0x00010000U        /*!<Bit 0 */\r\n#define  ADC_CR2_JEXTSEL_1                   0x00020000U        /*!<Bit 1 */\r\n#define  ADC_CR2_JEXTSEL_2                   0x00040000U        /*!<Bit 2 */\r\n#define  ADC_CR2_JEXTSEL_3                   0x00080000U        /*!<Bit 3 */\r\n#define  ADC_CR2_JEXTEN                      0x00300000U        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */\r\n#define  ADC_CR2_JEXTEN_0                    0x00100000U        /*!<Bit 0 */\r\n#define  ADC_CR2_JEXTEN_1                    0x00200000U        /*!<Bit 1 */\r\n#define  ADC_CR2_JSWSTART                    0x00400000U        /*!<Start Conversion of injected channels */\r\n#define  ADC_CR2_EXTSEL                      0x0F000000U        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */\r\n#define  ADC_CR2_EXTSEL_0                    0x01000000U        /*!<Bit 0 */\r\n#define  ADC_CR2_EXTSEL_1                    0x02000000U        /*!<Bit 1 */\r\n#define  ADC_CR2_EXTSEL_2                    0x04000000U        /*!<Bit 2 */\r\n#define  ADC_CR2_EXTSEL_3                    0x08000000U        /*!<Bit 3 */\r\n#define  ADC_CR2_EXTEN                       0x30000000U        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */\r\n#define  ADC_CR2_EXTEN_0                     0x10000000U        /*!<Bit 0 */\r\n#define  ADC_CR2_EXTEN_1                     0x20000000U        /*!<Bit 1 */\r\n#define  ADC_CR2_SWSTART                     0x40000000U        /*!<Start Conversion of regular channels */\r\n\r\n/******************  Bit definition for ADC_SMPR1 register  *******************/\r\n#define  ADC_SMPR1_SMP10                     0x00000007U        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */\r\n#define  ADC_SMPR1_SMP10_0                   0x00000001U        /*!<Bit 0 */\r\n#define  ADC_SMPR1_SMP10_1                   0x00000002U        /*!<Bit 1 */\r\n#define  ADC_SMPR1_SMP10_2                   0x00000004U        /*!<Bit 2 */\r\n#define  ADC_SMPR1_SMP11                     0x00000038U        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */\r\n#define  ADC_SMPR1_SMP11_0                   0x00000008U        /*!<Bit 0 */\r\n#define  ADC_SMPR1_SMP11_1                   0x00000010U        /*!<Bit 1 */\r\n#define  ADC_SMPR1_SMP11_2                   0x00000020U        /*!<Bit 2 */\r\n#define  ADC_SMPR1_SMP12                     0x000001C0U        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */\r\n#define  ADC_SMPR1_SMP12_0                   0x00000040U        /*!<Bit 0 */\r\n#define  ADC_SMPR1_SMP12_1                   0x00000080U        /*!<Bit 1 */\r\n#define  ADC_SMPR1_SMP12_2                   0x00000100U        /*!<Bit 2 */\r\n#define  ADC_SMPR1_SMP13                     0x00000E00U        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */\r\n#define  ADC_SMPR1_SMP13_0                   0x00000200U        /*!<Bit 0 */\r\n#define  ADC_SMPR1_SMP13_1                   0x00000400U        /*!<Bit 1 */\r\n#define  ADC_SMPR1_SMP13_2                   0x00000800U        /*!<Bit 2 */\r\n#define  ADC_SMPR1_SMP14                     0x00007000U        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */\r\n#define  ADC_SMPR1_SMP14_0                   0x00001000U        /*!<Bit 0 */\r\n#define  ADC_SMPR1_SMP14_1                   0x00002000U        /*!<Bit 1 */\r\n#define  ADC_SMPR1_SMP14_2                   0x00004000U        /*!<Bit 2 */\r\n#define  ADC_SMPR1_SMP15                     0x00038000U        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */\r\n#define  ADC_SMPR1_SMP15_0                   0x00008000U        /*!<Bit 0 */\r\n#define  ADC_SMPR1_SMP15_1                   0x00010000U        /*!<Bit 1 */\r\n#define  ADC_SMPR1_SMP15_2                   0x00020000U        /*!<Bit 2 */\r\n#define  ADC_SMPR1_SMP16                     0x001C0000U        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */\r\n#define  ADC_SMPR1_SMP16_0                   0x00040000U        /*!<Bit 0 */\r\n#define  ADC_SMPR1_SMP16_1                   0x00080000U        /*!<Bit 1 */\r\n#define  ADC_SMPR1_SMP16_2                   0x00100000U        /*!<Bit 2 */\r\n#define  ADC_SMPR1_SMP17                     0x00E00000U        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */\r\n#define  ADC_SMPR1_SMP17_0                   0x00200000U        /*!<Bit 0 */\r\n#define  ADC_SMPR1_SMP17_1                   0x00400000U        /*!<Bit 1 */\r\n#define  ADC_SMPR1_SMP17_2                   0x00800000U        /*!<Bit 2 */\r\n#define  ADC_SMPR1_SMP18                     0x07000000U        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */\r\n#define  ADC_SMPR1_SMP18_0                   0x01000000U        /*!<Bit 0 */\r\n#define  ADC_SMPR1_SMP18_1                   0x02000000U        /*!<Bit 1 */\r\n#define  ADC_SMPR1_SMP18_2                   0x04000000U        /*!<Bit 2 */\r\n\r\n/******************  Bit definition for ADC_SMPR2 register  *******************/\r\n#define  ADC_SMPR2_SMP0                      0x00000007U        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */\r\n#define  ADC_SMPR2_SMP0_0                    0x00000001U        /*!<Bit 0 */\r\n#define  ADC_SMPR2_SMP0_1                    0x00000002U        /*!<Bit 1 */\r\n#define  ADC_SMPR2_SMP0_2                    0x00000004U        /*!<Bit 2 */\r\n#define  ADC_SMPR2_SMP1                      0x00000038U        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */\r\n#define  ADC_SMPR2_SMP1_0                    0x00000008U        /*!<Bit 0 */\r\n#define  ADC_SMPR2_SMP1_1                    0x00000010U        /*!<Bit 1 */\r\n#define  ADC_SMPR2_SMP1_2                    0x00000020U        /*!<Bit 2 */\r\n#define  ADC_SMPR2_SMP2                      0x000001C0U        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */\r\n#define  ADC_SMPR2_SMP2_0                    0x00000040U        /*!<Bit 0 */\r\n#define  ADC_SMPR2_SMP2_1                    0x00000080U        /*!<Bit 1 */\r\n#define  ADC_SMPR2_SMP2_2                    0x00000100U        /*!<Bit 2 */\r\n#define  ADC_SMPR2_SMP3                      0x00000E00U        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */\r\n#define  ADC_SMPR2_SMP3_0                    0x00000200U        /*!<Bit 0 */\r\n#define  ADC_SMPR2_SMP3_1                    0x00000400U        /*!<Bit 1 */\r\n#define  ADC_SMPR2_SMP3_2                    0x00000800U        /*!<Bit 2 */\r\n#define  ADC_SMPR2_SMP4                      0x00007000U        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */\r\n#define  ADC_SMPR2_SMP4_0                    0x00001000U        /*!<Bit 0 */\r\n#define  ADC_SMPR2_SMP4_1                    0x00002000U        /*!<Bit 1 */\r\n#define  ADC_SMPR2_SMP4_2                    0x00004000U        /*!<Bit 2 */\r\n#define  ADC_SMPR2_SMP5                      0x00038000U        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */\r\n#define  ADC_SMPR2_SMP5_0                    0x00008000U        /*!<Bit 0 */\r\n#define  ADC_SMPR2_SMP5_1                    0x00010000U        /*!<Bit 1 */\r\n#define  ADC_SMPR2_SMP5_2                    0x00020000U        /*!<Bit 2 */\r\n#define  ADC_SMPR2_SMP6                      0x001C0000U        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */\r\n#define  ADC_SMPR2_SMP6_0                    0x00040000U        /*!<Bit 0 */\r\n#define  ADC_SMPR2_SMP6_1                    0x00080000U        /*!<Bit 1 */\r\n#define  ADC_SMPR2_SMP6_2                    0x00100000U        /*!<Bit 2 */\r\n#define  ADC_SMPR2_SMP7                      0x00E00000U        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */\r\n#define  ADC_SMPR2_SMP7_0                    0x00200000U        /*!<Bit 0 */\r\n#define  ADC_SMPR2_SMP7_1                    0x00400000U        /*!<Bit 1 */\r\n#define  ADC_SMPR2_SMP7_2                    0x00800000U        /*!<Bit 2 */\r\n#define  ADC_SMPR2_SMP8                      0x07000000U        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */\r\n#define  ADC_SMPR2_SMP8_0                    0x01000000U        /*!<Bit 0 */\r\n#define  ADC_SMPR2_SMP8_1                    0x02000000U        /*!<Bit 1 */\r\n#define  ADC_SMPR2_SMP8_2                    0x04000000U        /*!<Bit 2 */\r\n#define  ADC_SMPR2_SMP9                      0x38000000U        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */\r\n#define  ADC_SMPR2_SMP9_0                    0x08000000U        /*!<Bit 0 */\r\n#define  ADC_SMPR2_SMP9_1                    0x10000000U        /*!<Bit 1 */\r\n#define  ADC_SMPR2_SMP9_2                    0x20000000U        /*!<Bit 2 */\r\n\r\n/******************  Bit definition for ADC_JOFR1 register  *******************/\r\n#define  ADC_JOFR1_JOFFSET1                  0x0FFFU            /*!<Data offset for injected channel 1 */\r\n\r\n/******************  Bit definition for ADC_JOFR2 register  *******************/\r\n#define  ADC_JOFR2_JOFFSET2                  0x0FFFU            /*!<Data offset for injected channel 2 */\r\n\r\n/******************  Bit definition for ADC_JOFR3 register  *******************/\r\n#define  ADC_JOFR3_JOFFSET3                  0x0FFFU            /*!<Data offset for injected channel 3 */\r\n\r\n/******************  Bit definition for ADC_JOFR4 register  *******************/\r\n#define  ADC_JOFR4_JOFFSET4                  0x0FFFU            /*!<Data offset for injected channel 4 */\r\n\r\n/*******************  Bit definition for ADC_HTR register  ********************/\r\n#define  ADC_HTR_HT                          0x0FFFU            /*!<Analog watchdog high threshold */\r\n\r\n/*******************  Bit definition for ADC_LTR register  ********************/\r\n#define  ADC_LTR_LT                          0x0FFFU            /*!<Analog watchdog low threshold */\r\n\r\n/*******************  Bit definition for ADC_SQR1 register  *******************/\r\n#define  ADC_SQR1_SQ13                       0x0000001FU        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */\r\n#define  ADC_SQR1_SQ13_0                     0x00000001U        /*!<Bit 0 */\r\n#define  ADC_SQR1_SQ13_1                     0x00000002U        /*!<Bit 1 */\r\n#define  ADC_SQR1_SQ13_2                     0x00000004U        /*!<Bit 2 */\r\n#define  ADC_SQR1_SQ13_3                     0x00000008U        /*!<Bit 3 */\r\n#define  ADC_SQR1_SQ13_4                     0x00000010U        /*!<Bit 4 */\r\n#define  ADC_SQR1_SQ14                       0x000003E0U        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */\r\n#define  ADC_SQR1_SQ14_0                     0x00000020U        /*!<Bit 0 */\r\n#define  ADC_SQR1_SQ14_1                     0x00000040U        /*!<Bit 1 */\r\n#define  ADC_SQR1_SQ14_2                     0x00000080U        /*!<Bit 2 */\r\n#define  ADC_SQR1_SQ14_3                     0x00000100U        /*!<Bit 3 */\r\n#define  ADC_SQR1_SQ14_4                     0x00000200U        /*!<Bit 4 */\r\n#define  ADC_SQR1_SQ15                       0x00007C00U        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */\r\n#define  ADC_SQR1_SQ15_0                     0x00000400U        /*!<Bit 0 */\r\n#define  ADC_SQR1_SQ15_1                     0x00000800U        /*!<Bit 1 */\r\n#define  ADC_SQR1_SQ15_2                     0x00001000U        /*!<Bit 2 */\r\n#define  ADC_SQR1_SQ15_3                     0x00002000U        /*!<Bit 3 */\r\n#define  ADC_SQR1_SQ15_4                     0x00004000U        /*!<Bit 4 */\r\n#define  ADC_SQR1_SQ16                       0x000F8000U        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */\r\n#define  ADC_SQR1_SQ16_0                     0x00008000U        /*!<Bit 0 */\r\n#define  ADC_SQR1_SQ16_1                     0x00010000U        /*!<Bit 1 */\r\n#define  ADC_SQR1_SQ16_2                     0x00020000U        /*!<Bit 2 */\r\n#define  ADC_SQR1_SQ16_3                     0x00040000U        /*!<Bit 3 */\r\n#define  ADC_SQR1_SQ16_4                     0x00080000U        /*!<Bit 4 */\r\n#define  ADC_SQR1_L                          0x00F00000U        /*!<L[3:0] bits (Regular channel sequence length) */\r\n#define  ADC_SQR1_L_0                        0x00100000U        /*!<Bit 0 */\r\n#define  ADC_SQR1_L_1                        0x00200000U        /*!<Bit 1 */\r\n#define  ADC_SQR1_L_2                        0x00400000U        /*!<Bit 2 */\r\n#define  ADC_SQR1_L_3                        0x00800000U        /*!<Bit 3 */\r\n\r\n/*******************  Bit definition for ADC_SQR2 register  *******************/\r\n#define  ADC_SQR2_SQ7                        0x0000001FU        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */\r\n#define  ADC_SQR2_SQ7_0                      0x00000001U        /*!<Bit 0 */\r\n#define  ADC_SQR2_SQ7_1                      0x00000002U        /*!<Bit 1 */\r\n#define  ADC_SQR2_SQ7_2                      0x00000004U        /*!<Bit 2 */\r\n#define  ADC_SQR2_SQ7_3                      0x00000008U        /*!<Bit 3 */\r\n#define  ADC_SQR2_SQ7_4                      0x00000010U        /*!<Bit 4 */\r\n#define  ADC_SQR2_SQ8                        0x000003E0U        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */\r\n#define  ADC_SQR2_SQ8_0                      0x00000020U        /*!<Bit 0 */\r\n#define  ADC_SQR2_SQ8_1                      0x00000040U        /*!<Bit 1 */\r\n#define  ADC_SQR2_SQ8_2                      0x00000080U        /*!<Bit 2 */\r\n#define  ADC_SQR2_SQ8_3                      0x00000100U        /*!<Bit 3 */\r\n#define  ADC_SQR2_SQ8_4                      0x00000200U        /*!<Bit 4 */\r\n#define  ADC_SQR2_SQ9                        0x00007C00U        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */\r\n#define  ADC_SQR2_SQ9_0                      0x00000400U        /*!<Bit 0 */\r\n#define  ADC_SQR2_SQ9_1                      0x00000800U        /*!<Bit 1 */\r\n#define  ADC_SQR2_SQ9_2                      0x00001000U        /*!<Bit 2 */\r\n#define  ADC_SQR2_SQ9_3                      0x00002000U        /*!<Bit 3 */\r\n#define  ADC_SQR2_SQ9_4                      0x00004000U        /*!<Bit 4 */\r\n#define  ADC_SQR2_SQ10                       0x000F8000U        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */\r\n#define  ADC_SQR2_SQ10_0                     0x00008000U        /*!<Bit 0 */\r\n#define  ADC_SQR2_SQ10_1                     0x00010000U        /*!<Bit 1 */\r\n#define  ADC_SQR2_SQ10_2                     0x00020000U        /*!<Bit 2 */\r\n#define  ADC_SQR2_SQ10_3                     0x00040000U        /*!<Bit 3 */\r\n#define  ADC_SQR2_SQ10_4                     0x00080000U        /*!<Bit 4 */\r\n#define  ADC_SQR2_SQ11                       0x01F00000U        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */\r\n#define  ADC_SQR2_SQ11_0                     0x00100000U        /*!<Bit 0 */\r\n#define  ADC_SQR2_SQ11_1                     0x00200000U        /*!<Bit 1 */\r\n#define  ADC_SQR2_SQ11_2                     0x00400000U        /*!<Bit 2 */\r\n#define  ADC_SQR2_SQ11_3                     0x00800000U        /*!<Bit 3 */\r\n#define  ADC_SQR2_SQ11_4                     0x01000000U        /*!<Bit 4 */\r\n#define  ADC_SQR2_SQ12                       0x3E000000U        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */\r\n#define  ADC_SQR2_SQ12_0                     0x02000000U        /*!<Bit 0 */\r\n#define  ADC_SQR2_SQ12_1                     0x04000000U        /*!<Bit 1 */\r\n#define  ADC_SQR2_SQ12_2                     0x08000000U        /*!<Bit 2 */\r\n#define  ADC_SQR2_SQ12_3                     0x10000000U        /*!<Bit 3 */\r\n#define  ADC_SQR2_SQ12_4                     0x20000000U        /*!<Bit 4 */\r\n\r\n/*******************  Bit definition for ADC_SQR3 register  *******************/\r\n#define  ADC_SQR3_SQ1                        0x0000001FU        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */\r\n#define  ADC_SQR3_SQ1_0                      0x00000001U        /*!<Bit 0 */\r\n#define  ADC_SQR3_SQ1_1                      0x00000002U        /*!<Bit 1 */\r\n#define  ADC_SQR3_SQ1_2                      0x00000004U        /*!<Bit 2 */\r\n#define  ADC_SQR3_SQ1_3                      0x00000008U        /*!<Bit 3 */\r\n#define  ADC_SQR3_SQ1_4                      0x00000010U        /*!<Bit 4 */\r\n#define  ADC_SQR3_SQ2                        0x000003E0U        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */\r\n#define  ADC_SQR3_SQ2_0                      0x00000020U        /*!<Bit 0 */\r\n#define  ADC_SQR3_SQ2_1                      0x00000040U        /*!<Bit 1 */\r\n#define  ADC_SQR3_SQ2_2                      0x00000080U        /*!<Bit 2 */\r\n#define  ADC_SQR3_SQ2_3                      0x00000100U        /*!<Bit 3 */\r\n#define  ADC_SQR3_SQ2_4                      0x00000200U        /*!<Bit 4 */\r\n#define  ADC_SQR3_SQ3                        0x00007C00U        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */\r\n#define  ADC_SQR3_SQ3_0                      0x00000400U        /*!<Bit 0 */\r\n#define  ADC_SQR3_SQ3_1                      0x00000800U        /*!<Bit 1 */\r\n#define  ADC_SQR3_SQ3_2                      0x00001000U        /*!<Bit 2 */\r\n#define  ADC_SQR3_SQ3_3                      0x00002000U        /*!<Bit 3 */\r\n#define  ADC_SQR3_SQ3_4                      0x00004000U        /*!<Bit 4 */\r\n#define  ADC_SQR3_SQ4                        0x000F8000U        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */\r\n#define  ADC_SQR3_SQ4_0                      0x00008000U        /*!<Bit 0 */\r\n#define  ADC_SQR3_SQ4_1                      0x00010000U        /*!<Bit 1 */\r\n#define  ADC_SQR3_SQ4_2                      0x00020000U        /*!<Bit 2 */\r\n#define  ADC_SQR3_SQ4_3                      0x00040000U        /*!<Bit 3 */\r\n#define  ADC_SQR3_SQ4_4                      0x00080000U        /*!<Bit 4 */\r\n#define  ADC_SQR3_SQ5                        0x01F00000U        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */\r\n#define  ADC_SQR3_SQ5_0                      0x00100000U        /*!<Bit 0 */\r\n#define  ADC_SQR3_SQ5_1                      0x00200000U        /*!<Bit 1 */\r\n#define  ADC_SQR3_SQ5_2                      0x00400000U        /*!<Bit 2 */\r\n#define  ADC_SQR3_SQ5_3                      0x00800000U        /*!<Bit 3 */\r\n#define  ADC_SQR3_SQ5_4                      0x01000000U        /*!<Bit 4 */\r\n#define  ADC_SQR3_SQ6                        0x3E000000U        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */\r\n#define  ADC_SQR3_SQ6_0                      0x02000000U        /*!<Bit 0 */\r\n#define  ADC_SQR3_SQ6_1                      0x04000000U        /*!<Bit 1 */\r\n#define  ADC_SQR3_SQ6_2                      0x08000000U        /*!<Bit 2 */\r\n#define  ADC_SQR3_SQ6_3                      0x10000000U        /*!<Bit 3 */\r\n#define  ADC_SQR3_SQ6_4                      0x20000000U        /*!<Bit 4 */\r\n\r\n/*******************  Bit definition for ADC_JSQR register  *******************/\r\n#define  ADC_JSQR_JSQ1                       0x0000001FU        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  \r\n#define  ADC_JSQR_JSQ1_0                     0x00000001U        /*!<Bit 0 */\r\n#define  ADC_JSQR_JSQ1_1                     0x00000002U        /*!<Bit 1 */\r\n#define  ADC_JSQR_JSQ1_2                     0x00000004U        /*!<Bit 2 */\r\n#define  ADC_JSQR_JSQ1_3                     0x00000008U        /*!<Bit 3 */\r\n#define  ADC_JSQR_JSQ1_4                     0x00000010U        /*!<Bit 4 */\r\n#define  ADC_JSQR_JSQ2                       0x000003E0U        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */\r\n#define  ADC_JSQR_JSQ2_0                     0x00000020U        /*!<Bit 0 */\r\n#define  ADC_JSQR_JSQ2_1                     0x00000040U        /*!<Bit 1 */\r\n#define  ADC_JSQR_JSQ2_2                     0x00000080U        /*!<Bit 2 */\r\n#define  ADC_JSQR_JSQ2_3                     0x00000100U        /*!<Bit 3 */\r\n#define  ADC_JSQR_JSQ2_4                     0x00000200U        /*!<Bit 4 */\r\n#define  ADC_JSQR_JSQ3                       0x00007C00U        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */\r\n#define  ADC_JSQR_JSQ3_0                     0x00000400U        /*!<Bit 0 */\r\n#define  ADC_JSQR_JSQ3_1                     0x00000800U        /*!<Bit 1 */\r\n#define  ADC_JSQR_JSQ3_2                     0x00001000U        /*!<Bit 2 */\r\n#define  ADC_JSQR_JSQ3_3                     0x00002000U        /*!<Bit 3 */\r\n#define  ADC_JSQR_JSQ3_4                     0x00004000U        /*!<Bit 4 */\r\n#define  ADC_JSQR_JSQ4                       0x000F8000U        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */\r\n#define  ADC_JSQR_JSQ4_0                     0x00008000U        /*!<Bit 0 */\r\n#define  ADC_JSQR_JSQ4_1                     0x00010000U        /*!<Bit 1 */\r\n#define  ADC_JSQR_JSQ4_2                     0x00020000U        /*!<Bit 2 */\r\n#define  ADC_JSQR_JSQ4_3                     0x00040000U        /*!<Bit 3 */\r\n#define  ADC_JSQR_JSQ4_4                     0x00080000U        /*!<Bit 4 */\r\n#define  ADC_JSQR_JL                         0x00300000U        /*!<JL[1:0] bits (Injected Sequence length) */\r\n#define  ADC_JSQR_JL_0                       0x00100000U        /*!<Bit 0 */\r\n#define  ADC_JSQR_JL_1                       0x00200000U        /*!<Bit 1 */\r\n\r\n/*******************  Bit definition for ADC_JDR1 register  *******************/\r\n#define  ADC_JDR1_JDATA                      ((uint16_t)0xFFFFU)            /*!<Injected data */\r\n\r\n/*******************  Bit definition for ADC_JDR2 register  *******************/\r\n#define  ADC_JDR2_JDATA                      ((uint16_t)0xFFFFU)            /*!<Injected data */\r\n\r\n/*******************  Bit definition for ADC_JDR3 register  *******************/\r\n#define  ADC_JDR3_JDATA                      ((uint16_t)0xFFFFU)            /*!<Injected data */\r\n\r\n/*******************  Bit definition for ADC_JDR4 register  *******************/\r\n#define  ADC_JDR4_JDATA                      ((uint16_t)0xFFFFU)            /*!<Injected data */\r\n\r\n/********************  Bit definition for ADC_DR register  ********************/\r\n#define  ADC_DR_DATA                         0x0000FFFFU        /*!<Regular data */\r\n#define  ADC_DR_ADC2DATA                     0xFFFF0000U        /*!<ADC2 data */\r\n\r\n/*******************  Bit definition for ADC_CSR register  ********************/\r\n#define  ADC_CSR_AWD1                        0x00000001U        /*!<ADC1 Analog watchdog flag               */\r\n#define  ADC_CSR_EOC1                        0x00000002U        /*!<ADC1 End of conversion                  */\r\n#define  ADC_CSR_JEOC1                       0x00000004U        /*!<ADC1 Injected channel end of conversion */\r\n#define  ADC_CSR_JSTRT1                      0x00000008U        /*!<ADC1 Injected channel Start flag        */\r\n#define  ADC_CSR_STRT1                       0x00000010U        /*!<ADC1 Regular channel Start flag         */\r\n#define  ADC_CSR_OVR1                        0x00000020U        /*!<ADC1 Overrun flag                       */\r\n#define  ADC_CSR_AWD2                        0x00000100U        /*!<ADC2 Analog watchdog flag               */\r\n#define  ADC_CSR_EOC2                        0x00000200U        /*!<ADC2 End of conversion                  */\r\n#define  ADC_CSR_JEOC2                       0x00000400U        /*!<ADC2 Injected channel end of conversion */\r\n#define  ADC_CSR_JSTRT2                      0x00000800U        /*!<ADC2 Injected channel Start flag        */\r\n#define  ADC_CSR_STRT2                       0x00001000U        /*!<ADC2 Regular channel Start flag         */\r\n#define  ADC_CSR_OVR2                        0x00002000U        /*!<ADC2 Overrun flag                       */\r\n#define  ADC_CSR_AWD3                        0x00010000U        /*!<ADC3 Analog watchdog flag               */\r\n#define  ADC_CSR_EOC3                        0x00020000U        /*!<ADC3 End of conversion                  */\r\n#define  ADC_CSR_JEOC3                       0x00040000U        /*!<ADC3 Injected channel end of conversion */\r\n#define  ADC_CSR_JSTRT3                      0x00080000U        /*!<ADC3 Injected channel Start flag        */\r\n#define  ADC_CSR_STRT3                       0x00100000U        /*!<ADC3 Regular channel Start flag         */\r\n#define  ADC_CSR_OVR3                        0x00200000U        /*!<ADC3 Overrun flag                       */\r\n\r\n/* Legacy defines */\r\n#define  ADC_CSR_DOVR1                       ADC_CSR_OVR1\r\n#define  ADC_CSR_DOVR2                       ADC_CSR_OVR2\r\n#define  ADC_CSR_DOVR3                       ADC_CSR_OVR3\r\n\r\n\r\n/*******************  Bit definition for ADC_CCR register  ********************/\r\n#define  ADC_CCR_MULTI                       0x0000001FU        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  \r\n#define  ADC_CCR_MULTI_0                     0x00000001U        /*!<Bit 0 */\r\n#define  ADC_CCR_MULTI_1                     0x00000002U        /*!<Bit 1 */\r\n#define  ADC_CCR_MULTI_2                     0x00000004U        /*!<Bit 2 */\r\n#define  ADC_CCR_MULTI_3                     0x00000008U        /*!<Bit 3 */\r\n#define  ADC_CCR_MULTI_4                     0x00000010U        /*!<Bit 4 */\r\n#define  ADC_CCR_DELAY                       0x00000F00U        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  \r\n#define  ADC_CCR_DELAY_0                     0x00000100U        /*!<Bit 0 */\r\n#define  ADC_CCR_DELAY_1                     0x00000200U        /*!<Bit 1 */\r\n#define  ADC_CCR_DELAY_2                     0x00000400U        /*!<Bit 2 */\r\n#define  ADC_CCR_DELAY_3                     0x00000800U        /*!<Bit 3 */\r\n#define  ADC_CCR_DDS                         0x00002000U        /*!<DMA disable selection (Multi-ADC mode) */\r\n#define  ADC_CCR_DMA                         0x0000C000U        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  \r\n#define  ADC_CCR_DMA_0                       0x00004000U        /*!<Bit 0 */\r\n#define  ADC_CCR_DMA_1                       0x00008000U        /*!<Bit 1 */\r\n#define  ADC_CCR_ADCPRE                      0x00030000U        /*!<ADCPRE[1:0] bits (ADC prescaler) */  \r\n#define  ADC_CCR_ADCPRE_0                    0x00010000U        /*!<Bit 0 */\r\n#define  ADC_CCR_ADCPRE_1                    0x00020000U        /*!<Bit 1 */\r\n#define  ADC_CCR_VBATE                       0x00400000U        /*!<VBAT Enable */\r\n#define  ADC_CCR_TSVREFE                     0x00800000U        /*!<Temperature Sensor and VREFINT Enable */\r\n\r\n/*******************  Bit definition for ADC_CDR register  ********************/\r\n#define  ADC_CDR_DATA1                       0x0000FFFFU         /*!<1st data of a pair of regular conversions */\r\n#define  ADC_CDR_DATA2                       0xFFFF0000U         /*!<2nd data of a pair of regular conversions */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                         Controller Area Network                            */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*!<CAN control and status registers */\r\n/*******************  Bit definition for CAN_MCR register  ********************/\r\n#define  CAN_MCR_INRQ                        0x00000001U        /*!<Initialization Request            */\r\n#define  CAN_MCR_SLEEP                       0x00000002U        /*!<Sleep Mode Request                */\r\n#define  CAN_MCR_TXFP                        0x00000004U        /*!<Transmit FIFO Priority            */\r\n#define  CAN_MCR_RFLM                        0x00000008U        /*!<Receive FIFO Locked Mode          */\r\n#define  CAN_MCR_NART                        0x00000010U        /*!<No Automatic Retransmission       */\r\n#define  CAN_MCR_AWUM                        0x00000020U        /*!<Automatic Wakeup Mode             */\r\n#define  CAN_MCR_ABOM                        0x00000040U        /*!<Automatic Bus-Off Management      */\r\n#define  CAN_MCR_TTCM                        0x00000080U        /*!<Time Triggered Communication Mode */\r\n#define  CAN_MCR_RESET                       0x00008000U        /*!<bxCAN software master reset       */\r\n                                                                           \r\n/*******************  Bit definition for CAN_MSR register  ********************/\r\n#define  CAN_MSR_INAK                        0x00000001U        /*!<Initialization Acknowledge  */\r\n#define  CAN_MSR_SLAK                        0x00000002U        /*!<Sleep Acknowledge           */\r\n#define  CAN_MSR_ERRI                        0x00000004U        /*!<Error Interrupt             */\r\n#define  CAN_MSR_WKUI                        0x00000008U        /*!<Wakeup Interrupt            */\r\n#define  CAN_MSR_SLAKI                       0x00000010U        /*!<Sleep Acknowledge Interrupt */\r\n#define  CAN_MSR_TXM                         0x00000100U        /*!<Transmit Mode               */\r\n#define  CAN_MSR_RXM                         0x00000200U        /*!<Receive Mode                */\r\n#define  CAN_MSR_SAMP                        0x00000400U        /*!<Last Sample Point           */\r\n#define  CAN_MSR_RX                          0x00000800U        /*!<CAN Rx Signal               */\r\n\r\n/*******************  Bit definition for CAN_TSR register  ********************/\r\n#define  CAN_TSR_RQCP0                       0x00000001U        /*!<Request Completed Mailbox0      */\r\n#define  CAN_TSR_TXOK0                       0x00000002U        /*!<Transmission OK of Mailbox0     */\r\n#define  CAN_TSR_ALST0                       0x00000004U        /*!<Arbitration Lost for Mailbox0   */\r\n#define  CAN_TSR_TERR0                       0x00000008U        /*!<Transmission Error of Mailbox0  */\r\n#define  CAN_TSR_ABRQ0                       0x00000080U        /*!<Abort Request for Mailbox0      */\r\n#define  CAN_TSR_RQCP1                       0x00000100U        /*!<Request Completed Mailbox1      */\r\n#define  CAN_TSR_TXOK1                       0x00000200U        /*!<Transmission OK of Mailbox1     */\r\n#define  CAN_TSR_ALST1                       0x00000400U        /*!<Arbitration Lost for Mailbox1   */\r\n#define  CAN_TSR_TERR1                       0x00000800U        /*!<Transmission Error of Mailbox1  */\r\n#define  CAN_TSR_ABRQ1                       0x00008000U        /*!<Abort Request for Mailbox 1     */\r\n#define  CAN_TSR_RQCP2                       0x00010000U        /*!<Request Completed Mailbox2      */\r\n#define  CAN_TSR_TXOK2                       0x00020000U        /*!<Transmission OK of Mailbox 2    */\r\n#define  CAN_TSR_ALST2                       0x00040000U        /*!<Arbitration Lost for mailbox 2  */\r\n#define  CAN_TSR_TERR2                       0x00080000U        /*!<Transmission Error of Mailbox 2 */\r\n#define  CAN_TSR_ABRQ2                       0x00800000U        /*!<Abort Request for Mailbox 2     */\r\n#define  CAN_TSR_CODE                        0x03000000U        /*!<Mailbox Code                    */\r\n\r\n#define  CAN_TSR_TME                         0x1C000000U        /*!<TME[2:0] bits */\r\n#define  CAN_TSR_TME0                        0x04000000U        /*!<Transmit Mailbox 0 Empty */\r\n#define  CAN_TSR_TME1                        0x08000000U        /*!<Transmit Mailbox 1 Empty */\r\n#define  CAN_TSR_TME2                        0x10000000U        /*!<Transmit Mailbox 2 Empty */\r\n\r\n#define  CAN_TSR_LOW                         0xE0000000U        /*!<LOW[2:0] bits */\r\n#define  CAN_TSR_LOW0                        0x20000000U        /*!<Lowest Priority Flag for Mailbox 0 */\r\n#define  CAN_TSR_LOW1                        0x40000000U        /*!<Lowest Priority Flag for Mailbox 1 */\r\n#define  CAN_TSR_LOW2                        0x80000000U        /*!<Lowest Priority Flag for Mailbox 2 */\r\n\r\n/*******************  Bit definition for CAN_RF0R register  *******************/\r\n#define  CAN_RF0R_FMP0                       0x00000003U        /*!<FIFO 0 Message Pending        */\r\n#define  CAN_RF0R_FULL0                      0x00000008U        /*!<FIFO 0 Full                   */\r\n#define  CAN_RF0R_FOVR0                      0x00000010U        /*!<FIFO 0 Overrun                */\r\n#define  CAN_RF0R_RFOM0                      0x00000020U        /*!<Release FIFO 0 Output Mailbox */\r\n\r\n/*******************  Bit definition for CAN_RF1R register  *******************/\r\n#define  CAN_RF1R_FMP1                       0x00000003U        /*!<FIFO 1 Message Pending        */\r\n#define  CAN_RF1R_FULL1                      0x00000008U        /*!<FIFO 1 Full                   */\r\n#define  CAN_RF1R_FOVR1                      0x00000010U        /*!<FIFO 1 Overrun                */\r\n#define  CAN_RF1R_RFOM1                      0x00000020U        /*!<Release FIFO 1 Output Mailbox */\r\n\r\n/********************  Bit definition for CAN_IER register  *******************/\r\n#define  CAN_IER_TMEIE                       0x00000001U        /*!<Transmit Mailbox Empty Interrupt Enable */\r\n#define  CAN_IER_FMPIE0                      0x00000002U        /*!<FIFO Message Pending Interrupt Enable   */\r\n#define  CAN_IER_FFIE0                       0x00000004U        /*!<FIFO Full Interrupt Enable              */\r\n#define  CAN_IER_FOVIE0                      0x00000008U        /*!<FIFO Overrun Interrupt Enable           */\r\n#define  CAN_IER_FMPIE1                      0x00000010U        /*!<FIFO Message Pending Interrupt Enable   */\r\n#define  CAN_IER_FFIE1                       0x00000020U        /*!<FIFO Full Interrupt Enable              */\r\n#define  CAN_IER_FOVIE1                      0x00000040U        /*!<FIFO Overrun Interrupt Enable           */\r\n#define  CAN_IER_EWGIE                       0x00000100U        /*!<Error Warning Interrupt Enable          */\r\n#define  CAN_IER_EPVIE                       0x00000200U        /*!<Error Passive Interrupt Enable          */\r\n#define  CAN_IER_BOFIE                       0x00000400U        /*!<Bus-Off Interrupt Enable                */\r\n#define  CAN_IER_LECIE                       0x00000800U        /*!<Last Error Code Interrupt Enable        */\r\n#define  CAN_IER_ERRIE                       0x00008000U        /*!<Error Interrupt Enable                  */\r\n#define  CAN_IER_WKUIE                       0x00010000U        /*!<Wakeup Interrupt Enable                 */\r\n#define  CAN_IER_SLKIE                       0x00020000U        /*!<Sleep Interrupt Enable                  */\r\n\r\n/********************  Bit definition for CAN_ESR register  *******************/\r\n#define  CAN_ESR_EWGF                        0x00000001U        /*!<Error Warning Flag */\r\n#define  CAN_ESR_EPVF                        0x00000002U        /*!<Error Passive Flag */\r\n#define  CAN_ESR_BOFF                        0x00000004U        /*!<Bus-Off Flag */\r\n\r\n#define  CAN_ESR_LEC                         0x00000070U        /*!<LEC[2:0] bits (Last Error Code) */\r\n#define  CAN_ESR_LEC_0                       0x00000010U        /*!<Bit 0 */\r\n#define  CAN_ESR_LEC_1                       0x00000020U        /*!<Bit 1 */\r\n#define  CAN_ESR_LEC_2                       0x00000040U        /*!<Bit 2 */\r\n\r\n#define  CAN_ESR_TEC                         0x00FF0000U        /*!<Least significant byte of the 9-bit Transmit Error Counter */\r\n#define  CAN_ESR_REC                         0xFF000000U        /*!<Receive Error Counter */\r\n\r\n/*******************  Bit definition for CAN_BTR register  ********************/\r\n#define  CAN_BTR_BRP                         0x000003FFU        /*!<Baud Rate Prescaler           */\r\n#define  CAN_BTR_TS1                         0x000F0000U        /*!<Time Segment 1                */\r\n#define  CAN_BTR_TS1_0                       0x00010000U        /*!<Bit 0 */\r\n#define  CAN_BTR_TS1_1                       0x00020000U        /*!<Bit 1 */\r\n#define  CAN_BTR_TS1_2                       0x00040000U        /*!<Bit 2 */\r\n#define  CAN_BTR_TS1_3                       0x00080000U        /*!<Bit 3 */\r\n#define  CAN_BTR_TS2                         0x00700000U        /*!<Time Segment 2                */\r\n#define  CAN_BTR_TS2_0                       0x00100000U        /*!<Bit 0 */\r\n#define  CAN_BTR_TS2_1                       0x00200000U        /*!<Bit 1 */\r\n#define  CAN_BTR_TS2_2                       0x00400000U        /*!<Bit 2 */\r\n#define  CAN_BTR_SJW                         0x03000000U        /*!<Resynchronization Jump Width  */\r\n#define  CAN_BTR_SJW_0                       0x01000000U        /*!<Bit 0 */\r\n#define  CAN_BTR_SJW_1                       0x02000000U        /*!<Bit 1 */\r\n#define  CAN_BTR_LBKM                        0x40000000U        /*!<Loop Back Mode (Debug)        */\r\n#define  CAN_BTR_SILM                        0x80000000U        /*!<Silent Mode                   */\r\n\r\n/*!<Mailbox registers */\r\n/******************  Bit definition for CAN_TI0R register  ********************/\r\n#define  CAN_TI0R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request                   */\r\n#define  CAN_TI0R_RTR                        0x00000002U        /*!<Remote Transmission Request                */\r\n#define  CAN_TI0R_IDE                        0x00000004U        /*!<Identifier Extension                       */\r\n#define  CAN_TI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier                        */\r\n#define  CAN_TI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */\r\n\r\n/******************  Bit definition for CAN_TDT0R register  *******************/\r\n#define  CAN_TDT0R_DLC                       0x0000000FU        /*!<Data Length Code     */\r\n#define  CAN_TDT0R_TGT                       0x00000100U        /*!<Transmit Global Time */\r\n#define  CAN_TDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp   */\r\n\r\n/******************  Bit definition for CAN_TDL0R register  *******************/\r\n#define  CAN_TDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */\r\n#define  CAN_TDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */\r\n#define  CAN_TDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */\r\n#define  CAN_TDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */\r\n\r\n/******************  Bit definition for CAN_TDH0R register  *******************/\r\n#define  CAN_TDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */\r\n#define  CAN_TDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */\r\n#define  CAN_TDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */\r\n#define  CAN_TDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */\r\n\r\n/*******************  Bit definition for CAN_TI1R register  *******************/\r\n#define  CAN_TI1R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request                   */\r\n#define  CAN_TI1R_RTR                        0x00000002U        /*!<Remote Transmission Request                */\r\n#define  CAN_TI1R_IDE                        0x00000004U        /*!<Identifier Extension                       */\r\n#define  CAN_TI1R_EXID                       0x001FFFF8U        /*!<Extended Identifier                        */\r\n#define  CAN_TI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */\r\n\r\n/*******************  Bit definition for CAN_TDT1R register  ******************/\r\n#define  CAN_TDT1R_DLC                       0x0000000FU        /*!<Data Length Code     */\r\n#define  CAN_TDT1R_TGT                       0x00000100U        /*!<Transmit Global Time */\r\n#define  CAN_TDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp   */\r\n\r\n/*******************  Bit definition for CAN_TDL1R register  ******************/\r\n#define  CAN_TDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */\r\n#define  CAN_TDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */\r\n#define  CAN_TDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */\r\n#define  CAN_TDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */\r\n\r\n/*******************  Bit definition for CAN_TDH1R register  ******************/\r\n#define  CAN_TDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */\r\n#define  CAN_TDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */\r\n#define  CAN_TDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */\r\n#define  CAN_TDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */\r\n\r\n/*******************  Bit definition for CAN_TI2R register  *******************/\r\n#define  CAN_TI2R_TXRQ                       0x00000001U        /*!<Transmit Mailbox Request                   */\r\n#define  CAN_TI2R_RTR                        0x00000002U        /*!<Remote Transmission Request                */\r\n#define  CAN_TI2R_IDE                        0x00000004U        /*!<Identifier Extension                       */\r\n#define  CAN_TI2R_EXID                       0x001FFFF8U        /*!<Extended identifier                        */\r\n#define  CAN_TI2R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */\r\n\r\n/*******************  Bit definition for CAN_TDT2R register  ******************/  \r\n#define  CAN_TDT2R_DLC                       0x0000000FU        /*!<Data Length Code      */\r\n#define  CAN_TDT2R_TGT                       0x00000100U        /*!<Transmit Global Time  */\r\n#define  CAN_TDT2R_TIME                      0xFFFF0000U        /*!<Message Time Stamp    */\r\n\r\n/*******************  Bit definition for CAN_TDL2R register  ******************/\r\n#define  CAN_TDL2R_DATA0                     0x000000FFU        /*!<Data byte 0 */\r\n#define  CAN_TDL2R_DATA1                     0x0000FF00U        /*!<Data byte 1 */\r\n#define  CAN_TDL2R_DATA2                     0x00FF0000U        /*!<Data byte 2 */\r\n#define  CAN_TDL2R_DATA3                     0xFF000000U        /*!<Data byte 3 */\r\n\r\n/*******************  Bit definition for CAN_TDH2R register  ******************/\r\n#define  CAN_TDH2R_DATA4                     0x000000FFU        /*!<Data byte 4 */\r\n#define  CAN_TDH2R_DATA5                     0x0000FF00U        /*!<Data byte 5 */\r\n#define  CAN_TDH2R_DATA6                     0x00FF0000U        /*!<Data byte 6 */\r\n#define  CAN_TDH2R_DATA7                     0xFF000000U        /*!<Data byte 7 */\r\n\r\n/*******************  Bit definition for CAN_RI0R register  *******************/\r\n#define  CAN_RI0R_RTR                        0x00000002U        /*!<Remote Transmission Request                */\r\n#define  CAN_RI0R_IDE                        0x00000004U        /*!<Identifier Extension                       */\r\n#define  CAN_RI0R_EXID                       0x001FFFF8U        /*!<Extended Identifier                        */\r\n#define  CAN_RI0R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */\r\n\r\n/*******************  Bit definition for CAN_RDT0R register  ******************/\r\n#define  CAN_RDT0R_DLC                       0x0000000FU        /*!<Data Length Code */\r\n#define  CAN_RDT0R_FMI                       0x0000FF00U        /*!<Filter Match Index */\r\n#define  CAN_RDT0R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */\r\n\r\n/*******************  Bit definition for CAN_RDL0R register  ******************/\r\n#define  CAN_RDL0R_DATA0                     0x000000FFU        /*!<Data byte 0 */\r\n#define  CAN_RDL0R_DATA1                     0x0000FF00U        /*!<Data byte 1 */\r\n#define  CAN_RDL0R_DATA2                     0x00FF0000U        /*!<Data byte 2 */\r\n#define  CAN_RDL0R_DATA3                     0xFF000000U        /*!<Data byte 3 */\r\n\r\n/*******************  Bit definition for CAN_RDH0R register  ******************/\r\n#define  CAN_RDH0R_DATA4                     0x000000FFU        /*!<Data byte 4 */\r\n#define  CAN_RDH0R_DATA5                     0x0000FF00U        /*!<Data byte 5 */\r\n#define  CAN_RDH0R_DATA6                     0x00FF0000U        /*!<Data byte 6 */\r\n#define  CAN_RDH0R_DATA7                     0xFF000000U        /*!<Data byte 7 */\r\n\r\n/*******************  Bit definition for CAN_RI1R register  *******************/\r\n#define  CAN_RI1R_RTR                        0x00000002U        /*!<Remote Transmission Request                */\r\n#define  CAN_RI1R_IDE                        0x00000004U        /*!<Identifier Extension                       */\r\n#define  CAN_RI1R_EXID                       0x001FFFF8U        /*!<Extended identifier                        */\r\n#define  CAN_RI1R_STID                       0xFFE00000U        /*!<Standard Identifier or Extended Identifier */\r\n\r\n/*******************  Bit definition for CAN_RDT1R register  ******************/\r\n#define  CAN_RDT1R_DLC                       0x0000000FU        /*!<Data Length Code   */\r\n#define  CAN_RDT1R_FMI                       0x0000FF00U        /*!<Filter Match Index */\r\n#define  CAN_RDT1R_TIME                      0xFFFF0000U        /*!<Message Time Stamp */\r\n\r\n/*******************  Bit definition for CAN_RDL1R register  ******************/\r\n#define  CAN_RDL1R_DATA0                     0x000000FFU        /*!<Data byte 0 */\r\n#define  CAN_RDL1R_DATA1                     0x0000FF00U        /*!<Data byte 1 */\r\n#define  CAN_RDL1R_DATA2                     0x00FF0000U        /*!<Data byte 2 */\r\n#define  CAN_RDL1R_DATA3                     0xFF000000U        /*!<Data byte 3 */\r\n\r\n/*******************  Bit definition for CAN_RDH1R register  ******************/\r\n#define  CAN_RDH1R_DATA4                     0x000000FFU        /*!<Data byte 4 */\r\n#define  CAN_RDH1R_DATA5                     0x0000FF00U        /*!<Data byte 5 */\r\n#define  CAN_RDH1R_DATA6                     0x00FF0000U        /*!<Data byte 6 */\r\n#define  CAN_RDH1R_DATA7                     0xFF000000U        /*!<Data byte 7 */\r\n\r\n/*!<CAN filter registers */\r\n/*******************  Bit definition for CAN_FMR register  ********************/\r\n#define  CAN_FMR_FINIT                       ((uint8_t)0x01U)               /*!<Filter Init Mode */\r\n#define  CAN_FMR_CAN2SB                      0x00003F00U        /*!<CAN2 start bank */\r\n\r\n/*******************  Bit definition for CAN_FM1R register  *******************/\r\n#define  CAN_FM1R_FBM                        0x3FFFU            /*!<Filter Mode */\r\n#define  CAN_FM1R_FBM0                       0x0001U            /*!<Filter Init Mode bit 0  */\r\n#define  CAN_FM1R_FBM1                       0x0002U            /*!<Filter Init Mode bit 1  */\r\n#define  CAN_FM1R_FBM2                       0x0004U            /*!<Filter Init Mode bit 2  */\r\n#define  CAN_FM1R_FBM3                       0x0008U            /*!<Filter Init Mode bit 3  */\r\n#define  CAN_FM1R_FBM4                       0x0010U            /*!<Filter Init Mode bit 4  */\r\n#define  CAN_FM1R_FBM5                       0x0020U            /*!<Filter Init Mode bit 5  */\r\n#define  CAN_FM1R_FBM6                       0x0040U            /*!<Filter Init Mode bit 6  */\r\n#define  CAN_FM1R_FBM7                       0x0080U            /*!<Filter Init Mode bit 7  */\r\n#define  CAN_FM1R_FBM8                       0x0100U            /*!<Filter Init Mode bit 8  */\r\n#define  CAN_FM1R_FBM9                       0x0200U            /*!<Filter Init Mode bit 9  */\r\n#define  CAN_FM1R_FBM10                      0x0400U            /*!<Filter Init Mode bit 10 */\r\n#define  CAN_FM1R_FBM11                      0x0800U            /*!<Filter Init Mode bit 11 */\r\n#define  CAN_FM1R_FBM12                      0x1000U            /*!<Filter Init Mode bit 12 */\r\n#define  CAN_FM1R_FBM13                      0x2000U            /*!<Filter Init Mode bit 13 */\r\n\r\n/*******************  Bit definition for CAN_FS1R register  *******************/\r\n#define  CAN_FS1R_FSC                        0x00003FFFU        /*!<Filter Scale Configuration        */\r\n#define  CAN_FS1R_FSC0                       0x00000001U        /*!<Filter Scale Configuration bit 0  */\r\n#define  CAN_FS1R_FSC1                       0x00000002U        /*!<Filter Scale Configuration bit 1  */\r\n#define  CAN_FS1R_FSC2                       0x00000004U        /*!<Filter Scale Configuration bit 2  */\r\n#define  CAN_FS1R_FSC3                       0x00000008U        /*!<Filter Scale Configuration bit 3  */\r\n#define  CAN_FS1R_FSC4                       0x00000010U        /*!<Filter Scale Configuration bit 4  */\r\n#define  CAN_FS1R_FSC5                       0x00000020U        /*!<Filter Scale Configuration bit 5  */\r\n#define  CAN_FS1R_FSC6                       0x00000040U        /*!<Filter Scale Configuration bit 6  */\r\n#define  CAN_FS1R_FSC7                       0x00000080U        /*!<Filter Scale Configuration bit 7  */\r\n#define  CAN_FS1R_FSC8                       0x00000100U        /*!<Filter Scale Configuration bit 8  */\r\n#define  CAN_FS1R_FSC9                       0x00000200U        /*!<Filter Scale Configuration bit 9  */\r\n#define  CAN_FS1R_FSC10                      0x00000400U        /*!<Filter Scale Configuration bit 10 */\r\n#define  CAN_FS1R_FSC11                      0x00000800U        /*!<Filter Scale Configuration bit 11 */\r\n#define  CAN_FS1R_FSC12                      0x00001000U        /*!<Filter Scale Configuration bit 12 */\r\n#define  CAN_FS1R_FSC13                      0x00002000U        /*!<Filter Scale Configuration bit 13 */\r\n\r\n/******************  Bit definition for CAN_FFA1R register  *******************/\r\n#define  CAN_FFA1R_FFA                       0x00003FFFU        /*!<Filter FIFO Assignment */\r\n#define  CAN_FFA1R_FFA0                      0x00000001U        /*!<Filter FIFO Assignment for Filter 0 */\r\n#define  CAN_FFA1R_FFA1                      0x00000002U        /*!<Filter FIFO Assignment for Filter 1 */\r\n#define  CAN_FFA1R_FFA2                      0x00000004U        /*!<Filter FIFO Assignment for Filter 2 */\r\n#define  CAN_FFA1R_FFA3                      0x00000008U        /*!<Filter FIFO Assignment for Filter 3 */\r\n#define  CAN_FFA1R_FFA4                      0x00000010U        /*!<Filter FIFO Assignment for Filter 4 */\r\n#define  CAN_FFA1R_FFA5                      0x00000020U        /*!<Filter FIFO Assignment for Filter 5 */\r\n#define  CAN_FFA1R_FFA6                      0x00000040U        /*!<Filter FIFO Assignment for Filter 6 */\r\n#define  CAN_FFA1R_FFA7                      0x00000080U        /*!<Filter FIFO Assignment for Filter 7 */\r\n#define  CAN_FFA1R_FFA8                      0x00000100U        /*!<Filter FIFO Assignment for Filter 8 */\r\n#define  CAN_FFA1R_FFA9                      0x00000200U        /*!<Filter FIFO Assignment for Filter 9 */\r\n#define  CAN_FFA1R_FFA10                     0x00000400U        /*!<Filter FIFO Assignment for Filter 10 */\r\n#define  CAN_FFA1R_FFA11                     0x00000800U        /*!<Filter FIFO Assignment for Filter 11 */\r\n#define  CAN_FFA1R_FFA12                     0x00001000U        /*!<Filter FIFO Assignment for Filter 12 */\r\n#define  CAN_FFA1R_FFA13                     0x00002000U        /*!<Filter FIFO Assignment for Filter 13 */\r\n\r\n/*******************  Bit definition for CAN_FA1R register  *******************/\r\n#define  CAN_FA1R_FACT                       0x00003FFFU        /*!<Filter Active    */\r\n#define  CAN_FA1R_FACT0                      0x00000001U        /*!<Filter 0 Active  */\r\n#define  CAN_FA1R_FACT1                      0x00000002U        /*!<Filter 1 Active  */\r\n#define  CAN_FA1R_FACT2                      0x00000004U        /*!<Filter 2 Active  */\r\n#define  CAN_FA1R_FACT3                      0x00000008U        /*!<Filter 3 Active  */\r\n#define  CAN_FA1R_FACT4                      0x00000010U        /*!<Filter 4 Active  */\r\n#define  CAN_FA1R_FACT5                      0x00000020U        /*!<Filter 5 Active  */\r\n#define  CAN_FA1R_FACT6                      0x00000040U        /*!<Filter 6 Active  */\r\n#define  CAN_FA1R_FACT7                      0x00000080U        /*!<Filter 7 Active  */\r\n#define  CAN_FA1R_FACT8                      0x00000100U        /*!<Filter 8 Active  */\r\n#define  CAN_FA1R_FACT9                      0x00000200U        /*!<Filter 9 Active  */\r\n#define  CAN_FA1R_FACT10                     0x00000400U        /*!<Filter 10 Active */\r\n#define  CAN_FA1R_FACT11                     0x00000800U        /*!<Filter 11 Active */\r\n#define  CAN_FA1R_FACT12                     0x00001000U        /*!<Filter 12 Active */\r\n#define  CAN_FA1R_FACT13                     0x00002000U        /*!<Filter 13 Active */\r\n\r\n/*******************  Bit definition for CAN_F0R1 register  *******************/\r\n#define  CAN_F0R1_FB0                        0x00000001U        /*!<Filter bit 0 */\r\n#define  CAN_F0R1_FB1                        0x00000002U        /*!<Filter bit 1 */\r\n#define  CAN_F0R1_FB2                        0x00000004U        /*!<Filter bit 2 */\r\n#define  CAN_F0R1_FB3                        0x00000008U        /*!<Filter bit 3 */\r\n#define  CAN_F0R1_FB4                        0x00000010U        /*!<Filter bit 4 */\r\n#define  CAN_F0R1_FB5                        0x00000020U        /*!<Filter bit 5 */\r\n#define  CAN_F0R1_FB6                        0x00000040U        /*!<Filter bit 6 */\r\n#define  CAN_F0R1_FB7                        0x00000080U        /*!<Filter bit 7 */\r\n#define  CAN_F0R1_FB8                        0x00000100U        /*!<Filter bit 8 */\r\n#define  CAN_F0R1_FB9                        0x00000200U        /*!<Filter bit 9 */\r\n#define  CAN_F0R1_FB10                       0x00000400U        /*!<Filter bit 10 */\r\n#define  CAN_F0R1_FB11                       0x00000800U        /*!<Filter bit 11 */\r\n#define  CAN_F0R1_FB12                       0x00001000U        /*!<Filter bit 12 */\r\n#define  CAN_F0R1_FB13                       0x00002000U        /*!<Filter bit 13 */\r\n#define  CAN_F0R1_FB14                       0x00004000U        /*!<Filter bit 14 */\r\n#define  CAN_F0R1_FB15                       0x00008000U        /*!<Filter bit 15 */\r\n#define  CAN_F0R1_FB16                       0x00010000U        /*!<Filter bit 16 */\r\n#define  CAN_F0R1_FB17                       0x00020000U        /*!<Filter bit 17 */\r\n#define  CAN_F0R1_FB18                       0x00040000U        /*!<Filter bit 18 */\r\n#define  CAN_F0R1_FB19                       0x00080000U        /*!<Filter bit 19 */\r\n#define  CAN_F0R1_FB20                       0x00100000U        /*!<Filter bit 20 */\r\n#define  CAN_F0R1_FB21                       0x00200000U        /*!<Filter bit 21 */\r\n#define  CAN_F0R1_FB22                       0x00400000U        /*!<Filter bit 22 */\r\n#define  CAN_F0R1_FB23                       0x00800000U        /*!<Filter bit 23 */\r\n#define  CAN_F0R1_FB24                       0x01000000U        /*!<Filter bit 24 */\r\n#define  CAN_F0R1_FB25                       0x02000000U        /*!<Filter bit 25 */\r\n#define  CAN_F0R1_FB26                       0x04000000U        /*!<Filter bit 26 */\r\n#define  CAN_F0R1_FB27                       0x08000000U        /*!<Filter bit 27 */\r\n#define  CAN_F0R1_FB28                       0x10000000U        /*!<Filter bit 28 */\r\n#define  CAN_F0R1_FB29                       0x20000000U        /*!<Filter bit 29 */\r\n#define  CAN_F0R1_FB30                       0x40000000U        /*!<Filter bit 30 */\r\n#define  CAN_F0R1_FB31                       0x80000000U        /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F1R1 register  *******************/\r\n#define  CAN_F1R1_FB0                        0x00000001U        /*!<Filter bit 0 */\r\n#define  CAN_F1R1_FB1                        0x00000002U        /*!<Filter bit 1 */\r\n#define  CAN_F1R1_FB2                        0x00000004U        /*!<Filter bit 2 */\r\n#define  CAN_F1R1_FB3                        0x00000008U        /*!<Filter bit 3 */\r\n#define  CAN_F1R1_FB4                        0x00000010U        /*!<Filter bit 4 */\r\n#define  CAN_F1R1_FB5                        0x00000020U        /*!<Filter bit 5 */\r\n#define  CAN_F1R1_FB6                        0x00000040U        /*!<Filter bit 6 */\r\n#define  CAN_F1R1_FB7                        0x00000080U        /*!<Filter bit 7 */\r\n#define  CAN_F1R1_FB8                        0x00000100U        /*!<Filter bit 8 */\r\n#define  CAN_F1R1_FB9                        0x00000200U        /*!<Filter bit 9 */\r\n#define  CAN_F1R1_FB10                       0x00000400U        /*!<Filter bit 10 */\r\n#define  CAN_F1R1_FB11                       0x00000800U        /*!<Filter bit 11 */\r\n#define  CAN_F1R1_FB12                       0x00001000U        /*!<Filter bit 12 */\r\n#define  CAN_F1R1_FB13                       0x00002000U        /*!<Filter bit 13 */\r\n#define  CAN_F1R1_FB14                       0x00004000U        /*!<Filter bit 14 */\r\n#define  CAN_F1R1_FB15                       0x00008000U        /*!<Filter bit 15 */\r\n#define  CAN_F1R1_FB16                       0x00010000U        /*!<Filter bit 16 */\r\n#define  CAN_F1R1_FB17                       0x00020000U        /*!<Filter bit 17 */\r\n#define  CAN_F1R1_FB18                       0x00040000U        /*!<Filter bit 18 */\r\n#define  CAN_F1R1_FB19                       0x00080000U        /*!<Filter bit 19 */\r\n#define  CAN_F1R1_FB20                       0x00100000U        /*!<Filter bit 20 */\r\n#define  CAN_F1R1_FB21                       0x00200000U        /*!<Filter bit 21 */\r\n#define  CAN_F1R1_FB22                       0x00400000U        /*!<Filter bit 22 */\r\n#define  CAN_F1R1_FB23                       0x00800000U        /*!<Filter bit 23 */\r\n#define  CAN_F1R1_FB24                       0x01000000U        /*!<Filter bit 24 */\r\n#define  CAN_F1R1_FB25                       0x02000000U        /*!<Filter bit 25 */\r\n#define  CAN_F1R1_FB26                       0x04000000U        /*!<Filter bit 26 */\r\n#define  CAN_F1R1_FB27                       0x08000000U        /*!<Filter bit 27 */\r\n#define  CAN_F1R1_FB28                       0x10000000U        /*!<Filter bit 28 */\r\n#define  CAN_F1R1_FB29                       0x20000000U        /*!<Filter bit 29 */\r\n#define  CAN_F1R1_FB30                       0x40000000U        /*!<Filter bit 30 */\r\n#define  CAN_F1R1_FB31                       0x80000000U        /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F2R1 register  *******************/\r\n#define  CAN_F2R1_FB0                        0x00000001U        /*!<Filter bit 0 */\r\n#define  CAN_F2R1_FB1                        0x00000002U        /*!<Filter bit 1 */\r\n#define  CAN_F2R1_FB2                        0x00000004U        /*!<Filter bit 2 */\r\n#define  CAN_F2R1_FB3                        0x00000008U        /*!<Filter bit 3 */\r\n#define  CAN_F2R1_FB4                        0x00000010U        /*!<Filter bit 4 */\r\n#define  CAN_F2R1_FB5                        0x00000020U        /*!<Filter bit 5 */\r\n#define  CAN_F2R1_FB6                        0x00000040U        /*!<Filter bit 6 */\r\n#define  CAN_F2R1_FB7                        0x00000080U        /*!<Filter bit 7 */\r\n#define  CAN_F2R1_FB8                        0x00000100U        /*!<Filter bit 8 */\r\n#define  CAN_F2R1_FB9                        0x00000200U        /*!<Filter bit 9 */\r\n#define  CAN_F2R1_FB10                       0x00000400U        /*!<Filter bit 10 */\r\n#define  CAN_F2R1_FB11                       0x00000800U        /*!<Filter bit 11 */\r\n#define  CAN_F2R1_FB12                       0x00001000U        /*!<Filter bit 12 */\r\n#define  CAN_F2R1_FB13                       0x00002000U        /*!<Filter bit 13 */\r\n#define  CAN_F2R1_FB14                       0x00004000U        /*!<Filter bit 14 */\r\n#define  CAN_F2R1_FB15                       0x00008000U        /*!<Filter bit 15 */\r\n#define  CAN_F2R1_FB16                       0x00010000U        /*!<Filter bit 16 */\r\n#define  CAN_F2R1_FB17                       0x00020000U        /*!<Filter bit 17 */\r\n#define  CAN_F2R1_FB18                       0x00040000U        /*!<Filter bit 18 */\r\n#define  CAN_F2R1_FB19                       0x00080000U        /*!<Filter bit 19 */\r\n#define  CAN_F2R1_FB20                       0x00100000U        /*!<Filter bit 20 */\r\n#define  CAN_F2R1_FB21                       0x00200000U        /*!<Filter bit 21 */\r\n#define  CAN_F2R1_FB22                       0x00400000U        /*!<Filter bit 22 */\r\n#define  CAN_F2R1_FB23                       0x00800000U        /*!<Filter bit 23 */\r\n#define  CAN_F2R1_FB24                       0x01000000U        /*!<Filter bit 24 */\r\n#define  CAN_F2R1_FB25                       0x02000000U        /*!<Filter bit 25 */\r\n#define  CAN_F2R1_FB26                       0x04000000U        /*!<Filter bit 26 */\r\n#define  CAN_F2R1_FB27                       0x08000000U        /*!<Filter bit 27 */\r\n#define  CAN_F2R1_FB28                       0x10000000U        /*!<Filter bit 28 */\r\n#define  CAN_F2R1_FB29                       0x20000000U        /*!<Filter bit 29 */\r\n#define  CAN_F2R1_FB30                       0x40000000U        /*!<Filter bit 30 */\r\n#define  CAN_F2R1_FB31                       0x80000000U        /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F3R1 register  *******************/\r\n#define  CAN_F3R1_FB0                        0x00000001U        /*!<Filter bit 0 */\r\n#define  CAN_F3R1_FB1                        0x00000002U        /*!<Filter bit 1 */\r\n#define  CAN_F3R1_FB2                        0x00000004U        /*!<Filter bit 2 */\r\n#define  CAN_F3R1_FB3                        0x00000008U        /*!<Filter bit 3 */\r\n#define  CAN_F3R1_FB4                        0x00000010U        /*!<Filter bit 4 */\r\n#define  CAN_F3R1_FB5                        0x00000020U        /*!<Filter bit 5 */\r\n#define  CAN_F3R1_FB6                        0x00000040U        /*!<Filter bit 6 */\r\n#define  CAN_F3R1_FB7                        0x00000080U        /*!<Filter bit 7 */\r\n#define  CAN_F3R1_FB8                        0x00000100U        /*!<Filter bit 8 */\r\n#define  CAN_F3R1_FB9                        0x00000200U        /*!<Filter bit 9 */\r\n#define  CAN_F3R1_FB10                       0x00000400U        /*!<Filter bit 10 */\r\n#define  CAN_F3R1_FB11                       0x00000800U        /*!<Filter bit 11 */\r\n#define  CAN_F3R1_FB12                       0x00001000U        /*!<Filter bit 12 */\r\n#define  CAN_F3R1_FB13                       0x00002000U        /*!<Filter bit 13 */\r\n#define  CAN_F3R1_FB14                       0x00004000U        /*!<Filter bit 14 */\r\n#define  CAN_F3R1_FB15                       0x00008000U        /*!<Filter bit 15 */\r\n#define  CAN_F3R1_FB16                       0x00010000U        /*!<Filter bit 16 */\r\n#define  CAN_F3R1_FB17                       0x00020000U        /*!<Filter bit 17 */\r\n#define  CAN_F3R1_FB18                       0x00040000U        /*!<Filter bit 18 */\r\n#define  CAN_F3R1_FB19                       0x00080000U        /*!<Filter bit 19 */\r\n#define  CAN_F3R1_FB20                       0x00100000U        /*!<Filter bit 20 */\r\n#define  CAN_F3R1_FB21                       0x00200000U        /*!<Filter bit 21 */\r\n#define  CAN_F3R1_FB22                       0x00400000U        /*!<Filter bit 22 */\r\n#define  CAN_F3R1_FB23                       0x00800000U        /*!<Filter bit 23 */\r\n#define  CAN_F3R1_FB24                       0x01000000U        /*!<Filter bit 24 */\r\n#define  CAN_F3R1_FB25                       0x02000000U        /*!<Filter bit 25 */\r\n#define  CAN_F3R1_FB26                       0x04000000U        /*!<Filter bit 26 */\r\n#define  CAN_F3R1_FB27                       0x08000000U        /*!<Filter bit 27 */\r\n#define  CAN_F3R1_FB28                       0x10000000U        /*!<Filter bit 28 */\r\n#define  CAN_F3R1_FB29                       0x20000000U        /*!<Filter bit 29 */\r\n#define  CAN_F3R1_FB30                       0x40000000U        /*!<Filter bit 30 */\r\n#define  CAN_F3R1_FB31                       0x80000000U        /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F4R1 register  *******************/\r\n#define  CAN_F4R1_FB0                        0x00000001U        /*!<Filter bit 0 */\r\n#define  CAN_F4R1_FB1                        0x00000002U        /*!<Filter bit 1 */\r\n#define  CAN_F4R1_FB2                        0x00000004U        /*!<Filter bit 2 */\r\n#define  CAN_F4R1_FB3                        0x00000008U        /*!<Filter bit 3 */\r\n#define  CAN_F4R1_FB4                        0x00000010U        /*!<Filter bit 4 */\r\n#define  CAN_F4R1_FB5                        0x00000020U        /*!<Filter bit 5 */\r\n#define  CAN_F4R1_FB6                        0x00000040U        /*!<Filter bit 6 */\r\n#define  CAN_F4R1_FB7                        0x00000080U        /*!<Filter bit 7 */\r\n#define  CAN_F4R1_FB8                        0x00000100U        /*!<Filter bit 8 */\r\n#define  CAN_F4R1_FB9                        0x00000200U        /*!<Filter bit 9 */\r\n#define  CAN_F4R1_FB10                       0x00000400U        /*!<Filter bit 10 */\r\n#define  CAN_F4R1_FB11                       0x00000800U        /*!<Filter bit 11 */\r\n#define  CAN_F4R1_FB12                       0x00001000U        /*!<Filter bit 12 */\r\n#define  CAN_F4R1_FB13                       0x00002000U        /*!<Filter bit 13 */\r\n#define  CAN_F4R1_FB14                       0x00004000U        /*!<Filter bit 14 */\r\n#define  CAN_F4R1_FB15                       0x00008000U        /*!<Filter bit 15 */\r\n#define  CAN_F4R1_FB16                       0x00010000U        /*!<Filter bit 16 */\r\n#define  CAN_F4R1_FB17                       0x00020000U        /*!<Filter bit 17 */\r\n#define  CAN_F4R1_FB18                       0x00040000U        /*!<Filter bit 18 */\r\n#define  CAN_F4R1_FB19                       0x00080000U        /*!<Filter bit 19 */\r\n#define  CAN_F4R1_FB20                       0x00100000U        /*!<Filter bit 20 */\r\n#define  CAN_F4R1_FB21                       0x00200000U        /*!<Filter bit 21 */\r\n#define  CAN_F4R1_FB22                       0x00400000U        /*!<Filter bit 22 */\r\n#define  CAN_F4R1_FB23                       0x00800000U        /*!<Filter bit 23 */\r\n#define  CAN_F4R1_FB24                       0x01000000U        /*!<Filter bit 24 */\r\n#define  CAN_F4R1_FB25                       0x02000000U        /*!<Filter bit 25 */\r\n#define  CAN_F4R1_FB26                       0x04000000U        /*!<Filter bit 26 */\r\n#define  CAN_F4R1_FB27                       0x08000000U        /*!<Filter bit 27 */\r\n#define  CAN_F4R1_FB28                       0x10000000U        /*!<Filter bit 28 */\r\n#define  CAN_F4R1_FB29                       0x20000000U        /*!<Filter bit 29 */\r\n#define  CAN_F4R1_FB30                       0x40000000U        /*!<Filter bit 30 */\r\n#define  CAN_F4R1_FB31                       0x80000000U        /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F5R1 register  *******************/\r\n#define  CAN_F5R1_FB0                        0x00000001U        /*!<Filter bit 0 */\r\n#define  CAN_F5R1_FB1                        0x00000002U        /*!<Filter bit 1 */\r\n#define  CAN_F5R1_FB2                        0x00000004U        /*!<Filter bit 2 */\r\n#define  CAN_F5R1_FB3                        0x00000008U        /*!<Filter bit 3 */\r\n#define  CAN_F5R1_FB4                        0x00000010U        /*!<Filter bit 4 */\r\n#define  CAN_F5R1_FB5                        0x00000020U        /*!<Filter bit 5 */\r\n#define  CAN_F5R1_FB6                        0x00000040U        /*!<Filter bit 6 */\r\n#define  CAN_F5R1_FB7                        0x00000080U        /*!<Filter bit 7 */\r\n#define  CAN_F5R1_FB8                        0x00000100U        /*!<Filter bit 8 */\r\n#define  CAN_F5R1_FB9                        0x00000200U        /*!<Filter bit 9 */\r\n#define  CAN_F5R1_FB10                       0x00000400U        /*!<Filter bit 10 */\r\n#define  CAN_F5R1_FB11                       0x00000800U        /*!<Filter bit 11 */\r\n#define  CAN_F5R1_FB12                       0x00001000U        /*!<Filter bit 12 */\r\n#define  CAN_F5R1_FB13                       0x00002000U        /*!<Filter bit 13 */\r\n#define  CAN_F5R1_FB14                       0x00004000U        /*!<Filter bit 14 */\r\n#define  CAN_F5R1_FB15                       0x00008000U        /*!<Filter bit 15 */\r\n#define  CAN_F5R1_FB16                       0x00010000U        /*!<Filter bit 16 */\r\n#define  CAN_F5R1_FB17                       0x00020000U        /*!<Filter bit 17 */\r\n#define  CAN_F5R1_FB18                       0x00040000U        /*!<Filter bit 18 */\r\n#define  CAN_F5R1_FB19                       0x00080000U        /*!<Filter bit 19 */\r\n#define  CAN_F5R1_FB20                       0x00100000U        /*!<Filter bit 20 */\r\n#define  CAN_F5R1_FB21                       0x00200000U        /*!<Filter bit 21 */\r\n#define  CAN_F5R1_FB22                       0x00400000U        /*!<Filter bit 22 */\r\n#define  CAN_F5R1_FB23                       0x00800000U        /*!<Filter bit 23 */\r\n#define  CAN_F5R1_FB24                       0x01000000U        /*!<Filter bit 24 */\r\n#define  CAN_F5R1_FB25                       0x02000000U        /*!<Filter bit 25 */\r\n#define  CAN_F5R1_FB26                       0x04000000U        /*!<Filter bit 26 */\r\n#define  CAN_F5R1_FB27                       0x08000000U        /*!<Filter bit 27 */\r\n#define  CAN_F5R1_FB28                       0x10000000U        /*!<Filter bit 28 */\r\n#define  CAN_F5R1_FB29                       0x20000000U        /*!<Filter bit 29 */\r\n#define  CAN_F5R1_FB30                       0x40000000U        /*!<Filter bit 30 */\r\n#define  CAN_F5R1_FB31                       0x80000000U        /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F6R1 register  *******************/\r\n#define  CAN_F6R1_FB0                        0x00000001U        /*!<Filter bit 0 */\r\n#define  CAN_F6R1_FB1                        0x00000002U        /*!<Filter bit 1 */\r\n#define  CAN_F6R1_FB2                        0x00000004U        /*!<Filter bit 2 */\r\n#define  CAN_F6R1_FB3                        0x00000008U        /*!<Filter bit 3 */\r\n#define  CAN_F6R1_FB4                        0x00000010U        /*!<Filter bit 4 */\r\n#define  CAN_F6R1_FB5                        0x00000020U        /*!<Filter bit 5 */\r\n#define  CAN_F6R1_FB6                        0x00000040U        /*!<Filter bit 6 */\r\n#define  CAN_F6R1_FB7                        0x00000080U        /*!<Filter bit 7 */\r\n#define  CAN_F6R1_FB8                        0x00000100U        /*!<Filter bit 8 */\r\n#define  CAN_F6R1_FB9                        0x00000200U        /*!<Filter bit 9 */\r\n#define  CAN_F6R1_FB10                       0x00000400U        /*!<Filter bit 10 */\r\n#define  CAN_F6R1_FB11                       0x00000800U        /*!<Filter bit 11 */\r\n#define  CAN_F6R1_FB12                       0x00001000U        /*!<Filter bit 12 */\r\n#define  CAN_F6R1_FB13                       0x00002000U        /*!<Filter bit 13 */\r\n#define  CAN_F6R1_FB14                       0x00004000U        /*!<Filter bit 14 */\r\n#define  CAN_F6R1_FB15                       0x00008000U        /*!<Filter bit 15 */\r\n#define  CAN_F6R1_FB16                       0x00010000U        /*!<Filter bit 16 */\r\n#define  CAN_F6R1_FB17                       0x00020000U        /*!<Filter bit 17 */\r\n#define  CAN_F6R1_FB18                       0x00040000U        /*!<Filter bit 18 */\r\n#define  CAN_F6R1_FB19                       0x00080000U        /*!<Filter bit 19 */\r\n#define  CAN_F6R1_FB20                       0x00100000U        /*!<Filter bit 20 */\r\n#define  CAN_F6R1_FB21                       0x00200000U        /*!<Filter bit 21 */\r\n#define  CAN_F6R1_FB22                       0x00400000U        /*!<Filter bit 22 */\r\n#define  CAN_F6R1_FB23                       0x00800000U        /*!<Filter bit 23 */\r\n#define  CAN_F6R1_FB24                       0x01000000U        /*!<Filter bit 24 */\r\n#define  CAN_F6R1_FB25                       0x02000000U        /*!<Filter bit 25 */\r\n#define  CAN_F6R1_FB26                       0x04000000U        /*!<Filter bit 26 */\r\n#define  CAN_F6R1_FB27                       0x08000000U        /*!<Filter bit 27 */\r\n#define  CAN_F6R1_FB28                       0x10000000U        /*!<Filter bit 28 */\r\n#define  CAN_F6R1_FB29                       0x20000000U        /*!<Filter bit 29 */\r\n#define  CAN_F6R1_FB30                       0x40000000U        /*!<Filter bit 30 */\r\n#define  CAN_F6R1_FB31                       0x80000000U        /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F7R1 register  *******************/\r\n#define  CAN_F7R1_FB0                        0x00000001U        /*!<Filter bit 0 */\r\n#define  CAN_F7R1_FB1                        0x00000002U        /*!<Filter bit 1 */\r\n#define  CAN_F7R1_FB2                        0x00000004U        /*!<Filter bit 2 */\r\n#define  CAN_F7R1_FB3                        0x00000008U        /*!<Filter bit 3 */\r\n#define  CAN_F7R1_FB4                        0x00000010U        /*!<Filter bit 4 */\r\n#define  CAN_F7R1_FB5                        0x00000020U        /*!<Filter bit 5 */\r\n#define  CAN_F7R1_FB6                        0x00000040U        /*!<Filter bit 6 */\r\n#define  CAN_F7R1_FB7                        0x00000080U        /*!<Filter bit 7 */\r\n#define  CAN_F7R1_FB8                        0x00000100U        /*!<Filter bit 8 */\r\n#define  CAN_F7R1_FB9                        0x00000200U        /*!<Filter bit 9 */\r\n#define  CAN_F7R1_FB10                       0x00000400U        /*!<Filter bit 10 */\r\n#define  CAN_F7R1_FB11                       0x00000800U        /*!<Filter bit 11 */\r\n#define  CAN_F7R1_FB12                       0x00001000U        /*!<Filter bit 12 */\r\n#define  CAN_F7R1_FB13                       0x00002000U        /*!<Filter bit 13 */\r\n#define  CAN_F7R1_FB14                       0x00004000U        /*!<Filter bit 14 */\r\n#define  CAN_F7R1_FB15                       0x00008000U        /*!<Filter bit 15 */\r\n#define  CAN_F7R1_FB16                       0x00010000U        /*!<Filter bit 16 */\r\n#define  CAN_F7R1_FB17                       0x00020000U        /*!<Filter bit 17 */\r\n#define  CAN_F7R1_FB18                       0x00040000U        /*!<Filter bit 18 */\r\n#define  CAN_F7R1_FB19                       0x00080000U        /*!<Filter bit 19 */\r\n#define  CAN_F7R1_FB20                       0x00100000U        /*!<Filter bit 20 */\r\n#define  CAN_F7R1_FB21                       0x00200000U        /*!<Filter bit 21 */\r\n#define  CAN_F7R1_FB22                       0x00400000U        /*!<Filter bit 22 */\r\n#define  CAN_F7R1_FB23                       0x00800000U        /*!<Filter bit 23 */\r\n#define  CAN_F7R1_FB24                       0x01000000U        /*!<Filter bit 24 */\r\n#define  CAN_F7R1_FB25                       0x02000000U        /*!<Filter bit 25 */\r\n#define  CAN_F7R1_FB26                       0x04000000U        /*!<Filter bit 26 */\r\n#define  CAN_F7R1_FB27                       0x08000000U        /*!<Filter bit 27 */\r\n#define  CAN_F7R1_FB28                       0x10000000U        /*!<Filter bit 28 */\r\n#define  CAN_F7R1_FB29                       0x20000000U        /*!<Filter bit 29 */\r\n#define  CAN_F7R1_FB30                       0x40000000U        /*!<Filter bit 30 */\r\n#define  CAN_F7R1_FB31                       0x80000000U        /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F8R1 register  *******************/\r\n#define  CAN_F8R1_FB0                        0x00000001U        /*!<Filter bit 0 */\r\n#define  CAN_F8R1_FB1                        0x00000002U        /*!<Filter bit 1 */\r\n#define  CAN_F8R1_FB2                        0x00000004U        /*!<Filter bit 2 */\r\n#define  CAN_F8R1_FB3                        0x00000008U        /*!<Filter bit 3 */\r\n#define  CAN_F8R1_FB4                        0x00000010U        /*!<Filter bit 4 */\r\n#define  CAN_F8R1_FB5                        0x00000020U        /*!<Filter bit 5 */\r\n#define  CAN_F8R1_FB6                        0x00000040U        /*!<Filter bit 6 */\r\n#define  CAN_F8R1_FB7                        0x00000080U        /*!<Filter bit 7 */\r\n#define  CAN_F8R1_FB8                        0x00000100U        /*!<Filter bit 8 */\r\n#define  CAN_F8R1_FB9                        0x00000200U        /*!<Filter bit 9 */\r\n#define  CAN_F8R1_FB10                       0x00000400U        /*!<Filter bit 10 */\r\n#define  CAN_F8R1_FB11                       0x00000800U        /*!<Filter bit 11 */\r\n#define  CAN_F8R1_FB12                       0x00001000U        /*!<Filter bit 12 */\r\n#define  CAN_F8R1_FB13                       0x00002000U        /*!<Filter bit 13 */\r\n#define  CAN_F8R1_FB14                       0x00004000U        /*!<Filter bit 14 */\r\n#define  CAN_F8R1_FB15                       0x00008000U        /*!<Filter bit 15 */\r\n#define  CAN_F8R1_FB16                       0x00010000U        /*!<Filter bit 16 */\r\n#define  CAN_F8R1_FB17                       0x00020000U        /*!<Filter bit 17 */\r\n#define  CAN_F8R1_FB18                       0x00040000U        /*!<Filter bit 18 */\r\n#define  CAN_F8R1_FB19                       0x00080000U        /*!<Filter bit 19 */\r\n#define  CAN_F8R1_FB20                       0x00100000U        /*!<Filter bit 20 */\r\n#define  CAN_F8R1_FB21                       0x00200000U        /*!<Filter bit 21 */\r\n#define  CAN_F8R1_FB22                       0x00400000U        /*!<Filter bit 22 */\r\n#define  CAN_F8R1_FB23                       0x00800000U        /*!<Filter bit 23 */\r\n#define  CAN_F8R1_FB24                       0x01000000U        /*!<Filter bit 24 */\r\n#define  CAN_F8R1_FB25                       0x02000000U        /*!<Filter bit 25 */\r\n#define  CAN_F8R1_FB26                       0x04000000U        /*!<Filter bit 26 */\r\n#define  CAN_F8R1_FB27                       0x08000000U        /*!<Filter bit 27 */\r\n#define  CAN_F8R1_FB28                       0x10000000U        /*!<Filter bit 28 */\r\n#define  CAN_F8R1_FB29                       0x20000000U        /*!<Filter bit 29 */\r\n#define  CAN_F8R1_FB30                       0x40000000U        /*!<Filter bit 30 */\r\n#define  CAN_F8R1_FB31                       0x80000000U        /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F9R1 register  *******************/\r\n#define  CAN_F9R1_FB0                        0x00000001U        /*!<Filter bit 0 */\r\n#define  CAN_F9R1_FB1                        0x00000002U        /*!<Filter bit 1 */\r\n#define  CAN_F9R1_FB2                        0x00000004U        /*!<Filter bit 2 */\r\n#define  CAN_F9R1_FB3                        0x00000008U        /*!<Filter bit 3 */\r\n#define  CAN_F9R1_FB4                        0x00000010U        /*!<Filter bit 4 */\r\n#define  CAN_F9R1_FB5                        0x00000020U        /*!<Filter bit 5 */\r\n#define  CAN_F9R1_FB6                        0x00000040U        /*!<Filter bit 6 */\r\n#define  CAN_F9R1_FB7                        0x00000080U        /*!<Filter bit 7 */\r\n#define  CAN_F9R1_FB8                        0x00000100U        /*!<Filter bit 8 */\r\n#define  CAN_F9R1_FB9                        0x00000200U        /*!<Filter bit 9 */\r\n#define  CAN_F9R1_FB10                       0x00000400U        /*!<Filter bit 10 */\r\n#define  CAN_F9R1_FB11                       0x00000800U        /*!<Filter bit 11 */\r\n#define  CAN_F9R1_FB12                       0x00001000U        /*!<Filter bit 12 */\r\n#define  CAN_F9R1_FB13                       0x00002000U        /*!<Filter bit 13 */\r\n#define  CAN_F9R1_FB14                       0x00004000U        /*!<Filter bit 14 */\r\n#define  CAN_F9R1_FB15                       0x00008000U        /*!<Filter bit 15 */\r\n#define  CAN_F9R1_FB16                       0x00010000U        /*!<Filter bit 16 */\r\n#define  CAN_F9R1_FB17                       0x00020000U        /*!<Filter bit 17 */\r\n#define  CAN_F9R1_FB18                       0x00040000U        /*!<Filter bit 18 */\r\n#define  CAN_F9R1_FB19                       0x00080000U        /*!<Filter bit 19 */\r\n#define  CAN_F9R1_FB20                       0x00100000U        /*!<Filter bit 20 */\r\n#define  CAN_F9R1_FB21                       0x00200000U        /*!<Filter bit 21 */\r\n#define  CAN_F9R1_FB22                       0x00400000U        /*!<Filter bit 22 */\r\n#define  CAN_F9R1_FB23                       0x00800000U        /*!<Filter bit 23 */\r\n#define  CAN_F9R1_FB24                       0x01000000U        /*!<Filter bit 24 */\r\n#define  CAN_F9R1_FB25                       0x02000000U        /*!<Filter bit 25 */\r\n#define  CAN_F9R1_FB26                       0x04000000U        /*!<Filter bit 26 */\r\n#define  CAN_F9R1_FB27                       0x08000000U        /*!<Filter bit 27 */\r\n#define  CAN_F9R1_FB28                       0x10000000U        /*!<Filter bit 28 */\r\n#define  CAN_F9R1_FB29                       0x20000000U        /*!<Filter bit 29 */\r\n#define  CAN_F9R1_FB30                       0x40000000U        /*!<Filter bit 30 */\r\n#define  CAN_F9R1_FB31                       0x80000000U        /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F10R1 register  ******************/\r\n#define  CAN_F10R1_FB0                       0x00000001U        /*!<Filter bit 0 */\r\n#define  CAN_F10R1_FB1                       0x00000002U        /*!<Filter bit 1 */\r\n#define  CAN_F10R1_FB2                       0x00000004U        /*!<Filter bit 2 */\r\n#define  CAN_F10R1_FB3                       0x00000008U        /*!<Filter bit 3 */\r\n#define  CAN_F10R1_FB4                       0x00000010U        /*!<Filter bit 4 */\r\n#define  CAN_F10R1_FB5                       0x00000020U        /*!<Filter bit 5 */\r\n#define  CAN_F10R1_FB6                       0x00000040U        /*!<Filter bit 6 */\r\n#define  CAN_F10R1_FB7                       0x00000080U        /*!<Filter bit 7 */\r\n#define  CAN_F10R1_FB8                       0x00000100U        /*!<Filter bit 8 */\r\n#define  CAN_F10R1_FB9                       0x00000200U        /*!<Filter bit 9 */\r\n#define  CAN_F10R1_FB10                      0x00000400U        /*!<Filter bit 10 */\r\n#define  CAN_F10R1_FB11                      0x00000800U        /*!<Filter bit 11 */\r\n#define  CAN_F10R1_FB12                      0x00001000U        /*!<Filter bit 12 */\r\n#define  CAN_F10R1_FB13                      0x00002000U        /*!<Filter bit 13 */\r\n#define  CAN_F10R1_FB14                      0x00004000U        /*!<Filter bit 14 */\r\n#define  CAN_F10R1_FB15                      0x00008000U        /*!<Filter bit 15 */\r\n#define  CAN_F10R1_FB16                      0x00010000U        /*!<Filter bit 16 */\r\n#define  CAN_F10R1_FB17                      0x00020000U        /*!<Filter bit 17 */\r\n#define  CAN_F10R1_FB18                      0x00040000U        /*!<Filter bit 18 */\r\n#define  CAN_F10R1_FB19                      0x00080000U        /*!<Filter bit 19 */\r\n#define  CAN_F10R1_FB20                      0x00100000U        /*!<Filter bit 20 */\r\n#define  CAN_F10R1_FB21                      0x00200000U        /*!<Filter bit 21 */\r\n#define  CAN_F10R1_FB22                      0x00400000U        /*!<Filter bit 22 */\r\n#define  CAN_F10R1_FB23                      0x00800000U        /*!<Filter bit 23 */\r\n#define  CAN_F10R1_FB24                      0x01000000U        /*!<Filter bit 24 */\r\n#define  CAN_F10R1_FB25                      0x02000000U        /*!<Filter bit 25 */\r\n#define  CAN_F10R1_FB26                      0x04000000U        /*!<Filter bit 26 */\r\n#define  CAN_F10R1_FB27                      0x08000000U        /*!<Filter bit 27 */\r\n#define  CAN_F10R1_FB28                      0x10000000U        /*!<Filter bit 28 */\r\n#define  CAN_F10R1_FB29                      0x20000000U        /*!<Filter bit 29 */\r\n#define  CAN_F10R1_FB30                      0x40000000U        /*!<Filter bit 30 */\r\n#define  CAN_F10R1_FB31                      0x80000000U        /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F11R1 register  ******************/\r\n#define  CAN_F11R1_FB0                       0x00000001U        /*!<Filter bit 0 */\r\n#define  CAN_F11R1_FB1                       0x00000002U        /*!<Filter bit 1 */\r\n#define  CAN_F11R1_FB2                       0x00000004U        /*!<Filter bit 2 */\r\n#define  CAN_F11R1_FB3                       0x00000008U        /*!<Filter bit 3 */\r\n#define  CAN_F11R1_FB4                       0x00000010U        /*!<Filter bit 4 */\r\n#define  CAN_F11R1_FB5                       0x00000020U        /*!<Filter bit 5 */\r\n#define  CAN_F11R1_FB6                       0x00000040U        /*!<Filter bit 6 */\r\n#define  CAN_F11R1_FB7                       0x00000080U        /*!<Filter bit 7 */\r\n#define  CAN_F11R1_FB8                       0x00000100U        /*!<Filter bit 8 */\r\n#define  CAN_F11R1_FB9                       0x00000200U        /*!<Filter bit 9 */\r\n#define  CAN_F11R1_FB10                      0x00000400U        /*!<Filter bit 10 */\r\n#define  CAN_F11R1_FB11                      0x00000800U        /*!<Filter bit 11 */\r\n#define  CAN_F11R1_FB12                      0x00001000U        /*!<Filter bit 12 */\r\n#define  CAN_F11R1_FB13                      0x00002000U        /*!<Filter bit 13 */\r\n#define  CAN_F11R1_FB14                      0x00004000U        /*!<Filter bit 14 */\r\n#define  CAN_F11R1_FB15                      0x00008000U        /*!<Filter bit 15 */\r\n#define  CAN_F11R1_FB16                      0x00010000U        /*!<Filter bit 16 */\r\n#define  CAN_F11R1_FB17                      0x00020000U        /*!<Filter bit 17 */\r\n#define  CAN_F11R1_FB18                      0x00040000U        /*!<Filter bit 18 */\r\n#define  CAN_F11R1_FB19                      0x00080000U        /*!<Filter bit 19 */\r\n#define  CAN_F11R1_FB20                      0x00100000U        /*!<Filter bit 20 */\r\n#define  CAN_F11R1_FB21                      0x00200000U        /*!<Filter bit 21 */\r\n#define  CAN_F11R1_FB22                      0x00400000U        /*!<Filter bit 22 */\r\n#define  CAN_F11R1_FB23                      0x00800000U        /*!<Filter bit 23 */\r\n#define  CAN_F11R1_FB24                      0x01000000U        /*!<Filter bit 24 */\r\n#define  CAN_F11R1_FB25                      0x02000000U        /*!<Filter bit 25 */\r\n#define  CAN_F11R1_FB26                      0x04000000U        /*!<Filter bit 26 */\r\n#define  CAN_F11R1_FB27                      0x08000000U        /*!<Filter bit 27 */\r\n#define  CAN_F11R1_FB28                      0x10000000U        /*!<Filter bit 28 */\r\n#define  CAN_F11R1_FB29                      0x20000000U        /*!<Filter bit 29 */\r\n#define  CAN_F11R1_FB30                      0x40000000U        /*!<Filter bit 30 */\r\n#define  CAN_F11R1_FB31                      0x80000000U        /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F12R1 register  ******************/\r\n#define  CAN_F12R1_FB0                       0x00000001U        /*!<Filter bit 0 */\r\n#define  CAN_F12R1_FB1                       0x00000002U        /*!<Filter bit 1 */\r\n#define  CAN_F12R1_FB2                       0x00000004U        /*!<Filter bit 2 */\r\n#define  CAN_F12R1_FB3                       0x00000008U        /*!<Filter bit 3 */\r\n#define  CAN_F12R1_FB4                       0x00000010U        /*!<Filter bit 4 */\r\n#define  CAN_F12R1_FB5                       0x00000020U        /*!<Filter bit 5 */\r\n#define  CAN_F12R1_FB6                       0x00000040U        /*!<Filter bit 6 */\r\n#define  CAN_F12R1_FB7                       0x00000080U        /*!<Filter bit 7 */\r\n#define  CAN_F12R1_FB8                       0x00000100U        /*!<Filter bit 8 */\r\n#define  CAN_F12R1_FB9                       0x00000200U        /*!<Filter bit 9 */\r\n#define  CAN_F12R1_FB10                      0x00000400U        /*!<Filter bit 10 */\r\n#define  CAN_F12R1_FB11                      0x00000800U        /*!<Filter bit 11 */\r\n#define  CAN_F12R1_FB12                      0x00001000U        /*!<Filter bit 12 */\r\n#define  CAN_F12R1_FB13                      0x00002000U        /*!<Filter bit 13 */\r\n#define  CAN_F12R1_FB14                      0x00004000U        /*!<Filter bit 14 */\r\n#define  CAN_F12R1_FB15                      0x00008000U        /*!<Filter bit 15 */\r\n#define  CAN_F12R1_FB16                      0x00010000U        /*!<Filter bit 16 */\r\n#define  CAN_F12R1_FB17                      0x00020000U        /*!<Filter bit 17 */\r\n#define  CAN_F12R1_FB18                      0x00040000U        /*!<Filter bit 18 */\r\n#define  CAN_F12R1_FB19                      0x00080000U        /*!<Filter bit 19 */\r\n#define  CAN_F12R1_FB20                      0x00100000U        /*!<Filter bit 20 */\r\n#define  CAN_F12R1_FB21                      0x00200000U        /*!<Filter bit 21 */\r\n#define  CAN_F12R1_FB22                      0x00400000U        /*!<Filter bit 22 */\r\n#define  CAN_F12R1_FB23                      0x00800000U        /*!<Filter bit 23 */\r\n#define  CAN_F12R1_FB24                      0x01000000U        /*!<Filter bit 24 */\r\n#define  CAN_F12R1_FB25                      0x02000000U        /*!<Filter bit 25 */\r\n#define  CAN_F12R1_FB26                      0x04000000U        /*!<Filter bit 26 */\r\n#define  CAN_F12R1_FB27                      0x08000000U        /*!<Filter bit 27 */\r\n#define  CAN_F12R1_FB28                      0x10000000U        /*!<Filter bit 28 */\r\n#define  CAN_F12R1_FB29                      0x20000000U        /*!<Filter bit 29 */\r\n#define  CAN_F12R1_FB30                      0x40000000U        /*!<Filter bit 30 */\r\n#define  CAN_F12R1_FB31                      0x80000000U        /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F13R1 register  ******************/\r\n#define  CAN_F13R1_FB0                       0x00000001U        /*!<Filter bit 0 */\r\n#define  CAN_F13R1_FB1                       0x00000002U        /*!<Filter bit 1 */\r\n#define  CAN_F13R1_FB2                       0x00000004U        /*!<Filter bit 2 */\r\n#define  CAN_F13R1_FB3                       0x00000008U        /*!<Filter bit 3 */\r\n#define  CAN_F13R1_FB4                       0x00000010U        /*!<Filter bit 4 */\r\n#define  CAN_F13R1_FB5                       0x00000020U        /*!<Filter bit 5 */\r\n#define  CAN_F13R1_FB6                       0x00000040U        /*!<Filter bit 6 */\r\n#define  CAN_F13R1_FB7                       0x00000080U        /*!<Filter bit 7 */\r\n#define  CAN_F13R1_FB8                       0x00000100U        /*!<Filter bit 8 */\r\n#define  CAN_F13R1_FB9                       0x00000200U        /*!<Filter bit 9 */\r\n#define  CAN_F13R1_FB10                      0x00000400U        /*!<Filter bit 10 */\r\n#define  CAN_F13R1_FB11                      0x00000800U        /*!<Filter bit 11 */\r\n#define  CAN_F13R1_FB12                      0x00001000U        /*!<Filter bit 12 */\r\n#define  CAN_F13R1_FB13                      0x00002000U        /*!<Filter bit 13 */\r\n#define  CAN_F13R1_FB14                      0x00004000U        /*!<Filter bit 14 */\r\n#define  CAN_F13R1_FB15                      0x00008000U        /*!<Filter bit 15 */\r\n#define  CAN_F13R1_FB16                      0x00010000U        /*!<Filter bit 16 */\r\n#define  CAN_F13R1_FB17                      0x00020000U        /*!<Filter bit 17 */\r\n#define  CAN_F13R1_FB18                      0x00040000U        /*!<Filter bit 18 */\r\n#define  CAN_F13R1_FB19                      0x00080000U        /*!<Filter bit 19 */\r\n#define  CAN_F13R1_FB20                      0x00100000U        /*!<Filter bit 20 */\r\n#define  CAN_F13R1_FB21                      0x00200000U        /*!<Filter bit 21 */\r\n#define  CAN_F13R1_FB22                      0x00400000U        /*!<Filter bit 22 */\r\n#define  CAN_F13R1_FB23                      0x00800000U        /*!<Filter bit 23 */\r\n#define  CAN_F13R1_FB24                      0x01000000U        /*!<Filter bit 24 */\r\n#define  CAN_F13R1_FB25                      0x02000000U        /*!<Filter bit 25 */\r\n#define  CAN_F13R1_FB26                      0x04000000U        /*!<Filter bit 26 */\r\n#define  CAN_F13R1_FB27                      0x08000000U        /*!<Filter bit 27 */\r\n#define  CAN_F13R1_FB28                      0x10000000U        /*!<Filter bit 28 */\r\n#define  CAN_F13R1_FB29                      0x20000000U        /*!<Filter bit 29 */\r\n#define  CAN_F13R1_FB30                      0x40000000U        /*!<Filter bit 30 */\r\n#define  CAN_F13R1_FB31                      0x80000000U        /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F0R2 register  *******************/\r\n#define  CAN_F0R2_FB0                        0x00000001U        /*!<Filter bit 0 */\r\n#define  CAN_F0R2_FB1                        0x00000002U        /*!<Filter bit 1 */\r\n#define  CAN_F0R2_FB2                        0x00000004U        /*!<Filter bit 2 */\r\n#define  CAN_F0R2_FB3                        0x00000008U        /*!<Filter bit 3 */\r\n#define  CAN_F0R2_FB4                        0x00000010U        /*!<Filter bit 4 */\r\n#define  CAN_F0R2_FB5                        0x00000020U        /*!<Filter bit 5 */\r\n#define  CAN_F0R2_FB6                        0x00000040U        /*!<Filter bit 6 */\r\n#define  CAN_F0R2_FB7                        0x00000080U        /*!<Filter bit 7 */\r\n#define  CAN_F0R2_FB8                        0x00000100U        /*!<Filter bit 8 */\r\n#define  CAN_F0R2_FB9                        0x00000200U        /*!<Filter bit 9 */\r\n#define  CAN_F0R2_FB10                       0x00000400U        /*!<Filter bit 10 */\r\n#define  CAN_F0R2_FB11                       0x00000800U        /*!<Filter bit 11 */\r\n#define  CAN_F0R2_FB12                       0x00001000U        /*!<Filter bit 12 */\r\n#define  CAN_F0R2_FB13                       0x00002000U        /*!<Filter bit 13 */\r\n#define  CAN_F0R2_FB14                       0x00004000U        /*!<Filter bit 14 */\r\n#define  CAN_F0R2_FB15                       0x00008000U        /*!<Filter bit 15 */\r\n#define  CAN_F0R2_FB16                       0x00010000U        /*!<Filter bit 16 */\r\n#define  CAN_F0R2_FB17                       0x00020000U        /*!<Filter bit 17 */\r\n#define  CAN_F0R2_FB18                       0x00040000U        /*!<Filter bit 18 */\r\n#define  CAN_F0R2_FB19                       0x00080000U        /*!<Filter bit 19 */\r\n#define  CAN_F0R2_FB20                       0x00100000U        /*!<Filter bit 20 */\r\n#define  CAN_F0R2_FB21                       0x00200000U        /*!<Filter bit 21 */\r\n#define  CAN_F0R2_FB22                       0x00400000U        /*!<Filter bit 22 */\r\n#define  CAN_F0R2_FB23                       0x00800000U        /*!<Filter bit 23 */\r\n#define  CAN_F0R2_FB24                       0x01000000U        /*!<Filter bit 24 */\r\n#define  CAN_F0R2_FB25                       0x02000000U        /*!<Filter bit 25 */\r\n#define  CAN_F0R2_FB26                       0x04000000U        /*!<Filter bit 26 */\r\n#define  CAN_F0R2_FB27                       0x08000000U        /*!<Filter bit 27 */\r\n#define  CAN_F0R2_FB28                       0x10000000U        /*!<Filter bit 28 */\r\n#define  CAN_F0R2_FB29                       0x20000000U        /*!<Filter bit 29 */\r\n#define  CAN_F0R2_FB30                       0x40000000U        /*!<Filter bit 30 */\r\n#define  CAN_F0R2_FB31                       0x80000000U        /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F1R2 register  *******************/\r\n#define  CAN_F1R2_FB0                        0x00000001U        /*!<Filter bit 0 */\r\n#define  CAN_F1R2_FB1                        0x00000002U        /*!<Filter bit 1 */\r\n#define  CAN_F1R2_FB2                        0x00000004U        /*!<Filter bit 2 */\r\n#define  CAN_F1R2_FB3                        0x00000008U        /*!<Filter bit 3 */\r\n#define  CAN_F1R2_FB4                        0x00000010U        /*!<Filter bit 4 */\r\n#define  CAN_F1R2_FB5                        0x00000020U        /*!<Filter bit 5 */\r\n#define  CAN_F1R2_FB6                        0x00000040U        /*!<Filter bit 6 */\r\n#define  CAN_F1R2_FB7                        0x00000080U        /*!<Filter bit 7 */\r\n#define  CAN_F1R2_FB8                        0x00000100U        /*!<Filter bit 8 */\r\n#define  CAN_F1R2_FB9                        0x00000200U        /*!<Filter bit 9 */\r\n#define  CAN_F1R2_FB10                       0x00000400U        /*!<Filter bit 10 */\r\n#define  CAN_F1R2_FB11                       0x00000800U        /*!<Filter bit 11 */\r\n#define  CAN_F1R2_FB12                       0x00001000U        /*!<Filter bit 12 */\r\n#define  CAN_F1R2_FB13                       0x00002000U        /*!<Filter bit 13 */\r\n#define  CAN_F1R2_FB14                       0x00004000U        /*!<Filter bit 14 */\r\n#define  CAN_F1R2_FB15                       0x00008000U        /*!<Filter bit 15 */\r\n#define  CAN_F1R2_FB16                       0x00010000U        /*!<Filter bit 16 */\r\n#define  CAN_F1R2_FB17                       0x00020000U        /*!<Filter bit 17 */\r\n#define  CAN_F1R2_FB18                       0x00040000U        /*!<Filter bit 18 */\r\n#define  CAN_F1R2_FB19                       0x00080000U        /*!<Filter bit 19 */\r\n#define  CAN_F1R2_FB20                       0x00100000U        /*!<Filter bit 20 */\r\n#define  CAN_F1R2_FB21                       0x00200000U        /*!<Filter bit 21 */\r\n#define  CAN_F1R2_FB22                       0x00400000U        /*!<Filter bit 22 */\r\n#define  CAN_F1R2_FB23                       0x00800000U        /*!<Filter bit 23 */\r\n#define  CAN_F1R2_FB24                       0x01000000U        /*!<Filter bit 24 */\r\n#define  CAN_F1R2_FB25                       0x02000000U        /*!<Filter bit 25 */\r\n#define  CAN_F1R2_FB26                       0x04000000U        /*!<Filter bit 26 */\r\n#define  CAN_F1R2_FB27                       0x08000000U        /*!<Filter bit 27 */\r\n#define  CAN_F1R2_FB28                       0x10000000U        /*!<Filter bit 28 */\r\n#define  CAN_F1R2_FB29                       0x20000000U        /*!<Filter bit 29 */\r\n#define  CAN_F1R2_FB30                       0x40000000U        /*!<Filter bit 30 */\r\n#define  CAN_F1R2_FB31                       0x80000000U        /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F2R2 register  *******************/\r\n#define  CAN_F2R2_FB0                        0x00000001U        /*!<Filter bit 0 */\r\n#define  CAN_F2R2_FB1                        0x00000002U        /*!<Filter bit 1 */\r\n#define  CAN_F2R2_FB2                        0x00000004U        /*!<Filter bit 2 */\r\n#define  CAN_F2R2_FB3                        0x00000008U        /*!<Filter bit 3 */\r\n#define  CAN_F2R2_FB4                        0x00000010U        /*!<Filter bit 4 */\r\n#define  CAN_F2R2_FB5                        0x00000020U        /*!<Filter bit 5 */\r\n#define  CAN_F2R2_FB6                        0x00000040U        /*!<Filter bit 6 */\r\n#define  CAN_F2R2_FB7                        0x00000080U        /*!<Filter bit 7 */\r\n#define  CAN_F2R2_FB8                        0x00000100U        /*!<Filter bit 8 */\r\n#define  CAN_F2R2_FB9                        0x00000200U        /*!<Filter bit 9 */\r\n#define  CAN_F2R2_FB10                       0x00000400U        /*!<Filter bit 10 */\r\n#define  CAN_F2R2_FB11                       0x00000800U        /*!<Filter bit 11 */\r\n#define  CAN_F2R2_FB12                       0x00001000U        /*!<Filter bit 12 */\r\n#define  CAN_F2R2_FB13                       0x00002000U        /*!<Filter bit 13 */\r\n#define  CAN_F2R2_FB14                       0x00004000U        /*!<Filter bit 14 */\r\n#define  CAN_F2R2_FB15                       0x00008000U        /*!<Filter bit 15 */\r\n#define  CAN_F2R2_FB16                       0x00010000U        /*!<Filter bit 16 */\r\n#define  CAN_F2R2_FB17                       0x00020000U        /*!<Filter bit 17 */\r\n#define  CAN_F2R2_FB18                       0x00040000U        /*!<Filter bit 18 */\r\n#define  CAN_F2R2_FB19                       0x00080000U        /*!<Filter bit 19 */\r\n#define  CAN_F2R2_FB20                       0x00100000U        /*!<Filter bit 20 */\r\n#define  CAN_F2R2_FB21                       0x00200000U        /*!<Filter bit 21 */\r\n#define  CAN_F2R2_FB22                       0x00400000U        /*!<Filter bit 22 */\r\n#define  CAN_F2R2_FB23                       0x00800000U        /*!<Filter bit 23 */\r\n#define  CAN_F2R2_FB24                       0x01000000U        /*!<Filter bit 24 */\r\n#define  CAN_F2R2_FB25                       0x02000000U        /*!<Filter bit 25 */\r\n#define  CAN_F2R2_FB26                       0x04000000U        /*!<Filter bit 26 */\r\n#define  CAN_F2R2_FB27                       0x08000000U        /*!<Filter bit 27 */\r\n#define  CAN_F2R2_FB28                       0x10000000U        /*!<Filter bit 28 */\r\n#define  CAN_F2R2_FB29                       0x20000000U        /*!<Filter bit 29 */\r\n#define  CAN_F2R2_FB30                       0x40000000U        /*!<Filter bit 30 */\r\n#define  CAN_F2R2_FB31                       0x80000000U        /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F3R2 register  *******************/\r\n#define  CAN_F3R2_FB0                        0x00000001U        /*!<Filter bit 0 */\r\n#define  CAN_F3R2_FB1                        0x00000002U        /*!<Filter bit 1 */\r\n#define  CAN_F3R2_FB2                        0x00000004U        /*!<Filter bit 2 */\r\n#define  CAN_F3R2_FB3                        0x00000008U        /*!<Filter bit 3 */\r\n#define  CAN_F3R2_FB4                        0x00000010U        /*!<Filter bit 4 */\r\n#define  CAN_F3R2_FB5                        0x00000020U        /*!<Filter bit 5 */\r\n#define  CAN_F3R2_FB6                        0x00000040U        /*!<Filter bit 6 */\r\n#define  CAN_F3R2_FB7                        0x00000080U        /*!<Filter bit 7 */\r\n#define  CAN_F3R2_FB8                        0x00000100U        /*!<Filter bit 8 */\r\n#define  CAN_F3R2_FB9                        0x00000200U        /*!<Filter bit 9 */\r\n#define  CAN_F3R2_FB10                       0x00000400U        /*!<Filter bit 10 */\r\n#define  CAN_F3R2_FB11                       0x00000800U        /*!<Filter bit 11 */\r\n#define  CAN_F3R2_FB12                       0x00001000U        /*!<Filter bit 12 */\r\n#define  CAN_F3R2_FB13                       0x00002000U        /*!<Filter bit 13 */\r\n#define  CAN_F3R2_FB14                       0x00004000U        /*!<Filter bit 14 */\r\n#define  CAN_F3R2_FB15                       0x00008000U        /*!<Filter bit 15 */\r\n#define  CAN_F3R2_FB16                       0x00010000U        /*!<Filter bit 16 */\r\n#define  CAN_F3R2_FB17                       0x00020000U        /*!<Filter bit 17 */\r\n#define  CAN_F3R2_FB18                       0x00040000U        /*!<Filter bit 18 */\r\n#define  CAN_F3R2_FB19                       0x00080000U        /*!<Filter bit 19 */\r\n#define  CAN_F3R2_FB20                       0x00100000U        /*!<Filter bit 20 */\r\n#define  CAN_F3R2_FB21                       0x00200000U        /*!<Filter bit 21 */\r\n#define  CAN_F3R2_FB22                       0x00400000U        /*!<Filter bit 22 */\r\n#define  CAN_F3R2_FB23                       0x00800000U        /*!<Filter bit 23 */\r\n#define  CAN_F3R2_FB24                       0x01000000U        /*!<Filter bit 24 */\r\n#define  CAN_F3R2_FB25                       0x02000000U        /*!<Filter bit 25 */\r\n#define  CAN_F3R2_FB26                       0x04000000U        /*!<Filter bit 26 */\r\n#define  CAN_F3R2_FB27                       0x08000000U        /*!<Filter bit 27 */\r\n#define  CAN_F3R2_FB28                       0x10000000U        /*!<Filter bit 28 */\r\n#define  CAN_F3R2_FB29                       0x20000000U        /*!<Filter bit 29 */\r\n#define  CAN_F3R2_FB30                       0x40000000U        /*!<Filter bit 30 */\r\n#define  CAN_F3R2_FB31                       0x80000000U        /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F4R2 register  *******************/\r\n#define  CAN_F4R2_FB0                        0x00000001U        /*!<Filter bit 0 */\r\n#define  CAN_F4R2_FB1                        0x00000002U        /*!<Filter bit 1 */\r\n#define  CAN_F4R2_FB2                        0x00000004U        /*!<Filter bit 2 */\r\n#define  CAN_F4R2_FB3                        0x00000008U        /*!<Filter bit 3 */\r\n#define  CAN_F4R2_FB4                        0x00000010U        /*!<Filter bit 4 */\r\n#define  CAN_F4R2_FB5                        0x00000020U        /*!<Filter bit 5 */\r\n#define  CAN_F4R2_FB6                        0x00000040U        /*!<Filter bit 6 */\r\n#define  CAN_F4R2_FB7                        0x00000080U        /*!<Filter bit 7 */\r\n#define  CAN_F4R2_FB8                        0x00000100U        /*!<Filter bit 8 */\r\n#define  CAN_F4R2_FB9                        0x00000200U        /*!<Filter bit 9 */\r\n#define  CAN_F4R2_FB10                       0x00000400U        /*!<Filter bit 10 */\r\n#define  CAN_F4R2_FB11                       0x00000800U        /*!<Filter bit 11 */\r\n#define  CAN_F4R2_FB12                       0x00001000U        /*!<Filter bit 12 */\r\n#define  CAN_F4R2_FB13                       0x00002000U        /*!<Filter bit 13 */\r\n#define  CAN_F4R2_FB14                       0x00004000U        /*!<Filter bit 14 */\r\n#define  CAN_F4R2_FB15                       0x00008000U        /*!<Filter bit 15 */\r\n#define  CAN_F4R2_FB16                       0x00010000U        /*!<Filter bit 16 */\r\n#define  CAN_F4R2_FB17                       0x00020000U        /*!<Filter bit 17 */\r\n#define  CAN_F4R2_FB18                       0x00040000U        /*!<Filter bit 18 */\r\n#define  CAN_F4R2_FB19                       0x00080000U        /*!<Filter bit 19 */\r\n#define  CAN_F4R2_FB20                       0x00100000U        /*!<Filter bit 20 */\r\n#define  CAN_F4R2_FB21                       0x00200000U        /*!<Filter bit 21 */\r\n#define  CAN_F4R2_FB22                       0x00400000U        /*!<Filter bit 22 */\r\n#define  CAN_F4R2_FB23                       0x00800000U        /*!<Filter bit 23 */\r\n#define  CAN_F4R2_FB24                       0x01000000U        /*!<Filter bit 24 */\r\n#define  CAN_F4R2_FB25                       0x02000000U        /*!<Filter bit 25 */\r\n#define  CAN_F4R2_FB26                       0x04000000U        /*!<Filter bit 26 */\r\n#define  CAN_F4R2_FB27                       0x08000000U        /*!<Filter bit 27 */\r\n#define  CAN_F4R2_FB28                       0x10000000U        /*!<Filter bit 28 */\r\n#define  CAN_F4R2_FB29                       0x20000000U        /*!<Filter bit 29 */\r\n#define  CAN_F4R2_FB30                       0x40000000U        /*!<Filter bit 30 */\r\n#define  CAN_F4R2_FB31                       0x80000000U        /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F5R2 register  *******************/\r\n#define  CAN_F5R2_FB0                        0x00000001U        /*!<Filter bit 0 */\r\n#define  CAN_F5R2_FB1                        0x00000002U        /*!<Filter bit 1 */\r\n#define  CAN_F5R2_FB2                        0x00000004U        /*!<Filter bit 2 */\r\n#define  CAN_F5R2_FB3                        0x00000008U        /*!<Filter bit 3 */\r\n#define  CAN_F5R2_FB4                        0x00000010U        /*!<Filter bit 4 */\r\n#define  CAN_F5R2_FB5                        0x00000020U        /*!<Filter bit 5 */\r\n#define  CAN_F5R2_FB6                        0x00000040U        /*!<Filter bit 6 */\r\n#define  CAN_F5R2_FB7                        0x00000080U        /*!<Filter bit 7 */\r\n#define  CAN_F5R2_FB8                        0x00000100U        /*!<Filter bit 8 */\r\n#define  CAN_F5R2_FB9                        0x00000200U        /*!<Filter bit 9 */\r\n#define  CAN_F5R2_FB10                       0x00000400U        /*!<Filter bit 10 */\r\n#define  CAN_F5R2_FB11                       0x00000800U        /*!<Filter bit 11 */\r\n#define  CAN_F5R2_FB12                       0x00001000U        /*!<Filter bit 12 */\r\n#define  CAN_F5R2_FB13                       0x00002000U        /*!<Filter bit 13 */\r\n#define  CAN_F5R2_FB14                       0x00004000U        /*!<Filter bit 14 */\r\n#define  CAN_F5R2_FB15                       0x00008000U        /*!<Filter bit 15 */\r\n#define  CAN_F5R2_FB16                       0x00010000U        /*!<Filter bit 16 */\r\n#define  CAN_F5R2_FB17                       0x00020000U        /*!<Filter bit 17 */\r\n#define  CAN_F5R2_FB18                       0x00040000U        /*!<Filter bit 18 */\r\n#define  CAN_F5R2_FB19                       0x00080000U        /*!<Filter bit 19 */\r\n#define  CAN_F5R2_FB20                       0x00100000U        /*!<Filter bit 20 */\r\n#define  CAN_F5R2_FB21                       0x00200000U        /*!<Filter bit 21 */\r\n#define  CAN_F5R2_FB22                       0x00400000U        /*!<Filter bit 22 */\r\n#define  CAN_F5R2_FB23                       0x00800000U        /*!<Filter bit 23 */\r\n#define  CAN_F5R2_FB24                       0x01000000U        /*!<Filter bit 24 */\r\n#define  CAN_F5R2_FB25                       0x02000000U        /*!<Filter bit 25 */\r\n#define  CAN_F5R2_FB26                       0x04000000U        /*!<Filter bit 26 */\r\n#define  CAN_F5R2_FB27                       0x08000000U        /*!<Filter bit 27 */\r\n#define  CAN_F5R2_FB28                       0x10000000U        /*!<Filter bit 28 */\r\n#define  CAN_F5R2_FB29                       0x20000000U        /*!<Filter bit 29 */\r\n#define  CAN_F5R2_FB30                       0x40000000U        /*!<Filter bit 30 */\r\n#define  CAN_F5R2_FB31                       0x80000000U        /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F6R2 register  *******************/\r\n#define  CAN_F6R2_FB0                        0x00000001U        /*!<Filter bit 0 */\r\n#define  CAN_F6R2_FB1                        0x00000002U        /*!<Filter bit 1 */\r\n#define  CAN_F6R2_FB2                        0x00000004U        /*!<Filter bit 2 */\r\n#define  CAN_F6R2_FB3                        0x00000008U        /*!<Filter bit 3 */\r\n#define  CAN_F6R2_FB4                        0x00000010U        /*!<Filter bit 4 */\r\n#define  CAN_F6R2_FB5                        0x00000020U        /*!<Filter bit 5 */\r\n#define  CAN_F6R2_FB6                        0x00000040U        /*!<Filter bit 6 */\r\n#define  CAN_F6R2_FB7                        0x00000080U        /*!<Filter bit 7 */\r\n#define  CAN_F6R2_FB8                        0x00000100U        /*!<Filter bit 8 */\r\n#define  CAN_F6R2_FB9                        0x00000200U        /*!<Filter bit 9 */\r\n#define  CAN_F6R2_FB10                       0x00000400U        /*!<Filter bit 10 */\r\n#define  CAN_F6R2_FB11                       0x00000800U        /*!<Filter bit 11 */\r\n#define  CAN_F6R2_FB12                       0x00001000U        /*!<Filter bit 12 */\r\n#define  CAN_F6R2_FB13                       0x00002000U        /*!<Filter bit 13 */\r\n#define  CAN_F6R2_FB14                       0x00004000U        /*!<Filter bit 14 */\r\n#define  CAN_F6R2_FB15                       0x00008000U        /*!<Filter bit 15 */\r\n#define  CAN_F6R2_FB16                       0x00010000U        /*!<Filter bit 16 */\r\n#define  CAN_F6R2_FB17                       0x00020000U        /*!<Filter bit 17 */\r\n#define  CAN_F6R2_FB18                       0x00040000U        /*!<Filter bit 18 */\r\n#define  CAN_F6R2_FB19                       0x00080000U        /*!<Filter bit 19 */\r\n#define  CAN_F6R2_FB20                       0x00100000U        /*!<Filter bit 20 */\r\n#define  CAN_F6R2_FB21                       0x00200000U        /*!<Filter bit 21 */\r\n#define  CAN_F6R2_FB22                       0x00400000U        /*!<Filter bit 22 */\r\n#define  CAN_F6R2_FB23                       0x00800000U        /*!<Filter bit 23 */\r\n#define  CAN_F6R2_FB24                       0x01000000U        /*!<Filter bit 24 */\r\n#define  CAN_F6R2_FB25                       0x02000000U        /*!<Filter bit 25 */\r\n#define  CAN_F6R2_FB26                       0x04000000U        /*!<Filter bit 26 */\r\n#define  CAN_F6R2_FB27                       0x08000000U        /*!<Filter bit 27 */\r\n#define  CAN_F6R2_FB28                       0x10000000U        /*!<Filter bit 28 */\r\n#define  CAN_F6R2_FB29                       0x20000000U        /*!<Filter bit 29 */\r\n#define  CAN_F6R2_FB30                       0x40000000U        /*!<Filter bit 30 */\r\n#define  CAN_F6R2_FB31                       0x80000000U        /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F7R2 register  *******************/\r\n#define  CAN_F7R2_FB0                        0x00000001U        /*!<Filter bit 0 */\r\n#define  CAN_F7R2_FB1                        0x00000002U        /*!<Filter bit 1 */\r\n#define  CAN_F7R2_FB2                        0x00000004U        /*!<Filter bit 2 */\r\n#define  CAN_F7R2_FB3                        0x00000008U        /*!<Filter bit 3 */\r\n#define  CAN_F7R2_FB4                        0x00000010U        /*!<Filter bit 4 */\r\n#define  CAN_F7R2_FB5                        0x00000020U        /*!<Filter bit 5 */\r\n#define  CAN_F7R2_FB6                        0x00000040U        /*!<Filter bit 6 */\r\n#define  CAN_F7R2_FB7                        0x00000080U        /*!<Filter bit 7 */\r\n#define  CAN_F7R2_FB8                        0x00000100U        /*!<Filter bit 8 */\r\n#define  CAN_F7R2_FB9                        0x00000200U        /*!<Filter bit 9 */\r\n#define  CAN_F7R2_FB10                       0x00000400U        /*!<Filter bit 10 */\r\n#define  CAN_F7R2_FB11                       0x00000800U        /*!<Filter bit 11 */\r\n#define  CAN_F7R2_FB12                       0x00001000U        /*!<Filter bit 12 */\r\n#define  CAN_F7R2_FB13                       0x00002000U        /*!<Filter bit 13 */\r\n#define  CAN_F7R2_FB14                       0x00004000U        /*!<Filter bit 14 */\r\n#define  CAN_F7R2_FB15                       0x00008000U        /*!<Filter bit 15 */\r\n#define  CAN_F7R2_FB16                       0x00010000U        /*!<Filter bit 16 */\r\n#define  CAN_F7R2_FB17                       0x00020000U        /*!<Filter bit 17 */\r\n#define  CAN_F7R2_FB18                       0x00040000U        /*!<Filter bit 18 */\r\n#define  CAN_F7R2_FB19                       0x00080000U        /*!<Filter bit 19 */\r\n#define  CAN_F7R2_FB20                       0x00100000U        /*!<Filter bit 20 */\r\n#define  CAN_F7R2_FB21                       0x00200000U        /*!<Filter bit 21 */\r\n#define  CAN_F7R2_FB22                       0x00400000U        /*!<Filter bit 22 */\r\n#define  CAN_F7R2_FB23                       0x00800000U        /*!<Filter bit 23 */\r\n#define  CAN_F7R2_FB24                       0x01000000U        /*!<Filter bit 24 */\r\n#define  CAN_F7R2_FB25                       0x02000000U        /*!<Filter bit 25 */\r\n#define  CAN_F7R2_FB26                       0x04000000U        /*!<Filter bit 26 */\r\n#define  CAN_F7R2_FB27                       0x08000000U        /*!<Filter bit 27 */\r\n#define  CAN_F7R2_FB28                       0x10000000U        /*!<Filter bit 28 */\r\n#define  CAN_F7R2_FB29                       0x20000000U        /*!<Filter bit 29 */\r\n#define  CAN_F7R2_FB30                       0x40000000U        /*!<Filter bit 30 */\r\n#define  CAN_F7R2_FB31                       0x80000000U        /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F8R2 register  *******************/\r\n#define  CAN_F8R2_FB0                        0x00000001U        /*!<Filter bit 0 */\r\n#define  CAN_F8R2_FB1                        0x00000002U        /*!<Filter bit 1 */\r\n#define  CAN_F8R2_FB2                        0x00000004U        /*!<Filter bit 2 */\r\n#define  CAN_F8R2_FB3                        0x00000008U        /*!<Filter bit 3 */\r\n#define  CAN_F8R2_FB4                        0x00000010U        /*!<Filter bit 4 */\r\n#define  CAN_F8R2_FB5                        0x00000020U        /*!<Filter bit 5 */\r\n#define  CAN_F8R2_FB6                        0x00000040U        /*!<Filter bit 6 */\r\n#define  CAN_F8R2_FB7                        0x00000080U        /*!<Filter bit 7 */\r\n#define  CAN_F8R2_FB8                        0x00000100U        /*!<Filter bit 8 */\r\n#define  CAN_F8R2_FB9                        0x00000200U        /*!<Filter bit 9 */\r\n#define  CAN_F8R2_FB10                       0x00000400U        /*!<Filter bit 10 */\r\n#define  CAN_F8R2_FB11                       0x00000800U        /*!<Filter bit 11 */\r\n#define  CAN_F8R2_FB12                       0x00001000U        /*!<Filter bit 12 */\r\n#define  CAN_F8R2_FB13                       0x00002000U        /*!<Filter bit 13 */\r\n#define  CAN_F8R2_FB14                       0x00004000U        /*!<Filter bit 14 */\r\n#define  CAN_F8R2_FB15                       0x00008000U        /*!<Filter bit 15 */\r\n#define  CAN_F8R2_FB16                       0x00010000U        /*!<Filter bit 16 */\r\n#define  CAN_F8R2_FB17                       0x00020000U        /*!<Filter bit 17 */\r\n#define  CAN_F8R2_FB18                       0x00040000U        /*!<Filter bit 18 */\r\n#define  CAN_F8R2_FB19                       0x00080000U        /*!<Filter bit 19 */\r\n#define  CAN_F8R2_FB20                       0x00100000U        /*!<Filter bit 20 */\r\n#define  CAN_F8R2_FB21                       0x00200000U        /*!<Filter bit 21 */\r\n#define  CAN_F8R2_FB22                       0x00400000U        /*!<Filter bit 22 */\r\n#define  CAN_F8R2_FB23                       0x00800000U        /*!<Filter bit 23 */\r\n#define  CAN_F8R2_FB24                       0x01000000U        /*!<Filter bit 24 */\r\n#define  CAN_F8R2_FB25                       0x02000000U        /*!<Filter bit 25 */\r\n#define  CAN_F8R2_FB26                       0x04000000U        /*!<Filter bit 26 */\r\n#define  CAN_F8R2_FB27                       0x08000000U        /*!<Filter bit 27 */\r\n#define  CAN_F8R2_FB28                       0x10000000U        /*!<Filter bit 28 */\r\n#define  CAN_F8R2_FB29                       0x20000000U        /*!<Filter bit 29 */\r\n#define  CAN_F8R2_FB30                       0x40000000U        /*!<Filter bit 30 */\r\n#define  CAN_F8R2_FB31                       0x80000000U        /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F9R2 register  *******************/\r\n#define  CAN_F9R2_FB0                        0x00000001U        /*!<Filter bit 0 */\r\n#define  CAN_F9R2_FB1                        0x00000002U        /*!<Filter bit 1 */\r\n#define  CAN_F9R2_FB2                        0x00000004U        /*!<Filter bit 2 */\r\n#define  CAN_F9R2_FB3                        0x00000008U        /*!<Filter bit 3 */\r\n#define  CAN_F9R2_FB4                        0x00000010U        /*!<Filter bit 4 */\r\n#define  CAN_F9R2_FB5                        0x00000020U        /*!<Filter bit 5 */\r\n#define  CAN_F9R2_FB6                        0x00000040U        /*!<Filter bit 6 */\r\n#define  CAN_F9R2_FB7                        0x00000080U        /*!<Filter bit 7 */\r\n#define  CAN_F9R2_FB8                        0x00000100U        /*!<Filter bit 8 */\r\n#define  CAN_F9R2_FB9                        0x00000200U        /*!<Filter bit 9 */\r\n#define  CAN_F9R2_FB10                       0x00000400U        /*!<Filter bit 10 */\r\n#define  CAN_F9R2_FB11                       0x00000800U        /*!<Filter bit 11 */\r\n#define  CAN_F9R2_FB12                       0x00001000U        /*!<Filter bit 12 */\r\n#define  CAN_F9R2_FB13                       0x00002000U        /*!<Filter bit 13 */\r\n#define  CAN_F9R2_FB14                       0x00004000U        /*!<Filter bit 14 */\r\n#define  CAN_F9R2_FB15                       0x00008000U        /*!<Filter bit 15 */\r\n#define  CAN_F9R2_FB16                       0x00010000U        /*!<Filter bit 16 */\r\n#define  CAN_F9R2_FB17                       0x00020000U        /*!<Filter bit 17 */\r\n#define  CAN_F9R2_FB18                       0x00040000U        /*!<Filter bit 18 */\r\n#define  CAN_F9R2_FB19                       0x00080000U        /*!<Filter bit 19 */\r\n#define  CAN_F9R2_FB20                       0x00100000U        /*!<Filter bit 20 */\r\n#define  CAN_F9R2_FB21                       0x00200000U        /*!<Filter bit 21 */\r\n#define  CAN_F9R2_FB22                       0x00400000U        /*!<Filter bit 22 */\r\n#define  CAN_F9R2_FB23                       0x00800000U        /*!<Filter bit 23 */\r\n#define  CAN_F9R2_FB24                       0x01000000U        /*!<Filter bit 24 */\r\n#define  CAN_F9R2_FB25                       0x02000000U        /*!<Filter bit 25 */\r\n#define  CAN_F9R2_FB26                       0x04000000U        /*!<Filter bit 26 */\r\n#define  CAN_F9R2_FB27                       0x08000000U        /*!<Filter bit 27 */\r\n#define  CAN_F9R2_FB28                       0x10000000U        /*!<Filter bit 28 */\r\n#define  CAN_F9R2_FB29                       0x20000000U        /*!<Filter bit 29 */\r\n#define  CAN_F9R2_FB30                       0x40000000U        /*!<Filter bit 30 */\r\n#define  CAN_F9R2_FB31                       0x80000000U        /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F10R2 register  ******************/\r\n#define  CAN_F10R2_FB0                       0x00000001U        /*!<Filter bit 0 */\r\n#define  CAN_F10R2_FB1                       0x00000002U        /*!<Filter bit 1 */\r\n#define  CAN_F10R2_FB2                       0x00000004U        /*!<Filter bit 2 */\r\n#define  CAN_F10R2_FB3                       0x00000008U        /*!<Filter bit 3 */\r\n#define  CAN_F10R2_FB4                       0x00000010U        /*!<Filter bit 4 */\r\n#define  CAN_F10R2_FB5                       0x00000020U        /*!<Filter bit 5 */\r\n#define  CAN_F10R2_FB6                       0x00000040U        /*!<Filter bit 6 */\r\n#define  CAN_F10R2_FB7                       0x00000080U        /*!<Filter bit 7 */\r\n#define  CAN_F10R2_FB8                       0x00000100U        /*!<Filter bit 8 */\r\n#define  CAN_F10R2_FB9                       0x00000200U        /*!<Filter bit 9 */\r\n#define  CAN_F10R2_FB10                      0x00000400U        /*!<Filter bit 10 */\r\n#define  CAN_F10R2_FB11                      0x00000800U        /*!<Filter bit 11 */\r\n#define  CAN_F10R2_FB12                      0x00001000U        /*!<Filter bit 12 */\r\n#define  CAN_F10R2_FB13                      0x00002000U        /*!<Filter bit 13 */\r\n#define  CAN_F10R2_FB14                      0x00004000U        /*!<Filter bit 14 */\r\n#define  CAN_F10R2_FB15                      0x00008000U        /*!<Filter bit 15 */\r\n#define  CAN_F10R2_FB16                      0x00010000U        /*!<Filter bit 16 */\r\n#define  CAN_F10R2_FB17                      0x00020000U        /*!<Filter bit 17 */\r\n#define  CAN_F10R2_FB18                      0x00040000U        /*!<Filter bit 18 */\r\n#define  CAN_F10R2_FB19                      0x00080000U        /*!<Filter bit 19 */\r\n#define  CAN_F10R2_FB20                      0x00100000U        /*!<Filter bit 20 */\r\n#define  CAN_F10R2_FB21                      0x00200000U        /*!<Filter bit 21 */\r\n#define  CAN_F10R2_FB22                      0x00400000U        /*!<Filter bit 22 */\r\n#define  CAN_F10R2_FB23                      0x00800000U        /*!<Filter bit 23 */\r\n#define  CAN_F10R2_FB24                      0x01000000U        /*!<Filter bit 24 */\r\n#define  CAN_F10R2_FB25                      0x02000000U        /*!<Filter bit 25 */\r\n#define  CAN_F10R2_FB26                      0x04000000U        /*!<Filter bit 26 */\r\n#define  CAN_F10R2_FB27                      0x08000000U        /*!<Filter bit 27 */\r\n#define  CAN_F10R2_FB28                      0x10000000U        /*!<Filter bit 28 */\r\n#define  CAN_F10R2_FB29                      0x20000000U        /*!<Filter bit 29 */\r\n#define  CAN_F10R2_FB30                      0x40000000U        /*!<Filter bit 30 */\r\n#define  CAN_F10R2_FB31                      0x80000000U        /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F11R2 register  ******************/\r\n#define  CAN_F11R2_FB0                       0x00000001U        /*!<Filter bit 0 */\r\n#define  CAN_F11R2_FB1                       0x00000002U        /*!<Filter bit 1 */\r\n#define  CAN_F11R2_FB2                       0x00000004U        /*!<Filter bit 2 */\r\n#define  CAN_F11R2_FB3                       0x00000008U        /*!<Filter bit 3 */\r\n#define  CAN_F11R2_FB4                       0x00000010U        /*!<Filter bit 4 */\r\n#define  CAN_F11R2_FB5                       0x00000020U        /*!<Filter bit 5 */\r\n#define  CAN_F11R2_FB6                       0x00000040U        /*!<Filter bit 6 */\r\n#define  CAN_F11R2_FB7                       0x00000080U        /*!<Filter bit 7 */\r\n#define  CAN_F11R2_FB8                       0x00000100U        /*!<Filter bit 8 */\r\n#define  CAN_F11R2_FB9                       0x00000200U        /*!<Filter bit 9 */\r\n#define  CAN_F11R2_FB10                      0x00000400U        /*!<Filter bit 10 */\r\n#define  CAN_F11R2_FB11                      0x00000800U        /*!<Filter bit 11 */\r\n#define  CAN_F11R2_FB12                      0x00001000U        /*!<Filter bit 12 */\r\n#define  CAN_F11R2_FB13                      0x00002000U        /*!<Filter bit 13 */\r\n#define  CAN_F11R2_FB14                      0x00004000U        /*!<Filter bit 14 */\r\n#define  CAN_F11R2_FB15                      0x00008000U        /*!<Filter bit 15 */\r\n#define  CAN_F11R2_FB16                      0x00010000U        /*!<Filter bit 16 */\r\n#define  CAN_F11R2_FB17                      0x00020000U        /*!<Filter bit 17 */\r\n#define  CAN_F11R2_FB18                      0x00040000U        /*!<Filter bit 18 */\r\n#define  CAN_F11R2_FB19                      0x00080000U        /*!<Filter bit 19 */\r\n#define  CAN_F11R2_FB20                      0x00100000U        /*!<Filter bit 20 */\r\n#define  CAN_F11R2_FB21                      0x00200000U        /*!<Filter bit 21 */\r\n#define  CAN_F11R2_FB22                      0x00400000U        /*!<Filter bit 22 */\r\n#define  CAN_F11R2_FB23                      0x00800000U        /*!<Filter bit 23 */\r\n#define  CAN_F11R2_FB24                      0x01000000U        /*!<Filter bit 24 */\r\n#define  CAN_F11R2_FB25                      0x02000000U        /*!<Filter bit 25 */\r\n#define  CAN_F11R2_FB26                      0x04000000U        /*!<Filter bit 26 */\r\n#define  CAN_F11R2_FB27                      0x08000000U        /*!<Filter bit 27 */\r\n#define  CAN_F11R2_FB28                      0x10000000U        /*!<Filter bit 28 */\r\n#define  CAN_F11R2_FB29                      0x20000000U        /*!<Filter bit 29 */\r\n#define  CAN_F11R2_FB30                      0x40000000U        /*!<Filter bit 30 */\r\n#define  CAN_F11R2_FB31                      0x80000000U        /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F12R2 register  ******************/\r\n#define  CAN_F12R2_FB0                       0x00000001U        /*!<Filter bit 0 */\r\n#define  CAN_F12R2_FB1                       0x00000002U        /*!<Filter bit 1 */\r\n#define  CAN_F12R2_FB2                       0x00000004U        /*!<Filter bit 2 */\r\n#define  CAN_F12R2_FB3                       0x00000008U        /*!<Filter bit 3 */\r\n#define  CAN_F12R2_FB4                       0x00000010U        /*!<Filter bit 4 */\r\n#define  CAN_F12R2_FB5                       0x00000020U        /*!<Filter bit 5 */\r\n#define  CAN_F12R2_FB6                       0x00000040U        /*!<Filter bit 6 */\r\n#define  CAN_F12R2_FB7                       0x00000080U        /*!<Filter bit 7 */\r\n#define  CAN_F12R2_FB8                       0x00000100U        /*!<Filter bit 8 */\r\n#define  CAN_F12R2_FB9                       0x00000200U        /*!<Filter bit 9 */\r\n#define  CAN_F12R2_FB10                      0x00000400U        /*!<Filter bit 10 */\r\n#define  CAN_F12R2_FB11                      0x00000800U        /*!<Filter bit 11 */\r\n#define  CAN_F12R2_FB12                      0x00001000U        /*!<Filter bit 12 */\r\n#define  CAN_F12R2_FB13                      0x00002000U        /*!<Filter bit 13 */\r\n#define  CAN_F12R2_FB14                      0x00004000U        /*!<Filter bit 14 */\r\n#define  CAN_F12R2_FB15                      0x00008000U        /*!<Filter bit 15 */\r\n#define  CAN_F12R2_FB16                      0x00010000U        /*!<Filter bit 16 */\r\n#define  CAN_F12R2_FB17                      0x00020000U        /*!<Filter bit 17 */\r\n#define  CAN_F12R2_FB18                      0x00040000U        /*!<Filter bit 18 */\r\n#define  CAN_F12R2_FB19                      0x00080000U        /*!<Filter bit 19 */\r\n#define  CAN_F12R2_FB20                      0x00100000U        /*!<Filter bit 20 */\r\n#define  CAN_F12R2_FB21                      0x00200000U        /*!<Filter bit 21 */\r\n#define  CAN_F12R2_FB22                      0x00400000U        /*!<Filter bit 22 */\r\n#define  CAN_F12R2_FB23                      0x00800000U        /*!<Filter bit 23 */\r\n#define  CAN_F12R2_FB24                      0x01000000U        /*!<Filter bit 24 */\r\n#define  CAN_F12R2_FB25                      0x02000000U        /*!<Filter bit 25 */\r\n#define  CAN_F12R2_FB26                      0x04000000U        /*!<Filter bit 26 */\r\n#define  CAN_F12R2_FB27                      0x08000000U        /*!<Filter bit 27 */\r\n#define  CAN_F12R2_FB28                      0x10000000U        /*!<Filter bit 28 */\r\n#define  CAN_F12R2_FB29                      0x20000000U        /*!<Filter bit 29 */\r\n#define  CAN_F12R2_FB30                      0x40000000U        /*!<Filter bit 30 */\r\n#define  CAN_F12R2_FB31                      0x80000000U        /*!<Filter bit 31 */\r\n\r\n/*******************  Bit definition for CAN_F13R2 register  ******************/\r\n#define  CAN_F13R2_FB0                       0x00000001U        /*!<Filter bit 0 */\r\n#define  CAN_F13R2_FB1                       0x00000002U        /*!<Filter bit 1 */\r\n#define  CAN_F13R2_FB2                       0x00000004U        /*!<Filter bit 2 */\r\n#define  CAN_F13R2_FB3                       0x00000008U        /*!<Filter bit 3 */\r\n#define  CAN_F13R2_FB4                       0x00000010U        /*!<Filter bit 4 */\r\n#define  CAN_F13R2_FB5                       0x00000020U        /*!<Filter bit 5 */\r\n#define  CAN_F13R2_FB6                       0x00000040U        /*!<Filter bit 6 */\r\n#define  CAN_F13R2_FB7                       0x00000080U        /*!<Filter bit 7 */\r\n#define  CAN_F13R2_FB8                       0x00000100U        /*!<Filter bit 8 */\r\n#define  CAN_F13R2_FB9                       0x00000200U        /*!<Filter bit 9 */\r\n#define  CAN_F13R2_FB10                      0x00000400U        /*!<Filter bit 10 */\r\n#define  CAN_F13R2_FB11                      0x00000800U        /*!<Filter bit 11 */\r\n#define  CAN_F13R2_FB12                      0x00001000U        /*!<Filter bit 12 */\r\n#define  CAN_F13R2_FB13                      0x00002000U        /*!<Filter bit 13 */\r\n#define  CAN_F13R2_FB14                      0x00004000U        /*!<Filter bit 14 */\r\n#define  CAN_F13R2_FB15                      0x00008000U        /*!<Filter bit 15 */\r\n#define  CAN_F13R2_FB16                      0x00010000U        /*!<Filter bit 16 */\r\n#define  CAN_F13R2_FB17                      0x00020000U        /*!<Filter bit 17 */\r\n#define  CAN_F13R2_FB18                      0x00040000U        /*!<Filter bit 18 */\r\n#define  CAN_F13R2_FB19                      0x00080000U        /*!<Filter bit 19 */\r\n#define  CAN_F13R2_FB20                      0x00100000U        /*!<Filter bit 20 */\r\n#define  CAN_F13R2_FB21                      0x00200000U        /*!<Filter bit 21 */\r\n#define  CAN_F13R2_FB22                      0x00400000U        /*!<Filter bit 22 */\r\n#define  CAN_F13R2_FB23                      0x00800000U        /*!<Filter bit 23 */\r\n#define  CAN_F13R2_FB24                      0x01000000U        /*!<Filter bit 24 */\r\n#define  CAN_F13R2_FB25                      0x02000000U        /*!<Filter bit 25 */\r\n#define  CAN_F13R2_FB26                      0x04000000U        /*!<Filter bit 26 */\r\n#define  CAN_F13R2_FB27                      0x08000000U        /*!<Filter bit 27 */\r\n#define  CAN_F13R2_FB28                      0x10000000U        /*!<Filter bit 28 */\r\n#define  CAN_F13R2_FB29                      0x20000000U        /*!<Filter bit 29 */\r\n#define  CAN_F13R2_FB30                      0x40000000U        /*!<Filter bit 30 */\r\n#define  CAN_F13R2_FB31                      0x80000000U        /*!<Filter bit 31 */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                 HDMI-CEC (CEC)                             */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n\r\n/*******************  Bit definition for CEC_CR register  *********************/\r\n#define  CEC_CR_CECEN                        0x00000001U       /*!< CEC Enable                         */\r\n#define  CEC_CR_TXSOM                        0x00000002U       /*!< CEC Tx Start Of Message            */\r\n#define  CEC_CR_TXEOM                        0x00000004U       /*!< CEC Tx End Of Message              */\r\n\r\n/*******************  Bit definition for CEC_CFGR register  *******************/\r\n#define  CEC_CFGR_SFT                        0x00000007U       /*!< CEC Signal Free Time               */\r\n#define  CEC_CFGR_RXTOL                      0x00000008U       /*!< CEC Tolerance                      */\r\n#define  CEC_CFGR_BRESTP                     0x00000010U       /*!< CEC Rx Stop                        */\r\n#define  CEC_CFGR_BREGEN                     0x00000020U       /*!< CEC Bit Rising Error generation    */\r\n#define  CEC_CFGR_LBPEGEN                    0x00000040U       /*!< CEC Long Period Error generation   */\r\n#define  CEC_CFGR_BRDNOGEN                   0x00000080U       /*!< CEC Broadcast no Error generation  */\r\n#define  CEC_CFGR_SFTOPT                     0x00000100U       /*!< CEC Signal Free Time optional      */\r\n#define  CEC_CFGR_OAR                        0x7FFF0000U       /*!< CEC Own Address                    */\r\n#define  CEC_CFGR_LSTN                       0x80000000U       /*!< CEC Listen mode                    */\r\n\r\n/*******************  Bit definition for CEC_TXDR register  *******************/\r\n#define  CEC_TXDR_TXD                        0x000000FFU       /*!< CEC Tx Data                        */\r\n\r\n/*******************  Bit definition for CEC_RXDR register  *******************/\r\n#define  CEC_TXDR_RXD                        0x000000FFU       /*!< CEC Rx Data                        */\r\n\r\n/*******************  Bit definition for CEC_ISR register  ********************/\r\n#define  CEC_ISR_RXBR                        0x00000001U       /*!< CEC Rx-Byte Received                   */\r\n#define  CEC_ISR_RXEND                       0x00000002U       /*!< CEC End Of Reception                   */\r\n#define  CEC_ISR_RXOVR                       0x00000004U       /*!< CEC Rx-Overrun                         */\r\n#define  CEC_ISR_BRE                         0x00000008U       /*!< CEC Rx Bit Rising Error                */\r\n#define  CEC_ISR_SBPE                        0x00000010U       /*!< CEC Rx Short Bit period Error          */\r\n#define  CEC_ISR_LBPE                        0x00000020U       /*!< CEC Rx Long Bit period Error           */\r\n#define  CEC_ISR_RXACKE                      0x00000040U       /*!< CEC Rx Missing Acknowledge             */\r\n#define  CEC_ISR_ARBLST                      0x00000080U       /*!< CEC Arbitration Lost                   */\r\n#define  CEC_ISR_TXBR                        0x00000100U       /*!< CEC Tx Byte Request                    */\r\n#define  CEC_ISR_TXEND                       0x00000200U       /*!< CEC End of Transmission                */\r\n#define  CEC_ISR_TXUDR                       0x00000400U       /*!< CEC Tx-Buffer Underrun                 */\r\n#define  CEC_ISR_TXERR                       0x00000800U       /*!< CEC Tx-Error                           */\r\n#define  CEC_ISR_TXACKE                      0x00001000U       /*!< CEC Tx Missing Acknowledge             */\r\n\r\n/*******************  Bit definition for CEC_IER register  ********************/\r\n#define  CEC_IER_RXBRIE                      0x00000001U       /*!< CEC Rx-Byte Received IT Enable         */\r\n#define  CEC_IER_RXENDIE                     0x00000002U       /*!< CEC End Of Reception IT Enable         */\r\n#define  CEC_IER_RXOVRIE                     0x00000004U       /*!< CEC Rx-Overrun IT Enable               */\r\n#define  CEC_IER_BREIE                       0x00000008U       /*!< CEC Rx Bit Rising Error IT Enable      */\r\n#define  CEC_IER_SBPEIE                      0x00000010U       /*!< CEC Rx Short Bit period Error IT Enable*/\r\n#define  CEC_IER_LBPEIE                      0x00000020U       /*!< CEC Rx Long Bit period Error IT Enable */\r\n#define  CEC_IER_RXACKEIE                    0x00000040U       /*!< CEC Rx Missing Acknowledge IT Enable   */\r\n#define  CEC_IER_ARBLSTIE                    0x00000080U       /*!< CEC Arbitration Lost IT Enable         */\r\n#define  CEC_IER_TXBRIE                      0x00000100U       /*!< CEC Tx Byte Request  IT Enable         */\r\n#define  CEC_IER_TXENDIE                     0x00000200U       /*!< CEC End of Transmission IT Enable      */\r\n#define  CEC_IER_TXUDRIE                     0x00000400U       /*!< CEC Tx-Buffer Underrun IT Enable       */\r\n#define  CEC_IER_TXERRIE                     0x00000800U       /*!< CEC Tx-Error IT Enable                 */\r\n#define  CEC_IER_TXACKEIE                    0x00001000U       /*!< CEC Tx Missing Acknowledge IT Enable   */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                          CRC calculation unit                              */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************  Bit definition for CRC_DR register  *********************/\r\n#define  CRC_DR_DR                           0xFFFFFFFFU     /*!< Data register bits */\r\n\r\n/*******************  Bit definition for CRC_IDR register  ********************/\r\n#define  CRC_IDR_IDR                         0x000000FFU     /*!< General-purpose 8-bit data register bits */\r\n\r\n/********************  Bit definition for CRC_CR register  ********************/\r\n#define  CRC_CR_RESET                        0x00000001U     /*!< RESET the CRC computation unit bit */\r\n#define  CRC_CR_POLYSIZE                     0x00000018U     /*!< Polynomial size bits               */\r\n#define  CRC_CR_POLYSIZE_0                   0x00000008U     /*!< Polynomial size bit 0              */\r\n#define  CRC_CR_POLYSIZE_1                   0x00000010U     /*!< Polynomial size bit 1              */\r\n#define  CRC_CR_REV_IN                       0x00000060U     /*!< REV_IN Reverse Input Data bits     */\r\n#define  CRC_CR_REV_IN_0                     0x00000020U     /*!< Bit 0 */\r\n#define  CRC_CR_REV_IN_1                     0x00000040U     /*!< Bit 1 */\r\n#define  CRC_CR_REV_OUT                      0x00000080U     /*!< REV_OUT Reverse Output Data bits   */\r\n\r\n/*******************  Bit definition for CRC_INIT register  *******************/\r\n#define  CRC_INIT_INIT                       0xFFFFFFFFU     /*!< Initial CRC value bits         */\r\n\r\n/*******************  Bit definition for CRC_POL register  ********************/\r\n#define  CRC_POL_POL                         0xFFFFFFFFU     /*!< Coefficients of the polynomial */\r\n\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                      Digital to Analog Converter                           */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bit definition for DAC_CR register  ********************/\r\n#define  DAC_CR_EN1                          0x00000001U        /*!<DAC channel1 enable                         */\r\n#define  DAC_CR_BOFF1                        0x00000002U        /*!<DAC channel1 output buffer disable          */\r\n#define  DAC_CR_TEN1                         0x00000004U        /*!<DAC channel1 Trigger enable                 */\r\n#define  DAC_CR_TSEL1                        0x00000038U        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\r\n#define  DAC_CR_TSEL1_0                      0x00000008U        /*!<Bit 0 */\r\n#define  DAC_CR_TSEL1_1                      0x00000010U        /*!<Bit 1 */\r\n#define  DAC_CR_TSEL1_2                      0x00000020U        /*!<Bit 2 */\r\n#define  DAC_CR_WAVE1                        0x000000C0U        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enablEU) */\r\n#define  DAC_CR_WAVE1_0                      0x00000040U        /*!<Bit 0 */\r\n#define  DAC_CR_WAVE1_1                      0x00000080U        /*!<Bit 1 */\r\n#define  DAC_CR_MAMP1                        0x00000F00U        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\r\n#define  DAC_CR_MAMP1_0                      0x00000100U        /*!<Bit 0 */\r\n#define  DAC_CR_MAMP1_1                      0x00000200U        /*!<Bit 1 */\r\n#define  DAC_CR_MAMP1_2                      0x00000400U        /*!<Bit 2 */\r\n#define  DAC_CR_MAMP1_3                      0x00000800U        /*!<Bit 3 */\r\n#define  DAC_CR_DMAEN1                       0x00001000U        /*!<DAC channel1 DMA enable                     */\r\n#define  DAC_CR_DMAUDRIE1                    0x00002000U        /*!<DAC channel1 DMA underrun interrupt enable  */\r\n#define  DAC_CR_EN2                          0x00010000U        /*!<DAC channel2 enable                         */\r\n#define  DAC_CR_BOFF2                        0x00020000U        /*!<DAC channel2 output buffer disable          */\r\n#define  DAC_CR_TEN2                         0x00040000U        /*!<DAC channel2 Trigger enable                 */\r\n#define  DAC_CR_TSEL2                        0x00380000U        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */\r\n#define  DAC_CR_TSEL2_0                      0x00080000U        /*!<Bit 0 */\r\n#define  DAC_CR_TSEL2_1                      0x00100000U        /*!<Bit 1 */\r\n#define  DAC_CR_TSEL2_2                      0x00200000U        /*!<Bit 2 */\r\n#define  DAC_CR_WAVE2                        0x00C00000U        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\r\n#define  DAC_CR_WAVE2_0                      0x00400000U        /*!<Bit 0 */\r\n#define  DAC_CR_WAVE2_1                      0x00800000U        /*!<Bit 1 */\r\n#define  DAC_CR_MAMP2                        0x0F000000U        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\r\n#define  DAC_CR_MAMP2_0                      0x01000000U        /*!<Bit 0 */\r\n#define  DAC_CR_MAMP2_1                      0x02000000U        /*!<Bit 1 */\r\n#define  DAC_CR_MAMP2_2                      0x04000000U        /*!<Bit 2 */\r\n#define  DAC_CR_MAMP2_3                      0x08000000U        /*!<Bit 3 */\r\n#define  DAC_CR_DMAEN2                       0x10000000U        /*!<DAC channel2 DMA enable                    */\r\n#define  DAC_CR_DMAUDRIE2                    0x20000000U        /*!<DAC channel2 DMA underrun interrupt enable */\r\n\r\n/*****************  Bit definition for DAC_SWTRIGR register  ******************/\r\n#define  DAC_SWTRIGR_SWTRIG1                 0x01U               /*!<DAC channel1 software trigger */\r\n#define  DAC_SWTRIGR_SWTRIG2                 0x02U               /*!<DAC channel2 software trigger */\r\n\r\n/*****************  Bit definition for DAC_DHR12R1 register  ******************/\r\n#define  DAC_DHR12R1_DACC1DHR                0x0FFFU            /*!<DAC channel1 12-bit Right aligned data */\r\n\r\n/*****************  Bit definition for DAC_DHR12L1 register  ******************/\r\n#define  DAC_DHR12L1_DACC1DHR                0xFFF0U            /*!<DAC channel1 12-bit Left aligned data */\r\n\r\n/******************  Bit definition for DAC_DHR8R1 register  ******************/\r\n#define  DAC_DHR8R1_DACC1DHR                 0xFFU               /*!<DAC channel1 8-bit Right aligned data */\r\n\r\n/*****************  Bit definition for DAC_DHR12R2 register  ******************/\r\n#define  DAC_DHR12R2_DACC2DHR                0x0FFFU            /*!<DAC channel2 12-bit Right aligned data */\r\n\r\n/*****************  Bit definition for DAC_DHR12L2 register  ******************/\r\n#define  DAC_DHR12L2_DACC2DHR                0xFFF0U            /*!<DAC channel2 12-bit Left aligned data */\r\n\r\n/******************  Bit definition for DAC_DHR8R2 register  ******************/\r\n#define  DAC_DHR8R2_DACC2DHR                 0xFFU               /*!<DAC channel2 8-bit Right aligned data */\r\n\r\n/*****************  Bit definition for DAC_DHR12RD register  ******************/\r\n#define  DAC_DHR12RD_DACC1DHR                0x00000FFFU        /*!<DAC channel1 12-bit Right aligned data */\r\n#define  DAC_DHR12RD_DACC2DHR                0x0FFF0000U        /*!<DAC channel2 12-bit Right aligned data */\r\n\r\n/*****************  Bit definition for DAC_DHR12LD register  ******************/\r\n#define  DAC_DHR12LD_DACC1DHR                0x0000FFF0U        /*!<DAC channel1 12-bit Left aligned data */\r\n#define  DAC_DHR12LD_DACC2DHR                0xFFF00000U        /*!<DAC channel2 12-bit Left aligned data */\r\n\r\n/******************  Bit definition for DAC_DHR8RD register  ******************/\r\n#define  DAC_DHR8RD_DACC1DHR                 0x00FFU            /*!<DAC channel1 8-bit Right aligned data */\r\n#define  DAC_DHR8RD_DACC2DHR                 0xFF00U            /*!<DAC channel2 8-bit Right aligned data */\r\n\r\n/*******************  Bit definition for DAC_DOR1 register  *******************/\r\n#define  DAC_DOR1_DACC1DOR                   0x0FFFU            /*!<DAC channel1 data output */\r\n\r\n/*******************  Bit definition for DAC_DOR2 register  *******************/\r\n#define  DAC_DOR2_DACC2DOR                   0x0FFFU            /*!<DAC channel2 data output */\r\n\r\n/********************  Bit definition for DAC_SR register  ********************/\r\n#define  DAC_SR_DMAUDR1                      0x00002000U        /*!<DAC channel1 DMA underrun flag */\r\n#define  DAC_SR_DMAUDR2                      0x20000000U        /*!<DAC channel2 DMA underrun flag */\r\n\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                 Debug MCU                                  */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                    DCMI                                    */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bits definition for DCMI_CR register  ******************/\r\n#define DCMI_CR_CAPTURE                      0x00000001U\r\n#define DCMI_CR_CM                           0x00000002U\r\n#define DCMI_CR_CROP                         0x00000004U\r\n#define DCMI_CR_JPEG                         0x00000008U\r\n#define DCMI_CR_ESS                          0x00000010U\r\n#define DCMI_CR_PCKPOL                       0x00000020U\r\n#define DCMI_CR_HSPOL                        0x00000040U\r\n#define DCMI_CR_VSPOL                        0x00000080U\r\n#define DCMI_CR_FCRC_0                       0x00000100U\r\n#define DCMI_CR_FCRC_1                       0x00000200U\r\n#define DCMI_CR_EDM_0                        0x00000400U\r\n#define DCMI_CR_EDM_1                        0x00000800U\r\n#define DCMI_CR_CRE                          0x00001000U\r\n#define DCMI_CR_ENABLE                       0x00004000U\r\n#define DCMI_CR_BSM                          0x00030000U\r\n#define DCMI_CR_BSM_0                        0x00010000U\r\n#define DCMI_CR_BSM_1                        0x00020000U\r\n#define DCMI_CR_OEBS                         0x00040000U\r\n#define DCMI_CR_LSM                          0x00080000U\r\n#define DCMI_CR_OELS                         0x00100000U\r\n\r\n/********************  Bits definition for DCMI_SR register  ******************/\r\n#define DCMI_SR_HSYNC                        0x00000001U\r\n#define DCMI_SR_VSYNC                        0x00000002U\r\n#define DCMI_SR_FNE                          0x00000004U\r\n\r\n/********************  Bits definition for DCMI_RIS register   ****************/\r\n#define DCMI_RIS_FRAME_RIS                   0x00000001U\r\n#define DCMI_RIS_OVR_RIS                     0x00000002U\r\n#define DCMI_RIS_ERR_RIS                     0x00000004U\r\n#define DCMI_RIS_VSYNC_RIS                   0x00000008U\r\n#define DCMI_RIS_LINE_RIS                    0x00000010U\r\n\r\n/* Legacy defines */\r\n#define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS\r\n#define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS\r\n#define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS\r\n#define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS\r\n#define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS\r\n\r\n/********************  Bits definition for DCMI_IER register  *****************/\r\n#define DCMI_IER_FRAME_IE                    0x00000001U\r\n#define DCMI_IER_OVR_IE                      0x00000002U\r\n#define DCMI_IER_ERR_IE                      0x00000004U\r\n#define DCMI_IER_VSYNC_IE                    0x00000008U\r\n#define DCMI_IER_LINE_IE                     0x00000010U\r\n\r\n/* Legacy define */\r\n#define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE\r\n\r\n/********************  Bits definition for DCMI_MIS register  *****************/\r\n#define DCMI_MIS_FRAME_MIS                   0x00000001U\r\n#define DCMI_MIS_OVR_MIS                     0x00000002U\r\n#define DCMI_MIS_ERR_MIS                     0x00000004U\r\n#define DCMI_MIS_VSYNC_MIS                   0x00000008U\r\n#define DCMI_MIS_LINE_MIS                    0x00000010U\r\n\r\n/* Legacy defines */\r\n#define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS\r\n#define DCMI_MISR_OVF_MIS                    DCMI_MIS_OVR_MIS\r\n#define DCMI_MISR_ERR_MIS                    DCMI_MIS_ERR_MIS\r\n#define DCMI_MISR_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS\r\n#define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS\r\n\r\n/********************  Bits definition for DCMI_ICR register  *****************/\r\n#define DCMI_ICR_FRAME_ISC                   0x00000001U\r\n#define DCMI_ICR_OVR_ISC                     0x00000002U\r\n#define DCMI_ICR_ERR_ISC                     0x00000004U\r\n#define DCMI_ICR_VSYNC_ISC                   0x00000008U\r\n#define DCMI_ICR_LINE_ISC                    0x00000010U\r\n\r\n/* Legacy defines */\r\n#define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC\r\n\r\n/********************  Bits definition for DCMI_ESCR register  ******************/\r\n#define DCMI_ESCR_FSC                        0x000000FFU\r\n#define DCMI_ESCR_LSC                        0x0000FF00U\r\n#define DCMI_ESCR_LEC                        0x00FF0000U\r\n#define DCMI_ESCR_FEC                        0xFF000000U\r\n\r\n/********************  Bits definition for DCMI_ESUR register  ******************/\r\n#define DCMI_ESUR_FSU                        0x000000FFU\r\n#define DCMI_ESUR_LSU                        0x0000FF00U\r\n#define DCMI_ESUR_LEU                        0x00FF0000U\r\n#define DCMI_ESUR_FEU                        0xFF000000U\r\n\r\n/********************  Bits definition for DCMI_CWSTRT register  ******************/\r\n#define DCMI_CWSTRT_HOFFCNT                  0x00003FFFU\r\n#define DCMI_CWSTRT_VST                      0x1FFF0000U\r\n\r\n/********************  Bits definition for DCMI_CWSIZE register  ******************/\r\n#define DCMI_CWSIZE_CAPCNT                   0x00003FFFU\r\n#define DCMI_CWSIZE_VLINE                    0x3FFF0000U\r\n\r\n/********************  Bits definition for DCMI_DR register  ******************/\r\n#define DCMI_DR_BYTE0                        0x000000FFU\r\n#define DCMI_DR_BYTE1                        0x0000FF00U\r\n#define DCMI_DR_BYTE2                        0x00FF0000U\r\n#define DCMI_DR_BYTE3                        0xFF000000U\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                             DMA Controller                                 */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bits definition for DMA_SxCR register  *****************/ \r\n#define DMA_SxCR_CHSEL                       0x0E000000U\r\n#define DMA_SxCR_CHSEL_0                     0x02000000U\r\n#define DMA_SxCR_CHSEL_1                     0x04000000U\r\n#define DMA_SxCR_CHSEL_2                     0x08000000U\r\n#define DMA_SxCR_MBURST                      0x01800000U\r\n#define DMA_SxCR_MBURST_0                    0x00800000U\r\n#define DMA_SxCR_MBURST_1                    0x01000000U\r\n#define DMA_SxCR_PBURST                      0x00600000U\r\n#define DMA_SxCR_PBURST_0                    0x00200000U\r\n#define DMA_SxCR_PBURST_1                    0x00400000U\r\n#define DMA_SxCR_CT                          0x00080000U  \r\n#define DMA_SxCR_DBM                         0x00040000U\r\n#define DMA_SxCR_PL                          0x00030000U\r\n#define DMA_SxCR_PL_0                        0x00010000U\r\n#define DMA_SxCR_PL_1                        0x00020000U\r\n#define DMA_SxCR_PINCOS                      0x00008000U\r\n#define DMA_SxCR_MSIZE                       0x00006000U\r\n#define DMA_SxCR_MSIZE_0                     0x00002000U\r\n#define DMA_SxCR_MSIZE_1                     0x00004000U\r\n#define DMA_SxCR_PSIZE                       0x00001800U\r\n#define DMA_SxCR_PSIZE_0                     0x00000800U\r\n#define DMA_SxCR_PSIZE_1                     0x00001000U\r\n#define DMA_SxCR_MINC                        0x00000400U\r\n#define DMA_SxCR_PINC                        0x00000200U\r\n#define DMA_SxCR_CIRC                        0x00000100U\r\n#define DMA_SxCR_DIR                         0x000000C0U\r\n#define DMA_SxCR_DIR_0                       0x00000040U\r\n#define DMA_SxCR_DIR_1                       0x00000080U\r\n#define DMA_SxCR_PFCTRL                      0x00000020U\r\n#define DMA_SxCR_TCIE                        0x00000010U\r\n#define DMA_SxCR_HTIE                        0x00000008U\r\n#define DMA_SxCR_TEIE                        0x00000004U\r\n#define DMA_SxCR_DMEIE                       0x00000002U\r\n#define DMA_SxCR_EN                          0x00000001U\r\n\r\n/********************  Bits definition for DMA_SxCNDTR register  **************/\r\n#define DMA_SxNDT                            0x0000FFFFU\r\n#define DMA_SxNDT_0                          0x00000001U\r\n#define DMA_SxNDT_1                          0x00000002U\r\n#define DMA_SxNDT_2                          0x00000004U\r\n#define DMA_SxNDT_3                          0x00000008U\r\n#define DMA_SxNDT_4                          0x00000010U\r\n#define DMA_SxNDT_5                          0x00000020U\r\n#define DMA_SxNDT_6                          0x00000040U\r\n#define DMA_SxNDT_7                          0x00000080U\r\n#define DMA_SxNDT_8                          0x00000100U\r\n#define DMA_SxNDT_9                          0x00000200U\r\n#define DMA_SxNDT_10                         0x00000400U\r\n#define DMA_SxNDT_11                         0x00000800U\r\n#define DMA_SxNDT_12                         0x00001000U\r\n#define DMA_SxNDT_13                         0x00002000U\r\n#define DMA_SxNDT_14                         0x00004000U\r\n#define DMA_SxNDT_15                         0x00008000U\r\n\r\n/********************  Bits definition for DMA_SxFCR register  ****************/ \r\n#define DMA_SxFCR_FEIE                       0x00000080U\r\n#define DMA_SxFCR_FS                         0x00000038U\r\n#define DMA_SxFCR_FS_0                       0x00000008U\r\n#define DMA_SxFCR_FS_1                       0x00000010U\r\n#define DMA_SxFCR_FS_2                       0x00000020U\r\n#define DMA_SxFCR_DMDIS                      0x00000004U\r\n#define DMA_SxFCR_FTH                        0x00000003U\r\n#define DMA_SxFCR_FTH_0                      0x00000001U\r\n#define DMA_SxFCR_FTH_1                      0x00000002U\r\n\r\n/********************  Bits definition for DMA_LISR register  *****************/ \r\n#define DMA_LISR_TCIF3                       0x08000000U\r\n#define DMA_LISR_HTIF3                       0x04000000U\r\n#define DMA_LISR_TEIF3                       0x02000000U\r\n#define DMA_LISR_DMEIF3                      0x01000000U\r\n#define DMA_LISR_FEIF3                       0x00400000U\r\n#define DMA_LISR_TCIF2                       0x00200000U\r\n#define DMA_LISR_HTIF2                       0x00100000U\r\n#define DMA_LISR_TEIF2                       0x00080000U\r\n#define DMA_LISR_DMEIF2                      0x00040000U\r\n#define DMA_LISR_FEIF2                       0x00010000U\r\n#define DMA_LISR_TCIF1                       0x00000800U\r\n#define DMA_LISR_HTIF1                       0x00000400U\r\n#define DMA_LISR_TEIF1                       0x00000200U\r\n#define DMA_LISR_DMEIF1                      0x00000100U\r\n#define DMA_LISR_FEIF1                       0x00000040U\r\n#define DMA_LISR_TCIF0                       0x00000020U\r\n#define DMA_LISR_HTIF0                       0x00000010U\r\n#define DMA_LISR_TEIF0                       0x00000008U\r\n#define DMA_LISR_DMEIF0                      0x00000004U\r\n#define DMA_LISR_FEIF0                       0x00000001U\r\n\r\n/********************  Bits definition for DMA_HISR register  *****************/ \r\n#define DMA_HISR_TCIF7                       0x08000000U\r\n#define DMA_HISR_HTIF7                       0x04000000U\r\n#define DMA_HISR_TEIF7                       0x02000000U\r\n#define DMA_HISR_DMEIF7                      0x01000000U\r\n#define DMA_HISR_FEIF7                       0x00400000U\r\n#define DMA_HISR_TCIF6                       0x00200000U\r\n#define DMA_HISR_HTIF6                       0x00100000U\r\n#define DMA_HISR_TEIF6                       0x00080000U\r\n#define DMA_HISR_DMEIF6                      0x00040000U\r\n#define DMA_HISR_FEIF6                       0x00010000U\r\n#define DMA_HISR_TCIF5                       0x00000800U\r\n#define DMA_HISR_HTIF5                       0x00000400U\r\n#define DMA_HISR_TEIF5                       0x00000200U\r\n#define DMA_HISR_DMEIF5                      0x00000100U\r\n#define DMA_HISR_FEIF5                       0x00000040U\r\n#define DMA_HISR_TCIF4                       0x00000020U\r\n#define DMA_HISR_HTIF4                       0x00000010U\r\n#define DMA_HISR_TEIF4                       0x00000008U\r\n#define DMA_HISR_DMEIF4                      0x00000004U\r\n#define DMA_HISR_FEIF4                       0x00000001U\r\n\r\n/********************  Bits definition for DMA_LIFCR register  ****************/ \r\n#define DMA_LIFCR_CTCIF3                     0x08000000U\r\n#define DMA_LIFCR_CHTIF3                     0x04000000U\r\n#define DMA_LIFCR_CTEIF3                     0x02000000U\r\n#define DMA_LIFCR_CDMEIF3                    0x01000000U\r\n#define DMA_LIFCR_CFEIF3                     0x00400000U\r\n#define DMA_LIFCR_CTCIF2                     0x00200000U\r\n#define DMA_LIFCR_CHTIF2                     0x00100000U\r\n#define DMA_LIFCR_CTEIF2                     0x00080000U\r\n#define DMA_LIFCR_CDMEIF2                    0x00040000U\r\n#define DMA_LIFCR_CFEIF2                     0x00010000U\r\n#define DMA_LIFCR_CTCIF1                     0x00000800U\r\n#define DMA_LIFCR_CHTIF1                     0x00000400U\r\n#define DMA_LIFCR_CTEIF1                     0x00000200U\r\n#define DMA_LIFCR_CDMEIF1                    0x00000100U\r\n#define DMA_LIFCR_CFEIF1                     0x00000040U\r\n#define DMA_LIFCR_CTCIF0                     0x00000020U\r\n#define DMA_LIFCR_CHTIF0                     0x00000010U\r\n#define DMA_LIFCR_CTEIF0                     0x00000008U\r\n#define DMA_LIFCR_CDMEIF0                    0x00000004U\r\n#define DMA_LIFCR_CFEIF0                     0x00000001U\r\n\r\n/********************  Bits definition for DMA_HIFCR  register  ****************/ \r\n#define DMA_HIFCR_CTCIF7                     0x08000000U\r\n#define DMA_HIFCR_CHTIF7                     0x04000000U\r\n#define DMA_HIFCR_CTEIF7                     0x02000000U\r\n#define DMA_HIFCR_CDMEIF7                    0x01000000U\r\n#define DMA_HIFCR_CFEIF7                     0x00400000U\r\n#define DMA_HIFCR_CTCIF6                     0x00200000U\r\n#define DMA_HIFCR_CHTIF6                     0x00100000U\r\n#define DMA_HIFCR_CTEIF6                     0x00080000U\r\n#define DMA_HIFCR_CDMEIF6                    0x00040000U\r\n#define DMA_HIFCR_CFEIF6                     0x00010000U\r\n#define DMA_HIFCR_CTCIF5                     0x00000800U\r\n#define DMA_HIFCR_CHTIF5                     0x00000400U\r\n#define DMA_HIFCR_CTEIF5                     0x00000200U\r\n#define DMA_HIFCR_CDMEIF5                    0x00000100U\r\n#define DMA_HIFCR_CFEIF5                     0x00000040U\r\n#define DMA_HIFCR_CTCIF4                     0x00000020U\r\n#define DMA_HIFCR_CHTIF4                     0x00000010U\r\n#define DMA_HIFCR_CTEIF4                     0x00000008U\r\n#define DMA_HIFCR_CDMEIF4                    0x00000004U\r\n#define DMA_HIFCR_CFEIF4                     0x00000001U\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                         AHB Master DMA2D Controller (DMA2D)                */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n\r\n/********************  Bit definition for DMA2D_CR register  ******************/\r\n\r\n#define DMA2D_CR_START                     0x00000001U               /*!< Start transfer                          */\r\n#define DMA2D_CR_SUSP                      0x00000002U               /*!< Suspend transfer                        */\r\n#define DMA2D_CR_ABORT                     0x00000004U               /*!< Abort transfer                          */\r\n#define DMA2D_CR_TEIE                      0x00000100U               /*!< Transfer Error Interrupt Enable         */\r\n#define DMA2D_CR_TCIE                      0x00000200U               /*!< Transfer Complete Interrupt Enable      */\r\n#define DMA2D_CR_TWIE                      0x00000400U               /*!< Transfer Watermark Interrupt Enable     */\r\n#define DMA2D_CR_CAEIE                     0x00000800U               /*!< CLUT Access Error Interrupt Enable      */\r\n#define DMA2D_CR_CTCIE                     0x00001000U               /*!< CLUT Transfer Complete Interrupt Enable */\r\n#define DMA2D_CR_CEIE                      0x00002000U               /*!< Configuration Error Interrupt Enable    */\r\n#define DMA2D_CR_MODE                      0x00030000U               /*!< DMA2D Mode[1:0]                         */\r\n#define DMA2D_CR_MODE_0                    0x00010000U               /*!< DMA2D Mode bit 0                        */\r\n#define DMA2D_CR_MODE_1                    0x00020000U               /*!< DMA2D Mode bit 1                        */\r\n\r\n/********************  Bit definition for DMA2D_ISR register  *****************/\r\n\r\n#define DMA2D_ISR_TEIF                     0x00000001U               /*!< Transfer Error Interrupt Flag         */\r\n#define DMA2D_ISR_TCIF                     0x00000002U               /*!< Transfer Complete Interrupt Flag      */\r\n#define DMA2D_ISR_TWIF                     0x00000004U               /*!< Transfer Watermark Interrupt Flag     */\r\n#define DMA2D_ISR_CAEIF                    0x00000008U               /*!< CLUT Access Error Interrupt Flag      */\r\n#define DMA2D_ISR_CTCIF                    0x00000010U               /*!< CLUT Transfer Complete Interrupt Flag */\r\n#define DMA2D_ISR_CEIF                     0x00000020U               /*!< Configuration Error Interrupt Flag    */\r\n\r\n/********************  Bit definition for DMA2D_IFCR register  ****************/\r\n\r\n#define DMA2D_IFCR_CTEIF                   0x00000001U               /*!< Clears Transfer Error Interrupt Flag         */\r\n#define DMA2D_IFCR_CTCIF                   0x00000002U               /*!< Clears Transfer Complete Interrupt Flag      */\r\n#define DMA2D_IFCR_CTWIF                   0x00000004U               /*!< Clears Transfer Watermark Interrupt Flag     */\r\n#define DMA2D_IFCR_CAECIF                  0x00000008U               /*!< Clears CLUT Access Error Interrupt Flag      */\r\n#define DMA2D_IFCR_CCTCIF                  0x00000010U               /*!< Clears CLUT Transfer Complete Interrupt Flag */\r\n#define DMA2D_IFCR_CCEIF                   0x00000020U               /*!< Clears Configuration Error Interrupt Flag    */\r\n\r\n/* Legacy defines */\r\n#define DMA2D_IFSR_CTEIF                   DMA2D_IFCR_CTEIF                     /*!< Clears Transfer Error Interrupt Flag         */\r\n#define DMA2D_IFSR_CTCIF                   DMA2D_IFCR_CTCIF                     /*!< Clears Transfer Complete Interrupt Flag      */\r\n#define DMA2D_IFSR_CTWIF                   DMA2D_IFCR_CTWIF                     /*!< Clears Transfer Watermark Interrupt Flag     */\r\n#define DMA2D_IFSR_CCAEIF                  DMA2D_IFCR_CAECIF                    /*!< Clears CLUT Access Error Interrupt Flag      */\r\n#define DMA2D_IFSR_CCTCIF                  DMA2D_IFCR_CCTCIF                    /*!< Clears CLUT Transfer Complete Interrupt Flag */\r\n#define DMA2D_IFSR_CCEIF                   DMA2D_IFCR_CCEIF                     /*!< Clears Configuration Error Interrupt Flag    */\r\n\r\n/********************  Bit definition for DMA2D_FGMAR register  ***************/\r\n\r\n#define DMA2D_FGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */\r\n\r\n/********************  Bit definition for DMA2D_FGOR register  ****************/\r\n\r\n#define DMA2D_FGOR_LO                      0x00003FFFU               /*!< Line Offset */\r\n\r\n/********************  Bit definition for DMA2D_BGMAR register  ***************/\r\n\r\n#define DMA2D_BGMAR_MA                     0xFFFFFFFFU               /*!< Memory Address */\r\n\r\n/********************  Bit definition for DMA2D_BGOR register  ****************/\r\n\r\n#define DMA2D_BGOR_LO                      0x00003FFFU               /*!< Line Offset */\r\n\r\n/********************  Bit definition for DMA2D_FGPFCCR register  *************/\r\n\r\n#define DMA2D_FGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */\r\n#define DMA2D_FGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */\r\n#define DMA2D_FGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */\r\n#define DMA2D_FGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */\r\n#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */\r\n#define DMA2D_FGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */\r\n#define DMA2D_FGPFCCR_START                0x00000020U               /*!< Start */\r\n#define DMA2D_FGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */\r\n#define DMA2D_FGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */\r\n#define DMA2D_FGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */\r\n#define DMA2D_FGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */\r\n#define DMA2D_FGPFCCR_ALPHA                0xFF000000U               /*!< Alpha value */\r\n\r\n/********************  Bit definition for DMA2D_FGCOLR register  **************/\r\n\r\n#define DMA2D_FGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */\r\n#define DMA2D_FGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */\r\n#define DMA2D_FGCOLR_RED                   0x00FF0000U               /*!< Red Value */   \r\n\r\n/********************  Bit definition for DMA2D_BGPFCCR register  *************/\r\n\r\n#define DMA2D_BGPFCCR_CM                   0x0000000FU               /*!< Input color mode CM[3:0] */\r\n#define DMA2D_BGPFCCR_CM_0                 0x00000001U               /*!< Input color mode CM bit 0 */\r\n#define DMA2D_BGPFCCR_CM_1                 0x00000002U               /*!< Input color mode CM bit 1 */\r\n#define DMA2D_BGPFCCR_CM_2                 0x00000004U               /*!< Input color mode CM bit 2 */\r\n#define DMA2D_FGPFCCR_CM_3                 0x00000008U               /*!< Input color mode CM bit 3 */\r\n#define DMA2D_BGPFCCR_CCM                  0x00000010U               /*!< CLUT Color mode */\r\n#define DMA2D_BGPFCCR_START                0x00000020U               /*!< Start */\r\n#define DMA2D_BGPFCCR_CS                   0x0000FF00U               /*!< CLUT size */\r\n#define DMA2D_BGPFCCR_AM                   0x00030000U               /*!< Alpha mode AM[1:0] */\r\n#define DMA2D_BGPFCCR_AM_0                 0x00010000U               /*!< Alpha mode AM bit 0 */\r\n#define DMA2D_BGPFCCR_AM_1                 0x00020000U               /*!< Alpha mode AM bit 1 */\r\n#define DMA2D_BGPFCCR_ALPHA                0xFF000000U               /*!< background Input Alpha value */\r\n\r\n/********************  Bit definition for DMA2D_BGCOLR register  **************/\r\n\r\n#define DMA2D_BGCOLR_BLUE                  0x000000FFU               /*!< Blue Value */\r\n#define DMA2D_BGCOLR_GREEN                 0x0000FF00U               /*!< Green Value */\r\n#define DMA2D_BGCOLR_RED                   0x00FF0000U               /*!< Red Value */\r\n\r\n/********************  Bit definition for DMA2D_FGCMAR register  **************/\r\n\r\n#define DMA2D_FGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */\r\n\r\n/********************  Bit definition for DMA2D_BGCMAR register  **************/\r\n\r\n#define DMA2D_BGCMAR_MA                    0xFFFFFFFFU               /*!< Memory Address */\r\n\r\n/********************  Bit definition for DMA2D_OPFCCR register  **************/\r\n\r\n#define DMA2D_OPFCCR_CM                    0x00000007U               /*!< Color mode CM[2:0] */\r\n#define DMA2D_OPFCCR_CM_0                  0x00000001U               /*!< Color mode CM bit 0 */\r\n#define DMA2D_OPFCCR_CM_1                  0x00000002U               /*!< Color mode CM bit 1 */\r\n#define DMA2D_OPFCCR_CM_2                  0x00000004U               /*!< Color mode CM bit 2 */\r\n\r\n/********************  Bit definition for DMA2D_OCOLR register  ***************/\r\n\r\n/*!<Mode_ARGB8888/RGB888 */\r\n\r\n#define DMA2D_OCOLR_BLUE_1                 0x000000FFU               /*!< BLUE Value */\r\n#define DMA2D_OCOLR_GREEN_1                0x0000FF00U               /*!< GREEN Value  */\r\n#define DMA2D_OCOLR_RED_1                  0x00FF0000U               /*!< Red Value */\r\n#define DMA2D_OCOLR_ALPHA_1                0xFF000000U               /*!< Alpha Channel Value */\r\n\r\n/*!<Mode_RGB565 */\r\n#define DMA2D_OCOLR_BLUE_2                 0x0000001FU               /*!< BLUE Value */\r\n#define DMA2D_OCOLR_GREEN_2                0x000007E0U               /*!< GREEN Value  */\r\n#define DMA2D_OCOLR_RED_2                  0x0000F800U               /*!< Red Value */\r\n\r\n/*!<Mode_ARGB1555 */\r\n#define DMA2D_OCOLR_BLUE_3                 0x0000001FU               /*!< BLUE Value */\r\n#define DMA2D_OCOLR_GREEN_3                0x000003E0U               /*!< GREEN Value  */\r\n#define DMA2D_OCOLR_RED_3                  0x00007C00U               /*!< Red Value */\r\n#define DMA2D_OCOLR_ALPHA_3                0x00008000U               /*!< Alpha Channel Value */\r\n\r\n/*!<Mode_ARGB4444 */\r\n#define DMA2D_OCOLR_BLUE_4                 0x0000000FU               /*!< BLUE Value */\r\n#define DMA2D_OCOLR_GREEN_4                0x000000F0U               /*!< GREEN Value  */\r\n#define DMA2D_OCOLR_RED_4                  0x00000F00U               /*!< Red Value */\r\n#define DMA2D_OCOLR_ALPHA_4                0x0000F000U               /*!< Alpha Channel Value */\r\n\r\n/********************  Bit definition for DMA2D_OMAR register  ****************/\r\n\r\n#define DMA2D_OMAR_MA                      0xFFFFFFFFU               /*!< Memory Address */\r\n\r\n/********************  Bit definition for DMA2D_OOR register  *****************/\r\n\r\n#define DMA2D_OOR_LO                       0x00003FFFU               /*!< Line Offset */\r\n\r\n/********************  Bit definition for DMA2D_NLR register  *****************/\r\n\r\n#define DMA2D_NLR_NL                       0x0000FFFFU               /*!< Number of Lines */\r\n#define DMA2D_NLR_PL                       0x3FFF0000U               /*!< Pixel per Lines */\r\n\r\n/********************  Bit definition for DMA2D_LWR register  *****************/\r\n\r\n#define DMA2D_LWR_LW                       0x0000FFFFU               /*!< Line Watermark */\r\n\r\n/********************  Bit definition for DMA2D_AMTCR register  ***************/\r\n\r\n#define DMA2D_AMTCR_EN                     0x00000001U               /*!< Enable */\r\n#define DMA2D_AMTCR_DT                     0x0000FF00U               /*!< Dead Time */\r\n\r\n\r\n/********************  Bit definition for DMA2D_FGCLUT register  **************/\r\n                                                                     \r\n/********************  Bit definition for DMA2D_BGCLUT register  **************/\r\n\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                    External Interrupt/Event Controller                     */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************  Bit definition for EXTI_IMR register  *******************/\r\n#define  EXTI_IMR_MR0                        0x00000001U        /*!< Interrupt Mask on line 0 */\r\n#define  EXTI_IMR_MR1                        0x00000002U        /*!< Interrupt Mask on line 1 */\r\n#define  EXTI_IMR_MR2                        0x00000004U        /*!< Interrupt Mask on line 2 */\r\n#define  EXTI_IMR_MR3                        0x00000008U        /*!< Interrupt Mask on line 3 */\r\n#define  EXTI_IMR_MR4                        0x00000010U        /*!< Interrupt Mask on line 4 */\r\n#define  EXTI_IMR_MR5                        0x00000020U        /*!< Interrupt Mask on line 5 */\r\n#define  EXTI_IMR_MR6                        0x00000040U        /*!< Interrupt Mask on line 6 */\r\n#define  EXTI_IMR_MR7                        0x00000080U        /*!< Interrupt Mask on line 7 */\r\n#define  EXTI_IMR_MR8                        0x00000100U        /*!< Interrupt Mask on line 8 */\r\n#define  EXTI_IMR_MR9                        0x00000200U        /*!< Interrupt Mask on line 9 */\r\n#define  EXTI_IMR_MR10                       0x00000400U        /*!< Interrupt Mask on line 10 */\r\n#define  EXTI_IMR_MR11                       0x00000800U        /*!< Interrupt Mask on line 11 */\r\n#define  EXTI_IMR_MR12                       0x00001000U        /*!< Interrupt Mask on line 12 */\r\n#define  EXTI_IMR_MR13                       0x00002000U        /*!< Interrupt Mask on line 13 */\r\n#define  EXTI_IMR_MR14                       0x00004000U        /*!< Interrupt Mask on line 14 */\r\n#define  EXTI_IMR_MR15                       0x00008000U        /*!< Interrupt Mask on line 15 */\r\n#define  EXTI_IMR_MR16                       0x00010000U        /*!< Interrupt Mask on line 16 */\r\n#define  EXTI_IMR_MR17                       0x00020000U        /*!< Interrupt Mask on line 17 */\r\n#define  EXTI_IMR_MR18                       0x00040000U        /*!< Interrupt Mask on line 18 */\r\n#define  EXTI_IMR_MR19                       0x00080000U        /*!< Interrupt Mask on line 19 */\r\n#define  EXTI_IMR_MR20                       0x00100000U        /*!< Interrupt Mask on line 20 */\r\n#define  EXTI_IMR_MR21                       0x00200000U        /*!< Interrupt Mask on line 21 */\r\n#define  EXTI_IMR_MR22                       0x00400000U        /*!< Interrupt Mask on line 22 */\r\n#define  EXTI_IMR_MR23                       0x00800000U        /*!< Interrupt Mask on line 23 */\r\n\r\n/* Reference Defines */\r\n#define  EXTI_IMR_IM0                        EXTI_IMR_MR0                     \r\n#define  EXTI_IMR_IM1                        EXTI_IMR_MR1 \r\n#define  EXTI_IMR_IM2                        EXTI_IMR_MR2 \r\n#define  EXTI_IMR_IM3                        EXTI_IMR_MR3 \r\n#define  EXTI_IMR_IM4                        EXTI_IMR_MR4 \r\n#define  EXTI_IMR_IM5                        EXTI_IMR_MR5 \r\n#define  EXTI_IMR_IM6                        EXTI_IMR_MR6 \r\n#define  EXTI_IMR_IM7                        EXTI_IMR_MR7 \r\n#define  EXTI_IMR_IM8                        EXTI_IMR_MR8 \r\n#define  EXTI_IMR_IM9                        EXTI_IMR_MR9 \r\n#define  EXTI_IMR_IM10                       EXTI_IMR_MR10\r\n#define  EXTI_IMR_IM11                       EXTI_IMR_MR11\r\n#define  EXTI_IMR_IM12                       EXTI_IMR_MR12\r\n#define  EXTI_IMR_IM13                       EXTI_IMR_MR13\r\n#define  EXTI_IMR_IM14                       EXTI_IMR_MR14\r\n#define  EXTI_IMR_IM15                       EXTI_IMR_MR15\r\n#define  EXTI_IMR_IM16                       EXTI_IMR_MR16\r\n#define  EXTI_IMR_IM17                       EXTI_IMR_MR17\r\n#define  EXTI_IMR_IM18                       EXTI_IMR_MR18\r\n#define  EXTI_IMR_IM19                       EXTI_IMR_MR19\r\n#define  EXTI_IMR_IM20                       EXTI_IMR_MR20\r\n#define  EXTI_IMR_IM21                       EXTI_IMR_MR21\r\n#define  EXTI_IMR_IM22                       EXTI_IMR_MR22\r\n#define  EXTI_IMR_IM23                       EXTI_IMR_MR23\r\n\r\n#define  EXTI_IMR_IM                         0x00FFFFFFU        /*!< Interrupt Mask All */\r\n\r\n/*******************  Bit definition for EXTI_EMR register  *******************/\r\n#define  EXTI_EMR_MR0                        0x00000001U        /*!< Event Mask on line 0 */\r\n#define  EXTI_EMR_MR1                        0x00000002U        /*!< Event Mask on line 1 */\r\n#define  EXTI_EMR_MR2                        0x00000004U        /*!< Event Mask on line 2 */\r\n#define  EXTI_EMR_MR3                        0x00000008U        /*!< Event Mask on line 3 */\r\n#define  EXTI_EMR_MR4                        0x00000010U        /*!< Event Mask on line 4 */\r\n#define  EXTI_EMR_MR5                        0x00000020U        /*!< Event Mask on line 5 */\r\n#define  EXTI_EMR_MR6                        0x00000040U        /*!< Event Mask on line 6 */\r\n#define  EXTI_EMR_MR7                        0x00000080U        /*!< Event Mask on line 7 */\r\n#define  EXTI_EMR_MR8                        0x00000100U        /*!< Event Mask on line 8 */\r\n#define  EXTI_EMR_MR9                        0x00000200U        /*!< Event Mask on line 9 */\r\n#define  EXTI_EMR_MR10                       0x00000400U        /*!< Event Mask on line 10 */\r\n#define  EXTI_EMR_MR11                       0x00000800U        /*!< Event Mask on line 11 */\r\n#define  EXTI_EMR_MR12                       0x00001000U        /*!< Event Mask on line 12 */\r\n#define  EXTI_EMR_MR13                       0x00002000U        /*!< Event Mask on line 13 */\r\n#define  EXTI_EMR_MR14                       0x00004000U        /*!< Event Mask on line 14 */\r\n#define  EXTI_EMR_MR15                       0x00008000U        /*!< Event Mask on line 15 */\r\n#define  EXTI_EMR_MR16                       0x00010000U        /*!< Event Mask on line 16 */\r\n#define  EXTI_EMR_MR17                       0x00020000U        /*!< Event Mask on line 17 */\r\n#define  EXTI_EMR_MR18                       0x00040000U        /*!< Event Mask on line 18 */\r\n#define  EXTI_EMR_MR19                       0x00080000U        /*!< Event Mask on line 19 */\r\n#define  EXTI_EMR_MR20                       0x00100000U        /*!< Event Mask on line 20 */\r\n#define  EXTI_EMR_MR21                       0x00200000U        /*!< Event Mask on line 21 */\r\n#define  EXTI_EMR_MR22                       0x00400000U        /*!< Event Mask on line 22 */\r\n#define  EXTI_EMR_MR23                       0x00800000U        /*!< Event Mask on line 23 */\r\n\r\n/* Reference Defines */\r\n#define  EXTI_EMR_EM0                        EXTI_EMR_MR0                         \r\n#define  EXTI_EMR_EM1                        EXTI_EMR_MR1 \r\n#define  EXTI_EMR_EM2                        EXTI_EMR_MR2 \r\n#define  EXTI_EMR_EM3                        EXTI_EMR_MR3 \r\n#define  EXTI_EMR_EM4                        EXTI_EMR_MR4 \r\n#define  EXTI_EMR_EM5                        EXTI_EMR_MR5 \r\n#define  EXTI_EMR_EM6                        EXTI_EMR_MR6 \r\n#define  EXTI_EMR_EM7                        EXTI_EMR_MR7 \r\n#define  EXTI_EMR_EM8                        EXTI_EMR_MR8 \r\n#define  EXTI_EMR_EM9                        EXTI_EMR_MR9 \r\n#define  EXTI_EMR_EM10                       EXTI_EMR_MR10\r\n#define  EXTI_EMR_EM11                       EXTI_EMR_MR11\r\n#define  EXTI_EMR_EM12                       EXTI_EMR_MR12\r\n#define  EXTI_EMR_EM13                       EXTI_EMR_MR13\r\n#define  EXTI_EMR_EM14                       EXTI_EMR_MR14\r\n#define  EXTI_EMR_EM15                       EXTI_EMR_MR15\r\n#define  EXTI_EMR_EM16                       EXTI_EMR_MR16\r\n#define  EXTI_EMR_EM17                       EXTI_EMR_MR17\r\n#define  EXTI_EMR_EM18                       EXTI_EMR_MR18\r\n#define  EXTI_EMR_EM19                       EXTI_EMR_MR19\r\n#define  EXTI_EMR_EM20                       EXTI_EMR_MR20\r\n#define  EXTI_EMR_EM21                       EXTI_EMR_MR21\r\n#define  EXTI_EMR_EM22                       EXTI_EMR_MR22\r\n#define  EXTI_EMR_EM23                       EXTI_EMR_MR23\r\n\r\n\r\n/******************  Bit definition for EXTI_RTSR register  *******************/\r\n#define  EXTI_RTSR_TR0                       0x00000001U        /*!< Rising trigger event configuration bit of line 0 */\r\n#define  EXTI_RTSR_TR1                       0x00000002U        /*!< Rising trigger event configuration bit of line 1 */\r\n#define  EXTI_RTSR_TR2                       0x00000004U        /*!< Rising trigger event configuration bit of line 2 */\r\n#define  EXTI_RTSR_TR3                       0x00000008U        /*!< Rising trigger event configuration bit of line 3 */\r\n#define  EXTI_RTSR_TR4                       0x00000010U        /*!< Rising trigger event configuration bit of line 4 */\r\n#define  EXTI_RTSR_TR5                       0x00000020U        /*!< Rising trigger event configuration bit of line 5 */\r\n#define  EXTI_RTSR_TR6                       0x00000040U        /*!< Rising trigger event configuration bit of line 6 */\r\n#define  EXTI_RTSR_TR7                       0x00000080U        /*!< Rising trigger event configuration bit of line 7 */\r\n#define  EXTI_RTSR_TR8                       0x00000100U        /*!< Rising trigger event configuration bit of line 8 */\r\n#define  EXTI_RTSR_TR9                       0x00000200U        /*!< Rising trigger event configuration bit of line 9 */\r\n#define  EXTI_RTSR_TR10                      0x00000400U        /*!< Rising trigger event configuration bit of line 10 */\r\n#define  EXTI_RTSR_TR11                      0x00000800U        /*!< Rising trigger event configuration bit of line 11 */\r\n#define  EXTI_RTSR_TR12                      0x00001000U        /*!< Rising trigger event configuration bit of line 12 */\r\n#define  EXTI_RTSR_TR13                      0x00002000U        /*!< Rising trigger event configuration bit of line 13 */\r\n#define  EXTI_RTSR_TR14                      0x00004000U        /*!< Rising trigger event configuration bit of line 14 */\r\n#define  EXTI_RTSR_TR15                      0x00008000U        /*!< Rising trigger event configuration bit of line 15 */\r\n#define  EXTI_RTSR_TR16                      0x00010000U        /*!< Rising trigger event configuration bit of line 16 */\r\n#define  EXTI_RTSR_TR17                      0x00020000U        /*!< Rising trigger event configuration bit of line 17 */\r\n#define  EXTI_RTSR_TR18                      0x00040000U        /*!< Rising trigger event configuration bit of line 18 */\r\n#define  EXTI_RTSR_TR19                      0x00080000U        /*!< Rising trigger event configuration bit of line 19 */\r\n#define  EXTI_RTSR_TR20                      0x00100000U        /*!< Rising trigger event configuration bit of line 20 */\r\n#define  EXTI_RTSR_TR21                      0x00200000U        /*!< Rising trigger event configuration bit of line 21 */\r\n#define  EXTI_RTSR_TR22                      0x00400000U        /*!< Rising trigger event configuration bit of line 22 */\r\n#define  EXTI_RTSR_TR23                      0x00800000U        /*!< Rising trigger event configuration bit of line 23 */\r\n\r\n/******************  Bit definition for EXTI_FTSR register  *******************/\r\n#define  EXTI_FTSR_TR0                       0x00000001U        /*!< Falling trigger event configuration bit of line 0 */\r\n#define  EXTI_FTSR_TR1                       0x00000002U        /*!< Falling trigger event configuration bit of line 1 */\r\n#define  EXTI_FTSR_TR2                       0x00000004U        /*!< Falling trigger event configuration bit of line 2 */\r\n#define  EXTI_FTSR_TR3                       0x00000008U        /*!< Falling trigger event configuration bit of line 3 */\r\n#define  EXTI_FTSR_TR4                       0x00000010U        /*!< Falling trigger event configuration bit of line 4 */\r\n#define  EXTI_FTSR_TR5                       0x00000020U        /*!< Falling trigger event configuration bit of line 5 */\r\n#define  EXTI_FTSR_TR6                       0x00000040U        /*!< Falling trigger event configuration bit of line 6 */\r\n#define  EXTI_FTSR_TR7                       0x00000080U        /*!< Falling trigger event configuration bit of line 7 */\r\n#define  EXTI_FTSR_TR8                       0x00000100U        /*!< Falling trigger event configuration bit of line 8 */\r\n#define  EXTI_FTSR_TR9                       0x00000200U        /*!< Falling trigger event configuration bit of line 9 */\r\n#define  EXTI_FTSR_TR10                      0x00000400U        /*!< Falling trigger event configuration bit of line 10 */\r\n#define  EXTI_FTSR_TR11                      0x00000800U        /*!< Falling trigger event configuration bit of line 11 */\r\n#define  EXTI_FTSR_TR12                      0x00001000U        /*!< Falling trigger event configuration bit of line 12 */\r\n#define  EXTI_FTSR_TR13                      0x00002000U        /*!< Falling trigger event configuration bit of line 13 */\r\n#define  EXTI_FTSR_TR14                      0x00004000U        /*!< Falling trigger event configuration bit of line 14 */\r\n#define  EXTI_FTSR_TR15                      0x00008000U        /*!< Falling trigger event configuration bit of line 15 */\r\n#define  EXTI_FTSR_TR16                      0x00010000U        /*!< Falling trigger event configuration bit of line 16 */\r\n#define  EXTI_FTSR_TR17                      0x00020000U        /*!< Falling trigger event configuration bit of line 17 */\r\n#define  EXTI_FTSR_TR18                      0x00040000U        /*!< Falling trigger event configuration bit of line 18 */\r\n#define  EXTI_FTSR_TR19                      0x00080000U        /*!< Falling trigger event configuration bit of line 19 */\r\n#define  EXTI_FTSR_TR20                      0x00100000U        /*!< Falling trigger event configuration bit of line 20 */\r\n#define  EXTI_FTSR_TR21                      0x00200000U        /*!< Falling trigger event configuration bit of line 21 */\r\n#define  EXTI_FTSR_TR22                      0x00400000U        /*!< Falling trigger event configuration bit of line 22 */\r\n#define  EXTI_FTSR_TR23                      0x00800000U        /*!< Falling trigger event configuration bit of line 23 */\r\n\r\n/******************  Bit definition for EXTI_SWIER register  ******************/\r\n#define  EXTI_SWIER_SWIER0                   0x00000001U        /*!< Software Interrupt on line 0 */\r\n#define  EXTI_SWIER_SWIER1                   0x00000002U        /*!< Software Interrupt on line 1 */\r\n#define  EXTI_SWIER_SWIER2                   0x00000004U        /*!< Software Interrupt on line 2 */\r\n#define  EXTI_SWIER_SWIER3                   0x00000008U        /*!< Software Interrupt on line 3 */\r\n#define  EXTI_SWIER_SWIER4                   0x00000010U        /*!< Software Interrupt on line 4 */\r\n#define  EXTI_SWIER_SWIER5                   0x00000020U        /*!< Software Interrupt on line 5 */\r\n#define  EXTI_SWIER_SWIER6                   0x00000040U        /*!< Software Interrupt on line 6 */\r\n#define  EXTI_SWIER_SWIER7                   0x00000080U        /*!< Software Interrupt on line 7 */\r\n#define  EXTI_SWIER_SWIER8                   0x00000100U        /*!< Software Interrupt on line 8 */\r\n#define  EXTI_SWIER_SWIER9                   0x00000200U        /*!< Software Interrupt on line 9 */\r\n#define  EXTI_SWIER_SWIER10                  0x00000400U        /*!< Software Interrupt on line 10 */\r\n#define  EXTI_SWIER_SWIER11                  0x00000800U        /*!< Software Interrupt on line 11 */\r\n#define  EXTI_SWIER_SWIER12                  0x00001000U        /*!< Software Interrupt on line 12 */\r\n#define  EXTI_SWIER_SWIER13                  0x00002000U        /*!< Software Interrupt on line 13 */\r\n#define  EXTI_SWIER_SWIER14                  0x00004000U        /*!< Software Interrupt on line 14 */\r\n#define  EXTI_SWIER_SWIER15                  0x00008000U        /*!< Software Interrupt on line 15 */\r\n#define  EXTI_SWIER_SWIER16                  0x00010000U        /*!< Software Interrupt on line 16 */\r\n#define  EXTI_SWIER_SWIER17                  0x00020000U        /*!< Software Interrupt on line 17 */\r\n#define  EXTI_SWIER_SWIER18                  0x00040000U        /*!< Software Interrupt on line 18 */\r\n#define  EXTI_SWIER_SWIER19                  0x00080000U        /*!< Software Interrupt on line 19 */\r\n#define  EXTI_SWIER_SWIER20                  0x00100000U        /*!< Software Interrupt on line 20 */\r\n#define  EXTI_SWIER_SWIER21                  0x00200000U        /*!< Software Interrupt on line 21 */\r\n#define  EXTI_SWIER_SWIER22                  0x00400000U        /*!< Software Interrupt on line 22 */\r\n#define  EXTI_SWIER_SWIER23                  0x00800000U        /*!< Software Interrupt on line 23 */\r\n\r\n/*******************  Bit definition for EXTI_PR register  ********************/\r\n#define  EXTI_PR_PR0                         0x00000001U        /*!< Pending bit for line 0 */\r\n#define  EXTI_PR_PR1                         0x00000002U        /*!< Pending bit for line 1 */\r\n#define  EXTI_PR_PR2                         0x00000004U        /*!< Pending bit for line 2 */\r\n#define  EXTI_PR_PR3                         0x00000008U        /*!< Pending bit for line 3 */\r\n#define  EXTI_PR_PR4                         0x00000010U        /*!< Pending bit for line 4 */\r\n#define  EXTI_PR_PR5                         0x00000020U        /*!< Pending bit for line 5 */\r\n#define  EXTI_PR_PR6                         0x00000040U        /*!< Pending bit for line 6 */\r\n#define  EXTI_PR_PR7                         0x00000080U        /*!< Pending bit for line 7 */\r\n#define  EXTI_PR_PR8                         0x00000100U        /*!< Pending bit for line 8 */\r\n#define  EXTI_PR_PR9                         0x00000200U        /*!< Pending bit for line 9 */\r\n#define  EXTI_PR_PR10                        0x00000400U        /*!< Pending bit for line 10 */\r\n#define  EXTI_PR_PR11                        0x00000800U        /*!< Pending bit for line 11 */\r\n#define  EXTI_PR_PR12                        0x00001000U        /*!< Pending bit for line 12 */\r\n#define  EXTI_PR_PR13                        0x00002000U        /*!< Pending bit for line 13 */\r\n#define  EXTI_PR_PR14                        0x00004000U        /*!< Pending bit for line 14 */\r\n#define  EXTI_PR_PR15                        0x00008000U        /*!< Pending bit for line 15 */\r\n#define  EXTI_PR_PR16                        0x00010000U        /*!< Pending bit for line 16 */\r\n#define  EXTI_PR_PR17                        0x00020000U        /*!< Pending bit for line 17 */\r\n#define  EXTI_PR_PR18                        0x00040000U        /*!< Pending bit for line 18 */\r\n#define  EXTI_PR_PR19                        0x00080000U        /*!< Pending bit for line 19 */\r\n#define  EXTI_PR_PR20                        0x00100000U        /*!< Pending bit for line 20 */\r\n#define  EXTI_PR_PR21                        0x00200000U        /*!< Pending bit for line 21 */\r\n#define  EXTI_PR_PR22                        0x00400000U        /*!< Pending bit for line 22 */\r\n#define  EXTI_PR_PR23                        0x00800000U        /*!< Pending bit for line 23 */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                    FLASH                                   */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*\r\n* @brief FLASH Total Sectors Number\r\n*/\r\n#define FLASH_SECTOR_TOTAL  8\t\r\n\r\n/*******************  Bits definition for FLASH_ACR register  *****************/\r\n#define FLASH_ACR_LATENCY                    0x0000000FU\r\n#define FLASH_ACR_LATENCY_0WS                0x00000000U\r\n#define FLASH_ACR_LATENCY_1WS                0x00000001U\r\n#define FLASH_ACR_LATENCY_2WS                0x00000002U\r\n#define FLASH_ACR_LATENCY_3WS                0x00000003U\r\n#define FLASH_ACR_LATENCY_4WS                0x00000004U\r\n#define FLASH_ACR_LATENCY_5WS                0x00000005U\r\n#define FLASH_ACR_LATENCY_6WS                0x00000006U\r\n#define FLASH_ACR_LATENCY_7WS                0x00000007U\r\n#define FLASH_ACR_LATENCY_8WS                0x00000008U\r\n#define FLASH_ACR_LATENCY_9WS                0x00000009U\r\n#define FLASH_ACR_LATENCY_10WS               0x0000000AU\r\n#define FLASH_ACR_LATENCY_11WS               0x0000000BU\r\n#define FLASH_ACR_LATENCY_12WS               0x0000000CU\r\n#define FLASH_ACR_LATENCY_13WS               0x0000000DU\r\n#define FLASH_ACR_LATENCY_14WS               0x0000000EU\r\n#define FLASH_ACR_LATENCY_15WS               0x0000000FU\r\n#define FLASH_ACR_PRFTEN                     0x00000100U\r\n#define FLASH_ACR_ARTEN                      0x00000200U\r\n#define FLASH_ACR_ARTRST                     0x00000800U\r\n\r\n/*******************  Bits definition for FLASH_SR register  ******************/\r\n#define FLASH_SR_EOP                         0x00000001U\r\n#define FLASH_SR_OPERR                       0x00000002U\r\n#define FLASH_SR_WRPERR                      0x00000010U\r\n#define FLASH_SR_PGAERR                      0x00000020U\r\n#define FLASH_SR_PGPERR                      0x00000040U\r\n#define FLASH_SR_ERSERR                      0x00000080U\r\n#define FLASH_SR_BSY                         0x00010000U\r\n\r\n/*******************  Bits definition for FLASH_CR register  ******************/\r\n#define FLASH_CR_PG                          0x00000001U\r\n#define FLASH_CR_SER                         0x00000002U\r\n#define FLASH_CR_MER                         0x00000004U\r\n#define FLASH_CR_SNB                         0x00000078U\r\n#define FLASH_CR_SNB_0                       0x00000008U\r\n#define FLASH_CR_SNB_1                       0x00000010U\r\n#define FLASH_CR_SNB_2                       0x00000020U\r\n#define FLASH_CR_SNB_3                       0x00000040U\r\n#define FLASH_CR_PSIZE                       0x00000300U\r\n#define FLASH_CR_PSIZE_0                     0x00000100U\r\n#define FLASH_CR_PSIZE_1                     0x00000200U\r\n#define FLASH_CR_STRT                        0x00010000U\r\n#define FLASH_CR_EOPIE                       0x01000000U\r\n#define FLASH_CR_ERRIE                       0x02000000U\r\n#define FLASH_CR_LOCK                        0x80000000U\r\n\r\n/*******************  Bits definition for FLASH_OPTCR register  ***************/\r\n#define FLASH_OPTCR_OPTLOCK                 0x00000001U\r\n#define FLASH_OPTCR_OPTSTRT                 0x00000002U\r\n#define FLASH_OPTCR_BOR_LEV                 0x0000000CU\r\n#define FLASH_OPTCR_BOR_LEV_0               0x00000004U\r\n#define FLASH_OPTCR_BOR_LEV_1               0x00000008U\r\n#define FLASH_OPTCR_WWDG_SW                 0x00000010U\r\n#define FLASH_OPTCR_IWDG_SW                 0x00000020U\r\n#define FLASH_OPTCR_nRST_STOP               0x00000040U\r\n#define FLASH_OPTCR_nRST_STDBY              0x00000080U\r\n#define FLASH_OPTCR_RDP                     0x0000FF00U\r\n#define FLASH_OPTCR_RDP_0                   0x00000100U\r\n#define FLASH_OPTCR_RDP_1                   0x00000200U\r\n#define FLASH_OPTCR_RDP_2                   0x00000400U\r\n#define FLASH_OPTCR_RDP_3                   0x00000800U\r\n#define FLASH_OPTCR_RDP_4                   0x00001000U\r\n#define FLASH_OPTCR_RDP_5                   0x00002000U\r\n#define FLASH_OPTCR_RDP_6                   0x00004000U\r\n#define FLASH_OPTCR_RDP_7                   0x00008000U\r\n#define FLASH_OPTCR_nWRP                    0x00FF0000U\r\n#define FLASH_OPTCR_nWRP_0                  0x00010000U\r\n#define FLASH_OPTCR_nWRP_1                  0x00020000U\r\n#define FLASH_OPTCR_nWRP_2                  0x00040000U\r\n#define FLASH_OPTCR_nWRP_3                  0x00080000U\r\n#define FLASH_OPTCR_nWRP_4                  0x00100000U\r\n#define FLASH_OPTCR_nWRP_5                  0x00200000U\r\n#define FLASH_OPTCR_nWRP_6                  0x00400000U\r\n#define FLASH_OPTCR_nWRP_7                  0x00800000U\r\n#define FLASH_OPTCR_IWDG_STDBY              0x40000000U\r\n#define FLASH_OPTCR_IWDG_STOP               0x80000000U\r\n\r\n/*******************  Bits definition for FLASH_OPTCR1 register  ***************/\r\n#define FLASH_OPTCR1_BOOT_ADD0              0x0000FFFFU\r\n#define FLASH_OPTCR1_BOOT_ADD1              0xFFFF0000U\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                          Flexible Memory Controller                        */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/******************  Bit definition for FMC_BCR1 register  *******************/\r\n#define  FMC_BCR1_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */\r\n#define  FMC_BCR1_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */\r\n#define  FMC_BCR1_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */\r\n#define  FMC_BCR1_MTYP_0                    0x00000004U        /*!<Bit 0 */\r\n#define  FMC_BCR1_MTYP_1                    0x00000008U        /*!<Bit 1 */\r\n#define  FMC_BCR1_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */\r\n#define  FMC_BCR1_MWID_0                    0x00000010U        /*!<Bit 0 */\r\n#define  FMC_BCR1_MWID_1                    0x00000020U        /*!<Bit 1 */\r\n#define  FMC_BCR1_FACCEN                    0x00000040U        /*!<Flash access enable        */\r\n#define  FMC_BCR1_BURSTEN                   0x00000100U        /*!<Burst enable bit           */\r\n#define  FMC_BCR1_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */\r\n#define  FMC_BCR1_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */\r\n#define  FMC_BCR1_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */\r\n#define  FMC_BCR1_WREN                      0x00001000U        /*!<Write enable bit           */\r\n#define  FMC_BCR1_WAITEN                    0x00002000U        /*!<Wait enable bit            */\r\n#define  FMC_BCR1_EXTMOD                    0x00004000U        /*!<Extended mode enable       */\r\n#define  FMC_BCR1_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */\r\n#define  FMC_BCR1_CPSIZE                    0x00070000U        /*!<CRAM page size             */\r\n#define  FMC_BCR1_CPSIZE_0                  0x00010000U        /*!<Bit 0 */\r\n#define  FMC_BCR1_CPSIZE_1                  0x00020000U        /*!<Bit 1 */\r\n#define  FMC_BCR1_CPSIZE_2                  0x00040000U        /*!<Bit 2 */\r\n#define  FMC_BCR1_CBURSTRW                  0x00080000U        /*!<Write burst enable         */\r\n#define  FMC_BCR1_CCLKEN                    0x00100000U        /*!<Continous clock enable     */\r\n#define  FMC_BCR1_WFDIS                     0x00200000U        /*!<Write FIFO Disable         */\r\n\r\n/******************  Bit definition for FMC_BCR2 register  *******************/\r\n#define  FMC_BCR2_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */\r\n#define  FMC_BCR2_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */\r\n#define  FMC_BCR2_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */\r\n#define  FMC_BCR2_MTYP_0                    0x00000004U        /*!<Bit 0 */\r\n#define  FMC_BCR2_MTYP_1                    0x00000008U        /*!<Bit 1 */\r\n#define  FMC_BCR2_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */\r\n#define  FMC_BCR2_MWID_0                    0x00000010U        /*!<Bit 0 */\r\n#define  FMC_BCR2_MWID_1                    0x00000020U        /*!<Bit 1 */\r\n#define  FMC_BCR2_FACCEN                    0x00000040U        /*!<Flash access enable        */\r\n#define  FMC_BCR2_BURSTEN                   0x00000100U        /*!<Burst enable bit           */\r\n#define  FMC_BCR2_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */\r\n#define  FMC_BCR2_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */\r\n#define  FMC_BCR2_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */\r\n#define  FMC_BCR2_WREN                      0x00001000U        /*!<Write enable bit           */\r\n#define  FMC_BCR2_WAITEN                    0x00002000U        /*!<Wait enable bit            */\r\n#define  FMC_BCR2_EXTMOD                    0x00004000U        /*!<Extended mode enable       */\r\n#define  FMC_BCR2_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */\r\n#define  FMC_BCR2_CPSIZE                    0x00070000U        /*!<CRAM page size             */\r\n#define  FMC_BCR2_CPSIZE_0                  0x00010000U        /*!<Bit 0 */\r\n#define  FMC_BCR2_CPSIZE_1                  0x00020000U        /*!<Bit 1 */\r\n#define  FMC_BCR2_CPSIZE_2                  0x00040000U        /*!<Bit 2 */\r\n#define  FMC_BCR2_CBURSTRW                  0x00080000U        /*!<Write burst enable         */\r\n\r\n/******************  Bit definition for FMC_BCR3 register  *******************/\r\n#define  FMC_BCR3_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */\r\n#define  FMC_BCR3_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */\r\n#define  FMC_BCR3_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */\r\n#define  FMC_BCR3_MTYP_0                    0x00000004U        /*!<Bit 0 */\r\n#define  FMC_BCR3_MTYP_1                    0x00000008U        /*!<Bit 1 */\r\n#define  FMC_BCR3_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */\r\n#define  FMC_BCR3_MWID_0                    0x00000010U        /*!<Bit 0 */\r\n#define  FMC_BCR3_MWID_1                    0x00000020U        /*!<Bit 1 */\r\n#define  FMC_BCR3_FACCEN                    0x00000040U        /*!<Flash access enable        */\r\n#define  FMC_BCR3_BURSTEN                   0x00000100U        /*!<Burst enable bit           */\r\n#define  FMC_BCR3_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */\r\n#define  FMC_BCR3_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */\r\n#define  FMC_BCR3_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */\r\n#define  FMC_BCR3_WREN                      0x00001000U        /*!<Write enable bit           */\r\n#define  FMC_BCR3_WAITEN                    0x00002000U        /*!<Wait enable bit            */\r\n#define  FMC_BCR3_EXTMOD                    0x00004000U        /*!<Extended mode enable       */\r\n#define  FMC_BCR3_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */\r\n#define  FMC_BCR3_CPSIZE                    0x00070000U        /*!<CRAM page size             */\r\n#define  FMC_BCR3_CPSIZE_0                  0x00010000U        /*!<Bit 0 */\r\n#define  FMC_BCR3_CPSIZE_1                  0x00020000U        /*!<Bit 1 */\r\n#define  FMC_BCR3_CPSIZE_2                  0x00040000U        /*!<Bit 2 */\r\n#define  FMC_BCR3_CBURSTRW                  0x00080000U        /*!<Write burst enable         */\r\n\r\n/******************  Bit definition for FMC_BCR4 register  *******************/\r\n#define  FMC_BCR4_MBKEN                     0x00000001U        /*!<Memory bank enable bit                 */\r\n#define  FMC_BCR4_MUXEN                     0x00000002U        /*!<Address/data multiplexing enable bit   */\r\n#define  FMC_BCR4_MTYP                      0x0000000CU        /*!<MTYP[1:0] bits (Memory type)           */\r\n#define  FMC_BCR4_MTYP_0                    0x00000004U        /*!<Bit 0 */\r\n#define  FMC_BCR4_MTYP_1                    0x00000008U        /*!<Bit 1 */\r\n#define  FMC_BCR4_MWID                      0x00000030U        /*!<MWID[1:0] bits (Memory data bus width) */\r\n#define  FMC_BCR4_MWID_0                    0x00000010U        /*!<Bit 0 */\r\n#define  FMC_BCR4_MWID_1                    0x00000020U        /*!<Bit 1 */\r\n#define  FMC_BCR4_FACCEN                    0x00000040U        /*!<Flash access enable        */\r\n#define  FMC_BCR4_BURSTEN                   0x00000100U        /*!<Burst enable bit           */\r\n#define  FMC_BCR4_WAITPOL                   0x00000200U        /*!<Wait signal polarity bit   */\r\n#define  FMC_BCR4_WRAPMOD                   0x00000400U        /*!<Wrapped burst mode support */\r\n#define  FMC_BCR4_WAITCFG                   0x00000800U        /*!<Wait timing configuration  */\r\n#define  FMC_BCR4_WREN                      0x00001000U        /*!<Write enable bit           */\r\n#define  FMC_BCR4_WAITEN                    0x00002000U        /*!<Wait enable bit            */\r\n#define  FMC_BCR4_EXTMOD                    0x00004000U        /*!<Extended mode enable       */\r\n#define  FMC_BCR4_ASYNCWAIT                 0x00008000U        /*!<Asynchronous wait          */\r\n#define  FMC_BCR4_CPSIZE                    0x00070000U        /*!<CRAM page size             */\r\n#define  FMC_BCR4_CPSIZE_0                  0x00010000U        /*!<Bit 0 */\r\n#define  FMC_BCR4_CPSIZE_1                  0x00020000U        /*!<Bit 1 */\r\n#define  FMC_BCR4_CPSIZE_2                  0x00040000U        /*!<Bit 2 */\r\n#define  FMC_BCR4_CBURSTRW                  0x00080000U        /*!<Write burst enable         */\r\n\r\n/******************  Bit definition for FMC_BTR1 register  ******************/\r\n#define  FMC_BTR1_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */\r\n#define  FMC_BTR1_ADDSET_0                  0x00000001U        /*!<Bit 0 */\r\n#define  FMC_BTR1_ADDSET_1                  0x00000002U        /*!<Bit 1 */\r\n#define  FMC_BTR1_ADDSET_2                  0x00000004U        /*!<Bit 2 */\r\n#define  FMC_BTR1_ADDSET_3                  0x00000008U        /*!<Bit 3 */\r\n#define  FMC_BTR1_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */\r\n#define  FMC_BTR1_ADDHLD_0                  0x00000010U        /*!<Bit 0 */\r\n#define  FMC_BTR1_ADDHLD_1                  0x00000020U        /*!<Bit 1 */\r\n#define  FMC_BTR1_ADDHLD_2                  0x00000040U        /*!<Bit 2 */\r\n#define  FMC_BTR1_ADDHLD_3                  0x00000080U        /*!<Bit 3 */\r\n#define  FMC_BTR1_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */\r\n#define  FMC_BTR1_DATAST_0                  0x00000100U        /*!<Bit 0 */\r\n#define  FMC_BTR1_DATAST_1                  0x00000200U        /*!<Bit 1 */\r\n#define  FMC_BTR1_DATAST_2                  0x00000400U        /*!<Bit 2 */\r\n#define  FMC_BTR1_DATAST_3                  0x00000800U        /*!<Bit 3 */\r\n#define  FMC_BTR1_DATAST_4                  0x00001000U        /*!<Bit 4 */\r\n#define  FMC_BTR1_DATAST_5                  0x00002000U        /*!<Bit 5 */\r\n#define  FMC_BTR1_DATAST_6                  0x00004000U        /*!<Bit 6 */\r\n#define  FMC_BTR1_DATAST_7                  0x00008000U        /*!<Bit 7 */\r\n#define  FMC_BTR1_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r\n#define  FMC_BTR1_BUSTURN_0                 0x00010000U        /*!<Bit 0 */\r\n#define  FMC_BTR1_BUSTURN_1                 0x00020000U        /*!<Bit 1 */\r\n#define  FMC_BTR1_BUSTURN_2                 0x00040000U        /*!<Bit 2 */\r\n#define  FMC_BTR1_BUSTURN_3                 0x00080000U        /*!<Bit 3 */\r\n#define  FMC_BTR1_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r\n#define  FMC_BTR1_CLKDIV_0                  0x00100000U        /*!<Bit 0 */\r\n#define  FMC_BTR1_CLKDIV_1                  0x00200000U        /*!<Bit 1 */\r\n#define  FMC_BTR1_CLKDIV_2                  0x00400000U        /*!<Bit 2 */\r\n#define  FMC_BTR1_CLKDIV_3                  0x00800000U        /*!<Bit 3 */\r\n#define  FMC_BTR1_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */\r\n#define  FMC_BTR1_DATLAT_0                  0x01000000U        /*!<Bit 0 */\r\n#define  FMC_BTR1_DATLAT_1                  0x02000000U        /*!<Bit 1 */\r\n#define  FMC_BTR1_DATLAT_2                  0x04000000U        /*!<Bit 2 */\r\n#define  FMC_BTR1_DATLAT_3                  0x08000000U        /*!<Bit 3 */\r\n#define  FMC_BTR1_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */\r\n#define  FMC_BTR1_ACCMOD_0                  0x10000000U        /*!<Bit 0 */\r\n#define  FMC_BTR1_ACCMOD_1                  0x20000000U        /*!<Bit 1 */\r\n\r\n/******************  Bit definition for FMC_BTR2 register  *******************/\r\n#define  FMC_BTR2_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */\r\n#define  FMC_BTR2_ADDSET_0                  0x00000001U        /*!<Bit 0 */\r\n#define  FMC_BTR2_ADDSET_1                  0x00000002U        /*!<Bit 1 */\r\n#define  FMC_BTR2_ADDSET_2                  0x00000004U        /*!<Bit 2 */\r\n#define  FMC_BTR2_ADDSET_3                  0x00000008U        /*!<Bit 3 */\r\n#define  FMC_BTR2_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r\n#define  FMC_BTR2_ADDHLD_0                  0x00000010U        /*!<Bit 0 */\r\n#define  FMC_BTR2_ADDHLD_1                  0x00000020U        /*!<Bit 1 */\r\n#define  FMC_BTR2_ADDHLD_2                  0x00000040U        /*!<Bit 2 */\r\n#define  FMC_BTR2_ADDHLD_3                  0x00000080U        /*!<Bit 3 */\r\n#define  FMC_BTR2_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */\r\n#define  FMC_BTR2_DATAST_0                  0x00000100U        /*!<Bit 0 */\r\n#define  FMC_BTR2_DATAST_1                  0x00000200U        /*!<Bit 1 */\r\n#define  FMC_BTR2_DATAST_2                  0x00000400U        /*!<Bit 2 */\r\n#define  FMC_BTR2_DATAST_3                  0x00000800U        /*!<Bit 3 */\r\n#define  FMC_BTR2_DATAST_4                  0x00001000U        /*!<Bit 4 */\r\n#define  FMC_BTR2_DATAST_5                  0x00002000U        /*!<Bit 5 */\r\n#define  FMC_BTR2_DATAST_6                  0x00004000U        /*!<Bit 6 */\r\n#define  FMC_BTR2_DATAST_7                  0x00008000U        /*!<Bit 7 */\r\n#define  FMC_BTR2_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r\n#define  FMC_BTR2_BUSTURN_0                 0x00010000U        /*!<Bit 0 */\r\n#define  FMC_BTR2_BUSTURN_1                 0x00020000U        /*!<Bit 1 */\r\n#define  FMC_BTR2_BUSTURN_2                 0x00040000U        /*!<Bit 2 */\r\n#define  FMC_BTR2_BUSTURN_3                 0x00080000U        /*!<Bit 3 */\r\n#define  FMC_BTR2_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r\n#define  FMC_BTR2_CLKDIV_0                  0x00100000U        /*!<Bit 0 */\r\n#define  FMC_BTR2_CLKDIV_1                  0x00200000U        /*!<Bit 1 */\r\n#define  FMC_BTR2_CLKDIV_2                  0x00400000U        /*!<Bit 2 */\r\n#define  FMC_BTR2_CLKDIV_3                  0x00800000U        /*!<Bit 3 */\r\n#define  FMC_BTR2_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */\r\n#define  FMC_BTR2_DATLAT_0                  0x01000000U        /*!<Bit 0 */\r\n#define  FMC_BTR2_DATLAT_1                  0x02000000U        /*!<Bit 1 */\r\n#define  FMC_BTR2_DATLAT_2                  0x04000000U        /*!<Bit 2 */\r\n#define  FMC_BTR2_DATLAT_3                  0x08000000U        /*!<Bit 3 */\r\n#define  FMC_BTR2_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */\r\n#define  FMC_BTR2_ACCMOD_0                  0x10000000U        /*!<Bit 0 */\r\n#define  FMC_BTR2_ACCMOD_1                  0x20000000U        /*!<Bit 1 */\r\n\r\n/*******************  Bit definition for FMC_BTR3 register  *******************/\r\n#define  FMC_BTR3_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */\r\n#define  FMC_BTR3_ADDSET_0                  0x00000001U        /*!<Bit 0 */\r\n#define  FMC_BTR3_ADDSET_1                  0x00000002U        /*!<Bit 1 */\r\n#define  FMC_BTR3_ADDSET_2                  0x00000004U        /*!<Bit 2 */\r\n#define  FMC_BTR3_ADDSET_3                  0x00000008U        /*!<Bit 3 */\r\n#define  FMC_BTR3_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r\n#define  FMC_BTR3_ADDHLD_0                  0x00000010U        /*!<Bit 0 */\r\n#define  FMC_BTR3_ADDHLD_1                  0x00000020U        /*!<Bit 1 */\r\n#define  FMC_BTR3_ADDHLD_2                  0x00000040U        /*!<Bit 2 */\r\n#define  FMC_BTR3_ADDHLD_3                  0x00000080U        /*!<Bit 3 */\r\n#define  FMC_BTR3_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */\r\n#define  FMC_BTR3_DATAST_0                  0x00000100U        /*!<Bit 0 */\r\n#define  FMC_BTR3_DATAST_1                  0x00000200U        /*!<Bit 1 */\r\n#define  FMC_BTR3_DATAST_2                  0x00000400U        /*!<Bit 2 */\r\n#define  FMC_BTR3_DATAST_3                  0x00000800U        /*!<Bit 3 */\r\n#define  FMC_BTR3_DATAST_4                  0x00001000U        /*!<Bit 4 */\r\n#define  FMC_BTR3_DATAST_5                  0x00002000U        /*!<Bit 5 */\r\n#define  FMC_BTR3_DATAST_6                  0x00004000U        /*!<Bit 6 */\r\n#define  FMC_BTR3_DATAST_7                  0x00008000U        /*!<Bit 7 */\r\n#define  FMC_BTR3_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r\n#define  FMC_BTR3_BUSTURN_0                 0x00010000U        /*!<Bit 0 */\r\n#define  FMC_BTR3_BUSTURN_1                 0x00020000U        /*!<Bit 1 */\r\n#define  FMC_BTR3_BUSTURN_2                 0x00040000U        /*!<Bit 2 */\r\n#define  FMC_BTR3_BUSTURN_3                 0x00080000U        /*!<Bit 3 */\r\n#define  FMC_BTR3_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r\n#define  FMC_BTR3_CLKDIV_0                  0x00100000U        /*!<Bit 0 */\r\n#define  FMC_BTR3_CLKDIV_1                  0x00200000U        /*!<Bit 1 */\r\n#define  FMC_BTR3_CLKDIV_2                  0x00400000U        /*!<Bit 2 */\r\n#define  FMC_BTR3_CLKDIV_3                  0x00800000U        /*!<Bit 3 */\r\n#define  FMC_BTR3_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */\r\n#define  FMC_BTR3_DATLAT_0                  0x01000000U        /*!<Bit 0 */\r\n#define  FMC_BTR3_DATLAT_1                  0x02000000U        /*!<Bit 1 */\r\n#define  FMC_BTR3_DATLAT_2                  0x04000000U        /*!<Bit 2 */\r\n#define  FMC_BTR3_DATLAT_3                  0x08000000U        /*!<Bit 3 */\r\n#define  FMC_BTR3_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */\r\n#define  FMC_BTR3_ACCMOD_0                  0x10000000U        /*!<Bit 0 */\r\n#define  FMC_BTR3_ACCMOD_1                  0x20000000U        /*!<Bit 1 */\r\n\r\n/******************  Bit definition for FMC_BTR4 register  *******************/\r\n#define  FMC_BTR4_ADDSET                    0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */\r\n#define  FMC_BTR4_ADDSET_0                  0x00000001U        /*!<Bit 0 */\r\n#define  FMC_BTR4_ADDSET_1                  0x00000002U        /*!<Bit 1 */\r\n#define  FMC_BTR4_ADDSET_2                  0x00000004U        /*!<Bit 2 */\r\n#define  FMC_BTR4_ADDSET_3                  0x00000008U        /*!<Bit 3 */\r\n#define  FMC_BTR4_ADDHLD                    0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r\n#define  FMC_BTR4_ADDHLD_0                  0x00000010U        /*!<Bit 0 */\r\n#define  FMC_BTR4_ADDHLD_1                  0x00000020U        /*!<Bit 1 */\r\n#define  FMC_BTR4_ADDHLD_2                  0x00000040U        /*!<Bit 2 */\r\n#define  FMC_BTR4_ADDHLD_3                  0x00000080U        /*!<Bit 3 */\r\n#define  FMC_BTR4_DATAST                    0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */\r\n#define  FMC_BTR4_DATAST_0                  0x00000100U        /*!<Bit 0 */\r\n#define  FMC_BTR4_DATAST_1                  0x00000200U        /*!<Bit 1 */\r\n#define  FMC_BTR4_DATAST_2                  0x00000400U        /*!<Bit 2 */\r\n#define  FMC_BTR4_DATAST_3                  0x00000800U        /*!<Bit 3 */\r\n#define  FMC_BTR4_DATAST_4                  0x00001000U        /*!<Bit 4 */\r\n#define  FMC_BTR4_DATAST_5                  0x00002000U        /*!<Bit 5 */\r\n#define  FMC_BTR4_DATAST_6                  0x00004000U        /*!<Bit 6 */\r\n#define  FMC_BTR4_DATAST_7                  0x00008000U        /*!<Bit 7 */\r\n#define  FMC_BTR4_BUSTURN                   0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r\n#define  FMC_BTR4_BUSTURN_0                 0x00010000U        /*!<Bit 0 */\r\n#define  FMC_BTR4_BUSTURN_1                 0x00020000U        /*!<Bit 1 */\r\n#define  FMC_BTR4_BUSTURN_2                 0x00040000U        /*!<Bit 2 */\r\n#define  FMC_BTR4_BUSTURN_3                 0x00080000U        /*!<Bit 3 */\r\n#define  FMC_BTR4_CLKDIV                    0x00F00000U        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r\n#define  FMC_BTR4_CLKDIV_0                  0x00100000U        /*!<Bit 0 */\r\n#define  FMC_BTR4_CLKDIV_1                  0x00200000U        /*!<Bit 1 */\r\n#define  FMC_BTR4_CLKDIV_2                  0x00400000U        /*!<Bit 2 */\r\n#define  FMC_BTR4_CLKDIV_3                  0x00800000U        /*!<Bit 3 */\r\n#define  FMC_BTR4_DATLAT                    0x0F000000U        /*!<DATLA[3:0] bits (Data latency) */\r\n#define  FMC_BTR4_DATLAT_0                  0x01000000U        /*!<Bit 0 */\r\n#define  FMC_BTR4_DATLAT_1                  0x02000000U        /*!<Bit 1 */\r\n#define  FMC_BTR4_DATLAT_2                  0x04000000U        /*!<Bit 2 */\r\n#define  FMC_BTR4_DATLAT_3                  0x08000000U        /*!<Bit 3 */\r\n#define  FMC_BTR4_ACCMOD                    0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */\r\n#define  FMC_BTR4_ACCMOD_0                  0x10000000U        /*!<Bit 0 */\r\n#define  FMC_BTR4_ACCMOD_1                  0x20000000U        /*!<Bit 1 */\r\n\r\n/******************  Bit definition for FMC_BWTR1 register  ******************/\r\n#define  FMC_BWTR1_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */\r\n#define  FMC_BWTR1_ADDSET_0                 0x00000001U        /*!<Bit 0 */\r\n#define  FMC_BWTR1_ADDSET_1                 0x00000002U        /*!<Bit 1 */\r\n#define  FMC_BWTR1_ADDSET_2                 0x00000004U        /*!<Bit 2 */\r\n#define  FMC_BWTR1_ADDSET_3                 0x00000008U        /*!<Bit 3 */\r\n#define  FMC_BWTR1_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r\n#define  FMC_BWTR1_ADDHLD_0                 0x00000010U        /*!<Bit 0 */\r\n#define  FMC_BWTR1_ADDHLD_1                 0x00000020U        /*!<Bit 1 */\r\n#define  FMC_BWTR1_ADDHLD_2                 0x00000040U        /*!<Bit 2 */\r\n#define  FMC_BWTR1_ADDHLD_3                 0x00000080U        /*!<Bit 3 */\r\n#define  FMC_BWTR1_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */\r\n#define  FMC_BWTR1_DATAST_0                 0x00000100U        /*!<Bit 0 */\r\n#define  FMC_BWTR1_DATAST_1                 0x00000200U        /*!<Bit 1 */\r\n#define  FMC_BWTR1_DATAST_2                 0x00000400U        /*!<Bit 2 */\r\n#define  FMC_BWTR1_DATAST_3                 0x00000800U        /*!<Bit 3 */\r\n#define  FMC_BWTR1_DATAST_4                 0x00001000U        /*!<Bit 4 */\r\n#define  FMC_BWTR1_DATAST_5                 0x00002000U        /*!<Bit 5 */\r\n#define  FMC_BWTR1_DATAST_6                 0x00004000U        /*!<Bit 6 */\r\n#define  FMC_BWTR1_DATAST_7                 0x00008000U        /*!<Bit 7 */\r\n#define  FMC_BWTR1_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r\n#define  FMC_BWTR1_BUSTURN_0                0x00010000U        /*!<Bit 0 */\r\n#define  FMC_BWTR1_BUSTURN_1                0x00020000U        /*!<Bit 1 */\r\n#define  FMC_BWTR1_BUSTURN_2                0x00040000U        /*!<Bit 2 */\r\n#define  FMC_BWTR1_BUSTURN_3                0x00080000U        /*!<Bit 3 */\r\n#define  FMC_BWTR1_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */\r\n#define  FMC_BWTR1_ACCMOD_0                 0x10000000U        /*!<Bit 0 */\r\n#define  FMC_BWTR1_ACCMOD_1                 0x20000000U        /*!<Bit 1 */\r\n\r\n/******************  Bit definition for FMC_BWTR2 register  ******************/\r\n#define  FMC_BWTR2_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */\r\n#define  FMC_BWTR2_ADDSET_0                 0x00000001U        /*!<Bit 0 */\r\n#define  FMC_BWTR2_ADDSET_1                 0x00000002U        /*!<Bit 1 */\r\n#define  FMC_BWTR2_ADDSET_2                 0x00000004U        /*!<Bit 2 */\r\n#define  FMC_BWTR2_ADDSET_3                 0x00000008U        /*!<Bit 3 */\r\n#define  FMC_BWTR2_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r\n#define  FMC_BWTR2_ADDHLD_0                 0x00000010U        /*!<Bit 0 */\r\n#define  FMC_BWTR2_ADDHLD_1                 0x00000020U        /*!<Bit 1 */\r\n#define  FMC_BWTR2_ADDHLD_2                 0x00000040U        /*!<Bit 2 */\r\n#define  FMC_BWTR2_ADDHLD_3                 0x00000080U        /*!<Bit 3 */\r\n#define  FMC_BWTR2_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */\r\n#define  FMC_BWTR2_DATAST_0                 0x00000100U        /*!<Bit 0 */\r\n#define  FMC_BWTR2_DATAST_1                 0x00000200U        /*!<Bit 1 */\r\n#define  FMC_BWTR2_DATAST_2                 0x00000400U        /*!<Bit 2 */\r\n#define  FMC_BWTR2_DATAST_3                 0x00000800U        /*!<Bit 3 */\r\n#define  FMC_BWTR2_DATAST_4                 0x00001000U        /*!<Bit 4 */\r\n#define  FMC_BWTR2_DATAST_5                 0x00002000U        /*!<Bit 5 */\r\n#define  FMC_BWTR2_DATAST_6                 0x00004000U        /*!<Bit 6 */\r\n#define  FMC_BWTR2_DATAST_7                 0x00008000U        /*!<Bit 7 */\r\n#define  FMC_BWTR2_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r\n#define  FMC_BWTR2_BUSTURN_0                0x00010000U        /*!<Bit 0 */\r\n#define  FMC_BWTR2_BUSTURN_1                0x00020000U        /*!<Bit 1 */\r\n#define  FMC_BWTR2_BUSTURN_2                0x00040000U        /*!<Bit 2 */\r\n#define  FMC_BWTR2_BUSTURN_3                0x00080000U        /*!<Bit 3 */\r\n#define  FMC_BWTR2_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */\r\n#define  FMC_BWTR2_ACCMOD_0                 0x10000000U        /*!<Bit 0 */\r\n#define  FMC_BWTR2_ACCMOD_1                 0x20000000U        /*!<Bit 1 */\r\n\r\n/******************  Bit definition for FMC_BWTR3 register  ******************/\r\n#define  FMC_BWTR3_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */\r\n#define  FMC_BWTR3_ADDSET_0                 0x00000001U        /*!<Bit 0 */\r\n#define  FMC_BWTR3_ADDSET_1                 0x00000002U        /*!<Bit 1 */\r\n#define  FMC_BWTR3_ADDSET_2                 0x00000004U        /*!<Bit 2 */\r\n#define  FMC_BWTR3_ADDSET_3                 0x00000008U        /*!<Bit 3 */\r\n#define  FMC_BWTR3_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r\n#define  FMC_BWTR3_ADDHLD_0                 0x00000010U        /*!<Bit 0 */\r\n#define  FMC_BWTR3_ADDHLD_1                 0x00000020U        /*!<Bit 1 */\r\n#define  FMC_BWTR3_ADDHLD_2                 0x00000040U        /*!<Bit 2 */\r\n#define  FMC_BWTR3_ADDHLD_3                 0x00000080U        /*!<Bit 3 */\r\n#define  FMC_BWTR3_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */\r\n#define  FMC_BWTR3_DATAST_0                 0x00000100U        /*!<Bit 0 */\r\n#define  FMC_BWTR3_DATAST_1                 0x00000200U        /*!<Bit 1 */\r\n#define  FMC_BWTR3_DATAST_2                 0x00000400U        /*!<Bit 2 */\r\n#define  FMC_BWTR3_DATAST_3                 0x00000800U        /*!<Bit 3 */\r\n#define  FMC_BWTR3_DATAST_4                 0x00001000U        /*!<Bit 4 */\r\n#define  FMC_BWTR3_DATAST_5                 0x00002000U        /*!<Bit 5 */\r\n#define  FMC_BWTR3_DATAST_6                 0x00004000U        /*!<Bit 6 */\r\n#define  FMC_BWTR3_DATAST_7                 0x00008000U        /*!<Bit 7 */\r\n#define  FMC_BWTR3_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r\n#define  FMC_BWTR3_BUSTURN_0                0x00010000U        /*!<Bit 0 */\r\n#define  FMC_BWTR3_BUSTURN_1                0x00020000U        /*!<Bit 1 */\r\n#define  FMC_BWTR3_BUSTURN_2                0x00040000U        /*!<Bit 2 */\r\n#define  FMC_BWTR3_BUSTURN_3                0x00080000U        /*!<Bit 3 */\r\n#define  FMC_BWTR3_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */\r\n#define  FMC_BWTR3_ACCMOD_0                 0x10000000U        /*!<Bit 0 */\r\n#define  FMC_BWTR3_ACCMOD_1                 0x20000000U        /*!<Bit 1 */\r\n\r\n/******************  Bit definition for FMC_BWTR4 register  ******************/\r\n#define  FMC_BWTR4_ADDSET                   0x0000000FU        /*!<ADDSET[3:0] bits (Address setup phase duration) */\r\n#define  FMC_BWTR4_ADDSET_0                 0x00000001U        /*!<Bit 0 */\r\n#define  FMC_BWTR4_ADDSET_1                 0x00000002U        /*!<Bit 1 */\r\n#define  FMC_BWTR4_ADDSET_2                 0x00000004U        /*!<Bit 2 */\r\n#define  FMC_BWTR4_ADDSET_3                 0x00000008U        /*!<Bit 3 */\r\n#define  FMC_BWTR4_ADDHLD                   0x000000F0U        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r\n#define  FMC_BWTR4_ADDHLD_0                 0x00000010U        /*!<Bit 0 */\r\n#define  FMC_BWTR4_ADDHLD_1                 0x00000020U        /*!<Bit 1 */\r\n#define  FMC_BWTR4_ADDHLD_2                 0x00000040U        /*!<Bit 2 */\r\n#define  FMC_BWTR4_ADDHLD_3                 0x00000080U        /*!<Bit 3 */\r\n#define  FMC_BWTR4_DATAST                   0x0000FF00U        /*!<DATAST [3:0] bits (Data-phase duration) */\r\n#define  FMC_BWTR4_DATAST_0                 0x00000100U        /*!<Bit 0 */\r\n#define  FMC_BWTR4_DATAST_1                 0x00000200U        /*!<Bit 1 */\r\n#define  FMC_BWTR4_DATAST_2                 0x00000400U        /*!<Bit 2 */\r\n#define  FMC_BWTR4_DATAST_3                 0x00000800U        /*!<Bit 3 */\r\n#define  FMC_BWTR4_DATAST_4                 0x00001000U        /*!<Bit 4 */\r\n#define  FMC_BWTR4_DATAST_5                 0x00002000U        /*!<Bit 5 */\r\n#define  FMC_BWTR4_DATAST_6                 0x00004000U        /*!<Bit 6 */\r\n#define  FMC_BWTR4_DATAST_7                 0x00008000U        /*!<Bit 7 */\r\n#define  FMC_BWTR4_BUSTURN                  0x000F0000U        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r\n#define  FMC_BWTR4_BUSTURN_0                0x00010000U        /*!<Bit 0 */\r\n#define  FMC_BWTR4_BUSTURN_1                0x00020000U        /*!<Bit 1 */\r\n#define  FMC_BWTR4_BUSTURN_2                0x00040000U        /*!<Bit 2 */\r\n#define  FMC_BWTR4_BUSTURN_3                0x00080000U        /*!<Bit 3 */\r\n#define  FMC_BWTR4_ACCMOD                   0x30000000U        /*!<ACCMOD[1:0] bits (Access mode) */\r\n#define  FMC_BWTR4_ACCMOD_0                 0x10000000U        /*!<Bit 0 */\r\n#define  FMC_BWTR4_ACCMOD_1                 0x20000000U        /*!<Bit 1 */\r\n\r\n/******************  Bit definition for FMC_PCR register  *******************/\r\n#define  FMC_PCR_PWAITEN                   0x00000002U        /*!<Wait feature enable bit                   */\r\n#define  FMC_PCR_PBKEN                     0x00000004U        /*!<PC Card/NAND Flash memory bank enable bit */\r\n#define  FMC_PCR_PTYP                      0x00000008U        /*!<Memory type                               */\r\n#define  FMC_PCR_PWID                      0x00000030U        /*!<PWID[1:0] bits (NAND Flash databus width) */\r\n#define  FMC_PCR_PWID_0                    0x00000010U        /*!<Bit 0 */\r\n#define  FMC_PCR_PWID_1                    0x00000020U        /*!<Bit 1 */\r\n#define  FMC_PCR_ECCEN                     0x00000040U        /*!<ECC computation logic enable bit          */\r\n#define  FMC_PCR_TCLR                      0x00001E00U        /*!<TCLR[3:0] bits (CLE to RE delay)          */\r\n#define  FMC_PCR_TCLR_0                    0x00000200U        /*!<Bit 0 */\r\n#define  FMC_PCR_TCLR_1                    0x00000400U        /*!<Bit 1 */\r\n#define  FMC_PCR_TCLR_2                    0x00000800U        /*!<Bit 2 */\r\n#define  FMC_PCR_TCLR_3                    0x00001000U        /*!<Bit 3 */\r\n#define  FMC_PCR_TAR                       0x0001E000U        /*!<TAR[3:0] bits (ALE to RE delay)           */\r\n#define  FMC_PCR_TAR_0                     0x00002000U        /*!<Bit 0 */\r\n#define  FMC_PCR_TAR_1                     0x00004000U        /*!<Bit 1 */\r\n#define  FMC_PCR_TAR_2                     0x00008000U        /*!<Bit 2 */\r\n#define  FMC_PCR_TAR_3                     0x00010000U        /*!<Bit 3 */\r\n#define  FMC_PCR_ECCPS                     0x000E0000U        /*!<ECCPS[2:0] bits (ECC page size)           */\r\n#define  FMC_PCR_ECCPS_0                   0x00020000U        /*!<Bit 0 */\r\n#define  FMC_PCR_ECCPS_1                   0x00040000U        /*!<Bit 1 */\r\n#define  FMC_PCR_ECCPS_2                   0x00080000U        /*!<Bit 2 */\r\n\r\n/*******************  Bit definition for FMC_SR register  *******************/\r\n#define  FMC_SR_IRS                        0x01U              /*!<Interrupt Rising Edge status                */\r\n#define  FMC_SR_ILS                        0x02U              /*!<Interrupt Level status                      */\r\n#define  FMC_SR_IFS                        0x04U              /*!<Interrupt Falling Edge status               */\r\n#define  FMC_SR_IREN                       0x08U              /*!<Interrupt Rising Edge detection Enable bit  */\r\n#define  FMC_SR_ILEN                       0x10U              /*!<Interrupt Level detection Enable bit        */\r\n#define  FMC_SR_IFEN                       0x20U              /*!<Interrupt Falling Edge detection Enable bit */\r\n#define  FMC_SR_FEMPT                      0x40U              /*!<FIFO empty                                  */\r\n\r\n/******************  Bit definition for FMC_PMEM register  ******************/\r\n#define  FMC_PMEM_MEMSET3                  0x000000FFU        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */\r\n#define  FMC_PMEM_MEMSET3_0                0x00000001U        /*!<Bit 0 */\r\n#define  FMC_PMEM_MEMSET3_1                0x00000002U        /*!<Bit 1 */\r\n#define  FMC_PMEM_MEMSET3_2                0x00000004U        /*!<Bit 2 */\r\n#define  FMC_PMEM_MEMSET3_3                0x00000008U        /*!<Bit 3 */\r\n#define  FMC_PMEM_MEMSET3_4                0x00000010U        /*!<Bit 4 */\r\n#define  FMC_PMEM_MEMSET3_5                0x00000020U        /*!<Bit 5 */\r\n#define  FMC_PMEM_MEMSET3_6                0x00000040U        /*!<Bit 6 */\r\n#define  FMC_PMEM_MEMSET3_7                0x00000080U        /*!<Bit 7 */\r\n#define  FMC_PMEM_MEMWAIT3                 0x0000FF00U        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */\r\n#define  FMC_PMEM_MEMWAIT3_0               0x00000100U        /*!<Bit 0 */\r\n#define  FMC_PMEM_MEMWAIT3_1               0x00000200U        /*!<Bit 1 */\r\n#define  FMC_PMEM_MEMWAIT3_2               0x00000400U        /*!<Bit 2 */\r\n#define  FMC_PMEM_MEMWAIT3_3               0x00000800U        /*!<Bit 3 */\r\n#define  FMC_PMEM_MEMWAIT3_4               0x00001000U        /*!<Bit 4 */\r\n#define  FMC_PMEM_MEMWAIT3_5               0x00002000U        /*!<Bit 5 */\r\n#define  FMC_PMEM_MEMWAIT3_6               0x00004000U        /*!<Bit 6 */\r\n#define  FMC_PMEM_MEMWAIT3_7               0x00008000U        /*!<Bit 7 */\r\n#define  FMC_PMEM_MEMHOLD3                 0x00FF0000U        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */\r\n#define  FMC_PMEM_MEMHOLD3_0               0x00010000U        /*!<Bit 0 */\r\n#define  FMC_PMEM_MEMHOLD3_1               0x00020000U        /*!<Bit 1 */\r\n#define  FMC_PMEM_MEMHOLD3_2               0x00040000U        /*!<Bit 2 */\r\n#define  FMC_PMEM_MEMHOLD3_3               0x00080000U        /*!<Bit 3 */\r\n#define  FMC_PMEM_MEMHOLD3_4               0x00100000U        /*!<Bit 4 */\r\n#define  FMC_PMEM_MEMHOLD3_5               0x00200000U        /*!<Bit 5 */\r\n#define  FMC_PMEM_MEMHOLD3_6               0x00400000U        /*!<Bit 6 */\r\n#define  FMC_PMEM_MEMHOLD3_7               0x00800000U        /*!<Bit 7 */\r\n#define  FMC_PMEM_MEMHIZ3                  0xFF000000U        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */\r\n#define  FMC_PMEM_MEMHIZ3_0                0x01000000U        /*!<Bit 0 */\r\n#define  FMC_PMEM_MEMHIZ3_1                0x02000000U        /*!<Bit 1 */\r\n#define  FMC_PMEM_MEMHIZ3_2                0x04000000U        /*!<Bit 2 */\r\n#define  FMC_PMEM_MEMHIZ3_3                0x08000000U        /*!<Bit 3 */\r\n#define  FMC_PMEM_MEMHIZ3_4                0x10000000U        /*!<Bit 4 */\r\n#define  FMC_PMEM_MEMHIZ3_5                0x20000000U        /*!<Bit 5 */\r\n#define  FMC_PMEM_MEMHIZ3_6                0x40000000U        /*!<Bit 6 */\r\n#define  FMC_PMEM_MEMHIZ3_7                0x80000000U        /*!<Bit 7 */\r\n\r\n/******************  Bit definition for FMC_PATT register  ******************/\r\n#define  FMC_PATT_ATTSET3                  0x000000FFU        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */\r\n#define  FMC_PATT_ATTSET3_0                0x00000001U        /*!<Bit 0 */\r\n#define  FMC_PATT_ATTSET3_1                0x00000002U        /*!<Bit 1 */\r\n#define  FMC_PATT_ATTSET3_2                0x00000004U        /*!<Bit 2 */\r\n#define  FMC_PATT_ATTSET3_3                0x00000008U        /*!<Bit 3 */\r\n#define  FMC_PATT_ATTSET3_4                0x00000010U        /*!<Bit 4 */\r\n#define  FMC_PATT_ATTSET3_5                0x00000020U        /*!<Bit 5 */\r\n#define  FMC_PATT_ATTSET3_6                0x00000040U        /*!<Bit 6 */\r\n#define  FMC_PATT_ATTSET3_7                0x00000080U        /*!<Bit 7 */\r\n#define  FMC_PATT_ATTWAIT3                 0x0000FF00U        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */\r\n#define  FMC_PATT_ATTWAIT3_0               0x00000100U        /*!<Bit 0 */\r\n#define  FMC_PATT_ATTWAIT3_1               0x00000200U        /*!<Bit 1 */\r\n#define  FMC_PATT_ATTWAIT3_2               0x00000400U        /*!<Bit 2 */\r\n#define  FMC_PATT_ATTWAIT3_3               0x00000800U        /*!<Bit 3 */\r\n#define  FMC_PATT_ATTWAIT3_4               0x00001000U        /*!<Bit 4 */\r\n#define  FMC_PATT_ATTWAIT3_5               0x00002000U        /*!<Bit 5 */\r\n#define  FMC_PATT_ATTWAIT3_6               0x00004000U        /*!<Bit 6 */\r\n#define  FMC_PATT_ATTWAIT3_7               0x00008000U        /*!<Bit 7 */\r\n#define  FMC_PATT_ATTHOLD3                 0x00FF0000U        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */\r\n#define  FMC_PATT_ATTHOLD3_0               0x00010000U        /*!<Bit 0 */\r\n#define  FMC_PATT_ATTHOLD3_1               0x00020000U        /*!<Bit 1 */\r\n#define  FMC_PATT_ATTHOLD3_2               0x00040000U        /*!<Bit 2 */\r\n#define  FMC_PATT_ATTHOLD3_3               0x00080000U        /*!<Bit 3 */\r\n#define  FMC_PATT_ATTHOLD3_4               0x00100000U        /*!<Bit 4 */\r\n#define  FMC_PATT_ATTHOLD3_5               0x00200000U        /*!<Bit 5 */\r\n#define  FMC_PATT_ATTHOLD3_6               0x00400000U        /*!<Bit 6 */\r\n#define  FMC_PATT_ATTHOLD3_7               0x00800000U        /*!<Bit 7 */\r\n#define  FMC_PATT_ATTHIZ3                  0xFF000000U        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */\r\n#define  FMC_PATT_ATTHIZ3_0                0x01000000U        /*!<Bit 0 */\r\n#define  FMC_PATT_ATTHIZ3_1                0x02000000U        /*!<Bit 1 */\r\n#define  FMC_PATT_ATTHIZ3_2                0x04000000U        /*!<Bit 2 */\r\n#define  FMC_PATT_ATTHIZ3_3                0x08000000U        /*!<Bit 3 */\r\n#define  FMC_PATT_ATTHIZ3_4                0x10000000U        /*!<Bit 4 */\r\n#define  FMC_PATT_ATTHIZ3_5                0x20000000U        /*!<Bit 5 */\r\n#define  FMC_PATT_ATTHIZ3_6                0x40000000U        /*!<Bit 6 */\r\n#define  FMC_PATT_ATTHIZ3_7                0x80000000U        /*!<Bit 7 */\r\n\r\n/******************  Bit definition for FMC_ECCR register  ******************/\r\n#define  FMC_ECCR_ECC3                     0xFFFFFFFFU        /*!<ECC result */\r\n\r\n/******************  Bit definition for FMC_SDCR1 register  ******************/\r\n#define  FMC_SDCR1_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */\r\n#define  FMC_SDCR1_NC_0                     0x00000001U        /*!<Bit 0 */\r\n#define  FMC_SDCR1_NC_1                     0x00000002U        /*!<Bit 1 */\r\n#define  FMC_SDCR1_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */\r\n#define  FMC_SDCR1_NR_0                     0x00000004U        /*!<Bit 0 */\r\n#define  FMC_SDCR1_NR_1                     0x00000008U        /*!<Bit 1 */\r\n#define  FMC_SDCR1_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */\r\n#define  FMC_SDCR1_MWID_0                   0x00000010U        /*!<Bit 0 */\r\n#define  FMC_SDCR1_MWID_1                   0x00000020U        /*!<Bit 1 */\r\n#define  FMC_SDCR1_NB                       0x00000040U        /*!<Number of internal bank */\r\n#define  FMC_SDCR1_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */\r\n#define  FMC_SDCR1_CAS_0                    0x00000080U        /*!<Bit 0 */\r\n#define  FMC_SDCR1_CAS_1                    0x00000100U        /*!<Bit 1 */\r\n#define  FMC_SDCR1_WP                       0x00000200U        /*!<Write protection */\r\n#define  FMC_SDCR1_SDCLK                    0x00000C00U        /*!<SDRAM clock configuration */\r\n#define  FMC_SDCR1_SDCLK_0                  0x00000400U        /*!<Bit 0 */\r\n#define  FMC_SDCR1_SDCLK_1                  0x00000800U        /*!<Bit 1 */\r\n#define  FMC_SDCR1_RBURST                   0x00001000U        /*!<Read burst */\r\n#define  FMC_SDCR1_RPIPE                    0x00006000U        /*!<Write protection */\r\n#define  FMC_SDCR1_RPIPE_0                  0x00002000U        /*!<Bit 0 */\r\n#define  FMC_SDCR1_RPIPE_1                  0x00004000U        /*!<Bit 1 */\r\n\r\n/******************  Bit definition for FMC_SDCR2 register  ******************/\r\n#define  FMC_SDCR2_NC                       0x00000003U        /*!<NC[1:0] bits (Number of column bits) */\r\n#define  FMC_SDCR2_NC_0                     0x00000001U        /*!<Bit 0 */\r\n#define  FMC_SDCR2_NC_1                     0x00000002U        /*!<Bit 1 */\r\n#define  FMC_SDCR2_NR                       0x0000000CU        /*!<NR[1:0] bits (Number of row bits) */\r\n#define  FMC_SDCR2_NR_0                     0x00000004U        /*!<Bit 0 */\r\n#define  FMC_SDCR2_NR_1                     0x00000008U        /*!<Bit 1 */\r\n#define  FMC_SDCR2_MWID                     0x00000030U        /*!<NR[1:0] bits (Number of row bits) */\r\n#define  FMC_SDCR2_MWID_0                   0x00000010U        /*!<Bit 0 */\r\n#define  FMC_SDCR2_MWID_1                   0x00000020U        /*!<Bit 1 */\r\n#define  FMC_SDCR2_NB                       0x00000040U        /*!<Number of internal bank */\r\n#define  FMC_SDCR2_CAS                      0x00000180U        /*!<CAS[1:0] bits (CAS latency) */\r\n#define  FMC_SDCR2_CAS_0                    0x00000080U        /*!<Bit 0 */\r\n#define  FMC_SDCR2_CAS_1                    0x00000100U        /*!<Bit 1 */\r\n#define  FMC_SDCR2_WP                       0x00000200U        /*!<Write protection */\r\n#define  FMC_SDCR2_SDCLK                    0x00000C00U        /*!<SDCLK[1:0] (SDRAM clock configuration) */\r\n#define  FMC_SDCR2_SDCLK_0                  0x00000400U        /*!<Bit 0 */\r\n#define  FMC_SDCR2_SDCLK_1                  0x00000800U        /*!<Bit 1 */\r\n#define  FMC_SDCR2_RBURST                   0x00001000U        /*!<Read burst */\r\n#define  FMC_SDCR2_RPIPE                    0x00006000U        /*!<RPIPE[1:0](Read pipe) */\r\n#define  FMC_SDCR2_RPIPE_0                  0x00002000U        /*!<Bit 0 */\r\n#define  FMC_SDCR2_RPIPE_1                  0x00004000U        /*!<Bit 1 */\r\n\r\n/******************  Bit definition for FMC_SDTR1 register  ******************/\r\n#define  FMC_SDTR1_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */\r\n#define  FMC_SDTR1_TMRD_0                   0x00000001U        /*!<Bit 0 */\r\n#define  FMC_SDTR1_TMRD_1                   0x00000002U        /*!<Bit 1 */\r\n#define  FMC_SDTR1_TMRD_2                   0x00000004U        /*!<Bit 2 */\r\n#define  FMC_SDTR1_TMRD_3                   0x00000008U        /*!<Bit 3 */\r\n#define  FMC_SDTR1_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */\r\n#define  FMC_SDTR1_TXSR_0                   0x00000010U        /*!<Bit 0 */\r\n#define  FMC_SDTR1_TXSR_1                   0x00000020U        /*!<Bit 1 */\r\n#define  FMC_SDTR1_TXSR_2                   0x00000040U        /*!<Bit 2 */\r\n#define  FMC_SDTR1_TXSR_3                   0x00000080U        /*!<Bit 3 */\r\n#define  FMC_SDTR1_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */\r\n#define  FMC_SDTR1_TRAS_0                   0x00000100U        /*!<Bit 0 */\r\n#define  FMC_SDTR1_TRAS_1                   0x00000200U        /*!<Bit 1 */\r\n#define  FMC_SDTR1_TRAS_2                   0x00000400U        /*!<Bit 2 */\r\n#define  FMC_SDTR1_TRAS_3                   0x00000800U        /*!<Bit 3 */\r\n#define  FMC_SDTR1_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */\r\n#define  FMC_SDTR1_TRC_0                    0x00001000U        /*!<Bit 0 */\r\n#define  FMC_SDTR1_TRC_1                    0x00002000U        /*!<Bit 1 */\r\n#define  FMC_SDTR1_TRC_2                    0x00004000U        /*!<Bit 2 */\r\n#define  FMC_SDTR1_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */\r\n#define  FMC_SDTR1_TWR_0                    0x00010000U        /*!<Bit 0 */\r\n#define  FMC_SDTR1_TWR_1                    0x00020000U        /*!<Bit 1 */\r\n#define  FMC_SDTR1_TWR_2                    0x00040000U        /*!<Bit 2 */\r\n#define  FMC_SDTR1_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */\r\n#define  FMC_SDTR1_TRP_0                    0x00100000U        /*!<Bit 0 */\r\n#define  FMC_SDTR1_TRP_1                    0x00200000U        /*!<Bit 1 */\r\n#define  FMC_SDTR1_TRP_2                    0x00400000U        /*!<Bit 2 */\r\n#define  FMC_SDTR1_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */\r\n#define  FMC_SDTR1_TRCD_0                   0x01000000U        /*!<Bit 0 */\r\n#define  FMC_SDTR1_TRCD_1                   0x02000000U        /*!<Bit 1 */\r\n#define  FMC_SDTR1_TRCD_2                   0x04000000U        /*!<Bit 2 */\r\n\r\n/******************  Bit definition for FMC_SDTR2 register  ******************/\r\n#define  FMC_SDTR2_TMRD                     0x0000000FU        /*!<TMRD[3:0] bits (Load mode register to active) */\r\n#define  FMC_SDTR2_TMRD_0                   0x00000001U        /*!<Bit 0 */\r\n#define  FMC_SDTR2_TMRD_1                   0x00000002U        /*!<Bit 1 */\r\n#define  FMC_SDTR2_TMRD_2                   0x00000004U        /*!<Bit 2 */\r\n#define  FMC_SDTR2_TMRD_3                   0x00000008U        /*!<Bit 3 */\r\n#define  FMC_SDTR2_TXSR                     0x000000F0U        /*!<TXSR[3:0] bits (Exit self refresh) */\r\n#define  FMC_SDTR2_TXSR_0                   0x00000010U        /*!<Bit 0 */\r\n#define  FMC_SDTR2_TXSR_1                   0x00000020U        /*!<Bit 1 */\r\n#define  FMC_SDTR2_TXSR_2                   0x00000040U        /*!<Bit 2 */\r\n#define  FMC_SDTR2_TXSR_3                   0x00000080U        /*!<Bit 3 */\r\n#define  FMC_SDTR2_TRAS                     0x00000F00U        /*!<TRAS[3:0] bits (Self refresh time) */\r\n#define  FMC_SDTR2_TRAS_0                   0x00000100U        /*!<Bit 0 */\r\n#define  FMC_SDTR2_TRAS_1                   0x00000200U        /*!<Bit 1 */\r\n#define  FMC_SDTR2_TRAS_2                   0x00000400U        /*!<Bit 2 */\r\n#define  FMC_SDTR2_TRAS_3                   0x00000800U        /*!<Bit 3 */\r\n#define  FMC_SDTR2_TRC                      0x0000F000U        /*!<TRC[2:0] bits (Row cycle delay) */\r\n#define  FMC_SDTR2_TRC_0                    0x00001000U        /*!<Bit 0 */\r\n#define  FMC_SDTR2_TRC_1                    0x00002000U        /*!<Bit 1 */\r\n#define  FMC_SDTR2_TRC_2                    0x00004000U        /*!<Bit 2 */\r\n#define  FMC_SDTR2_TWR                      0x000F0000U        /*!<TRC[2:0] bits (Write recovery delay) */\r\n#define  FMC_SDTR2_TWR_0                    0x00010000U        /*!<Bit 0 */\r\n#define  FMC_SDTR2_TWR_1                    0x00020000U        /*!<Bit 1 */\r\n#define  FMC_SDTR2_TWR_2                    0x00040000U        /*!<Bit 2 */\r\n#define  FMC_SDTR2_TRP                      0x00F00000U        /*!<TRP[2:0] bits (Row precharge delay) */\r\n#define  FMC_SDTR2_TRP_0                    0x00100000U        /*!<Bit 0 */\r\n#define  FMC_SDTR2_TRP_1                    0x00200000U        /*!<Bit 1 */\r\n#define  FMC_SDTR2_TRP_2                    0x00400000U        /*!<Bit 2 */\r\n#define  FMC_SDTR2_TRCD                     0x0F000000U        /*!<TRP[2:0] bits (Row to column delay) */\r\n#define  FMC_SDTR2_TRCD_0                   0x01000000U        /*!<Bit 0 */\r\n#define  FMC_SDTR2_TRCD_1                   0x02000000U        /*!<Bit 1 */\r\n#define  FMC_SDTR2_TRCD_2                   0x04000000U        /*!<Bit 2 */\r\n\r\n/******************  Bit definition for FMC_SDCMR register  ******************/\r\n#define  FMC_SDCMR_MODE                     0x00000007U        /*!<MODE[2:0] bits (Command mode) */\r\n#define  FMC_SDCMR_MODE_0                   0x00000001U        /*!<Bit 0 */\r\n#define  FMC_SDCMR_MODE_1                   0x00000002U        /*!<Bit 1 */\r\n#define  FMC_SDCMR_MODE_2                   0x00000003U        /*!<Bit 2 */\r\n#define  FMC_SDCMR_CTB2                     0x00000008U        /*!<Command target 2 */\r\n#define  FMC_SDCMR_CTB1                     0x00000010U        /*!<Command target 1 */\r\n#define  FMC_SDCMR_NRFS                     0x000001E0U        /*!<NRFS[3:0] bits (Number of auto-refresh) */\r\n#define  FMC_SDCMR_NRFS_0                   0x00000020U        /*!<Bit 0 */\r\n#define  FMC_SDCMR_NRFS_1                   0x00000040U        /*!<Bit 1 */\r\n#define  FMC_SDCMR_NRFS_2                   0x00000080U        /*!<Bit 2 */\r\n#define  FMC_SDCMR_NRFS_3                   0x00000100U        /*!<Bit 3 */\r\n#define  FMC_SDCMR_MRD                      0x003FFE00U        /*!<MRD[12:0] bits (Mode register definition) */\r\n\r\n/******************  Bit definition for FMC_SDRTR register  ******************/\r\n#define  FMC_SDRTR_CRE                      0x00000001U        /*!<Clear refresh error flag */\r\n#define  FMC_SDRTR_COUNT                    0x00003FFEU        /*!<COUNT[12:0] bits (Refresh timer count) */\r\n#define  FMC_SDRTR_REIE                     0x00004000U        /*!<RES interupt enable */\r\n\r\n/******************  Bit definition for FMC_SDSR register  ******************/\r\n#define  FMC_SDSR_RE                        0x00000001U        /*!<Refresh error flag */\r\n#define  FMC_SDSR_MODES1                    0x00000006U        /*!<MODES1[1:0]bits (Status mode for bank 1) */\r\n#define  FMC_SDSR_MODES1_0                  0x00000002U        /*!<Bit 0 */\r\n#define  FMC_SDSR_MODES1_1                  0x00000004U        /*!<Bit 1 */\r\n#define  FMC_SDSR_MODES2                    0x00000018U        /*!<MODES2[1:0]bits (Status mode for bank 2) */\r\n#define  FMC_SDSR_MODES2_0                  0x00000008U        /*!<Bit 0 */\r\n#define  FMC_SDSR_MODES2_1                  0x00000010U        /*!<Bit 1 */\r\n#define  FMC_SDSR_BUSY                      0x00000020U        /*!<Busy status */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                            General Purpose I/O                             */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/******************  Bits definition for GPIO_MODER register  *****************/\r\n#define GPIO_MODER_MODER0                    0x00000003U\r\n#define GPIO_MODER_MODER0_0                  0x00000001U\r\n#define GPIO_MODER_MODER0_1                  0x00000002U\r\n#define GPIO_MODER_MODER1                    0x0000000CU\r\n#define GPIO_MODER_MODER1_0                  0x00000004U\r\n#define GPIO_MODER_MODER1_1                  0x00000008U\r\n#define GPIO_MODER_MODER2                    0x00000030U\r\n#define GPIO_MODER_MODER2_0                  0x00000010U\r\n#define GPIO_MODER_MODER2_1                  0x00000020U\r\n#define GPIO_MODER_MODER3                    0x000000C0U\r\n#define GPIO_MODER_MODER3_0                  0x00000040U\r\n#define GPIO_MODER_MODER3_1                  0x00000080U\r\n#define GPIO_MODER_MODER4                    0x00000300U\r\n#define GPIO_MODER_MODER4_0                  0x00000100U\r\n#define GPIO_MODER_MODER4_1                  0x00000200U\r\n#define GPIO_MODER_MODER5                    0x00000C00U\r\n#define GPIO_MODER_MODER5_0                  0x00000400U\r\n#define GPIO_MODER_MODER5_1                  0x00000800U\r\n#define GPIO_MODER_MODER6                    0x00003000U\r\n#define GPIO_MODER_MODER6_0                  0x00001000U\r\n#define GPIO_MODER_MODER6_1                  0x00002000U\r\n#define GPIO_MODER_MODER7                    0x0000C000U\r\n#define GPIO_MODER_MODER7_0                  0x00004000U\r\n#define GPIO_MODER_MODER7_1                  0x00008000U\r\n#define GPIO_MODER_MODER8                    0x00030000U\r\n#define GPIO_MODER_MODER8_0                  0x00010000U\r\n#define GPIO_MODER_MODER8_1                  0x00020000U\r\n#define GPIO_MODER_MODER9                    0x000C0000U\r\n#define GPIO_MODER_MODER9_0                  0x00040000U\r\n#define GPIO_MODER_MODER9_1                  0x00080000U\r\n#define GPIO_MODER_MODER10                   0x00300000U\r\n#define GPIO_MODER_MODER10_0                 0x00100000U\r\n#define GPIO_MODER_MODER10_1                 0x00200000U\r\n#define GPIO_MODER_MODER11                   0x00C00000U\r\n#define GPIO_MODER_MODER11_0                 0x00400000U\r\n#define GPIO_MODER_MODER11_1                 0x00800000U\r\n#define GPIO_MODER_MODER12                   0x03000000U\r\n#define GPIO_MODER_MODER12_0                 0x01000000U\r\n#define GPIO_MODER_MODER12_1                 0x02000000U\r\n#define GPIO_MODER_MODER13                   0x0C000000U\r\n#define GPIO_MODER_MODER13_0                 0x04000000U\r\n#define GPIO_MODER_MODER13_1                 0x08000000U\r\n#define GPIO_MODER_MODER14                   0x30000000U\r\n#define GPIO_MODER_MODER14_0                 0x10000000U\r\n#define GPIO_MODER_MODER14_1                 0x20000000U\r\n#define GPIO_MODER_MODER15                   0xC0000000U\r\n#define GPIO_MODER_MODER15_0                 0x40000000U\r\n#define GPIO_MODER_MODER15_1                 0x80000000U\r\n\r\n/******************  Bits definition for GPIO_OTYPER register  ****************/\r\n#define GPIO_OTYPER_OT_0                     0x00000001U\r\n#define GPIO_OTYPER_OT_1                     0x00000002U\r\n#define GPIO_OTYPER_OT_2                     0x00000004U\r\n#define GPIO_OTYPER_OT_3                     0x00000008U\r\n#define GPIO_OTYPER_OT_4                     0x00000010U\r\n#define GPIO_OTYPER_OT_5                     0x00000020U\r\n#define GPIO_OTYPER_OT_6                     0x00000040U\r\n#define GPIO_OTYPER_OT_7                     0x00000080U\r\n#define GPIO_OTYPER_OT_8                     0x00000100U\r\n#define GPIO_OTYPER_OT_9                     0x00000200U\r\n#define GPIO_OTYPER_OT_10                    0x00000400U\r\n#define GPIO_OTYPER_OT_11                    0x00000800U\r\n#define GPIO_OTYPER_OT_12                    0x00001000U\r\n#define GPIO_OTYPER_OT_13                    0x00002000U\r\n#define GPIO_OTYPER_OT_14                    0x00004000U\r\n#define GPIO_OTYPER_OT_15                    0x00008000U\r\n\r\n/******************  Bits definition for GPIO_OSPEEDR register  ***************/\r\n#define GPIO_OSPEEDER_OSPEEDR0               0x00000003U\r\n#define GPIO_OSPEEDER_OSPEEDR0_0             0x00000001U\r\n#define GPIO_OSPEEDER_OSPEEDR0_1             0x00000002U\r\n#define GPIO_OSPEEDER_OSPEEDR1               0x0000000CU\r\n#define GPIO_OSPEEDER_OSPEEDR1_0             0x00000004U\r\n#define GPIO_OSPEEDER_OSPEEDR1_1             0x00000008U\r\n#define GPIO_OSPEEDER_OSPEEDR2               0x00000030U\r\n#define GPIO_OSPEEDER_OSPEEDR2_0             0x00000010U\r\n#define GPIO_OSPEEDER_OSPEEDR2_1             0x00000020U\r\n#define GPIO_OSPEEDER_OSPEEDR3               0x000000C0U\r\n#define GPIO_OSPEEDER_OSPEEDR3_0             0x00000040U\r\n#define GPIO_OSPEEDER_OSPEEDR3_1             0x00000080U\r\n#define GPIO_OSPEEDER_OSPEEDR4               0x00000300U\r\n#define GPIO_OSPEEDER_OSPEEDR4_0             0x00000100U\r\n#define GPIO_OSPEEDER_OSPEEDR4_1             0x00000200U\r\n#define GPIO_OSPEEDER_OSPEEDR5               0x00000C00U\r\n#define GPIO_OSPEEDER_OSPEEDR5_0             0x00000400U\r\n#define GPIO_OSPEEDER_OSPEEDR5_1             0x00000800U\r\n#define GPIO_OSPEEDER_OSPEEDR6               0x00003000U\r\n#define GPIO_OSPEEDER_OSPEEDR6_0             0x00001000U\r\n#define GPIO_OSPEEDER_OSPEEDR6_1             0x00002000U\r\n#define GPIO_OSPEEDER_OSPEEDR7               0x0000C000U\r\n#define GPIO_OSPEEDER_OSPEEDR7_0             0x00004000U\r\n#define GPIO_OSPEEDER_OSPEEDR7_1             0x00008000U\r\n#define GPIO_OSPEEDER_OSPEEDR8               0x00030000U\r\n#define GPIO_OSPEEDER_OSPEEDR8_0             0x00010000U\r\n#define GPIO_OSPEEDER_OSPEEDR8_1             0x00020000U\r\n#define GPIO_OSPEEDER_OSPEEDR9               0x000C0000U\r\n#define GPIO_OSPEEDER_OSPEEDR9_0             0x00040000U\r\n#define GPIO_OSPEEDER_OSPEEDR9_1             0x00080000U\r\n#define GPIO_OSPEEDER_OSPEEDR10              0x00300000U\r\n#define GPIO_OSPEEDER_OSPEEDR10_0            0x00100000U\r\n#define GPIO_OSPEEDER_OSPEEDR10_1            0x00200000U\r\n#define GPIO_OSPEEDER_OSPEEDR11              0x00C00000U\r\n#define GPIO_OSPEEDER_OSPEEDR11_0            0x00400000U\r\n#define GPIO_OSPEEDER_OSPEEDR11_1            0x00800000U\r\n#define GPIO_OSPEEDER_OSPEEDR12              0x03000000U\r\n#define GPIO_OSPEEDER_OSPEEDR12_0            0x01000000U\r\n#define GPIO_OSPEEDER_OSPEEDR12_1            0x02000000U\r\n#define GPIO_OSPEEDER_OSPEEDR13              0x0C000000U\r\n#define GPIO_OSPEEDER_OSPEEDR13_0            0x04000000U\r\n#define GPIO_OSPEEDER_OSPEEDR13_1            0x08000000U\r\n#define GPIO_OSPEEDER_OSPEEDR14              0x30000000U\r\n#define GPIO_OSPEEDER_OSPEEDR14_0            0x10000000U\r\n#define GPIO_OSPEEDER_OSPEEDR14_1            0x20000000U\r\n#define GPIO_OSPEEDER_OSPEEDR15              0xC0000000U\r\n#define GPIO_OSPEEDER_OSPEEDR15_0            0x40000000U\r\n#define GPIO_OSPEEDER_OSPEEDR15_1            0x80000000U\r\n\r\n/******************  Bits definition for GPIO_PUPDR register  *****************/\r\n#define GPIO_PUPDR_PUPDR0                    0x00000003U\r\n#define GPIO_PUPDR_PUPDR0_0                  0x00000001U\r\n#define GPIO_PUPDR_PUPDR0_1                  0x00000002U\r\n#define GPIO_PUPDR_PUPDR1                    0x0000000CU\r\n#define GPIO_PUPDR_PUPDR1_0                  0x00000004U\r\n#define GPIO_PUPDR_PUPDR1_1                  0x00000008U\r\n#define GPIO_PUPDR_PUPDR2                    0x00000030U\r\n#define GPIO_PUPDR_PUPDR2_0                  0x00000010U\r\n#define GPIO_PUPDR_PUPDR2_1                  0x00000020U\r\n#define GPIO_PUPDR_PUPDR3                    0x000000C0U\r\n#define GPIO_PUPDR_PUPDR3_0                  0x00000040U\r\n#define GPIO_PUPDR_PUPDR3_1                  0x00000080U\r\n#define GPIO_PUPDR_PUPDR4                    0x00000300U\r\n#define GPIO_PUPDR_PUPDR4_0                  0x00000100U\r\n#define GPIO_PUPDR_PUPDR4_1                  0x00000200U\r\n#define GPIO_PUPDR_PUPDR5                    0x00000C00U\r\n#define GPIO_PUPDR_PUPDR5_0                  0x00000400U\r\n#define GPIO_PUPDR_PUPDR5_1                  0x00000800U\r\n#define GPIO_PUPDR_PUPDR6                    0x00003000U\r\n#define GPIO_PUPDR_PUPDR6_0                  0x00001000U\r\n#define GPIO_PUPDR_PUPDR6_1                  0x00002000U\r\n#define GPIO_PUPDR_PUPDR7                    0x0000C000U\r\n#define GPIO_PUPDR_PUPDR7_0                  0x00004000U\r\n#define GPIO_PUPDR_PUPDR7_1                  0x00008000U\r\n#define GPIO_PUPDR_PUPDR8                    0x00030000U\r\n#define GPIO_PUPDR_PUPDR8_0                  0x00010000U\r\n#define GPIO_PUPDR_PUPDR8_1                  0x00020000U\r\n#define GPIO_PUPDR_PUPDR9                    0x000C0000U\r\n#define GPIO_PUPDR_PUPDR9_0                  0x00040000U\r\n#define GPIO_PUPDR_PUPDR9_1                  0x00080000U\r\n#define GPIO_PUPDR_PUPDR10                   0x00300000U\r\n#define GPIO_PUPDR_PUPDR10_0                 0x00100000U\r\n#define GPIO_PUPDR_PUPDR10_1                 0x00200000U\r\n#define GPIO_PUPDR_PUPDR11                   0x00C00000U\r\n#define GPIO_PUPDR_PUPDR11_0                 0x00400000U\r\n#define GPIO_PUPDR_PUPDR11_1                 0x00800000U\r\n#define GPIO_PUPDR_PUPDR12                   0x03000000U\r\n#define GPIO_PUPDR_PUPDR12_0                 0x01000000U\r\n#define GPIO_PUPDR_PUPDR12_1                 0x02000000U\r\n#define GPIO_PUPDR_PUPDR13                   0x0C000000U\r\n#define GPIO_PUPDR_PUPDR13_0                 0x04000000U\r\n#define GPIO_PUPDR_PUPDR13_1                 0x08000000U\r\n#define GPIO_PUPDR_PUPDR14                   0x30000000U\r\n#define GPIO_PUPDR_PUPDR14_0                 0x10000000U\r\n#define GPIO_PUPDR_PUPDR14_1                 0x20000000U\r\n#define GPIO_PUPDR_PUPDR15                   0xC0000000U\r\n#define GPIO_PUPDR_PUPDR15_0                 0x40000000U\r\n#define GPIO_PUPDR_PUPDR15_1                 0x80000000U\r\n\r\n/******************  Bits definition for GPIO_IDR register  *******************/\r\n#define GPIO_IDR_IDR_0                       0x00000001U\r\n#define GPIO_IDR_IDR_1                       0x00000002U\r\n#define GPIO_IDR_IDR_2                       0x00000004U\r\n#define GPIO_IDR_IDR_3                       0x00000008U\r\n#define GPIO_IDR_IDR_4                       0x00000010U\r\n#define GPIO_IDR_IDR_5                       0x00000020U\r\n#define GPIO_IDR_IDR_6                       0x00000040U\r\n#define GPIO_IDR_IDR_7                       0x00000080U\r\n#define GPIO_IDR_IDR_8                       0x00000100U\r\n#define GPIO_IDR_IDR_9                       0x00000200U\r\n#define GPIO_IDR_IDR_10                      0x00000400U\r\n#define GPIO_IDR_IDR_11                      0x00000800U\r\n#define GPIO_IDR_IDR_12                      0x00001000U\r\n#define GPIO_IDR_IDR_13                      0x00002000U\r\n#define GPIO_IDR_IDR_14                      0x00004000U\r\n#define GPIO_IDR_IDR_15                      0x00008000U\r\n\r\n/******************  Bits definition for GPIO_ODR register  *******************/\r\n#define GPIO_ODR_ODR_0                       0x00000001U\r\n#define GPIO_ODR_ODR_1                       0x00000002U\r\n#define GPIO_ODR_ODR_2                       0x00000004U\r\n#define GPIO_ODR_ODR_3                       0x00000008U\r\n#define GPIO_ODR_ODR_4                       0x00000010U\r\n#define GPIO_ODR_ODR_5                       0x00000020U\r\n#define GPIO_ODR_ODR_6                       0x00000040U\r\n#define GPIO_ODR_ODR_7                       0x00000080U\r\n#define GPIO_ODR_ODR_8                       0x00000100U\r\n#define GPIO_ODR_ODR_9                       0x00000200U\r\n#define GPIO_ODR_ODR_10                      0x00000400U\r\n#define GPIO_ODR_ODR_11                      0x00000800U\r\n#define GPIO_ODR_ODR_12                      0x00001000U\r\n#define GPIO_ODR_ODR_13                      0x00002000U\r\n#define GPIO_ODR_ODR_14                      0x00004000U\r\n#define GPIO_ODR_ODR_15                      0x00008000U\r\n\r\n/******************  Bits definition for GPIO_BSRR register  ******************/\r\n#define GPIO_BSRR_BS_0                       0x00000001U\r\n#define GPIO_BSRR_BS_1                       0x00000002U\r\n#define GPIO_BSRR_BS_2                       0x00000004U\r\n#define GPIO_BSRR_BS_3                       0x00000008U\r\n#define GPIO_BSRR_BS_4                       0x00000010U\r\n#define GPIO_BSRR_BS_5                       0x00000020U\r\n#define GPIO_BSRR_BS_6                       0x00000040U\r\n#define GPIO_BSRR_BS_7                       0x00000080U\r\n#define GPIO_BSRR_BS_8                       0x00000100U\r\n#define GPIO_BSRR_BS_9                       0x00000200U\r\n#define GPIO_BSRR_BS_10                      0x00000400U\r\n#define GPIO_BSRR_BS_11                      0x00000800U\r\n#define GPIO_BSRR_BS_12                      0x00001000U\r\n#define GPIO_BSRR_BS_13                      0x00002000U\r\n#define GPIO_BSRR_BS_14                      0x00004000U\r\n#define GPIO_BSRR_BS_15                      0x00008000U\r\n#define GPIO_BSRR_BR_0                       0x00010000U\r\n#define GPIO_BSRR_BR_1                       0x00020000U\r\n#define GPIO_BSRR_BR_2                       0x00040000U\r\n#define GPIO_BSRR_BR_3                       0x00080000U\r\n#define GPIO_BSRR_BR_4                       0x00100000U\r\n#define GPIO_BSRR_BR_5                       0x00200000U\r\n#define GPIO_BSRR_BR_6                       0x00400000U\r\n#define GPIO_BSRR_BR_7                       0x00800000U\r\n#define GPIO_BSRR_BR_8                       0x01000000U\r\n#define GPIO_BSRR_BR_9                       0x02000000U\r\n#define GPIO_BSRR_BR_10                      0x04000000U\r\n#define GPIO_BSRR_BR_11                      0x08000000U\r\n#define GPIO_BSRR_BR_12                      0x10000000U\r\n#define GPIO_BSRR_BR_13                      0x20000000U\r\n#define GPIO_BSRR_BR_14                      0x40000000U\r\n#define GPIO_BSRR_BR_15                      0x80000000U\r\n\r\n/****************** Bit definition for GPIO_LCKR register *********************/\r\n#define GPIO_LCKR_LCK0                       0x00000001U\r\n#define GPIO_LCKR_LCK1                       0x00000002U\r\n#define GPIO_LCKR_LCK2                       0x00000004U\r\n#define GPIO_LCKR_LCK3                       0x00000008U\r\n#define GPIO_LCKR_LCK4                       0x00000010U\r\n#define GPIO_LCKR_LCK5                       0x00000020U\r\n#define GPIO_LCKR_LCK6                       0x00000040U\r\n#define GPIO_LCKR_LCK7                       0x00000080U\r\n#define GPIO_LCKR_LCK8                       0x00000100U\r\n#define GPIO_LCKR_LCK9                       0x00000200U\r\n#define GPIO_LCKR_LCK10                      0x00000400U\r\n#define GPIO_LCKR_LCK11                      0x00000800U\r\n#define GPIO_LCKR_LCK12                      0x00001000U\r\n#define GPIO_LCKR_LCK13                      0x00002000U\r\n#define GPIO_LCKR_LCK14                      0x00004000U\r\n#define GPIO_LCKR_LCK15                      0x00008000U\r\n#define GPIO_LCKR_LCKK                       0x00010000U\r\n\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                      Inter-integrated Circuit Interface (I2C)              */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************  Bit definition for I2C_CR1 register  *******************/\r\n#define  I2C_CR1_PE                          0x00000001U        /*!< Peripheral enable                   */\r\n#define  I2C_CR1_TXIE                        0x00000002U        /*!< TX interrupt enable                 */\r\n#define  I2C_CR1_RXIE                        0x00000004U        /*!< RX interrupt enable                 */\r\n#define  I2C_CR1_ADDRIE                      0x00000008U        /*!< Address match interrupt enable      */\r\n#define  I2C_CR1_NACKIE                      0x00000010U        /*!< NACK received interrupt enable      */\r\n#define  I2C_CR1_STOPIE                      0x00000020U        /*!< STOP detection interrupt enable     */\r\n#define  I2C_CR1_TCIE                        0x00000040U        /*!< Transfer complete interrupt enable  */\r\n#define  I2C_CR1_ERRIE                       0x00000080U        /*!< Errors interrupt enable             */\r\n#define  I2C_CR1_DNF                         0x00000F00U        /*!< Digital noise filter                */\r\n#define  I2C_CR1_ANFOFF                      0x00001000U        /*!< Analog noise filter OFF             */\r\n#define  I2C_CR1_TXDMAEN                     0x00004000U        /*!< DMA transmission requests enable    */\r\n#define  I2C_CR1_RXDMAEN                     0x00008000U        /*!< DMA reception requests enable       */\r\n#define  I2C_CR1_SBC                         0x00010000U        /*!< Slave byte control                  */\r\n#define  I2C_CR1_NOSTRETCH                   0x00020000U        /*!< Clock stretching disable            */\r\n#define  I2C_CR1_GCEN                        0x00080000U        /*!< General call enable                 */\r\n#define  I2C_CR1_SMBHEN                      0x00100000U        /*!< SMBus host address enable           */\r\n#define  I2C_CR1_SMBDEN                      0x00200000U        /*!< SMBus device default address enable */\r\n#define  I2C_CR1_ALERTEN                     0x00400000U        /*!< SMBus alert enable                  */\r\n#define  I2C_CR1_PECEN                       0x00800000U        /*!< PEC enable                          */\r\n\r\n/* Legacy define */\r\n#define  I2C_CR1_DFN                         I2C_CR1_DNF                   /*!< Digital noise filter                */\r\n\r\n/******************  Bit definition for I2C_CR2 register  ********************/\r\n#define  I2C_CR2_SADD                        0x000003FFU        /*!< Slave address (master mode)                             */\r\n#define  I2C_CR2_RD_WRN                      0x00000400U        /*!< Transfer direction (master mode)                        */\r\n#define  I2C_CR2_ADD10                       0x00000800U        /*!< 10-bit addressing mode (master mode)                    */\r\n#define  I2C_CR2_HEAD10R                     0x00001000U        /*!< 10-bit address header only read direction (master mode) */\r\n#define  I2C_CR2_START                       0x00002000U        /*!< START generation                                        */\r\n#define  I2C_CR2_STOP                        0x00004000U        /*!< STOP generation (master mode)                           */\r\n#define  I2C_CR2_NACK                        0x00008000U        /*!< NACK generation (slave mode)                            */\r\n#define  I2C_CR2_NBYTES                      0x00FF0000U        /*!< Number of bytes                                         */\r\n#define  I2C_CR2_RELOAD                      0x01000000U        /*!< NBYTES reload mode                                      */\r\n#define  I2C_CR2_AUTOEND                     0x02000000U        /*!< Automatic end mode (master mode)                        */\r\n#define  I2C_CR2_PECBYTE                     0x04000000U        /*!< Packet error checking byte                              */\r\n\r\n/*******************  Bit definition for I2C_OAR1 register  ******************/\r\n#define  I2C_OAR1_OA1                        0x000003FFU        /*!< Interface own address 1   */\r\n#define  I2C_OAR1_OA1MODE                    0x00000400U        /*!< Own address 1 10-bit mode */\r\n#define  I2C_OAR1_OA1EN                      0x00008000U        /*!< Own address 1 enable      */\r\n\r\n/*******************  Bit definition for I2C_OAR2 register  ******************/\r\n#define  I2C_OAR2_OA2                        0x000000FEU        /*!< Interface own address 2 */\r\n#define  I2C_OAR2_OA2MSK                     0x00000700U        /*!< Own address 2 masks     */\r\n#define  I2C_OAR2_OA2NOMASK                  0x00000000U        /*!< No mask */\r\n#define  I2C_OAR2_OA2MASK01                  0x00000100U        /*!< OA2[1] is masked, Only OA2[7:2] are compared */\r\n#define  I2C_OAR2_OA2MASK02                  0x00000200U        /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */\r\n#define  I2C_OAR2_OA2MASK03                  0x00000300U        /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */\r\n#define  I2C_OAR2_OA2MASK04                  0x00000400U        /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */\r\n#define  I2C_OAR2_OA2MASK05                  0x00000500U        /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */\r\n#define  I2C_OAR2_OA2MASK06                  0x00000600U        /*!< OA2[6:1] is masked, Only OA2[7] are compared */\r\n#define  I2C_OAR2_OA2MASK07                  0x00000700U        /*!< OA2[7:1] is masked, No comparison is done */\r\n#define  I2C_OAR2_OA2EN                      0x00008000U        /*!< Own address 2 enable    */\r\n\r\n/*******************  Bit definition for I2C_TIMINGR register *******************/\r\n#define  I2C_TIMINGR_SCLL                    0x000000FFU        /*!< SCL low period (master mode)  */\r\n#define  I2C_TIMINGR_SCLH                    0x0000FF00U        /*!< SCL high period (master mode) */\r\n#define  I2C_TIMINGR_SDADEL                  0x000F0000U        /*!< Data hold time                */\r\n#define  I2C_TIMINGR_SCLDEL                  0x00F00000U        /*!< Data setup time               */\r\n#define  I2C_TIMINGR_PRESC                   0xF0000000U        /*!< Timings prescaler             */\r\n\r\n/******************* Bit definition for I2C_TIMEOUTR register *******************/\r\n#define  I2C_TIMEOUTR_TIMEOUTA               0x00000FFFU        /*!< Bus timeout A                 */\r\n#define  I2C_TIMEOUTR_TIDLE                  0x00001000U        /*!< Idle clock timeout detection  */\r\n#define  I2C_TIMEOUTR_TIMOUTEN               0x00008000U        /*!< Clock timeout enable          */\r\n#define  I2C_TIMEOUTR_TIMEOUTB               0x0FFF0000U        /*!< Bus timeout B                 */\r\n#define  I2C_TIMEOUTR_TEXTEN                 0x80000000U        /*!< Extended clock timeout enable */\r\n\r\n/******************  Bit definition for I2C_ISR register  *********************/\r\n#define  I2C_ISR_TXE                         0x00000001U        /*!< Transmit data register empty    */\r\n#define  I2C_ISR_TXIS                        0x00000002U        /*!< Transmit interrupt status       */\r\n#define  I2C_ISR_RXNE                        0x00000004U        /*!< Receive data register not empty */\r\n#define  I2C_ISR_ADDR                        0x00000008U        /*!< Address matched (slave mode)    */\r\n#define  I2C_ISR_NACKF                       0x00000010U        /*!< NACK received flag              */\r\n#define  I2C_ISR_STOPF                       0x00000020U        /*!< STOP detection flag             */\r\n#define  I2C_ISR_TC                          0x00000040U        /*!< Transfer complete (master mode) */\r\n#define  I2C_ISR_TCR                         0x00000080U        /*!< Transfer complete reload        */\r\n#define  I2C_ISR_BERR                        0x00000100U        /*!< Bus error                       */\r\n#define  I2C_ISR_ARLO                        0x00000200U        /*!< Arbitration lost                */\r\n#define  I2C_ISR_OVR                         0x00000400U        /*!< Overrun/Underrun                */\r\n#define  I2C_ISR_PECERR                      0x00000800U        /*!< PEC error in reception          */\r\n#define  I2C_ISR_TIMEOUT                     0x00001000U        /*!< Timeout or Tlow detection flag  */\r\n#define  I2C_ISR_ALERT                       0x00002000U        /*!< SMBus alert                     */\r\n#define  I2C_ISR_BUSY                        0x00008000U        /*!< Bus busy                        */\r\n#define  I2C_ISR_DIR                         0x00010000U        /*!< Transfer direction (slave mode) */\r\n#define  I2C_ISR_ADDCODE                     0x00FE0000U        /*!< Address match code (slave mode) */\r\n\r\n/******************  Bit definition for I2C_ICR register  *********************/\r\n#define  I2C_ICR_ADDRCF                      0x00000008U        /*!< Address matched clear flag      */\r\n#define  I2C_ICR_NACKCF                      0x00000010U        /*!< NACK clear flag                 */\r\n#define  I2C_ICR_STOPCF                      0x00000020U        /*!< STOP detection clear flag       */\r\n#define  I2C_ICR_BERRCF                      0x00000100U        /*!< Bus error clear flag            */\r\n#define  I2C_ICR_ARLOCF                      0x00000200U        /*!< Arbitration lost clear flag     */\r\n#define  I2C_ICR_OVRCF                       0x00000400U        /*!< Overrun/Underrun clear flag     */\r\n#define  I2C_ICR_PECCF                       0x00000800U        /*!< PAC error clear flag            */\r\n#define  I2C_ICR_TIMOUTCF                    0x00001000U        /*!< Timeout clear flag              */\r\n#define  I2C_ICR_ALERTCF                     0x00002000U        /*!< Alert clear flag                */\r\n\r\n/******************  Bit definition for I2C_PECR register  *********************/\r\n#define  I2C_PECR_PEC                        0x000000FFU        /*!< PEC register        */\r\n\r\n/******************  Bit definition for I2C_RXDR register  *********************/\r\n#define  I2C_RXDR_RXDATA                     0x000000FFU        /*!< 8-bit receive data  */\r\n\r\n/******************  Bit definition for I2C_TXDR register  *********************/\r\n#define  I2C_TXDR_TXDATA                     0x000000FFU        /*!< 8-bit transmit data */\r\n\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                           Independent WATCHDOG                             */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************  Bit definition for IWDG_KR register  ********************/\r\n#define  IWDG_KR_KEY                         0xFFFFU            /*!<Key value (write only, read 0000h)  */\r\n\r\n/*******************  Bit definition for IWDG_PR register  ********************/\r\n#define  IWDG_PR_PR                          0x07U               /*!<PR[2:0] (Prescaler divider)         */\r\n#define  IWDG_PR_PR_0                        0x01U               /*!<Bit 0 */\r\n#define  IWDG_PR_PR_1                        0x02U               /*!<Bit 1 */\r\n#define  IWDG_PR_PR_2                        0x04U               /*!<Bit 2 */\r\n\r\n/*******************  Bit definition for IWDG_RLR register  *******************/\r\n#define  IWDG_RLR_RL                         0x0FFFU            /*!<Watchdog counter reload value        */\r\n\r\n/*******************  Bit definition for IWDG_SR register  ********************/\r\n#define  IWDG_SR_PVU                         0x01U               /*!< Watchdog prescaler value update */\r\n#define  IWDG_SR_RVU                         0x02U               /*!< Watchdog counter reload value update */\r\n#define  IWDG_SR_WVU                         0x04U               /*!< Watchdog counter window value update */\r\n\r\n/*******************  Bit definition for IWDG_KR register  ********************/\r\n#define  IWDG_WINR_WIN                       0x0FFFU             /*!< Watchdog counter window value */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                      LCD-TFT Display Controller (LTDC)                     */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n\r\n/********************  Bit definition for LTDC_SSCR register  *****************/\r\n\r\n#define LTDC_SSCR_VSH                       0x000007FFU              /*!< Vertical Synchronization Height  */\r\n#define LTDC_SSCR_HSW                       0x0FFF0000U              /*!< Horizontal Synchronization Width */\r\n\r\n/********************  Bit definition for LTDC_BPCR register  *****************/\r\n\r\n#define LTDC_BPCR_AVBP                      0x000007FFU              /*!< Accumulated Vertical Back Porch   */\r\n#define LTDC_BPCR_AHBP                      0x0FFF0000U              /*!< Accumulated Horizontal Back Porch */\r\n\r\n/********************  Bit definition for LTDC_AWCR register  *****************/\r\n\r\n#define LTDC_AWCR_AAH                       0x000007FFU              /*!< Accumulated Active heigh */\r\n#define LTDC_AWCR_AAW                       0x0FFF0000U              /*!< Accumulated Active Width */\r\n\r\n/********************  Bit definition for LTDC_TWCR register  *****************/\r\n\r\n#define LTDC_TWCR_TOTALH                    0x000007FFU              /*!< Total Heigh */\r\n#define LTDC_TWCR_TOTALW                    0x0FFF0000U              /*!< Total Width */\r\n\r\n/********************  Bit definition for LTDC_GCR register  ******************/\r\n\r\n#define LTDC_GCR_LTDCEN                     0x00000001U              /*!< LCD-TFT controller enable bit       */\r\n#define LTDC_GCR_DBW                        0x00000070U              /*!< Dither Blue Width                   */\r\n#define LTDC_GCR_DGW                        0x00000700U              /*!< Dither Green Width                  */\r\n#define LTDC_GCR_DRW                        0x00007000U              /*!< Dither Red Width                    */\r\n#define LTDC_GCR_DEN                        0x00010000U              /*!< Dither Enable                       */\r\n#define LTDC_GCR_PCPOL                      0x10000000U              /*!< Pixel Clock Polarity                */\r\n#define LTDC_GCR_DEPOL                      0x20000000U              /*!< Data Enable Polarity                */\r\n#define LTDC_GCR_VSPOL                      0x40000000U              /*!< Vertical Synchronization Polarity   */\r\n#define LTDC_GCR_HSPOL                      0x80000000U              /*!< Horizontal Synchronization Polarity */\r\n\r\n/* Legacy define */\r\n#define LTDC_GCR_DTEN                       LTDC_GCR_DEN\r\n\r\n/********************  Bit definition for LTDC_SRCR register  *****************/\r\n\r\n#define LTDC_SRCR_IMR                      0x00000001U               /*!< Immediate Reload         */\r\n#define LTDC_SRCR_VBR                      0x00000002U               /*!< Vertical Blanking Reload */\r\n\r\n/********************  Bit definition for LTDC_BCCR register  *****************/\r\n\r\n#define LTDC_BCCR_BCBLUE                    0x000000FFU              /*!< Background Blue value  */\r\n#define LTDC_BCCR_BCGREEN                   0x0000FF00U              /*!< Background Green value */\r\n#define LTDC_BCCR_BCRED                     0x00FF0000U              /*!< Background Red value   */\r\n\r\n/********************  Bit definition for LTDC_IER register  ******************/\r\n\r\n#define LTDC_IER_LIE                        0x00000001U              /*!< Line Interrupt Enable            */\r\n#define LTDC_IER_FUIE                       0x00000002U              /*!< FIFO Underrun Interrupt Enable   */\r\n#define LTDC_IER_TERRIE                     0x00000004U              /*!< Transfer Error Interrupt Enable  */\r\n#define LTDC_IER_RRIE                       0x00000008U              /*!< Register Reload interrupt enable */\r\n\r\n/********************  Bit definition for LTDC_ISR register  ******************/\r\n\r\n#define LTDC_ISR_LIF                        0x00000001U              /*!< Line Interrupt Flag */\r\n#define LTDC_ISR_FUIF                       0x00000002U              /*!< FIFO Underrun Interrupt Flag */\r\n#define LTDC_ISR_TERRIF                     0x00000004U              /*!< Transfer Error Interrupt Flag */\r\n#define LTDC_ISR_RRIF                       0x00000008U              /*!< Register Reload interrupt Flag */\r\n\r\n/********************  Bit definition for LTDC_ICR register  ******************/\r\n\r\n#define LTDC_ICR_CLIF                       0x00000001U              /*!< Clears the Line Interrupt Flag */\r\n#define LTDC_ICR_CFUIF                      0x00000002U              /*!< Clears the FIFO Underrun Interrupt Flag */\r\n#define LTDC_ICR_CTERRIF                    0x00000004U              /*!< Clears the Transfer Error Interrupt Flag */\r\n#define LTDC_ICR_CRRIF                      0x00000008U              /*!< Clears Register Reload interrupt Flag */\r\n\r\n/********************  Bit definition for LTDC_LIPCR register  ****************/\r\n\r\n#define LTDC_LIPCR_LIPOS                    0x000007FFU              /*!< Line Interrupt Position */\r\n\r\n/********************  Bit definition for LTDC_CPSR register  *****************/\r\n\r\n#define LTDC_CPSR_CYPOS                     0x0000FFFFU              /*!< Current Y Position */\r\n#define LTDC_CPSR_CXPOS                     0xFFFF0000U              /*!< Current X Position */\r\n\r\n/********************  Bit definition for LTDC_CDSR register  *****************/\r\n\r\n#define LTDC_CDSR_VDES                      0x00000001U              /*!< Vertical Data Enable Status       */\r\n#define LTDC_CDSR_HDES                      0x00000002U              /*!< Horizontal Data Enable Status     */\r\n#define LTDC_CDSR_VSYNCS                    0x00000004U              /*!< Vertical Synchronization Status   */\r\n#define LTDC_CDSR_HSYNCS                    0x00000008U              /*!< Horizontal Synchronization Status */\r\n\r\n/********************  Bit definition for LTDC_LxCR register  *****************/\r\n\r\n#define LTDC_LxCR_LEN                       0x00000001U              /*!< Layer Enable              */\r\n#define LTDC_LxCR_COLKEN                    0x00000002U              /*!< Color Keying Enable       */\r\n#define LTDC_LxCR_CLUTEN                    0x00000010U              /*!< Color Lockup Table Enable */\r\n\r\n/********************  Bit definition for LTDC_LxWHPCR register  **************/\r\n\r\n#define LTDC_LxWHPCR_WHSTPOS                0x00000FFFU              /*!< Window Horizontal Start Position */\r\n#define LTDC_LxWHPCR_WHSPPOS                0xFFFF0000U              /*!< Window Horizontal Stop Position  */\r\n\r\n/********************  Bit definition for LTDC_LxWVPCR register  **************/\r\n\r\n#define LTDC_LxWVPCR_WVSTPOS                0x00000FFFU              /*!< Window Vertical Start Position */\r\n#define LTDC_LxWVPCR_WVSPPOS                0xFFFF0000U              /*!< Window Vertical Stop Position  */\r\n\r\n/********************  Bit definition for LTDC_LxCKCR register  ***************/\r\n\r\n#define LTDC_LxCKCR_CKBLUE                  0x000000FFU              /*!< Color Key Blue value  */\r\n#define LTDC_LxCKCR_CKGREEN                 0x0000FF00U              /*!< Color Key Green value */\r\n#define LTDC_LxCKCR_CKRED                   0x00FF0000U              /*!< Color Key Red value   */\r\n\r\n/********************  Bit definition for LTDC_LxPFCR register  ***************/\r\n\r\n#define LTDC_LxPFCR_PF                      0x00000007U              /*!< Pixel Format */\r\n\r\n/********************  Bit definition for LTDC_LxCACR register  ***************/\r\n\r\n#define LTDC_LxCACR_CONSTA                  0x000000FFU              /*!< Constant Alpha */\r\n\r\n/********************  Bit definition for LTDC_LxDCCR register  ***************/\r\n\r\n#define LTDC_LxDCCR_DCBLUE                  0x000000FFU              /*!< Default Color Blue  */\r\n#define LTDC_LxDCCR_DCGREEN                 0x0000FF00U              /*!< Default Color Green */\r\n#define LTDC_LxDCCR_DCRED                   0x00FF0000U              /*!< Default Color Red   */\r\n#define LTDC_LxDCCR_DCALPHA                 0xFF000000U              /*!< Default Color Alpha */\r\n                                \r\n/********************  Bit definition for LTDC_LxBFCR register  ***************/\r\n\r\n#define LTDC_LxBFCR_BF2                     0x00000007U              /*!< Blending Factor 2 */\r\n#define LTDC_LxBFCR_BF1                     0x00000700U              /*!< Blending Factor 1 */\r\n\r\n/********************  Bit definition for LTDC_LxCFBAR register  **************/\r\n\r\n#define LTDC_LxCFBAR_CFBADD                 0xFFFFFFFFU              /*!< Color Frame Buffer Start Address */\r\n\r\n/********************  Bit definition for LTDC_LxCFBLR register  **************/\r\n\r\n#define LTDC_LxCFBLR_CFBLL                  0x00001FFFU              /*!< Color Frame Buffer Line Length    */\r\n#define LTDC_LxCFBLR_CFBP                   0x1FFF0000U              /*!< Color Frame Buffer Pitch in bytes */\r\n\r\n/********************  Bit definition for LTDC_LxCFBLNR register  *************/\r\n\r\n#define LTDC_LxCFBLNR_CFBLNBR               0x000007FFU              /*!< Frame Buffer Line Number */\r\n\r\n/********************  Bit definition for LTDC_LxCLUTWR register  *************/\r\n\r\n#define LTDC_LxCLUTWR_BLUE                  0x000000FFU              /*!< Blue value   */\r\n#define LTDC_LxCLUTWR_GREEN                 0x0000FF00U              /*!< Green value  */\r\n#define LTDC_LxCLUTWR_RED                   0x00FF0000U              /*!< Red value    */\r\n#define LTDC_LxCLUTWR_CLUTADD               0xFF000000U              /*!< CLUT address */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                             Power Control                                  */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bit definition for PWR_CR1 register  ********************/\r\n#define  PWR_CR1_LPDS                         0x00000001U     /*!< Low-Power Deepsleep                 */\r\n#define  PWR_CR1_PDDS                         0x00000002U     /*!< Power Down Deepsleep                */\r\n#define  PWR_CR1_CSBF                         0x00000008U     /*!< Clear Standby Flag                  */\r\n#define  PWR_CR1_PVDE                         0x00000010U     /*!< Power Voltage Detector Enable       */\r\n#define  PWR_CR1_PLS                          0x000000E0U     /*!< PLS[2:0] bits (PVD Level Selection) */\r\n#define  PWR_CR1_PLS_0                        0x00000020U     /*!< Bit 0 */\r\n#define  PWR_CR1_PLS_1                        0x00000040U     /*!< Bit 1 */\r\n#define  PWR_CR1_PLS_2                        0x00000080U     /*!< Bit 2 */\r\n\r\n/*!< PVD level configuration */\r\n#define  PWR_CR1_PLS_LEV0                     0x00000000U     /*!< PVD level 0 */\r\n#define  PWR_CR1_PLS_LEV1                     0x00000020U     /*!< PVD level 1 */\r\n#define  PWR_CR1_PLS_LEV2                     0x00000040U     /*!< PVD level 2 */\r\n#define  PWR_CR1_PLS_LEV3                     0x00000060U     /*!< PVD level 3 */\r\n#define  PWR_CR1_PLS_LEV4                     0x00000080U     /*!< PVD level 4 */\r\n#define  PWR_CR1_PLS_LEV5                     0x000000A0U     /*!< PVD level 5 */\r\n#define  PWR_CR1_PLS_LEV6                     0x000000C0U     /*!< PVD level 6 */\r\n#define  PWR_CR1_PLS_LEV7                     0x000000E0U     /*!< PVD level 7 */\r\n#define  PWR_CR1_DBP                          0x00000100U     /*!< Disable Backup Domain write protection                     */\r\n#define  PWR_CR1_FPDS                         0x00000200U     /*!< Flash power down in Stop mode                              */\r\n#define  PWR_CR1_LPUDS                        0x00000400U     /*!< Low-power regulator in deepsleep under-drive mode          */\r\n#define  PWR_CR1_MRUDS                        0x00000800U     /*!< Main regulator in deepsleep under-drive mode               */\r\n#define  PWR_CR1_ADCDC1                       0x00002000U     /*!< Refer to AN4073 on how to use this bit */ \r\n#define  PWR_CR1_VOS                          0x0000C000U     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */\r\n#define  PWR_CR1_VOS_0                        0x00004000U     /*!< Bit 0 */\r\n#define  PWR_CR1_VOS_1                        0x00008000U     /*!< Bit 1 */\r\n#define  PWR_CR1_ODEN                         0x00010000U     /*!< Over Drive enable                   */\r\n#define  PWR_CR1_ODSWEN                       0x00020000U     /*!< Over Drive switch enabled           */\r\n#define  PWR_CR1_UDEN                         0x000C0000U     /*!< Under Drive enable in stop mode     */\r\n#define  PWR_CR1_UDEN_0                       0x00040000U     /*!< Bit 0                               */\r\n#define  PWR_CR1_UDEN_1                       0x00080000U     /*!< Bit 1                               */\r\n\r\n/*******************  Bit definition for PWR_CSR1 register  ********************/\r\n#define  PWR_CSR1_WUIF                        0x00000001U     /*!< Wake up internal Flag                            */\r\n#define  PWR_CSR1_SBF                         0x00000002U     /*!< Standby Flag                                     */\r\n#define  PWR_CSR1_PVDO                        0x00000004U     /*!< PVD Output                                       */\r\n#define  PWR_CSR1_BRR                         0x00000008U     /*!< Backup regulator ready                           */\r\n#define  PWR_CSR1_EIWUP                       0x00000100U     /*!< Enable internal wakeup                           */\r\n#define  PWR_CSR1_BRE                         0x00000200U     /*!< Backup regulator enable                          */\r\n#define  PWR_CSR1_VOSRDY                      0x00004000U     /*!< Regulator voltage scaling output selection ready */\r\n#define  PWR_CSR1_ODRDY                       0x00010000U     /*!< Over Drive generator ready                       */\r\n#define  PWR_CSR1_ODSWRDY                     0x00020000U     /*!< Over Drive Switch ready                          */\r\n#define  PWR_CSR1_UDRDY                       0x000C0000U     /*!< Under Drive ready                                */\r\n\r\n/* Legacy define */\r\n#define  PWR_CSR1_UDSWRDY                     PWR_CSR1_UDRDY\r\n\r\n/********************  Bit definition for PWR_CR2 register  ********************/\r\n#define  PWR_CR2_CWUPF1                         0x00000001U     /*!< Clear Wakeup Pin Flag for PA0      */\r\n#define  PWR_CR2_CWUPF2                         0x00000002U     /*!< Clear Wakeup Pin Flag for PA2      */\r\n#define  PWR_CR2_CWUPF3                         0x00000004U     /*!< Clear Wakeup Pin Flag for PC1      */\r\n#define  PWR_CR2_CWUPF4                         0x00000008U     /*!< Clear Wakeup Pin Flag for PC13     */\r\n#define  PWR_CR2_CWUPF5                         0x00000010U     /*!< Clear Wakeup Pin Flag for PI8      */\r\n#define  PWR_CR2_CWUPF6                         0x00000020U     /*!< Clear Wakeup Pin Flag for PI11     */\r\n#define  PWR_CR2_WUPP1                          0x00000100U     /*!< Wakeup Pin Polarity bit for PA0    */\r\n#define  PWR_CR2_WUPP2                          0x00000200U     /*!< Wakeup Pin Polarity bit for PA2    */\r\n#define  PWR_CR2_WUPP3                          0x00000400U     /*!< Wakeup Pin Polarity bit for PC1    */\r\n#define  PWR_CR2_WUPP4                          0x00000800U     /*!< Wakeup Pin Polarity bit for PC13   */\r\n#define  PWR_CR2_WUPP5                          0x00001000U     /*!< Wakeup Pin Polarity bit for PI8    */\r\n#define  PWR_CR2_WUPP6                          0x00002000U     /*!< Wakeup Pin Polarity bit for PI11   */\r\n\r\n/*******************  Bit definition for PWR_CSR2 register  ********************/\r\n#define  PWR_CSR2_WUPF1                         0x00000001U     /*!< Wakeup Pin Flag for PA0            */\r\n#define  PWR_CSR2_WUPF2                         0x00000002U     /*!< Wakeup Pin Flag for PA2            */\r\n#define  PWR_CSR2_WUPF3                         0x00000004U     /*!< Wakeup Pin Flag for PC1            */\r\n#define  PWR_CSR2_WUPF4                         0x00000008U     /*!< Wakeup Pin Flag for PC13           */\r\n#define  PWR_CSR2_WUPF5                         0x00000010U     /*!< Wakeup Pin Flag for PI8            */\r\n#define  PWR_CSR2_WUPF6                         0x00000020U     /*!< Wakeup Pin Flag for PI11           */\r\n#define  PWR_CSR2_EWUP1                         0x00000100U     /*!< Enable Wakeup Pin PA0              */\r\n#define  PWR_CSR2_EWUP2                         0x00000200U     /*!< Enable Wakeup Pin PA2              */\r\n#define  PWR_CSR2_EWUP3                         0x00000400U     /*!< Enable Wakeup Pin PC1              */\r\n#define  PWR_CSR2_EWUP4                         0x00000800U     /*!< Enable Wakeup Pin PC13             */\r\n#define  PWR_CSR2_EWUP5                         0x00001000U     /*!< Enable Wakeup Pin PI8              */\r\n#define  PWR_CSR2_EWUP6                         0x00002000U     /*!< Enable Wakeup Pin PI11             */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                    QUADSPI                                 */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/* QUADSPI IP version */\r\n#define QSPI1_V1_0\r\n/*****************  Bit definition for QUADSPI_CR register  *******************/\r\n#define  QUADSPI_CR_EN                           0x00000001U            /*!< Enable                            */\r\n#define  QUADSPI_CR_ABORT                        0x00000002U            /*!< Abort request                     */\r\n#define  QUADSPI_CR_DMAEN                        0x00000004U            /*!< DMA Enable                        */\r\n#define  QUADSPI_CR_TCEN                         0x00000008U            /*!< Timeout Counter Enable            */\r\n#define  QUADSPI_CR_SSHIFT                       0x00000010U            /*!< Sample Shift                      */\r\n#define  QUADSPI_CR_DFM                          0x00000040U            /*!< Dual Flash Mode                   */\r\n#define  QUADSPI_CR_FSEL                         0x00000080U            /*!< Flash Select                      */\r\n#define  QUADSPI_CR_FTHRES                       0x00001F00U            /*!< FTHRES[4:0] FIFO Level            */\r\n#define  QUADSPI_CR_FTHRES_0                     0x00000100U            /*!< Bit 0 */\r\n#define  QUADSPI_CR_FTHRES_1                     0x00000200U            /*!< Bit 1 */\r\n#define  QUADSPI_CR_FTHRES_2                     0x00000400U            /*!< Bit 2 */\r\n#define  QUADSPI_CR_FTHRES_3                     0x00000800U            /*!< Bit 3 */\r\n#define  QUADSPI_CR_FTHRES_4                     0x00001000U            /*!< Bit 4 */\r\n#define  QUADSPI_CR_TEIE                         0x00010000U            /*!< Transfer Error Interrupt Enable    */\r\n#define  QUADSPI_CR_TCIE                         0x00020000U            /*!< Transfer Complete Interrupt Enable */\r\n#define  QUADSPI_CR_FTIE                         0x00040000U            /*!< FIFO Threshold Interrupt Enable    */\r\n#define  QUADSPI_CR_SMIE                         0x00080000U            /*!< Status Match Interrupt Enable      */\r\n#define  QUADSPI_CR_TOIE                         0x00100000U            /*!< TimeOut Interrupt Enable           */\r\n#define  QUADSPI_CR_APMS                         0x00400000U            /*!< Bit 1                              */\r\n#define  QUADSPI_CR_PMM                          0x00800000U            /*!< Polling Match Mode                 */\r\n#define  QUADSPI_CR_PRESCALER                    0xFF000000U            /*!< PRESCALER[7:0] Clock prescaler     */\r\n#define  QUADSPI_CR_PRESCALER_0                  0x01000000U            /*!< Bit 0 */\r\n#define  QUADSPI_CR_PRESCALER_1                  0x02000000U            /*!< Bit 1 */\r\n#define  QUADSPI_CR_PRESCALER_2                  0x04000000U            /*!< Bit 2 */\r\n#define  QUADSPI_CR_PRESCALER_3                  0x08000000U            /*!< Bit 3 */\r\n#define  QUADSPI_CR_PRESCALER_4                  0x10000000U            /*!< Bit 4 */\r\n#define  QUADSPI_CR_PRESCALER_5                  0x20000000U            /*!< Bit 5 */\r\n#define  QUADSPI_CR_PRESCALER_6                  0x40000000U            /*!< Bit 6 */\r\n#define  QUADSPI_CR_PRESCALER_7                  0x80000000U            /*!< Bit 7 */\r\n\r\n/*****************  Bit definition for QUADSPI_DCR register  ******************/\r\n#define  QUADSPI_DCR_CKMODE                      0x00000001U            /*!< Mode 0 / Mode 3                 */\r\n#define  QUADSPI_DCR_CSHT                        0x00000700U            /*!< CSHT[2:0]: ChipSelect High Time */\r\n#define  QUADSPI_DCR_CSHT_0                      0x00000100U            /*!< Bit 0 */\r\n#define  QUADSPI_DCR_CSHT_1                      0x00000200U            /*!< Bit 1 */\r\n#define  QUADSPI_DCR_CSHT_2                      0x00000400U            /*!< Bit 2 */\r\n#define  QUADSPI_DCR_FSIZE                       0x001F0000U            /*!< FSIZE[4:0]: Flash Size          */\r\n#define  QUADSPI_DCR_FSIZE_0                     0x00010000U            /*!< Bit 0 */\r\n#define  QUADSPI_DCR_FSIZE_1                     0x00020000U            /*!< Bit 1 */\r\n#define  QUADSPI_DCR_FSIZE_2                     0x00040000U            /*!< Bit 2 */\r\n#define  QUADSPI_DCR_FSIZE_3                     0x00080000U            /*!< Bit 3 */\r\n#define  QUADSPI_DCR_FSIZE_4                     0x00100000U            /*!< Bit 4 */\r\n\r\n/******************  Bit definition for QUADSPI_SR register  *******************/\r\n#define  QUADSPI_SR_TEF                          0x00000001U             /*!< Transfer Error Flag    */\r\n#define  QUADSPI_SR_TCF                          0x00000002U             /*!< Transfer Complete Flag */\r\n#define  QUADSPI_SR_FTF                          0x00000004U             /*!< FIFO Threshlod Flag    */\r\n#define  QUADSPI_SR_SMF                          0x00000008U             /*!< Status Match Flag      */\r\n#define  QUADSPI_SR_TOF                          0x00000010U             /*!< Timeout Flag           */\r\n#define  QUADSPI_SR_BUSY                         0x00000020U             /*!< Busy                   */\r\n#define  QUADSPI_SR_FLEVEL                       0x00001F00U             /*!< FIFO Threshlod Flag    */\r\n#define  QUADSPI_SR_FLEVEL_0                     0x00000100U             /*!< Bit 0 */\r\n#define  QUADSPI_SR_FLEVEL_1                     0x00000200U             /*!< Bit 1 */\r\n#define  QUADSPI_SR_FLEVEL_2                     0x00000400U             /*!< Bit 2 */\r\n#define  QUADSPI_SR_FLEVEL_3                     0x00000800U             /*!< Bit 3 */\r\n#define  QUADSPI_SR_FLEVEL_4                     0x00001000U             /*!< Bit 4 */\r\n\r\n/******************  Bit definition for QUADSPI_FCR register  ******************/\r\n#define  QUADSPI_FCR_CTEF                        0x00000001U             /*!< Clear Transfer Error Flag    */\r\n#define  QUADSPI_FCR_CTCF                        0x00000002U             /*!< Clear Transfer Complete Flag */\r\n#define  QUADSPI_FCR_CSMF                        0x00000008U             /*!< Clear Status Match Flag      */\r\n#define  QUADSPI_FCR_CTOF                        0x00000010U             /*!< Clear Timeout Flag           */\r\n\r\n/******************  Bit definition for QUADSPI_DLR register  ******************/\r\n#define  QUADSPI_DLR_DL                          0xFFFFFFFFU             /*!< DL[31:0]: Data Length */\r\n\r\n/******************  Bit definition for QUADSPI_CCR register  ******************/\r\n#define  QUADSPI_CCR_INSTRUCTION                  0x000000FFU            /*!< INSTRUCTION[7:0]: Instruction    */\r\n#define  QUADSPI_CCR_INSTRUCTION_0                0x00000001U            /*!< Bit 0 */\r\n#define  QUADSPI_CCR_INSTRUCTION_1                0x00000002U            /*!< Bit 1 */\r\n#define  QUADSPI_CCR_INSTRUCTION_2                0x00000004U            /*!< Bit 2 */\r\n#define  QUADSPI_CCR_INSTRUCTION_3                0x00000008U            /*!< Bit 3 */\r\n#define  QUADSPI_CCR_INSTRUCTION_4                0x00000010U            /*!< Bit 4 */\r\n#define  QUADSPI_CCR_INSTRUCTION_5                0x00000020U            /*!< Bit 5 */\r\n#define  QUADSPI_CCR_INSTRUCTION_6                0x00000040U            /*!< Bit 6 */\r\n#define  QUADSPI_CCR_INSTRUCTION_7                0x00000080U            /*!< Bit 7 */\r\n#define  QUADSPI_CCR_IMODE                        0x00000300U            /*!< IMODE[1:0]: Instruction Mode      */\r\n#define  QUADSPI_CCR_IMODE_0                      0x00000100U            /*!< Bit 0 */\r\n#define  QUADSPI_CCR_IMODE_1                      0x00000200U            /*!< Bit 1 */\r\n#define  QUADSPI_CCR_ADMODE                       0x00000C00U            /*!< ADMODE[1:0]: Address Mode         */\r\n#define  QUADSPI_CCR_ADMODE_0                     0x00000400U            /*!< Bit 0 */\r\n#define  QUADSPI_CCR_ADMODE_1                     0x00000800U            /*!< Bit 1 */\r\n#define  QUADSPI_CCR_ADSIZE                       0x00003000U            /*!< ADSIZE[1:0]: Address Size         */\r\n#define  QUADSPI_CCR_ADSIZE_0                     0x00001000U            /*!< Bit 0 */\r\n#define  QUADSPI_CCR_ADSIZE_1                     0x00002000U            /*!< Bit 1 */\r\n#define  QUADSPI_CCR_ABMODE                       0x0000C000U            /*!< ABMODE[1:0]: Alternate Bytes Mode */\r\n#define  QUADSPI_CCR_ABMODE_0                     0x00004000U            /*!< Bit 0 */\r\n#define  QUADSPI_CCR_ABMODE_1                     0x00008000U            /*!< Bit 1 */\r\n#define  QUADSPI_CCR_ABSIZE                       0x00030000U            /*!< ABSIZE[1:0]: Instruction Mode     */\r\n#define  QUADSPI_CCR_ABSIZE_0                     0x00010000U            /*!< Bit 0 */\r\n#define  QUADSPI_CCR_ABSIZE_1                     0x00020000U            /*!< Bit 1 */\r\n#define  QUADSPI_CCR_DCYC                         0x007C0000U            /*!< DCYC[4:0]: Dummy Cycles           */\r\n#define  QUADSPI_CCR_DCYC_0                       0x00040000U            /*!< Bit 0 */\r\n#define  QUADSPI_CCR_DCYC_1                       0x00080000U            /*!< Bit 1 */\r\n#define  QUADSPI_CCR_DCYC_2                       0x00100000U            /*!< Bit 2 */\r\n#define  QUADSPI_CCR_DCYC_3                       0x00200000U            /*!< Bit 3 */\r\n#define  QUADSPI_CCR_DCYC_4                       0x00400000U            /*!< Bit 4 */\r\n#define  QUADSPI_CCR_DMODE                        0x03000000U            /*!< DMODE[1:0]: Data Mode              */\r\n#define  QUADSPI_CCR_DMODE_0                      0x01000000U            /*!< Bit 0 */\r\n#define  QUADSPI_CCR_DMODE_1                      0x02000000U            /*!< Bit 1 */\r\n#define  QUADSPI_CCR_FMODE                        0x0C000000U            /*!< FMODE[1:0]: Functional Mode        */\r\n#define  QUADSPI_CCR_FMODE_0                      0x04000000U            /*!< Bit 0 */\r\n#define  QUADSPI_CCR_FMODE_1                      0x08000000U            /*!< Bit 1 */\r\n#define  QUADSPI_CCR_SIOO                         0x10000000U            /*!< SIOO: Send Instruction Only Once Mode */\r\n#define  QUADSPI_CCR_DHHC                         0x40000000U            /*!< DHHC: Delay Half Hclk Cycle           */\r\n#define  QUADSPI_CCR_DDRM                         0x80000000U            /*!< DDRM: Double Data Rate Mode           */ \r\n/******************  Bit definition for QUADSPI_AR register  *******************/\r\n#define  QUADSPI_AR_ADDRESS                       0xFFFFFFFFU            /*!< ADDRESS[31:0]: Address */\r\n\r\n/******************  Bit definition for QUADSPI_ABR register  ******************/\r\n#define  QUADSPI_ABR_ALTERNATE                    0xFFFFFFFFU            /*!< ALTERNATE[31:0]: Alternate Bytes */\r\n\r\n/******************  Bit definition for QUADSPI_DR register  *******************/\r\n#define  QUADSPI_DR_DATA                          0xFFFFFFFFU            /*!< DATA[31:0]: Data */\r\n\r\n/******************  Bit definition for QUADSPI_PSMKR register  ****************/\r\n#define  QUADSPI_PSMKR_MASK                       0xFFFFFFFFU            /*!< MASK[31:0]: Status Mask */\r\n\r\n/******************  Bit definition for QUADSPI_PSMAR register  ****************/\r\n#define  QUADSPI_PSMAR_MATCH                      0xFFFFFFFFU            /*!< MATCH[31:0]: Status Match */\r\n\r\n/******************  Bit definition for QUADSPI_PIR register  *****************/\r\n#define  QUADSPI_PIR_INTERVAL                     0x0000FFFFU            /*!< INTERVAL[15:0]: Polling Interval */\r\n\r\n/******************  Bit definition for QUADSPI_LPTR register  *****************/\r\n#define  QUADSPI_LPTR_TIMEOUT                     0x0000FFFFU            /*!< TIMEOUT[15:0]: Timeout period */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                         Reset and Clock Control            */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bit definition for RCC_CR register  ********************/\r\n#define  RCC_CR_HSION                        0x00000001U\r\n#define  RCC_CR_HSIRDY                       0x00000002U\r\n#define  RCC_CR_HSITRIM                      0x000000F8U\r\n#define  RCC_CR_HSITRIM_0                    0x00000008U /*!<Bit 0 */\r\n#define  RCC_CR_HSITRIM_1                    0x00000010U /*!<Bit 1 */\r\n#define  RCC_CR_HSITRIM_2                    0x00000020U /*!<Bit 2 */\r\n#define  RCC_CR_HSITRIM_3                    0x00000040U /*!<Bit 3 */\r\n#define  RCC_CR_HSITRIM_4                    0x00000080U /*!<Bit 4 */\r\n#define  RCC_CR_HSICAL                       0x0000FF00U\r\n#define  RCC_CR_HSICAL_0                     0x00000100U /*!<Bit 0 */\r\n#define  RCC_CR_HSICAL_1                     0x00000200U /*!<Bit 1 */\r\n#define  RCC_CR_HSICAL_2                     0x00000400U /*!<Bit 2 */\r\n#define  RCC_CR_HSICAL_3                     0x00000800U /*!<Bit 3 */\r\n#define  RCC_CR_HSICAL_4                     0x00001000U /*!<Bit 4 */\r\n#define  RCC_CR_HSICAL_5                     0x00002000U /*!<Bit 5 */\r\n#define  RCC_CR_HSICAL_6                     0x00004000U /*!<Bit 6 */\r\n#define  RCC_CR_HSICAL_7                     0x00008000U /*!<Bit 7 */\r\n#define  RCC_CR_HSEON                        0x00010000U\r\n#define  RCC_CR_HSERDY                       0x00020000U\r\n#define  RCC_CR_HSEBYP                       0x00040000U\r\n#define  RCC_CR_CSSON                        0x00080000U\r\n#define  RCC_CR_PLLON                        0x01000000U\r\n#define  RCC_CR_PLLRDY                       0x02000000U\r\n#define  RCC_CR_PLLI2SON                     0x04000000U\r\n#define  RCC_CR_PLLI2SRDY                    0x08000000U\r\n#define  RCC_CR_PLLSAION                     0x10000000U\r\n#define  RCC_CR_PLLSAIRDY                    0x20000000U\r\n\r\n/********************  Bit definition for RCC_PLLCFGR register  ***************/\r\n#define  RCC_PLLCFGR_PLLM                    0x0000003FU\r\n#define  RCC_PLLCFGR_PLLM_0                  0x00000001U\r\n#define  RCC_PLLCFGR_PLLM_1                  0x00000002U\r\n#define  RCC_PLLCFGR_PLLM_2                  0x00000004U\r\n#define  RCC_PLLCFGR_PLLM_3                  0x00000008U\r\n#define  RCC_PLLCFGR_PLLM_4                  0x00000010U\r\n#define  RCC_PLLCFGR_PLLM_5                  0x00000020U\r\n#define  RCC_PLLCFGR_PLLN                    0x00007FC0U\r\n#define  RCC_PLLCFGR_PLLN_0                  0x00000040U\r\n#define  RCC_PLLCFGR_PLLN_1                  0x00000080U\r\n#define  RCC_PLLCFGR_PLLN_2                  0x00000100U\r\n#define  RCC_PLLCFGR_PLLN_3                  0x00000200U\r\n#define  RCC_PLLCFGR_PLLN_4                  0x00000400U\r\n#define  RCC_PLLCFGR_PLLN_5                  0x00000800U\r\n#define  RCC_PLLCFGR_PLLN_6                  0x00001000U\r\n#define  RCC_PLLCFGR_PLLN_7                  0x00002000U\r\n#define  RCC_PLLCFGR_PLLN_8                  0x00004000U\r\n#define  RCC_PLLCFGR_PLLP                    0x00030000U\r\n#define  RCC_PLLCFGR_PLLP_0                  0x00010000U\r\n#define  RCC_PLLCFGR_PLLP_1                  0x00020000U\r\n#define  RCC_PLLCFGR_PLLSRC                  0x00400000U\r\n#define  RCC_PLLCFGR_PLLSRC_HSE              0x00400000U\r\n#define  RCC_PLLCFGR_PLLSRC_HSI              0x00000000U\r\n#define  RCC_PLLCFGR_PLLQ                    0x0F000000U\r\n#define  RCC_PLLCFGR_PLLQ_0                  0x01000000U\r\n#define  RCC_PLLCFGR_PLLQ_1                  0x02000000U\r\n#define  RCC_PLLCFGR_PLLQ_2                  0x04000000U\r\n#define  RCC_PLLCFGR_PLLQ_3                  0x08000000U\r\n\r\n\r\n/********************  Bit definition for RCC_CFGR register  ******************/\r\n/*!< SW configuration */\r\n#define  RCC_CFGR_SW                         0x00000003U        /*!< SW[1:0] bits (System clock Switch) */\r\n#define  RCC_CFGR_SW_0                       0x00000001U        /*!< Bit 0 */\r\n#define  RCC_CFGR_SW_1                       0x00000002U        /*!< Bit 1 */\r\n#define  RCC_CFGR_SW_HSI                     0x00000000U        /*!< HSI selected as system clock */\r\n#define  RCC_CFGR_SW_HSE                     0x00000001U        /*!< HSE selected as system clock */\r\n#define  RCC_CFGR_SW_PLL                     0x00000002U        /*!< PLL selected as system clock */\r\n\r\n/*!< SWS configuration */\r\n#define  RCC_CFGR_SWS                        0x0000000CU        /*!< SWS[1:0] bits (System Clock Switch Status) */\r\n#define  RCC_CFGR_SWS_0                      0x00000004U        /*!< Bit 0 */\r\n#define  RCC_CFGR_SWS_1                      0x00000008U        /*!< Bit 1 */\r\n#define  RCC_CFGR_SWS_HSI                    0x00000000U        /*!< HSI oscillator used as system clock */\r\n#define  RCC_CFGR_SWS_HSE                    0x00000004U        /*!< HSE oscillator used as system clock */\r\n#define  RCC_CFGR_SWS_PLL                    0x00000008U        /*!< PLL used as system clock */\r\n\r\n/*!< HPRE configuration */\r\n#define  RCC_CFGR_HPRE                       0x000000F0U        /*!< HPRE[3:0] bits (AHB prescaler) */\r\n#define  RCC_CFGR_HPRE_0                     0x00000010U        /*!< Bit 0 */\r\n#define  RCC_CFGR_HPRE_1                     0x00000020U        /*!< Bit 1 */\r\n#define  RCC_CFGR_HPRE_2                     0x00000040U        /*!< Bit 2 */\r\n#define  RCC_CFGR_HPRE_3                     0x00000080U        /*!< Bit 3 */\r\n\r\n#define  RCC_CFGR_HPRE_DIV1                  0x00000000U        /*!< SYSCLK not divided */\r\n#define  RCC_CFGR_HPRE_DIV2                  0x00000080U        /*!< SYSCLK divided by 2 */\r\n#define  RCC_CFGR_HPRE_DIV4                  0x00000090U        /*!< SYSCLK divided by 4 */\r\n#define  RCC_CFGR_HPRE_DIV8                  0x000000A0U        /*!< SYSCLK divided by 8 */\r\n#define  RCC_CFGR_HPRE_DIV16                 0x000000B0U        /*!< SYSCLK divided by 16 */\r\n#define  RCC_CFGR_HPRE_DIV64                 0x000000C0U        /*!< SYSCLK divided by 64 */\r\n#define  RCC_CFGR_HPRE_DIV128                0x000000D0U        /*!< SYSCLK divided by 128 */\r\n#define  RCC_CFGR_HPRE_DIV256                0x000000E0U        /*!< SYSCLK divided by 256 */\r\n#define  RCC_CFGR_HPRE_DIV512                0x000000F0U        /*!< SYSCLK divided by 512 */\r\n\r\n/*!< PPRE1 configuration */\r\n#define  RCC_CFGR_PPRE1                      0x00001C00U        /*!< PRE1[2:0] bits (APB1 prescaler) */\r\n#define  RCC_CFGR_PPRE1_0                    0x00000400U        /*!< Bit 0 */\r\n#define  RCC_CFGR_PPRE1_1                    0x00000800U        /*!< Bit 1 */\r\n#define  RCC_CFGR_PPRE1_2                    0x00001000U        /*!< Bit 2 */\r\n\r\n#define  RCC_CFGR_PPRE1_DIV1                 0x00000000U        /*!< HCLK not divided */\r\n#define  RCC_CFGR_PPRE1_DIV2                 0x00001000U        /*!< HCLK divided by 2 */\r\n#define  RCC_CFGR_PPRE1_DIV4                 0x00001400U        /*!< HCLK divided by 4 */\r\n#define  RCC_CFGR_PPRE1_DIV8                 0x00001800U        /*!< HCLK divided by 8 */\r\n#define  RCC_CFGR_PPRE1_DIV16                0x00001C00U        /*!< HCLK divided by 16 */\r\n\r\n/*!< PPRE2 configuration */\r\n#define  RCC_CFGR_PPRE2                      0x0000E000U        /*!< PRE2[2:0] bits (APB2 prescaler) */\r\n#define  RCC_CFGR_PPRE2_0                    0x00002000U        /*!< Bit 0 */\r\n#define  RCC_CFGR_PPRE2_1                    0x00004000U        /*!< Bit 1 */\r\n#define  RCC_CFGR_PPRE2_2                    0x00008000U        /*!< Bit 2 */\r\n\r\n#define  RCC_CFGR_PPRE2_DIV1                 0x00000000U        /*!< HCLK not divided */\r\n#define  RCC_CFGR_PPRE2_DIV2                 0x00008000U        /*!< HCLK divided by 2 */\r\n#define  RCC_CFGR_PPRE2_DIV4                 0x0000A000U        /*!< HCLK divided by 4 */\r\n#define  RCC_CFGR_PPRE2_DIV8                 0x0000C000U        /*!< HCLK divided by 8 */\r\n#define  RCC_CFGR_PPRE2_DIV16                0x0000E000U        /*!< HCLK divided by 16 */\r\n\r\n/*!< RTCPRE configuration */\r\n#define  RCC_CFGR_RTCPRE                     0x001F0000U\r\n#define  RCC_CFGR_RTCPRE_0                   0x00010000U\r\n#define  RCC_CFGR_RTCPRE_1                   0x00020000U\r\n#define  RCC_CFGR_RTCPRE_2                   0x00040000U\r\n#define  RCC_CFGR_RTCPRE_3                   0x00080000U\r\n#define  RCC_CFGR_RTCPRE_4                   0x00100000U\r\n\r\n/*!< MCO1 configuration */\r\n#define  RCC_CFGR_MCO1                       0x00600000U\r\n#define  RCC_CFGR_MCO1_0                     0x00200000U\r\n#define  RCC_CFGR_MCO1_1                     0x00400000U\r\n\r\n#define  RCC_CFGR_I2SSRC                     0x00800000U\r\n\r\n#define  RCC_CFGR_MCO1PRE                    0x07000000U\r\n#define  RCC_CFGR_MCO1PRE_0                  0x01000000U\r\n#define  RCC_CFGR_MCO1PRE_1                  0x02000000U\r\n#define  RCC_CFGR_MCO1PRE_2                  0x04000000U\r\n\r\n#define  RCC_CFGR_MCO2PRE                    0x38000000U\r\n#define  RCC_CFGR_MCO2PRE_0                  0x08000000U\r\n#define  RCC_CFGR_MCO2PRE_1                  0x10000000U\r\n#define  RCC_CFGR_MCO2PRE_2                  0x20000000U\r\n\r\n#define  RCC_CFGR_MCO2                       0xC0000000U\r\n#define  RCC_CFGR_MCO2_0                     0x40000000U\r\n#define  RCC_CFGR_MCO2_1                     0x80000000U\r\n\r\n/********************  Bit definition for RCC_CIR register  *******************/\r\n#define  RCC_CIR_LSIRDYF                     0x00000001U\r\n#define  RCC_CIR_LSERDYF                     0x00000002U\r\n#define  RCC_CIR_HSIRDYF                     0x00000004U\r\n#define  RCC_CIR_HSERDYF                     0x00000008U\r\n#define  RCC_CIR_PLLRDYF                     0x00000010U\r\n#define  RCC_CIR_PLLI2SRDYF                  0x00000020U\r\n#define  RCC_CIR_PLLSAIRDYF                  0x00000040U\r\n#define  RCC_CIR_CSSF                        0x00000080U\r\n#define  RCC_CIR_LSIRDYIE                    0x00000100U\r\n#define  RCC_CIR_LSERDYIE                    0x00000200U\r\n#define  RCC_CIR_HSIRDYIE                    0x00000400U\r\n#define  RCC_CIR_HSERDYIE                    0x00000800U\r\n#define  RCC_CIR_PLLRDYIE                    0x00001000U\r\n#define  RCC_CIR_PLLI2SRDYIE                 0x00002000U\r\n#define  RCC_CIR_PLLSAIRDYIE                 0x00004000U\r\n#define  RCC_CIR_LSIRDYC                     0x00010000U\r\n#define  RCC_CIR_LSERDYC                     0x00020000U\r\n#define  RCC_CIR_HSIRDYC                     0x00040000U\r\n#define  RCC_CIR_HSERDYC                     0x00080000U\r\n#define  RCC_CIR_PLLRDYC                     0x00100000U\r\n#define  RCC_CIR_PLLI2SRDYC                  0x00200000U\r\n#define  RCC_CIR_PLLSAIRDYC                  0x00400000U\r\n#define  RCC_CIR_CSSC                        0x00800000U\r\n\r\n/********************  Bit definition for RCC_AHB1RSTR register  **************/\r\n#define  RCC_AHB1RSTR_GPIOARST               0x00000001U\r\n#define  RCC_AHB1RSTR_GPIOBRST               0x00000002U\r\n#define  RCC_AHB1RSTR_GPIOCRST               0x00000004U\r\n#define  RCC_AHB1RSTR_GPIODRST               0x00000008U\r\n#define  RCC_AHB1RSTR_GPIOERST               0x00000010U\r\n#define  RCC_AHB1RSTR_GPIOFRST               0x00000020U\r\n#define  RCC_AHB1RSTR_GPIOGRST               0x00000040U\r\n#define  RCC_AHB1RSTR_GPIOHRST               0x00000080U\r\n#define  RCC_AHB1RSTR_GPIOIRST               0x00000100U\r\n#define  RCC_AHB1RSTR_GPIOJRST               0x00000200U\r\n#define  RCC_AHB1RSTR_GPIOKRST               0x00000400U\r\n#define  RCC_AHB1RSTR_CRCRST                 0x00001000U\r\n#define  RCC_AHB1RSTR_DMA1RST                0x00200000U\r\n#define  RCC_AHB1RSTR_DMA2RST                0x00400000U\r\n#define  RCC_AHB1RSTR_DMA2DRST               0x00800000U\r\n#define  RCC_AHB1RSTR_ETHMACRST              0x02000000U\r\n#define  RCC_AHB1RSTR_OTGHRST                0x20000000U\r\n\r\n/********************  Bit definition for RCC_AHB2RSTR register  **************/\r\n#define  RCC_AHB2RSTR_DCMIRST                0x00000001U\r\n#define  RCC_AHB2RSTR_RNGRST                 0x00000040U\r\n#define  RCC_AHB2RSTR_OTGFSRST               0x00000080U\r\n\r\n/********************  Bit definition for RCC_AHB3RSTR register  **************/\r\n\r\n#define  RCC_AHB3RSTR_FMCRST                 0x00000001U\r\n#define  RCC_AHB3RSTR_QSPIRST                0x00000002U\r\n\r\n/********************  Bit definition for RCC_APB1RSTR register  **************/\r\n#define  RCC_APB1RSTR_TIM2RST                0x00000001U\r\n#define  RCC_APB1RSTR_TIM3RST                0x00000002U\r\n#define  RCC_APB1RSTR_TIM4RST                0x00000004U\r\n#define  RCC_APB1RSTR_TIM5RST                0x00000008U\r\n#define  RCC_APB1RSTR_TIM6RST                0x00000010U\r\n#define  RCC_APB1RSTR_TIM7RST                0x00000020U\r\n#define  RCC_APB1RSTR_TIM12RST               0x00000040U\r\n#define  RCC_APB1RSTR_TIM13RST               0x00000080U\r\n#define  RCC_APB1RSTR_TIM14RST               0x00000100U\r\n#define  RCC_APB1RSTR_LPTIM1RST              0x00000200U\r\n#define  RCC_APB1RSTR_WWDGRST                0x00000800U\r\n#define  RCC_APB1RSTR_SPI2RST                0x00004000U\r\n#define  RCC_APB1RSTR_SPI3RST                0x00008000U\r\n#define  RCC_APB1RSTR_SPDIFRXRST             0x00010000U\r\n#define  RCC_APB1RSTR_USART2RST              0x00020000U\r\n#define  RCC_APB1RSTR_USART3RST              0x00040000U\r\n#define  RCC_APB1RSTR_UART4RST               0x00080000U\r\n#define  RCC_APB1RSTR_UART5RST               0x00100000U\r\n#define  RCC_APB1RSTR_I2C1RST                0x00200000U\r\n#define  RCC_APB1RSTR_I2C2RST                0x00400000U\r\n#define  RCC_APB1RSTR_I2C3RST                0x00800000U\r\n#define  RCC_APB1RSTR_I2C4RST                0x01000000U\r\n#define  RCC_APB1RSTR_CAN1RST                0x02000000U\r\n#define  RCC_APB1RSTR_CAN2RST                0x04000000U\r\n#define  RCC_APB1RSTR_CECRST                 0x08000000U\r\n#define  RCC_APB1RSTR_PWRRST                 0x10000000U\r\n#define  RCC_APB1RSTR_DACRST                 0x20000000U\r\n#define  RCC_APB1RSTR_UART7RST               0x40000000U\r\n#define  RCC_APB1RSTR_UART8RST               0x80000000U\r\n\r\n/********************  Bit definition for RCC_APB2RSTR register  **************/\r\n#define  RCC_APB2RSTR_TIM1RST                0x00000001U\r\n#define  RCC_APB2RSTR_TIM8RST                0x00000002U\r\n#define  RCC_APB2RSTR_USART1RST              0x00000010U\r\n#define  RCC_APB2RSTR_USART6RST              0x00000020U\r\n#define  RCC_APB2RSTR_ADCRST                 0x00000100U\r\n#define  RCC_APB2RSTR_SDMMC1RST              0x00000800U\r\n#define  RCC_APB2RSTR_SPI1RST                0x00001000U\r\n#define  RCC_APB2RSTR_SPI4RST                0x00002000U\r\n#define  RCC_APB2RSTR_SYSCFGRST              0x00004000U\r\n#define  RCC_APB2RSTR_TIM9RST                0x00010000U\r\n#define  RCC_APB2RSTR_TIM10RST               0x00020000U\r\n#define  RCC_APB2RSTR_TIM11RST               0x00040000U\r\n#define  RCC_APB2RSTR_SPI5RST                0x00100000U\r\n#define  RCC_APB2RSTR_SPI6RST                0x00200000U\r\n#define  RCC_APB2RSTR_SAI1RST                0x00400000U\r\n#define  RCC_APB2RSTR_SAI2RST                0x00800000U\r\n#define  RCC_APB2RSTR_LTDCRST                0x04000000U\r\n\r\n/********************  Bit definition for RCC_AHB1ENR register  ***************/\r\n#define  RCC_AHB1ENR_GPIOAEN                 0x00000001U\r\n#define  RCC_AHB1ENR_GPIOBEN                 0x00000002U\r\n#define  RCC_AHB1ENR_GPIOCEN                 0x00000004U\r\n#define  RCC_AHB1ENR_GPIODEN                 0x00000008U\r\n#define  RCC_AHB1ENR_GPIOEEN                 0x00000010U\r\n#define  RCC_AHB1ENR_GPIOFEN                 0x00000020U\r\n#define  RCC_AHB1ENR_GPIOGEN                 0x00000040U\r\n#define  RCC_AHB1ENR_GPIOHEN                 0x00000080U\r\n#define  RCC_AHB1ENR_GPIOIEN                 0x00000100U\r\n#define  RCC_AHB1ENR_GPIOJEN                 0x00000200U\r\n#define  RCC_AHB1ENR_GPIOKEN                 0x00000400U\r\n#define  RCC_AHB1ENR_CRCEN                   0x00001000U\r\n#define  RCC_AHB1ENR_BKPSRAMEN               0x00040000U\r\n#define  RCC_AHB1ENR_DTCMRAMEN               0x00100000U\r\n#define  RCC_AHB1ENR_DMA1EN                  0x00200000U\r\n#define  RCC_AHB1ENR_DMA2EN                  0x00400000U\r\n#define  RCC_AHB1ENR_DMA2DEN                 0x00800000U\r\n#define  RCC_AHB1ENR_ETHMACEN                0x02000000U\r\n#define  RCC_AHB1ENR_ETHMACTXEN              0x04000000U\r\n#define  RCC_AHB1ENR_ETHMACRXEN              0x08000000U\r\n#define  RCC_AHB1ENR_ETHMACPTPEN             0x10000000U\r\n#define  RCC_AHB1ENR_OTGHSEN                 0x20000000U\r\n#define  RCC_AHB1ENR_OTGHSULPIEN             0x40000000U\r\n\r\n/********************  Bit definition for RCC_AHB2ENR register  ***************/\r\n#define  RCC_AHB2ENR_DCMIEN                  0x00000001U\r\n#define  RCC_AHB2ENR_RNGEN                   0x00000040U\r\n#define  RCC_AHB2ENR_OTGFSEN                 0x00000080U\r\n\r\n/********************  Bit definition for RCC_AHB3ENR register  ***************/\r\n#define  RCC_AHB3ENR_FMCEN                  0x00000001U\r\n#define  RCC_AHB3ENR_QSPIEN                 0x00000002U\r\n\r\n/********************  Bit definition for RCC_APB1ENR register  ***************/\r\n#define  RCC_APB1ENR_TIM2EN                  0x00000001U\r\n#define  RCC_APB1ENR_TIM3EN                  0x00000002U\r\n#define  RCC_APB1ENR_TIM4EN                  0x00000004U\r\n#define  RCC_APB1ENR_TIM5EN                  0x00000008U\r\n#define  RCC_APB1ENR_TIM6EN                  0x00000010U\r\n#define  RCC_APB1ENR_TIM7EN                  0x00000020U\r\n#define  RCC_APB1ENR_TIM12EN                 0x00000040U\r\n#define  RCC_APB1ENR_TIM13EN                 0x00000080U\r\n#define  RCC_APB1ENR_TIM14EN                 0x00000100U\r\n#define  RCC_APB1ENR_LPTIM1EN                0x00000200U\r\n#define  RCC_APB1ENR_WWDGEN                  0x00000800U\r\n#define  RCC_APB1ENR_SPI2EN                  0x00004000U\r\n#define  RCC_APB1ENR_SPI3EN                  0x00008000U\r\n#define  RCC_APB1ENR_SPDIFRXEN               0x00010000U\r\n#define  RCC_APB1ENR_USART2EN                0x00020000U\r\n#define  RCC_APB1ENR_USART3EN                0x00040000U\r\n#define  RCC_APB1ENR_UART4EN                 0x00080000U\r\n#define  RCC_APB1ENR_UART5EN                 0x00100000U\r\n#define  RCC_APB1ENR_I2C1EN                  0x00200000U\r\n#define  RCC_APB1ENR_I2C2EN                  0x00400000U\r\n#define  RCC_APB1ENR_I2C3EN                  0x00800000U\r\n#define  RCC_APB1ENR_I2C4EN                  0x01000000U\r\n#define  RCC_APB1ENR_CAN1EN                  0x02000000U\r\n#define  RCC_APB1ENR_CAN2EN                  0x04000000U\r\n#define  RCC_APB1ENR_CECEN                   0x08000000U\r\n#define  RCC_APB1ENR_PWREN                   0x10000000U\r\n#define  RCC_APB1ENR_DACEN                   0x20000000U\r\n#define  RCC_APB1ENR_UART7EN                 0x40000000U\r\n#define  RCC_APB1ENR_UART8EN                 0x80000000U\r\n\r\n/********************  Bit definition for RCC_APB2ENR register  ***************/\r\n#define  RCC_APB2ENR_TIM1EN                  0x00000001U\r\n#define  RCC_APB2ENR_TIM8EN                  0x00000002U\r\n#define  RCC_APB2ENR_USART1EN                0x00000010U\r\n#define  RCC_APB2ENR_USART6EN                0x00000020U\r\n#define  RCC_APB2ENR_ADC1EN                  0x00000100U\r\n#define  RCC_APB2ENR_ADC2EN                  0x00000200U\r\n#define  RCC_APB2ENR_ADC3EN                  0x00000400U\r\n#define  RCC_APB2ENR_SDMMC1EN                0x00000800U\r\n#define  RCC_APB2ENR_SPI1EN                  0x00001000U\r\n#define  RCC_APB2ENR_SPI4EN                  0x00002000U\r\n#define  RCC_APB2ENR_SYSCFGEN                0x00004000U\r\n#define  RCC_APB2ENR_TIM9EN                  0x00010000U\r\n#define  RCC_APB2ENR_TIM10EN                 0x00020000U\r\n#define  RCC_APB2ENR_TIM11EN                 0x00040000U\r\n#define  RCC_APB2ENR_SPI5EN                  0x00100000U\r\n#define  RCC_APB2ENR_SPI6EN                  0x00200000U\r\n#define  RCC_APB2ENR_SAI1EN                  0x00400000U\r\n#define  RCC_APB2ENR_SAI2EN                  0x00800000U\r\n#define  RCC_APB2ENR_LTDCEN                  0x04000000U\r\n\r\n/********************  Bit definition for RCC_AHB1LPENR register  *************/\r\n#define  RCC_AHB1LPENR_GPIOALPEN             0x00000001U\r\n#define  RCC_AHB1LPENR_GPIOBLPEN             0x00000002U\r\n#define  RCC_AHB1LPENR_GPIOCLPEN             0x00000004U\r\n#define  RCC_AHB1LPENR_GPIODLPEN             0x00000008U\r\n#define  RCC_AHB1LPENR_GPIOELPEN             0x00000010U\r\n#define  RCC_AHB1LPENR_GPIOFLPEN             0x00000020U\r\n#define  RCC_AHB1LPENR_GPIOGLPEN             0x00000040U\r\n#define  RCC_AHB1LPENR_GPIOHLPEN             0x00000080U\r\n#define  RCC_AHB1LPENR_GPIOILPEN             0x00000100U\r\n#define  RCC_AHB1LPENR_GPIOJLPEN             0x00000200U\r\n#define  RCC_AHB1LPENR_GPIOKLPEN             0x00000400U\r\n#define  RCC_AHB1LPENR_CRCLPEN               0x00001000U\r\n#define  RCC_AHB1LPENR_AXILPEN               0x00002000U\r\n#define  RCC_AHB1LPENR_FLITFLPEN             0x00008000U\r\n#define  RCC_AHB1LPENR_SRAM1LPEN             0x00010000U\r\n#define  RCC_AHB1LPENR_SRAM2LPEN             0x00020000U\r\n#define  RCC_AHB1LPENR_BKPSRAMLPEN           0x00040000U\r\n#define  RCC_AHB1LPENR_DTCMLPEN              0x00100000U\r\n#define  RCC_AHB1LPENR_DMA1LPEN              0x00200000U\r\n#define  RCC_AHB1LPENR_DMA2LPEN              0x00400000U\r\n#define  RCC_AHB1LPENR_DMA2DLPEN             0x00800000U\r\n#define  RCC_AHB1LPENR_ETHMACLPEN            0x02000000U\r\n#define  RCC_AHB1LPENR_ETHMACTXLPEN          0x04000000U\r\n#define  RCC_AHB1LPENR_ETHMACRXLPEN          0x08000000U\r\n#define  RCC_AHB1LPENR_ETHMACPTPLPEN         0x10000000U\r\n#define  RCC_AHB1LPENR_OTGHSLPEN             0x20000000U\r\n#define  RCC_AHB1LPENR_OTGHSULPILPEN         0x40000000U\r\n\r\n/********************  Bit definition for RCC_AHB2LPENR register  *************/\r\n#define  RCC_AHB2LPENR_DCMILPEN              0x00000001U\r\n#define  RCC_AHB2LPENR_RNGLPEN               0x00000040U\r\n#define  RCC_AHB2LPENR_OTGFSLPEN             0x00000080U\r\n\r\n/********************  Bit definition for RCC_AHB3LPENR register  *************/\r\n#define  RCC_AHB3LPENR_FMCLPEN               0x00000001U\r\n#define  RCC_AHB3LPENR_QSPILPEN              0x00000002U\r\n/********************  Bit definition for RCC_APB1LPENR register  *************/\r\n#define  RCC_APB1LPENR_TIM2LPEN              0x00000001U\r\n#define  RCC_APB1LPENR_TIM3LPEN              0x00000002U\r\n#define  RCC_APB1LPENR_TIM4LPEN              0x00000004U\r\n#define  RCC_APB1LPENR_TIM5LPEN              0x00000008U\r\n#define  RCC_APB1LPENR_TIM6LPEN              0x00000010U\r\n#define  RCC_APB1LPENR_TIM7LPEN              0x00000020U\r\n#define  RCC_APB1LPENR_TIM12LPEN             0x00000040U\r\n#define  RCC_APB1LPENR_TIM13LPEN             0x00000080U\r\n#define  RCC_APB1LPENR_TIM14LPEN             0x00000100U\r\n#define  RCC_APB1LPENR_LPTIM1LPEN            0x00000200U\r\n#define  RCC_APB1LPENR_WWDGLPEN              0x00000800U\r\n#define  RCC_APB1LPENR_SPI2LPEN              0x00004000U\r\n#define  RCC_APB1LPENR_SPI3LPEN              0x00008000U\r\n#define  RCC_APB1LPENR_SPDIFRXLPEN           0x00010000U\r\n#define  RCC_APB1LPENR_USART2LPEN            0x00020000U\r\n#define  RCC_APB1LPENR_USART3LPEN            0x00040000U\r\n#define  RCC_APB1LPENR_UART4LPEN             0x00080000U\r\n#define  RCC_APB1LPENR_UART5LPEN             0x00100000U\r\n#define  RCC_APB1LPENR_I2C1LPEN              0x00200000U\r\n#define  RCC_APB1LPENR_I2C2LPEN              0x00400000U\r\n#define  RCC_APB1LPENR_I2C3LPEN              0x00800000U\r\n#define  RCC_APB1LPENR_I2C4LPEN              0x01000000U\r\n#define  RCC_APB1LPENR_CAN1LPEN              0x02000000U\r\n#define  RCC_APB1LPENR_CAN2LPEN              0x04000000U\r\n#define  RCC_APB1LPENR_CECLPEN               0x08000000U\r\n#define  RCC_APB1LPENR_PWRLPEN               0x10000000U\r\n#define  RCC_APB1LPENR_DACLPEN               0x20000000U\r\n#define  RCC_APB1LPENR_UART7LPEN             0x40000000U\r\n#define  RCC_APB1LPENR_UART8LPEN             0x80000000U\r\n\r\n/********************  Bit definition for RCC_APB2LPENR register  *************/\r\n#define  RCC_APB2LPENR_TIM1LPEN              0x00000001U\r\n#define  RCC_APB2LPENR_TIM8LPEN              0x00000002U\r\n#define  RCC_APB2LPENR_USART1LPEN            0x00000010U\r\n#define  RCC_APB2LPENR_USART6LPEN            0x00000020U\r\n#define  RCC_APB2LPENR_ADC1LPEN              0x00000100U\r\n#define  RCC_APB2LPENR_ADC2LPEN              0x00000200U\r\n#define  RCC_APB2LPENR_ADC3LPEN              0x00000400U\r\n#define  RCC_APB2LPENR_SDMMC1LPEN            0x00000800U\r\n#define  RCC_APB2LPENR_SPI1LPEN              0x00001000U\r\n#define  RCC_APB2LPENR_SPI4LPEN              0x00002000U\r\n#define  RCC_APB2LPENR_SYSCFGLPEN            0x00004000U\r\n#define  RCC_APB2LPENR_TIM9LPEN              0x00010000U\r\n#define  RCC_APB2LPENR_TIM10LPEN             0x00020000U\r\n#define  RCC_APB2LPENR_TIM11LPEN             0x00040000U\r\n#define  RCC_APB2LPENR_SPI5LPEN              0x00100000U\r\n#define  RCC_APB2LPENR_SPI6LPEN              0x00200000U\r\n#define  RCC_APB2LPENR_SAI1LPEN              0x00400000U\r\n#define  RCC_APB2LPENR_SAI2LPEN              0x00800000U\r\n#define  RCC_APB2LPENR_LTDCLPEN              0x04000000U\r\n\r\n/********************  Bit definition for RCC_BDCR register  ******************/\r\n#define  RCC_BDCR_LSEON                      0x00000001U\r\n#define  RCC_BDCR_LSERDY                     0x00000002U\r\n#define  RCC_BDCR_LSEBYP                     0x00000004U\r\n#define  RCC_BDCR_LSEDRV                     0x00000018U\r\n#define  RCC_BDCR_LSEDRV_0                   0x00000008U\r\n#define  RCC_BDCR_LSEDRV_1                   0x00000010U\r\n#define  RCC_BDCR_RTCSEL                     0x00000300U\r\n#define  RCC_BDCR_RTCSEL_0                   0x00000100U\r\n#define  RCC_BDCR_RTCSEL_1                   0x00000200U\r\n#define  RCC_BDCR_RTCEN                      0x00008000U\r\n#define  RCC_BDCR_BDRST                      0x00010000U\r\n\r\n/********************  Bit definition for RCC_CSR register  *******************/\r\n#define  RCC_CSR_LSION                       0x00000001U\r\n#define  RCC_CSR_LSIRDY                      0x00000002U\r\n#define  RCC_CSR_RMVF                        0x01000000U\r\n#define  RCC_CSR_BORRSTF                     0x02000000U\r\n#define  RCC_CSR_PINRSTF                     0x04000000U\r\n#define  RCC_CSR_PORRSTF                     0x08000000U\r\n#define  RCC_CSR_SFTRSTF                     0x10000000U\r\n#define  RCC_CSR_IWDGRSTF                    0x20000000U\r\n#define  RCC_CSR_WWDGRSTF                    0x40000000U\r\n#define  RCC_CSR_LPWRRSTF                    0x80000000U\r\n\r\n/********************  Bit definition for RCC_SSCGR register  *****************/\r\n#define  RCC_SSCGR_MODPER                    0x00001FFFU\r\n#define  RCC_SSCGR_INCSTEP                   0x0FFFE000U\r\n#define  RCC_SSCGR_SPREADSEL                 0x40000000U\r\n#define  RCC_SSCGR_SSCGEN                    0x80000000U\r\n\r\n/********************  Bit definition for RCC_PLLI2SCFGR register  ************/\r\n#define  RCC_PLLI2SCFGR_PLLI2SN              0x00007FC0U\r\n#define  RCC_PLLI2SCFGR_PLLI2SN_0            0x00000040U\r\n#define  RCC_PLLI2SCFGR_PLLI2SN_1            0x00000080U\r\n#define  RCC_PLLI2SCFGR_PLLI2SN_2            0x00000100U\r\n#define  RCC_PLLI2SCFGR_PLLI2SN_3            0x00000200U\r\n#define  RCC_PLLI2SCFGR_PLLI2SN_4            0x00000400U\r\n#define  RCC_PLLI2SCFGR_PLLI2SN_5            0x00000800U\r\n#define  RCC_PLLI2SCFGR_PLLI2SN_6            0x00001000U\r\n#define  RCC_PLLI2SCFGR_PLLI2SN_7            0x00002000U\r\n#define  RCC_PLLI2SCFGR_PLLI2SN_8            0x00004000U\r\n#define  RCC_PLLI2SCFGR_PLLI2SP              0x00030000U\r\n#define  RCC_PLLI2SCFGR_PLLI2SP_0            0x00010000U\r\n#define  RCC_PLLI2SCFGR_PLLI2SP_1            0x00020000U\r\n#define  RCC_PLLI2SCFGR_PLLI2SQ              0x0F000000U\r\n#define  RCC_PLLI2SCFGR_PLLI2SQ_0            0x01000000U\r\n#define  RCC_PLLI2SCFGR_PLLI2SQ_1            0x02000000U\r\n#define  RCC_PLLI2SCFGR_PLLI2SQ_2            0x04000000U\r\n#define  RCC_PLLI2SCFGR_PLLI2SQ_3            0x08000000U\r\n#define  RCC_PLLI2SCFGR_PLLI2SR              0x70000000U\r\n#define  RCC_PLLI2SCFGR_PLLI2SR_0            0x10000000U\r\n#define  RCC_PLLI2SCFGR_PLLI2SR_1            0x20000000U\r\n#define  RCC_PLLI2SCFGR_PLLI2SR_2            0x40000000U\r\n\r\n/********************  Bit definition for RCC_PLLSAICFGR register  ************/\r\n#define  RCC_PLLSAICFGR_PLLSAIN              0x00007FC0U\r\n#define  RCC_PLLSAICFGR_PLLSAIN_0            0x00000040U\r\n#define  RCC_PLLSAICFGR_PLLSAIN_1            0x00000080U\r\n#define  RCC_PLLSAICFGR_PLLSAIN_2            0x00000100U\r\n#define  RCC_PLLSAICFGR_PLLSAIN_3            0x00000200U\r\n#define  RCC_PLLSAICFGR_PLLSAIN_4            0x00000400U\r\n#define  RCC_PLLSAICFGR_PLLSAIN_5            0x00000800U\r\n#define  RCC_PLLSAICFGR_PLLSAIN_6            0x00001000U\r\n#define  RCC_PLLSAICFGR_PLLSAIN_7            0x00002000U\r\n#define  RCC_PLLSAICFGR_PLLSAIN_8            0x00004000U\r\n#define  RCC_PLLSAICFGR_PLLSAIP              0x00030000U\r\n#define  RCC_PLLSAICFGR_PLLSAIP_0            0x00010000U\r\n#define  RCC_PLLSAICFGR_PLLSAIP_1            0x00020000U\r\n#define  RCC_PLLSAICFGR_PLLSAIQ              0x0F000000U\r\n#define  RCC_PLLSAICFGR_PLLSAIQ_0            0x01000000U\r\n#define  RCC_PLLSAICFGR_PLLSAIQ_1            0x02000000U\r\n#define  RCC_PLLSAICFGR_PLLSAIQ_2            0x04000000U\r\n#define  RCC_PLLSAICFGR_PLLSAIQ_3            0x08000000U\r\n#define  RCC_PLLSAICFGR_PLLSAIR              0x70000000U\r\n#define  RCC_PLLSAICFGR_PLLSAIR_0            0x10000000U\r\n#define  RCC_PLLSAICFGR_PLLSAIR_1            0x20000000U\r\n#define  RCC_PLLSAICFGR_PLLSAIR_2            0x40000000U\r\n\r\n/********************  Bit definition for RCC_DCKCFGR1 register  ***************/\r\n#define  RCC_DCKCFGR1_PLLI2SDIVQ             0x0000001FU\r\n#define  RCC_DCKCFGR1_PLLI2SDIVQ_0           0x00000001U\r\n#define  RCC_DCKCFGR1_PLLI2SDIVQ_1           0x00000002U\r\n#define  RCC_DCKCFGR1_PLLI2SDIVQ_2           0x00000004U\r\n#define  RCC_DCKCFGR1_PLLI2SDIVQ_3           0x00000008U\r\n#define  RCC_DCKCFGR1_PLLI2SDIVQ_4           0x00000010U\r\n\r\n#define  RCC_DCKCFGR1_PLLSAIDIVQ             0x00001F00U\r\n#define  RCC_DCKCFGR1_PLLSAIDIVQ_0           0x00000100U\r\n#define  RCC_DCKCFGR1_PLLSAIDIVQ_1           0x00000200U\r\n#define  RCC_DCKCFGR1_PLLSAIDIVQ_2           0x00000400U\r\n#define  RCC_DCKCFGR1_PLLSAIDIVQ_3           0x00000800U\r\n#define  RCC_DCKCFGR1_PLLSAIDIVQ_4           0x00001000U\r\n\r\n#define  RCC_DCKCFGR1_PLLSAIDIVR             0x00030000U\r\n#define  RCC_DCKCFGR1_PLLSAIDIVR_0           0x00010000U\r\n#define  RCC_DCKCFGR1_PLLSAIDIVR_1           0x00020000U\r\n\r\n#define  RCC_DCKCFGR1_SAI1SEL                0x00300000U\r\n#define  RCC_DCKCFGR1_SAI1SEL_0              0x00100000U\r\n#define  RCC_DCKCFGR1_SAI1SEL_1              0x00200000U\r\n\r\n#define  RCC_DCKCFGR1_SAI2SEL                0x00C00000U\r\n#define  RCC_DCKCFGR1_SAI2SEL_0              0x00400000U\r\n#define  RCC_DCKCFGR1_SAI2SEL_1              0x00800000U\r\n\r\n#define  RCC_DCKCFGR1_TIMPRE                 0x01000000U\r\n\r\n/********************  Bit definition for RCC_DCKCFGR2 register  ***************/\r\n#define  RCC_DCKCFGR2_USART1SEL              0x00000003U\r\n#define  RCC_DCKCFGR2_USART1SEL_0            0x00000001U\r\n#define  RCC_DCKCFGR2_USART1SEL_1            0x00000002U\r\n#define  RCC_DCKCFGR2_USART2SEL              0x0000000CU\r\n#define  RCC_DCKCFGR2_USART2SEL_0            0x00000004U\r\n#define  RCC_DCKCFGR2_USART2SEL_1            0x00000008U\r\n#define  RCC_DCKCFGR2_USART3SEL              0x00000030U\r\n#define  RCC_DCKCFGR2_USART3SEL_0            0x00000010U\r\n#define  RCC_DCKCFGR2_USART3SEL_1            0x00000020U\r\n#define  RCC_DCKCFGR2_UART4SEL               0x000000C0U\r\n#define  RCC_DCKCFGR2_UART4SEL_0             0x00000040U\r\n#define  RCC_DCKCFGR2_UART4SEL_1             0x00000080U\r\n#define  RCC_DCKCFGR2_UART5SEL               0x00000300U\r\n#define  RCC_DCKCFGR2_UART5SEL_0             0x00000100U\r\n#define  RCC_DCKCFGR2_UART5SEL_1             0x00000200U\r\n#define  RCC_DCKCFGR2_USART6SEL              0x00000C00U\r\n#define  RCC_DCKCFGR2_USART6SEL_0            0x00000400U\r\n#define  RCC_DCKCFGR2_USART6SEL_1            0x00000800U\r\n#define  RCC_DCKCFGR2_UART7SEL               0x00003000U\r\n#define  RCC_DCKCFGR2_UART7SEL_0             0x00001000U\r\n#define  RCC_DCKCFGR2_UART7SEL_1             0x00002000U\r\n#define  RCC_DCKCFGR2_UART8SEL               0x0000C000U\r\n#define  RCC_DCKCFGR2_UART8SEL_0             0x00004000U\r\n#define  RCC_DCKCFGR2_UART8SEL_1             0x00008000U\r\n#define  RCC_DCKCFGR2_I2C1SEL                0x00030000U\r\n#define  RCC_DCKCFGR2_I2C1SEL_0              0x00010000U\r\n#define  RCC_DCKCFGR2_I2C1SEL_1              0x00020000U\r\n#define  RCC_DCKCFGR2_I2C2SEL                0x000C0000U\r\n#define  RCC_DCKCFGR2_I2C2SEL_0              0x00040000U\r\n#define  RCC_DCKCFGR2_I2C2SEL_1              0x00080000U\r\n#define  RCC_DCKCFGR2_I2C3SEL                0x00300000U\r\n#define  RCC_DCKCFGR2_I2C3SEL_0              0x00100000U\r\n#define  RCC_DCKCFGR2_I2C3SEL_1              0x00200000U\r\n#define  RCC_DCKCFGR2_I2C4SEL                0x00C00000U\r\n#define  RCC_DCKCFGR2_I2C4SEL_0              0x00400000U\r\n#define  RCC_DCKCFGR2_I2C4SEL_1              0x00800000U\r\n#define  RCC_DCKCFGR2_LPTIM1SEL              0x03000000U\r\n#define  RCC_DCKCFGR2_LPTIM1SEL_0            0x01000000U\r\n#define  RCC_DCKCFGR2_LPTIM1SEL_1            0x02000000U\r\n#define  RCC_DCKCFGR2_CECSEL                 0x04000000U\r\n#define  RCC_DCKCFGR2_CK48MSEL               0x08000000U\r\n#define  RCC_DCKCFGR2_SDMMC1SEL              0x10000000U\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                    RNG                                     */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bits definition for RNG_CR register  *******************/\r\n#define RNG_CR_RNGEN                         0x00000004U\r\n#define RNG_CR_IE                            0x00000008U\r\n\r\n/********************  Bits definition for RNG_SR register  *******************/\r\n#define RNG_SR_DRDY                          0x00000001U\r\n#define RNG_SR_CECS                          0x00000002U\r\n#define RNG_SR_SECS                          0x00000004U\r\n#define RNG_SR_CEIS                          0x00000020U\r\n#define RNG_SR_SEIS                          0x00000040U\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                           Real-Time Clock (RTC)                            */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bits definition for RTC_TR register  *******************/\r\n#define RTC_TR_PM                            0x00400000U\r\n#define RTC_TR_HT                            0x00300000U\r\n#define RTC_TR_HT_0                          0x00100000U\r\n#define RTC_TR_HT_1                          0x00200000U\r\n#define RTC_TR_HU                            0x000F0000U\r\n#define RTC_TR_HU_0                          0x00010000U\r\n#define RTC_TR_HU_1                          0x00020000U\r\n#define RTC_TR_HU_2                          0x00040000U\r\n#define RTC_TR_HU_3                          0x00080000U\r\n#define RTC_TR_MNT                           0x00007000U\r\n#define RTC_TR_MNT_0                         0x00001000U\r\n#define RTC_TR_MNT_1                         0x00002000U\r\n#define RTC_TR_MNT_2                         0x00004000U\r\n#define RTC_TR_MNU                           0x00000F00U\r\n#define RTC_TR_MNU_0                         0x00000100U\r\n#define RTC_TR_MNU_1                         0x00000200U\r\n#define RTC_TR_MNU_2                         0x00000400U\r\n#define RTC_TR_MNU_3                         0x00000800U\r\n#define RTC_TR_ST                            0x00000070U\r\n#define RTC_TR_ST_0                          0x00000010U\r\n#define RTC_TR_ST_1                          0x00000020U\r\n#define RTC_TR_ST_2                          0x00000040U\r\n#define RTC_TR_SU                            0x0000000FU\r\n#define RTC_TR_SU_0                          0x00000001U\r\n#define RTC_TR_SU_1                          0x00000002U\r\n#define RTC_TR_SU_2                          0x00000004U\r\n#define RTC_TR_SU_3                          0x00000008U\r\n\r\n/********************  Bits definition for RTC_DR register  *******************/\r\n#define RTC_DR_YT                            0x00F00000U\r\n#define RTC_DR_YT_0                          0x00100000U\r\n#define RTC_DR_YT_1                          0x00200000U\r\n#define RTC_DR_YT_2                          0x00400000U\r\n#define RTC_DR_YT_3                          0x00800000U\r\n#define RTC_DR_YU                            0x000F0000U\r\n#define RTC_DR_YU_0                          0x00010000U\r\n#define RTC_DR_YU_1                          0x00020000U\r\n#define RTC_DR_YU_2                          0x00040000U\r\n#define RTC_DR_YU_3                          0x00080000U\r\n#define RTC_DR_WDU                           0x0000E000U\r\n#define RTC_DR_WDU_0                         0x00002000U\r\n#define RTC_DR_WDU_1                         0x00004000U\r\n#define RTC_DR_WDU_2                         0x00008000U\r\n#define RTC_DR_MT                            0x00001000U\r\n#define RTC_DR_MU                            0x00000F00U\r\n#define RTC_DR_MU_0                          0x00000100U\r\n#define RTC_DR_MU_1                          0x00000200U\r\n#define RTC_DR_MU_2                          0x00000400U\r\n#define RTC_DR_MU_3                          0x00000800U\r\n#define RTC_DR_DT                            0x00000030U\r\n#define RTC_DR_DT_0                          0x00000010U\r\n#define RTC_DR_DT_1                          0x00000020U\r\n#define RTC_DR_DU                            0x0000000FU\r\n#define RTC_DR_DU_0                          0x00000001U\r\n#define RTC_DR_DU_1                          0x00000002U\r\n#define RTC_DR_DU_2                          0x00000004U\r\n#define RTC_DR_DU_3                          0x00000008U\r\n\r\n/********************  Bits definition for RTC_CR register  *******************/\r\n#define RTC_CR_ITSE                          0x01000000U \r\n#define RTC_CR_COE                           0x00800000U\r\n#define RTC_CR_OSEL                          0x00600000U\r\n#define RTC_CR_OSEL_0                        0x00200000U\r\n#define RTC_CR_OSEL_1                        0x00400000U\r\n#define RTC_CR_POL                           0x00100000U\r\n#define RTC_CR_COSEL                         0x00080000U\r\n#define RTC_CR_BCK                           0x00040000U\r\n#define RTC_CR_SUB1H                         0x00020000U\r\n#define RTC_CR_ADD1H                         0x00010000U\r\n#define RTC_CR_TSIE                          0x00008000U\r\n#define RTC_CR_WUTIE                         0x00004000U\r\n#define RTC_CR_ALRBIE                        0x00002000U\r\n#define RTC_CR_ALRAIE                        0x00001000U\r\n#define RTC_CR_TSE                           0x00000800U\r\n#define RTC_CR_WUTE                          0x00000400U\r\n#define RTC_CR_ALRBE                         0x00000200U\r\n#define RTC_CR_ALRAE                         0x00000100U\r\n#define RTC_CR_FMT                           0x00000040U\r\n#define RTC_CR_BYPSHAD                       0x00000020U\r\n#define RTC_CR_REFCKON                       0x00000010U\r\n#define RTC_CR_TSEDGE                        0x00000008U\r\n#define RTC_CR_WUCKSEL                       0x00000007U\r\n#define RTC_CR_WUCKSEL_0                     0x00000001U\r\n#define RTC_CR_WUCKSEL_1                     0x00000002U\r\n#define RTC_CR_WUCKSEL_2                     0x00000004U\r\n\r\n/********************  Bits definition for RTC_ISR register  ******************/\r\n#define RTC_ISR_ITSF                         0x00020000U\r\n#define RTC_ISR_RECALPF                      0x00010000U\r\n#define RTC_ISR_TAMP3F                       0x00008000U\r\n#define RTC_ISR_TAMP2F                       0x00004000U\r\n#define RTC_ISR_TAMP1F                       0x00002000U\r\n#define RTC_ISR_TSOVF                        0x00001000U\r\n#define RTC_ISR_TSF                          0x00000800U\r\n#define RTC_ISR_WUTF                         0x00000400U\r\n#define RTC_ISR_ALRBF                        0x00000200U\r\n#define RTC_ISR_ALRAF                        0x00000100U\r\n#define RTC_ISR_INIT                         0x00000080U\r\n#define RTC_ISR_INITF                        0x00000040U\r\n#define RTC_ISR_RSF                          0x00000020U\r\n#define RTC_ISR_INITS                        0x00000010U\r\n#define RTC_ISR_SHPF                         0x00000008U\r\n#define RTC_ISR_WUTWF                        0x00000004U\r\n#define RTC_ISR_ALRBWF                       0x00000002U\r\n#define RTC_ISR_ALRAWF                       0x00000001U\r\n\r\n/********************  Bits definition for RTC_PRER register  *****************/\r\n#define RTC_PRER_PREDIV_A                    0x007F0000U\r\n#define RTC_PRER_PREDIV_S                    0x00007FFFU\r\n\r\n/********************  Bits definition for RTC_WUTR register  *****************/\r\n#define RTC_WUTR_WUT                         0x0000FFFFU\r\n\r\n/********************  Bits definition for RTC_ALRMAR register  ***************/\r\n#define RTC_ALRMAR_MSK4                      0x80000000U\r\n#define RTC_ALRMAR_WDSEL                     0x40000000U\r\n#define RTC_ALRMAR_DT                        0x30000000U\r\n#define RTC_ALRMAR_DT_0                      0x10000000U\r\n#define RTC_ALRMAR_DT_1                      0x20000000U\r\n#define RTC_ALRMAR_DU                        0x0F000000U\r\n#define RTC_ALRMAR_DU_0                      0x01000000U\r\n#define RTC_ALRMAR_DU_1                      0x02000000U\r\n#define RTC_ALRMAR_DU_2                      0x04000000U\r\n#define RTC_ALRMAR_DU_3                      0x08000000U\r\n#define RTC_ALRMAR_MSK3                      0x00800000U\r\n#define RTC_ALRMAR_PM                        0x00400000U\r\n#define RTC_ALRMAR_HT                        0x00300000U\r\n#define RTC_ALRMAR_HT_0                      0x00100000U\r\n#define RTC_ALRMAR_HT_1                      0x00200000U\r\n#define RTC_ALRMAR_HU                        0x000F0000U\r\n#define RTC_ALRMAR_HU_0                      0x00010000U\r\n#define RTC_ALRMAR_HU_1                      0x00020000U\r\n#define RTC_ALRMAR_HU_2                      0x00040000U\r\n#define RTC_ALRMAR_HU_3                      0x00080000U\r\n#define RTC_ALRMAR_MSK2                      0x00008000U\r\n#define RTC_ALRMAR_MNT                       0x00007000U\r\n#define RTC_ALRMAR_MNT_0                     0x00001000U\r\n#define RTC_ALRMAR_MNT_1                     0x00002000U\r\n#define RTC_ALRMAR_MNT_2                     0x00004000U\r\n#define RTC_ALRMAR_MNU                       0x00000F00U\r\n#define RTC_ALRMAR_MNU_0                     0x00000100U\r\n#define RTC_ALRMAR_MNU_1                     0x00000200U\r\n#define RTC_ALRMAR_MNU_2                     0x00000400U\r\n#define RTC_ALRMAR_MNU_3                     0x00000800U\r\n#define RTC_ALRMAR_MSK1                      0x00000080U\r\n#define RTC_ALRMAR_ST                        0x00000070U\r\n#define RTC_ALRMAR_ST_0                      0x00000010U\r\n#define RTC_ALRMAR_ST_1                      0x00000020U\r\n#define RTC_ALRMAR_ST_2                      0x00000040U\r\n#define RTC_ALRMAR_SU                        0x0000000FU\r\n#define RTC_ALRMAR_SU_0                      0x00000001U\r\n#define RTC_ALRMAR_SU_1                      0x00000002U\r\n#define RTC_ALRMAR_SU_2                      0x00000004U\r\n#define RTC_ALRMAR_SU_3                      0x00000008U\r\n\r\n/********************  Bits definition for RTC_ALRMBR register  ***************/\r\n#define RTC_ALRMBR_MSK4                      0x80000000U\r\n#define RTC_ALRMBR_WDSEL                     0x40000000U\r\n#define RTC_ALRMBR_DT                        0x30000000U\r\n#define RTC_ALRMBR_DT_0                      0x10000000U\r\n#define RTC_ALRMBR_DT_1                      0x20000000U\r\n#define RTC_ALRMBR_DU                        0x0F000000U\r\n#define RTC_ALRMBR_DU_0                      0x01000000U\r\n#define RTC_ALRMBR_DU_1                      0x02000000U\r\n#define RTC_ALRMBR_DU_2                      0x04000000U\r\n#define RTC_ALRMBR_DU_3                      0x08000000U\r\n#define RTC_ALRMBR_MSK3                      0x00800000U\r\n#define RTC_ALRMBR_PM                        0x00400000U\r\n#define RTC_ALRMBR_HT                        0x00300000U\r\n#define RTC_ALRMBR_HT_0                      0x00100000U\r\n#define RTC_ALRMBR_HT_1                      0x00200000U\r\n#define RTC_ALRMBR_HU                        0x000F0000U\r\n#define RTC_ALRMBR_HU_0                      0x00010000U\r\n#define RTC_ALRMBR_HU_1                      0x00020000U\r\n#define RTC_ALRMBR_HU_2                      0x00040000U\r\n#define RTC_ALRMBR_HU_3                      0x00080000U\r\n#define RTC_ALRMBR_MSK2                      0x00008000U\r\n#define RTC_ALRMBR_MNT                       0x00007000U\r\n#define RTC_ALRMBR_MNT_0                     0x00001000U\r\n#define RTC_ALRMBR_MNT_1                     0x00002000U\r\n#define RTC_ALRMBR_MNT_2                     0x00004000U\r\n#define RTC_ALRMBR_MNU                       0x00000F00U\r\n#define RTC_ALRMBR_MNU_0                     0x00000100U\r\n#define RTC_ALRMBR_MNU_1                     0x00000200U\r\n#define RTC_ALRMBR_MNU_2                     0x00000400U\r\n#define RTC_ALRMBR_MNU_3                     0x00000800U\r\n#define RTC_ALRMBR_MSK1                      0x00000080U\r\n#define RTC_ALRMBR_ST                        0x00000070U\r\n#define RTC_ALRMBR_ST_0                      0x00000010U\r\n#define RTC_ALRMBR_ST_1                      0x00000020U\r\n#define RTC_ALRMBR_ST_2                      0x00000040U\r\n#define RTC_ALRMBR_SU                        0x0000000FU\r\n#define RTC_ALRMBR_SU_0                      0x00000001U\r\n#define RTC_ALRMBR_SU_1                      0x00000002U\r\n#define RTC_ALRMBR_SU_2                      0x00000004U\r\n#define RTC_ALRMBR_SU_3                      0x00000008U\r\n\r\n/********************  Bits definition for RTC_WPR register  ******************/\r\n#define RTC_WPR_KEY                          0x000000FFU\r\n\r\n/********************  Bits definition for RTC_SSR register  ******************/\r\n#define RTC_SSR_SS                           0x0000FFFFU\r\n\r\n/********************  Bits definition for RTC_SHIFTR register  ***************/\r\n#define RTC_SHIFTR_SUBFS                     0x00007FFFU\r\n#define RTC_SHIFTR_ADD1S                     0x80000000U\r\n\r\n/********************  Bits definition for RTC_TSTR register  *****************/\r\n#define RTC_TSTR_PM                          0x00400000U\r\n#define RTC_TSTR_HT                          0x00300000U\r\n#define RTC_TSTR_HT_0                        0x00100000U\r\n#define RTC_TSTR_HT_1                        0x00200000U\r\n#define RTC_TSTR_HU                          0x000F0000U\r\n#define RTC_TSTR_HU_0                        0x00010000U\r\n#define RTC_TSTR_HU_1                        0x00020000U\r\n#define RTC_TSTR_HU_2                        0x00040000U\r\n#define RTC_TSTR_HU_3                        0x00080000U\r\n#define RTC_TSTR_MNT                         0x00007000U\r\n#define RTC_TSTR_MNT_0                       0x00001000U\r\n#define RTC_TSTR_MNT_1                       0x00002000U\r\n#define RTC_TSTR_MNT_2                       0x00004000U\r\n#define RTC_TSTR_MNU                         0x00000F00U\r\n#define RTC_TSTR_MNU_0                       0x00000100U\r\n#define RTC_TSTR_MNU_1                       0x00000200U\r\n#define RTC_TSTR_MNU_2                       0x00000400U\r\n#define RTC_TSTR_MNU_3                       0x00000800U\r\n#define RTC_TSTR_ST                          0x00000070U\r\n#define RTC_TSTR_ST_0                        0x00000010U\r\n#define RTC_TSTR_ST_1                        0x00000020U\r\n#define RTC_TSTR_ST_2                        0x00000040U\r\n#define RTC_TSTR_SU                          0x0000000FU\r\n#define RTC_TSTR_SU_0                        0x00000001U\r\n#define RTC_TSTR_SU_1                        0x00000002U\r\n#define RTC_TSTR_SU_2                        0x00000004U\r\n#define RTC_TSTR_SU_3                        0x00000008U\r\n\r\n/********************  Bits definition for RTC_TSDR register  *****************/\r\n#define RTC_TSDR_WDU                         0x0000E000U\r\n#define RTC_TSDR_WDU_0                       0x00002000U\r\n#define RTC_TSDR_WDU_1                       0x00004000U\r\n#define RTC_TSDR_WDU_2                       0x00008000U\r\n#define RTC_TSDR_MT                          0x00001000U\r\n#define RTC_TSDR_MU                          0x00000F00U\r\n#define RTC_TSDR_MU_0                        0x00000100U\r\n#define RTC_TSDR_MU_1                        0x00000200U\r\n#define RTC_TSDR_MU_2                        0x00000400U\r\n#define RTC_TSDR_MU_3                        0x00000800U\r\n#define RTC_TSDR_DT                          0x00000030U\r\n#define RTC_TSDR_DT_0                        0x00000010U\r\n#define RTC_TSDR_DT_1                        0x00000020U\r\n#define RTC_TSDR_DU                          0x0000000FU\r\n#define RTC_TSDR_DU_0                        0x00000001U\r\n#define RTC_TSDR_DU_1                        0x00000002U\r\n#define RTC_TSDR_DU_2                        0x00000004U\r\n#define RTC_TSDR_DU_3                        0x00000008U\r\n\r\n/********************  Bits definition for RTC_TSSSR register  ****************/\r\n#define RTC_TSSSR_SS                         0x0000FFFFU\r\n\r\n/********************  Bits definition for RTC_CAL register  *****************/\r\n#define RTC_CALR_CALP                        0x00008000U\r\n#define RTC_CALR_CALW8                       0x00004000U\r\n#define RTC_CALR_CALW16                      0x00002000U\r\n#define RTC_CALR_CALM                        0x000001FFU\r\n#define RTC_CALR_CALM_0                      0x00000001U\r\n#define RTC_CALR_CALM_1                      0x00000002U\r\n#define RTC_CALR_CALM_2                      0x00000004U\r\n#define RTC_CALR_CALM_3                      0x00000008U\r\n#define RTC_CALR_CALM_4                      0x00000010U\r\n#define RTC_CALR_CALM_5                      0x00000020U\r\n#define RTC_CALR_CALM_6                      0x00000040U\r\n#define RTC_CALR_CALM_7                      0x00000080U\r\n#define RTC_CALR_CALM_8                      0x00000100U\r\n\r\n/********************  Bits definition for RTC_TAMPCR register  ****************/\r\n#define RTC_TAMPCR_TAMP3MF                   0x01000000U\r\n#define RTC_TAMPCR_TAMP3NOERASE              0x00800000U\r\n#define RTC_TAMPCR_TAMP3IE                   0x00400000U\r\n#define RTC_TAMPCR_TAMP2MF                   0x00200000U\r\n#define RTC_TAMPCR_TAMP2NOERASE              0x00100000U\r\n#define RTC_TAMPCR_TAMP2IE                   0x00080000U\r\n#define RTC_TAMPCR_TAMP1MF                   0x00040000U\r\n#define RTC_TAMPCR_TAMP1NOERASE              0x00020000U\r\n#define RTC_TAMPCR_TAMP1IE                   0x00010000U\r\n#define RTC_TAMPCR_TAMPPUDIS                 0x00008000U\r\n#define RTC_TAMPCR_TAMPPRCH                  0x00006000U\r\n#define RTC_TAMPCR_TAMPPRCH_0                0x00002000U\r\n#define RTC_TAMPCR_TAMPPRCH_1                0x00004000U\r\n#define RTC_TAMPCR_TAMPFLT                   0x00001800U\r\n#define RTC_TAMPCR_TAMPFLT_0                 0x00000800U\r\n#define RTC_TAMPCR_TAMPFLT_1                 0x00001000U\r\n#define RTC_TAMPCR_TAMPFREQ                  0x00000700U\r\n#define RTC_TAMPCR_TAMPFREQ_0                0x00000100U\r\n#define RTC_TAMPCR_TAMPFREQ_1                0x00000200U\r\n#define RTC_TAMPCR_TAMPFREQ_2                0x00000400U\r\n#define RTC_TAMPCR_TAMPTS                    0x00000080U\r\n#define RTC_TAMPCR_TAMP3TRG                  0x00000040U\r\n#define RTC_TAMPCR_TAMP3E                    0x00000020U\r\n#define RTC_TAMPCR_TAMP2TRG                  0x00000010U\r\n#define RTC_TAMPCR_TAMP2E                    0x00000008U\r\n#define RTC_TAMPCR_TAMPIE                    0x00000004U\r\n#define RTC_TAMPCR_TAMP1TRG                  0x00000002U\r\n#define RTC_TAMPCR_TAMP1E                    0x00000001U\r\n\r\n/* Legacy defines */\r\n#define RTC_TAMPCR_TAMP3_TRG                  RTC_TAMPCR_TAMP3TRG\r\n#define RTC_TAMPCR_TAMP2_TRG                  RTC_TAMPCR_TAMP2TRG\r\n#define RTC_TAMPCR_TAMP1_TRG                  RTC_TAMPCR_TAMP1TRG\r\n\r\n/********************  Bits definition for RTC_ALRMASSR register  *************/\r\n#define RTC_ALRMASSR_MASKSS                  0x0F000000U\r\n#define RTC_ALRMASSR_MASKSS_0                0x01000000U\r\n#define RTC_ALRMASSR_MASKSS_1                0x02000000U\r\n#define RTC_ALRMASSR_MASKSS_2                0x04000000U\r\n#define RTC_ALRMASSR_MASKSS_3                0x08000000U\r\n#define RTC_ALRMASSR_SS                      0x00007FFFU\r\n\r\n/********************  Bits definition for RTC_ALRMBSSR register  *************/\r\n#define RTC_ALRMBSSR_MASKSS                  0x0F000000U\r\n#define RTC_ALRMBSSR_MASKSS_0                0x01000000U\r\n#define RTC_ALRMBSSR_MASKSS_1                0x02000000U\r\n#define RTC_ALRMBSSR_MASKSS_2                0x04000000U\r\n#define RTC_ALRMBSSR_MASKSS_3                0x08000000U\r\n#define RTC_ALRMBSSR_SS                      0x00007FFFU\r\n\r\n/********************  Bits definition for RTC_OR register  ****************/\r\n#define RTC_OR_TSINSEL                       0x00000006U\r\n#define RTC_OR_TSINSEL_0                     0x00000002U\r\n#define RTC_OR_TSINSEL_1                     0x00000004U\r\n#define RTC_OR_ALARMTYPE                     0x00000008U\r\n\r\n/********************  Bits definition for RTC_BKP0R register  ****************/\r\n#define RTC_BKP0R                            0xFFFFFFFFU\r\n\r\n/********************  Bits definition for RTC_BKP1R register  ****************/\r\n#define RTC_BKP1R                            0xFFFFFFFFU\r\n\r\n/********************  Bits definition for RTC_BKP2R register  ****************/\r\n#define RTC_BKP2R                            0xFFFFFFFFU\r\n\r\n/********************  Bits definition for RTC_BKP3R register  ****************/\r\n#define RTC_BKP3R                            0xFFFFFFFFU\r\n\r\n/********************  Bits definition for RTC_BKP4R register  ****************/\r\n#define RTC_BKP4R                            0xFFFFFFFFU\r\n\r\n/********************  Bits definition for RTC_BKP5R register  ****************/\r\n#define RTC_BKP5R                            0xFFFFFFFFU\r\n\r\n/********************  Bits definition for RTC_BKP6R register  ****************/\r\n#define RTC_BKP6R                            0xFFFFFFFFU\r\n\r\n/********************  Bits definition for RTC_BKP7R register  ****************/\r\n#define RTC_BKP7R                            0xFFFFFFFFU\r\n\r\n/********************  Bits definition for RTC_BKP8R register  ****************/\r\n#define RTC_BKP8R                            0xFFFFFFFFU\r\n\r\n/********************  Bits definition for RTC_BKP9R register  ****************/\r\n#define RTC_BKP9R                            0xFFFFFFFFU\r\n\r\n/********************  Bits definition for RTC_BKP10R register  ***************/\r\n#define RTC_BKP10R                           0xFFFFFFFFU\r\n\r\n/********************  Bits definition for RTC_BKP11R register  ***************/\r\n#define RTC_BKP11R                           0xFFFFFFFFU\r\n\r\n/********************  Bits definition for RTC_BKP12R register  ***************/\r\n#define RTC_BKP12R                           0xFFFFFFFFU\r\n\r\n/********************  Bits definition for RTC_BKP13R register  ***************/\r\n#define RTC_BKP13R                           0xFFFFFFFFU\r\n\r\n/********************  Bits definition for RTC_BKP14R register  ***************/\r\n#define RTC_BKP14R                           0xFFFFFFFFU\r\n\r\n/********************  Bits definition for RTC_BKP15R register  ***************/\r\n#define RTC_BKP15R                           0xFFFFFFFFU\r\n\r\n/********************  Bits definition for RTC_BKP16R register  ***************/\r\n#define RTC_BKP16R                           0xFFFFFFFFU\r\n\r\n/********************  Bits definition for RTC_BKP17R register  ***************/\r\n#define RTC_BKP17R                           0xFFFFFFFFU\r\n\r\n/********************  Bits definition for RTC_BKP18R register  ***************/\r\n#define RTC_BKP18R                           0xFFFFFFFFU\r\n\r\n/********************  Bits definition for RTC_BKP19R register  ***************/\r\n#define RTC_BKP19R                           0xFFFFFFFFU\r\n\r\n/********************  Bits definition for RTC_BKP20R register  ***************/\r\n#define RTC_BKP20R                           0xFFFFFFFFU\r\n\r\n/********************  Bits definition for RTC_BKP21R register  ***************/\r\n#define RTC_BKP21R                           0xFFFFFFFFU\r\n\r\n/********************  Bits definition for RTC_BKP22R register  ***************/\r\n#define RTC_BKP22R                           0xFFFFFFFFU\r\n\r\n/********************  Bits definition for RTC_BKP23R register  ***************/\r\n#define RTC_BKP23R                           0xFFFFFFFFU\r\n\r\n/********************  Bits definition for RTC_BKP24R register  ***************/\r\n#define RTC_BKP24R                           0xFFFFFFFFU\r\n\r\n/********************  Bits definition for RTC_BKP25R register  ***************/\r\n#define RTC_BKP25R                           0xFFFFFFFFU\r\n\r\n/********************  Bits definition for RTC_BKP26R register  ***************/\r\n#define RTC_BKP26R                           0xFFFFFFFFU\r\n\r\n/********************  Bits definition for RTC_BKP27R register  ***************/\r\n#define RTC_BKP27R                           0xFFFFFFFFU\r\n\r\n/********************  Bits definition for RTC_BKP28R register  ***************/\r\n#define RTC_BKP28R                           0xFFFFFFFFU\r\n\r\n/********************  Bits definition for RTC_BKP29R register  ***************/\r\n#define RTC_BKP29R                           0xFFFFFFFFU\r\n\r\n/********************  Bits definition for RTC_BKP30R register  ***************/\r\n#define RTC_BKP30R                           0xFFFFFFFFU\r\n\r\n/********************  Bits definition for RTC_BKP31R register  ***************/\r\n#define RTC_BKP31R                           0xFFFFFFFFU\r\n\r\n/******************** Number of backup registers ******************************/\r\n#define RTC_BKP_NUMBER                       0x00000020U\r\n\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                          Serial Audio Interface                            */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bit definition for SAI_GCR register  *******************/\r\n#define  SAI_GCR_SYNCIN                      0x00000003U        /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */\r\n#define  SAI_GCR_SYNCIN_0                    0x00000001U        /*!<Bit 0 */\r\n#define  SAI_GCR_SYNCIN_1                    0x00000002U        /*!<Bit 1 */\r\n                                             \r\n#define  SAI_GCR_SYNCOUT                     0x00000030U        /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */\r\n#define  SAI_GCR_SYNCOUT_0                   0x00000010U        /*!<Bit 0 */\r\n#define  SAI_GCR_SYNCOUT_1                   0x00000020U        /*!<Bit 1 */\r\n\r\n/*******************  Bit definition for SAI_xCR1 register  *******************/\r\n#define  SAI_xCR1_MODE                       0x00000003U        /*!<MODE[1:0] bits (Audio Block Mode)           */\r\n#define  SAI_xCR1_MODE_0                     0x00000001U        /*!<Bit 0 */\r\n#define  SAI_xCR1_MODE_1                     0x00000002U        /*!<Bit 1 */\r\n                                             \r\n#define  SAI_xCR1_PRTCFG                     0x0000000CU        /*!<PRTCFG[1:0] bits (Protocol Configuration)   */\r\n#define  SAI_xCR1_PRTCFG_0                   0x00000004U        /*!<Bit 0 */\r\n#define  SAI_xCR1_PRTCFG_1                   0x00000008U        /*!<Bit 1 */\r\n                                             \r\n#define  SAI_xCR1_DS                         0x000000E0U        /*!<DS[1:0] bits (Data Size) */\r\n#define  SAI_xCR1_DS_0                       0x00000020U        /*!<Bit 0 */\r\n#define  SAI_xCR1_DS_1                       0x00000040U        /*!<Bit 1 */\r\n#define  SAI_xCR1_DS_2                       0x00000080U        /*!<Bit 2 */\r\n                                             \r\n#define  SAI_xCR1_LSBFIRST                   0x00000100U        /*!<LSB First Configuration  */\r\n#define  SAI_xCR1_CKSTR                      0x00000200U        /*!<ClocK STRobing edge      */\r\n                                             \r\n#define  SAI_xCR1_SYNCEN                     0x00000C00U        /*!<SYNCEN[1:0](SYNChronization ENable) */\r\n#define  SAI_xCR1_SYNCEN_0                   0x00000400U        /*!<Bit 0 */\r\n#define  SAI_xCR1_SYNCEN_1                   0x00000800U        /*!<Bit 1 */\r\n                                             \r\n#define  SAI_xCR1_MONO                       0x00001000U        /*!<Mono mode                  */\r\n#define  SAI_xCR1_OUTDRIV                    0x00002000U        /*!<Output Drive               */\r\n#define  SAI_xCR1_SAIEN                      0x00010000U        /*!<Audio Block enable         */\r\n#define  SAI_xCR1_DMAEN                      0x00020000U        /*!<DMA enable                 */\r\n#define  SAI_xCR1_NODIV                      0x00080000U        /*!<No Divider Configuration   */\r\n                                             \r\n#define  SAI_xCR1_MCKDIV                     0x00F00000U        /*!<MCKDIV[3:0] (Master ClocK Divider)  */\r\n#define  SAI_xCR1_MCKDIV_0                   0x00100000U        /*!<Bit 0  */\r\n#define  SAI_xCR1_MCKDIV_1                   0x00200000U        /*!<Bit 1  */\r\n#define  SAI_xCR1_MCKDIV_2                   0x00400000U        /*!<Bit 2  */\r\n#define  SAI_xCR1_MCKDIV_3                   0x00800000U        /*!<Bit 3  */\r\n\r\n/*******************  Bit definition for SAI_xCR2 register  *******************/\r\n#define  SAI_xCR2_FTH                        0x00000007U        /*!<FTH[2:0](Fifo THreshold)  */\r\n#define  SAI_xCR2_FTH_0                      0x00000001U        /*!<Bit 0 */\r\n#define  SAI_xCR2_FTH_1                      0x00000002U        /*!<Bit 1 */\r\n#define  SAI_xCR2_FTH_2                      0x00000004U        /*!<Bit 2 */\r\n                                             \r\n#define  SAI_xCR2_FFLUSH                     0x00000008U        /*!<Fifo FLUSH                       */\r\n#define  SAI_xCR2_TRIS                       0x00000010U        /*!<TRIState Management on data line */\r\n#define  SAI_xCR2_MUTE                       0x00000020U        /*!<Mute mode                        */\r\n#define  SAI_xCR2_MUTEVAL                    0x00000040U        /*!<Muate value                      */\r\n                                             \r\n#define  SAI_xCR2_MUTECNT                    0x00001F80U       /*!<MUTECNT[5:0] (MUTE counter) */\r\n#define  SAI_xCR2_MUTECNT_0                  0x00000080U        /*!<Bit 0 */\r\n#define  SAI_xCR2_MUTECNT_1                  0x00000100U        /*!<Bit 1 */\r\n#define  SAI_xCR2_MUTECNT_2                  0x00000200U        /*!<Bit 2 */\r\n#define  SAI_xCR2_MUTECNT_3                  0x00000400U        /*!<Bit 3 */\r\n#define  SAI_xCR2_MUTECNT_4                  0x00000800U        /*!<Bit 4 */\r\n#define  SAI_xCR2_MUTECNT_5                  0x00001000U        /*!<Bit 5 */\r\n                                             \r\n#define  SAI_xCR2_CPL                        0x00002000U        /*!< Complement Bit             */\r\n                                             \r\n#define  SAI_xCR2_COMP                       0x0000C000U        /*!<COMP[1:0] (Companding mode) */\r\n#define  SAI_xCR2_COMP_0                     0x00004000U        /*!<Bit 0 */\r\n#define  SAI_xCR2_COMP_1                     0x00008000U        /*!<Bit 1 */\r\n\r\n/******************  Bit definition for SAI_xFRCR register  *******************/\r\n#define  SAI_xFRCR_FRL                       0x000000FFU        /*!<FRL[1:0](Frame length)  */\r\n#define  SAI_xFRCR_FRL_0                     0x00000001U        /*!<Bit 0 */\r\n#define  SAI_xFRCR_FRL_1                     0x00000002U        /*!<Bit 1 */\r\n#define  SAI_xFRCR_FRL_2                     0x00000004U        /*!<Bit 2 */\r\n#define  SAI_xFRCR_FRL_3                     0x00000008U        /*!<Bit 3 */\r\n#define  SAI_xFRCR_FRL_4                     0x00000010U        /*!<Bit 4 */\r\n#define  SAI_xFRCR_FRL_5                     0x00000020U        /*!<Bit 5 */\r\n#define  SAI_xFRCR_FRL_6                     0x00000040U        /*!<Bit 6 */\r\n#define  SAI_xFRCR_FRL_7                     0x00000080U        /*!<Bit 7 */\r\n                                                        \r\n#define  SAI_xFRCR_FSALL                     0x00007F00U        /*!<FRL[1:0] (Frame synchronization active level length)  */\r\n#define  SAI_xFRCR_FSALL_0                   0x00000100U        /*!<Bit 0 */\r\n#define  SAI_xFRCR_FSALL_1                   0x00000200U        /*!<Bit 1 */\r\n#define  SAI_xFRCR_FSALL_2                   0x00000400U        /*!<Bit 2 */\r\n#define  SAI_xFRCR_FSALL_3                   0x00000800U        /*!<Bit 3 */\r\n#define  SAI_xFRCR_FSALL_4                   0x00001000U        /*!<Bit 4 */\r\n#define  SAI_xFRCR_FSALL_5                   0x00002000U        /*!<Bit 5 */\r\n#define  SAI_xFRCR_FSALL_6                   0x00004000U        /*!<Bit 6 */\r\n                                                        \r\n#define  SAI_xFRCR_FSDEF                     0x00010000U        /*!<Frame Synchronization Definition  */\r\n#define  SAI_xFRCR_FSPOL                     0x00020000U        /*!<Frame Synchronization POLarity    */\r\n#define  SAI_xFRCR_FSOFF                     0x00040000U        /*!<Frame Synchronization OFFset      */\r\n                                             \r\n/* Legacy define */                          \r\n#define  SAI_xFRCR_FSPO                      SAI_xFRCR_FSPOL\r\n\r\n/******************  Bit definition for SAI_xSLOTR register  *******************/\r\n#define  SAI_xSLOTR_FBOFF                    0x0000001FU        /*!<FRL[4:0](First Bit Offset)  */\r\n#define  SAI_xSLOTR_FBOFF_0                  0x00000001U        /*!<Bit 0 */\r\n#define  SAI_xSLOTR_FBOFF_1                  0x00000002U        /*!<Bit 1 */\r\n#define  SAI_xSLOTR_FBOFF_2                  0x00000004U        /*!<Bit 2 */\r\n#define  SAI_xSLOTR_FBOFF_3                  0x00000008U        /*!<Bit 3 */\r\n#define  SAI_xSLOTR_FBOFF_4                  0x00000010U        /*!<Bit 4 */\r\n                                            \r\n#define  SAI_xSLOTR_SLOTSZ                   0x000000C0U        /*!<SLOTSZ[1:0] (Slot size)  */\r\n#define  SAI_xSLOTR_SLOTSZ_0                 0x00000040U        /*!<Bit 0 */\r\n#define  SAI_xSLOTR_SLOTSZ_1                 0x00000080U        /*!<Bit 1 */\r\n                                            \r\n#define  SAI_xSLOTR_NBSLOT                   0x00000F00U        /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */\r\n#define  SAI_xSLOTR_NBSLOT_0                 0x00000100U        /*!<Bit 0 */\r\n#define  SAI_xSLOTR_NBSLOT_1                 0x00000200U        /*!<Bit 1 */\r\n#define  SAI_xSLOTR_NBSLOT_2                 0x00000400U        /*!<Bit 2 */\r\n#define  SAI_xSLOTR_NBSLOT_3                 0x00000800U        /*!<Bit 3 */\r\n                                            \r\n#define  SAI_xSLOTR_SLOTEN                   0xFFFF0000U        /*!<SLOTEN[15:0] (Slot Enable)  */\r\n\r\n/*******************  Bit definition for SAI_xIMR register  *******************/\r\n#define  SAI_xIMR_OVRUDRIE                   0x00000001U        /*!<Overrun underrun interrupt enable                              */\r\n#define  SAI_xIMR_MUTEDETIE                  0x00000002U        /*!<Mute detection interrupt enable                                */\r\n#define  SAI_xIMR_WCKCFGIE                   0x00000004U        /*!<Wrong Clock Configuration interrupt enable                     */\r\n#define  SAI_xIMR_FREQIE                     0x00000008U        /*!<FIFO request interrupt enable                                  */\r\n#define  SAI_xIMR_CNRDYIE                    0x00000010U        /*!<Codec not ready interrupt enable                               */\r\n#define  SAI_xIMR_AFSDETIE                   0x00000020U        /*!<Anticipated frame synchronization detection interrupt enable   */\r\n#define  SAI_xIMR_LFSDETIE                   0x00000040U        /*!<Late frame synchronization detection interrupt enable          */\r\n\r\n/********************  Bit definition for SAI_xSR register  *******************/\r\n#define  SAI_xSR_OVRUDR                      0x00000001U         /*!<Overrun underrun                               */\r\n#define  SAI_xSR_MUTEDET                     0x00000002U         /*!<Mute detection                                 */\r\n#define  SAI_xSR_WCKCFG                      0x00000004U         /*!<Wrong Clock Configuration                      */\r\n#define  SAI_xSR_FREQ                        0x00000008U         /*!<FIFO request                                   */\r\n#define  SAI_xSR_CNRDY                       0x00000010U         /*!<Codec not ready                                */\r\n#define  SAI_xSR_AFSDET                      0x00000020U         /*!<Anticipated frame synchronization detection    */\r\n#define  SAI_xSR_LFSDET                      0x00000040U         /*!<Late frame synchronization detection           */\r\n                                             \r\n#define  SAI_xSR_FLVL                        0x00070000U         /*!<FLVL[2:0] (FIFO Level Threshold)               */\r\n#define  SAI_xSR_FLVL_0                      0x00010000U         /*!<Bit 0 */\r\n#define  SAI_xSR_FLVL_1                      0x00020000U         /*!<Bit 1 */\r\n#define  SAI_xSR_FLVL_2                      0x00040000U         /*!<Bit 2 */\r\n\r\n/******************  Bit definition for SAI_xCLRFR register  ******************/\r\n#define  SAI_xCLRFR_COVRUDR                  0x00000001U        /*!<Clear Overrun underrun                               */\r\n#define  SAI_xCLRFR_CMUTEDET                 0x00000002U        /*!<Clear Mute detection                                 */\r\n#define  SAI_xCLRFR_CWCKCFG                  0x00000004U        /*!<Clear Wrong Clock Configuration                      */\r\n#define  SAI_xCLRFR_CFREQ                    0x00000008U        /*!<Clear FIFO request                                   */\r\n#define  SAI_xCLRFR_CCNRDY                   0x00000010U        /*!<Clear Codec not ready                                */\r\n#define  SAI_xCLRFR_CAFSDET                  0x00000020U        /*!<Clear Anticipated frame synchronization detection    */\r\n#define  SAI_xCLRFR_CLFSDET                  0x00000040U        /*!<Clear Late frame synchronization detection           */\r\n\r\n/******************  Bit definition for SAI_xDR register  *********************/\r\n#define  SAI_xDR_DATA                        0xFFFFFFFFU        \r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                              SPDIF-RX Interface                            */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bit definition for SPDIF_CR register  *******************/\r\n#define  SPDIFRX_CR_SPDIFEN                0x00000003U        /*!<Peripheral Block Enable                      */\r\n#define  SPDIFRX_CR_RXDMAEN                0x00000004U        /*!<Receiver DMA Enable for data flow            */\r\n#define  SPDIFRX_CR_RXSTEO                 0x00000008U        /*!<Stereo Mode                                  */\r\n#define  SPDIFRX_CR_DRFMT                  0x00000030U        /*!<RX Data format                               */\r\n#define  SPDIFRX_CR_PMSK                   0x00000040U        /*!<Mask Parity error bit                        */\r\n#define  SPDIFRX_CR_VMSK                   0x00000080U        /*!<Mask of Validity bit                         */\r\n#define  SPDIFRX_CR_CUMSK                  0x00000100U        /*!<Mask of channel status and user bits         */\r\n#define  SPDIFRX_CR_PTMSK                  0x00000200U        /*!<Mask of Preamble Type bits                   */\r\n#define  SPDIFRX_CR_CBDMAEN                0x00000400U        /*!<Control Buffer DMA ENable for control flow   */\r\n#define  SPDIFRX_CR_CHSEL                  0x00000800U        /*!<Channel Selection                            */\r\n#define  SPDIFRX_CR_NBTR                   0x00003000U        /*!<Maximum allowed re-tries during synchronization phase */\r\n#define  SPDIFRX_CR_WFA                    0x00004000U        /*!<Wait For Activity     */\r\n#define  SPDIFRX_CR_INSEL                  0x00070000U        /*!<SPDIF input selection */\r\n\r\n/*******************  Bit definition for SPDIFRX_IMR register  *******************/\r\n#define  SPDIFRX_IMR_RXNEIE                0x00000001U        /*!<RXNE interrupt enable                              */\r\n#define  SPDIFRX_IMR_CSRNEIE               0x00000002U        /*!<Control Buffer Ready Interrupt Enable              */\r\n#define  SPDIFRX_IMR_PERRIE                0x00000004U        /*!<Parity error interrupt enable                      */\r\n#define  SPDIFRX_IMR_OVRIE                 0x00000008U        /*!<Overrun error Interrupt Enable                     */\r\n#define  SPDIFRX_IMR_SBLKIE                0x00000010U        /*!<Synchronization Block Detected Interrupt Enable    */\r\n#define  SPDIFRX_IMR_SYNCDIE               0x00000020U        /*!<Synchronization Done                               */\r\n#define  SPDIFRX_IMR_IFEIE                 0x00000040U        /*!<Serial Interface Error Interrupt Enable            */\r\n\r\n/*******************  Bit definition for SPDIFRX_SR register  *******************/\r\n#define  SPDIFRX_SR_RXNE                   0x00000001U       /*!<Read data register not empty                          */\r\n#define  SPDIFRX_SR_CSRNE                  0x00000002U       /*!<The Control Buffer register is not empty              */\r\n#define  SPDIFRX_SR_PERR                   0x00000004U       /*!<Parity error                                          */\r\n#define  SPDIFRX_SR_OVR                    0x00000008U       /*!<Overrun error                                         */\r\n#define  SPDIFRX_SR_SBD                    0x00000010U       /*!<Synchronization Block Detected                        */\r\n#define  SPDIFRX_SR_SYNCD                  0x00000020U       /*!<Synchronization Done                                  */\r\n#define  SPDIFRX_SR_FERR                   0x00000040U       /*!<Framing error                                         */\r\n#define  SPDIFRX_SR_SERR                   0x00000080U       /*!<Synchronization error                                 */\r\n#define  SPDIFRX_SR_TERR                   0x00000100U       /*!<Time-out error                                        */\r\n#define  SPDIFRX_SR_WIDTH5                 0x7FFF0000U       /*!<Duration of 5 symbols counted with spdif_clk          */\r\n\r\n/*******************  Bit definition for SPDIFRX_IFCR register  *******************/\r\n#define  SPDIFRX_IFCR_PERRCF               0x00000004U       /*!<Clears the Parity error flag                         */\r\n#define  SPDIFRX_IFCR_OVRCF                0x00000008U       /*!<Clears the Overrun error flag                        */\r\n#define  SPDIFRX_IFCR_SBDCF                0x00000010U       /*!<Clears the Synchronization Block Detected flag       */\r\n#define  SPDIFRX_IFCR_SYNCDCF              0x00000020U       /*!<Clears the Synchronization Done flag                 */\r\n\r\n/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/\r\n#define  SPDIFRX_DR0_DR                    0x00FFFFFFU        /*!<Data value            */\r\n#define  SPDIFRX_DR0_PE                    0x01000000U        /*!<Parity Error bit      */\r\n#define  SPDIFRX_DR0_V                     0x02000000U        /*!<Validity bit          */\r\n#define  SPDIFRX_DR0_U                     0x04000000U        /*!<User bit              */\r\n#define  SPDIFRX_DR0_C                     0x08000000U        /*!<Channel Status bit    */\r\n#define  SPDIFRX_DR0_PT                    0x30000000U        /*!<Preamble Type         */\r\n\r\n/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/\r\n#define  SPDIFRX_DR1_DR                    0xFFFFFF00U        /*!<Data value            */\r\n#define  SPDIFRX_DR1_PT                    0x00000030U        /*!<Preamble Type         */\r\n#define  SPDIFRX_DR1_C                     0x00000008U        /*!<Channel Status bit    */\r\n#define  SPDIFRX_DR1_U                     0x00000004U        /*!<User bit              */\r\n#define  SPDIFRX_DR1_V                     0x00000002U        /*!<Validity bit          */\r\n#define  SPDIFRX_DR1_PE                    0x00000001U        /*!<Parity Error bit      */\r\n\r\n/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/\r\n#define  SPDIFRX_DR1_DRNL1                 0xFFFF0000U        /*!<Data value Channel B      */\r\n#define  SPDIFRX_DR1_DRNL2                 0x0000FFFFU        /*!<Data value Channel A      */\r\n\r\n/*******************  Bit definition for SPDIFRX_CSR register   *******************/\r\n#define  SPDIFRX_CSR_USR                   0x0000FFFFU        /*!<User data information           */\r\n#define  SPDIFRX_CSR_CS                    0x00FF0000U        /*!<Channel A status information    */\r\n#define  SPDIFRX_CSR_SOB                   0x01000000U        /*!<Start Of Block                  */\r\n\r\n/*******************  Bit definition for SPDIFRX_DIR register    *******************/\r\n#define  SPDIFRX_DIR_THI                   0x000013FFU        /*!<Threshold LOW      */\r\n#define  SPDIFRX_DIR_TLO                   0x1FFF0000U        /*!<Threshold HIGH     */\r\n\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                          SD host Interface                                 */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/******************  Bit definition for SDMMC_POWER register  ******************/\r\n#define  SDMMC_POWER_PWRCTRL                  0x03U               /*!<PWRCTRL[1:0] bits (Power supply control bits) */\r\n#define  SDMMC_POWER_PWRCTRL_0                0x01U               /*!<Bit 0 */\r\n#define  SDMMC_POWER_PWRCTRL_1                0x02U               /*!<Bit 1 */\r\n\r\n/******************  Bit definition for SDMMC_CLKCR register  ******************/\r\n#define  SDMMC_CLKCR_CLKDIV                   0x00FFU            /*!<Clock divide factor             */\r\n#define  SDMMC_CLKCR_CLKEN                    0x0100U            /*!<Clock enable bit                */\r\n#define  SDMMC_CLKCR_PWRSAV                   0x0200U            /*!<Power saving configuration bit  */\r\n#define  SDMMC_CLKCR_BYPASS                   0x0400U            /*!<Clock divider bypass enable bit */\r\n         \r\n#define  SDMMC_CLKCR_WIDBUS                   0x1800U            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */\r\n#define  SDMMC_CLKCR_WIDBUS_0                 0x0800U            /*!<Bit 0 */\r\n#define  SDMMC_CLKCR_WIDBUS_1                 0x1000U            /*!<Bit 1 */\r\n         \r\n#define  SDMMC_CLKCR_NEGEDGE                  0x2000U            /*!<SDMMC_CK dephasing selection bit */\r\n#define  SDMMC_CLKCR_HWFC_EN                  0x4000U            /*!<HW Flow Control enable          */\r\n\r\n/*******************  Bit definition for SDMMC_ARG register  *******************/\r\n#define  SDMMC_ARG_CMDARG                     0xFFFFFFFFU            /*!<Command argument */\r\n\r\n/*******************  Bit definition for SDMMC_CMD register  *******************/\r\n#define  SDMMC_CMD_CMDINDEX                   0x003FU            /*!<Command Index                               */\r\n         \r\n#define  SDMMC_CMD_WAITRESP                   0x00C0U            /*!<WAITRESP[1:0] bits (Wait for response bits) */\r\n#define  SDMMC_CMD_WAITRESP_0                 0x0040U            /*!< Bit 0 */\r\n#define  SDMMC_CMD_WAITRESP_1                 0x0080U            /*!< Bit 1 */\r\n         \r\n#define  SDMMC_CMD_WAITINT                    0x0100U            /*!<CPSM Waits for Interrupt Request                               */\r\n#define  SDMMC_CMD_WAITPEND                   0x0200U            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */\r\n#define  SDMMC_CMD_CPSMEN                     0x0400U            /*!<Command path state machine (CPSM) Enable bit                   */\r\n#define  SDMMC_CMD_SDIOSUSPEND                0x0800U            /*!<SD I/O suspend command                                         */\r\n\r\n/*****************  Bit definition for SDMMC_RESPCMD register  *****************/\r\n#define  SDMMC_RESPCMD_RESPCMD                0x3FU               /*!<Response command index */\r\n\r\n/******************  Bit definition for SDMMC_RESP0 register  ******************/\r\n#define  SDMMC_RESP0_CARDSTATUS0              0xFFFFFFFFU        /*!<Card Status */\r\n\r\n/******************  Bit definition for SDMMC_RESP1 register  ******************/\r\n#define  SDMMC_RESP1_CARDSTATUS1              0xFFFFFFFFU        /*!<Card Status */\r\n\r\n/******************  Bit definition for SDMMC_RESP2 register  ******************/\r\n#define  SDMMC_RESP2_CARDSTATUS2              0xFFFFFFFFU        /*!<Card Status */\r\n\r\n/******************  Bit definition for SDMMC_RESP3 register  ******************/\r\n#define  SDMMC_RESP3_CARDSTATUS3              0xFFFFFFFFU        /*!<Card Status */\r\n\r\n/******************  Bit definition for SDMMC_RESP4 register  ******************/\r\n#define  SDMMC_RESP4_CARDSTATUS4              0xFFFFFFFFU        /*!<Card Status */\r\n\r\n/******************  Bit definition for SDMMC_DTIMER register  *****************/\r\n#define  SDMMC_DTIMER_DATATIME                0xFFFFFFFFU        /*!<Data timeout period. */\r\n\r\n/******************  Bit definition for SDMMC_DLEN register  *******************/\r\n#define  SDMMC_DLEN_DATALENGTH                0x01FFFFFFU        /*!<Data length value    */\r\n\r\n/******************  Bit definition for SDMMC_DCTRL register  ******************/\r\n#define  SDMMC_DCTRL_DTEN                     0x0001U            /*!<Data transfer enabled bit         */\r\n#define  SDMMC_DCTRL_DTDIR                    0x0002U            /*!<Data transfer direction selection */\r\n#define  SDMMC_DCTRL_DTMODE                   0x0004U            /*!<Data transfer mode selection      */\r\n#define  SDMMC_DCTRL_DMAEN                    0x0008U            /*!<DMA enabled bit                   */\r\n\r\n#define  SDMMC_DCTRL_DBLOCKSIZE               0x00F0U            /*!<DBLOCKSIZE[3:0] bits (Data block size) */\r\n#define  SDMMC_DCTRL_DBLOCKSIZE_0             0x0010U            /*!<Bit 0 */\r\n#define  SDMMC_DCTRL_DBLOCKSIZE_1             0x0020U            /*!<Bit 1 */\r\n#define  SDMMC_DCTRL_DBLOCKSIZE_2             0x0040U            /*!<Bit 2 */\r\n#define  SDMMC_DCTRL_DBLOCKSIZE_3             0x0080U            /*!<Bit 3 */\r\n\r\n#define  SDMMC_DCTRL_RWSTART                  0x0100U            /*!<Read wait start         */\r\n#define  SDMMC_DCTRL_RWSTOP                   0x0200U            /*!<Read wait stop          */\r\n#define  SDMMC_DCTRL_RWMOD                    0x0400U            /*!<Read wait mode          */\r\n#define  SDMMC_DCTRL_SDIOEN                   0x0800U            /*!<SD I/O enable functions */\r\n\r\n/******************  Bit definition for SDMMC_DCOUNT register  *****************/\r\n#define  SDMMC_DCOUNT_DATACOUNT               0x01FFFFFFU        /*!<Data count value */\r\n\r\n/******************  Bit definition for SDMMC_STA registe  ********************/\r\n#define  SDMMC_STA_CCRCFAIL                   0x00000001U        /*!<Command response received (CRC check failed)  */\r\n#define  SDMMC_STA_DCRCFAIL                   0x00000002U        /*!<Data block sent/received (CRC check failed)   */\r\n#define  SDMMC_STA_CTIMEOUT                   0x00000004U        /*!<Command response timeout                      */\r\n#define  SDMMC_STA_DTIMEOUT                   0x00000008U        /*!<Data timeout                                  */\r\n#define  SDMMC_STA_TXUNDERR                   0x00000010U        /*!<Transmit FIFO underrun error                  */\r\n#define  SDMMC_STA_RXOVERR                    0x00000020U        /*!<Received FIFO overrun error                   */\r\n#define  SDMMC_STA_CMDREND                    0x00000040U        /*!<Command response received (CRC check passed)  */\r\n#define  SDMMC_STA_CMDSENT                    0x00000080U        /*!<Command sent (no response required)           */\r\n#define  SDMMC_STA_DATAEND                    0x00000100U        /*!<Data end (data counter, SDIDCOUNT, is zero)   */\r\n#define  SDMMC_STA_DBCKEND                    0x00000400U        /*!<Data block sent/received (CRC check passed)   */\r\n#define  SDMMC_STA_CMDACT                     0x00000800U        /*!<Command transfer in progress                  */\r\n#define  SDMMC_STA_TXACT                      0x00001000U        /*!<Data transmit in progress                     */\r\n#define  SDMMC_STA_RXACT                      0x00002000U        /*!<Data receive in progress                      */\r\n#define  SDMMC_STA_TXFIFOHE                   0x00004000U        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */\r\n#define  SDMMC_STA_RXFIFOHF                   0x00008000U        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */\r\n#define  SDMMC_STA_TXFIFOF                    0x00010000U        /*!<Transmit FIFO full                            */\r\n#define  SDMMC_STA_RXFIFOF                    0x00020000U        /*!<Receive FIFO full                             */\r\n#define  SDMMC_STA_TXFIFOE                    0x00040000U        /*!<Transmit FIFO empty                           */\r\n#define  SDMMC_STA_RXFIFOE                    0x00080000U        /*!<Receive FIFO empty                            */\r\n#define  SDMMC_STA_TXDAVL                     0x00100000U        /*!<Data available in transmit FIFO               */\r\n#define  SDMMC_STA_RXDAVL                     0x00200000U        /*!<Data available in receive FIFO                */\r\n#define  SDMMC_STA_SDIOIT                     0x00400000U        /*!<SDMMC interrupt received                       */\r\n\r\n/*******************  Bit definition for SDMMC_ICR register  *******************/\r\n#define  SDMMC_ICR_CCRCFAILC                  0x00000001U        /*!<CCRCFAIL flag clear bit */\r\n#define  SDMMC_ICR_DCRCFAILC                  0x00000002U        /*!<DCRCFAIL flag clear bit */\r\n#define  SDMMC_ICR_CTIMEOUTC                  0x00000004U        /*!<CTIMEOUT flag clear bit */\r\n#define  SDMMC_ICR_DTIMEOUTC                  0x00000008U        /*!<DTIMEOUT flag clear bit */\r\n#define  SDMMC_ICR_TXUNDERRC                  0x00000010U        /*!<TXUNDERR flag clear bit */\r\n#define  SDMMC_ICR_RXOVERRC                   0x00000020U        /*!<RXOVERR flag clear bit  */\r\n#define  SDMMC_ICR_CMDRENDC                   0x00000040U        /*!<CMDREND flag clear bit  */\r\n#define  SDMMC_ICR_CMDSENTC                   0x00000080U        /*!<CMDSENT flag clear bit  */\r\n#define  SDMMC_ICR_DATAENDC                   0x00000100U        /*!<DATAEND flag clear bit  */\r\n#define  SDMMC_ICR_DBCKENDC                   0x00000400U        /*!<DBCKEND flag clear bit  */\r\n#define  SDMMC_ICR_SDIOITC                    0x00400000U        /*!<SDMMCIT flag clear bit   */\r\n\r\n/******************  Bit definition for SDMMC_MASK register  *******************/\r\n#define  SDMMC_MASK_CCRCFAILIE                0x00000001U        /*!<Command CRC Fail Interrupt Enable          */\r\n#define  SDMMC_MASK_DCRCFAILIE                0x00000002U        /*!<Data CRC Fail Interrupt Enable             */\r\n#define  SDMMC_MASK_CTIMEOUTIE                0x00000004U        /*!<Command TimeOut Interrupt Enable           */\r\n#define  SDMMC_MASK_DTIMEOUTIE                0x00000008U        /*!<Data TimeOut Interrupt Enable              */\r\n#define  SDMMC_MASK_TXUNDERRIE                0x00000010U        /*!<Tx FIFO UnderRun Error Interrupt Enable    */\r\n#define  SDMMC_MASK_RXOVERRIE                 0x00000020U        /*!<Rx FIFO OverRun Error Interrupt Enable     */\r\n#define  SDMMC_MASK_CMDRENDIE                 0x00000040U        /*!<Command Response Received Interrupt Enable */\r\n#define  SDMMC_MASK_CMDSENTIE                 0x00000080U        /*!<Command Sent Interrupt Enable              */\r\n#define  SDMMC_MASK_DATAENDIE                 0x00000100U        /*!<Data End Interrupt Enable                  */\r\n#define  SDMMC_MASK_DBCKENDIE                 0x00000400U        /*!<Data Block End Interrupt Enable            */\r\n#define  SDMMC_MASK_CMDACTIE                  0x00000800U        /*!<CCommand Acting Interrupt Enable           */\r\n#define  SDMMC_MASK_TXACTIE                   0x00001000U        /*!<Data Transmit Acting Interrupt Enable      */\r\n#define  SDMMC_MASK_RXACTIE                   0x00002000U        /*!<Data receive acting interrupt enabled      */\r\n#define  SDMMC_MASK_TXFIFOHEIE                0x00004000U        /*!<Tx FIFO Half Empty interrupt Enable        */\r\n#define  SDMMC_MASK_RXFIFOHFIE                0x00008000U        /*!<Rx FIFO Half Full interrupt Enable         */\r\n#define  SDMMC_MASK_TXFIFOFIE                 0x00010000U        /*!<Tx FIFO Full interrupt Enable              */\r\n#define  SDMMC_MASK_RXFIFOFIE                 0x00020000U        /*!<Rx FIFO Full interrupt Enable              */\r\n#define  SDMMC_MASK_TXFIFOEIE                 0x00040000U        /*!<Tx FIFO Empty interrupt Enable             */\r\n#define  SDMMC_MASK_RXFIFOEIE                 0x00080000U        /*!<Rx FIFO Empty interrupt Enable             */\r\n#define  SDMMC_MASK_TXDAVLIE                  0x00100000U        /*!<Data available in Tx FIFO interrupt Enable */\r\n#define  SDMMC_MASK_RXDAVLIE                  0x00200000U        /*!<Data available in Rx FIFO interrupt Enable */\r\n#define  SDMMC_MASK_SDIOITIE                  0x00400000U        /*!<SDMMC Mode Interrupt Received interrupt Enable */\r\n\r\n/*****************  Bit definition for SDMMC_FIFOCNT register  *****************/\r\n#define  SDMMC_FIFOCNT_FIFOCOUNT              0x00FFFFFFU        /*!<Remaining number of words to be written to or read from the FIFO */\r\n\r\n/******************  Bit definition for SDMMC_FIFO register  *******************/\r\n#define  SDMMC_FIFO_FIFODATA                  0xFFFFFFFFU        /*!<Receive and transmit FIFO data */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                        Serial Peripheral Interface (SPI)                   */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************  Bit definition for SPI_CR1 register  ********************/\r\n#define  SPI_CR1_CPHA                        0x00000001U        /*!< Clock Phase                        */\r\n#define  SPI_CR1_CPOL                        0x00000002U        /*!< Clock Polarity                     */\r\n#define  SPI_CR1_MSTR                        0x00000004U        /*!< Master Selection                   */\r\n#define  SPI_CR1_BR                          0x00000038U        /*!< BR[2:0] bits (Baud Rate Control)   */\r\n#define  SPI_CR1_BR_0                        0x00000008U        /*!< Bit 0 */\r\n#define  SPI_CR1_BR_1                        0x00000010U        /*!< Bit 1 */\r\n#define  SPI_CR1_BR_2                        0x00000020U        /*!< Bit 2 */\r\n#define  SPI_CR1_SPE                         0x00000040U        /*!< SPI Enable                          */\r\n#define  SPI_CR1_LSBFIRST                    0x00000080U        /*!< Frame Format                        */\r\n#define  SPI_CR1_SSI                         0x00000100U        /*!< Internal slave select               */\r\n#define  SPI_CR1_SSM                         0x00000200U        /*!< Software slave management           */\r\n#define  SPI_CR1_RXONLY                      0x00000400U        /*!< Receive only                        */\r\n#define  SPI_CR1_CRCL                        0x00000800U        /*!< CRC Length                          */\r\n#define  SPI_CR1_CRCNEXT                     0x00001000U        /*!< Transmit CRC next                   */\r\n#define  SPI_CR1_CRCEN                       0x00002000U        /*!< Hardware CRC calculation enable     */\r\n#define  SPI_CR1_BIDIOE                      0x00004000U        /*!< Output enable in bidirectional mode */\r\n#define  SPI_CR1_BIDIMODE                    0x00008000U        /*!< Bidirectional data mode enable      */\r\n\r\n/*******************  Bit definition for SPI_CR2 register  ********************/\r\n#define  SPI_CR2_RXDMAEN                     0x00000001U        /*!< Rx Buffer DMA Enable                 */\r\n#define  SPI_CR2_TXDMAEN                     0x00000002U        /*!< Tx Buffer DMA Enable                 */\r\n#define  SPI_CR2_SSOE                        0x00000004U        /*!< SS Output Enable                     */\r\n#define  SPI_CR2_NSSP                        0x00000008U        /*!< NSS pulse management Enable          */\r\n#define  SPI_CR2_FRF                         0x00000010U        /*!< Frame Format Enable                  */\r\n#define  SPI_CR2_ERRIE                       0x00000020U        /*!< Error Interrupt Enable               */\r\n#define  SPI_CR2_RXNEIE                      0x00000040U        /*!< RX buffer Not Empty Interrupt Enable */\r\n#define  SPI_CR2_TXEIE                       0x00000080U        /*!< Tx buffer Empty Interrupt Enable     */\r\n#define  SPI_CR2_DS                          0x00000F00U        /*!< DS[3:0] Data Size                    */\r\n#define  SPI_CR2_DS_0                        0x00000100U        /*!< Bit 0 */\r\n#define  SPI_CR2_DS_1                        0x00000200U        /*!< Bit 1 */\r\n#define  SPI_CR2_DS_2                        0x00000400U        /*!< Bit 2 */\r\n#define  SPI_CR2_DS_3                        0x00000800U        /*!< Bit 3 */\r\n#define  SPI_CR2_FRXTH                       0x00001000U        /*!< FIFO reception Threshold           */\r\n#define  SPI_CR2_LDMARX                      0x00002000U        /*!< Last DMA transfer for reception    */\r\n#define  SPI_CR2_LDMATX                      0x00004000U        /*!< Last DMA transfer for transmission */\r\n\r\n/********************  Bit definition for SPI_SR register  ********************/\r\n#define  SPI_SR_RXNE                         0x00000001U        /*!< Receive buffer Not Empty  */\r\n#define  SPI_SR_TXE                          0x00000002U        /*!< Transmit buffer Empty     */\r\n#define  SPI_SR_CHSIDE                       0x00000004U        /*!< Channel side              */\r\n#define  SPI_SR_UDR                          0x00000008U        /*!< Underrun flag             */\r\n#define  SPI_SR_CRCERR                       0x00000010U        /*!< CRC Error flag            */\r\n#define  SPI_SR_MODF                         0x00000020U        /*!< Mode fault                */\r\n#define  SPI_SR_OVR                          0x00000040U        /*!< Overrun flag              */\r\n#define  SPI_SR_BSY                          0x00000080U        /*!< Busy flag                 */\r\n#define  SPI_SR_FRE                          0x00000100U        /*!< TI frame format error     */\r\n#define  SPI_SR_FRLVL                        0x00000600U        /*!< FIFO Reception Level      */\r\n#define  SPI_SR_FRLVL_0                      0x00000200U        /*!< Bit 0 */\r\n#define  SPI_SR_FRLVL_1                      0x00000400U        /*!< Bit 1 */\r\n#define  SPI_SR_FTLVL                        0x00001800U        /*!< FIFO Transmission Level   */\r\n#define  SPI_SR_FTLVL_0                      0x00000800U        /*!< Bit 0 */\r\n#define  SPI_SR_FTLVL_1                      0x00001000U        /*!< Bit 1 */  \r\n\r\n/********************  Bit definition for SPI_DR register  ********************/\r\n#define  SPI_DR_DR                           0xFFFFU            /*!< Data Register */\r\n\r\n/*******************  Bit definition for SPI_CRCPR register  ******************/\r\n#define  SPI_CRCPR_CRCPOLY                   0xFFFFU            /*!< CRC polynomial register */\r\n\r\n/******************  Bit definition for SPI_RXCRCR register  ******************/\r\n#define  SPI_RXCRCR_RXCRC                    0xFFFFU            /*!< Rx CRC Register */\r\n\r\n/******************  Bit definition for SPI_TXCRCR register  ******************/\r\n#define  SPI_TXCRCR_TXCRC                    0xFFFFU            /*!< Tx CRC Register */\r\n\r\n/******************  Bit definition for SPI_I2SCFGR register  *****************/\r\n#define  SPI_I2SCFGR_CHLEN                   0x00000001U        /*!<Channel length (number of bits per audio channel) */\r\n#define  SPI_I2SCFGR_DATLEN                  0x00000006U        /*!<DATLEN[1:0] bits (Data length to be transferred)  */\r\n#define  SPI_I2SCFGR_DATLEN_0                0x00000002U        /*!<Bit 0 */\r\n#define  SPI_I2SCFGR_DATLEN_1                0x00000004U        /*!<Bit 1 */\r\n#define  SPI_I2SCFGR_CKPOL                   0x00000008U        /*!<steady state clock polarity                       */\r\n#define  SPI_I2SCFGR_I2SSTD                  0x00000030U        /*!<I2SSTD[1:0] bits (I2S standard selection)         */\r\n#define  SPI_I2SCFGR_I2SSTD_0                0x00000010U        /*!<Bit 0 */\r\n#define  SPI_I2SCFGR_I2SSTD_1                0x00000020U        /*!<Bit 1 */\r\n#define  SPI_I2SCFGR_PCMSYNC                 0x00000080U        /*!<PCM frame synchronization                         */\r\n#define  SPI_I2SCFGR_I2SCFG                  0x00000300U        /*!<I2SCFG[1:0] bits (I2S configuration mode)         */\r\n#define  SPI_I2SCFGR_I2SCFG_0                0x00000100U        /*!<Bit 0 */\r\n#define  SPI_I2SCFGR_I2SCFG_1                0x00000200U        /*!<Bit 1 */\r\n#define  SPI_I2SCFGR_I2SE                    0x00000400U        /*!<I2S Enable                                        */\r\n#define  SPI_I2SCFGR_I2SMOD                  0x00000800U        /*!<I2S mode selection                                */\r\n#define  SPI_I2SCFGR_ASTRTEN                 0x00001000U        /*!<Asynchronous start enable                        */\r\n\r\n/******************  Bit definition for SPI_I2SPR register  *******************/\r\n#define  SPI_I2SPR_I2SDIV                    0x00FFU            /*!<I2S Linear prescaler         */\r\n#define  SPI_I2SPR_ODD                       0x0100U            /*!<Odd factor for the prescaler */\r\n#define  SPI_I2SPR_MCKOE                     0x0200U            /*!<Master Clock Output Enable   */\r\n\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                 SYSCFG                                     */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/******************  Bit definition for SYSCFG_MEMRMP register  ***************/  \r\n#define SYSCFG_MEMRMP_MEM_BOOT         0x00000001U /*!< Boot information after Reset */\r\n\r\n\r\n#define SYSCFG_MEMRMP_SWP_FMC          0x00000C00U /*!< FMC Memory Mapping swapping */\r\n#define SYSCFG_MEMRMP_SWP_FMC_0        0x00000400U \r\n#define SYSCFG_MEMRMP_SWP_FMC_1        0x00000800U \r\n\r\n/******************  Bit definition for SYSCFG_PMC register  ******************/\r\n\r\n#define SYSCFG_PMC_ADCxDC2              0x00070000U /*!< Refer to AN4073 on how to use this bit  */\r\n#define SYSCFG_PMC_ADC1DC2              0x00010000U /*!< Refer to AN4073 on how to use this bit  */\r\n#define SYSCFG_PMC_ADC2DC2              0x00020000U /*!< Refer to AN4073 on how to use this bit  */\r\n#define SYSCFG_PMC_ADC3DC2              0x00040000U /*!< Refer to AN4073 on how to use this bit  */\r\n\r\n#define SYSCFG_PMC_MII_RMII_SEL         0x00800000U /*!<Ethernet PHY interface selection */\r\n\r\n/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/\r\n#define SYSCFG_EXTICR1_EXTI0            0x000FU /*!<EXTI 0 configuration */\r\n#define SYSCFG_EXTICR1_EXTI1            0x00F0U /*!<EXTI 1 configuration */\r\n#define SYSCFG_EXTICR1_EXTI2            0x0F00U /*!<EXTI 2 configuration */\r\n#define SYSCFG_EXTICR1_EXTI3            0xF000U /*!<EXTI 3 configuration */\r\n/** \r\n  * @brief   EXTI0 configuration  \r\n  */ \r\n#define SYSCFG_EXTICR1_EXTI0_PA         0x0000U /*!<PA[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PB         0x0001U /*!<PB[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PC         0x0002U /*!<PC[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PD         0x0003U /*!<PD[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PE         0x0004U /*!<PE[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PF         0x0005U /*!<PF[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PG         0x0006U /*!<PG[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PH         0x0007U /*!<PH[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PI         0x0008U /*!<PI[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PJ         0x0009U /*!<PJ[0] pin */\r\n#define SYSCFG_EXTICR1_EXTI0_PK         0x000AU /*!<PK[0] pin */\r\n\r\n/** \r\n  * @brief   EXTI1 configuration  \r\n  */ \r\n#define SYSCFG_EXTICR1_EXTI1_PA         0x0000U /*!<PA[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PB         0x0010U /*!<PB[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PC         0x0020U /*!<PC[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PD         0x0030U /*!<PD[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PE         0x0040U /*!<PE[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PF         0x0050U /*!<PF[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PG         0x0060U /*!<PG[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PH         0x0070U /*!<PH[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PI         0x0080U /*!<PI[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PJ         0x0090U /*!<PJ[1] pin */\r\n#define SYSCFG_EXTICR1_EXTI1_PK         0x00A0U /*!<PK[1] pin */\r\n\r\n/** \r\n  * @brief   EXTI2 configuration  \r\n  */ \r\n#define SYSCFG_EXTICR1_EXTI2_PA         0x0000U /*!<PA[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PB         0x0100U /*!<PB[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PC         0x0200U /*!<PC[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PD         0x0300U /*!<PD[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PE         0x0400U /*!<PE[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PF         0x0500U /*!<PF[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PG         0x0600U /*!<PG[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PH         0x0700U /*!<PH[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PI         0x0800U /*!<PI[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PJ         0x0900U /*!<PJ[2] pin */\r\n#define SYSCFG_EXTICR1_EXTI2_PK         0x0A00U /*!<PK[2] pin */\r\n\r\n/** \r\n  * @brief   EXTI3 configuration  \r\n  */ \r\n#define SYSCFG_EXTICR1_EXTI3_PA         0x0000U /*!<PA[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PB         0x1000U /*!<PB[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PC         0x2000U /*!<PC[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PD         0x3000U /*!<PD[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PE         0x4000U /*!<PE[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PF         0x5000U /*!<PF[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PG         0x6000U /*!<PG[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PH         0x7000U /*!<PH[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PI         0x8000U /*!<PI[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PJ         0x9000U /*!<PJ[3] pin */\r\n#define SYSCFG_EXTICR1_EXTI3_PK         0xA000U /*!<PK[3] pin */\r\n\r\n/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/\r\n#define SYSCFG_EXTICR2_EXTI4            0x000FU /*!<EXTI 4 configuration */\r\n#define SYSCFG_EXTICR2_EXTI5            0x00F0U /*!<EXTI 5 configuration */\r\n#define SYSCFG_EXTICR2_EXTI6            0x0F00U /*!<EXTI 6 configuration */\r\n#define SYSCFG_EXTICR2_EXTI7            0xF000U /*!<EXTI 7 configuration */\r\n/** \r\n  * @brief   EXTI4 configuration  \r\n  */ \r\n#define SYSCFG_EXTICR2_EXTI4_PA         0x0000U /*!<PA[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PB         0x0001U /*!<PB[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PC         0x0002U /*!<PC[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PD         0x0003U /*!<PD[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PE         0x0004U /*!<PE[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PF         0x0005U /*!<PF[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PG         0x0006U /*!<PG[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PH         0x0007U /*!<PH[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PI         0x0008U /*!<PI[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PJ         0x0009U /*!<PJ[4] pin */\r\n#define SYSCFG_EXTICR2_EXTI4_PK         0x000AU /*!<PK[4] pin */\r\n\r\n/** \r\n  * @brief   EXTI5 configuration  \r\n  */ \r\n#define SYSCFG_EXTICR2_EXTI5_PA         0x0000U /*!<PA[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PB         0x0010U /*!<PB[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PC         0x0020U /*!<PC[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PD         0x0030U /*!<PD[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PE         0x0040U /*!<PE[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PF         0x0050U /*!<PF[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PG         0x0060U /*!<PG[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PH         0x0070U /*!<PH[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PI         0x0080U /*!<PI[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PJ         0x0090U /*!<PJ[5] pin */\r\n#define SYSCFG_EXTICR2_EXTI5_PK         0x00A0U /*!<PK[5] pin */\r\n\r\n/** \r\n  * @brief   EXTI6 configuration  \r\n  */ \r\n#define SYSCFG_EXTICR2_EXTI6_PA         0x0000U /*!<PA[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PB         0x0100U /*!<PB[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PC         0x0200U /*!<PC[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PD         0x0300U /*!<PD[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PE         0x0400U /*!<PE[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PF         0x0500U /*!<PF[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PG         0x0600U /*!<PG[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PH         0x0700U /*!<PH[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PI         0x0800U /*!<PI[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PJ         0x0900U /*!<PJ[6] pin */\r\n#define SYSCFG_EXTICR2_EXTI6_PK         0x0A00U /*!<PK[6] pin */\r\n\r\n/** \r\n  * @brief   EXTI7 configuration  \r\n  */ \r\n#define SYSCFG_EXTICR2_EXTI7_PA         0x0000U /*!<PA[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PB         0x1000U /*!<PB[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PC         0x2000U /*!<PC[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PD         0x3000U /*!<PD[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PE         0x4000U /*!<PE[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PF         0x5000U /*!<PF[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PG         0x6000U /*!<PG[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PH         0x7000U /*!<PH[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PI         0x8000U /*!<PI[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PJ         0x9000U /*!<PJ[7] pin */\r\n#define SYSCFG_EXTICR2_EXTI7_PK         0xA000U /*!<PK[7] pin */\r\n\r\n/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/\r\n#define SYSCFG_EXTICR3_EXTI8            0x000FU /*!<EXTI 8 configuration */\r\n#define SYSCFG_EXTICR3_EXTI9            0x00F0U /*!<EXTI 9 configuration */\r\n#define SYSCFG_EXTICR3_EXTI10           0x0F00U /*!<EXTI 10 configuration */\r\n#define SYSCFG_EXTICR3_EXTI11           0xF000U /*!<EXTI 11 configuration */\r\n           \r\n/** \r\n  * @brief   EXTI8 configuration  \r\n  */ \r\n#define SYSCFG_EXTICR3_EXTI8_PA         0x0000U /*!<PA[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PB         0x0001U /*!<PB[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PC         0x0002U /*!<PC[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PD         0x0003U /*!<PD[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PE         0x0004U /*!<PE[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PF         0x0005U /*!<PF[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PG         0x0006U /*!<PG[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PH         0x0007U /*!<PH[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PI         0x0008U /*!<PI[8] pin */\r\n#define SYSCFG_EXTICR3_EXTI8_PJ         0x0009U /*!<PJ[8] pin */\r\n\r\n/** \r\n  * @brief   EXTI9 configuration  \r\n  */ \r\n#define SYSCFG_EXTICR3_EXTI9_PA         0x0000U /*!<PA[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PB         0x0010U /*!<PB[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PC         0x0020U /*!<PC[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PD         0x0030U /*!<PD[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PE         0x0040U /*!<PE[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PF         0x0050U /*!<PF[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PG         0x0060U /*!<PG[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PH         0x0070U /*!<PH[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PI         0x0080U /*!<PI[9] pin */\r\n#define SYSCFG_EXTICR3_EXTI9_PJ         0x0090U /*!<PJ[9] pin */\r\n\r\n/** \r\n  * @brief   EXTI10 configuration  \r\n  */ \r\n#define SYSCFG_EXTICR3_EXTI10_PA        0x0000U /*!<PA[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PB        0x0100U /*!<PB[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PC        0x0200U /*!<PC[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PD        0x0300U /*!<PD[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PE        0x0400U /*!<PE[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PF        0x0500U /*!<PF[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PG        0x0600U /*!<PG[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PH        0x0700U /*!<PH[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PI        0x0800U /*!<PI[10] pin */\r\n#define SYSCFG_EXTICR3_EXTI10_PJ        0x0900U /*!<PJ[10] pin */\r\n\r\n/** \r\n  * @brief   EXTI11 configuration  \r\n  */ \r\n#define SYSCFG_EXTICR3_EXTI11_PA        0x0000U /*!<PA[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PB        0x1000U /*!<PB[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PC        0x2000U /*!<PC[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PD        0x3000U /*!<PD[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PE        0x4000U /*!<PE[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PF        0x5000U /*!<PF[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PG        0x6000U /*!<PG[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PH        0x7000U /*!<PH[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PI        0x8000U /*!<PI[11] pin */\r\n#define SYSCFG_EXTICR3_EXTI11_PJ        0x9000U /*!<PJ[11] pin */\r\n\r\n\r\n/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/\r\n#define SYSCFG_EXTICR4_EXTI12           0x000FU /*!<EXTI 12 configuration */\r\n#define SYSCFG_EXTICR4_EXTI13           0x00F0U /*!<EXTI 13 configuration */\r\n#define SYSCFG_EXTICR4_EXTI14           0x0F00U /*!<EXTI 14 configuration */\r\n#define SYSCFG_EXTICR4_EXTI15           0xF000U /*!<EXTI 15 configuration */\r\n/** \r\n  * @brief   EXTI12 configuration  \r\n  */ \r\n#define SYSCFG_EXTICR4_EXTI12_PA        0x0000U /*!<PA[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PB        0x0001U /*!<PB[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PC        0x0002U /*!<PC[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PD        0x0003U /*!<PD[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PE        0x0004U /*!<PE[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PF        0x0005U /*!<PF[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PG        0x0006U /*!<PG[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PH        0x0007U /*!<PH[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PI        0x0008U /*!<PI[12] pin */\r\n#define SYSCFG_EXTICR4_EXTI12_PJ        0x0009U /*!<PJ[12] pin */\r\n\r\n/** \r\n  * @brief   EXTI13 configuration  \r\n  */ \r\n#define SYSCFG_EXTICR4_EXTI13_PA        0x0000U /*!<PA[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PB        0x0010U /*!<PB[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PC        0x0020U /*!<PC[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PD        0x0030U /*!<PD[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PE        0x0040U /*!<PE[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PF        0x0050U /*!<PF[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PG        0x0060U /*!<PG[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PH        0x0070U /*!<PH[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PI        0x0080U /*!<PI[13] pin */\r\n#define SYSCFG_EXTICR4_EXTI13_PJ        0x0090U /*!<PJ[13] pin */\r\n\r\n/** \r\n  * @brief   EXTI14 configuration  \r\n  */ \r\n#define SYSCFG_EXTICR4_EXTI14_PA        0x0000U /*!<PA[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PB        0x0100U /*!<PB[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PC        0x0200U /*!<PC[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PD        0x0300U /*!<PD[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PE        0x0400U /*!<PE[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PF        0x0500U /*!<PF[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PG        0x0600U /*!<PG[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PH        0x0700U /*!<PH[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PI        0x0800U /*!<PI[14] pin */\r\n#define SYSCFG_EXTICR4_EXTI14_PJ        0x0900U /*!<PJ[14] pin */\r\n\r\n/** \r\n  * @brief   EXTI15 configuration  \r\n  */ \r\n#define SYSCFG_EXTICR4_EXTI15_PA        0x0000U /*!<PA[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PB        0x1000U /*!<PB[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PC        0x2000U /*!<PC[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PD        0x3000U /*!<PD[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PE        0x4000U /*!<PE[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PF        0x5000U /*!<PF[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PG        0x6000U /*!<PG[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PH        0x7000U /*!<PH[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PI        0x8000U /*!<PI[15] pin */\r\n#define SYSCFG_EXTICR4_EXTI15_PJ        0x9000U /*!<PJ[15] pin */\r\n\r\n\r\n/******************  Bit definition for SYSCFG_CMPCR register  ****************/  \r\n#define SYSCFG_CMPCR_CMP_PD             0x00000001U /*!<Compensation cell power-down */\r\n#define SYSCFG_CMPCR_READY              0x00000100U /*!<Compensation cell ready flag */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                    TIM                                     */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************  Bit definition for TIM_CR1 register  ********************/\r\n#define  TIM_CR1_CEN                         0x0001U            /*!<Counter enable        */\r\n#define  TIM_CR1_UDIS                        0x0002U            /*!<Update disable        */\r\n#define  TIM_CR1_URS                         0x0004U            /*!<Update request source */\r\n#define  TIM_CR1_OPM                         0x0008U            /*!<One pulse mode        */\r\n#define  TIM_CR1_DIR                         0x0010U            /*!<Direction             */\r\n\r\n#define  TIM_CR1_CMS                         0x0060U            /*!<CMS[1:0] bits (Center-aligned mode selection) */\r\n#define  TIM_CR1_CMS_0                       0x0020U            /*!<Bit 0 */\r\n#define  TIM_CR1_CMS_1                       0x0040U            /*!<Bit 1 */\r\n\r\n#define  TIM_CR1_ARPE                        0x0080U            /*!<Auto-reload preload enable     */\r\n\r\n#define  TIM_CR1_CKD                         0x0300U            /*!<CKD[1:0] bits (clock division) */\r\n#define  TIM_CR1_CKD_0                       0x0100U            /*!<Bit 0 */\r\n#define  TIM_CR1_CKD_1                       0x0200U            /*!<Bit 1 */\r\n#define  TIM_CR1_UIFREMAP                    0x0800U            /*!<UIF status bit */\r\n\r\n/*******************  Bit definition for TIM_CR2 register  ********************/\r\n#define  TIM_CR2_CCPC                        0x00000001U            /*!<Capture/Compare Preloaded Control        */\r\n#define  TIM_CR2_CCUS                        0x00000004U            /*!<Capture/Compare Control Update Selection */\r\n#define  TIM_CR2_CCDS                        0x00000008U            /*!<Capture/Compare DMA Selection            */\r\n\r\n#define  TIM_CR2_OIS5                        0x00010000U            /*!<Output Idle state 4 (OC4 output) */\r\n#define  TIM_CR2_OIS6                        0x00040000U            /*!<Output Idle state 4 (OC4 output) */\r\n\r\n#define  TIM_CR2_MMS                         0x0070U           /*!<MMS[2:0] bits (Master Mode Selection) */\r\n#define  TIM_CR2_MMS_0                       0x0010U           /*!<Bit 0 */\r\n#define  TIM_CR2_MMS_1                       0x0020U           /*!<Bit 1 */\r\n#define  TIM_CR2_MMS_2                       0x0040U           /*!<Bit 2 */\r\n\r\n#define  TIM_CR2_MMS2                        0x00F00000U            /*!<MMS[2:0] bits (Master Mode Selection) */\r\n#define  TIM_CR2_MMS2_0                      0x00100000U            /*!<Bit 0 */\r\n#define  TIM_CR2_MMS2_1                      0x00200000U            /*!<Bit 1 */\r\n#define  TIM_CR2_MMS2_2                      0x00400000U            /*!<Bit 2 */\r\n#define  TIM_CR2_MMS2_3                      0x00800000U            /*!<Bit 2 */\r\n\r\n#define  TIM_CR2_TI1S                        0x0080U            /*!<TI1 Selection */\r\n#define  TIM_CR2_OIS1                        0x0100U            /*!<Output Idle state 1 (OC1 output)  */\r\n#define  TIM_CR2_OIS1N                       0x0200U            /*!<Output Idle state 1 (OC1N output) */\r\n#define  TIM_CR2_OIS2                        0x0400U            /*!<Output Idle state 2 (OC2 output)  */\r\n#define  TIM_CR2_OIS2N                       0x0800U            /*!<Output Idle state 2 (OC2N output) */\r\n#define  TIM_CR2_OIS3                        0x1000U            /*!<Output Idle state 3 (OC3 output)  */\r\n#define  TIM_CR2_OIS3N                       0x2000U            /*!<Output Idle state 3 (OC3N output) */\r\n#define  TIM_CR2_OIS4                        0x4000U            /*!<Output Idle state 4 (OC4 output)  */\r\n\r\n/*******************  Bit definition for TIM_SMCR register  *******************/\r\n#define  TIM_SMCR_SMS                        0x00010007U            /*!<SMS[2:0] bits (Slave mode selection)    */\r\n#define  TIM_SMCR_SMS_0                      0x00000001U            /*!<Bit 0 */\r\n#define  TIM_SMCR_SMS_1                      0x00000002U            /*!<Bit 1 */\r\n#define  TIM_SMCR_SMS_2                      0x00000004U            /*!<Bit 2 */\r\n#define  TIM_SMCR_SMS_3                      0x00010000U            /*!<Bit 3 */\r\n#define  TIM_SMCR_OCCS                       0x00000008U            /*!< OCREF clear selection */\r\n\r\n#define  TIM_SMCR_TS                         0x0070U            /*!<TS[2:0] bits (Trigger selection)        */\r\n#define  TIM_SMCR_TS_0                       0x0010U            /*!<Bit 0 */\r\n#define  TIM_SMCR_TS_1                       0x0020U            /*!<Bit 1 */\r\n#define  TIM_SMCR_TS_2                       0x0040U            /*!<Bit 2 */\r\n\r\n#define  TIM_SMCR_MSM                        0x0080U            /*!<Master/slave mode                       */\r\n\r\n#define  TIM_SMCR_ETF                        0x0F00U            /*!<ETF[3:0] bits (External trigger filter) */\r\n#define  TIM_SMCR_ETF_0                      0x0100U            /*!<Bit 0 */\r\n#define  TIM_SMCR_ETF_1                      0x0200U            /*!<Bit 1 */\r\n#define  TIM_SMCR_ETF_2                      0x0400U            /*!<Bit 2 */\r\n#define  TIM_SMCR_ETF_3                      0x0800U            /*!<Bit 3 */\r\n\r\n#define  TIM_SMCR_ETPS                       0x3000U            /*!<ETPS[1:0] bits (External trigger prescaler) */\r\n#define  TIM_SMCR_ETPS_0                     0x1000U            /*!<Bit 0 */\r\n#define  TIM_SMCR_ETPS_1                     0x2000U            /*!<Bit 1 */\r\n\r\n#define  TIM_SMCR_ECE                        0x4000U            /*!<External clock enable     */\r\n#define  TIM_SMCR_ETP                        0x8000U            /*!<External trigger polarity */\r\n\r\n/*******************  Bit definition for TIM_DIER register  *******************/\r\n#define  TIM_DIER_UIE                        0x0001U            /*!<Update interrupt enable */\r\n#define  TIM_DIER_CC1IE                      0x0002U            /*!<Capture/Compare 1 interrupt enable   */\r\n#define  TIM_DIER_CC2IE                      0x0004U            /*!<Capture/Compare 2 interrupt enable   */\r\n#define  TIM_DIER_CC3IE                      0x0008U            /*!<Capture/Compare 3 interrupt enable   */\r\n#define  TIM_DIER_CC4IE                      0x0010U            /*!<Capture/Compare 4 interrupt enable   */\r\n#define  TIM_DIER_COMIE                      0x0020U            /*!<COM interrupt enable                 */\r\n#define  TIM_DIER_TIE                        0x0040U            /*!<Trigger interrupt enable             */\r\n#define  TIM_DIER_BIE                        0x0080U            /*!<Break interrupt enable               */\r\n#define  TIM_DIER_UDE                        0x0100U            /*!<Update DMA request enable            */\r\n#define  TIM_DIER_CC1DE                      0x0200U            /*!<Capture/Compare 1 DMA request enable */\r\n#define  TIM_DIER_CC2DE                      0x0400U            /*!<Capture/Compare 2 DMA request enable */\r\n#define  TIM_DIER_CC3DE                      0x0800U            /*!<Capture/Compare 3 DMA request enable */\r\n#define  TIM_DIER_CC4DE                      0x1000U            /*!<Capture/Compare 4 DMA request enable */\r\n#define  TIM_DIER_COMDE                      0x2000U            /*!<COM DMA request enable               */\r\n#define  TIM_DIER_TDE                        0x4000U            /*!<Trigger DMA request enable           */\r\n\r\n/********************  Bit definition for TIM_SR register  ********************/\r\n#define  TIM_SR_UIF                          0x0001U            /*!<Update interrupt Flag              */\r\n#define  TIM_SR_CC1IF                        0x0002U            /*!<Capture/Compare 1 interrupt Flag   */\r\n#define  TIM_SR_CC2IF                        0x0004U            /*!<Capture/Compare 2 interrupt Flag   */\r\n#define  TIM_SR_CC3IF                        0x0008U            /*!<Capture/Compare 3 interrupt Flag   */\r\n#define  TIM_SR_CC4IF                        0x0010U            /*!<Capture/Compare 4 interrupt Flag   */\r\n#define  TIM_SR_COMIF                        0x0020U            /*!<COM interrupt Flag                 */\r\n#define  TIM_SR_TIF                          0x0040U            /*!<Trigger interrupt Flag             */\r\n#define  TIM_SR_BIF                          0x0080U            /*!<Break interrupt Flag               */\r\n#define  TIM_SR_B2IF                         0x0100U            /*!<Break2 interrupt Flag               */\r\n#define  TIM_SR_CC1OF                        0x0200U            /*!<Capture/Compare 1 Overcapture Flag */\r\n#define  TIM_SR_CC2OF                        0x0400U            /*!<Capture/Compare 2 Overcapture Flag */\r\n#define  TIM_SR_CC3OF                        0x0800U            /*!<Capture/Compare 3 Overcapture Flag */\r\n#define  TIM_SR_CC4OF                        0x1000U            /*!<Capture/Compare 4 Overcapture Flag */\r\n\r\n/*******************  Bit definition for TIM_EGR register  ********************/\r\n#define  TIM_EGR_UG                          0x00000001U               /*!<Update Generation                         */\r\n#define  TIM_EGR_CC1G                        0x00000002U               /*!<Capture/Compare 1 Generation              */\r\n#define  TIM_EGR_CC2G                        0x00000004U               /*!<Capture/Compare 2 Generation              */\r\n#define  TIM_EGR_CC3G                        0x00000008U               /*!<Capture/Compare 3 Generation              */\r\n#define  TIM_EGR_CC4G                        0x00000010U               /*!<Capture/Compare 4 Generation              */\r\n#define  TIM_EGR_COMG                        0x00000020U               /*!<Capture/Compare Control Update Generation */\r\n#define  TIM_EGR_TG                          0x00000040U               /*!<Trigger Generation                        */\r\n#define  TIM_EGR_BG                          0x00000080U               /*!<Break Generation                          */\r\n#define  TIM_EGR_B2G                         0x00000100U              /*!<Break2 Generation                          */\r\n\r\n/******************  Bit definition for TIM_CCMR1 register  *******************/\r\n#define  TIM_CCMR1_CC1S                      0x00000003U            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\r\n#define  TIM_CCMR1_CC1S_0                    0x00000001U            /*!<Bit 0 */\r\n#define  TIM_CCMR1_CC1S_1                    0x00000002U            /*!<Bit 1 */\r\n\r\n#define  TIM_CCMR1_OC1FE                     0x00000004U            /*!<Output Compare 1 Fast enable                 */\r\n#define  TIM_CCMR1_OC1PE                     0x00000008U            /*!<Output Compare 1 Preload enable              */\r\n\r\n#define  TIM_CCMR1_OC1M                      0x00010070U            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */\r\n#define  TIM_CCMR1_OC1M_0                    0x00000010U            /*!<Bit 0 */\r\n#define  TIM_CCMR1_OC1M_1                    0x00000020U            /*!<Bit 1 */\r\n#define  TIM_CCMR1_OC1M_2                    0x00000040U            /*!<Bit 2 */\r\n#define  TIM_CCMR1_OC1M_3                    0x00010000U            /*!<Bit 3 */\r\n\r\n#define  TIM_CCMR1_OC1CE                     0x00000080U            /*!<Output Compare 1Clear Enable                 */\r\n\r\n#define  TIM_CCMR1_CC2S                      0x00000300U            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\r\n#define  TIM_CCMR1_CC2S_0                    0x00000100U            /*!<Bit 0 */\r\n#define  TIM_CCMR1_CC2S_1                    0x00000200U            /*!<Bit 1 */\r\n\r\n#define  TIM_CCMR1_OC2FE                     0x00000400U            /*!<Output Compare 2 Fast enable                 */\r\n#define  TIM_CCMR1_OC2PE                     0x00000800U            /*!<Output Compare 2 Preload enable              */\r\n\r\n#define  TIM_CCMR1_OC2M                      0x01007000U            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */\r\n#define  TIM_CCMR1_OC2M_0                    0x00001000U            /*!<Bit 0 */\r\n#define  TIM_CCMR1_OC2M_1                    0x00002000U            /*!<Bit 1 */\r\n#define  TIM_CCMR1_OC2M_2                    0x00004000U            /*!<Bit 2 */\r\n#define  TIM_CCMR1_OC2M_3                    0x01000000U            /*!<Bit 3 */\r\n\r\n#define  TIM_CCMR1_OC2CE                     0x00008000U            /*!<Output Compare 2 Clear Enable */\r\n\r\n/*----------------------------------------------------------------------------*/\r\n\r\n#define  TIM_CCMR1_IC1PSC                    0x000CU            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\r\n#define  TIM_CCMR1_IC1PSC_0                  0x0004U            /*!<Bit 0 */\r\n#define  TIM_CCMR1_IC1PSC_1                  0x0008U            /*!<Bit 1 */\r\n\r\n#define  TIM_CCMR1_IC1F                      0x00F0U            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */\r\n#define  TIM_CCMR1_IC1F_0                    0x0010U            /*!<Bit 0 */\r\n#define  TIM_CCMR1_IC1F_1                    0x0020U            /*!<Bit 1 */\r\n#define  TIM_CCMR1_IC1F_2                    0x0040U            /*!<Bit 2 */\r\n#define  TIM_CCMR1_IC1F_3                    0x0080U            /*!<Bit 3 */\r\n\r\n#define  TIM_CCMR1_IC2PSC                    0x0C00U            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */\r\n#define  TIM_CCMR1_IC2PSC_0                  0x0400U            /*!<Bit 0 */\r\n#define  TIM_CCMR1_IC2PSC_1                  0x0800U            /*!<Bit 1 */\r\n\r\n#define  TIM_CCMR1_IC2F                      0xF000U            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */\r\n#define  TIM_CCMR1_IC2F_0                    0x1000U            /*!<Bit 0 */\r\n#define  TIM_CCMR1_IC2F_1                    0x2000U            /*!<Bit 1 */\r\n#define  TIM_CCMR1_IC2F_2                    0x4000U            /*!<Bit 2 */\r\n#define  TIM_CCMR1_IC2F_3                    0x8000U            /*!<Bit 3 */\r\n\r\n/******************  Bit definition for TIM_CCMR2 register  *******************/\r\n#define  TIM_CCMR2_CC3S                      0x00000003U        /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */\r\n#define  TIM_CCMR2_CC3S_0                    0x00000001U        /*!<Bit 0 */\r\n#define  TIM_CCMR2_CC3S_1                    0x00000002U        /*!<Bit 1 */\r\n\r\n#define  TIM_CCMR2_OC3FE                     0x00000004U        /*!<Output Compare 3 Fast enable           */\r\n#define  TIM_CCMR2_OC3PE                     0x00000008U        /*!<Output Compare 3 Preload enable        */\r\n\r\n#define  TIM_CCMR2_OC3M                      0x00010070U        /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\r\n#define  TIM_CCMR2_OC3M_0                    0x00000010U        /*!<Bit 0 */\r\n#define  TIM_CCMR2_OC3M_1                    0x00000020U        /*!<Bit 1 */\r\n#define  TIM_CCMR2_OC3M_2                    0x00000040U        /*!<Bit 2 */\r\n#define  TIM_CCMR2_OC3M_3                    0x00010000U        /*!<Bit 3 */\r\n\r\n\r\n\r\n#define  TIM_CCMR2_OC3CE                     0x00000080U        /*!<Output Compare 3 Clear Enable */\r\n\r\n#define  TIM_CCMR2_CC4S                      0x00000300U        /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\r\n#define  TIM_CCMR2_CC4S_0                    0x00000100U        /*!<Bit 0 */\r\n#define  TIM_CCMR2_CC4S_1                    0x00000200U        /*!<Bit 1 */\r\n\r\n#define  TIM_CCMR2_OC4FE                     0x00000400U        /*!<Output Compare 4 Fast enable    */\r\n#define  TIM_CCMR2_OC4PE                     0x00000800U        /*!<Output Compare 4 Preload enable */\r\n\r\n#define  TIM_CCMR2_OC4M                      0x01007000U        /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r\n#define  TIM_CCMR2_OC4M_0                    0x00001000U        /*!<Bit 0 */\r\n#define  TIM_CCMR2_OC4M_1                    0x00002000U        /*!<Bit 1 */\r\n#define  TIM_CCMR2_OC4M_2                    0x00004000U        /*!<Bit 2 */\r\n#define  TIM_CCMR2_OC4M_3                    0x01000000U        /*!<Bit 3 */\r\n\r\n#define  TIM_CCMR2_OC4CE                     0x8000U            /*!<Output Compare 4 Clear Enable */\r\n\r\n/*----------------------------------------------------------------------------*/\r\n\r\n#define  TIM_CCMR2_IC3PSC                    0x000CU            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\r\n#define  TIM_CCMR2_IC3PSC_0                  0x0004U            /*!<Bit 0 */\r\n#define  TIM_CCMR2_IC3PSC_1                  0x0008U            /*!<Bit 1 */\r\n\r\n#define  TIM_CCMR2_IC3F                      0x00F0U            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\r\n#define  TIM_CCMR2_IC3F_0                    0x0010U            /*!<Bit 0 */\r\n#define  TIM_CCMR2_IC3F_1                    0x0020U            /*!<Bit 1 */\r\n#define  TIM_CCMR2_IC3F_2                    0x0040U            /*!<Bit 2 */\r\n#define  TIM_CCMR2_IC3F_3                    0x0080U            /*!<Bit 3 */\r\n\r\n#define  TIM_CCMR2_IC4PSC                    0x0C00U            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\r\n#define  TIM_CCMR2_IC4PSC_0                  0x0400U            /*!<Bit 0 */\r\n#define  TIM_CCMR2_IC4PSC_1                  0x0800U            /*!<Bit 1 */\r\n\r\n#define  TIM_CCMR2_IC4F                      0xF000U            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\r\n#define  TIM_CCMR2_IC4F_0                    0x1000U            /*!<Bit 0 */\r\n#define  TIM_CCMR2_IC4F_1                    0x2000U            /*!<Bit 1 */\r\n#define  TIM_CCMR2_IC4F_2                    0x4000U            /*!<Bit 2 */\r\n#define  TIM_CCMR2_IC4F_3                    0x8000U            /*!<Bit 3 */\r\n\r\n/*******************  Bit definition for TIM_CCER register  *******************/\r\n#define  TIM_CCER_CC1E                       0x00000001U            /*!<Capture/Compare 1 output enable */\r\n#define  TIM_CCER_CC1P                       0x00000002U            /*!<Capture/Compare 1 output Polarity */\r\n#define  TIM_CCER_CC1NE                      0x00000004U            /*!<Capture/Compare 1 Complementary output enable */\r\n#define  TIM_CCER_CC1NP                      0x00000008U            /*!<Capture/Compare 1 Complementary output Polarity */\r\n#define  TIM_CCER_CC2E                       0x00000010U            /*!<Capture/Compare 2 output enable */\r\n#define  TIM_CCER_CC2P                       0x00000020U            /*!<Capture/Compare 2 output Polarity */\r\n#define  TIM_CCER_CC2NE                      0x00000040U            /*!<Capture/Compare 2 Complementary output enable */\r\n#define  TIM_CCER_CC2NP                      0x00000080U            /*!<Capture/Compare 2 Complementary output Polarity */\r\n#define  TIM_CCER_CC3E                       0x00000100U            /*!<Capture/Compare 3 output enable */\r\n#define  TIM_CCER_CC3P                       0x00000200U            /*!<Capture/Compare 3 output Polarity */\r\n#define  TIM_CCER_CC3NE                      0x00000400U            /*!<Capture/Compare 3 Complementary output enable */\r\n#define  TIM_CCER_CC3NP                      0x00000800U            /*!<Capture/Compare 3 Complementary output Polarity */\r\n#define  TIM_CCER_CC4E                       0x00001000U            /*!<Capture/Compare 4 output enable */\r\n#define  TIM_CCER_CC4P                       0x00002000U            /*!<Capture/Compare 4 output Polarity */\r\n#define  TIM_CCER_CC4NP                      0x00008000U            /*!<Capture/Compare 4 Complementary output Polarity */\r\n#define  TIM_CCER_CC5E                       0x00010000U            /*!<Capture/Compare 5 output enable */\r\n#define  TIM_CCER_CC5P                       0x00020000U            /*!<Capture/Compare 5 output Polarity */\r\n#define  TIM_CCER_CC6E                       0x00100000U            /*!<Capture/Compare 6 output enable */\r\n#define  TIM_CCER_CC6P                       0x00200000U            /*!<Capture/Compare 6 output Polarity */\r\n\r\n\r\n/*******************  Bit definition for TIM_CNT register  ********************/\r\n#define  TIM_CNT_CNT                         0xFFFFU            /*!<Counter Value            */\r\n\r\n/*******************  Bit definition for TIM_PSC register  ********************/\r\n#define  TIM_PSC_PSC                         0xFFFFU            /*!<Prescaler Value          */\r\n\r\n/*******************  Bit definition for TIM_ARR register  ********************/\r\n#define  TIM_ARR_ARR                         0xFFFFU            /*!<actual auto-reload Value */\r\n\r\n/*******************  Bit definition for TIM_RCR register  ********************/\r\n#define  TIM_RCR_REP                         ((uint8_t)0xFFU)               /*!<Repetition Counter Value */\r\n\r\n/*******************  Bit definition for TIM_CCR1 register  *******************/\r\n#define  TIM_CCR1_CCR1                       0xFFFFU            /*!<Capture/Compare 1 Value  */\r\n\r\n/*******************  Bit definition for TIM_CCR2 register  *******************/\r\n#define  TIM_CCR2_CCR2                       0xFFFFU            /*!<Capture/Compare 2 Value  */\r\n\r\n/*******************  Bit definition for TIM_CCR3 register  *******************/\r\n#define  TIM_CCR3_CCR3                       0xFFFFU            /*!<Capture/Compare 3 Value  */\r\n\r\n/*******************  Bit definition for TIM_CCR4 register  *******************/\r\n#define  TIM_CCR4_CCR4                       0xFFFFU            /*!<Capture/Compare 4 Value  */\r\n\r\n/*******************  Bit definition for TIM_BDTR register  *******************/\r\n#define  TIM_BDTR_DTG                        0x000000FFU            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\r\n#define  TIM_BDTR_DTG_0                      0x00000001U            /*!<Bit 0 */\r\n#define  TIM_BDTR_DTG_1                      0x00000002U            /*!<Bit 1 */\r\n#define  TIM_BDTR_DTG_2                      0x00000004U            /*!<Bit 2 */\r\n#define  TIM_BDTR_DTG_3                      0x00000008U            /*!<Bit 3 */\r\n#define  TIM_BDTR_DTG_4                      0x00000010U            /*!<Bit 4 */\r\n#define  TIM_BDTR_DTG_5                      0x00000020U            /*!<Bit 5 */\r\n#define  TIM_BDTR_DTG_6                      0x00000040U            /*!<Bit 6 */\r\n#define  TIM_BDTR_DTG_7                      0x00000080U            /*!<Bit 7 */\r\n\r\n#define  TIM_BDTR_LOCK                       0x00000300U            /*!<LOCK[1:0] bits (Lock Configuration) */\r\n#define  TIM_BDTR_LOCK_0                     0x00000100U            /*!<Bit 0 */\r\n#define  TIM_BDTR_LOCK_1                     0x00000200U            /*!<Bit 1 */\r\n\r\n#define  TIM_BDTR_OSSI                       0x00000400U            /*!<Off-State Selection for Idle mode */\r\n#define  TIM_BDTR_OSSR                       0x00000800U            /*!<Off-State Selection for Run mode  */\r\n#define  TIM_BDTR_BKE                        0x00001000U            /*!<Break enable                      */\r\n#define  TIM_BDTR_BKP                        0x00002000U            /*!<Break Polarity                    */\r\n#define  TIM_BDTR_AOE                        0x00004000U            /*!<Automatic Output enable           */\r\n#define  TIM_BDTR_MOE                        0x00008000U            /*!<Main Output enable                */\r\n#define  TIM_BDTR_BKF                        0x000F0000U            /*!<Break Filter for Break1 */\r\n#define  TIM_BDTR_BK2F                       0x00F00000U            /*!<Break Filter for Break2 */\r\n#define  TIM_BDTR_BK2E                       0x01000000U            /*!<Break enable for Break2 */\r\n#define  TIM_BDTR_BK2P                       0x02000000U            /*!<Break Polarity for Break2 */\r\n\r\n/*******************  Bit definition for TIM_DCR register  ********************/\r\n#define  TIM_DCR_DBA                         0x001FU            /*!<DBA[4:0] bits (DMA Base Address) */\r\n#define  TIM_DCR_DBA_0                       0x0001U            /*!<Bit 0 */\r\n#define  TIM_DCR_DBA_1                       0x0002U            /*!<Bit 1 */\r\n#define  TIM_DCR_DBA_2                       0x0004U            /*!<Bit 2 */\r\n#define  TIM_DCR_DBA_3                       0x0008U            /*!<Bit 3 */\r\n#define  TIM_DCR_DBA_4                       0x0010U            /*!<Bit 4 */\r\n\r\n#define  TIM_DCR_DBL                         0x1F00U            /*!<DBL[4:0] bits (DMA Burst Length) */\r\n#define  TIM_DCR_DBL_0                       0x0100U            /*!<Bit 0 */\r\n#define  TIM_DCR_DBL_1                       0x0200U            /*!<Bit 1 */\r\n#define  TIM_DCR_DBL_2                       0x0400U            /*!<Bit 2 */\r\n#define  TIM_DCR_DBL_3                       0x0800U            /*!<Bit 3 */\r\n#define  TIM_DCR_DBL_4                       0x1000U            /*!<Bit 4 */\r\n\r\n/*******************  Bit definition for TIM_DMAR register  *******************/\r\n#define  TIM_DMAR_DMAB                       0xFFFFU            /*!<DMA register for burst accesses                    */\r\n\r\n/*******************  Bit definition for TIM_OR regiter  *********************/\r\n#define TIM_OR_TI4_RMP                       0x00C0U            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */\r\n#define TIM_OR_TI4_RMP_0                     0x0040U            /*!<Bit 0 */\r\n#define TIM_OR_TI4_RMP_1                     0x0080U            /*!<Bit 1 */\r\n#define TIM_OR_ITR1_RMP                      0x0C00U            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */\r\n#define TIM_OR_ITR1_RMP_0                    0x0400U            /*!<Bit 0 */\r\n#define TIM_OR_ITR1_RMP_1                    0x0800U            /*!<Bit 1 */\r\n\r\n/******************  Bit definition for TIM_CCMR3 register  *******************/\r\n#define  TIM_CCMR3_OC5FE                     0x00000004U            /*!<Output Compare 5 Fast enable */\r\n#define  TIM_CCMR3_OC5PE                     0x00000008U            /*!<Output Compare 5 Preload enable */\r\n\r\n#define  TIM_CCMR3_OC5M                      0x00010070U            /*!<OC5M[2:0] bits (Output Compare 5 Mode) */\r\n#define  TIM_CCMR3_OC5M_0                    0x00000010U            /*!<Bit 0 */\r\n#define  TIM_CCMR3_OC5M_1                    0x00000020U            /*!<Bit 1 */\r\n#define  TIM_CCMR3_OC5M_2                    0x00000040U            /*!<Bit 2 */\r\n#define  TIM_CCMR3_OC5M_3                    0x00010000U            /*!<Bit 3 */\r\n\r\n#define  TIM_CCMR3_OC5CE                     0x00000080U            /*!<Output Compare 5 Clear Enable */\r\n\r\n#define  TIM_CCMR3_OC6FE                     0x00000400U            /*!<Output Compare 4 Fast enable */\r\n#define  TIM_CCMR3_OC6PE                     0x00000800U            /*!<Output Compare 4 Preload enable */\r\n\r\n#define  TIM_CCMR3_OC6M                      0x01007000U            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r\n#define  TIM_CCMR3_OC6M_0                    0x00001000U            /*!<Bit 0 */\r\n#define  TIM_CCMR3_OC6M_1                    0x00002000U            /*!<Bit 1 */\r\n#define  TIM_CCMR3_OC6M_2                    0x00004000U            /*!<Bit 2 */\r\n#define  TIM_CCMR3_OC6M_3                    0x01000000U            /*!<Bit 3 */\r\n\r\n#define  TIM_CCMR3_OC6CE                     0x00008000U            /*!<Output Compare 4 Clear Enable */\r\n\r\n/*******************  Bit definition for TIM_CCR5 register  *******************/\r\n#define  TIM_CCR5_CCR5                       0xFFFFFFFFU        /*!<Capture/Compare 5 Value */\r\n#define  TIM_CCR5_GC5C1                      0x20000000U        /*!<Group Channel 5 and Channel 1 */\r\n#define  TIM_CCR5_GC5C2                      0x40000000U        /*!<Group Channel 5 and Channel 2 */\r\n#define  TIM_CCR5_GC5C3                      0x80000000U        /*!<Group Channel 5 and Channel 3 */\r\n\r\n/*******************  Bit definition for TIM_CCR6 register  *******************/\r\n#define  TIM_CCR6_CCR6                       ((uint16_t)0xFFFFU)            /*!<Capture/Compare 6 Value */\r\n\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                         Low Power Timer (LPTIM)                            */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/******************  Bit definition for LPTIM_ISR register  *******************/\r\n#define  LPTIM_ISR_CMPM                         0x00000001U            /*!< Compare match                       */\r\n#define  LPTIM_ISR_ARRM                         0x00000002U            /*!< Autoreload match                    */\r\n#define  LPTIM_ISR_EXTTRIG                      0x00000004U            /*!< External trigger edge event         */\r\n#define  LPTIM_ISR_CMPOK                        0x00000008U            /*!< Compare register update OK          */\r\n#define  LPTIM_ISR_ARROK                        0x00000010U            /*!< Autoreload register update OK       */\r\n#define  LPTIM_ISR_UP                           0x00000020U            /*!< Counter direction change down to up */\r\n#define  LPTIM_ISR_DOWN                         0x00000040U            /*!< Counter direction change up to down */\r\n\r\n/******************  Bit definition for LPTIM_ICR register  *******************/\r\n#define  LPTIM_ICR_CMPMCF                       0x00000001U            /*!< Compare match Clear Flag                       */\r\n#define  LPTIM_ICR_ARRMCF                       0x00000002U            /*!< Autoreload match Clear Flag                    */\r\n#define  LPTIM_ICR_EXTTRIGCF                    0x00000004U            /*!< External trigger edge event Clear Flag         */\r\n#define  LPTIM_ICR_CMPOKCF                      0x00000008U            /*!< Compare register update OK Clear Flag          */\r\n#define  LPTIM_ICR_ARROKCF                      0x00000010U            /*!< Autoreload register update OK Clear Flag       */\r\n#define  LPTIM_ICR_UPCF                         0x00000020U            /*!< Counter direction change down to up Clear Flag */\r\n#define  LPTIM_ICR_DOWNCF                       0x00000040U            /*!< Counter direction change up to down Clear Flag */\r\n\r\n/******************  Bit definition for LPTIM_IER register *******************/\r\n#define  LPTIM_IER_CMPMIE                       0x00000001U            /*!< Compare match Interrupt Enable                       */\r\n#define  LPTIM_IER_ARRMIE                       0x00000002U            /*!< Autoreload match Interrupt Enable                    */\r\n#define  LPTIM_IER_EXTTRIGIE                    0x00000004U            /*!< External trigger edge event Interrupt Enable         */\r\n#define  LPTIM_IER_CMPOKIE                      0x00000008U            /*!< Compare register update OK Interrupt Enable          */\r\n#define  LPTIM_IER_ARROKIE                      0x00000010U            /*!< Autoreload register update OK Interrupt Enable       */\r\n#define  LPTIM_IER_UPIE                         0x00000020U            /*!< Counter direction change down to up Interrupt Enable */\r\n#define  LPTIM_IER_DOWNIE                       0x00000040U            /*!< Counter direction change up to down Interrupt Enable */\r\n\r\n/******************  Bit definition for LPTIM_CFGR register*******************/\r\n#define  LPTIM_CFGR_CKSEL                       0x00000001U             /*!< Clock selector */\r\n\r\n#define  LPTIM_CFGR_CKPOL                       0x00000006U             /*!< CKPOL[1:0] bits (Clock polarity) */\r\n#define  LPTIM_CFGR_CKPOL_0                     0x00000002U             /*!< Bit 0 */\r\n#define  LPTIM_CFGR_CKPOL_1                     0x00000004U             /*!< Bit 1 */\r\n\r\n#define  LPTIM_CFGR_CKFLT                       0x00000018U             /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */\r\n#define  LPTIM_CFGR_CKFLT_0                     0x00000008U             /*!< Bit 0 */\r\n#define  LPTIM_CFGR_CKFLT_1                     0x00000010U             /*!< Bit 1 */\r\n\r\n#define  LPTIM_CFGR_TRGFLT                      0x000000C0U             /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */\r\n#define  LPTIM_CFGR_TRGFLT_0                    0x00000040U             /*!< Bit 0 */\r\n#define  LPTIM_CFGR_TRGFLT_1                    0x00000080U             /*!< Bit 1 */\r\n\r\n#define  LPTIM_CFGR_PRESC                       0x00000E00U             /*!< PRESC[2:0] bits (Clock prescaler) */\r\n#define  LPTIM_CFGR_PRESC_0                     0x00000200U             /*!< Bit 0 */\r\n#define  LPTIM_CFGR_PRESC_1                     0x00000400U             /*!< Bit 1 */\r\n#define  LPTIM_CFGR_PRESC_2                     0x00000800U             /*!< Bit 2 */\r\n\r\n#define  LPTIM_CFGR_TRIGSEL                     0x0000E000U             /*!< TRIGSEL[2:0]] bits (Trigger selector) */\r\n#define  LPTIM_CFGR_TRIGSEL_0                   0x00002000U             /*!< Bit 0 */\r\n#define  LPTIM_CFGR_TRIGSEL_1                   0x00004000U             /*!< Bit 1 */\r\n#define  LPTIM_CFGR_TRIGSEL_2                   0x00008000U             /*!< Bit 2 */\r\n\r\n#define  LPTIM_CFGR_TRIGEN                      0x00060000U             /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */\r\n#define  LPTIM_CFGR_TRIGEN_0                    0x00020000U             /*!< Bit 0 */\r\n#define  LPTIM_CFGR_TRIGEN_1                    0x00040000U             /*!< Bit 1 */\r\n\r\n#define  LPTIM_CFGR_TIMOUT                      0x00080000U             /*!< Timout enable           */\r\n#define  LPTIM_CFGR_WAVE                        0x00100000U             /*!< Waveform shape          */\r\n#define  LPTIM_CFGR_WAVPOL                      0x00200000U             /*!< Waveform shape polarity */\r\n#define  LPTIM_CFGR_PRELOAD                     0x00400000U             /*!< Reg update mode         */\r\n#define  LPTIM_CFGR_COUNTMODE                   0x00800000U             /*!< Counter mode enable     */     \r\n#define  LPTIM_CFGR_ENC                         0x01000000U             /*!< Encoder mode enable     */          \r\n\r\n/******************  Bit definition for LPTIM_CR register  ********************/\r\n#define  LPTIM_CR_ENABLE                        0x00000001U             /*!< LPTIMer enable                 */\r\n#define  LPTIM_CR_SNGSTRT                       0x00000002U             /*!< Timer start in single mode     */\r\n#define  LPTIM_CR_CNTSTRT                       0x00000004U             /*!< Timer start in continuous mode */\r\n\r\n/******************  Bit definition for LPTIM_CMP register *******************/\r\n#define  LPTIM_CMP_CMP                          0x0000FFFFU             /*!< Compare register     */\r\n\r\n/******************  Bit definition for LPTIM_ARR register *******************/\r\n#define  LPTIM_ARR_ARR                          0x0000FFFFU             /*!< Auto reload register */\r\n\r\n/******************  Bit definition for LPTIM_CNT register *******************/\r\n#define  LPTIM_CNT_CNT                          0x0000FFFFU             /*!< Counter register     */\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/******************  Bit definition for USART_CR1 register  *******************/\r\n#define  USART_CR1_UE                        0x00000001U            /*!< USART Enable                                    */\r\n#define  USART_CR1_RE                        0x00000004U            /*!< Receiver Enable                                 */\r\n#define  USART_CR1_TE                        0x00000008U            /*!< Transmitter Enable                              */\r\n#define  USART_CR1_IDLEIE                    0x00000010U            /*!< IDLE Interrupt Enable                           */\r\n#define  USART_CR1_RXNEIE                    0x00000020U            /*!< RXNE Interrupt Enable                           */\r\n#define  USART_CR1_TCIE                      0x00000040U            /*!< Transmission Complete Interrupt Enable          */\r\n#define  USART_CR1_TXEIE                     0x00000080U            /*!< TXE Interrupt Enable                            */\r\n#define  USART_CR1_PEIE                      0x00000100U            /*!< PE Interrupt Enable                             */\r\n#define  USART_CR1_PS                        0x00000200U            /*!< Parity Selection                                */\r\n#define  USART_CR1_PCE                       0x00000400U            /*!< Parity Control Enable                           */\r\n#define  USART_CR1_WAKE                      0x00000800U            /*!< Receiver Wakeup method                          */\r\n#define  USART_CR1_M                         0x10001000U            /*!< Word length                                     */\r\n#define  USART_CR1_M_0                       0x00001000U            /*!< Word length - Bit 0                             */\r\n#define  USART_CR1_MME                       0x00002000U            /*!< Mute Mode Enable                                */\r\n#define  USART_CR1_CMIE                      0x00004000U            /*!< Character match interrupt enable                */\r\n#define  USART_CR1_OVER8                     0x00008000U            /*!< Oversampling by 8-bit or 16-bit mode            */\r\n#define  USART_CR1_DEDT                      0x001F0000U            /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */\r\n#define  USART_CR1_DEDT_0                    0x00010000U            /*!< Bit 0 */\r\n#define  USART_CR1_DEDT_1                    0x00020000U            /*!< Bit 1 */\r\n#define  USART_CR1_DEDT_2                    0x00040000U            /*!< Bit 2 */\r\n#define  USART_CR1_DEDT_3                    0x00080000U            /*!< Bit 3 */\r\n#define  USART_CR1_DEDT_4                    0x00100000U            /*!< Bit 4 */\r\n#define  USART_CR1_DEAT                      0x03E00000U            /*!< DEAT[4:0] bits (Driver Enable Assertion Time)   */\r\n#define  USART_CR1_DEAT_0                    0x00200000U            /*!< Bit 0 */\r\n#define  USART_CR1_DEAT_1                    0x00400000U            /*!< Bit 1 */\r\n#define  USART_CR1_DEAT_2                    0x00800000U            /*!< Bit 2 */\r\n#define  USART_CR1_DEAT_3                    0x01000000U            /*!< Bit 3 */\r\n#define  USART_CR1_DEAT_4                    0x02000000U            /*!< Bit 4 */\r\n#define  USART_CR1_RTOIE                     0x04000000U            /*!< Receive Time Out interrupt enable */\r\n#define  USART_CR1_EOBIE                     0x08000000U            /*!< End of Block interrupt enable     */\r\n#define  USART_CR1_M_1                       0x10000000U            /*!< Word length - Bit 1               */\r\n\r\n/******************  Bit definition for USART_CR2 register  *******************/\r\n#define  USART_CR2_ADDM7                     0x00000010U            /*!< 7-bit or 4-bit Address Detection       */\r\n#define  USART_CR2_LBDL                      0x00000020U            /*!< LIN Break Detection Length             */\r\n#define  USART_CR2_LBDIE                     0x00000040U            /*!< LIN Break Detection Interrupt Enable   */\r\n#define  USART_CR2_LBCL                      0x00000100U            /*!< Last Bit Clock pulse                   */\r\n#define  USART_CR2_CPHA                      0x00000200U            /*!< Clock Phase                            */\r\n#define  USART_CR2_CPOL                      0x00000400U            /*!< Clock Polarity                         */\r\n#define  USART_CR2_CLKEN                     0x00000800U            /*!< Clock Enable                           */\r\n#define  USART_CR2_STOP                      0x00003000U            /*!< STOP[1:0] bits (STOP bits)             */\r\n#define  USART_CR2_STOP_0                    0x00001000U            /*!< Bit 0 */\r\n#define  USART_CR2_STOP_1                    0x00002000U            /*!< Bit 1 */\r\n#define  USART_CR2_LINEN                     0x00004000U            /*!< LIN mode enable                        */\r\n#define  USART_CR2_SWAP                      0x00008000U            /*!< SWAP TX/RX pins                        */\r\n#define  USART_CR2_RXINV                     0x00010000U            /*!< RX pin active level inversion          */\r\n#define  USART_CR2_TXINV                     0x00020000U            /*!< TX pin active level inversion          */\r\n#define  USART_CR2_DATAINV                   0x00040000U            /*!< Binary data inversion                  */\r\n#define  USART_CR2_MSBFIRST                  0x00080000U            /*!< Most Significant Bit First             */\r\n#define  USART_CR2_ABREN                     0x00100000U            /*!< Auto Baud-Rate Enable                  */\r\n#define  USART_CR2_ABRMODE                   0x00600000U            /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */\r\n#define  USART_CR2_ABRMODE_0                 0x00200000U            /*!< Bit 0 */\r\n#define  USART_CR2_ABRMODE_1                 0x00400000U            /*!< Bit 1 */\r\n#define  USART_CR2_RTOEN                     0x00800000U            /*!< Receiver Time-Out enable  */\r\n#define  USART_CR2_ADD                       0xFF000000U            /*!< Address of the USART node */\r\n\r\n/******************  Bit definition for USART_CR3 register  *******************/\r\n#define  USART_CR3_EIE                       0x00000001U            /*!< Error Interrupt Enable                         */\r\n#define  USART_CR3_IREN                      0x00000002U            /*!< IrDA mode Enable                               */\r\n#define  USART_CR3_IRLP                      0x00000004U            /*!< IrDA Low-Power                                 */\r\n#define  USART_CR3_HDSEL                     0x00000008U            /*!< Half-Duplex Selection                          */\r\n#define  USART_CR3_NACK                      0x00000010U            /*!< SmartCard NACK enable                          */\r\n#define  USART_CR3_SCEN                      0x00000020U            /*!< SmartCard mode enable                          */\r\n#define  USART_CR3_DMAR                      0x00000040U            /*!< DMA Enable Receiver                            */\r\n#define  USART_CR3_DMAT                      0x00000080U            /*!< DMA Enable Transmitter                         */\r\n#define  USART_CR3_RTSE                      0x00000100U            /*!< RTS Enable                                     */\r\n#define  USART_CR3_CTSE                      0x00000200U            /*!< CTS Enable                                     */\r\n#define  USART_CR3_CTSIE                     0x00000400U            /*!< CTS Interrupt Enable                           */\r\n#define  USART_CR3_ONEBIT                    0x00000800U            /*!< One sample bit method enable                   */\r\n#define  USART_CR3_OVRDIS                    0x00001000U            /*!< Overrun Disable                                */\r\n#define  USART_CR3_DDRE                      0x00002000U            /*!< DMA Disable on Reception Error                 */\r\n#define  USART_CR3_DEM                       0x00004000U            /*!< Driver Enable Mode                             */\r\n#define  USART_CR3_DEP                       0x00008000U            /*!< Driver Enable Polarity Selection               */\r\n#define  USART_CR3_SCARCNT                   0x000E0000U            /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */\r\n#define  USART_CR3_SCARCNT_0                 0x00020000U            /*!< Bit 0 */\r\n#define  USART_CR3_SCARCNT_1                 0x00040000U            /*!< Bit 1 */\r\n#define  USART_CR3_SCARCNT_2                 0x00080000U            /*!< Bit 2 */\r\n\r\n\r\n/******************  Bit definition for USART_BRR register  *******************/\r\n#define  USART_BRR_DIV_FRACTION              0x000FU                /*!< Fraction of USARTDIV */\r\n#define  USART_BRR_DIV_MANTISSA              0xFFF0U                /*!< Mantissa of USARTDIV */\r\n\r\n/******************  Bit definition for USART_GTPR register  ******************/\r\n#define  USART_GTPR_PSC                      0x00FFU                /*!< PSC[7:0] bits (Prescaler value) */\r\n#define  USART_GTPR_GT                       0xFF00U                /*!< GT[7:0] bits (Guard time value) */\r\n\r\n\r\n/*******************  Bit definition for USART_RTOR register  *****************/\r\n#define  USART_RTOR_RTO                      0x00FFFFFFU            /*!< Receiver Time Out Value */\r\n#define  USART_RTOR_BLEN                     0xFF000000U            /*!< Block Length */\r\n\r\n/*******************  Bit definition for USART_RQR register  ******************/\r\n#define  USART_RQR_ABRRQ                     0x0001U                /*!< Auto-Baud Rate Request      */\r\n#define  USART_RQR_SBKRQ                     0x0002U                /*!< Send Break Request          */\r\n#define  USART_RQR_MMRQ                      0x0004U                /*!< Mute Mode Request           */\r\n#define  USART_RQR_RXFRQ                     0x0008U                /*!< Receive Data flush Request  */\r\n#define  USART_RQR_TXFRQ                     0x0010U                /*!< Transmit data flush Request */\r\n\r\n/*******************  Bit definition for USART_ISR register  ******************/\r\n#define  USART_ISR_PE                        0x00000001U            /*!< Parity Error                        */\r\n#define  USART_ISR_FE                        0x00000002U            /*!< Framing Error                       */\r\n#define  USART_ISR_NE                        0x00000004U            /*!< Noise detected Flag                 */\r\n#define  USART_ISR_ORE                       0x00000008U            /*!< OverRun Error                       */\r\n#define  USART_ISR_IDLE                      0x00000010U            /*!< IDLE line detected                  */\r\n#define  USART_ISR_RXNE                      0x00000020U            /*!< Read Data Register Not Empty        */\r\n#define  USART_ISR_TC                        0x00000040U            /*!< Transmission Complete               */\r\n#define  USART_ISR_TXE                       0x00000080U            /*!< Transmit Data Register Empty        */\r\n#define  USART_ISR_LBDF                      0x00000100U            /*!< LIN Break Detection Flag            */\r\n#define  USART_ISR_CTSIF                     0x00000200U            /*!< CTS interrupt flag                  */\r\n#define  USART_ISR_CTS                       0x00000400U            /*!< CTS flag                            */\r\n#define  USART_ISR_RTOF                      0x00000800U            /*!< Receiver Time Out                   */\r\n#define  USART_ISR_EOBF                      0x00001000U            /*!< End Of Block Flag                   */\r\n#define  USART_ISR_ABRE                      0x00004000U            /*!< Auto-Baud Rate Error                */\r\n#define  USART_ISR_ABRF                      0x00008000U            /*!< Auto-Baud Rate Flag                 */\r\n#define  USART_ISR_BUSY                      0x00010000U            /*!< Busy Flag                           */\r\n#define  USART_ISR_CMF                       0x00020000U            /*!< Character Match Flag                */\r\n#define  USART_ISR_SBKF                      0x00040000U            /*!< Send Break Flag                     */\r\n#define  USART_ISR_RWU                       0x00080000U            /*!< Receive Wake Up from mute mode Flag */\r\n#define  USART_ISR_WUF                       0x00100000U            /*!< Wake Up from stop mode Flag         */\r\n#define  USART_ISR_TEACK                     0x00200000U            /*!< Transmit Enable Acknowledge Flag    */\r\n#define  USART_ISR_REACK                     0x00400000U            /*!< Receive Enable Acknowledge Flag     */\r\n\r\n/* Legacy define */\r\n#define  USART_ISR_LBD                       USART_ISR_LBDF\r\n\r\n/*******************  Bit definition for USART_ICR register  ******************/\r\n#define  USART_ICR_PECF                      0x00000001U            /*!< Parity Error Clear Flag             */\r\n#define  USART_ICR_FECF                      0x00000002U            /*!< Framing Error Clear Flag            */\r\n#define  USART_ICR_NCF                       0x00000004U            /*!< Noise detected Clear Flag           */\r\n#define  USART_ICR_ORECF                     0x00000008U            /*!< OverRun Error Clear Flag            */\r\n#define  USART_ICR_IDLECF                    0x00000010U            /*!< IDLE line detected Clear Flag       */\r\n#define  USART_ICR_TCCF                      0x00000040U            /*!< Transmission Complete Clear Flag    */\r\n#define  USART_ICR_LBDCF                     0x00000100U            /*!< LIN Break Detection Clear Flag      */\r\n#define  USART_ICR_CTSCF                     0x00000200U            /*!< CTS Interrupt Clear Flag            */\r\n#define  USART_ICR_RTOCF                     0x00000800U            /*!< Receiver Time Out Clear Flag        */\r\n#define  USART_ICR_EOBCF                     0x00001000U            /*!< End Of Block Clear Flag             */\r\n#define  USART_ICR_CMCF                      0x00020000U            /*!< Character Match Clear Flag          */\r\n#define  USART_ICR_WUCF                      0x00100000U            /*!< Wake Up from stop mode Clear Flag   */\r\n\r\n/*******************  Bit definition for USART_RDR register  ******************/\r\n#define  USART_RDR_RDR                       0x01FFU                /*!< RDR[8:0] bits (Receive Data value) */\r\n\r\n/*******************  Bit definition for USART_TDR register  ******************/\r\n#define  USART_TDR_TDR                       0x01FFU                /*!< TDR[8:0] bits (Transmit Data value) */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                            Window WATCHDOG                                 */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/*******************  Bit definition for WWDG_CR register  ********************/\r\n#define  WWDG_CR_T                            0x7FU                 /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */\r\n#define  WWDG_CR_T_0                          0x01U                 /*!<Bit 0 */\r\n#define  WWDG_CR_T_1                          0x02U                 /*!<Bit 1 */\r\n#define  WWDG_CR_T_2                          0x04U                 /*!<Bit 2 */\r\n#define  WWDG_CR_T_3                          0x08U                 /*!<Bit 3 */\r\n#define  WWDG_CR_T_4                          0x10U                 /*!<Bit 4 */\r\n#define  WWDG_CR_T_5                          0x20U                 /*!<Bit 5 */\r\n#define  WWDG_CR_T_6                          0x40U                 /*!<Bit 6 */\r\n\r\n/* Legacy defines */\r\n#define  WWDG_CR_T0                           WWDG_CR_T_0                      /*!<Bit 0 */\r\n#define  WWDG_CR_T1                           WWDG_CR_T_1                      /*!<Bit 1 */\r\n#define  WWDG_CR_T2                           WWDG_CR_T_2                      /*!<Bit 2 */\r\n#define  WWDG_CR_T3                           WWDG_CR_T_3                      /*!<Bit 3 */\r\n#define  WWDG_CR_T4                           WWDG_CR_T_4                      /*!<Bit 4 */\r\n#define  WWDG_CR_T5                           WWDG_CR_T_5                      /*!<Bit 5 */\r\n#define  WWDG_CR_T6                           WWDG_CR_T_6                      /*!<Bit 6 */\r\n\r\n#define  WWDG_CR_WDGA                        0x80U                  /*!<Activation bit */\r\n\r\n/*******************  Bit definition for WWDG_CFR register  *******************/\r\n#define  WWDG_CFR_W                          0x007FU                /*!<W[6:0] bits (7-bit window value) */\r\n#define  WWDG_CFR_W_0                        0x0001U                /*!<Bit 0 */\r\n#define  WWDG_CFR_W_1                        0x0002U                /*!<Bit 1 */\r\n#define  WWDG_CFR_W_2                        0x0004U                /*!<Bit 2 */\r\n#define  WWDG_CFR_W_3                        0x0008U                /*!<Bit 3 */\r\n#define  WWDG_CFR_W_4                        0x0010U                /*!<Bit 4 */\r\n#define  WWDG_CFR_W_5                        0x0020U                /*!<Bit 5 */\r\n#define  WWDG_CFR_W_6                        0x0040U                /*!<Bit 6 */\r\n\r\n/* Legacy defines */\r\n#define  WWDG_CFR_W0                         WWDG_CFR_W_0                      /*!<Bit 0 */\r\n#define  WWDG_CFR_W1                         WWDG_CFR_W_1                      /*!<Bit 1 */\r\n#define  WWDG_CFR_W2                         WWDG_CFR_W_2                      /*!<Bit 2 */\r\n#define  WWDG_CFR_W3                         WWDG_CFR_W_3                      /*!<Bit 3 */\r\n#define  WWDG_CFR_W4                         WWDG_CFR_W_4                      /*!<Bit 4 */\r\n#define  WWDG_CFR_W5                         WWDG_CFR_W_5                      /*!<Bit 5 */\r\n#define  WWDG_CFR_W6                         WWDG_CFR_W_6                      /*!<Bit 6 */\r\n\r\n#define  WWDG_CFR_WDGTB                      0x0180U                /*!<WDGTB[1:0] bits (Timer Base) */\r\n#define  WWDG_CFR_WDGTB_0                    0x0080U                /*!<Bit 0 */\r\n#define  WWDG_CFR_WDGTB_1                    0x0100U                /*!<Bit 1 */\r\n\r\n/* Legacy defines */\r\n#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0                  /*!<Bit 0 */\r\n#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1                  /*!<Bit 1 */\r\n\r\n#define  WWDG_CFR_EWI                        0x0200U               /*!<Early Wakeup Interrupt */\r\n\r\n/*******************  Bit definition for WWDG_SR register  ********************/\r\n#define  WWDG_SR_EWIF                        0x01U                  /*!<Early Wakeup Interrupt Flag */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                DBG                                         */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bit definition for DBGMCU_IDCODE register  *************/\r\n#define  DBGMCU_IDCODE_DEV_ID                0x00000FFFU\r\n#define  DBGMCU_IDCODE_REV_ID                0xFFFF0000U\r\n\r\n/********************  Bit definition for DBGMCU_CR register  *****************/\r\n#define  DBGMCU_CR_DBG_SLEEP                 0x00000001U\r\n#define  DBGMCU_CR_DBG_STOP                  0x00000002U\r\n#define  DBGMCU_CR_DBG_STANDBY               0x00000004U\r\n#define  DBGMCU_CR_TRACE_IOEN                0x00000020U\r\n\r\n#define  DBGMCU_CR_TRACE_MODE                0x000000C0U\r\n#define  DBGMCU_CR_TRACE_MODE_0              0x00000040U /*!<Bit 0 */\r\n#define  DBGMCU_CR_TRACE_MODE_1              0x00000080U /*!<Bit 1 */\r\n\r\n/********************  Bit definition for DBGMCU_APB1_FZ register  ************/\r\n#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            0x00000001U\r\n#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            0x00000002U\r\n#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            0x00000004U\r\n#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            0x00000008U\r\n#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            0x00000010U\r\n#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            0x00000020U\r\n#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           0x00000040U\r\n#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           0x00000080U\r\n#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           0x00000100U\r\n#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             0x00000400U\r\n#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            0x00000800U\r\n#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            0x00001000U\r\n#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U\r\n#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U\r\n#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U\r\n#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            0x02000000U\r\n#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            0x04000000U\r\n\r\n/********************  Bit definition for DBGMCU_APB2_FZ register  ************/\r\n#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP            0x00000001U\r\n#define  DBGMCU_APB2_FZ_DBG_TIM8_STOP            0x00000002U\r\n#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP            0x00010000U\r\n#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP           0x00020000U\r\n#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP           0x00040000U\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                Ethernet MAC Registers bits definitions                     */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/* Bit definition for Ethernet MAC Control Register register */\r\n#define ETH_MACCR_WD              0x00800000U  /* Watchdog disable */\r\n#define ETH_MACCR_JD              0x00400000U  /* Jabber disable */\r\n#define ETH_MACCR_IFG             0x000E0000U  /* Inter-frame gap */\r\n#define ETH_MACCR_IFG_96Bit       0x00000000U  /* Minimum IFG between frames during transmission is 96Bit */\r\n#define ETH_MACCR_IFG_88Bit       0x00020000U  /* Minimum IFG between frames during transmission is 88Bit */\r\n#define ETH_MACCR_IFG_80Bit       0x00040000U  /* Minimum IFG between frames during transmission is 80Bit */\r\n#define ETH_MACCR_IFG_72Bit       0x00060000U  /* Minimum IFG between frames during transmission is 72Bit */\r\n#define ETH_MACCR_IFG_64Bit       0x00080000U  /* Minimum IFG between frames during transmission is 64Bit */        \r\n#define ETH_MACCR_IFG_56Bit       0x000A0000U  /* Minimum IFG between frames during transmission is 56Bit */\r\n#define ETH_MACCR_IFG_48Bit       0x000C0000U  /* Minimum IFG between frames during transmission is 48Bit */\r\n#define ETH_MACCR_IFG_40Bit       0x000E0000U  /* Minimum IFG between frames during transmission is 40Bit */              \r\n#define ETH_MACCR_CSD             0x00010000U  /* Carrier sense disable (during transmission) */\r\n#define ETH_MACCR_FES             0x00004000U  /* Fast ethernet speed */\r\n#define ETH_MACCR_ROD             0x00002000U  /* Receive own disable */\r\n#define ETH_MACCR_LM              0x00001000U  /* loopback mode */\r\n#define ETH_MACCR_DM              0x00000800U  /* Duplex mode */\r\n#define ETH_MACCR_IPCO            0x00000400U  /* IP Checksum offload */\r\n#define ETH_MACCR_RD              0x00000200U  /* Retry disable */\r\n#define ETH_MACCR_APCS            0x00000080U  /* Automatic Pad/CRC stripping */\r\n#define ETH_MACCR_BL              0x00000060U  /* Back-off limit: random integer number (r) of slot time delays before rescheduling\r\n                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */\r\n#define ETH_MACCR_BL_10           0x00000000U  /* k = min (n, 10) */\r\n#define ETH_MACCR_BL_8            0x00000020U  /* k = min (n, 8) */\r\n#define ETH_MACCR_BL_4            0x00000040U  /* k = min (n, 4) */\r\n#define ETH_MACCR_BL_1            0x00000060U  /* k = min (n, 1) */ \r\n#define ETH_MACCR_DC              0x00000010U  /* Defferal check */\r\n#define ETH_MACCR_TE              0x00000008U  /* Transmitter enable */\r\n#define ETH_MACCR_RE              0x00000004U  /* Receiver enable */\r\n\r\n/* Bit definition for Ethernet MAC Frame Filter Register */\r\n#define ETH_MACFFR_RA             0x80000000U  /* Receive all */ \r\n#define ETH_MACFFR_HPF            0x00000400U  /* Hash or perfect filter */ \r\n#define ETH_MACFFR_SAF            0x00000200U  /* Source address filter enable */ \r\n#define ETH_MACFFR_SAIF           0x00000100U  /* SA inverse filtering */ \r\n#define ETH_MACFFR_PCF            0x000000C0U  /* Pass control frames: 3 cases */\r\n#define ETH_MACFFR_PCF_BlockAll                0x00000040U  /* MAC filters all control frames from reaching the application */\r\n#define ETH_MACFFR_PCF_ForwardAll              0x00000080U  /* MAC forwards all control frames to application even if they fail the Address Filter */\r\n#define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U  /* MAC forwards control frames that pass the Address Filter. */ \r\n#define ETH_MACFFR_BFD             0x00000020U  /* Broadcast frame disable */ \r\n#define ETH_MACFFR_PAM             0x00000010U  /* Pass all mutlicast */ \r\n#define ETH_MACFFR_DAIF            0x00000008U  /* DA Inverse filtering */ \r\n#define ETH_MACFFR_HM              0x00000004U  /* Hash multicast */ \r\n#define ETH_MACFFR_HU              0x00000002U  /* Hash unicast */\r\n#define ETH_MACFFR_PM              0x00000001U  /* Promiscuous mode */\r\n\r\n/* Bit definition for Ethernet MAC Hash Table High Register */\r\n#define ETH_MACHTHR_HTH            0xFFFFFFFFU  /* Hash table high */\r\n\r\n/* Bit definition for Ethernet MAC Hash Table Low Register */\r\n#define ETH_MACHTLR_HTL            0xFFFFFFFFU  /* Hash table low */\r\n\r\n/* Bit definition for Ethernet MAC MII Address Register */\r\n#define ETH_MACMIIAR_PA            0x0000F800U  /* Physical layer address */ \r\n#define ETH_MACMIIAR_MR            0x000007C0U  /* MII register in the selected PHY */ \r\n#define ETH_MACMIIAR_CR            0x0000001CU  /* CR clock range: 6 cases */ \r\n#define ETH_MACMIIAR_CR_Div42      0x00000000U  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */\r\n#define ETH_MACMIIAR_CR_Div62      0x00000004U  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */\r\n#define ETH_MACMIIAR_CR_Div16      0x00000008U  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */\r\n#define ETH_MACMIIAR_CR_Div26      0x0000000CU  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */\r\n#define ETH_MACMIIAR_CR_Div102     0x00000010U  /* HCLK:150-168 MHz; MDC clock= HCLK/102 */  \r\n#define ETH_MACMIIAR_MW            0x00000002U  /* MII write */ \r\n#define ETH_MACMIIAR_MB            0x00000001U  /* MII busy */ \r\n  \r\n/* Bit definition for Ethernet MAC MII Data Register */\r\n#define ETH_MACMIIDR_MD            0x0000FFFFU  /* MII data: read/write data from/to PHY */\r\n\r\n/* Bit definition for Ethernet MAC Flow Control Register */\r\n#define ETH_MACFCR_PT              0xFFFF0000U  /* Pause time */\r\n#define ETH_MACFCR_ZQPD            0x00000080U  /* Zero-quanta pause disable */\r\n#define ETH_MACFCR_PLT             0x00000030U  /* Pause low threshold: 4 cases */\r\n#define ETH_MACFCR_PLT_Minus4      0x00000000U  /* Pause time minus 4 slot times */\r\n#define ETH_MACFCR_PLT_Minus28     0x00000010U  /* Pause time minus 28 slot times */\r\n#define ETH_MACFCR_PLT_Minus144    0x00000020U  /* Pause time minus 144 slot times */\r\n#define ETH_MACFCR_PLT_Minus256    0x00000030U  /* Pause time minus 256 slot times */      \r\n#define ETH_MACFCR_UPFD            0x00000008U  /* Unicast pause frame detect */\r\n#define ETH_MACFCR_RFCE            0x00000004U  /* Receive flow control enable */\r\n#define ETH_MACFCR_TFCE            0x00000002U  /* Transmit flow control enable */\r\n#define ETH_MACFCR_FCBBPA          0x00000001U  /* Flow control busy/backpressure activate */\r\n\r\n/* Bit definition for Ethernet MAC VLAN Tag Register */\r\n#define ETH_MACVLANTR_VLANTC       0x00010000U  /* 12-bit VLAN tag comparison */\r\n#define ETH_MACVLANTR_VLANTI       0x0000FFFFU  /* VLAN tag identifier (for receive frames) */\r\n\r\n/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ \r\n#define ETH_MACRWUFFR_D            0xFFFFFFFFU  /* Wake-up frame filter register data */\r\n/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.\r\n   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */\r\n/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask\r\n   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask\r\n   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask\r\n   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask\r\n   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - \r\n                              RSVD - Filter1 Command - RSVD - Filter0 Command\r\n   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset\r\n   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16\r\n   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */\r\n\r\n/* Bit definition for Ethernet MAC PMT Control and Status Register */ \r\n#define ETH_MACPMTCSR_WFFRPR       0x80000000U  /* Wake-Up Frame Filter Register Pointer Reset */\r\n#define ETH_MACPMTCSR_GU           0x00000200U  /* Global Unicast */\r\n#define ETH_MACPMTCSR_WFR          0x00000040U  /* Wake-Up Frame Received */\r\n#define ETH_MACPMTCSR_MPR          0x00000020U  /* Magic Packet Received */\r\n#define ETH_MACPMTCSR_WFE          0x00000004U  /* Wake-Up Frame Enable */\r\n#define ETH_MACPMTCSR_MPE          0x00000002U  /* Magic Packet Enable */\r\n#define ETH_MACPMTCSR_PD           0x00000001U  /* Power Down */\r\n\r\n/* Bit definition for Ethernet MAC Status Register */\r\n#define ETH_MACSR_TSTS      0x00000200U  /* Time stamp trigger status */\r\n#define ETH_MACSR_MMCTS     0x00000040U  /* MMC transmit status */\r\n#define ETH_MACSR_MMMCRS    0x00000020U  /* MMC receive status */\r\n#define ETH_MACSR_MMCS      0x00000010U  /* MMC status */\r\n#define ETH_MACSR_PMTS      0x00000008U  /* PMT status */\r\n\r\n/* Bit definition for Ethernet MAC Interrupt Mask Register */\r\n#define ETH_MACIMR_TSTIM     0x00000200U  /* Time stamp trigger interrupt mask */\r\n#define ETH_MACIMR_PMTIM     0x00000008U  /* PMT interrupt mask */\r\n\r\n/* Bit definition for Ethernet MAC Address0 High Register */\r\n#define ETH_MACA0HR_MACA0H   0x0000FFFFU  /* MAC address0 high */\r\n\r\n/* Bit definition for Ethernet MAC Address0 Low Register */\r\n#define ETH_MACA0LR_MACA0L   0xFFFFFFFFU  /* MAC address0 low */\r\n\r\n/* Bit definition for Ethernet MAC Address1 High Register */\r\n#define ETH_MACA1HR_AE       0x80000000U  /* Address enable */\r\n#define ETH_MACA1HR_SA       0x40000000U  /* Source address */\r\n#define ETH_MACA1HR_MBC      0x3F000000U  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */\r\n  #define ETH_MACA1HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */\r\n  #define ETH_MACA1HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */\r\n  #define ETH_MACA1HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */\r\n  #define ETH_MACA1HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */\r\n  #define ETH_MACA1HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */\r\n  #define ETH_MACA1HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [7:0] */ \r\n#define ETH_MACA1HR_MACA1H            0x0000FFFFU  /* MAC address1 high */\r\n\r\n/* Bit definition for Ethernet MAC Address1 Low Register */\r\n#define ETH_MACA1LR_MACA1L   0xFFFFFFFFU  /* MAC address1 low */\r\n\r\n/* Bit definition for Ethernet MAC Address2 High Register */\r\n#define ETH_MACA2HR_AE       0x80000000U  /* Address enable */\r\n#define ETH_MACA2HR_SA       0x40000000U  /* Source address */\r\n#define ETH_MACA2HR_MBC      0x3F000000U  /* Mask byte control */\r\n  #define ETH_MACA2HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */\r\n  #define ETH_MACA2HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */\r\n  #define ETH_MACA2HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */\r\n  #define ETH_MACA2HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */\r\n  #define ETH_MACA2HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */\r\n  #define ETH_MACA2HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */\r\n#define ETH_MACA2HR_MACA2H   0x0000FFFFU  /* MAC address1 high */\r\n\r\n/* Bit definition for Ethernet MAC Address2 Low Register */\r\n#define ETH_MACA2LR_MACA2L   0xFFFFFFFFU  /* MAC address2 low */\r\n\r\n/* Bit definition for Ethernet MAC Address3 High Register */\r\n#define ETH_MACA3HR_AE       0x80000000U  /* Address enable */\r\n#define ETH_MACA3HR_SA       0x40000000U  /* Source address */\r\n#define ETH_MACA3HR_MBC      0x3F000000U  /* Mask byte control */\r\n  #define ETH_MACA3HR_MBC_HBits15_8    0x20000000U  /* Mask MAC Address high reg bits [15:8] */\r\n  #define ETH_MACA3HR_MBC_HBits7_0     0x10000000U  /* Mask MAC Address high reg bits [7:0] */\r\n  #define ETH_MACA3HR_MBC_LBits31_24   0x08000000U  /* Mask MAC Address low reg bits [31:24] */\r\n  #define ETH_MACA3HR_MBC_LBits23_16   0x04000000U  /* Mask MAC Address low reg bits [23:16] */\r\n  #define ETH_MACA3HR_MBC_LBits15_8    0x02000000U  /* Mask MAC Address low reg bits [15:8] */\r\n  #define ETH_MACA3HR_MBC_LBits7_0     0x01000000U  /* Mask MAC Address low reg bits [70] */\r\n#define ETH_MACA3HR_MACA3H   0x0000FFFFU  /* MAC address3 high */\r\n\r\n/* Bit definition for Ethernet MAC Address3 Low Register */\r\n#define ETH_MACA3LR_MACA3L   0xFFFFFFFFU  /* MAC address3 low */\r\n\r\n/******************************************************************************/\r\n/*                Ethernet MMC Registers bits definition                      */\r\n/******************************************************************************/\r\n\r\n/* Bit definition for Ethernet MMC Contol Register */\r\n#define ETH_MMCCR_MCFHP      0x00000020U  /* MMC counter Full-Half preset */\r\n#define ETH_MMCCR_MCP        0x00000010U  /* MMC counter preset */\r\n#define ETH_MMCCR_MCF        0x00000008U  /* MMC Counter Freeze */\r\n#define ETH_MMCCR_ROR        0x00000004U  /* Reset on Read */\r\n#define ETH_MMCCR_CSR        0x00000002U  /* Counter Stop Rollover */\r\n#define ETH_MMCCR_CR         0x00000001U  /* Counters Reset */\r\n\r\n/* Bit definition for Ethernet MMC Receive Interrupt Register */\r\n#define ETH_MMCRIR_RGUFS     0x00020000U  /* Set when Rx good unicast frames counter reaches half the maximum value */\r\n#define ETH_MMCRIR_RFAES     0x00000040U  /* Set when Rx alignment error counter reaches half the maximum value */\r\n#define ETH_MMCRIR_RFCES     0x00000020U  /* Set when Rx crc error counter reaches half the maximum value */\r\n\r\n/* Bit definition for Ethernet MMC Transmit Interrupt Register */\r\n#define ETH_MMCTIR_TGFS      0x00200000U  /* Set when Tx good frame count counter reaches half the maximum value */\r\n#define ETH_MMCTIR_TGFMSCS   0x00008000U  /* Set when Tx good multi col counter reaches half the maximum value */\r\n#define ETH_MMCTIR_TGFSCS    0x00004000U  /* Set when Tx good single col counter reaches half the maximum value */\r\n\r\n/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */\r\n#define ETH_MMCRIMR_RGUFM    0x00020000U  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */\r\n#define ETH_MMCRIMR_RFAEM    0x00000040U  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */\r\n#define ETH_MMCRIMR_RFCEM    0x00000020U  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */\r\n\r\n/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */\r\n#define ETH_MMCTIMR_TGFM     0x00200000U  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */\r\n#define ETH_MMCTIMR_TGFMSCM  0x00008000U  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */\r\n#define ETH_MMCTIMR_TGFSCM   0x00004000U  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */\r\n\r\n/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */\r\n#define ETH_MMCTGFSCCR_TGFSCC     0xFFFFFFFFU  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */\r\n\r\n/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */\r\n#define ETH_MMCTGFMSCCR_TGFMSCC   0xFFFFFFFFU  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */\r\n\r\n/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */\r\n#define ETH_MMCTGFCR_TGFC    0xFFFFFFFFU  /* Number of good frames transmitted. */\r\n\r\n/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */\r\n#define ETH_MMCRFCECR_RFCEC  0xFFFFFFFFU  /* Number of frames received with CRC error. */\r\n\r\n/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */\r\n#define ETH_MMCRFAECR_RFAEC  0xFFFFFFFFU  /* Number of frames received with alignment (dribble) error */\r\n\r\n/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */\r\n#define ETH_MMCRGUFCR_RGUFC  0xFFFFFFFFU  /* Number of good unicast frames received. */\r\n\r\n/******************************************************************************/\r\n/*               Ethernet PTP Registers bits definition                       */\r\n/******************************************************************************/\r\n\r\n/* Bit definition for Ethernet PTP Time Stamp Contol Register */\r\n#define ETH_PTPTSCR_TSCNT       0x00030000U  /* Time stamp clock node type */\r\n#define ETH_PTPTSSR_TSSMRME     0x00008000U  /* Time stamp snapshot for message relevant to master enable */\r\n#define ETH_PTPTSSR_TSSEME      0x00004000U  /* Time stamp snapshot for event message enable */\r\n#define ETH_PTPTSSR_TSSIPV4FE   0x00002000U  /* Time stamp snapshot for IPv4 frames enable */\r\n#define ETH_PTPTSSR_TSSIPV6FE   0x00001000U  /* Time stamp snapshot for IPv6 frames enable */\r\n#define ETH_PTPTSSR_TSSPTPOEFE  0x00000800U  /* Time stamp snapshot for PTP over ethernet frames enable */\r\n#define ETH_PTPTSSR_TSPTPPSV2E  0x00000400U  /* Time stamp PTP packet snooping for version2 format enable */\r\n#define ETH_PTPTSSR_TSSSR       0x00000200U  /* Time stamp Sub-seconds rollover */\r\n#define ETH_PTPTSSR_TSSARFE     0x00000100U  /* Time stamp snapshot for all received frames enable */\r\n\r\n#define ETH_PTPTSCR_TSARU       0x00000020U  /* Addend register update */\r\n#define ETH_PTPTSCR_TSITE       0x00000010U  /* Time stamp interrupt trigger enable */\r\n#define ETH_PTPTSCR_TSSTU       0x00000008U  /* Time stamp update */\r\n#define ETH_PTPTSCR_TSSTI       0x00000004U  /* Time stamp initialize */\r\n#define ETH_PTPTSCR_TSFCU       0x00000002U  /* Time stamp fine or coarse update */\r\n#define ETH_PTPTSCR_TSE         0x00000001U  /* Time stamp enable */\r\n\r\n/* Bit definition for Ethernet PTP Sub-Second Increment Register */\r\n#define ETH_PTPSSIR_STSSI      0x000000FFU   /* System time Sub-second increment value */\r\n\r\n/* Bit definition for Ethernet PTP Time Stamp High Register */\r\n#define ETH_PTPTSHR_STS        0xFFFFFFFFU   /* System Time second */\r\n\r\n/* Bit definition for Ethernet PTP Time Stamp Low Register */\r\n#define ETH_PTPTSLR_STPNS      0x80000000U  /* System Time Positive or negative time */\r\n#define ETH_PTPTSLR_STSS       0x7FFFFFFFU  /* System Time sub-seconds */\r\n\r\n/* Bit definition for Ethernet PTP Time Stamp High Update Register */\r\n#define ETH_PTPTSHUR_TSUS      0xFFFFFFFFU  /* Time stamp update seconds */\r\n\r\n/* Bit definition for Ethernet PTP Time Stamp Low Update Register */\r\n#define ETH_PTPTSLUR_TSUPNS    0x80000000U  /* Time stamp update Positive or negative time */\r\n#define ETH_PTPTSLUR_TSUSS     0x7FFFFFFFU  /* Time stamp update sub-seconds */\r\n\r\n/* Bit definition for Ethernet PTP Time Stamp Addend Register */\r\n#define ETH_PTPTSAR_TSA        0xFFFFFFFFU  /* Time stamp addend */\r\n\r\n/* Bit definition for Ethernet PTP Target Time High Register */\r\n#define ETH_PTPTTHR_TTSH       0xFFFFFFFFU  /* Target time stamp high */\r\n\r\n/* Bit definition for Ethernet PTP Target Time Low Register */\r\n#define ETH_PTPTTLR_TTSL       0xFFFFFFFFU  /* Target time stamp low */\r\n\r\n/* Bit definition for Ethernet PTP Time Stamp Status Register */\r\n#define ETH_PTPTSSR_TSTTR      0x00000020U  /* Time stamp target time reached */\r\n#define ETH_PTPTSSR_TSSO       0x00000010U  /* Time stamp seconds overflow */\r\n\r\n/******************************************************************************/\r\n/*                 Ethernet DMA Registers bits definition                     */\r\n/******************************************************************************/\r\n\r\n/* Bit definition for Ethernet DMA Bus Mode Register */\r\n#define ETH_DMABMR_AAB        0x02000000U  /* Address-Aligned beats */\r\n#define ETH_DMABMR_FPM        0x01000000U  /* 4xPBL mode */\r\n#define ETH_DMABMR_USP        0x00800000U  /* Use separate PBL */\r\n#define ETH_DMABMR_RDP        0x007E0000U  /* RxDMA PBL */\r\n  #define ETH_DMABMR_RDP_1Beat    0x00020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */\r\n  #define ETH_DMABMR_RDP_2Beat    0x00040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */\r\n  #define ETH_DMABMR_RDP_4Beat    0x00080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\r\n  #define ETH_DMABMR_RDP_8Beat    0x00100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\r\n  #define ETH_DMABMR_RDP_16Beat   0x00200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\r\n  #define ETH_DMABMR_RDP_32Beat   0x00400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                \r\n  #define ETH_DMABMR_RDP_4xPBL_4Beat   0x01020000U  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\r\n  #define ETH_DMABMR_RDP_4xPBL_8Beat   0x01040000U  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\r\n  #define ETH_DMABMR_RDP_4xPBL_16Beat  0x01080000U  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\r\n  #define ETH_DMABMR_RDP_4xPBL_32Beat  0x01100000U  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */\r\n  #define ETH_DMABMR_RDP_4xPBL_64Beat  0x01200000U  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */\r\n  #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  \r\n#define ETH_DMABMR_FB        0x00010000U  /* Fixed Burst */\r\n#define ETH_DMABMR_RTPR      0x0000C000U  /* Rx Tx priority ratio */\r\n  #define ETH_DMABMR_RTPR_1_1     0x00000000U  /* Rx Tx priority ratio */\r\n  #define ETH_DMABMR_RTPR_2_1     0x00004000U  /* Rx Tx priority ratio */\r\n  #define ETH_DMABMR_RTPR_3_1     0x00008000U  /* Rx Tx priority ratio */\r\n  #define ETH_DMABMR_RTPR_4_1     0x0000C000U  /* Rx Tx priority ratio */  \r\n#define ETH_DMABMR_PBL    0x00003F00U  /* Programmable burst length */\r\n  #define ETH_DMABMR_PBL_1Beat    0x00000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */\r\n  #define ETH_DMABMR_PBL_2Beat    0x00000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */\r\n  #define ETH_DMABMR_PBL_4Beat    0x00000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r\n  #define ETH_DMABMR_PBL_8Beat    0x00000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r\n  #define ETH_DMABMR_PBL_16Beat   0x00001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r\n  #define ETH_DMABMR_PBL_32Beat   0x00002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                \r\n  #define ETH_DMABMR_PBL_4xPBL_4Beat   0x01000100U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r\n  #define ETH_DMABMR_PBL_4xPBL_8Beat   0x01000200U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r\n  #define ETH_DMABMR_PBL_4xPBL_16Beat  0x01000400U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r\n  #define ETH_DMABMR_PBL_4xPBL_32Beat  0x01000800U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\r\n  #define ETH_DMABMR_PBL_4xPBL_64Beat  0x01001000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */\r\n  #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */\r\n#define ETH_DMABMR_EDE       0x00000080U  /* Enhanced Descriptor Enable */\r\n#define ETH_DMABMR_DSL       0x0000007CU  /* Descriptor Skip Length */\r\n#define ETH_DMABMR_DA        0x00000002U  /* DMA arbitration scheme */\r\n#define ETH_DMABMR_SR        0x00000001U  /* Software reset */\r\n\r\n/* Bit definition for Ethernet DMA Transmit Poll Demand Register */\r\n#define ETH_DMATPDR_TPD      0xFFFFFFFFU  /* Transmit poll demand */\r\n\r\n/* Bit definition for Ethernet DMA Receive Poll Demand Register */\r\n#define ETH_DMARPDR_RPD      0xFFFFFFFFU  /* Receive poll demand  */\r\n\r\n/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */\r\n#define ETH_DMARDLAR_SRL     0xFFFFFFFFU  /* Start of receive list */\r\n\r\n/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */\r\n#define ETH_DMATDLAR_STL     0xFFFFFFFFU  /* Start of transmit list */\r\n\r\n/* Bit definition for Ethernet DMA Status Register */\r\n#define ETH_DMASR_TSTS       0x20000000U  /* Time-stamp trigger status */\r\n#define ETH_DMASR_PMTS       0x10000000U  /* PMT status */\r\n#define ETH_DMASR_MMCS       0x08000000U  /* MMC status */\r\n#define ETH_DMASR_EBS        0x03800000U  /* Error bits status */\r\n  /* combination with EBS[2:0] for GetFlagStatus function */\r\n  #define ETH_DMASR_EBS_DescAccess      0x02000000U  /* Error bits 0-data buffer, 1-desc. access */\r\n  #define ETH_DMASR_EBS_ReadTransf      0x01000000U  /* Error bits 0-write trnsf, 1-read transfr */\r\n  #define ETH_DMASR_EBS_DataTransfTx    0x00800000U  /* Error bits 0-Rx DMA, 1-Tx DMA */\r\n#define ETH_DMASR_TPS         0x00700000U  /* Transmit process state */\r\n  #define ETH_DMASR_TPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Tx Command issued  */\r\n  #define ETH_DMASR_TPS_Fetching        0x00100000U  /* Running - fetching the Tx descriptor */\r\n  #define ETH_DMASR_TPS_Waiting         0x00200000U  /* Running - waiting for status */\r\n  #define ETH_DMASR_TPS_Reading         0x00300000U  /* Running - reading the data from host memory */\r\n  #define ETH_DMASR_TPS_Suspended       0x00600000U  /* Suspended - Tx Descriptor unavailabe */\r\n  #define ETH_DMASR_TPS_Closing         0x00700000U  /* Running - closing Rx descriptor */\r\n#define ETH_DMASR_RPS         0x000E0000U  /* Receive process state */\r\n  #define ETH_DMASR_RPS_Stopped         0x00000000U  /* Stopped - Reset or Stop Rx Command issued */\r\n  #define ETH_DMASR_RPS_Fetching        0x00020000U  /* Running - fetching the Rx descriptor */\r\n  #define ETH_DMASR_RPS_Waiting         0x00060000U  /* Running - waiting for packet */\r\n  #define ETH_DMASR_RPS_Suspended       0x00080000U  /* Suspended - Rx Descriptor unavailable */\r\n  #define ETH_DMASR_RPS_Closing         0x000A0000U  /* Running - closing descriptor */\r\n  #define ETH_DMASR_RPS_Queuing         0x000E0000U  /* Running - queuing the recieve frame into host memory */\r\n#define ETH_DMASR_NIS        0x00010000U  /* Normal interrupt summary */\r\n#define ETH_DMASR_AIS        0x00008000U  /* Abnormal interrupt summary */\r\n#define ETH_DMASR_ERS        0x00004000U  /* Early receive status */\r\n#define ETH_DMASR_FBES       0x00002000U  /* Fatal bus error status */\r\n#define ETH_DMASR_ETS        0x00000400U  /* Early transmit status */\r\n#define ETH_DMASR_RWTS       0x00000200U  /* Receive watchdog timeout status */\r\n#define ETH_DMASR_RPSS       0x00000100U  /* Receive process stopped status */\r\n#define ETH_DMASR_RBUS       0x00000080U  /* Receive buffer unavailable status */\r\n#define ETH_DMASR_RS         0x00000040U  /* Receive status */\r\n#define ETH_DMASR_TUS        0x00000020U  /* Transmit underflow status */\r\n#define ETH_DMASR_ROS        0x00000010U  /* Receive overflow status */\r\n#define ETH_DMASR_TJTS       0x00000008U  /* Transmit jabber timeout status */\r\n#define ETH_DMASR_TBUS       0x00000004U  /* Transmit buffer unavailable status */\r\n#define ETH_DMASR_TPSS       0x00000002U  /* Transmit process stopped status */\r\n#define ETH_DMASR_TS         0x00000001U  /* Transmit status */\r\n\r\n/* Bit definition for Ethernet DMA Operation Mode Register */\r\n#define ETH_DMAOMR_DTCEFD    0x04000000U  /* Disable Dropping of TCP/IP checksum error frames */\r\n#define ETH_DMAOMR_RSF       0x02000000U  /* Receive store and forward */\r\n#define ETH_DMAOMR_DFRF      0x01000000U  /* Disable flushing of received frames */\r\n#define ETH_DMAOMR_TSF       0x00200000U  /* Transmit store and forward */\r\n#define ETH_DMAOMR_FTF       0x00100000U  /* Flush transmit FIFO */\r\n#define ETH_DMAOMR_TTC       0x0001C000U  /* Transmit threshold control */\r\n  #define ETH_DMAOMR_TTC_64Bytes       0x00000000U  /* threshold level of the MTL Transmit FIFO is 64 Bytes */\r\n  #define ETH_DMAOMR_TTC_128Bytes      0x00004000U  /* threshold level of the MTL Transmit FIFO is 128 Bytes */\r\n  #define ETH_DMAOMR_TTC_192Bytes      0x00008000U  /* threshold level of the MTL Transmit FIFO is 192 Bytes */\r\n  #define ETH_DMAOMR_TTC_256Bytes      0x0000C000U  /* threshold level of the MTL Transmit FIFO is 256 Bytes */\r\n  #define ETH_DMAOMR_TTC_40Bytes       0x00010000U  /* threshold level of the MTL Transmit FIFO is 40 Bytes */\r\n  #define ETH_DMAOMR_TTC_32Bytes       0x00014000U  /* threshold level of the MTL Transmit FIFO is 32 Bytes */\r\n  #define ETH_DMAOMR_TTC_24Bytes       0x00018000U  /* threshold level of the MTL Transmit FIFO is 24 Bytes */\r\n  #define ETH_DMAOMR_TTC_16Bytes       0x0001C000U  /* threshold level of the MTL Transmit FIFO is 16 Bytes */\r\n#define ETH_DMAOMR_ST        0x00002000U  /* Start/stop transmission command */\r\n#define ETH_DMAOMR_FEF       0x00000080U  /* Forward error frames */\r\n#define ETH_DMAOMR_FUGF      0x00000040U  /* Forward undersized good frames */\r\n#define ETH_DMAOMR_RTC       0x00000018U  /* receive threshold control */\r\n  #define ETH_DMAOMR_RTC_64Bytes       0x00000000U  /* threshold level of the MTL Receive FIFO is 64 Bytes */\r\n  #define ETH_DMAOMR_RTC_32Bytes       0x00000008U  /* threshold level of the MTL Receive FIFO is 32 Bytes */\r\n  #define ETH_DMAOMR_RTC_96Bytes       0x00000010U  /* threshold level of the MTL Receive FIFO is 96 Bytes */\r\n  #define ETH_DMAOMR_RTC_128Bytes      0x00000018U  /* threshold level of the MTL Receive FIFO is 128 Bytes */\r\n#define ETH_DMAOMR_OSF       0x00000004U  /* operate on second frame */\r\n#define ETH_DMAOMR_SR        0x00000002U  /* Start/stop receive */\r\n\r\n/* Bit definition for Ethernet DMA Interrupt Enable Register */\r\n#define ETH_DMAIER_NISE      0x00010000U  /* Normal interrupt summary enable */\r\n#define ETH_DMAIER_AISE      0x00008000U  /* Abnormal interrupt summary enable */\r\n#define ETH_DMAIER_ERIE      0x00004000U  /* Early receive interrupt enable */\r\n#define ETH_DMAIER_FBEIE     0x00002000U  /* Fatal bus error interrupt enable */\r\n#define ETH_DMAIER_ETIE      0x00000400U  /* Early transmit interrupt enable */\r\n#define ETH_DMAIER_RWTIE     0x00000200U  /* Receive watchdog timeout interrupt enable */\r\n#define ETH_DMAIER_RPSIE     0x00000100U  /* Receive process stopped interrupt enable */\r\n#define ETH_DMAIER_RBUIE     0x00000080U  /* Receive buffer unavailable interrupt enable */\r\n#define ETH_DMAIER_RIE       0x00000040U  /* Receive interrupt enable */\r\n#define ETH_DMAIER_TUIE      0x00000020U  /* Transmit Underflow interrupt enable */\r\n#define ETH_DMAIER_ROIE      0x00000010U  /* Receive Overflow interrupt enable */\r\n#define ETH_DMAIER_TJTIE     0x00000008U  /* Transmit jabber timeout interrupt enable */\r\n#define ETH_DMAIER_TBUIE     0x00000004U  /* Transmit buffer unavailable interrupt enable */\r\n#define ETH_DMAIER_TPSIE     0x00000002U  /* Transmit process stopped interrupt enable */\r\n#define ETH_DMAIER_TIE       0x00000001U  /* Transmit interrupt enable */\r\n\r\n/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */\r\n#define ETH_DMAMFBOCR_OFOC   0x10000000U  /* Overflow bit for FIFO overflow counter */\r\n#define ETH_DMAMFBOCR_MFA    0x0FFE0000U  /* Number of frames missed by the application */\r\n#define ETH_DMAMFBOCR_OMFC   0x00010000U  /* Overflow bit for missed frame counter */\r\n#define ETH_DMAMFBOCR_MFC    0x0000FFFFU  /* Number of frames missed by the controller */\r\n\r\n/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */\r\n#define ETH_DMACHTDR_HTDAP   0xFFFFFFFFU  /* Host transmit descriptor address pointer */\r\n\r\n/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */\r\n#define ETH_DMACHRDR_HRDAP   0xFFFFFFFFU  /* Host receive descriptor address pointer */\r\n\r\n/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */\r\n#define ETH_DMACHTBAR_HTBAP  0xFFFFFFFFU  /* Host transmit buffer address pointer */\r\n\r\n/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */\r\n#define ETH_DMACHRBAR_HRBAP  0xFFFFFFFFU  /* Host receive buffer address pointer */\r\n\r\n/******************************************************************************/\r\n/*                                                                            */\r\n/*                                       USB_OTG                              */\r\n/*                                                                            */\r\n/******************************************************************************/\r\n/********************  Bit definition for USB_OTG_GOTGCTL register  ********************/\r\n#define USB_OTG_GOTGCTL_SRQSCS                  0x00000001U         /*!< Session request success */\r\n#define USB_OTG_GOTGCTL_SRQ                     0x00000002U         /*!< Session request */\r\n#define USB_OTG_GOTGCTL_VBVALOEN                0x00000004U         /*!< VBUS valid override enable */\r\n#define USB_OTG_GOTGCTL_VBVALOVAL               0x00000008U         /*!< VBUS valid override value */\r\n#define USB_OTG_GOTGCTL_AVALOEN                 0x00000010U         /*!< A-peripheral session valid override enable */\r\n#define USB_OTG_GOTGCTL_AVALOVAL                0x00000020U         /*!< A-peripheral session valid override value */\r\n#define USB_OTG_GOTGCTL_BVALOEN                 0x00000040U         /*!< B-peripheral session valid override enable */\r\n#define USB_OTG_GOTGCTL_BVALOVAL                0x00000080U         /*!< B-peripheral session valid override value  */\r\n#define USB_OTG_GOTGCTL_HNGSCS                  0x00000100U         /*!< Host set HNP enable */\r\n#define USB_OTG_GOTGCTL_HNPRQ                   0x00000200U         /*!< HNP request */\r\n#define USB_OTG_GOTGCTL_HSHNPEN                 0x00000400U         /*!< Host set HNP enable */\r\n#define USB_OTG_GOTGCTL_DHNPEN                  0x00000800U         /*!< Device HNP enabled */\r\n#define USB_OTG_GOTGCTL_EHEN                    0x00001000U         /*!< Embedded host enable */\r\n#define USB_OTG_GOTGCTL_CIDSTS                  0x00010000U         /*!< Connector ID status */\r\n#define USB_OTG_GOTGCTL_DBCT                    0x00020000U         /*!< Long/short debounce time */\r\n#define USB_OTG_GOTGCTL_ASVLD                   0x00040000U         /*!< A-session valid  */\r\n#define USB_OTG_GOTGCTL_BSESVLD                 0x00080000U         /*!< B-session valid */\r\n#define USB_OTG_GOTGCTL_OTGVER                  0x00100000U         /*!< OTG version  */\r\n\r\n/********************  Bit definition for USB_OTG_HCFG register  ********************/\r\n#define USB_OTG_HCFG_FSLSPCS                 0x00000003U            /*!< FS/LS PHY clock select  */\r\n#define USB_OTG_HCFG_FSLSPCS_0               0x00000001U            /*!<Bit 0 */\r\n#define USB_OTG_HCFG_FSLSPCS_1               0x00000002U            /*!<Bit 1 */\r\n#define USB_OTG_HCFG_FSLSS                   0x00000004U            /*!< FS- and LS-only support */\r\n\r\n/********************  Bit definition for USB_OTG_DCFG register  ********************/\r\n#define USB_OTG_DCFG_DSPD                    0x00000003U            /*!< Device speed */\r\n#define USB_OTG_DCFG_DSPD_0                  0x00000001U            /*!<Bit 0 */\r\n#define USB_OTG_DCFG_DSPD_1                  0x00000002U            /*!<Bit 1 */\r\n#define USB_OTG_DCFG_NZLSOHSK                0x00000004U            /*!< Nonzero-length status OUT handshake */\r\n\r\n#define USB_OTG_DCFG_DAD                     0x000007F0U            /*!< Device address */\r\n#define USB_OTG_DCFG_DAD_0                   0x00000010U            /*!<Bit 0 */\r\n#define USB_OTG_DCFG_DAD_1                   0x00000020U            /*!<Bit 1 */\r\n#define USB_OTG_DCFG_DAD_2                   0x00000040U            /*!<Bit 2 */\r\n#define USB_OTG_DCFG_DAD_3                   0x00000080U            /*!<Bit 3 */\r\n#define USB_OTG_DCFG_DAD_4                   0x00000100U            /*!<Bit 4 */\r\n#define USB_OTG_DCFG_DAD_5                   0x00000200U            /*!<Bit 5 */\r\n#define USB_OTG_DCFG_DAD_6                   0x00000400U            /*!<Bit 6 */\r\n\r\n#define USB_OTG_DCFG_PFIVL                   0x00001800U            /*!< Periodic (micro)frame interval */\r\n#define USB_OTG_DCFG_PFIVL_0                 0x00000800U            /*!<Bit 0 */\r\n#define USB_OTG_DCFG_PFIVL_1                 0x00001000U            /*!<Bit 1 */\r\n\r\n#define USB_OTG_DCFG_PERSCHIVL               0x03000000U            /*!< Periodic scheduling interval */\r\n#define USB_OTG_DCFG_PERSCHIVL_0             0x01000000U            /*!<Bit 0 */\r\n#define USB_OTG_DCFG_PERSCHIVL_1             0x02000000U            /*!<Bit 1 */\r\n\r\n/********************  Bit definition for USB_OTG_PCGCR register  ********************/\r\n#define USB_OTG_PCGCR_STPPCLK                 0x00000001U            /*!< Stop PHY clock */\r\n#define USB_OTG_PCGCR_GATEHCLK                0x00000002U            /*!< Gate HCLK */\r\n#define USB_OTG_PCGCR_PHYSUSP                 0x00000010U            /*!< PHY suspended */\r\n\r\n/********************  Bit definition for USB_OTG_GOTGINT register  ********************/\r\n#define USB_OTG_GOTGINT_SEDET                   0x00000004U            /*!< Session end detected                   */\r\n#define USB_OTG_GOTGINT_SRSSCHG                 0x00000100U            /*!< Session request success status change  */\r\n#define USB_OTG_GOTGINT_HNSSCHG                 0x00000200U            /*!< Host negotiation success status change */\r\n#define USB_OTG_GOTGINT_HNGDET                  0x00020000U            /*!< Host negotiation detected              */\r\n#define USB_OTG_GOTGINT_ADTOCHG                 0x00040000U            /*!< A-device timeout change                */\r\n#define USB_OTG_GOTGINT_DBCDNE                  0x00080000U            /*!< Debounce done                          */\r\n#define USB_OTG_GOTGINT_IDCHNG                  0x00100000U            /*!< Change in ID pin input value           */\r\n\r\n/********************  Bit definition for USB_OTG_DCTL register  ********************/\r\n#define USB_OTG_DCTL_RWUSIG                  0x00000001U            /*!< Remote wakeup signaling */\r\n#define USB_OTG_DCTL_SDIS                    0x00000002U            /*!< Soft disconnect         */\r\n#define USB_OTG_DCTL_GINSTS                  0x00000004U            /*!< Global IN NAK status    */\r\n#define USB_OTG_DCTL_GONSTS                  0x00000008U            /*!< Global OUT NAK status   */\r\n\r\n#define USB_OTG_DCTL_TCTL                    0x00000070U            /*!< Test control */\r\n#define USB_OTG_DCTL_TCTL_0                  0x00000010U            /*!<Bit 0 */\r\n#define USB_OTG_DCTL_TCTL_1                  0x00000020U            /*!<Bit 1 */\r\n#define USB_OTG_DCTL_TCTL_2                  0x00000040U            /*!<Bit 2 */\r\n#define USB_OTG_DCTL_SGINAK                  0x00000080U            /*!< Set global IN NAK         */\r\n#define USB_OTG_DCTL_CGINAK                  0x00000100U            /*!< Clear global IN NAK       */\r\n#define USB_OTG_DCTL_SGONAK                  0x00000200U            /*!< Set global OUT NAK        */\r\n#define USB_OTG_DCTL_CGONAK                  0x00000400U            /*!< Clear global OUT NAK      */\r\n#define USB_OTG_DCTL_POPRGDNE                0x00000800U            /*!< Power-on programming done */\r\n\r\n/********************  Bit definition for USB_OTG_HFIR register  ********************/\r\n#define USB_OTG_HFIR_FRIVL                   0x0000FFFFU            /*!< Frame interval */\r\n\r\n/********************  Bit definition for USB_OTG_HFNUM register  ********************/\r\n#define USB_OTG_HFNUM_FRNUM                   0x0000FFFFU            /*!< Frame number         */\r\n#define USB_OTG_HFNUM_FTREM                   0xFFFF0000U            /*!< Frame time remaining */\r\n\r\n/********************  Bit definition for USB_OTG_DSTS register  ********************/\r\n#define USB_OTG_DSTS_SUSPSTS                 0x00000001U            /*!< Suspend status   */\r\n\r\n#define USB_OTG_DSTS_ENUMSPD                 0x00000006U            /*!< Enumerated speed */\r\n#define USB_OTG_DSTS_ENUMSPD_0               0x00000002U            /*!<Bit 0 */\r\n#define USB_OTG_DSTS_ENUMSPD_1               0x00000004U            /*!<Bit 1 */\r\n#define USB_OTG_DSTS_EERR                    0x00000008U            /*!< Erratic error     */\r\n#define USB_OTG_DSTS_FNSOF                   0x003FFF00U            /*!< Frame number of the received SOF */\r\n\r\n/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/\r\n#define USB_OTG_GAHBCFG_GINT                    0x00000001U            /*!< Global interrupt mask */\r\n#define USB_OTG_GAHBCFG_HBSTLEN                 0x0000001EU            /*!< Burst length/type */\r\n#define USB_OTG_GAHBCFG_HBSTLEN_0               0x00000002U            /*!<Bit 0 */\r\n#define USB_OTG_GAHBCFG_HBSTLEN_1               0x00000004U            /*!<Bit 1 */\r\n#define USB_OTG_GAHBCFG_HBSTLEN_2               0x00000008U            /*!<Bit 2 */\r\n#define USB_OTG_GAHBCFG_HBSTLEN_3               0x00000010U            /*!<Bit 3 */\r\n#define USB_OTG_GAHBCFG_DMAEN                   0x00000020U            /*!< DMA enable */\r\n#define USB_OTG_GAHBCFG_TXFELVL                 0x00000080U            /*!< TxFIFO empty level */\r\n#define USB_OTG_GAHBCFG_PTXFELVL                0x00000100U            /*!< Periodic TxFIFO empty level */\r\n\r\n/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/\r\n#define USB_OTG_GUSBCFG_TOCAL                   0x00000007U            /*!< FS timeout calibration */\r\n#define USB_OTG_GUSBCFG_TOCAL_0                 0x00000001U            /*!<Bit 0 */\r\n#define USB_OTG_GUSBCFG_TOCAL_1                 0x00000002U            /*!<Bit 1 */\r\n#define USB_OTG_GUSBCFG_TOCAL_2                 0x00000004U            /*!<Bit 2 */\r\n#define USB_OTG_GUSBCFG_PHYSEL                  0x00000040U            /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */\r\n#define USB_OTG_GUSBCFG_SRPCAP                  0x00000100U            /*!< SRP-capable */\r\n#define USB_OTG_GUSBCFG_HNPCAP                  0x00000200U            /*!< HNP-capable */\r\n#define USB_OTG_GUSBCFG_TRDT                    0x00003C00U            /*!< USB turnaround time */\r\n#define USB_OTG_GUSBCFG_TRDT_0                  0x00000400U            /*!<Bit 0 */\r\n#define USB_OTG_GUSBCFG_TRDT_1                  0x00000800U            /*!<Bit 1 */\r\n#define USB_OTG_GUSBCFG_TRDT_2                  0x00001000U            /*!<Bit 2 */\r\n#define USB_OTG_GUSBCFG_TRDT_3                  0x00002000U            /*!<Bit 3 */\r\n#define USB_OTG_GUSBCFG_PHYLPCS                 0x00008000U            /*!< PHY Low-power clock select */\r\n#define USB_OTG_GUSBCFG_ULPIFSLS                0x00020000U            /*!< ULPI FS/LS select               */\r\n#define USB_OTG_GUSBCFG_ULPIAR                  0x00040000U            /*!< ULPI Auto-resume                */\r\n#define USB_OTG_GUSBCFG_ULPICSM                 0x00080000U            /*!< ULPI Clock SuspendM             */\r\n#define USB_OTG_GUSBCFG_ULPIEVBUSD              0x00100000U            /*!< ULPI External VBUS Drive        */\r\n#define USB_OTG_GUSBCFG_ULPIEVBUSI              0x00200000U            /*!< ULPI external VBUS indicator    */\r\n#define USB_OTG_GUSBCFG_TSDPS                   0x00400000U            /*!< TermSel DLine pulsing selection */\r\n#define USB_OTG_GUSBCFG_PCCI                    0x00800000U            /*!< Indicator complement            */\r\n#define USB_OTG_GUSBCFG_PTCI                    0x01000000U            /*!< Indicator pass through          */\r\n#define USB_OTG_GUSBCFG_ULPIIPD                 0x02000000U            /*!< ULPI interface protect disable  */\r\n#define USB_OTG_GUSBCFG_FHMOD                   0x20000000U            /*!< Forced host mode                */\r\n#define USB_OTG_GUSBCFG_FDMOD                   0x40000000U            /*!< Forced peripheral mode          */\r\n#define USB_OTG_GUSBCFG_CTXPKT                  0x80000000U            /*!< Corrupt Tx packet               */\r\n\r\n/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/\r\n#define USB_OTG_GRSTCTL_CSRST                   0x00000001U            /*!< Core soft reset          */\r\n#define USB_OTG_GRSTCTL_HSRST                   0x00000002U            /*!< HCLK soft reset          */\r\n#define USB_OTG_GRSTCTL_FCRST                   0x00000004U            /*!< Host frame counter reset */\r\n#define USB_OTG_GRSTCTL_RXFFLSH                 0x00000010U            /*!< RxFIFO flush             */\r\n#define USB_OTG_GRSTCTL_TXFFLSH                 0x00000020U            /*!< TxFIFO flush             */\r\n#define USB_OTG_GRSTCTL_TXFNUM                  0x000007C0U            /*!< TxFIFO number */\r\n#define USB_OTG_GRSTCTL_TXFNUM_0                0x00000040U            /*!<Bit 0 */\r\n#define USB_OTG_GRSTCTL_TXFNUM_1                0x00000080U            /*!<Bit 1 */\r\n#define USB_OTG_GRSTCTL_TXFNUM_2                0x00000100U            /*!<Bit 2 */\r\n#define USB_OTG_GRSTCTL_TXFNUM_3                0x00000200U            /*!<Bit 3 */\r\n#define USB_OTG_GRSTCTL_TXFNUM_4                0x00000400U            /*!<Bit 4 */\r\n#define USB_OTG_GRSTCTL_DMAREQ                  0x40000000U            /*!< DMA request signal */\r\n#define USB_OTG_GRSTCTL_AHBIDL                  0x80000000U            /*!< AHB master idle */\r\n\r\n/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/\r\n#define USB_OTG_DIEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask                 */\r\n#define USB_OTG_DIEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask                  */\r\n#define USB_OTG_DIEPMSK_TOM                     0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */\r\n#define USB_OTG_DIEPMSK_ITTXFEMSK               0x00000010U            /*!< IN token received when TxFIFO empty mask          */\r\n#define USB_OTG_DIEPMSK_INEPNMM                 0x00000020U            /*!< IN token received with EP mismatch mask           */\r\n#define USB_OTG_DIEPMSK_INEPNEM                 0x00000040U            /*!< IN endpoint NAK effective mask                    */\r\n#define USB_OTG_DIEPMSK_TXFURM                  0x00000100U            /*!< FIFO underrun mask                                */\r\n#define USB_OTG_DIEPMSK_BIM                     0x00000200U            /*!< BNA interrupt mask                                */\r\n\r\n/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/\r\n#define USB_OTG_HPTXSTS_PTXFSAVL                0x0000FFFFU            /*!< Periodic transmit data FIFO space available     */\r\n#define USB_OTG_HPTXSTS_PTXQSAV                 0x00FF0000U            /*!< Periodic transmit request queue space available */\r\n#define USB_OTG_HPTXSTS_PTXQSAV_0               0x00010000U            /*!<Bit 0 */\r\n#define USB_OTG_HPTXSTS_PTXQSAV_1               0x00020000U            /*!<Bit 1 */\r\n#define USB_OTG_HPTXSTS_PTXQSAV_2               0x00040000U            /*!<Bit 2 */\r\n#define USB_OTG_HPTXSTS_PTXQSAV_3               0x00080000U            /*!<Bit 3 */\r\n#define USB_OTG_HPTXSTS_PTXQSAV_4               0x00100000U            /*!<Bit 4 */\r\n#define USB_OTG_HPTXSTS_PTXQSAV_5               0x00200000U            /*!<Bit 5 */\r\n#define USB_OTG_HPTXSTS_PTXQSAV_6               0x00400000U            /*!<Bit 6 */\r\n#define USB_OTG_HPTXSTS_PTXQSAV_7               0x00800000U            /*!<Bit 7 */\r\n\r\n#define USB_OTG_HPTXSTS_PTXQTOP                 0xFF000000U            /*!< Top of the periodic transmit request queue */\r\n#define USB_OTG_HPTXSTS_PTXQTOP_0               0x01000000U            /*!<Bit 0 */\r\n#define USB_OTG_HPTXSTS_PTXQTOP_1               0x02000000U            /*!<Bit 1 */\r\n#define USB_OTG_HPTXSTS_PTXQTOP_2               0x04000000U            /*!<Bit 2 */\r\n#define USB_OTG_HPTXSTS_PTXQTOP_3               0x08000000U            /*!<Bit 3 */\r\n#define USB_OTG_HPTXSTS_PTXQTOP_4               0x10000000U            /*!<Bit 4 */\r\n#define USB_OTG_HPTXSTS_PTXQTOP_5               0x20000000U            /*!<Bit 5 */\r\n#define USB_OTG_HPTXSTS_PTXQTOP_6               0x40000000U            /*!<Bit 6 */\r\n#define USB_OTG_HPTXSTS_PTXQTOP_7               0x80000000U            /*!<Bit 7 */\r\n\r\n/********************  Bit definition for USB_OTG_HAINT register  ********************/\r\n#define USB_OTG_HAINT_HAINT                     0x0000FFFFU            /*!< Channel interrupts */\r\n\r\n/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/\r\n#define USB_OTG_DOEPMSK_XFRCM                   0x00000001U            /*!< Transfer completed interrupt mask */\r\n#define USB_OTG_DOEPMSK_EPDM                    0x00000002U            /*!< Endpoint disabled interrupt mask               */\r\n#define USB_OTG_DOEPMSK_STUPM                   0x00000008U            /*!< SETUP phase done mask                          */\r\n#define USB_OTG_DOEPMSK_OTEPDM                  0x00000010U            /*!< OUT token received when endpoint disabled mask */\r\n#define USB_OTG_DOEPMSK_OTEPSPRM                0x00000020U            /*!< Status Phase Received mask                     */\r\n#define USB_OTG_DOEPMSK_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received mask       */\r\n#define USB_OTG_DOEPMSK_OPEM                    0x00000100U            /*!< OUT packet error mask                          */\r\n#define USB_OTG_DOEPMSK_BOIM                    0x00000200U            /*!< BNA interrupt mask                             */\r\n\r\n/********************  Bit definition for USB_OTG_GINTSTS register  ********************/\r\n#define USB_OTG_GINTSTS_CMOD                    0x00000001U            /*!< Current mode of operation                      */\r\n#define USB_OTG_GINTSTS_MMIS                    0x00000002U            /*!< Mode mismatch interrupt                        */\r\n#define USB_OTG_GINTSTS_OTGINT                  0x00000004U            /*!< OTG interrupt                                  */\r\n#define USB_OTG_GINTSTS_SOF                     0x00000008U            /*!< Start of frame                                 */\r\n#define USB_OTG_GINTSTS_RXFLVL                  0x00000010U            /*!< RxFIFO nonempty                                */\r\n#define USB_OTG_GINTSTS_NPTXFE                  0x00000020U            /*!< Nonperiodic TxFIFO empty                       */\r\n#define USB_OTG_GINTSTS_GINAKEFF                0x00000040U            /*!< Global IN nonperiodic NAK effective            */\r\n#define USB_OTG_GINTSTS_BOUTNAKEFF              0x00000080U            /*!< Global OUT NAK effective                       */\r\n#define USB_OTG_GINTSTS_ESUSP                   0x00000400U            /*!< Early suspend                                  */\r\n#define USB_OTG_GINTSTS_USBSUSP                 0x00000800U            /*!< USB suspend                                    */\r\n#define USB_OTG_GINTSTS_USBRST                  0x00001000U            /*!< USB reset                                      */\r\n#define USB_OTG_GINTSTS_ENUMDNE                 0x00002000U            /*!< Enumeration done                               */\r\n#define USB_OTG_GINTSTS_ISOODRP                 0x00004000U            /*!< Isochronous OUT packet dropped interrupt       */\r\n#define USB_OTG_GINTSTS_EOPF                    0x00008000U            /*!< End of periodic frame interrupt                */\r\n#define USB_OTG_GINTSTS_IEPINT                  0x00040000U            /*!< IN endpoint interrupt                          */\r\n#define USB_OTG_GINTSTS_OEPINT                  0x00080000U            /*!< OUT endpoint interrupt                         */\r\n#define USB_OTG_GINTSTS_IISOIXFR                0x00100000U            /*!< Incomplete isochronous IN transfer             */\r\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       0x00200000U            /*!< Incomplete periodic transfer                   */\r\n#define USB_OTG_GINTSTS_DATAFSUSP               0x00400000U            /*!< Data fetch suspended                           */\r\n#define USB_OTG_GINTSTS_RSTDET                  0x00800000U            /*!< Reset detected interrupt                       */\r\n#define USB_OTG_GINTSTS_HPRTINT                 0x01000000U            /*!< Host port interrupt                            */\r\n#define USB_OTG_GINTSTS_HCINT                   0x02000000U            /*!< Host channels interrupt                        */\r\n#define USB_OTG_GINTSTS_PTXFE                   0x04000000U            /*!< Periodic TxFIFO empty                          */\r\n#define USB_OTG_GINTSTS_LPMINT                  0x08000000U            /*!< LPM interrupt                                  */\r\n#define USB_OTG_GINTSTS_CIDSCHG                 0x10000000U            /*!< Connector ID status change                     */\r\n#define USB_OTG_GINTSTS_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt                  */\r\n#define USB_OTG_GINTSTS_SRQINT                  0x40000000U            /*!< Session request/new session detected interrupt */\r\n#define USB_OTG_GINTSTS_WKUINT                  0x80000000U            /*!< Resume/remote wakeup detected interrupt        */\r\n\r\n/********************  Bit definition for USB_OTG_GINTMSK register  ********************/\r\n#define USB_OTG_GINTMSK_MMISM                   0x00000002U            /*!< Mode mismatch interrupt mask                        */\r\n#define USB_OTG_GINTMSK_OTGINT                  0x00000004U            /*!< OTG interrupt mask                                  */\r\n#define USB_OTG_GINTMSK_SOFM                    0x00000008U            /*!< Start of frame mask                                 */\r\n#define USB_OTG_GINTMSK_RXFLVLM                 0x00000010U            /*!< Receive FIFO nonempty mask                          */\r\n#define USB_OTG_GINTMSK_NPTXFEM                 0x00000020U            /*!< Nonperiodic TxFIFO empty mask                       */\r\n#define USB_OTG_GINTMSK_GINAKEFFM               0x00000040U            /*!< Global nonperiodic IN NAK effective mask            */\r\n#define USB_OTG_GINTMSK_GONAKEFFM               0x00000080U            /*!< Global OUT NAK effective mask                       */\r\n#define USB_OTG_GINTMSK_ESUSPM                  0x00000400U            /*!< Early suspend mask                                  */\r\n#define USB_OTG_GINTMSK_USBSUSPM                0x00000800U            /*!< USB suspend mask                                    */\r\n#define USB_OTG_GINTMSK_USBRST                  0x00001000U            /*!< USB reset mask                                      */\r\n#define USB_OTG_GINTMSK_ENUMDNEM                0x00002000U            /*!< Enumeration done mask                               */\r\n#define USB_OTG_GINTMSK_ISOODRPM                0x00004000U            /*!< Isochronous OUT packet dropped interrupt mask       */\r\n#define USB_OTG_GINTMSK_EOPFM                   0x00008000U            /*!< End of periodic frame interrupt mask                */\r\n#define USB_OTG_GINTMSK_EPMISM                  0x00020000U            /*!< Endpoint mismatch interrupt mask                    */\r\n#define USB_OTG_GINTMSK_IEPINT                  0x00040000U            /*!< IN endpoints interrupt mask                         */\r\n#define USB_OTG_GINTMSK_OEPINT                  0x00080000U            /*!< OUT endpoints interrupt mask                        */\r\n#define USB_OTG_GINTMSK_IISOIXFRM               0x00100000U            /*!< Incomplete isochronous IN transfer mask             */\r\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         0x00200000U            /*!< Incomplete periodic transfer mask                   */\r\n#define USB_OTG_GINTMSK_FSUSPM                  0x00400000U            /*!< Data fetch suspended mask                           */\r\n#define USB_OTG_GINTMSK_RSTDEM                  0x00800000U            /*!< Reset detected interrupt mask                       */\r\n#define USB_OTG_GINTMSK_PRTIM                   0x01000000U            /*!< Host port interrupt mask                            */\r\n#define USB_OTG_GINTMSK_HCIM                    0x02000000U            /*!< Host channels interrupt mask                        */\r\n#define USB_OTG_GINTMSK_PTXFEM                  0x04000000U            /*!< Periodic TxFIFO empty mask                          */\r\n#define USB_OTG_GINTMSK_LPMINTM                 0x08000000U            /*!< LPM interrupt Mask                                  */\r\n#define USB_OTG_GINTMSK_CIDSCHGM                0x10000000U            /*!< Connector ID status change mask                     */\r\n#define USB_OTG_GINTMSK_DISCINT                 0x20000000U            /*!< Disconnect detected interrupt mask                  */\r\n#define USB_OTG_GINTMSK_SRQIM                   0x40000000U            /*!< Session request/new session detected interrupt mask */\r\n#define USB_OTG_GINTMSK_WUIM                    0x80000000U            /*!< Resume/remote wakeup detected interrupt mask        */\r\n\r\n/********************  Bit definition for USB_OTG_DAINT register  ********************/\r\n#define USB_OTG_DAINT_IEPINT                  0x0000FFFFU            /*!< IN endpoint interrupt bits  */\r\n#define USB_OTG_DAINT_OEPINT                  0xFFFF0000U            /*!< OUT endpoint interrupt bits */\r\n\r\n/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/\r\n#define USB_OTG_HAINTMSK_HAINTM                  0x0000FFFFU            /*!< Channel interrupt mask */\r\n\r\n/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/\r\n#define USB_OTG_GRXSTSP_EPNUM                    0x0000000FU            /*!< IN EP interrupt mask bits  */\r\n#define USB_OTG_GRXSTSP_BCNT                     0x00007FF0U            /*!< OUT EP interrupt mask bits */\r\n#define USB_OTG_GRXSTSP_DPID                     0x00018000U            /*!< OUT EP interrupt mask bits */\r\n#define USB_OTG_GRXSTSP_PKTSTS                   0x001E0000U            /*!< OUT EP interrupt mask bits */\r\n\r\n/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/\r\n#define USB_OTG_DAINTMSK_IEPM                    0x0000FFFFU            /*!< IN EP interrupt mask bits */\r\n#define USB_OTG_DAINTMSK_OEPM                    0xFFFF0000U            /*!< OUT EP interrupt mask bits */\r\n\r\n/********************  Bit definition for OTG register  ********************/\r\n\r\n#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */\r\n#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */\r\n#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */\r\n#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */\r\n#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */\r\n#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */\r\n\r\n#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */\r\n#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */\r\n#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */\r\n\r\n#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */\r\n#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */\r\n#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */\r\n#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */\r\n#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */\r\n\r\n#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */\r\n#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */\r\n#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */\r\n#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */\r\n#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */\r\n\r\n#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */\r\n#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */\r\n#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */\r\n#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */\r\n#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */\r\n\r\n/********************  Bit definition for OTG register  ********************/\r\n\r\n#define USB_OTG_CHNUM                   0x0000000FU            /*!< Channel number */\r\n#define USB_OTG_CHNUM_0                 0x00000001U            /*!<Bit 0 */\r\n#define USB_OTG_CHNUM_1                 0x00000002U            /*!<Bit 1 */\r\n#define USB_OTG_CHNUM_2                 0x00000004U            /*!<Bit 2 */\r\n#define USB_OTG_CHNUM_3                 0x00000008U            /*!<Bit 3 */\r\n#define USB_OTG_BCNT                    0x00007FF0U            /*!< Byte count */\r\n\r\n#define USB_OTG_DPID                    0x00018000U            /*!< Data PID */\r\n#define USB_OTG_DPID_0                  0x00008000U            /*!<Bit 0 */\r\n#define USB_OTG_DPID_1                  0x00010000U            /*!<Bit 1 */\r\n\r\n#define USB_OTG_PKTSTS                  0x001E0000U            /*!< Packet status */\r\n#define USB_OTG_PKTSTS_0                0x00020000U            /*!<Bit 0 */\r\n#define USB_OTG_PKTSTS_1                0x00040000U            /*!<Bit 1 */\r\n#define USB_OTG_PKTSTS_2                0x00080000U            /*!<Bit 2 */\r\n#define USB_OTG_PKTSTS_3                0x00100000U            /*!<Bit 3 */\r\n\r\n#define USB_OTG_EPNUM                   0x0000000FU            /*!< Endpoint number */\r\n#define USB_OTG_EPNUM_0                 0x00000001U            /*!<Bit 0 */\r\n#define USB_OTG_EPNUM_1                 0x00000002U            /*!<Bit 1 */\r\n#define USB_OTG_EPNUM_2                 0x00000004U            /*!<Bit 2 */\r\n#define USB_OTG_EPNUM_3                 0x00000008U            /*!<Bit 3 */\r\n\r\n#define USB_OTG_FRMNUM                  0x01E00000U            /*!< Frame number */\r\n#define USB_OTG_FRMNUM_0                0x00200000U            /*!<Bit 0 */\r\n#define USB_OTG_FRMNUM_1                0x00400000U            /*!<Bit 1 */\r\n#define USB_OTG_FRMNUM_2                0x00800000U            /*!<Bit 2 */\r\n#define USB_OTG_FRMNUM_3                0x01000000U            /*!<Bit 3 */\r\n\r\n/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/\r\n#define USB_OTG_GRXFSIZ_RXFD            0x0000FFFFU            /*!< RxFIFO depth */\r\n\r\n/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/\r\n#define USB_OTG_DVBUSDIS_VBUSDT         0x0000FFFFU            /*!< Device VBUS discharge time */\r\n\r\n/********************  Bit definition for OTG register  ********************/\r\n#define USB_OTG_NPTXFSA                 0x0000FFFFU            /*!< Nonperiodic transmit RAM start address */\r\n#define USB_OTG_NPTXFD                  0xFFFF0000U            /*!< Nonperiodic TxFIFO depth               */\r\n#define USB_OTG_TX0FSA                  0x0000FFFFU            /*!< Endpoint 0 transmit RAM start address  */\r\n#define USB_OTG_TX0FD                   0xFFFF0000U            /*!< Endpoint 0 TxFIFO depth                */\r\n\r\n/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/\r\n#define USB_OTG_DVBUSPULSE_DVBUSP                0x00000FFFU            /*!< Device VBUS pulsing time */\r\n\r\n/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/\r\n#define USB_OTG_GNPTXSTS_NPTXFSAV                0x0000FFFFU            /*!< Nonperiodic TxFIFO space available */\r\n\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV                0x00FF0000U            /*!< Nonperiodic transmit request queue space available */\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_0              0x00010000U            /*!<Bit 0 */\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_1              0x00020000U            /*!<Bit 1 */\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_2              0x00040000U            /*!<Bit 2 */\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_3              0x00080000U            /*!<Bit 3 */\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_4              0x00100000U            /*!<Bit 4 */\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_5              0x00200000U            /*!<Bit 5 */\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_6              0x00400000U            /*!<Bit 6 */\r\n#define USB_OTG_GNPTXSTS_NPTQXSAV_7              0x00800000U            /*!<Bit 7 */\r\n\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP                0x7F000000U            /*!< Top of the nonperiodic transmit request queue */\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP_0              0x01000000U            /*!<Bit 0 */\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP_1              0x02000000U            /*!<Bit 1 */\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP_2              0x04000000U            /*!<Bit 2 */\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP_3              0x08000000U            /*!<Bit 3 */\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP_4              0x10000000U            /*!<Bit 4 */\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP_5              0x20000000U            /*!<Bit 5 */\r\n#define USB_OTG_GNPTXSTS_NPTXQTOP_6              0x40000000U            /*!<Bit 6 */\r\n\r\n/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/\r\n#define USB_OTG_DTHRCTL_NONISOTHREN             0x00000001U            /*!< Nonisochronous IN endpoints threshold enable */\r\n#define USB_OTG_DTHRCTL_ISOTHREN                0x00000002U            /*!< ISO IN endpoint threshold enable */\r\n\r\n#define USB_OTG_DTHRCTL_TXTHRLEN                0x000007FCU            /*!< Transmit threshold length */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_0              0x00000004U            /*!<Bit 0 */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_1              0x00000008U            /*!<Bit 1 */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_2              0x00000010U            /*!<Bit 2 */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_3              0x00000020U            /*!<Bit 3 */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_4              0x00000040U            /*!<Bit 4 */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_5              0x00000080U            /*!<Bit 5 */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_6              0x00000100U            /*!<Bit 6 */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_7              0x00000200U            /*!<Bit 7 */\r\n#define USB_OTG_DTHRCTL_TXTHRLEN_8              0x00000400U            /*!<Bit 8 */\r\n#define USB_OTG_DTHRCTL_RXTHREN                 0x00010000U            /*!< Receive threshold enable */\r\n\r\n#define USB_OTG_DTHRCTL_RXTHRLEN                0x03FE0000U            /*!< Receive threshold length */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_0              0x00020000U            /*!<Bit 0 */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_1              0x00040000U            /*!<Bit 1 */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_2              0x00080000U            /*!<Bit 2 */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_3              0x00100000U            /*!<Bit 3 */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_4              0x00200000U            /*!<Bit 4 */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_5              0x00400000U            /*!<Bit 5 */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_6              0x00800000U            /*!<Bit 6 */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_7              0x01000000U            /*!<Bit 7 */\r\n#define USB_OTG_DTHRCTL_RXTHRLEN_8              0x02000000U            /*!<Bit 8 */\r\n#define USB_OTG_DTHRCTL_ARPEN                   0x08000000U            /*!< Arbiter parking enable */\r\n\r\n/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/\r\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM            0x0000FFFFU         /*!< IN EP Tx FIFO empty interrupt mask bits */\r\n\r\n/********************  Bit definition for USB_OTG_DEACHINT register  ********************/\r\n#define USB_OTG_DEACHINT_IEP1INT                0x00000002U           /*!< IN endpoint 1interrupt bit   */\r\n#define USB_OTG_DEACHINT_OEP1INT                0x00020000U           /*!< OUT endpoint 1 interrupt bit */\r\n\r\n/********************  Bit definition for USB_OTG_GCCFG register  ********************/\r\n#define USB_OTG_GCCFG_PWRDWN                 0x00010000U              /*!< Power down */\r\n#define USB_OTG_GCCFG_VBDEN                  0x00200000U              /*!< USB VBUS Detection Enable */\r\n\r\n/********************  Bit definition for USB_OTG_GPWRDN) register  ********************/\r\n#define USB_OTG_GPWRDN_ADPMEN                 0x00000001U             /*!< ADP module enable */\r\n#define USB_OTG_GPWRDN_ADPIF                  0x00800000U             /*!< ADP Interrupt flag */\r\n\r\n/********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/\r\n#define USB_OTG_DEACHINTMSK_IEP1INTM          0x00000002U            /*!< IN Endpoint 1 interrupt mask bit  */\r\n#define USB_OTG_DEACHINTMSK_OEP1INTM          0x00020000U            /*!< OUT Endpoint 1 interrupt mask bit */\r\n \r\n/********************  Bit definition for USB_OTG_CID register  ********************/\r\n#define USB_OTG_CID_PRODUCT_ID               0xFFFFFFFFU            /*!< Product ID field */\r\n\r\n/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/\r\n#define  USB_OTG_GLPMCFG_LPMEN               0x00000001U            /*!< LPM support enable                                     */\r\n#define  USB_OTG_GLPMCFG_LPMACK              0x00000002U            /*!< LPM Token acknowledge enable                           */\r\n#define  USB_OTG_GLPMCFG_BESL                0x0000003CU            /*!< BESL value received with last ACKed LPM Token          */\r\n#define  USB_OTG_GLPMCFG_REMWAKE             0x00000040U            /*!< bRemoteWake value received with last ACKed LPM Token   */\r\n#define  USB_OTG_GLPMCFG_L1SSEN              0x00000080U            /*!< L1 shallow sleep enable                                */\r\n#define  USB_OTG_GLPMCFG_BESLTHRS            0x00000F00U            /*!< BESL threshold                                         */\r\n#define  USB_OTG_GLPMCFG_L1DSEN              0x00001000U            /*!< L1 deep sleep enable                                   */\r\n#define  USB_OTG_GLPMCFG_LPMRSP              0x00006000U            /*!< LPM response                                           */\r\n#define  USB_OTG_GLPMCFG_SLPSTS              0x00008000U            /*!< Port sleep status                                      */\r\n#define  USB_OTG_GLPMCFG_L1RSMOK             0x00010000U            /*!< Sleep State Resume OK                                  */\r\n#define  USB_OTG_GLPMCFG_LPMCHIDX            0x001E0000U            /*!< LPM Channel Index                                      */\r\n#define  USB_OTG_GLPMCFG_LPMRCNT             0x00E00000U            /*!< LPM retry count                                        */\r\n#define  USB_OTG_GLPMCFG_SNDLPM              0x01000000U            /*!< Send LPM transaction                                   */\r\n#define  USB_OTG_GLPMCFG_LPMRCNTSTS          0x0E000000U            /*!< LPM retry count status                                 */\r\n#define  USB_OTG_GLPMCFG_ENBESL              0x10000000U            /*!< Enable best effort service latency                     */\r\n\r\n/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/\r\n#define USB_OTG_DIEPEACHMSK1_XFRCM           0x00000001U            /*!< Transfer completed interrupt mask                 */\r\n#define USB_OTG_DIEPEACHMSK1_EPDM            0x00000002U            /*!< Endpoint disabled interrupt mask                  */\r\n#define USB_OTG_DIEPEACHMSK1_TOM             0x00000008U            /*!< Timeout condition mask (nonisochronous endpoints) */\r\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK       0x00000010U            /*!< IN token received when TxFIFO empty mask          */\r\n#define USB_OTG_DIEPEACHMSK1_INEPNMM         0x00000020U            /*!< IN token received with EP mismatch mask           */\r\n#define USB_OTG_DIEPEACHMSK1_INEPNEM         0x00000040U            /*!< IN endpoint NAK effective mask                    */\r\n#define USB_OTG_DIEPEACHMSK1_TXFURM          0x00000100U            /*!< FIFO underrun mask                                */\r\n#define USB_OTG_DIEPEACHMSK1_BIM             0x00000200U            /*!< BNA interrupt mask                                */\r\n#define USB_OTG_DIEPEACHMSK1_NAKM            0x00002000U            /*!< NAK interrupt mask                                */\r\n\r\n/********************  Bit definition for USB_OTG_HPRT register  ********************/\r\n#define USB_OTG_HPRT_PCSTS                   0x00000001U            /*!< Port connect status        */\r\n#define USB_OTG_HPRT_PCDET                   0x00000002U            /*!< Port connect detected      */\r\n#define USB_OTG_HPRT_PENA                    0x00000004U            /*!< Port enable                */\r\n#define USB_OTG_HPRT_PENCHNG                 0x00000008U            /*!< Port enable/disable change */\r\n#define USB_OTG_HPRT_POCA                    0x00000010U            /*!< Port overcurrent active    */\r\n#define USB_OTG_HPRT_POCCHNG                 0x00000020U            /*!< Port overcurrent change    */\r\n#define USB_OTG_HPRT_PRES                    0x00000040U            /*!< Port resume                */\r\n#define USB_OTG_HPRT_PSUSP                   0x00000080U            /*!< Port suspend               */\r\n#define USB_OTG_HPRT_PRST                    0x00000100U            /*!< Port reset                 */\r\n\r\n#define USB_OTG_HPRT_PLSTS                   0x00000C00U            /*!< Port line status           */\r\n#define USB_OTG_HPRT_PLSTS_0                 0x00000400U            /*!<Bit 0 */\r\n#define USB_OTG_HPRT_PLSTS_1                 0x00000800U            /*!<Bit 1 */\r\n#define USB_OTG_HPRT_PPWR                    0x00001000U            /*!< Port power                 */\r\n\r\n#define USB_OTG_HPRT_PTCTL                   0x0001E000U            /*!< Port test control          */\r\n#define USB_OTG_HPRT_PTCTL_0                 0x00002000U            /*!<Bit 0 */\r\n#define USB_OTG_HPRT_PTCTL_1                 0x00004000U            /*!<Bit 1 */\r\n#define USB_OTG_HPRT_PTCTL_2                 0x00008000U            /*!<Bit 2 */\r\n#define USB_OTG_HPRT_PTCTL_3                 0x00010000U            /*!<Bit 3 */\r\n\r\n#define USB_OTG_HPRT_PSPD                    0x00060000U            /*!< Port speed                 */\r\n#define USB_OTG_HPRT_PSPD_0                  0x00020000U            /*!<Bit 0 */\r\n#define USB_OTG_HPRT_PSPD_1                  0x00040000U            /*!<Bit 1 */\r\n\r\n/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/\r\n#define USB_OTG_DOEPEACHMSK1_XFRCM               0x00000001U            /*!< Transfer completed interrupt mask         */\r\n#define USB_OTG_DOEPEACHMSK1_EPDM                0x00000002U            /*!< Endpoint disabled interrupt mask          */\r\n#define USB_OTG_DOEPEACHMSK1_TOM                 0x00000008U            /*!< Timeout condition mask                    */\r\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           0x00000010U            /*!< IN token received when TxFIFO empty mask  */\r\n#define USB_OTG_DOEPEACHMSK1_INEPNMM             0x00000020U            /*!< IN token received with EP mismatch mask   */\r\n#define USB_OTG_DOEPEACHMSK1_INEPNEM             0x00000040U            /*!< IN endpoint NAK effective mask            */\r\n#define USB_OTG_DOEPEACHMSK1_TXFURM              0x00000100U            /*!< OUT packet error mask                     */\r\n#define USB_OTG_DOEPEACHMSK1_BIM                 0x00000200U            /*!< BNA interrupt mask                        */\r\n#define USB_OTG_DOEPEACHMSK1_BERRM               0x00001000U            /*!< Bubble error interrupt mask               */\r\n#define USB_OTG_DOEPEACHMSK1_NAKM                0x00002000U            /*!< NAK interrupt mask                        */\r\n#define USB_OTG_DOEPEACHMSK1_NYETM               0x00004000U            /*!< NYET interrupt mask                       */\r\n\r\n/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/\r\n#define USB_OTG_HPTXFSIZ_PTXSA                   0x0000FFFFU            /*!< Host periodic TxFIFO start address            */\r\n#define USB_OTG_HPTXFSIZ_PTXFD                   0xFFFF0000U            /*!< Host periodic TxFIFO depth                    */\r\n\r\n/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/\r\n#define USB_OTG_DIEPCTL_MPSIZ                   0x000007FFU            /*!< Maximum packet size              */\r\n#define USB_OTG_DIEPCTL_USBAEP                  0x00008000U            /*!< USB active endpoint              */\r\n#define USB_OTG_DIEPCTL_EONUM_DPID              0x00010000U            /*!< Even/odd frame                   */\r\n#define USB_OTG_DIEPCTL_NAKSTS                  0x00020000U            /*!< NAK status                       */\r\n\r\n#define USB_OTG_DIEPCTL_EPTYP                   0x000C0000U            /*!< Endpoint type                    */\r\n#define USB_OTG_DIEPCTL_EPTYP_0                 0x00040000U            /*!<Bit 0 */\r\n#define USB_OTG_DIEPCTL_EPTYP_1                 0x00080000U            /*!<Bit 1 */\r\n#define USB_OTG_DIEPCTL_STALL                   0x00200000U            /*!< STALL handshake                  */\r\n\r\n#define USB_OTG_DIEPCTL_TXFNUM                  0x03C00000U            /*!< TxFIFO number                    */\r\n#define USB_OTG_DIEPCTL_TXFNUM_0                0x00400000U            /*!<Bit 0 */\r\n#define USB_OTG_DIEPCTL_TXFNUM_1                0x00800000U            /*!<Bit 1 */\r\n#define USB_OTG_DIEPCTL_TXFNUM_2                0x01000000U            /*!<Bit 2 */\r\n#define USB_OTG_DIEPCTL_TXFNUM_3                0x02000000U            /*!<Bit 3 */\r\n#define USB_OTG_DIEPCTL_CNAK                    0x04000000U            /*!< Clear NAK                        */\r\n#define USB_OTG_DIEPCTL_SNAK                    0x08000000U            /*!< Set NAK */\r\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          0x10000000U            /*!< Set DATA0 PID                    */\r\n#define USB_OTG_DIEPCTL_SODDFRM                 0x20000000U            /*!< Set odd frame                    */\r\n#define USB_OTG_DIEPCTL_EPDIS                   0x40000000U            /*!< Endpoint disable                 */\r\n#define USB_OTG_DIEPCTL_EPENA                   0x80000000U            /*!< Endpoint enable                  */\r\n\r\n/********************  Bit definition for USB_OTG_HCCHAR register  ********************/\r\n#define USB_OTG_HCCHAR_MPSIZ                   0x000007FFU            /*!< Maximum packet size */\r\n\r\n#define USB_OTG_HCCHAR_EPNUM                   0x00007800U            /*!< Endpoint number */\r\n#define USB_OTG_HCCHAR_EPNUM_0                 0x00000800U            /*!<Bit 0 */\r\n#define USB_OTG_HCCHAR_EPNUM_1                 0x00001000U            /*!<Bit 1 */\r\n#define USB_OTG_HCCHAR_EPNUM_2                 0x00002000U            /*!<Bit 2 */\r\n#define USB_OTG_HCCHAR_EPNUM_3                 0x00004000U            /*!<Bit 3 */\r\n#define USB_OTG_HCCHAR_EPDIR                   0x00008000U            /*!< Endpoint direction */\r\n#define USB_OTG_HCCHAR_LSDEV                   0x00020000U            /*!< Low-speed device */\r\n\r\n#define USB_OTG_HCCHAR_EPTYP                   0x000C0000U            /*!< Endpoint type */\r\n#define USB_OTG_HCCHAR_EPTYP_0                 0x00040000U            /*!<Bit 0 */\r\n#define USB_OTG_HCCHAR_EPTYP_1                 0x00080000U            /*!<Bit 1 */\r\n\r\n#define USB_OTG_HCCHAR_MC                      0x00300000U            /*!< Multi Count (MC) / Error Count (EC) */\r\n#define USB_OTG_HCCHAR_MC_0                    0x00100000U            /*!<Bit 0 */\r\n#define USB_OTG_HCCHAR_MC_1                    0x00200000U            /*!<Bit 1 */\r\n\r\n#define USB_OTG_HCCHAR_DAD                     0x1FC00000U            /*!< Device address */\r\n#define USB_OTG_HCCHAR_DAD_0                   0x00400000U            /*!<Bit 0 */\r\n#define USB_OTG_HCCHAR_DAD_1                   0x00800000U            /*!<Bit 1 */\r\n#define USB_OTG_HCCHAR_DAD_2                   0x01000000U            /*!<Bit 2 */\r\n#define USB_OTG_HCCHAR_DAD_3                   0x02000000U            /*!<Bit 3 */\r\n#define USB_OTG_HCCHAR_DAD_4                   0x04000000U            /*!<Bit 4 */\r\n#define USB_OTG_HCCHAR_DAD_5                   0x08000000U            /*!<Bit 5 */\r\n#define USB_OTG_HCCHAR_DAD_6                   0x10000000U            /*!<Bit 6 */\r\n#define USB_OTG_HCCHAR_ODDFRM                  0x20000000U            /*!< Odd frame */\r\n#define USB_OTG_HCCHAR_CHDIS                   0x40000000U            /*!< Channel disable */\r\n#define USB_OTG_HCCHAR_CHENA                   0x80000000U            /*!< Channel enable */\r\n\r\n/********************  Bit definition for USB_OTG_HCSPLT register  ********************/\r\n\r\n#define USB_OTG_HCSPLT_PRTADDR                 0x0000007FU            /*!< Port address */\r\n#define USB_OTG_HCSPLT_PRTADDR_0               0x00000001U            /*!<Bit 0 */\r\n#define USB_OTG_HCSPLT_PRTADDR_1               0x00000002U            /*!<Bit 1 */\r\n#define USB_OTG_HCSPLT_PRTADDR_2               0x00000004U            /*!<Bit 2 */\r\n#define USB_OTG_HCSPLT_PRTADDR_3               0x00000008U            /*!<Bit 3 */\r\n#define USB_OTG_HCSPLT_PRTADDR_4               0x00000010U            /*!<Bit 4 */\r\n#define USB_OTG_HCSPLT_PRTADDR_5               0x00000020U            /*!<Bit 5 */\r\n#define USB_OTG_HCSPLT_PRTADDR_6               0x00000040U            /*!<Bit 6 */\r\n\r\n#define USB_OTG_HCSPLT_HUBADDR                 0x00003F80U            /*!< Hub address */\r\n#define USB_OTG_HCSPLT_HUBADDR_0               0x00000080U            /*!<Bit 0 */\r\n#define USB_OTG_HCSPLT_HUBADDR_1               0x00000100U            /*!<Bit 1 */\r\n#define USB_OTG_HCSPLT_HUBADDR_2               0x00000200U            /*!<Bit 2 */\r\n#define USB_OTG_HCSPLT_HUBADDR_3               0x00000400U            /*!<Bit 3 */\r\n#define USB_OTG_HCSPLT_HUBADDR_4               0x00000800U            /*!<Bit 4 */\r\n#define USB_OTG_HCSPLT_HUBADDR_5               0x00001000U            /*!<Bit 5 */\r\n#define USB_OTG_HCSPLT_HUBADDR_6               0x00002000U            /*!<Bit 6 */\r\n\r\n#define USB_OTG_HCSPLT_XACTPOS                 0x0000C000U            /*!< XACTPOS */\r\n#define USB_OTG_HCSPLT_XACTPOS_0               0x00004000U            /*!<Bit 0 */\r\n#define USB_OTG_HCSPLT_XACTPOS_1               0x00008000U            /*!<Bit 1 */\r\n#define USB_OTG_HCSPLT_COMPLSPLT               0x00010000U            /*!< Do complete split */\r\n#define USB_OTG_HCSPLT_SPLITEN                 0x80000000U            /*!< Split enable */\r\n\r\n/********************  Bit definition for USB_OTG_HCINT register  ********************/\r\n#define USB_OTG_HCINT_XFRC                    0x00000001U            /*!< Transfer completed */\r\n#define USB_OTG_HCINT_CHH                     0x00000002U            /*!< Channel halted */\r\n#define USB_OTG_HCINT_AHBERR                  0x00000004U            /*!< AHB error */\r\n#define USB_OTG_HCINT_STALL                   0x00000008U            /*!< STALL response received interrupt */\r\n#define USB_OTG_HCINT_NAK                     0x00000010U            /*!< NAK response received interrupt */\r\n#define USB_OTG_HCINT_ACK                     0x00000020U            /*!< ACK response received/transmitted interrupt */\r\n#define USB_OTG_HCINT_NYET                    0x00000040U            /*!< Response received interrupt */\r\n#define USB_OTG_HCINT_TXERR                   0x00000080U            /*!< Transaction error */\r\n#define USB_OTG_HCINT_BBERR                   0x00000100U            /*!< Babble error */\r\n#define USB_OTG_HCINT_FRMOR                   0x00000200U            /*!< Frame overrun */\r\n#define USB_OTG_HCINT_DTERR                   0x00000400U            /*!< Data toggle error */\r\n\r\n/********************  Bit definition for USB_OTG_DIEPINT register  ********************/\r\n#define USB_OTG_DIEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */\r\n#define USB_OTG_DIEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */\r\n#define USB_OTG_DIEPINT_TOC                     0x00000008U            /*!< Timeout condition */\r\n#define USB_OTG_DIEPINT_ITTXFE                  0x00000010U            /*!< IN token received when TxFIFO is empty */\r\n#define USB_OTG_DIEPINT_INEPNE                  0x00000040U            /*!< IN endpoint NAK effective */\r\n#define USB_OTG_DIEPINT_TXFE                    0x00000080U            /*!< Transmit FIFO empty */\r\n#define USB_OTG_DIEPINT_TXFIFOUDRN              0x00000100U            /*!< Transmit Fifo Underrun */\r\n#define USB_OTG_DIEPINT_BNA                     0x00000200U            /*!< Buffer not available interrupt */\r\n#define USB_OTG_DIEPINT_PKTDRPSTS               0x00000800U            /*!< Packet dropped status */\r\n#define USB_OTG_DIEPINT_BERR                    0x00001000U            /*!< Babble error interrupt */\r\n#define USB_OTG_DIEPINT_NAK                     0x00002000U            /*!< NAK interrupt */\r\n\r\n/********************  Bit definition for USB_OTG_HCINTMSK register  ********************/\r\n#define USB_OTG_HCINTMSK_XFRCM                   0x00000001U            /*!< Transfer completed mask */\r\n#define USB_OTG_HCINTMSK_CHHM                    0x00000002U            /*!< Channel halted mask */\r\n#define USB_OTG_HCINTMSK_AHBERR                  0x00000004U            /*!< AHB error */\r\n#define USB_OTG_HCINTMSK_STALLM                  0x00000008U            /*!< STALL response received interrupt mask */\r\n#define USB_OTG_HCINTMSK_NAKM                    0x00000010U            /*!< NAK response received interrupt mask */\r\n#define USB_OTG_HCINTMSK_ACKM                    0x00000020U            /*!< ACK response received/transmitted interrupt mask */\r\n#define USB_OTG_HCINTMSK_NYET                    0x00000040U            /*!< response received interrupt mask */\r\n#define USB_OTG_HCINTMSK_TXERRM                  0x00000080U            /*!< Transaction error mask */\r\n#define USB_OTG_HCINTMSK_BBERRM                  0x00000100U            /*!< Babble error mask */\r\n#define USB_OTG_HCINTMSK_FRMORM                  0x00000200U            /*!< Frame overrun mask */\r\n#define USB_OTG_HCINTMSK_DTERRM                  0x00000400U            /*!< Data toggle error mask */\r\n\r\n/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/\r\n\r\n#define USB_OTG_DIEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */\r\n#define USB_OTG_DIEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */\r\n#define USB_OTG_DIEPTSIZ_MULCNT                  0x60000000U            /*!< Packet count */\r\n/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/\r\n#define USB_OTG_HCTSIZ_XFRSIZ                    0x0007FFFFU            /*!< Transfer size */\r\n#define USB_OTG_HCTSIZ_PKTCNT                    0x1FF80000U            /*!< Packet count */\r\n#define USB_OTG_HCTSIZ_DOPING                    0x80000000U            /*!< Do PING */\r\n#define USB_OTG_HCTSIZ_DPID                      0x60000000U            /*!< Data PID */\r\n#define USB_OTG_HCTSIZ_DPID_0                    0x20000000U            /*!<Bit 0 */\r\n#define USB_OTG_HCTSIZ_DPID_1                    0x40000000U            /*!<Bit 1 */\r\n\r\n/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/\r\n#define USB_OTG_DIEPDMA_DMAADDR                  0xFFFFFFFFU            /*!< DMA address */\r\n\r\n/********************  Bit definition for USB_OTG_HCDMA register  ********************/\r\n#define USB_OTG_HCDMA_DMAADDR                    0xFFFFFFFFU            /*!< DMA address */\r\n\r\n/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/\r\n#define USB_OTG_DTXFSTS_INEPTFSAV                0x0000FFFFU            /*!< IN endpoint TxFIFO space available */\r\n\r\n/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/\r\n#define USB_OTG_DIEPTXF_INEPTXSA                 0x0000FFFFU            /*!< IN endpoint FIFOx transmit RAM start address */\r\n#define USB_OTG_DIEPTXF_INEPTXFD                 0xFFFF0000U            /*!< IN endpoint TxFIFO depth */\r\n\r\n/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/\r\n#define USB_OTG_DOEPCTL_MPSIZ                     0x000007FFU            /*!< Maximum packet size */          /*!<Bit 1 */\r\n#define USB_OTG_DOEPCTL_USBAEP                    0x00008000U            /*!< USB active endpoint */\r\n#define USB_OTG_DOEPCTL_NAKSTS                    0x00020000U            /*!< NAK status */\r\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM            0x10000000U            /*!< Set DATA0 PID */\r\n#define USB_OTG_DOEPCTL_SODDFRM                   0x20000000U            /*!< Set odd frame */\r\n#define USB_OTG_DOEPCTL_EPTYP                     0x000C0000U            /*!< Endpoint type */\r\n#define USB_OTG_DOEPCTL_EPTYP_0                   0x00040000U            /*!<Bit 0 */\r\n#define USB_OTG_DOEPCTL_EPTYP_1                   0x00080000U            /*!<Bit 1 */\r\n#define USB_OTG_DOEPCTL_SNPM                      0x00100000U            /*!< Snoop mode */\r\n#define USB_OTG_DOEPCTL_STALL                     0x00200000U            /*!< STALL handshake */\r\n#define USB_OTG_DOEPCTL_CNAK                      0x04000000U            /*!< Clear NAK */\r\n#define USB_OTG_DOEPCTL_SNAK                      0x08000000U            /*!< Set NAK */\r\n#define USB_OTG_DOEPCTL_EPDIS                     0x40000000U            /*!< Endpoint disable */\r\n#define USB_OTG_DOEPCTL_EPENA                     0x80000000U            /*!< Endpoint enable */\r\n\r\n/********************  Bit definition for USB_OTG_DOEPINT register  ********************/\r\n#define USB_OTG_DOEPINT_XFRC                    0x00000001U            /*!< Transfer completed interrupt */\r\n#define USB_OTG_DOEPINT_EPDISD                  0x00000002U            /*!< Endpoint disabled interrupt */\r\n#define USB_OTG_DOEPINT_STUP                    0x00000008U            /*!< SETUP phase done */\r\n#define USB_OTG_DOEPINT_OTEPDIS                 0x00000010U            /*!< OUT token received when endpoint disabled */\r\n#define USB_OTG_DOEPINT_OTEPSPR                 0x00000020U            /*!< Status Phase Received For Control Write */\r\n#define USB_OTG_DOEPINT_B2BSTUP                 0x00000040U            /*!< Back-to-back SETUP packets received */\r\n#define USB_OTG_DOEPINT_NYET                    0x00004000U            /*!< NYET interrupt */\r\n\r\n/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/\r\n#define USB_OTG_DOEPTSIZ_XFRSIZ                  0x0007FFFFU            /*!< Transfer size */\r\n#define USB_OTG_DOEPTSIZ_PKTCNT                  0x1FF80000U            /*!< Packet count */\r\n\r\n#define USB_OTG_DOEPTSIZ_STUPCNT                 0x60000000U            /*!< SETUP packet count */\r\n#define USB_OTG_DOEPTSIZ_STUPCNT_0               0x20000000U            /*!<Bit 0 */\r\n#define USB_OTG_DOEPTSIZ_STUPCNT_1               0x40000000U            /*!<Bit 1 */\r\n\r\n/********************  Bit definition for PCGCCTL register  ********************/\r\n#define USB_OTG_PCGCCTL_STOPCLK                 0x00000001U            /*!< SETUP packet count */\r\n#define USB_OTG_PCGCCTL_GATECLK                 0x00000002U            /*!<Bit 0 */\r\n#define USB_OTG_PCGCCTL_PHYSUSP                 0x00000010U            /*!<Bit 1 */\r\n\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup Exported_macros\r\n  * @{\r\n  */\r\n\r\n/******************************* ADC Instances ********************************/\r\n#define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \\\r\n                                       ((__INSTANCE__) == ADC2) || \\\r\n                                       ((__INSTANCE__) == ADC3))\r\n\r\n/******************************* CAN Instances ********************************/\r\n#define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \\\r\n                                           ((__INSTANCE__) == CAN2))\r\n/******************************* CRC Instances ********************************/\r\n#define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)\r\n\r\n/******************************* DAC Instances ********************************/\r\n#define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC)\r\n\r\n/******************************* DCMI Instances *******************************/\r\n#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)\r\n\r\n\r\n/******************************* DMA2D Instances *******************************/\r\n#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)\r\n\r\n/******************************** DMA Instances *******************************/\r\n#define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \\\r\n                                              ((__INSTANCE__) == DMA1_Stream1) || \\\r\n                                              ((__INSTANCE__) == DMA1_Stream2) || \\\r\n                                              ((__INSTANCE__) == DMA1_Stream3) || \\\r\n                                              ((__INSTANCE__) == DMA1_Stream4) || \\\r\n                                              ((__INSTANCE__) == DMA1_Stream5) || \\\r\n                                              ((__INSTANCE__) == DMA1_Stream6) || \\\r\n                                              ((__INSTANCE__) == DMA1_Stream7) || \\\r\n                                              ((__INSTANCE__) == DMA2_Stream0) || \\\r\n                                              ((__INSTANCE__) == DMA2_Stream1) || \\\r\n                                              ((__INSTANCE__) == DMA2_Stream2) || \\\r\n                                              ((__INSTANCE__) == DMA2_Stream3) || \\\r\n                                              ((__INSTANCE__) == DMA2_Stream4) || \\\r\n                                              ((__INSTANCE__) == DMA2_Stream5) || \\\r\n                                              ((__INSTANCE__) == DMA2_Stream6) || \\\r\n                                              ((__INSTANCE__) == DMA2_Stream7))\r\n\r\n/******************************* GPIO Instances *******************************/\r\n#define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \\\r\n                                        ((__INSTANCE__) == GPIOB) || \\\r\n                                        ((__INSTANCE__) == GPIOC) || \\\r\n                                        ((__INSTANCE__) == GPIOD) || \\\r\n                                        ((__INSTANCE__) == GPIOE) || \\\r\n                                        ((__INSTANCE__) == GPIOF) || \\\r\n                                        ((__INSTANCE__) == GPIOG) || \\\r\n                                        ((__INSTANCE__) == GPIOH) || \\\r\n                                        ((__INSTANCE__) == GPIOI) || \\\r\n                                        ((__INSTANCE__) == GPIOJ) || \\\r\n                                        ((__INSTANCE__) == GPIOK))\r\n\t\t\t\t\t\t\t\t\t\t\r\n#define IS_GPIO_AF_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == GPIOA) || \\\r\n                                        ((__INSTANCE__) == GPIOB) || \\\r\n                                        ((__INSTANCE__) == GPIOC) || \\\r\n                                        ((__INSTANCE__) == GPIOD) || \\\r\n                                        ((__INSTANCE__) == GPIOE) || \\\r\n                                        ((__INSTANCE__) == GPIOF) || \\\r\n                                        ((__INSTANCE__) == GPIOG) || \\\r\n                                        ((__INSTANCE__) == GPIOH) || \\\r\n                                        ((__INSTANCE__) == GPIOI) || \\\r\n                                        ((__INSTANCE__) == GPIOJ) || \\\r\n                                        ((__INSTANCE__) == GPIOK))\r\n\r\n/****************************** CEC Instances *********************************/\r\n#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)\r\n\r\n/****************************** QSPI Instances *********************************/\r\n#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)\r\n\r\n                                        \r\n/******************************** I2C Instances *******************************/\r\n#define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \\\r\n                                       ((__INSTANCE__) == I2C2) || \\\r\n                                       ((__INSTANCE__) == I2C3) || \\\r\n                                       ((__INSTANCE__) == I2C4))\r\n\r\n/******************************** I2S Instances *******************************/\r\n#define IS_I2S_ALL_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == SPI1) || \\\r\n                                    ((__INSTANCE__) == SPI2) || \\\r\n                                    ((__INSTANCE__) == SPI3))\r\n\r\n/******************************* LPTIM Instances ********************************/\r\n#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)\r\n\r\n/****************************** LTDC Instances ********************************/\r\n#define IS_LTDC_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == LTDC)\r\n\r\n\r\n\r\n/******************************* RNG Instances ********************************/\r\n#define IS_RNG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == RNG)\r\n\r\n/****************************** RTC Instances *********************************/\r\n#define IS_RTC_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == RTC)\r\n\r\n/******************************* SAI Instances ********************************/\r\n#define IS_SAI_ALL_INSTANCE(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \\\r\n                                         ((__PERIPH__) == SAI1_Block_B) || \\\r\n                                         ((__PERIPH__) == SAI2_Block_A) || \\\r\n                                         ((__PERIPH__) == SAI2_Block_B))\r\n/* Legacy define */\r\n#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE\r\n\r\n/******************************** SDMMC Instances *******************************/\r\n#define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SDMMC1)\r\n\r\n/****************************** SPDIFRX Instances *********************************/\r\n#define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)\r\n                                     \r\n/******************************** SPI Instances *******************************/\r\n#define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \\\r\n                                       ((__INSTANCE__) == SPI2) || \\\r\n                                       ((__INSTANCE__) == SPI3) || \\\r\n                                       ((__INSTANCE__) == SPI4) || \\\r\n                                       ((__INSTANCE__) == SPI5) || \\\r\n                                       ((__INSTANCE__) == SPI6))\r\n\r\n/****************** TIM Instances : All supported instances *******************/\r\n#define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)   || \\\r\n                                   ((__INSTANCE__) == TIM2)   || \\\r\n                                   ((__INSTANCE__) == TIM3)   || \\\r\n                                   ((__INSTANCE__) == TIM4)   || \\\r\n                                   ((__INSTANCE__) == TIM5)   || \\\r\n                                   ((__INSTANCE__) == TIM6)   || \\\r\n                                   ((__INSTANCE__) == TIM7)   || \\\r\n                                   ((__INSTANCE__) == TIM8)   || \\\r\n                                   ((__INSTANCE__) == TIM9)   || \\\r\n                                   ((__INSTANCE__) == TIM10)  || \\\r\n                                   ((__INSTANCE__) == TIM11)  || \\\r\n                                   ((__INSTANCE__) == TIM12)  || \\\r\n                                   ((__INSTANCE__) == TIM13)  || \\\r\n                                   ((__INSTANCE__) == TIM14))\r\n\r\n/************* TIM Instances : at least 1 capture/compare channel *************/\r\n#define IS_TIM_CC1_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1)  || \\\r\n                                         ((__INSTANCE__) == TIM2)  || \\\r\n                                         ((__INSTANCE__) == TIM3)  || \\\r\n                                         ((__INSTANCE__) == TIM4)  || \\\r\n                                         ((__INSTANCE__) == TIM5)  || \\\r\n                                         ((__INSTANCE__) == TIM8)  || \\\r\n                                         ((__INSTANCE__) == TIM9)  || \\\r\n                                         ((__INSTANCE__) == TIM10) || \\\r\n                                         ((__INSTANCE__) == TIM11) || \\\r\n                                         ((__INSTANCE__) == TIM12) || \\\r\n                                         ((__INSTANCE__) == TIM13) || \\\r\n                                         ((__INSTANCE__) == TIM14))\r\n\r\n/************ TIM Instances : at least 2 capture/compare channels *************/\r\n#define IS_TIM_CC2_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1)  || \\\r\n                                         ((__INSTANCE__) == TIM2)  || \\\r\n                                         ((__INSTANCE__) == TIM3)  || \\\r\n                                         ((__INSTANCE__) == TIM4)  || \\\r\n                                         ((__INSTANCE__) == TIM5)  || \\\r\n                                         ((__INSTANCE__) == TIM8)  || \\\r\n                                         ((__INSTANCE__) == TIM9)  || \\\r\n                                         ((__INSTANCE__) == TIM12))\r\n\r\n/************ TIM Instances : at least 3 capture/compare channels *************/\r\n#define IS_TIM_CC3_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1) || \\\r\n                                         ((__INSTANCE__) == TIM2) || \\\r\n                                         ((__INSTANCE__) == TIM3) || \\\r\n                                         ((__INSTANCE__) == TIM4) || \\\r\n                                         ((__INSTANCE__) == TIM5) || \\\r\n                                         ((__INSTANCE__) == TIM8))\r\n\r\n/************ TIM Instances : at least 4 capture/compare channels *************/\r\n#define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\\r\n                                       ((__INSTANCE__) == TIM2) || \\\r\n                                       ((__INSTANCE__) == TIM3) || \\\r\n                                       ((__INSTANCE__) == TIM4) || \\\r\n                                       ((__INSTANCE__) == TIM5) || \\\r\n                                       ((__INSTANCE__) == TIM8))\r\n                                       \r\n/****************** TIM Instances : supporting combined 3-phase PWM mode ******/\r\n#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \\\r\n                                       (((__INSTANCE__) == TIM1)    || \\\r\n                                        ((__INSTANCE__) == TIM8))\r\n\r\n/****************** TIM Instances : supporting OCxREF clear *******************/\r\n#define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\\\r\n                                  (((__INSTANCE__) == TIM1)    || \\\r\n                                   ((__INSTANCE__) == TIM2)    || \\\r\n                                   ((__INSTANCE__) == TIM3)    || \\\r\n                                   ((__INSTANCE__) == TIM4)    || \\\r\n                                   ((__INSTANCE__) == TIM8))\r\n\r\n/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/\r\n#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\\\r\n                                                 (((__INSTANCE__) == TIM1)    || \\\r\n                                                  ((__INSTANCE__) == TIM2)    || \\\r\n                                                  ((__INSTANCE__) == TIM3)    || \\\r\n                                                  ((__INSTANCE__) == TIM4)    || \\\r\n                                                  ((__INSTANCE__) == TIM5)    || \\\r\n                                                  ((__INSTANCE__) == TIM8))\r\n \r\n/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/\r\n#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\\\r\n                                                   (((__INSTANCE__) == TIM1)    || \\\r\n                                                    ((__INSTANCE__) == TIM2)    || \\\r\n                                                    ((__INSTANCE__) == TIM3)    || \\\r\n                                                    ((__INSTANCE__) == TIM4)    || \\\r\n                                                    ((__INSTANCE__) == TIM5)    || \\\r\n                                                    ((__INSTANCE__) == TIM8))\r\n/****************** TIM Instances : at least 5 capture/compare channels *******/\r\n#define IS_TIM_CC5_INSTANCE(__INSTANCE__)\\\r\n  (((__INSTANCE__) == TIM1)    || \\\r\n   ((__INSTANCE__) == TIM8) )\r\n\r\n/****************** TIM Instances : at least 6 capture/compare channels *******/\r\n#define IS_TIM_CC6_INSTANCE(__INSTANCE__)\\\r\n  (((__INSTANCE__) == TIM1)    || \\\r\n   ((__INSTANCE__) == TIM8))\r\n\r\n                                       \r\n/******************** TIM Instances : Advanced-control timers *****************/\r\n#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\\r\n                                            ((__INSTANCE__) == TIM8))\r\n\r\n/****************** TIM Instances : supporting 2 break inputs *****************/\r\n#define IS_TIM_BREAK_INSTANCE(__INSTANCE__)\\\r\n  (((__INSTANCE__) == TIM1)    || \\\r\n   ((__INSTANCE__) == TIM8))\r\n   \r\n/******************* TIM Instances : Timer input XOR function *****************/\r\n#define IS_TIM_XOR_INSTANCE(__INSTANCE__)   (((__INSTANCE__) == TIM1) || \\\r\n                                         ((__INSTANCE__) == TIM2) || \\\r\n                                         ((__INSTANCE__) == TIM3) || \\\r\n                                         ((__INSTANCE__) == TIM4) || \\\r\n                                         ((__INSTANCE__) == TIM5) || \\\r\n                                         ((__INSTANCE__) == TIM8))\r\n\r\n/****************** TIM Instances : DMA requests generation (UDE) *************/\r\n#define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\\r\n                                       ((__INSTANCE__) == TIM2) || \\\r\n                                       ((__INSTANCE__) == TIM3) || \\\r\n                                       ((__INSTANCE__) == TIM4) || \\\r\n                                       ((__INSTANCE__) == TIM5) || \\\r\n                                       ((__INSTANCE__) == TIM6) || \\\r\n                                       ((__INSTANCE__) == TIM7) || \\\r\n                                       ((__INSTANCE__) == TIM8))\r\n\r\n/************ TIM Instances : DMA requests generation (CCxDE) *****************/\r\n#define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\\r\n                                          ((__INSTANCE__) == TIM2) || \\\r\n                                          ((__INSTANCE__) == TIM3) || \\\r\n                                          ((__INSTANCE__) == TIM4) || \\\r\n                                          ((__INSTANCE__) == TIM5) || \\\r\n                                          ((__INSTANCE__) == TIM8))\r\n\r\n/************ TIM Instances : DMA requests generation (COMDE) *****************/\r\n#define IS_TIM_CCDMA_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1) || \\\r\n                                          ((__INSTANCE__) == TIM2) || \\\r\n                                          ((__INSTANCE__) == TIM3) || \\\r\n                                          ((__INSTANCE__) == TIM4) || \\\r\n                                          ((__INSTANCE__) == TIM5) || \\\r\n                                          ((__INSTANCE__) == TIM8)) \r\n\r\n/******************** TIM Instances : DMA burst feature ***********************/\r\n#define IS_TIM_DMABURST_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1) || \\\r\n                                             ((__INSTANCE__) == TIM2) || \\\r\n                                             ((__INSTANCE__) == TIM3) || \\\r\n                                             ((__INSTANCE__) == TIM4) || \\\r\n                                             ((__INSTANCE__) == TIM5) || \\\r\n                                             ((__INSTANCE__) == TIM8))\r\n\r\n/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/\r\n#define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\\r\n                                          ((__INSTANCE__) == TIM2) || \\\r\n                                          ((__INSTANCE__) == TIM3) || \\\r\n                                          ((__INSTANCE__) == TIM4) || \\\r\n                                          ((__INSTANCE__) == TIM5) || \\\r\n                                          ((__INSTANCE__) == TIM6) || \\\r\n                                          ((__INSTANCE__) == TIM7) || \\\r\n                                          ((__INSTANCE__) == TIM8) || \\\r\n                                          ((__INSTANCE__) == TIM13) || \\\r\n                                          ((__INSTANCE__) == TIM14))\r\n\r\n/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/\r\n#define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\\r\n                                         ((__INSTANCE__) == TIM2) || \\\r\n                                         ((__INSTANCE__) == TIM3) || \\\r\n                                         ((__INSTANCE__) == TIM4) || \\\r\n                                         ((__INSTANCE__) == TIM5) || \\\r\n                                         ((__INSTANCE__) == TIM8) || \\\r\n                                         ((__INSTANCE__) == TIM9) || \\\r\n                                         ((__INSTANCE__) == TIM12))\r\n\r\n/********************** TIM Instances : 32 bit Counter ************************/\r\n#define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__)(((__INSTANCE__) == TIM2) || \\\r\n                                              ((__INSTANCE__) == TIM5))\r\n\r\n/***************** TIM Instances : external trigger input available ************/\r\n#define IS_TIM_ETR_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1) || \\\r\n                                        ((__INSTANCE__) == TIM2) || \\\r\n                                        ((__INSTANCE__) == TIM3) || \\\r\n                                        ((__INSTANCE__) == TIM4) || \\\r\n                                        ((__INSTANCE__) == TIM5) || \\\r\n                                        ((__INSTANCE__) == TIM8))\r\n\r\n/****************** TIM Instances : remapping capability **********************/\r\n#define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2)  || \\\r\n                                         ((__INSTANCE__) == TIM5)  || \\\r\n                                         ((__INSTANCE__) == TIM11))\r\n\r\n/******************* TIM Instances : output(s) available **********************/\r\n#define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \\\r\n    ((((__INSTANCE__) == TIM1) &&                  \\\r\n     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_4)))           \\\r\n    ||                                         \\\r\n    (((__INSTANCE__) == TIM2) &&                   \\\r\n     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_4)))           \\\r\n    ||                                         \\\r\n    (((__INSTANCE__) == TIM3) &&                   \\\r\n     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_4)))           \\\r\n    ||                                         \\\r\n    (((__INSTANCE__) == TIM4) &&                   \\\r\n     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_4)))           \\\r\n    ||                                         \\\r\n    (((__INSTANCE__) == TIM5) &&                   \\\r\n     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_4)))           \\\r\n    ||                                         \\\r\n    (((__INSTANCE__) == TIM8) &&                   \\\r\n     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_2) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_3) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_4)))           \\\r\n    ||                                         \\\r\n    (((__INSTANCE__) == TIM9) &&                   \\\r\n     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_2)))           \\\r\n    ||                                         \\\r\n    (((__INSTANCE__) == TIM10) &&                  \\\r\n     (((__CHANNEL__) == TIM_CHANNEL_1)))           \\\r\n    ||                                         \\\r\n    (((__INSTANCE__) == TIM11) &&                  \\\r\n     (((__CHANNEL__) == TIM_CHANNEL_1)))           \\\r\n    ||                                         \\\r\n    (((__INSTANCE__) == TIM12) &&                  \\\r\n     (((__CHANNEL__) == TIM_CHANNEL_1) ||          \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_2)))           \\\r\n    ||                                         \\\r\n    (((__INSTANCE__) == TIM13) &&                  \\\r\n     (((__CHANNEL__) == TIM_CHANNEL_1)))           \\\r\n    ||                                         \\\r\n    (((__INSTANCE__) == TIM14) &&                  \\\r\n     (((__CHANNEL__) == TIM_CHANNEL_1))))\r\n\r\n/************ TIM Instances : complementary output(s) available ***************/\r\n#define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \\\r\n   ((((__INSTANCE__) == TIM1) &&                    \\\r\n     (((__CHANNEL__) == TIM_CHANNEL_1) ||           \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_2) ||           \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_3)))            \\\r\n    ||                                          \\\r\n    (((__INSTANCE__) == TIM8) &&                    \\\r\n     (((__CHANNEL__) == TIM_CHANNEL_1) ||           \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_2) ||           \\\r\n      ((__CHANNEL__) == TIM_CHANNEL_3))))\r\n\r\n/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/\r\n#define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\\\r\n  (((__INSTANCE__) == TIM1)    || \\\r\n   ((__INSTANCE__) == TIM8) )\r\n\r\n/****************** TIM Instances : supporting synchronization ****************/\r\n#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\\\r\n    (((__INSTANCE__) == TIM1)    || \\\r\n     ((__INSTANCE__) == TIM2)    || \\\r\n     ((__INSTANCE__) == TIM3)    || \\\r\n     ((__INSTANCE__) == TIM4)    || \\\r\n     ((__INSTANCE__) == TIM5)    || \\\r\n     ((__INSTANCE__) == TIM6)    || \\\r\n     ((__INSTANCE__) == TIM7)    || \\\r\n     ((__INSTANCE__) == TIM8))  \r\n      \r\n/******************** USART Instances : Synchronous mode **********************/\r\n#define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\\r\n                                     ((__INSTANCE__) == USART2) || \\\r\n                                     ((__INSTANCE__) == USART3) || \\\r\n                                     ((__INSTANCE__) == USART6))\r\n\r\n/******************** UART Instances : Asynchronous mode **********************/\r\n#define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\\r\n                                    ((__INSTANCE__) == USART2) || \\\r\n                                    ((__INSTANCE__) == USART3) || \\\r\n                                    ((__INSTANCE__) == UART4)  || \\\r\n                                    ((__INSTANCE__) == UART5)  || \\\r\n                                    ((__INSTANCE__) == USART6) || \\\r\n                                    ((__INSTANCE__) == UART7)  || \\\r\n                                    ((__INSTANCE__) == UART8))\r\n\r\n/****************** UART Instances : Driver Enable *****************/\r\n#define IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\\r\n                                    ((__INSTANCE__) == USART2) || \\\r\n                                    ((__INSTANCE__) == USART3) || \\\r\n                                    ((__INSTANCE__) == UART4)  || \\\r\n                                    ((__INSTANCE__) == UART5)  || \\\r\n                                    ((__INSTANCE__) == USART6) || \\\r\n                                    ((__INSTANCE__) == UART7)  || \\\r\n                                    ((__INSTANCE__) == UART8))\r\n\r\n/****************** UART Instances : Hardware Flow control ********************/\r\n#define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\\r\n                                    ((__INSTANCE__) == USART2) || \\\r\n                                    ((__INSTANCE__) == USART3) || \\\r\n                                    ((__INSTANCE__) == UART4)  || \\\r\n                                    ((__INSTANCE__) == UART5)  || \\\r\n                                    ((__INSTANCE__) == USART6) || \\\r\n                                    ((__INSTANCE__) == UART7)  || \\\r\n                                    ((__INSTANCE__) == UART8))\r\n\r\n/********************* UART Instances : Smart card mode ***********************/\r\n#define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\\r\n                                         ((__INSTANCE__) == USART2) || \\\r\n                                         ((__INSTANCE__) == USART3) || \\\r\n                                         ((__INSTANCE__) == USART6))\r\n\r\n/*********************** UART Instances : IRDA mode ***************************/\r\n#define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\\r\n                                    ((__INSTANCE__) == USART2) || \\\r\n                                    ((__INSTANCE__) == USART3) || \\\r\n                                    ((__INSTANCE__) == UART4)  || \\\r\n                                    ((__INSTANCE__) == UART5)  || \\\r\n                                    ((__INSTANCE__) == USART6) || \\\r\n                                    ((__INSTANCE__) == UART7)  || \\\r\n                                    ((__INSTANCE__) == UART8))     \r\n\r\n/****************************** IWDG Instances ********************************/\r\n#define IS_IWDG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == IWDG)\r\n\r\n/****************************** WWDG Instances ********************************/\r\n#define IS_WWDG_ALL_INSTANCE(__INSTANCE__)  ((__INSTANCE__) == WWDG)\r\n\r\n\r\n/******************************************************************************/\r\n/*  For a painless codes migration between the STM32F7xx device product       */\r\n/*  lines, the aliases defined below are put in place to overcome the         */\r\n/*  differences in the interrupt handlers and IRQn definitions.               */\r\n/*  No need to update developed interrupt code when moving across             */\r\n/*  product lines within the same STM32F7 Family                              */\r\n/******************************************************************************/\r\n\r\n/* Aliases for __IRQn */\r\n#define HASH_RNG_IRQn              RNG_IRQn\r\n\r\n/* Aliases for __IRQHandler */\r\n#define HASH_RNG_IRQHandler        RNG_IRQHandler\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif /* __cplusplus */\r\n\r\n#endif /* __STM32F746xx_H */\r\n\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/cfg/stm32f7xx.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   CMSIS STM32F7xx Device Peripheral Access Layer Header File.           \r\n  *            \r\n  *          The file is the unique include file that the application programmer\r\n  *          is using in the C source code, usually in main.c. This file contains:\r\n  *           - Configuration section that allows to select:\r\n  *              - The STM32F7xx device used in the target application\r\n  *              - To use or not the peripherals drivers in application code(i.e. \r\n  *                code will be based on direct access to peripherals registers \r\n  *                rather than drivers API), this option is controlled by \r\n  *                \"#define USE_HAL_DRIVER\"\r\n  *  \r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/** @addtogroup CMSIS\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup stm32f7xx\r\n  * @{\r\n  */\r\n    \r\n#ifndef __STM32F7xx_H\r\n#define __STM32F7xx_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif /* __cplusplus */\r\n  \r\n/** @addtogroup Library_configuration_section\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief STM32 Family\r\n  */\r\n#if !defined  (STM32F7)\r\n#define STM32F7\r\n#endif /* STM32F7 */\r\n\r\n/* Uncomment the line below according to the target STM32 device used in your\r\n   application \r\n  */\r\n#if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx) && !defined (STM32F767xx) && \\\r\n    !defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx)\r\n  /* #define STM32F756xx */   /*!< STM32F756VG, STM32F756ZG, STM32F756ZG, STM32F756IG, STM32F756BG,\r\n                                   STM32F756NG Devices */\r\n  /* #define STM32F746xx */   /*!< STM32F746VE, STM32F746VG, STM32F746ZE, STM32F746ZG, STM32F746IE, STM32F746IG,\r\n                                   STM32F746BE, STM32F746BG, STM32F746NE, STM32F746NG Devices */\r\n  /* #define STM32F745xx */   /*!< STM32F745VE, STM32F745VG, STM32F745ZG, STM32F745ZE, STM32F745IE, STM32F745IG Devices */\r\n  /* #define STM32F765xx */   /*!< STM32F765BI, STM32F765BG, STM32F765NI, STM32F765NG, STM32F765II, STM32F765IG,\r\n                                   STM32F765ZI, STM32F765ZG, STM32F765VI, STM32F765VG Devices */\r\n  /* #define STM32F767xx */   /*!< STM32F767BG, STM32F767BI, STM32F767IG, STM32F767II, STM32F767NG, STM32F767NI,\r\n                                   STM32F767VG, STM32F767VI, STM32F767ZG, STM32F767ZI, STM32F768AI Devices */\r\n  /* #define STM32F769xx */   /*!< STM32F769AG, STM32F769AI, STM32F769BG, STM32F769BI, STM32F769IG, STM32F769II,\r\n                                   STM32F769NG, STM32F769NI Devices */\r\n  /* #define STM32F777xx */   /*!< STM32F777VI, STM32F777ZI, STM32F777II, STM32F777BI, STM32F777NI, STM32F778AI Devices */\r\n  /* #define STM32F779xx */   /*!< STM32F779II, STM32F779BI, STM32F779NI, STM32F779AI Devices */\r\n#endif\r\n\r\n/*  Tip: To avoid modifying this file each time you need to switch between these\r\n        devices, you can define the device in your toolchain compiler preprocessor.\r\n  */\r\n\r\n#if !defined  (USE_HAL_DRIVER)\r\n/**\r\n * @brief Comment the line below if you will not use the peripherals drivers.\r\n   In this case, these drivers will not be included and the application code will \r\n   be based on direct access to peripherals registers \r\n   */\r\n  /*#define USE_HAL_DRIVER */\r\n#endif /* USE_HAL_DRIVER */\r\n\r\n/**\r\n  * @brief CMSIS Device version number V1.1.0\r\n  */\r\n#define __STM32F7_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */\r\n#define __STM32F7_CMSIS_VERSION_SUB1   (0x01) /*!< [23:16] sub1 version */\r\n#define __STM32F7_CMSIS_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */\r\n#define __STM32F7_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ \r\n#define __STM32F7_CMSIS_VERSION        ((__STM32F7_CMSIS_VERSION_MAIN << 24)\\\r\n                                       |(__STM32F7_CMSIS_VERSION_SUB1 << 16)\\\r\n                                       |(__STM32F7_CMSIS_VERSION_SUB2 << 8 )\\\r\n                                       |(__STM32F7_CMSIS_VERSION))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup Device_Included\r\n  * @{\r\n  */\r\n#if defined(STM32F756xx)\r\n  #include \"stm32f756xx.h\"\r\n#elif defined(STM32F746xx)\r\n  #include \"stm32f746xx.h\"\r\n#elif defined(STM32F745xx)\r\n  #include \"stm32f745xx.h\"\r\n#elif defined(STM32F765xx)\r\n  #include \"stm32f765xx.h\"\r\n#elif defined(STM32F767xx)\r\n  #include \"stm32f767xx.h\"\r\n#elif defined(STM32F769xx)\r\n  #include \"stm32f769xx.h\"\r\n#elif defined(STM32F777xx)\r\n  #include \"stm32f777xx.h\"\r\n#elif defined(STM32F779xx)\r\n  #include \"stm32f779xx.h\"  \r\n#else\r\n #error \"Please select first the target STM32F7xx device used in your application (in stm32f7xx.h file)\"\r\n#endif\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup Exported_types\r\n  * @{\r\n  */ \r\ntypedef enum \r\n{\r\n  RESET = 0, \r\n  SET = !RESET\r\n} FlagStatus, ITStatus;\r\n\r\ntypedef enum \r\n{\r\n  DISABLE = 0, \r\n  ENABLE = !DISABLE\r\n} FunctionalState;\r\n#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\r\n\r\ntypedef enum \r\n{\r\n  ERROR = 0, \r\n  SUCCESS = !ERROR\r\n} ErrorStatus;\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @addtogroup Exported_macro\r\n  * @{\r\n  */\r\n#define SET_BIT(REG, BIT)     ((REG) |= (BIT))\r\n\r\n#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))\r\n\r\n#define READ_BIT(REG, BIT)    ((REG) & (BIT))\r\n\r\n#define CLEAR_REG(REG)        ((REG) = (0x0))\r\n\r\n#define WRITE_REG(REG, VAL)   ((REG) = (VAL))\r\n\r\n#define READ_REG(REG)         ((REG))\r\n\r\n#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))\r\n\r\n#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL))) \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef USE_HAL_DRIVER\r\n  #include \"stm32f7xx_hal_conf.h\"\r\n#endif /* USE_HAL_DRIVER */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif /* __cplusplus */\r\n\r\n#endif /* __STM32F7xx_H */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n  /**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/cfg/stm32f7xx_hal_conf.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    USB_Device/CDC_Standalone/Inc/stm32f7xx_hal_conf.h\r\n  * @author  MCD Application Team\r\n  * @version V1.0.4\r\n  * @date    22-April-2016\r\n  * @brief   HAL configuration file.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_CONF_H\r\n#define __STM32F7xx_HAL_CONF_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/* ########################## Module Selection ############################## */\r\n/**\r\n  * @brief This is the list of modules to be used in the HAL driver \r\n  */\r\n#define HAL_MODULE_ENABLED  \r\n/* #define HAL_ADC_MODULE_ENABLED */\r\n/* #define HAL_CAN_MODULE_ENABLED */\r\n/* #define HAL_CEC_MODULE_ENABLED */\r\n/* #define HAL_CRC_MODULE_ENABLED */\r\n/* #define HAL_CRYP_MODULE_ENABLED */\r\n/* #define HAL_DAC_MODULE_ENABLED */\r\n/* #define HAL_DCMI_MODULE_ENABLED*/\r\n#define HAL_DMA_MODULE_ENABLED\r\n/* #define HAL_DMA2D_MODULE_ENABLED */\r\n/* #define HAL_ETH_MODULE_ENABLED */\r\n#define HAL_FLASH_MODULE_ENABLED\r\n/* #define HAL_NAND_MODULE_ENABLED */\r\n/* #define HAL_NOR_MODULE_ENABLED */\r\n/* #define HAL_SRAM_MODULE_ENABLED */\r\n/* #define HAL_SDRAM_MODULE_ENABLED */\r\n/* #define HAL_HASH_MODULE_ENABLED */\r\n#define HAL_GPIO_MODULE_ENABLED\r\n#define HAL_I2C_MODULE_ENABLED\r\n/* #define HAL_I2S_MODULE_ENABLED */\r\n#define HAL_IWDG_MODULE_ENABLED\r\n/* #define HAL_LPTIM_MODULE_ENABLED */\r\n/* #define HAL_LTDC_MODULE_ENABLED */\r\n#define HAL_PWR_MODULE_ENABLED\r\n/* #define HAL_QSPI_MODULE_ENABLED */\r\n#define HAL_RCC_MODULE_ENABLED \r\n/* #define HAL_RNG_MODULE_ENABLED */\r\n/* #define HAL_RTC_MODULE_ENABLED */\r\n/* #define HAL_SAI_MODULE_ENABLED */\r\n/* #define HAL_SD_MODULE_ENABLED */\r\n/* #define HAL_SPDIFRX_MODULE_ENABLED */\r\n/* #define HAL_SPI_MODULE_ENABLED */\r\n#define HAL_TIM_MODULE_ENABLED\r\n#define HAL_UART_MODULE_ENABLED\r\n/* #define HAL_USART_MODULE_ENABLED */\r\n/* #define HAL_IRDA_MODULE_ENABLED */\r\n/* #define HAL_SMARTCARD_MODULE_ENABLED */\r\n/* #define HAL_WWDG_MODULE_ENABLED */\r\n#define HAL_CORTEX_MODULE_ENABLED\r\n#define HAL_PCD_MODULE_ENABLED\r\n/* #define HAL_HCD_MODULE_ENABLED */\r\n\r\n\r\n/* ########################## HSE/HSI Values adaptation ##################### */\r\n/**\r\n  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.\r\n  *        This value is used by the RCC HAL module to compute the system frequency\r\n  *        (when HSE is used as system clock source, directly or through the PLL).  \r\n  */\r\n#if !defined  (HSE_VALUE) \r\n  #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */\r\n#endif /* HSE_VALUE */\r\n\r\n#if !defined  (HSE_STARTUP_TIMEOUT)\r\n  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */\r\n#endif /* HSE_STARTUP_TIMEOUT */\r\n\r\n/**\r\n  * @brief Internal High Speed oscillator (HSI) value.\r\n  *        This value is used by the RCC HAL module to compute the system frequency\r\n  *        (when HSI is used as system clock source, directly or through the PLL). \r\n  */\r\n#if !defined  (HSI_VALUE)\r\n  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/\r\n#endif /* HSI_VALUE */\r\n\r\n/**\r\n  * @brief Internal Low Speed oscillator (LSI) value.\r\n  */\r\n#if !defined  (LSI_VALUE) \r\n #define LSI_VALUE  ((uint32_t)32000)       /*!< LSI Typical Value in Hz*/\r\n#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz\r\n                                             The real value may vary depending on the variations\r\n                                             in voltage and temperature.  */\r\n/**\r\n  * @brief External Low Speed oscillator (LSE) value.\r\n  */\r\n#if !defined  (LSE_VALUE)\r\n #define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */\r\n#endif /* LSE_VALUE */\r\n#if !defined  (LSE_STARTUP_TIMEOUT)\r\n  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */\r\n#endif /* LSE_STARTUP_TIMEOUT */\r\n\r\n/**\r\n  * @brief External clock source for I2S peripheral\r\n  *        This value is used by the I2S HAL module to compute the I2S clock source \r\n  *        frequency, this source is inserted directly through I2S_CKIN pad. \r\n  */\r\n#if !defined  (EXTERNAL_CLOCK_VALUE)\r\n  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/\r\n#endif /* EXTERNAL_CLOCK_VALUE */\r\n\r\n/* Tip: To avoid modifying this file each time you need to use different HSE,\r\n   ===  you can define the HSE value in your toolchain compiler preprocessor. */\r\n\r\n/* ########################### System Configuration ######################### */\r\n/**\r\n  * @brief This is the HAL system configuration section\r\n  */     \r\n#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */\r\n#define  TICK_INT_PRIORITY            ((uint32_t)0x0) /*!< tick interrupt priority */\r\n#define  USE_RTOS                     0\r\n#define  ART_ACCLERATOR_ENABLE        1 /* To enable instruction cache and prefetch */\r\n\r\n/* ########################## Assert Selection ############################## */\r\n/**\r\n  * @brief Uncomment the line below to expanse the \"assert_param\" macro in the \r\n  *        HAL drivers code\r\n  */\r\n/* #define USE_FULL_ASSERT    1 */\r\n\r\n/* ################## Ethernet peripheral configuration ##################### */\r\n\r\n/* Section 1 : Ethernet peripheral configuration */\r\n\r\n/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */\r\n#define MAC_ADDR0   2\r\n#define MAC_ADDR1   0\r\n#define MAC_ADDR2   0\r\n#define MAC_ADDR3   0\r\n#define MAC_ADDR4   0\r\n#define MAC_ADDR5   0\r\n\r\n/* Definition of the Ethernet driver buffers size and count */   \r\n#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */\r\n#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */\r\n#define ETH_RXBUFNB                    ((uint32_t)4)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */\r\n#define ETH_TXBUFNB                    ((uint32_t)4)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */\r\n\r\n/* Section 2: PHY configuration section */\r\n\r\n/* DP83848 PHY Address*/ \r\n#define DP83848_PHY_ADDRESS             0x01\r\n/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ \r\n#define PHY_RESET_DELAY                 ((uint32_t)0x000000FF)\r\n/* PHY Configuration delay */\r\n#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)\r\n\r\n#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)\r\n#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)\r\n\r\n/* Section 3: Common PHY Registers */\r\n\r\n#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */\r\n#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */\r\n \r\n#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */\r\n#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */\r\n#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */\r\n#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */\r\n#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */\r\n#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */\r\n#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */\r\n#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */\r\n#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */\r\n#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */\r\n\r\n#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */\r\n#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */\r\n#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */\r\n  \r\n/* Section 4: Extended PHY Registers */\r\n\r\n#define PHY_SR                          ((uint16_t)0x10)    /*!< PHY status register Offset                      */\r\n#define PHY_MICR                        ((uint16_t)0x11)    /*!< MII Interrupt Control Register                  */\r\n#define PHY_MISR                        ((uint16_t)0x12)    /*!< MII Interrupt Status and Misc. Control Register */\r\n \r\n#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */\r\n#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */\r\n#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */\r\n\r\n#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */\r\n#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */\r\n\r\n#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */\r\n#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */\r\n\r\n/* ################## SPI peripheral configuration ########################## */\r\n\r\n/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver\r\n* Activated: CRC code is present inside driver\r\n* Deactivated: CRC code cleaned from driver\r\n*/\r\n\r\n#define USE_SPI_CRC                     1U\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n/**\r\n  * @brief Include module's header file \r\n  */\r\n\r\n#ifdef HAL_RCC_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_rcc.h\"\r\n#endif /* HAL_RCC_MODULE_ENABLED */\r\n\r\n#ifdef HAL_GPIO_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_gpio.h\"\r\n#endif /* HAL_GPIO_MODULE_ENABLED */\r\n\r\n#ifdef HAL_DMA_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_dma.h\"\r\n#endif /* HAL_DMA_MODULE_ENABLED */\r\n   \r\n#ifdef HAL_CORTEX_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_cortex.h\"\r\n#endif /* HAL_CORTEX_MODULE_ENABLED */\r\n\r\n#ifdef HAL_ADC_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_adc.h\"\r\n#endif /* HAL_ADC_MODULE_ENABLED */\r\n\r\n#ifdef HAL_CAN_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_can.h\"\r\n#endif /* HAL_CAN_MODULE_ENABLED */\r\n\r\n#ifdef HAL_CEC_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_cec.h\"\r\n#endif /* HAL_CEC_MODULE_ENABLED */\r\n\r\n#ifdef HAL_CRC_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_crc.h\"\r\n#endif /* HAL_CRC_MODULE_ENABLED */\r\n\r\n#ifdef HAL_CRYP_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_cryp.h\" \r\n#endif /* HAL_CRYP_MODULE_ENABLED */\r\n\r\n#ifdef HAL_DMA2D_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_dma2d.h\"\r\n#endif /* HAL_DMA2D_MODULE_ENABLED */\r\n\r\n#ifdef HAL_DAC_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_dac.h\"\r\n#endif /* HAL_DAC_MODULE_ENABLED */\r\n\r\n#ifdef HAL_DCMI_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_dcmi.h\"\r\n#endif /* HAL_DCMI_MODULE_ENABLED */\r\n\r\n#ifdef HAL_ETH_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_eth.h\"\r\n#endif /* HAL_ETH_MODULE_ENABLED */\r\n\r\n#ifdef HAL_FLASH_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_flash.h\"\r\n#endif /* HAL_FLASH_MODULE_ENABLED */\r\n \r\n#ifdef HAL_SRAM_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_sram.h\"\r\n#endif /* HAL_SRAM_MODULE_ENABLED */\r\n\r\n#ifdef HAL_NOR_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_nor.h\"\r\n#endif /* HAL_NOR_MODULE_ENABLED */\r\n\r\n#ifdef HAL_NAND_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_nand.h\"\r\n#endif /* HAL_NAND_MODULE_ENABLED */\r\n\r\n#ifdef HAL_SDRAM_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_sdram.h\"\r\n#endif /* HAL_SDRAM_MODULE_ENABLED */      \r\n\r\n#ifdef HAL_HASH_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_hash.h\"\r\n#endif /* HAL_HASH_MODULE_ENABLED */\r\n\r\n#ifdef HAL_I2C_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_i2c.h\"\r\n#endif /* HAL_I2C_MODULE_ENABLED */\r\n\r\n#ifdef HAL_I2S_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_i2s.h\"\r\n#endif /* HAL_I2S_MODULE_ENABLED */\r\n\r\n#ifdef HAL_IWDG_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_iwdg.h\"\r\n#endif /* HAL_IWDG_MODULE_ENABLED */\r\n\r\n#ifdef HAL_LPTIM_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_lptim.h\"\r\n#endif /* HAL_LPTIM_MODULE_ENABLED */\r\n\r\n#ifdef HAL_LTDC_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_ltdc.h\"\r\n#endif /* HAL_LTDC_MODULE_ENABLED */\r\n\r\n#ifdef HAL_PWR_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_pwr.h\"\r\n#endif /* HAL_PWR_MODULE_ENABLED */\r\n\r\n#ifdef HAL_QSPI_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_qspi.h\"\r\n#endif /* HAL_QSPI_MODULE_ENABLED */\r\n\r\n#ifdef HAL_RNG_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_rng.h\"\r\n#endif /* HAL_RNG_MODULE_ENABLED */\r\n\r\n#ifdef HAL_RTC_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_rtc.h\"\r\n#endif /* HAL_RTC_MODULE_ENABLED */\r\n\r\n#ifdef HAL_SAI_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_sai.h\"\r\n#endif /* HAL_SAI_MODULE_ENABLED */\r\n\r\n#ifdef HAL_SD_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_sd.h\"\r\n#endif /* HAL_SD_MODULE_ENABLED */\r\n\r\n#ifdef HAL_SPDIFRX_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_spdifrx.h\"\r\n#endif /* HAL_SPDIFRX_MODULE_ENABLED */\r\n\r\n#ifdef HAL_SPI_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_spi.h\"\r\n#endif /* HAL_SPI_MODULE_ENABLED */\r\n\r\n#ifdef HAL_TIM_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_tim.h\"\r\n#endif /* HAL_TIM_MODULE_ENABLED */\r\n\r\n#ifdef HAL_UART_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_uart.h\"\r\n#endif /* HAL_UART_MODULE_ENABLED */\r\n\r\n#ifdef HAL_USART_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_usart.h\"\r\n#endif /* HAL_USART_MODULE_ENABLED */\r\n\r\n#ifdef HAL_IRDA_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_irda.h\"\r\n#endif /* HAL_IRDA_MODULE_ENABLED */\r\n\r\n#ifdef HAL_SMARTCARD_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_smartcard.h\"\r\n#endif /* HAL_SMARTCARD_MODULE_ENABLED */\r\n\r\n#ifdef HAL_WWDG_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_wwdg.h\"\r\n#endif /* HAL_WWDG_MODULE_ENABLED */\r\n\r\n#ifdef HAL_PCD_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_pcd.h\"\r\n#endif /* HAL_PCD_MODULE_ENABLED */\r\n\r\n#ifdef HAL_HCD_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_hcd.h\"\r\n#endif /* HAL_HCD_MODULE_ENABLED */\r\n   \r\n/* Exported macro ------------------------------------------------------------*/\r\n#ifdef  USE_FULL_ASSERT\r\n/**\r\n  * @brief  The assert_param macro is used for function's parameters check.\r\n  * @param  expr: If expr is false, it calls assert_failed function\r\n  *         which reports the name of the source file and the source\r\n  *         line number of the call that failed. \r\n  *         If expr is true, it returns no value.\r\n  * @retval None\r\n  */\r\n  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))\r\n/* Exported functions ------------------------------------------------------- */\r\n  void assert_failed(uint8_t* file, uint32_t line);\r\n#else\r\n  #define assert_param(expr) ((void)0)\r\n#endif /* USE_FULL_ASSERT */\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_CONF_H */\r\n \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/cfg/stm32f7xx_it.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    USB_Device/CDC_Standalone/Src/stm32f7xx_it.c\r\n  * @author  MCD Application Team\r\n  * @version V1.0.3\r\n  * @date    18-November-2015\r\n  * @brief   Main Interrupt Service Routines.\r\n  *          This file provides template for all exceptions handler and \r\n  *          peripherals interrupt service routine.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software\r\n  * distributed under the License is distributed on an \"AS IS\" BASIS,\r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"bsp.h\"\r\n#include \"stm32f7xx_it.h\"\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\nextern PCD_HandleTypeDef hpcd;\r\n\r\n/* UART handler declared in \"usbd_cdc_interface.c\" file */\r\nextern UART_HandleTypeDef UartHandle;\r\n\r\n/* TIM handler declared in \"usbd_cdc_interface.c\" file */\r\nextern TIM_HandleTypeDef TimHandle;\r\n\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/******************************************************************************/\r\n/*            Cortex-M7 Processor Exceptions Handlers                         */\r\n/******************************************************************************/\r\n\r\n/**\r\n  * @brief   This function handles NMI exception.\r\n  * @param  None\r\n  * @retval None\r\n  */\r\nvoid NMI_Handler(void)\r\n{\r\n}\r\n\r\n/**\r\n  * @brief  This function handles Hard Fault exception.\r\n  * @param  None\r\n  * @retval None\r\n  */\r\nvoid HardFault_Handler(void)\r\n{\r\n  /* Go to infinite loop when Hard Fault exception occurs */\r\n  while (1)\r\n  {\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  This function handles Memory Manage exception.\r\n  * @param  None\r\n  * @retval None\r\n  */\r\nvoid MemManage_Handler(void)\r\n{\r\n  /* Go to infinite loop when Memory Manage exception occurs */\r\n  while (1)\r\n  {\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  This function handles Bus Fault exception.\r\n  * @param  None\r\n  * @retval None\r\n  */\r\nvoid BusFault_Handler(void)\r\n{\r\n  /* Go to infinite loop when Bus Fault exception occurs */\r\n  while (1)\r\n  {\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  This function handles Usage Fault exception.\r\n  * @param  None\r\n  * @retval None\r\n  */\r\nvoid UsageFault_Handler(void)\r\n{\r\n  /* Go to infinite loop when Usage Fault exception occurs */\r\n  while (1)\r\n  {\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  This function handles SVCall exception.\r\n  * @param  None\r\n  * @retval None\r\n  */\r\nvoid SVC_Handler(void)\r\n{\r\n}\r\n\r\n/**\r\n  * @brief  This function handles Debug Monitor exception.\r\n  * @param  None\r\n  * @retval None\r\n  */\r\nvoid DebugMon_Handler(void)\r\n{\r\n}\r\n\r\n/**\r\n  * @brief  This function handles PendSVC exception.\r\n  * @param  None\r\n  * @retval None\r\n  */\r\nvoid PendSV_Handler(void)\r\n{\r\n}\r\n\r\n/**\r\n  * @brief  This function handles SysTick Handler.\r\n  * @param  None\r\n  * @retval None\r\n  */\r\nvoid SysTick_Handler(void)\r\n{\r\n  HAL_IncTick();\r\n}\r\n\r\n/******************************************************************************/\r\n/*                 STM32F7xx Peripherals Interrupt Handlers                   */\r\n/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */\r\n/*  available peripheral interrupt handler's name please refer to the startup */\r\n/*  file (startup_stm32f7xx.s).                                               */\r\n/******************************************************************************/\r\n\r\n/**\r\n  * @brief  This function handles USB-On-The-Go FS/HS global interrupt request.\r\n  * @param  None\r\n  * @retval None\r\n  */\r\n#ifdef USE_USB_FS\r\nvoid OTG_FS_IRQHandler(void)\r\n#else\r\nvoid OTG_HS_IRQHandler(void)\r\n#endif\r\n{\r\n  HAL_PCD_IRQHandler(&hpcd);\r\n}\r\n\r\n/**\r\n  * @brief  This function handles DMA interrupt request.\r\n  * @param  None\r\n  * @retval None\r\n  */\r\nvoid USARTx_DMA_TX_IRQHandler(void)\r\n{\r\n  //HAL_DMA_IRQHandler(UartHandle.hdmatx);\r\n}\r\n\r\n/**\r\n  * @brief  This function handles UART interrupt request.\r\n  * @param  None\r\n  * @retval None\r\n  */\r\nvoid USARTx_IRQHandler(void)\r\n{\r\n  //HAL_UART_IRQHandler(&UartHandle);\r\n}\r\n\r\n/**\r\n  * @brief  This function handles TIM interrupt request.\r\n  * @param  None\r\n  * @retval None\r\n  */\r\nvoid TIMx_IRQHandler(void)\r\n{\r\n  //HAL_TIM_IRQHandler(&TimHandle);\r\n}\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/cfg/stm32f7xx_it.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    UART/UART_TwoBoards_ComIT/Inc/stm32f7xx_it.h \r\n  * @author  MCD Application Team\r\n  * @version V1.0.2\r\n  * @date    18-November-2015 \r\n  * @brief   This file contains the headers of the interrupt handlers.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_IT_H\r\n#define __STM32F7xx_IT_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions ------------------------------------------------------- */\r\n\r\nvoid NMI_Handler(void);\r\nvoid HardFault_Handler(void);\r\nvoid MemManage_Handler(void);\r\nvoid BusFault_Handler(void);\r\nvoid UsageFault_Handler(void);\r\nvoid SVC_Handler(void);\r\nvoid DebugMon_Handler(void);\r\nvoid PendSV_Handler(void);\r\nvoid SysTick_Handler(void);\r\nvoid USARTx_IRQHandler(void);\r\nvoid EXTI15_10_IRQHandler(void);\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_IT_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/cfg/syscalls.c",
    "content": "/* Support files for GNU libc.  Files in the system namespace go here.\r\n   Files in the C namespace (ie those that do not start with an\r\n   underscore) go in .c.  */\r\n\r\n#include <_ansi.h>\r\n#include <sys/types.h>\r\n#include <sys/stat.h>\r\n#include <sys/fcntl.h>\r\n#include <stdio.h>\r\n#include <string.h>\r\n#include <time.h>\r\n#include <sys/time.h>\r\n#include <sys/times.h>\r\n#include <errno.h>\r\n#include <reent.h>\r\n#include <unistd.h>\r\n#include <sys/wait.h>\r\n\r\n#undef errno\r\nextern int errno;\r\n\r\n#define FreeRTOS\r\n#define MAX_STACK_SIZE 0x2000\r\n\r\nextern int __io_putchar(int ch) __attribute__((weak));\r\nextern int __io_getchar(void) __attribute__((weak));\r\n\r\n#ifndef FreeRTOS\r\n  register char * stack_ptr asm(\"sp\");\r\n#endif\r\n\r\n\r\n\r\n\r\ncaddr_t _sbrk(int incr)\r\n{\r\n\textern char end asm(\"end\");\r\n\tstatic char *heap_end;\r\n\tchar *prev_heap_end,*min_stack_ptr;\r\n\r\n\tif (heap_end == 0)\r\n\t\theap_end = &end;\r\n\r\n\tprev_heap_end = heap_end;\r\n\r\n#ifdef FreeRTOS\r\n\t/* Use the NVIC offset register to locate the main stack pointer. */\r\n\tmin_stack_ptr = (char*)(*(unsigned int *)*(unsigned int *)0xE000ED08);\r\n\t/* Locate the STACK bottom address */\r\n\tmin_stack_ptr -= MAX_STACK_SIZE;\r\n\r\n\tif (heap_end + incr > min_stack_ptr)\r\n#else\r\n\tif (heap_end + incr > stack_ptr)\r\n#endif\r\n\t{\r\n//\t\twrite(1, \"Heap and stack collision\\n\", 25);\r\n//\t\tabort();\r\n\t\terrno = ENOMEM;\r\n\t\treturn (caddr_t) -1;\r\n\t}\r\n\r\n\theap_end += incr;\r\n\r\n\treturn (caddr_t) prev_heap_end;\r\n}\r\n\r\n/*\r\n * _gettimeofday primitive (Stub function)\r\n * */\r\nint _gettimeofday (struct timeval * tp, struct timezone * tzp)\r\n{\r\n  /* Return fixed data for the timezone.  */\r\n  if (tzp)\r\n    {\r\n      tzp->tz_minuteswest = 0;\r\n      tzp->tz_dsttime = 0;\r\n    }\r\n\r\n  return 0;\r\n}\r\nvoid initialise_monitor_handles()\r\n{\r\n}\r\n\r\nint _getpid(void)\r\n{\r\n\treturn 1;\r\n}\r\n\r\nint _kill(int pid, int sig)\r\n{\r\n\terrno = EINVAL;\r\n\treturn -1;\r\n}\r\n\r\nvoid _exit (int status)\r\n{\r\n\t_kill(status, -1);\r\n\twhile (1) {}\r\n}\r\n\r\nint _write(int file, char *ptr, int len)\r\n{\r\n\tint DataIdx;\r\n\r\n\t\tfor (DataIdx = 0; DataIdx < len; DataIdx++)\r\n\t\t{\r\n\t\t   __io_putchar( *ptr++ );\r\n\t\t}\r\n\treturn len;\r\n}\r\n\r\nint _close(int file)\r\n{\r\n\treturn -1;\r\n}\r\n\r\nint _fstat(int file, struct stat *st)\r\n{\r\n\tst->st_mode = S_IFCHR;\r\n\treturn 0;\r\n}\r\n\r\nint _isatty(int file)\r\n{\r\n\treturn 1;\r\n}\r\n\r\nint _lseek(int file, int ptr, int dir)\r\n{\r\n\treturn 0;\r\n}\r\n\r\nint _read(int file, char *ptr, int len)\r\n{\r\n\tint DataIdx;\r\n\r\n\tfor (DataIdx = 0; DataIdx < len; DataIdx++)\r\n\t{\r\n\t  *ptr++ = __io_getchar();\r\n\t}\r\n\r\n   return len;\r\n}\r\n\r\nint _open(char *path, int flags, ...)\r\n{\r\n\t/* Pretend like we always fail */\r\n\treturn -1;\r\n}\r\n\r\nint _wait(int *status)\r\n{\r\n\terrno = ECHILD;\r\n\treturn -1;\r\n}\r\n\r\nint _unlink(char *name)\r\n{\r\n\terrno = ENOENT;\r\n\treturn -1;\r\n}\r\n\r\nint _times(struct tms *buf)\r\n{\r\n\treturn -1;\r\n}\r\n\r\nint _stat(char *file, struct stat *st)\r\n{\r\n\tst->st_mode = S_IFCHR;\r\n\treturn 0;\r\n}\r\n\r\nint _link(char *old, char *new)\r\n{\r\n\terrno = EMLINK;\r\n\treturn -1;\r\n}\r\n\r\nint _fork(void)\r\n{\r\n\terrno = EAGAIN;\r\n\treturn -1;\r\n}\r\n\r\nint _execve(char *name, char **argv, char **env)\r\n{\r\n\terrno = ENOMEM;\r\n\treturn -1;\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/cfg/system_clock.c",
    "content": "#include \"stm32f7xx_hal.h\"\r\n#include \"stm32f7xx.h\"\r\n\r\n\r\n\r\n\r\n\r\n\r\n/**\r\n  * @brief  System Clock Configuration\r\n  *         The system Clock is configured as follow : \r\n  *            System Clock source            = PLL (HSE)\r\n  *            SYSCLK(Hz)                     = 216000000\r\n  *            HCLK(Hz)                       = 216000000\r\n  *            AHB Prescaler                  = 1\r\n  *            APB1 Prescaler                 = 4\r\n  *            APB2 Prescaler                 = 2\r\n  *            HSE Frequency(Hz)              = 25000000\r\n  *            PLL_M                          = 25\r\n  *            PLL_N                          = 432\r\n  *            PLL_P                          = 2\r\n  *            PLL_Q                          = 9\r\n  *            VDD(V)                         = 3.3\r\n  *            Main regulator output voltage  = Scale1 mode\r\n  *            Flash Latency(WS)              = 7\r\n  * @param  None\r\n  * @retval None\r\n  */\r\nvoid SystemClock_Config(void)\r\n{\r\n  RCC_ClkInitTypeDef RCC_ClkInitStruct;\r\n  RCC_OscInitTypeDef RCC_OscInitStruct;\r\n  HAL_StatusTypeDef ret = HAL_OK;\r\n\r\n  /* Enable HSE Oscillator and activate PLL with HSE as source */\r\n  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;\r\n  RCC_OscInitStruct.HSEState = RCC_HSE_ON;\r\n  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;\r\n  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;\r\n  RCC_OscInitStruct.PLL.PLLM = 25;\r\n  RCC_OscInitStruct.PLL.PLLN = 432;\r\n  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;\r\n  RCC_OscInitStruct.PLL.PLLQ = 9;\r\n  \r\n  ret = HAL_RCC_OscConfig(&RCC_OscInitStruct);\r\n  if(ret != HAL_OK)\r\n  {\r\n    while(1) { ; }\r\n  }\r\n  \r\n  /* Activate the OverDrive to reach the 216 MHz Frequency */  \r\n  ret = HAL_PWREx_EnableOverDrive();\r\n  if(ret != HAL_OK)\r\n  {\r\n    while(1) { ; }\r\n  }\r\n  \r\n  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */\r\n  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);\r\n  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;\r\n  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;\r\n  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;  \r\n  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; \r\n  \r\n  ret = HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7);\r\n  if(ret != HAL_OK)\r\n  {\r\n    while(1) { ; }\r\n  }  \r\n\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/cfg/system_clock.h",
    "content": "#ifndef __SYSTEM_CLOCK_H\r\n#define __SYSTEM_CLOCK_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif \r\n  \r\n\r\nextern void SystemClock_Config(void);\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/cfg/system_stm32f7xx.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    system_stm32f7xx.c\r\n  * @author  MCD Application Team\r\n  * @version V1.0.3\r\n  * @date    22-April-2016\r\n  * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.\r\n  *\r\n  *   This file provides two functions and one global variable to be called from \r\n  *   user application:\r\n  *      - SystemInit(): This function is called at startup just after reset and \r\n  *                      before branch to main program. This call is made inside\r\n  *                      the \"startup_stm32f7xx.s\" file.\r\n  *\r\n  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used\r\n  *                                  by the user application to setup the SysTick \r\n  *                                  timer or configure other parameters.\r\n  *                                     \r\n  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must\r\n  *                                 be called whenever the core clock is changed\r\n  *                                 during program execution.\r\n  *\r\n  *\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/** @addtogroup CMSIS\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup stm32f7xx_system\r\n  * @{\r\n  */  \r\n  \r\n/** @addtogroup STM32F7xx_System_Private_Includes\r\n  * @{\r\n  */\r\n\r\n#include \"stm32f7xx.h\"\r\n\r\n#if !defined  (HSE_VALUE) \r\n  #define HSE_VALUE    ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */\r\n#endif /* HSE_VALUE */\r\n\r\n#if !defined  (HSI_VALUE)\r\n  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/\r\n#endif /* HSI_VALUE */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup STM32F7xx_System_Private_TypesDefinitions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup STM32F7xx_System_Private_Defines\r\n  * @{\r\n  */\r\n\r\n/************************* Miscellaneous Configuration ************************/\r\n/*!< Uncomment the following line if you need to use external SDRAM mounted\r\n     on DK as data memory  */\r\n/* #define DATA_IN_ExtSDRAM */\r\n\r\n/*!< Uncomment the following line if you need to relocate your vector Table in\r\n     Internal SRAM. */\r\n/* #define VECT_TAB_SRAM */\r\n#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. \r\n                                   This value must be a multiple of 0x200. */\r\n/******************************************************************************/\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup STM32F7xx_System_Private_Macros\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup STM32F7xx_System_Private_Variables\r\n  * @{\r\n  */\r\n\r\n  /* This variable is updated in three ways:\r\n      1) by calling CMSIS function SystemCoreClockUpdate()\r\n      2) by calling HAL API function HAL_RCC_GetHCLKFreq()\r\n      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency \r\n         Note: If you use this function to configure the system clock; then there\r\n               is no need to call the 2 first functions listed above, since SystemCoreClock\r\n               variable is updated automatically.\r\n  */\r\n  uint32_t SystemCoreClock = 16000000;\r\n  const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};\r\n  const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes\r\n  * @{\r\n  */\r\n#if defined (DATA_IN_ExtSDRAM)\r\n  static void SystemInit_ExtMemCtl(void); \r\n#endif /* DATA_IN_ExtSDRAM */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup STM32F7xx_System_Private_Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Setup the microcontroller system\r\n  *         Initialize the Embedded Flash Interface, the PLL and update the \r\n  *         SystemFrequency variable.\r\n  * @param  None\r\n  * @retval None\r\n  */\r\nvoid SystemInit(void)\r\n{\r\n  /* FPU settings ------------------------------------------------------------*/\r\n  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r\n    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */\r\n  #endif\r\n  /* Reset the RCC clock configuration to the default reset state ------------*/\r\n  /* Set HSION bit */\r\n  RCC->CR |= (uint32_t)0x00000001;\r\n\r\n  /* Reset CFGR register */\r\n  RCC->CFGR = 0x00000000;\r\n\r\n  /* Reset HSEON, CSSON and PLLON bits */\r\n  RCC->CR &= (uint32_t)0xFEF6FFFF;\r\n\r\n  /* Reset PLLCFGR register */\r\n  RCC->PLLCFGR = 0x24003010;\r\n\r\n  /* Reset HSEBYP bit */\r\n  RCC->CR &= (uint32_t)0xFFFBFFFF;\r\n\r\n  /* Disable all interrupts */\r\n  RCC->CIR = 0x00000000;\r\n\r\n#if defined (DATA_IN_ExtSDRAM)\r\n  SystemInit_ExtMemCtl(); \r\n#endif /* DATA_IN_ExtSDRAM */\r\n\r\n  /* Configure the Vector Table location add offset address ------------------*/\r\n#ifdef VECT_TAB_SRAM\r\n  SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */\r\n#else\r\n  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */\r\n#endif\r\n}\r\n\r\n/**\r\n   * @brief  Update SystemCoreClock variable according to Clock Register Values.\r\n  *         The SystemCoreClock variable contains the core clock (HCLK), it can\r\n  *         be used by the user application to setup the SysTick timer or configure\r\n  *         other parameters.\r\n  *           \r\n  * @note   Each time the core clock (HCLK) changes, this function must be called\r\n  *         to update SystemCoreClock variable value. Otherwise, any configuration\r\n  *         based on this variable will be incorrect.         \r\n  *     \r\n  * @note   - The system frequency computed by this function is not the real \r\n  *           frequency in the chip. It is calculated based on the predefined \r\n  *           constant and the selected clock source:\r\n  *             \r\n  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)\r\n  *                                              \r\n  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)\r\n  *                          \r\n  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) \r\n  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.\r\n  *         \r\n  *         (*) HSI_VALUE is a constant defined in stm32f7xx.h file (default value\r\n  *             16 MHz) but the real value may vary depending on the variations\r\n  *             in voltage and temperature.   \r\n  *    \r\n  *         (**) HSE_VALUE is a constant defined in stm32f7xx.h file (default value\r\n  *              25 MHz), user has to ensure that HSE_VALUE is same as the real\r\n  *              frequency of the crystal used. Otherwise, this function may\r\n  *              have wrong result.\r\n  *                \r\n  *         - The result of this function could be not correct when using fractional\r\n  *           value for HSE crystal.\r\n  *     \r\n  * @param  None\r\n  * @retval None\r\n  */\r\nvoid SystemCoreClockUpdate(void)\r\n{\r\n  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;\r\n  \r\n  /* Get SYSCLK source -------------------------------------------------------*/\r\n  tmp = RCC->CFGR & RCC_CFGR_SWS;\r\n\r\n  switch (tmp)\r\n  {\r\n    case 0x00:  /* HSI used as system clock source */\r\n      SystemCoreClock = HSI_VALUE;\r\n      break;\r\n    case 0x04:  /* HSE used as system clock source */\r\n      SystemCoreClock = HSE_VALUE;\r\n      break;\r\n    case 0x08:  /* PLL used as system clock source */\r\n\r\n      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N\r\n         SYSCLK = PLL_VCO / PLL_P\r\n         */    \r\n      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;\r\n      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;\r\n      \r\n      if (pllsource != 0)\r\n      {\r\n        /* HSE used as PLL clock source */\r\n        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);\r\n      }\r\n      else\r\n      {\r\n        /* HSI used as PLL clock source */\r\n        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      \r\n      }\r\n\r\n      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;\r\n      SystemCoreClock = pllvco/pllp;\r\n      break;\r\n    default:\r\n      SystemCoreClock = HSI_VALUE;\r\n      break;\r\n  }\r\n  /* Compute HCLK frequency --------------------------------------------------*/\r\n  /* Get HCLK prescaler */\r\n  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];\r\n  /* HCLK frequency */\r\n  SystemCoreClock >>= tmp;\r\n}\r\n\r\n#if defined (DATA_IN_ExtSDRAM)\r\n/**\r\n  * @brief  Setup the external memory controller.\r\n  *         Called in startup_stm32f7xx.s before jump to main.\r\n  *         This function configures the external memories (SDRAM)\r\n  *         This SDRAM will be used as program data memory (including heap and stack).\r\n  * @param  None\r\n  * @retval None\r\n  */\r\nvoid SystemInit_ExtMemCtl(void)\r\n{\r\n  register uint32_t tmpreg = 0, timeout = 0xFFFF;\r\n  register __IO uint32_t index;\r\n\r\n  /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG and GPIOH interface\r\n  clock */\r\n  RCC->AHB1ENR |= 0x000000FC;\r\n  \r\n  /* Connect PCx pins to FMC Alternate function */\r\n  GPIOC->AFR[0]  = 0x0000C000;\r\n  GPIOC->AFR[1]  = 0x00000000;\r\n  /* Configure PCx pins in Alternate function mode */\r\n  GPIOC->MODER   = 0x00000080;\r\n  /* Configure PCx pins speed to 50 MHz */\r\n  GPIOC->OSPEEDR = 0x00000080;\r\n  /* Configure PCx pins Output type to push-pull */\r\n  GPIOC->OTYPER  = 0x00000000;\r\n  /* No pull-up, pull-down for PCx pins */\r\n  GPIOC->PUPDR   = 0x00000040;\r\n  \r\n  /* Connect PDx pins to FMC Alternate function */\r\n  GPIOD->AFR[0]  = 0x000000CC;\r\n  GPIOD->AFR[1]  = 0xCC000CCC;\r\n  /* Configure PDx pins in Alternate function mode */\r\n  GPIOD->MODER   = 0xA02A000A;\r\n  /* Configure PDx pins speed to 50 MHz */\r\n  GPIOD->OSPEEDR = 0xA02A000A;\r\n  /* Configure PDx pins Output type to push-pull */\r\n  GPIOD->OTYPER  = 0x00000000;\r\n  /* No pull-up, pull-down for PDx pins */ \r\n  GPIOD->PUPDR   = 0x50150005;\r\n\r\n  /* Connect PEx pins to FMC Alternate function */\r\n  GPIOE->AFR[0]  = 0xC00000CC;\r\n  GPIOE->AFR[1]  = 0xCCCCCCCC;\r\n  /* Configure PEx pins in Alternate function mode */ \r\n  GPIOE->MODER   = 0xAAAA800A;\r\n  /* Configure PEx pins speed to 50 MHz */\r\n  GPIOE->OSPEEDR = 0xAAAA800A;\r\n  /* Configure PEx pins Output type to push-pull */\r\n  GPIOE->OTYPER  = 0x00000000;\r\n  /* No pull-up, pull-down for PEx pins */ \r\n  GPIOE->PUPDR   = 0x55554005;\r\n\r\n  /* Connect PFx pins to FMC Alternate function */\r\n  GPIOF->AFR[0]  = 0x00CCCCCC;\r\n  GPIOF->AFR[1]  = 0xCCCCC000;\r\n  /* Configure PFx pins in Alternate function mode */\r\n  GPIOF->MODER   = 0xAA800AAA;\r\n  /* Configure PFx pins speed to 50 MHz */\r\n  GPIOF->OSPEEDR = 0xAA800AAA;\r\n  /* Configure PFx pins Output type to push-pull */\r\n  GPIOF->OTYPER  = 0x00000000;\r\n  /* No pull-up, pull-down for PFx pins */ \r\n  GPIOF->PUPDR   = 0x55400555;\r\n\r\n  /* Connect PGx pins to FMC Alternate function */\r\n  GPIOG->AFR[0]  = 0x00CC00CC;\r\n  GPIOG->AFR[1]  = 0xC000000C;\r\n  /* Configure PGx pins in Alternate function mode */ \r\n  GPIOG->MODER   = 0x80020A0A;\r\n  /* Configure PGx pins speed to 50 MHz */\r\n  GPIOG->OSPEEDR = 0x80020A0A;\r\n  /* Configure PGx pins Output type to push-pull */\r\n  GPIOG->OTYPER  = 0x00000000;\r\n  /* No pull-up, pull-down for PGx pins */ \r\n  GPIOG->PUPDR   = 0x40010505;\r\n  \r\n  /* Connect PHx pins to FMC Alternate function */\r\n  GPIOH->AFR[0]  = 0x00C0C000;\r\n  GPIOH->AFR[1]  = 0x00000000;\r\n  /* Configure PHx pins in Alternate function mode */ \r\n  GPIOH->MODER   = 0x00000880;\r\n  /* Configure PHx pins speed to 50 MHz */\r\n  GPIOH->OSPEEDR = 0x00000880;\r\n  /* Configure PHx pins Output type to push-pull */\r\n  GPIOH->OTYPER  = 0x00000000;\r\n  /* No pull-up, pull-down for PHx pins */ \r\n  GPIOH->PUPDR   = 0x00000440;\r\n  \r\n  /* Enable the FMC interface clock */\r\n  RCC->AHB3ENR |= 0x00000001;\r\n  \r\n\t/* Configure and enable SDRAM bank1 */\r\n  FMC_Bank5_6->SDCR[0]  = 0x00001954;\r\n  FMC_Bank5_6->SDTR[0]  = 0x01115351;\r\n  \r\n  /* SDRAM initialization sequence */\r\n  /* Clock enable command */\r\n  FMC_Bank5_6->SDCMR = 0x00000011; \r\n  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \r\n  while((tmpreg != 0) && (timeout-- > 0))\r\n  {\r\n    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \r\n  }\r\n\r\n  /* Delay */\r\n  for (index = 0; index<1000; index++);\r\n  \r\n  /* PALL command */\r\n  FMC_Bank5_6->SDCMR = 0x00000012;           \r\n  timeout = 0xFFFF;\r\n  while((tmpreg != 0) && (timeout-- > 0))\r\n  {\r\n    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \r\n  }\r\n  \r\n  /* Auto refresh command */\r\n  FMC_Bank5_6->SDCMR = 0x000000F3;\r\n  timeout = 0xFFFF;\r\n  while((tmpreg != 0) && (timeout-- > 0))\r\n  {\r\n    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \r\n  }\r\n \r\n  /* MRD register program */\r\n  FMC_Bank5_6->SDCMR = 0x00044014;\r\n  timeout = 0xFFFF;\r\n  while((tmpreg != 0) && (timeout-- > 0))\r\n  {\r\n    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \r\n  } \r\n  \r\n  /* Set refresh count */\r\n  tmpreg = FMC_Bank5_6->SDRTR;\r\n  FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));\r\n  \r\n  /* Disable write protection */\r\n  tmpreg = FMC_Bank5_6->SDCR[0]; \r\n  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);\r\n  \r\n  /*\r\n   * Disable the FMC bank1 (enabled after reset).\r\n   * This, prevents CPU speculation access on this bank which blocks the use of FMC during\r\n   * 24us. During this time the others FMC master (such as LTDC) cannot use it!\r\n   */\r\n  FMC_Bank1->BTCR[0] = 0x000030d2;\r\n}\r\n#endif /* DATA_IN_ExtSDRAM */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */    \r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/cfg/system_stm32f7xx.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    system_stm32f7xx.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   CMSIS Cortex-M7 Device System Source File for STM32F7xx devices.       \r\n  ******************************************************************************  \r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************  \r\n  */\r\n\r\n/** @addtogroup CMSIS\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup stm32f7xx_system\r\n  * @{\r\n  */  \r\n  \r\n/**\r\n  * @brief Define to prevent recursive inclusion\r\n  */\r\n#ifndef __SYSTEM_STM32F7XX_H\r\n#define __SYSTEM_STM32F7XX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif \r\n\r\n/** @addtogroup STM32F7xx_System_Includes\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @addtogroup STM32F7xx_System_Exported_Variables\r\n  * @{\r\n  */\r\n  /* The SystemCoreClock variable is updated in three ways:\r\n      1) by calling CMSIS function SystemCoreClockUpdate()\r\n      2) by calling HAL API function HAL_RCC_GetSysClockFreq()\r\n      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency \r\n         Note: If you use this function to configure the system clock; then there\r\n               is no need to call the 2 first functions listed above, since SystemCoreClock\r\n               variable is updated automatically.\r\n    */\r\nextern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */\r\n\r\nextern const uint8_t  AHBPrescTable[16];    /*!< AHB prescalers table values */\r\nextern const uint8_t  APBPrescTable[8];     /*!< APB prescalers table values */\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup STM32F7xx_System_Exported_Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup STM32F7xx_System_Exported_Macros\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup STM32F7xx_System_Exported_Functions\r\n  * @{\r\n  */\r\n  \r\nextern void SystemInit(void);\r\nextern void SystemCoreClockUpdate(void);\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /*__SYSTEM_STM32F7XX_H */\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */  \r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/include/arm_common_tables.h",
    "content": "/* ----------------------------------------------------------------------\r\n* Copyright (C) 2010-2014 ARM Limited. All rights reserved.\r\n*\r\n* $Date:        19. October 2015\r\n* $Revision: \tV.1.4.5 a\r\n*\r\n* Project: \t    CMSIS DSP Library\r\n* Title:\t    arm_common_tables.h\r\n*\r\n* Description:\tThis file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions\r\n*\r\n* Target Processor: Cortex-M4/Cortex-M3\r\n*\r\n* Redistribution and use in source and binary forms, with or without\r\n* modification, are permitted provided that the following conditions\r\n* are met:\r\n*   - Redistributions of source code must retain the above copyright\r\n*     notice, this list of conditions and the following disclaimer.\r\n*   - Redistributions in binary form must reproduce the above copyright\r\n*     notice, this list of conditions and the following disclaimer in\r\n*     the documentation and/or other materials provided with the\r\n*     distribution.\r\n*   - Neither the name of ARM LIMITED nor the names of its contributors\r\n*     may be used to endorse or promote products derived from this\r\n*     software without specific prior written permission.\r\n*\r\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\r\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\r\n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n* POSSIBILITY OF SUCH DAMAGE.\r\n* -------------------------------------------------------------------- */\r\n\r\n#ifndef _ARM_COMMON_TABLES_H\r\n#define _ARM_COMMON_TABLES_H\r\n\r\n#include \"arm_math.h\"\r\n\r\nextern const uint16_t armBitRevTable[1024];\r\nextern const q15_t armRecipTableQ15[64];\r\nextern const q31_t armRecipTableQ31[64];\r\n/* extern const q31_t realCoefAQ31[1024]; */\r\n/* extern const q31_t realCoefBQ31[1024]; */\r\nextern const float32_t twiddleCoef_16[32];\r\nextern const float32_t twiddleCoef_32[64];\r\nextern const float32_t twiddleCoef_64[128];\r\nextern const float32_t twiddleCoef_128[256];\r\nextern const float32_t twiddleCoef_256[512];\r\nextern const float32_t twiddleCoef_512[1024];\r\nextern const float32_t twiddleCoef_1024[2048];\r\nextern const float32_t twiddleCoef_2048[4096];\r\nextern const float32_t twiddleCoef_4096[8192];\r\n#define twiddleCoef twiddleCoef_4096\r\nextern const q31_t twiddleCoef_16_q31[24];\r\nextern const q31_t twiddleCoef_32_q31[48];\r\nextern const q31_t twiddleCoef_64_q31[96];\r\nextern const q31_t twiddleCoef_128_q31[192];\r\nextern const q31_t twiddleCoef_256_q31[384];\r\nextern const q31_t twiddleCoef_512_q31[768];\r\nextern const q31_t twiddleCoef_1024_q31[1536];\r\nextern const q31_t twiddleCoef_2048_q31[3072];\r\nextern const q31_t twiddleCoef_4096_q31[6144];\r\nextern const q15_t twiddleCoef_16_q15[24];\r\nextern const q15_t twiddleCoef_32_q15[48];\r\nextern const q15_t twiddleCoef_64_q15[96];\r\nextern const q15_t twiddleCoef_128_q15[192];\r\nextern const q15_t twiddleCoef_256_q15[384];\r\nextern const q15_t twiddleCoef_512_q15[768];\r\nextern const q15_t twiddleCoef_1024_q15[1536];\r\nextern const q15_t twiddleCoef_2048_q15[3072];\r\nextern const q15_t twiddleCoef_4096_q15[6144];\r\nextern const float32_t twiddleCoef_rfft_32[32];\r\nextern const float32_t twiddleCoef_rfft_64[64];\r\nextern const float32_t twiddleCoef_rfft_128[128];\r\nextern const float32_t twiddleCoef_rfft_256[256];\r\nextern const float32_t twiddleCoef_rfft_512[512];\r\nextern const float32_t twiddleCoef_rfft_1024[1024];\r\nextern const float32_t twiddleCoef_rfft_2048[2048];\r\nextern const float32_t twiddleCoef_rfft_4096[4096];\r\n\r\n\r\n/* floating-point bit reversal tables */\r\n#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )\r\n#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )\r\n#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )\r\n#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )\r\n#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )\r\n#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )\r\n#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)\r\n#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)\r\n#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)\r\n\r\nextern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];\r\nextern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];\r\nextern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];\r\nextern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];\r\nextern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];\r\nextern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];\r\nextern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];\r\nextern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];\r\nextern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];\r\n\r\n/* fixed-point bit reversal tables */\r\n#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )\r\n#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )\r\n#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )\r\n#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )\r\n#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )\r\n#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )\r\n#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )\r\n#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)\r\n#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)\r\n\r\nextern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];\r\nextern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];\r\nextern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];\r\nextern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];\r\nextern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];\r\nextern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];\r\nextern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];\r\nextern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];\r\nextern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];\r\n\r\n/* Tables for Fast Math Sine and Cosine */\r\nextern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];\r\nextern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];\r\nextern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];\r\n\r\n#endif /*  ARM_COMMON_TABLES_H */\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/include/arm_const_structs.h",
    "content": "/* ----------------------------------------------------------------------\r\n* Copyright (C) 2010-2014 ARM Limited. All rights reserved.\r\n*\r\n* $Date:        19. March 2015\r\n* $Revision: \tV.1.4.5\r\n*\r\n* Project: \t    CMSIS DSP Library\r\n* Title:\t    arm_const_structs.h\r\n*\r\n* Description:\tThis file has constant structs that are initialized for\r\n*              user convenience.  For example, some can be given as\r\n*              arguments to the arm_cfft_f32() function.\r\n*\r\n* Target Processor: Cortex-M4/Cortex-M3\r\n*\r\n* Redistribution and use in source and binary forms, with or without\r\n* modification, are permitted provided that the following conditions\r\n* are met:\r\n*   - Redistributions of source code must retain the above copyright\r\n*     notice, this list of conditions and the following disclaimer.\r\n*   - Redistributions in binary form must reproduce the above copyright\r\n*     notice, this list of conditions and the following disclaimer in\r\n*     the documentation and/or other materials provided with the\r\n*     distribution.\r\n*   - Neither the name of ARM LIMITED nor the names of its contributors\r\n*     may be used to endorse or promote products derived from this\r\n*     software without specific prior written permission.\r\n*\r\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\r\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\r\n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n* POSSIBILITY OF SUCH DAMAGE.\r\n* -------------------------------------------------------------------- */\r\n\r\n#ifndef _ARM_CONST_STRUCTS_H\r\n#define _ARM_CONST_STRUCTS_H\r\n\r\n#include \"arm_math.h\"\r\n#include \"arm_common_tables.h\"\r\n\r\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;\r\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;\r\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;\r\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;\r\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;\r\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;\r\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;\r\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;\r\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;\r\n\r\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;\r\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;\r\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;\r\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;\r\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;\r\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;\r\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;\r\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;\r\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;\r\n\r\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;\r\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;\r\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;\r\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;\r\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;\r\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;\r\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;\r\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;\r\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;\r\n\r\n#endif\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/include/arm_math.h",
    "content": "/* ----------------------------------------------------------------------\r\n* Copyright (C) 2010-2015 ARM Limited. All rights reserved.\r\n*\r\n* $Date:        20. October 2015\r\n* $Revision:    V1.4.5 b\r\n*\r\n* Project:      CMSIS DSP Library\r\n* Title:        arm_math.h\r\n*\r\n* Description:  Public header file for CMSIS DSP Library\r\n*\r\n* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0\r\n*\r\n* Redistribution and use in source and binary forms, with or without\r\n* modification, are permitted provided that the following conditions\r\n* are met:\r\n*   - Redistributions of source code must retain the above copyright\r\n*     notice, this list of conditions and the following disclaimer.\r\n*   - Redistributions in binary form must reproduce the above copyright\r\n*     notice, this list of conditions and the following disclaimer in\r\n*     the documentation and/or other materials provided with the\r\n*     distribution.\r\n*   - Neither the name of ARM LIMITED nor the names of its contributors\r\n*     may be used to endorse or promote products derived from this\r\n*     software without specific prior written permission.\r\n*\r\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\r\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\r\n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n* POSSIBILITY OF SUCH DAMAGE.\r\n * -------------------------------------------------------------------- */\r\n\r\n/**\r\n   \\mainpage CMSIS DSP Software Library\r\n   *\r\n   * Introduction\r\n   * ------------\r\n   *\r\n   * This user manual describes the CMSIS DSP software library,\r\n   * a suite of common signal processing functions for use on Cortex-M processor based devices.\r\n   *\r\n   * The library is divided into a number of functions each covering a specific category:\r\n   * - Basic math functions\r\n   * - Fast math functions\r\n   * - Complex math functions\r\n   * - Filters\r\n   * - Matrix functions\r\n   * - Transforms\r\n   * - Motor control functions\r\n   * - Statistical functions\r\n   * - Support functions\r\n   * - Interpolation functions\r\n   *\r\n   * The library has separate functions for operating on 8-bit integers, 16-bit integers,\r\n   * 32-bit integer and 32-bit floating-point values.\r\n   *\r\n   * Using the Library\r\n   * ------------\r\n   *\r\n   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.\r\n   * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7)\r\n   * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7)\r\n   * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7)\r\n   * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7)\r\n   * - arm_cortexM7l_math.lib (Little endian on Cortex-M7)\r\n   * - arm_cortexM7b_math.lib (Big endian on Cortex-M7)\r\n   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)\r\n   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)\r\n   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)\r\n   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)\r\n   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)\r\n   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)\r\n   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+)\r\n   * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+)\r\n   *\r\n   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.\r\n   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single\r\n   * public header file <code> arm_math.h</code> for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.\r\n   * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or  ARM_MATH_CM3 or\r\n   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.\r\n   *\r\n   * Examples\r\n   * --------\r\n   *\r\n   * The library ships with a number of examples which demonstrate how to use the library functions.\r\n   *\r\n   * Toolchain Support\r\n   * ------------\r\n   *\r\n   * The library has been developed and tested with MDK-ARM version 5.14.0.0\r\n   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.\r\n   *\r\n   * Building the Library\r\n   * ------------\r\n   *\r\n   * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\\\DSP_Lib\\\\Source\\\\ARM</code> folder.\r\n   * - arm_cortexM_math.uvprojx\r\n   *\r\n   *\r\n   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.\r\n   *\r\n   * Pre-processor Macros\r\n   * ------------\r\n   *\r\n   * Each library project have differant pre-processor macros.\r\n   *\r\n   * - UNALIGNED_SUPPORT_DISABLE:\r\n   *\r\n   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access\r\n   *\r\n   * - ARM_MATH_BIG_ENDIAN:\r\n   *\r\n   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.\r\n   *\r\n   * - ARM_MATH_MATRIX_CHECK:\r\n   *\r\n   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices\r\n   *\r\n   * - ARM_MATH_ROUNDING:\r\n   *\r\n   * Define macro ARM_MATH_ROUNDING for rounding on support functions\r\n   *\r\n   * - ARM_MATH_CMx:\r\n   *\r\n   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target\r\n   * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and\r\n   * ARM_MATH_CM7 for building the library on cortex-M7.\r\n   *\r\n   * - __FPU_PRESENT:\r\n   *\r\n   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries\r\n   *\r\n   * <hr>\r\n   * CMSIS-DSP in ARM::CMSIS Pack\r\n   * -----------------------------\r\n   *\r\n   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:\r\n   * |File/Folder                   |Content                                                                 |\r\n   * |------------------------------|------------------------------------------------------------------------|\r\n   * |\\b CMSIS\\\\Documentation\\\\DSP  | This documentation                                                     |\r\n   * |\\b CMSIS\\\\DSP_Lib             | Software license agreement (license.txt)                               |\r\n   * |\\b CMSIS\\\\DSP_Lib\\\\Examples   | Example projects demonstrating the usage of the library functions      |\r\n   * |\\b CMSIS\\\\DSP_Lib\\\\Source     | Source files for rebuilding the library                                |\r\n   *\r\n   * <hr>\r\n   * Revision History of CMSIS-DSP\r\n   * ------------\r\n   * Please refer to \\ref ChangeLog_pg.\r\n   *\r\n   * Copyright Notice\r\n   * ------------\r\n   *\r\n   * Copyright (C) 2010-2015 ARM Limited. All rights reserved.\r\n   */\r\n\r\n\r\n/**\r\n * @defgroup groupMath Basic Math Functions\r\n */\r\n\r\n/**\r\n * @defgroup groupFastMath Fast Math Functions\r\n * This set of functions provides a fast approximation to sine, cosine, and square root.\r\n * As compared to most of the other functions in the CMSIS math library, the fast math functions\r\n * operate on individual values and not arrays.\r\n * There are separate functions for Q15, Q31, and floating-point data.\r\n *\r\n */\r\n\r\n/**\r\n * @defgroup groupCmplxMath Complex Math Functions\r\n * This set of functions operates on complex data vectors.\r\n * The data in the complex arrays is stored in an interleaved fashion\r\n * (real, imag, real, imag, ...).\r\n * In the API functions, the number of samples in a complex array refers\r\n * to the number of complex values; the array contains twice this number of\r\n * real values.\r\n */\r\n\r\n/**\r\n * @defgroup groupFilters Filtering Functions\r\n */\r\n\r\n/**\r\n * @defgroup groupMatrix Matrix Functions\r\n *\r\n * This set of functions provides basic matrix math operations.\r\n * The functions operate on matrix data structures.  For example,\r\n * the type\r\n * definition for the floating-point matrix structure is shown\r\n * below:\r\n * <pre>\r\n *     typedef struct\r\n *     {\r\n *       uint16_t numRows;     // number of rows of the matrix.\r\n *       uint16_t numCols;     // number of columns of the matrix.\r\n *       float32_t *pData;     // points to the data of the matrix.\r\n *     } arm_matrix_instance_f32;\r\n * </pre>\r\n * There are similar definitions for Q15 and Q31 data types.\r\n *\r\n * The structure specifies the size of the matrix and then points to\r\n * an array of data.  The array is of size <code>numRows X numCols</code>\r\n * and the values are arranged in row order.  That is, the\r\n * matrix element (i, j) is stored at:\r\n * <pre>\r\n *     pData[i*numCols + j]\r\n * </pre>\r\n *\r\n * \\par Init Functions\r\n * There is an associated initialization function for each type of matrix\r\n * data structure.\r\n * The initialization function sets the values of the internal structure fields.\r\n * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>\r\n * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.\r\n *\r\n * \\par\r\n * Use of the initialization function is optional. However, if initialization function is used\r\n * then the instance structure cannot be placed into a const data section.\r\n * To place the instance structure in a const data\r\n * section, manually initialize the data structure.  For example:\r\n * <pre>\r\n * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>\r\n * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>\r\n * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>\r\n * </pre>\r\n * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>\r\n * specifies the number of columns, and <code>pData</code> points to the\r\n * data array.\r\n *\r\n * \\par Size Checking\r\n * By default all of the matrix functions perform size checking on the input and\r\n * output matrices.  For example, the matrix addition function verifies that the\r\n * two input matrices and the output matrix all have the same number of rows and\r\n * columns.  If the size check fails the functions return:\r\n * <pre>\r\n *     ARM_MATH_SIZE_MISMATCH\r\n * </pre>\r\n * Otherwise the functions return\r\n * <pre>\r\n *     ARM_MATH_SUCCESS\r\n * </pre>\r\n * There is some overhead associated with this matrix size checking.\r\n * The matrix size checking is enabled via the \\#define\r\n * <pre>\r\n *     ARM_MATH_MATRIX_CHECK\r\n * </pre>\r\n * within the library project settings.  By default this macro is defined\r\n * and size checking is enabled.  By changing the project settings and\r\n * undefining this macro size checking is eliminated and the functions\r\n * run a bit faster.  With size checking disabled the functions always\r\n * return <code>ARM_MATH_SUCCESS</code>.\r\n */\r\n\r\n/**\r\n * @defgroup groupTransforms Transform Functions\r\n */\r\n\r\n/**\r\n * @defgroup groupController Controller Functions\r\n */\r\n\r\n/**\r\n * @defgroup groupStats Statistics Functions\r\n */\r\n/**\r\n * @defgroup groupSupport Support Functions\r\n */\r\n\r\n/**\r\n * @defgroup groupInterpolation Interpolation Functions\r\n * These functions perform 1- and 2-dimensional interpolation of data.\r\n * Linear interpolation is used for 1-dimensional data and\r\n * bilinear interpolation is used for 2-dimensional data.\r\n */\r\n\r\n/**\r\n * @defgroup groupExamples Examples\r\n */\r\n#ifndef _ARM_MATH_H\r\n#define _ARM_MATH_H\r\n\r\n/* ignore some GCC warnings */\r\n#if defined ( __GNUC__ )\r\n#pragma GCC diagnostic push\r\n#pragma GCC diagnostic ignored \"-Wsign-conversion\"\r\n#pragma GCC diagnostic ignored \"-Wconversion\"\r\n#pragma GCC diagnostic ignored \"-Wunused-parameter\"\r\n#endif\r\n\r\n#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */\r\n\r\n#if defined(ARM_MATH_CM7)\r\n  #include \"core_cm7.h\"\r\n#elif defined (ARM_MATH_CM4)\r\n  #include \"core_cm4.h\"\r\n#elif defined (ARM_MATH_CM3)\r\n  #include \"core_cm3.h\"\r\n#elif defined (ARM_MATH_CM0)\r\n  #include \"core_cm0.h\"\r\n  #define ARM_MATH_CM0_FAMILY\r\n#elif defined (ARM_MATH_CM0PLUS)\r\n  #include \"core_cm0plus.h\"\r\n  #define ARM_MATH_CM0_FAMILY\r\n#else\r\n  #error \"Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0\"\r\n#endif\r\n\r\n#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */\r\n#include \"string.h\"\r\n#include \"math.h\"\r\n#ifdef   __cplusplus\r\nextern \"C\"\r\n{\r\n#endif\r\n\r\n\r\n  /**\r\n   * @brief Macros required for reciprocal calculation in Normalized LMS\r\n   */\r\n\r\n#define DELTA_Q31          (0x100)\r\n#define DELTA_Q15          0x5\r\n#define INDEX_MASK         0x0000003F\r\n#ifndef PI\r\n#define PI                 3.14159265358979f\r\n#endif\r\n\r\n  /**\r\n   * @brief Macros required for SINE and COSINE Fast math approximations\r\n   */\r\n\r\n#define FAST_MATH_TABLE_SIZE  512\r\n#define FAST_MATH_Q31_SHIFT   (32 - 10)\r\n#define FAST_MATH_Q15_SHIFT   (16 - 10)\r\n#define CONTROLLER_Q31_SHIFT  (32 - 9)\r\n#define TABLE_SIZE  256\r\n#define TABLE_SPACING_Q31     0x400000\r\n#define TABLE_SPACING_Q15     0x80\r\n\r\n  /**\r\n   * @brief Macros required for SINE and COSINE Controller functions\r\n   */\r\n  /* 1.31(q31) Fixed value of 2/360 */\r\n  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */\r\n#define INPUT_SPACING         0xB60B61\r\n\r\n  /**\r\n   * @brief Macro for Unaligned Support\r\n   */\r\n#ifndef UNALIGNED_SUPPORT_DISABLE\r\n    #define ALIGN4\r\n#else\r\n  #if defined  (__GNUC__)\r\n    #define ALIGN4 __attribute__((aligned(4)))\r\n  #else\r\n    #define ALIGN4 __align(4)\r\n  #endif\r\n#endif   /* #ifndef UNALIGNED_SUPPORT_DISABLE */\r\n\r\n  /**\r\n   * @brief Error status returned by some functions in the library.\r\n   */\r\n\r\n  typedef enum\r\n  {\r\n    ARM_MATH_SUCCESS = 0,                /**< No error */\r\n    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */\r\n    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */\r\n    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */\r\n    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */\r\n    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */\r\n    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */\r\n  } arm_status;\r\n\r\n  /**\r\n   * @brief 8-bit fractional data type in 1.7 format.\r\n   */\r\n  typedef int8_t q7_t;\r\n\r\n  /**\r\n   * @brief 16-bit fractional data type in 1.15 format.\r\n   */\r\n  typedef int16_t q15_t;\r\n\r\n  /**\r\n   * @brief 32-bit fractional data type in 1.31 format.\r\n   */\r\n  typedef int32_t q31_t;\r\n\r\n  /**\r\n   * @brief 64-bit fractional data type in 1.63 format.\r\n   */\r\n  typedef int64_t q63_t;\r\n\r\n  /**\r\n   * @brief 32-bit floating-point type definition.\r\n   */\r\n  typedef float float32_t;\r\n\r\n  /**\r\n   * @brief 64-bit floating-point type definition.\r\n   */\r\n  typedef double float64_t;\r\n\r\n  /**\r\n   * @brief definition to read/write two 16 bit values.\r\n   */\r\n#if defined __CC_ARM\r\n  #define __SIMD32_TYPE int32_t __packed\r\n  #define CMSIS_UNUSED __attribute__((unused))\r\n\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #define __SIMD32_TYPE int32_t\r\n  #define CMSIS_UNUSED __attribute__((unused))\r\n\r\n#elif defined __GNUC__\r\n  #define __SIMD32_TYPE int32_t\r\n  #define CMSIS_UNUSED __attribute__((unused))\r\n\r\n#elif defined __ICCARM__\r\n  #define __SIMD32_TYPE int32_t __packed\r\n  #define CMSIS_UNUSED\r\n\r\n#elif defined __CSMC__\r\n  #define __SIMD32_TYPE int32_t\r\n  #define CMSIS_UNUSED\r\n\r\n#elif defined __TASKING__\r\n  #define __SIMD32_TYPE __unaligned int32_t\r\n  #define CMSIS_UNUSED\r\n\r\n#else\r\n  #error Unknown compiler\r\n#endif\r\n\r\n#define __SIMD32(addr)        (*(__SIMD32_TYPE **) & (addr))\r\n#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))\r\n#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))\r\n#define __SIMD64(addr)        (*(int64_t **) & (addr))\r\n\r\n#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)\r\n  /**\r\n   * @brief definition to pack two 16 bit values.\r\n   */\r\n#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \\\r\n                                         (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )\r\n#define __PKHTB(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0xFFFF0000) | \\\r\n                                         (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )\r\n\r\n#endif\r\n\r\n\r\n   /**\r\n   * @brief definition to pack four 8 bit values.\r\n   */\r\n#ifndef ARM_MATH_BIG_ENDIAN\r\n\r\n#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) | \\\r\n                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) | \\\r\n                                (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \\\r\n                                (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )\r\n#else\r\n\r\n#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) | \\\r\n                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) | \\\r\n                                (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \\\r\n                                (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )\r\n\r\n#endif\r\n\r\n\r\n  /**\r\n   * @brief Clips Q63 to Q31 values.\r\n   */\r\n  static __INLINE q31_t clip_q63_to_q31(\r\n  q63_t x)\r\n  {\r\n    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\r\n      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;\r\n  }\r\n\r\n  /**\r\n   * @brief Clips Q63 to Q15 values.\r\n   */\r\n  static __INLINE q15_t clip_q63_to_q15(\r\n  q63_t x)\r\n  {\r\n    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\r\n      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);\r\n  }\r\n\r\n  /**\r\n   * @brief Clips Q31 to Q7 values.\r\n   */\r\n  static __INLINE q7_t clip_q31_to_q7(\r\n  q31_t x)\r\n  {\r\n    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?\r\n      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;\r\n  }\r\n\r\n  /**\r\n   * @brief Clips Q31 to Q15 values.\r\n   */\r\n  static __INLINE q15_t clip_q31_to_q15(\r\n  q31_t x)\r\n  {\r\n    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?\r\n      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;\r\n  }\r\n\r\n  /**\r\n   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.\r\n   */\r\n\r\n  static __INLINE q63_t mult32x64(\r\n  q63_t x,\r\n  q31_t y)\r\n  {\r\n    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +\r\n            (((q63_t) (x >> 32) * y)));\r\n  }\r\n\r\n/*\r\n  #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )\r\n  #define __CLZ __clz\r\n  #endif\r\n */\r\n/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */\r\n#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__))  )\r\n  static __INLINE uint32_t __CLZ(\r\n  q31_t data);\r\n\r\n  static __INLINE uint32_t __CLZ(\r\n  q31_t data)\r\n  {\r\n    uint32_t count = 0;\r\n    uint32_t mask = 0x80000000;\r\n\r\n    while((data & mask) == 0)\r\n    {\r\n      count += 1u;\r\n      mask = mask >> 1u;\r\n    }\r\n\r\n    return (count);\r\n  }\r\n#endif\r\n\r\n  /**\r\n   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.\r\n   */\r\n\r\n  static __INLINE uint32_t arm_recip_q31(\r\n  q31_t in,\r\n  q31_t * dst,\r\n  q31_t * pRecipTable)\r\n  {\r\n    q31_t out;\r\n    uint32_t tempVal;\r\n    uint32_t index, i;\r\n    uint32_t signBits;\r\n\r\n    if(in > 0)\r\n    {\r\n      signBits = ((uint32_t) (__CLZ( in) - 1));\r\n    }\r\n    else\r\n    {\r\n      signBits = ((uint32_t) (__CLZ(-in) - 1));\r\n    }\r\n\r\n    /* Convert input sample to 1.31 format */\r\n    in = (in << signBits);\r\n\r\n    /* calculation of index for initial approximated Val */\r\n    index = (uint32_t)(in >> 24);\r\n    index = (index & INDEX_MASK);\r\n\r\n    /* 1.31 with exp 1 */\r\n    out = pRecipTable[index];\r\n\r\n    /* calculation of reciprocal value */\r\n    /* running approximation for two iterations */\r\n    for (i = 0u; i < 2u; i++)\r\n    {\r\n      tempVal = (uint32_t) (((q63_t) in * out) >> 31);\r\n      tempVal = 0x7FFFFFFFu - tempVal;\r\n      /*      1.31 with exp 1 */\r\n      /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */\r\n      out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);\r\n    }\r\n\r\n    /* write output */\r\n    *dst = out;\r\n\r\n    /* return num of signbits of out = 1/in value */\r\n    return (signBits + 1u);\r\n  }\r\n\r\n\r\n  /**\r\n   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.\r\n   */\r\n  static __INLINE uint32_t arm_recip_q15(\r\n  q15_t in,\r\n  q15_t * dst,\r\n  q15_t * pRecipTable)\r\n  {\r\n    q15_t out = 0;\r\n    uint32_t tempVal = 0;\r\n    uint32_t index = 0, i = 0;\r\n    uint32_t signBits = 0;\r\n\r\n    if(in > 0)\r\n    {\r\n      signBits = ((uint32_t)(__CLZ( in) - 17));\r\n    }\r\n    else\r\n    {\r\n      signBits = ((uint32_t)(__CLZ(-in) - 17));\r\n    }\r\n\r\n    /* Convert input sample to 1.15 format */\r\n    in = (in << signBits);\r\n\r\n    /* calculation of index for initial approximated Val */\r\n    index = (uint32_t)(in >>  8);\r\n    index = (index & INDEX_MASK);\r\n\r\n    /*      1.15 with exp 1  */\r\n    out = pRecipTable[index];\r\n\r\n    /* calculation of reciprocal value */\r\n    /* running approximation for two iterations */\r\n    for (i = 0u; i < 2u; i++)\r\n    {\r\n      tempVal = (uint32_t) (((q31_t) in * out) >> 15);\r\n      tempVal = 0x7FFFu - tempVal;\r\n      /*      1.15 with exp 1 */\r\n      out = (q15_t) (((q31_t) out * tempVal) >> 14);\r\n      /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */\r\n    }\r\n\r\n    /* write output */\r\n    *dst = out;\r\n\r\n    /* return num of signbits of out = 1/in value */\r\n    return (signBits + 1);\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined intrinisic function for only M0 processors\r\n   */\r\n#if defined(ARM_MATH_CM0_FAMILY)\r\n  static __INLINE q31_t __SSAT(\r\n  q31_t x,\r\n  uint32_t y)\r\n  {\r\n    int32_t posMax, negMin;\r\n    uint32_t i;\r\n\r\n    posMax = 1;\r\n    for (i = 0; i < (y - 1); i++)\r\n    {\r\n      posMax = posMax * 2;\r\n    }\r\n\r\n    if(x > 0)\r\n    {\r\n      posMax = (posMax - 1);\r\n\r\n      if(x > posMax)\r\n      {\r\n        x = posMax;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      negMin = -posMax;\r\n\r\n      if(x < negMin)\r\n      {\r\n        x = negMin;\r\n      }\r\n    }\r\n    return (x);\r\n  }\r\n#endif /* end of ARM_MATH_CM0_FAMILY */\r\n\r\n\r\n  /*\r\n   * @brief C custom defined intrinsic function for M3 and M0 processors\r\n   */\r\n#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)\r\n\r\n  /*\r\n   * @brief C custom defined QADD8 for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __QADD8(\r\n  uint32_t x,\r\n  uint32_t y)\r\n  {\r\n    q31_t r, s, t, u;\r\n\r\n    r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;\r\n    s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;\r\n    t = __SSAT(((((q31_t)x <<  8) >> 24) + (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;\r\n    u = __SSAT(((((q31_t)x      ) >> 24) + (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;\r\n\r\n    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined QSUB8 for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __QSUB8(\r\n  uint32_t x,\r\n  uint32_t y)\r\n  {\r\n    q31_t r, s, t, u;\r\n\r\n    r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;\r\n    s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;\r\n    t = __SSAT(((((q31_t)x <<  8) >> 24) - (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;\r\n    u = __SSAT(((((q31_t)x      ) >> 24) - (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;\r\n\r\n    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined QADD16 for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __QADD16(\r\n  uint32_t x,\r\n  uint32_t y)\r\n  {\r\n/*  q31_t r,     s;  without initialisation 'arm_offset_q15 test' fails  but 'intrinsic' tests pass! for armCC */\r\n    q31_t r = 0, s = 0;\r\n\r\n    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\r\n    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;\r\n\r\n    return ((uint32_t)((s << 16) | (r      )));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined SHADD16 for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __SHADD16(\r\n  uint32_t x,\r\n  uint32_t y)\r\n  {\r\n    q31_t r, s;\r\n\r\n    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r\n    s = (((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r\n\r\n    return ((uint32_t)((s << 16) | (r      )));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined QSUB16 for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __QSUB16(\r\n  uint32_t x,\r\n  uint32_t y)\r\n  {\r\n    q31_t r, s;\r\n\r\n    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\r\n    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;\r\n\r\n    return ((uint32_t)((s << 16) | (r      )));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined SHSUB16 for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __SHSUB16(\r\n  uint32_t x,\r\n  uint32_t y)\r\n  {\r\n    q31_t r, s;\r\n\r\n    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r\n    s = (((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r\n\r\n    return ((uint32_t)((s << 16) | (r      )));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined QASX for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __QASX(\r\n  uint32_t x,\r\n  uint32_t y)\r\n  {\r\n    q31_t r, s;\r\n\r\n    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;\r\n    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\r\n\r\n    return ((uint32_t)((s << 16) | (r      )));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined SHASX for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __SHASX(\r\n  uint32_t x,\r\n  uint32_t y)\r\n  {\r\n    q31_t r, s;\r\n\r\n    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r\n    s = (((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r\n\r\n    return ((uint32_t)((s << 16) | (r      )));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined QSAX for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __QSAX(\r\n  uint32_t x,\r\n  uint32_t y)\r\n  {\r\n    q31_t r, s;\r\n\r\n    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;\r\n    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\r\n\r\n    return ((uint32_t)((s << 16) | (r      )));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined SHSAX for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __SHSAX(\r\n  uint32_t x,\r\n  uint32_t y)\r\n  {\r\n    q31_t r, s;\r\n\r\n    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r\n    s = (((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r\n\r\n    return ((uint32_t)((s << 16) | (r      )));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined SMUSDX for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __SMUSDX(\r\n  uint32_t x,\r\n  uint32_t y)\r\n  {\r\n    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -\r\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));\r\n  }\r\n\r\n  /*\r\n   * @brief C custom defined SMUADX for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __SMUADX(\r\n  uint32_t x,\r\n  uint32_t y)\r\n  {\r\n    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +\r\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined QADD for M3 and M0 processors\r\n   */\r\n  static __INLINE int32_t __QADD(\r\n  int32_t x,\r\n  int32_t y)\r\n  {\r\n    return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined QSUB for M3 and M0 processors\r\n   */\r\n  static __INLINE int32_t __QSUB(\r\n  int32_t x,\r\n  int32_t y)\r\n  {\r\n    return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined SMLAD for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __SMLAD(\r\n  uint32_t x,\r\n  uint32_t y,\r\n  uint32_t sum)\r\n  {\r\n    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +\r\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +\r\n                       ( ((q31_t)sum    )                                  )   ));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined SMLADX for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __SMLADX(\r\n  uint32_t x,\r\n  uint32_t y,\r\n  uint32_t sum)\r\n  {\r\n    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +\r\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +\r\n                       ( ((q31_t)sum    )                                  )   ));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined SMLSDX for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __SMLSDX(\r\n  uint32_t x,\r\n  uint32_t y,\r\n  uint32_t sum)\r\n  {\r\n    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -\r\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +\r\n                       ( ((q31_t)sum    )                                  )   ));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined SMLALD for M3 and M0 processors\r\n   */\r\n  static __INLINE uint64_t __SMLALD(\r\n  uint32_t x,\r\n  uint32_t y,\r\n  uint64_t sum)\r\n  {\r\n/*  return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */\r\n    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +\r\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +\r\n                       ( ((q63_t)sum    )                                  )   ));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined SMLALDX for M3 and M0 processors\r\n   */\r\n  static __INLINE uint64_t __SMLALDX(\r\n  uint32_t x,\r\n  uint32_t y,\r\n  uint64_t sum)\r\n  {\r\n/*  return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */\r\n    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +\r\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +\r\n                       ( ((q63_t)sum    )                                  )   ));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined SMUAD for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __SMUAD(\r\n  uint32_t x,\r\n  uint32_t y)\r\n  {\r\n    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +\r\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined SMUSD for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __SMUSD(\r\n  uint32_t x,\r\n  uint32_t y)\r\n  {\r\n    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -\r\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));\r\n  }\r\n\r\n\r\n  /*\r\n   * @brief C custom defined SXTB16 for M3 and M0 processors\r\n   */\r\n  static __INLINE uint32_t __SXTB16(\r\n  uint32_t x)\r\n  {\r\n    return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |\r\n                       ((((q31_t)x <<  8) >>  8) & (q31_t)0xFFFF0000)  ));\r\n  }\r\n\r\n#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the Q7 FIR filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numTaps;        /**< number of filter coefficients in the filter. */\r\n    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/\r\n  } arm_fir_instance_q7;\r\n\r\n  /**\r\n   * @brief Instance structure for the Q15 FIR filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numTaps;         /**< number of filter coefficients in the filter. */\r\n    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/\r\n  } arm_fir_instance_q15;\r\n\r\n  /**\r\n   * @brief Instance structure for the Q31 FIR filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numTaps;         /**< number of filter coefficients in the filter. */\r\n    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */\r\n  } arm_fir_instance_q31;\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point FIR filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numTaps;     /**< number of filter coefficients in the filter. */\r\n    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */\r\n  } arm_fir_instance_f32;\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q7 FIR filter.\r\n   * @param[in]  S          points to an instance of the Q7 FIR filter structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_fir_q7(\r\n  const arm_fir_instance_q7 * S,\r\n  q7_t * pSrc,\r\n  q7_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the Q7 FIR filter.\r\n   * @param[in,out] S          points to an instance of the Q7 FIR structure.\r\n   * @param[in]     numTaps    Number of filter coefficients in the filter.\r\n   * @param[in]     pCoeffs    points to the filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   * @param[in]     blockSize  number of samples that are processed.\r\n   */\r\n  void arm_fir_init_q7(\r\n  arm_fir_instance_q7 * S,\r\n  uint16_t numTaps,\r\n  q7_t * pCoeffs,\r\n  q7_t * pState,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q15 FIR filter.\r\n   * @param[in]  S          points to an instance of the Q15 FIR structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_fir_q15(\r\n  const arm_fir_instance_q15 * S,\r\n  q15_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.\r\n   * @param[in]  S          points to an instance of the Q15 FIR filter structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_fir_fast_q15(\r\n  const arm_fir_instance_q15 * S,\r\n  q15_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the Q15 FIR filter.\r\n   * @param[in,out] S          points to an instance of the Q15 FIR filter structure.\r\n   * @param[in]     numTaps    Number of filter coefficients in the filter. Must be even and greater than or equal to 4.\r\n   * @param[in]     pCoeffs    points to the filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   * @param[in]     blockSize  number of samples that are processed at a time.\r\n   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if\r\n   * <code>numTaps</code> is not a supported value.\r\n   */\r\n  arm_status arm_fir_init_q15(\r\n  arm_fir_instance_q15 * S,\r\n  uint16_t numTaps,\r\n  q15_t * pCoeffs,\r\n  q15_t * pState,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q31 FIR filter.\r\n   * @param[in]  S          points to an instance of the Q31 FIR filter structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_fir_q31(\r\n  const arm_fir_instance_q31 * S,\r\n  q31_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.\r\n   * @param[in]  S          points to an instance of the Q31 FIR structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_fir_fast_q31(\r\n  const arm_fir_instance_q31 * S,\r\n  q31_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the Q31 FIR filter.\r\n   * @param[in,out] S          points to an instance of the Q31 FIR structure.\r\n   * @param[in]     numTaps    Number of filter coefficients in the filter.\r\n   * @param[in]     pCoeffs    points to the filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   * @param[in]     blockSize  number of samples that are processed at a time.\r\n   */\r\n  void arm_fir_init_q31(\r\n  arm_fir_instance_q31 * S,\r\n  uint16_t numTaps,\r\n  q31_t * pCoeffs,\r\n  q31_t * pState,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the floating-point FIR filter.\r\n   * @param[in]  S          points to an instance of the floating-point FIR structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_fir_f32(\r\n  const arm_fir_instance_f32 * S,\r\n  float32_t * pSrc,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the floating-point FIR filter.\r\n   * @param[in,out] S          points to an instance of the floating-point FIR filter structure.\r\n   * @param[in]     numTaps    Number of filter coefficients in the filter.\r\n   * @param[in]     pCoeffs    points to the filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   * @param[in]     blockSize  number of samples that are processed at a time.\r\n   */\r\n  void arm_fir_init_f32(\r\n  arm_fir_instance_f32 * S,\r\n  uint16_t numTaps,\r\n  float32_t * pCoeffs,\r\n  float32_t * pState,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the Q15 Biquad cascade filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    int8_t numStages;        /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */\r\n    q15_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */\r\n    q15_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */\r\n    int8_t postShift;        /**< Additional shift, in bits, applied to each output sample. */\r\n  } arm_biquad_casd_df1_inst_q15;\r\n\r\n  /**\r\n   * @brief Instance structure for the Q31 Biquad cascade filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */\r\n    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */\r\n    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */\r\n    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */\r\n  } arm_biquad_casd_df1_inst_q31;\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point Biquad cascade filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */\r\n    float32_t *pState;       /**< Points to the array of state coefficients.  The array is of length 4*numStages. */\r\n    float32_t *pCoeffs;      /**< Points to the array of coefficients.  The array is of length 5*numStages. */\r\n  } arm_biquad_casd_df1_inst_f32;\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q15 Biquad cascade filter.\r\n   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_biquad_cascade_df1_q15(\r\n  const arm_biquad_casd_df1_inst_q15 * S,\r\n  q15_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the Q15 Biquad cascade filter.\r\n   * @param[in,out] S          points to an instance of the Q15 Biquad cascade structure.\r\n   * @param[in]     numStages  number of 2nd order stages in the filter.\r\n   * @param[in]     pCoeffs    points to the filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format\r\n   */\r\n  void arm_biquad_cascade_df1_init_q15(\r\n  arm_biquad_casd_df1_inst_q15 * S,\r\n  uint8_t numStages,\r\n  q15_t * pCoeffs,\r\n  q15_t * pState,\r\n  int8_t postShift);\r\n\r\n\r\n  /**\r\n   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.\r\n   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_biquad_cascade_df1_fast_q15(\r\n  const arm_biquad_casd_df1_inst_q15 * S,\r\n  q15_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q31 Biquad cascade filter\r\n   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_biquad_cascade_df1_q31(\r\n  const arm_biquad_casd_df1_inst_q31 * S,\r\n  q31_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.\r\n   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_biquad_cascade_df1_fast_q31(\r\n  const arm_biquad_casd_df1_inst_q31 * S,\r\n  q31_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the Q31 Biquad cascade filter.\r\n   * @param[in,out] S          points to an instance of the Q31 Biquad cascade structure.\r\n   * @param[in]     numStages  number of 2nd order stages in the filter.\r\n   * @param[in]     pCoeffs    points to the filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format\r\n   */\r\n  void arm_biquad_cascade_df1_init_q31(\r\n  arm_biquad_casd_df1_inst_q31 * S,\r\n  uint8_t numStages,\r\n  q31_t * pCoeffs,\r\n  q31_t * pState,\r\n  int8_t postShift);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the floating-point Biquad cascade filter.\r\n   * @param[in]  S          points to an instance of the floating-point Biquad cascade structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_biquad_cascade_df1_f32(\r\n  const arm_biquad_casd_df1_inst_f32 * S,\r\n  float32_t * pSrc,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the floating-point Biquad cascade filter.\r\n   * @param[in,out] S          points to an instance of the floating-point Biquad cascade structure.\r\n   * @param[in]     numStages  number of 2nd order stages in the filter.\r\n   * @param[in]     pCoeffs    points to the filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   */\r\n  void arm_biquad_cascade_df1_init_f32(\r\n  arm_biquad_casd_df1_inst_f32 * S,\r\n  uint8_t numStages,\r\n  float32_t * pCoeffs,\r\n  float32_t * pState);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point matrix structure.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numRows;     /**< number of rows of the matrix.     */\r\n    uint16_t numCols;     /**< number of columns of the matrix.  */\r\n    float32_t *pData;     /**< points to the data of the matrix. */\r\n  } arm_matrix_instance_f32;\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point matrix structure.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numRows;     /**< number of rows of the matrix.     */\r\n    uint16_t numCols;     /**< number of columns of the matrix.  */\r\n    float64_t *pData;     /**< points to the data of the matrix. */\r\n  } arm_matrix_instance_f64;\r\n\r\n  /**\r\n   * @brief Instance structure for the Q15 matrix structure.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numRows;     /**< number of rows of the matrix.     */\r\n    uint16_t numCols;     /**< number of columns of the matrix.  */\r\n    q15_t *pData;         /**< points to the data of the matrix. */\r\n  } arm_matrix_instance_q15;\r\n\r\n  /**\r\n   * @brief Instance structure for the Q31 matrix structure.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numRows;     /**< number of rows of the matrix.     */\r\n    uint16_t numCols;     /**< number of columns of the matrix.  */\r\n    q31_t *pData;         /**< points to the data of the matrix. */\r\n  } arm_matrix_instance_q31;\r\n\r\n\r\n  /**\r\n   * @brief Floating-point matrix addition.\r\n   * @param[in]  pSrcA  points to the first input matrix structure\r\n   * @param[in]  pSrcB  points to the second input matrix structure\r\n   * @param[out] pDst   points to output matrix structure\r\n   * @return     The function returns either\r\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_add_f32(\r\n  const arm_matrix_instance_f32 * pSrcA,\r\n  const arm_matrix_instance_f32 * pSrcB,\r\n  arm_matrix_instance_f32 * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Q15 matrix addition.\r\n   * @param[in]   pSrcA  points to the first input matrix structure\r\n   * @param[in]   pSrcB  points to the second input matrix structure\r\n   * @param[out]  pDst   points to output matrix structure\r\n   * @return     The function returns either\r\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_add_q15(\r\n  const arm_matrix_instance_q15 * pSrcA,\r\n  const arm_matrix_instance_q15 * pSrcB,\r\n  arm_matrix_instance_q15 * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Q31 matrix addition.\r\n   * @param[in]  pSrcA  points to the first input matrix structure\r\n   * @param[in]  pSrcB  points to the second input matrix structure\r\n   * @param[out] pDst   points to output matrix structure\r\n   * @return     The function returns either\r\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_add_q31(\r\n  const arm_matrix_instance_q31 * pSrcA,\r\n  const arm_matrix_instance_q31 * pSrcB,\r\n  arm_matrix_instance_q31 * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Floating-point, complex, matrix multiplication.\r\n   * @param[in]  pSrcA  points to the first input matrix structure\r\n   * @param[in]  pSrcB  points to the second input matrix structure\r\n   * @param[out] pDst   points to output matrix structure\r\n   * @return     The function returns either\r\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_cmplx_mult_f32(\r\n  const arm_matrix_instance_f32 * pSrcA,\r\n  const arm_matrix_instance_f32 * pSrcB,\r\n  arm_matrix_instance_f32 * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Q15, complex,  matrix multiplication.\r\n   * @param[in]  pSrcA  points to the first input matrix structure\r\n   * @param[in]  pSrcB  points to the second input matrix structure\r\n   * @param[out] pDst   points to output matrix structure\r\n   * @return     The function returns either\r\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_cmplx_mult_q15(\r\n  const arm_matrix_instance_q15 * pSrcA,\r\n  const arm_matrix_instance_q15 * pSrcB,\r\n  arm_matrix_instance_q15 * pDst,\r\n  q15_t * pScratch);\r\n\r\n\r\n  /**\r\n   * @brief Q31, complex, matrix multiplication.\r\n   * @param[in]  pSrcA  points to the first input matrix structure\r\n   * @param[in]  pSrcB  points to the second input matrix structure\r\n   * @param[out] pDst   points to output matrix structure\r\n   * @return     The function returns either\r\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_cmplx_mult_q31(\r\n  const arm_matrix_instance_q31 * pSrcA,\r\n  const arm_matrix_instance_q31 * pSrcB,\r\n  arm_matrix_instance_q31 * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Floating-point matrix transpose.\r\n   * @param[in]  pSrc  points to the input matrix\r\n   * @param[out] pDst  points to the output matrix\r\n   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>\r\n   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_trans_f32(\r\n  const arm_matrix_instance_f32 * pSrc,\r\n  arm_matrix_instance_f32 * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Q15 matrix transpose.\r\n   * @param[in]  pSrc  points to the input matrix\r\n   * @param[out] pDst  points to the output matrix\r\n   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>\r\n   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_trans_q15(\r\n  const arm_matrix_instance_q15 * pSrc,\r\n  arm_matrix_instance_q15 * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Q31 matrix transpose.\r\n   * @param[in]  pSrc  points to the input matrix\r\n   * @param[out] pDst  points to the output matrix\r\n   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>\r\n   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_trans_q31(\r\n  const arm_matrix_instance_q31 * pSrc,\r\n  arm_matrix_instance_q31 * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Floating-point matrix multiplication\r\n   * @param[in]  pSrcA  points to the first input matrix structure\r\n   * @param[in]  pSrcB  points to the second input matrix structure\r\n   * @param[out] pDst   points to output matrix structure\r\n   * @return     The function returns either\r\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_mult_f32(\r\n  const arm_matrix_instance_f32 * pSrcA,\r\n  const arm_matrix_instance_f32 * pSrcB,\r\n  arm_matrix_instance_f32 * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Q15 matrix multiplication\r\n   * @param[in]  pSrcA   points to the first input matrix structure\r\n   * @param[in]  pSrcB   points to the second input matrix structure\r\n   * @param[out] pDst    points to output matrix structure\r\n   * @param[in]  pState  points to the array for storing intermediate results\r\n   * @return     The function returns either\r\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_mult_q15(\r\n  const arm_matrix_instance_q15 * pSrcA,\r\n  const arm_matrix_instance_q15 * pSrcB,\r\n  arm_matrix_instance_q15 * pDst,\r\n  q15_t * pState);\r\n\r\n\r\n  /**\r\n   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\r\n   * @param[in]  pSrcA   points to the first input matrix structure\r\n   * @param[in]  pSrcB   points to the second input matrix structure\r\n   * @param[out] pDst    points to output matrix structure\r\n   * @param[in]  pState  points to the array for storing intermediate results\r\n   * @return     The function returns either\r\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_mult_fast_q15(\r\n  const arm_matrix_instance_q15 * pSrcA,\r\n  const arm_matrix_instance_q15 * pSrcB,\r\n  arm_matrix_instance_q15 * pDst,\r\n  q15_t * pState);\r\n\r\n\r\n  /**\r\n   * @brief Q31 matrix multiplication\r\n   * @param[in]  pSrcA  points to the first input matrix structure\r\n   * @param[in]  pSrcB  points to the second input matrix structure\r\n   * @param[out] pDst   points to output matrix structure\r\n   * @return     The function returns either\r\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_mult_q31(\r\n  const arm_matrix_instance_q31 * pSrcA,\r\n  const arm_matrix_instance_q31 * pSrcB,\r\n  arm_matrix_instance_q31 * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\r\n   * @param[in]  pSrcA  points to the first input matrix structure\r\n   * @param[in]  pSrcB  points to the second input matrix structure\r\n   * @param[out] pDst   points to output matrix structure\r\n   * @return     The function returns either\r\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_mult_fast_q31(\r\n  const arm_matrix_instance_q31 * pSrcA,\r\n  const arm_matrix_instance_q31 * pSrcB,\r\n  arm_matrix_instance_q31 * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Floating-point matrix subtraction\r\n   * @param[in]  pSrcA  points to the first input matrix structure\r\n   * @param[in]  pSrcB  points to the second input matrix structure\r\n   * @param[out] pDst   points to output matrix structure\r\n   * @return     The function returns either\r\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_sub_f32(\r\n  const arm_matrix_instance_f32 * pSrcA,\r\n  const arm_matrix_instance_f32 * pSrcB,\r\n  arm_matrix_instance_f32 * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Q15 matrix subtraction\r\n   * @param[in]  pSrcA  points to the first input matrix structure\r\n   * @param[in]  pSrcB  points to the second input matrix structure\r\n   * @param[out] pDst   points to output matrix structure\r\n   * @return     The function returns either\r\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_sub_q15(\r\n  const arm_matrix_instance_q15 * pSrcA,\r\n  const arm_matrix_instance_q15 * pSrcB,\r\n  arm_matrix_instance_q15 * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Q31 matrix subtraction\r\n   * @param[in]  pSrcA  points to the first input matrix structure\r\n   * @param[in]  pSrcB  points to the second input matrix structure\r\n   * @param[out] pDst   points to output matrix structure\r\n   * @return     The function returns either\r\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_sub_q31(\r\n  const arm_matrix_instance_q31 * pSrcA,\r\n  const arm_matrix_instance_q31 * pSrcB,\r\n  arm_matrix_instance_q31 * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Floating-point matrix scaling.\r\n   * @param[in]  pSrc   points to the input matrix\r\n   * @param[in]  scale  scale factor\r\n   * @param[out] pDst   points to the output matrix\r\n   * @return     The function returns either\r\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_scale_f32(\r\n  const arm_matrix_instance_f32 * pSrc,\r\n  float32_t scale,\r\n  arm_matrix_instance_f32 * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Q15 matrix scaling.\r\n   * @param[in]  pSrc        points to input matrix\r\n   * @param[in]  scaleFract  fractional portion of the scale factor\r\n   * @param[in]  shift       number of bits to shift the result by\r\n   * @param[out] pDst        points to output matrix\r\n   * @return     The function returns either\r\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_scale_q15(\r\n  const arm_matrix_instance_q15 * pSrc,\r\n  q15_t scaleFract,\r\n  int32_t shift,\r\n  arm_matrix_instance_q15 * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Q31 matrix scaling.\r\n   * @param[in]  pSrc        points to input matrix\r\n   * @param[in]  scaleFract  fractional portion of the scale factor\r\n   * @param[in]  shift       number of bits to shift the result by\r\n   * @param[out] pDst        points to output matrix structure\r\n   * @return     The function returns either\r\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r\n   */\r\n  arm_status arm_mat_scale_q31(\r\n  const arm_matrix_instance_q31 * pSrc,\r\n  q31_t scaleFract,\r\n  int32_t shift,\r\n  arm_matrix_instance_q31 * pDst);\r\n\r\n\r\n  /**\r\n   * @brief  Q31 matrix initialization.\r\n   * @param[in,out] S         points to an instance of the floating-point matrix structure.\r\n   * @param[in]     nRows     number of rows in the matrix.\r\n   * @param[in]     nColumns  number of columns in the matrix.\r\n   * @param[in]     pData     points to the matrix data array.\r\n   */\r\n  void arm_mat_init_q31(\r\n  arm_matrix_instance_q31 * S,\r\n  uint16_t nRows,\r\n  uint16_t nColumns,\r\n  q31_t * pData);\r\n\r\n\r\n  /**\r\n   * @brief  Q15 matrix initialization.\r\n   * @param[in,out] S         points to an instance of the floating-point matrix structure.\r\n   * @param[in]     nRows     number of rows in the matrix.\r\n   * @param[in]     nColumns  number of columns in the matrix.\r\n   * @param[in]     pData     points to the matrix data array.\r\n   */\r\n  void arm_mat_init_q15(\r\n  arm_matrix_instance_q15 * S,\r\n  uint16_t nRows,\r\n  uint16_t nColumns,\r\n  q15_t * pData);\r\n\r\n\r\n  /**\r\n   * @brief  Floating-point matrix initialization.\r\n   * @param[in,out] S         points to an instance of the floating-point matrix structure.\r\n   * @param[in]     nRows     number of rows in the matrix.\r\n   * @param[in]     nColumns  number of columns in the matrix.\r\n   * @param[in]     pData     points to the matrix data array.\r\n   */\r\n  void arm_mat_init_f32(\r\n  arm_matrix_instance_f32 * S,\r\n  uint16_t nRows,\r\n  uint16_t nColumns,\r\n  float32_t * pData);\r\n\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the Q15 PID Control.\r\n   */\r\n  typedef struct\r\n  {\r\n    q15_t A0;           /**< The derived gain, A0 = Kp + Ki + Kd . */\r\n#ifdef ARM_MATH_CM0_FAMILY\r\n    q15_t A1;\r\n    q15_t A2;\r\n#else\r\n    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/\r\n#endif\r\n    q15_t state[3];     /**< The state array of length 3. */\r\n    q15_t Kp;           /**< The proportional gain. */\r\n    q15_t Ki;           /**< The integral gain. */\r\n    q15_t Kd;           /**< The derivative gain. */\r\n  } arm_pid_instance_q15;\r\n\r\n  /**\r\n   * @brief Instance structure for the Q31 PID Control.\r\n   */\r\n  typedef struct\r\n  {\r\n    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */\r\n    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */\r\n    q31_t A2;            /**< The derived gain, A2 = Kd . */\r\n    q31_t state[3];      /**< The state array of length 3. */\r\n    q31_t Kp;            /**< The proportional gain. */\r\n    q31_t Ki;            /**< The integral gain. */\r\n    q31_t Kd;            /**< The derivative gain. */\r\n  } arm_pid_instance_q31;\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point PID Control.\r\n   */\r\n  typedef struct\r\n  {\r\n    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */\r\n    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */\r\n    float32_t A2;          /**< The derived gain, A2 = Kd . */\r\n    float32_t state[3];    /**< The state array of length 3. */\r\n    float32_t Kp;          /**< The proportional gain. */\r\n    float32_t Ki;          /**< The integral gain. */\r\n    float32_t Kd;          /**< The derivative gain. */\r\n  } arm_pid_instance_f32;\r\n\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the floating-point PID Control.\r\n   * @param[in,out] S               points to an instance of the PID structure.\r\n   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.\r\n   */\r\n  void arm_pid_init_f32(\r\n  arm_pid_instance_f32 * S,\r\n  int32_t resetStateFlag);\r\n\r\n\r\n  /**\r\n   * @brief  Reset function for the floating-point PID Control.\r\n   * @param[in,out] S  is an instance of the floating-point PID Control structure\r\n   */\r\n  void arm_pid_reset_f32(\r\n  arm_pid_instance_f32 * S);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the Q31 PID Control.\r\n   * @param[in,out] S               points to an instance of the Q15 PID structure.\r\n   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.\r\n   */\r\n  void arm_pid_init_q31(\r\n  arm_pid_instance_q31 * S,\r\n  int32_t resetStateFlag);\r\n\r\n\r\n  /**\r\n   * @brief  Reset function for the Q31 PID Control.\r\n   * @param[in,out] S   points to an instance of the Q31 PID Control structure\r\n   */\r\n\r\n  void arm_pid_reset_q31(\r\n  arm_pid_instance_q31 * S);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the Q15 PID Control.\r\n   * @param[in,out] S               points to an instance of the Q15 PID structure.\r\n   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.\r\n   */\r\n  void arm_pid_init_q15(\r\n  arm_pid_instance_q15 * S,\r\n  int32_t resetStateFlag);\r\n\r\n\r\n  /**\r\n   * @brief  Reset function for the Q15 PID Control.\r\n   * @param[in,out] S  points to an instance of the q15 PID Control structure\r\n   */\r\n  void arm_pid_reset_q15(\r\n  arm_pid_instance_q15 * S);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point Linear Interpolate function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint32_t nValues;           /**< nValues */\r\n    float32_t x1;               /**< x1 */\r\n    float32_t xSpacing;         /**< xSpacing */\r\n    float32_t *pYData;          /**< pointer to the table of Y values */\r\n  } arm_linear_interp_instance_f32;\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point bilinear interpolation function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numRows;   /**< number of rows in the data table. */\r\n    uint16_t numCols;   /**< number of columns in the data table. */\r\n    float32_t *pData;   /**< points to the data table. */\r\n  } arm_bilinear_interp_instance_f32;\r\n\r\n   /**\r\n   * @brief Instance structure for the Q31 bilinear interpolation function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numRows;   /**< number of rows in the data table. */\r\n    uint16_t numCols;   /**< number of columns in the data table. */\r\n    q31_t *pData;       /**< points to the data table. */\r\n  } arm_bilinear_interp_instance_q31;\r\n\r\n   /**\r\n   * @brief Instance structure for the Q15 bilinear interpolation function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numRows;   /**< number of rows in the data table. */\r\n    uint16_t numCols;   /**< number of columns in the data table. */\r\n    q15_t *pData;       /**< points to the data table. */\r\n  } arm_bilinear_interp_instance_q15;\r\n\r\n   /**\r\n   * @brief Instance structure for the Q15 bilinear interpolation function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numRows;   /**< number of rows in the data table. */\r\n    uint16_t numCols;   /**< number of columns in the data table. */\r\n    q7_t *pData;        /**< points to the data table. */\r\n  } arm_bilinear_interp_instance_q7;\r\n\r\n\r\n  /**\r\n   * @brief Q7 vector multiplication.\r\n   * @param[in]  pSrcA      points to the first input vector\r\n   * @param[in]  pSrcB      points to the second input vector\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   */\r\n  void arm_mult_q7(\r\n  q7_t * pSrcA,\r\n  q7_t * pSrcB,\r\n  q7_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Q15 vector multiplication.\r\n   * @param[in]  pSrcA      points to the first input vector\r\n   * @param[in]  pSrcB      points to the second input vector\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   */\r\n  void arm_mult_q15(\r\n  q15_t * pSrcA,\r\n  q15_t * pSrcB,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Q31 vector multiplication.\r\n   * @param[in]  pSrcA      points to the first input vector\r\n   * @param[in]  pSrcB      points to the second input vector\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   */\r\n  void arm_mult_q31(\r\n  q31_t * pSrcA,\r\n  q31_t * pSrcB,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Floating-point vector multiplication.\r\n   * @param[in]  pSrcA      points to the first input vector\r\n   * @param[in]  pSrcB      points to the second input vector\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   */\r\n  void arm_mult_f32(\r\n  float32_t * pSrcA,\r\n  float32_t * pSrcB,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the Q15 CFFT/CIFFT function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t fftLen;                 /**< length of the FFT. */\r\n    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r\n    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r\n    q15_t *pTwiddle;                 /**< points to the Sin twiddle factor table. */\r\n    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */\r\n    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r\n    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r\n  } arm_cfft_radix2_instance_q15;\r\n\r\n/* Deprecated */\r\n  arm_status arm_cfft_radix2_init_q15(\r\n  arm_cfft_radix2_instance_q15 * S,\r\n  uint16_t fftLen,\r\n  uint8_t ifftFlag,\r\n  uint8_t bitReverseFlag);\r\n\r\n/* Deprecated */\r\n  void arm_cfft_radix2_q15(\r\n  const arm_cfft_radix2_instance_q15 * S,\r\n  q15_t * pSrc);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the Q15 CFFT/CIFFT function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t fftLen;                 /**< length of the FFT. */\r\n    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r\n    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r\n    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */\r\n    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */\r\n    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r\n    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r\n  } arm_cfft_radix4_instance_q15;\r\n\r\n/* Deprecated */\r\n  arm_status arm_cfft_radix4_init_q15(\r\n  arm_cfft_radix4_instance_q15 * S,\r\n  uint16_t fftLen,\r\n  uint8_t ifftFlag,\r\n  uint8_t bitReverseFlag);\r\n\r\n/* Deprecated */\r\n  void arm_cfft_radix4_q15(\r\n  const arm_cfft_radix4_instance_q15 * S,\r\n  q15_t * pSrc);\r\n\r\n  /**\r\n   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t fftLen;                 /**< length of the FFT. */\r\n    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r\n    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r\n    q31_t *pTwiddle;                 /**< points to the Twiddle factor table. */\r\n    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */\r\n    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r\n    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r\n  } arm_cfft_radix2_instance_q31;\r\n\r\n/* Deprecated */\r\n  arm_status arm_cfft_radix2_init_q31(\r\n  arm_cfft_radix2_instance_q31 * S,\r\n  uint16_t fftLen,\r\n  uint8_t ifftFlag,\r\n  uint8_t bitReverseFlag);\r\n\r\n/* Deprecated */\r\n  void arm_cfft_radix2_q31(\r\n  const arm_cfft_radix2_instance_q31 * S,\r\n  q31_t * pSrc);\r\n\r\n  /**\r\n   * @brief Instance structure for the Q31 CFFT/CIFFT function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t fftLen;                 /**< length of the FFT. */\r\n    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r\n    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r\n    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */\r\n    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */\r\n    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r\n    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r\n  } arm_cfft_radix4_instance_q31;\r\n\r\n/* Deprecated */\r\n  void arm_cfft_radix4_q31(\r\n  const arm_cfft_radix4_instance_q31 * S,\r\n  q31_t * pSrc);\r\n\r\n/* Deprecated */\r\n  arm_status arm_cfft_radix4_init_q31(\r\n  arm_cfft_radix4_instance_q31 * S,\r\n  uint16_t fftLen,\r\n  uint8_t ifftFlag,\r\n  uint8_t bitReverseFlag);\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point CFFT/CIFFT function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t fftLen;                   /**< length of the FFT. */\r\n    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r\n    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r\n    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */\r\n    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */\r\n    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r\n    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r\n    float32_t onebyfftLen;             /**< value of 1/fftLen. */\r\n  } arm_cfft_radix2_instance_f32;\r\n\r\n/* Deprecated */\r\n  arm_status arm_cfft_radix2_init_f32(\r\n  arm_cfft_radix2_instance_f32 * S,\r\n  uint16_t fftLen,\r\n  uint8_t ifftFlag,\r\n  uint8_t bitReverseFlag);\r\n\r\n/* Deprecated */\r\n  void arm_cfft_radix2_f32(\r\n  const arm_cfft_radix2_instance_f32 * S,\r\n  float32_t * pSrc);\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point CFFT/CIFFT function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t fftLen;                   /**< length of the FFT. */\r\n    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r\n    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r\n    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */\r\n    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */\r\n    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r\n    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r\n    float32_t onebyfftLen;             /**< value of 1/fftLen. */\r\n  } arm_cfft_radix4_instance_f32;\r\n\r\n/* Deprecated */\r\n  arm_status arm_cfft_radix4_init_f32(\r\n  arm_cfft_radix4_instance_f32 * S,\r\n  uint16_t fftLen,\r\n  uint8_t ifftFlag,\r\n  uint8_t bitReverseFlag);\r\n\r\n/* Deprecated */\r\n  void arm_cfft_radix4_f32(\r\n  const arm_cfft_radix4_instance_f32 * S,\r\n  float32_t * pSrc);\r\n\r\n  /**\r\n   * @brief Instance structure for the fixed-point CFFT/CIFFT function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t fftLen;                   /**< length of the FFT. */\r\n    const q15_t *pTwiddle;             /**< points to the Twiddle factor table. */\r\n    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */\r\n    uint16_t bitRevLength;             /**< bit reversal table length. */\r\n  } arm_cfft_instance_q15;\r\n\r\nvoid arm_cfft_q15(\r\n    const arm_cfft_instance_q15 * S,\r\n    q15_t * p1,\r\n    uint8_t ifftFlag,\r\n    uint8_t bitReverseFlag);\r\n\r\n  /**\r\n   * @brief Instance structure for the fixed-point CFFT/CIFFT function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t fftLen;                   /**< length of the FFT. */\r\n    const q31_t *pTwiddle;             /**< points to the Twiddle factor table. */\r\n    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */\r\n    uint16_t bitRevLength;             /**< bit reversal table length. */\r\n  } arm_cfft_instance_q31;\r\n\r\nvoid arm_cfft_q31(\r\n    const arm_cfft_instance_q31 * S,\r\n    q31_t * p1,\r\n    uint8_t ifftFlag,\r\n    uint8_t bitReverseFlag);\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point CFFT/CIFFT function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t fftLen;                   /**< length of the FFT. */\r\n    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */\r\n    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */\r\n    uint16_t bitRevLength;             /**< bit reversal table length. */\r\n  } arm_cfft_instance_f32;\r\n\r\n  void arm_cfft_f32(\r\n  const arm_cfft_instance_f32 * S,\r\n  float32_t * p1,\r\n  uint8_t ifftFlag,\r\n  uint8_t bitReverseFlag);\r\n\r\n  /**\r\n   * @brief Instance structure for the Q15 RFFT/RIFFT function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint32_t fftLenReal;                      /**< length of the real FFT. */\r\n    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r\n    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r\n    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r\n    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */\r\n    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */\r\n    const arm_cfft_instance_q15 *pCfft;       /**< points to the complex FFT instance. */\r\n  } arm_rfft_instance_q15;\r\n\r\n  arm_status arm_rfft_init_q15(\r\n  arm_rfft_instance_q15 * S,\r\n  uint32_t fftLenReal,\r\n  uint32_t ifftFlagR,\r\n  uint32_t bitReverseFlag);\r\n\r\n  void arm_rfft_q15(\r\n  const arm_rfft_instance_q15 * S,\r\n  q15_t * pSrc,\r\n  q15_t * pDst);\r\n\r\n  /**\r\n   * @brief Instance structure for the Q31 RFFT/RIFFT function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint32_t fftLenReal;                        /**< length of the real FFT. */\r\n    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r\n    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r\n    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r\n    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */\r\n    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */\r\n    const arm_cfft_instance_q31 *pCfft;         /**< points to the complex FFT instance. */\r\n  } arm_rfft_instance_q31;\r\n\r\n  arm_status arm_rfft_init_q31(\r\n  arm_rfft_instance_q31 * S,\r\n  uint32_t fftLenReal,\r\n  uint32_t ifftFlagR,\r\n  uint32_t bitReverseFlag);\r\n\r\n  void arm_rfft_q31(\r\n  const arm_rfft_instance_q31 * S,\r\n  q31_t * pSrc,\r\n  q31_t * pDst);\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point RFFT/RIFFT function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint32_t fftLenReal;                        /**< length of the real FFT. */\r\n    uint16_t fftLenBy2;                         /**< length of the complex FFT. */\r\n    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r\n    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r\n    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r\n    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */\r\n    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */\r\n    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */\r\n  } arm_rfft_instance_f32;\r\n\r\n  arm_status arm_rfft_init_f32(\r\n  arm_rfft_instance_f32 * S,\r\n  arm_cfft_radix4_instance_f32 * S_CFFT,\r\n  uint32_t fftLenReal,\r\n  uint32_t ifftFlagR,\r\n  uint32_t bitReverseFlag);\r\n\r\n  void arm_rfft_f32(\r\n  const arm_rfft_instance_f32 * S,\r\n  float32_t * pSrc,\r\n  float32_t * pDst);\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point RFFT/RIFFT function.\r\n   */\r\ntypedef struct\r\n  {\r\n    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */\r\n    uint16_t fftLenRFFT;             /**< length of the real sequence */\r\n    float32_t * pTwiddleRFFT;        /**< Twiddle factors real stage  */\r\n  } arm_rfft_fast_instance_f32 ;\r\n\r\narm_status arm_rfft_fast_init_f32 (\r\n   arm_rfft_fast_instance_f32 * S,\r\n   uint16_t fftLen);\r\n\r\nvoid arm_rfft_fast_f32(\r\n  arm_rfft_fast_instance_f32 * S,\r\n  float32_t * p, float32_t * pOut,\r\n  uint8_t ifftFlag);\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point DCT4/IDCT4 function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t N;                          /**< length of the DCT4. */\r\n    uint16_t Nby2;                       /**< half of the length of the DCT4. */\r\n    float32_t normalize;                 /**< normalizing factor. */\r\n    float32_t *pTwiddle;                 /**< points to the twiddle factor table. */\r\n    float32_t *pCosFactor;               /**< points to the cosFactor table. */\r\n    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */\r\n    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */\r\n  } arm_dct4_instance_f32;\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the floating-point DCT4/IDCT4.\r\n   * @param[in,out] S          points to an instance of floating-point DCT4/IDCT4 structure.\r\n   * @param[in]     S_RFFT     points to an instance of floating-point RFFT/RIFFT structure.\r\n   * @param[in]     S_CFFT     points to an instance of floating-point CFFT/CIFFT structure.\r\n   * @param[in]     N          length of the DCT4.\r\n   * @param[in]     Nby2       half of the length of the DCT4.\r\n   * @param[in]     normalize  normalizing factor.\r\n   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.\r\n   */\r\n  arm_status arm_dct4_init_f32(\r\n  arm_dct4_instance_f32 * S,\r\n  arm_rfft_instance_f32 * S_RFFT,\r\n  arm_cfft_radix4_instance_f32 * S_CFFT,\r\n  uint16_t N,\r\n  uint16_t Nby2,\r\n  float32_t normalize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the floating-point DCT4/IDCT4.\r\n   * @param[in]     S              points to an instance of the floating-point DCT4/IDCT4 structure.\r\n   * @param[in]     pState         points to state buffer.\r\n   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.\r\n   */\r\n  void arm_dct4_f32(\r\n  const arm_dct4_instance_f32 * S,\r\n  float32_t * pState,\r\n  float32_t * pInlineBuffer);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the Q31 DCT4/IDCT4 function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t N;                          /**< length of the DCT4. */\r\n    uint16_t Nby2;                       /**< half of the length of the DCT4. */\r\n    q31_t normalize;                     /**< normalizing factor. */\r\n    q31_t *pTwiddle;                     /**< points to the twiddle factor table. */\r\n    q31_t *pCosFactor;                   /**< points to the cosFactor table. */\r\n    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */\r\n    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */\r\n  } arm_dct4_instance_q31;\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the Q31 DCT4/IDCT4.\r\n   * @param[in,out] S          points to an instance of Q31 DCT4/IDCT4 structure.\r\n   * @param[in]     S_RFFT     points to an instance of Q31 RFFT/RIFFT structure\r\n   * @param[in]     S_CFFT     points to an instance of Q31 CFFT/CIFFT structure\r\n   * @param[in]     N          length of the DCT4.\r\n   * @param[in]     Nby2       half of the length of the DCT4.\r\n   * @param[in]     normalize  normalizing factor.\r\n   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.\r\n   */\r\n  arm_status arm_dct4_init_q31(\r\n  arm_dct4_instance_q31 * S,\r\n  arm_rfft_instance_q31 * S_RFFT,\r\n  arm_cfft_radix4_instance_q31 * S_CFFT,\r\n  uint16_t N,\r\n  uint16_t Nby2,\r\n  q31_t normalize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q31 DCT4/IDCT4.\r\n   * @param[in]     S              points to an instance of the Q31 DCT4 structure.\r\n   * @param[in]     pState         points to state buffer.\r\n   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.\r\n   */\r\n  void arm_dct4_q31(\r\n  const arm_dct4_instance_q31 * S,\r\n  q31_t * pState,\r\n  q31_t * pInlineBuffer);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the Q15 DCT4/IDCT4 function.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t N;                          /**< length of the DCT4. */\r\n    uint16_t Nby2;                       /**< half of the length of the DCT4. */\r\n    q15_t normalize;                     /**< normalizing factor. */\r\n    q15_t *pTwiddle;                     /**< points to the twiddle factor table. */\r\n    q15_t *pCosFactor;                   /**< points to the cosFactor table. */\r\n    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */\r\n    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */\r\n  } arm_dct4_instance_q15;\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the Q15 DCT4/IDCT4.\r\n   * @param[in,out] S          points to an instance of Q15 DCT4/IDCT4 structure.\r\n   * @param[in]     S_RFFT     points to an instance of Q15 RFFT/RIFFT structure.\r\n   * @param[in]     S_CFFT     points to an instance of Q15 CFFT/CIFFT structure.\r\n   * @param[in]     N          length of the DCT4.\r\n   * @param[in]     Nby2       half of the length of the DCT4.\r\n   * @param[in]     normalize  normalizing factor.\r\n   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.\r\n   */\r\n  arm_status arm_dct4_init_q15(\r\n  arm_dct4_instance_q15 * S,\r\n  arm_rfft_instance_q15 * S_RFFT,\r\n  arm_cfft_radix4_instance_q15 * S_CFFT,\r\n  uint16_t N,\r\n  uint16_t Nby2,\r\n  q15_t normalize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q15 DCT4/IDCT4.\r\n   * @param[in]     S              points to an instance of the Q15 DCT4 structure.\r\n   * @param[in]     pState         points to state buffer.\r\n   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.\r\n   */\r\n  void arm_dct4_q15(\r\n  const arm_dct4_instance_q15 * S,\r\n  q15_t * pState,\r\n  q15_t * pInlineBuffer);\r\n\r\n\r\n  /**\r\n   * @brief Floating-point vector addition.\r\n   * @param[in]  pSrcA      points to the first input vector\r\n   * @param[in]  pSrcB      points to the second input vector\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   */\r\n  void arm_add_f32(\r\n  float32_t * pSrcA,\r\n  float32_t * pSrcB,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Q7 vector addition.\r\n   * @param[in]  pSrcA      points to the first input vector\r\n   * @param[in]  pSrcB      points to the second input vector\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   */\r\n  void arm_add_q7(\r\n  q7_t * pSrcA,\r\n  q7_t * pSrcB,\r\n  q7_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Q15 vector addition.\r\n   * @param[in]  pSrcA      points to the first input vector\r\n   * @param[in]  pSrcB      points to the second input vector\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   */\r\n  void arm_add_q15(\r\n  q15_t * pSrcA,\r\n  q15_t * pSrcB,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Q31 vector addition.\r\n   * @param[in]  pSrcA      points to the first input vector\r\n   * @param[in]  pSrcB      points to the second input vector\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   */\r\n  void arm_add_q31(\r\n  q31_t * pSrcA,\r\n  q31_t * pSrcB,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Floating-point vector subtraction.\r\n   * @param[in]  pSrcA      points to the first input vector\r\n   * @param[in]  pSrcB      points to the second input vector\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   */\r\n  void arm_sub_f32(\r\n  float32_t * pSrcA,\r\n  float32_t * pSrcB,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Q7 vector subtraction.\r\n   * @param[in]  pSrcA      points to the first input vector\r\n   * @param[in]  pSrcB      points to the second input vector\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   */\r\n  void arm_sub_q7(\r\n  q7_t * pSrcA,\r\n  q7_t * pSrcB,\r\n  q7_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Q15 vector subtraction.\r\n   * @param[in]  pSrcA      points to the first input vector\r\n   * @param[in]  pSrcB      points to the second input vector\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   */\r\n  void arm_sub_q15(\r\n  q15_t * pSrcA,\r\n  q15_t * pSrcB,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Q31 vector subtraction.\r\n   * @param[in]  pSrcA      points to the first input vector\r\n   * @param[in]  pSrcB      points to the second input vector\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   */\r\n  void arm_sub_q31(\r\n  q31_t * pSrcA,\r\n  q31_t * pSrcB,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Multiplies a floating-point vector by a scalar.\r\n   * @param[in]  pSrc       points to the input vector\r\n   * @param[in]  scale      scale factor to be applied\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in the vector\r\n   */\r\n  void arm_scale_f32(\r\n  float32_t * pSrc,\r\n  float32_t scale,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Multiplies a Q7 vector by a scalar.\r\n   * @param[in]  pSrc        points to the input vector\r\n   * @param[in]  scaleFract  fractional portion of the scale value\r\n   * @param[in]  shift       number of bits to shift the result by\r\n   * @param[out] pDst        points to the output vector\r\n   * @param[in]  blockSize   number of samples in the vector\r\n   */\r\n  void arm_scale_q7(\r\n  q7_t * pSrc,\r\n  q7_t scaleFract,\r\n  int8_t shift,\r\n  q7_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Multiplies a Q15 vector by a scalar.\r\n   * @param[in]  pSrc        points to the input vector\r\n   * @param[in]  scaleFract  fractional portion of the scale value\r\n   * @param[in]  shift       number of bits to shift the result by\r\n   * @param[out] pDst        points to the output vector\r\n   * @param[in]  blockSize   number of samples in the vector\r\n   */\r\n  void arm_scale_q15(\r\n  q15_t * pSrc,\r\n  q15_t scaleFract,\r\n  int8_t shift,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Multiplies a Q31 vector by a scalar.\r\n   * @param[in]  pSrc        points to the input vector\r\n   * @param[in]  scaleFract  fractional portion of the scale value\r\n   * @param[in]  shift       number of bits to shift the result by\r\n   * @param[out] pDst        points to the output vector\r\n   * @param[in]  blockSize   number of samples in the vector\r\n   */\r\n  void arm_scale_q31(\r\n  q31_t * pSrc,\r\n  q31_t scaleFract,\r\n  int8_t shift,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Q7 vector absolute value.\r\n   * @param[in]  pSrc       points to the input buffer\r\n   * @param[out] pDst       points to the output buffer\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   */\r\n  void arm_abs_q7(\r\n  q7_t * pSrc,\r\n  q7_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Floating-point vector absolute value.\r\n   * @param[in]  pSrc       points to the input buffer\r\n   * @param[out] pDst       points to the output buffer\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   */\r\n  void arm_abs_f32(\r\n  float32_t * pSrc,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Q15 vector absolute value.\r\n   * @param[in]  pSrc       points to the input buffer\r\n   * @param[out] pDst       points to the output buffer\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   */\r\n  void arm_abs_q15(\r\n  q15_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Q31 vector absolute value.\r\n   * @param[in]  pSrc       points to the input buffer\r\n   * @param[out] pDst       points to the output buffer\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   */\r\n  void arm_abs_q31(\r\n  q31_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Dot product of floating-point vectors.\r\n   * @param[in]  pSrcA      points to the first input vector\r\n   * @param[in]  pSrcB      points to the second input vector\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   * @param[out] result     output result returned here\r\n   */\r\n  void arm_dot_prod_f32(\r\n  float32_t * pSrcA,\r\n  float32_t * pSrcB,\r\n  uint32_t blockSize,\r\n  float32_t * result);\r\n\r\n\r\n  /**\r\n   * @brief Dot product of Q7 vectors.\r\n   * @param[in]  pSrcA      points to the first input vector\r\n   * @param[in]  pSrcB      points to the second input vector\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   * @param[out] result     output result returned here\r\n   */\r\n  void arm_dot_prod_q7(\r\n  q7_t * pSrcA,\r\n  q7_t * pSrcB,\r\n  uint32_t blockSize,\r\n  q31_t * result);\r\n\r\n\r\n  /**\r\n   * @brief Dot product of Q15 vectors.\r\n   * @param[in]  pSrcA      points to the first input vector\r\n   * @param[in]  pSrcB      points to the second input vector\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   * @param[out] result     output result returned here\r\n   */\r\n  void arm_dot_prod_q15(\r\n  q15_t * pSrcA,\r\n  q15_t * pSrcB,\r\n  uint32_t blockSize,\r\n  q63_t * result);\r\n\r\n\r\n  /**\r\n   * @brief Dot product of Q31 vectors.\r\n   * @param[in]  pSrcA      points to the first input vector\r\n   * @param[in]  pSrcB      points to the second input vector\r\n   * @param[in]  blockSize  number of samples in each vector\r\n   * @param[out] result     output result returned here\r\n   */\r\n  void arm_dot_prod_q31(\r\n  q31_t * pSrcA,\r\n  q31_t * pSrcB,\r\n  uint32_t blockSize,\r\n  q63_t * result);\r\n\r\n\r\n  /**\r\n   * @brief  Shifts the elements of a Q7 vector a specified number of bits.\r\n   * @param[in]  pSrc       points to the input vector\r\n   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in the vector\r\n   */\r\n  void arm_shift_q7(\r\n  q7_t * pSrc,\r\n  int8_t shiftBits,\r\n  q7_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Shifts the elements of a Q15 vector a specified number of bits.\r\n   * @param[in]  pSrc       points to the input vector\r\n   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in the vector\r\n   */\r\n  void arm_shift_q15(\r\n  q15_t * pSrc,\r\n  int8_t shiftBits,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Shifts the elements of a Q31 vector a specified number of bits.\r\n   * @param[in]  pSrc       points to the input vector\r\n   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in the vector\r\n   */\r\n  void arm_shift_q31(\r\n  q31_t * pSrc,\r\n  int8_t shiftBits,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Adds a constant offset to a floating-point vector.\r\n   * @param[in]  pSrc       points to the input vector\r\n   * @param[in]  offset     is the offset to be added\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in the vector\r\n   */\r\n  void arm_offset_f32(\r\n  float32_t * pSrc,\r\n  float32_t offset,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Adds a constant offset to a Q7 vector.\r\n   * @param[in]  pSrc       points to the input vector\r\n   * @param[in]  offset     is the offset to be added\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in the vector\r\n   */\r\n  void arm_offset_q7(\r\n  q7_t * pSrc,\r\n  q7_t offset,\r\n  q7_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Adds a constant offset to a Q15 vector.\r\n   * @param[in]  pSrc       points to the input vector\r\n   * @param[in]  offset     is the offset to be added\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in the vector\r\n   */\r\n  void arm_offset_q15(\r\n  q15_t * pSrc,\r\n  q15_t offset,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Adds a constant offset to a Q31 vector.\r\n   * @param[in]  pSrc       points to the input vector\r\n   * @param[in]  offset     is the offset to be added\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in the vector\r\n   */\r\n  void arm_offset_q31(\r\n  q31_t * pSrc,\r\n  q31_t offset,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Negates the elements of a floating-point vector.\r\n   * @param[in]  pSrc       points to the input vector\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in the vector\r\n   */\r\n  void arm_negate_f32(\r\n  float32_t * pSrc,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Negates the elements of a Q7 vector.\r\n   * @param[in]  pSrc       points to the input vector\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in the vector\r\n   */\r\n  void arm_negate_q7(\r\n  q7_t * pSrc,\r\n  q7_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Negates the elements of a Q15 vector.\r\n   * @param[in]  pSrc       points to the input vector\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in the vector\r\n   */\r\n  void arm_negate_q15(\r\n  q15_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Negates the elements of a Q31 vector.\r\n   * @param[in]  pSrc       points to the input vector\r\n   * @param[out] pDst       points to the output vector\r\n   * @param[in]  blockSize  number of samples in the vector\r\n   */\r\n  void arm_negate_q31(\r\n  q31_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Copies the elements of a floating-point vector.\r\n   * @param[in]  pSrc       input pointer\r\n   * @param[out] pDst       output pointer\r\n   * @param[in]  blockSize  number of samples to process\r\n   */\r\n  void arm_copy_f32(\r\n  float32_t * pSrc,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Copies the elements of a Q7 vector.\r\n   * @param[in]  pSrc       input pointer\r\n   * @param[out] pDst       output pointer\r\n   * @param[in]  blockSize  number of samples to process\r\n   */\r\n  void arm_copy_q7(\r\n  q7_t * pSrc,\r\n  q7_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Copies the elements of a Q15 vector.\r\n   * @param[in]  pSrc       input pointer\r\n   * @param[out] pDst       output pointer\r\n   * @param[in]  blockSize  number of samples to process\r\n   */\r\n  void arm_copy_q15(\r\n  q15_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Copies the elements of a Q31 vector.\r\n   * @param[in]  pSrc       input pointer\r\n   * @param[out] pDst       output pointer\r\n   * @param[in]  blockSize  number of samples to process\r\n   */\r\n  void arm_copy_q31(\r\n  q31_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Fills a constant value into a floating-point vector.\r\n   * @param[in]  value      input value to be filled\r\n   * @param[out] pDst       output pointer\r\n   * @param[in]  blockSize  number of samples to process\r\n   */\r\n  void arm_fill_f32(\r\n  float32_t value,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Fills a constant value into a Q7 vector.\r\n   * @param[in]  value      input value to be filled\r\n   * @param[out] pDst       output pointer\r\n   * @param[in]  blockSize  number of samples to process\r\n   */\r\n  void arm_fill_q7(\r\n  q7_t value,\r\n  q7_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Fills a constant value into a Q15 vector.\r\n   * @param[in]  value      input value to be filled\r\n   * @param[out] pDst       output pointer\r\n   * @param[in]  blockSize  number of samples to process\r\n   */\r\n  void arm_fill_q15(\r\n  q15_t value,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Fills a constant value into a Q31 vector.\r\n   * @param[in]  value      input value to be filled\r\n   * @param[out] pDst       output pointer\r\n   * @param[in]  blockSize  number of samples to process\r\n   */\r\n  void arm_fill_q31(\r\n  q31_t value,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n/**\r\n * @brief Convolution of floating-point sequences.\r\n * @param[in]  pSrcA    points to the first input sequence.\r\n * @param[in]  srcALen  length of the first input sequence.\r\n * @param[in]  pSrcB    points to the second input sequence.\r\n * @param[in]  srcBLen  length of the second input sequence.\r\n * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.\r\n */\r\n  void arm_conv_f32(\r\n  float32_t * pSrcA,\r\n  uint32_t srcALen,\r\n  float32_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  float32_t * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Convolution of Q15 sequences.\r\n   * @param[in]  pSrcA      points to the first input sequence.\r\n   * @param[in]  srcALen    length of the first input sequence.\r\n   * @param[in]  pSrcB      points to the second input sequence.\r\n   * @param[in]  srcBLen    length of the second input sequence.\r\n   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.\r\n   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r\n   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).\r\n   */\r\n  void arm_conv_opt_q15(\r\n  q15_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q15_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q15_t * pDst,\r\n  q15_t * pScratch1,\r\n  q15_t * pScratch2);\r\n\r\n\r\n/**\r\n * @brief Convolution of Q15 sequences.\r\n * @param[in]  pSrcA    points to the first input sequence.\r\n * @param[in]  srcALen  length of the first input sequence.\r\n * @param[in]  pSrcB    points to the second input sequence.\r\n * @param[in]  srcBLen  length of the second input sequence.\r\n * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.\r\n */\r\n  void arm_conv_q15(\r\n  q15_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q15_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q15_t * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r\n   * @param[in]  pSrcA    points to the first input sequence.\r\n   * @param[in]  srcALen  length of the first input sequence.\r\n   * @param[in]  pSrcB    points to the second input sequence.\r\n   * @param[in]  srcBLen  length of the second input sequence.\r\n   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.\r\n   */\r\n  void arm_conv_fast_q15(\r\n          q15_t * pSrcA,\r\n          uint32_t srcALen,\r\n          q15_t * pSrcB,\r\n          uint32_t srcBLen,\r\n          q15_t * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r\n   * @param[in]  pSrcA      points to the first input sequence.\r\n   * @param[in]  srcALen    length of the first input sequence.\r\n   * @param[in]  pSrcB      points to the second input sequence.\r\n   * @param[in]  srcBLen    length of the second input sequence.\r\n   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.\r\n   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r\n   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).\r\n   */\r\n  void arm_conv_fast_opt_q15(\r\n  q15_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q15_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q15_t * pDst,\r\n  q15_t * pScratch1,\r\n  q15_t * pScratch2);\r\n\r\n\r\n  /**\r\n   * @brief Convolution of Q31 sequences.\r\n   * @param[in]  pSrcA    points to the first input sequence.\r\n   * @param[in]  srcALen  length of the first input sequence.\r\n   * @param[in]  pSrcB    points to the second input sequence.\r\n   * @param[in]  srcBLen  length of the second input sequence.\r\n   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.\r\n   */\r\n  void arm_conv_q31(\r\n  q31_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q31_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q31_t * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r\n   * @param[in]  pSrcA    points to the first input sequence.\r\n   * @param[in]  srcALen  length of the first input sequence.\r\n   * @param[in]  pSrcB    points to the second input sequence.\r\n   * @param[in]  srcBLen  length of the second input sequence.\r\n   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.\r\n   */\r\n  void arm_conv_fast_q31(\r\n  q31_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q31_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q31_t * pDst);\r\n\r\n\r\n    /**\r\n   * @brief Convolution of Q7 sequences.\r\n   * @param[in]  pSrcA      points to the first input sequence.\r\n   * @param[in]  srcALen    length of the first input sequence.\r\n   * @param[in]  pSrcB      points to the second input sequence.\r\n   * @param[in]  srcBLen    length of the second input sequence.\r\n   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.\r\n   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r\n   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\r\n   */\r\n  void arm_conv_opt_q7(\r\n  q7_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q7_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q7_t * pDst,\r\n  q15_t * pScratch1,\r\n  q15_t * pScratch2);\r\n\r\n\r\n  /**\r\n   * @brief Convolution of Q7 sequences.\r\n   * @param[in]  pSrcA    points to the first input sequence.\r\n   * @param[in]  srcALen  length of the first input sequence.\r\n   * @param[in]  pSrcB    points to the second input sequence.\r\n   * @param[in]  srcBLen  length of the second input sequence.\r\n   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.\r\n   */\r\n  void arm_conv_q7(\r\n  q7_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q7_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q7_t * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Partial convolution of floating-point sequences.\r\n   * @param[in]  pSrcA       points to the first input sequence.\r\n   * @param[in]  srcALen     length of the first input sequence.\r\n   * @param[in]  pSrcB       points to the second input sequence.\r\n   * @param[in]  srcBLen     length of the second input sequence.\r\n   * @param[out] pDst        points to the block of output data\r\n   * @param[in]  firstIndex  is the first output sample to start with.\r\n   * @param[in]  numPoints   is the number of output points to be computed.\r\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r\n   */\r\n  arm_status arm_conv_partial_f32(\r\n  float32_t * pSrcA,\r\n  uint32_t srcALen,\r\n  float32_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  float32_t * pDst,\r\n  uint32_t firstIndex,\r\n  uint32_t numPoints);\r\n\r\n\r\n  /**\r\n   * @brief Partial convolution of Q15 sequences.\r\n   * @param[in]  pSrcA       points to the first input sequence.\r\n   * @param[in]  srcALen     length of the first input sequence.\r\n   * @param[in]  pSrcB       points to the second input sequence.\r\n   * @param[in]  srcBLen     length of the second input sequence.\r\n   * @param[out] pDst        points to the block of output data\r\n   * @param[in]  firstIndex  is the first output sample to start with.\r\n   * @param[in]  numPoints   is the number of output points to be computed.\r\n   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r\n   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).\r\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r\n   */\r\n  arm_status arm_conv_partial_opt_q15(\r\n  q15_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q15_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q15_t * pDst,\r\n  uint32_t firstIndex,\r\n  uint32_t numPoints,\r\n  q15_t * pScratch1,\r\n  q15_t * pScratch2);\r\n\r\n\r\n  /**\r\n   * @brief Partial convolution of Q15 sequences.\r\n   * @param[in]  pSrcA       points to the first input sequence.\r\n   * @param[in]  srcALen     length of the first input sequence.\r\n   * @param[in]  pSrcB       points to the second input sequence.\r\n   * @param[in]  srcBLen     length of the second input sequence.\r\n   * @param[out] pDst        points to the block of output data\r\n   * @param[in]  firstIndex  is the first output sample to start with.\r\n   * @param[in]  numPoints   is the number of output points to be computed.\r\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r\n   */\r\n  arm_status arm_conv_partial_q15(\r\n  q15_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q15_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q15_t * pDst,\r\n  uint32_t firstIndex,\r\n  uint32_t numPoints);\r\n\r\n\r\n  /**\r\n   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r\n   * @param[in]  pSrcA       points to the first input sequence.\r\n   * @param[in]  srcALen     length of the first input sequence.\r\n   * @param[in]  pSrcB       points to the second input sequence.\r\n   * @param[in]  srcBLen     length of the second input sequence.\r\n   * @param[out] pDst        points to the block of output data\r\n   * @param[in]  firstIndex  is the first output sample to start with.\r\n   * @param[in]  numPoints   is the number of output points to be computed.\r\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r\n   */\r\n  arm_status arm_conv_partial_fast_q15(\r\n  q15_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q15_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q15_t * pDst,\r\n  uint32_t firstIndex,\r\n  uint32_t numPoints);\r\n\r\n\r\n  /**\r\n   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r\n   * @param[in]  pSrcA       points to the first input sequence.\r\n   * @param[in]  srcALen     length of the first input sequence.\r\n   * @param[in]  pSrcB       points to the second input sequence.\r\n   * @param[in]  srcBLen     length of the second input sequence.\r\n   * @param[out] pDst        points to the block of output data\r\n   * @param[in]  firstIndex  is the first output sample to start with.\r\n   * @param[in]  numPoints   is the number of output points to be computed.\r\n   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r\n   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).\r\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r\n   */\r\n  arm_status arm_conv_partial_fast_opt_q15(\r\n  q15_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q15_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q15_t * pDst,\r\n  uint32_t firstIndex,\r\n  uint32_t numPoints,\r\n  q15_t * pScratch1,\r\n  q15_t * pScratch2);\r\n\r\n\r\n  /**\r\n   * @brief Partial convolution of Q31 sequences.\r\n   * @param[in]  pSrcA       points to the first input sequence.\r\n   * @param[in]  srcALen     length of the first input sequence.\r\n   * @param[in]  pSrcB       points to the second input sequence.\r\n   * @param[in]  srcBLen     length of the second input sequence.\r\n   * @param[out] pDst        points to the block of output data\r\n   * @param[in]  firstIndex  is the first output sample to start with.\r\n   * @param[in]  numPoints   is the number of output points to be computed.\r\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r\n   */\r\n  arm_status arm_conv_partial_q31(\r\n  q31_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q31_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q31_t * pDst,\r\n  uint32_t firstIndex,\r\n  uint32_t numPoints);\r\n\r\n\r\n  /**\r\n   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r\n   * @param[in]  pSrcA       points to the first input sequence.\r\n   * @param[in]  srcALen     length of the first input sequence.\r\n   * @param[in]  pSrcB       points to the second input sequence.\r\n   * @param[in]  srcBLen     length of the second input sequence.\r\n   * @param[out] pDst        points to the block of output data\r\n   * @param[in]  firstIndex  is the first output sample to start with.\r\n   * @param[in]  numPoints   is the number of output points to be computed.\r\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r\n   */\r\n  arm_status arm_conv_partial_fast_q31(\r\n  q31_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q31_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q31_t * pDst,\r\n  uint32_t firstIndex,\r\n  uint32_t numPoints);\r\n\r\n\r\n  /**\r\n   * @brief Partial convolution of Q7 sequences\r\n   * @param[in]  pSrcA       points to the first input sequence.\r\n   * @param[in]  srcALen     length of the first input sequence.\r\n   * @param[in]  pSrcB       points to the second input sequence.\r\n   * @param[in]  srcBLen     length of the second input sequence.\r\n   * @param[out] pDst        points to the block of output data\r\n   * @param[in]  firstIndex  is the first output sample to start with.\r\n   * @param[in]  numPoints   is the number of output points to be computed.\r\n   * @param[in]  pScratch1   points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r\n   * @param[in]  pScratch2   points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\r\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r\n   */\r\n  arm_status arm_conv_partial_opt_q7(\r\n  q7_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q7_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q7_t * pDst,\r\n  uint32_t firstIndex,\r\n  uint32_t numPoints,\r\n  q15_t * pScratch1,\r\n  q15_t * pScratch2);\r\n\r\n\r\n/**\r\n   * @brief Partial convolution of Q7 sequences.\r\n   * @param[in]  pSrcA       points to the first input sequence.\r\n   * @param[in]  srcALen     length of the first input sequence.\r\n   * @param[in]  pSrcB       points to the second input sequence.\r\n   * @param[in]  srcBLen     length of the second input sequence.\r\n   * @param[out] pDst        points to the block of output data\r\n   * @param[in]  firstIndex  is the first output sample to start with.\r\n   * @param[in]  numPoints   is the number of output points to be computed.\r\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r\n   */\r\n  arm_status arm_conv_partial_q7(\r\n  q7_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q7_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q7_t * pDst,\r\n  uint32_t firstIndex,\r\n  uint32_t numPoints);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the Q15 FIR decimator.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint8_t M;                  /**< decimation factor. */\r\n    uint16_t numTaps;           /**< number of coefficients in the filter. */\r\n    q15_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/\r\n    q15_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n  } arm_fir_decimate_instance_q15;\r\n\r\n  /**\r\n   * @brief Instance structure for the Q31 FIR decimator.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint8_t M;                  /**< decimation factor. */\r\n    uint16_t numTaps;           /**< number of coefficients in the filter. */\r\n    q31_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/\r\n    q31_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n  } arm_fir_decimate_instance_q31;\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point FIR decimator.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint8_t M;                  /**< decimation factor. */\r\n    uint16_t numTaps;           /**< number of coefficients in the filter. */\r\n    float32_t *pCoeffs;         /**< points to the coefficient array. The array is of length numTaps.*/\r\n    float32_t *pState;          /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n  } arm_fir_decimate_instance_f32;\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the floating-point FIR decimator.\r\n   * @param[in]  S          points to an instance of the floating-point FIR decimator structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data\r\n   * @param[in]  blockSize  number of input samples to process per call.\r\n   */\r\n  void arm_fir_decimate_f32(\r\n  const arm_fir_decimate_instance_f32 * S,\r\n  float32_t * pSrc,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the floating-point FIR decimator.\r\n   * @param[in,out] S          points to an instance of the floating-point FIR decimator structure.\r\n   * @param[in]     numTaps    number of coefficients in the filter.\r\n   * @param[in]     M          decimation factor.\r\n   * @param[in]     pCoeffs    points to the filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   * @param[in]     blockSize  number of input samples to process per call.\r\n   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r\n   * <code>blockSize</code> is not a multiple of <code>M</code>.\r\n   */\r\n  arm_status arm_fir_decimate_init_f32(\r\n  arm_fir_decimate_instance_f32 * S,\r\n  uint16_t numTaps,\r\n  uint8_t M,\r\n  float32_t * pCoeffs,\r\n  float32_t * pState,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q15 FIR decimator.\r\n   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data\r\n   * @param[in]  blockSize  number of input samples to process per call.\r\n   */\r\n  void arm_fir_decimate_q15(\r\n  const arm_fir_decimate_instance_q15 * S,\r\n  q15_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\r\n   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data\r\n   * @param[in]  blockSize  number of input samples to process per call.\r\n   */\r\n  void arm_fir_decimate_fast_q15(\r\n  const arm_fir_decimate_instance_q15 * S,\r\n  q15_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the Q15 FIR decimator.\r\n   * @param[in,out] S          points to an instance of the Q15 FIR decimator structure.\r\n   * @param[in]     numTaps    number of coefficients in the filter.\r\n   * @param[in]     M          decimation factor.\r\n   * @param[in]     pCoeffs    points to the filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   * @param[in]     blockSize  number of input samples to process per call.\r\n   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r\n   * <code>blockSize</code> is not a multiple of <code>M</code>.\r\n   */\r\n  arm_status arm_fir_decimate_init_q15(\r\n  arm_fir_decimate_instance_q15 * S,\r\n  uint16_t numTaps,\r\n  uint8_t M,\r\n  q15_t * pCoeffs,\r\n  q15_t * pState,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q31 FIR decimator.\r\n   * @param[in]  S     points to an instance of the Q31 FIR decimator structure.\r\n   * @param[in]  pSrc  points to the block of input data.\r\n   * @param[out] pDst  points to the block of output data\r\n   * @param[in] blockSize number of input samples to process per call.\r\n   */\r\n  void arm_fir_decimate_q31(\r\n  const arm_fir_decimate_instance_q31 * S,\r\n  q31_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n  /**\r\n   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\r\n   * @param[in]  S          points to an instance of the Q31 FIR decimator structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data\r\n   * @param[in]  blockSize  number of input samples to process per call.\r\n   */\r\n  void arm_fir_decimate_fast_q31(\r\n  arm_fir_decimate_instance_q31 * S,\r\n  q31_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the Q31 FIR decimator.\r\n   * @param[in,out] S          points to an instance of the Q31 FIR decimator structure.\r\n   * @param[in]     numTaps    number of coefficients in the filter.\r\n   * @param[in]     M          decimation factor.\r\n   * @param[in]     pCoeffs    points to the filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   * @param[in]     blockSize  number of input samples to process per call.\r\n   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r\n   * <code>blockSize</code> is not a multiple of <code>M</code>.\r\n   */\r\n  arm_status arm_fir_decimate_init_q31(\r\n  arm_fir_decimate_instance_q31 * S,\r\n  uint16_t numTaps,\r\n  uint8_t M,\r\n  q31_t * pCoeffs,\r\n  q31_t * pState,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the Q15 FIR interpolator.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint8_t L;                      /**< upsample factor. */\r\n    uint16_t phaseLength;           /**< length of each polyphase filter component. */\r\n    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */\r\n    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\r\n  } arm_fir_interpolate_instance_q15;\r\n\r\n  /**\r\n   * @brief Instance structure for the Q31 FIR interpolator.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint8_t L;                      /**< upsample factor. */\r\n    uint16_t phaseLength;           /**< length of each polyphase filter component. */\r\n    q31_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */\r\n    q31_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\r\n  } arm_fir_interpolate_instance_q31;\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point FIR interpolator.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint8_t L;                     /**< upsample factor. */\r\n    uint16_t phaseLength;          /**< length of each polyphase filter component. */\r\n    float32_t *pCoeffs;            /**< points to the coefficient array. The array is of length L*phaseLength. */\r\n    float32_t *pState;             /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */\r\n  } arm_fir_interpolate_instance_f32;\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q15 FIR interpolator.\r\n   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of input samples to process per call.\r\n   */\r\n  void arm_fir_interpolate_q15(\r\n  const arm_fir_interpolate_instance_q15 * S,\r\n  q15_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the Q15 FIR interpolator.\r\n   * @param[in,out] S          points to an instance of the Q15 FIR interpolator structure.\r\n   * @param[in]     L          upsample factor.\r\n   * @param[in]     numTaps    number of filter coefficients in the filter.\r\n   * @param[in]     pCoeffs    points to the filter coefficient buffer.\r\n   * @param[in]     pState     points to the state buffer.\r\n   * @param[in]     blockSize  number of input samples to process per call.\r\n   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r\n   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r\n   */\r\n  arm_status arm_fir_interpolate_init_q15(\r\n  arm_fir_interpolate_instance_q15 * S,\r\n  uint8_t L,\r\n  uint16_t numTaps,\r\n  q15_t * pCoeffs,\r\n  q15_t * pState,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q31 FIR interpolator.\r\n   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of input samples to process per call.\r\n   */\r\n  void arm_fir_interpolate_q31(\r\n  const arm_fir_interpolate_instance_q31 * S,\r\n  q31_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the Q31 FIR interpolator.\r\n   * @param[in,out] S          points to an instance of the Q31 FIR interpolator structure.\r\n   * @param[in]     L          upsample factor.\r\n   * @param[in]     numTaps    number of filter coefficients in the filter.\r\n   * @param[in]     pCoeffs    points to the filter coefficient buffer.\r\n   * @param[in]     pState     points to the state buffer.\r\n   * @param[in]     blockSize  number of input samples to process per call.\r\n   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r\n   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r\n   */\r\n  arm_status arm_fir_interpolate_init_q31(\r\n  arm_fir_interpolate_instance_q31 * S,\r\n  uint8_t L,\r\n  uint16_t numTaps,\r\n  q31_t * pCoeffs,\r\n  q31_t * pState,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the floating-point FIR interpolator.\r\n   * @param[in]  S          points to an instance of the floating-point FIR interpolator structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of input samples to process per call.\r\n   */\r\n  void arm_fir_interpolate_f32(\r\n  const arm_fir_interpolate_instance_f32 * S,\r\n  float32_t * pSrc,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the floating-point FIR interpolator.\r\n   * @param[in,out] S          points to an instance of the floating-point FIR interpolator structure.\r\n   * @param[in]     L          upsample factor.\r\n   * @param[in]     numTaps    number of filter coefficients in the filter.\r\n   * @param[in]     pCoeffs    points to the filter coefficient buffer.\r\n   * @param[in]     pState     points to the state buffer.\r\n   * @param[in]     blockSize  number of input samples to process per call.\r\n   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r\n   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r\n   */\r\n  arm_status arm_fir_interpolate_init_f32(\r\n  arm_fir_interpolate_instance_f32 * S,\r\n  uint8_t L,\r\n  uint16_t numTaps,\r\n  float32_t * pCoeffs,\r\n  float32_t * pState,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the high precision Q31 Biquad cascade filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */\r\n    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */\r\n    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */\r\n    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */\r\n  } arm_biquad_cas_df1_32x64_ins_q31;\r\n\r\n\r\n  /**\r\n   * @param[in]  S          points to an instance of the high precision Q31 Biquad cascade filter structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_biquad_cas_df1_32x64_q31(\r\n  const arm_biquad_cas_df1_32x64_ins_q31 * S,\r\n  q31_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @param[in,out] S          points to an instance of the high precision Q31 Biquad cascade filter structure.\r\n   * @param[in]     numStages  number of 2nd order stages in the filter.\r\n   * @param[in]     pCoeffs    points to the filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   * @param[in]     postShift  shift to be applied to the output. Varies according to the coefficients format\r\n   */\r\n  void arm_biquad_cas_df1_32x64_init_q31(\r\n  arm_biquad_cas_df1_32x64_ins_q31 * S,\r\n  uint8_t numStages,\r\n  q31_t * pCoeffs,\r\n  q63_t * pState,\r\n  uint8_t postShift);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */\r\n    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */\r\n    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */\r\n  } arm_biquad_cascade_df2T_instance_f32;\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */\r\n    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */\r\n    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */\r\n  } arm_biquad_cascade_stereo_df2T_instance_f32;\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */\r\n    float64_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */\r\n    float64_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */\r\n  } arm_biquad_cascade_df2T_instance_f64;\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.\r\n   * @param[in]  S          points to an instance of the filter data structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_biquad_cascade_df2T_f32(\r\n  const arm_biquad_cascade_df2T_instance_f32 * S,\r\n  float32_t * pSrc,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels\r\n   * @param[in]  S          points to an instance of the filter data structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_biquad_cascade_stereo_df2T_f32(\r\n  const arm_biquad_cascade_stereo_df2T_instance_f32 * S,\r\n  float32_t * pSrc,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.\r\n   * @param[in]  S          points to an instance of the filter data structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_biquad_cascade_df2T_f64(\r\n  const arm_biquad_cascade_df2T_instance_f64 * S,\r\n  float64_t * pSrc,\r\n  float64_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r\n   * @param[in,out] S          points to an instance of the filter data structure.\r\n   * @param[in]     numStages  number of 2nd order stages in the filter.\r\n   * @param[in]     pCoeffs    points to the filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   */\r\n  void arm_biquad_cascade_df2T_init_f32(\r\n  arm_biquad_cascade_df2T_instance_f32 * S,\r\n  uint8_t numStages,\r\n  float32_t * pCoeffs,\r\n  float32_t * pState);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r\n   * @param[in,out] S          points to an instance of the filter data structure.\r\n   * @param[in]     numStages  number of 2nd order stages in the filter.\r\n   * @param[in]     pCoeffs    points to the filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   */\r\n  void arm_biquad_cascade_stereo_df2T_init_f32(\r\n  arm_biquad_cascade_stereo_df2T_instance_f32 * S,\r\n  uint8_t numStages,\r\n  float32_t * pCoeffs,\r\n  float32_t * pState);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r\n   * @param[in,out] S          points to an instance of the filter data structure.\r\n   * @param[in]     numStages  number of 2nd order stages in the filter.\r\n   * @param[in]     pCoeffs    points to the filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   */\r\n  void arm_biquad_cascade_df2T_init_f64(\r\n  arm_biquad_cascade_df2T_instance_f64 * S,\r\n  uint8_t numStages,\r\n  float64_t * pCoeffs,\r\n  float64_t * pState);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the Q15 FIR lattice filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numStages;                  /**< number of filter stages. */\r\n    q15_t *pState;                       /**< points to the state variable array. The array is of length numStages. */\r\n    q15_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */\r\n  } arm_fir_lattice_instance_q15;\r\n\r\n  /**\r\n   * @brief Instance structure for the Q31 FIR lattice filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numStages;                  /**< number of filter stages. */\r\n    q31_t *pState;                       /**< points to the state variable array. The array is of length numStages. */\r\n    q31_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */\r\n  } arm_fir_lattice_instance_q31;\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point FIR lattice filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numStages;                  /**< number of filter stages. */\r\n    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */\r\n    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */\r\n  } arm_fir_lattice_instance_f32;\r\n\r\n\r\n  /**\r\n   * @brief Initialization function for the Q15 FIR lattice filter.\r\n   * @param[in] S          points to an instance of the Q15 FIR lattice structure.\r\n   * @param[in] numStages  number of filter stages.\r\n   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.\r\n   * @param[in] pState     points to the state buffer.  The array is of length numStages.\r\n   */\r\n  void arm_fir_lattice_init_q15(\r\n  arm_fir_lattice_instance_q15 * S,\r\n  uint16_t numStages,\r\n  q15_t * pCoeffs,\r\n  q15_t * pState);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q15 FIR lattice filter.\r\n   * @param[in]  S          points to an instance of the Q15 FIR lattice structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_fir_lattice_q15(\r\n  const arm_fir_lattice_instance_q15 * S,\r\n  q15_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Initialization function for the Q31 FIR lattice filter.\r\n   * @param[in] S          points to an instance of the Q31 FIR lattice structure.\r\n   * @param[in] numStages  number of filter stages.\r\n   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.\r\n   * @param[in] pState     points to the state buffer.   The array is of length numStages.\r\n   */\r\n  void arm_fir_lattice_init_q31(\r\n  arm_fir_lattice_instance_q31 * S,\r\n  uint16_t numStages,\r\n  q31_t * pCoeffs,\r\n  q31_t * pState);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q31 FIR lattice filter.\r\n   * @param[in]  S          points to an instance of the Q31 FIR lattice structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_fir_lattice_q31(\r\n  const arm_fir_lattice_instance_q31 * S,\r\n  q31_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n/**\r\n * @brief Initialization function for the floating-point FIR lattice filter.\r\n * @param[in] S          points to an instance of the floating-point FIR lattice structure.\r\n * @param[in] numStages  number of filter stages.\r\n * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.\r\n * @param[in] pState     points to the state buffer.  The array is of length numStages.\r\n */\r\n  void arm_fir_lattice_init_f32(\r\n  arm_fir_lattice_instance_f32 * S,\r\n  uint16_t numStages,\r\n  float32_t * pCoeffs,\r\n  float32_t * pState);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the floating-point FIR lattice filter.\r\n   * @param[in]  S          points to an instance of the floating-point FIR lattice structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_fir_lattice_f32(\r\n  const arm_fir_lattice_instance_f32 * S,\r\n  float32_t * pSrc,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the Q15 IIR lattice filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numStages;                  /**< number of stages in the filter. */\r\n    q15_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */\r\n    q15_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */\r\n    q15_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */\r\n  } arm_iir_lattice_instance_q15;\r\n\r\n  /**\r\n   * @brief Instance structure for the Q31 IIR lattice filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numStages;                  /**< number of stages in the filter. */\r\n    q31_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */\r\n    q31_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */\r\n    q31_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */\r\n  } arm_iir_lattice_instance_q31;\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point IIR lattice filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numStages;                  /**< number of stages in the filter. */\r\n    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages+blockSize. */\r\n    float32_t *pkCoeffs;                 /**< points to the reflection coefficient array. The array is of length numStages. */\r\n    float32_t *pvCoeffs;                 /**< points to the ladder coefficient array. The array is of length numStages+1. */\r\n  } arm_iir_lattice_instance_f32;\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the floating-point IIR lattice filter.\r\n   * @param[in]  S          points to an instance of the floating-point IIR lattice structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_iir_lattice_f32(\r\n  const arm_iir_lattice_instance_f32 * S,\r\n  float32_t * pSrc,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Initialization function for the floating-point IIR lattice filter.\r\n   * @param[in] S          points to an instance of the floating-point IIR lattice structure.\r\n   * @param[in] numStages  number of stages in the filter.\r\n   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.\r\n   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.\r\n   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize-1.\r\n   * @param[in] blockSize  number of samples to process.\r\n   */\r\n  void arm_iir_lattice_init_f32(\r\n  arm_iir_lattice_instance_f32 * S,\r\n  uint16_t numStages,\r\n  float32_t * pkCoeffs,\r\n  float32_t * pvCoeffs,\r\n  float32_t * pState,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q31 IIR lattice filter.\r\n   * @param[in]  S          points to an instance of the Q31 IIR lattice structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_iir_lattice_q31(\r\n  const arm_iir_lattice_instance_q31 * S,\r\n  q31_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Initialization function for the Q31 IIR lattice filter.\r\n   * @param[in] S          points to an instance of the Q31 IIR lattice structure.\r\n   * @param[in] numStages  number of stages in the filter.\r\n   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.\r\n   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.\r\n   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize.\r\n   * @param[in] blockSize  number of samples to process.\r\n   */\r\n  void arm_iir_lattice_init_q31(\r\n  arm_iir_lattice_instance_q31 * S,\r\n  uint16_t numStages,\r\n  q31_t * pkCoeffs,\r\n  q31_t * pvCoeffs,\r\n  q31_t * pState,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q15 IIR lattice filter.\r\n   * @param[in]  S          points to an instance of the Q15 IIR lattice structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[out] pDst       points to the block of output data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_iir_lattice_q15(\r\n  const arm_iir_lattice_instance_q15 * S,\r\n  q15_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n/**\r\n * @brief Initialization function for the Q15 IIR lattice filter.\r\n * @param[in] S          points to an instance of the fixed-point Q15 IIR lattice structure.\r\n * @param[in] numStages  number of stages in the filter.\r\n * @param[in] pkCoeffs   points to reflection coefficient buffer.  The array is of length numStages.\r\n * @param[in] pvCoeffs   points to ladder coefficient buffer.  The array is of length numStages+1.\r\n * @param[in] pState     points to state buffer.  The array is of length numStages+blockSize.\r\n * @param[in] blockSize  number of samples to process per call.\r\n */\r\n  void arm_iir_lattice_init_q15(\r\n  arm_iir_lattice_instance_q15 * S,\r\n  uint16_t numStages,\r\n  q15_t * pkCoeffs,\r\n  q15_t * pvCoeffs,\r\n  q15_t * pState,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point LMS filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numTaps;    /**< number of coefficients in the filter. */\r\n    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */\r\n    float32_t mu;        /**< step size that controls filter coefficient updates. */\r\n  } arm_lms_instance_f32;\r\n\r\n\r\n  /**\r\n   * @brief Processing function for floating-point LMS filter.\r\n   * @param[in]  S          points to an instance of the floating-point LMS filter structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[in]  pRef       points to the block of reference data.\r\n   * @param[out] pOut       points to the block of output data.\r\n   * @param[out] pErr       points to the block of error data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_lms_f32(\r\n  const arm_lms_instance_f32 * S,\r\n  float32_t * pSrc,\r\n  float32_t * pRef,\r\n  float32_t * pOut,\r\n  float32_t * pErr,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Initialization function for floating-point LMS filter.\r\n   * @param[in] S          points to an instance of the floating-point LMS filter structure.\r\n   * @param[in] numTaps    number of filter coefficients.\r\n   * @param[in] pCoeffs    points to the coefficient buffer.\r\n   * @param[in] pState     points to state buffer.\r\n   * @param[in] mu         step size that controls filter coefficient updates.\r\n   * @param[in] blockSize  number of samples to process.\r\n   */\r\n  void arm_lms_init_f32(\r\n  arm_lms_instance_f32 * S,\r\n  uint16_t numTaps,\r\n  float32_t * pCoeffs,\r\n  float32_t * pState,\r\n  float32_t mu,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the Q15 LMS filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numTaps;    /**< number of coefficients in the filter. */\r\n    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */\r\n    q15_t mu;            /**< step size that controls filter coefficient updates. */\r\n    uint32_t postShift;  /**< bit shift applied to coefficients. */\r\n  } arm_lms_instance_q15;\r\n\r\n\r\n  /**\r\n   * @brief Initialization function for the Q15 LMS filter.\r\n   * @param[in] S          points to an instance of the Q15 LMS filter structure.\r\n   * @param[in] numTaps    number of filter coefficients.\r\n   * @param[in] pCoeffs    points to the coefficient buffer.\r\n   * @param[in] pState     points to the state buffer.\r\n   * @param[in] mu         step size that controls filter coefficient updates.\r\n   * @param[in] blockSize  number of samples to process.\r\n   * @param[in] postShift  bit shift applied to coefficients.\r\n   */\r\n  void arm_lms_init_q15(\r\n  arm_lms_instance_q15 * S,\r\n  uint16_t numTaps,\r\n  q15_t * pCoeffs,\r\n  q15_t * pState,\r\n  q15_t mu,\r\n  uint32_t blockSize,\r\n  uint32_t postShift);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for Q15 LMS filter.\r\n   * @param[in]  S          points to an instance of the Q15 LMS filter structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[in]  pRef       points to the block of reference data.\r\n   * @param[out] pOut       points to the block of output data.\r\n   * @param[out] pErr       points to the block of error data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_lms_q15(\r\n  const arm_lms_instance_q15 * S,\r\n  q15_t * pSrc,\r\n  q15_t * pRef,\r\n  q15_t * pOut,\r\n  q15_t * pErr,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the Q31 LMS filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numTaps;    /**< number of coefficients in the filter. */\r\n    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */\r\n    q31_t mu;            /**< step size that controls filter coefficient updates. */\r\n    uint32_t postShift;  /**< bit shift applied to coefficients. */\r\n  } arm_lms_instance_q31;\r\n\r\n\r\n  /**\r\n   * @brief Processing function for Q31 LMS filter.\r\n   * @param[in]  S          points to an instance of the Q15 LMS filter structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[in]  pRef       points to the block of reference data.\r\n   * @param[out] pOut       points to the block of output data.\r\n   * @param[out] pErr       points to the block of error data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_lms_q31(\r\n  const arm_lms_instance_q31 * S,\r\n  q31_t * pSrc,\r\n  q31_t * pRef,\r\n  q31_t * pOut,\r\n  q31_t * pErr,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Initialization function for Q31 LMS filter.\r\n   * @param[in] S          points to an instance of the Q31 LMS filter structure.\r\n   * @param[in] numTaps    number of filter coefficients.\r\n   * @param[in] pCoeffs    points to coefficient buffer.\r\n   * @param[in] pState     points to state buffer.\r\n   * @param[in] mu         step size that controls filter coefficient updates.\r\n   * @param[in] blockSize  number of samples to process.\r\n   * @param[in] postShift  bit shift applied to coefficients.\r\n   */\r\n  void arm_lms_init_q31(\r\n  arm_lms_instance_q31 * S,\r\n  uint16_t numTaps,\r\n  q31_t * pCoeffs,\r\n  q31_t * pState,\r\n  q31_t mu,\r\n  uint32_t blockSize,\r\n  uint32_t postShift);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point normalized LMS filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numTaps;     /**< number of coefficients in the filter. */\r\n    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */\r\n    float32_t mu;         /**< step size that control filter coefficient updates. */\r\n    float32_t energy;     /**< saves previous frame energy. */\r\n    float32_t x0;         /**< saves previous input sample. */\r\n  } arm_lms_norm_instance_f32;\r\n\r\n\r\n  /**\r\n   * @brief Processing function for floating-point normalized LMS filter.\r\n   * @param[in]  S          points to an instance of the floating-point normalized LMS filter structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[in]  pRef       points to the block of reference data.\r\n   * @param[out] pOut       points to the block of output data.\r\n   * @param[out] pErr       points to the block of error data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_lms_norm_f32(\r\n  arm_lms_norm_instance_f32 * S,\r\n  float32_t * pSrc,\r\n  float32_t * pRef,\r\n  float32_t * pOut,\r\n  float32_t * pErr,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Initialization function for floating-point normalized LMS filter.\r\n   * @param[in] S          points to an instance of the floating-point LMS filter structure.\r\n   * @param[in] numTaps    number of filter coefficients.\r\n   * @param[in] pCoeffs    points to coefficient buffer.\r\n   * @param[in] pState     points to state buffer.\r\n   * @param[in] mu         step size that controls filter coefficient updates.\r\n   * @param[in] blockSize  number of samples to process.\r\n   */\r\n  void arm_lms_norm_init_f32(\r\n  arm_lms_norm_instance_f32 * S,\r\n  uint16_t numTaps,\r\n  float32_t * pCoeffs,\r\n  float32_t * pState,\r\n  float32_t mu,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the Q31 normalized LMS filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numTaps;     /**< number of coefficients in the filter. */\r\n    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */\r\n    q31_t mu;             /**< step size that controls filter coefficient updates. */\r\n    uint8_t postShift;    /**< bit shift applied to coefficients. */\r\n    q31_t *recipTable;    /**< points to the reciprocal initial value table. */\r\n    q31_t energy;         /**< saves previous frame energy. */\r\n    q31_t x0;             /**< saves previous input sample. */\r\n  } arm_lms_norm_instance_q31;\r\n\r\n\r\n  /**\r\n   * @brief Processing function for Q31 normalized LMS filter.\r\n   * @param[in]  S          points to an instance of the Q31 normalized LMS filter structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[in]  pRef       points to the block of reference data.\r\n   * @param[out] pOut       points to the block of output data.\r\n   * @param[out] pErr       points to the block of error data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_lms_norm_q31(\r\n  arm_lms_norm_instance_q31 * S,\r\n  q31_t * pSrc,\r\n  q31_t * pRef,\r\n  q31_t * pOut,\r\n  q31_t * pErr,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Initialization function for Q31 normalized LMS filter.\r\n   * @param[in] S          points to an instance of the Q31 normalized LMS filter structure.\r\n   * @param[in] numTaps    number of filter coefficients.\r\n   * @param[in] pCoeffs    points to coefficient buffer.\r\n   * @param[in] pState     points to state buffer.\r\n   * @param[in] mu         step size that controls filter coefficient updates.\r\n   * @param[in] blockSize  number of samples to process.\r\n   * @param[in] postShift  bit shift applied to coefficients.\r\n   */\r\n  void arm_lms_norm_init_q31(\r\n  arm_lms_norm_instance_q31 * S,\r\n  uint16_t numTaps,\r\n  q31_t * pCoeffs,\r\n  q31_t * pState,\r\n  q31_t mu,\r\n  uint32_t blockSize,\r\n  uint8_t postShift);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the Q15 normalized LMS filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numTaps;     /**< Number of coefficients in the filter. */\r\n    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r\n    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */\r\n    q15_t mu;             /**< step size that controls filter coefficient updates. */\r\n    uint8_t postShift;    /**< bit shift applied to coefficients. */\r\n    q15_t *recipTable;    /**< Points to the reciprocal initial value table. */\r\n    q15_t energy;         /**< saves previous frame energy. */\r\n    q15_t x0;             /**< saves previous input sample. */\r\n  } arm_lms_norm_instance_q15;\r\n\r\n\r\n  /**\r\n   * @brief Processing function for Q15 normalized LMS filter.\r\n   * @param[in]  S          points to an instance of the Q15 normalized LMS filter structure.\r\n   * @param[in]  pSrc       points to the block of input data.\r\n   * @param[in]  pRef       points to the block of reference data.\r\n   * @param[out] pOut       points to the block of output data.\r\n   * @param[out] pErr       points to the block of error data.\r\n   * @param[in]  blockSize  number of samples to process.\r\n   */\r\n  void arm_lms_norm_q15(\r\n  arm_lms_norm_instance_q15 * S,\r\n  q15_t * pSrc,\r\n  q15_t * pRef,\r\n  q15_t * pOut,\r\n  q15_t * pErr,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Initialization function for Q15 normalized LMS filter.\r\n   * @param[in] S          points to an instance of the Q15 normalized LMS filter structure.\r\n   * @param[in] numTaps    number of filter coefficients.\r\n   * @param[in] pCoeffs    points to coefficient buffer.\r\n   * @param[in] pState     points to state buffer.\r\n   * @param[in] mu         step size that controls filter coefficient updates.\r\n   * @param[in] blockSize  number of samples to process.\r\n   * @param[in] postShift  bit shift applied to coefficients.\r\n   */\r\n  void arm_lms_norm_init_q15(\r\n  arm_lms_norm_instance_q15 * S,\r\n  uint16_t numTaps,\r\n  q15_t * pCoeffs,\r\n  q15_t * pState,\r\n  q15_t mu,\r\n  uint32_t blockSize,\r\n  uint8_t postShift);\r\n\r\n\r\n  /**\r\n   * @brief Correlation of floating-point sequences.\r\n   * @param[in]  pSrcA    points to the first input sequence.\r\n   * @param[in]  srcALen  length of the first input sequence.\r\n   * @param[in]  pSrcB    points to the second input sequence.\r\n   * @param[in]  srcBLen  length of the second input sequence.\r\n   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\r\n   */\r\n  void arm_correlate_f32(\r\n  float32_t * pSrcA,\r\n  uint32_t srcALen,\r\n  float32_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  float32_t * pDst);\r\n\r\n\r\n   /**\r\n   * @brief Correlation of Q15 sequences\r\n   * @param[in]  pSrcA     points to the first input sequence.\r\n   * @param[in]  srcALen   length of the first input sequence.\r\n   * @param[in]  pSrcB     points to the second input sequence.\r\n   * @param[in]  srcBLen   length of the second input sequence.\r\n   * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\r\n   * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r\n   */\r\n  void arm_correlate_opt_q15(\r\n  q15_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q15_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q15_t * pDst,\r\n  q15_t * pScratch);\r\n\r\n\r\n  /**\r\n   * @brief Correlation of Q15 sequences.\r\n   * @param[in]  pSrcA    points to the first input sequence.\r\n   * @param[in]  srcALen  length of the first input sequence.\r\n   * @param[in]  pSrcB    points to the second input sequence.\r\n   * @param[in]  srcBLen  length of the second input sequence.\r\n   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\r\n   */\r\n\r\n  void arm_correlate_q15(\r\n  q15_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q15_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q15_t * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.\r\n   * @param[in]  pSrcA    points to the first input sequence.\r\n   * @param[in]  srcALen  length of the first input sequence.\r\n   * @param[in]  pSrcB    points to the second input sequence.\r\n   * @param[in]  srcBLen  length of the second input sequence.\r\n   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\r\n   */\r\n\r\n  void arm_correlate_fast_q15(\r\n  q15_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q15_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q15_t * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.\r\n   * @param[in]  pSrcA     points to the first input sequence.\r\n   * @param[in]  srcALen   length of the first input sequence.\r\n   * @param[in]  pSrcB     points to the second input sequence.\r\n   * @param[in]  srcBLen   length of the second input sequence.\r\n   * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\r\n   * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r\n   */\r\n  void arm_correlate_fast_opt_q15(\r\n  q15_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q15_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q15_t * pDst,\r\n  q15_t * pScratch);\r\n\r\n\r\n  /**\r\n   * @brief Correlation of Q31 sequences.\r\n   * @param[in]  pSrcA    points to the first input sequence.\r\n   * @param[in]  srcALen  length of the first input sequence.\r\n   * @param[in]  pSrcB    points to the second input sequence.\r\n   * @param[in]  srcBLen  length of the second input sequence.\r\n   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\r\n   */\r\n  void arm_correlate_q31(\r\n  q31_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q31_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q31_t * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r\n   * @param[in]  pSrcA    points to the first input sequence.\r\n   * @param[in]  srcALen  length of the first input sequence.\r\n   * @param[in]  pSrcB    points to the second input sequence.\r\n   * @param[in]  srcBLen  length of the second input sequence.\r\n   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\r\n   */\r\n  void arm_correlate_fast_q31(\r\n  q31_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q31_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q31_t * pDst);\r\n\r\n\r\n /**\r\n   * @brief Correlation of Q7 sequences.\r\n   * @param[in]  pSrcA      points to the first input sequence.\r\n   * @param[in]  srcALen    length of the first input sequence.\r\n   * @param[in]  pSrcB      points to the second input sequence.\r\n   * @param[in]  srcBLen    length of the second input sequence.\r\n   * @param[out] pDst       points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\r\n   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r\n   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\r\n   */\r\n  void arm_correlate_opt_q7(\r\n  q7_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q7_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q7_t * pDst,\r\n  q15_t * pScratch1,\r\n  q15_t * pScratch2);\r\n\r\n\r\n  /**\r\n   * @brief Correlation of Q7 sequences.\r\n   * @param[in]  pSrcA    points to the first input sequence.\r\n   * @param[in]  srcALen  length of the first input sequence.\r\n   * @param[in]  pSrcB    points to the second input sequence.\r\n   * @param[in]  srcBLen  length of the second input sequence.\r\n   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\r\n   */\r\n  void arm_correlate_q7(\r\n  q7_t * pSrcA,\r\n  uint32_t srcALen,\r\n  q7_t * pSrcB,\r\n  uint32_t srcBLen,\r\n  q7_t * pDst);\r\n\r\n\r\n  /**\r\n   * @brief Instance structure for the floating-point sparse FIR filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numTaps;             /**< number of coefficients in the filter. */\r\n    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */\r\n    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r\n    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/\r\n    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */\r\n    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */\r\n  } arm_fir_sparse_instance_f32;\r\n\r\n  /**\r\n   * @brief Instance structure for the Q31 sparse FIR filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numTaps;             /**< number of coefficients in the filter. */\r\n    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */\r\n    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r\n    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/\r\n    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */\r\n    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */\r\n  } arm_fir_sparse_instance_q31;\r\n\r\n  /**\r\n   * @brief Instance structure for the Q15 sparse FIR filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numTaps;             /**< number of coefficients in the filter. */\r\n    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */\r\n    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r\n    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/\r\n    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */\r\n    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */\r\n  } arm_fir_sparse_instance_q15;\r\n\r\n  /**\r\n   * @brief Instance structure for the Q7 sparse FIR filter.\r\n   */\r\n  typedef struct\r\n  {\r\n    uint16_t numTaps;             /**< number of coefficients in the filter. */\r\n    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */\r\n    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r\n    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/\r\n    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */\r\n    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */\r\n  } arm_fir_sparse_instance_q7;\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the floating-point sparse FIR filter.\r\n   * @param[in]  S           points to an instance of the floating-point sparse FIR structure.\r\n   * @param[in]  pSrc        points to the block of input data.\r\n   * @param[out] pDst        points to the block of output data\r\n   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.\r\n   * @param[in]  blockSize   number of input samples to process per call.\r\n   */\r\n  void arm_fir_sparse_f32(\r\n  arm_fir_sparse_instance_f32 * S,\r\n  float32_t * pSrc,\r\n  float32_t * pDst,\r\n  float32_t * pScratchIn,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the floating-point sparse FIR filter.\r\n   * @param[in,out] S          points to an instance of the floating-point sparse FIR structure.\r\n   * @param[in]     numTaps    number of nonzero coefficients in the filter.\r\n   * @param[in]     pCoeffs    points to the array of filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   * @param[in]     pTapDelay  points to the array of offset times.\r\n   * @param[in]     maxDelay   maximum offset time supported.\r\n   * @param[in]     blockSize  number of samples that will be processed per block.\r\n   */\r\n  void arm_fir_sparse_init_f32(\r\n  arm_fir_sparse_instance_f32 * S,\r\n  uint16_t numTaps,\r\n  float32_t * pCoeffs,\r\n  float32_t * pState,\r\n  int32_t * pTapDelay,\r\n  uint16_t maxDelay,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q31 sparse FIR filter.\r\n   * @param[in]  S           points to an instance of the Q31 sparse FIR structure.\r\n   * @param[in]  pSrc        points to the block of input data.\r\n   * @param[out] pDst        points to the block of output data\r\n   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.\r\n   * @param[in]  blockSize   number of input samples to process per call.\r\n   */\r\n  void arm_fir_sparse_q31(\r\n  arm_fir_sparse_instance_q31 * S,\r\n  q31_t * pSrc,\r\n  q31_t * pDst,\r\n  q31_t * pScratchIn,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the Q31 sparse FIR filter.\r\n   * @param[in,out] S          points to an instance of the Q31 sparse FIR structure.\r\n   * @param[in]     numTaps    number of nonzero coefficients in the filter.\r\n   * @param[in]     pCoeffs    points to the array of filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   * @param[in]     pTapDelay  points to the array of offset times.\r\n   * @param[in]     maxDelay   maximum offset time supported.\r\n   * @param[in]     blockSize  number of samples that will be processed per block.\r\n   */\r\n  void arm_fir_sparse_init_q31(\r\n  arm_fir_sparse_instance_q31 * S,\r\n  uint16_t numTaps,\r\n  q31_t * pCoeffs,\r\n  q31_t * pState,\r\n  int32_t * pTapDelay,\r\n  uint16_t maxDelay,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q15 sparse FIR filter.\r\n   * @param[in]  S            points to an instance of the Q15 sparse FIR structure.\r\n   * @param[in]  pSrc         points to the block of input data.\r\n   * @param[out] pDst         points to the block of output data\r\n   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.\r\n   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.\r\n   * @param[in]  blockSize    number of input samples to process per call.\r\n   */\r\n  void arm_fir_sparse_q15(\r\n  arm_fir_sparse_instance_q15 * S,\r\n  q15_t * pSrc,\r\n  q15_t * pDst,\r\n  q15_t * pScratchIn,\r\n  q31_t * pScratchOut,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the Q15 sparse FIR filter.\r\n   * @param[in,out] S          points to an instance of the Q15 sparse FIR structure.\r\n   * @param[in]     numTaps    number of nonzero coefficients in the filter.\r\n   * @param[in]     pCoeffs    points to the array of filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   * @param[in]     pTapDelay  points to the array of offset times.\r\n   * @param[in]     maxDelay   maximum offset time supported.\r\n   * @param[in]     blockSize  number of samples that will be processed per block.\r\n   */\r\n  void arm_fir_sparse_init_q15(\r\n  arm_fir_sparse_instance_q15 * S,\r\n  uint16_t numTaps,\r\n  q15_t * pCoeffs,\r\n  q15_t * pState,\r\n  int32_t * pTapDelay,\r\n  uint16_t maxDelay,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Processing function for the Q7 sparse FIR filter.\r\n   * @param[in]  S            points to an instance of the Q7 sparse FIR structure.\r\n   * @param[in]  pSrc         points to the block of input data.\r\n   * @param[out] pDst         points to the block of output data\r\n   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.\r\n   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.\r\n   * @param[in]  blockSize    number of input samples to process per call.\r\n   */\r\n  void arm_fir_sparse_q7(\r\n  arm_fir_sparse_instance_q7 * S,\r\n  q7_t * pSrc,\r\n  q7_t * pDst,\r\n  q7_t * pScratchIn,\r\n  q31_t * pScratchOut,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Initialization function for the Q7 sparse FIR filter.\r\n   * @param[in,out] S          points to an instance of the Q7 sparse FIR structure.\r\n   * @param[in]     numTaps    number of nonzero coefficients in the filter.\r\n   * @param[in]     pCoeffs    points to the array of filter coefficients.\r\n   * @param[in]     pState     points to the state buffer.\r\n   * @param[in]     pTapDelay  points to the array of offset times.\r\n   * @param[in]     maxDelay   maximum offset time supported.\r\n   * @param[in]     blockSize  number of samples that will be processed per block.\r\n   */\r\n  void arm_fir_sparse_init_q7(\r\n  arm_fir_sparse_instance_q7 * S,\r\n  uint16_t numTaps,\r\n  q7_t * pCoeffs,\r\n  q7_t * pState,\r\n  int32_t * pTapDelay,\r\n  uint16_t maxDelay,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Floating-point sin_cos function.\r\n   * @param[in]  theta   input value in degrees\r\n   * @param[out] pSinVal  points to the processed sine output.\r\n   * @param[out] pCosVal  points to the processed cos output.\r\n   */\r\n  void arm_sin_cos_f32(\r\n  float32_t theta,\r\n  float32_t * pSinVal,\r\n  float32_t * pCosVal);\r\n\r\n\r\n  /**\r\n   * @brief  Q31 sin_cos function.\r\n   * @param[in]  theta    scaled input value in degrees\r\n   * @param[out] pSinVal  points to the processed sine output.\r\n   * @param[out] pCosVal  points to the processed cosine output.\r\n   */\r\n  void arm_sin_cos_q31(\r\n  q31_t theta,\r\n  q31_t * pSinVal,\r\n  q31_t * pCosVal);\r\n\r\n\r\n  /**\r\n   * @brief  Floating-point complex conjugate.\r\n   * @param[in]  pSrc        points to the input vector\r\n   * @param[out] pDst        points to the output vector\r\n   * @param[in]  numSamples  number of complex samples in each vector\r\n   */\r\n  void arm_cmplx_conj_f32(\r\n  float32_t * pSrc,\r\n  float32_t * pDst,\r\n  uint32_t numSamples);\r\n\r\n  /**\r\n   * @brief  Q31 complex conjugate.\r\n   * @param[in]  pSrc        points to the input vector\r\n   * @param[out] pDst        points to the output vector\r\n   * @param[in]  numSamples  number of complex samples in each vector\r\n   */\r\n  void arm_cmplx_conj_q31(\r\n  q31_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t numSamples);\r\n\r\n\r\n  /**\r\n   * @brief  Q15 complex conjugate.\r\n   * @param[in]  pSrc        points to the input vector\r\n   * @param[out] pDst        points to the output vector\r\n   * @param[in]  numSamples  number of complex samples in each vector\r\n   */\r\n  void arm_cmplx_conj_q15(\r\n  q15_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t numSamples);\r\n\r\n\r\n  /**\r\n   * @brief  Floating-point complex magnitude squared\r\n   * @param[in]  pSrc        points to the complex input vector\r\n   * @param[out] pDst        points to the real output vector\r\n   * @param[in]  numSamples  number of complex samples in the input vector\r\n   */\r\n  void arm_cmplx_mag_squared_f32(\r\n  float32_t * pSrc,\r\n  float32_t * pDst,\r\n  uint32_t numSamples);\r\n\r\n\r\n  /**\r\n   * @brief  Q31 complex magnitude squared\r\n   * @param[in]  pSrc        points to the complex input vector\r\n   * @param[out] pDst        points to the real output vector\r\n   * @param[in]  numSamples  number of complex samples in the input vector\r\n   */\r\n  void arm_cmplx_mag_squared_q31(\r\n  q31_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t numSamples);\r\n\r\n\r\n  /**\r\n   * @brief  Q15 complex magnitude squared\r\n   * @param[in]  pSrc        points to the complex input vector\r\n   * @param[out] pDst        points to the real output vector\r\n   * @param[in]  numSamples  number of complex samples in the input vector\r\n   */\r\n  void arm_cmplx_mag_squared_q15(\r\n  q15_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t numSamples);\r\n\r\n\r\n /**\r\n   * @ingroup groupController\r\n   */\r\n\r\n  /**\r\n   * @defgroup PID PID Motor Control\r\n   *\r\n   * A Proportional Integral Derivative (PID) controller is a generic feedback control\r\n   * loop mechanism widely used in industrial control systems.\r\n   * A PID controller is the most commonly used type of feedback controller.\r\n   *\r\n   * This set of functions implements (PID) controllers\r\n   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample\r\n   * of data and each call to the function returns a single processed value.\r\n   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>\r\n   * is the input sample value. The functions return the output value.\r\n   *\r\n   * \\par Algorithm:\r\n   * <pre>\r\n   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]\r\n   *    A0 = Kp + Ki + Kd\r\n   *    A1 = (-Kp ) - (2 * Kd )\r\n   *    A2 = Kd  </pre>\r\n   *\r\n   * \\par\r\n   * where \\c Kp is proportional constant, \\c Ki is Integral constant and \\c Kd is Derivative constant\r\n   *\r\n   * \\par\r\n   * \\image html PID.gif \"Proportional Integral Derivative Controller\"\r\n   *\r\n   * \\par\r\n   * The PID controller calculates an \"error\" value as the difference between\r\n   * the measured output and the reference input.\r\n   * The controller attempts to minimize the error by adjusting the process control inputs.\r\n   * The proportional value determines the reaction to the current error,\r\n   * the integral value determines the reaction based on the sum of recent errors,\r\n   * and the derivative value determines the reaction based on the rate at which the error has been changing.\r\n   *\r\n   * \\par Instance Structure\r\n   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.\r\n   * A separate instance structure must be defined for each PID Controller.\r\n   * There are separate instance structure declarations for each of the 3 supported data types.\r\n   *\r\n   * \\par Reset Functions\r\n   * There is also an associated reset function for each data type which clears the state array.\r\n   *\r\n   * \\par Initialization Functions\r\n   * There is also an associated initialization function for each data type.\r\n   * The initialization function performs the following operations:\r\n   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.\r\n   * - Zeros out the values in the state buffer.\r\n   *\r\n   * \\par\r\n   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.\r\n   *\r\n   * \\par Fixed-Point Behavior\r\n   * Care must be taken when using the fixed-point versions of the PID Controller functions.\r\n   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.\r\n   * Refer to the function specific documentation below for usage guidelines.\r\n   */\r\n\r\n  /**\r\n   * @addtogroup PID\r\n   * @{\r\n   */\r\n\r\n  /**\r\n   * @brief  Process function for the floating-point PID Control.\r\n   * @param[in,out] S   is an instance of the floating-point PID Control structure\r\n   * @param[in]     in  input sample to process\r\n   * @return out processed output sample.\r\n   */\r\n  static __INLINE float32_t arm_pid_f32(\r\n  arm_pid_instance_f32 * S,\r\n  float32_t in)\r\n  {\r\n    float32_t out;\r\n\r\n    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */\r\n    out = (S->A0 * in) +\r\n      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);\r\n\r\n    /* Update state */\r\n    S->state[1] = S->state[0];\r\n    S->state[0] = in;\r\n    S->state[2] = out;\r\n\r\n    /* return to application */\r\n    return (out);\r\n\r\n  }\r\n\r\n  /**\r\n   * @brief  Process function for the Q31 PID Control.\r\n   * @param[in,out] S  points to an instance of the Q31 PID Control structure\r\n   * @param[in]     in  input sample to process\r\n   * @return out processed output sample.\r\n   *\r\n   * <b>Scaling and Overflow Behavior:</b>\r\n   * \\par\r\n   * The function is implemented using an internal 64-bit accumulator.\r\n   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.\r\n   * Thus, if the accumulator result overflows it wraps around rather than clip.\r\n   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.\r\n   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.\r\n   */\r\n  static __INLINE q31_t arm_pid_q31(\r\n  arm_pid_instance_q31 * S,\r\n  q31_t in)\r\n  {\r\n    q63_t acc;\r\n    q31_t out;\r\n\r\n    /* acc = A0 * x[n]  */\r\n    acc = (q63_t) S->A0 * in;\r\n\r\n    /* acc += A1 * x[n-1] */\r\n    acc += (q63_t) S->A1 * S->state[0];\r\n\r\n    /* acc += A2 * x[n-2]  */\r\n    acc += (q63_t) S->A2 * S->state[1];\r\n\r\n    /* convert output to 1.31 format to add y[n-1] */\r\n    out = (q31_t) (acc >> 31u);\r\n\r\n    /* out += y[n-1] */\r\n    out += S->state[2];\r\n\r\n    /* Update state */\r\n    S->state[1] = S->state[0];\r\n    S->state[0] = in;\r\n    S->state[2] = out;\r\n\r\n    /* return to application */\r\n    return (out);\r\n  }\r\n\r\n\r\n  /**\r\n   * @brief  Process function for the Q15 PID Control.\r\n   * @param[in,out] S   points to an instance of the Q15 PID Control structure\r\n   * @param[in]     in  input sample to process\r\n   * @return out processed output sample.\r\n   *\r\n   * <b>Scaling and Overflow Behavior:</b>\r\n   * \\par\r\n   * The function is implemented using a 64-bit internal accumulator.\r\n   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.\r\n   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.\r\n   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.\r\n   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.\r\n   * Lastly, the accumulator is saturated to yield a result in 1.15 format.\r\n   */\r\n  static __INLINE q15_t arm_pid_q15(\r\n  arm_pid_instance_q15 * S,\r\n  q15_t in)\r\n  {\r\n    q63_t acc;\r\n    q15_t out;\r\n\r\n#ifndef ARM_MATH_CM0_FAMILY\r\n    __SIMD32_TYPE *vstate;\r\n\r\n    /* Implementation of PID controller */\r\n\r\n    /* acc = A0 * x[n]  */\r\n    acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);\r\n\r\n    /* acc += A1 * x[n-1] + A2 * x[n-2]  */\r\n    vstate = __SIMD32_CONST(S->state);\r\n    acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);\r\n#else\r\n    /* acc = A0 * x[n]  */\r\n    acc = ((q31_t) S->A0) * in;\r\n\r\n    /* acc += A1 * x[n-1] + A2 * x[n-2]  */\r\n    acc += (q31_t) S->A1 * S->state[0];\r\n    acc += (q31_t) S->A2 * S->state[1];\r\n#endif\r\n\r\n    /* acc += y[n-1] */\r\n    acc += (q31_t) S->state[2] << 15;\r\n\r\n    /* saturate the output */\r\n    out = (q15_t) (__SSAT((acc >> 15), 16));\r\n\r\n    /* Update state */\r\n    S->state[1] = S->state[0];\r\n    S->state[0] = in;\r\n    S->state[2] = out;\r\n\r\n    /* return to application */\r\n    return (out);\r\n  }\r\n\r\n  /**\r\n   * @} end of PID group\r\n   */\r\n\r\n\r\n  /**\r\n   * @brief Floating-point matrix inverse.\r\n   * @param[in]  src   points to the instance of the input floating-point matrix structure.\r\n   * @param[out] dst   points to the instance of the output floating-point matrix structure.\r\n   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.\r\n   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.\r\n   */\r\n  arm_status arm_mat_inverse_f32(\r\n  const arm_matrix_instance_f32 * src,\r\n  arm_matrix_instance_f32 * dst);\r\n\r\n\r\n  /**\r\n   * @brief Floating-point matrix inverse.\r\n   * @param[in]  src   points to the instance of the input floating-point matrix structure.\r\n   * @param[out] dst   points to the instance of the output floating-point matrix structure.\r\n   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.\r\n   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.\r\n   */\r\n  arm_status arm_mat_inverse_f64(\r\n  const arm_matrix_instance_f64 * src,\r\n  arm_matrix_instance_f64 * dst);\r\n\r\n\r\n\r\n  /**\r\n   * @ingroup groupController\r\n   */\r\n\r\n  /**\r\n   * @defgroup clarke Vector Clarke Transform\r\n   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.\r\n   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents\r\n   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.\r\n   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below\r\n   * \\image html clarke.gif Stator current space vector and its components in (a,b).\r\n   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>\r\n   * can be calculated using only <code>Ia</code> and <code>Ib</code>.\r\n   *\r\n   * The function operates on a single sample of data and each call to the function returns the processed output.\r\n   * The library provides separate functions for Q31 and floating-point data types.\r\n   * \\par Algorithm\r\n   * \\image html clarkeFormula.gif\r\n   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and\r\n   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.\r\n   * \\par Fixed-Point Behavior\r\n   * Care must be taken when using the Q31 version of the Clarke transform.\r\n   * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r\n   * Refer to the function specific documentation below for usage guidelines.\r\n   */\r\n\r\n  /**\r\n   * @addtogroup clarke\r\n   * @{\r\n   */\r\n\r\n  /**\r\n   *\r\n   * @brief  Floating-point Clarke transform\r\n   * @param[in]  Ia       input three-phase coordinate <code>a</code>\r\n   * @param[in]  Ib       input three-phase coordinate <code>b</code>\r\n   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha\r\n   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta\r\n   */\r\n  static __INLINE void arm_clarke_f32(\r\n  float32_t Ia,\r\n  float32_t Ib,\r\n  float32_t * pIalpha,\r\n  float32_t * pIbeta)\r\n  {\r\n    /* Calculate pIalpha using the equation, pIalpha = Ia */\r\n    *pIalpha = Ia;\r\n\r\n    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */\r\n    *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);\r\n  }\r\n\r\n\r\n  /**\r\n   * @brief  Clarke transform for Q31 version\r\n   * @param[in]  Ia       input three-phase coordinate <code>a</code>\r\n   * @param[in]  Ib       input three-phase coordinate <code>b</code>\r\n   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha\r\n   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta\r\n   *\r\n   * <b>Scaling and Overflow Behavior:</b>\r\n   * \\par\r\n   * The function is implemented using an internal 32-bit accumulator.\r\n   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r\n   * There is saturation on the addition, hence there is no risk of overflow.\r\n   */\r\n  static __INLINE void arm_clarke_q31(\r\n  q31_t Ia,\r\n  q31_t Ib,\r\n  q31_t * pIalpha,\r\n  q31_t * pIbeta)\r\n  {\r\n    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */\r\n\r\n    /* Calculating pIalpha from Ia by equation pIalpha = Ia */\r\n    *pIalpha = Ia;\r\n\r\n    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */\r\n    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);\r\n\r\n    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */\r\n    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);\r\n\r\n    /* pIbeta is calculated by adding the intermediate products */\r\n    *pIbeta = __QADD(product1, product2);\r\n  }\r\n\r\n  /**\r\n   * @} end of clarke group\r\n   */\r\n\r\n  /**\r\n   * @brief  Converts the elements of the Q7 vector to Q31 vector.\r\n   * @param[in]  pSrc       input pointer\r\n   * @param[out] pDst       output pointer\r\n   * @param[in]  blockSize  number of samples to process\r\n   */\r\n  void arm_q7_to_q31(\r\n  q7_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n\r\n  /**\r\n   * @ingroup groupController\r\n   */\r\n\r\n  /**\r\n   * @defgroup inv_clarke Vector Inverse Clarke Transform\r\n   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.\r\n   *\r\n   * The function operates on a single sample of data and each call to the function returns the processed output.\r\n   * The library provides separate functions for Q31 and floating-point data types.\r\n   * \\par Algorithm\r\n   * \\image html clarkeInvFormula.gif\r\n   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and\r\n   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.\r\n   * \\par Fixed-Point Behavior\r\n   * Care must be taken when using the Q31 version of the Clarke transform.\r\n   * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r\n   * Refer to the function specific documentation below for usage guidelines.\r\n   */\r\n\r\n  /**\r\n   * @addtogroup inv_clarke\r\n   * @{\r\n   */\r\n\r\n   /**\r\n   * @brief  Floating-point Inverse Clarke transform\r\n   * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha\r\n   * @param[in]  Ibeta   input two-phase orthogonal vector axis beta\r\n   * @param[out] pIa     points to output three-phase coordinate <code>a</code>\r\n   * @param[out] pIb     points to output three-phase coordinate <code>b</code>\r\n   */\r\n  static __INLINE void arm_inv_clarke_f32(\r\n  float32_t Ialpha,\r\n  float32_t Ibeta,\r\n  float32_t * pIa,\r\n  float32_t * pIb)\r\n  {\r\n    /* Calculating pIa from Ialpha by equation pIa = Ialpha */\r\n    *pIa = Ialpha;\r\n\r\n    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */\r\n    *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;\r\n  }\r\n\r\n\r\n  /**\r\n   * @brief  Inverse Clarke transform for Q31 version\r\n   * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha\r\n   * @param[in]  Ibeta   input two-phase orthogonal vector axis beta\r\n   * @param[out] pIa     points to output three-phase coordinate <code>a</code>\r\n   * @param[out] pIb     points to output three-phase coordinate <code>b</code>\r\n   *\r\n   * <b>Scaling and Overflow Behavior:</b>\r\n   * \\par\r\n   * The function is implemented using an internal 32-bit accumulator.\r\n   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r\n   * There is saturation on the subtraction, hence there is no risk of overflow.\r\n   */\r\n  static __INLINE void arm_inv_clarke_q31(\r\n  q31_t Ialpha,\r\n  q31_t Ibeta,\r\n  q31_t * pIa,\r\n  q31_t * pIb)\r\n  {\r\n    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */\r\n\r\n    /* Calculating pIa from Ialpha by equation pIa = Ialpha */\r\n    *pIa = Ialpha;\r\n\r\n    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */\r\n    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);\r\n\r\n    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */\r\n    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);\r\n\r\n    /* pIb is calculated by subtracting the products */\r\n    *pIb = __QSUB(product2, product1);\r\n  }\r\n\r\n  /**\r\n   * @} end of inv_clarke group\r\n   */\r\n\r\n  /**\r\n   * @brief  Converts the elements of the Q7 vector to Q15 vector.\r\n   * @param[in]  pSrc       input pointer\r\n   * @param[out] pDst       output pointer\r\n   * @param[in]  blockSize  number of samples to process\r\n   */\r\n  void arm_q7_to_q15(\r\n  q7_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n\r\n  /**\r\n   * @ingroup groupController\r\n   */\r\n\r\n  /**\r\n   * @defgroup park Vector Park Transform\r\n   *\r\n   * Forward Park transform converts the input two-coordinate vector to flux and torque components.\r\n   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents\r\n   * from the stationary to the moving reference frame and control the spatial relationship between\r\n   * the stator vector current and rotor flux vector.\r\n   * If we consider the d axis aligned with the rotor flux, the diagram below shows the\r\n   * current vector and the relationship from the two reference frames:\r\n   * \\image html park.gif \"Stator current space vector and its component in (a,b) and in the d,q rotating reference frame\"\r\n   *\r\n   * The function operates on a single sample of data and each call to the function returns the processed output.\r\n   * The library provides separate functions for Q31 and floating-point data types.\r\n   * \\par Algorithm\r\n   * \\image html parkFormula.gif\r\n   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,\r\n   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the\r\n   * cosine and sine values of theta (rotor flux position).\r\n   * \\par Fixed-Point Behavior\r\n   * Care must be taken when using the Q31 version of the Park transform.\r\n   * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r\n   * Refer to the function specific documentation below for usage guidelines.\r\n   */\r\n\r\n  /**\r\n   * @addtogroup park\r\n   * @{\r\n   */\r\n\r\n  /**\r\n   * @brief Floating-point Park transform\r\n   * @param[in]  Ialpha  input two-phase vector coordinate alpha\r\n   * @param[in]  Ibeta   input two-phase vector coordinate beta\r\n   * @param[out] pId     points to output   rotor reference frame d\r\n   * @param[out] pIq     points to output   rotor reference frame q\r\n   * @param[in]  sinVal  sine value of rotation angle theta\r\n   * @param[in]  cosVal  cosine value of rotation angle theta\r\n   *\r\n   * The function implements the forward Park transform.\r\n   *\r\n   */\r\n  static __INLINE void arm_park_f32(\r\n  float32_t Ialpha,\r\n  float32_t Ibeta,\r\n  float32_t * pId,\r\n  float32_t * pIq,\r\n  float32_t sinVal,\r\n  float32_t cosVal)\r\n  {\r\n    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */\r\n    *pId = Ialpha * cosVal + Ibeta * sinVal;\r\n\r\n    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */\r\n    *pIq = -Ialpha * sinVal + Ibeta * cosVal;\r\n  }\r\n\r\n\r\n  /**\r\n   * @brief  Park transform for Q31 version\r\n   * @param[in]  Ialpha  input two-phase vector coordinate alpha\r\n   * @param[in]  Ibeta   input two-phase vector coordinate beta\r\n   * @param[out] pId     points to output rotor reference frame d\r\n   * @param[out] pIq     points to output rotor reference frame q\r\n   * @param[in]  sinVal  sine value of rotation angle theta\r\n   * @param[in]  cosVal  cosine value of rotation angle theta\r\n   *\r\n   * <b>Scaling and Overflow Behavior:</b>\r\n   * \\par\r\n   * The function is implemented using an internal 32-bit accumulator.\r\n   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r\n   * There is saturation on the addition and subtraction, hence there is no risk of overflow.\r\n   */\r\n  static __INLINE void arm_park_q31(\r\n  q31_t Ialpha,\r\n  q31_t Ibeta,\r\n  q31_t * pId,\r\n  q31_t * pIq,\r\n  q31_t sinVal,\r\n  q31_t cosVal)\r\n  {\r\n    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */\r\n    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */\r\n\r\n    /* Intermediate product is calculated by (Ialpha * cosVal) */\r\n    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);\r\n\r\n    /* Intermediate product is calculated by (Ibeta * sinVal) */\r\n    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);\r\n\r\n\r\n    /* Intermediate product is calculated by (Ialpha * sinVal) */\r\n    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);\r\n\r\n    /* Intermediate product is calculated by (Ibeta * cosVal) */\r\n    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);\r\n\r\n    /* Calculate pId by adding the two intermediate products 1 and 2 */\r\n    *pId = __QADD(product1, product2);\r\n\r\n    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */\r\n    *pIq = __QSUB(product4, product3);\r\n  }\r\n\r\n  /**\r\n   * @} end of park group\r\n   */\r\n\r\n  /**\r\n   * @brief  Converts the elements of the Q7 vector to floating-point vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[out] pDst       is output pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   */\r\n  void arm_q7_to_float(\r\n  q7_t * pSrc,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @ingroup groupController\r\n   */\r\n\r\n  /**\r\n   * @defgroup inv_park Vector Inverse Park transform\r\n   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.\r\n   *\r\n   * The function operates on a single sample of data and each call to the function returns the processed output.\r\n   * The library provides separate functions for Q31 and floating-point data types.\r\n   * \\par Algorithm\r\n   * \\image html parkInvFormula.gif\r\n   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,\r\n   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the\r\n   * cosine and sine values of theta (rotor flux position).\r\n   * \\par Fixed-Point Behavior\r\n   * Care must be taken when using the Q31 version of the Park transform.\r\n   * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r\n   * Refer to the function specific documentation below for usage guidelines.\r\n   */\r\n\r\n  /**\r\n   * @addtogroup inv_park\r\n   * @{\r\n   */\r\n\r\n   /**\r\n   * @brief  Floating-point Inverse Park transform\r\n   * @param[in]  Id       input coordinate of rotor reference frame d\r\n   * @param[in]  Iq       input coordinate of rotor reference frame q\r\n   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha\r\n   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta\r\n   * @param[in]  sinVal   sine value of rotation angle theta\r\n   * @param[in]  cosVal   cosine value of rotation angle theta\r\n   */\r\n  static __INLINE void arm_inv_park_f32(\r\n  float32_t Id,\r\n  float32_t Iq,\r\n  float32_t * pIalpha,\r\n  float32_t * pIbeta,\r\n  float32_t sinVal,\r\n  float32_t cosVal)\r\n  {\r\n    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */\r\n    *pIalpha = Id * cosVal - Iq * sinVal;\r\n\r\n    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */\r\n    *pIbeta = Id * sinVal + Iq * cosVal;\r\n  }\r\n\r\n\r\n  /**\r\n   * @brief  Inverse Park transform for   Q31 version\r\n   * @param[in]  Id       input coordinate of rotor reference frame d\r\n   * @param[in]  Iq       input coordinate of rotor reference frame q\r\n   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha\r\n   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta\r\n   * @param[in]  sinVal   sine value of rotation angle theta\r\n   * @param[in]  cosVal   cosine value of rotation angle theta\r\n   *\r\n   * <b>Scaling and Overflow Behavior:</b>\r\n   * \\par\r\n   * The function is implemented using an internal 32-bit accumulator.\r\n   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r\n   * There is saturation on the addition, hence there is no risk of overflow.\r\n   */\r\n  static __INLINE void arm_inv_park_q31(\r\n  q31_t Id,\r\n  q31_t Iq,\r\n  q31_t * pIalpha,\r\n  q31_t * pIbeta,\r\n  q31_t sinVal,\r\n  q31_t cosVal)\r\n  {\r\n    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */\r\n    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */\r\n\r\n    /* Intermediate product is calculated by (Id * cosVal) */\r\n    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);\r\n\r\n    /* Intermediate product is calculated by (Iq * sinVal) */\r\n    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);\r\n\r\n\r\n    /* Intermediate product is calculated by (Id * sinVal) */\r\n    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);\r\n\r\n    /* Intermediate product is calculated by (Iq * cosVal) */\r\n    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);\r\n\r\n    /* Calculate pIalpha by using the two intermediate products 1 and 2 */\r\n    *pIalpha = __QSUB(product1, product2);\r\n\r\n    /* Calculate pIbeta by using the two intermediate products 3 and 4 */\r\n    *pIbeta = __QADD(product4, product3);\r\n  }\r\n\r\n  /**\r\n   * @} end of Inverse park group\r\n   */\r\n\r\n\r\n  /**\r\n   * @brief  Converts the elements of the Q31 vector to floating-point vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[out] pDst       is output pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   */\r\n  void arm_q31_to_float(\r\n  q31_t * pSrc,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n  /**\r\n   * @ingroup groupInterpolation\r\n   */\r\n\r\n  /**\r\n   * @defgroup LinearInterpolate Linear Interpolation\r\n   *\r\n   * Linear interpolation is a method of curve fitting using linear polynomials.\r\n   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line\r\n   *\r\n   * \\par\r\n   * \\image html LinearInterp.gif \"Linear interpolation\"\r\n   *\r\n   * \\par\r\n   * A  Linear Interpolate function calculates an output value(y), for the input(x)\r\n   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)\r\n   *\r\n   * \\par Algorithm:\r\n   * <pre>\r\n   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))\r\n   *       where x0, x1 are nearest values of input x\r\n   *             y0, y1 are nearest values to output y\r\n   * </pre>\r\n   *\r\n   * \\par\r\n   * This set of functions implements Linear interpolation process\r\n   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single\r\n   * sample of data and each call to the function returns a single processed value.\r\n   * <code>S</code> points to an instance of the Linear Interpolate function data structure.\r\n   * <code>x</code> is the input sample value. The functions returns the output value.\r\n   *\r\n   * \\par\r\n   * if x is outside of the table boundary, Linear interpolation returns first value of the table\r\n   * if x is below input range and returns last value of table if x is above range.\r\n   */\r\n\r\n  /**\r\n   * @addtogroup LinearInterpolate\r\n   * @{\r\n   */\r\n\r\n  /**\r\n   * @brief  Process function for the floating-point Linear Interpolation Function.\r\n   * @param[in,out] S  is an instance of the floating-point Linear Interpolation structure\r\n   * @param[in]     x  input sample to process\r\n   * @return y processed output sample.\r\n   *\r\n   */\r\n  static __INLINE float32_t arm_linear_interp_f32(\r\n  arm_linear_interp_instance_f32 * S,\r\n  float32_t x)\r\n  {\r\n    float32_t y;\r\n    float32_t x0, x1;                            /* Nearest input values */\r\n    float32_t y0, y1;                            /* Nearest output values */\r\n    float32_t xSpacing = S->xSpacing;            /* spacing between input values */\r\n    int32_t i;                                   /* Index variable */\r\n    float32_t *pYData = S->pYData;               /* pointer to output table */\r\n\r\n    /* Calculation of index */\r\n    i = (int32_t) ((x - S->x1) / xSpacing);\r\n\r\n    if(i < 0)\r\n    {\r\n      /* Iniatilize output for below specified range as least output value of table */\r\n      y = pYData[0];\r\n    }\r\n    else if((uint32_t)i >= S->nValues)\r\n    {\r\n      /* Iniatilize output for above specified range as last output value of table */\r\n      y = pYData[S->nValues - 1];\r\n    }\r\n    else\r\n    {\r\n      /* Calculation of nearest input values */\r\n      x0 = S->x1 +  i      * xSpacing;\r\n      x1 = S->x1 + (i + 1) * xSpacing;\r\n\r\n      /* Read of nearest output values */\r\n      y0 = pYData[i];\r\n      y1 = pYData[i + 1];\r\n\r\n      /* Calculation of output */\r\n      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));\r\n\r\n    }\r\n\r\n    /* returns output value */\r\n    return (y);\r\n  }\r\n\r\n\r\n   /**\r\n   *\r\n   * @brief  Process function for the Q31 Linear Interpolation Function.\r\n   * @param[in] pYData   pointer to Q31 Linear Interpolation table\r\n   * @param[in] x        input sample to process\r\n   * @param[in] nValues  number of table values\r\n   * @return y processed output sample.\r\n   *\r\n   * \\par\r\n   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r\n   * This function can support maximum of table size 2^12.\r\n   *\r\n   */\r\n  static __INLINE q31_t arm_linear_interp_q31(\r\n  q31_t * pYData,\r\n  q31_t x,\r\n  uint32_t nValues)\r\n  {\r\n    q31_t y;                                     /* output */\r\n    q31_t y0, y1;                                /* Nearest output values */\r\n    q31_t fract;                                 /* fractional part */\r\n    int32_t index;                               /* Index to read nearest output values */\r\n\r\n    /* Input is in 12.20 format */\r\n    /* 12 bits for the table index */\r\n    /* Index value calculation */\r\n    index = ((x & (q31_t)0xFFF00000) >> 20);\r\n\r\n    if(index >= (int32_t)(nValues - 1))\r\n    {\r\n      return (pYData[nValues - 1]);\r\n    }\r\n    else if(index < 0)\r\n    {\r\n      return (pYData[0]);\r\n    }\r\n    else\r\n    {\r\n      /* 20 bits for the fractional part */\r\n      /* shift left by 11 to keep fract in 1.31 format */\r\n      fract = (x & 0x000FFFFF) << 11;\r\n\r\n      /* Read two nearest output values from the index in 1.31(q31) format */\r\n      y0 = pYData[index];\r\n      y1 = pYData[index + 1];\r\n\r\n      /* Calculation of y0 * (1-fract) and y is in 2.30 format */\r\n      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));\r\n\r\n      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */\r\n      y += ((q31_t) (((q63_t) y1 * fract) >> 32));\r\n\r\n      /* Convert y to 1.31 format */\r\n      return (y << 1u);\r\n    }\r\n  }\r\n\r\n\r\n  /**\r\n   *\r\n   * @brief  Process function for the Q15 Linear Interpolation Function.\r\n   * @param[in] pYData   pointer to Q15 Linear Interpolation table\r\n   * @param[in] x        input sample to process\r\n   * @param[in] nValues  number of table values\r\n   * @return y processed output sample.\r\n   *\r\n   * \\par\r\n   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r\n   * This function can support maximum of table size 2^12.\r\n   *\r\n   */\r\n  static __INLINE q15_t arm_linear_interp_q15(\r\n  q15_t * pYData,\r\n  q31_t x,\r\n  uint32_t nValues)\r\n  {\r\n    q63_t y;                                     /* output */\r\n    q15_t y0, y1;                                /* Nearest output values */\r\n    q31_t fract;                                 /* fractional part */\r\n    int32_t index;                               /* Index to read nearest output values */\r\n\r\n    /* Input is in 12.20 format */\r\n    /* 12 bits for the table index */\r\n    /* Index value calculation */\r\n    index = ((x & (int32_t)0xFFF00000) >> 20);\r\n\r\n    if(index >= (int32_t)(nValues - 1))\r\n    {\r\n      return (pYData[nValues - 1]);\r\n    }\r\n    else if(index < 0)\r\n    {\r\n      return (pYData[0]);\r\n    }\r\n    else\r\n    {\r\n      /* 20 bits for the fractional part */\r\n      /* fract is in 12.20 format */\r\n      fract = (x & 0x000FFFFF);\r\n\r\n      /* Read two nearest output values from the index */\r\n      y0 = pYData[index];\r\n      y1 = pYData[index + 1];\r\n\r\n      /* Calculation of y0 * (1-fract) and y is in 13.35 format */\r\n      y = ((q63_t) y0 * (0xFFFFF - fract));\r\n\r\n      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */\r\n      y += ((q63_t) y1 * (fract));\r\n\r\n      /* convert y to 1.15 format */\r\n      return (q15_t) (y >> 20);\r\n    }\r\n  }\r\n\r\n\r\n  /**\r\n   *\r\n   * @brief  Process function for the Q7 Linear Interpolation Function.\r\n   * @param[in] pYData   pointer to Q7 Linear Interpolation table\r\n   * @param[in] x        input sample to process\r\n   * @param[in] nValues  number of table values\r\n   * @return y processed output sample.\r\n   *\r\n   * \\par\r\n   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r\n   * This function can support maximum of table size 2^12.\r\n   */\r\n  static __INLINE q7_t arm_linear_interp_q7(\r\n  q7_t * pYData,\r\n  q31_t x,\r\n  uint32_t nValues)\r\n  {\r\n    q31_t y;                                     /* output */\r\n    q7_t y0, y1;                                 /* Nearest output values */\r\n    q31_t fract;                                 /* fractional part */\r\n    uint32_t index;                              /* Index to read nearest output values */\r\n\r\n    /* Input is in 12.20 format */\r\n    /* 12 bits for the table index */\r\n    /* Index value calculation */\r\n    if (x < 0)\r\n    {\r\n      return (pYData[0]);\r\n    }\r\n    index = (x >> 20) & 0xfff;\r\n\r\n    if(index >= (nValues - 1))\r\n    {\r\n      return (pYData[nValues - 1]);\r\n    }\r\n    else\r\n    {\r\n      /* 20 bits for the fractional part */\r\n      /* fract is in 12.20 format */\r\n      fract = (x & 0x000FFFFF);\r\n\r\n      /* Read two nearest output values from the index and are in 1.7(q7) format */\r\n      y0 = pYData[index];\r\n      y1 = pYData[index + 1];\r\n\r\n      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */\r\n      y = ((y0 * (0xFFFFF - fract)));\r\n\r\n      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */\r\n      y += (y1 * fract);\r\n\r\n      /* convert y to 1.7(q7) format */\r\n      return (q7_t) (y >> 20);\r\n     }\r\n  }\r\n\r\n  /**\r\n   * @} end of LinearInterpolate group\r\n   */\r\n\r\n  /**\r\n   * @brief  Fast approximation to the trigonometric sine function for floating-point data.\r\n   * @param[in] x  input value in radians.\r\n   * @return  sin(x).\r\n   */\r\n  float32_t arm_sin_f32(\r\n  float32_t x);\r\n\r\n\r\n  /**\r\n   * @brief  Fast approximation to the trigonometric sine function for Q31 data.\r\n   * @param[in] x  Scaled input value in radians.\r\n   * @return  sin(x).\r\n   */\r\n  q31_t arm_sin_q31(\r\n  q31_t x);\r\n\r\n\r\n  /**\r\n   * @brief  Fast approximation to the trigonometric sine function for Q15 data.\r\n   * @param[in] x  Scaled input value in radians.\r\n   * @return  sin(x).\r\n   */\r\n  q15_t arm_sin_q15(\r\n  q15_t x);\r\n\r\n\r\n  /**\r\n   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.\r\n   * @param[in] x  input value in radians.\r\n   * @return  cos(x).\r\n   */\r\n  float32_t arm_cos_f32(\r\n  float32_t x);\r\n\r\n\r\n  /**\r\n   * @brief Fast approximation to the trigonometric cosine function for Q31 data.\r\n   * @param[in] x  Scaled input value in radians.\r\n   * @return  cos(x).\r\n   */\r\n  q31_t arm_cos_q31(\r\n  q31_t x);\r\n\r\n\r\n  /**\r\n   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.\r\n   * @param[in] x  Scaled input value in radians.\r\n   * @return  cos(x).\r\n   */\r\n  q15_t arm_cos_q15(\r\n  q15_t x);\r\n\r\n\r\n  /**\r\n   * @ingroup groupFastMath\r\n   */\r\n\r\n\r\n  /**\r\n   * @defgroup SQRT Square Root\r\n   *\r\n   * Computes the square root of a number.\r\n   * There are separate functions for Q15, Q31, and floating-point data types.\r\n   * The square root function is computed using the Newton-Raphson algorithm.\r\n   * This is an iterative algorithm of the form:\r\n   * <pre>\r\n   *      x1 = x0 - f(x0)/f'(x0)\r\n   * </pre>\r\n   * where <code>x1</code> is the current estimate,\r\n   * <code>x0</code> is the previous estimate, and\r\n   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.\r\n   * For the square root function, the algorithm reduces to:\r\n   * <pre>\r\n   *     x0 = in/2                         [initial guess]\r\n   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]\r\n   * </pre>\r\n   */\r\n\r\n\r\n  /**\r\n   * @addtogroup SQRT\r\n   * @{\r\n   */\r\n\r\n  /**\r\n   * @brief  Floating-point square root function.\r\n   * @param[in]  in    input value.\r\n   * @param[out] pOut  square root of input value.\r\n   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r\n   * <code>in</code> is negative value and returns zero output for negative values.\r\n   */\r\n  static __INLINE arm_status arm_sqrt_f32(\r\n  float32_t in,\r\n  float32_t * pOut)\r\n  {\r\n    if(in >= 0.0f)\r\n    {\r\n\r\n#if   (__FPU_USED == 1) && defined ( __CC_ARM   )\r\n      *pOut = __sqrtf(in);\r\n#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\r\n      *pOut = __builtin_sqrtf(in);\r\n#elif (__FPU_USED == 1) && defined(__GNUC__)\r\n      *pOut = __builtin_sqrtf(in);\r\n#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)\r\n      __ASM(\"VSQRT.F32 %0,%1\" : \"=t\"(*pOut) : \"t\"(in));\r\n#else\r\n      *pOut = sqrtf(in);\r\n#endif\r\n\r\n      return (ARM_MATH_SUCCESS);\r\n    }\r\n    else\r\n    {\r\n      *pOut = 0.0f;\r\n      return (ARM_MATH_ARGUMENT_ERROR);\r\n    }\r\n  }\r\n\r\n\r\n  /**\r\n   * @brief Q31 square root function.\r\n   * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.\r\n   * @param[out] pOut  square root of input value.\r\n   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r\n   * <code>in</code> is negative value and returns zero output for negative values.\r\n   */\r\n  arm_status arm_sqrt_q31(\r\n  q31_t in,\r\n  q31_t * pOut);\r\n\r\n\r\n  /**\r\n   * @brief  Q15 square root function.\r\n   * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.\r\n   * @param[out] pOut  square root of input value.\r\n   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r\n   * <code>in</code> is negative value and returns zero output for negative values.\r\n   */\r\n  arm_status arm_sqrt_q15(\r\n  q15_t in,\r\n  q15_t * pOut);\r\n\r\n  /**\r\n   * @} end of SQRT group\r\n   */\r\n\r\n\r\n  /**\r\n   * @brief floating-point Circular write function.\r\n   */\r\n  static __INLINE void arm_circularWrite_f32(\r\n  int32_t * circBuffer,\r\n  int32_t L,\r\n  uint16_t * writeOffset,\r\n  int32_t bufferInc,\r\n  const int32_t * src,\r\n  int32_t srcInc,\r\n  uint32_t blockSize)\r\n  {\r\n    uint32_t i = 0u;\r\n    int32_t wOffset;\r\n\r\n    /* Copy the value of Index pointer that points\r\n     * to the current location where the input samples to be copied */\r\n    wOffset = *writeOffset;\r\n\r\n    /* Loop over the blockSize */\r\n    i = blockSize;\r\n\r\n    while(i > 0u)\r\n    {\r\n      /* copy the input sample to the circular buffer */\r\n      circBuffer[wOffset] = *src;\r\n\r\n      /* Update the input pointer */\r\n      src += srcInc;\r\n\r\n      /* Circularly update wOffset.  Watch out for positive and negative value */\r\n      wOffset += bufferInc;\r\n      if(wOffset >= L)\r\n        wOffset -= L;\r\n\r\n      /* Decrement the loop counter */\r\n      i--;\r\n    }\r\n\r\n    /* Update the index pointer */\r\n    *writeOffset = (uint16_t)wOffset;\r\n  }\r\n\r\n\r\n\r\n  /**\r\n   * @brief floating-point Circular Read function.\r\n   */\r\n  static __INLINE void arm_circularRead_f32(\r\n  int32_t * circBuffer,\r\n  int32_t L,\r\n  int32_t * readOffset,\r\n  int32_t bufferInc,\r\n  int32_t * dst,\r\n  int32_t * dst_base,\r\n  int32_t dst_length,\r\n  int32_t dstInc,\r\n  uint32_t blockSize)\r\n  {\r\n    uint32_t i = 0u;\r\n    int32_t rOffset, dst_end;\r\n\r\n    /* Copy the value of Index pointer that points\r\n     * to the current location from where the input samples to be read */\r\n    rOffset = *readOffset;\r\n    dst_end = (int32_t) (dst_base + dst_length);\r\n\r\n    /* Loop over the blockSize */\r\n    i = blockSize;\r\n\r\n    while(i > 0u)\r\n    {\r\n      /* copy the sample from the circular buffer to the destination buffer */\r\n      *dst = circBuffer[rOffset];\r\n\r\n      /* Update the input pointer */\r\n      dst += dstInc;\r\n\r\n      if(dst == (int32_t *) dst_end)\r\n      {\r\n        dst = dst_base;\r\n      }\r\n\r\n      /* Circularly update rOffset.  Watch out for positive and negative value  */\r\n      rOffset += bufferInc;\r\n\r\n      if(rOffset >= L)\r\n      {\r\n        rOffset -= L;\r\n      }\r\n\r\n      /* Decrement the loop counter */\r\n      i--;\r\n    }\r\n\r\n    /* Update the index pointer */\r\n    *readOffset = rOffset;\r\n  }\r\n\r\n\r\n  /**\r\n   * @brief Q15 Circular write function.\r\n   */\r\n  static __INLINE void arm_circularWrite_q15(\r\n  q15_t * circBuffer,\r\n  int32_t L,\r\n  uint16_t * writeOffset,\r\n  int32_t bufferInc,\r\n  const q15_t * src,\r\n  int32_t srcInc,\r\n  uint32_t blockSize)\r\n  {\r\n    uint32_t i = 0u;\r\n    int32_t wOffset;\r\n\r\n    /* Copy the value of Index pointer that points\r\n     * to the current location where the input samples to be copied */\r\n    wOffset = *writeOffset;\r\n\r\n    /* Loop over the blockSize */\r\n    i = blockSize;\r\n\r\n    while(i > 0u)\r\n    {\r\n      /* copy the input sample to the circular buffer */\r\n      circBuffer[wOffset] = *src;\r\n\r\n      /* Update the input pointer */\r\n      src += srcInc;\r\n\r\n      /* Circularly update wOffset.  Watch out for positive and negative value */\r\n      wOffset += bufferInc;\r\n      if(wOffset >= L)\r\n        wOffset -= L;\r\n\r\n      /* Decrement the loop counter */\r\n      i--;\r\n    }\r\n\r\n    /* Update the index pointer */\r\n    *writeOffset = (uint16_t)wOffset;\r\n  }\r\n\r\n\r\n  /**\r\n   * @brief Q15 Circular Read function.\r\n   */\r\n  static __INLINE void arm_circularRead_q15(\r\n  q15_t * circBuffer,\r\n  int32_t L,\r\n  int32_t * readOffset,\r\n  int32_t bufferInc,\r\n  q15_t * dst,\r\n  q15_t * dst_base,\r\n  int32_t dst_length,\r\n  int32_t dstInc,\r\n  uint32_t blockSize)\r\n  {\r\n    uint32_t i = 0;\r\n    int32_t rOffset, dst_end;\r\n\r\n    /* Copy the value of Index pointer that points\r\n     * to the current location from where the input samples to be read */\r\n    rOffset = *readOffset;\r\n\r\n    dst_end = (int32_t) (dst_base + dst_length);\r\n\r\n    /* Loop over the blockSize */\r\n    i = blockSize;\r\n\r\n    while(i > 0u)\r\n    {\r\n      /* copy the sample from the circular buffer to the destination buffer */\r\n      *dst = circBuffer[rOffset];\r\n\r\n      /* Update the input pointer */\r\n      dst += dstInc;\r\n\r\n      if(dst == (q15_t *) dst_end)\r\n      {\r\n        dst = dst_base;\r\n      }\r\n\r\n      /* Circularly update wOffset.  Watch out for positive and negative value */\r\n      rOffset += bufferInc;\r\n\r\n      if(rOffset >= L)\r\n      {\r\n        rOffset -= L;\r\n      }\r\n\r\n      /* Decrement the loop counter */\r\n      i--;\r\n    }\r\n\r\n    /* Update the index pointer */\r\n    *readOffset = rOffset;\r\n  }\r\n\r\n\r\n  /**\r\n   * @brief Q7 Circular write function.\r\n   */\r\n  static __INLINE void arm_circularWrite_q7(\r\n  q7_t * circBuffer,\r\n  int32_t L,\r\n  uint16_t * writeOffset,\r\n  int32_t bufferInc,\r\n  const q7_t * src,\r\n  int32_t srcInc,\r\n  uint32_t blockSize)\r\n  {\r\n    uint32_t i = 0u;\r\n    int32_t wOffset;\r\n\r\n    /* Copy the value of Index pointer that points\r\n     * to the current location where the input samples to be copied */\r\n    wOffset = *writeOffset;\r\n\r\n    /* Loop over the blockSize */\r\n    i = blockSize;\r\n\r\n    while(i > 0u)\r\n    {\r\n      /* copy the input sample to the circular buffer */\r\n      circBuffer[wOffset] = *src;\r\n\r\n      /* Update the input pointer */\r\n      src += srcInc;\r\n\r\n      /* Circularly update wOffset.  Watch out for positive and negative value */\r\n      wOffset += bufferInc;\r\n      if(wOffset >= L)\r\n        wOffset -= L;\r\n\r\n      /* Decrement the loop counter */\r\n      i--;\r\n    }\r\n\r\n    /* Update the index pointer */\r\n    *writeOffset = (uint16_t)wOffset;\r\n  }\r\n\r\n\r\n  /**\r\n   * @brief Q7 Circular Read function.\r\n   */\r\n  static __INLINE void arm_circularRead_q7(\r\n  q7_t * circBuffer,\r\n  int32_t L,\r\n  int32_t * readOffset,\r\n  int32_t bufferInc,\r\n  q7_t * dst,\r\n  q7_t * dst_base,\r\n  int32_t dst_length,\r\n  int32_t dstInc,\r\n  uint32_t blockSize)\r\n  {\r\n    uint32_t i = 0;\r\n    int32_t rOffset, dst_end;\r\n\r\n    /* Copy the value of Index pointer that points\r\n     * to the current location from where the input samples to be read */\r\n    rOffset = *readOffset;\r\n\r\n    dst_end = (int32_t) (dst_base + dst_length);\r\n\r\n    /* Loop over the blockSize */\r\n    i = blockSize;\r\n\r\n    while(i > 0u)\r\n    {\r\n      /* copy the sample from the circular buffer to the destination buffer */\r\n      *dst = circBuffer[rOffset];\r\n\r\n      /* Update the input pointer */\r\n      dst += dstInc;\r\n\r\n      if(dst == (q7_t *) dst_end)\r\n      {\r\n        dst = dst_base;\r\n      }\r\n\r\n      /* Circularly update rOffset.  Watch out for positive and negative value */\r\n      rOffset += bufferInc;\r\n\r\n      if(rOffset >= L)\r\n      {\r\n        rOffset -= L;\r\n      }\r\n\r\n      /* Decrement the loop counter */\r\n      i--;\r\n    }\r\n\r\n    /* Update the index pointer */\r\n    *readOffset = rOffset;\r\n  }\r\n\r\n\r\n  /**\r\n   * @brief  Sum of the squares of the elements of a Q31 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output value.\r\n   */\r\n  void arm_power_q31(\r\n  q31_t * pSrc,\r\n  uint32_t blockSize,\r\n  q63_t * pResult);\r\n\r\n\r\n  /**\r\n   * @brief  Sum of the squares of the elements of a floating-point vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output value.\r\n   */\r\n  void arm_power_f32(\r\n  float32_t * pSrc,\r\n  uint32_t blockSize,\r\n  float32_t * pResult);\r\n\r\n\r\n  /**\r\n   * @brief  Sum of the squares of the elements of a Q15 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output value.\r\n   */\r\n  void arm_power_q15(\r\n  q15_t * pSrc,\r\n  uint32_t blockSize,\r\n  q63_t * pResult);\r\n\r\n\r\n  /**\r\n   * @brief  Sum of the squares of the elements of a Q7 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output value.\r\n   */\r\n  void arm_power_q7(\r\n  q7_t * pSrc,\r\n  uint32_t blockSize,\r\n  q31_t * pResult);\r\n\r\n\r\n  /**\r\n   * @brief  Mean value of a Q7 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output value.\r\n   */\r\n  void arm_mean_q7(\r\n  q7_t * pSrc,\r\n  uint32_t blockSize,\r\n  q7_t * pResult);\r\n\r\n\r\n  /**\r\n   * @brief  Mean value of a Q15 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output value.\r\n   */\r\n  void arm_mean_q15(\r\n  q15_t * pSrc,\r\n  uint32_t blockSize,\r\n  q15_t * pResult);\r\n\r\n\r\n  /**\r\n   * @brief  Mean value of a Q31 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output value.\r\n   */\r\n  void arm_mean_q31(\r\n  q31_t * pSrc,\r\n  uint32_t blockSize,\r\n  q31_t * pResult);\r\n\r\n\r\n  /**\r\n   * @brief  Mean value of a floating-point vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output value.\r\n   */\r\n  void arm_mean_f32(\r\n  float32_t * pSrc,\r\n  uint32_t blockSize,\r\n  float32_t * pResult);\r\n\r\n\r\n  /**\r\n   * @brief  Variance of the elements of a floating-point vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output value.\r\n   */\r\n  void arm_var_f32(\r\n  float32_t * pSrc,\r\n  uint32_t blockSize,\r\n  float32_t * pResult);\r\n\r\n\r\n  /**\r\n   * @brief  Variance of the elements of a Q31 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output value.\r\n   */\r\n  void arm_var_q31(\r\n  q31_t * pSrc,\r\n  uint32_t blockSize,\r\n  q31_t * pResult);\r\n\r\n\r\n  /**\r\n   * @brief  Variance of the elements of a Q15 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output value.\r\n   */\r\n  void arm_var_q15(\r\n  q15_t * pSrc,\r\n  uint32_t blockSize,\r\n  q15_t * pResult);\r\n\r\n\r\n  /**\r\n   * @brief  Root Mean Square of the elements of a floating-point vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output value.\r\n   */\r\n  void arm_rms_f32(\r\n  float32_t * pSrc,\r\n  uint32_t blockSize,\r\n  float32_t * pResult);\r\n\r\n\r\n  /**\r\n   * @brief  Root Mean Square of the elements of a Q31 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output value.\r\n   */\r\n  void arm_rms_q31(\r\n  q31_t * pSrc,\r\n  uint32_t blockSize,\r\n  q31_t * pResult);\r\n\r\n\r\n  /**\r\n   * @brief  Root Mean Square of the elements of a Q15 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output value.\r\n   */\r\n  void arm_rms_q15(\r\n  q15_t * pSrc,\r\n  uint32_t blockSize,\r\n  q15_t * pResult);\r\n\r\n\r\n  /**\r\n   * @brief  Standard deviation of the elements of a floating-point vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output value.\r\n   */\r\n  void arm_std_f32(\r\n  float32_t * pSrc,\r\n  uint32_t blockSize,\r\n  float32_t * pResult);\r\n\r\n\r\n  /**\r\n   * @brief  Standard deviation of the elements of a Q31 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output value.\r\n   */\r\n  void arm_std_q31(\r\n  q31_t * pSrc,\r\n  uint32_t blockSize,\r\n  q31_t * pResult);\r\n\r\n\r\n  /**\r\n   * @brief  Standard deviation of the elements of a Q15 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output value.\r\n   */\r\n  void arm_std_q15(\r\n  q15_t * pSrc,\r\n  uint32_t blockSize,\r\n  q15_t * pResult);\r\n\r\n\r\n  /**\r\n   * @brief  Floating-point complex magnitude\r\n   * @param[in]  pSrc        points to the complex input vector\r\n   * @param[out] pDst        points to the real output vector\r\n   * @param[in]  numSamples  number of complex samples in the input vector\r\n   */\r\n  void arm_cmplx_mag_f32(\r\n  float32_t * pSrc,\r\n  float32_t * pDst,\r\n  uint32_t numSamples);\r\n\r\n\r\n  /**\r\n   * @brief  Q31 complex magnitude\r\n   * @param[in]  pSrc        points to the complex input vector\r\n   * @param[out] pDst        points to the real output vector\r\n   * @param[in]  numSamples  number of complex samples in the input vector\r\n   */\r\n  void arm_cmplx_mag_q31(\r\n  q31_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t numSamples);\r\n\r\n\r\n  /**\r\n   * @brief  Q15 complex magnitude\r\n   * @param[in]  pSrc        points to the complex input vector\r\n   * @param[out] pDst        points to the real output vector\r\n   * @param[in]  numSamples  number of complex samples in the input vector\r\n   */\r\n  void arm_cmplx_mag_q15(\r\n  q15_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t numSamples);\r\n\r\n\r\n  /**\r\n   * @brief  Q15 complex dot product\r\n   * @param[in]  pSrcA       points to the first input vector\r\n   * @param[in]  pSrcB       points to the second input vector\r\n   * @param[in]  numSamples  number of complex samples in each vector\r\n   * @param[out] realResult  real part of the result returned here\r\n   * @param[out] imagResult  imaginary part of the result returned here\r\n   */\r\n  void arm_cmplx_dot_prod_q15(\r\n  q15_t * pSrcA,\r\n  q15_t * pSrcB,\r\n  uint32_t numSamples,\r\n  q31_t * realResult,\r\n  q31_t * imagResult);\r\n\r\n\r\n  /**\r\n   * @brief  Q31 complex dot product\r\n   * @param[in]  pSrcA       points to the first input vector\r\n   * @param[in]  pSrcB       points to the second input vector\r\n   * @param[in]  numSamples  number of complex samples in each vector\r\n   * @param[out] realResult  real part of the result returned here\r\n   * @param[out] imagResult  imaginary part of the result returned here\r\n   */\r\n  void arm_cmplx_dot_prod_q31(\r\n  q31_t * pSrcA,\r\n  q31_t * pSrcB,\r\n  uint32_t numSamples,\r\n  q63_t * realResult,\r\n  q63_t * imagResult);\r\n\r\n\r\n  /**\r\n   * @brief  Floating-point complex dot product\r\n   * @param[in]  pSrcA       points to the first input vector\r\n   * @param[in]  pSrcB       points to the second input vector\r\n   * @param[in]  numSamples  number of complex samples in each vector\r\n   * @param[out] realResult  real part of the result returned here\r\n   * @param[out] imagResult  imaginary part of the result returned here\r\n   */\r\n  void arm_cmplx_dot_prod_f32(\r\n  float32_t * pSrcA,\r\n  float32_t * pSrcB,\r\n  uint32_t numSamples,\r\n  float32_t * realResult,\r\n  float32_t * imagResult);\r\n\r\n\r\n  /**\r\n   * @brief  Q15 complex-by-real multiplication\r\n   * @param[in]  pSrcCmplx   points to the complex input vector\r\n   * @param[in]  pSrcReal    points to the real input vector\r\n   * @param[out] pCmplxDst   points to the complex output vector\r\n   * @param[in]  numSamples  number of samples in each vector\r\n   */\r\n  void arm_cmplx_mult_real_q15(\r\n  q15_t * pSrcCmplx,\r\n  q15_t * pSrcReal,\r\n  q15_t * pCmplxDst,\r\n  uint32_t numSamples);\r\n\r\n\r\n  /**\r\n   * @brief  Q31 complex-by-real multiplication\r\n   * @param[in]  pSrcCmplx   points to the complex input vector\r\n   * @param[in]  pSrcReal    points to the real input vector\r\n   * @param[out] pCmplxDst   points to the complex output vector\r\n   * @param[in]  numSamples  number of samples in each vector\r\n   */\r\n  void arm_cmplx_mult_real_q31(\r\n  q31_t * pSrcCmplx,\r\n  q31_t * pSrcReal,\r\n  q31_t * pCmplxDst,\r\n  uint32_t numSamples);\r\n\r\n\r\n  /**\r\n   * @brief  Floating-point complex-by-real multiplication\r\n   * @param[in]  pSrcCmplx   points to the complex input vector\r\n   * @param[in]  pSrcReal    points to the real input vector\r\n   * @param[out] pCmplxDst   points to the complex output vector\r\n   * @param[in]  numSamples  number of samples in each vector\r\n   */\r\n  void arm_cmplx_mult_real_f32(\r\n  float32_t * pSrcCmplx,\r\n  float32_t * pSrcReal,\r\n  float32_t * pCmplxDst,\r\n  uint32_t numSamples);\r\n\r\n\r\n  /**\r\n   * @brief  Minimum value of a Q7 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] result     is output pointer\r\n   * @param[in]  index      is the array index of the minimum value in the input buffer.\r\n   */\r\n  void arm_min_q7(\r\n  q7_t * pSrc,\r\n  uint32_t blockSize,\r\n  q7_t * result,\r\n  uint32_t * index);\r\n\r\n\r\n  /**\r\n   * @brief  Minimum value of a Q15 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output pointer\r\n   * @param[in]  pIndex     is the array index of the minimum value in the input buffer.\r\n   */\r\n  void arm_min_q15(\r\n  q15_t * pSrc,\r\n  uint32_t blockSize,\r\n  q15_t * pResult,\r\n  uint32_t * pIndex);\r\n\r\n\r\n  /**\r\n   * @brief  Minimum value of a Q31 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output pointer\r\n   * @param[out] pIndex     is the array index of the minimum value in the input buffer.\r\n   */\r\n  void arm_min_q31(\r\n  q31_t * pSrc,\r\n  uint32_t blockSize,\r\n  q31_t * pResult,\r\n  uint32_t * pIndex);\r\n\r\n\r\n  /**\r\n   * @brief  Minimum value of a floating-point vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   * @param[out] pResult    is output pointer\r\n   * @param[out] pIndex     is the array index of the minimum value in the input buffer.\r\n   */\r\n  void arm_min_f32(\r\n  float32_t * pSrc,\r\n  uint32_t blockSize,\r\n  float32_t * pResult,\r\n  uint32_t * pIndex);\r\n\r\n\r\n/**\r\n * @brief Maximum value of a Q7 vector.\r\n * @param[in]  pSrc       points to the input buffer\r\n * @param[in]  blockSize  length of the input vector\r\n * @param[out] pResult    maximum value returned here\r\n * @param[out] pIndex     index of maximum value returned here\r\n */\r\n  void arm_max_q7(\r\n  q7_t * pSrc,\r\n  uint32_t blockSize,\r\n  q7_t * pResult,\r\n  uint32_t * pIndex);\r\n\r\n\r\n/**\r\n * @brief Maximum value of a Q15 vector.\r\n * @param[in]  pSrc       points to the input buffer\r\n * @param[in]  blockSize  length of the input vector\r\n * @param[out] pResult    maximum value returned here\r\n * @param[out] pIndex     index of maximum value returned here\r\n */\r\n  void arm_max_q15(\r\n  q15_t * pSrc,\r\n  uint32_t blockSize,\r\n  q15_t * pResult,\r\n  uint32_t * pIndex);\r\n\r\n\r\n/**\r\n * @brief Maximum value of a Q31 vector.\r\n * @param[in]  pSrc       points to the input buffer\r\n * @param[in]  blockSize  length of the input vector\r\n * @param[out] pResult    maximum value returned here\r\n * @param[out] pIndex     index of maximum value returned here\r\n */\r\n  void arm_max_q31(\r\n  q31_t * pSrc,\r\n  uint32_t blockSize,\r\n  q31_t * pResult,\r\n  uint32_t * pIndex);\r\n\r\n\r\n/**\r\n * @brief Maximum value of a floating-point vector.\r\n * @param[in]  pSrc       points to the input buffer\r\n * @param[in]  blockSize  length of the input vector\r\n * @param[out] pResult    maximum value returned here\r\n * @param[out] pIndex     index of maximum value returned here\r\n */\r\n  void arm_max_f32(\r\n  float32_t * pSrc,\r\n  uint32_t blockSize,\r\n  float32_t * pResult,\r\n  uint32_t * pIndex);\r\n\r\n\r\n  /**\r\n   * @brief  Q15 complex-by-complex multiplication\r\n   * @param[in]  pSrcA       points to the first input vector\r\n   * @param[in]  pSrcB       points to the second input vector\r\n   * @param[out] pDst        points to the output vector\r\n   * @param[in]  numSamples  number of complex samples in each vector\r\n   */\r\n  void arm_cmplx_mult_cmplx_q15(\r\n  q15_t * pSrcA,\r\n  q15_t * pSrcB,\r\n  q15_t * pDst,\r\n  uint32_t numSamples);\r\n\r\n\r\n  /**\r\n   * @brief  Q31 complex-by-complex multiplication\r\n   * @param[in]  pSrcA       points to the first input vector\r\n   * @param[in]  pSrcB       points to the second input vector\r\n   * @param[out] pDst        points to the output vector\r\n   * @param[in]  numSamples  number of complex samples in each vector\r\n   */\r\n  void arm_cmplx_mult_cmplx_q31(\r\n  q31_t * pSrcA,\r\n  q31_t * pSrcB,\r\n  q31_t * pDst,\r\n  uint32_t numSamples);\r\n\r\n\r\n  /**\r\n   * @brief  Floating-point complex-by-complex multiplication\r\n   * @param[in]  pSrcA       points to the first input vector\r\n   * @param[in]  pSrcB       points to the second input vector\r\n   * @param[out] pDst        points to the output vector\r\n   * @param[in]  numSamples  number of complex samples in each vector\r\n   */\r\n  void arm_cmplx_mult_cmplx_f32(\r\n  float32_t * pSrcA,\r\n  float32_t * pSrcB,\r\n  float32_t * pDst,\r\n  uint32_t numSamples);\r\n\r\n\r\n  /**\r\n   * @brief Converts the elements of the floating-point vector to Q31 vector.\r\n   * @param[in]  pSrc       points to the floating-point input vector\r\n   * @param[out] pDst       points to the Q31 output vector\r\n   * @param[in]  blockSize  length of the input vector\r\n   */\r\n  void arm_float_to_q31(\r\n  float32_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Converts the elements of the floating-point vector to Q15 vector.\r\n   * @param[in]  pSrc       points to the floating-point input vector\r\n   * @param[out] pDst       points to the Q15 output vector\r\n   * @param[in]  blockSize  length of the input vector\r\n   */\r\n  void arm_float_to_q15(\r\n  float32_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief Converts the elements of the floating-point vector to Q7 vector.\r\n   * @param[in]  pSrc       points to the floating-point input vector\r\n   * @param[out] pDst       points to the Q7 output vector\r\n   * @param[in]  blockSize  length of the input vector\r\n   */\r\n  void arm_float_to_q7(\r\n  float32_t * pSrc,\r\n  q7_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Converts the elements of the Q31 vector to Q15 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[out] pDst       is output pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   */\r\n  void arm_q31_to_q15(\r\n  q31_t * pSrc,\r\n  q15_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Converts the elements of the Q31 vector to Q7 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[out] pDst       is output pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   */\r\n  void arm_q31_to_q7(\r\n  q31_t * pSrc,\r\n  q7_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Converts the elements of the Q15 vector to floating-point vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[out] pDst       is output pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   */\r\n  void arm_q15_to_float(\r\n  q15_t * pSrc,\r\n  float32_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Converts the elements of the Q15 vector to Q31 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[out] pDst       is output pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   */\r\n  void arm_q15_to_q31(\r\n  q15_t * pSrc,\r\n  q31_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @brief  Converts the elements of the Q15 vector to Q7 vector.\r\n   * @param[in]  pSrc       is input pointer\r\n   * @param[out] pDst       is output pointer\r\n   * @param[in]  blockSize  is the number of samples to process\r\n   */\r\n  void arm_q15_to_q7(\r\n  q15_t * pSrc,\r\n  q7_t * pDst,\r\n  uint32_t blockSize);\r\n\r\n\r\n  /**\r\n   * @ingroup groupInterpolation\r\n   */\r\n\r\n  /**\r\n   * @defgroup BilinearInterpolate Bilinear Interpolation\r\n   *\r\n   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.\r\n   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process\r\n   * determines values between the grid points.\r\n   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.\r\n   * Bilinear interpolation is often used in image processing to rescale images.\r\n   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.\r\n   *\r\n   * <b>Algorithm</b>\r\n   * \\par\r\n   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.\r\n   * For floating-point, the instance structure is defined as:\r\n   * <pre>\r\n   *   typedef struct\r\n   *   {\r\n   *     uint16_t numRows;\r\n   *     uint16_t numCols;\r\n   *     float32_t *pData;\r\n   * } arm_bilinear_interp_instance_f32;\r\n   * </pre>\r\n   *\r\n   * \\par\r\n   * where <code>numRows</code> specifies the number of rows in the table;\r\n   * <code>numCols</code> specifies the number of columns in the table;\r\n   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.\r\n   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.\r\n   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.\r\n   *\r\n   * \\par\r\n   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:\r\n   * <pre>\r\n   *     XF = floor(x)\r\n   *     YF = floor(y)\r\n   * </pre>\r\n   * \\par\r\n   * The interpolated output point is computed as:\r\n   * <pre>\r\n   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))\r\n   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))\r\n   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)\r\n   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)\r\n   * </pre>\r\n   * Note that the coordinates (x, y) contain integer and fractional components.\r\n   * The integer components specify which portion of the table to use while the\r\n   * fractional components control the interpolation processor.\r\n   *\r\n   * \\par\r\n   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.\r\n   */\r\n\r\n  /**\r\n   * @addtogroup BilinearInterpolate\r\n   * @{\r\n   */\r\n\r\n\r\n  /**\r\n  *\r\n  * @brief  Floating-point bilinear interpolation.\r\n  * @param[in,out] S  points to an instance of the interpolation structure.\r\n  * @param[in]     X  interpolation coordinate.\r\n  * @param[in]     Y  interpolation coordinate.\r\n  * @return out interpolated value.\r\n  */\r\n  static __INLINE float32_t arm_bilinear_interp_f32(\r\n  const arm_bilinear_interp_instance_f32 * S,\r\n  float32_t X,\r\n  float32_t Y)\r\n  {\r\n    float32_t out;\r\n    float32_t f00, f01, f10, f11;\r\n    float32_t *pData = S->pData;\r\n    int32_t xIndex, yIndex, index;\r\n    float32_t xdiff, ydiff;\r\n    float32_t b1, b2, b3, b4;\r\n\r\n    xIndex = (int32_t) X;\r\n    yIndex = (int32_t) Y;\r\n\r\n    /* Care taken for table outside boundary */\r\n    /* Returns zero output when values are outside table boundary */\r\n    if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))\r\n    {\r\n      return (0);\r\n    }\r\n\r\n    /* Calculation of index for two nearest points in X-direction */\r\n    index = (xIndex - 1) + (yIndex - 1) * S->numCols;\r\n\r\n\r\n    /* Read two nearest points in X-direction */\r\n    f00 = pData[index];\r\n    f01 = pData[index + 1];\r\n\r\n    /* Calculation of index for two nearest points in Y-direction */\r\n    index = (xIndex - 1) + (yIndex) * S->numCols;\r\n\r\n\r\n    /* Read two nearest points in Y-direction */\r\n    f10 = pData[index];\r\n    f11 = pData[index + 1];\r\n\r\n    /* Calculation of intermediate values */\r\n    b1 = f00;\r\n    b2 = f01 - f00;\r\n    b3 = f10 - f00;\r\n    b4 = f00 - f01 - f10 + f11;\r\n\r\n    /* Calculation of fractional part in X */\r\n    xdiff = X - xIndex;\r\n\r\n    /* Calculation of fractional part in Y */\r\n    ydiff = Y - yIndex;\r\n\r\n    /* Calculation of bi-linear interpolated output */\r\n    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;\r\n\r\n    /* return to application */\r\n    return (out);\r\n  }\r\n\r\n\r\n  /**\r\n  *\r\n  * @brief  Q31 bilinear interpolation.\r\n  * @param[in,out] S  points to an instance of the interpolation structure.\r\n  * @param[in]     X  interpolation coordinate in 12.20 format.\r\n  * @param[in]     Y  interpolation coordinate in 12.20 format.\r\n  * @return out interpolated value.\r\n  */\r\n  static __INLINE q31_t arm_bilinear_interp_q31(\r\n  arm_bilinear_interp_instance_q31 * S,\r\n  q31_t X,\r\n  q31_t Y)\r\n  {\r\n    q31_t out;                                   /* Temporary output */\r\n    q31_t acc = 0;                               /* output */\r\n    q31_t xfract, yfract;                        /* X, Y fractional parts */\r\n    q31_t x1, x2, y1, y2;                        /* Nearest output values */\r\n    int32_t rI, cI;                              /* Row and column indices */\r\n    q31_t *pYData = S->pData;                    /* pointer to output table values */\r\n    uint32_t nCols = S->numCols;                 /* num of rows */\r\n\r\n    /* Input is in 12.20 format */\r\n    /* 12 bits for the table index */\r\n    /* Index value calculation */\r\n    rI = ((X & (q31_t)0xFFF00000) >> 20);\r\n\r\n    /* Input is in 12.20 format */\r\n    /* 12 bits for the table index */\r\n    /* Index value calculation */\r\n    cI = ((Y & (q31_t)0xFFF00000) >> 20);\r\n\r\n    /* Care taken for table outside boundary */\r\n    /* Returns zero output when values are outside table boundary */\r\n    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\r\n    {\r\n      return (0);\r\n    }\r\n\r\n    /* 20 bits for the fractional part */\r\n    /* shift left xfract by 11 to keep 1.31 format */\r\n    xfract = (X & 0x000FFFFF) << 11u;\r\n\r\n    /* Read two nearest output values from the index */\r\n    x1 = pYData[(rI) + (int32_t)nCols * (cI)    ];\r\n    x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];\r\n\r\n    /* 20 bits for the fractional part */\r\n    /* shift left yfract by 11 to keep 1.31 format */\r\n    yfract = (Y & 0x000FFFFF) << 11u;\r\n\r\n    /* Read two nearest output values from the index */\r\n    y1 = pYData[(rI) + (int32_t)nCols * (cI + 1)    ];\r\n    y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];\r\n\r\n    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */\r\n    out = ((q31_t) (((q63_t) x1  * (0x7FFFFFFF - xfract)) >> 32));\r\n    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));\r\n\r\n    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */\r\n    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));\r\n    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));\r\n\r\n    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */\r\n    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));\r\n    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\r\n\r\n    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */\r\n    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));\r\n    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\r\n\r\n    /* Convert acc to 1.31(q31) format */\r\n    return ((q31_t)(acc << 2));\r\n  }\r\n\r\n\r\n  /**\r\n  * @brief  Q15 bilinear interpolation.\r\n  * @param[in,out] S  points to an instance of the interpolation structure.\r\n  * @param[in]     X  interpolation coordinate in 12.20 format.\r\n  * @param[in]     Y  interpolation coordinate in 12.20 format.\r\n  * @return out interpolated value.\r\n  */\r\n  static __INLINE q15_t arm_bilinear_interp_q15(\r\n  arm_bilinear_interp_instance_q15 * S,\r\n  q31_t X,\r\n  q31_t Y)\r\n  {\r\n    q63_t acc = 0;                               /* output */\r\n    q31_t out;                                   /* Temporary output */\r\n    q15_t x1, x2, y1, y2;                        /* Nearest output values */\r\n    q31_t xfract, yfract;                        /* X, Y fractional parts */\r\n    int32_t rI, cI;                              /* Row and column indices */\r\n    q15_t *pYData = S->pData;                    /* pointer to output table values */\r\n    uint32_t nCols = S->numCols;                 /* num of rows */\r\n\r\n    /* Input is in 12.20 format */\r\n    /* 12 bits for the table index */\r\n    /* Index value calculation */\r\n    rI = ((X & (q31_t)0xFFF00000) >> 20);\r\n\r\n    /* Input is in 12.20 format */\r\n    /* 12 bits for the table index */\r\n    /* Index value calculation */\r\n    cI = ((Y & (q31_t)0xFFF00000) >> 20);\r\n\r\n    /* Care taken for table outside boundary */\r\n    /* Returns zero output when values are outside table boundary */\r\n    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\r\n    {\r\n      return (0);\r\n    }\r\n\r\n    /* 20 bits for the fractional part */\r\n    /* xfract should be in 12.20 format */\r\n    xfract = (X & 0x000FFFFF);\r\n\r\n    /* Read two nearest output values from the index */\r\n    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];\r\n    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];\r\n\r\n    /* 20 bits for the fractional part */\r\n    /* yfract should be in 12.20 format */\r\n    yfract = (Y & 0x000FFFFF);\r\n\r\n    /* Read two nearest output values from the index */\r\n    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];\r\n    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];\r\n\r\n    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */\r\n\r\n    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */\r\n    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */\r\n    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);\r\n    acc = ((q63_t) out * (0xFFFFF - yfract));\r\n\r\n    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */\r\n    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);\r\n    acc += ((q63_t) out * (xfract));\r\n\r\n    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */\r\n    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);\r\n    acc += ((q63_t) out * (yfract));\r\n\r\n    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */\r\n    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);\r\n    acc += ((q63_t) out * (yfract));\r\n\r\n    /* acc is in 13.51 format and down shift acc by 36 times */\r\n    /* Convert out to 1.15 format */\r\n    return ((q15_t)(acc >> 36));\r\n  }\r\n\r\n\r\n  /**\r\n  * @brief  Q7 bilinear interpolation.\r\n  * @param[in,out] S  points to an instance of the interpolation structure.\r\n  * @param[in]     X  interpolation coordinate in 12.20 format.\r\n  * @param[in]     Y  interpolation coordinate in 12.20 format.\r\n  * @return out interpolated value.\r\n  */\r\n  static __INLINE q7_t arm_bilinear_interp_q7(\r\n  arm_bilinear_interp_instance_q7 * S,\r\n  q31_t X,\r\n  q31_t Y)\r\n  {\r\n    q63_t acc = 0;                               /* output */\r\n    q31_t out;                                   /* Temporary output */\r\n    q31_t xfract, yfract;                        /* X, Y fractional parts */\r\n    q7_t x1, x2, y1, y2;                         /* Nearest output values */\r\n    int32_t rI, cI;                              /* Row and column indices */\r\n    q7_t *pYData = S->pData;                     /* pointer to output table values */\r\n    uint32_t nCols = S->numCols;                 /* num of rows */\r\n\r\n    /* Input is in 12.20 format */\r\n    /* 12 bits for the table index */\r\n    /* Index value calculation */\r\n    rI = ((X & (q31_t)0xFFF00000) >> 20);\r\n\r\n    /* Input is in 12.20 format */\r\n    /* 12 bits for the table index */\r\n    /* Index value calculation */\r\n    cI = ((Y & (q31_t)0xFFF00000) >> 20);\r\n\r\n    /* Care taken for table outside boundary */\r\n    /* Returns zero output when values are outside table boundary */\r\n    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\r\n    {\r\n      return (0);\r\n    }\r\n\r\n    /* 20 bits for the fractional part */\r\n    /* xfract should be in 12.20 format */\r\n    xfract = (X & (q31_t)0x000FFFFF);\r\n\r\n    /* Read two nearest output values from the index */\r\n    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];\r\n    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];\r\n\r\n    /* 20 bits for the fractional part */\r\n    /* yfract should be in 12.20 format */\r\n    yfract = (Y & (q31_t)0x000FFFFF);\r\n\r\n    /* Read two nearest output values from the index */\r\n    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];\r\n    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];\r\n\r\n    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */\r\n    out = ((x1 * (0xFFFFF - xfract)));\r\n    acc = (((q63_t) out * (0xFFFFF - yfract)));\r\n\r\n    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */\r\n    out = ((x2 * (0xFFFFF - yfract)));\r\n    acc += (((q63_t) out * (xfract)));\r\n\r\n    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */\r\n    out = ((y1 * (0xFFFFF - xfract)));\r\n    acc += (((q63_t) out * (yfract)));\r\n\r\n    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */\r\n    out = ((y2 * (yfract)));\r\n    acc += (((q63_t) out * (xfract)));\r\n\r\n    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */\r\n    return ((q7_t)(acc >> 40));\r\n  }\r\n\r\n  /**\r\n   * @} end of BilinearInterpolate group\r\n   */\r\n\r\n\r\n/* SMMLAR */\r\n#define multAcc_32x32_keep32_R(a, x, y) \\\r\n    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)\r\n\r\n/* SMMLSR */\r\n#define multSub_32x32_keep32_R(a, x, y) \\\r\n    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)\r\n\r\n/* SMMULR */\r\n#define mult_32x32_keep32_R(a, x, y) \\\r\n    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)\r\n\r\n/* SMMLA */\r\n#define multAcc_32x32_keep32(a, x, y) \\\r\n    a += (q31_t) (((q63_t) x * y) >> 32)\r\n\r\n/* SMMLS */\r\n#define multSub_32x32_keep32(a, x, y) \\\r\n    a -= (q31_t) (((q63_t) x * y) >> 32)\r\n\r\n/* SMMUL */\r\n#define mult_32x32_keep32(a, x, y) \\\r\n    a = (q31_t) (((q63_t) x * y ) >> 32)\r\n\r\n\r\n#if defined ( __CC_ARM )\r\n  /* Enter low optimization region - place directly above function definition */\r\n  #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)\r\n    #define LOW_OPTIMIZATION_ENTER \\\r\n       _Pragma (\"push\")         \\\r\n       _Pragma (\"O1\")\r\n  #else\r\n    #define LOW_OPTIMIZATION_ENTER\r\n  #endif\r\n\r\n  /* Exit low optimization region - place directly after end of function definition */\r\n  #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)\r\n    #define LOW_OPTIMIZATION_EXIT \\\r\n       _Pragma (\"pop\")\r\n  #else\r\n    #define LOW_OPTIMIZATION_EXIT\r\n  #endif\r\n\r\n  /* Enter low optimization region - place directly above function definition */\r\n  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r\n\r\n  /* Exit low optimization region - place directly after end of function definition */\r\n  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r\n\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #define LOW_OPTIMIZATION_ENTER\r\n  #define LOW_OPTIMIZATION_EXIT\r\n  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r\n  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r\n\r\n#elif defined(__GNUC__)\r\n  #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize(\"-O1\") ))\r\n  #define LOW_OPTIMIZATION_EXIT\r\n  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r\n  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r\n\r\n#elif defined(__ICCARM__)\r\n  /* Enter low optimization region - place directly above function definition */\r\n  #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)\r\n    #define LOW_OPTIMIZATION_ENTER \\\r\n       _Pragma (\"optimize=low\")\r\n  #else\r\n    #define LOW_OPTIMIZATION_ENTER\r\n  #endif\r\n\r\n  /* Exit low optimization region - place directly after end of function definition */\r\n  #define LOW_OPTIMIZATION_EXIT\r\n\r\n  /* Enter low optimization region - place directly above function definition */\r\n  #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)\r\n    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \\\r\n       _Pragma (\"optimize=low\")\r\n  #else\r\n    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r\n  #endif\r\n\r\n  /* Exit low optimization region - place directly after end of function definition */\r\n  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r\n\r\n#elif defined(__CSMC__)\r\n  #define LOW_OPTIMIZATION_ENTER\r\n  #define LOW_OPTIMIZATION_EXIT\r\n  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r\n  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r\n\r\n#elif defined(__TASKING__)\r\n  #define LOW_OPTIMIZATION_ENTER\r\n  #define LOW_OPTIMIZATION_EXIT\r\n  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r\n  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r\n\r\n#endif\r\n\r\n\r\n#ifdef   __cplusplus\r\n}\r\n#endif\r\n\r\n\r\n#if defined ( __GNUC__ )\r\n#pragma GCC diagnostic pop\r\n#endif\r\n\r\n#endif /* _ARM_MATH_H */\r\n\r\n/**\r\n *\r\n * End of file.\r\n */\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/include/cmsis_armcc.h",
    "content": "/**************************************************************************//**\r\n * @file     cmsis_armcc.h\r\n * @brief    CMSIS Cortex-M Core Function/Instruction Header File\r\n * @version  V4.30\r\n * @date     20. October 2015\r\n ******************************************************************************/\r\n/* Copyright (c) 2009 - 2015 ARM LIMITED\r\n\r\n   All rights reserved.\r\n   Redistribution and use in source and binary forms, with or without\r\n   modification, are permitted provided that the following conditions are met:\r\n   - Redistributions of source code must retain the above copyright\r\n     notice, this list of conditions and the following disclaimer.\r\n   - Redistributions in binary form must reproduce the above copyright\r\n     notice, this list of conditions and the following disclaimer in the\r\n     documentation and/or other materials provided with the distribution.\r\n   - Neither the name of ARM nor the names of its contributors may be used\r\n     to endorse or promote products derived from this software without\r\n     specific prior written permission.\r\n   *\r\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n   POSSIBILITY OF SUCH DAMAGE.\r\n   ---------------------------------------------------------------------------*/\r\n\r\n\r\n#ifndef __CMSIS_ARMCC_H\r\n#define __CMSIS_ARMCC_H\r\n\r\n\r\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)\r\n  #error \"Please use ARM Compiler Toolchain V4.0.677 or later!\"\r\n#endif\r\n\r\n/* ###########################  Core Function Access  ########################### */\r\n/** \\ingroup  CMSIS_Core_FunctionInterface\r\n    \\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r\n  @{\r\n */\r\n\r\n/* intrinsic void __enable_irq();     */\r\n/* intrinsic void __disable_irq();    */\r\n\r\n/**\r\n  \\brief   Get Control Register\r\n  \\details Returns the content of the Control Register.\r\n  \\return               Control Register value\r\n */\r\n__STATIC_INLINE uint32_t __get_CONTROL(void)\r\n{\r\n  register uint32_t __regControl         __ASM(\"control\");\r\n  return(__regControl);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Control Register\r\n  \\details Writes the given value to the Control Register.\r\n  \\param [in]    control  Control Register value to set\r\n */\r\n__STATIC_INLINE void __set_CONTROL(uint32_t control)\r\n{\r\n  register uint32_t __regControl         __ASM(\"control\");\r\n  __regControl = control;\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get IPSR Register\r\n  \\details Returns the content of the IPSR Register.\r\n  \\return               IPSR Register value\r\n */\r\n__STATIC_INLINE uint32_t __get_IPSR(void)\r\n{\r\n  register uint32_t __regIPSR          __ASM(\"ipsr\");\r\n  return(__regIPSR);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get APSR Register\r\n  \\details Returns the content of the APSR Register.\r\n  \\return               APSR Register value\r\n */\r\n__STATIC_INLINE uint32_t __get_APSR(void)\r\n{\r\n  register uint32_t __regAPSR          __ASM(\"apsr\");\r\n  return(__regAPSR);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get xPSR Register\r\n  \\details Returns the content of the xPSR Register.\r\n  \\return               xPSR Register value\r\n */\r\n__STATIC_INLINE uint32_t __get_xPSR(void)\r\n{\r\n  register uint32_t __regXPSR          __ASM(\"xpsr\");\r\n  return(__regXPSR);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Process Stack Pointer\r\n  \\details Returns the current value of the Process Stack Pointer (PSP).\r\n  \\return               PSP Register value\r\n */\r\n__STATIC_INLINE uint32_t __get_PSP(void)\r\n{\r\n  register uint32_t __regProcessStackPointer  __ASM(\"psp\");\r\n  return(__regProcessStackPointer);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Process Stack Pointer\r\n  \\details Assigns the given value to the Process Stack Pointer (PSP).\r\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\r\n */\r\n__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r\n{\r\n  register uint32_t __regProcessStackPointer  __ASM(\"psp\");\r\n  __regProcessStackPointer = topOfProcStack;\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Main Stack Pointer\r\n  \\details Returns the current value of the Main Stack Pointer (MSP).\r\n  \\return               MSP Register value\r\n */\r\n__STATIC_INLINE uint32_t __get_MSP(void)\r\n{\r\n  register uint32_t __regMainStackPointer     __ASM(\"msp\");\r\n  return(__regMainStackPointer);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Main Stack Pointer\r\n  \\details Assigns the given value to the Main Stack Pointer (MSP).\r\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\r\n */\r\n__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r\n{\r\n  register uint32_t __regMainStackPointer     __ASM(\"msp\");\r\n  __regMainStackPointer = topOfMainStack;\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Priority Mask\r\n  \\details Returns the current state of the priority mask bit from the Priority Mask Register.\r\n  \\return               Priority Mask value\r\n */\r\n__STATIC_INLINE uint32_t __get_PRIMASK(void)\r\n{\r\n  register uint32_t __regPriMask         __ASM(\"primask\");\r\n  return(__regPriMask);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Priority Mask\r\n  \\details Assigns the given value to the Priority Mask Register.\r\n  \\param [in]    priMask  Priority Mask\r\n */\r\n__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r\n{\r\n  register uint32_t __regPriMask         __ASM(\"primask\");\r\n  __regPriMask = (priMask);\r\n}\r\n\r\n\r\n#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\r\n\r\n/**\r\n  \\brief   Enable FIQ\r\n  \\details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r\n           Can only be executed in Privileged modes.\r\n */\r\n#define __enable_fault_irq                __enable_fiq\r\n\r\n\r\n/**\r\n  \\brief   Disable FIQ\r\n  \\details Disables FIQ interrupts by setting the F-bit in the CPSR.\r\n           Can only be executed in Privileged modes.\r\n */\r\n#define __disable_fault_irq               __disable_fiq\r\n\r\n\r\n/**\r\n  \\brief   Get Base Priority\r\n  \\details Returns the current value of the Base Priority register.\r\n  \\return               Base Priority register value\r\n */\r\n__STATIC_INLINE uint32_t  __get_BASEPRI(void)\r\n{\r\n  register uint32_t __regBasePri         __ASM(\"basepri\");\r\n  return(__regBasePri);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Base Priority\r\n  \\details Assigns the given value to the Base Priority register.\r\n  \\param [in]    basePri  Base Priority value to set\r\n */\r\n__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)\r\n{\r\n  register uint32_t __regBasePri         __ASM(\"basepri\");\r\n  __regBasePri = (basePri & 0xFFU);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Base Priority with condition\r\n  \\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r\n           or the new value increases the BASEPRI priority level.\r\n  \\param [in]    basePri  Base Priority value to set\r\n */\r\n__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)\r\n{\r\n  register uint32_t __regBasePriMax      __ASM(\"basepri_max\");\r\n  __regBasePriMax = (basePri & 0xFFU);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Fault Mask\r\n  \\details Returns the current value of the Fault Mask register.\r\n  \\return               Fault Mask register value\r\n */\r\n__STATIC_INLINE uint32_t __get_FAULTMASK(void)\r\n{\r\n  register uint32_t __regFaultMask       __ASM(\"faultmask\");\r\n  return(__regFaultMask);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Fault Mask\r\n  \\details Assigns the given value to the Fault Mask register.\r\n  \\param [in]    faultMask  Fault Mask value to set\r\n */\r\n__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r\n{\r\n  register uint32_t __regFaultMask       __ASM(\"faultmask\");\r\n  __regFaultMask = (faultMask & (uint32_t)1);\r\n}\r\n\r\n#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */\r\n\r\n\r\n#if       (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)\r\n\r\n/**\r\n  \\brief   Get FPSCR\r\n  \\details Returns the current value of the Floating Point Status/Control register.\r\n  \\return               Floating Point Status/Control register value\r\n */\r\n__STATIC_INLINE uint32_t __get_FPSCR(void)\r\n{\r\n#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r\n  register uint32_t __regfpscr         __ASM(\"fpscr\");\r\n  return(__regfpscr);\r\n#else\r\n   return(0U);\r\n#endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set FPSCR\r\n  \\details Assigns the given value to the Floating Point Status/Control register.\r\n  \\param [in]    fpscr  Floating Point Status/Control value to set\r\n */\r\n__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r\n{\r\n#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r\n  register uint32_t __regfpscr         __ASM(\"fpscr\");\r\n  __regfpscr = (fpscr);\r\n#endif\r\n}\r\n\r\n#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */\r\n\r\n\r\n\r\n/*@} end of CMSIS_Core_RegAccFunctions */\r\n\r\n\r\n/* ##########################  Core Instruction Access  ######################### */\r\n/** \\defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r\n  Access to dedicated instructions\r\n  @{\r\n*/\r\n\r\n/**\r\n  \\brief   No Operation\r\n  \\details No Operation does nothing. This instruction can be used for code alignment purposes.\r\n */\r\n#define __NOP                             __nop\r\n\r\n\r\n/**\r\n  \\brief   Wait For Interrupt\r\n  \\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r\n */\r\n#define __WFI                             __wfi\r\n\r\n\r\n/**\r\n  \\brief   Wait For Event\r\n  \\details Wait For Event is a hint instruction that permits the processor to enter\r\n           a low-power state until one of a number of events occurs.\r\n */\r\n#define __WFE                             __wfe\r\n\r\n\r\n/**\r\n  \\brief   Send Event\r\n  \\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r\n */\r\n#define __SEV                             __sev\r\n\r\n\r\n/**\r\n  \\brief   Instruction Synchronization Barrier\r\n  \\details Instruction Synchronization Barrier flushes the pipeline in the processor,\r\n           so that all instructions following the ISB are fetched from cache or memory,\r\n           after the instruction has been completed.\r\n */\r\n#define __ISB() do {\\\r\n                   __schedule_barrier();\\\r\n                   __isb(0xF);\\\r\n                   __schedule_barrier();\\\r\n                } while (0U)\r\n\r\n/**\r\n  \\brief   Data Synchronization Barrier\r\n  \\details Acts as a special kind of Data Memory Barrier.\r\n           It completes when all explicit memory accesses before this instruction complete.\r\n */\r\n#define __DSB() do {\\\r\n                   __schedule_barrier();\\\r\n                   __dsb(0xF);\\\r\n                   __schedule_barrier();\\\r\n                } while (0U)\r\n\r\n/**\r\n  \\brief   Data Memory Barrier\r\n  \\details Ensures the apparent order of the explicit memory operations before\r\n           and after the instruction, without ensuring their completion.\r\n */\r\n#define __DMB() do {\\\r\n                   __schedule_barrier();\\\r\n                   __dmb(0xF);\\\r\n                   __schedule_barrier();\\\r\n                } while (0U)\r\n\r\n/**\r\n  \\brief   Reverse byte order (32 bit)\r\n  \\details Reverses the byte order in integer value.\r\n  \\param [in]    value  Value to reverse\r\n  \\return               Reversed value\r\n */\r\n#define __REV                             __rev\r\n\r\n\r\n/**\r\n  \\brief   Reverse byte order (16 bit)\r\n  \\details Reverses the byte order in two unsigned short values.\r\n  \\param [in]    value  Value to reverse\r\n  \\return               Reversed value\r\n */\r\n#ifndef __NO_EMBEDDED_ASM\r\n__attribute__((section(\".rev16_text\"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)\r\n{\r\n  rev16 r0, r0\r\n  bx lr\r\n}\r\n#endif\r\n\r\n/**\r\n  \\brief   Reverse byte order in signed short value\r\n  \\details Reverses the byte order in a signed short value with sign extension to integer.\r\n  \\param [in]    value  Value to reverse\r\n  \\return               Reversed value\r\n */\r\n#ifndef __NO_EMBEDDED_ASM\r\n__attribute__((section(\".revsh_text\"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)\r\n{\r\n  revsh r0, r0\r\n  bx lr\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Rotate Right in unsigned value (32 bit)\r\n  \\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r\n  \\param [in]    value  Value to rotate\r\n  \\param [in]    value  Number of Bits to rotate\r\n  \\return               Rotated value\r\n */\r\n#define __ROR                             __ror\r\n\r\n\r\n/**\r\n  \\brief   Breakpoint\r\n  \\details Causes the processor to enter Debug state.\r\n           Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r\n  \\param [in]    value  is ignored by the processor.\r\n                 If required, a debugger can use it to store additional information about the breakpoint.\r\n */\r\n#define __BKPT(value)                       __breakpoint(value)\r\n\r\n\r\n/**\r\n  \\brief   Reverse bit order of value\r\n  \\details Reverses the bit order of the given value.\r\n  \\param [in]    value  Value to reverse\r\n  \\return               Reversed value\r\n */\r\n#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\r\n  #define __RBIT                          __rbit\r\n#else\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r\n{\r\n  uint32_t result;\r\n  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */\r\n\r\n  result = value;                      /* r will be reversed bits of v; first get LSB of v */\r\n  for (value >>= 1U; value; value >>= 1U)\r\n  {\r\n    result <<= 1U;\r\n    result |= value & 1U;\r\n    s--;\r\n  }\r\n  result <<= s;                        /* shift when v's highest bits are zero */\r\n  return(result);\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Count leading zeros\r\n  \\details Counts the number of leading zeros of a data value.\r\n  \\param [in]  value  Value to count the leading zeros\r\n  \\return             number of leading zeros in value\r\n */\r\n#define __CLZ                             __clz\r\n\r\n\r\n#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\r\n\r\n/**\r\n  \\brief   LDR Exclusive (8 bit)\r\n  \\details Executes a exclusive LDR instruction for 8 bit value.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return             value of type uint8_t at (*ptr)\r\n */\r\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r\n  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))\r\n#else\r\n  #define __LDREXB(ptr)          _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") ((uint8_t ) __ldrex(ptr))  _Pragma(\"pop\")\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   LDR Exclusive (16 bit)\r\n  \\details Executes a exclusive LDR instruction for 16 bit values.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return        value of type uint16_t at (*ptr)\r\n */\r\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r\n  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))\r\n#else\r\n  #define __LDREXH(ptr)          _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") ((uint16_t) __ldrex(ptr))  _Pragma(\"pop\")\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   LDR Exclusive (32 bit)\r\n  \\details Executes a exclusive LDR instruction for 32 bit values.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return        value of type uint32_t at (*ptr)\r\n */\r\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r\n  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))\r\n#else\r\n  #define __LDREXW(ptr)          _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") ((uint32_t ) __ldrex(ptr))  _Pragma(\"pop\")\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   STR Exclusive (8 bit)\r\n  \\details Executes a exclusive STR instruction for 8 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n  \\return          0  Function succeeded\r\n  \\return          1  Function failed\r\n */\r\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r\n  #define __STREXB(value, ptr)                                                 __strex(value, ptr)\r\n#else\r\n  #define __STREXB(value, ptr)   _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") __strex(value, ptr)        _Pragma(\"pop\")\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   STR Exclusive (16 bit)\r\n  \\details Executes a exclusive STR instruction for 16 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n  \\return          0  Function succeeded\r\n  \\return          1  Function failed\r\n */\r\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r\n  #define __STREXH(value, ptr)                                                 __strex(value, ptr)\r\n#else\r\n  #define __STREXH(value, ptr)   _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") __strex(value, ptr)        _Pragma(\"pop\")\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   STR Exclusive (32 bit)\r\n  \\details Executes a exclusive STR instruction for 32 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n  \\return          0  Function succeeded\r\n  \\return          1  Function failed\r\n */\r\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r\n  #define __STREXW(value, ptr)                                                 __strex(value, ptr)\r\n#else\r\n  #define __STREXW(value, ptr)   _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") __strex(value, ptr)        _Pragma(\"pop\")\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Remove the exclusive lock\r\n  \\details Removes the exclusive lock which is created by LDREX.\r\n */\r\n#define __CLREX                           __clrex\r\n\r\n\r\n/**\r\n  \\brief   Signed Saturate\r\n  \\details Saturates a signed value.\r\n  \\param [in]  value  Value to be saturated\r\n  \\param [in]    sat  Bit position to saturate to (1..32)\r\n  \\return             Saturated value\r\n */\r\n#define __SSAT                            __ssat\r\n\r\n\r\n/**\r\n  \\brief   Unsigned Saturate\r\n  \\details Saturates an unsigned value.\r\n  \\param [in]  value  Value to be saturated\r\n  \\param [in]    sat  Bit position to saturate to (0..31)\r\n  \\return             Saturated value\r\n */\r\n#define __USAT                            __usat\r\n\r\n\r\n/**\r\n  \\brief   Rotate Right with Extend (32 bit)\r\n  \\details Moves each bit of a bitstring right by one bit.\r\n           The carry input is shifted in at the left end of the bitstring.\r\n  \\param [in]    value  Value to rotate\r\n  \\return               Rotated value\r\n */\r\n#ifndef __NO_EMBEDDED_ASM\r\n__attribute__((section(\".rrx_text\"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)\r\n{\r\n  rrx r0, r0\r\n  bx lr\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   LDRT Unprivileged (8 bit)\r\n  \\details Executes a Unprivileged LDRT instruction for 8 bit value.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return             value of type uint8_t at (*ptr)\r\n */\r\n#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))\r\n\r\n\r\n/**\r\n  \\brief   LDRT Unprivileged (16 bit)\r\n  \\details Executes a Unprivileged LDRT instruction for 16 bit values.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return        value of type uint16_t at (*ptr)\r\n */\r\n#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))\r\n\r\n\r\n/**\r\n  \\brief   LDRT Unprivileged (32 bit)\r\n  \\details Executes a Unprivileged LDRT instruction for 32 bit values.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return        value of type uint32_t at (*ptr)\r\n */\r\n#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))\r\n\r\n\r\n/**\r\n  \\brief   STRT Unprivileged (8 bit)\r\n  \\details Executes a Unprivileged STRT instruction for 8 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n */\r\n#define __STRBT(value, ptr)               __strt(value, ptr)\r\n\r\n\r\n/**\r\n  \\brief   STRT Unprivileged (16 bit)\r\n  \\details Executes a Unprivileged STRT instruction for 16 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n */\r\n#define __STRHT(value, ptr)               __strt(value, ptr)\r\n\r\n\r\n/**\r\n  \\brief   STRT Unprivileged (32 bit)\r\n  \\details Executes a Unprivileged STRT instruction for 32 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n */\r\n#define __STRT(value, ptr)                __strt(value, ptr)\r\n\r\n#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */\r\n\r\n/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r\n\r\n\r\n/* ###################  Compiler specific Intrinsics  ########################### */\r\n/** \\defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r\n  Access to dedicated SIMD instructions\r\n  @{\r\n*/\r\n\r\n#if (__CORTEX_M >= 0x04U)  /* only for Cortex-M4 and above */\r\n\r\n#define __SADD8                           __sadd8\r\n#define __QADD8                           __qadd8\r\n#define __SHADD8                          __shadd8\r\n#define __UADD8                           __uadd8\r\n#define __UQADD8                          __uqadd8\r\n#define __UHADD8                          __uhadd8\r\n#define __SSUB8                           __ssub8\r\n#define __QSUB8                           __qsub8\r\n#define __SHSUB8                          __shsub8\r\n#define __USUB8                           __usub8\r\n#define __UQSUB8                          __uqsub8\r\n#define __UHSUB8                          __uhsub8\r\n#define __SADD16                          __sadd16\r\n#define __QADD16                          __qadd16\r\n#define __SHADD16                         __shadd16\r\n#define __UADD16                          __uadd16\r\n#define __UQADD16                         __uqadd16\r\n#define __UHADD16                         __uhadd16\r\n#define __SSUB16                          __ssub16\r\n#define __QSUB16                          __qsub16\r\n#define __SHSUB16                         __shsub16\r\n#define __USUB16                          __usub16\r\n#define __UQSUB16                         __uqsub16\r\n#define __UHSUB16                         __uhsub16\r\n#define __SASX                            __sasx\r\n#define __QASX                            __qasx\r\n#define __SHASX                           __shasx\r\n#define __UASX                            __uasx\r\n#define __UQASX                           __uqasx\r\n#define __UHASX                           __uhasx\r\n#define __SSAX                            __ssax\r\n#define __QSAX                            __qsax\r\n#define __SHSAX                           __shsax\r\n#define __USAX                            __usax\r\n#define __UQSAX                           __uqsax\r\n#define __UHSAX                           __uhsax\r\n#define __USAD8                           __usad8\r\n#define __USADA8                          __usada8\r\n#define __SSAT16                          __ssat16\r\n#define __USAT16                          __usat16\r\n#define __UXTB16                          __uxtb16\r\n#define __UXTAB16                         __uxtab16\r\n#define __SXTB16                          __sxtb16\r\n#define __SXTAB16                         __sxtab16\r\n#define __SMUAD                           __smuad\r\n#define __SMUADX                          __smuadx\r\n#define __SMLAD                           __smlad\r\n#define __SMLADX                          __smladx\r\n#define __SMLALD                          __smlald\r\n#define __SMLALDX                         __smlaldx\r\n#define __SMUSD                           __smusd\r\n#define __SMUSDX                          __smusdx\r\n#define __SMLSD                           __smlsd\r\n#define __SMLSDX                          __smlsdx\r\n#define __SMLSLD                          __smlsld\r\n#define __SMLSLDX                         __smlsldx\r\n#define __SEL                             __sel\r\n#define __QADD                            __qadd\r\n#define __QSUB                            __qsub\r\n\r\n#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \\\r\n                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )\r\n\r\n#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \\\r\n                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )\r\n\r\n#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \\\r\n                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))\r\n\r\n#endif /* (__CORTEX_M >= 0x04) */\r\n/*@} end of group CMSIS_SIMD_intrinsics */\r\n\r\n\r\n#endif /* __CMSIS_ARMCC_H */\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/include/cmsis_armcc_V6.h",
    "content": "/**************************************************************************//**\r\n * @file     cmsis_armcc_V6.h\r\n * @brief    CMSIS Cortex-M Core Function/Instruction Header File\r\n * @version  V4.30\r\n * @date     20. October 2015\r\n ******************************************************************************/\r\n/* Copyright (c) 2009 - 2015 ARM LIMITED\r\n\r\n   All rights reserved.\r\n   Redistribution and use in source and binary forms, with or without\r\n   modification, are permitted provided that the following conditions are met:\r\n   - Redistributions of source code must retain the above copyright\r\n     notice, this list of conditions and the following disclaimer.\r\n   - Redistributions in binary form must reproduce the above copyright\r\n     notice, this list of conditions and the following disclaimer in the\r\n     documentation and/or other materials provided with the distribution.\r\n   - Neither the name of ARM nor the names of its contributors may be used\r\n     to endorse or promote products derived from this software without\r\n     specific prior written permission.\r\n   *\r\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n   POSSIBILITY OF SUCH DAMAGE.\r\n   ---------------------------------------------------------------------------*/\r\n\r\n\r\n#ifndef __CMSIS_ARMCC_V6_H\r\n#define __CMSIS_ARMCC_V6_H\r\n\r\n\r\n/* ###########################  Core Function Access  ########################### */\r\n/** \\ingroup  CMSIS_Core_FunctionInterface\r\n    \\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief   Enable IRQ Interrupts\r\n  \\details Enables IRQ interrupts by clearing the I-bit in the CPSR.\r\n           Can only be executed in Privileged modes.\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)\r\n{\r\n  __ASM volatile (\"cpsie i\" : : : \"memory\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Disable IRQ Interrupts\r\n  \\details Disables IRQ interrupts by setting the I-bit in the CPSR.\r\n           Can only be executed in Privileged modes.\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)\r\n{\r\n  __ASM volatile (\"cpsid i\" : : : \"memory\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Control Register\r\n  \\details Returns the content of the Control Register.\r\n  \\return               Control Register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, control\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Get Control Register (non-secure)\r\n  \\details Returns the content of the non-secure Control Register when in secure mode.\r\n  \\return               non-secure Control Register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, control_ns\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Set Control Register\r\n  \\details Writes the given value to the Control Register.\r\n  \\param [in]    control  Control Register value to set\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)\r\n{\r\n  __ASM volatile (\"MSR control, %0\" : : \"r\" (control) : \"memory\");\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Set Control Register (non-secure)\r\n  \\details Writes the given value to the non-secure Control Register when in secure state.\r\n  \\param [in]    control  Control Register value to set\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)\r\n{\r\n  __ASM volatile (\"MSR control_ns, %0\" : : \"r\" (control) : \"memory\");\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Get IPSR Register\r\n  \\details Returns the content of the IPSR Register.\r\n  \\return               IPSR Register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, ipsr\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Get IPSR Register (non-secure)\r\n  \\details Returns the content of the non-secure IPSR Register when in secure state.\r\n  \\return               IPSR Register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, ipsr_ns\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Get APSR Register\r\n  \\details Returns the content of the APSR Register.\r\n  \\return               APSR Register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, apsr\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Get APSR Register (non-secure)\r\n  \\details Returns the content of the non-secure APSR Register when in secure state.\r\n  \\return               APSR Register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, apsr_ns\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Get xPSR Register\r\n  \\details Returns the content of the xPSR Register.\r\n  \\return               xPSR Register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, xpsr\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Get xPSR Register (non-secure)\r\n  \\details Returns the content of the non-secure xPSR Register when in secure state.\r\n  \\return               xPSR Register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, xpsr_ns\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Get Process Stack Pointer\r\n  \\details Returns the current value of the Process Stack Pointer (PSP).\r\n  \\return               PSP Register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)\r\n{\r\n  register uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, psp\"  : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Get Process Stack Pointer (non-secure)\r\n  \\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.\r\n  \\return               PSP Register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)\r\n{\r\n  register uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, psp_ns\"  : \"=r\" (result) );\r\n  return(result);\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Set Process Stack Pointer\r\n  \\details Assigns the given value to the Process Stack Pointer (PSP).\r\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r\n{\r\n  __ASM volatile (\"MSR psp, %0\" : : \"r\" (topOfProcStack) : \"sp\");\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Set Process Stack Pointer (non-secure)\r\n  \\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.\r\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)\r\n{\r\n  __ASM volatile (\"MSR psp_ns, %0\" : : \"r\" (topOfProcStack) : \"sp\");\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Get Main Stack Pointer\r\n  \\details Returns the current value of the Main Stack Pointer (MSP).\r\n  \\return               MSP Register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)\r\n{\r\n  register uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, msp\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Get Main Stack Pointer (non-secure)\r\n  \\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.\r\n  \\return               MSP Register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)\r\n{\r\n  register uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, msp_ns\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Set Main Stack Pointer\r\n  \\details Assigns the given value to the Main Stack Pointer (MSP).\r\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r\n{\r\n  __ASM volatile (\"MSR msp, %0\" : : \"r\" (topOfMainStack) : \"sp\");\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Set Main Stack Pointer (non-secure)\r\n  \\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.\r\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)\r\n{\r\n  __ASM volatile (\"MSR msp_ns, %0\" : : \"r\" (topOfMainStack) : \"sp\");\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Get Priority Mask\r\n  \\details Returns the current state of the priority mask bit from the Priority Mask Register.\r\n  \\return               Priority Mask value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, primask\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Get Priority Mask (non-secure)\r\n  \\details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.\r\n  \\return               Priority Mask value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, primask_ns\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Set Priority Mask\r\n  \\details Assigns the given value to the Priority Mask Register.\r\n  \\param [in]    priMask  Priority Mask\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r\n{\r\n  __ASM volatile (\"MSR primask, %0\" : : \"r\" (priMask) : \"memory\");\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Set Priority Mask (non-secure)\r\n  \\details Assigns the given value to the non-secure Priority Mask Register when in secure state.\r\n  \\param [in]    priMask  Priority Mask\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)\r\n{\r\n  __ASM volatile (\"MSR primask_ns, %0\" : : \"r\" (priMask) : \"memory\");\r\n}\r\n#endif\r\n\r\n\r\n#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U))  /* ToDo:  ARMCC_V6: check if this is ok for cortex >=3 */\r\n\r\n/**\r\n  \\brief   Enable FIQ\r\n  \\details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r\n           Can only be executed in Privileged modes.\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)\r\n{\r\n  __ASM volatile (\"cpsie f\" : : : \"memory\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Disable FIQ\r\n  \\details Disables FIQ interrupts by setting the F-bit in the CPSR.\r\n           Can only be executed in Privileged modes.\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)\r\n{\r\n  __ASM volatile (\"cpsid f\" : : : \"memory\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Base Priority\r\n  \\details Returns the current value of the Base Priority register.\r\n  \\return               Base Priority register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, basepri\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Get Base Priority (non-secure)\r\n  \\details Returns the current value of the non-secure Base Priority register when in secure state.\r\n  \\return               Base Priority register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, basepri_ns\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Set Base Priority\r\n  \\details Assigns the given value to the Base Priority register.\r\n  \\param [in]    basePri  Base Priority value to set\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value)\r\n{\r\n  __ASM volatile (\"MSR basepri, %0\" : : \"r\" (value) : \"memory\");\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Set Base Priority (non-secure)\r\n  \\details Assigns the given value to the non-secure Base Priority register when in secure state.\r\n  \\param [in]    basePri  Base Priority value to set\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value)\r\n{\r\n  __ASM volatile (\"MSR basepri_ns, %0\" : : \"r\" (value) : \"memory\");\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Set Base Priority with condition\r\n  \\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r\n           or the new value increases the BASEPRI priority level.\r\n  \\param [in]    basePri  Base Priority value to set\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)\r\n{\r\n  __ASM volatile (\"MSR basepri_max, %0\" : : \"r\" (value) : \"memory\");\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Set Base Priority with condition (non_secure)\r\n  \\details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled,\r\n\t       or the new value increases the BASEPRI priority level.\r\n  \\param [in]    basePri  Base Priority value to set\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value)\r\n{\r\n  __ASM volatile (\"MSR basepri_max_ns, %0\" : : \"r\" (value) : \"memory\");\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Get Fault Mask\r\n  \\details Returns the current value of the Fault Mask register.\r\n  \\return               Fault Mask register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, faultmask\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Get Fault Mask (non-secure)\r\n  \\details Returns the current value of the non-secure Fault Mask register when in secure state.\r\n  \\return               Fault Mask register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, faultmask_ns\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Set Fault Mask\r\n  \\details Assigns the given value to the Fault Mask register.\r\n  \\param [in]    faultMask  Fault Mask value to set\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r\n{\r\n  __ASM volatile (\"MSR faultmask, %0\" : : \"r\" (faultMask) : \"memory\");\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Set Fault Mask (non-secure)\r\n  \\details Assigns the given value to the non-secure Fault Mask register when in secure state.\r\n  \\param [in]    faultMask  Fault Mask value to set\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)\r\n{\r\n  __ASM volatile (\"MSR faultmask_ns, %0\" : : \"r\" (faultMask) : \"memory\");\r\n}\r\n#endif\r\n\r\n\r\n#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */\r\n\r\n\r\n#if (__ARM_ARCH_8M__ == 1U)\r\n\r\n/**\r\n  \\brief   Get Process Stack Pointer Limit\r\n  \\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).\r\n  \\return               PSPLIM Register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)\r\n{\r\n  register uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, psplim\"  : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M')     /* ToDo:  ARMCC_V6: check predefined macro for mainline */\r\n/**\r\n  \\brief   Get Process Stack Pointer Limit (non-secure)\r\n  \\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\r\n  \\return               PSPLIM Register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)\r\n{\r\n  register uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, psplim_ns\"  : \"=r\" (result) );\r\n  return(result);\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Set Process Stack Pointer Limit\r\n  \\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).\r\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)\r\n{\r\n  __ASM volatile (\"MSR psplim, %0\" : : \"r\" (ProcStackPtrLimit));\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M')     /* ToDo:  ARMCC_V6: check predefined macro for mainline */\r\n/**\r\n  \\brief   Set Process Stack Pointer (non-secure)\r\n  \\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\r\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)\r\n{\r\n  __ASM volatile (\"MSR psplim_ns, %0\\n\" : : \"r\" (ProcStackPtrLimit));\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Get Main Stack Pointer Limit\r\n  \\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).\r\n  \\return               MSPLIM Register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)\r\n{\r\n  register uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, msplim\" : \"=r\" (result) );\r\n\r\n  return(result);\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M')     /* ToDo:  ARMCC_V6: check predefined macro for mainline */\r\n/**\r\n  \\brief   Get Main Stack Pointer Limit (non-secure)\r\n  \\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.\r\n  \\return               MSPLIM Register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)\r\n{\r\n  register uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, msplim_ns\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Set Main Stack Pointer Limit\r\n  \\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).\r\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)\r\n{\r\n  __ASM volatile (\"MSR msplim, %0\" : : \"r\" (MainStackPtrLimit));\r\n}\r\n\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M')     /* ToDo:  ARMCC_V6: check predefined macro for mainline */\r\n/**\r\n  \\brief   Set Main Stack Pointer Limit (non-secure)\r\n  \\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.\r\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer value to set\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)\r\n{\r\n  __ASM volatile (\"MSR msplim_ns, %0\" : : \"r\" (MainStackPtrLimit));\r\n}\r\n#endif\r\n\r\n#endif /* (__ARM_ARCH_8M__ == 1U) */\r\n\r\n\r\n#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U))  /* ToDo:  ARMCC_V6: check if this is ok for cortex >=4 */\r\n\r\n/**\r\n  \\brief   Get FPSCR\r\n  \\details eturns the current value of the Floating Point Status/Control register.\r\n  \\return               Floating Point Status/Control register value\r\n */\r\n#define __get_FPSCR      __builtin_arm_get_fpscr\r\n#if 0\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)\r\n{\r\n#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"\");                                 /* Empty asm statement works as a scheduling barrier */\r\n  __ASM volatile (\"VMRS %0, fpscr\" : \"=r\" (result) );\r\n  __ASM volatile (\"\");\r\n  return(result);\r\n#else\r\n   return(0);\r\n#endif\r\n}\r\n#endif\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Get FPSCR (non-secure)\r\n  \\details Returns the current value of the non-secure Floating Point Status/Control register when in secure state.\r\n  \\return               Floating Point Status/Control register value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void)\r\n{\r\n#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"\");                                 /* Empty asm statement works as a scheduling barrier */\r\n  __ASM volatile (\"VMRS %0, fpscr_ns\" : \"=r\" (result) );\r\n  __ASM volatile (\"\");\r\n  return(result);\r\n#else\r\n   return(0);\r\n#endif\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Set FPSCR\r\n  \\details Assigns the given value to the Floating Point Status/Control register.\r\n  \\param [in]    fpscr  Floating Point Status/Control value to set\r\n */\r\n#define __set_FPSCR      __builtin_arm_set_fpscr\r\n#if 0\r\n__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r\n{\r\n#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r\n  __ASM volatile (\"\");                                 /* Empty asm statement works as a scheduling barrier */\r\n  __ASM volatile (\"VMSR fpscr, %0\" : : \"r\" (fpscr) : \"vfpcc\");\r\n  __ASM volatile (\"\");\r\n#endif\r\n}\r\n#endif\r\n\r\n#if  (__ARM_FEATURE_CMSE == 3U)\r\n/**\r\n  \\brief   Set FPSCR (non-secure)\r\n  \\details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state.\r\n  \\param [in]    fpscr  Floating Point Status/Control value to set\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr)\r\n{\r\n#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r\n  __ASM volatile (\"\");                                 /* Empty asm statement works as a scheduling barrier */\r\n  __ASM volatile (\"VMSR fpscr_ns, %0\" : : \"r\" (fpscr) : \"vfpcc\");\r\n  __ASM volatile (\"\");\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */\r\n\r\n\r\n\r\n/*@} end of CMSIS_Core_RegAccFunctions */\r\n\r\n\r\n/* ##########################  Core Instruction Access  ######################### */\r\n/** \\defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r\n  Access to dedicated instructions\r\n  @{\r\n*/\r\n\r\n/* Define macros for porting to both thumb1 and thumb2.\r\n * For thumb1, use low register (r0-r7), specified by constraint \"l\"\r\n * Otherwise, use general registers, specified by constraint \"r\" */\r\n#if defined (__thumb__) && !defined (__thumb2__)\r\n#define __CMSIS_GCC_OUT_REG(r) \"=l\" (r)\r\n#define __CMSIS_GCC_USE_REG(r) \"l\" (r)\r\n#else\r\n#define __CMSIS_GCC_OUT_REG(r) \"=r\" (r)\r\n#define __CMSIS_GCC_USE_REG(r) \"r\" (r)\r\n#endif\r\n\r\n/**\r\n  \\brief   No Operation\r\n  \\details No Operation does nothing. This instruction can be used for code alignment purposes.\r\n */\r\n#define __NOP          __builtin_arm_nop\r\n\r\n/**\r\n  \\brief   Wait For Interrupt\r\n  \\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r\n */\r\n#define __WFI          __builtin_arm_wfi\r\n\r\n\r\n/**\r\n  \\brief   Wait For Event\r\n  \\details Wait For Event is a hint instruction that permits the processor to enter\r\n           a low-power state until one of a number of events occurs.\r\n */\r\n#define __WFE          __builtin_arm_wfe\r\n\r\n\r\n/**\r\n  \\brief   Send Event\r\n  \\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r\n */\r\n#define __SEV          __builtin_arm_sev\r\n\r\n\r\n/**\r\n  \\brief   Instruction Synchronization Barrier\r\n  \\details Instruction Synchronization Barrier flushes the pipeline in the processor,\r\n           so that all instructions following the ISB are fetched from cache or memory,\r\n           after the instruction has been completed.\r\n */\r\n#define __ISB()        __builtin_arm_isb(0xF);\r\n\r\n/**\r\n  \\brief   Data Synchronization Barrier\r\n  \\details Acts as a special kind of Data Memory Barrier.\r\n           It completes when all explicit memory accesses before this instruction complete.\r\n */\r\n#define __DSB()        __builtin_arm_dsb(0xF);\r\n\r\n\r\n/**\r\n  \\brief   Data Memory Barrier\r\n  \\details Ensures the apparent order of the explicit memory operations before\r\n           and after the instruction, without ensuring their completion.\r\n */\r\n#define __DMB()        __builtin_arm_dmb(0xF);\r\n\r\n\r\n/**\r\n  \\brief   Reverse byte order (32 bit)\r\n  \\details Reverses the byte order in integer value.\r\n  \\param [in]    value  Value to reverse\r\n  \\return               Reversed value\r\n */\r\n#define __REV          __builtin_bswap32\r\n\r\n\r\n/**\r\n  \\brief   Reverse byte order (16 bit)\r\n  \\details Reverses the byte order in two unsigned short values.\r\n  \\param [in]    value  Value to reverse\r\n  \\return               Reversed value\r\n */\r\n#define __REV16          __builtin_bswap16                           /* ToDo:  ARMCC_V6: check if __builtin_bswap16 could be used */\r\n#if 0\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"rev16 %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r\n  return(result);\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Reverse byte order in signed short value\r\n  \\details Reverses the byte order in a signed short value with sign extension to integer.\r\n  \\param [in]    value  Value to reverse\r\n  \\return               Reversed value\r\n */\r\n                                                          /* ToDo:  ARMCC_V6: check if __builtin_bswap16 could be used */\r\n__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)\r\n{\r\n  int32_t result;\r\n\r\n  __ASM volatile (\"revsh %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r\n  return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Rotate Right in unsigned value (32 bit)\r\n  \\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r\n  \\param [in]    op1  Value to rotate\r\n  \\param [in]    op2  Number of Bits to rotate\r\n  \\return               Rotated value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r\n{\r\n  return (op1 >> op2) | (op1 << (32U - op2));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Breakpoint\r\n  \\details Causes the processor to enter Debug state.\r\n            Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r\n    \\param [in]    value  is ignored by the processor.\r\n                   If required, a debugger can use it to store additional information about the breakpoint.\r\n */\r\n#define __BKPT(value)                       __ASM volatile (\"bkpt \"#value)\r\n\r\n\r\n/**\r\n  \\brief   Reverse bit order of value\r\n  \\details Reverses the bit order of the given value.\r\n  \\param [in]    value  Value to reverse\r\n  \\return               Reversed value\r\n */\r\n                                                          /* ToDo:  ARMCC_V6: check if __builtin_arm_rbit is supported */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r\n{\r\n  uint32_t result;\r\n\r\n#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U))  /* ToDo:  ARMCC_V6: check if this is ok for cortex >=3 */\r\n   __ASM volatile (\"rbit %0, %1\" : \"=r\" (result) : \"r\" (value) );\r\n#else\r\n  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */\r\n\r\n  result = value;                      /* r will be reversed bits of v; first get LSB of v */\r\n  for (value >>= 1U; value; value >>= 1U)\r\n  {\r\n    result <<= 1U;\r\n    result |= value & 1U;\r\n    s--;\r\n  }\r\n  result <<= s;                        /* shift when v's highest bits are zero */\r\n#endif\r\n  return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Count leading zeros\r\n  \\details Counts the number of leading zeros of a data value.\r\n  \\param [in]  value  Value to count the leading zeros\r\n  \\return             number of leading zeros in value\r\n */\r\n#define __CLZ             __builtin_clz\r\n\r\n\r\n#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U))  /* ToDo:  ARMCC_V6: check if this is ok for cortex >=3 */\r\n\r\n/**\r\n  \\brief   LDR Exclusive (8 bit)\r\n  \\details Executes a exclusive LDR instruction for 8 bit value.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return             value of type uint8_t at (*ptr)\r\n */\r\n#define __LDREXB        (uint8_t)__builtin_arm_ldrex\r\n\r\n\r\n/**\r\n  \\brief   LDR Exclusive (16 bit)\r\n  \\details Executes a exclusive LDR instruction for 16 bit values.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return        value of type uint16_t at (*ptr)\r\n */\r\n#define __LDREXH        (uint16_t)__builtin_arm_ldrex\r\n\r\n\r\n/**\r\n  \\brief   LDR Exclusive (32 bit)\r\n  \\details Executes a exclusive LDR instruction for 32 bit values.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return        value of type uint32_t at (*ptr)\r\n */\r\n#define __LDREXW        (uint32_t)__builtin_arm_ldrex\r\n\r\n\r\n/**\r\n  \\brief   STR Exclusive (8 bit)\r\n  \\details Executes a exclusive STR instruction for 8 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n  \\return          0  Function succeeded\r\n  \\return          1  Function failed\r\n */\r\n#define __STREXB        (uint32_t)__builtin_arm_strex\r\n\r\n\r\n/**\r\n  \\brief   STR Exclusive (16 bit)\r\n  \\details Executes a exclusive STR instruction for 16 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n  \\return          0  Function succeeded\r\n  \\return          1  Function failed\r\n */\r\n#define __STREXH        (uint32_t)__builtin_arm_strex\r\n\r\n\r\n/**\r\n  \\brief   STR Exclusive (32 bit)\r\n  \\details Executes a exclusive STR instruction for 32 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n  \\return          0  Function succeeded\r\n  \\return          1  Function failed\r\n */\r\n#define __STREXW        (uint32_t)__builtin_arm_strex\r\n\r\n\r\n/**\r\n  \\brief   Remove the exclusive lock\r\n  \\details Removes the exclusive lock which is created by LDREX.\r\n */\r\n#define __CLREX             __builtin_arm_clrex\r\n\r\n\r\n/**\r\n  \\brief   Signed Saturate\r\n  \\details Saturates a signed value.\r\n  \\param [in]  value  Value to be saturated\r\n  \\param [in]    sat  Bit position to saturate to (1..32)\r\n  \\return             Saturated value\r\n */\r\n/*#define __SSAT             __builtin_arm_ssat*/\r\n#define __SSAT(ARG1,ARG2) \\\r\n({                          \\\r\n  int32_t __RES, __ARG1 = (ARG1); \\\r\n  __ASM (\"ssat %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\r\n  __RES; \\\r\n })\r\n\r\n\r\n/**\r\n  \\brief   Unsigned Saturate\r\n  \\details Saturates an unsigned value.\r\n  \\param [in]  value  Value to be saturated\r\n  \\param [in]    sat  Bit position to saturate to (0..31)\r\n  \\return             Saturated value\r\n */\r\n#define __USAT             __builtin_arm_usat\r\n#if 0\r\n#define __USAT(ARG1,ARG2) \\\r\n({                          \\\r\n  uint32_t __RES, __ARG1 = (ARG1); \\\r\n  __ASM (\"usat %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\r\n  __RES; \\\r\n })\r\n#endif\r\n\r\n\r\n/**\r\n  \\brief   Rotate Right with Extend (32 bit)\r\n  \\details Moves each bit of a bitstring right by one bit.\r\n           The carry input is shifted in at the left end of the bitstring.\r\n  \\param [in]    value  Value to rotate\r\n  \\return               Rotated value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"rrx %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r\n  return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   LDRT Unprivileged (8 bit)\r\n  \\details Executes a Unprivileged LDRT instruction for 8 bit value.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return             value of type uint8_t at (*ptr)\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)\r\n{\r\n    uint32_t result;\r\n\r\n   __ASM volatile (\"ldrbt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\r\n   return ((uint8_t) result);    /* Add explicit type cast here */\r\n}\r\n\r\n\r\n/**\r\n  \\brief   LDRT Unprivileged (16 bit)\r\n  \\details Executes a Unprivileged LDRT instruction for 16 bit values.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return        value of type uint16_t at (*ptr)\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)\r\n{\r\n    uint32_t result;\r\n\r\n   __ASM volatile (\"ldrht %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\r\n   return ((uint16_t) result);    /* Add explicit type cast here */\r\n}\r\n\r\n\r\n/**\r\n  \\brief   LDRT Unprivileged (32 bit)\r\n  \\details Executes a Unprivileged LDRT instruction for 32 bit values.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return        value of type uint32_t at (*ptr)\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)\r\n{\r\n    uint32_t result;\r\n\r\n   __ASM volatile (\"ldrt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\r\n   return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   STRT Unprivileged (8 bit)\r\n  \\details Executes a Unprivileged STRT instruction for 8 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\r\n{\r\n   __ASM volatile (\"strbt %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\r\n}\r\n\r\n\r\n/**\r\n  \\brief   STRT Unprivileged (16 bit)\r\n  \\details Executes a Unprivileged STRT instruction for 16 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\r\n{\r\n   __ASM volatile (\"strht %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\r\n}\r\n\r\n\r\n/**\r\n  \\brief   STRT Unprivileged (32 bit)\r\n  \\details Executes a Unprivileged STRT instruction for 32 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\r\n{\r\n   __ASM volatile (\"strt %1, %0\" : \"=Q\" (*ptr) : \"r\" (value) );\r\n}\r\n\r\n#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */\r\n\r\n\r\n#if (__ARM_ARCH_8M__ == 1U)\r\n\r\n/**\r\n  \\brief   Load-Acquire (8 bit)\r\n  \\details Executes a LDAB instruction for 8 bit value.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return             value of type uint8_t at (*ptr)\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)\r\n{\r\n    uint32_t result;\r\n\r\n   __ASM volatile (\"ldab %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\r\n   return ((uint8_t) result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Load-Acquire (16 bit)\r\n  \\details Executes a LDAH instruction for 16 bit values.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return        value of type uint16_t at (*ptr)\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)\r\n{\r\n    uint32_t result;\r\n\r\n   __ASM volatile (\"ldah %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\r\n   return ((uint16_t) result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Load-Acquire (32 bit)\r\n  \\details Executes a LDA instruction for 32 bit values.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return        value of type uint32_t at (*ptr)\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)\r\n{\r\n    uint32_t result;\r\n\r\n   __ASM volatile (\"lda %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\r\n   return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Store-Release (8 bit)\r\n  \\details Executes a STLB instruction for 8 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)\r\n{\r\n   __ASM volatile (\"stlb %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Store-Release (16 bit)\r\n  \\details Executes a STLH instruction for 16 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)\r\n{\r\n   __ASM volatile (\"stlh %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Store-Release (32 bit)\r\n  \\details Executes a STL instruction for 32 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)\r\n{\r\n   __ASM volatile (\"stl %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Load-Acquire Exclusive (8 bit)\r\n  \\details Executes a LDAB exclusive instruction for 8 bit value.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return             value of type uint8_t at (*ptr)\r\n */\r\n#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex\r\n\r\n\r\n/**\r\n  \\brief   Load-Acquire Exclusive (16 bit)\r\n  \\details Executes a LDAH exclusive instruction for 16 bit values.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return        value of type uint16_t at (*ptr)\r\n */\r\n#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex\r\n\r\n\r\n/**\r\n  \\brief   Load-Acquire Exclusive (32 bit)\r\n  \\details Executes a LDA exclusive instruction for 32 bit values.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return        value of type uint32_t at (*ptr)\r\n */\r\n#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex\r\n\r\n\r\n/**\r\n  \\brief   Store-Release Exclusive (8 bit)\r\n  \\details Executes a STLB exclusive instruction for 8 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n  \\return          0  Function succeeded\r\n  \\return          1  Function failed\r\n */\r\n#define     __STLEXB                 (uint32_t)__builtin_arm_stlex\r\n\r\n\r\n/**\r\n  \\brief   Store-Release Exclusive (16 bit)\r\n  \\details Executes a STLH exclusive instruction for 16 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n  \\return          0  Function succeeded\r\n  \\return          1  Function failed\r\n */\r\n#define     __STLEXH                 (uint32_t)__builtin_arm_stlex\r\n\r\n\r\n/**\r\n  \\brief   Store-Release Exclusive (32 bit)\r\n  \\details Executes a STL exclusive instruction for 32 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n  \\return          0  Function succeeded\r\n  \\return          1  Function failed\r\n */\r\n#define     __STLEX                  (uint32_t)__builtin_arm_stlex\r\n\r\n#endif /* (__ARM_ARCH_8M__ == 1U) */\r\n\r\n/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r\n\r\n\r\n/* ###################  Compiler specific Intrinsics  ########################### */\r\n/** \\defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r\n  Access to dedicated SIMD instructions\r\n  @{\r\n*/\r\n\r\n#if (__ARM_FEATURE_DSP == 1U)        /* ToDo:  ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"sadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"qadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"shadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uqadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uhadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"ssub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"qsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"shsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"usub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uqsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uhsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"sadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"qadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"shadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uqadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uhadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"ssub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"qsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"shsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"usub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uqsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uhsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"sasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"qasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"shasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uqasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uhasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"ssax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"qsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"shsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"usax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uqsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uhsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"usad8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"usada8 %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\r\n  return(result);\r\n}\r\n\r\n#define __SSAT16(ARG1,ARG2) \\\r\n({                          \\\r\n  uint32_t __RES, __ARG1 = (ARG1); \\\r\n  __ASM (\"ssat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\r\n  __RES; \\\r\n })\r\n\r\n#define __USAT16(ARG1,ARG2) \\\r\n({                          \\\r\n  uint32_t __RES, __ARG1 = (ARG1); \\\r\n  __ASM (\"usat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\r\n  __RES; \\\r\n })\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"sxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"sxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"smuad %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"smuadx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"smlad %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"smladx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\r\n{\r\n  union llreg_u{\r\n    uint32_t w32[2];\r\n    uint64_t w64;\r\n  } llr;\r\n  llr.w64 = acc;\r\n\r\n#ifndef __ARMEB__   /* Little endian */\r\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\r\n#else               /* Big endian */\r\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\r\n#endif\r\n\r\n  return(llr.w64);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\r\n{\r\n  union llreg_u{\r\n    uint32_t w32[2];\r\n    uint64_t w64;\r\n  } llr;\r\n  llr.w64 = acc;\r\n\r\n#ifndef __ARMEB__   /* Little endian */\r\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\r\n#else               /* Big endian */\r\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\r\n#endif\r\n\r\n  return(llr.w64);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"smusd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"smusdx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"smlsd %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"smlsdx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\r\n{\r\n  union llreg_u{\r\n    uint32_t w32[2];\r\n    uint64_t w64;\r\n  } llr;\r\n  llr.w64 = acc;\r\n\r\n#ifndef __ARMEB__   /* Little endian */\r\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\r\n#else               /* Big endian */\r\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\r\n#endif\r\n\r\n  return(llr.w64);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\r\n{\r\n  union llreg_u{\r\n    uint32_t w32[2];\r\n    uint64_t w64;\r\n  } llr;\r\n  llr.w64 = acc;\r\n\r\n#ifndef __ARMEB__   /* Little endian */\r\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\r\n#else               /* Big endian */\r\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\r\n#endif\r\n\r\n  return(llr.w64);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"sel %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE  int32_t __QADD( int32_t op1,  int32_t op2)\r\n{\r\n  int32_t result;\r\n\r\n  __ASM volatile (\"qadd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE  int32_t __QSUB( int32_t op1,  int32_t op2)\r\n{\r\n  int32_t result;\r\n\r\n  __ASM volatile (\"qsub %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n#define __PKHBT(ARG1,ARG2,ARG3) \\\r\n({                          \\\r\n  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\\r\n  __ASM (\"pkhbt %0, %1, %2, lsl %3\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2), \"I\" (ARG3)  ); \\\r\n  __RES; \\\r\n })\r\n\r\n#define __PKHTB(ARG1,ARG2,ARG3) \\\r\n({                          \\\r\n  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\\r\n  if (ARG3 == 0) \\\r\n    __ASM (\"pkhtb %0, %1, %2\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2)  ); \\\r\n  else \\\r\n    __ASM (\"pkhtb %0, %1, %2, asr %3\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2), \"I\" (ARG3)  ); \\\r\n  __RES; \\\r\n })\r\n\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\r\n{\r\n int32_t result;\r\n\r\n __ASM volatile (\"smmla %0, %1, %2, %3\" : \"=r\" (result): \"r\"  (op1), \"r\" (op2), \"r\" (op3) );\r\n return(result);\r\n}\r\n\r\n#endif /* (__ARM_FEATURE_DSP == 1U) */\r\n/*@} end of group CMSIS_SIMD_intrinsics */\r\n\r\n\r\n#endif /* __CMSIS_ARMCC_V6_H */\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/include/cmsis_gcc.h",
    "content": "/**************************************************************************//**\r\n * @file     cmsis_gcc.h\r\n * @brief    CMSIS Cortex-M Core Function/Instruction Header File\r\n * @version  V4.30\r\n * @date     20. October 2015\r\n ******************************************************************************/\r\n/* Copyright (c) 2009 - 2015 ARM LIMITED\r\n\r\n   All rights reserved.\r\n   Redistribution and use in source and binary forms, with or without\r\n   modification, are permitted provided that the following conditions are met:\r\n   - Redistributions of source code must retain the above copyright\r\n     notice, this list of conditions and the following disclaimer.\r\n   - Redistributions in binary form must reproduce the above copyright\r\n     notice, this list of conditions and the following disclaimer in the\r\n     documentation and/or other materials provided with the distribution.\r\n   - Neither the name of ARM nor the names of its contributors may be used\r\n     to endorse or promote products derived from this software without\r\n     specific prior written permission.\r\n   *\r\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n   POSSIBILITY OF SUCH DAMAGE.\r\n   ---------------------------------------------------------------------------*/\r\n\r\n\r\n#ifndef __CMSIS_GCC_H\r\n#define __CMSIS_GCC_H\r\n\r\n/* ignore some GCC warnings */\r\n#if defined ( __GNUC__ )\r\n#pragma GCC diagnostic push\r\n#pragma GCC diagnostic ignored \"-Wsign-conversion\"\r\n#pragma GCC diagnostic ignored \"-Wconversion\"\r\n#pragma GCC diagnostic ignored \"-Wunused-parameter\"\r\n#endif\r\n\r\n\r\n/* ###########################  Core Function Access  ########################### */\r\n/** \\ingroup  CMSIS_Core_FunctionInterface\r\n    \\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief   Enable IRQ Interrupts\r\n  \\details Enables IRQ interrupts by clearing the I-bit in the CPSR.\r\n           Can only be executed in Privileged modes.\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)\r\n{\r\n  __ASM volatile (\"cpsie i\" : : : \"memory\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Disable IRQ Interrupts\r\n  \\details Disables IRQ interrupts by setting the I-bit in the CPSR.\r\n  Can only be executed in Privileged modes.\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)\r\n{\r\n  __ASM volatile (\"cpsid i\" : : : \"memory\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Control Register\r\n  \\details Returns the content of the Control Register.\r\n  \\return               Control Register value\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, control\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Control Register\r\n  \\details Writes the given value to the Control Register.\r\n  \\param [in]    control  Control Register value to set\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)\r\n{\r\n  __ASM volatile (\"MSR control, %0\" : : \"r\" (control) : \"memory\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get IPSR Register\r\n  \\details Returns the content of the IPSR Register.\r\n  \\return               IPSR Register value\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, ipsr\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get APSR Register\r\n  \\details Returns the content of the APSR Register.\r\n  \\return               APSR Register value\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, apsr\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get xPSR Register\r\n  \\details Returns the content of the xPSR Register.\r\n\r\n    \\return               xPSR Register value\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, xpsr\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Process Stack Pointer\r\n  \\details Returns the current value of the Process Stack Pointer (PSP).\r\n  \\return               PSP Register value\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)\r\n{\r\n  register uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, psp\\n\"  : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Process Stack Pointer\r\n  \\details Assigns the given value to the Process Stack Pointer (PSP).\r\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r\n{\r\n  __ASM volatile (\"MSR psp, %0\\n\" : : \"r\" (topOfProcStack) : \"sp\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Main Stack Pointer\r\n  \\details Returns the current value of the Main Stack Pointer (MSP).\r\n  \\return               MSP Register value\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)\r\n{\r\n  register uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, msp\\n\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Main Stack Pointer\r\n  \\details Assigns the given value to the Main Stack Pointer (MSP).\r\n\r\n    \\param [in]    topOfMainStack  Main Stack Pointer value to set\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r\n{\r\n  __ASM volatile (\"MSR msp, %0\\n\" : : \"r\" (topOfMainStack) : \"sp\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Priority Mask\r\n  \\details Returns the current state of the priority mask bit from the Priority Mask Register.\r\n  \\return               Priority Mask value\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, primask\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Priority Mask\r\n  \\details Assigns the given value to the Priority Mask Register.\r\n  \\param [in]    priMask  Priority Mask\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r\n{\r\n  __ASM volatile (\"MSR primask, %0\" : : \"r\" (priMask) : \"memory\");\r\n}\r\n\r\n\r\n#if       (__CORTEX_M >= 0x03U)\r\n\r\n/**\r\n  \\brief   Enable FIQ\r\n  \\details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r\n           Can only be executed in Privileged modes.\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)\r\n{\r\n  __ASM volatile (\"cpsie f\" : : : \"memory\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Disable FIQ\r\n  \\details Disables FIQ interrupts by setting the F-bit in the CPSR.\r\n           Can only be executed in Privileged modes.\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)\r\n{\r\n  __ASM volatile (\"cpsid f\" : : : \"memory\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Base Priority\r\n  \\details Returns the current value of the Base Priority register.\r\n  \\return               Base Priority register value\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, basepri\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Base Priority\r\n  \\details Assigns the given value to the Base Priority register.\r\n  \\param [in]    basePri  Base Priority value to set\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)\r\n{\r\n  __ASM volatile (\"MSR basepri, %0\" : : \"r\" (value) : \"memory\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Base Priority with condition\r\n  \\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r\n           or the new value increases the BASEPRI priority level.\r\n  \\param [in]    basePri  Base Priority value to set\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)\r\n{\r\n  __ASM volatile (\"MSR basepri_max, %0\" : : \"r\" (value) : \"memory\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Fault Mask\r\n  \\details Returns the current value of the Fault Mask register.\r\n  \\return               Fault Mask register value\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"MRS %0, faultmask\" : \"=r\" (result) );\r\n  return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Fault Mask\r\n  \\details Assigns the given value to the Fault Mask register.\r\n  \\param [in]    faultMask  Fault Mask value to set\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r\n{\r\n  __ASM volatile (\"MSR faultmask, %0\" : : \"r\" (faultMask) : \"memory\");\r\n}\r\n\r\n#endif /* (__CORTEX_M >= 0x03U) */\r\n\r\n\r\n#if       (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)\r\n\r\n/**\r\n  \\brief   Get FPSCR\r\n  \\details Returns the current value of the Floating Point Status/Control register.\r\n  \\return               Floating Point Status/Control register value\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)\r\n{\r\n#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r\n  uint32_t result;\r\n\r\n  /* Empty asm statement works as a scheduling barrier */\r\n  __ASM volatile (\"\");\r\n  __ASM volatile (\"VMRS %0, fpscr\" : \"=r\" (result) );\r\n  __ASM volatile (\"\");\r\n  return(result);\r\n#else\r\n   return(0);\r\n#endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set FPSCR\r\n  \\details Assigns the given value to the Floating Point Status/Control register.\r\n  \\param [in]    fpscr  Floating Point Status/Control value to set\r\n */\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r\n{\r\n#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r\n  /* Empty asm statement works as a scheduling barrier */\r\n  __ASM volatile (\"\");\r\n  __ASM volatile (\"VMSR fpscr, %0\" : : \"r\" (fpscr) : \"vfpcc\");\r\n  __ASM volatile (\"\");\r\n#endif\r\n}\r\n\r\n#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */\r\n\r\n\r\n\r\n/*@} end of CMSIS_Core_RegAccFunctions */\r\n\r\n\r\n/* ##########################  Core Instruction Access  ######################### */\r\n/** \\defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r\n  Access to dedicated instructions\r\n  @{\r\n*/\r\n\r\n/* Define macros for porting to both thumb1 and thumb2.\r\n * For thumb1, use low register (r0-r7), specified by constraint \"l\"\r\n * Otherwise, use general registers, specified by constraint \"r\" */\r\n#if defined (__thumb__) && !defined (__thumb2__)\r\n#define __CMSIS_GCC_OUT_REG(r) \"=l\" (r)\r\n#define __CMSIS_GCC_USE_REG(r) \"l\" (r)\r\n#else\r\n#define __CMSIS_GCC_OUT_REG(r) \"=r\" (r)\r\n#define __CMSIS_GCC_USE_REG(r) \"r\" (r)\r\n#endif\r\n\r\n/**\r\n  \\brief   No Operation\r\n  \\details No Operation does nothing. This instruction can be used for code alignment purposes.\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)\r\n{\r\n  __ASM volatile (\"nop\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Wait For Interrupt\r\n  \\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)\r\n{\r\n  __ASM volatile (\"wfi\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Wait For Event\r\n  \\details Wait For Event is a hint instruction that permits the processor to enter\r\n    a low-power state until one of a number of events occurs.\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)\r\n{\r\n  __ASM volatile (\"wfe\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Send Event\r\n  \\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)\r\n{\r\n  __ASM volatile (\"sev\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Instruction Synchronization Barrier\r\n  \\details Instruction Synchronization Barrier flushes the pipeline in the processor,\r\n           so that all instructions following the ISB are fetched from cache or memory,\r\n           after the instruction has been completed.\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)\r\n{\r\n  __ASM volatile (\"isb 0xF\":::\"memory\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Data Synchronization Barrier\r\n  \\details Acts as a special kind of Data Memory Barrier.\r\n           It completes when all explicit memory accesses before this instruction complete.\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)\r\n{\r\n  __ASM volatile (\"dsb 0xF\":::\"memory\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Data Memory Barrier\r\n  \\details Ensures the apparent order of the explicit memory operations before\r\n           and after the instruction, without ensuring their completion.\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)\r\n{\r\n  __ASM volatile (\"dmb 0xF\":::\"memory\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Reverse byte order (32 bit)\r\n  \\details Reverses the byte order in integer value.\r\n  \\param [in]    value  Value to reverse\r\n  \\return               Reversed value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)\r\n{\r\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\r\n  return __builtin_bswap32(value);\r\n#else\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"rev %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r\n  return(result);\r\n#endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Reverse byte order (16 bit)\r\n  \\details Reverses the byte order in two unsigned short values.\r\n  \\param [in]    value  Value to reverse\r\n  \\return               Reversed value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"rev16 %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r\n  return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Reverse byte order in signed short value\r\n  \\details Reverses the byte order in a signed short value with sign extension to integer.\r\n  \\param [in]    value  Value to reverse\r\n  \\return               Reversed value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)\r\n{\r\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r\n  return (short)__builtin_bswap16(value);\r\n#else\r\n  int32_t result;\r\n\r\n  __ASM volatile (\"revsh %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r\n  return(result);\r\n#endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Rotate Right in unsigned value (32 bit)\r\n  \\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r\n  \\param [in]    value  Value to rotate\r\n  \\param [in]    value  Number of Bits to rotate\r\n  \\return               Rotated value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r\n{\r\n  return (op1 >> op2) | (op1 << (32U - op2));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Breakpoint\r\n  \\details Causes the processor to enter Debug state.\r\n           Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r\n  \\param [in]    value  is ignored by the processor.\r\n                 If required, a debugger can use it to store additional information about the breakpoint.\r\n */\r\n#define __BKPT(value)                       __ASM volatile (\"bkpt \"#value)\r\n\r\n\r\n/**\r\n  \\brief   Reverse bit order of value\r\n  \\details Reverses the bit order of the given value.\r\n  \\param [in]    value  Value to reverse\r\n  \\return               Reversed value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r\n{\r\n  uint32_t result;\r\n\r\n#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\r\n   __ASM volatile (\"rbit %0, %1\" : \"=r\" (result) : \"r\" (value) );\r\n#else\r\n  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */\r\n\r\n  result = value;                      /* r will be reversed bits of v; first get LSB of v */\r\n  for (value >>= 1U; value; value >>= 1U)\r\n  {\r\n    result <<= 1U;\r\n    result |= value & 1U;\r\n    s--;\r\n  }\r\n  result <<= s;                        /* shift when v's highest bits are zero */\r\n#endif\r\n  return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Count leading zeros\r\n  \\details Counts the number of leading zeros of a data value.\r\n  \\param [in]  value  Value to count the leading zeros\r\n  \\return             number of leading zeros in value\r\n */\r\n#define __CLZ             __builtin_clz\r\n\r\n\r\n#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\r\n\r\n/**\r\n  \\brief   LDR Exclusive (8 bit)\r\n  \\details Executes a exclusive LDR instruction for 8 bit value.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return             value of type uint8_t at (*ptr)\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)\r\n{\r\n    uint32_t result;\r\n\r\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r\n   __ASM volatile (\"ldrexb %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\r\n#else\r\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\r\n       accepted by assembler. So has to use following less efficient pattern.\r\n    */\r\n   __ASM volatile (\"ldrexb %0, [%1]\" : \"=r\" (result) : \"r\" (addr) : \"memory\" );\r\n#endif\r\n   return ((uint8_t) result);    /* Add explicit type cast here */\r\n}\r\n\r\n\r\n/**\r\n  \\brief   LDR Exclusive (16 bit)\r\n  \\details Executes a exclusive LDR instruction for 16 bit values.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return        value of type uint16_t at (*ptr)\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)\r\n{\r\n    uint32_t result;\r\n\r\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r\n   __ASM volatile (\"ldrexh %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\r\n#else\r\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\r\n       accepted by assembler. So has to use following less efficient pattern.\r\n    */\r\n   __ASM volatile (\"ldrexh %0, [%1]\" : \"=r\" (result) : \"r\" (addr) : \"memory\" );\r\n#endif\r\n   return ((uint16_t) result);    /* Add explicit type cast here */\r\n}\r\n\r\n\r\n/**\r\n  \\brief   LDR Exclusive (32 bit)\r\n  \\details Executes a exclusive LDR instruction for 32 bit values.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return        value of type uint32_t at (*ptr)\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)\r\n{\r\n    uint32_t result;\r\n\r\n   __ASM volatile (\"ldrex %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\r\n   return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   STR Exclusive (8 bit)\r\n  \\details Executes a exclusive STR instruction for 8 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n  \\return          0  Function succeeded\r\n  \\return          1  Function failed\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r\n{\r\n   uint32_t result;\r\n\r\n   __ASM volatile (\"strexb %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*addr) : \"r\" ((uint32_t)value) );\r\n   return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   STR Exclusive (16 bit)\r\n  \\details Executes a exclusive STR instruction for 16 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n  \\return          0  Function succeeded\r\n  \\return          1  Function failed\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r\n{\r\n   uint32_t result;\r\n\r\n   __ASM volatile (\"strexh %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*addr) : \"r\" ((uint32_t)value) );\r\n   return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   STR Exclusive (32 bit)\r\n  \\details Executes a exclusive STR instruction for 32 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n  \\return          0  Function succeeded\r\n  \\return          1  Function failed\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r\n{\r\n   uint32_t result;\r\n\r\n   __ASM volatile (\"strex %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*addr) : \"r\" (value) );\r\n   return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Remove the exclusive lock\r\n  \\details Removes the exclusive lock which is created by LDREX.\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)\r\n{\r\n  __ASM volatile (\"clrex\" ::: \"memory\");\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Signed Saturate\r\n  \\details Saturates a signed value.\r\n  \\param [in]  value  Value to be saturated\r\n  \\param [in]    sat  Bit position to saturate to (1..32)\r\n  \\return             Saturated value\r\n */\r\n#define __SSAT(ARG1,ARG2) \\\r\n({                          \\\r\n  uint32_t __RES, __ARG1 = (ARG1); \\\r\n  __ASM (\"ssat %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\r\n  __RES; \\\r\n })\r\n\r\n\r\n/**\r\n  \\brief   Unsigned Saturate\r\n  \\details Saturates an unsigned value.\r\n  \\param [in]  value  Value to be saturated\r\n  \\param [in]    sat  Bit position to saturate to (0..31)\r\n  \\return             Saturated value\r\n */\r\n#define __USAT(ARG1,ARG2) \\\r\n({                          \\\r\n  uint32_t __RES, __ARG1 = (ARG1); \\\r\n  __ASM (\"usat %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\r\n  __RES; \\\r\n })\r\n\r\n\r\n/**\r\n  \\brief   Rotate Right with Extend (32 bit)\r\n  \\details Moves each bit of a bitstring right by one bit.\r\n           The carry input is shifted in at the left end of the bitstring.\r\n  \\param [in]    value  Value to rotate\r\n  \\return               Rotated value\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"rrx %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r\n  return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   LDRT Unprivileged (8 bit)\r\n  \\details Executes a Unprivileged LDRT instruction for 8 bit value.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return             value of type uint8_t at (*ptr)\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)\r\n{\r\n    uint32_t result;\r\n\r\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r\n   __ASM volatile (\"ldrbt %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\r\n#else\r\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\r\n       accepted by assembler. So has to use following less efficient pattern.\r\n    */\r\n   __ASM volatile (\"ldrbt %0, [%1]\" : \"=r\" (result) : \"r\" (addr) : \"memory\" );\r\n#endif\r\n   return ((uint8_t) result);    /* Add explicit type cast here */\r\n}\r\n\r\n\r\n/**\r\n  \\brief   LDRT Unprivileged (16 bit)\r\n  \\details Executes a Unprivileged LDRT instruction for 16 bit values.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return        value of type uint16_t at (*ptr)\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)\r\n{\r\n    uint32_t result;\r\n\r\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r\n   __ASM volatile (\"ldrht %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\r\n#else\r\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\r\n       accepted by assembler. So has to use following less efficient pattern.\r\n    */\r\n   __ASM volatile (\"ldrht %0, [%1]\" : \"=r\" (result) : \"r\" (addr) : \"memory\" );\r\n#endif\r\n   return ((uint16_t) result);    /* Add explicit type cast here */\r\n}\r\n\r\n\r\n/**\r\n  \\brief   LDRT Unprivileged (32 bit)\r\n  \\details Executes a Unprivileged LDRT instruction for 32 bit values.\r\n  \\param [in]    ptr  Pointer to data\r\n  \\return        value of type uint32_t at (*ptr)\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)\r\n{\r\n    uint32_t result;\r\n\r\n   __ASM volatile (\"ldrt %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\r\n   return(result);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   STRT Unprivileged (8 bit)\r\n  \\details Executes a Unprivileged STRT instruction for 8 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)\r\n{\r\n   __ASM volatile (\"strbt %1, %0\" : \"=Q\" (*addr) : \"r\" ((uint32_t)value) );\r\n}\r\n\r\n\r\n/**\r\n  \\brief   STRT Unprivileged (16 bit)\r\n  \\details Executes a Unprivileged STRT instruction for 16 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)\r\n{\r\n   __ASM volatile (\"strht %1, %0\" : \"=Q\" (*addr) : \"r\" ((uint32_t)value) );\r\n}\r\n\r\n\r\n/**\r\n  \\brief   STRT Unprivileged (32 bit)\r\n  \\details Executes a Unprivileged STRT instruction for 32 bit values.\r\n  \\param [in]  value  Value to store\r\n  \\param [in]    ptr  Pointer to location\r\n */\r\n__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)\r\n{\r\n   __ASM volatile (\"strt %1, %0\" : \"=Q\" (*addr) : \"r\" (value) );\r\n}\r\n\r\n#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */\r\n\r\n/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r\n\r\n\r\n/* ###################  Compiler specific Intrinsics  ########################### */\r\n/** \\defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r\n  Access to dedicated SIMD instructions\r\n  @{\r\n*/\r\n\r\n#if (__CORTEX_M >= 0x04U)  /* only for Cortex-M4 and above */\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"sadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"qadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"shadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uqadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uhadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"ssub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"qsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"shsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"usub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uqsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uhsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"sadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"qadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"shadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uqadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uhadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"ssub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"qsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"shsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"usub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uqsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uhsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"sasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"qasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"shasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uqasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uhasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"ssax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"qsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"shsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"usax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uqsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uhsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"usad8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"usada8 %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\r\n  return(result);\r\n}\r\n\r\n#define __SSAT16(ARG1,ARG2) \\\r\n({                          \\\r\n  int32_t __RES, __ARG1 = (ARG1); \\\r\n  __ASM (\"ssat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\r\n  __RES; \\\r\n })\r\n\r\n#define __USAT16(ARG1,ARG2) \\\r\n({                          \\\r\n  uint32_t __RES, __ARG1 = (ARG1); \\\r\n  __ASM (\"usat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\r\n  __RES; \\\r\n })\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"uxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"sxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"sxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"smuad %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"smuadx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"smlad %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"smladx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\r\n{\r\n  union llreg_u{\r\n    uint32_t w32[2];\r\n    uint64_t w64;\r\n  } llr;\r\n  llr.w64 = acc;\r\n\r\n#ifndef __ARMEB__   /* Little endian */\r\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\r\n#else               /* Big endian */\r\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\r\n#endif\r\n\r\n  return(llr.w64);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\r\n{\r\n  union llreg_u{\r\n    uint32_t w32[2];\r\n    uint64_t w64;\r\n  } llr;\r\n  llr.w64 = acc;\r\n\r\n#ifndef __ARMEB__   /* Little endian */\r\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\r\n#else               /* Big endian */\r\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\r\n#endif\r\n\r\n  return(llr.w64);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"smusd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"smusdx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"smlsd %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"smlsdx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\r\n{\r\n  union llreg_u{\r\n    uint32_t w32[2];\r\n    uint64_t w64;\r\n  } llr;\r\n  llr.w64 = acc;\r\n\r\n#ifndef __ARMEB__   /* Little endian */\r\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\r\n#else               /* Big endian */\r\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\r\n#endif\r\n\r\n  return(llr.w64);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\r\n{\r\n  union llreg_u{\r\n    uint32_t w32[2];\r\n    uint64_t w64;\r\n  } llr;\r\n  llr.w64 = acc;\r\n\r\n#ifndef __ARMEB__   /* Little endian */\r\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\r\n#else               /* Big endian */\r\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\r\n#endif\r\n\r\n  return(llr.w64);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)\r\n{\r\n  uint32_t result;\r\n\r\n  __ASM volatile (\"sel %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE  int32_t __QADD( int32_t op1,  int32_t op2)\r\n{\r\n  int32_t result;\r\n\r\n  __ASM volatile (\"qadd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE  int32_t __QSUB( int32_t op1,  int32_t op2)\r\n{\r\n  int32_t result;\r\n\r\n  __ASM volatile (\"qsub %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\r\n  return(result);\r\n}\r\n\r\n#define __PKHBT(ARG1,ARG2,ARG3) \\\r\n({                          \\\r\n  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\\r\n  __ASM (\"pkhbt %0, %1, %2, lsl %3\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2), \"I\" (ARG3)  ); \\\r\n  __RES; \\\r\n })\r\n\r\n#define __PKHTB(ARG1,ARG2,ARG3) \\\r\n({                          \\\r\n  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\\r\n  if (ARG3 == 0) \\\r\n    __ASM (\"pkhtb %0, %1, %2\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2)  ); \\\r\n  else \\\r\n    __ASM (\"pkhtb %0, %1, %2, asr %3\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2), \"I\" (ARG3)  ); \\\r\n  __RES; \\\r\n })\r\n\r\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\r\n{\r\n int32_t result;\r\n\r\n __ASM volatile (\"smmla %0, %1, %2, %3\" : \"=r\" (result): \"r\"  (op1), \"r\" (op2), \"r\" (op3) );\r\n return(result);\r\n}\r\n\r\n#endif /* (__CORTEX_M >= 0x04) */\r\n/*@} end of group CMSIS_SIMD_intrinsics */\r\n\r\n\r\n#if defined ( __GNUC__ )\r\n#pragma GCC diagnostic pop\r\n#endif\r\n\r\n#endif /* __CMSIS_GCC_H */\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/include/core_cm0.h",
    "content": "/**************************************************************************//**\r\n * @file     core_cm0.h\r\n * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File\r\n * @version  V4.30\r\n * @date     20. October 2015\r\n ******************************************************************************/\r\n/* Copyright (c) 2009 - 2015 ARM LIMITED\r\n\r\n   All rights reserved.\r\n   Redistribution and use in source and binary forms, with or without\r\n   modification, are permitted provided that the following conditions are met:\r\n   - Redistributions of source code must retain the above copyright\r\n     notice, this list of conditions and the following disclaimer.\r\n   - Redistributions in binary form must reproduce the above copyright\r\n     notice, this list of conditions and the following disclaimer in the\r\n     documentation and/or other materials provided with the distribution.\r\n   - Neither the name of ARM nor the names of its contributors may be used\r\n     to endorse or promote products derived from this software without\r\n     specific prior written permission.\r\n   *\r\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n   POSSIBILITY OF SUCH DAMAGE.\r\n   ---------------------------------------------------------------------------*/\r\n\r\n\r\n#if   defined ( __ICCARM__ )\r\n #pragma system_include         /* treat file as system include file for MISRA check */\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #pragma clang system_header   /* treat file as system include file */\r\n#endif\r\n\r\n#ifndef __CORE_CM0_H_GENERIC\r\n#define __CORE_CM0_H_GENERIC\r\n\r\n#include <stdint.h>\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/**\r\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r\n  CMSIS violates the following MISRA-C:2004 rules:\r\n\r\n   \\li Required Rule 8.5, object/function definition in header file.<br>\r\n     Function definitions in header files are used to allow 'inlining'.\r\n\r\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r\n     Unions are used for effective representation of core registers.\r\n\r\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\r\n     Function-like macros are used to allow more efficient code.\r\n */\r\n\r\n\r\n/*******************************************************************************\r\n *                 CMSIS definitions\r\n ******************************************************************************/\r\n/**\r\n  \\ingroup Cortex_M0\r\n  @{\r\n */\r\n\r\n/*  CMSIS CM0 definitions */\r\n#define __CM0_CMSIS_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CMSIS HAL main version */\r\n#define __CM0_CMSIS_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CMSIS HAL sub version */\r\n#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \\\r\n                                    __CM0_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL version number */\r\n\r\n#define __CORTEX_M                (0x00U)                                      /*!< Cortex-M Core */\r\n\r\n\r\n#if   defined ( __CC_ARM )\r\n  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */\r\n  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */\r\n  #define __STATIC_INLINE  static __inline\r\n\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */\r\n  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */\r\n  #define __STATIC_INLINE  static __inline\r\n\r\n#elif defined ( __GNUC__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __ICCARM__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __TMS470__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __TASKING__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __CSMC__ )\r\n  #define __packed\r\n  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */\r\n  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#else\r\n  #error Unknown compiler\r\n#endif\r\n\r\n/** __FPU_USED indicates whether an FPU is used or not.\r\n    This core does not support an FPU at all\r\n*/\r\n#define __FPU_USED       0U\r\n\r\n#if defined ( __CC_ARM )\r\n  #if defined __TARGET_FPU_VFP\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #if defined __ARM_PCS_VFP\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __GNUC__ )\r\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __ICCARM__ )\r\n  #if defined __ARMVFP__\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __TMS470__ )\r\n  #if defined __TI_VFP_SUPPORT__\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __TASKING__ )\r\n  #if defined __FPU_VFP__\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __CSMC__ )\r\n  #if ( __CSMC__ & 0x400U)\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#endif\r\n\r\n#include \"core_cmInstr.h\"                /* Core Instruction Access */\r\n#include \"core_cmFunc.h\"                 /* Core Function Access */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __CORE_CM0_H_GENERIC */\r\n\r\n#ifndef __CMSIS_GENERIC\r\n\r\n#ifndef __CORE_CM0_H_DEPENDANT\r\n#define __CORE_CM0_H_DEPENDANT\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* check device defines and use defaults */\r\n#if defined __CHECK_DEVICE_DEFINES\r\n  #ifndef __CM0_REV\r\n    #define __CM0_REV               0x0000U\r\n    #warning \"__CM0_REV not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __NVIC_PRIO_BITS\r\n    #define __NVIC_PRIO_BITS          2U\r\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __Vendor_SysTickConfig\r\n    #define __Vendor_SysTickConfig    0U\r\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\r\n  #endif\r\n#endif\r\n\r\n/* IO definitions (access restrictions to peripheral registers) */\r\n/**\r\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\r\n\r\n    <strong>IO Type Qualifiers</strong> are used\r\n    \\li to specify the access to peripheral variables.\r\n    \\li for automatic generation of peripheral register debug information.\r\n*/\r\n#ifdef __cplusplus\r\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\r\n#else\r\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r\n#endif\r\n#define     __O     volatile             /*!< Defines 'write only' permissions */\r\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r\n\r\n/* following defines should be used for structure members */\r\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r\n\r\n/*@} end of group Cortex_M0 */\r\n\r\n\r\n\r\n/*******************************************************************************\r\n *                 Register Abstraction\r\n  Core Register contain:\r\n  - Core Register\r\n  - Core NVIC Register\r\n  - Core SCB Register\r\n  - Core SysTick Register\r\n ******************************************************************************/\r\n/**\r\n  \\defgroup CMSIS_core_register Defines and Type Definitions\r\n  \\brief Type definitions and defines for Cortex-M processor based devices.\r\n*/\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_CORE  Status and Control Registers\r\n  \\brief      Core Register type definitions.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Union type to access the Application Program Status Register (APSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\r\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} APSR_Type;\r\n\r\n/* APSR Register Definitions */\r\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r\n\r\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r\n\r\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r\n\r\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} IPSR_Type;\r\n\r\n/* IPSR Register Definitions */\r\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\r\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\r\n    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\r\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} xPSR_Type;\r\n\r\n/* xPSR Register Definitions */\r\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r\n\r\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r\n\r\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r\n\r\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r\n\r\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r\n\r\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Control Registers (CONTROL).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */\r\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\r\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} CONTROL_Type;\r\n\r\n/* CONTROL Register Definitions */\r\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r\n\r\n/*@} end of group CMSIS_CORE */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r\n  \\brief      Type definitions for the NVIC Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r\n        uint32_t RESERVED0[31U];\r\n  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r\n        uint32_t RSERVED1[31U];\r\n  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r\n        uint32_t RESERVED2[31U];\r\n  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r\n        uint32_t RESERVED3[31U];\r\n        uint32_t RESERVED4[64U];\r\n  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\r\n}  NVIC_Type;\r\n\r\n/*@} end of group CMSIS_NVIC */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\r\n  \\brief    Type definitions for the System Control Block Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Control Block (SCB).\r\n */\r\ntypedef struct\r\n{\r\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r\n        uint32_t RESERVED0;\r\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r\n        uint32_t RESERVED1;\r\n  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\r\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r\n} SCB_Type;\r\n\r\n/* SCB CPUID Register Definitions */\r\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r\n\r\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r\n\r\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r\n\r\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r\n\r\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r\n\r\n/* SCB Interrupt Control State Register Definitions */\r\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\r\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\r\n\r\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r\n\r\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r\n\r\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r\n\r\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r\n\r\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r\n\r\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r\n\r\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r\n\r\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r\n\r\n/* SCB Application Interrupt and Reset Control Register Definitions */\r\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r\n\r\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r\n\r\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r\n\r\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r\n\r\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r\n\r\n/* SCB System Control Register Definitions */\r\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r\n\r\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r\n\r\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r\n\r\n/* SCB Configuration Control Register Definitions */\r\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\r\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\r\n\r\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r\n\r\n/* SCB System Handler Control and State Register Definitions */\r\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r\n\r\n/*@} end of group CMSIS_SCB */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r\n  \\brief    Type definitions for the System Timer Registers.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Timer (SysTick).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r\n} SysTick_Type;\r\n\r\n/* SysTick Control / Status Register Definitions */\r\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r\n\r\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r\n\r\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r\n\r\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r\n\r\n/* SysTick Reload Register Definitions */\r\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r\n\r\n/* SysTick Current Register Definitions */\r\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r\n\r\n/* SysTick Calibration Register Definitions */\r\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r\n\r\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r\n\r\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r\n\r\n/*@} end of group CMSIS_SysTick */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r\n  \\brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\r\n            Therefore they are not covered by the Cortex-M0 header file.\r\n  @{\r\n */\r\n/*@} end of group CMSIS_CoreDebug */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\r\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief   Mask and shift a bit field value for use in a register bit range.\r\n  \\param[in] field  Name of the register bit field.\r\n  \\param[in] value  Value of the bit field.\r\n  \\return           Masked and shifted value.\r\n*/\r\n#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)\r\n\r\n/**\r\n  \\brief     Mask and shift a register value to extract a bit filed value.\r\n  \\param[in] field  Name of the register bit field.\r\n  \\param[in] value  Value of register.\r\n  \\return           Masked and shifted bit field value.\r\n*/\r\n#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)\r\n\r\n/*@} end of group CMSIS_core_bitfield */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_core_base     Core Definitions\r\n  \\brief      Definitions for base addresses, unions, and structures.\r\n  @{\r\n */\r\n\r\n/* Memory mapping of Cortex-M0 Hardware */\r\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\r\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\r\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\r\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\r\n\r\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\r\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\r\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\r\n\r\n\r\n/*@} */\r\n\r\n\r\n\r\n/*******************************************************************************\r\n *                Hardware Abstraction Layer\r\n  Core Function Interface contains:\r\n  - Core NVIC Functions\r\n  - Core SysTick Functions\r\n  - Core Register Access Functions\r\n ******************************************************************************/\r\n/**\r\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r\n*/\r\n\r\n\r\n\r\n/* ##########################   NVIC functions  #################################### */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\r\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\r\n  @{\r\n */\r\n\r\n/* Interrupt Priorities are WORD accessible only under ARMv6M                   */\r\n/* The following MACROS handle generation of the register offset and byte masks */\r\n#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\r\n#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\r\n#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\r\n\r\n\r\n/**\r\n  \\brief   Enable External Interrupt\r\n  \\details Enables a device-specific interrupt in the NVIC interrupt controller.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Disable External Interrupt\r\n  \\details Disables a device-specific interrupt in the NVIC interrupt controller.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Pending Interrupt\r\n  \\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\return             0  Interrupt status is not pending.\r\n  \\return             1  Interrupt status is pending.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Pending Interrupt\r\n  \\details Sets the pending bit of an external interrupt.\r\n  \\param [in]      IRQn  Interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Clear Pending Interrupt\r\n  \\details Clears the pending bit of an external interrupt.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Interrupt Priority\r\n  \\details Sets the priority of an interrupt.\r\n  \\note    The priority cannot be set for every core interrupt.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\param [in]  priority  Priority to set.\r\n */\r\n__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r\n{\r\n  if ((int32_t)(IRQn) < 0)\r\n  {\r\n    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r\n  }\r\n  else\r\n  {\r\n    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Interrupt Priority\r\n  \\details Reads the priority of an interrupt.\r\n           The interrupt number can be positive to specify an external (device specific) interrupt,\r\n           or negative to specify an internal (core) interrupt.\r\n  \\param [in]   IRQn  Interrupt number.\r\n  \\return             Interrupt Priority.\r\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r\n{\r\n\r\n  if ((int32_t)(IRQn) < 0)\r\n  {\r\n    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r\n  }\r\n  else\r\n  {\r\n    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   System Reset\r\n  \\details Initiates a system reset request to reset the MCU.\r\n */\r\n__STATIC_INLINE void NVIC_SystemReset(void)\r\n{\r\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\r\n                                                                       buffered write are completed before reset */\r\n  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r\n                 SCB_AIRCR_SYSRESETREQ_Msk);\r\n  __DSB();                                                          /* Ensure completion of memory access */\r\n\r\n  for(;;)                                                           /* wait until reset */\r\n  {\r\n    __NOP();\r\n  }\r\n}\r\n\r\n/*@} end of CMSIS_Core_NVICFunctions */\r\n\r\n\r\n\r\n/* ##################################    SysTick function  ############################################ */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r\n  \\brief    Functions that configure the System.\r\n  @{\r\n */\r\n\r\n#if (__Vendor_SysTickConfig == 0U)\r\n\r\n/**\r\n  \\brief   System Tick Configuration\r\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r\n           Counter is in free running mode to generate periodic interrupts.\r\n  \\param [in]  ticks  Number of ticks between two interrupts.\r\n  \\return          0  Function succeeded.\r\n  \\return          1  Function failed.\r\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r\n           must contain a vendor-specific implementation of this function.\r\n */\r\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r\n{\r\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r\n  {\r\n    return (1UL);                                                   /* Reload value impossible */\r\n  }\r\n\r\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r\n                   SysTick_CTRL_TICKINT_Msk   |\r\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r\n  return (0UL);                                                     /* Function successful */\r\n}\r\n\r\n#endif\r\n\r\n/*@} end of CMSIS_Core_SysTickFunctions */\r\n\r\n\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __CORE_CM0_H_DEPENDANT */\r\n\r\n#endif /* __CMSIS_GENERIC */\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/include/core_cm0plus.h",
    "content": "/**************************************************************************//**\r\n * @file     core_cm0plus.h\r\n * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File\r\n * @version  V4.30\r\n * @date     20. October 2015\r\n ******************************************************************************/\r\n/* Copyright (c) 2009 - 2015 ARM LIMITED\r\n\r\n   All rights reserved.\r\n   Redistribution and use in source and binary forms, with or without\r\n   modification, are permitted provided that the following conditions are met:\r\n   - Redistributions of source code must retain the above copyright\r\n     notice, this list of conditions and the following disclaimer.\r\n   - Redistributions in binary form must reproduce the above copyright\r\n     notice, this list of conditions and the following disclaimer in the\r\n     documentation and/or other materials provided with the distribution.\r\n   - Neither the name of ARM nor the names of its contributors may be used\r\n     to endorse or promote products derived from this software without\r\n     specific prior written permission.\r\n   *\r\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n   POSSIBILITY OF SUCH DAMAGE.\r\n   ---------------------------------------------------------------------------*/\r\n\r\n\r\n#if   defined ( __ICCARM__ )\r\n #pragma system_include         /* treat file as system include file for MISRA check */\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #pragma clang system_header   /* treat file as system include file */\r\n#endif\r\n\r\n#ifndef __CORE_CM0PLUS_H_GENERIC\r\n#define __CORE_CM0PLUS_H_GENERIC\r\n\r\n#include <stdint.h>\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/**\r\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r\n  CMSIS violates the following MISRA-C:2004 rules:\r\n\r\n   \\li Required Rule 8.5, object/function definition in header file.<br>\r\n     Function definitions in header files are used to allow 'inlining'.\r\n\r\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r\n     Unions are used for effective representation of core registers.\r\n\r\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\r\n     Function-like macros are used to allow more efficient code.\r\n */\r\n\r\n\r\n/*******************************************************************************\r\n *                 CMSIS definitions\r\n ******************************************************************************/\r\n/**\r\n  \\ingroup Cortex-M0+\r\n  @{\r\n */\r\n\r\n/*  CMSIS CM0+ definitions */\r\n#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U)                                   /*!< [31:16] CMSIS HAL main version */\r\n#define __CM0PLUS_CMSIS_VERSION_SUB  (0x1EU)                                   /*!< [15:0]  CMSIS HAL sub version */\r\n#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \\\r\n                                       __CM0PLUS_CMSIS_VERSION_SUB           ) /*!< CMSIS HAL version number */\r\n\r\n#define __CORTEX_M                (0x00U)                                      /*!< Cortex-M Core */\r\n\r\n\r\n#if   defined ( __CC_ARM )\r\n  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */\r\n  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */\r\n  #define __STATIC_INLINE  static __inline\r\n\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */\r\n  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */\r\n  #define __STATIC_INLINE  static __inline\r\n\r\n#elif defined ( __GNUC__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __ICCARM__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __TMS470__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __TASKING__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __CSMC__ )\r\n  #define __packed\r\n  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */\r\n  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#else\r\n  #error Unknown compiler\r\n#endif\r\n\r\n/** __FPU_USED indicates whether an FPU is used or not.\r\n    This core does not support an FPU at all\r\n*/\r\n#define __FPU_USED       0U\r\n\r\n#if defined ( __CC_ARM )\r\n  #if defined __TARGET_FPU_VFP\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #if defined __ARM_PCS_VFP\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __GNUC__ )\r\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __ICCARM__ )\r\n  #if defined __ARMVFP__\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __TMS470__ )\r\n  #if defined __TI_VFP_SUPPORT__\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __TASKING__ )\r\n  #if defined __FPU_VFP__\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __CSMC__ )\r\n  #if ( __CSMC__ & 0x400U)\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#endif\r\n\r\n#include \"core_cmInstr.h\"                /* Core Instruction Access */\r\n#include \"core_cmFunc.h\"                 /* Core Function Access */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __CORE_CM0PLUS_H_GENERIC */\r\n\r\n#ifndef __CMSIS_GENERIC\r\n\r\n#ifndef __CORE_CM0PLUS_H_DEPENDANT\r\n#define __CORE_CM0PLUS_H_DEPENDANT\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* check device defines and use defaults */\r\n#if defined __CHECK_DEVICE_DEFINES\r\n  #ifndef __CM0PLUS_REV\r\n    #define __CM0PLUS_REV             0x0000U\r\n    #warning \"__CM0PLUS_REV not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __MPU_PRESENT\r\n    #define __MPU_PRESENT             0U\r\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __VTOR_PRESENT\r\n    #define __VTOR_PRESENT            0U\r\n    #warning \"__VTOR_PRESENT not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __NVIC_PRIO_BITS\r\n    #define __NVIC_PRIO_BITS          2U\r\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __Vendor_SysTickConfig\r\n    #define __Vendor_SysTickConfig    0U\r\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\r\n  #endif\r\n#endif\r\n\r\n/* IO definitions (access restrictions to peripheral registers) */\r\n/**\r\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\r\n\r\n    <strong>IO Type Qualifiers</strong> are used\r\n    \\li to specify the access to peripheral variables.\r\n    \\li for automatic generation of peripheral register debug information.\r\n*/\r\n#ifdef __cplusplus\r\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\r\n#else\r\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r\n#endif\r\n#define     __O     volatile             /*!< Defines 'write only' permissions */\r\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r\n\r\n/* following defines should be used for structure members */\r\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r\n\r\n/*@} end of group Cortex-M0+ */\r\n\r\n\r\n\r\n/*******************************************************************************\r\n *                 Register Abstraction\r\n  Core Register contain:\r\n  - Core Register\r\n  - Core NVIC Register\r\n  - Core SCB Register\r\n  - Core SysTick Register\r\n  - Core MPU Register\r\n ******************************************************************************/\r\n/**\r\n  \\defgroup CMSIS_core_register Defines and Type Definitions\r\n  \\brief Type definitions and defines for Cortex-M processor based devices.\r\n*/\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_CORE  Status and Control Registers\r\n  \\brief      Core Register type definitions.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Union type to access the Application Program Status Register (APSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\r\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} APSR_Type;\r\n\r\n/* APSR Register Definitions */\r\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r\n\r\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r\n\r\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r\n\r\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} IPSR_Type;\r\n\r\n/* IPSR Register Definitions */\r\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\r\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\r\n    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\r\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} xPSR_Type;\r\n\r\n/* xPSR Register Definitions */\r\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r\n\r\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r\n\r\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r\n\r\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r\n\r\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r\n\r\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Control Registers (CONTROL).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\r\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\r\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} CONTROL_Type;\r\n\r\n/* CONTROL Register Definitions */\r\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r\n\r\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\r\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\r\n\r\n/*@} end of group CMSIS_CORE */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r\n  \\brief      Type definitions for the NVIC Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r\n        uint32_t RESERVED0[31U];\r\n  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r\n        uint32_t RSERVED1[31U];\r\n  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r\n        uint32_t RESERVED2[31U];\r\n  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r\n        uint32_t RESERVED3[31U];\r\n        uint32_t RESERVED4[64U];\r\n  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\r\n}  NVIC_Type;\r\n\r\n/*@} end of group CMSIS_NVIC */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\r\n  \\brief    Type definitions for the System Control Block Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Control Block (SCB).\r\n */\r\ntypedef struct\r\n{\r\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r\n#if (__VTOR_PRESENT == 1U)\r\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\r\n#else\r\n        uint32_t RESERVED0;\r\n#endif\r\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r\n        uint32_t RESERVED1;\r\n  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\r\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r\n} SCB_Type;\r\n\r\n/* SCB CPUID Register Definitions */\r\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r\n\r\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r\n\r\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r\n\r\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r\n\r\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r\n\r\n/* SCB Interrupt Control State Register Definitions */\r\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\r\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\r\n\r\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r\n\r\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r\n\r\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r\n\r\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r\n\r\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r\n\r\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r\n\r\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r\n\r\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r\n\r\n#if (__VTOR_PRESENT == 1U)\r\n/* SCB Interrupt Control State Register Definitions */\r\n#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */\r\n#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */\r\n#endif\r\n\r\n/* SCB Application Interrupt and Reset Control Register Definitions */\r\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r\n\r\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r\n\r\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r\n\r\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r\n\r\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r\n\r\n/* SCB System Control Register Definitions */\r\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r\n\r\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r\n\r\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r\n\r\n/* SCB Configuration Control Register Definitions */\r\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\r\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\r\n\r\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r\n\r\n/* SCB System Handler Control and State Register Definitions */\r\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r\n\r\n/*@} end of group CMSIS_SCB */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r\n  \\brief    Type definitions for the System Timer Registers.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Timer (SysTick).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r\n} SysTick_Type;\r\n\r\n/* SysTick Control / Status Register Definitions */\r\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r\n\r\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r\n\r\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r\n\r\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r\n\r\n/* SysTick Reload Register Definitions */\r\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r\n\r\n/* SysTick Current Register Definitions */\r\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r\n\r\n/* SysTick Calibration Register Definitions */\r\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r\n\r\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r\n\r\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r\n\r\n/*@} end of group CMSIS_SysTick */\r\n\r\n#if (__MPU_PRESENT == 1U)\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\r\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\r\n */\r\ntypedef struct\r\n{\r\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\r\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\r\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\r\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\r\n} MPU_Type;\r\n\r\n/* MPU Type Register Definitions */\r\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\r\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r\n\r\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\r\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r\n\r\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\r\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\r\n\r\n/* MPU Control Register Definitions */\r\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\r\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r\n\r\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\r\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r\n\r\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\r\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\r\n\r\n/* MPU Region Number Register Definitions */\r\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\r\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\r\n\r\n/* MPU Region Base Address Register Definitions */\r\n#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */\r\n#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */\r\n\r\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\r\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\r\n\r\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\r\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\r\n\r\n/* MPU Region Attribute and Size Register Definitions */\r\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\r\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\r\n\r\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\r\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\r\n\r\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\r\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\r\n\r\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\r\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\r\n\r\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\r\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\r\n\r\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\r\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\r\n\r\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\r\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\r\n\r\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\r\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\r\n\r\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\r\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\r\n\r\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\r\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\r\n\r\n/*@} end of group CMSIS_MPU */\r\n#endif\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r\n  \\brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\r\n            Therefore they are not covered by the Cortex-M0+ header file.\r\n  @{\r\n */\r\n/*@} end of group CMSIS_CoreDebug */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\r\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief   Mask and shift a bit field value for use in a register bit range.\r\n  \\param[in] field  Name of the register bit field.\r\n  \\param[in] value  Value of the bit field.\r\n  \\return           Masked and shifted value.\r\n*/\r\n#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)\r\n\r\n/**\r\n  \\brief     Mask and shift a register value to extract a bit filed value.\r\n  \\param[in] field  Name of the register bit field.\r\n  \\param[in] value  Value of register.\r\n  \\return           Masked and shifted bit field value.\r\n*/\r\n#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)\r\n\r\n/*@} end of group CMSIS_core_bitfield */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_core_base     Core Definitions\r\n  \\brief      Definitions for base addresses, unions, and structures.\r\n  @{\r\n */\r\n\r\n/* Memory mapping of Cortex-M0+ Hardware */\r\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\r\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\r\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\r\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\r\n\r\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\r\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\r\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\r\n\r\n#if (__MPU_PRESENT == 1U)\r\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\r\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\r\n#endif\r\n\r\n/*@} */\r\n\r\n\r\n\r\n/*******************************************************************************\r\n *                Hardware Abstraction Layer\r\n  Core Function Interface contains:\r\n  - Core NVIC Functions\r\n  - Core SysTick Functions\r\n  - Core Register Access Functions\r\n ******************************************************************************/\r\n/**\r\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r\n*/\r\n\r\n\r\n\r\n/* ##########################   NVIC functions  #################################### */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\r\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\r\n  @{\r\n */\r\n\r\n/* Interrupt Priorities are WORD accessible only under ARMv6M                   */\r\n/* The following MACROS handle generation of the register offset and byte masks */\r\n#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\r\n#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\r\n#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\r\n\r\n\r\n/**\r\n  \\brief   Enable External Interrupt\r\n  \\details Enables a device-specific interrupt in the NVIC interrupt controller.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Disable External Interrupt\r\n  \\details Disables a device-specific interrupt in the NVIC interrupt controller.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Pending Interrupt\r\n  \\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\return             0  Interrupt status is not pending.\r\n  \\return             1  Interrupt status is pending.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Pending Interrupt\r\n  \\details Sets the pending bit of an external interrupt.\r\n  \\param [in]      IRQn  Interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Clear Pending Interrupt\r\n  \\details Clears the pending bit of an external interrupt.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Interrupt Priority\r\n  \\details Sets the priority of an interrupt.\r\n  \\note    The priority cannot be set for every core interrupt.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\param [in]  priority  Priority to set.\r\n */\r\n__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r\n{\r\n  if ((int32_t)(IRQn) < 0)\r\n  {\r\n    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r\n  }\r\n  else\r\n  {\r\n    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Interrupt Priority\r\n  \\details Reads the priority of an interrupt.\r\n           The interrupt number can be positive to specify an external (device specific) interrupt,\r\n           or negative to specify an internal (core) interrupt.\r\n  \\param [in]   IRQn  Interrupt number.\r\n  \\return             Interrupt Priority.\r\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r\n{\r\n\r\n  if ((int32_t)(IRQn) < 0)\r\n  {\r\n    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r\n  }\r\n  else\r\n  {\r\n    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   System Reset\r\n  \\details Initiates a system reset request to reset the MCU.\r\n */\r\n__STATIC_INLINE void NVIC_SystemReset(void)\r\n{\r\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\r\n                                                                       buffered write are completed before reset */\r\n  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r\n                 SCB_AIRCR_SYSRESETREQ_Msk);\r\n  __DSB();                                                          /* Ensure completion of memory access */\r\n\r\n  for(;;)                                                           /* wait until reset */\r\n  {\r\n    __NOP();\r\n  }\r\n}\r\n\r\n/*@} end of CMSIS_Core_NVICFunctions */\r\n\r\n\r\n\r\n/* ##################################    SysTick function  ############################################ */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r\n  \\brief    Functions that configure the System.\r\n  @{\r\n */\r\n\r\n#if (__Vendor_SysTickConfig == 0U)\r\n\r\n/**\r\n  \\brief   System Tick Configuration\r\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r\n           Counter is in free running mode to generate periodic interrupts.\r\n  \\param [in]  ticks  Number of ticks between two interrupts.\r\n  \\return          0  Function succeeded.\r\n  \\return          1  Function failed.\r\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r\n           must contain a vendor-specific implementation of this function.\r\n */\r\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r\n{\r\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r\n  {\r\n    return (1UL);                                                   /* Reload value impossible */\r\n  }\r\n\r\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r\n                   SysTick_CTRL_TICKINT_Msk   |\r\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r\n  return (0UL);                                                     /* Function successful */\r\n}\r\n\r\n#endif\r\n\r\n/*@} end of CMSIS_Core_SysTickFunctions */\r\n\r\n\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __CORE_CM0PLUS_H_DEPENDANT */\r\n\r\n#endif /* __CMSIS_GENERIC */\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/include/core_cm3.h",
    "content": "/**************************************************************************//**\r\n * @file     core_cm3.h\r\n * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r\n * @version  V4.30\r\n * @date     20. October 2015\r\n ******************************************************************************/\r\n/* Copyright (c) 2009 - 2015 ARM LIMITED\r\n\r\n   All rights reserved.\r\n   Redistribution and use in source and binary forms, with or without\r\n   modification, are permitted provided that the following conditions are met:\r\n   - Redistributions of source code must retain the above copyright\r\n     notice, this list of conditions and the following disclaimer.\r\n   - Redistributions in binary form must reproduce the above copyright\r\n     notice, this list of conditions and the following disclaimer in the\r\n     documentation and/or other materials provided with the distribution.\r\n   - Neither the name of ARM nor the names of its contributors may be used\r\n     to endorse or promote products derived from this software without\r\n     specific prior written permission.\r\n   *\r\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n   POSSIBILITY OF SUCH DAMAGE.\r\n   ---------------------------------------------------------------------------*/\r\n\r\n\r\n#if   defined ( __ICCARM__ )\r\n #pragma system_include         /* treat file as system include file for MISRA check */\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #pragma clang system_header   /* treat file as system include file */\r\n#endif\r\n\r\n#ifndef __CORE_CM3_H_GENERIC\r\n#define __CORE_CM3_H_GENERIC\r\n\r\n#include <stdint.h>\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/**\r\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r\n  CMSIS violates the following MISRA-C:2004 rules:\r\n\r\n   \\li Required Rule 8.5, object/function definition in header file.<br>\r\n     Function definitions in header files are used to allow 'inlining'.\r\n\r\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r\n     Unions are used for effective representation of core registers.\r\n\r\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\r\n     Function-like macros are used to allow more efficient code.\r\n */\r\n\r\n\r\n/*******************************************************************************\r\n *                 CMSIS definitions\r\n ******************************************************************************/\r\n/**\r\n  \\ingroup Cortex_M3\r\n  @{\r\n */\r\n\r\n/*  CMSIS CM3 definitions */\r\n#define __CM3_CMSIS_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CMSIS HAL main version */\r\n#define __CM3_CMSIS_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CMSIS HAL sub version */\r\n#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \\\r\n                                    __CM3_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL version number */\r\n\r\n#define __CORTEX_M                (0x03U)                                      /*!< Cortex-M Core */\r\n\r\n\r\n#if   defined ( __CC_ARM )\r\n  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */\r\n  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */\r\n  #define __STATIC_INLINE  static __inline\r\n\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */\r\n  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */\r\n  #define __STATIC_INLINE  static __inline\r\n\r\n#elif defined ( __GNUC__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __ICCARM__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __TMS470__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __TASKING__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __CSMC__ )\r\n  #define __packed\r\n  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */\r\n  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#else\r\n  #error Unknown compiler\r\n#endif\r\n\r\n/** __FPU_USED indicates whether an FPU is used or not.\r\n    This core does not support an FPU at all\r\n*/\r\n#define __FPU_USED       0U\r\n\r\n#if defined ( __CC_ARM )\r\n  #if defined __TARGET_FPU_VFP\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #if defined __ARM_PCS_VFP\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __GNUC__ )\r\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __ICCARM__ )\r\n  #if defined __ARMVFP__\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __TMS470__ )\r\n  #if defined __TI_VFP_SUPPORT__\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __TASKING__ )\r\n  #if defined __FPU_VFP__\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __CSMC__ )\r\n  #if ( __CSMC__ & 0x400U)\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#endif\r\n\r\n#include \"core_cmInstr.h\"                /* Core Instruction Access */\r\n#include \"core_cmFunc.h\"                 /* Core Function Access */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __CORE_CM3_H_GENERIC */\r\n\r\n#ifndef __CMSIS_GENERIC\r\n\r\n#ifndef __CORE_CM3_H_DEPENDANT\r\n#define __CORE_CM3_H_DEPENDANT\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* check device defines and use defaults */\r\n#if defined __CHECK_DEVICE_DEFINES\r\n  #ifndef __CM3_REV\r\n    #define __CM3_REV               0x0200U\r\n    #warning \"__CM3_REV not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __MPU_PRESENT\r\n    #define __MPU_PRESENT             0U\r\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __NVIC_PRIO_BITS\r\n    #define __NVIC_PRIO_BITS          4U\r\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __Vendor_SysTickConfig\r\n    #define __Vendor_SysTickConfig    0U\r\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\r\n  #endif\r\n#endif\r\n\r\n/* IO definitions (access restrictions to peripheral registers) */\r\n/**\r\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\r\n\r\n    <strong>IO Type Qualifiers</strong> are used\r\n    \\li to specify the access to peripheral variables.\r\n    \\li for automatic generation of peripheral register debug information.\r\n*/\r\n#ifdef __cplusplus\r\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\r\n#else\r\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r\n#endif\r\n#define     __O     volatile             /*!< Defines 'write only' permissions */\r\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r\n\r\n/* following defines should be used for structure members */\r\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r\n\r\n/*@} end of group Cortex_M3 */\r\n\r\n\r\n\r\n/*******************************************************************************\r\n *                 Register Abstraction\r\n  Core Register contain:\r\n  - Core Register\r\n  - Core NVIC Register\r\n  - Core SCB Register\r\n  - Core SysTick Register\r\n  - Core Debug Register\r\n  - Core MPU Register\r\n ******************************************************************************/\r\n/**\r\n  \\defgroup CMSIS_core_register Defines and Type Definitions\r\n  \\brief Type definitions and defines for Cortex-M processor based devices.\r\n*/\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_CORE  Status and Control Registers\r\n  \\brief      Core Register type definitions.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Union type to access the Application Program Status Register (APSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */\r\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} APSR_Type;\r\n\r\n/* APSR Register Definitions */\r\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r\n\r\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r\n\r\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r\n\r\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r\n\r\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\r\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} IPSR_Type;\r\n\r\n/* IPSR Register Definitions */\r\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\r\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\r\n    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */\r\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} xPSR_Type;\r\n\r\n/* xPSR Register Definitions */\r\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r\n\r\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r\n\r\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r\n\r\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r\n\r\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\r\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\r\n\r\n#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */\r\n#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */\r\n\r\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r\n\r\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Control Registers (CONTROL).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\r\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\r\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} CONTROL_Type;\r\n\r\n/* CONTROL Register Definitions */\r\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r\n\r\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\r\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\r\n\r\n/*@} end of group CMSIS_CORE */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r\n  \\brief      Type definitions for the NVIC Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r\n        uint32_t RESERVED0[24U];\r\n  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r\n        uint32_t RSERVED1[24U];\r\n  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r\n        uint32_t RESERVED2[24U];\r\n  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r\n        uint32_t RESERVED3[24U];\r\n  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\r\n        uint32_t RESERVED4[56U];\r\n  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\r\n        uint32_t RESERVED5[644U];\r\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\r\n}  NVIC_Type;\r\n\r\n/* Software Triggered Interrupt Register Definitions */\r\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\r\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\r\n\r\n/*@} end of group CMSIS_NVIC */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\r\n  \\brief    Type definitions for the System Control Block Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Control Block (SCB).\r\n */\r\ntypedef struct\r\n{\r\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\r\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r\n  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\r\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\r\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\r\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\r\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\r\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\r\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\r\n  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */\r\n  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */\r\n  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\r\n  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\r\n  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\r\n        uint32_t RESERVED0[5U];\r\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\r\n} SCB_Type;\r\n\r\n/* SCB CPUID Register Definitions */\r\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r\n\r\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r\n\r\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r\n\r\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r\n\r\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r\n\r\n/* SCB Interrupt Control State Register Definitions */\r\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\r\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\r\n\r\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r\n\r\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r\n\r\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r\n\r\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r\n\r\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r\n\r\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r\n\r\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r\n\r\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\r\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\r\n\r\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r\n\r\n/* SCB Vector Table Offset Register Definitions */\r\n#if (__CM3_REV < 0x0201U)                   /* core r2p1 */\r\n#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */\r\n#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */\r\n\r\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\r\n#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */\r\n#else\r\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\r\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\r\n#endif\r\n\r\n/* SCB Application Interrupt and Reset Control Register Definitions */\r\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r\n\r\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r\n\r\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r\n\r\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\r\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\r\n\r\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r\n\r\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r\n\r\n#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\r\n#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\r\n\r\n/* SCB System Control Register Definitions */\r\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r\n\r\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r\n\r\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r\n\r\n/* SCB Configuration Control Register Definitions */\r\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\r\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\r\n\r\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\r\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\r\n\r\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\r\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\r\n\r\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r\n\r\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\r\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\r\n\r\n#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\r\n#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\r\n\r\n/* SCB System Handler Control and State Register Definitions */\r\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\r\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\r\n\r\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\r\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\r\n\r\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\r\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\r\n\r\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r\n\r\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\r\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r\n\r\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\r\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r\n\r\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\r\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\r\n\r\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\r\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\r\n\r\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\r\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\r\n\r\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\r\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\r\n\r\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\r\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\r\n\r\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\r\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\r\n\r\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\r\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\r\n\r\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\r\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\r\n\r\n/* SCB Configurable Fault Status Register Definitions */\r\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\r\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\r\n\r\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\r\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\r\n\r\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r\n\r\n/* SCB Hard Fault Status Register Definitions */\r\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\r\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\r\n\r\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\r\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\r\n\r\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\r\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\r\n\r\n/* SCB Debug Fault Status Register Definitions */\r\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\r\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\r\n\r\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\r\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\r\n\r\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\r\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\r\n\r\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\r\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\r\n\r\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\r\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\r\n\r\n/*@} end of group CMSIS_SCB */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\r\n */\r\ntypedef struct\r\n{\r\n        uint32_t RESERVED0[1U];\r\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\r\n#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U))\r\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\r\n#else\r\n        uint32_t RESERVED1[1U];\r\n#endif\r\n} SCnSCB_Type;\r\n\r\n/* Interrupt Controller Type Register Definitions */\r\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\r\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\r\n\r\n/* Auxiliary Control Register Definitions */\r\n\r\n#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */\r\n#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */\r\n\r\n#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */\r\n#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */\r\n\r\n#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\r\n#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\r\n\r\n/*@} end of group CMSIS_SCnotSCB */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r\n  \\brief    Type definitions for the System Timer Registers.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Timer (SysTick).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r\n} SysTick_Type;\r\n\r\n/* SysTick Control / Status Register Definitions */\r\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r\n\r\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r\n\r\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r\n\r\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r\n\r\n/* SysTick Reload Register Definitions */\r\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r\n\r\n/* SysTick Current Register Definitions */\r\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r\n\r\n/* SysTick Calibration Register Definitions */\r\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r\n\r\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r\n\r\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r\n\r\n/*@} end of group CMSIS_SysTick */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\r\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r\n */\r\ntypedef struct\r\n{\r\n  __OM  union\r\n  {\r\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\r\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\r\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\r\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\r\n        uint32_t RESERVED0[864U];\r\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\r\n        uint32_t RESERVED1[15U];\r\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\r\n        uint32_t RESERVED2[15U];\r\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\r\n        uint32_t RESERVED3[29U];\r\n  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\r\n  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\r\n  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\r\n        uint32_t RESERVED4[43U];\r\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\r\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\r\n        uint32_t RESERVED5[6U];\r\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\r\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\r\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\r\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\r\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\r\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\r\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\r\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\r\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\r\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\r\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\r\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\r\n} ITM_Type;\r\n\r\n/* ITM Trace Privilege Register Definitions */\r\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\r\n#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */\r\n\r\n/* ITM Trace Control Register Definitions */\r\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\r\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\r\n\r\n#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\r\n#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */\r\n\r\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\r\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\r\n\r\n#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\r\n#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\r\n\r\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\r\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\r\n\r\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\r\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\r\n\r\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\r\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\r\n\r\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\r\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\r\n\r\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\r\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\r\n\r\n/* ITM Integration Write Register Definitions */\r\n#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */\r\n#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\r\n\r\n/* ITM Integration Read Register Definitions */\r\n#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */\r\n#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\r\n\r\n/* ITM Integration Mode Control Register Definitions */\r\n#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */\r\n#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\r\n\r\n/* ITM Lock Status Register Definitions */\r\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\r\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\r\n\r\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\r\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\r\n\r\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\r\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\r\n\r\n/*@}*/ /* end of group CMSIS_ITM */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\r\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\r\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\r\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\r\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\r\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\r\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\r\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\r\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\r\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\r\n  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\r\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\r\n        uint32_t RESERVED0[1U];\r\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\r\n  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\r\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\r\n        uint32_t RESERVED1[1U];\r\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\r\n  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\r\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\r\n        uint32_t RESERVED2[1U];\r\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\r\n  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\r\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\r\n} DWT_Type;\r\n\r\n/* DWT Control Register Definitions */\r\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\r\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\r\n\r\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\r\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\r\n\r\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\r\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\r\n\r\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\r\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\r\n\r\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\r\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\r\n\r\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\r\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\r\n\r\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\r\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\r\n\r\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\r\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\r\n\r\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\r\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\r\n\r\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\r\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\r\n\r\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\r\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\r\n\r\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\r\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\r\n\r\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\r\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\r\n\r\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\r\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\r\n\r\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\r\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\r\n\r\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\r\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\r\n\r\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\r\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\r\n\r\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\r\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\r\n\r\n/* DWT CPI Count Register Definitions */\r\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\r\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\r\n\r\n/* DWT Exception Overhead Count Register Definitions */\r\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\r\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\r\n\r\n/* DWT Sleep Count Register Definitions */\r\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\r\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r\n\r\n/* DWT LSU Count Register Definitions */\r\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\r\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\r\n\r\n/* DWT Folded-instruction Count Register Definitions */\r\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\r\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\r\n\r\n/* DWT Comparator Mask Register Definitions */\r\n#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\r\n#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\r\n\r\n/* DWT Comparator Function Register Definitions */\r\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\r\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\r\n\r\n#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\r\n#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\r\n\r\n#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\r\n#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\r\n\r\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\r\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\r\n\r\n#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\r\n#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\r\n\r\n#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\r\n#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\r\n\r\n#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\r\n#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\r\n\r\n#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\r\n#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\r\n\r\n#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\r\n#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\r\n\r\n/*@}*/ /* end of group CMSIS_DWT */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\r\n  \\brief    Type definitions for the Trace Port Interface (TPI)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\r\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\r\n        uint32_t RESERVED0[2U];\r\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\r\n        uint32_t RESERVED1[55U];\r\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\r\n        uint32_t RESERVED2[131U];\r\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\r\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\r\n  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\r\n        uint32_t RESERVED3[759U];\r\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */\r\n  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\r\n  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\r\n        uint32_t RESERVED4[1U];\r\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\r\n  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\r\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\r\n        uint32_t RESERVED5[39U];\r\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\r\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\r\n        uint32_t RESERVED7[8U];\r\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\r\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\r\n} TPI_Type;\r\n\r\n/* TPI Asynchronous Clock Prescaler Register Definitions */\r\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\r\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\r\n\r\n/* TPI Selected Pin Protocol Register Definitions */\r\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\r\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\r\n\r\n/* TPI Formatter and Flush Status Register Definitions */\r\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\r\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\r\n\r\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\r\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\r\n\r\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\r\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\r\n\r\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\r\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\r\n\r\n/* TPI Formatter and Flush Control Register Definitions */\r\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\r\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\r\n\r\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\r\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\r\n\r\n/* TPI TRIGGER Register Definitions */\r\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\r\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\r\n\r\n/* TPI Integration ETM Data Register Definitions (FIFO0) */\r\n#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\r\n#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\r\n\r\n#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\r\n#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\r\n\r\n#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\r\n#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\r\n\r\n#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\r\n#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\r\n\r\n#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\r\n#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\r\n\r\n#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\r\n#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\r\n\r\n#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\r\n#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\r\n\r\n/* TPI ITATBCTR2 Register Definitions */\r\n#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */\r\n#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */\r\n\r\n/* TPI Integration ITM Data Register Definitions (FIFO1) */\r\n#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\r\n#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\r\n\r\n#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\r\n#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\r\n\r\n#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\r\n#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\r\n\r\n#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\r\n#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\r\n\r\n#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\r\n#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\r\n\r\n#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\r\n#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\r\n\r\n#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\r\n#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\r\n\r\n/* TPI ITATBCTR0 Register Definitions */\r\n#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */\r\n#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */\r\n\r\n/* TPI Integration Mode Control Register Definitions */\r\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\r\n#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\r\n\r\n/* TPI DEVID Register Definitions */\r\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\r\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\r\n\r\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\r\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\r\n\r\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\r\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\r\n\r\n#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\r\n#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\r\n\r\n#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\r\n#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\r\n\r\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\r\n#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\r\n\r\n/* TPI DEVTYPE Register Definitions */\r\n#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */\r\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\r\n\r\n#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */\r\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\r\n\r\n/*@}*/ /* end of group CMSIS_TPI */\r\n\r\n\r\n#if (__MPU_PRESENT == 1U)\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\r\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\r\n */\r\ntypedef struct\r\n{\r\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\r\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\r\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\r\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\r\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\r\n  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\r\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\r\n  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\r\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\r\n  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\r\n} MPU_Type;\r\n\r\n/* MPU Type Register Definitions */\r\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\r\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r\n\r\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\r\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r\n\r\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\r\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\r\n\r\n/* MPU Control Register Definitions */\r\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\r\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r\n\r\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\r\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r\n\r\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\r\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\r\n\r\n/* MPU Region Number Register Definitions */\r\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\r\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\r\n\r\n/* MPU Region Base Address Register Definitions */\r\n#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\r\n#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\r\n\r\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\r\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\r\n\r\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\r\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\r\n\r\n/* MPU Region Attribute and Size Register Definitions */\r\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\r\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\r\n\r\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\r\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\r\n\r\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\r\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\r\n\r\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\r\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\r\n\r\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\r\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\r\n\r\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\r\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\r\n\r\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\r\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\r\n\r\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\r\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\r\n\r\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\r\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\r\n\r\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\r\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\r\n\r\n/*@} end of group CMSIS_MPU */\r\n#endif\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r\n  \\brief    Type definitions for the Core Debug Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\r\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\r\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\r\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\r\n} CoreDebug_Type;\r\n\r\n/* Debug Halting Control and Status Register Definitions */\r\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\r\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\r\n\r\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\r\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r\n\r\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r\n\r\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\r\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r\n\r\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\r\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\r\n\r\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\r\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\r\n\r\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\r\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\r\n\r\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r\n\r\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\r\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r\n\r\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\r\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\r\n\r\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\r\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\r\n\r\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r\n\r\n/* Debug Core Register Selector Register Definitions */\r\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\r\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\r\n\r\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\r\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\r\n\r\n/* Debug Exception and Monitor Control Register Definitions */\r\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\r\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\r\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\r\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\r\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\r\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\r\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\r\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\r\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\r\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\r\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\r\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\r\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r\n\r\n/*@} end of group CMSIS_CoreDebug */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\r\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief   Mask and shift a bit field value for use in a register bit range.\r\n  \\param[in] field  Name of the register bit field.\r\n  \\param[in] value  Value of the bit field.\r\n  \\return           Masked and shifted value.\r\n*/\r\n#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)\r\n\r\n/**\r\n  \\brief     Mask and shift a register value to extract a bit filed value.\r\n  \\param[in] field  Name of the register bit field.\r\n  \\param[in] value  Value of register.\r\n  \\return           Masked and shifted bit field value.\r\n*/\r\n#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)\r\n\r\n/*@} end of group CMSIS_core_bitfield */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_core_base     Core Definitions\r\n  \\brief      Definitions for base addresses, unions, and structures.\r\n  @{\r\n */\r\n\r\n/* Memory mapping of Cortex-M3 Hardware */\r\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\r\n#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\r\n#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\r\n#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\r\n#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\r\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\r\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\r\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\r\n\r\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\r\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\r\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\r\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\r\n#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\r\n#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\r\n#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\r\n#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\r\n\r\n#if (__MPU_PRESENT == 1U)\r\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\r\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\r\n#endif\r\n\r\n/*@} */\r\n\r\n\r\n\r\n/*******************************************************************************\r\n *                Hardware Abstraction Layer\r\n  Core Function Interface contains:\r\n  - Core NVIC Functions\r\n  - Core SysTick Functions\r\n  - Core Debug Functions\r\n  - Core Register Access Functions\r\n ******************************************************************************/\r\n/**\r\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r\n*/\r\n\r\n\r\n\r\n/* ##########################   NVIC functions  #################################### */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\r\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief   Set Priority Grouping\r\n  \\details Sets the priority grouping field using the required unlock sequence.\r\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r\n           Only values from 0..7 are used.\r\n           In case of a conflict between priority grouping and available\r\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r\n  \\param [in]      PriorityGroup  Priority grouping field.\r\n */\r\n__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r\n{\r\n  uint32_t reg_value;\r\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\r\n\r\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\r\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\r\n  reg_value  =  (reg_value                                   |\r\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r\n                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */\r\n  SCB->AIRCR =  reg_value;\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Priority Grouping\r\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\r\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r\n{\r\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Enable External Interrupt\r\n  \\details Enables a device-specific interrupt in the NVIC interrupt controller.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Disable External Interrupt\r\n  \\details Disables a device-specific interrupt in the NVIC interrupt controller.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Pending Interrupt\r\n  \\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\return             0  Interrupt status is not pending.\r\n  \\return             1  Interrupt status is pending.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Pending Interrupt\r\n  \\details Sets the pending bit of an external interrupt.\r\n  \\param [in]      IRQn  Interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Clear Pending Interrupt\r\n  \\details Clears the pending bit of an external interrupt.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Active Interrupt\r\n  \\details Reads the active register in NVIC and returns the active bit.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\return             0  Interrupt status is not active.\r\n  \\return             1  Interrupt status is active.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r\n{\r\n  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Interrupt Priority\r\n  \\details Sets the priority of an interrupt.\r\n  \\note    The priority cannot be set for every core interrupt.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\param [in]  priority  Priority to set.\r\n */\r\n__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r\n{\r\n  if ((int32_t)(IRQn) < 0)\r\n  {\r\n    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r\n  }\r\n  else\r\n  {\r\n    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Interrupt Priority\r\n  \\details Reads the priority of an interrupt.\r\n           The interrupt number can be positive to specify an external (device specific) interrupt,\r\n           or negative to specify an internal (core) interrupt.\r\n  \\param [in]   IRQn  Interrupt number.\r\n  \\return             Interrupt Priority.\r\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r\n{\r\n\r\n  if ((int32_t)(IRQn) < 0)\r\n  {\r\n    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r\n  }\r\n  else\r\n  {\r\n    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Encode Priority\r\n  \\details Encodes the priority for an interrupt with the given priority group,\r\n           preemptive priority value, and subpriority value.\r\n           In case of a conflict between priority grouping and available\r\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r\n  \\param [in]     PriorityGroup  Used priority group.\r\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\r\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\r\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\r\n */\r\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r\n{\r\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r\n  uint32_t PreemptPriorityBits;\r\n  uint32_t SubPriorityBits;\r\n\r\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r\n\r\n  return (\r\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\r\n         );\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Decode Priority\r\n  \\details Decodes an interrupt priority value with a given priority group to\r\n           preemptive priority value and subpriority value.\r\n           In case of a conflict between priority grouping and available\r\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\r\n  \\param [in]     PriorityGroup  Used priority group.\r\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\r\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\r\n */\r\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r\n{\r\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r\n  uint32_t PreemptPriorityBits;\r\n  uint32_t SubPriorityBits;\r\n\r\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r\n\r\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   System Reset\r\n  \\details Initiates a system reset request to reset the MCU.\r\n */\r\n__STATIC_INLINE void NVIC_SystemReset(void)\r\n{\r\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\r\n                                                                       buffered write are completed before reset */\r\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\r\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\r\n  __DSB();                                                          /* Ensure completion of memory access */\r\n\r\n  for(;;)                                                           /* wait until reset */\r\n  {\r\n    __NOP();\r\n  }\r\n}\r\n\r\n/*@} end of CMSIS_Core_NVICFunctions */\r\n\r\n\r\n\r\n/* ##################################    SysTick function  ############################################ */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r\n  \\brief    Functions that configure the System.\r\n  @{\r\n */\r\n\r\n#if (__Vendor_SysTickConfig == 0U)\r\n\r\n/**\r\n  \\brief   System Tick Configuration\r\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r\n           Counter is in free running mode to generate periodic interrupts.\r\n  \\param [in]  ticks  Number of ticks between two interrupts.\r\n  \\return          0  Function succeeded.\r\n  \\return          1  Function failed.\r\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r\n           must contain a vendor-specific implementation of this function.\r\n */\r\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r\n{\r\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r\n  {\r\n    return (1UL);                                                   /* Reload value impossible */\r\n  }\r\n\r\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r\n                   SysTick_CTRL_TICKINT_Msk   |\r\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r\n  return (0UL);                                                     /* Function successful */\r\n}\r\n\r\n#endif\r\n\r\n/*@} end of CMSIS_Core_SysTickFunctions */\r\n\r\n\r\n\r\n/* ##################################### Debug In/Output function ########################################### */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\r\n  \\brief    Functions that access the ITM debug interface.\r\n  @{\r\n */\r\n\r\nextern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters. */\r\n#define                 ITM_RXBUFFER_EMPTY   0x5AA55AA5U /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\r\n\r\n\r\n/**\r\n  \\brief   ITM Send Character\r\n  \\details Transmits a character via the ITM channel 0, and\r\n           \\li Just returns when no debugger is connected that has booked the output.\r\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r\n  \\param [in]     ch  Character to transmit.\r\n  \\returns            Character to transmit.\r\n */\r\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r\n{\r\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\r\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\r\n  {\r\n    while (ITM->PORT[0U].u32 == 0UL)\r\n    {\r\n      __NOP();\r\n    }\r\n    ITM->PORT[0U].u8 = (uint8_t)ch;\r\n  }\r\n  return (ch);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   ITM Receive Character\r\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\r\n  \\return             Received character.\r\n  \\return         -1  No character pending.\r\n */\r\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r\n{\r\n  int32_t ch = -1;                           /* no character available */\r\n\r\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r\n  {\r\n    ch = ITM_RxBuffer;\r\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\r\n  }\r\n\r\n  return (ch);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   ITM Check Character\r\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\r\n  \\return          0  No character available.\r\n  \\return          1  Character available.\r\n */\r\n__STATIC_INLINE int32_t ITM_CheckChar (void)\r\n{\r\n\r\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r\n  {\r\n    return (0);                              /* no character available */\r\n  }\r\n  else\r\n  {\r\n    return (1);                              /*    character available */\r\n  }\r\n}\r\n\r\n/*@} end of CMSIS_core_DebugFunctions */\r\n\r\n\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __CORE_CM3_H_DEPENDANT */\r\n\r\n#endif /* __CMSIS_GENERIC */\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/include/core_cm4.h",
    "content": "/**************************************************************************//**\r\n * @file     core_cm4.h\r\n * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File\r\n * @version  V4.30\r\n * @date     20. October 2015\r\n ******************************************************************************/\r\n/* Copyright (c) 2009 - 2015 ARM LIMITED\r\n\r\n   All rights reserved.\r\n   Redistribution and use in source and binary forms, with or without\r\n   modification, are permitted provided that the following conditions are met:\r\n   - Redistributions of source code must retain the above copyright\r\n     notice, this list of conditions and the following disclaimer.\r\n   - Redistributions in binary form must reproduce the above copyright\r\n     notice, this list of conditions and the following disclaimer in the\r\n     documentation and/or other materials provided with the distribution.\r\n   - Neither the name of ARM nor the names of its contributors may be used\r\n     to endorse or promote products derived from this software without\r\n     specific prior written permission.\r\n   *\r\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n   POSSIBILITY OF SUCH DAMAGE.\r\n   ---------------------------------------------------------------------------*/\r\n\r\n\r\n#if   defined ( __ICCARM__ )\r\n #pragma system_include         /* treat file as system include file for MISRA check */\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #pragma clang system_header   /* treat file as system include file */\r\n#endif\r\n\r\n#ifndef __CORE_CM4_H_GENERIC\r\n#define __CORE_CM4_H_GENERIC\r\n\r\n#include <stdint.h>\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/**\r\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r\n  CMSIS violates the following MISRA-C:2004 rules:\r\n\r\n   \\li Required Rule 8.5, object/function definition in header file.<br>\r\n     Function definitions in header files are used to allow 'inlining'.\r\n\r\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r\n     Unions are used for effective representation of core registers.\r\n\r\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\r\n     Function-like macros are used to allow more efficient code.\r\n */\r\n\r\n\r\n/*******************************************************************************\r\n *                 CMSIS definitions\r\n ******************************************************************************/\r\n/**\r\n  \\ingroup Cortex_M4\r\n  @{\r\n */\r\n\r\n/*  CMSIS CM4 definitions */\r\n#define __CM4_CMSIS_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CMSIS HAL main version */\r\n#define __CM4_CMSIS_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CMSIS HAL sub version */\r\n#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \\\r\n                                    __CM4_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL version number */\r\n\r\n#define __CORTEX_M                (0x04U)                                      /*!< Cortex-M Core */\r\n\r\n\r\n#if   defined ( __CC_ARM )\r\n  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */\r\n  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */\r\n  #define __STATIC_INLINE  static __inline\r\n\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */\r\n  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */\r\n  #define __STATIC_INLINE  static __inline\r\n\r\n#elif defined ( __GNUC__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __ICCARM__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __TMS470__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __TASKING__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __CSMC__ )\r\n  #define __packed\r\n  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */\r\n  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#else\r\n  #error Unknown compiler\r\n#endif\r\n\r\n/** __FPU_USED indicates whether an FPU is used or not.\r\n    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r\n*/\r\n#if defined ( __CC_ARM )\r\n  #if defined __TARGET_FPU_VFP\r\n    #if (__FPU_PRESENT == 1U)\r\n      #define __FPU_USED       1U\r\n    #else\r\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n      #define __FPU_USED       0U\r\n    #endif\r\n  #else\r\n    #define __FPU_USED         0U\r\n  #endif\r\n\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #if defined __ARM_PCS_VFP\r\n    #if (__FPU_PRESENT == 1)\r\n      #define __FPU_USED       1U\r\n    #else\r\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n      #define __FPU_USED       0U\r\n    #endif\r\n  #else\r\n    #define __FPU_USED         0U\r\n  #endif\r\n\r\n#elif defined ( __GNUC__ )\r\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r\n    #if (__FPU_PRESENT == 1U)\r\n      #define __FPU_USED       1U\r\n    #else\r\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n      #define __FPU_USED       0U\r\n    #endif\r\n  #else\r\n    #define __FPU_USED         0U\r\n  #endif\r\n\r\n#elif defined ( __ICCARM__ )\r\n  #if defined __ARMVFP__\r\n    #if (__FPU_PRESENT == 1U)\r\n      #define __FPU_USED       1U\r\n    #else\r\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n      #define __FPU_USED       0U\r\n    #endif\r\n  #else\r\n    #define __FPU_USED         0U\r\n  #endif\r\n\r\n#elif defined ( __TMS470__ )\r\n  #if defined __TI_VFP_SUPPORT__\r\n    #if (__FPU_PRESENT == 1U)\r\n      #define __FPU_USED       1U\r\n    #else\r\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n      #define __FPU_USED       0U\r\n    #endif\r\n  #else\r\n    #define __FPU_USED         0U\r\n  #endif\r\n\r\n#elif defined ( __TASKING__ )\r\n  #if defined __FPU_VFP__\r\n    #if (__FPU_PRESENT == 1U)\r\n      #define __FPU_USED       1U\r\n    #else\r\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n      #define __FPU_USED       0U\r\n    #endif\r\n  #else\r\n    #define __FPU_USED         0U\r\n  #endif\r\n\r\n#elif defined ( __CSMC__ )\r\n  #if ( __CSMC__ & 0x400U)\r\n    #if (__FPU_PRESENT == 1U)\r\n      #define __FPU_USED       1U\r\n    #else\r\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n      #define __FPU_USED       0U\r\n    #endif\r\n  #else\r\n    #define __FPU_USED         0U\r\n  #endif\r\n\r\n#endif\r\n\r\n#include \"core_cmInstr.h\"                /* Core Instruction Access */\r\n#include \"core_cmFunc.h\"                 /* Core Function Access */\r\n#include \"core_cmSimd.h\"                 /* Compiler specific SIMD Intrinsics */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __CORE_CM4_H_GENERIC */\r\n\r\n#ifndef __CMSIS_GENERIC\r\n\r\n#ifndef __CORE_CM4_H_DEPENDANT\r\n#define __CORE_CM4_H_DEPENDANT\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* check device defines and use defaults */\r\n#if defined __CHECK_DEVICE_DEFINES\r\n  #ifndef __CM4_REV\r\n    #define __CM4_REV               0x0000U\r\n    #warning \"__CM4_REV not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __FPU_PRESENT\r\n    #define __FPU_PRESENT             0U\r\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __MPU_PRESENT\r\n    #define __MPU_PRESENT             0U\r\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __NVIC_PRIO_BITS\r\n    #define __NVIC_PRIO_BITS          4U\r\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __Vendor_SysTickConfig\r\n    #define __Vendor_SysTickConfig    0U\r\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\r\n  #endif\r\n#endif\r\n\r\n/* IO definitions (access restrictions to peripheral registers) */\r\n/**\r\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\r\n\r\n    <strong>IO Type Qualifiers</strong> are used\r\n    \\li to specify the access to peripheral variables.\r\n    \\li for automatic generation of peripheral register debug information.\r\n*/\r\n#ifdef __cplusplus\r\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\r\n#else\r\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r\n#endif\r\n#define     __O     volatile             /*!< Defines 'write only' permissions */\r\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r\n\r\n/* following defines should be used for structure members */\r\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r\n\r\n/*@} end of group Cortex_M4 */\r\n\r\n\r\n\r\n/*******************************************************************************\r\n *                 Register Abstraction\r\n  Core Register contain:\r\n  - Core Register\r\n  - Core NVIC Register\r\n  - Core SCB Register\r\n  - Core SysTick Register\r\n  - Core Debug Register\r\n  - Core MPU Register\r\n  - Core FPU Register\r\n ******************************************************************************/\r\n/**\r\n  \\defgroup CMSIS_core_register Defines and Type Definitions\r\n  \\brief Type definitions and defines for Cortex-M processor based devices.\r\n*/\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_CORE  Status and Control Registers\r\n  \\brief      Core Register type definitions.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Union type to access the Application Program Status Register (APSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\r\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\r\n    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\r\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} APSR_Type;\r\n\r\n/* APSR Register Definitions */\r\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r\n\r\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r\n\r\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r\n\r\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r\n\r\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\r\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\r\n\r\n#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\r\n#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} IPSR_Type;\r\n\r\n/* IPSR Register Definitions */\r\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r\n    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */\r\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\r\n    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\r\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\r\n    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */\r\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} xPSR_Type;\r\n\r\n/* xPSR Register Definitions */\r\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r\n\r\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r\n\r\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r\n\r\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r\n\r\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\r\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\r\n\r\n#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */\r\n#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */\r\n\r\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r\n\r\n#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\r\n#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\r\n\r\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Control Registers (CONTROL).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\r\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\r\n    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */\r\n    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} CONTROL_Type;\r\n\r\n/* CONTROL Register Definitions */\r\n#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\r\n#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\r\n\r\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r\n\r\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\r\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\r\n\r\n/*@} end of group CMSIS_CORE */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r\n  \\brief      Type definitions for the NVIC Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r\n        uint32_t RESERVED0[24U];\r\n  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r\n        uint32_t RSERVED1[24U];\r\n  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r\n        uint32_t RESERVED2[24U];\r\n  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r\n        uint32_t RESERVED3[24U];\r\n  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\r\n        uint32_t RESERVED4[56U];\r\n  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\r\n        uint32_t RESERVED5[644U];\r\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\r\n}  NVIC_Type;\r\n\r\n/* Software Triggered Interrupt Register Definitions */\r\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\r\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\r\n\r\n/*@} end of group CMSIS_NVIC */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\r\n  \\brief    Type definitions for the System Control Block Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Control Block (SCB).\r\n */\r\ntypedef struct\r\n{\r\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\r\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r\n  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\r\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\r\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\r\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\r\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\r\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\r\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\r\n  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */\r\n  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */\r\n  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\r\n  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\r\n  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\r\n        uint32_t RESERVED0[5U];\r\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\r\n} SCB_Type;\r\n\r\n/* SCB CPUID Register Definitions */\r\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r\n\r\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r\n\r\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r\n\r\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r\n\r\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r\n\r\n/* SCB Interrupt Control State Register Definitions */\r\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\r\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\r\n\r\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r\n\r\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r\n\r\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r\n\r\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r\n\r\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r\n\r\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r\n\r\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r\n\r\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\r\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\r\n\r\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r\n\r\n/* SCB Vector Table Offset Register Definitions */\r\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\r\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\r\n\r\n/* SCB Application Interrupt and Reset Control Register Definitions */\r\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r\n\r\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r\n\r\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r\n\r\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\r\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\r\n\r\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r\n\r\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r\n\r\n#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\r\n#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\r\n\r\n/* SCB System Control Register Definitions */\r\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r\n\r\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r\n\r\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r\n\r\n/* SCB Configuration Control Register Definitions */\r\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\r\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\r\n\r\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\r\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\r\n\r\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\r\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\r\n\r\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r\n\r\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\r\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\r\n\r\n#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\r\n#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\r\n\r\n/* SCB System Handler Control and State Register Definitions */\r\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\r\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\r\n\r\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\r\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\r\n\r\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\r\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\r\n\r\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r\n\r\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\r\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r\n\r\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\r\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r\n\r\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\r\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\r\n\r\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\r\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\r\n\r\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\r\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\r\n\r\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\r\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\r\n\r\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\r\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\r\n\r\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\r\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\r\n\r\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\r\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\r\n\r\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\r\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\r\n\r\n/* SCB Configurable Fault Status Register Definitions */\r\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\r\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\r\n\r\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\r\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\r\n\r\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r\n\r\n/* SCB Hard Fault Status Register Definitions */\r\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\r\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\r\n\r\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\r\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\r\n\r\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\r\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\r\n\r\n/* SCB Debug Fault Status Register Definitions */\r\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\r\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\r\n\r\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\r\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\r\n\r\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\r\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\r\n\r\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\r\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\r\n\r\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\r\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\r\n\r\n/*@} end of group CMSIS_SCB */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\r\n */\r\ntypedef struct\r\n{\r\n        uint32_t RESERVED0[1U];\r\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\r\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\r\n} SCnSCB_Type;\r\n\r\n/* Interrupt Controller Type Register Definitions */\r\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\r\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\r\n\r\n/* Auxiliary Control Register Definitions */\r\n#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */\r\n#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */\r\n\r\n#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */\r\n#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */\r\n\r\n#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */\r\n#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */\r\n\r\n#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */\r\n#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */\r\n\r\n#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\r\n#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\r\n\r\n/*@} end of group CMSIS_SCnotSCB */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r\n  \\brief    Type definitions for the System Timer Registers.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Timer (SysTick).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r\n} SysTick_Type;\r\n\r\n/* SysTick Control / Status Register Definitions */\r\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r\n\r\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r\n\r\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r\n\r\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r\n\r\n/* SysTick Reload Register Definitions */\r\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r\n\r\n/* SysTick Current Register Definitions */\r\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r\n\r\n/* SysTick Calibration Register Definitions */\r\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r\n\r\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r\n\r\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r\n\r\n/*@} end of group CMSIS_SysTick */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\r\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r\n */\r\ntypedef struct\r\n{\r\n  __OM  union\r\n  {\r\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\r\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\r\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\r\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\r\n        uint32_t RESERVED0[864U];\r\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\r\n        uint32_t RESERVED1[15U];\r\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\r\n        uint32_t RESERVED2[15U];\r\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\r\n        uint32_t RESERVED3[29U];\r\n  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\r\n  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\r\n  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\r\n        uint32_t RESERVED4[43U];\r\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\r\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\r\n        uint32_t RESERVED5[6U];\r\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\r\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\r\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\r\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\r\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\r\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\r\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\r\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\r\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\r\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\r\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\r\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\r\n} ITM_Type;\r\n\r\n/* ITM Trace Privilege Register Definitions */\r\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\r\n#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */\r\n\r\n/* ITM Trace Control Register Definitions */\r\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\r\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\r\n\r\n#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\r\n#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */\r\n\r\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\r\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\r\n\r\n#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\r\n#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\r\n\r\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\r\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\r\n\r\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\r\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\r\n\r\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\r\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\r\n\r\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\r\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\r\n\r\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\r\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\r\n\r\n/* ITM Integration Write Register Definitions */\r\n#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */\r\n#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\r\n\r\n/* ITM Integration Read Register Definitions */\r\n#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */\r\n#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\r\n\r\n/* ITM Integration Mode Control Register Definitions */\r\n#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */\r\n#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\r\n\r\n/* ITM Lock Status Register Definitions */\r\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\r\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\r\n\r\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\r\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\r\n\r\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\r\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\r\n\r\n/*@}*/ /* end of group CMSIS_ITM */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\r\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\r\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\r\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\r\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\r\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\r\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\r\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\r\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\r\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\r\n  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\r\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\r\n        uint32_t RESERVED0[1U];\r\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\r\n  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\r\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\r\n        uint32_t RESERVED1[1U];\r\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\r\n  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\r\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\r\n        uint32_t RESERVED2[1U];\r\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\r\n  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\r\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\r\n} DWT_Type;\r\n\r\n/* DWT Control Register Definitions */\r\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\r\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\r\n\r\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\r\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\r\n\r\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\r\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\r\n\r\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\r\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\r\n\r\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\r\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\r\n\r\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\r\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\r\n\r\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\r\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\r\n\r\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\r\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\r\n\r\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\r\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\r\n\r\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\r\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\r\n\r\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\r\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\r\n\r\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\r\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\r\n\r\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\r\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\r\n\r\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\r\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\r\n\r\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\r\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\r\n\r\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\r\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\r\n\r\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\r\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\r\n\r\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\r\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\r\n\r\n/* DWT CPI Count Register Definitions */\r\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\r\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\r\n\r\n/* DWT Exception Overhead Count Register Definitions */\r\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\r\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\r\n\r\n/* DWT Sleep Count Register Definitions */\r\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\r\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r\n\r\n/* DWT LSU Count Register Definitions */\r\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\r\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\r\n\r\n/* DWT Folded-instruction Count Register Definitions */\r\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\r\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\r\n\r\n/* DWT Comparator Mask Register Definitions */\r\n#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\r\n#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\r\n\r\n/* DWT Comparator Function Register Definitions */\r\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\r\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\r\n\r\n#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\r\n#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\r\n\r\n#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\r\n#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\r\n\r\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\r\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\r\n\r\n#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\r\n#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\r\n\r\n#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\r\n#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\r\n\r\n#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\r\n#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\r\n\r\n#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\r\n#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\r\n\r\n#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\r\n#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\r\n\r\n/*@}*/ /* end of group CMSIS_DWT */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\r\n  \\brief    Type definitions for the Trace Port Interface (TPI)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\r\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\r\n        uint32_t RESERVED0[2U];\r\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\r\n        uint32_t RESERVED1[55U];\r\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\r\n        uint32_t RESERVED2[131U];\r\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\r\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\r\n  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\r\n        uint32_t RESERVED3[759U];\r\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */\r\n  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\r\n  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\r\n        uint32_t RESERVED4[1U];\r\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\r\n  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\r\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\r\n        uint32_t RESERVED5[39U];\r\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\r\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\r\n        uint32_t RESERVED7[8U];\r\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\r\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\r\n} TPI_Type;\r\n\r\n/* TPI Asynchronous Clock Prescaler Register Definitions */\r\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\r\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\r\n\r\n/* TPI Selected Pin Protocol Register Definitions */\r\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\r\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\r\n\r\n/* TPI Formatter and Flush Status Register Definitions */\r\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\r\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\r\n\r\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\r\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\r\n\r\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\r\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\r\n\r\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\r\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\r\n\r\n/* TPI Formatter and Flush Control Register Definitions */\r\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\r\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\r\n\r\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\r\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\r\n\r\n/* TPI TRIGGER Register Definitions */\r\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\r\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\r\n\r\n/* TPI Integration ETM Data Register Definitions (FIFO0) */\r\n#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\r\n#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\r\n\r\n#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\r\n#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\r\n\r\n#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\r\n#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\r\n\r\n#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\r\n#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\r\n\r\n#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\r\n#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\r\n\r\n#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\r\n#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\r\n\r\n#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\r\n#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\r\n\r\n/* TPI ITATBCTR2 Register Definitions */\r\n#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */\r\n#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */\r\n\r\n/* TPI Integration ITM Data Register Definitions (FIFO1) */\r\n#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\r\n#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\r\n\r\n#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\r\n#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\r\n\r\n#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\r\n#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\r\n\r\n#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\r\n#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\r\n\r\n#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\r\n#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\r\n\r\n#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\r\n#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\r\n\r\n#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\r\n#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\r\n\r\n/* TPI ITATBCTR0 Register Definitions */\r\n#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */\r\n#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */\r\n\r\n/* TPI Integration Mode Control Register Definitions */\r\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\r\n#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\r\n\r\n/* TPI DEVID Register Definitions */\r\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\r\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\r\n\r\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\r\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\r\n\r\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\r\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\r\n\r\n#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\r\n#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\r\n\r\n#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\r\n#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\r\n\r\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\r\n#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\r\n\r\n/* TPI DEVTYPE Register Definitions */\r\n#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */\r\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\r\n\r\n#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */\r\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\r\n\r\n/*@}*/ /* end of group CMSIS_TPI */\r\n\r\n\r\n#if (__MPU_PRESENT == 1U)\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\r\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\r\n */\r\ntypedef struct\r\n{\r\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\r\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\r\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\r\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\r\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\r\n  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\r\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\r\n  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\r\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\r\n  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\r\n} MPU_Type;\r\n\r\n/* MPU Type Register Definitions */\r\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\r\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r\n\r\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\r\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r\n\r\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\r\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\r\n\r\n/* MPU Control Register Definitions */\r\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\r\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r\n\r\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\r\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r\n\r\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\r\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\r\n\r\n/* MPU Region Number Register Definitions */\r\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\r\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\r\n\r\n/* MPU Region Base Address Register Definitions */\r\n#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\r\n#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\r\n\r\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\r\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\r\n\r\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\r\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\r\n\r\n/* MPU Region Attribute and Size Register Definitions */\r\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\r\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\r\n\r\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\r\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\r\n\r\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\r\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\r\n\r\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\r\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\r\n\r\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\r\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\r\n\r\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\r\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\r\n\r\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\r\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\r\n\r\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\r\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\r\n\r\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\r\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\r\n\r\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\r\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\r\n\r\n/*@} end of group CMSIS_MPU */\r\n#endif\r\n\r\n\r\n#if (__FPU_PRESENT == 1U)\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_FPU     Floating Point Unit (FPU)\r\n  \\brief    Type definitions for the Floating Point Unit (FPU)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Floating Point Unit (FPU).\r\n */\r\ntypedef struct\r\n{\r\n        uint32_t RESERVED0[1U];\r\n  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\r\n  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\r\n  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\r\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */\r\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */\r\n} FPU_Type;\r\n\r\n/* Floating-Point Context Control Register Definitions */\r\n#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\r\n#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\r\n\r\n#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\r\n#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\r\n\r\n#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\r\n#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\r\n\r\n#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\r\n#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\r\n\r\n#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\r\n#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\r\n\r\n#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\r\n#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\r\n\r\n#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\r\n#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\r\n\r\n#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\r\n#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\r\n\r\n#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\r\n#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\r\n\r\n/* Floating-Point Context Address Register Definitions */\r\n#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\r\n#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\r\n\r\n/* Floating-Point Default Status Control Register Definitions */\r\n#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\r\n#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\r\n\r\n#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\r\n#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\r\n\r\n#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\r\n#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\r\n\r\n#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\r\n#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\r\n\r\n/* Media and FP Feature Register 0 Definitions */\r\n#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */\r\n#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */\r\n\r\n#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */\r\n#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */\r\n\r\n#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */\r\n#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */\r\n\r\n#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */\r\n#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */\r\n\r\n#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */\r\n#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */\r\n\r\n#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */\r\n#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */\r\n\r\n#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */\r\n#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */\r\n\r\n#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */\r\n#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */\r\n\r\n/* Media and FP Feature Register 1 Definitions */\r\n#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */\r\n#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */\r\n\r\n#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */\r\n#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */\r\n\r\n#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */\r\n#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */\r\n\r\n#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */\r\n#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */\r\n\r\n/*@} end of group CMSIS_FPU */\r\n#endif\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r\n  \\brief    Type definitions for the Core Debug Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\r\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\r\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\r\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\r\n} CoreDebug_Type;\r\n\r\n/* Debug Halting Control and Status Register Definitions */\r\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\r\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\r\n\r\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\r\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r\n\r\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r\n\r\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\r\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r\n\r\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\r\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\r\n\r\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\r\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\r\n\r\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\r\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\r\n\r\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r\n\r\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\r\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r\n\r\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\r\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\r\n\r\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\r\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\r\n\r\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r\n\r\n/* Debug Core Register Selector Register Definitions */\r\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\r\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\r\n\r\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\r\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\r\n\r\n/* Debug Exception and Monitor Control Register Definitions */\r\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\r\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\r\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\r\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\r\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\r\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\r\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\r\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\r\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\r\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\r\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\r\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\r\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r\n\r\n/*@} end of group CMSIS_CoreDebug */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\r\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief   Mask and shift a bit field value for use in a register bit range.\r\n  \\param[in] field  Name of the register bit field.\r\n  \\param[in] value  Value of the bit field.\r\n  \\return           Masked and shifted value.\r\n*/\r\n#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)\r\n\r\n/**\r\n  \\brief     Mask and shift a register value to extract a bit filed value.\r\n  \\param[in] field  Name of the register bit field.\r\n  \\param[in] value  Value of register.\r\n  \\return           Masked and shifted bit field value.\r\n*/\r\n#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)\r\n\r\n/*@} end of group CMSIS_core_bitfield */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_core_base     Core Definitions\r\n  \\brief      Definitions for base addresses, unions, and structures.\r\n  @{\r\n */\r\n\r\n/* Memory mapping of Cortex-M4 Hardware */\r\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\r\n#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\r\n#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\r\n#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\r\n#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\r\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\r\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\r\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\r\n\r\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\r\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\r\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\r\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\r\n#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\r\n#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\r\n#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\r\n#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\r\n\r\n#if (__MPU_PRESENT == 1U)\r\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\r\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\r\n#endif\r\n\r\n#if (__FPU_PRESENT == 1U)\r\n  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */\r\n  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */\r\n#endif\r\n\r\n/*@} */\r\n\r\n\r\n\r\n/*******************************************************************************\r\n *                Hardware Abstraction Layer\r\n  Core Function Interface contains:\r\n  - Core NVIC Functions\r\n  - Core SysTick Functions\r\n  - Core Debug Functions\r\n  - Core Register Access Functions\r\n ******************************************************************************/\r\n/**\r\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r\n*/\r\n\r\n\r\n\r\n/* ##########################   NVIC functions  #################################### */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\r\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief   Set Priority Grouping\r\n  \\details Sets the priority grouping field using the required unlock sequence.\r\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r\n           Only values from 0..7 are used.\r\n           In case of a conflict between priority grouping and available\r\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r\n  \\param [in]      PriorityGroup  Priority grouping field.\r\n */\r\n__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r\n{\r\n  uint32_t reg_value;\r\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\r\n\r\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\r\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\r\n  reg_value  =  (reg_value                                   |\r\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r\n                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */\r\n  SCB->AIRCR =  reg_value;\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Priority Grouping\r\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\r\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r\n{\r\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Enable External Interrupt\r\n  \\details Enables a device-specific interrupt in the NVIC interrupt controller.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Disable External Interrupt\r\n  \\details Disables a device-specific interrupt in the NVIC interrupt controller.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Pending Interrupt\r\n  \\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\return             0  Interrupt status is not pending.\r\n  \\return             1  Interrupt status is pending.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Pending Interrupt\r\n  \\details Sets the pending bit of an external interrupt.\r\n  \\param [in]      IRQn  Interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Clear Pending Interrupt\r\n  \\details Clears the pending bit of an external interrupt.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Active Interrupt\r\n  \\details Reads the active register in NVIC and returns the active bit.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\return             0  Interrupt status is not active.\r\n  \\return             1  Interrupt status is active.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r\n{\r\n  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Interrupt Priority\r\n  \\details Sets the priority of an interrupt.\r\n  \\note    The priority cannot be set for every core interrupt.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\param [in]  priority  Priority to set.\r\n */\r\n__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r\n{\r\n  if ((int32_t)(IRQn) < 0)\r\n  {\r\n    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r\n  }\r\n  else\r\n  {\r\n    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Interrupt Priority\r\n  \\details Reads the priority of an interrupt.\r\n           The interrupt number can be positive to specify an external (device specific) interrupt,\r\n           or negative to specify an internal (core) interrupt.\r\n  \\param [in]   IRQn  Interrupt number.\r\n  \\return             Interrupt Priority.\r\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r\n{\r\n\r\n  if ((int32_t)(IRQn) < 0)\r\n  {\r\n    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r\n  }\r\n  else\r\n  {\r\n    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Encode Priority\r\n  \\details Encodes the priority for an interrupt with the given priority group,\r\n           preemptive priority value, and subpriority value.\r\n           In case of a conflict between priority grouping and available\r\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r\n  \\param [in]     PriorityGroup  Used priority group.\r\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\r\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\r\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\r\n */\r\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r\n{\r\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r\n  uint32_t PreemptPriorityBits;\r\n  uint32_t SubPriorityBits;\r\n\r\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r\n\r\n  return (\r\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\r\n         );\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Decode Priority\r\n  \\details Decodes an interrupt priority value with a given priority group to\r\n           preemptive priority value and subpriority value.\r\n           In case of a conflict between priority grouping and available\r\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\r\n  \\param [in]     PriorityGroup  Used priority group.\r\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\r\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\r\n */\r\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r\n{\r\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r\n  uint32_t PreemptPriorityBits;\r\n  uint32_t SubPriorityBits;\r\n\r\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r\n\r\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   System Reset\r\n  \\details Initiates a system reset request to reset the MCU.\r\n */\r\n__STATIC_INLINE void NVIC_SystemReset(void)\r\n{\r\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\r\n                                                                       buffered write are completed before reset */\r\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\r\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\r\n  __DSB();                                                          /* Ensure completion of memory access */\r\n\r\n  for(;;)                                                           /* wait until reset */\r\n  {\r\n    __NOP();\r\n  }\r\n}\r\n\r\n/*@} end of CMSIS_Core_NVICFunctions */\r\n\r\n\r\n\r\n/* ##################################    SysTick function  ############################################ */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r\n  \\brief    Functions that configure the System.\r\n  @{\r\n */\r\n\r\n#if (__Vendor_SysTickConfig == 0U)\r\n\r\n/**\r\n  \\brief   System Tick Configuration\r\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r\n           Counter is in free running mode to generate periodic interrupts.\r\n  \\param [in]  ticks  Number of ticks between two interrupts.\r\n  \\return          0  Function succeeded.\r\n  \\return          1  Function failed.\r\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r\n           must contain a vendor-specific implementation of this function.\r\n */\r\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r\n{\r\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r\n  {\r\n    return (1UL);                                                   /* Reload value impossible */\r\n  }\r\n\r\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r\n                   SysTick_CTRL_TICKINT_Msk   |\r\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r\n  return (0UL);                                                     /* Function successful */\r\n}\r\n\r\n#endif\r\n\r\n/*@} end of CMSIS_Core_SysTickFunctions */\r\n\r\n\r\n\r\n/* ##################################### Debug In/Output function ########################################### */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\r\n  \\brief    Functions that access the ITM debug interface.\r\n  @{\r\n */\r\n\r\nextern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters. */\r\n#define                 ITM_RXBUFFER_EMPTY   0x5AA55AA5U /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\r\n\r\n\r\n/**\r\n  \\brief   ITM Send Character\r\n  \\details Transmits a character via the ITM channel 0, and\r\n           \\li Just returns when no debugger is connected that has booked the output.\r\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r\n  \\param [in]     ch  Character to transmit.\r\n  \\returns            Character to transmit.\r\n */\r\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r\n{\r\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\r\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\r\n  {\r\n    while (ITM->PORT[0U].u32 == 0UL)\r\n    {\r\n      __NOP();\r\n    }\r\n    ITM->PORT[0U].u8 = (uint8_t)ch;\r\n  }\r\n  return (ch);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   ITM Receive Character\r\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\r\n  \\return             Received character.\r\n  \\return         -1  No character pending.\r\n */\r\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r\n{\r\n  int32_t ch = -1;                           /* no character available */\r\n\r\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r\n  {\r\n    ch = ITM_RxBuffer;\r\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\r\n  }\r\n\r\n  return (ch);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   ITM Check Character\r\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\r\n  \\return          0  No character available.\r\n  \\return          1  Character available.\r\n */\r\n__STATIC_INLINE int32_t ITM_CheckChar (void)\r\n{\r\n\r\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r\n  {\r\n    return (0);                              /* no character available */\r\n  }\r\n  else\r\n  {\r\n    return (1);                              /*    character available */\r\n  }\r\n}\r\n\r\n/*@} end of CMSIS_core_DebugFunctions */\r\n\r\n\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __CORE_CM4_H_DEPENDANT */\r\n\r\n#endif /* __CMSIS_GENERIC */\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/include/core_cm7.h",
    "content": "/**************************************************************************//**\r\n * @file     core_cm7.h\r\n * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File\r\n * @version  V4.30\r\n * @date     20. October 2015\r\n ******************************************************************************/\r\n/* Copyright (c) 2009 - 2015 ARM LIMITED\r\n\r\n   All rights reserved.\r\n   Redistribution and use in source and binary forms, with or without\r\n   modification, are permitted provided that the following conditions are met:\r\n   - Redistributions of source code must retain the above copyright\r\n     notice, this list of conditions and the following disclaimer.\r\n   - Redistributions in binary form must reproduce the above copyright\r\n     notice, this list of conditions and the following disclaimer in the\r\n     documentation and/or other materials provided with the distribution.\r\n   - Neither the name of ARM nor the names of its contributors may be used\r\n     to endorse or promote products derived from this software without\r\n     specific prior written permission.\r\n   *\r\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n   POSSIBILITY OF SUCH DAMAGE.\r\n   ---------------------------------------------------------------------------*/\r\n\r\n\r\n#if   defined ( __ICCARM__ )\r\n #pragma system_include         /* treat file as system include file for MISRA check */\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #pragma clang system_header   /* treat file as system include file */\r\n#endif\r\n\r\n#ifndef __CORE_CM7_H_GENERIC\r\n#define __CORE_CM7_H_GENERIC\r\n\r\n#include <stdint.h>\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/**\r\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r\n  CMSIS violates the following MISRA-C:2004 rules:\r\n\r\n   \\li Required Rule 8.5, object/function definition in header file.<br>\r\n     Function definitions in header files are used to allow 'inlining'.\r\n\r\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r\n     Unions are used for effective representation of core registers.\r\n\r\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\r\n     Function-like macros are used to allow more efficient code.\r\n */\r\n\r\n\r\n/*******************************************************************************\r\n *                 CMSIS definitions\r\n ******************************************************************************/\r\n/**\r\n  \\ingroup Cortex_M7\r\n  @{\r\n */\r\n\r\n/*  CMSIS CM7 definitions */\r\n#define __CM7_CMSIS_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CMSIS HAL main version */\r\n#define __CM7_CMSIS_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CMSIS HAL sub version */\r\n#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \\\r\n                                    __CM7_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL version number */\r\n\r\n#define __CORTEX_M                (0x07U)                                      /*!< Cortex-M Core */\r\n\r\n\r\n#if   defined ( __CC_ARM )\r\n  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */\r\n  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */\r\n  #define __STATIC_INLINE  static __inline\r\n\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */\r\n  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */\r\n  #define __STATIC_INLINE  static __inline\r\n\r\n#elif defined ( __GNUC__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __ICCARM__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __TMS470__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __TASKING__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __CSMC__ )\r\n  #define __packed\r\n  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */\r\n  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#else\r\n  #error Unknown compiler\r\n#endif\r\n\r\n/** __FPU_USED indicates whether an FPU is used or not.\r\n    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r\n*/\r\n#if defined ( __CC_ARM )\r\n  #if defined __TARGET_FPU_VFP\r\n    #if (__FPU_PRESENT == 1U)\r\n      #define __FPU_USED       1U\r\n    #else\r\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n      #define __FPU_USED       0U\r\n    #endif\r\n  #else\r\n    #define __FPU_USED         0U\r\n  #endif\r\n\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #if defined __ARM_PCS_VFP\r\n    #if (__FPU_PRESENT == 1)\r\n      #define __FPU_USED       1U\r\n    #else\r\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n      #define __FPU_USED       0U\r\n    #endif\r\n  #else\r\n    #define __FPU_USED         0U\r\n  #endif\r\n\r\n#elif defined ( __GNUC__ )\r\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r\n    #if (__FPU_PRESENT == 1U)\r\n      #define __FPU_USED       1U\r\n    #else\r\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n      #define __FPU_USED       0U\r\n    #endif\r\n  #else\r\n    #define __FPU_USED         0U\r\n  #endif\r\n\r\n#elif defined ( __ICCARM__ )\r\n  #if defined __ARMVFP__\r\n    #if (__FPU_PRESENT == 1U)\r\n      #define __FPU_USED       1U\r\n    #else\r\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n      #define __FPU_USED       0U\r\n    #endif\r\n  #else\r\n    #define __FPU_USED         0U\r\n  #endif\r\n\r\n#elif defined ( __TMS470__ )\r\n  #if defined __TI_VFP_SUPPORT__\r\n    #if (__FPU_PRESENT == 1U)\r\n      #define __FPU_USED       1U\r\n    #else\r\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n      #define __FPU_USED       0U\r\n    #endif\r\n  #else\r\n    #define __FPU_USED         0U\r\n  #endif\r\n\r\n#elif defined ( __TASKING__ )\r\n  #if defined __FPU_VFP__\r\n    #if (__FPU_PRESENT == 1U)\r\n      #define __FPU_USED       1U\r\n    #else\r\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n      #define __FPU_USED       0U\r\n    #endif\r\n  #else\r\n    #define __FPU_USED         0U\r\n  #endif\r\n\r\n#elif defined ( __CSMC__ )\r\n  #if ( __CSMC__ & 0x400U)\r\n    #if (__FPU_PRESENT == 1U)\r\n      #define __FPU_USED       1U\r\n    #else\r\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n      #define __FPU_USED       0U\r\n    #endif\r\n  #else\r\n    #define __FPU_USED         0U\r\n  #endif\r\n\r\n#endif\r\n\r\n#include \"core_cmInstr.h\"                /* Core Instruction Access */\r\n#include \"core_cmFunc.h\"                 /* Core Function Access */\r\n#include \"core_cmSimd.h\"                 /* Compiler specific SIMD Intrinsics */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __CORE_CM7_H_GENERIC */\r\n\r\n#ifndef __CMSIS_GENERIC\r\n\r\n#ifndef __CORE_CM7_H_DEPENDANT\r\n#define __CORE_CM7_H_DEPENDANT\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* check device defines and use defaults */\r\n#if defined __CHECK_DEVICE_DEFINES\r\n  #ifndef __CM7_REV\r\n    #define __CM7_REV               0x0000U\r\n    #warning \"__CM7_REV not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __FPU_PRESENT\r\n    #define __FPU_PRESENT             0U\r\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __MPU_PRESENT\r\n    #define __MPU_PRESENT             0U\r\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __ICACHE_PRESENT\r\n    #define __ICACHE_PRESENT          0U\r\n    #warning \"__ICACHE_PRESENT not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __DCACHE_PRESENT\r\n    #define __DCACHE_PRESENT          0U\r\n    #warning \"__DCACHE_PRESENT not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __DTCM_PRESENT\r\n    #define __DTCM_PRESENT            0U\r\n    #warning \"__DTCM_PRESENT        not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __NVIC_PRIO_BITS\r\n    #define __NVIC_PRIO_BITS          3U\r\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __Vendor_SysTickConfig\r\n    #define __Vendor_SysTickConfig    0U\r\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\r\n  #endif\r\n#endif\r\n\r\n/* IO definitions (access restrictions to peripheral registers) */\r\n/**\r\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\r\n\r\n    <strong>IO Type Qualifiers</strong> are used\r\n    \\li to specify the access to peripheral variables.\r\n    \\li for automatic generation of peripheral register debug information.\r\n*/\r\n#ifdef __cplusplus\r\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\r\n#else\r\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r\n#endif\r\n#define     __O     volatile             /*!< Defines 'write only' permissions */\r\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r\n\r\n/* following defines should be used for structure members */\r\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r\n\r\n/*@} end of group Cortex_M7 */\r\n\r\n\r\n\r\n/*******************************************************************************\r\n *                 Register Abstraction\r\n  Core Register contain:\r\n  - Core Register\r\n  - Core NVIC Register\r\n  - Core SCB Register\r\n  - Core SysTick Register\r\n  - Core Debug Register\r\n  - Core MPU Register\r\n  - Core FPU Register\r\n ******************************************************************************/\r\n/**\r\n  \\defgroup CMSIS_core_register Defines and Type Definitions\r\n  \\brief Type definitions and defines for Cortex-M processor based devices.\r\n*/\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_CORE  Status and Control Registers\r\n  \\brief      Core Register type definitions.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Union type to access the Application Program Status Register (APSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\r\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\r\n    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\r\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} APSR_Type;\r\n\r\n/* APSR Register Definitions */\r\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r\n\r\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r\n\r\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r\n\r\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r\n\r\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\r\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\r\n\r\n#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\r\n#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} IPSR_Type;\r\n\r\n/* IPSR Register Definitions */\r\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r\n    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */\r\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\r\n    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\r\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\r\n    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */\r\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} xPSR_Type;\r\n\r\n/* xPSR Register Definitions */\r\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r\n\r\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r\n\r\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r\n\r\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r\n\r\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\r\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\r\n\r\n#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */\r\n#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */\r\n\r\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r\n\r\n#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\r\n#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\r\n\r\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Control Registers (CONTROL).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\r\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\r\n    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */\r\n    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} CONTROL_Type;\r\n\r\n/* CONTROL Register Definitions */\r\n#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\r\n#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\r\n\r\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r\n\r\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\r\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\r\n\r\n/*@} end of group CMSIS_CORE */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r\n  \\brief      Type definitions for the NVIC Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r\n        uint32_t RESERVED0[24U];\r\n  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r\n        uint32_t RSERVED1[24U];\r\n  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r\n        uint32_t RESERVED2[24U];\r\n  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r\n        uint32_t RESERVED3[24U];\r\n  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\r\n        uint32_t RESERVED4[56U];\r\n  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\r\n        uint32_t RESERVED5[644U];\r\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\r\n}  NVIC_Type;\r\n\r\n/* Software Triggered Interrupt Register Definitions */\r\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\r\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\r\n\r\n/*@} end of group CMSIS_NVIC */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\r\n  \\brief    Type definitions for the System Control Block Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Control Block (SCB).\r\n */\r\ntypedef struct\r\n{\r\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\r\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r\n  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\r\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\r\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\r\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\r\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\r\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\r\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\r\n  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */\r\n  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */\r\n  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\r\n  __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\r\n  __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\r\n        uint32_t RESERVED0[1U];\r\n  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */\r\n  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */\r\n  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */\r\n  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */\r\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\r\n        uint32_t RESERVED3[93U];\r\n  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */\r\n        uint32_t RESERVED4[15U];\r\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */\r\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */\r\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1 */\r\n        uint32_t RESERVED5[1U];\r\n  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */\r\n        uint32_t RESERVED6[1U];\r\n  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */\r\n  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */\r\n  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */\r\n  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */\r\n  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */\r\n  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */\r\n  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */\r\n  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */\r\n        uint32_t RESERVED7[6U];\r\n  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */\r\n  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */\r\n  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */\r\n  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */\r\n  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */\r\n        uint32_t RESERVED8[1U];\r\n  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */\r\n} SCB_Type;\r\n\r\n/* SCB CPUID Register Definitions */\r\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r\n\r\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r\n\r\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r\n\r\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r\n\r\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r\n\r\n/* SCB Interrupt Control State Register Definitions */\r\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\r\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\r\n\r\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r\n\r\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r\n\r\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r\n\r\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r\n\r\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r\n\r\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r\n\r\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r\n\r\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\r\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\r\n\r\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r\n\r\n/* SCB Vector Table Offset Register Definitions */\r\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\r\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\r\n\r\n/* SCB Application Interrupt and Reset Control Register Definitions */\r\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r\n\r\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r\n\r\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r\n\r\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\r\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\r\n\r\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r\n\r\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r\n\r\n#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\r\n#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\r\n\r\n/* SCB System Control Register Definitions */\r\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r\n\r\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r\n\r\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r\n\r\n/* SCB Configuration Control Register Definitions */\r\n#define SCB_CCR_BP_Pos                      18U                                           /*!< SCB CCR: Branch prediction enable bit Position */\r\n#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */\r\n\r\n#define SCB_CCR_IC_Pos                      17U                                           /*!< SCB CCR: Instruction cache enable bit Position */\r\n#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */\r\n\r\n#define SCB_CCR_DC_Pos                      16U                                           /*!< SCB CCR: Cache enable bit Position */\r\n#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */\r\n\r\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\r\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\r\n\r\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\r\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\r\n\r\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\r\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\r\n\r\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r\n\r\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\r\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\r\n\r\n#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\r\n#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\r\n\r\n/* SCB System Handler Control and State Register Definitions */\r\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\r\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\r\n\r\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\r\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\r\n\r\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\r\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\r\n\r\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r\n\r\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\r\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r\n\r\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\r\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r\n\r\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\r\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\r\n\r\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\r\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\r\n\r\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\r\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\r\n\r\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\r\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\r\n\r\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\r\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\r\n\r\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\r\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\r\n\r\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\r\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\r\n\r\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\r\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\r\n\r\n/* SCB Configurable Fault Status Register Definitions */\r\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\r\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\r\n\r\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\r\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\r\n\r\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r\n\r\n/* SCB Hard Fault Status Register Definitions */\r\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\r\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\r\n\r\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\r\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\r\n\r\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\r\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\r\n\r\n/* SCB Debug Fault Status Register Definitions */\r\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\r\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\r\n\r\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\r\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\r\n\r\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\r\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\r\n\r\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\r\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\r\n\r\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\r\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\r\n\r\n/* SCB Cache Level ID Register Definitions */\r\n#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */\r\n#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */\r\n\r\n#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */\r\n#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */\r\n\r\n/* SCB Cache Type Register Definitions */\r\n#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */\r\n#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */\r\n\r\n#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */\r\n#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */\r\n\r\n#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */\r\n#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */\r\n\r\n#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */\r\n#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */\r\n\r\n#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */\r\n#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */\r\n\r\n/* SCB Cache Size ID Register Definitions */\r\n#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */\r\n#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */\r\n\r\n#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */\r\n#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */\r\n\r\n#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */\r\n#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */\r\n\r\n#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */\r\n#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */\r\n\r\n#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */\r\n#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */\r\n\r\n#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */\r\n#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */\r\n\r\n#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */\r\n#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */\r\n\r\n/* SCB Cache Size Selection Register Definitions */\r\n#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */\r\n#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */\r\n\r\n#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */\r\n#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */\r\n\r\n/* SCB Software Triggered Interrupt Register Definitions */\r\n#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */\r\n#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */\r\n\r\n/* SCB D-Cache Invalidate by Set-way Register Definitions */\r\n#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */\r\n#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */\r\n\r\n#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */\r\n#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */\r\n\r\n/* SCB D-Cache Clean by Set-way Register Definitions */\r\n#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */\r\n#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */\r\n\r\n#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */\r\n#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */\r\n\r\n/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\r\n#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */\r\n#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */\r\n\r\n#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */\r\n#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */\r\n\r\n/* Instruction Tightly-Coupled Memory Control Register Definitions */\r\n#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */\r\n#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */\r\n\r\n#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */\r\n#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */\r\n\r\n#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */\r\n#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */\r\n\r\n#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */\r\n#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */\r\n\r\n/* Data Tightly-Coupled Memory Control Register Definitions */\r\n#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */\r\n#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */\r\n\r\n#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */\r\n#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */\r\n\r\n#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */\r\n#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */\r\n\r\n#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */\r\n#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */\r\n\r\n/* AHBP Control Register Definitions */\r\n#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */\r\n#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */\r\n\r\n#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */\r\n#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */\r\n\r\n/* L1 Cache Control Register Definitions */\r\n#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */\r\n#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */\r\n\r\n#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */\r\n#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */\r\n\r\n#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */\r\n#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */\r\n\r\n/* AHBS Control Register Definitions */\r\n#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */\r\n#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */\r\n\r\n#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */\r\n#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */\r\n\r\n#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/\r\n#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */\r\n\r\n/* Auxiliary Bus Fault Status Register Definitions */\r\n#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/\r\n#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */\r\n\r\n#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/\r\n#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */\r\n\r\n#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/\r\n#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */\r\n\r\n#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/\r\n#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */\r\n\r\n#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/\r\n#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */\r\n\r\n#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/\r\n#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */\r\n\r\n/*@} end of group CMSIS_SCB */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\r\n */\r\ntypedef struct\r\n{\r\n        uint32_t RESERVED0[1U];\r\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\r\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\r\n} SCnSCB_Type;\r\n\r\n/* Interrupt Controller Type Register Definitions */\r\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\r\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\r\n\r\n/* Auxiliary Control Register Definitions */\r\n#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: DISITMATBFLUSH Position */\r\n#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */\r\n\r\n#define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: DISRAMODE Position */\r\n#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */\r\n\r\n#define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: FPEXCODIS Position */\r\n#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */\r\n\r\n#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */\r\n#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */\r\n\r\n#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\r\n#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\r\n\r\n/*@} end of group CMSIS_SCnotSCB */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r\n  \\brief    Type definitions for the System Timer Registers.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Timer (SysTick).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r\n} SysTick_Type;\r\n\r\n/* SysTick Control / Status Register Definitions */\r\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r\n\r\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r\n\r\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r\n\r\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r\n\r\n/* SysTick Reload Register Definitions */\r\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r\n\r\n/* SysTick Current Register Definitions */\r\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r\n\r\n/* SysTick Calibration Register Definitions */\r\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r\n\r\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r\n\r\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r\n\r\n/*@} end of group CMSIS_SysTick */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\r\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r\n */\r\ntypedef struct\r\n{\r\n  __OM  union\r\n  {\r\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\r\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\r\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\r\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\r\n        uint32_t RESERVED0[864U];\r\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\r\n        uint32_t RESERVED1[15U];\r\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\r\n        uint32_t RESERVED2[15U];\r\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\r\n        uint32_t RESERVED3[29U];\r\n  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\r\n  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\r\n  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\r\n        uint32_t RESERVED4[43U];\r\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\r\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\r\n        uint32_t RESERVED5[6U];\r\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\r\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\r\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\r\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\r\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\r\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\r\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\r\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\r\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\r\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\r\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\r\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\r\n} ITM_Type;\r\n\r\n/* ITM Trace Privilege Register Definitions */\r\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\r\n#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */\r\n\r\n/* ITM Trace Control Register Definitions */\r\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\r\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\r\n\r\n#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\r\n#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */\r\n\r\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\r\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\r\n\r\n#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\r\n#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\r\n\r\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\r\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\r\n\r\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\r\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\r\n\r\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\r\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\r\n\r\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\r\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\r\n\r\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\r\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\r\n\r\n/* ITM Integration Write Register Definitions */\r\n#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */\r\n#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\r\n\r\n/* ITM Integration Read Register Definitions */\r\n#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */\r\n#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\r\n\r\n/* ITM Integration Mode Control Register Definitions */\r\n#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */\r\n#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\r\n\r\n/* ITM Lock Status Register Definitions */\r\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\r\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\r\n\r\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\r\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\r\n\r\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\r\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\r\n\r\n/*@}*/ /* end of group CMSIS_ITM */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\r\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\r\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\r\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\r\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\r\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\r\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\r\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\r\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\r\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\r\n  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\r\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\r\n        uint32_t RESERVED0[1U];\r\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\r\n  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\r\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\r\n        uint32_t RESERVED1[1U];\r\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\r\n  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\r\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\r\n        uint32_t RESERVED2[1U];\r\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\r\n  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\r\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\r\n        uint32_t RESERVED3[981U];\r\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */\r\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */\r\n} DWT_Type;\r\n\r\n/* DWT Control Register Definitions */\r\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\r\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\r\n\r\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\r\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\r\n\r\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\r\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\r\n\r\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\r\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\r\n\r\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\r\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\r\n\r\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\r\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\r\n\r\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\r\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\r\n\r\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\r\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\r\n\r\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\r\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\r\n\r\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\r\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\r\n\r\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\r\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\r\n\r\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\r\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\r\n\r\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\r\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\r\n\r\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\r\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\r\n\r\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\r\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\r\n\r\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\r\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\r\n\r\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\r\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\r\n\r\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\r\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\r\n\r\n/* DWT CPI Count Register Definitions */\r\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\r\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\r\n\r\n/* DWT Exception Overhead Count Register Definitions */\r\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\r\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\r\n\r\n/* DWT Sleep Count Register Definitions */\r\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\r\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r\n\r\n/* DWT LSU Count Register Definitions */\r\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\r\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\r\n\r\n/* DWT Folded-instruction Count Register Definitions */\r\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\r\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\r\n\r\n/* DWT Comparator Mask Register Definitions */\r\n#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\r\n#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\r\n\r\n/* DWT Comparator Function Register Definitions */\r\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\r\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\r\n\r\n#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\r\n#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\r\n\r\n#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\r\n#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\r\n\r\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\r\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\r\n\r\n#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\r\n#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\r\n\r\n#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\r\n#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\r\n\r\n#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\r\n#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\r\n\r\n#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\r\n#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\r\n\r\n#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\r\n#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\r\n\r\n/*@}*/ /* end of group CMSIS_DWT */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\r\n  \\brief    Type definitions for the Trace Port Interface (TPI)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\r\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\r\n        uint32_t RESERVED0[2U];\r\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\r\n        uint32_t RESERVED1[55U];\r\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\r\n        uint32_t RESERVED2[131U];\r\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\r\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\r\n  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\r\n        uint32_t RESERVED3[759U];\r\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */\r\n  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\r\n  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\r\n        uint32_t RESERVED4[1U];\r\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\r\n  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\r\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\r\n        uint32_t RESERVED5[39U];\r\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\r\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\r\n        uint32_t RESERVED7[8U];\r\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\r\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\r\n} TPI_Type;\r\n\r\n/* TPI Asynchronous Clock Prescaler Register Definitions */\r\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\r\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\r\n\r\n/* TPI Selected Pin Protocol Register Definitions */\r\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\r\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\r\n\r\n/* TPI Formatter and Flush Status Register Definitions */\r\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\r\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\r\n\r\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\r\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\r\n\r\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\r\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\r\n\r\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\r\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\r\n\r\n/* TPI Formatter and Flush Control Register Definitions */\r\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\r\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\r\n\r\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\r\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\r\n\r\n/* TPI TRIGGER Register Definitions */\r\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\r\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\r\n\r\n/* TPI Integration ETM Data Register Definitions (FIFO0) */\r\n#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\r\n#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\r\n\r\n#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\r\n#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\r\n\r\n#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\r\n#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\r\n\r\n#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\r\n#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\r\n\r\n#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\r\n#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\r\n\r\n#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\r\n#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\r\n\r\n#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\r\n#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\r\n\r\n/* TPI ITATBCTR2 Register Definitions */\r\n#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */\r\n#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */\r\n\r\n/* TPI Integration ITM Data Register Definitions (FIFO1) */\r\n#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\r\n#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\r\n\r\n#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\r\n#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\r\n\r\n#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\r\n#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\r\n\r\n#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\r\n#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\r\n\r\n#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\r\n#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\r\n\r\n#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\r\n#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\r\n\r\n#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\r\n#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\r\n\r\n/* TPI ITATBCTR0 Register Definitions */\r\n#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */\r\n#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */\r\n\r\n/* TPI Integration Mode Control Register Definitions */\r\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\r\n#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\r\n\r\n/* TPI DEVID Register Definitions */\r\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\r\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\r\n\r\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\r\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\r\n\r\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\r\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\r\n\r\n#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\r\n#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\r\n\r\n#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\r\n#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\r\n\r\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\r\n#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\r\n\r\n/* TPI DEVTYPE Register Definitions */\r\n#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */\r\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\r\n\r\n#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */\r\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\r\n\r\n/*@}*/ /* end of group CMSIS_TPI */\r\n\r\n\r\n#if (__MPU_PRESENT == 1U)\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\r\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\r\n */\r\ntypedef struct\r\n{\r\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\r\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\r\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\r\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\r\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\r\n  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\r\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\r\n  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\r\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\r\n  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\r\n} MPU_Type;\r\n\r\n/* MPU Type Register Definitions */\r\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\r\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r\n\r\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\r\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r\n\r\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\r\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\r\n\r\n/* MPU Control Register Definitions */\r\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\r\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r\n\r\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\r\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r\n\r\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\r\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\r\n\r\n/* MPU Region Number Register Definitions */\r\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\r\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\r\n\r\n/* MPU Region Base Address Register Definitions */\r\n#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\r\n#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\r\n\r\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\r\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\r\n\r\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\r\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\r\n\r\n/* MPU Region Attribute and Size Register Definitions */\r\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\r\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\r\n\r\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\r\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\r\n\r\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\r\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\r\n\r\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\r\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\r\n\r\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\r\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\r\n\r\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\r\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\r\n\r\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\r\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\r\n\r\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\r\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\r\n\r\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\r\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\r\n\r\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\r\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\r\n\r\n/*@} end of group CMSIS_MPU */\r\n#endif\r\n\r\n\r\n#if (__FPU_PRESENT == 1U)\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_FPU     Floating Point Unit (FPU)\r\n  \\brief    Type definitions for the Floating Point Unit (FPU)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Floating Point Unit (FPU).\r\n */\r\ntypedef struct\r\n{\r\n        uint32_t RESERVED0[1U];\r\n  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\r\n  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\r\n  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\r\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */\r\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */\r\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */\r\n} FPU_Type;\r\n\r\n/* Floating-Point Context Control Register Definitions */\r\n#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\r\n#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\r\n\r\n#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\r\n#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\r\n\r\n#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\r\n#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\r\n\r\n#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\r\n#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\r\n\r\n#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\r\n#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\r\n\r\n#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\r\n#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\r\n\r\n#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\r\n#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\r\n\r\n#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\r\n#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\r\n\r\n#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\r\n#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\r\n\r\n/* Floating-Point Context Address Register Definitions */\r\n#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\r\n#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\r\n\r\n/* Floating-Point Default Status Control Register Definitions */\r\n#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\r\n#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\r\n\r\n#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\r\n#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\r\n\r\n#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\r\n#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\r\n\r\n#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\r\n#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\r\n\r\n/* Media and FP Feature Register 0 Definitions */\r\n#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */\r\n#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */\r\n\r\n#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */\r\n#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */\r\n\r\n#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */\r\n#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */\r\n\r\n#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */\r\n#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */\r\n\r\n#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */\r\n#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */\r\n\r\n#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */\r\n#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */\r\n\r\n#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */\r\n#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */\r\n\r\n#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */\r\n#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */\r\n\r\n/* Media and FP Feature Register 1 Definitions */\r\n#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */\r\n#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */\r\n\r\n#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */\r\n#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */\r\n\r\n#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */\r\n#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */\r\n\r\n#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */\r\n#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */\r\n\r\n/* Media and FP Feature Register 2 Definitions */\r\n\r\n/*@} end of group CMSIS_FPU */\r\n#endif\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r\n  \\brief    Type definitions for the Core Debug Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\r\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\r\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\r\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\r\n} CoreDebug_Type;\r\n\r\n/* Debug Halting Control and Status Register Definitions */\r\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\r\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\r\n\r\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\r\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r\n\r\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r\n\r\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\r\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r\n\r\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\r\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\r\n\r\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\r\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\r\n\r\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\r\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\r\n\r\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r\n\r\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\r\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r\n\r\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\r\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\r\n\r\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\r\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\r\n\r\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r\n\r\n/* Debug Core Register Selector Register Definitions */\r\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\r\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\r\n\r\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\r\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\r\n\r\n/* Debug Exception and Monitor Control Register Definitions */\r\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\r\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\r\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\r\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\r\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\r\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\r\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\r\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\r\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\r\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\r\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\r\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\r\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r\n\r\n/*@} end of group CMSIS_CoreDebug */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\r\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief   Mask and shift a bit field value for use in a register bit range.\r\n  \\param[in] field  Name of the register bit field.\r\n  \\param[in] value  Value of the bit field.\r\n  \\return           Masked and shifted value.\r\n*/\r\n#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)\r\n\r\n/**\r\n  \\brief     Mask and shift a register value to extract a bit filed value.\r\n  \\param[in] field  Name of the register bit field.\r\n  \\param[in] value  Value of register.\r\n  \\return           Masked and shifted bit field value.\r\n*/\r\n#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)\r\n\r\n/*@} end of group CMSIS_core_bitfield */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_core_base     Core Definitions\r\n  \\brief      Definitions for base addresses, unions, and structures.\r\n  @{\r\n */\r\n\r\n/* Memory mapping of Cortex-M4 Hardware */\r\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\r\n#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\r\n#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\r\n#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\r\n#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\r\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\r\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\r\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\r\n\r\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\r\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\r\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\r\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\r\n#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\r\n#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\r\n#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\r\n#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\r\n\r\n#if (__MPU_PRESENT == 1U)\r\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\r\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\r\n#endif\r\n\r\n#if (__FPU_PRESENT == 1U)\r\n  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */\r\n  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */\r\n#endif\r\n\r\n/*@} */\r\n\r\n\r\n\r\n/*******************************************************************************\r\n *                Hardware Abstraction Layer\r\n  Core Function Interface contains:\r\n  - Core NVIC Functions\r\n  - Core SysTick Functions\r\n  - Core Debug Functions\r\n  - Core Register Access Functions\r\n ******************************************************************************/\r\n/**\r\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r\n*/\r\n\r\n\r\n\r\n/* ##########################   NVIC functions  #################################### */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\r\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief   Set Priority Grouping\r\n  \\details Sets the priority grouping field using the required unlock sequence.\r\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r\n           Only values from 0..7 are used.\r\n           In case of a conflict between priority grouping and available\r\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r\n  \\param [in]      PriorityGroup  Priority grouping field.\r\n */\r\n__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r\n{\r\n  uint32_t reg_value;\r\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\r\n\r\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\r\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\r\n  reg_value  =  (reg_value                                   |\r\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r\n                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */\r\n  SCB->AIRCR =  reg_value;\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Priority Grouping\r\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\r\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r\n{\r\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Enable External Interrupt\r\n  \\details Enables a device-specific interrupt in the NVIC interrupt controller.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Disable External Interrupt\r\n  \\details Disables a device-specific interrupt in the NVIC interrupt controller.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Pending Interrupt\r\n  \\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\return             0  Interrupt status is not pending.\r\n  \\return             1  Interrupt status is pending.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Pending Interrupt\r\n  \\details Sets the pending bit of an external interrupt.\r\n  \\param [in]      IRQn  Interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Clear Pending Interrupt\r\n  \\details Clears the pending bit of an external interrupt.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Active Interrupt\r\n  \\details Reads the active register in NVIC and returns the active bit.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\return             0  Interrupt status is not active.\r\n  \\return             1  Interrupt status is active.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r\n{\r\n  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Interrupt Priority\r\n  \\details Sets the priority of an interrupt.\r\n  \\note    The priority cannot be set for every core interrupt.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\param [in]  priority  Priority to set.\r\n */\r\n__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r\n{\r\n  if ((int32_t)(IRQn) < 0)\r\n  {\r\n    SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r\n  }\r\n  else\r\n  {\r\n    NVIC->IP[((uint32_t)(int32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Interrupt Priority\r\n  \\details Reads the priority of an interrupt.\r\n           The interrupt number can be positive to specify an external (device specific) interrupt,\r\n           or negative to specify an internal (core) interrupt.\r\n  \\param [in]   IRQn  Interrupt number.\r\n  \\return             Interrupt Priority.\r\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r\n{\r\n\r\n  if ((int32_t)(IRQn) < 0)\r\n  {\r\n    return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r\n  }\r\n  else\r\n  {\r\n    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Encode Priority\r\n  \\details Encodes the priority for an interrupt with the given priority group,\r\n           preemptive priority value, and subpriority value.\r\n           In case of a conflict between priority grouping and available\r\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r\n  \\param [in]     PriorityGroup  Used priority group.\r\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\r\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\r\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\r\n */\r\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r\n{\r\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r\n  uint32_t PreemptPriorityBits;\r\n  uint32_t SubPriorityBits;\r\n\r\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r\n\r\n  return (\r\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\r\n         );\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Decode Priority\r\n  \\details Decodes an interrupt priority value with a given priority group to\r\n           preemptive priority value and subpriority value.\r\n           In case of a conflict between priority grouping and available\r\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\r\n  \\param [in]     PriorityGroup  Used priority group.\r\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\r\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\r\n */\r\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r\n{\r\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r\n  uint32_t PreemptPriorityBits;\r\n  uint32_t SubPriorityBits;\r\n\r\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r\n\r\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   System Reset\r\n  \\details Initiates a system reset request to reset the MCU.\r\n */\r\n__STATIC_INLINE void NVIC_SystemReset(void)\r\n{\r\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\r\n                                                                       buffered write are completed before reset */\r\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\r\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\r\n  __DSB();                                                          /* Ensure completion of memory access */\r\n\r\n  for(;;)                                                           /* wait until reset */\r\n  {\r\n    __NOP();\r\n  }\r\n}\r\n\r\n/*@} end of CMSIS_Core_NVICFunctions */\r\n\r\n\r\n/* ##########################  FPU functions  #################################### */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\r\n  \\brief    Function that provides FPU type.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief   get FPU type\r\n  \\details returns the FPU type\r\n  \\returns\r\n   - \\b  0: No FPU\r\n   - \\b  1: Single precision FPU\r\n   - \\b  2: Double + Single precision FPU\r\n */\r\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r\n{\r\n  uint32_t mvfr0;\r\n\r\n  mvfr0 = SCB->MVFR0;\r\n  if        ((mvfr0 & 0x00000FF0UL) == 0x220UL)\r\n  {\r\n    return 2UL;           /* Double + Single precision FPU */\r\n  }\r\n  else if ((mvfr0 & 0x00000FF0UL) == 0x020UL)\r\n  {\r\n    return 1UL;           /* Single precision FPU */\r\n  }\r\n  else\r\n  {\r\n    return 0UL;           /* No FPU */\r\n  }\r\n}\r\n\r\n\r\n/*@} end of CMSIS_Core_FpuFunctions */\r\n\r\n\r\n\r\n/* ##########################  Cache functions  #################################### */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_CacheFunctions Cache Functions\r\n  \\brief    Functions that configure Instruction and Data cache.\r\n  @{\r\n */\r\n\r\n/* Cache Size ID Register Macros */\r\n#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)\r\n#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )\r\n\r\n\r\n/**\r\n  \\brief   Enable I-Cache\r\n  \\details Turns on I-Cache\r\n  */\r\n__STATIC_INLINE void SCB_EnableICache (void)\r\n{\r\n  #if (__ICACHE_PRESENT == 1U)\r\n    __DSB();\r\n    __ISB();\r\n    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */\r\n    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */\r\n    __DSB();\r\n    __ISB();\r\n  #endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Disable I-Cache\r\n  \\details Turns off I-Cache\r\n  */\r\n__STATIC_INLINE void SCB_DisableICache (void)\r\n{\r\n  #if (__ICACHE_PRESENT == 1U)\r\n    __DSB();\r\n    __ISB();\r\n    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */\r\n    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */\r\n    __DSB();\r\n    __ISB();\r\n  #endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Invalidate I-Cache\r\n  \\details Invalidates I-Cache\r\n  */\r\n__STATIC_INLINE void SCB_InvalidateICache (void)\r\n{\r\n  #if (__ICACHE_PRESENT == 1U)\r\n    __DSB();\r\n    __ISB();\r\n    SCB->ICIALLU = 0UL;\r\n    __DSB();\r\n    __ISB();\r\n  #endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Enable D-Cache\r\n  \\details Turns on D-Cache\r\n  */\r\n__STATIC_INLINE void SCB_EnableDCache (void)\r\n{\r\n  #if (__DCACHE_PRESENT == 1U)\r\n    uint32_t ccsidr;\r\n    uint32_t sets;\r\n    uint32_t ways;\r\n\r\n    SCB->CSSELR = (0U << 1U) | 0U;          /* Level 1 data cache */\r\n    __DSB();\r\n\r\n    ccsidr = SCB->CCSIDR;\r\n\r\n                                            /* invalidate D-Cache */\r\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r\n    do {\r\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r\n      do {\r\n        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\r\n                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );\r\n        #if defined ( __CC_ARM )\r\n          __schedule_barrier();\r\n        #endif\r\n      } while (ways--);\r\n    } while(sets--);\r\n    __DSB();\r\n\r\n    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */\r\n\r\n    __DSB();\r\n    __ISB();\r\n  #endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Disable D-Cache\r\n  \\details Turns off D-Cache\r\n  */\r\n__STATIC_INLINE void SCB_DisableDCache (void)\r\n{\r\n  #if (__DCACHE_PRESENT == 1U)\r\n    uint32_t ccsidr;\r\n    uint32_t sets;\r\n    uint32_t ways;\r\n\r\n    SCB->CSSELR = (0U << 1U) | 0U;          /* Level 1 data cache */\r\n    __DSB();\r\n\r\n    ccsidr = SCB->CCSIDR;\r\n\r\n    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */\r\n\r\n                                            /* clean & invalidate D-Cache */\r\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r\n    do {\r\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r\n      do {\r\n        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\r\n                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );\r\n        #if defined ( __CC_ARM )\r\n          __schedule_barrier();\r\n        #endif\r\n      } while (ways--);\r\n    } while(sets--);\r\n\r\n    __DSB();\r\n    __ISB();\r\n  #endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Invalidate D-Cache\r\n  \\details Invalidates D-Cache\r\n  */\r\n__STATIC_INLINE void SCB_InvalidateDCache (void)\r\n{\r\n  #if (__DCACHE_PRESENT == 1U)\r\n    uint32_t ccsidr;\r\n    uint32_t sets;\r\n    uint32_t ways;\r\n\r\n    SCB->CSSELR = (0U << 1U) | 0U;          /* Level 1 data cache */\r\n    __DSB();\r\n\r\n    ccsidr = SCB->CCSIDR;\r\n\r\n                                            /* invalidate D-Cache */\r\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r\n    do {\r\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r\n      do {\r\n        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\r\n                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );\r\n        #if defined ( __CC_ARM )\r\n          __schedule_barrier();\r\n        #endif\r\n      } while (ways--);\r\n    } while(sets--);\r\n\r\n    __DSB();\r\n    __ISB();\r\n  #endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Clean D-Cache\r\n  \\details Cleans D-Cache\r\n  */\r\n__STATIC_INLINE void SCB_CleanDCache (void)\r\n{\r\n  #if (__DCACHE_PRESENT == 1U)\r\n    uint32_t ccsidr;\r\n    uint32_t sets;\r\n    uint32_t ways;\r\n\r\n    SCB->CSSELR = (0U << 1U) | 0U;          /* Level 1 data cache */\r\n    __DSB();\r\n\r\n    ccsidr = SCB->CCSIDR;\r\n\r\n                                            /* clean D-Cache */\r\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r\n    do {\r\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r\n      do {\r\n        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |\r\n                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );\r\n        #if defined ( __CC_ARM )\r\n          __schedule_barrier();\r\n        #endif\r\n      } while (ways--);\r\n    } while(sets--);\r\n\r\n    __DSB();\r\n    __ISB();\r\n  #endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Clean & Invalidate D-Cache\r\n  \\details Cleans and Invalidates D-Cache\r\n  */\r\n__STATIC_INLINE void SCB_CleanInvalidateDCache (void)\r\n{\r\n  #if (__DCACHE_PRESENT == 1U)\r\n    uint32_t ccsidr;\r\n    uint32_t sets;\r\n    uint32_t ways;\r\n\r\n    SCB->CSSELR = (0U << 1U) | 0U;          /* Level 1 data cache */\r\n    __DSB();\r\n\r\n    ccsidr = SCB->CCSIDR;\r\n\r\n                                            /* clean & invalidate D-Cache */\r\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r\n    do {\r\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r\n      do {\r\n        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\r\n                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );\r\n        #if defined ( __CC_ARM )\r\n          __schedule_barrier();\r\n        #endif\r\n      } while (ways--);\r\n    } while(sets--);\r\n\r\n    __DSB();\r\n    __ISB();\r\n  #endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   D-Cache Invalidate by address\r\n  \\details Invalidates D-Cache for the given address\r\n  \\param[in]   addr    address (aligned to 32-byte boundary)\r\n  \\param[in]   dsize   size of memory block (in number of bytes)\r\n*/\r\n__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)\r\n{\r\n  #if (__DCACHE_PRESENT == 1U)\r\n     int32_t op_size = dsize;\r\n    uint32_t op_addr = (uint32_t)addr;\r\n     int32_t linesize = 32U;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r\n\r\n    __DSB();\r\n\r\n    while (op_size > 0) {\r\n      SCB->DCIMVAC = op_addr;\r\n      op_addr += linesize;\r\n      op_size -= linesize;\r\n    }\r\n\r\n    __DSB();\r\n    __ISB();\r\n  #endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   D-Cache Clean by address\r\n  \\details Cleans D-Cache for the given address\r\n  \\param[in]   addr    address (aligned to 32-byte boundary)\r\n  \\param[in]   dsize   size of memory block (in number of bytes)\r\n*/\r\n__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)\r\n{\r\n  #if (__DCACHE_PRESENT == 1)\r\n     int32_t op_size = dsize;\r\n    uint32_t op_addr = (uint32_t) addr;\r\n     int32_t linesize = 32U;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r\n\r\n    __DSB();\r\n\r\n    while (op_size > 0) {\r\n      SCB->DCCMVAC = op_addr;\r\n      op_addr += linesize;\r\n      op_size -= linesize;\r\n    }\r\n\r\n    __DSB();\r\n    __ISB();\r\n  #endif\r\n}\r\n\r\n\r\n/**\r\n  \\brief   D-Cache Clean and Invalidate by address\r\n  \\details Cleans and invalidates D_Cache for the given address\r\n  \\param[in]   addr    address (aligned to 32-byte boundary)\r\n  \\param[in]   dsize   size of memory block (in number of bytes)\r\n*/\r\n__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)\r\n{\r\n  #if (__DCACHE_PRESENT == 1U)\r\n     int32_t op_size = dsize;\r\n    uint32_t op_addr = (uint32_t) addr;\r\n     int32_t linesize = 32U;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r\n\r\n    __DSB();\r\n\r\n    while (op_size > 0) {\r\n      SCB->DCCIMVAC = op_addr;\r\n      op_addr += linesize;\r\n      op_size -= linesize;\r\n    }\r\n\r\n    __DSB();\r\n    __ISB();\r\n  #endif\r\n}\r\n\r\n\r\n/*@} end of CMSIS_Core_CacheFunctions */\r\n\r\n\r\n\r\n/* ##################################    SysTick function  ############################################ */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r\n  \\brief    Functions that configure the System.\r\n  @{\r\n */\r\n\r\n#if (__Vendor_SysTickConfig == 0U)\r\n\r\n/**\r\n  \\brief   System Tick Configuration\r\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r\n           Counter is in free running mode to generate periodic interrupts.\r\n  \\param [in]  ticks  Number of ticks between two interrupts.\r\n  \\return          0  Function succeeded.\r\n  \\return          1  Function failed.\r\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r\n           must contain a vendor-specific implementation of this function.\r\n */\r\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r\n{\r\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r\n  {\r\n    return (1UL);                                                   /* Reload value impossible */\r\n  }\r\n\r\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r\n                   SysTick_CTRL_TICKINT_Msk   |\r\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r\n  return (0UL);                                                     /* Function successful */\r\n}\r\n\r\n#endif\r\n\r\n/*@} end of CMSIS_Core_SysTickFunctions */\r\n\r\n\r\n\r\n/* ##################################### Debug In/Output function ########################################### */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\r\n  \\brief    Functions that access the ITM debug interface.\r\n  @{\r\n */\r\n\r\nextern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters. */\r\n#define                 ITM_RXBUFFER_EMPTY   0x5AA55AA5U /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\r\n\r\n\r\n/**\r\n  \\brief   ITM Send Character\r\n  \\details Transmits a character via the ITM channel 0, and\r\n           \\li Just returns when no debugger is connected that has booked the output.\r\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r\n  \\param [in]     ch  Character to transmit.\r\n  \\returns            Character to transmit.\r\n */\r\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r\n{\r\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\r\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\r\n  {\r\n    while (ITM->PORT[0U].u32 == 0UL)\r\n    {\r\n      __NOP();\r\n    }\r\n    ITM->PORT[0U].u8 = (uint8_t)ch;\r\n  }\r\n  return (ch);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   ITM Receive Character\r\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\r\n  \\return             Received character.\r\n  \\return         -1  No character pending.\r\n */\r\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r\n{\r\n  int32_t ch = -1;                           /* no character available */\r\n\r\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r\n  {\r\n    ch = ITM_RxBuffer;\r\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\r\n  }\r\n\r\n  return (ch);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   ITM Check Character\r\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\r\n  \\return          0  No character available.\r\n  \\return          1  Character available.\r\n */\r\n__STATIC_INLINE int32_t ITM_CheckChar (void)\r\n{\r\n\r\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r\n  {\r\n    return (0);                              /* no character available */\r\n  }\r\n  else\r\n  {\r\n    return (1);                              /*    character available */\r\n  }\r\n}\r\n\r\n/*@} end of CMSIS_core_DebugFunctions */\r\n\r\n\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __CORE_CM7_H_DEPENDANT */\r\n\r\n#endif /* __CMSIS_GENERIC */\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/include/core_cmFunc.h",
    "content": "/**************************************************************************//**\r\n * @file     core_cmFunc.h\r\n * @brief    CMSIS Cortex-M Core Function Access Header File\r\n * @version  V4.30\r\n * @date     20. October 2015\r\n ******************************************************************************/\r\n/* Copyright (c) 2009 - 2015 ARM LIMITED\r\n\r\n   All rights reserved.\r\n   Redistribution and use in source and binary forms, with or without\r\n   modification, are permitted provided that the following conditions are met:\r\n   - Redistributions of source code must retain the above copyright\r\n     notice, this list of conditions and the following disclaimer.\r\n   - Redistributions in binary form must reproduce the above copyright\r\n     notice, this list of conditions and the following disclaimer in the\r\n     documentation and/or other materials provided with the distribution.\r\n   - Neither the name of ARM nor the names of its contributors may be used\r\n     to endorse or promote products derived from this software without\r\n     specific prior written permission.\r\n   *\r\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n   POSSIBILITY OF SUCH DAMAGE.\r\n   ---------------------------------------------------------------------------*/\r\n\r\n\r\n#if   defined ( __ICCARM__ )\r\n #pragma system_include         /* treat file as system include file for MISRA check */\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #pragma clang system_header   /* treat file as system include file */\r\n#endif\r\n\r\n#ifndef __CORE_CMFUNC_H\r\n#define __CORE_CMFUNC_H\r\n\r\n\r\n/* ###########################  Core Function Access  ########################### */\r\n/** \\ingroup  CMSIS_Core_FunctionInterface\r\n    \\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r\n  @{\r\n*/\r\n\r\n/*------------------ RealView Compiler -----------------*/\r\n#if   defined ( __CC_ARM )\r\n  #include \"cmsis_armcc.h\"\r\n\r\n/*------------------ ARM Compiler V6 -------------------*/\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #include \"cmsis_armcc_V6.h\"\r\n\r\n/*------------------ GNU Compiler ----------------------*/\r\n#elif defined ( __GNUC__ )\r\n  #include \"cmsis_gcc.h\"\r\n\r\n/*------------------ ICC Compiler ----------------------*/\r\n#elif defined ( __ICCARM__ )\r\n  #include <cmsis_iar.h>\r\n\r\n/*------------------ TI CCS Compiler -------------------*/\r\n#elif defined ( __TMS470__ )\r\n  #include <cmsis_ccs.h>\r\n\r\n/*------------------ TASKING Compiler ------------------*/\r\n#elif defined ( __TASKING__ )\r\n  /*\r\n   * The CMSIS functions have been implemented as intrinsics in the compiler.\r\n   * Please use \"carm -?i\" to get an up to date list of all intrinsics,\r\n   * Including the CMSIS ones.\r\n   */\r\n\r\n/*------------------ COSMIC Compiler -------------------*/\r\n#elif defined ( __CSMC__ )\r\n  #include <cmsis_csm.h>\r\n\r\n#endif\r\n\r\n/*@} end of CMSIS_Core_RegAccFunctions */\r\n\r\n#endif /* __CORE_CMFUNC_H */\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/include/core_cmInstr.h",
    "content": "/**************************************************************************//**\r\n * @file     core_cmInstr.h\r\n * @brief    CMSIS Cortex-M Core Instruction Access Header File\r\n * @version  V4.30\r\n * @date     20. October 2015\r\n ******************************************************************************/\r\n/* Copyright (c) 2009 - 2015 ARM LIMITED\r\n\r\n   All rights reserved.\r\n   Redistribution and use in source and binary forms, with or without\r\n   modification, are permitted provided that the following conditions are met:\r\n   - Redistributions of source code must retain the above copyright\r\n     notice, this list of conditions and the following disclaimer.\r\n   - Redistributions in binary form must reproduce the above copyright\r\n     notice, this list of conditions and the following disclaimer in the\r\n     documentation and/or other materials provided with the distribution.\r\n   - Neither the name of ARM nor the names of its contributors may be used\r\n     to endorse or promote products derived from this software without\r\n     specific prior written permission.\r\n   *\r\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n   POSSIBILITY OF SUCH DAMAGE.\r\n   ---------------------------------------------------------------------------*/\r\n\r\n\r\n#if   defined ( __ICCARM__ )\r\n #pragma system_include         /* treat file as system include file for MISRA check */\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #pragma clang system_header   /* treat file as system include file */\r\n#endif\r\n\r\n#ifndef __CORE_CMINSTR_H\r\n#define __CORE_CMINSTR_H\r\n\r\n\r\n/* ##########################  Core Instruction Access  ######################### */\r\n/** \\defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r\n  Access to dedicated instructions\r\n  @{\r\n*/\r\n\r\n/*------------------ RealView Compiler -----------------*/\r\n#if   defined ( __CC_ARM )\r\n  #include \"cmsis_armcc.h\"\r\n\r\n/*------------------ ARM Compiler V6 -------------------*/\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #include \"cmsis_armcc_V6.h\"\r\n\r\n/*------------------ GNU Compiler ----------------------*/\r\n#elif defined ( __GNUC__ )\r\n  #include \"cmsis_gcc.h\"\r\n\r\n/*------------------ ICC Compiler ----------------------*/\r\n#elif defined ( __ICCARM__ )\r\n  #include <cmsis_iar.h>\r\n\r\n/*------------------ TI CCS Compiler -------------------*/\r\n#elif defined ( __TMS470__ )\r\n  #include <cmsis_ccs.h>\r\n\r\n/*------------------ TASKING Compiler ------------------*/\r\n#elif defined ( __TASKING__ )\r\n  /*\r\n   * The CMSIS functions have been implemented as intrinsics in the compiler.\r\n   * Please use \"carm -?i\" to get an up to date list of all intrinsics,\r\n   * Including the CMSIS ones.\r\n   */\r\n\r\n/*------------------ COSMIC Compiler -------------------*/\r\n#elif defined ( __CSMC__ )\r\n  #include <cmsis_csm.h>\r\n\r\n#endif\r\n\r\n/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r\n\r\n#endif /* __CORE_CMINSTR_H */\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/include/core_cmSimd.h",
    "content": "/**************************************************************************//**\r\n * @file     core_cmSimd.h\r\n * @brief    CMSIS Cortex-M SIMD Header File\r\n * @version  V4.30\r\n * @date     20. October 2015\r\n ******************************************************************************/\r\n/* Copyright (c) 2009 - 2015 ARM LIMITED\r\n\r\n   All rights reserved.\r\n   Redistribution and use in source and binary forms, with or without\r\n   modification, are permitted provided that the following conditions are met:\r\n   - Redistributions of source code must retain the above copyright\r\n     notice, this list of conditions and the following disclaimer.\r\n   - Redistributions in binary form must reproduce the above copyright\r\n     notice, this list of conditions and the following disclaimer in the\r\n     documentation and/or other materials provided with the distribution.\r\n   - Neither the name of ARM nor the names of its contributors may be used\r\n     to endorse or promote products derived from this software without\r\n     specific prior written permission.\r\n   *\r\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n   POSSIBILITY OF SUCH DAMAGE.\r\n   ---------------------------------------------------------------------------*/\r\n\r\n\r\n#if   defined ( __ICCARM__ )\r\n #pragma system_include         /* treat file as system include file for MISRA check */\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #pragma clang system_header   /* treat file as system include file */\r\n#endif\r\n\r\n#ifndef __CORE_CMSIMD_H\r\n#define __CORE_CMSIMD_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n\r\n/* ###################  Compiler specific Intrinsics  ########################### */\r\n/** \\defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r\n  Access to dedicated SIMD instructions\r\n  @{\r\n*/\r\n\r\n/*------------------ RealView Compiler -----------------*/\r\n#if   defined ( __CC_ARM )\r\n  #include \"cmsis_armcc.h\"\r\n\r\n/*------------------ ARM Compiler V6 -------------------*/\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #include \"cmsis_armcc_V6.h\"\r\n\r\n/*------------------ GNU Compiler ----------------------*/\r\n#elif defined ( __GNUC__ )\r\n  #include \"cmsis_gcc.h\"\r\n\r\n/*------------------ ICC Compiler ----------------------*/\r\n#elif defined ( __ICCARM__ )\r\n  #include <cmsis_iar.h>\r\n\r\n/*------------------ TI CCS Compiler -------------------*/\r\n#elif defined ( __TMS470__ )\r\n  #include <cmsis_ccs.h>\r\n\r\n/*------------------ TASKING Compiler ------------------*/\r\n#elif defined ( __TASKING__ )\r\n  /*\r\n   * The CMSIS functions have been implemented as intrinsics in the compiler.\r\n   * Please use \"carm -?i\" to get an up to date list of all intrinsics,\r\n   * Including the CMSIS ones.\r\n   */\r\n\r\n/*------------------ COSMIC Compiler -------------------*/\r\n#elif defined ( __CSMC__ )\r\n  #include <cmsis_csm.h>\r\n\r\n#endif\r\n\r\n/*@} end of group CMSIS_SIMD_intrinsics */\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __CORE_CMSIMD_H */\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/include/core_sc000.h",
    "content": "/**************************************************************************//**\r\n * @file     core_sc000.h\r\n * @brief    CMSIS SC000 Core Peripheral Access Layer Header File\r\n * @version  V4.30\r\n * @date     20. October 2015\r\n ******************************************************************************/\r\n/* Copyright (c) 2009 - 2015 ARM LIMITED\r\n\r\n   All rights reserved.\r\n   Redistribution and use in source and binary forms, with or without\r\n   modification, are permitted provided that the following conditions are met:\r\n   - Redistributions of source code must retain the above copyright\r\n     notice, this list of conditions and the following disclaimer.\r\n   - Redistributions in binary form must reproduce the above copyright\r\n     notice, this list of conditions and the following disclaimer in the\r\n     documentation and/or other materials provided with the distribution.\r\n   - Neither the name of ARM nor the names of its contributors may be used\r\n     to endorse or promote products derived from this software without\r\n     specific prior written permission.\r\n   *\r\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n   POSSIBILITY OF SUCH DAMAGE.\r\n   ---------------------------------------------------------------------------*/\r\n\r\n\r\n#if   defined ( __ICCARM__ )\r\n #pragma system_include         /* treat file as system include file for MISRA check */\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #pragma clang system_header   /* treat file as system include file */\r\n#endif\r\n\r\n#ifndef __CORE_SC000_H_GENERIC\r\n#define __CORE_SC000_H_GENERIC\r\n\r\n#include <stdint.h>\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/**\r\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r\n  CMSIS violates the following MISRA-C:2004 rules:\r\n\r\n   \\li Required Rule 8.5, object/function definition in header file.<br>\r\n     Function definitions in header files are used to allow 'inlining'.\r\n\r\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r\n     Unions are used for effective representation of core registers.\r\n\r\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\r\n     Function-like macros are used to allow more efficient code.\r\n */\r\n\r\n\r\n/*******************************************************************************\r\n *                 CMSIS definitions\r\n ******************************************************************************/\r\n/**\r\n  \\ingroup SC000\r\n  @{\r\n */\r\n\r\n/*  CMSIS SC000 definitions */\r\n#define __SC000_CMSIS_VERSION_MAIN  (0x04U)                                    /*!< [31:16] CMSIS HAL main version */\r\n#define __SC000_CMSIS_VERSION_SUB   (0x1EU)                                    /*!< [15:0]  CMSIS HAL sub version */\r\n#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \\\r\n                                      __SC000_CMSIS_VERSION_SUB           )    /*!< CMSIS HAL version number */\r\n\r\n#define __CORTEX_SC                 (000U)                                     /*!< Cortex secure core */\r\n\r\n\r\n#if   defined ( __CC_ARM )\r\n  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */\r\n  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */\r\n  #define __STATIC_INLINE  static __inline\r\n\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */\r\n  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */\r\n  #define __STATIC_INLINE  static __inline\r\n\r\n#elif defined ( __GNUC__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __ICCARM__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __TMS470__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __TASKING__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __CSMC__ )\r\n  #define __packed\r\n  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */\r\n  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#else\r\n  #error Unknown compiler\r\n#endif\r\n\r\n/** __FPU_USED indicates whether an FPU is used or not.\r\n    This core does not support an FPU at all\r\n*/\r\n#define __FPU_USED       0U\r\n\r\n#if defined ( __CC_ARM )\r\n  #if defined __TARGET_FPU_VFP\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #if defined __ARM_PCS_VFP\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __GNUC__ )\r\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __ICCARM__ )\r\n  #if defined __ARMVFP__\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __TMS470__ )\r\n  #if defined __TI_VFP_SUPPORT__\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __TASKING__ )\r\n  #if defined __FPU_VFP__\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __CSMC__ )\r\n  #if ( __CSMC__ & 0x400U)\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#endif\r\n\r\n#include \"core_cmInstr.h\"                /* Core Instruction Access */\r\n#include \"core_cmFunc.h\"                 /* Core Function Access */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __CORE_SC000_H_GENERIC */\r\n\r\n#ifndef __CMSIS_GENERIC\r\n\r\n#ifndef __CORE_SC000_H_DEPENDANT\r\n#define __CORE_SC000_H_DEPENDANT\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* check device defines and use defaults */\r\n#if defined __CHECK_DEVICE_DEFINES\r\n  #ifndef __SC000_REV\r\n    #define __SC000_REV             0x0000U\r\n    #warning \"__SC000_REV not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __MPU_PRESENT\r\n    #define __MPU_PRESENT             0U\r\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __NVIC_PRIO_BITS\r\n    #define __NVIC_PRIO_BITS          2U\r\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __Vendor_SysTickConfig\r\n    #define __Vendor_SysTickConfig    0U\r\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\r\n  #endif\r\n#endif\r\n\r\n/* IO definitions (access restrictions to peripheral registers) */\r\n/**\r\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\r\n\r\n    <strong>IO Type Qualifiers</strong> are used\r\n    \\li to specify the access to peripheral variables.\r\n    \\li for automatic generation of peripheral register debug information.\r\n*/\r\n#ifdef __cplusplus\r\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\r\n#else\r\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r\n#endif\r\n#define     __O     volatile             /*!< Defines 'write only' permissions */\r\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r\n\r\n/* following defines should be used for structure members */\r\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r\n\r\n/*@} end of group SC000 */\r\n\r\n\r\n\r\n/*******************************************************************************\r\n *                 Register Abstraction\r\n  Core Register contain:\r\n  - Core Register\r\n  - Core NVIC Register\r\n  - Core SCB Register\r\n  - Core SysTick Register\r\n  - Core MPU Register\r\n ******************************************************************************/\r\n/**\r\n  \\defgroup CMSIS_core_register Defines and Type Definitions\r\n  \\brief Type definitions and defines for Cortex-M processor based devices.\r\n*/\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_CORE  Status and Control Registers\r\n  \\brief      Core Register type definitions.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Union type to access the Application Program Status Register (APSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\r\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} APSR_Type;\r\n\r\n/* APSR Register Definitions */\r\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r\n\r\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r\n\r\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r\n\r\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} IPSR_Type;\r\n\r\n/* IPSR Register Definitions */\r\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\r\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\r\n    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\r\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} xPSR_Type;\r\n\r\n/* xPSR Register Definitions */\r\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r\n\r\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r\n\r\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r\n\r\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r\n\r\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r\n\r\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Control Registers (CONTROL).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */\r\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\r\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} CONTROL_Type;\r\n\r\n/* CONTROL Register Definitions */\r\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r\n\r\n/*@} end of group CMSIS_CORE */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r\n  \\brief      Type definitions for the NVIC Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r\n        uint32_t RESERVED0[31U];\r\n  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r\n        uint32_t RSERVED1[31U];\r\n  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r\n        uint32_t RESERVED2[31U];\r\n  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r\n        uint32_t RESERVED3[31U];\r\n        uint32_t RESERVED4[64U];\r\n  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\r\n}  NVIC_Type;\r\n\r\n/*@} end of group CMSIS_NVIC */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\r\n  \\brief    Type definitions for the System Control Block Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Control Block (SCB).\r\n */\r\ntypedef struct\r\n{\r\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\r\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r\n        uint32_t RESERVED0[1U];\r\n  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\r\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r\n        uint32_t RESERVED1[154U];\r\n  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */\r\n} SCB_Type;\r\n\r\n/* SCB CPUID Register Definitions */\r\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r\n\r\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r\n\r\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r\n\r\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r\n\r\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r\n\r\n/* SCB Interrupt Control State Register Definitions */\r\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\r\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\r\n\r\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r\n\r\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r\n\r\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r\n\r\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r\n\r\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r\n\r\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r\n\r\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r\n\r\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r\n\r\n/* SCB Interrupt Control State Register Definitions */\r\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\r\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\r\n\r\n/* SCB Application Interrupt and Reset Control Register Definitions */\r\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r\n\r\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r\n\r\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r\n\r\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r\n\r\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r\n\r\n/* SCB System Control Register Definitions */\r\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r\n\r\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r\n\r\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r\n\r\n/* SCB Configuration Control Register Definitions */\r\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\r\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\r\n\r\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r\n\r\n/* SCB System Handler Control and State Register Definitions */\r\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r\n\r\n/*@} end of group CMSIS_SCB */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\r\n */\r\ntypedef struct\r\n{\r\n        uint32_t RESERVED0[2U];\r\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\r\n} SCnSCB_Type;\r\n\r\n/* Auxiliary Control Register Definitions */\r\n#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\r\n#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\r\n\r\n/*@} end of group CMSIS_SCnotSCB */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r\n  \\brief    Type definitions for the System Timer Registers.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Timer (SysTick).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r\n} SysTick_Type;\r\n\r\n/* SysTick Control / Status Register Definitions */\r\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r\n\r\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r\n\r\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r\n\r\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r\n\r\n/* SysTick Reload Register Definitions */\r\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r\n\r\n/* SysTick Current Register Definitions */\r\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r\n\r\n/* SysTick Calibration Register Definitions */\r\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r\n\r\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r\n\r\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r\n\r\n/*@} end of group CMSIS_SysTick */\r\n\r\n#if (__MPU_PRESENT == 1U)\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\r\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\r\n */\r\ntypedef struct\r\n{\r\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\r\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\r\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\r\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\r\n} MPU_Type;\r\n\r\n/* MPU Type Register Definitions */\r\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\r\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r\n\r\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\r\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r\n\r\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\r\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\r\n\r\n/* MPU Control Register Definitions */\r\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\r\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r\n\r\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\r\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r\n\r\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\r\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\r\n\r\n/* MPU Region Number Register Definitions */\r\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\r\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\r\n\r\n/* MPU Region Base Address Register Definitions */\r\n#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */\r\n#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */\r\n\r\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\r\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\r\n\r\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\r\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\r\n\r\n/* MPU Region Attribute and Size Register Definitions */\r\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\r\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\r\n\r\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\r\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\r\n\r\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\r\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\r\n\r\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\r\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\r\n\r\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\r\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\r\n\r\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\r\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\r\n\r\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\r\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\r\n\r\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\r\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\r\n\r\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\r\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\r\n\r\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\r\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\r\n\r\n/*@} end of group CMSIS_MPU */\r\n#endif\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r\n  \\brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\r\n            Therefore they are not covered by the SC000 header file.\r\n  @{\r\n */\r\n/*@} end of group CMSIS_CoreDebug */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\r\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief   Mask and shift a bit field value for use in a register bit range.\r\n  \\param[in] field  Name of the register bit field.\r\n  \\param[in] value  Value of the bit field.\r\n  \\return           Masked and shifted value.\r\n*/\r\n#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)\r\n\r\n/**\r\n  \\brief     Mask and shift a register value to extract a bit filed value.\r\n  \\param[in] field  Name of the register bit field.\r\n  \\param[in] value  Value of register.\r\n  \\return           Masked and shifted bit field value.\r\n*/\r\n#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)\r\n\r\n/*@} end of group CMSIS_core_bitfield */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_core_base     Core Definitions\r\n  \\brief      Definitions for base addresses, unions, and structures.\r\n  @{\r\n */\r\n\r\n/* Memory mapping of SC000 Hardware */\r\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\r\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\r\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\r\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\r\n\r\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\r\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\r\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\r\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\r\n\r\n#if (__MPU_PRESENT == 1U)\r\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\r\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\r\n#endif\r\n\r\n/*@} */\r\n\r\n\r\n\r\n/*******************************************************************************\r\n *                Hardware Abstraction Layer\r\n  Core Function Interface contains:\r\n  - Core NVIC Functions\r\n  - Core SysTick Functions\r\n  - Core Register Access Functions\r\n ******************************************************************************/\r\n/**\r\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r\n*/\r\n\r\n\r\n\r\n/* ##########################   NVIC functions  #################################### */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\r\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\r\n  @{\r\n */\r\n\r\n/* Interrupt Priorities are WORD accessible only under ARMv6M                   */\r\n/* The following MACROS handle generation of the register offset and byte masks */\r\n#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\r\n#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\r\n#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\r\n\r\n\r\n/**\r\n  \\brief   Enable External Interrupt\r\n  \\details Enables a device-specific interrupt in the NVIC interrupt controller.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Disable External Interrupt\r\n  \\details Disables a device-specific interrupt in the NVIC interrupt controller.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Pending Interrupt\r\n  \\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\return             0  Interrupt status is not pending.\r\n  \\return             1  Interrupt status is pending.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Pending Interrupt\r\n  \\details Sets the pending bit of an external interrupt.\r\n  \\param [in]      IRQn  Interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Clear Pending Interrupt\r\n  \\details Clears the pending bit of an external interrupt.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Interrupt Priority\r\n  \\details Sets the priority of an interrupt.\r\n  \\note    The priority cannot be set for every core interrupt.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\param [in]  priority  Priority to set.\r\n */\r\n__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r\n{\r\n  if ((int32_t)(IRQn) < 0)\r\n  {\r\n    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r\n  }\r\n  else\r\n  {\r\n    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Interrupt Priority\r\n  \\details Reads the priority of an interrupt.\r\n           The interrupt number can be positive to specify an external (device specific) interrupt,\r\n           or negative to specify an internal (core) interrupt.\r\n  \\param [in]   IRQn  Interrupt number.\r\n  \\return             Interrupt Priority.\r\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r\n{\r\n\r\n  if ((int32_t)(IRQn) < 0)\r\n  {\r\n    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r\n  }\r\n  else\r\n  {\r\n    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   System Reset\r\n  \\details Initiates a system reset request to reset the MCU.\r\n */\r\n__STATIC_INLINE void NVIC_SystemReset(void)\r\n{\r\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\r\n                                                                       buffered write are completed before reset */\r\n  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r\n                 SCB_AIRCR_SYSRESETREQ_Msk);\r\n  __DSB();                                                          /* Ensure completion of memory access */\r\n\r\n  for(;;)                                                           /* wait until reset */\r\n  {\r\n    __NOP();\r\n  }\r\n}\r\n\r\n/*@} end of CMSIS_Core_NVICFunctions */\r\n\r\n\r\n\r\n/* ##################################    SysTick function  ############################################ */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r\n  \\brief    Functions that configure the System.\r\n  @{\r\n */\r\n\r\n#if (__Vendor_SysTickConfig == 0U)\r\n\r\n/**\r\n  \\brief   System Tick Configuration\r\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r\n           Counter is in free running mode to generate periodic interrupts.\r\n  \\param [in]  ticks  Number of ticks between two interrupts.\r\n  \\return          0  Function succeeded.\r\n  \\return          1  Function failed.\r\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r\n           must contain a vendor-specific implementation of this function.\r\n */\r\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r\n{\r\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r\n  {\r\n    return (1UL);                                                   /* Reload value impossible */\r\n  }\r\n\r\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r\n                   SysTick_CTRL_TICKINT_Msk   |\r\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r\n  return (0UL);                                                     /* Function successful */\r\n}\r\n\r\n#endif\r\n\r\n/*@} end of CMSIS_Core_SysTickFunctions */\r\n\r\n\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __CORE_SC000_H_DEPENDANT */\r\n\r\n#endif /* __CMSIS_GENERIC */\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/include/core_sc300.h",
    "content": "/**************************************************************************//**\r\n * @file     core_sc300.h\r\n * @brief    CMSIS SC300 Core Peripheral Access Layer Header File\r\n * @version  V4.30\r\n * @date     20. October 2015\r\n ******************************************************************************/\r\n/* Copyright (c) 2009 - 2015 ARM LIMITED\r\n\r\n   All rights reserved.\r\n   Redistribution and use in source and binary forms, with or without\r\n   modification, are permitted provided that the following conditions are met:\r\n   - Redistributions of source code must retain the above copyright\r\n     notice, this list of conditions and the following disclaimer.\r\n   - Redistributions in binary form must reproduce the above copyright\r\n     notice, this list of conditions and the following disclaimer in the\r\n     documentation and/or other materials provided with the distribution.\r\n   - Neither the name of ARM nor the names of its contributors may be used\r\n     to endorse or promote products derived from this software without\r\n     specific prior written permission.\r\n   *\r\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r\n   POSSIBILITY OF SUCH DAMAGE.\r\n   ---------------------------------------------------------------------------*/\r\n\r\n\r\n#if   defined ( __ICCARM__ )\r\n #pragma system_include         /* treat file as system include file for MISRA check */\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #pragma clang system_header   /* treat file as system include file */\r\n#endif\r\n\r\n#ifndef __CORE_SC300_H_GENERIC\r\n#define __CORE_SC300_H_GENERIC\r\n\r\n#include <stdint.h>\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/**\r\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\r\n  CMSIS violates the following MISRA-C:2004 rules:\r\n\r\n   \\li Required Rule 8.5, object/function definition in header file.<br>\r\n     Function definitions in header files are used to allow 'inlining'.\r\n\r\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r\n     Unions are used for effective representation of core registers.\r\n\r\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\r\n     Function-like macros are used to allow more efficient code.\r\n */\r\n\r\n\r\n/*******************************************************************************\r\n *                 CMSIS definitions\r\n ******************************************************************************/\r\n/**\r\n  \\ingroup SC3000\r\n  @{\r\n */\r\n\r\n/*  CMSIS SC300 definitions */\r\n#define __SC300_CMSIS_VERSION_MAIN  (0x04U)                                    /*!< [31:16] CMSIS HAL main version */\r\n#define __SC300_CMSIS_VERSION_SUB   (0x1EU)                                    /*!< [15:0]  CMSIS HAL sub version */\r\n#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16U) | \\\r\n                                      __SC300_CMSIS_VERSION_SUB           )    /*!< CMSIS HAL version number */\r\n\r\n#define __CORTEX_SC                 (300U)                                     /*!< Cortex secure core */\r\n\r\n\r\n#if   defined ( __CC_ARM )\r\n  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */\r\n  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */\r\n  #define __STATIC_INLINE  static __inline\r\n\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */\r\n  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */\r\n  #define __STATIC_INLINE  static __inline\r\n\r\n#elif defined ( __GNUC__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __ICCARM__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __TMS470__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __TASKING__ )\r\n  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */\r\n  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#elif defined ( __CSMC__ )\r\n  #define __packed\r\n  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */\r\n  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */\r\n  #define __STATIC_INLINE  static inline\r\n\r\n#else\r\n  #error Unknown compiler\r\n#endif\r\n\r\n/** __FPU_USED indicates whether an FPU is used or not.\r\n    This core does not support an FPU at all\r\n*/\r\n#define __FPU_USED       0U\r\n\r\n#if defined ( __CC_ARM )\r\n  #if defined __TARGET_FPU_VFP\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r\n  #if defined __ARM_PCS_VFP\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __GNUC__ )\r\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __ICCARM__ )\r\n  #if defined __ARMVFP__\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __TMS470__ )\r\n  #if defined __TI_VFP_SUPPORT__\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __TASKING__ )\r\n  #if defined __FPU_VFP__\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#elif defined ( __CSMC__ )\r\n  #if ( __CSMC__ & 0x400U)\r\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\r\n  #endif\r\n\r\n#endif\r\n\r\n#include \"core_cmInstr.h\"                /* Core Instruction Access */\r\n#include \"core_cmFunc.h\"                 /* Core Function Access */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __CORE_SC300_H_GENERIC */\r\n\r\n#ifndef __CMSIS_GENERIC\r\n\r\n#ifndef __CORE_SC300_H_DEPENDANT\r\n#define __CORE_SC300_H_DEPENDANT\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* check device defines and use defaults */\r\n#if defined __CHECK_DEVICE_DEFINES\r\n  #ifndef __SC300_REV\r\n    #define __SC300_REV               0x0000U\r\n    #warning \"__SC300_REV not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __MPU_PRESENT\r\n    #define __MPU_PRESENT             0U\r\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __NVIC_PRIO_BITS\r\n    #define __NVIC_PRIO_BITS          4U\r\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\r\n  #endif\r\n\r\n  #ifndef __Vendor_SysTickConfig\r\n    #define __Vendor_SysTickConfig    0U\r\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\r\n  #endif\r\n#endif\r\n\r\n/* IO definitions (access restrictions to peripheral registers) */\r\n/**\r\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\r\n\r\n    <strong>IO Type Qualifiers</strong> are used\r\n    \\li to specify the access to peripheral variables.\r\n    \\li for automatic generation of peripheral register debug information.\r\n*/\r\n#ifdef __cplusplus\r\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\r\n#else\r\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\r\n#endif\r\n#define     __O     volatile             /*!< Defines 'write only' permissions */\r\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\r\n\r\n/* following defines should be used for structure members */\r\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\r\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\r\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\r\n\r\n/*@} end of group SC300 */\r\n\r\n\r\n\r\n/*******************************************************************************\r\n *                 Register Abstraction\r\n  Core Register contain:\r\n  - Core Register\r\n  - Core NVIC Register\r\n  - Core SCB Register\r\n  - Core SysTick Register\r\n  - Core Debug Register\r\n  - Core MPU Register\r\n ******************************************************************************/\r\n/**\r\n  \\defgroup CMSIS_core_register Defines and Type Definitions\r\n  \\brief Type definitions and defines for Cortex-M processor based devices.\r\n*/\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_CORE  Status and Control Registers\r\n  \\brief      Core Register type definitions.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Union type to access the Application Program Status Register (APSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */\r\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} APSR_Type;\r\n\r\n/* APSR Register Definitions */\r\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\r\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\r\n\r\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\r\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\r\n\r\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\r\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\r\n\r\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\r\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\r\n\r\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\r\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} IPSR_Type;\r\n\r\n/* IPSR Register Definitions */\r\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\r\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\r\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\r\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\r\n    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */\r\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\r\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\r\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\r\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\r\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} xPSR_Type;\r\n\r\n/* xPSR Register Definitions */\r\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\r\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\r\n\r\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\r\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\r\n\r\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\r\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\r\n\r\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\r\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\r\n\r\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\r\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\r\n\r\n#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */\r\n#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */\r\n\r\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\r\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\r\n\r\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\r\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\r\n\r\n\r\n/**\r\n  \\brief  Union type to access the Control Registers (CONTROL).\r\n */\r\ntypedef union\r\n{\r\n  struct\r\n  {\r\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\r\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\r\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\r\n  } b;                                   /*!< Structure used for bit  access */\r\n  uint32_t w;                            /*!< Type      used for word access */\r\n} CONTROL_Type;\r\n\r\n/* CONTROL Register Definitions */\r\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\r\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\r\n\r\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\r\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\r\n\r\n/*@} end of group CMSIS_CORE */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\r\n  \\brief      Type definitions for the NVIC Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\r\n        uint32_t RESERVED0[24U];\r\n  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\r\n        uint32_t RSERVED1[24U];\r\n  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\r\n        uint32_t RESERVED2[24U];\r\n  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\r\n        uint32_t RESERVED3[24U];\r\n  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\r\n        uint32_t RESERVED4[56U];\r\n  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\r\n        uint32_t RESERVED5[644U];\r\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\r\n}  NVIC_Type;\r\n\r\n/* Software Triggered Interrupt Register Definitions */\r\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\r\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\r\n\r\n/*@} end of group CMSIS_NVIC */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\r\n  \\brief    Type definitions for the System Control Block Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Control Block (SCB).\r\n */\r\ntypedef struct\r\n{\r\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\r\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\r\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\r\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\r\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\r\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\r\n  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\r\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\r\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\r\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\r\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\r\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\r\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\r\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\r\n  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */\r\n  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */\r\n  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\r\n  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\r\n  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\r\n        uint32_t RESERVED0[5U];\r\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\r\n        uint32_t RESERVED1[129U];\r\n  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */\r\n} SCB_Type;\r\n\r\n/* SCB CPUID Register Definitions */\r\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\r\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\r\n\r\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\r\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\r\n\r\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\r\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\r\n\r\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\r\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\r\n\r\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\r\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\r\n\r\n/* SCB Interrupt Control State Register Definitions */\r\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\r\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\r\n\r\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\r\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\r\n\r\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\r\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\r\n\r\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\r\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\r\n\r\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\r\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\r\n\r\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\r\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\r\n\r\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\r\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\r\n\r\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\r\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\r\n\r\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\r\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\r\n\r\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\r\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\r\n\r\n/* SCB Vector Table Offset Register Definitions */\r\n#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */\r\n#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */\r\n\r\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\r\n#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */\r\n\r\n/* SCB Application Interrupt and Reset Control Register Definitions */\r\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\r\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\r\n\r\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\r\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\r\n\r\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\r\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\r\n\r\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\r\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\r\n\r\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\r\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\r\n\r\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\r\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r\n\r\n#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\r\n#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\r\n\r\n/* SCB System Control Register Definitions */\r\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\r\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\r\n\r\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\r\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\r\n\r\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\r\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\r\n\r\n/* SCB Configuration Control Register Definitions */\r\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\r\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\r\n\r\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\r\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\r\n\r\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\r\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\r\n\r\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\r\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\r\n\r\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\r\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\r\n\r\n#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\r\n#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\r\n\r\n/* SCB System Handler Control and State Register Definitions */\r\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\r\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\r\n\r\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\r\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\r\n\r\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\r\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\r\n\r\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\r\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\r\n\r\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\r\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r\n\r\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\r\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r\n\r\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\r\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\r\n\r\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\r\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\r\n\r\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\r\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\r\n\r\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\r\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\r\n\r\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\r\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\r\n\r\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\r\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\r\n\r\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\r\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\r\n\r\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\r\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\r\n\r\n/* SCB Configurable Fault Status Register Definitions */\r\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\r\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\r\n\r\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\r\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\r\n\r\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r\n\r\n/* SCB Hard Fault Status Register Definitions */\r\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\r\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\r\n\r\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\r\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\r\n\r\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\r\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\r\n\r\n/* SCB Debug Fault Status Register Definitions */\r\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\r\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\r\n\r\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\r\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\r\n\r\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\r\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\r\n\r\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\r\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\r\n\r\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\r\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\r\n\r\n/*@} end of group CMSIS_SCB */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\r\n */\r\ntypedef struct\r\n{\r\n        uint32_t RESERVED0[1U];\r\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\r\n        uint32_t RESERVED1[1U];\r\n} SCnSCB_Type;\r\n\r\n/* Interrupt Controller Type Register Definitions */\r\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\r\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\r\n\r\n/*@} end of group CMSIS_SCnotSCB */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\r\n  \\brief    Type definitions for the System Timer Registers.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the System Timer (SysTick).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\r\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\r\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\r\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\r\n} SysTick_Type;\r\n\r\n/* SysTick Control / Status Register Definitions */\r\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\r\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\r\n\r\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\r\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\r\n\r\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\r\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\r\n\r\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\r\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\r\n\r\n/* SysTick Reload Register Definitions */\r\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\r\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\r\n\r\n/* SysTick Current Register Definitions */\r\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\r\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\r\n\r\n/* SysTick Calibration Register Definitions */\r\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\r\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\r\n\r\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\r\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\r\n\r\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\r\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\r\n\r\n/*@} end of group CMSIS_SysTick */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\r\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r\n */\r\ntypedef struct\r\n{\r\n  __OM  union\r\n  {\r\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\r\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\r\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\r\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\r\n        uint32_t RESERVED0[864U];\r\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\r\n        uint32_t RESERVED1[15U];\r\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\r\n        uint32_t RESERVED2[15U];\r\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\r\n        uint32_t RESERVED3[29U];\r\n  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\r\n  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\r\n  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\r\n        uint32_t RESERVED4[43U];\r\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\r\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\r\n        uint32_t RESERVED5[6U];\r\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\r\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\r\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\r\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\r\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\r\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\r\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\r\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\r\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\r\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\r\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\r\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\r\n} ITM_Type;\r\n\r\n/* ITM Trace Privilege Register Definitions */\r\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\r\n#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */\r\n\r\n/* ITM Trace Control Register Definitions */\r\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\r\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\r\n\r\n#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\r\n#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */\r\n\r\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\r\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\r\n\r\n#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\r\n#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\r\n\r\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\r\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\r\n\r\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\r\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\r\n\r\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\r\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\r\n\r\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\r\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\r\n\r\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\r\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\r\n\r\n/* ITM Integration Write Register Definitions */\r\n#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */\r\n#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\r\n\r\n/* ITM Integration Read Register Definitions */\r\n#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */\r\n#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\r\n\r\n/* ITM Integration Mode Control Register Definitions */\r\n#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */\r\n#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\r\n\r\n/* ITM Lock Status Register Definitions */\r\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\r\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\r\n\r\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\r\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\r\n\r\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\r\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\r\n\r\n/*@}*/ /* end of group CMSIS_ITM */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\r\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\r\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\r\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\r\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\r\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\r\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\r\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\r\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\r\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\r\n  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\r\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\r\n        uint32_t RESERVED0[1U];\r\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\r\n  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\r\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\r\n        uint32_t RESERVED1[1U];\r\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\r\n  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\r\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\r\n        uint32_t RESERVED2[1U];\r\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\r\n  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\r\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\r\n} DWT_Type;\r\n\r\n/* DWT Control Register Definitions */\r\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\r\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\r\n\r\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\r\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\r\n\r\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\r\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\r\n\r\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\r\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\r\n\r\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\r\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\r\n\r\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\r\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\r\n\r\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\r\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\r\n\r\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\r\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\r\n\r\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\r\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\r\n\r\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\r\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\r\n\r\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\r\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\r\n\r\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\r\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\r\n\r\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\r\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\r\n\r\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\r\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\r\n\r\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\r\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\r\n\r\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\r\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\r\n\r\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\r\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\r\n\r\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\r\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\r\n\r\n/* DWT CPI Count Register Definitions */\r\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\r\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\r\n\r\n/* DWT Exception Overhead Count Register Definitions */\r\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\r\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\r\n\r\n/* DWT Sleep Count Register Definitions */\r\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\r\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r\n\r\n/* DWT LSU Count Register Definitions */\r\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\r\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\r\n\r\n/* DWT Folded-instruction Count Register Definitions */\r\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\r\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\r\n\r\n/* DWT Comparator Mask Register Definitions */\r\n#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\r\n#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\r\n\r\n/* DWT Comparator Function Register Definitions */\r\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\r\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\r\n\r\n#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\r\n#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\r\n\r\n#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\r\n#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\r\n\r\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\r\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\r\n\r\n#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\r\n#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\r\n\r\n#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\r\n#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\r\n\r\n#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\r\n#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\r\n\r\n#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\r\n#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\r\n\r\n#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\r\n#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\r\n\r\n/*@}*/ /* end of group CMSIS_DWT */\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\r\n  \\brief    Type definitions for the Trace Port Interface (TPI)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\r\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\r\n        uint32_t RESERVED0[2U];\r\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\r\n        uint32_t RESERVED1[55U];\r\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\r\n        uint32_t RESERVED2[131U];\r\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\r\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\r\n  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\r\n        uint32_t RESERVED3[759U];\r\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */\r\n  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\r\n  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\r\n        uint32_t RESERVED4[1U];\r\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\r\n  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\r\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\r\n        uint32_t RESERVED5[39U];\r\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\r\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\r\n        uint32_t RESERVED7[8U];\r\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\r\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\r\n} TPI_Type;\r\n\r\n/* TPI Asynchronous Clock Prescaler Register Definitions */\r\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\r\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\r\n\r\n/* TPI Selected Pin Protocol Register Definitions */\r\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\r\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\r\n\r\n/* TPI Formatter and Flush Status Register Definitions */\r\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\r\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\r\n\r\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\r\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\r\n\r\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\r\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\r\n\r\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\r\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\r\n\r\n/* TPI Formatter and Flush Control Register Definitions */\r\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\r\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\r\n\r\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\r\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\r\n\r\n/* TPI TRIGGER Register Definitions */\r\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\r\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\r\n\r\n/* TPI Integration ETM Data Register Definitions (FIFO0) */\r\n#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\r\n#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\r\n\r\n#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\r\n#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\r\n\r\n#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\r\n#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\r\n\r\n#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\r\n#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\r\n\r\n#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\r\n#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\r\n\r\n#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\r\n#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\r\n\r\n#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\r\n#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\r\n\r\n/* TPI ITATBCTR2 Register Definitions */\r\n#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */\r\n#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */\r\n\r\n/* TPI Integration ITM Data Register Definitions (FIFO1) */\r\n#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\r\n#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\r\n\r\n#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\r\n#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\r\n\r\n#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\r\n#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\r\n\r\n#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\r\n#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\r\n\r\n#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\r\n#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\r\n\r\n#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\r\n#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\r\n\r\n#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\r\n#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\r\n\r\n/* TPI ITATBCTR0 Register Definitions */\r\n#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */\r\n#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */\r\n\r\n/* TPI Integration Mode Control Register Definitions */\r\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\r\n#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\r\n\r\n/* TPI DEVID Register Definitions */\r\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\r\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\r\n\r\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\r\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\r\n\r\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\r\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\r\n\r\n#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\r\n#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\r\n\r\n#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\r\n#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\r\n\r\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\r\n#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\r\n\r\n/* TPI DEVTYPE Register Definitions */\r\n#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */\r\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\r\n\r\n#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */\r\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\r\n\r\n/*@}*/ /* end of group CMSIS_TPI */\r\n\r\n\r\n#if (__MPU_PRESENT == 1U)\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\r\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\r\n */\r\ntypedef struct\r\n{\r\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\r\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\r\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\r\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\r\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\r\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\r\n  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\r\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\r\n  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\r\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\r\n  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\r\n} MPU_Type;\r\n\r\n/* MPU Type Register Definitions */\r\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\r\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\r\n\r\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\r\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\r\n\r\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\r\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\r\n\r\n/* MPU Control Register Definitions */\r\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\r\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\r\n\r\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\r\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\r\n\r\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\r\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\r\n\r\n/* MPU Region Number Register Definitions */\r\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\r\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\r\n\r\n/* MPU Region Base Address Register Definitions */\r\n#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\r\n#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\r\n\r\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\r\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\r\n\r\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\r\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\r\n\r\n/* MPU Region Attribute and Size Register Definitions */\r\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\r\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\r\n\r\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\r\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\r\n\r\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\r\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\r\n\r\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\r\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\r\n\r\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\r\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\r\n\r\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\r\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\r\n\r\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\r\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\r\n\r\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\r\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\r\n\r\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\r\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\r\n\r\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\r\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\r\n\r\n/*@} end of group CMSIS_MPU */\r\n#endif\r\n\r\n\r\n/**\r\n  \\ingroup  CMSIS_core_register\r\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\r\n  \\brief    Type definitions for the Core Debug Registers\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\r\n */\r\ntypedef struct\r\n{\r\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\r\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\r\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\r\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\r\n} CoreDebug_Type;\r\n\r\n/* Debug Halting Control and Status Register Definitions */\r\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\r\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\r\n\r\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\r\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r\n\r\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r\n\r\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\r\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r\n\r\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\r\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\r\n\r\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\r\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\r\n\r\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\r\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\r\n\r\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r\n\r\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\r\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r\n\r\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\r\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\r\n\r\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\r\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\r\n\r\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r\n\r\n/* Debug Core Register Selector Register Definitions */\r\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\r\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\r\n\r\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\r\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\r\n\r\n/* Debug Exception and Monitor Control Register Definitions */\r\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\r\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\r\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\r\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\r\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\r\n\r\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\r\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\r\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\r\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\r\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\r\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\r\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\r\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\r\n\r\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\r\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r\n\r\n/*@} end of group CMSIS_CoreDebug */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\r\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief   Mask and shift a bit field value for use in a register bit range.\r\n  \\param[in] field  Name of the register bit field.\r\n  \\param[in] value  Value of the bit field.\r\n  \\return           Masked and shifted value.\r\n*/\r\n#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)\r\n\r\n/**\r\n  \\brief     Mask and shift a register value to extract a bit filed value.\r\n  \\param[in] field  Name of the register bit field.\r\n  \\param[in] value  Value of register.\r\n  \\return           Masked and shifted bit field value.\r\n*/\r\n#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)\r\n\r\n/*@} end of group CMSIS_core_bitfield */\r\n\r\n\r\n/**\r\n  \\ingroup    CMSIS_core_register\r\n  \\defgroup   CMSIS_core_base     Core Definitions\r\n  \\brief      Definitions for base addresses, unions, and structures.\r\n  @{\r\n */\r\n\r\n/* Memory mapping of Cortex-M3 Hardware */\r\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\r\n#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\r\n#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\r\n#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\r\n#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\r\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\r\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\r\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\r\n\r\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\r\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\r\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\r\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\r\n#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\r\n#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\r\n#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\r\n#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\r\n\r\n#if (__MPU_PRESENT == 1U)\r\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\r\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\r\n#endif\r\n\r\n/*@} */\r\n\r\n\r\n\r\n/*******************************************************************************\r\n *                Hardware Abstraction Layer\r\n  Core Function Interface contains:\r\n  - Core NVIC Functions\r\n  - Core SysTick Functions\r\n  - Core Debug Functions\r\n  - Core Register Access Functions\r\n ******************************************************************************/\r\n/**\r\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r\n*/\r\n\r\n\r\n\r\n/* ##########################   NVIC functions  #################################### */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\r\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\r\n  @{\r\n */\r\n\r\n/**\r\n  \\brief   Set Priority Grouping\r\n  \\details Sets the priority grouping field using the required unlock sequence.\r\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r\n           Only values from 0..7 are used.\r\n           In case of a conflict between priority grouping and available\r\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r\n  \\param [in]      PriorityGroup  Priority grouping field.\r\n */\r\n__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r\n{\r\n  uint32_t reg_value;\r\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\r\n\r\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\r\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\r\n  reg_value  =  (reg_value                                   |\r\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r\n                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */\r\n  SCB->AIRCR =  reg_value;\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Priority Grouping\r\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\r\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r\n{\r\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Enable External Interrupt\r\n  \\details Enables a device-specific interrupt in the NVIC interrupt controller.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Disable External Interrupt\r\n  \\details Disables a device-specific interrupt in the NVIC interrupt controller.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Pending Interrupt\r\n  \\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\return             0  Interrupt status is not pending.\r\n  \\return             1  Interrupt status is pending.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Pending Interrupt\r\n  \\details Sets the pending bit of an external interrupt.\r\n  \\param [in]      IRQn  Interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Clear Pending Interrupt\r\n  \\details Clears the pending bit of an external interrupt.\r\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\r\n */\r\n__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Active Interrupt\r\n  \\details Reads the active register in NVIC and returns the active bit.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\return             0  Interrupt status is not active.\r\n  \\return             1  Interrupt status is active.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r\n{\r\n  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Set Interrupt Priority\r\n  \\details Sets the priority of an interrupt.\r\n  \\note    The priority cannot be set for every core interrupt.\r\n  \\param [in]      IRQn  Interrupt number.\r\n  \\param [in]  priority  Priority to set.\r\n */\r\n__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r\n{\r\n  if ((int32_t)(IRQn) < 0)\r\n  {\r\n    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r\n  }\r\n  else\r\n  {\r\n    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Get Interrupt Priority\r\n  \\details Reads the priority of an interrupt.\r\n           The interrupt number can be positive to specify an external (device specific) interrupt,\r\n           or negative to specify an internal (core) interrupt.\r\n  \\param [in]   IRQn  Interrupt number.\r\n  \\return             Interrupt Priority.\r\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\r\n */\r\n__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r\n{\r\n\r\n  if ((int32_t)(IRQn) < 0)\r\n  {\r\n    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r\n  }\r\n  else\r\n  {\r\n    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Encode Priority\r\n  \\details Encodes the priority for an interrupt with the given priority group,\r\n           preemptive priority value, and subpriority value.\r\n           In case of a conflict between priority grouping and available\r\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r\n  \\param [in]     PriorityGroup  Used priority group.\r\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\r\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\r\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\r\n */\r\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r\n{\r\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r\n  uint32_t PreemptPriorityBits;\r\n  uint32_t SubPriorityBits;\r\n\r\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r\n\r\n  return (\r\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\r\n         );\r\n}\r\n\r\n\r\n/**\r\n  \\brief   Decode Priority\r\n  \\details Decodes an interrupt priority value with a given priority group to\r\n           preemptive priority value and subpriority value.\r\n           In case of a conflict between priority grouping and available\r\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\r\n  \\param [in]     PriorityGroup  Used priority group.\r\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\r\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\r\n */\r\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r\n{\r\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\r\n  uint32_t PreemptPriorityBits;\r\n  uint32_t SubPriorityBits;\r\n\r\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r\n\r\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   System Reset\r\n  \\details Initiates a system reset request to reset the MCU.\r\n */\r\n__STATIC_INLINE void NVIC_SystemReset(void)\r\n{\r\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\r\n                                                                       buffered write are completed before reset */\r\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\r\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\r\n  __DSB();                                                          /* Ensure completion of memory access */\r\n\r\n  for(;;)                                                           /* wait until reset */\r\n  {\r\n    __NOP();\r\n  }\r\n}\r\n\r\n/*@} end of CMSIS_Core_NVICFunctions */\r\n\r\n\r\n\r\n/* ##################################    SysTick function  ############################################ */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r\n  \\brief    Functions that configure the System.\r\n  @{\r\n */\r\n\r\n#if (__Vendor_SysTickConfig == 0U)\r\n\r\n/**\r\n  \\brief   System Tick Configuration\r\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r\n           Counter is in free running mode to generate periodic interrupts.\r\n  \\param [in]  ticks  Number of ticks between two interrupts.\r\n  \\return          0  Function succeeded.\r\n  \\return          1  Function failed.\r\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r\n           must contain a vendor-specific implementation of this function.\r\n */\r\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r\n{\r\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r\n  {\r\n    return (1UL);                                                   /* Reload value impossible */\r\n  }\r\n\r\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\r\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\r\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r\n                   SysTick_CTRL_TICKINT_Msk   |\r\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\r\n  return (0UL);                                                     /* Function successful */\r\n}\r\n\r\n#endif\r\n\r\n/*@} end of CMSIS_Core_SysTickFunctions */\r\n\r\n\r\n\r\n/* ##################################### Debug In/Output function ########################################### */\r\n/**\r\n  \\ingroup  CMSIS_Core_FunctionInterface\r\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\r\n  \\brief    Functions that access the ITM debug interface.\r\n  @{\r\n */\r\n\r\nextern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters. */\r\n#define                 ITM_RXBUFFER_EMPTY   0x5AA55AA5U /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\r\n\r\n\r\n/**\r\n  \\brief   ITM Send Character\r\n  \\details Transmits a character via the ITM channel 0, and\r\n           \\li Just returns when no debugger is connected that has booked the output.\r\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r\n  \\param [in]     ch  Character to transmit.\r\n  \\returns            Character to transmit.\r\n */\r\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r\n{\r\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\r\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\r\n  {\r\n    while (ITM->PORT[0U].u32 == 0UL)\r\n    {\r\n      __NOP();\r\n    }\r\n    ITM->PORT[0U].u8 = (uint8_t)ch;\r\n  }\r\n  return (ch);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   ITM Receive Character\r\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\r\n  \\return             Received character.\r\n  \\return         -1  No character pending.\r\n */\r\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r\n{\r\n  int32_t ch = -1;                           /* no character available */\r\n\r\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r\n  {\r\n    ch = ITM_RxBuffer;\r\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\r\n  }\r\n\r\n  return (ch);\r\n}\r\n\r\n\r\n/**\r\n  \\brief   ITM Check Character\r\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\r\n  \\return          0  No character available.\r\n  \\return          1  Character available.\r\n */\r\n__STATIC_INLINE int32_t ITM_CheckChar (void)\r\n{\r\n\r\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r\n  {\r\n    return (0);                              /* no character available */\r\n  }\r\n  else\r\n  {\r\n    return (1);                              /*    character available */\r\n  }\r\n}\r\n\r\n/*@} end of CMSIS_core_DebugFunctions */\r\n\r\n\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __CORE_SC300_H_DEPENDANT */\r\n\r\n#endif /* __CMSIS_GENERIC */\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/ld/opencr_flash.ld",
    "content": "/*\r\n*****************************************************************************\r\n**\r\n\r\n**  File        : LinkerScript.ld\r\n**\r\n**  Abstract    : Linker script for STM32F746IGTx Device with\r\n**                1024KByte FLASH, 320KByte RAM\r\n**\r\n**                Set heap size, stack size and stack location according\r\n**                to application requirements.\r\n**\r\n**                Set memory bank area and size if external memory is used.\r\n**\r\n**  Target      : STMicroelectronics STM32\r\n**\r\n**\r\n**  Distribution: The file is distributed as is, without any warranty\r\n**                of any kind.\r\n**\r\n**  (c)Copyright Ac6.\r\n**  You may use this file as-is or modify it according to the needs of your\r\n**  project. Distribution of this file (unmodified or modified) is not\r\n**  permitted. Ac6 permit registered System Workbench for MCU users the\r\n**  rights to distribute the assembled, compiled & linked contents of this\r\n**  file as part of an application binary file, provided that it is built\r\n**  using the System Workbench for MCU toolchain.\r\n**\r\n*****************************************************************************\r\n*/\r\n\r\n/* Entry Point */\r\nENTRY(Reset_Handler)\r\n\r\n/* Highest address of the user mode stack */\r\n_estack = 0x2004FFFF;    /* end of RAM */\r\n/* Generate a link error if heap and stack don't fit into RAM */\r\n_Min_Heap_Size  = 0x2000;      /* required amount of heap  */\r\n_Min_Stack_Size = 0x2800; /* required amount of stack */\r\n\r\n/* Specify the memory areas */\r\nMEMORY\r\n{\r\n\r\nFLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 64K\t\t/* 1024K */\r\nMemory1 (xrw)   : ORIGIN = 0x20000000, LENGTH = 0xA0\r\nMemory2 (xrw)   : ORIGIN = 0x200000A0, LENGTH = 0xA0\r\nMemory3 (xrw)   : ORIGIN = 0x20000140, LENGTH = 0x1dc4\r\nMemory4 (xrw)   : ORIGIN = 0x20001F04, LENGTH = 0x1dc4\r\nRAM1 (xrw)      : ORIGIN = 0x20003CC8, LENGTH = 0x6024\r\nRAM2 (xrw)      : ORIGIN = 0x20009CEC, LENGTH = 0x7800\r\nRAM (xrw)       : ORIGIN = 0x200114EC, LENGTH = 0x3EB14\r\nQSPI (rx)       : ORIGIN = 0x90000000, LENGTH = 16M\r\n\r\n}\r\n\r\n/* Define output sections */\r\nSECTIONS\r\n{\r\n  /* The startup code goes first into FLASH */\r\n  .isr_vector :\r\n  {\r\n    . = ALIGN(4);\r\n    KEEP(*(.isr_vector)) /* Startup code */\r\n    . = ALIGN(4);\r\n  } >FLASH\r\n\r\n  /* The program code and other data goes into FLASH */\r\n  .text :\r\n  {\r\n    . = ALIGN(4);\r\n    *(.text)           /* .text sections (code) */\r\n    *(.text*)          /* .text* sections (code) */\r\n    *(.glue_7)         /* glue arm to thumb code */\r\n    *(.glue_7t)        /* glue thumb to arm code */\r\n    *(.eh_frame)\r\n\r\n    KEEP (*(.init))\r\n    KEEP (*(.fini))\r\n\r\n    . = ALIGN(4);\r\n    _etext = .;        /* define a global symbols at end of code */\r\n  } >FLASH\r\n\r\n  /* Constant data goes into FLASH */\r\n  .rodata :\r\n  {\r\n    . = ALIGN(4);\r\n    *(.rodata)         /* .rodata sections (constants, strings, etc.) */\r\n    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */\r\n    . = ALIGN(4);\r\n  } >FLASH\r\n\r\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\r\n  .ARM : {\r\n    __exidx_start = .;\r\n    *(.ARM.exidx*)\r\n    __exidx_end = .;\r\n  } >FLASH\r\n\r\n  .preinit_array     :\r\n  {\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP (*(.preinit_array*))\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n  } >FLASH\r\n  .init_array :\r\n  {\r\n    PROVIDE_HIDDEN (__init_array_start = .);\r\n    KEEP (*(SORT(.init_array.*)))\r\n    KEEP (*(.init_array*))\r\n    PROVIDE_HIDDEN (__init_array_end = .);\r\n  } >FLASH\r\n  .fini_array :\r\n  {\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    KEEP (*(.fini_array*))\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n  } >FLASH\r\n\r\n  /* used by the startup to initialize data */\r\n  _sidata = LOADADDR(.data);\r\n\r\n  /* Initialized data sections goes into RAM, load LMA copy after code */\r\n  .data : \r\n  {\r\n    . = ALIGN(4);\r\n    _sdata = .;        /* create a global symbol at data start */\r\n    *(.data)           /* .data sections */\r\n    *(.data*)          /* .data* sections */\r\n\r\n    . = ALIGN(4);\r\n    _edata = .;        /* define a global symbol at data end */\r\n  } >RAM AT> FLASH\r\n\r\n  \r\n  /* Uninitialized data section */\r\n  . = ALIGN(4);\r\n  .bss :\r\n  {\r\n    /* This is used by the startup in order to initialize the .bss secion */\r\n    _sbss = .;         /* define a global symbol at bss start */\r\n    __bss_start__ = _sbss;\r\n    *(.bss)\r\n    *(.bss*)\r\n    *(COMMON)\r\n\r\n    . = ALIGN(4);\r\n    _ebss = .;         /* define a global symbol at bss end */\r\n    __bss_end__ = _ebss;\r\n  } >RAM\r\n\r\n  /* User_heap_stack section, used to check that there is enough RAM left */\r\n  ._user_heap_stack :\r\n  {\r\n    . = ALIGN(4);\r\n    PROVIDE ( end = . );\r\n    PROVIDE ( _end = . );\r\n    . = . + _Min_Heap_Size;\r\n    . = . + _Min_Stack_Size;\r\n    . = ALIGN(4);\r\n  } >RAM\r\n\r\n  \r\n\r\n  /* Remove information from the standard libraries */\r\n  /DISCARD/ :\r\n  {\r\n    libc.a ( * )\r\n    libm.a ( * )\r\n    libgcc.a ( * )\r\n  }\r\n\r\n  .ARM.attributes 0 : { *(.ARM.attributes) }\r\n  .RxDecripSection (NOLOAD) : { *(.RxDecripSection) } >Memory1\r\n  .TxDescripSection (NOLOAD) : { *(.TxDescripSection) } >Memory2\r\n  .RxBUF (NOLOAD) : { *(.RxBUF) } >Memory3\r\n  .TxBUF (NOLOAD) : { *(.TxBUF) } >Memory4\r\n  .ExtQSPIFlashSection : { *(.ExtQSPIFlashSection) } >QSPI\r\n  .RamData1 (NOLOAD) : { *(.RamData1) } >RAM1\r\n  .RamData2 (NOLOAD): { *(.RamData2) } >RAM2\r\n}\r\n\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/led.c",
    "content": "/*\r\n *  led.c\r\n *\r\n *  Created on: 2016. 5. 14.\r\n *      Author: Baram, PBHP\r\n */\r\n\r\n#include \"led.h\"\r\n\r\n#define LED_MAX   1\r\n\r\n\r\nGPIO_TypeDef *pLedGpio[LED_MAX] = { GPIOG };\r\nuint16_t      LedGpioPin[LED_MAX] = { GPIO_PIN_9 };\r\n\r\n//GPIO_TypeDef *pLedGpio[1] = { GPIOB };\r\n//uint16_t      LedGpioPin[1] = { GPIO_PIN_7 };\r\n\r\n\r\n\r\nvoid led_init()\r\n{\r\n  uint8_t i;\r\n  GPIO_InitTypeDef GPIO_InitStruct;\r\n\r\n  // GPIO Ports Clock Enable\r\n  __HAL_RCC_GPIOG_CLK_ENABLE();\r\n\r\n\r\n  for( i=0; i<LED_MAX; i++ )\r\n  {\r\n    // Configure GPIO pin Output Level\r\n    HAL_GPIO_WritePin(pLedGpio[i], LedGpioPin[i], GPIO_PIN_RESET);\r\n\r\n    // Configure GPIO pin : PB7\r\n    GPIO_InitStruct.Pin = LedGpioPin[i];\r\n    GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;\r\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\r\n    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;\r\n    HAL_GPIO_Init(pLedGpio[i], &GPIO_InitStruct);\r\n  }\r\n}\r\n\r\nvoid led_on( uint8_t ch )\r\n{\r\n  switch( ch )\r\n  {\r\n    case 0:\r\n      HAL_GPIO_WritePin(pLedGpio[ch], LedGpioPin[ch], GPIO_PIN_SET);\r\n      break;\r\n  }\r\n}\r\n\r\nvoid led_off( uint8_t ch )\r\n{\r\n  switch( ch )\r\n  {\r\n    case 0:\r\n      HAL_GPIO_WritePin(pLedGpio[ch], LedGpioPin[ch], GPIO_PIN_RESET);\r\n      break;\r\n  }\r\n}\r\n\r\nvoid led_toggle( uint8_t ch )\r\n{\r\n  switch( ch )\r\n  {\r\n    case 0:\r\n      HAL_GPIO_TogglePin(pLedGpio[ch], LedGpioPin[ch]);\r\n      break;\r\n  }\r\n}\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/led.h",
    "content": "/*\r\n *  led.h\r\n *\r\n *  Created on: 2016. 5. 14.\r\n *      Author: Baram, PBHP\r\n */\r\n\r\n#ifndef LED_H\r\n#define LED_H\r\n\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n\r\n#include \"def.h\"\r\n#include \"bsp.h\"\r\n\r\n\r\nvoid led_init(void);\r\nvoid led_on(uint8_t ch);\r\nvoid led_off(uint8_t ch);\r\nvoid led_toggle(uint8_t ch);\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/usbd_cdc.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_cdc.c\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   This file provides the high layer firmware functions to manage the \r\n  *          following functionalities of the USB CDC Class:\r\n  *           - Initialization and Configuration of high and low layer\r\n  *           - Enumeration as CDC Device (and enumeration for each implemented memory interface)\r\n  *           - OUT/IN data transfer\r\n  *           - Command IN transfer (class requests management)\r\n  *           - Error management\r\n  *           \r\n  *  @verbatim\r\n  *      \r\n  *          ===================================================================      \r\n  *                                CDC Class Driver Description\r\n  *          =================================================================== \r\n  *           This driver manages the \"Universal Serial Bus Class Definitions for Communications Devices\r\n  *           Revision 1.2 November 16, 2007\" and the sub-protocol specification of \"Universal Serial Bus \r\n  *           Communications Class Subclass Specification for PSTN Devices Revision 1.2 February 9, 2007\"\r\n  *           This driver implements the following aspects of the specification:\r\n  *             - Device descriptor management\r\n  *             - Configuration descriptor management\r\n  *             - Enumeration as CDC device with 2 data endpoints (IN and OUT) and 1 command endpoint (IN)\r\n  *             - Requests management (as described in section 6.2 in specification)\r\n  *             - Abstract Control Model compliant\r\n  *             - Union Functional collection (using 1 IN endpoint for control)\r\n  *             - Data interface class\r\n  * \r\n  *           These aspects may be enriched or modified for a specific user application.\r\n  *          \r\n  *            This driver doesn't implement the following aspects of the specification \r\n  *            (but it is possible to manage these features with some modifications on this driver):\r\n  *             - Any class-specific aspect relative to communication classes should be managed by user application.\r\n  *             - All communication classes other than PSTN are not managed\r\n  *      \r\n  *  @endverbatim\r\n  *                                  \r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_cdc.h\"\r\n#include \"usbd_desc.h\"\r\n#include \"usbd_ctlreq.h\"\r\n\r\n\r\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n\r\n\r\n/** @defgroup USBD_CDC \r\n  * @brief usbd core module\r\n  * @{\r\n  */ \r\n\r\n/** @defgroup USBD_CDC_Private_TypesDefinitions\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_CDC_Private_Defines\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_CDC_Private_Macros\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_CDC_Private_FunctionPrototypes\r\n  * @{\r\n  */\r\n\r\n\r\nstatic uint8_t  USBD_CDC_Init (USBD_HandleTypeDef *pdev, \r\n                               uint8_t cfgidx);\r\n\r\nstatic uint8_t  USBD_CDC_DeInit (USBD_HandleTypeDef *pdev, \r\n                                 uint8_t cfgidx);\r\n\r\nstatic uint8_t  USBD_CDC_Setup (USBD_HandleTypeDef *pdev, \r\n                                USBD_SetupReqTypedef *req);\r\n\r\nstatic uint8_t  USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, \r\n                                 uint8_t epnum);\r\n\r\nstatic uint8_t  USBD_CDC_DataOut (USBD_HandleTypeDef *pdev, \r\n                                 uint8_t epnum);\r\n\r\nstatic uint8_t  USBD_CDC_EP0_RxReady (USBD_HandleTypeDef *pdev);\r\n\r\nstatic uint8_t  *USBD_CDC_GetFSCfgDesc (uint16_t *length);\r\n\r\nstatic uint8_t  *USBD_CDC_GetHSCfgDesc (uint16_t *length);\r\n\r\nstatic uint8_t  *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length);\r\n\r\nstatic uint8_t  *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length);\r\n\r\nuint8_t  *USBD_CDC_GetDeviceQualifierDescriptor (uint16_t *length);\r\n\r\n/* USB Standard Device Descriptor */\r\n__ALIGN_BEGIN static uint8_t USBD_CDC_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END =\r\n{\r\n  USB_LEN_DEV_QUALIFIER_DESC,\r\n  USB_DESC_TYPE_DEVICE_QUALIFIER,\r\n  0x00,\r\n  0x02,\r\n  0x00,\r\n  0x00,\r\n  0x00,\r\n  0x40,\r\n  0x01,\r\n  0x00,\r\n};\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_CDC_Private_Variables\r\n  * @{\r\n  */ \r\n\r\n\r\n/* CDC interface class callbacks structure */\r\nUSBD_ClassTypeDef  USBD_CDC = \r\n{\r\n  USBD_CDC_Init,\r\n  USBD_CDC_DeInit,\r\n  USBD_CDC_Setup,\r\n  NULL,                 /* EP0_TxSent, */\r\n  USBD_CDC_EP0_RxReady,\r\n  USBD_CDC_DataIn,\r\n  USBD_CDC_DataOut,\r\n  NULL,\r\n  NULL,\r\n  NULL,     \r\n  USBD_CDC_GetHSCfgDesc,  \r\n  USBD_CDC_GetFSCfgDesc,    \r\n  USBD_CDC_GetOtherSpeedCfgDesc, \r\n  USBD_CDC_GetDeviceQualifierDescriptor,\r\n};\r\n\r\n/* USB CDC device Configuration Descriptor */\r\n__ALIGN_BEGIN uint8_t USBD_CDC_CfgHSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END =\r\n{\r\n  /*Configuration Descriptor*/\r\n  0x09,   /* bLength: Configuration Descriptor size */\r\n  USB_DESC_TYPE_CONFIGURATION,      /* bDescriptorType: Configuration */\r\n  USB_CDC_CONFIG_DESC_SIZ,                /* wTotalLength:no of returned bytes */\r\n  0x00,\r\n  0x02,   /* bNumInterfaces: 2 interface */\r\n  0x01,   /* bConfigurationValue: Configuration value */\r\n  0x00,   /* iConfiguration: Index of string descriptor describing the configuration */\r\n  0xC0,   /* bmAttributes: self powered */\r\n  0x32,   /* MaxPower 0 mA */\r\n  \r\n  /*---------------------------------------------------------------------------*/\r\n  \r\n  /*Interface Descriptor */\r\n  0x09,   /* bLength: Interface Descriptor size */\r\n  USB_DESC_TYPE_INTERFACE,  /* bDescriptorType: Interface */\r\n  /* Interface descriptor type */\r\n  0x00,   /* bInterfaceNumber: Number of Interface */\r\n  0x00,   /* bAlternateSetting: Alternate setting */\r\n  0x01,   /* bNumEndpoints: One endpoints used */\r\n  0x02,   /* bInterfaceClass: Communication Interface Class */\r\n  0x02,   /* bInterfaceSubClass: Abstract Control Model */\r\n  0x01,   /* bInterfaceProtocol: Common AT commands */\r\n  0x00,   /* iInterface: */\r\n  \r\n  /*Header Functional Descriptor*/\r\n  0x05,   /* bLength: Endpoint Descriptor size */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x00,   /* bDescriptorSubtype: Header Func Desc */\r\n  0x10,   /* bcdCDC: spec release number */\r\n  0x01,\r\n  \r\n  /*Call Management Functional Descriptor*/\r\n  0x05,   /* bFunctionLength */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x01,   /* bDescriptorSubtype: Call Management Func Desc */\r\n  0x00,   /* bmCapabilities: D0+D1 */\r\n  0x01,   /* bDataInterface: 1 */\r\n  \r\n  /*ACM Functional Descriptor*/\r\n  0x04,   /* bFunctionLength */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x02,   /* bDescriptorSubtype: Abstract Control Management desc */\r\n  0x02,   /* bmCapabilities */\r\n  \r\n  /*Union Functional Descriptor*/\r\n  0x05,   /* bFunctionLength */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x06,   /* bDescriptorSubtype: Union func desc */\r\n  0x00,   /* bMasterInterface: Communication class interface */\r\n  0x01,   /* bSlaveInterface0: Data Class Interface */\r\n  \r\n  /*Endpoint 2 Descriptor*/\r\n  0x07,                           /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_ENDPOINT,   /* bDescriptorType: Endpoint */\r\n  CDC_CMD_EP,                     /* bEndpointAddress */\r\n  0x03,                           /* bmAttributes: Interrupt */\r\n  LOBYTE(CDC_CMD_PACKET_SIZE),     /* wMaxPacketSize: */\r\n  HIBYTE(CDC_CMD_PACKET_SIZE),\r\n  0x10,                           /* bInterval: */ \r\n  /*---------------------------------------------------------------------------*/\r\n  \r\n  /*Data class interface descriptor*/\r\n  0x09,   /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_INTERFACE,  /* bDescriptorType: */\r\n  0x01,   /* bInterfaceNumber: Number of Interface */\r\n  0x00,   /* bAlternateSetting: Alternate setting */\r\n  0x02,   /* bNumEndpoints: Two endpoints used */\r\n  0x0A,   /* bInterfaceClass: CDC */\r\n  0x00,   /* bInterfaceSubClass: */\r\n  0x00,   /* bInterfaceProtocol: */\r\n  0x00,   /* iInterface: */\r\n  \r\n  /*Endpoint OUT Descriptor*/\r\n  0x07,   /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_ENDPOINT,      /* bDescriptorType: Endpoint */\r\n  CDC_OUT_EP,                        /* bEndpointAddress */\r\n  0x02,                              /* bmAttributes: Bulk */\r\n  LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE),  /* wMaxPacketSize: */\r\n  HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE),\r\n  0x00,                              /* bInterval: ignore for Bulk transfer */\r\n  \r\n  /*Endpoint IN Descriptor*/\r\n  0x07,   /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_ENDPOINT,      /* bDescriptorType: Endpoint */\r\n  CDC_IN_EP,                         /* bEndpointAddress */\r\n  0x02,                              /* bmAttributes: Bulk */\r\n  LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE),  /* wMaxPacketSize: */\r\n  HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE),\r\n  0x00                               /* bInterval: ignore for Bulk transfer */\r\n} ;\r\n\r\n\r\n/* USB CDC device Configuration Descriptor */\r\n__ALIGN_BEGIN uint8_t USBD_CDC_CfgFSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END =\r\n{\r\n  /*Configuration Descriptor*/\r\n  0x09,   /* bLength: Configuration Descriptor size */\r\n  USB_DESC_TYPE_CONFIGURATION,      /* bDescriptorType: Configuration */\r\n  USB_CDC_CONFIG_DESC_SIZ,                /* wTotalLength:no of returned bytes */\r\n  0x00,\r\n  0x02,   /* bNumInterfaces: 2 interface */\r\n  0x01,   /* bConfigurationValue: Configuration value */\r\n  0x00,   /* iConfiguration: Index of string descriptor describing the configuration */\r\n  0xC0,   /* bmAttributes: self powered */\r\n  0x32,   /* MaxPower 0 mA */\r\n  \r\n  /*---------------------------------------------------------------------------*/\r\n  \r\n  /*Interface Descriptor */\r\n  0x09,   /* bLength: Interface Descriptor size */\r\n  USB_DESC_TYPE_INTERFACE,  /* bDescriptorType: Interface */\r\n  /* Interface descriptor type */\r\n  0x00,   /* bInterfaceNumber: Number of Interface */\r\n  0x00,   /* bAlternateSetting: Alternate setting */\r\n  0x01,   /* bNumEndpoints: One endpoints used */\r\n  0x02,   /* bInterfaceClass: Communication Interface Class */\r\n  0x02,   /* bInterfaceSubClass: Abstract Control Model */\r\n  0x01,   /* bInterfaceProtocol: Common AT commands */\r\n  0x00,   /* iInterface: */\r\n  \r\n  /*Header Functional Descriptor*/\r\n  0x05,   /* bLength: Endpoint Descriptor size */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x00,   /* bDescriptorSubtype: Header Func Desc */\r\n  0x10,   /* bcdCDC: spec release number */\r\n  0x01,\r\n  \r\n  /*Call Management Functional Descriptor*/\r\n  0x05,   /* bFunctionLength */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x01,   /* bDescriptorSubtype: Call Management Func Desc */\r\n  0x00,   /* bmCapabilities: D0+D1 */\r\n  0x01,   /* bDataInterface: 1 */\r\n  \r\n  /*ACM Functional Descriptor*/\r\n  0x04,   /* bFunctionLength */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x02,   /* bDescriptorSubtype: Abstract Control Management desc */\r\n  0x02,   /* bmCapabilities */\r\n  \r\n  /*Union Functional Descriptor*/\r\n  0x05,   /* bFunctionLength */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x06,   /* bDescriptorSubtype: Union func desc */\r\n  0x00,   /* bMasterInterface: Communication class interface */\r\n  0x01,   /* bSlaveInterface0: Data Class Interface */\r\n  \r\n  /*Endpoint 2 Descriptor*/\r\n  0x07,                           /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_ENDPOINT,   /* bDescriptorType: Endpoint */\r\n  CDC_CMD_EP,                     /* bEndpointAddress */\r\n  0x03,                           /* bmAttributes: Interrupt */\r\n  LOBYTE(CDC_CMD_PACKET_SIZE),     /* wMaxPacketSize: */\r\n  HIBYTE(CDC_CMD_PACKET_SIZE),\r\n  0x10,                           /* bInterval: */ \r\n  /*---------------------------------------------------------------------------*/\r\n  \r\n  /*Data class interface descriptor*/\r\n  0x09,   /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_INTERFACE,  /* bDescriptorType: */\r\n  0x01,   /* bInterfaceNumber: Number of Interface */\r\n  0x00,   /* bAlternateSetting: Alternate setting */\r\n  0x02,   /* bNumEndpoints: Two endpoints used */\r\n  0x0A,   /* bInterfaceClass: CDC */\r\n  0x00,   /* bInterfaceSubClass: */\r\n  0x00,   /* bInterfaceProtocol: */\r\n  0x00,   /* iInterface: */\r\n  \r\n  /*Endpoint OUT Descriptor*/\r\n  0x07,   /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_ENDPOINT,      /* bDescriptorType: Endpoint */\r\n  CDC_OUT_EP,                        /* bEndpointAddress */\r\n  0x02,                              /* bmAttributes: Bulk */\r\n  LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE),  /* wMaxPacketSize: */\r\n  HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE),\r\n  0x00,                              /* bInterval: ignore for Bulk transfer */\r\n  \r\n  /*Endpoint IN Descriptor*/\r\n  0x07,   /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_ENDPOINT,      /* bDescriptorType: Endpoint */\r\n  CDC_IN_EP,                         /* bEndpointAddress */\r\n  0x02,                              /* bmAttributes: Bulk */\r\n  LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE),  /* wMaxPacketSize: */\r\n  HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE),\r\n  0x00                               /* bInterval: ignore for Bulk transfer */\r\n} ;\r\n\r\n__ALIGN_BEGIN uint8_t USBD_CDC_OtherSpeedCfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END =\r\n{ \r\n  0x09,   /* bLength: Configuation Descriptor size */\r\n  USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION,   \r\n  USB_CDC_CONFIG_DESC_SIZ,\r\n  0x00,\r\n  0x02,   /* bNumInterfaces: 2 interfaces */\r\n  0x01,   /* bConfigurationValue: */\r\n  0x04,   /* iConfiguration: */\r\n  0xC0,   /* bmAttributes: */\r\n  0x32,   /* MaxPower 100 mA */  \r\n  \r\n  /*Interface Descriptor */\r\n  0x09,   /* bLength: Interface Descriptor size */\r\n  USB_DESC_TYPE_INTERFACE,  /* bDescriptorType: Interface */\r\n  /* Interface descriptor type */\r\n  0x00,   /* bInterfaceNumber: Number of Interface */\r\n  0x00,   /* bAlternateSetting: Alternate setting */\r\n  0x01,   /* bNumEndpoints: One endpoints used */\r\n  0x02,   /* bInterfaceClass: Communication Interface Class */\r\n  0x02,   /* bInterfaceSubClass: Abstract Control Model */\r\n  0x01,   /* bInterfaceProtocol: Common AT commands */\r\n  0x00,   /* iInterface: */\r\n  \r\n  /*Header Functional Descriptor*/\r\n  0x05,   /* bLength: Endpoint Descriptor size */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x00,   /* bDescriptorSubtype: Header Func Desc */\r\n  0x10,   /* bcdCDC: spec release number */\r\n  0x01,\r\n  \r\n  /*Call Management Functional Descriptor*/\r\n  0x05,   /* bFunctionLength */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x01,   /* bDescriptorSubtype: Call Management Func Desc */\r\n  0x00,   /* bmCapabilities: D0+D1 */\r\n  0x01,   /* bDataInterface: 1 */\r\n  \r\n  /*ACM Functional Descriptor*/\r\n  0x04,   /* bFunctionLength */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x02,   /* bDescriptorSubtype: Abstract Control Management desc */\r\n  0x02,   /* bmCapabilities */\r\n  \r\n  /*Union Functional Descriptor*/\r\n  0x05,   /* bFunctionLength */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x06,   /* bDescriptorSubtype: Union func desc */\r\n  0x00,   /* bMasterInterface: Communication class interface */\r\n  0x01,   /* bSlaveInterface0: Data Class Interface */\r\n  \r\n  /*Endpoint 2 Descriptor*/\r\n  0x07,                           /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_ENDPOINT      ,   /* bDescriptorType: Endpoint */\r\n  CDC_CMD_EP,                     /* bEndpointAddress */\r\n  0x03,                           /* bmAttributes: Interrupt */\r\n  LOBYTE(CDC_CMD_PACKET_SIZE),     /* wMaxPacketSize: */\r\n  HIBYTE(CDC_CMD_PACKET_SIZE),\r\n  0xFF,                           /* bInterval: */\r\n  \r\n  /*---------------------------------------------------------------------------*/\r\n  \r\n  /*Data class interface descriptor*/\r\n  0x09,   /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_INTERFACE,  /* bDescriptorType: */\r\n  0x01,   /* bInterfaceNumber: Number of Interface */\r\n  0x00,   /* bAlternateSetting: Alternate setting */\r\n  0x02,   /* bNumEndpoints: Two endpoints used */\r\n  0x0A,   /* bInterfaceClass: CDC */\r\n  0x00,   /* bInterfaceSubClass: */\r\n  0x00,   /* bInterfaceProtocol: */\r\n  0x00,   /* iInterface: */\r\n  \r\n  /*Endpoint OUT Descriptor*/\r\n  0x07,   /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_ENDPOINT,      /* bDescriptorType: Endpoint */\r\n  CDC_OUT_EP,                        /* bEndpointAddress */\r\n  0x02,                              /* bmAttributes: Bulk */\r\n  0x40,                              /* wMaxPacketSize: */\r\n  0x00,\r\n  0x00,                              /* bInterval: ignore for Bulk transfer */\r\n  \r\n  /*Endpoint IN Descriptor*/\r\n  0x07,   /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_ENDPOINT,     /* bDescriptorType: Endpoint */\r\n  CDC_IN_EP,                        /* bEndpointAddress */\r\n  0x02,                             /* bmAttributes: Bulk */\r\n  0x40,                             /* wMaxPacketSize: */\r\n  0x00,\r\n  0x00                              /* bInterval */\r\n};\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_CDC_Private_Functions\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @brief  USBD_CDC_Init\r\n  *         Initialize the CDC interface\r\n  * @param  pdev: device instance\r\n  * @param  cfgidx: Configuration index\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_CDC_Init (USBD_HandleTypeDef *pdev, \r\n                               uint8_t cfgidx)\r\n{\r\n  uint8_t ret = 0;\r\n  USBD_CDC_HandleTypeDef   *hcdc;\r\n  \r\n  if(pdev->dev_speed == USBD_SPEED_HIGH  ) \r\n  {  \r\n    /* Open EP IN */\r\n    USBD_LL_OpenEP(pdev,\r\n                   CDC_IN_EP,\r\n                   USBD_EP_TYPE_BULK,\r\n                   CDC_DATA_HS_IN_PACKET_SIZE);\r\n    \r\n    /* Open EP OUT */\r\n    USBD_LL_OpenEP(pdev,\r\n                   CDC_OUT_EP,\r\n                   USBD_EP_TYPE_BULK,\r\n                   CDC_DATA_HS_OUT_PACKET_SIZE);\r\n    \r\n  }\r\n  else\r\n  {\r\n    /* Open EP IN */\r\n    USBD_LL_OpenEP(pdev,\r\n                   CDC_IN_EP,\r\n                   USBD_EP_TYPE_BULK,\r\n                   CDC_DATA_FS_IN_PACKET_SIZE);\r\n    \r\n    /* Open EP OUT */\r\n    USBD_LL_OpenEP(pdev,\r\n                   CDC_OUT_EP,\r\n                   USBD_EP_TYPE_BULK,\r\n                   CDC_DATA_FS_OUT_PACKET_SIZE);\r\n  }\r\n  /* Open Command IN EP */\r\n  USBD_LL_OpenEP(pdev,\r\n                 CDC_CMD_EP,\r\n                 USBD_EP_TYPE_INTR,\r\n                 CDC_CMD_PACKET_SIZE);\r\n  \r\n    \r\n  pdev->pClassData = USBD_malloc(sizeof (USBD_CDC_HandleTypeDef));\r\n  \r\n  if(pdev->pClassData == NULL)\r\n  {\r\n    ret = 1; \r\n  }\r\n  else\r\n  {\r\n    hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\r\n    \r\n    /* Init  physical Interface components */\r\n    ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Init();\r\n    \r\n    /* Init Xfer states */\r\n    hcdc->TxState =0;\r\n    hcdc->RxState =0;\r\n       \r\n    if(pdev->dev_speed == USBD_SPEED_HIGH  ) \r\n    {      \r\n      /* Prepare Out endpoint to receive next packet */\r\n      USBD_LL_PrepareReceive(pdev,\r\n                             CDC_OUT_EP,\r\n                             hcdc->RxBuffer,\r\n                             CDC_DATA_HS_OUT_PACKET_SIZE);\r\n    }\r\n    else\r\n    {\r\n      /* Prepare Out endpoint to receive next packet */\r\n      USBD_LL_PrepareReceive(pdev,\r\n                             CDC_OUT_EP,\r\n                             hcdc->RxBuffer,\r\n                             CDC_DATA_FS_OUT_PACKET_SIZE);\r\n    }\r\n    \r\n    \r\n  }\r\n  return ret;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_CDC_Init\r\n  *         DeInitialize the CDC layer\r\n  * @param  pdev: device instance\r\n  * @param  cfgidx: Configuration index\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_CDC_DeInit (USBD_HandleTypeDef *pdev, \r\n                                 uint8_t cfgidx)\r\n{\r\n  uint8_t ret = 0;\r\n  \r\n  /* Open EP IN */\r\n  USBD_LL_CloseEP(pdev,\r\n              CDC_IN_EP);\r\n  \r\n  /* Open EP OUT */\r\n  USBD_LL_CloseEP(pdev,\r\n              CDC_OUT_EP);\r\n  \r\n  /* Open Command IN EP */\r\n  USBD_LL_CloseEP(pdev,\r\n              CDC_CMD_EP);\r\n  \r\n  \r\n  /* DeInit  physical Interface components */\r\n  if(pdev->pClassData != NULL)\r\n  {\r\n    ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->DeInit();\r\n    USBD_free(pdev->pClassData);\r\n    pdev->pClassData = NULL;\r\n  }\r\n  \r\n  return ret;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_CDC_Setup\r\n  *         Handle the CDC specific requests\r\n  * @param  pdev: instance\r\n  * @param  req: usb requests\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_CDC_Setup (USBD_HandleTypeDef *pdev, \r\n                                USBD_SetupReqTypedef *req)\r\n{\r\n  USBD_CDC_HandleTypeDef   *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\r\n  static uint8_t ifalt = 0;\r\n    \r\n  switch (req->bmRequest & USB_REQ_TYPE_MASK)\r\n  {\r\n  case USB_REQ_TYPE_CLASS :\r\n    if (req->wLength)\r\n    {\r\n      if (req->bmRequest & 0x80)\r\n      {\r\n        ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,\r\n                                                          (uint8_t *)hcdc->data,\r\n                                                          req->wLength);\r\n          USBD_CtlSendData (pdev, \r\n                            (uint8_t *)hcdc->data,\r\n                            req->wLength);\r\n      }\r\n      else\r\n      {\r\n        hcdc->CmdOpCode = req->bRequest;\r\n        hcdc->CmdLength = req->wLength;\r\n        \r\n        USBD_CtlPrepareRx (pdev, \r\n                           (uint8_t *)hcdc->data,\r\n                           req->wLength);\r\n      }\r\n      \r\n    }\r\n    else\r\n    {\r\n      ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,\r\n                                                        (uint8_t*)req,\r\n                                                        0);\r\n    }\r\n    break;\r\n\r\n  case USB_REQ_TYPE_STANDARD:\r\n    switch (req->bRequest)\r\n    {      \r\n    case USB_REQ_GET_INTERFACE :\r\n      USBD_CtlSendData (pdev,\r\n                        &ifalt,\r\n                        1);\r\n      break;\r\n      \r\n    case USB_REQ_SET_INTERFACE :\r\n      break;\r\n    }\r\n \r\n  default: \r\n    break;\r\n  }\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_CDC_DataIn\r\n  *         Data sent on non-control IN endpoint\r\n  * @param  pdev: device instance\r\n  * @param  epnum: endpoint number\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum)\r\n{\r\n  USBD_CDC_HandleTypeDef   *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\r\n  \r\n  if(pdev->pClassData != NULL)\r\n  {\r\n    \r\n    hcdc->TxState = 0;\r\n\r\n    return USBD_OK;\r\n  }\r\n  else\r\n  {\r\n    return USBD_FAIL;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  USBD_CDC_DataOut\r\n  *         Data received on non-control Out endpoint\r\n  * @param  pdev: device instance\r\n  * @param  epnum: endpoint number\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_CDC_DataOut (USBD_HandleTypeDef *pdev, uint8_t epnum)\r\n{      \r\n  USBD_CDC_HandleTypeDef   *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\r\n  \r\n  /* Get the received data length */\r\n  hcdc->RxLength = USBD_LL_GetRxDataSize (pdev, epnum);\r\n  \r\n  /* USB data will be immediately processed, this allow next USB traffic being \r\n  NAKed till the end of the application Xfer */\r\n  if(pdev->pClassData != NULL)\r\n  {\r\n    ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hcdc->RxBuffer, &hcdc->RxLength);\r\n\r\n    return USBD_OK;\r\n  }\r\n  else\r\n  {\r\n    return USBD_FAIL;\r\n  }\r\n}\r\n\r\n\r\n\r\n/**\r\n  * @brief  USBD_CDC_DataOut\r\n  *         Data received on non-control Out endpoint\r\n  * @param  pdev: device instance\r\n  * @param  epnum: endpoint number\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_CDC_EP0_RxReady (USBD_HandleTypeDef *pdev)\r\n{ \r\n  USBD_CDC_HandleTypeDef   *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\r\n  \r\n  if((pdev->pUserData != NULL) && (hcdc->CmdOpCode != 0xFF))\r\n  {\r\n    ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode,\r\n                                                      (uint8_t *)hcdc->data,\r\n                                                      hcdc->CmdLength);\r\n      hcdc->CmdOpCode = 0xFF; \r\n      \r\n  }\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_CDC_GetFSCfgDesc \r\n  *         Return configuration descriptor\r\n  * @param  speed : current device speed\r\n  * @param  length : pointer data length\r\n  * @retval pointer to descriptor buffer\r\n  */\r\nstatic uint8_t  *USBD_CDC_GetFSCfgDesc (uint16_t *length)\r\n{\r\n  *length = sizeof (USBD_CDC_CfgFSDesc);\r\n  return USBD_CDC_CfgFSDesc;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_CDC_GetHSCfgDesc \r\n  *         Return configuration descriptor\r\n  * @param  speed : current device speed\r\n  * @param  length : pointer data length\r\n  * @retval pointer to descriptor buffer\r\n  */\r\nstatic uint8_t  *USBD_CDC_GetHSCfgDesc (uint16_t *length)\r\n{\r\n  *length = sizeof (USBD_CDC_CfgHSDesc);\r\n  return USBD_CDC_CfgHSDesc;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_CDC_GetCfgDesc \r\n  *         Return configuration descriptor\r\n  * @param  speed : current device speed\r\n  * @param  length : pointer data length\r\n  * @retval pointer to descriptor buffer\r\n  */\r\nstatic uint8_t  *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length)\r\n{\r\n  *length = sizeof (USBD_CDC_OtherSpeedCfgDesc);\r\n  return USBD_CDC_OtherSpeedCfgDesc;\r\n}\r\n\r\n/**\r\n* @brief  DeviceQualifierDescriptor \r\n*         return Device Qualifier descriptor\r\n* @param  length : pointer data length\r\n* @retval pointer to descriptor buffer\r\n*/\r\nuint8_t  *USBD_CDC_GetDeviceQualifierDescriptor (uint16_t *length)\r\n{\r\n  *length = sizeof (USBD_CDC_DeviceQualifierDesc);\r\n  return USBD_CDC_DeviceQualifierDesc;\r\n}\r\n\r\n/**\r\n* @brief  USBD_CDC_RegisterInterface\r\n  * @param  pdev: device instance\r\n  * @param  fops: CD  Interface callback\r\n  * @retval status\r\n  */\r\nuint8_t  USBD_CDC_RegisterInterface  (USBD_HandleTypeDef   *pdev, \r\n                                      USBD_CDC_ItfTypeDef *fops)\r\n{\r\n  uint8_t  ret = USBD_FAIL;\r\n  \r\n  if(fops != NULL)\r\n  {\r\n    pdev->pUserData= fops;\r\n    ret = USBD_OK;    \r\n  }\r\n  \r\n  return ret;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_CDC_SetTxBuffer\r\n  * @param  pdev: device instance\r\n  * @param  pbuff: Tx Buffer\r\n  * @retval status\r\n  */\r\nuint8_t  USBD_CDC_SetTxBuffer  (USBD_HandleTypeDef   *pdev,\r\n                                uint8_t  *pbuff,\r\n                                uint16_t length)\r\n{\r\n  USBD_CDC_HandleTypeDef   *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\r\n  \r\n  hcdc->TxBuffer = pbuff;\r\n  hcdc->TxLength = length;  \r\n  \r\n  return USBD_OK;  \r\n}\r\n\r\n\r\n/**\r\n  * @brief  USBD_CDC_SetRxBuffer\r\n  * @param  pdev: device instance\r\n  * @param  pbuff: Rx Buffer\r\n  * @retval status\r\n  */\r\nuint8_t  USBD_CDC_SetRxBuffer  (USBD_HandleTypeDef   *pdev,\r\n                                   uint8_t  *pbuff)\r\n{\r\n  USBD_CDC_HandleTypeDef   *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\r\n  \r\n  hcdc->RxBuffer = pbuff;\r\n  \r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_CDC_DataOut\r\n  *         Data received on non-control Out endpoint\r\n  * @param  pdev: device instance\r\n  * @param  epnum: endpoint number\r\n  * @retval status\r\n  */\r\nuint8_t  USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev)\r\n{      \r\n  USBD_CDC_HandleTypeDef   *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\r\n  \r\n  if(pdev->pClassData != NULL)\r\n  {\r\n    if(hcdc->TxState == 0)\r\n    {\r\n      /* Tx Transfer in progress */\r\n      hcdc->TxState = 1;\r\n      \r\n      /* Transmit next packet */\r\n      USBD_LL_Transmit(pdev,\r\n                       CDC_IN_EP,\r\n                       hcdc->TxBuffer,\r\n                       hcdc->TxLength);\r\n      \r\n      return USBD_OK;\r\n    }\r\n    else\r\n    {\r\n      return USBD_BUSY;\r\n    }\r\n  }\r\n  else\r\n  {\r\n    return USBD_FAIL;\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  * @brief  USBD_CDC_ReceivePacket\r\n  *         prepare OUT Endpoint for reception\r\n  * @param  pdev: device instance\r\n  * @retval status\r\n  */\r\nuint8_t  USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev)\r\n{      \r\n  USBD_CDC_HandleTypeDef   *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\r\n  \r\n  /* Suspend or Resume USB Out process */\r\n  if(pdev->pClassData != NULL)\r\n  {\r\n    if(pdev->dev_speed == USBD_SPEED_HIGH  ) \r\n    {      \r\n      /* Prepare Out endpoint to receive next packet */\r\n      USBD_LL_PrepareReceive(pdev,\r\n                             CDC_OUT_EP,\r\n                             hcdc->RxBuffer,\r\n                             CDC_DATA_HS_OUT_PACKET_SIZE);\r\n    }\r\n    else\r\n    {\r\n      /* Prepare Out endpoint to receive next packet */\r\n      USBD_LL_PrepareReceive(pdev,\r\n                             CDC_OUT_EP,\r\n                             hcdc->RxBuffer,\r\n                             CDC_DATA_FS_OUT_PACKET_SIZE);\r\n    }\r\n    return USBD_OK;\r\n  }\r\n  else\r\n  {\r\n    return USBD_FAIL;\r\n  }\r\n}\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/usbd_cdc.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_cdc.h\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   header file for the usbd_cdc.c file.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n \r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __USB_CDC_H\r\n#define __USB_CDC_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include  \"usbd_ioreq.h\"\r\n\r\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup usbd_cdc\r\n  * @brief This file is the Header file for usbd_cdc.c\r\n  * @{\r\n  */ \r\n\r\n\r\n/** @defgroup usbd_cdc_Exported_Defines\r\n  * @{\r\n  */ \r\n#define CDC_IN_EP                                   0x81  /* EP1 for data IN */\r\n#define CDC_OUT_EP                                  0x01  /* EP1 for data OUT */\r\n#define CDC_CMD_EP                                  0x82  /* EP2 for CDC commands */\r\n\r\n/* CDC Endpoints parameters: you can fine tune these values depending on the needed baudrates and performance. */\r\n#define CDC_DATA_HS_MAX_PACKET_SIZE                 512  /* Endpoint IN & OUT Packet size */\r\n#define CDC_DATA_FS_MAX_PACKET_SIZE                 64  /* Endpoint IN & OUT Packet size */\r\n#define CDC_CMD_PACKET_SIZE                         8  /* Control Endpoint Packet size */ \r\n\r\n#define USB_CDC_CONFIG_DESC_SIZ                     67\r\n#define CDC_DATA_HS_IN_PACKET_SIZE                  CDC_DATA_HS_MAX_PACKET_SIZE\r\n#define CDC_DATA_HS_OUT_PACKET_SIZE                 CDC_DATA_HS_MAX_PACKET_SIZE\r\n\r\n#define CDC_DATA_FS_IN_PACKET_SIZE                  CDC_DATA_FS_MAX_PACKET_SIZE\r\n#define CDC_DATA_FS_OUT_PACKET_SIZE                 CDC_DATA_FS_MAX_PACKET_SIZE\r\n\r\n/*---------------------------------------------------------------------*/\r\n/*  CDC definitions                                                    */\r\n/*---------------------------------------------------------------------*/\r\n#define CDC_SEND_ENCAPSULATED_COMMAND               0x00\r\n#define CDC_GET_ENCAPSULATED_RESPONSE               0x01\r\n#define CDC_SET_COMM_FEATURE                        0x02\r\n#define CDC_GET_COMM_FEATURE                        0x03\r\n#define CDC_CLEAR_COMM_FEATURE                      0x04\r\n#define CDC_SET_LINE_CODING                         0x20\r\n#define CDC_GET_LINE_CODING                         0x21\r\n#define CDC_SET_CONTROL_LINE_STATE                  0x22\r\n#define CDC_SEND_BREAK                              0x23\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_CORE_Exported_TypesDefinitions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\ntypedef struct\r\n{\r\n  uint32_t bitrate;\r\n  uint8_t  format;\r\n  uint8_t  paritytype;\r\n  uint8_t  datatype;\r\n}USBD_CDC_LineCodingTypeDef;\r\n\r\ntypedef struct _USBD_CDC_Itf\r\n{\r\n  int8_t (* Init)          (void);\r\n  int8_t (* DeInit)        (void);\r\n  int8_t (* Control)       (uint8_t, uint8_t * , uint16_t);   \r\n  int8_t (* Receive)       (uint8_t *, uint32_t *);  \r\n\r\n}USBD_CDC_ItfTypeDef;\r\n\r\n\r\ntypedef struct\r\n{\r\n  uint32_t data[CDC_DATA_HS_MAX_PACKET_SIZE/4];      /* Force 32bits alignment */\r\n  uint8_t  CmdOpCode;\r\n  uint8_t  CmdLength;    \r\n  uint8_t  *RxBuffer;  \r\n  uint8_t  *TxBuffer;   \r\n  uint32_t RxLength;\r\n  uint32_t TxLength;    \r\n  \r\n  __IO uint32_t TxState;     \r\n  __IO uint32_t RxState;    \r\n}\r\nUSBD_CDC_HandleTypeDef; \r\n\r\n\r\n\r\n/** @defgroup USBD_CORE_Exported_Macros\r\n  * @{\r\n  */ \r\n  \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_CORE_Exported_Variables\r\n  * @{\r\n  */ \r\n\r\nextern USBD_ClassTypeDef  USBD_CDC;\r\n#define USBD_CDC_CLASS    &USBD_CDC\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USB_CORE_Exported_Functions\r\n  * @{\r\n  */\r\nuint8_t  USBD_CDC_RegisterInterface  (USBD_HandleTypeDef   *pdev, \r\n                                      USBD_CDC_ItfTypeDef *fops);\r\n\r\nuint8_t  USBD_CDC_SetTxBuffer        (USBD_HandleTypeDef   *pdev,\r\n                                      uint8_t  *pbuff,\r\n                                      uint16_t length);\r\n\r\nuint8_t  USBD_CDC_SetRxBuffer        (USBD_HandleTypeDef   *pdev,\r\n                                      uint8_t  *pbuff);\r\n  \r\nuint8_t  USBD_CDC_ReceivePacket      (USBD_HandleTypeDef *pdev);\r\n\r\nuint8_t  USBD_CDC_TransmitPacket     (USBD_HandleTypeDef *pdev);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif  /* __USB_CDC_H */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/usbd_cdc_interface.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    USB_Device/CDC_Standalone/Src/usbd_cdc_interface.c\r\n  * @author  MCD Application Team\r\n  * @version V1.0.3\r\n  * @date    18-November-2015\r\n  * @brief   Source file for USBD CDC interface\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software\r\n  * distributed under the License is distributed on an \"AS IS\" BASIS,\r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_cdc_interface.h\"\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n#define APP_RX_BUF_SIZE   (1024*16)\r\n#define APP_RX_DATA_SIZE  (1024)\r\n#define APP_TX_DATA_SIZE  (1024)\r\n\r\n\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\nUSBD_CDC_LineCodingTypeDef LineCoding =\r\n{\r\n  115200, /* baud rate*/\r\n  0x00,   /* stop bits-1*/\r\n  0x00,   /* parity - none*/\r\n  0x08    /* nb. of bits 8*/\r\n};\r\n\r\nuint8_t UserRxBuffer[APP_RX_DATA_SIZE];/* Received Data over USB are stored in this buffer */\r\nuint8_t UserTxBuffer[APP_TX_DATA_SIZE];/* Received Data over UART (CDC interface) are stored in this buffer */\r\nuint32_t BuffLength;\r\nvolatile uint32_t UserTxBufPtrIn = 0;/* Increment this pointer or roll it back to\r\n                               start address when data are received over USART */\r\nvolatile uint32_t UserTxBufPtrOut = 0; /* Increment this pointer or roll it back to\r\n                                 start address when data are sent over USB */\r\n\r\nstatic BOOL is_opened = FALSE;\r\nstatic BOOL is_reopen = FALSE;\r\n\r\nvolatile uint8_t  rxd_buffer[APP_RX_BUF_SIZE];\r\nvolatile uint32_t rxd_length    = 0;\r\nvolatile uint32_t rxd_BufPtrIn  = 0;\r\nvolatile uint32_t rxd_BufPtrOut = 0;\r\n\r\n\r\n/* USB handler declaration */\r\nextern USBD_HandleTypeDef  USBD_Device;\r\n\r\n/* Private function prototypes -----------------------------------------------*/\r\nstatic int8_t CDC_Itf_Init(void);\r\nstatic int8_t CDC_Itf_DeInit(void);\r\nstatic int8_t CDC_Itf_Control(uint8_t cmd, uint8_t* pbuf, uint16_t length);\r\nstatic int8_t CDC_Itf_Receive(uint8_t* pbuf, uint32_t *Len);\r\n\r\n\r\n\r\n\r\nUSBD_CDC_ItfTypeDef USBD_CDC_fops =\r\n{\r\n  CDC_Itf_Init,\r\n  CDC_Itf_DeInit,\r\n  CDC_Itf_Control,\r\n  CDC_Itf_Receive\r\n};\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/**\r\n  * @brief  CDC_Itf_Init\r\n  *         Initializes the CDC media low layer\r\n  * @param  None\r\n  * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL\r\n  */\r\nstatic int8_t CDC_Itf_Init(void)\r\n{\r\n  USBD_CDC_SetTxBuffer(&USBD_Device, UserTxBuffer, 0);\r\n  USBD_CDC_SetRxBuffer(&USBD_Device, UserRxBuffer);\r\n\r\n  return (USBD_OK);\r\n}\r\n\r\n/**\r\n  * @brief  CDC_Itf_DeInit\r\n  *         DeInitializes the CDC media low layer\r\n  * @param  None\r\n  * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL\r\n  */\r\nstatic int8_t CDC_Itf_DeInit(void)\r\n{\r\n  return (USBD_OK);\r\n}\r\n\r\n/**\r\n  * @brief  CDC_Itf_Control\r\n  *         Manage the CDC class requests\r\n  * @param  Cmd: Command code\r\n  * @param  Buf: Buffer containing command data (request parameters)\r\n  * @param  Len: Number of data to be sent (in bytes)\r\n  * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL\r\n  */\r\nstatic int8_t CDC_Itf_Control (uint8_t cmd, uint8_t* pbuf, uint16_t length)\r\n{\r\n  USBD_SetupReqTypedef *req = (USBD_SetupReqTypedef *)pbuf;\r\n\r\n\r\n  switch (cmd)\r\n  {\r\n  case CDC_SEND_ENCAPSULATED_COMMAND:\r\n    /* Add your code here */\r\n    break;\r\n\r\n  case CDC_GET_ENCAPSULATED_RESPONSE:\r\n    /* Add your code here */\r\n    break;\r\n\r\n  case CDC_SET_COMM_FEATURE:\r\n    /* Add your code here */\r\n    break;\r\n\r\n  case CDC_GET_COMM_FEATURE:\r\n    /* Add your code here */\r\n    break;\r\n\r\n  case CDC_CLEAR_COMM_FEATURE:\r\n    /* Add your code here */\r\n    break;\r\n\r\n  case CDC_SET_LINE_CODING:\r\n    LineCoding.bitrate    = (uint32_t)(pbuf[0] | (pbuf[1] << 8) |\\\r\n                            (pbuf[2] << 16) | (pbuf[3] << 24));\r\n    LineCoding.format     = pbuf[4];\r\n    LineCoding.paritytype = pbuf[5];\r\n    LineCoding.datatype   = pbuf[6];\r\n\r\n    is_opened = TRUE;\r\n    break;\r\n\r\n  case CDC_GET_LINE_CODING:\r\n    pbuf[0] = (uint8_t)(LineCoding.bitrate);\r\n    pbuf[1] = (uint8_t)(LineCoding.bitrate >> 8);\r\n    pbuf[2] = (uint8_t)(LineCoding.bitrate >> 16);\r\n    pbuf[3] = (uint8_t)(LineCoding.bitrate >> 24);\r\n    pbuf[4] = LineCoding.format;\r\n    pbuf[5] = LineCoding.paritytype;\r\n    pbuf[6] = LineCoding.datatype;\r\n    break;\r\n\r\n  case CDC_SET_CONTROL_LINE_STATE:\r\n    /* Add your code here */\r\n    is_opened = req->wValue&0x01;\r\n    is_reopen = TRUE;\r\n    break;\r\n\r\n  case CDC_SEND_BREAK:\r\n     /* Add your code here */\r\n    break;\r\n\r\n  default:\r\n    break;\r\n  }\r\n\r\n  return (USBD_OK);\r\n}\r\n\r\n\r\n/**\r\n  * @brief  CDC_Itf_DataRx\r\n  *         Data received over USB OUT endpoint are sent over CDC interface\r\n  *         through this function.\r\n  * @param  Buf: Buffer of data to be transmitted\r\n  * @param  Len: Number of data received (in bytes)\r\n  * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL\r\n  */\r\nstatic int8_t CDC_Itf_Receive(uint8_t* Buf, uint32_t *Len)\r\n{\r\n  uint32_t i;\r\n\r\n\r\n  for( i=0; i<*Len; i++ )\r\n  {\r\n    rxd_buffer[rxd_BufPtrIn] = Buf[i];\r\n\r\n    rxd_BufPtrIn++;\r\n\r\n    /* To avoid buffer overflow */\r\n    if(rxd_BufPtrIn == APP_RX_BUF_SIZE)\r\n    {\r\n      rxd_BufPtrIn = 0;\r\n    }\r\n  }\r\n\r\n\r\n  USBD_CDC_ReceivePacket(&USBD_Device);\r\n  return (USBD_OK);\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : CDC_Itf_Write\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nvoid CDC_Itf_Write( uint8_t *p_buf, uint32_t length )\r\n{\r\n  uint32_t i;\r\n  uint32_t remain_length = 0;\r\n  uint32_t tx_length = 0;\r\n  uint32_t write_length;\r\n  uint32_t written_length;\r\n  uint32_t tTime;\r\n  uint32_t time_out = 1000;\r\n  uint8_t  ret;\r\n  BOOL timeout_expired = FALSE;\r\n\r\n\r\n  if( USBD_Device.pClassData == NULL ) return;\r\n  if( is_opened == FALSE && is_reopen == FALSE ) return;\r\n  is_reopen = FALSE;\r\n\r\n\r\n  written_length = 0;\r\n  while(1)\r\n  {\r\n    write_length = length - written_length;\r\n\r\n    if( write_length > APP_TX_DATA_SIZE )  write_length = APP_TX_DATA_SIZE;\r\n    memcpy( UserTxBuffer, &p_buf[written_length], write_length );\r\n\r\n    USBD_CDC_SetTxBuffer(&USBD_Device, UserTxBuffer, write_length);\r\n\r\n    tTime = millis();\r\n    while(1)\r\n    {\r\n      ret = USBD_CDC_TransmitPacket(&USBD_Device);\r\n      if(ret == USBD_OK)\r\n      {\r\n        written_length += write_length;\r\n        is_opened = TRUE;\r\n        break;\r\n      }\r\n      else if(ret == USBD_BUSY)\r\n      {\r\n        if( (millis()-tTime) > time_out )\r\n        {\r\n          if( is_reopen == FALSE )\r\n          {\r\n            is_opened = FALSE;\r\n          }\r\n          timeout_expired = TRUE;\r\n          break;\r\n        }\r\n\r\n        if(USBD_Device.dev_state != USBD_STATE_CONFIGURED)\r\n        {\r\n          is_opened = FALSE;\r\n          break;\r\n        }\r\n      }\r\n      else\r\n      {\r\n        is_opened = FALSE;\r\n        break;\r\n      }\r\n    }\r\n\r\n    if( is_opened       == FALSE ) break;\r\n    if( timeout_expired == TRUE )  break;\r\n    if( written_length >= length ) break;\r\n  }\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : CDC_Itf_IsAvailable\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nBOOL CDC_Itf_IsAvailable( void )\r\n{\r\n  if( rxd_BufPtrIn != rxd_BufPtrOut ) return TRUE;\r\n\r\n  return FALSE;\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : CDC_Itf_Getch\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nuint8_t CDC_Itf_Getch( void )\r\n{\r\n  uint8_t ch = 0;\r\n  uint32_t buffptr;\r\n\r\n\r\n  while(1)\r\n  {\r\n    if( CDC_Itf_IsAvailable() ) break;\r\n  }\r\n\r\n\r\n\r\n  buffptr = rxd_BufPtrOut;\r\n\r\n  ch = rxd_buffer[buffptr];\r\n\r\n  __disable_irq();\r\n  rxd_BufPtrOut += 1;\r\n  if (rxd_BufPtrOut == APP_RX_BUF_SIZE)\r\n  {\r\n    rxd_BufPtrOut = 0;\r\n  }\r\n  __enable_irq();\r\n\r\n  return ch;\r\n}\r\n\r\n\r\n\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/usbd_cdc_interface.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    USB_Device/CDC_Standalone/Inc/usbd_cdc_interface.h\r\n  * @author  MCD Application Team\r\n  * @version V1.0.3\r\n  * @date    18-November-2015\r\n  * @brief   Header for usbd_cdc_interface.c file.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __USBD_CDC_IF_H\r\n#define __USBD_CDC_IF_H\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"def.h\"\r\n#include \"usbd_cdc.h\"\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n\r\n\r\n\r\nextern USBD_CDC_ItfTypeDef  USBD_CDC_fops;\r\n\r\n\r\n\r\nvoid    CDC_Itf_Write( uint8_t *p_buf, uint32_t length );\r\nBOOL    CDC_Itf_IsAvailable( void );\r\nuint8_t CDC_Itf_Getch( void );\r\n\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions ------------------------------------------------------- */\r\n#endif /* __USBD_CDC_IF_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/usbd_conf.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    USB_Device/CDC_Standalone/Src/usbd_conf.c\r\n  * @author  MCD Application Team\r\n  * @version V1.0.3\r\n  * @date    18-November-2015\r\n  * @brief   This file implements the USB Device library callbacks and MSP\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"bsp.h\"\r\n#include \"usbd_core.h\"\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\nPCD_HandleTypeDef hpcd;\r\n\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n  \r\n/*******************************************************************************\r\n                       PCD BSP Routines\r\n*******************************************************************************/\r\n\r\n/**\r\n  * @brief  Initializes the PCD MSP.\r\n  * @param  hpcd: PCD handle\r\n  * @retval None\r\n  */\r\nvoid HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)\r\n{\r\n  GPIO_InitTypeDef  GPIO_InitStruct;\r\n  \r\n  if(hpcd->Instance == USB_OTG_FS)\r\n  {\r\n    /* Configure USB FS GPIOs */\r\n    __HAL_RCC_GPIOA_CLK_ENABLE();\r\n    \r\n    /* Configure DM DP Pins */\r\n    GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);\r\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\r\n    GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;\r\n    GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;\r\n    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); \r\n    \r\n    if(hpcd->Init.vbus_sensing_enable == 1)\r\n    {\r\n      /* Configure VBUS Pin */\r\n      GPIO_InitStruct.Pin = GPIO_PIN_9;\r\n      GPIO_InitStruct.Mode = GPIO_MODE_INPUT;\r\n      GPIO_InitStruct.Pull = GPIO_NOPULL;\r\n      HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);      \r\n    }\r\n    \r\n    /* Configure ID pin */\r\n    GPIO_InitStruct.Pin = GPIO_PIN_10;\r\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;\r\n    GPIO_InitStruct.Pull = GPIO_PULLUP;\r\n    GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;\r\n    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\r\n    \r\n    /* Enable USB FS Clock */\r\n    __HAL_RCC_USB_OTG_FS_CLK_ENABLE();\r\n    \r\n    /* Set USBFS Interrupt priority */\r\n    HAL_NVIC_SetPriority(OTG_FS_IRQn, 6, 0);\r\n    \r\n    /* Enable USBFS Interrupt */\r\n    HAL_NVIC_EnableIRQ(OTG_FS_IRQn);    \r\n  }\r\n  else if(hpcd->Instance == USB_OTG_HS)\r\n  {\r\n#ifdef USE_USB_HS_IN_FS\r\n    \r\n    __HAL_RCC_GPIOB_CLK_ENABLE();\r\n    \r\n    /*Configure GPIO for HS on FS mode*/\r\n    GPIO_InitStruct.Pin = GPIO_PIN_12 | GPIO_PIN_14 |GPIO_PIN_15;\r\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\r\n    GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;\r\n    GPIO_InitStruct.Alternate = GPIO_AF12_OTG_HS_FS;\r\n    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\r\n    \r\n    if(hpcd->Init.vbus_sensing_enable == 1)\r\n    {\r\n      /* Configure VBUS Pin */\r\n      GPIO_InitStruct.Pin = GPIO_PIN_13 ;\r\n      GPIO_InitStruct.Mode = GPIO_MODE_INPUT;\r\n      GPIO_InitStruct.Pull = GPIO_NOPULL;\r\n      HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\r\n    }\r\n#else\r\n    /* Configure USB FS GPIOs */\r\n    __HAL_RCC_GPIOA_CLK_ENABLE();\r\n    __HAL_RCC_GPIOB_CLK_ENABLE();\r\n    __HAL_RCC_GPIOC_CLK_ENABLE();\r\n    __HAL_RCC_GPIOH_CLK_ENABLE();\r\n    __HAL_RCC_GPIOI_CLK_ENABLE();\r\n    \r\n    /* CLK */\r\n    GPIO_InitStruct.Pin = GPIO_PIN_5;\r\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\r\n    GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;\r\n    GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;\r\n    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\r\n    \r\n    /* D0 */\r\n    GPIO_InitStruct.Pin = GPIO_PIN_3;\r\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\r\n    GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;\r\n    GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;\r\n    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\r\n    \r\n    /* D1 D2 D3 D4 D5 D6 D7 */\r\n    GPIO_InitStruct.Pin = GPIO_PIN_0  | GPIO_PIN_1  | GPIO_PIN_5 |\\\r\n      GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13;\r\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\r\n    GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;\r\n    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\r\n    \r\n    /* STP */\r\n    GPIO_InitStruct.Pin = GPIO_PIN_0;\r\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\r\n    GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;\r\n    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);\r\n    \r\n    /* NXT */\r\n    GPIO_InitStruct.Pin = GPIO_PIN_4;\r\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\r\n    GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;\r\n    HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);\r\n    \r\n    /* DIR */\r\n    GPIO_InitStruct.Pin = GPIO_PIN_11;\r\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\r\n    GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;\r\n    HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);\r\n    __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE();\r\n#endif     \r\n    /* Enable USB HS Clocks */\r\n    __HAL_RCC_USB_OTG_HS_CLK_ENABLE();\r\n    \r\n    /* Set USBHS Interrupt to the lowest priority */\r\n    HAL_NVIC_SetPriority(OTG_HS_IRQn, 6, 0);\r\n    \r\n    /* Enable USBHS Interrupt */\r\n    HAL_NVIC_EnableIRQ(OTG_HS_IRQn);\r\n  }   \r\n}\r\n\r\n/**\r\n  * @brief  De-Initializes the PCD MSP.\r\n  * @param  hpcd: PCD handle\r\n  * @retval None\r\n  */\r\nvoid HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)\r\n{\r\n  if(hpcd->Instance == USB_OTG_FS)\r\n  {  \r\n    /* Disable USB FS Clock */\r\n    __HAL_RCC_USB_OTG_FS_CLK_DISABLE();\r\n    __HAL_RCC_SYSCFG_CLK_DISABLE();\r\n  }\r\n  else if(hpcd->Instance == USB_OTG_HS)\r\n  {  \r\n    /* Disable USB HS Clocks */\r\n    __HAL_RCC_USB_OTG_HS_CLK_DISABLE();\r\n    __HAL_RCC_SYSCFG_CLK_DISABLE();\r\n  }  \r\n}\r\n\r\n/*******************************************************************************\r\n                       LL Driver Callbacks (PCD -> USB Device Library)\r\n*******************************************************************************/\r\n\r\n/**\r\n  * @brief  SetupStage callback.\r\n  * @param  hpcd: PCD handle\r\n  * @retval None\r\n  */\r\nvoid HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)\r\n{\r\n  USBD_LL_SetupStage(hpcd->pData, (uint8_t *)hpcd->Setup);\r\n}\r\n\r\n/**\r\n  * @brief  DataOut Stage callback.\r\n  * @param  hpcd: PCD handle\r\n  * @param  epnum: Endpoint Number\r\n  * @retval None\r\n  */\r\nvoid HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\r\n{\r\n  USBD_LL_DataOutStage(hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff);\r\n}\r\n\r\n/**\r\n  * @brief  DataIn Stage callback.\r\n  * @param  hpcd: PCD handle\r\n  * @param  epnum: Endpoint Number\r\n  * @retval None\r\n  */\r\nvoid HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\r\n{\r\n  USBD_LL_DataInStage(hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff);\r\n}\r\n\r\n/**\r\n  * @brief  SOF callback.\r\n  * @param  hpcd: PCD handle\r\n  * @retval None\r\n  */\r\nvoid HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)\r\n{\r\n  USBD_LL_SOF(hpcd->pData);\r\n}\r\n\r\n/**\r\n  * @brief  Reset callback.\r\n  * @param  hpcd: PCD handle\r\n  * @retval None\r\n  */\r\nvoid HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)\r\n{   \r\n  USBD_SpeedTypeDef speed = USBD_SPEED_FULL;\r\n  \r\n  /* Set USB Current Speed */\r\n  switch(hpcd->Init.speed)\r\n  {\r\n  case PCD_SPEED_HIGH:\r\n    speed = USBD_SPEED_HIGH;\r\n    break;\r\n    \r\n  case PCD_SPEED_FULL:\r\n    speed = USBD_SPEED_FULL;\r\n    break;   \r\n    \r\n  default:\r\n    speed = USBD_SPEED_FULL;\r\n    break;\r\n  }\r\n  \r\n  /* Reset Device */\r\n  USBD_LL_Reset(hpcd->pData);\r\n  \r\n  USBD_LL_SetSpeed(hpcd->pData, speed);\r\n}\r\n\r\n/**\r\n  * @brief  Suspend callback.\r\n  * @param  hpcd: PCD handle\r\n  * @retval None\r\n  */\r\nvoid HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)\r\n{\r\n  USBD_LL_Suspend(hpcd->pData);\r\n}\r\n\r\n/**\r\n  * @brief  Resume callback.\r\n  * @param  hpcd: PCD handle\r\n  * @retval None\r\n  */\r\nvoid HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)\r\n{\r\n  USBD_LL_Resume(hpcd->pData);\r\n}\r\n\r\n/**\r\n  * @brief  ISOOUTIncomplete callback.\r\n  * @param  hpcd: PCD handle \r\n  * @param  epnum: Endpoint Number\r\n  * @retval None\r\n  */\r\nvoid HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\r\n{\r\n  USBD_LL_IsoOUTIncomplete(hpcd->pData, epnum);\r\n}\r\n\r\n/**\r\n  * @brief  ISOINIncomplete callback.\r\n  * @param  hpcd: PCD handle \r\n  * @param  epnum: Endpoint Number\r\n  * @retval None\r\n  */\r\nvoid HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\r\n{\r\n  USBD_LL_IsoINIncomplete(hpcd->pData, epnum);\r\n}\r\n\r\n/**\r\n  * @brief  ConnectCallback callback.\r\n  * @param  hpcd: PCD handle\r\n  * @retval None\r\n  */\r\nvoid HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)\r\n{\r\n  USBD_LL_DevConnected(hpcd->pData);\r\n}\r\n\r\n/**\r\n  * @brief  Disconnect callback.\r\n  * @param  hpcd: PCD handle\r\n  * @retval None\r\n  */\r\nvoid HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)\r\n{\r\n  USBD_LL_DevDisconnected(hpcd->pData);\r\n}\r\n\r\n\r\n/*******************************************************************************\r\n                       LL Driver Interface (USB Device Library --> PCD)\r\n*******************************************************************************/\r\n\r\n/**\r\n  * @brief  Initializes the Low Level portion of the Device driver.\r\n  * @param  pdev: Device handle\r\n  * @retval USBD Status\r\n  */\r\nUSBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)\r\n{\r\n#ifdef USE_USB_FS\r\n  /* Set LL Driver parameters */\r\n  hpcd.Instance = USB_OTG_FS;\r\n  hpcd.Init.dev_endpoints = 4;\r\n  hpcd.Init.use_dedicated_ep1 = 0;\r\n  hpcd.Init.ep0_mps = 0x40;\r\n  hpcd.Init.dma_enable = 0;\r\n  hpcd.Init.low_power_enable = 0;\r\n  hpcd.Init.phy_itface = PCD_PHY_EMBEDDED;\r\n  hpcd.Init.Sof_enable = 0;\r\n  hpcd.Init.speed = PCD_SPEED_FULL;\r\n  hpcd.Init.vbus_sensing_enable = 0;\r\n  hpcd.Init.lpm_enable = 0;\r\n  \r\n  /* Link The driver to the stack */\r\n  hpcd.pData = pdev;\r\n  pdev->pData = &hpcd;\r\n  \r\n  /* Initialize LL Driver */\r\n  HAL_PCD_Init(&hpcd);\r\n  \r\n  HAL_PCDEx_SetRxFiFo(&hpcd, 0x80);\r\n  HAL_PCDEx_SetTxFiFo(&hpcd, 0, 0x40);\r\n  HAL_PCDEx_SetTxFiFo(&hpcd, 1, 0x80);\r\n#endif\r\n  \r\n#ifdef USE_USB_HS\r\n  /* Set LL Driver parameters */\r\n  hpcd.Instance = USB_OTG_HS;\r\n  hpcd.Init.dev_endpoints = 6;\r\n  hpcd.Init.use_dedicated_ep1 = 0;\r\n  hpcd.Init.ep0_mps = 0x40;\r\n  \r\n  /* Be aware that enabling DMA mode will result in data being sent only by\r\n  multiple of 4 packet sizes. This is due to the fact that USB DMA does\r\n  not allow sending data from non word-aligned addresses.\r\n  For this specific application, it is advised to not enable this option\r\n  unless required. */\r\n  hpcd.Init.dma_enable = 0;\r\n  hpcd.Init.low_power_enable = 0;\r\n  hpcd.Init.lpm_enable = 0;\r\n  \r\n#ifdef USE_USB_HS_IN_FS\r\n  hpcd.Init.phy_itface = PCD_PHY_EMBEDDED; \r\n#else  \r\n  hpcd.Init.phy_itface = PCD_PHY_ULPI; \r\n#endif \r\n  hpcd.Init.Sof_enable = 0;\r\n  hpcd.Init.speed = PCD_SPEED_HIGH;\r\n  hpcd.Init.vbus_sensing_enable = 1;\r\n  \r\n  /* Link The driver to the stack */\r\n  hpcd.pData = pdev;\r\n  pdev->pData = &hpcd;\r\n  \r\n  /* Initialize LL Driver */\r\n  HAL_PCD_Init(&hpcd);\r\n  \r\n  HAL_PCDEx_SetRxFiFo(&hpcd, 0x200);\r\n  HAL_PCDEx_SetTxFiFo(&hpcd, 0, 0x80);\r\n  HAL_PCDEx_SetTxFiFo(&hpcd, 1, 0x174);\r\n#endif \r\n  \r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  De-Initializes the Low Level portion of the Device driver.\r\n  * @param  pdev: Device handle\r\n  * @retval USBD Status\r\n  */\r\nUSBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev)\r\n{\r\n  HAL_PCD_DeInit(pdev->pData);\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the Low Level portion of the Device driver. \r\n  * @param  pdev: Device handle\r\n  * @retval USBD Status\r\n  */\r\nUSBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev)\r\n{\r\n  HAL_PCD_Start(pdev->pData);\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the Low Level portion of the Device driver.\r\n  * @param  pdev: Device handle\r\n  * @retval USBD Status\r\n  */\r\nUSBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev)\r\n{\r\n  HAL_PCD_Stop(pdev->pData);\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Opens an endpoint of the Low Level Driver.\r\n  * @param  pdev: Device handle\r\n  * @param  ep_addr: Endpoint Number\r\n  * @param  ep_type: Endpoint Type\r\n  * @param  ep_mps: Endpoint Max Packet Size\r\n  * @retval USBD Status\r\n  */\r\nUSBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev,\r\n                                  uint8_t ep_addr,\r\n                                  uint8_t ep_type,\r\n                                  uint16_t ep_mps)\r\n{\r\n  HAL_PCD_EP_Open(pdev->pData,\r\n                  ep_addr,\r\n                  ep_mps,\r\n                  ep_type);\r\n  \r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Closes an endpoint of the Low Level Driver.\r\n  * @param  pdev: Device handle\r\n  * @param  ep_addr: Endpoint Number\r\n  * @retval USBD Status\r\n  */\r\nUSBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)\r\n{\r\n  HAL_PCD_EP_Close(pdev->pData, ep_addr);\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Flushes an endpoint of the Low Level Driver.\r\n  * @param  pdev: Device handle\r\n  * @param  ep_addr: Endpoint Number\r\n  * @retval USBD Status\r\n  */\r\nUSBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)\r\n{\r\n  HAL_PCD_EP_Flush(pdev->pData, ep_addr);\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Sets a Stall condition on an endpoint of the Low Level Driver.\r\n  * @param  pdev: Device handle\r\n  * @param  ep_addr: Endpoint Number\r\n  * @retval USBD Status\r\n  */\r\nUSBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)\r\n{\r\n  HAL_PCD_EP_SetStall(pdev->pData, ep_addr);\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Clears a Stall condition on an endpoint of the Low Level Driver.\r\n  * @param  pdev: Device handle\r\n  * @param  ep_addr: Endpoint Number\r\n  * @retval USBD Status\r\n  */\r\nUSBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)\r\n{\r\n  HAL_PCD_EP_ClrStall(pdev->pData, ep_addr);\r\n  return USBD_OK; \r\n}\r\n\r\n/**\r\n  * @brief  Returns Stall condition.\r\n  * @param  pdev: Device handle\r\n  * @param  ep_addr: Endpoint Number\r\n  * @retval Stall (1: Yes, 0: No)\r\n  */\r\nuint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)\r\n{\r\n  PCD_HandleTypeDef *hpcd = pdev->pData;\r\n  \r\n  if((ep_addr & 0x80) == 0x80)\r\n  {\r\n    return hpcd->IN_ep[ep_addr & 0x7F].is_stall;\r\n  }\r\n  else\r\n  {\r\n    return hpcd->OUT_ep[ep_addr & 0x7F].is_stall;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Assigns a USB address to the device.\r\n  * @param  pdev: Device handle\r\n  * @param  ep_addr: Endpoint Number\r\n  * @retval USBD Status\r\n  */\r\nUSBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr)\r\n{\r\n  HAL_PCD_SetAddress(pdev->pData, dev_addr);\r\n  return USBD_OK; \r\n}\r\n\r\n/**\r\n  * @brief  Transmits data over an endpoint.\r\n  * @param  pdev: Device handle\r\n  * @param  ep_addr: Endpoint Number\r\n  * @param  pbuf: Pointer to data to be sent\r\n  * @param  size: Data size    \r\n  * @retval USBD Status\r\n  */\r\nUSBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, \r\n                                    uint8_t ep_addr,\r\n                                    uint8_t *pbuf,\r\n                                    uint16_t size)\r\n{\r\n  HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size);\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Prepares an endpoint for reception.\r\n  * @param  pdev: Device handle\r\n  * @param  ep_addr: Endpoint Number\r\n  * @param  pbuf: Pointer to data to be received\r\n  * @param  size: Data size\r\n  * @retval USBD Status\r\n  */\r\nUSBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, \r\n                                          uint8_t ep_addr,\r\n                                          uint8_t *pbuf,\r\n                                          uint16_t size)\r\n{\r\n  HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size);\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the last transferred packet size.\r\n  * @param  pdev: Device handle\r\n  * @param  ep_addr: Endpoint Number\r\n  * @retval Received Data Size\r\n  */\r\nuint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr)\r\n{\r\n  return HAL_PCD_EP_GetRxCount(pdev->pData, ep_addr);\r\n}\r\n\r\n/**\r\n  * @brief  Delays routine for the USB Device Library.\r\n  * @param  Delay: Delay in ms\r\n  * @retval None\r\n  */\r\nvoid USBD_LL_Delay(uint32_t Delay)\r\n{\r\n  HAL_Delay(Delay);\r\n}\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/usbd_conf.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    USB_Device/CDC_Standalone/Inc/usbd_conf.h\r\n  * @author  MCD Application Team\r\n  * @version V1.0.3\r\n  * @date    18-November-2015\r\n  * @brief   General low level driver configuration\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __USBD_CONF_H\r\n#define __USBD_CONF_H\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n#include <stdio.h>\r\n#include <stdlib.h>\r\n#include <string.h>\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n/* Common Config */\r\n#define USBD_MAX_NUM_INTERFACES               1\r\n#define USBD_MAX_NUM_CONFIGURATION            1\r\n#define USBD_MAX_STR_DESC_SIZ                 0x100\r\n#define USBD_SUPPORT_USER_STRING              0 \r\n#define USBD_SELF_POWERED                     1\r\n#define USBD_DEBUG_LEVEL                      0\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Memory management macros */   \r\n#define USBD_malloc               malloc\r\n#define USBD_free                 free\r\n#define USBD_memset               memset\r\n#define USBD_memcpy               memcpy\r\n    \r\n/* DEBUG macros */  \r\n#if (USBD_DEBUG_LEVEL > 0)\r\n#define  USBD_UsrLog(...)   printf(__VA_ARGS__);\\\r\n                            printf(\"\\n\");\r\n#else\r\n#define USBD_UsrLog(...)   \r\n#endif                            \r\n                            \r\n#if (USBD_DEBUG_LEVEL > 1)\r\n\r\n#define  USBD_ErrLog(...)   printf(\"ERROR: \") ;\\\r\n                            printf(__VA_ARGS__);\\\r\n                            printf(\"\\n\");\r\n#else\r\n#define USBD_ErrLog(...)   \r\n#endif \r\n                                                        \r\n#if (USBD_DEBUG_LEVEL > 2)                         \r\n#define  USBD_DbgLog(...)   printf(\"DEBUG : \") ;\\\r\n                            printf(__VA_ARGS__);\\\r\n                            printf(\"\\n\");\r\n#else\r\n#define USBD_DbgLog(...)                         \r\n#endif\r\n\r\n/* Exported functions ------------------------------------------------------- */\r\n\r\n#endif /* __USBD_CONF_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/usbd_desc.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    USB_Device/CDC_Standalone/Src/usbd_desc.c\r\n  * @author  MCD Application Team\r\n  * @version V1.0.3\r\n  * @date    18-November-2015\r\n  * @brief   This file provides the USBD descriptors and string formating method.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_core.h\"\r\n#include \"usbd_desc.h\"\r\n#include \"usbd_conf.h\"\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n#define USBD_VID                      0x0483\r\n#define USBD_PID                      0x5740\r\n//#define USBD_VID                      0xFFF1\r\n//#define USBD_PID                      0xFF48\r\n\r\n#define USBD_LANGID_STRING            0x409\r\n#define USBD_MANUFACTURER_STRING      \"ROBOTIS\"\r\n#define USBD_PRODUCT_HS_STRING        \"OpenCR Virtual ComPort in HS Mode\"\r\n#define USBD_PRODUCT_FS_STRING        \"OpenCR Virtual ComPort in FS Mode\"\r\n#define USBD_CONFIGURATION_HS_STRING  \"VCP Config\"\r\n#define USBD_INTERFACE_HS_STRING      \"VCP Interface\"\r\n#define USBD_CONFIGURATION_FS_STRING  \"VCP Config\"\r\n#define USBD_INTERFACE_FS_STRING      \"VCP Interface\"\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\nuint8_t *USBD_VCP_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);\r\nuint8_t *USBD_VCP_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);\r\nuint8_t *USBD_VCP_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);\r\nuint8_t *USBD_VCP_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);\r\nuint8_t *USBD_VCP_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);\r\nuint8_t *USBD_VCP_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);\r\nuint8_t *USBD_VCP_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);\r\n#ifdef USB_SUPPORT_USER_STRING_DESC\r\nuint8_t *USBD_VCP_USRStringDesc (USBD_SpeedTypeDef speed, uint8_t idx, uint16_t *length);  \r\n#endif /* USB_SUPPORT_USER_STRING_DESC */  \r\n\r\n/* Private variables ---------------------------------------------------------*/\r\nUSBD_DescriptorsTypeDef VCP_Desc = {\r\n  USBD_VCP_DeviceDescriptor,\r\n  USBD_VCP_LangIDStrDescriptor, \r\n  USBD_VCP_ManufacturerStrDescriptor,\r\n  USBD_VCP_ProductStrDescriptor,\r\n  USBD_VCP_SerialStrDescriptor,\r\n  USBD_VCP_ConfigStrDescriptor,\r\n  USBD_VCP_InterfaceStrDescriptor,  \r\n};\r\n\r\n/* USB Standard Device Descriptor */\r\n#if defined ( __ICCARM__ ) /*!< IAR Compiler */\r\n  #pragma data_alignment=4   \r\n#endif\r\n__ALIGN_BEGIN uint8_t USBD_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END = {\r\n  0x12,                       /* bLength */\r\n  USB_DESC_TYPE_DEVICE,       /* bDescriptorType */\r\n  0x00,                       /* bcdUSB */\r\n  0x02,\r\n  0x02,                       /* bDeviceClass */\r\n  0x00,                       /* bDeviceSubClass */\r\n  0x00,                       /* bDeviceProtocol */\r\n  USB_MAX_EP0_SIZE,           /* bMaxPacketSize */\r\n  LOBYTE(USBD_VID),           /* idVendor */\r\n  HIBYTE(USBD_VID),           /* idVendor */\r\n  LOBYTE(USBD_PID),           /* idVendor */\r\n  HIBYTE(USBD_PID),           /* idVendor */\r\n  0x00,                       /* bcdDevice rel. 2.00 */\r\n  0x02,\r\n  USBD_IDX_MFC_STR,           /* Index of manufacturer string */\r\n  USBD_IDX_PRODUCT_STR,       /* Index of product string */\r\n  USBD_IDX_SERIAL_STR,        /* Index of serial number string */\r\n  USBD_MAX_NUM_CONFIGURATION  /* bNumConfigurations */\r\n}; /* USB_DeviceDescriptor */\r\n\r\n/* USB Standard Device Descriptor */\r\n#if defined ( __ICCARM__ ) /*!< IAR Compiler */\r\n  #pragma data_alignment=4   \r\n#endif\r\n__ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_LEN_LANGID_STR_DESC] __ALIGN_END = {\r\n  USB_LEN_LANGID_STR_DESC,         \r\n  USB_DESC_TYPE_STRING,       \r\n  LOBYTE(USBD_LANGID_STRING),\r\n  HIBYTE(USBD_LANGID_STRING), \r\n};\r\n\r\nuint8_t USBD_StringSerial[USB_SIZ_STRING_SERIAL] =\r\n{\r\n  USB_SIZ_STRING_SERIAL,      \r\n  USB_DESC_TYPE_STRING,    \r\n};\r\n\r\n#if defined ( __ICCARM__ ) /*!< IAR Compiler */\r\n  #pragma data_alignment=4   \r\n#endif\r\n__ALIGN_BEGIN uint8_t USBD_StrDesc[USBD_MAX_STR_DESC_SIZ] __ALIGN_END;\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\nstatic void IntToUnicode (uint32_t value , uint8_t *pbuf , uint8_t len);\r\nstatic void Get_SerialNum(void);\r\n\r\n/**\r\n  * @brief  Returns the device descriptor. \r\n  * @param  speed: Current device speed\r\n  * @param  length: Pointer to data length variable\r\n  * @retval Pointer to descriptor buffer\r\n  */\r\nuint8_t *USBD_VCP_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)\r\n{\r\n  *length = sizeof(USBD_DeviceDesc);\r\n  return (uint8_t*)USBD_DeviceDesc;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the LangID string descriptor.        \r\n  * @param  speed: Current device speed\r\n  * @param  length: Pointer to data length variable\r\n  * @retval Pointer to descriptor buffer\r\n  */\r\nuint8_t *USBD_VCP_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)\r\n{\r\n  *length = sizeof(USBD_LangIDDesc);  \r\n  return (uint8_t*)USBD_LangIDDesc;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the product string descriptor. \r\n  * @param  speed: Current device speed\r\n  * @param  length: Pointer to data length variable\r\n  * @retval Pointer to descriptor buffer\r\n  */\r\nuint8_t *USBD_VCP_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)\r\n{\r\n  if(speed == USBD_SPEED_HIGH)\r\n  {   \r\n    USBD_GetString((uint8_t *)USBD_PRODUCT_HS_STRING, USBD_StrDesc, length);\r\n  }\r\n  else\r\n  {\r\n    USBD_GetString((uint8_t *)USBD_PRODUCT_FS_STRING, USBD_StrDesc, length);    \r\n  }\r\n  return USBD_StrDesc;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the manufacturer string descriptor. \r\n  * @param  speed: Current device speed\r\n  * @param  length: Pointer to data length variable\r\n  * @retval Pointer to descriptor buffer\r\n  */\r\nuint8_t *USBD_VCP_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)\r\n{\r\n  USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length);\r\n  return USBD_StrDesc;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the serial number string descriptor.        \r\n  * @param  speed: Current device speed\r\n  * @param  length: Pointer to data length variable\r\n  * @retval Pointer to descriptor buffer\r\n  */\r\nuint8_t *USBD_VCP_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)\r\n{\r\n  *length = USB_SIZ_STRING_SERIAL;\r\n  \r\n  /* Update the serial number string descriptor with the data from the unique ID*/\r\n  Get_SerialNum();\r\n  \r\n  return (uint8_t*)USBD_StringSerial;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the configuration string descriptor.    \r\n  * @param  speed: Current device speed\r\n  * @param  length: Pointer to data length variable\r\n  * @retval Pointer to descriptor buffer\r\n  */\r\nuint8_t *USBD_VCP_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)\r\n{\r\n  if(speed == USBD_SPEED_HIGH)\r\n  {  \r\n    USBD_GetString((uint8_t *)USBD_CONFIGURATION_HS_STRING, USBD_StrDesc, length);\r\n  }\r\n  else\r\n  {\r\n    USBD_GetString((uint8_t *)USBD_CONFIGURATION_FS_STRING, USBD_StrDesc, length); \r\n  }\r\n  return USBD_StrDesc;  \r\n}\r\n\r\n/**\r\n  * @brief  Returns the interface string descriptor.        \r\n  * @param  speed: Current device speed\r\n  * @param  length: Pointer to data length variable\r\n  * @retval Pointer to descriptor buffer\r\n  */\r\nuint8_t *USBD_VCP_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)\r\n{\r\n  if(speed == USBD_SPEED_HIGH)\r\n  {\r\n    USBD_GetString((uint8_t *)USBD_INTERFACE_HS_STRING, USBD_StrDesc, length);\r\n  }\r\n  else\r\n  {\r\n    USBD_GetString((uint8_t *)USBD_INTERFACE_FS_STRING, USBD_StrDesc, length);\r\n  }\r\n  return USBD_StrDesc;  \r\n}\r\n\r\n/**\r\n  * @brief  Create the serial number string descriptor \r\n  * @param  None \r\n  * @retval None\r\n  */\r\nstatic void Get_SerialNum(void)\r\n{\r\n  uint32_t deviceserial0, deviceserial1, deviceserial2;\r\n  \r\n  deviceserial0 = *(uint32_t*)DEVICE_ID1;\r\n  deviceserial1 = *(uint32_t*)DEVICE_ID2;\r\n  deviceserial2 = *(uint32_t*)DEVICE_ID3;\r\n  \r\n  deviceserial0 += deviceserial2;\r\n  \r\n  if (deviceserial0 != 0)\r\n  {\r\n    IntToUnicode (deviceserial0, &USBD_StringSerial[2] ,8);\r\n    IntToUnicode (deviceserial1, &USBD_StringSerial[18] ,4);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Convert Hex 32Bits value into char \r\n  * @param  value: value to convert\r\n  * @param  pbuf: pointer to the buffer \r\n  * @param  len: buffer length\r\n  * @retval None\r\n  */\r\nstatic void IntToUnicode (uint32_t value , uint8_t *pbuf , uint8_t len)\r\n{\r\n  uint8_t idx = 0;\r\n  \r\n  for( idx = 0; idx < len; idx ++)\r\n  {\r\n    if( ((value >> 28)) < 0xA )\r\n    {\r\n      pbuf[ 2* idx] = (value >> 28) + '0';\r\n    }\r\n    else\r\n    {\r\n      pbuf[2* idx] = (value >> 28) + 'A' - 10; \r\n    }\r\n    \r\n    value = value << 4;\r\n    \r\n    pbuf[ 2* idx + 1] = 0;\r\n  }\r\n}\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/usbd_desc.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    USB_Device/CDC_Standalone/Inc/usbd_desc.h\r\n  * @author  MCD Application Team\r\n  * @version V1.0.3\r\n  * @date    18-November-2015\r\n  * @brief   Header for usbd_desc.c module\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __USBD_DESC_H\r\n#define __USBD_DESC_H\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_def.h\"\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n#define         DEVICE_ID1          (0x1FFF7A10)\r\n#define         DEVICE_ID2          (0x1FFF7A14)\r\n#define         DEVICE_ID3          (0x1FFF7A18)\r\n\r\n#define  USB_SIZ_STRING_SERIAL       0x1A\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions ------------------------------------------------------- */\r\nextern USBD_DescriptorsTypeDef VCP_Desc;\r\n\r\n#endif /* __USBD_DESC_H */\r\n \r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/wdg.c",
    "content": "/*\r\n *  led.c\r\n *\r\n *  Created on: 2016. 7. 7.\r\n *      Author: Baram, PBHP\r\n */\r\n\r\n#include \"wdg.h\"\r\n\r\n\r\n\r\nstatic IWDG_HandleTypeDef IwdgHandle;\r\n\r\n\r\n\r\nvoid wdg_init()\r\n{\r\n}\r\n\r\nBOOL wdg_setup(uint32_t reload_time)\r\n{\r\n\r\n  IwdgHandle.Instance \t    = IWDG;\r\n  IwdgHandle.Init.Prescaler = IWDG_PRESCALER_32; // 32Khz/32 = 1Khz(1ms)\r\n  IwdgHandle.Init.Reload    = reload_time;\r\n  IwdgHandle.Init.Window    = IWDG_WINDOW_DISABLE;\r\n\r\n  if (HAL_IWDG_Init(&IwdgHandle) != HAL_OK)\r\n  {\r\n    return FALSE;\r\n  }\r\n}\r\n\r\nBOOL wdg_start(void)\r\n{\r\n  return TRUE;\r\n}\r\n\r\nBOOL wdg_get_reset(void)\r\n{\r\n\r\n  if (__HAL_RCC_GET_FLAG(RCC_FLAG_IWDGRST) != RESET)\r\n  {\r\n    // IWDGRST flag set\r\n    // Clear reset flags\r\n    __HAL_RCC_CLEAR_RESET_FLAGS();\r\n\r\n    return TRUE;\r\n  }\r\n  else\r\n  {\r\n    // IWDGRST flag is not set\r\n    return FALSE;\r\n  }\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/bsp/opencr/wdg.h",
    "content": "/*\r\n *  led.h\r\n *\r\n *  Created on: 2016. 7. 8.\r\n *      Author: Baram, PBHP\r\n */\r\n\r\n#ifndef WDG_H\r\n#define WDG_H\r\n\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n\r\n#include \"def.h\"\r\n#include \"bsp.h\"\r\n\r\n\r\nvoid wdg_init(void);\r\nBOOL wdg_setup(uint32_t reload_time);\r\nBOOL wdg_start(void);\r\nBOOL wdg_get_reset(void);\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/hal/def.h",
    "content": "/*\r\n *  def.h\r\n *\r\n *  Created on: 2016. 5. 14.\r\n *      Author: Baram, PBHP\r\n */\r\n\r\n#ifndef DEF_H\r\n#define DEF_H\r\n\r\n#include <stdint.h>\r\n\r\n\r\n#ifndef BOOL\r\n#define BOOL uint8_t\r\n#endif\r\n\r\n#ifndef TRUE\r\n#define TRUE  1\r\n#endif\r\n\r\n#ifndef FALSE\r\n#define FALSE 0\r\n#endif\r\n\r\n#ifndef bool\r\n#define bool uint8_t\r\n#endif\r\n\r\n#ifndef true\r\n#define true  1\r\n#endif\r\n\r\n#ifndef false\r\n#define false 0\r\n#endif\r\n\r\n\r\n\r\n#include \"def_err.h\"\r\n#include \"util.h\"\r\n#include \"../msg/mavlink/opencr_msg/mavlink.h\"\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/hal/def_err.h",
    "content": "/*\r\n *  def_err.h\r\n *\r\n *  Created on: 2016. 5. 14.\r\n *      Author: Baram, PBHP\r\n */\r\n\r\n#ifndef DEF_ERR_H\r\n#define DEF_ERR_H\r\n\r\n#include <stdint.h>\r\n\r\n\r\n\r\ntypedef uint16_t err_code_t;\r\n\r\n\r\n\r\n\r\n#define OK                                  0x0000\r\n#define ERR_INVALID_CMD                     0x0001\r\n#define ERR_FLASH_ERROR                     0x0010\r\n#define ERR_FLASH_BUSY                      0x0011\r\n#define ERR_FLASH_ERR_TIMEOUT               0x0012\r\n#define ERR_FLASH_NOT_EMPTY                 0x0013\r\n#define ERR_FLASH_WRITE                     0x0014\r\n#define ERR_FLASH_READ                      0x0015\r\n#define ERR_FLASH_ERASE                     0x0016\r\n#define ERR_FLASH_PACKET_SIZE               0x0017\r\n#define ERR_FLASH_SIZE         \t\t    0x0018\r\n#define ERR_FLASH_CRC         \t\t    0x0019\r\n\r\n\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/hal/delay.c",
    "content": "/*\r\n *  delay.h\r\n *\r\n *  Created on: 2016. 5. 14.\r\n *      Author: Baram, PBHP\r\n */\r\n\r\n#include \"delay.h\"\r\n\r\n\r\n\r\n\r\nvoid delay_ns(uint32_t ns)\r\n{\r\n  // TODO: actually tune this better on an oscilloscope\r\n  for (volatile uint32_t i = 0; i < ns/10; i++) { }\r\n}\r\n\r\nvoid delay_us(uint32_t us)\r\n{\r\n#if 0\r\n  // todo: care about wraparound\r\n  volatile uint32_t t_start = systime_usecs();\r\n  while (1)\r\n  {\r\n    volatile uint32_t t[2];\r\n    // poll time twice in case we happen to poll during timer wrap glitch\r\n    t[0] = systime_usecs();\r\n    t[1] = systime_usecs();\r\n    t[0] = t[1] < t[0] ? t[1] : t[0];\r\n    if (t[0] > t_start + us)\r\n      break;\r\n  }\r\n#endif\r\n}\r\n\r\nvoid delay_ms(uint32_t ms)\r\n{\r\n  volatile uint32_t t_start = millis();\r\n\r\n\r\n  while (1)\r\n  {\r\n    volatile uint32_t t[2];\r\n    // poll time twice in case we happen to poll during timer wrap glitch\r\n    t[0] = millis();\r\n    t[1] = millis();\r\n    t[0] = t[1] < t[0] ? t[1] : t[0];\r\n    if (t[0] > t_start + ms)\r\n      break;\r\n  }\r\n}\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/hal/delay.h",
    "content": "/*\r\n *  delay.h\r\n *\r\n *  Created on: 2016. 5. 14.\r\n *      Author: Baram, PBHP\r\n */\r\n\r\n#ifndef DELAY_H\r\n#define DELAY_H\r\n\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n\r\n#include \"def.h\"\r\n#include \"bsp.h\"\r\n\r\n\r\nvoid delay_ns(uint32_t ns);\r\nvoid delay_us(uint32_t us);\r\nvoid delay_ms(uint32_t ms);\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/hal/flash.c",
    "content": "/*\r\n *  flash.h\r\n *\r\n *  Created on: 2016. 5. 14.\r\n *      Author: Baram, PBHP\r\n */\r\n\r\n#include \"flash.h\"\r\n\r\n\r\n\r\n//static void               FLASH_MassErase(uint8_t VoltageRange);\r\n\r\nvoid flash_init()\r\n{\r\n\r\n}\r\n\r\n\r\nerr_code_t flash_write(uint32_t addr, uint8_t *p_data, uint32_t length)\r\n{\r\n  err_code_t err_code = OK;\r\n  HAL_StatusTypeDef HAL_FLASHStatus = HAL_OK;\r\n  uint32_t StartAddress = addr;\r\n  uint32_t WriteSize;\r\n  uint32_t WriteData;\r\n  uint32_t i;\r\n  uint32_t DataIndex;\r\n\r\n\r\n  WriteSize = length / 4; // 32Bit\r\n\r\n  if( (WriteSize%4) > 0 ) WriteSize++;\r\n\r\n  DataIndex = 0;\r\n  HAL_FLASH_Unlock();\r\n  for( i=0; i<WriteSize; i++ )\r\n  {\r\n    WriteData  = p_data[ DataIndex++ ] << 0;\r\n    WriteData |= p_data[ DataIndex++ ] << 8;\r\n    WriteData |= p_data[ DataIndex++ ] << 16;\r\n    WriteData |= p_data[ DataIndex++ ] << 24;\r\n\r\n    HAL_FLASHStatus = HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, StartAddress+i*4, (uint64_t)WriteData);\r\n\r\n    if( HAL_FLASHStatus != HAL_OK )\r\n    {\r\n        err_code = ERR_FLASH_WRITE;\r\n      break;\r\n    }\r\n  }\r\n  HAL_FLASH_Lock();\r\n\r\n  return err_code;\r\n}\r\n\r\n\r\nerr_code_t flash_read(uint32_t addr, uint8_t *p_data, uint32_t length)\r\n{\r\n  err_code_t err_code = OK;\r\n  uint32_t Dataindex;\r\n  uint32_t addr_cnt;\r\n\r\n\r\n  Dataindex = 0;\r\n  for (addr_cnt=0;addr_cnt<length;addr_cnt++)\r\n  {\r\n    p_data[Dataindex++] = *(volatile uint8_t*)(addr+addr_cnt);\r\n  }\r\n\r\n  return err_code;\r\n}\r\n\r\n\r\nerr_code_t flash_erase_whole_sectors(void)\r\n{\r\n\r\n  err_code_t err_code = OK;\r\n  HAL_StatusTypeDef HAL_FLASHStatus = HAL_OK;\r\n\r\n  HAL_FLASH_Unlock();\r\n\r\n  //HAL_FLASHStatus = FLASH_MassErase(FLASH_VOLTAGE_RANGE_3);\r\n  if(HAL_FLASHStatus != HAL_OK)\r\n  {\r\n    err_code = ERR_FLASH_ERASE;\r\n  }\r\n\r\n  HAL_FLASH_Lock();\r\n\r\n  return err_code;\r\n}\r\n\r\nerr_code_t flash_erase_fw_block( uint32_t length )\r\n{\r\n\r\n  err_code_t err_code = OK;\r\n  HAL_StatusTypeDef HAL_FLASHStatus = HAL_OK;\r\n  FLASH_EraseInitTypeDef pEraseInit;\r\n  uint32_t SectorError;\r\n  uint32_t sector_cnt;\r\n\r\n\r\n  sector_cnt = length/(256*1024);\r\n  if( length%(256*1024) > 0 )\r\n  {\r\n    sector_cnt++;\r\n  }\r\n  if( sector_cnt > (FLASH_SECTOR_TOTAL-FLASH_SECTOR_5) )\r\n  {\r\n    sector_cnt = (FLASH_SECTOR_TOTAL-FLASH_SECTOR_5);\r\n  }\r\n\r\n  //except user bootloader sectors\r\n  pEraseInit.TypeErase = FLASH_TYPEERASE_SECTORS;\r\n  pEraseInit.VoltageRange = FLASH_VOLTAGE_RANGE_3;\r\n  pEraseInit.Sector = FLASH_SECTOR_5;\r\n  pEraseInit.NbSectors = sector_cnt;\r\n\r\n  HAL_FLASH_Unlock();\r\n\r\n  HAL_FLASHStatus = HAL_FLASHEx_Erase(&pEraseInit, &SectorError);\r\n  if(HAL_FLASHStatus != HAL_OK)\r\n  {\r\n    err_code = ERR_FLASH_ERASE;\r\n  }\r\n\r\n  HAL_FLASH_Lock();\r\n\r\n  return err_code;\r\n}\r\n\r\n\r\nerr_code_t flash_erase_sector(uint32_t sector)\r\n{\r\n  err_code_t err_code = OK;\r\n  HAL_StatusTypeDef HAL_FLASHStatus = HAL_OK;\r\n  FLASH_EraseInitTypeDef pEraseInit;\r\n  uint32_t SectorError;\r\n\r\n  pEraseInit.TypeErase = FLASH_TYPEERASE_SECTORS;\r\n  pEraseInit.VoltageRange = FLASH_VOLTAGE_RANGE_3;\r\n  pEraseInit.Sector = sector;\r\n  pEraseInit.NbSectors = 1;\r\n\r\n  HAL_FLASH_Unlock();\r\n\r\n  HAL_FLASHStatus = HAL_FLASHEx_Erase(&pEraseInit, &SectorError);\r\n  if(HAL_FLASHStatus != HAL_OK)\r\n  {\r\n    err_code = ERR_FLASH_ERASE;\r\n  }\r\n\r\n  HAL_FLASH_Lock();\r\n\r\n  return err_code;\r\n}\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/hal/flash.h",
    "content": "/*\r\n *  flash.h\r\n *\r\n *  Created on: 2016. 5. 14.\r\n *      Author: Baram, PBHP\r\n */\r\n\r\n#ifndef FLASH_H\r\n#define FLASH_H\r\n\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n\r\n#include \"def.h\"\r\n#include \"bsp.h\"\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\nvoid flash_init(void);\r\n\r\nerr_code_t flash_write(uint32_t addr, uint8_t *p_data, uint32_t length);\r\nerr_code_t flash_read(uint32_t addr, uint8_t *p_data, uint32_t length);\r\nerr_code_t flash_erase_whole_sectors(void);\r\nerr_code_t flash_erase_sector(uint32_t sector);\r\nerr_code_t flash_erase_fw_block(uint32_t length);\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/hal/hal.c",
    "content": "/*\r\n *  hal.c\r\n *\r\n *  Created on: 2016. 5. 14.\r\n *      Author: Baram, PBHP\r\n */\r\n\r\n#include \"hal.h\"\r\n\r\n\r\n\r\n\r\n\r\nvoid hal_init()\r\n{\r\n\r\n}\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/hal/hal.h",
    "content": "/*\r\n *  hal.h\r\n *\r\n *  Created on: 2016. 5. 14.\r\n *      Author: Baram, PBHP\r\n */\r\n\r\n#ifndef HAL_H\r\n#define HAL_H\r\n\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n\r\n#include \"def.h\"\r\n#include \"bsp.h\"\r\n\r\n\r\n#include \"util.h\"\r\n#include \"delay.h\"\r\n#include \"flash.h\"\r\n#include \"vcp.h\"\r\n#include \"msg.h\"\r\n\r\n\r\n\r\nvoid hal_init();\r\n\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/hal/msg.c",
    "content": "/*\r\n *  msg.c\r\n *\r\n *  message process\r\n *\r\n *  Created on: 2016. 5. 14.\r\n *      Author: Baram, PBHP\r\n */\r\n\r\n#include \"msg.h\"\r\n#include \"vcp.h\"\r\n#include <math.h>\r\n#include <string.h>\r\n#include <stdarg.h>\r\n#include <stdio.h>\r\n\r\n\r\n\r\nvoid msg_init(void)\r\n{\r\n\r\n}\r\n\r\n\r\nvoid msg_send(uint8_t ch, mavlink_message_t *p_msg)\r\n{\r\n  uint8_t  buf[1024];\r\n  uint32_t len;\r\n  int i;\r\n\r\n\r\n  len = mavlink_msg_to_send_buffer(buf, p_msg);\r\n\r\n  switch(ch)\r\n  {\r\n    case 0:\r\n      vcp_write(buf, len);\r\n      break;\r\n\r\n    case 1:\r\n      break;\r\n  }\r\n}\r\n\r\n\r\nBOOL msg_recv( uint8_t ch, uint8_t data , msg_t *p_msg )\r\n{\r\n  BOOL ret = FALSE;\r\n  static mavlink_message_t msg[MSG_CH_MAX];\r\n  mavlink_status_t status[MSG_CH_MAX];\r\n\r\n\r\n  p_msg->ch = ch;\r\n\r\n  if(ch == 0)\r\n  {\r\n    if (mavlink_parse_char(MAVLINK_COMM_0, data, &msg[ch], &status[ch]) == MAVLINK_FRAMING_OK)\r\n    {\r\n      p_msg->p_msg = &msg[ch];\r\n      ret = TRUE;\r\n    }\r\n  }\r\n  else\r\n  {\r\n    if (mavlink_parse_char(MAVLINK_COMM_1, data, &msg[ch], &status[ch]) == MAVLINK_FRAMING_OK)\r\n    {\r\n      p_msg->p_msg = &msg[ch];\r\n      ret = TRUE;\r\n    }\r\n  }\r\n  return ret;\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/hal/msg.h",
    "content": "/*\r\n *  msg.h\r\n *\r\n *  message process\r\n *\r\n *  Created on: 2016. 5. 14.\r\n *      Author: Baram, PBHP\r\n */\r\n\r\n#ifndef MSG_H\r\n#define MSG_H\r\n\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n\r\n#include \"def.h\"\r\n#include \"bsp.h\"\r\n\r\n\r\n#define MSG_CH_MAX\t1\r\n\r\n\r\ntypedef struct\r\n{\r\n  uint8_t ch;\r\n  mavlink_message_t *p_msg;\r\n} msg_t;\r\n\r\n\r\n\r\nvoid msg_init(void);\r\nvoid msg_send(uint8_t ch, mavlink_message_t *p_msg);\r\nBOOL msg_recv( uint8_t ch, uint8_t data , msg_t *p_msg );\r\n\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/hal/util.c",
    "content": "/*\r\n *  util.c\r\n *\r\n *  Created on: 2016. 5. 14.\r\n *      Author: Baram, PBHP\r\n */\r\n\r\n#include \"util.h\"\r\n\r\n\r\n\r\n\r\n\r\nuint32_t millis()\r\n{\r\n  return HAL_GetTick();\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/hal/util.h",
    "content": "/*\r\n *  util.h\r\n *\r\n *  Created on: 2016. 5. 14.\r\n *      Author: Baram, PBHP\r\n */\r\n\r\n#ifndef UTIL_H\r\n#define UTIL_H\r\n\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n\r\n#include \"def.h\"\r\n#include \"bsp.h\"\r\n\r\n\r\n\r\n\r\n\r\nuint32_t millis();\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/hal/vcp.c",
    "content": "/*\r\n *  vcp.c\r\n *\r\n *  virtual_com_port\r\n *\r\n *  Created on: 2016. 5. 14.\r\n *      Author: Baram, PBHP\r\n */\r\n\r\n#include \"vcp.h\"\r\n#include <math.h>\r\n#include <string.h>\r\n#include <stdarg.h>\r\n#include <stdio.h>\r\n#include \"usbd_cdc_interface.h\"\r\n\r\n\r\n\r\nvoid vcp_init(void)\r\n{\r\n\r\n}\r\n\r\n\r\nBOOL vcp_is_available(void)\r\n{\r\n  BOOL ret = FALSE;\r\n\r\n  // TODO : 시리얼 버퍼에 데이터가 있으면 TRUE 리턴한다.\r\n\r\n  ret = CDC_Itf_IsAvailable();\r\n\r\n  return ret;\r\n}\r\n\r\n\r\nvoid vcp_putch(uint8_t ch)\r\n{\r\n  // TODO : 시리얼포트로 1바이트 데이터 전송\r\n  CDC_Itf_Write( &ch, 1 );\r\n}\r\n\r\n\r\nuint8_t vcp_getch(void)\r\n{\r\n  // TODO : 시리얼포트로 부터 1바이트 데이터 수신 (Block 방식)\r\n  return CDC_Itf_Getch();\r\n}\r\n\r\n\r\nint32_t vcp_write(uint8_t *p_data, uint32_t length)\r\n{\r\n  // TODO : 시리얼 포트로 length 길이만큼의 문자열을 전송함\r\n\r\n  CDC_Itf_Write( p_data, length );\r\n  return length;\r\n}\r\n\r\n\r\nint32_t vcp_printf( const char *fmt, ...)\r\n{\r\n  int32_t ret = 0;\r\n  va_list arg;\r\n  va_start (arg, fmt);\r\n  int32_t len;\r\n  static char print_buffer[255];\r\n\r\n  len = vsnprintf(print_buffer, 255, fmt, arg);\r\n  va_end (arg);\r\n\r\n\r\n  ret = vcp_write( print_buffer, len);\r\n\r\n  return ret;\r\n}\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/hal/vcp.h",
    "content": "/*\r\n *  vcp.h\r\n *\r\n *  virtual_com_port\r\n *\r\n *  Created on: 2016. 5. 14.\r\n *      Author: Baram, PBHP\r\n */\r\n\r\n#ifndef VCP_H\r\n#define VCP_H\r\n\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n\r\n#include \"def.h\"\r\n#include \"bsp.h\"\r\n\r\n\r\nvoid    vcp_init(void);\r\nBOOL    vcp_is_available(void);\r\nvoid    vcp_putch(uint8_t ch);\r\nuint8_t vcp_getch(void);\r\nint32_t vcp_write(uint8_t *p_data, uint32_t length);\r\n\r\nint32_t vcp_printf( const char *fmt, ...);\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32_hal_legacy.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   This file contains aliases definition for the STM32Cube HAL constants \r\n  *          macros and functions maintained for legacy purpose.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32_HAL_LEGACY\r\n#define __STM32_HAL_LEGACY\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define AES_FLAG_RDERR                  CRYP_FLAG_RDERR\r\n#define AES_FLAG_WRERR                  CRYP_FLAG_WRERR\r\n#define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF\r\n#define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR\r\n#define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define ADC_RESOLUTION12b               ADC_RESOLUTION_12B\r\n#define ADC_RESOLUTION10b               ADC_RESOLUTION_10B\r\n#define ADC_RESOLUTION8b                ADC_RESOLUTION_8B\r\n#define ADC_RESOLUTION6b                ADC_RESOLUTION_6B\r\n#define OVR_DATA_OVERWRITTEN            ADC_OVR_DATA_OVERWRITTEN\r\n#define OVR_DATA_PRESERVED              ADC_OVR_DATA_PRESERVED\r\n#define EOC_SINGLE_CONV                 ADC_EOC_SINGLE_CONV\r\n#define EOC_SEQ_CONV                    ADC_EOC_SEQ_CONV\r\n#define EOC_SINGLE_SEQ_CONV             ADC_EOC_SINGLE_SEQ_CONV\r\n#define REGULAR_GROUP                   ADC_REGULAR_GROUP\r\n#define INJECTED_GROUP                  ADC_INJECTED_GROUP\r\n#define REGULAR_INJECTED_GROUP          ADC_REGULAR_INJECTED_GROUP\r\n#define AWD_EVENT                       ADC_AWD_EVENT\r\n#define AWD1_EVENT                      ADC_AWD1_EVENT\r\n#define AWD2_EVENT                      ADC_AWD2_EVENT\r\n#define AWD3_EVENT                      ADC_AWD3_EVENT\r\n#define OVR_EVENT                       ADC_OVR_EVENT\r\n#define JQOVF_EVENT                     ADC_JQOVF_EVENT\r\n#define ALL_CHANNELS                    ADC_ALL_CHANNELS\r\n#define REGULAR_CHANNELS                ADC_REGULAR_CHANNELS\r\n#define INJECTED_CHANNELS               ADC_INJECTED_CHANNELS\r\n#define SYSCFG_FLAG_SENSOR_ADC          ADC_FLAG_SENSOR\r\n#define SYSCFG_FLAG_VREF_ADC            ADC_FLAG_VREFINT\r\n#define ADC_CLOCKPRESCALER_PCLK_DIV1    ADC_CLOCK_SYNC_PCLK_DIV1\r\n#define ADC_CLOCKPRESCALER_PCLK_DIV2    ADC_CLOCK_SYNC_PCLK_DIV2\r\n#define ADC_CLOCKPRESCALER_PCLK_DIV4    ADC_CLOCK_SYNC_PCLK_DIV4\r\n#define ADC_CLOCKPRESCALER_PCLK_DIV6    ADC_CLOCK_SYNC_PCLK_DIV6\r\n#define ADC_CLOCKPRESCALER_PCLK_DIV8    ADC_CLOCK_SYNC_PCLK_DIV8\r\n#define ADC_EXTERNALTRIG0_T6_TRGO       ADC_EXTERNALTRIGCONV_T6_TRGO \r\n#define ADC_EXTERNALTRIG1_T21_CC2       ADC_EXTERNALTRIGCONV_T21_CC2 \r\n#define ADC_EXTERNALTRIG2_T2_TRGO       ADC_EXTERNALTRIGCONV_T2_TRGO \r\n#define ADC_EXTERNALTRIG3_T2_CC4        ADC_EXTERNALTRIGCONV_T2_CC4  \r\n#define ADC_EXTERNALTRIG4_T22_TRGO      ADC_EXTERNALTRIGCONV_T22_TRGO\r\n#define ADC_EXTERNALTRIG7_EXT_IT11      ADC_EXTERNALTRIGCONV_EXT_IT11\r\n#define ADC_CLOCK_ASYNC                 ADC_CLOCK_ASYNC_DIV1\r\n#define ADC_EXTERNALTRIG_EDGE_NONE      ADC_EXTERNALTRIGCONVEDGE_NONE\r\n#define ADC_EXTERNALTRIG_EDGE_RISING    ADC_EXTERNALTRIGCONVEDGE_RISING\r\n#define ADC_EXTERNALTRIG_EDGE_FALLING   ADC_EXTERNALTRIGCONVEDGE_FALLING\r\n#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING\r\n#define ADC_SAMPLETIME_2CYCLE_5         ADC_SAMPLETIME_2CYCLES_5\r\n\r\n#define HAL_ADC_STATE_BUSY_REG          HAL_ADC_STATE_REG_BUSY\r\n#define HAL_ADC_STATE_BUSY_INJ          HAL_ADC_STATE_INJ_BUSY\r\n#define HAL_ADC_STATE_EOC_REG           HAL_ADC_STATE_REG_EOC\r\n#define HAL_ADC_STATE_EOC_INJ           HAL_ADC_STATE_INJ_EOC\r\n#define HAL_ADC_STATE_ERROR             HAL_ADC_STATE_ERROR_INTERNAL\r\n#define HAL_ADC_STATE_BUSY              HAL_ADC_STATE_BUSY_INTERNAL\r\n#define HAL_ADC_STATE_AWD               HAL_ADC_STATE_AWD1 \r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */ \r\n  \r\n#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG \r\n\r\n/**\r\n  * @}\r\n  */   \r\n   \r\n/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define COMP_WINDOWMODE_DISABLED       COMP_WINDOWMODE_DISABLE\r\n#define COMP_WINDOWMODE_ENABLED        COMP_WINDOWMODE_ENABLE\r\n#define COMP_EXTI_LINE_COMP1_EVENT     COMP_EXTI_LINE_COMP1\r\n#define COMP_EXTI_LINE_COMP2_EVENT     COMP_EXTI_LINE_COMP2\r\n#define COMP_EXTI_LINE_COMP3_EVENT     COMP_EXTI_LINE_COMP3\r\n#define COMP_EXTI_LINE_COMP4_EVENT     COMP_EXTI_LINE_COMP4\r\n#define COMP_EXTI_LINE_COMP5_EVENT     COMP_EXTI_LINE_COMP5\r\n#define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6\r\n#define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7\r\n#define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR\r\n#if defined(STM32F373xC) || defined(STM32F378xx)\r\n#define COMP_OUTPUT_TIM3IC1            COMP_OUTPUT_COMP1_TIM3IC1\r\n#define COMP_OUTPUT_TIM3OCREFCLR       COMP_OUTPUT_COMP1_TIM3OCREFCLR\r\n#endif /* STM32F373xC || STM32F378xx */\r\n\r\n#if defined(STM32L0) || defined(STM32L4)\r\n#define COMP_WINDOWMODE_ENABLE         COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON\r\n\r\n#define COMP_NONINVERTINGINPUT_IO1      COMP_INPUT_PLUS_IO1\r\n#define COMP_NONINVERTINGINPUT_IO2      COMP_INPUT_PLUS_IO2\r\n#define COMP_NONINVERTINGINPUT_IO3      COMP_INPUT_PLUS_IO3\r\n \r\n#define COMP_INVERTINGINPUT_1_4VREFINT  COMP_INPUT_MINUS_1_4VREFINT\r\n#define COMP_INVERTINGINPUT_1_2VREFINT  COMP_INPUT_MINUS_1_2VREFINT\r\n#define COMP_INVERTINGINPUT_3_4VREFINT  COMP_INPUT_MINUS_3_4VREFINT\r\n#define COMP_INVERTINGINPUT_VREFINT     COMP_INPUT_MINUS_VREFINT\r\n#define COMP_INVERTINGINPUT_DAC1_CH1    COMP_INPUT_MINUS_DAC1_CH1\r\n#define COMP_INVERTINGINPUT_DAC1_CH2    COMP_INPUT_MINUS_DAC1_CH2\r\n#define COMP_INVERTINGINPUT_DAC1        COMP_INPUT_MINUS_DAC1_CH1\r\n#define COMP_INVERTINGINPUT_DAC2        COMP_INPUT_MINUS_DAC1_CH2\r\n#define COMP_INVERTINGINPUT_IO1         COMP_INPUT_MINUS_IO1\r\n#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_IO2\r\n#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO3\r\n#define COMP_INVERTINGINPUT_IO4         COMP_INPUT_MINUS_IO4\r\n#define COMP_INVERTINGINPUT_IO5         COMP_INPUT_MINUS_IO5\r\n\r\n#define COMP_OUTPUTLEVEL_LOW            COMP_OUTPUT_LEVEL_LOW\r\n#define COMP_OUTPUTLEVEL_HIGH           COMP_OUTPUT_LEVEL_HIGH\r\n\r\n/* Note: Literal \"COMP_FLAG_LOCK\" kept for legacy purpose.                    */\r\n/*       To check COMP lock state, use macro \"__HAL_COMP_IS_LOCKED()\".        */\r\n#if defined(COMP_CSR_LOCK)\r\n#define COMP_FLAG_LOCK                 COMP_CSR_LOCK\r\n#elif defined(COMP_CSR_COMP1LOCK)\r\n#define COMP_FLAG_LOCK                 COMP_CSR_COMP1LOCK\r\n#elif defined(COMP_CSR_COMPxLOCK)\r\n#define COMP_FLAG_LOCK                 COMP_CSR_COMPxLOCK\r\n#endif\r\n\r\n#if defined(STM32L4)\r\n#define COMP_BLANKINGSRCE_TIM1OC5        COMP_BLANKINGSRC_TIM1_OC5_COMP1\r\n#define COMP_BLANKINGSRCE_TIM2OC3        COMP_BLANKINGSRC_TIM2_OC3_COMP1\r\n#define COMP_BLANKINGSRCE_TIM3OC3        COMP_BLANKINGSRC_TIM3_OC3_COMP1\r\n#define COMP_BLANKINGSRCE_TIM3OC4        COMP_BLANKINGSRC_TIM3_OC4_COMP2\r\n#define COMP_BLANKINGSRCE_TIM8OC5        COMP_BLANKINGSRC_TIM8_OC5_COMP2\r\n#define COMP_BLANKINGSRCE_TIM15OC1       COMP_BLANKINGSRC_TIM15_OC1_COMP2\r\n#define COMP_BLANKINGSRCE_NONE           COMP_BLANKINGSRC_NONE\r\n#endif\r\n\r\n#if defined(STM32L0)\r\n#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_MEDIUMSPEED\r\n#define COMP_MODE_LOWSPEED               COMP_POWERMODE_ULTRALOWPOWER\r\n#else\r\n#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_HIGHSPEED\r\n#define COMP_MODE_MEDIUMSPEED            COMP_POWERMODE_MEDIUMSPEED\r\n#define COMP_MODE_LOWPOWER               COMP_POWERMODE_LOWPOWER\r\n#define COMP_MODE_ULTRALOWPOWER          COMP_POWERMODE_ULTRALOWPOWER\r\n#endif\r\n\r\n#endif\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n  \r\n#define CRC_OUTPUTDATA_INVERSION_DISABLED    CRC_OUTPUTDATA_INVERSION_DISABLE\r\n#define CRC_OUTPUTDATA_INVERSION_ENABLED     CRC_OUTPUTDATA_INVERSION_ENABLE\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define DAC1_CHANNEL_1                                  DAC_CHANNEL_1\r\n#define DAC1_CHANNEL_2                                  DAC_CHANNEL_2\r\n#define DAC2_CHANNEL_1                                  DAC_CHANNEL_1\r\n#define DAC_WAVE_NONE                                   ((uint32_t)0x00000000U)\r\n#define DAC_WAVE_NOISE                                  ((uint32_t)DAC_CR_WAVE1_0)\r\n#define DAC_WAVE_TRIANGLE                               ((uint32_t)DAC_CR_WAVE1_1)                           \r\n#define DAC_WAVEGENERATION_NONE                         DAC_WAVE_NONE\r\n#define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE\r\n#define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define HAL_REMAPDMA_ADC_DMA_CH2                DMA_REMAP_ADC_DMA_CH2       \r\n#define HAL_REMAPDMA_USART1_TX_DMA_CH4          DMA_REMAP_USART1_TX_DMA_CH4 \r\n#define HAL_REMAPDMA_USART1_RX_DMA_CH5          DMA_REMAP_USART1_RX_DMA_CH5   \r\n#define HAL_REMAPDMA_TIM16_DMA_CH4              DMA_REMAP_TIM16_DMA_CH4       \r\n#define HAL_REMAPDMA_TIM17_DMA_CH2              DMA_REMAP_TIM17_DMA_CH2       \r\n#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32\r\n#define HAL_REMAPDMA_TIM16_DMA_CH6              DMA_REMAP_TIM16_DMA_CH6\r\n#define HAL_REMAPDMA_TIM17_DMA_CH7              DMA_REMAP_TIM17_DMA_CH7      \r\n#define HAL_REMAPDMA_SPI2_DMA_CH67              DMA_REMAP_SPI2_DMA_CH67  \r\n#define HAL_REMAPDMA_USART2_DMA_CH67            DMA_REMAP_USART2_DMA_CH67 \r\n#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32  \r\n#define HAL_REMAPDMA_I2C1_DMA_CH76              DMA_REMAP_I2C1_DMA_CH76   \r\n#define HAL_REMAPDMA_TIM1_DMA_CH6               DMA_REMAP_TIM1_DMA_CH6     \r\n#define HAL_REMAPDMA_TIM2_DMA_CH7               DMA_REMAP_TIM2_DMA_CH7      \r\n#define HAL_REMAPDMA_TIM3_DMA_CH6               DMA_REMAP_TIM3_DMA_CH6    \r\n  \r\n#define IS_HAL_REMAPDMA                          IS_DMA_REMAP  \r\n#define __HAL_REMAPDMA_CHANNEL_ENABLE            __HAL_DMA_REMAP_CHANNEL_ENABLE\r\n#define __HAL_REMAPDMA_CHANNEL_DISABLE           __HAL_DMA_REMAP_CHANNEL_DISABLE\r\n  \r\n  \r\n  \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n  \r\n#define TYPEPROGRAM_BYTE              FLASH_TYPEPROGRAM_BYTE\r\n#define TYPEPROGRAM_HALFWORD          FLASH_TYPEPROGRAM_HALFWORD\r\n#define TYPEPROGRAM_WORD              FLASH_TYPEPROGRAM_WORD\r\n#define TYPEPROGRAM_DOUBLEWORD        FLASH_TYPEPROGRAM_DOUBLEWORD\r\n#define TYPEERASE_SECTORS             FLASH_TYPEERASE_SECTORS\r\n#define TYPEERASE_PAGES               FLASH_TYPEERASE_PAGES\r\n#define TYPEERASE_PAGEERASE           FLASH_TYPEERASE_PAGES\r\n#define TYPEERASE_MASSERASE           FLASH_TYPEERASE_MASSERASE\r\n#define WRPSTATE_DISABLE              OB_WRPSTATE_DISABLE\r\n#define WRPSTATE_ENABLE               OB_WRPSTATE_ENABLE\r\n#define HAL_FLASH_TIMEOUT_VALUE       FLASH_TIMEOUT_VALUE\r\n#define OBEX_PCROP                    OPTIONBYTE_PCROP\r\n#define OBEX_BOOTCONFIG               OPTIONBYTE_BOOTCONFIG\r\n#define PCROPSTATE_DISABLE            OB_PCROP_STATE_DISABLE\r\n#define PCROPSTATE_ENABLE             OB_PCROP_STATE_ENABLE\r\n#define TYPEERASEDATA_BYTE            FLASH_TYPEERASEDATA_BYTE\r\n#define TYPEERASEDATA_HALFWORD        FLASH_TYPEERASEDATA_HALFWORD\r\n#define TYPEERASEDATA_WORD            FLASH_TYPEERASEDATA_WORD\r\n#define TYPEPROGRAMDATA_BYTE          FLASH_TYPEPROGRAMDATA_BYTE\r\n#define TYPEPROGRAMDATA_HALFWORD      FLASH_TYPEPROGRAMDATA_HALFWORD\r\n#define TYPEPROGRAMDATA_WORD          FLASH_TYPEPROGRAMDATA_WORD\r\n#define TYPEPROGRAMDATA_FASTBYTE      FLASH_TYPEPROGRAMDATA_FASTBYTE\r\n#define TYPEPROGRAMDATA_FASTHALFWORD  FLASH_TYPEPROGRAMDATA_FASTHALFWORD\r\n#define TYPEPROGRAMDATA_FASTWORD      FLASH_TYPEPROGRAMDATA_FASTWORD\r\n#define PAGESIZE                      FLASH_PAGE_SIZE\r\n#define TYPEPROGRAM_FASTBYTE          FLASH_TYPEPROGRAM_BYTE\r\n#define TYPEPROGRAM_FASTHALFWORD      FLASH_TYPEPROGRAM_HALFWORD\r\n#define TYPEPROGRAM_FASTWORD          FLASH_TYPEPROGRAM_WORD\r\n#define VOLTAGE_RANGE_1               FLASH_VOLTAGE_RANGE_1\r\n#define VOLTAGE_RANGE_2               FLASH_VOLTAGE_RANGE_2\r\n#define VOLTAGE_RANGE_3               FLASH_VOLTAGE_RANGE_3\r\n#define VOLTAGE_RANGE_4               FLASH_VOLTAGE_RANGE_4\r\n#define TYPEPROGRAM_FAST              FLASH_TYPEPROGRAM_FAST\r\n#define TYPEPROGRAM_FAST_AND_LAST     FLASH_TYPEPROGRAM_FAST_AND_LAST\r\n#define WRPAREA_BANK1_AREAA           OB_WRPAREA_BANK1_AREAA\r\n#define WRPAREA_BANK1_AREAB           OB_WRPAREA_BANK1_AREAB\r\n#define WRPAREA_BANK2_AREAA           OB_WRPAREA_BANK2_AREAA\r\n#define WRPAREA_BANK2_AREAB           OB_WRPAREA_BANK2_AREAB\r\n#define IWDG_STDBY_FREEZE             OB_IWDG_STDBY_FREEZE\r\n#define IWDG_STDBY_ACTIVE             OB_IWDG_STDBY_RUN\r\n#define IWDG_STOP_FREEZE              OB_IWDG_STOP_FREEZE\r\n#define IWDG_STOP_ACTIVE              OB_IWDG_STOP_RUN\r\n#define FLASH_ERROR_NONE              HAL_FLASH_ERROR_NONE\r\n#define FLASH_ERROR_RD                HAL_FLASH_ERROR_RD\r\n#define FLASH_ERROR_PG                HAL_FLASH_ERROR_PROG\r\n#define FLASH_ERROR_PGP               HAL_FLASH_ERROR_PGS\r\n#define FLASH_ERROR_WRP               HAL_FLASH_ERROR_WRP\r\n#define FLASH_ERROR_OPTV              HAL_FLASH_ERROR_OPTV\r\n#define FLASH_ERROR_OPTVUSR           HAL_FLASH_ERROR_OPTVUSR\r\n#define FLASH_ERROR_PROG              HAL_FLASH_ERROR_PROG\r\n#define FLASH_ERROR_OP                HAL_FLASH_ERROR_OPERATION\r\n#define FLASH_ERROR_PGA               HAL_FLASH_ERROR_PGA\r\n#define FLASH_ERROR_SIZE              HAL_FLASH_ERROR_SIZE\r\n#define FLASH_ERROR_SIZ               HAL_FLASH_ERROR_SIZE\r\n#define FLASH_ERROR_PGS               HAL_FLASH_ERROR_PGS\r\n#define FLASH_ERROR_MIS               HAL_FLASH_ERROR_MIS\r\n#define FLASH_ERROR_FAST              HAL_FLASH_ERROR_FAST\r\n#define FLASH_ERROR_FWWERR            HAL_FLASH_ERROR_FWWERR\r\n#define FLASH_ERROR_NOTZERO           HAL_FLASH_ERROR_NOTZERO\r\n#define FLASH_ERROR_OPERATION         HAL_FLASH_ERROR_OPERATION\r\n#define FLASH_ERROR_ERS               HAL_FLASH_ERROR_ERS\r\n#define OB_WDG_SW                     OB_IWDG_SW\r\n#define OB_WDG_HW                     OB_IWDG_HW\r\n#define OB_SDADC12_VDD_MONITOR_SET    OB_SDACD_VDD_MONITOR_SET\r\n#define OB_SDADC12_VDD_MONITOR_RESET  OB_SDACD_VDD_MONITOR_RESET\r\n#define OB_RAM_PARITY_CHECK_SET       OB_SRAM_PARITY_SET\r\n#define OB_RAM_PARITY_CHECK_RESET     OB_SRAM_PARITY_RESET\r\n#define IS_OB_SDADC12_VDD_MONITOR     IS_OB_SDACD_VDD_MONITOR\r\n#define OB_RDP_LEVEL0                 OB_RDP_LEVEL_0\r\n#define OB_RDP_LEVEL1                 OB_RDP_LEVEL_1\r\n#define OB_RDP_LEVEL2                 OB_RDP_LEVEL_2\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n  \r\n#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9    I2C_FASTMODEPLUS_PA9\r\n#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10   I2C_FASTMODEPLUS_PA10\r\n#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6    I2C_FASTMODEPLUS_PB6\r\n#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7    I2C_FASTMODEPLUS_PB7\r\n#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8    I2C_FASTMODEPLUS_PB8\r\n#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9    I2C_FASTMODEPLUS_PB9\r\n#define HAL_SYSCFG_FASTMODEPLUS_I2C1       I2C_FASTMODEPLUS_I2C1\r\n#define HAL_SYSCFG_FASTMODEPLUS_I2C2       I2C_FASTMODEPLUS_I2C2\r\n#define HAL_SYSCFG_FASTMODEPLUS_I2C3       I2C_FASTMODEPLUS_I2C3\r\n/**\r\n  * @}\r\n  */\r\n  \r\n\r\n/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose\r\n  * @{\r\n  */\r\n#if defined(STM32L4) || defined(STM32F7)\r\n#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE       FMC_NAND_WAIT_FEATURE_DISABLE\r\n#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE        FMC_NAND_WAIT_FEATURE_ENABLE\r\n#define FMC_NAND_PCC_MEM_BUS_WIDTH_8            FMC_NAND_MEM_BUS_WIDTH_8\r\n#define FMC_NAND_PCC_MEM_BUS_WIDTH_16           FMC_NAND_MEM_BUS_WIDTH_16\r\n#else\r\n#define FMC_NAND_WAIT_FEATURE_DISABLE           FMC_NAND_PCC_WAIT_FEATURE_DISABLE\r\n#define FMC_NAND_WAIT_FEATURE_ENABLE            FMC_NAND_PCC_WAIT_FEATURE_ENABLE\r\n#define FMC_NAND_MEM_BUS_WIDTH_8                FMC_NAND_PCC_MEM_BUS_WIDTH_8\r\n#define FMC_NAND_MEM_BUS_WIDTH_16               FMC_NAND_PCC_MEM_BUS_WIDTH_16\r\n#endif\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n  \r\n#define FSMC_NORSRAM_TYPEDEF                      FSMC_NORSRAM_TypeDef\r\n#define FSMC_NORSRAM_EXTENDED_TYPEDEF             FSMC_NORSRAM_EXTENDED_TypeDef\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define GET_GPIO_SOURCE                           GPIO_GET_INDEX\r\n#define GET_GPIO_INDEX                            GPIO_GET_INDEX\r\n\r\n#if defined(STM32F4)\r\n#define GPIO_AF12_SDMMC                           GPIO_AF12_SDIO\r\n#define GPIO_AF12_SDMMC1                          GPIO_AF12_SDIO\r\n#endif\r\n\r\n#if defined(STM32F7)\r\n#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1\r\n#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1\r\n#endif\r\n\r\n#if defined(STM32L4)\r\n#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1\r\n#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1\r\n#endif\r\n\r\n#define GPIO_AF0_LPTIM                            GPIO_AF0_LPTIM1\r\n#define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1\r\n#define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1\r\n\r\n#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)\r\n#define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW     \r\n#define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM     \r\n#define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH     \r\n#define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH       \r\n#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */\r\n\r\n#if defined(STM32L1) \r\n #define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW     \r\n #define  GPIO_SPEED_LOW         GPIO_SPEED_FREQ_MEDIUM     \r\n #define  GPIO_SPEED_MEDIUM      GPIO_SPEED_FREQ_HIGH     \r\n #define  GPIO_SPEED_HIGH        GPIO_SPEED_FREQ_VERY_HIGH     \r\n#endif /* STM32L1 */\r\n\r\n#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)\r\n #define  GPIO_SPEED_LOW    GPIO_SPEED_FREQ_LOW\r\n #define  GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM\r\n #define  GPIO_SPEED_HIGH   GPIO_SPEED_FREQ_HIGH\r\n#endif /* STM32F0 || STM32F3 || STM32F1 */\r\n\r\n#define GPIO_AF6_DFSDM                            GPIO_AF6_DFSDM1\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define HRTIM_TIMDELAYEDPROTECTION_DISABLED           HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED\r\n#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6\r\n#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6\r\n#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6\r\n#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6\r\n#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7\r\n#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7\r\n#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7\r\n#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7\r\n   \r\n#define __HAL_HRTIM_SetCounter        __HAL_HRTIM_SETCOUNTER\r\n#define __HAL_HRTIM_GetCounter        __HAL_HRTIM_GETCOUNTER\r\n#define __HAL_HRTIM_SetPeriod         __HAL_HRTIM_SETPERIOD\r\n#define __HAL_HRTIM_GetPeriod         __HAL_HRTIM_GETPERIOD\r\n#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER\r\n#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER\r\n#define __HAL_HRTIM_SetCompare        __HAL_HRTIM_SETCOMPARE\r\n#define __HAL_HRTIM_GetCompare        __HAL_HRTIM_GETCOMPARE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define I2C_DUALADDRESS_DISABLED                I2C_DUALADDRESS_DISABLE\r\n#define I2C_DUALADDRESS_ENABLED                 I2C_DUALADDRESS_ENABLE\r\n#define I2C_GENERALCALL_DISABLED                I2C_GENERALCALL_DISABLE\r\n#define I2C_GENERALCALL_ENABLED                 I2C_GENERALCALL_ENABLE\r\n#define I2C_NOSTRETCH_DISABLED                  I2C_NOSTRETCH_DISABLE\r\n#define I2C_NOSTRETCH_ENABLED                   I2C_NOSTRETCH_ENABLE\r\n#define I2C_ANALOGFILTER_ENABLED                I2C_ANALOGFILTER_ENABLE\r\n#define I2C_ANALOGFILTER_DISABLED               I2C_ANALOGFILTER_DISABLE\r\n#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)\r\n#define HAL_I2C_STATE_MEM_BUSY_TX               HAL_I2C_STATE_BUSY_TX\r\n#define HAL_I2C_STATE_MEM_BUSY_RX               HAL_I2C_STATE_BUSY_RX\r\n#define HAL_I2C_STATE_MASTER_BUSY_TX            HAL_I2C_STATE_BUSY_TX\r\n#define HAL_I2C_STATE_MASTER_BUSY_RX            HAL_I2C_STATE_BUSY_RX\r\n#define HAL_I2C_STATE_SLAVE_BUSY_TX             HAL_I2C_STATE_BUSY_TX\r\n#define HAL_I2C_STATE_SLAVE_BUSY_RX             HAL_I2C_STATE_BUSY_RX\r\n#endif\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define IRDA_ONE_BIT_SAMPLE_DISABLED            IRDA_ONE_BIT_SAMPLE_DISABLE\r\n#define IRDA_ONE_BIT_SAMPLE_ENABLED             IRDA_ONE_BIT_SAMPLE_ENABLE\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define KR_KEY_RELOAD                   IWDG_KEY_RELOAD\r\n#define KR_KEY_ENABLE                   IWDG_KEY_ENABLE\r\n#define KR_KEY_EWA                      IWDG_KEY_WRITE_ACCESS_ENABLE\r\n#define KR_KEY_DWA                      IWDG_KEY_WRITE_ACCESS_DISABLE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION\r\n#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_2TRANSITIONS\r\n#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_4TRANSITIONS\r\n#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_8TRANSITIONS\r\n\r\n#define LPTIM_CLOCKPOLARITY_RISINGEDGE          LPTIM_CLOCKPOLARITY_RISING\r\n#define LPTIM_CLOCKPOLARITY_FALLINGEDGE         LPTIM_CLOCKPOLARITY_FALLING\r\n#define LPTIM_CLOCKPOLARITY_BOTHEDGES           LPTIM_CLOCKPOLARITY_RISING_FALLING\r\n\r\n#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION  LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION\r\n#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS      LPTIM_TRIGSAMPLETIME_2TRANSITIONS\r\n#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS      LPTIM_TRIGSAMPLETIME_4TRANSITIONS\r\n#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS      LPTIM_TRIGSAMPLETIME_8TRANSITIONS        \r\n\r\n/* The following 3 definition have also been present in a temporary version of lptim.h */\r\n/* They need to be renamed also to the right name, just in case */\r\n#define LPTIM_TRIGSAMPLETIME_2TRANSITION        LPTIM_TRIGSAMPLETIME_2TRANSITIONS\r\n#define LPTIM_TRIGSAMPLETIME_4TRANSITION        LPTIM_TRIGSAMPLETIME_4TRANSITIONS\r\n#define LPTIM_TRIGSAMPLETIME_8TRANSITION        LPTIM_TRIGSAMPLETIME_8TRANSITIONS\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define HAL_NAND_Read_Page              HAL_NAND_Read_Page_8b\r\n#define HAL_NAND_Write_Page             HAL_NAND_Write_Page_8b\r\n#define HAL_NAND_Read_SpareArea         HAL_NAND_Read_SpareArea_8b\r\n#define HAL_NAND_Write_SpareArea        HAL_NAND_Write_SpareArea_8b\r\n\r\n#define NAND_AddressTypedef             NAND_AddressTypeDef\r\n\r\n#define __ARRAY_ADDRESS                 ARRAY_ADDRESS\r\n#define __ADDR_1st_CYCLE                ADDR_1ST_CYCLE\r\n#define __ADDR_2nd_CYCLE                ADDR_2ND_CYCLE\r\n#define __ADDR_3rd_CYCLE                ADDR_3RD_CYCLE\r\n#define __ADDR_4th_CYCLE                ADDR_4TH_CYCLE\r\n/**\r\n  * @}\r\n  */\r\n   \r\n/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define NOR_StatusTypedef              HAL_NOR_StatusTypeDef\r\n#define NOR_SUCCESS                    HAL_NOR_STATUS_SUCCESS\r\n#define NOR_ONGOING                    HAL_NOR_STATUS_ONGOING\r\n#define NOR_ERROR                      HAL_NOR_STATUS_ERROR\r\n#define NOR_TIMEOUT                    HAL_NOR_STATUS_TIMEOUT\r\n\r\n#define __NOR_WRITE                    NOR_WRITE\r\n#define __NOR_ADDR_SHIFT               NOR_ADDR_SHIFT\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define OPAMP_NONINVERTINGINPUT_VP0           OPAMP_NONINVERTINGINPUT_IO0\r\n#define OPAMP_NONINVERTINGINPUT_VP1           OPAMP_NONINVERTINGINPUT_IO1\r\n#define OPAMP_NONINVERTINGINPUT_VP2           OPAMP_NONINVERTINGINPUT_IO2\r\n#define OPAMP_NONINVERTINGINPUT_VP3           OPAMP_NONINVERTINGINPUT_IO3\r\n                                              \r\n#define OPAMP_SEC_NONINVERTINGINPUT_VP0       OPAMP_SEC_NONINVERTINGINPUT_IO0\r\n#define OPAMP_SEC_NONINVERTINGINPUT_VP1       OPAMP_SEC_NONINVERTINGINPUT_IO1\r\n#define OPAMP_SEC_NONINVERTINGINPUT_VP2       OPAMP_SEC_NONINVERTINGINPUT_IO2\r\n#define OPAMP_SEC_NONINVERTINGINPUT_VP3       OPAMP_SEC_NONINVERTINGINPUT_IO3   \r\n\r\n#define OPAMP_INVERTINGINPUT_VM0              OPAMP_INVERTINGINPUT_IO0\r\n#define OPAMP_INVERTINGINPUT_VM1              OPAMP_INVERTINGINPUT_IO1\r\n\r\n#define IOPAMP_INVERTINGINPUT_VM0             OPAMP_INVERTINGINPUT_IO0\r\n#define IOPAMP_INVERTINGINPUT_VM1             OPAMP_INVERTINGINPUT_IO1\r\n\r\n#define OPAMP_SEC_INVERTINGINPUT_VM0          OPAMP_SEC_INVERTINGINPUT_IO0\r\n#define OPAMP_SEC_INVERTINGINPUT_VM1          OPAMP_SEC_INVERTINGINPUT_IO1    \r\n\r\n#define OPAMP_INVERTINGINPUT_VINM             OPAMP_SEC_INVERTINGINPUT_IO1\r\n                                                                      \r\n#define OPAMP_PGACONNECT_NO                   OPAMP_PGA_CONNECT_INVERTINGINPUT_NO             \r\n#define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0            \r\n#define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1          \r\n                                                        \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define I2S_STANDARD_PHILLIPS      I2S_STANDARD_PHILIPS\r\n#if defined(STM32F7) \r\n  #define I2S_CLOCK_SYSCLK           I2S_CLOCK_PLL\r\n#endif\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n/* Compact Flash-ATA registers description */\r\n#define CF_DATA                       ATA_DATA                \r\n#define CF_SECTOR_COUNT               ATA_SECTOR_COUNT        \r\n#define CF_SECTOR_NUMBER              ATA_SECTOR_NUMBER       \r\n#define CF_CYLINDER_LOW               ATA_CYLINDER_LOW        \r\n#define CF_CYLINDER_HIGH              ATA_CYLINDER_HIGH       \r\n#define CF_CARD_HEAD                  ATA_CARD_HEAD           \r\n#define CF_STATUS_CMD                 ATA_STATUS_CMD          \r\n#define CF_STATUS_CMD_ALTERNATE       ATA_STATUS_CMD_ALTERNATE\r\n#define CF_COMMON_DATA_AREA           ATA_COMMON_DATA_AREA    \r\n\r\n/* Compact Flash-ATA commands */\r\n#define CF_READ_SECTOR_CMD            ATA_READ_SECTOR_CMD \r\n#define CF_WRITE_SECTOR_CMD           ATA_WRITE_SECTOR_CMD\r\n#define CF_ERASE_SECTOR_CMD           ATA_ERASE_SECTOR_CMD\r\n#define CF_IDENTIFY_CMD               ATA_IDENTIFY_CMD\r\n\r\n#define PCCARD_StatusTypedef          HAL_PCCARD_StatusTypeDef\r\n#define PCCARD_SUCCESS                HAL_PCCARD_STATUS_SUCCESS\r\n#define PCCARD_ONGOING                HAL_PCCARD_STATUS_ONGOING\r\n#define PCCARD_ERROR                  HAL_PCCARD_STATUS_ERROR\r\n#define PCCARD_TIMEOUT                HAL_PCCARD_STATUS_TIMEOUT\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n  \r\n#define FORMAT_BIN                  RTC_FORMAT_BIN\r\n#define FORMAT_BCD                  RTC_FORMAT_BCD\r\n\r\n#define RTC_ALARMSUBSECONDMASK_None     RTC_ALARMSUBSECONDMASK_NONE\r\n#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE\r\n#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE\r\n#define RTC_TAMPERMASK_FLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE\r\n#define RTC_TAMPERMASK_FLAG_ENABLED     RTC_TAMPERMASK_FLAG_ENABLE\r\n\r\n#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE \r\n#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE \r\n#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE\r\n#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE \r\n#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE \r\n#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE\r\n#define RTC_TAMPER1_2_INTERRUPT         RTC_ALL_TAMPER_INTERRUPT \r\n#define RTC_TAMPER1_2_3_INTERRUPT       RTC_ALL_TAMPER_INTERRUPT \r\n\r\n#define RTC_TIMESTAMPPIN_PC13  RTC_TIMESTAMPPIN_DEFAULT\r\n#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 \r\n#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1\r\n#define RTC_TIMESTAMPPIN_PC1   RTC_TIMESTAMPPIN_POS2\r\n\r\n#define RTC_OUTPUT_REMAP_PC13  RTC_OUTPUT_REMAP_NONE\r\n#define RTC_OUTPUT_REMAP_PB14  RTC_OUTPUT_REMAP_POS1\r\n#define RTC_OUTPUT_REMAP_PB2   RTC_OUTPUT_REMAP_POS1\r\n\r\n#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT \r\n#define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1 \r\n#define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n  \r\n/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define SMARTCARD_NACK_ENABLED                  SMARTCARD_NACK_ENABLE\r\n#define SMARTCARD_NACK_DISABLED                 SMARTCARD_NACK_DISABLE\r\n\r\n#define SMARTCARD_ONEBIT_SAMPLING_DISABLED      SMARTCARD_ONE_BIT_SAMPLE_DISABLE\r\n#define SMARTCARD_ONEBIT_SAMPLING_ENABLED       SMARTCARD_ONE_BIT_SAMPLE_ENABLE\r\n#define SMARTCARD_ONEBIT_SAMPLING_DISABLE       SMARTCARD_ONE_BIT_SAMPLE_DISABLE\r\n#define SMARTCARD_ONEBIT_SAMPLING_ENABLE        SMARTCARD_ONE_BIT_SAMPLE_ENABLE\r\n\r\n#define SMARTCARD_TIMEOUT_DISABLED              SMARTCARD_TIMEOUT_DISABLE\r\n#define SMARTCARD_TIMEOUT_ENABLED               SMARTCARD_TIMEOUT_ENABLE\r\n\r\n#define SMARTCARD_LASTBIT_DISABLED              SMARTCARD_LASTBIT_DISABLE\r\n#define SMARTCARD_LASTBIT_ENABLED               SMARTCARD_LASTBIT_ENABLE\r\n/**\r\n  * @}\r\n  */\r\n\r\n  \r\n/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define SMBUS_DUALADDRESS_DISABLED      SMBUS_DUALADDRESS_DISABLE\r\n#define SMBUS_DUALADDRESS_ENABLED       SMBUS_DUALADDRESS_ENABLE\r\n#define SMBUS_GENERALCALL_DISABLED      SMBUS_GENERALCALL_DISABLE\r\n#define SMBUS_GENERALCALL_ENABLED       SMBUS_GENERALCALL_ENABLE\r\n#define SMBUS_NOSTRETCH_DISABLED        SMBUS_NOSTRETCH_DISABLE\r\n#define SMBUS_NOSTRETCH_ENABLED         SMBUS_NOSTRETCH_ENABLE\r\n#define SMBUS_ANALOGFILTER_ENABLED      SMBUS_ANALOGFILTER_ENABLE\r\n#define SMBUS_ANALOGFILTER_DISABLED     SMBUS_ANALOGFILTER_DISABLE\r\n#define SMBUS_PEC_DISABLED              SMBUS_PEC_DISABLE\r\n#define SMBUS_PEC_ENABLED               SMBUS_PEC_ENABLE\r\n#define HAL_SMBUS_STATE_SLAVE_LISTEN    HAL_SMBUS_STATE_LISTEN\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define SPI_TIMODE_DISABLED             SPI_TIMODE_DISABLE\r\n#define SPI_TIMODE_ENABLED              SPI_TIMODE_ENABLE\r\n\r\n#define SPI_CRCCALCULATION_DISABLED     SPI_CRCCALCULATION_DISABLE\r\n#define SPI_CRCCALCULATION_ENABLED      SPI_CRCCALCULATION_ENABLE\r\n\r\n#define SPI_NSS_PULSE_DISABLED          SPI_NSS_PULSE_DISABLE\r\n#define SPI_NSS_PULSE_ENABLED           SPI_NSS_PULSE_ENABLE\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define CCER_CCxE_MASK                   TIM_CCER_CCxE_MASK\r\n#define CCER_CCxNE_MASK                  TIM_CCER_CCxNE_MASK\r\n  \r\n#define TIM_DMABase_CR1                  TIM_DMABASE_CR1\r\n#define TIM_DMABase_CR2                  TIM_DMABASE_CR2\r\n#define TIM_DMABase_SMCR                 TIM_DMABASE_SMCR\r\n#define TIM_DMABase_DIER                 TIM_DMABASE_DIER\r\n#define TIM_DMABase_SR                   TIM_DMABASE_SR\r\n#define TIM_DMABase_EGR                  TIM_DMABASE_EGR\r\n#define TIM_DMABase_CCMR1                TIM_DMABASE_CCMR1\r\n#define TIM_DMABase_CCMR2                TIM_DMABASE_CCMR2\r\n#define TIM_DMABase_CCER                 TIM_DMABASE_CCER\r\n#define TIM_DMABase_CNT                  TIM_DMABASE_CNT\r\n#define TIM_DMABase_PSC                  TIM_DMABASE_PSC\r\n#define TIM_DMABase_ARR                  TIM_DMABASE_ARR\r\n#define TIM_DMABase_RCR                  TIM_DMABASE_RCR\r\n#define TIM_DMABase_CCR1                 TIM_DMABASE_CCR1\r\n#define TIM_DMABase_CCR2                 TIM_DMABASE_CCR2\r\n#define TIM_DMABase_CCR3                 TIM_DMABASE_CCR3\r\n#define TIM_DMABase_CCR4                 TIM_DMABASE_CCR4\r\n#define TIM_DMABase_BDTR                 TIM_DMABASE_BDTR\r\n#define TIM_DMABase_DCR                  TIM_DMABASE_DCR\r\n#define TIM_DMABase_DMAR                 TIM_DMABASE_DMAR\r\n#define TIM_DMABase_OR1                  TIM_DMABASE_OR1\r\n#define TIM_DMABase_CCMR3                TIM_DMABASE_CCMR3\r\n#define TIM_DMABase_CCR5                 TIM_DMABASE_CCR5\r\n#define TIM_DMABase_CCR6                 TIM_DMABASE_CCR6\r\n#define TIM_DMABase_OR2                  TIM_DMABASE_OR2\r\n#define TIM_DMABase_OR3                  TIM_DMABASE_OR3\r\n#define TIM_DMABase_OR                   TIM_DMABASE_OR\r\n\r\n#define TIM_EventSource_Update           TIM_EVENTSOURCE_UPDATE\r\n#define TIM_EventSource_CC1              TIM_EVENTSOURCE_CC1\r\n#define TIM_EventSource_CC2              TIM_EVENTSOURCE_CC2\r\n#define TIM_EventSource_CC3              TIM_EVENTSOURCE_CC3\r\n#define TIM_EventSource_CC4              TIM_EVENTSOURCE_CC4\r\n#define TIM_EventSource_COM              TIM_EVENTSOURCE_COM\r\n#define TIM_EventSource_Trigger          TIM_EVENTSOURCE_TRIGGER\r\n#define TIM_EventSource_Break            TIM_EVENTSOURCE_BREAK\r\n#define TIM_EventSource_Break2           TIM_EVENTSOURCE_BREAK2\r\n\r\n#define TIM_DMABurstLength_1Transfer     TIM_DMABURSTLENGTH_1TRANSFER\r\n#define TIM_DMABurstLength_2Transfers    TIM_DMABURSTLENGTH_2TRANSFERS\r\n#define TIM_DMABurstLength_3Transfers    TIM_DMABURSTLENGTH_3TRANSFERS\r\n#define TIM_DMABurstLength_4Transfers    TIM_DMABURSTLENGTH_4TRANSFERS\r\n#define TIM_DMABurstLength_5Transfers    TIM_DMABURSTLENGTH_5TRANSFERS\r\n#define TIM_DMABurstLength_6Transfers    TIM_DMABURSTLENGTH_6TRANSFERS\r\n#define TIM_DMABurstLength_7Transfers    TIM_DMABURSTLENGTH_7TRANSFERS\r\n#define TIM_DMABurstLength_8Transfers    TIM_DMABURSTLENGTH_8TRANSFERS\r\n#define TIM_DMABurstLength_9Transfers    TIM_DMABURSTLENGTH_9TRANSFERS\r\n#define TIM_DMABurstLength_10Transfers   TIM_DMABURSTLENGTH_10TRANSFERS\r\n#define TIM_DMABurstLength_11Transfers   TIM_DMABURSTLENGTH_11TRANSFERS\r\n#define TIM_DMABurstLength_12Transfers   TIM_DMABURSTLENGTH_12TRANSFERS\r\n#define TIM_DMABurstLength_13Transfers   TIM_DMABURSTLENGTH_13TRANSFERS\r\n#define TIM_DMABurstLength_14Transfers   TIM_DMABURSTLENGTH_14TRANSFERS\r\n#define TIM_DMABurstLength_15Transfers   TIM_DMABURSTLENGTH_15TRANSFERS\r\n#define TIM_DMABurstLength_16Transfers   TIM_DMABURSTLENGTH_16TRANSFERS\r\n#define TIM_DMABurstLength_17Transfers   TIM_DMABURSTLENGTH_17TRANSFERS\r\n#define TIM_DMABurstLength_18Transfers   TIM_DMABURSTLENGTH_18TRANSFERS\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define TSC_SYNC_POL_FALL        TSC_SYNC_POLARITY_FALLING\r\n#define TSC_SYNC_POL_RISE_HIGH   TSC_SYNC_POLARITY_RISING\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define UART_ONEBIT_SAMPLING_DISABLED   UART_ONE_BIT_SAMPLE_DISABLE\r\n#define UART_ONEBIT_SAMPLING_ENABLED    UART_ONE_BIT_SAMPLE_ENABLE\r\n#define UART_ONE_BIT_SAMPLE_DISABLED    UART_ONE_BIT_SAMPLE_DISABLE\r\n#define UART_ONE_BIT_SAMPLE_ENABLED     UART_ONE_BIT_SAMPLE_ENABLE\r\n\r\n#define __HAL_UART_ONEBIT_ENABLE        __HAL_UART_ONE_BIT_SAMPLE_ENABLE\r\n#define __HAL_UART_ONEBIT_DISABLE       __HAL_UART_ONE_BIT_SAMPLE_DISABLE\r\n\r\n#define __DIV_SAMPLING16                UART_DIV_SAMPLING16\r\n#define __DIVMANT_SAMPLING16            UART_DIVMANT_SAMPLING16\r\n#define __DIVFRAQ_SAMPLING16            UART_DIVFRAQ_SAMPLING16\r\n#define __UART_BRR_SAMPLING16           UART_BRR_SAMPLING16\r\n\r\n#define __DIV_SAMPLING8                 UART_DIV_SAMPLING8\r\n#define __DIVMANT_SAMPLING8             UART_DIVMANT_SAMPLING8\r\n#define __DIVFRAQ_SAMPLING8             UART_DIVFRAQ_SAMPLING8\r\n#define __UART_BRR_SAMPLING8            UART_BRR_SAMPLING8\r\n\r\n#define UART_WAKEUPMETHODE_IDLELINE     UART_WAKEUPMETHOD_IDLELINE\r\n#define UART_WAKEUPMETHODE_ADDRESSMARK  UART_WAKEUPMETHOD_ADDRESSMARK\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n  \r\n/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define USART_CLOCK_DISABLED            USART_CLOCK_DISABLE\r\n#define USART_CLOCK_ENABLED             USART_CLOCK_ENABLE\r\n\r\n#define USARTNACK_ENABLED               USART_NACK_ENABLE\r\n#define USARTNACK_DISABLED              USART_NACK_DISABLE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define CFR_BASE                    WWDG_CFR_BASE\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define CAN_FilterFIFO0             CAN_FILTER_FIFO0\r\n#define CAN_FilterFIFO1             CAN_FILTER_FIFO1\r\n#define CAN_IT_RQCP0                CAN_IT_TME\r\n#define CAN_IT_RQCP1                CAN_IT_TME\r\n#define CAN_IT_RQCP2                CAN_IT_TME\r\n#define INAK_TIMEOUT                CAN_TIMEOUT_VALUE\r\n#define SLAK_TIMEOUT                CAN_TIMEOUT_VALUE\r\n#define CAN_TXSTATUS_FAILED         ((uint8_t)0x00U)\r\n#define CAN_TXSTATUS_OK             ((uint8_t)0x01U)\r\n#define CAN_TXSTATUS_PENDING        ((uint8_t)0x02U)\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define VLAN_TAG                ETH_VLAN_TAG\r\n#define MIN_ETH_PAYLOAD         ETH_MIN_ETH_PAYLOAD\r\n#define MAX_ETH_PAYLOAD         ETH_MAX_ETH_PAYLOAD\r\n#define JUMBO_FRAME_PAYLOAD     ETH_JUMBO_FRAME_PAYLOAD\r\n#define MACMIIAR_CR_MASK        ETH_MACMIIAR_CR_MASK\r\n#define MACCR_CLEAR_MASK        ETH_MACCR_CLEAR_MASK\r\n#define MACFCR_CLEAR_MASK       ETH_MACFCR_CLEAR_MASK\r\n#define DMAOMR_CLEAR_MASK       ETH_DMAOMR_CLEAR_MASK\r\n\r\n#define ETH_MMCCR              ((uint32_t)0x00000100U)  \r\n#define ETH_MMCRIR             ((uint32_t)0x00000104U)  \r\n#define ETH_MMCTIR             ((uint32_t)0x00000108U)  \r\n#define ETH_MMCRIMR            ((uint32_t)0x0000010CU)  \r\n#define ETH_MMCTIMR            ((uint32_t)0x00000110U)  \r\n#define ETH_MMCTGFSCCR         ((uint32_t)0x0000014CU)  \r\n#define ETH_MMCTGFMSCCR        ((uint32_t)0x00000150U)  \r\n#define ETH_MMCTGFCR           ((uint32_t)0x00000168U)  \r\n#define ETH_MMCRFCECR          ((uint32_t)0x00000194U)  \r\n#define ETH_MMCRFAECR          ((uint32_t)0x00000198U)  \r\n#define ETH_MMCRGUFCR          ((uint32_t)0x000001C4U)\r\n \r\n#define ETH_MAC_TXFIFO_FULL          ((uint32_t)0x02000000)  /* Tx FIFO full */\r\n#define ETH_MAC_TXFIFONOT_EMPTY      ((uint32_t)0x01000000)  /* Tx FIFO not empty */\r\n#define ETH_MAC_TXFIFO_WRITE_ACTIVE  ((uint32_t)0x00400000)  /* Tx FIFO write active */\r\n#define ETH_MAC_TXFIFO_IDLE     ((uint32_t)0x00000000)  /* Tx FIFO read status: Idle */\r\n#define ETH_MAC_TXFIFO_READ     ((uint32_t)0x00100000)  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */\r\n#define ETH_MAC_TXFIFO_WAITING  ((uint32_t)0x00200000)  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */\r\n#define ETH_MAC_TXFIFO_WRITING  ((uint32_t)0x00300000)  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */\r\n#define ETH_MAC_TRANSMISSION_PAUSE     ((uint32_t)0x00080000)  /* MAC transmitter in pause */\r\n#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE            ((uint32_t)0x00000000)  /* MAC transmit frame controller: Idle */\r\n#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         ((uint32_t)0x00020000)  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */\r\n#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   ((uint32_t)0x00040000)  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */\r\n#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    ((uint32_t)0x00060000)  /* MAC transmit frame controller: Transferring input frame for transmission */\r\n#define ETH_MAC_MII_TRANSMIT_ACTIVE      ((uint32_t)0x00010000)  /* MAC MII transmit engine active */\r\n#define ETH_MAC_RXFIFO_EMPTY             ((uint32_t)0x00000000)  /* Rx FIFO fill level: empty */\r\n#define ETH_MAC_RXFIFO_BELOW_THRESHOLD   ((uint32_t)0x00000100)  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */\r\n#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD   ((uint32_t)0x00000200)  /* Rx FIFO fill level: fill-level above flow-control activate threshold */\r\n#define ETH_MAC_RXFIFO_FULL              ((uint32_t)0x00000300)  /* Rx FIFO fill level: full */\r\n#if defined(STM32F1)\r\n#else\r\n#define ETH_MAC_READCONTROLLER_IDLE               ((uint32_t)0x00000000)  /* Rx FIFO read controller IDLE state */\r\n#define ETH_MAC_READCONTROLLER_READING_DATA       ((uint32_t)0x00000020)  /* Rx FIFO read controller Reading frame data */\r\n#define ETH_MAC_READCONTROLLER_READING_STATUS     ((uint32_t)0x00000040)  /* Rx FIFO read controller Reading frame status (or time-stamp) */\r\n#endif\r\n#define ETH_MAC_READCONTROLLER_FLUSHING           ((uint32_t)0x00000060)  /* Rx FIFO read controller Flushing the frame data and status */\r\n#define ETH_MAC_RXFIFO_WRITE_ACTIVE     ((uint32_t)0x00000010)  /* Rx FIFO write controller active */\r\n#define ETH_MAC_SMALL_FIFO_NOTACTIVE    ((uint32_t)0x00000000)  /* MAC small FIFO read / write controllers not active */\r\n#define ETH_MAC_SMALL_FIFO_READ_ACTIVE  ((uint32_t)0x00000002)  /* MAC small FIFO read controller active */\r\n#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004)  /* MAC small FIFO write controller active */\r\n#define ETH_MAC_SMALL_FIFO_RW_ACTIVE    ((uint32_t)0x00000006)  /* MAC small FIFO read / write controllers active */\r\n#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   ((uint32_t)0x00000001)  /* MAC MII receive protocol engine active */\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define HAL_DCMI_ERROR_OVF      HAL_DCMI_ERROR_OVR\r\n#define DCMI_IT_OVF             DCMI_IT_OVR\r\n#define DCMI_FLAG_OVFRI         DCMI_FLAG_OVRRI\r\n#define DCMI_FLAG_OVFMI         DCMI_FLAG_OVRMI\r\n\r\n#define HAL_DCMI_ConfigCROP     HAL_DCMI_ConfigCrop\r\n#define HAL_DCMI_EnableCROP     HAL_DCMI_EnableCrop\r\n#define HAL_DCMI_DisableCROP    HAL_DCMI_DisableCrop\r\n\r\n/**\r\n  * @}\r\n  */  \r\n  \r\n#if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\\\r\n    defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)\r\n/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define DMA2D_ARGB8888          DMA2D_OUTPUT_ARGB8888\r\n#define DMA2D_RGB888            DMA2D_OUTPUT_RGB888  \r\n#define DMA2D_RGB565            DMA2D_OUTPUT_RGB565  \r\n#define DMA2D_ARGB1555          DMA2D_OUTPUT_ARGB1555\r\n#define DMA2D_ARGB4444          DMA2D_OUTPUT_ARGB4444\r\n\r\n#define CM_ARGB8888             DMA2D_INPUT_ARGB8888\r\n#define CM_RGB888               DMA2D_INPUT_RGB888  \r\n#define CM_RGB565               DMA2D_INPUT_RGB565  \r\n#define CM_ARGB1555             DMA2D_INPUT_ARGB1555\r\n#define CM_ARGB4444             DMA2D_INPUT_ARGB4444\r\n#define CM_L8                   DMA2D_INPUT_L8      \r\n#define CM_AL44                 DMA2D_INPUT_AL44    \r\n#define CM_AL88                 DMA2D_INPUT_AL88    \r\n#define CM_L4                   DMA2D_INPUT_L4      \r\n#define CM_A8                   DMA2D_INPUT_A8      \r\n#define CM_A4                   DMA2D_INPUT_A4      \r\n/**\r\n  * @}\r\n  */    \r\n#endif  /* STM32L4xx ||  STM32F7*/\r\n\r\n/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define HAL_CRYP_ComputationCpltCallback     HAL_CRYPEx_ComputationCpltCallback\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose\r\n  * @{\r\n  */ \r\n#define HAL_HASH_STATETypeDef        HAL_HASH_StateTypeDef\r\n#define HAL_HASHPhaseTypeDef         HAL_HASH_PhaseTypeDef\r\n#define HAL_HMAC_MD5_Finish          HAL_HASH_MD5_Finish\r\n#define HAL_HMAC_SHA1_Finish         HAL_HASH_SHA1_Finish\r\n#define HAL_HMAC_SHA224_Finish       HAL_HASH_SHA224_Finish\r\n#define HAL_HMAC_SHA256_Finish       HAL_HASH_SHA256_Finish\r\n\r\n/*HASH Algorithm Selection*/\r\n\r\n#define HASH_AlgoSelection_SHA1      HASH_ALGOSELECTION_SHA1 \r\n#define HASH_AlgoSelection_SHA224    HASH_ALGOSELECTION_SHA224\r\n#define HASH_AlgoSelection_SHA256    HASH_ALGOSELECTION_SHA256\r\n#define HASH_AlgoSelection_MD5       HASH_ALGOSELECTION_MD5\r\n\r\n#define HASH_AlgoMode_HASH         HASH_ALGOMODE_HASH \r\n#define HASH_AlgoMode_HMAC         HASH_ALGOMODE_HMAC\r\n\r\n#define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY\r\n#define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode\r\n#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode\r\n#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode\r\n#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode\r\n#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode\r\n#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode\r\n#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))\r\n#define HAL_VREFINT_OutputSelect  HAL_SYSCFG_VREFINT_OutputSelect\r\n#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())\r\n#if defined(STM32L0)\r\n#else\r\n#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())\r\n#endif\r\n#define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())\r\n#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define FLASH_HalfPageProgram      HAL_FLASHEx_HalfPageProgram\r\n#define FLASH_EnableRunPowerDown   HAL_FLASHEx_EnableRunPowerDown\r\n#define FLASH_DisableRunPowerDown  HAL_FLASHEx_DisableRunPowerDown\r\n#define HAL_DATA_EEPROMEx_Unlock   HAL_FLASHEx_DATAEEPROM_Unlock\r\n#define HAL_DATA_EEPROMEx_Lock     HAL_FLASHEx_DATAEEPROM_Lock\r\n#define HAL_DATA_EEPROMEx_Erase    HAL_FLASHEx_DATAEEPROM_Erase\r\n#define HAL_DATA_EEPROMEx_Program  HAL_FLASHEx_DATAEEPROM_Program\r\n\r\n /**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define HAL_I2CEx_AnalogFilter_Config         HAL_I2CEx_ConfigAnalogFilter\r\n#define HAL_I2CEx_DigitalFilter_Config        HAL_I2CEx_ConfigDigitalFilter\r\n#define HAL_FMPI2CEx_AnalogFilter_Config      HAL_FMPI2CEx_ConfigAnalogFilter\r\n#define HAL_FMPI2CEx_DigitalFilter_Config     HAL_FMPI2CEx_ConfigDigitalFilter\r\n\r\n#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))\r\n /**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define HAL_PWR_PVDConfig                             HAL_PWR_ConfigPVD\r\n#define HAL_PWR_DisableBkUpReg                        HAL_PWREx_DisableBkUpReg\r\n#define HAL_PWR_DisableFlashPowerDown                 HAL_PWREx_DisableFlashPowerDown\r\n#define HAL_PWR_DisableVddio2Monitor                  HAL_PWREx_DisableVddio2Monitor\r\n#define HAL_PWR_EnableBkUpReg                         HAL_PWREx_EnableBkUpReg\r\n#define HAL_PWR_EnableFlashPowerDown                  HAL_PWREx_EnableFlashPowerDown\r\n#define HAL_PWR_EnableVddio2Monitor                   HAL_PWREx_EnableVddio2Monitor\r\n#define HAL_PWR_PVD_PVM_IRQHandler                    HAL_PWREx_PVD_PVM_IRQHandler\r\n#define HAL_PWR_PVDLevelConfig                        HAL_PWR_ConfigPVD\r\n#define HAL_PWR_Vddio2Monitor_IRQHandler              HAL_PWREx_Vddio2Monitor_IRQHandler\r\n#define HAL_PWR_Vddio2MonitorCallback                 HAL_PWREx_Vddio2MonitorCallback\r\n#define HAL_PWREx_ActivateOverDrive                   HAL_PWREx_EnableOverDrive\r\n#define HAL_PWREx_DeactivateOverDrive                 HAL_PWREx_DisableOverDrive\r\n#define HAL_PWREx_DisableSDADCAnalog                  HAL_PWREx_DisableSDADC\r\n#define HAL_PWREx_EnableSDADCAnalog                   HAL_PWREx_EnableSDADC\r\n#define HAL_PWREx_PVMConfig                           HAL_PWREx_ConfigPVM\r\n\r\n#define PWR_MODE_NORMAL                               PWR_PVD_MODE_NORMAL\r\n#define PWR_MODE_IT_RISING                            PWR_PVD_MODE_IT_RISING\r\n#define PWR_MODE_IT_FALLING                           PWR_PVD_MODE_IT_FALLING\r\n#define PWR_MODE_IT_RISING_FALLING                    PWR_PVD_MODE_IT_RISING_FALLING\r\n#define PWR_MODE_EVENT_RISING                         PWR_PVD_MODE_EVENT_RISING\r\n#define PWR_MODE_EVENT_FALLING                        PWR_PVD_MODE_EVENT_FALLING\r\n#define PWR_MODE_EVENT_RISING_FALLING                 PWR_PVD_MODE_EVENT_RISING_FALLING\r\n\r\n#define CR_OFFSET_BB                                  PWR_CR_OFFSET_BB\r\n#define CSR_OFFSET_BB                                 PWR_CSR_OFFSET_BB\r\n\r\n#define DBP_BitNumber                                 DBP_BIT_NUMBER\r\n#define PVDE_BitNumber                                PVDE_BIT_NUMBER\r\n#define PMODE_BitNumber                               PMODE_BIT_NUMBER\r\n#define EWUP_BitNumber                                EWUP_BIT_NUMBER\r\n#define FPDS_BitNumber                                FPDS_BIT_NUMBER\r\n#define ODEN_BitNumber                                ODEN_BIT_NUMBER\r\n#define ODSWEN_BitNumber                              ODSWEN_BIT_NUMBER\r\n#define MRLVDS_BitNumber                              MRLVDS_BIT_NUMBER\r\n#define LPLVDS_BitNumber                              LPLVDS_BIT_NUMBER\r\n#define BRE_BitNumber                                 BRE_BIT_NUMBER\r\n\r\n#define PWR_MODE_EVT                                  PWR_PVD_MODE_NORMAL\r\n \r\n /**\r\n  * @}\r\n  */  \r\n  \r\n/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define HAL_SMBUS_Slave_Listen_IT          HAL_SMBUS_EnableListen_IT\r\n#define HAL_SMBUS_SlaveAddrCallback        HAL_SMBUS_AddrCallback         \r\n#define HAL_SMBUS_SlaveListenCpltCallback  HAL_SMBUS_ListenCpltCallback   \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define HAL_SPI_FlushRxFifo                HAL_SPIEx_FlushRxFifo\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define HAL_TIM_DMADelayPulseCplt                       TIM_DMADelayPulseCplt\r\n#define HAL_TIM_DMAError                                TIM_DMAError\r\n#define HAL_TIM_DMACaptureCplt                          TIM_DMACaptureCplt\r\n#define HAL_TIMEx_DMACommutationCplt                    TIMEx_DMACommutationCplt\r\n/**\r\n  * @}\r\n  */\r\n   \r\n/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose\r\n  * @{\r\n  */ \r\n#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose\r\n  * @{\r\n  */ \r\n#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback\r\n/**\r\n  * @}\r\n  */  \r\n   \r\n  \r\n/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macros ------------------------------------------------------------*/\r\n\r\n/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define AES_IT_CC                      CRYP_IT_CC\r\n#define AES_IT_ERR                     CRYP_IT_ERR\r\n#define AES_FLAG_CCF                   CRYP_FLAG_CCF\r\n/**\r\n  * @}\r\n  */  \r\n  \r\n/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define __HAL_GET_BOOT_MODE                   __HAL_SYSCFG_GET_BOOT_MODE\r\n#define __HAL_REMAPMEMORY_FLASH               __HAL_SYSCFG_REMAPMEMORY_FLASH\r\n#define __HAL_REMAPMEMORY_SYSTEMFLASH         __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH\r\n#define __HAL_REMAPMEMORY_SRAM                __HAL_SYSCFG_REMAPMEMORY_SRAM\r\n#define __HAL_REMAPMEMORY_FMC                 __HAL_SYSCFG_REMAPMEMORY_FMC\r\n#define __HAL_REMAPMEMORY_FMC_SDRAM           __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM \r\n#define __HAL_REMAPMEMORY_FSMC                __HAL_SYSCFG_REMAPMEMORY_FSMC\r\n#define __HAL_REMAPMEMORY_QUADSPI             __HAL_SYSCFG_REMAPMEMORY_QUADSPI\r\n#define __HAL_FMC_BANK                        __HAL_SYSCFG_FMC_BANK\r\n#define __HAL_GET_FLAG                        __HAL_SYSCFG_GET_FLAG\r\n#define __HAL_CLEAR_FLAG                      __HAL_SYSCFG_CLEAR_FLAG\r\n#define __HAL_VREFINT_OUT_ENABLE              __HAL_SYSCFG_VREFINT_OUT_ENABLE\r\n#define __HAL_VREFINT_OUT_DISABLE             __HAL_SYSCFG_VREFINT_OUT_DISABLE\r\n\r\n#define SYSCFG_FLAG_VREF_READY                SYSCFG_FLAG_VREFINT_READY\r\n#define SYSCFG_FLAG_RC48                      RCC_FLAG_HSI48\r\n#define IS_SYSCFG_FASTMODEPLUS_CONFIG         IS_I2C_FASTMODEPLUS\r\n#define UFB_MODE_BitNumber                    UFB_MODE_BIT_NUMBER\r\n#define CMP_PD_BitNumber                      CMP_PD_BIT_NUMBER\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n   \r\n/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define __ADC_ENABLE                                     __HAL_ADC_ENABLE\r\n#define __ADC_DISABLE                                    __HAL_ADC_DISABLE\r\n#define __HAL_ADC_ENABLING_CONDITIONS                    ADC_ENABLING_CONDITIONS\r\n#define __HAL_ADC_DISABLING_CONDITIONS                   ADC_DISABLING_CONDITIONS\r\n#define __HAL_ADC_IS_ENABLED                             ADC_IS_ENABLE\r\n#define __ADC_IS_ENABLED                                 ADC_IS_ENABLE\r\n#define __HAL_ADC_IS_SOFTWARE_START_REGULAR              ADC_IS_SOFTWARE_START_REGULAR\r\n#define __HAL_ADC_IS_SOFTWARE_START_INJECTED             ADC_IS_SOFTWARE_START_INJECTED\r\n#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED\r\n#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR          ADC_IS_CONVERSION_ONGOING_REGULAR\r\n#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED         ADC_IS_CONVERSION_ONGOING_INJECTED\r\n#define __HAL_ADC_IS_CONVERSION_ONGOING                  ADC_IS_CONVERSION_ONGOING\r\n#define __HAL_ADC_CLEAR_ERRORCODE                        ADC_CLEAR_ERRORCODE\r\n\r\n#define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION\r\n#define __HAL_ADC_JSQR_RK                                ADC_JSQR_RK\r\n#define __HAL_ADC_CFGR_AWD1CH                            ADC_CFGR_AWD1CH_SHIFT\r\n#define __HAL_ADC_CFGR_AWD23CR                           ADC_CFGR_AWD23CR\r\n#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION            ADC_CFGR_INJECT_AUTO_CONVERSION\r\n#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE              ADC_CFGR_INJECT_CONTEXT_QUEUE\r\n#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS             ADC_CFGR_INJECT_DISCCONTINUOUS\r\n#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS                ADC_CFGR_REG_DISCCONTINUOUS\r\n#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM                 ADC_CFGR_DISCONTINUOUS_NUM\r\n#define __HAL_ADC_CFGR_AUTOWAIT                          ADC_CFGR_AUTOWAIT\r\n#define __HAL_ADC_CFGR_CONTINUOUS                        ADC_CFGR_CONTINUOUS\r\n#define __HAL_ADC_CFGR_OVERRUN                           ADC_CFGR_OVERRUN\r\n#define __HAL_ADC_CFGR_DMACONTREQ                        ADC_CFGR_DMACONTREQ\r\n#define __HAL_ADC_CFGR_EXTSEL                            ADC_CFGR_EXTSEL_SET\r\n#define __HAL_ADC_JSQR_JEXTSEL                           ADC_JSQR_JEXTSEL_SET\r\n#define __HAL_ADC_OFR_CHANNEL                            ADC_OFR_CHANNEL\r\n#define __HAL_ADC_DIFSEL_CHANNEL                         ADC_DIFSEL_CHANNEL\r\n#define __HAL_ADC_CALFACT_DIFF_SET                       ADC_CALFACT_DIFF_SET\r\n#define __HAL_ADC_CALFACT_DIFF_GET                       ADC_CALFACT_DIFF_GET\r\n#define __HAL_ADC_TRX_HIGHTHRESHOLD                      ADC_TRX_HIGHTHRESHOLD\r\n\r\n#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION                ADC_OFFSET_SHIFT_RESOLUTION\r\n#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION         ADC_AWD1THRESHOLD_SHIFT_RESOLUTION\r\n#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION        ADC_AWD23THRESHOLD_SHIFT_RESOLUTION\r\n#define __HAL_ADC_COMMON_REGISTER                        ADC_COMMON_REGISTER\r\n#define __HAL_ADC_COMMON_CCR_MULTI                       ADC_COMMON_CCR_MULTI\r\n#define __HAL_ADC_MULTIMODE_IS_ENABLED                   ADC_MULTIMODE_IS_ENABLE\r\n#define __ADC_MULTIMODE_IS_ENABLED                       ADC_MULTIMODE_IS_ENABLE\r\n#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER        ADC_NONMULTIMODE_OR_MULTIMODEMASTER\r\n#define __HAL_ADC_COMMON_ADC_OTHER                       ADC_COMMON_ADC_OTHER\r\n#define __HAL_ADC_MULTI_SLAVE                            ADC_MULTI_SLAVE\r\n\r\n#define __HAL_ADC_SQR1_L                                 ADC_SQR1_L_SHIFT\r\n#define __HAL_ADC_JSQR_JL                                ADC_JSQR_JL_SHIFT\r\n#define __HAL_ADC_JSQR_RK_JL                             ADC_JSQR_RK_JL\r\n#define __HAL_ADC_CR1_DISCONTINUOUS_NUM                  ADC_CR1_DISCONTINUOUS_NUM\r\n#define __HAL_ADC_CR1_SCAN                               ADC_CR1_SCAN_SET\r\n#define __HAL_ADC_CONVCYCLES_MAX_RANGE                   ADC_CONVCYCLES_MAX_RANGE\r\n#define __HAL_ADC_CLOCK_PRESCALER_RANGE                  ADC_CLOCK_PRESCALER_RANGE\r\n#define __HAL_ADC_GET_CLOCK_PRESCALER                    ADC_GET_CLOCK_PRESCALER\r\n\r\n#define __HAL_ADC_SQR1                                   ADC_SQR1\r\n#define __HAL_ADC_SMPR1                                  ADC_SMPR1\r\n#define __HAL_ADC_SMPR2                                  ADC_SMPR2\r\n#define __HAL_ADC_SQR3_RK                                ADC_SQR3_RK\r\n#define __HAL_ADC_SQR2_RK                                ADC_SQR2_RK\r\n#define __HAL_ADC_SQR1_RK                                ADC_SQR1_RK\r\n#define __HAL_ADC_CR2_CONTINUOUS                         ADC_CR2_CONTINUOUS\r\n#define __HAL_ADC_CR1_DISCONTINUOUS                      ADC_CR1_DISCONTINUOUS\r\n#define __HAL_ADC_CR1_SCANCONV                           ADC_CR1_SCANCONV\r\n#define __HAL_ADC_CR2_EOCSelection                       ADC_CR2_EOCSelection\r\n#define __HAL_ADC_CR2_DMAContReq                         ADC_CR2_DMAContReq\r\n#define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION\r\n#define __HAL_ADC_JSQR                                   ADC_JSQR\r\n\r\n#define __HAL_ADC_CHSELR_CHANNEL                         ADC_CHSELR_CHANNEL\r\n#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS               ADC_CFGR1_REG_DISCCONTINUOUS\r\n#define __HAL_ADC_CFGR1_AUTOOFF                          ADC_CFGR1_AUTOOFF\r\n#define __HAL_ADC_CFGR1_AUTOWAIT                         ADC_CFGR1_AUTOWAIT\r\n#define __HAL_ADC_CFGR1_CONTINUOUS                       ADC_CFGR1_CONTINUOUS\r\n#define __HAL_ADC_CFGR1_OVERRUN                          ADC_CFGR1_OVERRUN\r\n#define __HAL_ADC_CFGR1_SCANDIR                          ADC_CFGR1_SCANDIR\r\n#define __HAL_ADC_CFGR1_DMACONTREQ                       ADC_CFGR1_DMACONTREQ\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define __HAL_DHR12R1_ALIGNEMENT                        DAC_DHR12R1_ALIGNMENT\r\n#define __HAL_DHR12R2_ALIGNEMENT                        DAC_DHR12R2_ALIGNMENT\r\n#define __HAL_DHR12RD_ALIGNEMENT                        DAC_DHR12RD_ALIGNMENT\r\n#define IS_DAC_GENERATE_WAVE                            IS_DAC_WAVE\r\n\r\n/**\r\n  * @}\r\n  */\r\n   \r\n/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1\r\n#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1\r\n#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2\r\n#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2\r\n#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3\r\n#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3\r\n#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4\r\n#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4\r\n#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5\r\n#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5\r\n#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6\r\n#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6\r\n#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7\r\n#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7\r\n#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8\r\n#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8\r\n\r\n#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9\r\n#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9\r\n#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10\r\n#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10\r\n#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11\r\n#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11\r\n#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12\r\n#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12\r\n#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13\r\n#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13\r\n#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14\r\n#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14\r\n#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2\r\n#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2\r\n\r\n\r\n#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15\r\n#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15\r\n#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16\r\n#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16\r\n#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17\r\n#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17\r\n#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC\r\n#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC\r\n#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG\r\n#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG\r\n#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG\r\n#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG\r\n#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT\r\n#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT\r\n#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT\r\n#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT\r\n#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT\r\n#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT\r\n#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1\r\n#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1\r\n#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1\r\n#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1\r\n#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2\r\n#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n#if defined(STM32F3)\r\n#define COMP_START                                       __HAL_COMP_ENABLE\r\n#define COMP_STOP                                        __HAL_COMP_DISABLE\r\n#define COMP_LOCK                                        __HAL_COMP_LOCK\r\n   \r\n#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\r\n#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())\r\n#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())\r\n#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())\r\n#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())\r\n#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \\\r\n                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())\r\n#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \\\r\n                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())\r\n#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \\\r\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \\\r\n                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())\r\n#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \\\r\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \\\r\n                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())\r\n# endif\r\n# if defined(STM32F302xE) || defined(STM32F302xC)\r\n#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())\r\n#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())\r\n#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())\r\n#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())\r\n#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \\\r\n                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())\r\n#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \\\r\n                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())\r\n#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\\r\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \\\r\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \\\r\n                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())\r\n#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\\r\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \\\r\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \\\r\n                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())\r\n# endif\r\n# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)\r\n#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())\r\n#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())\r\n#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())\r\n#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())\r\n#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \\\r\n                                                          __HAL_COMP_COMP7_EXTI_ENABLE_IT())\r\n#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \\\r\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \\\r\n                                                          __HAL_COMP_COMP7_EXTI_DISABLE_IT())\r\n#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\\r\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \\\r\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \\\r\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \\\r\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \\\r\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \\\r\n                                                          __HAL_COMP_COMP7_EXTI_GET_FLAG())\r\n#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\\r\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \\\r\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \\\r\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \\\r\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \\\r\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \\\r\n                                                          __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())\r\n# endif\r\n# if defined(STM32F373xC) ||defined(STM32F378xx)\r\n#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())\r\n#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())\r\n#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())\r\n#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())\r\n#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\\r\n                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())\r\n#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\\r\n                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())\r\n#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\\r\n                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())\r\n#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\\r\n                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())\r\n# endif\r\n#else\r\n#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())\r\n#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())\r\n#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())\r\n#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\\r\n                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())\r\n#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\\r\n                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())\r\n#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\\r\n                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())\r\n#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\\r\n                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())\r\n#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\\r\n                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())\r\n#endif\r\n\r\n#define __HAL_COMP_GET_EXTI_LINE  COMP_GET_EXTI_LINE\r\n\r\n#if defined(STM32L0) || defined(STM32L4)\r\n/* Note: On these STM32 families, the only argument of this macro             */\r\n/*       is COMP_FLAG_LOCK.                                                   */\r\n/*       This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle  */\r\n/*       argument.                                                            */\r\n#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__)  (__HAL_COMP_IS_LOCKED(__HANDLE__))\r\n#endif\r\n/**\r\n  * @}\r\n  */\r\n\r\n#if defined(STM32L0) || defined(STM32L4)\r\n/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define HAL_COMP_Start_IT       HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */\r\n#define HAL_COMP_Stop_IT        HAL_COMP_Stop  /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */\r\n/**\r\n  * @}\r\n  */\r\n#endif\r\n\r\n/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \\\r\n                          ((WAVE) == DAC_WAVE_NOISE)|| \\\r\n                          ((WAVE) == DAC_WAVE_TRIANGLE))\r\n  \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define IS_WRPAREA          IS_OB_WRPAREA\r\n#define IS_TYPEPROGRAM      IS_FLASH_TYPEPROGRAM\r\n#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM\r\n#define IS_TYPEERASE        IS_FLASH_TYPEERASE\r\n#define IS_NBSECTORS        IS_FLASH_NBSECTORS\r\n#define IS_OB_WDG_SOURCE    IS_OB_IWDG_SOURCE\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n  \r\n#define __HAL_I2C_RESET_CR2             I2C_RESET_CR2\r\n#define __HAL_I2C_GENERATE_START        I2C_GENERATE_START\r\n#define __HAL_I2C_FREQ_RANGE            I2C_FREQ_RANGE\r\n#define __HAL_I2C_RISE_TIME             I2C_RISE_TIME\r\n#define __HAL_I2C_SPEED_STANDARD        I2C_SPEED_STANDARD\r\n#define __HAL_I2C_SPEED_FAST            I2C_SPEED_FAST\r\n#define __HAL_I2C_SPEED                 I2C_SPEED\r\n#define __HAL_I2C_7BIT_ADD_WRITE        I2C_7BIT_ADD_WRITE\r\n#define __HAL_I2C_7BIT_ADD_READ         I2C_7BIT_ADD_READ\r\n#define __HAL_I2C_10BIT_ADDRESS         I2C_10BIT_ADDRESS\r\n#define __HAL_I2C_10BIT_HEADER_WRITE    I2C_10BIT_HEADER_WRITE\r\n#define __HAL_I2C_10BIT_HEADER_READ     I2C_10BIT_HEADER_READ\r\n#define __HAL_I2C_MEM_ADD_MSB           I2C_MEM_ADD_MSB\r\n#define __HAL_I2C_MEM_ADD_LSB           I2C_MEM_ADD_LSB\r\n#define __HAL_I2C_FREQRANGE             I2C_FREQRANGE\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n  \r\n#define IS_I2S_INSTANCE                 IS_I2S_ALL_INSTANCE\r\n#define IS_I2S_INSTANCE_EXT             IS_I2S_ALL_INSTANCE_EXT\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n  \r\n#define __IRDA_DISABLE                  __HAL_IRDA_DISABLE\r\n#define __IRDA_ENABLE                   __HAL_IRDA_ENABLE\r\n\r\n#define __HAL_IRDA_GETCLOCKSOURCE       IRDA_GETCLOCKSOURCE\r\n#define __HAL_IRDA_MASK_COMPUTATION     IRDA_MASK_COMPUTATION\r\n#define __IRDA_GETCLOCKSOURCE           IRDA_GETCLOCKSOURCE\r\n#define __IRDA_MASK_COMPUTATION         IRDA_MASK_COMPUTATION\r\n\r\n#define IS_IRDA_ONEBIT_SAMPLE           IS_IRDA_ONE_BIT_SAMPLE                  \r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define __HAL_IWDG_ENABLE_WRITE_ACCESS  IWDG_ENABLE_WRITE_ACCESS\r\n#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define __HAL_LPTIM_ENABLE_INTERRUPT    __HAL_LPTIM_ENABLE_IT\r\n#define __HAL_LPTIM_DISABLE_INTERRUPT   __HAL_LPTIM_DISABLE_IT\r\n#define __HAL_LPTIM_GET_ITSTATUS        __HAL_LPTIM_GET_IT_SOURCE\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n  \r\n/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define __OPAMP_CSR_OPAXPD                OPAMP_CSR_OPAXPD\r\n#define __OPAMP_CSR_S3SELX                OPAMP_CSR_S3SELX\r\n#define __OPAMP_CSR_S4SELX                OPAMP_CSR_S4SELX\r\n#define __OPAMP_CSR_S5SELX                OPAMP_CSR_S5SELX\r\n#define __OPAMP_CSR_S6SELX                OPAMP_CSR_S6SELX\r\n#define __OPAMP_CSR_OPAXCAL_L             OPAMP_CSR_OPAXCAL_L\r\n#define __OPAMP_CSR_OPAXCAL_H             OPAMP_CSR_OPAXCAL_H\r\n#define __OPAMP_CSR_OPAXLPM               OPAMP_CSR_OPAXLPM\r\n#define __OPAMP_CSR_ALL_SWITCHES          OPAMP_CSR_ALL_SWITCHES\r\n#define __OPAMP_CSR_ANAWSELX              OPAMP_CSR_ANAWSELX\r\n#define __OPAMP_CSR_OPAXCALOUT            OPAMP_CSR_OPAXCALOUT\r\n#define __OPAMP_OFFSET_TRIM_BITSPOSITION  OPAMP_OFFSET_TRIM_BITSPOSITION\r\n#define __OPAMP_OFFSET_TRIM_SET           OPAMP_OFFSET_TRIM_SET\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define __HAL_PVD_EVENT_DISABLE                                  __HAL_PWR_PVD_EXTI_DISABLE_EVENT\r\n#define __HAL_PVD_EVENT_ENABLE                                   __HAL_PWR_PVD_EXTI_ENABLE_EVENT\r\n#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE\r\n#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE\r\n#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE\r\n#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE\r\n#define __HAL_PVM_EVENT_DISABLE                                  __HAL_PWR_PVM_EVENT_DISABLE\r\n#define __HAL_PVM_EVENT_ENABLE                                   __HAL_PWR_PVM_EVENT_ENABLE\r\n#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE\r\n#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE\r\n#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE\r\n#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE\r\n#define __HAL_PWR_INTERNALWAKEUP_DISABLE                         HAL_PWREx_DisableInternalWakeUpLine\r\n#define __HAL_PWR_INTERNALWAKEUP_ENABLE                          HAL_PWREx_EnableInternalWakeUpLine\r\n#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE                    HAL_PWREx_DisablePullUpPullDownConfig\r\n#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE                     HAL_PWREx_EnablePullUpPullDownConfig\r\n#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER()                  do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)\r\n#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE                         __HAL_PWR_PVD_EXTI_DISABLE_EVENT\r\n#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE                          __HAL_PWR_PVD_EXTI_ENABLE_EVENT\r\n#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE                __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE\r\n#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE                 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE\r\n#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE                 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE\r\n#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE                  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE\r\n#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER              __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE\r\n#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER               __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE\r\n#define __HAL_PWR_PVM_DISABLE()                                  do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)\r\n#define __HAL_PWR_PVM_ENABLE()                                   do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)\r\n#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE                  HAL_PWREx_DisableSRAM2ContentRetention\r\n#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE                   HAL_PWREx_EnableSRAM2ContentRetention\r\n#define __HAL_PWR_VDDIO2_DISABLE                                 HAL_PWREx_DisableVddIO2\r\n#define __HAL_PWR_VDDIO2_ENABLE                                  HAL_PWREx_EnableVddIO2\r\n#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER                 __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE\r\n#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER           __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE\r\n#define __HAL_PWR_VDDUSB_DISABLE                                 HAL_PWREx_DisableVddUSB\r\n#define __HAL_PWR_VDDUSB_ENABLE                                  HAL_PWREx_EnableVddUSB\r\n\r\n#if defined (STM32F4)\r\n#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD)         __HAL_PWR_PVD_EXTI_ENABLE_IT()\r\n#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_DISABLE_IT()\r\n#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD)          __HAL_PWR_PVD_EXTI_GET_FLAG()   \r\n#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_CLEAR_FLAG()\r\n#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD)     __HAL_PWR_PVD_EXTI_GENERATE_SWIT()\r\n#else\r\n#define __HAL_PVD_EXTI_CLEAR_FLAG                                __HAL_PWR_PVD_EXTI_CLEAR_FLAG\r\n#define __HAL_PVD_EXTI_DISABLE_IT                                __HAL_PWR_PVD_EXTI_DISABLE_IT\r\n#define __HAL_PVD_EXTI_ENABLE_IT                                 __HAL_PWR_PVD_EXTI_ENABLE_IT\r\n#define __HAL_PVD_EXTI_GENERATE_SWIT                             __HAL_PWR_PVD_EXTI_GENERATE_SWIT\r\n#define __HAL_PVD_EXTI_GET_FLAG                                  __HAL_PWR_PVD_EXTI_GET_FLAG \r\n#endif /* STM32F4 */\r\n/**   \r\n  * @}\r\n  */  \r\n  \r\n  \r\n/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose\r\n  * @{\r\n  */\r\n  \r\n#define RCC_StopWakeUpClock_MSI     RCC_STOP_WAKEUPCLOCK_MSI\r\n#define RCC_StopWakeUpClock_HSI     RCC_STOP_WAKEUPCLOCK_HSI\r\n\r\n#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback\r\n#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())\r\n\r\n#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE\r\n#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE\r\n#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE\r\n#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE\r\n#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET\r\n#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET\r\n#define __ADC1_CLK_DISABLE        __HAL_RCC_ADC1_CLK_DISABLE\r\n#define __ADC1_CLK_ENABLE         __HAL_RCC_ADC1_CLK_ENABLE\r\n#define __ADC1_FORCE_RESET        __HAL_RCC_ADC1_FORCE_RESET\r\n#define __ADC1_RELEASE_RESET      __HAL_RCC_ADC1_RELEASE_RESET\r\n#define __ADC1_CLK_SLEEP_ENABLE   __HAL_RCC_ADC1_CLK_SLEEP_ENABLE  \r\n#define __ADC1_CLK_SLEEP_DISABLE  __HAL_RCC_ADC1_CLK_SLEEP_DISABLE  \r\n#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE\r\n#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE\r\n#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET\r\n#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET\r\n#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE\r\n#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE\r\n#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET\r\n#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET\r\n#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE\r\n#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE\r\n#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE\r\n#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE\r\n#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET\r\n#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET\r\n#define __CRYP_CLK_SLEEP_ENABLE      __HAL_RCC_CRYP_CLK_SLEEP_ENABLE\r\n#define __CRYP_CLK_SLEEP_DISABLE  __HAL_RCC_CRYP_CLK_SLEEP_DISABLE\r\n#define __CRYP_CLK_ENABLE  __HAL_RCC_CRYP_CLK_ENABLE\r\n#define __CRYP_CLK_DISABLE  __HAL_RCC_CRYP_CLK_DISABLE\r\n#define __CRYP_FORCE_RESET  __HAL_RCC_CRYP_FORCE_RESET\r\n#define __CRYP_RELEASE_RESET  __HAL_RCC_CRYP_RELEASE_RESET\r\n#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE\r\n#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE\r\n#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET\r\n#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET\r\n#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET\r\n#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET\r\n#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET\r\n#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET\r\n#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET\r\n#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET\r\n#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET\r\n#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET\r\n#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET\r\n#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET\r\n#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET\r\n#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET\r\n#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE\r\n#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE\r\n#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET\r\n#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET\r\n#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE\r\n#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE\r\n#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE\r\n#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE\r\n#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET\r\n#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET\r\n#define __CAN_CLK_DISABLE         __HAL_RCC_CAN1_CLK_DISABLE\r\n#define __CAN_CLK_ENABLE          __HAL_RCC_CAN1_CLK_ENABLE\r\n#define __CAN_FORCE_RESET         __HAL_RCC_CAN1_FORCE_RESET\r\n#define __CAN_RELEASE_RESET       __HAL_RCC_CAN1_RELEASE_RESET\r\n#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE\r\n#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE\r\n#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET\r\n#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET\r\n#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE\r\n#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE\r\n#define __COMP_CLK_DISABLE        __HAL_RCC_COMP_CLK_DISABLE\r\n#define __COMP_CLK_ENABLE         __HAL_RCC_COMP_CLK_ENABLE\r\n#define __COMP_FORCE_RESET        __HAL_RCC_COMP_FORCE_RESET\r\n#define __COMP_RELEASE_RESET      __HAL_RCC_COMP_RELEASE_RESET\r\n#define __COMP_CLK_SLEEP_ENABLE   __HAL_RCC_COMP_CLK_SLEEP_ENABLE\r\n#define __COMP_CLK_SLEEP_DISABLE  __HAL_RCC_COMP_CLK_SLEEP_DISABLE\r\n#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET\r\n#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET\r\n#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE\r\n#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE\r\n#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE\r\n#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE\r\n#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET\r\n#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET\r\n#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE\r\n#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE\r\n#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET\r\n#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET\r\n#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE\r\n#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE\r\n#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE\r\n#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE\r\n#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET\r\n#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET\r\n#define __DBGMCU_CLK_ENABLE     __HAL_RCC_DBGMCU_CLK_ENABLE\r\n#define __DBGMCU_CLK_DISABLE     __HAL_RCC_DBGMCU_CLK_DISABLE\r\n#define __DBGMCU_FORCE_RESET    __HAL_RCC_DBGMCU_FORCE_RESET\r\n#define __DBGMCU_RELEASE_RESET  __HAL_RCC_DBGMCU_RELEASE_RESET\r\n#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE\r\n#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE\r\n#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE\r\n#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE\r\n#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET\r\n#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET\r\n#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE\r\n#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE\r\n#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE\r\n#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE\r\n#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET\r\n#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET\r\n#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE\r\n#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE\r\n#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE\r\n#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE\r\n#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET\r\n#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET\r\n#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE\r\n#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE\r\n#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET\r\n#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET\r\n#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE\r\n#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE\r\n#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE\r\n#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE\r\n#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE\r\n#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE\r\n#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE\r\n#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE\r\n#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE\r\n#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE\r\n#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET\r\n#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET\r\n#define __FLITF_CLK_DISABLE       __HAL_RCC_FLITF_CLK_DISABLE\r\n#define __FLITF_CLK_ENABLE        __HAL_RCC_FLITF_CLK_ENABLE\r\n#define __FLITF_FORCE_RESET       __HAL_RCC_FLITF_FORCE_RESET\r\n#define __FLITF_RELEASE_RESET     __HAL_RCC_FLITF_RELEASE_RESET\r\n#define __FLITF_CLK_SLEEP_ENABLE  __HAL_RCC_FLITF_CLK_SLEEP_ENABLE\r\n#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE\r\n#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE\r\n#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE\r\n#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE\r\n#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE\r\n#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET\r\n#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET\r\n#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE\r\n#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE\r\n#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE\r\n#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE\r\n#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE\r\n#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE\r\n#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET\r\n#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET\r\n#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE\r\n#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE\r\n#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE\r\n#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE\r\n#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET\r\n#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET\r\n#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE\r\n#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE\r\n#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE\r\n#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE\r\n#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET\r\n#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET\r\n#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE\r\n#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE\r\n#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE\r\n#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE\r\n#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET\r\n#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET\r\n#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE\r\n#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE\r\n#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE\r\n#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE\r\n#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET\r\n#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET\r\n#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE\r\n#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE\r\n#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE\r\n#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE\r\n#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET\r\n#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET\r\n#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE\r\n#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE\r\n#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE\r\n#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE\r\n#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET\r\n#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET\r\n#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE\r\n#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE\r\n#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE\r\n#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE\r\n#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET\r\n#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET\r\n#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE\r\n#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE\r\n#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE\r\n#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE\r\n#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET\r\n#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET\r\n#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE\r\n#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE\r\n#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE\r\n#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE\r\n#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET\r\n#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET\r\n#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE\r\n#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE\r\n#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE\r\n#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE\r\n#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET\r\n#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET\r\n#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE\r\n#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE\r\n#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE\r\n#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE\r\n#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET\r\n#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET\r\n#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE\r\n#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE\r\n#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE\r\n#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE\r\n#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET\r\n#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET\r\n#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE\r\n#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE\r\n#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE\r\n#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE\r\n#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET\r\n#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET\r\n#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE\r\n#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE\r\n#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE\r\n#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE\r\n#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET\r\n#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET\r\n#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE\r\n#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE\r\n#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE\r\n#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE\r\n#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET\r\n#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET\r\n#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE\r\n#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE\r\n#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE\r\n#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE\r\n#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET\r\n#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET\r\n#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE\r\n#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE\r\n#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE\r\n#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE\r\n#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET\r\n#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET\r\n#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE\r\n#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE\r\n#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE\r\n#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE\r\n#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET\r\n#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET\r\n#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE\r\n#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE\r\n#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE\r\n#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE\r\n#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET\r\n#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET\r\n#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE\r\n#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE\r\n#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE\r\n#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE\r\n#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET\r\n#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET\r\n#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE\r\n#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE\r\n#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE\r\n#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE\r\n#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET\r\n#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET\r\n#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE\r\n#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE\r\n#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE\r\n#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE\r\n#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE\r\n#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE\r\n#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET\r\n#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET\r\n#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE\r\n#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE\r\n#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE\r\n#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE\r\n#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET\r\n#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET\r\n#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE\r\n#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE\r\n#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE\r\n#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE\r\n#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET\r\n#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET\r\n#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE\r\n#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE\r\n#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE\r\n#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE\r\n#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET\r\n#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET\r\n#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE\r\n#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE\r\n#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE\r\n#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE\r\n#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE\r\n#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE\r\n#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE\r\n#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE\r\n#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE\r\n#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE\r\n#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET\r\n#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET\r\n#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE\r\n#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE\r\n#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE\r\n#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE\r\n#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET\r\n#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET\r\n#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE\r\n#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE\r\n#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE\r\n#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE\r\n#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET\r\n#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET\r\n#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE\r\n#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE\r\n#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET\r\n#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET\r\n#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE\r\n#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE\r\n#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET\r\n#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET\r\n#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE\r\n#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE\r\n#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET\r\n#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET\r\n#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE\r\n#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE\r\n#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET\r\n#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET\r\n#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE\r\n#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE\r\n#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET\r\n#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET\r\n#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE\r\n#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE\r\n#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE\r\n#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE\r\n#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET\r\n#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET\r\n#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE\r\n#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE\r\n#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE\r\n#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE\r\n#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET\r\n#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET\r\n#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE\r\n#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE\r\n#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE\r\n#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE\r\n#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET\r\n#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET\r\n#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE\r\n#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE\r\n#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE\r\n#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE\r\n#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET\r\n#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET\r\n#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE\r\n#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE\r\n#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE\r\n#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE\r\n#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET\r\n#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET\r\n#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE\r\n#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE\r\n#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE\r\n#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE\r\n#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET\r\n#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET\r\n#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE\r\n#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE\r\n#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE\r\n#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE\r\n#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET\r\n#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET\r\n#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE\r\n#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE\r\n#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE\r\n#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE\r\n#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET\r\n#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET\r\n#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE\r\n#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE\r\n#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE\r\n#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE\r\n#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET\r\n#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET\r\n#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE\r\n#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE\r\n#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE\r\n#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE\r\n#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET\r\n#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET\r\n#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE\r\n#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE\r\n#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET\r\n#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET\r\n#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE\r\n#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE\r\n#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE\r\n#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE\r\n#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET\r\n#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET\r\n#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE\r\n#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE\r\n#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE\r\n#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE\r\n#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET\r\n#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET\r\n#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE\r\n#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE\r\n#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE\r\n#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE\r\n#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET\r\n#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET\r\n#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE\r\n#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE\r\n#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE\r\n#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE\r\n#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET\r\n#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET\r\n#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE\r\n#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE\r\n#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE\r\n#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE\r\n#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET\r\n#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET\r\n#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE\r\n#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE\r\n#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE\r\n#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE\r\n#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET\r\n#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET\r\n#define __USART4_CLK_DISABLE        __HAL_RCC_USART4_CLK_DISABLE\r\n#define __USART4_CLK_ENABLE         __HAL_RCC_USART4_CLK_ENABLE\r\n#define __USART4_CLK_SLEEP_ENABLE   __HAL_RCC_USART4_CLK_SLEEP_ENABLE\r\n#define __USART4_CLK_SLEEP_DISABLE  __HAL_RCC_USART4_CLK_SLEEP_DISABLE \r\n#define __USART4_FORCE_RESET        __HAL_RCC_USART4_FORCE_RESET\r\n#define __USART4_RELEASE_RESET      __HAL_RCC_USART4_RELEASE_RESET\r\n#define __USART5_CLK_DISABLE        __HAL_RCC_USART5_CLK_DISABLE\r\n#define __USART5_CLK_ENABLE         __HAL_RCC_USART5_CLK_ENABLE\r\n#define __USART5_CLK_SLEEP_ENABLE   __HAL_RCC_USART5_CLK_SLEEP_ENABLE\r\n#define __USART5_CLK_SLEEP_DISABLE  __HAL_RCC_USART5_CLK_SLEEP_DISABLE \r\n#define __USART5_FORCE_RESET        __HAL_RCC_USART5_FORCE_RESET\r\n#define __USART5_RELEASE_RESET      __HAL_RCC_USART5_RELEASE_RESET\r\n#define __USART7_CLK_DISABLE        __HAL_RCC_USART7_CLK_DISABLE\r\n#define __USART7_CLK_ENABLE         __HAL_RCC_USART7_CLK_ENABLE\r\n#define __USART7_FORCE_RESET        __HAL_RCC_USART7_FORCE_RESET\r\n#define __USART7_RELEASE_RESET      __HAL_RCC_USART7_RELEASE_RESET\r\n#define __USART8_CLK_DISABLE        __HAL_RCC_USART8_CLK_DISABLE\r\n#define __USART8_CLK_ENABLE         __HAL_RCC_USART8_CLK_ENABLE\r\n#define __USART8_FORCE_RESET        __HAL_RCC_USART8_FORCE_RESET\r\n#define __USART8_RELEASE_RESET      __HAL_RCC_USART8_RELEASE_RESET\r\n#define __USB_CLK_DISABLE         __HAL_RCC_USB_CLK_DISABLE\r\n#define __USB_CLK_ENABLE          __HAL_RCC_USB_CLK_ENABLE\r\n#define __USB_FORCE_RESET         __HAL_RCC_USB_FORCE_RESET\r\n#define __USB_CLK_SLEEP_ENABLE    __HAL_RCC_USB_CLK_SLEEP_ENABLE\r\n#define __USB_CLK_SLEEP_DISABLE   __HAL_RCC_USB_CLK_SLEEP_DISABLE\r\n#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE\r\n#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE\r\n#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET\r\n#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE\r\n#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE\r\n#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE\r\n#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE\r\n#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET\r\n#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET\r\n#define __TIM21_CLK_ENABLE   __HAL_RCC_TIM21_CLK_ENABLE\r\n#define __TIM21_CLK_DISABLE   __HAL_RCC_TIM21_CLK_DISABLE\r\n#define __TIM21_FORCE_RESET   __HAL_RCC_TIM21_FORCE_RESET\r\n#define __TIM21_RELEASE_RESET  __HAL_RCC_TIM21_RELEASE_RESET\r\n#define __TIM21_CLK_SLEEP_ENABLE   __HAL_RCC_TIM21_CLK_SLEEP_ENABLE\r\n#define __TIM21_CLK_SLEEP_DISABLE   __HAL_RCC_TIM21_CLK_SLEEP_DISABLE\r\n#define __TIM22_CLK_ENABLE   __HAL_RCC_TIM22_CLK_ENABLE\r\n#define __TIM22_CLK_DISABLE   __HAL_RCC_TIM22_CLK_DISABLE\r\n#define __TIM22_FORCE_RESET   __HAL_RCC_TIM22_FORCE_RESET\r\n#define __TIM22_RELEASE_RESET  __HAL_RCC_TIM22_RELEASE_RESET\r\n#define __TIM22_CLK_SLEEP_ENABLE   __HAL_RCC_TIM22_CLK_SLEEP_ENABLE\r\n#define __TIM22_CLK_SLEEP_DISABLE   __HAL_RCC_TIM22_CLK_SLEEP_DISABLE\r\n#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE\r\n#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE\r\n#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE\r\n#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE\r\n#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET\r\n#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET\r\n#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE\r\n#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE\r\n\r\n#define __USB_OTG_FS_FORCE_RESET  __HAL_RCC_USB_OTG_FS_FORCE_RESET\r\n#define __USB_OTG_FS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET\r\n#define __USB_OTG_FS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE\r\n#define __USB_OTG_FS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE\r\n#define __USB_OTG_HS_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_DISABLE\r\n#define __USB_OTG_HS_CLK_ENABLE          __HAL_RCC_USB_OTG_HS_CLK_ENABLE\r\n#define __USB_OTG_HS_ULPI_CLK_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE\r\n#define __USB_OTG_HS_ULPI_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE  \r\n#define __TIM9_CLK_SLEEP_ENABLE          __HAL_RCC_TIM9_CLK_SLEEP_ENABLE\r\n#define __TIM9_CLK_SLEEP_DISABLE  __HAL_RCC_TIM9_CLK_SLEEP_DISABLE  \r\n#define __TIM10_CLK_SLEEP_ENABLE  __HAL_RCC_TIM10_CLK_SLEEP_ENABLE\r\n#define __TIM10_CLK_SLEEP_DISABLE  __HAL_RCC_TIM10_CLK_SLEEP_DISABLE  \r\n#define __TIM11_CLK_SLEEP_ENABLE  __HAL_RCC_TIM11_CLK_SLEEP_ENABLE\r\n#define __TIM11_CLK_SLEEP_DISABLE  __HAL_RCC_TIM11_CLK_SLEEP_DISABLE  \r\n#define __ETHMACPTP_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE\r\n#define __ETHMACPTP_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE\r\n#define __ETHMACPTP_CLK_ENABLE          __HAL_RCC_ETHMACPTP_CLK_ENABLE\r\n#define __ETHMACPTP_CLK_DISABLE          __HAL_RCC_ETHMACPTP_CLK_DISABLE  \r\n#define __HASH_CLK_ENABLE          __HAL_RCC_HASH_CLK_ENABLE\r\n#define __HASH_FORCE_RESET          __HAL_RCC_HASH_FORCE_RESET\r\n#define __HASH_RELEASE_RESET          __HAL_RCC_HASH_RELEASE_RESET\r\n#define __HASH_CLK_SLEEP_ENABLE          __HAL_RCC_HASH_CLK_SLEEP_ENABLE\r\n#define __HASH_CLK_SLEEP_DISABLE  __HAL_RCC_HASH_CLK_SLEEP_DISABLE\r\n#define __HASH_CLK_DISABLE            __HAL_RCC_HASH_CLK_DISABLE  \r\n#define __SPI5_CLK_ENABLE          __HAL_RCC_SPI5_CLK_ENABLE\r\n#define __SPI5_CLK_DISABLE              __HAL_RCC_SPI5_CLK_DISABLE\r\n#define __SPI5_FORCE_RESET          __HAL_RCC_SPI5_FORCE_RESET\r\n#define __SPI5_RELEASE_RESET          __HAL_RCC_SPI5_RELEASE_RESET\r\n#define __SPI5_CLK_SLEEP_ENABLE          __HAL_RCC_SPI5_CLK_SLEEP_ENABLE\r\n#define __SPI5_CLK_SLEEP_DISABLE  __HAL_RCC_SPI5_CLK_SLEEP_DISABLE  \r\n#define __SPI6_CLK_ENABLE          __HAL_RCC_SPI6_CLK_ENABLE\r\n#define __SPI6_CLK_DISABLE          __HAL_RCC_SPI6_CLK_DISABLE\r\n#define __SPI6_FORCE_RESET          __HAL_RCC_SPI6_FORCE_RESET\r\n#define __SPI6_RELEASE_RESET         __HAL_RCC_SPI6_RELEASE_RESET\r\n#define __SPI6_CLK_SLEEP_ENABLE          __HAL_RCC_SPI6_CLK_SLEEP_ENABLE\r\n#define __SPI6_CLK_SLEEP_DISABLE  __HAL_RCC_SPI6_CLK_SLEEP_DISABLE  \r\n#define __LTDC_CLK_ENABLE          __HAL_RCC_LTDC_CLK_ENABLE\r\n#define __LTDC_CLK_DISABLE          __HAL_RCC_LTDC_CLK_DISABLE\r\n#define __LTDC_FORCE_RESET          __HAL_RCC_LTDC_FORCE_RESET\r\n#define __LTDC_RELEASE_RESET          __HAL_RCC_LTDC_RELEASE_RESET\r\n#define __LTDC_CLK_SLEEP_ENABLE          __HAL_RCC_LTDC_CLK_SLEEP_ENABLE  \r\n#define __ETHMAC_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE\r\n#define __ETHMAC_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE  \r\n#define __ETHMACTX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE\r\n#define __ETHMACTX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE  \r\n#define __ETHMACRX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE\r\n#define __ETHMACRX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE  \r\n#define __TIM12_CLK_SLEEP_ENABLE  __HAL_RCC_TIM12_CLK_SLEEP_ENABLE\r\n#define __TIM12_CLK_SLEEP_DISABLE  __HAL_RCC_TIM12_CLK_SLEEP_DISABLE  \r\n#define __TIM13_CLK_SLEEP_ENABLE  __HAL_RCC_TIM13_CLK_SLEEP_ENABLE\r\n#define __TIM13_CLK_SLEEP_DISABLE  __HAL_RCC_TIM13_CLK_SLEEP_DISABLE  \r\n#define __TIM14_CLK_SLEEP_ENABLE  __HAL_RCC_TIM14_CLK_SLEEP_ENABLE\r\n#define __TIM14_CLK_SLEEP_DISABLE  __HAL_RCC_TIM14_CLK_SLEEP_DISABLE  \r\n#define __BKPSRAM_CLK_ENABLE          __HAL_RCC_BKPSRAM_CLK_ENABLE\r\n#define __BKPSRAM_CLK_DISABLE          __HAL_RCC_BKPSRAM_CLK_DISABLE\r\n#define __BKPSRAM_CLK_SLEEP_ENABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE\r\n#define __BKPSRAM_CLK_SLEEP_DISABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE  \r\n#define __CCMDATARAMEN_CLK_ENABLE  __HAL_RCC_CCMDATARAMEN_CLK_ENABLE\r\n#define __CCMDATARAMEN_CLK_DISABLE  __HAL_RCC_CCMDATARAMEN_CLK_DISABLE  \r\n#define __USART6_CLK_ENABLE          __HAL_RCC_USART6_CLK_ENABLE\r\n#define __USART6_CLK_DISABLE          __HAL_RCC_USART6_CLK_DISABLE\r\n#define __USART6_FORCE_RESET        __HAL_RCC_USART6_FORCE_RESET\r\n#define __USART6_RELEASE_RESET        __HAL_RCC_USART6_RELEASE_RESET\r\n#define __USART6_CLK_SLEEP_ENABLE  __HAL_RCC_USART6_CLK_SLEEP_ENABLE\r\n#define __USART6_CLK_SLEEP_DISABLE  __HAL_RCC_USART6_CLK_SLEEP_DISABLE  \r\n#define __SPI4_CLK_ENABLE          __HAL_RCC_SPI4_CLK_ENABLE\r\n#define __SPI4_CLK_DISABLE          __HAL_RCC_SPI4_CLK_DISABLE\r\n#define __SPI4_FORCE_RESET          __HAL_RCC_SPI4_FORCE_RESET\r\n#define __SPI4_RELEASE_RESET        __HAL_RCC_SPI4_RELEASE_RESET\r\n#define __SPI4_CLK_SLEEP_ENABLE   __HAL_RCC_SPI4_CLK_SLEEP_ENABLE\r\n#define __SPI4_CLK_SLEEP_DISABLE  __HAL_RCC_SPI4_CLK_SLEEP_DISABLE  \r\n#define __GPIOI_CLK_ENABLE          __HAL_RCC_GPIOI_CLK_ENABLE\r\n#define __GPIOI_CLK_DISABLE          __HAL_RCC_GPIOI_CLK_DISABLE\r\n#define __GPIOI_FORCE_RESET          __HAL_RCC_GPIOI_FORCE_RESET\r\n#define __GPIOI_RELEASE_RESET          __HAL_RCC_GPIOI_RELEASE_RESET\r\n#define __GPIOI_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE\r\n#define __GPIOI_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE  \r\n#define __GPIOJ_CLK_ENABLE          __HAL_RCC_GPIOJ_CLK_ENABLE\r\n#define __GPIOJ_CLK_DISABLE          __HAL_RCC_GPIOJ_CLK_DISABLE\r\n#define __GPIOJ_FORCE_RESET         __HAL_RCC_GPIOJ_FORCE_RESET\r\n#define __GPIOJ_RELEASE_RESET          __HAL_RCC_GPIOJ_RELEASE_RESET\r\n#define __GPIOJ_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE\r\n#define __GPIOJ_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE  \r\n#define __GPIOK_CLK_ENABLE          __HAL_RCC_GPIOK_CLK_ENABLE\r\n#define __GPIOK_CLK_DISABLE          __HAL_RCC_GPIOK_CLK_DISABLE\r\n#define __GPIOK_RELEASE_RESET          __HAL_RCC_GPIOK_RELEASE_RESET\r\n#define __GPIOK_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE\r\n#define __GPIOK_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE  \r\n#define __ETH_CLK_ENABLE          __HAL_RCC_ETH_CLK_ENABLE\r\n#define __ETH_CLK_DISABLE          __HAL_RCC_ETH_CLK_DISABLE  \r\n#define __DCMI_CLK_ENABLE          __HAL_RCC_DCMI_CLK_ENABLE\r\n#define __DCMI_CLK_DISABLE          __HAL_RCC_DCMI_CLK_DISABLE\r\n#define __DCMI_FORCE_RESET          __HAL_RCC_DCMI_FORCE_RESET\r\n#define __DCMI_RELEASE_RESET          __HAL_RCC_DCMI_RELEASE_RESET\r\n#define __DCMI_CLK_SLEEP_ENABLE   __HAL_RCC_DCMI_CLK_SLEEP_ENABLE\r\n#define __DCMI_CLK_SLEEP_DISABLE  __HAL_RCC_DCMI_CLK_SLEEP_DISABLE  \r\n#define __UART7_CLK_ENABLE          __HAL_RCC_UART7_CLK_ENABLE\r\n#define __UART7_CLK_DISABLE          __HAL_RCC_UART7_CLK_DISABLE\r\n#define __UART7_RELEASE_RESET       __HAL_RCC_UART7_RELEASE_RESET\r\n#define __UART7_FORCE_RESET       __HAL_RCC_UART7_FORCE_RESET\r\n#define __UART7_CLK_SLEEP_ENABLE  __HAL_RCC_UART7_CLK_SLEEP_ENABLE\r\n#define __UART7_CLK_SLEEP_DISABLE  __HAL_RCC_UART7_CLK_SLEEP_DISABLE  \r\n#define __UART8_CLK_ENABLE          __HAL_RCC_UART8_CLK_ENABLE\r\n#define __UART8_CLK_DISABLE          __HAL_RCC_UART8_CLK_DISABLE\r\n#define __UART8_FORCE_RESET          __HAL_RCC_UART8_FORCE_RESET\r\n#define __UART8_RELEASE_RESET          __HAL_RCC_UART8_RELEASE_RESET\r\n#define __UART8_CLK_SLEEP_ENABLE  __HAL_RCC_UART8_CLK_SLEEP_ENABLE\r\n#define __UART8_CLK_SLEEP_DISABLE  __HAL_RCC_UART8_CLK_SLEEP_DISABLE  \r\n#define __OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE\r\n#define __OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE\r\n#define __OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET\r\n#define __OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET  \r\n#define __OTGHSULPI_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE\r\n#define __OTGHSULPI_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE\r\n#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE\r\n#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE\r\n#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED\r\n#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED\r\n#define __HAL_RCC_OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET\r\n#define __HAL_RCC_OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET  \r\n#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE      __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE\r\n#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE     __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE \r\n#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED  __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED\r\n#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED   \r\n#define __CRYP_FORCE_RESET             __HAL_RCC_CRYP_FORCE_RESET  \r\n#define __SRAM3_CLK_SLEEP_ENABLE       __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE  \r\n#define __CAN2_CLK_SLEEP_ENABLE        __HAL_RCC_CAN2_CLK_SLEEP_ENABLE\r\n#define __CAN2_CLK_SLEEP_DISABLE       __HAL_RCC_CAN2_CLK_SLEEP_DISABLE  \r\n#define __DAC_CLK_SLEEP_ENABLE         __HAL_RCC_DAC_CLK_SLEEP_ENABLE\r\n#define __DAC_CLK_SLEEP_DISABLE        __HAL_RCC_DAC_CLK_SLEEP_DISABLE  \r\n#define __ADC2_CLK_SLEEP_ENABLE        __HAL_RCC_ADC2_CLK_SLEEP_ENABLE\r\n#define __ADC2_CLK_SLEEP_DISABLE       __HAL_RCC_ADC2_CLK_SLEEP_DISABLE  \r\n#define __ADC3_CLK_SLEEP_ENABLE        __HAL_RCC_ADC3_CLK_SLEEP_ENABLE\r\n#define __ADC3_CLK_SLEEP_DISABLE       __HAL_RCC_ADC3_CLK_SLEEP_DISABLE  \r\n#define __FSMC_FORCE_RESET             __HAL_RCC_FSMC_FORCE_RESET\r\n#define __FSMC_RELEASE_RESET           __HAL_RCC_FSMC_RELEASE_RESET\r\n#define __FSMC_CLK_SLEEP_ENABLE        __HAL_RCC_FSMC_CLK_SLEEP_ENABLE\r\n#define __FSMC_CLK_SLEEP_DISABLE       __HAL_RCC_FSMC_CLK_SLEEP_DISABLE  \r\n#define __SDIO_FORCE_RESET             __HAL_RCC_SDIO_FORCE_RESET\r\n#define __SDIO_RELEASE_RESET           __HAL_RCC_SDIO_RELEASE_RESET\r\n#define __SDIO_CLK_SLEEP_DISABLE       __HAL_RCC_SDIO_CLK_SLEEP_DISABLE\r\n#define __SDIO_CLK_SLEEP_ENABLE        __HAL_RCC_SDIO_CLK_SLEEP_ENABLE  \r\n#define __DMA2D_CLK_ENABLE             __HAL_RCC_DMA2D_CLK_ENABLE\r\n#define __DMA2D_CLK_DISABLE            __HAL_RCC_DMA2D_CLK_DISABLE\r\n#define __DMA2D_FORCE_RESET            __HAL_RCC_DMA2D_FORCE_RESET\r\n#define __DMA2D_RELEASE_RESET          __HAL_RCC_DMA2D_RELEASE_RESET\r\n#define __DMA2D_CLK_SLEEP_ENABLE       __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE\r\n#define __DMA2D_CLK_SLEEP_DISABLE      __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE\r\n\r\n/* alias define maintained for legacy */\r\n#define __HAL_RCC_OTGFS_FORCE_RESET    __HAL_RCC_USB_OTG_FS_FORCE_RESET\r\n#define __HAL_RCC_OTGFS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET\r\n\r\n#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE\r\n#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE\r\n#define __ADC34_CLK_ENABLE          __HAL_RCC_ADC34_CLK_ENABLE\r\n#define __ADC34_CLK_DISABLE         __HAL_RCC_ADC34_CLK_DISABLE\r\n#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE\r\n#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE\r\n#define __DAC2_CLK_ENABLE           __HAL_RCC_DAC2_CLK_ENABLE\r\n#define __DAC2_CLK_DISABLE          __HAL_RCC_DAC2_CLK_DISABLE\r\n#define __TIM18_CLK_ENABLE          __HAL_RCC_TIM18_CLK_ENABLE\r\n#define __TIM18_CLK_DISABLE         __HAL_RCC_TIM18_CLK_DISABLE\r\n#define __TIM19_CLK_ENABLE          __HAL_RCC_TIM19_CLK_ENABLE\r\n#define __TIM19_CLK_DISABLE         __HAL_RCC_TIM19_CLK_DISABLE\r\n#define __TIM20_CLK_ENABLE          __HAL_RCC_TIM20_CLK_ENABLE\r\n#define __TIM20_CLK_DISABLE         __HAL_RCC_TIM20_CLK_DISABLE\r\n#define __HRTIM1_CLK_ENABLE         __HAL_RCC_HRTIM1_CLK_ENABLE\r\n#define __HRTIM1_CLK_DISABLE        __HAL_RCC_HRTIM1_CLK_DISABLE\r\n#define __SDADC1_CLK_ENABLE         __HAL_RCC_SDADC1_CLK_ENABLE\r\n#define __SDADC2_CLK_ENABLE         __HAL_RCC_SDADC2_CLK_ENABLE\r\n#define __SDADC3_CLK_ENABLE         __HAL_RCC_SDADC3_CLK_ENABLE\r\n#define __SDADC1_CLK_DISABLE        __HAL_RCC_SDADC1_CLK_DISABLE\r\n#define __SDADC2_CLK_DISABLE        __HAL_RCC_SDADC2_CLK_DISABLE\r\n#define __SDADC3_CLK_DISABLE        __HAL_RCC_SDADC3_CLK_DISABLE\r\n\r\n#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET\r\n#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET\r\n#define __ADC34_FORCE_RESET         __HAL_RCC_ADC34_FORCE_RESET\r\n#define __ADC34_RELEASE_RESET       __HAL_RCC_ADC34_RELEASE_RESET\r\n#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET\r\n#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET\r\n#define __DAC2_FORCE_RESET          __HAL_RCC_DAC2_FORCE_RESET\r\n#define __DAC2_RELEASE_RESET        __HAL_RCC_DAC2_RELEASE_RESET\r\n#define __TIM18_FORCE_RESET         __HAL_RCC_TIM18_FORCE_RESET\r\n#define __TIM18_RELEASE_RESET       __HAL_RCC_TIM18_RELEASE_RESET\r\n#define __TIM19_FORCE_RESET         __HAL_RCC_TIM19_FORCE_RESET\r\n#define __TIM19_RELEASE_RESET       __HAL_RCC_TIM19_RELEASE_RESET\r\n#define __TIM20_FORCE_RESET         __HAL_RCC_TIM20_FORCE_RESET\r\n#define __TIM20_RELEASE_RESET       __HAL_RCC_TIM20_RELEASE_RESET\r\n#define __HRTIM1_FORCE_RESET        __HAL_RCC_HRTIM1_FORCE_RESET\r\n#define __HRTIM1_RELEASE_RESET      __HAL_RCC_HRTIM1_RELEASE_RESET\r\n#define __SDADC1_FORCE_RESET        __HAL_RCC_SDADC1_FORCE_RESET\r\n#define __SDADC2_FORCE_RESET        __HAL_RCC_SDADC2_FORCE_RESET\r\n#define __SDADC3_FORCE_RESET        __HAL_RCC_SDADC3_FORCE_RESET\r\n#define __SDADC1_RELEASE_RESET      __HAL_RCC_SDADC1_RELEASE_RESET\r\n#define __SDADC2_RELEASE_RESET      __HAL_RCC_SDADC2_RELEASE_RESET\r\n#define __SDADC3_RELEASE_RESET      __HAL_RCC_SDADC3_RELEASE_RESET\r\n\r\n#define __ADC1_IS_CLK_ENABLED       __HAL_RCC_ADC1_IS_CLK_ENABLED\r\n#define __ADC1_IS_CLK_DISABLED      __HAL_RCC_ADC1_IS_CLK_DISABLED\r\n#define __ADC12_IS_CLK_ENABLED      __HAL_RCC_ADC12_IS_CLK_ENABLED\r\n#define __ADC12_IS_CLK_DISABLED     __HAL_RCC_ADC12_IS_CLK_DISABLED\r\n#define __ADC34_IS_CLK_ENABLED      __HAL_RCC_ADC34_IS_CLK_ENABLED\r\n#define __ADC34_IS_CLK_DISABLED     __HAL_RCC_ADC34_IS_CLK_DISABLED\r\n#define __CEC_IS_CLK_ENABLED        __HAL_RCC_CEC_IS_CLK_ENABLED\r\n#define __CEC_IS_CLK_DISABLED       __HAL_RCC_CEC_IS_CLK_DISABLED\r\n#define __CRC_IS_CLK_ENABLED        __HAL_RCC_CRC_IS_CLK_ENABLED\r\n#define __CRC_IS_CLK_DISABLED       __HAL_RCC_CRC_IS_CLK_DISABLED\r\n#define __DAC1_IS_CLK_ENABLED       __HAL_RCC_DAC1_IS_CLK_ENABLED\r\n#define __DAC1_IS_CLK_DISABLED      __HAL_RCC_DAC1_IS_CLK_DISABLED\r\n#define __DAC2_IS_CLK_ENABLED       __HAL_RCC_DAC2_IS_CLK_ENABLED\r\n#define __DAC2_IS_CLK_DISABLED      __HAL_RCC_DAC2_IS_CLK_DISABLED\r\n#define __DMA1_IS_CLK_ENABLED       __HAL_RCC_DMA1_IS_CLK_ENABLED\r\n#define __DMA1_IS_CLK_DISABLED      __HAL_RCC_DMA1_IS_CLK_DISABLED\r\n#define __DMA2_IS_CLK_ENABLED       __HAL_RCC_DMA2_IS_CLK_ENABLED\r\n#define __DMA2_IS_CLK_DISABLED      __HAL_RCC_DMA2_IS_CLK_DISABLED\r\n#define __FLITF_IS_CLK_ENABLED      __HAL_RCC_FLITF_IS_CLK_ENABLED\r\n#define __FLITF_IS_CLK_DISABLED     __HAL_RCC_FLITF_IS_CLK_DISABLED\r\n#define __FMC_IS_CLK_ENABLED        __HAL_RCC_FMC_IS_CLK_ENABLED\r\n#define __FMC_IS_CLK_DISABLED       __HAL_RCC_FMC_IS_CLK_DISABLED\r\n#define __GPIOA_IS_CLK_ENABLED      __HAL_RCC_GPIOA_IS_CLK_ENABLED\r\n#define __GPIOA_IS_CLK_DISABLED     __HAL_RCC_GPIOA_IS_CLK_DISABLED\r\n#define __GPIOB_IS_CLK_ENABLED      __HAL_RCC_GPIOB_IS_CLK_ENABLED\r\n#define __GPIOB_IS_CLK_DISABLED     __HAL_RCC_GPIOB_IS_CLK_DISABLED\r\n#define __GPIOC_IS_CLK_ENABLED      __HAL_RCC_GPIOC_IS_CLK_ENABLED\r\n#define __GPIOC_IS_CLK_DISABLED     __HAL_RCC_GPIOC_IS_CLK_DISABLED\r\n#define __GPIOD_IS_CLK_ENABLED      __HAL_RCC_GPIOD_IS_CLK_ENABLED\r\n#define __GPIOD_IS_CLK_DISABLED     __HAL_RCC_GPIOD_IS_CLK_DISABLED\r\n#define __GPIOE_IS_CLK_ENABLED      __HAL_RCC_GPIOE_IS_CLK_ENABLED\r\n#define __GPIOE_IS_CLK_DISABLED     __HAL_RCC_GPIOE_IS_CLK_DISABLED\r\n#define __GPIOF_IS_CLK_ENABLED      __HAL_RCC_GPIOF_IS_CLK_ENABLED\r\n#define __GPIOF_IS_CLK_DISABLED     __HAL_RCC_GPIOF_IS_CLK_DISABLED\r\n#define __GPIOG_IS_CLK_ENABLED      __HAL_RCC_GPIOG_IS_CLK_ENABLED\r\n#define __GPIOG_IS_CLK_DISABLED     __HAL_RCC_GPIOG_IS_CLK_DISABLED\r\n#define __GPIOH_IS_CLK_ENABLED      __HAL_RCC_GPIOH_IS_CLK_ENABLED\r\n#define __GPIOH_IS_CLK_DISABLED     __HAL_RCC_GPIOH_IS_CLK_DISABLED\r\n#define __HRTIM1_IS_CLK_ENABLED     __HAL_RCC_HRTIM1_IS_CLK_ENABLED\r\n#define __HRTIM1_IS_CLK_DISABLED    __HAL_RCC_HRTIM1_IS_CLK_DISABLED\r\n#define __I2C1_IS_CLK_ENABLED       __HAL_RCC_I2C1_IS_CLK_ENABLED\r\n#define __I2C1_IS_CLK_DISABLED      __HAL_RCC_I2C1_IS_CLK_DISABLED\r\n#define __I2C2_IS_CLK_ENABLED       __HAL_RCC_I2C2_IS_CLK_ENABLED\r\n#define __I2C2_IS_CLK_DISABLED      __HAL_RCC_I2C2_IS_CLK_DISABLED\r\n#define __I2C3_IS_CLK_ENABLED       __HAL_RCC_I2C3_IS_CLK_ENABLED\r\n#define __I2C3_IS_CLK_DISABLED      __HAL_RCC_I2C3_IS_CLK_DISABLED\r\n#define __PWR_IS_CLK_ENABLED        __HAL_RCC_PWR_IS_CLK_ENABLED\r\n#define __PWR_IS_CLK_DISABLED       __HAL_RCC_PWR_IS_CLK_DISABLED\r\n#define __SYSCFG_IS_CLK_ENABLED     __HAL_RCC_SYSCFG_IS_CLK_ENABLED\r\n#define __SYSCFG_IS_CLK_DISABLED    __HAL_RCC_SYSCFG_IS_CLK_DISABLED\r\n#define __SPI1_IS_CLK_ENABLED       __HAL_RCC_SPI1_IS_CLK_ENABLED\r\n#define __SPI1_IS_CLK_DISABLED      __HAL_RCC_SPI1_IS_CLK_DISABLED\r\n#define __SPI2_IS_CLK_ENABLED       __HAL_RCC_SPI2_IS_CLK_ENABLED\r\n#define __SPI2_IS_CLK_DISABLED      __HAL_RCC_SPI2_IS_CLK_DISABLED\r\n#define __SPI3_IS_CLK_ENABLED       __HAL_RCC_SPI3_IS_CLK_ENABLED\r\n#define __SPI3_IS_CLK_DISABLED      __HAL_RCC_SPI3_IS_CLK_DISABLED\r\n#define __SPI4_IS_CLK_ENABLED       __HAL_RCC_SPI4_IS_CLK_ENABLED\r\n#define __SPI4_IS_CLK_DISABLED      __HAL_RCC_SPI4_IS_CLK_DISABLED\r\n#define __SDADC1_IS_CLK_ENABLED     __HAL_RCC_SDADC1_IS_CLK_ENABLED\r\n#define __SDADC1_IS_CLK_DISABLED    __HAL_RCC_SDADC1_IS_CLK_DISABLED\r\n#define __SDADC2_IS_CLK_ENABLED     __HAL_RCC_SDADC2_IS_CLK_ENABLED\r\n#define __SDADC2_IS_CLK_DISABLED    __HAL_RCC_SDADC2_IS_CLK_DISABLED\r\n#define __SDADC3_IS_CLK_ENABLED     __HAL_RCC_SDADC3_IS_CLK_ENABLED\r\n#define __SDADC3_IS_CLK_DISABLED    __HAL_RCC_SDADC3_IS_CLK_DISABLED\r\n#define __SRAM_IS_CLK_ENABLED       __HAL_RCC_SRAM_IS_CLK_ENABLED\r\n#define __SRAM_IS_CLK_DISABLED      __HAL_RCC_SRAM_IS_CLK_DISABLED\r\n#define __TIM1_IS_CLK_ENABLED       __HAL_RCC_TIM1_IS_CLK_ENABLED\r\n#define __TIM1_IS_CLK_DISABLED      __HAL_RCC_TIM1_IS_CLK_DISABLED\r\n#define __TIM2_IS_CLK_ENABLED       __HAL_RCC_TIM2_IS_CLK_ENABLED\r\n#define __TIM2_IS_CLK_DISABLED      __HAL_RCC_TIM2_IS_CLK_DISABLED\r\n#define __TIM3_IS_CLK_ENABLED       __HAL_RCC_TIM3_IS_CLK_ENABLED\r\n#define __TIM3_IS_CLK_DISABLED      __HAL_RCC_TIM3_IS_CLK_DISABLED\r\n#define __TIM4_IS_CLK_ENABLED       __HAL_RCC_TIM4_IS_CLK_ENABLED\r\n#define __TIM4_IS_CLK_DISABLED      __HAL_RCC_TIM4_IS_CLK_DISABLED\r\n#define __TIM5_IS_CLK_ENABLED       __HAL_RCC_TIM5_IS_CLK_ENABLED\r\n#define __TIM5_IS_CLK_DISABLED      __HAL_RCC_TIM5_IS_CLK_DISABLED\r\n#define __TIM6_IS_CLK_ENABLED       __HAL_RCC_TIM6_IS_CLK_ENABLED\r\n#define __TIM6_IS_CLK_DISABLED      __HAL_RCC_TIM6_IS_CLK_DISABLED\r\n#define __TIM7_IS_CLK_ENABLED       __HAL_RCC_TIM7_IS_CLK_ENABLED\r\n#define __TIM7_IS_CLK_DISABLED      __HAL_RCC_TIM7_IS_CLK_DISABLED\r\n#define __TIM8_IS_CLK_ENABLED       __HAL_RCC_TIM8_IS_CLK_ENABLED\r\n#define __TIM8_IS_CLK_DISABLED      __HAL_RCC_TIM8_IS_CLK_DISABLED\r\n#define __TIM12_IS_CLK_ENABLED      __HAL_RCC_TIM12_IS_CLK_ENABLED\r\n#define __TIM12_IS_CLK_DISABLED     __HAL_RCC_TIM12_IS_CLK_DISABLED\r\n#define __TIM13_IS_CLK_ENABLED      __HAL_RCC_TIM13_IS_CLK_ENABLED\r\n#define __TIM13_IS_CLK_DISABLED     __HAL_RCC_TIM13_IS_CLK_DISABLED\r\n#define __TIM14_IS_CLK_ENABLED      __HAL_RCC_TIM14_IS_CLK_ENABLED\r\n#define __TIM14_IS_CLK_DISABLED     __HAL_RCC_TIM14_IS_CLK_DISABLED\r\n#define __TIM15_IS_CLK_ENABLED      __HAL_RCC_TIM15_IS_CLK_ENABLED\r\n#define __TIM15_IS_CLK_DISABLED     __HAL_RCC_TIM15_IS_CLK_DISABLED\r\n#define __TIM16_IS_CLK_ENABLED      __HAL_RCC_TIM16_IS_CLK_ENABLED\r\n#define __TIM16_IS_CLK_DISABLED     __HAL_RCC_TIM16_IS_CLK_DISABLED\r\n#define __TIM17_IS_CLK_ENABLED      __HAL_RCC_TIM17_IS_CLK_ENABLED\r\n#define __TIM17_IS_CLK_DISABLED     __HAL_RCC_TIM17_IS_CLK_DISABLED\r\n#define __TIM18_IS_CLK_ENABLED      __HAL_RCC_TIM18_IS_CLK_ENABLED\r\n#define __TIM18_IS_CLK_DISABLED     __HAL_RCC_TIM18_IS_CLK_DISABLED\r\n#define __TIM19_IS_CLK_ENABLED      __HAL_RCC_TIM19_IS_CLK_ENABLED\r\n#define __TIM19_IS_CLK_DISABLED     __HAL_RCC_TIM19_IS_CLK_DISABLED\r\n#define __TIM20_IS_CLK_ENABLED      __HAL_RCC_TIM20_IS_CLK_ENABLED\r\n#define __TIM20_IS_CLK_DISABLED     __HAL_RCC_TIM20_IS_CLK_DISABLED\r\n#define __TSC_IS_CLK_ENABLED        __HAL_RCC_TSC_IS_CLK_ENABLED\r\n#define __TSC_IS_CLK_DISABLED       __HAL_RCC_TSC_IS_CLK_DISABLED\r\n#define __UART4_IS_CLK_ENABLED      __HAL_RCC_UART4_IS_CLK_ENABLED\r\n#define __UART4_IS_CLK_DISABLED     __HAL_RCC_UART4_IS_CLK_DISABLED\r\n#define __UART5_IS_CLK_ENABLED      __HAL_RCC_UART5_IS_CLK_ENABLED\r\n#define __UART5_IS_CLK_DISABLED     __HAL_RCC_UART5_IS_CLK_DISABLED\r\n#define __USART1_IS_CLK_ENABLED     __HAL_RCC_USART1_IS_CLK_ENABLED\r\n#define __USART1_IS_CLK_DISABLED    __HAL_RCC_USART1_IS_CLK_DISABLED\r\n#define __USART2_IS_CLK_ENABLED     __HAL_RCC_USART2_IS_CLK_ENABLED\r\n#define __USART2_IS_CLK_DISABLED    __HAL_RCC_USART2_IS_CLK_DISABLED\r\n#define __USART3_IS_CLK_ENABLED     __HAL_RCC_USART3_IS_CLK_ENABLED\r\n#define __USART3_IS_CLK_DISABLED    __HAL_RCC_USART3_IS_CLK_DISABLED\r\n#define __USB_IS_CLK_ENABLED        __HAL_RCC_USB_IS_CLK_ENABLED\r\n#define __USB_IS_CLK_DISABLED       __HAL_RCC_USB_IS_CLK_DISABLED\r\n#define __WWDG_IS_CLK_ENABLED       __HAL_RCC_WWDG_IS_CLK_ENABLED\r\n#define __WWDG_IS_CLK_DISABLED      __HAL_RCC_WWDG_IS_CLK_DISABLED\r\n\r\n#if defined(STM32F4)\r\n#define __HAL_RCC_SDMMC1_FORCE_RESET       __HAL_RCC_SDIO_FORCE_RESET\r\n#define __HAL_RCC_SDMMC1_RELEASE_RESET     __HAL_RCC_SDIO_RELEASE_RESET\r\n#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE  __HAL_RCC_SDIO_CLK_SLEEP_ENABLE\r\n#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE\r\n#define __HAL_RCC_SDMMC1_CLK_ENABLE        __HAL_RCC_SDIO_CLK_ENABLE\r\n#define __HAL_RCC_SDMMC1_CLK_DISABLE       __HAL_RCC_SDIO_CLK_DISABLE\r\n#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED    __HAL_RCC_SDIO_IS_CLK_ENABLED\r\n#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED   __HAL_RCC_SDIO_IS_CLK_DISABLED\r\n#define Sdmmc1ClockSelection               SdioClockSelection\r\n#define RCC_PERIPHCLK_SDMMC1               RCC_PERIPHCLK_SDIO\r\n#define RCC_SDMMC1CLKSOURCE_CLK48          RCC_SDIOCLKSOURCE_CK48\r\n#define RCC_SDMMC1CLKSOURCE_SYSCLK         RCC_SDIOCLKSOURCE_SYSCLK\r\n#define __HAL_RCC_SDMMC1_CONFIG            __HAL_RCC_SDIO_CONFIG\r\n#define __HAL_RCC_GET_SDMMC1_SOURCE        __HAL_RCC_GET_SDIO_SOURCE\r\n#endif\r\n\r\n#if defined(STM32F7) || defined(STM32L4)\r\n#define __HAL_RCC_SDIO_FORCE_RESET         __HAL_RCC_SDMMC1_FORCE_RESET\r\n#define __HAL_RCC_SDIO_RELEASE_RESET       __HAL_RCC_SDMMC1_RELEASE_RESET\r\n#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE    __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE\r\n#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE   __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE\r\n#define __HAL_RCC_SDIO_CLK_ENABLE          __HAL_RCC_SDMMC1_CLK_ENABLE\r\n#define __HAL_RCC_SDIO_CLK_DISABLE         __HAL_RCC_SDMMC1_CLK_DISABLE\r\n#define __HAL_RCC_SDIO_IS_CLK_ENABLED      __HAL_RCC_SDMMC1_IS_CLK_ENABLED\r\n#define __HAL_RCC_SDIO_IS_CLK_DISABLED     __HAL_RCC_SDMMC1_IS_CLK_DISABLED\r\n#define SdioClockSelection                 Sdmmc1ClockSelection\r\n#define RCC_PERIPHCLK_SDIO                 RCC_PERIPHCLK_SDMMC1\r\n#define __HAL_RCC_SDIO_CONFIG              __HAL_RCC_SDMMC1_CONFIG\r\n#define __HAL_RCC_GET_SDIO_SOURCE          __HAL_RCC_GET_SDMMC1_SOURCE\t\r\n#endif\r\n\r\n#if defined(STM32F7)\r\n#define RCC_SDIOCLKSOURCE_CLK48             RCC_SDMMC1CLKSOURCE_CLK48\r\n#define RCC_SDIOCLKSOURCE_SYSCLK           RCC_SDMMC1CLKSOURCE_SYSCLK\r\n#endif\r\n\r\n#define __HAL_RCC_I2SCLK            __HAL_RCC_I2S_CONFIG\r\n#define __HAL_RCC_I2SCLK_CONFIG     __HAL_RCC_I2S_CONFIG\r\n\r\n#define __RCC_PLLSRC                RCC_GET_PLL_OSCSOURCE\r\n\r\n#define IS_RCC_MSIRANGE             IS_RCC_MSI_CLOCK_RANGE\r\n#define IS_RCC_RTCCLK_SOURCE        IS_RCC_RTCCLKSOURCE\r\n#define IS_RCC_SYSCLK_DIV           IS_RCC_HCLK\r\n#define IS_RCC_HCLK_DIV             IS_RCC_PCLK\r\n#define IS_RCC_PERIPHCLK            IS_RCC_PERIPHCLOCK\r\n\r\n#define RCC_IT_HSI14                RCC_IT_HSI14RDY\r\n\r\n#if defined(STM32L0)\r\n#define RCC_IT_LSECSS              RCC_IT_CSSLSE \r\n#define RCC_IT_CSS                 RCC_IT_CSSHSE\r\n#endif\r\n\r\n#define IS_RCC_MCOSOURCE            IS_RCC_MCO1SOURCE\r\n#define __HAL_RCC_MCO_CONFIG        __HAL_RCC_MCO1_CONFIG\r\n#define RCC_MCO_NODIV               RCC_MCODIV_1\r\n#define RCC_MCO_DIV1                RCC_MCODIV_1\r\n#define RCC_MCO_DIV2                RCC_MCODIV_2\r\n#define RCC_MCO_DIV4                RCC_MCODIV_4\r\n#define RCC_MCO_DIV8                RCC_MCODIV_8\r\n#define RCC_MCO_DIV16               RCC_MCODIV_16\r\n#define RCC_MCO_DIV32               RCC_MCODIV_32\r\n#define RCC_MCO_DIV64               RCC_MCODIV_64\r\n#define RCC_MCO_DIV128              RCC_MCODIV_128\r\n#define RCC_MCOSOURCE_NONE          RCC_MCO1SOURCE_NOCLOCK\r\n#define RCC_MCOSOURCE_LSI           RCC_MCO1SOURCE_LSI\r\n#define RCC_MCOSOURCE_LSE           RCC_MCO1SOURCE_LSE\r\n#define RCC_MCOSOURCE_SYSCLK        RCC_MCO1SOURCE_SYSCLK\r\n#define RCC_MCOSOURCE_HSI           RCC_MCO1SOURCE_HSI\r\n#define RCC_MCOSOURCE_HSI14         RCC_MCO1SOURCE_HSI14\r\n#define RCC_MCOSOURCE_HSI48         RCC_MCO1SOURCE_HSI48\r\n#define RCC_MCOSOURCE_HSE           RCC_MCO1SOURCE_HSE\r\n#define RCC_MCOSOURCE_PLLCLK_DIV1   RCC_MCO1SOURCE_PLLCLK\r\n#define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK\r\n#define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2\r\n\r\n#define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK\r\n\r\n#define RCC_USBCLK_PLLSAI1          RCC_USBCLKSOURCE_PLLSAI1\r\n#define RCC_USBCLK_PLL              RCC_USBCLKSOURCE_PLL\r\n#define RCC_USBCLK_MSI              RCC_USBCLKSOURCE_MSI\r\n#define RCC_USBCLKSOURCE_PLLCLK     RCC_USBCLKSOURCE_PLL\r\n#define RCC_USBPLLCLK_DIV1          RCC_USBCLKSOURCE_PLL\r\n#define RCC_USBPLLCLK_DIV1_5        RCC_USBCLKSOURCE_PLL_DIV1_5\r\n#define RCC_USBPLLCLK_DIV2          RCC_USBCLKSOURCE_PLL_DIV2\r\n#define RCC_USBPLLCLK_DIV3          RCC_USBCLKSOURCE_PLL_DIV3\r\n\r\n#define HSION_BitNumber        RCC_HSION_BIT_NUMBER\r\n#define HSION_BITNUMBER        RCC_HSION_BIT_NUMBER\r\n#define HSEON_BitNumber        RCC_HSEON_BIT_NUMBER\r\n#define HSEON_BITNUMBER        RCC_HSEON_BIT_NUMBER\r\n#define MSION_BITNUMBER        RCC_MSION_BIT_NUMBER\r\n#define CSSON_BitNumber        RCC_CSSON_BIT_NUMBER\r\n#define CSSON_BITNUMBER        RCC_CSSON_BIT_NUMBER\r\n#define PLLON_BitNumber        RCC_PLLON_BIT_NUMBER\r\n#define PLLON_BITNUMBER        RCC_PLLON_BIT_NUMBER\r\n#define PLLI2SON_BitNumber     RCC_PLLI2SON_BIT_NUMBER\r\n#define I2SSRC_BitNumber       RCC_I2SSRC_BIT_NUMBER\r\n#define RTCEN_BitNumber        RCC_RTCEN_BIT_NUMBER\r\n#define RTCEN_BITNUMBER        RCC_RTCEN_BIT_NUMBER\r\n#define BDRST_BitNumber        RCC_BDRST_BIT_NUMBER\r\n#define BDRST_BITNUMBER        RCC_BDRST_BIT_NUMBER\r\n#define RTCRST_BITNUMBER       RCC_RTCRST_BIT_NUMBER\r\n#define LSION_BitNumber        RCC_LSION_BIT_NUMBER\r\n#define LSION_BITNUMBER        RCC_LSION_BIT_NUMBER\r\n#define LSEON_BitNumber        RCC_LSEON_BIT_NUMBER\r\n#define LSEON_BITNUMBER        RCC_LSEON_BIT_NUMBER\r\n#define LSEBYP_BITNUMBER       RCC_LSEBYP_BIT_NUMBER\r\n#define PLLSAION_BitNumber     RCC_PLLSAION_BIT_NUMBER\r\n#define TIMPRE_BitNumber       RCC_TIMPRE_BIT_NUMBER\r\n#define RMVF_BitNumber         RCC_RMVF_BIT_NUMBER\r\n#define RMVF_BITNUMBER         RCC_RMVF_BIT_NUMBER\r\n#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER\r\n#define CR_BYTE2_ADDRESS       RCC_CR_BYTE2_ADDRESS\r\n#define CIR_BYTE1_ADDRESS      RCC_CIR_BYTE1_ADDRESS\r\n#define CIR_BYTE2_ADDRESS      RCC_CIR_BYTE2_ADDRESS\r\n#define BDCR_BYTE0_ADDRESS     RCC_BDCR_BYTE0_ADDRESS\r\n#define DBP_TIMEOUT_VALUE      RCC_DBP_TIMEOUT_VALUE\r\n#define LSE_TIMEOUT_VALUE      RCC_LSE_TIMEOUT_VALUE\r\n\r\n#define CR_HSION_BB            RCC_CR_HSION_BB\r\n#define CR_CSSON_BB            RCC_CR_CSSON_BB\r\n#define CR_PLLON_BB            RCC_CR_PLLON_BB\r\n#define CR_PLLI2SON_BB         RCC_CR_PLLI2SON_BB\r\n#define CR_MSION_BB            RCC_CR_MSION_BB\r\n#define CSR_LSION_BB           RCC_CSR_LSION_BB\r\n#define CSR_LSEON_BB           RCC_CSR_LSEON_BB\r\n#define CSR_LSEBYP_BB          RCC_CSR_LSEBYP_BB\r\n#define CSR_RTCEN_BB           RCC_CSR_RTCEN_BB\r\n#define CSR_RTCRST_BB          RCC_CSR_RTCRST_BB\r\n#define CFGR_I2SSRC_BB         RCC_CFGR_I2SSRC_BB\r\n#define BDCR_RTCEN_BB          RCC_BDCR_RTCEN_BB\r\n#define BDCR_BDRST_BB          RCC_BDCR_BDRST_BB\r\n#define CR_HSEON_BB            RCC_CR_HSEON_BB\r\n#define CSR_RMVF_BB            RCC_CSR_RMVF_BB\r\n#define CR_PLLSAION_BB         RCC_CR_PLLSAION_BB\r\n#define DCKCFGR_TIMPRE_BB      RCC_DCKCFGR_TIMPRE_BB\r\n\r\n#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER     __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE\r\n#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER    __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE\r\n#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB        __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE\r\n#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB       __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE\r\n#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE         __HAL_RCC_CRS_RELOADVALUE_CALCULATE\r\n\r\n#define __HAL_RCC_GET_IT_SOURCE                     __HAL_RCC_GET_IT\r\n\r\n#define RCC_CRS_SYNCWARM       RCC_CRS_SYNCWARN\r\n#define RCC_CRS_TRIMOV         RCC_CRS_TRIMOVF\r\n\r\n#define RCC_PERIPHCLK_CK48               RCC_PERIPHCLK_CLK48\r\n#define RCC_CK48CLKSOURCE_PLLQ           RCC_CLK48CLKSOURCE_PLLQ\r\n#define RCC_CK48CLKSOURCE_PLLSAIP        RCC_CLK48CLKSOURCE_PLLSAIP\r\n#define RCC_CK48CLKSOURCE_PLLI2SQ        RCC_CLK48CLKSOURCE_PLLI2SQ\r\n#define IS_RCC_CK48CLKSOURCE             IS_RCC_CLK48CLKSOURCE\r\n#define RCC_SDIOCLKSOURCE_CK48           RCC_SDIOCLKSOURCE_CLK48\r\n\r\n#define __HAL_RCC_DFSDM_CLK_ENABLE             __HAL_RCC_DFSDM1_CLK_ENABLE\r\n#define __HAL_RCC_DFSDM_CLK_DISABLE            __HAL_RCC_DFSDM1_CLK_DISABLE\r\n#define __HAL_RCC_DFSDM_IS_CLK_ENABLED         __HAL_RCC_DFSDM1_IS_CLK_ENABLED\r\n#define __HAL_RCC_DFSDM_IS_CLK_DISABLED        __HAL_RCC_DFSDM1_IS_CLK_DISABLED\r\n#define __HAL_RCC_DFSDM_FORCE_RESET            __HAL_RCC_DFSDM1_FORCE_RESET\r\n#define __HAL_RCC_DFSDM_RELEASE_RESET          __HAL_RCC_DFSDM1_RELEASE_RESET\r\n#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE       __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE\r\n#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE      __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE\r\n#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED   __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED\r\n#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED  __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED\r\n#define DfsdmClockSelection         Dfsdm1ClockSelection\r\n#define RCC_PERIPHCLK_DFSDM         RCC_PERIPHCLK_DFSDM1\r\n#define RCC_DFSDMCLKSOURCE_PCLK     RCC_DFSDM1CLKSOURCE_PCLK\r\n#define RCC_DFSDMCLKSOURCE_SYSCLK   RCC_DFSDM1CLKSOURCE_SYSCLK\r\n#define __HAL_RCC_DFSDM_CONFIG      __HAL_RCC_DFSDM1_CONFIG\r\n#define __HAL_RCC_GET_DFSDM_SOURCE  __HAL_RCC_GET_DFSDM1_SOURCE\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define  HAL_RNG_ReadyCallback(__HANDLE__)  HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)                                       \r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n  \r\n#define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG\r\n#define __HAL_RTC_DISABLE_IT                      __HAL_RTC_EXTI_DISABLE_IT\r\n#define __HAL_RTC_ENABLE_IT                       __HAL_RTC_EXTI_ENABLE_IT\r\n\r\n#if defined (STM32F1)\r\n#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()\r\n\r\n#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_ENABLE_IT()\r\n\r\n#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_DISABLE_IT()\r\n\r\n#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT)    __HAL_RTC_ALARM_EXTI_GET_FLAG()\r\n\r\n#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()\r\n#else\r\n#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \\\r\n                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \\\r\n                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))\r\n#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__)   (((__EXTI_LINE__)  == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \\\r\n                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \\\r\n                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))\r\n#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \\\r\n                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \\\r\n                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))\r\n#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__)    (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \\\r\n                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \\\r\n                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))\r\n#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__)   (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \\\r\n                                                      (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() :  \\\r\n                                                          __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))\r\n#endif   /* STM32F1 */\r\n\r\n#define IS_ALARM                                  IS_RTC_ALARM\r\n#define IS_ALARM_MASK                             IS_RTC_ALARM_MASK\r\n#define IS_TAMPER                                 IS_RTC_TAMPER\r\n#define IS_TAMPER_ERASE_MODE                      IS_RTC_TAMPER_ERASE_MODE\r\n#define IS_TAMPER_FILTER                          IS_RTC_TAMPER_FILTER \r\n#define IS_TAMPER_INTERRUPT                       IS_RTC_TAMPER_INTERRUPT\r\n#define IS_TAMPER_MASKFLAG_STATE                  IS_RTC_TAMPER_MASKFLAG_STATE\r\n#define IS_TAMPER_PRECHARGE_DURATION              IS_RTC_TAMPER_PRECHARGE_DURATION\r\n#define IS_TAMPER_PULLUP_STATE                    IS_RTC_TAMPER_PULLUP_STATE\r\n#define IS_TAMPER_SAMPLING_FREQ                   IS_RTC_TAMPER_SAMPLING_FREQ\r\n#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION     IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION\r\n#define IS_TAMPER_TRIGGER                         IS_RTC_TAMPER_TRIGGER\r\n#define IS_WAKEUP_CLOCK                           IS_RTC_WAKEUP_CLOCK\r\n#define IS_WAKEUP_COUNTER                         IS_RTC_WAKEUP_COUNTER\r\n\r\n#define __RTC_WRITEPROTECTION_ENABLE  __HAL_RTC_WRITEPROTECTION_ENABLE\r\n#define __RTC_WRITEPROTECTION_DISABLE  __HAL_RTC_WRITEPROTECTION_DISABLE\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define SD_OCR_CID_CSD_OVERWRIETE   SD_OCR_CID_CSD_OVERWRITE\r\n#define SD_CMD_SD_APP_STAUS         SD_CMD_SD_APP_STATUS\r\n\r\n#if defined(STM32F4)\r\n#define  SD_SDMMC_DISABLED          SD_SDIO_DISABLED\r\n#define  SD_SDMMC_FUNCTION_BUSY     SD_SDIO_FUNCTION_BUSY     \r\n#define  SD_SDMMC_FUNCTION_FAILED   SD_SDIO_FUNCTION_FAILED   \r\n#define  SD_SDMMC_UNKNOWN_FUNCTION  SD_SDIO_UNKNOWN_FUNCTION  \r\n#define  SD_CMD_SDMMC_SEN_OP_COND   SD_CMD_SDIO_SEN_OP_COND   \r\n#define  SD_CMD_SDMMC_RW_DIRECT     SD_CMD_SDIO_RW_DIRECT     \r\n#define  SD_CMD_SDMMC_RW_EXTENDED   SD_CMD_SDIO_RW_EXTENDED   \r\n#define  __HAL_SD_SDMMC_ENABLE      __HAL_SD_SDIO_ENABLE      \r\n#define  __HAL_SD_SDMMC_DISABLE     __HAL_SD_SDIO_DISABLE     \r\n#define  __HAL_SD_SDMMC_DMA_ENABLE  __HAL_SD_SDIO_DMA_ENABLE  \r\n#define  __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL  \r\n#define  __HAL_SD_SDMMC_ENABLE_IT   __HAL_SD_SDIO_ENABLE_IT   \r\n#define  __HAL_SD_SDMMC_DISABLE_IT  __HAL_SD_SDIO_DISABLE_IT  \r\n#define  __HAL_SD_SDMMC_GET_FLAG    __HAL_SD_SDIO_GET_FLAG    \r\n#define  __HAL_SD_SDMMC_CLEAR_FLAG  __HAL_SD_SDIO_CLEAR_FLAG  \r\n#define  __HAL_SD_SDMMC_GET_IT      __HAL_SD_SDIO_GET_IT      \r\n#define  __HAL_SD_SDMMC_CLEAR_IT    __HAL_SD_SDIO_CLEAR_IT    \r\n#define  SDMMC_STATIC_FLAGS         SDIO_STATIC_FLAGS\t       \r\n#define  SDMMC_CMD0TIMEOUT          SDIO_CMD0TIMEOUT\t       \r\n#define  SD_SDMMC_SEND_IF_COND      SD_SDIO_SEND_IF_COND\r\n/* alias CMSIS */\r\n#define  SDMMC1_IRQn                SDIO_IRQn\r\n#define  SDMMC1_IRQHandler          SDIO_IRQHandler\r\n#endif\r\n\r\n#if defined(STM32F7) || defined(STM32L4)\r\n#define  SD_SDIO_DISABLED           SD_SDMMC_DISABLED\r\n#define  SD_SDIO_FUNCTION_BUSY      SD_SDMMC_FUNCTION_BUSY    \r\n#define  SD_SDIO_FUNCTION_FAILED    SD_SDMMC_FUNCTION_FAILED  \r\n#define  SD_SDIO_UNKNOWN_FUNCTION   SD_SDMMC_UNKNOWN_FUNCTION\r\n#define  SD_CMD_SDIO_SEN_OP_COND    SD_CMD_SDMMC_SEN_OP_COND\r\n#define  SD_CMD_SDIO_RW_DIRECT      SD_CMD_SDMMC_RW_DIRECT\r\n#define  SD_CMD_SDIO_RW_EXTENDED    SD_CMD_SDMMC_RW_EXTENDED\r\n#define  __HAL_SD_SDIO_ENABLE       __HAL_SD_SDMMC_ENABLE\r\n#define  __HAL_SD_SDIO_DISABLE      __HAL_SD_SDMMC_DISABLE\r\n#define  __HAL_SD_SDIO_DMA_ENABLE   __HAL_SD_SDMMC_DMA_ENABLE\r\n#define  __HAL_SD_SDIO_DMA_DISABL   __HAL_SD_SDMMC_DMA_DISABLE\r\n#define  __HAL_SD_SDIO_ENABLE_IT    __HAL_SD_SDMMC_ENABLE_IT\r\n#define  __HAL_SD_SDIO_DISABLE_IT   __HAL_SD_SDMMC_DISABLE_IT\r\n#define  __HAL_SD_SDIO_GET_FLAG     __HAL_SD_SDMMC_GET_FLAG\r\n#define  __HAL_SD_SDIO_CLEAR_FLAG   __HAL_SD_SDMMC_CLEAR_FLAG\r\n#define  __HAL_SD_SDIO_GET_IT       __HAL_SD_SDMMC_GET_IT\r\n#define  __HAL_SD_SDIO_CLEAR_IT     __HAL_SD_SDMMC_CLEAR_IT\r\n#define  SDIO_STATIC_FLAGS\t        SDMMC_STATIC_FLAGS\r\n#define  SDIO_CMD0TIMEOUT\t          SDMMC_CMD0TIMEOUT\r\n#define  SD_SDIO_SEND_IF_COND\t      SD_SDMMC_SEND_IF_COND\r\n/* alias CMSIS for compatibilities */\r\n#define  SDIO_IRQn                  SDMMC1_IRQn\r\n#define  SDIO_IRQHandler            SDMMC1_IRQHandler\r\n#endif\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define __SMARTCARD_ENABLE_IT           __HAL_SMARTCARD_ENABLE_IT\r\n#define __SMARTCARD_DISABLE_IT          __HAL_SMARTCARD_DISABLE_IT\r\n#define __SMARTCARD_ENABLE              __HAL_SMARTCARD_ENABLE\r\n#define __SMARTCARD_DISABLE             __HAL_SMARTCARD_DISABLE\r\n#define __SMARTCARD_DMA_REQUEST_ENABLE  __HAL_SMARTCARD_DMA_REQUEST_ENABLE\r\n#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE\r\n\r\n#define __HAL_SMARTCARD_GETCLOCKSOURCE  SMARTCARD_GETCLOCKSOURCE\r\n#define __SMARTCARD_GETCLOCKSOURCE      SMARTCARD_GETCLOCKSOURCE\r\n\r\n#define IS_SMARTCARD_ONEBIT_SAMPLING    IS_SMARTCARD_ONE_BIT_SAMPLE                  \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define __HAL_SMBUS_RESET_CR1           SMBUS_RESET_CR1\r\n#define __HAL_SMBUS_RESET_CR2           SMBUS_RESET_CR2\r\n#define __HAL_SMBUS_GENERATE_START      SMBUS_GENERATE_START\r\n#define __HAL_SMBUS_GET_ADDR_MATCH      SMBUS_GET_ADDR_MATCH\r\n#define __HAL_SMBUS_GET_DIR             SMBUS_GET_DIR\r\n#define __HAL_SMBUS_GET_STOP_MODE       SMBUS_GET_STOP_MODE\r\n#define __HAL_SMBUS_GET_PEC_MODE        SMBUS_GET_PEC_MODE\r\n#define __HAL_SMBUS_GET_ALERT_ENABLED   SMBUS_GET_ALERT_ENABLED\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define __HAL_SPI_1LINE_TX              SPI_1LINE_TX\r\n#define __HAL_SPI_1LINE_RX              SPI_1LINE_RX\r\n#define __HAL_SPI_RESET_CRC             SPI_RESET_CRC\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define __HAL_UART_GETCLOCKSOURCE       UART_GETCLOCKSOURCE\r\n#define __HAL_UART_MASK_COMPUTATION     UART_MASK_COMPUTATION\r\n#define __UART_GETCLOCKSOURCE           UART_GETCLOCKSOURCE\r\n#define __UART_MASK_COMPUTATION         UART_MASK_COMPUTATION\r\n\r\n#define IS_UART_WAKEUPMETHODE           IS_UART_WAKEUPMETHOD\r\n\r\n#define IS_UART_ONEBIT_SAMPLE           IS_UART_ONE_BIT_SAMPLE                  \r\n#define IS_UART_ONEBIT_SAMPLING         IS_UART_ONE_BIT_SAMPLE                  \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n\r\n#define __USART_ENABLE_IT               __HAL_USART_ENABLE_IT\r\n#define __USART_DISABLE_IT              __HAL_USART_DISABLE_IT\r\n#define __USART_ENABLE                  __HAL_USART_ENABLE\r\n#define __USART_DISABLE                 __HAL_USART_DISABLE\r\n\r\n#define __HAL_USART_GETCLOCKSOURCE      USART_GETCLOCKSOURCE\r\n#define __USART_GETCLOCKSOURCE          USART_GETCLOCKSOURCE\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define USB_EXTI_LINE_WAKEUP                               USB_WAKEUP_EXTI_LINE\r\n\r\n#define USB_FS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE\r\n#define USB_FS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE\r\n#define USB_FS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE\r\n#define USB_FS_EXTI_LINE_WAKEUP                            USB_OTG_FS_WAKEUP_EXTI_LINE\r\n\r\n#define USB_HS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE\r\n#define USB_HS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE\r\n#define USB_HS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE\r\n#define USB_HS_EXTI_LINE_WAKEUP                            USB_OTG_HS_WAKEUP_EXTI_LINE\r\n\r\n#define __HAL_USB_EXTI_ENABLE_IT                           __HAL_USB_WAKEUP_EXTI_ENABLE_IT\r\n#define __HAL_USB_EXTI_DISABLE_IT                          __HAL_USB_WAKEUP_EXTI_DISABLE_IT\r\n#define __HAL_USB_EXTI_GET_FLAG                            __HAL_USB_WAKEUP_EXTI_GET_FLAG\r\n#define __HAL_USB_EXTI_CLEAR_FLAG                          __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG\r\n#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER             __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE\r\n#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER            __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE\r\n#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER           __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE\r\n\r\n#define __HAL_USB_FS_EXTI_ENABLE_IT                        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT\r\n#define __HAL_USB_FS_EXTI_DISABLE_IT                       __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT\r\n#define __HAL_USB_FS_EXTI_GET_FLAG                         __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG\r\n#define __HAL_USB_FS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG\r\n#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE\r\n#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE\r\n#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE\r\n#define __HAL_USB_FS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT\r\n\r\n#define __HAL_USB_HS_EXTI_ENABLE_IT                        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT\r\n#define __HAL_USB_HS_EXTI_DISABLE_IT                       __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT\r\n#define __HAL_USB_HS_EXTI_GET_FLAG                         __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG\r\n#define __HAL_USB_HS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG\r\n#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE\r\n#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE\r\n#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE\r\n#define __HAL_USB_HS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT\r\n\r\n#define HAL_PCD_ActiveRemoteWakeup                         HAL_PCD_ActivateRemoteWakeup\r\n#define HAL_PCD_DeActiveRemoteWakeup                       HAL_PCD_DeActivateRemoteWakeup\r\n\r\n#define HAL_PCD_SetTxFiFo                                  HAL_PCDEx_SetTxFiFo\r\n#define HAL_PCD_SetRxFiFo                                  HAL_PCDEx_SetRxFiFo\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define __HAL_TIM_SetICPrescalerValue   TIM_SET_ICPRESCALERVALUE\r\n#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE\r\n\r\n#define TIM_GET_ITSTATUS                __HAL_TIM_GET_IT_SOURCE\r\n#define TIM_GET_CLEAR_IT                __HAL_TIM_CLEAR_IT\r\n\r\n#define __HAL_TIM_GET_ITSTATUS          __HAL_TIM_GET_IT_SOURCE\r\n\r\n#define __HAL_TIM_DIRECTION_STATUS      __HAL_TIM_IS_TIM_COUNTING_DOWN\r\n#define __HAL_TIM_PRESCALER             __HAL_TIM_SET_PRESCALER\r\n#define __HAL_TIM_SetCounter            __HAL_TIM_SET_COUNTER\r\n#define __HAL_TIM_GetCounter            __HAL_TIM_GET_COUNTER\r\n#define __HAL_TIM_SetAutoreload         __HAL_TIM_SET_AUTORELOAD\r\n#define __HAL_TIM_GetAutoreload         __HAL_TIM_GET_AUTORELOAD\r\n#define __HAL_TIM_SetClockDivision      __HAL_TIM_SET_CLOCKDIVISION\r\n#define __HAL_TIM_GetClockDivision      __HAL_TIM_GET_CLOCKDIVISION\r\n#define __HAL_TIM_SetICPrescaler        __HAL_TIM_SET_ICPRESCALER\r\n#define __HAL_TIM_GetICPrescaler        __HAL_TIM_GET_ICPRESCALER\r\n#define __HAL_TIM_SetCompare            __HAL_TIM_SET_COMPARE\r\n#define __HAL_TIM_GetCompare            __HAL_TIM_GET_COMPARE\r\n\r\n#define TIM_BREAKINPUTSOURCE_DFSDM  TIM_BREAKINPUTSOURCE_DFSDM1\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n  \r\n#define __HAL_ETH_EXTI_ENABLE_IT                   __HAL_ETH_WAKEUP_EXTI_ENABLE_IT\r\n#define __HAL_ETH_EXTI_DISABLE_IT                  __HAL_ETH_WAKEUP_EXTI_DISABLE_IT\r\n#define __HAL_ETH_EXTI_GET_FLAG                    __HAL_ETH_WAKEUP_EXTI_GET_FLAG\r\n#define __HAL_ETH_EXTI_CLEAR_FLAG                  __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG\r\n#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER     __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER\r\n#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER    __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER\r\n#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER   __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER\r\n\r\n#define ETH_PROMISCIOUSMODE_ENABLE   ETH_PROMISCUOUS_MODE_ENABLE \r\n#define ETH_PROMISCIOUSMODE_DISABLE  ETH_PROMISCUOUS_MODE_DISABLE\r\n#define IS_ETH_PROMISCIOUS_MODE      IS_ETH_PROMISCUOUS_MODE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define __HAL_LTDC_LAYER LTDC_LAYER\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n#define SAI_OUTPUTDRIVE_DISABLED          SAI_OUTPUTDRIVE_DISABLE\r\n#define SAI_OUTPUTDRIVE_ENABLED           SAI_OUTPUTDRIVE_ENABLE\r\n#define SAI_MASTERDIVIDER_ENABLED         SAI_MASTERDIVIDER_ENABLE\r\n#define SAI_MASTERDIVIDER_DISABLED        SAI_MASTERDIVIDER_DISABLE\r\n#define SAI_STREOMODE                     SAI_STEREOMODE\r\n#define SAI_FIFOStatus_Empty              SAI_FIFOSTATUS_EMPTY\r\n#define SAI_FIFOStatus_Less1QuarterFull   SAI_FIFOSTATUS_LESS1QUARTERFULL\r\n#define SAI_FIFOStatus_1QuarterFull       SAI_FIFOSTATUS_1QUARTERFULL\r\n#define SAI_FIFOStatus_HalfFull           SAI_FIFOSTATUS_HALFFULL\r\n#define SAI_FIFOStatus_3QuartersFull      SAI_FIFOSTATUS_3QUARTERFULL\r\n#define SAI_FIFOStatus_Full               SAI_FIFOSTATUS_FULL\r\n#define IS_SAI_BLOCK_MONO_STREO_MODE      IS_SAI_BLOCK_MONO_STEREO_MODE\r\n#define SAI_SYNCHRONOUS_EXT               SAI_SYNCHRONOUS_EXT_SAI1\r\n#define SAI_SYNCEXT_IN_ENABLE             SAI_SYNCEXT_OUTBLOCKA_ENABLE\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* ___STM32_HAL_LEGACY */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   This file contains all the functions prototypes for the HAL \r\n  *          module driver.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_H\r\n#define __STM32F7xx_HAL_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_conf.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup HAL\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup SYSCFG_BootMode Boot Mode\r\n  * @{\r\n  */\r\n#define SYSCFG_MEM_BOOT_ADD0          ((uint32_t)0x00000000U)\r\n#define SYSCFG_MEM_BOOT_ADD1          SYSCFG_MEMRMP_MEM_BOOT\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n   \r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup HAL_Exported_Macros HAL Exported Macros\r\n  * @{\r\n  */\r\n  \r\n/** @brief  Freeze/Unfreeze Peripherals in Debug mode \r\n  */\r\n#define __HAL_DBGMCU_FREEZE_TIM2()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))\r\n#define __HAL_DBGMCU_FREEZE_TIM3()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))\r\n#define __HAL_DBGMCU_FREEZE_TIM4()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))\r\n#define __HAL_DBGMCU_FREEZE_TIM5()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))\r\n#define __HAL_DBGMCU_FREEZE_TIM6()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))\r\n#define __HAL_DBGMCU_FREEZE_TIM7()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))\r\n#define __HAL_DBGMCU_FREEZE_TIM12()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))\r\n#define __HAL_DBGMCU_FREEZE_TIM13()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))\r\n#define __HAL_DBGMCU_FREEZE_TIM14()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))\r\n#define __HAL_DBGMCU_FREEZE_LPTIM1()         (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_LPTIM1_STOP))\r\n#define __HAL_DBGMCU_FREEZE_RTC()            (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))\r\n#define __HAL_DBGMCU_FREEZE_WWDG()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))\r\n#define __HAL_DBGMCU_FREEZE_IWDG()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))\r\n#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))\r\n#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))\r\n#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))\r\n#define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT))\r\n#define __HAL_DBGMCU_FREEZE_CAN1()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))\r\n#define __HAL_DBGMCU_FREEZE_CAN2()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))\r\n#define __HAL_DBGMCU_FREEZE_TIM1()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))\r\n#define __HAL_DBGMCU_FREEZE_TIM8()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))\r\n#define __HAL_DBGMCU_FREEZE_TIM9()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))\r\n#define __HAL_DBGMCU_FREEZE_TIM10()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))\r\n#define __HAL_DBGMCU_FREEZE_TIM11()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))\r\n\r\n#define __HAL_DBGMCU_UNFREEZE_TIM2()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_TIM3()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_TIM4()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_TIM5()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_TIM6()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_TIM7()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_TIM12()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_TIM13()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_TIM14()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_LPTIM1()         (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_LPTIM1_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_RTC()            (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_WWDG()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_IWDG()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))\r\n#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))\r\n#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))\r\n#define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT))\r\n#define __HAL_DBGMCU_UNFREEZE_CAN1()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_CAN2()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_TIM1()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_TIM8()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_TIM9()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_TIM10()          (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))\r\n#define __HAL_DBGMCU_UNFREEZE_TIM11()          (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))\r\n\r\n\r\n/** @brief  FMC (NOR/RAM) mapped at 0x60000000 and SDRAM mapped at 0xC0000000\r\n  */\r\n#define __HAL_SYSCFG_REMAPMEMORY_FMC()          (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC))\r\n                                       \r\n\r\n/** @brief  FMC/SDRAM  mapped at 0x60000000 (NOR/RAM) mapped at 0xC0000000\r\n  */\r\n#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC);\\\r\n                                          SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_SWP_FMC_0);\\\r\n                                         }while(0);\r\n/**\r\n  * @brief  Return the memory boot mapping as configured by user.\r\n  * @retval The boot mode as configured by user. The returned value can be one\r\n  *         of the following values:\r\n  *           @arg @ref SYSCFG_MEM_BOOT_ADD0\r\n  *           @arg @ref SYSCFG_MEM_BOOT_ADD1\r\n  */\r\n#define __HAL_SYSCFG_GET_BOOT_MODE()           READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_BOOT)\r\n\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n/** @brief  SYSCFG Break Cortex-M7 Lockup lock.\r\n  *         Enable and lock the connection of Cortex-M7 LOCKUP (Hardfault) output to TIM1/8 Break input.\r\n  * @note   The selected configuration is locked and can be unlocked only by system reset.\r\n  */\r\n#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()     SET_BIT(SYSCFG->CBR, SYSCFG_CBR_CLL)\r\n\r\n/** @brief  SYSCFG Break PVD lock.\r\n  *         Enable and lock the PVD connection to Timer1/8 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR1 register.\r\n  * @note   The selected configuration is locked and can be unlocked only by system reset.\r\n  */\r\n#define __HAL_SYSCFG_BREAK_PVD_LOCK()        SET_BIT(SYSCFG->CBR, SYSCFG_CBR_PVDL)\r\n#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup HAL_Exported_Functions\r\n  * @{\r\n  */\r\n/** @addtogroup HAL_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n/* Initialization and de-initialization functions  ******************************/\r\nHAL_StatusTypeDef HAL_Init(void);\r\nHAL_StatusTypeDef HAL_DeInit(void);\r\nvoid HAL_MspInit(void);\r\nvoid HAL_MspDeInit(void);\r\nHAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);\r\n/**\r\n  * @}\r\n  */\r\n \r\n/** @addtogroup HAL_Exported_Functions_Group2\r\n  * @{\r\n  */ \r\n/* Peripheral Control functions  ************************************************/\r\nvoid HAL_IncTick(void);\r\nvoid HAL_Delay(__IO uint32_t Delay);\r\nuint32_t HAL_GetTick(void);\r\nvoid HAL_SuspendTick(void);\r\nvoid HAL_ResumeTick(void);\r\nuint32_t HAL_GetHalVersion(void);\r\nuint32_t HAL_GetREVID(void);\r\nuint32_t HAL_GetDEVID(void);\r\nvoid HAL_DBGMCU_EnableDBGSleepMode(void);\r\nvoid HAL_DBGMCU_DisableDBGSleepMode(void);\r\nvoid HAL_DBGMCU_EnableDBGStopMode(void);\r\nvoid HAL_DBGMCU_DisableDBGStopMode(void);\r\nvoid HAL_DBGMCU_EnableDBGStandbyMode(void);\r\nvoid HAL_DBGMCU_DisableDBGStandbyMode(void);\r\nvoid HAL_EnableCompensationCell(void);\r\nvoid HAL_DisableCompensationCell(void);\r\nvoid HAL_EnableFMCMemorySwapping(void);\r\nvoid HAL_DisableFMCMemorySwapping(void);\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\nvoid HAL_EnableMemorySwappingBank(void);\r\nvoid HAL_DisableMemorySwappingBank(void);\r\n#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */  \r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @defgroup HAL_Private_Variables HAL Private Variables\r\n  * @{\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup HAL_Private_Constants HAL Private Constants\r\n  * @{\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n/* Private macros ------------------------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_adc.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of ADC HAL extension module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_ADC_H\r\n#define __STM32F7xx_ADC_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup ADC\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup ADC_Exported_Types ADC Exported Types\r\n  * @{\r\n  */\r\n\r\n/** \r\n  * @brief  Structure definition of ADC and regular group initialization \r\n  * @note   Parameters of this structure are shared within 2 scopes:\r\n  *          - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.\r\n  *          - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.\r\n  * @note   The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.\r\n  *         ADC state can be either:\r\n  *          - For all parameters: ADC disabled\r\n  *          - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.\r\n  *          - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.\r\n  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed\r\n  *         without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly).\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t ClockPrescaler;        /*!< Select ADC clock prescaler. The clock is common for \r\n                                       all the ADCs.\r\n                                       This parameter can be a value of @ref ADC_ClockPrescaler */\r\n  uint32_t Resolution;            /*!< Configures the ADC resolution.\r\n                                       This parameter can be a value of @ref ADC_Resolution */\r\n  uint32_t DataAlign;             /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)\r\n                                       or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).\r\n                                       This parameter can be a value of @ref ADC_Data_Align */\r\n  uint32_t ScanConvMode;          /*!< Configures the sequencer of regular and injected groups.\r\n                                       This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.\r\n                                       If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).\r\n                                                    Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).\r\n                                       If enabled:  Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).\r\n                                                    Scan direction is upward: from rank1 to rank 'n'.\r\n                                       This parameter can be set to ENABLE or DISABLE */\r\n  uint32_t EOCSelection;          /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.\r\n                                       This parameter can be a value of @ref ADC_EOCSelection.\r\n                                       Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.\r\n                                             Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)\r\n                                             or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.\r\n                                       Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).\r\n                                             If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */\r\n  uint32_t ContinuousConvMode;    /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,\r\n                                       after the selected trigger occurred (software start or external trigger).\r\n                                       This parameter can be set to ENABLE or DISABLE. */\r\n  uint32_t NbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the regular group sequencer.\r\n                                       To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.\r\n                                       This parameter must be a number between Min_Data = 1 and Max_Data = 16. */\r\n  uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).\r\n                                       Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.\r\n                                       Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.\r\n                                       This parameter can be set to ENABLE or DISABLE. */\r\n  uint32_t NbrOfDiscConversion;   /*!< Specifies the number of discontinuous conversions in which the  main sequence of regular group (parameter NbrOfConversion) will be subdivided.\r\n                                       If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.\r\n                                       This parameter must be a number between Min_Data = 1 and Max_Data = 8. */\r\n  uint32_t ExternalTrigConv;      /*!< Selects the external event used to trigger the conversion start of regular group.\r\n                                       If set to ADC_SOFTWARE_START, external triggers are disabled.\r\n                                       If set to external trigger source, triggering is on event rising edge by default.\r\n                                       This parameter can be a value of @ref ADC_External_trigger_Source_Regular */\r\n  uint32_t ExternalTrigConvEdge;  /*!< Selects the external trigger edge of regular group.\r\n                                       If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.\r\n                                       This parameter can be a value of @ref ADC_External_trigger_edge_Regular */\r\n  uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)\r\n                                       or in Continuous mode (DMA transfer unlimited, whatever number of conversions).\r\n                                       Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.\r\n                                       Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).\r\n                                       This parameter can be set to ENABLE or DISABLE. */\r\n}ADC_InitTypeDef;\r\n\r\n\r\n\r\n/** \r\n  * @brief  Structure definition of ADC channel for regular group   \r\n  * @note   The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.\r\n  *         ADC can be either disabled or enabled without conversion on going on regular group.\r\n  */ \r\ntypedef struct \r\n{\r\n  uint32_t Channel;                /*!< Specifies the channel to configure into ADC regular group.\r\n                                        This parameter can be a value of @ref ADC_channels */\r\n  uint32_t Rank;                   /*!< Specifies the rank in the regular group sequencer.\r\n                                        This parameter must be a number between Min_Data = 1 and Max_Data = 16 */\r\n  uint32_t SamplingTime;           /*!< Sampling time value to be set for the selected channel.\r\n                                        Unit: ADC clock cycles\r\n                                        Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).\r\n                                        This parameter can be a value of @ref ADC_sampling_times\r\n                                        Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.\r\n                                                 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.\r\n                                        Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),\r\n                                              sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)\r\n                                              Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */\r\n  uint32_t Offset;                 /*!< Reserved for future use, can be set to 0 */\r\n}ADC_ChannelConfTypeDef;\r\n\r\n/** \r\n  * @brief ADC Configuration multi-mode structure definition  \r\n  */ \r\ntypedef struct\r\n{\r\n  uint32_t WatchdogMode;      /*!< Configures the ADC analog watchdog mode.\r\n                                   This parameter can be a value of @ref ADC_analog_watchdog_selection */\r\n  uint32_t HighThreshold;     /*!< Configures the ADC analog watchdog High threshold value.\r\n                                   This parameter must be a 12-bit value. */     \r\n  uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog High threshold value.\r\n                                   This parameter must be a 12-bit value. */\r\n  uint32_t Channel;           /*!< Configures ADC channel for the analog watchdog. \r\n                                   This parameter has an effect only if watchdog mode is configured on single channel \r\n                                   This parameter can be a value of @ref ADC_channels */      \r\n  uint32_t ITMode;            /*!< Specifies whether the analog watchdog is configured\r\n                                   is interrupt mode or in polling mode.\r\n                                   This parameter can be set to ENABLE or DISABLE */\r\n  uint32_t WatchdogNumber;    /*!< Reserved for future use, can be set to 0 */\r\n}ADC_AnalogWDGConfTypeDef;\r\n\r\n/** \r\n  * @brief  HAL ADC state machine: ADC states definition (bitfields)\r\n  */ \r\n/* States of ADC global scope */\r\n#define HAL_ADC_STATE_RESET             ((uint32_t)0x00000000U)    /*!< ADC not yet initialized or disabled */\r\n#define HAL_ADC_STATE_READY             ((uint32_t)0x00000001U)    /*!< ADC peripheral ready for use */\r\n#define HAL_ADC_STATE_BUSY_INTERNAL     ((uint32_t)0x00000002U)    /*!< ADC is busy to internal process (initialization, calibration) */\r\n#define HAL_ADC_STATE_TIMEOUT           ((uint32_t)0x00000004U)    /*!< TimeOut occurrence */\r\n\r\n/* States of ADC errors */\r\n#define HAL_ADC_STATE_ERROR_INTERNAL    ((uint32_t)0x00000010U)    /*!< Internal error occurrence */\r\n#define HAL_ADC_STATE_ERROR_CONFIG      ((uint32_t)0x00000020U)    /*!< Configuration error occurrence */\r\n#define HAL_ADC_STATE_ERROR_DMA         ((uint32_t)0x00000040U)    /*!< DMA error occurrence */\r\n\r\n/* States of ADC group regular */\r\n#define HAL_ADC_STATE_REG_BUSY          ((uint32_t)0x00000100U)    /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,\r\n                                                                       external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */\r\n#define HAL_ADC_STATE_REG_EOC           ((uint32_t)0x00000200U)    /*!< Conversion data available on group regular */\r\n#define HAL_ADC_STATE_REG_OVR           ((uint32_t)0x00000400U)    /*!< Overrun occurrence */\r\n\r\n/* States of ADC group injected */\r\n#define HAL_ADC_STATE_INJ_BUSY          ((uint32_t)0x00001000U)    /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,\r\n                                                                       external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */\r\n#define HAL_ADC_STATE_INJ_EOC           ((uint32_t)0x00002000U)    /*!< Conversion data available on group injected */\r\n\r\n/* States of ADC analog watchdogs */\r\n#define HAL_ADC_STATE_AWD1              ((uint32_t)0x00010000U)    /*!< Out-of-window occurrence of analog watchdog 1 */\r\n#define HAL_ADC_STATE_AWD2              ((uint32_t)0x00020000U)    /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 2 */\r\n#define HAL_ADC_STATE_AWD3              ((uint32_t)0x00040000U)    /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 3 */\r\n\r\n/* States of ADC multi-mode */\r\n#define HAL_ADC_STATE_MULTIMODE_SLAVE   ((uint32_t)0x00100000U)    /*!< Not available on STM32F7 device: ADC in multimode slave state, controlled by another ADC master ( */\r\n\r\n\r\n/** \r\n  * @brief  ADC handle Structure definition\r\n  */ \r\ntypedef struct\r\n{\r\n  ADC_TypeDef                   *Instance;                   /*!< Register base address */\r\n\r\n  ADC_InitTypeDef               Init;                        /*!< ADC required parameters */\r\n\r\n  __IO uint32_t                 NbrOfCurrentConversionRank;  /*!< ADC number of current conversion rank */\r\n\r\n  DMA_HandleTypeDef             *DMA_Handle;                 /*!< Pointer DMA Handler */\r\n\r\n  HAL_LockTypeDef               Lock;                        /*!< ADC locking object */\r\n\r\n  __IO uint32_t                 State;                       /*!< ADC communication state */\r\n\r\n  __IO uint32_t                 ErrorCode;                   /*!< ADC Error code */\r\n}ADC_HandleTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup ADC_Exported_Constants ADC Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup ADC_Error_Code ADC Error Code\r\n  * @{\r\n  */\r\n#define HAL_ADC_ERROR_NONE        ((uint32_t)0x00U)   /*!< No error                                              */\r\n#define HAL_ADC_ERROR_INTERNAL    ((uint32_t)0x01U)   /*!< ADC IP internal error: if problem of clocking, \r\n                                                          enable/disable, erroneous state                       */\r\n#define HAL_ADC_ERROR_OVR         ((uint32_t)0x02U)   /*!< Overrun error                                         */\r\n#define HAL_ADC_ERROR_DMA         ((uint32_t)0x04U)   /*!< DMA transfer error                                    */\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup ADC_ClockPrescaler  ADC Clock Prescaler\r\n  * @{\r\n  */ \r\n#define ADC_CLOCK_SYNC_PCLK_DIV2    ((uint32_t)0x00000000U)\r\n#define ADC_CLOCK_SYNC_PCLK_DIV4    ((uint32_t)ADC_CCR_ADCPRE_0)\r\n#define ADC_CLOCK_SYNC_PCLK_DIV6    ((uint32_t)ADC_CCR_ADCPRE_1)\r\n#define ADC_CLOCK_SYNC_PCLK_DIV8    ((uint32_t)ADC_CCR_ADCPRE)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases\r\n  * @{\r\n  */ \r\n#define ADC_TWOSAMPLINGDELAY_5CYCLES    ((uint32_t)0x00000000U)\r\n#define ADC_TWOSAMPLINGDELAY_6CYCLES    ((uint32_t)ADC_CCR_DELAY_0)\r\n#define ADC_TWOSAMPLINGDELAY_7CYCLES    ((uint32_t)ADC_CCR_DELAY_1)\r\n#define ADC_TWOSAMPLINGDELAY_8CYCLES    ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))\r\n#define ADC_TWOSAMPLINGDELAY_9CYCLES    ((uint32_t)ADC_CCR_DELAY_2)\r\n#define ADC_TWOSAMPLINGDELAY_10CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))\r\n#define ADC_TWOSAMPLINGDELAY_11CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))\r\n#define ADC_TWOSAMPLINGDELAY_12CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))\r\n#define ADC_TWOSAMPLINGDELAY_13CYCLES   ((uint32_t)ADC_CCR_DELAY_3)\r\n#define ADC_TWOSAMPLINGDELAY_14CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))\r\n#define ADC_TWOSAMPLINGDELAY_15CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))\r\n#define ADC_TWOSAMPLINGDELAY_16CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))\r\n#define ADC_TWOSAMPLINGDELAY_17CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))\r\n#define ADC_TWOSAMPLINGDELAY_18CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))\r\n#define ADC_TWOSAMPLINGDELAY_19CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))\r\n#define ADC_TWOSAMPLINGDELAY_20CYCLES   ((uint32_t)ADC_CCR_DELAY)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup ADC_Resolution ADC Resolution\r\n  * @{\r\n  */ \r\n#define ADC_RESOLUTION_12B  ((uint32_t)0x00000000U)\r\n#define ADC_RESOLUTION_10B  ((uint32_t)ADC_CR1_RES_0)\r\n#define ADC_RESOLUTION_8B   ((uint32_t)ADC_CR1_RES_1)\r\n#define ADC_RESOLUTION_6B   ((uint32_t)ADC_CR1_RES)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular\r\n  * @{\r\n  */ \r\n#define ADC_EXTERNALTRIGCONVEDGE_NONE           ((uint32_t)0x00000000U)\r\n#define ADC_EXTERNALTRIGCONVEDGE_RISING         ((uint32_t)ADC_CR2_EXTEN_0)\r\n#define ADC_EXTERNALTRIGCONVEDGE_FALLING        ((uint32_t)ADC_CR2_EXTEN_1)\r\n#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CR2_EXTEN)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular\r\n  * @{\r\n  */\r\n/* Note: Parameter ADC_SOFTWARE_START is a software parameter used for        */\r\n/*       compatibility with other STM32 devices.                              */\r\n\r\n\r\n#define ADC_EXTERNALTRIGCONV_T1_CC1    ((uint32_t)0x00000000U)\r\n#define ADC_EXTERNALTRIGCONV_T1_CC2    ((uint32_t)ADC_CR2_EXTSEL_0)\r\n#define ADC_EXTERNALTRIGCONV_T1_CC3    ((uint32_t)ADC_CR2_EXTSEL_1)\r\n#define ADC_EXTERNALTRIGCONV_T2_CC2    ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))\r\n#define ADC_EXTERNALTRIGCONV_T5_TRGO   ((uint32_t)ADC_CR2_EXTSEL_2)\r\n#define ADC_EXTERNALTRIGCONV_T4_CC4    ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))\r\n#define ADC_EXTERNALTRIGCONV_T3_CC4    ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))\r\n#define ADC_EXTERNALTRIGCONV_T8_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))\r\n#define ADC_EXTERNALTRIGCONV_T8_TRGO2  ((uint32_t)ADC_CR2_EXTSEL_3)\r\n#define ADC_EXTERNALTRIGCONV_T1_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))\r\n#define ADC_EXTERNALTRIGCONV_T1_TRGO2  ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))\r\n#define ADC_EXTERNALTRIGCONV_T2_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))\r\n#define ADC_EXTERNALTRIGCONV_T4_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))\r\n#define ADC_EXTERNALTRIGCONV_T6_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))\r\n\r\n#define ADC_EXTERNALTRIGCONV_EXT_IT11  ((uint32_t)ADC_CR2_EXTSEL)\r\n#define ADC_SOFTWARE_START             ((uint32_t)ADC_CR2_EXTSEL + 1)\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup ADC_Data_Align ADC Data Align\r\n  * @{\r\n  */ \r\n#define ADC_DATAALIGN_RIGHT      ((uint32_t)0x00000000U)\r\n#define ADC_DATAALIGN_LEFT       ((uint32_t)ADC_CR2_ALIGN)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup ADC_channels ADC Common Channels\r\n  * @{\r\n  */ \r\n#define ADC_CHANNEL_0           ((uint32_t)0x00000000U)\r\n#define ADC_CHANNEL_1           ((uint32_t)ADC_CR1_AWDCH_0)\r\n#define ADC_CHANNEL_2           ((uint32_t)ADC_CR1_AWDCH_1)\r\n#define ADC_CHANNEL_3           ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))\r\n#define ADC_CHANNEL_4           ((uint32_t)ADC_CR1_AWDCH_2)\r\n#define ADC_CHANNEL_5           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))\r\n#define ADC_CHANNEL_6           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))\r\n#define ADC_CHANNEL_7           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))\r\n#define ADC_CHANNEL_8           ((uint32_t)ADC_CR1_AWDCH_3)\r\n#define ADC_CHANNEL_9           ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))\r\n#define ADC_CHANNEL_10          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))\r\n#define ADC_CHANNEL_11          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))\r\n#define ADC_CHANNEL_12          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))\r\n#define ADC_CHANNEL_13          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))\r\n#define ADC_CHANNEL_14          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))\r\n#define ADC_CHANNEL_15          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))\r\n#define ADC_CHANNEL_16          ((uint32_t)ADC_CR1_AWDCH_4)\r\n#define ADC_CHANNEL_17          ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))\r\n#define ADC_CHANNEL_18          ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))\r\n\r\n#define ADC_CHANNEL_VREFINT     ((uint32_t)ADC_CHANNEL_17)\r\n#define ADC_CHANNEL_VBAT        ((uint32_t)ADC_CHANNEL_18)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup ADC_sampling_times ADC Sampling Times\r\n  * @{\r\n  */ \r\n#define ADC_SAMPLETIME_3CYCLES    ((uint32_t)0x00000000U)\r\n#define ADC_SAMPLETIME_15CYCLES   ((uint32_t)ADC_SMPR1_SMP10_0)\r\n#define ADC_SAMPLETIME_28CYCLES   ((uint32_t)ADC_SMPR1_SMP10_1)\r\n#define ADC_SAMPLETIME_56CYCLES   ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))\r\n#define ADC_SAMPLETIME_84CYCLES   ((uint32_t)ADC_SMPR1_SMP10_2)\r\n#define ADC_SAMPLETIME_112CYCLES  ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))\r\n#define ADC_SAMPLETIME_144CYCLES  ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))\r\n#define ADC_SAMPLETIME_480CYCLES  ((uint32_t)ADC_SMPR1_SMP10)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n  /** @defgroup ADC_EOCSelection ADC EOC Selection\r\n  * @{\r\n  */ \r\n#define ADC_EOC_SEQ_CONV              ((uint32_t)0x00000000U)\r\n#define ADC_EOC_SINGLE_CONV           ((uint32_t)0x00000001U)\r\n#define ADC_EOC_SINGLE_SEQ_CONV       ((uint32_t)0x00000002U)  /*!< reserved for future use */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup ADC_Event_type ADC Event Type\r\n  * @{\r\n  */ \r\n#define ADC_AWD_EVENT             ((uint32_t)ADC_FLAG_AWD)\r\n#define ADC_OVR_EVENT             ((uint32_t)ADC_FLAG_OVR)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection\r\n  * @{\r\n  */ \r\n#define ADC_ANALOGWATCHDOG_SINGLE_REG         ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))\r\n#define ADC_ANALOGWATCHDOG_SINGLE_INJEC       ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))\r\n#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC    ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))\r\n#define ADC_ANALOGWATCHDOG_ALL_REG            ((uint32_t)ADC_CR1_AWDEN)\r\n#define ADC_ANALOGWATCHDOG_ALL_INJEC          ((uint32_t)ADC_CR1_JAWDEN)\r\n#define ADC_ANALOGWATCHDOG_ALL_REGINJEC       ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))\r\n#define ADC_ANALOGWATCHDOG_NONE               ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */ \r\n    \r\n/** @defgroup ADC_interrupts_definition ADC Interrupts Definition\r\n  * @{\r\n  */ \r\n#define ADC_IT_EOC      ((uint32_t)ADC_CR1_EOCIE)  \r\n#define ADC_IT_AWD      ((uint32_t)ADC_CR1_AWDIE) \r\n#define ADC_IT_JEOC     ((uint32_t)ADC_CR1_JEOCIE)\r\n#define ADC_IT_OVR      ((uint32_t)ADC_CR1_OVRIE) \r\n/**\r\n  * @}\r\n  */ \r\n    \r\n/** @defgroup ADC_flags_definition ADC Flags Definition\r\n  * @{\r\n  */ \r\n#define ADC_FLAG_AWD    ((uint32_t)ADC_SR_AWD)\r\n#define ADC_FLAG_EOC    ((uint32_t)ADC_SR_EOC)\r\n#define ADC_FLAG_JEOC   ((uint32_t)ADC_SR_JEOC)\r\n#define ADC_FLAG_JSTRT  ((uint32_t)ADC_SR_JSTRT)\r\n#define ADC_FLAG_STRT   ((uint32_t)ADC_SR_STRT)\r\n#define ADC_FLAG_OVR    ((uint32_t)ADC_SR_OVR)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup ADC_channels_type ADC Channels Type\r\n  * @{\r\n  */ \r\n#define ADC_ALL_CHANNELS      ((uint32_t)0x00000001U)\r\n#define ADC_REGULAR_CHANNELS  ((uint32_t)0x00000002U) /*!< reserved for future use */\r\n#define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003U) /*!< reserved for future use */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup ADC_Exported_Macros ADC Exported Macros\r\n  * @{\r\n  */\r\n\t\r\n/** @brief Reset ADC handle state\r\n  * @param  __HANDLE__: ADC handle\r\n  * @retval None\r\n  */\r\n#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)\r\n\r\n/**\r\n  * @brief  Enable the ADC peripheral.\r\n  * @param  __HANDLE__: ADC handle\r\n  * @retval None\r\n  */\r\n#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |=  ADC_CR2_ADON)\r\n\r\n/**\r\n  * @brief  Disable the ADC peripheral.\r\n  * @param  __HANDLE__: ADC handle\r\n  * @retval None\r\n  */\r\n#define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &=  ~ADC_CR2_ADON)\r\n\r\n/**\r\n  * @brief  Enable the ADC end of conversion interrupt.\r\n  * @param  __HANDLE__: specifies the ADC Handle.\r\n  * @param  __INTERRUPT__: ADC Interrupt.\r\n  * @retval None\r\n  */\r\n#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disable the ADC end of conversion interrupt.\r\n  * @param  __HANDLE__: specifies the ADC Handle.\r\n  * @param  __INTERRUPT__: ADC interrupt.\r\n  * @retval None\r\n  */\r\n#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))\r\n\r\n/** @brief  Check if the specified ADC interrupt source is enabled or disabled.\r\n  * @param  __HANDLE__: specifies the ADC Handle.\r\n  * @param  __INTERRUPT__: specifies the ADC interrupt source to check.\r\n  * @retval The new state of __IT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Clear the ADC's pending flags.\r\n  * @param  __HANDLE__: specifies the ADC Handle.\r\n  * @param  __FLAG__: ADC flag.\r\n  * @retval None\r\n  */\r\n#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))\r\n\r\n/**\r\n  * @brief  Get the selected ADC's flag status.\r\n  * @param  __HANDLE__: specifies the ADC Handle.\r\n  * @param  __FLAG__: ADC flag.\r\n  * @retval None\r\n  */\r\n#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Include ADC HAL Extension module */\r\n#include \"stm32f7xx_hal_adc_ex.h\"\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup ADC_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup ADC_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n/* Initialization/de-initialization functions ***********************************/\r\nHAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);\r\nHAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);\r\nvoid       HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);\r\nvoid       HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup ADC_Exported_Functions_Group2\r\n  * @{\r\n  */\r\n/* I/O operation functions ******************************************************/\r\nHAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);\r\nHAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);\r\nHAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);\r\n\r\nHAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);\r\n\r\nHAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);\r\nHAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);\r\n\r\nvoid              HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);\r\n\r\nHAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);\r\nHAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);\r\n\r\nuint32_t          HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);\r\n\r\nvoid       HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);\r\nvoid       HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);\r\nvoid       HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);\r\nvoid       HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup ADC_Exported_Functions_Group3\r\n  * @{\r\n  */\r\n/* Peripheral Control functions *************************************************/\r\nHAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);\r\nHAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup ADC_Exported_Functions_Group4\r\n  * @{\r\n  */\r\n/* Peripheral State functions ***************************************************/\r\nuint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);\r\nuint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup ADC_Private_Constants ADC Private Constants\r\n  * @{\r\n  */\r\n/* Delay for ADC stabilization time.                                        */\r\n/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB).       */\r\n/* Unit: us                                                                 */\r\n#define ADC_STAB_DELAY_US               ((uint32_t) 3U)\r\n/* Delay for temperature sensor stabilization time.                         */\r\n/* Maximum delay is 10us (refer to device datasheet, parameter tSTART).     */\r\n/* Unit: us                                                                 */\r\n#define ADC_TEMPSENSOR_DELAY_US         ((uint32_t) 10U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup ADC_Private_Macros ADC Private Macros\r\n  * @{\r\n  */\r\n/* Macro reserved for internal HAL driver usage, not intended to be used in\r\n   code of final user */\r\n\r\n/**\r\n  * @brief Verification of ADC state: enabled or disabled\r\n  * @param __HANDLE__: ADC handle\r\n  * @retval SET (ADC enabled) or RESET (ADC disabled)\r\n  */\r\n#define ADC_IS_ENABLE(__HANDLE__)                                              \\\r\n  ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS )            \\\r\n  ) ? SET : RESET)\r\n\r\n/**\r\n  * @brief Test if conversion trigger of regular group is software start\r\n  *        or external trigger.\r\n  * @param __HANDLE__: ADC handle\r\n  * @retval SET (software start) or RESET (external trigger)\r\n  */\r\n#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__)                              \\\r\n  (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)\r\n\r\n/**\r\n  * @brief Test if conversion trigger of injected group is software start\r\n  *        or external trigger.\r\n  * @param __HANDLE__: ADC handle\r\n  * @retval SET (software start) or RESET (external trigger)\r\n  */\r\n#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)                             \\\r\n  (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)\r\n\r\n/**\r\n  * @brief Simultaneously clears and sets specific bits of the handle State\r\n  * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),\r\n  *        the first parameter is the ADC handle State, the second parameter is the\r\n  *        bit field to clear, the third and last parameter is the bit field to set.\r\n  * @retval None\r\n  */\r\n#define ADC_STATE_CLR_SET MODIFY_REG\r\n\r\n/**\r\n  * @brief Clear ADC error code (set it to error code: \"no error\")\r\n  * @param __HANDLE__: ADC handle\r\n  * @retval None\r\n  */\r\n#define ADC_CLEAR_ERRORCODE(__HANDLE__)                                        \\\r\n  ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)\r\n#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__)     (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \\\r\n                                                  ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \\\r\n                                                  ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV6) || \\\r\n                                                  ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV8))\r\n#define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES)  || \\\r\n                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES)  || \\\r\n                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES)  || \\\r\n                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES)  || \\\r\n                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES)  || \\\r\n                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \\\r\n                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \\\r\n                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \\\r\n                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \\\r\n                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \\\r\n                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \\\r\n                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \\\r\n                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \\\r\n                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \\\r\n                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \\\r\n                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_20CYCLES))\r\n#define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \\\r\n                                           ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \\\r\n                                           ((__RESOLUTION__) == ADC_RESOLUTION_8B)  || \\\r\n                                           ((__RESOLUTION__) == ADC_RESOLUTION_6B))\t\t\t\r\n#define IS_ADC_EXT_TRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE)    || \\\r\n                                        ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING)  || \\\r\n                                        ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \\\r\n                                        ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))\r\n#define IS_ADC_EXT_TRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC1)   || \\\r\n                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC2)   || \\\r\n                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC3)   || \\\r\n                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_CC2)   || \\\r\n                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T5_TRGO)  || \\\r\n                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_CC4)   || \\\r\n                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T3_CC4) || \\\r\n                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO)  || \\\r\n                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \\\r\n                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO)  || \\\r\n                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \\\r\n                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_TRGO)  || \\\r\n                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_TRGO)  || \\\r\n                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T6_TRGO)  || \\\r\n                                      ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \\\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t((__REGTRIG__) == ADC_SOFTWARE_START))\r\n#define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \\\r\n                                      ((__ALIGN__) == ADC_DATAALIGN_LEFT))\t\t\r\n                                      \t\t\t\t\t\t\t\t\t\r\n#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_3CYCLES)   || \\\r\n                                      ((__TIME__) == ADC_SAMPLETIME_15CYCLES)  || \\\r\n                                      ((__TIME__) == ADC_SAMPLETIME_28CYCLES)  || \\\r\n                                      ((__TIME__) == ADC_SAMPLETIME_56CYCLES)  || \\\r\n                                      ((__TIME__) == ADC_SAMPLETIME_84CYCLES)  || \\\r\n                                      ((__TIME__) == ADC_SAMPLETIME_112CYCLES) || \\\r\n                                      ((__TIME__) == ADC_SAMPLETIME_144CYCLES) || \\\r\n                                      ((__TIME__) == ADC_SAMPLETIME_480CYCLES))\t\r\n#define IS_ADC_EOCSelection(__EOCSelection__) (((__EOCSelection__) == ADC_EOC_SINGLE_CONV)   || \\\r\n                                               ((__EOCSelection__) == ADC_EOC_SEQ_CONV)  || \\\r\n                                               ((__EOCSelection__) == ADC_EOC_SINGLE_SEQ_CONV))\t\r\n#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_AWD_EVENT) || \\\r\n                                      ((__EVENT__) == ADC_OVR_EVENT))\t\t\r\n#define IS_ADC_ANALOG_WATCHDOG(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REG)        || \\\r\n                                              ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)      || \\\r\n                                              ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)   || \\\r\n                                              ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REG)           || \\\r\n                                              ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_INJEC)         || \\\r\n                                              ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)      || \\\r\n                                              ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_NONE))\r\n#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \\\r\n                                            ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \\\r\n                                            ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))\r\n#define IS_ADC_THRESHOLD(__THRESHOLD__) ((__THRESHOLD__) <= ((uint32_t)0xFFF))\r\n#define IS_ADC_REGULAR_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16)))\r\n#define IS_ADC_REGULAR_RANK(__RANK__) (((__RANK__) >= ((uint32_t)1)) && ((__RANK__) <= ((uint32_t)16)))\r\n#define IS_ADC_REGULAR_DISC_NUMBER(__NUMBER__) (((__NUMBER__) >= ((uint32_t)1)) && ((__NUMBER__) <= ((uint32_t)8)))\r\n#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__)                                     \\\r\n   ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= ((uint32_t)0x0FFF))) || \\\r\n    (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= ((uint32_t)0x03FF))) || \\\r\n    (((__RESOLUTION__) == ADC_RESOLUTION_8B)  && ((__ADC_VALUE__) <= ((uint32_t)0x00FF))) || \\\r\n    (((__RESOLUTION__) == ADC_RESOLUTION_6B)  && ((__ADC_VALUE__) <= ((uint32_t)0x003F))))\r\n\r\n/**\r\n  * @brief  Set ADC Regular channel sequence length.\r\n  * @param  _NbrOfConversion_: Regular channel sequence length. \r\n  * @retval None\r\n  */\r\n#define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20)\r\n\r\n/**\r\n  * @brief  Set the ADC's sample time for channel numbers between 10 and 18.\r\n  * @param  _SAMPLETIME_: Sample time parameter.\r\n  * @param  _CHANNELNB_: Channel number.  \r\n  * @retval None\r\n  */\r\n#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10)))\r\n\r\n/**\r\n  * @brief  Set the ADC's sample time for channel numbers between 0 and 9.\r\n  * @param  _SAMPLETIME_: Sample time parameter.\r\n  * @param  _CHANNELNB_: Channel number.  \r\n  * @retval None\r\n  */\r\n#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((uint32_t)((uint16_t)(_CHANNELNB_)))))\r\n\r\n/**\r\n  * @brief  Set the selected regular channel rank for rank between 1 and 6.\r\n  * @param  _CHANNELNB_: Channel number.\r\n  * @param  _RANKNB_: Rank number.    \r\n  * @retval None\r\n  */\r\n#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 1)))\r\n\r\n/**\r\n  * @brief  Set the selected regular channel rank for rank between 7 and 12.\r\n  * @param  _CHANNELNB_: Channel number.\r\n  * @param  _RANKNB_: Rank number.    \r\n  * @retval None\r\n  */\r\n#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 7)))\r\n\r\n/**\r\n  * @brief  Set the selected regular channel rank for rank between 13 and 16.\r\n  * @param  _CHANNELNB_: Channel number.\r\n  * @param  _RANKNB_: Rank number.    \r\n  * @retval None\r\n  */\r\n#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 13)))\r\n\r\n/**\r\n  * @brief  Enable ADC continuous conversion mode.\r\n  * @param  _CONTINUOUS_MODE_: Continuous mode.\r\n  * @retval None\r\n  */\r\n#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1)\r\n\r\n/**\r\n  * @brief  Configures the number of discontinuous conversions for the regular group channels.\r\n  * @param  _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions.\r\n  * @retval None\r\n  */\r\n#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM))\r\n\r\n/**\r\n  * @brief  Enable ADC scan mode.\r\n  * @param  _SCANCONV_MODE_: Scan conversion mode.\r\n  * @retval None\r\n  */\r\n#define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8)\r\n\r\n/**\r\n  * @brief  Enable the ADC end of conversion selection.\r\n  * @param  _EOCSelection_MODE_: End of conversion selection mode.\r\n  * @retval None\r\n  */\r\n#define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10)\r\n\r\n/**\r\n  * @brief  Enable the ADC DMA continuous request.\r\n  * @param  _DMAContReq_MODE_: DMA continuous request mode.\r\n  * @retval None\r\n  */\r\n#define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9)\r\n\r\n/**\r\n  * @brief Return resolution bits in CR1 register.\r\n  * @param __HANDLE__: ADC handle\r\n  * @retval None\r\n  */\r\n#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\r\n/**\r\n  * @}\r\n  */\r\n\t\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup ADC_Private_Functions ADC Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\t\r\n/**\r\n  * @}\r\n  */\r\n\t\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /*__STM32F7xx_ADC_H */\r\n\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_adc.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of ADC HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_ADC_EX_H\r\n#define __STM32F7xx_ADC_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup ADCEx\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup ADCEx_Exported_Types ADC Exported Types\r\n  * @{\r\n  */\r\n   \r\n/** \r\n  * @brief  ADC Configuration injected Channel structure definition\r\n  * @note   Parameters of this structure are shared within 2 scopes:\r\n  *          - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset\r\n  *          - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,\r\n  *            AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.\r\n  * @note   The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.\r\n  *         ADC state can be either:\r\n  *          - For all parameters: ADC disabled\r\n  *          - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group.\r\n  *          - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group.\r\n  */\r\ntypedef struct \r\n{\r\n  uint32_t InjectedChannel;               /*!< Selection of ADC channel to configure\r\n                                               This parameter can be a value of @ref ADC_channels\r\n                                               Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */\r\n  uint32_t InjectedRank;                  /*!< Rank in the injected group sequencer\r\n                                               This parameter must be a value of @ref ADCEx_injected_rank\r\n                                               Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */\r\n  uint32_t InjectedSamplingTime;          /*!< Sampling time value to be set for the selected channel.\r\n                                               Unit: ADC clock cycles\r\n                                               Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).\r\n                                               This parameter can be a value of @ref ADC_sampling_times\r\n                                               Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.\r\n                                                        If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.\r\n                                               Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),\r\n                                                     sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)\r\n                                                     Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */\r\n  uint32_t InjectedOffset;                /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).\r\n                                               Offset value must be a positive number.\r\n                                               Depending of ADC resolution selected (12, 10, 8 or 6 bits),\r\n                                               this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */\r\n  uint32_t InjectedNbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the injected group sequencer.\r\n                                               To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.\r\n                                               This parameter must be a number between Min_Data = 1 and Max_Data = 4.\r\n                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to \r\n                                                        configure a channel on injected group can impact the configuration of other channels previously set. */\r\n  uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).\r\n                                               Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.\r\n                                               Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.\r\n                                               This parameter can be set to ENABLE or DISABLE.\r\n                                               Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.\r\n                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to \r\n                                                        configure a channel on injected group can impact the configuration of other channels previously set. */\r\n  uint32_t AutoInjectedConv;              /*!< Enables or disables the selected ADC automatic injected group conversion after regular one\r\n                                               This parameter can be set to ENABLE or DISABLE.      \r\n                                               Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)\r\n                                               Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)\r\n                                               Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.\r\n                                                     To maintain JAUTO always enabled, DMA must be configured in circular mode.\r\n                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to\r\n                                                        configure a channel on injected group can impact the configuration of other channels previously set. */\r\n  uint32_t ExternalTrigInjecConv;         /*!< Selects the external event used to trigger the conversion start of injected group.\r\n                                               If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.\r\n                                               If set to external trigger source, triggering is on event rising edge.\r\n                                               This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected\r\n                                               Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).\r\n                                                     If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)\r\n                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to\r\n                                                        configure a channel on injected group can impact the configuration of other channels previously set. */\r\n  uint32_t ExternalTrigInjecConvEdge;     /*!< Selects the external trigger edge of injected group.\r\n                                               This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected.\r\n                                               If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.\r\n                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to \r\n                                                        configure a channel on injected group can impact the configuration of other channels previously set. */\r\n}ADC_InjectionConfTypeDef; \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** \r\n  * @brief ADC Configuration multi-mode structure definition  \r\n  */ \r\ntypedef struct\r\n{\r\n  uint32_t Mode;              /*!< Configures the ADC to operate in independent or multi mode. \r\n                                   This parameter can be a value of @ref ADCEx_Common_mode */\r\n  uint32_t DMAAccessMode;     /*!< Configures the Direct memory access mode for multi ADC mode.\r\n                                   This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multi_mode */\r\n  uint32_t TwoSamplingDelay;  /*!< Configures the Delay between 2 sampling phases.\r\n                                   This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */\r\n}ADC_MultiModeTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup ADCEx_Exported_Constants ADC Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup ADCEx_Common_mode ADC Common Mode\r\n  * @{\r\n  */\r\n#define ADC_MODE_INDEPENDENT                  ((uint32_t)0x00000000U)      \r\n#define ADC_DUALMODE_REGSIMULT_INJECSIMULT    ((uint32_t)ADC_CCR_MULTI_0)\r\n#define ADC_DUALMODE_REGSIMULT_ALTERTRIG      ((uint32_t)ADC_CCR_MULTI_1)\r\n#define ADC_DUALMODE_INJECSIMULT              ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))\r\n#define ADC_DUALMODE_REGSIMULT                ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))\r\n#define ADC_DUALMODE_INTERL                   ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))\r\n#define ADC_DUALMODE_ALTERTRIG                ((uint32_t)(ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))\r\n#define ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT  ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0))\r\n#define ADC_TRIPLEMODE_REGSIMULT_AlterTrig    ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1))\r\n#define ADC_TRIPLEMODE_INJECSIMULT            ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))\r\n#define ADC_TRIPLEMODE_REGSIMULT              ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))\r\n#define ADC_TRIPLEMODE_INTERL                 ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))\r\n#define ADC_TRIPLEMODE_ALTERTRIG              ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode ADC Direct Memory Access Mode For Multi Mode\r\n  * @{\r\n  */ \r\n#define ADC_DMAACCESSMODE_DISABLED  ((uint32_t)0x00000000U)     /*!< DMA mode disabled */\r\n#define ADC_DMAACCESSMODE_1         ((uint32_t)ADC_CCR_DMA_0)  /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/\r\n#define ADC_DMAACCESSMODE_2         ((uint32_t)ADC_CCR_DMA_1)  /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/\r\n#define ADC_DMAACCESSMODE_3         ((uint32_t)ADC_CCR_DMA)    /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup ADCEx_External_trigger_edge_Injected ADC External Trigger Edge Injected\r\n  * @{\r\n  */\r\n#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE           ((uint32_t)0x00000000U)\r\n#define ADC_EXTERNALTRIGINJECCONVEDGE_RISING         ((uint32_t)ADC_CR2_JEXTEN_0)\r\n#define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING        ((uint32_t)ADC_CR2_JEXTEN_1)\r\n#define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CR2_JEXTEN)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup ADCEx_External_trigger_Source_Injected ADC External Trigger Source Injected\r\n  * @{\r\n  */\r\n#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO         ((uint32_t)0x00000000U)\r\n#define ADC_EXTERNALTRIGINJECCONV_T1_CC4          ((uint32_t)ADC_CR2_JEXTSEL_0)\r\n#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO         ((uint32_t)ADC_CR2_JEXTSEL_1)\r\n#define ADC_EXTERNALTRIGINJECCONV_T2_CC1          ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))\r\n#define ADC_EXTERNALTRIGINJECCONV_T3_CC4          ((uint32_t)ADC_CR2_JEXTSEL_2)\r\n#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO         ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))\r\n\r\n#define ADC_EXTERNALTRIGINJECCONV_T8_CC4          ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))\r\n#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2        ((uint32_t)ADC_CR2_JEXTSEL_3)\r\n#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO         ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0))\r\n#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO2        ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1))\r\n#define ADC_EXTERNALTRIGINJECCONV_T3_CC3          ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))\r\n#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO         ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2))\r\n#define ADC_EXTERNALTRIGINJECCONV_T3_CC1          ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))\r\n#define ADC_EXTERNALTRIGINJECCONV_T6_TRGO         ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))\r\n#define ADC_INJECTED_SOFTWARE_START                ((uint32_t)ADC_CR2_JEXTSEL + 1)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup ADCEx_injected_rank ADC Injected Rank\r\n  * @{\r\n  */ \r\n#define ADC_INJECTED_RANK_1    ((uint32_t)0x00000001U)\r\n#define ADC_INJECTED_RANK_2    ((uint32_t)0x00000002U)\r\n#define ADC_INJECTED_RANK_3    ((uint32_t)0x00000003U)\r\n#define ADC_INJECTED_RANK_4    ((uint32_t)0x00000004U)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup ADCEx_channels  ADC Specific Channels\r\n  * @{\r\n  */\r\n#define ADC_CHANNEL_TEMPSENSOR  ((uint32_t)ADC_CHANNEL_18 | 0x10000000U)    \r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup ADC_Exported_Macros ADC Exported Macros\r\n  * @{\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup ADCEx_Exported_Functions\r\n  * @{\r\n  */\r\n\t\r\n/** @addtogroup ADCEx_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n\r\n/* I/O operation functions ******************************************************/\r\nHAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);\r\nHAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);\r\nHAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);\r\nHAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);\r\nuint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);\r\nHAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);\r\nHAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc);\r\nuint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc);\r\nvoid HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);\r\n\r\n/* Peripheral Control functions *************************************************/\r\nHAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);\r\nHAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup ADCEx_Private_Constants ADC Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\t\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup ADCEx_Private_Macros ADC Private Macros\r\n  * @{\r\n  */\r\n#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18)  || \\\r\n                                 ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR))\r\n                                     \r\n#define IS_ADC_MODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT)                 || \\\r\n                               ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT)   || \\\r\n                               ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG)     || \\\r\n                               ((__MODE__) == ADC_DUALMODE_INJECSIMULT)             || \\\r\n                               ((__MODE__) == ADC_DUALMODE_REGSIMULT)               || \\\r\n                               ((__MODE__) == ADC_DUALMODE_INTERL)                  || \\\r\n                               ((__MODE__) == ADC_DUALMODE_ALTERTRIG)               || \\\r\n                               ((__MODE__) == ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT) || \\\r\n                               ((__MODE__) == ADC_TRIPLEMODE_REGSIMULT_AlterTrig)   || \\\r\n                               ((__MODE__) == ADC_TRIPLEMODE_INJECSIMULT)           || \\\r\n                               ((__MODE__) == ADC_TRIPLEMODE_REGSIMULT)             || \\\r\n                               ((__MODE__) == ADC_TRIPLEMODE_INTERL)                || \\\r\n                               ((__MODE__) == ADC_TRIPLEMODE_ALTERTRIG))\r\n#define IS_ADC_DMA_ACCESS_MODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || \\\r\n                                          ((__MODE__) == ADC_DMAACCESSMODE_1)        || \\\r\n                                          ((__MODE__) == ADC_DMAACCESSMODE_2)        || \\\r\n                                          ((__MODE__) == ADC_DMAACCESSMODE_3))\r\n#define IS_ADC_EXT_INJEC_TRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_NONE)    || \\\r\n                                              ((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_RISING)  || \\\r\n                                              ((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_FALLING) || \\\r\n                                              ((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING))\r\n#define IS_ADC_EXT_INJEC_TRIG(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO)  || \\\r\n                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_CC4)   || \\\r\n                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO)  || \\\r\n                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)   || \\\r\n                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)   || \\\r\n                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO)  || \\\r\n                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4)   || \\\r\n                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \\\r\n                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO)  || \\\r\n                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \\\r\n                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC3)   || \\\r\n                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO)  || \\\r\n                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC1)   || \\\r\n                                            ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO)  || \\\r\n\t\t\t\t\t\t\t\t\t\t\t((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START))\r\n#define IS_ADC_INJECTED_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)4)))\r\n#define IS_ADC_INJECTED_RANK(__RANK__) (((__RANK__) >= ((uint32_t)1)) && ((__RANK__) <= ((uint32_t)4)))\r\n\r\n/**\r\n  * @brief  Set the selected injected Channel rank.\r\n  * @param  _CHANNELNB_: Channel number.\r\n  * @param  _RANKNB_: Rank number. \r\n  * @param  _JSQR_JL_: Sequence length.     \r\n  * @retval None\r\n  */\r\n#define   ADC_JSQR(_CHANNELNB_, _RANKNB_,_JSQR_JL_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * (uint8_t)(((_RANKNB_) + 3) - (_JSQR_JL_))))\r\n/**\r\n  * @}\r\n  */\r\n\t\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup ADCEx_Private_Functions ADC Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\t\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /*__STM32F7xx_ADC_EX_H */\r\n\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_can.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_can.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of CAN HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_CAN_H\r\n#define __STM32F7xx_HAL_CAN_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup CAN\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup CAN_Exported_Types CAN Exported Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  HAL State structures definition\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_CAN_STATE_RESET             = 0x00U,  /*!< CAN not yet initialized or disabled */\r\n  HAL_CAN_STATE_READY             = 0x01U,  /*!< CAN initialized and ready for use   */\r\n  HAL_CAN_STATE_BUSY              = 0x02U,  /*!< CAN process is ongoing              */\r\n  HAL_CAN_STATE_BUSY_TX           = 0x12U,  /*!< CAN process is ongoing              */\r\n  HAL_CAN_STATE_BUSY_RX           = 0x22U,  /*!< CAN process is ongoing              */\r\n  HAL_CAN_STATE_BUSY_TX_RX        = 0x32U,  /*!< CAN process is ongoing              */\r\n  HAL_CAN_STATE_TIMEOUT           = 0x03U,  /*!< Timeout state                       */\r\n  HAL_CAN_STATE_ERROR             = 0x04U   /*!< CAN error state                     */\r\n\r\n}HAL_CAN_StateTypeDef;\r\n\r\n/**\r\n  * @brief  CAN init structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t Prescaler;  /*!< Specifies the length of a time quantum.\r\n                            This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */\r\n\r\n  uint32_t Mode;       /*!< Specifies the CAN operating mode.\r\n                            This parameter can be a value of @ref CAN_operating_mode */\r\n\r\n  uint32_t SJW;        /*!< Specifies the maximum number of time quanta\r\n                            the CAN hardware is allowed to lengthen or\r\n                            shorten a bit to perform resynchronization.\r\n                            This parameter can be a value of @ref CAN_synchronisation_jump_width */\r\n\r\n  uint32_t BS1;        /*!< Specifies the number of time quanta in Bit Segment 1.\r\n                            This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */\r\n\r\n  uint32_t BS2;        /*!< Specifies the number of time quanta in Bit Segment 2.\r\n                            This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */\r\n\r\n  uint32_t TTCM;       /*!< Enable or disable the time triggered communication mode.\r\n                            This parameter can be set to ENABLE or DISABLE. */\r\n\r\n  uint32_t ABOM;       /*!< Enable or disable the automatic bus-off management.\r\n                            This parameter can be set to ENABLE or DISABLE */\r\n\r\n  uint32_t AWUM;       /*!< Enable or disable the automatic wake-up mode.\r\n                            This parameter can be set to ENABLE or DISABLE */\r\n\r\n  uint32_t NART;       /*!< Enable or disable the non-automatic retransmission mode.\r\n                            This parameter can be set to ENABLE or DISABLE */\r\n\r\n  uint32_t RFLM;       /*!< Enable or disable the receive FIFO Locked mode.\r\n                            This parameter can be set to ENABLE or DISABLE */\r\n\r\n  uint32_t TXFP;       /*!< Enable or disable the transmit FIFO priority.\r\n                            This parameter can be set to ENABLE or DISABLE */\r\n}CAN_InitTypeDef;\r\n\r\n/**\r\n  * @brief  CAN filter configuration structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t FilterIdHigh;          /*!< Specifies the filter identification number (MSBs for a 32-bit\r\n                                       configuration, first one for a 16-bit configuration).\r\n                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r\n\r\n  uint32_t FilterIdLow;           /*!< Specifies the filter identification number (LSBs for a 32-bit\r\n                                       configuration, second one for a 16-bit configuration).\r\n                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r\n\r\n  uint32_t FilterMaskIdHigh;      /*!< Specifies the filter mask number or identification number,\r\n                                       according to the mode (MSBs for a 32-bit configuration,\r\n                                       first one for a 16-bit configuration).\r\n                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r\n\r\n  uint32_t FilterMaskIdLow;       /*!< Specifies the filter mask number or identification number,\r\n                                       according to the mode (LSBs for a 32-bit configuration,\r\n                                       second one for a 16-bit configuration).\r\n                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r\n\r\n  uint32_t FilterFIFOAssignment;  /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.\r\n                                       This parameter can be a value of @ref CAN_filter_FIFO */\r\n\r\n  uint32_t FilterNumber;          /*!< Specifies the filter which will be initialized.\r\n                                       This parameter must be a number between Min_Data = 0 and Max_Data = 27 */\r\n\r\n  uint32_t FilterMode;            /*!< Specifies the filter mode to be initialized.\r\n                                       This parameter can be a value of @ref CAN_filter_mode */\r\n\r\n  uint32_t FilterScale;           /*!< Specifies the filter scale.\r\n                                       This parameter can be a value of @ref CAN_filter_scale */\r\n\r\n  uint32_t FilterActivation;      /*!< Enable or disable the filter.\r\n                                       This parameter can be set to ENABLE or DISABLE. */\r\n\r\n  uint32_t BankNumber;            /*!< Select the start slave bank filter.\r\n                                       This parameter must be a number between Min_Data = 0 and Max_Data = 28 */\r\n\r\n}CAN_FilterConfTypeDef;\r\n\r\n/**\r\n  * @brief  CAN Tx message structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t StdId;    /*!< Specifies the standard identifier.\r\n                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */\r\n\r\n  uint32_t ExtId;    /*!< Specifies the extended identifier.\r\n                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */\r\n\r\n  uint32_t IDE;      /*!< Specifies the type of identifier for the message that will be transmitted.\r\n                          This parameter can be a value of @ref CAN_Identifier_Type */\r\n\r\n  uint32_t RTR;      /*!< Specifies the type of frame for the message that will be transmitted.\r\n                          This parameter can be a value of @ref CAN_remote_transmission_request */\r\n\r\n  uint32_t DLC;      /*!< Specifies the length of the frame that will be transmitted.\r\n                          This parameter must be a number between Min_Data = 0 and Max_Data = 8 */\r\n\r\n  uint8_t Data[8];  /*!< Contains the data to be transmitted.\r\n                          This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */\r\n\r\n}CanTxMsgTypeDef;\r\n\r\n/**\r\n  * @brief  CAN Rx message structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t StdId;       /*!< Specifies the standard identifier.\r\n                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */\r\n\r\n  uint32_t ExtId;       /*!< Specifies the extended identifier.\r\n                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */\r\n\r\n  uint32_t IDE;         /*!< Specifies the type of identifier for the message that will be received.\r\n                             This parameter can be a value of @ref CAN_Identifier_Type */\r\n\r\n  uint32_t RTR;         /*!< Specifies the type of frame for the received message.\r\n                             This parameter can be a value of @ref CAN_remote_transmission_request */\r\n\r\n  uint32_t DLC;         /*!< Specifies the length of the frame that will be received.\r\n                             This parameter must be a number between Min_Data = 0 and Max_Data = 8 */\r\n\r\n  uint8_t Data[8];      /*!< Contains the data to be received.\r\n                             This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */\r\n\r\n  uint32_t FMI;         /*!< Specifies the index of the filter the message stored in the mailbox passes through.\r\n                             This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */\r\n\r\n  uint32_t FIFONumber;  /*!< Specifies the receive FIFO number.\r\n                             This parameter can be CAN_FIFO0 or CAN_FIFO1 */\r\n\r\n}CanRxMsgTypeDef;\r\n\r\n/**\r\n  * @brief  CAN handle Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  CAN_TypeDef                 *Instance;  /*!< Register base address          */\r\n\r\n  CAN_InitTypeDef             Init;       /*!< CAN required parameters        */\r\n\r\n  CanTxMsgTypeDef*            pTxMsg;     /*!< Pointer to transmit structure  */\r\n\r\n  CanRxMsgTypeDef*            pRxMsg;     /*!< Pointer to reception structure */\r\n\r\n  __IO HAL_CAN_StateTypeDef   State;      /*!< CAN communication state        */\r\n\r\n  HAL_LockTypeDef             Lock;       /*!< CAN locking object             */\r\n\r\n  __IO uint32_t               ErrorCode;  /*!< CAN Error code                 */\r\n\r\n}CAN_HandleTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup CAN_Exported_Constants CAN Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup HAL_CAN_Error_Code HAL CAN Error Code\r\n  * @{\r\n  */\r\n#define   HAL_CAN_ERROR_NONE      0x00U    /*!< No error             */\r\n#define   HAL_CAN_ERROR_EWG       0x01U    /*!< EWG error            */\r\n#define   HAL_CAN_ERROR_EPV       0x02U    /*!< EPV error            */\r\n#define   HAL_CAN_ERROR_BOF       0x04U    /*!< BOF error            */\r\n#define   HAL_CAN_ERROR_STF       0x08U    /*!< Stuff error          */\r\n#define   HAL_CAN_ERROR_FOR       0x10U    /*!< Form error           */\r\n#define   HAL_CAN_ERROR_ACK       0x20U    /*!< Acknowledgment error */\r\n#define   HAL_CAN_ERROR_BR        0x40U    /*!< Bit recessive        */\r\n#define   HAL_CAN_ERROR_BD        0x80U    /*!< LEC dominant         */\r\n#define   HAL_CAN_ERROR_CRC       0x100U   /*!< LEC transfer error   */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CAN_InitStatus CAN InitStatus\r\n  * @{\r\n  */\r\n#define CAN_INITSTATUS_FAILED       ((uint8_t)0x00U)  /*!< CAN initialization failed */\r\n#define CAN_INITSTATUS_SUCCESS      ((uint8_t)0x01U)  /*!< CAN initialization OK */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CAN_operating_mode CAN Operating Mode\r\n  * @{\r\n  */\r\n#define CAN_MODE_NORMAL             ((uint32_t)0x00000000U)                     /*!< Normal mode   */\r\n#define CAN_MODE_LOOPBACK           ((uint32_t)CAN_BTR_LBKM)                   /*!< Loopback mode */\r\n#define CAN_MODE_SILENT             ((uint32_t)CAN_BTR_SILM)                   /*!< Silent mode   */\r\n#define CAN_MODE_SILENT_LOOPBACK    ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM))  /*!< Loopback combined with silent mode */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CAN_synchronisation_jump_width CAN Synchronisation Jump Width\r\n  * @{\r\n  */\r\n#define CAN_SJW_1TQ                 ((uint32_t)0x00000000U)     /*!< 1 time quantum */\r\n#define CAN_SJW_2TQ                 ((uint32_t)CAN_BTR_SJW_0)  /*!< 2 time quantum */\r\n#define CAN_SJW_3TQ                 ((uint32_t)CAN_BTR_SJW_1)  /*!< 3 time quantum */\r\n#define CAN_SJW_4TQ                 ((uint32_t)CAN_BTR_SJW)    /*!< 4 time quantum */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in bit segment 1\r\n  * @{\r\n  */\r\n#define CAN_BS1_1TQ                 ((uint32_t)0x00000000U)                                       /*!< 1 time quantum  */\r\n#define CAN_BS1_2TQ                 ((uint32_t)CAN_BTR_TS1_0)                                    /*!< 2 time quantum  */\r\n#define CAN_BS1_3TQ                 ((uint32_t)CAN_BTR_TS1_1)                                    /*!< 3 time quantum  */\r\n#define CAN_BS1_4TQ                 ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0))                  /*!< 4 time quantum  */\r\n#define CAN_BS1_5TQ                 ((uint32_t)CAN_BTR_TS1_2)                                    /*!< 5 time quantum  */\r\n#define CAN_BS1_6TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0))                  /*!< 6 time quantum  */\r\n#define CAN_BS1_7TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1))                  /*!< 7 time quantum  */\r\n#define CAN_BS1_8TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 8 time quantum  */\r\n#define CAN_BS1_9TQ                 ((uint32_t)CAN_BTR_TS1_3)                                    /*!< 9 time quantum  */\r\n#define CAN_BS1_10TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0))                  /*!< 10 time quantum */\r\n#define CAN_BS1_11TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1))                  /*!< 11 time quantum */\r\n#define CAN_BS1_12TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 12 time quantum */\r\n#define CAN_BS1_13TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2))                  /*!< 13 time quantum */\r\n#define CAN_BS1_14TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0))  /*!< 14 time quantum */\r\n#define CAN_BS1_15TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1))  /*!< 15 time quantum */\r\n#define CAN_BS1_16TQ                ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2\r\n  * @{\r\n  */\r\n#define CAN_BS2_1TQ                 ((uint32_t)0x00000000U)                       /*!< 1 time quantum */\r\n#define CAN_BS2_2TQ                 ((uint32_t)CAN_BTR_TS2_0)                    /*!< 2 time quantum */\r\n#define CAN_BS2_3TQ                 ((uint32_t)CAN_BTR_TS2_1)                    /*!< 3 time quantum */\r\n#define CAN_BS2_4TQ                 ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0))  /*!< 4 time quantum */\r\n#define CAN_BS2_5TQ                 ((uint32_t)CAN_BTR_TS2_2)                    /*!< 5 time quantum */\r\n#define CAN_BS2_6TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0))  /*!< 6 time quantum */\r\n#define CAN_BS2_7TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1))  /*!< 7 time quantum */\r\n#define CAN_BS2_8TQ                 ((uint32_t)CAN_BTR_TS2)                      /*!< 8 time quantum */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CAN_filter_mode  CAN Filter Mode\r\n  * @{\r\n  */\r\n#define CAN_FILTERMODE_IDMASK       ((uint8_t)0x00U)  /*!< Identifier mask mode */\r\n#define CAN_FILTERMODE_IDLIST       ((uint8_t)0x01U)  /*!< Identifier list mode */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CAN_filter_scale CAN Filter Scale\r\n  * @{\r\n  */\r\n#define CAN_FILTERSCALE_16BIT       ((uint8_t)0x00U)  /*!< Two 16-bit filters */\r\n#define CAN_FILTERSCALE_32BIT       ((uint8_t)0x01U)  /*!< One 32-bit filter  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CAN_filter_FIFO CAN Filter FIFO\r\n  * @{\r\n  */\r\n#define CAN_FILTER_FIFO0             ((uint8_t)0x00U)  /*!< Filter FIFO 0 assignment for filter x */\r\n#define CAN_FILTER_FIFO1             ((uint8_t)0x01U)  /*!< Filter FIFO 1 assignment for filter x */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CAN_Identifier_Type CAN Identifier Type\r\n  * @{\r\n  */\r\n#define CAN_ID_STD             ((uint32_t)0x00000000U)  /*!< Standard Id */\r\n#define CAN_ID_EXT             ((uint32_t)0x00000004U)  /*!< Extended Id */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request\r\n  * @{\r\n  */\r\n#define CAN_RTR_DATA                ((uint32_t)0x00000000U)  /*!< Data frame */\r\n#define CAN_RTR_REMOTE              ((uint32_t)0x00000002U)  /*!< Remote frame */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number Constants\r\n  * @{\r\n  */\r\n#define CAN_FIFO0                   ((uint8_t)0x00U)  /*!< CAN FIFO 0 used to receive */\r\n#define CAN_FIFO1                   ((uint8_t)0x01U)  /*!< CAN FIFO 1 used to receive */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CAN_flags CAN Flags\r\n  * @{\r\n  */\r\n/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()\r\n   and CAN_ClearFlag() functions. */\r\n/* If the flag is 0x1XXXXXXX, it means that it can only be used with\r\n   CAN_GetFlagStatus() function.  */\r\n\r\n/* Transmit Flags */\r\n#define CAN_FLAG_RQCP0             ((uint32_t)0x00000500U)  /*!< Request MailBox0 flag         */\r\n#define CAN_FLAG_RQCP1             ((uint32_t)0x00000508U)  /*!< Request MailBox1 flag         */\r\n#define CAN_FLAG_RQCP2             ((uint32_t)0x00000510U)  /*!< Request MailBox2 flag         */\r\n#define CAN_FLAG_TXOK0             ((uint32_t)0x00000501U)  /*!< Transmission OK MailBox0 flag */\r\n#define CAN_FLAG_TXOK1             ((uint32_t)0x00000509U)  /*!< Transmission OK MailBox1 flag */\r\n#define CAN_FLAG_TXOK2             ((uint32_t)0x00000511U)  /*!< Transmission OK MailBox2 flag */\r\n#define CAN_FLAG_TME0              ((uint32_t)0x0000051AU)  /*!< Transmit mailbox 0 empty flag */\r\n#define CAN_FLAG_TME1              ((uint32_t)0x0000051BU)  /*!< Transmit mailbox 0 empty flag */\r\n#define CAN_FLAG_TME2              ((uint32_t)0x0000051CU)  /*!< Transmit mailbox 0 empty flag */\r\n\r\n/* Receive Flags */\r\n#define CAN_FLAG_FF0               ((uint32_t)0x00000203U)  /*!< FIFO 0 Full flag    */\r\n#define CAN_FLAG_FOV0              ((uint32_t)0x00000204U)  /*!< FIFO 0 Overrun flag */\r\n\r\n#define CAN_FLAG_FF1               ((uint32_t)0x00000403U)  /*!< FIFO 1 Full flag    */\r\n#define CAN_FLAG_FOV1              ((uint32_t)0x00000404U)  /*!< FIFO 1 Overrun flag */\r\n\r\n/* Operating Mode Flags */\r\n#define CAN_FLAG_INAK              ((uint32_t)0x00000100U)  /*!<  Initialization acknowledge flag */\r\n#define CAN_FLAG_SLAK              ((uint32_t)0x00000101U)  /*!< Sleep acknowledge flag */\r\n#define CAN_FLAG_ERRI              ((uint32_t)0x00000102U)  /*!<  Error flag */\r\n#define CAN_FLAG_WKU               ((uint32_t)0x00000103U)  /*!< Wake up flag           */\r\n#define CAN_FLAG_SLAKI             ((uint32_t)0x00000104U)  /*!< Sleep acknowledge flag */\r\n\r\n/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.\r\n         In this case the SLAK bit can be polled.*/\r\n\r\n/* Error Flags */\r\n#define CAN_FLAG_EWG               ((uint32_t)0x00000300U)  /*!< Error warning flag   */\r\n#define CAN_FLAG_EPV               ((uint32_t)0x00000301U)  /*!< Error passive flag   */\r\n#define CAN_FLAG_BOF               ((uint32_t)0x00000302U)  /*!< Bus-Off flag         */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CAN_Interrupts CAN Interrupts\r\n  * @{\r\n  */\r\n#define CAN_IT_TME                  ((uint32_t)CAN_IER_TMEIE)   /*!< Transmit mailbox empty interrupt */\r\n\r\n/* Receive Interrupts */\r\n#define CAN_IT_FMP0                 ((uint32_t)CAN_IER_FMPIE0)  /*!< FIFO 0 message pending interrupt */\r\n#define CAN_IT_FF0                  ((uint32_t)CAN_IER_FFIE0)   /*!< FIFO 0 full interrupt            */\r\n#define CAN_IT_FOV0                 ((uint32_t)CAN_IER_FOVIE0)  /*!< FIFO 0 overrun interrupt         */\r\n#define CAN_IT_FMP1                 ((uint32_t)CAN_IER_FMPIE1)  /*!< FIFO 1 message pending interrupt */\r\n#define CAN_IT_FF1                  ((uint32_t)CAN_IER_FFIE1)   /*!< FIFO 1 full interrupt            */\r\n#define CAN_IT_FOV1                 ((uint32_t)CAN_IER_FOVIE1)  /*!< FIFO 1 overrun interrupt         */\r\n\r\n/* Operating Mode Interrupts */\r\n#define CAN_IT_WKU                  ((uint32_t)CAN_IER_WKUIE)  /*!< Wake-up interrupt           */\r\n#define CAN_IT_SLK                  ((uint32_t)CAN_IER_SLKIE)  /*!< Sleep acknowledge interrupt */\r\n\r\n/* Error Interrupts */\r\n#define CAN_IT_EWG                  ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt   */\r\n#define CAN_IT_EPV                  ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt   */\r\n#define CAN_IT_BOF                  ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt         */\r\n#define CAN_IT_LEC                  ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */\r\n#define CAN_IT_ERR                  ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt           */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CAN_Mailboxes_Definition CAN Mailboxes Definition\r\n  * @{\r\n  */\r\n#define CAN_TXMAILBOX_0   ((uint8_t)0x00U)\r\n#define CAN_TXMAILBOX_1   ((uint8_t)0x01U)\r\n#define CAN_TXMAILBOX_2   ((uint8_t)0x02U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup CAN_Exported_Macros CAN Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief Reset CAN handle state\r\n  * @param  __HANDLE__: specifies the CAN Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)\r\n\r\n/**\r\n  * @brief  Enable the specified CAN interrupts.\r\n  * @param  __HANDLE__: CAN handle\r\n  * @param  __INTERRUPT__: CAN Interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disable the specified CAN interrupts.\r\n  * @param  __HANDLE__: CAN handle\r\n  * @param  __INTERRUPT__: CAN Interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Return the number of pending received messages.\r\n  * @param  __HANDLE__: CAN handle\r\n  * @param  __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.\r\n  * @retval The number of pending message.\r\n  */\r\n#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \\\r\n((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03)))\r\n\r\n/** @brief  Check whether the specified CAN flag is set or not.\r\n  * @param  __HANDLE__: CAN Handle\r\n  * @param  __FLAG__: specifies the flag to check.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag\r\n  *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag\r\n  *            @arg CAN_TSR_RQCP2: Request MailBox2 Flag\r\n  *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag\r\n  *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag\r\n  *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag\r\n  *            @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag\r\n  *            @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag\r\n  *            @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag\r\n  *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag\r\n  *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag\r\n  *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag\r\n  *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag\r\n  *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag\r\n  *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag\r\n  *            @arg CAN_FLAG_WKU: Wake up Flag\r\n  *            @arg CAN_FLAG_SLAK: Sleep acknowledge Flag\r\n  *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag\r\n  *            @arg CAN_FLAG_EWG: Error Warning Flag\r\n  *            @arg CAN_FLAG_EPV: Error Passive Flag\r\n  *            @arg CAN_FLAG_BOF: Bus-Off Flag\r\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \\\r\n((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \\\r\n (((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \\\r\n (((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \\\r\n (((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \\\r\n ((((__HANDLE__)->Instance->ESR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))))\r\n\r\n/** @brief  Clear the specified CAN pending flag.\r\n  * @param  __HANDLE__: CAN Handle.\r\n  * @param  __FLAG__: specifies the flag to check.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag\r\n  *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag\r\n  *            @arg CAN_TSR_RQCP2: Request MailBox2 Flag\r\n  *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag\r\n  *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag\r\n  *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag\r\n  *            @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag\r\n  *            @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag\r\n  *            @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag\r\n  *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag\r\n  *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag\r\n  *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag\r\n  *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag\r\n  *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag\r\n  *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag\r\n  *            @arg CAN_FLAG_WKU: Wake up Flag\r\n  *            @arg CAN_FLAG_SLAK: Sleep acknowledge Flag\r\n  *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag\r\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \\\r\n((((__FLAG__) >> 8) == 5)? (((__HANDLE__)->Instance->TSR) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \\\r\n (((__FLAG__) >> 8) == 2)? (((__HANDLE__)->Instance->RF0R) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \\\r\n (((__FLAG__) >> 8) == 4)? (((__HANDLE__)->Instance->RF1R) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \\\r\n (((__HANDLE__)->Instance->MSR) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))))\r\n\r\n/** @brief  Check if the specified CAN interrupt source is enabled or disabled.\r\n  * @param  __HANDLE__: CAN Handle\r\n  * @param  __INTERRUPT__: specifies the CAN interrupt source to check.\r\n  *          This parameter can be one of the following values:\r\n  *             @arg CAN_IT_TME: Transmit mailbox empty interrupt enable\r\n  *             @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable\r\n  *             @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable\r\n  * @retval The new state of __IT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r\n\r\n/**\r\n  * @brief  Check the transmission status of a CAN Frame.\r\n  * @param  __HANDLE__: CAN Handle\r\n  * @param  __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.\r\n  * @retval The new status of transmission  (TRUE or FALSE).\r\n  */\r\n#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\\\r\n(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\\\r\n ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\\\r\n ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))\r\n\r\n/**\r\n  * @brief  Release the specified receive FIFO.\r\n  * @param  __HANDLE__: CAN handle\r\n  * @param  __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.\r\n  * @retval None\r\n  */\r\n#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \\\r\n((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1))\r\n\r\n/**\r\n  * @brief  Cancel a transmit request.\r\n  * @param  __HANDLE__: CAN Handle\r\n  * @param  __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.\r\n  * @retval None\r\n  */\r\n#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\\\r\n(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\\\r\n ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\\\r\n ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2))\r\n\r\n/**\r\n  * @brief  Enable or disable the DBG Freeze for CAN.\r\n  * @param  __HANDLE__: CAN Handle\r\n  * @param  __NEWSTATE__: new state of the CAN peripheral.\r\n  *          This parameter can be: ENABLE (CAN reception/transmission is frozen\r\n  *          during debug. Reception FIFOs can still be accessed/controlled normally)\r\n  *          or DISABLE (CAN is working during debug).\r\n  * @retval None\r\n  */\r\n#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \\\r\n((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup CAN_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup CAN_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n/* Initialization/de-initialization functions ***********************************/\r\nHAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);\r\nHAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);\r\nHAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);\r\nvoid HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);\r\nvoid HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup CAN_Exported_Functions_Group2\r\n  * @{\r\n  */\r\n/* I/O operation functions ******************************************************/\r\nHAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);\r\nHAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);\r\nHAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);\r\nHAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);\r\nvoid HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);\r\nvoid HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);\r\nvoid HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);\r\nvoid HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup CAN_Exported_Functions_Group3\r\n  * @{\r\n  */\r\n/* Peripheral State functions ***************************************************/\r\nuint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);\r\nHAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/** @defgroup CAN_Private_Types CAN Private Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @defgroup CAN_Private_Variables CAN Private Variables\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup CAN_Private_Constants CAN Private Constants\r\n  * @{\r\n  */\r\n#define CAN_TXSTATUS_NOMAILBOX      ((uint8_t)0x04U)  /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */\r\n#define CAN_FLAG_MASK  ((uint32_t)0x000000FFU)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup CAN_Private_Macros CAN Private Macros\r\n  * @{\r\n  */\r\n#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \\\r\n                           ((MODE) == CAN_MODE_LOOPBACK)|| \\\r\n                           ((MODE) == CAN_MODE_SILENT) || \\\r\n                           ((MODE) == CAN_MODE_SILENT_LOOPBACK))\r\n#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \\\r\n                         ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))\r\n#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)\r\n#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)\r\n#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))\r\n#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)\r\n#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \\\r\n                                  ((MODE) == CAN_FILTERMODE_IDLIST))\r\n#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \\\r\n                                    ((SCALE) == CAN_FILTERSCALE_32BIT))\r\n#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \\\r\n                                  ((FIFO) == CAN_FILTER_FIFO1))\r\n#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)\r\n\r\n#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))\r\n#define IS_CAN_STDID(STDID)   ((STDID) <= ((uint32_t)0x7FF))\r\n#define IS_CAN_EXTID(EXTID)   ((EXTID) <= ((uint32_t)0x1FFFFFFF))\r\n#define IS_CAN_DLC(DLC)       ((DLC) <= ((uint8_t)0x08))\r\n\r\n#define IS_CAN_IDTYPE(IDTYPE)  (((IDTYPE) == CAN_ID_STD) || \\\r\n                                ((IDTYPE) == CAN_ID_EXT))\r\n#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))\r\n#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup CAN_Private_Functions CAN Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_CAN_H */\r\n\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cec.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_cec.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of CEC HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************  \r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_CEC_H\r\n#define __STM32F7xx_HAL_CEC_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup CEC\r\n  * @{\r\n  */\r\n  \r\n/* Exported types ------------------------------------------------------------*/ \r\n/** @defgroup CEC_Exported_Types CEC Exported Types\r\n  * @{\r\n  */\r\n  \r\n/** \r\n  * @brief CEC Init Structure definition  \r\n  */ \r\ntypedef struct\r\n{\r\n  uint32_t SignalFreeTime;               /*!< Set SFT field, specifies the Signal Free Time.\r\n                                              It can be one of @ref CEC_Signal_Free_Time \r\n                                              and belongs to the set {0,...,7} where  \r\n                                              0x0 is the default configuration \r\n                                              else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */\r\n\r\n  uint32_t Tolerance;                    /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,\r\n                                              it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE \r\n                                              or CEC_EXTENDED_TOLERANCE */\r\n\r\n  uint32_t BRERxStop;                    /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception. \r\n                                              CEC_NO_RX_STOP_ON_BRE: reception is not stopped. \r\n                                              CEC_RX_STOP_ON_BRE:    reception is stopped. */\r\n\r\n  uint32_t BREErrorBitGen;               /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the\r\n                                              CEC line upon Bit Rising Error detection.\r\n                                              CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.\r\n                                              CEC_BRE_ERRORBIT_GENERATION:    error-bit generation if BRESTP is set. */\r\n                                              \r\n  uint32_t LBPEErrorBitGen;              /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the\r\n                                              CEC line upon Long Bit Period Error detection.\r\n                                              CEC_LBPE_ERRORBIT_NO_GENERATION:  no error-bit generation. \r\n                                              CEC_LBPE_ERRORBIT_GENERATION:     error-bit generation. */  \r\n                                              \r\n  uint32_t BroadcastMsgNoErrorBitGen;    /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line\r\n                                              upon an error detected on a broadcast message. \r\n                                              \r\n                                              It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:\r\n                                              \r\n                                              1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.\r\n                                                 a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE \r\n                                                    and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.\r\n                                                 b) LBPE detection: error-bit generation on the CEC line \r\n                                                    if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.\r\n                                                    \r\n                                              2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.\r\n                                                 no error-bit generation in case neither a) nor b) are satisfied. Additionally,\r\n                                                 there is no error-bit generation in case of Short Bit Period Error detection in \r\n                                                 a broadcast message while LSTN bit is set. */\r\n \r\n  uint32_t SignalFreeTimeOption;         /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.\r\n                                              CEC_SFT_START_ON_TXSOM SFT:    timer starts when TXSOM is set by software.\r\n                                              CEC_SFT_START_ON_TX_RX_END:  SFT timer starts automatically at the end of message transmission/reception. */\r\n  \r\n  uint32_t ListenMode;                   /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:\r\n  \r\n                                              CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its \r\n                                                own address (OAR). Messages addressed to different destination are ignored. \r\n                                                Broadcast messages are always received.\r\n                                                \r\n                                              CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own \r\n                                                address (OAR) with positive acknowledge. Messages addressed to different destination \r\n                                                are received, but without interfering with the CEC bus: no acknowledge sent.  */\r\n\r\n  uint16_t  OwnAddress;                 /*!< Own addresses configuration\r\n                                             This parameter can be a value of @ref CEC_OWN_ADDRESS */\r\n  \r\n  uint8_t  *RxBuffer;                    /*!< CEC Rx buffer pointeur */\r\n  \r\n\r\n}CEC_InitTypeDef;\r\n\r\n/** \r\n  * @brief HAL CEC State structures definition \r\n  * @note  HAL CEC State value is a combination of 2 different substates: gState and RxState.\r\n  *        - gState contains CEC state information related to global Handle management \r\n  *          and also information related to Tx operations.\r\n  *          gState value coding follow below described bitmap :\r\n  *          b7 (not used)\r\n  *             x  : Should be set to 0\r\n  *          b6  Error information \r\n  *             0  : No Error\r\n  *             1  : Error\r\n  *          b5     IP initilisation status\r\n  *             0  : Reset (IP not initialized)\r\n  *             1  : Init done (IP initialized. HAL CEC Init function already called)\r\n  *          b4-b3  (not used)\r\n  *             xx : Should be set to 00\r\n  *          b2     Intrinsic process state\r\n  *             0  : Ready\r\n  *             1  : Busy (IP busy with some configuration or internal operations)\r\n  *          b1     (not used)\r\n  *             x  : Should be set to 0\r\n  *          b0     Tx state\r\n  *             0  : Ready (no Tx operation ongoing)\r\n  *             1  : Busy (Tx operation ongoing)\r\n  *        - RxState contains information related to Rx operations.\r\n  *          RxState value coding follow below described bitmap :\r\n  *          b7-b6  (not used)\r\n  *             xx : Should be set to 00\r\n  *          b5     IP initilisation status\r\n  *             0  : Reset (IP not initialized)\r\n  *             1  : Init done (IP initialized)\r\n  *          b4-b2  (not used)\r\n  *            xxx : Should be set to 000\r\n  *          b1     Rx state\r\n  *             0  : Ready (no Rx operation ongoing)\r\n  *             1  : Busy (Rx operation ongoing)\r\n  *          b0     (not used)\r\n  *             x  : Should be set to 0.  \r\n  */ \r\ntypedef enum\r\n{\r\n  HAL_CEC_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized \r\n                                                   Value is allowed for gState and RxState             */\r\n  HAL_CEC_STATE_READY             = 0x20U,    /*!< Peripheral Initialized and ready for use\r\n                                                   Value is allowed for gState and RxState             */\r\n  HAL_CEC_STATE_BUSY              = 0x24U,    /*!< an internal process is ongoing\r\n                                                   Value is allowed for gState only                    */\r\n  HAL_CEC_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing\r\n                                                   Value is allowed for RxState only                   */\r\n  HAL_CEC_STATE_BUSY_TX           = 0x21U,    /*!< Data Transmission process is ongoing \r\n                                                   Value is allowed for gState only                    */                                                  \r\n  HAL_CEC_STATE_BUSY_RX_TX        = 0x23U,    /*!< an internal process is ongoing\r\n                                                   Value is allowed for gState only                    */\r\n  HAL_CEC_STATE_ERROR             = 0x60U     /*!< Error Value is allowed for gState only              */\r\n}HAL_CEC_StateTypeDef;\r\n\r\n/** \r\n  * @brief  CEC handle Structure definition  \r\n  */  \r\ntypedef struct\r\n{\r\n  CEC_TypeDef             *Instance;      /*!< CEC registers base address */\r\n  \r\n  CEC_InitTypeDef         Init;           /*!< CEC communication parameters */\r\n  \r\n  uint8_t                 *pTxBuffPtr;    /*!< Pointer to CEC Tx transfer Buffer */\r\n  \r\n  uint16_t                TxXferCount;    /*!< CEC Tx Transfer Counter */\r\n  \r\n  uint16_t                RxXferSize;     /*!< CEC Rx Transfer size, 0: header received only */\r\n  \r\n  HAL_LockTypeDef         Lock;           /*!< Locking object */\r\n\r\n  HAL_CEC_StateTypeDef    gState;         /*!< CEC state information related to global Handle management \r\n                                               and also related to Tx operations.\r\n                                               This parameter can be a value of @ref HAL_CEC_StateTypeDef */\r\n  \r\n  HAL_CEC_StateTypeDef    RxState;        /*!< CEC state information related to Rx operations.\r\n                                               This parameter can be a value of @ref HAL_CEC_StateTypeDef */\r\n  \r\n  uint32_t                ErrorCode;      /*!< For errors handling purposes, copy of ISR register \r\n                                               in case error is reported */    \r\n}CEC_HandleTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup CEC_Exported_Constants CEC Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CEC_Error_Code CEC Error Code\r\n  * @{\r\n  */ \r\n#define HAL_CEC_ERROR_NONE    (uint32_t) 0x0000U     /*!< no error                      */\r\n#define HAL_CEC_ERROR_RXOVR   CEC_ISR_RXOVR          /*!< CEC Rx-Overrun                */\r\n#define HAL_CEC_ERROR_BRE     CEC_ISR_BRE            /*!< CEC Rx Bit Rising Error       */\r\n#define HAL_CEC_ERROR_SBPE    CEC_ISR_SBPE           /*!< CEC Rx Short Bit period Error */\r\n#define HAL_CEC_ERROR_LBPE    CEC_ISR_LBPE           /*!< CEC Rx Long Bit period Error  */\r\n#define HAL_CEC_ERROR_RXACKE  CEC_ISR_RXACKE         /*!< CEC Rx Missing Acknowledge    */\r\n#define HAL_CEC_ERROR_ARBLST  CEC_ISR_ARBLST         /*!< CEC Arbitration Lost          */\r\n#define HAL_CEC_ERROR_TXUDR   CEC_ISR_TXUDR          /*!< CEC Tx-Buffer Underrun        */\r\n#define HAL_CEC_ERROR_TXERR   CEC_ISR_TXERR          /*!< CEC Tx-Error                  */\r\n#define HAL_CEC_ERROR_TXACKE  CEC_ISR_TXACKE         /*!< CEC Tx Missing Acknowledge    */\r\n/**\r\n  * @}\r\n  */\r\n       \r\n/** @defgroup CEC_Signal_Free_Time  CEC Signal Free Time setting parameter\r\n  * @{\r\n  */\r\n#define CEC_DEFAULT_SFT                    ((uint32_t)0x00000000U)\r\n#define CEC_0_5_BITPERIOD_SFT              ((uint32_t)0x00000001U)\r\n#define CEC_1_5_BITPERIOD_SFT              ((uint32_t)0x00000002U)\r\n#define CEC_2_5_BITPERIOD_SFT              ((uint32_t)0x00000003U)\r\n#define CEC_3_5_BITPERIOD_SFT              ((uint32_t)0x00000004U)\r\n#define CEC_4_5_BITPERIOD_SFT              ((uint32_t)0x00000005U)\r\n#define CEC_5_5_BITPERIOD_SFT              ((uint32_t)0x00000006U)\r\n#define CEC_6_5_BITPERIOD_SFT              ((uint32_t)0x00000007U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CEC_Tolerance CEC Receiver Tolerance\r\n  * @{\r\n  */\r\n#define CEC_STANDARD_TOLERANCE             ((uint32_t)0x00000000U)\r\n#define CEC_EXTENDED_TOLERANCE             ((uint32_t)CEC_CFGR_RXTOL)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup CEC_BRERxStop CEC Reception Stop on Error\r\n  * @{\r\n  */\r\n#define CEC_NO_RX_STOP_ON_BRE             ((uint32_t)0x00000000U)\r\n#define CEC_RX_STOP_ON_BRE                ((uint32_t)CEC_CFGR_BRESTP)\r\n/**\r\n  * @}\r\n  */            \r\n             \r\n/** @defgroup CEC_BREErrorBitGen  CEC Error Bit Generation if Bit Rise Error reported\r\n  * @{\r\n  */ \r\n#define CEC_BRE_ERRORBIT_NO_GENERATION     ((uint32_t)0x00000000U)\r\n#define CEC_BRE_ERRORBIT_GENERATION        ((uint32_t)CEC_CFGR_BREGEN)\r\n/**\r\n  * @}\r\n  */ \r\n                        \r\n/** @defgroup CEC_LBPEErrorBitGen  CEC Error Bit Generation if Long Bit Period Error reported\r\n  * @{\r\n  */ \r\n#define CEC_LBPE_ERRORBIT_NO_GENERATION     ((uint32_t)0x00000000U)\r\n#define CEC_LBPE_ERRORBIT_GENERATION        ((uint32_t)CEC_CFGR_LBPEGEN)\r\n/**\r\n  * @}\r\n  */    \r\n\r\n/** @defgroup CEC_BroadCastMsgErrorBitGen  CEC Error Bit Generation on Broadcast message\r\n  * @{\r\n  */ \r\n#define CEC_BROADCASTERROR_ERRORBIT_GENERATION     ((uint32_t)0x00000000U)\r\n#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION  ((uint32_t)CEC_CFGR_BRDNOGEN)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup CEC_SFT_Option     CEC Signal Free Time start option\r\n  * @{\r\n  */ \r\n#define CEC_SFT_START_ON_TXSOM           ((uint32_t)0x00000000U)\r\n#define CEC_SFT_START_ON_TX_RX_END       ((uint32_t)CEC_CFGR_SFTOPT)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup CEC_Listening_Mode    CEC Listening mode option\r\n  * @{\r\n  */ \r\n#define CEC_REDUCED_LISTENING_MODE          ((uint32_t)0x00000000U)\r\n#define CEC_FULL_LISTENING_MODE             ((uint32_t)CEC_CFGR_LSTN)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup CEC_OAR_Position   CEC Device Own Address position in CEC CFGR register     \r\n  * @{\r\n  */\r\n#define CEC_CFGR_OAR_LSB_POS            ((uint32_t) 16U)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup CEC_Initiator_Position   CEC Initiator logical address position in message header     \r\n  * @{\r\n  */\r\n#define CEC_INITIATOR_LSB_POS           ((uint32_t) 4U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CEC_OWN_ADDRESS   CEC Own Address    \r\n  * @{\r\n  */\r\n#define CEC_OWN_ADDRESS_NONE           ((uint16_t) 0x0000U)   /* Reset value */\r\n#define CEC_OWN_ADDRESS_0              ((uint16_t) 0x0001U)   /* Logical Address 0 */\r\n#define CEC_OWN_ADDRESS_1              ((uint16_t) 0x0002U)   /* Logical Address 1 */\r\n#define CEC_OWN_ADDRESS_2              ((uint16_t) 0x0004U)   /* Logical Address 2 */\r\n#define CEC_OWN_ADDRESS_3              ((uint16_t) 0x0008U)   /* Logical Address 3 */\r\n#define CEC_OWN_ADDRESS_4              ((uint16_t) 0x0010U)   /* Logical Address 4 */\r\n#define CEC_OWN_ADDRESS_5              ((uint16_t) 0x0020U)   /* Logical Address 5 */\r\n#define CEC_OWN_ADDRESS_6              ((uint16_t) 0x0040U)   /* Logical Address 6 */\r\n#define CEC_OWN_ADDRESS_7              ((uint16_t) 0x0080U)   /* Logical Address 7 */\r\n#define CEC_OWN_ADDRESS_8              ((uint16_t) 0x0100U)   /* Logical Address 9 */\r\n#define CEC_OWN_ADDRESS_9              ((uint16_t) 0x0200U)   /* Logical Address 10 */\r\n#define CEC_OWN_ADDRESS_10             ((uint16_t) 0x0400U)   /* Logical Address 11 */\r\n#define CEC_OWN_ADDRESS_11             ((uint16_t) 0x0800U)   /* Logical Address 12 */\r\n#define CEC_OWN_ADDRESS_12             ((uint16_t) 0x1000U)   /* Logical Address 13 */\r\n#define CEC_OWN_ADDRESS_13             ((uint16_t) 0x2000U)   /* Logical Address 14 */\r\n#define CEC_OWN_ADDRESS_14             ((uint16_t) 0x4000U)   /* Logical Address 15 */\r\n/**\r\n  * @}\r\n  */\r\n    \r\n/** @defgroup CEC_Interrupts_Definitions  CEC Interrupts definition\r\n  * @{\r\n  */\r\n#define CEC_IT_TXACKE                   CEC_IER_TXACKEIE\r\n#define CEC_IT_TXERR                    CEC_IER_TXERRIE\r\n#define CEC_IT_TXUDR                    CEC_IER_TXUDRIE\r\n#define CEC_IT_TXEND                    CEC_IER_TXENDIE\r\n#define CEC_IT_TXBR                     CEC_IER_TXBRIE\r\n#define CEC_IT_ARBLST                   CEC_IER_ARBLSTIE\r\n#define CEC_IT_RXACKE                   CEC_IER_RXACKEIE\r\n#define CEC_IT_LBPE                     CEC_IER_LBPEIE\r\n#define CEC_IT_SBPE                     CEC_IER_SBPEIE\r\n#define CEC_IT_BRE                      CEC_IER_BREIE\r\n#define CEC_IT_RXOVR                    CEC_IER_RXOVRIE\r\n#define CEC_IT_RXEND                    CEC_IER_RXENDIE\r\n#define CEC_IT_RXBR                     CEC_IER_RXBRIE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CEC_Flags_Definitions  CEC Flags definition\r\n  * @{\r\n  */\r\n#define CEC_FLAG_TXACKE                 CEC_ISR_TXACKE\r\n#define CEC_FLAG_TXERR                  CEC_ISR_TXERR\r\n#define CEC_FLAG_TXUDR                  CEC_ISR_TXUDR\r\n#define CEC_FLAG_TXEND                  CEC_ISR_TXEND\r\n#define CEC_FLAG_TXBR                   CEC_ISR_TXBR\r\n#define CEC_FLAG_ARBLST                 CEC_ISR_ARBLST\r\n#define CEC_FLAG_RXACKE                 CEC_ISR_RXACKE\r\n#define CEC_FLAG_LBPE                   CEC_ISR_LBPE\r\n#define CEC_FLAG_SBPE                   CEC_ISR_SBPE\r\n#define CEC_FLAG_BRE                    CEC_ISR_BRE\r\n#define CEC_FLAG_RXOVR                  CEC_ISR_RXOVR\r\n#define CEC_FLAG_RXEND                  CEC_ISR_RXEND\r\n#define CEC_FLAG_RXBR                   CEC_ISR_RXBR\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags \r\n  * @{\r\n  */\r\n#define CEC_ISR_ALL_ERROR              ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\\\r\n                                                  CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag \r\n  * @{\r\n  */\r\n#define CEC_IER_RX_ALL_ERR              ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag \r\n  * @{\r\n  */\r\n#define CEC_IER_TX_ALL_ERR              ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */  \r\n  \r\n/* Exported macros -----------------------------------------------------------*/\r\n/** @defgroup CEC_Exported_Macros CEC Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief  Reset CEC handle gstate & RxState\r\n  * @param  __HANDLE__: CEC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{                                                   \\\r\n                                                       (__HANDLE__)->gState = HAL_CEC_STATE_RESET;     \\\r\n                                                       (__HANDLE__)->RxState = HAL_CEC_STATE_RESET;    \\\r\n                                                     } while(0)\r\n\r\n/** @brief  Checks whether or not the specified CEC interrupt flag is set.\r\n  * @param  __HANDLE__: specifies the CEC Handle.\r\n  * @param  __FLAG__: specifies the flag to check.\r\n  *            @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error\r\n  *            @arg CEC_FLAG_TXERR: Tx Error.\r\n  *            @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.\r\n  *            @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).\r\n  *            @arg CEC_FLAG_TXBR: Tx-Byte Request.\r\n  *            @arg CEC_FLAG_ARBLST: Arbitration Lost\r\n  *            @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge \r\n  *            @arg CEC_FLAG_LBPE: Rx Long period Error\r\n  *            @arg CEC_FLAG_SBPE: Rx Short period Error\r\n  *            @arg CEC_FLAG_BRE: Rx Bit Rising Error\r\n  *            @arg CEC_FLAG_RXOVR: Rx Overrun.\r\n  *            @arg CEC_FLAG_RXEND: End Of Reception.\r\n  *            @arg CEC_FLAG_RXBR: Rx-Byte Received.      \r\n  * @retval ITStatus\r\n  */\r\n#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->ISR & (__FLAG__)) \r\n\r\n/** @brief  Clears the interrupt or status flag when raised (write at 1)\r\n  * @param  __HANDLE__: specifies the CEC Handle.\r\n  * @param  __FLAG__: specifies the interrupt/status flag to clear.\r\n  *        This parameter can be one of the following values:\r\n  *            @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error\r\n  *            @arg CEC_FLAG_TXERR: Tx Error.\r\n  *            @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.\r\n  *            @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).\r\n  *            @arg CEC_FLAG_TXBR: Tx-Byte Request.\r\n  *            @arg CEC_FLAG_ARBLST: Arbitration Lost\r\n  *            @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge \r\n  *            @arg CEC_FLAG_LBPE: Rx Long period Error\r\n  *            @arg CEC_FLAG_SBPE: Rx Short period Error\r\n  *            @arg CEC_FLAG_BRE: Rx Bit Rising Error\r\n  *            @arg CEC_FLAG_RXOVR: Rx Overrun.\r\n  *            @arg CEC_FLAG_RXEND: End Of Reception.\r\n  *            @arg CEC_FLAG_RXBR: Rx-Byte Received. \r\n  * @retval none  \r\n  */\r\n#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \r\n\r\n/** @brief  Enables the specified CEC interrupt.\r\n  * @param  __HANDLE__: specifies the CEC Handle.\r\n  * @param  __INTERRUPT__: specifies the CEC interrupt to enable.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable \r\n  *            @arg CEC_IT_TXERR: Tx Error IT Enable \r\n  *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable \r\n  *            @arg CEC_IT_TXEND: End of transmission IT Enable \r\n  *            @arg CEC_IT_TXBR: Tx-Byte Request IT Enable \r\n  *            @arg CEC_IT_ARBLST: Arbitration Lost IT Enable \r\n  *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable \r\n  *            @arg CEC_IT_LBPE: Rx Long period Error IT Enable \r\n  *            @arg CEC_IT_SBPE: Rx Short period Error IT Enable \r\n  *            @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable \r\n  *            @arg CEC_IT_RXOVR: Rx Overrun IT Enable \r\n  *            @arg CEC_IT_RXEND: End Of Reception IT Enable \r\n  *            @arg CEC_IT_RXBR: Rx-Byte Received IT Enable                          \r\n  * @retval none\r\n  */\r\n#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))  \r\n\r\n/** @brief  Disables the specified CEC interrupt.\r\n  * @param  __HANDLE__: specifies the CEC Handle.\r\n  * @param  __INTERRUPT__: specifies the CEC interrupt to disable.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable \r\n  *            @arg CEC_IT_TXERR: Tx Error IT Enable \r\n  *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable \r\n  *            @arg CEC_IT_TXEND: End of transmission IT Enable \r\n  *            @arg CEC_IT_TXBR: Tx-Byte Request IT Enable \r\n  *            @arg CEC_IT_ARBLST: Arbitration Lost IT Enable \r\n  *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable \r\n  *            @arg CEC_IT_LBPE: Rx Long period Error IT Enable \r\n  *            @arg CEC_IT_SBPE: Rx Short period Error IT Enable \r\n  *            @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable \r\n  *            @arg CEC_IT_RXOVR: Rx Overrun IT Enable \r\n  *            @arg CEC_IT_RXEND: End Of Reception IT Enable \r\n  *            @arg CEC_IT_RXBR: Rx-Byte Received IT Enable                   \r\n  * @retval none\r\n  */   \r\n#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))  \r\n\r\n/** @brief  Checks whether or not the specified CEC interrupt is enabled.\r\n  * @param  __HANDLE__: specifies the CEC Handle.\r\n  * @param  __INTERRUPT__: specifies the CEC interrupt to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable \r\n  *            @arg CEC_IT_TXERR: Tx Error IT Enable \r\n  *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable \r\n  *            @arg CEC_IT_TXEND: End of transmission IT Enable \r\n  *            @arg CEC_IT_TXBR: Tx-Byte Request IT Enable \r\n  *            @arg CEC_IT_ARBLST: Arbitration Lost IT Enable \r\n  *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable \r\n  *            @arg CEC_IT_LBPE: Rx Long period Error IT Enable \r\n  *            @arg CEC_IT_SBPE: Rx Short period Error IT Enable \r\n  *            @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable \r\n  *            @arg CEC_IT_RXOVR: Rx Overrun IT Enable \r\n  *            @arg CEC_IT_RXEND: End Of Reception IT Enable \r\n  *            @arg CEC_IT_RXBR: Rx-Byte Received IT Enable                  \r\n  * @retval FlagStatus  \r\n  */\r\n#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))\r\n\r\n/** @brief  Enables the CEC device\r\n  * @param  __HANDLE__: specifies the CEC Handle.               \r\n  * @retval none \r\n  */\r\n#define __HAL_CEC_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR |=  CEC_CR_CECEN)\r\n\r\n/** @brief  Disables the CEC device\r\n  * @param  __HANDLE__: specifies the CEC Handle.               \r\n  * @retval none \r\n  */\r\n#define __HAL_CEC_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR &=  ~CEC_CR_CECEN)\r\n\r\n/** @brief  Set Transmission Start flag\r\n  * @param  __HANDLE__: specifies the CEC Handle.               \r\n  * @retval none \r\n  */\r\n#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__)        ((__HANDLE__)->Instance->CR |=  CEC_CR_TXSOM)\r\n\r\n/** @brief  Set Transmission End flag\r\n  * @param  __HANDLE__: specifies the CEC Handle.               \r\n  * @retval none \r\n  * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.  \r\n  */\r\n#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__)         ((__HANDLE__)->Instance->CR |=  CEC_CR_TXEOM)\r\n\r\n/** @brief  Get Transmission Start flag\r\n  * @param  __HANDLE__: specifies the CEC Handle.               \r\n  * @retval FlagStatus \r\n  */\r\n#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)\r\n\r\n/** @brief  Get Transmission End flag\r\n  * @param  __HANDLE__: specifies the CEC Handle.               \r\n  * @retval FlagStatus \r\n  */\r\n#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__)   ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)   \r\n\r\n/** @brief  Clear OAR register\r\n  * @param  __HANDLE__: specifies the CEC Handle.               \r\n  * @retval none \r\n  */\r\n#define __HAL_CEC_CLEAR_OAR(__HANDLE__)   CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)\r\n\r\n/** @brief  Set OAR register (without resetting previously set address in case of multi-address mode)\r\n  *          To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand\r\n  * @param  __HANDLE__: specifies the CEC Handle. \r\n  * @param  __ADDRESS__: Own Address value (CEC logical address is identified by bit position)                   \r\n  * @retval none \r\n  */\r\n#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__)   SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)\r\n\r\n/**\r\n  * @}\r\n  */                       \r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup CEC_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup CEC_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n/* Initialization and de-initialization functions  ****************************/\r\nHAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);\r\nHAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);\r\nHAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);\r\nvoid HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);\r\nvoid HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup CEC_Exported_Functions_Group2\r\n  * @{\r\n  */\r\n/* I/O operation functions  ***************************************************/\r\nHAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);\r\nuint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);\r\nvoid HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer);\r\nvoid HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);\r\nvoid HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);\r\nvoid HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);\r\nvoid HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup CEC_Exported_Functions_Group3\r\n  * @{\r\n  */\r\n/* Peripheral State functions  ************************************************/\r\nHAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);\r\nuint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Private types -------------------------------------------------------------*/\r\n/** @defgroup CEC_Private_Types CEC Private Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @defgroup CEC_Private_Variables CEC Private Variables\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup CEC_Private_Constants CEC Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup CEC_Private_Macros CEC Private Macros\r\n  * @{\r\n  */\r\n  \r\n#define IS_CEC_SIGNALFREETIME(__SFT__)     ((__SFT__) <= CEC_CFGR_SFT)  \r\n\r\n#define IS_CEC_TOLERANCE(__RXTOL__)        (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \\\r\n                                            ((__RXTOL__) == CEC_EXTENDED_TOLERANCE))\r\n                                            \r\n#define IS_CEC_BRERXSTOP(__BRERXSTOP__)   (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \\\r\n                                           ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))\r\n                                           \r\n#define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \\\r\n                                                ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))\r\n\r\n#define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \\\r\n                                                 ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))\r\n                                                 \r\n#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \\\r\n                                                                       ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))\r\n                                                                       \r\n#define IS_CEC_SFTOP(__SFTOP__)          (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \\\r\n                                          ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))\r\n                                          \r\n#define IS_CEC_LISTENING_MODE(__MODE__)     (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \\\r\n                                             ((__MODE__) == CEC_FULL_LISTENING_MODE))\r\n\r\n/** @brief Check CEC message size.\r\n  *       The message size is the payload size: without counting the header, \r\n  *       it varies from 0 byte (ping operation, one header only, no payload) to \r\n  *       15 bytes (1 opcode and up to 14 operands following the header). \r\n  * @param  __SIZE__: CEC message size.               \r\n  * @retval Test result (TRUE or FALSE).\r\n  */\r\n#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10)  \r\n                                                 \r\n/** @brief Check CEC device Own Address Register (OAR) setting.\r\n  *        OAR address is written in a 15-bit field within CEC_CFGR register. \r\n  * @param  __ADDRESS__: CEC own address.               \r\n  * @retval Test result (TRUE or FALSE).\r\n  */\r\n#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFF)\r\n\r\n/** @brief Check CEC initiator or destination logical address setting.\r\n  *        Initiator and destination addresses are coded over 4 bits. \r\n  * @param  __ADDRESS__: CEC initiator or logical address.               \r\n  * @retval Test result (TRUE or FALSE).\r\n  */\r\n#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF) \r\n/**\r\n  * @}\r\n  */\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup CEC_Private_Functions CEC Private Functions\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_CEC_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_conf_template.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_conf_template.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   HAL configuration template file. \r\n  *          This file should be copied to the application folder and renamed\r\n  *          to stm32f7xx_hal_conf.h.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_CONF_H\r\n#define __STM32F7xx_HAL_CONF_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/* ########################## Module Selection ############################## */\r\n/**\r\n  * @brief This is the list of modules to be used in the HAL driver \r\n  */\r\n#define HAL_MODULE_ENABLED  \r\n#define HAL_ADC_MODULE_ENABLED  \r\n#define HAL_CAN_MODULE_ENABLED\r\n#define HAL_CEC_MODULE_ENABLED  \r\n#define HAL_CRC_MODULE_ENABLED  \r\n#define HAL_CRYP_MODULE_ENABLED  \r\n#define HAL_DAC_MODULE_ENABLED  \r\n#define HAL_DCMI_MODULE_ENABLED \r\n#define HAL_DMA_MODULE_ENABLED\r\n#define HAL_DMA2D_MODULE_ENABLED \r\n#define HAL_ETH_MODULE_ENABLED \r\n#define HAL_FLASH_MODULE_ENABLED \r\n#define HAL_NAND_MODULE_ENABLED\r\n#define HAL_NOR_MODULE_ENABLED\r\n#define HAL_SRAM_MODULE_ENABLED\r\n#define HAL_SDRAM_MODULE_ENABLED\r\n#define HAL_HASH_MODULE_ENABLED  \r\n#define HAL_GPIO_MODULE_ENABLED\r\n#define HAL_I2C_MODULE_ENABLED\r\n#define HAL_I2S_MODULE_ENABLED   \r\n#define HAL_IWDG_MODULE_ENABLED \r\n#define HAL_LPTIM_MODULE_ENABLED\r\n#define HAL_LTDC_MODULE_ENABLED \r\n#define HAL_PWR_MODULE_ENABLED\r\n#define HAL_QSPI_MODULE_ENABLED   \r\n#define HAL_RCC_MODULE_ENABLED \r\n#define HAL_RNG_MODULE_ENABLED   \r\n#define HAL_RTC_MODULE_ENABLED\r\n#define HAL_SAI_MODULE_ENABLED   \r\n#define HAL_SD_MODULE_ENABLED  \r\n#define HAL_SPDIFRX_MODULE_ENABLED\r\n#define HAL_SPI_MODULE_ENABLED   \r\n#define HAL_TIM_MODULE_ENABLED   \r\n#define HAL_UART_MODULE_ENABLED \r\n#define HAL_USART_MODULE_ENABLED \r\n#define HAL_IRDA_MODULE_ENABLED \r\n#define HAL_SMARTCARD_MODULE_ENABLED \r\n#define HAL_WWDG_MODULE_ENABLED  \r\n#define HAL_CORTEX_MODULE_ENABLED\r\n#define HAL_PCD_MODULE_ENABLED\r\n#define HAL_HCD_MODULE_ENABLED\r\n#define HAL_DFSDM_MODULE_ENABLED\r\n#define HAL_DSI_MODULE_ENABLED\r\n#define HAL_JPEG_MODULE_ENABLED\r\n#define HAL_MDIOS_MODULE_ENABLED\r\n\r\n\r\n/* ########################## HSE/HSI Values adaptation ##################### */\r\n/**\r\n  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.\r\n  *        This value is used by the RCC HAL module to compute the system frequency\r\n  *        (when HSE is used as system clock source, directly or through the PLL).  \r\n  */\r\n#if !defined  (HSE_VALUE) \r\n  #define HSE_VALUE    25000000U /*!< Value of the External oscillator in Hz */\r\n#endif /* HSE_VALUE */\r\n\r\n#if !defined  (HSE_STARTUP_TIMEOUT)\r\n  #define HSE_STARTUP_TIMEOUT    100U   /*!< Time out for HSE start up, in ms */\r\n#endif /* HSE_STARTUP_TIMEOUT */\r\n\r\n/**\r\n  * @brief Internal High Speed oscillator (HSI) value.\r\n  *        This value is used by the RCC HAL module to compute the system frequency\r\n  *        (when HSI is used as system clock source, directly or through the PLL). \r\n  */\r\n#if !defined  (HSI_VALUE)\r\n  #define HSI_VALUE    16000000U /*!< Value of the Internal oscillator in Hz*/\r\n#endif /* HSI_VALUE */\r\n\r\n/**\r\n  * @brief Internal Low Speed oscillator (LSI) value.\r\n  */\r\n#if !defined  (LSI_VALUE) \r\n #define LSI_VALUE  32000U                  /*!< LSI Typical Value in Hz*/\r\n#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz\r\n                                             The real value may vary depending on the variations\r\n                                             in voltage and temperature.  */\r\n/**\r\n  * @brief External Low Speed oscillator (LSE) value.\r\n  */\r\n#if !defined  (LSE_VALUE)\r\n #define LSE_VALUE  32768U    /*!< Value of the External Low Speed oscillator in Hz */\r\n#endif /* LSE_VALUE */\r\n\r\n#if !defined  (LSE_STARTUP_TIMEOUT)\r\n  #define LSE_STARTUP_TIMEOUT    5000U   /*!< Time out for LSE start up, in ms */\r\n#endif /* LSE_STARTUP_TIMEOUT */\r\n\r\n/**\r\n  * @brief External clock source for I2S peripheral\r\n  *        This value is used by the I2S HAL module to compute the I2S clock source \r\n  *        frequency, this source is inserted directly through I2S_CKIN pad. \r\n  */\r\n#if !defined  (EXTERNAL_CLOCK_VALUE)\r\n  #define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the Internal oscillator in Hz*/\r\n#endif /* EXTERNAL_CLOCK_VALUE */\r\n\r\n/* Tip: To avoid modifying this file each time you need to use different HSE,\r\n   ===  you can define the HSE value in your toolchain compiler preprocessor. */\r\n\r\n/* ########################### System Configuration ######################### */\r\n/**\r\n  * @brief This is the HAL system configuration section\r\n  */     \r\n#define  VDD_VALUE                    3300U /*!< Value of VDD in mv */\r\n#define  TICK_INT_PRIORITY            0x0FU /*!< tick interrupt priority */\r\n#define  USE_RTOS                     0U\r\n#define  PREFETCH_ENABLE              1U\r\n#define  ART_ACCLERATOR_ENABLE        1U /* To enable instruction cache and prefetch */\r\n\r\n/* ########################## Assert Selection ############################## */\r\n/**\r\n  * @brief Uncomment the line below to expanse the \"assert_param\" macro in the \r\n  *        HAL drivers code\r\n  */\r\n/* #define USE_FULL_ASSERT    1 */\r\n\r\n/* ################## Ethernet peripheral configuration ##################### */\r\n\r\n/* Section 1 : Ethernet peripheral configuration */\r\n\r\n/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */\r\n#define MAC_ADDR0   2U\r\n#define MAC_ADDR1   0U\r\n#define MAC_ADDR2   0U\r\n#define MAC_ADDR3   0U\r\n#define MAC_ADDR4   0U\r\n#define MAC_ADDR5   0U\r\n\r\n/* Definition of the Ethernet driver buffers size and count */   \r\n#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */\r\n#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */\r\n#define ETH_RXBUFNB                    4U       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */\r\n#define ETH_TXBUFNB                    4U       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */\r\n\r\n/* Section 2: PHY configuration section */\r\n\r\n/* DP83848 PHY Address*/ \r\n#define DP83848_PHY_ADDRESS             0x01U\r\n/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ \r\n#define PHY_RESET_DELAY                 0x000000FFU\r\n/* PHY Configuration delay */\r\n#define PHY_CONFIG_DELAY                0x00000FFFU\r\n\r\n#define PHY_READ_TO                     0x0000FFFFU\r\n#define PHY_WRITE_TO                    0x0000FFFFU\r\n\r\n/* Section 3: Common PHY Registers */\r\n\r\n#define PHY_BCR                         ((uint16_t)0x00U)    /*!< Transceiver Basic Control Register   */\r\n#define PHY_BSR                         ((uint16_t)0x01U)    /*!< Transceiver Basic Status Register    */\r\n \r\n#define PHY_RESET                       ((uint16_t)0x8000U)  /*!< PHY Reset */\r\n#define PHY_LOOPBACK                    ((uint16_t)0x4000U)  /*!< Select loop-back mode */\r\n#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100U)  /*!< Set the full-duplex mode at 100 Mb/s */\r\n#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000U)  /*!< Set the half-duplex mode at 100 Mb/s */\r\n#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100U)  /*!< Set the full-duplex mode at 10 Mb/s  */\r\n#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000U)  /*!< Set the half-duplex mode at 10 Mb/s  */\r\n#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000U)  /*!< Enable auto-negotiation function     */\r\n#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200U)  /*!< Restart auto-negotiation function    */\r\n#define PHY_POWERDOWN                   ((uint16_t)0x0800U)  /*!< Select the power down mode           */\r\n#define PHY_ISOLATE                     ((uint16_t)0x0400U)  /*!< Isolate PHY from MII                 */\r\n\r\n#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020U)  /*!< Auto-Negotiation process completed   */\r\n#define PHY_LINKED_STATUS               ((uint16_t)0x0004U)  /*!< Valid link established               */\r\n#define PHY_JABBER_DETECTION            ((uint16_t)0x0002U)  /*!< Jabber condition detected            */\r\n  \r\n/* Section 4: Extended PHY Registers */\r\n\r\n#define PHY_SR                          ((uint16_t)0x10U)    /*!< PHY status register Offset                      */\r\n#define PHY_MICR                        ((uint16_t)0x11U)    /*!< MII Interrupt Control Register                  */\r\n#define PHY_MISR                        ((uint16_t)0x12U)    /*!< MII Interrupt Status and Misc. Control Register */\r\n \r\n#define PHY_LINK_STATUS                 ((uint16_t)0x0001U)  /*!< PHY Link mask                                   */\r\n#define PHY_SPEED_STATUS                ((uint16_t)0x0002U)  /*!< PHY Speed mask                                  */\r\n#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004U)  /*!< PHY Duplex mask                                 */\r\n\r\n#define PHY_MICR_INT_EN                 ((uint16_t)0x0002U)  /*!< PHY Enable interrupts                           */\r\n#define PHY_MICR_INT_OE                 ((uint16_t)0x0001U)  /*!< PHY Enable output interrupt events              */\r\n\r\n#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020U)  /*!< Enable Interrupt on change of link status       */\r\n#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000U)  /*!< PHY link status interrupt mask                  */\r\n\r\n/* ################## SPI peripheral configuration ########################## */\r\n\r\n/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver\r\n* Activated: CRC code is present inside driver\r\n* Deactivated: CRC code cleaned from driver\r\n*/\r\n\r\n#define USE_SPI_CRC                     1U\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n/**\r\n  * @brief Include module's header file \r\n  */\r\n\r\n#ifdef HAL_RCC_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_rcc.h\"\r\n#endif /* HAL_RCC_MODULE_ENABLED */\r\n\r\n#ifdef HAL_GPIO_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_gpio.h\"\r\n#endif /* HAL_GPIO_MODULE_ENABLED */\r\n\r\n#ifdef HAL_DMA_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_dma.h\"\r\n#endif /* HAL_DMA_MODULE_ENABLED */\r\n   \r\n#ifdef HAL_CORTEX_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_cortex.h\"\r\n#endif /* HAL_CORTEX_MODULE_ENABLED */\r\n\r\n#ifdef HAL_ADC_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_adc.h\"\r\n#endif /* HAL_ADC_MODULE_ENABLED */\r\n\r\n#ifdef HAL_CAN_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_can.h\"\r\n#endif /* HAL_CAN_MODULE_ENABLED */\r\n\r\n#ifdef HAL_CEC_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_cec.h\"\r\n#endif /* HAL_CEC_MODULE_ENABLED */\r\n\r\n#ifdef HAL_CRC_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_crc.h\"\r\n#endif /* HAL_CRC_MODULE_ENABLED */\r\n\r\n#ifdef HAL_CRYP_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_cryp.h\" \r\n#endif /* HAL_CRYP_MODULE_ENABLED */\r\n\r\n#ifdef HAL_DMA2D_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_dma2d.h\"\r\n#endif /* HAL_DMA2D_MODULE_ENABLED */\r\n\r\n#ifdef HAL_DAC_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_dac.h\"\r\n#endif /* HAL_DAC_MODULE_ENABLED */\r\n\r\n#ifdef HAL_DCMI_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_dcmi.h\"\r\n#endif /* HAL_DCMI_MODULE_ENABLED */\r\n\r\n#ifdef HAL_ETH_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_eth.h\"\r\n#endif /* HAL_ETH_MODULE_ENABLED */\r\n\r\n#ifdef HAL_FLASH_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_flash.h\"\r\n#endif /* HAL_FLASH_MODULE_ENABLED */\r\n \r\n#ifdef HAL_SRAM_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_sram.h\"\r\n#endif /* HAL_SRAM_MODULE_ENABLED */\r\n\r\n#ifdef HAL_NOR_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_nor.h\"\r\n#endif /* HAL_NOR_MODULE_ENABLED */\r\n\r\n#ifdef HAL_NAND_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_nand.h\"\r\n#endif /* HAL_NAND_MODULE_ENABLED */\r\n\r\n#ifdef HAL_SDRAM_MODULE_ENABLED\r\n  #include \"stm32f7xx_hal_sdram.h\"\r\n#endif /* HAL_SDRAM_MODULE_ENABLED */      \r\n\r\n#ifdef HAL_HASH_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_hash.h\"\r\n#endif /* HAL_HASH_MODULE_ENABLED */\r\n\r\n#ifdef HAL_I2C_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_i2c.h\"\r\n#endif /* HAL_I2C_MODULE_ENABLED */\r\n\r\n#ifdef HAL_I2S_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_i2s.h\"\r\n#endif /* HAL_I2S_MODULE_ENABLED */\r\n\r\n#ifdef HAL_IWDG_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_iwdg.h\"\r\n#endif /* HAL_IWDG_MODULE_ENABLED */\r\n\r\n#ifdef HAL_LPTIM_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_lptim.h\"\r\n#endif /* HAL_LPTIM_MODULE_ENABLED */\r\n\r\n#ifdef HAL_LTDC_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_ltdc.h\"\r\n#endif /* HAL_LTDC_MODULE_ENABLED */\r\n\r\n#ifdef HAL_PWR_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_pwr.h\"\r\n#endif /* HAL_PWR_MODULE_ENABLED */\r\n\r\n#ifdef HAL_QSPI_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_qspi.h\"\r\n#endif /* HAL_QSPI_MODULE_ENABLED */\r\n\r\n#ifdef HAL_RNG_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_rng.h\"\r\n#endif /* HAL_RNG_MODULE_ENABLED */\r\n\r\n#ifdef HAL_RTC_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_rtc.h\"\r\n#endif /* HAL_RTC_MODULE_ENABLED */\r\n\r\n#ifdef HAL_SAI_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_sai.h\"\r\n#endif /* HAL_SAI_MODULE_ENABLED */\r\n\r\n#ifdef HAL_SD_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_sd.h\"\r\n#endif /* HAL_SD_MODULE_ENABLED */\r\n\r\n#ifdef HAL_SPDIFRX_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_spdifrx.h\"\r\n#endif /* HAL_SPDIFRX_MODULE_ENABLED */\r\n\r\n#ifdef HAL_SPI_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_spi.h\"\r\n#endif /* HAL_SPI_MODULE_ENABLED */\r\n\r\n#ifdef HAL_TIM_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_tim.h\"\r\n#endif /* HAL_TIM_MODULE_ENABLED */\r\n\r\n#ifdef HAL_UART_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_uart.h\"\r\n#endif /* HAL_UART_MODULE_ENABLED */\r\n\r\n#ifdef HAL_USART_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_usart.h\"\r\n#endif /* HAL_USART_MODULE_ENABLED */\r\n\r\n#ifdef HAL_IRDA_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_irda.h\"\r\n#endif /* HAL_IRDA_MODULE_ENABLED */\r\n\r\n#ifdef HAL_SMARTCARD_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_smartcard.h\"\r\n#endif /* HAL_SMARTCARD_MODULE_ENABLED */\r\n\r\n#ifdef HAL_WWDG_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_wwdg.h\"\r\n#endif /* HAL_WWDG_MODULE_ENABLED */\r\n\r\n#ifdef HAL_PCD_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_pcd.h\"\r\n#endif /* HAL_PCD_MODULE_ENABLED */\r\n\r\n#ifdef HAL_HCD_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_hcd.h\"\r\n#endif /* HAL_HCD_MODULE_ENABLED */\r\n\r\n#ifdef HAL_DFSDM_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_dfsdm.h\"\r\n#endif /* HAL_DFSDM_MODULE_ENABLED */\r\n\r\n#ifdef HAL_DSI_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_dsi.h\"\r\n#endif /* HAL_DSI_MODULE_ENABLED */\r\n\r\n#ifdef HAL_JPEG_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_jpeg.h\"\r\n#endif /* HAL_JPEG_MODULE_ENABLED */\r\n\r\n#ifdef HAL_MDIOS_MODULE_ENABLED\r\n #include \"stm32f7xx_hal_mdios.h\"\r\n#endif /* HAL_MDIOS_MODULE_ENABLED */\r\n   \r\n/* Exported macro ------------------------------------------------------------*/\r\n#ifdef  USE_FULL_ASSERT\r\n/**\r\n  * @brief  The assert_param macro is used for function's parameters check.\r\n  * @param  expr: If expr is false, it calls assert_failed function\r\n  *         which reports the name of the source file and the source\r\n  *         line number of the call that failed. \r\n  *         If expr is true, it returns no value.\r\n  * @retval None\r\n  */\r\n  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))\r\n/* Exported functions ------------------------------------------------------- */\r\n  void assert_failed(uint8_t* file, uint32_t line);\r\n#else\r\n  #define assert_param(expr) ((void)0)\r\n#endif /* USE_FULL_ASSERT */\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_CONF_H */\r\n \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_cortex.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of CORTEX HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_CORTEX_H\r\n#define __STM32F7xx_HAL_CORTEX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup CORTEX\r\n  * @{\r\n  */ \r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup CORTEX_Exported_Types Cortex Exported Types\r\n  * @{\r\n  */\r\n\r\n#if (__MPU_PRESENT == 1)\r\n/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition\r\n  * @brief  MPU Region initialization structure \r\n  * @{\r\n  */\r\ntypedef struct\r\n{\r\n  uint8_t                Enable;                /*!< Specifies the status of the region. \r\n                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */\r\n  uint8_t                Number;                /*!< Specifies the number of the region to protect. \r\n                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */\r\n  uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */\r\n  uint8_t                Size;                  /*!< Specifies the size of the region to protect. \r\n                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */\r\n  uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable. \r\n                                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */         \r\n  uint8_t                TypeExtField;          /*!< Specifies the TEX field level.\r\n                                                     This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */                 \r\n  uint8_t                AccessPermission;      /*!< Specifies the region access permission type. \r\n                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */\r\n  uint8_t                DisableExec;           /*!< Specifies the instruction access status. \r\n                                                     This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */\r\n  uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region. \r\n                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */\r\n  uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected. \r\n                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */\r\n  uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region. \r\n                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */\r\n}MPU_Region_InitTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n#endif /* __MPU_PRESENT */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group\r\n  * @{\r\n  */\r\n#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007U) /*!< 0 bits for pre-emption priority\r\n                                                                 4 bits for subpriority */\r\n#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006U) /*!< 1 bits for pre-emption priority\r\n                                                                 3 bits for subpriority */\r\n#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005U) /*!< 2 bits for pre-emption priority\r\n                                                                 2 bits for subpriority */\r\n#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004U) /*!< 3 bits for pre-emption priority\r\n                                                                 1 bits for subpriority */\r\n#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003U) /*!< 4 bits for pre-emption priority\r\n                                                                 0 bits for subpriority */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source \r\n  * @{\r\n  */\r\n#define SYSTICK_CLKSOURCE_HCLK_DIV8    ((uint32_t)0x00000000U)\r\n#define SYSTICK_CLKSOURCE_HCLK         ((uint32_t)0x00000004U)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#if (__MPU_PRESENT == 1)\r\n/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control\r\n  * @{\r\n  */\r\n#define  MPU_HFNMI_PRIVDEF_NONE      ((uint32_t)0x00000000U)  \r\n#define  MPU_HARDFAULT_NMI           ((uint32_t)0x00000002U)\r\n#define  MPU_PRIVILEGED_DEFAULT      ((uint32_t)0x00000004U)\r\n#define  MPU_HFNMI_PRIVDEF           ((uint32_t)0x00000006U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable\r\n  * @{\r\n  */\r\n#define  MPU_REGION_ENABLE     ((uint8_t)0x01U)\r\n#define  MPU_REGION_DISABLE    ((uint8_t)0x00U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access\r\n  * @{\r\n  */\r\n#define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00U)\r\n#define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable\r\n  * @{\r\n  */\r\n#define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01U)\r\n#define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable\r\n  * @{\r\n  */\r\n#define  MPU_ACCESS_CACHEABLE         ((uint8_t)0x01U)\r\n#define  MPU_ACCESS_NOT_CACHEABLE     ((uint8_t)0x00U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable\r\n  * @{\r\n  */\r\n#define  MPU_ACCESS_BUFFERABLE         ((uint8_t)0x01U)\r\n#define  MPU_ACCESS_NOT_BUFFERABLE     ((uint8_t)0x00U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels\r\n  * @{\r\n  */\r\n#define  MPU_TEX_LEVEL0    ((uint8_t)0x00U)\r\n#define  MPU_TEX_LEVEL1    ((uint8_t)0x01U)\r\n#define  MPU_TEX_LEVEL2    ((uint8_t)0x02U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size\r\n  * @{\r\n  */\r\n#define   MPU_REGION_SIZE_32B      ((uint8_t)0x04U)\r\n#define   MPU_REGION_SIZE_64B      ((uint8_t)0x05U)\r\n#define   MPU_REGION_SIZE_128B     ((uint8_t)0x06U) \r\n#define   MPU_REGION_SIZE_256B     ((uint8_t)0x07U) \r\n#define   MPU_REGION_SIZE_512B     ((uint8_t)0x08U) \r\n#define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09U)  \r\n#define   MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU)\r\n#define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) \r\n#define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) \r\n#define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) \r\n#define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) \r\n#define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) \r\n#define   MPU_REGION_SIZE_128KB    ((uint8_t)0x10U)\r\n#define   MPU_REGION_SIZE_256KB    ((uint8_t)0x11U)\r\n#define   MPU_REGION_SIZE_512KB    ((uint8_t)0x12U)\r\n#define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) \r\n#define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) \r\n#define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) \r\n#define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) \r\n#define   MPU_REGION_SIZE_16MB     ((uint8_t)0x17U)\r\n#define   MPU_REGION_SIZE_32MB     ((uint8_t)0x18U)\r\n#define   MPU_REGION_SIZE_64MB     ((uint8_t)0x19U)\r\n#define   MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU)\r\n#define   MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU)\r\n#define   MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU)\r\n#define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) \r\n#define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) \r\n#define   MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU)\r\n/**                                \r\n  * @}\r\n  */\r\n   \r\n/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes \r\n  * @{\r\n  */\r\n#define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00U)  \r\n#define  MPU_REGION_PRIV_RW        ((uint8_t)0x01U) \r\n#define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02U)  \r\n#define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03U)  \r\n#define  MPU_REGION_PRIV_RO        ((uint8_t)0x05U) \r\n#define  MPU_REGION_PRIV_RO_URO    ((uint8_t)0x06U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number\r\n  * @{\r\n  */\r\n#define  MPU_REGION_NUMBER0    ((uint8_t)0x00U)  \r\n#define  MPU_REGION_NUMBER1    ((uint8_t)0x01U) \r\n#define  MPU_REGION_NUMBER2    ((uint8_t)0x02U)  \r\n#define  MPU_REGION_NUMBER3    ((uint8_t)0x03U)  \r\n#define  MPU_REGION_NUMBER4    ((uint8_t)0x04U) \r\n#define  MPU_REGION_NUMBER5    ((uint8_t)0x05U)\r\n#define  MPU_REGION_NUMBER6    ((uint8_t)0x06U)\r\n#define  MPU_REGION_NUMBER7    ((uint8_t)0x07U)\r\n/**\r\n  * @}\r\n  */\r\n#endif /* __MPU_PRESENT */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/* Exported Macros -----------------------------------------------------------*/\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup CORTEX_Exported_Functions\r\n  * @{\r\n  */\r\n  \r\n/** @addtogroup CORTEX_Exported_Functions_Group1\r\n * @{\r\n */\r\n/* Initialization and de-initialization functions *****************************/\r\nvoid HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);\r\nvoid HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);\r\nvoid HAL_NVIC_EnableIRQ(IRQn_Type IRQn);\r\nvoid HAL_NVIC_DisableIRQ(IRQn_Type IRQn);\r\nvoid HAL_NVIC_SystemReset(void);\r\nuint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup CORTEX_Exported_Functions_Group2\r\n * @{\r\n */\r\n/* Peripheral Control functions ***********************************************/\r\n#if (__MPU_PRESENT == 1)\r\nvoid HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);\r\n#endif /* __MPU_PRESENT */\r\nuint32_t HAL_NVIC_GetPriorityGrouping(void);\r\nvoid HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);\r\nuint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);\r\nvoid HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);\r\nvoid HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);\r\nuint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);\r\nvoid HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);\r\nvoid HAL_SYSTICK_IRQHandler(void);\r\nvoid HAL_SYSTICK_Callback(void);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private types -------------------------------------------------------------*/ \r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup CORTEX_Private_Macros CORTEX Private Macros\r\n  * @{\r\n  */\r\n#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \\\r\n                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \\\r\n                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \\\r\n                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \\\r\n                                       ((GROUP) == NVIC_PRIORITYGROUP_4))\r\n\r\n#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10U)\r\n\r\n#define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10U)\r\n\r\n#define IS_NVIC_DEVICE_IRQ(IRQ)                ((IRQ) >= 0x00)\r\n\r\n#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \\\r\n                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))\r\n\r\n#if (__MPU_PRESENT == 1)\r\n#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \\\r\n                                     ((STATE) == MPU_REGION_DISABLE))\r\n\r\n#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \\\r\n                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))\r\n\r\n#define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \\\r\n                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))\r\n\r\n#define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \\\r\n                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))\r\n\r\n#define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \\\r\n                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))\r\n\r\n#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \\\r\n                                ((TYPE) == MPU_TEX_LEVEL1)  || \\\r\n                                ((TYPE) == MPU_TEX_LEVEL2))\r\n\r\n#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \\\r\n                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \\\r\n                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \\\r\n                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \\\r\n                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \\\r\n                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))\r\n\r\n#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \\\r\n                                         ((NUMBER) == MPU_REGION_NUMBER1) || \\\r\n                                         ((NUMBER) == MPU_REGION_NUMBER2) || \\\r\n                                         ((NUMBER) == MPU_REGION_NUMBER3) || \\\r\n                                         ((NUMBER) == MPU_REGION_NUMBER4) || \\\r\n                                         ((NUMBER) == MPU_REGION_NUMBER5) || \\\r\n                                         ((NUMBER) == MPU_REGION_NUMBER6) || \\\r\n                                         ((NUMBER) == MPU_REGION_NUMBER7))\r\n\r\n#define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_64B)   || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_128B)  || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_256B)  || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \\\r\n                                     ((SIZE) == MPU_REGION_SIZE_4GB))\r\n\r\n#define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FFU)\r\n#endif /* __MPU_PRESENT */\r\n\r\n/**                                                                          \r\n  * @}                                                                  \r\n  */                                                                            \r\n                                                                                   \r\n/* Private functions ---------------------------------------------------------*/   \r\n/** @defgroup CORTEX_Private_Functions CORTEX Private Functions\r\n  * @brief    CORTEX private  functions \r\n  * @{\r\n  */\r\n\r\n#if (__MPU_PRESENT == 1)\r\n/**\r\n  * @brief  Disables the MPU\r\n  * @retval None\r\n  */\r\n__STATIC_INLINE void HAL_MPU_Disable(void)\r\n{\r\n  /* Disable fault exceptions */\r\n  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\r\n  \r\n  /* Disable the MPU */\r\n  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;\r\n}\r\n\r\n/**\r\n  * @brief  Enables the MPU\r\n  * @param  MPU_Control: Specifies the control mode of the MPU during hard fault, \r\n  *          NMI, FAULTMASK and privileged access to the default memory \r\n  *          This parameter can be one of the following values:\r\n  *            @arg MPU_HFNMI_PRIVDEF_NONE\r\n  *            @arg MPU_HARDFAULT_NMI\r\n  *            @arg MPU_PRIVILEGED_DEFAULT\r\n  *            @arg MPU_HFNMI_PRIVDEF\r\n  * @retval None\r\n  */\r\n__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)\r\n{\r\n  /* Enable the MPU */\r\n  MPU->CTRL   = MPU_Control | MPU_CTRL_ENABLE_Msk;\r\n  \r\n  /* Enable fault exceptions */\r\n  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\r\n}\r\n#endif /* __MPU_PRESENT */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_CORTEX_H */\r\n \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_crc.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_crc.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of CRC HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_CRC_H\r\n#define __STM32F7xx_HAL_CRC_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CRC CRC\r\n  * @brief CRC HAL module driver\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup CRC_Exported_Types CRC Exported Types\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CRC_Exported_Types_Group1 CRC State Structure definition \r\n  * @{\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_CRC_STATE_RESET     = 0x00U,  /*!< CRC not yet initialized or disabled */\r\n  HAL_CRC_STATE_READY     = 0x01U,  /*!< CRC initialized and ready for use   */\r\n  HAL_CRC_STATE_BUSY      = 0x02U,  /*!< CRC internal process is ongoing     */\r\n  HAL_CRC_STATE_TIMEOUT   = 0x03U,  /*!< CRC timeout state                   */\r\n  HAL_CRC_STATE_ERROR     = 0x04U   /*!< CRC error state                     */\r\n}HAL_CRC_StateTypeDef;\r\n/** \r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRC_Exported_Types_Group2 CRC Init Structure definition  \r\n  * @{\r\n  */\r\ntypedef struct\r\n{\r\n  uint8_t DefaultPolynomialUse;       /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.  \r\n                                            If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default \r\n                                            X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1. \r\n                                            In that case, there is no need to set GeneratingPolynomial field.\r\n                                            If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set */\r\n\r\n  uint8_t DefaultInitValueUse;        /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used. \r\n                                           If set to DEFAULT_INIT_VALUE_ENABLE, resort to default\r\n                                           0xFFFFFFFF value. In that case, there is no need to set InitValue field.   \r\n                                           If otherwise set to DEFAULT_INIT_VALUE_DISABLE,  InitValue field must be set */\r\n\r\n  uint32_t GeneratingPolynomial;      /*!< Set CRC generating polynomial. 7, 8, 16 or 32-bit long value for a polynomial degree\r\n                                           respectively equal to 7, 8, 16 or 32. This field is written in normal representation, \r\n                                           e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65.\r\n                                           No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE   */                                                \r\n\r\n  uint32_t CRCLength;                 /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.\r\n                                           Value can be either one of\r\n                                           CRC_POLYLENGTH_32B                  (32-bit CRC)\r\n                                           CRC_POLYLENGTH_16B                  (16-bit CRC)\r\n                                           CRC_POLYLENGTH_8B                   (8-bit CRC)\r\n                                           CRC_POLYLENGTH_7B                   (7-bit CRC) */\r\n                                              \r\n  uint32_t InitValue;                 /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse \r\n                                           is set to DEFAULT_INIT_VALUE_ENABLE   */                                                \r\n  \r\n  uint32_t InputDataInversionMode;    /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode. \r\n                                           Can be either one of the following values \r\n                                           CRC_INPUTDATA_INVERSION_NONE      no input data inversion\r\n                                           CRC_INPUTDATA_INVERSION_BYTE      byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2\r\n                                           CRC_INPUTDATA_INVERSION_HALFWORD  halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C\r\n                                           CRC_INPUTDATA_INVERSION_WORD      word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */  \r\n                                              \r\n  uint32_t OutputDataInversionMode;   /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.\r\n                                            Can be either \r\n                                            CRC_OUTPUTDATA_INVERSION_DISABLE   no CRC inversion, or\r\n                                            CRC_OUTPUTDATA_INVERSION_ENABLE    CRC 0x11223344 is converted into 0x22CC4488 */\r\n}CRC_InitTypeDef;\r\n/** \r\n  * @}\r\n  */\r\n  \r\n/** @defgroup CRC_Exported_Types_Group3 CRC Handle Structure definition   \r\n  * @{\r\n  */\r\ntypedef struct\r\n{\r\n  CRC_TypeDef                 *Instance;   /*!< Register base address        */ \r\n  \r\n  CRC_InitTypeDef             Init;        /*!< CRC configuration parameters */\r\n  \r\n  HAL_LockTypeDef             Lock;        /*!< CRC Locking object           */\r\n    \r\n  __IO HAL_CRC_StateTypeDef   State;       /*!< CRC communication state      */\r\n  \r\n  uint32_t InputDataFormat;                /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format. \r\n                                            Can be either \r\n                                            CRC_INPUTDATA_FORMAT_BYTES       input data is a stream of bytes (8-bit data)\r\n                                            CRC_INPUTDATA_FORMAT_HALFWORDS   input data is a stream of half-words (16-bit data)\r\n                                            CRC_INPUTDATA_FORMAT_WORDS       input data is a stream of words (32-bits data)                                                                                        \r\n                                           Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error\r\n                                           must occur if InputBufferFormat is not one of the three values listed above  */ \r\n}CRC_HandleTypeDef;\r\n/** \r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup CRC_Exported_Constants   CRC exported constants\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup CRC_Default_Polynomial_Value    Default CRC generating polynomial\r\n  * @{\r\n  */\r\n#define DEFAULT_CRC32_POLY      0x04C11DB7U\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRC_Default_InitValue    Default CRC computation initialization value\r\n  * @{\r\n  */\r\n#define DEFAULT_CRC_INITVALUE   0xFFFFFFFFU\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRC_Default_Polynomial    Indicates whether or not default polynomial is used\r\n  * @{\r\n  */\r\n#define DEFAULT_POLYNOMIAL_ENABLE       ((uint8_t)0x00U)\r\n#define DEFAULT_POLYNOMIAL_DISABLE      ((uint8_t)0x01U)\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n \r\n/** @defgroup CRC_Default_InitValue_Use    Indicates whether or not default init value is used\r\n  * @{\r\n  */                                      \r\n#define DEFAULT_INIT_VALUE_ENABLE      ((uint8_t)0x00U)\r\n#define DEFAULT_INIT_VALUE_DISABLE     ((uint8_t)0x01U)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP\r\n  * @{\r\n  */\r\n#define CRC_POLYLENGTH_32B                  ((uint32_t)0x00000000U)\r\n#define CRC_POLYLENGTH_16B                  ((uint32_t)CRC_CR_POLYSIZE_0)\r\n#define CRC_POLYLENGTH_8B                   ((uint32_t)CRC_CR_POLYSIZE_1)\r\n#define CRC_POLYLENGTH_7B                   ((uint32_t)CRC_CR_POLYSIZE)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions\r\n  * @{\r\n  */\r\n#define HAL_CRC_LENGTH_32B     32U\r\n#define HAL_CRC_LENGTH_16B     16U\r\n#define HAL_CRC_LENGTH_8B       8U\r\n#define HAL_CRC_LENGTH_7B       7U\r\n\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup CRC_Input_Buffer_Format CRC input buffer format\r\n  * @{\r\n  */\r\n/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but\r\n * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set \r\n * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for \r\n * the CRC APIs to provide a correct result */   \r\n#define CRC_INPUTDATA_FORMAT_UNDEFINED             ((uint32_t)0x00000000U)\r\n#define CRC_INPUTDATA_FORMAT_BYTES                 ((uint32_t)0x00000001U)\r\n#define CRC_INPUTDATA_FORMAT_HALFWORDS             ((uint32_t)0x00000002U)\r\n#define CRC_INPUTDATA_FORMAT_WORDS                 ((uint32_t)0x00000003U)\r\n/** \r\n  * @}\r\n  */   \r\n\r\n/** \r\n  * @}\r\n  */ \r\n/* Exported macros -----------------------------------------------------------*/\r\n\r\n/** @defgroup CRC_Exported_Macros CRC exported macros\r\n  * @{\r\n  */\r\n\r\n/** @brief Reset CRC handle state\r\n  * @param  __HANDLE__: CRC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)\r\n\r\n/**\r\n  * @brief  Reset CRC Data Register.\r\n  * @param  __HANDLE__: CRC handle\r\n  * @retval None.\r\n  */\r\n#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)\r\n\r\n/**\r\n  * @brief  Set CRC INIT non-default value\r\n  * @param  __HANDLE__    : CRC handle\r\n  * @param  __INIT__      : 32-bit initial value  \r\n  * @retval None.\r\n  */\r\n#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))    \r\n\r\n/**\r\n  * @brief Stores a 8-bit data in the Independent Data(ID) register.\r\n  * @param __HANDLE__: CRC handle\r\n  * @param __VALUE__: 8-bit value to be stored in the ID register\r\n  * @retval None\r\n  */\r\n#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, CRC_IDR_IDR, (__VALUE__)))\r\n\r\n/**\r\n  * @brief Returns the 8-bit data stored in the Independent Data(ID) register.\r\n  * @param __HANDLE__: CRC handle\r\n  * @retval 8-bit value of the ID register \r\n  */\r\n#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/* Include CRC HAL Extension module */\r\n#include \"stm32f7xx_hal_crc_ex.h\"\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup CRC_Exported_Functions CRC Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CRC_Exported_Functions_Group1 Initialization/de-initialization functions\r\n  * @{\r\n  */\r\n/* Initialization and de-initialization functions  ****************************/\r\nHAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);\r\nHAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);\r\nvoid HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);\r\nvoid HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Aliases for inter STM32 series compatibility */\r\n#define HAL_CRC_Input_Data_Reverse   HAL_CRCEx_Input_Data_Reverse\r\n#define HAL_CRC_Output_Data_Reverse  HAL_CRCEx_Output_Data_Reverse\r\n\r\n/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions\r\n  * @{\r\n  */\r\n/* Peripheral Control functions ***********************************************/\r\nuint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);\r\nuint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions\r\n  * @{\r\n  */\r\n/* Peripheral State and Error functions ***************************************/\r\nHAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/** @defgroup CRC_Private_Types CRC Private Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private defines -----------------------------------------------------------*/\r\n/** @defgroup CRC_Private_Defines CRC Private Defines\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @defgroup CRC_Private_Variables CRC Private Variables\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup CRC_Private_Constants CRC Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup CRC_Private_Macros CRC Private Macros\r\n  * @{\r\n  */\r\n#define IS_DEFAULT_POLYNOMIAL(__DEFAULT__) (((__DEFAULT__) == DEFAULT_POLYNOMIAL_ENABLE) || \\\r\n                                            ((__DEFAULT__) == DEFAULT_POLYNOMIAL_DISABLE))\r\n#define IS_DEFAULT_INIT_VALUE(__VALUE__)  (((__VALUE__) == DEFAULT_INIT_VALUE_ENABLE) || \\\r\n                                           ((__VALUE__) == DEFAULT_INIT_VALUE_DISABLE))\r\n#define IS_CRC_POL_LENGTH(__LENGTH__)     (((__LENGTH__) == CRC_POLYLENGTH_32B) || \\\r\n                                           ((__LENGTH__) == CRC_POLYLENGTH_16B) || \\\r\n                                           ((__LENGTH__) == CRC_POLYLENGTH_8B)  || \\\r\n                                           ((__LENGTH__) == CRC_POLYLENGTH_7B))\r\n#define IS_CRC_INPUTDATA_FORMAT(__FORMAT__)       (((__FORMAT__) == CRC_INPUTDATA_FORMAT_BYTES) || \\\r\n                                                   ((__FORMAT__) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \\\r\n                                                   ((__FORMAT__) == CRC_INPUTDATA_FORMAT_WORDS))\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions prototypes ----------------------------------------------*/\r\n/** @defgroup CRC_Private_Functions_Prototypes CRC Private Functions Prototypes\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup CRC_Private_Functions CRC Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_CRC_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_crc_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_crc_ex.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of CRC HAL extension module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_CRC_EX_H\r\n#define __STM32F7xx_HAL_CRC_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CRCEx CRCEx\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/ \r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup CRCEx_Exported_Constants CRC Extended exported constants\r\n * @{\r\n */\r\n\r\n/** @defgroup CRCEx_Input_Data_Inversion CRC Extended input data inversion modes\r\n  * @{\r\n  */\r\n#define CRC_INPUTDATA_INVERSION_NONE              ((uint32_t)0x00000000U)\r\n#define CRC_INPUTDATA_INVERSION_BYTE              ((uint32_t)CRC_CR_REV_IN_0)\r\n#define CRC_INPUTDATA_INVERSION_HALFWORD          ((uint32_t)CRC_CR_REV_IN_1)\r\n#define CRC_INPUTDATA_INVERSION_WORD              ((uint32_t)CRC_CR_REV_IN)\r\n\r\n#define IS_CRC_INPUTDATA_INVERSION_MODE(__MODE__)     (((__MODE__) == CRC_INPUTDATA_INVERSION_NONE) || \\\r\n                                                       ((__MODE__) == CRC_INPUTDATA_INVERSION_BYTE) || \\\r\n                                                       ((__MODE__) == CRC_INPUTDATA_INVERSION_HALFWORD) || \\\r\n                                                       ((__MODE__) == CRC_INPUTDATA_INVERSION_WORD))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRCEx_Output_Data_Inversion CRC Extended output data inversion modes\r\n  * @{\r\n  */\r\n#define CRC_OUTPUTDATA_INVERSION_DISABLE         ((uint32_t)0x00000000U)\r\n#define CRC_OUTPUTDATA_INVERSION_ENABLE          ((uint32_t)CRC_CR_REV_OUT)\r\n\r\n#define IS_CRC_OUTPUTDATA_INVERSION_MODE(__MODE__)    (((__MODE__) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \\\r\n                                                       ((__MODE__) == CRC_OUTPUTDATA_INVERSION_ENABLE))\r\n/**                                               \r\n  * @}\r\n  */\r\n\r\n\r\n/**\r\n * @}\r\n */\r\n/* Exported macro ------------------------------------------------------------*/\r\n\r\n/** @defgroup CRCEx_Exported_Macros CRC Extended exported macros\r\n  * @{\r\n  */\r\n    \r\n/**\r\n  * @brief  Set CRC output reversal\r\n  * @param  __HANDLE__    : CRC handle\r\n  * @retval None.\r\n  */\r\n#define  __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)   \r\n\r\n/**\r\n  * @brief  Unset CRC output reversal\r\n  * @param  __HANDLE__    : CRC handle\r\n  * @retval None.\r\n  */\r\n#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))   \r\n\r\n/**\r\n  * @brief  Set CRC non-default polynomial\r\n  * @param  __HANDLE__    : CRC handle\r\n  * @param  __POLYNOMIAL__: 7, 8, 16 or 32-bit polynomial  \r\n  * @retval None.\r\n  */\r\n#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CRCEx_Exported_Functions_Group1 Extended CRC features functions\r\n  * @{\r\n  */\r\n/* Exported functions --------------------------------------------------------*/\r\n/* Initialization and de-initialization functions  ****************************/\r\nHAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);\r\nHAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);\r\nHAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);\r\n\r\n/* Peripheral Control functions ***********************************************/\r\n/* Peripheral State and Error functions ***************************************/\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_CRC_EX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cryp.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_cryp.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of CRYP HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_CRYP_H\r\n#define __STM32F7xx_HAL_CRYP_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup CRYP\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n\r\n/** @defgroup CRYP_Exported_Types CRYP Exported Types\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CRYP_Exported_Types_Group1 CRYP Configuration Structure definition\r\n  * @{\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  uint32_t DataType;    /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.\r\n                             This parameter can be a value of @ref CRYP_Data_Type */\r\n\r\n  uint32_t KeySize;     /*!< Used only in AES mode only : 128, 192 or 256 bit key length. \r\n                             This parameter can be a value of @ref CRYP_Key_Size */\r\n\r\n  uint8_t* pKey;        /*!< The key used for encryption/decryption */\r\n\r\n  uint8_t* pInitVect;   /*!< The initialization vector used also as initialization\r\n                             counter in CTR mode */\r\n\r\n  uint8_t IVSize;       /*!< The size of initialization vector. \r\n                             This parameter (called nonce size in CCM) is used only \r\n                             in AES-128/192/256 encryption/decryption CCM mode */\r\n\r\n  uint8_t TagSize;      /*!< The size of returned authentication TAG. \r\n                             This parameter is used only in AES-128/192/256 \r\n                             encryption/decryption CCM mode */\r\n\r\n  uint8_t* Header;      /*!< The header used in GCM and CCM modes */\r\n\r\n  uint32_t HeaderSize;  /*!< The size of header buffer in bytes */\r\n\r\n  uint8_t* pScratch;    /*!< Scratch buffer used to append the header. It's size must be equal to header size + 21 bytes.\r\n                             This parameter is used only in AES-128/192/256 encryption/decryption CCM mode */\r\n}CRYP_InitTypeDef;\r\n\r\n/** \r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRYP_Exported_Types_Group2 CRYP State structures definition\r\n  * @{\r\n  */\r\n    \r\n\r\ntypedef enum\r\n{\r\n  HAL_CRYP_STATE_RESET             = 0x00U,  /*!< CRYP not yet initialized or disabled  */\r\n  HAL_CRYP_STATE_READY             = 0x01U,  /*!< CRYP initialized and ready for use    */\r\n  HAL_CRYP_STATE_BUSY              = 0x02U,  /*!< CRYP internal processing is ongoing   */\r\n  HAL_CRYP_STATE_TIMEOUT           = 0x03U,  /*!< CRYP timeout state                    */\r\n  HAL_CRYP_STATE_ERROR             = 0x04U   /*!< CRYP error state                      */\r\n}HAL_CRYP_STATETypeDef;\r\n\r\n/** \r\n  * @}\r\n  */\r\n  \r\n/** @defgroup CRYP_Exported_Types_Group3 CRYP phase structures definition\r\n  * @{\r\n  */\r\n    \r\n\r\ntypedef enum\r\n{\r\n  HAL_CRYP_PHASE_READY             = 0x01U,    /*!< CRYP peripheral is ready for initialization. */\r\n  HAL_CRYP_PHASE_PROCESS           = 0x02U,    /*!< CRYP peripheral is in processing phase */\r\n  HAL_CRYP_PHASE_FINAL             = 0x03U     /*!< CRYP peripheral is in final phase\r\n                                                   This is relevant only with CCM and GCM modes */\r\n}HAL_PhaseTypeDef;\r\n\r\n/** \r\n  * @}\r\n  */\r\n  \r\n/** @defgroup CRYP_Exported_Types_Group4 CRYP handle Structure definition\r\n  * @{\r\n  */\r\n  \r\ntypedef struct\r\n{\r\n      CRYP_TypeDef             *Instance;        /*!< CRYP registers base address */\r\n\r\n      CRYP_InitTypeDef         Init;             /*!< CRYP required parameters */\r\n\r\n      uint8_t                  *pCrypInBuffPtr;  /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */\r\n\r\n      uint8_t                  *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */\r\n\r\n      __IO uint16_t            CrypInCount;      /*!< Counter of input data */\r\n\r\n      __IO uint16_t            CrypOutCount;     /*!< Counter of output data */\r\n\r\n      HAL_StatusTypeDef        Status;           /*!< CRYP peripheral status */\r\n\r\n      HAL_PhaseTypeDef         Phase;            /*!< CRYP peripheral phase */\r\n\r\n      DMA_HandleTypeDef        *hdmain;          /*!< CRYP In DMA handle parameters */\r\n\r\n      DMA_HandleTypeDef        *hdmaout;         /*!< CRYP Out DMA handle parameters */\r\n\r\n      HAL_LockTypeDef          Lock;             /*!< CRYP locking object */\r\n\r\n   __IO  HAL_CRYP_STATETypeDef State;            /*!< CRYP peripheral state */\r\n}CRYP_HandleTypeDef;\r\n\r\n/** \r\n  * @}\r\n  */\r\n\r\n/** \r\n  * @}\r\n  */\r\n    \r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup CRYP_Exported_Constants CRYP Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CRYP_Key_Size CRYP Key Size\r\n  * @{\r\n  */\r\n#define CRYP_KEYSIZE_128B         ((uint32_t)0x00000000U)\r\n#define CRYP_KEYSIZE_192B         CRYP_CR_KEYSIZE_0\r\n#define CRYP_KEYSIZE_256B         CRYP_CR_KEYSIZE_1\r\n/**                                \r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRYP_Data_Type CRYP Data Type\r\n  * @{\r\n  */\r\n#define CRYP_DATATYPE_32B         ((uint32_t)0x00000000U)\r\n#define CRYP_DATATYPE_16B         CRYP_CR_DATATYPE_0\r\n#define CRYP_DATATYPE_8B          CRYP_CR_DATATYPE_1\r\n#define CRYP_DATATYPE_1B          CRYP_CR_DATATYPE\r\n/**                                \r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRYP_Exported_Constants_Group3 CRYP CRYP_AlgoModeDirection\r\n  * @{\r\n  */\r\n#define CRYP_CR_ALGOMODE_DIRECTION         ((uint32_t)0x0008003CU)\r\n#define CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT  ((uint32_t)0x00000000U)\r\n#define CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT  ((uint32_t)0x00000004U)\r\n#define CRYP_CR_ALGOMODE_TDES_CBC_ENCRYPT  ((uint32_t)0x00000008U)\r\n#define CRYP_CR_ALGOMODE_TDES_CBC_DECRYPT  ((uint32_t)0x0000000CU)\r\n#define CRYP_CR_ALGOMODE_DES_ECB_ENCRYPT   ((uint32_t)0x00000010U)\r\n#define CRYP_CR_ALGOMODE_DES_ECB_DECRYPT   ((uint32_t)0x00000014U)\r\n#define CRYP_CR_ALGOMODE_DES_CBC_ENCRYPT   ((uint32_t)0x00000018U)\r\n#define CRYP_CR_ALGOMODE_DES_CBC_DECRYPT   ((uint32_t)0x0000001CU)\r\n#define CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT   ((uint32_t)0x00000020U)\r\n#define CRYP_CR_ALGOMODE_AES_ECB_DECRYPT   ((uint32_t)0x00000024U)\r\n#define CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT   ((uint32_t)0x00000028U)\r\n#define CRYP_CR_ALGOMODE_AES_CBC_DECRYPT   ((uint32_t)0x0000002CU)\r\n#define CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT   ((uint32_t)0x00000030U)\r\n#define CRYP_CR_ALGOMODE_AES_CTR_DECRYPT   ((uint32_t)0x00000034U)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup CRYP_Exported_Constants_Group4 CRYP CRYP_Interrupt\r\n  * @{\r\n  */\r\n#define CRYP_IT_INI               ((uint32_t)CRYP_IMSCR_INIM)   /*!< Input FIFO Interrupt */\r\n#define CRYP_IT_OUTI              ((uint32_t)CRYP_IMSCR_OUTIM)  /*!< Output FIFO Interrupt */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRYP_Exported_Constants_Group5 CRYP CRYP_Flags\r\n  * @{\r\n  */\r\n#define CRYP_FLAG_BUSY   ((uint32_t)0x00000010U)  /*!< The CRYP core is currently \r\n                                                     processing a block of data \r\n                                                     or a key preparation (for \r\n                                                     AES decryption). */\r\n#define CRYP_FLAG_IFEM   ((uint32_t)0x00000001U)  /*!< Input FIFO is empty */\r\n#define CRYP_FLAG_IFNF   ((uint32_t)0x00000002U)  /*!< Input FIFO is not Full */\r\n#define CRYP_FLAG_OFNE   ((uint32_t)0x00000004U)  /*!< Output FIFO is not empty */\r\n#define CRYP_FLAG_OFFU   ((uint32_t)0x00000008U)  /*!< Output FIFO is Full */\r\n#define CRYP_FLAG_OUTRIS ((uint32_t)0x01000002U)  /*!< Output FIFO service raw \r\n                                                      interrupt status */\r\n#define CRYP_FLAG_INRIS  ((uint32_t)0x01000001U)  /*!< Input FIFO service raw \r\n                                                      interrupt status */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup CRYP_Exported_Macros CRYP Exported Macros\r\n  * @{\r\n  */\r\n  \r\n/** @brief Reset CRYP handle state\r\n  * @param  __HANDLE__: specifies the CRYP handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)\r\n\r\n/**\r\n  * @brief  Enable/Disable the CRYP peripheral.\r\n  * @param  __HANDLE__: specifies the CRYP handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_CRYP_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  CRYP_CR_CRYPEN)\r\n#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &=  ~CRYP_CR_CRYPEN)\r\n\r\n/**\r\n  * @brief  Flush the data FIFO.\r\n  * @param  __HANDLE__: specifies the CRYP handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |=  CRYP_CR_FFLUSH)\r\n\r\n/**\r\n  * @brief  Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC.\r\n  * @param  __HANDLE__: specifies the CRYP handle.\r\n  * @param  MODE: The algorithm mode.\r\n  * @retval None\r\n  */\r\n#define __HAL_CRYP_SET_MODE(__HANDLE__, MODE)  ((__HANDLE__)->Instance->CR |= (uint32_t)(MODE))\r\n\r\n/** @brief  Check whether the specified CRYP flag is set or not.\r\n  * @param  __HANDLE__: specifies the CRYP handle.\r\n  * @param  __FLAG__: specifies the flag to check.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data \r\n  *                                 or a key preparation (for AES decryption). \r\n  *            @arg CRYP_FLAG_IFEM: Input FIFO is empty\r\n  *            @arg CRYP_FLAG_IFNF: Input FIFO is not full\r\n  *            @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending\r\n  *            @arg CRYP_FLAG_OFNE: Output FIFO is not empty\r\n  *            @arg CRYP_FLAG_OFFU: Output FIFO is full\r\n  *            @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending\r\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\r\n  */\r\n\r\n#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \\\r\n                                                 ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))\r\n\r\n/** @brief  Check whether the specified CRYP interrupt is set or not.\r\n  * @param  __HANDLE__: specifies the CRYP handle.\r\n  * @param  __INTERRUPT__: specifies the interrupt to check.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg CRYP_IT_INRIS: Input FIFO service raw interrupt is pending\r\n  *            @arg CRYP_IT_OUTRIS: Output FIFO service raw interrupt is pending\r\n  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Enable the CRYP interrupt.\r\n  * @param  __HANDLE__: specifies the CRYP handle.\r\n  * @param  __INTERRUPT__: CRYP Interrupt.\r\n  * @retval None\r\n  */\r\n#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disable the CRYP interrupt.\r\n  * @param  __HANDLE__: specifies the CRYP handle.\r\n  * @param  __INTERRUPT__: CRYP interrupt.\r\n  * @retval None\r\n  */\r\n#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__))\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/* Include CRYP HAL Extension module */\r\n#include \"stm32f7xx_hal_cryp_ex.h\"\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup CRYP_Exported_Functions CRYP Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup CRYP_Exported_Functions_Group1\r\n  * @{\r\n  */    \r\nHAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);\r\nHAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);\r\nvoid HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);\r\nvoid HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @addtogroup CRYP_Exported_Functions_Group2\r\n  * @{\r\n  */  \r\n/* AES encryption/decryption using polling  ***********************************/\r\nHAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);\r\n\r\n/* AES encryption/decryption using interrupt  *********************************/\r\nHAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\nHAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\nHAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\n\r\n/* AES encryption/decryption using DMA  ***************************************/\r\nHAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\nHAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\nHAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @addtogroup CRYP_Exported_Functions_Group3\r\n  * @{\r\n  */  \r\n/* DES encryption/decryption using polling  ***********************************/\r\nHAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);\r\n\r\n/* DES encryption/decryption using interrupt  *********************************/\r\nHAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\nHAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\n\r\n/* DES encryption/decryption using DMA  ***************************************/\r\nHAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\nHAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @addtogroup CRYP_Exported_Functions_Group4\r\n  * @{\r\n  */  \r\n/* TDES encryption/decryption using polling  **********************************/\r\nHAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);\r\n\r\n/* TDES encryption/decryption using interrupt  ********************************/\r\nHAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\nHAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\n\r\n/* TDES encryption/decryption using DMA  **************************************/\r\nHAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\nHAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @addtogroup CRYP_Exported_Functions_Group5\r\n  * @{\r\n  */  \r\nvoid HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);\r\nvoid HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);\r\nvoid HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @addtogroup CRYP_Exported_Functions_Group6\r\n  * @{\r\n  */  \r\nvoid HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @addtogroup CRYP_Exported_Functions_Group7\r\n  * @{\r\n  */  \r\nHAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/** @defgroup CRYP_Private_Types CRYP Private Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @defgroup CRYP_Private_Variables CRYP Private Variables\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup CRYP_Private_Constants CRYP Private Constants\r\n  * @{\r\n  */\r\n#define CRYP_FLAG_MASK  ((uint32_t)0x0000001F)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup CRYP_Private_Macros CRYP Private Macros\r\n  * @{\r\n  */\r\n\r\n#define IS_CRYP_KEYSIZE(__KEYSIZE__)  (((__KEYSIZE__) == CRYP_KEYSIZE_128B)  || \\\r\n                                       ((__KEYSIZE__) == CRYP_KEYSIZE_192B)  || \\\r\n                                       ((__KEYSIZE__) == CRYP_KEYSIZE_256B))\r\n\r\n\r\n#define IS_CRYP_DATATYPE(__DATATYPE__) (((__DATATYPE__) == CRYP_DATATYPE_32B) || \\\r\n                                        ((__DATATYPE__) == CRYP_DATATYPE_16B) || \\\r\n                                        ((__DATATYPE__) == CRYP_DATATYPE_8B)  || \\\r\n                                        ((__DATATYPE__) == CRYP_DATATYPE_1B))  \r\n\r\n\r\n /**\r\n  * @}\r\n  */ \r\n  \r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup CRYP_Private_Functions CRYP Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n     \r\n/**\r\n  * @}\r\n  */ \r\n\r\n#endif /* STM32F756xx || STM32F777xx || STM32F779xx */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_CRYP_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cryp_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_cryp_ex.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of CRYP HAL Extension module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_CRYP_EX_H\r\n#define __STM32F7xx_HAL_CRYP_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup CRYPEx\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/ \r\n/* Exported constants --------------------------------------------------------*/\r\n   \r\n/** @defgroup CRYPEx_Exported_Constants   CRYPEx Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CRYPEx_Exported_Constants_Group1 CRYP AlgoModeDirection\r\n  * @{\r\n  */ \r\n#define CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT   ((uint32_t)0x00080000U)\r\n#define CRYP_CR_ALGOMODE_AES_GCM_DECRYPT   ((uint32_t)0x00080004U)\r\n#define CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT   ((uint32_t)0x00080008U)\r\n#define CRYP_CR_ALGOMODE_AES_CCM_DECRYPT   ((uint32_t)0x0008000CU)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRYPEx_Exported_Constants_Group3 CRYP PhaseConfig\r\n  * @brief    The phases are relevant only to AES-GCM and AES-CCM\r\n  * @{\r\n  */ \r\n#define CRYP_PHASE_INIT           ((uint32_t)0x00000000U)\r\n#define CRYP_PHASE_HEADER         CRYP_CR_GCM_CCMPH_0\r\n#define CRYP_PHASE_PAYLOAD        CRYP_CR_GCM_CCMPH_1\r\n#define CRYP_PHASE_FINAL          CRYP_CR_GCM_CCMPH\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup CRYPEx_Exported_Macros CRYP Exported Macros\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @brief  Set the phase: Init, header, payload, final. \r\n  *         This is relevant only for GCM and CCM modes.\r\n  * @param  __HANDLE__: specifies the CRYP handle.\r\n  * @param  __PHASE__: The phase.\r\n  * @retval None\r\n  */\r\n#define __HAL_CRYP_SET_PHASE(__HANDLE__, __PHASE__)  do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\\\r\n                                                        (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\\\r\n                                                       }while(0)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup CRYPEx_Exported_Functions_Group1\r\n  * @{\r\n  */  \r\n    \r\n/* AES encryption/decryption using polling  ***********************************/\r\nHAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint32_t Size, uint8_t *AuthTag, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *AuthTag, uint32_t Timeout);\r\n\r\n/* AES encryption/decryption using interrupt  *********************************/\r\nHAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\nHAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\n\r\n/* AES encryption/decryption using DMA  ***************************************/\r\nHAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\nHAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);\r\nHAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/** @addtogroup CRYPEx_Exported_Functions_Group2\r\n  * @{\r\n  */  \r\n    \r\nvoid HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n \r\n /**\r\n  * @}\r\n  */ \r\n \r\n\r\n /* Private types -------------------------------------------------------------*/\r\n/** @defgroup CRYPEx_Private_Types CRYPEx Private Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros\r\n  * @{\r\n  */\r\n\r\n /**\r\n  * @}\r\n  */ \r\n  \r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n   \r\n/**\r\n  * @}\r\n  */ \r\n\r\n#endif /* STM32F756xx || STM32F777xx || STM32F779xx */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_CRYP_EX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_dac.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of DAC HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_DAC_H\r\n#define __STM32F7xx_HAL_DAC_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup DAC\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup DAC_Exported_Types DAC Exported Types\r\n  * @{\r\n  */\r\n\r\n/** \r\n  * @brief HAL State structures definition\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_DAC_STATE_RESET             = 0x00U,  /*!< DAC not yet initialized or disabled  */\r\n  HAL_DAC_STATE_READY             = 0x01U,  /*!< DAC initialized and ready for use    */\r\n  HAL_DAC_STATE_BUSY              = 0x02U,  /*!< DAC internal processing is ongoing   */\r\n  HAL_DAC_STATE_TIMEOUT           = 0x03U,  /*!< DAC timeout state                    */\r\n  HAL_DAC_STATE_ERROR             = 0x04U   /*!< DAC error state                      */\r\n}HAL_DAC_StateTypeDef;\r\n \r\n/** \r\n  * @brief DAC handle Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  DAC_TypeDef                 *Instance;     /*!< Register base address             */\r\n\r\n  __IO HAL_DAC_StateTypeDef   State;         /*!< DAC communication state           */\r\n\r\n  HAL_LockTypeDef             Lock;          /*!< DAC locking object                */\r\n\r\n  DMA_HandleTypeDef           *DMA_Handle1;  /*!< Pointer DMA handler for channel 1 */\r\n\r\n  DMA_HandleTypeDef           *DMA_Handle2;  /*!< Pointer DMA handler for channel 2 */\r\n\r\n  __IO uint32_t               ErrorCode;     /*!< DAC Error code                    */\r\n\r\n}DAC_HandleTypeDef;\r\n\r\n/** \r\n  * @brief DAC Configuration regular Channel structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t DAC_Trigger;       /*!< Specifies the external trigger for the selected DAC channel.\r\n                                   This parameter can be a value of @ref DAC_trigger_selection */\r\n\r\n  uint32_t DAC_OutputBuffer;  /*!< Specifies whether the DAC channel output buffer is enabled or disabled.\r\n                                   This parameter can be a value of @ref DAC_output_buffer */\r\n}DAC_ChannelConfTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup DAC_Exported_Constants DAC Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup DAC_Error_Code DAC Error Code\r\n  * @{\r\n  */\r\n#define  HAL_DAC_ERROR_NONE              0x00U    /*!< No error                          */\r\n#define  HAL_DAC_ERROR_DMAUNDERRUNCH1    0x01U    /*!< DAC channel1 DAM underrun error   */\r\n#define  HAL_DAC_ERROR_DMAUNDERRUNCH2    0x02U    /*!< DAC channel2 DAM underrun error   */\r\n#define  HAL_DAC_ERROR_DMA               0x04U    /*!< DMA error                         */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DAC_trigger_selection DAC Trigger Selection\r\n  * @{\r\n  */\r\n\r\n#define DAC_TRIGGER_NONE                   ((uint32_t)0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register \r\n                                                                       has been loaded, and not by external trigger */\r\n#define DAC_TRIGGER_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */\r\n#define DAC_TRIGGER_T4_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */\r\n#define DAC_TRIGGER_T5_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */\r\n#define DAC_TRIGGER_T6_TRGO                ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */\r\n#define DAC_TRIGGER_T7_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */\r\n#define DAC_TRIGGER_T8_TRGO                ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */                                                                       \r\n\r\n#define DAC_TRIGGER_EXT_IT9                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */\r\n#define DAC_TRIGGER_SOFTWARE               ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DAC_output_buffer  DAC Output Buffer\r\n  * @{\r\n  */\r\n#define DAC_OUTPUTBUFFER_ENABLE            ((uint32_t)0x00000000U)\r\n#define DAC_OUTPUTBUFFER_DISABLE           ((uint32_t)DAC_CR_BOFF1)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DAC_Channel_selection DAC Channel Selection\r\n  * @{\r\n  */\r\n#define DAC_CHANNEL_1                      ((uint32_t)0x00000000U)\r\n#define DAC_CHANNEL_2                      ((uint32_t)0x00000010U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DAC_data_alignment DAC Data Alignment\r\n  * @{\r\n  */\r\n#define DAC_ALIGN_12B_R                    ((uint32_t)0x00000000U)\r\n#define DAC_ALIGN_12B_L                    ((uint32_t)0x00000004U)\r\n#define DAC_ALIGN_8B_R                     ((uint32_t)0x00000008U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DAC_flags_definition DAC Flags Definition\r\n  * @{\r\n  */ \r\n#define DAC_FLAG_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)\r\n#define DAC_FLAG_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DAC_IT_definition DAC IT Definition\r\n  * @{\r\n  */ \r\n#define DAC_IT_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)\r\n#define DAC_IT_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup DAC_Exported_Macros DAC Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief Reset DAC handle state\r\n  * @param  __HANDLE__: specifies the DAC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)\r\n\r\n/** @brief Enable the DAC channel\r\n  * @param  __HANDLE__: specifies the DAC handle.\r\n  * @param  __DAC_CHANNEL__: specifies the DAC channel\r\n  * @retval None\r\n  */\r\n#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_CHANNEL__) \\\r\n((__HANDLE__)->Instance->CR |=  (DAC_CR_EN1 << (__DAC_CHANNEL__)))\r\n\r\n/** @brief Disable the DAC channel\r\n  * @param  __HANDLE__: specifies the DAC handle\r\n  * @param  __DAC_CHANNEL__: specifies the DAC channel.\r\n  * @retval None\r\n  */\r\n#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_CHANNEL__) \\\r\n((__HANDLE__)->Instance->CR &=  ~(DAC_CR_EN1 << (__DAC_CHANNEL__)))\r\n\r\n\r\n/** @brief Enable the DAC interrupt\r\n  * @param  __HANDLE__: specifies the DAC handle\r\n  * @param  __INTERRUPT__: specifies the DAC interrupt.\r\n  * @retval None\r\n  */\r\n#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))\r\n\r\n/** @brief Disable the DAC interrupt\r\n  * @param  __HANDLE__: specifies the DAC handle\r\n  * @param  __INTERRUPT__: specifies the DAC interrupt.\r\n  * @retval None\r\n  */\r\n#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))\r\n\r\n/** @brief  Checks if the specified DAC interrupt source is enabled or disabled.\r\n  * @param __HANDLE__: DAC handle\r\n  * @param __INTERRUPT__: DAC interrupt source to check\r\n  *          This parameter can be any combination of the following values:\r\n  *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt\r\n  *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt\r\n  * @retval State of interruption (SET or RESET)\r\n  */\r\n#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))\r\n\r\n/** @brief  Get the selected DAC's flag status.\r\n  * @param  __HANDLE__: specifies the DAC handle.\r\n  * @param  __FLAG__: specifies the flag to clear.\r\n  *         This parameter can be any combination of the following values:\r\n  *            @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag\r\n  *            @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag\r\n  * @retval None\r\n  */\r\n#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))\r\n\r\n/** @brief  Clear the DAC's flag.\r\n  * @param  __HANDLE__: specifies the DAC handle.\r\n  * @param  __FLAG__: specifies the flag to clear.\r\n  *         This parameter can be any combination of the following values:\r\n  *            @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag\r\n  *            @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag\r\n  * @retval None\r\n  */\r\n#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Include DAC HAL Extension module */\r\n#include \"stm32f7xx_hal_dac_ex.h\"\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup DAC_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup DAC_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n/* Initialization/de-initialization functions *********************************/\r\nHAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);\r\nHAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);\r\nvoid HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);\r\nvoid HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup DAC_Exported_Functions_Group2\r\n  * @{\r\n  */\r\n/* I/O operation functions ****************************************************/\r\nHAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);\r\nHAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);\r\nuint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup DAC_Exported_Functions_Group3\r\n  * @{\r\n  */\r\n/* Peripheral Control functions ***********************************************/\r\nHAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup DAC_Exported_Functions_Group4\r\n  * @{\r\n  */\r\n/* Peripheral State functions *************************************************/\r\nHAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);\r\nvoid HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);\r\nuint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);\r\n\r\nvoid HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);\r\nvoid HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);\r\nvoid HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);\r\nvoid HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup DAC_Private_Constants DAC Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup DAC_Private_Macros DAC Private Macros\r\n  * @{\r\n  */\r\n#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)\r\n#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \\\r\n                             ((ALIGN) == DAC_ALIGN_12B_L) || \\\r\n                             ((ALIGN) == DAC_ALIGN_8B_R))\r\n#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \\\r\n                                 ((CHANNEL) == DAC_CHANNEL_2))\r\n#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \\\r\n                                           ((STATE) == DAC_OUTPUTBUFFER_DISABLE))\r\n\r\n#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \\\r\n                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \\\r\n                                 ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \\\r\n                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \\\r\n                                 ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \\\r\n                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \\\r\n                                 ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \\\r\n                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \\\r\n                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))\r\n\r\n/** @brief Set DHR12R1 alignment\r\n  * @param  __ALIGNMENT__: specifies the DAC alignment\r\n  * @retval None\r\n  */\r\n#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008U) + (__ALIGNMENT__))\r\n\r\n/** @brief  Set DHR12R2 alignment\r\n  * @param  __ALIGNMENT__: specifies the DAC alignment\r\n  * @retval None\r\n  */\r\n#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014U) + (__ALIGNMENT__))\r\n\r\n/** @brief  Set DHR12RD alignment\r\n  * @param  __ALIGNMENT__: specifies the DAC alignment\r\n  * @retval None\r\n  */\r\n#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020U) + (__ALIGNMENT__))\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup DAC_Private_Functions DAC Private Functions\r\n  * @{\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /*__STM32F7xx_HAL_DAC_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_dac.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of DAC HAL Extension module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_DAC_EX_H\r\n#define __STM32F7xx_HAL_DAC_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup DACEx\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup DACEx_Exported_Constants DAC Exported Constants\r\n  * @{\r\n  */\r\n   \r\n/** @defgroup DACEx_lfsrunmask_triangleamplitude DAC LFS Run Mask Triangle Amplitude\r\n  * @{\r\n  */\r\n#define DAC_LFSRUNMASK_BIT0                ((uint32_t)0x00000000U) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */\r\n#define DAC_LFSRUNMASK_BITS1_0             ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */\r\n#define DAC_LFSRUNMASK_BITS2_0             ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */\r\n#define DAC_LFSRUNMASK_BITS3_0             ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */\r\n#define DAC_LFSRUNMASK_BITS4_0             ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */\r\n#define DAC_LFSRUNMASK_BITS5_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */\r\n#define DAC_LFSRUNMASK_BITS6_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */\r\n#define DAC_LFSRUNMASK_BITS7_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */\r\n#define DAC_LFSRUNMASK_BITS8_0             ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */\r\n#define DAC_LFSRUNMASK_BITS9_0             ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */\r\n#define DAC_LFSRUNMASK_BITS10_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */\r\n#define DAC_LFSRUNMASK_BITS11_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */\r\n#define DAC_TRIANGLEAMPLITUDE_1            ((uint32_t)0x00000000U) /*!< Select max triangle amplitude of 1 */\r\n#define DAC_TRIANGLEAMPLITUDE_3            ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */\r\n#define DAC_TRIANGLEAMPLITUDE_7            ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */\r\n#define DAC_TRIANGLEAMPLITUDE_15           ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */\r\n#define DAC_TRIANGLEAMPLITUDE_31           ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */\r\n#define DAC_TRIANGLEAMPLITUDE_63           ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */\r\n#define DAC_TRIANGLEAMPLITUDE_127          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */\r\n#define DAC_TRIANGLEAMPLITUDE_255          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */\r\n#define DAC_TRIANGLEAMPLITUDE_511          ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */\r\n#define DAC_TRIANGLEAMPLITUDE_1023         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */\r\n#define DAC_TRIANGLEAMPLITUDE_2047         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */\r\n#define DAC_TRIANGLEAMPLITUDE_4095         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup DACEx_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup DACEx_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n/* Extension features functions ***********************************************/\r\nuint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);\r\nHAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);\r\nHAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);\r\nHAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);\r\n\r\nvoid HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);\r\nvoid HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);\r\nvoid HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);\r\nvoid HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup DACEx_Private_Constants DAC Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup DACEx_Private_Macros DAC Private Macros\r\n  * @{\r\n  */\r\n#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \\\r\n                                                      ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \\\r\n                                                      ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \\\r\n                                                      ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \\\r\n                                                      ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \\\r\n                                                      ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \\\r\n                                                      ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \\\r\n                                                      ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \\\r\n                                                      ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \\\r\n                                                      ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \\\r\n                                                      ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \\\r\n                                                      ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \\\r\n                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \\\r\n                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \\\r\n                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \\\r\n                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \\\r\n                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \\\r\n                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \\\r\n                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \\\r\n                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \\\r\n                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \\\r\n                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \\\r\n                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \\\r\n                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup DACEx_Private_Functions DAC Private Functions\r\n  * @{\r\n  */\r\nvoid DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);\r\nvoid DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);\r\nvoid DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); \r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /*__STM32F7xx_HAL_DAC_EX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dcmi.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_dcmi.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of DCMI HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_DCMI_H\r\n#define __STM32F7xx_HAL_DCMI_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n \r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup DCMI DCMI\r\n  * @brief DCMI HAL module driver\r\n  * @{\r\n  */  \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup DCMI_Exported_Types DCMI Exported Types\r\n  * @{\r\n  */\r\n/** \r\n  * @brief  HAL DCMI State structures definition\r\n  */ \r\ntypedef enum\r\n{\r\n  HAL_DCMI_STATE_RESET             = 0x00U,  /*!< DCMI not yet initialized or disabled  */\r\n  HAL_DCMI_STATE_READY             = 0x01U,  /*!< DCMI initialized and ready for use    */\r\n  HAL_DCMI_STATE_BUSY              = 0x02U,  /*!< DCMI internal processing is ongoing   */\r\n  HAL_DCMI_STATE_TIMEOUT           = 0x03U,  /*!< DCMI timeout state                    */\r\n  HAL_DCMI_STATE_ERROR             = 0x04U,  /*!< DCMI error state                      */\r\n  HAL_DCMI_STATE_SUSPENDED         = 0x05U   /*!< DCMI suspend state                    */    \r\n}HAL_DCMI_StateTypeDef;\r\n\r\n/** \r\n  * @brief   DCMIEx Embedded Synchronisation CODE Init structure definition\r\n  */ \r\ntypedef struct\r\n{\r\n  uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */\r\n  uint8_t LineStartCode;  /*!< Specifies the code of the line start delimiter.  */\r\n  uint8_t LineEndCode;    /*!< Specifies the code of the line end delimiter.    */\r\n  uint8_t FrameEndCode;   /*!< Specifies the code of the frame end delimiter.   */\r\n}DCMI_CodesInitTypeDef;\r\n\r\n/** \r\n  * @brief   DCMI Init structure definition\r\n  */  \r\ntypedef struct\r\n{\r\n  uint32_t  SynchroMode;                /*!< Specifies the Synchronization Mode: Hardware or Embedded.\r\n                                             This parameter can be a value of @ref DCMI_Synchronization_Mode */\r\n\r\n  uint32_t  PCKPolarity;                /*!< Specifies the Pixel clock polarity: Falling or Rising.\r\n                                             This parameter can be a value of @ref DCMI_PIXCK_Polarity       */\r\n\r\n  uint32_t  VSPolarity;                 /*!< Specifies the Vertical synchronization polarity: High or Low.\r\n                                             This parameter can be a value of @ref DCMI_VSYNC_Polarity       */\r\n\r\n  uint32_t  HSPolarity;                 /*!< Specifies the Horizontal synchronization polarity: High or Low.\r\n                                             This parameter can be a value of @ref DCMI_HSYNC_Polarity       */\r\n\r\n  uint32_t  CaptureRate;                /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.\r\n                                             This parameter can be a value of @ref DCMI_Capture_Rate         */\r\n\r\n  uint32_t  ExtendedDataMode;           /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.\r\n                                             This parameter can be a value of @ref DCMI_Extended_Data_Mode   */\r\n\r\n  DCMI_CodesInitTypeDef SyncroCode;     /*!< Specifies the code of the line/frame start delimiter and the\r\n                                             line/frame end delimiter */\r\n\r\n  uint32_t JPEGMode;                    /*!< Enable or Disable the JPEG mode.                                \r\n                                             This parameter can be a value of @ref DCMI_MODE_JPEG            */\r\n\r\n  uint32_t ByteSelectMode;              /*!< Specifies the data to be captured by the interface \r\n                                            This parameter can be a value of @ref DCMI_Byte_Select_Mode      */\r\n                                            \r\n  uint32_t ByteSelectStart;             /*!< Specifies if the data to be captured by the interface is even or odd\r\n                                            This parameter can be a value of @ref DCMI_Byte_Select_Start     */\r\n\r\n  uint32_t LineSelectMode;              /*!< Specifies the line of data to be captured by the interface \r\n                                            This parameter can be a value of @ref DCMI_Line_Select_Mode      */\r\n                                            \r\n  uint32_t LineSelectStart;             /*!< Specifies if the line of data to be captured by the interface is even or odd\r\n                                            This parameter can be a value of @ref DCMI_Line_Select_Start     */\r\n}DCMI_InitTypeDef;\r\n\r\n/** \r\n  * @brief  DCMI handle Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  DCMI_TypeDef                  *Instance;           /*!< DCMI Register base address   */\r\n\r\n  DCMI_InitTypeDef              Init;                /*!< DCMI parameters              */\r\n\r\n  HAL_LockTypeDef               Lock;                /*!< DCMI locking object          */\r\n\r\n  __IO HAL_DCMI_StateTypeDef    State;               /*!< DCMI state                   */\r\n\r\n  __IO uint32_t                 XferCount;           /*!< DMA transfer counter         */\r\n\r\n  __IO uint32_t                 XferSize;            /*!< DMA transfer size            */\r\n\r\n  uint32_t                      XferTransferNumber;  /*!< DMA transfer number          */\r\n\r\n  uint32_t                      pBuffPtr;            /*!< Pointer to DMA output buffer */\r\n\r\n  DMA_HandleTypeDef             *DMA_Handle;         /*!< Pointer to the DMA handler   */\r\n\r\n  __IO uint32_t                 ErrorCode;           /*!< DCMI Error code              */\r\n\r\n}DCMI_HandleTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup DCMI_Exported_Constants DCMI Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup DCMI_Error_Code DCMI Error Code\r\n  * @{\r\n  */\r\n#define HAL_DCMI_ERROR_NONE      ((uint32_t)0x00000000U)    /*!< No error              */\r\n#define HAL_DCMI_ERROR_OVR       ((uint32_t)0x00000001U)    /*!< Overrun error         */\r\n#define HAL_DCMI_ERROR_SYNC      ((uint32_t)0x00000002U)    /*!< Synchronization error */\r\n#define HAL_DCMI_ERROR_TIMEOUT   ((uint32_t)0x00000020U)    /*!< Timeout error         */\r\n#define HAL_DCMI_ERROR_DMA       ((uint32_t)0x00000040U)    /*!< DMA error             */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DCMI_Capture_Mode DCMI Capture Mode\r\n  * @{\r\n  */ \r\n#define DCMI_MODE_CONTINUOUS           ((uint32_t)0x00000000U)  /*!< The received data are transferred continuously \r\n                                                                    into the destination memory through the DMA             */\r\n#define DCMI_MODE_SNAPSHOT             ((uint32_t)DCMI_CR_CM)  /*!< Once activated, the interface waits for the start of \r\n                                                                    frame and then transfers a single frame through the DMA */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode\r\n  * @{\r\n  */ \r\n#define DCMI_SYNCHRO_HARDWARE        ((uint32_t)0x00000000U)   /*!< Hardware synchronization data capture (frame/line start/stop)\r\n                                                                   is synchronized with the HSYNC/VSYNC signals                  */\r\n#define DCMI_SYNCHRO_EMBEDDED        ((uint32_t)DCMI_CR_ESS)  /*!< Embedded synchronization data capture is synchronized with \r\n                                                                   synchronization codes embedded in the data flow               */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DCMI_PIXCK_Polarity DCMI PIXCK Polarity\r\n  * @{\r\n  */\r\n#define DCMI_PCKPOLARITY_FALLING    ((uint32_t)0x00000000U)      /*!< Pixel clock active on Falling edge */\r\n#define DCMI_PCKPOLARITY_RISING     ((uint32_t)DCMI_CR_PCKPOL)  /*!< Pixel clock active on Rising edge  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity\r\n  * @{\r\n  */\r\n#define DCMI_VSPOLARITY_LOW     ((uint32_t)0x00000000U)     /*!< Vertical synchronization active Low  */\r\n#define DCMI_VSPOLARITY_HIGH    ((uint32_t)DCMI_CR_VSPOL)  /*!< Vertical synchronization active High */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity\r\n  * @{\r\n  */ \r\n#define DCMI_HSPOLARITY_LOW     ((uint32_t)0x00000000U)     /*!< Horizontal synchronization active Low  */\r\n#define DCMI_HSPOLARITY_HIGH    ((uint32_t)DCMI_CR_HSPOL)  /*!< Horizontal synchronization active High */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DCMI_MODE_JPEG DCMI MODE JPEG\r\n  * @{\r\n  */\r\n#define DCMI_JPEG_DISABLE   ((uint32_t)0x00000000U)    /*!< Mode JPEG Disabled  */\r\n#define DCMI_JPEG_ENABLE    ((uint32_t)DCMI_CR_JPEG)  /*!< Mode JPEG Enabled   */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DCMI_Capture_Rate DCMI Capture Rate\r\n  * @{\r\n  */\r\n#define DCMI_CR_ALL_FRAME            ((uint32_t)0x00000000U)      /*!< All frames are captured        */\r\n#define DCMI_CR_ALTERNATE_2_FRAME    ((uint32_t)DCMI_CR_FCRC_0)  /*!< Every alternate frame captured */\r\n#define DCMI_CR_ALTERNATE_4_FRAME    ((uint32_t)DCMI_CR_FCRC_1)  /*!< One frame in 4 frames captured */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode\r\n  * @{\r\n  */\r\n#define DCMI_EXTEND_DATA_8B     ((uint32_t)0x00000000U)                       /*!< Interface captures 8-bit data on every pixel clock  */\r\n#define DCMI_EXTEND_DATA_10B    ((uint32_t)DCMI_CR_EDM_0)                    /*!< Interface captures 10-bit data on every pixel clock */\r\n#define DCMI_EXTEND_DATA_12B    ((uint32_t)DCMI_CR_EDM_1)                    /*!< Interface captures 12-bit data on every pixel clock */\r\n#define DCMI_EXTEND_DATA_14B    ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1))  /*!< Interface captures 14-bit data on every pixel clock */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate \r\n  * @{\r\n  */\r\n#define DCMI_WINDOW_COORDINATE    ((uint32_t)0x3FFFU)  /*!< Window coordinate */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DCMI_Window_Height DCMI Window Height\r\n  * @{\r\n  */ \r\n#define DCMI_WINDOW_HEIGHT    ((uint32_t)0x1FFFU)  /*!< Window Height */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DCMI_interrupt_sources  DCMI interrupt sources\r\n  * @{\r\n  */\r\n#define DCMI_IT_FRAME    ((uint32_t)DCMI_IER_FRAME_IE)    /*!< Capture complete interrupt      */\r\n#define DCMI_IT_OVR      ((uint32_t)DCMI_IER_OVR_IE)      /*!< Overrun interrupt               */\r\n#define DCMI_IT_ERR      ((uint32_t)DCMI_IER_ERR_IE)      /*!< Synchronization error interrupt */\r\n#define DCMI_IT_VSYNC    ((uint32_t)DCMI_IER_VSYNC_IE)    /*!< VSYNC interrupt                 */\r\n#define DCMI_IT_LINE     ((uint32_t)DCMI_IER_LINE_IE)     /*!< Line interrupt                  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DCMI_Flags DCMI Flags\r\n  * @{\r\n  */\r\n\r\n/** \r\n  * @brief   DCMI SR register\r\n  */ \r\n#define DCMI_FLAG_HSYNC     ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC) /*!< HSYNC pin state (active line / synchronization between lines)   */\r\n#define DCMI_FLAG_VSYNC     ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC) /*!< VSYNC pin state (active frame / synchronization between frames) */\r\n#define DCMI_FLAG_FNE       ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE)   /*!< FIFO not empty flag                                                 */\r\n/** \r\n  * @brief   DCMI RIS register  \r\n  */ \r\n#define DCMI_FLAG_FRAMERI    ((uint32_t)DCMI_RIS_FRAME_RIS)  /*!< Frame capture complete interrupt flag */ \r\n#define DCMI_FLAG_OVRRI      ((uint32_t)DCMI_RIS_OVR_RIS)    /*!< Overrun interrupt flag                */ \r\n#define DCMI_FLAG_ERRRI      ((uint32_t)DCMI_RIS_ERR_RIS)    /*!< Synchronization error interrupt flag  */ \r\n#define DCMI_FLAG_VSYNCRI    ((uint32_t)DCMI_RIS_VSYNC_RIS)  /*!< VSYNC interrupt flag                  */ \r\n#define DCMI_FLAG_LINERI     ((uint32_t)DCMI_RIS_LINE_RIS)   /*!< Line interrupt flag                   */ \r\n/** \r\n  * @brief   DCMI MIS register  \r\n  */ \r\n#define DCMI_FLAG_FRAMEMI    ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS)  /*!< DCMI Frame capture complete masked interrupt status */      \r\n#define DCMI_FLAG_OVRMI      ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS  )  /*!< DCMI Overrun masked interrupt status                */               \r\n#define DCMI_FLAG_ERRMI      ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS  )  /*!< DCMI Synchronization error masked interrupt status  */ \r\n#define DCMI_FLAG_VSYNCMI    ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS)  /*!< DCMI VSYNC masked interrupt status                  */                 \r\n#define DCMI_FLAG_LINEMI     ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS )  /*!< DCMI Line masked interrupt status                   */                  \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup DCMI_Byte_Select_Mode DCMI Byte Select Mode\r\n  * @{\r\n  */\r\n#define DCMI_BSM_ALL                 ((uint32_t)0x00000000U) /*!< Interface captures all received data */\r\n#define DCMI_BSM_OTHER               ((uint32_t)DCMI_CR_BSM_0) /*!< Interface captures every other byte from the received data */\r\n#define DCMI_BSM_ALTERNATE_4         ((uint32_t)DCMI_CR_BSM_1) /*!< Interface captures one byte out of four */\r\n#define DCMI_BSM_ALTERNATE_2         ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1)) /*!< Interface captures two bytes out of four */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DCMI_Byte_Select_Start DCMI Byte Select Start\r\n  * @{\r\n  */ \r\n#define DCMI_OEBS_ODD               ((uint32_t)0x00000000U) /*!< Interface captures first data from the frame/line start, second one being dropped */\r\n#define DCMI_OEBS_EVEN              ((uint32_t)DCMI_CR_OEBS) /*!< Interface captures second data from the frame/line start, first one being dropped */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DCMI_Line_Select_Mode DCMI Line Select Mode\r\n  * @{\r\n  */\r\n#define DCMI_LSM_ALL                 ((uint32_t)0x00000000U) /*!< Interface captures all received lines */\r\n#define DCMI_LSM_ALTERNATE_2         ((uint32_t)DCMI_CR_LSM) /*!< Interface captures one line out of two */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DCMI_Line_Select_Start DCMI Line Select Start\r\n  * @{\r\n  */ \r\n#define DCMI_OELS_ODD               ((uint32_t)0x00000000U) /*!< Interface captures first line from the frame start, second one being dropped */\r\n#define DCMI_OELS_EVEN              ((uint32_t)DCMI_CR_OELS) /*!< Interface captures second line from the frame start, first one being dropped */\r\n\r\n/**\r\n  * @}\r\n  */\r\n    \r\n/**\r\n  * @}\r\n  */\r\n \r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup DCMI_Exported_Macros DCMI Exported Macros\r\n  * @{\r\n  */\r\n  \r\n/** @brief Reset DCMI handle state\r\n  * @param  __HANDLE__: specifies the DCMI handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)\r\n\r\n/**\r\n  * @brief  Enable the DCMI.\r\n  * @param  __HANDLE__: DCMI handle\r\n  * @retval None\r\n  */\r\n#define __HAL_DCMI_ENABLE(__HANDLE__)    ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)\r\n\r\n/**\r\n  * @brief  Disable the DCMI.\r\n  * @param  __HANDLE__: DCMI handle\r\n  * @retval None\r\n  */\r\n#define __HAL_DCMI_DISABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))\r\n\r\n/* Interrupt & Flag management */\r\n/**\r\n  * @brief  Get the DCMI pending flag.\r\n  * @param  __HANDLE__: DCMI handle\r\n  * @param  __FLAG__: Get the specified flag.\r\n  *         This parameter can be one of the following values (no combination allowed)\r\n  *            @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines)   \r\n  *            @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames) \r\n  *            @arg DCMI_FLAG_FNE: FIFO empty flag                                                  \r\n  *            @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask\r\n  *            @arg DCMI_FLAG_OVRRI: Overrun flag mask\r\n  *            @arg DCMI_FLAG_ERRRI: Synchronization error flag mask\r\n  *            @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask\r\n  *            @arg DCMI_FLAG_LINERI: Line flag mask\r\n  *            @arg DCMI_FLAG_FRAMEMI: DCMI Capture complete masked interrupt status      \r\n  *            @arg DCMI_FLAG_OVRMI: DCMI Overrun masked interrupt status               \r\n  *            @arg DCMI_FLAG_ERRMI: DCMI Synchronization error masked interrupt status \r\n  *            @arg DCMI_FLAG_VSYNCMI: DCMI VSYNC masked interrupt status                 \r\n  *            @arg DCMI_FLAG_LINEMI: DCMI Line masked interrupt status                  \r\n  * @retval The state of FLAG.\r\n  */\r\n#define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\\\r\n((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0)? ((__HANDLE__)->Instance->RIS & (__FLAG__)) :\\\r\n (((__FLAG__) & DCMI_SR_INDEX) == 0x0)? ((__HANDLE__)->Instance->MIS & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__)))\r\n\r\n/**\r\n  * @brief  Clear the DCMI pending flags.\r\n  * @param  __HANDLE__: DCMI handle\r\n  * @param  __FLAG__: specifies the flag to clear.\r\n  *         This parameter can be any combination of the following values:\r\n  *            @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask\r\n  *            @arg DCMI_FLAG_OVFRI: Overflow flag mask\r\n  *            @arg DCMI_FLAG_ERRRI: Synchronization error flag mask\r\n  *            @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask\r\n  *            @arg DCMI_FLAG_LINERI: Line flag mask\r\n  * @retval None\r\n  */\r\n#define __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))\r\n\r\n/**\r\n  * @brief  Enable the specified DCMI interrupts.\r\n  * @param  __HANDLE__:    DCMI handle\r\n  * @param  __INTERRUPT__: specifies the DCMI interrupt sources to be enabled. \r\n  *         This parameter can be any combination of the following values:\r\n  *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask\r\n  *            @arg DCMI_IT_OVF: Overflow interrupt mask\r\n  *            @arg DCMI_IT_ERR: Synchronization error interrupt mask\r\n  *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask\r\n  *            @arg DCMI_IT_LINE: Line interrupt mask\r\n  * @retval None\r\n  */\r\n#define __HAL_DCMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disable the specified DCMI interrupts.\r\n  * @param  __HANDLE__: DCMI handle\r\n  * @param  __INTERRUPT__: specifies the DCMI interrupt sources to be enabled. \r\n  *         This parameter can be any combination of the following values:\r\n  *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask\r\n  *            @arg DCMI_IT_OVF: Overflow interrupt mask\r\n  *            @arg DCMI_IT_ERR: Synchronization error interrupt mask\r\n  *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask\r\n  *            @arg DCMI_IT_LINE: Line interrupt mask\r\n  * @retval None\r\n  */\r\n#define __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Check whether the specified DCMI interrupt has occurred or not.\r\n  * @param  __HANDLE__: DCMI handle\r\n  * @param  __INTERRUPT__: specifies the DCMI interrupt source to check.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask\r\n  *            @arg DCMI_IT_OVF: Overflow interrupt mask\r\n  *            @arg DCMI_IT_ERR: Synchronization error interrupt mask\r\n  *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask\r\n  *            @arg DCMI_IT_LINE: Line interrupt mask\r\n  * @retval The state of INTERRUPT.\r\n  */\r\n#define __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__))\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup DCMI_Exported_Functions DCMI Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions\r\n * @{\r\n */\r\n/* Initialization and de-initialization functions *****************************/\r\nHAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);\r\nHAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);\r\nvoid       HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi);\r\nvoid       HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi);\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @addtogroup DCMI_Exported_Functions_Group2 IO operation functions\r\n * @{\r\n */\r\n/* IO operation functions *****************************************************/\r\nHAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);\r\nHAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi);\r\nHAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi);\r\nHAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi);\r\nvoid       HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi);\r\nvoid       HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi);\r\nvoid       HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi);\r\nvoid       HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi);\r\nvoid       HAL_DCMI_VsyncCallback(DCMI_HandleTypeDef *hdcmi);\r\nvoid       HAL_DCMI_HsyncCallback(DCMI_HandleTypeDef *hdcmi);\r\nvoid       HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @addtogroup DCMI_Exported_Functions_Group3 Peripheral Control functions\r\n * @{\r\n */\r\n/* Peripheral Control functions ***********************************************/\r\nHAL_StatusTypeDef     HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);\r\nHAL_StatusTypeDef     HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi);\r\nHAL_StatusTypeDef     HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi);\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @addtogroup DCMI_Exported_Functions_Group4 Peripheral State functions\r\n * @{\r\n */\r\n/* Peripheral State functions *************************************************/\r\nHAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi);\r\nuint32_t              HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup DCMI_Private_Constants DCMI Private Constants\r\n  * @{\r\n  */\r\n#define DCMI_MIS_INDEX        ((uint32_t)0x1000) /*!< DCMI MIS register index */\r\n#define DCMI_SR_INDEX         ((uint32_t)0x2000) /*!< DCMI SR register index  */   \r\n/**\r\n  * @}\r\n  */   \r\n/* Private macro -------------------------------------------------------------*/\r\n/** @defgroup DCMI_Private_Macros DCMI Private Macros\r\n  * @{\r\n  */\r\n#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \\\r\n                                   ((MODE) == DCMI_MODE_SNAPSHOT))\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t \r\n#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \\\r\n                              ((MODE) == DCMI_SYNCHRO_EMBEDDED))\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\r\n#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \\\r\n                                      ((POLARITY) == DCMI_PCKPOLARITY_RISING))\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\r\n#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \\\r\n                                     ((POLARITY) == DCMI_VSPOLARITY_HIGH))\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t \r\n#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \\\r\n                                     ((POLARITY) == DCMI_HSPOLARITY_HIGH))\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t \r\n#define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \\\r\n                                     ((JPEG_MODE) == DCMI_JPEG_ENABLE))\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t \r\n#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME)         || \\\r\n                                    ((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \\\r\n                                    ((RATE) == DCMI_CR_ALTERNATE_4_FRAME))\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\r\n#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B)  || \\\r\n                                    ((DATA) == DCMI_EXTEND_DATA_10B) || \\\r\n                                    ((DATA) == DCMI_EXTEND_DATA_12B) || \\\r\n                                    ((DATA) == DCMI_EXTEND_DATA_14B))\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\r\n#define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)\r\n\r\n#define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)\r\n\r\n#define IS_DCMI_BYTE_SELECT_MODE(MODE)(((MODE) == DCMI_BSM_ALL) || \\\r\n                                       ((MODE) == DCMI_BSM_OTHER) || \\\r\n                                       ((MODE) == DCMI_BSM_ALTERNATE_4) || \\\r\n                                       ((MODE) == DCMI_BSM_ALTERNATE_2))\r\n                                                                                                \r\n#define IS_DCMI_BYTE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OEBS_ODD) || \\\r\n                                            ((POLARITY) == DCMI_OEBS_EVEN))\r\n                              \r\n#define IS_DCMI_LINE_SELECT_MODE(MODE)(((MODE) == DCMI_LSM_ALL) || \\\r\n                                       ((MODE) == DCMI_LSM_ALTERNATE_2))\r\n                                      \r\n#define IS_DCMI_LINE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OELS_ODD) || \\\r\n                                            ((POLARITY) == DCMI_OELS_EVEN))\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @addtogroup DCMI_Private_Functions DCMI Private Functions\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */\r\n      \r\n/**\r\n  * @}\r\n  */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_DCMI_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dcmi_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_dcmi_ex.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of DCMI Extension HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_DCMI_EX_H\r\n#define __STM32F7xx_HAL_DCMI_EX_H\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n/* Exported macro ------------------------------------------------------------*/      \r\n/* Exported functions --------------------------------------------------------*/\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/   \r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n#endif /* __STM32F7xx_HAL_DCMI_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_def.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   This file contains HAL common defines, enumeration, macros and \r\n  *          structures definitions. \r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_DEF\r\n#define __STM32F7xx_HAL_DEF\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx.h\"\r\n#include \"Legacy/stm32_hal_legacy.h\"\r\n#include <stdio.h>\r\n/* Exported types ------------------------------------------------------------*/\r\n\r\n/** \r\n  * @brief  HAL Status structures definition  \r\n  */  \r\ntypedef enum \r\n{\r\n  HAL_OK       = 0x00U,\r\n  HAL_ERROR    = 0x01U,\r\n  HAL_BUSY     = 0x02U,\r\n  HAL_TIMEOUT  = 0x03U\r\n} HAL_StatusTypeDef;\r\n\r\n/** \r\n  * @brief  HAL Lock structures definition  \r\n  */\r\ntypedef enum \r\n{\r\n  HAL_UNLOCKED = 0x00,\r\n  HAL_LOCKED   = 0x01  \r\n} HAL_LockTypeDef;\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n#define HAL_MAX_DELAY      0xFFFFFFFFU\r\n\r\n#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) != RESET)\r\n#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == RESET)\r\n\r\n#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__)               \\\r\n                        do{                                                      \\\r\n                              (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \\\r\n                              (__DMA_HANDLE__).Parent = (__HANDLE__);             \\\r\n                          } while(0)\r\n\r\n#define UNUSED(x) ((void)(x))\r\n\r\n/** @brief Reset the Handle's State field.\r\n  * @param __HANDLE__: specifies the Peripheral Handle.\r\n  * @note  This macro can be used for the following purpose: \r\n  *          - When the Handle is declared as local variable; before passing it as parameter\r\n  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro \r\n  *            to set to 0 the Handle's \"State\" field.\r\n  *            Otherwise, \"State\" field may have any random value and the first time the function \r\n  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed\r\n  *            (i.e. HAL_PPP_MspInit() will not be executed).\r\n  *          - When there is a need to reconfigure the low level hardware: instead of calling\r\n  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().\r\n  *            In this later function, when the Handle's \"State\" field is set to 0, it will execute the function\r\n  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.\r\n  * @retval None\r\n  */\r\n#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)\r\n\r\n#if (USE_RTOS == 1)\r\n  /* Reserved for future use */\r\n  #error \"USE_RTOS should be 0 in the current HAL release\"\r\n#else\r\n  #define __HAL_LOCK(__HANDLE__)                                           \\\r\n                                do{                                        \\\r\n                                    if((__HANDLE__)->Lock == HAL_LOCKED)   \\\r\n                                    {                                      \\\r\n                                       return HAL_BUSY;                    \\\r\n                                    }                                      \\\r\n                                    else                                   \\\r\n                                    {                                      \\\r\n                                       (__HANDLE__)->Lock = HAL_LOCKED;    \\\r\n                                    }                                      \\\r\n                                  }while (0)\r\n\r\n  #define __HAL_UNLOCK(__HANDLE__)                                          \\\r\n                                  do{                                       \\\r\n                                      (__HANDLE__)->Lock = HAL_UNLOCKED;    \\\r\n                                    }while (0)\r\n#endif /* USE_RTOS */\r\n\r\n#if  defined ( __GNUC__ )\r\n  #ifndef __weak\r\n    #define __weak   __attribute__((weak))\r\n  #endif /* __weak */\r\n  #ifndef __packed\r\n    #define __packed __attribute__((__packed__))\r\n  #endif /* __packed */\r\n#endif /* __GNUC__ */\r\n\r\n\r\n/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive \"#pragma data_alignment=4\" must be used instead */\r\n#if defined   (__GNUC__)        /* GNU Compiler */\r\n  #ifndef __ALIGN_END\r\n    #define __ALIGN_END    __attribute__ ((aligned (4)))\r\n  #endif /* __ALIGN_END */\r\n  #ifndef __ALIGN_BEGIN  \r\n    #define __ALIGN_BEGIN\r\n  #endif /* __ALIGN_BEGIN */\r\n#else\r\n  #ifndef __ALIGN_END\r\n    #define __ALIGN_END\r\n  #endif /* __ALIGN_END */\r\n  #ifndef __ALIGN_BEGIN      \r\n    #if defined   (__CC_ARM)      /* ARM Compiler */\r\n      #define __ALIGN_BEGIN    __align(4)  \r\n    #elif defined (__ICCARM__)    /* IAR Compiler */\r\n      #define __ALIGN_BEGIN \r\n    #endif /* __CC_ARM */\r\n  #endif /* __ALIGN_BEGIN */\r\n#endif /* __GNUC__ */\r\n\r\n\r\n/** \r\n  * @brief  __RAM_FUNC definition\r\n  */ \r\n#if defined ( __CC_ARM   )\r\n/* ARM Compiler\r\n   ------------\r\n   RAM functions are defined using the toolchain options. \r\n   Functions that are executed in RAM should reside in a separate source module.\r\n   Using the 'Options for File' dialog you can simply change the 'Code / Const' \r\n   area of a module to a memory space in physical RAM.\r\n   Available memory areas are declared in the 'Target' tab of the 'Options for Target'\r\n   dialog. \r\n*/\r\n#define __RAM_FUNC HAL_StatusTypeDef \r\n\r\n#elif defined ( __ICCARM__ )\r\n/* ICCARM Compiler\r\n   ---------------\r\n   RAM functions are defined using a specific toolchain keyword \"__ramfunc\". \r\n*/\r\n#define __RAM_FUNC __ramfunc HAL_StatusTypeDef\r\n\r\n#elif defined   (  __GNUC__  )\r\n/* GNU Compiler\r\n   ------------\r\n  RAM functions are defined using a specific toolchain attribute \r\n   \"__attribute__((section(\".RamFunc\")))\".\r\n*/\r\n#define __RAM_FUNC HAL_StatusTypeDef  __attribute__((section(\".RamFunc\")))\r\n\r\n#endif\r\n\r\n/** \r\n  * @brief  __NOINLINE definition\r\n  */ \r\n#if defined ( __CC_ARM   ) || defined   (  __GNUC__  )\r\n/* ARM & GNUCompiler \r\n   ---------------- \r\n*/\r\n#define __NOINLINE __attribute__ ( (noinline) )\r\n\r\n#elif defined ( __ICCARM__ )\r\n/* ICCARM Compiler\r\n   ---------------\r\n*/\r\n#define __NOINLINE _Pragma(\"optimize = no_inline\")\r\n\r\n#endif\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* ___STM32F7xx_HAL_DEF */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dfsdm.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_dfsdm.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of DFSDM HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_DFSDM_H\r\n#define __STM32F7xx_HAL_DFSDM_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup DFSDM\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup DFSDM_Exported_Types DFSDM Exported Types\r\n  * @{\r\n  */\r\n\r\n/** \r\n  * @brief  HAL DFSDM Channel states definition  \r\n  */ \r\ntypedef enum\r\n{\r\n  HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */\r\n  HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */\r\n  HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU  /*!< DFSDM channel state error */\r\n}HAL_DFSDM_Channel_StateTypeDef;\r\n\r\n/** \r\n  * @brief  DFSDM channel output clock structure definition  \r\n  */  \r\ntypedef struct\r\n{\r\n  FunctionalState Activation; /*!< Output clock enable/disable */\r\n  uint32_t        Selection;  /*!< Output clock is system clock or audio clock.\r\n                                   This parameter can be a value of @ref DFSDM_Channel_OuputClock */\r\n  uint32_t        Divider;    /*!< Output clock divider.\r\n                                   This parameter must be a number between Min_Data = 2 and Max_Data = 256 */\r\n}DFSDM_Channel_OutputClockTypeDef;\r\n\r\n/** \r\n  * @brief  DFSDM channel input structure definition  \r\n  */  \r\ntypedef struct\r\n{\r\n  uint32_t Multiplexer; /*!< Input is external serial inputs or internal register.\r\n                             This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */\r\n  uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register.\r\n                             This parameter can be a value of @ref DFSDM_Channel_DataPacking */\r\n  uint32_t Pins;        /*!< Input pins are taken from same or following channel.\r\n                             This parameter can be a value of @ref DFSDM_Channel_InputPins */\r\n}DFSDM_Channel_InputTypeDef;\r\n\r\n/** \r\n  * @brief  DFSDM channel serial interface structure definition  \r\n  */  \r\ntypedef struct\r\n{\r\n  uint32_t Type;     /*!< SPI or Manchester modes.\r\n                          This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */\r\n  uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point).\r\n                          This parameter can be a value of @ref DFSDM_Channel_SpiClock */\r\n}DFSDM_Channel_SerialInterfaceTypeDef;\r\n\r\n/** \r\n  * @brief  DFSDM channel analog watchdog structure definition  \r\n  */  \r\ntypedef struct\r\n{\r\n  uint32_t FilterOrder;  /*!< Analog watchdog Sinc filter order.\r\n                              This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */\r\n  uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio.\r\n                              This parameter must be a number between Min_Data = 1 and Max_Data = 32 */\r\n}DFSDM_Channel_AwdTypeDef;\r\n\r\n/** \r\n  * @brief  DFSDM channel init structure definition  \r\n  */  \r\ntypedef struct\r\n{\r\n  DFSDM_Channel_OutputClockTypeDef     OutputClock;     /*!< DFSDM channel output clock parameters */\r\n  DFSDM_Channel_InputTypeDef           Input;           /*!< DFSDM channel input parameters */\r\n  DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */\r\n  DFSDM_Channel_AwdTypeDef             Awd;             /*!< DFSDM channel analog watchdog parameters */\r\n  int32_t                              Offset;          /*!< DFSDM channel offset.\r\n                                                             This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */\r\n  uint32_t                             RightBitShift;   /*!< DFSDM channel right bit shift.\r\n                                                             This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */\r\n}DFSDM_Channel_InitTypeDef;\r\n\r\n/** \r\n  * @brief  DFSDM channel handle structure definition  \r\n  */  \r\ntypedef struct\r\n{\r\n  DFSDM_Channel_TypeDef          *Instance; /*!< DFSDM channel instance */\r\n  DFSDM_Channel_InitTypeDef      Init;      /*!< DFSDM channel init parameters */\r\n  HAL_DFSDM_Channel_StateTypeDef State;     /*!< DFSDM channel state */\r\n}DFSDM_Channel_HandleTypeDef;\r\n\r\n/** \r\n  * @brief  HAL DFSDM Filter states definition  \r\n  */ \r\ntypedef enum\r\n{\r\n  HAL_DFSDM_FILTER_STATE_RESET   = 0x00U, /*!< DFSDM filter not initialized */\r\n  HAL_DFSDM_FILTER_STATE_READY   = 0x01U, /*!< DFSDM filter initialized and ready for use */\r\n  HAL_DFSDM_FILTER_STATE_REG     = 0x02U, /*!< DFSDM filter regular conversion in progress */\r\n  HAL_DFSDM_FILTER_STATE_INJ     = 0x03U, /*!< DFSDM filter injected conversion in progress */\r\n  HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */\r\n  HAL_DFSDM_FILTER_STATE_ERROR   = 0xFFU  /*!< DFSDM filter state error */\r\n}HAL_DFSDM_Filter_StateTypeDef;\r\n\r\n/** \r\n  * @brief  DFSDM filter regular conversion parameters structure definition  \r\n  */  \r\ntypedef struct\r\n{\r\n  uint32_t        Trigger;  /*!< Trigger used to start regular conversion: software or synchronous.\r\n                                 This parameter can be a value of @ref DFSDM_Filter_Trigger */\r\n  FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */\r\n  FunctionalState DmaMode;  /*!< Enable/disable DMA for regular conversion */\r\n}DFSDM_Filter_RegularParamTypeDef;\r\n\r\n/** \r\n  * @brief  DFSDM filter injected conversion parameters structure definition  \r\n  */  \r\ntypedef struct\r\n{\r\n  uint32_t        Trigger;        /*!< Trigger used to start injected conversion: software, external or synchronous.\r\n                                       This parameter can be a value of @ref DFSDM_Filter_Trigger */\r\n  FunctionalState ScanMode;       /*!< Enable/disable scanning mode for injected conversion */\r\n  FunctionalState DmaMode;        /*!< Enable/disable DMA for injected conversion */\r\n  uint32_t        ExtTrigger;     /*!< External trigger.\r\n                                       This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */\r\n  uint32_t        ExtTriggerEdge; /*!< External trigger edge: rising, falling or both.\r\n                                       This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */\r\n}DFSDM_Filter_InjectedParamTypeDef;\r\n\r\n/** \r\n  * @brief  DFSDM filter parameters structure definition  \r\n  */  \r\ntypedef struct\r\n{\r\n  uint32_t SincOrder;       /*!< Sinc filter order.\r\n                                 This parameter can be a value of @ref DFSDM_Filter_SincOrder */\r\n  uint32_t Oversampling;    /*!< Filter oversampling ratio.\r\n                                 This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */\r\n  uint32_t IntOversampling; /*!< Integrator oversampling ratio.\r\n                                 This parameter must be a number between Min_Data = 1 and Max_Data = 256 */\r\n}DFSDM_Filter_FilterParamTypeDef;\r\n\r\n/** \r\n  * @brief  DFSDM filter init structure definition  \r\n  */  \r\ntypedef struct\r\n{\r\n  DFSDM_Filter_RegularParamTypeDef  RegularParam;  /*!< DFSDM regular conversion parameters */\r\n  DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */\r\n  DFSDM_Filter_FilterParamTypeDef   FilterParam;   /*!< DFSDM filter parameters */\r\n}DFSDM_Filter_InitTypeDef;\r\n\r\n/** \r\n  * @brief  DFSDM filter handle structure definition  \r\n  */  \r\ntypedef struct\r\n{\r\n  DFSDM_Filter_TypeDef          *Instance;           /*!< DFSDM filter instance */\r\n  DFSDM_Filter_InitTypeDef      Init;                /*!< DFSDM filter init parameters */\r\n  DMA_HandleTypeDef             *hdmaReg;            /*!< Pointer on DMA handler for regular conversions */\r\n  DMA_HandleTypeDef             *hdmaInj;            /*!< Pointer on DMA handler for injected conversions */\r\n  uint32_t                      RegularContMode;     /*!< Regular conversion continuous mode */\r\n  uint32_t                      RegularTrigger;      /*!< Trigger used for regular conversion */\r\n  uint32_t                      InjectedTrigger;     /*!< Trigger used for injected conversion */\r\n  uint32_t                      ExtTriggerEdge;      /*!< Rising, falling or both edges selected */\r\n  FunctionalState               InjectedScanMode;    /*!< Injected scanning mode */\r\n  uint32_t                      InjectedChannelsNbr; /*!< Number of channels in injected sequence */\r\n  uint32_t                      InjConvRemaining;    /*!< Injected conversions remaining */\r\n  HAL_DFSDM_Filter_StateTypeDef State;               /*!< DFSDM filter state */\r\n  uint32_t                      ErrorCode;           /*!< DFSDM filter error code */  \r\n}DFSDM_Filter_HandleTypeDef;\r\n\r\n/** \r\n  * @brief  DFSDM filter analog watchdog parameters structure definition  \r\n  */  \r\ntypedef struct\r\n{\r\n  uint32_t DataSource;      /*!< Values from digital filter or from channel watchdog filter.\r\n                                 This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */\r\n  uint32_t Channel;         /*!< Analog watchdog channel selection.\r\n                                 This parameter can be a values combination of @ref DFSDM_Channel_Selection */\r\n  int32_t  HighThreshold;   /*!< High threshold for the analog watchdog.\r\n                                 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */\r\n  int32_t  LowThreshold;    /*!< Low threshold for the analog watchdog.\r\n                                 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */\r\n  uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event.\r\n                                 This parameter can be a values combination of @ref DFSDM_BreakSignals */\r\n  uint32_t LowBreakSignal;  /*!< Break signal assigned to analog watchdog low threshold event.\r\n                                 This parameter can be a values combination of @ref DFSDM_BreakSignals */\r\n}DFSDM_Filter_AwdParamTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */ \r\n/* End of exported types -----------------------------------------------------*/\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection\r\n  * @{\r\n  */\r\n#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM    ((uint32_t)0x00000000U) /*!< Source for ouput clock is system clock */\r\n#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO     DFSDM_CHCFGR1_CKOUTSRC  /*!< Source for ouput clock is audio clock */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer\r\n  * @{\r\n  */\r\n#define DFSDM_CHANNEL_EXTERNAL_INPUTS    ((uint32_t)0x00000000U) /*!< Data are taken from external inputs */\r\n#define DFSDM_CHANNEL_INTERNAL_REGISTER  DFSDM_CHCFGR1_DATMPX_1  /*!< Data are taken from internal register */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing\r\n  * @{\r\n  */\r\n#define DFSDM_CHANNEL_STANDARD_MODE         ((uint32_t)0x00000000U) /*!< Standard data packing mode */\r\n#define DFSDM_CHANNEL_INTERLEAVED_MODE      DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */\r\n#define DFSDM_CHANNEL_DUAL_MODE             DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins\r\n  * @{\r\n  */\r\n#define DFSDM_CHANNEL_SAME_CHANNEL_PINS      ((uint32_t)0x00000000U) /*!< Input from pins on same channel */\r\n#define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL   /*!< Input from pins on following channel */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type\r\n  * @{\r\n  */\r\n#define DFSDM_CHANNEL_SPI_RISING         ((uint32_t)0x00000000U) /*!< SPI with rising edge */\r\n#define DFSDM_CHANNEL_SPI_FALLING        DFSDM_CHCFGR1_SITP_0    /*!< SPI with falling edge */\r\n#define DFSDM_CHANNEL_MANCHESTER_RISING  DFSDM_CHCFGR1_SITP_1    /*!< Manchester with rising edge */\r\n#define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP      /*!< Manchester with falling edge */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection\r\n  * @{\r\n  */\r\n#define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL              ((uint32_t)0x00000000U)  /*!< External SPI clock */\r\n#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL              DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */\r\n#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */\r\n#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING  DFSDM_CHCFGR1_SPICKSEL   /*!< Internal SPI clock divided by 2, rising edge */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order\r\n  * @{\r\n  */\r\n#define DFSDM_CHANNEL_FASTSINC_ORDER ((uint32_t)0x00000000U) /*!< FastSinc filter type */\r\n#define DFSDM_CHANNEL_SINC1_ORDER    DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */\r\n#define DFSDM_CHANNEL_SINC2_ORDER    DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */\r\n#define DFSDM_CHANNEL_SINC3_ORDER    DFSDM_CHAWSCDR_AWFORD   /*!< Sinc 3 filter type */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger\r\n  * @{\r\n  */\r\n#define DFSDM_FILTER_SW_TRIGGER   ((uint32_t)0x00000000U) /*!< Software trigger */\r\n#define DFSDM_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001U) /*!< Synchronous with DFSDM_FLT0 */\r\n#define DFSDM_FILTER_EXT_TRIGGER  ((uint32_t)0x00000002U) /*!< External trigger (only for injected conversion) */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger\r\n  * @{\r\n  */\r\n#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO  ((uint32_t)0x00000000U)                             /*!< For DFSDM filter 0, 1, 2 and 3 */\r\n#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0                              /*!< For DFSDM filter 0, 1, 2 and 3 */ \r\n#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO  DFSDM_FLTCR1_JEXTSEL_1                              /*!< For DFSDM filter 0, 1, 2 and 3 */\r\n#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1)   /*!< For DFSDM filter 0, 1, 2 and 3 */\r\n#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO  DFSDM_FLTCR1_JEXTSEL_2                              /*!< For DFSDM filter 0, 1, 2 and 3 */\r\n#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2)   /*!< For DFSDM filter 0, 1, 2 and 3 */\r\n#define DFSDM_FILTER_EXT_TRIG_TIM10_OC1  (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2)   /*!< For DFSDM filter 0, 1, 2 and 3 */\r\n#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1 | \\\r\n                                         DFSDM_FLTCR1_JEXTSEL_2)                             /*!< For DFSDM filter 0, 1, 2 and 3 */\r\n#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO  DFSDM_FLTCR1_JEXTSEL_3                              /*!< For DFSDM filter 0, 1, 2 and 3 */\r\n#define DFSDM_FILTER_EXT_TRIG_EXTI11     (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_4)   /*!< For DFSDM filter 0, 1, 2 and 3 */\r\n#define DFSDM_FILTER_EXT_TRIG_EXTI15     (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_3 | \\\r\n                                         DFSDM_FLTCR1_JEXTSEL_4)                             /*!< For DFSDM filter 0, 1, 2 and 3 */                         \r\n#define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_3 | \\\r\n                                         DFSDM_FLTCR1_JEXTSEL_4)                             /*!< For DFSDM filter 0, 1, 2 and 3 */                          \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge\r\n  * @{\r\n  */\r\n#define DFSDM_FILTER_EXT_TRIG_RISING_EDGE  DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */\r\n#define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */\r\n#define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES   DFSDM_FLTCR1_JEXTEN   /*!< External rising and falling edges */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order\r\n  * @{\r\n  */\r\n#define DFSDM_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000U)                     /*!< FastSinc filter type */\r\n#define DFSDM_FILTER_SINC1_ORDER    DFSDM_FLTFCR_FORD_0                         /*!< Sinc 1 filter type */\r\n#define DFSDM_FILTER_SINC2_ORDER    DFSDM_FLTFCR_FORD_1                         /*!< Sinc 2 filter type */\r\n#define DFSDM_FILTER_SINC3_ORDER    (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */\r\n#define DFSDM_FILTER_SINC4_ORDER    DFSDM_FLTFCR_FORD_2                         /*!< Sinc 4 filter type */\r\n#define DFSDM_FILTER_SINC5_ORDER    (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source\r\n  * @{\r\n  */\r\n#define DFSDM_FILTER_AWD_FILTER_DATA  ((uint32_t)0x00000000U) /*!< From digital filter */\r\n#define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL     /*!< From analog watchdog channel */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code\r\n  * @{\r\n  */ \r\n#define DFSDM_FILTER_ERROR_NONE             ((uint32_t)0x00000000U) /*!< No error */\r\n#define DFSDM_FILTER_ERROR_REGULAR_OVERRUN  ((uint32_t)0x00000001U) /*!< Overrun occurs during regular conversion */\r\n#define DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002U) /*!< Overrun occurs during injected conversion */\r\n#define DFSDM_FILTER_ERROR_DMA              ((uint32_t)0x00000003U) /*!< DMA error occurs */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DFSDM_BreakSignals DFSDM break signals\r\n  * @{\r\n  */\r\n#define DFSDM_NO_BREAK_SIGNAL ((uint32_t)0x00000000U) /*!< No break signal */\r\n#define DFSDM_BREAK_SIGNAL_0  ((uint32_t)0x00000001U) /*!< Break signal 0 */\r\n#define DFSDM_BREAK_SIGNAL_1  ((uint32_t)0x00000002U) /*!< Break signal 1 */\r\n#define DFSDM_BREAK_SIGNAL_2  ((uint32_t)0x00000004U) /*!< Break signal 2 */\r\n#define DFSDM_BREAK_SIGNAL_3  ((uint32_t)0x00000008U) /*!< Break signal 3 */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection\r\n  * @{\r\n  */\r\n/* DFSDM Channels ------------------------------------------------------------*/\r\n/* The DFSDM channels are defined as follows:\r\n   - in 16-bit LSB the channel mask is set\r\n   - in 16-bit MSB the channel number is set\r\n   e.g. for channel 5 definition:\r\n        - the channel mask is 0x00000020 (bit 5 is set)\r\n        - the channel number 5 is 0x00050000 \r\n        --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */\r\n#define DFSDM_CHANNEL_0                              ((uint32_t)0x00000001U)\r\n#define DFSDM_CHANNEL_1                              ((uint32_t)0x00010002U)\r\n#define DFSDM_CHANNEL_2                              ((uint32_t)0x00020004U)\r\n#define DFSDM_CHANNEL_3                              ((uint32_t)0x00030008U)\r\n#define DFSDM_CHANNEL_4                              ((uint32_t)0x00040010U)\r\n#define DFSDM_CHANNEL_5                              ((uint32_t)0x00050020U)\r\n#define DFSDM_CHANNEL_6                              ((uint32_t)0x00060040U)\r\n#define DFSDM_CHANNEL_7                              ((uint32_t)0x00070080U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode\r\n  * @{\r\n  */\r\n#define DFSDM_CONTINUOUS_CONV_OFF            ((uint32_t)0x00000000U) /*!< Conversion are not continuous */\r\n#define DFSDM_CONTINUOUS_CONV_ON             ((uint32_t)0x00000001U) /*!< Conversion are continuous */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold\r\n  * @{\r\n  */\r\n#define DFSDM_AWD_HIGH_THRESHOLD            ((uint32_t)0x00000000U) /*!< Analog watchdog high threshold */\r\n#define DFSDM_AWD_LOW_THRESHOLD             ((uint32_t)0x00000001U) /*!< Analog watchdog low threshold */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n/* End of exported constants -------------------------------------------------*/\r\n\r\n/* Exported macros -----------------------------------------------------------*/  \r\n/** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros\r\n * @{\r\n */\r\n\r\n/** @brief  Reset DFSDM channel handle state.\r\n  * @param  __HANDLE__: DFSDM channel handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)\r\n\r\n/** @brief  Reset DFSDM filter handle state.\r\n  * @param  __HANDLE__: DFSDM filter handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* End of exported macros ----------------------------------------------------*/\r\n  \r\n/* Exported functions --------------------------------------------------------*/  \r\n/** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions\r\n  * @{\r\n  */\r\n/* Channel initialization and de-initialization functions *********************/\r\nHAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r\nHAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r\nvoid HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r\nvoid HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions\r\n  * @{\r\n  */\r\n/* Channel operation functions ************************************************/\r\nHAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r\nHAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r\nHAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r\nHAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r\n\r\nHAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);\r\nHAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);\r\nHAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r\nHAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r\n\r\nint16_t           HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r\nHAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset);\r\n\r\nHAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);\r\n\r\nvoid HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r\nvoid HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function\r\n  * @{\r\n  */\r\n/* Channel state function *****************************************************/\r\nHAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions\r\n  * @{\r\n  */\r\n/* Filter initialization and de-initialization functions *********************/\r\nHAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r\nHAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r\nvoid HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r\nvoid HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions\r\n  * @{\r\n  */\r\n/* Filter control functions *********************/\r\nHAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r\n                                                   uint32_t                    Channel,\r\n                                                   uint32_t                    ContinuousMode);\r\nHAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r\n                                                   uint32_t                    Channel);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions\r\n  * @{\r\n  */\r\n/* Filter operation functions *********************/\r\nHAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r\nHAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r\nHAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);\r\nHAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);\r\nHAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r\nHAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r\nHAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r\nHAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r\nHAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r\nHAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);\r\nHAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);\r\nHAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r\nHAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r\nHAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r\nHAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r\n                                              DFSDM_Filter_AwdParamTypeDef* awdParam);\r\nHAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r\nHAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r\n\r\nint32_t  HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);\r\nint32_t  HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);\r\nint32_t  HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);\r\nint32_t  HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);\r\nuint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r\n\r\nvoid HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r\n\r\nHAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);\r\n\r\nvoid HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r\nvoid HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r\nvoid HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r\nvoid HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r\nvoid HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);\r\nvoid HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions\r\n  * @{\r\n  */\r\n/* Filter state functions *****************************************************/\r\nHAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r\nuint32_t                      HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* End of exported functions -------------------------------------------------*/\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup DFSDM_Private_Macros DFSDM Private Macros\r\n* @{\r\n*/\r\n#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK)          (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \\\r\n                                                       ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))\r\n#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256))\r\n#define IS_DFSDM_CHANNEL_INPUT(INPUT)                 (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \\\r\n                                                       ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))\r\n#define IS_DFSDM_CHANNEL_DATA_PACKING(MODE)           (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \\\r\n                                                       ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \\\r\n                                                       ((MODE) == DFSDM_CHANNEL_DUAL_MODE))\r\n#define IS_DFSDM_CHANNEL_INPUT_PINS(PINS)             (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \\\r\n                                                       ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))\r\n#define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE)  (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \\\r\n                                                       ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \\\r\n                                                       ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \\\r\n                                                       ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))\r\n#define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE)              (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \\\r\n                                                       ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \\\r\n                                                       ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \\\r\n                                                       ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))\r\n#define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER)          (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \\\r\n                                                       ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \\\r\n                                                       ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \\\r\n                                                       ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))\r\n#define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO)       ((1 <= (RATIO)) && ((RATIO) <= 32))\r\n#define IS_DFSDM_CHANNEL_OFFSET(VALUE)                 ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))\r\n#define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE)        ((VALUE) <= 0x1F)\r\n#define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE)          ((VALUE) <= 0xFF)\r\n#define IS_DFSDM_FILTER_REG_TRIGGER(TRIG)             (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \\\r\n                                                       ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))\r\n#define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG)             (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \\\r\n                                                       ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \\\r\n                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIGGER))\r\n#define IS_DFSDM_FILTER_EXT_TRIG(TRIG)                (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \\\r\n                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2)|| \\\r\n                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \\\r\n                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2)|| \\\r\n                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \\\r\n                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \\\r\n                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) || \\\r\n                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \\\r\n                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \\\r\n                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11)    || \\\r\n                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15)    ||\\\r\n                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT))\r\n#define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE)           (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE)  || \\\r\n                                                       ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE)  || \\\r\n                                                       ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))\r\n#define IS_DFSDM_FILTER_SINC_ORDER(ORDER)             (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \\\r\n                                                       ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \\\r\n                                                       ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \\\r\n                                                       ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \\\r\n                                                       ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \\\r\n                                                       ((ORDER) == DFSDM_FILTER_SINC5_ORDER))\r\n#define IS_DFSDM_FILTER_OVS_RATIO(RATIO)               ((1 <= (RATIO)) && ((RATIO) <= 1024))\r\n#define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO)    ((1 <= (RATIO)) && ((RATIO) <= 256))\r\n#define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA)         (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA)  || \\\r\n                                                       ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))\r\n#define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE)           ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))\r\n#define IS_DFSDM_BREAK_SIGNALS(VALUE)                  ((VALUE) <= 0xFU)\r\n#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL)             (((CHANNEL) == DFSDM_CHANNEL_0)  || \\\r\n                                                       ((CHANNEL) == DFSDM_CHANNEL_1)  || \\\r\n                                                       ((CHANNEL) == DFSDM_CHANNEL_2)  || \\\r\n                                                       ((CHANNEL) == DFSDM_CHANNEL_3)  || \\\r\n                                                       ((CHANNEL) == DFSDM_CHANNEL_4)  || \\\r\n                                                       ((CHANNEL) == DFSDM_CHANNEL_5)  || \\\r\n                                                       ((CHANNEL) == DFSDM_CHANNEL_6)  || \\\r\n                                                       ((CHANNEL) == DFSDM_CHANNEL_7))\r\n#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL)            (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F00FFU))\r\n#define IS_DFSDM_CONTINUOUS_MODE(MODE)                (((MODE) == DFSDM_CONTINUOUS_CONV_OFF)  || \\\r\n                                                       ((MODE) == DFSDM_CONTINUOUS_CONV_ON))\r\n/**\r\n  * @}\r\n  */ \r\n/* End of private macros -----------------------------------------------------*/\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_DFSDM_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_dma.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of DMA HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_DMA_H\r\n#define __STM32F7xx_HAL_DMA_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup DMA\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n\r\n/** @defgroup DMA_Exported_Types DMA Exported Types\r\n  * @brief    DMA Exported Types \r\n  * @{\r\n  */\r\n   \r\n/** \r\n  * @brief  DMA Configuration Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t Channel;              /*!< Specifies the channel used for the specified stream. \r\n                                      This parameter can be a value of @ref DMAEx_Channel_selection                  */\r\n\r\n  uint32_t Direction;            /*!< Specifies if the data will be transferred from memory to peripheral, \r\n                                      from memory to memory or from peripheral to memory.\r\n                                      This parameter can be a value of @ref DMA_Data_transfer_direction              */\r\n\r\n  uint32_t PeriphInc;            /*!< Specifies whether the Peripheral address register should be incremented or not.\r\n                                      This parameter can be a value of @ref DMA_Peripheral_incremented_mode          */\r\n\r\n  uint32_t MemInc;               /*!< Specifies whether the memory address register should be incremented or not.\r\n                                      This parameter can be a value of @ref DMA_Memory_incremented_mode              */\r\n\r\n  uint32_t PeriphDataAlignment;  /*!< Specifies the Peripheral data width.\r\n                                      This parameter can be a value of @ref DMA_Peripheral_data_size                 */\r\n\r\n  uint32_t MemDataAlignment;     /*!< Specifies the Memory data width.\r\n                                      This parameter can be a value of @ref DMA_Memory_data_size                     */\r\n\r\n  uint32_t Mode;                 /*!< Specifies the operation mode of the DMAy Streamx.\r\n                                      This parameter can be a value of @ref DMA_mode\r\n                                      @note The circular buffer mode cannot be used if the memory-to-memory\r\n                                            data transfer is configured on the selected Stream                        */\r\n\r\n  uint32_t Priority;             /*!< Specifies the software priority for the DMAy Streamx.\r\n                                      This parameter can be a value of @ref DMA_Priority_level                       */\r\n\r\n  uint32_t FIFOMode;             /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.\r\n                                      This parameter can be a value of @ref DMA_FIFO_direct_mode\r\n                                      @note The Direct mode (FIFO mode disabled) cannot be used if the \r\n                                            memory-to-memory data transfer is configured on the selected stream       */\r\n\r\n  uint32_t FIFOThreshold;        /*!< Specifies the FIFO threshold level.\r\n                                      This parameter can be a value of @ref DMA_FIFO_threshold_level                  */\r\n\r\n  uint32_t MemBurst;             /*!< Specifies the Burst transfer configuration for the memory transfers. \r\n                                      It specifies the amount of data to be transferred in a single non interruptible \r\n                                      transaction.\r\n                                      This parameter can be a value of @ref DMA_Memory_burst \r\n                                      @note The burst mode is possible only if the address Increment mode is enabled. */\r\n\r\n  uint32_t PeriphBurst;          /*!< Specifies the Burst transfer configuration for the peripheral transfers. \r\n                                      It specifies the amount of data to be transferred in a single non interruptible \r\n                                      transaction. \r\n                                      This parameter can be a value of @ref DMA_Peripheral_burst\r\n                                      @note The burst mode is possible only if the address Increment mode is enabled. */\r\n}DMA_InitTypeDef;\r\n\r\n/** \r\n  * @brief  HAL DMA State structures definition\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled */\r\n  HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use   */\r\n  HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing              */\r\n  HAL_DMA_STATE_TIMEOUT           = 0x03U,  /*!< DMA timeout state                   */\r\n  HAL_DMA_STATE_ERROR             = 0x04U,  /*!< DMA error state                     */\r\n  HAL_DMA_STATE_ABORT             = 0x05U,  /*!< DMA Abort state                     */\r\n}HAL_DMA_StateTypeDef;\r\n\r\n/** \r\n  * @brief  HAL DMA Error Code structure definition\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_DMA_FULL_TRANSFER      = 0x00U,    /*!< Full transfer     */\r\n  HAL_DMA_HALF_TRANSFER      = 0x01U,    /*!< Half Transfer     */\r\n}HAL_DMA_LevelCompleteTypeDef;\r\n\r\n/** \r\n  * @brief  HAL DMA Error Code structure definition\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer     */\r\n  HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,    /*!< Half Transfer     */\r\n  HAL_DMA_XFER_M1CPLT_CB_ID        = 0x02U,    /*!< M1 Full Transfer  */\r\n  HAL_DMA_XFER_M1HALFCPLT_CB_ID    = 0x03U,    /*!< M1 Half Transfer  */\r\n  HAL_DMA_XFER_ERROR_CB_ID         = 0x04U,    /*!< Error             */\r\n  HAL_DMA_XFER_ABORT_CB_ID         = 0x05U,    /*!< Abort             */\r\n  HAL_DMA_XFER_ALL_CB_ID           = 0x06U     /*!< All               */\r\n}HAL_DMA_CallbackIDTypeDef;\r\n\r\n/** \r\n  * @brief  DMA handle Structure definition\r\n  */\r\ntypedef struct __DMA_HandleTypeDef\r\n{\r\n  DMA_Stream_TypeDef         *Instance;                                                    /*!< Register base address                  */\r\n\r\n  DMA_InitTypeDef            Init;                                                         /*!< DMA communication parameters           */ \r\n\r\n  HAL_LockTypeDef            Lock;                                                         /*!< DMA locking object                     */  \r\n\r\n  __IO HAL_DMA_StateTypeDef  State;                                                        /*!< DMA transfer state                     */\r\n\r\n  void                       *Parent;                                                      /*!< Parent object state                    */ \r\n\r\n  void                       (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback         */\r\n\r\n  void                       (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback    */\r\n\r\n  void                       (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer complete Memory1 callback */\r\n  \r\n  void                       (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer Half complete Memory1 callback */\r\n  \r\n  void                       (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback            */\r\n  \r\n  void                       (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer Abort callback            */  \r\n\r\n __IO uint32_t               ErrorCode;                                                    /*!< DMA Error code                          */\r\n  \r\n uint32_t                    StreamBaseAddress;                                            /*!< DMA Stream Base Address                */\r\n\r\n uint32_t                    StreamIndex;                                                  /*!< DMA Stream Index                       */\r\n \r\n}DMA_HandleTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup DMA_Exported_Constants DMA Exported Constants\r\n  * @brief    DMA Exported constants \r\n  * @{\r\n  */\r\n\r\n/** @defgroup DMA_Error_Code DMA Error Code\r\n  * @brief    DMA Error Code \r\n  * @{\r\n  */ \r\n#define HAL_DMA_ERROR_NONE            ((uint32_t)0x00000000U)    /*!< No error                               */\r\n#define HAL_DMA_ERROR_TE              ((uint32_t)0x00000001U)    /*!< Transfer error                         */\r\n#define HAL_DMA_ERROR_FE              ((uint32_t)0x00000002U)    /*!< FIFO error                             */\r\n#define HAL_DMA_ERROR_DME             ((uint32_t)0x00000004U)    /*!< Direct Mode error                      */\r\n#define HAL_DMA_ERROR_TIMEOUT         ((uint32_t)0x00000020U)    /*!< Timeout error                          */\r\n#define HAL_DMA_ERROR_PARAM           ((uint32_t)0x00000040U)    /*!< Parameter error                        */\r\n#define HAL_DMA_ERROR_NO_XFER         ((uint32_t)0x00000080U)    /*!< Abort requested with no Xfer ongoing   */ \r\n#define HAL_DMA_ERROR_NOT_SUPPORTED   ((uint32_t)0x00000100U)    /*!< Not supported mode                     */     \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction\r\n  * @brief    DMA data transfer direction \r\n  * @{\r\n  */ \r\n#define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000U)      /*!< Peripheral to memory direction */\r\n#define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_SxCR_DIR_0)  /*!< Memory to peripheral direction */\r\n#define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_SxCR_DIR_1)  /*!< Memory to memory direction     */\r\n/**\r\n  * @}\r\n  */\r\n        \r\n/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode\r\n  * @brief    DMA peripheral incremented mode \r\n  * @{\r\n  */ \r\n#define DMA_PINC_ENABLE        ((uint32_t)DMA_SxCR_PINC)  /*!< Peripheral increment mode enable  */\r\n#define DMA_PINC_DISABLE       ((uint32_t)0x00000000U)     /*!< Peripheral increment mode disable */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode\r\n  * @brief    DMA memory incremented mode \r\n  * @{\r\n  */ \r\n#define DMA_MINC_ENABLE         ((uint32_t)DMA_SxCR_MINC)  /*!< Memory increment mode enable  */\r\n#define DMA_MINC_DISABLE        ((uint32_t)0x00000000U)     /*!< Memory increment mode disable */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size\r\n  * @brief    DMA peripheral data size \r\n  * @{\r\n  */ \r\n#define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000U)        /*!< Peripheral data alignment: Byte     */\r\n#define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_PSIZE_0)  /*!< Peripheral data alignment: HalfWord */\r\n#define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_SxCR_PSIZE_1)  /*!< Peripheral data alignment: Word     */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup DMA_Memory_data_size DMA Memory data size\r\n  * @brief    DMA memory data size \r\n  * @{ \r\n  */\r\n#define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000U)        /*!< Memory data alignment: Byte     */\r\n#define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_MSIZE_0)  /*!< Memory data alignment: HalfWord */\r\n#define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_SxCR_MSIZE_1)  /*!< Memory data alignment: Word     */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DMA_mode DMA mode\r\n  * @brief    DMA mode \r\n  * @{\r\n  */ \r\n#define DMA_NORMAL         ((uint32_t)0x00000000U)       /*!< Normal mode                  */\r\n#define DMA_CIRCULAR       ((uint32_t)DMA_SxCR_CIRC)    /*!< Circular mode                */\r\n#define DMA_PFCTRL         ((uint32_t)DMA_SxCR_PFCTRL)  /*!< Peripheral flow control mode */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DMA_Priority_level DMA Priority level\r\n  * @brief    DMA priority levels \r\n  * @{\r\n  */\r\n#define DMA_PRIORITY_LOW             ((uint32_t)0x00000000U)     /*!< Priority level: Low       */\r\n#define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_SxCR_PL_0)  /*!< Priority level: Medium    */\r\n#define DMA_PRIORITY_HIGH            ((uint32_t)DMA_SxCR_PL_1)  /*!< Priority level: High      */\r\n#define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_SxCR_PL)    /*!< Priority level: Very High */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode\r\n  * @brief    DMA FIFO direct mode\r\n  * @{\r\n  */\r\n#define DMA_FIFOMODE_DISABLE        ((uint32_t)0x00000000U)       /*!< FIFO mode disable */\r\n#define DMA_FIFOMODE_ENABLE         ((uint32_t)DMA_SxFCR_DMDIS)  /*!< FIFO mode enable  */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level\r\n  * @brief    DMA FIFO level \r\n  * @{\r\n  */\r\n#define DMA_FIFO_THRESHOLD_1QUARTERFULL       ((uint32_t)0x00000000U)       /*!< FIFO threshold 1 quart full configuration  */\r\n#define DMA_FIFO_THRESHOLD_HALFFULL           ((uint32_t)DMA_SxFCR_FTH_0)  /*!< FIFO threshold half full configuration     */\r\n#define DMA_FIFO_THRESHOLD_3QUARTERSFULL      ((uint32_t)DMA_SxFCR_FTH_1)  /*!< FIFO threshold 3 quarts full configuration */\r\n#define DMA_FIFO_THRESHOLD_FULL               ((uint32_t)DMA_SxFCR_FTH)    /*!< FIFO threshold full configuration          */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup DMA_Memory_burst DMA Memory burst\r\n  * @brief    DMA memory burst \r\n  * @{\r\n  */ \r\n#define DMA_MBURST_SINGLE       ((uint32_t)0x00000000U)  \r\n#define DMA_MBURST_INC4         ((uint32_t)DMA_SxCR_MBURST_0)  \r\n#define DMA_MBURST_INC8         ((uint32_t)DMA_SxCR_MBURST_1)  \r\n#define DMA_MBURST_INC16        ((uint32_t)DMA_SxCR_MBURST)  \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup DMA_Peripheral_burst DMA Peripheral burst\r\n  * @brief    DMA peripheral burst \r\n  * @{\r\n  */ \r\n#define DMA_PBURST_SINGLE       ((uint32_t)0x00000000U)\r\n#define DMA_PBURST_INC4         ((uint32_t)DMA_SxCR_PBURST_0)\r\n#define DMA_PBURST_INC8         ((uint32_t)DMA_SxCR_PBURST_1)\r\n#define DMA_PBURST_INC16        ((uint32_t)DMA_SxCR_PBURST)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions\r\n  * @brief    DMA interrupts definition \r\n  * @{\r\n  */\r\n#define DMA_IT_TC                         ((uint32_t)DMA_SxCR_TCIE)\r\n#define DMA_IT_HT                         ((uint32_t)DMA_SxCR_HTIE)\r\n#define DMA_IT_TE                         ((uint32_t)DMA_SxCR_TEIE)\r\n#define DMA_IT_DME                        ((uint32_t)DMA_SxCR_DMEIE)\r\n#define DMA_IT_FE                         ((uint32_t)0x00000080U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DMA_flag_definitions DMA flag definitions\r\n  * @brief    DMA flag definitions \r\n  * @{\r\n  */ \r\n#define DMA_FLAG_FEIF0_4                    ((uint32_t)0x00800001U)\r\n#define DMA_FLAG_DMEIF0_4                   ((uint32_t)0x00800004U)\r\n#define DMA_FLAG_TEIF0_4                    ((uint32_t)0x00000008U)\r\n#define DMA_FLAG_HTIF0_4                    ((uint32_t)0x00000010U)\r\n#define DMA_FLAG_TCIF0_4                    ((uint32_t)0x00000020U)\r\n#define DMA_FLAG_FEIF1_5                    ((uint32_t)0x00000040U)\r\n#define DMA_FLAG_DMEIF1_5                   ((uint32_t)0x00000100U)\r\n#define DMA_FLAG_TEIF1_5                    ((uint32_t)0x00000200U)\r\n#define DMA_FLAG_HTIF1_5                    ((uint32_t)0x00000400U)\r\n#define DMA_FLAG_TCIF1_5                    ((uint32_t)0x00000800U)\r\n#define DMA_FLAG_FEIF2_6                    ((uint32_t)0x00010000U)\r\n#define DMA_FLAG_DMEIF2_6                   ((uint32_t)0x00040000U)\r\n#define DMA_FLAG_TEIF2_6                    ((uint32_t)0x00080000U)\r\n#define DMA_FLAG_HTIF2_6                    ((uint32_t)0x00100000U)\r\n#define DMA_FLAG_TCIF2_6                    ((uint32_t)0x00200000U)\r\n#define DMA_FLAG_FEIF3_7                    ((uint32_t)0x00400000U)\r\n#define DMA_FLAG_DMEIF3_7                   ((uint32_t)0x01000000U)\r\n#define DMA_FLAG_TEIF3_7                    ((uint32_t)0x02000000U)\r\n#define DMA_FLAG_HTIF3_7                    ((uint32_t)0x04000000U)\r\n#define DMA_FLAG_TCIF3_7                    ((uint32_t)0x08000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n \r\n/* Exported macro ------------------------------------------------------------*/\r\n\r\n/** @brief Reset DMA handle state\r\n  * @param  __HANDLE__: specifies the DMA handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)\r\n\r\n/**\r\n  * @brief  Return the current DMA Stream FIFO filled level.\r\n  * @param  __HANDLE__: DMA handle\r\n  * @retval The FIFO filling state.\r\n  *           - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full \r\n  *                                              and not empty.\r\n  *           - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.\r\n  *           - DMA_FIFOStatus_HalfFull: if more than 1 half-full.\r\n  *           - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.\r\n  *           - DMA_FIFOStatus_Empty: when FIFO is empty\r\n  *           - DMA_FIFOStatus_Full: when FIFO is full\r\n  */\r\n#define __HAL_DMA_GET_FS(__HANDLE__)      (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))\r\n\r\n/**\r\n  * @brief  Enable the specified DMA Stream.\r\n  * @param  __HANDLE__: DMA handle\r\n  * @retval None\r\n  */\r\n#define __HAL_DMA_ENABLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  DMA_SxCR_EN)\r\n\r\n/**\r\n  * @brief  Disable the specified DMA Stream.\r\n  * @param  __HANDLE__: DMA handle\r\n  * @retval None\r\n  */\r\n#define __HAL_DMA_DISABLE(__HANDLE__)     ((__HANDLE__)->Instance->CR &=  ~DMA_SxCR_EN)\r\n\r\n/* Interrupt & Flag management */\r\n\r\n/**\r\n  * @brief  Return the current DMA Stream transfer complete flag.\r\n  * @param  __HANDLE__: DMA handle\r\n  * @retval The specified transfer complete flag index.\r\n  */\r\n#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \\\r\n(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\\\r\n   DMA_FLAG_TCIF3_7)\r\n\r\n/**\r\n  * @brief  Return the current DMA Stream half transfer complete flag.\r\n  * @param  __HANDLE__: DMA handle\r\n  * @retval The specified half transfer complete flag index.\r\n  */      \r\n#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\\\r\n(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\\\r\n   DMA_FLAG_HTIF3_7)\r\n\r\n/**\r\n  * @brief  Return the current DMA Stream transfer error flag.\r\n  * @param  __HANDLE__: DMA handle\r\n  * @retval The specified transfer error flag index.\r\n  */\r\n#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\\\r\n(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\\\r\n   DMA_FLAG_TEIF3_7)\r\n\r\n/**\r\n  * @brief  Return the current DMA Stream FIFO error flag.\r\n  * @param  __HANDLE__: DMA handle\r\n  * @retval The specified FIFO error flag index.\r\n  */\r\n#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\\\r\n(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\\\r\n   DMA_FLAG_FEIF3_7)\r\n\r\n/**\r\n  * @brief  Return the current DMA Stream direct mode error flag.\r\n  * @param  __HANDLE__: DMA handle\r\n  * @retval The specified direct mode error flag index.\r\n  */\r\n#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\\\r\n(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\\\r\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\\\r\n   DMA_FLAG_DMEIF3_7)\r\n\r\n/**\r\n  * @brief  Get the DMA Stream pending flags.\r\n  * @param  __HANDLE__: DMA handle\r\n  * @param  __FLAG__: Get the specified flag.\r\n  *          This parameter can be any combination of the following values:\r\n  *            @arg DMA_FLAG_TCIFx: Transfer complete flag.\r\n  *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.\r\n  *            @arg DMA_FLAG_TEIFx: Transfer error flag.\r\n  *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.\r\n  *            @arg DMA_FLAG_FEIFx: FIFO error flag.\r\n  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.   \r\n  * @retval The state of FLAG (SET or RESET).\r\n  */\r\n#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\\\r\n(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\\\r\n ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\\\r\n ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))\r\n\r\n/**\r\n  * @brief  Clear the DMA Stream pending flags.\r\n  * @param  __HANDLE__: DMA handle\r\n  * @param  __FLAG__: specifies the flag to clear.\r\n  *          This parameter can be any combination of the following values:\r\n  *            @arg DMA_FLAG_TCIFx: Transfer complete flag.\r\n  *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.\r\n  *            @arg DMA_FLAG_TEIFx: Transfer error flag.\r\n  *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.\r\n  *            @arg DMA_FLAG_FEIFx: FIFO error flag.\r\n  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.   \r\n  * @retval None\r\n  */\r\n#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \\\r\n(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\\\r\n ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\\\r\n ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))\r\n\r\n/**\r\n  * @brief  Enable the specified DMA Stream interrupts.\r\n  * @param  __HANDLE__: DMA handle\r\n  * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. \r\n  *        This parameter can be one of the following values:\r\n  *           @arg DMA_IT_TC: Transfer complete interrupt mask.\r\n  *           @arg DMA_IT_HT: Half transfer complete interrupt mask.\r\n  *           @arg DMA_IT_TE: Transfer error interrupt mask.\r\n  *           @arg DMA_IT_FE: FIFO error interrupt mask.\r\n  *           @arg DMA_IT_DME: Direct mode error interrupt.\r\n  * @retval None\r\n  */\r\n#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((__INTERRUPT__) != DMA_IT_FE)? \\\r\n((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))\r\n\r\n/**\r\n  * @brief  Disable the specified DMA Stream interrupts.\r\n  * @param  __HANDLE__: DMA handle\r\n  * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. \r\n  *         This parameter can be one of the following values:\r\n  *            @arg DMA_IT_TC: Transfer complete interrupt mask.\r\n  *            @arg DMA_IT_HT: Half transfer complete interrupt mask.\r\n  *            @arg DMA_IT_TE: Transfer error interrupt mask.\r\n  *            @arg DMA_IT_FE: FIFO error interrupt mask.\r\n  *            @arg DMA_IT_DME: Direct mode error interrupt.\r\n  * @retval None\r\n  */\r\n#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \\\r\n((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))\r\n\r\n/**\r\n  * @brief  Check whether the specified DMA Stream interrupt is enabled or not.\r\n  * @param  __HANDLE__: DMA handle\r\n  * @param  __INTERRUPT__: specifies the DMA interrupt source to check.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg DMA_IT_TC: Transfer complete interrupt mask.\r\n  *            @arg DMA_IT_HT: Half transfer complete interrupt mask.\r\n  *            @arg DMA_IT_TE: Transfer error interrupt mask.\r\n  *            @arg DMA_IT_FE: FIFO error interrupt mask.\r\n  *            @arg DMA_IT_DME: Direct mode error interrupt.\r\n  * @retval The state of DMA_IT.\r\n  */\r\n#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \\\r\n                                                        ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \\\r\n                                                        ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))\r\n\r\n/**\r\n  * @brief  Writes the number of data units to be transferred on the DMA Stream.\r\n  * @param  __HANDLE__: DMA handle\r\n  * @param  __COUNTER__: Number of data units to be transferred (from 0 to 65535) \r\n  *          Number of data items depends only on the Peripheral data format.\r\n  *            \r\n  * @note   If Peripheral data format is Bytes: number of data units is equal \r\n  *         to total number of bytes to be transferred.\r\n  *           \r\n  * @note   If Peripheral data format is Half-Word: number of data units is  \r\n  *         equal to total number of bytes to be transferred / 2.\r\n  *           \r\n  * @note   If Peripheral data format is Word: number of data units is equal \r\n  *         to total  number of bytes to be transferred / 4.\r\n  *      \r\n  * @retval The number of remaining data units in the current DMAy Streamx transfer.\r\n  */\r\n#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))\r\n\r\n/**\r\n  * @brief  Returns the number of remaining data units in the current DMAy Streamx transfer.\r\n  * @param  __HANDLE__: DMA handle\r\n  *   \r\n  * @retval The number of remaining data units in the current DMA Stream transfer.\r\n  */\r\n#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)\r\n\r\n\r\n/* Include DMA HAL Extension module */\r\n#include \"stm32f7xx_hal_dma_ex.h\"   \r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @defgroup DMA_Exported_Functions DMA Exported Functions\r\n  * @brief    DMA Exported functions \r\n  * @{\r\n  */\r\n\r\n/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions\r\n  * @brief   Initialization and de-initialization functions \r\n  * @{\r\n  */\r\nHAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); \r\nHAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions\r\n  * @brief   I/O operation functions  \r\n  * @{\r\n  */\r\nHAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r\nHAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r\nHAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);\r\nHAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);\r\nHAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);\r\nvoid              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);\r\nHAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);\r\nHAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));\r\nHAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions\r\n  * @brief    Peripheral State functions \r\n  * @{\r\n  */\r\nHAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);\r\nuint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);\r\n/**\r\n  * @}\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n/* Private Constants -------------------------------------------------------------*/\r\n/** @defgroup DMA_Private_Constants DMA Private Constants\r\n  * @brief    DMA private defines and constants \r\n  * @{\r\n  */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup DMA_Private_Macros DMA Private Macros\r\n  * @brief    DMA private macros \r\n  * @{\r\n  */\r\n#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \\\r\n                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \\\r\n                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) \r\n\r\n#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))\r\n\r\n#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \\\r\n                                            ((STATE) == DMA_PINC_DISABLE))\r\n\r\n#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \\\r\n                                        ((STATE) == DMA_MINC_DISABLE))\r\n\r\n#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \\\r\n                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \\\r\n                                           ((SIZE) == DMA_PDATAALIGN_WORD))\r\n\r\n#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \\\r\n                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \\\r\n                                       ((SIZE) == DMA_MDATAALIGN_WORD ))\r\n\r\n#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \\\r\n                           ((MODE) == DMA_CIRCULAR) || \\\r\n                           ((MODE) == DMA_PFCTRL)) \r\n\r\n#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \\\r\n                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \\\r\n                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \\\r\n                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) \r\n\r\n#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \\\r\n                                       ((STATE) == DMA_FIFOMODE_ENABLE))\r\n\r\n#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \\\r\n                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL)      || \\\r\n                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \\\r\n                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))\r\n\r\n#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \\\r\n                                    ((BURST) == DMA_MBURST_INC4)   || \\\r\n                                    ((BURST) == DMA_MBURST_INC8)   || \\\r\n                                    ((BURST) == DMA_MBURST_INC16))\r\n\r\n#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \\\r\n                                        ((BURST) == DMA_PBURST_INC4)   || \\\r\n                                        ((BURST) == DMA_PBURST_INC8)   || \\\r\n                                        ((BURST) == DMA_PBURST_INC16))\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup DMA_Private_Functions DMA Private Functions\r\n  * @brief    DMA private  functions \r\n  * @{\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_DMA_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_dma2d.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of DMA2D HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_DMA2D_H\r\n#define __STM32F7xx_HAL_DMA2D_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup DMA2D DMA2D\r\n  * @brief DMA2D HAL module driver\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup DMA2D_Exported_Types DMA2D Exported Types\r\n  * @{\r\n  */\r\n#define MAX_DMA2D_LAYER  2\r\n\r\n/** \r\n  * @brief DMA2D color Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t Blue;               /*!< Configures the blue value.\r\n                                    This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */\r\n\r\n  uint32_t Green;              /*!< Configures the green value.\r\n                                    This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */\r\n\r\n  uint32_t Red;                /*!< Configures the red value.\r\n                                    This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */\r\n} DMA2D_ColorTypeDef;\r\n\r\n/** \r\n  * @brief DMA2D CLUT Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t *pCLUT;                  /*!< Configures the DMA2D CLUT memory address.*/\r\n\r\n  uint32_t CLUTColorMode;           /*!< Configures the DMA2D CLUT color mode.\r\n                                         This parameter can be one value of @ref DMA2D_CLUT_CM. */\r\n\r\n  uint32_t Size;                    /*!< Configures the DMA2D CLUT size. \r\n                                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/\r\n} DMA2D_CLUTCfgTypeDef;\r\n\r\n/** \r\n  * @brief DMA2D Init structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t             Mode;               /*!< Configures the DMA2D transfer mode.\r\n                                                This parameter can be one value of @ref DMA2D_Mode. */\r\n\r\n  uint32_t             ColorMode;          /*!< Configures the color format of the output image.\r\n                                                This parameter can be one value of @ref DMA2D_Output_Color_Mode. */\r\n\r\n  uint32_t             OutputOffset;       /*!< Specifies the Offset value. \r\n                                                This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */\r\n#if defined (DMA2D_OPFCCR_AI)\r\n  uint32_t             AlphaInverted;     /*!< Select regular or inverted alpha value for the output pixel format converter.\r\n                                               This parameter can be one value of @ref DMA2D_Alpha_Inverted. */\r\n#endif /* DMA2D_OPFCCR_AI */  \r\n\r\n#if defined (DMA2D_OPFCCR_RBS) \r\n  uint32_t             RedBlueSwap;       /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR)\r\n                                               for the output pixel format converter.\r\n                                               This parameter can be one value of @ref DMA2D_RB_Swap. */ \r\n#endif /* DMA2D_OPFCCR_RBS */\r\n  \r\n} DMA2D_InitTypeDef;\r\n\r\n\r\n/** \r\n  * @brief DMA2D Layer structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t             InputOffset;       /*!< Configures the DMA2D foreground or background offset.\r\n                                               This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */\r\n\r\n  uint32_t             InputColorMode;    /*!< Configures the DMA2D foreground or background color mode. \r\n                                               This parameter can be one value of @ref DMA2D_Input_Color_Mode. */\r\n\r\n  uint32_t             AlphaMode;         /*!< Configures the DMA2D foreground or background alpha mode. \r\n                                               This parameter can be one value of @ref DMA2D_Alpha_Mode. */\r\n\r\n  uint32_t             InputAlpha;        /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode. \r\n                                               This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below.\r\n                                               @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between \r\n                                               Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where \r\n                                               - InputAlpha[24:31] is the alpha value ALPHA[0:7]\r\n                                               - InputAlpha[16:23] is the red value RED[0:7]\r\n                                               - InputAlpha[8:15] is the green value GREEN[0:7]\r\n                                               - InputAlpha[0:7] is the blue value BLUE[0:7]. */\r\n\r\n#if defined (DMA2D_FGPFCCR_AI) && defined (DMA2D_BGPFCCR_AI) \r\n  uint32_t             AlphaInverted;     /*!< Select regular or inverted alpha value.\r\n                                               This parameter can be one value of @ref DMA2D_Alpha_Inverted. \r\n                                               This feature is only available on devices :\r\n                                               STM32F756xx, STM32F767xx, STM32F769xx, STM32F777xx and STM32F779xx.*/\r\n  \r\n#endif /* (DMA2D_FGPFCCR_AI) && (DMA2D_BGPFCCR_AI)  */   \r\n\r\n#if defined (DMA2D_FGPFCCR_RBS) && defined (DMA2D_BGPFCCR_RBS)   \r\n  uint32_t             RedBlueSwap;       /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR).\r\n                                               This parameter can be one value of @ref DMA2D_RB_Swap\r\n                                               This feature is only available on devices :\r\n                                               STM32F756xx, STM32F767xx, STM32F769xx, STM32F777xx and STM32F779xx.*/  \r\n\r\n#endif /* (DMA2D_FGPFCCR_RBS) && (DMA2D_BGPFCCR_RBS)  */\r\n  \r\n} DMA2D_LayerCfgTypeDef;\r\n\r\n/** \r\n  * @brief  HAL DMA2D State structures definition\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_DMA2D_STATE_RESET             = 0x00U,    /*!< DMA2D not yet initialized or disabled       */\r\n  HAL_DMA2D_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */\r\n  HAL_DMA2D_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */\r\n  HAL_DMA2D_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */\r\n  HAL_DMA2D_STATE_ERROR             = 0x04U,    /*!< DMA2D state error                           */\r\n  HAL_DMA2D_STATE_SUSPEND           = 0x05U     /*!< DMA2D process is suspended                  */\r\n}HAL_DMA2D_StateTypeDef;\r\n\r\n/** \r\n  * @brief  DMA2D handle Structure definition\r\n  */\r\ntypedef struct __DMA2D_HandleTypeDef\r\n{\r\n  DMA2D_TypeDef               *Instance;                                                    /*!< DMA2D register base address.               */\r\n                                                                                                                                          \r\n  DMA2D_InitTypeDef           Init;                                                         /*!< DMA2D communication parameters.            */\r\n\r\n  void                        (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d);  /*!< DMA2D transfer complete callback.          */\r\n                                                                                                                                           \r\n  void                        (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback.             */                                                                                                                                             \r\n\r\n  DMA2D_LayerCfgTypeDef       LayerCfg[MAX_DMA2D_LAYER];                                    /*!< DMA2D Layers parameters           */  \r\n\r\n  HAL_LockTypeDef             Lock;                                                         /*!< DMA2D lock.                                */  \r\n                                                                                                                                           \r\n  __IO HAL_DMA2D_StateTypeDef State;                                                        /*!< DMA2D transfer state.                      */\r\n                                                                                                                                           \r\n  __IO uint32_t               ErrorCode;                                                    /*!< DMA2D error code.                          */  \r\n} DMA2D_HandleTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup DMA2D_Error_Code DMA2D Error Code\r\n  * @{\r\n  */\r\n#define HAL_DMA2D_ERROR_NONE        ((uint32_t)0x00000000U)  /*!< No error             */\r\n#define HAL_DMA2D_ERROR_TE          ((uint32_t)0x00000001U)  /*!< Transfer error       */\r\n#define HAL_DMA2D_ERROR_CE          ((uint32_t)0x00000002U)  /*!< Configuration error  */\r\n#define HAL_DMA2D_ERROR_CAE         ((uint32_t)0x00000004U)  /*!< CLUT access error    */\r\n#define HAL_DMA2D_ERROR_TIMEOUT     ((uint32_t)0x00000020U)  /*!< Timeout error        */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DMA2D_Mode DMA2D Mode \r\n  * @{\r\n  */\r\n#define DMA2D_M2M                   ((uint32_t)0x00000000U)  /*!< DMA2D memory to memory transfer mode */\r\n#define DMA2D_M2M_PFC               DMA2D_CR_MODE_0          /*!< DMA2D memory to memory with pixel format conversion transfer mode */\r\n#define DMA2D_M2M_BLEND             DMA2D_CR_MODE_1          /*!< DMA2D memory to memory with blending transfer mode */\r\n#define DMA2D_R2M                   DMA2D_CR_MODE            /*!< DMA2D register to memory transfer mode */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode \r\n  * @{\r\n  */\r\n#define DMA2D_OUTPUT_ARGB8888       ((uint32_t)0x00000000U)               /*!< ARGB8888 DMA2D color mode */\r\n#define DMA2D_OUTPUT_RGB888         DMA2D_OPFCCR_CM_0                     /*!< RGB888 DMA2D color mode   */\r\n#define DMA2D_OUTPUT_RGB565         DMA2D_OPFCCR_CM_1                     /*!< RGB565 DMA2D color mode   */\r\n#define DMA2D_OUTPUT_ARGB1555       (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */\r\n#define DMA2D_OUTPUT_ARGB4444       DMA2D_OPFCCR_CM_2                     /*!< ARGB4444 DMA2D color mode */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode\r\n  * @{\r\n  */\r\n#define DMA2D_INPUT_ARGB8888        ((uint32_t)0x00000000U)  /*!< ARGB8888 color mode */\r\n#define DMA2D_INPUT_RGB888          ((uint32_t)0x00000001U)  /*!< RGB888 color mode   */\r\n#define DMA2D_INPUT_RGB565          ((uint32_t)0x00000002U)  /*!< RGB565 color mode   */\r\n#define DMA2D_INPUT_ARGB1555        ((uint32_t)0x00000003U)  /*!< ARGB1555 color mode */\r\n#define DMA2D_INPUT_ARGB4444        ((uint32_t)0x00000004U)  /*!< ARGB4444 color mode */\r\n#define DMA2D_INPUT_L8              ((uint32_t)0x00000005U)  /*!< L8 color mode       */\r\n#define DMA2D_INPUT_AL44            ((uint32_t)0x00000006U)  /*!< AL44 color mode     */\r\n#define DMA2D_INPUT_AL88            ((uint32_t)0x00000007U)  /*!< AL88 color mode     */\r\n#define DMA2D_INPUT_L4              ((uint32_t)0x00000008U)  /*!< L4 color mode       */\r\n#define DMA2D_INPUT_A8              ((uint32_t)0x00000009U)  /*!< A8 color mode       */\r\n#define DMA2D_INPUT_A4              ((uint32_t)0x0000000AU)  /*!< A4 color mode       */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode\r\n  * @{\r\n  */\r\n#define DMA2D_NO_MODIF_ALPHA        ((uint32_t)0x00000000U)  /*!< No modification of the alpha channel value */\r\n#define DMA2D_REPLACE_ALPHA         ((uint32_t)0x00000001U)  /*!< Replace original alpha channel value by programmed alpha value */\r\n#define DMA2D_COMBINE_ALPHA         ((uint32_t)0x00000002U)  /*!< Replace original alpha channel value by programmed alpha value\r\n                                                                with original alpha channel value                              */\r\n/**\r\n  * @}\r\n  */    \r\n\r\n#if defined (DMA2D_FGPFCCR_AI) && defined (DMA2D_BGPFCCR_AI)    \r\n/** @defgroup DMA2D_Alpha_Inverted DMA2D ALPHA Inversion\r\n  * @{\r\n  */\r\n#define DMA2D_REGULAR_ALPHA         ((uint32_t)0x00000000U)  /*!< No modification of the alpha channel value */\r\n#define DMA2D_INVERTED_ALPHA        ((uint32_t)0x00000001U)  /*!< Invert the alpha channel value */                                  \r\n/**\r\n  * @}\r\n  */\r\n#endif /* (DMA2D_FGPFCCR_AI) && (DMA2D_BGPFCCR_AI)  */\r\n\r\n#if defined (DMA2D_FGPFCCR_RBS) && defined (DMA2D_BGPFCCR_RBS)  \r\n/** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap\r\n  * @{\r\n  */\r\n#define DMA2D_RB_REGULAR            ((uint32_t)0x00000000U)  /*!< Select regular mode (RGB or ARGB) */\r\n#define DMA2D_RB_SWAP               ((uint32_t)0x00000001U)  /*!< Select swap mode (BGR or ABGR) */\r\n/**\r\n  * @}\r\n  */ \r\n#endif /* (DMA2D_FGPFCCR_RBS) && (DMA2D_BGPFCCR_RBS)  */     \r\n\r\n/** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode\r\n  * @{\r\n  */\r\n#define DMA2D_CCM_ARGB8888          ((uint32_t)0x00000000U)  /*!< ARGB8888 DMA2D CLUT color mode */\r\n#define DMA2D_CCM_RGB888            ((uint32_t)0x00000001U)  /*!< RGB888 DMA2D CLUT color mode   */\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup DMA2D_Interrupts DMA2D Interrupts \r\n  * @{\r\n  */\r\n#define DMA2D_IT_CE                 DMA2D_CR_CEIE            /*!< Configuration Error Interrupt */\r\n#define DMA2D_IT_CTC                DMA2D_CR_CTCIE           /*!< CLUT Transfer Complete Interrupt */\r\n#define DMA2D_IT_CAE                DMA2D_CR_CAEIE           /*!< CLUT Access Error Interrupt */\r\n#define DMA2D_IT_TW                 DMA2D_CR_TWIE            /*!< Transfer Watermark Interrupt */\r\n#define DMA2D_IT_TC                 DMA2D_CR_TCIE            /*!< Transfer Complete Interrupt */\r\n#define DMA2D_IT_TE                 DMA2D_CR_TEIE            /*!< Transfer Error Interrupt */\r\n/**                                                         \r\n  * @}                                                      \r\n  */                                                        \r\n                                                            \r\n/** @defgroup DMA2D_Flags DMA2D Flags                       \r\n  * @{                                                      \r\n  */                                                        \r\n#define DMA2D_FLAG_CE               DMA2D_ISR_CEIF           /*!< Configuration Error Interrupt Flag */\r\n#define DMA2D_FLAG_CTC              DMA2D_ISR_CTCIF          /*!< CLUT Transfer Complete Interrupt Flag */\r\n#define DMA2D_FLAG_CAE              DMA2D_ISR_CAEIF          /*!< CLUT Access Error Interrupt Flag */\r\n#define DMA2D_FLAG_TW               DMA2D_ISR_TWIF           /*!< Transfer Watermark Interrupt Flag */\r\n#define DMA2D_FLAG_TC               DMA2D_ISR_TCIF           /*!< Transfer Complete Interrupt Flag */\r\n#define DMA2D_FLAG_TE               DMA2D_ISR_TEIF           /*!< Transfer Error Interrupt Flag */\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup DMA2D_Aliases DMA2D API Aliases\r\n  * @{\r\n  */\r\n#define HAL_DMA2D_DisableCLUT       HAL_DMA2D_CLUTLoading_Abort    /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */\r\n/**\r\n  * @}\r\n  */\r\n  \r\n  \r\n/**\r\n  * @}\r\n  */\r\n/* Exported macros ------------------------------------------------------------*/\r\n/** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief Reset DMA2D handle state\r\n  * @param  __HANDLE__: specifies the DMA2D handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)\r\n\r\n/**\r\n  * @brief  Enable the DMA2D.\r\n  * @param  __HANDLE__: DMA2D handle\r\n  * @retval None.\r\n  */\r\n#define __HAL_DMA2D_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)\r\n\r\n\r\n/* Interrupt & Flag management */\r\n/**\r\n  * @brief  Get the DMA2D pending flags.\r\n  * @param  __HANDLE__: DMA2D handle\r\n  * @param  __FLAG__: flag to check.\r\n  *          This parameter can be any combination of the following values:\r\n  *            @arg DMA2D_FLAG_CE:  Configuration error flag\r\n  *            @arg DMA2D_FLAG_CTC: CLUT transfer complete flag\r\n  *            @arg DMA2D_FLAG_CAE: CLUT access error flag\r\n  *            @arg DMA2D_FLAG_TW:  Transfer Watermark flag\r\n  *            @arg DMA2D_FLAG_TC:  Transfer complete flag\r\n  *            @arg DMA2D_FLAG_TE:  Transfer error flag   \r\n  * @retval The state of FLAG.\r\n  */\r\n#define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))\r\n\r\n/**\r\n  * @brief  Clear the DMA2D pending flags.\r\n  * @param  __HANDLE__: DMA2D handle\r\n  * @param  __FLAG__: specifies the flag to clear.\r\n  *          This parameter can be any combination of the following values:\r\n  *            @arg DMA2D_FLAG_CE:  Configuration error flag\r\n  *            @arg DMA2D_FLAG_CTC: CLUT transfer complete flag\r\n  *            @arg DMA2D_FLAG_CAE: CLUT access error flag\r\n  *            @arg DMA2D_FLAG_TW:  Transfer Watermark flag\r\n  *            @arg DMA2D_FLAG_TC:  Transfer complete flag\r\n  *            @arg DMA2D_FLAG_TE:  Transfer error flag    \r\n  * @retval None\r\n  */\r\n#define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))\r\n\r\n/**\r\n  * @brief  Enable the specified DMA2D interrupts.\r\n  * @param  __HANDLE__: DMA2D handle\r\n  * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled. \r\n  *          This parameter can be any combination of the following values:\r\n  *            @arg DMA2D_IT_CE:  Configuration error interrupt mask\r\n  *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask\r\n  *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask\r\n  *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask\r\n  *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask\r\n  *            @arg DMA2D_IT_TE:  Transfer error interrupt mask\r\n  * @retval None\r\n  */\r\n#define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disable the specified DMA2D interrupts.\r\n  * @param  __HANDLE__: DMA2D handle\r\n  * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled. \r\n  *          This parameter can be any combination of the following values:\r\n  *            @arg DMA2D_IT_CE:  Configuration error interrupt mask\r\n  *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask\r\n  *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask\r\n  *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask\r\n  *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask\r\n  *            @arg DMA2D_IT_TE:  Transfer error interrupt mask\r\n  * @retval None\r\n  */\r\n#define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Check whether the specified DMA2D interrupt source is enabled or not.\r\n  * @param  __HANDLE__: DMA2D handle\r\n  * @param  __INTERRUPT__: specifies the DMA2D interrupt source to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg DMA2D_IT_CE:  Configuration error interrupt mask\r\n  *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask\r\n  *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask\r\n  *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask\r\n  *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask\r\n  *            @arg DMA2D_IT_TE:  Transfer error interrupt mask\r\n  * @retval The state of INTERRUPT source.\r\n  */\r\n#define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))\r\n     \r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/  \r\n/** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions\r\n  * @{\r\n  */  \r\n  \r\n/* Initialization and de-initialization functions *******************************/\r\nHAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); \r\nHAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);\r\nvoid              HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);\r\nvoid              HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions\r\n  * @{\r\n  */\r\n  \r\n/* IO operation functions *******************************************************/\r\nHAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);\r\nHAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width,  uint32_t Height);\r\nHAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);\r\nHAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);\r\nHAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);\r\nHAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);\r\nHAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);\r\nHAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);\r\nvoid              HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);\r\nvoid              HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d);\r\nvoid              HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions\r\n  * @{\r\n  */\r\n\r\n/* Peripheral Control functions *************************************************/\r\nHAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);\r\nHAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d);\r\nHAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d);\r\nHAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions\r\n  * @{\r\n  */\r\n\r\n/* Peripheral State functions ***************************************************/\r\nHAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);\r\nuint32_t               HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private constants ---------------------------------------------------------*/  \r\n  \r\n/** @addtogroup DMA2D_Private_Constants DMA2D Private Constants\r\n  * @{\r\n  */                         \r\n\r\n/** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark \r\n  * @{\r\n  */\r\n#define DMA2D_LINE_WATERMARK_MAX            DMA2D_LWR_LW       /*!< DMA2D maximum line watermark */\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup DMA2D_Color_Value DMA2D Color Value\r\n  * @{\r\n  */\r\n#define DMA2D_COLOR_VALUE                 ((uint32_t)0x000000FFU)  /*!< Color value mask */\r\n/**\r\n  * @}\r\n  */      \r\n\r\n/** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers\r\n  * @{\r\n  */  \r\n#define DMA2D_MAX_LAYER         2         /*!< DMA2D maximum number of layers */  \r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/** @defgroup DMA2D_Offset DMA2D Offset \r\n  * @{\r\n  */\r\n#define DMA2D_OFFSET                DMA2D_FGOR_LO            /*!< Line Offset */\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/** @defgroup DMA2D_Size DMA2D Size \r\n  * @{\r\n  */\r\n#define DMA2D_PIXEL                 (DMA2D_NLR_PL >> 16U)    /*!< DMA2D number of pixels per line */\r\n#define DMA2D_LINE                  DMA2D_NLR_NL             /*!< DMA2D number of lines           */\r\n/**\r\n  * @}\r\n  */    \r\n  \r\n/** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size\r\n  * @{\r\n  */\r\n#define DMA2D_CLUT_SIZE             (DMA2D_FGPFCCR_CS >> 8)  /*!< DMA2D CLUT size */\r\n/**\r\n  * @}\r\n  */   \r\n    \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup DMA2D_Private_Macros DMA2D Private Macros\r\n  * @{\r\n  */\r\n#define IS_DMA2D_LAYER(LAYER)                 ((LAYER) <= DMA2D_MAX_LAYER)\r\n#define IS_DMA2D_MODE(MODE)                   (((MODE) == DMA2D_M2M)       || ((MODE) == DMA2D_M2M_PFC) || \\\r\n                                               ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))\r\n#define IS_DMA2D_CMODE(MODE_ARGB)             (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888)   || \\\r\n                                               ((MODE_ARGB) == DMA2D_OUTPUT_RGB565)   || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \\\r\n                                               ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))\r\n#define IS_DMA2D_COLOR(COLOR)                 ((COLOR) <= DMA2D_COLOR_VALUE)\r\n#define IS_DMA2D_LINE(LINE)                   ((LINE) <= DMA2D_LINE)\r\n#define IS_DMA2D_PIXEL(PIXEL)                 ((PIXEL) <= DMA2D_PIXEL)\r\n#define IS_DMA2D_OFFSET(OOFFSET)              ((OOFFSET) <= DMA2D_OFFSET)\r\n#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM)   (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888)   || \\\r\n                                               ((INPUT_CM) == DMA2D_INPUT_RGB565)   || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \\\r\n                                               ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8)       || \\\r\n                                               ((INPUT_CM) == DMA2D_INPUT_AL44)     || ((INPUT_CM) == DMA2D_INPUT_AL88)     || \\\r\n                                               ((INPUT_CM) == DMA2D_INPUT_L4)       || ((INPUT_CM) == DMA2D_INPUT_A8)       || \\\r\n                                               ((INPUT_CM) == DMA2D_INPUT_A4))\r\n#define IS_DMA2D_ALPHA_MODE(AlphaMode)        (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \\\r\n                                               ((AlphaMode) == DMA2D_REPLACE_ALPHA)  || \\\r\n                                               ((AlphaMode) == DMA2D_COMBINE_ALPHA))\r\n\r\n#define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \\\r\n                                                 ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA))\r\n\r\n#define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \\\r\n                                   ((RB_Swap) == DMA2D_RB_SWAP))\r\n\r\n#define IS_DMA2D_CLUT_CM(CLUT_CM)             (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))\r\n#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE)         ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)\r\n#define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)\r\n#define IS_DMA2D_IT(IT)                       (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \\\r\n                                               ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \\\r\n                                               ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))\r\n#define IS_DMA2D_GET_FLAG(FLAG)               (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \\\r\n                                               ((FLAG) == DMA2D_FLAG_TW)   || ((FLAG) == DMA2D_FLAG_TC)  || \\\r\n                                               ((FLAG) == DMA2D_FLAG_TE)   || ((FLAG) == DMA2D_FLAG_CE))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_DMA2D_H */\r\n \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_dma_ex.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of DMA HAL extension module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_DMA_EX_H\r\n#define __STM32F7xx_HAL_DMA_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup DMAEx\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup DMAEx_Exported_Types DMAEx Exported Types\r\n  * @brief DMAEx Exported types\r\n  * @{\r\n  */\r\n   \r\n/** \r\n  * @brief  HAL DMA Memory definition  \r\n  */ \r\ntypedef enum\r\n{\r\n  MEMORY0      = 0x00U,    /*!< Memory 0     */\r\n  MEMORY1      = 0x01U,    /*!< Memory 1     */\r\n\r\n}HAL_DMA_MemoryTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup DMA_Exported_Constants DMA Exported Constants\r\n  * @brief    DMA Exported constants \r\n  * @{\r\n  */\r\n\r\n/** @defgroup DMAEx_Channel_selection DMA Channel selection\r\n  * @brief    DMAEx channel selection \r\n  * @{\r\n  */ \r\n#define DMA_CHANNEL_0        ((uint32_t)0x00000000U)  /*!< DMA Channel 0 */\r\n#define DMA_CHANNEL_1        ((uint32_t)0x02000000U)  /*!< DMA Channel 1 */\r\n#define DMA_CHANNEL_2        ((uint32_t)0x04000000U)  /*!< DMA Channel 2 */\r\n#define DMA_CHANNEL_3        ((uint32_t)0x06000000U)  /*!< DMA Channel 3 */\r\n#define DMA_CHANNEL_4        ((uint32_t)0x08000000U)  /*!< DMA Channel 4 */\r\n#define DMA_CHANNEL_5        ((uint32_t)0x0A000000U)  /*!< DMA Channel 5 */\r\n#define DMA_CHANNEL_6        ((uint32_t)0x0C000000U)  /*!< DMA Channel 6 */\r\n#define DMA_CHANNEL_7        ((uint32_t)0x0E000000U)  /*!< DMA Channel 7 */\r\n#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r\n#define DMA_CHANNEL_8        ((uint32_t)0x10000000U)  /*!< DMA Channel 8 */\r\n#define DMA_CHANNEL_9        ((uint32_t)0x12000000U)  /*!< DMA Channel 9 */\r\n#define DMA_CHANNEL_10       ((uint32_t)0x14000000U)  /*!< DMA Channel 10*/\r\n#define DMA_CHANNEL_11       ((uint32_t)0x16000000U)  /*!< DMA Channel 11*/\r\n#define DMA_CHANNEL_12       ((uint32_t)0x18000000U)  /*!< DMA Channel 12*/\r\n#define DMA_CHANNEL_13       ((uint32_t)0x1A000000U)  /*!< DMA Channel 13*/\r\n#define DMA_CHANNEL_14       ((uint32_t)0x1C000000U)  /*!< DMA Channel 14*/\r\n#define DMA_CHANNEL_15       ((uint32_t)0x1E000000U)  /*!< DMA Channel 15*/\r\n#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */  \r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions\r\n  * @brief   DMAEx Exported functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions\r\n  * @brief   Extended features functions\r\n  * @{\r\n  */\r\n\r\n/* IO operation functions *******************************************************/\r\nHAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);\r\nHAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);\r\nHAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);\r\n\r\n/**\r\n  * @}\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup DMAEx_Private_Macros DMA Private Macros\r\n  * @brief    DMAEx private macros \r\n  * @{\r\n  */\r\n#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r\n#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0)  || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_1)  || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_2)  || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_3)  || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_4)  || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_5)  || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_6)  || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_7)  || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_8)  || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_9)  || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_10) || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_11) || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_12) || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_13) || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_14) || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_15)) \r\n#else\r\n#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_1) || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_2) || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_3) || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_4) || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_5) || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_6) || \\\r\n                                 ((CHANNEL) == DMA_CHANNEL_7))\r\n#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n/**\r\n  * @}\r\n  */  \r\n         \r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup DMAEx_Private_Functions DMAEx Private Functions\r\n  * @brief DMAEx Private functions\r\n  * @{\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_DMA_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dsi.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_dsi.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of DSI HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_DSI_H\r\n#define __STM32F7xx_HAL_DSI_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n#if defined (STM32F769xx) || defined (STM32F779xx)\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup DSI DSI\r\n  * @brief DSI HAL module driver\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** \r\n  * @brief  DSI Init Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t AutomaticClockLaneControl; /*!< Automatic clock lane control\r\n                                           This parameter can be any value of @ref DSI_Automatic_Clk_Lane_Control */\r\n  \r\n  uint32_t TXEscapeCkdiv;             /*!< TX Escape clock division\r\n                                           The values 0 and 1 stop the TX_ESC clock generation                    */\r\n  \r\n  uint32_t NumberOfLanes;             /*!< Number of lanes\r\n                                           This parameter can be any value of @ref DSI_Number_Of_Lanes            */\r\n  \r\n}DSI_InitTypeDef;\r\n\r\n/** \r\n  * @brief  DSI PLL Clock structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t PLLNDIV; /*!< PLL Loop Division Factor\r\n                         This parameter must be a value between 10 and 125   */\r\n  \r\n  uint32_t PLLIDF;  /*!< PLL Input Division Factor\r\n                         This parameter can be any value of @ref DSI_PLL_IDF */\r\n  \r\n  uint32_t PLLODF;  /*!< PLL Output Division Factor\r\n                         This parameter can be any value of @ref DSI_PLL_ODF */\r\n  \r\n}DSI_PLLInitTypeDef;\r\n\r\n/** \r\n  * @brief  DSI Video mode configuration\r\n  */\r\ntypedef struct \r\n{\r\n  uint32_t VirtualChannelID;             /*!< Virtual channel ID                                                 */\r\n  \r\n  uint32_t ColorCoding;                  /*!< Color coding for LTDC interface\r\n                                              This parameter can be any value of @ref DSI_Color_Coding           */\r\n  \r\n  uint32_t LooselyPacked;                /*!< Enable or disable loosely packed stream (needed only when using\r\n                                              18-bit configuration).\r\n                                              This parameter can be any value of @ref DSI_LooselyPacked          */\r\n  \r\n  uint32_t Mode;                         /*!< Video mode type\r\n                                              This parameter can be any value of @ref DSI_Video_Mode_Type        */\r\n                                         \r\n  uint32_t PacketSize;                   /*!< Video packet size                                                  */\r\n                                         \r\n  uint32_t NumberOfChunks;               /*!< Number of chunks                                                   */\r\n                                         \r\n  uint32_t NullPacketSize;               /*!< Null packet size                                                   */\r\n  \r\n  uint32_t HSPolarity;                   /*!< HSYNC pin polarity\r\n                                              This parameter can be any value of @ref DSI_HSYNC_Polarity         */\r\n  \r\n  uint32_t VSPolarity;                   /*!< VSYNC pin polarity\r\n                                              This parameter can be any value of @ref DSI_VSYNC_Polarity         */\r\n  \r\n  uint32_t DEPolarity;                   /*!< Data Enable pin polarity\r\n                                              This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity   */\r\n                                         \r\n  uint32_t HorizontalSyncActive;         /*!< Horizontal synchronism active duration (in lane byte clock cycles) */\r\n                                         \r\n  uint32_t HorizontalBackPorch;          /*!< Horizontal back-porch duration (in lane byte clock cycles)         */\r\n                                         \r\n  uint32_t HorizontalLine;               /*!< Horizontal line duration (in lane byte clock cycles)               */\r\n                                         \r\n  uint32_t VerticalSyncActive;           /*!< Vertical synchronism active duration                               */\r\n                                         \r\n  uint32_t VerticalBackPorch;            /*!< Vertical back-porch duration                                       */\r\n                                         \r\n  uint32_t VerticalFrontPorch;           /*!< Vertical front-porch duration                                      */\r\n                                         \r\n  uint32_t VerticalActive;               /*!< Vertical active duration                                           */\r\n                                         \r\n  uint32_t LPCommandEnable;              /*!< Low-power command enable\r\n                                              This parameter can be any value of @ref DSI_LP_Command             */\r\n  \r\n  uint32_t LPLargestPacketSize;          /*!< The size, in bytes, of the low power largest packet that\r\n                                              can fit in a line during VSA, VBP and VFP regions                  */\r\n           \r\n  uint32_t LPVACTLargestPacketSize;      /*!< The size, in bytes, of the low power largest packet that\r\n                                              can fit in a line during VACT region                               */\r\n           \r\n  uint32_t LPHorizontalFrontPorchEnable; /*!< Low-power horizontal front-porch enable\r\n                                              This parameter can be any value of @ref DSI_LP_HFP                 */\r\n           \r\n  uint32_t LPHorizontalBackPorchEnable;  /*!< Low-power horizontal back-porch enable\r\n                                              This parameter can be any value of @ref DSI_LP_HBP                 */\r\n           \r\n  uint32_t LPVerticalActiveEnable;       /*!< Low-power vertical active enable\r\n                                              This parameter can be any value of @ref DSI_LP_VACT                */\r\n           \r\n  uint32_t LPVerticalFrontPorchEnable;   /*!< Low-power vertical front-porch enable\r\n                                              This parameter can be any value of @ref DSI_LP_VFP                 */\r\n           \r\n  uint32_t LPVerticalBackPorchEnable;    /*!< Low-power vertical back-porch enable\r\n                                              This parameter can be any value of @ref DSI_LP_VBP                 */\r\n           \r\n  uint32_t LPVerticalSyncActiveEnable;   /*!< Low-power vertical sync active enable\r\n                                              This parameter can be any value of @ref DSI_LP_VSYNC               */\r\n           \r\n  uint32_t FrameBTAAcknowledgeEnable;    /*!< Frame bus-turn-around acknowledge enable\r\n                                              This parameter can be any value of @ref DSI_FBTA_acknowledge       */\r\n  \r\n}DSI_VidCfgTypeDef;\r\n\r\n/** \r\n  * @brief  DSI Adapted command mode configuration\r\n  */\r\ntypedef struct \r\n{\r\n  uint32_t VirtualChannelID;      /*!< Virtual channel ID                                                */\r\n  \r\n  uint32_t ColorCoding;           /*!< Color coding for LTDC interface\r\n                                       This parameter can be any value of @ref DSI_Color_Coding          */\r\n  \r\n  uint32_t CommandSize;           /*!< Maximum allowed size for an LTDC write memory command, measured in \r\n                                       pixels. This parameter can be any value between 0x00 and 0xFFFF   */\r\n  \r\n  uint32_t TearingEffectSource;   /*!< Tearing effect source\r\n                                       This parameter can be any value of @ref DSI_TearingEffectSource   */\r\n  \r\n  uint32_t TearingEffectPolarity; /*!< Tearing effect pin polarity\r\n                                       This parameter can be any value of @ref DSI_TearingEffectPolarity */\r\n  \r\n  uint32_t HSPolarity;            /*!< HSYNC pin polarity\r\n                                       This parameter can be any value of @ref DSI_HSYNC_Polarity        */\r\n  \r\n  uint32_t VSPolarity;            /*!< VSYNC pin polarity\r\n                                       This parameter can be any value of @ref DSI_VSYNC_Polarity        */\r\n  \r\n  uint32_t DEPolarity;            /*!< Data Enable pin polarity\r\n                                       This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity  */\r\n  \r\n  uint32_t VSyncPol;              /*!< VSync edge on which the LTDC is halted\r\n                                       This parameter can be any value of @ref DSI_Vsync_Polarity        */\r\n  \r\n  uint32_t AutomaticRefresh;      /*!< Automatic refresh mode\r\n                                       This parameter can be any value of @ref DSI_AutomaticRefresh      */\r\n  \r\n  uint32_t TEAcknowledgeRequest;  /*!< Tearing Effect Acknowledge Request Enable\r\n                                       This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */\r\n  \r\n}DSI_CmdCfgTypeDef;\r\n\r\n/** \r\n  * @brief  DSI command transmission mode configuration\r\n  */\r\ntypedef struct \r\n{\r\n  uint32_t LPGenShortWriteNoP;  /*!< Generic Short Write Zero parameters Transmission\r\n                                     This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP  */\r\n  \r\n  uint32_t LPGenShortWriteOneP; /*!< Generic Short Write One parameter Transmission\r\n                                     This parameter can be any value of @ref DSI_LP_LPGenShortWriteOneP */\r\n  \r\n  uint32_t LPGenShortWriteTwoP; /*!< Generic Short Write Two parameters Transmission\r\n                                     This parameter can be any value of @ref DSI_LP_LPGenShortWriteTwoP */\r\n  \r\n  uint32_t LPGenShortReadNoP;   /*!< Generic Short Read Zero parameters Transmission\r\n                                     This parameter can be any value of @ref DSI_LP_LPGenShortReadNoP   */\r\n           \r\n  uint32_t LPGenShortReadOneP;  /*!< Generic Short Read One parameter Transmission\r\n                                     This parameter can be any value of @ref DSI_LP_LPGenShortReadOneP  */\r\n           \r\n  uint32_t LPGenShortReadTwoP;  /*!< Generic Short Read Two parameters Transmission\r\n                                     This parameter can be any value of @ref DSI_LP_LPGenShortReadTwoP  */\r\n  \r\n  uint32_t LPGenLongWrite;      /*!< Generic Long Write Transmission\r\n                                     This parameter can be any value of @ref DSI_LP_LPGenLongWrite      */\r\n  \r\n  uint32_t LPDcsShortWriteNoP;  /*!< DCS Short Write Zero parameters Transmission\r\n                                     This parameter can be any value of @ref DSI_LP_LPDcsShortWriteNoP  */\r\n  \r\n  uint32_t LPDcsShortWriteOneP; /*!< DCS Short Write One parameter Transmission\r\n                                     This parameter can be any value of @ref DSI_LP_LPDcsShortWriteOneP */\r\n  \r\n  uint32_t LPDcsShortReadNoP;   /*!< DCS Short Read Zero parameters Transmission\r\n                                     This parameter can be any value of @ref DSI_LP_LPDcsShortReadNoP   */\r\n  \r\n  uint32_t LPDcsLongWrite;      /*!< DCS Long Write Transmission\r\n                                     This parameter can be any value of @ref DSI_LP_LPDcsLongWrite      */\r\n  \r\n  uint32_t LPMaxReadPacket;     /*!< Maximum Read Packet Size Transmission\r\n                                     This parameter can be any value of @ref DSI_LP_LPMaxReadPacket     */\r\n  \r\n  uint32_t AcknowledgeRequest;  /*!< Acknowledge Request Enable\r\n                                     This parameter can be any value of @ref DSI_AcknowledgeRequest     */\r\n  \r\n}DSI_LPCmdTypeDef;\r\n\r\n/** \r\n  * @brief  DSI PHY Timings definition\r\n  */\r\ntypedef struct \r\n{\r\n  uint32_t ClockLaneHS2LPTime;        /*!< The maximum time that the D-PHY clock lane takes to go from high-speed\r\n                                           to low-power transmission                                              */\r\n  \r\n  uint32_t ClockLaneLP2HSTime;        /*!< The maximum time that the D-PHY clock lane takes to go from low-power\r\n                                           to high-speed transmission                                             */\r\n  \r\n  uint32_t DataLaneHS2LPTime;         /*!< The maximum time that the D-PHY data lanes takes to go from high-speed\r\n                                           to low-power transmission                                              */\r\n  \r\n  uint32_t DataLaneLP2HSTime;         /*!< The maximum time that the D-PHY data lanes takes to go from low-power\r\n                                           to high-speed transmission                                             */\r\n  \r\n  uint32_t DataLaneMaxReadTime;       /*!< The maximum time required to perform a read command */\r\n  \r\n  uint32_t StopWaitTime;              /*!< The minimum wait period to request a High-Speed transmission after the\r\n                                           Stop state                                                             */\r\n  \r\n}DSI_PHY_TimerTypeDef;\r\n\r\n/** \r\n  * @brief  DSI HOST Timeouts definition\r\n  */\r\ntypedef struct \r\n{\r\n  uint32_t TimeoutCkdiv;                 /*!< Time-out clock division                                  */\r\n  \r\n  uint32_t HighSpeedTransmissionTimeout; /*!< High-speed transmission time-out                         */\r\n  \r\n  uint32_t LowPowerReceptionTimeout;     /*!< Low-power reception time-out                             */\r\n  \r\n  uint32_t HighSpeedReadTimeout;         /*!< High-speed read time-out                                 */\r\n  \r\n  uint32_t LowPowerReadTimeout;          /*!< Low-power read time-out                                  */\r\n  \r\n  uint32_t HighSpeedWriteTimeout;        /*!< High-speed write time-out                                */\r\n  \r\n  uint32_t HighSpeedWritePrespMode;      /*!< High-speed write presp mode\r\n                                              This parameter can be any value of @ref DSI_HS_PrespMode */\r\n  \r\n  uint32_t LowPowerWriteTimeout;         /*!< Low-speed write time-out                                 */\r\n  \r\n  uint32_t BTATimeout;                   /*!< BTA time-out                                             */\r\n  \r\n}DSI_HOST_TimeoutTypeDef;\r\n\r\n/**\r\n  * @brief  DSI States Structure definition\r\n  */\r\ntypedef enum \r\n{\r\n  HAL_DSI_STATE_RESET   = 0x00U,\r\n  HAL_DSI_STATE_READY   = 0x01U,\r\n  HAL_DSI_STATE_ERROR   = 0x02U,\r\n  HAL_DSI_STATE_BUSY    = 0x03U,\r\n  HAL_DSI_STATE_TIMEOUT = 0x04U\r\n}HAL_DSI_StateTypeDef;\r\n\r\n/**\r\n  * @brief  DSI Handle Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  DSI_TypeDef               *Instance;    /*!< Register base address      */\r\n  DSI_InitTypeDef           Init;         /*!< DSI required parameters    */\r\n  HAL_LockTypeDef           Lock;         /*!< DSI peripheral status      */\r\n  __IO HAL_DSI_StateTypeDef State;        /*!< DSI communication state    */\r\n  __IO uint32_t             ErrorCode;    /*!< DSI Error code             */\r\n  uint32_t                  ErrorMsk;     /*!< DSI Error monitoring mask  */\r\n}DSI_HandleTypeDef;\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup DSI_DCS_Command DSI DCS Command\r\n  * @{\r\n  */\r\n#define DSI_ENTER_IDLE_MODE       0x39U\r\n#define DSI_ENTER_INVERT_MODE     0x21U\r\n#define DSI_ENTER_NORMAL_MODE     0x13U\r\n#define DSI_ENTER_PARTIAL_MODE    0x12U\r\n#define DSI_ENTER_SLEEP_MODE      0x10U\r\n#define DSI_EXIT_IDLE_MODE        0x38U\r\n#define DSI_EXIT_INVERT_MODE      0x20U\r\n#define DSI_EXIT_SLEEP_MODE       0x11U\r\n#define DSI_GET_3D_CONTROL        0x3FU\r\n#define DSI_GET_ADDRESS_MODE      0x0BU\r\n#define DSI_GET_BLUE_CHANNEL      0x08U\r\n#define DSI_GET_DIAGNOSTIC_RESULT 0x0FU\r\n#define DSI_GET_DISPLAY_MODE      0x0DU\r\n#define DSI_GET_GREEN_CHANNEL     0x07U\r\n#define DSI_GET_PIXEL_FORMAT      0x0CU\r\n#define DSI_GET_POWER_MODE        0x0AU\r\n#define DSI_GET_RED_CHANNEL       0x06U\r\n#define DSI_GET_SCANLINE          0x45U\r\n#define DSI_GET_SIGNAL_MODE       0x0EU\r\n#define DSI_NOP                   0x00U\r\n#define DSI_READ_DDB_CONTINUE     0xA8U\r\n#define DSI_READ_DDB_START        0xA1U\r\n#define DSI_READ_MEMORY_CONTINUE  0x3EU\r\n#define DSI_READ_MEMORY_START     0x2EU\r\n#define DSI_SET_3D_CONTROL        0x3DU\r\n#define DSI_SET_ADDRESS_MODE      0x36U\r\n#define DSI_SET_COLUMN_ADDRESS    0x2AU\r\n#define DSI_SET_DISPLAY_OFF       0x28U\r\n#define DSI_SET_DISPLAY_ON        0x29U\r\n#define DSI_SET_GAMMA_CURVE       0x26U\r\n#define DSI_SET_PAGE_ADDRESS      0x2BU\r\n#define DSI_SET_PARTIAL_COLUMNS   0x31U\r\n#define DSI_SET_PARTIAL_ROWS      0x30U\r\n#define DSI_SET_PIXEL_FORMAT      0x3AU\r\n#define DSI_SET_SCROLL_AREA       0x33U\r\n#define DSI_SET_SCROLL_START      0x37U\r\n#define DSI_SET_TEAR_OFF          0x34U\r\n#define DSI_SET_TEAR_ON           0x35U\r\n#define DSI_SET_TEAR_SCANLINE     0x44U\r\n#define DSI_SET_VSYNC_TIMING      0x40U\r\n#define DSI_SOFT_RESET            0x01U\r\n#define DSI_WRITE_LUT             0x2DU\r\n#define DSI_WRITE_MEMORY_CONTINUE 0x3CU\r\n#define DSI_WRITE_MEMORY_START    0x2CU\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_Video_Mode_Type DSI Video Mode Type\r\n  * @{\r\n  */\r\n#define DSI_VID_MODE_NB_PULSES 0U\r\n#define DSI_VID_MODE_NB_EVENTS 1U\r\n#define DSI_VID_MODE_BURST     2U\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_Color_Mode DSI Color Mode\r\n  * @{\r\n  */\r\n#define DSI_COLOR_MODE_FULL  0U\r\n#define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_ShutDown DSI ShutDown\r\n  * @{\r\n  */\r\n#define DSI_DISPLAY_ON  0U\r\n#define DSI_DISPLAY_OFF DSI_WCR_SHTDN\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_LP_Command DSI LP Command\r\n  * @{\r\n  */\r\n#define DSI_LP_COMMAND_DISABLE 0U\r\n#define DSI_LP_COMMAND_ENABLE  DSI_VMCR_LPCE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_LP_HFP DSI LP HFP\r\n  * @{\r\n  */\r\n#define DSI_LP_HFP_DISABLE 0U\r\n#define DSI_LP_HFP_ENABLE  DSI_VMCR_LPHFPE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_LP_HBP DSI LP HBP\r\n  * @{\r\n  */\r\n#define DSI_LP_HBP_DISABLE 0U\r\n#define DSI_LP_HBP_ENABLE  DSI_VMCR_LPHBPE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_LP_VACT DSI LP VACT\r\n  * @{\r\n  */\r\n#define DSI_LP_VACT_DISABLE 0U\r\n#define DSI_LP_VACT_ENABLE  DSI_VMCR_LPVAE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_LP_VFP DSI LP VFP\r\n  * @{\r\n  */\r\n#define DSI_LP_VFP_DISABLE 0\r\n#define DSI_LP_VFP_ENABLE  DSI_VMCR_LPVFPE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_LP_VBP DSI LP VBP\r\n  * @{\r\n  */\r\n#define DSI_LP_VBP_DISABLE 0U\r\n#define DSI_LP_VBP_ENABLE  DSI_VMCR_LPVBPE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_LP_VSYNC DSI LP VSYNC\r\n  * @{\r\n  */\r\n#define DSI_LP_VSYNC_DISABLE 0U\r\n#define DSI_LP_VSYNC_ENABLE  DSI_VMCR_LPVSAE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_FBTA_acknowledge DSI FBTA Acknowledge\r\n  * @{\r\n  */\r\n#define DSI_FBTAA_DISABLE 0U\r\n#define DSI_FBTAA_ENABLE  DSI_VMCR_FBTAAE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_TearingEffectSource DSI Tearing Effect Source\r\n  * @{\r\n  */\r\n#define DSI_TE_DSILINK  0U\r\n#define DSI_TE_EXTERNAL DSI_WCFGR_TESRC\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_TearingEffectPolarity DSI Tearing Effect Polarity\r\n  * @{\r\n  */\r\n#define DSI_TE_RISING_EDGE  0U\r\n#define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_Vsync_Polarity DSI Vsync Polarity\r\n  * @{\r\n  */\r\n#define DSI_VSYNC_FALLING 0U\r\n#define DSI_VSYNC_RISING  DSI_WCFGR_VSPOL\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_AutomaticRefresh DSI Automatic Refresh\r\n  * @{\r\n  */\r\n#define DSI_AR_DISABLE 0U\r\n#define DSI_AR_ENABLE  DSI_WCFGR_AR\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_TE_AcknowledgeRequest DSI TE Acknowledge Request\r\n  * @{\r\n  */\r\n#define DSI_TE_ACKNOWLEDGE_DISABLE 0U\r\n#define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_AcknowledgeRequest DSI Acknowledge Request\r\n  * @{\r\n  */\r\n#define DSI_ACKNOWLEDGE_DISABLE 0U\r\n#define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_LP_LPGenShortWriteNoP DSI LP LPGen Short Write NoP\r\n  * @{\r\n  */\r\n#define DSI_LP_GSW0P_DISABLE 0U\r\n#define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_LP_LPGenShortWriteOneP DSI LP LPGen Short Write OneP\r\n  * @{\r\n  */\r\n#define DSI_LP_GSW1P_DISABLE 0U\r\n#define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_LP_LPGenShortWriteTwoP DSI LP LPGen Short Write TwoP\r\n  * @{\r\n  */\r\n#define DSI_LP_GSW2P_DISABLE 0U\r\n#define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_LP_LPGenShortReadNoP DSI LP LPGen Short Read NoP\r\n  * @{\r\n  */\r\n#define DSI_LP_GSR0P_DISABLE 0U\r\n#define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_LP_LPGenShortReadOneP DSI LP LPGen Short Read OneP\r\n  * @{\r\n  */\r\n#define DSI_LP_GSR1P_DISABLE 0U\r\n#define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_LP_LPGenShortReadTwoP DSI LP LPGen Short Read TwoP\r\n  * @{\r\n  */\r\n#define DSI_LP_GSR2P_DISABLE 0U\r\n#define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_LP_LPGenLongWrite DSI LP LPGen LongWrite\r\n  * @{\r\n  */\r\n#define DSI_LP_GLW_DISABLE 0U\r\n#define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_LP_LPDcsShortWriteNoP DSI LP LPDcs Short Write NoP\r\n  * @{\r\n  */\r\n#define DSI_LP_DSW0P_DISABLE 0U\r\n#define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_LP_LPDcsShortWriteOneP DSI LP LPDcs Short Write OneP\r\n  * @{\r\n  */\r\n#define DSI_LP_DSW1P_DISABLE 0U\r\n#define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_LP_LPDcsShortReadNoP DSI LP LPDcs Short Read NoP\r\n  * @{\r\n  */\r\n#define DSI_LP_DSR0P_DISABLE 0U\r\n#define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_LP_LPDcsLongWrite DSI LP LPDcs Long Write\r\n  * @{\r\n  */\r\n#define DSI_LP_DLW_DISABLE 0U\r\n#define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_LP_LPMaxReadPacket DSI LP LPMax Read Packet\r\n  * @{\r\n  */\r\n#define DSI_LP_MRDP_DISABLE 0U\r\n#define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_HS_PrespMode DSI HS Presp Mode\r\n  * @{\r\n  */\r\n#define DSI_HS_PM_DISABLE 0U\r\n#define DSI_HS_PM_ENABLE DSI_TCCR3_PM\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup DSI_Automatic_Clk_Lane_Control DSI Automatic Clk Lane Control\r\n  * @{\r\n  */\r\n#define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0U\r\n#define DSI_AUTO_CLK_LANE_CTRL_ENABLE  DSI_CLCR_ACR\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_Number_Of_Lanes DSI Number Of Lanes\r\n  * @{\r\n  */\r\n#define DSI_ONE_DATA_LANE  0U\r\n#define DSI_TWO_DATA_LANES 1U\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_FlowControl DSI Flow Control\r\n  * @{\r\n  */\r\n#define DSI_FLOW_CONTROL_CRC_RX  DSI_PCR_CRCRXE\r\n#define DSI_FLOW_CONTROL_ECC_RX  DSI_PCR_ECCRXE\r\n#define DSI_FLOW_CONTROL_BTA     DSI_PCR_BTAE\r\n#define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE\r\n#define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE\r\n#define DSI_FLOW_CONTROL_ALL     (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \\\r\n                                  DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \\\r\n                                  DSI_FLOW_CONTROL_EOTP_TX)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_Color_Coding DSI Color Coding\r\n  * @{\r\n  */\r\n#define DSI_RGB565 ((uint32_t)0x00000000U) /*!< The values 0x00000001 and 0x00000002 can also be used for the RGB565 color mode configuration */\r\n#define DSI_RGB666 ((uint32_t)0x00000003U) /*!< The value 0x00000004 can also be used for the RGB666 color mode configuration                 */\r\n#define DSI_RGB888 ((uint32_t)0x00000005U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_LooselyPacked DSI Loosely Packed\r\n  * @{\r\n  */\r\n#define DSI_LOOSELY_PACKED_ENABLE  DSI_LCOLCR_LPE\r\n#define DSI_LOOSELY_PACKED_DISABLE 0U\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_HSYNC_Polarity DSI HSYNC Polarity\r\n  * @{\r\n  */\r\n#define DSI_HSYNC_ACTIVE_HIGH       0U\r\n#define DSI_HSYNC_ACTIVE_LOW        DSI_LPCR_HSP\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_VSYNC_Polarity DSI VSYNC Polarity\r\n  * @{\r\n  */\r\n#define DSI_VSYNC_ACTIVE_HIGH       0U\r\n#define DSI_VSYNC_ACTIVE_LOW        DSI_LPCR_VSP\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_DATA_ENABLE_Polarity DSI DATA ENABLE Polarity\r\n  * @{\r\n  */\r\n#define DSI_DATA_ENABLE_ACTIVE_HIGH 0U\r\n#define DSI_DATA_ENABLE_ACTIVE_LOW  DSI_LPCR_DEP\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_PLL_IDF DSI PLL IDF\r\n  * @{\r\n  */\r\n#define DSI_PLL_IN_DIV1 ((uint32_t)0x00000001U)\r\n#define DSI_PLL_IN_DIV2 ((uint32_t)0x00000002U)\r\n#define DSI_PLL_IN_DIV3 ((uint32_t)0x00000003U)\r\n#define DSI_PLL_IN_DIV4 ((uint32_t)0x00000004U)\r\n#define DSI_PLL_IN_DIV5 ((uint32_t)0x00000005U)\r\n#define DSI_PLL_IN_DIV6 ((uint32_t)0x00000006U)\r\n#define DSI_PLL_IN_DIV7 ((uint32_t)0x00000007U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_PLL_ODF DSI PLL ODF\r\n  * @{\r\n  */\r\n#define DSI_PLL_OUT_DIV1 ((uint32_t)0x00000000U)\r\n#define DSI_PLL_OUT_DIV2 ((uint32_t)0x00000001U)\r\n#define DSI_PLL_OUT_DIV4 ((uint32_t)0x00000002U)\r\n#define DSI_PLL_OUT_DIV8 ((uint32_t)0x00000003U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_Flags DSI Flags\r\n  * @{\r\n  */\r\n#define DSI_FLAG_TE    DSI_WISR_TEIF\r\n#define DSI_FLAG_ER    DSI_WISR_ERIF\r\n#define DSI_FLAG_BUSY  DSI_WISR_BUSY\r\n#define DSI_FLAG_PLLLS DSI_WISR_PLLLS\r\n#define DSI_FLAG_PLLL  DSI_WISR_PLLLIF\r\n#define DSI_FLAG_PLLU  DSI_WISR_PLLUIF\r\n#define DSI_FLAG_RRS   DSI_WISR_RRS\r\n#define DSI_FLAG_RR    DSI_WISR_RRIF\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_Interrupts DSI Interrupts\r\n  * @{\r\n  */\r\n#define DSI_IT_TE   DSI_WIER_TEIE\r\n#define DSI_IT_ER   DSI_WIER_ERIE\r\n#define DSI_IT_PLLL DSI_WIER_PLLLIE\r\n#define DSI_IT_PLLU DSI_WIER_PLLUIE\r\n#define DSI_IT_RR   DSI_WIER_RRIE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_SHORT_WRITE_PKT_Data_Type DSI SHORT WRITE PKT Data Type\r\n  * @{\r\n  */\r\n#define DSI_DCS_SHORT_PKT_WRITE_P0 ((uint32_t)0x00000005U) /*!< DCS short write, no parameters      */\r\n#define DSI_DCS_SHORT_PKT_WRITE_P1 ((uint32_t)0x00000015U) /*!< DCS short write, one parameter      */\r\n#define DSI_GEN_SHORT_PKT_WRITE_P0 ((uint32_t)0x00000003U) /*!< Generic short write, no parameters  */\r\n#define DSI_GEN_SHORT_PKT_WRITE_P1 ((uint32_t)0x00000013U) /*!< Generic short write, one parameter  */\r\n#define DSI_GEN_SHORT_PKT_WRITE_P2 ((uint32_t)0x00000023U) /*!< Generic short write, two parameters */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_LONG_WRITE_PKT_Data_Type DSI LONG WRITE PKT Data Type\r\n  * @{\r\n  */\r\n#define DSI_DCS_LONG_PKT_WRITE ((uint32_t)0x00000039U) /*!< DCS long write     */\r\n#define DSI_GEN_LONG_PKT_WRITE ((uint32_t)0x00000029U) /*!< Generic long write */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_SHORT_READ_PKT_Data_Type DSI SHORT READ PKT Data Type\r\n  * @{\r\n  */\r\n#define DSI_DCS_SHORT_PKT_READ    ((uint32_t)0x00000006U) /*!< DCS short read                     */\r\n#define DSI_GEN_SHORT_PKT_READ_P0 ((uint32_t)0x00000004U) /*!< Generic short read, no parameters  */\r\n#define DSI_GEN_SHORT_PKT_READ_P1 ((uint32_t)0x00000014U) /*!< Generic short read, one parameter  */\r\n#define DSI_GEN_SHORT_PKT_READ_P2 ((uint32_t)0x00000024U) /*!< Generic short read, two parameters */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_Error_Data_Type DSI Error Data Type\r\n  * @{\r\n  */\r\n#define HAL_DSI_ERROR_NONE 0\r\n#define HAL_DSI_ERROR_ACK  ((uint32_t)0x00000001U) /*!< acknowledge errors          */\r\n#define HAL_DSI_ERROR_PHY  ((uint32_t)0x00000002U) /*!< PHY related errors          */\r\n#define HAL_DSI_ERROR_TX   ((uint32_t)0x00000004U) /*!< transmission error          */\r\n#define HAL_DSI_ERROR_RX   ((uint32_t)0x00000008U) /*!< reception error             */\r\n#define HAL_DSI_ERROR_ECC  ((uint32_t)0x00000010U) /*!< ECC errors                  */\r\n#define HAL_DSI_ERROR_CRC  ((uint32_t)0x00000020U) /*!< CRC error                   */\r\n#define HAL_DSI_ERROR_PSE  ((uint32_t)0x00000040U) /*!< Packet Size error           */\r\n#define HAL_DSI_ERROR_EOT  ((uint32_t)0x00000080U) /*!< End Of Transmission error   */\r\n#define HAL_DSI_ERROR_OVF  ((uint32_t)0x00000100U) /*!< FIFO overflow error         */\r\n#define HAL_DSI_ERROR_GEN  ((uint32_t)0x00000200U) /*!< Generic FIFO related errors */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_Lane_Group DSI Lane Group\r\n  * @{\r\n  */\r\n#define DSI_CLOCK_LANE ((uint32_t)0x00000000U)\r\n#define DSI_DATA_LANES ((uint32_t)0x00000001U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_Communication_Delay DSI Communication Delay\r\n  * @{\r\n  */\r\n#define DSI_SLEW_RATE_HSTX ((uint32_t)0x00000000U)\r\n#define DSI_SLEW_RATE_LPTX ((uint32_t)0x00000001U)\r\n#define DSI_HS_DELAY       ((uint32_t)0x00000002U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_CustomLane DSI CustomLane\r\n  * @{\r\n  */\r\n#define DSI_SWAP_LANE_PINS   ((uint32_t)0x00000000U)\r\n#define DSI_INVERT_HS_SIGNAL ((uint32_t)0x00000001U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_Lane_Select DSI Lane Select\r\n  * @{\r\n  */\r\n#define DSI_CLOCK_LANE ((uint32_t)0x00000000U)\r\n#define DSI_DATA_LANE0 ((uint32_t)0x00000001U)\r\n#define DSI_DATA_LANE1 ((uint32_t)0x00000002U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_PHY_Timing DSI PHY Timing\r\n  * @{\r\n  */\r\n#define DSI_TCLK_POST    ((uint32_t)0x00000000U)\r\n#define DSI_TLPX_CLK     ((uint32_t)0x00000001U)\r\n#define DSI_THS_EXIT     ((uint32_t)0x00000002U)\r\n#define DSI_TLPX_DATA    ((uint32_t)0x00000003U)\r\n#define DSI_THS_ZERO     ((uint32_t)0x00000004U)\r\n#define DSI_THS_TRAIL    ((uint32_t)0x00000005U)\r\n#define DSI_THS_PREPARE  ((uint32_t)0x00000006U)\r\n#define DSI_TCLK_ZERO    ((uint32_t)0x00000007U)\r\n#define DSI_TCLK_PREPARE ((uint32_t)0x00000008U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macros -----------------------------------------------------------*/\r\n/**\r\n  * @brief  Enables the DSI host.\r\n  * @param  __HANDLE__: DSI handle\r\n  * @retval None.\r\n  */\r\n#define __HAL_DSI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DSI_CR_EN)\r\n\r\n/**\r\n  * @brief  Disables the DSI host.\r\n  * @param  __HANDLE__: DSI handle\r\n  * @retval None.\r\n  */\r\n#define __HAL_DSI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DSI_CR_EN)\r\n\r\n/**\r\n  * @brief  Enables the DSI wrapper.\r\n  * @param  __HANDLE__: DSI handle\r\n  * @retval None.\r\n  */\r\n#define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WCR |= DSI_WCR_DSIEN)\r\n\r\n/**\r\n  * @brief  Disable the DSI wrapper.\r\n  * @param  __HANDLE__: DSI handle\r\n  * @retval None.\r\n  */\r\n#define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WCR &= ~DSI_WCR_DSIEN)\r\n\r\n/**\r\n  * @brief  Enables the DSI PLL.\r\n  * @param  __HANDLE__: DSI handle\r\n  * @retval None.\r\n  */\r\n#define __HAL_DSI_PLL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR |= DSI_WRPCR_PLLEN)\r\n\r\n/**\r\n  * @brief  Disables the DSI PLL.\r\n  * @param  __HANDLE__: DSI handle\r\n  * @retval None.\r\n  */\r\n#define __HAL_DSI_PLL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR &= ~DSI_WRPCR_PLLEN)\r\n\r\n/**\r\n  * @brief  Enables the DSI regulator.\r\n  * @param  __HANDLE__: DSI handle\r\n  * @retval None.\r\n  */\r\n#define __HAL_DSI_REG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR |= DSI_WRPCR_REGEN)\r\n\r\n/**\r\n  * @brief  Disables the DSI regulator.\r\n  * @param  __HANDLE__: DSI handle\r\n  * @retval None.\r\n  */\r\n#define __HAL_DSI_REG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR &= ~DSI_WRPCR_REGEN)\r\n\r\n/**\r\n  * @brief  Get the DSI pending flags.\r\n  * @param  __HANDLE__: DSI handle.\r\n  * @param  __FLAG__: Get the specified flag.\r\n  *          This parameter can be any combination of the following values:\r\n  *            @arg DSI_FLAG_TE   : Tearing Effect Interrupt Flag \r\n  *            @arg DSI_FLAG_ER   : End of Refresh Interrupt Flag \r\n  *            @arg DSI_FLAG_BUSY : Busy Flag\r\n  *            @arg DSI_FLAG_PLLLS: PLL Lock Status\r\n  *            @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag\r\n  *            @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag\r\n  *            @arg DSI_FLAG_RRS  : Regulator Ready Flag\r\n  *            @arg DSI_FLAG_RR   : Regulator Ready Interrupt Flag\r\n  * @retval The state of FLAG (SET or RESET).\r\n  */\r\n#define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__))\r\n\r\n/**\r\n  * @brief  Clears the DSI pending flags.\r\n  * @param  __HANDLE__: DSI handle.\r\n  * @param  __FLAG__: specifies the flag to clear.\r\n  *          This parameter can be any combination of the following values:\r\n  *            @arg DSI_FLAG_TE   : Tearing Effect Interrupt Flag \r\n  *            @arg DSI_FLAG_ER   : End of Refresh Interrupt Flag \r\n  *            @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag\r\n  *            @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag\r\n  *            @arg DSI_FLAG_RR   : Regulator Ready Interrupt Flag\r\n  * @retval None\r\n  */\r\n#define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__))\r\n\r\n/**\r\n  * @brief  Enables the specified DSI interrupts.\r\n  * @param  __HANDLE__: DSI handle.\r\n  * @param __INTERRUPT__: specifies the DSI interrupt sources to be enabled. \r\n  *          This parameter can be any combination of the following values:\r\n  *            @arg DSI_IT_TE  : Tearing Effect Interrupt\r\n  *            @arg DSI_IT_ER  : End of Refresh Interrupt\r\n  *            @arg DSI_IT_PLLL: PLL Lock Interrupt\r\n  *            @arg DSI_IT_PLLU: PLL Unlock Interrupt\r\n  *            @arg DSI_IT_RR  : Regulator Ready Interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER |= (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disables the specified DSI interrupts.\r\n  * @param  __HANDLE__: DSI handle\r\n  * @param __INTERRUPT__: specifies the DSI interrupt sources to be disabled. \r\n  *          This parameter can be any combination of the following values:\r\n  *            @arg DSI_IT_TE  : Tearing Effect Interrupt\r\n  *            @arg DSI_IT_ER  : End of Refresh Interrupt\r\n  *            @arg DSI_IT_PLLL: PLL Lock Interrupt\r\n  *            @arg DSI_IT_PLLU: PLL Unlock Interrupt\r\n  *            @arg DSI_IT_RR  : Regulator Ready Interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Checks whether the specified DSI interrupt has occurred or not.\r\n  * @param  __HANDLE__: DSI handle\r\n  * @param  __INTERRUPT__: specifies the DSI interrupt source to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg DSI_IT_TE  : Tearing Effect Interrupt\r\n  *            @arg DSI_IT_ER  : End of Refresh Interrupt\r\n  *            @arg DSI_IT_PLLL: PLL Lock Interrupt\r\n  *            @arg DSI_IT_PLLU: PLL Unlock Interrupt\r\n  *            @arg DSI_IT_RR  : Regulator Ready Interrupt\r\n  * @retval The state of INTERRUPT (SET or RESET).\r\n  */\r\n#define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WISR & (__INTERRUPT__))\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup DSI_Exported_Functions DSI Exported Functions\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit);\r\nHAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi);\r\nvoid HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi);\r\nvoid HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi);\r\n\r\nvoid HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi);\r\nvoid HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi);\r\nvoid HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi);\r\nvoid HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi);\r\n\r\nHAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID);\r\nHAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg);\r\nHAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg);\r\nHAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd);\r\nHAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl);\r\nHAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers);\r\nHAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts);\r\nHAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi);\r\nHAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi);\r\nHAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi);\r\nHAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode);\r\nHAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown);\r\nHAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,\r\n                                     uint32_t ChannelID,\r\n                                     uint32_t Mode,\r\n                                     uint32_t Param1,\r\n                                     uint32_t Param2);\r\nHAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,\r\n                                    uint32_t ChannelID,\r\n                                    uint32_t Mode,\r\n                                    uint32_t NbParams,\r\n                                    uint32_t Param1,\r\n                                    uint8_t* ParametersTable);\r\nHAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,\r\n                               uint32_t ChannelNbr,\r\n                               uint8_t* Array,\r\n                               uint32_t Size,\r\n                               uint32_t Mode,\r\n                               uint32_t DCSCmd,\r\n                               uint8_t* ParametersTable);\r\nHAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi);\r\nHAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi);\r\nHAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi);\r\nHAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi);\r\n\r\nHAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation);\r\nHAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi);\r\n\r\nHAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value);\r\nHAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency);\r\nHAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State);\r\nHAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State);\r\nHAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value);\r\nHAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State);\r\nHAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State);\r\nHAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State);\r\nHAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State);\r\nHAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State);\r\n\r\nuint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi);\r\nHAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors);\r\nHAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/** @defgroup DSI_Private_Types DSI Private Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private defines -----------------------------------------------------------*/\r\n/** @defgroup DSI_Private_Defines DSI Private Defines\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n          \r\n/* Private variables ---------------------------------------------------------*/\r\n/** @defgroup DSI_Private_Variables DSI Private Variables\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup DSI_Private_Constants DSI Private Constants\r\n  * @{\r\n  */\r\n#define DSI_MAX_RETURN_PKT_SIZE ((uint32_t)0x00000037) /*!< Maximum return packet configuration */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup DSI_Private_Macros DSI Private Macros\r\n  * @{\r\n  */\r\n#define IS_DSI_PLL_NDIV(NDIV)                       ((10U <= (NDIV)) && ((NDIV) <= 125U))\r\n#define IS_DSI_PLL_IDF(IDF)                         (((IDF) == DSI_PLL_IN_DIV1) || \\\r\n                                                     ((IDF) == DSI_PLL_IN_DIV2) || \\\r\n                                                     ((IDF) == DSI_PLL_IN_DIV3) || \\\r\n                                                     ((IDF) == DSI_PLL_IN_DIV4) || \\\r\n                                                     ((IDF) == DSI_PLL_IN_DIV5) || \\\r\n                                                     ((IDF) == DSI_PLL_IN_DIV6) || \\\r\n                                                     ((IDF) == DSI_PLL_IN_DIV7))\r\n#define IS_DSI_PLL_ODF(ODF)                         (((ODF) == DSI_PLL_OUT_DIV1) || \\\r\n                                                     ((ODF) == DSI_PLL_OUT_DIV2) || \\\r\n                                                     ((ODF) == DSI_PLL_OUT_DIV4) || \\\r\n                                                     ((ODF) == DSI_PLL_OUT_DIV8))\r\n#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane)    (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))\r\n#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes)       (((NumberOfLanes) == DSI_ONE_DATA_LANE) || ((NumberOfLanes) == DSI_TWO_DATA_LANES))\r\n#define IS_DSI_FLOW_CONTROL(FlowControl)            (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL)\r\n#define IS_DSI_COLOR_CODING(ColorCoding)            ((ColorCoding) <= 5)\r\n#define IS_DSI_LOOSELY_PACKED(LooselyPacked)        (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))\r\n#define IS_DSI_DE_POLARITY(DataEnable)              (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))\r\n#define IS_DSI_VSYNC_POLARITY(VSYNC)                (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))\r\n#define IS_DSI_HSYNC_POLARITY(HSYNC)                (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW))\r\n#define IS_DSI_VIDEO_MODE_TYPE(VideoModeType)       (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \\\r\n                                                     ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \\\r\n                                                     ((VideoModeType) == DSI_VID_MODE_BURST))\r\n#define IS_DSI_COLOR_MODE(ColorMode)                (((ColorMode) == DSI_COLOR_MODE_FULL) || ((ColorMode) == DSI_COLOR_MODE_EIGHT))\r\n#define IS_DSI_SHUT_DOWN(ShutDown)                  (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF))\r\n#define IS_DSI_LP_COMMAND(LPCommand)                (((LPCommand) == DSI_LP_COMMAND_DISABLE) || ((LPCommand) == DSI_LP_COMMAND_ENABLE))\r\n#define IS_DSI_LP_HFP(LPHFP)                        (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE))\r\n#define IS_DSI_LP_HBP(LPHBP)                        (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE))\r\n#define IS_DSI_LP_VACTIVE(LPVActive)                (((LPVActive) == DSI_LP_VACT_DISABLE) || ((LPVActive) == DSI_LP_VACT_ENABLE))\r\n#define IS_DSI_LP_VFP(LPVFP)                        (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE))\r\n#define IS_DSI_LP_VBP(LPVBP)                        (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE))\r\n#define IS_DSI_LP_VSYNC(LPVSYNC)                    (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE))\r\n#define IS_DSI_FBTAA(FrameBTAAcknowledge)           (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE))\r\n#define IS_DSI_TE_SOURCE(TESource)                  (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL))\r\n#define IS_DSI_TE_POLARITY(TEPolarity)              (((TEPolarity) == DSI_TE_RISING_EDGE) || ((TEPolarity) == DSI_TE_FALLING_EDGE))\r\n#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh)  (((AutomaticRefresh) == DSI_AR_DISABLE) || ((AutomaticRefresh) == DSI_AR_ENABLE))\r\n#define IS_DSI_VS_POLARITY(VSPolarity)              (((VSPolarity) == DSI_VSYNC_FALLING) || ((VSPolarity) == DSI_VSYNC_RISING))\r\n#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE))\r\n#define IS_DSI_ACK_REQUEST(AcknowledgeRequest)      (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE))\r\n#define IS_DSI_LP_GSW0P(LP_GSW0P)                   (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE))\r\n#define IS_DSI_LP_GSW1P(LP_GSW1P)                   (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE))\r\n#define IS_DSI_LP_GSW2P(LP_GSW2P)                   (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE))\r\n#define IS_DSI_LP_GSR0P(LP_GSR0P)                   (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE))\r\n#define IS_DSI_LP_GSR1P(LP_GSR1P)                   (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE))\r\n#define IS_DSI_LP_GSR2P(LP_GSR2P)                   (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE))\r\n#define IS_DSI_LP_GLW(LP_GLW)                       (((LP_GLW) == DSI_LP_GLW_DISABLE) || ((LP_GLW) == DSI_LP_GLW_ENABLE))\r\n#define IS_DSI_LP_DSW0P(LP_DSW0P)                   (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE))\r\n#define IS_DSI_LP_DSW1P(LP_DSW1P)                   (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE))\r\n#define IS_DSI_LP_DSR0P(LP_DSR0P)                   (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE))\r\n#define IS_DSI_LP_DLW(LP_DLW)                       (((LP_DLW) == DSI_LP_DLW_DISABLE) || ((LP_DLW) == DSI_LP_DLW_ENABLE))\r\n#define IS_DSI_LP_MRDP(LP_MRDP)                     (((LP_MRDP) == DSI_LP_MRDP_DISABLE) || ((LP_MRDP) == DSI_LP_MRDP_ENABLE))\r\n#define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE)        (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \\\r\n                                                     ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \\\r\n                                                     ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \\\r\n                                                     ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) || \\\r\n                                                     ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2))\r\n#define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE)         (((MODE) == DSI_DCS_LONG_PKT_WRITE) || \\\r\n                                                     ((MODE) == DSI_GEN_LONG_PKT_WRITE))\r\n#define IS_DSI_READ_PACKET_TYPE(MODE)               (((MODE) == DSI_DCS_SHORT_PKT_READ) || \\\r\n                                                     ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \\\r\n                                                     ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \\\r\n                                                     ((MODE) == DSI_GEN_SHORT_PKT_READ_P2))\r\n#define IS_DSI_COMMUNICATION_DELAY(CommDelay)       (((CommDelay) == DSI_SLEW_RATE_HSTX) || ((CommDelay) == DSI_SLEW_RATE_LPTX) || ((CommDelay) == DSI_HS_DELAY))\r\n#define IS_DSI_LANE_GROUP(Lane)                     (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES))\r\n#define IS_DSI_CUSTOM_LANE(CustomLane)              (((CustomLane) == DSI_SWAP_LANE_PINS) || ((CustomLane) == DSI_INVERT_HS_SIGNAL))\r\n#define IS_DSI_LANE(Lane)                           (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1))\r\n#define IS_DSI_PHY_TIMING(Timing)                   (((Timing) == DSI_TCLK_POST   ) || \\\r\n                                                     ((Timing) == DSI_TLPX_CLK    ) || \\\r\n                                                     ((Timing) == DSI_THS_EXIT    ) || \\\r\n                                                     ((Timing) == DSI_TLPX_DATA   ) || \\\r\n                                                     ((Timing) == DSI_THS_ZERO    ) || \\\r\n                                                     ((Timing) == DSI_THS_TRAIL   ) || \\\r\n                                                     ((Timing) == DSI_THS_PREPARE ) || \\\r\n                                                     ((Timing) == DSI_TCLK_ZERO   ) || \\\r\n                                                     ((Timing) == DSI_TCLK_PREPARE))\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private functions prototypes ----------------------------------------------*/\r\n/** @defgroup DSI_Private_Functions_Prototypes DSI Private Functions Prototypes\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup DSI_Private_Functions DSI Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n#endif /*STM32F769xx | STM32F779xx */\r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_DSI_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_eth.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of ETH HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_ETH_H\r\n#define __STM32F7xx_HAL_ETH_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup ETH\r\n  * @{\r\n  */ \r\n  \r\n/** @addtogroup ETH_Private_Macros\r\n  * @{\r\n  */\r\n#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)\r\n#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \\\r\n                                     ((CMD) == ETH_AUTONEGOTIATION_DISABLE))\r\n#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \\\r\n                             ((SPEED) == ETH_SPEED_100M))\r\n#define IS_ETH_DUPLEX_MODE(MODE)  (((MODE) == ETH_MODE_FULLDUPLEX) || \\\r\n                                  ((MODE) == ETH_MODE_HALFDUPLEX))\r\n#define IS_ETH_RX_MODE(MODE)    (((MODE) == ETH_RXPOLLING_MODE) || \\\r\n                                 ((MODE) == ETH_RXINTERRUPT_MODE)) \r\n#define IS_ETH_CHECKSUM_MODE(MODE)    (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \\\r\n                                      ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))\r\n#define IS_ETH_MEDIA_INTERFACE(MODE)         (((MODE) == ETH_MEDIA_INTERFACE_MII) || \\\r\n                                              ((MODE) == ETH_MEDIA_INTERFACE_RMII))\r\n#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \\\r\n                              ((CMD) == ETH_WATCHDOG_DISABLE))\r\n#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \\\r\n                            ((CMD) == ETH_JABBER_DISABLE))\r\n#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \\\r\n                                     ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \\\r\n                                     ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \\\r\n                                     ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \\\r\n                                     ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \\\r\n                                     ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \\\r\n                                     ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \\\r\n                                     ((GAP) == ETH_INTERFRAMEGAP_40BIT))\r\n#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \\\r\n                                   ((CMD) == ETH_CARRIERSENCE_DISABLE))\r\n#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \\\r\n                                 ((CMD) == ETH_RECEIVEOWN_DISABLE))\r\n#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \\\r\n                                   ((CMD) == ETH_LOOPBACKMODE_DISABLE))\r\n#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \\\r\n                                      ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))\r\n#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \\\r\n                                        ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))\r\n#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \\\r\n                                            ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))\r\n#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \\\r\n                                     ((LIMIT) == ETH_BACKOFFLIMIT_8) || \\\r\n                                     ((LIMIT) == ETH_BACKOFFLIMIT_4) || \\\r\n                                     ((LIMIT) == ETH_BACKOFFLIMIT_1))\r\n#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \\\r\n                                    ((CMD) == ETH_DEFFERRALCHECK_DISABLE))\r\n#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \\\r\n                                 ((CMD) == ETH_RECEIVEAll_DISABLE))\r\n#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \\\r\n                                        ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \\\r\n                                        ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))\r\n#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \\\r\n                                     ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \\\r\n                                     ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))\r\n#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \\\r\n                                                ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))\r\n#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \\\r\n                                                ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))\r\n#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \\\r\n                                      ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))\r\n#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \\\r\n                                                ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \\\r\n                                                ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \\\r\n                                                ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))\r\n#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \\\r\n                                              ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \\\r\n                                              ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))\r\n#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)\r\n#define IS_ETH_ZEROQUANTA_PAUSE(CMD)   (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \\\r\n                                        ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))\r\n#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \\\r\n                                               ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \\\r\n                                               ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \\\r\n                                               ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))\r\n#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \\\r\n                                                ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))\r\n#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \\\r\n                                         ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))\r\n#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \\\r\n                                          ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))\r\n#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \\\r\n                                                ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))\r\n#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)\r\n#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \\\r\n                                         ((ADDRESS) == ETH_MAC_ADDRESS1) || \\\r\n                                         ((ADDRESS) == ETH_MAC_ADDRESS2) || \\\r\n                                         ((ADDRESS) == ETH_MAC_ADDRESS3))\r\n#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \\\r\n                                        ((ADDRESS) == ETH_MAC_ADDRESS2) || \\\r\n                                        ((ADDRESS) == ETH_MAC_ADDRESS3))\r\n#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \\\r\n                                           ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))\r\n#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \\\r\n                                       ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \\\r\n                                       ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \\\r\n                                       ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \\\r\n                                       ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \\\r\n                                       ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))\r\n#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \\\r\n                                               ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))\r\n#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \\\r\n                                           ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))\r\n#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \\\r\n                                         ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))\r\n#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \\\r\n                                            ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))\r\n#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \\\r\n                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \\\r\n                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \\\r\n                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \\\r\n                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \\\r\n                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \\\r\n                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \\\r\n                                                      ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))\r\n#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \\\r\n                                          ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))\r\n#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \\\r\n                                                    ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))\r\n#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \\\r\n                                                     ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \\\r\n                                                     ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \\\r\n                                                     ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))\r\n#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \\\r\n                                          ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))\r\n#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \\\r\n                                           ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))\r\n#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \\\r\n                                 ((CMD) == ETH_FIXEDBURST_DISABLE))\r\n#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \\\r\n                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \\\r\n                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \\\r\n                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \\\r\n                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \\\r\n                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \\\r\n                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \\\r\n                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \\\r\n                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \\\r\n                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \\\r\n                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \\\r\n                                           ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))\r\n#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \\\r\n                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \\\r\n                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \\\r\n                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \\\r\n                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \\\r\n                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \\\r\n                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \\\r\n                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \\\r\n                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \\\r\n                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \\\r\n                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \\\r\n                                           ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))\r\n#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)\r\n#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \\\r\n                                                       ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \\\r\n                                                       ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \\\r\n                                                       ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \\\r\n                                                       ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))\r\n#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_IC) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_LS) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_FS) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_DC) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_DP) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_TTSE) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_TER) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_TCH) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_TTSS) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_IHE) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_ES) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_JT) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_FF) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_PCE) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_LCA) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_NC) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_LCO) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_EC) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_VF) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_CC) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_ED) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_UF) || \\\r\n                                         ((FLAG) == ETH_DMATXDESC_DB))\r\n#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \\\r\n                                            ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))\r\n#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \\\r\n                                              ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \\\r\n                                              ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \\\r\n                                              ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))\r\n#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)\r\n#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \\\r\n                                         ((FLAG) == ETH_DMARXDESC_AFM) || \\\r\n                                         ((FLAG) == ETH_DMARXDESC_ES) || \\\r\n                                         ((FLAG) == ETH_DMARXDESC_DE) || \\\r\n                                         ((FLAG) == ETH_DMARXDESC_SAF) || \\\r\n                                         ((FLAG) == ETH_DMARXDESC_LE) || \\\r\n                                         ((FLAG) == ETH_DMARXDESC_OE) || \\\r\n                                         ((FLAG) == ETH_DMARXDESC_VLAN) || \\\r\n                                         ((FLAG) == ETH_DMARXDESC_FS) || \\\r\n                                         ((FLAG) == ETH_DMARXDESC_LS) || \\\r\n                                         ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \\\r\n                                         ((FLAG) == ETH_DMARXDESC_LC) || \\\r\n                                         ((FLAG) == ETH_DMARXDESC_FT) || \\\r\n                                         ((FLAG) == ETH_DMARXDESC_RWT) || \\\r\n                                         ((FLAG) == ETH_DMARXDESC_RE) || \\\r\n                                         ((FLAG) == ETH_DMARXDESC_DBE) || \\\r\n                                         ((FLAG) == ETH_DMARXDESC_CE) || \\\r\n                                         ((FLAG) == ETH_DMARXDESC_MAMPCE))\r\n#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \\\r\n                                          ((BUFFER) == ETH_DMARXDESC_BUFFER2))\r\n#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \\\r\n                                   ((FLAG) == ETH_PMT_FLAG_MPR))\r\n#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00)) \r\n#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \\\r\n                                   ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \\\r\n                                   ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \\\r\n                                   ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \\\r\n                                   ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \\\r\n                                   ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \\\r\n                                   ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \\\r\n                                   ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \\\r\n                                   ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \\\r\n                                   ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \\\r\n                                   ((FLAG) == ETH_DMA_FLAG_T))\r\n#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF1) == 0x00) && ((IT) != 0x00))\r\n#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \\\r\n                               ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \\\r\n                               ((IT) == ETH_MAC_IT_PMT))\r\n#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \\\r\n                                   ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \\\r\n                                   ((FLAG) == ETH_MAC_FLAG_PMT))\r\n#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))\r\n#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \\\r\n                               ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \\\r\n                               ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \\\r\n                               ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \\\r\n                               ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \\\r\n                               ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \\\r\n                               ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \\\r\n                               ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \\\r\n                               ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))\r\n#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \\\r\n                                           ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))\r\n#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \\\r\n                           ((IT) != 0x00))\r\n#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \\\r\n                               ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \\\r\n                               ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))\r\n#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \\\r\n                                                ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup ETH_Private_Defines\r\n  * @{\r\n  */\r\n/* Delay to wait when writing to some Ethernet registers */\r\n#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001U)\r\n\r\n/* Ethernet Errors */\r\n#define  ETH_SUCCESS            ((uint32_t)0U)\r\n#define  ETH_ERROR              ((uint32_t)1U)\r\n\r\n/* Ethernet DMA Tx descriptors Collision Count Shift */\r\n#define  ETH_DMATXDESC_COLLISION_COUNTSHIFT         ((uint32_t)3U)\r\n\r\n/* Ethernet DMA Tx descriptors Buffer2 Size Shift */\r\n#define  ETH_DMATXDESC_BUFFER2_SIZESHIFT           ((uint32_t)16U)\r\n\r\n/* Ethernet DMA Rx descriptors Frame Length Shift */\r\n#define  ETH_DMARXDESC_FRAME_LENGTHSHIFT           ((uint32_t)16U)\r\n\r\n/* Ethernet DMA Rx descriptors Buffer2 Size Shift */\r\n#define  ETH_DMARXDESC_BUFFER2_SIZESHIFT           ((uint32_t)16U)\r\n\r\n/* Ethernet DMA Rx descriptors Frame length Shift */\r\n#define  ETH_DMARXDESC_FRAMELENGTHSHIFT            ((uint32_t)16)\r\n\r\n/* Ethernet MAC address offsets */\r\n#define ETH_MAC_ADDR_HBASE    (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40U)  /* Ethernet MAC address high offset */\r\n#define ETH_MAC_ADDR_LBASE    (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44U)  /* Ethernet MAC address low offset */\r\n\r\n/* Ethernet MACMIIAR register Mask */\r\n#define ETH_MACMIIAR_CR_MASK    ((uint32_t)0xFFFFFFE3U)\r\n\r\n/* Ethernet MACCR register Mask */\r\n#define ETH_MACCR_CLEAR_MASK    ((uint32_t)0xFF20810FU)  \r\n\r\n/* Ethernet MACFCR register Mask */\r\n#define ETH_MACFCR_CLEAR_MASK   ((uint32_t)0x0000FF41U)\r\n\r\n/* Ethernet DMAOMR register Mask */\r\n#define ETH_DMAOMR_CLEAR_MASK   ((uint32_t)0xF8DE3F23U)\r\n\r\n/* Ethernet Remote Wake-up frame register length */\r\n#define ETH_WAKEUP_REGISTER_LENGTH      8U\r\n\r\n/* Ethernet Missed frames counter Shift */\r\n#define  ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT     17U\r\n /**\r\n  * @}\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/ \r\n/** @defgroup ETH_Exported_Types ETH Exported Types\r\n  * @{\r\n  */\r\n\r\n/** \r\n  * @brief  HAL State structures definition  \r\n  */ \r\ntypedef enum\r\n{\r\n  HAL_ETH_STATE_RESET             = 0x00U,    /*!< Peripheral not yet Initialized or disabled         */\r\n  HAL_ETH_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use           */\r\n  HAL_ETH_STATE_BUSY              = 0x02U,    /*!< an internal process is ongoing                     */\r\n  HAL_ETH_STATE_BUSY_TX           = 0x12U,    /*!< Data Transmission process is ongoing               */\r\n  HAL_ETH_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing                  */\r\n  HAL_ETH_STATE_BUSY_TX_RX        = 0x32U,    /*!< Data Transmission and Reception process is ongoing */\r\n  HAL_ETH_STATE_BUSY_WR           = 0x42U,    /*!< Write process is ongoing                           */\r\n  HAL_ETH_STATE_BUSY_RD           = 0x82U,    /*!< Read process is ongoing                            */\r\n  HAL_ETH_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                                      */\r\n  HAL_ETH_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                       */\r\n}HAL_ETH_StateTypeDef;\r\n\r\n/** \r\n  * @brief  ETH Init Structure definition  \r\n  */\r\n\r\ntypedef struct\r\n{\r\n  uint32_t             AutoNegotiation;           /*!< Selects or not the AutoNegotiation mode for the external PHY\r\n                                                           The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)\r\n                                                           and the mode (half/full-duplex).\r\n                                                           This parameter can be a value of @ref ETH_AutoNegotiation */\r\n\r\n  uint32_t             Speed;                     /*!< Sets the Ethernet speed: 10/100 Mbps.\r\n                                                           This parameter can be a value of @ref ETH_Speed */\r\n\r\n  uint32_t             DuplexMode;                /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode\r\n                                                           This parameter can be a value of @ref ETH_Duplex_Mode */\r\n  \r\n  uint16_t             PhyAddress;                /*!< Ethernet PHY address.\r\n                                                           This parameter must be a number between Min_Data = 0 and Max_Data = 32 */\r\n  \r\n  uint8_t             *MACAddr;                   /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */\r\n  \r\n  uint32_t             RxMode;                    /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.\r\n                                                           This parameter can be a value of @ref ETH_Rx_Mode */\r\n  \r\n  uint32_t             ChecksumMode;              /*!< Selects if the checksum is check by hardware or by software. \r\n                                                         This parameter can be a value of @ref ETH_Checksum_Mode */\r\n  \r\n  uint32_t             MediaInterface    ;               /*!< Selects the media-independent interface or the reduced media-independent interface. \r\n                                                         This parameter can be a value of @ref ETH_Media_Interface */\r\n\r\n} ETH_InitTypeDef;\r\n\r\n\r\n /** \r\n  * @brief  ETH MAC Configuration Structure definition  \r\n  */\r\n\r\ntypedef struct\r\n{\r\n  uint32_t             Watchdog;                  /*!< Selects or not the Watchdog timer\r\n                                                           When enabled, the MAC allows no more then 2048 bytes to be received.\r\n                                                           When disabled, the MAC can receive up to 16384 bytes.\r\n                                                           This parameter can be a value of @ref ETH_Watchdog */  \r\n\r\n  uint32_t             Jabber;                    /*!< Selects or not Jabber timer\r\n                                                           When enabled, the MAC allows no more then 2048 bytes to be sent.\r\n                                                           When disabled, the MAC can send up to 16384 bytes.\r\n                                                           This parameter can be a value of @ref ETH_Jabber */\r\n\r\n  uint32_t             InterFrameGap;             /*!< Selects the minimum IFG between frames during transmission.\r\n                                                           This parameter can be a value of @ref ETH_Inter_Frame_Gap */   \r\n\r\n  uint32_t             CarrierSense;              /*!< Selects or not the Carrier Sense.\r\n                                                           This parameter can be a value of @ref ETH_Carrier_Sense */\r\n\r\n  uint32_t             ReceiveOwn;                /*!< Selects or not the ReceiveOwn,\r\n                                                           ReceiveOwn allows the reception of frames when the TX_EN signal is asserted\r\n                                                           in Half-Duplex mode.\r\n                                                           This parameter can be a value of @ref ETH_Receive_Own */  \r\n\r\n  uint32_t             LoopbackMode;              /*!< Selects or not the internal MAC MII Loopback mode.\r\n                                                           This parameter can be a value of @ref ETH_Loop_Back_Mode */  \r\n\r\n  uint32_t             ChecksumOffload;           /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.\r\n                                                           This parameter can be a value of @ref ETH_Checksum_Offload */    \r\n\r\n  uint32_t             RetryTransmission;         /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,\r\n                                                           when a collision occurs (Half-Duplex mode).\r\n                                                           This parameter can be a value of @ref ETH_Retry_Transmission */\r\n\r\n  uint32_t             AutomaticPadCRCStrip;      /*!< Selects or not the Automatic MAC Pad/CRC Stripping.\r\n                                                           This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ \r\n\r\n  uint32_t             BackOffLimit;              /*!< Selects the BackOff limit value.\r\n                                                           This parameter can be a value of @ref ETH_Back_Off_Limit */\r\n\r\n  uint32_t             DeferralCheck;             /*!< Selects or not the deferral check function (Half-Duplex mode).\r\n                                                           This parameter can be a value of @ref ETH_Deferral_Check */                                                                                                        \r\n\r\n  uint32_t             ReceiveAll;                /*!< Selects or not all frames reception by the MAC (No filtering).\r\n                                                           This parameter can be a value of @ref ETH_Receive_All */   \r\n\r\n  uint32_t             SourceAddrFilter;          /*!< Selects the Source Address Filter mode.                                                           \r\n                                                           This parameter can be a value of @ref ETH_Source_Addr_Filter */                  \r\n\r\n  uint32_t             PassControlFrames;         /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)                                                          \r\n                                                           This parameter can be a value of @ref ETH_Pass_Control_Frames */ \r\n\r\n  uint32_t             BroadcastFramesReception;  /*!< Selects or not the reception of Broadcast Frames.\r\n                                                           This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */\r\n\r\n  uint32_t             DestinationAddrFilter;     /*!< Sets the destination filter mode for both unicast and multicast frames.\r\n                                                           This parameter can be a value of @ref ETH_Destination_Addr_Filter */ \r\n\r\n  uint32_t             PromiscuousMode;           /*!< Selects or not the Promiscuous Mode\r\n                                                           This parameter can be a value of @ref ETH_Promiscuous_Mode */\r\n\r\n  uint32_t             MulticastFramesFilter;     /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.\r\n                                                           This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ \r\n\r\n  uint32_t             UnicastFramesFilter;       /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.\r\n                                                           This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ \r\n\r\n  uint32_t             HashTableHigh;             /*!< This field holds the higher 32 bits of Hash table.\r\n                                                           This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */\r\n\r\n  uint32_t             HashTableLow;              /*!< This field holds the lower 32 bits of Hash table.\r\n                                                           This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF  */    \r\n\r\n  uint32_t             PauseTime;                 /*!< This field holds the value to be used in the Pause Time field in the transmit control frame. \r\n                                                           This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */\r\n\r\n  uint32_t             ZeroQuantaPause;           /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.\r\n                                                           This parameter can be a value of @ref ETH_Zero_Quanta_Pause */  \r\n\r\n  uint32_t             PauseLowThreshold;         /*!< This field configures the threshold of the PAUSE to be checked for\r\n                                                           automatic retransmission of PAUSE Frame.\r\n                                                           This parameter can be a value of @ref ETH_Pause_Low_Threshold */\r\n                                                           \r\n  uint32_t             UnicastPauseFrameDetect;   /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0\r\n                                                           unicast address and unique multicast address).\r\n                                                           This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */  \r\n\r\n  uint32_t             ReceiveFlowControl;        /*!< Enables or disables the MAC to decode the received Pause frame and\r\n                                                           disable its transmitter for a specified time (Pause Time)\r\n                                                           This parameter can be a value of @ref ETH_Receive_Flow_Control */\r\n\r\n  uint32_t             TransmitFlowControl;       /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)\r\n                                                           or the MAC back-pressure operation (Half-Duplex mode)\r\n                                                           This parameter can be a value of @ref ETH_Transmit_Flow_Control */     \r\n\r\n  uint32_t             VLANTagComparison;         /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for\r\n                                                           comparison and filtering.\r\n                                                           This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ \r\n\r\n  uint32_t             VLANTagIdentifier;         /*!< Holds the VLAN tag identifier for receive frames */\r\n\r\n} ETH_MACInitTypeDef;\r\n\r\n\r\n/** \r\n  * @brief  ETH DMA Configuration Structure definition  \r\n  */\r\n\r\ntypedef struct\r\n{\r\n uint32_t              DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.\r\n                                                             This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ \r\n\r\n  uint32_t             ReceiveStoreForward;         /*!< Enables or disables the Receive store and forward mode.\r\n                                                             This parameter can be a value of @ref ETH_Receive_Store_Forward */ \r\n\r\n  uint32_t             FlushReceivedFrame;          /*!< Enables or disables the flushing of received frames.\r\n                                                             This parameter can be a value of @ref ETH_Flush_Received_Frame */ \r\n\r\n  uint32_t             TransmitStoreForward;        /*!< Enables or disables Transmit store and forward mode.\r\n                                                             This parameter can be a value of @ref ETH_Transmit_Store_Forward */ \r\n\r\n  uint32_t             TransmitThresholdControl;    /*!< Selects or not the Transmit Threshold Control.\r\n                                                             This parameter can be a value of @ref ETH_Transmit_Threshold_Control */\r\n\r\n  uint32_t             ForwardErrorFrames;          /*!< Selects or not the forward to the DMA of erroneous frames.\r\n                                                             This parameter can be a value of @ref ETH_Forward_Error_Frames */\r\n\r\n  uint32_t             ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error\r\n                                                             and length less than 64 bytes) including pad-bytes and CRC)\r\n                                                             This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */\r\n\r\n  uint32_t             ReceiveThresholdControl;     /*!< Selects the threshold level of the Receive FIFO.\r\n                                                             This parameter can be a value of @ref ETH_Receive_Threshold_Control */\r\n\r\n  uint32_t             SecondFrameOperate;          /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second\r\n                                                             frame of Transmit data even before obtaining the status for the first frame.\r\n                                                             This parameter can be a value of @ref ETH_Second_Frame_Operate */\r\n\r\n  uint32_t             AddressAlignedBeats;         /*!< Enables or disables the Address Aligned Beats.\r\n                                                             This parameter can be a value of @ref ETH_Address_Aligned_Beats */\r\n\r\n  uint32_t             FixedBurst;                  /*!< Enables or disables the AHB Master interface fixed burst transfers.\r\n                                                             This parameter can be a value of @ref ETH_Fixed_Burst */\r\n                       \r\n  uint32_t             RxDMABurstLength;            /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.\r\n                                                             This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ \r\n\r\n  uint32_t             TxDMABurstLength;            /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.\r\n                                                             This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */\r\n  \r\n  uint32_t             EnhancedDescriptorFormat;    /*!< Enables the enhanced descriptor format.\r\n                                                             This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */\r\n\r\n  uint32_t             DescriptorSkipLength;        /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)\r\n                                                             This parameter must be a number between Min_Data = 0 and Max_Data = 32 */                                                             \r\n\r\n  uint32_t             DMAArbitration;              /*!< Selects the DMA Tx/Rx arbitration.\r\n                                                             This parameter can be a value of @ref ETH_DMA_Arbitration */  \r\n} ETH_DMAInitTypeDef;\r\n\r\n\r\n/** \r\n  * @brief  ETH DMA Descriptors data structure definition\r\n  */ \r\n\r\ntypedef struct  \r\n{\r\n  __IO uint32_t   Status;           /*!< Status */\r\n  \r\n  uint32_t   ControlBufferSize;     /*!< Control and Buffer1, Buffer2 lengths */\r\n  \r\n  uint32_t   Buffer1Addr;           /*!< Buffer1 address pointer */\r\n  \r\n  uint32_t   Buffer2NextDescAddr;   /*!< Buffer2 or next descriptor address pointer */\r\n  \r\n  /*!< Enhanced Ethernet DMA PTP Descriptors */\r\n  uint32_t   ExtendedStatus;        /*!< Extended status for PTP receive descriptor */\r\n  \r\n  uint32_t   Reserved1;             /*!< Reserved */\r\n  \r\n  uint32_t   TimeStampLow;          /*!< Time Stamp Low value for transmit and receive */\r\n  \r\n  uint32_t   TimeStampHigh;         /*!< Time Stamp High value for transmit and receive */\r\n\r\n} ETH_DMADescTypeDef;\r\n\r\n\r\n/** \r\n  * @brief  Received Frame Informations structure definition\r\n  */ \r\ntypedef struct  \r\n{\r\n  ETH_DMADescTypeDef *FSRxDesc;          /*!< First Segment Rx Desc */\r\n  \r\n  ETH_DMADescTypeDef *LSRxDesc;          /*!< Last Segment Rx Desc */\r\n  \r\n  uint32_t  SegCount;                    /*!< Segment count */\r\n  \r\n  uint32_t length;                       /*!< Frame length */\r\n  \r\n  uint32_t buffer;                       /*!< Frame buffer */\r\n\r\n} ETH_DMARxFrameInfos;\r\n\r\n\r\n/** \r\n  * @brief  ETH Handle Structure definition  \r\n  */\r\n  \r\ntypedef struct\r\n{\r\n  ETH_TypeDef                *Instance;     /*!< Register base address       */\r\n  \r\n  ETH_InitTypeDef            Init;          /*!< Ethernet Init Configuration */\r\n  \r\n  uint32_t                   LinkStatus;    /*!< Ethernet link status        */\r\n  \r\n  ETH_DMADescTypeDef         *RxDesc;       /*!< Rx descriptor to Get        */\r\n  \r\n  ETH_DMADescTypeDef         *TxDesc;       /*!< Tx descriptor to Set        */\r\n  \r\n  ETH_DMARxFrameInfos        RxFrameInfos;  /*!< last Rx frame infos         */\r\n  \r\n  __IO HAL_ETH_StateTypeDef  State;         /*!< ETH communication state     */\r\n  \r\n  HAL_LockTypeDef            Lock;          /*!< ETH Lock                    */\r\n\r\n} ETH_HandleTypeDef;\r\n\r\n /**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup ETH_Exported_Constants ETH Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup ETH_Buffers_setting ETH Buffers setting\r\n  * @{\r\n  */ \r\n#define ETH_MAX_PACKET_SIZE    ((uint32_t)1524U)    /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */\r\n#define ETH_HEADER               ((uint32_t)14U)    /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */\r\n#define ETH_CRC                   ((uint32_t)4U)    /*!< Ethernet CRC */\r\n#define ETH_EXTRA                 ((uint32_t)2U)    /*!< Extra bytes in some cases */   \r\n#define ETH_VLAN_TAG              ((uint32_t)4U)    /*!< optional 802.1q VLAN Tag */\r\n#define ETH_MIN_ETH_PAYLOAD       ((uint32_t)46U)    /*!< Minimum Ethernet payload size */\r\n#define ETH_MAX_ETH_PAYLOAD       ((uint32_t)1500U)    /*!< Maximum Ethernet payload size */\r\n#define ETH_JUMBO_FRAME_PAYLOAD   ((uint32_t)9000U)    /*!< Jumbo frame payload size */      \r\n\r\n /* Ethernet driver receive buffers are organized in a chained linked-list, when\r\n    an Ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO\r\n    to the driver receive buffers memory.\r\n\r\n    Depending on the size of the received Ethernet packet and the size of \r\n    each Ethernet driver receive buffer, the received packet can take one or more\r\n    Ethernet driver receive buffer. \r\n\r\n    In below are defined the size of one Ethernet driver receive buffer ETH_RX_BUF_SIZE \r\n    and the total count of the driver receive buffers ETH_RXBUFNB.\r\n\r\n    The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as \r\n    example, they can be reconfigured in the application layer to fit the application \r\n    needs */ \r\n\r\n/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet\r\n   packet */\r\n#ifndef ETH_RX_BUF_SIZE\r\n #define ETH_RX_BUF_SIZE         ETH_MAX_PACKET_SIZE \r\n#endif\r\n\r\n/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/ \r\n#ifndef ETH_RXBUFNB\r\n #define ETH_RXBUFNB             ((uint32_t)5U     /*  5 Rx buffers of size ETH_RX_BUF_SIZE */\r\n#endif\r\n\r\n\r\n /* Ethernet driver transmit buffers are organized in a chained linked-list, when\r\n    an Ethernet packet is transmitted, Tx-DMA will transfer the packet from the \r\n    driver transmit buffers memory to the TxFIFO.\r\n\r\n    Depending on the size of the Ethernet packet to be transmitted and the size of \r\n    each Ethernet driver transmit buffer, the packet to be transmitted can take \r\n    one or more Ethernet driver transmit buffer. \r\n\r\n    In below are defined the size of one Ethernet driver transmit buffer ETH_TX_BUF_SIZE \r\n    and the total count of the driver transmit buffers ETH_TXBUFNB.\r\n\r\n    The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as \r\n    example, they can be reconfigured in the application layer to fit the application \r\n    needs */ \r\n\r\n/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet\r\n   packet */\r\n#ifndef ETH_TX_BUF_SIZE \r\n #define ETH_TX_BUF_SIZE         ETH_MAX_PACKET_SIZE\r\n#endif\r\n\r\n/* 5 Ethernet driver transmit buffers are used (in a chained linked list)*/ \r\n#ifndef ETH_TXBUFNB\r\n #define ETH_TXBUFNB             ((uint32_t)5U      /* 5  Tx buffers of size ETH_TX_BUF_SIZE */\r\n#endif\r\n\r\n /**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor\r\n  * @{\r\n  */\r\n\r\n/*\r\n   DMA Tx Descriptor\r\n  -----------------------------------------------------------------------------------------------\r\n  TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |\r\n  -----------------------------------------------------------------------------------------------\r\n  TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |\r\n  -----------------------------------------------------------------------------------------------\r\n  TDES2 |                         Buffer1 Address [31:0]                                         |\r\n  -----------------------------------------------------------------------------------------------\r\n  TDES3 |                   Buffer2 Address [31:0] / Next Descriptor Address [31:0]              |\r\n  -----------------------------------------------------------------------------------------------\r\n*/\r\n\r\n/** \r\n  * @brief  Bit definition of TDES0 register: DMA Tx descriptor status register\r\n  */ \r\n#define ETH_DMATXDESC_OWN                     ((uint32_t)0x80000000U)  /*!< OWN bit: descriptor is owned by DMA engine */\r\n#define ETH_DMATXDESC_IC                      ((uint32_t)0x40000000U)  /*!< Interrupt on Completion */\r\n#define ETH_DMATXDESC_LS                      ((uint32_t)0x20000000U)  /*!< Last Segment */\r\n#define ETH_DMATXDESC_FS                      ((uint32_t)0x10000000U)  /*!< First Segment */\r\n#define ETH_DMATXDESC_DC                      ((uint32_t)0x08000000U)  /*!< Disable CRC */\r\n#define ETH_DMATXDESC_DP                      ((uint32_t)0x04000000U)  /*!< Disable Padding */\r\n#define ETH_DMATXDESC_TTSE                    ((uint32_t)0x02000000U)  /*!< Transmit Time Stamp Enable */\r\n#define ETH_DMATXDESC_CIC                     ((uint32_t)0x00C00000U)  /*!< Checksum Insertion Control: 4 cases */\r\n#define ETH_DMATXDESC_CIC_BYPASS              ((uint32_t)0x00000000U)  /*!< Do Nothing: Checksum Engine is bypassed */ \r\n#define ETH_DMATXDESC_CIC_IPV4HEADER          ((uint32_t)0x00400000U)  /*!< IPV4 header Checksum Insertion */ \r\n#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT  ((uint32_t)0x00800000U)  /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ \r\n#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL     ((uint32_t)0x00C00000U)  /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ \r\n#define ETH_DMATXDESC_TER                     ((uint32_t)0x00200000U)  /*!< Transmit End of Ring */\r\n#define ETH_DMATXDESC_TCH                     ((uint32_t)0x00100000U)  /*!< Second Address Chained */\r\n#define ETH_DMATXDESC_TTSS                    ((uint32_t)0x00020000U)  /*!< Tx Time Stamp Status */\r\n#define ETH_DMATXDESC_IHE                     ((uint32_t)0x00010000U)  /*!< IP Header Error */\r\n#define ETH_DMATXDESC_ES                      ((uint32_t)0x00008000U)  /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */\r\n#define ETH_DMATXDESC_JT                      ((uint32_t)0x00004000U)  /*!< Jabber Timeout */\r\n#define ETH_DMATXDESC_FF                      ((uint32_t)0x00002000U)  /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */\r\n#define ETH_DMATXDESC_PCE                     ((uint32_t)0x00001000U)  /*!< Payload Checksum Error */\r\n#define ETH_DMATXDESC_LCA                     ((uint32_t)0x00000800U)  /*!< Loss of Carrier: carrier lost during transmission */\r\n#define ETH_DMATXDESC_NC                      ((uint32_t)0x00000400U)  /*!< No Carrier: no carrier signal from the transceiver */\r\n#define ETH_DMATXDESC_LCO                     ((uint32_t)0x00000200U)  /*!< Late Collision: transmission aborted due to collision */\r\n#define ETH_DMATXDESC_EC                      ((uint32_t)0x00000100U)  /*!< Excessive Collision: transmission aborted after 16 collisions */\r\n#define ETH_DMATXDESC_VF                      ((uint32_t)0x00000080U)  /*!< VLAN Frame */\r\n#define ETH_DMATXDESC_CC                      ((uint32_t)0x00000078U)  /*!< Collision Count */\r\n#define ETH_DMATXDESC_ED                      ((uint32_t)0x00000004U)  /*!< Excessive Deferral */\r\n#define ETH_DMATXDESC_UF                      ((uint32_t)0x00000002U)  /*!< Underflow Error: late data arrival from the memory */\r\n#define ETH_DMATXDESC_DB                      ((uint32_t)0x00000001U)  /*!< Deferred Bit */\r\n\r\n/** \r\n  * @brief  Bit definition of TDES1 register\r\n  */ \r\n#define ETH_DMATXDESC_TBS2  ((uint32_t)0x1FFF0000U)  /*!< Transmit Buffer2 Size */\r\n#define ETH_DMATXDESC_TBS1  ((uint32_t)0x00001FFFU)  /*!< Transmit Buffer1 Size */\r\n\r\n/** \r\n  * @brief  Bit definition of TDES2 register\r\n  */ \r\n#define ETH_DMATXDESC_B1AP  ((uint32_t)0xFFFFFFFFU)  /*!< Buffer1 Address Pointer */\r\n\r\n/** \r\n  * @brief  Bit definition of TDES3 register\r\n  */ \r\n#define ETH_DMATXDESC_B2AP  ((uint32_t)0xFFFFFFFFU)  /*!< Buffer2 Address Pointer */\r\n\r\n  /*---------------------------------------------------------------------------------------------\r\n  TDES6 |                         Transmit Time Stamp Low [31:0]                                 |\r\n  -----------------------------------------------------------------------------------------------\r\n  TDES7 |                         Transmit Time Stamp High [31:0]                                |\r\n  ----------------------------------------------------------------------------------------------*/\r\n\r\n/* Bit definition of TDES6 register */\r\n #define ETH_DMAPTPTXDESC_TTSL  ((uint32_t)0xFFFFFFFFU)  /* Transmit Time Stamp Low */\r\n\r\n/* Bit definition of TDES7 register */\r\n #define ETH_DMAPTPTXDESC_TTSH  ((uint32_t)0xFFFFFFFFU)  /* Transmit Time Stamp High */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor\r\n  * @{\r\n  */\r\n\r\n/*\r\n  DMA Rx Descriptor\r\n  --------------------------------------------------------------------------------------------------------------------\r\n  RDES0 | OWN(31) |                                             Status [30:0]                                          |\r\n  ---------------------------------------------------------------------------------------------------------------------\r\n  RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |\r\n  ---------------------------------------------------------------------------------------------------------------------\r\n  RDES2 |                                       Buffer1 Address [31:0]                                                 |\r\n  ---------------------------------------------------------------------------------------------------------------------\r\n  RDES3 |                          Buffer2 Address [31:0] / Next Descriptor Address [31:0]                             |\r\n  ---------------------------------------------------------------------------------------------------------------------\r\n*/\r\n\r\n/** \r\n  * @brief  Bit definition of RDES0 register: DMA Rx descriptor status register\r\n  */ \r\n#define ETH_DMARXDESC_OWN         ((uint32_t)0x80000000U)  /*!< OWN bit: descriptor is owned by DMA engine  */\r\n#define ETH_DMARXDESC_AFM         ((uint32_t)0x40000000U)  /*!< DA Filter Fail for the rx frame  */\r\n#define ETH_DMARXDESC_FL          ((uint32_t)0x3FFF0000U)  /*!< Receive descriptor frame length  */\r\n#define ETH_DMARXDESC_ES          ((uint32_t)0x00008000U)  /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */\r\n#define ETH_DMARXDESC_DE          ((uint32_t)0x00004000U)  /*!< Descriptor error: no more descriptors for receive frame  */\r\n#define ETH_DMARXDESC_SAF         ((uint32_t)0x00002000U)  /*!< SA Filter Fail for the received frame */\r\n#define ETH_DMARXDESC_LE          ((uint32_t)0x00001000U)  /*!< Frame size not matching with length field */\r\n#define ETH_DMARXDESC_OE          ((uint32_t)0x00000800U)  /*!< Overflow Error: Frame was damaged due to buffer overflow */\r\n#define ETH_DMARXDESC_VLAN        ((uint32_t)0x00000400U)  /*!< VLAN Tag: received frame is a VLAN frame */\r\n#define ETH_DMARXDESC_FS          ((uint32_t)0x00000200U)  /*!< First descriptor of the frame  */\r\n#define ETH_DMARXDESC_LS          ((uint32_t)0x00000100U)  /*!< Last descriptor of the frame  */ \r\n#define ETH_DMARXDESC_IPV4HCE     ((uint32_t)0x00000080U)  /*!< IPC Checksum Error: Rx Ipv4 header checksum error   */    \r\n#define ETH_DMARXDESC_LC          ((uint32_t)0x00000040U)  /*!< Late collision occurred during reception   */\r\n#define ETH_DMARXDESC_FT          ((uint32_t)0x00000020U)  /*!< Frame type - Ethernet, otherwise 802.3    */\r\n#define ETH_DMARXDESC_RWT         ((uint32_t)0x00000010U)  /*!< Receive Watchdog Timeout: watchdog timer expired during reception    */\r\n#define ETH_DMARXDESC_RE          ((uint32_t)0x00000008U)  /*!< Receive error: error reported by MII interface  */\r\n#define ETH_DMARXDESC_DBE         ((uint32_t)0x00000004U)  /*!< Dribble bit error: frame contains non int multiple of 8 bits  */\r\n#define ETH_DMARXDESC_CE          ((uint32_t)0x00000002U)  /*!< CRC error */\r\n#define ETH_DMARXDESC_MAMPCE      ((uint32_t)0x00000001U)  /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */\r\n\r\n/** \r\n  * @brief  Bit definition of RDES1 register\r\n  */ \r\n#define ETH_DMARXDESC_DIC   ((uint32_t)0x80000000U)  /*!< Disable Interrupt on Completion */\r\n#define ETH_DMARXDESC_RBS2  ((uint32_t)0x1FFF0000U)  /*!< Receive Buffer2 Size */\r\n#define ETH_DMARXDESC_RER   ((uint32_t)0x00008000U)  /*!< Receive End of Ring */\r\n#define ETH_DMARXDESC_RCH   ((uint32_t)0x00004000U)  /*!< Second Address Chained */\r\n#define ETH_DMARXDESC_RBS1  ((uint32_t)0x00001FFFU)  /*!< Receive Buffer1 Size */\r\n\r\n/** \r\n  * @brief  Bit definition of RDES2 register  \r\n  */ \r\n#define ETH_DMARXDESC_B1AP  ((uint32_t)0xFFFFFFFFU)  /*!< Buffer1 Address Pointer */\r\n\r\n/** \r\n  * @brief  Bit definition of RDES3 register  \r\n  */ \r\n#define ETH_DMARXDESC_B2AP  ((uint32_t)0xFFFFFFFFU)  /*!< Buffer2 Address Pointer */\r\n\r\n/*---------------------------------------------------------------------------------------------------------------------\r\n  RDES4 |                   Reserved[31:15]              |             Extended Status [14:0]                          |\r\n  ---------------------------------------------------------------------------------------------------------------------\r\n  RDES5 |                                            Reserved[31:0]                                                    |\r\n  ---------------------------------------------------------------------------------------------------------------------\r\n  RDES6 |                                       Receive Time Stamp Low [31:0]                                          |\r\n  ---------------------------------------------------------------------------------------------------------------------\r\n  RDES7 |                                       Receive Time Stamp High [31:0]                                         |\r\n  --------------------------------------------------------------------------------------------------------------------*/\r\n\r\n/* Bit definition of RDES4 register */\r\n#define ETH_DMAPTPRXDESC_PTPV                            ((uint32_t)0x00002000U)  /* PTP Version */\r\n#define ETH_DMAPTPRXDESC_PTPFT                           ((uint32_t)0x00001000U)  /* PTP Frame Type */\r\n#define ETH_DMAPTPRXDESC_PTPMT                           ((uint32_t)0x00000F00U)  /* PTP Message Type */\r\n#define ETH_DMAPTPRXDESC_PTPMT_SYNC                      ((uint32_t)0x00000100U)  /* SYNC message (all clock types) */\r\n#define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP                  ((uint32_t)0x00000200U)  /* FollowUp message (all clock types) */ \r\n#define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ                  ((uint32_t)0x00000300U)  /* DelayReq message (all clock types) */ \r\n#define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP                 ((uint32_t)0x00000400U)  /* DelayResp message (all clock types) */ \r\n#define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE        ((uint32_t)0x00000500U)  /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */ \r\n#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG          ((uint32_t)0x00000600U)  /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock)  */ \r\n#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700U)  /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */           \r\n#define ETH_DMAPTPRXDESC_IPV6PR                          ((uint32_t)0x00000080U)  /* IPv6 Packet Received */\r\n#define ETH_DMAPTPRXDESC_IPV4PR                          ((uint32_t)0x00000040U)  /* IPv4 Packet Received */\r\n#define ETH_DMAPTPRXDESC_IPCB                            ((uint32_t)0x00000020U)  /* IP Checksum Bypassed */\r\n#define ETH_DMAPTPRXDESC_IPPE                            ((uint32_t)0x00000010U)  /* IP Payload Error */\r\n#define ETH_DMAPTPRXDESC_IPHE                            ((uint32_t)0x00000008U)  /* IP Header Error */\r\n#define ETH_DMAPTPRXDESC_IPPT                            ((uint32_t)0x00000007U)  /* IP Payload Type */\r\n#define ETH_DMAPTPRXDESC_IPPT_UDP                        ((uint32_t)0x00000001U)  /* UDP payload encapsulated in the IP datagram */\r\n#define ETH_DMAPTPRXDESC_IPPT_TCP                        ((uint32_t)0x00000002U)  /* TCP payload encapsulated in the IP datagram */ \r\n#define ETH_DMAPTPRXDESC_IPPT_ICMP                       ((uint32_t)0x00000003U)  /* ICMP payload encapsulated in the IP datagram */\r\n\r\n/* Bit definition of RDES6 register */\r\n#define ETH_DMAPTPRXDESC_RTSL  ((uint32_t)0xFFFFFFFFU)  /* Receive Time Stamp Low */\r\n\r\n/* Bit definition of RDES7 register */\r\n#define ETH_DMAPTPRXDESC_RTSH  ((uint32_t)0xFFFFFFFFU)  /* Receive Time Stamp High */\r\n/**\r\n  * @}\r\n  */\r\n /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation \r\n  * @{\r\n  */ \r\n#define ETH_AUTONEGOTIATION_ENABLE     ((uint32_t)0x00000001U)\r\n#define ETH_AUTONEGOTIATION_DISABLE    ((uint32_t)0x00000000U)\r\n\r\n/**\r\n  * @}\r\n  */\r\n/** @defgroup ETH_Speed ETH Speed \r\n  * @{\r\n  */ \r\n#define ETH_SPEED_10M        ((uint32_t)0x00000000U)\r\n#define ETH_SPEED_100M       ((uint32_t)0x00004000U)\r\n\r\n/**\r\n  * @}\r\n  */\r\n/** @defgroup ETH_Duplex_Mode ETH Duplex Mode\r\n  * @{\r\n  */ \r\n#define ETH_MODE_FULLDUPLEX       ((uint32_t)0x00000800U)\r\n#define ETH_MODE_HALFDUPLEX       ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n/** @defgroup ETH_Rx_Mode ETH Rx Mode\r\n  * @{\r\n  */ \r\n#define ETH_RXPOLLING_MODE      ((uint32_t)0x00000000U)\r\n#define ETH_RXINTERRUPT_MODE    ((uint32_t)0x00000001U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Checksum_Mode ETH Checksum Mode\r\n  * @{\r\n  */ \r\n#define ETH_CHECKSUM_BY_HARDWARE      ((uint32_t)0x00000000U)\r\n#define ETH_CHECKSUM_BY_SOFTWARE      ((uint32_t)0x00000001U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Media_Interface ETH Media Interface\r\n  * @{\r\n  */ \r\n#define ETH_MEDIA_INTERFACE_MII       ((uint32_t)0x00000000U)\r\n#define ETH_MEDIA_INTERFACE_RMII      ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Watchdog ETH Watchdog \r\n  * @{\r\n  */ \r\n#define ETH_WATCHDOG_ENABLE       ((uint32_t)0x00000000U)\r\n#define ETH_WATCHDOG_DISABLE      ((uint32_t)0x00800000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Jabber ETH Jabber\r\n  * @{\r\n  */ \r\n#define ETH_JABBER_ENABLE    ((uint32_t)0x00000000U)\r\n#define ETH_JABBER_DISABLE   ((uint32_t)0x00400000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap \r\n  * @{\r\n  */ \r\n#define ETH_INTERFRAMEGAP_96BIT   ((uint32_t)0x00000000U)  /*!< minimum IFG between frames during transmission is 96Bit */\r\n#define ETH_INTERFRAMEGAP_88BIT   ((uint32_t)0x00020000U)  /*!< minimum IFG between frames during transmission is 88Bit */\r\n#define ETH_INTERFRAMEGAP_80BIT   ((uint32_t)0x00040000U)  /*!< minimum IFG between frames during transmission is 80Bit */\r\n#define ETH_INTERFRAMEGAP_72BIT   ((uint32_t)0x00060000U)  /*!< minimum IFG between frames during transmission is 72Bit */\r\n#define ETH_INTERFRAMEGAP_64BIT   ((uint32_t)0x00080000U)  /*!< minimum IFG between frames during transmission is 64Bit */\r\n#define ETH_INTERFRAMEGAP_56BIT   ((uint32_t)0x000A0000U)  /*!< minimum IFG between frames during transmission is 56Bit */\r\n#define ETH_INTERFRAMEGAP_48BIT   ((uint32_t)0x000C0000U)  /*!< minimum IFG between frames during transmission is 48Bit */\r\n#define ETH_INTERFRAMEGAP_40BIT   ((uint32_t)0x000E0000U)  /*!< minimum IFG between frames during transmission is 40Bit */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Carrier_Sense ETH Carrier Sense\r\n  * @{\r\n  */ \r\n#define ETH_CARRIERSENCE_ENABLE   ((uint32_t)0x00000000U)\r\n#define ETH_CARRIERSENCE_DISABLE  ((uint32_t)0x00010000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Receive_Own ETH Receive Own \r\n  * @{\r\n  */ \r\n#define ETH_RECEIVEOWN_ENABLE     ((uint32_t)0x00000000U)\r\n#define ETH_RECEIVEOWN_DISABLE    ((uint32_t)0x00002000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode \r\n  * @{\r\n  */ \r\n#define ETH_LOOPBACKMODE_ENABLE        ((uint32_t)0x00001000U)\r\n#define ETH_LOOPBACKMODE_DISABLE       ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Checksum_Offload ETH Checksum Offload\r\n  * @{\r\n  */ \r\n#define ETH_CHECKSUMOFFLAOD_ENABLE     ((uint32_t)0x00000400U)\r\n#define ETH_CHECKSUMOFFLAOD_DISABLE    ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Retry_Transmission ETH Retry Transmission\r\n  * @{\r\n  */ \r\n#define ETH_RETRYTRANSMISSION_ENABLE   ((uint32_t)0x00000000U)\r\n#define ETH_RETRYTRANSMISSION_DISABLE  ((uint32_t)0x00000200U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip\r\n  * @{\r\n  */ \r\n#define ETH_AUTOMATICPADCRCSTRIP_ENABLE     ((uint32_t)0x00000080U)\r\n#define ETH_AUTOMATICPADCRCSTRIP_DISABLE    ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit\r\n  * @{\r\n  */ \r\n#define ETH_BACKOFFLIMIT_10  ((uint32_t)0x00000000U)\r\n#define ETH_BACKOFFLIMIT_8   ((uint32_t)0x00000020U)\r\n#define ETH_BACKOFFLIMIT_4   ((uint32_t)0x00000040U)\r\n#define ETH_BACKOFFLIMIT_1   ((uint32_t)0x00000060U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Deferral_Check ETH Deferral Check\r\n  * @{\r\n  */\r\n#define ETH_DEFFERRALCHECK_ENABLE       ((uint32_t)0x00000010U)\r\n#define ETH_DEFFERRALCHECK_DISABLE      ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Receive_All ETH Receive All\r\n  * @{\r\n  */ \r\n#define ETH_RECEIVEALL_ENABLE     ((uint32_t)0x80000000U)\r\n#define ETH_RECEIVEAll_DISABLE    ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter\r\n  * @{\r\n  */ \r\n#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE       ((uint32_t)0x00000200U)\r\n#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE      ((uint32_t)0x00000300U)\r\n#define ETH_SOURCEADDRFILTER_DISABLE             ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames\r\n  * @{\r\n  */ \r\n#define ETH_PASSCONTROLFRAMES_BLOCKALL                ((uint32_t)0x00000040U)  /*!< MAC filters all control frames from reaching the application */\r\n#define ETH_PASSCONTROLFRAMES_FORWARDALL              ((uint32_t)0x00000080U)  /*!< MAC forwards all control frames to application even if they fail the Address Filter */\r\n#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0U)  /*!< MAC forwards control frames that pass the Address Filter. */ \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception\r\n  * @{\r\n  */ \r\n#define ETH_BROADCASTFRAMESRECEPTION_ENABLE     ((uint32_t)0x00000000U)\r\n#define ETH_BROADCASTFRAMESRECEPTION_DISABLE    ((uint32_t)0x00000020U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter\r\n  * @{\r\n  */ \r\n#define ETH_DESTINATIONADDRFILTER_NORMAL    ((uint32_t)0x00000000U)\r\n#define ETH_DESTINATIONADDRFILTER_INVERSE   ((uint32_t)0x00000008U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode\r\n  * @{\r\n  */ \r\n#define ETH_PROMISCUOUS_MODE_ENABLE     ((uint32_t)0x00000001U)\r\n#define ETH_PROMISCUOUS_MODE_DISABLE    ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter\r\n  * @{\r\n  */ \r\n#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE    ((uint32_t)0x00000404U)\r\n#define ETH_MULTICASTFRAMESFILTER_HASHTABLE           ((uint32_t)0x00000004U)\r\n#define ETH_MULTICASTFRAMESFILTER_PERFECT             ((uint32_t)0x00000000U)\r\n#define ETH_MULTICASTFRAMESFILTER_NONE                ((uint32_t)0x00000010U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter\r\n  * @{\r\n  */ \r\n#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402U)\r\n#define ETH_UNICASTFRAMESFILTER_HASHTABLE        ((uint32_t)0x00000002U)\r\n#define ETH_UNICASTFRAMESFILTER_PERFECT          ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause \r\n  * @{\r\n  */ \r\n#define ETH_ZEROQUANTAPAUSE_ENABLE     ((uint32_t)0x00000000U)\r\n#define ETH_ZEROQUANTAPAUSE_DISABLE    ((uint32_t)0x00000080U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold\r\n  * @{\r\n  */ \r\n#define ETH_PAUSELOWTHRESHOLD_MINUS4        ((uint32_t)0x00000000U)  /*!< Pause time minus 4 slot times */\r\n#define ETH_PAUSELOWTHRESHOLD_MINUS28       ((uint32_t)0x00000010U)  /*!< Pause time minus 28 slot times */\r\n#define ETH_PAUSELOWTHRESHOLD_MINUS144      ((uint32_t)0x00000020U)  /*!< Pause time minus 144 slot times */\r\n#define ETH_PAUSELOWTHRESHOLD_MINUS256      ((uint32_t)0x00000030U)  /*!< Pause time minus 256 slot times */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect\r\n  * @{\r\n  */ \r\n#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE  ((uint32_t)0x00000008U)\r\n#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control\r\n  * @{\r\n  */ \r\n#define ETH_RECEIVEFLOWCONTROL_ENABLE       ((uint32_t)0x00000004U)\r\n#define ETH_RECEIVEFLOWCONTROL_DISABLE      ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control\r\n  * @{\r\n  */ \r\n#define ETH_TRANSMITFLOWCONTROL_ENABLE      ((uint32_t)0x00000002U)\r\n#define ETH_TRANSMITFLOWCONTROL_DISABLE     ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison\r\n  * @{\r\n  */ \r\n#define ETH_VLANTAGCOMPARISON_12BIT    ((uint32_t)0x00010000U)\r\n#define ETH_VLANTAGCOMPARISON_16BIT    ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_MAC_addresses ETH MAC addresses\r\n  * @{\r\n  */ \r\n#define ETH_MAC_ADDRESS0     ((uint32_t)0x00000000U)\r\n#define ETH_MAC_ADDRESS1     ((uint32_t)0x00000008U)\r\n#define ETH_MAC_ADDRESS2     ((uint32_t)0x00000010U)\r\n#define ETH_MAC_ADDRESS3     ((uint32_t)0x00000018U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA \r\n  * @{\r\n  */ \r\n#define ETH_MAC_ADDRESSFILTER_SA       ((uint32_t)0x00000000U)\r\n#define ETH_MAC_ADDRESSFILTER_DA       ((uint32_t)0x00000008U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes\r\n  * @{\r\n  */ \r\n#define ETH_MAC_ADDRESSMASK_BYTE6      ((uint32_t)0x20000000U)  /*!< Mask MAC Address high reg bits [15:8] */\r\n#define ETH_MAC_ADDRESSMASK_BYTE5      ((uint32_t)0x10000000U)  /*!< Mask MAC Address high reg bits [7:0] */\r\n#define ETH_MAC_ADDRESSMASK_BYTE4      ((uint32_t)0x08000000U)  /*!< Mask MAC Address low reg bits [31:24] */\r\n#define ETH_MAC_ADDRESSMASK_BYTE3      ((uint32_t)0x04000000U)  /*!< Mask MAC Address low reg bits [23:16] */\r\n#define ETH_MAC_ADDRESSMASK_BYTE2      ((uint32_t)0x02000000U)  /*!< Mask MAC Address low reg bits [15:8] */\r\n#define ETH_MAC_ADDRESSMASK_BYTE1      ((uint32_t)0x01000000U)  /*!< Mask MAC Address low reg bits [70] */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame\r\n  * @{\r\n  */ \r\n#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE   ((uint32_t)0x00000000U)\r\n#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE  ((uint32_t)0x04000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward\r\n  * @{\r\n  */ \r\n#define ETH_RECEIVESTOREFORWARD_ENABLE      ((uint32_t)0x02000000U)\r\n#define ETH_RECEIVESTOREFORWARD_DISABLE     ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame\r\n  * @{\r\n  */ \r\n#define ETH_FLUSHRECEIVEDFRAME_ENABLE       ((uint32_t)0x00000000U)\r\n#define ETH_FLUSHRECEIVEDFRAME_DISABLE      ((uint32_t)0x01000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward\r\n  * @{\r\n  */ \r\n#define ETH_TRANSMITSTOREFORWARD_ENABLE     ((uint32_t)0x00200000U)\r\n#define ETH_TRANSMITSTOREFORWARD_DISABLE    ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control\r\n  * @{\r\n  */ \r\n#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES     ((uint32_t)0x00000000U)  /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */\r\n#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES    ((uint32_t)0x00004000U)  /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */\r\n#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES    ((uint32_t)0x00008000U)  /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */\r\n#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES    ((uint32_t)0x0000C000U)  /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */\r\n#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES     ((uint32_t)0x00010000U)  /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */\r\n#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES     ((uint32_t)0x00014000U)  /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */\r\n#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES     ((uint32_t)0x00018000U)  /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */\r\n#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES     ((uint32_t)0x0001C000U)  /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames\r\n  * @{\r\n  */ \r\n#define ETH_FORWARDERRORFRAMES_ENABLE       ((uint32_t)0x00000080U)\r\n#define ETH_FORWARDERRORFRAMES_DISABLE      ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames\r\n  * @{\r\n  */ \r\n#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE   ((uint32_t)0x00000040U)\r\n#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE  ((uint32_t)0x00000000U)     \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control\r\n  * @{\r\n  */ \r\n#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES      ((uint32_t)0x00000000U)  /*!< threshold level of the MTL Receive FIFO is 64 Bytes */\r\n#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES      ((uint32_t)0x00000008U)  /*!< threshold level of the MTL Receive FIFO is 32 Bytes */\r\n#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES      ((uint32_t)0x00000010U)  /*!< threshold level of the MTL Receive FIFO is 96 Bytes */\r\n#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES     ((uint32_t)0x00000018U)  /*!< threshold level of the MTL Receive FIFO is 128 Bytes */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate\r\n  * @{\r\n  */ \r\n#define ETH_SECONDFRAMEOPERARTE_ENABLE       ((uint32_t)0x00000004U)\r\n#define ETH_SECONDFRAMEOPERARTE_DISABLE      ((uint32_t)0x00000000U)  \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats \r\n  * @{\r\n  */ \r\n#define ETH_ADDRESSALIGNEDBEATS_ENABLE      ((uint32_t)0x02000000U)\r\n#define ETH_ADDRESSALIGNEDBEATS_DISABLE     ((uint32_t)0x00000000U) \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Fixed_Burst ETH Fixed Burst\r\n  * @{\r\n  */ \r\n#define ETH_FIXEDBURST_ENABLE     ((uint32_t)0x00010000U)\r\n#define ETH_FIXEDBURST_DISABLE    ((uint32_t)0x00000000U) \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length\r\n  * @{\r\n  */ \r\n#define ETH_RXDMABURSTLENGTH_1BEAT          ((uint32_t)0x00020000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */\r\n#define ETH_RXDMABURSTLENGTH_2BEAT          ((uint32_t)0x00040000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */\r\n#define ETH_RXDMABURSTLENGTH_4BEAT          ((uint32_t)0x00080000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */\r\n#define ETH_RXDMABURSTLENGTH_8BEAT          ((uint32_t)0x00100000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */\r\n#define ETH_RXDMABURSTLENGTH_16BEAT         ((uint32_t)0x00200000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */\r\n#define ETH_RXDMABURSTLENGTH_32BEAT         ((uint32_t)0x00400000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */                \r\n#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT    ((uint32_t)0x01020000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */\r\n#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT    ((uint32_t)0x01040000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */\r\n#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT   ((uint32_t)0x01080000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */\r\n#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT   ((uint32_t)0x01100000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */\r\n#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT   ((uint32_t)0x01200000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */\r\n#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT  ((uint32_t)0x01400000U)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length\r\n  * @{\r\n  */ \r\n#define ETH_TXDMABURSTLENGTH_1BEAT          ((uint32_t)0x00000100U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */\r\n#define ETH_TXDMABURSTLENGTH_2BEAT          ((uint32_t)0x00000200U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */\r\n#define ETH_TXDMABURSTLENGTH_4BEAT          ((uint32_t)0x00000400U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r\n#define ETH_TXDMABURSTLENGTH_8BEAT          ((uint32_t)0x00000800U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r\n#define ETH_TXDMABURSTLENGTH_16BEAT         ((uint32_t)0x00001000U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r\n#define ETH_TXDMABURSTLENGTH_32BEAT         ((uint32_t)0x00002000U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                \r\n#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT    ((uint32_t)0x01000100U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r\n#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT    ((uint32_t)0x01000200U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r\n#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT   ((uint32_t)0x01000400U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r\n#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT   ((uint32_t)0x01000800U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\r\n#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT   ((uint32_t)0x01001000U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */\r\n#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT  ((uint32_t)0x01002000U)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format\r\n  * @{\r\n  */  \r\n#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE              ((uint32_t)0x00000080U)\r\n#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE             ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration\r\n  * @{\r\n  */ \r\n#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1   ((uint32_t)0x00000000U)\r\n#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1   ((uint32_t)0x00004000U)\r\n#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1   ((uint32_t)0x00008000U)\r\n#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1   ((uint32_t)0x0000C000U)\r\n#define ETH_DMAARBITRATION_RXPRIORTX             ((uint32_t)0x00000002U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment\r\n  * @{\r\n  */ \r\n#define ETH_DMATXDESC_LASTSEGMENTS      ((uint32_t)0x40000000U)  /*!< Last Segment */\r\n#define ETH_DMATXDESC_FIRSTSEGMENT      ((uint32_t)0x20000000U)  /*!< First Segment */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control\r\n  * @{\r\n  */ \r\n#define ETH_DMATXDESC_CHECKSUMBYPASS             ((uint32_t)0x00000000U)   /*!< Checksum engine bypass */\r\n#define ETH_DMATXDESC_CHECKSUMIPV4HEADER         ((uint32_t)0x00400000U)   /*!< IPv4 header checksum insertion  */\r\n#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT  ((uint32_t)0x00800000U)   /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */\r\n#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL     ((uint32_t)0x00C00000U)   /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers \r\n  * @{\r\n  */ \r\n#define ETH_DMARXDESC_BUFFER1     ((uint32_t)0x00000000U)  /*!< DMA Rx Desc Buffer1 */\r\n#define ETH_DMARXDESC_BUFFER2     ((uint32_t)0x00000001U)  /*!< DMA Rx Desc Buffer2 */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_PMT_Flags ETH PMT Flags\r\n  * @{\r\n  */ \r\n#define ETH_PMT_FLAG_WUFFRPR      ((uint32_t)0x80000000U)  /*!< Wake-Up Frame Filter Register Pointer Reset */\r\n#define ETH_PMT_FLAG_WUFR         ((uint32_t)0x00000040U)  /*!< Wake-Up Frame Received */\r\n#define ETH_PMT_FLAG_MPR          ((uint32_t)0x00000020U)  /*!< Magic Packet Received */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts\r\n  * @{\r\n  */ \r\n#define ETH_MMC_IT_TGF       ((uint32_t)0x00200000U)  /*!< When Tx good frame counter reaches half the maximum value */\r\n#define ETH_MMC_IT_TGFMSC    ((uint32_t)0x00008000U)  /*!< When Tx good multi col counter reaches half the maximum value */\r\n#define ETH_MMC_IT_TGFSC     ((uint32_t)0x00004000U)  /*!< When Tx good single col counter reaches half the maximum value */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts\r\n  * @{\r\n  */\r\n#define ETH_MMC_IT_RGUF      ((uint32_t)0x10020000U)  /*!< When Rx good unicast frames counter reaches half the maximum value */\r\n#define ETH_MMC_IT_RFAE      ((uint32_t)0x10000040U)  /*!< When Rx alignment error counter reaches half the maximum value */\r\n#define ETH_MMC_IT_RFCE      ((uint32_t)0x10000020U)  /*!< When Rx crc error counter reaches half the maximum value */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_MAC_Flags ETH MAC Flags\r\n  * @{\r\n  */ \r\n#define ETH_MAC_FLAG_TST     ((uint32_t)0x00000200U)  /*!< Time stamp trigger flag (on MAC) */\r\n#define ETH_MAC_FLAG_MMCT    ((uint32_t)0x00000040U)  /*!< MMC transmit flag  */\r\n#define ETH_MAC_FLAG_MMCR    ((uint32_t)0x00000020U)  /*!< MMC receive flag */\r\n#define ETH_MAC_FLAG_MMC     ((uint32_t)0x00000010U)  /*!< MMC flag (on MAC) */\r\n#define ETH_MAC_FLAG_PMT     ((uint32_t)0x00000008U)  /*!< PMT flag (on MAC) */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_DMA_Flags ETH DMA Flags\r\n  * @{\r\n  */ \r\n#define ETH_DMA_FLAG_TST               ((uint32_t)0x20000000U)  /*!< Time-stamp trigger interrupt (on DMA) */\r\n#define ETH_DMA_FLAG_PMT               ((uint32_t)0x10000000U)  /*!< PMT interrupt (on DMA) */\r\n#define ETH_DMA_FLAG_MMC               ((uint32_t)0x08000000U)  /*!< MMC interrupt (on DMA) */\r\n#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000U)  /*!< Error bits 0-Rx DMA, 1-Tx DMA */\r\n#define ETH_DMA_FLAG_READWRITEERROR    ((uint32_t)0x01000000U)  /*!< Error bits 0-write transfer, 1-read transfer */\r\n#define ETH_DMA_FLAG_ACCESSERROR       ((uint32_t)0x02000000U)  /*!< Error bits 0-data buffer, 1-desc. access */\r\n#define ETH_DMA_FLAG_NIS               ((uint32_t)0x00010000U)  /*!< Normal interrupt summary flag */\r\n#define ETH_DMA_FLAG_AIS               ((uint32_t)0x00008000U)  /*!< Abnormal interrupt summary flag */\r\n#define ETH_DMA_FLAG_ER                ((uint32_t)0x00004000U)  /*!< Early receive flag */\r\n#define ETH_DMA_FLAG_FBE               ((uint32_t)0x00002000U)  /*!< Fatal bus error flag */\r\n#define ETH_DMA_FLAG_ET                ((uint32_t)0x00000400U)  /*!< Early transmit flag */\r\n#define ETH_DMA_FLAG_RWT               ((uint32_t)0x00000200U)  /*!< Receive watchdog timeout flag */\r\n#define ETH_DMA_FLAG_RPS               ((uint32_t)0x00000100U)  /*!< Receive process stopped flag */\r\n#define ETH_DMA_FLAG_RBU               ((uint32_t)0x00000080U)  /*!< Receive buffer unavailable flag */\r\n#define ETH_DMA_FLAG_R                 ((uint32_t)0x00000040U)  /*!< Receive flag */\r\n#define ETH_DMA_FLAG_TU                ((uint32_t)0x00000020U)  /*!< Underflow flag */\r\n#define ETH_DMA_FLAG_RO                ((uint32_t)0x00000010U)  /*!< Overflow flag */\r\n#define ETH_DMA_FLAG_TJT               ((uint32_t)0x00000008U)  /*!< Transmit jabber timeout flag */\r\n#define ETH_DMA_FLAG_TBU               ((uint32_t)0x00000004U)  /*!< Transmit buffer unavailable flag */\r\n#define ETH_DMA_FLAG_TPS               ((uint32_t)0x00000002U)  /*!< Transmit process stopped flag */\r\n#define ETH_DMA_FLAG_T                 ((uint32_t)0x00000001U)  /*!< Transmit flag */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts \r\n  * @{\r\n  */ \r\n#define ETH_MAC_IT_TST       ((uint32_t)0x00000200U)  /*!< Time stamp trigger interrupt (on MAC) */\r\n#define ETH_MAC_IT_MMCT      ((uint32_t)0x00000040U)  /*!< MMC transmit interrupt */\r\n#define ETH_MAC_IT_MMCR      ((uint32_t)0x00000020U)  /*!< MMC receive interrupt */\r\n#define ETH_MAC_IT_MMC       ((uint32_t)0x00000010U)  /*!< MMC interrupt (on MAC) */\r\n#define ETH_MAC_IT_PMT       ((uint32_t)0x00000008U)  /*!< PMT interrupt (on MAC) */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts \r\n  * @{\r\n  */ \r\n#define ETH_DMA_IT_TST       ((uint32_t)0x20000000U)  /*!< Time-stamp trigger interrupt (on DMA) */\r\n#define ETH_DMA_IT_PMT       ((uint32_t)0x10000000U)  /*!< PMT interrupt (on DMA) */\r\n#define ETH_DMA_IT_MMC       ((uint32_t)0x08000000U)  /*!< MMC interrupt (on DMA) */\r\n#define ETH_DMA_IT_NIS       ((uint32_t)0x00010000U)  /*!< Normal interrupt summary */\r\n#define ETH_DMA_IT_AIS       ((uint32_t)0x00008000U)  /*!< Abnormal interrupt summary */\r\n#define ETH_DMA_IT_ER        ((uint32_t)0x00004000U)  /*!< Early receive interrupt */\r\n#define ETH_DMA_IT_FBE       ((uint32_t)0x00002000U)  /*!< Fatal bus error interrupt */\r\n#define ETH_DMA_IT_ET        ((uint32_t)0x00000400U)  /*!< Early transmit interrupt */\r\n#define ETH_DMA_IT_RWT       ((uint32_t)0x00000200U)  /*!< Receive watchdog timeout interrupt */\r\n#define ETH_DMA_IT_RPS       ((uint32_t)0x00000100U)  /*!< Receive process stopped interrupt */\r\n#define ETH_DMA_IT_RBU       ((uint32_t)0x00000080U)  /*!< Receive buffer unavailable interrupt */\r\n#define ETH_DMA_IT_R         ((uint32_t)0x00000040U)  /*!< Receive interrupt */\r\n#define ETH_DMA_IT_TU        ((uint32_t)0x00000020U)  /*!< Underflow interrupt */\r\n#define ETH_DMA_IT_RO        ((uint32_t)0x00000010U)  /*!< Overflow interrupt */\r\n#define ETH_DMA_IT_TJT       ((uint32_t)0x00000008U)  /*!< Transmit jabber timeout interrupt */\r\n#define ETH_DMA_IT_TBU       ((uint32_t)0x00000004U)  /*!< Transmit buffer unavailable interrupt */\r\n#define ETH_DMA_IT_TPS       ((uint32_t)0x00000002U)  /*!< Transmit process stopped interrupt */\r\n#define ETH_DMA_IT_T         ((uint32_t)0x00000001U)  /*!< Transmit interrupt */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state \r\n  * @{\r\n  */ \r\n#define ETH_DMA_TRANSMITPROCESS_STOPPED     ((uint32_t)0x00000000U)  /*!< Stopped - Reset or Stop Tx Command issued */\r\n#define ETH_DMA_TRANSMITPROCESS_FETCHING    ((uint32_t)0x00100000U)  /*!< Running - fetching the Tx descriptor */\r\n#define ETH_DMA_TRANSMITPROCESS_WAITING     ((uint32_t)0x00200000U)  /*!< Running - waiting for status */\r\n#define ETH_DMA_TRANSMITPROCESS_READING     ((uint32_t)0x00300000U)  /*!< Running - reading the data from host memory */\r\n#define ETH_DMA_TRANSMITPROCESS_SUSPENDED   ((uint32_t)0x00600000U)  /*!< Suspended - Tx Descriptor unavailable */\r\n#define ETH_DMA_TRANSMITPROCESS_CLOSING     ((uint32_t)0x00700000U)  /*!< Running - closing Rx descriptor */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state \r\n  * @{\r\n  */ \r\n#define ETH_DMA_RECEIVEPROCESS_STOPPED      ((uint32_t)0x00000000U)  /*!< Stopped - Reset or Stop Rx Command issued */\r\n#define ETH_DMA_RECEIVEPROCESS_FETCHING     ((uint32_t)0x00020000U)  /*!< Running - fetching the Rx descriptor */\r\n#define ETH_DMA_RECEIVEPROCESS_WAITING      ((uint32_t)0x00060000U)  /*!< Running - waiting for packet */\r\n#define ETH_DMA_RECEIVEPROCESS_SUSPENDED    ((uint32_t)0x00080000U)  /*!< Suspended - Rx Descriptor unavailable */\r\n#define ETH_DMA_RECEIVEPROCESS_CLOSING      ((uint32_t)0x000A0000U)  /*!< Running - closing descriptor */\r\n#define ETH_DMA_RECEIVEPROCESS_QUEUING      ((uint32_t)0x000E0000U)  /*!< Running - queuing the receive frame into host memory */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_DMA_overflow ETH DMA overflow\r\n  * @{\r\n  */ \r\n#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER      ((uint32_t)0x10000000U)  /*!< Overflow bit for FIFO overflow counter */\r\n#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000U)  /*!< Overflow bit for missed frame counter */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP\r\n  * @{\r\n  */ \r\n#define ETH_EXTI_LINE_WAKEUP              ((uint32_t)0x00080000U)  /*!< External interrupt line 19 Connected to the ETH EXTI Line */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup ETH_Exported_Macros ETH Exported Macros\r\n *  @brief macros to handle interrupts and specific clock configurations\r\n * @{\r\n */\r\n \r\n/** @brief Reset ETH handle state\r\n  * @param  __HANDLE__: specifies the ETH handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)\r\n\r\n/** \r\n  * @brief  Checks whether the specified Ethernet DMA Tx Desc flag is set or not.\r\n  * @param  __HANDLE__: ETH Handle\r\n  * @param  __FLAG__: specifies the flag of TDES0 to check.\r\n  * @retval the ETH_DMATxDescFlag (SET or RESET).\r\n  */\r\n#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__)             ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))\r\n\r\n/**\r\n  * @brief  Checks whether the specified Ethernet DMA Rx Desc flag is set or not.\r\n  * @param  __HANDLE__: ETH Handle\r\n  * @param  __FLAG__: specifies the flag of RDES0 to check.\r\n  * @retval the ETH_DMATxDescFlag (SET or RESET).\r\n  */\r\n#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__)             ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))\r\n\r\n/**\r\n  * @brief  Enables the specified DMA Rx Desc receive interrupt.\r\n  * @param  __HANDLE__: ETH Handle\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__)                          ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))\r\n\r\n/**\r\n  * @brief  Disables the specified DMA Rx Desc receive interrupt.\r\n  * @param  __HANDLE__: ETH Handle\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__)                         ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)\r\n\r\n/**\r\n  * @brief  Set the specified DMA Rx Desc Own bit.\r\n  * @param  __HANDLE__: ETH Handle\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__)                           ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)\r\n\r\n/**\r\n  * @brief  Returns the specified Ethernet DMA Tx Desc collision count.\r\n  * @param  __HANDLE__: ETH Handle                     \r\n  * @retval The Transmit descriptor collision counter value.\r\n  */\r\n#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__)                   (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)\r\n\r\n/**\r\n  * @brief  Set the specified DMA Tx Desc Own bit.\r\n  * @param  __HANDLE__: ETH Handle\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__)                       ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)\r\n\r\n/**\r\n  * @brief  Enables the specified DMA Tx Desc Transmit interrupt.\r\n  * @param  __HANDLE__: ETH Handle                   \r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__)                          ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)\r\n\r\n/**\r\n  * @brief  Disables the specified DMA Tx Desc Transmit interrupt.\r\n  * @param  __HANDLE__: ETH Handle             \r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__)                          ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)\r\n\r\n/**\r\n  * @brief  Selects the specified Ethernet DMA Tx Desc Checksum Insertion.\r\n  * @param  __HANDLE__: ETH Handle  \r\n  * @param  __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.\r\n  *   This parameter can be one of the following values:\r\n  *     @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass\r\n  *     @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum\r\n  *     @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present\r\n  *     @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header                                                                \r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__)     ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))\r\n\r\n/**\r\n  * @brief  Enables the DMA Tx Desc CRC.\r\n  * @param  __HANDLE__: ETH Handle \r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__)                          ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)\r\n\r\n/**\r\n  * @brief  Disables the DMA Tx Desc CRC.\r\n  * @param  __HANDLE__: ETH Handle \r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__)                         ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)\r\n\r\n/**\r\n  * @brief  Enables the DMA Tx Desc padding for frame shorter than 64 bytes.\r\n  * @param  __HANDLE__: ETH Handle \r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__)            ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)\r\n\r\n/**\r\n  * @brief  Disables the DMA Tx Desc padding for frame shorter than 64 bytes.\r\n  * @param  __HANDLE__: ETH Handle \r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__)           ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)\r\n\r\n/** \r\n * @brief  Enables the specified Ethernet MAC interrupts.\r\n  * @param  __HANDLE__   : ETH Handle\r\n  * @param  __INTERRUPT__: specifies the Ethernet MAC interrupt sources to be\r\n  *   enabled or disabled.\r\n  *   This parameter can be any combination of the following values:\r\n  *     @arg ETH_MAC_IT_TST : Time stamp trigger interrupt \r\n  *     @arg ETH_MAC_IT_PMT : PMT interrupt \r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                 ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disables the specified Ethernet MAC interrupts.\r\n  * @param  __HANDLE__   : ETH Handle\r\n  * @param  __INTERRUPT__: specifies the Ethernet MAC interrupt sources to be\r\n  *   enabled or disabled.\r\n  *   This parameter can be any combination of the following values:\r\n  *     @arg ETH_MAC_IT_TST : Time stamp trigger interrupt \r\n  *     @arg ETH_MAC_IT_PMT : PMT interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__)                ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Initiate a Pause Control Frame (Full-duplex only).\r\n  * @param  __HANDLE__: ETH Handle\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__)              ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)\r\n\r\n/**\r\n  * @brief  Checks whether the Ethernet flow control busy bit is set or not.\r\n  * @param  __HANDLE__: ETH Handle\r\n  * @retval The new state of flow control busy status bit (SET or RESET).\r\n  */\r\n#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__)               (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)\r\n\r\n/**\r\n  * @brief  Enables the MAC Back Pressure operation activation (Half-duplex only).\r\n  * @param  __HANDLE__: ETH Handle\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__)          ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)\r\n\r\n/**\r\n  * @brief  Disables the MAC BackPressure operation activation (Half-duplex only).\r\n  * @param  __HANDLE__: ETH Handle\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__)         ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)\r\n\r\n/**\r\n  * @brief  Checks whether the specified Ethernet MAC flag is set or not.\r\n  * @param  __HANDLE__: ETH Handle\r\n  * @param  __FLAG__: specifies the flag to check.\r\n  *   This parameter can be one of the following values:\r\n  *     @arg ETH_MAC_FLAG_TST  : Time stamp trigger flag   \r\n  *     @arg ETH_MAC_FLAG_MMCT : MMC transmit flag  \r\n  *     @arg ETH_MAC_FLAG_MMCR : MMC receive flag   \r\n  *     @arg ETH_MAC_FLAG_MMC  : MMC flag  \r\n  *     @arg ETH_MAC_FLAG_PMT  : PMT flag  \r\n  * @retval The state of Ethernet MAC flag.\r\n  */\r\n#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__)                   (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))\r\n\r\n/** \r\n  * @brief  Enables the specified Ethernet DMA interrupts.\r\n  * @param  __HANDLE__   : ETH Handle\r\n  * @param  __INTERRUPT__: specifies the Ethernet DMA interrupt sources to be\r\n  *   enabled @ref ETH_DMA_Interrupts\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)                 ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disables the specified Ethernet DMA interrupts.\r\n  * @param  __HANDLE__   : ETH Handle\r\n  * @param  __INTERRUPT__: specifies the Ethernet DMA interrupt sources to be\r\n  *   disabled. @ref ETH_DMA_Interrupts\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)                ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Clears the Ethernet DMA IT pending bit.\r\n  * @param  __HANDLE__   : ETH Handle\r\n  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Checks whether the specified Ethernet DMA flag is set or not.\r\n* @param  __HANDLE__: ETH Handle\r\n  * @param  __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags\r\n  * @retval The new state of ETH_DMA_FLAG (SET or RESET).\r\n  */\r\n#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__)                   (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))\r\n\r\n/**\r\n  * @brief  Checks whether the specified Ethernet DMA flag is set or not.\r\n  * @param  __HANDLE__: ETH Handle\r\n  * @param  __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags\r\n  * @retval The new state of ETH_DMA_FLAG (SET or RESET).\r\n  */\r\n#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)                 ((__HANDLE__)->Instance->DMASR = (__FLAG__))\r\n\r\n/**\r\n  * @brief  Checks whether the specified Ethernet DMA overflow flag is set or not.\r\n  * @param  __HANDLE__: ETH Handle\r\n  * @param  __OVERFLOW__: specifies the DMA overflow flag to check.\r\n  *   This parameter can be one of the following values:\r\n  *     @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter\r\n  *     @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter\r\n  * @retval The state of Ethernet DMA overflow Flag (SET or RESET).\r\n  */\r\n#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__)       (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))\r\n\r\n/**\r\n  * @brief  Set the DMA Receive status watchdog timer register value\r\n  * @param  __HANDLE__: ETH Handle\r\n  * @param  __VALUE__: DMA Receive status watchdog timer register value   \r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__)       ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))\r\n\r\n/** \r\n  * @brief  Enables any unicast packet filtered by the MAC address\r\n  *   recognition to be a wake-up frame.\r\n  * @param  __HANDLE__: ETH Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)\r\n\r\n/**\r\n  * @brief  Disables any unicast packet filtered by the MAC address\r\n  *   recognition to be a wake-up frame.\r\n  * @param  __HANDLE__: ETH Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)\r\n\r\n/**\r\n  * @brief  Enables the MAC Wake-Up Frame Detection.\r\n  * @param  __HANDLE__: ETH Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__)              ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)\r\n\r\n/**\r\n  * @brief  Disables the MAC Wake-Up Frame Detection.\r\n  * @param  __HANDLE__: ETH Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__)             ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)\r\n\r\n/**\r\n  * @brief  Enables the MAC Magic Packet Detection.\r\n  * @param  __HANDLE__: ETH Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__)              ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)\r\n\r\n/**\r\n  * @brief  Disables the MAC Magic Packet Detection.\r\n  * @param  __HANDLE__: ETH Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__)             ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)\r\n\r\n/**\r\n  * @brief  Enables the MAC Power Down.\r\n  * @param  __HANDLE__: ETH Handle\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)\r\n\r\n/**\r\n  * @brief  Disables the MAC Power Down.\r\n  * @param  __HANDLE__: ETH Handle\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)\r\n\r\n/**\r\n  * @brief  Checks whether the specified Ethernet PMT flag is set or not.\r\n  * @param  __HANDLE__: ETH Handle.\r\n  * @param  __FLAG__: specifies the flag to check.\r\n  *   This parameter can be one of the following values:\r\n  *     @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset \r\n  *     @arg ETH_PMT_FLAG_WUFR    : Wake-Up Frame Received \r\n  *     @arg ETH_PMT_FLAG_MPR     : Magic Packet Received\r\n  * @retval The new state of Ethernet PMT Flag (SET or RESET).\r\n  */\r\n#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__)               (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))\r\n\r\n/** \r\n  * @brief  Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)\r\n  * @param   __HANDLE__: ETH Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__)                     ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))\r\n\r\n/**\r\n  * @brief  Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)\r\n  * @param  __HANDLE__: ETH Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__)                     do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\\\r\n                                                                          (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)\r\n\r\n/**\r\n  * @brief  Enables the MMC Counter Freeze.\r\n  * @param  __HANDLE__: ETH Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__)                  ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)\r\n\r\n/**\r\n  * @brief  Disables the MMC Counter Freeze.\r\n  * @param  __HANDLE__: ETH Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__)                 ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)\r\n\r\n/**\r\n  * @brief  Enables the MMC Reset On Read.\r\n  * @param  __HANDLE__: ETH Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)\r\n\r\n/**\r\n  * @brief  Disables the MMC Reset On Read.\r\n  * @param  __HANDLE__: ETH Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)\r\n\r\n/**\r\n  * @brief  Enables the MMC Counter Stop Rollover.\r\n  * @param  __HANDLE__: ETH Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__)            ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)\r\n\r\n/**\r\n  * @brief  Disables the MMC Counter Stop Rollover.\r\n  * @param  __HANDLE__: ETH Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__)           ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)\r\n\r\n/**\r\n  * @brief  Resets the MMC Counters.\r\n  * @param   __HANDLE__: ETH Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__)                         ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)\r\n\r\n/**\r\n  * @brief  Enables the specified Ethernet MMC Rx interrupts.\r\n  * @param   __HANDLE__: ETH Handle.\r\n  * @param  __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled.\r\n  *   This parameter can be one of the following values:  \r\n  *     @arg ETH_MMC_IT_RGUF  : When Rx good unicast frames counter reaches half the maximum value \r\n  *     @arg ETH_MMC_IT_RFAE  : When Rx alignment error counter reaches half the maximum value \r\n  *     @arg ETH_MMC_IT_RFCE  : When Rx crc error counter reaches half the maximum value\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__)               (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)\r\n/**\r\n  * @brief  Disables the specified Ethernet MMC Rx interrupts.\r\n  * @param   __HANDLE__: ETH Handle.\r\n  * @param  __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled.\r\n  *   This parameter can be one of the following values: \r\n  *     @arg ETH_MMC_IT_RGUF  : When Rx good unicast frames counter reaches half the maximum value \r\n  *     @arg ETH_MMC_IT_RFAE  : When Rx alignment error counter reaches half the maximum value \r\n  *     @arg ETH_MMC_IT_RFCE  : When Rx crc error counter reaches half the maximum value\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__)              (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF)\r\n/**\r\n  * @brief  Enables the specified Ethernet MMC Tx interrupts.\r\n  * @param   __HANDLE__: ETH Handle.\r\n  * @param  __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled.\r\n  *   This parameter can be one of the following values:  \r\n  *     @arg ETH_MMC_IT_TGF   : When Tx good frame counter reaches half the maximum value \r\n  *     @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value \r\n  *     @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value \r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__)            ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disables the specified Ethernet MMC Tx interrupts.\r\n  * @param   __HANDLE__: ETH Handle.\r\n  * @param  __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled.\r\n  *   This parameter can be one of the following values:  \r\n  *     @arg ETH_MMC_IT_TGF   : When Tx good frame counter reaches half the maximum value \r\n  *     @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value \r\n  *     @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value \r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__)           ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Enables the ETH External interrupt line.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT()    EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)\r\n\r\n/**\r\n  * @brief  Disables the ETH External interrupt line.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT()   EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)\r\n\r\n/**\r\n  * @brief Enable event on ETH External event line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT()  EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)\r\n\r\n/**\r\n  * @brief Disable event on ETH External event line\r\n  * @retval None.\r\n  */\r\n#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)\r\n\r\n/**\r\n  * @brief  Get flag of the ETH External interrupt line.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG()     EXTI->PR & (ETH_EXTI_LINE_WAKEUP)\r\n\r\n/**\r\n  * @brief  Clear flag of the ETH External interrupt line.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG()   EXTI->PR = (ETH_EXTI_LINE_WAKEUP)\r\n\r\n/**\r\n  * @brief  Enables rising edge trigger to the ETH External interrupt line.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER()  EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP\r\n                                                            \r\n/**\r\n  * @brief  Disables the rising edge trigger to the ETH External interrupt line.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER()  EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)                                                          \r\n\r\n/**\r\n  * @brief  Enables falling edge trigger to the ETH External interrupt line.\r\n  * @retval None\r\n  */                                                      \r\n#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER()  EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)\r\n\r\n/**\r\n  * @brief  Disables falling edge trigger to the ETH External interrupt line.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER()  EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)\r\n\r\n/**\r\n  * @brief  Enables rising/falling edge trigger to the ETH External interrupt line.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER()  EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\\\r\n                                                              EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP\r\n\r\n/**\r\n  * @brief  Disables rising/falling edge trigger to the ETH External interrupt line.\r\n  * @retval None\r\n  */\r\n#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER()  EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\\\r\n                                                               EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)\r\n\r\n/**\r\n  * @brief Generate a Software interrupt on selected EXTI line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT()                  EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @addtogroup ETH_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/* Initialization and de-initialization functions  ****************************/\r\n\r\n/** @addtogroup ETH_Exported_Functions_Group1\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);\r\nHAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);\r\nvoid HAL_ETH_MspInit(ETH_HandleTypeDef *heth);\r\nvoid HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);\r\nHAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);\r\nHAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* IO operation functions  ****************************************************/\r\n\r\n/** @addtogroup ETH_Exported_Functions_Group2\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);\r\nHAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);\r\n/* Communication with PHY functions*/\r\nHAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);\r\nHAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);\r\nvoid HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);\r\n/* Callback in non blocking modes (Interrupt) */\r\nvoid HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);\r\nvoid HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);\r\nvoid HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Peripheral Control functions  **********************************************/\r\n\r\n/** @addtogroup ETH_Exported_Functions_Group3\r\n  * @{\r\n  */\r\n\r\nHAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);\r\nHAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);\r\nHAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);\r\nHAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Peripheral State functions  ************************************************/\r\n\r\n/** @addtogroup ETH_Exported_Functions_Group4\r\n  * @{\r\n  */\r\nHAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_ETH_H */\r\n\r\n\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_flash.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of FLASH HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_FLASH_H\r\n#define __STM32F7xx_HAL_FLASH_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup FLASH\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/ \r\n/** @defgroup FLASH_Exported_Types FLASH Exported Types\r\n  * @{\r\n  */\r\n \r\n/**\r\n  * @brief  FLASH Procedure structure definition\r\n  */\r\ntypedef enum \r\n{\r\n  FLASH_PROC_NONE = 0U, \r\n  FLASH_PROC_SECTERASE,\r\n  FLASH_PROC_MASSERASE,\r\n  FLASH_PROC_PROGRAM\r\n} FLASH_ProcedureTypeDef;\r\n\r\n\r\n/** \r\n  * @brief  FLASH handle Structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  __IO FLASH_ProcedureTypeDef ProcedureOnGoing;   /* Internal variable to indicate which procedure is ongoing or not in IT context */\r\n  \r\n  __IO uint32_t               NbSectorsToErase;   /* Internal variable to save the remaining sectors to erase in IT context        */\r\n  \r\n  __IO uint8_t                VoltageForErase;    /* Internal variable to provide voltage range selected by user in IT context     */\r\n  \r\n  __IO uint32_t               Sector;             /* Internal variable to define the current sector which is erasing               */\r\n\r\n  __IO uint32_t               Address;            /* Internal variable to save address selected for program                        */\r\n  \r\n  HAL_LockTypeDef             Lock;               /* FLASH locking object                                                          */\r\n\r\n  __IO uint32_t               ErrorCode;          /* FLASH error code                                                              */\r\n\r\n}FLASH_ProcessTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup FLASH_Exported_Constants FLASH Exported Constants\r\n  * @{\r\n  */  \r\n\r\n/** @defgroup FLASH_Error_Code FLASH Error Code\r\n  * @brief    FLASH Error Code \r\n  * @{\r\n  */ \r\n#define HAL_FLASH_ERROR_NONE         ((uint32_t)0x00000000U)    /*!< No error                      */\r\n#define HAL_FLASH_ERROR_ERS          ((uint32_t)0x00000002U)    /*!< Programming Sequence error    */\r\n#define HAL_FLASH_ERROR_PGP          ((uint32_t)0x00000004U)    /*!< Programming Parallelism error */\r\n#define HAL_FLASH_ERROR_PGA          ((uint32_t)0x00000008U)    /*!< Programming Alignment error   */\r\n#define HAL_FLASH_ERROR_WRP          ((uint32_t)0x00000010U)    /*!< Write protection error        */\r\n#define HAL_FLASH_ERROR_OPERATION    ((uint32_t)0x00000020U)    /*!< Operation Error               */\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup FLASH_Type_Program FLASH Type Program\r\n  * @{\r\n  */ \r\n#define FLASH_TYPEPROGRAM_BYTE        ((uint32_t)0x00U)  /*!< Program byte (8-bit) at a specified address           */\r\n#define FLASH_TYPEPROGRAM_HALFWORD    ((uint32_t)0x01U)  /*!< Program a half-word (16-bit) at a specified address   */\r\n#define FLASH_TYPEPROGRAM_WORD        ((uint32_t)0x02U)  /*!< Program a word (32-bit) at a specified address        */\r\n#define FLASH_TYPEPROGRAM_DOUBLEWORD  ((uint32_t)0x03U)  /*!< Program a double word (64-bit) at a specified address */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FLASH_Flag_definition FLASH Flag definition\r\n  * @brief Flag definition\r\n  * @{\r\n  */ \r\n#define FLASH_FLAG_EOP                 FLASH_SR_EOP            /*!< FLASH End of Operation flag               */\r\n#define FLASH_FLAG_OPERR               FLASH_SR_OPERR          /*!< FLASH operation Error flag                */\r\n#define FLASH_FLAG_WRPERR              FLASH_SR_WRPERR         /*!< FLASH Write protected error flag          */\r\n#define FLASH_FLAG_PGAERR              FLASH_SR_PGAERR         /*!< FLASH Programming Alignment error flag    */\r\n#define FLASH_FLAG_PGPERR              FLASH_SR_PGPERR         /*!< FLASH Programming Parallelism error flag  */\r\n#define FLASH_FLAG_ERSERR              FLASH_SR_ERSERR         /*!< FLASH Erasing Sequence error flag         */\r\n#define FLASH_FLAG_BSY                 FLASH_SR_BSY            /*!< FLASH Busy flag                           */ \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition\r\n  * @brief FLASH Interrupt definition\r\n  * @{\r\n  */\r\n#define FLASH_IT_EOP                   FLASH_CR_EOPIE          /*!< End of FLASH Operation Interrupt source */\r\n#define FLASH_IT_ERR                   ((uint32_t)0x02000000U)  /*!< Error Interrupt source                  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism\r\n  * @{\r\n  */\r\n#define FLASH_PSIZE_BYTE           ((uint32_t)0x00000000U)\r\n#define FLASH_PSIZE_HALF_WORD      ((uint32_t)FLASH_CR_PSIZE_0)\r\n#define FLASH_PSIZE_WORD           ((uint32_t)FLASH_CR_PSIZE_1)\r\n#define FLASH_PSIZE_DOUBLE_WORD    ((uint32_t)FLASH_CR_PSIZE)\r\n#define CR_PSIZE_MASK              ((uint32_t)0xFFFFFCFFU)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup FLASH_Keys FLASH Keys\r\n  * @{\r\n  */ \r\n#define FLASH_KEY1               ((uint32_t)0x45670123U)\r\n#define FLASH_KEY2               ((uint32_t)0xCDEF89ABU)\r\n#define FLASH_OPT_KEY1           ((uint32_t)0x08192A3BU)\r\n#define FLASH_OPT_KEY2           ((uint32_t)0x4C5D6E7FU)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FLASH_Sectors FLASH Sectors\r\n  * @{\r\n  */\r\n#define FLASH_SECTOR_0           ((uint32_t)0U) /*!< Sector Number 0   */\r\n#define FLASH_SECTOR_1           ((uint32_t)1U) /*!< Sector Number 1   */\r\n#define FLASH_SECTOR_2           ((uint32_t)2U) /*!< Sector Number 2   */\r\n#define FLASH_SECTOR_3           ((uint32_t)3U) /*!< Sector Number 3   */\r\n#define FLASH_SECTOR_4           ((uint32_t)4U) /*!< Sector Number 4   */\r\n#define FLASH_SECTOR_5           ((uint32_t)5U) /*!< Sector Number 5   */\r\n#define FLASH_SECTOR_6           ((uint32_t)6U) /*!< Sector Number 6   */\r\n#define FLASH_SECTOR_7           ((uint32_t)7U) /*!< Sector Number 7   */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup FLASH_Exported_Macros FLASH Exported Macros\r\n  * @{\r\n  */\r\n/**\r\n  * @brief  Set the FLASH Latency.\r\n  * @param  __LATENCY__: FLASH Latency                   \r\n  *         The value of this parameter depend on device used within the same series\r\n  * @retval none\r\n  */\r\n#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \\\r\n                  MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))\r\n\r\n/**\r\n  * @brief  Get the FLASH Latency.\r\n  * @retval FLASH Latency                   \r\n  *          The value of this parameter depend on device used within the same series\r\n  */ \r\n#define __HAL_FLASH_GET_LATENCY()     (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))\r\n\r\n/**\r\n  * @brief  Enable the FLASH prefetch buffer.\r\n  * @retval none\r\n  */ \r\n#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE()  (FLASH->ACR |= FLASH_ACR_PRFTEN)\r\n\r\n/**\r\n  * @brief  Disable the FLASH prefetch buffer.\r\n  * @retval none\r\n  */ \r\n#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE()   (FLASH->ACR &= (~FLASH_ACR_PRFTEN))\r\n\r\n/**\r\n  * @brief  Enable the FLASH Adaptive Real-Time memory accelerator.\r\n  * @note   The ART accelerator is available only for flash access on ITCM interface.\r\n  * @retval none\r\n  */ \r\n#define __HAL_FLASH_ART_ENABLE()  SET_BIT(FLASH->ACR, FLASH_ACR_ARTEN)\r\n\r\n/**\r\n  * @brief  Disable the FLASH Adaptive Real-Time memory accelerator.\r\n  * @retval none\r\n  */ \r\n#define __HAL_FLASH_ART_DISABLE()   CLEAR_BIT(FLASH->ACR, FLASH_ACR_ARTEN)\r\n\r\n/**\r\n  * @brief  Resets the FLASH Adaptive Real-Time memory accelerator.\r\n  * @note   This function must be used only when the Adaptive Real-Time memory accelerator\r\n  *         is disabled.  \r\n  * @retval None\r\n  */\r\n#define __HAL_FLASH_ART_RESET()  (FLASH->ACR |= FLASH_ACR_ARTRST)\r\n\r\n/**\r\n  * @brief  Enable the specified FLASH interrupt.\r\n  * @param  __INTERRUPT__ : FLASH interrupt \r\n  *         This parameter can be any combination of the following values:\r\n  *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt\r\n  *     @arg FLASH_IT_ERR: Error Interrupt    \r\n  * @retval none\r\n  */  \r\n#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)  (FLASH->CR |= (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disable the specified FLASH interrupt.\r\n  * @param  __INTERRUPT__ : FLASH interrupt \r\n  *         This parameter can be any combination of the following values:\r\n  *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt\r\n  *     @arg FLASH_IT_ERR: Error Interrupt    \r\n  * @retval none\r\n  */  \r\n#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)  (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Get the specified FLASH flag status. \r\n  * @param  __FLAG__: specifies the FLASH flag to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg FLASH_FLAG_EOP   : FLASH End of Operation flag \r\n  *            @arg FLASH_FLAG_OPERR : FLASH operation Error flag \r\n  *            @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag \r\n  *            @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag\r\n  *            @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag\r\n  *            @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag \r\n  *            @arg FLASH_FLAG_BSY   : FLASH Busy flag\r\n  * @retval The new state of __FLAG__ (SET or RESET).\r\n  */\r\n#define __HAL_FLASH_GET_FLAG(__FLAG__)   ((FLASH->SR & (__FLAG__)))\r\n\r\n/**\r\n  * @brief  Clear the specified FLASH flag.\r\n  * @param  __FLAG__: specifies the FLASH flags to clear.\r\n  *          This parameter can be any combination of the following values:\r\n  *            @arg FLASH_FLAG_EOP   : FLASH End of Operation flag \r\n  *            @arg FLASH_FLAG_OPERR : FLASH operation Error flag \r\n  *            @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag \r\n  *            @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag \r\n  *            @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag\r\n  *            @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag    \r\n  * @retval none\r\n  */\r\n#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)   (FLASH->SR = (__FLAG__))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Include FLASH HAL Extension module */\r\n#include \"stm32f7xx_hal_flash_ex.h\"\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup FLASH_Exported_Functions\r\n  * @{\r\n  */\r\n/** @addtogroup FLASH_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n/* Program operation functions  ***********************************************/\r\nHAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);\r\nHAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);\r\n/* FLASH IRQ handler method */\r\nvoid HAL_FLASH_IRQHandler(void);\r\n/* Callbacks in non blocking modes */ \r\nvoid HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);\r\nvoid HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup FLASH_Exported_Functions_Group2\r\n  * @{\r\n  */\r\n/* Peripheral Control functions  **********************************************/\r\nHAL_StatusTypeDef HAL_FLASH_Unlock(void);\r\nHAL_StatusTypeDef HAL_FLASH_Lock(void);\r\nHAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);\r\nHAL_StatusTypeDef HAL_FLASH_OB_Lock(void);\r\n/* Option bytes control */\r\nHAL_StatusTypeDef HAL_FLASH_OB_Launch(void);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup FLASH_Exported_Functions_Group3\r\n  * @{\r\n  */\r\n/* Peripheral State functions  ************************************************/\r\nuint32_t HAL_FLASH_GetError(void);\r\nHAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @defgroup FLASH_Private_Variables FLASH Private Variables\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup FLASH_Private_Constants FLASH Private Constants\r\n  * @{\r\n  */\r\n\r\n/** \r\n  * @brief   OPTCR register byte 1 (Bits[15:8]) base address  \r\n  */ \r\n#define OPTCR_BYTE1_ADDRESS         ((uint32_t)0x40023C15)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup FLASH_Private_Macros FLASH Private Macros\r\n  * @{\r\n  */\r\n\r\n/** @defgroup FLASH_IS_FLASH_Definitions FLASH Private macros to check input parameters\r\n  * @{\r\n  */\r\n#define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \\\r\n                                    ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \\\r\n                                    ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \\\r\n                                    ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))  \r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup FLASH_Private_Functions FLASH Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_FLASH_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_flash_ex.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of FLASH HAL Extension module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_FLASH_EX_H\r\n#define __STM32F7xx_HAL_FLASH_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup FLASHEx\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/ \r\n/** @defgroup FLASHEx_Exported_Types FLASH Exported Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  FLASH Erase structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t TypeErase;   /*!< Mass erase or sector Erase.\r\n                             This parameter can be a value of @ref FLASHEx_Type_Erase */\r\n\r\n#if defined (FLASH_OPTCR_nDBANK)  \r\n  uint32_t Banks;       /*!< Select banks to erase when Mass erase is enabled.\r\n                             This parameter must be a value of @ref FLASHEx_Banks */\r\n#endif /* FLASH_OPTCR_nDBANK */  \r\n  \r\n  uint32_t Sector;      /*!< Initial FLASH sector to erase when Mass erase is disabled\r\n                             This parameter must be a value of @ref FLASHEx_Sectors */\r\n\r\n  uint32_t NbSectors;   /*!< Number of sectors to be erased.\r\n                             This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/\r\n\r\n  uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism\r\n                             This parameter must be a value of @ref FLASHEx_Voltage_Range */\r\n\r\n} FLASH_EraseInitTypeDef;\r\n\r\n/**\r\n  * @brief  FLASH Option Bytes Program structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t OptionType;   /*!< Option byte to be configured.\r\n                              This parameter can be a value of @ref FLASHEx_Option_Type */\r\n\r\n  uint32_t WRPState;     /*!< Write protection activation or deactivation.\r\n                              This parameter can be a value of @ref FLASHEx_WRP_State */\r\n\r\n  uint32_t WRPSector;    /*!< Specifies the sector(s) to be write protected.\r\n                              The value of this parameter depend on device used within the same series */\r\n\r\n  uint32_t RDPLevel;     /*!< Set the read protection level.\r\n                              This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */\r\n\r\n  uint32_t BORLevel;     /*!< Set the BOR Level.\r\n                              This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */\r\n\r\n  uint32_t USERConfig;   /*!< Program the FLASH User Option Byte: WWDG_SW / IWDG_SW / RST_STOP / RST_STDBY / \r\n                              IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / nDBANK / nDBOOT.\r\n                              nDBANK / nDBOOT are only available for STM32F76xxx/STM32F77xxx devices */\r\n \r\n  uint32_t BootAddr0;    /*!< Boot base address when Boot pin = 0.\r\n                              This parameter can be a value of @ref FLASHEx_Boot_Address */\r\n\r\n  uint32_t BootAddr1;    /*!< Boot base address when Boot pin = 1.\r\n                              This parameter can be a value of @ref FLASHEx_Boot_Address */\r\n\r\n} FLASH_OBProgramInitTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup FLASHEx_Type_Erase FLASH Type Erase\r\n  * @{\r\n  */ \r\n#define FLASH_TYPEERASE_SECTORS         ((uint32_t)0x00U)  /*!< Sectors erase only          */\r\n#define FLASH_TYPEERASE_MASSERASE       ((uint32_t)0x01U)  /*!< Flash Mass erase activation */\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range\r\n  * @{\r\n  */ \r\n#define FLASH_VOLTAGE_RANGE_1        ((uint32_t)0x00U)  /*!< Device operating range: 1.8V to 2.1V                */\r\n#define FLASH_VOLTAGE_RANGE_2        ((uint32_t)0x01U)  /*!< Device operating range: 2.1V to 2.7V                */\r\n#define FLASH_VOLTAGE_RANGE_3        ((uint32_t)0x02U)  /*!< Device operating range: 2.7V to 3.6V                */\r\n#define FLASH_VOLTAGE_RANGE_4        ((uint32_t)0x03U)  /*!< Device operating range: 2.7V to 3.6V + External Vpp */\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup FLASHEx_WRP_State FLASH WRP State\r\n  * @{\r\n  */ \r\n#define OB_WRPSTATE_DISABLE       ((uint32_t)0x00U)  /*!< Disable the write protection of the desired bank 1 sectors */\r\n#define OB_WRPSTATE_ENABLE        ((uint32_t)0x01U)  /*!< Enable the write protection of the desired bank 1 sectors  */\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup FLASHEx_Option_Type FLASH Option Type\r\n  * @{\r\n  */ \r\n#define OPTIONBYTE_WRP         ((uint32_t)0x01U)  /*!< WRP option byte configuration  */\r\n#define OPTIONBYTE_RDP         ((uint32_t)0x02U)  /*!< RDP option byte configuration  */\r\n#define OPTIONBYTE_USER        ((uint32_t)0x04U)  /*!< USER option byte configuration */\r\n#define OPTIONBYTE_BOR         ((uint32_t)0x08U)  /*!< BOR option byte configuration  */\r\n#define OPTIONBYTE_BOOTADDR_0  ((uint32_t)0x10U)  /*!< Boot 0 Address configuration   */\r\n#define OPTIONBYTE_BOOTADDR_1  ((uint32_t)0x20U)  /*!< Boot 1 Address configuration   */\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection\r\n  * @{\r\n  */\r\n#define OB_RDP_LEVEL_0       ((uint8_t)0xAAU)\r\n#define OB_RDP_LEVEL_1       ((uint8_t)0x55U)\r\n#define OB_RDP_LEVEL_2       ((uint8_t)0xCCU)   /*!< Warning: When enabling read protection level 2 \r\n                                                  it s no more possible to go back to level 1 or 0 */\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog\r\n  * @{\r\n  */ \r\n#define OB_WWDG_SW           ((uint32_t)0x10U)  /*!< Software WWDG selected */\r\n#define OB_WWDG_HW           ((uint32_t)0x00U)  /*!< Hardware WWDG selected */\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n\r\n/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog\r\n  * @{\r\n  */ \r\n#define OB_IWDG_SW           ((uint32_t)0x20U)  /*!< Software IWDG selected */\r\n#define OB_IWDG_HW           ((uint32_t)0x00U)  /*!< Hardware IWDG selected */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP\r\n  * @{\r\n  */ \r\n#define OB_STOP_NO_RST       ((uint32_t)0x40U) /*!< No reset generated when entering in STOP */\r\n#define OB_STOP_RST          ((uint32_t)0x00U) /*!< Reset generated when entering in STOP    */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY\r\n  * @{\r\n  */                               \r\n#define OB_STDBY_NO_RST      ((uint32_t)0x80U) /*!< No reset generated when entering in STANDBY */\r\n#define OB_STDBY_RST         ((uint32_t)0x00U) /*!< Reset generated when entering in STANDBY    */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP\r\n  * @{\r\n  */\r\n#define OB_IWDG_STOP_FREEZE      ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STOP mode */\r\n#define OB_IWDG_STOP_ACTIVE      ((uint32_t)0x80000000U) /*!< IWDG counter active in STOP mode */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY\r\n  * @{\r\n  */\r\n#define OB_IWDG_STDBY_FREEZE      ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STANDBY mode */\r\n#define OB_IWDG_STDBY_ACTIVE      ((uint32_t)0x40000000U) /*!< IWDG counter active in STANDBY mode */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level\r\n  * @{\r\n  */\r\n#define OB_BOR_LEVEL3          ((uint32_t)0x00U)  /*!< Supply voltage ranges from 2.70 to 3.60 V */\r\n#define OB_BOR_LEVEL2          ((uint32_t)0x04U)  /*!< Supply voltage ranges from 2.40 to 2.70 V */\r\n#define OB_BOR_LEVEL1          ((uint32_t)0x08U)  /*!< Supply voltage ranges from 2.10 to 2.40 V */\r\n#define OB_BOR_OFF             ((uint32_t)0x0CU)  /*!< Supply voltage ranges from 1.62 to 2.10 V */\r\n/**\r\n  * @}\r\n  */\r\n\r\n#if defined (FLASH_OPTCR_nDBOOT)\r\n/** @defgroup FLASHEx_Option_Bytes_nDBOOT FLASH Option Bytes nDBOOT\r\n  * @{\r\n  */                               \r\n#define OB_DUAL_BOOT_DISABLE      ((uint32_t)0x10000000U) /* !< Dual Boot disable. Boot according to boot address option */\r\n#define OB_DUAL_BOOT_ENABLE       ((uint32_t)0x00000000U) /* !< Dual Boot enable. Boot always from system memory if boot address in flash \r\n                                                              (Dual bank Boot mode), or RAM if Boot address option in RAM    */\r\n/**\r\n  * @}\r\n  */  \r\n#endif /* FLASH_OPTCR_nDBOOT */\r\n\r\n#if defined (FLASH_OPTCR_nDBANK)\r\n/** @defgroup FLASHEx_Option_Bytes_nDBank FLASH Single Bank or Dual Bank\r\n  * @{\r\n  */\r\n#define OB_NDBANK_SINGLE_BANK      ((uint32_t)0x20000000U) /*!< NDBANK bit is set : Single Bank mode */\r\n#define OB_NDBANK_DUAL_BANK        ((uint32_t)0x00000000U) /*!< NDBANK bit is reset : Dual Bank mode */\r\n/**\r\n  * @}\r\n  */\r\n#endif /* FLASH_OPTCR_nDBANK */\r\n\r\n/** @defgroup FLASHEx_Boot_Address FLASH Boot Address\r\n  * @{\r\n  */\r\n#define OB_BOOTADDR_ITCM_RAM         ((uint32_t)0x0000U)  /*!< Boot from ITCM RAM (0x00000000)                 */\r\n#define OB_BOOTADDR_SYSTEM           ((uint32_t)0x0040U)  /*!< Boot from System memory bootloader (0x00100000) */\r\n#define OB_BOOTADDR_ITCM_FLASH       ((uint32_t)0x0080U)  /*!< Boot from Flash on ITCM interface (0x00200000)  */\r\n#define OB_BOOTADDR_AXIM_FLASH       ((uint32_t)0x2000U)  /*!< Boot from Flash on AXIM interface (0x08000000)  */\r\n#define OB_BOOTADDR_DTCM_RAM         ((uint32_t)0x8000U)  /*!< Boot from DTCM RAM (0x20000000)                 */\r\n#define OB_BOOTADDR_SRAM1            ((uint32_t)0x8004U)  /*!< Boot from SRAM1 (0x20010000)                    */\r\n#define OB_BOOTADDR_SRAM2            ((uint32_t)0x8013U)  /*!< Boot from SRAM2 (0x2004C000)                    */\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup FLASH_Latency FLASH Latency\r\n  * @{\r\n  */\r\n#define FLASH_LATENCY_0                FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero Latency cycle      */\r\n#define FLASH_LATENCY_1                FLASH_ACR_LATENCY_1WS   /*!< FLASH One Latency cycle       */\r\n#define FLASH_LATENCY_2                FLASH_ACR_LATENCY_2WS   /*!< FLASH Two Latency cycles      */\r\n#define FLASH_LATENCY_3                FLASH_ACR_LATENCY_3WS   /*!< FLASH Three Latency cycles    */\r\n#define FLASH_LATENCY_4                FLASH_ACR_LATENCY_4WS   /*!< FLASH Four Latency cycles     */\r\n#define FLASH_LATENCY_5                FLASH_ACR_LATENCY_5WS   /*!< FLASH Five Latency cycles     */\r\n#define FLASH_LATENCY_6                FLASH_ACR_LATENCY_6WS   /*!< FLASH Six Latency cycles      */\r\n#define FLASH_LATENCY_7                FLASH_ACR_LATENCY_7WS   /*!< FLASH Seven Latency cycles    */\r\n#define FLASH_LATENCY_8                FLASH_ACR_LATENCY_8WS   /*!< FLASH Eight Latency cycles    */\r\n#define FLASH_LATENCY_9                FLASH_ACR_LATENCY_9WS   /*!< FLASH Nine Latency cycles     */\r\n#define FLASH_LATENCY_10               FLASH_ACR_LATENCY_10WS  /*!< FLASH Ten Latency cycles      */\r\n#define FLASH_LATENCY_11               FLASH_ACR_LATENCY_11WS  /*!< FLASH Eleven Latency cycles   */\r\n#define FLASH_LATENCY_12               FLASH_ACR_LATENCY_12WS  /*!< FLASH Twelve Latency cycles   */\r\n#define FLASH_LATENCY_13               FLASH_ACR_LATENCY_13WS  /*!< FLASH Thirteen Latency cycles */\r\n#define FLASH_LATENCY_14               FLASH_ACR_LATENCY_14WS  /*!< FLASH Fourteen Latency cycles */\r\n#define FLASH_LATENCY_15               FLASH_ACR_LATENCY_15WS  /*!< FLASH Fifteen Latency cycles  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n#if defined (FLASH_OPTCR_nDBANK)\r\n/** @defgroup FLASHEx_Banks FLASH Banks\r\n  * @{\r\n  */\r\n#define FLASH_BANK_1                       ((uint32_t)0x01U)                          /*!< Bank 1   */\r\n#define FLASH_BANK_2                       ((uint32_t)0x02U)                          /*!< Bank 2   */\r\n#define FLASH_BANK_BOTH                    ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2  */\r\n/**\r\n  * @}\r\n  */\r\n#endif /* FLASH_OPTCR_nDBANK */\r\n\r\n/** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit\r\n  * @{\r\n  */\r\n#if defined (FLASH_OPTCR_nDBANK)\r\n#define FLASH_MER_BIT     (FLASH_CR_MER1 | FLASH_CR_MER2) /*!< 2 MER bits */\r\n#else\r\n#define FLASH_MER_BIT     (FLASH_CR_MER) /*!< only 1 MER bit */\r\n#endif /* FLASH_OPTCR_nDBANK */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FLASHEx_Sectors FLASH Sectors\r\n  * @{\r\n  */\r\n#if (FLASH_SECTOR_TOTAL == 24)\r\n#define FLASH_SECTOR_8     ((uint32_t)8U)  /*!< Sector Number 8   */\r\n#define FLASH_SECTOR_9     ((uint32_t)9U)  /*!< Sector Number 9   */\r\n#define FLASH_SECTOR_10    ((uint32_t)10U) /*!< Sector Number 10  */\r\n#define FLASH_SECTOR_11    ((uint32_t)11U) /*!< Sector Number 11  */\r\n#define FLASH_SECTOR_12    ((uint32_t)12U) /*!< Sector Number 12  */\r\n#define FLASH_SECTOR_13    ((uint32_t)13U) /*!< Sector Number 13  */\r\n#define FLASH_SECTOR_14    ((uint32_t)14U) /*!< Sector Number 14  */\r\n#define FLASH_SECTOR_15    ((uint32_t)15U) /*!< Sector Number 15  */\r\n#define FLASH_SECTOR_16    ((uint32_t)16U) /*!< Sector Number 16  */\r\n#define FLASH_SECTOR_17    ((uint32_t)17U) /*!< Sector Number 17  */\r\n#define FLASH_SECTOR_18    ((uint32_t)18U) /*!< Sector Number 18  */\r\n#define FLASH_SECTOR_19    ((uint32_t)19U) /*!< Sector Number 19  */\r\n#define FLASH_SECTOR_20    ((uint32_t)20U) /*!< Sector Number 20  */\r\n#define FLASH_SECTOR_21    ((uint32_t)21U) /*!< Sector Number 21  */\r\n#define FLASH_SECTOR_22    ((uint32_t)22U) /*!< Sector Number 22  */\r\n#define FLASH_SECTOR_23    ((uint32_t)23U) /*!< Sector Number 23  */\r\n#endif /* FLASH_SECTOR_TOTAL == 24 */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n#if (FLASH_SECTOR_TOTAL == 24)\r\n/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection\r\n  * @note For Single Bank mode, use OB_WRP_SECTOR_x defines: In fact, in FLASH_OPTCR register,\r\n  *       nWRP[11:0] bits contain the value of the write-protection option bytes for sectors 0 to 11.\r\n  *       For Dual Bank mode, use OB_WRP_DB_SECTOR_x defines: In fact, in FLASH_OPTCR register,\r\n  *       nWRP[11:0] bits are divided on two groups, one group dedicated for bank 1 and \r\n  *       a second one dedicated for bank 2 (nWRP[i] activates Write protection on sector 2*i and 2*i+1).\r\n  *       This behavior is applicable only for STM32F76xxx / STM32F77xxx devices.\r\n  * @{\r\n  */\r\n/* Single Bank Sectors */\r\n#define OB_WRP_SECTOR_0       ((uint32_t)0x00010000U) /*!< Write protection of Single Bank Sector0   */\r\n#define OB_WRP_SECTOR_1       ((uint32_t)0x00020000U) /*!< Write protection of Single Bank Sector1   */\r\n#define OB_WRP_SECTOR_2       ((uint32_t)0x00040000U) /*!< Write protection of Single Bank Sector2   */\r\n#define OB_WRP_SECTOR_3       ((uint32_t)0x00080000U) /*!< Write protection of Single Bank Sector3   */\r\n#define OB_WRP_SECTOR_4       ((uint32_t)0x00100000U) /*!< Write protection of Single Bank Sector4   */\r\n#define OB_WRP_SECTOR_5       ((uint32_t)0x00200000U) /*!< Write protection of Single Bank Sector5   */\r\n#define OB_WRP_SECTOR_6       ((uint32_t)0x00400000U) /*!< Write protection of Single Bank Sector6   */\r\n#define OB_WRP_SECTOR_7       ((uint32_t)0x00800000U) /*!< Write protection of Single Bank Sector7   */\r\n#define OB_WRP_SECTOR_8       ((uint32_t)0x01000000U) /*!< Write protection of Single Bank Sector8   */\r\n#define OB_WRP_SECTOR_9       ((uint32_t)0x02000000U) /*!< Write protection of Single Bank Sector9   */\r\n#define OB_WRP_SECTOR_10      ((uint32_t)0x04000000U) /*!< Write protection of Single Bank Sector10  */\r\n#define OB_WRP_SECTOR_11      ((uint32_t)0x08000000U) /*!< Write protection of Single Bank Sector11  */   \r\n#define OB_WRP_SECTOR_All     ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Single Bank Flash */\r\n\r\n/* Dual Bank Sectors */\r\n#define OB_WRP_DB_SECTOR_0    ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector0     */\r\n#define OB_WRP_DB_SECTOR_1    ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector1     */\r\n#define OB_WRP_DB_SECTOR_2    ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector2     */\r\n#define OB_WRP_DB_SECTOR_3    ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector3     */\r\n#define OB_WRP_DB_SECTOR_4    ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector4     */\r\n#define OB_WRP_DB_SECTOR_5    ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector5     */\r\n#define OB_WRP_DB_SECTOR_6    ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector6     */\r\n#define OB_WRP_DB_SECTOR_7    ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector7     */\r\n#define OB_WRP_DB_SECTOR_8    ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector8     */\r\n#define OB_WRP_DB_SECTOR_9    ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector9     */\r\n#define OB_WRP_DB_SECTOR_10   ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector10    */\r\n#define OB_WRP_DB_SECTOR_11   ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector11    */    \r\n#define OB_WRP_DB_SECTOR_12   ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector12    */\r\n#define OB_WRP_DB_SECTOR_13   ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector13    */\r\n#define OB_WRP_DB_SECTOR_14   ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector14    */\r\n#define OB_WRP_DB_SECTOR_15   ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector15    */\r\n#define OB_WRP_DB_SECTOR_16   ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector16    */\r\n#define OB_WRP_DB_SECTOR_17   ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector17    */\r\n#define OB_WRP_DB_SECTOR_18   ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector18    */\r\n#define OB_WRP_DB_SECTOR_19   ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector19    */\r\n#define OB_WRP_DB_SECTOR_20   ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector20    */\r\n#define OB_WRP_DB_SECTOR_21   ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector21    */\r\n#define OB_WRP_DB_SECTOR_22   ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector22    */\r\n#define OB_WRP_DB_SECTOR_23   ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector23    */\r\n#define OB_WRP_DB_SECTOR_All  ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Dual Bank Flash */\r\n/**\r\n  * @}\r\n  */\r\n#endif /* FLASH_SECTOR_TOTAL == 24 */\r\n    \r\n#if (FLASH_SECTOR_TOTAL == 8)\r\n/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection\r\n  * @{\r\n  */\r\n#define OB_WRP_SECTOR_0       ((uint32_t)0x00010000U) /*!< Write protection of Sector0     */\r\n#define OB_WRP_SECTOR_1       ((uint32_t)0x00020000U) /*!< Write protection of Sector1     */\r\n#define OB_WRP_SECTOR_2       ((uint32_t)0x00040000U) /*!< Write protection of Sector2     */\r\n#define OB_WRP_SECTOR_3       ((uint32_t)0x00080000U) /*!< Write protection of Sector3     */\r\n#define OB_WRP_SECTOR_4       ((uint32_t)0x00100000U) /*!< Write protection of Sector4     */\r\n#define OB_WRP_SECTOR_5       ((uint32_t)0x00200000U) /*!< Write protection of Sector5     */\r\n#define OB_WRP_SECTOR_6       ((uint32_t)0x00400000U) /*!< Write protection of Sector6     */\r\n#define OB_WRP_SECTOR_7       ((uint32_t)0x00800000U) /*!< Write protection of Sector7     */\r\n#define OB_WRP_SECTOR_All     ((uint32_t)0x00FF0000U) /*!< Write protection of all Sectors */\r\n/**\r\n  * @}\r\n  */\r\n#endif /* FLASH_SECTOR_TOTAL == 8 */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup FLASH_Exported_Macros FLASH Exported Macros\r\n  * @{\r\n  */\r\n/**\r\n  * @brief  Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1)\r\n  * @note   Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14].\r\n  * @param  __ADDRESS__: FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB)\r\n  * @retval The FLASH Boot Base Adress\r\n  */\r\n#define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14)\r\n /**\r\n  * @}\r\n  */\r\n                    \r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup FLASHEx_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup FLASHEx_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n/* Extension Program operation functions  *************************************/\r\nHAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);\r\nHAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);\r\nHAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);\r\nvoid              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup FLASHEx_Private_Macros FLASH Private Macros\r\n  * @{\r\n  */\r\n\r\n/** @defgroup FLASHEx_IS_FLASH_Definitions FLASH Private macros to check input parameters\r\n  * @{\r\n  */\r\n\r\n#define IS_FLASH_TYPEERASE(VALUE)(((VALUE) == FLASH_TYPEERASE_SECTORS) || \\\r\n                                  ((VALUE) == FLASH_TYPEERASE_MASSERASE))  \r\n\r\n#define IS_VOLTAGERANGE(RANGE)(((RANGE) == FLASH_VOLTAGE_RANGE_1) || \\\r\n                               ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \\\r\n                               ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \\\r\n                               ((RANGE) == FLASH_VOLTAGE_RANGE_4))  \r\n\r\n#define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \\\r\n                           ((VALUE) == OB_WRPSTATE_ENABLE))  \r\n\r\n#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP        | OPTIONBYTE_USER |\\\r\n                                          OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1)))\r\n\r\n#define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013)\r\n\r\n#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0)   ||\\\r\n                                ((LEVEL) == OB_RDP_LEVEL_1)   ||\\\r\n                                ((LEVEL) == OB_RDP_LEVEL_2))\r\n\r\n#define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))\r\n\r\n#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))\r\n\r\n#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))\r\n\r\n#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))\r\n\r\n#define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))\r\n\r\n#define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))\r\n\r\n#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\\\r\n                                ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))\r\n\r\n#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0)  || \\\r\n                                   ((LATENCY) == FLASH_LATENCY_1)  || \\\r\n                                   ((LATENCY) == FLASH_LATENCY_2)  || \\\r\n                                   ((LATENCY) == FLASH_LATENCY_3)  || \\\r\n                                   ((LATENCY) == FLASH_LATENCY_4)  || \\\r\n                                   ((LATENCY) == FLASH_LATENCY_5)  || \\\r\n                                   ((LATENCY) == FLASH_LATENCY_6)  || \\\r\n                                   ((LATENCY) == FLASH_LATENCY_7)  || \\\r\n                                   ((LATENCY) == FLASH_LATENCY_8)  || \\\r\n                                   ((LATENCY) == FLASH_LATENCY_9)  || \\\r\n                                   ((LATENCY) == FLASH_LATENCY_10) || \\\r\n                                   ((LATENCY) == FLASH_LATENCY_11) || \\\r\n                                   ((LATENCY) == FLASH_LATENCY_12) || \\\r\n                                   ((LATENCY) == FLASH_LATENCY_13) || \\\r\n                                   ((LATENCY) == FLASH_LATENCY_14) || \\\r\n                                   ((LATENCY) == FLASH_LATENCY_15))\r\n\r\n#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END))\r\n\r\n#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))\r\n\r\n#if (FLASH_SECTOR_TOTAL == 8)\r\n#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\\\r\n                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\\\r\n                                 ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\\\r\n                                 ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7))\r\n\r\n#define IS_OB_WRP_SECTOR(SECTOR)  ((((SECTOR) & (uint32_t)0xFF00FFFF) == 0x00000000U) && ((SECTOR) != 0x00000000U))\r\n#endif /* FLASH_SECTOR_TOTAL == 8 */\r\n\r\n#if (FLASH_SECTOR_TOTAL == 24)\r\n#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\\\r\n                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\\\r\n                                 ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\\\r\n                                 ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7)   ||\\\r\n                                 ((SECTOR) == FLASH_SECTOR_8)   || ((SECTOR) == FLASH_SECTOR_9)   ||\\\r\n                                 ((SECTOR) == FLASH_SECTOR_10)  || ((SECTOR) == FLASH_SECTOR_11)  ||\\\r\n                                 ((SECTOR) == FLASH_SECTOR_12)  || ((SECTOR) == FLASH_SECTOR_13)  ||\\\r\n                                 ((SECTOR) == FLASH_SECTOR_14)  || ((SECTOR) == FLASH_SECTOR_15)  ||\\\r\n                                 ((SECTOR) == FLASH_SECTOR_16)  || ((SECTOR) == FLASH_SECTOR_17)  ||\\\r\n                                 ((SECTOR) == FLASH_SECTOR_18)  || ((SECTOR) == FLASH_SECTOR_19)  ||\\\r\n                                 ((SECTOR) == FLASH_SECTOR_20)  || ((SECTOR) == FLASH_SECTOR_21)  ||\\\r\n                                 ((SECTOR) == FLASH_SECTOR_22)  || ((SECTOR) == FLASH_SECTOR_23))\r\n\r\n#define IS_OB_WRP_SECTOR(SECTOR)  ((((SECTOR) & (uint32_t)0xF000FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U))\r\n#endif /* FLASH_SECTOR_TOTAL == 24 */\r\n\r\n#if defined (FLASH_OPTCR_nDBANK)\r\n#define IS_OB_NDBANK(VALUE)        (((VALUE) == OB_NDBANK_SINGLE_BANK) || \\\r\n                                    ((VALUE) == OB_NDBANK_DUAL_BANK))\r\n\r\n#define IS_FLASH_BANK(BANK)        (((BANK) == FLASH_BANK_1)  || \\\r\n                                    ((BANK) == FLASH_BANK_2)  || \\\r\n                                    ((BANK) == FLASH_BANK_BOTH))\r\n#endif /* FLASH_OPTCR_nDBANK */\r\n\r\n#if defined (FLASH_OPTCR_nDBOOT)\r\n#define IS_OB_NDBOOT(VALUE)        (((VALUE) == OB_DUAL_BOOT_DISABLE) || \\\r\n                                    ((VALUE) == OB_DUAL_BOOT_ENABLE))\r\n#endif /* FLASH_OPTCR_nDBOOT */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup FLASHEx_Private_Functions FLASH Private Functions\r\n  * @{\r\n  */\r\nvoid FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_FLASH_EX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_gpio.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of GPIO HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_GPIO_H\r\n#define __STM32F7xx_HAL_GPIO_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup GPIO\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup GPIO_Exported_Types GPIO Exported Types\r\n  * @{\r\n  */\r\n\r\n/** \r\n  * @brief GPIO Init structure definition  \r\n  */ \r\ntypedef struct\r\n{\r\n  uint32_t Pin;       /*!< Specifies the GPIO pins to be configured.\r\n                           This parameter can be any value of @ref GPIO_pins_define */\r\n\r\n  uint32_t Mode;      /*!< Specifies the operating mode for the selected pins.\r\n                           This parameter can be a value of @ref GPIO_mode_define */\r\n\r\n  uint32_t Pull;      /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.\r\n                           This parameter can be a value of @ref GPIO_pull_define */\r\n\r\n  uint32_t Speed;     /*!< Specifies the speed for the selected pins.\r\n                           This parameter can be a value of @ref GPIO_speed_define */\r\n\r\n  uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins. \r\n                            This parameter can be a value of @ref GPIO_Alternate_function_selection */\r\n}GPIO_InitTypeDef;\r\n\r\n/** \r\n  * @brief  GPIO Bit SET and Bit RESET enumeration \r\n  */\r\ntypedef enum\r\n{\r\n  GPIO_PIN_RESET = 0,\r\n  GPIO_PIN_SET\r\n}GPIO_PinState;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup GPIO_Exported_Constants GPIO Exported Constants\r\n  * @{\r\n  */ \r\n\r\n/** @defgroup GPIO_pins_define GPIO pins define\r\n  * @{\r\n  */\r\n#define GPIO_PIN_0                 ((uint16_t)0x0001U)  /* Pin 0 selected    */\r\n#define GPIO_PIN_1                 ((uint16_t)0x0002U)  /* Pin 1 selected    */\r\n#define GPIO_PIN_2                 ((uint16_t)0x0004U)  /* Pin 2 selected    */\r\n#define GPIO_PIN_3                 ((uint16_t)0x0008U)  /* Pin 3 selected    */\r\n#define GPIO_PIN_4                 ((uint16_t)0x0010U)  /* Pin 4 selected    */\r\n#define GPIO_PIN_5                 ((uint16_t)0x0020U)  /* Pin 5 selected    */\r\n#define GPIO_PIN_6                 ((uint16_t)0x0040U)  /* Pin 6 selected    */\r\n#define GPIO_PIN_7                 ((uint16_t)0x0080U)  /* Pin 7 selected    */\r\n#define GPIO_PIN_8                 ((uint16_t)0x0100U)  /* Pin 8 selected    */\r\n#define GPIO_PIN_9                 ((uint16_t)0x0200U)  /* Pin 9 selected    */\r\n#define GPIO_PIN_10                ((uint16_t)0x0400U)  /* Pin 10 selected   */\r\n#define GPIO_PIN_11                ((uint16_t)0x0800U)  /* Pin 11 selected   */\r\n#define GPIO_PIN_12                ((uint16_t)0x1000U)  /* Pin 12 selected   */\r\n#define GPIO_PIN_13                ((uint16_t)0x2000U)  /* Pin 13 selected   */\r\n#define GPIO_PIN_14                ((uint16_t)0x4000U)  /* Pin 14 selected   */\r\n#define GPIO_PIN_15                ((uint16_t)0x8000U)  /* Pin 15 selected   */\r\n#define GPIO_PIN_All               ((uint16_t)0xFFFFU)  /* All pins selected */\r\n\r\n#define GPIO_PIN_MASK              ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup GPIO_mode_define GPIO mode define\r\n  * @brief GPIO Configuration Mode \r\n  *        Elements values convention: 0xX0yz00YZ\r\n  *           - X  : GPIO mode or EXTI Mode\r\n  *           - y  : External IT or Event trigger detection \r\n  *           - z  : IO configuration on External IT or Event\r\n  *           - Y  : Output type (Push Pull or Open Drain)\r\n  *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)\r\n  * @{\r\n  */ \r\n#define  GPIO_MODE_INPUT                        ((uint32_t)0x00000000U)   /*!< Input Floating Mode                   */\r\n#define  GPIO_MODE_OUTPUT_PP                    ((uint32_t)0x00000001U)   /*!< Output Push Pull Mode                 */\r\n#define  GPIO_MODE_OUTPUT_OD                    ((uint32_t)0x00000011U)   /*!< Output Open Drain Mode                */\r\n#define  GPIO_MODE_AF_PP                        ((uint32_t)0x00000002U)   /*!< Alternate Function Push Pull Mode     */\r\n#define  GPIO_MODE_AF_OD                        ((uint32_t)0x00000012U)   /*!< Alternate Function Open Drain Mode    */\r\n\r\n#define  GPIO_MODE_ANALOG                       ((uint32_t)0x00000003U)   /*!< Analog Mode  */\r\n    \r\n#define  GPIO_MODE_IT_RISING                    ((uint32_t)0x10110000U)   /*!< External Interrupt Mode with Rising edge trigger detection          */\r\n#define  GPIO_MODE_IT_FALLING                   ((uint32_t)0x10210000U)   /*!< External Interrupt Mode with Falling edge trigger detection         */\r\n#define  GPIO_MODE_IT_RISING_FALLING            ((uint32_t)0x10310000U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */\r\n \r\n#define  GPIO_MODE_EVT_RISING                   ((uint32_t)0x10120000U)   /*!< External Event Mode with Rising edge trigger detection               */\r\n#define  GPIO_MODE_EVT_FALLING                  ((uint32_t)0x10220000U)   /*!< External Event Mode with Falling edge trigger detection              */\r\n#define  GPIO_MODE_EVT_RISING_FALLING           ((uint32_t)0x10320000U)   /*!< External Event Mode with Rising/Falling edge trigger detection       */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup GPIO_speed_define  GPIO speed define\r\n  * @brief GPIO Output Maximum frequency\r\n  * @{\r\n  */  \r\n#define  GPIO_SPEED_FREQ_LOW         ((uint32_t)0x00000000U)  /*!< Low speed     */\r\n#define  GPIO_SPEED_FREQ_MEDIUM      ((uint32_t)0x00000001U)  /*!< Medium speed  */\r\n#define  GPIO_SPEED_FREQ_HIGH        ((uint32_t)0x00000002U)  /*!< Fast speed    */\r\n#define  GPIO_SPEED_FREQ_VERY_HIGH   ((uint32_t)0x00000003U)  /*!< High speed    */\r\n/**\r\n  * @}\r\n  */\r\n\r\n /** @defgroup GPIO_pull_define GPIO pull define\r\n   * @brief GPIO Pull-Up or Pull-Down Activation\r\n   * @{\r\n   */  \r\n#define  GPIO_NOPULL        ((uint32_t)0x00000000U)   /*!< No Pull-up or Pull-down activation  */\r\n#define  GPIO_PULLUP        ((uint32_t)0x00000001U)   /*!< Pull-up activation                  */\r\n#define  GPIO_PULLDOWN      ((uint32_t)0x00000002U)   /*!< Pull-down activation                */\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup GPIO_Exported_Macros GPIO Exported Macros\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Checks whether the specified EXTI line flag is set or not.\r\n  * @param  __EXTI_LINE__: specifies the EXTI line flag to check.\r\n  *         This parameter can be GPIO_PIN_x where x can be(0..15)\r\n  * @retval The new state of __EXTI_LINE__ (SET or RESET).\r\n  */\r\n#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))\r\n\r\n/**\r\n  * @brief  Clears the EXTI's line pending flags.\r\n  * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.\r\n  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)\r\n  * @retval None\r\n  */\r\n#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))\r\n\r\n/**\r\n  * @brief  Checks whether the specified EXTI line is asserted or not.\r\n  * @param  __EXTI_LINE__: specifies the EXTI line to check.\r\n  *          This parameter can be GPIO_PIN_x where x can be(0..15)\r\n  * @retval The new state of __EXTI_LINE__ (SET or RESET).\r\n  */\r\n#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))\r\n\r\n/**\r\n  * @brief  Clears the EXTI's line pending bits.\r\n  * @param  __EXTI_LINE__: specifies the EXTI lines to clear.\r\n  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)\r\n  * @retval None\r\n  */\r\n#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))\r\n\r\n/**\r\n  * @brief  Generates a Software interrupt on selected EXTI line.\r\n  * @param  __EXTI_LINE__: specifies the EXTI line to check.\r\n  *          This parameter can be GPIO_PIN_x where x can be(0..15)\r\n  * @retval None\r\n  */\r\n#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Include GPIO HAL Extension module */\r\n#include \"stm32f7xx_hal_gpio_ex.h\"\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup GPIO_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup GPIO_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n/* Initialization and de-initialization functions *****************************/\r\nvoid  HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);\r\nvoid  HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup GPIO_Exported_Functions_Group2\r\n  * @{\r\n  */\r\n/* IO operation functions *****************************************************/\r\nGPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r\nvoid HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);\r\nvoid HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r\nHAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r\nvoid HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);\r\nvoid HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup GPIO_Private_Constants GPIO Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup GPIO_Private_Macros GPIO Private Macros\r\n  * @{\r\n  */\r\n#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))\r\n#define IS_GPIO_PIN(PIN)           (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00)\r\n#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT)              ||\\\r\n                            ((MODE) == GPIO_MODE_OUTPUT_PP)          ||\\\r\n                            ((MODE) == GPIO_MODE_OUTPUT_OD)          ||\\\r\n                            ((MODE) == GPIO_MODE_AF_PP)              ||\\\r\n                            ((MODE) == GPIO_MODE_AF_OD)              ||\\\r\n                            ((MODE) == GPIO_MODE_IT_RISING)          ||\\\r\n                            ((MODE) == GPIO_MODE_IT_FALLING)         ||\\\r\n                            ((MODE) == GPIO_MODE_IT_RISING_FALLING)  ||\\\r\n                            ((MODE) == GPIO_MODE_EVT_RISING)         ||\\\r\n                            ((MODE) == GPIO_MODE_EVT_FALLING)        ||\\\r\n                            ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\\\r\n                            ((MODE) == GPIO_MODE_ANALOG))\r\n#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_LOW)  || ((SPEED) == GPIO_SPEED_MEDIUM) || \\\r\n                              ((SPEED) == GPIO_SPEED_FAST) || ((SPEED) == GPIO_SPEED_HIGH))\r\n#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \\\r\n                            ((PULL) == GPIO_PULLDOWN))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup GPIO_Private_Functions GPIO Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_GPIO_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_gpio_ex.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of GPIO HAL Extension module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_GPIO_EX_H\r\n#define __STM32F7xx_HAL_GPIO_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup GPIOEx GPIOEx\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection\r\n  * @{\r\n  */  \r\n\r\n/** \r\n  * @brief   AF 0 selection  \r\n  */ \r\n#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00U)  /* RTC_50Hz Alternate Function mapping                       */\r\n#define GPIO_AF0_MCO           ((uint8_t)0x00U)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\r\n#define GPIO_AF0_SWJ           ((uint8_t)0x00U)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\r\n#define GPIO_AF0_TRACE         ((uint8_t)0x00U)  /* TRACE Alternate Function mapping                          */\r\n\r\n/** \r\n  * @brief   AF 1 selection  \r\n  */ \r\n#define GPIO_AF1_TIM1          ((uint8_t)0x01U)  /* TIM1 Alternate Function mapping */\r\n#define GPIO_AF1_TIM2          ((uint8_t)0x01U)  /* TIM2 Alternate Function mapping */\r\n#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r\n#define GPIO_AF1_UART5         ((uint8_t)0x01U)  /* UART5 Alternate Function mapping */\r\n#define GPIO_AF1_I2C4          ((uint8_t)0x01U)  /* I2C4 Alternate Function mapping  */   \r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n/** \r\n  * @brief   AF 2 selection  \r\n  */ \r\n#define GPIO_AF2_TIM3          ((uint8_t)0x02U)  /* TIM3 Alternate Function mapping */\r\n#define GPIO_AF2_TIM4          ((uint8_t)0x02U)  /* TIM4 Alternate Function mapping */\r\n#define GPIO_AF2_TIM5          ((uint8_t)0x02U)  /* TIM5 Alternate Function mapping */\r\n\r\n/** \r\n  * @brief   AF 3 selection  \r\n  */ \r\n#define GPIO_AF3_TIM8          ((uint8_t)0x03U)  /* TIM8 Alternate Function mapping  */\r\n#define GPIO_AF3_TIM9          ((uint8_t)0x03U)  /* TIM9 Alternate Function mapping  */\r\n#define GPIO_AF3_TIM10         ((uint8_t)0x03U)  /* TIM10 Alternate Function mapping */\r\n#define GPIO_AF3_TIM11         ((uint8_t)0x03U)  /* TIM11 Alternate Function mapping */\r\n#define GPIO_AF3_LPTIM1        ((uint8_t)0x03U)  /* LPTIM1 Alternate Function mapping */\r\n#define GPIO_AF3_CEC           ((uint8_t)0x03U)  /* CEC Alternate Function mapping */\r\n#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r\n#define GPIO_AF3_DFSDM1         ((uint8_t)0x03U)  /* DFSDM1 Alternate Function mapping */\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n/** \r\n  * @brief   AF 4 selection  \r\n  */ \r\n#define GPIO_AF4_I2C1          ((uint8_t)0x04U)  /* I2C1 Alternate Function mapping */\r\n#define GPIO_AF4_I2C2          ((uint8_t)0x04U)  /* I2C2 Alternate Function mapping */\r\n#define GPIO_AF4_I2C3          ((uint8_t)0x04U)  /* I2C3 Alternate Function mapping */\r\n#define GPIO_AF4_I2C4          ((uint8_t)0x04U)  /* I2C4 Alternate Function mapping */\r\n#define GPIO_AF4_CEC           ((uint8_t)0x04U)  /* CEC Alternate Function mapping */\r\n#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r\n#define GPIO_AF4_USART1        ((uint8_t)0x04)  /* USART1 Alternate Function mapping */\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */   \r\n\r\n/** \r\n  * @brief   AF 5 selection  \r\n  */ \r\n#define GPIO_AF5_SPI1          ((uint8_t)0x05U)  /* SPI1 Alternate Function mapping        */\r\n#define GPIO_AF5_SPI2          ((uint8_t)0x05U)  /* SPI2/I2S2 Alternate Function mapping   */\r\n#define GPIO_AF5_SPI3          ((uint8_t)0x05U)  /* SPI3/I2S3 Alternate Function mapping   */\r\n#define GPIO_AF5_SPI4          ((uint8_t)0x05U)  /* SPI4 Alternate Function mapping        */\r\n#define GPIO_AF5_SPI5          ((uint8_t)0x05U)  /* SPI5 Alternate Function mapping        */\r\n#define GPIO_AF5_SPI6          ((uint8_t)0x05U)  /* SPI6 Alternate Function mapping        */\r\n\r\n/** \r\n  * @brief   AF 6 selection  \r\n  */ \r\n#define GPIO_AF6_SPI3          ((uint8_t)0x06U)  /* SPI3/I2S3 Alternate Function mapping  */\r\n#define GPIO_AF6_SAI1          ((uint8_t)0x06U)  /* SAI1 Alternate Function mapping       */\r\n#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r\n#define GPIO_AF6_UART4         ((uint8_t)0x06U)   /* UART4 Alternate Function mapping     */   \r\n#define GPIO_AF6_DFSDM1        ((uint8_t)0x06U)  /* DFSDM1 Alternate Function mapping     */\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */   \r\n\r\n/** \r\n  * @brief   AF 7 selection  \r\n  */ \r\n#define GPIO_AF7_USART1        ((uint8_t)0x07U)  /* USART1 Alternate Function mapping     */\r\n#define GPIO_AF7_USART2        ((uint8_t)0x07U)  /* USART2 Alternate Function mapping     */\r\n#define GPIO_AF7_USART3        ((uint8_t)0x07U)  /* USART3 Alternate Function mapping     */\r\n#define GPIO_AF7_UART5         ((uint8_t)0x07U)  /* UART5 Alternate Function mapping      */\r\n#define GPIO_AF7_SPDIFRX       ((uint8_t)0x07U)  /* SPDIF-RX Alternate Function mapping   */\r\n#define GPIO_AF7_SPI2          ((uint8_t)0x07U)  /* SPI2 Alternate Function mapping       */\r\n#define GPIO_AF7_SPI3          ((uint8_t)0x07U)  /* SPI3 Alternate Function mapping       */\r\n#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r\n#define GPIO_AF7_SPI6          ((uint8_t)0x07U)  /* SPI6 Alternate Function mapping       */\r\n#define GPIO_AF7_DFSDM1         ((uint8_t)0x07U) /* DFSDM1 Alternate Function mapping      */\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */  \r\n\r\n/** \r\n  * @brief   AF 8 selection  \r\n  */ \r\n#define GPIO_AF8_UART4         ((uint8_t)0x08U)  /* UART4 Alternate Function mapping  */\r\n#define GPIO_AF8_UART5         ((uint8_t)0x08U)  /* UART5 Alternate Function mapping  */\r\n#define GPIO_AF8_USART6        ((uint8_t)0x08U)  /* USART6 Alternate Function mapping */\r\n#define GPIO_AF8_UART7         ((uint8_t)0x08U)  /* UART7 Alternate Function mapping  */\r\n#define GPIO_AF8_UART8         ((uint8_t)0x08U)  /* UART8 Alternate Function mapping  */\r\n#define GPIO_AF8_SPDIFRX       ((uint8_t)0x08U)  /* SPIDIF-RX Alternate Function mapping */\r\n#define GPIO_AF8_SAI2          ((uint8_t)0x08U)  /* SAI2 Alternate Function mapping   */\r\n#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r\n#define GPIO_AF8_SPI6          ((uint8_t)0x08U)  /* SPI6 Alternate Function mapping   */  \r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */    \r\n\r\n\r\n/** \r\n  * @brief   AF 9 selection \r\n  */ \r\n#define GPIO_AF9_CAN1          ((uint8_t)0x09U)  /* CAN1 Alternate Function mapping    */\r\n#define GPIO_AF9_CAN2          ((uint8_t)0x09U)  /* CAN2 Alternate Function mapping    */\r\n#define GPIO_AF9_TIM12         ((uint8_t)0x09U)  /* TIM12 Alternate Function mapping   */\r\n#define GPIO_AF9_TIM13         ((uint8_t)0x09U)  /* TIM13 Alternate Function mapping   */\r\n#define GPIO_AF9_TIM14         ((uint8_t)0x09U)  /* TIM14 Alternate Function mapping   */\r\n#define GPIO_AF9_QUADSPI       ((uint8_t)0x09U)  /* QUADSPI Alternate Function mapping */\r\n#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r\n#define GPIO_AF9_LTDC          ((uint8_t)0x09U)  /* LCD-TFT Alternate Function mapping */\r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F765xx) || defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r\n#define GPIO_AF9_FMC           ((uint8_t)0x09U)   /* FMC Alternate Function mapping     */\r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n/** \r\n  * @brief   AF 10 selection  \r\n  */ \r\n#define GPIO_AF10_OTG_FS        ((uint8_t)0xAU)  /* OTG_FS Alternate Function mapping */\r\n#define GPIO_AF10_OTG_HS        ((uint8_t)0xAU)  /* OTG_HS Alternate Function mapping */\r\n#define GPIO_AF10_QUADSPI       ((uint8_t)0xAU)  /* QUADSPI Alternate Function mapping */\r\n#define GPIO_AF10_SAI2          ((uint8_t)0xAU)  /* SAI2 Alternate Function mapping */\r\n#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r\n#define GPIO_AF10_DFSDM1         ((uint8_t)0x0AU)  /* DFSDM1 Alternate Function mapping  */\r\n#define GPIO_AF10_SDMMC2        ((uint8_t)0x0AU)  /* SDMMC2 Alternate Function mapping */   \r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */   \r\n\r\n/** \r\n  * @brief   AF 11 selection  \r\n  */ \r\n#define GPIO_AF11_ETH           ((uint8_t)0x0BU)  /* ETHERNET Alternate Function mapping */\r\n#if defined(STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define GPIO_AF11_CAN3          ((uint8_t)0x0BU)  /* CAN3 Alternate Function mapping     */\r\n#define GPIO_AF11_SDMMC2        ((uint8_t)0x0BU)  /* SDMMC2 Alternate Function mapping   */\r\n#define GPIO_AF11_I2C4          ((uint8_t)0x0BU)  /* I2C4 Alternate Function mapping     */   \r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n   \r\n/** \r\n  * @brief   AF 12 selection  \r\n  */ \r\n#define GPIO_AF12_FMC           ((uint8_t)0xCU)  /* FMC Alternate Function mapping                      */\r\n#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0xCU)  /* OTG HS configured in FS, Alternate Function mapping */\r\n#define GPIO_AF12_SDMMC1        ((uint8_t)0xCU)  /* SDMMC1 Alternate Function mapping                   */\r\n#if defined(STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)   \r\n#define GPIO_AF12_MDIOS        ((uint8_t)0xCU)  /* SDMMC1 Alternate Function mapping                    */\r\n#define GPIO_AF12_UART7        ((uint8_t)0xCU)  /* UART7 Alternate Function mapping                     */   \r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n   \r\n/** \r\n  * @brief   AF 13 selection  \r\n  */ \r\n#define GPIO_AF13_DCMI          ((uint8_t)0x0DU)  /* DCMI Alternate Function mapping */\r\n#if defined (STM32F769xx) || defined (STM32F779xx)   \r\n#define GPIO_AF13_DSI           ((uint8_t)0x0DU)  /* DSI Alternate Function mapping  */\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */   \r\n#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r\n#define GPIO_AF13_LTDC          ((uint8_t)0x0DU)  /* LTDC Alternate Function mapping */   \r\n   \r\n/** \r\n  * @brief   AF 14 selection  \r\n  */\r\n#define GPIO_AF14_LTDC          ((uint8_t)0x0EU)  /* LCD-TFT Alternate Function mapping */\r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n/** \r\n  * @brief   AF 15 selection  \r\n  */ \r\n#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0FU)  /* EVENTOUT Alternate Function mapping */\r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros\r\n  * @{\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/ \r\n/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions\r\n  * @{\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup GPIOEx_Private_Constants GPIO Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief   GPIO pin available on the platform\r\n  */\r\n/* Defines the available pins per GPIOs */\r\n#define GPIOA_PIN_AVAILABLE  GPIO_PIN_All\r\n#define GPIOB_PIN_AVAILABLE  GPIO_PIN_All\r\n#define GPIOC_PIN_AVAILABLE  GPIO_PIN_All\r\n#define GPIOD_PIN_AVAILABLE  GPIO_PIN_All\r\n#define GPIOE_PIN_AVAILABLE  GPIO_PIN_All\r\n#define GPIOF_PIN_AVAILABLE  GPIO_PIN_All\r\n#define GPIOG_PIN_AVAILABLE  GPIO_PIN_All\r\n#define GPIOI_PIN_AVAILABLE  GPIO_PIN_All\r\n#define GPIOJ_PIN_AVAILABLE  GPIO_PIN_All\r\n#define GPIOH_PIN_AVAILABLE  GPIO_PIN_All\r\n#define GPIOK_PIN_AVAILABLE  (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_4 | \\\r\n                              GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup GPIOEx_Private_Macros GPIO Private Macros\r\n  * @{\r\n  */\r\n/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index\r\n  * @{\r\n  */\r\n#define GPIO_GET_INDEX(__GPIOx__)   (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\\\r\n                                              ((__GPIOx__) == (GPIOB))? 1U :\\\r\n                                              ((__GPIOx__) == (GPIOC))? 2U :\\\r\n                                              ((__GPIOx__) == (GPIOD))? 3U :\\\r\n                                              ((__GPIOx__) == (GPIOE))? 4U :\\\r\n                                              ((__GPIOx__) == (GPIOF))? 5U :\\\r\n                                              ((__GPIOx__) == (GPIOG))? 6U :\\\r\n                                              ((__GPIOx__) == (GPIOH))? 7U :\\\r\n                                              ((__GPIOx__) == (GPIOI))? 8U :\\\r\n                                              ((__GPIOx__) == (GPIOJ))? 9U : 10U)\t\t\t\r\n/**\r\n  * @}\r\n  */\r\n\r\n#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__)  \\\r\n           ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \\\r\n            (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \\\r\n            (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \\\r\n            (((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))) || \\\r\n            (((__INSTANCE__) == GPIOE) && (((__PIN__) & (GPIOE_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOE_PIN_AVAILABLE)) == (GPIOE_PIN_AVAILABLE))) || \\\r\n            (((__INSTANCE__) == GPIOF) && (((__PIN__) & (GPIOF_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOF_PIN_AVAILABLE)) == (GPIOF_PIN_AVAILABLE))) || \\\r\n\t\t\t(((__INSTANCE__) == GPIOG) && (((__PIN__) & (GPIOG_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOG_PIN_AVAILABLE)) == (GPIOG_PIN_AVAILABLE))) || \\\r\n\t\t\t(((__INSTANCE__) == GPIOI) && (((__PIN__) & (GPIOI_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOI_PIN_AVAILABLE)) == (GPIOI_PIN_AVAILABLE))) || \\\r\n\t\t\t(((__INSTANCE__) == GPIOJ) && (((__PIN__) & (GPIOJ_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOJ_PIN_AVAILABLE)) == (GPIOJ_PIN_AVAILABLE))) || \\\r\n\t\t\t(((__INSTANCE__) == GPIOK) && (((__PIN__) & (GPIOK_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOK_PIN_AVAILABLE)) == (GPIOK_PIN_AVAILABLE))) || \\\r\n\t\t\t(((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE))))\r\n/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function\r\n  * @{\r\n  */\r\n#if defined(STM32F756xx) || defined(STM32F746xx)\r\n#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF1_TIM1)        || \\\r\n                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \\\r\n                          ((AF) == GPIO_AF0_MCO)       || ((AF) == GPIO_AF1_TIM2)       || \\\r\n                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \\\r\n                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \\\r\n                          ((AF) == GPIO_AF3_TIM9)       || ((AF) == GPIO_AF3_TIM10)      || \\\r\n                          ((AF) == GPIO_AF3_TIM11)      || ((AF) == GPIO_AF3_LPTIM1)     || \\\r\n                          ((AF) == GPIO_AF3_CEC)        || ((AF) == GPIO_AF4_CEC)        || \\\r\n                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \\\r\n                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF4_I2C4)       || \\\r\n                          ((AF) == GPIO_AF5_SPI1)       || ((AF) == GPIO_AF5_SPI2)       || \\\r\n                          ((AF) == GPIO_AF5_SPI3)       || ((AF) == GPIO_AF5_SPI4)       || \\\r\n                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \\\r\n                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF6_SAI1)       || \\\r\n                          ((AF) == GPIO_AF7_SPI3)       || ((AF) == GPIO_AF7_SPI2)        || \\\r\n                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)      || \\\r\n                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF7_UART5)       || \\\r\n                          ((AF) == GPIO_AF7_SPDIFRX)    || ((AF) == GPIO_AF8_SPDIFRX)     || \\\r\n                          ((AF) == GPIO_AF8_SAI2)       || ((AF) == GPIO_AF8_USART6)      || \\\r\n                          ((AF) == GPIO_AF8_UART4)      || ((AF) == GPIO_AF8_UART5)       || \\\r\n                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)       || \\\r\n                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)        || \\\r\n                          ((AF) == GPIO_AF9_TIM12)      || ((AF) == GPIO_AF9_TIM12)      || \\\r\n                          ((AF) == GPIO_AF9_TIM14)      || ((AF) == GPIO_AF9_QUADSPI)    || \\\r\n                          ((AF) == GPIO_AF9_LTDC)       || ((AF) == GPIO_AF10_OTG_FS)    || \\\r\n                          ((AF) == GPIO_AF10_OTG_HS)    || ((AF) == GPIO_AF10_SAI2)      || \\\r\n                          ((AF) == GPIO_AF10_QUADSPI)   || ((AF) == GPIO_AF11_ETH)       || \\\r\n                          ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1)     || \\\r\n                          ((AF) == GPIO_AF12_FMC)       || ((AF) == GPIO_AF15_EVENTOUT)  || \\\r\n                          ((AF) == GPIO_AF13_DCMI)      || ((AF) == GPIO_AF14_LTDC))\r\n#elif defined(STM32F745xx)\r\n#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF1_TIM1)        || \\\r\n                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \\\r\n                          ((AF) == GPIO_AF0_MCO)       || ((AF) == GPIO_AF1_TIM2)       || \\\r\n                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \\\r\n                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \\\r\n                          ((AF) == GPIO_AF3_TIM9)       || ((AF) == GPIO_AF3_TIM10)      || \\\r\n                          ((AF) == GPIO_AF3_TIM11)      || ((AF) == GPIO_AF3_LPTIM1)     || \\\r\n                          ((AF) == GPIO_AF3_CEC)        || ((AF) == GPIO_AF4_CEC)        || \\\r\n                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \\\r\n                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF4_I2C4)       || \\\r\n                          ((AF) == GPIO_AF5_SPI1)       || ((AF) == GPIO_AF5_SPI2)       || \\\r\n                          ((AF) == GPIO_AF5_SPI3)       || ((AF) == GPIO_AF5_SPI4)       || \\\r\n                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \\\r\n                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF6_SAI1)       || \\\r\n                          ((AF) == GPIO_AF7_SPI3)       || ((AF) == GPIO_AF7_SPI2)        || \\\r\n                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)      || \\\r\n                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF7_UART5)       || \\\r\n                          ((AF) == GPIO_AF7_SPDIFRX)    || ((AF) == GPIO_AF8_SPDIFRX)     || \\\r\n                          ((AF) == GPIO_AF8_SAI2)       || ((AF) == GPIO_AF8_USART6)      || \\\r\n                          ((AF) == GPIO_AF8_UART4)      || ((AF) == GPIO_AF8_UART5)       || \\\r\n                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)       || \\\r\n                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)        || \\\r\n                          ((AF) == GPIO_AF9_TIM12)      || ((AF) == GPIO_AF9_TIM12)      || \\\r\n                          ((AF) == GPIO_AF9_TIM14)      || ((AF) == GPIO_AF9_QUADSPI)    || \\\r\n                          ((AF) == GPIO_AF13_DCMI)      || ((AF) == GPIO_AF10_OTG_FS)    || \\\r\n                          ((AF) == GPIO_AF10_OTG_HS)    || ((AF) == GPIO_AF10_SAI2)      || \\\r\n                          ((AF) == GPIO_AF10_QUADSPI)   || ((AF) == GPIO_AF11_ETH)       || \\\r\n                          ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1)     || \\\r\n                          ((AF) == GPIO_AF12_FMC)       || ((AF) == GPIO_AF15_EVENTOUT))\r\n#elif defined(STM32F767xx) || defined(STM32F777xx)\r\n#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF1_TIM1)        || \\\r\n                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \\\r\n                          ((AF) == GPIO_AF0_MCO)       || ((AF) == GPIO_AF1_TIM2)       || \\\r\n                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \\\r\n                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \\\r\n                          ((AF) == GPIO_AF3_TIM9)       || ((AF) == GPIO_AF3_TIM10)      || \\\r\n                          ((AF) == GPIO_AF3_TIM11)      || ((AF) == GPIO_AF3_LPTIM1)     || \\\r\n                          ((AF) == GPIO_AF3_CEC)        || ((AF) == GPIO_AF4_CEC)        || \\\r\n                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \\\r\n                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF4_I2C4)       || \\\r\n                          ((AF) == GPIO_AF5_SPI1)       || ((AF) == GPIO_AF5_SPI2)       || \\\r\n                          ((AF) == GPIO_AF5_SPI3)       || ((AF) == GPIO_AF5_SPI4)       || \\\r\n                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \\\r\n                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF6_SAI1)       || \\\r\n                          ((AF) == GPIO_AF7_SPI3)       || ((AF) == GPIO_AF7_SPI2)       || \\\r\n                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \\\r\n                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF7_UART5)      || \\\r\n                          ((AF) == GPIO_AF7_SPDIFRX)    || ((AF) == GPIO_AF8_SPDIFRX)    || \\\r\n                          ((AF) == GPIO_AF8_SAI2)       || ((AF) == GPIO_AF8_USART6)     || \\\r\n                          ((AF) == GPIO_AF8_UART4)      || ((AF) == GPIO_AF8_UART5)      || \\\r\n                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \\\r\n                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \\\r\n                          ((AF) == GPIO_AF9_TIM12)      || ((AF) == GPIO_AF9_TIM12)      || \\\r\n                          ((AF) == GPIO_AF9_TIM14)      || ((AF) == GPIO_AF9_QUADSPI)    || \\\r\n                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF9_LTDC)       || \\\r\n                          ((AF) == GPIO_AF10_OTG_HS)    || ((AF) == GPIO_AF10_SAI2)      || \\\r\n                          ((AF) == GPIO_AF10_QUADSPI)   || ((AF) == GPIO_AF11_ETH)       || \\\r\n                          ((AF) == GPIO_AF11_CAN3)      || ((AF) == GPIO_AF12_OTG_HS_FS) || \\\r\n                          ((AF) == GPIO_AF12_SDMMC1)    || ((AF) == GPIO_AF12_FMC)       || \\\r\n                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF13_DCMI)      || \\\r\n\t\t\t\t\t\t  ((AF) == GPIO_AF14_LTDC))\r\n#elif defined(STM32F769xx) || defined(STM32F779xx)\r\n#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF1_TIM1)        || \\\r\n                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \\\r\n                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF1_TIM2)       || \\\r\n                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \\\r\n                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \\\r\n                          ((AF) == GPIO_AF3_TIM9)       || ((AF) == GPIO_AF3_TIM10)      || \\\r\n                          ((AF) == GPIO_AF3_TIM11)      || ((AF) == GPIO_AF3_LPTIM1)     || \\\r\n                          ((AF) == GPIO_AF3_CEC)        || ((AF) == GPIO_AF4_CEC)        || \\\r\n                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \\\r\n                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF4_I2C4)       || \\\r\n                          ((AF) == GPIO_AF5_SPI1)       || ((AF) == GPIO_AF5_SPI2)       || \\\r\n                          ((AF) == GPIO_AF5_SPI3)       || ((AF) == GPIO_AF5_SPI4)       || \\\r\n                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \\\r\n                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF6_SAI1)       || \\\r\n                          ((AF) == GPIO_AF7_SPI3)       || ((AF) == GPIO_AF7_SPI2)       || \\\r\n                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \\\r\n                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF7_UART5)      || \\\r\n                          ((AF) == GPIO_AF7_SPDIFRX)    || ((AF) == GPIO_AF8_SPDIFRX)    || \\\r\n                          ((AF) == GPIO_AF8_SAI2)       || ((AF) == GPIO_AF8_USART6)     || \\\r\n                          ((AF) == GPIO_AF8_UART4)      || ((AF) == GPIO_AF8_UART5)      || \\\r\n                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \\\r\n                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \\\r\n                          ((AF) == GPIO_AF9_TIM12)      || ((AF) == GPIO_AF9_TIM12)      || \\\r\n                          ((AF) == GPIO_AF9_TIM14)      || ((AF) == GPIO_AF9_QUADSPI)    || \\\r\n                          ((AF) == GPIO_AF9_LTDC)       || ((AF) == GPIO_AF10_OTG_FS)    || \\\r\n                          ((AF) == GPIO_AF10_OTG_HS)    || ((AF) == GPIO_AF10_SAI2)      || \\\r\n                          ((AF) == GPIO_AF10_QUADSPI)   || ((AF) == GPIO_AF11_ETH)       || \\\r\n                          ((AF) == GPIO_AF11_CAN3)      || ((AF) == GPIO_AF12_OTG_HS_FS) || \\\r\n                          ((AF) == GPIO_AF12_SDMMC1)    || ((AF) == GPIO_AF12_FMC)       || \\\r\n                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF13_DCMI)      || \\\r\n                          ((AF) == GPIO_AF14_LTDC)      || ((AF) == GPIO_AF13_DSI))\r\n#elif defined(STM32F765xx)\r\n#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF1_TIM1)        || \\\r\n                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \\\r\n                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF1_TIM2)       || \\\r\n                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \\\r\n                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \\\r\n                          ((AF) == GPIO_AF3_TIM9)       || ((AF) == GPIO_AF3_TIM10)      || \\\r\n                          ((AF) == GPIO_AF3_TIM11)      || ((AF) == GPIO_AF3_LPTIM1)     || \\\r\n                          ((AF) == GPIO_AF3_CEC)        || ((AF) == GPIO_AF4_CEC)        || \\\r\n                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \\\r\n                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF4_I2C4)       || \\\r\n                          ((AF) == GPIO_AF5_SPI1)       || ((AF) == GPIO_AF5_SPI2)       || \\\r\n                          ((AF) == GPIO_AF5_SPI3)       || ((AF) == GPIO_AF5_SPI4)       || \\\r\n                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \\\r\n                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF6_SAI1)       || \\\r\n                          ((AF) == GPIO_AF7_SPI3)       || ((AF) == GPIO_AF7_SPI2)       || \\\r\n                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \\\r\n                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF7_UART5)      || \\\r\n                          ((AF) == GPIO_AF7_SPDIFRX)    || ((AF) == GPIO_AF8_SPDIFRX)    || \\\r\n                          ((AF) == GPIO_AF8_SAI2)       || ((AF) == GPIO_AF8_USART6)     || \\\r\n                          ((AF) == GPIO_AF8_UART4)      || ((AF) == GPIO_AF8_UART5)      || \\\r\n                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \\\r\n                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \\\r\n                          ((AF) == GPIO_AF9_TIM12)      || ((AF) == GPIO_AF9_TIM12)      || \\\r\n                          ((AF) == GPIO_AF9_TIM14)      || ((AF) == GPIO_AF9_QUADSPI)    || \\\r\n                          ((AF) == GPIO_AF10_OTG_HS)    || ((AF) == GPIO_AF10_SAI2)      || \\\r\n                          ((AF) == GPIO_AF10_QUADSPI)   || ((AF) == GPIO_AF11_ETH)       || \\\r\n                          ((AF) == GPIO_AF11_CAN3)      || ((AF) == GPIO_AF12_OTG_HS_FS) || \\\r\n                          ((AF) == GPIO_AF12_SDMMC1)    || ((AF) == GPIO_AF12_FMC)       || \\\r\n                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF13_DCMI)      || \\\r\n                          ((AF) == GPIO_AF10_OTG_FS))\r\n#endif /* STM32F756xx || STM32F746xx */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup GPIOEx_Private_Functions GPIO Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_GPIO_EX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_hash.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of HASH HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_HASH_H\r\n#define __STM32F7xx_HAL_HASH_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup HASH    \r\n  * @brief HASH HAL module driver \r\n  *  @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup HASH_Exported_Types HASH Exported Types\r\n  * @{\r\n  */\r\n\r\n/** @defgroup HASH_Exported_Types_Group1 HASH Configuration Structure definition\r\n  * @{\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  uint32_t DataType;  /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.\r\n                           This parameter can be a value of @ref HASH_Data_Type */\r\n\r\n  uint32_t KeySize;   /*!< The key size is used only in HMAC operation          */\r\n\r\n  uint8_t* pKey;      /*!< The key is used only in HMAC operation               */\r\n}HASH_InitTypeDef;\r\n\r\n/** \r\n  * @}\r\n  */\r\n\r\n/** @defgroup HASH_Exported_Types_Group2 HASH State structures definition\r\n  * @{\r\n  */\r\n\r\ntypedef enum\r\n{\r\n  HAL_HASH_STATE_RESET     = 0x00U,  /*!< HASH not yet initialized or disabled */\r\n  HAL_HASH_STATE_READY     = 0x01U,  /*!< HASH initialized and ready for use   */\r\n  HAL_HASH_STATE_BUSY      = 0x02U,  /*!< HASH internal process is ongoing     */\r\n  HAL_HASH_STATE_TIMEOUT   = 0x03U,  /*!< HASH timeout state                   */\r\n  HAL_HASH_STATE_ERROR     = 0x04U   /*!< HASH error state                     */\r\n}HAL_HASH_StateTypeDef;\r\n\r\n/** \r\n  * @}\r\n  */\r\n  \r\n/** @defgroup HASH_Exported_Types_Group3 HASH phase structures definition\r\n  * @{\r\n  */\r\n  \r\ntypedef enum\r\n{\r\n  HAL_HASH_PHASE_READY     = 0x01U,  /*!< HASH peripheral is ready for initialization */\r\n  HAL_HASH_PHASE_PROCESS   = 0x02U,  /*!< HASH peripheral is in processing phase      */\r\n}HAL_HASHPhaseTypeDef;\r\n\r\n/** \r\n  * @}\r\n  */\r\n \r\n/** @defgroup HASH_Exported_Types_Group4 HASH Handle structures definition\r\n  * @{\r\n  */ \r\n  \r\ntypedef struct\r\n{\r\n      HASH_InitTypeDef           Init;              /*!< HASH required parameters       */\r\n\r\n      uint8_t                    *pHashInBuffPtr;   /*!< Pointer to input buffer        */\r\n\r\n      uint8_t                    *pHashOutBuffPtr;  /*!< Pointer to input buffer        */\r\n\r\n     __IO uint32_t               HashBuffSize;      /*!< Size of buffer to be processed */\r\n\r\n     __IO uint32_t               HashInCount;       /*!< Counter of inputed data        */\r\n\r\n     __IO uint32_t               HashITCounter;     /*!< Counter of issued interrupts   */\r\n\r\n      HAL_StatusTypeDef          Status;            /*!< HASH peripheral status         */\r\n\r\n      HAL_HASH_PhaseTypeDef       Phase;             /*!< HASH peripheral phase          */\r\n\r\n      DMA_HandleTypeDef          *hdmain;           /*!< HASH In DMA handle parameters  */\r\n\r\n      HAL_LockTypeDef            Lock;              /*!< HASH locking object            */\r\n\r\n     __IO HAL_HASH_StateTypeDef  State;             /*!< HASH peripheral state          */\r\n} HASH_HandleTypeDef;\r\n\r\n/** \r\n  * @}\r\n  */\r\n  \r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup HASH_Exported_Constants HASH Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup HASH_Exported_Constants_Group1 HASH Algorithm Selection\r\n  * @{\r\n  */\r\n#define HASH_ALGOSELECTION_SHA1      ((uint32_t)0x0000U)  /*!< HASH function is SHA1   */\r\n#define HASH_ALGOSELECTION_SHA224    HASH_CR_ALGO_1      /*!< HASH function is SHA224 */\r\n#define HASH_ALGOSELECTION_SHA256    HASH_CR_ALGO        /*!< HASH function is SHA256 */\r\n#define HASH_ALGOSELECTION_MD5       HASH_CR_ALGO_0      /*!< HASH function is MD5    */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HASH_Exported_Constants_Group2 HASH Algorithm Mode\r\n  * @{\r\n  */\r\n#define HASH_ALGOMODE_HASH         ((uint32_t)0x00000000U)  /*!< Algorithm is HASH */ \r\n#define HASH_ALGOMODE_HMAC         HASH_CR_MODE            /*!< Algorithm is HMAC */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HASH_Data_Type HASH Data Type\r\n  * @{\r\n  */\r\n#define HASH_DATATYPE_32B          ((uint32_t)0x0000U) /*!< 32-bit data. No swapping                     */\r\n#define HASH_DATATYPE_16B          HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped       */\r\n#define HASH_DATATYPE_8B           HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped            */\r\n#define HASH_DATATYPE_1B           HASH_CR_DATATYPE   /*!< 1-bit data. In the word all bits are swapped */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HASH_Exported_Constants_Group4 HASH HMAC Long key \r\n  * @brief HASH HMAC Long key used only for HMAC mode\r\n  * @{\r\n  */\r\n#define HASH_HMAC_KEYTYPE_SHORTKEY      ((uint32_t)0x00000000U)  /*!< HMAC Key is <= 64 bytes */\r\n#define HASH_HMAC_KEYTYPE_LONGKEY       HASH_CR_LKEY            /*!< HMAC Key is > 64 bytes  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HASH_Exported_Constants_Group5 HASH Flags definition \r\n  * @{\r\n  */\r\n#define HASH_FLAG_DINIS            HASH_SR_DINIS  /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer */\r\n#define HASH_FLAG_DCIS             HASH_SR_DCIS   /*!< Digest calculation complete                                                         */\r\n#define HASH_FLAG_DMAS             HASH_SR_DMAS   /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing                          */\r\n#define HASH_FLAG_BUSY             HASH_SR_BUSY   /*!< The hash core is Busy : processing a block of data                                  */\r\n#define HASH_FLAG_DINNE            HASH_CR_DINNE  /*!< DIN not empty : The input buffer contains at least one word of data                 */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HASH_Exported_Constants_Group6 HASH Interrupts definition \r\n  * @{\r\n  */\r\n#define HASH_IT_DINI               HASH_IMR_DINIE  /*!< A new block can be entered into the input buffer (DIN) */\r\n#define HASH_IT_DCI                HASH_IMR_DCIE   /*!< Digest calculation complete                            */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup HASH_Exported_Macros HASH Exported Macros\r\n  * @{\r\n  */\r\n  \r\n/** @brief Reset HASH handle state\r\n  * @param  __HANDLE__: specifies the HASH handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)\r\n\r\n/** @brief  Check whether the specified HASH flag is set or not.\r\n  * @param  __FLAG__: specifies the flag to check.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg HASH_FLAG_DINIS: A new block can be entered into the input buffer. \r\n  *            @arg HASH_FLAG_DCIS: Digest calculation complete\r\n  *            @arg HASH_FLAG_DMAS: DMA interface is enabled (DMAE=1) or a transfer is ongoing\r\n  *            @arg HASH_FLAG_BUSY: The hash core is Busy : processing a block of data\r\n  *            @arg HASH_FLAG_DINNE: DIN not empty : The input buffer contains at least one word of data\r\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\\\r\n                                                           ((HASH->SR & (__FLAG__)) == (__FLAG__)))\r\n\r\n/**\r\n  * @brief  Enable the multiple DMA mode. \r\n  *         This feature is available only in STM32F429x and STM32F439x devices.\r\n  * @retval None\r\n  */\r\n#define __HAL_HASH_SET_MDMAT()          HASH->CR |= HASH_CR_MDMAT\r\n\r\n/**\r\n  * @brief  Disable the multiple DMA mode.\r\n  * @retval None\r\n  */\r\n#define __HAL_HASH_RESET_MDMAT()        HASH->CR &= (uint32_t)(~HASH_CR_MDMAT)\r\n\r\n/**\r\n  * @brief  Start the digest computation\r\n  * @retval None\r\n  */\r\n#define __HAL_HASH_START_DIGEST()       HASH->STR |= HASH_STR_DCAL\r\n\r\n/**\r\n  * @brief Set the number of valid bits in last word written in Data register\r\n  * @param  SIZE: size in byte of last data written in Data register.\r\n  * @retval None\r\n*/\r\n#define __HAL_HASH_SET_NBVALIDBITS(SIZE) do{HASH->STR &= ~(HASH_STR_NBW);\\\r\n                                            HASH->STR |= 8 * ((SIZE) % 4);\\\r\n                                           }while(0)\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Include HASH HAL Extension module */\r\n#include \"stm32f7xx_hal_hash_ex.h\"\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @defgroup HASH_Exported_Functions HASH Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup HASH_Exported_Functions_Group1\r\n  * @{\r\n  */  \r\nHAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash);\r\nHAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @addtogroup HASH_Exported_Functions_Group2\r\n  * @{\r\n  */  \r\nHAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r\nHAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/** @addtogroup HASH_Exported_Functions_Group3\r\n  * @{\r\n  */  \r\nHAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @addtogroup HASH_Exported_Functions_Group4\r\n  * @{\r\n  */  \r\nHAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);\r\nHAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @addtogroup HASH_Exported_Functions_Group5\r\n  * @{\r\n  */    \r\nHAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r\nHAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r\nHAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @addtogroup HASH_Exported_Functions_Group6\r\n  * @{\r\n  */  \r\nHAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r\nHAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @addtogroup HASH_Exported_Functions_Group7\r\n  * @{\r\n  */  \r\nvoid HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @addtogroup HASH_Exported_Functions_Group8\r\n  * @{\r\n  */\r\nHAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);\r\nvoid HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);\r\nvoid HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);\r\nvoid HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);\r\nvoid HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);\r\nvoid HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n /**\r\n  * @}\r\n  */ \r\n \r\n /* Private types -------------------------------------------------------------*/\r\n/** @defgroup HASH_Private_Types HASH Private Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @defgroup HASH_Private_Variables HASH Private Variables\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup HASH_Private_Constants HASH Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup HASH_Private_Macros HASH Private Macros\r\n  * @{\r\n  */\r\n#define IS_HASH_ALGOSELECTION(__ALGOSELECTION__) (((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA1)   || \\\r\n                                                  ((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA224) || \\\r\n                                                  ((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA256) || \\\r\n                                                  ((__ALGOSELECTION__) == HASH_ALGOSELECTION_MD5))\r\n\r\n\r\n#define IS_HASH_ALGOMODE(__ALGOMODE__) (((__ALGOMODE__) == HASH_ALGOMODE_HASH) || \\\r\n                                        ((__ALGOMODE__) == HASH_ALGOMODE_HMAC))\r\n\r\n\r\n#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \\\r\n                                        ((__DATATYPE__) == HASH_DATATYPE_16B)|| \\\r\n                                        ((__DATATYPE__) == HASH_DATATYPE_8B) || \\\r\n                                        ((__DATATYPE__) == HASH_DATATYPE_1B))\r\n\r\n\r\n#define IS_HASH_HMAC_KEYTYPE(__KEYTYPE__) (((__KEYTYPE__) == HASH_HMAC_KEYTYPE_SHORTKEY) || \\\r\n                                           ((__KEYTYPE__) == HASH_HMAC_KEYTYPE_LONGKEY))\r\n                                           \r\n#define IS_HASH_SHA1_BUFFER_SIZE(__SIZE__) ((((__SIZE__)%4) != 0)? 0U: 1U)\r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup HASH_Private_Functions HASH Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n \r\n/**\r\n  * @}\r\n  */ \r\n#endif /* STM32F756xx || STM32F777xx || STM32F779xx */\r\n/**\r\n  * @}\r\n  */\r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n\r\n#endif /* __STM32F7xx_HAL_HASH_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_hash_ex.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of HASH HAL Extension module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_HASH_EX_H\r\n#define __STM32F7xx_HAL_HASH_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup HASHEx    \r\n  * @brief HASHEx HAL Extension module driver \r\n  *  @{\r\n  */ \r\n  \r\n/* Exported types ------------------------------------------------------------*/ \r\n/* Exported constants --------------------------------------------------------*/\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @defgroup HASHEx_Exported_Functions HASHEx Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup HASHEx_Exported_Functions_Group1 HASHEx processing using polling functions\r\n  * @{\r\n  */  \r\n\r\nHAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r\nHAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/** @defgroup HASHEx_Exported_Functions_Group2 HMAC processing using polling functions\r\n  * @{\r\n  */ \r\n  \r\nHAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/** @defgroup HASHEx_Exported_Functions_Group3 HASHEx processing using  functions\r\n  * @{\r\n  */ \r\n  \r\nHAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);\r\nHAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/** @defgroup HASHEx_Exported_Functions_Group4 HASHEx processing using DMA\r\n  * @{\r\n  */\r\n  \r\nHAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r\nHAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r\nHAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/** @defgroup HASHEx_Exported_Functions_Group5 HMAC processing using DMA\r\n  * @{\r\n  */\r\n  \r\nHAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r\nHAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/** @defgroup HASHEx_Exported_Functions_Group6 HASHEx processing functions\r\n  * @{\r\n  */\r\n  \r\nvoid HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n \r\n /* Private types -------------------------------------------------------------*/\r\n/** @defgroup HASHEx_Private_Types HASHEx Private Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @defgroup HASHEx_Private_Variables HASHEx Private Variables\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup HASHEx_Private_Constants HASHEx Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup HASHEx_Private_Macros HASHEx Private Macros\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup HASHEx_Private_Functions HASHEx Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n   \r\n/**\r\n  * @}\r\n  */ \r\n#endif /* STM32F756xx || STM32F777xx || STM32F779xx */\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_HASH_EX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hcd.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_hcd.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of HCD HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_HCD_H\r\n#define __STM32F7xx_HAL_HCD_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_ll_usb.h\"\r\n   \r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup HCD HCD\r\n  * @brief HCD HAL module driver\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup HCD_Exported_Types HCD Exported Types\r\n  * @{\r\n  */ \r\n\r\n/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition \r\n  * @{\r\n  */\r\ntypedef enum \r\n{\r\n  HAL_HCD_STATE_RESET    = 0x00U,\r\n  HAL_HCD_STATE_READY    = 0x01U,\r\n  HAL_HCD_STATE_ERROR    = 0x02U,\r\n  HAL_HCD_STATE_BUSY     = 0x03U,\r\n  HAL_HCD_STATE_TIMEOUT  = 0x04U\r\n} HCD_StateTypeDef;\r\n\r\ntypedef USB_OTG_GlobalTypeDef   HCD_TypeDef;\r\ntypedef USB_OTG_CfgTypeDef      HCD_InitTypeDef;\r\ntypedef USB_OTG_HCTypeDef       HCD_HCTypeDef ;   \r\ntypedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef ;\r\ntypedef USB_OTG_HCStateTypeDef  HCD_HCStateTypeDef ;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition   \r\n  * @{\r\n  */ \r\ntypedef struct\r\n{\r\n  HCD_TypeDef               *Instance;  /*!< Register base address    */ \r\n  HCD_InitTypeDef           Init;       /*!< HCD required parameters  */\r\n  HCD_HCTypeDef             hc[15];     /*!< Host channels parameters */\r\n  HAL_LockTypeDef           Lock;       /*!< HCD peripheral status    */\r\n  __IO HCD_StateTypeDef     State;      /*!< HCD communication state  */\r\n  void                      *pData;     /*!< Pointer Stack Handler    */\r\n} HCD_HandleTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup HCD_Exported_Constants HCD Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup HCD_Speed HCD Speed\r\n  * @{\r\n  */\r\n#define HCD_SPEED_HIGH               0U\r\n#define HCD_SPEED_LOW                2U  \r\n#define HCD_SPEED_FULL               3U\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup HCD_PHY_Module HCD PHY Module\r\n  * @{\r\n  */\r\n#define HCD_PHY_ULPI                 1U\r\n#define HCD_PHY_EMBEDDED             2U\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup HCD_Exported_Macros HCD Exported Macros\r\n *  @brief macros to handle interrupts and specific clock configurations\r\n * @{\r\n */\r\n#define __HAL_HCD_ENABLE(__HANDLE__)                   USB_EnableGlobalInt ((__HANDLE__)->Instance)\r\n#define __HAL_HCD_DISABLE(__HANDLE__)                  USB_DisableGlobalInt ((__HANDLE__)->Instance)\r\n\r\n#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))\r\n#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))\r\n#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)    \r\n\r\n#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__)  (USBx_HC(chnum)->HCINT = (__INTERRUPT__)) \r\n#define __HAL_HCD_MASK_HALT_HC_INT(chnum)             (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM) \r\n#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum)           (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM) \r\n#define __HAL_HCD_MASK_ACK_HC_INT(chnum)              (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM) \r\n#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum)            (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM) \r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup HCD_Exported_Functions HCD Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef      HAL_HCD_Init(HCD_HandleTypeDef *hhcd);\r\nHAL_StatusTypeDef      HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd);\r\nHAL_StatusTypeDef      HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,  \r\n                                  uint8_t ch_num,\r\n                                  uint8_t epnum,\r\n                                  uint8_t dev_address,\r\n                                  uint8_t speed,\r\n                                  uint8_t ep_type,\r\n                                  uint16_t mps);\r\n\r\nHAL_StatusTypeDef   HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);\r\nvoid                HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);\r\nvoid                HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* I/O operation functions  ***************************************************/\r\n/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef       HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,\r\n                                                 uint8_t pipe, \r\n                                                 uint8_t direction ,\r\n                                                 uint8_t ep_type,  \r\n                                                 uint8_t token, \r\n                                                 uint8_t* pbuff, \r\n                                                 uint16_t length,\r\n                                                 uint8_t do_ping);\r\n\r\n /* Non-Blocking mode: Interrupt */\r\nvoid                    HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);\r\nvoid             HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);\r\nvoid             HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);\r\nvoid             HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);\r\nvoid             HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, \r\n                                                            uint8_t chnum, \r\n                                                            HCD_URBStateTypeDef urb_state);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Peripheral Control functions  **********************************************/\r\n/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef       HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);\r\nHAL_StatusTypeDef       HAL_HCD_Start(HCD_HandleTypeDef *hhcd);\r\nHAL_StatusTypeDef       HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Peripheral State functions  ************************************************/\r\n/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions\r\n  * @{\r\n  */\r\nHCD_StateTypeDef        HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);\r\nHCD_URBStateTypeDef     HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);\r\nuint32_t                HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);\r\nHCD_HCStateTypeDef      HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);\r\nuint32_t                HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);\r\nuint32_t                HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup HCD_Private_Macros HCD Private Macros\r\n * @{\r\n */\r\n/** @defgroup HCD_Instance_definition HCD Instance definition\r\n  * @{\r\n  */\r\n#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \\\r\n                                       ((INSTANCE) == USB_OTG_HS))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions prototypes ----------------------------------------------*/\r\n/** @defgroup HCD_Private_Functions_Prototypes HCD Private Functions Prototypes\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup HCD_Private_Functions HCD Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_HCD_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_i2c.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of I2C HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_I2C_H\r\n#define __STM32F7xx_HAL_I2C_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"  \r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup I2C\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup I2C_Exported_Types I2C Exported Types\r\n  * @{\r\n  */\r\n\r\n/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition\r\n  * @brief  I2C Configuration Structure definition  \r\n  * @{\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t Timing;              /*!< Specifies the I2C_TIMINGR_register value.\r\n                                  This parameter calculated by referring to I2C initialization \r\n                                         section in Reference manual */\r\n\r\n  uint32_t OwnAddress1;         /*!< Specifies the first device own address.\r\n                                  This parameter can be a 7-bit or 10-bit address. */\r\n\r\n  uint32_t AddressingMode;      /*!< Specifies if 7-bit or 10-bit addressing mode is selected.\r\n                                  This parameter can be a value of @ref I2C_ADDRESSING_MODE */\r\n\r\n  uint32_t DualAddressMode;     /*!< Specifies if dual addressing mode is selected.\r\n                                  This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */\r\n\r\n  uint32_t OwnAddress2;         /*!< Specifies the second device own address if dual addressing mode is selected\r\n                                  This parameter can be a 7-bit address. */\r\n\r\n  uint32_t OwnAddress2Masks;    /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected\r\n                                  This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */\r\n\r\n  uint32_t GeneralCallMode;     /*!< Specifies if general call mode is selected.\r\n                                  This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */\r\n\r\n  uint32_t NoStretchMode;       /*!< Specifies if nostretch mode is selected.\r\n                                  This parameter can be a value of @ref I2C_NOSTRETCH_MODE */\r\n\r\n}I2C_InitTypeDef;\r\n\r\n/** \r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_state_structure_definition HAL state structure definition\r\n  * @brief  HAL State structure definition\r\n  * @note  HAL I2C State value coding follow below described bitmap :\r\n  *          b7-b6  Error information \r\n  *             00 : No Error\r\n  *             01 : Abort (Abort user request on going)\r\n  *             10 : Timeout\r\n  *             11 : Error\r\n  *          b5     IP initilisation status\r\n  *             0  : Reset (IP not initialized)\r\n  *             1  : Init done (IP initialized and ready to use. HAL I2C Init function called)\r\n  *          b4     (not used)\r\n  *             x  : Should be set to 0\r\n  *          b3\r\n  *             0  : Ready or Busy (No Listen mode ongoing)\r\n  *             1  : Listen (IP in Address Listen Mode)\r\n  *          b2     Intrinsic process state\r\n  *             0  : Ready\r\n  *             1  : Busy (IP busy with some configuration or internal operations)\r\n  *          b1     Rx state\r\n  *             0  : Ready (no Rx operation ongoing)\r\n  *             1  : Busy (Rx operation ongoing)\r\n  *          b0     Tx state\r\n  *             0  : Ready (no Tx operation ongoing)\r\n  *             1  : Busy (Tx operation ongoing)\r\n  * @{\r\n  */ \r\n\r\ntypedef enum\r\n{\r\n  HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */\r\n  HAL_I2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */\r\n  HAL_I2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */\r\n  HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */ \r\n  HAL_I2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */\r\n  HAL_I2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */\r\n  HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission\r\n                                                 process is ongoing                        */\r\n  HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception\r\n                                                 process is ongoing                        */\r\n  HAL_I2C_STATE_ABORT             = 0x60,    /*!< Abort user request ongoing                */\r\n  HAL_I2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */\r\n  HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */ \r\n\r\n}HAL_I2C_StateTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_mode_structure_definition HAL mode structure definition\r\n  * @brief  HAL Mode structure definition\r\n  * @note  HAL I2C Mode value coding follow below described bitmap :\r\n  *          b7     (not used)\r\n  *             x  : Should be set to 0\r\n  *          b6\r\n  *             0  : None\r\n  *             1  : Memory (HAL I2C communication is in Memory Mode)\r\n  *          b5\r\n  *             0  : None\r\n  *             1  : Slave (HAL I2C communication is in Slave Mode)\r\n  *          b4\r\n  *             0  : None\r\n  *             1  : Master (HAL I2C communication is in Master Mode)\r\n  *          b3-b2-b1-b0  (not used)\r\n  *             xxxx : Should be set to 0000\r\n  * @{\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_I2C_MODE_NONE               = 0x00U,   /*!< No I2C communication on going             */\r\n  HAL_I2C_MODE_MASTER             = 0x10U,   /*!< I2C communication is in Master Mode       */\r\n  HAL_I2C_MODE_SLAVE              = 0x20U,   /*!< I2C communication is in Slave Mode        */\r\n  HAL_I2C_MODE_MEM                = 0x40U    /*!< I2C communication is in Memory Mode       */\r\n\r\n}HAL_I2C_ModeTypeDef;\r\n\r\n/** \r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2C_Error_Code_definition I2C Error Code definition\r\n  * @brief  I2C Error Code definition  \r\n  * @{\r\n  */\r\n#define HAL_I2C_ERROR_NONE      ((uint32_t)0x00000000U)    /*!< No error              */\r\n#define HAL_I2C_ERROR_BERR      ((uint32_t)0x00000001U)    /*!< BERR error            */\r\n#define HAL_I2C_ERROR_ARLO      ((uint32_t)0x00000002U)    /*!< ARLO error            */\r\n#define HAL_I2C_ERROR_AF        ((uint32_t)0x00000004U)    /*!< ACKF error            */\r\n#define HAL_I2C_ERROR_OVR       ((uint32_t)0x00000008U)    /*!< OVR error             */\r\n#define HAL_I2C_ERROR_DMA       ((uint32_t)0x00000010U)    /*!< DMA transfer error    */\r\n#define HAL_I2C_ERROR_TIMEOUT   ((uint32_t)0x00000020U)    /*!< Timeout error         */\r\n#define HAL_I2C_ERROR_SIZE      ((uint32_t)0x00000040U)    /*!< Size Management error */\r\n#define HAL_I2C_ERROR_ABORT     ((uint32_t)0x00000080U)    /*!< Abort user request    */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition\r\n  * @brief  I2C handle Structure definition  \r\n  * @{\r\n  */\r\ntypedef struct __I2C_HandleTypeDef\r\n{\r\n  I2C_TypeDef                *Instance;      /*!< I2C registers base address                */\r\n\r\n  I2C_InitTypeDef            Init;           /*!< I2C communication parameters              */\r\n\r\n  uint8_t                    *pBuffPtr;      /*!< Pointer to I2C transfer buffer            */\r\n\r\n  uint16_t                   XferSize;       /*!< I2C transfer size                         */\r\n\r\n  __IO uint16_t              XferCount;      /*!< I2C transfer counter                      */\r\n\r\n  __IO uint32_t              XferOptions;    /*!< I2C sequantial transfer options, this parameter can\r\n                                                  be a value of @ref I2C_XFEROPTIONS */\r\n\r\n  __IO uint32_t              PreviousState;  /*!< I2C communication Previous state          */\r\n\r\n  HAL_StatusTypeDef (*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */\r\n\r\n  DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters              */\r\n\r\n  DMA_HandleTypeDef          *hdmarx;        /*!< I2C Rx DMA handle parameters              */\r\n\r\n  HAL_LockTypeDef            Lock;           /*!< I2C locking object                        */\r\n\r\n  __IO HAL_I2C_StateTypeDef  State;          /*!< I2C communication state                   */\r\n\r\n  __IO HAL_I2C_ModeTypeDef   Mode;           /*!< I2C communication mode                    */\r\n\r\n  __IO uint32_t              ErrorCode;      /*!< I2C Error code                            */\r\n\r\n  __IO uint32_t              AddrEventCount; /*!< I2C Address Event counter                 */\r\n}I2C_HandleTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */  \r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup I2C_Exported_Constants I2C Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup I2C_XFEROPTIONS  I2C Sequential Transfer Options\r\n  * @{\r\n  */\r\n#define I2C_NO_OPTION_FRAME             ((uint32_t)0xFFFF0000U)\r\n#define I2C_FIRST_FRAME                 ((uint32_t)I2C_SOFTEND_MODE)\r\n#define I2C_NEXT_FRAME                  ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))\r\n#define I2C_FIRST_AND_LAST_FRAME        ((uint32_t)I2C_AUTOEND_MODE)\r\n#define I2C_LAST_FRAME                  ((uint32_t)I2C_AUTOEND_MODE)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode\r\n  * @{\r\n  */\r\n#define I2C_ADDRESSINGMODE_7BIT         ((uint32_t)0x00000001U)\r\n#define I2C_ADDRESSINGMODE_10BIT        ((uint32_t)0x00000002U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode\r\n  * @{\r\n  */\r\n#define I2C_DUALADDRESS_DISABLE         ((uint32_t)0x00000000U)\r\n#define I2C_DUALADDRESS_ENABLE          I2C_OAR2_OA2EN\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks\r\n  * @{\r\n  */\r\n#define I2C_OA2_NOMASK                  ((uint8_t)0x00U)\r\n#define I2C_OA2_MASK01                  ((uint8_t)0x01U)\r\n#define I2C_OA2_MASK02                  ((uint8_t)0x02U)\r\n#define I2C_OA2_MASK03                  ((uint8_t)0x03U)\r\n#define I2C_OA2_MASK04                  ((uint8_t)0x04U)\r\n#define I2C_OA2_MASK05                  ((uint8_t)0x05U)\r\n#define I2C_OA2_MASK06                  ((uint8_t)0x06U)\r\n#define I2C_OA2_MASK07                  ((uint8_t)0x07U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode\r\n  * @{\r\n  */\r\n#define I2C_GENERALCALL_DISABLE         ((uint32_t)0x00000000U)\r\n#define I2C_GENERALCALL_ENABLE          I2C_CR1_GCEN\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode\r\n  * @{\r\n  */\r\n#define I2C_NOSTRETCH_DISABLE           ((uint32_t)0x00000000U)\r\n#define I2C_NOSTRETCH_ENABLE            I2C_CR1_NOSTRETCH\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size\r\n  * @{\r\n  */\r\n#define I2C_MEMADD_SIZE_8BIT            ((uint32_t)0x00000001U)\r\n#define I2C_MEMADD_SIZE_16BIT           ((uint32_t)0x00000002U)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup I2C_XferDirection I2C Transfer Direction\r\n  * @{\r\n  */\r\n#define I2C_DIRECTION_TRANSMIT          ((uint32_t)0x00000000U)\r\n#define I2C_DIRECTION_RECEIVE           ((uint32_t)0x00000001U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode\r\n  * @{\r\n  */\r\n#define  I2C_RELOAD_MODE                I2C_CR2_RELOAD\r\n#define  I2C_AUTOEND_MODE               I2C_CR2_AUTOEND\r\n#define  I2C_SOFTEND_MODE               ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode\r\n  * @{\r\n  */\r\n#define  I2C_NO_STARTSTOP               ((uint32_t)0x00000000U)\r\n#define  I2C_GENERATE_STOP              I2C_CR2_STOP\r\n#define  I2C_GENERATE_START_READ        (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)\r\n#define  I2C_GENERATE_START_WRITE       I2C_CR2_START\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition\r\n  * @brief I2C Interrupt definition\r\n  *        Elements values convention: 0xXXXXXXXX\r\n  *           - XXXXXXXX  : Interrupt control mask\r\n  * @{\r\n  */\r\n#define I2C_IT_ERRI                     I2C_CR1_ERRIE\r\n#define I2C_IT_TCI                      I2C_CR1_TCIE\r\n#define I2C_IT_STOPI                    I2C_CR1_STOPIE\r\n#define I2C_IT_NACKI                    I2C_CR1_NACKIE\r\n#define I2C_IT_ADDRI                    I2C_CR1_ADDRIE\r\n#define I2C_IT_RXI                      I2C_CR1_RXIE\r\n#define I2C_IT_TXI                      I2C_CR1_TXIE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2C_Flag_definition I2C Flag definition\r\n  * @{\r\n  */ \r\n#define I2C_FLAG_TXE                    I2C_ISR_TXE\r\n#define I2C_FLAG_TXIS                   I2C_ISR_TXIS\r\n#define I2C_FLAG_RXNE                   I2C_ISR_RXNE\r\n#define I2C_FLAG_ADDR                   I2C_ISR_ADDR\r\n#define I2C_FLAG_AF                     I2C_ISR_NACKF\r\n#define I2C_FLAG_STOPF                  I2C_ISR_STOPF\r\n#define I2C_FLAG_TC                     I2C_ISR_TC\r\n#define I2C_FLAG_TCR                    I2C_ISR_TCR\r\n#define I2C_FLAG_BERR                   I2C_ISR_BERR\r\n#define I2C_FLAG_ARLO                   I2C_ISR_ARLO\r\n#define I2C_FLAG_OVR                    I2C_ISR_OVR\r\n#define I2C_FLAG_PECERR                 I2C_ISR_PECERR\r\n#define I2C_FLAG_TIMEOUT                I2C_ISR_TIMEOUT\r\n#define I2C_FLAG_ALERT                  I2C_ISR_ALERT\r\n#define I2C_FLAG_BUSY                   I2C_ISR_BUSY\r\n#define I2C_FLAG_DIR                    I2C_ISR_DIR\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macros -----------------------------------------------------------*/\r\n  \r\n/** @defgroup I2C_Exported_Macros I2C Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief Reset I2C handle state.\r\n  * @param  __HANDLE__ specifies the I2C Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_I2C_STATE_RESET)\r\n\r\n/** @brief  Enable the specified I2C interrupt.\r\n  * @param  __HANDLE__ specifies the I2C Handle.\r\n  * @param  __INTERRUPT__ specifies the interrupt source to enable.\r\n  *        This parameter can be one of the following values:\r\n  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable\r\n  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable\r\n  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable\r\n  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable\r\n  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable\r\n  *            @arg @ref I2C_IT_RXI   RX interrupt enable\r\n  *            @arg @ref I2C_IT_TXI   TX interrupt enable\r\n  *\r\n  * @retval None\r\n  */\r\n#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))\r\n\r\n/** @brief  Disable the specified I2C interrupt.\r\n  * @param  __HANDLE__ specifies the I2C Handle.\r\n  * @param  __INTERRUPT__ specifies the interrupt source to disable.\r\n  *        This parameter can be one of the following values:\r\n  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable\r\n  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable\r\n  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable\r\n  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable\r\n  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable\r\n  *            @arg @ref I2C_IT_RXI   RX interrupt enable\r\n  *            @arg @ref I2C_IT_TXI   TX interrupt enable\r\n  *   \r\n  * @retval None\r\n  */\r\n#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))\r\n \r\n/** @brief  Check whether the specified I2C interrupt source is enabled or not.\r\n  * @param  __HANDLE__ specifies the I2C Handle.\r\n  * @param  __INTERRUPT__ specifies the I2C interrupt source to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable\r\n  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable\r\n  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable\r\n  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable\r\n  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable\r\n  *            @arg @ref I2C_IT_RXI   RX interrupt enable\r\n  *            @arg @ref I2C_IT_TXI   TX interrupt enable\r\n  *\r\n  * @retval The new state of __INTERRUPT__ (SET or RESET).\r\n  */\r\n#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r\n\r\n/** @brief  Check whether the specified I2C flag is set or not.\r\n  * @param  __HANDLE__ specifies the I2C Handle.\r\n  * @param  __FLAG__ specifies the flag to check.\r\n  *        This parameter can be one of the following values:\r\n  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty\r\n  *            @arg @ref I2C_FLAG_TXIS    Transmit interrupt status\r\n  *            @arg @ref I2C_FLAG_RXNE    Receive data register not empty\r\n  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)\r\n  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag\r\n  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag\r\n  *            @arg @ref I2C_FLAG_TC      Transfer complete (master mode)\r\n  *            @arg @ref I2C_FLAG_TCR     Transfer complete reload\r\n  *            @arg @ref I2C_FLAG_BERR    Bus error\r\n  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost\r\n  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun\r\n  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception\r\n  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag\r\n  *            @arg @ref I2C_FLAG_ALERT   SMBus alert\r\n  *            @arg @ref I2C_FLAG_BUSY    Bus busy\r\n  *            @arg @ref I2C_FLAG_DIR     Transfer direction (slave mode)\r\n  *\r\n  * @retval The new state of __FLAG__ (SET or RESET).\r\n  */\r\n#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)\r\n\r\n/** @brief  Clear the I2C pending flags which are cleared by writing 1 in a specific bit.\r\n  * @param  __HANDLE__ specifies the I2C Handle.\r\n  * @param  __FLAG__ specifies the flag to clear.\r\n  *          This parameter can be any combination of the following values:\r\n  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty\r\n  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)\r\n  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag\r\n  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag\r\n  *            @arg @ref I2C_FLAG_BERR    Bus error\r\n  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost\r\n  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun            \r\n  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception\r\n  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag \r\n  *            @arg @ref I2C_FLAG_ALERT   SMBus alert\r\n  *\r\n  * @retval None\r\n  */\r\n#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \\\r\n                                                                                 : ((__HANDLE__)->Instance->ICR = (__FLAG__)))\r\n \r\n/** @brief  Enable the specified I2C peripheral.\r\n  * @param  __HANDLE__ specifies the I2C Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_I2C_ENABLE(__HANDLE__)                            (SET_BIT((__HANDLE__)->Instance->CR1,  I2C_CR1_PE))\r\n\r\n/** @brief  Disable the specified I2C peripheral.\r\n  * @param  __HANDLE__ specifies the I2C Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_I2C_DISABLE(__HANDLE__)                           (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))\r\n\r\n/** @brief  Generate a Non-Acknowledge I2C peripheral in Slave mode.\r\n  * @param  __HANDLE__: specifies the I2C Handle. \r\n  * @retval None\r\n  */\r\n#define __HAL_I2C_GENERATE_NACK(__HANDLE__)                     (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Include I2C HAL Extended module */\r\n#include \"stm32f7xx_hal_i2c_ex.h\"\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup I2C_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions\r\n  * @{\r\n  */\r\n/* Initialization and de-initialization functions******************************/\r\nHAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);\r\nHAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);\r\nvoid HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);\r\nvoid HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions\r\n  * @{\r\n  */\r\n/* IO operation functions  ****************************************************/\r\n /******* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);\r\n\r\n /******* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\r\n\r\nHAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r\nHAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r\nHAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r\nHAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\r\nHAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);\r\nHAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);\r\nHAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);\r\n\r\n /******* Non-Blocking mode: DMA */\r\nHAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks\r\n * @{\r\n */\r\n/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */\r\nvoid HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);\r\nvoid HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);\r\nvoid HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);\r\nvoid HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);\r\nvoid HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);\r\nvoid HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);\r\nvoid HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);\r\nvoid HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);\r\nvoid HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);\r\nvoid HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);\r\nvoid HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);\r\nvoid HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions\r\n  * @{\r\n  */\r\n/* Peripheral State, Mode and Error functions  *********************************/\r\nHAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);\r\nHAL_I2C_ModeTypeDef  HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);\r\nuint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup I2C_Private_Constants I2C Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup I2C_Private_Macro I2C Private Macros\r\n  * @{\r\n  */\r\n\r\n#define IS_I2C_ADDRESSING_MODE(MODE)    (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \\\r\n                                         ((MODE) == I2C_ADDRESSINGMODE_10BIT))\r\n\r\n#define IS_I2C_DUAL_ADDRESS(ADDRESS)    (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \\\r\n                                         ((ADDRESS) == I2C_DUALADDRESS_ENABLE))\r\n\r\n#define IS_I2C_OWN_ADDRESS2_MASK(MASK)  (((MASK) == I2C_OA2_NOMASK)  || \\\r\n                                         ((MASK) == I2C_OA2_MASK01) || \\\r\n                                         ((MASK) == I2C_OA2_MASK02) || \\\r\n                                         ((MASK) == I2C_OA2_MASK03) || \\\r\n                                         ((MASK) == I2C_OA2_MASK04) || \\\r\n                                         ((MASK) == I2C_OA2_MASK05) || \\\r\n                                         ((MASK) == I2C_OA2_MASK06) || \\\r\n                                         ((MASK) == I2C_OA2_MASK07))\r\n\r\n#define IS_I2C_GENERAL_CALL(CALL)       (((CALL) == I2C_GENERALCALL_DISABLE) || \\\r\n                                         ((CALL) == I2C_GENERALCALL_ENABLE))\r\n\r\n#define IS_I2C_NO_STRETCH(STRETCH)      (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \\\r\n                                         ((STRETCH) == I2C_NOSTRETCH_ENABLE))\r\n\r\n#define IS_I2C_MEMADD_SIZE(SIZE)        (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \\\r\n                                         ((SIZE) == I2C_MEMADD_SIZE_16BIT))\r\n\r\n#define IS_TRANSFER_MODE(MODE)          (((MODE) == I2C_RELOAD_MODE)   || \\\r\n                                         ((MODE) == I2C_AUTOEND_MODE) || \\\r\n                                         ((MODE) == I2C_SOFTEND_MODE))\r\n\r\n#define IS_TRANSFER_REQUEST(REQUEST)    (((REQUEST) == I2C_GENERATE_STOP)        || \\\r\n                                         ((REQUEST) == I2C_GENERATE_START_READ)  || \\\r\n                                         ((REQUEST) == I2C_GENERATE_START_WRITE) || \\\r\n                                         ((REQUEST) == I2C_NO_STARTSTOP))\r\n\r\n#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)  (((REQUEST) == I2C_FIRST_FRAME)          || \\\r\n                                                   ((REQUEST) == I2C_NEXT_FRAME)           || \\\r\n                                                   ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \\\r\n                                                   ((REQUEST) == I2C_LAST_FRAME))\r\n\r\n#define I2C_RESET_CR2(__HANDLE__)                 ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))\r\n\r\n#define I2C_GET_ADDR_MATCH(__HANDLE__)            (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16)\r\n#define I2C_GET_DIR(__HANDLE__)                   (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16)\r\n#define I2C_GET_STOP_MODE(__HANDLE__)             ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)\r\n#define I2C_GET_OWN_ADDRESS1(__HANDLE__)          ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)\r\n#define I2C_GET_OWN_ADDRESS2(__HANDLE__)          ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)\r\n\r\n#define IS_I2C_OWN_ADDRESS1(ADDRESS1)             ((ADDRESS1) <= (uint32_t)0x000003FF)\r\n#define IS_I2C_OWN_ADDRESS2(ADDRESS2)             ((ADDRESS2) <= (uint16_t)0x00FF)\r\n\r\n#define I2C_MEM_ADD_MSB(__ADDRESS__)              ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))\r\n#define I2C_MEM_ADD_LSB(__ADDRESS__)              ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))\r\n\r\n#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \\\r\n                                                          (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private Functions ---------------------------------------------------------*/\r\n/** @defgroup I2C_Private_Functions I2C Private Functions\r\n  * @{\r\n  */\r\n/* Private functions are defined in stm32f7xx_hal_i2c.c file */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n\r\n#endif /* __STM32F7xx_HAL_I2C_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_i2c_ex.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of I2C HAL Extension module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_I2C_EX_H\r\n#define __STM32F7xx_HAL_I2C_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup I2CEx\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup I2CEx_Exported_Constants I2CEx Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup I2CEx_Analog_Filter I2CEx Analog Filter\r\n  * @{\r\n  */\r\n#define I2C_ANALOGFILTER_ENABLE        ((uint32_t)0x00000000U)\r\n#define I2C_ANALOGFILTER_DISABLE       I2C_CR1_ANFOFF\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus\r\n  * @{\r\n  */\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n\r\n#define I2C_FASTMODEPLUS_PB6          SYSCFG_PMC_I2C_PB6_FMP\r\n#define I2C_FASTMODEPLUS_PB7          SYSCFG_PMC_I2C_PB7_FMP\r\n#define I2C_FASTMODEPLUS_PB8          SYSCFG_PMC_I2C_PB8_FMP\r\n#define I2C_FASTMODEPLUS_PB9          SYSCFG_PMC_I2C_PB9_FMP\r\n\r\n#define I2C_FASTMODEPLUS_I2C1         SYSCFG_PMC_I2C1_FMP\r\n#define I2C_FASTMODEPLUS_I2C2         SYSCFG_PMC_I2C2_FMP\r\n#define I2C_FASTMODEPLUS_I2C3         SYSCFG_PMC_I2C3_FMP\r\n#define I2C_FASTMODEPLUS_I2C4         SYSCFG_PMC_I2C4_FMP\r\n\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx  */\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/* Peripheral Control methods  ************************************************/\r\nHAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);\r\nHAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\nvoid HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);\r\nvoid HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup I2C_Private_Constants I2C Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup I2C_Private_Macro I2C Private Macros\r\n  * @{\r\n  */\r\n#define IS_I2C_ANALOG_FILTER(FILTER)    (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \\\r\n                                          ((FILTER) == I2C_ANALOGFILTER_DISABLE))\r\n\r\n#define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000FU)\r\n\r\n#if defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) && defined(SYSCFG_PMC_I2C3_FMP) && defined(SYSCFG_PMC_I2C4_FMP) \r\n#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \\\r\n\t\t\t\t\t\t\t\t\t\t (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4))\r\n#elif defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) && defined(SYSCFG_PMC_I2C3_FMP)\r\n#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \\\r\n\t\t\t\t\t\t\t\t\t\t (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3))\r\n#elif defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP)\r\n#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2))\r\n#elif defined(SYSCFG_PMC_I2C1_FMP)\r\n#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \\\r\n                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1))\r\n#endif /* SYSCFG_PMC_I2C1_FMP && SYSCFG_PMC_I2C2_FMP && SYSCFG_PMC_I2C3_FMP && SYSCFG_PMC_I2C4_FMP */\r\n/**\r\n  * @}\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private Functions ---------------------------------------------------------*/\r\n/** @defgroup I2C_Private_Functions I2C Private Functions\r\n  * @{\r\n  */\r\n/* Private functions are defined in stm32f7xx_hal_i2c_ex.c file */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_I2C_EX_H */\r\n\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2s.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_i2s.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of I2S HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_I2S_H\r\n#define __STM32F7xx_HAL_I2S_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"  \r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup I2S\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/ \r\n/** @defgroup I2S_Exported_Types I2S Exported Types\r\n  * @{\r\n  */\r\n\r\n/** \r\n  * @brief I2S Init structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t Mode;                /*!< Specifies the I2S operating mode.\r\n                                     This parameter can be a value of @ref I2S_Mode */\r\n\r\n  uint32_t Standard;            /*!< Specifies the standard used for the I2S communication.\r\n                                     This parameter can be a value of @ref I2S_Standard */\r\n\r\n  uint32_t DataFormat;          /*!< Specifies the data format for the I2S communication.\r\n                                     This parameter can be a value of @ref I2S_Data_Format */\r\n\r\n  uint32_t MCLKOutput;          /*!< Specifies whether the I2S MCLK output is enabled or not.\r\n                                     This parameter can be a value of @ref I2S_MCLK_Output */\r\n\r\n  uint32_t AudioFreq;           /*!< Specifies the frequency selected for the I2S communication.\r\n                                     This parameter can be a value of @ref I2S_Audio_Frequency */\r\n\r\n  uint32_t CPOL;                /*!< Specifies the idle state of the I2S clock.\r\n                                     This parameter can be a value of @ref I2S_Clock_Polarity */\r\n   \r\n  uint32_t ClockSource;         /*!< Specifies the I2S Clock Source.\r\n                                     This parameter can be a value of @ref I2S_Clock_Source */\r\n}I2S_InitTypeDef;\r\n\r\n/** \r\n  * @brief  HAL State structures definition  \r\n  */ \r\ntypedef enum\r\n{\r\n  HAL_I2S_STATE_RESET      = 0x00U,  /*!< I2S not yet initialized or disabled                */\r\n  HAL_I2S_STATE_READY      = 0x01U,  /*!< I2S initialized and ready for use                  */\r\n  HAL_I2S_STATE_BUSY       = 0x02U,  /*!< I2S internal process is ongoing                    */   \r\n  HAL_I2S_STATE_BUSY_TX    = 0x03U,  /*!< Data Transmission process is ongoing               */ \r\n  HAL_I2S_STATE_BUSY_RX    = 0x04U,  /*!< Data Reception process is ongoing                  */\r\n  HAL_I2S_STATE_BUSY_TX_RX = 0x05U,  /*!< Data Transmission and Reception process is ongoing */\r\n  HAL_I2S_STATE_TIMEOUT    = 0x06U,  /*!< I2S timeout state                                  */  \r\n  HAL_I2S_STATE_ERROR      = 0x07U   /*!< I2S error state                                    */      \r\n                                                                        \r\n}HAL_I2S_StateTypeDef;\r\n\r\n/** \r\n  * @brief I2S handle Structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  SPI_TypeDef                *Instance;    /* I2S registers base address */\r\n\r\n  I2S_InitTypeDef            Init;         /* I2S communication parameters */\r\n  \r\n  uint16_t                   *pTxBuffPtr;  /* Pointer to I2S Tx transfer buffer */\r\n  \r\n  __IO uint16_t              TxXferSize;   /* I2S Tx transfer size */\r\n  \r\n  __IO uint16_t              TxXferCount;  /* I2S Tx transfer Counter */\r\n  \r\n  uint16_t                   *pRxBuffPtr;  /* Pointer to I2S Rx transfer buffer */\r\n  \r\n  __IO uint16_t              RxXferSize;   /* I2S Rx transfer size */\r\n  \r\n  __IO uint16_t              RxXferCount;  /* I2S Rx transfer counter \r\n                                              (This field is initialized at the \r\n                                               same value as transfer size at the \r\n                                               beginning of the transfer and \r\n                                               decremented when a sample is received. \r\n                                               NbSamplesReceived = RxBufferSize-RxBufferCount) */\r\n\r\n  DMA_HandleTypeDef          *hdmatx;      /* I2S Tx DMA handle parameters */\r\n\r\n  DMA_HandleTypeDef          *hdmarx;      /* I2S Rx DMA handle parameters */\r\n  \r\n  __IO HAL_LockTypeDef       Lock;         /* I2S locking object */\r\n  \r\n  __IO HAL_I2S_StateTypeDef  State;        /* I2S communication state */\r\n\r\n  __IO uint32_t  ErrorCode;                /* I2S Error code                 */\r\n\r\n}I2S_HandleTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup I2S_Exported_Constants I2S Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup I2S_Error_Defintion I2S_Error_Defintion\r\n  *@brief     I2S Error Code\r\n  * @{\r\n  */\r\n#define HAL_I2S_ERROR_NONE      ((uint32_t)0x00000000U)  /*!< No error           */\r\n#define HAL_I2S_ERROR_TIMEOUT   ((uint32_t)0x00000001U)  /*!< Timeout error      */\r\n#define HAL_I2S_ERROR_OVR       ((uint32_t)0x00000002U)  /*!< OVR error          */\r\n#define HAL_I2S_ERROR_UDR       ((uint32_t)0x00000004U)  /*!< UDR error          */\r\n#define HAL_I2S_ERROR_DMA       ((uint32_t)0x00000008U)  /*!< DMA transfer error */\r\n#define HAL_I2S_ERROR_UNKNOW    ((uint32_t)0x00000010U)  /*!< Unknow Error error */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/** @defgroup I2S_Clock_Source I2S Clock Source\r\n  * @{\r\n  */\r\n#define I2S_CLOCK_EXTERNAL                ((uint32_t)0x00000001U)\r\n#define I2S_CLOCK_PLL                     ((uint32_t)0x00000002U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2S_Mode I2S Mode\r\n  * @{\r\n  */\r\n#define I2S_MODE_SLAVE_TX                ((uint32_t)0x00000000U)\r\n#define I2S_MODE_SLAVE_RX                ((uint32_t)0x00000100U)\r\n#define I2S_MODE_MASTER_TX               ((uint32_t)0x00000200U)\r\n#define I2S_MODE_MASTER_RX               ((uint32_t)0x00000300U)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup I2S_Standard I2S Standard\r\n  * @{\r\n  */\r\n#define I2S_STANDARD_PHILIPS             ((uint32_t)0x00000000U)\r\n#define I2S_STANDARD_MSB                 ((uint32_t)0x00000010U)\r\n#define I2S_STANDARD_LSB                 ((uint32_t)0x00000020U)\r\n#define I2S_STANDARD_PCM_SHORT           ((uint32_t)0x00000030U)\r\n#define I2S_STANDARD_PCM_LONG            ((uint32_t)0x000000B0U)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup I2S_Data_Format I2S Data Format\r\n  * @{\r\n  */\r\n#define I2S_DATAFORMAT_16B               ((uint32_t)0x00000000U)\r\n#define I2S_DATAFORMAT_16B_EXTENDED      ((uint32_t)0x00000001U)\r\n#define I2S_DATAFORMAT_24B               ((uint32_t)0x00000003U)\r\n#define I2S_DATAFORMAT_32B               ((uint32_t)0x00000005U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2S_MCLK_Output I2S Mclk Output\r\n  * @{\r\n  */\r\n#define I2S_MCLKOUTPUT_ENABLE           ((uint32_t)SPI_I2SPR_MCKOE)\r\n#define I2S_MCLKOUTPUT_DISABLE          ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2S_Audio_Frequency I2S Audio Frequency\r\n  * @{\r\n  */\r\n#define I2S_AUDIOFREQ_192K               ((uint32_t)192000U)\r\n#define I2S_AUDIOFREQ_96K                ((uint32_t)96000U)\r\n#define I2S_AUDIOFREQ_48K                ((uint32_t)48000U)\r\n#define I2S_AUDIOFREQ_44K                ((uint32_t)44100U)\r\n#define I2S_AUDIOFREQ_32K                ((uint32_t)32000U)\r\n#define I2S_AUDIOFREQ_22K                ((uint32_t)22050U)\r\n#define I2S_AUDIOFREQ_16K                ((uint32_t)16000U)\r\n#define I2S_AUDIOFREQ_11K                ((uint32_t)11025U)\r\n#define I2S_AUDIOFREQ_8K                 ((uint32_t)8000U)\r\n#define I2S_AUDIOFREQ_DEFAULT            ((uint32_t)2U)\r\n/**\r\n  * @}\r\n  */\r\n            \r\n\r\n/** @defgroup I2S_Clock_Polarity I2S Clock Polarity\r\n  * @{\r\n  */\r\n#define I2S_CPOL_LOW                    ((uint32_t)0x00000000U)\r\n#define I2S_CPOL_HIGH                   ((uint32_t)SPI_I2SCFGR_CKPOL)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition\r\n  * @{\r\n  */\r\n#define I2S_IT_TXE                      SPI_CR2_TXEIE\r\n#define I2S_IT_RXNE                     SPI_CR2_RXNEIE\r\n#define I2S_IT_ERR                      SPI_CR2_ERRIE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2S_Flags_Definition I2S Flags Definition\r\n  * @{\r\n  */ \r\n#define I2S_FLAG_TXE                    SPI_SR_TXE\r\n#define I2S_FLAG_RXNE                   SPI_SR_RXNE\r\n\r\n#define I2S_FLAG_UDR                    SPI_SR_UDR\r\n#define I2S_FLAG_OVR                    SPI_SR_OVR\r\n#define I2S_FLAG_FRE                    SPI_SR_FRE\r\n\r\n#define I2S_FLAG_CHSIDE                 SPI_SR_CHSIDE\r\n#define I2S_FLAG_BSY                    SPI_SR_BSY\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/* Exported macros -----------------------------------------------------------*/\r\n/** @defgroup I2S_Exported_Macros I2S Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief  Reset I2S handle state\r\n  * @param  __HANDLE__: specifies the I2S handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)\r\n\r\n/** @brief  Enable or disable the specified SPI peripheral (in I2S mode).\r\n  * @param  __HANDLE__: specifies the I2S Handle. \r\n  * @retval None\r\n  */\r\n#define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)\r\n#define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= ~SPI_I2SCFGR_I2SE)\r\n\r\n/** @brief  Enable or disable the specified I2S interrupts.\r\n  * @param  __HANDLE__: specifies the I2S Handle.\r\n  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.\r\n  *        This parameter can be one of the following values:\r\n  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable\r\n  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable\r\n  *            @arg I2S_IT_ERR: Error interrupt enable\r\n  * @retval None\r\n  */  \r\n#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))\r\n#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= ~(__INTERRUPT__))\r\n \r\n/** @brief  Checks if the specified I2S interrupt source is enabled or disabled.\r\n  * @param  __HANDLE__: specifies the I2S Handle.\r\n  *         This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.\r\n  * @param  __INTERRUPT__: specifies the I2S interrupt source to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable\r\n  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable\r\n  *            @arg I2S_IT_ERR: Error interrupt enable\r\n  * @retval The new state of __IT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r\n\r\n/** @brief  Checks whether the specified I2S flag is set or not.\r\n  * @param  __HANDLE__: specifies the I2S Handle.\r\n  * @param  __FLAG__: specifies the flag to check.\r\n  *        This parameter can be one of the following values:\r\n  *            @arg I2S_FLAG_RXNE: Receive buffer not empty flag\r\n  *            @arg I2S_FLAG_TXE: Transmit buffer empty flag\r\n  *            @arg I2S_FLAG_UDR: Underrun flag\r\n  *            @arg I2S_FLAG_OVR: Overrun flag\r\n  *            @arg I2S_FLAG_FRE: Frame error flag\r\n  *            @arg I2S_FLAG_CHSIDE: Channel Side flag\r\n  *            @arg I2S_FLAG_BSY: Busy flag\r\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))\r\n\r\n/** @brief Clears the I2S OVR pending flag.\r\n  * @param  __HANDLE__: specifies the I2S Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__)     \\\r\n  do{                                           \\\r\n    __IO uint32_t tmpreg;                       \\\r\n    tmpreg = (__HANDLE__)->Instance->DR;        \\\r\n    tmpreg = (__HANDLE__)->Instance->SR;        \\\r\n    UNUSED(tmpreg);                             \\\r\n  } while(0)\r\n    \r\n/** @brief Clears the I2S UDR pending flag.\r\n  * @param  __HANDLE__: specifies the I2S Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)     \\\r\n  do{                                             \\\r\n  __IO uint32_t tmpreg;                         \\\r\n  tmpreg = (__HANDLE__)->Instance->SR;          \\\r\n  UNUSED(tmpreg);                               \\\r\n  } while(0)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup I2S_Exported_Functions  I2S Exported Functions\r\n  * @{\r\n  */\r\n                                                \r\n/** @addtogroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions \r\n  * @{\r\n  */\r\n\r\n/* Initialization and de-initialization functions *****************************/\r\nHAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);\r\nHAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);\r\nvoid HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);\r\nvoid HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup I2S_Exported_Functions_Group2 Input and Output operation functions \r\n  * @{\r\n  */\r\n/* I/O operation functions  ***************************************************/\r\n /* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);\r\n\r\n /* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);\r\nvoid HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);\r\n\r\n/* Non-Blocking mode: DMA */\r\nHAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);\r\n\r\nHAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);\r\nHAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);\r\nHAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);\r\n\r\n/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/\r\nvoid HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);\r\nvoid HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);\r\nvoid HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);\r\nvoid HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);\r\nvoid HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions\r\n  * @{\r\n  */\r\n/* Peripheral Control and State functions  ************************************/\r\nHAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);\r\nuint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup I2S_Private_Constants I2S Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup I2S_Private_Macros I2S Private Macros\r\n  * @{\r\n  */\r\n#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \\\r\n                                   ((CLOCK) == I2S_CLOCK_PLL))\r\n\t\t\t\t\t\t\t\t   \r\n#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \\\r\n                           ((MODE) == I2S_MODE_SLAVE_RX) || \\\r\n                           ((MODE) == I2S_MODE_MASTER_TX)|| \\\r\n                           ((MODE) == I2S_MODE_MASTER_RX))\r\n                           \r\n#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS)   || \\\r\n                                   ((STANDARD) == I2S_STANDARD_MSB)       || \\\r\n                                   ((STANDARD) == I2S_STANDARD_LSB)       || \\\r\n                                   ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \\\r\n                                   ((STANDARD) == I2S_STANDARD_PCM_LONG))\r\n\r\n#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B)          || \\\r\n                                    ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \\\r\n                                    ((FORMAT) == I2S_DATAFORMAT_24B)          || \\\r\n                                    ((FORMAT) == I2S_DATAFORMAT_32B))\r\n\r\n#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \\\r\n                                    ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))\r\n                                    \r\n#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \\\r\n                                 ((FREQ) <= I2S_AUDIOFREQ_192K)) || \\\r\n                                 ((FREQ) == I2S_AUDIOFREQ_DEFAULT))\r\n\t\t\t\t\t\t\t\t \r\n#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \\\r\n                           ((CPOL) == I2S_CPOL_HIGH))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */  \r\n\t\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n\r\n#endif /* __STM32F7xx_HAL_I2S_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_irda.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_irda.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of IRDA HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_IRDA_H\r\n#define __STM32F7xx_HAL_IRDA_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup IRDA\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/ \r\n/** @defgroup IRDA_Exported_Types IRDA Exported Types\r\n  * @{\r\n  */\r\n/** \r\n  * @brief IRDA Init Structure definition  \r\n  */ \r\ntypedef struct\r\n{\r\n  uint32_t BaudRate;                  /*!< This member configures the IRDA communication baud rate.\r\n                                           The baud rate register is computed using the following formula:\r\n                                              Baud Rate Register = ((PCLKx) / ((hirda->Init.BaudRate))) */\r\n\r\n  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.\r\n                                           This parameter can be a value of @ref IRDAEx_Word_Length */\r\n\r\n  uint32_t Parity;                    /*!< Specifies the parity mode.\r\n                                           This parameter can be a value of @ref IRDA_Parity\r\n                                           @note When parity is enabled, the computed parity is inserted\r\n                                                 at the MSB position of the transmitted data (9th bit when\r\n                                                 the word length is set to 9 data bits; 8th bit when the\r\n                                                 word length is set to 8 data bits). */\r\n \r\n  uint16_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.\r\n                                           This parameter can be a value of @ref IRDA_Transfer_Mode */\r\n  \r\n  uint8_t  Prescaler;                 /*!< Specifies the Prescaler value for dividing the UART/USART source clock\r\n                                           to achieve low-power frequency.\r\n                                           @note Prescaler value 0 is forbidden */\r\n  \r\n  uint16_t PowerMode;                 /*!< Specifies the IRDA power mode.\r\n                                           This parameter can be a value of @ref IRDA_Low_Power */\r\n}IRDA_InitTypeDef;\r\n\r\n/** \r\n  * @brief HAL IRDA State structures definition \r\n  * @note  HAL IRDA State value is a combination of 2 different substates: gState and RxState.\r\n  *        - gState contains IRDA state information related to global Handle management \r\n  *          and also information related to Tx operations.\r\n  *          gState value coding follow below described bitmap :\r\n  *          b7-b6  Error information \r\n  *             00 : No Error\r\n  *             01 : (Not Used)\r\n  *             10 : Timeout\r\n  *             11 : Error\r\n  *          b5     IP initilisation status\r\n  *             0  : Reset (IP not initialized)\r\n  *             1  : Init done (IP not initialized. HAL IRDA Init function already called)\r\n  *          b4-b3  (not used)\r\n  *             xx : Should be set to 00\r\n  *          b2     Intrinsic process state\r\n  *             0  : Ready\r\n  *             1  : Busy (IP busy with some configuration or internal operations)\r\n  *          b1     (not used)\r\n  *             x  : Should be set to 0\r\n  *          b0     Tx state\r\n  *             0  : Ready (no Tx operation ongoing)\r\n  *             1  : Busy (Tx operation ongoing)\r\n  *        - RxState contains information related to Rx operations.\r\n  *          RxState value coding follow below described bitmap :\r\n  *          b7-b6  (not used)\r\n  *             xx : Should be set to 00\r\n  *          b5     IP initilisation status\r\n  *             0  : Reset (IP not initialized)\r\n  *             1  : Init done (IP not initialized)\r\n  *          b4-b2  (not used)\r\n  *            xxx : Should be set to 000\r\n  *          b1     Rx state\r\n  *             0  : Ready (no Rx operation ongoing)\r\n  *             1  : Busy (Rx operation ongoing)\r\n  *          b0     (not used)\r\n  *             x  : Should be set to 0.\r\n  */ \r\ntypedef enum\r\n{\r\n  HAL_IRDA_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized \r\n                                                   Value is allowed for gState and RxState */\r\n  HAL_IRDA_STATE_READY             = 0x20U,    /*!< Peripheral Initialized and ready for use \r\n                                                   Value is allowed for gState and RxState */\r\n  HAL_IRDA_STATE_BUSY              = 0x24U,    /*!< An internal process is ongoing \r\n                                                   Value is allowed for gState only */\r\n  HAL_IRDA_STATE_BUSY_TX           = 0x21U,    /*!< Data Transmission process is ongoing \r\n                                                   Value is allowed for gState only */\r\n  HAL_IRDA_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing \r\n                                                   Value is allowed for RxState only */\r\n  HAL_IRDA_STATE_BUSY_TX_RX        = 0x23U,    /*!< Data Transmission and Reception process is ongoing \r\n                                                   Not to be used for neither gState nor RxState.\r\n                                                   Value is result of combination (Or) between gState and RxState values */\r\n  HAL_IRDA_STATE_TIMEOUT           = 0xA0U,    /*!< Timeout state \r\n                                                   Value is allowed for gState only */\r\n  HAL_IRDA_STATE_ERROR             = 0xE0U     /*!< Error \r\n                                                   Value is allowed for gState only */\r\n}HAL_IRDA_StateTypeDef;\r\n\r\n/**\r\n  * @brief IRDA clock sources definition\r\n  */\r\ntypedef enum\r\n{\r\n  IRDA_CLOCKSOURCE_PCLK1      = 0x00U,    /*!< PCLK1 clock source  */\r\n  IRDA_CLOCKSOURCE_PCLK2      = 0x01U,    /*!< PCLK2 clock source  */\r\n  IRDA_CLOCKSOURCE_HSI        = 0x02U,    /*!< HSI clock source    */\r\n  IRDA_CLOCKSOURCE_SYSCLK     = 0x04U,    /*!< SYSCLK clock source */\r\n  IRDA_CLOCKSOURCE_LSE        = 0x08U     /*!< LSE clock source     */\r\n}IRDA_ClockSourceTypeDef;\r\n\r\n/** \r\n  * @brief  IRDA handle Structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  USART_TypeDef            *Instance;        /* IRDA registers base address        */\r\n\r\n  IRDA_InitTypeDef         Init;             /* IRDA communication parameters      */\r\n\r\n  uint8_t                  *pTxBuffPtr;      /* Pointer to IRDA Tx transfer Buffer */\r\n\r\n  uint16_t                 TxXferSize;       /* IRDA Tx Transfer size              */\r\n\r\n  uint16_t                 TxXferCount;      /* IRDA Tx Transfer Counter           */\r\n\r\n  uint8_t                  *pRxBuffPtr;      /* Pointer to IRDA Rx transfer Buffer */\r\n\r\n  uint16_t                 RxXferSize;       /* IRDA Rx Transfer size              */\r\n\r\n  uint16_t                 RxXferCount;      /* IRDA Rx Transfer Counter           */\r\n\r\n  uint16_t                 Mask;             /* IRDA RX RDR register mask         */\r\n\r\n  DMA_HandleTypeDef        *hdmatx;          /* IRDA Tx DMA Handle parameters      */\r\n\r\n  DMA_HandleTypeDef        *hdmarx;          /* IRDA Rx DMA Handle parameters      */\r\n\r\n  HAL_LockTypeDef          Lock;             /* Locking object                     */\r\n\r\n  __IO HAL_IRDA_StateTypeDef  gState;           /* IRDA state information related to global Handle management \r\n                                                   and also related to Tx operations.\r\n                                                   This parameter can be a value of @ref HAL_IRDA_StateTypeDef */\r\n\r\n  __IO HAL_IRDA_StateTypeDef  RxState;          /* IRDA state information related to Rx operations.\r\n                                                   This parameter can be a value of @ref HAL_IRDA_StateTypeDef */\r\n\r\n  __IO uint32_t    ErrorCode;   /* IRDA Error code                    */\r\n\r\n}IRDA_HandleTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** \r\n  * @brief  IRDA Configuration enumeration values definition  \r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup IRDA_Exported_Constants IRDA Exported constants\r\n  * @{\r\n  */\r\n/** @defgroup IRDA_Error_Code IRDA Error Code\r\n  * @brief    IRDA Error Code \r\n  * @{\r\n  */ \r\n\r\n#define HAL_IRDA_ERROR_NONE      ((uint32_t)0x00000000U)    /*!< No error            */\r\n#define HAL_IRDA_ERROR_PE        ((uint32_t)0x00000001U)    /*!< Parity error        */\r\n#define HAL_IRDA_ERROR_NE        ((uint32_t)0x00000002U)    /*!< Noise error         */\r\n#define HAL_IRDA_ERROR_FE        ((uint32_t)0x00000004U)    /*!< frame error         */\r\n#define HAL_IRDA_ERROR_ORE       ((uint32_t)0x00000008U)    /*!< Overrun error       */\r\n#define HAL_IRDA_ERROR_DMA       ((uint32_t)0x00000010U)    /*!< DMA transfer error  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup IRDA_Parity IRDA Parity\r\n  * @{\r\n  */ \r\n#define IRDA_PARITY_NONE                    ((uint32_t)0x0000U)\r\n#define IRDA_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)\r\n#define IRDA_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode\r\n  * @{\r\n  */ \r\n#define IRDA_MODE_RX                        ((uint32_t)USART_CR1_RE)\r\n#define IRDA_MODE_TX                        ((uint32_t)USART_CR1_TE)\r\n#define IRDA_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup IRDA_Low_Power IRDA Low Power\r\n  * @{\r\n  */\r\n#define IRDA_POWERMODE_NORMAL                    ((uint32_t)0x0000U)\r\n#define IRDA_POWERMODE_LOWPOWER                  ((uint32_t)USART_CR3_IRLP)\r\n/**\r\n  * @}\r\n  */\r\n    \r\n /** @defgroup IRDA_State IRDA State\r\n  * @{\r\n  */ \r\n#define IRDA_STATE_DISABLE                  ((uint32_t)0x0000U)\r\n#define IRDA_STATE_ENABLE                   ((uint32_t)USART_CR1_UE)\r\n/**\r\n  * @}\r\n  */\r\n\r\n /** @defgroup IRDA_Mode IRDA Mode\r\n  * @{\r\n  */ \r\n#define IRDA_MODE_DISABLE                  ((uint32_t)0x0000U)\r\n#define IRDA_MODE_ENABLE                   ((uint32_t)USART_CR3_IREN)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup IRDA_One_Bit IRDA One Bit\r\n  * @{\r\n  */\r\n#define IRDA_ONE_BIT_SAMPLE_DISABLE          ((uint32_t)0x00000000U)\r\n#define IRDA_ONE_BIT_SAMPLE_ENABLE           ((uint32_t)USART_CR3_ONEBIT)\r\n/**\r\n  * @}\r\n  */  \r\n  \r\n/** @defgroup IRDA_DMA_Tx IRDA DMA Tx\r\n  * @{\r\n  */\r\n#define IRDA_DMA_TX_DISABLE          ((uint32_t)0x00000000U)\r\n#define IRDA_DMA_TX_ENABLE           ((uint32_t)USART_CR3_DMAT)\r\n/**\r\n  * @}\r\n  */  \r\n  \r\n/** @defgroup IRDA_DMA_Rx IRDA DMA Rx\r\n  * @{\r\n  */\r\n#define IRDA_DMA_RX_DISABLE           ((uint32_t)0x0000U)\r\n#define IRDA_DMA_RX_ENABLE            ((uint32_t)USART_CR3_DMAR)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup IRDA_Flags IRDA Flags\r\n  *        Elements values convention: 0xXXXX\r\n  *           - 0xXXXX  : Flag mask in the ISR register\r\n  * @{\r\n  */\r\n#define IRDA_FLAG_REACK                     ((uint32_t)0x00400000U)\r\n#define IRDA_FLAG_TEACK                     ((uint32_t)0x00200000U)  \r\n#define IRDA_FLAG_BUSY                      ((uint32_t)0x00010000U)\r\n#define IRDA_FLAG_ABRF                      ((uint32_t)0x00008000U)  \r\n#define IRDA_FLAG_ABRE                      ((uint32_t)0x00004000U)\r\n#define IRDA_FLAG_TXE                       ((uint32_t)0x00000080U)\r\n#define IRDA_FLAG_TC                        ((uint32_t)0x00000040U)\r\n#define IRDA_FLAG_RXNE                      ((uint32_t)0x00000020U)\r\n#define IRDA_FLAG_ORE                       ((uint32_t)0x00000008U)\r\n#define IRDA_FLAG_NE                        ((uint32_t)0x00000004U)\r\n#define IRDA_FLAG_FE                        ((uint32_t)0x00000002U)\r\n#define IRDA_FLAG_PE                        ((uint32_t)0x00000001U)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup IRDA_Interrupt_definition IRDA Interrupt definition\r\n  *        Elements values convention: 0000ZZZZ0XXYYYYYb\r\n  *           - YYYYY  : Interrupt source position in the XX register (5bits)\r\n  *           - XX  : Interrupt source register (2bits)\r\n  *                 - 01: CR1 register\r\n  *                 - 10: CR2 register\r\n  *                 - 11: CR3 register\r\n  *           - ZZZZ  : Flag position in the ISR register(4bits)\r\n  * @{   \r\n  */  \r\n#define IRDA_IT_PE                          ((uint16_t)0x0028U)\r\n#define IRDA_IT_TXE                         ((uint16_t)0x0727U)\r\n#define IRDA_IT_TC                          ((uint16_t)0x0626U)\r\n#define IRDA_IT_RXNE                        ((uint16_t)0x0525U)\r\n#define IRDA_IT_IDLE                        ((uint16_t)0x0424U)\r\n\r\n\r\n                                \r\n/**       Elements values convention: 000000000XXYYYYYb\r\n  *           - YYYYY  : Interrupt source position in the XX register (5bits)\r\n  *           - XX  : Interrupt source register (2bits)\r\n  *                 - 01: CR1 register\r\n  *                 - 10: CR2 register\r\n  *                 - 11: CR3 register\r\n  */\r\n#define IRDA_IT_ERR                         ((uint16_t)0x0060U)\r\n\r\n/**       Elements values convention: 0000ZZZZ00000000b\r\n  *           - ZZZZ  : Flag position in the ISR register(4bits)\r\n  */\r\n#define IRDA_IT_ORE                         ((uint16_t)0x0300U)\r\n#define IRDA_IT_NE                          ((uint16_t)0x0200U)\r\n#define IRDA_IT_FE                          ((uint16_t)0x0100U)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup IRDA_IT_CLEAR_Flags IRDA IT CLEAR Flags\r\n  * @{\r\n  */\r\n#define IRDA_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag */          \r\n#define IRDA_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag */         \r\n#define IRDA_CLEAR_NEF                       USART_ICR_NCF             /*!< Noise detected Clear Flag */        \r\n#define IRDA_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag */         \r\n#define IRDA_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n\r\n/** @defgroup IRDA_Request_Parameters IRDA Request Parameters\r\n  * @{\r\n  */\r\n#define IRDA_AUTOBAUD_REQUEST            ((uint16_t)USART_RQR_ABRRQ)        /*!< Auto-Baud Rate Request */     \r\n#define IRDA_RXDATA_FLUSH_REQUEST        ((uint16_t)USART_RQR_RXFRQ)        /*!< Receive Data flush Request */ \r\n#define IRDA_TXDATA_FLUSH_REQUEST        ((uint16_t)USART_RQR_TXFRQ)        /*!< Transmit data flush Request */\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n * @}\r\n */\r\n\r\n  \r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup IRDA_Exported_Macros IRDA Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief Reset IRDA handle state\r\n  * @param  __HANDLE__: specifies the IRDA Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @retval None\r\n  */\r\n#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET)\r\n\r\n/** @brief  Check whether the specified IRDA flag is set or not.\r\n  * @param  __HANDLE__: specifies the IRDA Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  *         UART peripheral\r\n  * @param  __FLAG__: specifies the flag to check.\r\n  *        This parameter can be one of the following values:\r\n  *            @arg IRDA_FLAG_REACK: Receive enable acknowledge flag\r\n  *            @arg IRDA_FLAG_TEACK: Transmit enable acknowledge flag\r\n  *            @arg IRDA_FLAG_BUSY:  Busy flag\r\n  *            @arg IRDA_FLAG_ABRF:  Auto Baud rate detection flag\r\n  *            @arg IRDA_FLAG_ABRE:  Auto Baud rate detection error flag\r\n  *            @arg IRDA_FLAG_TXE:   Transmit data register empty flag\r\n  *            @arg IRDA_FLAG_TC:    Transmission Complete flag\r\n  *            @arg IRDA_FLAG_RXNE:  Receive data register not empty flag\r\n  *            @arg IRDA_FLAG_IDLE:  Idle Line detection flag\r\n  *            @arg IRDA_FLAG_ORE:   OverRun Error flag\r\n  *            @arg IRDA_FLAG_NE:    Noise Error flag\r\n  *            @arg IRDA_FLAG_FE:    Framing Error flag\r\n  *            @arg IRDA_FLAG_PE:    Parity Error flag\r\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))   \r\n\r\n/** @brief  Enable the specified IRDA interrupt.\r\n  * @param  __HANDLE__: specifies the IRDA Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  *         UART peripheral\r\n  * @param  __INTERRUPT__: specifies the IRDA interrupt source to enable.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg IRDA_IT_TXE:  Transmit Data Register empty interrupt\r\n  *            @arg IRDA_IT_TC:   Transmission complete interrupt\r\n  *            @arg IRDA_IT_RXNE: Receive Data register not empty interrupt\r\n  *            @arg IRDA_IT_IDLE: Idle line detection interrupt\r\n  *            @arg IRDA_IT_PE:   Parity Error interrupt\r\n  *            @arg IRDA_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)\r\n  * @retval None\r\n  */\r\n#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 |= (1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \\\r\n                                                          ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 |= (1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \\\r\n                                                          ((__HANDLE__)->Instance->CR3 |= (1 << ((__INTERRUPT__) & IRDA_IT_MASK))))\r\n\r\n/** @brief  Disable the specified IRDA interrupt.\r\n  * @param  __HANDLE__: specifies the IRDA Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @param  __INTERRUPT__: specifies the IRDA interrupt source to disable.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg IRDA_IT_TXE:  Transmit Data Register empty interrupt\r\n  *            @arg IRDA_IT_TC:   Transmission complete interrupt\r\n  *            @arg IRDA_IT_RXNE: Receive Data register not empty interrupt\r\n  *            @arg IRDA_IT_IDLE: Idle line detection interrupt\r\n  *            @arg IRDA_IT_PE:   Parity Error interrupt\r\n  *            @arg IRDA_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)\r\n  * @retval None\r\n  */\r\n#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \\\r\n                                                           ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \\\r\n                                                           ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & IRDA_IT_MASK))))\r\n\r\n/** @brief  Check whether the specified IRDA interrupt has occurred or not.\r\n  * @param  __HANDLE__: specifies the IRDA Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @param  __IT__: specifies the IRDA interrupt source to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg IRDA_IT_TXE: Transmit Data Register empty interrupt\r\n  *            @arg IRDA_IT_TC:  Transmission complete interrupt\r\n  *            @arg IRDA_IT_RXNE: Receive Data register not empty interrupt\r\n  *            @arg IRDA_IT_IDLE: Idle line detection interrupt\r\n  *            @arg IRDA_IT_ORE: OverRun Error interrupt\r\n  *            @arg IRDA_IT_NE: Noise Error interrupt\r\n  *            @arg IRDA_IT_FE: Framing Error interrupt\r\n  *            @arg IRDA_IT_PE: Parity Error interrupt  \r\n  * @retval The new state of __IT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) \r\n\r\n/** @brief  Check whether the specified IRDA interrupt source is enabled.\r\n  * @param  __HANDLE__: specifies the IRDA Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @param  __IT__: specifies the IRDA interrupt source to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg IRDA_IT_TXE: Transmit Data Register empty interrupt\r\n  *            @arg IRDA_IT_TC:  Transmission complete interrupt\r\n  *            @arg IRDA_IT_RXNE: Receive Data register not empty interrupt\r\n  *            @arg IRDA_IT_IDLE: Idle line detection interrupt\r\n  *            @arg IRDA_IT_ORE: OverRun Error interrupt\r\n  *            @arg IRDA_IT_NE: Noise Error interrupt\r\n  *            @arg IRDA_IT_FE: Framing Error interrupt\r\n  *            @arg IRDA_IT_PE: Parity Error interrupt  \r\n  * @retval The new state of __IT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \\\r\n                                                          (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & IRDA_IT_MASK)))\r\n\r\n/** @brief  Clear the specified IRDA ISR flag, in setting the proper ICR register flag.\r\n  * @param  __HANDLE__: specifies the IRDA Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @param  __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set\r\n  *                       to clear the corresponding interrupt\r\n  *          This parameter can be one of the following values:\r\n  *            @arg IRDA_CLEAR_PEF: Parity Error Clear Flag\r\n  *            @arg IRDA_CLEAR_FEF: Framing Error Clear Flag\r\n  *            @arg IRDA_CLEAR_NEF: Noise detected Clear Flag\r\n  *            @arg IRDA_CLEAR_OREF: OverRun Error Clear Flag\r\n  *            @arg IRDA_CLEAR_TCF: Transmission Complete Clear Flag \r\n  * @retval None\r\n  */\r\n#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))\r\n\r\n/** @brief  Set a specific IRDA request flag.\r\n  * @param  __HANDLE__: specifies the IRDA Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @param  __REQ__: specifies the request flag to set\r\n  *          This parameter can be one of the following values:\r\n  *            @arg IRDA_AUTOBAUD_REQUEST: Auto-Baud Rate Request     \r\n  *            @arg IRDA_RXDATA_FLUSH_REQUEST: Receive Data flush Request \r\n  *            @arg IRDA_TXDATA_FLUSH_REQUEST: Transmit data flush Request \r\n  *\r\n  * @retval None\r\n  */\r\n#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) \r\n\r\n/** @brief  Enable UART/USART associated to IRDA Handle\r\n  * @param  __HANDLE__: specifies the IRDA Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @retval None\r\n  */\r\n#define __HAL_IRDA_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)\r\n\r\n/** @brief  Disable UART/USART associated to IRDA Handle\r\n  * @param  __HANDLE__: specifies the IRDA Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @retval None\r\n  */\r\n#define __HAL_IRDA_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Include IRDA HAL Extension module */\r\n#include \"stm32f7xx_hal_irda_ex.h\"  \r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup IRDA_Exported_Functions IrDA Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions\r\n  * @{\r\n  */\r\n\r\n/* Initialization and de-initialization functions  ****************************/\r\nHAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);\r\nHAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);\r\nvoid HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);\r\nvoid HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions\r\n  * @{\r\n  */\r\n\r\n/* IO operation functions *****************************************************/\r\nHAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);\r\nHAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);\r\nHAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);\r\nvoid HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);\r\nvoid HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);\r\nvoid HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);\r\nvoid HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);\r\nvoid HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);\r\nvoid HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);\r\n/**\r\n * @}\r\n */\r\n\r\n/** @addtogroup IRDA_Exported_Functions_Group3 Peripheral Control functions\r\n * @{\r\n */\r\n/* Peripheral State methods  **************************************************/\r\nHAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);\r\nuint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup IRDA_Private_Constants IRDA Private Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup IRDA_Interruption_Mask IRDA Interruption Mask\r\n  * @{\r\n  */ \r\n#define IRDA_IT_MASK  ((uint16_t)0x001FU)\r\n/**\r\n  * @}\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros --------------------------------------------------------*/\r\n/** @defgroup IRDA_Private_Macros   IRDA Private Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief  Ensure that IRDA Baud rate is less or equal to maximum value\r\n  * @param  __BAUDRATE__: specifies the IRDA Baudrate set by the user.\r\n  * @retval True or False\r\n  */   \r\n#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201)\r\n\r\n/** @brief  Ensure that IRDA prescaler value is strictly larger than 0\r\n  * @param  __PRESCALER__: specifies the IRDA prescaler value set by the user.\r\n  * @retval True or False\r\n  */  \r\n#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0)\r\n\r\n#define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \\\r\n                                    ((__PARITY__) == IRDA_PARITY_EVEN) || \\\r\n                                    ((__PARITY__) == IRDA_PARITY_ODD))\r\n\t\t\t\t\t\t\t\t\r\n#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00U))\r\n\r\n#define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \\\r\n                                     ((__MODE__) == IRDA_POWERMODE_NORMAL))\r\n\t\t\t\t\t\t\t\t\t \r\n#define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \\\r\n                                  ((__STATE__) == IRDA_STATE_ENABLE))\r\n\t\t\t\t\t\t\t\t  \r\n#define IS_IRDA_MODE(__STATE__)  (((__STATE__) == IRDA_MODE_DISABLE) || \\\r\n                                  ((__STATE__) == IRDA_MODE_ENABLE))\r\n\t\t\t\t\t\t\t\t  \r\n#define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__)     (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \\\r\n                                               ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))\r\n\r\n#define IS_IRDA_DMA_TX(__DMATX__)     (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \\\r\n                                       ((__DMATX__) == IRDA_DMA_TX_ENABLE))\t\t\r\n\r\n#define IS_IRDA_DMA_RX(__DMARX__)     (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \\\r\n                                       ((__DMARX__) == IRDA_DMA_RX_ENABLE))\r\n\r\n#define IS_IRDA_REQUEST_PARAMETER(PARAM) (((PARAM) == IRDA_AUTOBAUD_REQUEST) || \\\r\n                                          ((PARAM) == IRDA_SENDBREAK_REQUEST) || \\\r\n                                          ((PARAM) == IRDA_MUTE_MODE_REQUEST) || \\\r\n                                          ((PARAM) == IRDA_RXDATA_FLUSH_REQUEST) || \\\r\n                                          ((PARAM) == IRDA_TXDATA_FLUSH_REQUEST))\t\t\t\t\t\t\t\t\t   \r\n/**\r\n * @}\r\n */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup IRDA_Private_Functions IRDA Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_IRDA_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_irda_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_irda_ex.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of IRDA HAL Extension module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *                               \r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************  \r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_IRDA_EX_H\r\n#define __STM32F7xx_HAL_IRDA_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup IRDAEx\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup IRDAEx_Extended_Exported_Constants IRDAEx Extended Exported Constants\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup IRDAEx_Word_Length IRDAEx Word Length\r\n  * @{\r\n  */\r\n#define IRDA_WORDLENGTH_7B                  ((uint32_t)USART_CR1_M_1)\r\n#define IRDA_WORDLENGTH_8B                  ((uint32_t)0x00000000U)\r\n#define IRDA_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M_0)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n  \r\n/**\r\n  * @}\r\n  */  \r\n  \r\n/* Exported macro ------------------------------------------------------------*/\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n\r\n/** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros\r\n  * @{\r\n  */\r\n/** @brief  Reports the IRDA clock source.\r\n  * @param  __HANDLE__: specifies the IRDA Handle\r\n  * @param  __CLOCKSOURCE__ : output variable\r\n  * @retval IRDA clocking source, written in __CLOCKSOURCE__.\r\n  */\r\n#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \\\r\n  do {                                                        \\\r\n    if((__HANDLE__)->Instance == USART1)                      \\\r\n    {                                                         \\\r\n       switch(__HAL_RCC_GET_USART1_SOURCE())                  \\\r\n       {                                                      \\\r\n        case RCC_USART1CLKSOURCE_PCLK2:                       \\\r\n          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2;         \\\r\n          break;                                              \\\r\n        case RCC_USART1CLKSOURCE_HSI:                         \\\r\n          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \\\r\n          break;                                              \\\r\n        case RCC_USART1CLKSOURCE_SYSCLK:                      \\\r\n          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                              \\\r\n        case RCC_USART1CLKSOURCE_LSE:                         \\\r\n          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \\\r\n          break;                                              \\\r\n        default:                                              \\\r\n          break;                                              \\\r\n       }                                                      \\\r\n    }                                                         \\\r\n    else if((__HANDLE__)->Instance == USART2)                 \\\r\n    {                                                         \\\r\n       switch(__HAL_RCC_GET_USART2_SOURCE())                  \\\r\n       {                                                      \\\r\n        case RCC_USART2CLKSOURCE_PCLK1:                       \\\r\n          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \\\r\n          break;                                              \\\r\n        case RCC_USART2CLKSOURCE_HSI:                         \\\r\n          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \\\r\n          break;                                              \\\r\n        case RCC_USART2CLKSOURCE_SYSCLK:                      \\\r\n          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                              \\\r\n        case RCC_USART2CLKSOURCE_LSE:                         \\\r\n          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \\\r\n          break;                                              \\\r\n        default:                                              \\\r\n          break;                                              \\\r\n       }                                                      \\\r\n    }                                                         \\\r\n    else if((__HANDLE__)->Instance == USART3)                 \\\r\n    {                                                         \\\r\n       switch(__HAL_RCC_GET_USART3_SOURCE())                  \\\r\n       {                                                      \\\r\n        case RCC_USART3CLKSOURCE_PCLK1:                       \\\r\n          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;         \\\r\n          break;                                              \\\r\n        case RCC_USART3CLKSOURCE_HSI:                         \\\r\n          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \\\r\n          break;                                              \\\r\n        case RCC_USART3CLKSOURCE_SYSCLK:                      \\\r\n          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                              \\\r\n        case RCC_USART3CLKSOURCE_LSE:                         \\\r\n          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \\\r\n          break;                                              \\\r\n        default:                                              \\\r\n          break;                                              \\\r\n       }                                                      \\\r\n    }                                                         \\\r\n    else if((__HANDLE__)->Instance == USART6)                 \\\r\n    {                                                         \\\r\n       switch(__HAL_RCC_GET_USART6_SOURCE())                  \\\r\n       {                                                      \\\r\n        case RCC_USART6CLKSOURCE_PCLK2:                       \\\r\n          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2;         \\\r\n          break;                                              \\\r\n        case RCC_USART6CLKSOURCE_HSI:                         \\\r\n          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \\\r\n          break;                                              \\\r\n        case RCC_USART6CLKSOURCE_SYSCLK:                      \\\r\n          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                              \\\r\n        case RCC_USART6CLKSOURCE_LSE:                         \\\r\n          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \\\r\n          break;                                              \\\r\n        default:                                              \\\r\n          break;                                              \\\r\n       }                                                      \\\r\n    }                                                         \\\r\n\t} while(0)\r\n\r\n/** @brief  Reports the mask to apply to retrieve the received data\r\n  *         according to the word length and to the parity bits activation.\r\n  * @param  __HANDLE__: specifies the IRDA Handle\r\n  * @retval mask to apply to USART RDR register value.\r\n  */    \r\n#define IRDA_MASK_COMPUTATION(__HANDLE__)                       \\\r\n  do {                                                                \\\r\n  if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B)            \\\r\n  {                                                                   \\\r\n     if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x01FF ;                                 \\\r\n     }                                                                \\\r\n     else                                                             \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x00FF ;                                 \\\r\n     }                                                                \\\r\n  }                                                                   \\\r\n  else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B)       \\\r\n  {                                                                   \\\r\n     if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x00FF ;                                 \\\r\n     }                                                                \\\r\n     else                                                             \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x007F ;                                 \\\r\n     }                                                                \\\r\n  }                                                                   \\\r\n  else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B)       \\\r\n  {                                                                   \\\r\n     if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x007F ;                                 \\\r\n     }                                                                \\\r\n     else                                                             \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x003F ;                                 \\\r\n     }                                                                \\\r\n  }                                                                   \\\r\n} while(0)\r\n\r\n#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_7B) || \\\r\n                                     ((LENGTH) == IRDA_WORDLENGTH_8B) || \\\r\n                                     ((LENGTH) == IRDA_WORDLENGTH_9B))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_IRDA_EX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_iwdg.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_iwdg.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of IWDG HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_IWDG_H\r\n#define __STM32F7xx_HAL_IWDG_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup IWDG IWDG\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup IWDG_Exported_Types IWDG Exported Types\r\n  * @{\r\n  */\r\n\r\n/** \r\n  * @brief  IWDG Init structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t Prescaler;  /*!< Select the prescaler of the IWDG.\r\n                            This parameter can be a value of @ref IWDG_Prescaler */\r\n\r\n  uint32_t Reload;     /*!< Specifies the IWDG down-counter reload value.\r\n                            This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */\r\n\r\n  uint32_t Window;     /*!< Specifies the window value to be compared to the down-counter.\r\n                            This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */\r\n\r\n} IWDG_InitTypeDef;\r\n\r\n/** \r\n  * @brief  IWDG Handle Structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  IWDG_TypeDef                 *Instance;  /*!< Register base address    */\r\n\r\n  IWDG_InitTypeDef             Init;       /*!< IWDG required parameters */\r\n\r\n}IWDG_HandleTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup IWDG_Exported_Constants IWDG Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup IWDG_Prescaler IWDG Prescaler\r\n  * @{\r\n  */\r\n#define IWDG_PRESCALER_4                0x00000000u                   /*!< IWDG prescaler set to 4   */\r\n#define IWDG_PRESCALER_8                IWDG_PR_PR_0                  /*!< IWDG prescaler set to 8   */\r\n#define IWDG_PRESCALER_16               IWDG_PR_PR_1                  /*!< IWDG prescaler set to 16  */\r\n#define IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32  */\r\n#define IWDG_PRESCALER_64               IWDG_PR_PR_2                  /*!< IWDG prescaler set to 64  */\r\n#define IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */\r\n#define IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup IWDG_Window_option IWDG Window option\r\n  * @{\r\n  */\r\n#define IWDG_WINDOW_DISABLE             IWDG_WINR_WIN\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macros -----------------------------------------------------------*/\r\n/** @defgroup IWDG_Exported_Macros IWDG Exported Macros\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Enable the IWDG peripheral.\r\n  * @param  __HANDLE__: IWDG handle\r\n  * @retval None\r\n  */\r\n#define __HAL_IWDG_START(__HANDLE__)                WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)\r\n\r\n/**\r\n  * @brief  Reload IWDG counter with value defined in the reload register\r\n  *         (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled).\r\n  * @param  __HANDLE__:  IWDG handle\r\n  * @retval None\r\n  */\r\n#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__)       WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup IWDG_Exported_Functions  IWDG Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions\r\n  * @{\r\n  */\r\n/* Initialization/Start functions  ********************************************/\r\nHAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions\r\n  * @{\r\n  */\r\n/* I/O operation functions ****************************************************/\r\nHAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup IWDG_Private_Constants IWDG Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  IWDG Key Register BitMask\r\n  */\r\n#define IWDG_KEY_RELOAD                 0x0000AAAAu  /*!< IWDG Reload Counter Enable   */\r\n#define IWDG_KEY_ENABLE                 0x0000CCCCu  /*!< IWDG Peripheral Enable       */\r\n#define IWDG_KEY_WRITE_ACCESS_ENABLE    0x00005555u  /*!< IWDG KR Write Access Enable  */\r\n#define IWDG_KEY_WRITE_ACCESS_DISABLE   0x00000000u  /*!< IWDG KR Write Access Disable */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup IWDG_Private_Macros IWDG Private Macros\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.\r\n  * @param  __HANDLE__: IWDG handle\r\n  * @retval None\r\n  */\r\n#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__)  WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)\r\n\r\n/**\r\n  * @brief  Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.\r\n  * @param  __HANDLE__: IWDG handle\r\n  * @retval None\r\n  */\r\n#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)\r\n\r\n/**\r\n  * @brief  Check IWDG prescaler value.\r\n  * @param  __PRESCALER__: IWDG prescaler value\r\n  * @retval None\r\n  */\r\n#define IS_IWDG_PRESCALER(__PRESCALER__)      (((__PRESCALER__) == IWDG_PRESCALER_4)  || \\\r\n                                               ((__PRESCALER__) == IWDG_PRESCALER_8)  || \\\r\n                                               ((__PRESCALER__) == IWDG_PRESCALER_16) || \\\r\n                                               ((__PRESCALER__) == IWDG_PRESCALER_32) || \\\r\n                                               ((__PRESCALER__) == IWDG_PRESCALER_64) || \\\r\n                                               ((__PRESCALER__) == IWDG_PRESCALER_128)|| \\\r\n                                               ((__PRESCALER__) == IWDG_PRESCALER_256))\r\n\r\n/**\r\n  * @brief  Check IWDG reload value.\r\n  * @param  __RELOAD__: IWDG reload value\r\n  * @retval None\r\n  */\r\n#define IS_IWDG_RELOAD(__RELOAD__)            ((__RELOAD__) <= IWDG_RLR_RL)\r\n\r\n/**\r\n  * @brief  Check IWDG window value.\r\n  * @param  __WINDOW__: IWDG window value\r\n  * @retval None\r\n  */\r\n#define IS_IWDG_WINDOW(__WINDOW__)            ((__WINDOW__) <= IWDG_WINR_WIN)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_IWDG_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_jpeg.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_jpeg.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of JPEG HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_JPEG_H\r\n#define __STM32F7xx_HAL_JPEG_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup JPEG\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup JPEG_Exported_Types JPEG Exported Types\r\n  * @{\r\n  */\r\n\r\n/** @defgroup JPEG_Configuration_Structure_definition JPEG Configuration for encoding Structure definition\r\n  * @brief  JPEG encoding configuration Structure definition \r\n  * @{\r\n  */\r\ntypedef struct\r\n{\r\n  uint8_t  ColorSpace;                /*!< Image Color space : gray-scale, YCBCR, RGB or CMYK\r\n                                           This parameter can be a value of @ref JPEG_ColorSpace_Type */\r\n  \r\n  uint8_t  ChromaSubsampling;         /*!< Chroma Subsampling in case of YCBCR or CMYK color space, 0-> 4:4:4 , 1-> 4:2:2, 2 -> 4:1:1, 3 -> 4:2:0\r\n                                           This parameter can be a value of @ref JPEG_ChromaSubsampling_Type */\r\n  \r\n  uint32_t ImageHeight;               /*!< Image height : number of lines */\r\n  \r\n  uint32_t ImageWidth;                /*!< Image width : number of pixels per line */\r\n  \r\n  uint8_t  ImageQuality;               /*!< Quality of the JPEG encoding : from 1 to 100 */\r\n\r\n}JPEG_ConfTypeDef;\r\n/** \r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_JPEG_state_structure_definition HAL JPEG state structure definition\r\n  * @brief  HAL JPEG State structure definition  \r\n  * @{\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_JPEG_STATE_RESET              = 0x00U,  /*!< JPEG not yet initialized or disabled  */\r\n  HAL_JPEG_STATE_READY              = 0x01U,  /*!< JPEG initialized and ready for use    */\r\n  HAL_JPEG_STATE_BUSY               = 0x02U,  /*!< JPEG internal processing is ongoing   */\r\n  HAL_JPEG_STATE_BUSY_ENCODING      = 0x03U,  /*!< JPEG encoding processing is ongoing   */\r\n  HAL_JPEG_STATE_BUSY_DECODING      = 0x04U,  /*!< JPEG decoding processing is ongoing   */  \r\n  HAL_JPEG_STATE_TIMEOUT            = 0x05U,  /*!< JPEG timeout state                    */\r\n  HAL_JPEG_STATE_ERROR              = 0x06U   /*!< JPEG error state                      */\r\n}HAL_JPEG_STATETypeDef;\r\n\r\n/** \r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup JPEG_handle_Structure_definition JPEG handle Structure definition \r\n  * @brief  JPEG handle Structure definition  \r\n  * @{\r\n  */\r\ntypedef struct\r\n{\r\n  JPEG_TypeDef             *Instance;        /*!< JPEG peripheral register base address */\r\n            \r\n  JPEG_ConfTypeDef         Conf;             /*!< Current JPEG encoding/decoding parameters */\r\n\r\n  uint8_t                  *pJpegInBuffPtr;  /*!< Pointer to JPEG processing (encoding, decoding,...) input buffer */\r\n\r\n  uint8_t                  *pJpegOutBuffPtr; /*!< Pointer to JPEG processing (encoding, decoding,...) output buffer */\r\n\r\n  __IO uint32_t            JpegInCount;      /*!< Internal Counter of input data */\r\n\r\n  __IO uint32_t            JpegOutCount;     /*!< Internal Counter of output data */\r\n    \r\n  uint32_t                 InDataLength;     /*!< Input Buffer Length in Bytes */\r\n\r\n  uint32_t                 OutDataLength;    /*!< Output Buffer Length in Bytes */  \r\n\r\n  DMA_HandleTypeDef        *hdmain;          /*!< JPEG In DMA handle parameters */\r\n\r\n  DMA_HandleTypeDef        *hdmaout;         /*!< JPEG Out DMA handle parameters */\r\n\r\n  uint8_t                  CustomQuanTable;  /*!< If set to 1 specify that user customized quantization tables are used */\r\n      \r\n  uint8_t                  *QuantTable0;     /*!< Basic Quantization Table for component 0 */\r\n\r\n  uint8_t                  *QuantTable1;     /*!< Basic Quantization Table for component 1 */\r\n      \r\n  uint8_t                  *QuantTable2;     /*!< Basic Quantization Table for component 2 */\r\n      \r\n  uint8_t                  *QuantTable3;     /*!< Basic Quantization Table for component 3 */      \r\n      \r\n  HAL_LockTypeDef          Lock;             /*!< JPEG locking object */\r\n      \r\n  __IO  HAL_JPEG_STATETypeDef State;         /*!< JPEG peripheral state */\r\n      \r\n  __IO  uint32_t           ErrorCode;        /*!< JPEG Error code */\r\n  \r\n  __IO uint32_t Context;                     /*!< JPEG Internal context */\r\n\r\n}JPEG_HandleTypeDef;\r\n\r\n/** \r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup JPEG_Exported_Constants JPEG Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup JPEG_Error_Code_definition JPEG Error Code definition\r\n  * @brief  JPEG Error Code definition  \r\n  * @{\r\n  */ \r\n\r\n#define  HAL_JPEG_ERROR_NONE        ((uint32_t)0x00000000U)    /*!< No error             */\r\n#define  HAL_JPEG_ERROR_HUFF_TABLE  ((uint32_t)0x00000001U)    /*!< HUffman Table programming error */\r\n#define  HAL_JPEG_ERROR_QUANT_TABLE ((uint32_t)0x00000002U)    /*!< Quantization Table programming error */\r\n#define  HAL_JPEG_ERROR_DMA         ((uint32_t)0x00000004U)    /*!< DMA transfer error   */\r\n#define  HAL_JPEG_ERROR_TIMEOUT     ((uint32_t)0x00000008U)    /*!< Timeout error        */\r\n\r\n/** \r\n  * @}\r\n  */\r\n\r\n/** @defgroup JPEG_Quantization_Table_Size JPEG Quantization Table Size\r\n  * @brief  JPEG Quantization Table Size  \r\n  * @{\r\n  */\r\n#define JPEG_QUANT_TABLE_SIZE  ((uint32_t)64U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n  \r\n/** @defgroup JPEG_ColorSpace_Type JPEG ColorSpace\r\n  * @brief  JPEG Color Space  \r\n  * @{\r\n  */\r\n#define JPEG_GRAYSCALE_COLORSPACE     ((uint32_t)0x00000000U)\r\n#define JPEG_YCBCR_COLORSPACE         JPEG_CONFR1_COLORSPACE_0\r\n#define JPEG_CMYK_COLORSPACE          JPEG_CONFR1_COLORSPACE\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup JPEG_ChromaSubsampling_Type JPEG Chrominance Sampling\r\n  * @brief  JPEG Chrominance Sampling  \r\n  * @{\r\n  */\r\n#define JPEG_444_SUBSAMPLING     ((uint32_t)0x00000000U)   /*!< Chroma Subsampling 4:4:4 */\r\n#define JPEG_420_SUBSAMPLING     ((uint32_t)0x00000001U)   /*!< Chroma Subsampling 4:2:0 */\r\n#define JPEG_422_SUBSAMPLING     ((uint32_t)0x00000002U)   /*!< Chroma Subsampling 4:2:2 */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup JPEG_ImageQuality JPEG Image Quality\r\n  * @brief  JPEG Min and Max Image Quality  \r\n  * @{\r\n  */\r\n#define JPEG_IMAGE_QUALITY_MIN     ((uint32_t)1U)     /*!< Minimum JPEG quality */\r\n#define JPEG_IMAGE_QUALITY_MAX     ((uint32_t)100U)   /*!< Maximum JPEG quality */\r\n\r\n/**\r\n  * @}\r\n  */     \r\n  \r\n/** @defgroup JPEG_Interrupt_configuration_definition JPEG Interrupt configuration definition\r\n  * @brief JPEG Interrupt definition\r\n  * @{\r\n  */\r\n#define JPEG_IT_IFT     ((uint32_t)JPEG_CR_IFTIE)   /*!< Input FIFO Threshold Interrupt */\r\n#define JPEG_IT_IFNF    ((uint32_t)JPEG_CR_IFNFIE)  /*!< Input FIFO Not Full Interrupt */\r\n#define JPEG_IT_OFT     ((uint32_t)JPEG_CR_OFTIE)   /*!< Output FIFO Threshold Interrupt */\r\n#define JPEG_IT_OFNE    ((uint32_t)JPEG_CR_OFTIE)   /*!< Output FIFO Not Empty Interrupt */\r\n#define JPEG_IT_EOC     ((uint32_t)JPEG_CR_EOCIE)   /*!< End of Conversion Interrupt */\r\n#define JPEG_IT_HPD     ((uint32_t)JPEG_CR_HPDIE)   /*!< Header Parsing Done Interrupt */ \r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup JPEG_Flag_definition JPEG Flag definition\r\n  * @brief JPEG Flags definition\r\n  * @{\r\n  */ \r\n#define JPEG_FLAG_IFTF     ((uint32_t)JPEG_SR_IFTF)   /*!< Input FIFO is not full and is bellow its threshold flag */\r\n#define JPEG_FLAG_IFNFF    ((uint32_t)JPEG_SR_IFNFF)  /*!< Input FIFO Not Full Flag, a data can be written */\r\n#define JPEG_FLAG_OFTF     ((uint32_t)JPEG_SR_OFTF)   /*!< Output FIFO is not empty and has reach its threshold */\r\n#define JPEG_FLAG_OFNEF    ((uint32_t)JPEG_SR_OFNEF)  /*!< Output FIFO is not empty, a data is available  */\r\n#define JPEG_FLAG_EOCF     ((uint32_t)JPEG_SR_EOCF)   /*!< JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO  */\r\n#define JPEG_FLAG_HPDF     ((uint32_t)JPEG_SR_HPDF)   /*!< JPEG Codec has finished the parsing of the headers and the internal registers have been updated  */\r\n#define JPEG_FLAG_COF      ((uint32_t)JPEG_SR_COF)    /*!< JPEG Codec operation on going  flag*/\r\n\r\n#define JPEG_FLAG_ALL      ((uint32_t)0x000000FEU)     /*!< JPEG Codec All previous flag*/\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup JPEG_PROCESS_PAUSE_RESUME_definition JPEG Process Pause Resume definition\r\n  * @brief JPEG process pause, resume definition\r\n  * @{\r\n  */  \r\n#define JPEG_PAUSE_RESUME_INPUT          ((uint32_t)0x00000001U)     /*!< Pause/Resume Input FIFO Xfer*/\r\n#define JPEG_PAUSE_RESUME_OUTPUT         ((uint32_t)0x00000002U)     /*!< Pause/Resume Output FIFO Xfer*/\r\n#define JPEG_PAUSE_RESUME_INPUT_OUTPUT   ((uint32_t)0x00000003U)     /*!< Pause/Resume Input and Output FIFO Xfer*/\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Exported macro ------------------------------------------------------------*/\r\n\r\n/** @defgroup JPEG_Exported_Macros JPEG Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief Reset JPEG handle state\r\n  * @param  __HANDLE__: specifies the JPEG handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_JPEG_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_JPEG_STATE_RESET)\r\n\r\n\r\n/**\r\n  * @brief  Enable the JPEG peripheral.\r\n  * @param  __HANDLE__: specifies the JPEG handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_JPEG_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  JPEG_CR_JCEN)\r\n\r\n/**\r\n  * @brief Disable the JPEG peripheral.\r\n  * @param  __HANDLE__: specifies the JPEG handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_JPEG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &=  ~JPEG_CR_JCEN)\r\n\r\n\r\n/**\r\n  * @brief  Check the specified JPEG status flag.\r\n  * @param  __HANDLE__: specifies the JPEG handle. \r\n  * @param  __FLAG__ : specifies the flag to check\r\n  *         This parameter can be one of the following values:\r\n  *         @arg JPEG_FLAG_IFTF  : The input FIFO is not full and is bellow its threshold flag\r\n  *         @arg JPEG_FLAG_IFNFF : The input FIFO Not Full Flag, a data can be written\r\n  *         @arg JPEG_FLAG_OFTF  : The output FIFO is not empty and has reach its threshold\r\n  *         @arg JPEG_FLAG_OFNEF : The output FIFO is not empty, a data is available\r\n  *         @arg JPEG_FLAG_EOCF  : JPEG Codec core has finished the encoding or the decoding process \r\n  *                                and than last data has been sent to the output FIFO\r\n  *         @arg JPEG_FLAG_HPDF  : JPEG Codec has finished the parsing of the headers \r\n  *                                and the internal registers have been updated\r\n  *         @arg JPEG_FLAG_COF   : JPEG Codec operation on going  flag\r\n  *                        \r\n  * @retval : __HAL_JPEG_GET_FLAG : returns The new state of __FLAG__ (TRUE or FALSE)  \r\n  */\r\n\r\n#define __HAL_JPEG_GET_FLAG(__HANDLE__,__FLAG__)  (((__HANDLE__)->Instance->SR & (__FLAG__)))\r\n\r\n/**\r\n  * @brief  Clear the specified JPEG status flag.\r\n  * @param  __HANDLE__: specifies the JPEG handle. \r\n  * @param  __FLAG__ : specifies the flag to clear\r\n  *         This parameter can be one of the following values:\r\n  *         @arg JPEG_FLAG_EOCF  : JPEG Codec core has finished the encoding or the decoding process \r\n  *                                and than last data has been sent to the output FIFO\r\n  *         @arg JPEG_FLAG_HPDF  : JPEG Codec has finished the parsing of the headers \r\n  * @retval : None    \r\n  */\r\n\r\n#define __HAL_JPEG_CLEAR_FLAG(__HANDLE__,__FLAG__)  (((__HANDLE__)->Instance->CFR |= ((__FLAG__) & (JPEG_FLAG_EOCF | JPEG_FLAG_HPDF))))\r\n\r\n\r\n/**\r\n  * @brief  Enable Interrupt.\r\n  * @param   __HANDLE__: specifies the JPEG handle.\r\n  * @param  __INTERRUPT__ : specifies the interrupt to enable\r\n  *         This parameter can be one of the following values:\r\n  *         @arg JPEG_IT_IFT   : Input FIFO Threshold Interrupt\r\n  *         @arg JPEG_IT_IFNF  : Input FIFO Not Full Interrupt\r\n  *         @arg JPEG_IT_OFT   : Output FIFO Threshold Interrupt\r\n  *         @arg JPEG_IT_OFNE  : Output FIFO Not empty Interrupt\r\n  *         @arg JPEG_IT_EOC   : End of Conversion Interrupt\r\n  *         @arg JPEG_IT_HPD   : Header Parsing Done Interrupt       \r\n  *           \r\n  * @retval : No retrun \r\n  */\r\n#define __HAL_JPEG_ENABLE_IT(__HANDLE__,__INTERRUPT__)  ((__HANDLE__)->Instance->CR |= (__INTERRUPT__) )\r\n\r\n/**\r\n  * @brief  Disable Interrupt.\r\n  * @param   __HANDLE__: specifies the JPEG handle.\r\n  * @param  __INTERRUPT__ : specifies the interrupt to disable\r\n  *         This parameter can be one of the following values:\r\n  *         @arg JPEG_IT_IFT   : Input FIFO Threshold Interrupt\r\n  *         @arg JPEG_IT_IFNF  : Input FIFO Not Full Interrupt\r\n  *         @arg JPEG_IT_OFT   : Output FIFO Threshold Interrupt\r\n  *         @arg JPEG_IT_OFNE  : Output FIFO Not empty Interrupt\r\n  *         @arg JPEG_IT_EOC   : End of Conversion Interrupt\r\n  *         @arg JPEG_IT_HPD   : Header Parsing Done Interrupt       \r\n  *           \r\n  * @note  : To disable an IT we must use MODIFY_REG macro to avoid writing \"1\" to the FIFO flush bits \r\n  *          located in the same IT enable register (CR register).  \r\n  * @retval : No retrun \r\n  */\r\n#define __HAL_JPEG_DISABLE_IT(__HANDLE__,__INTERRUPT__) MODIFY_REG((__HANDLE__)->Instance->CR, (__INTERRUPT__), 0)\r\n\r\n\r\n/**\r\n  * @brief  Get Interrupt state.\r\n  * @param   __HANDLE__: specifies the JPEG handle.\r\n  * @param  __INTERRUPT__ : specifies the interrupt to check\r\n  *         This parameter can be one of the following values:\r\n  *         @arg JPEG_IT_IFT   : Input FIFO Threshold Interrupt\r\n  *         @arg JPEG_IT_IFNF  : Input FIFO Not Full Interrupt\r\n  *         @arg JPEG_IT_OFT   : Output FIFO Threshold Interrupt\r\n  *         @arg JPEG_IT_OFNE  : Output FIFO Not empty Interrupt\r\n  *         @arg JPEG_IT_EOC   : End of Conversion Interrupt\r\n  *         @arg JPEG_IT_HPD   : Header Parsing Done Interrupt       \r\n  *           \r\n  * @retval : returns The new state of __INTERRUPT__ (Enabled or disabled)\r\n  */\r\n#define __HAL_JPEG_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__)     ((__HANDLE__)->Instance->CR & (__INTERRUPT__))\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup JPEG_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup JPEG_Exported_Functions_Group1\r\n  * @{\r\n  */    \r\n/* Initialization/de-initialization functions  ********************************/\r\nHAL_StatusTypeDef HAL_JPEG_Init(JPEG_HandleTypeDef *hjpeg);\r\nHAL_StatusTypeDef HAL_JPEG_DeInit(JPEG_HandleTypeDef *hjpeg);\r\nvoid HAL_JPEG_MspInit(JPEG_HandleTypeDef *hjpeg);\r\nvoid HAL_JPEG_MspDeInit(JPEG_HandleTypeDef *hjpeg);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup JPEG_Exported_Functions_Group2\r\n  * @{\r\n  */ \r\n/* Encoding/Decoding Configuration functions  ********************************/\r\nHAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pConf);\r\nHAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo);\r\nHAL_StatusTypeDef HAL_JPEG_EnableHeaderParsing(JPEG_HandleTypeDef *hjpeg);\r\nHAL_StatusTypeDef HAL_JPEG_DisableHeaderParsing(JPEG_HandleTypeDef *hjpeg);\r\nHAL_StatusTypeDef HAL_JPEG_SetUserQuantTables(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable0, uint8_t *QTable1, uint8_t *QTable2, uint8_t *QTable3);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup JPEG_Exported_Functions_Group3\r\n  * @{\r\n  */ \r\n/* JPEG processing functions  **************************************/\r\nHAL_StatusTypeDef  HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout);\r\nHAL_StatusTypeDef  HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength, uint32_t Timeout);\r\nHAL_StatusTypeDef  HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength);\r\nHAL_StatusTypeDef  HAL_JPEG_Decode_IT(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength);\r\nHAL_StatusTypeDef  HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength);\r\nHAL_StatusTypeDef  HAL_JPEG_Decode_DMA(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength);\r\nHAL_StatusTypeDef  HAL_JPEG_Pause(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection);\r\nHAL_StatusTypeDef  HAL_JPEG_Resume(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection);\r\nvoid HAL_JPEG_ConfigInputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewInputBuffer, uint32_t InDataLength);\r\nvoid HAL_JPEG_ConfigOutputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputBuffer, uint32_t OutDataLength);\r\nHAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup JPEG_Exported_Functions_Group4\r\n  * @{\r\n  */ \r\n/* JPEG Decode/Encode callback functions  ********************************************************/\r\nvoid HAL_JPEG_InfoReadyCallback(JPEG_HandleTypeDef *hjpeg,JPEG_ConfTypeDef *pInfo);\r\nvoid HAL_JPEG_EncodeCpltCallback(JPEG_HandleTypeDef *hjpeg);\r\nvoid HAL_JPEG_DecodeCpltCallback(JPEG_HandleTypeDef *hjpeg);\r\nvoid HAL_JPEG_ErrorCallback(JPEG_HandleTypeDef *hjpeg);\r\nvoid HAL_JPEG_GetDataCallback(JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData);\r\nvoid HAL_JPEG_DataReadyCallback (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup JPEG_Exported_Functions_Group5\r\n  * @{\r\n  */ \r\n/* JPEG IRQ handler management  ******************************************************/\r\nvoid HAL_JPEG_IRQHandler(JPEG_HandleTypeDef *hjpeg);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup JPEG_Exported_Functions_Group6\r\n  * @{\r\n  */ \r\n/* Peripheral State and Error functions  ************************************************/\r\nHAL_JPEG_STATETypeDef  HAL_JPEG_GetState(JPEG_HandleTypeDef *hjpeg);\r\nuint32_t               HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/** @defgroup JPEG_Private_Types JPEG Private Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private defines -----------------------------------------------------------*/\r\n/** @defgroup JPEG_Private_Defines JPEG Private Defines\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n          \r\n/* Private variables ---------------------------------------------------------*/\r\n/** @defgroup JPEG_Private_Variables JPEG Private Variables\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup JPEG_Private_Constants JPEG Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup JPEG_Private_Macros JPEG Private Macros\r\n  * @{\r\n  */\r\n\r\n/** @defgroup JPEG_IS_Definitions JPEG Private macros to check input parameters\r\n  * @{\r\n  */\r\n\r\n#define IS_JPEG_CHROMASUBSAMPLING(SUBSAMPLING) (((SUBSAMPLING) == JPEG_444_SUBSAMPLING) || \\\r\n                                                ((SUBSAMPLING) == JPEG_420_SUBSAMPLING) || \\\r\n                                                ((SUBSAMPLING) == JPEG_422_SUBSAMPLING))\r\n\r\n#define IS_JPEG_IMAGE_QUALITY(NUMBER) (((NUMBER) >= JPEG_IMAGE_QUALITY_MIN) && ((NUMBER) <= JPEG_IMAGE_QUALITY_MAX))\r\n\r\n#define IS_JPEG_COLORSPACE(COLORSPACE) (((COLORSPACE) == JPEG_GRAYSCALE_COLORSPACE) || \\\r\n                                        ((COLORSPACE) == JPEG_YCBCR_COLORSPACE)     || \\\r\n                                        ((COLORSPACE) == JPEG_CMYK_COLORSPACE))\r\n\r\n#define IS_JPEG_PAUSE_RESUME_STATE(VALUE) (((VALUE) == JPEG_PAUSE_RESUME_INPUT) || \\\r\n                                           ((VALUE) == JPEG_PAUSE_RESUME_OUTPUT)|| \\\r\n                                           ((VALUE) == JPEG_PAUSE_RESUME_INPUT_OUTPUT))\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private functions prototypes ----------------------------------------------*/\r\n/** @defgroup JPEG_Private_Functions_Prototypes JPEG Private Functions Prototypes\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup JPEG_Private_Functions JPEG Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* STM32F767xx ||  STM32F769xx ||  STM32F777xx ||  STM32F779xx */ \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_JPEG_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_lptim.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_lptim.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of LPTIM HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_LPTIM_H\r\n#define __STM32F7xx_HAL_LPTIM_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup LPTIM LPTIM\r\n  * @brief LPTIM HAL module driver\r\n  * @{\r\n  */\r\n  \r\n/* Exported types ------------------------------------------------------------*/ \r\n/** @defgroup LPTIM_Exported_Types LPTIM Exported Types\r\n  * @{\r\n  */\r\n\r\n/** @defgroup LPTIM_WAKEUPTIMER_EXTILINE LPTIM WAKEUP Timer EXTI Line\r\n  * @{\r\n  */\r\n#define LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT  ((uint32_t)EXTI_IMR_MR23)  /*!< External interrupt line 23 Connected to the LPTIM EXTI Line */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** \r\n  * @brief  LPTIM Clock configuration definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t Source;         /*!< Selects the clock source.\r\n                           This parameter can be a value of @ref LPTIM_Clock_Source   */\r\n\r\n  uint32_t Prescaler;      /*!< Specifies the counter clock Prescaler.\r\n                           This parameter can be a value of @ref LPTIM_Clock_Prescaler */\r\n  \r\n}LPTIM_ClockConfigTypeDef;\r\n\r\n/** \r\n  * @brief  LPTIM Clock configuration definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t Polarity;      /*!< Selects the polarity of the active edge for the counter unit\r\n                           if the ULPTIM input is selected.\r\n                           Note: This parameter is used only when Ultra low power clock source is used.\r\n                           Note: If the polarity is configured on 'both edges', an auxiliary clock\r\n                           (one of the Low power oscillator) must be active.\r\n                           This parameter can be a value of @ref LPTIM_Clock_Polarity */ \r\n  \r\n  uint32_t SampleTime;     /*!< Selects the clock sampling time to configure the clock glitch filter.\r\n                           Note: This parameter is used only when Ultra low power clock source is used.\r\n                           This parameter can be a value of @ref LPTIM_Clock_Sample_Time */  \r\n  \r\n}LPTIM_ULPClockConfigTypeDef;\r\n\r\n/** \r\n  * @brief  LPTIM Trigger configuration definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t Source;        /*!< Selects the Trigger source.\r\n                          This parameter can be a value of @ref LPTIM_Trigger_Source */\r\n  \r\n  uint32_t ActiveEdge;    /*!< Selects the Trigger active edge.\r\n                          Note: This parameter is used only when an external trigger is used.\r\n                          This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */\r\n  \r\n  uint32_t SampleTime;    /*!< Selects the trigger sampling time to configure the clock glitch filter.\r\n                          Note: This parameter is used only when an external trigger is used.\r\n                          This parameter can be a value of @ref LPTIM_Trigger_Sample_Time  */  \r\n}LPTIM_TriggerConfigTypeDef;\r\n\r\n/** \r\n  * @brief  LPTIM Initialization Structure definition  \r\n  */\r\ntypedef struct\r\n{                                                    \r\n  LPTIM_ClockConfigTypeDef     Clock;               /*!< Specifies the clock parameters */\r\n                                                    \r\n  LPTIM_ULPClockConfigTypeDef  UltraLowPowerClock;  /*!< Specifies the Ultra Low Power clock parameters */\r\n                                                    \r\n  LPTIM_TriggerConfigTypeDef   Trigger;             /*!< Specifies the Trigger parameters */\r\n                                                    \r\n  uint32_t                     OutputPolarity;      /*!< Specifies the Output polarity.\r\n                                                    This parameter can be a value of @ref LPTIM_Output_Polarity */\r\n                                                    \r\n  uint32_t                     UpdateMode;          /*!< Specifies whether the update of the autorelaod and the compare\r\n                                                    values is done immediately or after the end of current period.\r\n                                                    This parameter can be a value of @ref LPTIM_Updating_Mode */\r\n\r\n  uint32_t                     CounterSource;       /*!< Specifies whether the counter is incremented each internal event\r\n                                                    or each external event.\r\n                                                    This parameter can be a value of @ref LPTIM_Counter_Source */  \r\n  \r\n}LPTIM_InitTypeDef;\r\n\r\n/** \r\n  * @brief  HAL LPTIM State structure definition  \r\n  */ \r\ntypedef enum __HAL_LPTIM_StateTypeDef\r\n{\r\n  HAL_LPTIM_STATE_RESET            = 0x00U,    /*!< Peripheral not yet initialized or disabled  */\r\n  HAL_LPTIM_STATE_READY            = 0x01U,    /*!< Peripheral Initialized and ready for use    */\r\n  HAL_LPTIM_STATE_BUSY             = 0x02U,    /*!< An internal process is ongoing              */    \r\n  HAL_LPTIM_STATE_TIMEOUT          = 0x03U,    /*!< Timeout state                               */  \r\n  HAL_LPTIM_STATE_ERROR            = 0x04U     /*!< Internal Process is ongoing                */                                                                             \r\n}HAL_LPTIM_StateTypeDef;\r\n\r\n/** \r\n  * @brief  LPTIM handle Structure definition  \r\n  */ \r\ntypedef struct\r\n{\r\n      LPTIM_TypeDef              *Instance;         /*!< Register base address     */\r\n      \r\n      LPTIM_InitTypeDef           Init;             /*!< LPTIM required parameters */\r\n  \r\n      HAL_StatusTypeDef           Status;           /*!< LPTIM peripheral status   */  \r\n  \r\n      HAL_LockTypeDef             Lock;             /*!< LPTIM locking object      */\r\n  \r\n   __IO  HAL_LPTIM_StateTypeDef   State;            /*!< LPTIM peripheral state    */\r\n  \r\n}LPTIM_HandleTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup LPTIM_Clock_Source LPTIM Clock Source\r\n  * @{\r\n  */\r\n#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC        ((uint32_t)0x00U)\r\n#define LPTIM_CLOCKSOURCE_ULPTIM                LPTIM_CFGR_CKSEL                                           \r\n/**                                             \r\n  * @}\r\n  */\r\n\r\n/** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler\r\n  * @{\r\n  */\r\n#define LPTIM_PRESCALER_DIV1                    ((uint32_t)0x000000U)\r\n#define LPTIM_PRESCALER_DIV2                    LPTIM_CFGR_PRESC_0\r\n#define LPTIM_PRESCALER_DIV4                    LPTIM_CFGR_PRESC_1\r\n#define LPTIM_PRESCALER_DIV8                    ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1))\r\n#define LPTIM_PRESCALER_DIV16                   LPTIM_CFGR_PRESC_2\r\n#define LPTIM_PRESCALER_DIV32                   ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2))\r\n#define LPTIM_PRESCALER_DIV64                   ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2))\r\n#define LPTIM_PRESCALER_DIV128                  ((uint32_t)LPTIM_CFGR_PRESC)                                             \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity\r\n  * @{\r\n  */\r\n\r\n#define LPTIM_OUTPUTPOLARITY_HIGH               ((uint32_t)0x00000000U)\r\n#define LPTIM_OUTPUTPOLARITY_LOW                (LPTIM_CFGR_WAVPOL)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time\r\n  * @{\r\n  */\r\n#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U)\r\n#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS     LPTIM_CFGR_CKFLT_0\r\n#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS     LPTIM_CFGR_CKFLT_1\r\n#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS     LPTIM_CFGR_CKFLT\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity\r\n  * @{\r\n  */\r\n\r\n#define LPTIM_CLOCKPOLARITY_RISING                ((uint32_t)0x00000000U)\r\n#define LPTIM_CLOCKPOLARITY_FALLING               LPTIM_CFGR_CKPOL_0\r\n#define LPTIM_CLOCKPOLARITY_RISING_FALLING        LPTIM_CFGR_CKPOL_1\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source\r\n  * @{\r\n  */\r\n#define LPTIM_TRIGSOURCE_SOFTWARE               ((uint32_t)0x0000FFFFU)\r\n#define LPTIM_TRIGSOURCE_0                      ((uint32_t)0x00000000U)\r\n#define LPTIM_TRIGSOURCE_1                      ((uint32_t)LPTIM_CFGR_TRIGSEL_0)\r\n#define LPTIM_TRIGSOURCE_2                      LPTIM_CFGR_TRIGSEL_1\r\n#define LPTIM_TRIGSOURCE_3                      ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)\r\n#define LPTIM_TRIGSOURCE_4                      LPTIM_CFGR_TRIGSEL_2\r\n#define LPTIM_TRIGSOURCE_5                      ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity\r\n  * @{\r\n  */\r\n#define LPTIM_ACTIVEEDGE_RISING                LPTIM_CFGR_TRIGEN_0\r\n#define LPTIM_ACTIVEEDGE_FALLING               LPTIM_CFGR_TRIGEN_1\r\n#define LPTIM_ACTIVEEDGE_RISING_FALLING        LPTIM_CFGR_TRIGEN\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time\r\n  * @{\r\n  */\r\n#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION  ((uint32_t)0x00000000U)\r\n#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS      LPTIM_CFGR_TRGFLT_0\r\n#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS      LPTIM_CFGR_TRGFLT_1\r\n#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS      LPTIM_CFGR_TRGFLT\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode\r\n  * @{\r\n  */\r\n\r\n#define LPTIM_UPDATE_IMMEDIATE                  ((uint32_t)0x00000000U)\r\n#define LPTIM_UPDATE_ENDOFPERIOD                LPTIM_CFGR_PRELOAD\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LPTIM_Counter_Source LPTIM Counter Source\r\n  * @{\r\n  */\r\n\r\n#define LPTIM_COUNTERSOURCE_INTERNAL            ((uint32_t)0x00000000U)\r\n#define LPTIM_COUNTERSOURCE_EXTERNAL            LPTIM_CFGR_COUNTMODE\r\n/**\r\n  * @}\r\n  */\r\n \r\n/** @defgroup LPTIM_Flag_Definition LPTIM Flag Definition\r\n  * @{\r\n  */\r\n\r\n#define LPTIM_FLAG_DOWN                          LPTIM_ISR_DOWN\r\n#define LPTIM_FLAG_UP                            LPTIM_ISR_UP\r\n#define LPTIM_FLAG_ARROK                         LPTIM_ISR_ARROK\r\n#define LPTIM_FLAG_CMPOK                         LPTIM_ISR_CMPOK\r\n#define LPTIM_FLAG_EXTTRIG                       LPTIM_ISR_EXTTRIG\r\n#define LPTIM_FLAG_ARRM                          LPTIM_ISR_ARRM\r\n#define LPTIM_FLAG_CMPM                          LPTIM_ISR_CMPM\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition\r\n  * @{\r\n  */\r\n\r\n#define LPTIM_IT_DOWN                            LPTIM_IER_DOWNIE\r\n#define LPTIM_IT_UP                              LPTIM_IER_UPIE\r\n#define LPTIM_IT_ARROK                           LPTIM_IER_ARROKIE\r\n#define LPTIM_IT_CMPOK                           LPTIM_IER_CMPOKIE\r\n#define LPTIM_IT_EXTTRIG                         LPTIM_IER_EXTTRIGIE\r\n#define LPTIM_IT_ARRM                            LPTIM_IER_ARRMIE\r\n#define LPTIM_IT_CMPM                            LPTIM_IER_CMPMIE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief Reset LPTIM handle state\r\n  * @param  __HANDLE__: LPTIM handle\r\n  * @retval None\r\n  */\r\n#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)\r\n\r\n/**\r\n  * @brief  Enable/Disable the LPTIM peripheral.\r\n  * @param  __HANDLE__: LPTIM handle\r\n  * @retval None\r\n  */\r\n#define __HAL_LPTIM_ENABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR |=  (LPTIM_CR_ENABLE))\r\n#define __HAL_LPTIM_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR &=  ~(LPTIM_CR_ENABLE))\r\n\r\n/**\r\n  * @brief  Starts the LPTIM peripheral in Continuous or in single mode.\r\n  * @param  __HANDLE__: DMA handle\r\n  * @retval None\r\n  */\r\n#define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  LPTIM_CR_CNTSTRT)\r\n#define __HAL_LPTIM_START_SINGLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  LPTIM_CR_SNGSTRT)\r\n \r\n    \r\n/**\r\n  * @brief  Writes the passed parameter in the Autoreload register.\r\n  * @param  __HANDLE__: LPTIM handle\r\n  * @param  __VALUE__ : Autoreload value\r\n  * @retval None\r\n  */\r\n#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__)  ((__HANDLE__)->Instance->ARR =  (__VALUE__))\r\n\r\n/**\r\n  * @brief  Writes the passed parameter in the Compare register.\r\n  * @param  __HANDLE__: LPTIM handle\r\n  * @param  __VALUE__ : Compare value\r\n  * @retval None\r\n  */\r\n#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__)     ((__HANDLE__)->Instance->CMP =  (__VALUE__))\r\n\r\n/**\r\n  * @brief  Checks whether the specified LPTIM flag is set or not.\r\n  * @param  __HANDLE__: LPTIM handle\r\n  * @param  __FLAG__  : LPTIM flag to check\r\n  *            This parameter can be a value of:\r\n  *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.\r\n  *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.\r\n  *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.\r\n  *            @arg LPTIM_FLAG_CMPOK   : Compare register update OK Flag.\r\n  *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.\r\n  *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.\r\n  *            @arg LPTIM_FLAG_CMPM    : Compare match Flag.\r\n  * @retval The state of the specified flag (SET or RESET).\r\n  */\r\n#define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))\r\n\r\n/**\r\n  * @brief  Clears the specified LPTIM flag.\r\n  * @param  __HANDLE__: LPTIM handle.\r\n  * @param  __FLAG__  : LPTIM flag to clear.\r\n  *            This parameter can be a value of:\r\n  *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.\r\n  *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.\r\n  *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.\r\n  *            @arg LPTIM_FLAG_CMPOK   : Compare register update OK Flag.\r\n  *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.\r\n  *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.\r\n  *            @arg LPTIM_FLAG_CMPM    : Compare match Flag.\r\n  * @retval None.\r\n  */\r\n#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->ICR  = (__FLAG__))\r\n\r\n/**\r\n  * @brief  Enable the specified LPTIM interrupt.\r\n  * @param  __HANDLE__    : LPTIM handle.\r\n  * @param  __INTERRUPT__ : LPTIM interrupt to set.\r\n  *            This parameter can be a value of:\r\n  *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.\r\n  *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.\r\n  *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.\r\n  *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.\r\n  *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.\r\n  *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.\r\n  *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.\r\n  * @retval None.\r\n  */\r\n#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->IER  |= (__INTERRUPT__))\r\n\r\n /**\r\n  * @brief  Disable the specified LPTIM interrupt.\r\n  * @param  __HANDLE__    : LPTIM handle.\r\n  * @param  __INTERRUPT__ : LPTIM interrupt to set.\r\n  *            This parameter can be a value of:\r\n  *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.\r\n  *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.\r\n  *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.\r\n  *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.\r\n  *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.\r\n  *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.\r\n  *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.\r\n  * @retval None.\r\n  */\r\n#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->IER  &= (~(__INTERRUPT__)))\r\n\r\n    /**\r\n  * @brief  Checks whether the specified LPTIM interrupt is set or not.\r\n  * @param  __HANDLE__    : LPTIM handle.\r\n  * @param  __INTERRUPT__ : LPTIM interrupt to check.\r\n  *            This parameter can be a value of:\r\n  *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.\r\n  *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.\r\n  *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.\r\n  *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.\r\n  *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.\r\n  *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.\r\n  *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.\r\n  * @retval Interrupt status.\r\n  */\r\n    \r\n#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r\n\r\n/**\r\n  * @brief  Enable interrupt on the LPTIM Wake-up Timer associated Exti line.\r\n  * @retval None\r\n  */\r\n#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT()       (EXTI->IMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)\r\n\r\n/**\r\n  * @brief  Disable interrupt on the LPTIM Wake-up Timer associated Exti line.\r\n  * @retval None\r\n  */\r\n#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT()      (EXTI->IMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))\r\n\r\n/**\r\n  * @brief  Enable event on the LPTIM Wake-up Timer associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT()    (EXTI->EMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)\r\n\r\n/**\r\n  * @brief  Disable event on the LPTIM Wake-up Timer associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT()   (EXTI->EMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))\r\n\r\n/**\r\n  * @brief  Enable falling edge trigger on the LPTIM Wake-up Timer associated Exti line. \r\n  * @retval None.\r\n  */\r\n#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)\r\n\r\n/**\r\n  * @brief  Disable falling edge trigger on the LPTIM Wake-up Timer associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))\r\n\r\n/**\r\n  * @brief  Enable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)\r\n\r\n/**\r\n  * @brief  Disable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))\r\n\r\n/**\r\n  * @brief  Enable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();\\\r\n                                                                     __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();\\\r\n                                                                    }while(0)\r\n\r\n/**\r\n  * @brief  Disable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.\r\n  * This parameter can be:\r\n  * @retval None.\r\n  */\r\n#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\\\r\n                                                                      __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\\\r\n                                                                     }while(0)\r\n\r\n/**\r\n  * @brief Check whether the LPTIM Wake-up Timer associated Exti line interrupt flag is set or not.\r\n  * @retval Line Status.\r\n  */\r\n#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG()              (EXTI->PR & LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)\r\n\r\n/**\r\n  * @brief Clear the LPTIM Wake-up Timer associated Exti line flag.\r\n  * @retval None.\r\n  */\r\n#define __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG()            (EXTI->PR = LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)\r\n\r\n/**\r\n  * @brief Generate a Software interrupt on the LPTIM Wake-up Timer associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT()         (EXTI->SWIER |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)\r\n\r\n/**\r\n  * @}\r\n  */\r\n   \r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions\r\n  * @{\r\n  */\r\n\r\n/* Initialization/de-initialization functions  ********************************/\r\nHAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);\r\nHAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);\r\n\r\n/* MSP functions  *************************************************************/\r\nvoid HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);\r\nvoid HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);\r\n\r\n/* Start/Stop operation functions  *********************************************/\r\n/* ################################# PWM Mode ################################*/\r\n/* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);\r\nHAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim);\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);\r\nHAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim);\r\n\r\n/* ############################# One Pulse Mode ##############################*/\r\n/* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);\r\nHAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim);\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);\r\nHAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim);\r\n\r\n/* ############################## Set once Mode ##############################*/\r\n/* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);\r\nHAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim);\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);\r\nHAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim);\r\n\r\n/* ############################### Encoder Mode ##############################*/\r\n/* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);\r\nHAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim);\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);\r\nHAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim);\r\n\r\n/* ############################# Time out  Mode ##############################*/\r\n/* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim);\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim);\r\n\r\n/* ############################## Counter Mode ###############################*/\r\n/* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);\r\nHAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);\r\nHAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);\r\n\r\n/* Reading operation functions ************************************************/\r\nuint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);\r\nuint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);\r\nuint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);\r\n\r\n/* LPTIM IRQ functions  *******************************************************/\r\nvoid HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);\r\n\r\n/* CallBack functions  ********************************************************/\r\nvoid HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim);\r\nvoid HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim);\r\nvoid HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim);\r\nvoid HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim);\r\nvoid HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim);\r\nvoid HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim);\r\nvoid HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);\r\n\r\n/* Peripheral State functions  ************************************************/\r\nHAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Private types -------------------------------------------------------------*/\r\n/** @defgroup LPTIM_Private_Types LPTIM Private Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @defgroup LPTIM_Private_Variables LPTIM Private Variables\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup LPTIM_Private_Constants LPTIM Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup LPTIM_Private_Macros LPTIM Private Macros\r\n  * @{\r\n  */\r\n  \r\n#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__)           (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \\\r\n                                                     ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t \r\n#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__)     (((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1  ) || \\\r\n                                                     ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV2  ) || \\\r\n                                                     ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV4  ) || \\\r\n                                                     ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV8  ) || \\\r\n                                                     ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV16 ) || \\\r\n                                                     ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV32 ) || \\\r\n                                                     ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV64 ) || \\\r\n                                                     ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV128))\r\n#define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1)\t\t\t\t\t\t\t\t\t\t\t\t\t \r\n\r\n#define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__)      (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \\\r\n                                                     ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t \r\n#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__)  (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \\\r\n                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS)     || \\\r\n                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS)     || \\\r\n                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))\r\n\r\n#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__)       (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING)  || \\\r\n                                                     ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \\\r\n                                                     ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))\r\n\r\n#define IS_LPTIM_TRG_SOURCE(__TRIG__)               (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \\\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \\\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \\\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \\\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \\\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \\\r\n\t\t\t\t\t\t\t\t\t\t\t\t\t ((__TRIG__) == LPTIM_TRIGSOURCE_5))\r\n\r\n#define IS_LPTIM_EXT_TRG_POLARITY(__POLAR__)        (((__POLAR__) == LPTIM_ACTIVEEDGE_RISING         ) || \\\r\n                                                     ((__POLAR__) == LPTIM_ACTIVEEDGE_FALLING        ) || \\\r\n                                                     ((__POLAR__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))\r\n\r\n#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__)   (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \\\r\n                                                     ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS    ) || \\\r\n                                                     ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS    ) || \\\r\n                                                     ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS    ))\t\t\r\n\r\n#define IS_LPTIM_UPDATE_MODE(__MODE__)              (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \\\r\n                                                     ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))\r\n\r\n#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__)         (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \\\r\n                                                     ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))\r\n\r\n#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__)         ((__AUTORELOAD__) <= 0x0000FFFFU)\r\n\r\n#define IS_LPTIM_COMPARE(__COMPARE__)               ((__COMPARE__) <= 0x0000FFFFU)\r\n  \r\n#define IS_LPTIM_PERIOD(PERIOD)               ((PERIOD) <= 0x0000FFFFU)\r\n\r\n#define IS_LPTIM_PULSE(PULSE)                 ((PULSE) <= 0x0000FFFFU)\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup LPTIM_Private_Functions LPTIM Private Functions\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_LPTIM_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_ltdc.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of LTDC HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_LTDC_H\r\n#define __STM32F7xx_HAL_LTDC_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup LTDC LTDC\r\n  * @brief LTDC HAL module driver\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup LTDC_Exported_Types LTDC Exported Types\r\n  * @{\r\n  */\r\n#define MAX_LAYER  2\r\n\r\n/** \r\n  * @brief  LTDC color structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint8_t Blue;                    /*!< Configures the blue value.\r\n                                        This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */\r\n\r\n  uint8_t Green;                   /*!< Configures the green value.\r\n                                        This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */\r\n\r\n  uint8_t Red;                     /*!< Configures the red value. \r\n                                        This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */\r\n\r\n  uint8_t Reserved;                /*!< Reserved 0xFF */\r\n} LTDC_ColorTypeDef;\r\n\r\n/** \r\n  * @brief  LTDC Init structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t            HSPolarity;                /*!< configures the horizontal synchronization polarity.\r\n                                                      This parameter can be one value of @ref LTDC_HS_POLARITY */\r\n\r\n  uint32_t            VSPolarity;                /*!< configures the vertical synchronization polarity.\r\n                                                      This parameter can be one value of @ref LTDC_VS_POLARITY */\r\n\r\n  uint32_t            DEPolarity;                /*!< configures the data enable polarity. \r\n                                                      This parameter can be one of value of @ref LTDC_DE_POLARITY */\r\n\r\n  uint32_t            PCPolarity;                /*!< configures the pixel clock polarity. \r\n                                                      This parameter can be one of value of @ref LTDC_PC_POLARITY */\r\n\r\n  uint32_t            HorizontalSync;            /*!< configures the number of Horizontal synchronization width.\r\n                                                      This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */\r\n\r\n  uint32_t            VerticalSync;              /*!< configures the number of Vertical synchronization height. \r\n                                                      This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */\r\n\r\n  uint32_t            AccumulatedHBP;            /*!< configures the accumulated horizontal back porch width.\r\n                                                      This parameter must be a number between Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */\r\n\r\n  uint32_t            AccumulatedVBP;            /*!< configures the accumulated vertical back porch height.\r\n                                                      This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */\r\n\r\n  uint32_t            AccumulatedActiveW;        /*!< configures the accumulated active width. \r\n                                                      This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */\r\n\r\n  uint32_t            AccumulatedActiveH;        /*!< configures the accumulated active height.\r\n                                                      This parameter must be a number between Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */\r\n\r\n  uint32_t            TotalWidth;                /*!< configures the total width.\r\n                                                      This parameter must be a number between Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */\r\n\r\n  uint32_t            TotalHeigh;                /*!< configures the total height.\r\n                                                      This parameter must be a number between Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */\r\n\r\n  LTDC_ColorTypeDef   Backcolor;                 /*!< Configures the background color. */\r\n} LTDC_InitTypeDef;\r\n\r\n/** \r\n  * @brief  LTDC Layer structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t WindowX0;                   /*!< Configures the Window Horizontal Start Position.\r\n                                            This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */\r\n\r\n  uint32_t WindowX1;                   /*!< Configures the Window Horizontal Stop Position.\r\n                                            This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */\r\n\r\n  uint32_t WindowY0;                   /*!< Configures the Window vertical Start Position.\r\n                                            This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */\r\n\r\n  uint32_t WindowY1;                   /*!< Configures the Window vertical Stop Position.\r\n                                            This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FF. */\r\n\r\n  uint32_t PixelFormat;                /*!< Specifies the pixel format. \r\n                                            This parameter can be one of value of @ref LTDC_Pixelformat */\r\n\r\n  uint32_t Alpha;                      /*!< Specifies the constant alpha used for blending.\r\n                                            This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */\r\n\r\n  uint32_t Alpha0;                     /*!< Configures the default alpha value.\r\n                                            This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */\r\n\r\n  uint32_t BlendingFactor1;            /*!< Select the blending factor 1. \r\n                                            This parameter can be one of value of @ref LTDC_BlendingFactor1 */\r\n\r\n  uint32_t BlendingFactor2;            /*!< Select the blending factor 2. \r\n                                            This parameter can be one of value of @ref LTDC_BlendingFactor2 */\r\n\r\n  uint32_t FBStartAdress;              /*!< Configures the color frame buffer address */\r\n\r\n  uint32_t ImageWidth;                 /*!< Configures the color frame buffer line length. \r\n                                            This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x1FFF. */\r\n\r\n  uint32_t ImageHeight;                /*!< Specifies the number of line in frame buffer. \r\n                                            This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */\r\n\r\n  LTDC_ColorTypeDef   Backcolor;       /*!< Configures the layer background color. */\r\n} LTDC_LayerCfgTypeDef;\r\n\r\n/** \r\n  * @brief  HAL LTDC State structures definition\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_LTDC_STATE_RESET             = 0x00U,    /*!< LTDC not yet initialized or disabled */\r\n  HAL_LTDC_STATE_READY             = 0x01U,    /*!< LTDC initialized and ready for use   */\r\n  HAL_LTDC_STATE_BUSY              = 0x02U,    /*!< LTDC internal process is ongoing     */\r\n  HAL_LTDC_STATE_TIMEOUT           = 0x03U,    /*!< LTDC Timeout state                   */\r\n  HAL_LTDC_STATE_ERROR             = 0x04U     /*!< LTDC state error                     */\r\n}HAL_LTDC_StateTypeDef;\r\n\r\n/** \r\n  * @brief  LTDC handle Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  LTDC_TypeDef                *Instance;                /*!< LTDC Register base address                */\r\n\r\n  LTDC_InitTypeDef            Init;                     /*!< LTDC parameters                           */\r\n\r\n  LTDC_LayerCfgTypeDef        LayerCfg[MAX_LAYER];      /*!< LTDC Layers parameters                    */\r\n\r\n  HAL_LockTypeDef             Lock;                     /*!< LTDC Lock                                 */\r\n\r\n  __IO HAL_LTDC_StateTypeDef  State;                    /*!< LTDC state                                */\r\n\r\n  __IO uint32_t               ErrorCode;                /*!< LTDC Error code                           */\r\n\r\n} LTDC_HandleTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup LTDC_Exported_Constants LTDC Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup LTDC_Error_Code LTDC Error Code\r\n  * @{\r\n  */\r\n#define HAL_LTDC_ERROR_NONE      ((uint32_t)0x00000000U)    /*!< LTDC No error             */\r\n#define HAL_LTDC_ERROR_TE        ((uint32_t)0x00000001U)    /*!< LTDC Transfer error       */\r\n#define HAL_LTDC_ERROR_FU        ((uint32_t)0x00000002U)    /*!< LTDC FIFO Underrun        */\r\n#define HAL_LTDC_ERROR_TIMEOUT   ((uint32_t)0x00000020U)    /*!< LTDC Timeout error        */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LTDC_HS_POLARITY LTDC HS POLARITY\r\n  * @{\r\n  */\r\n#define LTDC_HSPOLARITY_AL                ((uint32_t)0x00000000U)                /*!< Horizontal Synchronization is active low. */\r\n#define LTDC_HSPOLARITY_AH                LTDC_GCR_HSPOL                        /*!< Horizontal Synchronization is active high. */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LTDC_VS_POLARITY LTDC VS POLARITY\r\n  * @{\r\n  */\r\n#define LTDC_VSPOLARITY_AL                ((uint32_t)0x00000000U)                /*!< Vertical Synchronization is active low. */\r\n#define LTDC_VSPOLARITY_AH                LTDC_GCR_VSPOL                        /*!< Vertical Synchronization is active high. */\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup LTDC_DE_POLARITY LTDC DE POLARITY\r\n  * @{\r\n  */\r\n#define LTDC_DEPOLARITY_AL                ((uint32_t)0x00000000U)                /*!< Data Enable, is active low. */\r\n#define LTDC_DEPOLARITY_AH                LTDC_GCR_DEPOL                        /*!< Data Enable, is active high. */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LTDC_PC_POLARITY LTDC PC POLARITY\r\n  * @{\r\n  */\r\n#define LTDC_PCPOLARITY_IPC               ((uint32_t)0x00000000U)                /*!< input pixel clock. */\r\n#define LTDC_PCPOLARITY_IIPC              LTDC_GCR_PCPOL                        /*!< inverted input pixel clock. */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LTDC_SYNC LTDC SYNC\r\n  * @{\r\n  */\r\n#define LTDC_HORIZONTALSYNC               (LTDC_SSCR_HSW >> 16)                 /*!< Horizontal synchronization width. */ \r\n#define LTDC_VERTICALSYNC                 LTDC_SSCR_VSH                         /*!< Vertical synchronization height. */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LTDC_BACK_COLOR LTDC BACK COLOR\r\n  * @{\r\n  */\r\n#define LTDC_COLOR                   ((uint32_t)0x000000FFU)                     /*!< Color mask */ \r\n/**\r\n  * @}\r\n  */\r\n      \r\n/** @defgroup LTDC_BlendingFactor1 LTDC Blending Factor1\r\n  * @{\r\n  */\r\n#define LTDC_BLENDING_FACTOR1_CA                       ((uint32_t)0x00000400U)   /*!< Blending factor : Cte Alpha */\r\n#define LTDC_BLENDING_FACTOR1_PAxCA                    ((uint32_t)0x00000600U)   /*!< Blending factor : Cte Alpha x Pixel Alpha*/\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LTDC_BlendingFactor2 LTDC Blending Factor2\r\n  * @{\r\n  */\r\n#define LTDC_BLENDING_FACTOR2_CA                       ((uint32_t)0x00000005U)   /*!< Blending factor : Cte Alpha */\r\n#define LTDC_BLENDING_FACTOR2_PAxCA                    ((uint32_t)0x00000007U)   /*!< Blending factor : Cte Alpha x Pixel Alpha*/\r\n/**\r\n  * @}\r\n  */\r\n      \r\n/** @defgroup LTDC_Pixelformat LTDC Pixel format\r\n  * @{\r\n  */\r\n#define LTDC_PIXEL_FORMAT_ARGB8888                  ((uint32_t)0x00000000U)      /*!< ARGB8888 LTDC pixel format */\r\n#define LTDC_PIXEL_FORMAT_RGB888                    ((uint32_t)0x00000001U)      /*!< RGB888 LTDC pixel format   */\r\n#define LTDC_PIXEL_FORMAT_RGB565                    ((uint32_t)0x00000002U)      /*!< RGB565 LTDC pixel format   */\r\n#define LTDC_PIXEL_FORMAT_ARGB1555                  ((uint32_t)0x00000003U)      /*!< ARGB1555 LTDC pixel format */\r\n#define LTDC_PIXEL_FORMAT_ARGB4444                  ((uint32_t)0x00000004U)      /*!< ARGB4444 LTDC pixel format */\r\n#define LTDC_PIXEL_FORMAT_L8                        ((uint32_t)0x00000005U)      /*!< L8 LTDC pixel format       */\r\n#define LTDC_PIXEL_FORMAT_AL44                      ((uint32_t)0x00000006U)      /*!< AL44 LTDC pixel format     */\r\n#define LTDC_PIXEL_FORMAT_AL88                      ((uint32_t)0x00000007U)      /*!< AL88 LTDC pixel format     */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LTDC_Alpha LTDC Alpha\r\n  * @{\r\n  */\r\n#define LTDC_ALPHA               LTDC_LxCACR_CONSTA                             /*!< LTDC Cte Alpha mask */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LTDC_LAYER_Config LTDC LAYER Config\r\n  * @{\r\n  */\r\n#define LTDC_STOPPOSITION                 (LTDC_LxWHPCR_WHSPPOS >> 16)          /*!< LTDC Layer stop position  */\r\n#define LTDC_STARTPOSITION                LTDC_LxWHPCR_WHSTPOS                  /*!< LTDC Layer start position */\r\n\r\n#define LTDC_COLOR_FRAME_BUFFER           LTDC_LxCFBLR_CFBLL                    /*!< LTDC Layer Line length    */ \r\n#define LTDC_LINE_NUMBER                  LTDC_LxCFBLNR_CFBLNBR                 /*!< LTDC Layer Line number    */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LTDC_Interrupts LTDC Interrupts\r\n  * @{\r\n  */\r\n#define LTDC_IT_LI                      LTDC_IER_LIE\r\n#define LTDC_IT_FU                      LTDC_IER_FUIE\r\n#define LTDC_IT_TE                      LTDC_IER_TERRIE\r\n#define LTDC_IT_RR                      LTDC_IER_RRIE\r\n/**\r\n  * @}\r\n  */\r\n      \r\n/** @defgroup LTDC_Flag LTDC Flag\r\n  * @{\r\n  */\r\n#define LTDC_FLAG_LI                     LTDC_ISR_LIF\r\n#define LTDC_FLAG_FU                     LTDC_ISR_FUIF\r\n#define LTDC_FLAG_TE                     LTDC_ISR_TERRIF\r\n#define LTDC_FLAG_RR                     LTDC_ISR_RRIF\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LTDC_Reload_Type LTDC Reload Type\r\n  * @{\r\n  */\r\n#define LTDC_RELOAD_IMMEDIATE            LTDC_SRCR_IMR       /*!< Immediate Reload */\r\n#define LTDC_RELOAD_VERTICAL_BLANKING    LTDC_SRCR_VBR       /*!< Vertical Blanking Reload */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup LTDC_Exported_Macros LTDC Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief Reset LTDC handle state\r\n  * @param  __HANDLE__: specifies the LTDC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET)\r\n\r\n/**\r\n  * @brief  Enable the LTDC.\r\n  * @param  __HANDLE__: LTDC handle\r\n  * @retval None.\r\n  */\r\n#define __HAL_LTDC_ENABLE(__HANDLE__)    ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN)\r\n\r\n/**\r\n  * @brief  Disable the LTDC.\r\n  * @param  __HANDLE__: LTDC handle\r\n  * @retval None.\r\n  */\r\n#define __HAL_LTDC_DISABLE(__HANDLE__)   ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN))\r\n\r\n/**\r\n  * @brief  Enable the LTDC Layer.\r\n  * @param  __HANDLE__: LTDC handle\r\n  * @param  __LAYER__: Specify the layer to be enabled\r\n  *                     This parameter can be 0 or 1\r\n  * @retval None.\r\n  */\r\n#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__)  ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN)\r\n\r\n/**\r\n  * @brief  Disable the LTDC Layer.\r\n  * @param  __HANDLE__: LTDC handle\r\n  * @param  __LAYER__: Specify the layer to be disabled\r\n  *                     This parameter can be 0 or 1\r\n  * @retval None.\r\n  */\r\n#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN)\r\n\r\n/**\r\n  * @brief  Reload  Layer Configuration.\r\n  * @param  __HANDLE__: LTDC handle\r\n  * @retval None.\r\n  */\r\n#define __HAL_LTDC_RELOAD_CONFIG(__HANDLE__)   ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR)\r\n\r\n/* Interrupt & Flag management */\r\n/**\r\n  * @brief  Get the LTDC pending flags.\r\n  * @param  __HANDLE__: LTDC handle\r\n  * @param  __FLAG__: Get the specified flag.\r\n  *          This parameter can be any combination of the following values:\r\n  *            @arg LTDC_FLAG_LI: Line Interrupt flag \r\n  *            @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag\r\n  *            @arg LTDC_FLAG_TE: Transfer Error interrupt flag\r\n  *            @arg LTDC_FLAG_RR: Register Reload Interrupt Flag \r\n  * @retval The state of FLAG (SET or RESET).\r\n  */\r\n#define __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))\r\n\r\n/**\r\n  * @brief  Clears the LTDC pending flags.\r\n  * @param  __HANDLE__: LTDC handle\r\n  * @param  __FLAG__: specifies the flag to clear.\r\n  *          This parameter can be any combination of the following values:\r\n  *            @arg LTDC_FLAG_LI: Line Interrupt flag \r\n  *            @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag\r\n  *            @arg LTDC_FLAG_TE: Transfer Error interrupt flag\r\n  *            @arg LTDC_FLAG_RR: Register Reload Interrupt Flag \r\n  * @retval None\r\n  */\r\n#define __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))\r\n\r\n/**\r\n  * @brief  Enables the specified LTDC interrupts.\r\n  * @param  __HANDLE__: LTDC handle\r\n  * @param __INTERRUPT__: specifies the LTDC interrupt sources to be enabled. \r\n  *          This parameter can be any combination of the following values:\r\n  *            @arg LTDC_IT_LI: Line Interrupt flag \r\n  *            @arg LTDC_IT_FU: FIFO Underrun Interrupt flag\r\n  *            @arg LTDC_IT_TE: Transfer Error interrupt flag\r\n  *            @arg LTDC_IT_RR: Register Reload Interrupt Flag\r\n  * @retval None\r\n  */\r\n#define __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disables the specified LTDC interrupts.\r\n  * @param  __HANDLE__: LTDC handle\r\n  * @param __INTERRUPT__: specifies the LTDC interrupt sources to be disabled. \r\n  *          This parameter can be any combination of the following values:\r\n  *            @arg LTDC_IT_LI: Line Interrupt flag \r\n  *            @arg LTDC_IT_FU: FIFO Underrun Interrupt flag\r\n  *            @arg LTDC_IT_TE: Transfer Error interrupt flag\r\n  *            @arg LTDC_IT_RR: Register Reload Interrupt Flag\r\n  * @retval None\r\n  */\r\n#define __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Checks whether the specified LTDC interrupt has occurred or not.\r\n  * @param  __HANDLE__: LTDC handle\r\n  * @param  __INTERRUPT__: specifies the LTDC interrupt source to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg LTDC_IT_LI: Line Interrupt flag \r\n  *            @arg LTDC_IT_FU: FIFO Underrun Interrupt flag\r\n  *            @arg LTDC_IT_TE: Transfer Error interrupt flag\r\n  *            @arg LTDC_IT_RR: Register Reload Interrupt Flag\r\n  * @retval The state of INTERRUPT (SET or RESET).\r\n  */\r\n#define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->ISR & (__INTERRUPT__))\r\n/**\r\n  * @}\r\n  */\r\n\r\n#if defined (STM32F769xx) || defined (STM32F779xx)  \r\n/* Include LTDC HAL Extension module */\r\n#include \"stm32f7xx_hal_ltdc_ex.h\"\r\n#endif /* STM32F769xx) | STM32F779xx */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup LTDC_Exported_Functions\r\n  * @{\r\n  */\r\n/** @addtogroup LTDC_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n/* Initialization and de-initialization functions *****************************/\r\nHAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc);\r\nHAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc);\r\nvoid HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc);\r\nvoid HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc);\r\nvoid HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc);\r\nvoid HAL_LTDC_LineEvenCallback(LTDC_HandleTypeDef *hltdc);\r\nvoid HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup LTDC_Exported_Functions_Group2\r\n  * @{\r\n  */\r\n/* IO operation functions *****************************************************/\r\nvoid  HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup LTDC_Exported_Functions_Group3\r\n  * @{\r\n  */\r\n/* Peripheral Control functions ***********************************************/\r\nHAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line);\r\nHAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc);\r\nHAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc);\r\nHAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType);\r\nHAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);\r\nHAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup LTDC_Exported_Functions_Group4\r\n  * @{\r\n  */\r\n/* Peripheral State functions *************************************************/\r\nHAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc);\r\nuint32_t              HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Private types -------------------------------------------------------------*/\r\n/** @defgroup LTDC_Private_Types LTDC Private Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @defgroup LTDC_Private_Variables LTDC Private Variables\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup LTDC_Private_Constants LTDC Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup LTDC_Private_Macros LTDC Private Macros\r\n  * @{\r\n  */\r\n#define LTDC_LAYER(__HANDLE__, __LAYER__)         ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84 + (0x80*(__LAYER__)))))\r\n#define IS_LTDC_LAYER(LAYER)                      ((LAYER) <= MAX_LAYER)\r\n#define IS_LTDC_HSPOL(HSPOL)                      (((HSPOL) == LTDC_HSPOLARITY_AL) || \\\r\n                                                   ((HSPOL) == LTDC_HSPOLARITY_AH))\r\n#define IS_LTDC_VSPOL(VSPOL)                      (((VSPOL) == LTDC_VSPOLARITY_AL) || \\\r\n                                                   ((VSPOL) == LTDC_VSPOLARITY_AH))\r\n#define IS_LTDC_DEPOL(DEPOL)                      (((DEPOL) ==  LTDC_DEPOLARITY_AL) || \\\r\n                                                   ((DEPOL) ==  LTDC_DEPOLARITY_AH))\r\n#define IS_LTDC_PCPOL(PCPOL)                      (((PCPOL) ==  LTDC_PCPOLARITY_IPC) || \\\r\n                                                   ((PCPOL) ==  LTDC_PCPOLARITY_IIPC))\r\n#define IS_LTDC_HSYNC(HSYNC)                      ((HSYNC)  <= LTDC_HORIZONTALSYNC)\r\n#define IS_LTDC_VSYNC(VSYNC)                      ((VSYNC)  <= LTDC_VERTICALSYNC)\r\n#define IS_LTDC_AHBP(AHBP)                        ((AHBP)   <= LTDC_HORIZONTALSYNC)\r\n#define IS_LTDC_AVBP(AVBP)                        ((AVBP)   <= LTDC_VERTICALSYNC)\r\n#define IS_LTDC_AAW(AAW)                          ((AAW)    <= LTDC_HORIZONTALSYNC)\r\n#define IS_LTDC_AAH(AAH)                          ((AAH)    <= LTDC_VERTICALSYNC)\r\n#define IS_LTDC_TOTALW(TOTALW)                    ((TOTALW) <= LTDC_HORIZONTALSYNC)\r\n#define IS_LTDC_TOTALH(TOTALH)                    ((TOTALH) <= LTDC_VERTICALSYNC)\r\n#define IS_LTDC_BLUEVALUE(BBLUE)                  ((BBLUE)  <= LTDC_COLOR)\r\n#define IS_LTDC_GREENVALUE(BGREEN)                ((BGREEN) <= LTDC_COLOR)\r\n#define IS_LTDC_REDVALUE(BRED)                    ((BRED)   <= LTDC_COLOR)\r\n#define IS_LTDC_BLENDING_FACTOR1(BlendingFactor1) (((BlendingFactor1) == LTDC_BLENDING_FACTOR1_CA) || \\\r\n                                                   ((BlendingFactor1) == LTDC_BLENDING_FACTOR1_PAxCA))\r\n#define IS_LTDC_BLENDING_FACTOR2(BlendingFactor2) (((BlendingFactor2) == LTDC_BLENDING_FACTOR2_CA) || \\\r\n                                                   ((BlendingFactor2) == LTDC_BLENDING_FACTOR2_PAxCA))\r\n#define IS_LTDC_PIXEL_FORMAT(Pixelformat)         (((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB8888) || ((Pixelformat) == LTDC_PIXEL_FORMAT_RGB888)   || \\\r\n                                                   ((Pixelformat) == LTDC_PIXEL_FORMAT_RGB565)   || ((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB1555) || \\\r\n                                                   ((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB4444) || ((Pixelformat) == LTDC_PIXEL_FORMAT_L8)       || \\\r\n                                                   ((Pixelformat) == LTDC_PIXEL_FORMAT_AL44)     || ((Pixelformat) == LTDC_PIXEL_FORMAT_AL88))\r\n#define IS_LTDC_ALPHA(ALPHA)                      ((ALPHA) <= LTDC_ALPHA)\r\n#define IS_LTDC_HCONFIGST(HCONFIGST)              ((HCONFIGST) <= LTDC_STARTPOSITION)\r\n#define IS_LTDC_HCONFIGSP(HCONFIGSP)              ((HCONFIGSP) <= LTDC_STOPPOSITION)\r\n#define IS_LTDC_VCONFIGST(VCONFIGST)              ((VCONFIGST) <= LTDC_STARTPOSITION)\r\n#define IS_LTDC_VCONFIGSP(VCONFIGSP)              ((VCONFIGSP) <= LTDC_STOPPOSITION)\r\n#define IS_LTDC_CFBP(CFBP)                        ((CFBP) <= LTDC_COLOR_FRAME_BUFFER)\r\n#define IS_LTDC_CFBLL(CFBLL)                      ((CFBLL) <= LTDC_COLOR_FRAME_BUFFER)\r\n#define IS_LTDC_CFBLNBR(CFBLNBR)                  ((CFBLNBR) <= LTDC_LINE_NUMBER)\r\n#define IS_LTDC_LIPOS(LIPOS)                      ((LIPOS) <= 0x7FF)\r\n#define IS_LTDC_RELAOD(RELOADTYPE)                (((RELOADTYPE) == LTDC_RELOAD_IMMEDIATE) || ((RELOADTYPE) == LTDC_SRCR_VBR))\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup LTDC_Private_Functions LTDC Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_LTDC_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_ltdc_ex.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of LTDC HAL Extension module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_LTDC_EX_H\r\n#define __STM32F7xx_HAL_LTDC_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n#if defined (STM32F769xx) || defined (STM32F779xx)\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n#include \"stm32f7xx_hal_dsi.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup LTDCEx\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/ \r\n/* Exported constants --------------------------------------------------------*/\r\n   \r\n/** @defgroup LTDCEx_Exported_Constants   LTDCEx Exported Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup LTDCEx_Exported_Macros LTDC Exported Macros\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup LTDCEx_Exported_Functions LTDC Extended Exported Functions\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_StructInitFromVideoConfig(LTDC_HandleTypeDef* hltdc, DSI_VidCfgTypeDef *VidCfg);\r\nHAL_StatusTypeDef HAL_LTDC_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef* hltdc, DSI_CmdCfgTypeDef *CmdCfg);\r\n/**\r\n  * @}\r\n  */ \r\n \r\n\r\n /* Private types -------------------------------------------------------------*/\r\n/** @defgroup LTDCEx_Private_Types LTDCEx Private Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @defgroup LTDCEx_Private_Variables LTDCEx Private Variables\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup LTDCEx_Private_Constants LTDCEx Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup LTDCEx_Private_Macros LTDCEx Private Macros\r\n  * @{\r\n  */\r\n\r\n /**\r\n  * @}\r\n  */ \r\n  \r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup LTDCEx_Private_Functions LTDCEx Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /*STM32F769xx | STM32F779xx */\r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_LTDC_EX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_mdios.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_mdios.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of MDIOS HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_MDIOS_H\r\n#define __STM32F7xx_HAL_MDIOS_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n#if defined (MDIOS)\r\n   \r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup MDIOS\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup MDIOS_Exported_Types MDIOS Exported Types\r\n  * @{\r\n  */\r\n   \r\n/** @defgroup MDIOS_Exported_Types_Group1 MDIOS State structures definition\r\n  * @{\r\n  */\r\n\r\ntypedef enum\r\n{\r\n  HAL_MDIOS_STATE_RESET             = 0x00U,    /*!< Peripheral not yet Initialized or disabled         */\r\n  HAL_MDIOS_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use           */\r\n  HAL_MDIOS_STATE_BUSY              = 0x02U,    /*!< an internal process is ongoing                     */\r\n  HAL_MDIOS_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                       */\r\n}HAL_MDIOS_StateTypeDef;\r\n\r\n/** \r\n  * @}\r\n  */\r\n\r\n/** @defgroup MDIOS_Exported_Types_Group2 MDIOS Init Structure definition\r\n  * @{\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  uint32_t PortAddress;           /*!< Specifies the MDIOS port address.   \r\n                                       This parameter can be a value from 0 to 31 */\r\n  uint32_t PreambleCheck;         /*!< Specifies whether the preamble check is enabled or disabled.   \r\n                                       This parameter can be a value of @ref MDIOS_Preamble_Check */   \r\n}MDIOS_InitTypeDef;\r\n\r\n/** \r\n  * @}\r\n  */\r\n\r\n/** @defgroup MDIOS_Exported_Types_Group4 MDIOS handle Structure definition\r\n  * @{\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  MDIOS_TypeDef                *Instance;     /*!< Register base address       */\r\n  \r\n  MDIOS_InitTypeDef            Init;          /*!< MDIOS Init Structure        */\r\n  \r\n  __IO HAL_MDIOS_StateTypeDef  State;         /*!< MDIOS communication state   */\r\n  \r\n  HAL_LockTypeDef              Lock;          /*!< MDIOS Lock                  */\r\n}MDIOS_HandleTypeDef;\r\n\r\n/** \r\n  * @}\r\n  */\r\n\r\n/** \r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup MDIOS_Exported_Constants MDIOS Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup MDIOS_Preamble_Check  MDIOS Preamble Check\r\n  * @{\r\n  */\r\n#define MDIOS_PREAMBLE_CHECK_ENABLE      ((uint32_t)0x00000000U)\r\n#define MDIOS_PREAMBLE_CHECK_DISABLE     MDIOS_CR_DPC  \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup MDIOS_Input_Output_Registers_Definitions MDIOS Input Output Registers Definitions\r\n  * @{\r\n  */\r\n#define MDIOS_REG0                      ((uint32_t)0x00000000U)\r\n#define MDIOS_REG1                      ((uint32_t)0x00000001U)\r\n#define MDIOS_REG2                      ((uint32_t)0x00000002U)\r\n#define MDIOS_REG3                      ((uint32_t)0x00000003U)\r\n#define MDIOS_REG4                      ((uint32_t)0x00000004U)\r\n#define MDIOS_REG5                      ((uint32_t)0x00000005U)\r\n#define MDIOS_REG6                      ((uint32_t)0x00000006U)\r\n#define MDIOS_REG7                      ((uint32_t)0x00000007U)\r\n#define MDIOS_REG8                      ((uint32_t)0x00000008U)\r\n#define MDIOS_REG9                      ((uint32_t)0x00000009U)\r\n#define MDIOS_REG10                     ((uint32_t)0x0000000AU)\r\n#define MDIOS_REG11                     ((uint32_t)0x0000000BU)\r\n#define MDIOS_REG12                     ((uint32_t)0x0000000CU)\r\n#define MDIOS_REG13                     ((uint32_t)0x0000000DU)\r\n#define MDIOS_REG14                     ((uint32_t)0x0000000EU)\r\n#define MDIOS_REG15                     ((uint32_t)0x0000000FU)\r\n#define MDIOS_REG16                     ((uint32_t)0x00000010U)\r\n#define MDIOS_REG17                     ((uint32_t)0x00000011U)\r\n#define MDIOS_REG18                     ((uint32_t)0x00000012U)\r\n#define MDIOS_REG19                     ((uint32_t)0x00000013U)\r\n#define MDIOS_REG20                     ((uint32_t)0x00000014U)\r\n#define MDIOS_REG21                     ((uint32_t)0x00000015U)\r\n#define MDIOS_REG22                     ((uint32_t)0x00000016U)\r\n#define MDIOS_REG23                     ((uint32_t)0x00000017U)\r\n#define MDIOS_REG24                     ((uint32_t)0x00000018U)\r\n#define MDIOS_REG25                     ((uint32_t)0x00000019U)\r\n#define MDIOS_REG26                     ((uint32_t)0x0000001AU)\r\n#define MDIOS_REG27                     ((uint32_t)0x0000001BU)\r\n#define MDIOS_REG28                     ((uint32_t)0x0000001CU)\r\n#define MDIOS_REG29                     ((uint32_t)0x0000001DU)\r\n#define MDIOS_REG30                     ((uint32_t)0x0000001EU)\r\n#define MDIOS_REG31                     ((uint32_t)0x0000001FU)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup MDIOS_Registers_Flags  MDIOS Registers Flags\r\n  * @{\r\n  */\r\n#define MDIOS_REG0_FLAG\t\t\t((uint32_t)0x00000001U)\r\n#define\tMDIOS_REG1_FLAG\t\t\t((uint32_t)0x00000002U)\r\n#define\tMDIOS_REG2_FLAG\t\t\t((uint32_t)0x00000004U)\r\n#define\tMDIOS_REG3_FLAG\t\t\t((uint32_t)0x00000008U)\r\n#define\tMDIOS_REG4_FLAG\t\t\t((uint32_t)0x00000010U)\r\n#define\tMDIOS_REG5_FLAG\t\t\t((uint32_t)0x00000020U)\r\n#define\tMDIOS_REG6_FLAG\t\t\t((uint32_t)0x00000040U)\r\n#define\tMDIOS_REG7_FLAG\t\t\t((uint32_t)0x00000080U)\r\n#define\tMDIOS_REG8_FLAG\t\t\t((uint32_t)0x00000100U)\r\n#define\tMDIOS_REG9_FLAG\t\t\t((uint32_t)0x00000200U)\r\n#define\tMDIOS_REG10_FLAG\t\t((uint32_t)0x00000400U)\r\n#define\tMDIOS_REG11_FLAG\t\t((uint32_t)0x00000800U)\r\n#define\tMDIOS_REG12_FLAG\t\t((uint32_t)0x00001000U)\r\n#define\tMDIOS_REG13_FLAG\t\t((uint32_t)0x00002000U)\r\n#define\tMDIOS_REG14_FLAG\t\t((uint32_t)0x00004000U)\r\n#define\tMDIOS_REG15_FLAG\t\t((uint32_t)0x00008000U)\r\n#define\tMDIOS_REG16_FLAG\t\t((uint32_t)0x00010000U)\r\n#define\tMDIOS_REG17_FLAG\t\t((uint32_t)0x00020000U)\r\n#define\tMDIOS_REG18_FLAG\t\t((uint32_t)0x00040000U)\r\n#define\tMDIOS_REG19_FLAG\t\t((uint32_t)0x00080000U)\r\n#define\tMDIOS_REG20_FLAG\t\t((uint32_t)0x00100000U)\r\n#define\tMDIOS_REG21_FLAG\t\t((uint32_t)0x00200000U)\r\n#define\tMDIOS_REG22_FLAG\t\t((uint32_t)0x00400000U)\r\n#define\tMDIOS_REG23_FLAG\t\t((uint32_t)0x00800000U)\r\n#define\tMDIOS_REG24_FLAG\t\t((uint32_t)0x01000000U)\r\n#define\tMDIOS_REG25_FLAG\t\t((uint32_t)0x02000000U)\r\n#define\tMDIOS_REG26_FLAG\t\t((uint32_t)0x04000000U)\r\n#define\tMDIOS_REG27_FLAG\t\t((uint32_t)0x08000000U)\r\n#define\tMDIOS_REG28_FLAG\t\t((uint32_t)0x10000000U)\r\n#define\tMDIOS_REG29_FLAG\t\t((uint32_t)0x20000000U)\r\n#define\tMDIOS_REG30_FLAG\t\t((uint32_t)0x40000000U)\r\n#define\tMDIOS_REG31_FLAG\t\t((uint32_t)0x80000000U)\r\n#define\tMDIOS_ALLREG_FLAG\t\t((uint32_t)0xFFFFFFFFU)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup MDIOS_Interrupt_sources Interrupt Sources\r\n  * @{\r\n  */\r\n#define MDIOS_IT_WRITE                   MDIOS_CR_WRIE\r\n#define MDIOS_IT_READ                    MDIOS_CR_RDIE\r\n#define MDIOS_IT_ERROR                   MDIOS_CR_EIE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup MDIOS_Interrupt_Flags  MDIOS Interrupt Flags\r\n  * @{\r\n  */\r\n#define\tMDIOS_TURNAROUND_ERROR_FLAG       MDIOS_SR_TERF\r\n#define\tMDIOS_START_ERROR_FLAG            MDIOS_SR_SERF\r\n#define\tMDIOS_PREAMBLE_ERROR_FLAG         MDIOS_SR_PERF\r\n/**\r\n  * @}\r\n  */\r\n\r\n /** @defgroup MDIOS_Wakeup_Line  MDIOS Wakeup Line\r\n  * @{\r\n  */\r\n#define MDIOS_WAKEUP_EXTI_LINE  ((uint32_t)0x01000000)  /* !<  EXTI Line 24 */\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */\r\n/* Exported macros -----------------------------------------------------------*/\r\n/** @defgroup MDIOS_Exported_Macros MDIOS Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief Reset MDIOS handle state\r\n  * @param  __HANDLE__: MDIOS handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_MDIOS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MDIOS_STATE_RESET)\r\n\r\n/**\r\n  * @brief  Enable/Disable the MDIOS peripheral.\r\n  * @param  __HANDLE__: specifies the MDIOS handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_MDIOS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= MDIOS_CR_EN)\r\n#define __HAL_MDIOS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~MDIOS_CR_EN)\r\n\r\n\r\n/**\r\n  * @brief  Enable the MDIOS device interrupt.\r\n  * @param  __HANDLE__: specifies the MDIOS handle.\r\n  * @param  __INTERRUPT__ : specifies the MDIOS interrupt sources to be enabled.\r\n  *         This parameter can be one or a combination of the following values:\r\n  *            @arg MDIOS_IT_WRITE: Register write interrupt\r\n  *            @arg MDIOS_IT_READ: Register read interrupt\r\n  *            @arg MDIOS_IT_ERROR: Error interrupt \r\n  * @retval None\r\n  */\r\n#define __HAL_MDIOS_ENABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disable the MDIOS device interrupt.\r\n  * @param  __HANDLE__: specifies the MDIOS handle.\r\n  * @param  __INTERRUPT__ : specifies the MDIOS interrupt sources to be disabled.\r\n  *         This parameter can be one or a combination of the following values:\r\n  *            @arg MDIOS_IT_WRITE: Register write interrupt\r\n  *            @arg MDIOS_IT_READ: Register read interrupt\r\n  *            @arg MDIOS_IT_ERROR: Error interrupt \r\n  * @retval None\r\n  */\r\n#define __HAL_MDIOS_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))\r\n\r\n/** @brief Set MDIOS slave get write register flag\r\n  * @param  __HANDLE__: specifies the MDIOS handle.\r\n  * @param  __FLAG__: specifies the write register flag\r\n  * @retval The state of write flag\r\n  */\r\n#define __HAL_MDIOS_GET_WRITE_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->WRFR &  (__FLAG__))\r\n\r\n/** @brief MDIOS slave get read register flag\r\n  * @param  __HANDLE__: specifies the MDIOS handle.\r\n  * @param  __FLAG__: specifies the read register flag\r\n  * @retval The state of read flag\r\n  */\r\n#define __HAL_MDIOS_GET_READ_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->RDFR &  (__FLAG__))\r\n\r\n/** @brief MDIOS slave get interrupt\r\n  * @param  __HANDLE__: specifies the MDIOS handle.\r\n  * @param  __FLAG__ : specifies the Error flag.\r\n  *         This parameter can be one or a combination of the following values:\r\n  *            @arg MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt\r\n  *            @arg MDIOS_START_ERROR_FLAG: Register read interrupt\r\n  *            @arg MDIOS_PREAMBLE_ERROR_FLAG: Error interrupt \r\n  * @retval The state of the error flag\r\n  */\r\n#define __HAL_MDIOS_GET_ERROR_FLAG(__HANDLE__, __FLAG__)       ((__HANDLE__)->Instance->SR &  (__FLAG__))\r\n\r\n/** @brief  MDIOS slave clear interrupt\r\n  * @param  __HANDLE__: specifies the MDIOS handle.\r\n  * @param  __FLAG__ : specifies the Error flag.\r\n  *         This parameter can be one or a combination of the following values:\r\n  *            @arg MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt\r\n  *            @arg MDIOS_START_ERROR_FLAG: Register read interrupt\r\n  *            @arg MDIOS_PREAMBLE_ERROR_FLAG: Error interrupt \r\n  * @retval none\r\n  */\r\n#define __HAL_MDIOS_CLEAR_ERROR_FLAG(__HANDLE__, __FLAG__)       ((__HANDLE__)->Instance->CLRFR) |= (__FLAG__)\r\n\r\n/**\r\n  * @brief  Checks whether the specified MDIOS interrupt is set or not.\r\n  * @param  __HANDLE__: specifies the MDIOS handle.\r\n  * @param  __INTERRUPT__ : specifies the MDIOS interrupt sources\r\n  *            This parameter can be one or a combination of the following values:\r\n  *            @arg MDIOS_IT_WRITE: Register write interrupt\r\n  *            @arg MDIOS_IT_READ: Register read interrupt\r\n  *            @arg MDIOS_IT_ERROR: Error interrupt \r\n  * @retval The state of the interrupt source\r\n  */\r\n#define __HAL_MDIOS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief Enable the MDIOS WAKEUP Exti Line.    \r\n  * @retval None.\r\n  */\r\n#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_IT()   (EXTI->IMR |= (MDIOS_WAKEUP_EXTI_LINE))\r\n\r\n/**\r\n  * @brief Disable the MDIOS WAKEUP Exti Line.    \r\n  * @retval None.\r\n  */\r\n#define __HAL_MDIOS_WAKEUP_EXTI_DISABLE_IT()   (EXTI->IMR &= ~(MDIOS_WAKEUP_EXTI_LINE)) \r\n\r\n/**\r\n  * @brief Enable event on MDIOS WAKEUP Exti Line.    \r\n  * @retval None.\r\n  */\r\n#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_EVENT()   (EXTI->EMR |= (MDIOS_WAKEUP_EXTI_LINE))\r\n\r\n/**\r\n  * @brief Disable event on MDIOS WAKEUP Exti Line.    \r\n  * @retval None.\r\n  */\r\n#define __HAL_MDIOS_WAKEUP_EXTI_DISABLE_EVENT()   (EXTI->EMR &= ~(MDIOS_WAKEUP_EXTI_LINE))   \r\n\r\n/**\r\n  * @brief checks whether the specified MDIOS WAKEUP Exti interrupt flag is set or not. \r\n  * @retval EXTI MDIOS WAKEUP Line Status.\r\n  */\r\n#define __HAL_MDIOS_WAKEUP_EXTI_GET_FLAG()  (EXTI->PR & (MDIOS_WAKEUP_EXTI_LINE))\r\n\r\n/**\r\n  * @brief Clear the MDIOS WAKEUP Exti flag. \r\n  * @retval None.\r\n  */\r\n#define __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG() (EXTI->PR = (MDIOS_WAKEUP_EXTI_LINE))\r\n\r\n/**\r\n  * @brief  Enables rising edge trigger to the MDIOS External interrupt line.\r\n  * @retval None\r\n  */\r\n#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER()  EXTI->RTSR |= MDIOS_WAKEUP_EXTI_LINE\r\n                                                            \r\n/**\r\n  * @brief  Disables the rising edge trigger to the MDIOS External interrupt line.\r\n  * @retval None\r\n  */\r\n#define __HAL_MDIOS_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER()  EXTI->RTSR &= ~(MDIOS_WAKEUP_EXTI_LINE)                                                          \r\n\r\n/**\r\n  * @brief  Enables falling edge trigger to the MDIOS External interrupt line.\r\n  * @retval None\r\n  */                                                      \r\n#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER()  EXTI->FTSR |= (MDIOS_WAKEUP_EXTI_LINE)\r\n\r\n/**\r\n  * @brief  Disables falling edge trigger to the MDIOS External interrupt line.\r\n  * @retval None\r\n  */\r\n#define __HAL_MDIOS_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER()  EXTI->FTSR &= ~(MDIOS_WAKEUP_EXTI_LINE)\r\n\r\n/**\r\n  * @brief  Enables rising/falling edge trigger to the MDIOS External interrupt line.\r\n  * @retval None\r\n  */\r\n#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER()  EXTI->RTSR |= MDIOS_WAKEUP_EXTI_LINE;\\\r\n                                                                EXTI->FTSR |= MDIOS_WAKEUP_EXTI_LINE\r\n\r\n/**\r\n  * @brief  Disables rising/falling edge trigger to the MDIOS External interrupt line.\r\n  * @retval None\r\n  */\r\n#define __HAL_MDIOS_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER()  EXTI->RTSR &= ~(MDIOS_WAKEUP_EXTI_LINE);\\\r\n                                                                 EXTI->FTSR &= ~(MDIOS_WAKEUP_EXTI_LINE)\r\n/**\r\n  * @brief  Generates a Software interrupt on selected EXTI line.\r\n  * @retval None\r\n  */\r\n#define __HAL_MDIOS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (MDIOS_WAKEUP_EXTI_LINE))  \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup MDIOS_Exported_Functions MDIOS Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup MDIOS_Exported_Functions_Group1\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef HAL_MDIOS_Init(MDIOS_HandleTypeDef *hmdios);\r\nHAL_StatusTypeDef HAL_MDIOS_DeInit(MDIOS_HandleTypeDef *hmdios);\r\nvoid HAL_MDIOS_MspInit(MDIOS_HandleTypeDef *hmdios);\r\nvoid  HAL_MDIOS_MspDeInit(MDIOS_HandleTypeDef *hmdios);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup MDIOS_Exported_Functions_Group2\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef HAL_MDIOS_WriteReg(MDIOS_HandleTypeDef *hmdios,  uint32_t RegNum, uint16_t Data);\r\nHAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios,  uint32_t RegNum, uint16_t *pData);\r\n\r\nuint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios);\r\nuint32_t HAL_MDIOS_GetReadRegAddress(MDIOS_HandleTypeDef *hmdios);\r\nHAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum);\r\nHAL_StatusTypeDef HAL_MDIOS_ClearReadRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum);\r\n\r\nHAL_StatusTypeDef HAL_MDIOS_EnableEvents(MDIOS_HandleTypeDef *hmdios);\r\nvoid HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios);\r\nvoid HAL_MDIOS_WriteCpltCallback(MDIOS_HandleTypeDef *hmdios);\r\nvoid HAL_MDIOS_ReadCpltCallback(MDIOS_HandleTypeDef *hmdios);\r\nvoid HAL_MDIOS_ErrorCallback(MDIOS_HandleTypeDef *hmdios);\r\nvoid HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup MDIOS_Exported_Functions_Group3\r\n  * @{\r\n  */\r\nuint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios);\r\nHAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/** @defgroup MDIOS_Private_Types MDIOS Private Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @defgroup MDIOS_Private_Variables MDIOS Private Variables\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup MDIOS_Private_Constants MDIOS Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup MDIOS_Private_Macros MDIOS Private Macros\r\n  * @{\r\n  */\r\n\r\n#define IS_MDIOS_PORTADDRESS(__ADDR__) ((__ADDR__) < 32)\r\n\r\n#define IS_MDIOS_REGISTER(__REGISTER__) ((__REGISTER__) < 32)\r\n\r\n#define IS_MDIOS_PREAMBLECHECK(__PREAMBLECHECK__) (((__PREAMBLECHECK__) == MDIOS_PREAMBLE_CHECK_ENABLE) || \\\r\n                                                   ((__PREAMBLECHECK__) == MDIOS_PREAMBLE_CHECK_DISABLE))\r\n\r\n /**\r\n  * @}\r\n  */\r\n  \r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup MDIOS_Private_Functions MDIOS Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* MDIOS */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_MDIOS_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_nand.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_nand.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of NAND HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_NAND_H\r\n#define __STM32F7xx_HAL_NAND_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_ll_fmc.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup NAND\r\n  * @{\r\n  */ \r\n\r\n/* Exported typedef ----------------------------------------------------------*/\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup NAND_Exported_Types NAND Exported Types\r\n  * @{\r\n  */\r\n\r\n/** \r\n  * @brief  HAL NAND State structures definition\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_NAND_STATE_RESET     = 0x00U,  /*!< NAND not yet initialized or disabled */\r\n  HAL_NAND_STATE_READY     = 0x01U,  /*!< NAND initialized and ready for use   */\r\n  HAL_NAND_STATE_BUSY      = 0x02U,  /*!< NAND internal process is ongoing     */\r\n  HAL_NAND_STATE_ERROR     = 0x03U   /*!< NAND error state                     */\r\n}HAL_NAND_StateTypeDef;\r\n   \r\n/** \r\n  * @brief  NAND Memory electronic signature Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  /*<! NAND memory electronic signature maker and device IDs */\r\n\r\n  uint8_t Maker_Id; \r\n\r\n  uint8_t Device_Id;\r\n\r\n  uint8_t Third_Id;\r\n\r\n  uint8_t Fourth_Id;\r\n}NAND_IDTypeDef;\r\n\r\n/** \r\n  * @brief  NAND Memory address Structure definition\r\n  */\r\ntypedef struct \r\n{\r\n  uint16_t Page;   /*!< NAND memory Page address  */\r\n\r\n  uint16_t Zone;   /*!< NAND memory Zone address  */\r\n\r\n  uint16_t Block;  /*!< NAND memory Block address */\r\n\r\n}NAND_AddressTypeDef;\r\n\r\n/** \r\n  * @brief  NAND Memory info Structure definition\r\n  */ \r\ntypedef struct\r\n{\r\n  uint32_t PageSize;       /*!< NAND memory page (without spare area) size measured in K. bytes */\r\n\r\n  uint32_t SpareAreaSize;  /*!< NAND memory spare area size measured in K. bytes                */\r\n\r\n  uint32_t BlockSize;      /*!< NAND memory block size number of pages                          */\r\n\r\n  uint32_t BlockNbr;       /*!< NAND memory number of blocks                                    */\r\n\r\n  uint32_t ZoneSize;       /*!< NAND memory zone size measured in number of blocks              */\r\n}NAND_InfoTypeDef;\r\n\r\n/** \r\n  * @brief  NAND handle Structure definition\r\n  */   \r\ntypedef struct\r\n{\r\n  FMC_NAND_TypeDef             *Instance;  /*!< Register base address                        */\r\n  \r\n  FMC_NAND_InitTypeDef         Init;       /*!< NAND device control configuration parameters */\r\n\r\n  HAL_LockTypeDef              Lock;       /*!< NAND locking object                          */\r\n\r\n  __IO HAL_NAND_StateTypeDef   State;      /*!< NAND device access state                     */\r\n\r\n  NAND_InfoTypeDef             Info;       /*!< NAND characteristic information structure    */\r\n}NAND_HandleTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup NAND_Exported_Macros NAND Exported Macros\r\n * @{\r\n */ \r\n\r\n/** @brief Reset NAND handle state\r\n  * @param  __HANDLE__: specifies the NAND handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup NAND_Exported_Functions NAND Exported Functions\r\n  * @{\r\n  */\r\n    \r\n/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions \r\n  * @{\r\n  */\r\n\r\n/* Initialization/de-initialization functions  ********************************/\r\nHAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);\r\nHAL_StatusTypeDef  HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);\r\nvoid               HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);\r\nvoid               HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);\r\nvoid               HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);\r\nvoid               HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions \r\n  * @{\r\n  */\r\n\r\n/* IO operation functions  ****************************************************/\r\nHAL_StatusTypeDef  HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);\r\nHAL_StatusTypeDef  HAL_NAND_Reset(NAND_HandleTypeDef *hnand);\r\n\r\nHAL_StatusTypeDef  HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);\r\nHAL_StatusTypeDef  HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);\r\nHAL_StatusTypeDef  HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);\r\nHAL_StatusTypeDef  HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);\r\nHAL_StatusTypeDef  HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);\r\nHAL_StatusTypeDef  HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);\r\nHAL_StatusTypeDef  HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);\r\nHAL_StatusTypeDef  HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);\r\nHAL_StatusTypeDef  HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);\r\nuint32_t           HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);\r\nuint32_t           HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions \r\n  * @{\r\n  */\r\n\r\n/* NAND Control functions  ****************************************************/\r\nHAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);\r\nHAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);\r\nHAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);\r\n\r\n/**\r\n  * @}\r\n  */\r\n    \r\n/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions \r\n  * @{\r\n  */\r\n/* NAND State functions *******************************************************/\r\nHAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);\r\nuint32_t              HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup NAND_Private_Constants NAND Private Constants\r\n  * @{\r\n  */\r\n#define NAND_DEVICE                ((uint32_t)0x80000000U) \r\n#define NAND_WRITE_TIMEOUT         ((uint32_t)0x01000000U)\r\n\r\n#define CMD_AREA                   ((uint32_t)(1<<16))  /* A16 = CLE high */\r\n#define ADDR_AREA                  ((uint32_t)(1<<17))  /* A17 = ALE high */\r\n\r\n#define NAND_CMD_AREA_A            ((uint8_t)0x00U)\r\n#define NAND_CMD_AREA_B            ((uint8_t)0x01U)\r\n#define NAND_CMD_AREA_C            ((uint8_t)0x50U)\r\n#define NAND_CMD_AREA_TRUE1        ((uint8_t)0x30U)\r\n\r\n#define NAND_CMD_WRITE0            ((uint8_t)0x80U)\r\n#define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10U)\r\n#define NAND_CMD_ERASE0            ((uint8_t)0x60U)\r\n#define NAND_CMD_ERASE1            ((uint8_t)0xD0U)\r\n#define NAND_CMD_READID            ((uint8_t)0x90U)\r\n#define NAND_CMD_STATUS            ((uint8_t)0x70U)\r\n#define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7AU)\r\n#define NAND_CMD_RESET             ((uint8_t)0xFFU)\r\n\r\n/* NAND memory status */\r\n#define NAND_VALID_ADDRESS         ((uint32_t)0x00000100U)\r\n#define NAND_INVALID_ADDRESS       ((uint32_t)0x00000200U)\r\n#define NAND_TIMEOUT_ERROR         ((uint32_t)0x00000400U)\r\n#define NAND_BUSY                  ((uint32_t)0x00000000U)\r\n#define NAND_ERROR                 ((uint32_t)0x00000001U)\r\n#define NAND_READY                 ((uint32_t)0x00000040U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup NAND_Private_Macros NAND Private Macros\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  NAND memory address computation.\r\n  * @param  __ADDRESS__: NAND memory address.\r\n  * @param  __HANDLE__ : NAND handle.\r\n  * @retval NAND Raw address value\r\n  */\r\n#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \\\r\n                         (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize)))\r\n\r\n/**\r\n  * @brief  NAND memory address cycling.\r\n  * @param  __ADDRESS__: NAND memory address.\r\n  * @retval NAND address cycling value.\r\n  */\r\n#define ADDR_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st addressing cycle */\r\n#define ADDR_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd addressing cycle */\r\n#define ADDR_3RD_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 16)      /* 3rd addressing cycle */\r\n#define ADDR_4TH_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 24)      /* 4th addressing cycle */\r\n/**\r\n  * @}\r\n  */\r\n    \r\n/**\r\n  * @}\r\n  */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_NAND_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_nor.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_nor.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of NOR HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_NOR_H\r\n#define __STM32F7xx_HAL_NOR_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_ll_fmc.h\"\r\n\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup NOR\r\n  * @{\r\n  */ \r\n\r\n/* Exported typedef ----------------------------------------------------------*/\r\n/** @defgroup NOR_Exported_Types NOR Exported Types\r\n  * @{\r\n  */\r\n\r\n/** \r\n  * @brief  HAL SRAM State structures definition  \r\n  */ \r\ntypedef enum\r\n{  \r\n  HAL_NOR_STATE_RESET             = 0x00U,  /*!< NOR not yet initialized or disabled  */\r\n  HAL_NOR_STATE_READY             = 0x01U,  /*!< NOR initialized and ready for use    */\r\n  HAL_NOR_STATE_BUSY              = 0x02U,  /*!< NOR internal processing is ongoing   */\r\n  HAL_NOR_STATE_ERROR             = 0x03U,  /*!< NOR error state                      */\r\n  HAL_NOR_STATE_PROTECTED         = 0x04U   /*!< NOR NORSRAM device write protected   */\r\n}HAL_NOR_StateTypeDef;\r\n\r\n/**\r\n  * @brief  FMC NOR Status typedef\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_NOR_STATUS_SUCCESS  = 0U,\r\n  HAL_NOR_STATUS_ONGOING,\r\n  HAL_NOR_STATUS_ERROR,\r\n  HAL_NOR_STATUS_TIMEOUT\r\n}HAL_NOR_StatusTypeDef;\r\n\r\n/**\r\n  * @brief  FMC NOR ID typedef\r\n  */\r\ntypedef struct\r\n{\r\n  uint16_t Manufacturer_Code;  /*!< Defines the device's manufacturer code used to identify the memory       */\r\n\r\n  uint16_t Device_Code1;\r\n\r\n  uint16_t Device_Code2;\r\n\r\n  uint16_t Device_Code3;       /*!< Defines the device's codes used to identify the memory. \r\n                                    These codes can be accessed by performing read operations with specific \r\n                                    control signals and addresses set.They can also be accessed by issuing \r\n                                    an Auto Select command                                                   */\r\n}NOR_IDTypeDef;\r\n\r\n/**\r\n  * @brief  FMC NOR CFI typedef\r\n  */\r\ntypedef struct\r\n{\r\n  /*!< Defines the information stored in the memory's Common flash interface\r\n       which contains a description of various electrical and timing parameters, \r\n       density information and functions supported by the memory                   */\r\n\r\n  uint16_t CFI_1;\r\n\r\n  uint16_t CFI_2;\r\n\r\n  uint16_t CFI_3;\r\n\r\n  uint16_t CFI_4;\r\n}NOR_CFITypeDef;\r\n\r\n/** \r\n  * @brief  NOR handle Structure definition\r\n  */ \r\ntypedef struct\r\n{\r\n  FMC_NORSRAM_TypeDef           *Instance;    /*!< Register base address                        */\r\n\r\n  FMC_NORSRAM_EXTENDED_TypeDef  *Extended;    /*!< Extended mode register base address          */\r\n\r\n  FMC_NORSRAM_InitTypeDef       Init;         /*!< NOR device control configuration parameters  */\r\n\r\n  HAL_LockTypeDef               Lock;         /*!< NOR locking object                           */\r\n\r\n  __IO HAL_NOR_StateTypeDef     State;        /*!< NOR device access state                      */\r\n\r\n}NOR_HandleTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Exported constants --------------------------------------------------------*/\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup NOR_Exported_Macros NOR Exported Macros\r\n  * @{\r\n  */\r\n/** @brief Reset NOR handle state\r\n  * @param  __HANDLE__: specifies the NOR handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup NOR_Exported_Functions NOR Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions \r\n  * @{\r\n  */\r\n\r\n/* Initialization/de-initialization functions  ********************************/\r\nHAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);\r\nHAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);\r\nvoid HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);\r\nvoid HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);\r\nvoid HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions \r\n  * @{\r\n  */\r\n\r\n/* I/O operation functions  ***************************************************/\r\nHAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);\r\nHAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);\r\nHAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);\r\nHAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);\r\n\r\nHAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);\r\nHAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);\r\n\r\nHAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);\r\nHAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);\r\nHAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions \r\n  * @{\r\n  */\r\n\r\n/* NOR Control functions  *****************************************************/\r\nHAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);\r\nHAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @addtogroup NOR_Exported_Functions_Group4 NOR State functions \r\n  * @{\r\n  */\r\n\r\n/* NOR State functions ********************************************************/\r\nHAL_NOR_StateTypeDef  HAL_NOR_GetState(NOR_HandleTypeDef *hnor);\r\nHAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);\r\n/**\r\n  * @}\r\n  */\r\n    \r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup NOR_Private_Constants NOR Private Constants\r\n  * @{\r\n  */\r\n/* NOR device IDs addresses */\r\n#define MC_ADDRESS               ((uint16_t)0x0000U)\r\n#define DEVICE_CODE1_ADDR        ((uint16_t)0x0001U)\r\n#define DEVICE_CODE2_ADDR        ((uint16_t)0x000EU)\r\n#define DEVICE_CODE3_ADDR        ((uint16_t)0x000FU)\r\n\r\n/* NOR CFI IDs addresses */\r\n#define CFI1_ADDRESS             ((uint16_t)0x61U)\r\n#define CFI2_ADDRESS             ((uint16_t)0x62U)\r\n#define CFI3_ADDRESS             ((uint16_t)0x63U)\r\n#define CFI4_ADDRESS             ((uint16_t)0x64U)\r\n\r\n/* NOR operation wait timeout */\r\n#define NOR_TMEOUT               ((uint16_t)0xFFFFU)\r\n   \r\n/* NOR memory data width */\r\n#define NOR_MEMORY_8B            ((uint8_t)0x0U)\r\n#define NOR_MEMORY_16B           ((uint8_t)0x1U)\r\n\r\n/* NOR memory device read/write start address */\r\n#define NOR_MEMORY_ADRESS1       ((uint32_t)0x60000000U)\r\n#define NOR_MEMORY_ADRESS2       ((uint32_t)0x64000000U)\r\n#define NOR_MEMORY_ADRESS3       ((uint32_t)0x68000000U)\r\n#define NOR_MEMORY_ADRESS4       ((uint32_t)0x6C000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup NOR_Private_Macros NOR Private Macros\r\n  * @{\r\n  */\r\n/**\r\n  * @brief  NOR memory address shifting.\r\n  * @param  __NOR_ADDRESS: NOR base address \r\n  * @param  __NOR_MEMORY_WIDTH_: NOR memory width\r\n  * @param  __ADDRESS__: NOR memory address \r\n  * @retval NOR shifted address value\r\n  */\r\n#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)       \\\r\n            ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)?              \\\r\n              ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))):              \\\r\n              ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))\r\n \r\n/**\r\n  * @brief  NOR memory write data to specified address.\r\n  * @param  __ADDRESS__: NOR memory address \r\n  * @param  __DATA__: Data to write\r\n  * @retval None\r\n  */\r\n#define NOR_WRITE(__ADDRESS__, __DATA__)   do{                                                             \\\r\n                                                 (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \\\r\n                                                 __DSB();                                                    \\\r\n                                               } while(0)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_NOR_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_pcd.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of PCD HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_PCD_H\r\n#define __STM32F7xx_HAL_PCD_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_ll_usb.h\"\r\n   \r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup PCD\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/ \r\n/** @defgroup PCD_Exported_Types PCD Exported Types\r\n  * @{\r\n  */\r\n   \r\n/**\r\n  * @brief  PCD State structure definition\r\n  */ \r\ntypedef enum \r\n{\r\n  HAL_PCD_STATE_RESET   = 0x00U,\r\n  HAL_PCD_STATE_READY   = 0x01U,\r\n  HAL_PCD_STATE_ERROR   = 0x02U,\r\n  HAL_PCD_STATE_BUSY    = 0x03U,\r\n  HAL_PCD_STATE_TIMEOUT = 0x04U\r\n} PCD_StateTypeDef;\r\n\r\n/* Device LPM suspend state */\r\ntypedef enum  \r\n{\r\n  LPM_L0 = 0x00U, /* on */\r\n  LPM_L1 = 0x01U, /* LPM L1 sleep */\r\n  LPM_L2 = 0x02U, /* suspend */\r\n  LPM_L3 = 0x03U, /* off */\r\n}PCD_LPM_StateTypeDef;\r\n\r\ntypedef USB_OTG_GlobalTypeDef  PCD_TypeDef;\r\ntypedef USB_OTG_CfgTypeDef     PCD_InitTypeDef;\r\ntypedef USB_OTG_EPTypeDef      PCD_EPTypeDef ;                          \r\n\r\n/** \r\n  * @brief  PCD Handle Structure definition  \r\n  */ \r\ntypedef struct\r\n{\r\n  PCD_TypeDef             *Instance;   /*!< Register base address              */ \r\n  PCD_InitTypeDef         Init;       /*!< PCD required parameters            */\r\n  PCD_EPTypeDef           IN_ep[15];  /*!< IN endpoint parameters             */\r\n  PCD_EPTypeDef           OUT_ep[15]; /*!< OUT endpoint parameters            */ \r\n  HAL_LockTypeDef         Lock;       /*!< PCD peripheral status              */\r\n  __IO PCD_StateTypeDef   State;      /*!< PCD communication state            */\r\n  uint32_t                Setup[12];  /*!< Setup packet buffer                */\r\n  PCD_LPM_StateTypeDef    LPM_State;    /*!< LPM State                          */\r\n  uint32_t                BESL;\r\n  uint32_t                lpm_active;   /*!< Enable or disable the Link Power Management .                                  \r\n                                        This parameter can be set to ENABLE or DISABLE */\r\n  void                    *pData;       /*!< Pointer to upper stack Handler */  \r\n} PCD_HandleTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n    \r\n/* Include PCD HAL Extension module */\r\n#include \"stm32f7xx_hal_pcd_ex.h\"\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup PCD_Exported_Constants PCD Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup PCD_Speed PCD Speed\r\n  * @{\r\n  */\r\n#define PCD_SPEED_HIGH               0U\r\n#define PCD_SPEED_HIGH_IN_FULL       1U\r\n#define PCD_SPEED_FULL               2U\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup PCD_PHY_Module PCD PHY Module\r\n  * @{\r\n  */\r\n#define PCD_PHY_ULPI                 1U\r\n#define PCD_PHY_EMBEDDED             2U\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup PCD_Turnaround_Timeout Turnaround Timeout Value\r\n  * @{\r\n  */\r\n#ifndef USBD_HS_TRDT_VALUE\r\n #define USBD_HS_TRDT_VALUE           9U\r\n#endif /* USBD_HS_TRDT_VALUE */\r\n#ifndef USBD_FS_TRDT_VALUE\r\n #define USBD_FS_TRDT_VALUE           5U\r\n#endif /* USBD_HS_TRDT_VALUE */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/* Exported macros -----------------------------------------------------------*/\r\n/** @defgroup PCD_Exported_Macros PCD Exported Macros\r\n *  @brief macros to handle interrupts and specific clock configurations\r\n * @{\r\n */\r\n#define __HAL_PCD_ENABLE(__HANDLE__)                   USB_EnableGlobalInt ((__HANDLE__)->Instance)\r\n#define __HAL_PCD_DISABLE(__HANDLE__)                  USB_DisableGlobalInt ((__HANDLE__)->Instance)\r\n   \r\n#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))\r\n#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))\r\n#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)\r\n\r\n\r\n#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)             *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \\\r\n                                                       ~(USB_OTG_PCGCCTL_STOPCLK)\r\n\r\n#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__)               *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK\r\n                                                      \r\n#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__)            ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10)\r\n                                                         \r\n#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE                ((uint32_t)0x08U) \r\n#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE               ((uint32_t)0x0CU) \r\n#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE        ((uint32_t)0x10U) \r\n\r\n#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE                ((uint32_t)0x08U) \r\n#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE               ((uint32_t)0x0CU) \r\n#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE        ((uint32_t)0x10U) \r\n\r\n#define USB_OTG_HS_WAKEUP_EXTI_LINE                       ((uint32_t)0x00100000U)  /*!< External interrupt line 20 Connected to the USB HS EXTI Line */\r\n#define USB_OTG_FS_WAKEUP_EXTI_LINE                       ((uint32_t)0x00040000U)  /*!< External interrupt line 18 Connected to the USB FS EXTI Line */\r\n\r\n#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT()    EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE)\r\n#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT()   EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)\r\n#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG()     EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE)\r\n#define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG()   EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE)\r\n\r\n#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\\\r\n                                                          EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE\r\n                                                      \r\n#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE()  EXTI->FTSR |= (USB_OTG_HS_WAKEUP_EXTI_LINE);\\\r\n                                                            EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)\r\n\r\n#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()   EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\\\r\n                                                                    EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE;)\\\r\n                                                                    EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\\\r\n                                                                    EXTI->FTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE\r\n\r\n#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT()   (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE) \r\n                                                                                                                    \r\n#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT()    EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE\r\n#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT()   EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)\r\n#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG()     EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)\r\n#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG()   EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE\r\n\r\n#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\\\r\n                                                          EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE\r\n\r\n                                                      \r\n#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE()  EXTI->FTSR |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\\\r\n                                                            EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)\r\n\r\n#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()  EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\\\r\n                                                                   EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\\\r\n                                                                   EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\\\r\n                                                                   EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE \r\n                                                         \r\n#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT()  (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)                                                     \r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup PCD_Exported_Functions PCD Exported Functions\r\n  * @{\r\n  */\r\n\r\n/* Initialization/de-initialization functions  ********************************/\r\n/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);\r\nHAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);\r\nvoid HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);\r\nvoid HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* I/O operation functions  ***************************************************/\r\n/* Non-Blocking mode: Interrupt */\r\n/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);\r\nHAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);\r\nvoid HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);\r\n\r\nvoid HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);\r\nvoid HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);\r\nvoid HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);\r\nvoid HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);\r\nvoid HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);\r\nvoid HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);\r\nvoid HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);\r\nvoid HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);\r\nvoid HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);\r\nvoid HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);\r\nvoid HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Peripheral Control functions  **********************************************/\r\n/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);\r\nHAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);\r\nHAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);\r\nHAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);\r\nHAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);\r\nHAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);\r\nHAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);\r\nuint16_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);\r\nHAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);\r\nHAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);\r\nHAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);\r\nHAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);\r\nHAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Peripheral State functions  ************************************************/\r\n/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions\r\n  * @{\r\n  */\r\nPCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup PCD_Private_Macros PCD Private Macros\r\n * @{\r\n */\r\n/** @defgroup PCD_Instance_definition PCD Instance definition\r\n  * @{\r\n  */\r\n#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \\\r\n                                       ((INSTANCE) == USB_OTG_HS))\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n\r\n#endif /* __STM32F7xx_HAL_PCD_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_pcd_ex.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of PCD HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_PCD_EX_H\r\n#define __STM32F7xx_HAL_PCD_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n   \r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup PCDEx\r\n  * @{\r\n  */\r\n/* Exported types ------------------------------------------------------------*/\r\ntypedef enum  \r\n{\r\n  PCD_LPM_L0_ACTIVE = 0x00U, /* on */\r\n  PCD_LPM_L1_ACTIVE = 0x01U, /* LPM L1 sleep */\r\n}PCD_LPM_MsgTypeDef;\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/* Exported macros -----------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions\r\n  * @{\r\n  */\r\n/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);\r\nHAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);\r\nHAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);\r\nHAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);\r\nvoid HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n\r\n#endif /* __STM32F7xx_HAL_PCD_EX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_pwr.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of PWR HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_PWR_H\r\n#define __STM32F7xx_HAL_PWR_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup PWR\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n\r\n/** @defgroup PWR_Exported_Types PWR Exported Types\r\n  * @{\r\n  */\r\n   \r\n/**\r\n  * @brief  PWR PVD configuration structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t PVDLevel;   /*!< PVDLevel: Specifies the PVD detection level.\r\n                            This parameter can be a value of @ref PWR_PVD_detection_level */\r\n\r\n  uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.\r\n                           This parameter can be a value of @ref PWR_PVD_Mode */\r\n}PWR_PVDTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup PWR_Exported_Constants PWR Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup PWR_PVD_detection_level PWR PVD detection level\r\n  * @{\r\n  */ \r\n#define PWR_PVDLEVEL_0                  PWR_CR1_PLS_LEV0\r\n#define PWR_PVDLEVEL_1                  PWR_CR1_PLS_LEV1\r\n#define PWR_PVDLEVEL_2                  PWR_CR1_PLS_LEV2\r\n#define PWR_PVDLEVEL_3                  PWR_CR1_PLS_LEV3\r\n#define PWR_PVDLEVEL_4                  PWR_CR1_PLS_LEV4\r\n#define PWR_PVDLEVEL_5                  PWR_CR1_PLS_LEV5\r\n#define PWR_PVDLEVEL_6                  PWR_CR1_PLS_LEV6\r\n#define PWR_PVDLEVEL_7                  PWR_CR1_PLS_LEV7/* External input analog voltage \r\n                                                          (Compare internally to VREFINT) */\r\n\r\n/**\r\n  * @}\r\n  */   \r\n \r\n/** @defgroup PWR_PVD_Mode PWR PVD Mode\r\n  * @{\r\n  */\r\n#define PWR_PVD_MODE_NORMAL                 ((uint32_t)0x00000000U)   /*!< basic mode is used */\r\n#define PWR_PVD_MODE_IT_RISING              ((uint32_t)0x00010001U)   /*!< External Interrupt Mode with Rising edge trigger detection */\r\n#define PWR_PVD_MODE_IT_FALLING             ((uint32_t)0x00010002U)   /*!< External Interrupt Mode with Falling edge trigger detection */\r\n#define PWR_PVD_MODE_IT_RISING_FALLING      ((uint32_t)0x00010003U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */\r\n#define PWR_PVD_MODE_EVENT_RISING           ((uint32_t)0x00020001U)   /*!< Event Mode with Rising edge trigger detection */\r\n#define PWR_PVD_MODE_EVENT_FALLING          ((uint32_t)0x00020002U)   /*!< Event Mode with Falling edge trigger detection */\r\n#define PWR_PVD_MODE_EVENT_RISING_FALLING   ((uint32_t)0x00020003U)   /*!< Event Mode with Rising/Falling edge trigger detection */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode\r\n  * @{\r\n  */\r\n#define PWR_MAINREGULATOR_ON                        ((uint32_t)0x00000000U)\r\n#define PWR_LOWPOWERREGULATOR_ON                    PWR_CR1_LPDS\r\n/**\r\n  * @}\r\n  */\r\n    \r\n/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry\r\n  * @{\r\n  */\r\n#define PWR_SLEEPENTRY_WFI              ((uint8_t)0x01U)\r\n#define PWR_SLEEPENTRY_WFE              ((uint8_t)0x02U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry\r\n  * @{\r\n  */\r\n#define PWR_STOPENTRY_WFI               ((uint8_t)0x01U)\r\n#define PWR_STOPENTRY_WFE               ((uint8_t)0x02U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale\r\n  * @{\r\n  */\r\n#define PWR_REGULATOR_VOLTAGE_SCALE1         PWR_CR1_VOS\r\n#define PWR_REGULATOR_VOLTAGE_SCALE2         PWR_CR1_VOS_1\r\n#define PWR_REGULATOR_VOLTAGE_SCALE3         PWR_CR1_VOS_0\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup PWR_Flag PWR Flag\r\n  * @{\r\n  */\r\n#define PWR_FLAG_WU                     PWR_CSR1_WUIF\r\n#define PWR_FLAG_SB                     PWR_CSR1_SBF\r\n#define PWR_FLAG_PVDO                   PWR_CSR1_PVDO\r\n#define PWR_FLAG_BRR                    PWR_CSR1_BRR\r\n#define PWR_FLAG_VOSRDY                 PWR_CSR1_VOSRDY\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup PWR_Exported_Macro PWR Exported Macro\r\n  * @{\r\n  */\r\n\r\n/** @brief  macros configure the main internal regulator output voltage.\r\n  * @param  __REGULATOR__: specifies the regulator output voltage to achieve\r\n  *         a tradeoff between performance and power consumption when the device does\r\n  *         not operate at the maximum frequency (refer to the datasheets for more details).\r\n  *          This parameter can be one of the following values:\r\n  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode\r\n  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode\r\n  *            @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode\r\n  * @retval None\r\n  */\r\n#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do {                                                     \\\r\n                                                            __IO uint32_t tmpreg;                               \\\r\n                                                            MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \\\r\n                                                            /* Delay after an RCC peripheral clock enabling */  \\\r\n                                                            tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS);           \\\r\n                                                            UNUSED(tmpreg);                                     \\\r\n\t\t\t\t                                                \t} while(0)\r\n\r\n/** @brief  Check PWR flag is set or not.\r\n  * @param  __FLAG__: specifies the flag to check.\r\n  *           This parameter can be one of the following values:\r\n  *            @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event \r\n  *                  was received on the internal wakeup line in standby mode (RTC alarm (Alarm A or Alarm B),\r\n  *                  RTC Tamper event, RTC TimeStamp event or RTC Wakeup)).\r\n  *            @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was\r\n  *                  resumed from StandBy mode.    \r\n  *            @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled \r\n  *                  by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode \r\n  *                  For this reason, this bit is equal to 0 after Standby or reset\r\n  *                  until the PVDE bit is set.\r\n  *            @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset \r\n  *                  when the device wakes up from Standby mode or by a system reset \r\n  *                  or power reset.  \r\n  *            @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage \r\n  *                 scaling output selection is ready.\r\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__))\r\n\r\n/** @brief  Clear the PWR's pending flags.\r\n  * @param  __FLAG__: specifies the flag to clear.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg PWR_FLAG_SB: StandBy flag\r\n  */\r\n#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR1 |=  (__FLAG__) << 2)\r\n\r\n/**\r\n  * @brief Enable the PVD Exti Line 16.\r\n  * @retval None.\r\n  */\r\n#define __HAL_PWR_PVD_EXTI_ENABLE_IT()   (EXTI->IMR |= (PWR_EXTI_LINE_PVD))\r\n\r\n/**\r\n  * @brief Disable the PVD EXTI Line 16.\r\n  * @retval None.\r\n  */\r\n#define __HAL_PWR_PVD_EXTI_DISABLE_IT()  (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))\r\n\r\n/**\r\n  * @brief Enable event on PVD Exti Line 16.\r\n  * @retval None.\r\n  */\r\n#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT()   (EXTI->EMR |= (PWR_EXTI_LINE_PVD))\r\n\r\n/**\r\n  * @brief Disable event on PVD Exti Line 16.\r\n  * @retval None.\r\n  */\r\n#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT()  (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))\r\n\r\n/**\r\n  * @brief Enable the PVD Extended Interrupt Rising Trigger.\r\n  * @retval None.\r\n  */\r\n#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)\r\n\r\n/**\r\n  * @brief Disable the PVD Extended Interrupt Rising Trigger.\r\n  * @retval None.\r\n  */\r\n#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)\r\n\r\n/**\r\n  * @brief Enable the PVD Extended Interrupt Falling Trigger.\r\n  * @retval None.\r\n  */\r\n#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)\r\n\r\n\r\n/**\r\n  * @brief Disable the PVD Extended Interrupt Falling Trigger.\r\n  * @retval None.\r\n  */\r\n#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)\r\n\r\n\r\n/**\r\n  * @brief  PVD EXTI line configuration: set rising & falling edge trigger.\r\n  * @retval None.\r\n  */\r\n#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()   __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\r\n\r\n/**\r\n  * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.\r\n  * @retval None.\r\n  */\r\n#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\r\n\r\n/**\r\n  * @brief checks whether the specified PVD Exti interrupt flag is set or not.\r\n  * @retval EXTI PVD Line Status.\r\n  */\r\n#define __HAL_PWR_PVD_EXTI_GET_FLAG()  (EXTI->PR & (PWR_EXTI_LINE_PVD))\r\n\r\n/**\r\n  * @brief Clear the PVD Exti flag.\r\n  * @retval None.\r\n  */\r\n#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG()  (EXTI->PR = (PWR_EXTI_LINE_PVD))\r\n\r\n/**\r\n  * @brief  Generates a Software interrupt on PVD EXTI line.\r\n  * @retval None\r\n  */\r\n#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Include PWR HAL Extension module */\r\n#include \"stm32f7xx_hal_pwr_ex.h\"\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup PWR_Exported_Functions PWR Exported Functions\r\n  * @{\r\n  */\r\n  \r\n/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions \r\n  * @{\r\n  */\r\n/* Initialization and de-initialization functions *****************************/\r\nvoid HAL_PWR_DeInit(void);\r\nvoid HAL_PWR_EnableBkUpAccess(void);\r\nvoid HAL_PWR_DisableBkUpAccess(void);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions \r\n  * @{\r\n  */\r\n/* Peripheral Control functions  **********************************************/\r\n/* PVD configuration */\r\nvoid HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);\r\nvoid HAL_PWR_EnablePVD(void);\r\nvoid HAL_PWR_DisablePVD(void);\r\n\r\n/* WakeUp pins configuration */\r\nvoid HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);\r\nvoid HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);\r\n\r\n/* Low Power modes entry */\r\nvoid HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);\r\nvoid HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);\r\nvoid HAL_PWR_EnterSTANDBYMode(void);\r\n\r\n/* Power PVD IRQ Handler */\r\nvoid HAL_PWR_PVD_IRQHandler(void);\r\nvoid HAL_PWR_PVDCallback(void);\r\n\r\n/* Cortex System Control functions  *******************************************/\r\nvoid HAL_PWR_EnableSleepOnExit(void);\r\nvoid HAL_PWR_DisableSleepOnExit(void);\r\nvoid HAL_PWR_EnableSEVOnPend(void);\r\nvoid HAL_PWR_DisableSEVOnPend(void);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup PWR_Private_Constants PWR Private Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line\r\n  * @{\r\n  */\r\n#define PWR_EXTI_LINE_PVD  ((uint32_t)EXTI_IMR_IM16)  /*!< External interrupt line 16 Connected to the PVD EXTI Line */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup PWR_Private_Macros PWR Private Macros\r\n  * @{\r\n  */\r\n\r\n/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters\r\n  * @{\r\n  */\r\n#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \\\r\n                                 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \\\r\n                                 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \\\r\n                                 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))\r\n#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \\\r\n                              ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \\\r\n                              ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \\\r\n                              ((MODE) == PWR_PVD_MODE_NORMAL))\r\n#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \\\r\n                                     ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))\r\n#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))\r\n#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))\r\n#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \\\r\n                                           ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \\\r\n                                           ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n\r\n#endif /* __STM32F7xx_HAL_PWR_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_pwr_ex.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of PWR HAL Extension module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_PWR_EX_H\r\n#define __STM32F7xx_HAL_PWR_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup PWREx\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/ \r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup PWREx_Exported_Constants PWREx Exported Constants\r\n  * @{\r\n  */\r\n/** @defgroup PWREx_WakeUp_Pins PWREx Wake Up Pins\r\n  * @{\r\n  */\r\n#define PWR_WAKEUP_PIN1                PWR_CSR2_EWUP1\r\n#define PWR_WAKEUP_PIN2                PWR_CSR2_EWUP2\r\n#define PWR_WAKEUP_PIN3                PWR_CSR2_EWUP3\r\n#define PWR_WAKEUP_PIN4                PWR_CSR2_EWUP4\r\n#define PWR_WAKEUP_PIN5                PWR_CSR2_EWUP5\r\n#define PWR_WAKEUP_PIN6                PWR_CSR2_EWUP6\r\n#define PWR_WAKEUP_PIN1_HIGH           PWR_CSR2_EWUP1\r\n#define PWR_WAKEUP_PIN2_HIGH           PWR_CSR2_EWUP2\r\n#define PWR_WAKEUP_PIN3_HIGH           PWR_CSR2_EWUP3\r\n#define PWR_WAKEUP_PIN4_HIGH           PWR_CSR2_EWUP4\r\n#define PWR_WAKEUP_PIN5_HIGH           PWR_CSR2_EWUP5\r\n#define PWR_WAKEUP_PIN6_HIGH           PWR_CSR2_EWUP6\r\n#define PWR_WAKEUP_PIN1_LOW            (uint32_t)((PWR_CR2_WUPP1<<6) | PWR_CSR2_EWUP1)\r\n#define PWR_WAKEUP_PIN2_LOW            (uint32_t)((PWR_CR2_WUPP2<<6) | PWR_CSR2_EWUP2)\r\n#define PWR_WAKEUP_PIN3_LOW            (uint32_t)((PWR_CR2_WUPP3<<6) | PWR_CSR2_EWUP3)\r\n#define PWR_WAKEUP_PIN4_LOW            (uint32_t)((PWR_CR2_WUPP4<<6) | PWR_CSR2_EWUP4)\r\n#define PWR_WAKEUP_PIN5_LOW            (uint32_t)((PWR_CR2_WUPP5<<6) | PWR_CSR2_EWUP5)\r\n#define PWR_WAKEUP_PIN6_LOW            (uint32_t)((PWR_CR2_WUPP6<<6) | PWR_CSR2_EWUP6)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\t\r\n/** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode\r\n  * @{\r\n  */\r\n#define PWR_MAINREGULATOR_UNDERDRIVE_ON                       PWR_CR1_MRUDS\r\n#define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON                   ((uint32_t)(PWR_CR1_LPDS | PWR_CR1_LPUDS))\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag\r\n  * @{\r\n  */\r\n#define PWR_FLAG_ODRDY                  PWR_CSR1_ODRDY\r\n#define PWR_FLAG_ODSWRDY                PWR_CSR1_ODSWRDY\r\n#define PWR_FLAG_UDRDY                  PWR_CSR1_UDRDY\r\n/**\r\n  * @}\r\n  */\r\n\t\r\n/** @defgroup PWREx_Wakeup_Pins_Flag PWREx Wake Up Pin Flags\r\n  * @{\r\n  */\r\n#define PWR_WAKEUP_PIN_FLAG1            PWR_CSR2_WUPF1\r\n#define PWR_WAKEUP_PIN_FLAG2            PWR_CSR2_WUPF2\r\n#define PWR_WAKEUP_PIN_FLAG3            PWR_CSR2_WUPF3\r\n#define PWR_WAKEUP_PIN_FLAG4            PWR_CSR2_WUPF4\r\n#define PWR_WAKEUP_PIN_FLAG5            PWR_CSR2_WUPF5\r\n#define PWR_WAKEUP_PIN_FLAG6            PWR_CSR2_WUPF6\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup PWREx_Exported_Macro PWREx Exported Macro\r\n  *  @{\r\n  */\r\n/** @brief Macros to enable or disable the Over drive mode.\r\n  */\r\n#define __HAL_PWR_OVERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODEN)\r\n#define __HAL_PWR_OVERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODEN))\r\n\r\n/** @brief Macros to enable or disable the Over drive switching.\r\n  */\r\n#define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODSWEN)\r\n#define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODSWEN))\r\n\r\n/** @brief Macros to enable or disable the Under drive mode.\r\n  * @note  This mode is enabled only with STOP low power mode.\r\n  *        In this mode, the 1.2V domain is preserved in reduced leakage mode. This \r\n  *        mode is only available when the main regulator or the low power regulator \r\n  *        is in low voltage mode.      \r\n  * @note  If the Under-drive mode was enabled, it is automatically disabled after \r\n  *        exiting Stop mode. \r\n  *        When the voltage regulator operates in Under-drive mode, an additional  \r\n  *        startup delay is induced when waking up from Stop mode.\r\n  */\r\n#define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_UDEN)\r\n#define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_UDEN))\r\n\r\n/** @brief  Check PWR flag is set or not.\r\n  * @param  __FLAG__: specifies the flag to check.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode\r\n  *                                 is ready \r\n  *            @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode\r\n  *                                   switching is ready  \r\n  *            @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode\r\n  *                                 is enabled in Stop mode\r\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__))\r\n\r\n/** @brief Clear the Under-Drive Ready flag.\r\n  */\r\n#define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR1 |= PWR_FLAG_UDRDY)\r\n\r\n/** @brief  Check Wake Up flag is set or not.\r\n  * @param  __WUFLAG__: specifies the Wake Up flag to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0\r\n  *            @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2\r\n  *            @arg PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag for PC1\r\n  *            @arg PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag for PC13\r\n  *            @arg PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag for PI8\r\n  *            @arg PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag for PI11          \r\n  */\r\n#define __HAL_PWR_GET_WAKEUP_FLAG(__WUFLAG__) (PWR->CSR2 & (__WUFLAG__))\r\n\r\n/** @brief  Clear the WakeUp pins flags.\r\n  * @param  __WUFLAG__: specifies the Wake Up pin flag to clear.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0\r\n  *            @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2\r\n  *            @arg PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag for PC1\r\n  *            @arg PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag for PC13\r\n  *            @arg PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag for PI8\r\n  *            @arg PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag for PI11          \r\n  */\r\n#define __HAL_PWR_CLEAR_WAKEUP_FLAG(__WUFLAG__) (PWR->CR2 |=  (__WUFLAG__))\r\n/**\r\n  * @}\r\n  */\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions\r\n  *  @{\r\n  */\r\n \r\n/** @addtogroup PWREx_Exported_Functions_Group1\r\n  * @{\r\n  */\r\nuint32_t HAL_PWREx_GetVoltageRange(void);\r\nHAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);\r\n\r\nvoid HAL_PWREx_EnableFlashPowerDown(void);\r\nvoid HAL_PWREx_DisableFlashPowerDown(void); \r\nHAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);\r\nHAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void); \r\n\r\nvoid HAL_PWREx_EnableMainRegulatorLowVoltage(void);\r\nvoid HAL_PWREx_DisableMainRegulatorLowVoltage(void);\r\nvoid HAL_PWREx_EnableLowRegulatorLowVoltage(void);\r\nvoid HAL_PWREx_DisableLowRegulatorLowVoltage(void);\r\n\r\nHAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void);\r\nHAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void);\r\nHAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup PWREx_Private_Macros PWREx Private Macros\r\n  * @{\r\n  */\r\n\r\n/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters\r\n  * @{\r\n  */\r\n#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \\\r\n                                                ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON))\r\n#define IS_PWR_WAKEUP_PIN(__PIN__)         (((__PIN__) == PWR_WAKEUP_PIN1)       || \\\r\n                                            ((__PIN__) == PWR_WAKEUP_PIN2)       || \\\r\n                                            ((__PIN__) == PWR_WAKEUP_PIN3)       || \\\r\n                                            ((__PIN__) == PWR_WAKEUP_PIN4)       || \\\r\n                                            ((__PIN__) == PWR_WAKEUP_PIN5)       || \\\r\n                                            ((__PIN__) == PWR_WAKEUP_PIN6)  \t\t || \\\r\n                                            ((__PIN__) == PWR_WAKEUP_PIN1_HIGH)  || \\\r\n                                            ((__PIN__) == PWR_WAKEUP_PIN2_HIGH)  || \\\r\n                                            ((__PIN__) == PWR_WAKEUP_PIN3_HIGH)  || \\\r\n                                            ((__PIN__) == PWR_WAKEUP_PIN4_HIGH)  || \\\r\n                                            ((__PIN__) == PWR_WAKEUP_PIN5_HIGH)  || \\\r\n                                            ((__PIN__) == PWR_WAKEUP_PIN6_HIGH)  || \\\r\n                                            ((__PIN__) == PWR_WAKEUP_PIN1_LOW)   || \\\r\n                                            ((__PIN__) == PWR_WAKEUP_PIN2_LOW)   || \\\r\n                                            ((__PIN__) == PWR_WAKEUP_PIN3_LOW)   || \\\r\n                                            ((__PIN__) == PWR_WAKEUP_PIN4_LOW)   || \\\r\n                                            ((__PIN__) == PWR_WAKEUP_PIN5_LOW)\t || \\\r\n                                            ((__PIN__) == PWR_WAKEUP_PIN6_LOW))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n\r\n#endif /* __STM32F7xx_HAL_PWR_EX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_qspi.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_qspi.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of QSPI HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************  \r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_QSPI_H\r\n#define __STM32F7xx_HAL_QSPI_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup QSPI\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/ \r\n/** @defgroup QSPI_Exported_Types QSPI Exported Types\r\n  * @{\r\n  */\r\n  \r\n/** \r\n  * @brief  QSPI Init structure definition  \r\n  */\r\n\r\ntypedef struct\r\n{\r\n  uint32_t ClockPrescaler;     /* Specifies the prescaler factor for generating clock based on the AHB clock.\r\n                                  This parameter can be a number between 0 and 255 */ \r\n                                  \r\n  uint32_t FifoThreshold;      /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)\r\n                                  This parameter can be a value between 1 and 32 */\r\n                                  \r\n  uint32_t SampleShifting;     /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to \r\n                                  take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)\r\n                                  This parameter can be a value of @ref QSPI_SampleShifting */\r\n                                  \r\n  uint32_t FlashSize;          /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits \r\n                                  required to address the flash memory. The flash capacity can be up to 4GB \r\n                                  (addressed using 32 bits) in indirect mode, but the addressable space in \r\n                                  memory-mapped mode is limited to 256MB\r\n                                  This parameter can be a number between 0 and 31 */\r\n                                  \r\n  uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number \r\n                                  of clock cycles which the chip select must remain high between commands.\r\n                                  This parameter can be a value of @ref QSPI_ChipSelectHighTime */ \r\n                                    \r\n  uint32_t ClockMode;          /* Specifies the Clock Mode. It indicates the level that clock takes between commands.\r\n                                  This parameter can be a value of @ref QSPI_ClockMode */\r\n                                 \r\n  uint32_t FlashID;            /* Specifies the Flash which will be used,\r\n                                  This parameter can be a value of @ref QSPI_Flash_Select */\r\n                                 \r\n  uint32_t DualFlash;          /* Specifies the Dual Flash Mode State\r\n                                  This parameter can be a value of @ref QSPI_DualFlash_Mode */                                               \r\n}QSPI_InitTypeDef;\r\n\r\n/** \r\n  * @brief HAL QSPI State structures definition  \r\n  */ \r\ntypedef enum\r\n{\r\n  HAL_QSPI_STATE_RESET             = 0x00U,    /*!< Peripheral not initialized                            */\r\n  HAL_QSPI_STATE_READY             = 0x01U,    /*!< Peripheral initialized and ready for use              */\r\n  HAL_QSPI_STATE_BUSY              = 0x02U,    /*!< Peripheral in indirect mode and busy                  */ \r\n  HAL_QSPI_STATE_BUSY_INDIRECT_TX  = 0x12U,    /*!< Peripheral in indirect mode with transmission ongoing */ \r\n  HAL_QSPI_STATE_BUSY_INDIRECT_RX  = 0x22U,    /*!< Peripheral in indirect mode with reception ongoing    */\r\n  HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U,    /*!< Peripheral in auto polling mode ongoing               */\r\n  HAL_QSPI_STATE_BUSY_MEM_MAPPED   = 0x82U,    /*!< Peripheral in memory mapped mode ongoing              */\r\n  HAL_QSPI_STATE_ABORT             = 0x08U,    /*!< Peripheral with abort request ongoing                 */\r\n  HAL_QSPI_STATE_ERROR             = 0x04U     /*!< Peripheral in error                                   */\r\n}HAL_QSPI_StateTypeDef;\r\n\r\n/** \r\n  * @brief  QSPI Handle Structure definition  \r\n  */  \r\ntypedef struct\r\n{\r\n  QUADSPI_TypeDef            *Instance;        /* QSPI registers base address        */\r\n  QSPI_InitTypeDef           Init;             /* QSPI communication parameters      */\r\n  uint8_t                    *pTxBuffPtr;      /* Pointer to QSPI Tx transfer Buffer */\r\n  __IO uint16_t              TxXferSize;       /* QSPI Tx Transfer size              */\r\n  __IO uint16_t              TxXferCount;      /* QSPI Tx Transfer Counter           */\r\n  uint8_t                    *pRxBuffPtr;      /* Pointer to QSPI Rx transfer Buffer */\r\n  __IO uint16_t              RxXferSize;       /* QSPI Rx Transfer size              */\r\n  __IO uint16_t              RxXferCount;      /* QSPI Rx Transfer Counter           */\r\n  DMA_HandleTypeDef          *hdma;            /* QSPI Rx/Tx DMA Handle parameters   */\r\n  __IO HAL_LockTypeDef       Lock;             /* Locking object                     */\r\n  __IO HAL_QSPI_StateTypeDef State;            /* QSPI communication state           */\r\n  __IO uint32_t              ErrorCode;        /* QSPI Error code                    */\r\n  uint32_t                   Timeout;          /* Timeout for the QSPI memory access */ \r\n}QSPI_HandleTypeDef;\r\n\r\n/** \r\n  * @brief  QSPI Command structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t Instruction;        /* Specifies the Instruction to be sent\r\n                                  This parameter can be a value (8-bit) between 0x00 and 0xFF */\r\n  uint32_t Address;            /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)\r\n                                  This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */\r\n  uint32_t AlternateBytes;     /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)\r\n                                  This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */\r\n  uint32_t AddressSize;        /* Specifies the Address Size\r\n                                  This parameter can be a value of @ref QSPI_AddressSize */\r\n  uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size\r\n                                  This parameter can be a value of @ref QSPI_AlternateBytesSize */\r\n  uint32_t DummyCycles;        /* Specifies the Number of Dummy Cycles.\r\n                                  This parameter can be a number between 0 and 31 */\r\n  uint32_t InstructionMode;    /* Specifies the Instruction Mode\r\n                                  This parameter can be a value of @ref QSPI_InstructionMode */\r\n  uint32_t AddressMode;        /* Specifies the Address Mode\r\n                                  This parameter can be a value of @ref QSPI_AddressMode */\r\n  uint32_t AlternateByteMode;  /* Specifies the Alternate Bytes Mode\r\n                                  This parameter can be a value of @ref QSPI_AlternateBytesMode */\r\n  uint32_t DataMode;           /* Specifies the Data Mode (used for dummy cycles and data phases)\r\n                                  This parameter can be a value of @ref QSPI_DataMode */\r\n  uint32_t NbData;             /* Specifies the number of data to transfer. \r\n                                  This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length \r\n                                  until end of memory)*/\r\n  uint32_t DdrMode;            /* Specifies the double data rate mode for address, alternate byte and data phase\r\n                                  This parameter can be a value of @ref QSPI_DdrMode */\r\n  uint32_t DdrHoldHalfCycle;   /* Specifies the DDR hold half cycle. It delays the data output by one half of \r\n                                  system clock in DDR mode.\r\n                                  This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */\r\n  uint32_t SIOOMode;          /* Specifies the send instruction only once mode\r\n                                  This parameter can be a value of @ref QSPI_SIOOMode */\r\n}QSPI_CommandTypeDef;\r\n\r\n/** \r\n  * @brief  QSPI Auto Polling mode configuration structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t Match;              /* Specifies the value to be compared with the masked status register to get a match.\r\n                                  This parameter can be any value between 0 and 0xFFFFFFFF */\r\n  uint32_t Mask;               /* Specifies the mask to be applied to the status bytes received. \r\n                                  This parameter can be any value between 0 and 0xFFFFFFFF */\r\n  uint32_t Interval;           /* Specifies the number of clock cycles between two read during automatic polling phases.\r\n                                  This parameter can be any value between 0 and 0xFFFF */\r\n  uint32_t StatusBytesSize;    /* Specifies the size of the status bytes received.\r\n                                  This parameter can be any value between 1 and 4 */\r\n  uint32_t MatchMode;          /* Specifies the method used for determining a match.\r\n                                  This parameter can be a value of @ref QSPI_MatchMode */\r\n  uint32_t AutomaticStop;      /* Specifies if automatic polling is stopped after a match.\r\n                                  This parameter can be a value of @ref QSPI_AutomaticStop */\r\n}QSPI_AutoPollingTypeDef;\r\n                           \r\n/** \r\n  * @brief  QSPI Memory Mapped mode configuration structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t TimeOutPeriod;      /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.\r\n                                  This parameter can be any value between 0 and 0xFFFF */\r\n  uint32_t TimeOutActivation;  /* Specifies if the time out counter is enabled to release the chip select. \r\n                                  This parameter can be a value of @ref QSPI_TimeOutActivation */\r\n}QSPI_MemoryMappedTypeDef;                                     \r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup QSPI_Exported_Constants QSPI Exported Constants\r\n  * @{\r\n  */\r\n/** @defgroup QSPI_ErrorCode QSPI Error Code\r\n  * @{\r\n  */ \r\n#define HAL_QSPI_ERROR_NONE            ((uint32_t)0x00000000U) /*!< No error           */\r\n#define HAL_QSPI_ERROR_TIMEOUT         ((uint32_t)0x00000001U) /*!< Timeout error      */\r\n#define HAL_QSPI_ERROR_TRANSFER        ((uint32_t)0x00000002U) /*!< Transfer error     */\r\n#define HAL_QSPI_ERROR_DMA             ((uint32_t)0x00000004U) /*!< DMA transfer error */\r\n#define HAL_QSPI_ERROR_INVALID_PARAM   ((uint32_t)0x00000008U) /*!< Invalid parameters error */\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/** @defgroup QSPI_SampleShifting QSPI Sample Shifting\r\n  * @{\r\n  */\r\n#define QSPI_SAMPLE_SHIFTING_NONE           ((uint32_t)0x00000000U)        /*!<No clock cycle shift to sample data*/\r\n#define QSPI_SAMPLE_SHIFTING_HALFCYCLE      ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup QSPI_ChipSelectHighTime QSPI Chip Select High Time\r\n  * @{\r\n  */\r\n#define QSPI_CS_HIGH_TIME_1_CYCLE           ((uint32_t)0x00000000U)                              /*!<nCS stay high for at least 1 clock cycle between commands*/\r\n#define QSPI_CS_HIGH_TIME_2_CYCLE           ((uint32_t)QUADSPI_DCR_CSHT_0)                      /*!<nCS stay high for at least 2 clock cycles between commands*/\r\n#define QSPI_CS_HIGH_TIME_3_CYCLE           ((uint32_t)QUADSPI_DCR_CSHT_1)                      /*!<nCS stay high for at least 3 clock cycles between commands*/\r\n#define QSPI_CS_HIGH_TIME_4_CYCLE           ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/\r\n#define QSPI_CS_HIGH_TIME_5_CYCLE           ((uint32_t)QUADSPI_DCR_CSHT_2)                      /*!<nCS stay high for at least 5 clock cycles between commands*/\r\n#define QSPI_CS_HIGH_TIME_6_CYCLE           ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/\r\n#define QSPI_CS_HIGH_TIME_7_CYCLE           ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/\r\n#define QSPI_CS_HIGH_TIME_8_CYCLE           ((uint32_t)QUADSPI_DCR_CSHT)                        /*!<nCS stay high for at least 8 clock cycles between commands*/\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup QSPI_ClockMode QSPI Clock Mode\r\n  * @{\r\n  */\r\n#define QSPI_CLOCK_MODE_0                   ((uint32_t)0x00000000U)         /*!<Clk stays low while nCS is released*/\r\n#define QSPI_CLOCK_MODE_3                   ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup QSPI_Flash_Select QSPI Flash Select\r\n  * @{\r\n  */\r\n#define QSPI_FLASH_ID_1           ((uint32_t)0x00000000U)\r\n#define QSPI_FLASH_ID_2           ((uint32_t)QUADSPI_CR_FSEL)\r\n/**\r\n  * @}\r\n  */  \r\n\r\n  /** @defgroup QSPI_DualFlash_Mode  QSPI Dual Flash Mode\r\n  * @{\r\n  */\r\n#define QSPI_DUALFLASH_ENABLE            ((uint32_t)QUADSPI_CR_DFM)\r\n#define QSPI_DUALFLASH_DISABLE           ((uint32_t)0x00000000U) \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup QSPI_AddressSize QSPI Address Size \r\n  * @{\r\n  */\r\n#define QSPI_ADDRESS_8_BITS            ((uint32_t)0x00000000U)           /*!<8-bit address*/\r\n#define QSPI_ADDRESS_16_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/\r\n#define QSPI_ADDRESS_24_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/\r\n#define QSPI_ADDRESS_32_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE)   /*!<32-bit address*/\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size\r\n  * @{\r\n  */\r\n#define QSPI_ALTERNATE_BYTES_8_BITS    ((uint32_t)0x00000000U)           /*!<8-bit alternate bytes*/\r\n#define QSPI_ALTERNATE_BYTES_16_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/\r\n#define QSPI_ALTERNATE_BYTES_24_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/\r\n#define QSPI_ALTERNATE_BYTES_32_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE)   /*!<32-bit alternate bytes*/\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup QSPI_InstructionMode QSPI Instruction Mode\r\n* @{\r\n*/\r\n#define QSPI_INSTRUCTION_NONE          ((uint32_t)0x00000000U)          /*!<No instruction*/\r\n#define QSPI_INSTRUCTION_1_LINE        ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/\r\n#define QSPI_INSTRUCTION_2_LINES       ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/\r\n#define QSPI_INSTRUCTION_4_LINES       ((uint32_t)QUADSPI_CCR_IMODE)   /*!<Instruction on four lines*/\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup QSPI_AddressMode QSPI Address Mode\r\n* @{\r\n*/\r\n#define QSPI_ADDRESS_NONE              ((uint32_t)0x00000000U)           /*!<No address*/\r\n#define QSPI_ADDRESS_1_LINE            ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/\r\n#define QSPI_ADDRESS_2_LINES           ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/\r\n#define QSPI_ADDRESS_4_LINES           ((uint32_t)QUADSPI_CCR_ADMODE)   /*!<Address on four lines*/\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup QSPI_AlternateBytesMode  QSPI Alternate Bytes Mode\r\n* @{                                  \r\n*/\r\n#define QSPI_ALTERNATE_BYTES_NONE      ((uint32_t)0x00000000U)           /*!<No alternate bytes*/\r\n#define QSPI_ALTERNATE_BYTES_1_LINE    ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/\r\n#define QSPI_ALTERNATE_BYTES_2_LINES   ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/\r\n#define QSPI_ALTERNATE_BYTES_4_LINES   ((uint32_t)QUADSPI_CCR_ABMODE)   /*!<Alternate bytes on four lines*/\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup QSPI_DataMode QSPI Data Mode\r\n  * @{\r\n  */\r\n#define QSPI_DATA_NONE                 ((uint32_t)0X00000000)           /*!<No data*/\r\n#define QSPI_DATA_1_LINE               ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/\r\n#define QSPI_DATA_2_LINES              ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/\r\n#define QSPI_DATA_4_LINES              ((uint32_t)QUADSPI_CCR_DMODE)   /*!<Data on four lines*/\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup QSPI_DdrMode QSPI Ddr Mode\r\n  * @{\r\n  */\r\n#define QSPI_DDR_MODE_DISABLE              ((uint32_t)0x00000000U)       /*!<Double data rate mode disabled*/\r\n#define QSPI_DDR_MODE_ENABLE               ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup QSPI_DdrHoldHalfCycle QSPI Ddr HoldHalfCycle\r\n  * @{\r\n  */\r\n#define QSPI_DDR_HHC_ANALOG_DELAY           ((uint32_t)0x00000000U)       /*!<Delay the data output using analog delay in DDR mode*/\r\n#define QSPI_DDR_HHC_HALF_CLK_DELAY         ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup QSPI_SIOOMode QSPI SIOO Mode\r\n  * @{\r\n  */\r\n#define QSPI_SIOO_INST_EVERY_CMD       ((uint32_t)0x00000000U)       /*!<Send instruction on every transaction*/\r\n#define QSPI_SIOO_INST_ONLY_FIRST_CMD  ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup QSPI_MatchMode QSPI Match Mode\r\n  * @{\r\n  */\r\n#define QSPI_MATCH_MODE_AND                 ((uint32_t)0x00000000U)     /*!<AND match mode between unmasked bits*/\r\n#define QSPI_MATCH_MODE_OR                  ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop\r\n  * @{\r\n  */\r\n#define QSPI_AUTOMATIC_STOP_DISABLE        ((uint32_t)0x00000000U)      /*!<AutoPolling stops only with abort or QSPI disabling*/\r\n#define QSPI_AUTOMATIC_STOP_ENABLE         ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup QSPI_TimeOutActivation QSPI TimeOut Activation\r\n  * @{\r\n  */\r\n#define QSPI_TIMEOUT_COUNTER_DISABLE       ((uint32_t)0x00000000U)      /*!<Timeout counter disabled, nCS remains active*/\r\n#define QSPI_TIMEOUT_COUNTER_ENABLE        ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup QSPI_Flags  QSPI Flags\r\n  * @{\r\n  */\r\n#define QSPI_FLAG_BUSY                 QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/\r\n#define QSPI_FLAG_TO                   QUADSPI_SR_TOF  /*!<Timeout flag: timeout occurs in memory-mapped mode*/\r\n#define QSPI_FLAG_SM                   QUADSPI_SR_SMF  /*!<Status match flag: received data matches in autopolling mode*/\r\n#define QSPI_FLAG_FT                   QUADSPI_SR_FTF  /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/\r\n#define QSPI_FLAG_TC                   QUADSPI_SR_TCF  /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/\r\n#define QSPI_FLAG_TE                   QUADSPI_SR_TEF  /*!<Transfer error flag: invalid address is being accessed*/\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup QSPI_Interrupts  QSPI Interrupts\r\n  * @{\r\n  */  \r\n#define QSPI_IT_TO                          QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/\r\n#define QSPI_IT_SM                          QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/\r\n#define QSPI_IT_FT                          QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/\r\n#define QSPI_IT_TC                          QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/\r\n#define QSPI_IT_TE                          QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup QSPI_Timeout_definition QSPI Timeout definition\r\n  * @{\r\n  */ \r\n#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */\r\n/**\r\n  * @}\r\n  */  \r\n    \r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macros -----------------------------------------------------------*/\r\n/** @defgroup QSPI_Exported_Macros QSPI Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief Reset QSPI handle state\r\n  * @param  __HANDLE__: QSPI handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)\r\n\r\n/** @brief  Enable QSPI\r\n  * @param  __HANDLE__: specifies the QSPI Handle.\r\n  * @retval None\r\n  */ \r\n#define __HAL_QSPI_ENABLE(__HANDLE__)                       SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)\r\n\r\n/** @brief  Disable QSPI\r\n  * @param  __HANDLE__: specifies the QSPI Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_QSPI_DISABLE(__HANDLE__)                      CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)\r\n\r\n/** @brief  Enables the specified QSPI interrupt.\r\n  * @param  __HANDLE__: specifies the QSPI Handle.\r\n  * @param  __INTERRUPT__: specifies the QSPI interrupt source to enable.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg QSPI_IT_TO: QSPI Time out interrupt\r\n  *            @arg QSPI_IT_SM: QSPI Status match interrupt\r\n  *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt\r\n  *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt\r\n  *            @arg QSPI_IT_TE: QSPI Transfer error interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)     SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\r\n\r\n\r\n/** @brief  Disables the specified QSPI interrupt.\r\n  * @param  __HANDLE__: specifies the QSPI Handle.\r\n  * @param  __INTERRUPT__: specifies the QSPI interrupt source to disable.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg QSPI_IT_TO: QSPI Timeout interrupt\r\n  *            @arg QSPI_IT_SM: QSPI Status match interrupt\r\n  *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt\r\n  *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt\r\n  *            @arg QSPI_IT_TE: QSPI Transfer error interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)    CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\r\n\r\n/** @brief  Checks whether the specified QSPI interrupt source is enabled.\r\n  * @param  __HANDLE__: specifies the QSPI Handle.\r\n  * @param  __INTERRUPT__: specifies the QSPI interrupt source to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg QSPI_IT_TO: QSPI Time out interrupt\r\n  *            @arg QSPI_IT_SM: QSPI Status match interrupt\r\n  *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt\r\n  *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt\r\n  *            @arg QSPI_IT_TE: QSPI Transfer error interrupt\r\n  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) \r\n\r\n/**\r\n  * @brief  Get the selected QSPI's flag status.\r\n  * @param  __HANDLE__: specifies the QSPI Handle.\r\n  * @param  __FLAG__: specifies the QSPI flag to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg QSPI_FLAG_BUSY: QSPI Busy flag\r\n  *            @arg QSPI_FLAG_TO:   QSPI Time out flag\r\n  *            @arg QSPI_FLAG_SM:   QSPI Status match flag\r\n  *            @arg QSPI_FLAG_FT:   QSPI FIFO threshold flag\r\n  *            @arg QSPI_FLAG_TC:   QSPI Transfer complete flag\r\n  *            @arg QSPI_FLAG_TE:   QSPI Transfer error flag\r\n  * @retval None\r\n  */\r\n#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__)           (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0)\r\n\r\n/** @brief  Clears the specified QSPI's flag status.\r\n  * @param  __HANDLE__: specifies the QSPI Handle.\r\n  * @param  __FLAG__: specifies the QSPI clear register flag that needs to be set\r\n  *          This parameter can be one of the following values:\r\n  *            @arg QSPI_FLAG_TO: QSPI Time out flag\r\n  *            @arg QSPI_FLAG_SM: QSPI Status match flag\r\n  *            @arg QSPI_FLAG_TC: QSPI Transfer complete flag\r\n  *            @arg QSPI_FLAG_TE: QSPI Transfer error flag\r\n  * @retval None\r\n  */\r\n#define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__)         WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup QSPI_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup QSPI_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n/* Initialization/de-initialization functions  ********************************/\r\nHAL_StatusTypeDef     HAL_QSPI_Init     (QSPI_HandleTypeDef *hqspi);\r\nHAL_StatusTypeDef     HAL_QSPI_DeInit   (QSPI_HandleTypeDef *hqspi);\r\nvoid                  HAL_QSPI_MspInit  (QSPI_HandleTypeDef *hqspi);\r\nvoid                  HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup QSPI_Exported_Functions_Group2\r\n  * @{\r\n  */  \r\n/* IO operation functions *****************************************************/\r\n/* QSPI IRQ handler method */\r\nvoid                  HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);\r\n\r\n/* QSPI indirect mode */\r\nHAL_StatusTypeDef     HAL_QSPI_Command      (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);\r\nHAL_StatusTypeDef     HAL_QSPI_Transmit     (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);\r\nHAL_StatusTypeDef     HAL_QSPI_Receive      (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);\r\nHAL_StatusTypeDef     HAL_QSPI_Command_IT   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);\r\nHAL_StatusTypeDef     HAL_QSPI_Transmit_IT  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);\r\nHAL_StatusTypeDef     HAL_QSPI_Receive_IT   (QSPI_HandleTypeDef *hqspi, uint8_t *pData);\r\nHAL_StatusTypeDef     HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);\r\nHAL_StatusTypeDef     HAL_QSPI_Receive_DMA  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);\r\n\r\n/* QSPI status flag polling mode */\r\nHAL_StatusTypeDef     HAL_QSPI_AutoPolling   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);\r\nHAL_StatusTypeDef     HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);\r\n\r\n/* QSPI memory-mapped mode */\r\nHAL_StatusTypeDef     HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup QSPI_Exported_Functions_Group3\r\n  * @{\r\n  */  \r\n/* Callback functions in non-blocking modes ***********************************/\r\nvoid                  HAL_QSPI_ErrorCallback        (QSPI_HandleTypeDef *hqspi);\r\nvoid                  HAL_QSPI_AbortCpltCallback    (QSPI_HandleTypeDef *hqspi);\r\nvoid                  HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);\r\n\r\n/* QSPI indirect mode */\r\nvoid                  HAL_QSPI_CmdCpltCallback      (QSPI_HandleTypeDef *hqspi);\r\nvoid                  HAL_QSPI_RxCpltCallback       (QSPI_HandleTypeDef *hqspi);\r\nvoid                  HAL_QSPI_TxCpltCallback       (QSPI_HandleTypeDef *hqspi);\r\nvoid                  HAL_QSPI_RxHalfCpltCallback   (QSPI_HandleTypeDef *hqspi);\r\nvoid                  HAL_QSPI_TxHalfCpltCallback   (QSPI_HandleTypeDef *hqspi);\r\n\r\n/* QSPI status flag polling mode */\r\nvoid                  HAL_QSPI_StatusMatchCallback  (QSPI_HandleTypeDef *hqspi);\r\n\r\n/* QSPI memory-mapped mode */\r\nvoid                  HAL_QSPI_TimeOutCallback      (QSPI_HandleTypeDef *hqspi);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup QSPI_Exported_Functions_Group4\r\n  * @{\r\n  */  \r\n/* Peripheral Control and State functions  ************************************/\r\nHAL_QSPI_StateTypeDef HAL_QSPI_GetState        (QSPI_HandleTypeDef *hqspi);\r\nuint32_t              HAL_QSPI_GetError        (QSPI_HandleTypeDef *hqspi);\r\nHAL_StatusTypeDef     HAL_QSPI_Abort           (QSPI_HandleTypeDef *hqspi);\r\nHAL_StatusTypeDef     HAL_QSPI_Abort_IT        (QSPI_HandleTypeDef *hqspi);\r\nvoid                  HAL_QSPI_SetTimeout      (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);\r\nHAL_StatusTypeDef     HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);\r\nuint32_t              HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup QSPI_Private_Macros QSPI Private Macros\r\n  * @{\r\n  */\r\n/** @defgroup QSPI_ClockPrescaler QSPI Clock Prescaler\r\n  * @{\r\n  */ \r\n#define IS_QSPI_CLOCK_PRESCALER(PRESCALER)  ((PRESCALER) <= 0xFF)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup QSPI_FifoThreshold  QSPI Fifo Threshold \r\n  * @{\r\n  */\r\n#define IS_QSPI_FIFO_THRESHOLD(THR)         (((THR) > 0) && ((THR) <= 32))\r\n/**\r\n  * @}\r\n  */\r\n  \r\n#define IS_QSPI_SSHIFT(SSHIFT)              (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \\\r\n                                             ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE)) \r\n\r\n/** @defgroup QSPI_FlashSize QSPI Flash Size\r\n  * @{\r\n  */\r\n#define IS_QSPI_FLASH_SIZE(FSIZE)           (((FSIZE) <= 31))\r\n/**\r\n  * @}\r\n  */\r\n  \r\n#define IS_QSPI_CS_HIGH_TIME(CSHTIME)       (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \\\r\n                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \\\r\n                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \\\r\n                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \\\r\n                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \\\r\n                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \\\r\n                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \\\r\n                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))   \r\n\r\n#define IS_QSPI_CLOCK_MODE(CLKMODE)         (((CLKMODE) == QSPI_CLOCK_MODE_0) || \\\r\n                                             ((CLKMODE) == QSPI_CLOCK_MODE_3))\r\n\r\n#define IS_QSPI_FLASH_ID(FLA)    (((FLA) == QSPI_FLASH_ID_1) || \\\r\n                                  ((FLA) == QSPI_FLASH_ID_2)) \r\n                                  \r\n#define IS_QSPI_DUAL_FLASH_MODE(MODE)    (((MODE) == QSPI_DUALFLASH_ENABLE) || \\\r\n                                          ((MODE) == QSPI_DUALFLASH_DISABLE))\r\n                                          \r\n  \r\n/** @defgroup QSPI_Instruction QSPI Instruction\r\n  * @{\r\n  */\r\n#define IS_QSPI_INSTRUCTION(INSTRUCTION)    ((INSTRUCTION) <= 0xFF) \r\n/**\r\n  * @}\r\n  */ \r\n\r\n#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE)     (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS)  || \\\r\n                                             ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \\\r\n                                             ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \\\r\n                                             ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))\r\n\r\n#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE)  (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS)  || \\\r\n                                             ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \\\r\n                                             ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \\\r\n                                             ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))                                               \r\n\r\n\r\n/** @defgroup QSPI_DummyCycles QSPI Dummy Cycles\r\n  * @{\r\n  */\r\n#define IS_QSPI_DUMMY_CYCLES(DCY)           ((DCY) <= 31) \r\n/**\r\n  * @}\r\n  */\r\n\r\n#define IS_QSPI_INSTRUCTION_MODE(MODE)      (((MODE) == QSPI_INSTRUCTION_NONE)    || \\\r\n                                             ((MODE) == QSPI_INSTRUCTION_1_LINE)  || \\\r\n                                             ((MODE) == QSPI_INSTRUCTION_2_LINES) || \\\r\n                                             ((MODE) == QSPI_INSTRUCTION_4_LINES))  \r\n\r\n#define IS_QSPI_ADDRESS_MODE(MODE)          (((MODE) == QSPI_ADDRESS_NONE)    || \\\r\n                                             ((MODE) == QSPI_ADDRESS_1_LINE)  || \\\r\n                                             ((MODE) == QSPI_ADDRESS_2_LINES) || \\\r\n                                             ((MODE) == QSPI_ADDRESS_4_LINES))\r\n\r\n#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE)  (((MODE) == QSPI_ALTERNATE_BYTES_NONE)    || \\\r\n                                             ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE)  || \\\r\n                                             ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \\\r\n                                             ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))\r\n\r\n#define IS_QSPI_DATA_MODE(MODE)             (((MODE) == QSPI_DATA_NONE)    || \\\r\n                                             ((MODE) == QSPI_DATA_1_LINE)  || \\\r\n                                             ((MODE) == QSPI_DATA_2_LINES) || \\\r\n                                             ((MODE) == QSPI_DATA_4_LINES))\r\n\r\n#define IS_QSPI_DDR_MODE(DDR_MODE)          (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \\\r\n                                             ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))\r\n\r\n#define IS_QSPI_DDR_HHC(DDR_HHC)            (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \\\r\n                                             ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))\r\n\r\n#define IS_QSPI_SIOO_MODE(SIOO_MODE)      (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \\\r\n                                             ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))\r\n\r\n/** @defgroup QSPI_Interval QSPI Interval \r\n  * @{\r\n  */\r\n#define IS_QSPI_INTERVAL(INTERVAL)        ((INTERVAL) <= QUADSPI_PIR_INTERVAL) \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup QSPI_StatusBytesSize QSPI Status Bytes Size\r\n  * @{\r\n  */\r\n#define IS_QSPI_STATUS_BYTES_SIZE(SIZE)   (((SIZE) >= 1) && ((SIZE) <= 4)) \r\n/**\r\n  * @}\r\n  */\r\n#define IS_QSPI_MATCH_MODE(MODE)            (((MODE) == QSPI_MATCH_MODE_AND) || \\\r\n                                             ((MODE) == QSPI_MATCH_MODE_OR)) \r\n                                             \r\n#define IS_QSPI_AUTOMATIC_STOP(APMS)        (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \\\r\n                                             ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))                                                                                                                                                                                                                                    \r\n\r\n#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN)    (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \\\r\n                                             ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) \r\n\r\n/** @defgroup QSPI_TimeOutPeriod  QSPI TimeOut Period\r\n  * @{\r\n  */\r\n#define IS_QSPI_TIMEOUT_PERIOD(PERIOD)      ((PERIOD) <= 0xFFFF) \r\n/**\r\n  * @}\r\n  */\r\n\r\n#define IS_QSPI_GET_FLAG(FLAG)              (((FLAG) == QSPI_FLAG_BUSY) || \\\r\n                                             ((FLAG) == QSPI_FLAG_TO)   || \\\r\n                                             ((FLAG) == QSPI_FLAG_SM)   || \\\r\n                                             ((FLAG) == QSPI_FLAG_FT)   || \\\r\n                                             ((FLAG) == QSPI_FLAG_TC)   || \\\r\n                                             ((FLAG) == QSPI_FLAG_TE))    \r\n\r\n#define IS_QSPI_IT(IT)                      ((((IT) & (uint32_t)0xFFE0FFFFU) == 0x00000000U) && ((IT) != 0x00000000U))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup QSPI_Private_Functions QSPI Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_QSPI_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_rcc.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of RCC HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_RCC_H\r\n#define __STM32F7xx_HAL_RCC_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n   \r\n/* Include RCC HAL Extended module */\r\n/* (include on top of file since RCC structures are defined in extended file) */\r\n#include \"stm32f7xx_hal_rcc_ex.h\"   \r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup RCC\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/ \r\n\r\n/** @defgroup RCC_Exported_Types RCC Exported Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t OscillatorType;       /*!< The oscillators to be configured.\r\n                                      This parameter can be a value of @ref RCC_Oscillator_Type                   */\r\n\r\n  uint32_t HSEState;             /*!< The new state of the HSE.\r\n                                      This parameter can be a value of @ref RCC_HSE_Config                        */\r\n\r\n  uint32_t LSEState;             /*!< The new state of the LSE.\r\n                                      This parameter can be a value of @ref RCC_LSE_Config                        */\r\n                                          \r\n  uint32_t HSIState;             /*!< The new state of the HSI.\r\n                                      This parameter can be a value of @ref RCC_HSI_Config                        */\r\n\r\n  uint32_t HSICalibrationValue;   /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).\r\n                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */\r\n                               \r\n  uint32_t LSIState;             /*!< The new state of the LSI.\r\n                                      This parameter can be a value of @ref RCC_LSI_Config                        */\r\n\r\n  RCC_PLLInitTypeDef PLL;        /*!< PLL structure parameters                                                    */      \r\n\r\n}RCC_OscInitTypeDef;\r\n\r\n/**\r\n  * @brief  RCC System, AHB and APB busses clock configuration structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t ClockType;             /*!< The clock to be configured.\r\n                                       This parameter can be a value of @ref RCC_System_Clock_Type */\r\n  \r\n  uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.\r\n                                       This parameter can be a value of @ref RCC_System_Clock_Source    */\r\n\r\n  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).\r\n                                       This parameter can be a value of @ref RCC_AHB_Clock_Source       */\r\n\r\n  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).\r\n                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */\r\n\r\n  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).\r\n                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */\r\n\r\n}RCC_ClkInitTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup RCC_Exported_Constants RCC Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup RCC_Oscillator_Type Oscillator Type\r\n  * @{\r\n  */\r\n#define RCC_OSCILLATORTYPE_NONE            ((uint32_t)0x00000000U)\r\n#define RCC_OSCILLATORTYPE_HSE             ((uint32_t)0x00000001U)\r\n#define RCC_OSCILLATORTYPE_HSI             ((uint32_t)0x00000002U)\r\n#define RCC_OSCILLATORTYPE_LSE             ((uint32_t)0x00000004U)\r\n#define RCC_OSCILLATORTYPE_LSI             ((uint32_t)0x00000008U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_HSE_Config RCC HSE Config\r\n  * @{\r\n  */\r\n#define RCC_HSE_OFF                      ((uint32_t)0x00000000U)\r\n#define RCC_HSE_ON                       RCC_CR_HSEON\r\n#define RCC_HSE_BYPASS                   ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_LSE_Config RCC LSE Config\r\n  * @{\r\n  */\r\n#define RCC_LSE_OFF                    ((uint32_t)0x00000000U)\r\n#define RCC_LSE_ON                     RCC_BDCR_LSEON\r\n#define RCC_LSE_BYPASS                 ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_HSI_Config RCC HSI Config\r\n  * @{\r\n  */\r\n#define RCC_HSI_OFF                    ((uint32_t)0x00000000U)\r\n#define RCC_HSI_ON                     RCC_CR_HSION\r\n\r\n#define RCC_HSICALIBRATION_DEFAULT     ((uint32_t)0x10U)         /* Default HSI calibration trimming value */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_LSI_Config RCC LSI Config\r\n  * @{\r\n  */\r\n#define RCC_LSI_OFF                    ((uint32_t)0x00000000U)\r\n#define RCC_LSI_ON                     RCC_CSR_LSION\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_PLL_Config RCC PLL Config\r\n  * @{\r\n  */\r\n#define RCC_PLL_NONE                   ((uint32_t)0x00000000U)\r\n#define RCC_PLL_OFF                    ((uint32_t)0x00000001U)\r\n#define RCC_PLL_ON                     ((uint32_t)0x00000002U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider\r\n  * @{\r\n  */\r\n#define RCC_PLLP_DIV2                  ((uint32_t)0x00000002U)\r\n#define RCC_PLLP_DIV4                  ((uint32_t)0x00000004U)\r\n#define RCC_PLLP_DIV6                  ((uint32_t)0x00000006U)\r\n#define RCC_PLLP_DIV8                  ((uint32_t)0x00000008U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_PLL_Clock_Source PLL Clock Source\r\n  * @{\r\n  */\r\n#define RCC_PLLSOURCE_HSI                RCC_PLLCFGR_PLLSRC_HSI\r\n#define RCC_PLLSOURCE_HSE                RCC_PLLCFGR_PLLSRC_HSE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_System_Clock_Type RCC System Clock Type\r\n  * @{\r\n  */\r\n#define RCC_CLOCKTYPE_SYSCLK             ((uint32_t)0x00000001U)\r\n#define RCC_CLOCKTYPE_HCLK               ((uint32_t)0x00000002U)\r\n#define RCC_CLOCKTYPE_PCLK1              ((uint32_t)0x00000004U)\r\n#define RCC_CLOCKTYPE_PCLK2              ((uint32_t)0x00000008U)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup RCC_System_Clock_Source RCC System Clock Source\r\n  * @{\r\n  */\r\n#define RCC_SYSCLKSOURCE_HSI             RCC_CFGR_SW_HSI\r\n#define RCC_SYSCLKSOURCE_HSE             RCC_CFGR_SW_HSE\r\n#define RCC_SYSCLKSOURCE_PLLCLK          RCC_CFGR_SW_PLL\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status\r\n  * @{\r\n  */\r\n#define RCC_SYSCLKSOURCE_STATUS_HSI      RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */\r\n#define RCC_SYSCLKSOURCE_STATUS_HSE      RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */\r\n#define RCC_SYSCLKSOURCE_STATUS_PLLCLK   RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source\r\n  * @{\r\n  */\r\n#define RCC_SYSCLK_DIV1                  RCC_CFGR_HPRE_DIV1\r\n#define RCC_SYSCLK_DIV2                  RCC_CFGR_HPRE_DIV2\r\n#define RCC_SYSCLK_DIV4                  RCC_CFGR_HPRE_DIV4\r\n#define RCC_SYSCLK_DIV8                  RCC_CFGR_HPRE_DIV8\r\n#define RCC_SYSCLK_DIV16                 RCC_CFGR_HPRE_DIV16\r\n#define RCC_SYSCLK_DIV64                 RCC_CFGR_HPRE_DIV64\r\n#define RCC_SYSCLK_DIV128                RCC_CFGR_HPRE_DIV128\r\n#define RCC_SYSCLK_DIV256                RCC_CFGR_HPRE_DIV256\r\n#define RCC_SYSCLK_DIV512                RCC_CFGR_HPRE_DIV512\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1/APB2 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_HCLK_DIV1                    RCC_CFGR_PPRE1_DIV1\r\n#define RCC_HCLK_DIV2                    RCC_CFGR_PPRE1_DIV2\r\n#define RCC_HCLK_DIV4                    RCC_CFGR_PPRE1_DIV4\r\n#define RCC_HCLK_DIV8                    RCC_CFGR_PPRE1_DIV8\r\n#define RCC_HCLK_DIV16                   RCC_CFGR_PPRE1_DIV16\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source\r\n  * @{\r\n  */\r\n#define RCC_RTCCLKSOURCE_LSE             ((uint32_t)0x00000100U)\r\n#define RCC_RTCCLKSOURCE_LSI             ((uint32_t)0x00000200U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV2        ((uint32_t)0x00020300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV3        ((uint32_t)0x00030300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV4        ((uint32_t)0x00040300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV5        ((uint32_t)0x00050300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV6        ((uint32_t)0x00060300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV7        ((uint32_t)0x00070300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV8        ((uint32_t)0x00080300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV9        ((uint32_t)0x00090300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV10       ((uint32_t)0x000A0300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV11       ((uint32_t)0x000B0300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV12       ((uint32_t)0x000C0300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV13       ((uint32_t)0x000D0300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV14       ((uint32_t)0x000E0300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV15       ((uint32_t)0x000F0300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV16       ((uint32_t)0x00100300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV17       ((uint32_t)0x00110300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV18       ((uint32_t)0x00120300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV19       ((uint32_t)0x00130300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV20       ((uint32_t)0x00140300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV21       ((uint32_t)0x00150300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV22       ((uint32_t)0x00160300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV23       ((uint32_t)0x00170300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV24       ((uint32_t)0x00180300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV25       ((uint32_t)0x00190300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV26       ((uint32_t)0x001A0300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV27       ((uint32_t)0x001B0300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV28       ((uint32_t)0x001C0300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV29       ((uint32_t)0x001D0300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV30       ((uint32_t)0x001E0300U)\r\n#define RCC_RTCCLKSOURCE_HSE_DIV31       ((uint32_t)0x001F0300U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n\r\n/** @defgroup RCC_MCO_Index RCC MCO Index\r\n  * @{\r\n  */\r\n#define RCC_MCO1                         ((uint32_t)0x00000000U)\r\n#define RCC_MCO2                         ((uint32_t)0x00000001U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_MCO1SOURCE_HSI               ((uint32_t)0x00000000U)\r\n#define RCC_MCO1SOURCE_LSE               RCC_CFGR_MCO1_0\r\n#define RCC_MCO1SOURCE_HSE               RCC_CFGR_MCO1_1\r\n#define RCC_MCO1SOURCE_PLLCLK            RCC_CFGR_MCO1\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_MCO2SOURCE_SYSCLK            ((uint32_t)0x00000000U)\r\n#define RCC_MCO2SOURCE_PLLI2SCLK         RCC_CFGR_MCO2_0\r\n#define RCC_MCO2SOURCE_HSE               RCC_CFGR_MCO2_1\r\n#define RCC_MCO2SOURCE_PLLCLK            RCC_CFGR_MCO2\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler\r\n  * @{\r\n  */\r\n#define RCC_MCODIV_1                    ((uint32_t)0x00000000U)\r\n#define RCC_MCODIV_2                    RCC_CFGR_MCO1PRE_2\r\n#define RCC_MCODIV_3                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)\r\n#define RCC_MCODIV_4                    ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)\r\n#define RCC_MCODIV_5                    RCC_CFGR_MCO1PRE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_Interrupt RCC Interrupt \r\n  * @{\r\n  */\r\n#define RCC_IT_LSIRDY                    ((uint8_t)0x01U)\r\n#define RCC_IT_LSERDY                    ((uint8_t)0x02U)\r\n#define RCC_IT_HSIRDY                    ((uint8_t)0x04U)\r\n#define RCC_IT_HSERDY                    ((uint8_t)0x08U)\r\n#define RCC_IT_PLLRDY                    ((uint8_t)0x10U)\r\n#define RCC_IT_PLLI2SRDY                 ((uint8_t)0x20U)\r\n#define RCC_IT_PLLSAIRDY                 ((uint8_t)0x40U)\r\n#define RCC_IT_CSS                       ((uint8_t)0x80U)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup RCC_Flag RCC Flags\r\n  *        Elements values convention: 0XXYYYYYb\r\n  *           - YYYYY  : Flag position in the register\r\n  *           - 0XX  : Register index\r\n  *                 - 01: CR register\r\n  *                 - 10: BDCR register\r\n  *                 - 11: CSR register\r\n  * @{\r\n  */\r\n/* Flags in the CR register */\r\n#define RCC_FLAG_HSIRDY                  ((uint8_t)0x21U)\r\n#define RCC_FLAG_HSERDY                  ((uint8_t)0x31U)\r\n#define RCC_FLAG_PLLRDY                  ((uint8_t)0x39U)\r\n#define RCC_FLAG_PLLI2SRDY               ((uint8_t)0x3BU)\r\n#define RCC_FLAG_PLLSAIRDY               ((uint8_t)0x3CU)\r\n\r\n/* Flags in the BDCR register */\r\n#define RCC_FLAG_LSERDY                  ((uint8_t)0x41U)\r\n\r\n/* Flags in the CSR register */\r\n#define RCC_FLAG_LSIRDY                  ((uint8_t)0x61U)\r\n#define RCC_FLAG_BORRST                  ((uint8_t)0x79U)\r\n#define RCC_FLAG_PINRST                  ((uint8_t)0x7AU)\r\n#define RCC_FLAG_PORRST                  ((uint8_t)0x7BU)\r\n#define RCC_FLAG_SFTRST                  ((uint8_t)0x7CU)\r\n#define RCC_FLAG_IWDGRST                 ((uint8_t)0x7DU)\r\n#define RCC_FLAG_WWDGRST                 ((uint8_t)0x7EU)\r\n#define RCC_FLAG_LPWRRST                 ((uint8_t)0x7FU)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup RCC_LSEDrive_Configuration RCC LSE Drive configurations\r\n  * @{\r\n  */\r\n#define RCC_LSEDRIVE_LOW                 ((uint32_t)0x00000000U)\r\n#define RCC_LSEDRIVE_MEDIUMLOW           RCC_BDCR_LSEDRV_1\r\n#define RCC_LSEDRIVE_MEDIUMHIGH          RCC_BDCR_LSEDRV_0\r\n#define RCC_LSEDRIVE_HIGH                RCC_BDCR_LSEDRV\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */\r\n   \r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup RCC_Exported_Macros RCC Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable\r\n  * @brief  Enable or disable the AHB1 peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before \r\n  *         using it.   \r\n  * @{\r\n  */\r\n#define __HAL_RCC_CRC_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\t\t\t\t\t\t\t\t\t  \r\n#define __HAL_RCC_DMA1_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_CRC_CLK_DISABLE()          (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))\r\n#define __HAL_RCC_DMA1_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable\r\n  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before\r\n  *         using it.\r\n  * @{\r\n  */\r\n#define __HAL_RCC_WWDG_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\t\t\t\t\t\t\t\t\t  \r\n#define __HAL_RCC_PWR_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\t\t\t\t\t\t\t\t\t  \r\n\r\n#define __HAL_RCC_WWDG_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))\r\n#define __HAL_RCC_PWR_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable                                      \r\n  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before \r\n  *         using it.\r\n  * @{\r\n  */\r\n#define __HAL_RCC_SYSCFG_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\t\t\t\t\t\t\t\t\t  \r\n#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status\r\n  * @brief  Get the enable or disable status of the AHB1 peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before\r\n  *         using it.\r\n  * @{\r\n  */\r\n#define __HAL_RCC_CRC_IS_CLK_ENABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)  \r\n#define __HAL_RCC_DMA1_IS_CLK_ENABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) != RESET)\r\n\r\n#define __HAL_RCC_CRC_IS_CLK_DISABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)\r\n#define __HAL_RCC_DMA1_IS_CLK_DISABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) == RESET)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable  Status\r\n  * @brief  Get the enable or disable status of the APB1 peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before\r\n  *         using it.\r\n  * @{\r\n  */\r\n#define __HAL_RCC_WWDG_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)\r\n#define __HAL_RCC_PWR_IS_CLK_ENABLED()         ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)\r\n\r\n#define __HAL_RCC_WWDG_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)\r\n#define __HAL_RCC_PWR_IS_CLK_DISABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status\r\n  * @brief  EGet the enable or disable status of the APB2 peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before\r\n  *         using it.\r\n  * @{\r\n  */\r\n#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)\r\n#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)\r\n/**\r\n  * @}\r\n  */  \r\n  \r\n/** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release\r\n  * @brief  Force or release AHB peripheral reset.\r\n  * @{\r\n  */  \r\n#define __HAL_RCC_AHB1_FORCE_RESET()    (RCC->AHB1RSTR = 0xFFFFFFFFU)\r\n#define __HAL_RCC_CRC_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))\r\n#define __HAL_RCC_DMA1_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))\r\n\r\n#define __HAL_RCC_AHB1_RELEASE_RESET()  (RCC->AHB1RSTR = 0x00U)\r\n#define __HAL_RCC_CRC_RELEASE_RESET()   (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))\r\n#define __HAL_RCC_DMA1_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset \r\n  * @brief  Force or release APB1 peripheral reset.\r\n  * @{\r\n  */\r\n#define __HAL_RCC_APB1_FORCE_RESET()     (RCC->APB1RSTR = 0xFFFFFFFFU)  \r\n#define __HAL_RCC_WWDG_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))\r\n#define __HAL_RCC_PWR_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))\r\n\r\n#define __HAL_RCC_APB1_RELEASE_RESET()   (RCC->APB1RSTR = 0x00U) \r\n#define __HAL_RCC_WWDG_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))\r\n#define __HAL_RCC_PWR_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset \r\n  * @brief  Force or release APB2 peripheral reset.\r\n  * @{\r\n  */\r\n#define __HAL_RCC_APB2_FORCE_RESET()     (RCC->APB2RSTR = 0xFFFFFFFFU)  \r\n#define __HAL_RCC_SYSCFG_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))\r\n\r\n#define __HAL_RCC_APB2_RELEASE_RESET()   (RCC->APB2RSTR = 0x00U)\r\n#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable\r\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r\n  *         power consumption.\r\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r\n  * @{\r\n  */\r\n#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))\r\n#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))\r\n\r\n#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))\r\n#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))\r\n\r\n/** @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.\r\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r\n  *         power consumption.\r\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r\n  */\r\n#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))\r\n#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))\r\n\r\n#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))\r\n#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))\r\n\r\n/** @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.\r\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r\n  *         power consumption.\r\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r\n  */\r\n#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))\r\n#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enable Disable Status\r\n  * @brief  Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.\r\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r\n  *         power consumption.\r\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r\n  * @{\r\n  */\r\n#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != RESET)\r\n#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != RESET)\r\n\r\n#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == RESET)\r\n#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED()   ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == RESET)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status\r\n  * @brief  Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.\r\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r\n  *         power consumption.\r\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r\n  * @{\r\n  */\r\n#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED()      ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET)\r\n#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET)\r\n\r\n#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED()     ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET)\r\n#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED()      ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status\r\n  * @brief  Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.\r\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r\n  *         power consumption.\r\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r\n  * @{\r\n  */\r\n#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET)\r\n#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET)\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup RCC_HSI_Configuration HSI Configuration\r\n  * @{   \r\n  */ \r\n                                      \r\n/** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).\r\n  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.\r\n  *         It is used (enabled by hardware) as system clock source after startup\r\n  *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure\r\n  *         of the HSE used directly or indirectly as system clock (if the Clock\r\n  *         Security System CSS is enabled).             \r\n  * @note   HSI can not be stopped if it is used as system clock source. In this case,\r\n  *         you have to select another source of the system clock then stop the HSI.  \r\n  * @note   After enabling the HSI, the application software should wait on HSIRDY\r\n  *         flag to be set indicating that HSI clock is stable and can be used as\r\n  *         system clock source.  \r\n  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator\r\n  *         clock cycles.  \r\n  */\r\n#define __HAL_RCC_HSI_ENABLE() (RCC->CR |= (RCC_CR_HSION))\r\n#define __HAL_RCC_HSI_DISABLE() (RCC->CR &= ~(RCC_CR_HSION))\r\n\r\n/** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.\r\n  * @note   The calibration is used to compensate for the variations in voltage\r\n  *         and temperature that influence the frequency of the internal HSI RC.\r\n  * @param  __HSICALIBRATIONVALUE__: specifies the calibration trimming value.\r\n  *         (default is RCC_HSICALIBRATION_DEFAULT).\r\n  */\r\n#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) (MODIFY_REG(RCC->CR,\\\r\n        RCC_CR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_CR_HSITRIM)))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_LSI_Configuration LSI Configuration\r\n  * @{   \r\n  */ \r\n\r\n/** @brief  Macros to enable or disable the Internal Low Speed oscillator (LSI).\r\n  * @note   After enabling the LSI, the application software should wait on \r\n  *         LSIRDY flag to be set indicating that LSI clock is stable and can\r\n  *         be used to clock the IWDG and/or the RTC.\r\n  * @note   LSI can not be disabled if the IWDG is running.\r\n  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator\r\n  *         clock cycles. \r\n  */\r\n#define __HAL_RCC_LSI_ENABLE()  (RCC->CSR |= (RCC_CSR_LSION))\r\n#define __HAL_RCC_LSI_DISABLE() (RCC->CSR &= ~(RCC_CSR_LSION))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_HSE_Configuration HSE Configuration\r\n  * @{   \r\n  */ \r\n/**\r\n  * @brief  Macro to configure the External High Speed oscillator (HSE).\r\n  * @note   Transitions HSE Bypass to HSE On and HSE On to HSE Bypass are not\r\n  *         supported by this macro. User should request a transition to HSE Off\r\n  *         first and then HSE On or HSE Bypass.\r\n  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application\r\n  *         software should wait on HSERDY flag to be set indicating that HSE clock\r\n  *         is stable and can be used to clock the PLL and/or system clock.\r\n  * @note   HSE state can not be changed if it is used directly or through the\r\n  *         PLL as system clock. In this case, you have to select another source\r\n  *         of the system clock then change the HSE state (ex. disable it).\r\n  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.\r\n  * @note   This function reset the CSSON bit, so if the clock security system(CSS)\r\n  *         was previously enabled you have to enable it again after calling this\r\n  *         function.\r\n  * @param  __STATE__: specifies the new state of the HSE.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after\r\n  *                              6 HSE oscillator clock cycles.\r\n  *            @arg RCC_HSE_ON: turn ON the HSE oscillator.\r\n  *            @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.\r\n  */\r\n#define __HAL_RCC_HSE_CONFIG(__STATE__)                         \\\r\n                    do {                                        \\\r\n                      if ((__STATE__) == RCC_HSE_ON)            \\\r\n                      {                                         \\\r\n                        SET_BIT(RCC->CR, RCC_CR_HSEON);         \\\r\n                      }                                         \\\r\n                      else if ((__STATE__) == RCC_HSE_OFF)      \\\r\n                      {                                         \\\r\n                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);       \\\r\n                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);      \\\r\n                      }                                         \\\r\n                      else if ((__STATE__) == RCC_HSE_BYPASS)   \\\r\n                      {                                         \\\r\n                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);        \\\r\n                        SET_BIT(RCC->CR, RCC_CR_HSEON);         \\\r\n                      }                                         \\\r\n                      else                                      \\\r\n                      {                                         \\\r\n                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);       \\\r\n                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);      \\\r\n                      }                                         \\\r\n                    } while(0)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_LSE_Configuration LSE Configuration\r\n  * @{   \r\n  */\r\n\r\n/**\r\n  * @brief  Macro to configure the External Low Speed oscillator (LSE).\r\n  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. \r\n  *         User should request a transition to LSE Off first and then LSE On or LSE Bypass.  \r\n  * @note   As the LSE is in the Backup domain and write access is denied to\r\n  *         this domain after reset, you have to enable write access using \r\n  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE\r\n  *         (to be done once after reset).  \r\n  * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application\r\n  *         software should wait on LSERDY flag to be set indicating that LSE clock\r\n  *         is stable and can be used to clock the RTC.\r\n  * @param  __STATE__: specifies the new state of the LSE.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after\r\n  *                              6 LSE oscillator clock cycles.\r\n  *            @arg RCC_LSE_ON: turn ON the LSE oscillator.\r\n  *            @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.\r\n  */\r\n#define __HAL_RCC_LSE_CONFIG(__STATE__) \\\r\n                    do {                                       \\\r\n                      if((__STATE__) == RCC_LSE_ON)            \\\r\n                      {                                        \\\r\n                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \\\r\n                      }                                        \\\r\n                      else if((__STATE__) == RCC_LSE_OFF)      \\\r\n                      {                                        \\\r\n                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \\\r\n                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \\\r\n                      }                                        \\\r\n                      else if((__STATE__) == RCC_LSE_BYPASS)   \\\r\n                      {                                        \\\r\n                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);   \\\r\n                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \\\r\n                      }                                        \\\r\n                      else                                     \\\r\n                      {                                        \\\r\n                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \\\r\n                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \\\r\n                      }                                        \\\r\n                    } while(0)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration\r\n  * @{   \r\n  */\r\n\r\n/** @brief  Macros to enable or disable the RTC clock.\r\n  * @note   These macros must be used only after the RTC clock source was selected.\r\n  */\r\n#define __HAL_RCC_RTC_ENABLE()  (RCC->BDCR |= (RCC_BDCR_RTCEN))\r\n#define __HAL_RCC_RTC_DISABLE() (RCC->BDCR &= ~(RCC_BDCR_RTCEN))\r\n\r\n/** @brief  Macros to configure the RTC clock (RTCCLK).\r\n  * @note   As the RTC clock configuration bits are in the Backup domain and write\r\n  *         access is denied to this domain after reset, you have to enable write\r\n  *         access using the Power Backup Access macro before to configure\r\n  *         the RTC clock source (to be done once after reset).    \r\n  * @note   Once the RTC clock is configured it can't be changed unless the  \r\n  *         Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by\r\n  *         a Power On Reset (POR).\r\n  * @param  __RTCCLKSource__: specifies the RTC clock source.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.\r\n  *            @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.\r\n  *            @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected\r\n  *                                            as RTC clock, where x:[2,31]\r\n  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to\r\n  *         work in STOP and STANDBY modes, and can be used as wakeup source.\r\n  *         However, when the HSE clock is used as RTC clock source, the RTC\r\n  *         cannot be used in STOP and STANDBY modes.    \r\n  * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as\r\n  *         RTC clock source).\r\n  */\r\n#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ?    \\\r\n                                                 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)\r\n                                                   \r\n#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__);    \\\r\n                                                    RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF);  \\\r\n                                                   } while (0)\r\n\r\n/** @brief  Macros to force or release the Backup domain reset.\r\n  * @note   This function resets the RTC peripheral (including the backup registers)\r\n  *         and the RTC clock source selection in RCC_CSR register.\r\n  * @note   The BKPSRAM is not affected by this reset.   \r\n  */\r\n#define __HAL_RCC_BACKUPRESET_FORCE()   (RCC->BDCR |= (RCC_BDCR_BDRST))\r\n#define __HAL_RCC_BACKUPRESET_RELEASE() (RCC->BDCR &= ~(RCC_BDCR_BDRST))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_PLL_Configuration PLL Configuration\r\n  * @{   \r\n  */\r\n\r\n/** @brief  Macros to enable or disable the main PLL.\r\n  * @note   After enabling the main PLL, the application software should wait on \r\n  *         PLLRDY flag to be set indicating that PLL clock is stable and can\r\n  *         be used as system clock source.\r\n  * @note   The main PLL can not be disabled if it is used as system clock source\r\n  * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.\r\n  */\r\n#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)\r\n#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)\r\n                            \r\n/** @brief  Macro to configure the PLL clock source.\r\n  * @note   This function must be used only when the main PLL is disabled.\r\n  * @param  __PLLSOURCE__: specifies the PLL entry clock source.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry\r\n  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry\r\n  *      \r\n  */\r\n#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))\r\n\r\n/** @brief  Macro to configure the PLL multiplication factor.\r\n  * @note   This function must be used only when the main PLL is disabled.\r\n  * @param  __PLLM__: specifies the division factor for PLL VCO input clock\r\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.\r\n  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input\r\n  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency\r\n  *         of 2 MHz to limit PLL jitter.\r\n  *      \r\n  */\r\n#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration\r\n  * @{   \r\n  */\r\n\r\n/** @brief  Macro to configure the I2S clock source (I2SCLK).\r\n  * @note   This function must be called before enabling the I2S APB clock.\r\n  * @param  __SOURCE__: specifies the I2S clock source.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.\r\n  *            @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin\r\n  *                                       used as I2S clock source.\r\n  */\r\n#define __HAL_RCC_I2S_CONFIG(__SOURCE__) do {RCC->CFGR &= ~(RCC_CFGR_I2SSRC); \\\r\n                                             RCC->CFGR |= (__SOURCE__);       \\\r\n                                            }while(0)\r\n\r\n/** @brief Macros to enable or disable the PLLI2S. \r\n  * @note  The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.\r\n  */\r\n#define __HAL_RCC_PLLI2S_ENABLE() (RCC->CR |= (RCC_CR_PLLI2SON))\r\n#define __HAL_RCC_PLLI2S_DISABLE() (RCC->CR &= ~(RCC_CR_PLLI2SON))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_Get_Clock_source Get Clock source\r\n  * @{   \r\n  */\r\n/**\r\n  * @brief Macro to configure the system clock source.\r\n  * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.\r\n  * This parameter can be one of the following values:\r\n  *              - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.\r\n  *              - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.\r\n  *              - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.\r\n  */\r\n#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))\r\n\r\n/** @brief  Macro to get the clock source used as system clock.\r\n  * @retval The clock source used as system clock. The returned value can be one\r\n  *         of the following:\r\n  *              - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.\r\n  *              - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.\r\n  *              - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.\r\n  */     \r\n#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))\r\n\r\n/**\r\n  * @brief  Macro to configures the External Low Speed oscillator (LSE) drive capability.\r\n  * @note   As the LSE is in the Backup domain and write access is denied to\r\n  *         this domain after reset, you have to enable write access using\r\n  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE\r\n  *         (to be done once after reset).\r\n  * @param  __RCC_LSEDRIVE__: specifies the new state of the LSE drive capability.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.\r\n  *            @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.\r\n  *            @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.\r\n  *            @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.\r\n  * @retval None\r\n  */\r\n#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) \\\r\n                  (MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))\r\n\r\n/** @brief  Macro to get the oscillator used as PLL clock source.\r\n  * @retval The oscillator used as PLL clock source. The returned value can be one\r\n  *         of the following:\r\n  *              - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.\r\n  *              - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.\r\n  */\r\n#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config\r\n  * @{   \r\n  */ \r\n  \r\n/** @brief  Macro to configure the MCO1 clock.\r\n  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source\r\n  *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source\r\n  *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source\r\n  *            @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source\r\n  * @param  __MCODIV__ specifies the MCO clock prescaler.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_MCODIV_1: no division applied to MCOx clock\r\n  *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock\r\n  *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock\r\n  *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock\r\n  *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock\r\n  */\r\n\r\n#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \\\r\n        MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))\r\n                \r\n/** @brief  Macro to configure the MCO2 clock.\r\n  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source\r\n  *            @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source \r\n  *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source\r\n  *            @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source\r\n  * @param  __MCODIV__ specifies the MCO clock prescaler.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_MCODIV_1: no division applied to MCOx clock\r\n  *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock\r\n  *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock\r\n  *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock\r\n  *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock\r\n  */\r\n\r\n#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \\\r\n        MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3)));\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management\r\n  * @brief macros to manage the specified RCC Flags and interrupts.\r\n  * @{\r\n  */\r\n\r\n/** @brief  Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable\r\n  *         the selected interrupts).\r\n  * @param  __INTERRUPT__: specifies the RCC interrupt sources to be enabled.\r\n  *         This parameter can be any combination of the following values:\r\n  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.\r\n  *            @arg RCC_IT_LSERDY: LSE ready interrupt.\r\n  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.\r\n  *            @arg RCC_IT_HSERDY: HSE ready interrupt.\r\n  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.\r\n  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.\r\n  */\r\n#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))\r\n\r\n/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable \r\n  *        the selected interrupts).\r\n  * @param  __INTERRUPT__: specifies the RCC interrupt sources to be disabled.\r\n  *         This parameter can be any combination of the following values:\r\n  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.\r\n  *            @arg RCC_IT_LSERDY: LSE ready interrupt.\r\n  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.\r\n  *            @arg RCC_IT_HSERDY: HSE ready interrupt.\r\n  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.\r\n  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.\r\n  */\r\n#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))\r\n\r\n/** @brief  Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]\r\n  *         bits to clear the selected interrupt pending bits.\r\n  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.\r\n  *         This parameter can be any combination of the following values:\r\n  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.\r\n  *            @arg RCC_IT_LSERDY: LSE ready interrupt.\r\n  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.\r\n  *            @arg RCC_IT_HSERDY: HSE ready interrupt.\r\n  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.\r\n  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.  \r\n  *            @arg RCC_IT_CSS: Clock Security System interrupt\r\n  */\r\n#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))\r\n\r\n/** @brief  Check the RCC's interrupt has occurred or not.\r\n  * @param  __INTERRUPT__: specifies the RCC interrupt source to check.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.\r\n  *            @arg RCC_IT_LSERDY: LSE ready interrupt.\r\n  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.\r\n  *            @arg RCC_IT_HSERDY: HSE ready interrupt.\r\n  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.\r\n  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.\r\n  *            @arg RCC_IT_CSS: Clock Security System interrupt\r\n  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))\r\n\r\n/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, \r\n  *        RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.\r\n  */\r\n#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)\r\n\r\n/** @brief  Check RCC flag is set or not.\r\n  * @param  __FLAG__: specifies the flag to check.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.\r\n  *            @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.\r\n  *            @arg RCC_FLAG_PLLRDY: Main PLL clock ready.\r\n  *            @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.\r\n  *            @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.\r\n  *            @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.\r\n  *            @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.\r\n  *            @arg RCC_FLAG_PINRST: Pin reset.\r\n  *            @arg RCC_FLAG_PORRST: POR/PDR reset.\r\n  *            @arg RCC_FLAG_SFTRST: Software reset.\r\n  *            @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.\r\n  *            @arg RCC_FLAG_WWDGRST: Window Watchdog reset.\r\n  *            @arg RCC_FLAG_LPWRRST: Low Power reset.\r\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\r\n  */\r\n#define RCC_FLAG_MASK  ((uint8_t)0x1F)\r\n#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)\r\n\r\n/**\r\n  * @}\r\n  */\r\n     \r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Include RCC HAL Extension module */\r\n#include \"stm32f7xx_hal_rcc_ex.h\"\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n /** @addtogroup RCC_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup RCC_Exported_Functions_Group1\r\n  * @{\r\n  */                             \r\n/* Initialization and de-initialization functions  ******************************/\r\nvoid HAL_RCC_DeInit(void);\r\nHAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);\r\nHAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup RCC_Exported_Functions_Group2\r\n  * @{\r\n  */\r\n/* Peripheral Control functions  ************************************************/\r\nvoid     HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);\r\nvoid     HAL_RCC_EnableCSS(void);\r\nvoid     HAL_RCC_DisableCSS(void);\r\nuint32_t HAL_RCC_GetSysClockFreq(void);\r\nuint32_t HAL_RCC_GetHCLKFreq(void);\r\nuint32_t HAL_RCC_GetPCLK1Freq(void);\r\nuint32_t HAL_RCC_GetPCLK2Freq(void);\r\nvoid     HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);\r\nvoid     HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);\r\n\r\n/* CSS NMI IRQ handler */\r\nvoid HAL_RCC_NMI_IRQHandler(void);\r\n\r\n/* User Callbacks in non blocking mode (IT mode) */ \r\nvoid HAL_RCC_CSSCallback(void);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup RCC_Private_Constants RCC Private Constants\r\n  * @{\r\n  */\r\n#define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT\r\n#define HSI_TIMEOUT_VALUE          ((uint32_t)2)  /* 2 ms */\r\n#define LSI_TIMEOUT_VALUE          ((uint32_t)2)  /* 2 ms */\r\n#define PLL_TIMEOUT_VALUE          ((uint32_t)2)  /* 2 ms */\r\n#define CLOCKSWITCH_TIMEOUT_VALUE  ((uint32_t)5000) /* 5 s    */ \r\n\r\n/** @defgroup RCC_BitAddress_Alias RCC BitAddress Alias\r\n  * @brief RCC registers bit address alias\r\n  * @{\r\n  */\r\n/* CIR register byte 2 (Bits[15:8]) base address */\r\n#define RCC_CIR_BYTE1_ADDRESS         ((uint32_t)(RCC_BASE + 0x0C + 0x01))\r\n\r\n/* CIR register byte 3 (Bits[23:16]) base address */\r\n#define RCC_CIR_BYTE2_ADDRESS         ((uint32_t)(RCC_BASE + 0x0C + 0x02))\r\n\r\n#define RCC_DBP_TIMEOUT_VALUE      ((uint32_t)100)\r\n#define RCC_LSE_TIMEOUT_VALUE      LSE_STARTUP_TIMEOUT\r\n/**\r\n  * @}\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @addtogroup RCC_Private_Macros RCC Private Macros\r\n  * @{\r\n  */\r\n    \r\n/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters\r\n  * @{\r\n  */  \r\n#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)\r\n\r\n#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \\\r\n                         ((HSE) == RCC_HSE_BYPASS))\r\n\r\n#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \\\r\n                         ((LSE) == RCC_LSE_BYPASS))\r\n\r\n#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))\r\n\r\n#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))\r\n\r\n#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))\r\n\r\n#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \\\r\n                                  ((SOURCE) == RCC_PLLSOURCE_HSE))\r\n\r\n#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \\\r\n                                     ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \\\r\n                                     ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))\r\n#define IS_RCC_PLLM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63))\r\n\r\n#define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))\r\n\r\n#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == RCC_PLLP_DIV2) || ((VALUE) == RCC_PLLP_DIV4) || \\\r\n                                  ((VALUE) == RCC_PLLP_DIV6) || ((VALUE) == RCC_PLLP_DIV8))\r\n#define IS_RCC_PLLQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))\r\n\r\n#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1)   || ((HCLK) == RCC_SYSCLK_DIV2)   || \\\r\n                           ((HCLK) == RCC_SYSCLK_DIV4)   || ((HCLK) == RCC_SYSCLK_DIV8)   || \\\r\n                           ((HCLK) == RCC_SYSCLK_DIV16)  || ((HCLK) == RCC_SYSCLK_DIV64)  || \\\r\n                           ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \\\r\n                           ((HCLK) == RCC_SYSCLK_DIV512))\r\n\r\n#define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))\r\n\r\n#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \\\r\n                           ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \\\r\n                           ((PCLK) == RCC_HCLK_DIV16))\r\n\r\n#define IS_RCC_MCO(MCOX) (((MCOX) == RCC_MCO1) || ((MCOX) == RCC_MCO2))\r\n\r\n\r\n#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \\\r\n                                   ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))\r\n\r\n#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \\\r\n                                   ((SOURCE) == RCC_MCO2SOURCE_HSE)    || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))\r\n\r\n#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1)  || ((DIV) == RCC_MCODIV_2) || \\\r\n                             ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \\\r\n                             ((DIV) == RCC_MCODIV_5)) \r\n#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)\r\n\r\n#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \\\r\n                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \\\r\n                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \\\r\n                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \\\r\n                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \\\r\n                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \\\r\n                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \\\r\n                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \\\r\n                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \\\r\n                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \\\r\n                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \\\r\n                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \\\r\n                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \\\r\n                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \\\r\n                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \\\r\n                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31))\r\n\r\n\r\n#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDRIVE_LOW)        || \\\r\n                                 ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW)  || \\\r\n                                 ((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) || \\\r\n                                 ((DRIVE) == RCC_LSEDRIVE_HIGH))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_RCC_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_rcc_ex.h\r\n  * @author  MCD Application Team                                                                                                     \r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of RCC HAL Extension module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_RCC_EX_H\r\n#define __STM32F7xx_HAL_RCC_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup RCCEx\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup RCCEx_Exported_Types RCCEx Exported Types\r\n  * @{\r\n  */\r\n   \r\n/** \r\n  * @brief  RCC PLL configuration structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t PLLState;   /*!< The new state of the PLL.\r\n                            This parameter can be a value of @ref RCC_PLL_Config                      */\r\n\r\n  uint32_t PLLSource;  /*!< RCC_PLLSource: PLL entry clock source.\r\n                            This parameter must be a value of @ref RCC_PLL_Clock_Source               */           \r\n\r\n  uint32_t PLLM;       /*!< PLLM: Division factor for PLL VCO input clock.\r\n                            This parameter must be a number between Min_Data = 2 and Max_Data = 63    */        \r\n\r\n  uint32_t PLLN;       /*!< PLLN: Multiplication factor for PLL VCO output clock.\r\n                            This parameter must be a number between Min_Data = 50 and Max_Data = 432  */\r\n\r\n  uint32_t PLLP;       /*!< PLLP: Division factor for main system clock (SYSCLK).\r\n                            This parameter must be a value of @ref RCC_PLLP_Clock_Divider             */\r\n\r\n  uint32_t PLLQ;       /*!< PLLQ: Division factor for OTG FS, SDMMC and RNG clocks.\r\n                            This parameter must be a number between Min_Data = 2 and Max_Data = 15    */\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n  uint32_t PLLR;       /*!< PLLR: Division factor for DSI clock.\r\n                            This parameter must be a number between Min_Data = 2 and Max_Data = 7    */\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */  \r\n\r\n}RCC_PLLInitTypeDef;   \r\n\r\n/** \r\n  * @brief  PLLI2S Clock structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t PLLI2SN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.\r\n                            This parameter must be a number between Min_Data = 50 and Max_Data = 432.\r\n                            This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */\r\n\r\n  uint32_t PLLI2SR;    /*!< Specifies the division factor for I2S clock.\r\n                            This parameter must be a number between Min_Data = 2 and Max_Data = 7. \r\n                            This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */\r\n\r\n  uint32_t PLLI2SQ;    /*!< Specifies the division factor for SAI1 clock.\r\n                            This parameter must be a number between Min_Data = 2 and Max_Data = 15. \r\n                            This parameter will be used only when PLLI2S is selected as Clock Source SAI */\r\n\r\n  uint32_t PLLI2SP;    /*!< Specifies the division factor for SPDIF-RX clock.\r\n                            This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider. \r\n                            This parameter will be used only when PLLI2S is selected as Clock Source SPDIF-RX */\r\n}RCC_PLLI2SInitTypeDef;\r\n\r\n/** \r\n  * @brief  PLLSAI Clock structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t PLLSAIN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.\r\n                            This parameter must be a number between Min_Data = 50 and Max_Data = 432.\r\n                            This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ \r\n                                 \r\n  uint32_t PLLSAIQ;    /*!< Specifies the division factor for SAI1 clock.\r\n                            This parameter must be a number between Min_Data = 2 and Max_Data = 15.\r\n                            This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */\r\n                              \r\n  uint32_t PLLSAIR;    /*!< specifies the division factor for LTDC clock\r\n                            This parameter must be a number between Min_Data = 2 and Max_Data = 7.\r\n                            This parameter will be used only when PLLSAI is selected as Clock Source LTDC */\r\n\r\n  uint32_t PLLSAIP;    /*!< Specifies the division factor for 48MHz clock.\r\n                            This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider\r\n                            This parameter will be used only when PLLSAI is disabled */\r\n}RCC_PLLSAIInitTypeDef;\r\n\r\n/** \r\n  * @brief  RCC extended clocks structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.\r\n                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */\r\n\r\n  RCC_PLLI2SInitTypeDef PLLI2S;  /*!< PLL I2S structure parameters. \r\n                                      This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */\r\n\r\n  RCC_PLLSAIInitTypeDef PLLSAI;  /*!< PLL SAI structure parameters. \r\n                                      This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */\r\n\r\n  uint32_t PLLI2SDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.\r\n                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32\r\n                                      This parameter will be used only when PLLI2S is selected as Clock Source SAI */\r\n\r\n  uint32_t PLLSAIDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.\r\n                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32\r\n                                      This parameter will be used only when PLLSAI is selected as Clock Source SAI */\r\n\r\n  uint32_t PLLSAIDivR;           /*!< Specifies the PLLSAI division factor for LTDC clock.\r\n                                      This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */\r\n\r\n  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock source Selection. \r\n                                        This parameter can be a value of @ref RCC_RTC_Clock_Source */\r\n                                        \r\n  uint32_t I2sClockSelection;      /*!< Specifies I2S Clock source Selection. \r\n                                        This parameter can be a value of @ref RCCEx_I2S_Clock_Source */\r\n\r\n  uint32_t TIMPresSelection;      /*!< Specifies TIM Clock Prescalers Selection. \r\n                                       This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */\r\n  \r\n  uint32_t Sai1ClockSelection;     /*!< Specifies SAI1 Clock Prescalers Selection\r\n                                        This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */\r\n\r\n  uint32_t Sai2ClockSelection;     /*!< Specifies SAI2 Clock Prescalers Selection\r\n                                        This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */\r\n  \r\n  uint32_t Usart1ClockSelection; /*!< USART1 clock source      \r\n                                      This parameter can be a value of @ref RCCEx_USART1_Clock_Source */\r\n  \r\n  uint32_t Usart2ClockSelection; /*!< USART2 clock source      \r\n                                      This parameter can be a value of @ref RCCEx_USART2_Clock_Source */\r\n\r\n  uint32_t Usart3ClockSelection; /*!< USART3 clock source      \r\n                                      This parameter can be a value of @ref RCCEx_USART3_Clock_Source */                                \r\n  \r\n  uint32_t Uart4ClockSelection;  /*!< UART4 clock source      \r\n                                      This parameter can be a value of @ref RCCEx_UART4_Clock_Source */\r\n  \r\n  uint32_t Uart5ClockSelection;  /*!< UART5 clock source      \r\n                                      This parameter can be a value of @ref RCCEx_UART5_Clock_Source */\r\n  \r\n  uint32_t Usart6ClockSelection;  /*!< USART6 clock source      \r\n                                      This parameter can be a value of @ref RCCEx_USART6_Clock_Source */\r\n  \r\n  uint32_t Uart7ClockSelection;  /*!< UART7 clock source      \r\n                                      This parameter can be a value of @ref RCCEx_UART7_Clock_Source */\r\n  \r\n  uint32_t Uart8ClockSelection;  /*!< UART8 clock source      \r\n                                      This parameter can be a value of @ref RCCEx_UART8_Clock_Source */\r\n  \r\n  uint32_t I2c1ClockSelection;   /*!< I2C1 clock source      \r\n                                      This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */\r\n\r\n  uint32_t I2c2ClockSelection;   /*!< I2C2 clock source      \r\n                                      This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */\r\n\r\n  uint32_t I2c3ClockSelection;   /*!< I2C3 clock source      \r\n                                      This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */\r\n  \r\n  uint32_t I2c4ClockSelection;   /*!< I2C4 clock source      \r\n                                      This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */\r\n  \r\n  uint32_t Lptim1ClockSelection;   /*!< Specifies LPTIM1 clock source\r\n                                        This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */\r\n  \r\n  uint32_t CecClockSelection;      /*!< CEC clock source      \r\n                                        This parameter can be a value of @ref RCCEx_CEC_Clock_Source */\r\n  \r\n  uint32_t Clk48ClockSelection;    /*!< Specifies 48Mhz clock source used by USB OTG FS, RNG and SDMMC\r\n                                        This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */\r\n  \r\n  uint32_t Sdmmc1ClockSelection;     /*!< SDMMC1 clock source      \r\n                                        This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */\r\n                                          \r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)  \r\n  uint32_t Sdmmc2ClockSelection;     /*!< SDMMC2 clock source      \r\n                                        This parameter can be a value of @ref RCCEx_SDMMC2_Clock_Source */\r\n  \r\n  uint32_t Dfsdm1ClockSelection;     /*!< DFSDM1 clock source      \r\n                                        This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */\r\n                                          \r\n  uint32_t Dfsdm1AudioClockSelection; /*!< DFSDM1 clock source      \r\n                                        This parameter can be a value of @ref RCCEx_DFSDM1_AUDIO_Clock_Source */\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */  \r\n}RCC_PeriphCLKInitTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection\r\n  * @{\r\n  */\r\n#define RCC_PERIPHCLK_I2S             ((uint32_t)0x00000001U)\r\n#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define RCC_PERIPHCLK_LTDC            ((uint32_t)0x00000008U)\r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n#define RCC_PERIPHCLK_TIM             ((uint32_t)0x00000010U)\r\n#define RCC_PERIPHCLK_RTC             ((uint32_t)0x00000020U)\r\n#define RCC_PERIPHCLK_USART1          ((uint32_t)0x00000040U)\r\n#define RCC_PERIPHCLK_USART2          ((uint32_t)0x00000080U)\r\n#define RCC_PERIPHCLK_USART3          ((uint32_t)0x00000100U)\r\n#define RCC_PERIPHCLK_UART4           ((uint32_t)0x00000200U)\r\n#define RCC_PERIPHCLK_UART5           ((uint32_t)0x00000400U)\r\n#define RCC_PERIPHCLK_USART6          ((uint32_t)0x00000800U)\r\n#define RCC_PERIPHCLK_UART7           ((uint32_t)0x00001000U)\r\n#define RCC_PERIPHCLK_UART8           ((uint32_t)0x00002000U)\r\n#define RCC_PERIPHCLK_I2C1            ((uint32_t)0x00004000U)\r\n#define RCC_PERIPHCLK_I2C2            ((uint32_t)0x00008000U)\r\n#define RCC_PERIPHCLK_I2C3            ((uint32_t)0x00010000U)\r\n#define RCC_PERIPHCLK_I2C4            ((uint32_t)0x00020000U)\r\n#define RCC_PERIPHCLK_LPTIM1          ((uint32_t)0x00040000U)\r\n#define RCC_PERIPHCLK_SAI1            ((uint32_t)0x00080000U)\r\n#define RCC_PERIPHCLK_SAI2            ((uint32_t)0x00100000U)\r\n#define RCC_PERIPHCLK_CLK48           ((uint32_t)0x00200000U)\r\n#define RCC_PERIPHCLK_CEC             ((uint32_t)0x00400000U)\r\n#define RCC_PERIPHCLK_SDMMC1          ((uint32_t)0x00800000U)\r\n#define RCC_PERIPHCLK_SPDIFRX         ((uint32_t)0x01000000U)\r\n#define RCC_PERIPHCLK_PLLI2S          ((uint32_t)0x02000000U)\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)    \r\n#define RCC_PERIPHCLK_SDMMC2          ((uint32_t)0x04000000U)\r\n#define RCC_PERIPHCLK_DFSDM1           ((uint32_t)0x08000000U)\r\n#define RCC_PERIPHCLK_DFSDM1_AUDIO      ((uint32_t)0x10000000U)    \r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n    \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCCEx PLLI2SP Clock Divider\r\n  * @{\r\n  */\r\n#define RCC_PLLI2SP_DIV2                  ((uint32_t)0x00000000U)\r\n#define RCC_PLLI2SP_DIV4                  ((uint32_t)0x00000001U)\r\n#define RCC_PLLI2SP_DIV6                  ((uint32_t)0x00000002U)\r\n#define RCC_PLLI2SP_DIV8                  ((uint32_t)0x00000003U)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider\r\n  * @{\r\n  */\r\n#define RCC_PLLSAIP_DIV2                  ((uint32_t)0x00000000U)\r\n#define RCC_PLLSAIP_DIV4                  ((uint32_t)0x00000001U)\r\n#define RCC_PLLSAIP_DIV6                  ((uint32_t)0x00000002U)\r\n#define RCC_PLLSAIP_DIV8                  ((uint32_t)0x00000003U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_PLLSAI_DIVR RCCEx PLLSAI DIVR\r\n  * @{\r\n  */\r\n#define RCC_PLLSAIDIVR_2                ((uint32_t)0x00000000U)\r\n#define RCC_PLLSAIDIVR_4                RCC_DCKCFGR1_PLLSAIDIVR_0\r\n#define RCC_PLLSAIDIVR_8                RCC_DCKCFGR1_PLLSAIDIVR_1\r\n#define RCC_PLLSAIDIVR_16               RCC_DCKCFGR1_PLLSAIDIVR\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_I2S_Clock_Source RCCEx I2S Clock Source\r\n  * @{\r\n  */\r\n#define RCC_I2SCLKSOURCE_PLLI2S             ((uint32_t)0x00000000U)\r\n#define RCC_I2SCLKSOURCE_EXT                RCC_CFGR_I2SSRC\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n  \r\n/** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_SAI1CLKSOURCE_PLLSAI             ((uint32_t)0x00000000U)\r\n#define RCC_SAI1CLKSOURCE_PLLI2S             RCC_DCKCFGR1_SAI1SEL_0\r\n#define RCC_SAI1CLKSOURCE_PIN                RCC_DCKCFGR1_SAI1SEL_1\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define RCC_SAI1CLKSOURCE_PLLSRC             RCC_DCKCFGR1_SAI1SEL\r\n#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup RCCEx_SAI2_Clock_Source RCCEx SAI2 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_SAI2CLKSOURCE_PLLSAI             ((uint32_t)0x00000000U)\r\n#define RCC_SAI2CLKSOURCE_PLLI2S             RCC_DCKCFGR1_SAI2SEL_0\r\n#define RCC_SAI2CLKSOURCE_PIN                RCC_DCKCFGR1_SAI2SEL_1\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define RCC_SAI2CLKSOURCE_PLLSRC             RCC_DCKCFGR1_SAI2SEL\r\n#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source\r\n  * @{\r\n  */\r\n#define RCC_CECCLKSOURCE_LSE             ((uint32_t)0x00000000U)\r\n#define RCC_CECCLKSOURCE_HSI             RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_USART1CLKSOURCE_PCLK2      ((uint32_t)0x00000000U)\r\n#define RCC_USART1CLKSOURCE_SYSCLK     RCC_DCKCFGR2_USART1SEL_0\r\n#define RCC_USART1CLKSOURCE_HSI        RCC_DCKCFGR2_USART1SEL_1\r\n#define RCC_USART1CLKSOURCE_LSE        RCC_DCKCFGR2_USART1SEL\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_USART2CLKSOURCE_PCLK1       ((uint32_t)0x00000000U)\r\n#define RCC_USART2CLKSOURCE_SYSCLK     RCC_DCKCFGR2_USART2SEL_0\r\n#define RCC_USART2CLKSOURCE_HSI        RCC_DCKCFGR2_USART2SEL_1\r\n#define RCC_USART2CLKSOURCE_LSE        RCC_DCKCFGR2_USART2SEL\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_USART3CLKSOURCE_PCLK1       ((uint32_t)0x00000000U)\r\n#define RCC_USART3CLKSOURCE_SYSCLK     RCC_DCKCFGR2_USART3SEL_0\r\n#define RCC_USART3CLKSOURCE_HSI        RCC_DCKCFGR2_USART3SEL_1\r\n#define RCC_USART3CLKSOURCE_LSE        RCC_DCKCFGR2_USART3SEL\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_UART4CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)\r\n#define RCC_UART4CLKSOURCE_SYSCLK       RCC_DCKCFGR2_UART4SEL_0\r\n#define RCC_UART4CLKSOURCE_HSI          RCC_DCKCFGR2_UART4SEL_1\r\n#define RCC_UART4CLKSOURCE_LSE          RCC_DCKCFGR2_UART4SEL\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_UART5CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)\r\n#define RCC_UART5CLKSOURCE_SYSCLK       RCC_DCKCFGR2_UART5SEL_0\r\n#define RCC_UART5CLKSOURCE_HSI          RCC_DCKCFGR2_UART5SEL_1\r\n#define RCC_UART5CLKSOURCE_LSE          RCC_DCKCFGR2_UART5SEL\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_USART6CLKSOURCE_PCLK2       ((uint32_t)0x00000000U)\r\n#define RCC_USART6CLKSOURCE_SYSCLK      RCC_DCKCFGR2_USART6SEL_0\r\n#define RCC_USART6CLKSOURCE_HSI         RCC_DCKCFGR2_USART6SEL_1\r\n#define RCC_USART6CLKSOURCE_LSE         RCC_DCKCFGR2_USART6SEL\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_UART7CLKSOURCE_PCLK1       ((uint32_t)0x00000000U)\r\n#define RCC_UART7CLKSOURCE_SYSCLK      RCC_DCKCFGR2_UART7SEL_0\r\n#define RCC_UART7CLKSOURCE_HSI         RCC_DCKCFGR2_UART7SEL_1\r\n#define RCC_UART7CLKSOURCE_LSE         RCC_DCKCFGR2_UART7SEL\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_UART8CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)\r\n#define RCC_UART8CLKSOURCE_SYSCLK      RCC_DCKCFGR2_UART8SEL_0\r\n#define RCC_UART8CLKSOURCE_HSI         RCC_DCKCFGR2_UART8SEL_1\r\n#define RCC_UART8CLKSOURCE_LSE         RCC_DCKCFGR2_UART8SEL\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_I2C1CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)\r\n#define RCC_I2C1CLKSOURCE_SYSCLK       RCC_DCKCFGR2_I2C1SEL_0\r\n#define RCC_I2C1CLKSOURCE_HSI          RCC_DCKCFGR2_I2C1SEL_1\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_I2C2CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)\r\n#define RCC_I2C2CLKSOURCE_SYSCLK       RCC_DCKCFGR2_I2C2SEL_0\r\n#define RCC_I2C2CLKSOURCE_HSI          RCC_DCKCFGR2_I2C2SEL_1\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_I2C3CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)\r\n#define RCC_I2C3CLKSOURCE_SYSCLK       RCC_DCKCFGR2_I2C3SEL_0\r\n#define RCC_I2C3CLKSOURCE_HSI          RCC_DCKCFGR2_I2C3SEL_1\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_I2C4CLKSOURCE_PCLK1        ((uint32_t)0x00000000U)\r\n#define RCC_I2C4CLKSOURCE_SYSCLK       RCC_DCKCFGR2_I2C4SEL_0\r\n#define RCC_I2C4CLKSOURCE_HSI          RCC_DCKCFGR2_I2C4SEL_1\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_LPTIM1CLKSOURCE_PCLK       ((uint32_t)0x00000000U)\r\n#define RCC_LPTIM1CLKSOURCE_LSI        RCC_DCKCFGR2_LPTIM1SEL_0\r\n#define RCC_LPTIM1CLKSOURCE_HSI        RCC_DCKCFGR2_LPTIM1SEL_1\r\n#define RCC_LPTIM1CLKSOURCE_LSE        RCC_DCKCFGR2_LPTIM1SEL\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_CLK48_Clock_Source RCCEx CLK48 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_CLK48SOURCE_PLL         ((uint32_t)0x00000000U)\r\n#define RCC_CLK48SOURCE_PLLSAIP     RCC_DCKCFGR2_CK48MSEL\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection\r\n  * @{\r\n  */\r\n#define RCC_TIMPRES_DESACTIVATED        ((uint32_t)0x00000000U)\r\n#define RCC_TIMPRES_ACTIVATED           RCC_DCKCFGR1_TIMPRE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_SDMMC1CLKSOURCE_CLK48              ((uint32_t)0x00000000U)\r\n#define RCC_SDMMC1CLKSOURCE_SYSCLK             RCC_DCKCFGR2_SDMMC1SEL\r\n/**\r\n  * @}\r\n  */\r\n\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n/** @defgroup RCCEx_SDMMC2_Clock_Source RCCEx SDMMC2 Clock Source\r\n  * @{\r\n  */\r\n#define RCC_SDMMC2CLKSOURCE_CLK48              ((uint32_t)0x00000000U)\r\n#define RCC_SDMMC2CLKSOURCE_SYSCLK             RCC_DCKCFGR2_SDMMC2SEL\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source  RCCEx DFSDM1 Kernel Clock Source\r\n  * @{\r\n  */\r\n#define RCC_DFSDM1CLKSOURCE_PCLK             ((uint32_t)0x00000000U)\r\n#define RCC_DFSDM1CLKSOURCE_SYSCLK           RCC_DCKCFGR1_DFSDM1SEL\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_DFSDM1_AUDIO_Clock_Source RCCEx DFSDM1 AUDIO Clock Source\r\n  * @{\r\n  */\r\n#define RCC_DFSDM1AUDIOCLKSOURCE_SAI1        ((uint32_t)0x00000000U)\r\n#define RCC_DFSDM1AUDIOCLKSOURCE_SAI2        RCC_DCKCFGR1_ADFSDM1SEL\r\n/**\r\n  * @}\r\n  */\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n#if defined (STM32F769xx) || defined (STM32F779xx)\r\n/** @defgroup RCCEx_DSI_Clock_Source  RCC DSI Clock Source\r\n  * @{\r\n  */\r\n#define RCC_DSICLKSOURCE_DSIPHY             ((uint32_t)0x00000000U)\r\n#define RCC_DSICLKSOURCE_PLLR               ((uint32_t)RCC_DCKCFGR2_DSISEL)      \r\n/**\r\n  * @}\r\n  */ \r\n#endif /* STM32F769xx || STM32F779xx */\r\n\r\n/**\r\n  * @}\r\n  */\r\n     \r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros\r\n  * @{\r\n  */\r\n/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable\r\n  * @brief  Enables or disables the AHB/APB peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before \r\n  *         using it.   \r\n  * @{\r\n  */\r\n \r\n/** @brief  Enables or disables the AHB1 peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before \r\n  *         using it.\r\n  */\r\n#define __HAL_RCC_BKPSRAM_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n                                      \r\n#define __HAL_RCC_DTCMRAMEN_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n                                      \r\n#define __HAL_RCC_DMA2_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)  \r\n\r\n#define __HAL_RCC_DMA2D_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0) \r\n\r\n#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_GPIOC_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_GPIOF_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_GPIOG_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_GPIOH_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_GPIOI_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_GPIOJ_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_GPIOK_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_BKPSRAM_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))\r\n#define __HAL_RCC_DTCMRAMEN_CLK_DISABLE()       (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN))\r\n#define __HAL_RCC_DMA2_CLK_DISABLE()            (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))\r\n#define __HAL_RCC_DMA2D_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))\r\n#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()      (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))\r\n#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))\r\n#define __HAL_RCC_GPIOA_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))\r\n#define __HAL_RCC_GPIOB_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))\r\n#define __HAL_RCC_GPIOC_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))\r\n#define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))\r\n#define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))\r\n#define __HAL_RCC_GPIOF_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))\r\n#define __HAL_RCC_GPIOG_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))\r\n#define __HAL_RCC_GPIOH_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))\r\n#define __HAL_RCC_GPIOI_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))\r\n#define __HAL_RCC_GPIOJ_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))\r\n#define __HAL_RCC_GPIOK_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))\r\n/**\r\n  * @brief  Enable ETHERNET clock.\r\n  */\r\n#define __HAL_RCC_ETHMAC_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_ETHMACTX_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_ETHMACRX_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_ETHMACPTP_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n                                      \r\n#define __HAL_RCC_ETH_CLK_ENABLE()       do {                            \\\r\n                                     __HAL_RCC_ETHMAC_CLK_ENABLE();      \\\r\n                                     __HAL_RCC_ETHMACTX_CLK_ENABLE();    \\\r\n                                     __HAL_RCC_ETHMACRX_CLK_ENABLE();    \\\r\n                                    } while(0)\r\n/**\r\n  * @brief  Disable ETHERNET clock.\r\n  */\r\n#define __HAL_RCC_ETHMAC_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))\r\n#define __HAL_RCC_ETHMACTX_CLK_DISABLE()  (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))\r\n#define __HAL_RCC_ETHMACRX_CLK_DISABLE()  (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))\r\n#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))\r\n#define __HAL_RCC_ETH_CLK_DISABLE()       do {                             \\\r\n                                      __HAL_RCC_ETHMACTX_CLK_DISABLE();    \\\r\n                                      __HAL_RCC_ETHMACRX_CLK_DISABLE();    \\\r\n                                      __HAL_RCC_ETHMAC_CLK_DISABLE();      \\\r\n                                     } while(0)\r\n                                     \r\n/** @brief  Enable or disable the AHB2 peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before \r\n  *         using it.\r\n  */\r\n#define __HAL_RCC_DCMI_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)                                        \r\n#define __HAL_RCC_JPEG_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n#define __HAL_RCC_JPEG_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_JPEGEN))                                        \r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */                                       \r\n\r\n#define __HAL_RCC_RNG_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                        __HAL_RCC_SYSCFG_CLK_ENABLE();\\\r\n                                      } while(0) \r\n                                      \r\n#define __HAL_RCC_DCMI_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))                                        \r\n#define __HAL_RCC_RNG_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))                                        \r\n\r\n#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))\r\n#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_CRYP_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_HASH_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n                                      \r\n#define __HAL_RCC_CRYP_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))\r\n#define __HAL_RCC_HASH_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) \r\n#endif /* STM32F756x || STM32F777xx || STM32F779xx */\r\n                                        \r\n/** @brief  Enables or disables the AHB3 peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before \r\n  *         using it. \r\n  */\r\n#define __HAL_RCC_FMC_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_QSPI_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_FMC_CLK_DISABLE()   (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))\r\n#define __HAL_RCC_QSPI_CLK_DISABLE()  (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))\r\n\r\n/** @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before \r\n  *         using it. \r\n  */\r\n#define __HAL_RCC_TIM2_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_TIM3_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_TIM4_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_TIM5_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_TIM12_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_TIM13_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_TIM14_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_LPTIM1_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_RTC_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n                                        \r\n#define __HAL_RCC_CAN3_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n                                        \r\n#define __HAL_RCC_SPI2_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_SPI3_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_SPDIFRX_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_USART2_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_USART3_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_UART4_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_UART5_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_I2C1_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_I2C2_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_I2C3_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_I2C4_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_CAN1_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_CAN2_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_CEC_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_DAC_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_UART7_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_UART8_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))\r\n#define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))\r\n#define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))\r\n#define __HAL_RCC_TIM5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))\r\n#define __HAL_RCC_TIM6_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))\r\n#define __HAL_RCC_TIM7_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))\r\n#define __HAL_RCC_TIM12_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))\r\n#define __HAL_RCC_TIM13_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))\r\n#define __HAL_RCC_TIM14_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))\r\n#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_RTC_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCEN))                                        \r\n#define __HAL_RCC_CAN3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN))\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */                                        \r\n#define __HAL_RCC_SPI2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))\r\n#define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))\r\n#define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))\r\n#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))\r\n#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))\r\n#define __HAL_RCC_UART4_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))\r\n#define __HAL_RCC_UART5_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))\r\n#define __HAL_RCC_I2C1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))\r\n#define __HAL_RCC_I2C2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))\r\n#define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))\r\n#define __HAL_RCC_I2C4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN))\r\n#define __HAL_RCC_CAN1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))\r\n#define __HAL_RCC_CAN2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))\r\n#define __HAL_RCC_CEC_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))\r\n#define __HAL_RCC_DAC_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))\r\n#define __HAL_RCC_UART7_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))\r\n#define __HAL_RCC_UART8_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))\r\n\r\n/** @brief  Enable or disable the High Speed APB (APB2) peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before \r\n  *         using it.\r\n  */\r\n#define __HAL_RCC_TIM1_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_TIM8_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_USART1_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_USART6_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)                                        \r\n#define __HAL_RCC_SDMMC2_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n#define __HAL_RCC_ADC1_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_ADC2_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_ADC3_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_SDMMC1_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_SPI1_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_SPI4_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_TIM9_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_TIM10_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_TIM11_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_SPI5_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_SPI6_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_SAI1_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#define __HAL_RCC_SAI2_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n\r\n#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_LTDC_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n                                        \r\n#if defined (STM32F769xx) || defined (STM32F779xx)                                        \r\n#define __HAL_RCC_DSI_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)                                                                            \r\n#endif /* STM32F769xx || STM32F779xx */\r\n                                        \r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)                                        \r\n#define __HAL_RCC_DFSDM1_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)    \r\n\r\n#define __HAL_RCC_MDIO_CLK_ENABLE()   do { \\\r\n                                        __IO uint32_t tmpreg; \\\r\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\\\r\n                                        /* Delay after an RCC peripheral clock enabling */ \\\r\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\\\r\n                                        UNUSED(tmpreg); \\\r\n                                      } while(0)\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n                                        \r\n#define __HAL_RCC_TIM1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))\r\n#define __HAL_RCC_TIM8_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))\r\n#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))\r\n#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)                                        \r\n#define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC2EN))\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */                                        \r\n#define __HAL_RCC_ADC1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))\r\n#define __HAL_RCC_ADC2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))\r\n#define __HAL_RCC_ADC3_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))\r\n#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN))\r\n#define __HAL_RCC_SPI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))\r\n#define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))\r\n#define __HAL_RCC_TIM9_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))\r\n#define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))\r\n#define __HAL_RCC_TIM11_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))\r\n#define __HAL_RCC_SPI5_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))\r\n#define __HAL_RCC_SPI6_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))\r\n#define __HAL_RCC_SAI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))\r\n#define __HAL_RCC_SAI2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))\r\n#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_LTDC_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))\r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n#if defined (STM32F769xx) || defined (STM32F779xx)                                        \r\n#define __HAL_RCC_DSI_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))\r\n#endif /* STM32F769xx || STM32F779xx */                                        \r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)                                        \r\n#define __HAL_RCC_DFSDM1_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN))\r\n#define __HAL_RCC_MDIO_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_MDIOEN))\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n                                        \r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status\r\n  * @brief  Get the enable or disable status of the AHB/APB peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before\r\n  *         using it.\r\n  * @{\r\n  */\r\n \r\n/** @brief  Get the enable or disable status of the AHB1 peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before\r\n  *         using it. \r\n  */\r\n#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)\r\n#define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET)\r\n#define __HAL_RCC_DMA2_IS_CLK_ENABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET)  \r\n#define __HAL_RCC_DMA2D_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)\r\n#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)\r\n#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)\r\n#define __HAL_RCC_GPIOA_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET)\r\n#define __HAL_RCC_GPIOB_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET)\r\n#define __HAL_RCC_GPIOC_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET)\r\n#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)\r\n#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)\r\n#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)\r\n#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)\r\n#define __HAL_RCC_GPIOH_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET)\r\n#define __HAL_RCC_GPIOI_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)\r\n#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)\r\n#define __HAL_RCC_GPIOK_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)\r\n\r\n#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)\r\n#define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET)\r\n#define __HAL_RCC_DMA2_IS_CLK_DISABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET)\r\n#define __HAL_RCC_DMA2D_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)\r\n#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)\r\n#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)\r\n#define __HAL_RCC_GPIOA_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET)\r\n#define __HAL_RCC_GPIOB_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET)\r\n#define __HAL_RCC_GPIOC_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET)\r\n#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)\r\n#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)\r\n#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)\r\n#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)\r\n#define __HAL_RCC_GPIOH_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET)\r\n#define __HAL_RCC_GPIOI_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)\r\n#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)\r\n#define __HAL_RCC_GPIOK_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)\r\n/**\r\n  * @brief  Enable ETHERNET clock.\r\n  */\r\n#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)\r\n#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)\r\n#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)\r\n#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)\r\n#define __HAL_RCC_ETH_IS_CLK_ENABLED()        (__HAL_RCC_ETHMAC_IS_CLK_ENABLED()   && \\\r\n                                               __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \\\r\n                                               __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())\r\n\r\n/**\r\n  * @brief  Disable ETHERNET clock.\r\n  */\r\n#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)\r\n#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)\r\n#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)\r\n#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)\r\n#define __HAL_RCC_ETH_IS_CLK_DISABLED()        (__HAL_RCC_ETHMAC_IS_CLK_DISABLED()   && \\\r\n                                                __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \\\r\n                                                __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())\r\n\r\n/** @brief  Get the enable or disable status of the AHB2 peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before\r\n  *         using it. \r\n  */\r\n#define __HAL_RCC_DCMI_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)\r\n#define __HAL_RCC_RNG_IS_CLK_ENABLED()         ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)\r\n#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)\r\n                                   \r\n#define __HAL_RCC_DCMI_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)\r\n#define __HAL_RCC_RNG_IS_CLK_DISABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)                                        \r\n#define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)\r\n\r\n#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_CRYP_IS_CLK_ENABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)\r\n#define __HAL_RCC_HASH_IS_CLK_ENABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)\r\n#define __HAL_RCC_CRYP_IS_CLK_DISABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)\r\n#define __HAL_RCC_HASH_IS_CLK_DISABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) \r\n#endif /* STM32F756xx || STM32F777xx || STM32F779xx */\r\n\r\n#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_JPEG_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) != RESET)\r\n#define __HAL_RCC_JPEG_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) == RESET)\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n/** @brief  Get the enable or disable status of the AHB3 peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before\r\n  *         using it.\r\n  */  \r\n#define __HAL_RCC_FMC_IS_CLK_ENABLED()   ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)\r\n#define __HAL_RCC_QSPI_IS_CLK_ENABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)\r\n\r\n#define __HAL_RCC_FMC_IS_CLK_DISABLED()   ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)\r\n#define __HAL_RCC_QSPI_IS_CLK_DISABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)\r\n\r\n/** @brief  Get the enable or disable status of the APB1 peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before\r\n  *         using it.\r\n  */\r\n#define __HAL_RCC_TIM2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)\r\n#define __HAL_RCC_TIM3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)\r\n#define __HAL_RCC_TIM4_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)\r\n#define __HAL_RCC_TIM5_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)\r\n#define __HAL_RCC_TIM6_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)\r\n#define __HAL_RCC_TIM7_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)\r\n#define __HAL_RCC_TIM12_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)\r\n#define __HAL_RCC_TIM13_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)\r\n#define __HAL_RCC_TIM14_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)\r\n#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_RTC_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) != RESET)\r\n#define __HAL_RCC_CAN3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET)\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n#define __HAL_RCC_SPI2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)\r\n#define __HAL_RCC_SPI3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)\r\n#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)\r\n#define __HAL_RCC_USART2_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)\r\n#define __HAL_RCC_USART3_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)\r\n#define __HAL_RCC_UART4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)\r\n#define __HAL_RCC_UART5_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)\r\n#define __HAL_RCC_I2C1_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)\r\n#define __HAL_RCC_I2C2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)\r\n#define __HAL_RCC_I2C3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)\r\n#define __HAL_RCC_I2C4_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET)\r\n#define __HAL_RCC_CAN1_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)\r\n#define __HAL_RCC_CAN2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)\r\n#define __HAL_RCC_CEC_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)\r\n#define __HAL_RCC_DAC_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)\r\n#define __HAL_RCC_UART7_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)\r\n#define __HAL_RCC_UART8_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)\r\n\r\n#define __HAL_RCC_TIM2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)\r\n#define __HAL_RCC_TIM3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)\r\n#define __HAL_RCC_TIM4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)\r\n#define __HAL_RCC_TIM5_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)\r\n#define __HAL_RCC_TIM6_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)\r\n#define __HAL_RCC_TIM7_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)\r\n#define __HAL_RCC_TIM12_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)\r\n#define __HAL_RCC_TIM13_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)\r\n#define __HAL_RCC_TIM14_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)\r\n#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_RTC_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) == RESET)\r\n#define __HAL_RCC_CAN3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET)\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n#define __HAL_RCC_SPI2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)\r\n#define __HAL_RCC_SPI3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)\r\n#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)\r\n#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)\r\n#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)\r\n#define __HAL_RCC_UART4_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)\r\n#define __HAL_RCC_UART5_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)\r\n#define __HAL_RCC_I2C1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)\r\n#define __HAL_RCC_I2C2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)\r\n#define __HAL_RCC_I2C3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)\r\n#define __HAL_RCC_I2C4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET)\r\n#define __HAL_RCC_CAN1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)\r\n#define __HAL_RCC_CAN2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)\r\n#define __HAL_RCC_CEC_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)\r\n#define __HAL_RCC_DAC_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)\r\n#define __HAL_RCC_UART7_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)\r\n#define __HAL_RCC_UART8_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)\r\n\r\n/** @brief  Get the enable or disable status of the APB2 peripheral clock.\r\n  * @note   After reset, the peripheral clock (used for registers read/write access)\r\n  *         is disabled and the application software has to enable this clock before\r\n  *         using it.\r\n  */\r\n#define __HAL_RCC_TIM1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)\r\n#define __HAL_RCC_TIM8_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)\r\n#define __HAL_RCC_USART1_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)\r\n#define __HAL_RCC_USART6_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)\r\n#define __HAL_RCC_ADC1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)\r\n#define __HAL_RCC_ADC2_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)\r\n#define __HAL_RCC_ADC3_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)\r\n#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET)\r\n#define __HAL_RCC_SPI1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)\r\n#define __HAL_RCC_SPI4_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)\r\n#define __HAL_RCC_TIM9_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)\r\n#define __HAL_RCC_TIM10_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)\r\n#define __HAL_RCC_TIM11_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)\r\n#define __HAL_RCC_SPI5_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)\r\n#define __HAL_RCC_SPI6_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)\r\n#define __HAL_RCC_SAI1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)\r\n#define __HAL_RCC_SAI2_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)\r\n#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_LTDC_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)\r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n#if defined (STM32F769xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_DSI_IS_CLK_ENABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET)\r\n#endif /* STM32F769xx || STM32F779xx */\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) != RESET)\r\n#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET)\r\n#define __HAL_RCC_MDIO_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) != RESET)\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n#define __HAL_RCC_TIM1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)\r\n#define __HAL_RCC_TIM8_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)\r\n#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)\r\n#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)\r\n#define __HAL_RCC_ADC1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)\r\n#define __HAL_RCC_ADC2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)\r\n#define __HAL_RCC_ADC3_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)\r\n#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET)\r\n#define __HAL_RCC_SPI1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)\r\n#define __HAL_RCC_SPI4_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)\r\n#define __HAL_RCC_TIM9_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)\r\n#define __HAL_RCC_TIM10_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)\r\n#define __HAL_RCC_TIM11_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)\r\n#define __HAL_RCC_SPI5_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)\r\n#define __HAL_RCC_SPI6_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)\r\n#define __HAL_RCC_SAI1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)\r\n#define __HAL_RCC_SAI2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)\r\n#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_LTDC_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)  \r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n#if defined (STM32F769xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_DSI_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET)\r\n#endif /* STM32F769xx || STM32F779xx */\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) == RESET)\r\n#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET)\r\n#define __HAL_RCC_MDIO_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) == RESET)\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset\r\n  * @brief  Forces or releases AHB/APB peripheral reset.\r\n  * @{\r\n  */\r\n  \r\n/** @brief  Force or release AHB1 peripheral reset.\r\n  */  \r\n#define __HAL_RCC_DMA2_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))\r\n#define __HAL_RCC_DMA2D_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))\r\n#define __HAL_RCC_ETHMAC_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))\r\n#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))\r\n#define __HAL_RCC_GPIOA_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))\r\n#define __HAL_RCC_GPIOB_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))\r\n#define __HAL_RCC_GPIOC_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))\r\n#define __HAL_RCC_GPIOD_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))\r\n#define __HAL_RCC_GPIOE_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))\r\n#define __HAL_RCC_GPIOF_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))\r\n#define __HAL_RCC_GPIOG_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))\r\n#define __HAL_RCC_GPIOH_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))\r\n#define __HAL_RCC_GPIOI_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))\r\n#define __HAL_RCC_GPIOJ_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))\r\n#define __HAL_RCC_GPIOK_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))\r\n\r\n#define __HAL_RCC_DMA2_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))\r\n#define __HAL_RCC_DMA2D_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))\r\n#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))\r\n#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))\r\n#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))\r\n#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))\r\n#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))\r\n#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))\r\n#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))\r\n#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))\r\n#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))\r\n#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))\r\n#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))\r\n#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))\r\n#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))\r\n \r\n/** @brief  Force or release AHB2 peripheral reset.\r\n  */\r\n#define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFFU) \r\n#define __HAL_RCC_DCMI_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))\r\n#define __HAL_RCC_RNG_FORCE_RESET()    (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))\r\n#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))\r\n\r\n#define __HAL_RCC_AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00U)\r\n#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))\r\n#define __HAL_RCC_RNG_RELEASE_RESET()  (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))\r\n#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))\r\n\r\n#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_JPEG_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_JPEGRST))\r\n#define __HAL_RCC_JPEG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_JPEGRST))\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_CRYP_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))\r\n#define __HAL_RCC_HASH_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))\r\n#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))\r\n#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))\r\n#endif /* STM32F756xx || STM32F777xx || STM32F779xx */\r\n\r\n/** @brief  Force or release AHB3 peripheral reset\r\n  */ \r\n#define __HAL_RCC_AHB3_FORCE_RESET()   (RCC->AHB3RSTR = 0xFFFFFFFFU) \r\n#define __HAL_RCC_FMC_FORCE_RESET()    (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))\r\n#define __HAL_RCC_QSPI_FORCE_RESET()   (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))\r\n\r\n#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)\r\n#define __HAL_RCC_FMC_RELEASE_RESET()  (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))\r\n#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))\r\n \r\n/** @brief  Force or release APB1 peripheral reset.\r\n  */ \r\n#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))\r\n#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))\r\n#define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))\r\n#define __HAL_RCC_TIM5_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))\r\n#define __HAL_RCC_TIM6_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))\r\n#define __HAL_RCC_TIM7_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))\r\n#define __HAL_RCC_TIM12_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))\r\n#define __HAL_RCC_TIM13_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))\r\n#define __HAL_RCC_TIM14_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))\r\n#define __HAL_RCC_LPTIM1_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_CAN3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST))\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n#define __HAL_RCC_SPI2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))\r\n#define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))\r\n#define __HAL_RCC_SPDIFRX_FORCE_RESET()  (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST))\r\n#define __HAL_RCC_USART2_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))\r\n#define __HAL_RCC_USART3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))\r\n#define __HAL_RCC_UART4_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))\r\n#define __HAL_RCC_UART5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))\r\n#define __HAL_RCC_I2C1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))\r\n#define __HAL_RCC_I2C2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))\r\n#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))\r\n#define __HAL_RCC_I2C4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST))\r\n#define __HAL_RCC_CAN1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))\r\n#define __HAL_RCC_CAN2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))\r\n#define __HAL_RCC_CEC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))\r\n#define __HAL_RCC_DAC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))\r\n#define __HAL_RCC_UART7_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))\r\n#define __HAL_RCC_UART8_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))\r\n\r\n#define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))\r\n#define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))\r\n#define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))\r\n#define __HAL_RCC_TIM5_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))\r\n#define __HAL_RCC_TIM6_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))\r\n#define __HAL_RCC_TIM7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))\r\n#define __HAL_RCC_TIM12_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))\r\n#define __HAL_RCC_TIM13_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))\r\n#define __HAL_RCC_TIM14_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))\r\n#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_CAN3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST))\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n#define __HAL_RCC_SPI2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))\r\n#define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))\r\n#define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))\r\n#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))\r\n#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))\r\n#define __HAL_RCC_UART4_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))\r\n#define __HAL_RCC_UART5_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))\r\n#define __HAL_RCC_I2C1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))\r\n#define __HAL_RCC_I2C2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))\r\n#define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))\r\n#define __HAL_RCC_I2C4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST))\r\n#define __HAL_RCC_CAN1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))\r\n#define __HAL_RCC_CAN2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))\r\n#define __HAL_RCC_CEC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))\r\n#define __HAL_RCC_DAC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))\r\n#define __HAL_RCC_UART7_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))\r\n#define __HAL_RCC_UART8_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))\r\n\r\n/** @brief  Force or release APB2 peripheral reset.\r\n  */\r\n#define __HAL_RCC_TIM1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))\r\n#define __HAL_RCC_TIM8_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))\r\n#define __HAL_RCC_USART1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))\r\n#define __HAL_RCC_USART6_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))\r\n#define __HAL_RCC_ADC_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))\r\n#define __HAL_RCC_SDMMC1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC1RST))\r\n#define __HAL_RCC_SPI1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))\r\n#define __HAL_RCC_SPI4_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))\r\n#define __HAL_RCC_TIM9_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))\r\n#define __HAL_RCC_TIM10_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))\r\n#define __HAL_RCC_TIM11_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))\r\n#define __HAL_RCC_SPI5_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))\r\n#define __HAL_RCC_SPI6_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))\r\n#define __HAL_RCC_SAI1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))\r\n#define __HAL_RCC_SAI2_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))\r\n#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_LTDC_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))\r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n#define __HAL_RCC_TIM1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))\r\n#define __HAL_RCC_TIM8_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))\r\n#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))\r\n#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))\r\n#define __HAL_RCC_ADC_RELEASE_RESET()    (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))\r\n#define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC1RST))\r\n#define __HAL_RCC_SPI1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))\r\n#define __HAL_RCC_SPI4_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))\r\n#define __HAL_RCC_TIM9_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))\r\n#define __HAL_RCC_TIM10_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))\r\n#define __HAL_RCC_TIM11_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))\r\n#define __HAL_RCC_SPI5_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))\r\n#define __HAL_RCC_SPI6_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))\r\n#define __HAL_RCC_SAI1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))\r\n#define __HAL_RCC_SAI2_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))\r\n#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_LTDC_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))\r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n#if defined (STM32F769xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_DSI_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST))\r\n#define __HAL_RCC_DSI_RELEASE_RESET()    (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST))\r\n#endif /* STM32F769xx || STM32F779xx */\r\n\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_SDMMC2_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC2RST))\r\n#define __HAL_RCC_DFSDM1_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST))\r\n#define __HAL_RCC_MDIO_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_MDIORST))\r\n\r\n#define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC2RST))\r\n#define __HAL_RCC_DFSDM1_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST))\r\n#define __HAL_RCC_MDIO_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_MDIORST))\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable\r\n  * @brief  Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode.\r\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r\n  *         power consumption.\r\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r\n  * @{\r\n  */ \r\n  \r\n/** @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.\r\n  */ \r\n#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))\r\n#define __HAL_RCC_AXI_CLK_SLEEP_ENABLE()        (RCC->AHB1LPENR |= (RCC_AHB1LPENR_AXILPEN))\r\n#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))\r\n#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))\r\n#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))\r\n#define __HAL_RCC_DTCM_CLK_SLEEP_ENABLE()       (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DTCMLPEN))\r\n#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE()       (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))\r\n#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))\r\n#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))\r\n#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))\r\n#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))\r\n#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))\r\n#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))\r\n#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))\r\n#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))\r\n#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))\r\n#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))\r\n#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))\r\n#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))\r\n#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))\r\n#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))\r\n#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))\r\n#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))\r\n#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))\r\n#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))\r\n\r\n#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))\r\n#define __HAL_RCC_AXI_CLK_SLEEP_DISABLE()       (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_AXILPEN))\r\n#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))\r\n#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))\r\n#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))\r\n#define __HAL_RCC_DTCM_CLK_SLEEP_DISABLE()      (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DTCMLPEN))\r\n#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE()      (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))\r\n#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))\r\n#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))\r\n#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))\r\n#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))\r\n#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))\r\n#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()      (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))\r\n#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))\r\n#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))\r\n#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))\r\n#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))\r\n#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))\r\n#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))\r\n#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))\r\n#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))\r\n#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))\r\n#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))\r\n#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))\r\n#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))\r\n\r\n/** @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.\r\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r\n  *         power consumption.\r\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r\n  */\r\n#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()        (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))\r\n#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE()       (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))\r\n\r\n#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE()        (RCC->AHB2LPENR |= (RCC_AHB2LPENR_JPEGLPEN))\r\n#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE()       (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_JPEGLPEN))\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()         (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))\r\n#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()        (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))\r\n\r\n#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))\r\n#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))\r\n\r\n#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE()        (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))\r\n#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE()        (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))\r\n                                         \r\n#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE()       (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))\r\n#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE()       (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))\r\n#endif /* STM32F756xx || STM32F777xx || STM32F779xx */\r\n\r\n/** @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.\r\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r\n  *         power consumption.\r\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r\n  */\r\n#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))\r\n#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))\r\n\r\n#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))\r\n#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))\r\n\r\n/** @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.\r\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r\n  *         power consumption.\r\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r\n  */  \r\n#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))\r\n#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))\r\n#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))\r\n#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))\r\n#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))\r\n#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))\r\n#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))\r\n#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))\r\n#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))\r\n#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCLPEN))\r\n#define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN))\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))\r\n#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))\r\n#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN))\r\n#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))\r\n#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))\r\n#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))\r\n#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))\r\n#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))\r\n#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))\r\n#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))\r\n#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN))\r\n#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))\r\n#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))\r\n#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN))\r\n#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))\r\n#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))\r\n#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))\r\n\r\n#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))\r\n#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))\r\n#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))\r\n#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))\r\n#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))\r\n#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))\r\n#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))\r\n#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))\r\n#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))\r\n#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCLPEN))\r\n#define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN))\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))\r\n#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))\r\n#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))\r\n#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))\r\n#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))\r\n#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))\r\n#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))\r\n#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))\r\n#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))\r\n#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))\r\n#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN))\r\n#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))\r\n#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))\r\n#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))\r\n#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))\r\n#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))\r\n#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))\r\n\r\n/** @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.\r\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r\n  *         power consumption.\r\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r\n  */ \r\n#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))\r\n#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))\r\n#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))\r\n#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))\r\n#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))\r\n#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))\r\n#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))\r\n#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC1LPEN))\r\n#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))\r\n#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))\r\n#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))\r\n#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))\r\n#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))\r\n#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))\r\n#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))\r\n#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))\r\n#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))\r\n#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))\r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))\r\n#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))\r\n#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))\r\n#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))\r\n#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))\r\n#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))\r\n#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))\r\n#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC1LPEN))\r\n#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))\r\n#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))\r\n#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))\r\n#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))\r\n#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))\r\n#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))\r\n#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))\r\n#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))\r\n#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))\r\n#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))\r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n#if defined (STM32F769xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE()     (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN))\r\n#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN))\r\n#endif /* STM32F769xx || STM32F779xx */\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC2LPEN))\r\n#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN))\r\n#define __HAL_RCC_MDIO_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_MDIOLPEN))\r\n\r\n#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC2LPEN))\r\n#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN))\r\n#define __HAL_RCC_MDIO_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_MDIOLPEN))\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_Clock_Sleep_Enable_Disable_Status AHB/APB Peripheral Clock Sleep Enable Disable Status\r\n  * @brief  Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode.\r\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r\n  *         power consumption.\r\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r\n  * @{\r\n  */\r\n  \r\n/** @brief  Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.\r\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r\n  *         power consumption.\r\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.  \r\n  */\r\n#define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET)\r\n#define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED()        ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET)\r\n#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET)\r\n#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET)\r\n#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET)\r\n#define __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED()       ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET)\r\n#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED()       ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET)\r\n#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET)\r\n#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET)\r\n#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED()   ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET)\r\n#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED()   ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET)\r\n#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED()  ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET)\r\n#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET)\r\n#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET)\r\n#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET)\r\n#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET)\r\n#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET)\r\n#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET)\r\n#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET)\r\n#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET)\r\n#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET)\r\n#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET)\r\n#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET)\r\n#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET)\r\n#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET)\r\n\r\n#define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET)\r\n#define __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED()       ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET)\r\n#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET)\r\n#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET)\r\n#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED()   ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET)\r\n#define __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET)\r\n#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET)\r\n#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET)\r\n#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED()    ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET)\r\n#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED()  ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET)\r\n#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED()  ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET)\r\n#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET)\r\n#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET)\r\n#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET)\r\n#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET)\r\n#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET)\r\n#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET)\r\n#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET)\r\n#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET)\r\n#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET)\r\n#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET)\r\n#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET)\r\n#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET)\r\n#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET)\r\n#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED()     ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET)\r\n\r\n/** @brief  Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode.\r\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r\n  *         power consumption.\r\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r\n  */\r\n#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED()        ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET)\r\n#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED()       ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET)\r\n\r\n#if defined(STM32F767xx) || defined(STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) \r\n#define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED()        ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) != RESET)\r\n#define __HAL_RCC_JPEG_IS_CLK_SLEEP_DISABLED()       ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) == RESET)\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n                                         \r\n#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED()         ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET)\r\n#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED()        ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET)\r\n\r\n#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED()  ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET)\r\n#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET)\r\n\r\n#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) \r\n#define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED()        ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET)\r\n#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED()        ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET)\r\n                                         \r\n#define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED()       ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET)\r\n#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED()       ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET)\r\n#endif /* STM32F756xx || STM32F777xx || STM32F779xx */\r\n\r\n/** @brief  Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode.\r\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r\n  *         power consumption.\r\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r\n  */\r\n#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED()  ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET)\r\n#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET)\r\n\r\n#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED()  ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET)\r\n#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET)\r\n\r\n/** @brief  Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.\r\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r\n  *         power consumption.\r\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r\n  */  \r\n#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET)\r\n#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET)\r\n#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET)\r\n#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET)\r\n#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET)\r\n#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET)\r\n#define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET)\r\n#define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET)\r\n#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET)\r\n#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET)\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED()     ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) != RESET)\r\n#define __HAL_RCC_CAN3_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) != RESET)\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET)\r\n#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET)\r\n#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET)\r\n#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET)\r\n#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET)\r\n#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET)\r\n#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET)\r\n#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET)\r\n#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET)\r\n#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET)\r\n#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET)\r\n#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET)\r\n#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET)\r\n#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED()     ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET)\r\n#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED()     ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET)\r\n#define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET)\r\n#define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET)\r\n\r\n#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET)\r\n#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET)\r\n#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET)\r\n#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET)\r\n#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET)\r\n#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET)\r\n#define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET)\r\n#define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET)\r\n#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET)\r\n#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET)\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) == RESET)\r\n#define __HAL_RCC_CAN3_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) == RESET)\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET)\r\n#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET)\r\n#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET)\r\n#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET)\r\n#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET)\r\n#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET)\r\n#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET)\r\n#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET)\r\n#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET)\r\n#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET)\r\n#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET)\r\n#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET)\r\n#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED()   ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET)\r\n#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET)\r\n#define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED()    ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET)\r\n#define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET)\r\n#define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED()  ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET)\r\n\r\n/** @brief  Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.\r\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\r\n  *         power consumption.\r\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\r\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\r\n  */ \r\n#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET)\r\n#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET)\r\n#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED()  ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET)\r\n#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED()  ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET)\r\n#define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET)\r\n#define __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET)\r\n#define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET)\r\n#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED()  ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET)\r\n#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET)\r\n#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET)\r\n#define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET)\r\n#define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET)\r\n#define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET)\r\n#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET)\r\n#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET)\r\n#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET)\r\n#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET)\r\n#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET)\r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n#if defined (STM32F769xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED()     ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) != RESET)\r\n#endif /* STM32F769xx || STM32F779xx */\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED()  ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) != RESET)\r\n#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != RESET)\r\n#define __HAL_RCC_MDIO_IS_CLK_SLEEP_ENABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) != RESET)\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET)\r\n#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET)\r\n#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET)\r\n#define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET)\r\n#define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET)\r\n#define __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET)\r\n#define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET)\r\n#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET)\r\n#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET)\r\n#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET)\r\n#define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET)\r\n#define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED()  ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET)\r\n#define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED()  ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET)\r\n#define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET)\r\n#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET)\r\n#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET)\r\n#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET)\r\n#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET)\r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n#if defined (STM32F769xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED()     ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) == RESET)\r\n#endif /* STM32F769xx || STM32F779xx */\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED()  ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) == RESET)\r\n#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED()   ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == RESET)\r\n#define __HAL_RCC_MDIO_IS_CLK_SLEEP_DISABLED()    ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) == RESET)\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/*------------------------------- PLL Configuration --------------------------*/\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n/** @brief  Macro to configure the main PLL clock source, multiplication and division factors.\r\n  * @note   This function must be used only when the main PLL is disabled.\r\n  * @param  __RCC_PLLSource__: specifies the PLL entry clock source.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry\r\n  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry\r\n  * @note   This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.  \r\n  * @param  __PLLM__: specifies the division factor for PLL VCO input clock\r\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.\r\n  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input\r\n  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency\r\n  *         of 2 MHz to limit PLL jitter.\r\n  * @param  __PLLN__: specifies the multiplication factor for PLL VCO output clock\r\n  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.\r\n  * @note   You have to set the PLLN parameter correctly to ensure that the VCO\r\n  *         output frequency is between 100 and 432 MHz.\r\n  * @param  __PLLP__: specifies the division factor for main system clock (SYSCLK)\r\n  *         This parameter must be a number in the range {2, 4, 6, or 8}.\r\n  * @note   You have to set the PLLP parameter correctly to not exceed 216 MHz on\r\n  *         the System clock frequency.\r\n  * @param  __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks\r\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.\r\n  * @note   If the USB OTG FS is used in your application, you have to set the\r\n  *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,\r\n  *         the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work\r\n  *         correctly.\r\n  * @param  __PLLR__: specifies the division factor for DSI clock\r\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.\r\n  */\r\n#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__)  \\\r\n                            (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__)                   | \\\r\n                            ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN))                      | \\\r\n                            ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP))          | \\\r\n                            ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))                      | \\\r\n                            ((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR))))\r\n#else\r\n/** @brief  Macro to configure the main PLL clock source, multiplication and division factors.\r\n  * @note   This function must be used only when the main PLL is disabled.\r\n  * @param  __RCC_PLLSource__: specifies the PLL entry clock source.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry\r\n  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry\r\n  * @note   This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.  \r\n  * @param  __PLLM__: specifies the division factor for PLL VCO input clock\r\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.\r\n  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input\r\n  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency\r\n  *         of 2 MHz to limit PLL jitter.\r\n  * @param  __PLLN__: specifies the multiplication factor for PLL VCO output clock\r\n  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.\r\n  * @note   You have to set the PLLN parameter correctly to ensure that the VCO\r\n  *         output frequency is between 100 and 432 MHz.\r\n  * @param  __PLLP__: specifies the division factor for main system clock (SYSCLK)\r\n  *         This parameter must be a number in the range {2, 4, 6, or 8}.\r\n  * @note   You have to set the PLLP parameter correctly to not exceed 216 MHz on\r\n  *         the System clock frequency.\r\n  * @param  __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks\r\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.\r\n  * @note   If the USB OTG FS is used in your application, you have to set the\r\n  *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,\r\n  *         the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work\r\n  *         correctly.\r\n  */\r\n#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)     \\\r\n                            (RCC->PLLCFGR = (0x20000000 | (__RCC_PLLSource__) | (__PLLM__)| \\\r\n                            ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN))                | \\\r\n                            ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP))    | \\\r\n                            ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ \r\n/*---------------------------------------------------------------------------------------------*/\r\n\r\n/** @brief  Macro to configure the Timers clocks prescalers \r\n  * @param  __PRESC__ : specifies the Timers clocks prescalers selection\r\n  *         This parameter can be one of the following values:\r\n  *            @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is \r\n  *                 equal to HPRE if PPREx is corresponding to division by 1 or 2, \r\n  *                 else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to \r\n  *                 division by 4 or more.       \r\n  *            @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is \r\n  *                 equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, \r\n  *                 else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding \r\n  *                 to division by 8 or more.\r\n  */     \r\n#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\\\r\n                                                 RCC->DCKCFGR1 |= (__PRESC__);           \\\r\n                                                }while(0)\r\n\r\n/** @brief Macros to Enable or Disable the PLLISAI. \r\n  * @note  The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. \r\n  */\r\n#define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR |= (RCC_CR_PLLSAION))\r\n#define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION))\r\n\r\n/** @brief  Macro to configure the PLLSAI clock multiplication and division factors.\r\n  * @note   This function must be used only when the PLLSAI is disabled.\r\n  * @note   PLLSAI clock source is common with the main PLL (configured in \r\n  *         RCC_PLLConfig function )\r\n  * @param  __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.\r\n  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.\r\n  * @note   You have to set the PLLSAIN parameter correctly to ensure that the VCO \r\n  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.\r\n  * @param  __PLLSAIP__: specifies the division factor for USB, RNG, SDMMC clocks\r\n  *         This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider.                                                  \r\n  * @param  __PLLSAIQ__: specifies the division factor for SAI clock\r\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.\r\n  * @param  __PLLSAIR__: specifies the division factor for LTDC clock\r\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.\r\n  */   \r\n#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__)                        \\\r\n                               (RCC->PLLSAICFGR = ((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) |\\\r\n                               ((__PLLSAIP__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP))                    |\\\r\n                               ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ))                    |\\\r\n                               ((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)))\r\n\r\n/** @brief  Macro to configure the PLLI2S clock multiplication and division factors.\r\n  * @note   This macro must be used only when the PLLI2S is disabled.\r\n  * @note   PLLI2S clock source is common with the main PLL (configured in \r\n  *         HAL_RCC_ClockConfig() API)             \r\n  * @param  __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.\r\n  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.\r\n  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO \r\n  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.\r\n  * @param  __PLLI2SP__: specifies the division factor for SPDDIF-RX clock.\r\n  *         This parameter can be a value of @ref RCCEx_PLLI2SP_Clock_Divider.                                 \r\n  * @param  __PLLI2SQ__: specifies the division factor for SAI clock.\r\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15. \r\n  * @param  __PLLI2SR__: specifies the division factor for I2S clock\r\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.\r\n  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz\r\n  *         on the I2S clock frequency. \r\n  */\r\n#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__)                        \\\r\n                               (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\\\r\n                               ((__PLLI2SP__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP))                    |\\\r\n                               ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ))                    |\\\r\n                               ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))\r\n    \r\n/** @brief  Macro to configure the SAI clock Divider coming from PLLI2S.\r\n  * @note   This function must be called before enabling the PLLI2S.          \r\n  * @param  __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .\r\n  *          This parameter must be a number between 1 and 32.\r\n  *          SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ \r\n  */\r\n#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))\r\n\r\n/** @brief  Macro to configure the SAI clock Divider coming from PLLSAI.\r\n  * @note   This function must be called before enabling the PLLSAI.\r\n  * @param  __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .\r\n  *         This parameter must be a number between Min_Data = 1 and Max_Data = 32.\r\n  *         SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__  \r\n  */\r\n#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))\r\n\r\n/** @brief  Macro to configure the LTDC clock Divider coming from PLLSAI.\r\n  * \r\n  * @note   This function must be called before enabling the PLLSAI. \r\n  * @param  __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .\r\n  *          This parameter can be a value of @ref RCCEx_PLLSAI_DIVR.\r\n  *          LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ \r\n  */   \r\n#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\\\r\n                            MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__))\r\n\r\n/** @brief  Macro to configure SAI1 clock source selection.\r\n  * @note   This function must be called before enabling PLLSAI, PLLI2S and  \r\n  *         the SAI clock.\r\n  * @param  __SOURCE__: specifies the SAI1 clock source.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used \r\n  *                                           as SAI1 clock. \r\n  *            @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used \r\n  *                                           as SAI1 clock.\r\n  *            @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin\r\n  *                                        used as SAI1 clock.\r\n  *            @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock \r\n  *                                           used as SAI1 clock.\r\n  * @note      The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices                               \r\n  */\r\n#define __HAL_RCC_SAI1_CONFIG(__SOURCE__)\\\r\n                             MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__))\r\n\r\n/** @brief  Macro to get the SAI1 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used \r\n  *                                           as SAI1 clock. \r\n  *            @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used \r\n  *                                           as SAI1 clock.\r\n  *            @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin\r\n  *                                        used as SAI1 clock.\r\n  *            @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock \r\n  *                                           used as SAI1 clock.\r\n  * @note      The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices                               \r\n  */\r\n#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL)))\r\n\r\n\r\n/** @brief  Macro to configure SAI2 clock source selection.\r\n  * @note   This function must be called before enabling PLLSAI, PLLI2S and  \r\n  *         the SAI clock.\r\n  * @param  __SOURCE__: specifies the SAI2 clock source.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used \r\n  *                                           as SAI2 clock. \r\n  *            @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used \r\n  *                                           as SAI2 clock. \r\n  *            @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin\r\n  *                                        used as SAI2 clock.\r\n  *            @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock \r\n  *                                           used as SAI2 clock.\r\n  * @note      The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices                                \r\n  */\r\n#define __HAL_RCC_SAI2_CONFIG(__SOURCE__)\\\r\n                            MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__))\r\n\r\n\r\n/** @brief  Macro to get the SAI2 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used \r\n  *                                           as SAI2 clock. \r\n  *            @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used \r\n  *                                           as SAI2 clock.\r\n  *            @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin\r\n  *                                        used as SAI2 clock.\r\n  *            @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock \r\n  *                                           used as SAI2 clock.\r\n  * @note      The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices                              \r\n  */\r\n#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL)))\r\n\r\n\r\n/** @brief Enable PLLSAI_RDY interrupt.\r\n  */\r\n#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))\r\n\r\n/** @brief Disable PLLSAI_RDY interrupt.\r\n  */\r\n#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))\r\n\r\n/** @brief Clear the PLLSAI RDY interrupt pending bits.\r\n  */\r\n#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))\r\n\r\n/** @brief Check the PLLSAI RDY interrupt has occurred or not.\r\n  * @retval The new state (TRUE or FALSE).\r\n  */\r\n#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))\r\n\r\n/** @brief  Check PLLSAI RDY flag is set or not.\r\n  * @retval The new state (TRUE or FALSE).\r\n  */\r\n#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))\r\n\r\n/** @brief  Macro to Get I2S clock source selection.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. \r\n  *            @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source\r\n  */\r\n#define __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))\r\n\r\n/** @brief  Macro to configure the I2C1 clock (I2C1CLK).\r\n  *\r\n  * @param  __I2C1_CLKSOURCE__: specifies the I2C1 clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock\r\n  *            @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock\r\n  *            @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock\r\n  */\r\n#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))\r\n\r\n/** @brief  Macro to get the I2C1 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock\r\n  *            @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock\r\n  *            @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock\r\n  */\r\n#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL)))\r\n\r\n/** @brief  Macro to configure the I2C2 clock (I2C2CLK).\r\n  *\r\n  * @param  __I2C2_CLKSOURCE__: specifies the I2C2 clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock\r\n  *            @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock\r\n  *            @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock\r\n  */\r\n#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))\r\n\r\n/** @brief  Macro to get the I2C2 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock\r\n  *            @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock\r\n  *            @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock\r\n  */\r\n#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL)))\r\n\r\n/** @brief  Macro to configure the I2C3 clock (I2C3CLK).\r\n  *\r\n  * @param  __I2C3_CLKSOURCE__: specifies the I2C3 clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock\r\n  *            @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock\r\n  *            @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock\r\n  */\r\n#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))\r\n\r\n/** @brief  macro to get the I2C3 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock\r\n  *            @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock\r\n  *            @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock\r\n  */\r\n#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL)))\r\n\r\n/** @brief  Macro to configure the I2C4 clock (I2C4CLK).\r\n  *\r\n  * @param  __I2C4_CLKSOURCE__: specifies the I2C4 clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock\r\n  *            @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock\r\n  *            @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock\r\n  */\r\n#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__))\r\n\r\n/** @brief  macro to get the I2C4 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock\r\n  *            @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock\r\n  *            @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock\r\n  */\r\n#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL)))\r\n\r\n/** @brief  Macro to configure the USART1 clock (USART1CLK).\r\n  *\r\n  * @param  __USART1_CLKSOURCE__: specifies the USART1 clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock\r\n  *            @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock\r\n  *            @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock\r\n  *            @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock\r\n  */\r\n#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))\r\n\r\n/** @brief  macro to get the USART1 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock\r\n  *            @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock\r\n  *            @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock\r\n  *            @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock\r\n  */\r\n#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL)))\r\n\r\n/** @brief  Macro to configure the USART2 clock (USART2CLK).\r\n  *\r\n  * @param  __USART2_CLKSOURCE__: specifies the USART2 clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock\r\n  *            @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock\r\n  *            @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock\r\n  *            @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock\r\n  */\r\n#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))\r\n\r\n/** @brief  macro to get the USART2 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock\r\n  *            @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock\r\n  *            @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock\r\n  *            @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock\r\n  */\r\n#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL)))\r\n\r\n/** @brief  Macro to configure the USART3 clock (USART3CLK).\r\n  *\r\n  * @param  __USART3_CLKSOURCE__: specifies the USART3 clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock\r\n  *            @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock\r\n  *            @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock\r\n  *            @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock\r\n  */\r\n#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))\r\n\r\n/** @brief  macro to get the USART3 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock\r\n  *            @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock\r\n  *            @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock\r\n  *            @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock\r\n  */\r\n#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL)))\r\n\r\n /** @brief  Macro to configure the UART4 clock (UART4CLK).\r\n  *\r\n  * @param  __UART4_CLKSOURCE__: specifies the UART4 clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock\r\n  *            @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock\r\n  *            @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock\r\n  *            @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock\r\n  */\r\n#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))\r\n\r\n/** @brief  macro to get the UART4 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock\r\n  *            @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock\r\n  *            @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock\r\n  *            @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock\r\n  */\r\n#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL)))\r\n\r\n /** @brief  Macro to configure the UART5 clock (UART5CLK).\r\n  *\r\n  * @param  __UART5_CLKSOURCE__: specifies the UART5 clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock\r\n  *            @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock\r\n  *            @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock\r\n  *            @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock\r\n  */\r\n#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))\r\n\r\n/** @brief  macro to get the UART5 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock\r\n  *            @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock\r\n  *            @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock\r\n  *            @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock\r\n  */\r\n#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL)))\r\n\r\n /** @brief  Macro to configure the USART6 clock (USART6CLK).\r\n  *\r\n  * @param  __USART6_CLKSOURCE__: specifies the USART6 clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock\r\n  *            @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock\r\n  *            @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock\r\n  *            @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock\r\n  */\r\n#define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__))\r\n\r\n/** @brief  macro to get the USART6 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock\r\n  *            @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock\r\n  *            @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock\r\n  *            @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock\r\n  */\r\n#define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL)))\r\n\r\n /** @brief  Macro to configure the UART7 clock (UART7CLK).\r\n  *\r\n  * @param  __UART7_CLKSOURCE__: specifies the UART7 clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock\r\n  *            @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock\r\n  *            @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock\r\n  *            @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock\r\n  */\r\n#define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__))\r\n\r\n/** @brief  macro to get the UART7 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock\r\n  *            @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock\r\n  *            @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock\r\n  *            @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock\r\n  */\r\n#define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL)))\r\n\r\n/** @brief  Macro to configure the UART8 clock (UART8CLK).\r\n  *\r\n  * @param  __UART8_CLKSOURCE__: specifies the UART8 clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock\r\n  *            @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock\r\n  *            @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock\r\n  *            @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock\r\n  */\r\n#define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__))\r\n\r\n/** @brief  macro to get the UART8 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock\r\n  *            @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock\r\n  *            @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock\r\n  *            @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock\r\n  */\r\n#define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL)))\r\n\r\n/** @brief  Macro to configure the LPTIM1 clock (LPTIM1CLK).\r\n  *\r\n  * @param  __LPTIM1_CLKSOURCE__: specifies the LPTIM1 clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock\r\n  *            @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock\r\n  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock\r\n  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock\r\n  */\r\n#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))\r\n\r\n/** @brief  macro to get the LPTIM1 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock\r\n  *            @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock\r\n  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock\r\n  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock\r\n  */\r\n#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)))\r\n\r\n/** @brief  Macro to configure the CEC clock (CECCLK).\r\n  *\r\n  * @param  __CEC_CLKSOURCE__: specifies the CEC clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock\r\n  *            @arg RCC_CECCLKSOURCE_HSI: HSI divided by 488 selected as CEC clock\r\n  */\r\n#define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__))\r\n\r\n/** @brief  macro to get the CEC clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock\r\n  *            @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock\r\n  */\r\n#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)))\r\n\r\n/** @brief  Macro to configure the CLK48 source (CLK48CLK).\r\n  *\r\n  * @param  __CLK48_SOURCE__: specifies the CLK48 clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source\r\n  *            @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP selected as CLK48 source\r\n  */\r\n#define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__))\r\n\r\n/** @brief  macro to get the CLK48 source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_CLK48SOURCE_PLL: PLL used as CLK48 source\r\n  *            @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP used as CLK48 source\r\n  */\r\n#define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)))\r\n\r\n/** @brief  Macro to configure the SDMMC1 clock (SDMMC1CLK).\r\n  *\r\n  * @param  __SDMMC1_CLKSOURCE__: specifies the SDMMC1 clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC clock\r\n  *            @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC clock\r\n  */\r\n#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))\r\n\r\n/** @brief  macro to get the SDMMC1 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC1 clock\r\n  *            @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC1 clock\r\n  */\r\n#define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL)))\r\n\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)                    \r\n/** @brief  Macro to configure the SDMMC2 clock (SDMMC2CLK).\r\n  * @param  __SDMMC2_CLKSOURCE__: specifies the SDMMC2 clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock\r\n  *            @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock\r\n  */\r\n#define __HAL_RCC_SDMMC2_CONFIG(__SDMMC2_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL, (uint32_t)(__SDMMC2_CLKSOURCE__))\r\n\r\n/** @brief  macro to get the SDMMC2 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock\r\n  *            @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock\r\n  */\r\n#define __HAL_RCC_GET_SDMMC2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL)))\r\n                    \r\n/** @brief  Macro to configure the DFSDM1 clock\r\n  * @param  __DFSDM1_CLKSOURCE__: specifies the DFSDM1  clock source.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg RCC_DFSDM1CLKSOURCE_PCLK: PCLK2 Clock selected as DFSDM clock\r\n  *            @arg RCC_DFSDMCLKSOURCE_SYSCLK: System Clock selected as DFSDM clock\r\n  */\r\n#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__))\r\n\r\n/** @brief  Macro to get the DFSDM1 clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_DFSDM1CLKSOURCE_PCLK:  PCLK2 Clock selected as DFSDM1 clock\r\n  *            @arg RCC_DFSDM1CLKSOURCE_SYSCLK:   System Clock selected as DFSDM1 clock\r\n  */\r\n#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL)))\r\n\r\n/** @brief  Macro to configure the DFSDM1 Audio clock\r\n  * @param  __DFSDM1AUDIO_CLKSOURCE__: specifies the DFSDM1 Audio clock source.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1:  SAI1 Clock selected as DFSDM1 Audio clock\r\n  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2:  SAI2 Clock selected as DFSDM1 Audio clock\r\n  */\r\n#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \\\r\n                  MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, (uint32_t)(__DFSDM1AUDIO_CLKSOURCE__))\r\n\r\n/** @brief  Macro to get the DFSDM1 Audio clock source.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1:  SAI1 Clock selected as DFSDM1 Audio clock\r\n  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2:  SAI2 Clock selected as DFSDM1 Audio clock\r\n  */\r\n#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL)))                   \r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n#if defined (STM32F769xx) || defined (STM32F779xx)\r\n/** @brief  Macro to configure the DSI clock.\r\n  * @param  __DSI_CLKSOURCE__: specifies the DSI clock source.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. \r\n  *            @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. \r\n  */\r\n#define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, (uint32_t)(__DSI_CLKSOURCE__)))\r\n\r\n/** @brief  Macro to Get the DSI clock.\r\n  * @retval The clock source can be one of the following values:\r\n  *            @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. \r\n  *            @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. \r\n  */\r\n#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL))                    \r\n#endif /* STM32F769xx || STM32F779xx */                    \r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup RCCEx_Exported_Functions_Group1\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);\r\nvoid HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);\r\nuint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n/* Private macros ------------------------------------------------------------*/\r\n/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros\r\n  * @{\r\n  */\r\n/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters\r\n  * @{\r\n  */\r\n#if defined(STM32F756xx) || defined(STM32F746xx)\r\n#define IS_RCC_PERIPHCLOCK(SELECTION)  \\\r\n               ((((SELECTION) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_LTDC)        == RCC_PERIPHCLK_LTDC)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_TIM)         == RCC_PERIPHCLK_TIM)     || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART6)      == RCC_PERIPHCLK_USART6)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART7)       == RCC_PERIPHCLK_UART7)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART8)       == RCC_PERIPHCLK_UART8)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_I2C4)        == RCC_PERIPHCLK_I2C4)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SAI2)        == RCC_PERIPHCLK_SAI2)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_CLK48)       == RCC_PERIPHCLK_CLK48)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_CEC)         == RCC_PERIPHCLK_CEC)     || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SDMMC1)      == RCC_PERIPHCLK_SDMMC1)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SPDIFRX)     == RCC_PERIPHCLK_SPDIFRX) || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC))\r\n#elif defined(STM32F745xx)\r\n#define IS_RCC_PERIPHCLOCK(SELECTION)  \\\r\n               ((((SELECTION) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_TIM)         == RCC_PERIPHCLK_TIM)     || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART6)      == RCC_PERIPHCLK_USART6)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART7)       == RCC_PERIPHCLK_UART7)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART8)       == RCC_PERIPHCLK_UART8)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_I2C4)        == RCC_PERIPHCLK_I2C4)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SAI2)        == RCC_PERIPHCLK_SAI2)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_CLK48)       == RCC_PERIPHCLK_CLK48)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_CEC)         == RCC_PERIPHCLK_CEC)     || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SDMMC1)      == RCC_PERIPHCLK_SDMMC1)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SPDIFRX)     == RCC_PERIPHCLK_SPDIFRX) || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC))\r\n#elif defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define IS_RCC_PERIPHCLOCK(SELECTION)  \\\r\n               ((((SELECTION) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_LTDC)        == RCC_PERIPHCLK_LTDC)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_TIM)         == RCC_PERIPHCLK_TIM)     || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART6)      == RCC_PERIPHCLK_USART6)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART7)       == RCC_PERIPHCLK_UART7)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART8)       == RCC_PERIPHCLK_UART8)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_I2C4)        == RCC_PERIPHCLK_I2C4)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SAI2)        == RCC_PERIPHCLK_SAI2)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_CLK48)       == RCC_PERIPHCLK_CLK48)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_CEC)         == RCC_PERIPHCLK_CEC)     || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SDMMC1)      == RCC_PERIPHCLK_SDMMC1)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SDMMC2)      == RCC_PERIPHCLK_SDMMC2)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_DFSDM1)       == RCC_PERIPHCLK_DFSDM1)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SPDIFRX)     == RCC_PERIPHCLK_SPDIFRX) || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC))                \r\n#elif defined (STM32F765xx)\r\n#define IS_RCC_PERIPHCLOCK(SELECTION)  \\\r\n               ((((SELECTION) & RCC_PERIPHCLK_I2S)         == RCC_PERIPHCLK_I2S)     || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_TIM)         == RCC_PERIPHCLK_TIM)     || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART1)      == RCC_PERIPHCLK_USART1)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART2)      == RCC_PERIPHCLK_USART2)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART3)      == RCC_PERIPHCLK_USART3)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART4)       == RCC_PERIPHCLK_UART4)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART5)       == RCC_PERIPHCLK_UART5)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_USART6)      == RCC_PERIPHCLK_USART6)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART7)       == RCC_PERIPHCLK_UART7)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_UART8)       == RCC_PERIPHCLK_UART8)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_I2C1)        == RCC_PERIPHCLK_I2C1)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_I2C2)        == RCC_PERIPHCLK_I2C2)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_I2C3)        == RCC_PERIPHCLK_I2C3)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_I2C4)        == RCC_PERIPHCLK_I2C4)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_LPTIM1)      == RCC_PERIPHCLK_LPTIM1)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SAI1)        == RCC_PERIPHCLK_SAI1)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SAI2)        == RCC_PERIPHCLK_SAI2)    || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_CLK48)       == RCC_PERIPHCLK_CLK48)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_CEC)         == RCC_PERIPHCLK_CEC)     || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SDMMC1)      == RCC_PERIPHCLK_SDMMC1)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SDMMC2)      == RCC_PERIPHCLK_SDMMC2)  || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_DFSDM1)       == RCC_PERIPHCLK_DFSDM1)   || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_SPDIFRX)     == RCC_PERIPHCLK_SPDIFRX) || \\\r\n                (((SELECTION) & RCC_PERIPHCLK_RTC)         == RCC_PERIPHCLK_RTC)) \r\n#endif /* STM32F746xx || STM32F756xx */\r\n#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))\r\n#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\\\r\n                                     ((VALUE) == RCC_PLLI2SP_DIV4) ||\\\r\n                                     ((VALUE) == RCC_PLLI2SP_DIV6) ||\\\r\n                                     ((VALUE) == RCC_PLLI2SP_DIV8))                 \r\n#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))\r\n#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))\r\n\r\n#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))\r\n#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\\\r\n                                     ((VALUE) == RCC_PLLSAIP_DIV4) ||\\\r\n                                     ((VALUE) == RCC_PLLSAIP_DIV6) ||\\\r\n                                     ((VALUE) == RCC_PLLSAIP_DIV8))\r\n#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))\r\n#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))  \r\n\r\n#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))\r\n\r\n#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))\r\n\r\n#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\\\r\n                                         ((VALUE) == RCC_PLLSAIDIVR_4) ||\\\r\n                                         ((VALUE) == RCC_PLLSAIDIVR_8) ||\\\r\n                                         ((VALUE) == RCC_PLLSAIDIVR_16))\r\n#define IS_RCC_I2SCLKSOURCE(SOURCE)  (((SOURCE) == RCC_I2SCLKSOURCE_PLLI2S) || \\\r\n                                      ((SOURCE) == RCC_I2SCLKSOURCE_EXT))\r\n\r\n#define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) || \\\r\n                                        ((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48))\r\n\r\n#define IS_RCC_CECCLKSOURCE(SOURCE)  (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \\\r\n                                      ((SOURCE) == RCC_CECCLKSOURCE_LSE))\r\n#define IS_RCC_USART1CLKSOURCE(SOURCE)  \\\r\n               (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2)  || \\\r\n                ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \\\r\n                ((SOURCE) == RCC_USART1CLKSOURCE_LSE)    || \\\r\n                ((SOURCE) == RCC_USART1CLKSOURCE_HSI))\r\n\r\n#define IS_RCC_USART2CLKSOURCE(SOURCE)  \\\r\n               (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1)  || \\\r\n                ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \\\r\n                ((SOURCE) == RCC_USART2CLKSOURCE_LSE)    || \\\r\n                ((SOURCE) == RCC_USART2CLKSOURCE_HSI))\r\n#define IS_RCC_USART3CLKSOURCE(SOURCE)  \\\r\n               (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1)  || \\\r\n                ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \\\r\n                ((SOURCE) == RCC_USART3CLKSOURCE_LSE)    || \\\r\n                ((SOURCE) == RCC_USART3CLKSOURCE_HSI))\r\n\r\n#define IS_RCC_UART4CLKSOURCE(SOURCE)  \\\r\n               (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1)  || \\\r\n                ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \\\r\n                ((SOURCE) == RCC_UART4CLKSOURCE_LSE)    || \\\r\n                ((SOURCE) == RCC_UART4CLKSOURCE_HSI))\r\n\r\n#define IS_RCC_UART5CLKSOURCE(SOURCE)  \\\r\n               (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1)  || \\\r\n                ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \\\r\n                ((SOURCE) == RCC_UART5CLKSOURCE_LSE)    || \\\r\n                ((SOURCE) == RCC_UART5CLKSOURCE_HSI))\r\n\r\n#define IS_RCC_USART6CLKSOURCE(SOURCE)  \\\r\n               (((SOURCE) == RCC_USART6CLKSOURCE_PCLK2)  || \\\r\n                ((SOURCE) == RCC_USART6CLKSOURCE_SYSCLK) || \\\r\n                ((SOURCE) == RCC_USART6CLKSOURCE_LSE)    || \\\r\n                ((SOURCE) == RCC_USART6CLKSOURCE_HSI))\r\n\r\n#define IS_RCC_UART7CLKSOURCE(SOURCE)  \\\r\n               (((SOURCE) == RCC_UART7CLKSOURCE_PCLK1)  || \\\r\n                ((SOURCE) == RCC_UART7CLKSOURCE_SYSCLK) || \\\r\n                ((SOURCE) == RCC_UART7CLKSOURCE_LSE)    || \\\r\n                ((SOURCE) == RCC_UART7CLKSOURCE_HSI))\r\n\r\n#define IS_RCC_UART8CLKSOURCE(SOURCE)  \\\r\n               (((SOURCE) == RCC_UART8CLKSOURCE_PCLK1)  || \\\r\n                ((SOURCE) == RCC_UART8CLKSOURCE_SYSCLK) || \\\r\n                ((SOURCE) == RCC_UART8CLKSOURCE_LSE)    || \\\r\n                ((SOURCE) == RCC_UART8CLKSOURCE_HSI))\r\n#define IS_RCC_I2C1CLKSOURCE(SOURCE)   \\\r\n               (((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) || \\\r\n                ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)|| \\\r\n                ((SOURCE) == RCC_I2C1CLKSOURCE_HSI))\r\n#define IS_RCC_I2C2CLKSOURCE(SOURCE)   \\\r\n               (((SOURCE) == RCC_I2C2CLKSOURCE_PCLK1) || \\\r\n                ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)|| \\\r\n                ((SOURCE) == RCC_I2C2CLKSOURCE_HSI))\r\n\r\n#define IS_RCC_I2C3CLKSOURCE(SOURCE)   \\\r\n               (((SOURCE) == RCC_I2C3CLKSOURCE_PCLK1) || \\\r\n                ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)|| \\\r\n                ((SOURCE) == RCC_I2C3CLKSOURCE_HSI))\r\n#define IS_RCC_I2C4CLKSOURCE(SOURCE)   \\\r\n               (((SOURCE) == RCC_I2C4CLKSOURCE_PCLK1) || \\\r\n                ((SOURCE) == RCC_I2C4CLKSOURCE_SYSCLK)|| \\\r\n                ((SOURCE) == RCC_I2C4CLKSOURCE_HSI))\r\n#define IS_RCC_LPTIM1CLK(SOURCE)  \\\r\n               (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) || \\\r\n                ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI)  || \\\r\n                ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI)  || \\\r\n                ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))\r\n#define IS_RCC_CLK48SOURCE(SOURCE)  \\\r\n               (((SOURCE) == RCC_CLK48SOURCE_PLLSAIP) || \\\r\n                ((SOURCE) == RCC_CLK48SOURCE_PLL))\r\n#define IS_RCC_TIMPRES(VALUE)  \\\r\n               (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \\\r\n                ((VALUE) == RCC_TIMPRES_ACTIVATED))\r\n\r\n#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx)\r\n#define IS_RCC_SAI1CLKSOURCE(SOURCE)  (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \\\r\n                                       ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \\\r\n                                       ((SOURCE) == RCC_SAI1CLKSOURCE_PIN))\r\n#define IS_RCC_SAI2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \\\r\n                                       ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \\\r\n                                       ((SOURCE) == RCC_SAI2CLKSOURCE_PIN))\r\n#endif /* STM32F745xx || STM32F746xx || STM32F756xx */\r\n                 \r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define IS_RCC_PLLR_VALUE(VALUE)            ((2 <= (VALUE)) && ((VALUE) <= 7))\r\n                 \r\n#define IS_RCC_SAI1CLKSOURCE(SOURCE)  (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \\\r\n                                       ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \\\r\n                                       ((SOURCE) == RCC_SAI1CLKSOURCE_PIN)    || \\\r\n                                       ((SOURCE) == RCC_SAI1CLKSOURCE_PLLSRC))\r\n\r\n#define IS_RCC_SAI2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \\\r\n                                       ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \\\r\n                                       ((SOURCE) == RCC_SAI2CLKSOURCE_PIN)    || \\\r\n                                       ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))\r\n\r\n#define IS_RCC_SDMMC2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_SDMMC2CLKSOURCE_SYSCLK) || \\\r\n                                         ((SOURCE) == RCC_SDMMC2CLKSOURCE_CLK48))\r\n\r\n#define IS_RCC_DFSDM1CLKSOURCE(SOURCE)  (((SOURCE) == RCC_DFSDM1CLKSOURCE_PCLK) || \\\r\n                                        ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYSCLK))\r\n\r\n#define IS_RCC_DFSDM1AUDIOCLKSOURCE(SOURCE)  (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \\\r\n                                             ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI2))\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR)  ||\\\r\n                                             ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY))\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n                 \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_RCC_EX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rng.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_rng.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of RNG HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_RNG_H\r\n#define __STM32F7xx_HAL_RNG_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup RNG RNG\r\n  * @brief RNG HAL module driver\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/ \r\n\r\n/** @defgroup RNG_Exported_Types RNG Exported Types\r\n  * @{\r\n  */\r\n\r\n/** @defgroup RNG_Exported_Types_Group1 RNG State Structure definition \r\n  * @{\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_RNG_STATE_RESET     = 0x00U,  /*!< RNG not yet initialized or disabled */\r\n  HAL_RNG_STATE_READY     = 0x01U,  /*!< RNG initialized and ready for use   */\r\n  HAL_RNG_STATE_BUSY      = 0x02U,  /*!< RNG internal process is ongoing     */ \r\n  HAL_RNG_STATE_TIMEOUT   = 0x03U,  /*!< RNG timeout state                   */\r\n  HAL_RNG_STATE_ERROR     = 0x04U   /*!< RNG error state                     */\r\n    \r\n}HAL_RNG_StateTypeDef;\r\n\r\n/** \r\n  * @}\r\n  */\r\n\r\n/** @defgroup RNG_Exported_Types_Group2 RNG Handle Structure definition   \r\n  * @{\r\n  */ \r\ntypedef struct\r\n{\r\n  RNG_TypeDef                 *Instance;    /*!< Register base address   */\r\n\r\n  uint32_t                    RandomNumber; /*!< Last Generated random number */\t\r\n  \r\n  HAL_LockTypeDef             Lock;         /*!< RNG locking object      */\r\n  \r\n  __IO HAL_RNG_StateTypeDef   State;        /*!< RNG communication state */\r\n  \r\n}RNG_HandleTypeDef;\r\n\r\n/** \r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n   \r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup RNG_Exported_Constants RNG Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition\r\n  * @{\r\n  */\r\n#define RNG_IT_DRDY  RNG_SR_DRDY  /*!< Data Ready interrupt  */\r\n#define RNG_IT_CEI   RNG_SR_CEIS  /*!< Clock error interrupt */\r\n#define RNG_IT_SEI   RNG_SR_SEIS  /*!< Seed error interrupt  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition\r\n  * @{\r\n  */\r\n#define RNG_FLAG_DRDY   RNG_SR_DRDY  /*!< Data ready                 */\r\n#define RNG_FLAG_CECS   RNG_SR_CECS  /*!< Clock error current status */\r\n#define RNG_FLAG_SECS   RNG_SR_SECS  /*!< Seed error current status  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/* Exported macros -----------------------------------------------------------*/\r\n\r\n/** @defgroup RNG_Exported_Macros RNG Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief Reset RNG handle state\r\n  * @param  __HANDLE__: RNG Handle\r\n  * @retval None\r\n  */\r\n#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)\r\n\r\n/**\r\n  * @brief  Enables the RNG peripheral.\r\n  * @param  __HANDLE__: RNG Handle\r\n  * @retval None\r\n  */\r\n#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_RNGEN)\r\n\r\n/**\r\n  * @brief  Disables the RNG peripheral.\r\n  * @param  __HANDLE__: RNG Handle\r\n  * @retval None\r\n  */\r\n#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)\r\n\r\n/**\r\n  * @brief  Check the selected RNG flag status.\r\n  * @param  __HANDLE__: RNG Handle\r\n  * @param  __FLAG__: RNG flag\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RNG_FLAG_DRDY: Data ready                \r\n  *            @arg RNG_FLAG_CECS: Clock error current status\r\n  *            @arg RNG_FLAG_SECS: Seed error current status \r\n  * @retval The new state of __FLAG__ (SET or RESET).\r\n  */\r\n#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))\r\n\r\n/**\r\n  * @brief  Clears the selected RNG flag status.\r\n  * @param  __HANDLE__: RNG handle\r\n  * @param  __FLAG__: RNG flag to clear  \r\n  * @note   WARNING: This is a dummy macro for HAL code alignment,\r\n  *         flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.\r\n  * @retval None\r\n  */\r\n#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__)                      /* dummy  macro */\r\n\r\n\r\n\r\n/**\r\n  * @brief  Enables the RNG interrupts.\r\n  * @param  __HANDLE__: RNG Handle\r\n  * @retval None\r\n  */\r\n#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_IE)\r\n    \r\n/**\r\n  * @brief  Disables the RNG interrupts.\r\n  * @param  __HANDLE__: RNG Handle\r\n  * @retval None\r\n  */\r\n#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)\r\n\r\n/**\r\n  * @brief  Checks whether the specified RNG interrupt has occurred or not.\r\n  * @param  __HANDLE__: RNG Handle\r\n  * @param  __INTERRUPT__: specifies the RNG interrupt status flag to check.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg RNG_IT_DRDY: Data ready interrupt              \r\n  *            @arg RNG_IT_CEI: Clock error interrupt\r\n  *            @arg RNG_IT_SEI: Seed error interrupt\r\n  * @retval The new state of __INTERRUPT__ (SET or RESET).\r\n  */\r\n#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))   \r\n\r\n/**\r\n  * @brief  Clear the RNG interrupt status flags.\r\n  * @param  __HANDLE__: RNG Handle\r\n  * @param  __INTERRUPT__: specifies the RNG interrupt status flag to clear.\r\n  *          This parameter can be one of the following values:            \r\n  *            @arg RNG_IT_CEI: Clock error interrupt\r\n  *            @arg RNG_IT_SEI: Seed error interrupt\r\n  * @note   RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.          \r\n  * @retval None\r\n  */\r\n#define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup RNG_Exported_Functions RNG Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup RNG_Exported_Functions_Group1 Initialization and de-initialization functions\r\n  * @{\r\n  */  \r\nHAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);\r\nHAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng);\r\nvoid HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);\r\nvoid HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions\r\n  * @{\r\n  */\r\nuint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng);    /* Obsolete, use HAL_RNG_GenerateRandomNumber() instead    */\r\nuint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */\r\n\r\nHAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);\r\nHAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);\r\nuint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);\r\n\r\nvoid HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);\r\nvoid HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);\r\nvoid HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef* hrng, uint32_t random32bit);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions\r\n  * @{\r\n  */\r\nHAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/** @defgroup RNG_Private_Types RNG Private Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private defines -----------------------------------------------------------*/\r\n/** @defgroup RNG_Private_Defines RNG Private Defines\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n          \r\n/* Private variables ---------------------------------------------------------*/\r\n/** @defgroup RNG_Private_Variables RNG Private Variables\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup RNG_Private_Constants RNG Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup RNG_Private_Macros RNG Private Macros\r\n  * @{\r\n  */\r\n#define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \\\r\n                       ((IT) == RNG_IT_SEI))\r\n\r\n#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \\\r\n                           ((FLAG) == RNG_FLAG_CECS) || \\\r\n                           ((FLAG) == RNG_FLAG_SECS))\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private functions prototypes ----------------------------------------------*/\r\n/** @defgroup RNG_Private_Functions_Prototypes RNG Private Functions Prototypes\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup RNG_Private_Functions RNG Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_RNG_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_rtc.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of RTC HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_RTC_H\r\n#define __STM32F7xx_HAL_RTC_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup RTC\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup RTC_Exported_Types RTC Exported Types\r\n  * @{\r\n  */\r\n\r\n/** \r\n  * @brief  HAL State structures definition  \r\n  */ \r\ntypedef enum\r\n{\r\n  HAL_RTC_STATE_RESET             = 0x00U,  /*!< RTC not yet initialized or disabled */\r\n  HAL_RTC_STATE_READY             = 0x01U,  /*!< RTC initialized and ready for use   */\r\n  HAL_RTC_STATE_BUSY              = 0x02U,  /*!< RTC process is ongoing              */     \r\n  HAL_RTC_STATE_TIMEOUT           = 0x03U,  /*!< RTC timeout state                   */  \r\n  HAL_RTC_STATE_ERROR             = 0x04U   /*!< RTC error state                     */      \r\n                                                                        \r\n}HAL_RTCStateTypeDef;\r\n\r\n/** \r\n  * @brief  RTC Configuration Structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t HourFormat;      /*!< Specifies the RTC Hour Format.\r\n                                 This parameter can be a value of @ref RTC_Hour_Formats */         \r\n\r\n  uint32_t AsynchPrediv;    /*!< Specifies the RTC Asynchronous Predivider value.\r\n                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */        \r\n                               \r\n  uint32_t SynchPrediv;     /*!< Specifies the RTC Synchronous Predivider value.\r\n                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */   \r\n  \r\n  uint32_t OutPut;          /*!< Specifies which signal will be routed to the RTC output.   \r\n                                 This parameter can be a value of @ref RTCEx_Output_selection_Definitions */      \r\n  \r\n  uint32_t OutPutPolarity;  /*!< Specifies the polarity of the output signal.  \r\n                                 This parameter can be a value of @ref RTC_Output_Polarity_Definitions */ \r\n  \r\n  uint32_t OutPutType;      /*!< Specifies the RTC Output Pin mode.   \r\n                                 This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */             \r\n}RTC_InitTypeDef;\r\n\r\n/** \r\n  * @brief  RTC Time structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint8_t Hours;            /*!< Specifies the RTC Time Hour.\r\n                                 This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.\r\n                                 This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected  */\r\n\r\n  uint8_t Minutes;          /*!< Specifies the RTC Time Minutes.\r\n                                 This parameter must be a number between Min_Data = 0 and Max_Data = 59 */\r\n  \r\n  uint8_t Seconds;          /*!< Specifies the RTC Time Seconds.\r\n                                 This parameter must be a number between Min_Data = 0 and Max_Data = 59 */\r\n  \r\n  uint32_t SubSeconds;      /*!< Specifies the RTC_SSR RTC Sub Second register content.\r\n                                 This parameter corresponds to a time unit range between [0-1] Second\r\n                                 with [1 Sec / SecondFraction +1] granularity */\r\n  \r\n  uint32_t SecondFraction;  /*!< Specifies the range or granularity of Sub Second register content\r\n                                 corresponding to Synchronous pre-scaler factor value (PREDIV_S)\r\n                                 This parameter corresponds to a time unit range between [0-1] Second\r\n                                 with [1 Sec / SecondFraction +1] granularity.\r\n                                 This field will be used only by HAL_RTC_GetTime function */\r\n\r\n  uint8_t TimeFormat;       /*!< Specifies the RTC AM/PM Time.\r\n                                 This parameter can be a value of @ref RTC_AM_PM_Definitions */ \r\n  \r\n  uint32_t DayLightSaving;  /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.\r\n                                 This parameter can be a value of @ref RTC_DayLightSaving_Definitions */\r\n  \r\n  uint32_t StoreOperation;  /*!< Specifies RTC_StoreOperation value to be written in the BCK bit \r\n                                 in CR register to store the operation.\r\n                                 This parameter can be a value of @ref RTC_StoreOperation_Definitions */\r\n}RTC_TimeTypeDef; \r\n  \r\n/** \r\n  * @brief  RTC Date structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.\r\n                         This parameter can be a value of @ref RTC_WeekDay_Definitions */\r\n  \r\n  uint8_t Month;    /*!< Specifies the RTC Date Month (in BCD format).\r\n                         This parameter can be a value of @ref RTC_Month_Date_Definitions */\r\n\r\n  uint8_t Date;     /*!< Specifies the RTC Date.\r\n                         This parameter must be a number between Min_Data = 1 and Max_Data = 31 */\r\n  \r\n  uint8_t Year;     /*!< Specifies the RTC Date Year.\r\n                         This parameter must be a number between Min_Data = 0 and Max_Data = 99 */\r\n                        \r\n}RTC_DateTypeDef;\r\n\r\n/** \r\n  * @brief  RTC Alarm structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  RTC_TimeTypeDef AlarmTime;     /*!< Specifies the RTC Alarm Time members */\r\n    \r\n  uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.\r\n                                      This parameter can be a value of @ref RTC_AlarmMask_Definitions */\r\n  \r\n  uint32_t AlarmSubSecondMask;   /*!< Specifies the RTC Alarm SubSeconds Masks.\r\n                                      This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */                                   \r\n\r\n  uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.\r\n                                     This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */\r\n  \r\n  uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.\r\n                                      If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.\r\n                                      If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */\r\n                                                                     \r\n  uint32_t Alarm;                /*!< Specifies the alarm .\r\n                                      This parameter can be a value of @ref RTC_Alarms_Definitions */                            \r\n}RTC_AlarmTypeDef;\r\n\r\n/** \r\n  * @brief  RTC Handle Structure definition  \r\n  */ \r\ntypedef struct\r\n{\r\n  RTC_TypeDef                 *Instance;  /*!< Register base address    */\r\n   \r\n  RTC_InitTypeDef             Init;       /*!< RTC required parameters  */ \r\n  \r\n  HAL_LockTypeDef             Lock;       /*!< RTC locking object       */\r\n  \r\n  __IO HAL_RTCStateTypeDef    State;      /*!< Time communication state */\r\n    \r\n}RTC_HandleTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup RTC_Exported_Constants RTC Exported Constants\r\n  * @{\r\n  */\r\n \r\n/** @defgroup RTC_Hour_Formats RTC Hour Formats\r\n  * @{\r\n  */ \r\n#define RTC_HOURFORMAT_24              ((uint32_t)0x00000000U)\r\n#define RTC_HOURFORMAT_12              ((uint32_t)0x00000040U)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions \r\n  * @{\r\n  */ \r\n#define RTC_OUTPUT_POLARITY_HIGH       ((uint32_t)0x00000000U)\r\n#define RTC_OUTPUT_POLARITY_LOW        ((uint32_t)0x00100000U)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT\r\n  * @{\r\n  */ \r\n#define RTC_OUTPUT_TYPE_OPENDRAIN      ((uint32_t)0x00000000U)\r\n#define RTC_OUTPUT_TYPE_PUSHPULL       ((uint32_t)RTC_OR_ALARMTYPE)  /* 0x00000008 */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions\r\n  * @{\r\n  */ \r\n#define RTC_HOURFORMAT12_AM            ((uint8_t)0x00U)\r\n#define RTC_HOURFORMAT12_PM            ((uint8_t)0x40U)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions\r\n  * @{\r\n  */ \r\n#define RTC_DAYLIGHTSAVING_SUB1H       ((uint32_t)0x00020000U)\r\n#define RTC_DAYLIGHTSAVING_ADD1H       ((uint32_t)0x00010000U)\r\n#define RTC_DAYLIGHTSAVING_NONE        ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions\r\n  * @{\r\n  */ \r\n#define RTC_STOREOPERATION_RESET        ((uint32_t)0x00000000U)\r\n#define RTC_STOREOPERATION_SET          ((uint32_t)0x00040000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions\r\n  * @{\r\n  */ \r\n#define RTC_FORMAT_BIN                      ((uint32_t)0x00000000U)\r\n#define RTC_FORMAT_BCD                      ((uint32_t)0x00000001U)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions\r\n  * @{\r\n  */\r\n/* Coded in BCD format */\r\n#define RTC_MONTH_JANUARY              ((uint8_t)0x01U)\r\n#define RTC_MONTH_FEBRUARY             ((uint8_t)0x02U)\r\n#define RTC_MONTH_MARCH                ((uint8_t)0x03U)\r\n#define RTC_MONTH_APRIL                ((uint8_t)0x04U)\r\n#define RTC_MONTH_MAY                  ((uint8_t)0x05U)\r\n#define RTC_MONTH_JUNE                 ((uint8_t)0x06U)\r\n#define RTC_MONTH_JULY                 ((uint8_t)0x07U)\r\n#define RTC_MONTH_AUGUST               ((uint8_t)0x08U)\r\n#define RTC_MONTH_SEPTEMBER            ((uint8_t)0x09U)\r\n#define RTC_MONTH_OCTOBER              ((uint8_t)0x10U)\r\n#define RTC_MONTH_NOVEMBER             ((uint8_t)0x11U)\r\n#define RTC_MONTH_DECEMBER             ((uint8_t)0x12U)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions\r\n  * @{\r\n  */   \r\n#define RTC_WEEKDAY_MONDAY             ((uint8_t)0x01U)\r\n#define RTC_WEEKDAY_TUESDAY            ((uint8_t)0x02U)\r\n#define RTC_WEEKDAY_WEDNESDAY          ((uint8_t)0x03U)\r\n#define RTC_WEEKDAY_THURSDAY           ((uint8_t)0x04U)\r\n#define RTC_WEEKDAY_FRIDAY             ((uint8_t)0x05U)\r\n#define RTC_WEEKDAY_SATURDAY           ((uint8_t)0x06U)\r\n#define RTC_WEEKDAY_SUNDAY             ((uint8_t)0x07U)\r\n/**\r\n  * @}\r\n  */                                 \r\n\r\n/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions\r\n  * @{\r\n  */ \r\n#define RTC_ALARMDATEWEEKDAYSEL_DATE      ((uint32_t)0x00000000U)\r\n#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY   ((uint32_t)0x40000000U)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions \r\n  * @{\r\n  */ \r\n#define RTC_ALARMMASK_NONE                ((uint32_t)0x00000000U)\r\n#define RTC_ALARMMASK_DATEWEEKDAY         RTC_ALRMAR_MSK4\r\n#define RTC_ALARMMASK_HOURS               RTC_ALRMAR_MSK3\r\n#define RTC_ALARMMASK_MINUTES             RTC_ALRMAR_MSK2\r\n#define RTC_ALARMMASK_SECONDS             RTC_ALRMAR_MSK1\r\n#define RTC_ALARMMASK_ALL                 ((uint32_t)0x80808080U)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions \r\n  * @{\r\n  */ \r\n#define RTC_ALARM_A                       RTC_CR_ALRAE\r\n#define RTC_ALARM_B                       RTC_CR_ALRBE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions\r\n  * @{\r\n  */\r\n#define RTC_ALARMSUBSECONDMASK_ALL         ((uint32_t)0x00000000U)  /*!< All Alarm SS fields are masked. \r\n                                                                        There is no comparison on sub seconds \r\n                                                                        for Alarm */\r\n#define RTC_ALARMSUBSECONDMASK_SS14_1      ((uint32_t)0x01000000U)  /*!< SS[14:1] are don't care in Alarm \r\n                                                                        comparison. Only SS[0] is compared.    */\r\n#define RTC_ALARMSUBSECONDMASK_SS14_2      ((uint32_t)0x02000000U)  /*!< SS[14:2] are don't care in Alarm \r\n                                                                        comparison. Only SS[1:0] are compared  */\r\n#define RTC_ALARMSUBSECONDMASK_SS14_3      ((uint32_t)0x03000000U)  /*!< SS[14:3] are don't care in Alarm \r\n                                                                        comparison. Only SS[2:0] are compared  */\r\n#define RTC_ALARMSUBSECONDMASK_SS14_4      ((uint32_t)0x04000000U)  /*!< SS[14:4] are don't care in Alarm \r\n                                                                        comparison. Only SS[3:0] are compared  */\r\n#define RTC_ALARMSUBSECONDMASK_SS14_5      ((uint32_t)0x05000000U)  /*!< SS[14:5] are don't care in Alarm \r\n                                                                        comparison. Only SS[4:0] are compared  */\r\n#define RTC_ALARMSUBSECONDMASK_SS14_6      ((uint32_t)0x06000000U)  /*!< SS[14:6] are don't care in Alarm \r\n                                                                        comparison. Only SS[5:0] are compared  */\r\n#define RTC_ALARMSUBSECONDMASK_SS14_7      ((uint32_t)0x07000000U)  /*!< SS[14:7] are don't care in Alarm \r\n                                                                        comparison. Only SS[6:0] are compared  */\r\n#define RTC_ALARMSUBSECONDMASK_SS14_8      ((uint32_t)0x08000000U)  /*!< SS[14:8] are don't care in Alarm \r\n                                                                        comparison. Only SS[7:0] are compared  */\r\n#define RTC_ALARMSUBSECONDMASK_SS14_9      ((uint32_t)0x09000000U)  /*!< SS[14:9] are don't care in Alarm \r\n                                                                        comparison. Only SS[8:0] are compared  */\r\n#define RTC_ALARMSUBSECONDMASK_SS14_10     ((uint32_t)0x0A000000U)  /*!< SS[14:10] are don't care in Alarm \r\n                                                                        comparison. Only SS[9:0] are compared  */\r\n#define RTC_ALARMSUBSECONDMASK_SS14_11     ((uint32_t)0x0B000000U)  /*!< SS[14:11] are don't care in Alarm \r\n                                                                        comparison. Only SS[10:0] are compared */\r\n#define RTC_ALARMSUBSECONDMASK_SS14_12     ((uint32_t)0x0C000000U)  /*!< SS[14:12] are don't care in Alarm \r\n                                                                        comparison.Only SS[11:0] are compared  */\r\n#define RTC_ALARMSUBSECONDMASK_SS14_13     ((uint32_t)0x0D000000U)  /*!< SS[14:13] are don't care in Alarm \r\n                                                                        comparison. Only SS[12:0] are compared */\r\n#define RTC_ALARMSUBSECONDMASK_SS14        ((uint32_t)0x0E000000U)  /*!< SS[14] is don't care in Alarm \r\n                                                                        comparison.Only SS[13:0] are compared  */\r\n#define RTC_ALARMSUBSECONDMASK_NONE        ((uint32_t)0x0F000000U)  /*!< SS[14:0] are compared and must match \r\n                                                                        to activate alarm. */\r\n/**\r\n  * @}\r\n  */   \r\n\r\n/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions \r\n  * @{\r\n  */ \r\n#define RTC_IT_TS                         ((uint32_t)RTC_CR_TSIE)\r\n#define RTC_IT_WUT                        ((uint32_t)RTC_CR_WUTIE)\r\n#define RTC_IT_ALRA                       ((uint32_t)RTC_CR_ALRAIE)\r\n#define RTC_IT_ALRB                       ((uint32_t)RTC_CR_ALRBIE)\r\n#define RTC_IT_TAMP                       ((uint32_t)RTC_TAMPCR_TAMPIE) /* Used only to Enable the Tamper Interrupt */\r\n#define RTC_IT_TAMP1                      ((uint32_t)RTC_TAMPCR_TAMP1IE)\r\n#define RTC_IT_TAMP2                      ((uint32_t)RTC_TAMPCR_TAMP2IE)\r\n#define RTC_IT_TAMP3                      ((uint32_t)RTC_TAMPCR_TAMP3IE)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RTC_Flags_Definitions RTC Flags Definitions \r\n  * @{\r\n  */ \r\n#define RTC_FLAG_RECALPF                  ((uint32_t)RTC_ISR_RECALPF)\r\n#define RTC_FLAG_TAMP3F                   ((uint32_t)RTC_ISR_TAMP3F)\r\n#define RTC_FLAG_TAMP2F                   ((uint32_t)RTC_ISR_TAMP2F)\r\n#define RTC_FLAG_TAMP1F                   ((uint32_t)RTC_ISR_TAMP1F)\r\n#define RTC_FLAG_TSOVF                    ((uint32_t)RTC_ISR_TSOVF)\r\n#define RTC_FLAG_TSF                      ((uint32_t)RTC_ISR_TSF)\r\n#define RTC_FLAG_ITSF                     ((uint32_t)RTC_ISR_ITSF)\r\n#define RTC_FLAG_WUTF                     ((uint32_t)RTC_ISR_WUTF)\r\n#define RTC_FLAG_ALRBF                    ((uint32_t)RTC_ISR_ALRBF)\r\n#define RTC_FLAG_ALRAF                    ((uint32_t)RTC_ISR_ALRAF)\r\n#define RTC_FLAG_INITF                    ((uint32_t)RTC_ISR_INITF)\r\n#define RTC_FLAG_RSF                      ((uint32_t)RTC_ISR_RSF)\r\n#define RTC_FLAG_INITS                    ((uint32_t)RTC_ISR_INITS)\r\n#define RTC_FLAG_SHPF                     ((uint32_t)RTC_ISR_SHPF)\r\n#define RTC_FLAG_WUTWF                    ((uint32_t)RTC_ISR_WUTWF)\r\n#define RTC_FLAG_ALRBWF                   ((uint32_t)RTC_ISR_ALRBWF)\r\n#define RTC_FLAG_ALRAWF                   ((uint32_t)RTC_ISR_ALRAWF)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup RTC_Exported_Macros RTC Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief Reset RTC handle state\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)\r\n\r\n/**\r\n  * @brief  Disable the write protection for RTC registers.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)             \\\r\n                        do{                                       \\\r\n                            (__HANDLE__)->Instance->WPR = 0xCA;   \\\r\n                            (__HANDLE__)->Instance->WPR = 0x53;   \\\r\n                          } while(0)\r\n\r\n/**\r\n  * @brief  Enable the write protection for RTC registers.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)              \\\r\n                        do{                                       \\\r\n                            (__HANDLE__)->Instance->WPR = 0xFF;   \\\r\n                          } while(0)                            \r\n \r\n/**\r\n  * @brief  Enable the RTC ALARMA peripheral.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__)                           ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))\r\n\r\n/**\r\n  * @brief  Disable the RTC ALARMA peripheral.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))\r\n\r\n/**\r\n  * @brief  Enable the RTC ALARMB peripheral.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__)                           ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))\r\n\r\n/**\r\n  * @brief  Disable the RTC ALARMB peripheral.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))\r\n\r\n/**\r\n  * @brief  Enable the RTC Alarm interrupt.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. \r\n  *          This parameter can be any combination of the following values:\r\n  *             @arg RTC_IT_ALRA: Alarm A interrupt\r\n  *             @arg RTC_IT_ALRB: Alarm B interrupt  \r\n  * @retval None\r\n  */   \r\n#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disable the RTC Alarm interrupt.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. \r\n  *         This parameter can be any combination of the following values:\r\n  *            @arg RTC_IT_ALRA: Alarm A interrupt\r\n  *            @arg RTC_IT_ALRB: Alarm B interrupt  \r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Check whether the specified RTC Alarm interrupt has occurred or not.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt to check.\r\n  *         This parameter can be:\r\n  *            @arg RTC_IT_ALRA: Alarm A interrupt\r\n  *            @arg RTC_IT_ALRB: Alarm B interrupt  \r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__)                  ((((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) & 0x0000FFFF) != RESET)? SET : RESET)\r\n\r\n/**\r\n  * @brief  Get the selected RTC Alarm's flag status.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @param  __FLAG__: specifies the RTC Alarm Flag to check.\r\n  *         This parameter can be:\r\n  *            @arg RTC_FLAG_ALRAF\r\n  *            @arg RTC_FLAG_ALRBF\r\n  *            @arg RTC_FLAG_ALRAWF     \r\n  *            @arg RTC_FLAG_ALRBWF    \r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)                (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)\r\n\r\n/**\r\n  * @brief  Clear the RTC Alarm's pending flags.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @param  __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.\r\n  *          This parameter can be:\r\n  *             @arg RTC_FLAG_ALRAF\r\n  *             @arg RTC_FLAG_ALRBF \r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)                  ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))\r\n                                       \r\n/**\r\n  * @brief  Check whether the specified RTC Alarm interrupt has been enabled or not.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.\r\n  *         This parameter can be:\r\n  *            @arg RTC_IT_ALRA: Alarm A interrupt\r\n  *            @arg RTC_IT_ALRB: Alarm B interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)\r\n\r\n/**\r\n  * @brief  Enable interrupt on the RTC Alarm associated Exti line.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_ALARM_EXTI_ENABLE_IT()            (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)\r\n\r\n/**\r\n  * @brief  Disable interrupt on the RTC Alarm associated Exti line.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_ALARM_EXTI_DISABLE_IT()           (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))\r\n\r\n/**\r\n  * @brief  Enable event on the RTC Alarm associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT()         (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)\r\n\r\n/**\r\n  * @brief  Disable event on the RTC Alarm associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT()         (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))\r\n\r\n/**\r\n  * @brief  Enable falling edge trigger on the RTC Alarm associated Exti line.  \r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)\r\n\r\n/**\r\n  * @brief  Disable falling edge trigger on the RTC Alarm associated Exti line.  \r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))\r\n\r\n/**\r\n  * @brief  Enable rising edge trigger on the RTC Alarm associated Exti line.  \r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)\r\n\r\n/**\r\n  * @brief  Disable rising edge trigger on the RTC Alarm associated Exti line.  \r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))\r\n\r\n/**\r\n  * @brief  Enable rising & falling edge trigger on the RTC Alarm associated Exti line.  \r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();\r\n\r\n/**\r\n  * @brief  Disable rising & falling edge trigger on the RTC Alarm associated Exti line.  \r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();\r\n\r\n/**\r\n  * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.\r\n  * @retval Line Status.\r\n  */\r\n#define __HAL_RTC_ALARM_EXTI_GET_FLAG()              (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)\r\n\r\n/**\r\n  * @brief Clear the RTC Alarm associated Exti line flag.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()            (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)\r\n\r\n/**\r\n  * @brief Generate a Software interrupt on RTC Alarm associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()         (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Include RTC HAL Extension module */\r\n#include \"stm32f7xx_hal_rtc_ex.h\"\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup RTC_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup RTC_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n/* Initialization and de-initialization functions  ****************************/\r\nHAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);\r\nHAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);\r\nvoid       HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);\r\nvoid       HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup RTC_Exported_Functions_Group2\r\n  * @{\r\n  */\r\n/* RTC Time and Date functions ************************************************/\r\nHAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);\r\nHAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);\r\nHAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);\r\nHAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup RTC_Exported_Functions_Group3\r\n  * @{\r\n  */\r\n/* RTC Alarm functions ********************************************************/\r\nHAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);\r\nHAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);\r\nHAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);\r\nHAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);\r\nvoid                HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);\r\nHAL_StatusTypeDef   HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);\r\nvoid         HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup RTC_Exported_Functions_Group4\r\n  * @{\r\n  */\r\n/* Peripheral Control functions ***********************************************/\r\nHAL_StatusTypeDef   HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup RTC_Exported_Functions_Group5\r\n  * @{\r\n  */\r\n/* Peripheral State functions *************************************************/\r\nHAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup RTC_Private_Constants RTC Private Constants\r\n  * @{\r\n  */\r\n/* Masks Definition */\r\n#define RTC_TR_RESERVED_MASK    ((uint32_t)0x007F7F7FU)\r\n#define RTC_DR_RESERVED_MASK    ((uint32_t)0x00FFFF3FU) \r\n#define RTC_INIT_MASK           ((uint32_t)0xFFFFFFFFU)  \r\n#define RTC_RSF_MASK            ((uint32_t)0xFFFFFF5FU)\r\n\r\n#define RTC_TIMEOUT_VALUE       1000\r\n\r\n#define RTC_EXTI_LINE_ALARM_EVENT             ((uint32_t)EXTI_IMR_IM17)  /*!< External interrupt line 17 Connected to the RTC Alarm event */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup RTC_Private_Macros RTC Private Macros\r\n  * @{\r\n  */\r\n\r\n/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters\r\n  * @{\r\n  */\r\n#define IS_RTC_HOUR_FORMAT(__FORMAT__) (((__FORMAT__) == RTC_HOURFORMAT_12) || \\\r\n                                        ((__FORMAT__) == RTC_HOURFORMAT_24))\r\n#define IS_RTC_OUTPUT_POL(__POL__)     (((__POL__) == RTC_OUTPUT_POLARITY_HIGH) || \\\r\n                                        ((__POL__) == RTC_OUTPUT_POLARITY_LOW))\r\n#define IS_RTC_OUTPUT_TYPE(__TYPE__)   (((__TYPE__) == RTC_OUTPUT_TYPE_OPENDRAIN) || \\\r\n                                        ((__TYPE__) == RTC_OUTPUT_TYPE_PUSHPULL))\r\n#define IS_RTC_ASYNCH_PREDIV(__PREDIV__)   ((__PREDIV__) <= (uint32_t)0x7F) \r\n#define IS_RTC_SYNCH_PREDIV(__PREDIV__)    ((__PREDIV__) <= (uint32_t)0x7FFF)\r\n#define IS_RTC_HOUR12(__HOUR__)            (((__HOUR__) > (uint32_t)0) && ((__HOUR__) <= (uint32_t)12))\r\n#define IS_RTC_HOUR24(__HOUR__)            ((__HOUR__) <= (uint32_t)23)\r\n#define IS_RTC_MINUTES(__MINUTES__)        ((__MINUTES__) <= (uint32_t)59)\r\n#define IS_RTC_SECONDS(__SECONDS__)        ((__SECONDS__) <= (uint32_t)59)\r\n#define IS_RTC_HOURFORMAT12(__PM__)  (((__PM__) == RTC_HOURFORMAT12_AM) || ((__PM__) == RTC_HOURFORMAT12_PM))\r\n#define IS_RTC_DAYLIGHT_SAVING(__SAVE__) (((__SAVE__) == RTC_DAYLIGHTSAVING_SUB1H) || \\\r\n                                          ((__SAVE__) == RTC_DAYLIGHTSAVING_ADD1H) || \\\r\n                                          ((__SAVE__) == RTC_DAYLIGHTSAVING_NONE))\r\n#define IS_RTC_STORE_OPERATION(__OPERATION__) (((__OPERATION__) == RTC_STOREOPERATION_RESET) || \\\r\n                                               ((__OPERATION__) == RTC_STOREOPERATION_SET))\r\n#define IS_RTC_FORMAT(__FORMAT__) (((__FORMAT__) == RTC_FORMAT_BIN) || ((__FORMAT__) == RTC_FORMAT_BCD))\r\n#define IS_RTC_YEAR(__YEAR__)              ((__YEAR__) <= (uint32_t)99)\r\n#define IS_RTC_MONTH(__MONTH__)            (((__MONTH__) >= (uint32_t)1) && ((__MONTH__) <= (uint32_t)12))\r\n#define IS_RTC_DATE(__DATE__)              (((__DATE__) >= (uint32_t)1) && ((__DATE__) <= (uint32_t)31))\r\n#define IS_RTC_WEEKDAY(__WEEKDAY__) (((__WEEKDAY__) == RTC_WEEKDAY_MONDAY)    || \\\r\n                                     ((__WEEKDAY__) == RTC_WEEKDAY_TUESDAY)   || \\\r\n                                     ((__WEEKDAY__) == RTC_WEEKDAY_WEDNESDAY) || \\\r\n                                     ((__WEEKDAY__) == RTC_WEEKDAY_THURSDAY)  || \\\r\n                                     ((__WEEKDAY__) == RTC_WEEKDAY_FRIDAY)    || \\\r\n                                     ((__WEEKDAY__) == RTC_WEEKDAY_SATURDAY)  || \\\r\n                                     ((__WEEKDAY__) == RTC_WEEKDAY_SUNDAY))\r\n\r\n#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(__DATE__) (((__DATE__) >(uint32_t) 0) && ((__DATE__) <= (uint32_t)31))\r\n#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(__WEEKDAY__) (((__WEEKDAY__) == RTC_WEEKDAY_MONDAY)    || \\\r\n                                                        ((__WEEKDAY__) == RTC_WEEKDAY_TUESDAY)   || \\\r\n                                                        ((__WEEKDAY__) == RTC_WEEKDAY_WEDNESDAY) || \\\r\n                                                        ((__WEEKDAY__) == RTC_WEEKDAY_THURSDAY)  || \\\r\n                                                        ((__WEEKDAY__) == RTC_WEEKDAY_FRIDAY)    || \\\r\n                                                        ((__WEEKDAY__) == RTC_WEEKDAY_SATURDAY)  || \\\r\n                                                        ((__WEEKDAY__) == RTC_WEEKDAY_SUNDAY))\r\n#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \\\r\n                                                ((__SEL__) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))\r\n#define IS_RTC_ALARM_MASK(__MASK__)  (((__MASK__) & 0x7F7F7F7F) == (uint32_t)RESET)\r\n#define IS_RTC_ALARM(__ALARM__)      (((__ALARM__) == RTC_ALARM_A) || ((__ALARM__) == RTC_ALARM_B))\r\n#define IS_RTC_ALARM_SUB_SECOND_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)0x00007FFF)\r\n#define IS_RTC_ALARM_SUB_SECOND_MASK(__MASK__)   (((__MASK__) == RTC_ALARMSUBSECONDMASK_ALL) || \\\r\n                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_1) || \\\r\n                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_2) || \\\r\n                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_3) || \\\r\n                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_4) || \\\r\n                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_5) || \\\r\n                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_6) || \\\r\n                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_7) || \\\r\n                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_8) || \\\r\n                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_9) || \\\r\n                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_10) || \\\r\n                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_11) || \\\r\n                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_12) || \\\r\n                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_13) || \\\r\n                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14) || \\\r\n                                                  ((__MASK__) == RTC_ALARMSUBSECONDMASK_NONE))\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup RTC_Private_Functions RTC Private Functions\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef  RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);\r\nuint8_t            RTC_ByteToBcd2(uint8_t Value);\r\nuint8_t            RTC_Bcd2ToByte(uint8_t Value);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_RTC_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_rtc_ex.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of RTC HAL Extension module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_RTC_EX_H\r\n#define __STM32F7xx_HAL_RTC_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup RTCEx\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/ \r\n/** @defgroup RTCEx_Exported_Types RTCEx Exported Types\r\n  * @{\r\n  */\r\n\r\n/** \r\n  * @brief  RTC Tamper structure definition  \r\n  */\r\ntypedef struct \r\n{\r\n  uint32_t Tamper;                      /*!< Specifies the Tamper Pin.\r\n                                             This parameter can be a value of @ref  RTCEx_Tamper_Pins_Definitions */\r\n  \r\n  uint32_t Interrupt;                   /*!< Specifies the Tamper Interrupt.\r\n                                             This parameter can be a value of @ref  RTCEx_Tamper_Interrupt_Definitions */                                  \r\n                                             \r\n  uint32_t Trigger;                     /*!< Specifies the Tamper Trigger.\r\n                                             This parameter can be a value of @ref  RTCEx_Tamper_Trigger_Definitions */\r\n                                             \r\n  uint32_t NoErase;                     /*!< Specifies the Tamper no erase mode.\r\n                                             This parameter can be a value of @ref  RTCEx_Tamper_EraseBackUp_Definitions */\r\n\r\n  uint32_t MaskFlag;                     /*!< Specifies the Tamper Flag masking.\r\n                                             This parameter can be a value of @ref RTCEx_Tamper_MaskFlag_Definitions   */\r\n\r\n  uint32_t Filter;                      /*!< Specifies the RTC Filter Tamper.\r\n                                             This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */\r\n  \r\n  uint32_t SamplingFrequency;           /*!< Specifies the sampling frequency.\r\n                                             This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */\r\n                                      \r\n  uint32_t PrechargeDuration;           /*!< Specifies the Precharge Duration .\r\n                                             This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */ \r\n \r\n  uint32_t TamperPullUp;                /*!< Specifies the Tamper PullUp .\r\n                                             This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */           \r\n \r\n  uint32_t TimeStampOnTamperDetection;  /*!< Specifies the TimeStampOnTamperDetection.\r\n                                             This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */                      \r\n}RTC_TamperTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup RTCEx_Output_selection_Definitions RTCEx Output selection Definitions \r\n  * @{\r\n  */ \r\n#define RTC_OUTPUT_DISABLE             ((uint32_t)0x00000000U)\r\n#define RTC_OUTPUT_ALARMA              ((uint32_t)0x00200000U)\r\n#define RTC_OUTPUT_ALARMB              ((uint32_t)0x00400000U)\r\n#define RTC_OUTPUT_WAKEUP              ((uint32_t)0x00600000U)\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/** @defgroup RTCEx_Backup_Registers_Definitions RTC Backup Registers Definitions\r\n  * @{\r\n  */\r\n#define RTC_BKP_DR0                       ((uint32_t)0x00000000U)\r\n#define RTC_BKP_DR1                       ((uint32_t)0x00000001U)\r\n#define RTC_BKP_DR2                       ((uint32_t)0x00000002U)\r\n#define RTC_BKP_DR3                       ((uint32_t)0x00000003U)\r\n#define RTC_BKP_DR4                       ((uint32_t)0x00000004U)\r\n#define RTC_BKP_DR5                       ((uint32_t)0x00000005U)\r\n#define RTC_BKP_DR6                       ((uint32_t)0x00000006U)\r\n#define RTC_BKP_DR7                       ((uint32_t)0x00000007U)\r\n#define RTC_BKP_DR8                       ((uint32_t)0x00000008U)\r\n#define RTC_BKP_DR9                       ((uint32_t)0x00000009U)\r\n#define RTC_BKP_DR10                      ((uint32_t)0x0000000AU)\r\n#define RTC_BKP_DR11                      ((uint32_t)0x0000000BU)\r\n#define RTC_BKP_DR12                      ((uint32_t)0x0000000CU)\r\n#define RTC_BKP_DR13                      ((uint32_t)0x0000000DU)\r\n#define RTC_BKP_DR14                      ((uint32_t)0x0000000EU)\r\n#define RTC_BKP_DR15                      ((uint32_t)0x0000000FU)\r\n#define RTC_BKP_DR16                      ((uint32_t)0x00000010U)\r\n#define RTC_BKP_DR17                      ((uint32_t)0x00000011U)\r\n#define RTC_BKP_DR18                      ((uint32_t)0x00000012U)\r\n#define RTC_BKP_DR19                      ((uint32_t)0x00000013U)\r\n#define RTC_BKP_DR20                      ((uint32_t)0x00000014U)\r\n#define RTC_BKP_DR21                      ((uint32_t)0x00000015U)\r\n#define RTC_BKP_DR22                      ((uint32_t)0x00000016U)\r\n#define RTC_BKP_DR23                      ((uint32_t)0x00000017U)\r\n#define RTC_BKP_DR24                      ((uint32_t)0x00000018U)\r\n#define RTC_BKP_DR25                      ((uint32_t)0x00000019U)\r\n#define RTC_BKP_DR26                      ((uint32_t)0x0000001AU)\r\n#define RTC_BKP_DR27                      ((uint32_t)0x0000001BU)\r\n#define RTC_BKP_DR28                      ((uint32_t)0x0000001CU)\r\n#define RTC_BKP_DR29                      ((uint32_t)0x0000001DU)\r\n#define RTC_BKP_DR30                      ((uint32_t)0x0000001EU)\r\n#define RTC_BKP_DR31                      ((uint32_t)0x0000001FU)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges definitions \r\n  * @{\r\n  */ \r\n#define RTC_TIMESTAMPEDGE_RISING          ((uint32_t)0x00000000U)\r\n#define RTC_TIMESTAMPEDGE_FALLING         ((uint32_t)0x00000008U)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup RTCEx_Tamper_Pins_Definitions RTCEx Tamper Pins Definitions \r\n  * @{\r\n  */ \r\n#define RTC_TAMPER_1                    RTC_TAMPCR_TAMP1E\r\n#define RTC_TAMPER_2                    RTC_TAMPCR_TAMP2E\r\n#define RTC_TAMPER_3                    RTC_TAMPCR_TAMP3E\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RTCEx_Tamper_Interrupt_Definitions RTCEx Tamper Interrupt Definitions\r\n  * @{\r\n  */\r\n#define RTC_TAMPER1_INTERRUPT                RTC_TAMPCR_TAMP1IE\r\n#define RTC_TAMPER2_INTERRUPT                RTC_TAMPCR_TAMP2IE\r\n#define RTC_TAMPER3_INTERRUPT                RTC_TAMPCR_TAMP3IE\r\n#define RTC_ALL_TAMPER_INTERRUPT             RTC_TAMPCR_TAMPIE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RTCEx_TimeStamp_Pin_Selection RTCEx TimeStamp Pin Selection\r\n  * @{\r\n  */ \r\n#define RTC_TIMESTAMPPIN_DEFAULT            ((uint32_t)0x00000000U)\r\n#define RTC_TIMESTAMPPIN_POS1               ((uint32_t)0x00000002U)\r\n#define RTC_TIMESTAMPPIN_POS2               ((uint32_t)0x00000004U)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup RTCEx_Tamper_Trigger_Definitions RTCEx Tamper Trigger Definitions \r\n  * @{\r\n  */ \r\n#define RTC_TAMPERTRIGGER_RISINGEDGE       ((uint32_t)0x00000000U)\r\n#define RTC_TAMPERTRIGGER_FALLINGEDGE      ((uint32_t)0x00000002U)\r\n#define RTC_TAMPERTRIGGER_LOWLEVEL         RTC_TAMPERTRIGGER_RISINGEDGE\r\n#define RTC_TAMPERTRIGGER_HIGHLEVEL        RTC_TAMPERTRIGGER_FALLINGEDGE \r\n/**\r\n  * @}\r\n  */  \r\n\r\n  /** @defgroup RTCEx_Tamper_EraseBackUp_Definitions RTCEx Tamper EraseBackUp Definitions\r\n* @{\r\n*/\r\n#define RTC_TAMPER_ERASE_BACKUP_ENABLE               ((uint32_t)0x00000000U)\r\n#define RTC_TAMPER_ERASE_BACKUP_DISABLE              ((uint32_t)0x00020000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RTCEx_Tamper_MaskFlag_Definitions RTCEx Tamper MaskFlag Definitions\r\n  * @{\r\n  */\r\n#define RTC_TAMPERMASK_FLAG_DISABLE                ((uint32_t)0x00000000U)\r\n#define RTC_TAMPERMASK_FLAG_ENABLE                 ((uint32_t)0x00040000U)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup RTCEx_Tamper_Filter_Definitions RTCEx Tamper Filter Definitions \r\n  * @{\r\n  */ \r\n#define RTC_TAMPERFILTER_DISABLE   ((uint32_t)0x00000000U)  /*!< Tamper filter is disabled */\r\n\r\n#define RTC_TAMPERFILTER_2SAMPLE   ((uint32_t)0x00000800U)  /*!< Tamper is activated after 2 \r\n                                                                consecutive samples at the active level */\r\n#define RTC_TAMPERFILTER_4SAMPLE   ((uint32_t)0x00001000U)  /*!< Tamper is activated after 4 \r\n                                                                consecutive samples at the active level */\r\n#define RTC_TAMPERFILTER_8SAMPLE   ((uint32_t)0x00001800U)  /*!< Tamper is activated after 8 \r\n                                                                consecutive samples at the active leve. */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTCEx Tamper Sampling Frequencies Definitions \r\n  * @{\r\n  */\r\n#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768  ((uint32_t)0x00000000U)  /*!< Each of the tamper inputs are sampled\r\n                                                                             with a frequency =  RTCCLK / 32768 */\r\n#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384  ((uint32_t)0x00000100U)  /*!< Each of the tamper inputs are sampled\r\n                                                                             with a frequency =  RTCCLK / 16384 */\r\n#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192   ((uint32_t)0x00000200U)  /*!< Each of the tamper inputs are sampled\r\n                                                                             with a frequency =  RTCCLK / 8192  */\r\n#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096   ((uint32_t)0x00000300U)  /*!< Each of the tamper inputs are sampled\r\n                                                                             with a frequency =  RTCCLK / 4096  */\r\n#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048   ((uint32_t)0x00000400U)  /*!< Each of the tamper inputs are sampled\r\n                                                                             with a frequency =  RTCCLK / 2048  */\r\n#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024   ((uint32_t)0x00000500U)  /*!< Each of the tamper inputs are sampled\r\n                                                                             with a frequency =  RTCCLK / 1024  */\r\n#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512    ((uint32_t)0x00000600U)  /*!< Each of the tamper inputs are sampled\r\n                                                                             with a frequency =  RTCCLK / 512   */\r\n#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256    ((uint32_t)0x00000700U)  /*!< Each of the tamper inputs are sampled\r\n                                                                             with a frequency =  RTCCLK / 256   */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTCEx Tamper Pin Precharge Duration Definitions \r\n  * @{\r\n  */ \r\n#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000U)  /*!< Tamper pins are pre-charged before \r\n                                                                         sampling during 1 RTCCLK cycle */\r\n#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000U)  /*!< Tamper pins are pre-charged before \r\n                                                                         sampling during 2 RTCCLK cycles */\r\n#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000U)  /*!< Tamper pins are pre-charged before \r\n                                                                         sampling during 4 RTCCLK cycles */\r\n#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000U)  /*!< Tamper pins are pre-charged before \r\n                                                                         sampling during 8 RTCCLK cycles */\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTCEx Tamper TimeStampOnTamperDetection Definitions\r\n  * @{\r\n  */ \r\n#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE  ((uint32_t)RTC_TAMPCR_TAMPTS)  /*!< TimeStamp on Tamper Detection event saved        */\r\n#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000U)        /*!< TimeStamp on Tamper Detection event is not saved */                                                                      \r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup  RTCEx_Tamper_Pull_UP_Definitions RTCEx Tamper Pull UP Definitions\r\n  * @{\r\n  */ \r\n#define RTC_TAMPER_PULLUP_ENABLE  ((uint32_t)0x00000000U)            /*!< TimeStamp on Tamper Detection event saved        */\r\n#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAMPCR_TAMPPUDIS)   /*!< TimeStamp on Tamper Detection event is not saved */                                                                  \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definitions \r\n  * @{\r\n  */ \r\n#define RTC_WAKEUPCLOCK_RTCCLK_DIV16        ((uint32_t)0x00000000U)\r\n#define RTC_WAKEUPCLOCK_RTCCLK_DIV8         ((uint32_t)0x00000001U)\r\n#define RTC_WAKEUPCLOCK_RTCCLK_DIV4         ((uint32_t)0x00000002U)\r\n#define RTC_WAKEUPCLOCK_RTCCLK_DIV2         ((uint32_t)0x00000003U)\r\n#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS      ((uint32_t)0x00000004U)\r\n#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS      ((uint32_t)0x00000006U)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth calib period Definitions \r\n  * @{\r\n  */ \r\n#define RTC_SMOOTHCALIB_PERIOD_32SEC   ((uint32_t)0x00000000U)  /*!< If RTCCLK = 32768 Hz, Smooth calibration\r\n                                                                    period is 32s,  else 2exp20 RTCCLK seconds */\r\n#define RTC_SMOOTHCALIB_PERIOD_16SEC   ((uint32_t)0x00002000U)  /*!< If RTCCLK = 32768 Hz, Smooth calibration \r\n                                                                    period is 16s, else 2exp19 RTCCLK seconds */\r\n#define RTC_SMOOTHCALIB_PERIOD_8SEC    ((uint32_t)0x00004000U)  /*!< If RTCCLK = 32768 Hz, Smooth calibration \r\n                                                                    period is 8s, else 2exp18 RTCCLK seconds */                                        \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth calib Plus pulses Definitions \r\n  * @{\r\n  */ \r\n#define RTC_SMOOTHCALIB_PLUSPULSES_SET    ((uint32_t)0x00008000U)  /*!< The number of RTCCLK pulses added  \r\n                                                                       during a X -second window = Y - CALM[8:0] \r\n                                                                       with Y = 512, 256, 128 when X = 32, 16, 8 */\r\n#define RTC_SMOOTHCALIB_PLUSPULSES_RESET  ((uint32_t)0x00000000U)  /*!< The number of RTCCLK pulses subbstited\r\n                                                                       during a 32-second window = CALM[8:0] */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions RTCEx Add 1 Second Parameter Definitions\r\n  * @{\r\n  */ \r\n#define RTC_SHIFTADD1S_RESET      ((uint32_t)0x00000000U)\r\n#define RTC_SHIFTADD1S_SET        ((uint32_t)0x80000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n /** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions\r\n  * @{\r\n  */ \r\n#define RTC_CALIBOUTPUT_512HZ            ((uint32_t)0x00000000U) \r\n#define RTC_CALIBOUTPUT_1HZ              ((uint32_t)0x00080000U)\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/* Exported macros -----------------------------------------------------------*/\r\n/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Enable the RTC WakeUp Timer peripheral.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__)                     ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))\r\n\r\n/**\r\n  * @brief  Disable the RTC WakeUp Timer peripheral.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__)                    ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))\r\n\r\n/**\r\n  * @brief  Enable the RTC WakeUpTimer interrupt.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.\r\n  *         This parameter can be:\r\n  *            @arg RTC_IT_WUT: WakeUpTimer interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disable the RTC WakeUpTimer interrupt.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.\r\n  *         This parameter can be:\r\n  *            @arg RTC_IT_WUT: WakeUpTimer interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Check whether the specified RTC WakeUpTimer interrupt has occurred or not.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to check.\r\n  *         This parameter can be:\r\n  *            @arg RTC_IT_WUT:  WakeUpTimer interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__)       (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)\r\n\r\n/**\r\n  * @brief  Check whether the specified RTC Wake Up timer interrupt has been enabled or not.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @param  __INTERRUPT__: specifies the RTC Wake Up timer interrupt sources to check.\r\n  *         This parameter can be:\r\n  *            @arg RTC_IT_WUT:  WakeUpTimer interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)   (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)\r\n\r\n/**\r\n  * @brief  Get the selected RTC WakeUpTimer's flag status.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @param  __FLAG__: specifies the RTC WakeUpTimer Flag is pending or not.\r\n  *          This parameter can be:\r\n  *             @arg RTC_FLAG_WUTF\r\n  *             @arg RTC_FLAG_WUTWF\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__)   (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)\r\n\r\n/**\r\n  * @brief  Clear the RTC Wake Up timer's pending flags.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @param  __FLAG__: specifies the RTC WakeUpTimer Flag to clear.\r\n  *         This parameter can be:\r\n  *            @arg RTC_FLAG_WUTF\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))    \r\n\r\n/**\r\n  * @brief  Enable the RTC Tamper1 input detection.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E))\r\n\r\n/**\r\n  * @brief  Disable the RTC Tamper1 input detection.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E))\r\n\r\n/**\r\n  * @brief  Enable the RTC Tamper2 input detection.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E))\r\n\r\n/**\r\n  * @brief  Disable the RTC Tamper2 input detection.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E))\r\n\r\n/**\r\n  * @brief  Enable the RTC Tamper3 input detection.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E))\r\n\r\n/**\r\n  * @brief  Disable the RTC Tamper3 input detection.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E))\r\n\r\n/**\r\n  * @brief  Check whether the specified RTC Tamper interrupt has occurred or not.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @param  __INTERRUPT__: specifies the RTC Tamper interrupt to check.\r\n  *         This parameter can be:\r\n  *            @arg  RTC_IT_TAMP: All tampers interrupts\r\n  *            @arg  RTC_IT_TAMP1: Tamper1 interrupt\r\n  *            @arg  RTC_IT_TAMP2: Tamper2 interrupt\r\n  *            @arg  RTC_IT_TAMP3: Tamper3 interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)           (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3)) != RESET) ? SET : RESET) : \\\r\n                                                                      ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET) : \\\r\n                                                                                                          (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7)) != RESET) ? SET : RESET))\r\n\r\n/**\r\n  * @brief  Check whether the specified RTC Tamper interrupt has been enabled or not.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @param  __INTERRUPT__: specifies the RTC Tamper interrupt source to check.\r\n  *         This parameter can be:\r\n  *            @arg  RTC_IT_TAMP: All tampers interrupts\r\n  *            @arg  RTC_IT_TAMP1: Tamper1 interrupt\r\n  *            @arg  RTC_IT_TAMP2: Tamper2 interrupt\r\n  *            @arg  RTC_IT_TAMP3: Tamper3 interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)    (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)\r\n\r\n/**\r\n  * @brief  Get the selected RTC Tamper's flag status.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @param  __FLAG__: specifies the RTC Tamper Flag is pending or not.\r\n  *          This parameter can be:\r\n  *             @arg RTC_FLAG_TAMP1F: Tamper1 flag\r\n  *             @arg RTC_FLAG_TAMP2F: Tamper2 flag\r\n  *             @arg RTC_FLAG_TAMP3F: Tamper3 flag\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__)        (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)\r\n\r\n/**\r\n  * @brief  Clear the RTC Tamper's pending flags.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @param  __FLAG__: specifies the RTC Tamper Flag sources to clear.\r\n  *          This parameter can be:\r\n  *             @arg RTC_FLAG_TAMP1F: Tamper1 flag\r\n  *             @arg RTC_FLAG_TAMP2F: Tamper2 flag\r\n  *             @arg RTC_FLAG_TAMP3F: Tamper3 flag\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))\r\n\r\n/**\r\n  * @brief  Enable the RTC TimeStamp peripheral.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))\r\n\r\n/**\r\n  * @brief  Disable the RTC TimeStamp peripheral.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))\r\n\r\n/**\r\n  * @brief  Enable the RTC TimeStamp interrupt.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.\r\n  *         This parameter can be:\r\n  *            @arg RTC_IT_TS: TimeStamp interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disable the RTC TimeStamp interrupt.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. \r\n  *         This parameter can be:\r\n  *            @arg RTC_IT_TS: TimeStamp interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Check whether the specified RTC TimeStamp interrupt has occurred or not.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to check.\r\n  *         This parameter can be:\r\n  *            @arg RTC_IT_TS: TimeStamp interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__)        (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)\r\n\r\n/**\r\n  * @brief  Check whether the specified RTC Time Stamp interrupt has been enabled or not.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @param  __INTERRUPT__: specifies the RTC Time Stamp interrupt source to check.\r\n  *         This parameter can be:\r\n  *            @arg RTC_IT_TS: TimeStamp interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)\r\n\r\n/**\r\n  * @brief  Get the selected RTC TimeStamp's flag status.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @param  __FLAG__: specifies the RTC TimeStamp Flag is pending or not.\r\n  *         This parameter can be:\r\n  *            @arg RTC_FLAG_TSF\r\n  *            @arg RTC_FLAG_TSOVF\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)     (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)\r\n\r\n/**\r\n  * @brief  Clear the RTC Time Stamp's pending flags.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @param  __FLAG__: specifies the RTC Alarm Flag sources to clear.\r\n  *          This parameter can be:\r\n  *             @arg RTC_FLAG_TSF\r\n  *             @arg RTC_FLAG_TSOVF\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)   ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))\r\n\r\n/**\r\n  * @brief  Enable the RTC internal TimeStamp peripheral.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))\r\n\r\n/**\r\n  * @brief  Disable the RTC internal TimeStamp peripheral.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))\r\n\r\n/**\r\n  * @brief  Get the selected RTC Internal Time Stamp's flag status.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @param  __FLAG__: specifies the RTC Internal Time Stamp Flag is pending or not.\r\n  *         This parameter can be:\r\n  *            @arg RTC_FLAG_ITSF\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)    (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)\r\n\r\n/**\r\n  * @brief  Clear the RTC Internal Time Stamp's pending flags.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @param  __FLAG__: specifies the RTC Internal Time Stamp Flag source to clear.\r\n  *          This parameter can be:\r\n  *             @arg RTC_FLAG_ITSF\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)  ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0003FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))\r\n\r\n/**\r\n  * @brief  Enable the RTC calibration output.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))\r\n\r\n/**\r\n  * @brief  Disable the calibration output.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))\r\n\r\n/**\r\n  * @brief  Enable the clock reference detection.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))\r\n\r\n/**\r\n  * @brief  Disable the clock reference detection.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))\r\n\r\n/**\r\n  * @brief  Get the selected RTC shift operation's flag status.\r\n  * @param  __HANDLE__: specifies the RTC handle.\r\n  * @param  __FLAG__: specifies the RTC shift operation Flag is pending or not.\r\n  *          This parameter can be:\r\n  *             @arg RTC_FLAG_SHPF\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__)         (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)\r\n\r\n/**\r\n  * @brief  Enable interrupt on the RTC WakeUp Timer associated Exti line.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT()       (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)\r\n\r\n/**\r\n  * @brief  Disable interrupt on the RTC WakeUp Timer associated Exti line.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT()      (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))\r\n\r\n/**\r\n  * @brief  Enable event on the RTC WakeUp Timer associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT()    (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)\r\n\r\n/**\r\n  * @brief  Disable event on the RTC WakeUp Timer associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT()   (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))\r\n\r\n/**\r\n  * @brief  Enable falling edge trigger on the RTC WakeUp Timer associated Exti line. \r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)\r\n\r\n/**\r\n  * @brief  Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))\r\n\r\n/**\r\n  * @brief  Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)\r\n\r\n/**\r\n  * @brief  Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))\r\n\r\n/**\r\n  * @brief  Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();\r\n\r\n/**\r\n  * @brief  Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.\r\n  * This parameter can be:\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\r\n\r\n/**\r\n  * @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.\r\n  * @retval Line Status.\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG()              (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)\r\n\r\n/**\r\n  * @brief Clear the RTC WakeUp Timer associated Exti line flag.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG()            (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)\r\n\r\n/**\r\n  * @brief Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT()         (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)\r\n\r\n/**\r\n  * @brief  Enable interrupt on the RTC Tamper and Timestamp associated Exti line.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()        (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)\r\n\r\n/**\r\n  * @brief  Disable interrupt on the RTC Tamper and Timestamp associated Exti line.\r\n  * @retval None\r\n  */\r\n#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()       (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))\r\n\r\n/**\r\n  * @brief  Enable event on the RTC Tamper and Timestamp associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT()    (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)\r\n\r\n/**\r\n  * @brief  Disable event on the RTC Tamper and Timestamp associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT()   (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))\r\n\r\n/**\r\n  * @brief  Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line. \r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)\r\n\r\n/**\r\n  * @brief  Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))\r\n\r\n/**\r\n  * @brief  Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)\r\n\r\n/**\r\n  * @brief  Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))\r\n\r\n/**\r\n  * @brief  Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE();\r\n\r\n/**\r\n  * @brief  Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.\r\n  * This parameter can be:\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE();\r\n\r\n/**\r\n  * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.\r\n  * @retval Line Status.\r\n  */\r\n#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()         (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)\r\n\r\n/**\r\n  * @brief Clear the RTC Tamper and Timestamp associated Exti line flag.\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()       (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)\r\n\r\n/**\r\n  * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line\r\n  * @retval None.\r\n  */\r\n#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()    (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup RTCEx_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n\r\n/* RTC TimeStamp and Tamper functions *****************************************/\r\nHAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);\r\nHAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);\r\nHAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);\r\nHAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc);\r\nHAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc);\r\nHAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);\r\n\r\nHAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);\r\nHAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);\r\nHAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);\r\nvoid              HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);\r\n\r\nvoid              HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);\r\nvoid              HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);\r\nvoid              HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc);\r\nvoid              HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);\r\nHAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup RTCEx_Exported_Functions_Group2\r\n  * @{\r\n  */\r\n/* RTC Wake-up functions ******************************************************/\r\nHAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);\r\nHAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);\r\nuint32_t          HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);\r\nuint32_t          HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);\r\nvoid              HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);\r\nvoid              HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);\r\nHAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup RTCEx_Exported_Functions_Group3\r\n  * @{\r\n  */\r\n/* Extension Control functions ************************************************/\r\nvoid              HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);\r\nuint32_t          HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);\r\n\r\nHAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue);\r\nHAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);\r\nHAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);\r\nHAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);\r\nHAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);\r\nHAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);\r\nHAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);\r\nHAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup RTCEx_Exported_Functions_Group4\r\n  * @{\r\n  */\r\n/* Extension RTC features functions *******************************************/\r\nvoid              HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); \r\nHAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n/* Private types -------------------------------------------------------------*/ \r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup RTCEx_Private_Constants RTCEx Private Constants\r\n  * @{\r\n  */\r\n#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT  ((uint32_t)EXTI_IMR_IM21)  /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */                                               \r\n#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT       ((uint32_t)EXTI_IMR_IM22)  /*!< External interrupt line 22 Connected to the RTC Wake-up event */  \r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup RTCEx_Private_Constants RTCEx Private Constants\r\n  * @{\r\n  */\r\n/* Masks Definition */\r\n#define RTC_TAMPCR_TAMPXE     ((uint32_t) (RTC_TAMPCR_TAMP3E | RTC_TAMPCR_TAMP2E | RTC_TAMPCR_TAMP1E))\r\n#define RTC_TAMPCR_TAMPXIE    ((uint32_t) (RTC_TAMPER1_INTERRUPT | RTC_TAMPER2_INTERRUPT | RTC_TAMPER3_INTERRUPT | RTC_ALL_TAMPER_INTERRUPT))\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Private macros ------------------------------------------------------------*/   \r\n/** @defgroup RTCEx_Private_Macros RTCEx Private Macros\r\n  * @{\r\n  */\r\n\r\n/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters\r\n  * @{\r\n  */\r\n#define IS_RTC_OUTPUT(__OUTPUT__)      (((__OUTPUT__) == RTC_OUTPUT_DISABLE) || \\\r\n                                        ((__OUTPUT__) == RTC_OUTPUT_ALARMA)  || \\\r\n                                        ((__OUTPUT__) == RTC_OUTPUT_ALARMB)  || \\\r\n                                        ((__OUTPUT__) == RTC_OUTPUT_WAKEUP))\r\n#define IS_RTC_BKP(__BKP__)               ((__BKP__) < (uint32_t) RTC_BKP_NUMBER)\r\n#define IS_TIMESTAMP_EDGE(__EDGE__) (((__EDGE__) == RTC_TIMESTAMPEDGE_RISING) || \\\r\n                                     ((__EDGE__) == RTC_TIMESTAMPEDGE_FALLING))\r\n#define IS_RTC_TAMPER(__TAMPER__)   ((((__TAMPER__) & ((uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXE))) == 0x00U) && ((__TAMPER__) != (uint32_t)RESET))\r\n\r\n#define IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__)  ((((__INTERRUPT__) & (uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXIE)) == 0x00U) && ((__INTERRUPT__) != (uint32_t)RESET))\r\n\r\n#define IS_RTC_TIMESTAMP_PIN(__PIN__) (((__PIN__) == RTC_TIMESTAMPPIN_DEFAULT) || \\\r\n                                       ((__PIN__) == RTC_TIMESTAMPPIN_POS1)  || \\\r\n                                       ((__PIN__) == RTC_TIMESTAMPPIN_POS2))\r\n#define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE) || \\\r\n                                        ((__TRIGGER__) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \\\r\n                                        ((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL) || \\\r\n                                        ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL))\r\n#define IS_RTC_TAMPER_ERASE_MODE(__MODE__)             (((__MODE__) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \\\r\n                                                        ((__MODE__) == RTC_TAMPER_ERASE_BACKUP_DISABLE))\r\n#define IS_RTC_TAMPER_MASKFLAG_STATE(__STATE__)     (((__STATE__) == RTC_TAMPERMASK_FLAG_ENABLE) || \\\r\n                                                     ((__STATE__) == RTC_TAMPERMASK_FLAG_DISABLE))\r\n#define IS_RTC_TAMPER_FILTER(__FILTER__)  (((__FILTER__) == RTC_TAMPERFILTER_DISABLE) || \\\r\n                                       ((__FILTER__) == RTC_TAMPERFILTER_2SAMPLE) || \\\r\n                                       ((__FILTER__) == RTC_TAMPERFILTER_4SAMPLE) || \\\r\n                                       ((__FILTER__) == RTC_TAMPERFILTER_8SAMPLE))\r\n#define IS_RTC_TAMPER_SAMPLING_FREQ(__FREQ__) (((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \\\r\n                                           ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \\\r\n                                           ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \\\r\n                                           ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \\\r\n                                           ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \\\r\n                                           ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \\\r\n                                           ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512)  || \\\r\n                                           ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))\r\n#define IS_RTC_TAMPER_PRECHARGE_DURATION(__DURATION__) (((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \\\r\n                                                    ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \\\r\n                                                    ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \\\r\n                                                    ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))\r\n#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(__DETECTION__) (((__DETECTION__) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \\\r\n                                                              ((__DETECTION__) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))\r\n#define IS_RTC_TAMPER_PULLUP_STATE(__STATE__) (((__STATE__) == RTC_TAMPER_PULLUP_ENABLE) || \\\r\n                                       ((__STATE__) == RTC_TAMPER_PULLUP_DISABLE))\r\n#define IS_RTC_WAKEUP_CLOCK(__CLOCK__) (((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV16)       || \\\r\n                                    ((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV8)    || \\\r\n                                    ((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV4)    || \\\r\n                                    ((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV2)    || \\\r\n                                    ((__CLOCK__) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \\\r\n                                    ((__CLOCK__) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))\r\n\r\n#define IS_RTC_WAKEUP_COUNTER(__COUNTER__)  ((__COUNTER__) <= 0xFFFF)\r\n#define IS_RTC_SMOOTH_CALIB_PERIOD(__PERIOD__) (((__PERIOD__) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \\\r\n                                                ((__PERIOD__) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \\\r\n                                                ((__PERIOD__) == RTC_SMOOTHCALIB_PERIOD_8SEC))\r\n#define IS_RTC_SMOOTH_CALIB_PLUS(__PLUS__) (((__PLUS__) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \\\r\n                                            ((__PLUS__) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))\r\n#define  IS_RTC_SMOOTH_CALIB_MINUS(__VALUE__) ((__VALUE__) <= 0x000001FF)\r\n#define IS_RTC_SHIFT_ADD1S(__SEL__) (((__SEL__) == RTC_SHIFTADD1S_RESET) || \\\r\n                                     ((__SEL__) == RTC_SHIFTADD1S_SET))\r\n#define IS_RTC_SHIFT_SUBFS(__FS__) ((__FS__) <= 0x00007FFF)\r\n#define IS_RTC_CALIB_OUTPUT(__OUTPUT__)  (((__OUTPUT__) == RTC_CALIBOUTPUT_512HZ) || \\\r\n                                          ((__OUTPUT__) == RTC_CALIBOUTPUT_1HZ))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_RTC_EX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sai.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_sai.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of SAI HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_SAI_H\r\n#define __STM32F7xx_HAL_SAI_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup SAI\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup SAI_Exported_Types SAI Exported Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  HAL State structures definition\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_SAI_STATE_RESET    = 0x00U,  /*!< SAI not yet initialized or disabled                */\r\n  HAL_SAI_STATE_READY    = 0x01U,  /*!< SAI initialized and ready for use                  */\r\n  HAL_SAI_STATE_BUSY     = 0x02U,  /*!< SAI internal process is ongoing                    */\r\n  HAL_SAI_STATE_BUSY_TX  = 0x12U,  /*!< Data transmission process is ongoing               */\r\n  HAL_SAI_STATE_BUSY_RX  = 0x22U,  /*!< Data reception process is ongoing                  */\r\n}HAL_SAI_StateTypeDef;\r\n\r\n/**\r\n  * @brief  SAI Callback prototype\r\n  */\r\ntypedef void (*SAIcallback)(void);\r\n\r\n/** @defgroup SAI_Init_Structure_definition SAI Init Structure definition\r\n  * @brief  SAI Init Structure definition\r\n  * @{\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t AudioMode;           /*!< Specifies the SAI Block audio Mode.\r\n                                     This parameter can be a value of @ref SAI_Block_Mode */\r\n\r\n  uint32_t Synchro;             /*!< Specifies SAI Block synchronization\r\n                                     This parameter can be a value of @ref SAI_Block_Synchronization */\r\n\r\n  uint32_t SynchroExt;          /*!< Specifies SAI external output synchronization, this setup is common\r\n                                     for BlockA and BlockB\r\n                                     This parameter can be a value of @ref SAI_Block_SyncExt\r\n                                     @note: If both audio blocks of same SAI are used, this parameter has\r\n                                            to be set to the same value for each audio block */\r\n\r\n  uint32_t OutputDrive;         /*!< Specifies when SAI Block outputs are driven.\r\n                                     This parameter can be a value of @ref SAI_Block_Output_Drive\r\n                                     @note this value has to be set before enabling the audio block\r\n                                     but after the audio block configuration. */\r\n\r\n  uint32_t NoDivider;           /*!< Specifies whether master clock will be divided or not.\r\n                                     This parameter can be a value of @ref SAI_Block_NoDivider\r\n                                     @note: If bit NODIV in the SAI_xCR1 register is cleared, the frame length\r\n                                            should be aligned to a number equal to a power of 2, from 8 to 256.\r\n                                            If bit NODIV in the SAI_xCR1 register is set, the frame length can\r\n                                            take any of the values without constraint since the input clock of\r\n                                            the audio block should be equal to the bit clock.\r\n                                            There is no MCLK_x clock which can be output. */\r\n\r\n  uint32_t FIFOThreshold;       /*!< Specifies SAI Block FIFO threshold.\r\n                                     This parameter can be a value of @ref SAI_Block_Fifo_Threshold */\r\n\r\n  uint32_t AudioFrequency;      /*!< Specifies the audio frequency sampling.\r\n                                     This parameter can be a value of @ref SAI_Audio_Frequency */\r\n\r\n  uint32_t Mckdiv;              /*!< Specifies the master clock divider, the parameter will be used if for\r\n                                     AudioFrequency the user choice\r\n                                     This parameter must be a number between Min_Data = 0 and Max_Data = 15 */\r\n\r\n  uint32_t MonoStereoMode;      /*!< Specifies if the mono or stereo mode is selected.\r\n                                     This parameter can be a value of @ref SAI_Mono_Stereo_Mode */\r\n\r\n  uint32_t CompandingMode;      /*!< Specifies the companding mode type.\r\n                                     This parameter can be a value of @ref SAI_Block_Companding_Mode */\r\n\r\n  uint32_t TriState;            /*!< Specifies the companding mode type.\r\n                                     This parameter can be a value of @ref SAI_TRIState_Management */\r\n\r\n  /* This part of the structure is automatically filled if your are using the high level initialisation\r\n     function HAL_SAI_InitProtocol */\r\n\r\n  uint32_t Protocol;        /*!< Specifies the SAI Block protocol.\r\n                                 This parameter can be a value of @ref SAI_Block_Protocol */\r\n\r\n  uint32_t DataSize;        /*!< Specifies the SAI Block data size.\r\n                                 This parameter can be a value of @ref SAI_Block_Data_Size */\r\n\r\n  uint32_t FirstBit;        /*!< Specifies whether data transfers start from MSB or LSB bit.\r\n                                 This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */\r\n\r\n  uint32_t ClockStrobing;   /*!< Specifies the SAI Block clock strobing edge sensitivity.\r\n                                 This parameter can be a value of @ref SAI_Block_Clock_Strobing */\r\n}SAI_InitTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition\r\n  * @brief  SAI Frame Init structure definition\r\n  * @{\r\n  */\r\ntypedef struct\r\n{\r\n\r\n  uint32_t FrameLength;        /*!< Specifies the Frame length, the number of SCK clocks for each audio frame.\r\n                                    This parameter must be a number between Min_Data = 8 and Max_Data = 256.\r\n                                    @note: If master clock MCLK_x pin is declared as an output, the frame length\r\n                                           should be aligned to a number equal to power of 2 in order to keep\r\n                                           in an audio frame, an integer number of MCLK pulses by bit Clock. */\r\n\r\n  uint32_t ActiveFrameLength;  /*!< Specifies the Frame synchronization active level length.\r\n                                    This Parameter specifies the length in number of bit clock (SCK + 1)\r\n                                    of the active level of FS signal in audio frame.\r\n                                    This parameter must be a number between Min_Data = 1 and Max_Data = 128 */\r\n\r\n  uint32_t FSDefinition;       /*!< Specifies the Frame synchronization definition.\r\n                                    This parameter can be a value of @ref SAI_Block_FS_Definition */\r\n\r\n  uint32_t FSPolarity;         /*!< Specifies the Frame synchronization Polarity.\r\n                                    This parameter can be a value of @ref SAI_Block_FS_Polarity */\r\n\r\n  uint32_t FSOffset;           /*!< Specifies the Frame synchronization Offset.\r\n                                    This parameter can be a value of @ref SAI_Block_FS_Offset */\r\n\r\n}SAI_FrameInitTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition\r\n  * @brief   SAI Block Slot Init Structure definition\r\n  * @{\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t FirstBitOffset;  /*!< Specifies the position of first data transfer bit in the slot.\r\n                                 This parameter must be a number between Min_Data = 0 and Max_Data = 24 */\r\n\r\n  uint32_t SlotSize;        /*!< Specifies the Slot Size.\r\n                                 This parameter can be a value of @ref SAI_Block_Slot_Size */\r\n\r\n  uint32_t SlotNumber;      /*!< Specifies the number of slot in the audio frame.\r\n                                 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */\r\n\r\n  uint32_t SlotActive;      /*!< Specifies the slots in audio frame that will be activated.\r\n                                 This parameter can be a value of @ref SAI_Block_Slot_Active */\r\n}SAI_SlotInitTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Handle_Structure_definition SAI Handle Structure definition\r\n  * @brief  SAI handle Structure definition\r\n  * @{\r\n  */\r\ntypedef struct __SAI_HandleTypeDef\r\n{\r\n  SAI_Block_TypeDef         *Instance;    /*!< SAI Blockx registers base address */\r\n\r\n  SAI_InitTypeDef           Init;         /*!< SAI communication parameters */\r\n\r\n  SAI_FrameInitTypeDef      FrameInit;    /*!< SAI Frame configuration parameters */\r\n\r\n  SAI_SlotInitTypeDef       SlotInit;     /*!< SAI Slot configuration parameters */\r\n\r\n  uint8_t                  *pBuffPtr;     /*!< Pointer to SAI transfer Buffer */\r\n\r\n  uint16_t                  XferSize;     /*!< SAI transfer size */\r\n\r\n  uint16_t                  XferCount;    /*!< SAI transfer counter */\r\n\r\n  DMA_HandleTypeDef         *hdmatx;      /*!< SAI Tx DMA handle parameters */\r\n\r\n  DMA_HandleTypeDef         *hdmarx;      /*!< SAI Rx DMA handle parameters */\r\n\r\n  SAIcallback               mutecallback; /*!< SAI mute callback */\r\n\r\n  void (*InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai); /* function pointer for IRQ handler */\r\n\r\n  HAL_LockTypeDef           Lock;         /*!< SAI locking object */\r\n\r\n  __IO HAL_SAI_StateTypeDef State;        /*!< SAI communication state */\r\n\r\n  __IO uint32_t             ErrorCode;    /*!< SAI Error code */\r\n}SAI_HandleTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup SAI_Exported_Constants SAI Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup SAI_Error_Code SAI Error Code\r\n  * @{\r\n  */\r\n#define HAL_SAI_ERROR_NONE    ((uint32_t)0x00000000U)  /*!< No error                                    */\r\n#define HAL_SAI_ERROR_OVR     ((uint32_t)0x00000001U)  /*!< Overrun Error                               */\r\n#define HAL_SAI_ERROR_UDR     ((uint32_t)0x00000002U)  /*!< Underrun error                              */\r\n#define HAL_SAI_ERROR_AFSDET  ((uint32_t)0x00000004U)  /*!< Anticipated Frame synchronisation detection */\r\n#define HAL_SAI_ERROR_LFSDET  ((uint32_t)0x00000008U)  /*!< Late Frame synchronisation detection        */\r\n#define HAL_SAI_ERROR_CNREADY ((uint32_t)0x00000010U)  /*!< codec not ready                             */\r\n#define HAL_SAI_ERROR_WCKCFG  ((uint32_t)0x00000020U)  /*!< Wrong clock configuration                   */\r\n#define HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000040U)  /*!< Timeout error                               */\r\n#define HAL_SAI_ERROR_DMA     ((uint32_t)0x00000080U)  /*!< DMA error                                   */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_SyncExt SAI External synchronisation\r\n  * @{\r\n  */\r\n#define SAI_SYNCEXT_DISABLE          0\r\n#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1\r\n#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Protocol SAI Supported protocol\r\n  * @{\r\n  */\r\n#define SAI_I2S_STANDARD      0\r\n#define SAI_I2S_MSBJUSTIFIED  1\r\n#define SAI_I2S_LSBJUSTIFIED  2\r\n#define SAI_PCM_LONG          3\r\n#define SAI_PCM_SHORT         4\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Protocol_DataSize SAI protocol data size\r\n  * @{\r\n  */\r\n#define SAI_PROTOCOL_DATASIZE_16BIT         0\r\n#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1\r\n#define SAI_PROTOCOL_DATASIZE_24BIT         2\r\n#define SAI_PROTOCOL_DATASIZE_32BIT         3\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Audio_Frequency SAI Audio Frequency\r\n  * @{\r\n  */\r\n#define SAI_AUDIO_FREQUENCY_192K          ((uint32_t)192000U)\r\n#define SAI_AUDIO_FREQUENCY_96K           ((uint32_t)96000U)\r\n#define SAI_AUDIO_FREQUENCY_48K           ((uint32_t)48000U)\r\n#define SAI_AUDIO_FREQUENCY_44K           ((uint32_t)44100U)\r\n#define SAI_AUDIO_FREQUENCY_32K           ((uint32_t)32000U)\r\n#define SAI_AUDIO_FREQUENCY_22K           ((uint32_t)22050U)\r\n#define SAI_AUDIO_FREQUENCY_16K           ((uint32_t)16000U)\r\n#define SAI_AUDIO_FREQUENCY_11K           ((uint32_t)11025U)\r\n#define SAI_AUDIO_FREQUENCY_8K            ((uint32_t)8000U)\r\n#define SAI_AUDIO_FREQUENCY_MCKDIV        ((uint32_t)0U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_Mode SAI Block Mode\r\n  * @{\r\n  */\r\n#define SAI_MODEMASTER_TX         ((uint32_t)0x00000000U)\r\n#define SAI_MODEMASTER_RX         ((uint32_t)SAI_xCR1_MODE_0)\r\n#define SAI_MODESLAVE_TX          ((uint32_t)SAI_xCR1_MODE_1)\r\n#define SAI_MODESLAVE_RX          ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0))\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_Protocol SAI Block Protocol\r\n  * @{\r\n  */\r\n#define SAI_FREE_PROTOCOL                 ((uint32_t)0x00000000U)\r\n#define SAI_SPDIF_PROTOCOL                ((uint32_t)SAI_xCR1_PRTCFG_0)\r\n#define SAI_AC97_PROTOCOL                 ((uint32_t)SAI_xCR1_PRTCFG_1)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_Data_Size SAI Block Data Size\r\n  * @{\r\n  */\r\n#define SAI_DATASIZE_8     ((uint32_t)SAI_xCR1_DS_1)\r\n#define SAI_DATASIZE_10    ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0))\r\n#define SAI_DATASIZE_16    ((uint32_t)SAI_xCR1_DS_2)\r\n#define SAI_DATASIZE_20    ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0))\r\n#define SAI_DATASIZE_24    ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1))\r\n#define SAI_DATASIZE_32    ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission\r\n  * @{\r\n  */\r\n#define SAI_FIRSTBIT_MSB                  ((uint32_t)0x00000000U)\r\n#define SAI_FIRSTBIT_LSB                  ((uint32_t)SAI_xCR1_LSBFIRST)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing\r\n  * @{\r\n  */\r\n#define SAI_CLOCKSTROBING_FALLINGEDGE     0\r\n#define SAI_CLOCKSTROBING_RISINGEDGE      1\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_Synchronization SAI Block Synchronization\r\n  * @{\r\n  */\r\n#define SAI_ASYNCHRONOUS                  0 /*!< Asynchronous */\r\n#define SAI_SYNCHRONOUS                   1 /*!< Synchronous with other block of same SAI */\r\n#define SAI_SYNCHRONOUS_EXT_SAI1          2 /*!< Synchronous with other SAI, SAI1 */\r\n#define SAI_SYNCHRONOUS_EXT_SAI2          3 /*!< Synchronous with other SAI, SAI2 */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_Output_Drive SAI Block Output Drive\r\n  * @{\r\n  */\r\n#define SAI_OUTPUTDRIVE_DISABLE          ((uint32_t)0x00000000U)\r\n#define SAI_OUTPUTDRIVE_ENABLE           ((uint32_t)SAI_xCR1_OUTDRIV)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_NoDivider SAI Block NoDivider\r\n  * @{\r\n  */\r\n#define SAI_MASTERDIVIDER_ENABLE         ((uint32_t)0x00000000U)\r\n#define SAI_MASTERDIVIDER_DISABLE        ((uint32_t)SAI_xCR1_NODIV)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n\r\n/** @defgroup SAI_Block_FS_Definition SAI Block FS Definition\r\n  * @{\r\n  */\r\n#define SAI_FS_STARTFRAME                 ((uint32_t)0x00000000U)\r\n#define SAI_FS_CHANNEL_IDENTIFICATION     ((uint32_t)SAI_xFRCR_FSDEF)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity\r\n  * @{\r\n  */\r\n#define SAI_FS_ACTIVE_LOW                  ((uint32_t)0x00000000U)\r\n#define SAI_FS_ACTIVE_HIGH                 ((uint32_t)SAI_xFRCR_FSPOL)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_FS_Offset SAI Block FS Offset\r\n  * @{\r\n  */\r\n#define SAI_FS_FIRSTBIT                   ((uint32_t)0x00000000U)\r\n#define SAI_FS_BEFOREFIRSTBIT             ((uint32_t)SAI_xFRCR_FSOFF)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n\r\n  /** @defgroup SAI_Block_Slot_Size SAI Block Slot Size\r\n  * @{\r\n  */\r\n#define SAI_SLOTSIZE_DATASIZE             ((uint32_t)0x00000000U)\r\n#define SAI_SLOTSIZE_16B                  ((uint32_t)SAI_xSLOTR_SLOTSZ_0)\r\n#define SAI_SLOTSIZE_32B                  ((uint32_t)SAI_xSLOTR_SLOTSZ_1)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_Slot_Active SAI Block Slot Active\r\n  * @{\r\n  */\r\n#define SAI_SLOT_NOTACTIVE           ((uint32_t)0x00000000U)\r\n#define SAI_SLOTACTIVE_0             ((uint32_t)0x00000001U)\r\n#define SAI_SLOTACTIVE_1             ((uint32_t)0x00000002U)\r\n#define SAI_SLOTACTIVE_2             ((uint32_t)0x00000004U)\r\n#define SAI_SLOTACTIVE_3             ((uint32_t)0x00000008U)\r\n#define SAI_SLOTACTIVE_4             ((uint32_t)0x00000010U)\r\n#define SAI_SLOTACTIVE_5             ((uint32_t)0x00000020U)\r\n#define SAI_SLOTACTIVE_6             ((uint32_t)0x00000040U)\r\n#define SAI_SLOTACTIVE_7             ((uint32_t)0x00000080U)\r\n#define SAI_SLOTACTIVE_8             ((uint32_t)0x00000100U)\r\n#define SAI_SLOTACTIVE_9             ((uint32_t)0x00000200U)\r\n#define SAI_SLOTACTIVE_10            ((uint32_t)0x00000400U)\r\n#define SAI_SLOTACTIVE_11            ((uint32_t)0x00000800U)\r\n#define SAI_SLOTACTIVE_12            ((uint32_t)0x00001000U)\r\n#define SAI_SLOTACTIVE_13            ((uint32_t)0x00002000U)\r\n#define SAI_SLOTACTIVE_14            ((uint32_t)0x00004000U)\r\n#define SAI_SLOTACTIVE_15            ((uint32_t)0x00008000U)\r\n#define SAI_SLOTACTIVE_ALL           ((uint32_t)0x0000FFFFU)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode\r\n  * @{\r\n  */\r\n#define SAI_STEREOMODE               ((uint32_t)0x00000000U)\r\n#define SAI_MONOMODE                 ((uint32_t)SAI_xCR1_MONO)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_TRIState_Management SAI TRIState Management\r\n  * @{\r\n  */\r\n#define SAI_OUTPUT_NOTRELEASED        ((uint32_t)0x00000000U)\r\n#define SAI_OUTPUT_RELEASED           ((uint32_t)SAI_xCR2_TRIS)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold\r\n  * @{\r\n  */\r\n#define SAI_FIFOTHRESHOLD_EMPTY  ((uint32_t)0x00000000U)\r\n#define SAI_FIFOTHRESHOLD_1QF    ((uint32_t)(SAI_xCR2_FTH_0))\r\n#define SAI_FIFOTHRESHOLD_HF     ((uint32_t)(SAI_xCR2_FTH_1))\r\n#define SAI_FIFOTHRESHOLD_3QF    ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0))\r\n#define SAI_FIFOTHRESHOLD_FULL   ((uint32_t)(SAI_xCR2_FTH_2))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode\r\n  * @{\r\n  */\r\n#define SAI_NOCOMPANDING                 ((uint32_t)0x00000000U)\r\n#define SAI_ULAW_1CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1))\r\n#define SAI_ALAW_1CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0))\r\n#define SAI_ULAW_2CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL))\r\n#define SAI_ALAW_2CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_Mute_Value SAI Block Mute Value\r\n  * @{\r\n  */\r\n#define SAI_ZERO_VALUE                   ((uint32_t)0x00000000U)\r\n#define SAI_LAST_SENT_VALUE              ((uint32_t)SAI_xCR2_MUTEVAL)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition\r\n  * @{\r\n  */\r\n#define SAI_IT_OVRUDR                     ((uint32_t)SAI_xIMR_OVRUDRIE)\r\n#define SAI_IT_MUTEDET                    ((uint32_t)SAI_xIMR_MUTEDETIE)\r\n#define SAI_IT_WCKCFG                     ((uint32_t)SAI_xIMR_WCKCFGIE)\r\n#define SAI_IT_FREQ                       ((uint32_t)SAI_xIMR_FREQIE)\r\n#define SAI_IT_CNRDY                      ((uint32_t)SAI_xIMR_CNRDYIE)\r\n#define SAI_IT_AFSDET                     ((uint32_t)SAI_xIMR_AFSDETIE)\r\n#define SAI_IT_LFSDET                     ((uint32_t)SAI_xIMR_LFSDETIE)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_Flags_Definition  SAI Block Flags Definition\r\n  * @{\r\n  */\r\n#define SAI_FLAG_OVRUDR                   ((uint32_t)SAI_xSR_OVRUDR)\r\n#define SAI_FLAG_MUTEDET                  ((uint32_t)SAI_xSR_MUTEDET)\r\n#define SAI_FLAG_WCKCFG                   ((uint32_t)SAI_xSR_WCKCFG)\r\n#define SAI_FLAG_FREQ                     ((uint32_t)SAI_xSR_FREQ)\r\n#define SAI_FLAG_CNRDY                    ((uint32_t)SAI_xSR_CNRDY)\r\n#define SAI_FLAG_AFSDET                   ((uint32_t)SAI_xSR_AFSDET)\r\n#define SAI_FLAG_LFSDET                   ((uint32_t)SAI_xSR_LFSDET)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Block_Fifo_Status_Level   SAI Block Fifo Status Level\r\n  * @{\r\n  */\r\n#define SAI_FIFOSTATUS_EMPTY              ((uint32_t)0x00000000U)\r\n#define SAI_FIFOSTATUS_LESS1QUARTERFULL   ((uint32_t)0x00010000U)\r\n#define SAI_FIFOSTATUS_1QUARTERFULL       ((uint32_t)0x00020000U)\r\n#define SAI_FIFOSTATUS_HALFFULL           ((uint32_t)0x00030000U)\r\n#define SAI_FIFOSTATUS_3QUARTERFULL       ((uint32_t)0x00040000U)\r\n#define SAI_FIFOSTATUS_FULL               ((uint32_t)0x00050000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n\r\n/** @defgroup SAI_Exported_Macros SAI Exported Macros\r\n *  @brief macros to handle interrupts and specific configurations\r\n * @{\r\n */\r\n\r\n/** @brief Reset SAI handle state.\r\n  * @param  __HANDLE__: specifies the SAI Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)\r\n\r\n/** @brief  Enable or disable the specified SAI interrupts.\r\n  * @param  __HANDLE__: specifies the SAI Handle.\r\n  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable\r\n  *            @arg SAI_IT_MUTEDET: Mute detection interrupt enable\r\n  *            @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable\r\n  *            @arg SAI_IT_FREQ: FIFO request interrupt enable\r\n  *            @arg SAI_IT_CNRDY: Codec not ready interrupt enable\r\n  *            @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable\r\n  *            @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable\r\n  * @retval None\r\n  */\r\n#define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))\r\n#define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))\r\n\r\n/** @brief  Check whether the specified SAI interrupt source is enabled or not.\r\n  * @param  __HANDLE__: specifies the SAI Handle.\r\n  * @param  __INTERRUPT__: specifies the SAI interrupt source to check.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable\r\n  *            @arg SAI_IT_MUTEDET: Mute detection interrupt enable\r\n  *            @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable\r\n  *            @arg SAI_IT_FREQ: FIFO request interrupt enable\r\n  *            @arg SAI_IT_CNRDY: Codec not ready interrupt enable\r\n  *            @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable\r\n  *            @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable\r\n  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r\n\r\n/** @brief  Check whether the specified SAI flag is set or not.\r\n  * @param  __HANDLE__: specifies the SAI Handle.\r\n  * @param  __FLAG__: specifies the flag to check.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg SAI_FLAG_OVRUDR: Overrun underrun flag.\r\n  *            @arg SAI_FLAG_MUTEDET: Mute detection flag.\r\n  *            @arg SAI_FLAG_WCKCFG: Wrong Clock Configuration flag.\r\n  *            @arg SAI_FLAG_FREQ: FIFO request flag.\r\n  *            @arg SAI_FLAG_CNRDY: Codec not ready flag.\r\n  *            @arg SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag.\r\n  *            @arg SAI_FLAG_LFSDET: Late frame synchronization detection flag.\r\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))\r\n\r\n/** @brief  Clear the specified SAI pending flag.\r\n  * @param  __HANDLE__: specifies the SAI Handle.\r\n  * @param  __FLAG__: specifies the flag to check.\r\n  *          This parameter can be any combination of the following values:\r\n  *            @arg SAI_FLAG_OVRUDR: Clear Overrun underrun\r\n  *            @arg SAI_FLAG_MUTEDET: Clear Mute detection\r\n  *            @arg SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration\r\n  *            @arg SAI_FLAG_FREQ: Clear FIFO request\r\n  *            @arg SAI_FLAG_CNRDY: Clear Codec not ready\r\n  *            @arg SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection\r\n  *            @arg SAI_FLAG_LFSDET: Clear Late frame synchronization detection\r\n  *\r\n  * @retval None\r\n  */\r\n#define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))\r\n\r\n#define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |=  SAI_xCR1_SAIEN)\r\n#define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &=  ~SAI_xCR1_SAIEN)\r\n\r\n /**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @addtogroup SAI_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/* Initialization/de-initialization functions  ********************************/\r\n\r\n/** @addtogroup SAI_Exported_Functions_Group1\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);\r\nHAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai);\r\nHAL_StatusTypeDef HAL_SAI_DeInit (SAI_HandleTypeDef *hsai);\r\nvoid HAL_SAI_MspInit(SAI_HandleTypeDef *hsai);\r\nvoid HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* I/O operation functions  ***************************************************/\r\n\r\n/** @addtogroup SAI_Exported_Functions_Group2\r\n  * @{\r\n  */\r\n/* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r\n\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);\r\n\r\n/* Non-Blocking mode: DMA */\r\nHAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai);\r\nHAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai);\r\nHAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai);\r\n\r\n/* Abort function */\r\nHAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai);\r\n\r\n/* Mute management */\r\nHAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val);\r\nHAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai);\r\nHAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter);\r\nHAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai);\r\n\r\n/* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */\r\nvoid HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai);\r\nvoid HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai);\r\nvoid HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai);\r\nvoid HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai);\r\nvoid HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai);\r\nvoid HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup SAI_Exported_Functions_Group3\r\n  * @{\r\n  */\r\n/* Peripheral State functions  ************************************************/\r\nHAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai);\r\nuint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @addtogroup SAI_Private_Macros\r\n  * @{\r\n  */\r\n#define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE)          ||\\\r\n                                     ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\\\r\n                                     ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE))\r\n\r\n#define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL)   (((PROTOCOL) == SAI_I2S_STANDARD)     ||\\\r\n                                               ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\\\r\n                                               ((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\\\r\n                                               ((PROTOCOL) == SAI_PCM_LONG)         ||\\\r\n                                               ((PROTOCOL) == SAI_PCM_SHORT))\r\n\r\n#define IS_SAI_PROTOCOL_DATASIZE(DATASIZE)   (((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT)         ||\\\r\n                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\\\r\n                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT)         ||\\\r\n                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT))\r\n\r\n#define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \\\r\n                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_48K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \\\r\n                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_32K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \\\r\n                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_16K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \\\r\n                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_8K)   || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV))\r\n\r\n#define IS_SAI_BLOCK_MODE(MODE)  (((MODE) == SAI_MODEMASTER_TX) || \\\r\n                                  ((MODE) == SAI_MODEMASTER_RX) || \\\r\n                                  ((MODE) == SAI_MODESLAVE_TX)  || \\\r\n                                  ((MODE) == SAI_MODESLAVE_RX))\r\n\r\n#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL)  || \\\r\n                                         ((PROTOCOL) == SAI_AC97_PROTOCOL)  || \\\r\n                                         ((PROTOCOL) == SAI_SPDIF_PROTOCOL))\r\n\r\n#define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8)  || \\\r\n                                         ((DATASIZE) == SAI_DATASIZE_10) || \\\r\n                                         ((DATASIZE) == SAI_DATASIZE_16) || \\\r\n                                         ((DATASIZE) == SAI_DATASIZE_20) || \\\r\n                                         ((DATASIZE) == SAI_DATASIZE_24) || \\\r\n                                         ((DATASIZE) == SAI_DATASIZE_32))\r\n\r\n#define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || \\\r\n                                     ((BIT) == SAI_FIRSTBIT_LSB))\r\n\r\n#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \\\r\n                                            ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))\r\n\r\n#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS)         || \\\r\n                                       ((SYNCHRO) == SAI_SYNCHRONOUS)          || \\\r\n                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) || \\\r\n                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2))\r\n\r\n#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \\\r\n                                          ((DRIVE) == SAI_OUTPUTDRIVE_ENABLE))\r\n\r\n#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \\\r\n                                           ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE))\r\n\r\n#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63)\r\n\r\n#define IS_SAI_BLOCK_MUTE_VALUE(VALUE)    (((VALUE) == SAI_ZERO_VALUE)     || \\\r\n                                           ((VALUE) == SAI_LAST_SENT_VALUE))\r\n\r\n#define IS_SAI_BLOCK_COMPANDING_MODE(MODE)    (((MODE) == SAI_NOCOMPANDING)         || \\\r\n                                               ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \\\r\n                                               ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \\\r\n                                               ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \\\r\n                                               ((MODE) == SAI_ALAW_2CPL_COMPANDING))\r\n\r\n#define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY)   || \\\r\n                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF)     || \\\r\n                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF)      || \\\r\n                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF)     || \\\r\n                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL))\r\n\r\n#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\\\r\n                                                 ((STATE) == SAI_OUTPUT_RELEASED))\r\n\r\n#define IS_SAI_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\\\r\n                                       ((MODE) == SAI_STEREOMODE))\r\n\r\n#define IS_SAI_SLOT_ACTIVE(ACTIVE)  ((ACTIVE) <= SAI_SLOTACTIVE_ALL)\r\n\r\n#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16))\r\n\r\n#define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \\\r\n                                      ((SIZE) == SAI_SLOTSIZE_16B)      || \\\r\n                                      ((SIZE) == SAI_SLOTSIZE_32B))\r\n\r\n#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24)\r\n\r\n#define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \\\r\n                                        ((OFFSET) == SAI_FS_BEFOREFIRSTBIT))\r\n\r\n#define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \\\r\n                                            ((POLARITY) == SAI_FS_ACTIVE_HIGH))\r\n\r\n#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \\\r\n                                                ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))\r\n\r\n#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15)\r\n\r\n#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256))\r\n\r\n#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128))\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup SAI_Private_Functions SAI Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_SAI_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sai_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_sai_ex.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of SAI Extension HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_SAI_EX_H\r\n#define __STM32F7xx_HAL_SAI_EX_H\r\n\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/    \r\n/* Exported functions --------------------------------------------------------*/\r\n/* Extended features functions ************************************************/\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/* Private macros ------------------------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n#endif /* __STM32F7xx_HAL_SAI_EX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_sd.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of SD HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_SD_H\r\n#define __STM32F7xx_HAL_SD_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_ll_sdmmc.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup SD SD\r\n  * @brief SD HAL module driver\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/ \r\n/** @defgroup SD_Exported_Types SD Exported Types\r\n  * @{\r\n  */\r\n\r\n/** @defgroup SD_Exported_Types_Group1 SD Handle Structure definition   \r\n  * @{\r\n  */\r\n#define SD_InitTypeDef      SDMMC_InitTypeDef \r\n#define SD_TypeDef          SDMMC_TypeDef\r\n\r\ntypedef struct\r\n{\r\n  SD_TypeDef                   *Instance;        /*!< SDMMC register base address                     */\r\n  \r\n  SD_InitTypeDef               Init;             /*!< SD required parameters                         */\r\n  \r\n  HAL_LockTypeDef              Lock;             /*!< SD locking object                              */\r\n  \r\n  uint32_t                     CardType;         /*!< SD card type                                   */\r\n  \r\n  uint32_t                     RCA;              /*!< SD relative card address                       */\r\n  \r\n  uint32_t                     CSD[4];           /*!< SD card specific data table                    */\r\n  \r\n  uint32_t                     CID[4];           /*!< SD card identification number table            */\r\n  \r\n  __IO uint32_t                SdTransferCplt;   /*!< SD transfer complete flag in non blocking mode */\r\n  \r\n  __IO uint32_t                SdTransferErr;    /*!< SD transfer error flag in non blocking mode    */\r\n  \r\n  __IO uint32_t                DmaTransferCplt;  /*!< SD DMA transfer complete flag                  */\r\n  \r\n  __IO uint32_t                SdOperation;      /*!< SD transfer operation (read/write)             */\r\n  \r\n  DMA_HandleTypeDef            *hdmarx;          /*!< SD Rx DMA handle parameters                    */\r\n  \r\n  DMA_HandleTypeDef            *hdmatx;          /*!< SD Tx DMA handle parameters                    */\r\n  \r\n}SD_HandleTypeDef;\r\n/** \r\n  * @}\r\n  */\r\n\r\n/** @defgroup SD_Exported_Types_Group2 Card Specific Data: CSD Register \r\n  * @{\r\n  */ \r\ntypedef struct\r\n{\r\n  __IO uint8_t  CSDStruct;            /*!< CSD structure                         */\r\n  __IO uint8_t  SysSpecVersion;       /*!< System specification version          */\r\n  __IO uint8_t  Reserved1;            /*!< Reserved                              */\r\n  __IO uint8_t  TAAC;                 /*!< Data read access time 1               */\r\n  __IO uint8_t  NSAC;                 /*!< Data read access time 2 in CLK cycles */\r\n  __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency              */\r\n  __IO uint16_t CardComdClasses;      /*!< Card command classes                  */\r\n  __IO uint8_t  RdBlockLen;           /*!< Max. read data block length           */\r\n  __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed       */\r\n  __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment              */\r\n  __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment               */\r\n  __IO uint8_t  DSRImpl;              /*!< DSR implemented                       */\r\n  __IO uint8_t  Reserved2;            /*!< Reserved                              */\r\n  __IO uint32_t DeviceSize;           /*!< Device Size                           */\r\n  __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min           */\r\n  __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max           */\r\n  __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min          */\r\n  __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max          */\r\n  __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier                */\r\n  __IO uint8_t  EraseGrSize;          /*!< Erase group size                      */\r\n  __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier           */\r\n  __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size              */\r\n  __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable            */\r\n  __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC              */\r\n  __IO uint8_t  WrSpeedFact;          /*!< Write speed factor                    */\r\n  __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length          */\r\n  __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed      */\r\n  __IO uint8_t  Reserved3;            /*!< Reserved                              */\r\n  __IO uint8_t  ContentProtectAppli;  /*!< Content protection application        */\r\n  __IO uint8_t  FileFormatGrouop;     /*!< File format group                     */\r\n  __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP)                       */\r\n  __IO uint8_t  PermWrProtect;        /*!< Permanent write protection            */\r\n  __IO uint8_t  TempWrProtect;        /*!< Temporary write protection            */\r\n  __IO uint8_t  FileFormat;           /*!< File format                           */\r\n  __IO uint8_t  ECC;                  /*!< ECC code                              */\r\n  __IO uint8_t  CSD_CRC;              /*!< CSD CRC                               */\r\n  __IO uint8_t  Reserved4;            /*!< Always 1                              */\r\n\r\n}HAL_SD_CSDTypedef;\r\n/** \r\n  * @}\r\n  */\r\n\r\n/** @defgroup SD_Exported_Types_Group3 Card Identification Data: CID Register\r\n  * @{\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint8_t  ManufacturerID;  /*!< Manufacturer ID       */\r\n  __IO uint16_t OEM_AppliID;     /*!< OEM/Application ID    */\r\n  __IO uint32_t ProdName1;       /*!< Product Name part1    */\r\n  __IO uint8_t  ProdName2;       /*!< Product Name part2    */\r\n  __IO uint8_t  ProdRev;         /*!< Product Revision      */\r\n  __IO uint32_t ProdSN;          /*!< Product Serial Number */\r\n  __IO uint8_t  Reserved1;       /*!< Reserved1             */\r\n  __IO uint16_t ManufactDate;    /*!< Manufacturing Date    */\r\n  __IO uint8_t  CID_CRC;         /*!< CID CRC               */\r\n  __IO uint8_t  Reserved2;       /*!< Always 1              */\r\n\r\n}HAL_SD_CIDTypedef;\r\n/** \r\n  * @}\r\n  */\r\n\r\n/** @defgroup SD_Exported_Types_Group4 SD Card Status returned by ACMD13 \r\n  * @{\r\n  */\r\ntypedef struct\r\n{\r\n  __IO uint8_t  DAT_BUS_WIDTH;           /*!< Shows the currently defined data bus width                 */\r\n  __IO uint8_t  SECURED_MODE;            /*!< Card is in secured mode of operation                       */\r\n  __IO uint16_t SD_CARD_TYPE;            /*!< Carries information about card type                        */\r\n  __IO uint32_t SIZE_OF_PROTECTED_AREA;  /*!< Carries information about the capacity of protected area   */\r\n  __IO uint8_t  SPEED_CLASS;             /*!< Carries information about the speed class of the card      */\r\n  __IO uint8_t  PERFORMANCE_MOVE;        /*!< Carries information about the card's performance move      */\r\n  __IO uint8_t  AU_SIZE;                 /*!< Carries information about the card's allocation unit size  */\r\n  __IO uint16_t ERASE_SIZE;              /*!< Determines the number of AUs to be erased in one operation */\r\n  __IO uint8_t  ERASE_TIMEOUT;           /*!< Determines the timeout for any number of AU erase          */\r\n  __IO uint8_t  ERASE_OFFSET;            /*!< Carries information about the erase offset                 */\r\n\r\n}HAL_SD_CardStatusTypedef;\r\n/** \r\n  * @}\r\n  */\r\n\r\n/** @defgroup SD_Exported_Types_Group5 SD Card information structure \r\n  * @{\r\n  */\r\ntypedef struct\r\n{\r\n  HAL_SD_CSDTypedef   SD_csd;         /*!< SD card specific data register         */\r\n  HAL_SD_CIDTypedef   SD_cid;         /*!< SD card identification number register */\r\n  uint64_t            CardCapacity;   /*!< Card capacity                          */\r\n  uint32_t            CardBlockSize;  /*!< Card block size                        */\r\n  uint16_t            RCA;            /*!< SD relative card address               */\r\n  uint8_t             CardType;       /*!< SD card type                           */\r\n\r\n}HAL_SD_CardInfoTypedef;\r\n/** \r\n  * @}\r\n  */\r\n\r\n/** @defgroup SD_Exported_Types_Group6 SD Error status enumeration Structure definition \r\n  * @{\r\n  */\r\ntypedef enum\r\n{\r\n/** \r\n  * @brief  SD specific error defines  \r\n  */   \r\n  SD_CMD_CRC_FAIL                    = (1),   /*!< Command response received (but CRC check failed)              */\r\n  SD_DATA_CRC_FAIL                   = (2),   /*!< Data block sent/received (CRC check failed)                   */\r\n  SD_CMD_RSP_TIMEOUT                 = (3),   /*!< Command response timeout                                      */\r\n  SD_DATA_TIMEOUT                    = (4),   /*!< Data timeout                                                  */\r\n  SD_TX_UNDERRUN                     = (5),   /*!< Transmit FIFO underrun                                        */\r\n  SD_RX_OVERRUN                      = (6),   /*!< Receive FIFO overrun                                          */\r\n  SD_START_BIT_ERR                   = (7),   /*!< Start bit not detected on all data signals in wide bus mode   */\r\n  SD_CMD_OUT_OF_RANGE                = (8),   /*!< Command's argument was out of range.                          */\r\n  SD_ADDR_MISALIGNED                 = (9),   /*!< Misaligned address                                            */\r\n  SD_BLOCK_LEN_ERR                   = (10),  /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */\r\n  SD_ERASE_SEQ_ERR                   = (11),  /*!< An error in the sequence of erase command occurs.            */\r\n  SD_BAD_ERASE_PARAM                 = (12),  /*!< An invalid selection for erase groups                        */\r\n  SD_WRITE_PROT_VIOLATION            = (13),  /*!< Attempt to program a write protect block                     */\r\n  SD_LOCK_UNLOCK_FAILED              = (14),  /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */\r\n  SD_COM_CRC_FAILED                  = (15),  /*!< CRC check of the previous command failed                     */\r\n  SD_ILLEGAL_CMD                     = (16),  /*!< Command is not legal for the card state                      */\r\n  SD_CARD_ECC_FAILED                 = (17),  /*!< Card internal ECC was applied but failed to correct the data */\r\n  SD_CC_ERROR                        = (18),  /*!< Internal card controller error                               */\r\n  SD_GENERAL_UNKNOWN_ERROR           = (19),  /*!< General or unknown error                                     */\r\n  SD_STREAM_READ_UNDERRUN            = (20),  /*!< The card could not sustain data transfer in stream read operation. */\r\n  SD_STREAM_WRITE_OVERRUN            = (21),  /*!< The card could not sustain data programming in stream mode   */\r\n  SD_CID_CSD_OVERWRITE               = (22),  /*!< CID/CSD overwrite error                                      */\r\n  SD_WP_ERASE_SKIP                   = (23),  /*!< Only partial address space was erased                        */\r\n  SD_CARD_ECC_DISABLED               = (24),  /*!< Command has been executed without using internal ECC         */\r\n  SD_ERASE_RESET                     = (25),  /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */\r\n  SD_AKE_SEQ_ERROR                   = (26),  /*!< Error in sequence of authentication.                         */\r\n  SD_INVALID_VOLTRANGE               = (27),\r\n  SD_ADDR_OUT_OF_RANGE               = (28),\r\n  SD_SWITCH_ERROR                    = (29),\r\n  SD_SDMMC_DISABLED                  = (30),\r\n  SD_SDMMC_FUNCTION_BUSY             = (31),\r\n  SD_SDMMC_FUNCTION_FAILED           = (32),\r\n  SD_SDMMC_UNKNOWN_FUNCTION          = (33),\r\n\r\n/** \r\n  * @brief  Standard error defines   \r\n  */ \r\n  SD_INTERNAL_ERROR                  = (34),\r\n  SD_NOT_CONFIGURED                  = (35),\r\n  SD_REQUEST_PENDING                 = (36),\r\n  SD_REQUEST_NOT_APPLICABLE          = (37),\r\n  SD_INVALID_PARAMETER               = (38),\r\n  SD_UNSUPPORTED_FEATURE             = (39),\r\n  SD_UNSUPPORTED_HW                  = (40),\r\n  SD_ERROR                           = (41),\r\n  SD_OK                              = (0) \r\n\r\n}HAL_SD_ErrorTypedef;\r\n/** \r\n  * @}\r\n  */\r\n\r\n/** @defgroup SD_Exported_Types_Group7 SD Transfer state enumeration structure\r\n  * @{\r\n  */   \r\ntypedef enum\r\n{\r\n  SD_TRANSFER_OK    = 0,  /*!< Transfer success      */\r\n  SD_TRANSFER_BUSY  = 1,  /*!< Transfer is occurring */\r\n  SD_TRANSFER_ERROR = 2   /*!< Transfer failed       */\r\n\r\n}HAL_SD_TransferStateTypedef;\r\n/** \r\n  * @}\r\n  */\r\n\r\n/** @defgroup SD_Exported_Types_Group8 SD Card State enumeration structure\r\n  * @{\r\n  */   \r\ntypedef enum\r\n{\r\n  SD_CARD_READY                  = ((uint32_t)0x00000001U),  /*!< Card state is ready                     */\r\n  SD_CARD_IDENTIFICATION         = ((uint32_t)0x00000002U),  /*!< Card is in identification state         */\r\n  SD_CARD_STANDBY                = ((uint32_t)0x00000003U),  /*!< Card is in standby state                */\r\n  SD_CARD_TRANSFER               = ((uint32_t)0x00000004U),  /*!< Card is in transfer state               */  \r\n  SD_CARD_SENDING                = ((uint32_t)0x00000005U),  /*!< Card is sending an operation            */\r\n  SD_CARD_RECEIVING              = ((uint32_t)0x00000006U),  /*!< Card is receiving operation information */\r\n  SD_CARD_PROGRAMMING            = ((uint32_t)0x00000007U),  /*!< Card is in programming state            */\r\n  SD_CARD_DISCONNECTED           = ((uint32_t)0x00000008U),  /*!< Card is disconnected                    */\r\n  SD_CARD_ERROR                  = ((uint32_t)0x000000FFU)   /*!< Card is in error state                  */\r\n\r\n}HAL_SD_CardStateTypedef;\r\n/** \r\n  * @}\r\n  */\r\n\r\n/** @defgroup SD_Exported_Types_Group9 SD Operation enumeration structure\r\n  * @{\r\n  */   \r\ntypedef enum\r\n{\r\n  SD_READ_SINGLE_BLOCK    = 0U,  /*!< Read single block operation      */\r\n  SD_READ_MULTIPLE_BLOCK  = 1U,  /*!< Read multiple blocks operation   */\r\n  SD_WRITE_SINGLE_BLOCK   = 2U,  /*!< Write single block operation     */\r\n  SD_WRITE_MULTIPLE_BLOCK = 3U   /*!< Write multiple blocks operation  */\r\n\r\n}HAL_SD_OperationTypedef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup SD_Exported_Constants SD Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** \r\n  * @brief SD Commands Index \r\n  */\r\n#define SD_CMD_GO_IDLE_STATE                       ((uint8_t)0U)   /*!< Resets the SD memory card.                                                               */\r\n#define SD_CMD_SEND_OP_COND                        ((uint8_t)1U)   /*!< Sends host capacity support information and activates the card's initialization process. */\r\n#define SD_CMD_ALL_SEND_CID                        ((uint8_t)2U)   /*!< Asks any card connected to the host to send the CID numbers on the CMD line.             */\r\n#define SD_CMD_SET_REL_ADDR                        ((uint8_t)3U)   /*!< Asks the card to publish a new relative address (RCA).                                   */\r\n#define SD_CMD_SET_DSR                             ((uint8_t)4U)   /*!< Programs the DSR of all cards.                                                           */\r\n#define SD_CMD_SDMMC_SEN_OP_COND                   ((uint8_t)5U)   /*!< Sends host capacity support information (HCS) and asks the accessed card to send its \r\n                                                                       operating condition register (OCR) content in the response on the CMD line.              */\r\n#define SD_CMD_HS_SWITCH                           ((uint8_t)6U)   /*!< Checks switchable function (mode 0) and switch card function (mode 1).                   */\r\n#define SD_CMD_SEL_DESEL_CARD                      ((uint8_t)7U)   /*!< Selects the card by its own relative address and gets deselected by any other address    */\r\n#define SD_CMD_HS_SEND_EXT_CSD                     ((uint8_t)8U)   /*!< Sends SD Memory Card interface condition, which includes host supply voltage information \r\n                                                                       and asks the card whether card supports voltage.                                         */\r\n#define SD_CMD_SEND_CSD                            ((uint8_t)9U)   /*!< Addressed card sends its card specific data (CSD) on the CMD line.                       */\r\n#define SD_CMD_SEND_CID                            ((uint8_t)10U)  /*!< Addressed card sends its card identification (CID) on the CMD line.                      */\r\n#define SD_CMD_READ_DAT_UNTIL_STOP                 ((uint8_t)11U)  /*!< SD card doesn't support it.                                                              */\r\n#define SD_CMD_STOP_TRANSMISSION                   ((uint8_t)12U)  /*!< Forces the card to stop transmission.                                                    */\r\n#define SD_CMD_SEND_STATUS                         ((uint8_t)13U)  /*!< Addressed card sends its status register.                                                */\r\n#define SD_CMD_HS_BUSTEST_READ                     ((uint8_t)14U) \r\n#define SD_CMD_GO_INACTIVE_STATE                   ((uint8_t)15U)  /*!< Sends an addressed card into the inactive state.                                         */\r\n#define SD_CMD_SET_BLOCKLEN                        ((uint8_t)16U)  /*!< Sets the block length (in bytes for SDSC) for all following block commands \r\n                                                                       (read, write, lock). Default block length is fixed to 512 Bytes. Not effective \r\n                                                                       for SDHS and SDXC.                                                                       */\r\n#define SD_CMD_READ_SINGLE_BLOCK                   ((uint8_t)17U)  /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of \r\n                                                                       fixed 512 bytes in case of SDHC and SDXC.                                                */\r\n#define SD_CMD_READ_MULT_BLOCK                     ((uint8_t)18U)  /*!< Continuously transfers data blocks from card to host until interrupted by \r\n                                                                       STOP_TRANSMISSION command.                                                               */\r\n#define SD_CMD_HS_BUSTEST_WRITE                    ((uint8_t)19U)  /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104.                                    */\r\n#define SD_CMD_WRITE_DAT_UNTIL_STOP                ((uint8_t)20U)  /*!< Speed class control command.                                                             */\r\n#define SD_CMD_SET_BLOCK_COUNT                     ((uint8_t)23U)  /*!< Specify block count for CMD18 and CMD25.                                                 */\r\n#define SD_CMD_WRITE_SINGLE_BLOCK                  ((uint8_t)24U)  /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of \r\n                                                                       fixed 512 bytes in case of SDHC and SDXC.                                                */\r\n#define SD_CMD_WRITE_MULT_BLOCK                    ((uint8_t)25U)  /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows.                    */\r\n#define SD_CMD_PROG_CID                            ((uint8_t)26U)  /*!< Reserved for manufacturers.                                                              */\r\n#define SD_CMD_PROG_CSD                            ((uint8_t)27U)  /*!< Programming of the programmable bits of the CSD.                                         */\r\n#define SD_CMD_SET_WRITE_PROT                      ((uint8_t)28U)  /*!< Sets the write protection bit of the addressed group.                                    */\r\n#define SD_CMD_CLR_WRITE_PROT                      ((uint8_t)29U)  /*!< Clears the write protection bit of the addressed group.                                  */\r\n#define SD_CMD_SEND_WRITE_PROT                     ((uint8_t)30U)  /*!< Asks the card to send the status of the write protection bits.                           */\r\n#define SD_CMD_SD_ERASE_GRP_START                  ((uint8_t)32U)  /*!< Sets the address of the first write block to be erased. (For SD card only).              */\r\n#define SD_CMD_SD_ERASE_GRP_END                    ((uint8_t)33U)  /*!< Sets the address of the last write block of the continuous range to be erased.           */\r\n#define SD_CMD_ERASE_GRP_START                     ((uint8_t)35U)  /*!< Sets the address of the first write block to be erased. Reserved for each command \r\n                                                                       system set by switch function command (CMD6).                                            */\r\n#define SD_CMD_ERASE_GRP_END                       ((uint8_t)36U)  /*!< Sets the address of the last write block of the continuous range to be erased. \r\n                                                                       Reserved for each command system set by switch function command (CMD6).                  */\r\n#define SD_CMD_ERASE                               ((uint8_t)38U)  /*!< Reserved for SD security applications.                                                   */\r\n#define SD_CMD_FAST_IO                             ((uint8_t)39U)  /*!< SD card doesn't support it (Reserved).                                                   */\r\n#define SD_CMD_GO_IRQ_STATE                        ((uint8_t)40U)  /*!< SD card doesn't support it (Reserved).                                                   */\r\n#define SD_CMD_LOCK_UNLOCK                         ((uint8_t)42U)  /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by \r\n                                                                       the SET_BLOCK_LEN command.                                                               */\r\n#define SD_CMD_APP_CMD                             ((uint8_t)55U)  /*!< Indicates to the card that the next command is an application specific command rather \r\n                                                                       than a standard command.                                                                 */\r\n#define SD_CMD_GEN_CMD                             ((uint8_t)56U)  /*!< Used either to transfer a data block to the card or to get a data block from the card \r\n                                                                       for general purpose/application specific commands.                                       */\r\n#define SD_CMD_NO_CMD                              ((uint8_t)64U) \r\n\r\n/** \r\n  * @brief Following commands are SD Card Specific commands.\r\n  *        SDMMC_APP_CMD should be sent before sending these commands. \r\n  */\r\n#define SD_CMD_APP_SD_SET_BUSWIDTH                 ((uint8_t)6U)   /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus \r\n                                                                       widths are given in SCR register.                                                          */\r\n#define SD_CMD_SD_APP_STATUS                       ((uint8_t)13U)  /*!< (ACMD13) Sends the SD status.                                                              */\r\n#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS        ((uint8_t)22U)  /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with \r\n                                                                       32bit+CRC data block.                                                                      */\r\n#define SD_CMD_SD_APP_OP_COND                      ((uint8_t)41U)  /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to \r\n                                                                       send its operating condition register (OCR) content in the response on the CMD line.       */\r\n#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT          ((uint8_t)42U)  /*!< (ACMD42) Connects/Disconnects the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card. */\r\n#define SD_CMD_SD_APP_SEND_SCR                     ((uint8_t)51U)  /*!< Reads the SD Configuration Register (SCR).                                                 */\r\n#define SD_CMD_SDMMC_RW_DIRECT                     ((uint8_t)52U)  /*!< For SD I/O card only, reserved for security specification.                                 */\r\n#define SD_CMD_SDMMC_RW_EXTENDED                   ((uint8_t)53U)  /*!< For SD I/O card only, reserved for security specification.                                 */\r\n\r\n/** \r\n  * @brief Following commands are SD Card Specific security commands.\r\n  *        SD_CMD_APP_CMD should be sent before sending these commands. \r\n  */\r\n#define SD_CMD_SD_APP_GET_MKB                      ((uint8_t)43U)  /*!< For SD card only */\r\n#define SD_CMD_SD_APP_GET_MID                      ((uint8_t)44U)  /*!< For SD card only */\r\n#define SD_CMD_SD_APP_SET_CER_RN1                  ((uint8_t)45U)  /*!< For SD card only */\r\n#define SD_CMD_SD_APP_GET_CER_RN2                  ((uint8_t)46U)  /*!< For SD card only */\r\n#define SD_CMD_SD_APP_SET_CER_RES2                 ((uint8_t)47U)  /*!< For SD card only */\r\n#define SD_CMD_SD_APP_GET_CER_RES1                 ((uint8_t)48U)  /*!< For SD card only */\r\n#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK   ((uint8_t)18U)  /*!< For SD card only */\r\n#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK  ((uint8_t)25U)  /*!< For SD card only */\r\n#define SD_CMD_SD_APP_SECURE_ERASE                 ((uint8_t)38U)  /*!< For SD card only */\r\n#define SD_CMD_SD_APP_CHANGE_SECURE_AREA           ((uint8_t)49U)  /*!< For SD card only */\r\n#define SD_CMD_SD_APP_SECURE_WRITE_MKB             ((uint8_t)48U)  /*!< For SD card only */\r\n\r\n/** \r\n  * @brief Supported SD Memory Cards \r\n  */\r\n#define STD_CAPACITY_SD_CARD_V1_1             ((uint32_t)0x00000000U)\r\n#define STD_CAPACITY_SD_CARD_V2_0             ((uint32_t)0x00000001U)\r\n#define HIGH_CAPACITY_SD_CARD                 ((uint32_t)0x00000002U)\r\n#define MULTIMEDIA_CARD                       ((uint32_t)0x00000003U)\r\n#define SECURE_DIGITAL_IO_CARD                ((uint32_t)0x00000004U)\r\n#define HIGH_SPEED_MULTIMEDIA_CARD            ((uint32_t)0x00000005U)\r\n#define SECURE_DIGITAL_IO_COMBO_CARD          ((uint32_t)0x00000006U)\r\n#define HIGH_CAPACITY_MMC_CARD                ((uint32_t)0x00000007U)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup SD_Exported_macros SD Exported Macros\r\n *  @brief macros to handle interrupts and specific clock configurations\r\n * @{\r\n */\r\n \r\n/**\r\n  * @brief  Enable the SD device.\r\n  * @retval None\r\n  */ \r\n#define __HAL_SD_SDMMC_ENABLE(__HANDLE__) __SDMMC_ENABLE((__HANDLE__)->Instance)\r\n\r\n/**\r\n  * @brief  Disable the SD device.\r\n  * @retval None\r\n  */\r\n#define __HAL_SD_SDMMC_DISABLE(__HANDLE__) __SDMMC_DISABLE((__HANDLE__)->Instance)\r\n\r\n/**\r\n  * @brief  Enable the SDMMC DMA transfer.\r\n  * @retval None\r\n  */ \r\n#define __HAL_SD_SDMMC_DMA_ENABLE(__HANDLE__) __SDMMC_DMA_ENABLE((__HANDLE__)->Instance)\r\n\r\n/**\r\n  * @brief  Disable the SDMMC DMA transfer.\r\n  * @retval None\r\n  */\r\n#define __HAL_SD_SDMMC_DMA_DISABLE(__HANDLE__)  __SDMMC_DMA_DISABLE((__HANDLE__)->Instance)\r\n \r\n/**\r\n  * @brief  Enable the SD device interrupt.\r\n  * @param  __HANDLE__: SD Handle  \r\n  * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.\r\n  *         This parameter can be one or a combination of the following values:\r\n  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r\n  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r\n  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt\r\n  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt\r\n  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r\n  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt\r\n  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt\r\n  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt\r\n  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt\r\n  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt\r\n  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt\r\n  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt\r\n  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt\r\n  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\r\n  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt\r\n  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt\r\n  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt\r\n  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt\r\n  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt\r\n  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt\r\n  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt\r\n  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_SD_SDMMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disable the SD device interrupt.\r\n  * @param  __HANDLE__: SD Handle   \r\n  * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.\r\n  *          This parameter can be one or a combination of the following values:\r\n  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r\n  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r\n  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt\r\n  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt\r\n  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r\n  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt\r\n  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt\r\n  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt\r\n  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt\r\n  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt\r\n  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt\r\n  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt\r\n  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt\r\n  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\r\n  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt\r\n  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt\r\n  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt\r\n  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt\r\n  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt\r\n  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt\r\n  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt\r\n  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt   \r\n  * @retval None\r\n  */\r\n#define __HAL_SD_SDMMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Check whether the specified SD flag is set or not. \r\n  * @param  __HANDLE__: SD Handle   \r\n  * @param  __FLAG__: specifies the flag to check. \r\n  *          This parameter can be one of the following values:\r\n  *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)\r\n  *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)\r\n  *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout\r\n  *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout\r\n  *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error\r\n  *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error\r\n  *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)\r\n  *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)\r\n  *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)\r\n  *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)\r\n  *            @arg SDMMC_FLAG_CMDACT:   Command transfer in progress\r\n  *            @arg SDMMC_FLAG_TXACT:    Data transmit in progress\r\n  *            @arg SDMMC_FLAG_RXACT:    Data receive in progress\r\n  *            @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty\r\n  *            @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full\r\n  *            @arg SDMMC_FLAG_TXFIFOF:  Transmit FIFO full\r\n  *            @arg SDMMC_FLAG_RXFIFOF:  Receive FIFO full\r\n  *            @arg SDMMC_FLAG_TXFIFOE:  Transmit FIFO empty\r\n  *            @arg SDMMC_FLAG_RXFIFOE:  Receive FIFO empty\r\n  *            @arg SDMMC_FLAG_TXDAVL:   Data available in transmit FIFO\r\n  *            @arg SDMMC_FLAG_RXDAVL:   Data available in receive FIFO\r\n  *            @arg SDMMC_FLAG_SDIOIT:   SD I/O interrupt received\r\n  * @retval The new state of SD FLAG (SET or RESET).\r\n  */\r\n#define __HAL_SD_SDMMC_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))\r\n\r\n/**\r\n  * @brief  Clear the SD's pending flags.\r\n  * @param  __HANDLE__: SD Handle  \r\n  * @param  __FLAG__: specifies the flag to clear.  \r\n  *          This parameter can be one or a combination of the following values:\r\n  *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)\r\n  *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)\r\n  *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout\r\n  *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout\r\n  *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error\r\n  *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error\r\n  *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)\r\n  *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)\r\n  *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)\r\n  *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)\r\n  *            @arg SDMMC_FLAG_SDIOIT:   SD I/O interrupt received\r\n  * @retval None\r\n  */\r\n#define __HAL_SD_SDMMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))\r\n\r\n/**\r\n  * @brief  Check whether the specified SD interrupt has occurred or not.\r\n  * @param  __HANDLE__: SD Handle   \r\n  * @param  __INTERRUPT__: specifies the SDMMC interrupt source to check. \r\n  *          This parameter can be one of the following values:\r\n  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r\n  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r\n  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt\r\n  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt\r\n  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r\n  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt\r\n  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt\r\n  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt\r\n  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt\r\n  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt\r\n  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt\r\n  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt\r\n  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt\r\n  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\r\n  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt\r\n  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt\r\n  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt\r\n  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt\r\n  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt\r\n  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt\r\n  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt\r\n  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt\r\n  * @retval The new state of SD IT (SET or RESET).\r\n  */\r\n#define __HAL_SD_SDMMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Clear the SD's interrupt pending bits.\r\n  * @param  __HANDLE__: SD Handle\r\n  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. \r\n  *          This parameter can be one or a combination of the following values:\r\n  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r\n  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r\n  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt\r\n  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt\r\n  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r\n  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt\r\n  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt\r\n  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt\r\n  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDMMC_DCOUNT, is zero) interrupt\r\n  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt\r\n  * @retval None\r\n  */\r\n#define __HAL_SD_SDMMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup SD_Exported_Functions SD Exported Functions\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions\r\n  * @{\r\n  */\r\nHAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo);\r\nHAL_StatusTypeDef   HAL_SD_DeInit (SD_HandleTypeDef *hsd);\r\nvoid HAL_SD_MspInit(SD_HandleTypeDef *hsd);\r\nvoid HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions\r\n  * @{\r\n  */\r\n/* Blocking mode: Polling */\r\nHAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);\r\nHAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);\r\nHAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr);\r\n\r\n/* Non-Blocking mode: Interrupt */\r\nvoid HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);\r\n\r\n/* Callback in non blocking modes (DMA) */\r\nvoid HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma);\r\nvoid HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma);\r\nvoid HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma);\r\nvoid HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma);\r\nvoid HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd);\r\nvoid HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd);\r\n\r\n/* Non-Blocking mode: DMA */\r\nHAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);\r\nHAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);\r\nHAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);\r\nHAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions\r\n  * @{\r\n  */\r\nHAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo);\r\nHAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode);\r\nHAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd);\r\nHAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd);\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Peripheral State functions  ************************************************/\r\n/** @defgroup SD_Exported_Functions_Group4 Peripheral State functions\r\n  * @{\r\n  */\r\nHAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);\r\nHAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus);\r\nHAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd);\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */\r\n    \r\n/* Private types -------------------------------------------------------------*/\r\n/** @defgroup SD_Private_Types SD Private Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private defines -----------------------------------------------------------*/\r\n/** @defgroup SD_Private_Defines SD Private Defines\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n          \r\n/* Private variables ---------------------------------------------------------*/\r\n/** @defgroup SD_Private_Variables SD Private Variables\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup SD_Private_Constants SD Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup SD_Private_Macros SD Private Macros\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions prototypes ----------------------------------------------*/\r\n/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup SD_Private_Functions SD Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n\r\n#endif /* __STM32F7xx_HAL_SD_H */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_sdram.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of SDRAM HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_SDRAM_H\r\n#define __STM32F7xx_HAL_SDRAM_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_ll_fmc.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup SDRAM\r\n  * @{\r\n  */ \r\n\r\n/* Exported typedef ----------------------------------------------------------*/   \r\n\r\n/** @defgroup SDRAM_Exported_Types SDRAM Exported Types\r\n  * @{\r\n  */\r\n\t \r\n/** \r\n  * @brief  HAL SDRAM State structure definition  \r\n  */ \r\ntypedef enum\r\n{\r\n  HAL_SDRAM_STATE_RESET             = 0x00U,  /*!< SDRAM not yet initialized or disabled */\r\n  HAL_SDRAM_STATE_READY             = 0x01U,  /*!< SDRAM initialized and ready for use   */\r\n  HAL_SDRAM_STATE_BUSY              = 0x02U,  /*!< SDRAM internal process is ongoing     */\r\n  HAL_SDRAM_STATE_ERROR             = 0x03U,  /*!< SDRAM error state                     */\r\n  HAL_SDRAM_STATE_WRITE_PROTECTED   = 0x04U,  /*!< SDRAM device write protected          */\r\n  HAL_SDRAM_STATE_PRECHARGED        = 0x05U   /*!< SDRAM device precharged               */\r\n  \r\n}HAL_SDRAM_StateTypeDef;\r\n\r\n/** \r\n  * @brief  SDRAM handle Structure definition  \r\n  */ \r\ntypedef struct\r\n{\r\n  FMC_SDRAM_TypeDef             *Instance;  /*!< Register base address                 */\r\n  \r\n  FMC_SDRAM_InitTypeDef         Init;       /*!< SDRAM device configuration parameters */\r\n  \r\n  __IO HAL_SDRAM_StateTypeDef   State;      /*!< SDRAM access state                    */\r\n  \r\n  HAL_LockTypeDef               Lock;       /*!< SDRAM locking object                  */ \r\n\r\n  DMA_HandleTypeDef             *hdma;      /*!< Pointer DMA handler                   */\r\n  \r\n}SDRAM_HandleTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/* Exported macro ------------------------------------------------------------*/\r\n\r\n/** @defgroup SDRAM_Exported_Macros SDRAM Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief Reset SDRAM handle state\r\n  * @param  __HANDLE__: specifies the SDRAM handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @addtogroup SDRAM_Exported_Functions SDRAM Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup SDRAM_Exported_Functions_Group1 \r\n  * @{\r\n  */\r\n\r\n/* Initialization/de-initialization functions *********************************/\r\nHAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing);\r\nHAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram);\r\nvoid HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram);\r\nvoid HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram);\r\n\r\nvoid HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram);\r\nvoid HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram);\r\nvoid HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);\r\nvoid HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup SDRAM_Exported_Functions_Group2 \r\n  * @{\r\n  */\r\n/* I/O operation functions ****************************************************/\r\nHAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);\r\nHAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);\r\nHAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);\r\nHAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);\r\nHAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);\r\nHAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);\r\n\r\nHAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t * pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);\r\nHAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @addtogroup SDRAM_Exported_Functions_Group3 \r\n  * @{\r\n  */\r\n/* SDRAM Control functions  *****************************************************/\r\nHAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram);\r\nHAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram);\r\nHAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate);\r\nHAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber);\r\nuint32_t          HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup SDRAM_Exported_Functions_Group4 \r\n  * @{\r\n  */\r\n/* SDRAM State functions ********************************************************/\r\nHAL_SDRAM_StateTypeDef  HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_SDRAM_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smartcard.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_smartcard.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of SMARTCARD HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_SMARTCARD_H\r\n#define __STM32F7xx_HAL_SMARTCARD_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup SMARTCARD\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/ \r\n/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types\r\n  * @{\r\n  */\r\n\r\n/** \r\n  * @brief SMARTCARD Init Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t BaudRate;                  /*!< Configures the SmartCard communication baud rate.\r\n                                           The baud rate register is computed using the following formula:\r\n                                              Baud Rate Register = ((PCLKx) / ((hsc->Init.BaudRate))) */\r\n                                           \r\n  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.\r\n                                           This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */\r\n\r\n  uint32_t StopBits;                  /*!< Specifies the number of stop bits @ref SMARTCARD_Stop_Bits. \r\n                                           Only 1.5 stop bits are authorized in SmartCard mode. */\r\n\r\n  uint32_t Parity;                    /*!< Specifies the parity mode.\r\n                                           This parameter can be a value of @ref SMARTCARD_Parity\r\n                                           @note The parity is enabled by default (PCE is forced to 1).\r\n                                                 Since the WordLength is forced to 8 bits + parity, M is\r\n                                                 forced to 1 and the parity bit is the 9th bit. */\r\n \r\n  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.\r\n                                           This parameter can be a value of @ref SMARTCARD_Mode */\r\n\r\n  uint32_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.\r\n                                           This parameter can be a value of @ref SMARTCARD_Clock_Polarity */\r\n\r\n  uint32_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.\r\n                                           This parameter can be a value of @ref SMARTCARD_Clock_Phase */\r\n\r\n  uint32_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted\r\n                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.\r\n                                           This parameter can be a value of @ref SMARTCARD_Last_Bit */\r\n                                             \r\n  uint32_t OneBitSampling;            /*!< Specifies  whether a single sample or three samples' majority vote is selected.\r\n                                           Selecting the single sample method increases the receiver tolerance to clock\r\n                                           deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling */\r\n\r\n  uint32_t  Prescaler;                 /*!< Specifies the SmartCard Prescaler */\r\n  \r\n  uint32_t  GuardTime;                 /*!< Specifies the SmartCard Guard Time */\r\n  \r\n  uint32_t NACKState;                  /*!< Specifies whether the SmartCard NACK transmission is enabled\r\n                                            in case of parity error.\r\n                                            This parameter can be a value of @ref SMARTCARD_NACK_State */ \r\n                                           \r\n  uint32_t TimeOutEnable;              /*!< Specifies whether the receiver timeout is enabled. \r\n                                            This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/\r\n  \r\n  uint32_t TimeOutValue;               /*!< Specifies the receiver time out value in number of baud blocks: \r\n                                            it is used to implement the Character Wait Time (CWT) and \r\n                                            Block Wait Time (BWT). It is coded over 24 bits. */ \r\n                                           \r\n  uint32_t BlockLength;                /*!< Specifies the SmartCard Block Length in T=1 Reception mode.\r\n                                            This parameter can be any value from 0x0 to 0xFF */ \r\n                                           \r\n  uint32_t AutoRetryCount;              /*!< Specifies the SmartCard auto-retry count (number of retries in\r\n                                             receive and transmit mode). When set to 0, retransmission is \r\n                                             disabled. Otherwise, its maximum value is 7 (before signalling\r\n                                             an error) */  \r\n\r\n}SMARTCARD_InitTypeDef;\r\n\r\n/** \r\n  * @brief HAL SMARTCARD State structures definition\r\n  * @note  HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState.\r\n  *        - gState contains SMARTCARD state information related to global Handle management \r\n  *          and also information related to Tx operations.\r\n  *          gState value coding follow below described bitmap :\r\n  *          b7-b6  Error information \r\n  *             00 : No Error\r\n  *             01 : (Not Used)\r\n  *             10 : Timeout\r\n  *             11 : Error\r\n  *          b5     IP initilisation status\r\n  *             0  : Reset (IP not initialized)\r\n  *             1  : Init done (IP not initialized. HAL SMARTCARD Init function already called)\r\n  *          b4-b3  (not used)\r\n  *             xx : Should be set to 00\r\n  *          b2     Intrinsic process state\r\n  *             0  : Ready\r\n  *             1  : Busy (IP busy with some configuration or internal operations)\r\n  *          b1     (not used)\r\n  *             x  : Should be set to 0\r\n  *          b0     Tx state\r\n  *             0  : Ready (no Tx operation ongoing)\r\n  *             1  : Busy (Tx operation ongoing)\r\n  *        - RxState contains information related to Rx operations.\r\n  *          RxState value coding follow below described bitmap :\r\n  *          b7-b6  (not used)\r\n  *             xx : Should be set to 00\r\n  *          b5     IP initilisation status\r\n  *             0  : Reset (IP not initialized)\r\n  *             1  : Init done (IP not initialized)\r\n  *          b4-b2  (not used)\r\n  *            xxx : Should be set to 000\r\n  *          b1     Rx state\r\n  *             0  : Ready (no Rx operation ongoing)\r\n  *             1  : Busy (Rx operation ongoing)\r\n  *          b0     (not used)\r\n  *             x  : Should be set to 0.\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t AdvFeatureInit;            /*!< Specifies which advanced SMARTCARD features is initialized. Several\r\n                                           advanced features may be initialized at the same time. This parameter \r\n                                           can be a value of @ref SMARTCARD_Advanced_Features_Initialization_Type */\r\n\r\n  uint32_t TxPinLevelInvert;          /*!< Specifies whether the TX pin active level is inverted.\r\n                                           This parameter can be a value of @ref SMARTCARD_Tx_Inv  */\r\n\r\n  uint32_t RxPinLevelInvert;          /*!< Specifies whether the RX pin active level is inverted.\r\n                                           This parameter can be a value of @ref SMARTCARD_Rx_Inv  */\r\n\r\n  uint32_t DataInvert;                /*!< Specifies whether data are inverted (positive/direct logic\r\n                                           vs negative/inverted logic).\r\n                                           This parameter can be a value of @ref SMARTCARD_Data_Inv */\r\n\r\n  uint32_t Swap;                      /*!< Specifies whether TX and RX pins are swapped.   \r\n                                           This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */\r\n\r\n  uint32_t OverrunDisable;            /*!< Specifies whether the reception overrun detection is disabled.   \r\n                                           This parameter can be a value of @ref SMARTCARD_Overrun_Disable */\r\n\r\n  uint32_t DMADisableonRxError;       /*!< Specifies whether the DMA is disabled in case of reception error.     \r\n                                           This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */\r\n\r\n  uint32_t MSBFirst;                  /*!< Specifies whether MSB is sent first on UART line.      \r\n                                           This parameter can be a value of @ref SMARTCARD_MSB_First */\r\n}SMARTCARD_AdvFeatureInitTypeDef;\r\n\r\n/** \r\n  * @brief HAL State structures definition  \r\n  */ \r\ntypedef enum\r\n{\r\n  HAL_SMARTCARD_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized\r\n                                                        Value is allowed for gState and RxState */\r\n  HAL_SMARTCARD_STATE_READY             = 0x20U,    /*!< Peripheral Initialized and ready for use\r\n                                                        Value is allowed for gState and RxState */\r\n  HAL_SMARTCARD_STATE_BUSY              = 0x24U,    /*!< an internal process is ongoing\r\n                                                        Value is allowed for gState only */\r\n  HAL_SMARTCARD_STATE_BUSY_TX           = 0x21U,    /*!< Data Transmission process is ongoing\r\n                                                        Value is allowed for gState only */\r\n  HAL_SMARTCARD_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing\r\n                                                        Value is allowed for RxState only */\r\n  HAL_SMARTCARD_STATE_BUSY_TX_RX        = 0x23U,    /*!< Data Transmission and Reception process is ongoing \r\n                                                        Not to be used for neither gState nor RxState.\r\n                                                        Value is result of combination (Or) between gState and RxState values */\r\n  HAL_SMARTCARD_STATE_TIMEOUT           = 0xA0U,    /*!< Timeout state\r\n                                                        Value is allowed for gState only */\r\n  HAL_SMARTCARD_STATE_ERROR             = 0xE0U     /*!< Error\r\n                                                        Value is allowed for gState only */\r\n}HAL_SMARTCARD_StateTypeDef;\r\n\r\n\r\n/**\r\n  * @brief  SMARTCARD clock sources definition\r\n  */\r\ntypedef enum\r\n{\r\n  SMARTCARD_CLOCKSOURCE_PCLK1      = 0x00U,    /*!< PCLK1 clock source  */\r\n  SMARTCARD_CLOCKSOURCE_PCLK2      = 0x01U,    /*!< PCLK2 clock source  */\r\n  SMARTCARD_CLOCKSOURCE_HSI        = 0x02U,    /*!< HSI clock source    */\r\n  SMARTCARD_CLOCKSOURCE_SYSCLK     = 0x04U,    /*!< SYSCLK clock source */\r\n  SMARTCARD_CLOCKSOURCE_LSE        = 0x08U     /*!< LSE clock source    */\r\n}SMARTCARD_ClockSourceTypeDef;\r\n\r\n/** \r\n  * @brief  SMARTCARD handle Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  USART_TypeDef                       *Instance;        /* USART registers base address                          */\r\n\r\n  SMARTCARD_InitTypeDef               Init;             /* SmartCard communication parameters                    */\r\n\r\n  SMARTCARD_AdvFeatureInitTypeDef     AdvancedInit;     /* SmartCard advanced features initialization parameters */\r\n\r\n  uint8_t                             *pTxBuffPtr;      /* Pointer to SmartCard Tx transfer Buffer            */\r\n\r\n  uint16_t                            TxXferSize;       /* SmartCard Tx Transfer size                         */\r\n\r\n  uint16_t                            TxXferCount;      /* SmartCard Tx Transfer Counter                      */\r\n\r\n  uint8_t                             *pRxBuffPtr;      /* Pointer to SmartCard Rx transfer Buffer        */\r\n\r\n  uint16_t                            RxXferSize;       /* SmartCard Rx Transfer size                     */\r\n\r\n  uint16_t                            RxXferCount;      /* SmartCard Rx Transfer Counter                  */\r\n\r\n  DMA_HandleTypeDef                   *hdmatx;          /* SmartCard Tx DMA Handle parameters             */\r\n\r\n  DMA_HandleTypeDef                   *hdmarx;          /* SmartCard Rx DMA Handle parameters             */\r\n\r\n  HAL_LockTypeDef                     Lock;             /* Locking object                                 */\r\n\r\n  __IO HAL_SMARTCARD_StateTypeDef    gState;      /*!< UART state information related to global Handle management \r\n                                                  and also related to Tx operations.\r\n                                                  This parameter can be a value of @ref HAL_UART_StateTypeDef */\r\n\r\n  __IO HAL_SMARTCARD_StateTypeDef    RxState;     /*!< UART state information related to Rx operations.\r\n                                                  This parameter can be a value of @ref HAL_UART_StateTypeDef */\r\n\r\n  __IO uint32_t                       ErrorCode;        /* SmartCard Error code                           */\r\n\r\n}SMARTCARD_HandleTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup SMARTCARD_Exported_Constants  SMARTCARD Exported constants\r\n  * @{\r\n  */\r\n/** @defgroup SMARTCARD_Error_Code SMARTCARD Error Code\r\n  * @brief    SMARTCARD Error Code \r\n  * @{\r\n  */ \r\n#define HAL_SMARTCARD_ERROR_NONE      ((uint32_t)0x00U)    /*!< No error                */\r\n#define HAL_SMARTCARD_ERROR_PE        ((uint32_t)0x01U)    /*!< Parity error            */\r\n#define HAL_SMARTCARD_ERROR_NE        ((uint32_t)0x02U)    /*!< Noise error             */\r\n#define HAL_SMARTCARD_ERROR_FE        ((uint32_t)0x04U)    /*!< frame error             */\r\n#define HAL_SMARTCARD_ERROR_ORE       ((uint32_t)0x08U)    /*!< Overrun error           */\r\n#define HAL_SMARTCARD_ERROR_DMA       ((uint32_t)0x10U)    /*!< DMA transfer error      */\r\n#define HAL_SMARTCARD_ERROR_RTO       ((uint32_t)0x20U)    /*!< Receiver TimeOut error  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length\r\n  * @{\r\n  */\r\n#define SMARTCARD_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M_0)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits\r\n  * @{\r\n  */\r\n#define SMARTCARD_STOPBITS_1_5                   ((uint32_t)(USART_CR2_STOP))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SMARTCARD_Parity SMARTCARD Parity\r\n  * @{\r\n  */\r\n#define SMARTCARD_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)\r\n#define SMARTCARD_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SMARTCARD_Mode SMARTCARD Mode\r\n  * @{\r\n  */\r\n#define SMARTCARD_MODE_RX                        ((uint32_t)USART_CR1_RE)\r\n#define SMARTCARD_MODE_TX                        ((uint32_t)USART_CR1_TE)\r\n#define SMARTCARD_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity\r\n  * @{\r\n  */\r\n#define SMARTCARD_POLARITY_LOW                   ((uint32_t)0x0000U)\r\n#define SMARTCARD_POLARITY_HIGH                  ((uint32_t)USART_CR2_CPOL)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup SMARTCARD_Clock_Phase  SMARTCARD Clock Phase\r\n  * @{\r\n  */\r\n#define SMARTCARD_PHASE_1EDGE                    ((uint32_t)0x0000U)\r\n#define SMARTCARD_PHASE_2EDGE                    ((uint32_t)USART_CR2_CPHA)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SMARTCARD_Last_Bit  SMARTCARD Last Bit\r\n  * @{\r\n  */\r\n#define SMARTCARD_LASTBIT_DISABLE                ((uint32_t)0x0000U)\r\n#define SMARTCARD_LASTBIT_ENABLE                 ((uint32_t)USART_CR2_LBCL)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD OneBit Sampling\r\n  * @{\r\n  */\r\n#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE   ((uint32_t)0x0000U)\r\n#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE    ((uint32_t)USART_CR3_ONEBIT)\r\n/**\r\n  * @}\r\n  */  \r\n\r\n\r\n/** @defgroup SMARTCARD_NACK_State  SMARTCARD NACK State\r\n  * @{\r\n  */\r\n#define SMARTCARD_NACK_ENABLE           ((uint32_t)USART_CR3_NACK)\r\n#define SMARTCARD_NACK_DISABLE          ((uint32_t)0x0000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable\r\n  * @{\r\n  */\r\n#define SMARTCARD_TIMEOUT_DISABLE      ((uint32_t)0x00000000U)\r\n#define SMARTCARD_TIMEOUT_ENABLE       ((uint32_t)USART_CR2_RTOEN)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup SMARTCARD_DMA_Requests   SMARTCARD DMA requests\r\n  * @{\r\n  */\r\n\r\n#define SMARTCARD_DMAREQ_TX                    ((uint32_t)USART_CR3_DMAT)\r\n#define SMARTCARD_DMAREQ_RX                    ((uint32_t)USART_CR3_DMAR)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SMARTCARD_Advanced_Features_Initialization_Type SMARTCARD Advanced Features Initialization Type\r\n  * @{\r\n  */\r\n#define SMARTCARD_ADVFEATURE_NO_INIT                 ((uint32_t)0x00000000U)\r\n#define SMARTCARD_ADVFEATURE_TXINVERT_INIT           ((uint32_t)0x00000001U)\r\n#define SMARTCARD_ADVFEATURE_RXINVERT_INIT           ((uint32_t)0x00000002U)\r\n#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT         ((uint32_t)0x00000004U)\r\n#define SMARTCARD_ADVFEATURE_SWAP_INIT               ((uint32_t)0x00000008U)\r\n#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT   ((uint32_t)0x00000010U)\r\n#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT  ((uint32_t)0x00000020U)\r\n#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT           ((uint32_t)0x00000080U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SMARTCARD_Tx_Inv SMARTCARD Tx Inv\r\n  * @{\r\n  */\r\n#define SMARTCARD_ADVFEATURE_TXINV_DISABLE   ((uint32_t)0x00000000U)\r\n#define SMARTCARD_ADVFEATURE_TXINV_ENABLE    ((uint32_t)USART_CR2_TXINV)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SMARTCARD_Rx_Inv SMARTCARD Rx Inv\r\n  * @{\r\n  */\r\n#define SMARTCARD_ADVFEATURE_RXINV_DISABLE   ((uint32_t)0x00000000U)\r\n#define SMARTCARD_ADVFEATURE_RXINV_ENABLE    ((uint32_t)USART_CR2_RXINV)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SMARTCARD_Data_Inv SMARTCARD Data Inv\r\n  * @{\r\n  */\r\n#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE     ((uint32_t)0x00000000U)\r\n#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE      ((uint32_t)USART_CR2_DATAINV)\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD Rx Tx Swap\r\n  * @{\r\n  */\r\n#define SMARTCARD_ADVFEATURE_SWAP_DISABLE   ((uint32_t)0x00000000U)\r\n#define SMARTCARD_ADVFEATURE_SWAP_ENABLE    ((uint32_t)USART_CR2_SWAP)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup SMARTCARD_Overrun_Disable SMARTCARD Overrun Disable\r\n  * @{\r\n  */\r\n#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE   ((uint32_t)0x00000000U)\r\n#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE  ((uint32_t)USART_CR3_OVRDIS)\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD DMA Disable on Rx Error\r\n  * @{\r\n  */\r\n#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR       ((uint32_t)0x00000000U)\r\n#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR      ((uint32_t)USART_CR3_DDRE)\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup SMARTCARD_MSB_First SMARTCARD MSB First\r\n  * @{\r\n  */\r\n#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE      ((uint32_t)0x00000000U)\r\n#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE       ((uint32_t)USART_CR2_MSBFIRST)\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup SmartCard_Flags SMARTCARD Flags\r\n  *        Elements values convention: 0xXXXX\r\n  *           - 0xXXXX  : Flag mask in the ISR register\r\n  * @{\r\n  */\r\n#define SMARTCARD_FLAG_REACK                     ((uint32_t)0x00400000U)\r\n#define SMARTCARD_FLAG_TEACK                     ((uint32_t)0x00200000U)\r\n#define SMARTCARD_FLAG_BUSY                      ((uint32_t)0x00010000U)\r\n#define SMARTCARD_FLAG_EOBF                      ((uint32_t)0x00001000U)\r\n#define SMARTCARD_FLAG_RTOF                      ((uint32_t)0x00000800U)\r\n#define SMARTCARD_FLAG_TXE                       ((uint32_t)0x00000080U)\r\n#define SMARTCARD_FLAG_TC                        ((uint32_t)0x00000040U)\r\n#define SMARTCARD_FLAG_RXNE                      ((uint32_t)0x00000020U)\r\n#define SMARTCARD_FLAG_IDLE                      ((uint32_t)0x00000010U)\r\n#define SMARTCARD_FLAG_ORE                       ((uint32_t)0x00000008U)\r\n#define SMARTCARD_FLAG_NE                        ((uint32_t)0x00000004U)\r\n#define SMARTCARD_FLAG_FE                        ((uint32_t)0x00000002U)\r\n#define SMARTCARD_FLAG_PE                        ((uint32_t)0x00000001U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SMARTCARD_Interrupt_definition SMARTCARD Interrupt definition\r\n  *        Elements values convention: 0000ZZZZ0XXYYYYYb\r\n  *           - YYYYY  : Interrupt source position in the XX register (5bits)\r\n  *           - XX  : Interrupt source register (2bits)\r\n  *                 - 01: CR1 register\r\n  *                 - 10: CR2 register\r\n  *                 - 11: CR3 register\r\n  *           - ZZZZ  : Flag position in the ISR register(4bits)\r\n  * @{\r\n  */\r\n  \r\n#define SMARTCARD_IT_PE                          ((uint16_t)0x0028U)\r\n#define SMARTCARD_IT_TXE                         ((uint16_t)0x0727U)\r\n#define SMARTCARD_IT_TC                          ((uint16_t)0x0626U)\r\n#define SMARTCARD_IT_RXNE                        ((uint16_t)0x0525U)\r\n#define SMARTCARD_IT_IDLE                        ((uint16_t)0x0424U)\r\n#define SMARTCARD_IT_ERR                         ((uint16_t)0x0060U)\r\n#define SMARTCARD_IT_ORE                         ((uint16_t)0x0300U)\r\n#define SMARTCARD_IT_NE                          ((uint16_t)0x0200U)\r\n#define SMARTCARD_IT_FE                          ((uint16_t)0x0100U)\r\n\r\n#define SMARTCARD_IT_EOB                         ((uint16_t)0x0C3BU)\r\n#define SMARTCARD_IT_RTO                         ((uint16_t)0x0B3AU)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup SMARTCARD_IT_CLEAR_Flags SMARTCARD IT CLEAR Flags\r\n  * @{\r\n  */\r\n#define SMARTCARD_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag */          \r\n#define SMARTCARD_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag */         \r\n#define SMARTCARD_CLEAR_NEF                       USART_ICR_NCF             /*!< Noise detected Clear Flag */        \r\n#define SMARTCARD_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag */         \r\n#define SMARTCARD_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< Idle line detected clear Flag */\r\n#define SMARTCARD_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag */ \r\n#define SMARTCARD_CLEAR_RTOF                      USART_ICR_RTOCF           /*!< Receiver Time Out Clear Flag */     \r\n#define SMARTCARD_CLEAR_EOBF                      USART_ICR_EOBCF           /*!< End Of Block Clear Flag */          \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters\r\n  * @{\r\n  */        \r\n#define SMARTCARD_RXDATA_FLUSH_REQUEST        ((uint32_t)USART_RQR_RXFRQ)        /*!< Receive Data flush Request */ \r\n#define SMARTCARD_TXDATA_FLUSH_REQUEST        ((uint32_t)USART_RQR_TXFRQ)        /*!< Transmit data flush Request */\r\n/**\r\n  * @}\r\n  */\r\n  \r\n  \r\n/** @defgroup SMARTCARD_CR3_SCAR_CNT_LSB_POS SMARTCARD CR3 SCAR CNT LSB POS\r\n  * @{\r\n  */\r\n#define SMARTCARD_CR3_SCARCNT_LSB_POS            ((uint32_t) 17U)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup SMARTCARD_GTPR_GT_LSBPOS SMARTCARD GTPR GT LSBPOS\r\n  * @{\r\n  */\r\n#define SMARTCARD_GTPR_GT_LSB_POS            ((uint32_t) 8U)\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/** @defgroup SMARTCARD_RTOR_BLEN_LSBPOS SMARTCARD RTOR BLEN LSBPOS\r\n  * @{\r\n  */\r\n#define SMARTCARD_RTOR_BLEN_LSB_POS          ((uint32_t) 24U)\r\n/**\r\n  * @}\r\n  */    \r\n \r\n/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD Interruption Mask\r\n  * @{\r\n  */ \r\n#define SMARTCARD_IT_MASK  ((uint16_t)0x001FU)  \r\n/**\r\n  * @}\r\n  */\r\n    \r\n/**\r\n  * @}\r\n  */    \r\n    \r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief Reset SMARTCARD handle state\r\n  * @param  __HANDLE__: specifies the SMARTCARD Handle.\r\n  *         The Handle Instance which can be USART1 or USART2\r\n  * @retval None\r\n  */\r\n#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMARTCARD_STATE_RESET)\r\n\r\n/** @brief  Flush the Smartcard DR register \r\n  * @param  __HANDLE__: specifies the SMARTCARD Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @retval None\r\n  */\r\n#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) (__HAL_SMARTCARD_SEND_REQ((__HANDLE__), SMARTCARD_RXDATA_FLUSH_REQUEST))\r\n\r\n/** @brief  Checks whether the specified Smartcard flag is set or not.\r\n  * @param  __HANDLE__: specifies the SMARTCARD Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @param  __FLAG__: specifies the flag to check.\r\n  *        This parameter can be one of the following values:\r\n  *            @arg SMARTCARD_FLAG_REACK: Receive enable acknowledge flag\r\n  *            @arg SMARTCARD_FLAG_TEACK: Transmit enable acknowledge flag\r\n  *            @arg SMARTCARD_FLAG_BUSY:  Busy flag\r\n  *            @arg SMARTCARD_FLAG_EOBF:  End of block flag   \r\n  *            @arg SMARTCARD_FLAG_RTOF:  Receiver timeout flag\r\n  *            @arg SMARTCARD_FLAG_TXE:   Transmit data register empty flag\r\n  *            @arg SMARTCARD_FLAG_TC:    Transmission Complete flag\r\n  *            @arg SMARTCARD_FLAG_RXNE:  Receive data register not empty flag\r\n  *            @arg SMARTCARD_FLAG_ORE:   OverRun Error flag\r\n  *            @arg SMARTCARD_FLAG_NE:    Noise Error flag\r\n  *            @arg SMARTCARD_FLAG_FE:    Framing Error flag\r\n  *            @arg SMARTCARD_FLAG_PE:    Parity Error flag\r\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))\r\n\r\n/** @brief  Enables the specified SmartCard interrupt.\r\n  * @param  __HANDLE__: specifies the SMARTCARD Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @param  __INTERRUPT__: specifies the SMARTCARD interrupt to enable.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg SMARTCARD_IT_EOBF: End Of Block interrupt\r\n  *            @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt\r\n  *            @arg SMARTCARD_IT_TXE:  Transmit Data Register empty interrupt\r\n  *            @arg SMARTCARD_IT_TC:   Transmission complete interrupt\r\n  *            @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt\r\n  *            @arg SMARTCARD_IT_PE:   Parity Error interrupt\r\n  *            @arg SMARTCARD_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)\r\n  * @retval None\r\n  */\r\n#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 |= (1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \\\r\n                                                        ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 |= (1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \\\r\n                                                        ((__HANDLE__)->Instance->CR3 |= (1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))\r\n/** @brief  Disables the specified SmartCard interrupt.\r\n  * @param  __HANDLE__: specifies the SMARTCARD Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @param  __INTERRUPT__: specifies the SMARTCARD interrupt to enable.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg SMARTCARD_IT_EOBF: End Of Block interrupt\r\n  *            @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt\r\n  *            @arg SMARTCARD_IT_TXE:  Transmit Data Register empty interrupt\r\n  *            @arg SMARTCARD_IT_TC:   Transmission complete interrupt\r\n  *            @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt\r\n  *            @arg SMARTCARD_IT_PE:   Parity Error interrupt\r\n  *            @arg SMARTCARD_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)\r\n  * @retval None\r\n  */\r\n#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \\\r\n                                                        ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \\\r\n                                                        ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))\r\n\r\n/** @brief  Checks whether the specified SmartCard interrupt has occurred or not.\r\n  * @param  __HANDLE__: specifies the SMARTCARD Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @param  __IT__: specifies the SMARTCARD interrupt to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg SMARTCARD_IT_EOBF: End Of Block interrupt\r\n  *            @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt  \r\n  *            @arg SMARTCARD_IT_TXE:  Transmit Data Register empty interrupt\r\n  *            @arg SMARTCARD_IT_TC:   Transmission complete interrupt\r\n  *            @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt\r\n  *            @arg SMARTCARD_IT_ORE:  OverRun Error interrupt\r\n  *            @arg SMARTCARD_IT_NE:   Noise Error interrupt\r\n  *            @arg SMARTCARD_IT_FE:   Framing Error interrupt\r\n  *            @arg SMARTCARD_IT_PE:   Parity Error interrupt\r\n  * @retval The new state of __IT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) \r\n\r\n/** @brief  Checks whether the specified SmartCard interrupt interrupt source is enabled.\r\n  * @param  __HANDLE__: specifies the SMARTCARD Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @param  __IT__: specifies the SMARTCARD interrupt source to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg SMARTCARD_IT_EOBF: End Of Block interrupt\r\n  *            @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt  \r\n  *            @arg SMARTCARD_IT_TXE:  Transmit Data Register empty interrupt\r\n  *            @arg SMARTCARD_IT_TC:   Transmission complete interrupt\r\n  *            @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt\r\n  *            @arg SMARTCARD_IT_ORE:  OverRun Error interrupt\r\n  *            @arg SMARTCARD_IT_NE:   Noise Error interrupt\r\n  *            @arg SMARTCARD_IT_FE:   Framing Error interrupt\r\n  *            @arg SMARTCARD_IT_PE:   Parity Error interrupt\r\n  * @retval The new state of __IT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \\\r\n                                                               (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << \\\r\n                                                               (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK)))\r\n\r\n\r\n/** @brief  Clears the specified SMARTCARD ISR flag, in setting the proper ICR register flag.\r\n  * @param  __HANDLE__: specifies the SMARTCARD Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @param  __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set\r\n  *                       to clear the corresponding interrupt\r\n  *          This parameter can be one of the following values:\r\n  *            @arg USART_CLEAR_PEF: Parity Error Clear Flag\r\n  *            @arg USART_CLEAR_FEF: Framing Error Clear Flag\r\n  *            @arg USART_CLEAR_NEF: Noise detected Clear Flag\r\n  *            @arg USART_CLEAR_OREF: OverRun Error Clear Flag\r\n  *            @arg USART_CLEAR_TCF: Transmission Complete Clear Flag\r\n  *            @arg USART_CLEAR_RTOF: Receiver Time Out Clear Flag\r\n  *            @arg USART_CLEAR_EOBF: End Of Block Clear Flag \r\n  * @retval None\r\n  */\r\n#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) \r\n\r\n/** @brief  Set a specific SMARTCARD request flag.\r\n  * @param  __HANDLE__: specifies the SMARTCARD Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @param  __REQ__: specifies the request flag to set\r\n  *          This parameter can be one of the following values:  \r\n  *            @arg SMARTCARD_RXDATA_FLUSH_REQUEST: Receive Data flush Request \r\n  *            @arg SMARTCARD_TXDATA_FLUSH_REQUEST: Transmit data flush Request \r\n  *\r\n  * @retval None\r\n  */ \r\n#define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__)) \r\n\r\n/** @brief  Enable the USART associated to the SMARTCARD Handle\r\n  * @param  __HANDLE__: specifies the SMARTCARD Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @retval None\r\n  */\r\n#define __HAL_SMARTCARD_ENABLE(__HANDLE__)               ( (__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)\r\n\r\n/** @brief  Disable the USART associated to the SMARTCARD Handle\r\n  * @param  __HANDLE__: specifies the SMARTCARD Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @retval None\r\n  */\r\n#define __HAL_SMARTCARD_DISABLE(__HANDLE__)              ( (__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)\r\n\r\n/** @brief  Macros to enable or disable the SmartCard DMA request.\r\n  * @param  __HANDLE__: specifies the SMARTCARD Handle.\r\n  *         The Handle Instance which can be USART1 or USART2.\r\n  * @param  __REQUEST__: specifies the SmartCard DMA request.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request\r\n  *            @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request\r\n  */\r\n#define __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__)    ((__HANDLE__)->Instance->CR3 |=  (__REQUEST__))\r\n#define __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__)   ((__HANDLE__)->Instance->CR3 &=  ~(__REQUEST__))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Include SMARTCARD HAL Extension module */\r\n#include \"stm32f7xx_hal_smartcard_ex.h\"\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup SMARTCARD_Exported_Functions\r\n  * @{\r\n  */\r\n  \r\n/** @addtogroup SMARTCARD_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n/* Initialization/de-initialization functions  **********************************/\r\nHAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc);\r\nHAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc);\r\nvoid HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc);\r\nvoid HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup SMARTCARD_Exported_Functions_Group2\r\n  * @{\r\n  */\r\n/* IO operation functions *******************************************************/\r\nHAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);\r\nvoid HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc);\r\nvoid HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc);\r\nvoid HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc);\r\nvoid HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup SMARTCARD_Exported_Functions_Group3\r\n  * @{\r\n  */\r\n/* Peripheral State functions  **************************************************/\r\nHAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc);\r\nuint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants\r\n  * @{\r\n  */\r\n\r\n#define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B) \r\n#define IS_SMARTCARD_STOPBITS(__STOPBITS__) ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5)\r\n#define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \\\r\n                                         ((__PARITY__) == SMARTCARD_PARITY_ODD))\r\n#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFF3) == 0x00) && ((__MODE__) != (uint32_t)0x00))\r\n#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))\r\n#define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))\r\n#define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \\\r\n                                           ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))\r\n#define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \\\r\n                                                  ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))\r\n#define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \\\r\n                                     ((__NACK__) == SMARTCARD_NACK_DISABLE))\r\n#define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \\\r\n                                           ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))\r\n#define IS_SMARTCARD_ADVFEATURE_INIT(INIT)           ((INIT) <= (SMARTCARD_ADVFEATURE_NO_INIT | \\\r\n                                                            SMARTCARD_ADVFEATURE_TXINVERT_INIT | \\\r\n                                                            SMARTCARD_ADVFEATURE_RXINVERT_INIT | \\\r\n                                                            SMARTCARD_ADVFEATURE_DATAINVERT_INIT | \\\r\n                                                            SMARTCARD_ADVFEATURE_SWAP_INIT | \\\r\n                                                            SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT | \\\r\n                                                            SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT   | \\\r\n                                                            SMARTCARD_ADVFEATURE_MSBFIRST_INIT))  \r\n#define IS_SMARTCARD_ADVFEATURE_TXINV(TXINV) (((TXINV) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \\\r\n                                         ((TXINV) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))\r\n#define IS_SMARTCARD_ADVFEATURE_RXINV(RXINV) (((RXINV) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \\\r\n                                         ((RXINV) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))\r\n#define IS_SMARTCARD_ADVFEATURE_DATAINV(DATAINV) (((DATAINV) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \\\r\n                                             ((DATAINV) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))\r\n#define IS_SMARTCARD_ADVFEATURE_SWAP(SWAP) (((SWAP) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \\\r\n                                       ((SWAP) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))\r\n#define IS_SMARTCARD_OVERRUN(OVERRUN)         (((OVERRUN) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \\\r\n                                          ((OVERRUN) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))\r\n#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(DMA)      (((DMA) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \\\r\n                                                   ((DMA) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))\r\n#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001)\r\n#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFF)\r\n#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__)    ((__TIMEOUTVALUE__) <= 0xFFFFFF)\r\n#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__)         ((__COUNT__) <= 0x7)\r\n#define IS_SMARTCARD_ADVFEATURE_MSBFIRST(MSBFIRST) (((MSBFIRST) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \\\r\n                                               ((MSBFIRST) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))\r\n#define IS_SMARTCARD_REQUEST_PARAMETER(PARAM) (((PARAM) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \\\r\n                                               ((PARAM) == SMARTCARD_TXDATA_FLUSH_REQUEST))   \r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_SMARTCARD_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smartcard_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_smartcard_ex.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of SMARTCARD HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_SMARTCARD_EX_H\r\n#define __STM32F7xx_HAL_SMARTCARD_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup SMARTCARDEx\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n/* Exported macro ------------------------------------------------------------*/\r\n   \r\n/** @brief  Reports the SMARTCARD clock source.\r\n  * @param  __HANDLE__: specifies the USART Handle\r\n  * @param  __CLOCKSOURCE__ : output variable   \r\n  * @retval the USART clocking source, written in __CLOCKSOURCE__.\r\n  */\r\n#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \\\r\n  do {                                                             \\\r\n    if((__HANDLE__)->Instance == USART1)                           \\\r\n    {                                                              \\\r\n       switch(__HAL_RCC_GET_USART1_SOURCE())                       \\\r\n       {                                                           \\\r\n        case RCC_USART1CLKSOURCE_PCLK2:                            \\\r\n          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2;         \\\r\n          break;                                                   \\\r\n        case RCC_USART1CLKSOURCE_HSI:                              \\\r\n          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;           \\\r\n          break;                                                   \\\r\n        case RCC_USART1CLKSOURCE_SYSCLK:                           \\\r\n          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                                   \\\r\n        case RCC_USART1CLKSOURCE_LSE:                              \\\r\n          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;           \\\r\n          break;                                                   \\\r\n        default:                                                   \\\r\n          break;                                                   \\\r\n       }                                                           \\\r\n    }                                                              \\\r\n    else if((__HANDLE__)->Instance == USART2)                      \\\r\n    {                                                              \\\r\n       switch(__HAL_RCC_GET_USART2_SOURCE())                       \\\r\n       {                                                           \\\r\n        case RCC_USART2CLKSOURCE_PCLK1:                            \\\r\n          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1;         \\\r\n          break;                                                   \\\r\n        case RCC_USART2CLKSOURCE_HSI:                              \\\r\n          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;           \\\r\n          break;                                                   \\\r\n        case RCC_USART2CLKSOURCE_SYSCLK:                           \\\r\n          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                                   \\\r\n        case RCC_USART2CLKSOURCE_LSE:                              \\\r\n          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;           \\\r\n          break;                                                   \\\r\n        default:                                                   \\\r\n          break;                                                   \\\r\n       }                                                           \\\r\n    }                                                              \\\r\n    else if((__HANDLE__)->Instance == USART3)                      \\\r\n    {                                                              \\\r\n       switch(__HAL_RCC_GET_USART3_SOURCE())                       \\\r\n       {                                                           \\\r\n        case RCC_USART3CLKSOURCE_PCLK1:                            \\\r\n          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1;         \\\r\n          break;                                                   \\\r\n        case RCC_USART3CLKSOURCE_HSI:                              \\\r\n          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;           \\\r\n          break;                                                   \\\r\n        case RCC_USART3CLKSOURCE_SYSCLK:                           \\\r\n          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                                   \\\r\n        case RCC_USART3CLKSOURCE_LSE:                              \\\r\n          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;           \\\r\n          break;                                                   \\\r\n        default:                                                   \\\r\n          break;                                                   \\\r\n       }                                                           \\\r\n    }                                                              \\\r\n    else if((__HANDLE__)->Instance == USART6)                      \\\r\n    {                                                              \\\r\n       switch(__HAL_RCC_GET_USART6_SOURCE())                       \\\r\n       {                                                           \\\r\n        case RCC_USART6CLKSOURCE_PCLK2:                            \\\r\n          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2;         \\\r\n          break;                                                   \\\r\n        case RCC_USART6CLKSOURCE_HSI:                              \\\r\n          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;           \\\r\n          break;                                                   \\\r\n        case RCC_USART6CLKSOURCE_SYSCLK:                           \\\r\n          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                                   \\\r\n        case RCC_USART6CLKSOURCE_LSE:                              \\\r\n          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;           \\\r\n          break;                                                   \\\r\n        default:                                                   \\\r\n          break;                                                   \\\r\n       }                                                           \\\r\n    }                                                              \\\r\n    } while(0)\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/* Initialization and de-initialization functions  ****************************/\r\n/* IO operation functions *****************************************************/\r\n/* Peripheral Control functions ***********************************************/\r\nvoid HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsc, uint8_t BlockLength);\r\nvoid HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsc, uint32_t TimeOutValue);\r\nHAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsc);\r\nHAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsc);\r\n\r\n/* Peripheral State and Error functions ***************************************/\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_SMARTCARD_EX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spdifrx.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_spdifrx.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of SPDIFRX HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_SPDIFRX_H\r\n#define __STM32F7xx_HAL_SPDIFRX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"  \r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup SPDIFRX\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/ \r\n/** @defgroup SPDIFRX_Exported_Types SPDIFRX Exported Types\r\n  * @{\r\n  */\r\n\r\n/** \r\n  * @brief SPDIFRX Init structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t InputSelection;           /*!< Specifies the SPDIF input selection.\r\n                                          This parameter can be a value of @ref SPDIFRX_Input_Selection */\r\n\r\n  uint32_t Retries;                  /*!< Specifies the Maximum allowed re-tries during synchronization phase.\r\n                                          This parameter can be a value of @ref SPDIFRX_Max_Retries */\r\n\r\n  uint32_t WaitForActivity;          /*!< Specifies the wait for activity on SPDIF selected input.\r\n                                          This parameter can be a value of @ref SPDIFRX_Wait_For_Activity. */\r\n\r\n  uint32_t ChannelSelection;         /*!< Specifies whether the control flow will take the channel status from channel A or B.\r\n                                          This parameter can be a value of @ref SPDIFRX_Channel_Selection */\r\n\r\n  uint32_t DataFormat;               /*!< Specifies the Data samples format (LSB, MSB, ...).\r\n                                          This parameter can be a value of @ref SPDIFRX_Data_Format */\r\n                                               \r\n  uint32_t StereoMode;               /*!< Specifies whether the peripheral is in stereo or mono mode.\r\n                                          This parameter can be a value of @ref SPDIFRX_Stereo_Mode */\r\n\r\n    uint32_t PreambleTypeMask;          /*!< Specifies whether The preamble type bits are copied or not into the received frame.\r\n                                                                                   This parameter can be a value of @ref SPDIFRX_PT_Mask */\r\n\r\n    uint32_t ChannelStatusMask;        /*!< Specifies whether the channel status and user bits are copied or not into the received frame.\r\n                                                                                  This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */\r\n    \r\n    uint32_t ValidityBitMask;          /*!< Specifies whether the validity bit is copied or not into the received frame.\r\n                                                                                  This parameter can be a value of @ref SPDIFRX_V_Mask */                                                                                \r\n                                                                                \r\n    uint32_t ParityErrorMask;          /*!< Specifies whether the parity error bit is copied or not into the received frame.\r\n                                                                                  This parameter can be a value of @ref SPDIFRX_PE_Mask */\r\n    \r\n}SPDIFRX_InitTypeDef;\r\n\r\n/** \r\n  * @brief SPDIFRX SetDataFormat structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t DataFormat;               /*!< Specifies the Data samples format (LSB, MSB, ...).\r\n                                          This parameter can be a value of @ref SPDIFRX_Data_Format */\r\n                                               \r\n  uint32_t StereoMode;               /*!< Specifies whether the peripheral is in stereo or mono mode.\r\n                                          This parameter can be a value of @ref SPDIFRX_Stereo_Mode */\r\n\r\n  uint32_t PreambleTypeMask;          /*!< Specifies whether The preamble type bits are copied or not into the received frame.\r\n                                                                                   This parameter can be a value of @ref SPDIFRX_PT_Mask */\r\n\r\n  uint32_t ChannelStatusMask;        /*!< Specifies whether the channel status and user bits are copied or not into the received frame.\r\n                                                                                  This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */\r\n    \r\n  uint32_t ValidityBitMask;          /*!< Specifies whether the validity bit is copied or not into the received frame.\r\n                                                                                  This parameter can be a value of @ref SPDIFRX_V_Mask */                                                                                \r\n                                                                                \r\n  uint32_t ParityErrorMask;          /*!< Specifies whether the parity error bit is copied or not into the received frame.\r\n                                                                                  This parameter can be a value of @ref SPDIFRX_PE_Mask */\r\n    \r\n}SPDIFRX_SetDataFormatTypeDef;\r\n\r\n/** \r\n  * @brief  HAL State structures definition  \r\n  */ \r\ntypedef enum\r\n{\r\n  HAL_SPDIFRX_STATE_RESET      = 0x00U,  /*!< SPDIFRX not yet initialized or disabled                */\r\n  HAL_SPDIFRX_STATE_READY      = 0x01U,  /*!< SPDIFRX initialized and ready for use                  */\r\n  HAL_SPDIFRX_STATE_BUSY       = 0x02U,  /*!< SPDIFRX internal process is ongoing                    */ \r\n  HAL_SPDIFRX_STATE_BUSY_RX    = 0x03U,  /*!< SPDIFRX internal Data Flow RX process is ongoing       */  \r\n  HAL_SPDIFRX_STATE_BUSY_CX    = 0x04U,  /*!< SPDIFRX internal Control Flow RX process is ongoing    */    \r\n  HAL_SPDIFRX_STATE_ERROR      = 0x07U   /*!< SPDIFRX error state                                    */      \r\n}HAL_SPDIFRX_StateTypeDef;\r\n\r\n/** \r\n  * @brief SPDIFRX handle Structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  SPDIFRX_TypeDef            *Instance;    /* SPDIFRX registers base address */\r\n\r\n  SPDIFRX_InitTypeDef        Init;         /* SPDIFRX communication parameters */\r\n                            \r\n  uint32_t                   *pRxBuffPtr;  /* Pointer to SPDIFRX Rx transfer buffer */\r\n    \r\n    uint32_t                   *pCsBuffPtr;  /* Pointer to SPDIFRX Cx transfer buffer */\r\n  \r\n  __IO uint16_t              RxXferSize;   /* SPDIFRX Rx transfer size */\r\n  \r\n  __IO uint16_t              RxXferCount;  /* SPDIFRX Rx transfer counter \r\n                                              (This field is initialized at the \r\n                                               same value as transfer size at the \r\n                                               beginning of the transfer and \r\n                                               decremented when a sample is received. \r\n                                               NbSamplesReceived = RxBufferSize-RxBufferCount) */\r\n    \r\n  __IO uint16_t              CsXferSize;   /* SPDIFRX Rx transfer size */\r\n  \r\n  __IO uint16_t              CsXferCount;  /* SPDIFRX Rx transfer counter \r\n                                              (This field is initialized at the \r\n                                               same value as transfer size at the \r\n                                               beginning of the transfer and \r\n                                               decremented when a sample is received. \r\n                                               NbSamplesReceived = RxBufferSize-RxBufferCount) */\r\n                                                                                             \r\n  DMA_HandleTypeDef          *hdmaCsRx;    /* SPDIFRX EC60958_channel_status and user_information DMA handle parameters */\r\n\r\n  DMA_HandleTypeDef          *hdmaDrRx;    /* SPDIFRX Rx DMA handle parameters */\r\n  \r\n  __IO HAL_LockTypeDef       Lock;         /* SPDIFRX locking object */\r\n  \r\n  __IO HAL_SPDIFRX_StateTypeDef  State;    /* SPDIFRX communication state */\r\n\r\n  __IO uint32_t  ErrorCode;                /* SPDIFRX Error code                 */\r\n\r\n}SPDIFRX_HandleTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup SPDIFRX_Exported_Constants SPDIFRX Exported Constants\r\n  * @{\r\n  */\r\n/** @defgroup SPDIFRX_ErrorCode SPDIFRX Error Code\r\n  * @{\r\n  */ \r\n#define HAL_SPDIFRX_ERROR_NONE      ((uint32_t)0x00000000U)  /*!< No error           */\r\n#define HAL_SPDIFRX_ERROR_TIMEOUT   ((uint32_t)0x00000001U)  /*!< Timeout error      */  \r\n#define HAL_SPDIFRX_ERROR_OVR       ((uint32_t)0x00000002U)  /*!< OVR error          */\r\n#define HAL_SPDIFRX_ERROR_PE        ((uint32_t)0x00000004U)  /*!< Parity error       */\r\n#define HAL_SPDIFRX_ERROR_DMA       ((uint32_t)0x00000008U)  /*!< DMA transfer error */\r\n#define HAL_SPDIFRX_ERROR_UNKNOWN   ((uint32_t)0x00000010U)  /*!< Unknown Error error */  \r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup SPDIFRX_Input_Selection SPDIFRX Input Selection\r\n  * @{\r\n  */\r\n#define SPDIFRX_INPUT_IN0               ((uint32_t)0x00000000U)\r\n#define SPDIFRX_INPUT_IN1               ((uint32_t)0x00010000U)  \r\n#define SPDIFRX_INPUT_IN2               ((uint32_t)0x00020000U)\r\n#define SPDIFRX_INPUT_IN3               ((uint32_t)0x00030000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPDIFRX_Max_Retries SPDIFRX Maximum Retries\r\n  * @{\r\n  */\r\n#define SPDIFRX_MAXRETRIES_NONE            ((uint32_t)0x00000000U)\r\n#define SPDIFRX_MAXRETRIES_3               ((uint32_t)0x00001000U)  \r\n#define SPDIFRX_MAXRETRIES_15              ((uint32_t)0x00002000U)\r\n#define SPDIFRX_MAXRETRIES_63              ((uint32_t)0x00003000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPDIFRX_Wait_For_Activity SPDIFRX Wait For Activity\r\n  * @{\r\n  */\r\n#define SPDIFRX_WAITFORACTIVITY_OFF                   ((uint32_t)0x00000000U)\r\n#define SPDIFRX_WAITFORACTIVITY_ON                    ((uint32_t)SPDIFRX_CR_WFA)\r\n/**\r\n  * @}\r\n  */\r\n    \r\n/** @defgroup SPDIFRX_PT_Mask SPDIFRX Preamble Type Mask\r\n* @{\r\n*/\r\n#define SPDIFRX_PREAMBLETYPEMASK_OFF                   ((uint32_t)0x00000000U)\r\n#define SPDIFRX_PREAMBLETYPEMASK_ON                    ((uint32_t)SPDIFRX_CR_PTMSK)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPDIFRX_ChannelStatus_Mask  SPDIFRX Channel Status Mask\r\n* @{\r\n*/\r\n#define SPDIFRX_CHANNELSTATUS_OFF                 ((uint32_t)0x00000000U)        /* The channel status and user bits are copied into the SPDIF_DR */\r\n#define SPDIFRX_CHANNELSTATUS_ON                  ((uint32_t)SPDIFRX_CR_CUMSK)  /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPDIFRX_V_Mask SPDIFRX Validity Mask\r\n* @{\r\n*/\r\n#define SPDIFRX_VALIDITYMASK_OFF                   ((uint32_t)0x00000000U)\r\n#define SPDIFRX_VALIDITYMASK_ON                    ((uint32_t)SPDIFRX_CR_VMSK)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPDIFRX_PE_Mask  SPDIFRX Parity Error Mask\r\n* @{\r\n*/\r\n#define SPDIFRX_PARITYERRORMASK_OFF                   ((uint32_t)0x00000000U)\r\n#define SPDIFRX_PARITYERRORMASK_ON                    ((uint32_t)SPDIFRX_CR_PMSK)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPDIFRX_Channel_Selection  SPDIFRX Channel Selection\r\n  * @{\r\n  */\r\n#define SPDIFRX_CHANNEL_A      ((uint32_t)0x00000000U)\r\n#define SPDIFRX_CHANNEL_B      ((uint32_t)SPDIFRX_CR_CHSEL)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPDIFRX_Data_Format SPDIFRX Data Format\r\n  * @{\r\n  */\r\n#define SPDIFRX_DATAFORMAT_LSB                   ((uint32_t)0x00000000U)\r\n#define SPDIFRX_DATAFORMAT_MSB                   ((uint32_t)0x00000010U)\r\n#define SPDIFRX_DATAFORMAT_32BITS                ((uint32_t)0x00000020U)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup SPDIFRX_Stereo_Mode SPDIFRX Stereo Mode\r\n  * @{\r\n  */\r\n#define SPDIFRX_STEREOMODE_DISABLE           ((uint32_t)0x00000000U)\r\n#define SPDIFRX_STEREOMODE_ENABLE           ((uint32_t)SPDIFRX_CR_RXSTEO)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup SPDIFRX_State SPDIFRX State\r\n  * @{\r\n  */\r\n\r\n#define SPDIFRX_STATE_IDLE    ((uint32_t)0xFFFFFFFCU)\r\n#define SPDIFRX_STATE_SYNC    ((uint32_t)0x00000001U)\r\n#define SPDIFRX_STATE_RCV     ((uint32_t)SPDIFRX_CR_SPDIFEN)\r\n/**\r\n  * @}\r\n  */\r\n    \r\n/** @defgroup SPDIFRX_Interrupts_Definition SPDIFRX Interrupts Definition\r\n  * @{\r\n  */\r\n#define SPDIFRX_IT_RXNE                       ((uint32_t)SPDIFRX_IMR_RXNEIE)\r\n#define SPDIFRX_IT_CSRNE                      ((uint32_t)SPDIFRX_IMR_CSRNEIE)\r\n#define SPDIFRX_IT_PERRIE                     ((uint32_t)SPDIFRX_IMR_PERRIE)\r\n#define SPDIFRX_IT_OVRIE                      ((uint32_t)SPDIFRX_IMR_OVRIE)\r\n#define SPDIFRX_IT_SBLKIE                     ((uint32_t)SPDIFRX_IMR_SBLKIE)\r\n#define SPDIFRX_IT_SYNCDIE                    ((uint32_t)SPDIFRX_IMR_SYNCDIE)\r\n#define SPDIFRX_IT_IFEIE                      ((uint32_t)SPDIFRX_IMR_IFEIE )\r\n/**\r\n  * @}\r\n  */\r\n    \r\n/** @defgroup SPDIFRX_Flags_Definition SPDIFRX Flags Definition\r\n  * @{\r\n  */\r\n#define SPDIFRX_FLAG_RXNE                   ((uint32_t)SPDIFRX_SR_RXNE)\r\n#define SPDIFRX_FLAG_CSRNE                  ((uint32_t)SPDIFRX_SR_CSRNE)\r\n#define SPDIFRX_FLAG_PERR                   ((uint32_t)SPDIFRX_SR_PERR)\r\n#define SPDIFRX_FLAG_OVR                    ((uint32_t)SPDIFRX_SR_OVR)\r\n#define SPDIFRX_FLAG_SBD                    ((uint32_t)SPDIFRX_SR_SBD)\r\n#define SPDIFRX_FLAG_SYNCD                  ((uint32_t)SPDIFRX_SR_SYNCD)\r\n#define SPDIFRX_FLAG_FERR                   ((uint32_t)SPDIFRX_SR_FERR)\r\n#define SPDIFRX_FLAG_SERR                   ((uint32_t)SPDIFRX_SR_SERR)\r\n#define SPDIFRX_FLAG_TERR                   ((uint32_t)SPDIFRX_SR_TERR)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/* Exported macros -----------------------------------------------------------*/\r\n/** @defgroup SPDIFRX_Exported_macros SPDIFRX Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief  Reset SPDIFRX handle state\r\n  * @param  __HANDLE__: SPDIFRX handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = (uint16_t)SPDIFRX_CR_SPDIFEN)\r\n\r\n/** @brief  Disable the specified SPDIFRX peripheral (IDLE State).\r\n  * @param  __HANDLE__: specifies the SPDIFRX Handle. \r\n  * @retval None\r\n  */\r\n#define __HAL_SPDIFRX_IDLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE)\r\n\r\n/** @brief  Enable the specified SPDIFRX peripheral (SYNC State).\r\n  * @param  __HANDLE__: specifies the SPDIFRX Handle. \r\n  * @retval None\r\n  */\r\n#define __HAL_SPDIFRX_SYNC(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC)\r\n\r\n\r\n/** @brief  Enable the specified SPDIFRX peripheral (RCV State).\r\n  * @param  __HANDLE__: specifies the SPDIFRX Handle. \r\n  * @retval None\r\n  */\r\n#define __HAL_SPDIFRX_RCV(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV)\r\n\r\n\r\n/** @brief  Enable or disable the specified SPDIFRX interrupts.\r\n  * @param  __HANDLE__: specifies the SPDIFRX Handle.\r\n  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.\r\n  *        This parameter can be one of the following values:\r\n  *            @arg SPDIFRX_IT_RXNE\r\n  *            @arg SPDIFRX_IT_CSRNE\r\n  *            @arg SPDIFRX_IT_PERRIE\r\n  *            @arg SPDIFRX_IT_OVRIE\r\n  *            @arg SPDIFRX_IT_SBLKIE\r\n  *            @arg SPDIFRX_IT_SYNCDIE\r\n  *            @arg SPDIFRX_IT_IFEIE\r\n  * @retval None\r\n  */  \r\n#define __HAL_SPDIFRX_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))\r\n#define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__)))\r\n \r\n/** @brief  Checks if the specified SPDIFRX interrupt source is enabled or disabled.\r\n  * @param  __HANDLE__: specifies the SPDIFRX Handle.\r\n  * @param  __INTERRUPT__: specifies the SPDIFRX interrupt source to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg SPDIFRX_IT_RXNE\r\n  *            @arg SPDIFRX_IT_CSRNE\r\n  *            @arg SPDIFRX_IT_PERRIE\r\n  *            @arg SPDIFRX_IT_OVRIE\r\n  *            @arg SPDIFRX_IT_SBLKIE\r\n  *            @arg SPDIFRX_IT_SYNCDIE\r\n  *            @arg SPDIFRX_IT_IFEIE\r\n  * @retval The new state of __IT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r\n\r\n/** @brief  Checks whether the specified SPDIFRX flag is set or not.\r\n  * @param  __HANDLE__: specifies the SPDIFRX Handle.\r\n  * @param  __FLAG__: specifies the flag to check.\r\n  *        This parameter can be one of the following values:\r\n  *            @arg SPDIFRX_FLAG_RXNE\r\n  *            @arg SPDIFRX_FLAG_CSRNE\r\n  *            @arg SPDIFRX_FLAG_PERR\r\n  *            @arg SPDIFRX_FLAG_OVR\r\n  *            @arg SPDIFRX_FLAG_SBD\r\n  *            @arg SPDIFRX_FLAG_SYNCD \r\n  *            @arg SPDIFRX_FLAG_FERR \r\n  *            @arg SPDIFRX_FLAG_SERR \r\n  *            @arg SPDIFRX_FLAG_TERR \r\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))\r\n\r\n/** @brief  Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit.\r\n  * @param  __HANDLE__: specifies the USART Handle.\r\n  * @param  __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set\r\n  *                       to clear the corresponding interrupt\r\n  *          This parameter can be one of the following values:\r\n  *            @arg SPDIFRX_FLAG_PERR\r\n  *            @arg SPDIFRX_FLAG_OVR\r\n  *            @arg SPDIFRX_SR_SBD\r\n  *            @arg SPDIFRX_SR_SYNCD\r\n  * @retval None\r\n  */\r\n#define __HAL_SPDIFRX_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->IFCR = (uint32_t)(__IT_CLEAR__)) \r\n  \r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup SPDIFRX_Exported_Functions\r\n  * @{\r\n  */\r\n                                                \r\n/** @addtogroup SPDIFRX_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n/* Initialization/de-initialization functions  **********************************/\r\nHAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif);\r\nHAL_StatusTypeDef HAL_SPDIFRX_DeInit (SPDIFRX_HandleTypeDef *hspdif);\r\nvoid HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif);\r\nvoid HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif);\r\nHAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef  sDataFormat);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup SPDIFRX_Exported_Functions_Group2\r\n  * @{\r\n  */\r\n/* I/O operation functions  ***************************************************/\r\n /* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);\r\n\r\n /* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);\r\nvoid HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif);\r\n\r\n/* Non-Blocking mode: DMA */\r\nHAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);\r\n\r\nHAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif);\r\n\r\n/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/\r\nvoid HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif);\r\nvoid HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);\r\nvoid HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif);\r\nvoid HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif);\r\nvoid HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup SPDIFRX_Exported_Functions_Group3\r\n  * @{\r\n  */\r\n/* Peripheral Control and State functions  ************************************/\r\nHAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif);\r\nuint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup SPDIFRX_Private_Macros SPDIFRX Private Macros\r\n  * @{\r\n  */\r\n#define IS_SPDIFRX_INPUT_SELECT(INPUT)  (((INPUT) == SPDIFRX_INPUT_IN1) || \\\r\n                                         ((INPUT) == SPDIFRX_INPUT_IN2) || \\\r\n                                         ((INPUT) == SPDIFRX_INPUT_IN3)  || \\\r\n                                         ((INPUT) == SPDIFRX_INPUT_IN0))\r\n#define IS_SPDIFRX_MAX_RETRIES(RET)   (((RET) == SPDIFRX_MAXRETRIES_NONE) || \\\r\n                                      ((RET) == SPDIFRX_MAXRETRIES_3)  || \\\r\n                                      ((RET) == SPDIFRX_MAXRETRIES_15) || \\\r\n                                      ((RET) == SPDIFRX_MAXRETRIES_63))\r\n#define IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL)    (((VAL) == SPDIFRX_WAITFORACTIVITY_ON) || \\\r\n                                               ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF))\r\n#define IS_PREAMBLE_TYPE_MASK(VAL)           (((VAL) == SPDIFRX_PREAMBLETYPEMASK_ON) || \\\r\n                                             ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF))\r\n#define IS_VALIDITY_MASK(VAL)               (((VAL) == SPDIFRX_VALIDITYMASK_OFF) || \\\r\n                                             ((VAL) == SPDIFRX_VALIDITYMASK_ON))\r\n#define IS_PARITY_ERROR_MASK(VAL)            (((VAL) == SPDIFRX_PARITYERRORMASK_OFF) || \\\r\n                                             ((VAL) == SPDIFRX_PARITYERRORMASK_ON))\r\n#define IS_SPDIFRX_CHANNEL(CHANNEL)   (((CHANNEL) == SPDIFRX_CHANNEL_A) || \\\r\n                                       ((CHANNEL) == SPDIFRX_CHANNEL_B))\r\n#define IS_SPDIFRX_DATA_FORMAT(FORMAT)           (((FORMAT) == SPDIFRX_DATAFORMAT_LSB) || \\\r\n                                                 ((FORMAT) == SPDIFRX_DATAFORMAT_MSB) || \\\r\n                                                 ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS))\r\n#define IS_STEREO_MODE(MODE)                 (((MODE) == SPDIFRX_STEREOMODE_DISABLE) || \\\r\n                                             ((MODE) == SPDIFRX_STEREOMODE_ENABLE))\r\n                                             \r\n#define IS_CHANNEL_STATUS_MASK(VAL)          (((VAL) == SPDIFRX_CHANNELSTATUS_ON) || \\\r\n                                              ((VAL) == SPDIFRX_CHANNELSTATUS_OFF))\r\n/**                                                                                    \r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup SPDIFRX_Private_Functions SPDIFRX Private Functions\r\n  * @{\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n \r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n    \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n\r\n#endif /* __STM32F7xx_HAL_SPDIFRX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h",
    "content": " /**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_spi.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of SPI HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************  \r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_SPI_H\r\n#define __STM32F7xx_HAL_SPI_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup SPI\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup SPI_Exported_Types SPI Exported Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  SPI Configuration Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t Mode;                /*!< Specifies the SPI operating mode.\r\n                                     This parameter can be a value of @ref SPI_Mode */\r\n\r\n  uint32_t Direction;           /*!< Specifies the SPI bidirectional mode state.\r\n                                     This parameter can be a value of @ref SPI_Direction */\r\n\r\n  uint32_t DataSize;            /*!< Specifies the SPI data size.\r\n                                     This parameter can be a value of @ref SPI_Data_Size */\r\n\r\n  uint32_t CLKPolarity;         /*!< Specifies the serial clock steady state.\r\n                                     This parameter can be a value of @ref SPI_Clock_Polarity */\r\n\r\n  uint32_t CLKPhase;            /*!< Specifies the clock active edge for the bit capture.\r\n                                     This parameter can be a value of @ref SPI_Clock_Phase */\r\n\r\n  uint32_t NSS;                 /*!< Specifies whether the NSS signal is managed by\r\n                                     hardware (NSS pin) or by software using the SSI bit.\r\n                                     This parameter can be a value of @ref SPI_Slave_Select_management */\r\n\r\n  uint32_t BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be\r\n                                     used to configure the transmit and receive SCK clock.\r\n                                     This parameter can be a value of @ref SPI_BaudRate_Prescaler\r\n                                     @note The communication clock is derived from the master\r\n                                     clock. The slave clock does not need to be set. */\r\n\r\n  uint32_t FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.\r\n                                     This parameter can be a value of @ref SPI_MSB_LSB_transmission */\r\n\r\n  uint32_t TIMode;              /*!< Specifies if the TI mode is enabled or not .\r\n                                     This parameter can be a value of @ref SPI_TI_mode */\r\n\r\n  uint32_t CRCCalculation;      /*!< Specifies if the CRC calculation is enabled or not.\r\n                                     This parameter can be a value of @ref SPI_CRC_Calculation */\r\n\r\n  uint32_t CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation.\r\n                                     This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */\r\n\r\n  uint32_t CRCLength;           /*!< Specifies the CRC Length used for the CRC calculation.\r\n                                     CRC Length is only used with Data8 and Data16, not other data size\r\n                                     This parameter can be a value of @ref SPI_CRC_length */\r\n\r\n  uint32_t NSSPMode;            /*!< Specifies whether the NSSP signal is enabled or not .\r\n                                     This parameter can be a value of @ref SPI_NSSP_Mode\r\n                                     This mode is activated by the NSSP bit in the SPIx_CR2 register and\r\n                                     it takes effect only if the SPI interface is configured as Motorola SPI\r\n                                     master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,\r\n                                     CPOL setting is ignored).. */\r\n} SPI_InitTypeDef;\r\n\r\n/**\r\n  * @brief  HAL State structures definition\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_SPI_STATE_RESET      = 0x00U,    /*!< Peripheral not Initialized                         */\r\n  HAL_SPI_STATE_READY      = 0x01U,    /*!< Peripheral Initialized and ready for use           */\r\n  HAL_SPI_STATE_BUSY       = 0x02U,    /*!< an internal process is ongoing                     */\r\n  HAL_SPI_STATE_BUSY_TX    = 0x03U,    /*!< Data Transmission process is ongoing               */\r\n  HAL_SPI_STATE_BUSY_RX    = 0x04U,    /*!< Data Reception process is ongoing                  */\r\n  HAL_SPI_STATE_BUSY_TX_RX = 0x05U,    /*!< Data Transmission and Reception process is ongoing*/\r\n  HAL_SPI_STATE_ERROR      = 0x06U     /*!< SPI error state                                   */\r\n}HAL_SPI_StateTypeDef;\r\n\r\n/**\r\n  * @brief  SPI handle Structure definition\r\n  */\r\ntypedef struct __SPI_HandleTypeDef\r\n{\r\n  SPI_TypeDef             *Instance;      /* SPI registers base address     */\r\n\r\n  SPI_InitTypeDef         Init;           /* SPI communication parameters   */\r\n\r\n  uint8_t                 *pTxBuffPtr;    /* Pointer to SPI Tx transfer Buffer */\r\n\r\n  uint16_t                TxXferSize;     /* SPI Tx Transfer size */\r\n\r\n  uint16_t                TxXferCount;    /* SPI Tx Transfer Counter */\r\n\r\n  uint8_t                 *pRxBuffPtr;    /* Pointer to SPI Rx transfer Buffer */\r\n\r\n  uint16_t                RxXferSize;     /* SPI Rx Transfer size */\r\n\r\n  uint16_t                RxXferCount;    /* SPI Rx Transfer Counter */\r\n\r\n  uint32_t                CRCSize;        /* SPI CRC size used for the transfer */\r\n\r\n  void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Rx IRQ handler   */\r\n\r\n  void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Tx IRQ handler   */\r\n\r\n  DMA_HandleTypeDef       *hdmatx;        /* SPI Tx DMA Handle parameters   */\r\n\r\n  DMA_HandleTypeDef       *hdmarx;        /* SPI Rx DMA Handle parameters   */\r\n\r\n  HAL_LockTypeDef         Lock;           /* Locking object                 */\r\n\r\n  __IO HAL_SPI_StateTypeDef    State;          /* SPI communication state        */\r\n\r\n  __IO uint32_t                ErrorCode;      /* SPI Error code                 */\r\n\r\n}SPI_HandleTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup SPI_Exported_Constants SPI Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup SPI_Error_Code SPI Error Code\r\n  * @{\r\n  */\r\n#define HAL_SPI_ERROR_NONE   ((uint32_t)0x00000000U)  /*!< No error                          */\r\n#define HAL_SPI_ERROR_MODF   ((uint32_t)0x00000001U)  /*!< MODF error                        */\r\n#define HAL_SPI_ERROR_CRC    ((uint32_t)0x00000002U)  /*!< CRC error                         */\r\n#define HAL_SPI_ERROR_OVR    ((uint32_t)0x00000004U)  /*!< OVR error                         */\r\n#define HAL_SPI_ERROR_FRE    ((uint32_t)0x00000008U)  /*!< FRE error                         */\r\n#define HAL_SPI_ERROR_DMA    ((uint32_t)0x00000010U)  /*!< DMA transfer error                */\r\n#define HAL_SPI_ERROR_FLAG   ((uint32_t)0x00000020U)  /*!< Error on BSY/TXE/FTLVL/FRLVL Flag */\r\n#define HAL_SPI_ERROR_UNKNOW ((uint32_t)0x00000040U)  /*!< Unknow Error error                */\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup SPI_Mode SPI Mode\r\n  * @{\r\n  */\r\n#define SPI_MODE_SLAVE                  ((uint32_t)0x00000000U)\r\n#define SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_Direction SPI Direction Mode\r\n  * @{\r\n  */\r\n#define SPI_DIRECTION_2LINES            ((uint32_t)0x00000000U)\r\n#define SPI_DIRECTION_2LINES_RXONLY     SPI_CR1_RXONLY\r\n#define SPI_DIRECTION_1LINE             SPI_CR1_BIDIMODE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_Data_Size SPI Data Size\r\n  * @{\r\n  */\r\n#define SPI_DATASIZE_4BIT               ((uint32_t)0x0300U)\r\n#define SPI_DATASIZE_5BIT               ((uint32_t)0x0400U)\r\n#define SPI_DATASIZE_6BIT               ((uint32_t)0x0500U)\r\n#define SPI_DATASIZE_7BIT               ((uint32_t)0x0600U)\r\n#define SPI_DATASIZE_8BIT               ((uint32_t)0x0700U)\r\n#define SPI_DATASIZE_9BIT               ((uint32_t)0x0800U)\r\n#define SPI_DATASIZE_10BIT              ((uint32_t)0x0900U)\r\n#define SPI_DATASIZE_11BIT              ((uint32_t)0x0A00U)\r\n#define SPI_DATASIZE_12BIT              ((uint32_t)0x0B00U)\r\n#define SPI_DATASIZE_13BIT              ((uint32_t)0x0C00U)\r\n#define SPI_DATASIZE_14BIT              ((uint32_t)0x0D00U)\r\n#define SPI_DATASIZE_15BIT              ((uint32_t)0x0E00U)\r\n#define SPI_DATASIZE_16BIT              ((uint32_t)0x0F00U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_Clock_Polarity SPI Clock Polarity\r\n  * @{\r\n  */\r\n#define SPI_POLARITY_LOW                ((uint32_t)0x00000000U)\r\n#define SPI_POLARITY_HIGH               SPI_CR1_CPOL\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_Clock_Phase SPI Clock Phase\r\n  * @{\r\n  */\r\n#define SPI_PHASE_1EDGE                 ((uint32_t)0x00000000U)\r\n#define SPI_PHASE_2EDGE                 SPI_CR1_CPHA\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_Slave_Select_management SPI Slave Select management\r\n  * @{\r\n  */\r\n#define SPI_NSS_SOFT                    SPI_CR1_SSM\r\n#define SPI_NSS_HARD_INPUT              ((uint32_t)0x00000000U)\r\n#define SPI_NSS_HARD_OUTPUT             ((uint32_t)0x00040000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode\r\n  * @{\r\n  */\r\n#define SPI_NSS_PULSE_ENABLE            SPI_CR2_NSSP\r\n#define SPI_NSS_PULSE_DISABLE           ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler\r\n  * @{\r\n  */\r\n#define SPI_BAUDRATEPRESCALER_2         ((uint32_t)0x00000000U)\r\n#define SPI_BAUDRATEPRESCALER_4         ((uint32_t)0x00000008U)\r\n#define SPI_BAUDRATEPRESCALER_8         ((uint32_t)0x00000010U)\r\n#define SPI_BAUDRATEPRESCALER_16        ((uint32_t)0x00000018U)\r\n#define SPI_BAUDRATEPRESCALER_32        ((uint32_t)0x00000020U)\r\n#define SPI_BAUDRATEPRESCALER_64        ((uint32_t)0x00000028U)\r\n#define SPI_BAUDRATEPRESCALER_128       ((uint32_t)0x00000030U)\r\n#define SPI_BAUDRATEPRESCALER_256       ((uint32_t)0x00000038U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission\r\n  * @{\r\n  */\r\n#define SPI_FIRSTBIT_MSB                ((uint32_t)0x00000000U)\r\n#define SPI_FIRSTBIT_LSB                SPI_CR1_LSBFIRST\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_TI_mode SPI TI mode\r\n  * @{\r\n  */\r\n#define SPI_TIMODE_DISABLE              ((uint32_t)0x00000000U)\r\n#define SPI_TIMODE_ENABLE               SPI_CR2_FRF\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_CRC_Calculation SPI CRC Calculation\r\n  * @{\r\n  */\r\n#define SPI_CRCCALCULATION_DISABLE      ((uint32_t)0x00000000U)\r\n#define SPI_CRCCALCULATION_ENABLE       SPI_CR1_CRCEN\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_CRC_length SPI CRC Length\r\n  * @{\r\n  * This parameter can be one of the following values:\r\n  *     SPI_CRC_LENGTH_DATASIZE: aligned with the data size\r\n  *     SPI_CRC_LENGTH_8BIT    : CRC 8bit\r\n  *     SPI_CRC_LENGTH_16BIT   : CRC 16bit\r\n  */\r\n#define SPI_CRC_LENGTH_DATASIZE         ((uint32_t)0x00000000U)\r\n#define SPI_CRC_LENGTH_8BIT             ((uint32_t)0x00000001U)\r\n#define SPI_CRC_LENGTH_16BIT            ((uint32_t)0x00000002U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold\r\n  * @{\r\n  * This parameter can be one of the following values:\r\n  *     SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :\r\n  *          RXNE event is generated if the FIFO\r\n  *          level is greater or equal to 1/2(16-bits).\r\n  *     SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO\r\n  *          level is greater or equal to 1/4(8 bits). */\r\n#define SPI_RXFIFO_THRESHOLD            SPI_CR2_FRXTH\r\n#define SPI_RXFIFO_THRESHOLD_QF         SPI_CR2_FRXTH\r\n#define SPI_RXFIFO_THRESHOLD_HF         ((uint32_t)0x00000000U)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition\r\n  * @brief SPI Interrupt definition\r\n  *        Elements values convention: 0xXXXXXXXX\r\n  *           - XXXXXXXX  : Interrupt control mask\r\n  * @{\r\n  */\r\n#define SPI_IT_TXE                      SPI_CR2_TXEIE\r\n#define SPI_IT_RXNE                     SPI_CR2_RXNEIE\r\n#define SPI_IT_ERR                      SPI_CR2_ERRIE\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup SPI_Flag_definition SPI Flag definition\r\n  * @brief Flag definition\r\n  *        Elements values convention: 0xXXXXYYYY\r\n  *           - XXXX  : Flag register Index\r\n  *           - YYYY  : Flag mask\r\n  * @{\r\n  */\r\n#define SPI_FLAG_RXNE                   SPI_SR_RXNE   /* SPI status flag: Rx buffer not empty flag */\r\n#define SPI_FLAG_TXE                    SPI_SR_TXE    /* SPI status flag: Tx buffer empty flag */\r\n#define SPI_FLAG_BSY                    SPI_SR_BSY    /* SPI status flag: Busy flag */\r\n#define SPI_FLAG_CRCERR                 SPI_SR_CRCERR /* SPI Error flag: CRC error flag */\r\n#define SPI_FLAG_MODF                   SPI_SR_MODF   /* SPI Error flag: Mode fault flag */\r\n#define SPI_FLAG_OVR                    SPI_SR_OVR    /* SPI Error flag: Overrun flag */\r\n#define SPI_FLAG_FRE                    SPI_SR_FRE    /* SPI Error flag: TI mode frame format error flag */\r\n#define SPI_FLAG_FTLVL                  SPI_SR_FTLVL  /* SPI fifo transmission level */\r\n#define SPI_FLAG_FRLVL                  SPI_SR_FRLVL  /* SPI fifo reception level */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level\r\n  * @{\r\n  */\r\n#define SPI_FTLVL_EMPTY           ((uint32_t)0x0000U)\r\n#define SPI_FTLVL_QUARTER_FULL    ((uint32_t)0x0800U)\r\n#define SPI_FTLVL_HALF_FULL       ((uint32_t)0x1000U)\r\n#define SPI_FTLVL_FULL            ((uint32_t)0x1800U)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level\r\n  * @{\r\n  */\r\n#define SPI_FRLVL_EMPTY           ((uint32_t)0x0000U)\r\n#define SPI_FRLVL_QUARTER_FULL    ((uint32_t)0x0200U)\r\n#define SPI_FRLVL_HALF_FULL       ((uint32_t)0x0400U)\r\n#define SPI_FRLVL_FULL            ((uint32_t)0x0600U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macros ------------------------------------------------------------*/\r\n/** @defgroup SPI_Exported_Macros SPI Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief  Reset SPI handle state\r\n  * @param  __HANDLE__: SPI handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)\r\n\r\n/** @brief  Enables or disables the specified SPI interrupts.\r\n  * @param  __HANDLE__ : specifies the SPI Handle.\r\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r\n  * @param  __INTERRUPT__ : specifies the interrupt source to enable or disable.\r\n  *        This parameter can be one of the following values:\r\n  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable\r\n  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable\r\n  *            @arg SPI_IT_ERR: Error interrupt enable\r\n  * @retval None\r\n  */\r\n#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))\r\n#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))\r\n\r\n/** @brief  Checks if the specified SPI interrupt source is enabled or disabled.\r\n  * @param  __HANDLE__ : specifies the SPI Handle.\r\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r\n  * @param  __INTERRUPT__ : specifies the SPI interrupt source to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable\r\n  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable\r\n  *            @arg SPI_IT_ERR: Error interrupt enable\r\n  * @retval The new state of __IT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r\n\r\n/** @brief  Checks whether the specified SPI flag is set or not.\r\n  * @param  __HANDLE__ : specifies the SPI Handle.\r\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r\n  * @param  __FLAG__ : specifies the flag to check.\r\n  *        This parameter can be one of the following values:\r\n  *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag\r\n  *            @arg SPI_FLAG_TXE: Transmit buffer empty flag\r\n  *            @arg SPI_FLAG_CRCERR: CRC error flag\r\n  *            @arg SPI_FLAG_MODF: Mode fault flag\r\n  *            @arg SPI_FLAG_OVR: Overrun flag\r\n  *            @arg SPI_FLAG_BSY: Busy flag\r\n  *            @arg SPI_FLAG_FRE: Frame format error flag\r\n  *            @arg SPI_FLAG_FTLVL: SPI fifo transmission level\r\n  *            @arg SPI_FLAG_FRLVL: SPI fifo reception level\r\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))\r\n\r\n/** @brief  Clears the SPI CRCERR pending flag.\r\n  * @param  __HANDLE__ : specifies the SPI Handle.\r\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r\n  * @retval None\r\n  */\r\n#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))\r\n\r\n/** @brief  Clears the SPI MODF pending flag.\r\n  * @param  __HANDLE__ : specifies the SPI Handle.\r\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r\n  *\r\n  * @retval None\r\n  */\r\n#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)        \\\r\n   do{                                              \\\r\n     __IO uint32_t tmpreg;                          \\\r\n     tmpreg = (__HANDLE__)->Instance->SR;           \\\r\n     (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \\\r\n     UNUSED(tmpreg);                                \\\r\n   } while(0)\r\n\r\n/** @brief  Clears the SPI OVR pending flag.\r\n  * @param  __HANDLE__ : specifies the SPI Handle.\r\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r\n  *\r\n  * @retval None\r\n  */\r\n#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)         \\\r\n   do{                                              \\\r\n     __IO uint32_t tmpreg;                          \\\r\n     tmpreg = (__HANDLE__)->Instance->DR;           \\\r\n     tmpreg = (__HANDLE__)->Instance->SR;           \\\r\n     UNUSED(tmpreg);                                \\\r\n   } while(0)\r\n\r\n/** @brief  Clears the SPI FRE pending flag.\r\n  * @param  __HANDLE__ : specifies the SPI Handle.\r\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r\n  *\r\n  * @retval None\r\n  */\r\n#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)         \\\r\n   do{                                              \\\r\n     __IO uint32_t tmpreg;                          \\\r\n     tmpreg = (__HANDLE__)->Instance->SR;           \\\r\n     UNUSED(tmpreg);                                \\\r\n   } while(0)\r\n\r\n/** @brief  Enables the SPI.\r\n  * @param  __HANDLE__ : specifies the SPI Handle.\r\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r\n  * @retval None\r\n  */\r\n#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |=  SPI_CR1_SPE)\r\n\r\n/** @brief  Disables the SPI.\r\n  * @param  __HANDLE__ : specifies the SPI Handle.\r\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r\n  * @retval None\r\n  */\r\n#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros --------------------------------------------------------*/\r\n/** @defgroup SPI_Private_Macros   SPI Private Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief  Sets the SPI transmit-only mode.\r\n  * @param  __HANDLE__ : specifies the SPI Handle.\r\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r\n  * @retval None\r\n  */\r\n#define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)\r\n\r\n/** @brief  Sets the SPI receive-only mode.\r\n  * @param  __HANDLE__ : specifies the SPI Handle.\r\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r\n  * @retval None\r\n  */\r\n#define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))\r\n\r\n/** @brief  Resets the CRC calculation of the SPI.\r\n  * @param  __HANDLE__ : specifies the SPI Handle.\r\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\r\n  * @retval None\r\n  */\r\n#define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\\\r\n                                     (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)\r\n\r\n#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \\\r\n                           ((MODE) == SPI_MODE_MASTER))\r\n\r\n#define IS_SPI_DIRECTION(MODE)   (((MODE) == SPI_DIRECTION_2LINES) || \\\r\n                                  ((MODE) == SPI_DIRECTION_2LINES_RXONLY) ||\\\r\n                                  ((MODE) == SPI_DIRECTION_1LINE))\r\n\r\n#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)\r\n\r\n#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \\\r\n                                                 ((MODE) == SPI_DIRECTION_1LINE))\r\n\r\n#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \\\r\n                                   ((DATASIZE) == SPI_DATASIZE_15BIT) || \\\r\n                                   ((DATASIZE) == SPI_DATASIZE_14BIT) || \\\r\n                                   ((DATASIZE) == SPI_DATASIZE_13BIT) || \\\r\n                                   ((DATASIZE) == SPI_DATASIZE_12BIT) || \\\r\n                                   ((DATASIZE) == SPI_DATASIZE_11BIT) || \\\r\n                                   ((DATASIZE) == SPI_DATASIZE_10BIT) || \\\r\n                                   ((DATASIZE) == SPI_DATASIZE_9BIT)  || \\\r\n                                   ((DATASIZE) == SPI_DATASIZE_8BIT)  || \\\r\n                                   ((DATASIZE) == SPI_DATASIZE_7BIT)  || \\\r\n                                   ((DATASIZE) == SPI_DATASIZE_6BIT)  || \\\r\n                                   ((DATASIZE) == SPI_DATASIZE_5BIT)  || \\\r\n                                   ((DATASIZE) == SPI_DATASIZE_4BIT))\r\n\r\n#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \\\r\n                           ((CPOL) == SPI_POLARITY_HIGH))\r\n\r\n#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \\\r\n                           ((CPHA) == SPI_PHASE_2EDGE))\r\n\r\n#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \\\r\n                         ((NSS) == SPI_NSS_HARD_INPUT) || \\\r\n                         ((NSS) == SPI_NSS_HARD_OUTPUT))\r\n\r\n#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \\\r\n                           ((NSSP) == SPI_NSS_PULSE_DISABLE))\r\n\r\n#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \\\r\n                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \\\r\n                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \\\r\n                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \\\r\n                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \\\r\n                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \\\r\n                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \\\r\n                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))\r\n\r\n#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \\\r\n                               ((BIT) == SPI_FIRSTBIT_LSB))\r\n\r\n#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \\\r\n                             ((MODE) == SPI_TIMODE_ENABLE))\r\n\r\n#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \\\r\n                                             ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))\r\n\r\n#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\\\r\n                                   ((LENGTH) == SPI_CRC_LENGTH_8BIT)  ||   \\\r\n                                   ((LENGTH) == SPI_CRC_LENGTH_16BIT))\r\n\r\n#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF) && (((POLYNOMIAL)&0x1) != 0))\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup SPI_Exported_Functions SPI Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions\r\n  * @{\r\n  */\r\n\r\n/* Initialization and de-initialization functions  ****************************/\r\nHAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);\r\nHAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);\r\nvoid HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);\r\nvoid HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup SPI_Exported_Functions_Group2 IO operation functions\r\n  * @{\r\n  */\r\n\r\n/* IO operation functions *****************************************************/\r\nHAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);\r\nHAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);\r\nHAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);\r\n\r\nvoid HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);\r\nvoid HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);\r\nvoid HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);\r\nvoid HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);\r\nvoid HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);\r\nvoid HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);\r\nvoid HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);\r\nvoid HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions\r\n  * @{\r\n  */\r\n\r\n/* Peripheral State and Error functions ***************************************/\r\nHAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);\r\nuint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_SPI_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sram.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_sram.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of SRAM HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_SRAM_H\r\n#define __STM32F7xx_HAL_SRAM_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_ll_fmc.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n/** @addtogroup SRAM\r\n  * @{\r\n  */ \r\n\r\n/* Exported typedef ----------------------------------------------------------*/\r\n\r\n/** @defgroup SRAM_Exported_Types SRAM Exported Types\r\n  * @{\r\n  */\r\n/** \r\n  * @brief  HAL SRAM State structures definition  \r\n  */ \r\ntypedef enum\r\n{\r\n  HAL_SRAM_STATE_RESET     = 0x00U,  /*!< SRAM not yet initialized or disabled           */\r\n  HAL_SRAM_STATE_READY     = 0x01U,  /*!< SRAM initialized and ready for use             */\r\n  HAL_SRAM_STATE_BUSY      = 0x02U,  /*!< SRAM internal process is ongoing               */\r\n  HAL_SRAM_STATE_ERROR     = 0x03U,  /*!< SRAM error state                               */\r\n  HAL_SRAM_STATE_PROTECTED = 0x04U   /*!< SRAM peripheral NORSRAM device write protected */\r\n  \r\n}HAL_SRAM_StateTypeDef;\r\n\r\n/** \r\n  * @brief  SRAM handle Structure definition  \r\n  */ \r\ntypedef struct\r\n{\r\n  FMC_NORSRAM_TypeDef           *Instance;  /*!< Register base address                        */ \r\n  \r\n  FMC_NORSRAM_EXTENDED_TypeDef  *Extended;  /*!< Extended mode register base address          */\r\n  \r\n  FMC_NORSRAM_InitTypeDef       Init;       /*!< SRAM device control configuration parameters */\r\n\r\n  HAL_LockTypeDef               Lock;       /*!< SRAM locking object                          */ \r\n  \r\n  __IO HAL_SRAM_StateTypeDef    State;      /*!< SRAM device access state                     */\r\n  \r\n  DMA_HandleTypeDef             *hdma;      /*!< Pointer DMA handler                          */\r\n  \r\n}SRAM_HandleTypeDef; \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/* Exported macro ------------------------------------------------------------*/\r\n\r\n/** @defgroup SRAM_Exported_Macros SRAM Exported Macros\r\n * @{\r\n */\r\n\r\n/** @brief Reset SRAM handle state\r\n  * @param  __HANDLE__: SRAM handle\r\n  * @retval None\r\n  */\r\n#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions\r\n * @{\r\n */\r\n\r\n/* Initialization/de-initialization functions  ********************************/\r\nHAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);\r\nHAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);\r\nvoid HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);\r\nvoid HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions\r\n * @{\r\n */\r\n\r\n/* I/O operation functions  ***************************************************/\r\nHAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);\r\nHAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);\r\nHAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);\r\nHAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);\r\nHAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);\r\nHAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);\r\nHAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);\r\nHAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);\r\n\r\nvoid HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);\r\nvoid HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @addtogroup SRAM_Exported_Functions_Group3 Control functions\r\n * @{\r\n */\r\n\r\n/* SRAM Control functions  ****************************************************/\r\nHAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);\r\nHAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions\r\n * @{\r\n */\r\n\r\n/* SRAM  State functions ******************************************************/\r\nHAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_SRAM_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_tim.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of TIM HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_TIM_H\r\n#define __STM32F7xx_HAL_TIM_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup TIM\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup TIM_Exported_Types TIM Exported Types\r\n  * @{\r\n  */\r\n  \r\n/** \r\n  * @brief  TIM Time base Configuration Structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.\r\n                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r\n\r\n  uint32_t CounterMode;       /*!< Specifies the counter mode.\r\n                                   This parameter can be a value of @ref TIM_Counter_Mode */\r\n\r\n  uint32_t Period;            /*!< Specifies the period value to be loaded into the active\r\n                                   Auto-Reload Register at the next update event.\r\n                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */\r\n\r\n  uint32_t ClockDivision;     /*!< Specifies the clock division.\r\n                                   This parameter can be a value of @ref TIM_ClockDivision */\r\n\r\n  uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR down-counter\r\n                                    reaches zero, an update event is generated and counting restarts\r\n                                    from the RCR value (N).\r\n                                    This means in PWM mode that (N+1) corresponds to:\r\n                                        - the number of PWM periods in edge-aligned mode\r\n                                        - the number of half PWM period in center-aligned mode\r\n                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. \r\n                                     @note This parameter is valid only for TIM1 and TIM8. */\r\n} TIM_Base_InitTypeDef;\r\n\r\n/** \r\n  * @brief  TIM Output Compare Configuration Structure definition  \r\n  */\r\n\r\ntypedef struct\r\n{\r\n  uint32_t OCMode;        /*!< Specifies the TIM mode.\r\n                               This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */\r\n\r\n  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register. \r\n                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r\n\r\n  uint32_t OCPolarity;    /*!< Specifies the output polarity.\r\n                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */\r\n\r\n  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.\r\n                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity\r\n                               @note This parameter is valid only for TIM1 and TIM8. */\r\n  \r\n  uint32_t OCFastMode;   /*!< Specifies the Fast mode state.\r\n                               This parameter can be a value of @ref TIM_Output_Fast_State\r\n                               @note This parameter is valid only in PWM1 and PWM2 mode. */\r\n\r\n\r\n  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.\r\n                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State\r\n                               @note This parameter is valid only for TIM1 and TIM8. */\r\n\r\n  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.\r\n                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State\r\n                               @note This parameter is valid only for TIM1 and TIM8. */\r\n} TIM_OC_InitTypeDef;  \r\n\r\n/** \r\n  * @brief  TIM One Pulse Mode Configuration Structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t OCMode;        /*!< Specifies the TIM mode.\r\n                               This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */\r\n\r\n  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register. \r\n                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\r\n\r\n  uint32_t OCPolarity;    /*!< Specifies the output polarity.\r\n                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */\r\n\r\n  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.\r\n                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity\r\n                               @note This parameter is valid only for TIM1 and TIM8. */\r\n\r\n  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.\r\n                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State\r\n                               @note This parameter is valid only for TIM1 and TIM8. */\r\n\r\n  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.\r\n                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State\r\n                               @note This parameter is valid only for TIM1 and TIM8. */\r\n\r\n  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.\r\n                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r\n\r\n  uint32_t ICSelection;   /*!< Specifies the input.\r\n                              This parameter can be a value of @ref TIM_Input_Capture_Selection */\r\n\r\n  uint32_t ICFilter;      /*!< Specifies the input capture filter.\r\n                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */  \r\n} TIM_OnePulse_InitTypeDef;  \r\n\r\n\r\n/** \r\n  * @brief  TIM Input Capture Configuration Structure definition  \r\n  */\r\n\r\ntypedef struct\r\n{\r\n  uint32_t  ICPolarity;   /*!< Specifies the active edge of the input signal.\r\n                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r\n\r\n  uint32_t ICSelection;  /*!< Specifies the input.\r\n                              This parameter can be a value of @ref TIM_Input_Capture_Selection */\r\n\r\n  uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.\r\n                              This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r\n\r\n  uint32_t ICFilter;     /*!< Specifies the input capture filter.\r\n                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r\n} TIM_IC_InitTypeDef;\r\n\r\n/** \r\n  * @brief  TIM Encoder Configuration Structure definition  \r\n  */\r\n\r\ntypedef struct\r\n{\r\n  uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.\r\n                               This parameter can be a value of @ref TIM_Encoder_Mode */\r\n                                  \r\n  uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.\r\n                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r\n\r\n  uint32_t IC1Selection;  /*!< Specifies the input.\r\n                               This parameter can be a value of @ref TIM_Input_Capture_Selection */\r\n\r\n  uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.\r\n                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r\n\r\n  uint32_t IC1Filter;     /*!< Specifies the input capture filter.\r\n                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r\n                                  \r\n  uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.\r\n                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r\n\r\n  uint32_t IC2Selection;  /*!< Specifies the input.\r\n                              This parameter can be a value of @ref TIM_Input_Capture_Selection */\r\n\r\n  uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.\r\n                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r\n\r\n  uint32_t IC2Filter;     /*!< Specifies the input capture filter.\r\n                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r\n} TIM_Encoder_InitTypeDef;\r\n\r\n/** \r\n  * @brief  Clock Configuration Handle Structure definition  \r\n  */ \r\ntypedef struct\r\n{\r\n  uint32_t ClockSource;     /*!< TIM clock sources. \r\n                                 This parameter can be a value of @ref TIM_Clock_Source */ \r\n  uint32_t ClockPolarity;   /*!< TIM clock polarity. \r\n                                 This parameter can be a value of @ref TIM_Clock_Polarity */\r\n  uint32_t ClockPrescaler;  /*!< TIM clock prescaler. \r\n                                 This parameter can be a value of @ref TIM_Clock_Prescaler */\r\n  uint32_t ClockFilter;    /*!< TIM clock filter. \r\n                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r\n}TIM_ClockConfigTypeDef;\r\n\r\n/** \r\n  * @brief  Clear Input Configuration Handle Structure definition  \r\n  */ \r\ntypedef struct\r\n{ \r\n  uint32_t ClearInputState;      /*!< TIM clear Input state. \r\n                                      This parameter can be ENABLE or DISABLE */  \r\n  uint32_t ClearInputSource;     /*!< TIM clear Input sources. \r\n                                      This parameter can be a value of @ref TIMEx_ClearInput_Source */ \r\n  uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity. \r\n                                      This parameter can be a value of @ref TIM_ClearInput_Polarity */\r\n  uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler. \r\n                                      This parameter can be a value of @ref TIM_ClearInput_Prescaler */\r\n  uint32_t ClearInputFilter;    /*!< TIM Clear Input filter. \r\n                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\r\n}TIM_ClearInputConfigTypeDef;\r\n\r\n/** \r\n  * @brief  TIM Slave configuration Structure definition  \r\n  */ \r\ntypedef struct {\r\n  uint32_t  SlaveMode;         /*!< Slave mode selection \r\n                                  This parameter can be a value of @ref TIMEx_Slave_Mode */ \r\n  uint32_t  InputTrigger;      /*!< Input Trigger source \r\n                                  This parameter can be a value of @ref TIM_Trigger_Selection */\r\n  uint32_t  TriggerPolarity;   /*!< Input Trigger polarity \r\n                                  This parameter can be a value of @ref TIM_Trigger_Polarity */\r\n  uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler \r\n                                  This parameter can be a value of @ref TIM_Trigger_Prescaler */\r\n  uint32_t  TriggerFilter;     /*!< Input trigger filter \r\n                                  This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */  \r\n\r\n}TIM_SlaveConfigTypeDef;\r\n\r\n/** \r\n  * @brief  HAL State structures definition  \r\n  */ \r\ntypedef enum\r\n{\r\n  HAL_TIM_STATE_RESET             = 0x00U,    /*!< Peripheral not yet initialized or disabled  */\r\n  HAL_TIM_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */\r\n  HAL_TIM_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */\r\n  HAL_TIM_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */\r\n  HAL_TIM_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                */\r\n}HAL_TIM_StateTypeDef;\r\n\r\n/** \r\n  * @brief  HAL Active channel structures definition  \r\n  */ \r\ntypedef enum\r\n{\r\n  HAL_TIM_ACTIVE_CHANNEL_1        = 0x01U,    /*!< The active channel is 1     */\r\n  HAL_TIM_ACTIVE_CHANNEL_2        = 0x02U,    /*!< The active channel is 2     */\r\n  HAL_TIM_ACTIVE_CHANNEL_3        = 0x04U,    /*!< The active channel is 3     */\r\n  HAL_TIM_ACTIVE_CHANNEL_4        = 0x08U,    /*!< The active channel is 4     */\r\n  HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00U     /*!< All active channels cleared */\r\n}HAL_TIM_ActiveChannel;\r\n\r\n/** \r\n  * @brief  TIM Time Base Handle Structure definition  \r\n  */ \r\ntypedef struct\r\n{\r\n  TIM_TypeDef                 *Instance;     /*!< Register base address             */\r\n  TIM_Base_InitTypeDef        Init;          /*!< TIM Time Base required parameters */\r\n  HAL_TIM_ActiveChannel       Channel;       /*!< Active channel                    */\r\n  DMA_HandleTypeDef           *hdma[7];      /*!< DMA Handlers array\r\n                                             This array is accessed by a @ref DMA_Handle_index */\r\n  HAL_LockTypeDef             Lock;          /*!< Locking object                    */\r\n  __IO HAL_TIM_StateTypeDef   State;         /*!< TIM operation state               */\r\n}TIM_HandleTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup TIM_Exported_Constants  TIM Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity\r\n  * @{\r\n  */\r\n#define  TIM_INPUTCHANNELPOLARITY_RISING      ((uint32_t)0x00000000U)            /*!< Polarity for TIx source */\r\n#define  TIM_INPUTCHANNELPOLARITY_FALLING     (TIM_CCER_CC1P)                   /*!< Polarity for TIx source */\r\n#define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_ETR_Polarity  TIM ETR Polarity\r\n  * @{\r\n  */\r\n#define TIM_ETRPOLARITY_INVERTED              (TIM_SMCR_ETP)                    /*!< Polarity for ETR source */\r\n#define TIM_ETRPOLARITY_NONINVERTED           ((uint32_t)0x0000U)                /*!< Polarity for ETR source */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_ETR_Prescaler  TIM ETR Prescaler\r\n  * @{\r\n  */\r\n#define TIM_ETRPRESCALER_DIV1                 ((uint32_t)0x0000U)                /*!< No prescaler is used */\r\n#define TIM_ETRPRESCALER_DIV2                 (TIM_SMCR_ETPS_0)                 /*!< ETR input source is divided by 2 */\r\n#define TIM_ETRPRESCALER_DIV4                 (TIM_SMCR_ETPS_1)                 /*!< ETR input source is divided by 4 */\r\n#define TIM_ETRPRESCALER_DIV8                 (TIM_SMCR_ETPS)                   /*!< ETR input source is divided by 8 */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Counter_Mode  TIM Counter Mode\r\n  * @{\r\n  */\r\n#define TIM_COUNTERMODE_UP                 ((uint32_t)0x0000U)\r\n#define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR\r\n#define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0\r\n#define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1\r\n#define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_ClockDivision TIM Clock Division\r\n  * @{\r\n  */\r\n#define TIM_CLOCKDIVISION_DIV1                       ((uint32_t)0x0000U)\r\n#define TIM_CLOCKDIVISION_DIV2                       (TIM_CR1_CKD_0)\r\n#define TIM_CLOCKDIVISION_DIV4                       (TIM_CR1_CKD_1)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Output_Compare_State TIM Output Compare State\r\n  * @{\r\n  */\r\n#define TIM_OUTPUTSTATE_DISABLE            ((uint32_t)0x0000U)\r\n#define TIM_OUTPUTSTATE_ENABLE             (TIM_CCER_CC1E)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Output_Fast_State  TIM Output Fast State \r\n  * @{\r\n  */\r\n#define TIM_OCFAST_DISABLE                ((uint32_t)0x0000U)\r\n#define TIM_OCFAST_ENABLE                 (TIM_CCMR1_OC1FE)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State\r\n  * @{\r\n  */\r\n#define TIM_OUTPUTNSTATE_DISABLE            ((uint32_t)0x0000U)\r\n#define TIM_OUTPUTNSTATE_ENABLE             (TIM_CCER_CC1NE)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity \r\n  * @{\r\n  */\r\n#define TIM_OCPOLARITY_HIGH                ((uint32_t)0x0000U)\r\n#define TIM_OCPOLARITY_LOW                 (TIM_CCER_CC1P)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity\r\n  * @{\r\n  */\r\n#define TIM_OCNPOLARITY_HIGH               ((uint32_t)0x0000U)\r\n#define TIM_OCNPOLARITY_LOW                (TIM_CCER_CC1NP)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Output_Compare_Idle_State  TIM Output Compare Idle State\r\n  * @{\r\n  */\r\n#define TIM_OCIDLESTATE_SET                (TIM_CR2_OIS1)\r\n#define TIM_OCIDLESTATE_RESET              ((uint32_t)0x0000U)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup TIM_Output_Compare_N_Idle_State  TIM Output Compare N Idle State\r\n  * @{\r\n  */\r\n#define TIM_OCNIDLESTATE_SET               (TIM_CR2_OIS1N)\r\n#define TIM_OCNIDLESTATE_RESET             ((uint32_t)0x0000U)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup TIM_Input_Capture_Polarity  TIM Input Capture Polarity \r\n  * @{\r\n  */\r\n#define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING\r\n#define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING\r\n#define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Input_Capture_Selection  TIM Input Capture Selection\r\n  * @{\r\n  */\r\n#define TIM_ICSELECTION_DIRECTTI           (TIM_CCMR1_CC1S_0)   /*!< TIM Input 1, 2, 3 or 4 is selected to be \r\n                                                                     connected to IC1, IC2, IC3 or IC4, respectively */\r\n#define TIM_ICSELECTION_INDIRECTTI         (TIM_CCMR1_CC1S_1)   /*!< TIM Input 1, 2, 3 or 4 is selected to be\r\n                                                                     connected to IC2, IC1, IC4 or IC3, respectively */\r\n#define TIM_ICSELECTION_TRC                (TIM_CCMR1_CC1S)     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Input_Capture_Prescaler  TIM Input Capture Prescaler\r\n  * @{\r\n  */\r\n#define TIM_ICPSC_DIV1                     ((uint32_t)0x0000U)       /*!< Capture performed each time an edge is detected on the capture input */\r\n#define TIM_ICPSC_DIV2                     (TIM_CCMR1_IC1PSC_0)     /*!< Capture performed once every 2 events */\r\n#define TIM_ICPSC_DIV4                     (TIM_CCMR1_IC1PSC_1)     /*!< Capture performed once every 4 events */\r\n#define TIM_ICPSC_DIV8                     (TIM_CCMR1_IC1PSC)       /*!< Capture performed once every 8 events */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode\r\n  * @{\r\n  */\r\n#define TIM_OPMODE_SINGLE                  (TIM_CR1_OPM)\r\n#define TIM_OPMODE_REPETITIVE              ((uint32_t)0x0000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Encoder_Mode TIM Encoder Mode\r\n  * @{\r\n  */\r\n#define TIM_ENCODERMODE_TI1                (TIM_SMCR_SMS_0)\r\n#define TIM_ENCODERMODE_TI2                (TIM_SMCR_SMS_1)\r\n#define TIM_ENCODERMODE_TI12               (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Interrupt_definition  TIM Interrupt definition\r\n  * @{\r\n  */ \r\n#define TIM_IT_UPDATE           (TIM_DIER_UIE)\r\n#define TIM_IT_CC1              (TIM_DIER_CC1IE)\r\n#define TIM_IT_CC2              (TIM_DIER_CC2IE)\r\n#define TIM_IT_CC3              (TIM_DIER_CC3IE)\r\n#define TIM_IT_CC4              (TIM_DIER_CC4IE)\r\n#define TIM_IT_COM              (TIM_DIER_COMIE)\r\n#define TIM_IT_TRIGGER          (TIM_DIER_TIE)\r\n#define TIM_IT_BREAK            (TIM_DIER_BIE)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup TIM_Commutation_Source  TIM Commutation Source \r\n  * @{\r\n  */  \r\n#define TIM_COMMUTATION_TRGI              (TIM_CR2_CCUS)\r\n#define TIM_COMMUTATION_SOFTWARE          ((uint32_t)0x0000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_DMA_sources  TIM DMA sources\r\n  * @{\r\n  */\r\n#define TIM_DMA_UPDATE                     (TIM_DIER_UDE)\r\n#define TIM_DMA_CC1                        (TIM_DIER_CC1DE)\r\n#define TIM_DMA_CC2                        (TIM_DIER_CC2DE)\r\n#define TIM_DMA_CC3                        (TIM_DIER_CC3DE)\r\n#define TIM_DMA_CC4                        (TIM_DIER_CC4DE)\r\n#define TIM_DMA_COM                        (TIM_DIER_COMDE)\r\n#define TIM_DMA_TRIGGER                    (TIM_DIER_TDE)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Event_Source  TIM Event Source \r\n  * @{\r\n  */\r\n#define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG  \r\n#define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G\r\n#define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G\r\n#define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G\r\n#define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G\r\n#define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG\r\n#define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG  \r\n#define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG \r\n#define TIM_EVENTSOURCE_BREAK2              TIM_EGR_B2G   \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Flag_definition  TIM Flag definition\r\n  * @{\r\n  */\r\n#define TIM_FLAG_UPDATE                    (TIM_SR_UIF)\r\n#define TIM_FLAG_CC1                       (TIM_SR_CC1IF)\r\n#define TIM_FLAG_CC2                       (TIM_SR_CC2IF)\r\n#define TIM_FLAG_CC3                       (TIM_SR_CC3IF)\r\n#define TIM_FLAG_CC4                       (TIM_SR_CC4IF)\r\n#define TIM_FLAG_COM                       (TIM_SR_COMIF)\r\n#define TIM_FLAG_TRIGGER                   (TIM_SR_TIF)\r\n#define TIM_FLAG_BREAK                     (TIM_SR_BIF)\r\n#define TIM_FLAG_BREAK2                    (TIM_SR_B2IF)\r\n#define TIM_FLAG_CC1OF                     (TIM_SR_CC1OF)\r\n#define TIM_FLAG_CC2OF                     (TIM_SR_CC2OF)\r\n#define TIM_FLAG_CC3OF                     (TIM_SR_CC3OF)\r\n#define TIM_FLAG_CC4OF                     (TIM_SR_CC4OF)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Clock_Source  TIM Clock Source\r\n  * @{\r\n  */\r\n#define\tTIM_CLOCKSOURCE_ETRMODE2    (TIM_SMCR_ETPS_1) \r\n#define\tTIM_CLOCKSOURCE_INTERNAL    (TIM_SMCR_ETPS_0) \r\n#define\tTIM_CLOCKSOURCE_ITR0        ((uint32_t)0x0000U)\r\n#define\tTIM_CLOCKSOURCE_ITR1        (TIM_SMCR_TS_0)\r\n#define\tTIM_CLOCKSOURCE_ITR2        (TIM_SMCR_TS_1)\r\n#define\tTIM_CLOCKSOURCE_ITR3        (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)\r\n#define\tTIM_CLOCKSOURCE_TI1ED       (TIM_SMCR_TS_2)\r\n#define\tTIM_CLOCKSOURCE_TI1         (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)\r\n#define\tTIM_CLOCKSOURCE_TI2         (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)\r\n#define\tTIM_CLOCKSOURCE_ETRMODE1    (TIM_SMCR_TS)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Clock_Polarity  TIM Clock Polarity\r\n  * @{\r\n  */\r\n#define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED          /*!< Polarity for ETRx clock sources */ \r\n#define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED       /*!< Polarity for ETRx clock sources */ \r\n#define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING   /*!< Polarity for TIx clock sources */ \r\n#define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */ \r\n#define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */ \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Clock_Prescaler  TIM Clock Prescaler\r\n  * @{\r\n  */\r\n#define TIM_CLOCKPRESCALER_DIV1              TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */\r\n#define TIM_CLOCKPRESCALER_DIV2              TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */\r\n#define TIM_CLOCKPRESCALER_DIV4              TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */\r\n#define TIM_CLOCKPRESCALER_DIV8              TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_ClearInput_Polarity  TIM Clear Input Polarity\r\n  * @{\r\n  */\r\n#define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED                    /*!< Polarity for ETRx pin */ \r\n#define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED                 /*!< Polarity for ETRx pin */ \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler\r\n  * @{\r\n  */\r\n#define TIM_CLEARINPUTPRESCALER_DIV1                    TIM_ETRPRESCALER_DIV1      /*!< No prescaler is used */\r\n#define TIM_CLEARINPUTPRESCALER_DIV2                    TIM_ETRPRESCALER_DIV2      /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */\r\n#define TIM_CLEARINPUTPRESCALER_DIV4                    TIM_ETRPRESCALER_DIV4      /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */\r\n#define TIM_CLEARINPUTPRESCALER_DIV8                    TIM_ETRPRESCALER_DIV8        /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state\r\n  * @{\r\n  */  \r\n#define TIM_OSSR_ENABLE \t      (TIM_BDTR_OSSR)\r\n#define TIM_OSSR_DISABLE          ((uint32_t)0x0000U)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state\r\n  * @{\r\n  */\r\n#define TIM_OSSI_ENABLE\t \t    (TIM_BDTR_OSSI)\r\n#define TIM_OSSI_DISABLE            ((uint32_t)0x0000U)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup TIM_Lock_level  TIM Lock level\r\n  * @{\r\n  */\r\n#define TIM_LOCKLEVEL_OFF\t   ((uint32_t)0x0000U)\r\n#define TIM_LOCKLEVEL_1            (TIM_BDTR_LOCK_0)\r\n#define TIM_LOCKLEVEL_2            (TIM_BDTR_LOCK_1)\r\n#define TIM_LOCKLEVEL_3            (TIM_BDTR_LOCK)\r\n/**\r\n  * @}\r\n  */  \r\n/** @defgroup TIM_Break_Input_enable_disable  TIM Break Input State\r\n  * @{\r\n  */                         \r\n#define TIM_BREAK_ENABLE          (TIM_BDTR_BKE)\r\n#define TIM_BREAK_DISABLE         ((uint32_t)0x0000U)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup TIM_Break_Polarity  TIM Break Polarity \r\n  * @{\r\n  */\r\n#define TIM_BREAKPOLARITY_LOW        ((uint32_t)0x0000U)\r\n#define TIM_BREAKPOLARITY_HIGH       (TIM_BDTR_BKP)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup TIM_AOE_Bit_Set_Reset  TIM AOE Bit State\r\n  * @{\r\n  */\r\n#define TIM_AUTOMATICOUTPUT_ENABLE           (TIM_BDTR_AOE)\r\n#define\tTIM_AUTOMATICOUTPUT_DISABLE          ((uint32_t)0x0000U)\r\n/**\r\n  * @}\r\n  */  \r\n  \r\n/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection\r\n  * @{\r\n  */  \r\n#define\tTIM_TRGO_RESET            ((uint32_t)0x0000U)             \r\n#define\tTIM_TRGO_ENABLE           (TIM_CR2_MMS_0)           \r\n#define\tTIM_TRGO_UPDATE           (TIM_CR2_MMS_1)             \r\n#define\tTIM_TRGO_OC1              ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))    \r\n#define\tTIM_TRGO_OC1REF           (TIM_CR2_MMS_2)           \r\n#define\tTIM_TRGO_OC2REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))          \r\n#define\tTIM_TRGO_OC3REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))           \r\n#define\tTIM_TRGO_OC4REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))   \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup TIM_Master_Slave_Mode  TIM Master Slave Mode\r\n  * @{\r\n  */\r\n#define TIM_MASTERSLAVEMODE_ENABLE          ((uint32_t)0x0080)\r\n#define TIM_MASTERSLAVEMODE_DISABLE         ((uint32_t)0x0000U)\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/** @defgroup TIM_Trigger_Selection  TIM Trigger Selection\r\n  * @{\r\n  */\r\n#define TIM_TS_ITR0                        ((uint32_t)0x0000U)\r\n#define TIM_TS_ITR1                        ((uint32_t)0x0010U)\r\n#define TIM_TS_ITR2                        ((uint32_t)0x0020U)\r\n#define TIM_TS_ITR3                        ((uint32_t)0x0030U)\r\n#define TIM_TS_TI1F_ED                     ((uint32_t)0x0040U)\r\n#define TIM_TS_TI1FP1                      ((uint32_t)0x0050U)\r\n#define TIM_TS_TI2FP2                      ((uint32_t)0x0060U)\r\n#define TIM_TS_ETRF                        ((uint32_t)0x0070U)\r\n#define TIM_TS_NONE                        ((uint32_t)0xFFFFU)\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity\r\n  * @{\r\n  */\r\n#define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx trigger sources */ \r\n#define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx trigger sources */ \r\n#define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */ \r\n#define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */ \r\n#define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */ \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler\r\n  * @{\r\n  */\r\n#define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */\r\n#define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */\r\n#define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */\r\n#define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup TIM_TI1_Selection TIM TI1 Selection\r\n  * @{\r\n  */\r\n#define TIM_TI1SELECTION_CH1                ((uint32_t)0x0000U)\r\n#define TIM_TI1SELECTION_XORCOMBINATION     (TIM_CR2_TI1S)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup TIM_DMA_Base_address  TIM DMA Base address\r\n  * @{\r\n  */\r\n#define TIM_DMABASE_CR1                    (0x00000000U)\r\n#define TIM_DMABASE_CR2                    (0x00000001U)\r\n#define TIM_DMABASE_SMCR                   (0x00000002U)\r\n#define TIM_DMABASE_DIER                   (0x00000003U)\r\n#define TIM_DMABASE_SR                     (0x00000004U)\r\n#define TIM_DMABASE_EGR                    (0x00000005U)\r\n#define TIM_DMABASE_CCMR1                  (0x00000006U)\r\n#define TIM_DMABASE_CCMR2                  (0x00000007U)\r\n#define TIM_DMABASE_CCER                   (0x00000008U)\r\n#define TIM_DMABASE_CNT                    (0x00000009U)\r\n#define TIM_DMABASE_PSC                    (0x0000000AU)\r\n#define TIM_DMABASE_ARR                    (0x0000000BU)\r\n#define TIM_DMABASE_RCR                    (0x0000000CU)\r\n#define TIM_DMABASE_CCR1                   (0x0000000DU)\r\n#define TIM_DMABASE_CCR2                   (0x0000000EU)\r\n#define TIM_DMABASE_CCR3                   (0x0000000FU)\r\n#define TIM_DMABASE_CCR4                   (0x00000010U)\r\n#define TIM_DMABASE_BDTR                   (0x00000011U)\r\n#define TIM_DMABASE_DCR                    (0x00000012U)\r\n#define TIM_DMABASE_OR                     (0x00000013U)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup TIM_DMA_Burst_Length  TIM DMA Burst Length \r\n  * @{\r\n  */\r\n#define TIM_DMABURSTLENGTH_1TRANSFER           (0x00000000U)\r\n#define TIM_DMABURSTLENGTH_2TRANSFERS          (0x00000100U)\r\n#define TIM_DMABURSTLENGTH_3TRANSFERS          (0x00000200U)\r\n#define TIM_DMABURSTLENGTH_4TRANSFERS          (0x00000300U)\r\n#define TIM_DMABURSTLENGTH_5TRANSFERS          (0x00000400U)\r\n#define TIM_DMABURSTLENGTH_6TRANSFERS          (0x00000500U)\r\n#define TIM_DMABURSTLENGTH_7TRANSFERS          (0x00000600U)\r\n#define TIM_DMABURSTLENGTH_8TRANSFERS          (0x00000700U)\r\n#define TIM_DMABURSTLENGTH_9TRANSFERS          (0x00000800U)\r\n#define TIM_DMABURSTLENGTH_10TRANSFERS         (0x00000900U)\r\n#define TIM_DMABURSTLENGTH_11TRANSFERS         (0x00000A00U)\r\n#define TIM_DMABURSTLENGTH_12TRANSFERS         (0x00000B00U)\r\n#define TIM_DMABURSTLENGTH_13TRANSFERS         (0x00000C00U)\r\n#define TIM_DMABURSTLENGTH_14TRANSFERS         (0x00000D00U)\r\n#define TIM_DMABURSTLENGTH_15TRANSFERS         (0x00000E00U)\r\n#define TIM_DMABURSTLENGTH_16TRANSFERS         (0x00000F00U)\r\n#define TIM_DMABURSTLENGTH_17TRANSFERS         (0x00001000U)\r\n#define TIM_DMABURSTLENGTH_18TRANSFERS         (0x00001100U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DMA_Handle_index  DMA Handle index\r\n  * @{\r\n  */\r\n#define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0U)       /*!< Index of the DMA handle used for Update DMA requests */\r\n#define TIM_DMA_ID_CC1                   ((uint16_t) 0x1U)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */\r\n#define TIM_DMA_ID_CC2                   ((uint16_t) 0x2U)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */\r\n#define TIM_DMA_ID_CC3                   ((uint16_t) 0x3U)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */\r\n#define TIM_DMA_ID_CC4                   ((uint16_t) 0x4U)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */\r\n#define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x5U)       /*!< Index of the DMA handle used for Commutation DMA requests */\r\n#define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x6U)       /*!< Index of the DMA handle used for Trigger DMA requests */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup Channel_CC_State  Channel CC State\r\n  * @{\r\n  */\r\n#define TIM_CCx_ENABLE                   ((uint32_t)0x0001U)\r\n#define TIM_CCx_DISABLE                  ((uint32_t)0x0000U)\r\n#define TIM_CCxN_ENABLE                  ((uint32_t)0x0004U)\r\n#define TIM_CCxN_DISABLE                 ((uint32_t)0x0000U)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */   \r\n  \r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup TIM_Exported_Macros TIM Exported Macros\r\n  * @{\r\n  */\r\n/** @brief Reset TIM handle state\r\n  * @param  __HANDLE__: TIM handle\r\n  * @retval None\r\n  */\r\n#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)\r\n\r\n/**\r\n  * @brief  Enable the TIM peripheral.\r\n  * @param  __HANDLE__: TIM handle\r\n  * @retval None\r\n */\r\n#define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))\r\n\r\n/**\r\n  * @brief  Enable the TIM update source request.\r\n  * @param  __HANDLE__: TIM handle\r\n  * @retval None\r\n */\r\n#define __HAL_TIM_URS_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->CR1|=(TIM_CR1_URS))\r\n\r\n/**\r\n  * @brief  Enable the TIM main Output.\r\n  * @param  __HANDLE__: TIM handle\r\n  * @retval None\r\n  */\r\n#define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))\r\n\r\n\r\n/* The counter of a timer instance is disabled only if all the CCx and CCxN\r\n   channels have been disabled */\r\n#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))\r\n#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))\r\n\r\n/**\r\n  * @brief  Disable the TIM peripheral.\r\n  * @param  __HANDLE__: TIM handle\r\n  * @retval None\r\n  */\r\n#define __HAL_TIM_DISABLE(__HANDLE__) \\\r\n                        do { \\\r\n                          if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \\\r\n                          { \\\r\n                            if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \\\r\n                            { \\\r\n                              (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \\\r\n                            } \\\r\n                          } \\\r\n                        } while(0)\r\n                        \r\n/**\r\n  * @brief  Disable the TIM update source request.\r\n  * @param  __HANDLE__: TIM handle\r\n  * @retval None\r\n */\r\n#define __HAL_TIM_URS_DISABLE(__HANDLE__)            ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))\r\n\r\n\r\n/* The Main Output of a timer instance is disabled only if all the CCx and CCxN\r\n   channels have been disabled */\r\n/**\r\n  * @brief  Disable the TIM main Output.\r\n  * @param  __HANDLE__: TIM handle\r\n  * @retval None\r\n  */\r\n#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \\\r\n                        do { \\\r\n                          if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \\\r\n                          { \\\r\n                            if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \\\r\n                            { \\\r\n                              (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \\\r\n                            } \\\r\n                          } \\\r\n                        } while(0)\r\n\r\n#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))\r\n#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))\r\n#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))\r\n#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))\r\n#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))\r\n#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))\r\n\r\n#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\r\n#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))\r\n\r\n#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)            (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))\r\n#define __HAL_TIM_SET_PRESCALER (__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))\r\n\r\n#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \\\r\n(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\\\r\n ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\\\r\n ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\\\r\n ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))\r\n\r\n#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \\\r\n(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\\\r\n ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\\\r\n ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\\\r\n ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))\r\n\r\n#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \\\r\n(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\\\r\n ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\\\r\n ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\\\r\n ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))\r\n\r\n#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \\\r\n(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\\\r\n ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\\\r\n ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\\\r\n ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))\r\n \r\n/**\r\n  * @brief  Sets the TIM Counter Register value on runtime.\r\n  * @param  __HANDLE__: TIM handle.\r\n  * @param  __COUNTER__: specifies the Counter register new value.\r\n  * @retval None\r\n  */\r\n#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))\r\n\r\n/**\r\n  * @brief  Gets the TIM Counter Register value on runtime.\r\n  * @param  __HANDLE__: TIM handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)\r\n\r\n/**\r\n  * @brief  Sets the TIM Autoreload Register value on runtime without calling \r\n  *         another time any Init function.\r\n  * @param  __HANDLE__: TIM handle.\r\n  * @param  __AUTORELOAD__: specifies the Counter register new value.\r\n  * @retval None\r\n  */\r\n#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__)                  \\\r\n                        do{                                                  \\\r\n                            (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \\\r\n                            (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \\\r\n                          } while(0)\r\n/**\r\n  * @brief  Gets the TIM Autoreload Register value on runtime\r\n  * @param  __HANDLE__: TIM handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)\r\n\r\n/**\r\n  * @brief  Sets the TIM Clock Division value on runtime without calling \r\n  *         another time any Init function. \r\n  * @param  __HANDLE__: TIM handle.\r\n  * @param  __CKD__: specifies the clock division value.\r\n  *          This parameter can be one of the following value:\r\n  *            @arg TIM_CLOCKDIVISION_DIV1\r\n  *            @arg TIM_CLOCKDIVISION_DIV2\r\n  *            @arg TIM_CLOCKDIVISION_DIV4\r\n  * @retval None\r\n  */\r\n#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \\\r\n                        do{                                                             \\\r\n                              (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD);  \\\r\n                              (__HANDLE__)->Instance->CR1 |= (__CKD__);                 \\\r\n                              (__HANDLE__)->Init.ClockDivision = (__CKD__);             \\\r\n                          } while(0)\r\n/**\r\n  * @brief  Gets the TIM Clock Division value on runtime\r\n  * @param  __HANDLE__: TIM handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)\r\n\r\n/**\r\n  * @brief  Sets the TIM Input Capture prescaler on runtime without calling \r\n  *         another time HAL_TIM_IC_ConfigChannel() function.\r\n  * @param  __HANDLE__: TIM handle.\r\n  * @param  __CHANNEL__ : TIM Channels to be configured.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @param  __ICPSC__: specifies the Input Capture4 prescaler new value.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_ICPSC_DIV1: no prescaler\r\n  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r\n  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r\n  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r\n  * @retval None\r\n  */\r\n#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \\\r\n                        do{                                                    \\\r\n                              TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \\\r\n                              TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \\\r\n                          } while(0)\r\n\r\n/**\r\n  * @brief  Gets the TIM Input Capture prescaler on runtime\r\n  * @param  __HANDLE__: TIM handle.\r\n  * @param  __CHANNEL__ : TIM Channels to be configured.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value\r\n  *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value\r\n  *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value\r\n  *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value\r\n  * @retval None\r\n  */\r\n#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \\\r\n  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\\\r\n   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\\\r\n   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\\\r\n   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)\r\n  \r\n/**\r\n  * @brief  Sets the TIM Capture x input polarity on runtime.\r\n  * @param  __HANDLE__: TIM handle.\r\n  * @param  __CHANNEL__: TIM Channels to be configured.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @param  __POLARITY__: Polarity for TIx source   \r\n  *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge\r\n  *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge\r\n  *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge\r\n  * @note  The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized  for TIM Channel 4.     \r\n  * @retval None\r\n  */\r\n#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)                          \\\r\n                       do{                                                                            \\\r\n                           TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \\\r\n                           TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \\\r\n                         }while(0)\r\n\t\t\t\t\t\t\t\t\t\t\t \r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Include TIM HAL Extension module */\r\n#include \"stm32f7xx_hal_tim_ex.h\"\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup TIM_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup TIM_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n\r\n/* Time Base functions ********************************************************/\r\nHAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);\r\nHAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);\r\nvoid HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);\r\nvoid HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);\r\n/* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);\r\nHAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);\r\nHAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);\r\n/* Non-Blocking mode: DMA */\r\nHAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);\r\nHAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup TIM_Exported_Functions_Group2\r\n  * @{\r\n  */\r\n/* Timer Output Compare functions **********************************************/\r\nHAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);\r\nHAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);\r\nvoid HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);\r\nvoid HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);\r\n/* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r\n/* Non-Blocking mode: DMA */\r\nHAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r\nHAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup TIM_Exported_Functions_Group3\r\n  * @{\r\n  */\r\n/* Timer PWM functions *********************************************************/\r\nHAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);\r\nHAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);\r\nvoid HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);\r\nvoid HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);\r\n/* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r\n/* Non-Blocking mode: DMA */\r\nHAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r\nHAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup TIM_Exported_Functions_Group4\r\n  * @{\r\n  */\r\n/* Timer Input Capture functions ***********************************************/\r\nHAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);\r\nHAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);\r\nvoid HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);\r\nvoid HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);\r\n/* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r\n/* Non-Blocking mode: DMA */\r\nHAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r\nHAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup TIM_Exported_Functions_Group5\r\n  * @{\r\n  */\r\n/* Timer One Pulse functions ***************************************************/\r\nHAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);\r\nHAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);\r\nvoid HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);\r\nvoid HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);\r\n/* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r\nHAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r\n\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r\nHAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup TIM_Exported_Functions_Group6\r\n  * @{\r\n  */\r\n/* Timer Encoder functions *****************************************************/\r\nHAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig);\r\nHAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);\r\nvoid HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);\r\nvoid HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);\r\n /* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\r\n/* Non-Blocking mode: DMA */\r\nHAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);\r\nHAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup TIM_Exported_Functions_Group7\r\n  * @{\r\n  */\r\n/* Interrupt Handler functions  **********************************************/\r\nvoid HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup TIM_Exported_Functions_Group8\r\n  * @{\r\n  */\r\n/* Control functions  *********************************************************/\r\nHAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel,  uint32_t InputChannel);\r\nHAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);    \r\nHAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);\r\nHAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);\r\nHAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);\r\nHAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \\\r\n                                              uint32_t  *BurstBuffer, uint32_t  BurstLength);\r\nHAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);\r\nHAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \\\r\n                                              uint32_t  *BurstBuffer, uint32_t  BurstLength);\r\nHAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);\r\nHAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);\r\nuint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup TIM_Exported_Functions_Group9\r\n  * @{\r\n  */\r\n/* Callback in non blocking modes (Interrupt and DMA) *************************/\r\nvoid HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);\r\nvoid HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);\r\nvoid HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);\r\nvoid HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);\r\nvoid HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);\r\nvoid HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup TIM_Exported_Functions_Group10\r\n  * @{\r\n  */\r\n/* Peripheral State functions  **************************************************/\r\nHAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);\r\nHAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);\r\nHAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);\r\nHAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);\r\nHAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);\r\nHAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup TIM_Private_Macros TIM Private Macros\r\n  * @{\r\n  */\r\n\r\n/** @defgroup TIM_IS_TIM_Definitions TIM Private macros to check input parameters\r\n  * @{\r\n  */\r\n#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP)              || \\\r\n                                       ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \\\r\n                                       ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \\\r\n                                       ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \\\r\n                                       ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))\r\n\r\n#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \\\r\n                                           ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \\\r\n                                           ((__DIV__) == TIM_CLOCKDIVISION_DIV4))\r\n\r\n#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \\\r\n                                      ((__STATE__) == TIM_OCFAST_ENABLE))\r\n\r\n#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \\\r\n                                    ((STATE) == TIM_OUTPUTSTATE_ENABLE))\r\n\r\n#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \\\r\n                                     ((STATE) == TIM_OUTPUTNSTATE_ENABLE))\r\n\r\n#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \\\r\n                                          ((__POLARITY__) == TIM_OCPOLARITY_LOW))\r\n\r\n#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \\\r\n                                           ((__POLARITY__) == TIM_OCNPOLARITY_LOW))\r\n\r\n#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \\\r\n                                        ((__STATE__) == TIM_OCIDLESTATE_RESET))\r\n\r\n#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \\\r\n                                         ((__STATE__) == TIM_OCNIDLESTATE_RESET))\r\n\r\n#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \\\r\n                                          ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \\\r\n                                          ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))\r\n\r\n#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \\\r\n                                            ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \\\r\n                                            ((__SELECTION__) == TIM_ICSELECTION_TRC))\r\n\r\n#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \\\r\n                                            ((__PRESCALER__) == TIM_ICPSC_DIV2) || \\\r\n                                            ((__PRESCALER__) == TIM_ICPSC_DIV4) || \\\r\n                                            ((__PRESCALER__) == TIM_ICPSC_DIV8))\r\n\r\n#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \\\r\n                                   ((__MODE__) == TIM_OPMODE_REPETITIVE))\r\n\r\n#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \\\r\n                                       ((__MODE__) == TIM_ENCODERMODE_TI2) || \\\r\n                                       ((__MODE__) == TIM_ENCODERMODE_TI12))   \r\n\r\n#define IS_TIM_IT(__IT__) ((((__IT__) & 0xFFFFFF00U) == 0x00000000U) && ((__IT__) != 0x00000000U))\r\n\r\n\r\n#define IS_TIM_GET_IT(__IT__) (((__IT__) == TIM_IT_UPDATE)  || \\\r\n                               ((__IT__) == TIM_IT_CC1)     || \\\r\n                               ((__IT__) == TIM_IT_CC2)     || \\\r\n                               ((__IT__) == TIM_IT_CC3)     || \\\r\n                               ((__IT__) == TIM_IT_CC4)     || \\\r\n                               ((__IT__) == TIM_IT_COM)     || \\\r\n                               ((__IT__) == TIM_IT_TRIGGER) || \\\r\n                               ((__IT__) == TIM_IT_BREAK))\r\n\r\n#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))\r\n\r\n#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))\r\n\r\n#define IS_TIM_FLAG(__FLAG__) (((__FLAG__) == TIM_FLAG_UPDATE) || \\\r\n                               ((__FLAG__) == TIM_FLAG_CC1)     || \\\r\n                               ((__FLAG__) == TIM_FLAG_CC2)     || \\\r\n                               ((__FLAG__) == TIM_FLAG_CC3)     || \\\r\n                               ((__FLAG__) == TIM_FLAG_CC4)     || \\\r\n                               ((__FLAG__) == TIM_FLAG_COM)     || \\\r\n                               ((__FLAG__) == TIM_FLAG_TRIGGER) || \\\r\n                               ((__FLAG__) == TIM_FLAG_BREAK)   || \\\r\n                               ((__FLAG__) == TIM_FLAG_BREAK2)  || \\\r\n                               ((__FLAG__) == TIM_FLAG_CC1OF)   || \\\r\n                               ((__FLAG__) == TIM_FLAG_CC2OF)   || \\\r\n                               ((__FLAG__) == TIM_FLAG_CC3OF)   || \\\r\n                               ((__FLAG__) == TIM_FLAG_CC4OF))\r\n\r\n#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \\\r\n                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \\\r\n                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \\\r\n                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \\\r\n                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \\\r\n                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \\\r\n                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \\\r\n                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \\\r\n                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \\\r\n                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))\r\n\r\n#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \\\r\n                                        ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \\\r\n                                        ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \\\r\n                                        ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \\\r\n                                        ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))\r\n\r\n#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \\\r\n                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \\\r\n                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \\\r\n                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) \r\n\r\n#define IS_TIM_CLOCKFILTER(__ICFILTER__)      ((__ICFILTER__) <= 0xF) \r\n\r\n#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \\\r\n                                                    ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))\r\n\r\n#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__)   (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \\\r\n                                                 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \\\r\n                                                 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \\\r\n                                                 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))\r\n\r\n#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) \r\n\r\n#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \\\r\n                                      ((__STATE__) == TIM_OSSR_DISABLE))\r\n\r\n#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \\\r\n                                      ((__STATE__) == TIM_OSSI_DISABLE))\r\n\r\n#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \\\r\n                                      ((__LEVEL__) == TIM_LOCKLEVEL_1) || \\\r\n                                      ((__LEVEL__) == TIM_LOCKLEVEL_2) || \\\r\n                                      ((__LEVEL__) == TIM_LOCKLEVEL_3)) \r\n\r\n#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \\\r\n                                       ((__STATE__) == TIM_BREAK_DISABLE))\r\n\r\n#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \\\r\n                                             ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))\r\n\r\n#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \\\r\n                                                  ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))\r\n\r\n#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \\\r\n                                        ((__SOURCE__) == TIM_TRGO_ENABLE) || \\\r\n                                        ((__SOURCE__) == TIM_TRGO_UPDATE) || \\\r\n                                        ((__SOURCE__) == TIM_TRGO_OC1) || \\\r\n                                        ((__SOURCE__) == TIM_TRGO_OC1REF) || \\\r\n                                        ((__SOURCE__) == TIM_TRGO_OC2REF) || \\\r\n                                        ((__SOURCE__) == TIM_TRGO_OC3REF) || \\\r\n                                        ((__SOURCE__) == TIM_TRGO_OC4REF))\r\n\r\n#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \\\r\n                                     ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))\r\n\r\n#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \\\r\n                                                 ((__SELECTION__) == TIM_TS_ITR1) || \\\r\n                                                 ((__SELECTION__) == TIM_TS_ITR2) || \\\r\n                                                 ((__SELECTION__) == TIM_TS_ITR3) || \\\r\n                                                 ((__SELECTION__) == TIM_TS_TI1F_ED) || \\\r\n                                                 ((__SELECTION__) == TIM_TS_TI1FP1) || \\\r\n                                                 ((__SELECTION__) == TIM_TS_TI2FP2) || \\\r\n                                                 ((__SELECTION__) == TIM_TS_ETRF))\r\n\r\n#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\\r\n                                                      ((SELECTION) == TIM_TS_ITR1) || \\\r\n                                                      ((SELECTION) == TIM_TS_ITR2) || \\\r\n                                                      ((SELECTION) == TIM_TS_ITR3))\r\n\r\n#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \\\r\n                                                               ((__SELECTION__) == TIM_TS_ITR1) || \\\r\n                                                               ((__SELECTION__) == TIM_TS_ITR2) || \\\r\n                                                               ((__SELECTION__) == TIM_TS_ITR3) || \\\r\n                                                               ((__SELECTION__) == TIM_TS_NONE))\r\n\r\n#define IS_TIM_TRIGGERPOLARITY(__POLARITY__)     (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \\\r\n                                                  ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \\\r\n                                                  ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \\\r\n                                                  ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \\\r\n                                                  ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))\r\n\r\n#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__)  (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \\\r\n                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \\\r\n                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \\\r\n                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) \r\n\r\n#define IS_TIM_TRIGGERFILTER(__ICFILTER__)     ((__ICFILTER__) <= 0xF) \r\n\r\n#define IS_TIM_TI1SELECTION(__TI1SELECTION__)   (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \\\r\n                                                 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))\r\n\r\n#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_CR2) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_SMCR) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_DIER) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_SR) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_EGR) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_CCMR1) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_CCMR2) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_CCER) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_CNT) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_PSC) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_ARR) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_RCR) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_CCR1) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_CCR2) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_CCR3) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_CCR4) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_BDTR) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_DCR) || \\\r\n                                   ((__BASE__) == TIM_DMABASE_OR))\r\n\r\n#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \\\r\n                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \\\r\n                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \\\r\n                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \\\r\n                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \\\r\n                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \\\r\n                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \\\r\n                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \\\r\n                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \\\r\n                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \\\r\n                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \\\r\n                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \\\r\n                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \\\r\n                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \\\r\n                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \\\r\n                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \\\r\n                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \\\r\n                                       ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))\r\n\r\n#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) \r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup TIM_Private_Functions TIM Private Functions\r\n  * @{\r\n  */\r\nvoid TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);\r\nvoid TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);\r\nvoid TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r\nvoid TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r\nvoid TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r\nvoid TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r\nvoid TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);\r\n\r\nvoid HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);\r\nvoid HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);\r\nvoid HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);\r\nvoid TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);\r\n/**\r\n  * @}\r\n  */ \r\n     \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_TIM_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_tim_ex.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of TIM HAL Extension module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_TIM_EX_H\r\n#define __STM32F7xx_HAL_TIM_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup TIMEx\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/ \r\n/** @defgroup TIMEx_Exported_Types TIM Exported Types\r\n  * @{\r\n  */\r\n  \r\n/** \r\n  * @brief  TIM Hall sensor Configuration Structure definition  \r\n  */\r\n\r\ntypedef struct\r\n{\r\n                                  \r\n  uint32_t IC1Polarity;            /*!< Specifies the active edge of the input signal.\r\n                                        This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r\n                                                                   \r\n  uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.\r\n                                     This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r\n                                  \r\n  uint32_t IC1Filter;           /*!< Specifies the input capture filter.\r\n                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */  \r\n  uint32_t Commutation_Delay;  /*!< Specifies the pulse value to be loaded into the Capture Compare Register. \r\n                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */                              \r\n} TIM_HallSensor_InitTypeDef;\r\n\r\n/** \r\n  * @brief  TIM Master configuration Structure definition  \r\n  */ \r\ntypedef struct {\r\n  uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection. \r\n                                      This parameter can be a value of @ref TIM_Master_Mode_Selection */ \r\n  uint32_t  MasterOutputTrigger2;  /*!< Trigger output2 (TRGO2) selection \r\n                                      This parameter can be a value of @ref TIMEx_Master_Mode_Selection_2 */\r\n  uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection. \r\n                                      This parameter can be a value of @ref TIM_Master_Slave_Mode */\r\n}TIM_MasterConfigTypeDef;\r\n\r\n/** \r\n  * @brief  TIM Break input(s) and Dead time configuration Structure definition  \r\n  * @note   2 break inputs can be configured (BKIN and BKIN2) with configurable \r\n  *        filter and polarity.\r\n  */ \r\ntypedef struct\r\n{\r\n  uint32_t OffStateRunMode;\t    /*!< TIM off state in run mode.\r\n                                       This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */\r\n  uint32_t OffStateIDLEMode;\t    /*!< TIM off state in IDLE mode.\r\n                                       This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */\r\n  uint32_t LockLevel;\t \t        /*!< TIM Lock level.\r\n                                       This parameter can be a value of @ref TIM_Lock_level */                             \r\n  uint32_t DeadTime;\t \t        /*!< TIM dead Time.\r\n                                       This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */\r\n  uint32_t BreakState;\t \t        /*!< TIM Break State.\r\n                                       This parameter can be a value of @ref TIM_Break_Input_enable_disable */\r\n  uint32_t BreakPolarity;           /*!< TIM Break input polarity.\r\n                                       This parameter can be a value of @ref TIM_Break_Polarity */\r\n  uint32_t BreakFilter;             /*!< Specifies the break input filter.\r\n                                       This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */  \r\n  uint32_t Break2State;\t \t        /*!< TIM Break2 State \r\n                                       This parameter can be a value of @ref TIMEx_Break2_Input_enable_disable */\r\n  uint32_t Break2Polarity;          /*!< TIM Break2 input polarity \r\n                                       This parameter can be a value of @ref TIMEx_Break2_Polarity */\r\n  uint32_t Break2Filter;            /*!< TIM break2 input filter.\r\n                                       This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */  \r\n  uint32_t AutomaticOutput;         /*!< TIM Automatic Output Enable state \r\n                                       This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */           \r\n} TIM_BreakDeadTimeConfigTypeDef;\r\n\r\n#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r\n/** \r\n  * @brief  TIM Break/Break2 input configuration   \r\n  */\r\ntypedef struct {\r\n  uint32_t Source;         /*!< Specifies the source of the timer break input.\r\n                                This parameter can be a value of @ref TIMEx_Break_Input_Source */\r\n  uint32_t Enable;         /*!< Specifies whether or not the break input source is enabled.\r\n                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */\r\n} TIMEx_BreakInputConfigTypeDef;\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n/**\r\n  * @}\r\n  */  \r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup TIMEx_Exported_Constants  TIMEx Exported Constants\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup TIMEx_Channel TIMEx Channel\r\n  * @{\r\n  */\r\n\r\n#define TIM_CHANNEL_1                      ((uint32_t)0x0000U)\r\n#define TIM_CHANNEL_2                      ((uint32_t)0x0004U)\r\n#define TIM_CHANNEL_3                      ((uint32_t)0x0008U)\r\n#define TIM_CHANNEL_4                      ((uint32_t)0x000CU)\r\n#define TIM_CHANNEL_5                      ((uint32_t)0x0010U)\r\n#define TIM_CHANNEL_6                      ((uint32_t)0x0014U)\r\n#define TIM_CHANNEL_ALL                    ((uint32_t)0x003CU)\r\n                                 \r\n/**\r\n  * @}\r\n  */ \r\n    \r\n/** @defgroup TIMEx_Output_Compare_and_PWM_modes TIMEx Output Compare and PWM Modes\r\n  * @{\r\n  */\r\n#define TIM_OCMODE_TIMING                   ((uint32_t)0x0000U)\r\n#define TIM_OCMODE_ACTIVE                   ((uint32_t)TIM_CCMR1_OC1M_0)\r\n#define TIM_OCMODE_INACTIVE                 ((uint32_t)TIM_CCMR1_OC1M_1)\r\n#define TIM_OCMODE_TOGGLE                   ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)\r\n#define TIM_OCMODE_PWM1                     ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)\r\n#define TIM_OCMODE_PWM2                     ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)\r\n#define TIM_OCMODE_FORCED_ACTIVE            ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)\r\n#define TIM_OCMODE_FORCED_INACTIVE          ((uint32_t)TIM_CCMR1_OC1M_2)\r\n\r\n#define TIM_OCMODE_RETRIGERRABLE_OPM1      ((uint32_t)TIM_CCMR1_OC1M_3)\r\n#define TIM_OCMODE_RETRIGERRABLE_OPM2      ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)\r\n#define TIM_OCMODE_COMBINED_PWM1           ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)\r\n#define TIM_OCMODE_COMBINED_PWM2           ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)\r\n#define TIM_OCMODE_ASSYMETRIC_PWM1         ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)\r\n#define TIM_OCMODE_ASSYMETRIC_PWM2         ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)\r\n/**\r\n  * @}\r\n  */\r\n      \r\n/** @defgroup TIMEx_Remap  TIMEx Remap\r\n  * @{\r\n  */\r\n#define TIM_TIM2_TIM8_TRGO                     (0x00000000U)\r\n#define TIM_TIM2_ETH_PTP                       (0x00000400U)\r\n#define TIM_TIM2_USBFS_SOF                     (0x00000800U)\r\n#define TIM_TIM2_USBHS_SOF                     (0x00000C00U)\r\n#define TIM_TIM5_GPIO                          (0x00000000U)\r\n#define TIM_TIM5_LSI                           (0x00000040U)\r\n#define TIM_TIM5_LSE                           (0x00000080U)\r\n#define TIM_TIM5_RTC                           (0x000000C0U)\r\n#define TIM_TIM11_GPIO                         (0x00000000U)\r\n#define TIM_TIM11_SPDIFRX                      (0x00000001U)\r\n#define TIM_TIM11_HSE                          (0x00000002U)\r\n#define TIM_TIM11_MCO1                         (0x00000003U)\r\n/**\r\n  * @}\r\n  */\t\r\n\r\n/** @defgroup TIMEx_ClearInput_Source TIMEx Clear Input Source\r\n  * @{\r\n  */\r\n#define TIM_CLEARINPUTSOURCE_ETR            ((uint32_t)0x0001U) \r\n#define TIM_CLEARINPUTSOURCE_OCREFCLR       ((uint32_t)0x0002U) \r\n#define TIM_CLEARINPUTSOURCE_NONE           ((uint32_t)0x0000U)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup TIMEx_Break2_Input_enable_disable  TIMEx Break input 2 Enable\r\n  * @{\r\n  */                         \r\n#define TIM_BREAK2_DISABLE         ((uint32_t)0x00000000U)\r\n#define TIM_BREAK2_ENABLE          ((uint32_t)TIM_BDTR_BK2E)\r\n/**\r\n  * @}\r\n  */\r\n    \r\n/** @defgroup TIMEx_Break2_Polarity TIMEx Break2 Polarity\r\n  * @{\r\n  */\r\n#define TIM_BREAK2POLARITY_LOW        ((uint32_t)0x00000000U)\r\n#define TIM_BREAK2POLARITY_HIGH       (TIM_BDTR_BK2P)\r\n/**\r\n  * @}\r\n  */\r\n \r\n/** @defgroup TIMEx_Group_Channel5 TIMEx Group Channel 5 and Channel 1, 2 or 3\r\n  * @{\r\n  */\r\n#define TIM_GROUPCH5_NONE       ((uint32_t)0x00000000U)  /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */\r\n#define TIM_GROUPCH5_OC1REFC    (TIM_CCR5_GC5C1)      /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */\r\n#define TIM_GROUPCH5_OC2REFC    (TIM_CCR5_GC5C2)      /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */\r\n#define TIM_GROUPCH5_OC3REFC    (TIM_CCR5_GC5C3)       /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */\r\n/**\r\n  * @}\r\n  */\r\n\t\r\n/** @defgroup TIMEx_Master_Mode_Selection_2 TIMEx Master Mode Selection 2 (TRGO2)\r\n  * @{\r\n  */  \r\n#define\tTIM_TRGO2_RESET                          ((uint32_t)0x00000000U)             \r\n#define\tTIM_TRGO2_ENABLE                         ((uint32_t)(TIM_CR2_MMS2_0))          \r\n#define\tTIM_TRGO2_UPDATE                         ((uint32_t)(TIM_CR2_MMS2_1))\r\n#define\tTIM_TRGO2_OC1                            ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))   \r\n#define\tTIM_TRGO2_OC1REF                         ((uint32_t)(TIM_CR2_MMS2_2))           \r\n#define\tTIM_TRGO2_OC2REF                         ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))          \r\n#define\tTIM_TRGO2_OC3REF                         ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))           \r\n#define\tTIM_TRGO2_OC4REF                         ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))  \r\n#define\tTIM_TRGO2_OC5REF                         ((uint32_t)(TIM_CR2_MMS2_3))   \r\n#define\tTIM_TRGO2_OC6REF                         ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))   \r\n#define\tTIM_TRGO2_OC4REF_RISINGFALLING           ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))   \r\n#define\tTIM_TRGO2_OC6REF_RISINGFALLING           ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))   \r\n#define\tTIM_TRGO2_OC4REF_RISING_OC6REF_RISING    ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))   \r\n#define\tTIM_TRGO2_OC4REF_RISING_OC6REF_FALLING   ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))   \r\n#define\tTIM_TRGO2_OC5REF_RISING_OC6REF_RISING    ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))   \r\n#define\tTIM_TRGO2_OC5REF_RISING_OC6REF_FALLING   ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))   \r\n/**\r\n  * @}\r\n  */ \r\n    \r\n/** @defgroup TIMEx_Slave_Mode TIMEx Slave mode\r\n  * @{\r\n  */\r\n#define TIM_SLAVEMODE_DISABLE                ((uint32_t)0x0000U)\r\n#define TIM_SLAVEMODE_RESET                  ((uint32_t)(TIM_SMCR_SMS_2))\r\n#define TIM_SLAVEMODE_GATED                  ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))\r\n#define TIM_SLAVEMODE_TRIGGER                ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))\r\n#define TIM_SLAVEMODE_EXTERNAL1              ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))\r\n#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER  ((uint32_t)(TIM_SMCR_SMS_3))\r\n/**\r\n  * @}\r\n  */\r\n#if defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r\n/** @defgroup TIMEx_Break_Input TIM  Extended Break input\r\n  * @{\r\n  */\r\n#define TIM_BREAKINPUT_BRK     ((uint32_t)0x00000001U) /* !< Timer break input  */\r\n#define TIM_BREAKINPUT_BRK2    ((uint32_t)0x00000002U) /* !< Timer break2 input */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIMEx_Break_Input_Source TIM  Extended Break input source\r\n  * @{\r\n  */\r\n#define TIM_BREAKINPUTSOURCE_BKIN     ((uint32_t)0x00000001U) /* !< An external source (GPIO) is connected to the BKIN pin  */\r\n#define TIM_BREAKINPUTSOURCE_DFSDM1    ((uint32_t)0x00000008U) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling\r\n  * @{\r\n  */\r\n#define TIM_BREAKINPUTSOURCE_DISABLE     ((uint32_t)0x00000000U) /* !< Break input source is disabled */\r\n#define TIM_BREAKINPUTSOURCE_ENABLE      ((uint32_t)0x00000001U) /* !< Break input source is enabled */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup TIMEx_Exported_Macros TIMEx Exported Macros\r\n  * @{\r\n  */  \r\n\r\n/**\r\n  * @brief  Sets the TIM Capture Compare Register value on runtime without\r\n  *         calling another time ConfigChannel function.\r\n  * @param  __HANDLE__: TIM handle.\r\n  * @param  __CHANNEL__ : TIM Channels to be configured.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected\r\n  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected\r\n  * @param  __COMPARE__: specifies the Capture Compare register new value.\r\n  * @retval None\r\n  */\r\n#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \\\r\n(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\\\r\n ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\\\r\n ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\\\r\n ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\\\r\n ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\\\r\n ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))\r\n\r\n/**\r\n  * @brief  Gets the TIM Capture Compare Register value on runtime\r\n  * @param  __HANDLE__: TIM handle.\r\n  * @param  __CHANNEL__ : TIM Channel associated with the capture compare register\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: get capture/compare 1 register value\r\n  *            @arg TIM_CHANNEL_2: get capture/compare 2 register value\r\n  *            @arg TIM_CHANNEL_3: get capture/compare 3 register value\r\n  *            @arg TIM_CHANNEL_4: get capture/compare 4 register value\r\n  *            @arg TIM_CHANNEL_5: get capture/compare 5 register value\r\n  *            @arg TIM_CHANNEL_6: get capture/compare 6 register value\r\n  * @retval None\r\n  */\r\n#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \\\r\n(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\\\r\n ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\\\r\n ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\\\r\n ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\\\r\n ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\\\r\n ((__HANDLE__)->Instance->CCR6))\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup TIMEx_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup TIMEx_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n/*  Timer Hall Sensor functions  **********************************************/\r\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef* htim, TIM_HallSensor_InitTypeDef* sConfig);\r\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef* htim);\r\n\r\nvoid HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef* htim);\r\nvoid HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef* htim);\r\n\r\n /* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef* htim);\r\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef* htim);\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef* htim);\r\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef* htim);\r\n/* Non-Blocking mode: DMA */\r\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef* htim, uint32_t *pData, uint16_t Length);\r\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef* htim);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup TIMEx_Exported_Functions_Group2\r\n  * @{\r\n  */\r\n/*  Timer Complementary Output Compare functions  *****************************/\r\n/* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);\r\n\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);\r\n\r\n/* Non-Blocking mode: DMA */\r\nHAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r\nHAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup TIMEx_Exported_Functions_Group3\r\n  * @{\r\n  */\r\n/*  Timer Complementary PWM functions  ****************************************/\r\n/* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);\r\n\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);\r\nHAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);\r\n/* Non-Blocking mode: DMA */\r\nHAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\r\nHAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup TIMEx_Exported_Functions_Group4\r\n  * @{\r\n  */\r\n/*  Timer Complementary One Pulse functions  **********************************/\r\n/* Blocking mode: Polling */\r\nHAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef* htim, uint32_t OutputChannel);\r\nHAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef* htim, uint32_t OutputChannel);\r\n\r\n/* Non-Blocking mode: Interrupt */\r\nHAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);\r\nHAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup TIMEx_Exported_Functions_Group5\r\n  * @{\r\n  */\r\n/* Extension Control functions  ************************************************/\r\nHAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef* htim, uint32_t  InputTrigger, uint32_t  CommutationSource);\r\nHAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef* htim, uint32_t  InputTrigger, uint32_t  CommutationSource);\r\nHAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef* htim, uint32_t  InputTrigger, uint32_t  CommutationSource);\r\nHAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef* htim, TIM_MasterConfigTypeDef * sMasterConfig);\r\nHAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef* htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);\r\n#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r\nHAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\nHAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef* htim, uint32_t Remap);\r\nHAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRef);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup TIMEx_Exported_Functions_Group6\r\n  * @{\r\n  */ \r\n/* Extension Callback *********************************************************/\r\nvoid HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef* htim);\r\nvoid HAL_TIMEx_BreakCallback(TIM_HandleTypeDef* htim);\r\nvoid HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup TIMEx_Exported_Functions_Group7\r\n  * @{\r\n  */\r\n/* Extension Peripheral State functions  **************************************/\r\nHAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup TIMEx_Private_Macros TIMEx Private Macros\r\n  * @{\r\n  */\r\n#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \\\r\n                                  ((CHANNEL) == TIM_CHANNEL_2) || \\\r\n                                  ((CHANNEL) == TIM_CHANNEL_3) || \\\r\n                                  ((CHANNEL) == TIM_CHANNEL_4) || \\\r\n                                  ((CHANNEL) == TIM_CHANNEL_5) || \\\r\n                                  ((CHANNEL) == TIM_CHANNEL_6) || \\\r\n                                  ((CHANNEL) == TIM_CHANNEL_ALL))\r\n                                 \r\n#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \\\r\n                                       ((CHANNEL) == TIM_CHANNEL_2))\r\n                                      \r\n#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \\\r\n                                      ((CHANNEL) == TIM_CHANNEL_2))                                       \r\n\r\n#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \\\r\n                                                ((CHANNEL) == TIM_CHANNEL_2) || \\\r\n                                                ((CHANNEL) == TIM_CHANNEL_3))\r\n#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1)               || \\\r\n\t                       ((MODE) == TIM_OCMODE_PWM2)               || \\\r\n                               ((MODE) == TIM_OCMODE_COMBINED_PWM1)      || \\\r\n                               ((MODE) == TIM_OCMODE_COMBINED_PWM2)      || \\\r\n                               ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM1)    || \\\r\n                               ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM2))\r\n                              \r\n#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING)             || \\\r\n                             ((MODE) == TIM_OCMODE_ACTIVE)             || \\\r\n                             ((MODE) == TIM_OCMODE_INACTIVE)           || \\\r\n                             ((MODE) == TIM_OCMODE_TOGGLE)             || \\\r\n                             ((MODE) == TIM_OCMODE_FORCED_ACTIVE)      || \\\r\n                             ((MODE) == TIM_OCMODE_FORCED_INACTIVE)    || \\\r\n                             ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \\\r\n                             ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM2))\r\n#define IS_TIM_REMAP(__TIM_REMAP__)\t (((__TIM_REMAP__) == TIM_TIM2_TIM8_TRGO)||\\\r\n                                      ((__TIM_REMAP__) == TIM_TIM2_ETH_PTP)||\\\r\n                                      ((__TIM_REMAP__) == TIM_TIM2_USBFS_SOF)||\\\r\n                                      ((__TIM_REMAP__) == TIM_TIM2_USBHS_SOF)||\\\r\n                                      ((__TIM_REMAP__) == TIM_TIM5_GPIO)||\\\r\n                                      ((__TIM_REMAP__) == TIM_TIM5_LSI)||\\\r\n                                      ((__TIM_REMAP__) == TIM_TIM5_LSE)||\\\r\n                                      ((__TIM_REMAP__) == TIM_TIM5_RTC)||\\\r\n                                      ((__TIM_REMAP__) == TIM_TIM11_GPIO)||\\\r\n                                      ((__TIM_REMAP__) == TIM_TIM11_SPDIFRX)||\\\r\n                                      ((__TIM_REMAP__) == TIM_TIM11_HSE)||\\\r\n                                      ((__TIM_REMAP__) == TIM_TIM11_MCO1))  \r\n#define IS_TIM_DEADTIME(__DEADTIME__)      ((__DEADTIME__) <= 0xFF) \r\n#define IS_TIM_BREAK_FILTER(__FILTER__) ((__FILTER__) <= 0xF)\r\n#define IS_TIM_CLEARINPUT_SOURCE(MODE) (((MODE) == TIM_CLEARINPUTSOURCE_ETR)      || \\\r\n                                        ((MODE) == TIM_CLEARINPUTSOURCE_OCREFCLR)  || \\\r\n                                        ((MODE) == TIM_CLEARINPUTSOURCE_NONE))\r\n#define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_BREAK2_ENABLE) || \\\r\n                                    ((STATE) == TIM_BREAK2_DISABLE))\r\n#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \\\r\n                                              ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))\r\n#define IS_TIM_GROUPCH5(OCREF) ((((OCREF) & 0x1FFFFFFF) == 0x00000000))\r\n#define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2_RESET)                        || \\\r\n                                     ((SOURCE) == TIM_TRGO2_ENABLE)                       || \\\r\n                                     ((SOURCE) == TIM_TRGO2_UPDATE)                       || \\\r\n                                     ((SOURCE) == TIM_TRGO2_OC1)                          || \\\r\n                                     ((SOURCE) == TIM_TRGO2_OC1REF)                       || \\\r\n                                     ((SOURCE) == TIM_TRGO2_OC2REF)                       || \\\r\n                                     ((SOURCE) == TIM_TRGO2_OC3REF)                       || \\\r\n                                     ((SOURCE) == TIM_TRGO2_OC3REF)                       || \\\r\n                                     ((SOURCE) == TIM_TRGO2_OC4REF)                       || \\\r\n                                     ((SOURCE) == TIM_TRGO2_OC5REF)                       || \\\r\n                                     ((SOURCE) == TIM_TRGO2_OC6REF)                       || \\\r\n                                     ((SOURCE) == TIM_TRGO2_OC4REF_RISINGFALLING)         || \\\r\n                                     ((SOURCE) == TIM_TRGO2_OC6REF_RISINGFALLING)         || \\\r\n                                     ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING)  || \\\r\n                                     ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \\\r\n                                     ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING)  || \\\r\n                                     ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))\r\n#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE)   || \\\r\n                                 ((MODE) == TIM_SLAVEMODE_RESET)     || \\\r\n                                 ((MODE) == TIM_SLAVEMODE_GATED)     || \\\r\n                                 ((MODE) == TIM_SLAVEMODE_TRIGGER)   || \\\r\n                                 ((MODE) == TIM_SLAVEMODE_EXTERNAL1) || \\\r\n                                 ((MODE) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))\r\n\r\n#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r\n#define IS_TIM_BREAKINPUT(__BREAKINPUT__)  (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK)  || \\\r\n                                            ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))\r\n                                            \r\n#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \\\r\n                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM))\r\n\r\n#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)  (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE)  || \\\r\n                                                   ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))\r\n                                                   \r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup TIMEx_Private_Functions TIMEx Private Functions\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n    \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_TIM_EX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_uart.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of UART HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************  \r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_UART_H\r\n#define __STM32F7xx_HAL_UART_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup UART\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup UART_Exported_Types UART Exported Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief UART Init Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t BaudRate;                  /*!< This member configures the UART communication baud rate.\r\n                                           The baud rate register is computed using the following formula:\r\n                                           - If oversampling is 16 or in LIN mode,\r\n                                              Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate)))\r\n                                           - If oversampling is 8,\r\n                                              Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4]\r\n                                              Baud Rate Register[3] =  0\r\n                                              Baud Rate Register[2:0] =  (((2 * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1      */\r\n\r\n  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.\r\n                                           This parameter can be a value of @ref UARTEx_Word_Length */\r\n\r\n  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.\r\n                                           This parameter can be a value of @ref UART_Stop_Bits */\r\n\r\n  uint32_t Parity;                    /*!< Specifies the parity mode.\r\n                                           This parameter can be a value of @ref UART_Parity\r\n                                           @note When parity is enabled, the computed parity is inserted\r\n                                                 at the MSB position of the transmitted data (9th bit when\r\n                                                 the word length is set to 9 data bits; 8th bit when the\r\n                                                 word length is set to 8 data bits). */\r\n\r\n  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.\r\n                                           This parameter can be a value of @ref UART_Mode */\r\n\r\n  uint32_t HwFlowCtl;                 /*!< Specifies whether the hardware flow control mode is enabled\r\n                                           or disabled.\r\n                                           This parameter can be a value of @ref UART_Hardware_Flow_Control */\r\n\r\n  uint32_t OverSampling;              /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).\r\n                                           This parameter can be a value of @ref UART_Over_Sampling */\r\n\r\n  uint32_t OneBitSampling;            /*!< Specifies whether a single sample or three samples' majority vote is selected.\r\n                                           Selecting the single sample method increases the receiver tolerance to clock\r\n                                           deviations. This parameter can be a value of @ref UART_OneBit_Sampling */\r\n}UART_InitTypeDef;\r\n\r\n/**\r\n  * @brief  UART Advanced Features initialization structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t AdvFeatureInit;        /*!< Specifies which advanced UART features is initialized. Several\r\n                                       Advanced Features may be initialized at the same time .\r\n                                       This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type */\r\n\r\n  uint32_t TxPinLevelInvert;      /*!< Specifies whether the TX pin active level is inverted.\r\n                                       This parameter can be a value of @ref UART_Tx_Inv  */\r\n\r\n  uint32_t RxPinLevelInvert;      /*!< Specifies whether the RX pin active level is inverted.\r\n                                       This parameter can be a value of @ref UART_Rx_Inv  */\r\n\r\n  uint32_t DataInvert;            /*!< Specifies whether data are inverted (positive/direct logic\r\n                                       vs negative/inverted logic).\r\n                                       This parameter can be a value of @ref UART_Data_Inv */\r\n\r\n  uint32_t Swap;                  /*!< Specifies whether TX and RX pins are swapped.\r\n                                       This parameter can be a value of @ref UART_Rx_Tx_Swap */\r\n\r\n  uint32_t OverrunDisable;        /*!< Specifies whether the reception overrun detection is disabled.\r\n                                       This parameter can be a value of @ref UART_Overrun_Disable */\r\n\r\n  uint32_t DMADisableonRxError;   /*!< Specifies whether the DMA is disabled in case of reception error.\r\n                                       This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error */\r\n\r\n  uint32_t AutoBaudRateEnable;    /*!< Specifies whether auto Baud rate detection is enabled.\r\n                                       This parameter can be a value of @ref UART_AutoBaudRate_Enable */\r\n\r\n  uint32_t AutoBaudRateMode;      /*!< If auto Baud rate detection is enabled, specifies how the rate\r\n                                       detection is carried out.\r\n                                       This parameter can be a value of @ref UART_AutoBaud_Rate_Mode */\r\n\r\n  uint32_t MSBFirst;              /*!< Specifies whether MSB is sent first on UART line.\r\n                                       This parameter can be a value of @ref UART_MSB_First */\r\n} UART_AdvFeatureInitTypeDef;\r\n\r\n\r\n\r\n/**\r\n  * @brief HAL UART State structures definition\r\n  * @note  HAL UART State value is a combination of 2 different substates: gState and RxState.\r\n  *        - gState contains UART state information related to global Handle management \r\n  *          and also information related to Tx operations.\r\n  *          gState value coding follow below described bitmap :\r\n  *          b7-b6  Error information \r\n  *             00 : No Error\r\n  *             01 : (Not Used)\r\n  *             10 : Timeout\r\n  *             11 : Error\r\n  *          b5     IP initilisation status\r\n  *             0  : Reset (IP not initialized)\r\n  *             1  : Init done (IP not initialized. HAL UART Init function already called)\r\n  *          b4-b3  (not used)\r\n  *             xx : Should be set to 00\r\n  *          b2     Intrinsic process state\r\n  *             0  : Ready\r\n  *             1  : Busy (IP busy with some configuration or internal operations)\r\n  *          b1     (not used)\r\n  *             x  : Should be set to 0\r\n  *          b0     Tx state\r\n  *             0  : Ready (no Tx operation ongoing)\r\n  *             1  : Busy (Tx operation ongoing)\r\n  *        - RxState contains information related to Rx operations.\r\n  *          RxState value coding follow below described bitmap :\r\n  *          b7-b6  (not used)\r\n  *             xx : Should be set to 00\r\n  *          b5     IP initilisation status\r\n  *             0  : Reset (IP not initialized)\r\n  *             1  : Init done (IP not initialized)\r\n  *          b4-b2  (not used)\r\n  *            xxx : Should be set to 000\r\n  *          b1     Rx state\r\n  *             0  : Ready (no Rx operation ongoing)\r\n  *             1  : Busy (Rx operation ongoing)\r\n  *          b0     (not used)\r\n  *             x  : Should be set to 0.\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_UART_STATE_RESET             = 0x00U,   /*!< Peripheral is not initialized\r\n                                                   Value is allowed for gState and RxState */\r\n  HAL_UART_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use\r\n                                                   Value is allowed for gState and RxState */\r\n  HAL_UART_STATE_BUSY              = 0x24U,   /*!< an internal process is ongoing \r\n                                                   Value is allowed for gState only */\r\n  HAL_UART_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing\r\n                                                   Value is allowed for gState only */\r\n  HAL_UART_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing\r\n                                                   Value is allowed for RxState only */\r\n  HAL_UART_STATE_BUSY_TX_RX        = 0x23U,   /*!< Data Transmission and Reception process is ongoing\r\n                                                   Not to be used for neither gState nor RxState.\r\n                                                   Value is result of combination (Or) between gState and RxState values */\r\n  HAL_UART_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state\r\n                                                   Value is allowed for gState only */\r\n  HAL_UART_STATE_ERROR             = 0xE0U    /*!< Error\r\n                                                   Value is allowed for gState only */\r\n}HAL_UART_StateTypeDef;\r\n\r\n/**\r\n  * @brief UART clock sources definition\r\n  */\r\ntypedef enum\r\n{\r\n  UART_CLOCKSOURCE_PCLK1      = 0x00U,    /*!< PCLK1 clock source  */\r\n  UART_CLOCKSOURCE_PCLK2      = 0x01U,    /*!< PCLK2 clock source  */\r\n  UART_CLOCKSOURCE_HSI        = 0x02U,    /*!< HSI clock source    */\r\n  UART_CLOCKSOURCE_SYSCLK     = 0x04U,    /*!< SYSCLK clock source */\r\n  UART_CLOCKSOURCE_LSE        = 0x08U,    /*!< LSE clock source       */\r\n  UART_CLOCKSOURCE_UNDEFINED  = 0x10U     /*!< Undefined clock source */\r\n}UART_ClockSourceTypeDef;\r\n\r\n/**\r\n  * @brief  UART handle Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  USART_TypeDef            *Instance;        /*!< UART registers base address        */\r\n\r\n  UART_InitTypeDef         Init;             /*!< UART communication parameters      */\r\n\r\n  UART_AdvFeatureInitTypeDef AdvancedInit;   /*!< UART Advanced Features initialization parameters */\r\n\r\n  uint8_t                  *pTxBuffPtr;      /*!< Pointer to UART Tx transfer Buffer */\r\n\r\n  uint16_t                 TxXferSize;       /*!< UART Tx Transfer size              */\r\n\r\n  uint16_t                 TxXferCount;      /*!< UART Tx Transfer Counter           */\r\n\r\n  uint8_t                  *pRxBuffPtr;      /*!< Pointer to UART Rx transfer Buffer */\r\n\r\n  uint16_t                 RxXferSize;       /*!< UART Rx Transfer size              */\r\n\r\n  uint16_t                 RxXferCount;      /*!< UART Rx Transfer Counter           */\r\n\r\n  uint16_t                 Mask;             /*!< UART Rx RDR register mask          */\r\n\r\n  DMA_HandleTypeDef        *hdmatx;          /*!< UART Tx DMA Handle parameters      */\r\n\r\n  DMA_HandleTypeDef        *hdmarx;          /*!< UART Rx DMA Handle parameters      */\r\n\r\n  HAL_LockTypeDef           Lock;            /*!< Locking object                     */\r\n\r\n  __IO HAL_UART_StateTypeDef    gState;      /*!< UART state information related to global Handle management \r\n                                                  and also related to Tx operations.\r\n                                                  This parameter can be a value of @ref HAL_UART_StateTypeDef */\r\n\r\n  __IO HAL_UART_StateTypeDef    RxState;     /*!< UART state information related to Rx operations.\r\n                                                  This parameter can be a value of @ref HAL_UART_StateTypeDef */\r\n\r\n  __IO uint32_t             ErrorCode;   /*!< UART Error code                    */\r\n\r\n}UART_HandleTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup UART_Exported_Constants UART Exported Constants\r\n  * @{\r\n  */\r\n/** @defgroup UART_Error_Definition   UART Error Definition\r\n  * @{\r\n  */\r\n#define  HAL_UART_ERROR_NONE       ((uint32_t)0x00000000U)    /*!< No error            */\r\n#define  HAL_UART_ERROR_PE         ((uint32_t)0x00000001U)    /*!< Parity error        */\r\n#define  HAL_UART_ERROR_NE         ((uint32_t)0x00000002U)    /*!< Noise error         */\r\n#define  HAL_UART_ERROR_FE         ((uint32_t)0x00000004U)    /*!< frame error         */\r\n#define  HAL_UART_ERROR_ORE        ((uint32_t)0x00000008U)    /*!< Overrun error       */\r\n#define  HAL_UART_ERROR_DMA        ((uint32_t)0x00000010U)    /*!< DMA transfer error  */\r\n/**\r\n  * @}\r\n  */\r\n/** @defgroup UART_Stop_Bits   UART Number of Stop Bits\r\n  * @{\r\n  */\r\n#define UART_STOPBITS_1                     ((uint32_t)0x00000000U)\r\n#define UART_STOPBITS_2                     ((uint32_t)USART_CR2_STOP_1)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Parity  UART Parity\r\n  * @{\r\n  */\r\n#define UART_PARITY_NONE                    ((uint32_t)0x00000000U)\r\n#define UART_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)\r\n#define UART_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control\r\n  * @{\r\n  */\r\n#define UART_HWCONTROL_NONE                  ((uint32_t)0x00000000U)\r\n#define UART_HWCONTROL_RTS                   ((uint32_t)USART_CR3_RTSE)\r\n#define UART_HWCONTROL_CTS                   ((uint32_t)USART_CR3_CTSE)\r\n#define UART_HWCONTROL_RTS_CTS               ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Mode UART Transfer Mode\r\n  * @{\r\n  */\r\n#define UART_MODE_RX                        ((uint32_t)USART_CR1_RE)\r\n#define UART_MODE_TX                        ((uint32_t)USART_CR1_TE)\r\n#define UART_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))\r\n/**\r\n  * @}\r\n  */\r\n\r\n /** @defgroup UART_State  UART State\r\n  * @{\r\n  */\r\n#define UART_STATE_DISABLE                  ((uint32_t)0x00000000U)\r\n#define UART_STATE_ENABLE                   ((uint32_t)USART_CR1_UE)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Over_Sampling UART Over Sampling\r\n  * @{\r\n  */\r\n#define UART_OVERSAMPLING_16                ((uint32_t)0x00000000U)\r\n#define UART_OVERSAMPLING_8                 ((uint32_t)USART_CR1_OVER8)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method\r\n  * @{\r\n  */\r\n#define UART_ONE_BIT_SAMPLE_DISABLE         ((uint32_t)0x00000000U)\r\n#define UART_ONE_BIT_SAMPLE_ENABLE          ((uint32_t)USART_CR3_ONEBIT)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_AutoBaud_Rate_Mode    UART Advanced Feature AutoBaud Rate Mode\r\n  * @{\r\n  */\r\n#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT    ((uint32_t)0x0000U)\r\n#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0)\r\n#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME   ((uint32_t)USART_CR2_ABRMODE_1)\r\n#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME   ((uint32_t)USART_CR2_ABRMODE)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut\r\n  * @{\r\n  */\r\n#define UART_RECEIVER_TIMEOUT_DISABLE       ((uint32_t)0x00000000U)\r\n#define UART_RECEIVER_TIMEOUT_ENABLE        ((uint32_t)USART_CR2_RTOEN)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_LIN    UART Local Interconnection Network mode\r\n  * @{\r\n  */\r\n#define UART_LIN_DISABLE                    ((uint32_t)0x00000000U)\r\n#define UART_LIN_ENABLE                     ((uint32_t)USART_CR2_LINEN)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_LIN_Break_Detection  UART LIN Break Detection\r\n  * @{\r\n  */\r\n#define UART_LINBREAKDETECTLENGTH_10B       ((uint32_t)0x00000000U)\r\n#define UART_LINBREAKDETECTLENGTH_11B       ((uint32_t)USART_CR2_LBDL)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_DMA_Tx    UART DMA Tx\r\n  * @{\r\n  */\r\n#define UART_DMA_TX_DISABLE                 ((uint32_t)0x00000000U)\r\n#define UART_DMA_TX_ENABLE                  ((uint32_t)USART_CR3_DMAT)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_DMA_Rx   UART DMA Rx\r\n  * @{\r\n  */\r\n#define UART_DMA_RX_DISABLE                 ((uint32_t)0x0000U)\r\n#define UART_DMA_RX_ENABLE                  ((uint32_t)USART_CR3_DMAR)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Half_Duplex_Selection  UART Half Duplex Selection\r\n  * @{\r\n  */\r\n#define UART_HALF_DUPLEX_DISABLE            ((uint32_t)0x0000U)\r\n#define UART_HALF_DUPLEX_ENABLE             ((uint32_t)USART_CR3_HDSEL)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_WakeUp_Methods   UART WakeUp Methods\r\n  * @{\r\n  */\r\n#define UART_WAKEUPMETHOD_IDLELINE          ((uint32_t)0x00000000U)\r\n#define UART_WAKEUPMETHOD_ADDRESSMARK       ((uint32_t)USART_CR1_WAKE)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Request_Parameters UART Request Parameters\r\n  * @{\r\n  */\r\n#define UART_AUTOBAUD_REQUEST               ((uint32_t)USART_RQR_ABRRQ)        /*!< Auto-Baud Rate Request */\r\n#define UART_SENDBREAK_REQUEST              ((uint32_t)USART_RQR_SBKRQ)        /*!< Send Break Request */\r\n#define UART_MUTE_MODE_REQUEST              ((uint32_t)USART_RQR_MMRQ)         /*!< Mute Mode Request */\r\n#define UART_RXDATA_FLUSH_REQUEST           ((uint32_t)USART_RQR_RXFRQ)        /*!< Receive Data flush Request */\r\n#define UART_TXDATA_FLUSH_REQUEST           ((uint32_t)USART_RQR_TXFRQ)        /*!< Transmit data flush Request */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Advanced_Features_Initialization_Type  UART Advanced Feature Initialization Type\r\n  * @{\r\n  */\r\n#define UART_ADVFEATURE_NO_INIT                 ((uint32_t)0x00000000U)\r\n#define UART_ADVFEATURE_TXINVERT_INIT           ((uint32_t)0x00000001U)\r\n#define UART_ADVFEATURE_RXINVERT_INIT           ((uint32_t)0x00000002U)\r\n#define UART_ADVFEATURE_DATAINVERT_INIT         ((uint32_t)0x00000004U)\r\n#define UART_ADVFEATURE_SWAP_INIT               ((uint32_t)0x00000008U)\r\n#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT   ((uint32_t)0x00000010U)\r\n#define UART_ADVFEATURE_DMADISABLEONERROR_INIT  ((uint32_t)0x00000020U)\r\n#define UART_ADVFEATURE_AUTOBAUDRATE_INIT       ((uint32_t)0x00000040U)\r\n#define UART_ADVFEATURE_MSBFIRST_INIT           ((uint32_t)0x00000080U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion\r\n  * @{\r\n  */\r\n#define UART_ADVFEATURE_TXINV_DISABLE       ((uint32_t)0x00000000U)\r\n#define UART_ADVFEATURE_TXINV_ENABLE        ((uint32_t)USART_CR2_TXINV)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion\r\n  * @{\r\n  */\r\n#define UART_ADVFEATURE_RXINV_DISABLE       ((uint32_t)0x00000000U)\r\n#define UART_ADVFEATURE_RXINV_ENABLE        ((uint32_t)USART_CR2_RXINV)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Data_Inv  UART Advanced Feature Binary Data Inversion\r\n  * @{\r\n  */\r\n#define UART_ADVFEATURE_DATAINV_DISABLE     ((uint32_t)0x00000000U)\r\n#define UART_ADVFEATURE_DATAINV_ENABLE      ((uint32_t)USART_CR2_DATAINV)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap\r\n  * @{\r\n  */\r\n#define UART_ADVFEATURE_SWAP_DISABLE        ((uint32_t)0x00000000U)\r\n#define UART_ADVFEATURE_SWAP_ENABLE         ((uint32_t)USART_CR2_SWAP)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Overrun_Disable  UART Advanced Feature Overrun Disable\r\n  * @{\r\n  */\r\n#define UART_ADVFEATURE_OVERRUN_ENABLE      ((uint32_t)0x00000000U)\r\n#define UART_ADVFEATURE_OVERRUN_DISABLE     ((uint32_t)USART_CR3_OVRDIS)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_AutoBaudRate_Enable  UART Advanced Feature Auto BaudRate Enable\r\n  * @{\r\n  */\r\n#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE   ((uint32_t)0x00000000U)\r\n#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE    ((uint32_t)USART_CR2_ABREN)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_DMA_Disable_on_Rx_Error   UART Advanced Feature DMA Disable On Rx Error\r\n  * @{\r\n  */\r\n#define UART_ADVFEATURE_DMA_ENABLEONRXERROR    ((uint32_t)0x00000000U)\r\n#define UART_ADVFEATURE_DMA_DISABLEONRXERROR   ((uint32_t)USART_CR3_DDRE)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_MSB_First   UART Advanced Feature MSB First\r\n  * @{\r\n  */\r\n#define UART_ADVFEATURE_MSBFIRST_DISABLE    ((uint32_t)0x00000000U)\r\n#define UART_ADVFEATURE_MSBFIRST_ENABLE     ((uint32_t)USART_CR2_MSBFIRST)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Mute_Mode   UART Advanced Feature Mute Mode Enable\r\n  * @{\r\n  */\r\n#define UART_ADVFEATURE_MUTEMODE_DISABLE    ((uint32_t)0x00000000U)\r\n#define UART_ADVFEATURE_MUTEMODE_ENABLE     ((uint32_t)USART_CR1_MME)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_CR2_ADDRESS_LSB_POS    UART Address-matching LSB Position In CR2 Register\r\n  * @{\r\n  */\r\n#define UART_CR2_ADDRESS_LSB_POS            ((uint32_t) 24U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_DriverEnable_Polarity      UART DriverEnable Polarity\r\n  * @{\r\n  */\r\n#define UART_DE_POLARITY_HIGH               ((uint32_t)0x00000000U)\r\n#define UART_DE_POLARITY_LOW                ((uint32_t)USART_CR3_DEP)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS    UART Driver Enable Assertion Time LSB Position In CR1 Register\r\n  * @{\r\n  */\r\n#define UART_CR1_DEAT_ADDRESS_LSB_POS       ((uint32_t) 21U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS    UART Driver Enable DeAssertion Time LSB Position In CR1 Register\r\n  * @{\r\n  */\r\n#define UART_CR1_DEDT_ADDRESS_LSB_POS       ((uint32_t) 16U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Interruption_Mask    UART Interruptions Flag Mask\r\n  * @{\r\n  */\r\n#define UART_IT_MASK                        ((uint32_t)0x001FU)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_TimeOut_Value    UART polling-based communications time-out value\r\n  * @{\r\n  */\r\n#define HAL_UART_TIMEOUT_VALUE              0x1FFFFFFU\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Flags     UART Status Flags\r\n  *        Elements values convention: 0xXXXX\r\n  *           - 0xXXXX  : Flag mask in the ISR register\r\n  * @{\r\n  */\r\n#define UART_FLAG_TEACK                     ((uint32_t)0x00200000U)\r\n#define UART_FLAG_SBKF                      ((uint32_t)0x00040000U)\r\n#define UART_FLAG_CMF                       ((uint32_t)0x00020000U)\r\n#define UART_FLAG_BUSY                      ((uint32_t)0x00010000U)\r\n#define UART_FLAG_ABRF                      ((uint32_t)0x00008000U)\r\n#define UART_FLAG_ABRE                      ((uint32_t)0x00004000U)\r\n#define UART_FLAG_EOBF                      ((uint32_t)0x00001000U)\r\n#define UART_FLAG_RTOF                      ((uint32_t)0x00000800U)\r\n#define UART_FLAG_CTS                       ((uint32_t)0x00000400U)\r\n#define UART_FLAG_CTSIF                     ((uint32_t)0x00000200U)\r\n#define UART_FLAG_LBDF                      ((uint32_t)0x00000100U)\r\n#define UART_FLAG_TXE                       ((uint32_t)0x00000080U)\r\n#define UART_FLAG_TC                        ((uint32_t)0x00000040U)\r\n#define UART_FLAG_RXNE                      ((uint32_t)0x00000020U)\r\n#define UART_FLAG_IDLE                      ((uint32_t)0x00000010U)\r\n#define UART_FLAG_ORE                       ((uint32_t)0x00000008U)\r\n#define UART_FLAG_NE                        ((uint32_t)0x00000004U)\r\n#define UART_FLAG_FE                        ((uint32_t)0x00000002U)\r\n#define UART_FLAG_PE                        ((uint32_t)0x00000001U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Interrupt_definition   UART Interrupts Definition\r\n  *        Elements values convention: 0000ZZZZ0XXYYYYYb\r\n  *           - YYYYY  : Interrupt source position in the XX register (5bits)\r\n  *           - XX  : Interrupt source register (2bits)\r\n  *                 - 01: CR1 register\r\n  *                 - 10: CR2 register\r\n  *                 - 11: CR3 register\r\n  *           - ZZZZ  : Flag position in the ISR register(4bits)\r\n  * @{\r\n  */\r\n#define UART_IT_PE                          ((uint32_t)0x0028U)\r\n#define UART_IT_TXE                         ((uint32_t)0x0727U)\r\n#define UART_IT_TC                          ((uint32_t)0x0626U)\r\n#define UART_IT_RXNE                        ((uint32_t)0x0525U)\r\n#define UART_IT_IDLE                        ((uint32_t)0x0424U)\r\n#define UART_IT_LBD                         ((uint32_t)0x0846U)\r\n#define UART_IT_CTS                         ((uint32_t)0x096AU)\r\n#define UART_IT_CM                          ((uint32_t)0x112EU)\r\n\r\n/**       Elements values convention: 000000000XXYYYYYb\r\n  *           - YYYYY  : Interrupt source position in the XX register (5bits)\r\n  *           - XX  : Interrupt source register (2bits)\r\n  *                 - 01: CR1 register\r\n  *                 - 10: CR2 register\r\n  *                 - 11: CR3 register\r\n  */\r\n#define UART_IT_ERR                         ((uint32_t)0x0060U)\r\n\r\n/**       Elements values convention: 0000ZZZZ00000000b\r\n  *           - ZZZZ  : Flag position in the ISR register(4bits)\r\n  */\r\n#define UART_IT_ORE                         ((uint32_t)0x0300U)\r\n#define UART_IT_NE                          ((uint32_t)0x0200U)\r\n#define UART_IT_FE                          ((uint32_t)0x0100U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_IT_CLEAR_Flags  UART Interruption Clear Flags\r\n  * @{\r\n  */\r\n#define UART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag */\r\n#define UART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag */\r\n#define UART_CLEAR_NEF                       USART_ICR_NCF             /*!< Noise detected Clear Flag */\r\n#define UART_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag */\r\n#define UART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag */\r\n#define UART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag */\r\n#define UART_CLEAR_LBDF                      USART_ICR_LBDCF           /*!< LIN Break Detection Clear Flag */\r\n#define UART_CLEAR_CTSF                      USART_ICR_CTSCF           /*!< CTS Interrupt Clear Flag */\r\n#define UART_CLEAR_RTOF                      USART_ICR_RTOCF           /*!< Receiver Time Out Clear Flag */\r\n#define UART_CLEAR_EOBF                      USART_ICR_EOBCF           /*!< End Of Block Clear Flag */\r\n#define UART_CLEAR_CMF                       USART_ICR_CMCF            /*!< Character Match Clear Flag */\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macros -----------------------------------------------------------*/\r\n/** @defgroup UART_Exported_Macros UART Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief Reset UART handle state\r\n  * @param  __HANDLE__: UART handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \\\r\n                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \\\r\n                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \\\r\n                                                     } while(0)\r\n\r\n/** @brief  Flush the UART Data registers\r\n  * @param  __HANDLE__: specifies the UART Handle.\r\n  */\r\n#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)  \\\r\n  do{                \\\r\n      SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \\\r\n      SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \\\r\n    }  while(0)\r\n\r\n/** @brief  Clears the specified UART ISR flag, in setting the proper ICR register flag.\r\n  * @param  __HANDLE__: specifies the UART Handle.\r\n  * @param  __FLAG__: specifies the interrupt clear register flag that needs to be set\r\n  *                       to clear the corresponding interrupt\r\n  *          This parameter can be one of the following values:\r\n  *            @arg UART_CLEAR_PEF: Parity Error Clear Flag\r\n  *            @arg UART_CLEAR_FEF: Framing Error Clear Flag\r\n  *            @arg UART_CLEAR_NEF: Noise detected Clear Flag\r\n  *            @arg UART_CLEAR_OREF: OverRun Error Clear Flag\r\n  *            @arg UART_CLEAR_IDLEF: IDLE line detected Clear Flag\r\n  *            @arg UART_CLEAR_TCF: Transmission Complete Clear Flag\r\n  *            @arg UART_CLEAR_LBDF: LIN Break Detection Clear Flag\r\n  *            @arg UART_CLEAR_CTSF: CTS Interrupt Clear Flag\r\n  *            @arg UART_CLEAR_RTOF: Receiver Time Out Clear Flag\r\n  *            @arg UART_CLEAR_EOBF: End Of Block Clear Flag\r\n  *            @arg UART_CLEAR_CMF: Character Match Clear Flag\r\n  * @retval None\r\n  */\r\n#define __HAL_UART_CLEAR_IT(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__FLAG__))\r\n\r\n/** @brief  Clear the UART PE pending flag.\r\n  * @param  __HANDLE__: specifies the UART Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__)   __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_PEF)\r\n\r\n/** @brief  Clear the UART FE pending flag.\r\n  * @param  __HANDLE__: specifies the UART Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__)   __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_FEF)\r\n\r\n/** @brief  Clear the UART NE pending flag.\r\n  * @param  __HANDLE__: specifies the UART Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__)  __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_NEF)\r\n\r\n/** @brief  Clear the UART ORE pending flag.\r\n  * @param  __HANDLE__: specifies the UART Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__)   __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_OREF)\r\n\r\n/** @brief  Clear the UART IDLE pending flag.\r\n  * @param  __HANDLE__: specifies the UART Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_IDLEF)\r\n\r\n/** @brief  Checks whether the specified UART flag is set or not.\r\n  * @param  __HANDLE__: specifies the UART Handle.\r\n  * @param  __FLAG__: specifies the flag to check.\r\n  *        This parameter can be one of the following values:\r\n  *            @arg UART_FLAG_REACK: Receive enable acknowledge flag\r\n  *            @arg UART_FLAG_TEACK: Transmit enable acknowledge flag\r\n  *            @arg UART_FLAG_WUF:   Wake up from stop mode flag\r\n  *            @arg UART_FLAG_RWU:   Receiver wake up flag (is the UART in mute mode)\r\n  *            @arg UART_FLAG_SBKF:  Send Break flag\r\n  *            @arg UART_FLAG_CMF:   Character match flag\r\n  *            @arg UART_FLAG_BUSY:  Busy flag\r\n  *            @arg UART_FLAG_ABRF:  Auto Baud rate detection flag\r\n  *            @arg UART_FLAG_ABRE:  Auto Baud rate detection error flag\r\n  *            @arg UART_FLAG_EOBF:  End of block flag\r\n  *            @arg UART_FLAG_RTOF:  Receiver timeout flag\r\n  *            @arg UART_FLAG_CTS:   CTS Change flag (not available for UART4 and UART5)\r\n  *            @arg UART_FLAG_LBD:   LIN Break detection flag\r\n  *            @arg UART_FLAG_TXE:   Transmit data register empty flag\r\n  *            @arg UART_FLAG_TC:    Transmission Complete flag\r\n  *            @arg UART_FLAG_RXNE:  Receive data register not empty flag\r\n  *            @arg UART_FLAG_IDLE:  Idle Line detection flag\r\n  *            @arg UART_FLAG_ORE:   OverRun Error flag\r\n  *            @arg UART_FLAG_NE:    Noise Error flag\r\n  *            @arg UART_FLAG_FE:    Framing Error flag\r\n  *            @arg UART_FLAG_PE:    Parity Error flag\r\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))\r\n\r\n/** @brief  Enables the specified UART interrupt.\r\n  * @param  __HANDLE__: specifies the UART Handle.\r\n  * @param  __INTERRUPT__: specifies the UART interrupt source to enable.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg UART_IT_WUF:  Wakeup from stop mode interrupt\r\n  *            @arg UART_IT_CM:   Character match interrupt\r\n  *            @arg UART_IT_CTS:  CTS change interrupt\r\n  *            @arg UART_IT_LBD:  LIN Break detection interrupt\r\n  *            @arg UART_IT_TXE:  Transmit Data Register empty interrupt\r\n  *            @arg UART_IT_TC:   Transmission complete interrupt\r\n  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt\r\n  *            @arg UART_IT_IDLE: Idle line detection interrupt\r\n  *            @arg UART_IT_PE:   Parity Error interrupt\r\n  *            @arg UART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)\r\n  * @retval None\r\n  */\r\n#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \\\r\n                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \\\r\n                                                           ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))\r\n\r\n\r\n/** @brief  Disables the specified UART interrupt.\r\n  * @param  __HANDLE__: specifies the UART Handle.\r\n  * @param  __INTERRUPT__: specifies the UART interrupt source to disable.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg UART_IT_CM:   Character match interrupt\r\n  *            @arg UART_IT_CTS:  CTS change interrupt\r\n  *            @arg UART_IT_LBD:  LIN Break detection interrupt\r\n  *            @arg UART_IT_TXE:  Transmit Data Register empty interrupt\r\n  *            @arg UART_IT_TC:   Transmission complete interrupt\r\n  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt\r\n  *            @arg UART_IT_IDLE: Idle line detection interrupt\r\n  *            @arg UART_IT_PE:   Parity Error interrupt\r\n  *            @arg UART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)\r\n  * @retval None\r\n  */\r\n#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \\\r\n                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \\\r\n                                                           ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))\r\n\r\n/** @brief  Checks whether the specified UART interrupt has occurred or not.\r\n  * @param  __HANDLE__: specifies the UART Handle.\r\n  * @param  __IT__: specifies the UART interrupt to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg UART_IT_CM:   Character match interrupt\r\n  *            @arg UART_IT_CTS:  CTS change interrupt (not available for UART4 and UART5)\r\n  *            @arg UART_IT_LBD:  LIN Break detection interrupt\r\n  *            @arg UART_IT_TXE:  Transmit Data Register empty interrupt\r\n  *            @arg UART_IT_TC:   Transmission complete interrupt\r\n  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt\r\n  *            @arg UART_IT_IDLE: Idle line detection interrupt\r\n  *            @arg UART_IT_ORE:  OverRun Error interrupt\r\n  *            @arg UART_IT_NE:   Noise Error interrupt\r\n  *            @arg UART_IT_FE:   Framing Error interrupt\r\n  *            @arg UART_IT_PE:   Parity Error interrupt\r\n  * @retval The new state of __IT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))\r\n\r\n/** @brief  Checks whether the specified UART interrupt source is enabled.\r\n  * @param  __HANDLE__: specifies the UART Handle.\r\n  * @param  __IT__: specifies the UART interrupt source to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)\r\n  *            @arg UART_IT_LBD: LIN Break detection interrupt\r\n  *            @arg UART_IT_TXE: Transmit Data Register empty interrupt\r\n  *            @arg UART_IT_TC:  Transmission complete interrupt\r\n  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt\r\n  *            @arg UART_IT_IDLE: Idle line detection interrupt\r\n  *            @arg UART_IT_ORE: OverRun Error interrupt\r\n  *            @arg UART_IT_NE: Noise Error interrupt\r\n  *            @arg UART_IT_FE: Framing Error interrupt\r\n  *            @arg UART_IT_PE: Parity Error interrupt\r\n  * @retval The new state of __IT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \\\r\n                                                       (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & UART_IT_MASK)))\r\n\r\n/** @brief  Set a specific UART request flag.\r\n  * @param  __HANDLE__: specifies the UART Handle.\r\n  * @param  __REQ__: specifies the request flag to set\r\n  *          This parameter can be one of the following values:\r\n  *            @arg UART_AUTOBAUD_REQUEST: Auto-Baud Rate Request\r\n  *            @arg UART_SENDBREAK_REQUEST: Send Break Request\r\n  *            @arg UART_MUTE_MODE_REQUEST: Mute Mode Request\r\n  *            @arg UART_RXDATA_FLUSH_REQUEST: Receive Data flush Request\r\n  *            @arg UART_TXDATA_FLUSH_REQUEST: Transmit data flush Request\r\n  * @retval None\r\n  */\r\n#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))\r\n\r\n/** @brief  Enables the UART one bit sample method\r\n  * @param  __HANDLE__: specifies the UART Handle.  \r\n  * @retval None\r\n  */     \r\n#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)\r\n\r\n/** @brief  Disables the UART one bit sample method\r\n  * @param  __HANDLE__: specifies the UART Handle.  \r\n  * @retval None\r\n  */      \r\n#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))\r\n\r\n/** @brief  Enable UART\r\n  * @param  __HANDLE__: specifies the UART Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_UART_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)\r\n\r\n/** @brief  Disable UART\r\n  * @param  __HANDLE__: specifies the UART Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_UART_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)\r\n\r\n/** @brief  Enable CTS flow control \r\n  *         This macro allows to enable CTS hardware flow control for a given UART instance, \r\n  *         without need to call HAL_UART_Init() function.\r\n  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\r\n  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need\r\n  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\r\n  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )\r\n  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))\r\n  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).                                                                                                                  \r\n  * @param  __HANDLE__: specifies the UART Handle.\r\n  *         The Handle Instance can be USART1, USART2 or LPUART.\r\n  * @retval None\r\n  */\r\n#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)        \\\r\n  do{                                                      \\\r\n    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \\\r\n    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \\\r\n  } while(0)\r\n\r\n/** @brief  Disable CTS flow control \r\n  *         This macro allows to disable CTS hardware flow control for a given UART instance, \r\n  *         without need to call HAL_UART_Init() function.\r\n  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\r\n  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need\r\n  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\r\n  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )\r\n  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))\r\n  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). \r\n  * @param  __HANDLE__: specifies the UART Handle.\r\n  *         The Handle Instance can be USART1, USART2 or LPUART.\r\n  * @retval None\r\n  */\r\n#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)        \\\r\n  do{                                                       \\\r\n    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \\\r\n    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \\\r\n  } while(0)\r\n\r\n/** @brief  Enable RTS flow control \r\n  *         This macro allows to enable RTS hardware flow control for a given UART instance, \r\n  *         without need to call HAL_UART_Init() function.\r\n  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\r\n  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need\r\n  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\r\n  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )\r\n  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))\r\n  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). \r\n  * @param  __HANDLE__: specifies the UART Handle.\r\n  *         The Handle Instance can be USART1, USART2 or LPUART.\r\n  * @retval None\r\n  */\r\n#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)       \\\r\n  do{                                                     \\\r\n    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \\\r\n    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \\\r\n  } while(0)\r\n\r\n/** @brief  Disable RTS flow control \r\n  *         This macro allows to disable RTS hardware flow control for a given UART instance, \r\n  *         without need to call HAL_UART_Init() function.\r\n  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\r\n  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need\r\n  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\r\n  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )\r\n  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))\r\n  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). \r\n  * @param  __HANDLE__: specifies the UART Handle.\r\n  *         The Handle Instance can be USART1, USART2 or LPUART.\r\n  * @retval None\r\n  */\r\n#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)       \\\r\n  do{                                                      \\\r\n    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\\\r\n    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \\\r\n  } while(0)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros --------------------------------------------------------*/\r\n/** @defgroup UART_Private_Macros   UART Private Macros\r\n  * @{\r\n  */\r\n/** @brief  BRR division operation to set BRR register with LPUART\r\n  * @param  _PCLK_: LPUART clock\r\n  * @param  _BAUD_: Baud rate set by the user\r\n  * @retval Division result\r\n  */\r\n#define UART_DIV_LPUART(_PCLK_, _BAUD_)                ((((_PCLK_)*256)+((_BAUD_)/2))/((_BAUD_)))\r\n\r\n/** @brief  BRR division operation to set BRR register in 8-bit oversampling mode\r\n  * @param  _PCLK_: UART clock\r\n  * @param  _BAUD_: Baud rate set by the user\r\n  * @retval Division result\r\n  */\r\n#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_)             ((((_PCLK_)*2)+((_BAUD_)/2))/((_BAUD_)))\r\n\r\n/** @brief  BRR division operation to set BRR register in 16-bit oversampling mode\r\n  * @param  _PCLK_: UART clock\r\n  * @param  _BAUD_: Baud rate set by the user\r\n  * @retval Division result\r\n  */\r\n#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_)             ((((_PCLK_))+((_BAUD_)/2))/((_BAUD_)))\r\n\r\n/** @brief  Check UART Baud rate\r\n  * @param  BAUDRATE: Baudrate specified by the user\r\n  *         The maximum Baud Rate is derived from the maximum clock on F7 (i.e. 216 MHz)\r\n  *         divided by the smallest oversampling used on the USART (i.e. 8)\r\n  * @retval Test result (TRUE or FALSE).\r\n  */\r\n#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 9000001)\r\n\r\n/** @brief  Check UART assertion time\r\n  * @param  TIME: 5-bit value assertion time\r\n  * @retval Test result (TRUE or FALSE).\r\n  */\r\n#define IS_UART_ASSERTIONTIME(TIME)    ((TIME) <= 0x1F)\r\n\r\n/** @brief  Check UART deassertion time\r\n  * @param  TIME: 5-bit value deassertion time\r\n  * @retval Test result (TRUE or FALSE).\r\n  */\r\n#define IS_UART_DEASSERTIONTIME(TIME) ((TIME) <= 0x1F)\r\n\r\n#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \\\r\n                                    ((STOPBITS) == UART_STOPBITS_2))\r\n\r\n#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \\\r\n                                ((PARITY) == UART_PARITY_EVEN) || \\\r\n                                ((PARITY) == UART_PARITY_ODD))\r\n\r\n#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\\\r\n                              (((CONTROL) == UART_HWCONTROL_NONE) || \\\r\n                               ((CONTROL) == UART_HWCONTROL_RTS) || \\\r\n                               ((CONTROL) == UART_HWCONTROL_CTS) || \\\r\n                               ((CONTROL) == UART_HWCONTROL_RTS_CTS))\r\n\r\n#define IS_UART_MODE(MODE) ((((MODE) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((MODE) != (uint32_t)0x00))\r\n\r\n#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \\\r\n                              ((STATE) == UART_STATE_ENABLE))\r\n\r\n#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \\\r\n                                        ((SAMPLING) == UART_OVERSAMPLING_8))\r\n\r\n#define IS_UART_ONE_BIT_SAMPLE(ONEBIT) (((ONEBIT) == UART_ONE_BIT_SAMPLE_DISABLE) || \\\r\n                                        ((ONEBIT) == UART_ONE_BIT_SAMPLE_ENABLE))\r\n\r\n#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(MODE)  (((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \\\r\n                                                    ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \\\r\n                                                    ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \\\r\n                                                    ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))\r\n\r\n#define IS_UART_RECEIVER_TIMEOUT(TIMEOUT) (((TIMEOUT) == UART_RECEIVER_TIMEOUT_DISABLE) || \\\r\n                                           ((TIMEOUT) == UART_RECEIVER_TIMEOUT_ENABLE))\r\n\r\n#define IS_UART_LIN(LIN)            (((LIN) == UART_LIN_DISABLE) || \\\r\n                                     ((LIN) == UART_LIN_ENABLE))\r\n\r\n#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \\\r\n                                      ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))\r\n\r\n#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \\\r\n                                                 ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))\r\n\r\n#define IS_UART_DMA_TX(DMATX)         (((DMATX) == UART_DMA_TX_DISABLE) || \\\r\n                                       ((DMATX) == UART_DMA_TX_ENABLE))\r\n\r\n#define IS_UART_DMA_RX(DMARX)         (((DMARX) == UART_DMA_RX_DISABLE) || \\\r\n                                       ((DMARX) == UART_DMA_RX_ENABLE))\r\n\r\n#define IS_UART_HALF_DUPLEX(HDSEL)         (((HDSEL) == UART_HALF_DUPLEX_DISABLE) || \\\r\n                                            ((HDSEL) == UART_HALF_DUPLEX_ENABLE))\r\n\r\n#define IS_UART_REQUEST_PARAMETER(PARAM) (((PARAM) == UART_AUTOBAUD_REQUEST) || \\\r\n                                          ((PARAM) == UART_SENDBREAK_REQUEST) || \\\r\n                                          ((PARAM) == UART_MUTE_MODE_REQUEST) || \\\r\n                                          ((PARAM) == UART_RXDATA_FLUSH_REQUEST) || \\\r\n                                          ((PARAM) == UART_TXDATA_FLUSH_REQUEST))\r\n\r\n#define IS_UART_ADVFEATURE_INIT(INIT)           ((INIT) <= (UART_ADVFEATURE_NO_INIT | \\\r\n                                                            UART_ADVFEATURE_TXINVERT_INIT | \\\r\n                                                            UART_ADVFEATURE_RXINVERT_INIT | \\\r\n                                                            UART_ADVFEATURE_DATAINVERT_INIT | \\\r\n                                                            UART_ADVFEATURE_SWAP_INIT | \\\r\n                                                            UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \\\r\n                                                            UART_ADVFEATURE_DMADISABLEONERROR_INIT   | \\\r\n                                                            UART_ADVFEATURE_AUTOBAUDRATE_INIT | \\\r\n                                                            UART_ADVFEATURE_MSBFIRST_INIT))\r\n\r\n#define IS_UART_ADVFEATURE_TXINV(TXINV) (((TXINV) == UART_ADVFEATURE_TXINV_DISABLE) || \\\r\n                                         ((TXINV) == UART_ADVFEATURE_TXINV_ENABLE))\r\n\r\n#define IS_UART_ADVFEATURE_RXINV(RXINV) (((RXINV) == UART_ADVFEATURE_RXINV_DISABLE) || \\\r\n                                         ((RXINV) == UART_ADVFEATURE_RXINV_ENABLE))\r\n\r\n#define IS_UART_ADVFEATURE_DATAINV(DATAINV) (((DATAINV) == UART_ADVFEATURE_DATAINV_DISABLE) || \\\r\n                                             ((DATAINV) == UART_ADVFEATURE_DATAINV_ENABLE))\r\n\r\n#define IS_UART_ADVFEATURE_SWAP(SWAP) (((SWAP) == UART_ADVFEATURE_SWAP_DISABLE) || \\\r\n                                       ((SWAP) == UART_ADVFEATURE_SWAP_ENABLE))\r\n\r\n#define IS_UART_OVERRUN(OVERRUN)         (((OVERRUN) == UART_ADVFEATURE_OVERRUN_ENABLE) || \\\r\n                                          ((OVERRUN) == UART_ADVFEATURE_OVERRUN_DISABLE))\r\n\r\n#define IS_UART_ADVFEATURE_AUTOBAUDRATE(AUTOBAUDRATE)  (((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \\\r\n                                                        ((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))\r\n\r\n#define IS_UART_ADVFEATURE_DMAONRXERROR(DMA)      (((DMA) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \\\r\n                                                   ((DMA) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))\r\n\r\n#define IS_UART_ADVFEATURE_MSBFIRST(MSBFIRST) (((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \\\r\n                                               ((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_ENABLE))\r\n\r\n#define IS_UART_MUTE_MODE(MUTE)           (((MUTE) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \\\r\n                                           ((MUTE) == UART_ADVFEATURE_MUTEMODE_ENABLE))\r\n\r\n#define IS_UART_DE_POLARITY(POLARITY)    (((POLARITY) == UART_DE_POLARITY_HIGH) || \\\r\n                                          ((POLARITY) == UART_DE_POLARITY_LOW))\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Include UART HAL Extension module */\r\n#include \"stm32f7xx_hal_uart_ex.h\"\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup UART_Exported_Functions UART Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions\r\n  * @{\r\n  */\r\n\r\n/* Initialization and de-initialization functions  ****************************/\r\nHAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);\r\nHAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);\r\nHAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);\r\nHAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);\r\nHAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime);\r\nHAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);\r\nvoid HAL_UART_MspInit(UART_HandleTypeDef *huart);\r\nvoid HAL_UART_MspDeInit(UART_HandleTypeDef *huart);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup UART_Exported_Functions_Group2 IO operation functions\r\n  * @{\r\n  */\r\n\r\n/* IO operation functions *****************************************************/\r\nHAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);\r\nHAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);\r\nHAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);\r\n\r\nvoid HAL_UART_IRQHandler(UART_HandleTypeDef *huart);\r\nvoid HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);\r\nvoid HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);\r\nvoid HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);\r\nvoid HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);\r\nvoid HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions\r\n  * @{\r\n  */\r\n\r\n/* Peripheral Control functions  ************************************************/\r\nHAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);\r\nHAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);\r\nHAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);\r\nHAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);\r\nvoid HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);\r\nHAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);\r\nHAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions\r\n  * @{\r\n  */\r\n\r\n/* Peripheral State and Errors functions  **************************************************/\r\nHAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);\r\nuint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions -----------------------------------------------------------*/\r\n/** @addtogroup UART_Private_Functions UART Private Functions\r\n  * @{\r\n  */\r\n\r\nHAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);\r\nHAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);\r\nHAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);\r\nvoid UART_AdvFeatureConfig(UART_HandleTypeDef *huart);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_UART_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_uart_ex.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of UART HAL Extension module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************  \r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_UART_EX_H\r\n#define __STM32F7xx_HAL_UART_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup UARTEx\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup UARTEx_Word_Length UARTEx Word Length\r\n  * @{\r\n  */\r\n#define UART_WORDLENGTH_7B                  ((uint32_t)USART_CR1_M_1)\r\n#define UART_WORDLENGTH_8B                  ((uint32_t)0x0000U)\r\n#define UART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M_0)\r\n#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \\\r\n                                         ((__LENGTH__) == UART_WORDLENGTH_8B) || \\\r\n                                         ((__LENGTH__) == UART_WORDLENGTH_9B))\r\n#define IS_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B))\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t \r\n/**\r\n  * @}\r\n  */\r\n\r\n  \r\n/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length\r\n  * @{\r\n  */\r\n#define UART_ADDRESS_DETECT_4B                ((uint32_t)0x00000000U)\r\n#define UART_ADDRESS_DETECT_7B                ((uint32_t)USART_CR2_ADDM7)\r\n#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \\\r\n                                                   ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))\r\n/**\r\n  * @}\r\n  */  \r\n\r\n  \r\n/**\r\n  * @}\r\n  */  \r\n  \r\n/* Exported macro ------------------------------------------------------------*/\r\n\r\n/** @defgroup UARTEx_Exported_Macros UARTEx Exported Macros\r\n  * @{\r\n  */\r\n           \r\n/** @brief  Reports the UART clock source.\r\n  * @param  __HANDLE__: specifies the UART Handle\r\n  * @param  __CLOCKSOURCE__: output variable   \r\n  * @retval UART clocking source, written in __CLOCKSOURCE__.\r\n  */\r\n#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \\\r\n  do {                                                        \\\r\n    if((__HANDLE__)->Instance == USART1)                      \\\r\n    {                                                         \\\r\n       switch(__HAL_RCC_GET_USART1_SOURCE())                  \\\r\n       {                                                      \\\r\n        case RCC_USART1CLKSOURCE_PCLK2:                       \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \\\r\n          break;                                              \\\r\n        case RCC_USART1CLKSOURCE_HSI:                         \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\\r\n          break;                                              \\\r\n        case RCC_USART1CLKSOURCE_SYSCLK:                      \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                              \\\r\n        case RCC_USART1CLKSOURCE_LSE:                         \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\\r\n          break;                                              \\\r\n        default:                                              \\\r\n          break;                                              \\\r\n       }                                                      \\\r\n    }                                                         \\\r\n    else if((__HANDLE__)->Instance == USART2)                 \\\r\n    {                                                         \\\r\n       switch(__HAL_RCC_GET_USART2_SOURCE())                  \\\r\n       {                                                      \\\r\n        case RCC_USART2CLKSOURCE_PCLK1:                       \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\\r\n          break;                                              \\\r\n        case RCC_USART2CLKSOURCE_HSI:                         \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\\r\n          break;                                              \\\r\n        case RCC_USART2CLKSOURCE_SYSCLK:                      \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                              \\\r\n        case RCC_USART2CLKSOURCE_LSE:                         \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\\r\n          break;                                              \\\r\n        default:                                              \\\r\n          break;                                              \\\r\n       }                                                      \\\r\n    }                                                         \\\r\n    else if((__HANDLE__)->Instance == USART3)                 \\\r\n    {                                                         \\\r\n       switch(__HAL_RCC_GET_USART3_SOURCE())                  \\\r\n       {                                                      \\\r\n        case RCC_USART3CLKSOURCE_PCLK1:                       \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\\r\n          break;                                              \\\r\n        case RCC_USART3CLKSOURCE_HSI:                         \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\\r\n          break;                                              \\\r\n        case RCC_USART3CLKSOURCE_SYSCLK:                      \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                              \\\r\n        case RCC_USART3CLKSOURCE_LSE:                         \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\\r\n          break;                                              \\\r\n        default:                                              \\\r\n          break;                                              \\\r\n       }                                                      \\\r\n    }                                                         \\\r\n    else if((__HANDLE__)->Instance == UART4)                  \\\r\n    {                                                         \\\r\n       switch(__HAL_RCC_GET_UART4_SOURCE())                   \\\r\n       {                                                      \\\r\n        case RCC_UART4CLKSOURCE_PCLK1:                        \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\\r\n          break;                                              \\\r\n        case RCC_UART4CLKSOURCE_HSI:                          \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\\r\n          break;                                              \\\r\n        case RCC_UART4CLKSOURCE_SYSCLK:                       \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                              \\\r\n        case RCC_UART4CLKSOURCE_LSE:                          \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\\r\n          break;                                              \\\r\n        default:                                              \\\r\n          break;                                              \\\r\n       }                                                      \\\r\n    }                                                         \\\r\n    else if ((__HANDLE__)->Instance == UART5)                 \\\r\n    {                                                         \\\r\n       switch(__HAL_RCC_GET_UART5_SOURCE())                   \\\r\n       {                                                      \\\r\n        case RCC_UART5CLKSOURCE_PCLK1:                        \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\\r\n          break;                                              \\\r\n        case RCC_UART5CLKSOURCE_HSI:                          \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\\r\n          break;                                              \\\r\n        case RCC_UART5CLKSOURCE_SYSCLK:                       \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                              \\\r\n        case RCC_UART5CLKSOURCE_LSE:                          \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\\r\n          break;                                              \\\r\n        default:                                              \\\r\n          break;                                              \\\r\n       }                                                      \\\r\n    }                                                         \\\r\n    else if((__HANDLE__)->Instance == USART6)                 \\\r\n    {                                                         \\\r\n       switch(__HAL_RCC_GET_USART6_SOURCE())                  \\\r\n       {                                                      \\\r\n        case RCC_USART6CLKSOURCE_PCLK2:                       \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \\\r\n          break;                                              \\\r\n        case RCC_USART6CLKSOURCE_HSI:                         \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\\r\n          break;                                              \\\r\n        case RCC_USART6CLKSOURCE_SYSCLK:                      \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                              \\\r\n        case RCC_USART6CLKSOURCE_LSE:                         \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\\r\n          break;                                              \\\r\n        default:                                              \\\r\n          break;                                              \\\r\n       }                                                      \\\r\n    }                                                         \\\r\n    else if ((__HANDLE__)->Instance == UART7)                 \\\r\n    {                                                         \\\r\n       switch(__HAL_RCC_GET_UART7_SOURCE())                   \\\r\n       {                                                      \\\r\n        case RCC_UART7CLKSOURCE_PCLK1:                        \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\\r\n          break;                                              \\\r\n        case RCC_UART7CLKSOURCE_HSI:                          \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\\r\n          break;                                              \\\r\n        case RCC_UART7CLKSOURCE_SYSCLK:                       \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                              \\\r\n        case RCC_UART7CLKSOURCE_LSE:                          \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\\r\n          break;                                              \\\r\n        default:                                              \\\r\n          break;                                              \\\r\n       }                                                      \\\r\n    } \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n    else if ((__HANDLE__)->Instance == UART8)                 \\\r\n    {                                                         \\\r\n       switch(__HAL_RCC_GET_UART8_SOURCE())                   \\\r\n       {                                                      \\\r\n        case RCC_UART8CLKSOURCE_PCLK1:                        \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \\\r\n          break;                                              \\\r\n        case RCC_UART8CLKSOURCE_HSI:                          \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \\\r\n          break;                                              \\\r\n        case RCC_UART8CLKSOURCE_SYSCLK:                       \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                              \\\r\n        case RCC_UART8CLKSOURCE_LSE:                          \\\r\n          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \\\r\n          break;                                              \\\r\n        default:                                              \\\r\n          break;                                              \\\r\n       }                                                      \\\r\n    } \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\r\n  } while(0)\r\n\r\n/** @brief  Reports the UART mask to apply to retrieve the received data\r\n  *         according to the word length and to the parity bits activation.\r\n  *         If PCE = 1, the parity bit is not included in the data extracted\r\n  *         by the reception API().\r\n  *         This masking operation is not carried out in the case of\r\n  *         DMA transfers.        \r\n  * @param  __HANDLE__: specifies the UART Handle\r\n  * @retval mask to apply to UART RDR register value.\r\n  */\r\n#define UART_MASK_COMPUTATION(__HANDLE__)                       \\\r\n  do {                                                                \\\r\n  if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B)            \\\r\n  {                                                                   \\\r\n     if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x01FF ;                                 \\\r\n     }                                                                \\\r\n     else                                                             \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x00FF ;                                 \\\r\n     }                                                                \\\r\n  }                                                                   \\\r\n  else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B)       \\\r\n  {                                                                   \\\r\n     if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x00FF ;                                 \\\r\n     }                                                                \\\r\n     else                                                             \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x007F ;                                 \\\r\n     }                                                                \\\r\n  }                                                                   \\\r\n  else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B)       \\\r\n  {                                                                   \\\r\n     if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x007F ;                                 \\\r\n     }                                                                \\\r\n     else                                                             \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x003F ;                                 \\\r\n     }                                                                \\\r\n  }                                                                   \\\r\n} while(0)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @addtogroup UARTEx_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup UARTEx_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n\r\n/* Initialization and de-initialization functions  ****************************/\r\nHAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime);\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @addtogroup UARTEx_Exported_Functions_Group3\r\n  * @{\r\n  */\r\n\r\n/* Peripheral Control functions  **********************************************/\r\nHAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_UART_EX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_usart.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_usart.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of USART HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_USART_H\r\n#define __STM32F7xx_HAL_USART_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup USART\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/** @defgroup USART_Exported_Types USART Exported Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief USART Init Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t BaudRate;                  /*!< This member configures the Usart communication baud rate.\r\n                                           The baud rate is computed using the following formula:\r\n                                              Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate))) */\r\n\r\n  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.\r\n                                           This parameter can be a value of @ref USARTEx_Word_Length */\r\n\r\n  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.\r\n                                           This parameter can be a value of @ref USART_Stop_Bits */\r\n\r\n  uint32_t Parity;                   /*!< Specifies the parity mode.\r\n                                           This parameter can be a value of @ref USART_Parity\r\n                                           @note When parity is enabled, the computed parity is inserted\r\n                                                 at the MSB position of the transmitted data (9th bit when\r\n                                                 the word length is set to 9 data bits; 8th bit when the\r\n                                                 word length is set to 8 data bits). */\r\n\r\n  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.\r\n                                           This parameter can be a value of @ref USART_Mode */\r\n\r\n  uint32_t OverSampling;              /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).\r\n                                           This parameter can be a value of @ref USART_Over_Sampling */                                                                                        \r\n\r\n  uint32_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.\r\n                                           This parameter can be a value of @ref USART_Clock_Polarity */\r\n\r\n  uint32_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.\r\n                                           This parameter can be a value of @ref USART_Clock_Phase */\r\n\r\n  uint32_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted\r\n                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.\r\n                                           This parameter can be a value of @ref USART_Last_Bit */\r\n}USART_InitTypeDef;\r\n\r\n/**\r\n  * @brief HAL USART State structures definition\r\n  */\r\ntypedef enum\r\n{\r\n  HAL_USART_STATE_RESET             = 0x00U,    /*!< Peripheral is not initialized   */\r\n  HAL_USART_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use */\r\n  HAL_USART_STATE_BUSY              = 0x02U,    /*!< an internal process is ongoing */\r\n  HAL_USART_STATE_BUSY_TX           = 0x12U,    /*!< Data Transmission process is ongoing */\r\n  HAL_USART_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing */\r\n  HAL_USART_STATE_BUSY_TX_RX        = 0x32U,    /*!< Data Transmission Reception process is ongoing */\r\n  HAL_USART_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state */\r\n  HAL_USART_STATE_ERROR             = 0x04U     /*!< Error */\r\n}HAL_USART_StateTypeDef;\r\n\r\n\r\n/**\r\n  * @brief  USART clock sources definitions\r\n  */\r\ntypedef enum\r\n{\r\n  USART_CLOCKSOURCE_PCLK1      = 0x00U,    /*!< PCLK1 clock source  */\r\n  USART_CLOCKSOURCE_PCLK2      = 0x01U,    /*!< PCLK2 clock source  */\r\n  USART_CLOCKSOURCE_HSI        = 0x02U,    /*!< HSI clock source    */\r\n  USART_CLOCKSOURCE_SYSCLK     = 0x04U,    /*!< SYSCLK clock source */\r\n  USART_CLOCKSOURCE_LSE        = 0x08U,    /*!< LSE clock source       */\r\n  USART_CLOCKSOURCE_UNDEFINED  = 0x10U     /*!< Undefined clock source */\r\n}USART_ClockSourceTypeDef;\r\n\r\n\r\n/**\r\n  * @brief  USART handle Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  USART_TypeDef                 *Instance;        /*!<  USART registers base address        */\r\n\r\n  USART_InitTypeDef             Init;             /*!< USART communication parameters      */\r\n\r\n  uint8_t                       *pTxBuffPtr;      /*!< Pointer to USART Tx transfer Buffer */\r\n\r\n  uint16_t                      TxXferSize;       /*!< USART Tx Transfer size              */\r\n\r\n  uint16_t                      TxXferCount;      /*!< USART Tx Transfer Counter           */\r\n\r\n  uint8_t                       *pRxBuffPtr;      /*!< Pointer to USART Rx transfer Buffer */\r\n\r\n  uint16_t                      RxXferSize;       /*!< USART Rx Transfer size              */\r\n\r\n  uint16_t                      RxXferCount;      /*!< USART Rx Transfer Counter           */\r\n\r\n  uint16_t                      Mask;             /*!< USART Rx RDR register mask          */\r\n\r\n  DMA_HandleTypeDef             *hdmatx;          /*!< USART Tx DMA Handle parameters      */\r\n\r\n  DMA_HandleTypeDef             *hdmarx;          /*!< USART Rx DMA Handle parameters      */\r\n\r\n  HAL_LockTypeDef               Lock;            /*!<  Locking object                      */\r\n\r\n  HAL_USART_StateTypeDef        State;           /*!< USART communication state           */\r\n\r\n  __IO uint32_t                 ErrorCode;       /*!< USART Error code                    */\r\n\r\n}USART_HandleTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup USART_Exported_Constants USART Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup USART_Error_Code USART Error Code\r\n  * @brief    USART Error Code \r\n  * @{\r\n  */ \r\n#define HAL_USART_ERROR_NONE         ((uint32_t)0x00000000U)   /*!< No error            */\r\n#define HAL_USART_ERROR_PE           ((uint32_t)0x00000001U)   /*!< Parity error        */\r\n#define HAL_USART_ERROR_NE           ((uint32_t)0x00000002U)   /*!< Noise error         */\r\n#define HAL_USART_ERROR_FE           ((uint32_t)0x00000004U)   /*!< Frame error         */\r\n#define HAL_USART_ERROR_ORE          ((uint32_t)0x00000008U)   /*!< Overrun error       */\r\n#define HAL_USART_ERROR_DMA          ((uint32_t)0x00000010U)   /*!< DMA transfer error  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USART_Stop_Bits  USART Number of Stop Bits\r\n  * @{\r\n  */\r\n#define USART_STOPBITS_1                     ((uint32_t)0x0000U)\r\n#define USART_STOPBITS_2                     ((uint32_t)USART_CR2_STOP_1)\r\n#define USART_STOPBITS_1_5                   ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USART_Parity    USART Parity\r\n  * @{\r\n  */\r\n#define USART_PARITY_NONE                   ((uint32_t)0x0000U)\r\n#define USART_PARITY_EVEN                   ((uint32_t)USART_CR1_PCE)\r\n#define USART_PARITY_ODD                    ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USART_Mode   USART Mode\r\n  * @{\r\n  */\r\n#define USART_MODE_RX                       ((uint32_t)USART_CR1_RE)\r\n#define USART_MODE_TX                       ((uint32_t)USART_CR1_TE)\r\n#define USART_MODE_TX_RX                    ((uint32_t)(USART_CR1_TE |USART_CR1_RE))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USART_Over_Sampling USART Over Sampling\r\n  * @{\r\n  */\r\n#define USART_OVERSAMPLING_16               ((uint32_t)0x0000U)\r\n#define USART_OVERSAMPLING_8                ((uint32_t)USART_CR1_OVER8)\r\n/**\r\n  * @}\r\n  */\r\n/** @defgroup USART_Clock  USART Clock\r\n  * @{\r\n  */\r\n#define USART_CLOCK_DISABLE                 ((uint32_t)0x0000U)\r\n#define USART_CLOCK_ENABLE                  ((uint32_t)USART_CR2_CLKEN)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USART_Clock_Polarity  USART Clock Polarity\r\n  * @{\r\n  */\r\n#define USART_POLARITY_LOW                  ((uint32_t)0x0000U)\r\n#define USART_POLARITY_HIGH                 ((uint32_t)USART_CR2_CPOL)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USART_Clock_Phase   USART Clock Phase\r\n  * @{\r\n  */\r\n#define USART_PHASE_1EDGE                   ((uint32_t)0x0000U)\r\n#define USART_PHASE_2EDGE                   ((uint32_t)USART_CR2_CPHA)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USART_Last_Bit  USART Last Bit\r\n  * @{\r\n  */\r\n#define USART_LASTBIT_DISABLE               ((uint32_t)0x0000U)\r\n#define USART_LASTBIT_ENABLE                ((uint32_t)USART_CR2_LBCL)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USART_Request_Parameters  USART Request Parameters\r\n  * @{\r\n  */\r\n#define USART_RXDATA_FLUSH_REQUEST        ((uint32_t)USART_RQR_RXFRQ)        /*!< Receive Data flush Request */ \r\n#define USART_TXDATA_FLUSH_REQUEST        ((uint32_t)USART_RQR_TXFRQ)        /*!< Transmit data flush Request */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USART_Flags      USART Flags\r\n  *        Elements values convention: 0xXXXX\r\n  *           - 0xXXXX  : Flag mask in the ISR register\r\n  * @{\r\n  */\r\n#define USART_FLAG_REACK                     ((uint32_t)0x00400000U)\r\n#define USART_FLAG_TEACK                     ((uint32_t)0x00200000U)  \r\n#define USART_FLAG_BUSY                      ((uint32_t)0x00010000U)\r\n#define USART_FLAG_CTS                       ((uint32_t)0x00000400U)\r\n#define USART_FLAG_CTSIF                     ((uint32_t)0x00000200U)\r\n#define USART_FLAG_LBDF                      ((uint32_t)0x00000100U)\r\n#define USART_FLAG_TXE                       ((uint32_t)0x00000080U)\r\n#define USART_FLAG_TC                        ((uint32_t)0x00000040U)\r\n#define USART_FLAG_RXNE                      ((uint32_t)0x00000020U)\r\n#define USART_FLAG_IDLE                      ((uint32_t)0x00000010U)\r\n#define USART_FLAG_ORE                       ((uint32_t)0x00000008U)\r\n#define USART_FLAG_NE                        ((uint32_t)0x00000004U)\r\n#define USART_FLAG_FE                        ((uint32_t)0x00000002U)\r\n#define USART_FLAG_PE                        ((uint32_t)0x00000001U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USART_Interrupt_definition USART Interrupts Definition\r\n  *        Elements values convention: 0000ZZZZ0XXYYYYYb\r\n  *           - YYYYY  : Interrupt source position in the XX register (5bits)\r\n  *           - XX  : Interrupt source register (2bits)\r\n  *                 - 01: CR1 register\r\n  *                 - 10: CR2 register\r\n  *                 - 11: CR3 register\r\n  *           - ZZZZ  : Flag position in the ISR register(4bits)\r\n  * @{\r\n  */\r\n\r\n#define USART_IT_PE                          ((uint16_t)0x0028U)\r\n#define USART_IT_TXE                         ((uint16_t)0x0727U)\r\n#define USART_IT_TC                          ((uint16_t)0x0626U)\r\n#define USART_IT_RXNE                        ((uint16_t)0x0525U)\r\n#define USART_IT_IDLE                        ((uint16_t)0x0424U)\r\n#define USART_IT_ERR                         ((uint16_t)0x0060U)\r\n\r\n#define USART_IT_ORE                         ((uint16_t)0x0300U)\r\n#define USART_IT_NE                          ((uint16_t)0x0200U)\r\n#define USART_IT_FE                          ((uint16_t)0x0100U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USART_IT_CLEAR_Flags    USART Interruption Clear Flags\r\n  * @{\r\n  */\r\n#define USART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag */\r\n#define USART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag */\r\n#define USART_CLEAR_NEF                       USART_ICR_NCF             /*!< Noise detected Clear Flag */\r\n#define USART_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag */\r\n#define USART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag */\r\n#define USART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag */\r\n#define USART_CLEAR_CTSF                      USART_ICR_CTSCF           /*!< CTS Interrupt Clear Flag */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported macros -----------------------------------------------------------*/\r\n/** @defgroup USART_Exported_Macros USART Exported Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief Reset USART handle state\r\n  * @param  __HANDLE__: USART handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)  ((__HANDLE__)->State = HAL_USART_STATE_RESET)\r\n\r\n/** @brief  Checks whether the specified USART flag is set or not.\r\n  * @param  __HANDLE__: specifies the USART Handle\r\n  * @param  __FLAG__: specifies the flag to check.\r\n  *        This parameter can be one of the following values:\r\n  *            @arg USART_FLAG_REACK: Receive enable acknowledge flag\r\n  *            @arg USART_FLAG_TEACK: Transmit enable acknowledge flag\r\n  *            @arg USART_FLAG_BUSY:  Busy flag\r\n  *            @arg USART_FLAG_CTS:   CTS Change flag\r\n  *            @arg USART_FLAG_TXE:   Transmit data register empty flag\r\n  *            @arg USART_FLAG_TC:    Transmission Complete flag\r\n  *            @arg USART_FLAG_RXNE:  Receive data register not empty flag\r\n  *            @arg USART_FLAG_IDLE:  Idle Line detection flag\r\n  *            @arg USART_FLAG_ORE:   OverRun Error flag\r\n  *            @arg USART_FLAG_NE:    Noise Error flag\r\n  *            @arg USART_FLAG_FE:    Framing Error flag\r\n  *            @arg USART_FLAG_PE:    Parity Error flag\r\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))\r\n\r\n\r\n/** @brief  Enables the specified USART interrupt.\r\n  * @param  __HANDLE__: specifies the USART Handle\r\n  * @param  __INTERRUPT__: specifies the USART interrupt source to enable.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg USART_IT_TXE:  Transmit Data Register empty interrupt\r\n  *            @arg USART_IT_TC:   Transmission complete interrupt\r\n  *            @arg USART_IT_RXNE: Receive Data register not empty interrupt\r\n  *            @arg USART_IT_IDLE: Idle line detection interrupt\r\n  *            @arg USART_IT_PE:   Parity Error interrupt\r\n  *            @arg USART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)\r\n  * @retval None\r\n  */\r\n#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \\\r\n                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \\\r\n                                                            ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))\r\n\r\n/** @brief  Disables the specified USART interrupt.\r\n  * @param  __HANDLE__: specifies the USART Handle.\r\n  * @param  __INTERRUPT__: specifies the USART interrupt source to disable.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg USART_IT_TXE:  Transmit Data Register empty interrupt\r\n  *            @arg USART_IT_TC:   Transmission complete interrupt\r\n  *            @arg USART_IT_RXNE: Receive Data register not empty interrupt\r\n  *            @arg USART_IT_IDLE: Idle line detection interrupt\r\n  *            @arg USART_IT_PE:   Parity Error interrupt\r\n  *            @arg USART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)\r\n  * @retval None\r\n  */\r\n#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \\\r\n                                                            ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \\\r\n                                                            ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))\r\n\r\n\r\n/** @brief  Checks whether the specified USART interrupt has occurred or not.\r\n  * @param  __HANDLE__: specifies the USART Handle\r\n  * @param  __IT__: specifies the USART interrupt source to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg USART_IT_TXE: Transmit Data Register empty interrupt\r\n  *            @arg USART_IT_TC:  Transmission complete interrupt\r\n  *            @arg USART_IT_RXNE: Receive Data register not empty interrupt\r\n  *            @arg USART_IT_IDLE: Idle line detection interrupt\r\n  *            @arg USART_IT_ORE: OverRun Error interrupt\r\n  *            @arg USART_IT_NE: Noise Error interrupt\r\n  *            @arg USART_IT_FE: Framing Error interrupt\r\n  *            @arg USART_IT_PE: Parity Error interrupt\r\n  * @retval The new state of __IT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))\r\n\r\n/** @brief  Checks whether the specified USART interrupt source is enabled.\r\n  * @param  __HANDLE__: specifies the USART Handle.\r\n  * @param  __IT__: specifies the USART interrupt source to check.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg USART_IT_TXE: Transmit Data Register empty interrupt\r\n  *            @arg USART_IT_TC:  Transmission complete interrupt\r\n  *            @arg USART_IT_RXNE: Receive Data register not empty interrupt\r\n  *            @arg USART_IT_IDLE: Idle line detection interrupt\r\n  *            @arg USART_IT_ORE: OverRun Error interrupt\r\n  *            @arg USART_IT_NE: Noise Error interrupt\r\n  *            @arg USART_IT_FE: Framing Error interrupt\r\n  *            @arg USART_IT_PE: Parity Error interrupt\r\n  * @retval The new state of __IT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \\\r\n                                                   (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << \\\r\n                                                   (((uint16_t)(__IT__)) & USART_IT_MASK)))\r\n\r\n\r\n/** @brief  Clears the specified USART ISR flag, in setting the proper ICR register flag.\r\n  * @param  __HANDLE__: specifies the USART Handle.\r\n  * @param  __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set\r\n  *                       to clear the corresponding interrupt\r\n  *          This parameter can be one of the following values:\r\n  *            @arg USART_CLEAR_PEF: Parity Error Clear Flag\r\n  *            @arg USART_CLEAR_FEF: Framing Error Clear Flag\r\n  *            @arg USART_CLEAR_NEF: Noise detected Clear Flag\r\n  *            @arg USART_CLEAR_OREF: OverRun Error Clear Flag\r\n  *            @arg USART_CLEAR_IDLEF: IDLE line detected Clear Flag\r\n  *            @arg USART_CLEAR_TCF: Transmission Complete Clear Flag\r\n  *            @arg USART_CLEAR_CTSF: CTS Interrupt Clear Flag\r\n  * @retval None\r\n  */\r\n#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))\r\n\r\n/** @brief  Set a specific USART request flag.\r\n  * @param  __HANDLE__: specifies the USART Handle.\r\n  * @param  __REQ__: specifies the request flag to set\r\n  *          This parameter can be one of the following values:\r\n  *            @arg USART_RXDATA_FLUSH_REQUEST: Receive Data flush Request\r\n  *            @arg USART_TXDATA_FLUSH_REQUEST: Transmit data flush Request\r\n  *\r\n  * @retval None\r\n  */\r\n#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) \r\n\r\n/** @brief  Enable USART\r\n  * @param  __HANDLE__: specifies the USART Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_USART_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)\r\n\r\n/** @brief  Disable USART\r\n  * @param  __HANDLE__: specifies the USART Handle.\r\n  * @retval None\r\n  */\r\n#define __HAL_USART_DISABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Include UART HAL Extension module */\r\n#include \"stm32f7xx_hal_usart_ex.h\"\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup USART_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup USART_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n/* Initialization/de-initialization functions  **********************************/\r\nHAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);\r\nHAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);\r\nvoid HAL_USART_MspInit(USART_HandleTypeDef *husart);\r\nvoid HAL_USART_MspDeInit(USART_HandleTypeDef *husart);\r\nHAL_StatusTypeDef HAL_USART_CheckIdleState(USART_HandleTypeDef *husart);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup USART_Exported_Functions_Group2\r\n  * @{\r\n  */\r\n/* IO operation functions *******************************************************/\r\nHAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);\r\nHAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,  uint16_t Size);\r\nHAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);\r\nHAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);\r\nHAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);\r\nHAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);\r\nvoid HAL_USART_IRQHandler(USART_HandleTypeDef *husart);\r\nvoid HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);\r\nvoid HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);\r\nvoid HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);\r\nvoid HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);\r\nvoid HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);\r\nvoid HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @addtogroup USART_Exported_Functions_Group3\r\n  * @{\r\n  */\r\n/* Peripheral State functions  ************************************************/\r\nHAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);\r\nuint32_t               HAL_USART_GetError(USART_HandleTypeDef *husart);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @defgroup USART_Private_Constants USART Private Constants\r\n  * @{\r\n  */\r\n/** @brief USART interruptions flag mask\r\n  * \r\n  */ \r\n#define USART_IT_MASK                             ((uint16_t)0x001FU)\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup USART_Private_Macros USART Private Macros\r\n  * @{\r\n  */\r\n/** @brief  Reports the USART clock source.\r\n  * @param  __HANDLE__: specifies the USART Handle\r\n  * @param  __CLOCKSOURCE__ : output variable\r\n  * @retval the USART clocking source, written in __CLOCKSOURCE__.\r\n  */\r\n#define USART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)\\\r\n  do {                                                         \\\r\n    if((__HANDLE__)->Instance == USART1)                       \\\r\n    {                                                          \\\r\n       switch(__HAL_RCC_GET_USART1_SOURCE())                   \\\r\n       {                                                       \\\r\n        case RCC_USART1CLKSOURCE_PCLK2:                        \\\r\n          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2;         \\\r\n          break;                                               \\\r\n        case RCC_USART1CLKSOURCE_HSI:                          \\\r\n          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \\\r\n          break;                                               \\\r\n        case RCC_USART1CLKSOURCE_SYSCLK:                       \\\r\n          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                               \\\r\n        case RCC_USART1CLKSOURCE_LSE:                          \\\r\n          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \\\r\n          break;                                               \\\r\n        default:                                               \\\r\n          break;                                               \\\r\n       }                                                       \\\r\n    }                                                          \\\r\n    else if((__HANDLE__)->Instance == USART2)                  \\\r\n    {                                                          \\\r\n       switch(__HAL_RCC_GET_USART2_SOURCE())                   \\\r\n       {                                                       \\\r\n        case RCC_USART2CLKSOURCE_PCLK1:                        \\\r\n          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;         \\\r\n          break;                                               \\\r\n        case RCC_USART2CLKSOURCE_HSI:                          \\\r\n          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \\\r\n          break;                                               \\\r\n        case RCC_USART2CLKSOURCE_SYSCLK:                       \\\r\n          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                               \\\r\n        case RCC_USART2CLKSOURCE_LSE:                          \\\r\n          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \\\r\n          break;                                               \\\r\n        default:                                               \\\r\n          break;                                               \\\r\n       }                                                       \\\r\n    }                                                          \\\r\n    else if((__HANDLE__)->Instance == USART3)                  \\\r\n    {                                                          \\\r\n       switch(__HAL_RCC_GET_USART3_SOURCE())                   \\\r\n       {                                                       \\\r\n        case RCC_USART3CLKSOURCE_PCLK1:                        \\\r\n          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1;         \\\r\n          break;                                               \\\r\n        case RCC_USART3CLKSOURCE_HSI:                          \\\r\n          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \\\r\n          break;                                               \\\r\n        case RCC_USART3CLKSOURCE_SYSCLK:                       \\\r\n          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                               \\\r\n        case RCC_USART3CLKSOURCE_LSE:                          \\\r\n          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \\\r\n          break;                                               \\\r\n        default:                                               \\\r\n          break;                                               \\\r\n       }                                                       \\\r\n    }                                                          \\\r\n    else if((__HANDLE__)->Instance == USART6)                  \\\r\n    {                                                          \\\r\n       switch(__HAL_RCC_GET_USART6_SOURCE())                   \\\r\n       {                                                       \\\r\n        case RCC_USART6CLKSOURCE_PCLK2:                        \\\r\n          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2;         \\\r\n          break;                                               \\\r\n        case RCC_USART6CLKSOURCE_HSI:                          \\\r\n          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \\\r\n          break;                                               \\\r\n        case RCC_USART6CLKSOURCE_SYSCLK:                       \\\r\n          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK;        \\\r\n          break;                                               \\\r\n        case RCC_USART6CLKSOURCE_LSE:                          \\\r\n          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \\\r\n          break;                                               \\\r\n        default:                                               \\\r\n          break;                                               \\\r\n       }                                                       \\\r\n    }                                                          \\\r\n } while(0)\r\n  \r\n\r\n#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_1) || \\\r\n                                         ((__STOPBITS__) == USART_STOPBITS_1_5) || \\\r\n                                         ((__STOPBITS__) == USART_STOPBITS_2))\r\n#define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \\\r\n                                     ((__PARITY__) == USART_PARITY_EVEN) || \\\r\n                                     ((__PARITY__) == USART_PARITY_ODD))\r\n#define IS_USART_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFFFFFF3U) == 0x00U) && ((__MODE__) != (uint32_t)0x00U))\r\n#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \\\r\n                                             ((__SAMPLING__) == USART_OVERSAMPLING_8))\r\n#define IS_USART_CLOCK(__CLOCK__)     (((__CLOCK__)== USART_CLOCK_DISABLE) || \\\r\n                                       ((__CLOCK__)== USART_CLOCK_ENABLE))\r\n#define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))\r\n#define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))\r\n#define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \\\r\n                                       ((__LASTBIT__) == USART_LASTBIT_ENABLE))\r\n#define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \\\r\n                                               ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))   \r\n#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup USART_Private_Functions USART Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_USART_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_usart_ex.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_usart_ex.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of USART HAL Extension module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_USART_EX_H\r\n#define __STM32F7xx_HAL_USART_EX_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup USARTEx\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup USARTEx_Word_Length USARTEx Word Length\r\n  * @{\r\n  */\r\n#define USART_WORDLENGTH_7B                  ((uint32_t)USART_CR1_M_1)\r\n#define USART_WORDLENGTH_8B                  ((uint32_t)0x00000000U)\r\n#define USART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M_0)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup USARTEx_Private_Macros USARTEx Private Macros\r\n  * @{\r\n  */\r\n\r\n/** @brief  Computes the USART mask to apply to retrieve the received data\r\n  *         according to the word length and to the parity bits activation.\r\n  *         If PCE = 1, the parity bit is not included in the data extracted\r\n  *         by the reception API().\r\n  *         This masking operation is not carried out in the case of\r\n  *         DMA transfers.\r\n  * @param  __HANDLE__: specifies the USART Handle\r\n  * @retval none\r\n  */\r\n#define __HAL_USART_MASK_COMPUTATION(__HANDLE__)                      \\\r\n  do {                                                                \\\r\n  if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B)           \\\r\n  {                                                                   \\\r\n     if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)              \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x01FF ;                                 \\\r\n     }                                                                \\\r\n     else                                                             \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x00FF ;                                 \\\r\n     }                                                                \\\r\n  }                                                                   \\\r\n  else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B)      \\\r\n  {                                                                   \\\r\n     if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)              \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x00FF ;                                 \\\r\n     }                                                                \\\r\n     else                                                             \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x007F ;                                 \\\r\n     }                                                                \\\r\n  }                                                                   \\\r\n  else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B)      \\\r\n  {                                                                   \\\r\n     if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)              \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x007F ;                                 \\\r\n     }                                                                \\\r\n     else                                                             \\\r\n     {                                                                \\\r\n        (__HANDLE__)->Mask = 0x003F ;                                 \\\r\n     }                                                                \\\r\n  }                                                                   \\\r\n} while(0)\r\n\r\n#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \\\r\n                                          ((__LENGTH__) == USART_WORDLENGTH_8B) || \\\r\n                                          ((__LENGTH__) == USART_WORDLENGTH_9B))                                 \r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/* Initialization/de-initialization methods  **********************************/\r\n/* IO operation methods *******************************************************/\r\n/* Peripheral Control methods  ************************************************/\r\n/* Peripheral State methods  **************************************************/\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_USART_EX_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_wwdg.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_wwdg.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of WWDG HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_HAL_WWDG_H\r\n#define __STM32F7xx_HAL_WWDG_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup WWDG\r\n  * @{\r\n  */\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n\r\n/** @defgroup WWDG_Exported_Types WWDG Exported Types\r\n  * @{\r\n  */\r\n\r\n/** \r\n  * @brief  WWDG Init structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t Prescaler;     /*!< Specifies the prescaler value of the WWDG.\r\n                               This parameter can be a value of @ref WWDG_Prescaler */\r\n\r\n  uint32_t Window;        /*!< Specifies the WWDG window value to be compared to the downcounter.\r\n                               This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */\r\n\r\n  uint32_t Counter;       /*!< Specifies the WWDG free-running downcounter  value.\r\n                               This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */\r\n\r\n  uint32_t EWIMode ;      /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.\r\n                               This parameter can be a value of @ref WWDG_EWI_Mode */\r\n\r\n}WWDG_InitTypeDef;\r\n\r\n/**\r\n  * @brief  WWDG handle Structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  WWDG_TypeDef                 *Instance;  /*!< Register base address    */\r\n\r\n  WWDG_InitTypeDef             Init;       /*!< WWDG required parameters */\r\n\r\n}WWDG_HandleTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup WWDG_Exported_Constants WWDG Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition\r\n  * @{\r\n  */\r\n#define WWDG_IT_EWI                         WWDG_CFR_EWI  /*!< Early wakeup interrupt */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup WWDG_Flag_definition WWDG Flag definition\r\n  * @brief WWDG Flag definition\r\n  * @{\r\n  */\r\n#define WWDG_FLAG_EWIF                      WWDG_SR_EWIF  /*!< Early wakeup interrupt flag */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup WWDG_Prescaler WWDG Prescaler\r\n  * @{\r\n  */\r\n#define WWDG_PRESCALER_1                    0x00000000U       /*!< WWDG counter clock = (PCLK1/4096)/1 */\r\n#define WWDG_PRESCALER_2                    WWDG_CFR_WDGTB_0  /*!< WWDG counter clock = (PCLK1/4096)/2 */\r\n#define WWDG_PRESCALER_4                    WWDG_CFR_WDGTB_1  /*!< WWDG counter clock = (PCLK1/4096)/4 */\r\n#define WWDG_PRESCALER_8                    WWDG_CFR_WDGTB    /*!< WWDG counter clock = (PCLK1/4096)/8 */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode\r\n  * @{\r\n  */\r\n#define WWDG_EWI_DISABLE                    0x00000000u       /*!< EWI Disable */\r\n#define WWDG_EWI_ENABLE                     WWDG_CFR_EWI      /*!< EWI Enable */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n\r\n/** @defgroup WWDG_Private_Macros WWDG Private Macros\r\n  * @{\r\n  */\r\n#define IS_WWDG_PRESCALER(__PRESCALER__)    (((__PRESCALER__) == WWDG_PRESCALER_1) || \\\r\n                                             ((__PRESCALER__) == WWDG_PRESCALER_2) || \\\r\n                                             ((__PRESCALER__) == WWDG_PRESCALER_4) || \\\r\n                                             ((__PRESCALER__) == WWDG_PRESCALER_8))\r\n\r\n#define IS_WWDG_WINDOW(__WINDOW__)          (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))\r\n\r\n#define IS_WWDG_COUNTER(__COUNTER__)        (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))\r\n\r\n#define IS_WWDG_EWI_MODE(__MODE__)          (((__MODE__) == WWDG_EWI_ENABLE) || \\\r\n                                             ((__MODE__) == WWDG_EWI_DISABLE))\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/* Exported macros ------------------------------------------------------------*/\r\n\r\n/** @defgroup WWDG_Exported_Macros WWDG Exported Macros\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Enable the WWDG peripheral.\r\n  * @param  __HANDLE__  WWDG handle\r\n  * @retval None\r\n  */\r\n#define __HAL_WWDG_ENABLE(__HANDLE__)                         SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)\r\n\r\n/**\r\n  * @brief  Enable the WWDG early wakeup interrupt.\r\n  * @param  __HANDLE__: WWDG handle\r\n  * @param  __INTERRUPT__  specifies the interrupt to enable.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg WWDG_IT_EWI: Early wakeup interrupt\r\n  * @note   Once enabled this interrupt cannot be disabled except by a system reset.\r\n  * @retval None\r\n  */\r\n#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__)       SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Check whether the selected WWDG interrupt has occurred or not.\r\n  * @param  __HANDLE__  WWDG handle\r\n  * @param  __INTERRUPT__  specifies the it to check.\r\n  *        This parameter can be one of the following values:\r\n  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT\r\n  * @retval The new state of WWDG_FLAG (SET or RESET).\r\n  */\r\n#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__)        __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))\r\n\r\n/** @brief  Clear the WWDG interrupt pending bits.\r\n  *         bits to clear the selected interrupt pending bits.\r\n  * @param  __HANDLE__  WWDG handle\r\n  * @param  __INTERRUPT__  specifies the interrupt pending bit to clear.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag\r\n  */\r\n#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__)      __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Check whether the specified WWDG flag is set or not.\r\n  * @param  __HANDLE__  WWDG handle\r\n  * @param  __FLAG__  specifies the flag to check.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag\r\n  * @retval The new state of WWDG_FLAG (SET or RESET).\r\n  */\r\n#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__)           (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))\r\n\r\n/**\r\n  * @brief  Clear the WWDG's pending flags.\r\n  * @param  __HANDLE__  WWDG handle\r\n  * @param  __FLAG__  specifies the flag to clear.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag\r\n  * @retval None\r\n  */\r\n#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->SR = ~(__FLAG__))\r\n\r\n/** @brief  Check whether the specified WWDG interrupt source is enabled or not.\r\n  * @param  __HANDLE__  WWDG Handle.\r\n  * @param  __INTERRUPT__  specifies the WWDG interrupt source to check.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg WWDG_IT_EWI: Early Wakeup Interrupt\r\n  * @retval state of __INTERRUPT__ (TRUE or FALSE).\r\n  */\r\n#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @addtogroup WWDG_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup WWDG_Exported_Functions_Group1\r\n  * @{\r\n  */\r\n/* Initialization/de-initialization functions  **********************************/\r\nHAL_StatusTypeDef     HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);\r\nvoid                  HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup WWDG_Exported_Functions_Group2\r\n  * @{\r\n  */\r\n/* I/O operation functions ******************************************************/\r\nHAL_StatusTypeDef     HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);\r\nvoid                  HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);\r\nvoid                  HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_HAL_WWDG_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_ll_fmc.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of FMC HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_LL_FMC_H\r\n#define __STM32F7xx_LL_FMC_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup FMC_LL\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup FMC_LL_Private_Macros\r\n  * @{\r\n  */\r\n#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \\\r\n                                   ((BANK) == FMC_NORSRAM_BANK2) || \\\r\n                                   ((BANK) == FMC_NORSRAM_BANK3) || \\\r\n                                   ((BANK) == FMC_NORSRAM_BANK4))\r\n\r\n#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \\\r\n                              ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))\r\n\r\n#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \\\r\n                                    ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \\\r\n                                    ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))\r\n\r\n#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8)  || \\\r\n                                                 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \\\r\n                                                 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))\r\n\r\n#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \\\r\n                                       ((__MODE__) == FMC_ACCESS_MODE_B) || \\\r\n                                       ((__MODE__) == FMC_ACCESS_MODE_C) || \\\r\n                                       ((__MODE__) == FMC_ACCESS_MODE_D))\r\n\r\n#define IS_FMC_NAND_BANK(BANK) ((BANK) == FMC_NAND_BANK3)\r\n\r\n#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_WAIT_FEATURE_DISABLE) || \\\r\n                                      ((FEATURE) == FMC_NAND_WAIT_FEATURE_ENABLE))\r\n\r\n#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_8) || \\\r\n                                         ((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_16))\r\n\r\n#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \\\r\n                                 ((STATE) == FMC_NAND_ECC_ENABLE))\r\n\r\n#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE)  || \\\r\n                                   ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE)  || \\\r\n                                   ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \\\r\n                                   ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \\\r\n                                   ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \\\r\n                                   ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))\r\n\t\t\t\t\t\t\t\t   \r\n#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8)  || \\\r\n                                      ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \\\r\n                                      ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))\r\n\r\n#define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \\\r\n                                            ((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))\t\t\t\t\t\t\t\t\t  \r\n\r\n#define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE)  || \\\r\n                                           ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \\\r\n                                           ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3))\r\n\t\t\t\t\t\t\t\t\t\t   \r\n#define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \\\r\n                                       ((__RBURST__) == FMC_SDRAM_RBURST_ENABLE))\r\n\t\t\t\t\t\t\t\t\t   \r\n#define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \\\r\n                                          ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \\\r\n                                          ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2))\r\n\r\n#define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE)      || \\\r\n                                          ((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE)       || \\\r\n                                          ((__COMMAND__) == FMC_SDRAM_CMD_PALL)             || \\\r\n                                          ((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \\\r\n                                          ((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE)        || \\\r\n                                          ((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \\\r\n                                          ((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE))\r\n\r\n#define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \\\r\n                                           ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \\\r\n                                           ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2)) \t\t\t\t\t\t\t\t\t\t  \r\n\t\t\t\t\t\t   \r\n/** @defgroup FMC_TCLR_Setup_Time FMC TCLR Setup Time\r\n  * @{\r\n  */\r\n#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_TAR_Setup_Time FMC TAR Setup Time \r\n  * @{\r\n  */\r\n#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_Setup_Time FMC Setup Time \r\n  * @{\r\n  */\r\n#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 254)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_Wait_Setup_Time FMC Wait Setup Time \r\n  * @{\r\n  */\r\n#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 254)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_Hold_Setup_Time FMC Hold Setup Time \r\n  * @{\r\n  */\r\n#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 254)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_HiZ_Setup_Time FMC HiZ Setup Time \r\n  * @{\r\n  */\r\n#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 254)\r\n/**\r\n  * @}\r\n  */\r\n\r\n#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \\\r\n                                      ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))\r\n\r\n#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \\\r\n                                             ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))\r\n\r\n#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \\\r\n                                                ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) \r\n\r\n#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \\\r\n                                                ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))\r\n\r\n#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \\\r\n                                          ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))\r\n\r\n#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \\\r\n                                         ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))\r\n\r\n#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \\\r\n                                     ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))\r\n\r\n/** @defgroup FMC_Data_Latency FMC Data Latency \r\n  * @{\r\n  */\r\n#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))\r\n/**\r\n  * @}\r\n  */\r\n\r\n#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \\\r\n                                        ((__BURST__) == FMC_WRITE_BURST_ENABLE))\r\n\r\n#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \\\r\n                                        ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))\r\n\r\n\r\n/** @defgroup FMC_Address_Setup_Time FMC Address Setup Time\r\n  * @{\r\n  */\r\n#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_Address_Hold_Time FMC Address Hold Time\r\n  * @{\r\n  */\r\n#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_Data_Setup_Time FMC Data Setup Time\r\n  * @{\r\n  */\r\n#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_Bus_Turn_around_Duration FMC Bus Turn around Duration\r\n  * @{\r\n  */\r\n#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_CLK_Division FMC CLK Division \r\n  * @{\r\n  */\r\n#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_SDRAM_LoadToActive_Delay FMC SDRAM LoadToActive Delay\r\n  * @{\r\n  */\r\n#define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup FMC_SDRAM_ExitSelfRefresh_Delay FMC SDRAM ExitSelfRefresh Delay\r\n  * @{\r\n  */\r\n#define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))\r\n/**\r\n  * @}\r\n  */ \r\n     \r\n/** @defgroup FMC_SDRAM_SelfRefresh_Time FMC SDRAM SelfRefresh Time\r\n  * @{\r\n  */  \r\n#define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16))\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup FMC_SDRAM_RowCycle_Delay FMC SDRAM RowCycle Delay\r\n  * @{\r\n  */  \r\n#define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))\r\n/**\r\n  * @}\r\n  */  \r\n  \r\n/** @defgroup FMC_SDRAM_Write_Recovery_Time FMC SDRAM Write Recovery Time\r\n  * @{\r\n  */  \r\n#define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16))\r\n/**\r\n  * @}\r\n  */         \r\n  \r\n/** @defgroup FMC_SDRAM_RP_Delay FMC SDRAM RP Delay\r\n  * @{\r\n  */  \r\n#define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/** @defgroup FMC_SDRAM_RCD_Delay FMC SDRAM RCD Delay\r\n  * @{\r\n  */  \r\n#define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup FMC_SDRAM_AutoRefresh_Number FMC SDRAM AutoRefresh Number\r\n  * @{\r\n  */  \r\n#define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0) && ((__NUMBER__) <= 16))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_SDRAM_ModeRegister_Definition FMC SDRAM ModeRegister Definition\r\n  * @{\r\n  */\r\n#define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_SDRAM_Refresh_rate FMC SDRAM Refresh rate\r\n  * @{\r\n  */\r\n#define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup FMC_NORSRAM_Device_Instance FMC NORSRAM Device Instance\r\n  * @{\r\n  */\r\n#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance FMC NORSRAM EXTENDED Device Instance\r\n  * @{\r\n  */\r\n#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance\r\n  * @{\r\n  */\r\n#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_SDRAM_Device_Instance FMC SDRAM Device Instance\r\n  * @{\r\n  */\r\n#define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE)\r\n/**\r\n  * @}\r\n  */\r\n\r\n#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \\\r\n                                 ((BANK) == FMC_SDRAM_BANK2))\r\n\r\n#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8)  || \\\r\n                                          ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9)  || \\\r\n                                          ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \\\r\n                                          ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))\r\n\r\n#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || \\\r\n                                    ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || \\\r\n                                    ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))\r\n\r\n#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \\\r\n                                            ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))\r\n\r\n\r\n#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \\\r\n                                     ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \\\r\n                                     ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))\r\n\r\n#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \\\r\n                                   ((__SIZE__) == FMC_PAGE_SIZE_128) || \\\r\n                                   ((__SIZE__) == FMC_PAGE_SIZE_256) || \\\r\n                                   ((__SIZE__) == FMC_PAGE_SIZE_512) || \\\r\n                                   ((__SIZE__) == FMC_PAGE_SIZE_1024))\r\n\r\n#define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \\\r\n                                     ((__FIFO__) == FMC_WRITE_FIFO_ENABLE))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported typedef ----------------------------------------------------------*/\r\n/** @defgroup FMC_Exported_typedef FMC Low Layer Exported Types\r\n  * @{\r\n  */\r\n#define FMC_NORSRAM_TypeDef            FMC_Bank1_TypeDef\r\n#define FMC_NORSRAM_EXTENDED_TypeDef   FMC_Bank1E_TypeDef\r\n#define FMC_NAND_TypeDef               FMC_Bank3_TypeDef\r\n#define FMC_SDRAM_TypeDef              FMC_Bank5_6_TypeDef\r\n\r\n#define FMC_NORSRAM_DEVICE             FMC_Bank1\r\n#define FMC_NORSRAM_EXTENDED_DEVICE    FMC_Bank1E\r\n#define FMC_NAND_DEVICE                FMC_Bank3\r\n#define FMC_SDRAM_DEVICE               FMC_Bank5_6\r\n\r\n/** \r\n  * @brief  FMC NORSRAM Configuration Structure definition\r\n  */ \r\ntypedef struct\r\n{\r\n  uint32_t NSBank;                       /*!< Specifies the NORSRAM memory device that will be used.\r\n                                              This parameter can be a value of @ref FMC_NORSRAM_Bank                     */\r\n\r\n  uint32_t DataAddressMux;               /*!< Specifies whether the address and data values are\r\n                                              multiplexed on the data bus or not. \r\n                                              This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing    */\r\n\r\n  uint32_t MemoryType;                   /*!< Specifies the type of external memory attached to\r\n                                              the corresponding memory device.\r\n                                              This parameter can be a value of @ref FMC_Memory_Type                      */\r\n\r\n  uint32_t MemoryDataWidth;              /*!< Specifies the external memory device width.\r\n                                              This parameter can be a value of @ref FMC_NORSRAM_Data_Width               */\r\n\r\n  uint32_t BurstAccessMode;              /*!< Enables or disables the burst access mode for Flash memory,\r\n                                              valid only with synchronous burst Flash memories.\r\n                                              This parameter can be a value of @ref FMC_Burst_Access_Mode                */\r\n\r\n  uint32_t WaitSignalPolarity;           /*!< Specifies the wait signal polarity, valid only when accessing\r\n                                              the Flash memory in burst mode.\r\n                                              This parameter can be a value of @ref FMC_Wait_Signal_Polarity             */\r\n\r\n  uint32_t WaitSignalActive;             /*!< Specifies if the wait signal is asserted by the memory one\r\n                                              clock cycle before the wait state or during the wait state,\r\n                                              valid only when accessing memories in burst mode. \r\n                                              This parameter can be a value of @ref FMC_Wait_Timing                      */\r\n\r\n  uint32_t WriteOperation;               /*!< Enables or disables the write operation in the selected device by the FMC. \r\n                                              This parameter can be a value of @ref FMC_Write_Operation                  */\r\n\r\n  uint32_t WaitSignal;                   /*!< Enables or disables the wait state insertion via wait\r\n                                              signal, valid for Flash memory access in burst mode. \r\n                                              This parameter can be a value of @ref FMC_Wait_Signal                      */\r\n\r\n  uint32_t ExtendedMode;                 /*!< Enables or disables the extended mode.\r\n                                              This parameter can be a value of @ref FMC_Extended_Mode                    */\r\n\r\n  uint32_t AsynchronousWait;             /*!< Enables or disables wait signal during asynchronous transfers,\r\n                                              valid only with asynchronous Flash memories.\r\n                                              This parameter can be a value of @ref FMC_AsynchronousWait                 */\r\n\r\n  uint32_t WriteBurst;                   /*!< Enables or disables the write burst operation.\r\n                                              This parameter can be a value of @ref FMC_Write_Burst                      */\r\n\r\n  uint32_t ContinuousClock;              /*!< Enables or disables the FMC clock output to external memory devices.\r\n                                              This parameter is only enabled through the FMC_BCR1 register, and don't care \r\n                                              through FMC_BCR2..4 registers.\r\n                                              This parameter can be a value of @ref FMC_Continous_Clock                  */\r\n\r\n  uint32_t WriteFifo;                    /*!< Enables or disables the write FIFO used by the FMC controller.\r\n                                              This parameter is only enabled through the FMC_BCR1 register, and don't care \r\n                                              through FMC_BCR2..4 registers.\r\n                                              This parameter can be a value of @ref FMC_Write_FIFO                      */\r\n\r\n  uint32_t PageSize;                     /*!< Specifies the memory page size.\r\n                                              This parameter can be a value of @ref FMC_Page_Size                        */\r\n\r\n}FMC_NORSRAM_InitTypeDef;\r\n\r\n/** \r\n  * @brief  FMC NORSRAM Timing parameters structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t AddressSetupTime;             /*!< Defines the number of HCLK cycles to configure\r\n                                              the duration of the address setup time. \r\n                                              This parameter can be a value between Min_Data = 0 and Max_Data = 15.\r\n                                              @note This parameter is not used with synchronous NOR Flash memories.      */\r\n\r\n  uint32_t AddressHoldTime;              /*!< Defines the number of HCLK cycles to configure\r\n                                              the duration of the address hold time.\r\n                                              This parameter can be a value between Min_Data = 1 and Max_Data = 15. \r\n                                              @note This parameter is not used with synchronous NOR Flash memories.      */\r\n\r\n  uint32_t DataSetupTime;                /*!< Defines the number of HCLK cycles to configure\r\n                                              the duration of the data setup time.\r\n                                              This parameter can be a value between Min_Data = 1 and Max_Data = 255.\r\n                                              @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed \r\n                                              NOR Flash memories.                                                        */\r\n\r\n  uint32_t BusTurnAroundDuration;        /*!< Defines the number of HCLK cycles to configure\r\n                                              the duration of the bus turnaround.\r\n                                              This parameter can be a value between Min_Data = 0 and Max_Data = 15.\r\n                                              @note This parameter is only used for multiplexed NOR Flash memories.      */\r\n\r\n  uint32_t CLKDivision;                  /*!< Defines the period of CLK clock output signal, expressed in number of \r\n                                              HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.\r\n                                              @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM \r\n                                              accesses.                                                                  */\r\n\r\n  uint32_t DataLatency;                  /*!< Defines the number of memory clock cycles to issue\r\n                                              to the memory before getting the first data.\r\n                                              The parameter value depends on the memory type as shown below:\r\n                                              - It must be set to 0 in case of a CRAM\r\n                                              - It is don't care in asynchronous NOR, SRAM or ROM accesses\r\n                                              - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories\r\n                                                with synchronous burst mode enable                                       */\r\n\r\n  uint32_t AccessMode;                   /*!< Specifies the asynchronous access mode. \r\n                                              This parameter can be a value of @ref FMC_Access_Mode                      */\r\n}FMC_NORSRAM_TimingTypeDef;\r\n\r\n/** \r\n  * @brief  FMC NAND Configuration Structure definition  \r\n  */ \r\ntypedef struct\r\n{\r\n  uint32_t NandBank;               /*!< Specifies the NAND memory device that will be used.\r\n                                        This parameter can be a value of @ref FMC_NAND_Bank                    */\r\n\r\n  uint32_t Waitfeature;            /*!< Enables or disables the Wait feature for the NAND Memory device.\r\n                                        This parameter can be any value of @ref FMC_Wait_feature               */\r\n\r\n  uint32_t MemoryDataWidth;        /*!< Specifies the external memory device width.\r\n                                        This parameter can be any value of @ref FMC_NAND_Data_Width            */\r\n\r\n  uint32_t EccComputation;         /*!< Enables or disables the ECC computation.\r\n                                        This parameter can be any value of @ref FMC_ECC                        */\r\n\r\n  uint32_t ECCPageSize;            /*!< Defines the page size for the extended ECC.\r\n                                        This parameter can be any value of @ref FMC_ECC_Page_Size              */\r\n\r\n  uint32_t TCLRSetupTime;          /*!< Defines the number of HCLK cycles to configure the\r\n                                        delay between CLE low and RE low.\r\n                                        This parameter can be a value between Min_Data = 0 and Max_Data = 255  */\r\n\r\n  uint32_t TARSetupTime;           /*!< Defines the number of HCLK cycles to configure the\r\n                                        delay between ALE low and RE low.\r\n                                        This parameter can be a number between Min_Data = 0 and Max_Data = 255 */\r\n}FMC_NAND_InitTypeDef;\r\n\r\n/** \r\n  * @brief  FMC NAND Timing parameters structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t SetupTime;            /*!< Defines the number of HCLK cycles to setup address before\r\n                                      the command assertion for NAND-Flash read or write access\r\n                                      to common/Attribute or I/O memory space (depending on\r\n                                      the memory space timing to be configured).\r\n                                      This parameter can be a value between Min_Data = 0 and Max_Data = 254    */\r\n\r\n  uint32_t WaitSetupTime;        /*!< Defines the minimum number of HCLK cycles to assert the\r\n                                      command for NAND-Flash read or write access to\r\n                                      common/Attribute or I/O memory space (depending on the\r\n                                      memory space timing to be configured). \r\n                                      This parameter can be a number between Min_Data = 0 and Max_Data = 254   */\r\n\r\n  uint32_t HoldSetupTime;        /*!< Defines the number of HCLK clock cycles to hold address\r\n                                      (and data for write access) after the command de-assertion\r\n                                      for NAND-Flash read or write access to common/Attribute\r\n                                      or I/O memory space (depending on the memory space timing\r\n                                      to be configured).\r\n                                      This parameter can be a number between Min_Data = 0 and Max_Data = 254   */\r\n\r\n  uint32_t HiZSetupTime;         /*!< Defines the number of HCLK clock cycles during which the\r\n                                      data bus is kept in HiZ after the start of a NAND-Flash\r\n                                      write access to common/Attribute or I/O memory space (depending\r\n                                      on the memory space timing to be configured).\r\n                                      This parameter can be a number between Min_Data = 0 and Max_Data = 254   */\r\n}FMC_NAND_PCC_TimingTypeDef;\r\n\r\n/** \r\n  * @brief  FMC SDRAM Configuration Structure definition  \r\n  */  \r\ntypedef struct\r\n{\r\n  uint32_t SDBank;                      /*!< Specifies the SDRAM memory device that will be used.\r\n                                             This parameter can be a value of @ref FMC_SDRAM_Bank                */\r\n\r\n  uint32_t ColumnBitsNumber;            /*!< Defines the number of bits of column address.\r\n                                             This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */\r\n\r\n  uint32_t RowBitsNumber;               /*!< Defines the number of bits of column address.\r\n                                             This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number.    */\r\n\r\n  uint32_t MemoryDataWidth;             /*!< Defines the memory device width.\r\n                                             This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width.   */\r\n\r\n  uint32_t InternalBankNumber;          /*!< Defines the number of the device's internal banks.\r\n                                             This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number.      */\r\n\r\n  uint32_t CASLatency;                  /*!< Defines the SDRAM CAS latency in number of memory clock cycles.\r\n                                             This parameter can be a value of @ref FMC_SDRAM_CAS_Latency.        */\r\n\r\n  uint32_t WriteProtection;             /*!< Enables the SDRAM device to be accessed in write mode.\r\n                                             This parameter can be a value of @ref FMC_SDRAM_Write_Protection.   */\r\n\r\n  uint32_t SDClockPeriod;               /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow \r\n                                             to disable the clock before changing frequency.\r\n                                             This parameter can be a value of @ref FMC_SDRAM_Clock_Period.       */\r\n\r\n  uint32_t ReadBurst;                   /*!< This bit enable the SDRAM controller to anticipate the next read \r\n                                             commands during the CAS latency and stores data in the Read FIFO.\r\n                                             This parameter can be a value of @ref FMC_SDRAM_Read_Burst.         */\r\n\r\n  uint32_t ReadPipeDelay;               /*!< Define the delay in system clock cycles on read data path.\r\n                                             This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay.    */\r\n}FMC_SDRAM_InitTypeDef;\r\n\r\n/** \r\n  * @brief FMC SDRAM Timing parameters structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t LoadToActiveDelay;            /*!< Defines the delay between a Load Mode Register command and \r\n                                              an active or Refresh command in number of memory clock cycles.\r\n                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */\r\n\r\n  uint32_t ExitSelfRefreshDelay;         /*!< Defines the delay from releasing the self refresh command to \r\n                                              issuing the Activate command in number of memory clock cycles.\r\n                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */\r\n\r\n  uint32_t SelfRefreshTime;              /*!< Defines the minimum Self Refresh period in number of memory clock \r\n                                              cycles.\r\n                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */\r\n\r\n  uint32_t RowCycleDelay;                /*!< Defines the delay between the Refresh command and the Activate command\r\n                                              and the delay between two consecutive Refresh commands in number of \r\n                                              memory clock cycles.\r\n                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */\r\n\r\n  uint32_t WriteRecoveryTime;            /*!< Defines the Write recovery Time in number of memory clock cycles.\r\n                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */\r\n\r\n  uint32_t RPDelay;                      /*!< Defines the delay between a Precharge Command and an other command \r\n                                              in number of memory clock cycles.\r\n                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */\r\n\r\n  uint32_t RCDDelay;                     /*!< Defines the delay between the Activate Command and a Read/Write \r\n                                              command in number of memory clock cycles.\r\n                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */ \r\n}FMC_SDRAM_TimingTypeDef;\r\n\r\n/** \r\n  * @brief SDRAM command parameters structure definition\r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t CommandMode;                  /*!< Defines the command issued to the SDRAM device.\r\n                                              This parameter can be a value of @ref FMC_SDRAM_Command_Mode.          */\r\n\r\n  uint32_t CommandTarget;                /*!< Defines which device (1 or 2) the command will be issued to.\r\n                                              This parameter can be a value of @ref FMC_SDRAM_Command_Target.        */\r\n\r\n  uint32_t AutoRefreshNumber;            /*!< Defines the number of consecutive auto refresh command issued\r\n                                              in auto refresh mode.\r\n                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16   */\r\n  uint32_t ModeRegisterDefinition;       /*!< Defines the SDRAM Mode register content                                */\r\n}FMC_SDRAM_CommandTypeDef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported constants --------------------------------------------------------*/\r\n/** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller \r\n  * @{\r\n  */\r\n\r\n/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank\r\n  * @{\r\n  */\r\n#define FMC_NORSRAM_BANK1                       ((uint32_t)0x00000000U)\r\n#define FMC_NORSRAM_BANK2                       ((uint32_t)0x00000002U)\r\n#define FMC_NORSRAM_BANK3                       ((uint32_t)0x00000004U)\r\n#define FMC_NORSRAM_BANK4                       ((uint32_t)0x00000006U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing\r\n  * @{\r\n  */\r\n#define FMC_DATA_ADDRESS_MUX_DISABLE            ((uint32_t)0x00000000U)\r\n#define FMC_DATA_ADDRESS_MUX_ENABLE             ((uint32_t)0x00000002U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_Memory_Type FMC Memory Type\r\n  * @{\r\n  */\r\n#define FMC_MEMORY_TYPE_SRAM                    ((uint32_t)0x00000000U)\r\n#define FMC_MEMORY_TYPE_PSRAM                   ((uint32_t)0x00000004U)\r\n#define FMC_MEMORY_TYPE_NOR                     ((uint32_t)0x00000008U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width\r\n  * @{\r\n  */\r\n#define FMC_NORSRAM_MEM_BUS_WIDTH_8             ((uint32_t)0x00000000U)\r\n#define FMC_NORSRAM_MEM_BUS_WIDTH_16            ((uint32_t)0x00000010U)\r\n#define FMC_NORSRAM_MEM_BUS_WIDTH_32            ((uint32_t)0x00000020U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access\r\n  * @{\r\n  */\r\n#define FMC_NORSRAM_FLASH_ACCESS_ENABLE         ((uint32_t)0x00000040U)\r\n#define FMC_NORSRAM_FLASH_ACCESS_DISABLE        ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode\r\n  * @{\r\n  */\r\n#define FMC_BURST_ACCESS_MODE_DISABLE           ((uint32_t)0x00000000U) \r\n#define FMC_BURST_ACCESS_MODE_ENABLE            ((uint32_t)0x00000100U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity\r\n  * @{\r\n  */\r\n#define FMC_WAIT_SIGNAL_POLARITY_LOW            ((uint32_t)0x00000000U)\r\n#define FMC_WAIT_SIGNAL_POLARITY_HIGH           ((uint32_t)0x00000200U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_Wait_Timing FMC Wait Timing\r\n  * @{\r\n  */\r\n#define FMC_WAIT_TIMING_BEFORE_WS               ((uint32_t)0x00000000U)\r\n#define FMC_WAIT_TIMING_DURING_WS               ((uint32_t)0x00000800U) \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_Write_Operation FMC Write Operation\r\n  * @{\r\n  */\r\n#define FMC_WRITE_OPERATION_DISABLE             ((uint32_t)0x00000000U)\r\n#define FMC_WRITE_OPERATION_ENABLE              ((uint32_t)0x00001000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_Wait_Signal FMC Wait Signal\r\n  * @{\r\n  */\r\n#define FMC_WAIT_SIGNAL_DISABLE                 ((uint32_t)0x00000000U)\r\n#define FMC_WAIT_SIGNAL_ENABLE                  ((uint32_t)0x00002000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_Extended_Mode FMC Extended Mode\r\n  * @{\r\n  */\r\n#define FMC_EXTENDED_MODE_DISABLE               ((uint32_t)0x00000000U)\r\n#define FMC_EXTENDED_MODE_ENABLE                ((uint32_t)0x00004000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait\r\n  * @{\r\n  */\r\n#define FMC_ASYNCHRONOUS_WAIT_DISABLE           ((uint32_t)0x00000000U)\r\n#define FMC_ASYNCHRONOUS_WAIT_ENABLE            ((uint32_t)0x00008000U)\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup FMC_Page_Size FMC Page Size\r\n  * @{\r\n  */\r\n#define FMC_PAGE_SIZE_NONE           ((uint32_t)0x00000000U)\r\n#define FMC_PAGE_SIZE_128            ((uint32_t)FMC_BCR1_CPSIZE_0)\r\n#define FMC_PAGE_SIZE_256            ((uint32_t)FMC_BCR1_CPSIZE_1)\r\n#define FMC_PAGE_SIZE_512            ((uint32_t)(FMC_BCR1_CPSIZE_0 | FMC_BCR1_CPSIZE_1))\r\n#define FMC_PAGE_SIZE_1024           ((uint32_t)FMC_BCR1_CPSIZE_2)\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup FMC_Write_Burst FMC Write Burst\r\n  * @{\r\n  */\r\n#define FMC_WRITE_BURST_DISABLE                 ((uint32_t)0x00000000U)\r\n#define FMC_WRITE_BURST_ENABLE                  ((uint32_t)0x00080000U) \r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup FMC_Continous_Clock FMC Continuous Clock\r\n  * @{\r\n  */\r\n#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY          ((uint32_t)0x00000000U)\r\n#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC         ((uint32_t)0x00100000U)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup FMC_Write_FIFO FMC Write FIFO \r\n  * @{\r\n  */\r\n#define FMC_WRITE_FIFO_DISABLE           ((uint32_t)FMC_BCR1_WFDIS)\r\n#define FMC_WRITE_FIFO_ENABLE            ((uint32_t)0x00000000U)\r\n/**\r\n  * @}\r\n  */\r\n\t\r\n/** @defgroup FMC_Access_Mode FMC Access Mode \r\n  * @{\r\n  */\r\n#define FMC_ACCESS_MODE_A                        ((uint32_t)0x00000000U)\r\n#define FMC_ACCESS_MODE_B                        ((uint32_t)0x10000000U) \r\n#define FMC_ACCESS_MODE_C                        ((uint32_t)0x20000000U)\r\n#define FMC_ACCESS_MODE_D                        ((uint32_t)0x30000000)\r\n/**\r\n  * @}\r\n  */\r\n    \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller \r\n  * @{\r\n  */\r\n/** @defgroup FMC_NAND_Bank FMC NAND Bank \r\n  * @{\r\n  */\r\n#define FMC_NAND_BANK3                          ((uint32_t)0x00000100U) \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_Wait_feature FMC Wait feature\r\n  * @{\r\n  */\r\n#define FMC_NAND_WAIT_FEATURE_DISABLE           ((uint32_t)0x00000000U)\r\n#define FMC_NAND_WAIT_FEATURE_ENABLE            ((uint32_t)0x00000002U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type \r\n  * @{\r\n  */\r\n#define FMC_PCR_MEMORY_TYPE_NAND          ((uint32_t)0x00000008U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width \r\n  * @{\r\n  */\r\n#define FMC_NAND_MEM_BUS_WIDTH_8                ((uint32_t)0x00000000U)\r\n#define FMC_NAND_MEM_BUS_WIDTH_16               ((uint32_t)0x00000010U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_ECC FMC ECC \r\n  * @{\r\n  */\r\n#define FMC_NAND_ECC_DISABLE                    ((uint32_t)0x00000000U)\r\n#define FMC_NAND_ECC_ENABLE                     ((uint32_t)0x00000040U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size \r\n  * @{\r\n  */\r\n#define FMC_NAND_ECC_PAGE_SIZE_256BYTE          ((uint32_t)0x00000000U)\r\n#define FMC_NAND_ECC_PAGE_SIZE_512BYTE          ((uint32_t)0x00020000U)\r\n#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE         ((uint32_t)0x00040000U)\r\n#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE         ((uint32_t)0x00060000U)\r\n#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE         ((uint32_t)0x00080000U)\r\n#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE         ((uint32_t)0x000A0000U)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller \r\n  * @{\r\n  */\r\n/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank\r\n  * @{\r\n  */\r\n#define FMC_SDRAM_BANK1                       ((uint32_t)0x00000000U)\r\n#define FMC_SDRAM_BANK2                       ((uint32_t)0x00000001U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number \r\n  * @{\r\n  */\r\n#define FMC_SDRAM_COLUMN_BITS_NUM_8           ((uint32_t)0x00000000U)\r\n#define FMC_SDRAM_COLUMN_BITS_NUM_9           ((uint32_t)0x00000001U)\r\n#define FMC_SDRAM_COLUMN_BITS_NUM_10          ((uint32_t)0x00000002U)\r\n#define FMC_SDRAM_COLUMN_BITS_NUM_11          ((uint32_t)0x00000003U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number\r\n  * @{\r\n  */\r\n#define FMC_SDRAM_ROW_BITS_NUM_11             ((uint32_t)0x00000000U)\r\n#define FMC_SDRAM_ROW_BITS_NUM_12             ((uint32_t)0x00000004U)\r\n#define FMC_SDRAM_ROW_BITS_NUM_13             ((uint32_t)0x00000008U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width\r\n  * @{\r\n  */\r\n#define FMC_SDRAM_MEM_BUS_WIDTH_8             ((uint32_t)0x00000000U)\r\n#define FMC_SDRAM_MEM_BUS_WIDTH_16            ((uint32_t)0x00000010U)\r\n#define FMC_SDRAM_MEM_BUS_WIDTH_32            ((uint32_t)0x00000020U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number\r\n  * @{\r\n  */\r\n#define FMC_SDRAM_INTERN_BANKS_NUM_2          ((uint32_t)0x00000000U)\r\n#define FMC_SDRAM_INTERN_BANKS_NUM_4          ((uint32_t)0x00000040U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency\r\n  * @{\r\n  */\r\n#define FMC_SDRAM_CAS_LATENCY_1               ((uint32_t)0x00000080U)\r\n#define FMC_SDRAM_CAS_LATENCY_2               ((uint32_t)0x00000100U)\r\n#define FMC_SDRAM_CAS_LATENCY_3               ((uint32_t)0x00000180)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection\r\n  * @{\r\n  */\r\n#define FMC_SDRAM_WRITE_PROTECTION_DISABLE    ((uint32_t)0x00000000U)\r\n#define FMC_SDRAM_WRITE_PROTECTION_ENABLE     ((uint32_t)0x00000200U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period\r\n  * @{\r\n  */\r\n#define FMC_SDRAM_CLOCK_DISABLE               ((uint32_t)0x00000000U)\r\n#define FMC_SDRAM_CLOCK_PERIOD_2              ((uint32_t)0x00000800U)\r\n#define FMC_SDRAM_CLOCK_PERIOD_3              ((uint32_t)0x00000C00)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst\r\n  * @{\r\n  */\r\n#define FMC_SDRAM_RBURST_DISABLE              ((uint32_t)0x00000000U)\r\n#define FMC_SDRAM_RBURST_ENABLE               ((uint32_t)0x00001000U)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay\r\n  * @{\r\n  */\r\n#define FMC_SDRAM_RPIPE_DELAY_0               ((uint32_t)0x00000000U)\r\n#define FMC_SDRAM_RPIPE_DELAY_1               ((uint32_t)0x00002000U)\r\n#define FMC_SDRAM_RPIPE_DELAY_2               ((uint32_t)0x00004000U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode\r\n  * @{\r\n  */\r\n#define FMC_SDRAM_CMD_NORMAL_MODE             ((uint32_t)0x00000000U)\r\n#define FMC_SDRAM_CMD_CLK_ENABLE              ((uint32_t)0x00000001U)\r\n#define FMC_SDRAM_CMD_PALL                    ((uint32_t)0x00000002U)\r\n#define FMC_SDRAM_CMD_AUTOREFRESH_MODE        ((uint32_t)0x00000003U)\r\n#define FMC_SDRAM_CMD_LOAD_MODE               ((uint32_t)0x00000004U)\r\n#define FMC_SDRAM_CMD_SELFREFRESH_MODE        ((uint32_t)0x00000005U)\r\n#define FMC_SDRAM_CMD_POWERDOWN_MODE          ((uint32_t)0x00000006U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target\r\n  * @{\r\n  */\r\n#define FMC_SDRAM_CMD_TARGET_BANK2            FMC_SDCMR_CTB2\r\n#define FMC_SDRAM_CMD_TARGET_BANK1            FMC_SDCMR_CTB1\r\n#define FMC_SDRAM_CMD_TARGET_BANK1_2          ((uint32_t)0x00000018U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status \r\n  * @{\r\n  */\r\n#define FMC_SDRAM_NORMAL_MODE                     ((uint32_t)0x00000000U)\r\n#define FMC_SDRAM_SELF_REFRESH_MODE               FMC_SDSR_MODES1_0\r\n#define FMC_SDRAM_POWER_DOWN_MODE                 FMC_SDSR_MODES1_1\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition  \r\n  * @{\r\n  */  \r\n#define FMC_IT_RISING_EDGE                ((uint32_t)0x00000008U)\r\n#define FMC_IT_LEVEL                      ((uint32_t)0x00000010U)\r\n#define FMC_IT_FALLING_EDGE               ((uint32_t)0x00000020U)\r\n#define FMC_IT_REFRESH_ERROR              ((uint32_t)0x00004000U)\r\n/**\r\n  * @}\r\n  */\r\n    \r\n/** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition \r\n  * @{\r\n  */ \r\n#define FMC_FLAG_RISING_EDGE                    ((uint32_t)0x00000001U)\r\n#define FMC_FLAG_LEVEL                          ((uint32_t)0x00000002U)\r\n#define FMC_FLAG_FALLING_EDGE                   ((uint32_t)0x00000004U)\r\n#define FMC_FLAG_FEMPT                          ((uint32_t)0x00000040U)\r\n#define FMC_SDRAM_FLAG_REFRESH_IT               FMC_SDSR_RE\r\n#define FMC_SDRAM_FLAG_BUSY                     FMC_SDSR_BUSY\r\n#define FMC_SDRAM_FLAG_REFRESH_ERROR            FMC_SDRTR_CRE\r\n/**\r\n  * @}\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/** @defgroup FMC_LL_Private_Macros FMC_LL  Private Macros\r\n  * @{\r\n  */\r\n\r\n/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros\r\n *  @brief macros to handle NOR device enable/disable and read/write operations\r\n *  @{\r\n */\r\n \r\n/**\r\n  * @brief  Enable the NORSRAM device access.\r\n  * @param  __INSTANCE__: FMC_NORSRAM Instance\r\n  * @param  __BANK__: FMC_NORSRAM Bank     \r\n  * @retval None\r\n  */ \r\n#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__)  ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN)\r\n\r\n/**\r\n  * @brief  Disable the NORSRAM device access.\r\n  * @param  __INSTANCE__: FMC_NORSRAM Instance\r\n  * @param  __BANK__: FMC_NORSRAM Bank   \r\n  * @retval None\r\n  */ \r\n#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)  \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros\r\n *  @brief macros to handle NAND device enable/disable\r\n *  @{\r\n */\r\n \r\n/**\r\n  * @brief  Enable the NAND device access.\r\n  * @param  __INSTANCE__: FMC_NAND Instance    \r\n  * @retval None\r\n  */  \r\n#define __FMC_NAND_ENABLE(__INSTANCE__)  ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)\r\n\r\n/**\r\n  * @brief  Disable the NAND device access.\r\n  * @param  __INSTANCE__: FMC_NAND Instance  \r\n  * @retval None\r\n  */\r\n#define __FMC_NAND_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)\r\n\r\n/**\r\n  * @}\r\n  */ \r\n    \r\n/** @defgroup FMC_Interrupt FMC Interrupt\r\n *  @brief macros to handle FMC interrupts\r\n * @{\r\n */ \r\n\r\n/**\r\n  * @brief  Enable the NAND device interrupt.\r\n  * @param  __INSTANCE__:  FMC_NAND instance     \r\n  * @param  __INTERRUPT__: FMC_NAND interrupt \r\n  *         This parameter can be any combination of the following values:\r\n  *            @arg FMC_IT_RISING_EDGE: Interrupt rising edge.\r\n  *            @arg FMC_IT_LEVEL: Interrupt level.\r\n  *            @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.       \r\n  * @retval None\r\n  */  \r\n#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SR |= (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disable the NAND device interrupt.\r\n  * @param  __INSTANCE__:  FMC_NAND Instance\r\n  * @param  __INTERRUPT__: FMC_NAND interrupt\r\n  *         This parameter can be any combination of the following values:\r\n  *            @arg FMC_IT_RISING_EDGE: Interrupt rising edge.\r\n  *            @arg FMC_IT_LEVEL: Interrupt level.\r\n  *            @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.   \r\n  * @retval None\r\n  */\r\n#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SR &= ~(__INTERRUPT__))\r\n                                                                                                                           \r\n/**\r\n  * @brief  Get flag status of the NAND device.\r\n  * @param  __INSTANCE__: FMC_NAND Instance\r\n  * @param  __BANK__:     FMC_NAND Bank     \r\n  * @param  __FLAG__: FMC_NAND flag\r\n  *         This parameter can be any combination of the following values:\r\n  *            @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.\r\n  *            @arg FMC_FLAG_LEVEL: Interrupt level edge flag.\r\n  *            @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.\r\n  *            @arg FMC_FLAG_FEMPT: FIFO empty flag.   \r\n  * @retval The state of FLAG (SET or RESET).\r\n  */\r\n#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__)  (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))\r\n\r\n/**\r\n  * @brief  Clear flag status of the NAND device.\r\n  * @param  __INSTANCE__: FMC_NAND Instance   \r\n  * @param  __FLAG__: FMC_NAND flag\r\n  *         This parameter can be any combination of the following values:\r\n  *            @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.\r\n  *            @arg FMC_FLAG_LEVEL: Interrupt level edge flag.\r\n  *            @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.\r\n  *            @arg FMC_FLAG_FEMPT: FIFO empty flag.   \r\n  * @retval None\r\n  */\r\n#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->SR &= ~(__FLAG__))  \r\n\r\n/**\r\n  * @brief  Enable the SDRAM device interrupt.\r\n  * @param  __INSTANCE__: FMC_SDRAM instance  \r\n  * @param  __INTERRUPT__: FMC_SDRAM interrupt \r\n  *         This parameter can be any combination of the following values:\r\n  *            @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error      \r\n  * @retval None\r\n  */\r\n#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SDRTR |= (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disable the SDRAM device interrupt.\r\n  * @param  __INSTANCE__: FMC_SDRAM instance  \r\n  * @param  __INTERRUPT__: FMC_SDRAM interrupt \r\n  *         This parameter can be any combination of the following values:\r\n  *            @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error      \r\n  * @retval None\r\n  */\r\n#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Get flag status of the SDRAM device.\r\n  * @param  __INSTANCE__: FMC_SDRAM instance  \r\n  * @param  __FLAG__: FMC_SDRAM flag\r\n  *         This parameter can be any combination of the following values:\r\n  *            @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.\r\n  *            @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.\r\n  *            @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.\r\n  * @retval The state of FLAG (SET or RESET).\r\n  */\r\n#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))\r\n\r\n/**\r\n  * @brief  Clear flag status of the SDRAM device.\r\n  * @param  __INSTANCE__: FMC_SDRAM instance  \r\n  * @param  __FLAG__: FMC_SDRAM flag\r\n  *         This parameter can be any combination of the following values:\r\n  *           @arg FMC_SDRAM_FLAG_REFRESH_ERROR\r\n  * @retval None\r\n  */\r\n#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->SDRTR |= (__FLAG__))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions\r\n  *  @{\r\n  */\r\n\r\n/** @defgroup FMC_LL_NORSRAM  NOR SRAM\r\n  *  @{\r\n  */\r\n/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions \r\n  *  @{\r\n  */\r\nHAL_StatusTypeDef  FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);\r\nHAL_StatusTypeDef  FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);\r\nHAL_StatusTypeDef  FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);\r\nHAL_StatusTypeDef  FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions \r\n  *  @{\r\n  */\r\nHAL_StatusTypeDef  FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);\r\nHAL_StatusTypeDef  FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);\r\n/**\r\n  * @}\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_LL_NAND NAND\r\n  *  @{\r\n  */\r\n/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions \r\n  *  @{\r\n  */\r\nHAL_StatusTypeDef  FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);\r\nHAL_StatusTypeDef  FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);\r\nHAL_StatusTypeDef  FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);\r\nHAL_StatusTypeDef  FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions \r\n  *  @{\r\n  */\r\nHAL_StatusTypeDef  FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);\r\nHAL_StatusTypeDef  FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);\r\nHAL_StatusTypeDef  FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_LL_SDRAM SDRAM\r\n  *  @{\r\n  */\r\n/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions \r\n  *  @{\r\n  */\r\nHAL_StatusTypeDef  FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);\r\nHAL_StatusTypeDef  FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);\r\nHAL_StatusTypeDef  FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions \r\n  *  @{\r\n  */\r\nHAL_StatusTypeDef  FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);\r\nHAL_StatusTypeDef  FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);\r\nHAL_StatusTypeDef  FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);\r\nHAL_StatusTypeDef  FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);\r\nHAL_StatusTypeDef  FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);\r\nuint32_t           FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_LL_FMC_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_ll_sdmmc.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of SDMMC HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_LL_SDMMC_H\r\n#define __STM32F7xx_LL_SDMMC_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup SDMMC_LL\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/ \r\n/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types\r\n  * @{\r\n  */\r\n  \r\n/** \r\n  * @brief  SDMMC Configuration Structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t ClockEdge;            /*!< Specifies the clock transition on which the bit capture is made.\r\n                                      This parameter can be a value of @ref SDMMC_LL_Clock_Edge                 */\r\n\r\n  uint32_t ClockBypass;          /*!< Specifies whether the SDMMC Clock divider bypass is\r\n                                      enabled or disabled.\r\n                                      This parameter can be a value of @ref SDMMC_LL_Clock_Bypass               */\r\n\r\n  uint32_t ClockPowerSave;       /*!< Specifies whether SDMMC Clock output is enabled or\r\n                                      disabled when the bus is idle.\r\n                                      This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save           */\r\n\r\n  uint32_t BusWide;              /*!< Specifies the SDMMC bus width.\r\n                                      This parameter can be a value of @ref SDMMC_LL_Bus_Wide                   */\r\n\r\n  uint32_t HardwareFlowControl;  /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.\r\n                                      This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control      */\r\n\r\n  uint32_t ClockDiv;             /*!< Specifies the clock frequency of the SDMMC controller.\r\n                                      This parameter can be a value between Min_Data = 0 and Max_Data = 255 */  \r\n  \r\n}SDMMC_InitTypeDef;\r\n  \r\n\r\n/** \r\n  * @brief  SDMMC Command Control structure \r\n  */\r\ntypedef struct                                                                                            \r\n{\r\n  uint32_t Argument;            /*!< Specifies the SDMMC command argument which is sent\r\n                                     to a card as part of a command message. If a command\r\n                                     contains an argument, it must be loaded into this register\r\n                                     before writing the command to the command register.              */\r\n\r\n  uint32_t CmdIndex;            /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and \r\n                                     Max_Data = 64                                                    */\r\n\r\n  uint32_t Response;            /*!< Specifies the SDMMC response type.\r\n                                     This parameter can be a value of @ref SDMMC_LL_Response_Type         */\r\n\r\n  uint32_t WaitForInterrupt;    /*!< Specifies whether SDMMC wait for interrupt request is \r\n                                     enabled or disabled.\r\n                                     This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State  */\r\n\r\n  uint32_t CPSM;                /*!< Specifies whether SDMMC Command path state machine (CPSM)\r\n                                     is enabled or disabled.\r\n                                     This parameter can be a value of @ref SDMMC_LL_CPSM_State            */\r\n}SDMMC_CmdInitTypeDef;\r\n\r\n\r\n/** \r\n  * @brief  SDMMC Data Control structure \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t DataTimeOut;         /*!< Specifies the data timeout period in card bus clock periods.  */\r\n\r\n  uint32_t DataLength;          /*!< Specifies the number of data bytes to be transferred.         */\r\n \r\n  uint32_t DataBlockSize;       /*!< Specifies the data block size for block transfer.\r\n                                     This parameter can be a value of @ref SDMMC_LL_Data_Block_Size    */\r\n \r\n  uint32_t TransferDir;         /*!< Specifies the data transfer direction, whether the transfer\r\n                                     is a read or write.\r\n                                     This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */\r\n \r\n  uint32_t TransferMode;        /*!< Specifies whether data transfer is in stream or block mode.\r\n                                     This parameter can be a value of @ref SDMMC_LL_Transfer_Type      */\r\n \r\n  uint32_t DPSM;                /*!< Specifies whether SDMMC Data path state machine (DPSM)\r\n                                     is enabled or disabled.\r\n                                     This parameter can be a value of @ref SDMMC_LL_DPSM_State         */\r\n}SDMMC_DataInitTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Exported constants --------------------------------------------------------*/\r\n/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup SDMMC_LL_Clock_Edge Clock Edge\r\n  * @{\r\n  */\r\n#define SDMMC_CLOCK_EDGE_RISING               ((uint32_t)0x00000000U)\r\n#define SDMMC_CLOCK_EDGE_FALLING              SDMMC_CLKCR_NEGEDGE\r\n\r\n#define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \\\r\n                                  ((EDGE) == SDMMC_CLOCK_EDGE_FALLING))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass\r\n  * @{\r\n  */\r\n#define SDMMC_CLOCK_BYPASS_DISABLE             ((uint32_t)0x00000000U)\r\n#define SDMMC_CLOCK_BYPASS_ENABLE              SDMMC_CLKCR_BYPASS   \r\n\r\n#define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || \\\r\n                                      ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE))\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving\r\n  * @{\r\n  */\r\n#define SDMMC_CLOCK_POWER_SAVE_DISABLE         ((uint32_t)0x00000000U)\r\n#define SDMMC_CLOCK_POWER_SAVE_ENABLE          SDMMC_CLKCR_PWRSAV\r\n\r\n#define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \\\r\n                                        ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SDMMC_LL_Bus_Wide Bus Width\r\n  * @{\r\n  */\r\n#define SDMMC_BUS_WIDE_1B                      ((uint32_t)0x00000000U)\r\n#define SDMMC_BUS_WIDE_4B                      SDMMC_CLKCR_WIDBUS_0\r\n#define SDMMC_BUS_WIDE_8B                      SDMMC_CLKCR_WIDBUS_1\r\n\r\n#define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \\\r\n                                ((WIDE) == SDMMC_BUS_WIDE_4B) || \\\r\n                                ((WIDE) == SDMMC_BUS_WIDE_8B))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control\r\n  * @{\r\n  */\r\n#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE    ((uint32_t)0x00000000U)\r\n#define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE     SDMMC_CLKCR_HWFC_EN\r\n\r\n#define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \\\r\n                                                ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup SDMMC_LL_Clock_Division Clock Division\r\n  * @{\r\n  */\r\n#define IS_SDMMC_CLKDIV(DIV)   ((DIV) <= 0xFF)\r\n/**\r\n  * @}\r\n  */  \r\n    \r\n/** @defgroup SDMMC_LL_Command_Index Command Index\r\n  * @{\r\n  */\r\n#define IS_SDMMC_CMD_INDEX(INDEX)            ((INDEX) < 0x40)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SDMMC_LL_Response_Type Response Type\r\n  * @{\r\n  */\r\n#define SDMMC_RESPONSE_NO                    ((uint32_t)0x00000000U)\r\n#define SDMMC_RESPONSE_SHORT                 SDMMC_CMD_WAITRESP_0\r\n#define SDMMC_RESPONSE_LONG                  SDMMC_CMD_WAITRESP\r\n\r\n#define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO)    || \\\r\n                                    ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \\\r\n                                    ((RESPONSE) == SDMMC_RESPONSE_LONG))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt\r\n  * @{\r\n  */\r\n#define SDMMC_WAIT_NO                        ((uint32_t)0x00000000U)\r\n#define SDMMC_WAIT_IT                        SDMMC_CMD_WAITINT \r\n#define SDMMC_WAIT_PEND                      SDMMC_CMD_WAITPEND\r\n\r\n#define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \\\r\n                            ((WAIT) == SDMMC_WAIT_IT) || \\\r\n                            ((WAIT) == SDMMC_WAIT_PEND))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SDMMC_LL_CPSM_State CPSM State\r\n  * @{\r\n  */\r\n#define SDMMC_CPSM_DISABLE                   ((uint32_t)0x00000000U)\r\n#define SDMMC_CPSM_ENABLE                    SDMMC_CMD_CPSMEN\r\n\r\n#define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \\\r\n                            ((CPSM) == SDMMC_CPSM_ENABLE))\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup SDMMC_LL_Response_Registers Response Register\r\n  * @{\r\n  */\r\n#define SDMMC_RESP1                          ((uint32_t)0x00000000U)\r\n#define SDMMC_RESP2                          ((uint32_t)0x00000004U)\r\n#define SDMMC_RESP3                          ((uint32_t)0x00000008U)\r\n#define SDMMC_RESP4                          ((uint32_t)0x0000000C)\r\n\r\n#define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \\\r\n                            ((RESP) == SDMMC_RESP2) || \\\r\n                            ((RESP) == SDMMC_RESP3) || \\\r\n                            ((RESP) == SDMMC_RESP4))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SDMMC_LL_Data_Length Data Lenght\r\n  * @{\r\n  */\r\n#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SDMMC_LL_Data_Block_Size  Data Block Size\r\n  * @{\r\n  */\r\n#define SDMMC_DATABLOCK_SIZE_1B               ((uint32_t)0x00000000U)\r\n#define SDMMC_DATABLOCK_SIZE_2B               SDMMC_DCTRL_DBLOCKSIZE_0\r\n#define SDMMC_DATABLOCK_SIZE_4B               SDMMC_DCTRL_DBLOCKSIZE_1\r\n#define SDMMC_DATABLOCK_SIZE_8B               (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1)\r\n#define SDMMC_DATABLOCK_SIZE_16B              SDMMC_DCTRL_DBLOCKSIZE_2\r\n#define SDMMC_DATABLOCK_SIZE_32B              (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2)\r\n#define SDMMC_DATABLOCK_SIZE_64B              (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)\r\n#define SDMMC_DATABLOCK_SIZE_128B             (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)\r\n#define SDMMC_DATABLOCK_SIZE_256B             SDMMC_DCTRL_DBLOCKSIZE_3\r\n#define SDMMC_DATABLOCK_SIZE_512B             (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3)\r\n#define SDMMC_DATABLOCK_SIZE_1024B            (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)\r\n#define SDMMC_DATABLOCK_SIZE_2048B            (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) \r\n#define SDMMC_DATABLOCK_SIZE_4096B            (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)\r\n#define SDMMC_DATABLOCK_SIZE_8192B            (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)\r\n#define SDMMC_DATABLOCK_SIZE_16384B           (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)\r\n\r\n#define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B)    || \\\r\n                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_2B)    || \\\r\n                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_4B)    || \\\r\n                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_8B)    || \\\r\n                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_16B)   || \\\r\n                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_32B)   || \\\r\n                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_64B)   || \\\r\n                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_128B)  || \\\r\n                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_256B)  || \\\r\n                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_512B)  || \\\r\n                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \\\r\n                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \\\r\n                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \\\r\n                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \\\r\n                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B)) \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction\r\n  * @{\r\n  */\r\n#define SDMMC_TRANSFER_DIR_TO_CARD            ((uint32_t)0x00000000U)\r\n#define SDMMC_TRANSFER_DIR_TO_SDMMC            SDMMC_DCTRL_DTDIR\r\n\r\n#define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \\\r\n                                   ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SDMMC_LL_Transfer_Type Transfer Type\r\n  * @{\r\n  */\r\n#define SDMMC_TRANSFER_MODE_BLOCK             ((uint32_t)0x00000000U)\r\n#define SDMMC_TRANSFER_MODE_STREAM            SDMMC_DCTRL_DTMODE\r\n\r\n#define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \\\r\n                                     ((MODE) == SDMMC_TRANSFER_MODE_STREAM))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SDMMC_LL_DPSM_State DPSM State\r\n  * @{\r\n  */\r\n#define SDMMC_DPSM_DISABLE                    ((uint32_t)0x00000000U)\r\n#define SDMMC_DPSM_ENABLE                     SDMMC_DCTRL_DTEN\r\n\r\n#define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\\\r\n                            ((DPSM) == SDMMC_DPSM_ENABLE))\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode\r\n  * @{\r\n  */\r\n#define SDMMC_READ_WAIT_MODE_DATA2                ((uint32_t)0x00000000U)\r\n#define SDMMC_READ_WAIT_MODE_CLK                  (SDMMC_DCTRL_RWMOD)\r\n\r\n#define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \\\r\n                                     ((MODE) == SDMMC_READ_WAIT_MODE_DATA2))\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources\r\n  * @{\r\n  */\r\n#define SDMMC_IT_CCRCFAIL                    SDMMC_STA_CCRCFAIL\r\n#define SDMMC_IT_DCRCFAIL                    SDMMC_STA_DCRCFAIL\r\n#define SDMMC_IT_CTIMEOUT                    SDMMC_STA_CTIMEOUT\r\n#define SDMMC_IT_DTIMEOUT                    SDMMC_STA_DTIMEOUT\r\n#define SDMMC_IT_TXUNDERR                    SDMMC_STA_TXUNDERR\r\n#define SDMMC_IT_RXOVERR                     SDMMC_STA_RXOVERR\r\n#define SDMMC_IT_CMDREND                     SDMMC_STA_CMDREND\r\n#define SDMMC_IT_CMDSENT                     SDMMC_STA_CMDSENT\r\n#define SDMMC_IT_DATAEND                     SDMMC_STA_DATAEND\r\n#define SDMMC_IT_DBCKEND                     SDMMC_STA_DBCKEND\r\n#define SDMMC_IT_CMDACT                      SDMMC_STA_CMDACT\r\n#define SDMMC_IT_TXACT                       SDMMC_STA_TXACT\r\n#define SDMMC_IT_RXACT                       SDMMC_STA_RXACT\r\n#define SDMMC_IT_TXFIFOHE                    SDMMC_STA_TXFIFOHE\r\n#define SDMMC_IT_RXFIFOHF                    SDMMC_STA_RXFIFOHF\r\n#define SDMMC_IT_TXFIFOF                     SDMMC_STA_TXFIFOF\r\n#define SDMMC_IT_RXFIFOF                     SDMMC_STA_RXFIFOF\r\n#define SDMMC_IT_TXFIFOE                     SDMMC_STA_TXFIFOE\r\n#define SDMMC_IT_RXFIFOE                     SDMMC_STA_RXFIFOE\r\n#define SDMMC_IT_TXDAVL                      SDMMC_STA_TXDAVL\r\n#define SDMMC_IT_RXDAVL                      SDMMC_STA_RXDAVL\r\n#define SDMMC_IT_SDIOIT                      SDMMC_STA_SDIOIT\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup SDMMC_LL_Flags Flags\r\n  * @{\r\n  */\r\n#define SDMMC_FLAG_CCRCFAIL                  SDMMC_STA_CCRCFAIL\r\n#define SDMMC_FLAG_DCRCFAIL                  SDMMC_STA_DCRCFAIL\r\n#define SDMMC_FLAG_CTIMEOUT                  SDMMC_STA_CTIMEOUT\r\n#define SDMMC_FLAG_DTIMEOUT                  SDMMC_STA_DTIMEOUT\r\n#define SDMMC_FLAG_TXUNDERR                  SDMMC_STA_TXUNDERR\r\n#define SDMMC_FLAG_RXOVERR                   SDMMC_STA_RXOVERR\r\n#define SDMMC_FLAG_CMDREND                   SDMMC_STA_CMDREND\r\n#define SDMMC_FLAG_CMDSENT                   SDMMC_STA_CMDSENT\r\n#define SDMMC_FLAG_DATAEND                   SDMMC_STA_DATAEND\r\n#define SDMMC_FLAG_DBCKEND                   SDMMC_STA_DBCKEND\r\n#define SDMMC_FLAG_CMDACT                    SDMMC_STA_CMDACT\r\n#define SDMMC_FLAG_TXACT                     SDMMC_STA_TXACT\r\n#define SDMMC_FLAG_RXACT                     SDMMC_STA_RXACT\r\n#define SDMMC_FLAG_TXFIFOHE                  SDMMC_STA_TXFIFOHE\r\n#define SDMMC_FLAG_RXFIFOHF                  SDMMC_STA_RXFIFOHF\r\n#define SDMMC_FLAG_TXFIFOF                   SDMMC_STA_TXFIFOF\r\n#define SDMMC_FLAG_RXFIFOF                   SDMMC_STA_RXFIFOF\r\n#define SDMMC_FLAG_TXFIFOE                   SDMMC_STA_TXFIFOE\r\n#define SDMMC_FLAG_RXFIFOE                   SDMMC_STA_RXFIFOE\r\n#define SDMMC_FLAG_TXDAVL                    SDMMC_STA_TXDAVL\r\n#define SDMMC_FLAG_RXDAVL                    SDMMC_STA_RXDAVL\r\n#define SDMMC_FLAG_SDIOIT                    SDMMC_STA_SDIOIT\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Exported macro ------------------------------------------------------------*/\r\n/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions\r\n  * @brief SDMMC_LL registers bit address in the alias region\r\n  * @{\r\n  */\r\n/* ---------------------- SDMMC registers bit mask --------------------------- */\r\n/* --- CLKCR Register ---*/\r\n/* CLKCR register clear mask */ \r\n#define CLKCR_CLEAR_MASK         ((uint32_t)(SDMMC_CLKCR_CLKDIV  | SDMMC_CLKCR_PWRSAV |\\\r\n                                             SDMMC_CLKCR_BYPASS  | SDMMC_CLKCR_WIDBUS |\\\r\n                                             SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN))\r\n\r\n/* --- DCTRL Register ---*/\r\n/* SDMMC DCTRL Clear Mask */\r\n#define DCTRL_CLEAR_MASK         ((uint32_t)(SDMMC_DCTRL_DTEN    | SDMMC_DCTRL_DTDIR |\\\r\n                                             SDMMC_DCTRL_DTMODE  | SDMMC_DCTRL_DBLOCKSIZE))\r\n\r\n/* --- CMD Register ---*/\r\n/* CMD Register clear mask */\r\n#define CMD_CLEAR_MASK           ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\\\r\n                                             SDMMC_CMD_WAITINT  | SDMMC_CMD_WAITPEND |\\\r\n                                             SDMMC_CMD_CPSMEN   | SDMMC_CMD_SDIOSUSPEND))\r\n\r\n/* SDMMC Initialization Frequency (400KHz max) */\r\n#define SDMMC_INIT_CLK_DIV ((uint8_t)0x76)\r\n\r\n/* SDMMC Data Transfer Frequency (25MHz max) */\r\n#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0)\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration\r\n *  @brief macros to handle interrupts and specific clock configurations\r\n * @{\r\n */\r\n \r\n/**\r\n  * @brief  Enable the SDMMC device.\r\n  * @param  __INSTANCE__: SDMMC Instance  \r\n  * @retval None\r\n  */ \r\n#define __SDMMC_ENABLE(__INSTANCE__)  ((__INSTANCE__)->CLKCR |= SDMMC_CLKCR_CLKEN)\r\n\r\n/**\r\n  * @brief  Disable the SDMMC device.\r\n  * @param  __INSTANCE__: SDMMC Instance  \r\n  * @retval None\r\n  */\r\n#define __SDMMC_DISABLE(__INSTANCE__)  ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN)\r\n\r\n/**\r\n  * @brief  Enable the SDMMC DMA transfer.\r\n  * @param  __INSTANCE__: SDMMC Instance  \r\n  * @retval None\r\n  */ \r\n#define __SDMMC_DMA_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_DMAEN)\r\n/**\r\n  * @brief  Disable the SDMMC DMA transfer.\r\n  * @param  __INSTANCE__: SDMMC Instance   \r\n  * @retval None\r\n  */\r\n#define __SDMMC_DMA_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN)\r\n \r\n/**\r\n  * @brief  Enable the SDMMC device interrupt.\r\n  * @param  __INSTANCE__ : Pointer to SDMMC register base  \r\n  * @param  __INTERRUPT__ : specifies the SDMMC interrupt sources to be enabled.\r\n  *         This parameter can be one or a combination of the following values:\r\n  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r\n  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r\n  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt\r\n  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt\r\n  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r\n  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt\r\n  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt\r\n  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt\r\n  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt\r\n  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt\r\n  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt\r\n  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt\r\n  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt\r\n  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\r\n  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt\r\n  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt\r\n  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt\r\n  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt\r\n  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt\r\n  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt\r\n  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt\r\n  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt   \r\n  * @retval None\r\n  */\r\n#define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK |= (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Disable the SDMMC device interrupt.\r\n  * @param  __INSTANCE__ : Pointer to SDMMC register base   \r\n  * @param  __INTERRUPT__ : specifies the SDMMC interrupt sources to be disabled.\r\n  *          This parameter can be one or a combination of the following values:\r\n  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r\n  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r\n  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt\r\n  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt\r\n  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r\n  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt\r\n  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt\r\n  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt\r\n  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt\r\n  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt\r\n  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt\r\n  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt\r\n  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt\r\n  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\r\n  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt\r\n  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt\r\n  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt\r\n  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt\r\n  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt\r\n  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt\r\n  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt\r\n  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt   \r\n  * @retval None\r\n  */\r\n#define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Checks whether the specified SDMMC flag is set or not. \r\n  * @param  __INSTANCE__ : Pointer to SDMMC register base   \r\n  * @param  __FLAG__: specifies the flag to check. \r\n  *          This parameter can be one of the following values:\r\n  *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)\r\n  *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)\r\n  *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout\r\n  *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout\r\n  *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error\r\n  *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error\r\n  *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)\r\n  *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)\r\n  *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)\r\n  *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)\r\n  *            @arg SDMMC_FLAG_CMDACT:   Command transfer in progress\r\n  *            @arg SDMMC_FLAG_TXACT:    Data transmit in progress\r\n  *            @arg SDMMC_FLAG_RXACT:    Data receive in progress\r\n  *            @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty\r\n  *            @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full\r\n  *            @arg SDMMC_FLAG_TXFIFOF:  Transmit FIFO full\r\n  *            @arg SDMMC_FLAG_RXFIFOF:  Receive FIFO full\r\n  *            @arg SDMMC_FLAG_TXFIFOE:  Transmit FIFO empty\r\n  *            @arg SDMMC_FLAG_RXFIFOE:  Receive FIFO empty\r\n  *            @arg SDMMC_FLAG_TXDAVL:   Data available in transmit FIFO\r\n  *            @arg SDMMC_FLAG_RXDAVL:   Data available in receive FIFO\r\n  *            @arg SDMMC_FLAG_SDMMCIT:   SD I/O interrupt received\r\n  * @retval The new state of SDMMC_FLAG (SET or RESET).\r\n  */\r\n#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->STA &(__FLAG__)) != RESET)\r\n\r\n\r\n/**\r\n  * @brief  Clears the SDMMC pending flags.\r\n  * @param  __INSTANCE__ : Pointer to SDMMC register base  \r\n  * @param  __FLAG__: specifies the flag to clear.  \r\n  *          This parameter can be one or a combination of the following values:\r\n  *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)\r\n  *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)\r\n  *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout\r\n  *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout\r\n  *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error\r\n  *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error\r\n  *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)\r\n  *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)\r\n  *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)\r\n  *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)\r\n  *            @arg SDMMC_FLAG_SDMMCIT:   SD I/O interrupt received\r\n  * @retval None\r\n  */\r\n#define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->ICR = (__FLAG__))\r\n\r\n/**\r\n  * @brief  Checks whether the specified SDMMC interrupt has occurred or not.\r\n  * @param  __INSTANCE__ : Pointer to SDMMC register base   \r\n  * @param  __INTERRUPT__: specifies the SDMMC interrupt source to check. \r\n  *          This parameter can be one of the following values:\r\n  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r\n  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r\n  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt\r\n  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt\r\n  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r\n  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt\r\n  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt\r\n  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt\r\n  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt\r\n  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt\r\n  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt\r\n  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt\r\n  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt\r\n  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\r\n  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt\r\n  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt\r\n  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt\r\n  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt\r\n  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt\r\n  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt\r\n  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt\r\n  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt\r\n  * @retval The new state of SDMMC_IT (SET or RESET).\r\n  */\r\n#define __SDMMC_GET_IT  (__INSTANCE__, __INTERRUPT__)  (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Clears the SDMMC's interrupt pending bits.\r\n  * @param  __INSTANCE__ : Pointer to SDMMC register base \r\n  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. \r\n  *          This parameter can be one or a combination of the following values:\r\n  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r\n  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r\n  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt\r\n  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt\r\n  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r\n  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt\r\n  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt\r\n  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt\r\n  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDMMC_DCOUNT, is zero) interrupt\r\n  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt\r\n  * @retval None\r\n  */\r\n#define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->ICR = (__INTERRUPT__))\r\n\r\n/**\r\n  * @brief  Enable Start the SD I/O Read Wait operation.\r\n  * @param  __INSTANCE__ : Pointer to SDMMC register base  \r\n  * @retval None\r\n  */  \r\n#define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART)\r\n\r\n/**\r\n  * @brief  Disable Start the SD I/O Read Wait operations.\r\n  * @param  __INSTANCE__ : Pointer to SDMMC register base   \r\n  * @retval None\r\n  */  \r\n#define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)\r\n\r\n/**\r\n  * @brief  Enable Start the SD I/O Read Wait operation.\r\n  * @param  __INSTANCE__ : Pointer to SDMMC register base   \r\n  * @retval None\r\n  */  \r\n#define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP)\r\n\r\n/**\r\n  * @brief  Disable Stop the SD I/O Read Wait operations.\r\n  * @param  __INSTANCE__ : Pointer to SDMMC register base  \r\n  * @retval None\r\n  */  \r\n#define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)\r\n\r\n/**\r\n  * @brief  Enable the SD I/O Mode Operation.\r\n  * @param  __INSTANCE__ : Pointer to SDMMC register base   \r\n  * @retval None\r\n  */  \r\n#define __SDMMC_OPERATION_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN) \r\n\r\n/**\r\n  * @brief  Disable the SD I/O Mode Operation.\r\n  * @param  __INSTANCE__ : Pointer to SDMMC register base \r\n  * @retval None\r\n  */  \r\n#define __SDMMC_OPERATION_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN) \r\n\r\n/**\r\n  * @brief  Enable the SD I/O Suspend command sending.\r\n  * @param  __INSTANCE__ : Pointer to SDMMC register base  \r\n  * @retval None\r\n  */  \r\n#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__)  ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND) \r\n\r\n/**\r\n  * @brief  Disable the SD I/O Suspend command sending.\r\n  * @param  __INSTANCE__ : Pointer to SDMMC register base  \r\n  * @retval None\r\n  */  \r\n#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__)  ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND) \r\n      \r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup SDMMC_LL_Exported_Functions\r\n  * @{\r\n  */\r\n  \r\n/* Initialization/de-initialization functions  **********************************/\r\n/** @addtogroup HAL_SDMMC_LL_Group1\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* I/O operation functions  *****************************************************/\r\n/** @addtogroup HAL_SDMMC_LL_Group2\r\n  * @{\r\n  */\r\n/* Blocking mode: Polling */\r\nuint32_t          SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);\r\nHAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData);\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Peripheral Control functions  ************************************************/\r\n/** @addtogroup HAL_SDMMC_LL_Group3\r\n  * @{\r\n  */\r\nHAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx);\r\nHAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);\r\nuint32_t          SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx);\r\n\r\n/* Command path state machine (CPSM) management functions */\r\nHAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command);\r\nuint8_t           SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx);\r\nuint32_t          SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);\r\n\r\n/* Data path state machine (DPSM) management functions */\r\nHAL_StatusTypeDef SDMMC_DataConfig(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data);\r\nuint32_t          SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);\r\nuint32_t          SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);\r\n\r\n/* SDMMC Cards mode management functions */\r\nHAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __STM32F7xx_LL_SDMMC_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usb.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_ll_usb.h\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Header file of USB Core HAL module.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __STM32F7xx_LL_USB_H\r\n#define __STM32F7xx_LL_USB_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal_def.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup USB_Core\r\n  * @{\r\n  */ \r\n\r\n/* Exported types ------------------------------------------------------------*/ \r\n\r\n/** \r\n  * @brief  USB Mode definition  \r\n  */  \r\ntypedef enum \r\n{\r\n   USB_OTG_DEVICE_MODE  = 0U,\r\n   USB_OTG_HOST_MODE    = 1U,\r\n   USB_OTG_DRD_MODE     = 2U\r\n   \r\n}USB_OTG_ModeTypeDef;\r\n\r\n/** \r\n  * @brief  URB States definition  \r\n  */ \r\ntypedef enum {\r\n  URB_IDLE = 0U,\r\n  URB_DONE,\r\n  URB_NOTREADY,\r\n  URB_NYET,\r\n  URB_ERROR,\r\n  URB_STALL\r\n    \r\n}USB_OTG_URBStateTypeDef;\r\n\r\n/** \r\n  * @brief  Host channel States  definition  \r\n  */ \r\ntypedef enum {\r\n  HC_IDLE = 0U,\r\n  HC_XFRC,\r\n  HC_HALTED,\r\n  HC_NAK,\r\n  HC_NYET,\r\n  HC_STALL,\r\n  HC_XACTERR,  \r\n  HC_BBLERR,   \r\n  HC_DATATGLERR\r\n    \r\n}USB_OTG_HCStateTypeDef;\r\n\r\n/** \r\n  * @brief  PCD Initialization Structure definition  \r\n  */\r\ntypedef struct\r\n{\r\n  uint32_t dev_endpoints;        /*!< Device Endpoints number.\r\n                                      This parameter depends on the used USB core.   \r\n                                      This parameter must be a number between Min_Data = 1 and Max_Data = 15 */    \r\n  \r\n  uint32_t Host_channels;        /*!< Host Channels number.\r\n                                      This parameter Depends on the used USB core.   \r\n                                      This parameter must be a number between Min_Data = 1 and Max_Data = 15 */       \r\n\r\n  uint32_t speed;                /*!< USB Core speed.\r\n                                      This parameter can be any value of @ref USB_Core_Speed_                */        \r\n                               \r\n  uint32_t dma_enable;           /*!< Enable or disable of the USB embedded DMA.                             */            \r\n\r\n  uint32_t ep0_mps;              /*!< Set the Endpoint 0 Max Packet size. \r\n                                      This parameter can be any value of @ref USB_EP0_MPS_                   */              \r\n                       \r\n  uint32_t phy_itface;           /*!< Select the used PHY interface.\r\n                                      This parameter can be any value of @ref USB_Core_PHY_                  */ \r\n                                \r\n  uint32_t Sof_enable;           /*!< Enable or disable the output of the SOF signal.                        */     \r\n                               \r\n  uint32_t low_power_enable;     /*!< Enable or disable the low power mode.                                  */\r\n  \r\n  uint32_t lpm_enable;           /*!< Enable or disable Link Power Management.                               */\r\n                          \r\n  uint32_t vbus_sensing_enable;  /*!< Enable or disable the VBUS Sensing feature.                            */ \r\n\r\n  uint32_t use_dedicated_ep1;    /*!< Enable or disable the use of the dedicated EP1 interrupt.              */      \r\n  \r\n  uint32_t use_external_vbus;    /*!< Enable or disable the use of the external VBUS.                        */   \r\n  \r\n}USB_OTG_CfgTypeDef;\r\n\r\ntypedef struct\r\n{\r\n  uint8_t   num;            /*!< Endpoint number\r\n                                This parameter must be a number between Min_Data = 1 and Max_Data = 15    */ \r\n                                \r\n  uint8_t   is_in;          /*!< Endpoint direction\r\n                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */ \r\n  \r\n  uint8_t   is_stall;       /*!< Endpoint stall condition\r\n                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */ \r\n  \r\n  uint8_t   type;           /*!< Endpoint type\r\n                                 This parameter can be any value of @ref USB_EP_Type_                     */ \r\n                                \r\n  uint8_t   data_pid_start; /*!< Initial data PID\r\n                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */\r\n                                \r\n  uint8_t   even_odd_frame; /*!< IFrame parity\r\n                                 This parameter must be a number between Min_Data = 0 and Max_Data = 1    */\r\n                                \r\n  uint16_t  tx_fifo_num;    /*!< Transmission FIFO number\r\n                                 This parameter must be a number between Min_Data = 1 and Max_Data = 15   */\r\n                                \r\n  uint32_t  maxpacket;      /*!< Endpoint Max packet size\r\n                                 This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */\r\n\r\n  uint8_t   *xfer_buff;     /*!< Pointer to transfer buffer                                               */\r\n                                \r\n  uint32_t  dma_addr;       /*!< 32 bits aligned transfer buffer address                                  */\r\n  \r\n  uint32_t  xfer_len;       /*!< Current transfer length                                                  */\r\n  \r\n  uint32_t  xfer_count;     /*!< Partial transfer length in case of multi packet transfer                 */\r\n\r\n}USB_OTG_EPTypeDef;\r\n\r\ntypedef struct\r\n{\r\n  uint8_t   dev_addr ;     /*!< USB device address.\r\n                                This parameter must be a number between Min_Data = 1 and Max_Data = 255    */ \r\n\r\n  uint8_t   ch_num;        /*!< Host channel number.\r\n                                This parameter must be a number between Min_Data = 1 and Max_Data = 15     */ \r\n                                \r\n  uint8_t   ep_num;        /*!< Endpoint number.\r\n                                This parameter must be a number between Min_Data = 1 and Max_Data = 15     */ \r\n                                \r\n  uint8_t   ep_is_in;      /*!< Endpoint direction\r\n                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */ \r\n                                \r\n  uint8_t   speed;         /*!< USB Host speed.\r\n                                This parameter can be any value of @ref USB_Core_Speed_                    */\r\n                                \r\n  uint8_t   do_ping;       /*!< Enable or disable the use of the PING protocol for HS mode.                */\r\n  \r\n  uint8_t   process_ping;  /*!< Execute the PING protocol for HS mode.                                     */\r\n\r\n  uint8_t   ep_type;       /*!< Endpoint Type.\r\n                                This parameter can be any value of @ref USB_EP_Type_                       */\r\n                                \r\n  uint16_t  max_packet;    /*!< Endpoint Max packet size.\r\n                                This parameter must be a number between Min_Data = 0 and Max_Data = 64KB   */\r\n                                \r\n  uint8_t   data_pid;      /*!< Initial data PID.\r\n                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */\r\n                                \r\n  uint8_t   *xfer_buff;    /*!< Pointer to transfer buffer.                                                */\r\n  \r\n  uint32_t  xfer_len;      /*!< Current transfer length.                                                   */\r\n  \r\n  uint32_t  xfer_count;    /*!< Partial transfer length in case of multi packet transfer.                  */\r\n  \r\n  uint8_t   toggle_in;     /*!< IN transfer current toggle flag.\r\n                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */\r\n                                \r\n  uint8_t   toggle_out;    /*!< OUT transfer current toggle flag\r\n                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */\r\n  \r\n  uint32_t  dma_addr;      /*!< 32 bits aligned transfer buffer address.                                   */\r\n  \r\n  uint32_t  ErrCnt;        /*!< Host channel error count.*/\r\n  \r\n  USB_OTG_URBStateTypeDef  urb_state;  /*!< URB state. \r\n                                           This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ \r\n  \r\n  USB_OTG_HCStateTypeDef   state;     /*!< Host Channel state. \r\n                                           This parameter can be any value of @ref USB_OTG_HCStateTypeDef  */ \r\n                                             \r\n}USB_OTG_HCTypeDef;\r\n  \r\n/* Exported constants --------------------------------------------------------*/\r\n\r\n/** @defgroup PCD_Exported_Constants PCD Exported Constants\r\n  * @{\r\n  */\r\n\r\n/** @defgroup USB_Core_Mode_ USB Core Mode\r\n  * @{\r\n  */\r\n#define USB_OTG_MODE_DEVICE                    0U\r\n#define USB_OTG_MODE_HOST                      1U\r\n#define USB_OTG_MODE_DRD                       2U\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USB_Core_Speed_   USB Core Speed\r\n  * @{\r\n  */  \r\n#define USB_OTG_SPEED_HIGH                     0U\r\n#define USB_OTG_SPEED_HIGH_IN_FULL             1U\r\n#define USB_OTG_SPEED_LOW                      2U  \r\n#define USB_OTG_SPEED_FULL                     3U\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup USB_Core_PHY_   USB Core PHY\r\n  * @{\r\n  */   \r\n#define USB_OTG_ULPI_PHY                       1U\r\n#define USB_OTG_EMBEDDED_PHY                   2U\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup USB_Core_MPS_   USB Core MPS\r\n  * @{\r\n  */\r\n#define USB_OTG_HS_MAX_PACKET_SIZE           512U\r\n#define USB_OTG_FS_MAX_PACKET_SIZE           64U\r\n#define USB_OTG_MAX_EP0_SIZE                 64U\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USB_Core_Phy_Frequency_   USB Core Phy Frequency\r\n  * @{\r\n  */\r\n#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ     (0 << 1)\r\n#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ     (1 << 1)\r\n#define DSTS_ENUMSPD_LS_PHY_6MHZ               (2 << 1)\r\n#define DSTS_ENUMSPD_FS_PHY_48MHZ              (3 << 1)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup USB_CORE_Frame_Interval_   USB CORE Frame Interval\r\n  * @{\r\n  */  \r\n#define DCFG_FRAME_INTERVAL_80                 0U\r\n#define DCFG_FRAME_INTERVAL_85                 1U\r\n#define DCFG_FRAME_INTERVAL_90                 2U\r\n#define DCFG_FRAME_INTERVAL_95                 3U\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USB_EP0_MPS_  USB EP0 MPS\r\n  * @{\r\n  */\r\n#define DEP0CTL_MPS_64                         0U\r\n#define DEP0CTL_MPS_32                         1U\r\n#define DEP0CTL_MPS_16                         2U\r\n#define DEP0CTL_MPS_8                          3U\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USB_EP_Speed_  USB EP Speed\r\n  * @{\r\n  */\r\n#define EP_SPEED_LOW                           0U\r\n#define EP_SPEED_FULL                          1U\r\n#define EP_SPEED_HIGH                          2U\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USB_EP_Type_  USB EP Type\r\n  * @{\r\n  */\r\n#define EP_TYPE_CTRL                           0U\r\n#define EP_TYPE_ISOC                           1U\r\n#define EP_TYPE_BULK                           2U\r\n#define EP_TYPE_INTR                           3U\r\n#define EP_TYPE_MSK                            3U\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USB_STS_Defines_   USB STS Defines\r\n  * @{\r\n  */\r\n#define STS_GOUT_NAK                           1U\r\n#define STS_DATA_UPDT                          2U\r\n#define STS_XFER_COMP                          3U\r\n#define STS_SETUP_COMP                         4U\r\n#define STS_SETUP_UPDT                         6U\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HCFG_SPEED_Defines_   HCFG SPEED Defines\r\n  * @{\r\n  */  \r\n#define HCFG_30_60_MHZ                         0U\r\n#define HCFG_48_MHZ                            1U\r\n#define HCFG_6_MHZ                             2U\r\n/**\r\n  * @}\r\n  */\r\n    \r\n/** @defgroup HPRT0_PRTSPD_SPEED_Defines_  HPRT0 PRTSPD SPEED Defines\r\n  * @{\r\n  */    \r\n#define HPRT0_PRTSPD_HIGH_SPEED                0U\r\n#define HPRT0_PRTSPD_FULL_SPEED                1U\r\n#define HPRT0_PRTSPD_LOW_SPEED                 2U\r\n/**\r\n  * @}\r\n  */  \r\n   \r\n#define HCCHAR_CTRL                            0U\r\n#define HCCHAR_ISOC                            1U\r\n#define HCCHAR_BULK                            2U\r\n#define HCCHAR_INTR                            3U\r\n       \r\n#define HC_PID_DATA0                           0U\r\n#define HC_PID_DATA2                           1U\r\n#define HC_PID_DATA1                           2U\r\n#define HC_PID_SETUP                           3U\r\n\r\n#define GRXSTS_PKTSTS_IN                       2U\r\n#define GRXSTS_PKTSTS_IN_XFER_COMP             3U\r\n#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR          5U\r\n#define GRXSTS_PKTSTS_CH_HALTED                7U\r\n    \r\n#define USBx_PCGCCTL    *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE)\r\n#define USBx_HPRT0      *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE)\r\n\r\n#define USBx_DEVICE     ((USB_OTG_DeviceTypeDef *)((uint32_t )USBx + USB_OTG_DEVICE_BASE)) \r\n#define USBx_INEP(i)    ((USB_OTG_INEndpointTypeDef *)((uint32_t)USBx + USB_OTG_IN_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))        \r\n#define USBx_OUTEP(i)   ((USB_OTG_OUTEndpointTypeDef *)((uint32_t)USBx + USB_OTG_OUT_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))        \r\n#define USBx_DFIFO(i)   *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_FIFO_BASE + (i) * USB_OTG_FIFO_SIZE)\r\n\r\n#define USBx_HOST       ((USB_OTG_HostTypeDef *)((uint32_t )USBx + USB_OTG_HOST_BASE))  \r\n#define USBx_HC(i)      ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE))\r\n/**\r\n  * @}\r\n  */\r\n/* Exported macro ------------------------------------------------------------*/\r\n#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)     ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))\r\n#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)   ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))\r\n    \r\n#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__)          (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))\r\n#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__)         (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))  \r\n\r\n/* Exported functions --------------------------------------------------------*/\r\nHAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);\r\nHAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);\r\nHAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);\r\nHAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);\r\nHAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode);\r\nHAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed);\r\nHAL_StatusTypeDef USB_FlushRxFifo (USB_OTG_GlobalTypeDef *USBx);\r\nHAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num );\r\nHAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);\r\nHAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);\r\nHAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);\r\nHAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);\r\nHAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);\r\nHAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);\r\nHAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma);\r\nvoid *            USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);\r\nHAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);\r\nHAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);\r\nHAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address);\r\nHAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx);\r\nHAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx);\r\nHAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);\r\nHAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx);\r\nHAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup);\r\nuint8_t           USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);\r\nuint32_t          USB_GetMode(USB_OTG_GlobalTypeDef *USBx);\r\nuint32_t          USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx);\r\nuint32_t          USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx);\r\nuint32_t          USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);\r\nuint32_t          USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx);\r\nuint32_t          USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);\r\nvoid              USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);\r\n\r\nHAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);\r\nHAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq);\r\nHAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);\r\nHAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state);\r\nuint32_t          USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx);\r\nuint32_t          USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx);\r\nHAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,  \r\n                                  uint8_t ch_num,\r\n                                  uint8_t epnum,\r\n                                  uint8_t dev_address,\r\n                                  uint8_t speed,\r\n                                  uint8_t ep_type,\r\n                                  uint16_t mps);\r\nHAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma);\r\nuint32_t          USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx);\r\nHAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num);\r\nHAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num);\r\nHAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n\r\n#endif /* __STM32F7xx_LL_USB_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
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span.MsoHyperlinkFollowed\r\n{mso-style-unhide:no;\r\ncolor:blue;\r\ntext-decoration:underline;\r\ntext-underline:single;}\r\np\r\n{mso-style-unhide:no;\r\nmso-margin-top-alt:auto;\r\nmargin-right:0in;\r\nmso-margin-bottom-alt:auto;\r\nmargin-left:0in;\r\nmso-pagination:widow-orphan;\r\nfont-size:12.0pt;\r\nfont-family:\"Times New Roman\",\"serif\";\r\nmso-fareast-font-family:\"Times New Roman\";}\r\np.MsoAcetate, li.MsoAcetate, div.MsoAcetate\r\n{mso-style-unhide:no;\r\nmso-style-link:\"Balloon Text Char\";\r\nmargin:0in;\r\nmargin-bottom:.0001pt;\r\nmso-pagination:widow-orphan;\r\nfont-size:8.0pt;\r\nfont-family:\"Tahoma\",\"sans-serif\";\r\nmso-fareast-font-family:\"Times New Roman\";}\r\nspan.Heading1Char\r\n{mso-style-name:\"Heading 1 Char\";\r\nmso-style-unhide:no;\r\nmso-style-locked:yes;\r\nmso-style-link:\"Heading 1\";\r\nmso-ansi-font-size:14.0pt;\r\nmso-bidi-font-size:14.0pt;\r\nfont-family:\"Cambria\",\"serif\";\r\nmso-ascii-font-family:Cambria;\r\nmso-ascii-theme-font:major-latin;\r\nmso-fareast-font-family:\"Times New Roman\";\r\nmso-fareast-theme-font:major-fareast;\r\nmso-hansi-font-family:Cambria;\r\nmso-hansi-theme-font:major-latin;\r\nmso-bidi-font-family:\"Times New Roman\";\r\nmso-bidi-theme-font:major-bidi;\r\ncolor:#365F91;\r\nmso-themecolor:accent1;\r\nmso-themeshade:191;\r\nfont-weight:bold;}\r\nspan.Heading2Char\r\n{mso-style-name:\"Heading 2 Char\";\r\nmso-style-unhide:no;\r\nmso-style-locked:yes;\r\nmso-style-link:\"Heading 2\";\r\nmso-ansi-font-size:13.0pt;\r\nmso-bidi-font-size:13.0pt;\r\nfont-family:\"Cambria\",\"serif\";\r\nmso-ascii-font-family:Cambria;\r\nmso-ascii-theme-font:major-latin;\r\nmso-fareast-font-family:\"Times New Roman\";\r\nmso-fareast-theme-font:major-fareast;\r\nmso-hansi-font-family:Cambria;\r\nmso-hansi-theme-font:major-latin;\r\nmso-bidi-font-family:\"Times New Roman\";\r\nmso-bidi-theme-font:major-bidi;\r\ncolor:#4F81BD;\r\nmso-themecolor:accent1;\r\nfont-weight:bold;}\r\nspan.Heading3Char\r\n{mso-style-name:\"Heading 3 Char\";\r\nmso-style-unhide:no;\r\nmso-style-locked:yes;\r\nmso-style-link:\"Heading 3\";\r\nmso-ansi-font-size:12.0pt;\r\nmso-bidi-font-size:12.0pt;\r\nfont-family:\"Cambria\",\"serif\";\r\nmso-ascii-font-family:Cambria;\r\nmso-ascii-theme-font:major-latin;\r\nmso-fareast-font-family:\"Times New Roman\";\r\nmso-fareast-theme-font:major-fareast;\r\nmso-hansi-font-family:Cambria;\r\nmso-hansi-theme-font:major-latin;\r\nmso-bidi-font-family:\"Times New Roman\";\r\nmso-bidi-theme-font:major-bidi;\r\ncolor:#4F81BD;\r\nmso-themecolor:accent1;\r\nfont-weight:bold;}\r\nspan.BalloonTextChar\r\n{mso-style-name:\"Balloon Text Char\";\r\nmso-style-unhide:no;\r\nmso-style-locked:yes;\r\nmso-style-link:\"Balloon Text\";\r\nmso-ansi-font-size:8.0pt;\r\nmso-bidi-font-size:8.0pt;\r\nfont-family:\"Tahoma\",\"sans-serif\";\r\nmso-ascii-font-family:Tahoma;\r\nmso-hansi-font-family:Tahoma;\r\nmso-bidi-font-family:Tahoma;}\r\n.MsoChpDefault\r\n{mso-style-type:export-only;\r\nmso-default-props:yes;\r\nfont-size:10.0pt;\r\nmso-ansi-font-size:10.0pt;\r\nmso-bidi-font-size:10.0pt;}\r\n@page WordSection1\r\n{size:8.5in 11.0in;\r\nmargin:1.0in 1.25in 1.0in 1.25in;\r\nmso-header-margin:.5in;\r\nmso-footer-margin:.5in;\r\nmso-paper-source:0;}\r\ndiv.WordSection1\r\n{page:WordSection1;}\r\n/* List Definitions */\r\n@list l0\r\n{mso-list-id:62067358;\r\nmso-list-template-ids:-174943062;}\r\n@list l0:level1\r\n{mso-level-number-format:bullet;\r\nmso-level-text:\\F0B7;\r\nmso-level-tab-stop:.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;\r\nmso-ansi-font-size:10.0pt;\r\nfont-family:Symbol;}\r\n@list l0:level2\r\n{mso-level-tab-stop:1.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l0:level3\r\n{mso-level-tab-stop:1.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l0:level4\r\n{mso-level-tab-stop:2.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l0:level5\r\n{mso-level-tab-stop:2.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l0:level6\r\n{mso-level-tab-stop:3.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l0:level7\r\n{mso-level-tab-stop:3.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l0:level8\r\n{mso-level-tab-stop:4.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l0:level9\r\n{mso-level-tab-stop:4.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l1\r\n{mso-list-id:128015942;\r\nmso-list-template-ids:-90681214;}\r\n@list l1:level1\r\n{mso-level-tab-stop:.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l1:level2\r\n{mso-level-tab-stop:1.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l1:level3\r\n{mso-level-tab-stop:1.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l1:level4\r\n{mso-level-tab-stop:2.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l1:level5\r\n{mso-level-tab-stop:2.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l1:level6\r\n{mso-level-tab-stop:3.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l1:level7\r\n{mso-level-tab-stop:3.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l1:level8\r\n{mso-level-tab-stop:4.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l1:level9\r\n{mso-level-tab-stop:4.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l2\r\n{mso-list-id:216556000;\r\nmso-list-template-ids:925924412;}\r\n@list l2:level1\r\n{mso-level-number-format:bullet;\r\nmso-level-text:\\F0B7;\r\nmso-level-tab-stop:.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;\r\nmso-ansi-font-size:10.0pt;\r\nfont-family:Symbol;}\r\n@list l2:level2\r\n{mso-level-number-format:bullet;\r\nmso-level-text:\\F0B7;\r\nmso-level-tab-stop:1.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;\r\nmso-ansi-font-size:10.0pt;\r\nfont-family:Symbol;}\r\n@list l2:level3\r\n{mso-level-tab-stop:1.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l2:level4\r\n{mso-level-tab-stop:2.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l2:level5\r\n{mso-level-tab-stop:2.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l2:level6\r\n{mso-level-tab-stop:3.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l2:level7\r\n{mso-level-tab-stop:3.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l2:level8\r\n{mso-level-tab-stop:4.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l2:level9\r\n{mso-level-tab-stop:4.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l3\r\n{mso-list-id:562446694;\r\nmso-list-template-ids:913898366;}\r\n@list l3:level1\r\n{mso-level-number-format:bullet;\r\nmso-level-text:\\F0B7;\r\nmso-level-tab-stop:.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;\r\nmso-ansi-font-size:10.0pt;\r\nfont-family:Symbol;}\r\n@list l3:level2\r\n{mso-level-tab-stop:1.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l3:level3\r\n{mso-level-tab-stop:1.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l3:level4\r\n{mso-level-tab-stop:2.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l3:level5\r\n{mso-level-tab-stop:2.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l3:level6\r\n{mso-level-tab-stop:3.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l3:level7\r\n{mso-level-tab-stop:3.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l3:level8\r\n{mso-level-tab-stop:4.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l3:level9\r\n{mso-level-tab-stop:4.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l4\r\n{mso-list-id:797802132;\r\nmso-list-template-ids:-1971191336;}\r\n@list l4:level1\r\n{mso-level-tab-stop:.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l4:level2\r\n{mso-level-tab-stop:1.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l4:level3\r\n{mso-level-tab-stop:1.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l4:level4\r\n{mso-level-tab-stop:2.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l4:level5\r\n{mso-level-tab-stop:2.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l4:level6\r\n{mso-level-tab-stop:3.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l4:level7\r\n{mso-level-tab-stop:3.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l4:level8\r\n{mso-level-tab-stop:4.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l4:level9\r\n{mso-level-tab-stop:4.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l5\r\n{mso-list-id:907304066;\r\nmso-list-template-ids:1969781532;}\r\n@list l5:level1\r\n{mso-level-tab-stop:.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l5:level2\r\n{mso-level-tab-stop:1.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l5:level3\r\n{mso-level-tab-stop:1.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l5:level4\r\n{mso-level-tab-stop:2.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l5:level5\r\n{mso-level-tab-stop:2.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l5:level6\r\n{mso-level-tab-stop:3.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l5:level7\r\n{mso-level-tab-stop:3.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l5:level8\r\n{mso-level-tab-stop:4.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l5:level9\r\n{mso-level-tab-stop:4.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l6\r\n{mso-list-id:1050613616;\r\nmso-list-template-ids:-1009886748;}\r\n@list l6:level1\r\n{mso-level-number-format:bullet;\r\nmso-level-text:\\F0B7;\r\nmso-level-tab-stop:.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;\r\nmso-ansi-font-size:10.0pt;\r\nfont-family:Symbol;}\r\n@list l6:level2\r\n{mso-level-number-format:bullet;\r\nmso-level-text:\\F0B7;\r\nmso-level-tab-stop:1.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;\r\nmso-ansi-font-size:10.0pt;\r\nfont-family:Symbol;}\r\n@list l6:level3\r\n{mso-level-tab-stop:1.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l6:level4\r\n{mso-level-tab-stop:2.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l6:level5\r\n{mso-level-tab-stop:2.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l6:level6\r\n{mso-level-tab-stop:3.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l6:level7\r\n{mso-level-tab-stop:3.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l6:level8\r\n{mso-level-tab-stop:4.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l6:level9\r\n{mso-level-tab-stop:4.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l7\r\n{mso-list-id:1234970193;\r\nmso-list-template-ids:2055904002;}\r\n@list l7:level1\r\n{mso-level-number-format:bullet;\r\nmso-level-text:\\F0B7;\r\nmso-level-tab-stop:.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;\r\nmso-ansi-font-size:10.0pt;\r\nfont-family:Symbol;}\r\n@list l7:level2\r\n{mso-level-number-format:bullet;\r\nmso-level-text:\\F0B7;\r\nmso-level-tab-stop:1.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;\r\nmso-ansi-font-size:10.0pt;\r\nfont-family:Symbol;}\r\n@list l7:level3\r\n{mso-level-tab-stop:1.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l7:level4\r\n{mso-level-tab-stop:2.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l7:level5\r\n{mso-level-tab-stop:2.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l7:level6\r\n{mso-level-tab-stop:3.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l7:level7\r\n{mso-level-tab-stop:3.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l7:level8\r\n{mso-level-tab-stop:4.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l7:level9\r\n{mso-level-tab-stop:4.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l8\r\n{mso-list-id:1846092290;\r\nmso-list-template-ids:-768590846;}\r\n@list l8:level1\r\n{mso-level-start-at:2;\r\nmso-level-tab-stop:.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l8:level2\r\n{mso-level-tab-stop:1.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l8:level3\r\n{mso-level-tab-stop:1.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l8:level4\r\n{mso-level-tab-stop:2.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l8:level5\r\n{mso-level-tab-stop:2.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l8:level6\r\n{mso-level-tab-stop:3.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l8:level7\r\n{mso-level-tab-stop:3.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l8:level8\r\n{mso-level-tab-stop:4.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l8:level9\r\n{mso-level-tab-stop:4.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l9\r\n{mso-list-id:1894656566;\r\nmso-list-template-ids:1199983812;}\r\n@list l9:level1\r\n{mso-level-start-at:2;\r\nmso-level-tab-stop:.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l9:level2\r\n{mso-level-tab-stop:1.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l9:level3\r\n{mso-level-tab-stop:1.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l9:level4\r\n{mso-level-tab-stop:2.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l9:level5\r\n{mso-level-tab-stop:2.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l9:level6\r\n{mso-level-tab-stop:3.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l9:level7\r\n{mso-level-tab-stop:3.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l9:level8\r\n{mso-level-tab-stop:4.0in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\n@list l9:level9\r\n{mso-level-tab-stop:4.5in;\r\nmso-level-number-position:left;\r\ntext-indent:-.25in;}\r\nol\r\n{margin-bottom:0in;}\r\nul\r\n{margin-bottom:0in;}\r\n-->\r\n</style><!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:\"Table Normal\"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:\"\"; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:\"Times New Roman\",\"serif\";} </style> <![endif]--><!--[if gte mso 9]><xml> <o:shapedefaults v:ext=\"edit\" spidmax=\"7170\"/> </xml><![endif]--><!--[if gte mso 9]><xml> <o:shapelayout v:ext=\"edit\"> <o:idmap v:ext=\"edit\" data=\"1\"/> </o:shapelayout></xml><![endif]-->\r\n<meta content=\"MCD Application Team\" name=\"author\"></head>\r\n<body link=\"blue\" vlink=\"blue\">\r\n<div class=\"WordSection1\">\r\n<p class=\"MsoNormal\"><span style=\"font-family: &quot;Arial&quot;,&quot;sans-serif&quot;;\"><o:p>&nbsp;</o:p></span></p>\r\n<div align=\"center\">\r\n<table class=\"MsoNormalTable\" style=\"width: 675pt;\" border=\"0\" cellpadding=\"0\" cellspacing=\"0\" width=\"900\">\r\n<tbody>\r\n<tr style=\"\">\r\n<td style=\"padding: 0in;\" valign=\"top\">\r\n<table class=\"MsoNormalTable\" style=\"width: 675pt;\" border=\"0\" cellpadding=\"0\" cellspacing=\"0\" width=\"900\">\r\n<tbody>\r\n<tr style=\"\">\r\n<td style=\"padding: 0in 5.4pt;\" valign=\"top\">\r\n<p class=\"MsoNormal\"><span style=\"font-size: 8pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: blue;\"><a href=\"../../Release_Notes.html\">Back to Release page</a></span><span style=\"font-size: 10pt;\"><o:p></o:p></span></p>\r\n</td>\r\n</tr>\r\n<tr style=\"\">\r\n<td style=\"padding: 1.5pt;\">\r\n<h1 style=\"margin-bottom: 0.25in; text-align: center;\" align=\"center\"><span style=\"font-size: 20pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: rgb(51, 102, 255);\">Release\r\nNotes for STM32F7xx HAL Drivers</span><span style=\"font-size: 20pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\"><o:p></o:p></span></h1>\r\n<p class=\"MsoNormal\" style=\"text-align: center;\" align=\"center\"><span style=\"font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;\">Copyright\r\n2016 STMicroelectronics</span><span style=\"color: black;\"><u1:p></u1:p><o:p></o:p></span></p>\r\n<p class=\"MsoNormal\" style=\"text-align: center;\" align=\"center\"><span style=\"font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;\"><img style=\"border: 0px solid ; width: 171px; height: 126px;\" alt=\"\" id=\"_x0000_i1026\" src=\"../../_htmresc/st_logo.png\"></span><span style=\"font-size: 10pt;\"><o:p></o:p></span></p>\r\n</td>\r\n</tr>\r\n</tbody>\r\n</table>\r\n<p class=\"MsoNormal\"><span style=\"font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; display: none;\"><o:p>&nbsp;</o:p></span></p>\r\n<table class=\"MsoNormalTable\" style=\"width: 675pt;\" border=\"0\" cellpadding=\"0\" width=\"900\">\r\n<tbody>\r\n<tr style=\"\">\r\n<td style=\"padding: 0in;\" valign=\"top\">\r\n<h2 style=\"background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;\"><a name=\"History\"></a><span style=\"font-size: 12pt; color: white;\">Update History</span></h2>\r\n<h3 style=\"background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;\"><span style=\"font-size: 10pt; font-family: Arial; color: white;\">V1.1.0 / 22-April-2016</span></h3>\r\n<p class=\"MsoNormal\" style=\"margin: 4.5pt 0cm 4.5pt 18pt;\"><b style=\"\"><u><span style=\"font-size: 10pt; font-family: Verdana; color: black;\">Main\r\nChanges</span></u></b></p><ul style=\"margin-top: 0cm;\" type=\"square\"><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Official release to add the support of <span style=\"font-weight: bold;\">STM32F765xx, STM32F767xx, STM32F768xx, STM32F769xx, STM32F777xx, STM32F778xx</span> <span style=\"font-weight: bold;\">and STM32F779xx</span> devices<br></span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">General updates \r\nto fix known defects and enhancements implementation</span></li><li class=\"MsoNormal\" style=\"margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;\"><span style=\"font-size: 10pt; font-family: Verdana,sans-serif;\">Add new HAL drivers for<span class=\"Apple-converted-space\"> </span><span style=\"font-weight: bold;\">DFSDM, DSI<span class=\"Apple-converted-space\">, JPEG </span></span>and<span class=\"Apple-converted-space\"> </span><span style=\"font-weight: bold;\">MDIOS<span class=\"Apple-converted-space\"> </span></span>peripherals</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Enhance HAL delay and timebase implementation</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Add new \r\ndrivers stm32f7xx_hal_timebase_tim_template.c, stm32f7xx_hal_timebase_rtc_alarm_template.c and \r\nstm32f7xx_hal_timebase_rtc_wakeup_template.c which override the native HAL time \r\nbase functions (defined as weak) to either use the TIM or the RTC as time base tick source. For \r\nmore details about the usage of these drivers, please refer to HAL\\HAL_TimeBase \r\nexamples&nbsp;</span><span style=\"color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;\">and FreeRTOS-based applications</span></li></ul></ul><ul style=\"margin-top: 0cm;\" type=\"square\"><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-weight: bold;\">The following changes done on the HAL drivers require an update on the \r\napplication code based on HAL V1.0.4</span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"></span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\">HAL UART, USART, IRDA, SMARTCARD, SPI, I2C,&nbsp;QSPI </span></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\"></span>(referenced as <span style=\"font-style: italic;\">PPP</span> here below)<span style=\"font-style: italic;\"></span></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\"> </span>drivers</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"></span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Add PPP error management during DMA process. This requires the following updates on&nbsp;</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">user application:</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Configure and enable \r\nthe PPP IRQ in HAL_PPP_MspInit() function<br></span></li></ul><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">In </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">stm32f7xx_it.c file, \r\n</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">PPP_IRQHandler() \r\nfunction: </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">add a call to \r\nHAL_PPP_IRQHandler() function</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add and customize \r\nthe Error Callback API: HAL_PPP_ErrorCallback()<br></span></li></ul></ul></ul></ul>\r\n<ul><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\">HAL I2C</span><span style=\"font-style: italic;\"></span></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\"></span> (referenced as <span style=\"font-style: italic;\">PPP</span> here below)<span style=\"font-style: italic;\"></span></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\"> </span>drivers:</span>\r\n<ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update to avoid waiting on </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">STOPF/BTF/AF flag under DMA ISR by using the </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">PPP end of transfer interrupt in the </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">DMA transfer process.</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"> This requires the following updates on&nbsp;</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">user application</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">:</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Configure and enable \r\nthe PPP IRQ in HAL_PPP_MspInit() function<br></span></li></ul></ul>\r\n<ul><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">In </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">stm32f7xx_it.c file, \r\n</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">PPP_IRQHandler() \r\nfunction: </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">add a call to \r\nHAL_PPP_IRQHandler() function</span></li></ul></ul></li></ul></ul>\r\n<ul><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\">HAL IWDG</span></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\"> </span>driver: rework overall driver for better implementation</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Remove&nbsp;</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_IWDG_Start(), </span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_IWDG_MspInit() and </span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_IWDG_GetState()&nbsp;</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">APIs</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\">HAL WWDG</span></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\"> </span>driver: rework overall driver for better implementation</span>\r\n<ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Remove HAL_WWDG_Start(), </span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_WWDG_Start_IT(),</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"> \r\nHAL_WWDG_MspDeInit() and </span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_WWDG_GetState() APIs&nbsp;</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Update the&nbsp;</span><span style=\"font-family: 'Calibri',sans-serif; font-size: 11pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Calibri',sans-serif; font-size: 11pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Calibri',sans-serif; font-size: 11pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Calibri',sans-serif; font-size: 11pt;\" lang=\"EN-US\">HAL_WWDG_Refresh</span><span style=\"font-family: 'Calibri',sans-serif; font-size: 11pt;\" lang=\"EN-US\">(WWDG_HandleTypeDef *hwwdg, uint32_t counter) &nbsp;function and API &nbsp;by removing the &nbsp;\"counter\" parameter</span><span style=\"font-family: 'Calibri',sans-serif; font-size: 11pt;\" lang=\"EN-US\"></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\"></span></span></li></ul></li></ul></ul><ul style=\"margin-top: 0cm;\" type=\"square\"><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\">HAL QSPI driver: </span>&nbsp;Enhance the DMA transmit process by&nbsp;using&nbsp;PPP TC interrupt instead of waiting on TC flag under DMA ISR.&nbsp;</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">This requires the following updates on&nbsp;</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">user application</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">:</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Configure and enable \r\nthe QSPI&nbsp;IRQ in HAL_QSPI_MspInit() function</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">In </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">stm32f7xx_it.c file, </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">QSPI_IRQHandler() \r\nfunction: </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">add a call to \r\nHAL_QSPI_IRQHandler() function</span></li></ul></ul></ul>\r\n<ul style=\"margin-bottom: 0in; list-style-type: square;\"><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\"></span></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\"></span></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\">HAL CEC driver: </span>&nbsp;Overall driver rework with compatibility break versus previous HAL version</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Remove HAL CEC polling Process functions: HAL_CEC_Transmit() and HAL_CEC_Receive()</span><span style=\"font-family: 'Times New Roman',serif; font-size: 12pt;\" lang=\"EN-US\"><o:p></o:p></span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Remove\r\nHAL CEC receive interrupt process function&nbsp;HAL_CEC_Receive_IT()\r\nand enable the \"receive\" &nbsp;mode during the Init phase</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Rename&nbsp;HAL_CEC_GetReceivedFrameSize() funtion to&nbsp;HAL_CEC_GetLastReceivedFrameSize()<br></span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Add new HAL APIs: HAL_CEC_SetDeviceAddress() and  \r\nHAL_CEC_ChangeRxBuffer()</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Remove the&nbsp;<span></span>'InitiatorAddress' field from the&nbsp;CEC_InitTypeDef \r\nstructure&nbsp;and manage it&nbsp;as a parameter in the HAL_CEC_Transmit_IT() function</span><span style=\"font-family: 'Times New Roman',serif; font-size: 12pt;\" lang=\"EN-US\"><o:p></o:p></span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Add new parameter 'RxFrameSize' in HAL_CEC_RxCpltCallback() function</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Move CEC Rx buffer pointer&nbsp;from CEC_HandleTypeDef structure to \r\nCEC_InitTypeDef structure</span></li></ul></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL CAN</span> update&nbsp;</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Add the support of CAN3</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL CEC</span> update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Overall driver rework with&nbsp;break of compatibility with HAL \r\nV1.0.4<br></span></li></ul><ul><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Remove the HAL CEC polling Process: HAL_CEC_Transmit() and HAL_CEC_Receive()</span><span style=\"font-family: 'Times New Roman',serif; font-size: 12pt;\" lang=\"EN-US\"><o:p></o:p></span></li></ul></ul></ul>\r\n<ul style=\"margin-top: 0cm;\" type=\"disc\"><ul style=\"margin-top: 0cm;\" type=\"circle\"><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Remove the HAL CEC receive interrupt process (HAL_CEC_Receive_IT()) and manage the \"Receive\" mode enable within the Init phase</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Rename HAL_CEC_GetReceivedFrameSize() function to&nbsp;HAL_CEC_GetLastReceivedFrameSize() function<br></span></li></ul><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Add new HAL APIs: HAL_CEC_SetDeviceAddress() and  \r\nHAL_CEC_ChangeRxBuffer()</span></li></ul><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Remove the&nbsp;<span></span>'InitiatorAddress' field from the&nbsp;CEC_InitTypeDef \r\nstructure&nbsp;and manage it&nbsp;as a parameter in the HAL_CEC_Transmit_IT() function</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span></li></ul><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Add new parameter 'RxFrameSize' in HAL_CEC_RxCpltCallback() function</span><span style=\"font-family: 'Times New Roman',serif; font-size: 12pt;\" lang=\"EN-US\"><o:p></o:p></span></li></ul><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Move CEC Rx buffer pointer&nbsp;from CEC_HandleTypeDef structure to \r\nCEC_InitTypeDef structure</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"> <o:p></o:p></span></li></ul></ul></ul>\r\n<ul style=\"text-transform: none; margin-top: 0cm; text-indent: 0px; letter-spacing: normal; font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; font-size: medium; line-height: normal; font-size-adjust: none; font-stretch: normal; white-space: normal; margin-bottom: 0in; color: rgb(0, 0, 0); word-spacing: 0px;\" type=\"square\"><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update driver to implement the new CEC state machine: </span></li></ul><ul><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Add new&nbsp;</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">\"rxState\"</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"> field in \r\nCEC_HandleTypeDef structure to provide the </span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">CEC \r\n</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">state \r\ninformation related to Rx Operations</span></li></ul><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Rename \"state\" \r\nfield in CEC_HandleTypeDef structure to \"gstate\": CEC </span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">state information \r\nrelated to global Handle management and Tx Operations</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update CEC process \r\nto manage the new CEC states.</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; color: black; font-size: 10pt;\" lang=\"EN-US\">Update __HAL_CEC_RESET_HANDLE_STATE() macro to handle the new CEC \r\nstate parameters (gState, rxState)</span><br></li></ul></ul></ul><ul style=\"margin-bottom: 0in; list-style-type: square;\"><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL DMA</span> update&nbsp;</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add\r\nnew APIs HAL_DMA_RegisterCallback() and HAL_DMA_UnRegisterCallback to\r\nregister/unregister the different callbacks identified by\r\nthe enum typedef HAL_DMA_CallbackIDTypeDef</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add new API HAL_DMA_Abort_IT() to abort DMA transfer under interrupt context<br></span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">The new registered Abort callback is called when DMA transfer abortion is completed</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add the check of \r\ncompatibility between FIFO threshold level and size of the memory burst in the \r\nHAL_DMA_Init() API</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add new Error Codes: \r\nHAL_DMA_ERROR_PARAM, HAL_DMA_ERROR_NO_XFER and \r\nHAL_DMA_ERROR_NOT_SUPPORTED</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Remove all DMA states \r\nrelated to MEM0/MEM1 in HAL_DMA_StateTypeDef</span><span style=\"font-family: 'Helvetica',sans-serif; color: rgb(98, 98, 98); font-size: 9.5pt;\" lang=\"EN-US\"><o:p></o:p></span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL DMA2D</span> update&nbsp;</span></li><ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update the \r\nHAL_DMA2D_DeInit() function to:</span>\r\n<ul style=\"margin-bottom: 0in;\"><li style=\"margin: 4.5pt 0in; list-style-type: square; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Abort transfer in case \r\nof ongoing DMA2D transfer</span></li></ul>\r\n<ul><li><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Reset DMA2D control \r\nregisters</span></li></ul></li><li><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update \r\nHAL_DMA2D_Abort() to disable DMA2D interrupts after stopping transfer</span></li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Optimize \r\nHAL_DMA2D_IRQHandler() by reading status registers only once</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update \r\nHAL_DMA2D_ProgramLineEvent() function to:</span>\r\n<ul style=\"margin-bottom: 0in;\"><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Return HAL error state \r\nin case of wrong line value</span></li></ul>\r\n<ul style=\"margin-bottom: 0in;\"><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Enable line interrupt \r\nafter setting the line watermark configuration</span></li></ul></li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add new HAL_DMA2D_CLUTLoad() and </span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">HAL_DMA2D_CLUTLoad_IT()</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"> \r\nfunctions to start DMA2D CLUT loading</span></li><ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_DMA2D_CLUTLoading_Abort() \r\nfunction to abort the DMA2D CLUT loading</span></li></ul><ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_DMA2D_CLUTLoading_Suspend() \r\nfunction to suspend the DMA2D CLUT loading</span></li></ul><ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_DMA2D_CLUTLoading_Resume() \r\nfunction to resume the DMA2D CLUT loading</span></li></ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add new DMA2D dead time \r\nmanagement:</span></li><ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_DMA2D_EnableDeadTime() \r\nfunction to enable DMA2D dead time feature</span></li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_DMA2D_DisableDeadTime() \r\nfunction to disable DMA2D dead time feature</span></li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_DMA2D_ConfigDeadTime() \r\nfunction to configure dead time</span></li></ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update the name of \r\nDMA2D Input/Output color mode defines to be more clear for user (DMA2D_INPUT_XXX \r\nfor input layers Colors, DMA2D_OUTPUT_XXX for output framebuffer \r\nColors)</span></li></ul></ul>\r\n\r\n<ul style=\"margin-top: 0cm;\" type=\"square\"><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL DCMI</span> update&nbsp;</span></li><ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Rename DCMI_DMAConvCplt \r\nto DCMI_DMAXferCplt</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_DCMI_Start_DMA() function to&nbsp;</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Enable the DCMI peripheral</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add new timeout \r\nimplementation based on cpu cycles for DCMI stop</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add HAL_DCMI_Suspend() \r\nfunction to suspend DCMI capture</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add HAL_DCMI_Resume() \r\nfunction to resume capture after DCMI suspend</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update lock mechanism \r\nfor DCMI process</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update HAL_DCMI_IRQHandler() function to:</span>\r\n<ul style=\"margin-bottom: 0in;\"><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add error management in \r\ncase DMA errors through XferAbortCallback() and \r\nHAL_DMA_Abort_IT()</span></li></ul>\r\n<ul style=\"margin-bottom: 0in;\"><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Optimize code by using \r\ndirect register read</span></li></ul></li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Move\r\nthe content of the stm32f7xx_hal_dcmi_ex.c/.h files to common driver\r\nfiles (the extension files are kept empty for projects compatibility\r\nreason)</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"></span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL FLASH</span> update&nbsp;</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Add the support of Dual BANK feature</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Add __HAL_FLASH_CALC_BOOT_BASE_ADR() macro to calculate the FLASH Boot Base Adress</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Move Flash total sector define to CMSIS header files</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL FMC</span> update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update FMC_NORSRAM_Init() to remove the Burst access mode configuration</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update FMC_SDRAM_Timing_Init() to fix initialization issue when configuring 2 SDRAM banks<br></span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL HCD</span> update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update HCD_Port_IRQHandler() to be compliant with new Time base implementation</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><b><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL \r\nI2C</span></b><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\"></span></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\"> </span></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">update</span>\r\n<ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Add the support of I2C fast mode plus (FM+)</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"></span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">Update </span><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">Polling management:</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,sans-serif;\" lang=\"EN-US\">The Timeout value must be estimated for the overall process duration: the Timeout measurement is cumulative<br></span></li></ul></ul>\r\n<ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add the management of Abort service:&nbsp;Abort DMA transfer through interrupt</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">In the case of Master Abort IT transfer usage:</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add&nbsp;new user HAL_I2C_AbortCpltCallback() to inform user of the end of abort process</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">A new abort state is defined in the </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_I2C_StateTypeDef </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">structure</span></li></ul></ul></ul>\r\n<ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add the management of I2C peripheral errors, ACK\r\nfailure and STOP condition detection during DMA process. This requires the following updates\r\non user application:</span></li><ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Configure and enable the I2C IRQ in HAL_I2C_MspInit() function</span></li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">In stm32f7xx_it.c file, I2C_IRQHandler() function: add a call to HAL_I2C_IRQHandler() function</span></li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add and customize the Error Callback API: HAL_I2C_ErrorCallback()</span></li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Refer to the I2C_EEPROM or I2C_TwoBoards_ComDMA project examples usage of the API<br></span></li></ul></ul><ul><li><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Add the support of&nbsp;I2C repeated start feature:</span>\r\n<ul><li><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">With the following new APIs<br></span></li></ul>\r\n<ul><ul><li><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_I2C_Master_Sequential_Transmit_IT()</span>\r\n</li><li><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">I2C_Master_Sequential_Receive_IT()</span>\r\n</li><li><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">I2C_Master_Abort_IT()</span>\r\n</li><li><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">I2C_Slave_Sequential_Transmit_IT()</span>\r\n</li><li><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">I2C_Slave_Sequential_Receive_IT()</span>\r\n</li><li><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">I2C_EnableListen_IT()</span>\r\n</li><li><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">I2C_DisableListen_IT()</span></li></ul></ul>\r\n<ul><li><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Add new user callbacks:</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"><br></span></li></ul>\r\n<ul><ul><li><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">I2C_ListenCpltCallback()</span></li></ul><ul><li><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">I2C_AddrCallback()</span></li></ul></ul>\r\n</li><li><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Several \r\nupdates on HAL I2C driver to implement the new I2C state machine: </span>\r\n<ul><li><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Add new API to get the&nbsp;</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">I2C mode: \r\nHAL_</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">I2C_GetMode()</span>\r\n</li><li><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update&nbsp;</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">I2C process to \r\nmanage the new&nbsp;</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">I2C states</span></li></ul></li></ul>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL IWDG</span> update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Overall rework of the driver for a more efficient&nbsp;implementation</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Remove the following APIs:</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_IWDG_Start()</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_IWDG_MspInit()</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_IWDG_GetState()</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Update implementation:</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_IWDG_Init() : this function insures the configuration and the start of the IWDG counter</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_IWDG_Refresh() : this function insures the reload of the IWDG counter</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Refer to the following example to identify the changes: IWDG_Example<br></span></li></ul></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL LPTIM </span>update</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\"></span></span></li><ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\">Update </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_LPTIM_TimeOut_Start_IT() and HAL_LPTIM_Counter_Start_IT( ) APIs \r\nto configure WakeUp Timer EXTI interrupt to be able to wakeup MCU from low power \r\nmode by </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\">pressing the EXTI line </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\">Update </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_LPTIM_TimeOut_Stop_IT() and HAL_LPTIM_Counter_Stop_IT( ) APIs to \r\ndisable WakeUp Timer EXTI interrupt </span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL LTDC </span>update</span></li><ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update \r\nHAL_LTDC_IRQHandler() to manage the case of reload interrupt</span></li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Add LTDC extension driver needed with DSI</span></li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Add HAL_LTDC_SetPitch() function for pitch reconfiguration</span></li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add new callback API \r\nHAL_LTDC_ReloadEventCallback()</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add HAL_LTDC_Reload() \r\nto configure LTDC reload feature</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add new No Reload LTDC \r\nvariant APIs<br></span>\r\n<ul style=\"margin-bottom: 0in;\"><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_LTDC_ConfigLayer_NoReload() \r\nto configure the LTDC Layer according to the specified without reloading</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_LTDC_SetWindowSize_NoReload() \r\nto set the LTDC window size without reloading</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_LTDC_SetWindowPosition_NoReload() \r\nto set the LTDC window position without reloading</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_LTDC_SetPixelFormat_NoReload() \r\nto reconfigure the pixel format without reloading</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_LTDC_SetAlpha_NoReload() \r\nto reconfigure the layer alpha value without reloading</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_LTDC_SetAddress_NoReload() \r\nto reconfigure the frame buffer Address without reloading</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_LTDC_SetPitch_NoReload() \r\nto reconfigure the pitch for specific cases</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_LTDC_ConfigColorKeying_NoReload() \r\nto configure the color keying without reloading</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_LTDC_EnableColorKeying_NoReload() \r\nto enable the color keying without reloading</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_LTDC_DisableColorKeying_NoReload() \r\nto disable the color keying without reloading</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_LTDC_EnableCLUT_NoReload() \r\nto enable the color lookup table without reloading</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_LTDC_DisableCLUT_NoReload() \r\nto disable the color lookup table without \r\nreloading</span></li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"text-decoration: underline; font-style: italic;\">Note:</span>\r\nVariant functions with _NoReload post fix allows to set the LTDC\r\nconfiguration/settings without immediate reload. This is useful in case\r\nwhen the program requires to modify several LTDC settings (on one or\r\nboth layers) then applying (reload) these settings in one shot by\r\ncalling the function HAL_LTDC_Reload<br></span></li></ul></li></ul></ul>\r\n<ul style=\"margin-top: 0cm;\" type=\"square\"><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL NOR</span> update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Update NOR_ADDR_SHIFT macro implementation</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL PCD</span> update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update HAL_PCD_IRQHandler() to get HCLK frequency before setting TRDT value</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL QSPI </span>update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update to manage QSPI error management during DMA process</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Improve the DMA transmit process by using QSPI TC interrupt instead of waiting loop on TC flag under DMA ISR</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">These two improvements require the following updates on user application:</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Configure and enable the QSPI IRQ in HAL_QSPI_MspInit() function</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">In stm32f7xx_it.c file, QSPI_IRQHandler() function: add a call to HAL_QSPI_IRQHandler() function</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add and customize the Error Callback API: HAL_QSPI_ErrorCallback()</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add\r\nthe management of non-blocking transfer abort service:&nbsp;HAL_QSPI_Abort_IT(). In\r\nthis case the user must:</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add new callback HAL_QSPI_AbortCpltCallback() to inform user at the end of abort process</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">A new value of State in the HAL_QSPI_StateTypeDef provides the current state during the abort phase</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Polling management update:</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">The Timeout value user must be estimated for the overall process duration: the Timeout measurement is cumulative.&nbsp;</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Refer to the following examples, which describe the changes:</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">QSPI_ReadWrite_DMA</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">QSPI_MemoryMapped</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">QSPI_ExecuteInPlace<br></span></li></ul></ul></ul><ul style=\"margin-top: 0cm;\" type=\"square\"><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Add two new APIs for the QSPI fifo threshold:</span><span style=\"font-family: 'Times New Roman',serif; font-size: 12pt;\" lang=\"EN-US\"><o:p></o:p></span>\r\n<ul style=\"margin-top: 0cm;\" type=\"circle\"><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_QSPI_SetFifoThreshold(): configure the FIFO threshold of \r\nthe QSPI</span><span style=\"font-family: 'Times New Roman',serif; font-size: 12pt;\" lang=\"EN-US\"><o:p></o:p></span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL_QSPI_GetFifoThreshold(): give the current FIFO \r\nthreshold</span><span style=\"font-family: 'Times New Roman',serif; font-size: 12pt;\" lang=\"EN-US\"><o:p></o:p></span></li></ul>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Fix wrong data size management in HAL_QSPI_Receive_DMA()</span><span style=\"font-family: 'Times New Roman',serif; font-size: 12pt;\" lang=\"EN-US\"><o:p></o:p></span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL RCC </span>update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update HAL_RCC_PeriphCLKConfig() function to adjust the SystemCoreClock</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Optimize HAL_RCC_ClockConfig() function code</span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"></span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">O</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">ptimize internal oscillators and PLL startup times</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL RTC </span>update&nbsp;</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update HAL_RTC_GetTime() with proper 'SubSeconds' and 'SecondFraction' management</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL SAI </span>update&nbsp;</span></li><ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update SAI state in case of TIMEOUT error within the </span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">HAL_SAI_Transmit() / HAL_SAI_Receive()</span>\r\n</li></ul><ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update HAL_SAI_IRQHandler:</span>\r\n<ul style=\"margin-bottom: 0in;\"><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add error management in \r\ncase DMA errors through XferAbortCallback() and HAL_DMA_Abort_IT()</span>\r\n</li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add error management in \r\ncase of IT</span></li></ul></li></ul><ul style=\"margin-bottom: 0in;\"><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Move\r\nSAI_BlockSynchroConfig() and SAI_GetInputClock() functions to\r\nstm32f7xx_hal_sai.c/.h files (extension files are kept empty for\r\nprojects compatibility reason)</span></li></ul></ul>\r\n<ul style=\"margin-top: 0cm;\" type=\"square\"><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL SPDIFRX </span>update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Overall driver update for wait on flag management optimization <br></span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL SPI </span>update</span><b><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\"></span></b></li><ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Overall driver optimization to improve performance in polling/interrupt mode to reach maximum peripheral frequency</span></li><ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Polling mode:</span>\r\n</li><ul><li><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Replace the use of SPI_WaitOnFlagUnitTimeout() function by \"if\" \r\nstatement to check on RXNE/TXE flage while transferring \r\ndata</span></li></ul></ul></ul></ul>\r\n<ul style=\"margin-top: 0cm;\" type=\"square\"><ul><ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">&nbsp;Interrupt mode:</span></li><ul><li><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Minimize access on SPI registers</span>\r\n</li></ul></ul><ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">All modes:</span></li><ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add the USE_SPI_CRC switch to minimize the number of statements when CRC calculation is disabled</span></li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update&nbsp;timeout management to check on global processes</span></li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update error code management in all processes</span></li></ul></ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update DMA process:<o:p></o:p></span>\r\n<ul style=\"margin-bottom: 0in;\"><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add the management of SPI peripheral errors during DMA process. This requires the following updates in\r\nthe user application:</span></li><ul><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Configure and enable the SPI IRQ in HAL_SPI_MspInit() function</span></li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">In stm32f7xx_it.c file, SPI_IRQHandler() function: add a call to HAL_SPI_IRQHandler() function</span></li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Add and customize the Error Callback API: HAL_SPI_ErrorCallback()</span></li><li style=\"margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Refer to the following example which describe the changes: SPI_FullDuplex_ComDMA<br></span></li></ul></ul>\r\n</li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL TIM </span>update&nbsp;</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update HAL_TIM_ConfigOCrefClear() function for proper configuration of the SMCR register</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Add new function HAL_TIMEx_ConfigBreakInput() to configure the break input source</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><b><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">HAL UART, USART, SMARTCARD and IRDA </span></b><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\"></span></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\"></span>(referenced as <span style=\"font-style: italic;\">PPP</span> here below)<span style=\"font-style: italic;\"></span></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-style: italic;\"> </span></span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">update<b><o:p></o:p></b></span> \r\n</li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Update Polling management:</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">The user Timeout value&nbsp;must be estimated for the overall process duration: the Timeout measurement is cumulative</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update DMA process:</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"></span><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">Update the m</span><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">anagement of PPP peripheral errors during DMA process. This requires the following updates in user application:</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Configure and enable the PPP IRQ in HAL_PPP_MspInit() function</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">In stm32f7xx_it.c file, PPP_IRQHandler() function: add a call to HAL_PPP_IRQHandler() function</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana',sans-serif; font-size: 10pt;\" lang=\"EN-US\">Add and customize the Error Callback API: HAL_PPP_ErrorCallback()<br></span></li></ul></ul></ul></ul><ul style=\"margin-top: 0cm;\" type=\"square\"><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL WWDG </span>update&nbsp;</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Overall rework of the driver for more efficient implementation</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Remove the following APIs:</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">HAL_WWDG_Start()</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">HAL_WWDG_Start_IT()</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">HAL_WWDG_MspDeInit()</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">HAL_WWDG_GetState()</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update implementation:</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">HAL_WWDG_Init()</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">A&nbsp;new parameter in the Init Structure:&nbsp;EWIMode</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">HAL_WWDG_MspInit()</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">HAL_WWDG_Refresh()&nbsp;</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">This function insures the reload of the counter</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">The \"counter\" parameter has been removed</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">HAL_WWDG_IRQHandler()</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">HAL_WWDG_EarlyWakeupCallback() is the new prototype of HAL_WWDG_WakeupCallback()<br></span></li></ul></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Refer to the following example to identify the changes: WWDG_Example</span></li></ul></ul><h3 style=\"background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;\"><span style=\"font-size: 10pt; font-family: Arial; color: white;\">V1.0.4 / 09-December-2015</span></h3>\r\n<p class=\"MsoNormal\" style=\"margin: 4.5pt 0cm 4.5pt 18pt;\"><b style=\"\"><u><span style=\"font-size: 10pt; font-family: Verdana; color: black;\">Main\r\nChanges</span></u></b></p><ul style=\"margin-top: 0cm;\" type=\"square\"><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL Generic </span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\">update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update HAL \r\nweak empty callbacks to prevent unused argument compilation warnings with some \r\ncompilers by calling the following line:</span>\r\n</li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">UNUSED(hppp);</span></li></ul></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL ETH</span> update&nbsp;</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update HAL_ETH_Init() function to add timeout on the Software reset management<br></span></li></ul></ul><h3 style=\"background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;\"><span style=\"font-size: 10pt; font-family: Arial; color: white;\">V1.0.3 / 13-November-2015</span></h3>\r\n<p class=\"MsoNormal\" style=\"margin: 4.5pt 0cm 4.5pt 18pt;\"><b style=\"\"><u><span style=\"font-size: 10pt; font-family: Verdana; color: black;\">Main\r\nChanges</span></u></b></p><ul style=\"margin-top: 0cm;\" type=\"square\"><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">General updates \r\nto fix known defects and enhancements implementation</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\"></span></span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\"><span style=\"font-weight: bold;\">One change done on the HAL CRYP requires an update on \r\nthe application code based on HAL V1.0.2</span></span>\r\n</li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update \r\nHAL_CRYP_DESECB_Decrypt() API to invert pPlainData and pCypherData \r\nparameters</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL Generic </span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\">update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update HAL \r\nweak empty callbacks to prevent unused argument compilation warnings with some \r\ncompilers by calling the following line:</span>\r\n</li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">UNUSED(hppp);</span></li></ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Remove references to STM32CubeMX and MicroXplorer from stm32f7xx_hal_msp_template.c file<br></span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL ADC</span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\"> update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\">Replace ADC_CHANNEL_TEMPSENSOR definition from ADC_CHANNEL_16 to ADC_CHANNEL_18 </span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\">&nbsp;</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\">Update HAL ADC driver state machine for code efficiency</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\" lang=\"EN-US\">Add new literal: ADC_INJECTED_SOFTWARE_START to be used as possible \r\nvalue for the ExternalTrigInjecConvEdge parameter in the ADC_InitTypeDef \r\nstructure to select the ADC software trigger mode.</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL CORTEX </span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update</span>\r\n</li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Remove duplication \r\nfor __HAL_CORTEX_SYSTICKCLK_CONFIG() macro</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL CRYP </span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update HAL_CRYP_DESECB_Decrypt() API to fix the inverted pPlainData and pCypherData parameters issue </span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL FLASH </span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update OB_IWDG_STOP_ACTIVE definition</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update OB_RDP_LEVEL_x definition by proper values</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update FLASH_MassErase() function to consider the voltage range parameter in the mass erase configuration <br></span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL RCC</span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\"> update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update values for LSE Drive capability defines</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update PLLN min value 50 instead of 100</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">add RCC_PLLI2SP_DIVx defines for PLLI2SP clock divider</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"></span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\" lang=\"EN-US\">Update __HAL_RCC_USB_OTG_FS_CLK_DISABLE() macro to remove the disable of the SYSCFG</span><span style=\"font-family: Verdana; font-size: 10pt;\">&nbsp;</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">Update HAL_RCCEx_GetPeriphCLKFreq() function for proper SAI clock configuration<br></span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL SAI </span></span><span style=\"font-weight: bold;\"></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\">update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update for proper management of the external synchronization input selection</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update of&nbsp;HAL_SAI_Init () funciton</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update definition of SAI_Block_SyncExt and SAI_Block_Synchronization groups</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update SAI_SLOTACTIVE_X &nbsp;defines values</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update&nbsp;</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">HAL_SAI_Init() function for proper companding mode management</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update SAI_Transmit_ITxxBit() functions to add the check on transfer counter before writing new data to SAIx_DR registers</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update SAI_FillFifo() function to avoid issue when the number of data to transmit is smaller than the FIFO size</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update HAL_SAI_EnableRxMuteMode() function for proper mute management</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update SAI_InitPCM() function to support 24bits configuration</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL SD </span></span><span style=\"font-weight: bold;\"></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\">update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\">update HAL_SD_Get_CardInfo() to properly support high capacity cards</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\"><br></span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL SPDIFRX </span></span><span style=\"font-weight: bold;\"></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\">update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update SPDIFRX_DMARxCplt() function implementation to&nbsp;check on circular mode before disabling the DMA</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL TIM </span></span><span style=\"font-weight: bold;\"></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\">update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update HAL_TIM_ConfigClockSource() function implementation for proper parameters check</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL UART</span> update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">Update __HAL_UART_CLEAR_IT macro for proper functionning&nbsp;</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\"><span style=\"font-weight: bold;\">ll FMC</span> update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">add FMC_PAGE_SIZE_512 define</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\"><span style=\"font-weight: bold;\">ll SDMMC</span> update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update SDMMC_SetSDMMCReadWaitMode() function for proper functionning</span></li></ul></ul><h3 style=\"background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;\"><span style=\"font-size: 10pt; font-family: Arial; color: white;\">V1.0.2 / 21-September-2015</span></h3>\r\n<p class=\"MsoNormal\" style=\"margin: 4.5pt 0cm 4.5pt 18pt;\"><b style=\"\"><u><span style=\"font-size: 10pt; font-family: Verdana; color: black;\">Main\r\nChanges</span></u></b></p><ul style=\"margin-top: 0cm;\" type=\"square\"><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL Generic </span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\">update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">stm32f7xx_hal.conf_template.h: update&nbsp;</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">HSE_STARTUP_TIMEOUT</span></li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">stm32f7xx_hal_def.h: update the</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"> quotation marks used in #error\"USE_RTOS should be 0 in the current HAL release\"</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL DMA</span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\"> update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Overall \r\ndriver update for code optimization</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"></span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">add \r\nStreamBaseAddress and StreamIndex new fields in the DMA_HandleTypeDef \r\nstructure</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">add \r\nDMA_Base_Registers private structure</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">add static function \r\nDMA_CalcBaseAndBitshift()</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update \r\nHAL_DMA_Init() function to use the new added static function</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update \r\nHAL_DMA_DeInit() function to optimize clear flag operations</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update \r\nHAL_DMA_Start_IT() function to optimize interrupts enable</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update \r\nHAL_DMA_PollForTransfer() function to optimize check on flags</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update \r\nHAL_DMA_IRQHandler() function to optimize interrupt flag management</span></li></ul></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL ETH&nbsp;</span></span><span style=\"font-weight: bold;\"></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\">update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">remove duplicated macro IS_ETH_RX_MODE()</span><small><span style=\"font-style: italic;\"></span></small></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL GPIO </span></span><span style=\"font-weight: bold;\"></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\">update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Rename \r\nGPIO_SPEED_LOW define to GPIO_SPEED_FREQ_LOW</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Rename \r\nGPIO_SPEED_MEDIUM define to GPIO_SPEED_FREQ_MEDIUM</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Rename \r\nGPIO_SPEED_FAST define to GPIO_SPEED_FREQ_HIGH</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Rename \r\nGPIO_SPEED_HIGH define to GPIO_SPEED_FREQ_VERY_HIGH</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL HASH </span></span><span style=\"font-weight: bold;\"></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\">update</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Rename \r\nHAL_HASH_STATETypeDef to HAL_HASH_StateTypeDef</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Rename \r\nHAL_HASH_PhaseTypeDef to HAL_HASHPhaseTypeDef</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL RCC </span></span><span style=\"font-weight: bold;\"></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;\">update</span><span style=\"font-weight: bold;\"></span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update values for LSE Drive capability defines</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update PLLN/PLLI2SN/PLLSAI VCO min value 100MHz instead of 192MHz</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">add __HAL_RCC_MCO1_CONFIG() and </span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">__HAL_RCC_MCO2_CONFIG() macros</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"></span></li></ul><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update HAL_RCCEx_PeriphCLKConfig() function to reset the Backup domain only if the RTC Clock source selection is modified&nbsp;</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL TIM</span> update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update the implementation of __HAL_TIM_SET_COMPARE() macro</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">remove useless assert() in&nbsp;HAL_TIM_PWM_ConfigChannel(), TIM_OC2_SetConfig() and HAL_TIM_PWM_ConfigChannel() </span><span style=\"font-family: Verdana; font-size: 10pt;\">functions</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL CAN</span> update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">add the clear flag ERRI bit in HAL_CAN_IRQHandler()</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL I2S</span> update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update I2S HAL_I2S_Transmit() API&nbsp;to keep the check on busy flag only for the slave</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL QSPI</span> update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">Add __HAL_QSPI_CLEAR_FLAG() before QSPI_Config()</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL UART</span> update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">Remove\r\nenabling of ERR IT source and PE source from HAL_UART_Transmit_IT() and\r\nremove the corresponding disabling ERR/PE IT from UART_EndTransmit_IT()</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL PCD</span></span><span style=\"font-family: Verdana; font-size: 10pt;\"> update</span><span style=\"font-weight: bold;\">&nbsp;</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">Clean status phase received interrupt when DMA mode enabled&nbsp;</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL HCD </span></span><span style=\"font-family: Verdana; font-size: 10pt;\">update</span><span style=\"font-family: Verdana; font-size: 10pt;\"><span style=\"font-weight: bold;\"></span></span><span style=\"font-weight: bold;\"></span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update to use local \r\nvariable in USB Host channel re-activation</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\"><span style=\"font-weight: bold;\">ll FMC</span> update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update the define FMC Write FIFO Disable/Enable: FMC_WRITE_FIFO_DISABLE and FMC_WRITE_FIFO_ENABLE</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">remove return HAL_ERROR from FMC_SDRAM_SendCommand() function</span></li></ul></ul><span style=\"font-family: Verdana; font-size: 10pt;\"></span><h3 style=\"background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;\"><span style=\"font-size: 10pt; font-family: Arial; color: white;\">V1.0.1 / 25-June-2015</span></h3>\r\n<p class=\"MsoNormal\" style=\"margin: 4.5pt 0cm 4.5pt 18pt;\"><b style=\"\"><u><span style=\"font-size: 10pt; font-family: Verdana; color: black;\">Main\r\nChanges</span></u></b></p><ul style=\"margin-top: 0cm;\" type=\"square\"><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana,sans-serif; font-size: 10pt;\">General updates \r\nto fix known defects and enhancements implementation</span><span style=\"font-family: Verdana; font-size: 10pt;\"></span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL CRC&nbsp;</span>update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update __HAL_CRC_SET_IDR() macro implementation to use WRITE_REG() instead of MODIFY_REG()<br></span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL CEC&nbsp;</span>update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update timeout management in HAL_CEC_Transmit() and HAL_CEC_Receive() functions</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL Cortex </span>update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update HAL_MPU_ConfigRegion() function to be misra compliant</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL ETH </span>update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Remove \r\nduplicated IS_ETH_DUPLEX_MODE() and IS_ETH_RX_MODE() macros</span><span style=\"font-family: Verdana; font-size: 10pt;\"></span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Remove \r\nillegal space ETH_MAC_READCONTROLLER_FLUSHING macro</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update \r\nETH_MAC_READCONTROLLER_XXX defined values (XXX can be IDLE, READING_DATA and \r\nREADING_STATUS)</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL FLASH </span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update FLASH_OB_GetRDP() function to return uint8_t &nbsp;instead of FlagStatus</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update OB_RDP_LEVELx definition</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">add __HAL_FLASH_GET_LATENCY() macro</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL HASH </span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update</span><span style=\"font-family: Verdana; font-size: 10pt;\"></span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update\r\nHASH_DMAXferCplt() and HASHEx_DMAXferCplt() functions to properly\r\nconfigure the number of valid bits in last word of the message</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update HAL_HASH_SHA1_Accumulate() function to check on the length of the input buffer</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update\r\nHAL_HASH_<span style=\"font-weight: bold; font-style: italic;\">MODE</span>_Start_IT() functions (<span style=\"font-style: italic;\"><span style=\"font-weight: bold;\">Mode </span></span><span style=\"font-weight: bold;\"></span>stands for MD5, SHA1, SHA224 and SHA256<span style=\"font-style: italic;\"><span style=\"font-weight: bold;\"> </span></span>) to :</span></li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Fix processing \r\nfail for small input buffers</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">to unlock \r\nthe process and call return HAL_OK at the end of HASH processing to avoid \r\nincorrect repeating software</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">properly to manage \r\nthe HashITCounter efficiency </span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update to call the \r\nHAL_HASH_InCpltCallback() at the end of the complete buffer instead \r\nof</span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"> \r\nevery each 512 bits </span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update HASH_IT_DINI and HASH_IT_DCI definition</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update __HAL_HASH_GET_FLAG() macro definition<br></span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL I2S </span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update HAL_I2S_Transmit() function to ensure the waiting on Busy flag in case of slave mode selection</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL RTC </span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update HAL_RTCEx_SetWakeUpTimer() and HAL_RTCEx_SetWakeUpTimer_IT() functions to properly check on WUTWF flag</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">rename RTC_TIMESTAMPPIN_PI8 define to RTC_TIMESTAMPPIN_POS1</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">rename RTC_TIMESTAMPPIN_PC1 define to RTC_TIMESTAMPPIN_POS2</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG() macro definition</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update __HAL_RTC_TAMPER_GET_IT() macro definition</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update __HAL_RTC_TAMPER_CLEAR_FLAG() macro definition</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update __HAL_RTC_TIMESTAMP_CLEAR_FLAG() macro definition</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() macro definition</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">add RTC_TAMPCR_TAMPXE and RTC_TAMPCR_TAMPXIE defines</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL SMARTCARD </span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">add SMARTCARD_FLAG_IDLE, SMARTCARD_IT_IDLE and&nbsp; SMARTCARD_CLEAR_IDLEF defines<br></span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL UART </span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update HAL_UART_DMAResume() function to clear overrun flag before resuming the Rx transfer</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update UART_FLAG_SBKF definition<br></span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">HAL USART </span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update HAL_USART_DMAResume() function to </span><span style=\"font-family: Verdana; font-size: 10pt;\">clear overrun flag before resuming the Rx transfer</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">LL FMC </span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update</span></li><ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">update NAND timing maximum values</span></li></ul><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\"><span style=\"font-weight: bold;\">LL USB </span></span><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">update</span>\r\n</li><ul><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">USB_FlushTxFifo API: \r\nupdate to flush all Tx FIFO</span>\r\n</li><li style=\"margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;\" class=\"MsoNormal\"><span style=\"font-family: 'Verdana','sans-serif'; font-size: 10pt;\">Update to use local \r\nvariable in USB Host channel re-activation</span></li></ul></ul>\r\n<b><u><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;\"></span></u></b>\r\n<h3 style=\"background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;\"><span style=\"font-size: 10pt; font-family: Arial; color: white;\">V1.0.0 / 12-May-2015</span></h3>\r\n<p class=\"MsoNormal\" style=\"margin: 4.5pt 0cm 4.5pt 18pt;\"><b style=\"\"><u><span style=\"font-size: 10pt; font-family: Verdana; color: black;\">Main\r\nChanges</span></u></b></p><ul style=\"margin-top: 0cm;\" type=\"square\"><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-family: Verdana; font-size: 10pt;\">First official release for</span><span style=\"font-family: Verdana; font-size: 10pt;\"><span style=\"font-style: italic; font-weight: bold;\"> STM32F756xx/746xx/745xx</span> \r\ndevices</span><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\"></span></li></ul>\r\n<b><u><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;\"></span></u></b>\r\n<h2 style=\"background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;\"><a name=\"License\"></a><span style=\"font-size: 12pt; color: white;\">License<o:p></o:p></span></h2>\r\n<div style=\"text-align: justify;\">\r\n<div style=\"text-align: justify;\"><font size=\"-1\"><span style=\"font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\">Redistribution\r\nand use in source and binary forms, with or without\r\nmodification, are permitted provided that the following conditions are\r\nmet:</span><br>\r\n</font>\r\n<ol>\r\n<li><font size=\"-1\"><span style=\"font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\">Redistributions\r\nof source code must retain the above copyright notice, this list of\r\nconditions and the following disclaimer.</span><span style=\"font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\"></span></font></li>\r\n<li><font size=\"-1\"><span style=\"font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\">Redistributions\r\nin binary form must reproduce the above copyright notice, this list of\r\nconditions and the following disclaimer in </span><span style=\"font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\">the\r\ndocumentation and/or other materials provided with the distribution.</span><span style=\"font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\"></span></font></li>\r\n<li><font size=\"-1\"><span style=\"font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\">Neither the\r\nname of STMicroelectronics nor the names of its contributors may be\r\nused to endorse or promote products derived </span><br>\r\n</font> </li>\r\n</ol>\r\n<font size=\"-1\"><span style=\"font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;\r\nfrom this software without specific prior written permission.</span><br>\r\n<span style=\"font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\"></span><br>\r\n<span style=\"font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\">THIS\r\nSOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\nAND ANY EXPRESS OR IMPLIED</span><span style=\"font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\"> WARRANTIES,\r\nINCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r\nMERCHANTABILITY AND FITNESS FOR A </span><span style=\"font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\">PARTICULAR\r\nPURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR\r\nCONTRIBUTORS BE LIABLE FOR ANY </span><span style=\"font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\">DIRECT,\r\nINDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r\n(INCLUDING, BUT NOT LIMITED TO, </span><span style=\"font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\">PROCUREMENT OF\r\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\r\nBUSINESS INTERRUPTION) HOWEVER</span><span style=\"font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\"> CAUSED AND ON\r\nANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r\n(INCLUDING NEGLIGENCE OR </span><span style=\"font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\">OTHERWISE)\r\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF\r\nTHE POSSIBILITY OF SUCH DAMAGE.</span></font> </div>\r\n<span style=\"font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\"></span></div>\r\n<span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;\"></span>\r\n<div class=\"MsoNormal\" style=\"text-align: center;\" align=\"center\"><span style=\"color: black;\">\r\n<hr align=\"center\" size=\"2\" width=\"100%\"></span></div>\r\n<p class=\"MsoNormal\" style=\"margin: 4.5pt 0in 4.5pt 0.25in; text-align: center;\" align=\"center\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;\">For\r\ncomplete documentation on </span><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\">STM32<span style=\"color: black;\"> Microcontrollers visit </span><u><span style=\"color: blue;\"><a href=\"http://www.st.com/internet/mcu/family/141.jsp\" target=\"_blank\">www.st.com/STM32</a></span></u></span><span style=\"color: black;\"><o:p></o:p></span></p>\r\n</td>\r\n</tr>\r\n<tr><td style=\"padding: 0in;\" valign=\"top\"></td></tr></tbody>\r\n</table>\r\n<p class=\"MsoNormal\"><span style=\"font-size: 10pt;\"><o:p></o:p></span></p>\r\n</td>\r\n</tr>\r\n</tbody>\r\n</table>\r\n</div>\r\n<p class=\"MsoNormal\"><o:p>&nbsp;</o:p></p>\r\n</div>\r\n</body></html>"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   HAL module driver.\r\n  *          This is the common part of the HAL initialization\r\n  *\r\n  @verbatim\r\n  ==============================================================================\r\n                     ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]\r\n    The common HAL driver contains a set of generic and common APIs that can be\r\n    used by the PPP peripheral drivers and the user to start using the HAL. \r\n    [..]\r\n    The HAL contains two APIs' categories: \r\n         (+) Common HAL APIs\r\n         (+) Services HAL APIs\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup HAL HAL\r\n  * @brief HAL module driver.\r\n  * @{\r\n  */\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @addtogroup HAL_Private_Constants\r\n  * @{\r\n  */\r\n/**\r\n * @brief STM32F7xx HAL Driver version number V1.1.0\r\n   */\r\n#define __STM32F7xx_HAL_VERSION_MAIN   (0x01) /*!< [31:24] main version */\r\n#define __STM32F7xx_HAL_VERSION_SUB1   (0x01) /*!< [23:16] sub1 version */\r\n#define __STM32F7xx_HAL_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */\r\n#define __STM32F7xx_HAL_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ \r\n#define __STM32F7xx_HAL_VERSION         ((__STM32F7xx_HAL_VERSION_MAIN << 24)\\\r\n                                        |(__STM32F7xx_HAL_VERSION_SUB1 << 16)\\\r\n                                        |(__STM32F7xx_HAL_VERSION_SUB2 << 8 )\\\r\n                                        |(__STM32F7xx_HAL_VERSION_RC))\r\n                                        \r\n#define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @addtogroup HAL_Private_Variables\r\n  * @{\r\n  */\r\n__IO uint32_t uwTick;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup HAL_Exported_Functions HAL Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions \r\n *  @brief    Initialization and de-initialization functions\r\n *\r\n@verbatim    \r\n ===============================================================================\r\n              ##### Initialization and de-initialization functions #####\r\n ===============================================================================\r\n    [..]  This section provides functions allowing to:\r\n      (+) Initializes the Flash interface the NVIC allocation and initial clock \r\n          configuration. It initializes the systick also when timeout is needed \r\n          and the backup domain when enabled.\r\n      (+) de-Initializes common part of the HAL\r\n      (+) Configure The time base source to have 1ms time base with a dedicated \r\n          Tick interrupt priority. \r\n        (++) Systick timer is used by default as source of time base, but user \r\n             can eventually implement his proper time base source (a general purpose \r\n             timer for example or other time source), keeping in mind that Time base \r\n             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and \r\n             handled in milliseconds basis.\r\n        (++) Time base configuration function (HAL_InitTick ()) is called automatically \r\n             at the beginning of the program after reset by HAL_Init() or at any time \r\n             when clock is configured, by HAL_RCC_ClockConfig(). \r\n        (++) Source of time base is configured  to generate interrupts at regular \r\n             time intervals. Care must be taken if HAL_Delay() is called from a \r\n             peripheral ISR process, the Tick interrupt line must have higher priority \r\n            (numerically lower) than the peripheral interrupt. Otherwise the caller \r\n            ISR process will be blocked. \r\n       (++) functions affecting time base configurations are declared as __weak  \r\n             to make  override possible  in case of other  implementations in user file.\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  This function is used to initialize the HAL Library; it must be the first \r\n  *         instruction to be executed in the main program (before to call any other\r\n  *         HAL function), it performs the following:\r\n  *           Configure the Flash prefetch, and instruction cache through ART accelerator.\r\n  *           Configures the SysTick to generate an interrupt each 1 millisecond,\r\n  *           which is clocked by the HSI (at this stage, the clock is not yet\r\n  *           configured and thus the system is running from the internal HSI at 16 MHz).\r\n  *           Set NVIC Group Priority to 4.\r\n  *           Calls the HAL_MspInit() callback function defined in user file \r\n  *           \"stm32f7xx_hal_msp.c\" to do the global low level hardware initialization \r\n  *            \r\n  * @note   SysTick is used as time base for the HAL_Delay() function, the application\r\n  *         need to ensure that the SysTick time base is always set to 1 millisecond\r\n  *         to have correct HAL operation.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_Init(void)\r\n{\r\n  /* Configure Flash prefetch and Instruction cache through ART accelerator */ \r\n#if (ART_ACCLERATOR_ENABLE != 0)\r\n   __HAL_FLASH_ART_ENABLE();\r\n#endif /* ART_ACCLERATOR_ENABLE */\r\n\r\n  /* Set Interrupt Group Priority */\r\n  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);\r\n\r\n  /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */\r\n  HAL_InitTick(TICK_INT_PRIORITY);\r\n  \r\n  /* Init the low level hardware */\r\n  HAL_MspInit();\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  This function de-Initializes common part of the HAL and stops the systick.\r\n  *         This function is optional.   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DeInit(void)\r\n{\r\n  /* Reset of all peripherals */\r\n  __HAL_RCC_APB1_FORCE_RESET();\r\n  __HAL_RCC_APB1_RELEASE_RESET();\r\n\r\n  __HAL_RCC_APB2_FORCE_RESET();\r\n  __HAL_RCC_APB2_RELEASE_RESET();\r\n\r\n  __HAL_RCC_AHB1_FORCE_RESET();\r\n  __HAL_RCC_AHB1_RELEASE_RESET();\r\n\r\n  __HAL_RCC_AHB2_FORCE_RESET();\r\n  __HAL_RCC_AHB2_RELEASE_RESET();\r\n\r\n  __HAL_RCC_AHB3_FORCE_RESET();\r\n  __HAL_RCC_AHB3_RELEASE_RESET();\r\n\r\n  /* De-Init the low level hardware */\r\n  HAL_MspDeInit();\r\n    \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the MSP.\r\n  * @retval None\r\n  */\r\n__weak void HAL_MspInit(void)\r\n{\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_MspInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the MSP.\r\n  * @retval None\r\n  */\r\n__weak void HAL_MspDeInit(void)\r\n{\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_MspDeInit could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief This function configures the source of the time base.\r\n  *        The time source is configured  to have 1ms time base with a dedicated \r\n  *        Tick interrupt priority.\r\n  * @note This function is called  automatically at the beginning of program after\r\n  *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().\r\n  * @note In the default implementation, SysTick timer is the source of time base. \r\n  *       It is used to generate interrupts at regular time intervals. \r\n  *       Care must be taken if HAL_Delay() is called from a peripheral ISR process, \r\n  *       The the SysTick interrupt must have higher priority (numerically lower) \r\n  *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.\r\n  *       The function is declared as __weak  to be overwritten  in case of other\r\n  *       implementation  in user file.\r\n  * @param TickPriority: Tick interrupt priority.\r\n  * @retval HAL status\r\n  */\r\n__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)\r\n{\r\n  /*Configure the SysTick to have interrupt in 1ms time basis*/\r\n  HAL_SYSTICK_Config(SystemCoreClock/1000);\r\n\r\n  /*Configure the SysTick IRQ priority */\r\n  HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0);\r\n\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions \r\n *  @brief    HAL Control functions\r\n *\r\n@verbatim\r\n ===============================================================================\r\n                      ##### HAL Control functions #####\r\n ===============================================================================\r\n    [..]  This section provides functions allowing to:\r\n      (+) Provide a tick value in millisecond\r\n      (+) Provide a blocking delay in millisecond\r\n      (+) Suspend the time base source interrupt\r\n      (+) Resume the time base source interrupt\r\n      (+) Get the HAL API driver version\r\n      (+) Get the device identifier\r\n      (+) Get the device revision identifier\r\n      (+) Enable/Disable Debug module during SLEEP mode\r\n      (+) Enable/Disable Debug module during STOP mode\r\n      (+) Enable/Disable Debug module during STANDBY mode\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief This function is called to increment  a global variable \"uwTick\"\r\n  *        used as application time base.\r\n  * @note In the default implementation, this variable is incremented each 1ms\r\n  *       in Systick ISR.\r\n * @note This function is declared as __weak to be overwritten in case of other \r\n  *      implementations in user file.\r\n  * @retval None\r\n  */\r\n__weak void HAL_IncTick(void)\r\n{\r\n  uwTick++;\r\n}\r\n\r\n/**\r\n  * @brief Provides a tick value in millisecond.\r\n  * @note This function is declared as __weak to be overwritten in case of other \r\n  *       implementations in user file.\r\n  * @retval tick value\r\n  */\r\n__weak uint32_t HAL_GetTick(void)\r\n{\r\n  return uwTick;\r\n}\r\n\r\n/**\r\n  * @brief This function provides accurate delay (in milliseconds) based \r\n  *        on variable incremented.\r\n  * @note In the default implementation , SysTick timer is the source of time base.\r\n  *       It is used to generate interrupts at regular time intervals where uwTick\r\n  *       is incremented.\r\n  * @note This function is declared as __weak to be overwritten in case of other\r\n  *       implementations in user file.\r\n  * @param Delay: specifies the delay time length, in milliseconds.\r\n  * @retval None\r\n  */\r\n__weak void HAL_Delay(__IO uint32_t Delay)\r\n{\r\n  uint32_t tickstart = 0;\r\n  tickstart = HAL_GetTick();\r\n  while((HAL_GetTick() - tickstart) < Delay)\r\n  {\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Suspend Tick increment.\r\n  * @note In the default implementation , SysTick timer is the source of time base. It is\r\n  *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()\r\n  *       is called, the SysTick interrupt will be disabled and so Tick increment \r\n  *       is suspended.\r\n  * @note This function is declared as __weak to be overwritten in case of other\r\n  *       implementations in user file.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SuspendTick(void)\r\n{\r\n  /* Disable SysTick Interrupt */\r\n  SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;\r\n}\r\n\r\n/**\r\n  * @brief Resume Tick increment.\r\n  * @note In the default implementation , SysTick timer is the source of time base. It is\r\n  *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()\r\n  *       is called, the SysTick interrupt will be enabled and so Tick increment \r\n  *       is resumed.\r\n  * @note This function is declared as __weak to be overwritten in case of other\r\n  *       implementations in user file.\r\n  * @retval None\r\n  */\r\n__weak void HAL_ResumeTick(void)\r\n{\r\n  /* Enable SysTick Interrupt */\r\n  SysTick->CTRL  |= SysTick_CTRL_TICKINT_Msk;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the HAL revision\r\n  * @retval version : 0xXYZR (8bits for each decimal, R for RC)\r\n  */\r\nuint32_t HAL_GetHalVersion(void)\r\n{\r\n return __STM32F7xx_HAL_VERSION;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the device revision identifier.\r\n  * @retval Device revision identifier\r\n  */\r\nuint32_t HAL_GetREVID(void)\r\n{\r\n   return((DBGMCU->IDCODE) >> 16U);\r\n}\r\n\r\n/**\r\n  * @brief  Returns the device identifier.\r\n  * @retval Device identifier\r\n  */\r\nuint32_t HAL_GetDEVID(void)\r\n{\r\n   return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);\r\n}\r\n\r\n/**\r\n  * @brief  Enable the Debug Module during SLEEP mode\r\n  * @retval None\r\n  */\r\nvoid HAL_DBGMCU_EnableDBGSleepMode(void)\r\n{\r\n  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);\r\n}\r\n\r\n/**\r\n  * @brief  Disable the Debug Module during SLEEP mode\r\n  * @retval None\r\n  */\r\nvoid HAL_DBGMCU_DisableDBGSleepMode(void)\r\n{\r\n  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);\r\n}\r\n\r\n/**\r\n  * @brief  Enable the Debug Module during STOP mode\r\n  * @retval None\r\n  */\r\nvoid HAL_DBGMCU_EnableDBGStopMode(void)\r\n{\r\n  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);\r\n}\r\n\r\n/**\r\n  * @brief  Disable the Debug Module during STOP mode\r\n  * @retval None\r\n  */\r\nvoid HAL_DBGMCU_DisableDBGStopMode(void)\r\n{\r\n  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);\r\n}\r\n\r\n/**\r\n  * @brief  Enable the Debug Module during STANDBY mode\r\n  * @retval None\r\n  */\r\nvoid HAL_DBGMCU_EnableDBGStandbyMode(void)\r\n{\r\n  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);\r\n}\r\n\r\n/**\r\n  * @brief  Disable the Debug Module during STANDBY mode\r\n  * @retval None\r\n  */\r\nvoid HAL_DBGMCU_DisableDBGStandbyMode(void)\r\n{\r\n  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);\r\n}\r\n\r\n/**\r\n  * @brief  Enables the I/O Compensation Cell.\r\n  * @note   The I/O compensation cell can be used only when the device supply\r\n  *         voltage ranges from 2.4 to 3.6 V.  \r\n  * @retval None\r\n  */\r\nvoid HAL_EnableCompensationCell(void)\r\n{\r\n  SYSCFG->CMPCR |= SYSCFG_CMPCR_CMP_PD;\r\n}\r\n\r\n/**\r\n  * @brief  Power-down the I/O Compensation Cell.\r\n  * @note   The I/O compensation cell can be used only when the device supply\r\n  *         voltage ranges from 2.4 to 3.6 V.  \r\n  * @retval None\r\n  */\r\nvoid HAL_DisableCompensationCell(void)\r\n{\r\n  SYSCFG->CMPCR &= (uint32_t)~((uint32_t)SYSCFG_CMPCR_CMP_PD);\r\n}\r\n\r\n/**\r\n  * @brief  Enables the FMC Memory Mapping Swapping.\r\n  *   \r\n  * @note   SDRAM is accessible at 0x60000000 \r\n  *         and NOR/RAM is accessible at 0xC0000000   \r\n  *\r\n  * @retval None\r\n  */\r\nvoid HAL_EnableFMCMemorySwapping(void)\r\n{\r\n  SYSCFG->MEMRMP |= SYSCFG_MEMRMP_SWP_FMC_0;\r\n}\r\n\r\n/**\r\n  * @brief  Disables the FMC Memory Mapping Swapping\r\n  *   \r\n  * @note   SDRAM is accessible at 0xC0000000 (default mapping)  \r\n  *         and NOR/RAM is accessible at 0x60000000 (default mapping)    \r\n  *           \r\n  * @retval None\r\n  */\r\nvoid HAL_DisableFMCMemorySwapping(void)\r\n{\r\n\r\n  SYSCFG->MEMRMP &= (uint32_t)~((uint32_t)SYSCFG_MEMRMP_SWP_FMC);\r\n}\r\n\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n/**\r\n* @brief  Enable the Internal FLASH Bank Swapping.\r\n*   \r\n* @note   This function can be used only for STM32F77xx/STM32F76xx devices. \r\n*\r\n* @note   Flash Bank2 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM)) \r\n*         and Flash Bank1 mapped at 0x08100000 (AXI) (aliased at 0x00300000 (TCM))   \r\n*\r\n* @retval None\r\n*/\r\nvoid HAL_EnableMemorySwappingBank(void)\r\n{\r\n  SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB);\r\n}\r\n\r\n/**\r\n* @brief  Disable the Internal FLASH Bank Swapping.\r\n*   \r\n* @note   This function can be used only for STM32F77xx/STM32F76xx devices. \r\n*\r\n* @note   The default state : Flash Bank1 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM)) \r\n*         and Flash Bank2 mapped at 0x08100000 (AXI)( aliased at 0x00300000 (TCM)) \r\n*           \r\n* @retval None\r\n*/\r\nvoid HAL_DisableMemorySwappingBank(void)\r\n{\r\n  CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB);\r\n}\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_adc.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   This file provides firmware functions to manage the following \r\n  *          functionalities of the Analog to Digital Convertor (ADC) peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + IO operation functions\r\n  *           + State and errors functions\r\n  *         \r\n  @verbatim\r\n  ==============================================================================\r\n                    ##### ADC Peripheral features #####\r\n  ==============================================================================\r\n  [..] \r\n  (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.\r\n  (#) Interrupt generation at the end of conversion, end of injected conversion,  \r\n      and in case of analog watchdog or overrun events\r\n  (#) Single and continuous conversion modes.\r\n  (#) Scan mode for automatic conversion of channel 0 to channel x.\r\n  (#) Data alignment with in-built data coherency.\r\n  (#) Channel-wise programmable sampling time.\r\n  (#) External trigger option with configurable polarity for both regular and \r\n      injected conversion.\r\n  (#) Dual/Triple mode (on devices with 2 ADCs or more).\r\n  (#) Configurable DMA data storage in Dual/Triple ADC mode. \r\n  (#) Configurable delay between conversions in Dual/Triple interleaved mode.\r\n  (#) ADC conversion type (refer to the datasheets).\r\n  (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at \r\n      slower speed.\r\n  (#) ADC input range: VREF(minus) = VIN = VREF(plus).\r\n  (#) DMA request generation during regular channel conversion.\r\n\r\n\r\n                     ##### How to use this driver #####\r\n  ==============================================================================\r\n  [..]\r\n  (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():\r\n       (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()\r\n       (##) ADC pins configuration\r\n             (+++) Enable the clock for the ADC GPIOs using the following function:\r\n                   __HAL_RCC_GPIOx_CLK_ENABLE()  \r\n             (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init() \r\n       (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())\r\n             (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()\r\n             (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()\r\n             (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()\r\n       (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())\r\n             (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()\r\n             (+++) Configure and enable two DMA streams stream for managing data\r\n                 transfer from peripheral to memory (output stream)\r\n             (+++) Associate the initialized DMA handle to the CRYP DMA handle\r\n                 using  __HAL_LINKDMA()\r\n             (+++) Configure the priority and enable the NVIC for the transfer complete\r\n                 interrupt on the two DMA Streams. The output stream should have higher\r\n                 priority than the input stream.\r\n                       \r\n    *** Configuration of ADC, groups regular/injected, channels parameters ***\r\n  ==============================================================================\r\n  [..]\r\n  (#) Configure the ADC parameters (resolution, data alignment, ...)\r\n      and regular group parameters (conversion trigger, sequencer, ...)\r\n      using function HAL_ADC_Init().\r\n\r\n  (#) Configure the channels for regular group parameters (channel number, \r\n      channel rank into sequencer, ..., into regular group)\r\n      using function HAL_ADC_ConfigChannel().\r\n\r\n  (#) Optionally, configure the injected group parameters (conversion trigger, \r\n      sequencer, ..., of injected group)\r\n      and the channels for injected group parameters (channel number, \r\n      channel rank into sequencer, ..., into injected group)\r\n      using function HAL_ADCEx_InjectedConfigChannel().\r\n\r\n  (#) Optionally, configure the analog watchdog parameters (channels\r\n      monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig().\r\n\r\n  (#) Optionally, for devices with several ADC instances: configure the \r\n      multimode parameters using function HAL_ADCEx_MultiModeConfigChannel().\r\n\r\n                       *** Execution of ADC conversions ***\r\n  ==============================================================================\r\n  [..]  \r\n  (#) ADC driver can be used among three modes: polling, interruption,\r\n      transfer by DMA.    \r\n\r\n     *** Polling mode IO operation ***\r\n     =================================\r\n     [..]    \r\n       (+) Start the ADC peripheral using HAL_ADC_Start() \r\n       (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage\r\n           user can specify the value of timeout according to his end application      \r\n       (+) To read the ADC converted values, use the HAL_ADC_GetValue() function.\r\n       (+) Stop the ADC peripheral using HAL_ADC_Stop()\r\n       \r\n     *** Interrupt mode IO operation ***    \r\n     ===================================\r\n     [..]    \r\n       (+) Start the ADC peripheral using HAL_ADC_Start_IT() \r\n       (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine\r\n       (+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can \r\n           add his own code by customization of function pointer HAL_ADC_ConvCpltCallback \r\n       (+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can \r\n           add his own code by customization of function pointer HAL_ADC_ErrorCallback\r\n       (+) Stop the ADC peripheral using HAL_ADC_Stop_IT()     \r\n\r\n     *** DMA mode IO operation ***    \r\n     ==============================\r\n     [..]    \r\n       (+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length \r\n           of data to be transferred at each end of conversion \r\n       (+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can \r\n           add his own code by customization of function pointer HAL_ADC_ConvCpltCallback \r\n       (+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can \r\n           add his own code by customization of function pointer HAL_ADC_ErrorCallback\r\n       (+) Stop the ADC peripheral using HAL_ADC_Stop_DMA()\r\n                    \r\n     *** ADC HAL driver macros list ***\r\n     ============================================= \r\n     [..]\r\n       Below the list of most used macros in ADC HAL driver.\r\n       \r\n      (+) __HAL_ADC_ENABLE : Enable the ADC peripheral\r\n      (+) __HAL_ADC_DISABLE : Disable the ADC peripheral\r\n      (+) __HAL_ADC_ENABLE_IT: Enable the ADC end of conversion interrupt\r\n      (+) __HAL_ADC_DISABLE_IT: Disable the ADC end of conversion interrupt\r\n      (+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabled\r\n      (+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags\r\n      (+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status\r\n      (+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register \r\n      \r\n     [..] \r\n       (@) You can refer to the ADC HAL driver header file for more useful macros \r\n\r\n                      *** Deinitialization of ADC ***\r\n  ==============================================================================\r\n  [..]\r\n  (#) Disable the ADC interface\r\n     (++) ADC clock can be hard reset and disabled at RCC top level.\r\n     (++) Hard reset of ADC peripherals\r\n          using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET().\r\n     (++) ADC clock disable using the equivalent macro/functions as configuration step.\r\n               (+++) Example:\r\n                   Into HAL_ADC_MspDeInit() (recommended code location) or with\r\n                   other device clock parameters configuration:\r\n               (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure);\r\n               (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;\r\n               (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock)\r\n               (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);\r\n\r\n  (#) ADC pins configuration\r\n     (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE()\r\n\r\n  (#) Optionally, in case of usage of ADC with interruptions:\r\n     (++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn)\r\n\r\n  (#) Optionally, in case of usage of DMA:\r\n        (++) Deinitialize the DMA using function HAL_DMA_DeInit().\r\n        (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn)   \r\n\r\n    @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup ADC ADC\r\n  * @brief ADC driver modules\r\n  * @{\r\n  */ \r\n\r\n#ifdef HAL_ADC_MODULE_ENABLED\r\n    \r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @addtogroup ADC_Private_Functions\r\n  * @{\r\n  */\r\n/* Private function prototypes -----------------------------------------------*/\r\nstatic void ADC_Init(ADC_HandleTypeDef* hadc);\r\nstatic void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);\r\nstatic void ADC_DMAError(DMA_HandleTypeDef *hdma);\r\nstatic void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup ADC_Exported_Functions ADC Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions \r\n *  @brief    Initialization and Configuration functions \r\n *\r\n@verbatim    \r\n ===============================================================================\r\n              ##### Initialization and de-initialization functions #####\r\n ===============================================================================\r\n    [..]  This section provides functions allowing to:\r\n      (+) Initialize and configure the ADC. \r\n      (+) De-initialize the ADC. \r\n         \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the ADCx peripheral according to the specified parameters \r\n  *         in the ADC_InitStruct and initializes the ADC MSP.\r\n  *           \r\n  * @note   This function is used to configure the global features of the ADC ( \r\n  *         ClockPrescaler, Resolution, Data Alignment and number of conversion), however,\r\n  *         the rest of the configuration parameters are specific to the regular\r\n  *         channels group (scan mode activation, continuous mode activation,\r\n  *         External trigger source and edge, DMA continuous request after the  \r\n  *         last transfer and End of conversion selection).\r\n  *             \r\n  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)\r\n{\r\n  HAL_StatusTypeDef tmp_hal_status = HAL_OK;\r\n  \r\n  /* Check ADC handle */\r\n  if(hadc == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\r\n  assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));\r\n  assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));\r\n  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ScanConvMode));\r\n  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));\r\n  assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv));\r\n  assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));\r\n  assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));\r\n  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));\r\n  assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));\r\n  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));\r\n\r\n  if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)\r\n  {\r\n    assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));\r\n  }\r\n\r\n  if(hadc->State == HAL_ADC_STATE_RESET)\r\n  {\r\n    /* Initialize ADC error code */\r\n    ADC_CLEAR_ERRORCODE(hadc);\r\n    \r\n    /* Allocate lock resource and initialize it */\r\n    hadc->Lock = HAL_UNLOCKED;\r\n    /* Init the low level hardware */\r\n    HAL_ADC_MspInit(hadc);\r\n  }\r\n  \r\n  /* Configuration of ADC parameters if previous preliminary actions are      */ \r\n  /* correctly completed.                                                     */\r\n  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))\r\n  {\r\n    /* Set ADC state */\r\n    ADC_STATE_CLR_SET(hadc->State,\r\n                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,\r\n                      HAL_ADC_STATE_BUSY_INTERNAL);\r\n    \r\n    /* Set ADC parameters */\r\n    ADC_Init(hadc);\r\n    \r\n    /* Set ADC error code to none */\r\n    ADC_CLEAR_ERRORCODE(hadc);\r\n    \r\n    /* Set the ADC state */\r\n    ADC_STATE_CLR_SET(hadc->State,\r\n                      HAL_ADC_STATE_BUSY_INTERNAL,\r\n                      HAL_ADC_STATE_READY);\r\n  }\r\n  else\r\n  {\r\n    tmp_hal_status = HAL_ERROR;\r\n  }\r\n  \r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hadc);\r\n\r\n  /* Return function status */\r\n  return tmp_hal_status;\r\n}\r\n\r\n/**\r\n  * @brief  Deinitializes the ADCx peripheral registers to their default reset values. \r\n  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)\r\n{\r\n  HAL_StatusTypeDef tmp_hal_status = HAL_OK;\r\n  \r\n  /* Check ADC handle */\r\n  if(hadc == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\r\n  \r\n  /* Set ADC state */\r\n  SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);\r\n  \r\n  /* Stop potential conversion on going, on regular and injected groups */\r\n  /* Disable ADC peripheral */\r\n  __HAL_ADC_DISABLE(hadc);\r\n  \r\n  /* Configuration of ADC parameters if previous preliminary actions are      */ \r\n  /* correctly completed.                                                     */\r\n  if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))\r\n  {\r\n    /* DeInit the low level hardware */\r\n    HAL_ADC_MspDeInit(hadc);\r\n    \r\n    /* Set ADC error code to none */\r\n    ADC_CLEAR_ERRORCODE(hadc);\r\n    \r\n    /* Set ADC state */\r\n    hadc->State = HAL_ADC_STATE_RESET;\r\n  }\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hadc);\r\n  \r\n  /* Return function status */\r\n  return tmp_hal_status;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the ADC MSP.\r\n  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.  \r\n  * @retval None\r\n  */\r\n__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hadc);\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_ADC_MspInit could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the ADC MSP.\r\n  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.  \r\n  * @retval None\r\n  */\r\n__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hadc);\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_ADC_MspDeInit could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ADC_Exported_Functions_Group2 IO operation functions\r\n *  @brief    IO operation functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n             ##### IO operation functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Start conversion of regular channel.\r\n      (+) Stop conversion of regular channel.\r\n      (+) Start conversion of regular channel and enable interrupt.\r\n      (+) Stop conversion of regular channel and disable interrupt.\r\n      (+) Start conversion of regular channel and enable DMA transfer.\r\n      (+) Stop conversion of regular channel and disable DMA transfer.\r\n      (+) Handle ADC interrupt request. \r\n               \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Enables ADC and starts conversion of the regular channels.\r\n  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)\r\n{\r\n  __IO uint32_t counter = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));\r\n  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); \r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hadc);\r\n  \r\n  /* Enable the ADC peripheral */\r\n  /* Check if ADC peripheral is disabled in order to enable it and wait during \r\n  Tstab time the ADC's stabilization */\r\n  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)\r\n  {  \r\n    /* Enable the Peripheral */\r\n    __HAL_ADC_ENABLE(hadc);\r\n    \r\n    /* Delay for ADC stabilization time */\r\n    /* Compute number of CPU cycles to wait for */\r\n    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));\r\n    while(counter != 0)\r\n    {\r\n      counter--;\r\n    }\r\n  }\r\n  \r\n  /* Start conversion if ADC is effectively enabled */\r\n  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))\r\n  {\r\n    /* Set ADC state                                                          */\r\n    /* - Clear state bitfield related to regular group conversion results     */\r\n    /* - Set state bitfield related to regular group operation                */\r\n    ADC_STATE_CLR_SET(hadc->State,\r\n                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,\r\n                      HAL_ADC_STATE_REG_BUSY);\r\n    \r\n    /* If conversions on group regular are also triggering group injected,    */\r\n    /* update ADC state.                                                      */\r\n    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)\r\n    {\r\n      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  \r\n    }\r\n    \r\n    /* State machine update: Check if an injected conversion is ongoing */\r\n    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))\r\n    {\r\n      /* Reset ADC error code fields related to conversions on group regular */\r\n      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         \r\n    }\r\n    else\r\n    {\r\n      /* Reset ADC all error code fields */\r\n      ADC_CLEAR_ERRORCODE(hadc);\r\n    }\r\n    \r\n    /* Process unlocked */\r\n    /* Unlock before starting ADC conversions: in case of potential           */\r\n    /* interruption, to let the process to ADC IRQ Handler.                   */\r\n    __HAL_UNLOCK(hadc);\r\n    \r\n    /* Clear regular group conversion flag and overrun flag */\r\n    /* (To ensure of no unknown state from potential previous ADC operations) */\r\n    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);\r\n    \r\n    /* Check if Multimode enabled */\r\n    if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))\r\n    {\r\n      /* if no external trigger present enable software conversion of regular channels */\r\n      if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) \r\n      {\r\n        /* Enable the selected ADC software conversion for regular group */\r\n        hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* if instance of handle correspond to ADC1 and  no external trigger present enable software conversion of regular channels */\r\n      if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))\r\n      {\r\n        /* Enable the selected ADC software conversion for regular group */\r\n          hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Disables ADC and stop conversion of regular channels.\r\n  * \r\n  * @note   Caution: This function will stop also injected channels.  \r\n  *\r\n  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  *\r\n  * @retval HAL status.\r\n  */\r\nHAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hadc);\r\n  \r\n  /* Stop potential conversion on going, on regular and injected groups */\r\n  /* Disable ADC peripheral */\r\n  __HAL_ADC_DISABLE(hadc);\r\n  \r\n  /* Check if ADC is effectively disabled */\r\n  if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))\r\n  {\r\n    /* Set ADC state */\r\n    ADC_STATE_CLR_SET(hadc->State,\r\n                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,\r\n                      HAL_ADC_STATE_READY);\r\n  }\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hadc);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Poll for regular conversion complete\r\n  * @note   ADC conversion flags EOS (end of sequence) and EOC (end of\r\n  *         conversion) are cleared by this function.\r\n  * @note   This function cannot be used in a particular setup: ADC configured \r\n  *         in DMA mode and polling for end of each conversion (ADC init\r\n  *         parameter \"EOCSelection\" set to ADC_EOC_SINGLE_CONV).\r\n  *         In this case, DMA resets the flag EOC and polling cannot be\r\n  *         performed on each conversion. Nevertheless, polling can still \r\n  *         be performed on the complete sequence.\r\n  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @param  Timeout: Timeout value in millisecond.  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Verification that ADC configuration is compliant with polling for      */\r\n  /* each conversion:                                                       */\r\n  /* Particular case is ADC configured in DMA mode and ADC sequencer with   */\r\n  /* several ranks and polling for end of each conversion.                  */\r\n  /* For code simplicity sake, this particular case is generalized to       */\r\n  /* ADC configured in DMA mode and polling for end of each conversion.     */\r\n  if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&\r\n      HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)    )\r\n  {\r\n    /* Update ADC state machine to error */\r\n    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);\r\n    \r\n    /* Process unlocked */\r\n    __HAL_UNLOCK(hadc);\r\n    \r\n    return HAL_ERROR;\r\n  }\r\n \r\n  /* Get tick */ \r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Check End of conversion flag */\r\n  while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))\r\n  {\r\n    /* Check if timeout is disabled (set to infinite wait) */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        /* Update ADC state machine to timeout */\r\n        SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);\r\n        \r\n        /* Process unlocked */\r\n        __HAL_UNLOCK(hadc);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Clear regular group conversion flag */\r\n  __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);\r\n  \r\n  /* Update ADC state machine */\r\n  SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);\r\n  \r\n  /* Determine whether any further conversion upcoming on group regular       */\r\n  /* by external trigger, continuous mode or scan sequence on going.          */\r\n  /* Note: On STM32F7, there is no independent flag of end of sequence.       */\r\n  /*       The test of scan sequence on going is done either with scan        */\r\n  /*       sequence disabled or with end of conversion flag set to            */\r\n  /*       of end of sequence.                                                */\r\n  if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&\r\n     (hadc->Init.ContinuousConvMode == DISABLE)            &&\r\n     (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||\r\n      HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )\r\n  {\r\n    /* Set ADC state */\r\n    CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);   \r\n    \r\n    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))\r\n    { \r\n      SET_BIT(hadc->State, HAL_ADC_STATE_READY);\r\n    }\r\n  }\r\n  \r\n  /* Return ADC state */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Poll for conversion event\r\n  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @param  EventType: the ADC event type.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg ADC_AWD_EVENT: ADC Analog watch Dog event.\r\n  *            @arg ADC_OVR_EVENT: ADC Overrun event.\r\n  * @param  Timeout: Timeout value in millisecond.   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\r\n  assert_param(IS_ADC_EVENT_TYPE(EventType));\r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Check selected event flag */\r\n  while(!(__HAL_ADC_GET_FLAG(hadc,EventType)))\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        /* Update ADC state machine to timeout */\r\n        SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);\r\n        \r\n        /* Process unlocked */\r\n        __HAL_UNLOCK(hadc);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Analog watchdog (level out of window) event */\r\n  if(EventType == ADC_AWD_EVENT)\r\n  {\r\n    /* Set ADC state */\r\n    SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);\r\n      \r\n    /* Clear ADC analog watchdog flag */\r\n    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);\r\n  }\r\n  /* Overrun event */\r\n  else\r\n  {\r\n    /* Set ADC state */\r\n    SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);\r\n    /* Set ADC error code to overrun */\r\n    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);\r\n    \r\n    /* Clear ADC overrun flag */\r\n    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);\r\n  }\r\n  \r\n  /* Return ADC state */\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Enables the interrupt and starts ADC conversion of regular channels.\r\n  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @retval HAL status.\r\n  */\r\nHAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)\r\n{\r\n  __IO uint32_t counter = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));\r\n  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); \r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hadc);\r\n  \r\n  /* Enable the ADC peripheral */\r\n  /* Check if ADC peripheral is disabled in order to enable it and wait during \r\n     Tstab time the ADC's stabilization */\r\n  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)\r\n  {  \r\n    /* Enable the Peripheral */\r\n    __HAL_ADC_ENABLE(hadc);\r\n    \r\n    /* Delay for ADC stabilization time */\r\n    /* Compute number of CPU cycles to wait for */\r\n    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));\r\n    while(counter != 0)\r\n    {\r\n      counter--;\r\n    }\r\n  }\r\n  \r\n  /* Start conversion if ADC is effectively enabled */\r\n  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))\r\n  {\r\n    /* Set ADC state                                                          */\r\n    /* - Clear state bitfield related to regular group conversion results     */\r\n    /* - Set state bitfield related to regular group operation                */\r\n    ADC_STATE_CLR_SET(hadc->State,\r\n                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,\r\n                      HAL_ADC_STATE_REG_BUSY);\r\n    \r\n    /* If conversions on group regular are also triggering group injected,    */\r\n    /* update ADC state.                                                      */\r\n    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)\r\n    {\r\n      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  \r\n    }\r\n    \r\n    /* State machine update: Check if an injected conversion is ongoing */\r\n    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))\r\n    {\r\n      /* Reset ADC error code fields related to conversions on group regular */\r\n      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         \r\n    }\r\n    else\r\n    {\r\n      /* Reset ADC all error code fields */\r\n      ADC_CLEAR_ERRORCODE(hadc);\r\n    }\r\n    \r\n    /* Process unlocked */\r\n    /* Unlock before starting ADC conversions: in case of potential           */\r\n    /* interruption, to let the process to ADC IRQ Handler.                   */\r\n    __HAL_UNLOCK(hadc);\r\n    \r\n    /* Clear regular group conversion flag and overrun flag */\r\n    /* (To ensure of no unknown state from potential previous ADC operations) */\r\n    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);\r\n    \r\n    /* Enable end of conversion interrupt for regular group */\r\n    __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));\r\n    \r\n    /* Check if Multimode enabled */\r\n    if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))\r\n    {\r\n      /* if no external trigger present enable software conversion of regular channels */\r\n      if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) \r\n      {\r\n        /* Enable the selected ADC software conversion for regular group */\r\n        hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* if instance of handle correspond to ADC1 and  no external trigger present enable software conversion of regular channels */\r\n      if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))\r\n      {\r\n        /* Enable the selected ADC software conversion for regular group */\r\n          hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Disables the interrupt and stop ADC conversion of regular channels.\r\n  * \r\n  * @note   Caution: This function will stop also injected channels.  \r\n  *\r\n  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @retval HAL status.\r\n  */\r\nHAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hadc);\r\n  \r\n  /* Stop potential conversion on going, on regular and injected groups */\r\n  /* Disable ADC peripheral */\r\n  __HAL_ADC_DISABLE(hadc);\r\n  \r\n  /* Check if ADC is effectively disabled */\r\n  if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))\r\n  {\r\n  \t/* Disable ADC end of conversion interrupt for regular group */\r\n    __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));\r\n\r\n    /* Set ADC state */\r\n    ADC_STATE_CLR_SET(hadc->State,\r\n                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,\r\n                      HAL_ADC_STATE_READY);\r\n  }\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hadc);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Handles ADC interrupt request  \r\n  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @retval None\r\n  */\r\nvoid HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)\r\n{\r\n  uint32_t tmp1 = 0, tmp2 = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));\r\n  assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));\r\n  assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));\r\n  \r\n  tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC);\r\n  tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC);\r\n  /* Check End of conversion flag for regular channels */\r\n  if(tmp1 && tmp2)\r\n  {\r\n    /* Update state machine on conversion status if not in error state */\r\n    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))\r\n    {\r\n      /* Set ADC state */\r\n      SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); \r\n    }\r\n    \r\n    /* Determine whether any further conversion upcoming on group regular   */\r\n    /* by external trigger, continuous mode or scan sequence on going.      */\r\n    /* Note: On STM32F7, there is no independent flag of end of sequence.   */\r\n    /*       The test of scan sequence on going is done either with scan    */\r\n    /*       sequence disabled or with end of conversion flag set to        */\r\n    /*       of end of sequence.                                            */\r\n    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&\r\n       (hadc->Init.ContinuousConvMode == DISABLE)            &&\r\n       (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || \r\n        HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )\r\n    {\r\n      /* Disable ADC end of single conversion interrupt on group regular */\r\n      /* Note: Overrun interrupt was enabled with EOC interrupt in          */\r\n      /* HAL_ADC_Start_IT(), but is not disabled here because can be used   */\r\n      /* by overrun IRQ process below.                                      */\r\n      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);\r\n      \r\n      /* Set ADC state */\r\n      CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);\r\n      \r\n      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))\r\n      {\r\n        SET_BIT(hadc->State, HAL_ADC_STATE_READY);\r\n      }\r\n    }\r\n    \r\n    /* Conversion complete callback */ \r\n    HAL_ADC_ConvCpltCallback(hadc);\r\n    \r\n    /* Clear regular group conversion flag */\r\n    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);\r\n  }\r\n  \r\n  tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC);\r\n  tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC);                               \r\n  /* Check End of conversion flag for injected channels */\r\n  if(tmp1 && tmp2)\r\n  {\r\n    /* Update state machine on conversion status if not in error state */\r\n    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))\r\n    {\r\n      /* Set ADC state */\r\n      SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);\r\n    }\r\n\r\n    /* Determine whether any further conversion upcoming on group injected  */\r\n    /* by external trigger, scan sequence on going or by automatic injected */\r\n    /* conversion from group regular (same conditions as group regular      */\r\n    /* interruption disabling above).                                       */\r\n    if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                    &&\r\n       (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||\r\n        HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)) &&\r\n       (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&\r\n       (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&\r\n       (hadc->Init.ContinuousConvMode == DISABLE))))\r\n    {\r\n      /* Disable ADC end of single conversion interrupt on group injected */\r\n      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);\r\n      \r\n      /* Set ADC state */\r\n      CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);   \r\n\r\n      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))\r\n      { \r\n        SET_BIT(hadc->State, HAL_ADC_STATE_READY);\r\n      }\r\n    }\r\n\r\n    /* Conversion complete callback */ \r\n    HAL_ADCEx_InjectedConvCpltCallback(hadc);\r\n    \r\n    /* Clear injected group conversion flag */\r\n    __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));\r\n  }\r\n  \r\n  tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD);\r\n  tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD);                          \r\n  /* Check Analog watchdog flag */\r\n  if(tmp1 && tmp2)\r\n  {\r\n    if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))\r\n    {\r\n      /* Set ADC state */\r\n      SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);\r\n      \r\n      /* Level out of window callback */ \r\n      HAL_ADC_LevelOutOfWindowCallback(hadc);\r\n      \r\n      /* Clear the ADC analog watchdog flag */\r\n      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);\r\n    }\r\n  }\r\n  \r\n  tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR);\r\n  tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR);\r\n  /* Check Overrun flag */\r\n  if(tmp1 && tmp2)\r\n  {\r\n    /* Note: On STM32F7, ADC overrun can be set through other parameters    */\r\n    /*       refer to description of parameter \"EOCSelection\" for more      */\r\n    /*       details.                                                       */\r\n    \r\n    /* Set ADC error code to overrun */\r\n    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);\r\n    \r\n    /* Clear ADC overrun flag */\r\n    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);\r\n    \r\n    /* Error callback */ \r\n    HAL_ADC_ErrorCallback(hadc);\r\n    \r\n    /* Clear the Overrun flag */\r\n    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral  \r\n  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @param  pData: The destination Buffer address.\r\n  * @param  Length: The length of data to be transferred from ADC peripheral to memory.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)\r\n{\r\n  __IO uint32_t counter = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));\r\n  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); \r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hadc);\r\n  \r\n  /* Enable the ADC peripheral */\r\n  /* Check if ADC peripheral is disabled in order to enable it and wait during \r\n     Tstab time the ADC's stabilization */\r\n  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)\r\n  {  \r\n    /* Enable the Peripheral */\r\n    __HAL_ADC_ENABLE(hadc);\r\n    \r\n    /* Delay for ADC stabilization time */\r\n    /* Compute number of CPU cycles to wait for */\r\n    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));\r\n    while(counter != 0)\r\n    {\r\n      counter--;\r\n    }\r\n  }\r\n  \r\n  /* Start conversion if ADC is effectively enabled */\r\n  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))\r\n  {\r\n    /* Set ADC state                                                          */\r\n    /* - Clear state bitfield related to regular group conversion results     */\r\n    /* - Set state bitfield related to regular group operation                */\r\n    ADC_STATE_CLR_SET(hadc->State,\r\n                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,\r\n                      HAL_ADC_STATE_REG_BUSY);\r\n    \r\n    /* If conversions on group regular are also triggering group injected,    */\r\n    /* update ADC state.                                                      */\r\n    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)\r\n    {\r\n      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  \r\n    }\r\n    \r\n    /* State machine update: Check if an injected conversion is ongoing */\r\n    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))\r\n    {\r\n      /* Reset ADC error code fields related to conversions on group regular */\r\n      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         \r\n    }\r\n    else\r\n    {\r\n      /* Reset ADC all error code fields */\r\n      ADC_CLEAR_ERRORCODE(hadc);\r\n    }\r\n    \r\n    /* Process unlocked */\r\n    /* Unlock before starting ADC conversions: in case of potential           */\r\n    /* interruption, to let the process to ADC IRQ Handler.                   */\r\n    __HAL_UNLOCK(hadc);   \r\n\r\n    /* Set the DMA transfer complete callback */\r\n    hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;\r\n\r\n    /* Set the DMA half transfer complete callback */\r\n    hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;\r\n    \r\n    /* Set the DMA error callback */\r\n    hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;\r\n\r\n    \r\n    /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */\r\n    /* start (in case of SW start):                                           */\r\n    \r\n    /* Clear regular group conversion flag and overrun flag */\r\n    /* (To ensure of no unknown state from potential previous ADC operations) */\r\n    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);\r\n\r\n    /* Enable ADC overrun interrupt */\r\n    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);\r\n    \r\n    /* Enable ADC DMA mode */\r\n    hadc->Instance->CR2 |= ADC_CR2_DMA;\r\n    \r\n    /* Start the DMA channel */\r\n    HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);\r\n    \r\n    /* Check if Multimode enabled */\r\n    if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))\r\n    {\r\n      /* if no external trigger present enable software conversion of regular channels */\r\n      if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) \r\n      {\r\n        /* Enable the selected ADC software conversion for regular group */\r\n        hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* if instance of handle correspond to ADC1 and  no external trigger present enable software conversion of regular channels */\r\n      if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))\r\n      {\r\n        /* Enable the selected ADC software conversion for regular group */\r\n          hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Disables ADC DMA (Single-ADC mode) and disables ADC peripheral    \r\n  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)\r\n{\r\n  HAL_StatusTypeDef tmp_hal_status = HAL_OK;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hadc);\r\n  \r\n  /* Stop potential conversion on going, on regular and injected groups */\r\n  /* Disable ADC peripheral */\r\n  __HAL_ADC_DISABLE(hadc);\r\n  \r\n  /* Check if ADC is effectively disabled */\r\n  if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))\r\n  {\r\n    /* Disable the selected ADC DMA mode */\r\n    hadc->Instance->CR2 &= ~ADC_CR2_DMA;\r\n    \r\n    /* Disable the DMA channel (in case of DMA in circular mode or stop while */\r\n    /* DMA transfer is on going)                                              */\r\n    tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);\r\n    \r\n    /* Disable ADC overrun interrupt */\r\n    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);\r\n    \r\n    /* Set ADC state */\r\n    ADC_STATE_CLR_SET(hadc->State,\r\n                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,\r\n                      HAL_ADC_STATE_READY);\r\n  }\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hadc);\r\n  \r\n  /* Return function status */\r\n  return tmp_hal_status;\r\n}\r\n\r\n/**\r\n  * @brief  Gets the converted value from data register of regular channel.\r\n  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @retval Converted value\r\n  */\r\nuint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)\r\n{       \r\n  /* Return the selected ADC converted value */ \r\n  return hadc->Instance->DR;\r\n}\r\n\r\n/**\r\n  * @brief  Regular conversion complete callback in non blocking mode \r\n  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hadc);\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_ADC_ConvCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Regular conversion half DMA transfer callback in non blocking mode \r\n  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hadc);\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Analog watchdog callback in non blocking mode \r\n  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hadc);\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Error ADC callback.\r\n  * @note   In case of error due to overrun when using ADC with DMA transfer \r\n  *         (HAL ADC handle paramater \"ErrorCode\" to state \"HAL_ADC_ERROR_OVR\"):\r\n  *         - Reinitialize the DMA using function \"HAL_ADC_Stop_DMA()\".\r\n  *         - If needed, restart a new ADC conversion using function\r\n  *           \"HAL_ADC_Start_DMA()\"\r\n  *           (this function is also clearing overrun flag)\r\n  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hadc);\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_ADC_ErrorCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions\r\n *  @brief   \tPeripheral Control functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n             ##### Peripheral Control functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Configure regular channels. \r\n      (+) Configure injected channels.\r\n      (+) Configure multimode.\r\n      (+) Configure the analog watch dog.\r\n      \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n  /**\r\n  * @brief  Configures for the selected ADC regular channel its corresponding\r\n  *         rank in the sequencer and its sample time.\r\n  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @param  sConfig: ADC configuration structure. \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)\r\n{\r\n  __IO uint32_t counter = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_ADC_CHANNEL(sConfig->Channel));\r\n  assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));\r\n  assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hadc);\r\n\t\t\t\r\n\t/* if ADC_Channel_10 ... ADC_Channel_18 is selected */\r\n\tif (sConfig->Channel > ADC_CHANNEL_9)\r\n\t{\r\n\t\t/* Clear the old sample time */\r\n\t\thadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);\r\n\r\n\t\tif (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)\r\n\t\t{\r\n\t\t\t/* Set the new sample time */\r\n\t\t\thadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, ADC_CHANNEL_18);\r\n\t\t}\r\n\t  else\r\n\t  {\t\r\n\t\t  /* Set the new sample time */\r\n\t\t  hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);\r\n\t  }\r\n  }\r\n  else /* ADC_Channel include in ADC_Channel_[0..9] */\r\n  {\r\n    /* Clear the old sample time */\r\n    hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);\r\n    \r\n    /* Set the new sample time */\r\n    hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);\r\n  }\r\n  \r\n  /* For Rank 1 to 6 */\r\n  if (sConfig->Rank < 7)\r\n  {\r\n    /* Clear the old SQx bits for the selected rank */\r\n    hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);\r\n    \r\n    /* Set the SQx bits for the selected rank */\r\n    hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);\r\n  }\r\n  /* For Rank 7 to 12 */\r\n  else if (sConfig->Rank < 13)\r\n  {\r\n    /* Clear the old SQx bits for the selected rank */\r\n    hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);\r\n    \r\n    /* Set the SQx bits for the selected rank */\r\n    hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);\r\n  }\r\n  /* For Rank 13 to 16 */\r\n  else\r\n  {\r\n    /* Clear the old SQx bits for the selected rank */\r\n    hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);\r\n    \r\n    /* Set the SQx bits for the selected rank */\r\n    hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);\r\n  }\r\n  \r\n  /* if ADC1 Channel_18 is selected enable VBAT Channel */\r\n  if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))\r\n  {\r\n    /* Enable the VBAT channel*/\r\n    ADC->CCR |= ADC_CCR_VBATE;\r\n  }\r\n  \r\n  /* if ADC1 Channel_18 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */\r\n  if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)))\r\n  {\r\n    /* Enable the TSVREFE channel*/\r\n    ADC->CCR |= ADC_CCR_TSVREFE;\r\n\r\n    if(sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)\r\n    {\r\n      /* Delay for temperature sensor stabilization time */\r\n      /* Compute number of CPU cycles to wait for */\r\n      counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));\r\n      while(counter != 0)\r\n      {\r\n        counter--;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hadc);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Configures the analog watchdog.\r\n  * @note   Analog watchdog thresholds can be modified while ADC conversion\r\n  *         is on going.\r\n  *         In this case, some constraints must be taken into account:\r\n  *         the programmed threshold values are effective from the next\r\n  *         ADC EOC (end of unitary conversion).\r\n  *         Considering that registers write delay may happen due to\r\n  *         bus activity, this might cause an uncertainty on the\r\n  *         effective timing of the new programmed threshold values.\r\n  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @param  AnalogWDGConfig : pointer to an ADC_AnalogWDGConfTypeDef structure \r\n  *         that contains the configuration information of ADC analog watchdog.\r\n  * @retval HAL status\t  \r\n  */\r\nHAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)\r\n{\r\n#ifdef USE_FULL_ASSERT  \r\n  uint32_t tmp = 0;\r\n#endif /* USE_FULL_ASSERT  */  \r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_ADC_ANALOG_WATCHDOG(AnalogWDGConfig->WatchdogMode));\r\n  assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));\r\n  assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));\r\n\r\n#ifdef USE_FULL_ASSERT  \r\n  tmp = ADC_GET_RESOLUTION(hadc);\r\n  assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->HighThreshold));\r\n  assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->LowThreshold));\r\n#endif /* USE_FULL_ASSERT  */\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hadc);\r\n  \r\n  if(AnalogWDGConfig->ITMode == ENABLE)\r\n  {\r\n    /* Enable the ADC Analog watchdog interrupt */\r\n    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);\r\n  }\r\n  else\r\n  {\r\n    /* Disable the ADC Analog watchdog interrupt */\r\n    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);\r\n  }\r\n  \r\n  /* Clear AWDEN, JAWDEN and AWDSGL bits */\r\n  hadc->Instance->CR1 &=  ~(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN);\r\n  \r\n  /* Set the analog watchdog enable mode */\r\n  hadc->Instance->CR1 |= AnalogWDGConfig->WatchdogMode;\r\n  \r\n  /* Set the high threshold */\r\n  hadc->Instance->HTR = AnalogWDGConfig->HighThreshold;\r\n  \r\n  /* Set the low threshold */\r\n  hadc->Instance->LTR = AnalogWDGConfig->LowThreshold;\r\n  \r\n  /* Clear the Analog watchdog channel select bits */\r\n  hadc->Instance->CR1 &= ~ADC_CR1_AWDCH;\r\n  \r\n  /* Set the Analog watchdog channel */\r\n  hadc->Instance->CR1 |= (uint32_t)((uint16_t)(AnalogWDGConfig->Channel));\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hadc);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ADC_Exported_Functions_Group4 ADC Peripheral State functions\r\n *  @brief   ADC Peripheral State functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n            ##### Peripheral State and errors functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides functions allowing to\r\n      (+) Check the ADC state\r\n      (+) Check the ADC Error\r\n         \r\n@endverbatim\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @brief  return the ADC state\r\n  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @retval HAL state\r\n  */\r\nuint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)\r\n{\r\n  /* Return ADC state */\r\n  return hadc->State;\r\n}\r\n\r\n/**\r\n  * @brief  Return the ADC error code\r\n  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @retval ADC Error Code\r\n  */\r\nuint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)\r\n{\r\n  return hadc->ErrorCode;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup ADC_Private_Functions ADC Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the ADCx peripheral according to the specified parameters \r\n  *         in the ADC_InitStruct without initializing the ADC MSP.       \r\n  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.  \r\n  * @retval None\r\n  */\r\nstatic void ADC_Init(ADC_HandleTypeDef* hadc)\r\n{\r\n  /* Set ADC parameters */\r\n  /* Set the ADC clock prescaler */\r\n  ADC->CCR &= ~(ADC_CCR_ADCPRE);\r\n  ADC->CCR |=  hadc->Init.ClockPrescaler;\r\n  \r\n  /* Set ADC scan mode */\r\n  hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);\r\n  hadc->Instance->CR1 |=  ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);\r\n  \r\n  /* Set ADC resolution */\r\n  hadc->Instance->CR1 &= ~(ADC_CR1_RES);\r\n  hadc->Instance->CR1 |=  hadc->Init.Resolution;\r\n  \r\n  /* Set ADC data alignment */\r\n  hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);\r\n  hadc->Instance->CR2 |= hadc->Init.DataAlign;\r\n  \r\n  /* Enable external trigger if trigger selection is different of software  */\r\n  /* start.                                                                 */\r\n  /* Note: This configuration keeps the hardware feature of parameter       */\r\n  /*       ExternalTrigConvEdge \"trigger edge none\" equivalent to           */\r\n  /*       software start.                                                  */\r\n  if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)\r\n  {\r\n    /* Select external trigger to start conversion */\r\n    hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);\r\n    hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;\r\n    \r\n    /* Select external trigger polarity */\r\n    hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);\r\n    hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;\r\n  }\r\n  else\r\n  {\r\n    /* Reset the external trigger */\r\n    hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);\r\n    hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);\r\n  }\r\n  \r\n  /* Enable or disable ADC continuous conversion mode */\r\n  hadc->Instance->CR2 &= ~(ADC_CR2_CONT);\r\n  hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode);\r\n  \r\n  if(hadc->Init.DiscontinuousConvMode != DISABLE)\r\n  {\r\n    assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));\r\n  \r\n    /* Enable the selected ADC regular discontinuous mode */\r\n    hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN;\r\n    \r\n    /* Set the number of channels to be converted in discontinuous mode */\r\n    hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM);\r\n    hadc->Instance->CR1 |=  ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);\r\n  }\r\n  else\r\n  {\r\n    /* Disable the selected ADC regular discontinuous mode */\r\n    hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN);\r\n  }\r\n  \r\n  /* Set ADC number of conversion */\r\n  hadc->Instance->SQR1 &= ~(ADC_SQR1_L);\r\n  hadc->Instance->SQR1 |=  ADC_SQR1(hadc->Init.NbrOfConversion);\r\n  \r\n  /* Enable or disable ADC DMA continuous request */\r\n  hadc->Instance->CR2 &= ~(ADC_CR2_DDS);\r\n  hadc->Instance->CR2 |= ADC_CR2_DMAContReq(hadc->Init.DMAContinuousRequests);\r\n  \r\n  /* Enable or disable ADC end of conversion selection */\r\n  hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);\r\n  hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection);\r\n}\r\n\r\n/**\r\n  * @brief  DMA transfer complete callback. \r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)   \r\n{\r\n  /* Retrieve ADC handle corresponding to current DMA handle */\r\n  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  \r\n  /* Update state machine on conversion status if not in error state */\r\n  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))\r\n  {\r\n    /* Update ADC state machine */\r\n    SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);\r\n    \r\n    /* Determine whether any further conversion upcoming on group regular   */\r\n    /* by external trigger, continuous mode or scan sequence on going.      */\r\n    /* Note: On STM32F7, there is no independent flag of end of sequence.   */\r\n    /*       The test of scan sequence on going is done either with scan    */\r\n    /*       sequence disabled or with end of conversion flag set to        */\r\n    /*       of end of sequence.                                            */\r\n    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&\r\n       (hadc->Init.ContinuousConvMode == DISABLE)            &&\r\n       (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || \r\n        HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )\r\n    {\r\n      /* Disable ADC end of single conversion interrupt on group regular */\r\n      /* Note: Overrun interrupt was enabled with EOC interrupt in          */\r\n      /* HAL_ADC_Start_IT(), but is not disabled here because can be used   */\r\n      /* by overrun IRQ process below.                                      */\r\n      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);\r\n      \r\n      /* Set ADC state */\r\n      CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);   \r\n      \r\n      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))\r\n      {\r\n        SET_BIT(hadc->State, HAL_ADC_STATE_READY);\r\n      }\r\n    }\r\n    \r\n    /* Conversion complete callback */\r\n    HAL_ADC_ConvCpltCallback(hadc);\r\n  }\r\n  else\r\n  {\r\n    /* Call DMA error callback */\r\n    hadc->DMA_Handle->XferErrorCallback(hdma);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  DMA half transfer complete callback. \r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)   \r\n{\r\n  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  /* Conversion complete callback */\r\n  HAL_ADC_ConvHalfCpltCallback(hadc); \r\n}\r\n\r\n/**\r\n  * @brief  DMA error callback \r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void ADC_DMAError(DMA_HandleTypeDef *hdma)   \r\n{\r\n  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  hadc->State= HAL_ADC_STATE_ERROR_DMA;\r\n  /* Set ADC error code to DMA error */\r\n  hadc->ErrorCode |= HAL_ADC_ERROR_DMA;\r\n  HAL_ADC_ErrorCallback(hadc); \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_ADC_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_adc_ex.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   This file provides firmware functions to manage the following \r\n  *          functionalities of the ADC extension peripheral:\r\n  *           + Extended features functions\r\n  *         \r\n  @verbatim\r\n  ==============================================================================\r\n                    ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]\r\n    (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():\r\n       (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()\r\n       (##) ADC pins configuration\r\n             (+++) Enable the clock for the ADC GPIOs using the following function:\r\n                   __HAL_RCC_GPIOx_CLK_ENABLE()  \r\n             (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init() \r\n       (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())\r\n             (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()\r\n             (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()\r\n             (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()\r\n      (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())\r\n             (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()\r\n             (+++) Configure and enable two DMA streams stream for managing data\r\n                 transfer from peripheral to memory (output stream)\r\n             (+++) Associate the initialized DMA handle to the ADC DMA handle\r\n                 using  __HAL_LINKDMA()\r\n             (+++) Configure the priority and enable the NVIC for the transfer complete\r\n                 interrupt on the two DMA Streams. The output stream should have higher\r\n                 priority than the input stream.                  \r\n     (#) Configure the ADC Prescaler, conversion resolution and data alignment \r\n         using the HAL_ADC_Init() function. \r\n  \r\n     (#) Configure the ADC Injected channels group features, use HAL_ADC_Init()\r\n         and HAL_ADC_ConfigChannel() functions.\r\n         \r\n     (#) Three operation modes are available within this driver :     \r\n  \r\n     *** Polling mode IO operation ***\r\n     =================================\r\n     [..]    \r\n       (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart() \r\n       (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage\r\n           user can specify the value of timeout according to his end application      \r\n       (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue() function.\r\n       (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop()\r\n  \r\n     *** Interrupt mode IO operation ***    \r\n     ===================================\r\n     [..]    \r\n       (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_IT() \r\n       (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine\r\n       (+) At ADC end of conversion HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can \r\n            add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback \r\n       (+) In case of ADC Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can \r\n            add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback\r\n       (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_IT()\r\n       \r\n            \r\n     *** DMA mode IO operation ***    \r\n     ==============================\r\n     [..]    \r\n       (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_DMA(), at this stage the user specify the length \r\n           of data to be transferred at each end of conversion \r\n       (+) At The end of data transfer ba HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can \r\n            add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback \r\n       (+) In case of transfer Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can \r\n            add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback\r\n        (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_DMA()\r\n        \r\n     *** Multi mode ADCs Regular channels configuration ***\r\n     ======================================================\r\n     [..]        \r\n       (+) Select the Multi mode ADC regular channels features (dual or triple mode)  \r\n          and configure the DMA mode using HAL_ADCEx_MultiModeConfigChannel() functions. \r\n       (+) Start the ADC peripheral using HAL_ADCEx_MultiModeStart_DMA(), at this stage the user specify the length \r\n           of data to be transferred at each end of conversion           \r\n       (+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue() function.\r\n  \r\n  \r\n    @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup ADCEx ADCEx\r\n  * @brief ADC Extended driver modules\r\n  * @{\r\n  */ \r\n\r\n#ifdef HAL_ADC_MODULE_ENABLED\r\n    \r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/ \r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @addtogroup ADCEx_Private_Functions\r\n  * @{\r\n  */\r\n/* Private function prototypes -----------------------------------------------*/\r\nstatic void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma);\r\nstatic void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma);\r\nstatic void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma); \r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup ADCEx_Exported_Functions ADC Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup ADCEx_Exported_Functions_Group1  Extended features functions \r\n  *  @brief    Extended features functions  \r\n  *\r\n@verbatim   \r\n ===============================================================================\r\n                 ##### Extended features functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Start conversion of injected channel.\r\n      (+) Stop conversion of injected channel.\r\n      (+) Start multimode and enable DMA transfer.\r\n      (+) Stop multimode and disable DMA transfer.\r\n      (+) Get result of injected channel conversion.\r\n      (+) Get result of multimode conversion.\r\n      (+) Configure injected channels.\r\n      (+) Configure multimode.\r\n               \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Enables the selected ADC software start conversion of the injected channels.\r\n  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)\r\n{\r\n  __IO uint32_t counter = 0;\r\n  uint32_t tmp1 = 0, tmp2 = 0;\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hadc);\r\n  \r\n  /* Enable the ADC peripheral */\r\n  \r\n  /* Check if ADC peripheral is disabled in order to enable it and wait during \r\n     Tstab time the ADC's stabilization */\r\n  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)\r\n  {  \r\n    /* Enable the Peripheral */\r\n    __HAL_ADC_ENABLE(hadc);\r\n    \r\n    /* Delay for ADC stabilization time */\r\n    /* Compute number of CPU cycles to wait for */\r\n    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));\r\n    while(counter != 0)\r\n    {\r\n      counter--;\r\n    }\r\n  }\r\n  \r\n  /* Start conversion if ADC is effectively enabled */\r\n  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))\r\n  {\r\n    /* Set ADC state                                                          */\r\n    /* - Clear state bitfield related to injected group conversion results    */\r\n    /* - Set state bitfield related to injected operation                     */\r\n    ADC_STATE_CLR_SET(hadc->State,\r\n                      HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,\r\n                      HAL_ADC_STATE_INJ_BUSY);\r\n    \r\n    /* Check if a regular conversion is ongoing */\r\n    /* Note: On this device, there is no ADC error code fields related to     */\r\n    /*       conversions on group injected only. In case of conversion on     */\r\n    /*       going on group regular, no error code is reset.                  */\r\n    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))\r\n    {\r\n      /* Reset ADC all error code fields */\r\n      ADC_CLEAR_ERRORCODE(hadc);\r\n    }\r\n    \r\n    /* Process unlocked */\r\n    /* Unlock before starting ADC conversions: in case of potential           */\r\n    /* interruption, to let the process to ADC IRQ Handler.                   */\r\n    __HAL_UNLOCK(hadc);\r\n    \r\n    /* Clear injected group conversion flag */\r\n    /* (To ensure of no unknown state from potential previous ADC operations) */\r\n    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);\r\n    \r\n    /* Check if Multimode enabled */\r\n    if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))\r\n    {\r\n      tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);\r\n      tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);\r\n      if(tmp1 && tmp2)\r\n      {\r\n        /* Enable the selected ADC software conversion for injected group */\r\n        hadc->Instance->CR2 |= ADC_CR2_JSWSTART;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);\r\n      tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);\r\n      if((hadc->Instance == ADC1) && tmp1 && tmp2)  \r\n      {\r\n        /* Enable the selected ADC software conversion for injected group */\r\n        hadc->Instance->CR2 |= ADC_CR2_JSWSTART;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Enables the interrupt and starts ADC conversion of injected channels.\r\n  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  *\r\n  * @retval HAL status.\r\n  */\r\nHAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)\r\n{\r\n  __IO uint32_t counter = 0;\r\n  uint32_t tmp1 = 0, tmp2 = 0;\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hadc);\r\n  \r\n  /* Enable the ADC peripheral */\r\n  \r\n  /* Check if ADC peripheral is disabled in order to enable it and wait during \r\n     Tstab time the ADC's stabilization */\r\n  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)\r\n  {  \r\n    /* Enable the Peripheral */\r\n    __HAL_ADC_ENABLE(hadc);\r\n    \r\n    /* Delay for ADC stabilization time */\r\n    /* Compute number of CPU cycles to wait for */\r\n    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));\r\n    while(counter != 0)\r\n    {\r\n      counter--;\r\n    }\r\n  }\r\n  \r\n  /* Start conversion if ADC is effectively enabled */\r\n  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))\r\n  {\r\n    /* Set ADC state                                                          */\r\n    /* - Clear state bitfield related to injected group conversion results    */\r\n    /* - Set state bitfield related to injected operation                     */\r\n    ADC_STATE_CLR_SET(hadc->State,\r\n                      HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,\r\n                      HAL_ADC_STATE_INJ_BUSY);\r\n    \r\n    /* Check if a regular conversion is ongoing */\r\n    /* Note: On this device, there is no ADC error code fields related to     */\r\n    /*       conversions on group injected only. In case of conversion on     */\r\n    /*       going on group regular, no error code is reset.                  */\r\n    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))\r\n    {\r\n      /* Reset ADC all error code fields */\r\n      ADC_CLEAR_ERRORCODE(hadc);\r\n    }\r\n    \r\n    /* Process unlocked */\r\n    /* Unlock before starting ADC conversions: in case of potential           */\r\n    /* interruption, to let the process to ADC IRQ Handler.                   */\r\n    __HAL_UNLOCK(hadc);\r\n    \r\n    /* Clear injected group conversion flag */\r\n    /* (To ensure of no unknown state from potential previous ADC operations) */\r\n    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);\r\n    \r\n    /* Enable end of conversion interrupt for injected channels */\r\n    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);\r\n    \r\n    /* Check if Multimode enabled */\r\n    if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))\r\n    {\r\n      tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);\r\n      tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);\r\n      if(tmp1 && tmp2)\r\n      {\r\n        /* Enable the selected ADC software conversion for injected group */\r\n        hadc->Instance->CR2 |= ADC_CR2_JSWSTART;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);\r\n      tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);\r\n      if((hadc->Instance == ADC1) && tmp1 && tmp2)  \r\n      {\r\n        /* Enable the selected ADC software conversion for injected group */\r\n        hadc->Instance->CR2 |= ADC_CR2_JSWSTART;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stop conversion of injected channels. Disable ADC peripheral if\r\n  *         no regular conversion is on going.\r\n  * @note   If ADC must be disabled and if conversion is on going on \r\n  *         regular group, function HAL_ADC_Stop must be used to stop both\r\n  *         injected and regular groups, and disable the ADC.\r\n  * @note   If injected group mode auto-injection is enabled,\r\n  *         function HAL_ADC_Stop must be used.\r\n  * @note   In case of auto-injection mode, HAL_ADC_Stop must be used.\r\n  * @param  hadc: ADC handle\r\n  * @retval None\r\n  */\r\nHAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)\r\n{\r\n  HAL_StatusTypeDef tmp_hal_status = HAL_OK;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hadc);\r\n    \r\n  /* Stop potential conversion and disable ADC peripheral                     */\r\n  /* Conditioned to:                                                          */\r\n  /* - No conversion on the other group (regular group) is intended to        */\r\n  /*   continue (injected and regular groups stop conversion and ADC disable  */\r\n  /*   are common)                                                            */\r\n  /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */\r\n  if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET)  &&\r\n     HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )\r\n  {\r\n    /* Stop potential conversion on going, on regular and injected groups */\r\n    /* Disable ADC peripheral */\r\n    __HAL_ADC_DISABLE(hadc);\r\n    \r\n    /* Check if ADC is effectively disabled */\r\n    if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))\r\n    {\r\n      /* Set ADC state */\r\n      ADC_STATE_CLR_SET(hadc->State,\r\n                        HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,\r\n                        HAL_ADC_STATE_READY);\r\n    }\r\n  }\r\n  else\r\n  {\r\n    /* Update ADC state machine to error */\r\n    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);\r\n      \r\n    tmp_hal_status = HAL_ERROR;\r\n  }\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hadc);\r\n  \r\n  /* Return function status */\r\n  return tmp_hal_status;\r\n}\r\n\r\n/**\r\n  * @brief  Poll for injected conversion complete\r\n  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @param  Timeout: Timeout value in millisecond.  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;\r\n\r\n  /* Get tick */ \r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Check End of conversion flag */\r\n  while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)))\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        hadc->State= HAL_ADC_STATE_TIMEOUT;\r\n        /* Process unlocked */\r\n        __HAL_UNLOCK(hadc);\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Clear injected group conversion flag */\r\n  __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC);\r\n    \r\n  /* Update ADC state machine */\r\n  SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);\r\n  \r\n  /* Determine whether any further conversion upcoming on group injected      */\r\n  /* by external trigger, continuous mode or scan sequence on going.          */\r\n  /* Note: On STM32F7, there is no independent flag of end of sequence.       */\r\n  /*       The test of scan sequence on going is done either with scan        */\r\n  /*       sequence disabled or with end of conversion flag set to            */\r\n  /*       of end of sequence.                                                */\r\n  if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                    &&\r\n     (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL)  ||\r\n      HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)    ) &&\r\n     (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&\r\n      (ADC_IS_SOFTWARE_START_REGULAR(hadc)       &&\r\n      (hadc->Init.ContinuousConvMode == DISABLE)   )       )   )\r\n  {\r\n    /* Set ADC state */\r\n    CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);\r\n    \r\n    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))\r\n    { \r\n      SET_BIT(hadc->State, HAL_ADC_STATE_READY);\r\n    }\r\n  }\r\n  \r\n  /* Return ADC state */\r\n  return HAL_OK;\r\n}      \r\n  \r\n/**\r\n  * @brief  Stop conversion of injected channels, disable interruption of \r\n  *         end-of-conversion. Disable ADC peripheral if no regular conversion\r\n  *         is on going.\r\n  * @note   If ADC must be disabled and if conversion is on going on \r\n  *         regular group, function HAL_ADC_Stop must be used to stop both\r\n  *         injected and regular groups, and disable the ADC.\r\n  * @note   If injected group mode auto-injection is enabled,\r\n  *         function HAL_ADC_Stop must be used.\r\n  * @param  hadc: ADC handle\r\n  * @retval None\r\n  */\r\nHAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)\r\n{\r\n  HAL_StatusTypeDef tmp_hal_status = HAL_OK;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hadc);\r\n    \r\n  /* Stop potential conversion and disable ADC peripheral                     */\r\n  /* Conditioned to:                                                          */\r\n  /* - No conversion on the other group (regular group) is intended to        */\r\n  /*   continue (injected and regular groups stop conversion and ADC disable  */\r\n  /*   are common)                                                            */\r\n  /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */ \r\n  if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET)  &&\r\n     HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )\r\n  {\r\n    /* Stop potential conversion on going, on regular and injected groups */\r\n    /* Disable ADC peripheral */\r\n    __HAL_ADC_DISABLE(hadc);\r\n    \r\n    /* Check if ADC is effectively disabled */\r\n    if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))\r\n    {\r\n      /* Disable ADC end of conversion interrupt for injected channels */\r\n      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);\r\n      \r\n      /* Set ADC state */\r\n      ADC_STATE_CLR_SET(hadc->State,\r\n                        HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,\r\n                        HAL_ADC_STATE_READY);\r\n    }\r\n  }\r\n  else\r\n  {\r\n    /* Update ADC state machine to error */\r\n    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);\r\n      \r\n    tmp_hal_status = HAL_ERROR;\r\n  }\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hadc);\r\n  \r\n  /* Return function status */\r\n  return tmp_hal_status;\r\n}\r\n\r\n/**\r\n  * @brief  Gets the converted value from data register of injected channel.\r\n  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @param  InjectedRank: the ADC injected rank.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg ADC_INJECTED_RANK_1: Injected Channel1 selected\r\n  *            @arg ADC_INJECTED_RANK_2: Injected Channel2 selected\r\n  *            @arg ADC_INJECTED_RANK_3: Injected Channel3 selected\r\n  *            @arg ADC_INJECTED_RANK_4: Injected Channel4 selected\r\n  * @retval None\r\n  */\r\nuint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)\r\n{\r\n  __IO uint32_t tmp = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_ADC_INJECTED_RANK(InjectedRank));\r\n  \r\n  /* Clear injected group conversion flag to have similar behaviour as        */\r\n  /* regular group: reading data register also clears end of conversion flag. */\r\n  __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);\r\n  \r\n  /* Return the selected ADC converted value */ \r\n  switch(InjectedRank)\r\n  {  \r\n    case ADC_INJECTED_RANK_4:\r\n    {\r\n      tmp =  hadc->Instance->JDR4;\r\n    }  \r\n    break;\r\n    case ADC_INJECTED_RANK_3: \r\n    {  \r\n      tmp =  hadc->Instance->JDR3;\r\n    }  \r\n    break;\r\n    case ADC_INJECTED_RANK_2: \r\n    {  \r\n      tmp =  hadc->Instance->JDR2;\r\n    }\r\n    break;\r\n    case ADC_INJECTED_RANK_1:\r\n    {\r\n      tmp =  hadc->Instance->JDR1;\r\n    }\r\n    break;\r\n    default:\r\n    break;  \r\n  }\r\n  return tmp;\r\n}\r\n\r\n/**\r\n  * @brief  Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral\r\n  * \r\n  * @note   Caution: This function must be used only with the ADC master.  \r\n  *\r\n  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @param  pData:   Pointer to buffer in which transferred from ADC peripheral to memory will be stored. \r\n  * @param  Length:  The length of data to be transferred from ADC peripheral to memory.  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)\r\n{\r\n  __IO uint32_t counter = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));\r\n  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));\r\n  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hadc);\r\n  \r\n  /* Check if ADC peripheral is disabled in order to enable it and wait during \r\n     Tstab time the ADC's stabilization */\r\n  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)\r\n  {  \r\n    /* Enable the Peripheral */\r\n    __HAL_ADC_ENABLE(hadc);\r\n    \r\n    /* Delay for temperature sensor stabilization time */\r\n    /* Compute number of CPU cycles to wait for */\r\n    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));\r\n    while(counter != 0)\r\n    {\r\n      counter--;\r\n    }\r\n  }\r\n  \r\n  /* Start conversion if ADC is effectively enabled */\r\n  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))\r\n  {\r\n    /* Set ADC state                                                          */\r\n    /* - Clear state bitfield related to regular group conversion results     */\r\n    /* - Set state bitfield related to regular group operation                */\r\n    ADC_STATE_CLR_SET(hadc->State,\r\n                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,\r\n                      HAL_ADC_STATE_REG_BUSY);\r\n    \r\n    /* If conversions on group regular are also triggering group injected,    */\r\n    /* update ADC state.                                                      */\r\n    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)\r\n    {\r\n      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  \r\n    }\r\n    \r\n    /* State machine update: Check if an injected conversion is ongoing */\r\n    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))\r\n    {\r\n      /* Reset ADC error code fields related to conversions on group regular */\r\n      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         \r\n    }\r\n    else\r\n    {\r\n      /* Reset ADC all error code fields */\r\n      ADC_CLEAR_ERRORCODE(hadc);\r\n    }\r\n    \r\n    /* Process unlocked */\r\n    /* Unlock before starting ADC conversions: in case of potential           */\r\n    /* interruption, to let the process to ADC IRQ Handler.                   */\r\n    __HAL_UNLOCK(hadc);\r\n    \r\n    /* Set the DMA transfer complete callback */\r\n    hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt;\r\n    \r\n    /* Set the DMA half transfer complete callback */\r\n    hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt;\r\n    \r\n    /* Set the DMA error callback */\r\n    hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ;\r\n    \r\n    /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */\r\n    /* start (in case of SW start):                                           */\r\n    \r\n    /* Clear regular group conversion flag and overrun flag */\r\n    /* (To ensure of no unknown state from potential previous ADC operations) */\r\n    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);\r\n\r\n    /* Enable ADC overrun interrupt */\r\n    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);\r\n    \r\n    if (hadc->Init.DMAContinuousRequests != DISABLE)\r\n    {\r\n      /* Enable the selected ADC DMA request after last transfer */\r\n      ADC->CCR |= ADC_CCR_DDS;\r\n    }\r\n    else\r\n    {\r\n      /* Disable the selected ADC EOC rising on each regular channel conversion */\r\n      ADC->CCR &= ~ADC_CCR_DDS;\r\n    }\r\n    \r\n    /* Enable the DMA Stream */\r\n    HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length);\r\n    \r\n    /* if no external trigger present enable software conversion of regular channels */\r\n    if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) \r\n    {\r\n      /* Enable the selected ADC software conversion for regular group */\r\n      hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Disables ADC DMA (multi-ADC mode) and disables ADC peripheral    \r\n  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)\r\n{\r\n  HAL_StatusTypeDef tmp_hal_status = HAL_OK;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hadc);\r\n  \r\n  /* Stop potential conversion on going, on regular and injected groups */\r\n  /* Disable ADC peripheral */\r\n  __HAL_ADC_DISABLE(hadc);\r\n  \r\n  /* Check if ADC is effectively disabled */\r\n  if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))\r\n  {\r\n    /* Disable the selected ADC DMA mode for multimode */\r\n    ADC->CCR &= ~ADC_CCR_DDS;\r\n    \r\n    /* Disable the DMA channel (in case of DMA in circular mode or stop while */\r\n    /* DMA transfer is on going)                                              */\r\n    tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);\r\n    \r\n    /* Disable ADC overrun interrupt */\r\n    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);\r\n    \r\n    /* Set ADC state */\r\n    ADC_STATE_CLR_SET(hadc->State,\r\n                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,\r\n                      HAL_ADC_STATE_READY);\r\n  }\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hadc);\r\n  \r\n  /* Return function status */\r\n  return tmp_hal_status;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the last ADC1, ADC2 and ADC3 regular conversions results \r\n  *         data in the selected multi mode.\r\n  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @retval The converted data value.\r\n  */\r\nuint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)\r\n{\r\n  /* Return the multi mode conversion value */\r\n  return ADC->CDR;\r\n}\r\n\r\n/**\r\n  * @brief  Injected conversion complete callback in non blocking mode \r\n  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hadc);\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_ADC_InjectedConvCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Configures for the selected ADC injected channel its corresponding\r\n  *         rank in the sequencer and its sample time.\r\n  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified ADC.\r\n  * @param  sConfigInjected: ADC configuration structure for injected channel. \r\n  * @retval None\r\n  */\r\nHAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)\r\n{\r\n  \r\n#ifdef USE_FULL_ASSERT  \r\n  uint32_t tmp = 0;\r\n#endif /* USE_FULL_ASSERT  */\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));\r\n  assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));\r\n  assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));\r\n  assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv));\r\n  assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion));\r\n  assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));\r\n  assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));\r\n\r\n#ifdef USE_FULL_ASSERT\r\n  tmp = ADC_GET_RESOLUTION(hadc);\r\n  assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset));\r\n#endif /* USE_FULL_ASSERT  */\r\n\r\n  if(sConfigInjected->ExternalTrigInjecConvEdge != ADC_INJECTED_SOFTWARE_START)\r\n  {\r\n    assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));\r\n  }\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hadc);\r\n  \r\n  /* if ADC_Channel_10 ... ADC_Channel_18 is selected */\r\n  if (sConfigInjected->InjectedChannel > ADC_CHANNEL_9)\r\n  {\r\n    /* Clear the old sample time */\r\n    hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel);\r\n    \r\n    /* Set the new sample time */\r\n    hadc->Instance->SMPR1 |= ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);\r\n  }\r\n  else /* ADC_Channel include in ADC_Channel_[0..9] */\r\n  {\r\n    /* Clear the old sample time */\r\n    hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel);\r\n    \r\n    /* Set the new sample time */\r\n    hadc->Instance->SMPR2 |= ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);\r\n  }\r\n  \r\n  /*---------------------------- ADCx JSQR Configuration -----------------*/\r\n  hadc->Instance->JSQR &= ~(ADC_JSQR_JL);\r\n  hadc->Instance->JSQR |=  ADC_SQR1(sConfigInjected->InjectedNbrOfConversion);\r\n  \r\n  /* Rank configuration */\r\n  \r\n  /* Clear the old SQx bits for the selected rank */\r\n  hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);\r\n   \r\n  /* Set the SQx bits for the selected rank */\r\n  hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);\r\n\r\n  /* Enable external trigger if trigger selection is different of software  */\r\n  /* start.                                                                 */\r\n  /* Note: This configuration keeps the hardware feature of parameter       */\r\n  /*       ExternalTrigConvEdge \"trigger edge none\" equivalent to           */\r\n  /*       software start.                                                  */ \r\n  if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)\r\n  {  \r\n    /* Select external trigger to start conversion */\r\n    hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);\r\n    hadc->Instance->CR2 |=  sConfigInjected->ExternalTrigInjecConv;\r\n    \r\n    /* Select external trigger polarity */\r\n    hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);\r\n    hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge;\r\n  }\r\n  else\r\n  {\r\n    /* Reset the external trigger */\r\n    hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);\r\n    hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);  \r\n  }\r\n  \r\n  if (sConfigInjected->AutoInjectedConv != DISABLE)\r\n  {\r\n    /* Enable the selected ADC automatic injected group conversion */\r\n    hadc->Instance->CR1 |= ADC_CR1_JAUTO;\r\n  }\r\n  else\r\n  {\r\n    /* Disable the selected ADC automatic injected group conversion */\r\n    hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO);\r\n  }\r\n  \r\n  if (sConfigInjected->InjectedDiscontinuousConvMode != DISABLE)\r\n  {\r\n    /* Enable the selected ADC injected discontinuous mode */\r\n    hadc->Instance->CR1 |= ADC_CR1_JDISCEN;\r\n  }\r\n  else\r\n  {\r\n    /* Disable the selected ADC injected discontinuous mode */\r\n    hadc->Instance->CR1 &= ~(ADC_CR1_JDISCEN);\r\n  }\r\n  \r\n  switch(sConfigInjected->InjectedRank)\r\n  {\r\n    case 1:\r\n      /* Set injected channel 1 offset */\r\n      hadc->Instance->JOFR1 &= ~(ADC_JOFR1_JOFFSET1);\r\n      hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset;\r\n      break;\r\n    case 2:\r\n      /* Set injected channel 2 offset */\r\n      hadc->Instance->JOFR2 &= ~(ADC_JOFR2_JOFFSET2);\r\n      hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset;\r\n      break;\r\n    case 3:\r\n      /* Set injected channel 3 offset */\r\n      hadc->Instance->JOFR3 &= ~(ADC_JOFR3_JOFFSET3);\r\n      hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset;\r\n      break;\r\n    default:\r\n      /* Set injected channel 4 offset */\r\n      hadc->Instance->JOFR4 &= ~(ADC_JOFR4_JOFFSET4);\r\n      hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset;\r\n      break;\r\n  }\r\n  \r\n  /* if ADC1 Channel_18 is selected enable VBAT Channel */\r\n  if ((hadc->Instance == ADC1) && (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT))\r\n  {\r\n    /* Enable the VBAT channel*/\r\n    ADC->CCR |= ADC_CCR_VBATE;\r\n  }\r\n  \r\n  /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */\r\n  if ((hadc->Instance == ADC1) && ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)))\r\n  {\r\n    /* Enable the TSVREFE channel*/\r\n    ADC->CCR |= ADC_CCR_TSVREFE;\r\n  }\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hadc);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Configures the ADC multi-mode \r\n  * @param  hadc      : pointer to a ADC_HandleTypeDef structure that contains\r\n  *                     the configuration information for the specified ADC.  \r\n  * @param  multimode : pointer to an ADC_MultiModeTypeDef structure that contains \r\n  *                     the configuration information for  multimode.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_ADC_MODE(multimode->Mode));\r\n  assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode));\r\n  assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hadc);\r\n  \r\n  /* Set ADC mode */\r\n  ADC->CCR &= ~(ADC_CCR_MULTI);\r\n  ADC->CCR |= multimode->Mode;\r\n  \r\n  /* Set the ADC DMA access mode */\r\n  ADC->CCR &= ~(ADC_CCR_DMA);\r\n  ADC->CCR |= multimode->DMAAccessMode;\r\n  \r\n  /* Set delay between two sampling phases */\r\n  ADC->CCR &= ~(ADC_CCR_DELAY);\r\n  ADC->CCR |= multimode->TwoSamplingDelay;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hadc);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n  /**\r\n  * @brief  DMA transfer complete callback. \r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma)   \r\n{\r\n  /* Retrieve ADC handle corresponding to current DMA handle */\r\n  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  \r\n  /* Update state machine on conversion status if not in error state */\r\n  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))\r\n  {\r\n    /* Update ADC state machine */\r\n    SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);\r\n    \r\n    /* Determine whether any further conversion upcoming on group regular   */\r\n    /* by external trigger, continuous mode or scan sequence on going.      */\r\n    /* Note: On STM32F7, there is no independent flag of end of sequence.   */\r\n    /*       The test of scan sequence on going is done either with scan    */\r\n    /*       sequence disabled or with end of conversion flag set to        */\r\n    /*       of end of sequence.                                            */\r\n    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&\r\n       (hadc->Init.ContinuousConvMode == DISABLE)            &&\r\n       (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || \r\n        HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )\r\n    {\r\n      /* Disable ADC end of single conversion interrupt on group regular */\r\n      /* Note: Overrun interrupt was enabled with EOC interrupt in          */\r\n      /* HAL_ADC_Start_IT(), but is not disabled here because can be used   */\r\n      /* by overrun IRQ process below.                                      */\r\n      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);\r\n      \r\n      /* Set ADC state */\r\n      CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);   \r\n      \r\n      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))\r\n      {\r\n        SET_BIT(hadc->State, HAL_ADC_STATE_READY);\r\n      }\r\n    }\r\n    \r\n    /* Conversion complete callback */\r\n    HAL_ADC_ConvCpltCallback(hadc);\r\n  }\r\n  else\r\n  {\r\n    /* Call DMA error callback */\r\n    hadc->DMA_Handle->XferErrorCallback(hdma);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  DMA half transfer complete callback. \r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma)   \r\n{\r\n    ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n    /* Conversion complete callback */\r\n    HAL_ADC_ConvHalfCpltCallback(hadc); \r\n}\r\n\r\n/**\r\n  * @brief  DMA error callback \r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma)   \r\n{\r\n    ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n    hadc->State= HAL_ADC_STATE_ERROR_DMA;\r\n    /* Set ADC error code to DMA error */\r\n    hadc->ErrorCode |= HAL_ADC_ERROR_DMA;\r\n    HAL_ADC_ErrorCallback(hadc); \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_ADC_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_can.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_can.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   CAN HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the Controller Area Network (CAN) peripheral:\r\n  *           + Initialization and de-initialization functions \r\n  *           + IO operation functions\r\n  *           + Peripheral Control functions\r\n  *           + Peripheral State and Error functions\r\n  *\r\n  @verbatim\r\n  ==============================================================================\r\n                        ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]            \r\n      (#) Enable the CAN controller interface clock using \r\n          __HAL_RCC_CAN1_CLK_ENABLE() for CAN1,  __HAL_RCC_CAN2_CLK_ENABLE() for CAN2\r\n         and  __HAL_RCC_CAN3_CLK_ENABLE() for CAN3\r\n      -@- In case you are using CAN2 only, you have to enable the CAN1 clock.\r\n       \r\n      (#) CAN pins configuration\r\n        (++) Enable the clock for the CAN GPIOs using the following function:\r\n             __HAL_RCC_GPIOx_CLK_ENABLE()   \r\n        (++) Connect and configure the involved CAN pins to AF9 using the \r\n              following function HAL_GPIO_Init() \r\n              \r\n      (#) Initialize and configure the CAN using HAL_CAN_Init() function.   \r\n                 \r\n      (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.\r\n\r\n      (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function.\r\n           \r\n      (#) Receive a CAN frame using HAL_CAN_Receive() function.\r\n\r\n      (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function.\r\n\r\n     *** Polling mode IO operation ***\r\n     =================================\r\n     [..]    \r\n       (+) Start the CAN peripheral transmission and wait the end of this operation \r\n           using HAL_CAN_Transmit(), at this stage user can specify the value of timeout\r\n           according to his end application\r\n       (+) Start the CAN peripheral reception and wait the end of this operation \r\n           using HAL_CAN_Receive(), at this stage user can specify the value of timeout\r\n           according to his end application \r\n       \r\n     *** Interrupt mode IO operation ***    \r\n     ===================================\r\n     [..]    \r\n       (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()\r\n       (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()         \r\n       (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine\r\n       (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can \r\n            add his own code by customization of function pointer HAL_CAN_TxCpltCallback \r\n       (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can \r\n            add his own code by customization of function pointer HAL_CAN_ErrorCallback\r\n \r\n     *** CAN HAL driver macros list ***\r\n     ============================================= \r\n     [..]\r\n       Below the list of most used macros in CAN HAL driver.\r\n       \r\n      (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts\r\n      (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts\r\n      (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled\r\n      (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags\r\n      (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status\r\n      \r\n     [..] \r\n      (@) You can refer to the CAN HAL driver header file for more useful macros \r\n                \r\n  @endverbatim\r\n           \r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CAN CAN\r\n  * @brief CAN driver modules\r\n  * @{\r\n  */ \r\n  \r\n#ifdef HAL_CAN_MODULE_ENABLED  \r\n\r\n  \r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @addtogroup CAN_Private_Constants\r\n  * @{\r\n  */\r\n#define CAN_TIMEOUT_VALUE  10\r\n/**\r\n  * @}\r\n  */\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/** @addtogroup CAN_Private_Functions\r\n  * @{\r\n  */\r\nstatic HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);\r\nstatic HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup CAN_Exported_Functions CAN Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions \r\n *  @brief    Initialization and Configuration functions \r\n *\r\n@verbatim    \r\n  ==============================================================================\r\n              ##### Initialization and de-initialization functions #####\r\n  ==============================================================================\r\n    [..]  This section provides functions allowing to:\r\n      (+) Initialize and configure the CAN. \r\n      (+) De-initialize the CAN. \r\n         \r\n@endverbatim\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @brief  Initializes the CAN peripheral according to the specified\r\n  *         parameters in the CAN_InitStruct.\r\n  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)\r\n{\r\n  uint32_t InitStatus = CAN_INITSTATUS_FAILED;\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Check CAN handle */\r\n  if(hcan == NULL)\r\n  {\r\n     return HAL_ERROR;\r\n  }\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));\r\n  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));\r\n  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));\r\n  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));\r\n  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));\r\n  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));\r\n  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));\r\n  assert_param(IS_CAN_MODE(hcan->Init.Mode));\r\n  assert_param(IS_CAN_SJW(hcan->Init.SJW));\r\n  assert_param(IS_CAN_BS1(hcan->Init.BS1));\r\n  assert_param(IS_CAN_BS2(hcan->Init.BS2));\r\n  assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));\r\n  \r\n\r\n  if(hcan->State == HAL_CAN_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    hcan->Lock = HAL_UNLOCKED;\r\n    /* Init the low level hardware */\r\n    HAL_CAN_MspInit(hcan);\r\n  }\r\n  \r\n  /* Initialize the CAN state*/\r\n  hcan->State = HAL_CAN_STATE_BUSY;\r\n  \r\n  /* Exit from sleep mode */\r\n  hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP);\r\n\r\n  /* Request initialisation */\r\n  hcan->Instance->MCR |= CAN_MCR_INRQ ;\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Wait the acknowledge */\r\n  while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)\r\n  {\r\n    if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)\r\n    {\r\n      hcan->State= HAL_CAN_STATE_TIMEOUT;\r\n      /* Process unlocked */\r\n      __HAL_UNLOCK(hcan);\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n\r\n  /* Check acknowledge */\r\n  if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)\r\n  {\r\n    /* Set the time triggered communication mode */\r\n    if (hcan->Init.TTCM == ENABLE)\r\n    {\r\n      hcan->Instance->MCR |= CAN_MCR_TTCM;\r\n    }\r\n    else\r\n    {\r\n      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM;\r\n    }\r\n\r\n    /* Set the automatic bus-off management */\r\n    if (hcan->Init.ABOM == ENABLE)\r\n    {\r\n      hcan->Instance->MCR |= CAN_MCR_ABOM;\r\n    }\r\n    else\r\n    {\r\n      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM;\r\n    }\r\n\r\n    /* Set the automatic wake-up mode */\r\n    if (hcan->Init.AWUM == ENABLE)\r\n    {\r\n      hcan->Instance->MCR |= CAN_MCR_AWUM;\r\n    }\r\n    else\r\n    {\r\n      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM;\r\n    }\r\n\r\n    /* Set the no automatic retransmission */\r\n    if (hcan->Init.NART == ENABLE)\r\n    {\r\n      hcan->Instance->MCR |= CAN_MCR_NART;\r\n    }\r\n    else\r\n    {\r\n      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART;\r\n    }\r\n\r\n    /* Set the receive FIFO locked mode */\r\n    if (hcan->Init.RFLM == ENABLE)\r\n    {\r\n      hcan->Instance->MCR |= CAN_MCR_RFLM;\r\n    }\r\n    else\r\n    {\r\n      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM;\r\n    }\r\n\r\n    /* Set the transmit FIFO priority */\r\n    if (hcan->Init.TXFP == ENABLE)\r\n    {\r\n      hcan->Instance->MCR |= CAN_MCR_TXFP;\r\n    }\r\n    else\r\n    {\r\n      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP;\r\n    }\r\n\r\n    /* Set the bit timing register */\r\n    hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \\\r\n                ((uint32_t)hcan->Init.SJW) | \\\r\n                ((uint32_t)hcan->Init.BS1) | \\\r\n                ((uint32_t)hcan->Init.BS2) | \\\r\n                ((uint32_t)hcan->Init.Prescaler - 1);\r\n\r\n    /* Request leave initialisation */\r\n    hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ;\r\n\r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n    /* Wait the acknowledge */\r\n    while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)\r\n      {\r\n        hcan->State= HAL_CAN_STATE_TIMEOUT;\r\n        /* Process unlocked */\r\n        __HAL_UNLOCK(hcan);\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n\r\n    /* Check acknowledged */\r\n    if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)\r\n    {\r\n      InitStatus = CAN_INITSTATUS_SUCCESS;\r\n    }\r\n  }\r\n \r\n  if(InitStatus == CAN_INITSTATUS_SUCCESS)\r\n  {\r\n    /* Set CAN error code to none */\r\n    hcan->ErrorCode = HAL_CAN_ERROR_NONE;\r\n    \r\n    /* Initialize the CAN state */\r\n    hcan->State = HAL_CAN_STATE_READY;\r\n  \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    /* Initialize the CAN state */\r\n    hcan->State = HAL_CAN_STATE_ERROR;\r\n    \r\n    /* Return function status */\r\n    return HAL_ERROR;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Configures the CAN reception filter according to the specified\r\n  *         parameters in the CAN_FilterInitStruct.\r\n  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @param  sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that\r\n  *         contains the filter configuration information.\r\n  * @retval None\r\n  */\r\nHAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)\r\n{\r\n  uint32_t filternbrbitpos = 0;\r\n  CAN_TypeDef *can_ip;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));\r\n  assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));\r\n  assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));\r\n  assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));\r\n  assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));\r\n  assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));\r\n  \r\n  filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber;\r\n#if defined (CAN3)\r\n  /* Check the CAN instance */\r\n  if(hcan->Instance == CAN3)\r\n  {\t\r\n    can_ip = CAN3;\r\n  }\r\n  else\r\n  {\r\n    can_ip = CAN1;    \r\n  }\r\n#else\r\n  can_ip = CAN1;\r\n#endif\r\n\r\n  /* Initialisation mode for the filter */\r\n  can_ip->FMR |= (uint32_t)CAN_FMR_FINIT;\r\n  \r\n  /* Select the start slave bank */\r\n  can_ip->FMR &= ~((uint32_t)CAN_FMR_CAN2SB);\r\n  can_ip->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8);\r\n     \r\n  /* Filter Deactivation */\r\n  can_ip->FA1R &= ~(uint32_t)filternbrbitpos;\r\n\r\n  /* Filter Scale */\r\n  if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)\r\n  {\r\n    /* 16-bit scale for the filter */\r\n    can_ip->FS1R &= ~(uint32_t)filternbrbitpos;\r\n\r\n    /* First 16-bit identifier and First 16-bit mask */\r\n    /* Or First 16-bit identifier and Second 16-bit identifier */\r\n    can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 = \r\n     ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) |\r\n      (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);\r\n\r\n    /* Second 16-bit identifier and Second 16-bit mask */\r\n    /* Or Third 16-bit identifier and Fourth 16-bit identifier */\r\n    can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 = \r\n     ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |\r\n      (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh);\r\n  }\r\n\r\n  if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)\r\n  {\r\n    /* 32-bit scale for the filter */\r\n    can_ip->FS1R |= filternbrbitpos;\r\n    \r\n    /* 32-bit identifier or First 32-bit identifier */\r\n    can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 = \r\n     ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) |\r\n      (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);\r\n    \r\n    /* 32-bit mask or Second 32-bit identifier */\r\n    can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 = \r\n     ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |\r\n      (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow);\r\n  }\r\n\r\n  /* Filter Mode */\r\n  if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)\r\n  {\r\n    /*Id/Mask mode for the filter*/\r\n    can_ip->FM1R &= ~(uint32_t)filternbrbitpos;\r\n  }\r\n  else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */\r\n  {\r\n    /*Identifier list mode for the filter*/\r\n    can_ip->FM1R |= (uint32_t)filternbrbitpos;\r\n  }\r\n\r\n  /* Filter FIFO assignment */\r\n  if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)\r\n  {\r\n    /* FIFO 0 assignation for the filter */\r\n    can_ip->FFA1R &= ~(uint32_t)filternbrbitpos;\r\n  }\r\n\r\n  if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1)\r\n  {\r\n    /* FIFO 1 assignation for the filter */\r\n    can_ip->FFA1R |= (uint32_t)filternbrbitpos;\r\n  }\r\n  \r\n  /* Filter activation */\r\n  if (sFilterConfig->FilterActivation == ENABLE)\r\n  {\r\n    can_ip->FA1R |= filternbrbitpos;\r\n  }\r\n\r\n  /* Leave the initialisation mode for the filter */\r\n  can_ip->FMR &= ~((uint32_t)CAN_FMR_FINIT);\r\n   \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Deinitializes the CANx peripheral registers to their default reset values. \r\n  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)\r\n{\r\n  /* Check CAN handle */\r\n  if(hcan == NULL)\r\n  {\r\n     return HAL_ERROR;\r\n  }\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));\r\n  \r\n  /* Change CAN state */\r\n  hcan->State = HAL_CAN_STATE_BUSY;\r\n  \r\n  /* DeInit the low level hardware */\r\n  HAL_CAN_MspDeInit(hcan);\r\n  \r\n  /* Change CAN state */\r\n  hcan->State = HAL_CAN_STATE_RESET;\r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hcan);\r\n\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CAN MSP.\r\n  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.  \r\n  * @retval None\r\n  */\r\n__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcan);\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_CAN_MspInit could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the CAN MSP.\r\n  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.  \r\n  * @retval None\r\n  */\r\n__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcan);\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_CAN_MspDeInit could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CAN_Exported_Functions_Group2 IO operation functions\r\n *  @brief    IO operation functions \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                      ##### IO operation functions #####\r\n  ==============================================================================\r\n    [..]  This section provides functions allowing to:\r\n      (+) Transmit a CAN frame message.\r\n      (+) Receive a CAN frame message.\r\n      (+) Enter CAN peripheral in sleep mode. \r\n      (+) Wake up the CAN peripheral from sleep mode.\r\n               \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initiates and transmits a CAN frame message.\r\n  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.  \r\n  * @param  Timeout: Specify Timeout value   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)\r\n{\r\n  uint32_t  transmitmailbox = CAN_TXSTATUS_NOMAILBOX;\r\n  uint32_t tickstart = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));\r\n  assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));\r\n  assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));\r\n\r\n  if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \\\r\n     ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \\\r\n     ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))\r\n  {  \r\n    /* Process locked */\r\n    __HAL_LOCK(hcan);\r\n  \r\n    if(hcan->State == HAL_CAN_STATE_BUSY_RX) \r\n    {\r\n      /* Change CAN state */\r\n      hcan->State = HAL_CAN_STATE_BUSY_TX_RX;\r\n    }\r\n    else\r\n    {\r\n      /* Change CAN state */\r\n      hcan->State = HAL_CAN_STATE_BUSY_TX;\r\n    }\r\n  \r\n    /* Select one empty transmit mailbox */\r\n    if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)\r\n    {\r\n      transmitmailbox = CAN_TXMAILBOX_0;\r\n    }\r\n    else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)\r\n    {\r\n      transmitmailbox = CAN_TXMAILBOX_1;\r\n    }\r\n    else\r\n    {\r\n      transmitmailbox = CAN_TXMAILBOX_2;\r\n    }\r\n\t\r\n    /* Set up the Id */\r\n    hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;\r\n    if (hcan->pTxMsg->IDE == CAN_ID_STD)\r\n    {\r\n      assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));  \r\n      hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \\\r\n                                                  hcan->pTxMsg->RTR);\r\n    }\r\n    else\r\n    {\r\n      assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));\r\n      hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \\\r\n                                                  hcan->pTxMsg->IDE | \\\r\n                                                  hcan->pTxMsg->RTR);\r\n    }\r\n    \r\n    /* Set up the DLC */\r\n    hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;\r\n    hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;\r\n    hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;\r\n\r\n    /* Set up the data field */\r\n    hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | \r\n                                             ((uint32_t)hcan->pTxMsg->Data[2] << 16) |\r\n                                             ((uint32_t)hcan->pTxMsg->Data[1] << 8) | \r\n                                             ((uint32_t)hcan->pTxMsg->Data[0]));\r\n    hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | \r\n                                             ((uint32_t)hcan->pTxMsg->Data[6] << 16) |\r\n                                             ((uint32_t)hcan->pTxMsg->Data[5] << 8) |\r\n                                             ((uint32_t)hcan->pTxMsg->Data[4]));\r\n    /* Request transmission */\r\n    hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;\r\n  \r\n    /* Get tick */ \r\n    tickstart = HAL_GetTick();\r\n  \r\n    /* Check End of transmission flag */\r\n    while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))\r\n    {\r\n      /* Check for the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n       {\r\n         hcan->State = HAL_CAN_STATE_TIMEOUT;\r\n         /* Process unlocked */\r\n         __HAL_UNLOCK(hcan);\r\n         return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n    if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) \r\n    {\r\n      /* Change CAN state */\r\n      hcan->State = HAL_CAN_STATE_BUSY_RX;\r\n    }\r\n    else\r\n    {\r\n      /* Change CAN state */\r\n      hcan->State = HAL_CAN_STATE_READY;\r\n    }\r\n    \r\n    /* Process unlocked */\r\n    __HAL_UNLOCK(hcan);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    /* Change CAN state */\r\n    hcan->State = HAL_CAN_STATE_ERROR; \r\n\r\n    /* Return function status */\r\n    return HAL_ERROR;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Initiates and transmits a CAN frame message.\r\n  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)\r\n{\r\n  uint32_t  transmitmailbox = CAN_TXSTATUS_NOMAILBOX;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));\r\n  assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));\r\n  assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));\r\n  \r\n  if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \\\r\n     ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \\\r\n     ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcan);\r\n    \r\n    /* Select one empty transmit mailbox */\r\n    if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)\r\n    {\r\n      transmitmailbox = CAN_TXMAILBOX_0;\r\n    }\r\n    else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)\r\n    {\r\n      transmitmailbox = CAN_TXMAILBOX_1;\r\n    }\r\n    else\r\n    {\r\n      transmitmailbox = CAN_TXMAILBOX_2;\r\n    }\r\n\t\r\n    /* Set up the Id */\r\n    hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;\r\n    if(hcan->pTxMsg->IDE == CAN_ID_STD)\r\n    {\r\n      assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));  \r\n      hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \\\r\n                                                hcan->pTxMsg->RTR);\r\n    }\r\n    else\r\n    {\r\n      assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));\r\n      hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \\\r\n                                                hcan->pTxMsg->IDE | \\\r\n                                                hcan->pTxMsg->RTR);\r\n    }\r\n    \r\n    /* Set up the DLC */\r\n    hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;\r\n    hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;\r\n    hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;\r\n\r\n    /* Set up the data field */\r\n    hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | \r\n                                           ((uint32_t)hcan->pTxMsg->Data[2] << 16) |\r\n                                           ((uint32_t)hcan->pTxMsg->Data[1] << 8) | \r\n                                           ((uint32_t)hcan->pTxMsg->Data[0]));\r\n    hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | \r\n                                           ((uint32_t)hcan->pTxMsg->Data[6] << 16) |\r\n                                           ((uint32_t)hcan->pTxMsg->Data[5] << 8) |\r\n                                           ((uint32_t)hcan->pTxMsg->Data[4]));\r\n    \r\n    if(hcan->State == HAL_CAN_STATE_BUSY_RX) \r\n    {\r\n      /* Change CAN state */\r\n      hcan->State = HAL_CAN_STATE_BUSY_TX_RX;\r\n    }\r\n    else\r\n    {\r\n      /* Change CAN state */\r\n      hcan->State = HAL_CAN_STATE_BUSY_TX;\r\n    }\r\n      \r\n    /* Set CAN error code to none */\r\n    hcan->ErrorCode = HAL_CAN_ERROR_NONE;\r\n      \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hcan);\r\n\t\r\n    /* Enable Error warning, Error passive, Bus-off,\r\n       Last error and Error Interrupts */\t\r\n    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |\r\n                              CAN_IT_EPV |\r\n                              CAN_IT_BOF |\r\n                              CAN_IT_LEC |\r\n                              CAN_IT_ERR |\r\n\t\t\t\t\t\t\t  CAN_IT_TME);\r\n      \r\n    /* Request transmission */\r\n    hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;\r\n  }\r\n  else\r\n  {\r\n    /* Change CAN state */\r\n    hcan->State = HAL_CAN_STATE_ERROR; \r\n\r\n    /* Return function status */\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Receives a correct CAN frame.\r\n  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.  \r\n  * @param  FIFONumber: FIFO Number value\r\n  * @param  Timeout: Specify Timeout value \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;\r\n   \r\n  /* Check the parameters */\r\n  assert_param(IS_CAN_FIFO(FIFONumber));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hcan);\r\n  \r\n  if(hcan->State == HAL_CAN_STATE_BUSY_TX) \r\n  {\r\n    /* Change CAN state */\r\n    hcan->State = HAL_CAN_STATE_BUSY_TX_RX;\r\n  }\r\n  else\r\n  {\r\n    /* Change CAN state */\r\n    hcan->State = HAL_CAN_STATE_BUSY_RX;\r\n  }\r\n    \r\n  /* Get tick */ \r\n  tickstart = HAL_GetTick();\r\n  \r\n  /* Check pending message */\r\n  while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0)\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        hcan->State = HAL_CAN_STATE_TIMEOUT;\r\n        /* Process unlocked */\r\n        __HAL_UNLOCK(hcan);\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Get the Id */\r\n  hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;\r\n  if (hcan->pRxMsg->IDE == CAN_ID_STD)\r\n  {\r\n    hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);\r\n  }\r\n  else\r\n  {\r\n    hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);\r\n  }\r\n  \r\n  hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;\r\n  /* Get the DLC */\r\n  hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;\r\n  /* Get the FMI */\r\n  hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);\r\n  /* Get the data field */\r\n  hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;\r\n  hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);\r\n  hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);\r\n  hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);\r\n  hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;\r\n  hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);\r\n  hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);\r\n  hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);\r\n  \r\n  /* Release the FIFO */\r\n  if(FIFONumber == CAN_FIFO0)\r\n  {\r\n    /* Release FIFO0 */\r\n    __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);\r\n  }\r\n  else /* FIFONumber == CAN_FIFO1 */\r\n  {\r\n    /* Release FIFO1 */\r\n    __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);\r\n  }\r\n  \r\n  if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) \r\n  {\r\n    /* Change CAN state */\r\n    hcan->State = HAL_CAN_STATE_BUSY_TX;\r\n  }\r\n  else\r\n  {\r\n    /* Change CAN state */\r\n    hcan->State = HAL_CAN_STATE_READY;\r\n  }\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hcan);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Receives a correct CAN frame.\r\n  * @param  hcan:       Pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.  \r\n  * @param  FIFONumber: Specify the FIFO number    \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)\r\n{\r\n  uint32_t tmp = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_CAN_FIFO(FIFONumber));\r\n  \r\n  tmp = hcan->State;\r\n  if((tmp == HAL_CAN_STATE_READY) || (tmp == HAL_CAN_STATE_BUSY_TX))\r\n  {\r\n    /* Process locked */\r\n    __HAL_LOCK(hcan);\r\n  \r\n    if(hcan->State == HAL_CAN_STATE_BUSY_TX) \r\n    {\r\n      /* Change CAN state */\r\n      hcan->State = HAL_CAN_STATE_BUSY_TX_RX;\r\n    }\r\n    else\r\n    {\r\n      /* Change CAN state */\r\n      hcan->State = HAL_CAN_STATE_BUSY_RX;\r\n    }\r\n    \r\n    /* Set CAN error code to none */\r\n    hcan->ErrorCode = HAL_CAN_ERROR_NONE;\r\n\r\n    /* Enable Error warning, Error passive, Bus-off,\r\n       Last error and Error Interrupts */\t\r\n    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |\r\n                              CAN_IT_EPV |\r\n                              CAN_IT_BOF |\r\n                              CAN_IT_LEC |\r\n                              CAN_IT_ERR);\r\n\r\n    /* Process unlocked */\r\n    __HAL_UNLOCK(hcan);\r\n\r\n    if(FIFONumber == CAN_FIFO0)\r\n    {\r\n      /* Enable FIFO 0 message pending Interrupt */\r\n      __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0);\r\n    }\r\n    else\r\n    {\r\n      /* Enable FIFO 1 message pending Interrupt */\r\n      __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1);\r\n    }\r\n    \r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Enters the Sleep (low power) mode.\r\n  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @retval HAL status.\r\n  */\r\nHAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)\r\n{\r\n  uint32_t tickstart = 0;\r\n   \r\n  /* Process locked */\r\n  __HAL_LOCK(hcan);\r\n  \r\n  /* Change CAN state */\r\n  hcan->State = HAL_CAN_STATE_BUSY; \r\n    \r\n  /* Request Sleep mode */\r\n   hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);\r\n   \r\n  /* Sleep mode status */\r\n  if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)\r\n  {\r\n    /* Process unlocked */\r\n    __HAL_UNLOCK(hcan);\r\n\r\n    /* Return function status */\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Get tick */ \r\n  tickstart = HAL_GetTick();\r\n  \r\n  /* Wait the acknowledge */\r\n  while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)\r\n  {\r\n    if((HAL_GetTick()  - tickstart) > CAN_TIMEOUT_VALUE)\r\n    {\r\n      hcan->State = HAL_CAN_STATE_TIMEOUT;\r\n      /* Process unlocked */\r\n      __HAL_UNLOCK(hcan);\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  \r\n  /* Change CAN state */\r\n  hcan->State = HAL_CAN_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hcan);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral\r\n  *         is in the normal mode.\r\n  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @retval HAL status.\r\n  */\r\nHAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)\r\n{\r\n  uint32_t tickstart = 0;\r\n    \r\n  /* Process locked */\r\n  __HAL_LOCK(hcan);\r\n  \r\n  /* Change CAN state */\r\n  hcan->State = HAL_CAN_STATE_BUSY;  \r\n \r\n  /* Wake up request */\r\n  hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP;\r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Sleep mode status */\r\n  while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)\r\n  {\r\n    if((HAL_GetTick()  - tickstart) > CAN_TIMEOUT_VALUE)\r\n    {\r\n      hcan->State= HAL_CAN_STATE_TIMEOUT;\r\n      /* Process unlocked */\r\n      __HAL_UNLOCK(hcan);\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)\r\n  {\r\n    /* Process unlocked */\r\n    __HAL_UNLOCK(hcan);\r\n\r\n    /* Return function status */\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Change CAN state */\r\n  hcan->State = HAL_CAN_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hcan);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Handles CAN interrupt request  \r\n  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @retval None\r\n  */\r\nvoid HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)\r\n{\r\n  uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0;\r\n  \r\n  /* Check End of transmission flag */\r\n  if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))\r\n  {\r\n    tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0);\r\n    tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1);\r\n    tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2);\r\n    if(tmp1 || tmp2 || tmp3)  \r\n    {\r\n      /* Call transmit function */\r\n      CAN_Transmit_IT(hcan);\r\n    }\r\n  }\r\n  \r\n  tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0);\r\n  tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0);\r\n  /* Check End of reception flag for FIFO0 */\r\n  if((tmp1 != 0) && tmp2)\r\n  {\r\n    /* Call receive function */\r\n    CAN_Receive_IT(hcan, CAN_FIFO0);\r\n  }\r\n  \r\n  tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1);\r\n  tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1);\r\n  /* Check End of reception flag for FIFO1 */\r\n  if((tmp1 != 0) && tmp2)\r\n  {\r\n    /* Call receive function */\r\n    CAN_Receive_IT(hcan, CAN_FIFO1);\r\n  }\r\n  \r\n  tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG);\r\n  tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG);\r\n  tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);\r\n  /* Check Error Warning Flag */\r\n  if(tmp1 && tmp2 && tmp3)\r\n  {\r\n    /* Set CAN error code to EWG error */\r\n    hcan->ErrorCode |= HAL_CAN_ERROR_EWG;\r\n  }\r\n  \r\n  tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV);\r\n  tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV);\r\n  tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); \r\n  /* Check Error Passive Flag */\r\n  if(tmp1 && tmp2 && tmp3)\r\n  {\r\n    /* Set CAN error code to EPV error */\r\n    hcan->ErrorCode |= HAL_CAN_ERROR_EPV;\r\n  }\r\n  \r\n  tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF);\r\n  tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF);\r\n  tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);  \r\n  /* Check Bus-Off Flag */\r\n  if(tmp1 && tmp2 && tmp3)\r\n  {\r\n    /* Set CAN error code to BOF error */\r\n    hcan->ErrorCode |= HAL_CAN_ERROR_BOF;\r\n  }\r\n  \r\n  tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC);\r\n  tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC);\r\n  tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);\r\n  /* Check Last error code Flag */\r\n  if((!tmp1) && tmp2 && tmp3)\r\n  {\r\n    tmp1 = (hcan->Instance->ESR) & CAN_ESR_LEC;\r\n    switch(tmp1)\r\n    {\r\n      case(CAN_ESR_LEC_0):\r\n          /* Set CAN error code to STF error */\r\n          hcan->ErrorCode |= HAL_CAN_ERROR_STF;\r\n          break;\r\n      case(CAN_ESR_LEC_1):\r\n          /* Set CAN error code to FOR error */\r\n          hcan->ErrorCode |= HAL_CAN_ERROR_FOR;\r\n          break;\r\n      case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):\r\n          /* Set CAN error code to ACK error */\r\n          hcan->ErrorCode |= HAL_CAN_ERROR_ACK;\r\n          break;\r\n      case(CAN_ESR_LEC_2):\r\n          /* Set CAN error code to BR error */\r\n          hcan->ErrorCode |= HAL_CAN_ERROR_BR;\r\n          break;\r\n      case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):\r\n          /* Set CAN error code to BD error */\r\n          hcan->ErrorCode |= HAL_CAN_ERROR_BD;\r\n          break;\r\n      case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):\r\n          /* Set CAN error code to CRC error */\r\n          hcan->ErrorCode |= HAL_CAN_ERROR_CRC;\r\n          break;\r\n      default:\r\n          break;\r\n    }\r\n\r\n    /* Clear Last error code Flag */ \r\n    hcan->Instance->ESR &= ~(CAN_ESR_LEC);\r\n  }\r\n\r\n  /* Call the Error call Back in case of Errors */\r\n  if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)\r\n  {\r\n    /* Clear ERRI Flag */ \r\n    hcan->Instance->MSR = CAN_MSR_ERRI; \r\n    /* Set the CAN state ready to be able to start again the process */\r\n    hcan->State = HAL_CAN_STATE_READY;\r\n    /* Call Error callback function */\r\n    HAL_CAN_ErrorCallback(hcan);\r\n  }  \r\n}\r\n\r\n/**\r\n  * @brief  Transmission  complete callback in non blocking mode \r\n  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @retval None\r\n  */\r\n__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcan);\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_CAN_TxCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Transmission  complete callback in non blocking mode \r\n  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @retval None\r\n  */\r\n__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcan);\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_CAN_RxCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Error CAN callback.\r\n  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @retval None\r\n  */\r\n__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcan);\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_CAN_ErrorCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions\r\n *  @brief   CAN Peripheral State functions \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n            ##### Peripheral State and Error functions #####\r\n  ==============================================================================\r\n    [..]\r\n    This subsection provides functions allowing to :\r\n      (+) Check the CAN state.\r\n      (+) Check CAN Errors detected during interrupt process\r\n         \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  return the CAN state\r\n  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @retval HAL state\r\n  */\r\nHAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)\r\n{\r\n  /* Return CAN state */\r\n  return hcan->State;\r\n}\r\n\r\n/**\r\n  * @brief  Return the CAN error code\r\n  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.\r\n  * @retval CAN Error Code\r\n  */\r\nuint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)\r\n{\r\n  return hcan->ErrorCode;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n/**\r\n  * @brief  Initiates and transmits a CAN frame message.\r\n  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.  \r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)\r\n{\r\n  /* Disable Transmit mailbox empty Interrupt */\r\n  __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);\r\n  \r\n  if(hcan->State == HAL_CAN_STATE_BUSY_TX)\r\n  {   \r\n    /* Disable Error warning, Error passive, Bus-off, Last error code\r\n       and Error Interrupts */\t\r\n\t__HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |\r\n                               CAN_IT_EPV |\r\n                               CAN_IT_BOF |\r\n                               CAN_IT_LEC |\r\n                               CAN_IT_ERR );\r\n  }\r\n  \r\n  if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) \r\n  {\r\n    /* Change CAN state */\r\n    hcan->State = HAL_CAN_STATE_BUSY_RX;\r\n  }\r\n  else\r\n  {\r\n    /* Change CAN state */\r\n    hcan->State = HAL_CAN_STATE_READY;\r\n  }\r\n  \r\n  /* Transmission complete callback */ \r\n  HAL_CAN_TxCpltCallback(hcan);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Receives a correct CAN frame.\r\n  * @param  hcan:       Pointer to a CAN_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified CAN.  \r\n  * @param  FIFONumber: Specify the FIFO number    \r\n  * @retval HAL status\r\n  * @retval None\r\n  */\r\nstatic HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)\r\n{\r\n  /* Get the Id */\r\n  hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;\r\n  if (hcan->pRxMsg->IDE == CAN_ID_STD)\r\n  {\r\n    hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);\r\n  }\r\n  else\r\n  {\r\n    hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);\r\n  }\r\n  \r\n  hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;\r\n  /* Get the DLC */\r\n  hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;\r\n  /* Get the FMI */\r\n  hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);\r\n  /* Get the data field */\r\n  hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;\r\n  hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);\r\n  hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);\r\n  hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);\r\n  hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;\r\n  hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);\r\n  hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);\r\n  hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);\r\n  /* Release the FIFO */\r\n  /* Release FIFO0 */\r\n  if (FIFONumber == CAN_FIFO0)\r\n  {\r\n    __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);\r\n    \r\n    /* Disable FIFO 0 message pending Interrupt */\r\n    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0);\r\n  }\r\n  /* Release FIFO1 */\r\n  else /* FIFONumber == CAN_FIFO1 */\r\n  {\r\n    __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);\r\n    \r\n    /* Disable FIFO 1 message pending Interrupt */\r\n    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1);\r\n  }\r\n  \r\n  if(hcan->State == HAL_CAN_STATE_BUSY_RX)\r\n  {   \r\n    /* Disable Error warning, Error passive, Bus-off, Last error code\r\n       and Error Interrupts */\r\n\t__HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |\r\n                               CAN_IT_EPV |\r\n                               CAN_IT_BOF |\r\n                               CAN_IT_LEC |\r\n                               CAN_IT_ERR);\r\n  }\r\n  \r\n  if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) \r\n  {\r\n    /* Disable CAN state */\r\n    hcan->State = HAL_CAN_STATE_BUSY_TX;\r\n  }\r\n  else\r\n  {\r\n    /* Change CAN state */\r\n    hcan->State = HAL_CAN_STATE_READY;\r\n  }\r\n\r\n  /* Receive complete callback */ \r\n  HAL_CAN_RxCpltCallback(hcan);\r\n\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n * @}\r\n */\r\n\r\n#endif /* HAL_CAN_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cec.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_cec.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   CEC HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the High Definition Multimedia Interface \r\n  *          Consumer Electronics Control Peripheral (CEC).\r\n  *           + Initialization and de-initialization function\r\n  *           + IO operation function\r\n  *           + Peripheral Control function\r\n  *\r\n  *           \r\n  @verbatim       \r\n ===============================================================================\r\n                        ##### How to use this driver #####\r\n ===============================================================================\r\n    [..]\r\n    The CEC HAL driver can be used as follow:\r\n    \r\n    (#) Declare a CEC_HandleTypeDef handle structure.\r\n    (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:\r\n        (##) Enable the CEC interface clock.\r\n        (##) CEC pins configuration:\r\n            (+++) Enable the clock for the CEC GPIOs.\r\n            (+++) Configure these CEC pins as alternate function pull-up.\r\n        (##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()\r\n             and HAL_CEC_Receive_IT() APIs):\r\n            (+++) Configure the CEC interrupt priority.\r\n            (+++) Enable the NVIC CEC IRQ handle.\r\n            (+++) The specific CEC interrupts (Transmission complete interrupt, \r\n                  RXNE interrupt and Error Interrupts) will be managed using the macros\r\n                  __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit \r\n                  and receive process.\r\n\r\n    (#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in\r\n        in case of Bit Rising Error, Error-Bit generation conditions, device logical\r\n        address and Listen mode in the hcec Init structure.\r\n\r\n    (#) Initialize the CEC registers by calling the HAL_CEC_Init() API.\r\n\r\n  [..]        \r\n    (@) This API (HAL_CEC_Init()) configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)\r\n        by calling the customed HAL_CEC_MspInit() API.\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************  \r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CEC CEC \r\n  * @brief HAL CEC module driver\r\n  * @{\r\n  */\r\n#ifdef HAL_CEC_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @defgroup CEC_Private_Constants CEC Private Constants\r\n  * @{\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n \r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/** @defgroup CEC_Private_Functions CEC Private Functions\r\n  * @{\r\n  */\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Exported functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup CEC_Exported_Functions CEC Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions\r\n  *  @brief    Initialization and Configuration functions \r\n  *\r\n@verbatim                                                \r\n===============================================================================\r\n            ##### Initialization and Configuration functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides a set of functions allowing to initialize the CEC\r\n      (+) The following parameters need to be configured: \r\n        (++) SignalFreeTime\r\n        (++) Tolerance \r\n        (++) BRERxStop                 (RX stopped or not upon Bit Rising Error)\r\n        (++) BREErrorBitGen            (Error-Bit generation in case of Bit Rising Error)\r\n        (++) LBPEErrorBitGen           (Error-Bit generation in case of Long Bit Period Error)\r\n        (++) BroadcastMsgNoErrorBitGen (Error-bit generation in case of broadcast message error)\r\n        (++) SignalFreeTimeOption      (SFT Timer start definition)\r\n        (++) OwnAddress                (CEC device address)\r\n        (++) ListenMode\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief Initializes the CEC mode according to the specified\r\n  *         parameters in the CEC_InitTypeDef and creates the associated handle .\r\n  * @param hcec: CEC handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)\r\n{  \r\n  /* Check the CEC handle allocation */\r\n  if((hcec == NULL) ||(hcec->Init.RxBuffer == NULL))\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */ \r\n  assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));\r\n  assert_param(IS_CEC_SIGNALFREETIME(hcec->Init.SignalFreeTime));\r\n  assert_param(IS_CEC_TOLERANCE(hcec->Init.Tolerance));  \r\n  assert_param(IS_CEC_BRERXSTOP(hcec->Init.BRERxStop));\r\n  assert_param(IS_CEC_BREERRORBITGEN(hcec->Init.BREErrorBitGen));\r\n  assert_param(IS_CEC_LBPEERRORBITGEN(hcec->Init.LBPEErrorBitGen));\r\n  assert_param(IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(hcec->Init.BroadcastMsgNoErrorBitGen));\r\n  assert_param(IS_CEC_SFTOP(hcec->Init.SignalFreeTimeOption)); \r\n  assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode));\r\n  assert_param(IS_CEC_OWN_ADDRESS(hcec->Init.OwnAddress));  \r\n\r\n  if(hcec->gState == HAL_CEC_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    hcec->Lock = HAL_UNLOCKED;   \r\n    /* Init the low level hardware : GPIO, CLOCK */\r\n    HAL_CEC_MspInit(hcec);\r\n  }\r\n  hcec->gState = HAL_CEC_STATE_BUSY;\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_CEC_DISABLE(hcec);\r\n  \r\n  /* Write to CEC Control Register */\r\n  hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop|\\\r\n                         hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | hcec->Init.BroadcastMsgNoErrorBitGen |\\\r\n\t\t\t hcec->Init.SignalFreeTimeOption |((uint32_t)(hcec->Init.OwnAddress)<<16U) |\\\r\n                         hcec->Init.ListenMode;\r\n  \r\n  /* Enable the following CEC Transmission/Reception interrupts as\r\n   * well as the following CEC Transmission/Reception Errors interrupts \r\n   * Rx Byte Received IT \r\n   * End of Reception IT \r\n   * Rx overrun\r\n   * Rx bit rising error\r\n   * Rx short bit period error\r\n   * Rx long bit period error\r\n   * Rx missing acknowledge\r\n   * Tx Byte Request IT \r\n   * End of Transmission IT\r\n   * Tx Missing Acknowledge IT\r\n   * Tx-Error IT\r\n   * Tx-Buffer Underrun IT \r\n   * Tx arbitration lost   */\r\n __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);\r\n    \r\n  /* Enable the CEC Peripheral */\r\n  __HAL_CEC_ENABLE(hcec);\r\n  \r\n  hcec->ErrorCode = HAL_CEC_ERROR_NONE;\r\n  hcec->gState = HAL_CEC_STATE_READY;\r\n  hcec->RxState = HAL_CEC_STATE_READY;\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief DeInitializes the CEC peripheral \r\n  * @param hcec: CEC handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)\r\n{\r\n  /* Check the CEC handle allocation */\r\n  if(hcec == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));\r\n\r\n  hcec->gState = HAL_CEC_STATE_BUSY;\r\n  \r\n  /* DeInit the low level hardware */\r\n  HAL_CEC_MspDeInit(hcec);\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_CEC_DISABLE(hcec);\r\n  \r\n  /* Clear Flags */\r\n  __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXEND|CEC_FLAG_TXBR|CEC_FLAG_RXBR|CEC_FLAG_RXEND|CEC_ISR_ALL_ERROR);\r\n  \r\n  /* Disable the following CEC Transmission/Reception interrupts as\r\n   * well as the following CEC Transmission/Reception Errors interrupts \r\n   * Rx Byte Received IT \r\n   * End of Reception IT \r\n   * Rx overrun\r\n   * Rx bit rising error\r\n   * Rx short bit period error\r\n   * Rx long bit period error\r\n   * Rx missing acknowledge\r\n   * Tx Byte Request IT \r\n   * End of Transmission IT\r\n   * Tx Missing Acknowledge IT\r\n   * Tx-Error IT\r\n   * Tx-Buffer Underrun IT \r\n   * Tx arbitration lost   */\r\n  __HAL_CEC_DISABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);\r\n  \r\n  hcec->ErrorCode = HAL_CEC_ERROR_NONE;\r\n  hcec->gState = HAL_CEC_STATE_RESET;\r\n  hcec->RxState = HAL_CEC_STATE_RESET;\r\n  \r\n  /* Process Unlock */\r\n  __HAL_UNLOCK(hcec);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Initializes the Own Address of the CEC device\r\n  * @param hcec: CEC handle\r\n  * @param  CEC_OwnAddress: The CEC own address.  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_CEC_OWN_ADDRESS(CEC_OwnAddress));\r\n\r\n  if ((hcec->gState == HAL_CEC_STATE_READY) && (hcec->RxState == HAL_CEC_STATE_READY))\r\n  { \r\n    /* Process Locked */\r\n    __HAL_LOCK(hcec); \r\n    \r\n    hcec->gState = HAL_CEC_STATE_BUSY;\r\n  \r\n    /* Disable the Peripheral */\r\n    __HAL_CEC_DISABLE(hcec);\r\n    \r\n    if(CEC_OwnAddress != CEC_OWN_ADDRESS_NONE)\r\n    {\r\n      hcec->Instance->CFGR |= ((uint32_t)CEC_OwnAddress<<16);\r\n    }\r\n    else\r\n    {\r\n      hcec->Instance->CFGR &= ~(CEC_CFGR_OAR);\r\n    }\r\n        \r\n    hcec->gState = HAL_CEC_STATE_READY;\r\n    hcec->ErrorCode = HAL_CEC_ERROR_NONE;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hcec); \r\n    \r\n    /* Enable the Peripheral */\r\n    __HAL_CEC_ENABLE(hcec);\r\n    \r\n    return  HAL_OK; \r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief CEC MSP Init\r\n  * @param hcec: CEC handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcec);\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_CEC_MspInit can be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief CEC MSP DeInit\r\n  * @param hcec: CEC handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcec);\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_CEC_MspDeInit can be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CEC_Exported_Functions_Group2 Input and Output operation functions \r\n  *  @brief CEC Transmit/Receive functions \r\n  *\r\n@verbatim     \r\n ===============================================================================\r\n                      ##### IO operation functions ##### \r\n ===============================================================================  \r\n    This subsection provides a set of functions allowing to manage the CEC data transfers.\r\n    \r\n    (#) The CEC handle must contain the initiator (TX side) and the destination (RX side)\r\n        logical addresses (4-bit long addresses, 0xF for broadcast messages destination)\r\n    \r\n    (#) The communication is performed using Interrupts. \r\n           These API's return the HAL status.\r\n           The end of the data processing will be indicated through the \r\n           dedicated CEC IRQ when using Interrupt mode.\r\n           The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks \r\n           will be executed respectively at the end of the transmit or Receive process\r\n           The HAL_CEC_ErrorCallback() user callback will be executed when a communication \r\n           error is detected\r\n        \r\n    (#) API's with Interrupt are :\r\n         (+) HAL_CEC_Transmit_IT()\r\n         (+) HAL_CEC_IRQHandler()\r\n\r\n    (#) A set of User Callbacks are provided:\r\n         (+) HAL_CEC_TxCpltCallback()\r\n         (+) HAL_CEC_RxCpltCallback()\r\n         (+) HAL_CEC_ErrorCallback()\r\n      \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief Send data in interrupt mode \r\n  * @param hcec: CEC handle \r\n  * @param InitiatorAddress: Initiator address\r\n  * @param DestinationAddress: destination logical address      \r\n  * @param pData: pointer to input byte data buffer\r\n  * @param Size: amount of data to be sent in bytes (without counting the header).\r\n  *              0 means only the header is sent (ping operation).\r\n  *              Maximum TX size is 15 bytes (1 opcode and up to 14 operands).    \r\n  * @retval HAL status\r\n  */  \r\nHAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)\r\n{\r\n  /* if the IP isn't already busy and if there is no previous transmission\r\n     already pending due to arbitration lost */\r\n  if (hcec->gState == HAL_CEC_STATE_READY) \r\n  {    \r\n    if((pData == NULL ) && (Size > 0)) \r\n    {\r\n      return  HAL_ERROR;                                    \r\n    }\r\n\r\n    assert_param(IS_CEC_ADDRESS(DestinationAddress)); \r\n    assert_param(IS_CEC_ADDRESS(InitiatorAddress)); \r\n    assert_param(IS_CEC_MSGSIZE(Size));\r\n    \r\n    /* Process Locked */\r\n    __HAL_LOCK(hcec);\r\n    hcec->pTxBuffPtr = pData;\r\n    hcec->gState = HAL_CEC_STATE_BUSY_TX;\r\n    hcec->ErrorCode = HAL_CEC_ERROR_NONE;\r\n  \r\n    /* initialize the number of bytes to send,\r\n     * 0 means only one header is sent (ping operation) */\r\n    hcec->TxXferCount = Size;\r\n    \r\n    /* in case of no payload (Size = 0), sender is only pinging the system;\r\n       Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */\r\n    if (Size == 0)\r\n    {\r\n      __HAL_CEC_LAST_BYTE_TX_SET(hcec);\r\n    }\r\n    /* send header block */\r\n    hcec->Instance->TXDR = ((uint8_t)(InitiatorAddress << CEC_INITIATOR_LSB_POS) |(uint8_t) DestinationAddress);\r\n    /* Set TX Start of Message  (TXSOM) bit */\r\n    __HAL_CEC_FIRST_BYTE_TX_SET(hcec);\r\n\t    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hcec); \r\n  \r\n    return HAL_OK;\r\n\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Get size of the received frame.\r\n  * @param hcec: CEC handle\r\n  * @retval Frame size\r\n  */\r\nuint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec)\r\n{\r\n  return hcec->RxXferSize;\r\n}\r\n\r\n/**\r\n  * @brief Change Rx Buffer.\r\n  * @param hcec: CEC handle\r\n  * @param Rxbuffer: Rx Buffer\r\n  * @note  This function can be called only inside the HAL_CEC_RxCpltCallback() \r\n  * @retval Frame size\r\n  */\r\nvoid HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer)\r\n{\r\n  hcec->Init.RxBuffer = Rxbuffer; \r\n}\r\n  \r\n/**\r\n  * @brief This function handles CEC interrupt requests.\r\n  * @param hcec: CEC handle\r\n  * @retval None\r\n  */\r\nvoid HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)\r\n{\r\n  \r\n  /* save interrupts register for further error or interrupts handling purposes */\r\n  uint32_t reg = 0;\r\n  reg = hcec->Instance->ISR;\r\n\r\n  \r\n  /* ----------------------------Arbitration Lost Management----------------------------------*/     \r\n  /* CEC TX arbitration error interrupt occurred --------------------------------------*/\r\n  if((reg & CEC_FLAG_ARBLST) != RESET) \r\n  { \r\n    hcec->ErrorCode = HAL_CEC_ERROR_ARBLST;\r\n    __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST);\r\n  }\r\n  \r\n  /* ----------------------------Rx Management----------------------------------*/ \r\n  /* CEC RX byte received interrupt  ---------------------------------------------------*/\r\n  if((reg & CEC_FLAG_RXBR) != RESET) \r\n  { \r\n    /* reception is starting */ \r\n    hcec->RxState = HAL_CEC_STATE_BUSY_RX;\r\n    hcec->RxXferSize++;\r\n    /* read received byte */\r\n    *hcec->Init.RxBuffer++ = hcec->Instance->RXDR;\r\n    __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR);  \r\n  }\r\n  \r\n  /* CEC RX end received interrupt  ---------------------------------------------------*/\r\n  if((reg & CEC_FLAG_RXEND) != RESET) \r\n  { \r\n    /* clear IT */\r\n    __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND);\r\n    \r\n    /* Rx process is completed, restore hcec->RxState to Ready */\r\n    hcec->RxState = HAL_CEC_STATE_READY; \r\n    hcec->ErrorCode = HAL_CEC_ERROR_NONE;\r\n    hcec->Init.RxBuffer-=hcec->RxXferSize;\r\n    HAL_CEC_RxCpltCallback(hcec, hcec->RxXferSize); \r\n    hcec->RxXferSize = 0; \r\n  }\r\n  \r\n  /* ----------------------------Tx Management----------------------------------*/  \r\n  /* CEC TX byte request interrupt ------------------------------------------------*/\r\n  if((reg & CEC_FLAG_TXBR) != RESET) \r\n  {\r\n    if (hcec->TxXferCount == 0)\r\n    {\r\n      /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */\r\n      __HAL_CEC_LAST_BYTE_TX_SET(hcec);\r\n      hcec->Instance->TXDR = *hcec->pTxBuffPtr++;\r\n    }\r\n    else\r\n    {\t\r\n      hcec->Instance->TXDR = *hcec->pTxBuffPtr++;\r\n      hcec->TxXferCount--;\r\n    }  \r\n    /* clear Tx-Byte request flag */\r\n    __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR); \r\n  } \r\n  \r\n  /* CEC TX end interrupt ------------------------------------------------*/\r\n  if((reg & CEC_FLAG_TXEND) != RESET) \r\n  {\t\r\n    __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND);\r\n    \r\n    /* Tx process is ended, restore hcec->gState to Ready */     \r\n    hcec->gState = HAL_CEC_STATE_READY;\r\n    /* Call the Process Unlocked before calling the Tx call back API to give the possibility to\r\n    start again the Transmission under the Tx call back API */\r\n    __HAL_UNLOCK(hcec);\r\n    hcec->ErrorCode = HAL_CEC_ERROR_NONE;\r\n    HAL_CEC_TxCpltCallback(hcec);\r\n  } \r\n  \r\n  /* ----------------------------Rx/Tx Error Management----------------------------------*/   \r\n  if ((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != 0)\r\n  {\r\n    hcec->ErrorCode = reg;\r\n    __HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR|HAL_CEC_ERROR_BRE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|HAL_CEC_ERROR_RXACKE|HAL_CEC_ERROR_TXUDR|HAL_CEC_ERROR_TXERR|HAL_CEC_ERROR_TXACKE);\r\n\r\n    \r\n    if((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE)) != RESET)\r\n    {\r\n      hcec->Init.RxBuffer-=hcec->RxXferSize;\t\r\n      hcec->RxXferSize = 0; \r\n      hcec->RxState = HAL_CEC_STATE_READY;\r\n    }\r\n    else if (((reg & (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != RESET) && ((reg & CEC_ISR_ARBLST) == RESET))\r\n    {\t\r\n      /* Set the CEC state ready to be able to start again the process */\r\n      hcec->gState = HAL_CEC_STATE_READY;\r\n    }\t\r\n    \r\n    /* Error  Call Back */    \r\n    HAL_CEC_ErrorCallback(hcec);\r\n  }\r\n  \r\n}\r\n\r\n/**\r\n  * @brief Tx Transfer completed callback\r\n  * @param hcec: CEC handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcec);  \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_CEC_TxCpltCallback can be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief Rx Transfer completed callback\r\n  * @param hcec: CEC handle\r\n  * @param RxFrameSize: Size of frame\r\n  * @retval None\r\n  */\r\n__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcec);\r\n  UNUSED(RxFrameSize);\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_CEC_RxCpltCallback can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief CEC error callbacks\r\n  * @param hcec: CEC handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcec);\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_CEC_ErrorCallback can be implemented in the user file\r\n   */ \r\n}\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control function \r\n  *  @brief   CEC control functions \r\n  *\r\n@verbatim   \r\n ===============================================================================\r\n                      ##### Peripheral Control function #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides a set of functions allowing to control the CEC.\r\n     (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral. \r\n\t (+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral. \r\n@endverbatim\r\n  * @{\r\n  */\r\n/**\r\n  * @brief return the CEC state\r\n  * @param hcec: pointer to a CEC_HandleTypeDef structure that contains\r\n  *              the configuration information for the specified CEC module.\r\n  * @retval HAL state\r\n  */\r\nHAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)\r\n{\r\n  uint32_t temp1= 0x00U, temp2 = 0x00U;\r\n  temp1 = hcec->gState;\r\n  temp2 = hcec->RxState;\r\n  \r\n  return (HAL_CEC_StateTypeDef)(temp1 | temp2);\r\n}\r\n\r\n/**\r\n* @brief  Return the CEC error code\r\n* @param  hcec : pointer to a CEC_HandleTypeDef structure that contains\r\n  *              the configuration information for the specified CEC.\r\n* @retval CEC Error Code\r\n*/\r\nuint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)\r\n{\r\n  return hcec->ErrorCode;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */  \r\n#endif /* HAL_CEC_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_cortex.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   CORTEX HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the CORTEX:\r\n  *           + Initialization and de-initialization functions\r\n  *           + Peripheral Control functions \r\n  *\r\n  @verbatim  \r\n  ==============================================================================\r\n                        ##### How to use this driver #####\r\n  ==============================================================================\r\n\r\n    [..]  \r\n    *** How to configure Interrupts using CORTEX HAL driver ***\r\n    ===========================================================\r\n    [..]     \r\n    This section provides functions allowing to configure the NVIC interrupts (IRQ).\r\n    The Cortex-M4 exceptions are managed by CMSIS functions.\r\n   \r\n    (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()\r\n        function according to the following table.\r\n    (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). \r\n    (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().\r\n    (#) please refer to programming manual for details in how to configure priority. \r\n      \r\n     -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. \r\n         The pending IRQ priority will be managed only by the sub priority.\r\n   \r\n     -@- IRQ priority order (sorted by highest to lowest priority):\r\n        (+@) Lowest preemption priority\r\n        (+@) Lowest sub priority\r\n        (+@) Lowest hardware priority (IRQ number)\r\n \r\n    [..]  \r\n    *** How to configure Systick using CORTEX HAL driver ***\r\n    ========================================================\r\n    [..]\r\n    Setup SysTick Timer for time base.\r\n           \r\n   (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which\r\n       is a CMSIS function that:\r\n        (++) Configures the SysTick Reload register with value passed as function parameter.\r\n        (++) Configures the SysTick IRQ priority to the lowest value (0x0F).\r\n        (++) Resets the SysTick Counter register.\r\n        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).\r\n        (++) Enables the SysTick Interrupt.\r\n        (++) Starts the SysTick Counter.\r\n    \r\n   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro\r\n       __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the\r\n       HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined\r\n       inside the stm32f7xx_hal_cortex.h file.\r\n\r\n   (+) You can change the SysTick IRQ priority by calling the\r\n       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function \r\n       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.\r\n\r\n   (+) To adjust the SysTick time base, use the following formula:\r\n                            \r\n       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)\r\n       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function\r\n       (++) Reload Value should not exceed 0xFFFFFF\r\n   \r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CORTEX CORTEX\r\n  * @brief CORTEX HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_CORTEX_MODULE_ENABLED\r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/* Private macros ------------------------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions\r\n  * @{\r\n  */\r\n\r\n\r\n/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions\r\n *  @brief    Initialization and Configuration functions \r\n *\r\n@verbatim    \r\n  ==============================================================================\r\n              ##### Initialization and de-initialization functions #####\r\n  ==============================================================================\r\n    [..]\r\n      This section provides the CORTEX HAL driver functions allowing to configure Interrupts\r\n      Systick functionalities \r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n\r\n/**\r\n  * @brief  Sets the priority grouping field (preemption priority and subpriority)\r\n  *         using the required unlock sequence.\r\n  * @param  PriorityGroup: The priority grouping bits length. \r\n  *         This parameter can be one of the following values:\r\n  *         @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority\r\n  *                                    4 bits for subpriority\r\n  *         @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority\r\n  *                                    3 bits for subpriority\r\n  *         @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority\r\n  *                                    2 bits for subpriority\r\n  *         @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority\r\n  *                                    1 bits for subpriority\r\n  *         @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority\r\n  *                                    0 bits for subpriority\r\n  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. \r\n  *         The pending IRQ priority will be managed only by the subpriority. \r\n  * @retval None\r\n  */\r\nvoid HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));\r\n  \r\n  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */\r\n  NVIC_SetPriorityGrouping(PriorityGroup);\r\n}\r\n\r\n/**\r\n  * @brief  Sets the priority of an interrupt.\r\n  * @param  IRQn: External interrupt number.\r\n  *         This parameter can be an enumerator of IRQn_Type enumeration\r\n  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r\n  * @param  PreemptPriority: The preemption priority for the IRQn channel.\r\n  *         This parameter can be a value between 0 and 15\r\n  *         A lower priority value indicates a higher priority \r\n  * @param  SubPriority: the subpriority level for the IRQ channel.\r\n  *         This parameter can be a value between 0 and 15\r\n  *         A lower priority value indicates a higher priority.          \r\n  * @retval None\r\n  */\r\nvoid HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)\r\n{ \r\n  uint32_t prioritygroup = 0x00;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));\r\n  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));\r\n  \r\n  prioritygroup = NVIC_GetPriorityGrouping();\r\n  \r\n  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));\r\n}\r\n\r\n/**\r\n  * @brief  Enables a device specific interrupt in the NVIC interrupt controller.\r\n  * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()\r\n  *         function should be called before. \r\n  * @param  IRQn External interrupt number.\r\n  *         This parameter can be an enumerator of IRQn_Type enumeration\r\n  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r\n  * @retval None\r\n  */\r\nvoid HAL_NVIC_EnableIRQ(IRQn_Type IRQn)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r\n  \r\n  /* Enable interrupt */\r\n  NVIC_EnableIRQ(IRQn);\r\n}\r\n\r\n/**\r\n  * @brief  Disables a device specific interrupt in the NVIC interrupt controller.\r\n  * @param  IRQn External interrupt number.\r\n  *         This parameter can be an enumerator of IRQn_Type enumeration\r\n  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r\n  * @retval None\r\n  */\r\nvoid HAL_NVIC_DisableIRQ(IRQn_Type IRQn)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r\n  \r\n  /* Disable interrupt */\r\n  NVIC_DisableIRQ(IRQn);\r\n}\r\n\r\n/**\r\n  * @brief  Initiates a system reset request to reset the MCU.\r\n  * @retval None\r\n  */\r\nvoid HAL_NVIC_SystemReset(void)\r\n{\r\n  /* System Reset */\r\n  NVIC_SystemReset();\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r\n  *         Counter is in free running mode to generate periodic interrupts.\r\n  * @param  TicksNumb: Specifies the ticks Number of ticks between two interrupts.\r\n  * @retval status:  - 0  Function succeeded.\r\n  *                  - 1  Function failed.\r\n  */\r\nuint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)\r\n{\r\n   return SysTick_Config(TicksNumb);\r\n}\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions\r\n *  @brief   Cortex control functions \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                      ##### Peripheral Control functions #####\r\n  ==============================================================================  \r\n    [..]\r\n      This subsection provides a set of functions allowing to control the CORTEX\r\n      (NVIC, SYSTICK, MPU) functionalities. \r\n \r\n      \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n#if (__MPU_PRESENT == 1)\r\n/**\r\n  * @brief  Initializes and configures the Region and the memory to be protected.\r\n  * @param  MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains\r\n  *                the initialization and configuration information.\r\n  * @retval None\r\n  */\r\nvoid HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));\r\n  assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));\r\n\r\n  /* Set the Region number */\r\n  MPU->RNR = MPU_Init->Number;\r\n\r\n  if ((MPU_Init->Enable) != RESET)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));\r\n    assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));\r\n    assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));\r\n    assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));\r\n    assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));\r\n    assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));\r\n    assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));\r\n    assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));\r\n    \r\n    MPU->RBAR = MPU_Init->BaseAddress;\r\n    MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |\r\n                ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |\r\n                ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |\r\n                ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |\r\n                ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |\r\n                ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |\r\n                ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |\r\n                ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |\r\n                ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);\r\n  }\r\n  else\r\n  {\r\n    MPU->RBAR = 0x00;\r\n    MPU->RASR = 0x00;\r\n  }\r\n}\r\n#endif /* __MPU_PRESENT */\r\n\r\n/**\r\n  * @brief  Gets the priority grouping field from the NVIC Interrupt Controller.\r\n  * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)\r\n  */\r\nuint32_t HAL_NVIC_GetPriorityGrouping(void)\r\n{\r\n  /* Get the PRIGROUP[10:8] field value */\r\n  return NVIC_GetPriorityGrouping();\r\n}\r\n\r\n/**\r\n  * @brief  Gets the priority of an interrupt.\r\n  * @param  IRQn: External interrupt number.\r\n  *         This parameter can be an enumerator of IRQn_Type enumeration\r\n  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r\n  * @param   PriorityGroup: the priority grouping bits length.\r\n  *         This parameter can be one of the following values:\r\n  *           @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority\r\n  *                                      4 bits for subpriority\r\n  *           @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority\r\n  *                                      3 bits for subpriority\r\n  *           @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority\r\n  *                                      2 bits for subpriority\r\n  *           @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority\r\n  *                                      1 bits for subpriority\r\n  *           @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority\r\n  *                                      0 bits for subpriority\r\n  * @param  pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).\r\n  * @param  pSubPriority: Pointer on the Subpriority value (starting from 0).\r\n  * @retval None\r\n  */\r\nvoid HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));\r\n /* Get priority for Cortex-M system or device specific interrupts */\r\n  NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);\r\n}\r\n\r\n/**\r\n  * @brief  Sets Pending bit of an external interrupt.\r\n  * @param  IRQn External interrupt number\r\n  *         This parameter can be an enumerator of IRQn_Type enumeration\r\n  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r\n  * @retval None\r\n  */\r\nvoid HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r\n  \r\n  /* Set interrupt pending */\r\n  NVIC_SetPendingIRQ(IRQn);\r\n}\r\n\r\n/**\r\n  * @brief  Gets Pending Interrupt (reads the pending register in the NVIC \r\n  *         and returns the pending bit for the specified interrupt).\r\n  * @param  IRQn External interrupt number.\r\n  *          This parameter can be an enumerator of IRQn_Type enumeration\r\n  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r\n  * @retval status: - 0  Interrupt status is not pending.\r\n  *                 - 1  Interrupt status is pending.\r\n  */\r\nuint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r\n  \r\n  /* Return 1 if pending else 0 */\r\n  return NVIC_GetPendingIRQ(IRQn);\r\n}\r\n\r\n/**\r\n  * @brief  Clears the pending bit of an external interrupt.\r\n  * @param  IRQn External interrupt number.\r\n  *         This parameter can be an enumerator of IRQn_Type enumeration\r\n  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r\n  * @retval None\r\n  */\r\nvoid HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r\n  \r\n  /* Clear pending interrupt */\r\n  NVIC_ClearPendingIRQ(IRQn);\r\n}\r\n\r\n/**\r\n  * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).\r\n  * @param IRQn External interrupt number\r\n  *         This parameter can be an enumerator of IRQn_Type enumeration\r\n  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))\r\n  * @retval status: - 0  Interrupt status is not pending.\r\n  *                 - 1  Interrupt status is pending.\r\n  */\r\nuint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\r\n  \r\n  /* Return 1 if active else 0 */\r\n  return NVIC_GetActive(IRQn);\r\n}\r\n\r\n/**\r\n  * @brief  Configures the SysTick clock source.\r\n  * @param  CLKSource: specifies the SysTick clock source.\r\n  *          This parameter can be one of the following values:\r\n  *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.\r\n  *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.\r\n  * @retval None\r\n  */\r\nvoid HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));\r\n  if (CLKSource == SYSTICK_CLKSOURCE_HCLK)\r\n  {\r\n    SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;\r\n  }\r\n  else\r\n  {\r\n    SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  This function handles SYSTICK interrupt request.\r\n  * @retval None\r\n  */\r\nvoid HAL_SYSTICK_IRQHandler(void)\r\n{\r\n  HAL_SYSTICK_Callback();\r\n}\r\n\r\n/**\r\n  * @brief  SYSTICK callback.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SYSTICK_Callback(void)\r\n{\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_SYSTICK_Callback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_CORTEX_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_crc.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   CRC HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the Cyclic Redundancy Check (CRC) peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + Peripheral Control functions \r\n  *           + Peripheral State functions\r\n  *\r\n  @verbatim\r\n ===============================================================================\r\n                     ##### CRC How to use this driver #####\r\n ===============================================================================\r\n    [..]\r\n\r\n    (#) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();\r\n\r\n    (#) Initialize CRC calculator\r\n         (++) specify generating polynomial (IP default or non-default one)\r\n         (++) specify initialization value (IP default or non-default one)\r\n         (++) specify input data format\r\n         (++) specify input or output data inversion mode if any\r\n\r\n    (#) Use HAL_CRC_Accumulate() function to compute the CRC value of the \r\n        input data buffer starting with the previously computed CRC as \r\n        initialization value\r\n\r\n    (#) Use HAL_CRC_Calculate() function to compute the CRC value of the \r\n        input data buffer starting with the defined initialization value \r\n        (default or non-default) to initiate CRC calculation\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CRC CRC\r\n  * @brief CRC HAL module driver.\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_CRC_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\nstatic uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);\r\nstatic uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @defgroup CRC_Exported_Functions CRC Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup HAL_CRC_Group1 Initialization/de-initialization functions \r\n  *  @brief    Initialization and Configuration functions. \r\n  *\r\n@verbatim    \r\n ===============================================================================\r\n            ##### Initialization and de-initialization functions #####\r\n ===============================================================================\r\n    [..]  This section provides functions allowing to:\r\n      (+) Initialize the CRC according to the specified parameters \r\n          in the CRC_InitTypeDef and create the associated handle\r\n      (+) DeInitialize the CRC peripheral\r\n      (+) Initialize the CRC MSP\r\n      (+) DeInitialize CRC MSP \r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initialize the CRC according to the specified\r\n  *         parameters in the CRC_InitTypeDef and create the associated handle.\r\n  * @param  hcrc: CRC handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)\r\n{\r\n  /* Check the CRC handle allocation */\r\n  if(hcrc == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));\r\n\r\n  if(hcrc->State == HAL_CRC_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    hcrc->Lock = HAL_UNLOCKED;\r\n    /* Init the low level hardware */\r\n    HAL_CRC_MspInit(hcrc);\r\n  }\r\n  \r\n  /* Change CRC peripheral state */\r\n  hcrc->State = HAL_CRC_STATE_BUSY;\r\n  \r\n  /* check whether or not non-default generating polynomial has been \r\n   * picked up by user */\r\n  assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse)); \r\n  if(hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)\r\n  {\r\n    /* initialize IP with default generating polynomial */\r\n    WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);  \r\n    MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);\r\n  }\r\n  else\r\n  {\r\n    /* initialize CRC IP with generating polynomial defined by user */\r\n    if(HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n  }\r\n  \r\n  /* check whether or not non-default CRC initial value has been \r\n   * picked up by user */\r\n  assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));\r\n  if(hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)\r\n  {\r\n    WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);  \r\n  }\r\n  else\r\n  {\r\n    WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);\r\n  }\r\n  \r\n\r\n  /* set input data inversion mode */\r\n  assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode)); \r\n  MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode); \r\n  \r\n  /* set output data inversion mode */\r\n  assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode)); \r\n  MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);  \r\n  \r\n  /* makes sure the input data format (bytes, halfwords or words stream)\r\n   * is properly specified by user */\r\n  assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));\r\n\r\n  /* Change CRC peripheral state */\r\n  hcrc->State = HAL_CRC_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  DeInitialize the CRC peripheral.\r\n  * @param  hcrc: CRC handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)\r\n{\r\n  /* Check the CRC handle allocation */\r\n  if(hcrc == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));\r\n  \r\n  /* Check the CRC peripheral state */\r\n  if(hcrc->State == HAL_CRC_STATE_BUSY)\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n  \r\n  /* Change CRC peripheral state */\r\n  hcrc->State = HAL_CRC_STATE_BUSY;\r\n  \r\n  /* Reset CRC calculation unit */\r\n  __HAL_CRC_DR_RESET(hcrc);\r\n\r\n  /* DeInit the low level hardware */\r\n  HAL_CRC_MspDeInit(hcrc);\r\n\r\n  /* Change CRC peripheral state */\r\n  hcrc->State = HAL_CRC_STATE_RESET;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hcrc);\r\n\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initialize the CRC MSP.\r\n  * @param  hcrc: CRC handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcrc);\r\n  \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_CRC_MspInit can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DeInitialize the CRC MSP.\r\n  * @param  hcrc: CRC handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcrc);\r\n  \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_CRC_MspDeInit can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_CRC_Group2 Peripheral Control functions \r\n  *  @brief   Peripheral Control functions \r\n  *\r\n@verbatim  \r\n ==============================================================================\r\n                      ##### Peripheral Control functions #####\r\n ==============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer\r\n          using combination of the previous CRC value and the new one.\r\n          \r\n          or\r\n          \r\n      (+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer\r\n          independently of the previous CRC value.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**                  \r\n  * @brief  Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer\r\n  *         starting with the previously computed CRC as initialization value.\r\n  * @param  hcrc: CRC handle\r\n  * @param  pBuffer: pointer to the input data buffer, exact input data format is\r\n  *         provided by hcrc->InputDataFormat.  \r\n  * @param  BufferLength: input data buffer length (number of bytes if pBuffer\r\n  *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,\r\n  *         number of words if pBuffer type is * uint32_t).\r\n  * @note  By default, the API expects a uint32_t pointer as input buffer parameter.\r\n  *        Input buffer pointers with other types simply need to be cast in uint32_t\r\n  *        and the API will internally adjust its input data processing based on the  \r\n  *        handle field hcrc->InputDataFormat.  \r\n  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)\r\n  */\r\nuint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)\r\n{\r\n  uint32_t index = 0; /* CRC input data buffer index */\r\n  uint32_t temp = 0;  /* CRC output (read from hcrc->Instance->DR register) */\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hcrc); \r\n    \r\n  /* Change CRC peripheral state */  \r\n  hcrc->State = HAL_CRC_STATE_BUSY;\r\n  \r\n  switch (hcrc->InputDataFormat)\r\n  {\r\n    case CRC_INPUTDATA_FORMAT_WORDS:  \r\n      /* Enter Data to the CRC calculator */\r\n      for(index = 0; index < BufferLength; index++)\r\n      {\r\n        hcrc->Instance->DR = pBuffer[index];\r\n      }\r\n      temp = hcrc->Instance->DR;\r\n      break;\r\n      \r\n    case CRC_INPUTDATA_FORMAT_BYTES: \r\n      temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);\r\n      break;\r\n      \r\n    case CRC_INPUTDATA_FORMAT_HALFWORDS: \r\n      temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);\r\n      break;\r\n    default:\r\n      break;  \r\n  }\r\n  \r\n  /* Change CRC peripheral state */    \r\n  hcrc->State = HAL_CRC_STATE_READY; \r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hcrc);\r\n  \r\n  /* Return the CRC computed value */ \r\n  return temp;\r\n}\r\n\r\n/**                  \r\n  * @brief  Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer\r\n  *         starting with hcrc->Instance->INIT as initialization value.\r\n  * @param  hcrc: CRC handle\r\n  * @param  pBuffer: pointer to the input data buffer, exact input data format is\r\n  *         provided by hcrc->InputDataFormat.  \r\n  * @param  BufferLength: input data buffer length (number of bytes if pBuffer\r\n  *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,\r\n  *         number of words if pBuffer type is * uint32_t).\r\n  * @note  By default, the API expects a uint32_t pointer as input buffer parameter.\r\n  *        Input buffer pointers with other types simply need to be cast in uint32_t\r\n  *        and the API will internally adjust its input data processing based on the  \r\n  *        handle field hcrc->InputDataFormat.   \r\n  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)\r\n  */  \r\nuint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)\r\n{\r\n  uint32_t index = 0; /* CRC input data buffer index */\r\n  uint32_t temp = 0;  /* CRC output (read from hcrc->Instance->DR register) */\r\n    \r\n  /* Process locked */\r\n  __HAL_LOCK(hcrc); \r\n  \r\n  /* Change CRC peripheral state */  \r\n  hcrc->State = HAL_CRC_STATE_BUSY;\r\n  \r\n  /* Reset CRC Calculation Unit (hcrc->Instance->INIT is \r\n  *  written in hcrc->Instance->DR) */\r\n  __HAL_CRC_DR_RESET(hcrc);\r\n  \r\n  switch (hcrc->InputDataFormat)\r\n  {\r\n    case CRC_INPUTDATA_FORMAT_WORDS:  \r\n      /* Enter 32-bit input data to the CRC calculator */\r\n      for(index = 0; index < BufferLength; index++)\r\n      {\r\n        hcrc->Instance->DR = pBuffer[index];\r\n      }\r\n      temp = hcrc->Instance->DR;\r\n      break;\r\n      \r\n    case CRC_INPUTDATA_FORMAT_BYTES: \r\n      /* Specific 8-bit input data handling  */\r\n      temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);\r\n      break;\r\n      \r\n    case CRC_INPUTDATA_FORMAT_HALFWORDS: \r\n      /* Specific 16-bit input data handling  */\r\n      temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);\r\n      break;\r\n    default:\r\n      break;\r\n  }\r\n\r\n  /* Change CRC peripheral state */\r\n  hcrc->State = HAL_CRC_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hcrc);\r\n  \r\n  /* Return the CRC computed value */ \r\n  return temp;\r\n}\r\n\r\n/**             \r\n  * @brief  Enter 8-bit input data to the CRC calculator.\r\n  *         Specific data handling to optimize processing time.  \r\n  * @param  hcrc: CRC handle\r\n  * @param  pBuffer: pointer to the input data buffer\r\n  * @param  BufferLength: input data buffer length\r\n  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)\r\n  */\r\nstatic uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)\r\n{\r\n  uint32_t i = 0; /* input data buffer index */\r\n  \r\n   /* Processing time optimization: 4 bytes are entered in a row with a single word write,\r\n    * last bytes must be carefully fed to the CRC calculator to ensure a correct type\r\n    * handling by the IP */\r\n   for(i = 0; i < (BufferLength/4); i++)\r\n   {\r\n     hcrc->Instance->DR = (uint32_t)(((uint32_t)(pBuffer[4*i])<<24) | ((uint32_t)(pBuffer[4*i+1])<<16) | ((uint32_t)(pBuffer[4*i+2])<<8) | (uint32_t)(pBuffer[4*i+3]));\r\n   }\r\n   /* last bytes specific handling */\r\n   if((BufferLength%4) != 0)\r\n   {\r\n     if(BufferLength%4 == 1)\r\n     {\r\n       *(__IO uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i];\r\n     }\r\n     if(BufferLength%4 == 2)\r\n     {\r\n       *(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)((uint16_t)((uint16_t)(pBuffer[4*i])<<8) | (uint16_t)(pBuffer[4*i+1]));\r\n     }\r\n     if(BufferLength%4 == 3)\r\n     {\r\n       *(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)((uint16_t)((uint16_t)(pBuffer[4*i])<<8) | (uint16_t)(pBuffer[4*i+1]));\r\n       *(__IO uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i+2];       \r\n     }\r\n   }\r\n  \r\n  /* Return the CRC computed value */ \r\n  return hcrc->Instance->DR;\r\n}\r\n\r\n/**             \r\n  * @brief  Enter 16-bit input data to the CRC calculator.\r\n  *         Specific data handling to optimize processing time.  \r\n  * @param  hcrc: CRC handle\r\n  * @param  pBuffer: pointer to the input data buffer\r\n  * @param  BufferLength: input data buffer length\r\n  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)\r\n  */  \r\nstatic uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)\r\n{\r\n  uint32_t i = 0;  /* input data buffer index */\r\n  \r\n  /* Processing time optimization: 2 HalfWords are entered in a row with a single word write,\r\n   * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure \r\n   * a correct type handling by the IP */\r\n  for(i = 0; i < (BufferLength/2); i++)\r\n  {\r\n    hcrc->Instance->DR = (((uint32_t)(pBuffer[2*i])<<16) | (uint32_t)(pBuffer[2*i+1]));\r\n  }\r\n  if((BufferLength%2) != 0)\r\n  {\r\n     *(__IO uint16_t*) (&hcrc->Instance->DR) = pBuffer[2*i]; \r\n  }\r\n   \r\n  /* Return the CRC computed value */ \r\n  return hcrc->Instance->DR;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_CRC_Group3 Peripheral State functions \r\n  *  @brief    Peripheral State functions. \r\n  *\r\n@verbatim   \r\n ==============================================================================\r\n                      ##### Peripheral State functions #####\r\n ==============================================================================  \r\n    [..]\r\n    This subsection permits to get in run-time the status of the peripheral \r\n    and the data flow.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Return the CRC state.\r\n  * @param  hcrc: CRC handle\r\n  * @retval HAL state\r\n  */\r\nHAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)\r\n{\r\n  return hcrc->State;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_CRC_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc_ex.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_crc_ex.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Extended CRC HAL module driver.\r\n  *    \r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the CRC peripheral:\r\n  *           + Initialization/de-initialization functions\r\n  *         \r\n  @verbatim\r\n  ==============================================================================\r\n                    ##### CRC specific features #####\r\n  ==============================================================================\r\n  [..] \r\n  (#) Polynomial configuration.\r\n  (#) Input data reverse mode.\r\n  (#) Output data reverse mode.\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************  \r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup CRCEx\r\n  * @brief CRC Extended HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_CRC_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @addtogroup CRCEx_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup CRCEx_Exported_Functions_Group1\r\n *  @brief    Extended CRC features functions\r\n *\r\n@verbatim   \r\n ===============================================================================\r\n            ##### CRC Extended features functions #####\r\n ===============================================================================  \r\n    [..]\r\nThis subsection provides function allowing to:\r\n      (+) Set CRC polynomial if different from default one.\r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n\r\n/**\r\n  * @brief  Initializes the CRC polynomial if different from default one.\r\n  * @param  hcrc: CRC handle\r\n  * @param  Pol: CRC generating polynomial (7, 8, 16 or 32-bit long)\r\n  *         This parameter is written in normal representation, e.g.\r\n  *         for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 \r\n  *         for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021     \r\n  * @param  PolyLength: CRC polynomial length \r\n  *         This parameter can be one of the following values:\r\n  *          @arg CRC_POLYLENGTH_7B: 7-bit long CRC (generating polynomial of degree 7)\r\n  *          @arg CRC_POLYLENGTH_8B: 8-bit long CRC (generating polynomial of degree 8)\r\n  *          @arg CRC_POLYLENGTH_16B: 16-bit long CRC (generating polynomial of degree 16)\r\n  *          @arg CRC_POLYLENGTH_32B: 32-bit long CRC (generating polynomial of degree 32)                \r\n  * @retval HAL status\r\n  */                                   \r\nHAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)\r\n{\r\n  uint32_t msb = 31; /* polynomial degree is 32 at most, so msb is initialized to max value */\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_CRC_POL_LENGTH(PolyLength));\r\n  \r\n  /* check polynomial definition vs polynomial size:\r\n   * polynomial length must be aligned with polynomial\r\n   * definition. HAL_ERROR is reported if Pol degree is \r\n   * larger than that indicated by PolyLength.\r\n   * Look for MSB position: msb will contain the degree of\r\n   *  the second to the largest polynomial member. E.g., for\r\n   *  X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */\r\n  while (((Pol & ((uint32_t)(0x1) << msb)) == 0) && (msb-- > 0))\r\n  {\r\n  }\r\n\r\n  switch (PolyLength)\r\n  {\r\n    case CRC_POLYLENGTH_7B:\r\n      if (msb >= HAL_CRC_LENGTH_7B)\r\n      { \r\n        return  HAL_ERROR;\r\n      }\r\n      break;\r\n    case CRC_POLYLENGTH_8B:\r\n      if (msb >= HAL_CRC_LENGTH_8B)\r\n      {\r\n        return  HAL_ERROR;\r\n      }\r\n      break;\r\n    case CRC_POLYLENGTH_16B:\r\n      if (msb >= HAL_CRC_LENGTH_16B)\r\n      {\r\n        return  HAL_ERROR;\r\n      }\r\n      break;\r\n    case CRC_POLYLENGTH_32B:\r\n      /* no polynomial definition vs. polynomial length issue possible */\r\n      break;\r\n  default:\r\n      break;\r\n  }\r\n\r\n  /* set generating polynomial */\r\n  WRITE_REG(hcrc->Instance->POL, Pol);\r\n  \r\n  /* set generating polynomial size */\r\n  MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);  \r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Set the Reverse Input data mode.\r\n  * @param  hcrc: CRC handle\r\n  * @param  InputReverseMode: Input Data inversion mode\r\n  *         This parameter can be one of the following values:\r\n  *          @arg CRC_INPUTDATA_INVERSION_NONE: no change in bit order (default value)\r\n  *          @arg CRC_INPUTDATA_INVERSION_BYTE: Byte-wise bit reversal\r\n  *          @arg CRC_INPUTDATA_INVERSION_HALFWORD: HalfWord-wise bit reversal\r\n  *          @arg CRC_INPUTDATA_INVERSION_WORD: Word-wise bit reversal              \r\n  * @retval HAL status\r\n  */                                   \r\nHAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)\r\n{  \r\n  /* Check the parameters */\r\n  assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));\r\n  \r\n  /* Change CRC peripheral state */\r\n  hcrc->State = HAL_CRC_STATE_BUSY;\r\n\r\n  /* set input data inversion mode */\r\n  MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode);    \r\n  /* Change CRC peripheral state */\r\n  hcrc->State = HAL_CRC_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Set the Reverse Output data mode.\r\n  * @param  hcrc: CRC handle\r\n  * @param  OutputReverseMode: Output Data inversion mode\r\n  *         This parameter can be one of the following values:\r\n  *          @arg CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion (default value)\r\n  *          @arg CRC_OUTPUTDATA_INVERSION_ENABLE: bit-level inversion (e.g for a 8-bit CRC: 0xB5 becomes 0xAD)\r\n  * @retval HAL status\r\n  */                                   \r\nHAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));\r\n  \r\n  /* Change CRC peripheral state */\r\n  hcrc->State = HAL_CRC_STATE_BUSY;\r\n\r\n  /* set output data inversion mode */\r\n  MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode); \r\n      \r\n  /* Change CRC peripheral state */\r\n  hcrc->State = HAL_CRC_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n#endif /* HAL_CRC_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cryp.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_cryp.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   CRYP HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the Cryptography (CRYP) peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + AES processing functions\r\n  *           + DES processing functions\r\n  *           + TDES processing functions\r\n  *           + DMA callback functions\r\n  *           + CRYP IRQ handler management\r\n  *           + Peripheral State functions\r\n  *\r\n  @verbatim\r\n  ==============================================================================\r\n                     ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]\r\n      The CRYP HAL driver can be used as follows:\r\n\r\n      (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():\r\n         (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()\r\n         (##) In case of using interrupts (e.g. HAL_CRYP_AESECB_Encrypt_IT())\r\n             (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()\r\n             (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()\r\n             (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()\r\n         (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_AESECB_Encrypt_DMA())\r\n             (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()\r\n             (+++) Configure and enable two DMA streams one for managing data transfer from\r\n                 memory to peripheral (input stream) and another stream for managing data\r\n                 transfer from peripheral to memory (output stream)\r\n             (+++) Associate the initialized DMA handle to the CRYP DMA handle\r\n                 using  __HAL_LINKDMA()\r\n             (+++) Configure the priority and enable the NVIC for the transfer complete\r\n                 interrupt on the two DMA Streams. The output stream should have higher\r\n                 priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()\r\n    \r\n      (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:\r\n         (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit\r\n         (##) The key size: 128, 192 and 256. This parameter is relevant only for AES\r\n         (##) The encryption/decryption key. It's size depends on the algorithm\r\n              used for encryption/decryption\r\n         (##) The initialization vector (counter). It is not used ECB mode.\r\n    \r\n      (#)Three processing (encryption/decryption) functions are available:\r\n         (##) Polling mode: encryption and decryption APIs are blocking functions\r\n              i.e. they process the data and wait till the processing is finished,\r\n              e.g. HAL_CRYP_AESCBC_Encrypt()\r\n         (##) Interrupt mode: encryption and decryption APIs are not blocking functions\r\n              i.e. they process the data under interrupt,\r\n              e.g. HAL_CRYP_AESCBC_Encrypt_IT()\r\n         (##) DMA mode: encryption and decryption APIs are not blocking functions\r\n              i.e. the data transfer is ensured by DMA,\r\n              e.g. HAL_CRYP_AESCBC_Encrypt_DMA()\r\n    \r\n      (#)When the processing function is called at first time after HAL_CRYP_Init()\r\n         the CRYP peripheral is initialized and processes the buffer in input.\r\n         At second call, the processing function performs an append of the already\r\n         processed buffer.\r\n         When a new data block is to be processed, call HAL_CRYP_Init() then the\r\n         processing function.\r\n    \r\n       (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n/** @defgroup CRYP CRYP\r\n  * @brief CRYP HAL module driver.\r\n  * @{\r\n  */\r\n\r\n\r\n#ifdef HAL_CRYP_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @addtogroup CRYP_Private_define\r\n  * @{\r\n  */\r\n#define CRYP_TIMEOUT_VALUE  1\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/** @addtogroup CRYP_Private_Functions_prototypes\r\n  * @{\r\n  */  \r\nstatic void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize);\r\nstatic void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize);\r\nstatic HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);\r\nstatic HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);\r\nstatic void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);\r\nstatic void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);\r\nstatic void CRYP_DMAError(DMA_HandleTypeDef *hdma);\r\nstatic void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);\r\nstatic void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);\r\nstatic void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);\r\nstatic void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);\r\nstatic void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);\r\n/**\r\n  * @}\r\n  */ \r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @addtogroup CRYP_Private_Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  DMA CRYP Input Data process complete callback.\r\n  * @param  hdma: DMA handle\r\n  * @retval None\r\n  */\r\nstatic void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)  \r\n{\r\n  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n  \r\n  /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit\r\n     in the DMACR register */\r\n  hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);\r\n  \r\n  /* Call input data transfer complete callback */\r\n  HAL_CRYP_InCpltCallback(hcryp);\r\n}\r\n\r\n/**\r\n  * @brief  DMA CRYP Output Data process complete callback.\r\n  * @param  hdma: DMA handle\r\n  * @retval None\r\n  */\r\nstatic void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n  \r\n  /* Disable the DMA transfer for output FIFO request by resetting the DOEN bit\r\n     in the DMACR register */\r\n  hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);\r\n  \r\n  /* Disable CRYP */\r\n  __HAL_CRYP_DISABLE(hcryp);\r\n  \r\n  /* Change the CRYP state to ready */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Call output data transfer complete callback */\r\n  HAL_CRYP_OutCpltCallback(hcryp);\r\n}\r\n\r\n/**\r\n  * @brief  DMA CRYP communication error callback. \r\n  * @param  hdma: DMA handle\r\n  * @retval None\r\n  */\r\nstatic void CRYP_DMAError(DMA_HandleTypeDef *hdma)\r\n{\r\n  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n  hcryp->State= HAL_CRYP_STATE_READY;\r\n  HAL_CRYP_ErrorCallback(hcryp);\r\n}\r\n\r\n/**\r\n  * @brief  Writes the Key in Key registers. \r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  Key: Pointer to Key buffer\r\n  * @param  KeySize: Size of Key\r\n  * @retval None\r\n  */\r\nstatic void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize)\r\n{\r\n  uint32_t keyaddr = (uint32_t)Key;\r\n  \r\n  switch(KeySize)\r\n  {\r\n  case CRYP_KEYSIZE_256B:\r\n    /* Key Initialisation */\r\n    hcryp->Instance->K0LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K0RR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));\r\n    break;\r\n  case CRYP_KEYSIZE_192B:\r\n    hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));\r\n    break;\r\n  case CRYP_KEYSIZE_128B:       \r\n    hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));\r\n    break;\r\n  default:\r\n    break;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Writes the InitVector/InitCounter in IV registers. \r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  InitVector: Pointer to InitVector/InitCounter buffer\r\n  * @param  IVSize: Size of the InitVector/InitCounter\r\n  * @retval None\r\n  */\r\nstatic void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize)\r\n{\r\n  uint32_t ivaddr = (uint32_t)InitVector;\r\n  \r\n  switch(IVSize)\r\n  {\r\n  case CRYP_KEYSIZE_128B:\r\n    hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));\r\n    ivaddr+=4;\r\n    hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));\r\n    ivaddr+=4;\r\n    hcryp->Instance->IV1LR = __REV(*(uint32_t*)(ivaddr));\r\n    ivaddr+=4;\r\n    hcryp->Instance->IV1RR = __REV(*(uint32_t*)(ivaddr));\r\n    break;\r\n    /* Whatever key size 192 or 256, Init vector is written in IV0LR and IV0RR */\r\n  case CRYP_KEYSIZE_192B:\r\n    hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));\r\n    ivaddr+=4;\r\n    hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));\r\n    break;\r\n  case CRYP_KEYSIZE_256B:\r\n    hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));\r\n    ivaddr+=4;\r\n    hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));\r\n    break;\r\n  default:\r\n    break;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Process Data: Writes Input data in polling mode and read the output data\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  Input: Pointer to the Input buffer\r\n  * @param  Ilength: Length of the Input buffer, must be a multiple of 16.\r\n  * @param  Output: Pointer to the returned buffer\r\n  * @param  Timeout: Timeout value\r\n  * @retval None\r\n  */\r\nstatic HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  uint32_t i = 0;\r\n  uint32_t inputaddr  = (uint32_t)Input;\r\n  uint32_t outputaddr = (uint32_t)Output;\r\n  \r\n  for(i=0; (i < Ilength); i+=16)\r\n  {\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    \r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n    while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))\r\n    {    \r\n      /* Check for the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n        \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n  }\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Process Data: Write Input data in polling mode. \r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  Input: Pointer to the Input buffer\r\n  * @param  Ilength: Length of the Input buffer, must be a multiple of 8\r\n  * @param  Output: Pointer to the returned buffer\r\n  * @param  Timeout: Specify Timeout value  \r\n  * @retval None\r\n  */\r\nstatic HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  \r\n  uint32_t i = 0;\r\n  uint32_t inputaddr  = (uint32_t)Input;\r\n  uint32_t outputaddr = (uint32_t)Output;\r\n  \r\n  for(i=0; (i < Ilength); i+=8)\r\n  {\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    \r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n    \r\n    while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))\r\n    {\r\n      /* Check for the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */          \r\n          __HAL_UNLOCK(hcryp);\r\n          \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n  }\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Set the DMA configuration and start the DMA transfer\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  inputaddr: address of the Input buffer\r\n  * @param  Size: Size of the Input buffer, must be a multiple of 16.\r\n  * @param  outputaddr: address of the Output buffer\r\n  * @retval None\r\n  */\r\nstatic void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)\r\n{\r\n  /* Set the CRYP DMA transfer complete callback */\r\n  hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;\r\n  /* Set the DMA error callback */\r\n  hcryp->hdmain->XferErrorCallback = CRYP_DMAError;\r\n  \r\n  /* Set the CRYP DMA transfer complete callback */\r\n  hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;\r\n  /* Set the DMA error callback */\r\n  hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;\r\n  \r\n  /* Enable CRYP */\r\n  __HAL_CRYP_ENABLE(hcryp);\r\n  \r\n  /* Enable the DMA In DMA Stream */\r\n  HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DR, Size/4);\r\n\r\n  /* Enable In DMA request */\r\n  hcryp->Instance->DMACR = (CRYP_DMACR_DIEN);\r\n  \r\n  /* Enable the DMA Out DMA Stream */\r\n  HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size/4);\r\n  \r\n  /* Enable Out DMA request */\r\n  hcryp->Instance->DMACR |= CRYP_DMACR_DOEN;\r\n \r\n}\r\n\r\n/**\r\n  * @brief  Sets the CRYP peripheral in DES ECB mode.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  Direction: Encryption or decryption\r\n  * @retval None\r\n  */\r\nstatic void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)\r\n{\r\n  /* Check if initialization phase has already been performed */\r\n  if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n  {\r\n    /* Set the CRYP peripheral in AES ECB mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_DES_ECB | Direction);\r\n    \r\n    /* Set the key */\r\n    hcryp->Instance->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));\r\n    hcryp->Instance->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4));\r\n    \r\n    /* Flush FIFO */\r\n    __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n    /* Set the phase */\r\n    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Sets the CRYP peripheral in DES CBC mode.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  Direction: Encryption or decryption\r\n  * @retval None\r\n  */\r\nstatic void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)\r\n{\r\n  /* Check if initialization phase has already been performed */\r\n  if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n  {\r\n    /* Set the CRYP peripheral in AES ECB mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_DES_CBC | Direction);\r\n    \r\n    /* Set the key */\r\n    hcryp->Instance->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));\r\n    hcryp->Instance->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4));\r\n    \r\n    /* Set the Initialization Vector */\r\n    CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);\r\n    \r\n    /* Flush FIFO */\r\n    __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n    /* Set the phase */\r\n    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Sets the CRYP peripheral in TDES ECB mode.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  Direction: Encryption or decryption\r\n  * @retval None\r\n  */\r\nstatic void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)\r\n{\r\n  /* Check if initialization phase has already been performed */\r\n  if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n  {\r\n    /* Set the CRYP peripheral in AES ECB mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_TDES_ECB | Direction);\r\n    \r\n    /* Set the key */\r\n    CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);\r\n    \r\n    /* Flush FIFO */\r\n    __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n    /* Set the phase */\r\n    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Sets the CRYP peripheral in TDES CBC mode\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  Direction: Encryption or decryption\r\n  * @retval None\r\n  */\r\nstatic void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)\r\n{\r\n  /* Check if initialization phase has already been performed */\r\n  if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n  {\r\n    /* Set the CRYP peripheral in AES CBC mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_TDES_CBC | Direction);\r\n    \r\n    /* Set the key */\r\n    CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);\r\n    \r\n    /* Set the Initialization Vector */\r\n    CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);\r\n    \r\n    /* Flush FIFO */\r\n    __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n    /* Set the phase */\r\n    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n /* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup CRYP_Exported_Functions\r\n  * @{\r\n  */ \r\n  \r\n/** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions \r\n *  @brief    Initialization and Configuration functions. \r\n *\r\n@verbatim    \r\n  ==============================================================================\r\n              ##### Initialization and de-initialization functions #####\r\n  ==============================================================================\r\n    [..]  This section provides functions allowing to:\r\n      (+) Initialize the CRYP according to the specified parameters \r\n          in the CRYP_InitTypeDef and creates the associated handle\r\n      (+) DeInitialize the CRYP peripheral\r\n      (+) Initialize the CRYP MSP\r\n      (+) DeInitialize CRYP MSP \r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the CRYP according to the specified\r\n  *         parameters in the CRYP_InitTypeDef and creates the associated handle.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)\r\n{ \r\n  /* Check the CRYP handle allocation */\r\n  if(hcryp == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));\r\n  assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));\r\n    \r\n  if(hcryp->State == HAL_CRYP_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    hcryp->Lock = HAL_UNLOCKED;\r\n    /* Init the low level hardware */\r\n    HAL_CRYP_MspInit(hcryp);\r\n  }\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Set the key size and data type*/\r\n  CRYP->CR = (uint32_t) (hcryp->Init.KeySize | hcryp->Init.DataType);\r\n  \r\n  /* Reset CrypInCount and CrypOutCount */\r\n  hcryp->CrypInCount = 0;\r\n  hcryp->CrypOutCount = 0;\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Set the default CRYP phase */\r\n  hcryp->Phase = HAL_CRYP_PHASE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the CRYP peripheral. \r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)\r\n{\r\n  /* Check the CRYP handle allocation */\r\n  if(hcryp == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Set the default CRYP phase */\r\n  hcryp->Phase = HAL_CRYP_PHASE_READY;\r\n  \r\n  /* Reset CrypInCount and CrypOutCount */\r\n  hcryp->CrypInCount = 0;\r\n  hcryp->CrypOutCount = 0;\r\n  \r\n  /* Disable the CRYP Peripheral Clock */\r\n  __HAL_CRYP_DISABLE(hcryp);\r\n  \r\n  /* DeInit the low level hardware: CLOCK, NVIC.*/\r\n  HAL_CRYP_MspDeInit(hcryp);\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_RESET;\r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hcryp);\r\n\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP MSP.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @retval None\r\n  */\r\n__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcryp);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_CRYP_MspInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes CRYP MSP.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @retval None\r\n  */\r\n__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcryp);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_CRYP_MspDeInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRYP_Exported_Functions_Group2 AES processing functions \r\n *  @brief   processing functions. \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                      ##### AES processing functions #####\r\n  ==============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Encrypt plaintext using AES-128/192/256 using chaining modes\r\n      (+) Decrypt cyphertext using AES-128/192/256 using chaining modes\r\n    [..]  Three processing functions are available:\r\n      (+) Polling mode\r\n      (+) Interrupt mode\r\n      (+) DMA mode\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES ECB encryption mode\r\n  *         then encrypt pPlainData. The cypher data are available in pCypherData\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @param  Timeout: Specify Timeout value \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n  {\r\n    /* Set the key */\r\n    CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n    \r\n    /* Set the CRYP peripheral in AES ECB mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);\r\n    \r\n    /* Flush FIFO */\r\n    __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Set the phase */\r\n    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n  }\r\n  \r\n    /* Write Plain Data and Get Cypher Data */\r\n    if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES CBC encryption mode\r\n  *         then encrypt pPlainData. The cypher data are available in pCypherData\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @param  Timeout: Specify Timeout value  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n  {\r\n    /* Set the key */\r\n    CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n    \r\n    /* Set the CRYP peripheral in AES ECB mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);\r\n    \r\n    /* Set the Initialization Vector */\r\n    CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r\n    \r\n    /* Flush FIFO */\r\n    __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Set the phase */\r\n    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n  }\r\n  \r\n    /* Write Plain Data and Get Cypher Data */\r\n    if(CRYP_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES CTR encryption mode\r\n  *         then encrypt pPlainData. The cypher data are available in pCypherData\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @param  Timeout: Specify Timeout value  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r\n{  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n  {\r\n    /* Set the key */\r\n    CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n    \r\n    /* Set the CRYP peripheral in AES ECB mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);\r\n    \r\n    /* Set the Initialization Vector */\r\n    CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r\n    \r\n    /* Flush FIFO */\r\n    __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Set the phase */\r\n    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n  }\r\n  \r\n    /* Write Plain Data and Get Cypher Data */\r\n    if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES ECB decryption mode\r\n  *         then decrypted pCypherData. The cypher data are available in pPlainData\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Timeout: Specify Timeout value  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r\n{\r\n   uint32_t tickstart = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n  {\r\n    /* Set the key */\r\n    CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n    \r\n    /* Set the CRYP peripheral in AES Key mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Get tick */ \r\n    tickstart = HAL_GetTick();\r\n\r\n    while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))\r\n    {\r\n      /* Check for the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */          \r\n          __HAL_UNLOCK(hcryp);\r\n        \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n    \r\n    /* Disable CRYP */\r\n    __HAL_CRYP_DISABLE(hcryp);\r\n    \r\n    /* Reset the ALGOMODE bits*/\r\n    CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);\r\n    \r\n    /* Set the CRYP peripheral in AES ECB decryption mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);\r\n    /* Flush FIFO */\r\n    __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Set the phase */\r\n    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n  }\r\n    \r\n    /* Write Plain Data and Get Cypher Data */\r\n    if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES ECB decryption mode\r\n  *         then decrypted pCypherData. The cypher data are available in pPlainData\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Timeout: Specify Timeout value  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n  {\r\n    /* Set the key */\r\n    CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n    \r\n    /* Set the CRYP peripheral in AES Key mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Get tick */ \r\n    tickstart = HAL_GetTick();\r\n\r\n    while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))\r\n    {\r\n      /* Check for the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n          \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n    \r\n    /* Reset the ALGOMODE bits*/\r\n    CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);\r\n    \r\n    /* Set the CRYP peripheral in AES CBC decryption mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);\r\n    \r\n    /* Set the Initialization Vector */\r\n    CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r\n    \r\n    /* Flush FIFO */\r\n    __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Set the phase */\r\n    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n  }\r\n  \r\n    /* Write Plain Data and Get Cypher Data */\r\n    if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES CTR decryption mode\r\n  *         then decrypted pCypherData. The cypher data are available in pPlainData\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Timeout: Specify Timeout value  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r\n{  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n  {\r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Set the key */\r\n    CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n    \r\n    /* Set the CRYP peripheral in AES CTR mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);\r\n    \r\n    /* Set the Initialization Vector */\r\n    CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r\n    \r\n    /* Flush FIFO */\r\n    __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Set the phase */\r\n    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n  }\r\n  \r\n    /* Write Plain Data and Get Cypher Data */\r\n    if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES ECB encryption mode using Interrupt.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pPlainData;\r\n    hcryp->pCrypOutBuffPtr = pCypherData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {\r\n      /* Set the key */\r\n      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES ECB mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n     /* Set the phase */\r\n     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n    \r\n    /* Enable Interrupts */\r\n    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    hcryp->pCrypInBuffPtr += 16;\r\n    hcryp->CrypInCount -= 16;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call the Input data transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    hcryp->pCrypOutBuffPtr += 16;\r\n    hcryp->CrypOutCount -= 16;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Process Locked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES CBC encryption mode using Interrupt.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pPlainData;\r\n    hcryp->pCrypOutBuffPtr = pCypherData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {      \r\n      /* Set the key */\r\n      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES CBC mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);\r\n      \r\n      /* Set the Initialization Vector */\r\n      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n     /* Set the phase */\r\n     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n    /* Enable Interrupts */\r\n    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    hcryp->pCrypInBuffPtr += 16;\r\n    hcryp->CrypInCount -= 16;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call the Input data transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    hcryp->pCrypOutBuffPtr += 16;\r\n    hcryp->CrypOutCount -= 16;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Process Locked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES CTR encryption mode using Interrupt.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pPlainData;\r\n    hcryp->pCrypOutBuffPtr = pCypherData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {\r\n      /* Set the key */\r\n      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES CTR mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);\r\n      \r\n      /* Set the Initialization Vector */\r\n      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n     /* Set the phase */\r\n     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n    /* Enable Interrupts */\r\n    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    hcryp->pCrypInBuffPtr += 16;\r\n    hcryp->CrypInCount -= 16;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call the Input data transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    hcryp->pCrypOutBuffPtr += 16;\r\n    hcryp->CrypOutCount -= 16;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES ECB decryption mode using Interrupt.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  uint32_t tickstart = 0;\r\n\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pCypherData;\r\n    hcryp->pCrypOutBuffPtr = pPlainData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n  /* Check if initialization phase has already been performed */\r\n  if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n  {\r\n    /* Set the key */\r\n    CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n    \r\n    /* Set the CRYP peripheral in AES Key mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);\r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Get tick */ \r\n    tickstart = HAL_GetTick();\r\n\r\n    while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))\r\n    {\r\n      /* Check for the Timeout */\r\n      if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)\r\n      {\r\n        /* Change state */\r\n        hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hcryp);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n    \r\n    /* Reset the ALGOMODE bits*/\r\n    CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);\r\n    \r\n    /* Set the CRYP peripheral in AES ECB decryption mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);\r\n    \r\n    /* Flush FIFO */\r\n    __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n     /* Set the phase */\r\n     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n  }\r\n     \r\n    /* Enable Interrupts */\r\n    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    hcryp->pCrypInBuffPtr += 16;\r\n    hcryp->CrypInCount -= 16;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call the Input data transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    hcryp->pCrypOutBuffPtr += 16;\r\n    hcryp->CrypOutCount -= 16;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES CBC decryption mode using IT.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 16\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n\r\n  uint32_t tickstart = 0;   \r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    /* Get the buffer addresses and sizes */    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pCypherData;\r\n    hcryp->pCrypOutBuffPtr = pPlainData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {\r\n      /* Set the key */\r\n      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES Key mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);\r\n      \r\n      /* Enable CRYP */\r\n      __HAL_CRYP_ENABLE(hcryp);\r\n      \r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n    while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))\r\n    {\r\n      /* Check for the Timeout */\r\n      if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)\r\n      {\r\n        /* Change state */\r\n        hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hcryp);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n    \r\n      /* Reset the ALGOMODE bits*/\r\n      CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);\r\n    \r\n      /* Set the CRYP peripheral in AES CBC decryption mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);\r\n    \r\n      /* Set the Initialization Vector */\r\n      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r\n    \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n      /* Enable CRYP */\r\n      __HAL_CRYP_ENABLE(hcryp);\r\n      \r\n      /* Set the phase */\r\n      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n    \r\n    /* Enable Interrupts */\r\n    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    hcryp->pCrypInBuffPtr += 16;\r\n    hcryp->CrypInCount -= 16;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call the Input data transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    hcryp->pCrypOutBuffPtr += 16;\r\n    hcryp->CrypOutCount -= 16;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES CTR decryption mode using Interrupt.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 16\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    /* Get the buffer addresses and sizes */    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pCypherData;\r\n    hcryp->pCrypOutBuffPtr = pPlainData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {\r\n      /* Set the key */\r\n      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES CTR mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);\r\n      \r\n      /* Set the Initialization Vector */\r\n      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n      /* Set the phase */\r\n      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n    \r\n    /* Enable Interrupts */\r\n    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    hcryp->pCrypInBuffPtr += 16;\r\n    hcryp->CrypInCount -= 16;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call the Input data transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    hcryp->pCrypOutBuffPtr += 16;\r\n    hcryp->CrypOutCount -= 16;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES ECB encryption mode using DMA.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pPlainData;\r\n    outputaddr = (uint32_t)pCypherData;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {\r\n      /* Set the key */\r\n      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES ECB mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n     /* Set the phase */\r\n     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n    /* Set the input and output addresses and start DMA transfer */ \r\n    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hcryp);\r\n     \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES CBC encryption mode using DMA.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pPlainData;\r\n    outputaddr = (uint32_t)pCypherData;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {\r\n      /* Set the key */\r\n      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES ECB mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);\r\n      \r\n      /* Set the Initialization Vector */\r\n      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n       /* Set the phase */\r\n       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n     }\r\n     /* Set the input and output addresses and start DMA transfer */ \r\n     CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n     \r\n     /* Process Unlocked */\r\n     __HAL_UNLOCK(hcryp);\r\n     \r\n     /* Return function status */\r\n     return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES CTR encryption mode using DMA.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pPlainData;\r\n    outputaddr = (uint32_t)pCypherData;\r\n    \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {\r\n      /* Set the key */\r\n      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES ECB mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);\r\n      \r\n      /* Set the Initialization Vector */\r\n      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n       /* Set the phase */\r\n       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n    \r\n    /* Set the input and output addresses and start DMA transfer */ \r\n    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES ECB decryption mode using DMA.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pCypherData;\r\n    outputaddr = (uint32_t)pPlainData;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {\r\n    /* Set the key */\r\n    CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n    \r\n    /* Set the CRYP peripheral in AES Key mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n    \r\n    while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))\r\n    {\r\n      /* Check for the Timeout */\r\n      if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)\r\n      {\r\n        /* Change state */\r\n        hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hcryp);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n    \r\n    /* Reset the ALGOMODE bits*/\r\n    CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);\r\n    \r\n    /* Set the CRYP peripheral in AES ECB decryption mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);\r\n    \r\n    /* Flush FIFO */\r\n    __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n     /* Set the phase */\r\n     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n     \r\n    /* Set the input and output addresses and start DMA transfer */ \r\n    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n    \r\n     /* Process Unlocked */\r\n     __HAL_UNLOCK(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES CBC encryption mode using DMA.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pCypherData;\r\n    outputaddr = (uint32_t)pPlainData;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {\r\n      /* Set the key */\r\n      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES Key mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);\r\n      \r\n      /* Enable CRYP */\r\n      __HAL_CRYP_ENABLE(hcryp);\r\n      \r\n      /* Get tick */\r\n      tickstart = HAL_GetTick();\r\n\r\n      while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))\r\n      {\r\n        /* Check for the Timeout */\r\n        if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n          \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n      \r\n      /* Reset the ALGOMODE bits*/\r\n      CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);\r\n      \r\n      /* Set the CRYP peripheral in AES CBC decryption mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);\r\n      \r\n      /* Set the Initialization Vector */\r\n      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n      /* Set the phase */\r\n      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n    \r\n    /* Set the input and output addresses and start DMA transfer */ \r\n    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES CTR decryption mode using DMA.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 16\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{  \r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pCypherData;\r\n    outputaddr = (uint32_t)pPlainData;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {\r\n      /* Set the key */\r\n      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES CTR mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);\r\n      \r\n      /* Set the Initialization Vector */\r\n      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n      /* Set the phase */\r\n      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n    \r\n    /* Set the input and output addresses and start DMA transfer */ \r\n    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup CRYP_Exported_Functions_Group3 DES processing functions \r\n *  @brief   processing functions. \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                      ##### DES processing functions #####\r\n  ==============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Encrypt plaintext using DES using ECB or CBC chaining modes\r\n      (+) Decrypt cyphertext using ECB or CBC chaining modes\r\n    [..]  Three processing functions are available:\r\n      (+) Polling mode\r\n      (+) Interrupt mode\r\n      (+) DMA mode\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in DES ECB encryption mode.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @param  Timeout: Specify Timeout value  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Set CRYP peripheral in DES ECB encryption mode */\r\n  CRYP_SetDESECBMode(hcryp, 0);\r\n  \r\n  /* Enable CRYP */\r\n  __HAL_CRYP_ENABLE(hcryp);\r\n  \r\n  /* Write Plain Data and Get Cypher Data */\r\n  if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r\n  {\r\n    return HAL_TIMEOUT;\r\n  }\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in DES ECB decryption mode.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Timeout: Specify Timeout value  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Set CRYP peripheral in DES ECB decryption mode */\r\n  CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);\r\n  \r\n  /* Enable CRYP */\r\n  __HAL_CRYP_ENABLE(hcryp);\r\n  \r\n  /* Write Plain Data and Get Cypher Data */\r\n  if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)\r\n  {\r\n    return HAL_TIMEOUT;\r\n  }\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in DES CBC encryption mode.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @param  Timeout: Specify Timeout value  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Set CRYP peripheral in DES CBC encryption mode */\r\n  CRYP_SetDESCBCMode(hcryp, 0);\r\n  \r\n  /* Enable CRYP */\r\n  __HAL_CRYP_ENABLE(hcryp);\r\n  \r\n  /* Write Plain Data and Get Cypher Data */\r\n  if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r\n  {\r\n    return HAL_TIMEOUT;\r\n  }\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in DES ECB decryption mode.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Timeout: Specify Timeout value  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Set CRYP peripheral in DES CBC decryption mode */\r\n  CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);\r\n  \r\n  /* Enable CRYP */\r\n  __HAL_CRYP_ENABLE(hcryp);\r\n  \r\n  /* Write Plain Data and Get Cypher Data */\r\n  if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)\r\n  {\r\n    return HAL_TIMEOUT;\r\n  }\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in DES ECB encryption mode using IT.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pPlainData;\r\n    hcryp->pCrypOutBuffPtr = pCypherData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Set CRYP peripheral in DES ECB encryption mode */\r\n    CRYP_SetDESECBMode(hcryp, 0);\r\n    \r\n    /* Enable Interrupts */\r\n    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    \r\n    hcryp->pCrypInBuffPtr += 8;\r\n    hcryp->CrypInCount -= 8;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call the Input data transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    \r\n    hcryp->pCrypOutBuffPtr += 8;\r\n    hcryp->CrypOutCount -= 8;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      /* Disable IT */\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Disable CRYP */\r\n      __HAL_CRYP_DISABLE(hcryp);\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in DES CBC encryption mode using interrupt.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pPlainData;\r\n    hcryp->pCrypOutBuffPtr = pCypherData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Set CRYP peripheral in DES CBC encryption mode */\r\n    CRYP_SetDESCBCMode(hcryp, 0);\r\n    \r\n    /* Enable Interrupts */\r\n    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  \r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n\r\n    hcryp->pCrypInBuffPtr += 8;\r\n    hcryp->CrypInCount -= 8;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call the Input data transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n\r\n    hcryp->pCrypOutBuffPtr += 8;\r\n    hcryp->CrypOutCount -= 8;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      /* Disable IT */\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Disable CRYP */\r\n      __HAL_CRYP_DISABLE(hcryp);\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in DES ECB decryption mode using IT.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pCypherData;\r\n    hcryp->pCrypOutBuffPtr = pPlainData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Set CRYP peripheral in DES ECB decryption mode */\r\n    CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);\r\n    \r\n    /* Enable Interrupts */\r\n    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    \r\n    hcryp->pCrypInBuffPtr += 8;\r\n    hcryp->CrypInCount -= 8;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call the Input data transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n\r\n    hcryp->pCrypOutBuffPtr += 8;\r\n    hcryp->CrypOutCount -= 8;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      /* Disable IT */\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Disable CRYP */\r\n      __HAL_CRYP_DISABLE(hcryp);\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in DES ECB decryption mode using interrupt.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pCypherData;\r\n    hcryp->pCrypOutBuffPtr = pPlainData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Set CRYP peripheral in DES CBC decryption mode */\r\n    CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);\r\n    \r\n    /* Enable Interrupts */\r\n    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n\r\n    hcryp->pCrypInBuffPtr += 8;\r\n    hcryp->CrypInCount -= 8;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call the Input data transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n\r\n    hcryp->pCrypOutBuffPtr += 8;\r\n    hcryp->CrypOutCount -= 8;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      /* Disable IT */\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Disable CRYP */\r\n      __HAL_CRYP_DISABLE(hcryp);\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in DES ECB encryption mode using DMA.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pPlainData;\r\n    outputaddr = (uint32_t)pCypherData;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Set CRYP peripheral in DES ECB encryption mode */\r\n    CRYP_SetDESECBMode(hcryp, 0);\r\n    \r\n    /* Set the input and output addresses and start DMA transfer */ \r\n    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in DES CBC encryption mode using DMA.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pPlainData;\r\n    outputaddr = (uint32_t)pCypherData;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Set CRYP peripheral in DES CBC encryption mode */\r\n    CRYP_SetDESCBCMode(hcryp, 0);\r\n    \r\n    /* Set the input and output addresses and start DMA transfer */ \r\n    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in DES ECB decryption mode using DMA.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pCypherData;\r\n    outputaddr = (uint32_t)pPlainData;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Set CRYP peripheral in DES ECB decryption mode */\r\n    CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);\r\n    \r\n    /* Set the input and output addresses and start DMA transfer */ \r\n    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in DES ECB decryption mode using DMA.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pCypherData;\r\n    outputaddr = (uint32_t)pPlainData;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Set CRYP peripheral in DES CBC decryption mode */\r\n    CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);\r\n    \r\n    /* Set the input and output addresses and start DMA transfer */ \r\n    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRYP_Exported_Functions_Group4 TDES processing functions \r\n *  @brief   processing functions. \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                      ##### TDES processing functions #####\r\n  ==============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Encrypt plaintext using TDES based on ECB or CBC chaining modes\r\n      (+) Decrypt cyphertext using TDES based on ECB or CBC chaining modes\r\n    [..]  Three processing functions are available:\r\n      (+) Polling mode\r\n      (+) Interrupt mode\r\n      (+) DMA mode\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in TDES ECB encryption mode\r\n  *         then encrypt pPlainData. The cypher data are available in pCypherData\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @param  Timeout: Specify Timeout value  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Set CRYP peripheral in TDES ECB encryption mode */\r\n  CRYP_SetTDESECBMode(hcryp, 0);\r\n  \r\n  /* Enable CRYP */\r\n  __HAL_CRYP_ENABLE(hcryp);\r\n  \r\n  /* Write Plain Data and Get Cypher Data */\r\n  if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r\n  {\r\n    return HAL_TIMEOUT;\r\n  }\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in TDES ECB decryption mode\r\n  *         then decrypted pCypherData. The cypher data are available in pPlainData\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @param  Timeout: Specify Timeout value  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r\n{  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Set CRYP peripheral in TDES ECB decryption mode */\r\n  CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);\r\n  \r\n  /* Enable CRYP */\r\n  __HAL_CRYP_ENABLE(hcryp);\r\n  \r\n  /* Write Cypher Data and Get Plain Data */\r\n  if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)\r\n  {\r\n    return HAL_TIMEOUT;\r\n  }\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in TDES CBC encryption mode\r\n  *         then encrypt pPlainData. The cypher data are available in pCypherData\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @param  Timeout: Specify Timeout value  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Set CRYP peripheral in TDES CBC encryption mode */\r\n  CRYP_SetTDESCBCMode(hcryp, 0);\r\n  \r\n  /* Enable CRYP */\r\n  __HAL_CRYP_ENABLE(hcryp);\r\n  \r\n  /* Write Plain Data and Get Cypher Data */\r\n  if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r\n  {\r\n    return HAL_TIMEOUT;\r\n  }\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in TDES CBC decryption mode\r\n  *         then decrypted pCypherData. The cypher data are available in pPlainData\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Timeout: Specify Timeout value  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Set CRYP peripheral in TDES CBC decryption mode */\r\n  CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);\r\n  \r\n  /* Enable CRYP */\r\n  __HAL_CRYP_ENABLE(hcryp);\r\n  \r\n  /* Write Cypher Data and Get Plain Data */\r\n  if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)\r\n  {\r\n    return HAL_TIMEOUT;\r\n  }\r\n  \r\n  /* Change the CRYP state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in TDES ECB encryption mode using interrupt.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pPlainData;\r\n    hcryp->pCrypOutBuffPtr = pCypherData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Set CRYP peripheral in TDES ECB encryption mode */\r\n    CRYP_SetTDESECBMode(hcryp, 0);\r\n    \r\n    /* Enable Interrupts */\r\n    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n\r\n    hcryp->pCrypInBuffPtr += 8;\r\n    hcryp->CrypInCount -= 8;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call the Input data transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n\r\n    hcryp->pCrypOutBuffPtr += 8;\r\n    hcryp->CrypOutCount -= 8;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      /* Disable IT */\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Disable CRYP */\r\n      __HAL_CRYP_DISABLE(hcryp);\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call the Output data transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in TDES CBC encryption mode.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pPlainData;\r\n    hcryp->pCrypOutBuffPtr = pCypherData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Set CRYP peripheral in TDES CBC encryption mode */\r\n    CRYP_SetTDESCBCMode(hcryp, 0);\r\n    \r\n    /* Enable Interrupts */\r\n    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n\r\n    hcryp->pCrypInBuffPtr += 8;\r\n    hcryp->CrypInCount -= 8;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call the Input data transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n        \r\n    hcryp->pCrypOutBuffPtr += 8;\r\n    hcryp->CrypOutCount -= 8;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Disable CRYP */\r\n      __HAL_CRYP_DISABLE(hcryp);\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in TDES ECB decryption mode.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pCypherData;\r\n    hcryp->pCrypOutBuffPtr = pPlainData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Set CRYP peripheral in TDES ECB decryption mode */\r\n    CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);\r\n    \r\n    /* Enable Interrupts */\r\n    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n\r\n    hcryp->pCrypInBuffPtr += 8;\r\n    hcryp->CrypInCount -= 8;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call the Input data transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n\r\n    hcryp->pCrypOutBuffPtr += 8;\r\n    hcryp->CrypOutCount -= 8;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Disable CRYP */\r\n      __HAL_CRYP_DISABLE(hcryp);\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n} \r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in TDES CBC decryption mode.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pCypherData;\r\n    hcryp->pCrypOutBuffPtr = pPlainData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Set CRYP peripheral in TDES CBC decryption mode */\r\n    CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);\r\n    \r\n    /* Enable Interrupts */\r\n    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n    \r\n    /* Enable CRYP */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n\r\n    hcryp->pCrypInBuffPtr += 8;\r\n    hcryp->CrypInCount -= 8;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call the Input data transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n\r\n    hcryp->pCrypOutBuffPtr += 8;\r\n    hcryp->CrypOutCount -= 8;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Disable CRYP */\r\n      __HAL_CRYP_DISABLE(hcryp);\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in TDES ECB encryption mode using DMA.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pPlainData;\r\n    outputaddr = (uint32_t)pCypherData;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Set CRYP peripheral in TDES ECB encryption mode */\r\n    CRYP_SetTDESECBMode(hcryp, 0);\r\n    \r\n    /* Set the input and output addresses and start DMA transfer */ \r\n    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in TDES CBC encryption mode using DMA.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pPlainData;\r\n    outputaddr = (uint32_t)pCypherData;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Set CRYP peripheral in TDES CBC encryption mode */\r\n    CRYP_SetTDESCBCMode(hcryp, 0);\r\n    \r\n    /* Set the input and output addresses and start DMA transfer */ \r\n    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in TDES ECB decryption mode using DMA.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pCypherData;\r\n    outputaddr = (uint32_t)pPlainData;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Set CRYP peripheral in TDES ECB decryption mode */\r\n    CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);\r\n    \r\n    /* Set the input and output addresses and start DMA transfer */ \r\n    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in TDES CBC decryption mode using DMA.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 8\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pCypherData;\r\n    outputaddr = (uint32_t)pPlainData;\r\n    \r\n    /* Change the CRYP state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Set CRYP peripheral in TDES CBC decryption mode */\r\n    CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);\r\n    \r\n    /* Set the input and output addresses and start DMA transfer */ \r\n    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRYP_Exported_Functions_Group5 DMA callback functions \r\n *  @brief   DMA callback functions. \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                      ##### DMA callback functions  #####\r\n  ==============================================================================  \r\n    [..]  This section provides DMA callback functions:\r\n      (+) DMA Input data transfer complete\r\n      (+) DMA Output data transfer complete\r\n      (+) DMA error\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Input FIFO transfer completed callbacks.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @retval None\r\n  */\r\n__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcryp);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_CRYP_InCpltCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  Output FIFO transfer completed callbacks.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @retval None\r\n  */\r\n__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcryp);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_CRYP_OutCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  CRYP error callbacks.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @retval None\r\n  */\r\n __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hcryp);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_CRYP_ErrorCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRYP_Exported_Functions_Group6 CRYP IRQ handler management  \r\n *  @brief   CRYP IRQ handler.\r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                ##### CRYP IRQ handler management #####\r\n  ==============================================================================  \r\n[..]  This section provides CRYP IRQ handler function.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  This function handles CRYP interrupt request.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @retval None\r\n  */\r\nvoid HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)\r\n{\r\n  switch(CRYP->CR & CRYP_CR_ALGOMODE_DIRECTION)\r\n  {\r\n  case CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT:\r\n    HAL_CRYP_TDESECB_Encrypt_IT(hcryp, NULL, 0, NULL);\r\n    break;\r\n    \r\n  case CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT:\r\n    HAL_CRYP_TDESECB_Decrypt_IT(hcryp, NULL, 0, NULL);\r\n    break;\r\n    \r\n  case CRYP_CR_ALGOMODE_TDES_CBC_ENCRYPT:\r\n    HAL_CRYP_TDESCBC_Encrypt_IT(hcryp, NULL, 0, NULL);\r\n    break;\r\n    \r\n  case CRYP_CR_ALGOMODE_TDES_CBC_DECRYPT:\r\n    HAL_CRYP_TDESCBC_Decrypt_IT(hcryp, NULL, 0, NULL);\r\n    break;\r\n    \r\n  case CRYP_CR_ALGOMODE_DES_ECB_ENCRYPT:\r\n    HAL_CRYP_DESECB_Encrypt_IT(hcryp, NULL, 0, NULL);\r\n    break;\r\n    \r\n  case CRYP_CR_ALGOMODE_DES_ECB_DECRYPT:\r\n    HAL_CRYP_DESECB_Decrypt_IT(hcryp, NULL, 0, NULL);\r\n    break;\r\n    \r\n  case CRYP_CR_ALGOMODE_DES_CBC_ENCRYPT:\r\n    HAL_CRYP_DESCBC_Encrypt_IT(hcryp, NULL, 0, NULL);\r\n    break;\r\n    \r\n  case CRYP_CR_ALGOMODE_DES_CBC_DECRYPT:\r\n    HAL_CRYP_DESCBC_Decrypt_IT(hcryp, NULL, 0, NULL);\r\n    break;\r\n    \r\n  case CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT:\r\n    HAL_CRYP_AESECB_Encrypt_IT(hcryp, NULL, 0, NULL);\r\n    break;\r\n    \r\n  case CRYP_CR_ALGOMODE_AES_ECB_DECRYPT:\r\n    HAL_CRYP_AESECB_Decrypt_IT(hcryp, NULL, 0, NULL);\r\n    break;\r\n    \r\n  case CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT:\r\n    HAL_CRYP_AESCBC_Encrypt_IT(hcryp, NULL, 0, NULL);\r\n    break;\r\n    \r\n  case CRYP_CR_ALGOMODE_AES_CBC_DECRYPT:\r\n    HAL_CRYP_AESCBC_Decrypt_IT(hcryp, NULL, 0, NULL);\r\n    break;\r\n    \r\n  case CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT:\r\n    HAL_CRYP_AESCTR_Encrypt_IT(hcryp, NULL, 0, NULL);       \r\n    break;\r\n    \r\n  case CRYP_CR_ALGOMODE_AES_CTR_DECRYPT:\r\n    HAL_CRYP_AESCTR_Decrypt_IT(hcryp, NULL, 0, NULL);        \r\n    break;\r\n    \r\n  default:\r\n    break;\r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup CRYP_Exported_Functions_Group7 Peripheral State functions \r\n *  @brief   Peripheral State functions. \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                      ##### Peripheral State functions #####\r\n  ==============================================================================  \r\n    [..]\r\n    This subsection permits to get in run-time the status of the peripheral.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Returns the CRYP state.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @retval HAL state\r\n  */\r\nHAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)\r\n{\r\n  return hcryp->State;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_CRYP_MODULE_ENABLED */\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n#endif /* STM32F756xx || STM32F777xx || STM32F779xx */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cryp_ex.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_cryp_ex.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Extended CRYP HAL module driver\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of CRYP extension peripheral:\r\n  *           + Extended AES processing functions     \r\n  *  \r\n  @verbatim\r\n  ==============================================================================\r\n                     ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]\r\n    The CRYP Extension HAL driver can be used as follows:\r\n    (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():\r\n        (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()\r\n        (##) In case of using interrupts (e.g. HAL_CRYPEx_AESGCM_Encrypt_IT())\r\n            (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()\r\n            (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()\r\n            (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()\r\n        (##) In case of using DMA to control data transfer (e.g. HAL_AES_ECB_Encrypt_DMA())\r\n            (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()\r\n            (+++) Configure and enable two DMA streams one for managing data transfer from\r\n                memory to peripheral (input stream) and another stream for managing data\r\n                transfer from peripheral to memory (output stream)\r\n            (+++) Associate the initialized DMA handle to the CRYP DMA handle\r\n                using  __HAL_LINKDMA()\r\n            (+++) Configure the priority and enable the NVIC for the transfer complete\r\n                interrupt on the two DMA Streams. The output stream should have higher\r\n                priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()\r\n    (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:\r\n        (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit\r\n        (##) The key size: 128, 192 and 256. This parameter is relevant only for AES\r\n        (##) The encryption/decryption key. Its size depends on the algorithm\r\n                used for encryption/decryption\r\n        (##) The initialization vector (counter). It is not used ECB mode.\r\n    (#)Three processing (encryption/decryption) functions are available:\r\n        (##) Polling mode: encryption and decryption APIs are blocking functions\r\n             i.e. they process the data and wait till the processing is finished\r\n             e.g. HAL_CRYPEx_AESGCM_Encrypt()\r\n        (##) Interrupt mode: encryption and decryption APIs are not blocking functions\r\n                i.e. they process the data under interrupt\r\n                e.g. HAL_CRYPEx_AESGCM_Encrypt_IT()\r\n        (##) DMA mode: encryption and decryption APIs are not blocking functions\r\n                i.e. the data transfer is ensured by DMA\r\n                e.g. HAL_CRYPEx_AESGCM_Encrypt_DMA()\r\n    (#)When the processing function is called at first time after HAL_CRYP_Init()\r\n       the CRYP peripheral is initialized and processes the buffer in input.\r\n       At second call, the processing function performs an append of the already\r\n       processed buffer.\r\n       When a new data block is to be processed, call HAL_CRYP_Init() then the\r\n       processing function.\r\n    (#)In AES-GCM and AES-CCM modes are an authenticated encryption algorithms\r\n       which provide authentication messages.\r\n       HAL_AES_GCM_Finish() and HAL_AES_CCM_Finish() are used to provide those\r\n       authentication messages.\r\n       Call those functions after the processing ones (polling, interrupt or DMA).\r\n       e.g. in AES-CCM mode call HAL_CRYPEx_AESCCM_Encrypt() to encrypt the plain data\r\n            then call HAL_CRYPEx_AESCCM_Finish() to get the authentication message      \r\n    -@- For CCM Encrypt/Decrypt API's, only DataType = 8-bit is supported by this version.       \r\n    -@- The HAL_CRYPEx_AESGCM_xxxx() implementation is limited to 32bits inputs data length \r\n        (Plain/Cyphertext, Header) compared with GCM standards specifications (800-38D).\r\n    (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n/** @defgroup CRYPEx CRYPEx\r\n  * @brief CRYP Extension HAL module driver.\r\n  * @{\r\n  */\r\n\r\n\r\n#ifdef HAL_CRYP_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @addtogroup CRYPEx_Private_define\r\n  * @{\r\n  */\r\n#define CRYPEx_TIMEOUT_VALUE  1\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/** @defgroup CRYPEx_Private_Functions_prototypes  CRYP Private Functions Prototypes\r\n  * @{\r\n  */\r\nstatic void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector);\r\nstatic void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize);\r\nstatic HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout);\r\nstatic HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint32_t Timeout);\r\nstatic void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma);\r\nstatic void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma);\r\nstatic void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma);\r\nstatic void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @addtogroup CRYPEx_Private_Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  DMA CRYP Input Data process complete callback. \r\n  * @param  hdma: DMA handle\r\n  * @retval None\r\n  */\r\nstatic void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma)  \r\n{\r\n  CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  \r\n  /* Disable the DMA transfer for input Fifo request by resetting the DIEN bit\r\n     in the DMACR register */\r\n  hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);\r\n  \r\n  /* Call input data transfer complete callback */\r\n  HAL_CRYP_InCpltCallback(hcryp);\r\n}\r\n\r\n/**\r\n  * @brief  DMA CRYP Output Data process complete callback.\r\n  * @param  hdma: DMA handle\r\n  * @retval None\r\n  */\r\nstatic void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  \r\n  /* Disable the DMA transfer for output Fifo request by resetting the DOEN bit\r\n     in the DMACR register */\r\n  hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);\r\n  \r\n  /* Enable the CRYP peripheral */\r\n  __HAL_CRYP_DISABLE(hcryp);\r\n  \r\n  /* Change the CRYP peripheral state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Call output data transfer complete callback */\r\n  HAL_CRYP_OutCpltCallback(hcryp);\r\n}\r\n\r\n/**\r\n  * @brief  DMA CRYP communication error callback. \r\n  * @param  hdma: DMA handle\r\n  * @retval None\r\n  */\r\nstatic void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma)\r\n{\r\n  CRYP_HandleTypeDef* hcryp = ( CRYP_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  hcryp->State= HAL_CRYP_STATE_READY;\r\n  HAL_CRYP_ErrorCallback(hcryp);\r\n}\r\n\r\n/**\r\n  * @brief  Writes the Key in Key registers. \r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  Key: Pointer to Key buffer\r\n  * @param  KeySize: Size of Key\r\n  * @retval None\r\n  */\r\nstatic void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize)\r\n{\r\n  uint32_t keyaddr = (uint32_t)Key;\r\n  \r\n  switch(KeySize)\r\n  {\r\n  case CRYP_KEYSIZE_256B:\r\n    /* Key Initialisation */\r\n    hcryp->Instance->K0LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K0RR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));\r\n    break;\r\n  case CRYP_KEYSIZE_192B:\r\n    hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));\r\n    break;\r\n  case CRYP_KEYSIZE_128B:       \r\n    hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));\r\n    keyaddr+=4;\r\n    hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));\r\n    break;\r\n  default:\r\n    break;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Writes the InitVector/InitCounter in IV registers.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  InitVector: Pointer to InitVector/InitCounter buffer\r\n  * @retval None\r\n  */\r\nstatic void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector)\r\n{\r\n  uint32_t ivaddr = (uint32_t)InitVector;\r\n  \r\n  hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));\r\n  ivaddr+=4;\r\n  hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));\r\n  ivaddr+=4;\r\n  hcryp->Instance->IV1LR = __REV(*(uint32_t*)(ivaddr));\r\n  ivaddr+=4;\r\n  hcryp->Instance->IV1RR = __REV(*(uint32_t*)(ivaddr));\r\n}\r\n\r\n/**\r\n  * @brief  Process Data: Writes Input data in polling mode and read the Output data.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  Input: Pointer to the Input buffer.\r\n  * @param  Ilength: Length of the Input buffer, must be a multiple of 16\r\n  * @param  Output: Pointer to the returned buffer\r\n  * @param  Timeout: Timeout value \r\n  * @retval None\r\n  */\r\nstatic HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  uint32_t i = 0;\r\n  uint32_t inputaddr  = (uint32_t)Input;\r\n  uint32_t outputaddr = (uint32_t)Output;\r\n  \r\n  for(i=0; (i < Ilength); i+=16)\r\n  {\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    \r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n \r\n    while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))\r\n    {\r\n      /* Check for the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n          \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n    /* Read the Output block from the OUT FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n  }\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Sets the header phase\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  Input: Pointer to the Input buffer.\r\n  * @param  Ilength: Length of the Input buffer, must be a multiple of 16\r\n  * @param  Timeout: Timeout value   \r\n  * @retval None\r\n  */\r\nstatic HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  uint32_t loopcounter = 0;\r\n  uint32_t headeraddr = (uint32_t)Input;\r\n  \r\n  /***************************** Header phase *********************************/\r\n  if(hcryp->Init.HeaderSize != 0)\r\n  {\r\n    /* Select header phase */\r\n    __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);\r\n    /* Enable the CRYP peripheral */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    for(loopcounter = 0; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=16)\r\n    {\r\n      /* Get tick */\r\n      tickstart = HAL_GetTick();\r\n      \r\n      while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))\r\n      {\r\n        /* Check for the Timeout */\r\n        if(Timeout != HAL_MAX_DELAY)\r\n        {\r\n          if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n          {\r\n            /* Change state */\r\n            hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n            \r\n            /* Process Unlocked */\r\n            __HAL_UNLOCK(hcryp);\r\n            \r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n      }\r\n      /* Write the Input block in the IN FIFO */\r\n      hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n      headeraddr+=4;\r\n      hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n      headeraddr+=4;\r\n      hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n      headeraddr+=4;\r\n      hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n      headeraddr+=4;\r\n    }\r\n    \r\n    /* Wait until the complete message has been processed */\r\n\r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n    while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)\r\n    {\r\n      /* Check for the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n          \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n  }\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Sets the DMA configuration and start the DMA transfer.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  inputaddr: Address of the Input buffer\r\n  * @param  Size: Size of the Input buffer, must be a multiple of 16\r\n  * @param  outputaddr: Address of the Output buffer\r\n  * @retval None\r\n  */\r\nstatic void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)\r\n{\r\n  /* Set the CRYP DMA transfer complete callback */\r\n  hcryp->hdmain->XferCpltCallback = CRYPEx_GCMCCM_DMAInCplt;\r\n  /* Set the DMA error callback */\r\n  hcryp->hdmain->XferErrorCallback = CRYPEx_GCMCCM_DMAError;\r\n  \r\n  /* Set the CRYP DMA transfer complete callback */\r\n  hcryp->hdmaout->XferCpltCallback = CRYPEx_GCMCCM_DMAOutCplt;\r\n  /* Set the DMA error callback */\r\n  hcryp->hdmaout->XferErrorCallback = CRYPEx_GCMCCM_DMAError;\r\n  \r\n  /* Enable the CRYP peripheral */\r\n  __HAL_CRYP_ENABLE(hcryp);\r\n  \r\n  /* Enable the DMA In DMA Stream */\r\n  HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DR, Size/4);\r\n  \r\n  /* Enable In DMA request */\r\n  hcryp->Instance->DMACR = CRYP_DMACR_DIEN;\r\n  \r\n  /* Enable the DMA Out DMA Stream */\r\n  HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size/4);\r\n  \r\n  /* Enable Out DMA request */\r\n  hcryp->Instance->DMACR |= CRYP_DMACR_DOEN;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions---------------------------------------------------------*/\r\n/** @addtogroup CRYPEx_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions \r\n *  @brief   Extended processing functions. \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n              ##### Extended AES processing functions #####\r\n  ==============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Encrypt plaintext using AES-128/192/256 using GCM and CCM chaining modes\r\n      (+) Decrypt cyphertext using AES-128/192/256 using GCM and CCM chaining modes\r\n      (+) Finish the processing. This function is available only for GCM and CCM\r\n    [..]  Three processing methods are available:\r\n      (+) Polling mode\r\n      (+) Interrupt mode\r\n      (+) DMA mode\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES CCM encryption mode then \r\n  *         encrypt pPlainData. The cypher data are available in pCypherData.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 16\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @param  Timeout: Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;\r\n  uint32_t headersize = hcryp->Init.HeaderSize;\r\n  uint32_t headeraddr = (uint32_t)hcryp->Init.Header;\r\n  uint32_t loopcounter = 0;\r\n  uint32_t bufferidx = 0;\r\n  uint8_t blockb0[16] = {0};/* Block B0 */\r\n  uint8_t ctr[16] = {0}; /* Counter */\r\n  uint32_t b0addr = (uint32_t)blockb0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP peripheral state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n  {\r\n    /************************ Formatting the header block *********************/\r\n    if(headersize != 0)\r\n    {\r\n      /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */\r\n      if(headersize < 65280)\r\n      {\r\n        hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);\r\n        hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);\r\n        headersize += 2;\r\n      }\r\n      else\r\n      {\r\n        /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */\r\n        hcryp->Init.pScratch[bufferidx++] = 0xFF;\r\n        hcryp->Init.pScratch[bufferidx++] = 0xFE;\r\n        hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;\r\n        hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;\r\n        hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;\r\n        hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;\r\n        headersize += 6;\r\n      }\r\n      /* Copy the header buffer in internal buffer \"hcryp->Init.pScratch\" */\r\n      for(loopcounter = 0; loopcounter < headersize; loopcounter++)\r\n      {\r\n        hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];\r\n      }\r\n      /* Check if the header size is modulo 16 */\r\n      if ((headersize % 16) != 0)\r\n      {\r\n        /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */\r\n        for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)\r\n        {\r\n          hcryp->Init.pScratch[loopcounter] = 0;\r\n        }\r\n        /* Set the header size to modulo 16 */\r\n        headersize = ((headersize/16) + 1) * 16;\r\n      }\r\n      /* Set the pointer headeraddr to hcryp->Init.pScratch */\r\n      headeraddr = (uint32_t)hcryp->Init.pScratch;\r\n    }\r\n    /*********************** Formatting the block B0 **************************/\r\n    if(headersize != 0)\r\n    {\r\n      blockb0[0] = 0x40;\r\n    }\r\n    /* Flags byte */\r\n    /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */\r\n    blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);\r\n    blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);\r\n \r\n    for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)\r\n    {\r\n      blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];\r\n    }\r\n    for ( ; loopcounter < 13; loopcounter++)\r\n    {\r\n      blockb0[loopcounter+1] = 0;\r\n    }\r\n    \r\n    blockb0[14] = (Size >> 8);\r\n    blockb0[15] = (Size & 0xFF);\r\n    \r\n    /************************* Formatting the initial counter *****************/\r\n    /* Byte 0:\r\n       Bits 7 and 6 are reserved and shall be set to 0\r\n       Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter blocks\r\n       are distinct from B0\r\n       Bits 0, 1, and 2 contain the same encoding of q as in B0\r\n    */\r\n    ctr[0] = blockb0[0] & 0x07;\r\n    /* byte 1 to NonceSize is the IV (Nonce) */\r\n    for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)\r\n    {\r\n      ctr[loopcounter] = blockb0[loopcounter];\r\n    }\r\n    /* Set the LSB to 1 */\r\n    ctr[15] |= 0x01;\r\n    \r\n    /* Set the key */\r\n    CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n    \r\n    /* Set the CRYP peripheral in AES CCM mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);\r\n    \r\n    /* Set the Initialization Vector */\r\n    CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);\r\n    \r\n    /* Select init phase */\r\n    __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);\r\n    \r\n    b0addr = (uint32_t)blockb0;\r\n    /* Write the blockb0 block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n    b0addr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n    b0addr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n    b0addr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n    \r\n    /* Enable the CRYP peripheral */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n    while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r\n    {\r\n      /* Check for the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n        \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n    /***************************** Header phase *******************************/\r\n    if(headersize != 0)\r\n    {\r\n      /* Select header phase */\r\n      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);\r\n      \r\n      /* Enable the CRYP peripheral */\r\n      __HAL_CRYP_ENABLE(hcryp);\r\n      \r\n      for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)\r\n      {\r\n        /* Get tick */\r\n        tickstart = HAL_GetTick();\r\n\r\n        while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))\r\n        {\r\n          {\r\n            /* Check for the Timeout */\r\n            if(Timeout != HAL_MAX_DELAY)\r\n            {\r\n              if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n              {\r\n                /* Change state */\r\n                hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n                \r\n                /* Process Unlocked */\r\n                __HAL_UNLOCK(hcryp);\r\n                \r\n                return HAL_TIMEOUT;\r\n              }\r\n            }\r\n          }\r\n        }\r\n        /* Write the header block in the IN FIFO */\r\n        hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n        headeraddr+=4;\r\n        hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n        headeraddr+=4;\r\n        hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n        headeraddr+=4;\r\n        hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n        headeraddr+=4;\r\n      }\r\n      \r\n      /* Get tick */\r\n      tickstart = HAL_GetTick();\r\n\r\n      while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)\r\n      {\r\n        /* Check for the Timeout */\r\n        if(Timeout != HAL_MAX_DELAY)\r\n        {\r\n          if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n          {\r\n            /* Change state */\r\n            hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n            \r\n            /* Process Unlocked */\r\n            __HAL_UNLOCK(hcryp);\r\n            \r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n      }\r\n    }\r\n    /* Save formatted counter into the scratch buffer pScratch */\r\n    for(loopcounter = 0; (loopcounter < 16); loopcounter++)\r\n    {\r\n      hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];\r\n    }\r\n    /* Reset bit 0 */\r\n    hcryp->Init.pScratch[15] &= 0xfe;\r\n    \r\n    /* Select payload phase once the header phase is performed */\r\n    __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r\n    \r\n    /* Flush FIFO */\r\n    __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n    /* Enable the CRYP peripheral */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Set the phase */\r\n    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n  }\r\n  \r\n  /* Write Plain Data and Get Cypher Data */\r\n  if(CRYPEx_GCMCCM_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r\n  {\r\n    return HAL_TIMEOUT;\r\n  }\r\n  \r\n  /* Change the CRYP peripheral state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES GCM encryption mode then \r\n  *         encrypt pPlainData. The cypher data are available in pCypherData.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 16\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @param  Timeout: Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP peripheral state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n  {\r\n    /* Set the key */\r\n    CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n    \r\n    /* Set the CRYP peripheral in AES GCM mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);\r\n    \r\n    /* Set the Initialization Vector */\r\n    CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);\r\n    \r\n    /* Flush FIFO */\r\n    __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n    /* Enable the CRYP peripheral */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n    while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r\n    {\r\n      /* Check for the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n          \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n    \r\n    /* Set the header phase */\r\n    if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, Timeout) != HAL_OK)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n    \r\n    /* Disable the CRYP peripheral */\r\n    __HAL_CRYP_DISABLE(hcryp);\r\n    \r\n    /* Select payload phase once the header phase is performed */\r\n    __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r\n    \r\n    /* Flush FIFO */\r\n    __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n    /* Enable the CRYP peripheral */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Set the phase */\r\n    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n  }\r\n  \r\n  /* Write Plain Data and Get Cypher Data */\r\n  if(CRYPEx_GCMCCM_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)\r\n  {\r\n    return HAL_TIMEOUT;\r\n  }\r\n  \r\n  /* Change the CRYP peripheral state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES GCM decryption mode then\r\n  *         decrypted pCypherData. The cypher data are available in pPlainData.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @param  Size: Length of the cyphertext buffer, must be a multiple of 16\r\n  * @param  pPlainData: Pointer to the plaintext buffer \r\n  * @param  Timeout: Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP peripheral state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n  {\r\n    /* Set the key */\r\n    CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n    \r\n    /* Set the CRYP peripheral in AES GCM decryption mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);\r\n    \r\n    /* Set the Initialization Vector */\r\n    CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);\r\n    \r\n    /* Flush FIFO */\r\n    __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n    /* Enable the CRYP peripheral */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n    while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r\n    {\r\n      /* Check for the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n          \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n    \r\n    /* Set the header phase */\r\n    if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, Timeout) != HAL_OK)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n    /* Disable the CRYP peripheral */\r\n    __HAL_CRYP_DISABLE(hcryp);\r\n    \r\n    /* Select payload phase once the header phase is performed */\r\n    __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r\n    \r\n    /* Enable the CRYP peripheral */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Set the phase */\r\n    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n  }\r\n  \r\n  /* Write Plain Data and Get Cypher Data */\r\n  if(CRYPEx_GCMCCM_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)\r\n  {\r\n    return HAL_TIMEOUT;\r\n  }\r\n  \r\n  /* Change the CRYP peripheral state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Computes the authentication TAG.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  Size: Total length of the plain/cyphertext buffer\r\n  * @param  AuthTag: Pointer to the authentication buffer\r\n  * @param  Timeout: Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint32_t Size, uint8_t *AuthTag, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  uint64_t headerlength = hcryp->Init.HeaderSize * 8; /* Header length in bits */\r\n  uint64_t inputlength = Size * 8; /* input length in bits */\r\n  uint32_t tagaddr = (uint32_t)AuthTag;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP peripheral state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hcryp->Phase == HAL_CRYP_PHASE_PROCESS)\r\n  {\r\n    /* Change the CRYP phase */\r\n    hcryp->Phase = HAL_CRYP_PHASE_FINAL;\r\n    \r\n    /* Disable CRYP to start the final phase */\r\n    __HAL_CRYP_DISABLE(hcryp);\r\n    \r\n    /* Select final phase */\r\n    __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_FINAL);\r\n    \r\n    /* Enable the CRYP peripheral */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Write the number of bits in header (64 bits) followed by the number of bits\r\n       in the payload */\r\n    if(hcryp->Init.DataType == CRYP_DATATYPE_1B)\r\n    {\r\n      hcryp->Instance->DR = __RBIT(headerlength >> 32);\r\n      hcryp->Instance->DR = __RBIT(headerlength);\r\n      hcryp->Instance->DR = __RBIT(inputlength >> 32);\r\n      hcryp->Instance->DR = __RBIT(inputlength);\r\n    }\r\n    else if(hcryp->Init.DataType == CRYP_DATATYPE_8B)\r\n    {\r\n      hcryp->Instance->DR = __REV(headerlength >> 32);\r\n      hcryp->Instance->DR = __REV(headerlength);\r\n      hcryp->Instance->DR = __REV(inputlength >> 32);\r\n      hcryp->Instance->DR = __REV(inputlength);\r\n    }\r\n    else if(hcryp->Init.DataType == CRYP_DATATYPE_16B)\r\n    {\r\n      hcryp->Instance->DR = __ROR((uint32_t)(headerlength >> 32), 16);\r\n      hcryp->Instance->DR = __ROR((uint32_t)headerlength, 16);\r\n      hcryp->Instance->DR = __ROR((uint32_t)(inputlength >> 32), 16);\r\n      hcryp->Instance->DR = __ROR((uint32_t)inputlength, 16);\r\n    }\r\n    else if(hcryp->Init.DataType == CRYP_DATATYPE_32B)\r\n    {\r\n      hcryp->Instance->DR = (uint32_t)(headerlength >> 32);\r\n      hcryp->Instance->DR = (uint32_t)(headerlength);\r\n      hcryp->Instance->DR = (uint32_t)(inputlength >> 32);\r\n      hcryp->Instance->DR = (uint32_t)(inputlength);\r\n    }\r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n    while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))\r\n    {\r\n      /* Check for the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n        \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n    \r\n    /* Read the Auth TAG in the IN FIFO */\r\n    *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;\r\n    tagaddr+=4;\r\n    *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;\r\n    tagaddr+=4;\r\n    *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;\r\n    tagaddr+=4;\r\n    *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT;\r\n  }\r\n  \r\n  /* Change the CRYP peripheral state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Computes the authentication TAG for AES CCM mode.\r\n  * @note   This API is called after HAL_AES_CCM_Encrypt()/HAL_AES_CCM_Decrypt()   \r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  AuthTag: Pointer to the authentication buffer\r\n  * @param  Timeout: Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *AuthTag, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  uint32_t tagaddr = (uint32_t)AuthTag;\r\n  uint32_t ctraddr = (uint32_t)hcryp->Init.pScratch;\r\n  uint32_t temptag[4] = {0}; /* Temporary TAG (MAC) */\r\n  uint32_t loopcounter;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP peripheral state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hcryp->Phase == HAL_CRYP_PHASE_PROCESS)\r\n  {\r\n    /* Change the CRYP phase */\r\n    hcryp->Phase = HAL_CRYP_PHASE_FINAL;\r\n    \r\n    /* Disable CRYP to start the final phase */\r\n    __HAL_CRYP_DISABLE(hcryp);\r\n    \r\n    /* Select final phase */\r\n    __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_FINAL);\r\n    \r\n    /* Enable the CRYP peripheral */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Write the counter block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)ctraddr;\r\n    ctraddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)ctraddr;\r\n    ctraddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)ctraddr;\r\n    ctraddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)ctraddr;\r\n    \r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n    while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))\r\n    {\r\n      /* Check for the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n          \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n    \r\n    /* Read the Auth TAG in the IN FIFO */\r\n    temptag[0] = hcryp->Instance->DOUT;\r\n    temptag[1] = hcryp->Instance->DOUT;\r\n    temptag[2] = hcryp->Instance->DOUT;\r\n    temptag[3] = hcryp->Instance->DOUT;\r\n  }\r\n  \r\n  /* Copy temporary authentication TAG in user TAG buffer */\r\n  for(loopcounter = 0; loopcounter < hcryp->Init.TagSize ; loopcounter++)\r\n  {\r\n    /* Set the authentication TAG buffer */\r\n    *((uint8_t*)tagaddr+loopcounter) = *((uint8_t*)temptag+loopcounter);\r\n  }\r\n  \r\n  /* Change the CRYP peripheral state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES CCM decryption mode then\r\n  *         decrypted pCypherData. The cypher data are available in pPlainData.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 16\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @param  Timeout: Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  uint32_t headersize = hcryp->Init.HeaderSize;\r\n  uint32_t headeraddr = (uint32_t)hcryp->Init.Header;\r\n  uint32_t loopcounter = 0;\r\n  uint32_t bufferidx = 0;\r\n  uint8_t blockb0[16] = {0};/* Block B0 */\r\n  uint8_t ctr[16] = {0}; /* Counter */\r\n  uint32_t b0addr = (uint32_t)blockb0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hcryp);\r\n  \r\n  /* Change the CRYP peripheral state */\r\n  hcryp->State = HAL_CRYP_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n  {\r\n    /************************ Formatting the header block *********************/\r\n    if(headersize != 0)\r\n    {\r\n      /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */\r\n      if(headersize < 65280)\r\n      {\r\n        hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFFU);\r\n        hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU);\r\n        headersize += 2;\r\n      }\r\n      else\r\n      {\r\n        /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */\r\n        hcryp->Init.pScratch[bufferidx++] = 0xFFU;\r\n        hcryp->Init.pScratch[bufferidx++] = 0xFEU;\r\n        hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;\r\n        hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;\r\n        hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;\r\n        hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;\r\n        headersize += 6;\r\n      }\r\n      /* Copy the header buffer in internal buffer \"hcryp->Init.pScratch\" */\r\n      for(loopcounter = 0; loopcounter < headersize; loopcounter++)\r\n      {\r\n        hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];\r\n      }\r\n      /* Check if the header size is modulo 16 */\r\n      if ((headersize % 16) != 0)\r\n      {\r\n        /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */\r\n        for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)\r\n        {\r\n          hcryp->Init.pScratch[loopcounter] = 0;\r\n        }\r\n        /* Set the header size to modulo 16 */\r\n        headersize = ((headersize/16) + 1) * 16;\r\n      }\r\n      /* Set the pointer headeraddr to hcryp->Init.pScratch */\r\n      headeraddr = (uint32_t)hcryp->Init.pScratch;\r\n    }\r\n    /*********************** Formatting the block B0 **************************/\r\n    if(headersize != 0)\r\n    {\r\n      blockb0[0] = 0x40;\r\n    }\r\n    /* Flags byte */\r\n    /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */\r\n    blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);\r\n    blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);\r\n    \r\n    for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)\r\n    {\r\n      blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];\r\n    }\r\n    for ( ; loopcounter < 13; loopcounter++)\r\n    {\r\n      blockb0[loopcounter+1] = 0;\r\n    }\r\n    \r\n    blockb0[14] = (Size >> 8);\r\n    blockb0[15] = (Size & 0xFF);\r\n    \r\n    /************************* Formatting the initial counter *****************/\r\n    /* Byte 0:\r\n       Bits 7 and 6 are reserved and shall be set to 0\r\n       Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter \r\n       blocks are distinct from B0\r\n       Bits 0, 1, and 2 contain the same encoding of q as in B0\r\n    */\r\n    ctr[0] = blockb0[0] & 0x07;\r\n    /* byte 1 to NonceSize is the IV (Nonce) */\r\n    for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)\r\n    {\r\n      ctr[loopcounter] = blockb0[loopcounter];\r\n    }\r\n    /* Set the LSB to 1 */\r\n    ctr[15] |= 0x01;\r\n    \r\n    /* Set the key */\r\n    CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n    \r\n    /* Set the CRYP peripheral in AES CCM mode */\r\n    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);\r\n    \r\n    /* Set the Initialization Vector */\r\n    CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);\r\n    \r\n    /* Select init phase */\r\n    __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);\r\n    \r\n    b0addr = (uint32_t)blockb0;\r\n    /* Write the blockb0 block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n    b0addr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n    b0addr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n    b0addr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n    \r\n    /* Enable the CRYP peripheral */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n \r\n    while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r\n    {\r\n      /* Check for the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n        \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n    /***************************** Header phase *******************************/\r\n    if(headersize != 0)\r\n    {\r\n      /* Select header phase */\r\n      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);\r\n      \r\n      /* Enable Crypto processor */\r\n      __HAL_CRYP_ENABLE(hcryp);\r\n      \r\n      for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)\r\n      {\r\n        /* Get tick */\r\n        tickstart = HAL_GetTick();\r\n\r\n        while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))\r\n        {\r\n          /* Check for the Timeout */\r\n          if(Timeout != HAL_MAX_DELAY)\r\n          {\r\n            if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n            {\r\n              /* Change state */\r\n              hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n              \r\n              /* Process Unlocked */\r\n              __HAL_UNLOCK(hcryp);\r\n              \r\n              return HAL_TIMEOUT;\r\n            }\r\n          }\r\n        }\r\n        /* Write the header block in the IN FIFO */\r\n        hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n        headeraddr+=4;\r\n        hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n        headeraddr+=4;\r\n        hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n        headeraddr+=4;\r\n        hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n        headeraddr+=4;\r\n      }\r\n      \r\n      /* Get tick */\r\n      tickstart = HAL_GetTick();\r\n\r\n      while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)\r\n      {\r\n      /* Check for the Timeout */\r\n        if(Timeout != HAL_MAX_DELAY)\r\n        {\r\n          if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n          {\r\n            /* Change state */\r\n            hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n            \r\n            /* Process Unlocked */\r\n            __HAL_UNLOCK(hcryp);\r\n            \r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n      }\r\n    }\r\n    /* Save formatted counter into the scratch buffer pScratch */\r\n    for(loopcounter = 0; (loopcounter < 16); loopcounter++)\r\n    {\r\n      hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];\r\n    }\r\n    /* Reset bit 0 */\r\n    hcryp->Init.pScratch[15] &= 0xfe;\r\n    /* Select payload phase once the header phase is performed */\r\n    __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r\n    \r\n    /* Flush FIFO */\r\n    __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n    \r\n    /* Enable the CRYP peripheral */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Set the phase */\r\n    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n  }\r\n  \r\n  /* Write Plain Data and Get Cypher Data */\r\n  if(CRYPEx_GCMCCM_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)\r\n  {\r\n    return HAL_TIMEOUT;\r\n  }\r\n  \r\n  /* Change the CRYP peripheral state */\r\n  hcryp->State = HAL_CRYP_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hcryp);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES GCM encryption mode using IT.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 16\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    /* Get the buffer addresses and sizes */    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pPlainData;\r\n    hcryp->pCrypOutBuffPtr = pCypherData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP peripheral state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {\r\n      /* Set the key */\r\n      CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES GCM mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);\r\n      \r\n      /* Set the Initialization Vector */\r\n      CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n      /* Enable CRYP to start the init phase */\r\n      __HAL_CRYP_ENABLE(hcryp);\r\n      \r\n     /* Get tick */\r\n     tickstart = HAL_GetTick();\r\n\r\n      while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r\n      {\r\n        /* Check for the Timeout */\r\n        \r\n        if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n          \r\n          return HAL_TIMEOUT;\r\n          \r\n        }\r\n      }\r\n      \r\n      /* Set the header phase */\r\n      if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n      /* Disable the CRYP peripheral */\r\n      __HAL_CRYP_DISABLE(hcryp);\r\n      \r\n      /* Select payload phase once the header phase is performed */\r\n      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n      /* Set the phase */\r\n      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n    \r\n    if(Size != 0)\r\n    {\r\n      /* Enable Interrupts */\r\n      __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n      /* Enable the CRYP peripheral */\r\n      __HAL_CRYP_ENABLE(hcryp);\r\n    }\r\n    else\r\n    {\r\n      /* Process Locked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP state and phase */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n    }\r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    hcryp->pCrypInBuffPtr += 16;\r\n    hcryp->CrypInCount -= 16;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call the Input data transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    hcryp->pCrypOutBuffPtr += 16;\r\n    hcryp->CrypOutCount -= 16;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP peripheral state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES CCM encryption mode using interrupt.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 16\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  uint32_t headersize = hcryp->Init.HeaderSize;\r\n  uint32_t headeraddr = (uint32_t)hcryp->Init.Header;\r\n  uint32_t loopcounter = 0;\r\n  uint32_t bufferidx = 0;\r\n  uint8_t blockb0[16] = {0};/* Block B0 */\r\n  uint8_t ctr[16] = {0}; /* Counter */\r\n  uint32_t b0addr = (uint32_t)blockb0;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pPlainData;\r\n    hcryp->pCrypOutBuffPtr = pCypherData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP peripheral state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {    \r\n      /************************ Formatting the header block *******************/\r\n      if(headersize != 0)\r\n      {\r\n        /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */\r\n        if(headersize < 65280)\r\n        {\r\n          hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFFU);\r\n          hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU);\r\n          headersize += 2;\r\n        }\r\n        else\r\n        {\r\n          /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */\r\n          hcryp->Init.pScratch[bufferidx++] = 0xFFU;\r\n          hcryp->Init.pScratch[bufferidx++] = 0xFEU;\r\n          hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;\r\n          hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;\r\n          hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;\r\n          hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;\r\n          headersize += 6;\r\n        }\r\n        /* Copy the header buffer in internal buffer \"hcryp->Init.pScratch\" */\r\n        for(loopcounter = 0; loopcounter < headersize; loopcounter++)\r\n        {\r\n          hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];\r\n        }\r\n        /* Check if the header size is modulo 16 */\r\n        if ((headersize % 16) != 0)\r\n        {\r\n          /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */\r\n          for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)\r\n          {\r\n            hcryp->Init.pScratch[loopcounter] = 0;\r\n          }\r\n          /* Set the header size to modulo 16 */\r\n          headersize = ((headersize/16) + 1) * 16;\r\n        }\r\n        /* Set the pointer headeraddr to hcryp->Init.pScratch */\r\n        headeraddr = (uint32_t)hcryp->Init.pScratch;\r\n      }\r\n      /*********************** Formatting the block B0 ************************/\r\n      if(headersize != 0)\r\n      {\r\n        blockb0[0] = 0x40;\r\n      }\r\n      /* Flags byte */\r\n      /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */\r\n      blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);\r\n      blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);\r\n      \r\n      for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)\r\n      {\r\n        blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];\r\n      }\r\n      for ( ; loopcounter < 13; loopcounter++)\r\n      {\r\n        blockb0[loopcounter+1] = 0;\r\n      }\r\n      \r\n      blockb0[14] = (Size >> 8);\r\n      blockb0[15] = (Size & 0xFF);\r\n      \r\n      /************************* Formatting the initial counter ***************/\r\n      /* Byte 0:\r\n         Bits 7 and 6 are reserved and shall be set to 0\r\n         Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter \r\n         blocks are distinct from B0\r\n         Bits 0, 1, and 2 contain the same encoding of q as in B0\r\n      */\r\n      ctr[0] = blockb0[0] & 0x07;\r\n      /* byte 1 to NonceSize is the IV (Nonce) */\r\n      for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)\r\n      {\r\n        ctr[loopcounter] = blockb0[loopcounter];\r\n      }\r\n      /* Set the LSB to 1 */\r\n      ctr[15] |= 0x01;\r\n      \r\n      /* Set the key */\r\n      CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES CCM mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);\r\n      \r\n      /* Set the Initialization Vector */\r\n      CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);\r\n      \r\n      /* Select init phase */\r\n      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);\r\n      \r\n      b0addr = (uint32_t)blockb0;\r\n      /* Write the blockb0 block in the IN FIFO */\r\n      hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n      b0addr+=4;\r\n      hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n      b0addr+=4;\r\n      hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n      b0addr+=4;\r\n      hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n      \r\n      /* Enable the CRYP peripheral */\r\n      __HAL_CRYP_ENABLE(hcryp);\r\n      \r\n     /* Get tick */\r\n     tickstart = HAL_GetTick();\r\n\r\n      while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r\n      {\r\n        /* Check for the Timeout */\r\n        if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n          \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n      /***************************** Header phase *****************************/\r\n      if(headersize != 0)\r\n      {\r\n        /* Select header phase */\r\n        __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);\r\n        \r\n        /* Enable Crypto processor */\r\n        __HAL_CRYP_ENABLE(hcryp);\r\n        \r\n        for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)\r\n        {\r\n         /* Get tick */\r\n         tickstart = HAL_GetTick();\r\n\r\n          while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))\r\n          {\r\n            /* Check for the Timeout */\r\n            if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r\n            {\r\n              /* Change state */\r\n              hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n              \r\n              /* Process Unlocked */\r\n              __HAL_UNLOCK(hcryp);\r\n              \r\n              return HAL_TIMEOUT;\r\n            }\r\n          }\r\n          /* Write the header block in the IN FIFO */\r\n          hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n          headeraddr+=4;\r\n          hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n          headeraddr+=4;\r\n          hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n          headeraddr+=4;\r\n          hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n          headeraddr+=4;\r\n        }\r\n\r\n        /* Get tick */\r\n        tickstart = HAL_GetTick();\r\n\r\n        while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)\r\n        {\r\n          /* Check for the Timeout */\r\n          if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r\n          {\r\n            /* Change state */\r\n            hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n            \r\n            /* Process Unlocked */\r\n            __HAL_UNLOCK(hcryp);\r\n            \r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n      }\r\n      /* Save formatted counter into the scratch buffer pScratch */\r\n      for(loopcounter = 0; (loopcounter < 16); loopcounter++)\r\n      {\r\n        hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];\r\n      }\r\n      /* Reset bit 0 */\r\n      hcryp->Init.pScratch[15] &= 0xfe;\r\n      \r\n      /* Select payload phase once the header phase is performed */\r\n      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n      /* Set the phase */\r\n      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n    \r\n    if(Size != 0)\r\n    {\r\n      /* Enable Interrupts */\r\n      __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n      /* Enable the CRYP peripheral */\r\n      __HAL_CRYP_ENABLE(hcryp);\r\n    }\r\n    else\r\n    {\r\n      /* Change the CRYP state and phase */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n    }\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    hcryp->pCrypInBuffPtr += 16;\r\n    hcryp->CrypInCount -= 16;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    hcryp->pCrypOutBuffPtr += 16;\r\n    hcryp->CrypOutCount -= 16;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP peripheral state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES GCM decryption mode using IT.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @param  Size: Length of the cyphertext buffer, must be a multiple of 16\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    /* Get the buffer addresses and sizes */    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pCypherData;\r\n    hcryp->pCrypOutBuffPtr = pPlainData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP peripheral state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {\r\n      /* Set the key */\r\n      CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES GCM decryption mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);\r\n      \r\n      /* Set the Initialization Vector */\r\n      CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n      /* Enable CRYP to start the init phase */\r\n      __HAL_CRYP_ENABLE(hcryp);\r\n\r\n        /* Get tick */\r\n        tickstart = HAL_GetTick();\r\n\r\n      while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r\n      {\r\n        /* Check for the Timeout */\r\n        if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n          \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n      \r\n      /* Set the header phase */\r\n      if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n      /* Disable the CRYP peripheral */\r\n      __HAL_CRYP_DISABLE(hcryp);\r\n      \r\n      /* Select payload phase once the header phase is performed */\r\n      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r\n      \r\n      /* Set the phase */\r\n      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n    \r\n    if(Size != 0)\r\n    {\r\n      /* Enable Interrupts */\r\n      __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n      /* Enable the CRYP peripheral */\r\n      __HAL_CRYP_ENABLE(hcryp);\r\n    }\r\n    else\r\n    {\r\n      /* Process Locked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP state and phase */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n    }\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    hcryp->pCrypInBuffPtr += 16;\r\n    hcryp->CrypInCount -= 16;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call the Input data transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    hcryp->pCrypOutBuffPtr += 16;\r\n    hcryp->CrypOutCount -= 16;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP peripheral state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES CCM decryption mode using interrupt\r\n  *         then decrypted pCypherData. The cypher data are available in pPlainData.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData: Pointer to the cyphertext buffer \r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 16\r\n  * @param  pPlainData: Pointer to the plaintext buffer  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  uint32_t tickstart = 0;\r\n  uint32_t headersize = hcryp->Init.HeaderSize;\r\n  uint32_t headeraddr = (uint32_t)hcryp->Init.Header;\r\n  uint32_t loopcounter = 0;\r\n  uint32_t bufferidx = 0;\r\n  uint8_t blockb0[16] = {0};/* Block B0 */\r\n  uint8_t ctr[16] = {0}; /* Counter */\r\n  uint32_t b0addr = (uint32_t)blockb0;\r\n  \r\n  if(hcryp->State == HAL_CRYP_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pCypherData;\r\n    hcryp->pCrypOutBuffPtr = pPlainData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP peripheral state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {\r\n      /************************ Formatting the header block *******************/\r\n      if(headersize != 0)\r\n      {\r\n        /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */\r\n        if(headersize < 65280)\r\n        {\r\n          hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFFU);\r\n          hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU);\r\n          headersize += 2;\r\n        }\r\n        else\r\n        {\r\n          /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */\r\n          hcryp->Init.pScratch[bufferidx++] = 0xFFU;\r\n          hcryp->Init.pScratch[bufferidx++] = 0xFEU;\r\n          hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;\r\n          hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;\r\n          hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;\r\n          hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;\r\n          headersize += 6;\r\n        }\r\n        /* Copy the header buffer in internal buffer \"hcryp->Init.pScratch\" */\r\n        for(loopcounter = 0; loopcounter < headersize; loopcounter++)\r\n        {\r\n          hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];\r\n        }\r\n        /* Check if the header size is modulo 16 */\r\n        if ((headersize % 16) != 0)\r\n        {\r\n          /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */\r\n          for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)\r\n          {\r\n            hcryp->Init.pScratch[loopcounter] = 0;\r\n          }\r\n          /* Set the header size to modulo 16 */\r\n          headersize = ((headersize/16) + 1) * 16;\r\n        }\r\n        /* Set the pointer headeraddr to hcryp->Init.pScratch */\r\n        headeraddr = (uint32_t)hcryp->Init.pScratch;\r\n      }\r\n      /*********************** Formatting the block B0 ************************/\r\n      if(headersize != 0)\r\n      {\r\n        blockb0[0] = 0x40;\r\n      }\r\n      /* Flags byte */\r\n      /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */\r\n      blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);\r\n      blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);\r\n      \r\n      for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)\r\n      {\r\n        blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];\r\n      }\r\n      for ( ; loopcounter < 13; loopcounter++)\r\n      {\r\n        blockb0[loopcounter+1] = 0;\r\n      }\r\n      \r\n      blockb0[14] = (Size >> 8);\r\n      blockb0[15] = (Size & 0xFF);\r\n      \r\n      /************************* Formatting the initial counter ***************/\r\n      /* Byte 0:\r\n         Bits 7 and 6 are reserved and shall be set to 0\r\n         Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter \r\n         blocks are distinct from B0\r\n         Bits 0, 1, and 2 contain the same encoding of q as in B0\r\n      */\r\n      ctr[0] = blockb0[0] & 0x07;\r\n      /* byte 1 to NonceSize is the IV (Nonce) */\r\n      for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)\r\n      {\r\n        ctr[loopcounter] = blockb0[loopcounter];\r\n      }\r\n      /* Set the LSB to 1 */\r\n      ctr[15] |= 0x01;\r\n      \r\n      /* Set the key */\r\n      CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES CCM mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);\r\n      \r\n      /* Set the Initialization Vector */\r\n      CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);\r\n      \r\n      /* Select init phase */\r\n      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);\r\n      \r\n      b0addr = (uint32_t)blockb0;\r\n      /* Write the blockb0 block in the IN FIFO */\r\n      hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n      b0addr+=4;\r\n      hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n      b0addr+=4;\r\n      hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n      b0addr+=4;\r\n      hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n      \r\n      /* Enable the CRYP peripheral */\r\n      __HAL_CRYP_ENABLE(hcryp);\r\n\r\n      /* Get tick */\r\n      tickstart = HAL_GetTick();\r\n\r\n      while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r\n      {\r\n        /* Check for the Timeout */\r\n        if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n          \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n      /***************************** Header phase *****************************/\r\n      if(headersize != 0)\r\n      {\r\n        /* Select header phase */\r\n        __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);\r\n        \r\n        /* Enable Crypto processor */\r\n        __HAL_CRYP_ENABLE(hcryp);\r\n        \r\n        for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)\r\n        {\r\n         /* Get tick */\r\n         tickstart = HAL_GetTick();\r\n\r\n          while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))\r\n          {\r\n            /* Check for the Timeout */\r\n            if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r\n            {\r\n              /* Change state */\r\n              hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n              \r\n              /* Process Unlocked */\r\n              __HAL_UNLOCK(hcryp);\r\n              \r\n              return HAL_TIMEOUT;\r\n            }\r\n          }\r\n          /* Write the header block in the IN FIFO */\r\n          hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n          headeraddr+=4;\r\n          hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n          headeraddr+=4;\r\n          hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n          headeraddr+=4;\r\n          hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n          headeraddr+=4;\r\n        }\r\n\r\n        /* Get tick */\r\n        tickstart = HAL_GetTick();\r\n\r\n        while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)\r\n        {\r\n          /* Check for the Timeout */\r\n          if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r\n          {\r\n            /* Change state */\r\n            hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n            \r\n            /* Process Unlocked */\r\n            __HAL_UNLOCK(hcryp);\r\n            \r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n      }\r\n      /* Save formatted counter into the scratch buffer pScratch */\r\n      for(loopcounter = 0; (loopcounter < 16); loopcounter++)\r\n      {\r\n        hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];\r\n      }\r\n      /* Reset bit 0 */\r\n      hcryp->Init.pScratch[15] &= 0xfe;\r\n      /* Select payload phase once the header phase is performed */\r\n      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n      /* Set the phase */\r\n      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n    \r\n    /* Enable Interrupts */\r\n    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);\r\n    \r\n    /* Enable the CRYP peripheral */\r\n    __HAL_CRYP_ENABLE(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))\r\n  {\r\n    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;\r\n    /* Write the Input block in the IN FIFO */\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);\r\n    inputaddr+=4;\r\n    hcryp->Instance->DR = *(uint32_t*)(inputaddr);\r\n    hcryp->pCrypInBuffPtr += 16;\r\n    hcryp->CrypInCount -= 16;\r\n    if(hcryp->CrypInCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);\r\n      /* Call the Input data transfer complete callback */\r\n      HAL_CRYP_InCpltCallback(hcryp);\r\n    }\r\n  }\r\n  else if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))\r\n  {\r\n    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;\r\n    hcryp->pCrypOutBuffPtr += 16;\r\n    hcryp->CrypOutCount -= 16;\r\n    if(hcryp->CrypOutCount == 0)\r\n    {\r\n      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hcryp);\r\n      /* Change the CRYP peripheral state */\r\n      hcryp->State = HAL_CRYP_STATE_READY;\r\n      /* Call Input transfer complete callback */\r\n      HAL_CRYP_OutCpltCallback(hcryp);\r\n    }\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES GCM encryption mode using DMA.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 16\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t tickstart = 0;\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pPlainData;\r\n    outputaddr = (uint32_t)pCypherData;\r\n    \r\n    /* Change the CRYP peripheral state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {\r\n      /* Set the key */\r\n      CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES GCM mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT);\r\n      \r\n      /* Set the Initialization Vector */\r\n      CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n      /* Enable CRYP to start the init phase */\r\n      __HAL_CRYP_ENABLE(hcryp);\r\n      \r\n      /* Get tick */\r\n      tickstart = HAL_GetTick();\r\n\r\n      while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r\n      {\r\n        /* Check for the Timeout */\r\n        if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n          \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n      /* Set the header phase */\r\n      if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n      /* Disable the CRYP peripheral */\r\n      __HAL_CRYP_DISABLE(hcryp);\r\n      \r\n      /* Select payload phase once the header phase is performed */\r\n      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n      /* Set the phase */\r\n      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n    \r\n    /* Set the input and output addresses and start DMA transfer */ \r\n    CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n    \r\n    /* Unlock process */\r\n    __HAL_UNLOCK(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES CCM encryption mode using interrupt.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 16\r\n  * @param  pCypherData: Pointer to the cyphertext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  uint32_t headersize;\r\n  uint32_t headeraddr;\r\n  uint32_t loopcounter = 0;\r\n  uint32_t bufferidx = 0;\r\n  uint8_t blockb0[16] = {0};/* Block B0 */\r\n  uint8_t ctr[16] = {0}; /* Counter */\r\n  uint32_t b0addr = (uint32_t)blockb0;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pPlainData;\r\n    outputaddr = (uint32_t)pCypherData;\r\n    \r\n    headersize = hcryp->Init.HeaderSize;\r\n    headeraddr = (uint32_t)hcryp->Init.Header;\r\n    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pPlainData;\r\n    hcryp->pCrypOutBuffPtr = pCypherData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP peripheral state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {\r\n      /************************ Formatting the header block *******************/\r\n      if(headersize != 0)\r\n      {\r\n        /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */\r\n        if(headersize < 65280)\r\n        {\r\n          hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFFU);\r\n          hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU);\r\n          headersize += 2;\r\n        }\r\n        else\r\n        {\r\n          /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */\r\n          hcryp->Init.pScratch[bufferidx++] = 0xFFU;\r\n          hcryp->Init.pScratch[bufferidx++] = 0xFEU;\r\n          hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;\r\n          hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;\r\n          hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;\r\n          hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;\r\n          headersize += 6;\r\n        }\r\n        /* Copy the header buffer in internal buffer \"hcryp->Init.pScratch\" */\r\n        for(loopcounter = 0; loopcounter < headersize; loopcounter++)\r\n        {\r\n          hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];\r\n        }\r\n        /* Check if the header size is modulo 16 */\r\n        if ((headersize % 16) != 0)\r\n        {\r\n          /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */\r\n          for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)\r\n          {\r\n            hcryp->Init.pScratch[loopcounter] = 0;\r\n          }\r\n          /* Set the header size to modulo 16 */\r\n          headersize = ((headersize/16) + 1) * 16;\r\n        }\r\n        /* Set the pointer headeraddr to hcryp->Init.pScratch */\r\n        headeraddr = (uint32_t)hcryp->Init.pScratch;\r\n      }\r\n      /*********************** Formatting the block B0 ************************/\r\n      if(headersize != 0)\r\n      {\r\n        blockb0[0] = 0x40;\r\n      }\r\n      /* Flags byte */\r\n      /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */\r\n      blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);\r\n      blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);\r\n      \r\n      for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)\r\n      {\r\n        blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];\r\n      }\r\n      for ( ; loopcounter < 13; loopcounter++)\r\n      {\r\n        blockb0[loopcounter+1] = 0;\r\n      }\r\n      \r\n      blockb0[14] = (Size >> 8);\r\n      blockb0[15] = (Size & 0xFF);\r\n      \r\n      /************************* Formatting the initial counter ***************/\r\n      /* Byte 0:\r\n         Bits 7 and 6 are reserved and shall be set to 0\r\n         Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter \r\n         blocks are distinct from B0\r\n         Bits 0, 1, and 2 contain the same encoding of q as in B0\r\n      */\r\n      ctr[0] = blockb0[0] & 0x07;\r\n      /* byte 1 to NonceSize is the IV (Nonce) */\r\n      for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)\r\n      {\r\n        ctr[loopcounter] = blockb0[loopcounter];\r\n      }\r\n      /* Set the LSB to 1 */\r\n      ctr[15] |= 0x01;\r\n      \r\n      /* Set the key */\r\n      CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES CCM mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT);\r\n      \r\n      /* Set the Initialization Vector */\r\n      CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);\r\n      \r\n      /* Select init phase */\r\n      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);\r\n      \r\n      b0addr = (uint32_t)blockb0;\r\n      /* Write the blockb0 block in the IN FIFO */\r\n      hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n      b0addr+=4;\r\n      hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n      b0addr+=4;\r\n      hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n      b0addr+=4;\r\n      hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n      \r\n      /* Enable the CRYP peripheral */\r\n      __HAL_CRYP_ENABLE(hcryp);\r\n      \r\n      /* Get tick */\r\n      tickstart = HAL_GetTick();\r\n \r\n      while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r\n      {\r\n        /* Check for the Timeout */\r\n        if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n          \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n      /***************************** Header phase *****************************/\r\n      if(headersize != 0)\r\n      {\r\n        /* Select header phase */\r\n        __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);\r\n        \r\n        /* Enable Crypto processor */\r\n        __HAL_CRYP_ENABLE(hcryp);\r\n        \r\n        for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)\r\n        {\r\n         /* Get tick */\r\n         tickstart = HAL_GetTick();\r\n\r\n          while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))\r\n          {\r\n            /* Check for the Timeout */\r\n            if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r\n            {\r\n              /* Change state */\r\n              hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n              \r\n              /* Process Unlocked */\r\n              __HAL_UNLOCK(hcryp);\r\n              \r\n              return HAL_TIMEOUT;\r\n            }\r\n          }\r\n          /* Write the header block in the IN FIFO */\r\n          hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n          headeraddr+=4;\r\n          hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n          headeraddr+=4;\r\n          hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n          headeraddr+=4;\r\n          hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n          headeraddr+=4;\r\n        }\r\n        \r\n        /* Get tick */\r\n        tickstart = HAL_GetTick();\r\n\r\n        while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)\r\n        {\r\n          /* Check for the Timeout */\r\n          if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r\n          {\r\n            /* Change state */\r\n            hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n            \r\n            /* Process Unlocked */\r\n            __HAL_UNLOCK(hcryp);\r\n            \r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n      }\r\n      /* Save formatted counter into the scratch buffer pScratch */\r\n      for(loopcounter = 0; (loopcounter < 16); loopcounter++)\r\n      {\r\n        hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];\r\n      }\r\n      /* Reset bit 0 */\r\n      hcryp->Init.pScratch[15] &= 0xfe;\r\n      \r\n      /* Select payload phase once the header phase is performed */\r\n      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n      /* Set the phase */\r\n      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n    \r\n    /* Set the input and output addresses and start DMA transfer */ \r\n    CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n    \r\n    /* Unlock process */\r\n    __HAL_UNLOCK(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES GCM decryption mode using DMA.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData: Pointer to the cyphertext buffer.\r\n  * @param  Size: Length of the cyphertext buffer, must be a multiple of 16\r\n  * @param  pPlainData: Pointer to the plaintext buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pCypherData;\r\n    outputaddr = (uint32_t)pPlainData;\r\n    \r\n    /* Change the CRYP peripheral state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {\r\n      /* Set the key */\r\n      CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES GCM decryption mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_GCM_DECRYPT);\r\n      \r\n      /* Set the Initialization Vector */\r\n      CRYPEx_GCMCCM_SetInitVector(hcryp, hcryp->Init.pInitVect);\r\n      \r\n      /* Enable CRYP to start the init phase */\r\n      __HAL_CRYP_ENABLE(hcryp);\r\n      \r\n      /* Get tick */\r\n      tickstart = HAL_GetTick();\r\n\r\n      while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r\n      {\r\n        /* Check for the Timeout */\r\n        if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n          \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n      \r\n      /* Set the header phase */\r\n      if(CRYPEx_GCMCCM_SetHeaderPhase(hcryp, hcryp->Init.Header, hcryp->Init.HeaderSize, 1) != HAL_OK)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n      /* Disable the CRYP peripheral */\r\n      __HAL_CRYP_DISABLE(hcryp);\r\n      \r\n      /* Select payload phase once the header phase is performed */\r\n      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r\n      \r\n      /* Set the phase */\r\n      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n    \r\n    /* Set the input and output addresses and start DMA transfer */ \r\n    CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n    \r\n    /* Unlock process */\r\n    __HAL_UNLOCK(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the CRYP peripheral in AES CCM decryption mode using DMA\r\n  *         then decrypted pCypherData. The cypher data are available in pPlainData.\r\n  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @param  pCypherData: Pointer to the cyphertext buffer  \r\n  * @param  Size: Length of the plaintext buffer, must be a multiple of 16\r\n  * @param  pPlainData: Pointer to the plaintext buffer  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  uint32_t headersize;\r\n  uint32_t headeraddr;\r\n  uint32_t loopcounter = 0;\r\n  uint32_t bufferidx = 0;\r\n  uint8_t blockb0[16] = {0};/* Block B0 */\r\n  uint8_t ctr[16] = {0}; /* Counter */\r\n  uint32_t b0addr = (uint32_t)blockb0;\r\n  \r\n  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hcryp);\r\n    \r\n    inputaddr  = (uint32_t)pCypherData;\r\n    outputaddr = (uint32_t)pPlainData;\r\n    \r\n    headersize = hcryp->Init.HeaderSize;\r\n    headeraddr = (uint32_t)hcryp->Init.Header;\r\n    \r\n    hcryp->CrypInCount = Size;\r\n    hcryp->pCrypInBuffPtr = pCypherData;\r\n    hcryp->pCrypOutBuffPtr = pPlainData;\r\n    hcryp->CrypOutCount = Size;\r\n    \r\n    /* Change the CRYP peripheral state */\r\n    hcryp->State = HAL_CRYP_STATE_BUSY;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hcryp->Phase == HAL_CRYP_PHASE_READY)\r\n    {\r\n      /************************ Formatting the header block *******************/\r\n      if(headersize != 0)\r\n      {\r\n        /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */\r\n        if(headersize < 65280)\r\n        {\r\n          hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFFU);\r\n          hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU);\r\n          headersize += 2;\r\n        }\r\n        else\r\n        {\r\n          /* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */\r\n          hcryp->Init.pScratch[bufferidx++] = 0xFFU;\r\n          hcryp->Init.pScratch[bufferidx++] = 0xFEU;\r\n          hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;\r\n          hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;\r\n          hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;\r\n          hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;\r\n          headersize += 6;\r\n        }\r\n        /* Copy the header buffer in internal buffer \"hcryp->Init.pScratch\" */\r\n        for(loopcounter = 0; loopcounter < headersize; loopcounter++)\r\n        {\r\n          hcryp->Init.pScratch[bufferidx++] = hcryp->Init.Header[loopcounter];\r\n        }\r\n        /* Check if the header size is modulo 16 */\r\n        if ((headersize % 16) != 0)\r\n        {\r\n          /* Padd the header buffer with 0s till the hcryp->Init.pScratch length is modulo 16 */\r\n          for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++)\r\n          {\r\n            hcryp->Init.pScratch[loopcounter] = 0;\r\n          }\r\n          /* Set the header size to modulo 16 */\r\n          headersize = ((headersize/16) + 1) * 16;\r\n        }\r\n        /* Set the pointer headeraddr to hcryp->Init.pScratch */\r\n        headeraddr = (uint32_t)hcryp->Init.pScratch;\r\n      }\r\n      /*********************** Formatting the block B0 ************************/\r\n      if(headersize != 0)\r\n      {\r\n        blockb0[0] = 0x40;\r\n      }\r\n      /* Flags byte */\r\n      /* blockb0[0] |= 0u | (((( (uint8_t) hcryp->Init.TagSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - hcryp->Init.IVSize) - 1) & 0x07) */\r\n      blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)(((uint8_t)(hcryp->Init.TagSize - (uint8_t)(2))) >> 1) & (uint8_t)0x07 ) << 3);\r\n      blockb0[0] |= (uint8_t)((uint8_t)((uint8_t)((uint8_t)(15) - hcryp->Init.IVSize) - (uint8_t)1) & (uint8_t)0x07);\r\n      \r\n      for (loopcounter = 0; loopcounter < hcryp->Init.IVSize; loopcounter++)\r\n      {\r\n        blockb0[loopcounter+1] = hcryp->Init.pInitVect[loopcounter];\r\n      }\r\n      for ( ; loopcounter < 13; loopcounter++)\r\n      {\r\n        blockb0[loopcounter+1] = 0;\r\n      }\r\n      \r\n      blockb0[14] = (Size >> 8);\r\n      blockb0[15] = (Size & 0xFF);\r\n      \r\n      /************************* Formatting the initial counter ***************/\r\n      /* Byte 0:\r\n         Bits 7 and 6 are reserved and shall be set to 0\r\n         Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter \r\n         blocks are distinct from B0\r\n         Bits 0, 1, and 2 contain the same encoding of q as in B0\r\n      */\r\n      ctr[0] = blockb0[0] & 0x07;\r\n      /* byte 1 to NonceSize is the IV (Nonce) */\r\n      for(loopcounter = 1; loopcounter < hcryp->Init.IVSize + 1; loopcounter++)\r\n      {\r\n        ctr[loopcounter] = blockb0[loopcounter];\r\n      }\r\n      /* Set the LSB to 1 */\r\n      ctr[15] |= 0x01;\r\n      \r\n      /* Set the key */\r\n      CRYPEx_GCMCCM_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);\r\n      \r\n      /* Set the CRYP peripheral in AES CCM mode */\r\n      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CCM_DECRYPT);\r\n      \r\n      /* Set the Initialization Vector */\r\n      CRYPEx_GCMCCM_SetInitVector(hcryp, ctr);\r\n      \r\n      /* Select init phase */\r\n      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);\r\n      \r\n      b0addr = (uint32_t)blockb0;\r\n      /* Write the blockb0 block in the IN FIFO */\r\n      hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n      b0addr+=4;\r\n      hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n      b0addr+=4;\r\n      hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n      b0addr+=4;\r\n      hcryp->Instance->DR = *(uint32_t*)(b0addr);\r\n      \r\n      /* Enable the CRYP peripheral */\r\n      __HAL_CRYP_ENABLE(hcryp);\r\n      \r\n      /* Get tick */\r\n      tickstart = HAL_GetTick();\r\n \r\n      while((CRYP->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)\r\n      {\r\n        /* Check for the Timeout */\r\n        \r\n        if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r\n        {\r\n          /* Change state */\r\n          hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hcryp);\r\n          \r\n          return HAL_TIMEOUT;\r\n          \r\n        }\r\n      }\r\n      /***************************** Header phase *****************************/\r\n      if(headersize != 0)\r\n      {\r\n        /* Select header phase */\r\n        __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);\r\n        \r\n        /* Enable Crypto processor */\r\n        __HAL_CRYP_ENABLE(hcryp);\r\n        \r\n        for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16)\r\n        {\r\n         /* Get tick */\r\n         tickstart = HAL_GetTick();\r\n \r\n          while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))\r\n          {\r\n            /* Check for the Timeout */\r\n            if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r\n            {\r\n              /* Change state */\r\n              hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n              \r\n              /* Process Unlocked */\r\n              __HAL_UNLOCK(hcryp);\r\n              \r\n              return HAL_TIMEOUT;\r\n            }\r\n          }\r\n          /* Write the header block in the IN FIFO */\r\n          hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n          headeraddr+=4;\r\n          hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n          headeraddr+=4;\r\n          hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n          headeraddr+=4;\r\n          hcryp->Instance->DR = *(uint32_t*)(headeraddr);\r\n          headeraddr+=4;\r\n        }\r\n        \r\n        /* Get tick */\r\n        tickstart = HAL_GetTick();\r\n\r\n        while((hcryp->Instance->SR & CRYP_FLAG_BUSY) == CRYP_FLAG_BUSY)\r\n        {\r\n          /* Check for the Timeout */\r\n          if((HAL_GetTick() - tickstart ) > CRYPEx_TIMEOUT_VALUE)\r\n          {\r\n            /* Change state */\r\n            hcryp->State = HAL_CRYP_STATE_TIMEOUT;\r\n            \r\n            /* Process Unlocked */\r\n            __HAL_UNLOCK(hcryp);\r\n            \r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n      }\r\n      /* Save formatted counter into the scratch buffer pScratch */\r\n      for(loopcounter = 0; (loopcounter < 16); loopcounter++)\r\n      {\r\n        hcryp->Init.pScratch[loopcounter] = ctr[loopcounter];\r\n      }\r\n      /* Reset bit 0 */\r\n      hcryp->Init.pScratch[15] &= 0xfe;\r\n      /* Select payload phase once the header phase is performed */\r\n      __HAL_CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);\r\n      \r\n      /* Flush FIFO */\r\n      __HAL_CRYP_FIFO_FLUSH(hcryp);\r\n      \r\n      /* Set the phase */\r\n      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;\r\n    }\r\n    /* Set the input and output addresses and start DMA transfer */ \r\n    CRYPEx_GCMCCM_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);\r\n    \r\n    /* Unlock process */\r\n    __HAL_UNLOCK(hcryp);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;   \r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup CRYPEx_Exported_Functions_Group2 CRYPEx IRQ handler management  \r\n *  @brief   CRYPEx IRQ handler.\r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                ##### CRYPEx IRQ handler management #####\r\n  ==============================================================================  \r\n[..]  This section provides CRYPEx IRQ handler function.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  This function handles CRYPEx interrupt request.\r\n  * @param  hcryp: pointer to a CRYPEx_HandleTypeDef structure that contains\r\n  *         the configuration information for CRYP module\r\n  * @retval None\r\n  */\r\nvoid HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp)\r\n{\r\n  switch(CRYP->CR & CRYP_CR_ALGOMODE_DIRECTION)\r\n  {    \r\n  case CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT:\r\n    HAL_CRYPEx_AESGCM_Encrypt_IT(hcryp, NULL, 0, NULL);\r\n    break;\r\n    \r\n  case CRYP_CR_ALGOMODE_AES_GCM_DECRYPT:\r\n    HAL_CRYPEx_AESGCM_Decrypt_IT(hcryp, NULL, 0, NULL);\r\n    break;\r\n    \r\n  case CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT:\r\n    HAL_CRYPEx_AESCCM_Encrypt_IT(hcryp, NULL, 0, NULL);\r\n    break;\r\n    \r\n  case CRYP_CR_ALGOMODE_AES_CCM_DECRYPT:\r\n    HAL_CRYPEx_AESCCM_Decrypt_IT(hcryp, NULL, 0, NULL);\r\n    break;\r\n    \r\n  default:\r\n    break;\r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n#endif /* HAL_CRYP_MODULE_ENABLED */\r\n\r\n/**\r\n  * @}\r\n  */\r\n#endif /* STM32F756xx || STM32F777xx || STM32F779xx */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_dac.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   DAC HAL module driver.\r\n  *         This file provides firmware functions to manage the following \r\n  *         functionalities of the Digital to Analog Converter (DAC) peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + IO operation functions\r\n  *           + Peripheral Control functions\r\n  *           + Peripheral State and Errors functions      \r\n  *     \r\n  *\r\n  @verbatim      \r\n  ==============================================================================\r\n                      ##### DAC Peripheral features #####\r\n  ==============================================================================\r\n    [..]        \r\n      *** DAC Channels ***\r\n      ====================  \r\n    [..]  \r\n    The device integrates two 12-bit Digital Analog Converters that can \r\n    be used independently or simultaneously (dual mode):\r\n      (#) DAC channel1 with DAC_OUT1 (PA4) as output\r\n      (#) DAC channel2 with DAC_OUT2 (PA5) as output\r\n      \r\n      *** DAC Triggers ***\r\n      ====================\r\n    [..]\r\n    Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE\r\n    and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register. \r\n    [..] \r\n    Digital to Analog conversion can be triggered by:\r\n      (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_TRIGGER_EXT_IT9.\r\n          The used pin (GPIOx_Pin9) must be configured in input mode.\r\n  \r\n      (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8 \r\n          (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...)\r\n  \r\n      (#) Software using DAC_TRIGGER_SOFTWARE\r\n  \r\n      *** DAC Buffer mode feature ***\r\n      =============================== \r\n      [..] \r\n      Each DAC channel integrates an output buffer that can be used to \r\n      reduce the output impedance, and to drive external loads directly\r\n      without having to add an external operational amplifier.\r\n      To enable, the output buffer use  \r\n      sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;\r\n      [..]           \r\n      (@) Refer to the device datasheet for more details about output \r\n          impedance value with and without output buffer.\r\n            \r\n       *** DAC wave generation feature ***\r\n       =================================== \r\n       [..]     \r\n       Both DAC channels can be used to generate\r\n         (#) Noise wave using HAL_DACEx_NoiseWaveGenerate() \r\n         (#) Triangle wave using HAL_DACEx_TriangleWaveGenerate()\r\n            \r\n       *** DAC data format ***\r\n       =======================\r\n       [..]   \r\n       The DAC data format can be:\r\n         (#) 8-bit right alignment using DAC_ALIGN_8B_R\r\n         (#) 12-bit left alignment using DAC_ALIGN_12B_L\r\n         (#) 12-bit right alignment using DAC_ALIGN_12B_R\r\n  \r\n       *** DAC data value to voltage correspondence ***  \r\n       ================================================ \r\n       [..] \r\n       The analog output voltage on each DAC channel pin is determined\r\n       by the following equation: \r\n       DAC_OUTx = VREF+ * DOR / 4095\r\n       with  DOR is the Data Output Register\r\n          VEF+ is the input voltage reference (refer to the device datasheet)\r\n        e.g. To set DAC_OUT1 to 0.7V, use\r\n          Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V\r\n  \r\n       *** DMA requests  ***\r\n       =====================\r\n       [..]    \r\n       A DMA1 request can be generated when an external trigger (but not\r\n       a software trigger) occurs if DMA1 requests are enabled using\r\n       HAL_DAC_Start_DMA()\r\n       [..]\r\n       DMA1 requests are mapped as following:\r\n         (#) DAC channel1 : mapped on DMA1 Stream5 channel7 which must be \r\n             already configured\r\n         (#) DAC channel2 : mapped on DMA1 Stream6 channel7 which must be \r\n             already configured\r\n       \r\n    -@- For Dual mode and specific signal (Triangle and noise) generation please \r\n        refer to Extension Features Driver description        \r\n  \r\n      \r\n                      ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]          \r\n      (+) DAC APB clock must be enabled to get write access to DAC\r\n          registers using HAL_DAC_Init()\r\n      (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.\r\n      (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.\r\n      (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions\r\n\r\n     *** Polling mode IO operation ***\r\n     =================================\r\n     [..]    \r\n       (+) Start the DAC peripheral using HAL_DAC_Start() \r\n       (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.\r\n       (+) Stop the DAC peripheral using HAL_DAC_Stop()\r\n\r\n\t   \r\n     *** DMA mode IO operation ***    \r\n     ==============================\r\n     [..]    \r\n       (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length \r\n           of data to be transferred at each end of conversion \r\n       (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2()  \r\n           function is executed and user can add his own code by customization of function pointer \r\n           HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2\r\n       (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can \r\n            add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1\r\n       (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()\r\n\r\n                    \r\n     *** DAC HAL driver macros list ***\r\n     ============================================= \r\n     [..]\r\n       Below the list of most used macros in DAC HAL driver.\r\n       \r\n      (+) __HAL_DAC_ENABLE : Enable the DAC peripheral\r\n      (+) __HAL_DAC_DISABLE : Disable the DAC peripheral\r\n      (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags\r\n      (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status\r\n      \r\n     [..]\r\n      (@) You can refer to the DAC HAL driver header file for more useful macros  \r\n   \r\n @endverbatim    \r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup DAC DAC\r\n  * @brief DAC driver modules\r\n  * @{\r\n  */ \r\n\r\n#ifdef HAL_DAC_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @addtogroup DAC_Private_Functions\r\n  * @{\r\n  */\r\n/* Private function prototypes -----------------------------------------------*/\r\nstatic void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);\r\nstatic void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);\r\nstatic void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); \r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup DAC_Exported_Functions DAC Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions \r\n *  @brief    Initialization and Configuration functions \r\n *\r\n@verbatim    \r\n  ==============================================================================\r\n              ##### Initialization and de-initialization functions #####\r\n  ==============================================================================\r\n    [..]  This section provides functions allowing to:\r\n      (+) Initialize and configure the DAC. \r\n      (+) De-initialize the DAC. \r\n         \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the DAC peripheral according to the specified parameters\r\n  *         in the DAC_InitStruct.\r\n  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified DAC.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)\r\n{ \r\n  /* Check DAC handle */\r\n  if(hdac == NULL)\r\n  {\r\n     return HAL_ERROR;\r\n  }\r\n  /* Check the parameters */\r\n  assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));\r\n  \r\n  if(hdac->State == HAL_DAC_STATE_RESET)\r\n  { \r\n    /* Allocate lock resource and initialize it */\r\n    hdac->Lock = HAL_UNLOCKED; \r\n    /* Init the low level hardware */\r\n    HAL_DAC_MspInit(hdac);\r\n  }\r\n  \r\n  /* Initialize the DAC state*/\r\n  hdac->State = HAL_DAC_STATE_BUSY;\r\n  \r\n  /* Set DAC error code to none */\r\n  hdac->ErrorCode = HAL_DAC_ERROR_NONE;\r\n  \r\n  /* Initialize the DAC state*/\r\n  hdac->State = HAL_DAC_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Deinitializes the DAC peripheral registers to their default reset values.\r\n  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified DAC.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)\r\n{\r\n  /* Check DAC handle */\r\n  if(hdac == NULL)\r\n  {\r\n     return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));\r\n\r\n  /* Change DAC state */\r\n  hdac->State = HAL_DAC_STATE_BUSY;\r\n\r\n  /* DeInit the low level hardware */\r\n  HAL_DAC_MspDeInit(hdac);\r\n\r\n  /* Set DAC error code to none */\r\n  hdac->ErrorCode = HAL_DAC_ERROR_NONE;\r\n\r\n  /* Change DAC state */\r\n  hdac->State = HAL_DAC_STATE_RESET;\r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hdac);\r\n\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the DAC MSP.\r\n  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified DAC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdac);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_DAC_MspInit could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the DAC MSP.\r\n  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified DAC.  \r\n  * @retval None\r\n  */\r\n__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdac);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_DAC_MspDeInit could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DAC_Exported_Functions_Group2 IO operation functions\r\n *  @brief    IO operation functions \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n             ##### IO operation functions #####\r\n  ==============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Start conversion.\r\n      (+) Stop conversion.\r\n      (+) Start conversion and enable DMA transfer.\r\n      (+) Stop conversion and disable DMA transfer.\r\n      (+) Get result of conversion.\r\n                     \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Enables DAC and starts conversion of channel.\r\n  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified DAC.\r\n  * @param  Channel: The selected DAC channel. \r\n  *          This parameter can be one of the following values:\r\n  *            @arg DAC_CHANNEL_1: DAC Channel1 selected\r\n  *            @arg DAC_CHANNEL_2: DAC Channel2 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)\r\n{\r\n  uint32_t tmp1 = 0, tmp2 = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_DAC_CHANNEL(Channel));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hdac);\r\n  \r\n  /* Change DAC state */\r\n  hdac->State = HAL_DAC_STATE_BUSY;\r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_DAC_ENABLE(hdac, Channel);\r\n  \r\n  if(Channel == DAC_CHANNEL_1)\r\n  {\r\n    tmp1 = hdac->Instance->CR & DAC_CR_TEN1;\r\n    tmp2 = hdac->Instance->CR & DAC_CR_TSEL1;\r\n    /* Check if software trigger enabled */\r\n    if((tmp1 ==  DAC_CR_TEN1) && (tmp2 ==  DAC_CR_TSEL1))\r\n    {\r\n      /* Enable the selected DAC software conversion */\r\n      hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1;\r\n    }\r\n  }\r\n  else\r\n  {\r\n    tmp1 = hdac->Instance->CR & DAC_CR_TEN2;\r\n    tmp2 = hdac->Instance->CR & DAC_CR_TSEL2;    \r\n    /* Check if software trigger enabled */\r\n    if((tmp1 == DAC_CR_TEN2) && (tmp2 == DAC_CR_TSEL2))\r\n    {\r\n      /* Enable the selected DAC software conversion*/\r\n      hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG2;\r\n    }\r\n  }\r\n  \r\n  /* Change DAC state */\r\n  hdac->State = HAL_DAC_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdac);\r\n    \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Disables DAC and stop conversion of channel.\r\n  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified DAC.\r\n  * @param  Channel: The selected DAC channel. \r\n  *          This parameter can be one of the following values:\r\n  *            @arg DAC_CHANNEL_1: DAC Channel1 selected\r\n  *            @arg DAC_CHANNEL_2: DAC Channel2 selected  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_DAC_CHANNEL(Channel));\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_DAC_DISABLE(hdac, Channel);\r\n  \r\n  /* Change DAC state */\r\n  hdac->State = HAL_DAC_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Enables DAC and starts conversion of channel.\r\n  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified DAC.\r\n  * @param  Channel: The selected DAC channel. \r\n  *          This parameter can be one of the following values:\r\n  *            @arg DAC_CHANNEL_1: DAC Channel1 selected\r\n  *            @arg DAC_CHANNEL_2: DAC Channel2 selected\r\n  * @param  pData: The destination peripheral Buffer address.\r\n  * @param  Length: The length of data to be transferred from memory to DAC peripheral\r\n  * @param  Alignment: Specifies the data alignment for DAC channel.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected\r\n  *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected\r\n  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)\r\n{\r\n  uint32_t tmpreg = 0;\r\n    \r\n  /* Check the parameters */\r\n  assert_param(IS_DAC_CHANNEL(Channel));\r\n  assert_param(IS_DAC_ALIGN(Alignment));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hdac);\r\n  \r\n  /* Change DAC state */\r\n  hdac->State = HAL_DAC_STATE_BUSY;\r\n\r\n  if(Channel == DAC_CHANNEL_1)\r\n  {\r\n    /* Set the DMA transfer complete callback for channel1 */\r\n    hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;\r\n\r\n    /* Set the DMA half transfer complete callback for channel1 */\r\n    hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;\r\n\r\n    /* Set the DMA error callback for channel1 */\r\n    hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;\r\n\r\n    /* Enable the selected DAC channel1 DMA request */\r\n    hdac->Instance->CR |= DAC_CR_DMAEN1;\r\n    \r\n    /* Case of use of channel 1 */\r\n    switch(Alignment)\r\n    {\r\n      case DAC_ALIGN_12B_R:\r\n        /* Get DHR12R1 address */\r\n        tmpreg = (uint32_t)&hdac->Instance->DHR12R1;\r\n        break;\r\n      case DAC_ALIGN_12B_L:\r\n        /* Get DHR12L1 address */\r\n        tmpreg = (uint32_t)&hdac->Instance->DHR12L1;\r\n        break;\r\n      case DAC_ALIGN_8B_R:\r\n        /* Get DHR8R1 address */\r\n        tmpreg = (uint32_t)&hdac->Instance->DHR8R1;\r\n        break;\r\n      default:\r\n        break;\r\n    }\r\n  }\r\n  else\r\n  {\r\n    /* Set the DMA transfer complete callback for channel2 */\r\n    hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;\r\n\r\n    /* Set the DMA half transfer complete callback for channel2 */\r\n    hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;\r\n\r\n    /* Set the DMA error callback for channel2 */\r\n    hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;\r\n\r\n    /* Enable the selected DAC channel2 DMA request */\r\n    hdac->Instance->CR |= DAC_CR_DMAEN2;\r\n\r\n    /* Case of use of channel 2 */\r\n    switch(Alignment)\r\n    {\r\n      case DAC_ALIGN_12B_R:\r\n        /* Get DHR12R2 address */\r\n        tmpreg = (uint32_t)&hdac->Instance->DHR12R2;\r\n        break;\r\n      case DAC_ALIGN_12B_L:\r\n        /* Get DHR12L2 address */\r\n        tmpreg = (uint32_t)&hdac->Instance->DHR12L2;\r\n        break;\r\n      case DAC_ALIGN_8B_R:\r\n        /* Get DHR8R2 address */\r\n        tmpreg = (uint32_t)&hdac->Instance->DHR8R2;\r\n        break;\r\n      default:\r\n        break;\r\n    }\r\n  }\r\n  \r\n  /* Enable the DMA Stream */\r\n  if(Channel == DAC_CHANNEL_1)\r\n  {\r\n    /* Enable the DAC DMA underrun interrupt */\r\n    __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);\r\n    \r\n    /* Enable the DMA Stream */\r\n    HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);\r\n  } \r\n  else\r\n  {\r\n    /* Enable the DAC DMA underrun interrupt */\r\n    __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);\r\n    \r\n    /* Enable the DMA Stream */\r\n    HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);\r\n  }\r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_DAC_ENABLE(hdac, Channel);\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hdac);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Disables DAC and stop conversion of channel.\r\n  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified DAC.\r\n  * @param  Channel: The selected DAC channel. \r\n  *          This parameter can be one of the following values:\r\n  *            @arg DAC_CHANNEL_1: DAC Channel1 selected\r\n  *            @arg DAC_CHANNEL_2: DAC Channel2 selected   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_DAC_CHANNEL(Channel));\r\n  \r\n  /* Disable the selected DAC channel DMA request */\r\n   hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);\r\n    \r\n  /* Disable the Peripheral */\r\n  __HAL_DAC_DISABLE(hdac, Channel);\r\n  \r\n  /* Disable the DMA Channel */\r\n  /* Channel1 is used */\r\n  if(Channel == DAC_CHANNEL_1)\r\n  { \r\n    status = HAL_DMA_Abort(hdac->DMA_Handle1);\r\n  }\r\n  else /* Channel2 is used for */\r\n  { \r\n    status = HAL_DMA_Abort(hdac->DMA_Handle2); \r\n  }\r\n\r\n  /* Check if DMA Channel effectively disabled */\r\n  if(status != HAL_OK)\r\n  {\r\n    /* Update DAC state machine to error */\r\n    hdac->State = HAL_DAC_STATE_ERROR;      \r\n  }\r\n  else\r\n  {\r\n    /* Change DAC state */\r\n    hdac->State = HAL_DAC_STATE_READY;\r\n  }\r\n\r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the last data output value of the selected DAC channel.\r\n  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified DAC.\r\n  * @param  Channel: The selected DAC channel. \r\n  *          This parameter can be one of the following values:\r\n  *            @arg DAC_CHANNEL_1: DAC Channel1 selected\r\n  *            @arg DAC_CHANNEL_2: DAC Channel2 selected\r\n  * @retval The selected DAC channel data output value.\r\n  */\r\nuint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_DAC_CHANNEL(Channel));\r\n  \r\n  /* Returns the DAC channel data output register value */\r\n  if(Channel == DAC_CHANNEL_1)\r\n  {\r\n    return hdac->Instance->DOR1;\r\n  }\r\n  else\r\n  {\r\n    return hdac->Instance->DOR2;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Handles DAC interrupt request  \r\n  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified DAC.\r\n  * @retval None\r\n  */\r\nvoid HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)\r\n{\r\n  /* Check underrun channel 1 flag */\r\n  if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))\r\n  {\r\n    /* Change DAC state to error state */\r\n    hdac->State = HAL_DAC_STATE_ERROR;\r\n    \r\n    /* Set DAC error code to channel1 DMA underrun error */\r\n    hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;\r\n    \r\n    /* Clear the underrun flag */\r\n    __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);\r\n    \r\n    /* Disable the selected DAC channel1 DMA request */\r\n    hdac->Instance->CR &= ~DAC_CR_DMAEN1;\r\n    \r\n    /* Error callback */ \r\n    HAL_DAC_DMAUnderrunCallbackCh1(hdac);\r\n  }\r\n  /* Check underrun channel 2 flag */\r\n  if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))\r\n  {\r\n    /* Change DAC state to error state */\r\n    hdac->State = HAL_DAC_STATE_ERROR;\r\n    \r\n    /* Set DAC error code to channel2 DMA underrun error */\r\n    hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2;\r\n    \r\n    /* Clear the underrun flag */\r\n    __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);\r\n    \r\n    /* Disable the selected DAC channel1 DMA request */\r\n    hdac->Instance->CR &= ~DAC_CR_DMAEN2;\r\n    \r\n    /* Error callback */ \r\n    HAL_DACEx_DMAUnderrunCallbackCh2(hdac);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Conversion complete callback in non blocking mode for Channel1 \r\n  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified DAC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdac);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_DAC_ConvCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Conversion half DMA transfer callback in non blocking mode for Channel1 \r\n  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified DAC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdac);\r\n   \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Error DAC callback for Channel1.\r\n  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified DAC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdac);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DMA underrun DAC callback for channel1.\r\n  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified DAC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdac);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions\r\n *  @brief   \tPeripheral Control functions \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n             ##### Peripheral Control functions #####\r\n  ==============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Configure channels. \r\n      (+) Set the specified data holding register value for DAC channel.\r\n      \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Configures the selected DAC channel.\r\n  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified DAC.\r\n  * @param  sConfig: DAC configuration structure.\r\n  * @param  Channel: The selected DAC channel. \r\n  *          This parameter can be one of the following values:\r\n  *            @arg DAC_CHANNEL_1: DAC Channel1 selected\r\n  *            @arg DAC_CHANNEL_2: DAC Channel2 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)\r\n{\r\n  uint32_t tmpreg1 = 0, tmpreg2 = 0;\r\n\r\n  /* Check the DAC parameters */\r\n  assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));\r\n  assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));\r\n  assert_param(IS_DAC_CHANNEL(Channel));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hdac);\r\n  \r\n  /* Change DAC state */\r\n  hdac->State = HAL_DAC_STATE_BUSY;\r\n  \r\n  /* Get the DAC CR value */\r\n  tmpreg1 = hdac->Instance->CR;\r\n  /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */\r\n  tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);\r\n  /* Configure for the selected DAC channel: buffer output, trigger */\r\n  /* Set TSELx and TENx bits according to DAC_Trigger value */\r\n  /* Set BOFFx bit according to DAC_OutputBuffer value */   \r\n  tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);\r\n  /* Calculate CR register value depending on DAC_Channel */\r\n  tmpreg1 |= tmpreg2 << Channel;\r\n  /* Write to DAC CR */\r\n  hdac->Instance->CR = tmpreg1;\r\n  /* Disable wave generation */\r\n  hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);\r\n  \r\n  /* Change DAC state */\r\n  hdac->State = HAL_DAC_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdac);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Set the specified data holding register value for DAC channel.\r\n  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified DAC.\r\n  * @param  Channel: The selected DAC channel. \r\n  *          This parameter can be one of the following values:\r\n  *            @arg DAC_CHANNEL_1: DAC Channel1 selected\r\n  *            @arg DAC_CHANNEL_2: DAC Channel2 selected  \r\n  * @param  Alignment: Specifies the data alignment.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected\r\n  *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected\r\n  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected\r\n  * @param  Data: Data to be loaded in the selected data holding register.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)\r\n{  \r\n  __IO uint32_t tmp = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_DAC_CHANNEL(Channel));\r\n  assert_param(IS_DAC_ALIGN(Alignment));\r\n  assert_param(IS_DAC_DATA(Data));\r\n  \r\n  tmp = (uint32_t)hdac->Instance; \r\n  if(Channel == DAC_CHANNEL_1)\r\n  {\r\n    tmp += DAC_DHR12R1_ALIGNMENT(Alignment);\r\n  }\r\n  else\r\n  {\r\n    tmp += DAC_DHR12R2_ALIGNMENT(Alignment);\r\n  }\r\n\r\n  /* Set the DAC channel1 selected data holding register */\r\n  *(__IO uint32_t *) tmp = Data;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions\r\n *  @brief   Peripheral State and Errors functions \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n            ##### Peripheral State and Errors functions #####\r\n  ==============================================================================  \r\n    [..]\r\n    This subsection provides functions allowing to\r\n      (+) Check the DAC state.\r\n      (+) Check the DAC Errors.\r\n        \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  return the DAC state\r\n  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified DAC.\r\n  * @retval HAL state\r\n  */\r\nHAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)\r\n{\r\n  /* Return DAC state */\r\n  return hdac->State;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Return the DAC error code\r\n  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified DAC.\r\n  * @retval DAC Error Code\r\n  */\r\nuint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)\r\n{\r\n  return hdac->ErrorCode;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @brief  DMA conversion complete callback. \r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)   \r\n{\r\n  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  \r\n  HAL_DAC_ConvCpltCallbackCh1(hdac); \r\n  \r\n  hdac->State= HAL_DAC_STATE_READY;\r\n}\r\n\r\n/**\r\n  * @brief  DMA half transfer complete callback. \r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)   \r\n{\r\n    DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n    /* Conversion complete callback */\r\n    HAL_DAC_ConvHalfCpltCallbackCh1(hdac); \r\n}\r\n\r\n/**\r\n  * @brief  DMA error callback \r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)   \r\n{\r\n  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n    \r\n  /* Set DAC error code to DMA error */\r\n  hdac->ErrorCode |= HAL_DAC_ERROR_DMA;\r\n    \r\n  HAL_DAC_ErrorCallbackCh1(hdac); \r\n    \r\n  hdac->State= HAL_DAC_STATE_READY;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_DAC_MODULE_ENABLED */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_dac_ex.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Extended DAC HAL module driver.\r\n  *         This file provides firmware functions to manage the following \r\n  *         functionalities of DAC extension peripheral:\r\n  *           + Extended features functions\r\n  *     \r\n  *\r\n  @verbatim      \r\n  ==============================================================================\r\n                      ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]          \r\n      (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) :\r\n          Use HAL_DACEx_DualGetValue() to get digital data to be converted and use\r\n          HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.  \r\n      (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.\r\n      (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.\r\n   \r\n @endverbatim    \r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup DACEx DACEx\r\n  * @brief DAC driver modules\r\n  * @{\r\n  */ \r\n\r\n#ifdef HAL_DAC_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup DACEx_Exported_Functions DAC Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup DACEx_Exported_Functions_Group1 Extended features functions\r\n *  @brief    Extended features functions \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                 ##### Extended features functions #####\r\n  ==============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Start conversion.\r\n      (+) Stop conversion.\r\n      (+) Start conversion and enable DMA transfer.\r\n      (+) Stop conversion and disable DMA transfer.\r\n      (+) Get result of conversion.\r\n      (+) Get result of dual mode conversion.\r\n                     \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Returns the last data output value of the selected DAC channel.\r\n  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified DAC.\r\n  * @retval The selected DAC channel data output value.\r\n  */\r\nuint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)\r\n{\r\n  uint32_t tmp = 0;\r\n  \r\n  tmp |= hdac->Instance->DOR1;\r\n  \r\n  tmp |= hdac->Instance->DOR2 << 16;\r\n  \r\n  /* Returns the DAC channel data output register value */\r\n  return tmp;\r\n}\r\n\r\n/**\r\n  * @brief  Enables or disables the selected DAC channel wave generation.\r\n  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified DAC.\r\n  * @param  Channel: The selected DAC channel. \r\n  *          This parameter can be one of the following values:\r\n  *            @arg DAC_CHANNEL_1: DAC Channel1 selected \r\n  *            @arg DAC_CHANNEL_2: DAC Channel2 selected\r\n  * @param  Amplitude: Select max triangle amplitude. \r\n  *          This parameter can be one of the following values:\r\n  *            @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1\r\n  *            @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3\r\n  *            @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7\r\n  *            @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15\r\n  *            @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31\r\n  *            @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63\r\n  *            @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127\r\n  *            @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255\r\n  *            @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511\r\n  *            @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023\r\n  *            @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047\r\n  *            @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095                               \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)\r\n{  \r\n  /* Check the parameters */\r\n  assert_param(IS_DAC_CHANNEL(Channel));\r\n  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hdac);\r\n  \r\n  /* Change DAC state */\r\n  hdac->State = HAL_DAC_STATE_BUSY;\r\n  \r\n  /* Enable the selected wave generation for the selected DAC channel */\r\n  MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);\r\n\r\n  /* Change DAC state */\r\n  hdac->State = HAL_DAC_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdac);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Enables or disables the selected DAC channel wave generation.\r\n  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified DAC. \r\n  * @param  Channel: The selected DAC channel. \r\n  *          This parameter can be one of the following values:\r\n  *            @arg DAC_CHANNEL_1: DAC Channel1 selected \r\n  *            @arg DAC_CHANNEL_2: DAC Channel2 selected\r\n  * @param  Amplitude: Unmask DAC channel LFSR for noise wave generation. \r\n  *          This parameter can be one of the following values: \r\n  *            @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation\r\n  *            @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation  \r\n  *            @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation\r\n  *            @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation \r\n  *            @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation \r\n  *            @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation \r\n  *            @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation \r\n  *            @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation \r\n  *            @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation \r\n  *            @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation \r\n  *            @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation \r\n  *            @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)\r\n{  \r\n  /* Check the parameters */\r\n  assert_param(IS_DAC_CHANNEL(Channel));\r\n  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hdac);\r\n  \r\n  /* Change DAC state */\r\n  hdac->State = HAL_DAC_STATE_BUSY;\r\n  \r\n  /* Enable the selected wave generation for the selected DAC channel */\r\n  MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);\r\n  \r\n  /* Change DAC state */\r\n  hdac->State = HAL_DAC_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdac);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Set the specified data holding register value for dual DAC channel.\r\n  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified DAC.\r\n  * @param  Alignment: Specifies the data alignment for dual channel DAC.\r\n  *          This parameter can be one of the following values:\r\n  *            DAC_ALIGN_8B_R: 8bit right data alignment selected\r\n  *            DAC_ALIGN_12B_L: 12bit left data alignment selected\r\n  *            DAC_ALIGN_12B_R: 12bit right data alignment selected\r\n  * @param  Data1: Data for DAC Channel2 to be loaded in the selected data holding register.\r\n  * @param  Data2: Data for DAC Channel1 to be loaded in the selected data  holding register.\r\n  * @note   In dual mode, a unique register access is required to write in both\r\n  *          DAC channels at the same time.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)\r\n{  \r\n  uint32_t data = 0, tmp = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_DAC_ALIGN(Alignment));\r\n  assert_param(IS_DAC_DATA(Data1));\r\n  assert_param(IS_DAC_DATA(Data2));\r\n  \r\n  /* Calculate and set dual DAC data holding register value */\r\n  if (Alignment == DAC_ALIGN_8B_R)\r\n  {\r\n    data = ((uint32_t)Data2 << 8) | Data1; \r\n  }\r\n  else\r\n  {\r\n    data = ((uint32_t)Data2 << 16) | Data1;\r\n  }\r\n  \r\n  tmp = (uint32_t)hdac->Instance;\r\n  tmp += DAC_DHR12RD_ALIGNMENT(Alignment);\r\n\r\n  /* Set the dual DAC selected data holding register */\r\n  *(__IO uint32_t *)tmp = data;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @brief  Conversion complete callback in non blocking mode for Channel2 \r\n  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified DAC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdac);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_DAC_ConvCpltCallbackCh2 could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Conversion half DMA transfer callback in non blocking mode for Channel2 \r\n  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified DAC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdac);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Error DAC callback for Channel2.\r\n  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified DAC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdac);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DMA underrun DAC callback for channel2.\r\n  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains\r\n  *         the configuration information for the specified DAC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdac);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DMA conversion complete callback. \r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nvoid DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)   \r\n{\r\n  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  \r\n  HAL_DACEx_ConvCpltCallbackCh2(hdac); \r\n  \r\n  hdac->State= HAL_DAC_STATE_READY;\r\n}\r\n\r\n/**\r\n  * @brief  DMA half transfer complete callback. \r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nvoid DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)   \r\n{\r\n    DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n    /* Conversion complete callback */\r\n    HAL_DACEx_ConvHalfCpltCallbackCh2(hdac); \r\n}\r\n\r\n/**\r\n  * @brief  DMA error callback \r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nvoid DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)   \r\n{\r\n  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n    \r\n  /* Set DAC error code to DMA error */\r\n  hdac->ErrorCode |= HAL_DAC_ERROR_DMA;\r\n    \r\n  HAL_DACEx_ErrorCallbackCh2(hdac); \r\n    \r\n  hdac->State= HAL_DAC_STATE_READY;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_DAC_MODULE_ENABLED */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dcmi.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_dcmi.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   DCMI HAL module driver\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the Digital Camera Interface (DCMI) peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + IO operation functions\r\n  *           + Peripheral Control functions \r\n  *           + Peripheral State and Error functions  \r\n  *           \r\n  @verbatim\r\n  ==============================================================================\r\n                        ##### How to use this driver #####\r\n  ==============================================================================\r\n  [..]\r\n      The sequence below describes how to use this driver to capture image\r\n      from a camera module connected to the DCMI Interface.\r\n      This sequence does not take into account the configuration of the\r\n      camera module, which should be made before to configure and enable\r\n      the DCMI to capture images.\r\n\r\n    (#) Program the required configuration through following parameters:\r\n        horizontal and vertical polarity, pixel clock polarity, Capture Rate,\r\n        Synchronization Mode, code of the frame delimiter and data width \r\n        using HAL_DCMI_Init() function.\r\n\r\n    (#) Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR\r\n        register to the destination memory buffer.\r\n\r\n    (#) Program the required configuration through following parameters:\r\n        DCMI mode, destination memory Buffer address and the data length \r\n        and enable capture using HAL_DCMI_Start_DMA() function.\r\n\r\n    (#) Optionally, configure and Enable the CROP feature to select a rectangular\r\n        window from the received image using HAL_DCMI_ConfigCrop() \r\n        and HAL_DCMI_EnableCROP() functions\r\n\r\n    (#) The capture can be stopped using HAL_DCMI_Stop() function.\r\n\r\n    (#) To control DCMI state you can use the function HAL_DCMI_GetState().\r\n\r\n     *** DCMI HAL driver macros list ***\r\n     ============================================= \r\n     [..]\r\n       Below the list of most used macros in DCMI HAL driver.\r\n       \r\n      (+) __HAL_DCMI_ENABLE: Enable the DCMI peripheral.\r\n      (+) __HAL_DCMI_DISABLE: Disable the DCMI peripheral.\r\n      (+) __HAL_DCMI_GET_FLAG: Get the DCMI pending flags.\r\n      (+) __HAL_DCMI_CLEAR_FLAG: Clear the DCMI pending flags.\r\n      (+) __HAL_DCMI_ENABLE_IT: Enable the specified DCMI interrupts.\r\n      (+) __HAL_DCMI_DISABLE_IT: Disable the specified DCMI interrupts.\r\n      (+) __HAL_DCMI_GET_IT_SOURCE: Check whether the specified DCMI interrupt has occurred or not.\r\n \r\n     [..] \r\n       (@) You can refer to the DCMI HAL driver header file for more useful macros\r\n      \r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n/** @defgroup DCMI DCMI\r\n  * @brief DCMI HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_DCMI_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n#define HAL_TIMEOUT_DCMI_STOP    ((uint32_t)1000) /* Set timeout to 1s  */\r\n\r\n#define DCMI_POSITION_CWSIZE_VLINE (uint32_t)POSITION_VAL(DCMI_CWSIZE_VLINE) /*!< Required left shift to set crop window vertical line count       */\r\n#define DCMI_POSITION_CWSTRT_VST   (uint32_t)POSITION_VAL(DCMI_CWSTRT_VST)   /*!< Required left shift to set crop window vertical start line count */\r\n\r\n#define DCMI_POSITION_ESCR_LSC     (uint32_t)POSITION_VAL(DCMI_ESCR_LSC)     /*!< Required left shift to set line start delimiter */\r\n#define DCMI_POSITION_ESCR_LEC     (uint32_t)POSITION_VAL(DCMI_ESCR_LEC)     /*!< Required left shift to set line end delimiter   */\r\n#define DCMI_POSITION_ESCR_FEC     (uint32_t)POSITION_VAL(DCMI_ESCR_FEC)     /*!< Required left shift to set frame end delimiter  */\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\nstatic void       DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma);\r\nstatic void       DCMI_DMAError(DMA_HandleTypeDef *hdma);\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @defgroup DCMI_Exported_Functions DCMI Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions\r\n *  @brief   Initialization and Configuration functions\r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                ##### Initialization and Configuration functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Initialize and configure the DCMI\r\n      (+) De-initialize the DCMI \r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @brief  Initializes the DCMI according to the specified\r\n  *         parameters in the DCMI_InitTypeDef and create the associated handle.\r\n  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r\n  *                the configuration information for DCMI.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)\r\n{     \r\n  /* Check the DCMI peripheral state */\r\n  if(hdcmi == NULL)\r\n  {\r\n     return HAL_ERROR;\r\n  }\r\n  \r\n  /* Check function parameters */\r\n  assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance));\r\n  assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity));\r\n  assert_param(IS_DCMI_VSPOLARITY(hdcmi->Init.VSPolarity));\r\n  assert_param(IS_DCMI_HSPOLARITY(hdcmi->Init.HSPolarity));\r\n  assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode));\r\n  assert_param(IS_DCMI_CAPTURE_RATE(hdcmi->Init.CaptureRate));\r\n  assert_param(IS_DCMI_EXTENDED_DATA(hdcmi->Init.ExtendedDataMode));\r\n  assert_param(IS_DCMI_MODE_JPEG(hdcmi->Init.JPEGMode));\r\n\r\n  assert_param(IS_DCMI_BYTE_SELECT_MODE(hdcmi->Init.ByteSelectMode));\r\n  assert_param(IS_DCMI_BYTE_SELECT_START(hdcmi->Init.ByteSelectStart));\r\n  assert_param(IS_DCMI_LINE_SELECT_MODE(hdcmi->Init.LineSelectMode));\r\n  assert_param(IS_DCMI_LINE_SELECT_START(hdcmi->Init.LineSelectStart));\r\n                \r\n  if(hdcmi->State == HAL_DCMI_STATE_RESET)\r\n  {\r\n    /* Init the low level hardware */\r\n    HAL_DCMI_MspInit(hdcmi);\r\n  } \r\n  \r\n  /* Change the DCMI state */\r\n  hdcmi->State = HAL_DCMI_STATE_BUSY; \r\n                          /* Configures the HS, VS, DE and PC polarity */\r\n  hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL  | DCMI_CR_VSPOL  | DCMI_CR_EDM_0 |\\\r\n                           DCMI_CR_EDM_1  | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG  |\\\r\n                           DCMI_CR_ESS | DCMI_CR_BSM_0 | DCMI_CR_BSM_1 | DCMI_CR_OEBS |\\\r\n                           DCMI_CR_LSM | DCMI_CR_OELS);\r\n\r\n  hdcmi->Instance->CR |=  (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate |\\\r\n                                     hdcmi->Init.VSPolarity  | hdcmi->Init.HSPolarity  |\\\r\n                                     hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode |\\\r\n                                     hdcmi->Init.JPEGMode | hdcmi->Init.ByteSelectMode |\\\r\n                                     hdcmi->Init.ByteSelectStart | hdcmi->Init.LineSelectMode |\\\r\n                                     hdcmi->Init.LineSelectStart);\r\n                                     \r\n  if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)\r\n  {\r\n    hdcmi->Instance->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode)    |\\\r\n                             ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << DCMI_POSITION_ESCR_LSC)|\\\r\n                             ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << DCMI_POSITION_ESCR_LEC) |\\\r\n                             ((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << DCMI_POSITION_ESCR_FEC));\r\n\r\n  }\r\n\r\n  /* Enable the Line, Vsync, Error and Overrun interrupts */\r\n  __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR);\r\n\r\n  /* Update error code */\r\n  hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;\r\n  \r\n  /* Initialize the DCMI state*/\r\n  hdcmi->State  = HAL_DCMI_STATE_READY;\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Deinitializes the DCMI peripheral registers to their default reset\r\n  *         values.\r\n  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r\n  *                the configuration information for DCMI.\r\n  * @retval HAL status\r\n  */\r\n\r\nHAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi)\r\n{\r\n  /* DeInit the low level hardware */\r\n  HAL_DCMI_MspDeInit(hdcmi);\r\n\r\n  /* Update error code */\r\n  hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;\r\n\r\n  /* Initialize the DCMI state*/\r\n  hdcmi->State = HAL_DCMI_STATE_RESET;\r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hdcmi);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the DCMI MSP.\r\n  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r\n  *                the configuration information for DCMI.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdcmi);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_DCMI_MspInit could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the DCMI MSP.\r\n  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r\n  *                the configuration information for DCMI.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdcmi);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_DCMI_MspDeInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n/** @defgroup DCMI_Exported_Functions_Group2 IO operation functions \r\n *  @brief   IO operation functions  \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                      #####  IO operation functions  #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Configure destination address and data length and \r\n          Enables DCMI DMA request and enables DCMI capture\r\n      (+) Stop the DCMI capture.\r\n      (+) Handles DCMI interrupt request.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Enables DCMI DMA request and enables DCMI capture  \r\n  * @param  hdcmi:     pointer to a DCMI_HandleTypeDef structure that contains\r\n  *                    the configuration information for DCMI.\r\n  * @param  DCMI_Mode: DCMI capture mode snapshot or continuous grab.\r\n  * @param  pData:     The destination memory Buffer address (LCD Frame buffer).\r\n  * @param  Length:    The length of capture to be transferred.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)\r\n{  \r\n  /* Initialize the second memory address */\r\n  uint32_t SecondMemAddress = 0;\r\n\r\n  /* Check function parameters */\r\n  assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode));\r\n\r\n  /* Process Locked */\r\n  __HAL_LOCK(hdcmi);\r\n  \r\n  /* Lock the DCMI peripheral state */\r\n  hdcmi->State = HAL_DCMI_STATE_BUSY;\r\n\r\n  /* Enable DCMI by setting DCMIEN bit */\r\n  __HAL_DCMI_ENABLE(hdcmi);\r\n  \r\n  /* Configure the DCMI Mode */\r\n  hdcmi->Instance->CR &= ~(DCMI_CR_CM);\r\n  hdcmi->Instance->CR |=  (uint32_t)(DCMI_Mode);\r\n\r\n  /* Set the DMA memory0 conversion complete callback */\r\n  hdcmi->DMA_Handle->XferCpltCallback = DCMI_DMAXferCplt;\r\n\r\n  /* Set the DMA error callback */\r\n  hdcmi->DMA_Handle->XferErrorCallback = DCMI_DMAError;\r\n\r\n  /* Set the dma abort callback */\r\n  hdcmi->DMA_Handle->XferAbortCallback = NULL;\r\n\r\n  /* Reset transfer counters value */ \r\n  hdcmi->XferCount = 0;\r\n  hdcmi->XferTransferNumber = 0;\r\n  \r\n  if(Length <= 0xFFFF)\r\n  {\r\n    /* Enable the DMA Stream */\r\n    HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, Length);\r\n  }\r\n  else /* DCMI_DOUBLE_BUFFER Mode */\r\n  {\r\n    /* Set the DMA memory1 conversion complete callback */\r\n    hdcmi->DMA_Handle->XferM1CpltCallback = DCMI_DMAXferCplt; \r\n\r\n    /* Initialize transfer parameters */\r\n    hdcmi->XferCount = 1;\r\n    hdcmi->XferSize = Length;\r\n    hdcmi->pBuffPtr = pData;\r\n      \r\n    /* Get the number of buffer */\r\n    while(hdcmi->XferSize > 0xFFFF)\r\n    {\r\n      hdcmi->XferSize = (hdcmi->XferSize/2);\r\n      hdcmi->XferCount = hdcmi->XferCount*2;\r\n    }\r\n\r\n    /* Update DCMI counter  and transfer number*/\r\n    hdcmi->XferCount = (hdcmi->XferCount - 2);\r\n    hdcmi->XferTransferNumber = hdcmi->XferCount;\r\n\r\n    /* Update second memory address */\r\n    SecondMemAddress = (uint32_t)(pData + (4*hdcmi->XferSize));\r\n\r\n    /* Start DMA multi buffer transfer */\r\n    HAL_DMAEx_MultiBufferStart_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, SecondMemAddress, hdcmi->XferSize);\r\n  }\r\n  \r\n  /* Enable Capture */\r\n  hdcmi->Instance->CR |= DCMI_CR_CAPTURE;\r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hdcmi);\r\n\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Disable DCMI DMA request and Disable DCMI capture  \r\n  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r\n  *                the configuration information for DCMI. \r\n  * @retval HAL status     \r\n  */\r\nHAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)\r\n{\r\n  register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock /8/1000);\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hdcmi);\r\n  \r\n  /* Lock the DCMI peripheral state */\r\n  hdcmi->State = HAL_DCMI_STATE_BUSY;\r\n\r\n  /* Disable Capture */\r\n  hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE);\r\n\r\n  /* Check if the DCMI capture effectively disabled */\r\n  do\r\n  {\r\n    if (count-- == 0)\r\n    {\r\n      /* Update error code */\r\n      hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;\r\n      \r\n      status = HAL_TIMEOUT;\r\n      break;\r\n    } \r\n  }\r\n  while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0);\r\n\r\n  /* Disable the DCMI */\r\n  __HAL_DCMI_DISABLE(hdcmi);\r\n\r\n  /* Disable the DMA */\r\n  HAL_DMA_Abort(hdcmi->DMA_Handle);\r\n\r\n  /* Update error code */\r\n  hdcmi->ErrorCode |= HAL_DCMI_ERROR_NONE;\r\n\r\n  /* Change DCMI state */\r\n  hdcmi->State = HAL_DCMI_STATE_READY;\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hdcmi);\r\n\r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Suspend DCMI capture  \r\n  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r\n  *                the configuration information for DCMI. \r\n  * @retval HAL status     \r\n  */\r\nHAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi)\r\n{\r\n  register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock /8/1000);\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hdcmi);\r\n\r\n  if(hdcmi->State == HAL_DCMI_STATE_BUSY)\r\n  {\r\n    /* Change DCMI state */\r\n    hdcmi->State = HAL_DCMI_STATE_SUSPENDED;\r\n\r\n    /* Disable Capture */\r\n    hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE);\r\n\r\n    /* Check if the DCMI capture effectively disabled */\r\n    do\r\n    {\r\n      if (count-- == 0)\r\n      {        \r\n        /* Update error code */\r\n        hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;\r\n        \r\n        /* Change DCMI state */\r\n        hdcmi->State = HAL_DCMI_STATE_READY;\r\n        \r\n        status = HAL_TIMEOUT;\r\n        break;\r\n      }\r\n    }\r\n    while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0);\r\n  }    \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hdcmi);\r\n  \r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Resume DCMI capture  \r\n  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r\n  *                the configuration information for DCMI. \r\n  * @retval HAL status     \r\n  */\r\nHAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hdcmi);\r\n  \r\n  if(hdcmi->State == HAL_DCMI_STATE_SUSPENDED)\r\n  {\r\n    /* Change DCMI state */\r\n    hdcmi->State = HAL_DCMI_STATE_BUSY;\r\n    \r\n    /* Disable Capture */\r\n    hdcmi->Instance->CR |= DCMI_CR_CAPTURE;\r\n  } \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hdcmi);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Handles DCMI interrupt request.\r\n  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r\n  *                the configuration information for the DCMI.\r\n  * @retval None\r\n  */\r\nvoid HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)\r\n{  \r\n  uint32_t isr_value = READ_REG(hdcmi->Instance->MISR);\r\n  \r\n  /* Synchronization error interrupt management *******************************/\r\n  if((isr_value & DCMI_FLAG_ERRRI) == DCMI_FLAG_ERRRI)\r\n  {\r\n    /* Clear the Synchronization error flag */\r\n    __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_ERRRI);\r\n    \r\n    /* Update error code */\r\n    hdcmi->ErrorCode |= HAL_DCMI_ERROR_SYNC;\r\n    \r\n    /* Change DCMI state */\r\n    hdcmi->State = HAL_DCMI_STATE_ERROR;\r\n    \r\n    /* Set the synchronization error callback */\r\n    hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;\r\n    \r\n    /* Abort the DMA Transfer */\r\n    HAL_DMA_Abort_IT(hdcmi->DMA_Handle); \r\n  }\r\n  /* Overflow interrupt management ********************************************/\r\n  if((isr_value & DCMI_FLAG_OVRRI) == DCMI_FLAG_OVRRI)\r\n  {\r\n    /* Clear the Overflow flag */\r\n    __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_OVRRI);\r\n    \r\n    /* Update error code */\r\n    hdcmi->ErrorCode |= HAL_DCMI_ERROR_OVR;\r\n    \r\n    /* Change DCMI state */\r\n    hdcmi->State = HAL_DCMI_STATE_ERROR;\r\n    \r\n    /* Set the overflow callback */\r\n    hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;\r\n    \r\n    /* Abort the DMA Transfer */\r\n    HAL_DMA_Abort_IT(hdcmi->DMA_Handle);\r\n  }\r\n  /* Line Interrupt management ************************************************/\r\n  if((isr_value & DCMI_FLAG_LINERI) == DCMI_FLAG_LINERI)\r\n  {\r\n    /* Clear the Line interrupt flag */  \r\n    __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI);\r\n    \r\n    /* Line interrupt Callback */\r\n    HAL_DCMI_LineEventCallback(hdcmi);\r\n  }\r\n  /* VSYNC interrupt management ***********************************************/\r\n  if((isr_value & DCMI_FLAG_VSYNCRI) == DCMI_FLAG_VSYNCRI)\r\n  {\r\n    /* Clear the VSYNC flag */\r\n    __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI);\r\n    \r\n    /* VSYNC Callback */\r\n    HAL_DCMI_VsyncEventCallback(hdcmi);\r\n  }\r\n  /* FRAME interrupt management ***********************************************/\r\n  if((isr_value & DCMI_FLAG_FRAMERI) == DCMI_FLAG_FRAMERI)   \r\n  {\r\n    /* When snapshot mode, disable Vsync, Error and Overrun interrupts */\r\n    if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)\r\n    { \r\n      /* Disable the Line, Vsync, Error and Overrun interrupts */\r\n      __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR);\r\n    }\r\n    \r\n    /* Disable the Frame interrupt */\r\n    __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_FRAME);\r\n    \r\n    /* Clear the End of Frame flag */\r\n    __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_FRAMERI);\r\n    \r\n    /* Frame Callback */\r\n    HAL_DCMI_FrameEventCallback(hdcmi);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Error DCMI callback.\r\n  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r\n  *                the configuration information for DCMI.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdcmi);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_DCMI_ErrorCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Line Event callback.\r\n  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r\n  *                the configuration information for DCMI.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi)\r\n{\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_DCMI_LineEventCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  VSYNC Event callback.\r\n  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r\n  *                the configuration information for DCMI.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdcmi);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_DCMI_VsyncEventCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Frame Event callback.\r\n  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r\n  *                the configuration information for DCMI.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdcmi);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_DCMI_FrameEventCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DCMI_Exported_Functions_Group3 Peripheral Control functions\r\n *  @brief    Peripheral Control functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                    ##### Peripheral Control functions #####\r\n ===============================================================================  \r\n[..]  This section provides functions allowing to:\r\n      (+) Configure the CROP feature.\r\n      (+) Enable/Disable the CROP feature.\r\n      (+) Set embedded synchronization delimiters unmasks.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Configure the DCMI CROP coordinate.\r\n  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r\n  *                the configuration information for DCMI.\r\n  * @param  YSize: DCMI Line number\r\n  * @param  XSize: DCMI Pixel per line\r\n  * @param  X0:    DCMI window X offset\r\n  * @param  Y0:    DCMI window Y offset\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hdcmi);\r\n\r\n  /* Lock the DCMI peripheral state */\r\n  hdcmi->State = HAL_DCMI_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_DCMI_WINDOW_COORDINATE(X0));\r\n  assert_param(IS_DCMI_WINDOW_HEIGHT(Y0));\r\n  assert_param(IS_DCMI_WINDOW_COORDINATE(XSize));\r\n  assert_param(IS_DCMI_WINDOW_COORDINATE(YSize));\r\n\t\r\n  /* Configure CROP */\r\n  hdcmi->Instance->CWSIZER = (XSize | (YSize << DCMI_POSITION_CWSIZE_VLINE));\r\n  hdcmi->Instance->CWSTRTR = (X0 | (Y0 << DCMI_POSITION_CWSTRT_VST));\r\n\r\n  /* Initialize the DCMI state*/\r\n  hdcmi->State  = HAL_DCMI_STATE_READY;\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hdcmi);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Disable the Crop feature.\r\n  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r\n  *                the configuration information for DCMI.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hdcmi);\r\n\r\n  /* Lock the DCMI peripheral state */\r\n  hdcmi->State = HAL_DCMI_STATE_BUSY;\r\n\r\n  /* Disable DCMI Crop feature */\r\n  hdcmi->Instance->CR &= ~(uint32_t)DCMI_CR_CROP;  \r\n\r\n  /* Change the DCMI state*/\r\n  hdcmi->State = HAL_DCMI_STATE_READY;   \r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hdcmi);\r\n\r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Enable the Crop feature.\r\n  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r\n  *                the configuration information for DCMI.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hdcmi);\r\n\r\n  /* Lock the DCMI peripheral state */\r\n  hdcmi->State = HAL_DCMI_STATE_BUSY;\r\n\r\n  /* Enable DCMI Crop feature */\r\n  hdcmi->Instance->CR |= (uint32_t)DCMI_CR_CROP;\r\n\r\n  /* Change the DCMI state*/\r\n  hdcmi->State = HAL_DCMI_STATE_READY;\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hdcmi);\r\n\r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DCMI_Exported_Functions_Group4 Peripheral State functions\r\n *  @brief    Peripheral State functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n               ##### Peripheral State and Errors functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides functions allowing to\r\n      (+) Check the DCMI state.\r\n      (+) Get the specific DCMI error flag.  \r\n\r\n@endverbatim\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @brief  Return the DCMI state\r\n  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains\r\n  *                the configuration information for DCMI.\r\n  * @retval HAL state\r\n  */\r\nHAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi)  \r\n{\r\n  return hdcmi->State;\r\n}\r\n\r\n/**\r\n* @brief  Return the DCMI error code\r\n* @param  hdcmi : pointer to a DCMI_HandleTypeDef structure that contains\r\n  *               the configuration information for DCMI.\r\n* @retval DCMI Error Code\r\n*/\r\nuint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi)\r\n{\r\n  return hdcmi->ErrorCode;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup DCMI_Private_Functions DCMI Private Functions\r\n  * @{\r\n  */\r\n  /**\r\n  * @brief  DMA conversion complete callback. \r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  uint32_t tmp = 0;\r\n\r\n  DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n\r\n  if(hdcmi->XferCount != 0)\r\n  {\r\n    /* Update memory 0 address location */\r\n    tmp = ((hdcmi->DMA_Handle->Instance->CR) & DMA_SxCR_CT);\r\n    if(((hdcmi->XferCount % 2) == 0) && (tmp != 0))\r\n    {\r\n      tmp = hdcmi->DMA_Handle->Instance->M0AR;\r\n      HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8*hdcmi->XferSize)), MEMORY0);\r\n      hdcmi->XferCount--;\r\n    }\r\n    /* Update memory 1 address location */\r\n    else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0)\r\n    {\r\n      tmp = hdcmi->DMA_Handle->Instance->M1AR;\r\n      HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8*hdcmi->XferSize)), MEMORY1);\r\n      hdcmi->XferCount--;\r\n    }\r\n  }\r\n  /* Update memory 0 address location */\r\n  else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) != 0)\r\n  {\r\n    hdcmi->DMA_Handle->Instance->M0AR = hdcmi->pBuffPtr;\r\n  }\r\n  /* Update memory 1 address location */\r\n  else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0)\r\n  {\r\n    tmp = hdcmi->pBuffPtr;\r\n    hdcmi->DMA_Handle->Instance->M1AR = (tmp + (4*hdcmi->XferSize));\r\n    hdcmi->XferCount = hdcmi->XferTransferNumber;\r\n  }\r\n\r\n  /* Check if the frame is transferred */\r\n  if(hdcmi->XferCount == hdcmi->XferTransferNumber)\r\n  {\r\n    /* Enable the Frame interrupt */\r\n    __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME);\r\n    \r\n    /* When snapshot mode, set dcmi state to ready */\r\n    if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)\r\n    {  \r\n      hdcmi->State= HAL_DCMI_STATE_READY;\r\n    }\r\n  }  \r\n}\r\n\r\n/**\r\n  * @brief  DMA error callback \r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void DCMI_DMAError(DMA_HandleTypeDef *hdma)\r\n{\r\n  DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n \r\n  if(hdcmi->DMA_Handle->ErrorCode != HAL_DMA_ERROR_FE)\r\n  {\r\n    /* Initialize the DCMI state*/\r\n    hdcmi->State = HAL_DCMI_STATE_READY;\r\n    \r\n    /* Set DCMI Error Code */\r\n    hdcmi->ErrorCode |= HAL_DCMI_ERROR_DMA;\r\n  }\r\n\r\n  /* DCMI error Callback */  \r\n  HAL_DCMI_ErrorCallback(hdcmi);\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */\r\n#endif /* HAL_DCMI_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dcmi_ex.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_dcmi_ex.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Empty file; This file is no longer used to handle the Black&White\r\n  *          feature. Its content is now moved to common files\r\n  *          (stm32f7xx_hal_dcmi.c/.h) as there's no device's dependency within F7\r\n  *          family. It's just kept for compatibility reasons.\r\n  * \r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dfsdm.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_dfsdm.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   This file provides firmware functions to manage the following \r\n  *          functionalities of the Digital Filter for Sigma-Delta Modulators\r\n  *          (DFSDM) peripherals:\r\n  *           + Initialization and configuration of channels and filters\r\n  *           + Regular channels configuration\r\n  *           + Injected channels configuration\r\n  *           + Regular/Injected Channels DMA Configuration\r\n  *           + Interrupts and flags management\r\n  *           + Analog watchdog feature\r\n  *           + Short-circuit detector feature\r\n  *           + Extremes detector feature\r\n  *           + Clock absence detector feature\r\n  *           + Break generation on analog watchdog or short-circuit event\r\n  *         \r\n  @verbatim\r\n  ==============================================================================\r\n                     ##### How to use this driver #####\r\n  ==============================================================================\r\n  [..]\r\n    *** Channel initialization ***\r\n    ==============================\r\n    [..]\r\n      (#) User has first to initialize channels (before filters initialization).\r\n      (#) As prerequisite, fill in the HAL_DFSDM_ChannelMspInit() :\r\n        (++) Enable DFSDMz clock interface with __HAL_RCC_DFSDMz_CLK_ENABLE().\r\n        (++) Enable the clocks for the DFSDMz GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().\r\n        (++) Configure these DFSDMz pins in alternate mode using HAL_GPIO_Init().\r\n        (++) If interrupt mode is used, enable and configure DFSDMz_FLT0 global\r\n            interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().\r\n      (#) Configure the output clock, input, serial interface, analog watchdog,\r\n          offset and data right bit shift parameters for this channel using the \r\n          HAL_DFSDM_ChannelInit() function.\r\n\r\n    *** Channel clock absence detector ***\r\n    ======================================\r\n    [..]\r\n      (#) Start clock absence detector using HAL_DFSDM_ChannelCkabStart() or\r\n          HAL_DFSDM_ChannelCkabStart_IT().\r\n      (#) In polling mode, use HAL_DFSDM_ChannelPollForCkab() to detect the clock\r\n          absence.\r\n      (#) In interrupt mode, HAL_DFSDM_ChannelCkabCallback() will be called if\r\n          clock absence is detected.\r\n      (#) Stop clock absence detector using HAL_DFSDM_ChannelCkabStop() or\r\n          HAL_DFSDM_ChannelCkabStop_IT().\r\n      (#) Please note that the same mode (polling or interrupt) has to be used \r\n          for all channels because the channels are sharing the same interrupt.\r\n      (#) Please note also that in interrupt mode, if clock absence detector is\r\n          stopped for one channel, interrupt will be disabled for all channels.\r\n\r\n    *** Channel short circuit detector ***\r\n    ======================================\r\n    [..]    \r\n      (#) Start short circuit detector using HAL_DFSDM_ChannelScdStart() or\r\n          or HAL_DFSDM_ChannelScdStart_IT().\r\n      (#) In polling mode, use HAL_DFSDM_ChannelPollForScd() to detect short\r\n          circuit.\r\n      (#) In interrupt mode, HAL_DFSDM_ChannelScdCallback() will be called if \r\n          short circuit is detected.\r\n      (#) Stop short circuit detector using HAL_DFSDM_ChannelScdStop() or\r\n          or HAL_DFSDM_ChannelScdStop_IT().\r\n      (#) Please note that the same mode (polling or interrupt) has to be used \r\n          for all channels because the channels are sharing the same interrupt.\r\n      (#) Please note also that in interrupt mode, if short circuit detector is\r\n          stopped for one channel, interrupt will be disabled for all channels.\r\n\r\n    *** Channel analog watchdog value ***\r\n    =====================================\r\n    [..]    \r\n      (#) Get analog watchdog filter value of a channel using\r\n          HAL_DFSDM_ChannelGetAwdValue().\r\n\r\n    *** Channel offset value ***\r\n    =====================================\r\n    [..]    \r\n      (#) Modify offset value of a channel using HAL_DFSDM_ChannelModifyOffset().\r\n\r\n    *** Filter initialization ***\r\n    =============================\r\n    [..]\r\n      (#) After channel initialization, user has to init filters.\r\n      (#) As prerequisite, fill in the HAL_DFSDM_FilterMspInit() :\r\n        (++) If interrupt mode is used , enable and configure DFSDMz_FLTx global\r\n            interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().\r\n            Please note that DFSDMz_FLT0 global interrupt could be already\r\n            enabled if interrupt is used for channel.\r\n        (++) If DMA mode is used, configure DMA with HAL_DMA_Init() and link it\r\n            with DFSDMz filter handle using __HAL_LINKDMA().\r\n      (#) Configure the regular conversion, injected conversion and filter\r\n          parameters for this filter using the HAL_DFSDM_FilterInit() function.\r\n\r\n    *** Filter regular channel conversion ***\r\n    =========================================\r\n    [..]    \r\n      (#) Select regular channel and enable/disable continuous mode using\r\n          HAL_DFSDM_FilterConfigRegChannel().\r\n      (#) Start regular conversion using HAL_DFSDM_FilterRegularStart(),\r\n          HAL_DFSDM_FilterRegularStart_IT(), HAL_DFSDM_FilterRegularStart_DMA() or\r\n          HAL_DFSDM_FilterRegularMsbStart_DMA().\r\n      (#) In polling mode, use HAL_DFSDM_FilterPollForRegConversion() to detect \r\n          the end of regular conversion.\r\n      (#) In interrupt mode, HAL_DFSDM_FilterRegConvCpltCallback() will be called\r\n          at the end of regular conversion.\r\n      (#) Get value of regular conversion and corresponding channel using \r\n          HAL_DFSDM_FilterGetRegularValue().\r\n      (#) In DMA mode, HAL_DFSDM_FilterRegConvHalfCpltCallback() and \r\n          HAL_DFSDM_FilterRegConvCpltCallback() will be called respectively at the\r\n          half transfer and at the transfer complete. Please note that \r\n          HAL_DFSDM_FilterRegConvHalfCpltCallback() will be called only in DMA\r\n          circular mode.\r\n      (#) Stop regular conversion using HAL_DFSDM_FilterRegularStop(),\r\n          HAL_DFSDM_FilterRegularStop_IT() or HAL_DFSDM_FilterRegularStop_DMA().\r\n\r\n    *** Filter injected channels conversion ***\r\n    ===========================================\r\n    [..]\r\n      (#) Select injected channels using HAL_DFSDM_FilterConfigInjChannel().\r\n      (#) Start injected conversion using HAL_DFSDM_FilterInjectedStart(),\r\n          HAL_DFSDM_FilterInjectedStart_IT(), HAL_DFSDM_FilterInjectedStart_DMA() or\r\n          HAL_DFSDM_FilterInjectedMsbStart_DMA().\r\n      (#) In polling mode, use HAL_DFSDM_FilterPollForInjConversion() to detect \r\n          the end of injected conversion.\r\n      (#) In interrupt mode, HAL_DFSDM_FilterInjConvCpltCallback() will be called\r\n          at the end of injected conversion.\r\n      (#) Get value of injected conversion and corresponding channel using \r\n          HAL_DFSDM_FilterGetInjectedValue().\r\n      (#) In DMA mode, HAL_DFSDM_FilterInjConvHalfCpltCallback() and \r\n          HAL_DFSDM_FilterInjConvCpltCallback() will be called respectively at the\r\n          half transfer and at the transfer complete. Please note that \r\n          HAL_DFSDM_FilterInjConvCpltCallback() will be called only in DMA\r\n          circular mode.\r\n      (#) Stop injected conversion using HAL_DFSDM_FilterInjectedStop(),\r\n          HAL_DFSDM_FilterInjectedStop_IT() or HAL_DFSDM_FilterInjectedStop_DMA().\r\n\r\n    *** Filter analog watchdog ***\r\n    ==============================\r\n    [..]\r\n      (#) Start filter analog watchdog using HAL_DFSDM_FilterAwdStart_IT().\r\n      (#) HAL_DFSDM_FilterAwdCallback() will be called if analog watchdog occurs.\r\n      (#) Stop filter analog watchdog using HAL_DFSDM_FilterAwdStop_IT().\r\n\r\n    *** Filter extreme detector ***\r\n    ===============================\r\n    [..]\r\n      (#) Start filter extreme detector using HAL_DFSDM_FilterExdStart().\r\n      (#) Get extreme detector maximum value using HAL_DFSDM_FilterGetExdMaxValue().\r\n      (#) Get extreme detector minimum value using HAL_DFSDM_FilterGetExdMinValue().\r\n      (#) Start filter extreme detector using HAL_DFSDM_FilterExdStop().\r\n\r\n    *** Filter conversion time ***\r\n    ==============================\r\n    [..]\r\n      (#) Get conversion time value using HAL_DFSDM_FilterGetConvTimeValue().\r\n\r\n    @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n#ifdef HAL_DFSDM_MODULE_ENABLED\r\n#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r\n/** @defgroup DFSDM DFSDM\r\n  * @brief DFSDM HAL driver module\r\n  * @{\r\n  */ \r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @defgroup DFSDM_Private_Define DFSDM Private Define\r\n * @{\r\n */\r\n#define DFSDM_CHCFGR1_CLK_DIV_OFFSET POSITION_VAL(DFSDM_CHCFGR1_CKOUTDIV)\r\n#define DFSDM_CHAWSCDR_BKSCD_OFFSET     POSITION_VAL(DFSDM_CHAWSCDR_BKSCD)\r\n#define DFSDM_CHAWSCDR_FOSR_OFFSET      POSITION_VAL(DFSDM_CHAWSCDR_AWFOSR)\r\n#define DFSDM_CHCFGR2_OFFSET_OFFSET  POSITION_VAL(DFSDM_CHCFGR2_OFFSET)\r\n#define DFSDM_CHCFGR2_DTRBS_OFFSET   POSITION_VAL(DFSDM_CHCFGR2_DTRBS)\r\n#define DFSDM_FLTFCR_FOSR_OFFSET        POSITION_VAL(DFSDM_FLTFCR_FOSR)\r\n#define DFSDM_FLTCR1_MSB_RCH_OFFSET     8\r\n#define DFSDM_FLTCR2_EXCH_OFFSET        POSITION_VAL(DFSDM_FLTCR2_EXCH)\r\n#define DFSDM_FLTCR2_AWDCH_OFFSET       POSITION_VAL(DFSDM_FLTCR2_AWDCH)\r\n#define DFSDM_FLTISR_CKABF_OFFSET       POSITION_VAL(DFSDM_FLTISR_CKABF)\r\n#define DFSDM_FLTISR_SCDF_OFFSET        POSITION_VAL(DFSDM_FLTISR_SCDF)\r\n#define DFSDM_FLTICR_CLRCKABF_OFFSET    POSITION_VAL(DFSDM_FLTICR_CLRCKABF)\r\n#define DFSDM_FLTICR_CLRSCDF_OFFSET     POSITION_VAL(DFSDM_FLTICR_CLRSCSDF)\r\n#define DFSDM_FLTRDATAR_DATA_OFFSET     POSITION_VAL(DFSDM_FLTRDATAR_RDATA)\r\n#define DFSDM_FLTJDATAR_DATA_OFFSET     POSITION_VAL(DFSDM_FLTJDATAR_JDATA)\r\n#define DFSDM_FLTAWHTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWHTR_AWHT)\r\n#define DFSDM_FLTAWLTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWLTR_AWLT)\r\n#define DFSDM_FLTEXMAX_DATA_OFFSET      POSITION_VAL(DFSDM_FLTEXMAX_EXMAX)\r\n#define DFSDM_FLTEXMIN_DATA_OFFSET      POSITION_VAL(DFSDM_FLTEXMIN_EXMIN)\r\n#define DFSDM_FLTCNVTIMR_DATA_OFFSET    POSITION_VAL(DFSDM_FLTCNVTIMR_CNVCNT)\r\n#define DFSDM_FLTAWSR_HIGH_OFFSET       POSITION_VAL(DFSDM_FLTAWSR_AWHTF)\r\n#define DFSDM_MSB_MASK               0xFFFF0000U\r\n#define DFSDM_LSB_MASK               0x0000FFFFU\r\n#define DFSDM_CKAB_TIMEOUT           5000U\r\n#define DFSDM1_CHANNEL_NUMBER           8U\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @defgroup DFSDM_Private_Variables DFSDM Private Variables\r\n  * @{\r\n  */\r\n__IO uint32_t                v_dfsdm1ChannelCounter = 0;\r\nDFSDM_Channel_HandleTypeDef* a_dfsdm1ChannelHandle[DFSDM1_CHANNEL_NUMBER] = {NULL};\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private function prototypes -----------------------------------------------*/\r\n/** @defgroup DFSDM_Private_Functions DFSDM Private Functions\r\n  * @{\r\n  */\r\nstatic uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels);\r\nstatic uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance);\r\nstatic void     DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);\r\nstatic void     DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);\r\nstatic void     DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);\r\nstatic void     DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);\r\nstatic void     DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma);\r\nstatic void     DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma);\r\nstatic void     DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma);\r\nstatic void     DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma);\r\nstatic void     DFSDM_DMAError(DMA_HandleTypeDef *hdma);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup DFSDM_Exported_Functions DFSDM Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions\r\n *  @brief    Channel initialization and de-initialization functions \r\n *\r\n@verbatim\r\n  ==============================================================================\r\n        ##### Channel initialization and de-initialization functions #####\r\n  ==============================================================================\r\n    [..]  This section provides functions allowing to:\r\n      (+) Initialize the DFSDM channel.\r\n      (+) De-initialize the DFSDM channel.\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initialize the DFSDM channel according to the specified parameters\r\n  *         in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle.\r\n  * @param  hdfsdm_channel : DFSDM channel handle.\r\n  * @retval HAL status.\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r\n{\r\n  /* Check DFSDM Channel handle */\r\n  if(hdfsdm_channel == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r\n  assert_param(IS_FUNCTIONAL_STATE(hdfsdm_channel->Init.OutputClock.Activation));\r\n  assert_param(IS_DFSDM_CHANNEL_INPUT(hdfsdm_channel->Init.Input.Multiplexer));\r\n  assert_param(IS_DFSDM_CHANNEL_DATA_PACKING(hdfsdm_channel->Init.Input.DataPacking));\r\n  assert_param(IS_DFSDM_CHANNEL_INPUT_PINS(hdfsdm_channel->Init.Input.Pins));\r\n  assert_param(IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(hdfsdm_channel->Init.SerialInterface.Type));\r\n  assert_param(IS_DFSDM_CHANNEL_SPI_CLOCK(hdfsdm_channel->Init.SerialInterface.SpiClock));\r\n  assert_param(IS_DFSDM_CHANNEL_FILTER_ORDER(hdfsdm_channel->Init.Awd.FilterOrder));\r\n  assert_param(IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(hdfsdm_channel->Init.Awd.Oversampling));\r\n  assert_param(IS_DFSDM_CHANNEL_OFFSET(hdfsdm_channel->Init.Offset));\r\n  assert_param(IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(hdfsdm_channel->Init.RightBitShift));\r\n  \r\n  /* Check that channel has not been already initialized */\r\n  if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Call MSP init function */\r\n  HAL_DFSDM_ChannelMspInit(hdfsdm_channel);\r\n  \r\n  /* Update the channel counter */\r\n  v_dfsdm1ChannelCounter++;\r\n  \r\n  /* Configure output serial clock and enable global DFSDM interface only for first channel */\r\n  if(v_dfsdm1ChannelCounter == 1)\r\n  {\r\n    assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection));\r\n    /* Set the output serial clock source */\r\n    DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);\r\n    DFSDM1_Channel0->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection;\r\n    \r\n    /* Reset clock divider */\r\n    DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV);\r\n    if(hdfsdm_channel->Init.OutputClock.Activation == ENABLE)\r\n    {\r\n      assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider));\r\n      /* Set the output clock divider */\r\n      DFSDM1_Channel0->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1) << \r\n                                             DFSDM_CHCFGR1_CLK_DIV_OFFSET);\r\n    }\r\n    \r\n    /* enable the DFSDM global interface */\r\n    DFSDM1_Channel0->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;\r\n  }\r\n  \r\n  /* Set channel input parameters */\r\n  hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX | \r\n                                         DFSDM_CHCFGR1_CHINSEL);\r\n  hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer | \r\n                                        hdfsdm_channel->Init.Input.DataPacking | \r\n                                        hdfsdm_channel->Init.Input.Pins);\r\n  \r\n  /* Set serial interface parameters */\r\n  hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL);\r\n  hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type | \r\n                                        hdfsdm_channel->Init.SerialInterface.SpiClock);\r\n  \r\n  /* Set analog watchdog parameters */\r\n  hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);\r\n  hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder | \r\n                                       ((hdfsdm_channel->Init.Awd.Oversampling - 1) << DFSDM_CHAWSCDR_FOSR_OFFSET));\r\n\r\n  /* Set channel offset and right bit shift */\r\n  hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS);\r\n  hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_OFFSET) | \r\n                                        (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_OFFSET));\r\n\r\n  /* Enable DFSDM channel */\r\n  hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN;\r\n  \r\n  /* Set DFSDM Channel to ready state */\r\n  hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY;\r\n\r\n  /* Store channel handle in DFSDM channel handle table */\r\n  a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel;\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  De-initialize the DFSDM channel.\r\n  * @param  hdfsdm_channel : DFSDM channel handle.\r\n  * @retval HAL status.\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r\n{\r\n  /* Check DFSDM Channel handle */\r\n  if(hdfsdm_channel == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r\n  \r\n  /* Check that channel has not been already deinitialized */\r\n  if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Disable the DFSDM channel */\r\n  hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CHEN);\r\n  \r\n  /* Update the channel counter */\r\n  v_dfsdm1ChannelCounter--;\r\n  \r\n  /* Disable global DFSDM at deinit of last channel */\r\n  if(v_dfsdm1ChannelCounter == 0)\r\n  {\r\n    DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_DFSDMEN);\r\n  }\r\n\r\n  /* Call MSP deinit function */\r\n  HAL_DFSDM_ChannelMspDeInit(hdfsdm_channel);\r\n\r\n  /* Set DFSDM Channel in reset state */\r\n  hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_RESET;\r\n\r\n  /* Reset channel handle in DFSDM channel handle table */\r\n  a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = (DFSDM_Channel_HandleTypeDef *) NULL;\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initialize the DFSDM channel MSP.\r\n  * @param  hdfsdm_channel : DFSDM channel handle.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdfsdm_channel);\r\n  \r\n  /* NOTE : This function should not be modified, when the function is needed,\r\n            the HAL_DFSDM_ChannelMspInit could be implemented in the user file.\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  De-initialize the DFSDM channel MSP.\r\n  * @param  hdfsdm_channel : DFSDM channel handle.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdfsdm_channel);\r\n  \r\n  /* NOTE : This function should not be modified, when the function is needed,\r\n            the HAL_DFSDM_ChannelMspDeInit could be implemented in the user file.\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions\r\n *  @brief    Channel operation functions\r\n *\r\n@verbatim\r\n  ==============================================================================\r\n                   ##### Channel operation functions #####\r\n  ==============================================================================\r\n    [..]  This section provides functions allowing to:\r\n      (+) Manage clock absence detector feature.\r\n      (+) Manage short circuit detector feature.\r\n      (+) Get analog watchdog value.\r\n      (+) Modify offset value.\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  This function allows to start clock absence detection in polling mode.\r\n  * @note   Same mode has to be used for all channels.\r\n  * @note   If clock is not available on this channel during 5 seconds,\r\n  *         clock absence detection will not be activated and function\r\n  *         will return HAL_TIMEOUT error.\r\n  * @param  hdfsdm_channel : DFSDM channel handle.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  uint32_t channel;\r\n  uint32_t tickstart;\r\n\r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r\n  \r\n  /* Check DFSDM channel state */\r\n  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r\n  {\r\n    /* Return error status */\r\n    status = HAL_ERROR;\r\n  }\r\n  else\r\n  {\r\n    /* Get channel number from channel instance */\r\n    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);\r\n\r\n    /* Get timeout */\r\n    tickstart = HAL_GetTick();\r\n\r\n    /* Clear clock absence flag */\r\n    while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) != 0)\r\n    {\r\n      DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));\r\n\r\n      /* Check the Timeout */\r\n      if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)\r\n      {\r\n        /* Set timeout status */\r\n        status = HAL_TIMEOUT;\r\n        break;\r\n      }\r\n    }\r\n\r\n    if(status == HAL_OK)\r\n    {\r\n      /* Start clock absence detection */\r\n      hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;\r\n    }\r\n  }\r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to poll for the clock absence detection.\r\n  * @param  hdfsdm_channel : DFSDM channel handle.\r\n  * @param  Timeout : Timeout value in milliseconds.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, \r\n                                               uint32_t Timeout)\r\n{\r\n  uint32_t tickstart;\r\n  uint32_t channel;\r\n  \r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r\n\r\n  /* Check DFSDM channel state */\r\n  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r\n  {\r\n    /* Return error status */\r\n    return HAL_ERROR;\r\n  }\r\n  else\r\n  {\r\n    /* Get channel number from channel instance */\r\n    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);\r\n    \r\n    /* Get timeout */\r\n    tickstart = HAL_GetTick();\r\n\r\n    /* Wait clock absence detection */\r\n    while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) == 0)\r\n    {\r\n      /* Check the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))\r\n        {\r\n          /* Return timeout status */\r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n    \r\n    /* Clear clock absence detection flag */\r\n    DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to stop clock absence detection in polling mode.\r\n  * @param  hdfsdm_channel : DFSDM channel handle.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  uint32_t channel;\r\n\r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r\n  \r\n  /* Check DFSDM channel state */\r\n  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r\n  {\r\n    /* Return error status */\r\n    status = HAL_ERROR;\r\n  }\r\n  else\r\n  {\r\n    /* Stop clock absence detection */\r\n    hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);\r\n    \r\n    /* Clear clock absence flag */\r\n    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);\r\n    DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));\r\n  }\r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to start clock absence detection in interrupt mode.\r\n  * @note   Same mode has to be used for all channels.\r\n  * @note   If clock is not available on this channel during 5 seconds,\r\n  *         clock absence detection will not be activated and function\r\n  *         will return HAL_TIMEOUT error.\r\n  * @param  hdfsdm_channel : DFSDM channel handle.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  uint32_t channel;\r\n  uint32_t tickstart;\r\n\r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r\n  \r\n  /* Check DFSDM channel state */\r\n  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r\n  {\r\n    /* Return error status */\r\n    status = HAL_ERROR;\r\n  }\r\n  else\r\n  {\r\n    /* Get channel number from channel instance */\r\n    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);\r\n\r\n    /* Get timeout */\r\n    tickstart = HAL_GetTick();\r\n\r\n    /* Clear clock absence flag */\r\n    while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) != 0)\r\n    {\r\n      DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));\r\n\r\n      /* Check the Timeout */\r\n      if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)\r\n      {\r\n        /* Set timeout status */\r\n        status = HAL_TIMEOUT;\r\n        break;\r\n      }\r\n    }\r\n\r\n    if(status == HAL_OK)\r\n    {\r\n      /* Activate clock absence detection interrupt */\r\n      DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_CKABIE;\r\n\r\n      /* Start clock absence detection */\r\n      hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;\r\n    }\r\n  }\r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Clock absence detection callback. \r\n  * @param  hdfsdm_channel : DFSDM channel handle.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdfsdm_channel);\r\n  \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_DFSDM_ChannelCkabCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to stop clock absence detection in interrupt mode.\r\n  * @note   Interrupt will be disabled for all channels\r\n  * @param  hdfsdm_channel : DFSDM channel handle.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  uint32_t channel;\r\n\r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r\n  \r\n  /* Check DFSDM channel state */\r\n  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r\n  {\r\n    /* Return error status */\r\n    status = HAL_ERROR;\r\n  }\r\n  else\r\n  {\r\n    /* Stop clock absence detection */\r\n    hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);\r\n    \r\n    /* Clear clock absence flag */\r\n    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);\r\n    DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));\r\n\r\n    /* Disable clock absence detection interrupt */\r\n    DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE);\r\n  }\r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to start short circuit detection in polling mode.\r\n  * @note   Same mode has to be used for all channels\r\n  * @param  hdfsdm_channel : DFSDM channel handle.\r\n  * @param  Threshold : Short circuit detector threshold.\r\n  *         This parameter must be a number between Min_Data = 0 and Max_Data = 255.\r\n  * @param  BreakSignal : Break signals assigned to short circuit event.\r\n  *         This parameter can be a values combination of @ref DFSDM_BreakSignals.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,\r\n                                            uint32_t Threshold,\r\n                                            uint32_t BreakSignal)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r\n  assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));\r\n  assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));\r\n  \r\n  /* Check DFSDM channel state */\r\n  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r\n  {\r\n    /* Return error status */\r\n    status = HAL_ERROR;\r\n  }\r\n  else\r\n  {\r\n    /* Configure threshold and break signals */\r\n    hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);\r\n    hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_OFFSET) | \\\r\n                                         Threshold);\r\n    \r\n    /* Start short circuit detection */\r\n    hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;\r\n  }\r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to poll for the short circuit detection.\r\n  * @param  hdfsdm_channel : DFSDM channel handle.\r\n  * @param  Timeout : Timeout value in milliseconds.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, \r\n                                              uint32_t Timeout)\r\n{\r\n  uint32_t tickstart;\r\n  uint32_t channel;\r\n  \r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r\n\r\n  /* Check DFSDM channel state */\r\n  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r\n  {\r\n    /* Return error status */\r\n    return HAL_ERROR;\r\n  }\r\n  else\r\n  {\r\n    /* Get channel number from channel instance */\r\n    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);\r\n    \r\n    /* Get timeout */\r\n    tickstart = HAL_GetTick();\r\n\r\n    /* Wait short circuit detection */\r\n    while(((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_OFFSET + channel)) == 0)\r\n    {\r\n      /* Check the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))\r\n        {\r\n          /* Return timeout status */\r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n    \r\n    /* Clear short circuit detection flag */\r\n    DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to stop short circuit detection in polling mode.\r\n  * @param  hdfsdm_channel : DFSDM channel handle.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  uint32_t channel;\r\n\r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r\n  \r\n  /* Check DFSDM channel state */\r\n  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r\n  {\r\n    /* Return error status */\r\n    status = HAL_ERROR;\r\n  }\r\n  else\r\n  {\r\n    /* Stop short circuit detection */\r\n    hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);\r\n    \r\n    /* Clear short circuit detection flag */\r\n    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);\r\n    DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));\r\n  }\r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to start short circuit detection in interrupt mode.\r\n  * @note   Same mode has to be used for all channels\r\n  * @param  hdfsdm_channel : DFSDM channel handle.\r\n  * @param  Threshold : Short circuit detector threshold.\r\n  *         This parameter must be a number between Min_Data = 0 and Max_Data = 255.\r\n  * @param  BreakSignal : Break signals assigned to short circuit event.\r\n  *         This parameter can be a values combination of @ref DFSDM_BreakSignals.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,\r\n                                               uint32_t Threshold,\r\n                                               uint32_t BreakSignal)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r\n  assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));\r\n  assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));\r\n  \r\n  /* Check DFSDM channel state */\r\n  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r\n  {\r\n    /* Return error status */\r\n    status = HAL_ERROR;\r\n  }\r\n  else\r\n  {\r\n    /* Activate short circuit detection interrupt */\r\n    DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_SCDIE;\r\n\r\n    /* Configure threshold and break signals */\r\n    hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);\r\n    hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_OFFSET) | \\\r\n                                         Threshold);\r\n    \r\n    /* Start short circuit detection */\r\n    hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;\r\n  }\r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Short circuit detection callback. \r\n  * @param  hdfsdm_channel : DFSDM channel handle.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdfsdm_channel);\r\n  \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_DFSDM_ChannelScdCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to stop short circuit detection in interrupt mode.\r\n  * @note   Interrupt will be disabled for all channels\r\n  * @param  hdfsdm_channel : DFSDM channel handle.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  uint32_t channel;\r\n\r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r\n  \r\n  /* Check DFSDM channel state */\r\n  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r\n  {\r\n    /* Return error status */\r\n    status = HAL_ERROR;\r\n  }\r\n  else\r\n  {\r\n    /* Stop short circuit detection */\r\n    hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);\r\n    \r\n    /* Clear short circuit detection flag */\r\n    channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);\r\n    DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));\r\n\r\n    /* Disable short circuit detection interrupt */\r\n    DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE);\r\n  }\r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to get channel analog watchdog value.\r\n  * @param  hdfsdm_channel : DFSDM channel handle.\r\n  * @retval Channel analog watchdog value.\r\n  */\r\nint16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r\n{\r\n  return (int16_t) hdfsdm_channel->Instance->CHWDATAR;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to modify channel offset value.\r\n  * @param  hdfsdm_channel : DFSDM channel handle.\r\n  * @param  Offset : DFSDM channel offset.\r\n  *         This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607.\r\n  * @retval HAL status.\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,\r\n                                                int32_t Offset)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));\r\n  assert_param(IS_DFSDM_CHANNEL_OFFSET(Offset));\r\n  \r\n  /* Check DFSDM channel state */\r\n  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)\r\n  {\r\n    /* Return error status */\r\n    status = HAL_ERROR;\r\n  }\r\n  else\r\n  {\r\n    /* Modify channel offset */\r\n    hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET);\r\n    hdfsdm_channel->Instance->CHCFGR2 |= ((uint32_t) Offset << DFSDM_CHCFGR2_OFFSET_OFFSET);\r\n  }\r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function\r\n *  @brief    Channel state function\r\n *\r\n@verbatim\r\n  ==============================================================================\r\n                   ##### Channel state function #####\r\n  ==============================================================================\r\n    [..]  This section provides function allowing to:\r\n      (+) Get channel handle state.\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  This function allows to get the current DFSDM channel handle state.\r\n  * @param  hdfsdm_channel : DFSDM channel handle.\r\n  * @retval DFSDM channel state.\r\n  */\r\nHAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)\r\n{\r\n  /* Return DFSDM channel handle state */\r\n  return hdfsdm_channel->State;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions\r\n *  @brief    Filter initialization and de-initialization functions \r\n *\r\n@verbatim\r\n  ==============================================================================\r\n        ##### Filter initialization and de-initialization functions #####\r\n  ==============================================================================\r\n    [..]  This section provides functions allowing to:\r\n      (+) Initialize the DFSDM filter.\r\n      (+) De-initialize the DFSDM filter.\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initialize the DFSDM filter according to the specified parameters\r\n  *         in the DFSDM_FilterInitTypeDef structure and initialize the associated handle.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @retval HAL status.\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r\n{\r\n  /* Check DFSDM Channel handle */\r\n  if(hdfsdm_filter == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r\n  assert_param(IS_DFSDM_FILTER_REG_TRIGGER(hdfsdm_filter->Init.RegularParam.Trigger));\r\n  assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.FastMode));\r\n  assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.DmaMode));\r\n  assert_param(IS_DFSDM_FILTER_INJ_TRIGGER(hdfsdm_filter->Init.InjectedParam.Trigger));\r\n  assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.ScanMode));\r\n  assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.DmaMode));\r\n  assert_param(IS_DFSDM_FILTER_SINC_ORDER(hdfsdm_filter->Init.FilterParam.SincOrder));\r\n  assert_param(IS_DFSDM_FILTER_OVS_RATIO(hdfsdm_filter->Init.FilterParam.Oversampling));\r\n  assert_param(IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(hdfsdm_filter->Init.FilterParam.IntOversampling));\r\n\r\n  /* Check parameters compatibility */\r\n  if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \r\n    ((hdfsdm_filter->Init.RegularParam.Trigger  == DFSDM_FILTER_SYNC_TRIGGER) || \r\n     (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER)))\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Initialize DFSDM filter variables with default values */\r\n  hdfsdm_filter->RegularContMode     = DFSDM_CONTINUOUS_CONV_OFF;\r\n  hdfsdm_filter->InjectedChannelsNbr = 1;\r\n  hdfsdm_filter->InjConvRemaining    = 1;\r\n  hdfsdm_filter->ErrorCode           = DFSDM_FILTER_ERROR_NONE;\r\n  \r\n  /* Call MSP init function */\r\n  HAL_DFSDM_FilterMspInit(hdfsdm_filter);\r\n\r\n  /* Set regular parameters */\r\n  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);\r\n  if(hdfsdm_filter->Init.RegularParam.FastMode == ENABLE)\r\n  {\r\n    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_FAST;\r\n  }\r\n  else\r\n  {\r\n    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_FAST);\r\n  }\r\n\r\n  if(hdfsdm_filter->Init.RegularParam.DmaMode == ENABLE)\r\n  {\r\n    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RDMAEN;\r\n  }\r\n  else\r\n  {\r\n    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RDMAEN);\r\n  }\r\n\r\n  /* Set injected parameters */\r\n  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC | DFSDM_FLTCR1_JEXTEN | DFSDM_FLTCR1_JEXTSEL);\r\n  if(hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_EXT_TRIGGER)\r\n  {\r\n    assert_param(IS_DFSDM_FILTER_EXT_TRIG(hdfsdm_filter->Init.InjectedParam.ExtTrigger));\r\n    assert_param(IS_DFSDM_FILTER_EXT_TRIG_EDGE(hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge));\r\n    hdfsdm_filter->Instance->FLTCR1 |= (hdfsdm_filter->Init.InjectedParam.ExtTrigger);\r\n  }\r\n\r\n  if(hdfsdm_filter->Init.InjectedParam.ScanMode == ENABLE)\r\n  {\r\n    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSCAN;\r\n  }\r\n  else\r\n  {\r\n    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSCAN);\r\n  }\r\n\r\n  if(hdfsdm_filter->Init.InjectedParam.DmaMode == ENABLE)\r\n  {\r\n    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JDMAEN;\r\n  }\r\n  else\r\n  {\r\n    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JDMAEN);\r\n  }\r\n  \r\n  /* Set filter parameters */\r\n  hdfsdm_filter->Instance->FLTFCR &= ~(DFSDM_FLTFCR_FORD | DFSDM_FLTFCR_FOSR | DFSDM_FLTFCR_IOSR);\r\n  hdfsdm_filter->Instance->FLTFCR |= (hdfsdm_filter->Init.FilterParam.SincOrder |\r\n                                    ((hdfsdm_filter->Init.FilterParam.Oversampling - 1) << DFSDM_FLTFCR_FOSR_OFFSET) |\r\n                                  (hdfsdm_filter->Init.FilterParam.IntOversampling - 1));\r\n\r\n  /* Store regular and injected triggers and injected scan mode*/\r\n  hdfsdm_filter->RegularTrigger   = hdfsdm_filter->Init.RegularParam.Trigger;\r\n  hdfsdm_filter->InjectedTrigger  = hdfsdm_filter->Init.InjectedParam.Trigger;\r\n  hdfsdm_filter->ExtTriggerEdge   = hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge;\r\n  hdfsdm_filter->InjectedScanMode = hdfsdm_filter->Init.InjectedParam.ScanMode;\r\n  \r\n  /* Enable DFSDM filter */\r\n  hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;\r\n\r\n  /* Set DFSDM filter to ready state */\r\n  hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_READY;\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  De-initializes the DFSDM filter.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @retval HAL status.\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r\n{\r\n  /* Check DFSDM filter handle */\r\n  if(hdfsdm_filter == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r\n  \r\n  /* Disable the DFSDM filter */\r\n  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);\r\n  \r\n  /* Call MSP deinit function */\r\n  HAL_DFSDM_FilterMspDeInit(hdfsdm_filter);\r\n\r\n  /* Set DFSDM filter in reset state */\r\n  hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_RESET;\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the DFSDM filter MSP.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdfsdm_filter);\r\n  \r\n  /* NOTE : This function should not be modified, when the function is needed,\r\n            the HAL_DFSDM_FilterMspInit could be implemented in the user file.\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  De-initializes the DFSDM filter MSP.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdfsdm_filter);\r\n  \r\n  /* NOTE : This function should not be modified, when the function is needed,\r\n            the HAL_DFSDM_FilterMspDeInit could be implemented in the user file.\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DFSDM_Exported_Functions_Group2_Filter Filter control functions\r\n *  @brief    Filter control functions\r\n *\r\n@verbatim\r\n  ==============================================================================\r\n                    ##### Filter control functions #####\r\n  ==============================================================================\r\n    [..]  This section provides functions allowing to:\r\n      (+) Select channel and enable/disable continuous mode for regular conversion.\r\n      (+) Select channels for injected conversion.\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  This function allows to select channel and to enable/disable\r\n  *         continuous mode for regular conversion.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @param  Channel : Channel for regular conversion.\r\n  *         This parameter can be a value of @ref DFSDM_Channel_Selection.\r\n  * @param  ContinuousMode : Enable/disable continuous mode for regular conversion.\r\n  *         This parameter can be a value of @ref DFSDM_ContinuousMode.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r\n                                                   uint32_t                    Channel,\r\n                                                   uint32_t                    ContinuousMode)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  \r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r\n  assert_param(IS_DFSDM_REGULAR_CHANNEL(Channel));\r\n  assert_param(IS_DFSDM_CONTINUOUS_MODE(ContinuousMode));\r\n  \r\n  /* Check DFSDM filter state */\r\n  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) && \r\n     (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))\r\n  {\r\n    /* Configure channel and continuous mode for regular conversion */\r\n    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RCH | DFSDM_FLTCR1_RCONT);\r\n    if(ContinuousMode == DFSDM_CONTINUOUS_CONV_ON)\r\n    {\r\n      hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) (((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET) |\r\n                                                     DFSDM_FLTCR1_RCONT);\r\n    }\r\n    else\r\n    {\r\n      hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) ((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET);\r\n    }\r\n    /* Store continuous mode information */\r\n    hdfsdm_filter->RegularContMode = ContinuousMode;\r\n  }  \r\n  else\r\n  {\r\n    status = HAL_ERROR;\r\n  }\r\n\r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to select channels for injected conversion.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @param  Channel : Channels for injected conversion.\r\n  *         This parameter can be a values combination of @ref DFSDM_Channel_Selection.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r\n                                                   uint32_t                    Channel)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r\n  assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));\r\n  \r\n  /* Check DFSDM filter state */\r\n  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) && \r\n     (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))\r\n  {\r\n    /* Configure channel for injected conversion */\r\n    hdfsdm_filter->Instance->FLTJCHGR = (uint32_t) (Channel & DFSDM_LSB_MASK);\r\n    /* Store number of injected channels */\r\n    hdfsdm_filter->InjectedChannelsNbr = DFSDM_GetInjChannelsNbr(Channel);\r\n    /* Update number of injected channels remaining */\r\n    hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \\\r\n                                      hdfsdm_filter->InjectedChannelsNbr : 1;\r\n  }\r\n  else\r\n  {\r\n    status = HAL_ERROR;\r\n  }\r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions\r\n *  @brief    Filter operation functions\r\n *\r\n@verbatim\r\n  ==============================================================================\r\n                    ##### Filter operation functions #####\r\n  ==============================================================================\r\n    [..]  This section provides functions allowing to:\r\n      (+) Start conversion of regular/injected channel.\r\n      (+) Poll for the end of regular/injected conversion.\r\n      (+) Stop conversion of regular/injected channel.\r\n      (+) Start conversion of regular/injected channel and enable interrupt.\r\n      (+) Call the callback functions at the end of regular/injected conversions.\r\n      (+) Stop conversion of regular/injected channel and disable interrupt.\r\n      (+) Start conversion of regular/injected channel and enable DMA transfer.\r\n      (+) Stop conversion of regular/injected channel and disable DMA transfer.\r\n      (+) Start analog watchdog and enable interrupt.\r\n      (+) Call the callback function when analog watchdog occurs.\r\n      (+) Stop analog watchdog and disable interrupt.\r\n      (+) Start extreme detector.\r\n      (+) Stop extreme detector.\r\n      (+) Get result of regular channel conversion.\r\n      (+) Get result of injected channel conversion.\r\n      (+) Get extreme detector maximum and minimum values.\r\n      (+) Get conversion time.\r\n      (+) Handle DFSDM interrupt request.\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  This function allows to start regular conversion in polling mode.\r\n  * @note   This function should be called only when DFSDM filter instance is \r\n  *         in idle state or if injected conversion is ongoing.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r\n\r\n  /* Check DFSDM filter state */\r\n  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \\\r\n     (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))\r\n  {\r\n    /* Start regular conversion */\r\n    DFSDM_RegConvStart(hdfsdm_filter);\r\n  }\r\n  else\r\n  {\r\n    status = HAL_ERROR;\r\n  }\r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to poll for the end of regular conversion.\r\n  * @note   This function should be called only if regular conversion is ongoing.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @param  Timeout : Timeout value in milliseconds.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r\n                                                       uint32_t                    Timeout)\r\n{\r\n  uint32_t tickstart;\r\n\r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r\n\r\n  /* Check DFSDM filter state */\r\n  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \\\r\n     (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))\r\n  {\r\n    /* Return error status */\r\n    return HAL_ERROR;\r\n  }\r\n  else\r\n  {\r\n    /* Get timeout */\r\n    tickstart = HAL_GetTick();  \r\n\r\n    /* Wait end of regular conversion */\r\n    while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != DFSDM_FLTISR_REOCF)\r\n    {\r\n      /* Check the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))\r\n        {\r\n          /* Return timeout status */\r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n    /* Check if overrun occurs */\r\n    if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) == DFSDM_FLTISR_ROVRF)\r\n    {\r\n      /* Update error code and call error callback */\r\n      hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;\r\n      HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);\r\n\r\n      /* Clear regular overrun flag */\r\n      hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;\r\n    }\r\n    /* Update DFSDM filter state only if not continuous conversion and SW trigger */\r\n    if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \\\r\n       (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))\r\n    {\r\n      hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \\\r\n                             HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;\r\n    }\r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to stop regular conversion in polling mode.\r\n  * @note   This function should be called only if regular conversion is ongoing.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r\n\r\n  /* Check DFSDM filter state */\r\n  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \\\r\n     (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))\r\n  {\r\n    /* Return error status */\r\n    status = HAL_ERROR;\r\n  }\r\n  else\r\n  {\r\n    /* Stop regular conversion */\r\n    DFSDM_RegConvStop(hdfsdm_filter);\r\n  }\r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to start regular conversion in interrupt mode.\r\n  * @note   This function should be called only when DFSDM filter instance is \r\n  *         in idle state or if injected conversion is ongoing.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r\n\r\n  /* Check DFSDM filter state */\r\n  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \\\r\n     (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))\r\n  {\r\n    /* Enable interrupts for regular conversions */\r\n    hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);\r\n    \r\n    /* Start regular conversion */\r\n    DFSDM_RegConvStart(hdfsdm_filter);\r\n  }\r\n  else\r\n  {\r\n    status = HAL_ERROR;\r\n  }\r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to stop regular conversion in interrupt mode.\r\n  * @note   This function should be called only if regular conversion is ongoing.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r\n\r\n  /* Check DFSDM filter state */\r\n  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \\\r\n     (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))\r\n  {\r\n    /* Return error status */\r\n    status = HAL_ERROR;\r\n  }\r\n  else\r\n  {\r\n    /* Disable interrupts for regular conversions */\r\n    hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);\r\n    \r\n    /* Stop regular conversion */\r\n    DFSDM_RegConvStop(hdfsdm_filter);\r\n  }\r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to start regular conversion in DMA mode.\r\n  * @note   This function should be called only when DFSDM filter instance is \r\n  *         in idle state or if injected conversion is ongoing.\r\n  *         Please note that data on buffer will contain signed regular conversion\r\n  *         value on 24 most significant bits and corresponding channel on 3 least\r\n  *         significant bits.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @param  pData : The destination buffer address.\r\n  * @param  Length : The length of data to be transferred from DFSDM filter to memory.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r\n                                                   int32_t                    *pData,\r\n                                                   uint32_t                    Length)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r\n\r\n  /* Check destination address and length */\r\n  if((pData == NULL) || (Length == 0))\r\n  {\r\n    status = HAL_ERROR;\r\n  }\r\n  /* Check that DMA is enabled for regular conversion */\r\n  else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN)\r\n  {\r\n    status = HAL_ERROR;\r\n  }\r\n  /* Check parameters compatibility */\r\n  else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \\\r\n          (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \\\r\n          (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \\\r\n          (Length != 1))\r\n  {\r\n    status = HAL_ERROR;\r\n  }\r\n  else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \\\r\n          (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \\\r\n          (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))\r\n  {\r\n    status = HAL_ERROR;\r\n  }\r\n  /* Check DFSDM filter state */\r\n  else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \\\r\n          (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))\r\n  {\r\n    /* Set callbacks on DMA handler */\r\n    hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;\r\n    hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;\r\n    hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\\\r\n                                                   DFSDM_DMARegularHalfConvCplt : NULL;\r\n    \r\n    /* Start DMA in interrupt mode */\r\n    if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)&hdfsdm_filter->Instance->FLTRDATAR, \\\r\n                        (uint32_t) pData, Length) != HAL_OK)\r\n    {\r\n      /* Set DFSDM filter in error state */\r\n      hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;\r\n      status = HAL_ERROR;\r\n    }\r\n    else\r\n    {\r\n      /* Start regular conversion */\r\n      DFSDM_RegConvStart(hdfsdm_filter);\r\n    }\r\n  }\r\n  else\r\n  {\r\n    status = HAL_ERROR;\r\n  }\r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to start regular conversion in DMA mode and to get\r\n  *         only the 16 most significant bits of conversion.\r\n  * @note   This function should be called only when DFSDM filter instance is \r\n  *         in idle state or if injected conversion is ongoing.\r\n  *         Please note that data on buffer will contain signed 16 most significant\r\n  *         bits of regular conversion.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @param  pData : The destination buffer address.\r\n  * @param  Length : The length of data to be transferred from DFSDM filter to memory.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r\n                                                      int16_t                    *pData,\r\n                                                      uint32_t                    Length)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r\n\r\n  /* Check destination address and length */\r\n  if((pData == NULL) || (Length == 0))\r\n  {\r\n    status = HAL_ERROR;\r\n  }\r\n  /* Check that DMA is enabled for regular conversion */\r\n  else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN)\r\n  {\r\n    status = HAL_ERROR;\r\n  }\r\n  /* Check parameters compatibility */\r\n  else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \\\r\n          (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \\\r\n          (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \\\r\n          (Length != 1))\r\n  {\r\n    status = HAL_ERROR;\r\n  }\r\n  else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \\\r\n          (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \\\r\n          (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))\r\n  {\r\n    status = HAL_ERROR;\r\n  }\r\n  /* Check DFSDM filter state */\r\n  else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \\\r\n          (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))\r\n  {\r\n    /* Set callbacks on DMA handler */\r\n    hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;\r\n    hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;\r\n    hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\\\r\n                                                   DFSDM_DMARegularHalfConvCplt : NULL;\r\n    \r\n    /* Start DMA in interrupt mode */\r\n    if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)(&hdfsdm_filter->Instance->FLTRDATAR) + 2, \\\r\n                        (uint32_t) pData, Length) != HAL_OK)\r\n    {\r\n      /* Set DFSDM filter in error state */\r\n      hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;\r\n      status = HAL_ERROR;\r\n    }\r\n    else\r\n    {\r\n      /* Start regular conversion */\r\n      DFSDM_RegConvStart(hdfsdm_filter);\r\n    }\r\n  }\r\n  else\r\n  {\r\n    status = HAL_ERROR;\r\n  }\r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to stop regular conversion in DMA mode.\r\n  * @note   This function should be called only if regular conversion is ongoing.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r\n\r\n  /* Check DFSDM filter state */\r\n  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \\\r\n     (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))\r\n  {\r\n    /* Return error status */\r\n    status = HAL_ERROR;\r\n  }\r\n  else\r\n  {\r\n    /* Stop current DMA transfer */\r\n    if(HAL_DMA_Abort(hdfsdm_filter->hdmaReg) != HAL_OK)\r\n    {\r\n      /* Set DFSDM filter in error state */\r\n      hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;\r\n      status = HAL_ERROR;\r\n    }\r\n    else\r\n    {\r\n      /* Stop regular conversion */\r\n      DFSDM_RegConvStop(hdfsdm_filter);\r\n    }\r\n  }\r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to get regular conversion value.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @param  Channel : Corresponding channel of regular conversion.\r\n  * @retval Regular conversion value\r\n  */\r\nint32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r\n                                        uint32_t                   *Channel)\r\n{\r\n  uint32_t reg = 0;\r\n  int32_t  value = 0;\r\n  \r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r\n  assert_param(Channel != NULL);\r\n\r\n  /* Get value of data register for regular channel */\r\n  reg = hdfsdm_filter->Instance->FLTRDATAR;\r\n  \r\n  /* Extract channel and regular conversion value */\r\n  *Channel = (reg & DFSDM_FLTRDATAR_RDATACH);\r\n  value = ((reg & DFSDM_FLTRDATAR_RDATA) >> DFSDM_FLTRDATAR_DATA_OFFSET);\r\n\r\n  /* return regular conversion value */\r\n  return value;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to start injected conversion in polling mode.\r\n  * @note   This function should be called only when DFSDM filter instance is \r\n  *         in idle state or if regular conversion is ongoing.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r\n\r\n  /* Check DFSDM filter state */\r\n  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \\\r\n     (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))\r\n  {\r\n    /* Start injected conversion */\r\n    DFSDM_InjConvStart(hdfsdm_filter);\r\n  }\r\n  else\r\n  {\r\n    status = HAL_ERROR;\r\n  }\r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to poll for the end of injected conversion.\r\n  * @note   This function should be called only if injected conversion is ongoing.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @param  Timeout : Timeout value in milliseconds.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r\n                                                       uint32_t                    Timeout)\r\n{\r\n  uint32_t tickstart;\r\n\r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r\n\r\n  /* Check DFSDM filter state */\r\n  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \\\r\n     (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))\r\n  {\r\n    /* Return error status */\r\n    return HAL_ERROR;\r\n  }\r\n  else\r\n  {\r\n    /* Get timeout */\r\n    tickstart = HAL_GetTick();  \r\n\r\n    /* Wait end of injected conversions */\r\n    while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != DFSDM_FLTISR_JEOCF)\r\n    {\r\n      /* Check the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))\r\n        {\r\n          /* Return timeout status */\r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n    /* Check if overrun occurs */\r\n    if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) == DFSDM_FLTISR_JOVRF)\r\n    {\r\n      /* Update error code and call error callback */\r\n      hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;\r\n      HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);\r\n\r\n      /* Clear injected overrun flag */\r\n      hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;\r\n    }\r\n\r\n    /* Update remaining injected conversions */\r\n    hdfsdm_filter->InjConvRemaining--;\r\n    if(hdfsdm_filter->InjConvRemaining == 0)\r\n    {\r\n      /* Update DFSDM filter state only if trigger is software */\r\n      if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)\r\n      {\r\n        hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \\\r\n                               HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;\r\n      }\r\n      \r\n      /* end of injected sequence, reset the value */\r\n      hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \\\r\n                                         hdfsdm_filter->InjectedChannelsNbr : 1;\r\n    }\r\n\r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to stop injected conversion in polling mode.\r\n  * @note   This function should be called only if injected conversion is ongoing.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r\n\r\n  /* Check DFSDM filter state */\r\n  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \\\r\n     (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))\r\n  {\r\n    /* Return error status */\r\n    status = HAL_ERROR;\r\n  }\r\n  else\r\n  {\r\n    /* Stop injected conversion */\r\n    DFSDM_InjConvStop(hdfsdm_filter);\r\n  }\r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to start injected conversion in interrupt mode.\r\n  * @note   This function should be called only when DFSDM filter instance is \r\n  *         in idle state or if regular conversion is ongoing.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r\n\r\n  /* Check DFSDM filter state */\r\n  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \\\r\n     (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))\r\n  {\r\n    /* Enable interrupts for injected conversions */\r\n    hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);\r\n    \r\n    /* Start injected conversion */\r\n    DFSDM_InjConvStart(hdfsdm_filter);\r\n  }\r\n  else\r\n  {\r\n    status = HAL_ERROR;\r\n  }\r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to stop injected conversion in interrupt mode.\r\n  * @note   This function should be called only if injected conversion is ongoing.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r\n\r\n  /* Check DFSDM filter state */\r\n  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \\\r\n     (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))\r\n  {\r\n    /* Return error status */\r\n    status = HAL_ERROR;\r\n  }\r\n  else\r\n  {\r\n    /* Disable interrupts for injected conversions */\r\n    hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);\r\n    \r\n    /* Stop injected conversion */\r\n    DFSDM_InjConvStop(hdfsdm_filter);\r\n  }\r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to start injected conversion in DMA mode.\r\n  * @note   This function should be called only when DFSDM filter instance is \r\n  *         in idle state or if regular conversion is ongoing.\r\n  *         Please note that data on buffer will contain signed injected conversion\r\n  *         value on 24 most significant bits and corresponding channel on 3 least\r\n  *         significant bits.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @param  pData : The destination buffer address.\r\n  * @param  Length : The length of data to be transferred from DFSDM filter to memory.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r\n                                                    int32_t                    *pData,\r\n                                                    uint32_t                    Length)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r\n\r\n  /* Check destination address and length */\r\n  if((pData == NULL) || (Length == 0))\r\n  {\r\n    status = HAL_ERROR;\r\n  }\r\n  /* Check that DMA is enabled for injected conversion */\r\n  else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN)\r\n  {\r\n    status = HAL_ERROR;\r\n  }\r\n  /* Check parameters compatibility */\r\n  else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \\\r\n          (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \\\r\n          (Length > hdfsdm_filter->InjConvRemaining))\r\n  {\r\n    status = HAL_ERROR;\r\n  }\r\n  else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \\\r\n          (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))\r\n  {\r\n    status = HAL_ERROR;\r\n  }\r\n  /* Check DFSDM filter state */\r\n  else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \\\r\n          (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))\r\n  {\r\n    /* Set callbacks on DMA handler */\r\n    hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;\r\n    hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;\r\n    hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\\\r\n                                                   DFSDM_DMAInjectedHalfConvCplt : NULL;\r\n    \r\n    /* Start DMA in interrupt mode */\r\n    if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)&hdfsdm_filter->Instance->FLTJDATAR, \\\r\n                        (uint32_t) pData, Length) != HAL_OK)\r\n    {\r\n      /* Set DFSDM filter in error state */\r\n      hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;\r\n      status = HAL_ERROR;\r\n    }\r\n    else\r\n    {\r\n      /* Start injected conversion */\r\n      DFSDM_InjConvStart(hdfsdm_filter);\r\n    }\r\n  }\r\n  else\r\n  {\r\n    status = HAL_ERROR;\r\n  }\r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to start injected conversion in DMA mode and to get\r\n  *         only the 16 most significant bits of conversion.\r\n  * @note   This function should be called only when DFSDM filter instance is \r\n  *         in idle state or if regular conversion is ongoing.\r\n  *         Please note that data on buffer will contain signed 16 most significant\r\n  *         bits of injected conversion.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @param  pData : The destination buffer address.\r\n  * @param  Length : The length of data to be transferred from DFSDM filter to memory.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r\n                                                       int16_t                    *pData,\r\n                                                       uint32_t                    Length)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r\n\r\n  /* Check destination address and length */\r\n  if((pData == NULL) || (Length == 0))\r\n  {\r\n    status = HAL_ERROR;\r\n  }\r\n  /* Check that DMA is enabled for injected conversion */\r\n  else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN)\r\n  {\r\n    status = HAL_ERROR;\r\n  }\r\n  /* Check parameters compatibility */\r\n  else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \\\r\n          (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \\\r\n          (Length > hdfsdm_filter->InjConvRemaining))\r\n  {\r\n    status = HAL_ERROR;\r\n  }\r\n  else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \\\r\n          (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))\r\n  {\r\n    status = HAL_ERROR;\r\n  }\r\n  /* Check DFSDM filter state */\r\n  else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \\\r\n          (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))\r\n  {\r\n    /* Set callbacks on DMA handler */\r\n    hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;\r\n    hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;\r\n    hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\\\r\n                                                   DFSDM_DMAInjectedHalfConvCplt : NULL;\r\n    \r\n    /* Start DMA in interrupt mode */\r\n    if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)(&hdfsdm_filter->Instance->FLTJDATAR) + 2, \\\r\n                        (uint32_t) pData, Length) != HAL_OK)\r\n    {\r\n      /* Set DFSDM filter in error state */\r\n      hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;\r\n      status = HAL_ERROR;\r\n    }\r\n    else\r\n    {\r\n      /* Start injected conversion */\r\n      DFSDM_InjConvStart(hdfsdm_filter);\r\n    }\r\n  }\r\n  else\r\n  {\r\n    status = HAL_ERROR;\r\n  }\r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to stop injected conversion in DMA mode.\r\n  * @note   This function should be called only if injected conversion is ongoing.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r\n\r\n  /* Check DFSDM filter state */\r\n  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \\\r\n     (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))\r\n  {\r\n    /* Return error status */\r\n    status = HAL_ERROR;\r\n  }\r\n  else\r\n  {\r\n    /* Stop current DMA transfer */\r\n    if(HAL_DMA_Abort(hdfsdm_filter->hdmaInj) != HAL_OK)\r\n    {\r\n      /* Set DFSDM filter in error state */\r\n      hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;\r\n      status = HAL_ERROR;\r\n    }\r\n    else\r\n    {\r\n      /* Stop regular conversion */\r\n      DFSDM_InjConvStop(hdfsdm_filter);\r\n    }\r\n  }\r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to get injected conversion value.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @param  Channel : Corresponding channel of injected conversion.\r\n  * @retval Injected conversion value\r\n  */\r\nint32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, \r\n                                         uint32_t                   *Channel)\r\n{\r\n  uint32_t reg = 0;\r\n  int32_t  value = 0;\r\n  \r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r\n  assert_param(Channel != NULL);\r\n\r\n  /* Get value of data register for injected channel */\r\n  reg = hdfsdm_filter->Instance->FLTJDATAR;\r\n  \r\n  /* Extract channel and injected conversion value */\r\n  *Channel = (reg & DFSDM_FLTJDATAR_JDATACH);\r\n  value = ((reg & DFSDM_FLTJDATAR_JDATA) >> DFSDM_FLTJDATAR_DATA_OFFSET);\r\n\r\n  /* return regular conversion value */\r\n  return value;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to start filter analog watchdog in interrupt mode.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @param  awdParam : DFSDM filter analog watchdog parameters.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef   *hdfsdm_filter,\r\n                                              DFSDM_Filter_AwdParamTypeDef *awdParam)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r\n  assert_param(IS_DFSDM_FILTER_AWD_DATA_SOURCE(awdParam->DataSource));\r\n  assert_param(IS_DFSDM_INJECTED_CHANNEL(awdParam->Channel));\r\n  assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->HighThreshold));\r\n  assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->LowThreshold));\r\n  assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->HighBreakSignal));\r\n  assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->LowBreakSignal));\r\n  \r\n  /* Check DFSDM filter state */\r\n  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \\\r\n     (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))\r\n  {\r\n    /* Return error status */\r\n    status = HAL_ERROR;\r\n  }\r\n  else\r\n  {\r\n    /* Set analog watchdog data source */\r\n    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL);\r\n    hdfsdm_filter->Instance->FLTCR1 |= awdParam->DataSource;\r\n\r\n    /* Set thresholds and break signals */\r\n    hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);\r\n    hdfsdm_filter->Instance->FLTAWHTR |= (((uint32_t) awdParam->HighThreshold << DFSDM_FLTAWHTR_THRESHOLD_OFFSET) | \\\r\n                                        awdParam->HighBreakSignal);\r\n    hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);\r\n    hdfsdm_filter->Instance->FLTAWLTR |= (((uint32_t) awdParam->LowThreshold << DFSDM_FLTAWLTR_THRESHOLD_OFFSET) | \\\r\n                                        awdParam->LowBreakSignal);\r\n\r\n    /* Set channels and interrupt for analog watchdog */\r\n    hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH);\r\n    hdfsdm_filter->Instance->FLTCR2 |= (((awdParam->Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_AWDCH_OFFSET) | \\\r\n                                        DFSDM_FLTCR2_AWDIE);\r\n  }\r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to stop filter analog watchdog in interrupt mode.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r\n  \r\n  /* Check DFSDM filter state */\r\n  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \\\r\n     (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))\r\n  {\r\n    /* Return error status */\r\n    status = HAL_ERROR;\r\n  }\r\n  else\r\n  {\r\n    /* Reset channels for analog watchdog and deactivate interrupt */\r\n    hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH | DFSDM_FLTCR2_AWDIE);\r\n\r\n    /* Clear all analog watchdog flags */\r\n    hdfsdm_filter->Instance->FLTAWCFR = (DFSDM_FLTAWCFR_CLRAWHTF | DFSDM_FLTAWCFR_CLRAWLTF);\r\n    \r\n    /* Reset thresholds and break signals */\r\n    hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);\r\n    hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);\r\n\r\n    /* Reset analog watchdog data source */\r\n    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL);\r\n  }\r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to start extreme detector feature.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @param  Channel : Channels where extreme detector is enabled.\r\n  *         This parameter can be a values combination of @ref DFSDM_Channel_Selection.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r\n                                           uint32_t                    Channel)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r\n  assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));\r\n  \r\n  /* Check DFSDM filter state */\r\n  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \\\r\n     (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))\r\n  {\r\n    /* Return error status */\r\n    status = HAL_ERROR;\r\n  }\r\n  else\r\n  {\r\n    /* Set channels for extreme detector */\r\n    hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);\r\n    hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_OFFSET);    \r\n  }\r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to stop extreme detector feature.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  __IO uint32_t     reg1;\r\n  __IO uint32_t     reg2;\r\n\r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r\n  \r\n  /* Check DFSDM filter state */\r\n  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \\\r\n     (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))\r\n  {\r\n    /* Return error status */\r\n    status = HAL_ERROR;\r\n  }\r\n  else\r\n  {\r\n    /* Reset channels for extreme detector */\r\n    hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);\r\n\r\n    /* Clear extreme detector values */\r\n    reg1 = hdfsdm_filter->Instance->FLTEXMAX;\r\n    reg2 = hdfsdm_filter->Instance->FLTEXMIN;    \r\n    UNUSED(reg1); /* To avoid GCC warning */\r\n    UNUSED(reg2); /* To avoid GCC warning */\r\n  }\r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to get extreme detector maximum value.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @param  Channel : Corresponding channel.\r\n  * @retval Extreme detector maximum value\r\n  *         This value is between Min_Data = -8388608 and Max_Data = 8388607.\r\n  */\r\nint32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r\n                                       uint32_t                   *Channel)\r\n{\r\n  uint32_t reg = 0;\r\n  int32_t  value = 0;\r\n  \r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r\n  assert_param(Channel != NULL);\r\n\r\n  /* Get value of extreme detector maximum register */\r\n  reg = hdfsdm_filter->Instance->FLTEXMAX;\r\n  \r\n  /* Extract channel and extreme detector maximum value */\r\n  *Channel = (reg & DFSDM_FLTEXMAX_EXMAXCH);\r\n  value = ((reg & DFSDM_FLTEXMAX_EXMAX) >> DFSDM_FLTEXMAX_DATA_OFFSET);\r\n\r\n  /* return extreme detector maximum value */\r\n  return value;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to get extreme detector minimum value.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @param  Channel : Corresponding channel.\r\n  * @retval Extreme detector minimum value\r\n  *         This value is between Min_Data = -8388608 and Max_Data = 8388607.\r\n  */\r\nint32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r\n                                       uint32_t                   *Channel)\r\n{\r\n  uint32_t reg = 0;\r\n  int32_t  value = 0;\r\n  \r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r\n  assert_param(Channel != NULL);\r\n\r\n  /* Get value of extreme detector minimum register */\r\n  reg = hdfsdm_filter->Instance->FLTEXMIN;\r\n  \r\n  /* Extract channel and extreme detector minimum value */\r\n  *Channel = (reg & DFSDM_FLTEXMIN_EXMINCH);\r\n  value = ((reg & DFSDM_FLTEXMIN_EXMIN) >> DFSDM_FLTEXMIN_DATA_OFFSET);\r\n\r\n  /* return extreme detector minimum value */\r\n  return value;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to get conversion time value.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @retval Conversion time value\r\n  * @note   To get time in second, this value has to be divided by DFSDM clock frequency.\r\n  */\r\nuint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r\n{\r\n  uint32_t reg = 0;\r\n  uint32_t value = 0;\r\n  \r\n  /* Check parameters */\r\n  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));\r\n\r\n  /* Get value of conversion timer register */\r\n  reg = hdfsdm_filter->Instance->FLTCNVTIMR;\r\n  \r\n  /* Extract conversion time value */\r\n  value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_DATA_OFFSET);\r\n\r\n  /* return extreme detector minimum value */\r\n  return value;\r\n}\r\n\r\n/**\r\n  * @brief  This function handles the DFSDM interrupts.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @retval None\r\n  */\r\nvoid HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r\n{\r\n  /* Check if overrun occurs during regular conversion */\r\n  if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) != 0) && \\\r\n     ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_ROVRIE) != 0))\r\n  {\r\n    /* Clear regular overrun flag */\r\n    hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;\r\n\r\n    /* Update error code */\r\n    hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;\r\n\r\n    /* Call error callback */\r\n    HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);\r\n  }\r\n  /* Check if overrun occurs during injected conversion */\r\n  else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) != 0) && \\\r\n          ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JOVRIE) != 0))\r\n  {\r\n    /* Clear injected overrun flag */\r\n    hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;\r\n\r\n    /* Update error code */\r\n    hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;\r\n\r\n    /* Call error callback */\r\n    HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);\r\n  }\r\n  /* Check if end of regular conversion */\r\n  else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != 0) && \\\r\n          ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_REOCIE) != 0))\r\n  {\r\n    /* Call regular conversion complete callback */\r\n    HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);\r\n\r\n    /* End of conversion if mode is not continuous and software trigger */\r\n    if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \\\r\n       (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))\r\n    {\r\n      /* Disable interrupts for regular conversions */\r\n      hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE);\r\n\r\n      /* Update DFSDM filter state */\r\n      hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \\\r\n                             HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;\r\n    }\r\n  }\r\n  /* Check if end of injected conversion */\r\n  else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != 0) && \\\r\n          ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JEOCIE) != 0))\r\n  {\r\n    /* Call injected conversion complete callback */\r\n    HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);\r\n\r\n    /* Update remaining injected conversions */\r\n    hdfsdm_filter->InjConvRemaining--;\r\n    if(hdfsdm_filter->InjConvRemaining == 0)\r\n    {\r\n      /* End of conversion if trigger is software */\r\n      if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)\r\n      {\r\n        /* Disable interrupts for injected conversions */\r\n        hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE);\r\n\r\n        /* Update DFSDM filter state */\r\n        hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \\\r\n                               HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;\r\n      }\r\n      /* end of injected sequence, reset the value */\r\n      hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \\\r\n                                         hdfsdm_filter->InjectedChannelsNbr : 1;\r\n    }\r\n  }\r\n  /* Check if analog watchdog occurs */\r\n  else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_AWDF) != 0) && \\\r\n          ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_AWDIE) != 0))\r\n  {\r\n    uint32_t reg = 0;\r\n    uint32_t threshold = 0;\r\n    uint32_t channel = 0;\r\n    \r\n    /* Get channel and threshold */\r\n    reg = hdfsdm_filter->Instance->FLTAWSR;\r\n    threshold = ((reg & DFSDM_FLTAWSR_AWLTF) != 0) ? DFSDM_AWD_LOW_THRESHOLD : DFSDM_AWD_HIGH_THRESHOLD;\r\n    if(threshold == DFSDM_AWD_HIGH_THRESHOLD)\r\n    {\r\n      reg = reg >> DFSDM_FLTAWSR_HIGH_OFFSET;\r\n    }\r\n    while((reg & 1) == 0)\r\n    {\r\n      channel++;\r\n      reg = reg >> 1;\r\n    }\r\n    /* Clear analog watchdog flag */\r\n    hdfsdm_filter->Instance->FLTAWCFR = (threshold == DFSDM_AWD_HIGH_THRESHOLD) ? \\\r\n                                        (1 << (DFSDM_FLTAWSR_HIGH_OFFSET + channel)) : \\\r\n                                     (1 << channel);\r\n\r\n    /* Call analog watchdog callback */\r\n    HAL_DFSDM_FilterAwdCallback(hdfsdm_filter, channel, threshold);\r\n  }\r\n  /* Check if clock absence occurs */\r\n  else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \\\r\n         ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) != 0) && \\\r\n         ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_CKABIE) != 0))\r\n  {\r\n    uint32_t reg = 0;\r\n    uint32_t channel = 0;\r\n    \r\n    reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_OFFSET);\r\n\r\n    while(channel < DFSDM1_CHANNEL_NUMBER)\r\n    {\r\n      /* Check if flag is set and corresponding channel is enabled */\r\n      if(((reg & 1) != 0) && (a_dfsdm1ChannelHandle[channel] != NULL))\r\n      {\r\n        /* Check clock absence has been enabled for this channel */\r\n        if((a_dfsdm1ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0)\r\n        {\r\n          /* Clear clock absence flag */\r\n          hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));\r\n\r\n          /* Call clock absence callback */\r\n          HAL_DFSDM_ChannelCkabCallback(a_dfsdm1ChannelHandle[channel]);\r\n        }\r\n      }\r\n      channel++;\r\n      reg = reg >> 1;\r\n    }\r\n  }\r\n  /* Check if short circuit detection occurs */\r\n  else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \\\r\n         ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) != 0) && \\\r\n         ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_SCDIE) != 0))\r\n  {\r\n    uint32_t reg = 0;\r\n    uint32_t channel = 0;\r\n    \r\n    /* Get channel */\r\n    reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_OFFSET);\r\n    while((reg & 1) == 0)\r\n    {\r\n      channel++;\r\n      reg = reg >> 1;\r\n    }\r\n    \r\n    /* Clear short circuit detection flag */\r\n    hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));\r\n\r\n    /* Call short circuit detection callback */\r\n    HAL_DFSDM_ChannelScdCallback(a_dfsdm1ChannelHandle[channel]);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Regular conversion complete callback. \r\n  * @note   In interrupt mode, user has to read conversion value in this function\r\n  *         using HAL_DFSDM_FilterGetRegularValue.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdfsdm_filter);\r\n  \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_DFSDM_FilterRegConvCpltCallback could be implemented in the user file.\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Half regular conversion complete callback. \r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdfsdm_filter);\r\n  \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_DFSDM_FilterRegConvHalfCpltCallback could be implemented in the user file.\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Injected conversion complete callback. \r\n  * @note   In interrupt mode, user has to read conversion value in this function\r\n  *         using HAL_DFSDM_FilterGetInjectedValue.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdfsdm_filter);\r\n  \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_DFSDM_FilterInjConvCpltCallback could be implemented in the user file.\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Half injected conversion complete callback. \r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdfsdm_filter);\r\n  \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_DFSDM_FilterInjConvHalfCpltCallback could be implemented in the user file.\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Filter analog watchdog callback. \r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @param  Channel : Corresponding channel.\r\n  * @param  Threshold : Low or high threshold has been reached.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,\r\n                                        uint32_t Channel, uint32_t Threshold)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdfsdm_filter);\r\n  UNUSED(Channel);\r\n  UNUSED(Threshold);\r\n  \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_DFSDM_FilterAwdCallback could be implemented in the user file.\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Error callback. \r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdfsdm_filter);\r\n  \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_DFSDM_FilterErrorCallback could be implemented in the user file.\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions\r\n *  @brief    Filter state functions\r\n *\r\n@verbatim\r\n  ==============================================================================\r\n                     ##### Filter state functions #####\r\n  ==============================================================================\r\n    [..]  This section provides functions allowing to:\r\n      (+) Get the DFSDM filter state.\r\n      (+) Get the DFSDM filter error.\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  This function allows to get the current DFSDM filter handle state.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @retval DFSDM filter state.\r\n  */\r\nHAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r\n{\r\n  /* Return DFSDM filter handle state */\r\n  return hdfsdm_filter->State;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to get the current DFSDM filter error.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @retval DFSDM filter error code.\r\n  */\r\nuint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)\r\n{\r\n  return hdfsdm_filter->ErrorCode;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* End of exported functions -------------------------------------------------*/\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @addtogroup DFSDM_Private_Functions DFSDM Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  DMA half transfer complete callback for regular conversion. \r\n  * @param  hdma : DMA handle.\r\n  * @retval None\r\n  */\r\nstatic void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)   \r\n{\r\n  /* Get DFSDM filter handle */\r\n  DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;\r\n\r\n  /* Call regular half conversion complete callback */\r\n  HAL_DFSDM_FilterRegConvHalfCpltCallback(hdfsdm_filter);\r\n}\r\n\r\n/**\r\n  * @brief  DMA transfer complete callback for regular conversion. \r\n  * @param  hdma : DMA handle.\r\n  * @retval None\r\n  */\r\nstatic void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma)   \r\n{\r\n  /* Get DFSDM filter handle */\r\n  DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;\r\n\r\n  /* Call regular conversion complete callback */\r\n  HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);\r\n}\r\n\r\n/**\r\n  * @brief  DMA half transfer complete callback for injected conversion. \r\n  * @param  hdma : DMA handle.\r\n  * @retval None\r\n  */\r\nstatic void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)   \r\n{\r\n  /* Get DFSDM filter handle */\r\n  DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;\r\n\r\n  /* Call injected half conversion complete callback */\r\n  HAL_DFSDM_FilterInjConvHalfCpltCallback(hdfsdm_filter);\r\n}\r\n\r\n/**\r\n  * @brief  DMA transfer complete callback for injected conversion. \r\n  * @param  hdma : DMA handle.\r\n  * @retval None\r\n  */\r\nstatic void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)   \r\n{\r\n  /* Get DFSDM filter handle */\r\n  DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;\r\n\r\n  /* Call injected conversion complete callback */\r\n  HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);\r\n}\r\n\r\n/**\r\n  * @brief  DMA error callback. \r\n  * @param  hdma : DMA handle.\r\n  * @retval None\r\n  */\r\nstatic void DFSDM_DMAError(DMA_HandleTypeDef *hdma)   \r\n{\r\n  /* Get DFSDM filter handle */\r\n  DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;\r\n\r\n  /* Update error code */\r\n  hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_DMA;\r\n\r\n  /* Call error callback */\r\n  HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to get the number of injected channels.\r\n  * @param  Channels : bitfield of injected channels.\r\n  * @retval Number of injected channels.\r\n  */\r\nstatic uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels)\r\n{\r\n  uint32_t nbChannels = 0;\r\n  uint32_t tmp;\r\n  \r\n  /* Get the number of channels from bitfield */\r\n  tmp = (uint32_t) (Channels & DFSDM_LSB_MASK);\r\n  while(tmp != 0)\r\n  {\r\n    if((tmp & 1) != 0)\r\n    {\r\n      nbChannels++;\r\n    }\r\n    tmp = (uint32_t) (tmp >> 1);\r\n  }\r\n  return nbChannels;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to get the channel number from channel instance.\r\n  * @param  Instance : DFSDM channel instance.\r\n  * @retval Channel number.\r\n  */\r\nstatic uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance)\r\n{\r\n  uint32_t channel = 0xFF;\r\n  \r\n  /* Get channel from instance */\r\n  if(Instance == DFSDM1_Channel0)\r\n  {\r\n    channel = 0;\r\n  }\r\n  else if(Instance == DFSDM1_Channel1)\r\n  {\r\n    channel = 1;\r\n  }\r\n  else if(Instance == DFSDM1_Channel2)\r\n  {\r\n    channel = 2;\r\n  }\r\n  else if(Instance == DFSDM1_Channel3)\r\n  {\r\n    channel = 3;\r\n  }\r\n  else if(Instance == DFSDM1_Channel4)\r\n  {\r\n    channel = 4;\r\n  }\r\n  else if(Instance == DFSDM1_Channel5)\r\n  {\r\n    channel = 5;\r\n  }\r\n  else if(Instance == DFSDM1_Channel6)\r\n  {\r\n    channel = 6;\r\n  }\r\n  else if(Instance == DFSDM1_Channel7)\r\n  {\r\n    channel = 7;\r\n  }\r\n\r\n  return channel;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to really start regular conversion.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @retval None\r\n  */\r\nstatic void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)\r\n{\r\n  /* Check regular trigger */\r\n  if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)\r\n  {\r\n    /* Software start of regular conversion */\r\n    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;\r\n  }\r\n  else /* synchronous trigger */\r\n  {\r\n    /* Disable DFSDM filter */\r\n    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);\r\n    \r\n    /* Set RSYNC bit in DFSDM_FLTCR1 register */\r\n    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSYNC;\r\n\r\n    /* Enable DFSDM  filter */\r\n    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;\r\n    \r\n    /* If injected conversion was in progress, restart it */\r\n    if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)\r\n    {\r\n      if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)\r\n      {\r\n        hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;\r\n      }\r\n      /* Update remaining injected conversions */\r\n      hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \\\r\n                                         hdfsdm_filter->InjectedChannelsNbr : 1;\r\n    }\r\n  }\r\n  /* Update DFSDM filter state */\r\n  hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \\\r\n                          HAL_DFSDM_FILTER_STATE_REG : HAL_DFSDM_FILTER_STATE_REG_INJ;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to really stop regular conversion.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @retval None\r\n  */\r\nstatic void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)\r\n{\r\n  /* Disable DFSDM filter */\r\n  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);\r\n\r\n  /* If regular trigger was synchronous, reset RSYNC bit in DFSDM_FLTCR1 register */\r\n  if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SYNC_TRIGGER)\r\n  {\r\n    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);\r\n  }\r\n\r\n  /* Enable DFSDM filter */\r\n  hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;\r\n  \r\n  /* If injected conversion was in progress, restart it */\r\n  if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ)\r\n  {\r\n    if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)\r\n    {\r\n      hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;\r\n    }\r\n    /* Update remaining injected conversions */\r\n    hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \\\r\n                                       hdfsdm_filter->InjectedChannelsNbr : 1;\r\n  }\r\n  \r\n  /* Update DFSDM filter state */\r\n  hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \\\r\n                          HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to really start injected conversion.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @retval None\r\n  */\r\nstatic void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)\r\n{\r\n  /* Check injected trigger */\r\n  if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)\r\n  {\r\n    /* Software start of injected conversion */\r\n    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;\r\n  }\r\n  else /* external or synchronous trigger */\r\n  {\r\n    /* Disable DFSDM filter */\r\n    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);\r\n      \r\n    if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)\r\n    {\r\n      /* Set JSYNC bit in DFSDM_FLTCR1 register */\r\n      hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSYNC;\r\n    }\r\n    else /* external trigger */\r\n    {\r\n      /* Set JEXTEN[1:0] bits in DFSDM_FLTCR1 register */\r\n      hdfsdm_filter->Instance->FLTCR1 |= hdfsdm_filter->ExtTriggerEdge;\r\n    }\r\n    \r\n    /* Enable DFSDM filter */\r\n    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;\r\n\r\n    /* If regular conversion was in progress, restart it */\r\n    if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) && \\\r\n       (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))\r\n    {\r\n      hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;\r\n    }\r\n  }\r\n  /* Update DFSDM filter state */\r\n  hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \\\r\n                         HAL_DFSDM_FILTER_STATE_INJ : HAL_DFSDM_FILTER_STATE_REG_INJ;\r\n}\r\n\r\n/**\r\n  * @brief  This function allows to really stop injected conversion.\r\n  * @param  hdfsdm_filter : DFSDM filter handle.\r\n  * @retval None\r\n  */\r\nstatic void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)\r\n{\r\n  /* Disable DFSDM filter */\r\n  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);\r\n\r\n  /* If injected trigger was synchronous, reset JSYNC bit in DFSDM_FLTCR1 register */\r\n  if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)\r\n  {\r\n    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC);\r\n  }\r\n  else if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_EXT_TRIGGER)\r\n  {\r\n    /* Reset JEXTEN[1:0] bits in DFSDM_FLTCR1 register */\r\n    hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JEXTEN);\r\n  }\r\n\r\n  /* Enable DFSDM filter */\r\n  hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;\r\n  \r\n  /* If regular conversion was in progress, restart it */\r\n  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) && \\\r\n     (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))\r\n  {\r\n    hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;\r\n  }\r\n\r\n  /* Update remaining injected conversions */\r\n  hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \\\r\n                                     hdfsdm_filter->InjectedChannelsNbr : 1;\r\n\r\n  /* Update DFSDM filter state */\r\n  hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \\\r\n                          HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* End of private functions --------------------------------------------------*/\r\n\r\n/**\r\n  * @}\r\n  */\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n#endif /* HAL_DFSDM_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_dma.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   DMA HAL module driver.\r\n  *    \r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the Direct Memory Access (DMA) peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + IO operation functions\r\n  *           + Peripheral State and errors functions\r\n  @verbatim     \r\n  ==============================================================================      \r\n                        ##### How to use this driver #####\r\n  ============================================================================== \r\n  [..]\r\n   (#) Enable and configure the peripheral to be connected to the DMA Stream\r\n       (except for internal SRAM/FLASH memories: no initialization is \r\n       necessary) please refer to Reference manual for connection between peripherals\r\n       and DMA requests . \r\n          \r\n   (#) For a given Stream, program the required configuration through the following parameters:   \r\n       Transfer Direction, Source and Destination data formats, \r\n       Circular, Normal or peripheral flow control mode, Stream Priority level, \r\n       Source and Destination Increment mode, FIFO mode and its Threshold (if needed), \r\n       Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.\r\n                     \r\n     *** Polling mode IO operation ***\r\n     =================================   \r\n    [..] \r\n          (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source \r\n              address and destination address and the Length of data to be transferred\r\n          (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this  \r\n              case a fixed Timeout can be configured by User depending from his application.\r\n               \r\n     *** Interrupt mode IO operation ***    \r\n     =================================== \r\n    [..]     \r\n          (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()\r\n          (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() \r\n          (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of  \r\n              Source address and destination address and the Length of data to be transferred. In this \r\n              case the DMA interrupt is configured \r\n          (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine\r\n          (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can \r\n              add his own function by customization of function pointer XferCpltCallback and \r\n              XferErrorCallback (i.e a member of DMA handle structure). \r\n    [..]                \r\n     (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error \r\n         detection.\r\n         \r\n     (#) Use HAL_DMA_Abort() function to abort the current transfer\r\n     \r\n     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.\r\n    \r\n     -@-   The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is\r\n           possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set\r\n           Half-Word data size for the peripheral to access its data register and set Word data size\r\n           for the Memory to gain in access time. Each two half words will be packed and written in\r\n           a single access to a Word in the Memory).\r\n      \r\n     -@-   When FIFO is disabled, it is not allowed to configure different Data Sizes for Source\r\n           and Destination. In this case the Peripheral Data Size will be applied to both Source\r\n           and Destination.               \r\n  \r\n     *** DMA HAL driver macros list ***\r\n     ============================================= \r\n     [..]\r\n       Below the list of most used macros in DMA HAL driver.\r\n       \r\n      (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.\r\n      (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.\r\n      (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level.\r\n      (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts.\r\n      (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.\r\n      (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not. \r\n     \r\n     [..] \r\n      (@) You can refer to the DMA HAL driver header file for more useful macros  \r\n  \r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup DMA DMA\r\n  * @brief DMA HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_DMA_MODULE_ENABLED\r\n\r\n/* Private types -------------------------------------------------------------*/\r\ntypedef struct\r\n{\r\n  __IO uint32_t ISR;   /*!< DMA interrupt status register */\r\n  __IO uint32_t Reserved0;\r\n  __IO uint32_t IFCR;  /*!< DMA interrupt flag clear register */\r\n} DMA_Base_Registers;\r\n\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @addtogroup DMA_Private_Constants\r\n * @{\r\n */\r\n #define HAL_TIMEOUT_DMA_ABORT    ((uint32_t)5)  /* 5 ms */\r\n/**\r\n  * @}\r\n  */\r\n/* Private macros ------------------------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @addtogroup DMA_Private_Functions\r\n  * @{\r\n  */\r\nstatic void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r\nstatic uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);\r\nstatic HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);\r\n\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/* Exported functions ---------------------------------------------------------*/\r\n/** @addtogroup DMA_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup DMA_Exported_Functions_Group1\r\n  *\r\n@verbatim   \r\n ===============================================================================\r\n             ##### Initialization and de-initialization functions  #####\r\n ===============================================================================  \r\n    [..]\r\n    This section provides functions allowing to initialize the DMA Stream source\r\n    and destination addresses, incrementation and data sizes, transfer direction, \r\n    circular/normal mode selection, memory-to-memory mode selection and Stream priority value.\r\n    [..]\r\n    The HAL_DMA_Init() function follows the DMA configuration procedures as described in\r\n    reference manual.  \r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @brief  Initialize the DMA according to the specified\r\n  *         parameters in the DMA_InitTypeDef and create the associated handle.\r\n  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified DMA Stream.  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)\r\n{\r\n  uint32_t tmp = 0U;\r\n  uint32_t tickstart = HAL_GetTick();\r\n  DMA_Base_Registers *regs;\r\n\r\n  /* Check the DMA peripheral state */\r\n  if(hdma == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));\r\n  assert_param(IS_DMA_CHANNEL(hdma->Init.Channel));\r\n  assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));\r\n  assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));\r\n  assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));\r\n  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));\r\n  assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));\r\n  assert_param(IS_DMA_MODE(hdma->Init.Mode));\r\n  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));\r\n  assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));\r\n  /* Check the memory burst, peripheral burst and FIFO threshold parameters only\r\n     when FIFO mode is enabled */\r\n  if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)\r\n  {\r\n    assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));\r\n    assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));\r\n    assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));\r\n  }\r\n  \r\n  /* Allocate lock resource */\r\n  __HAL_UNLOCK(hdma);\r\n\r\n  /* Change DMA peripheral state */\r\n  hdma->State = HAL_DMA_STATE_BUSY;\r\n  \r\n  /* Disable the peripheral */\r\n  __HAL_DMA_DISABLE(hdma);\r\n  \r\n  /* Check if the DMA Stream is effectively disabled */\r\n  while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)\r\n  {\r\n    /* Check for the Timeout */\r\n    if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)\r\n    {\r\n      /* Update error code */\r\n      hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;\r\n      \r\n      /* Change the DMA state */\r\n      hdma->State = HAL_DMA_STATE_TIMEOUT;\r\n      \r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  \r\n  /* Get the CR register value */\r\n  tmp = hdma->Instance->CR;\r\n\r\n  /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */\r\n  tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \\\r\n                      DMA_SxCR_PL    | DMA_SxCR_MSIZE  | DMA_SxCR_PSIZE  | \\\r\n                      DMA_SxCR_MINC  | DMA_SxCR_PINC   | DMA_SxCR_CIRC   | \\\r\n                      DMA_SxCR_DIR   | DMA_SxCR_CT     | DMA_SxCR_DBM));\r\n\r\n  /* Prepare the DMA Stream configuration */\r\n  tmp |=  hdma->Init.Channel             | hdma->Init.Direction        |\r\n          hdma->Init.PeriphInc           | hdma->Init.MemInc           |\r\n          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |\r\n          hdma->Init.Mode                | hdma->Init.Priority;\r\n\r\n  /* the Memory burst and peripheral burst are not used when the FIFO is disabled */\r\n  if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)\r\n  {\r\n    /* Get memory burst and peripheral burst */\r\n    tmp |=  hdma->Init.MemBurst | hdma->Init.PeriphBurst;\r\n  }\r\n  \r\n  /* Write to DMA Stream CR register */\r\n  hdma->Instance->CR = tmp;  \r\n\r\n  /* Get the FCR register value */\r\n  tmp = hdma->Instance->FCR;\r\n\r\n  /* Clear Direct mode and FIFO threshold bits */\r\n  tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);\r\n\r\n  /* Prepare the DMA Stream FIFO configuration */\r\n  tmp |= hdma->Init.FIFOMode;\r\n\r\n  /* the FIFO threshold is not used when the FIFO mode is disabled */\r\n  if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)\r\n  {\r\n    /* Get the FIFO threshold */\r\n    tmp |= hdma->Init.FIFOThreshold;\r\n    \r\n    if (DMA_CheckFifoParam(hdma) != HAL_OK)\r\n    {\r\n      /* Update error code */\r\n      hdma->ErrorCode = HAL_DMA_ERROR_PARAM;\r\n      \r\n      /* Change the DMA state */\r\n      hdma->State = HAL_DMA_STATE_READY;\r\n      \r\n      return HAL_ERROR; \r\n    }\r\n  }\r\n  \r\n  /* Write to DMA Stream FCR */\r\n  hdma->Instance->FCR = tmp;\r\n\r\n  /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate\r\n     DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */\r\n  regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);\r\n  \r\n  /* Clear all interrupt flags */\r\n  regs->IFCR = 0x3FU << hdma->StreamIndex;\r\n\r\n  /* Initialize the error code */\r\n  hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r\n                                                                                     \r\n  /* Initialize the DMA state */\r\n  hdma->State = HAL_DMA_STATE_READY;\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the DMA peripheral \r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified DMA Stream.  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)\r\n{\r\n  DMA_Base_Registers *regs;\r\n\r\n  /* Check the DMA peripheral state */\r\n  if(hdma == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Check the DMA peripheral state */\r\n  if(hdma->State == HAL_DMA_STATE_BUSY)\r\n  {\r\n    /* Return error status */\r\n    return HAL_BUSY;\r\n  }\r\n\r\n  /* Disable the selected DMA Streamx */\r\n  __HAL_DMA_DISABLE(hdma);\r\n\r\n  /* Reset DMA Streamx control register */\r\n  hdma->Instance->CR   = 0U;\r\n\r\n  /* Reset DMA Streamx number of data to transfer register */\r\n  hdma->Instance->NDTR = 0U;\r\n\r\n  /* Reset DMA Streamx peripheral address register */\r\n  hdma->Instance->PAR  = 0U;\r\n\r\n  /* Reset DMA Streamx memory 0 address register */\r\n  hdma->Instance->M0AR = 0U;\r\n  \r\n  /* Reset DMA Streamx memory 1 address register */\r\n  hdma->Instance->M1AR = 0U;\r\n  \r\n  /* Reset DMA Streamx FIFO control register */\r\n  hdma->Instance->FCR  = (uint32_t)0x00000021U;\r\n  \r\n  /* Get DMA steam Base Address */  \r\n  regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);\r\n  \r\n  /* Clear all interrupt flags at correct offset within the register */\r\n  regs->IFCR = 0x3FU << hdma->StreamIndex;\r\n\r\n  /* Initialize the error code */\r\n  hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r\n\r\n  /* Initialize the DMA state */\r\n  hdma->State = HAL_DMA_STATE_RESET;\r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hdma);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup DMA_Exported_Functions_Group2\r\n  *\r\n@verbatim   \r\n ===============================================================================\r\n                      #####  IO operation functions  #####\r\n ===============================================================================\r\n    [..]  This section provides functions allowing to:\r\n      (+) Configure the source, destination address and data length and Start DMA transfer\r\n      (+) Configure the source, destination address and data length and \r\n          Start DMA transfer with interrupt\r\n      (+) Abort DMA transfer\r\n      (+) Poll for transfer complete\r\n      (+) Handle DMA interrupt request  \r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Starts the DMA Transfer.\r\n  * @param  hdma      : pointer to a DMA_HandleTypeDef structure that contains\r\n  *                     the configuration information for the specified DMA Stream.  \r\n  * @param  SrcAddress: The source memory Buffer address\r\n  * @param  DstAddress: The destination memory Buffer address\r\n  * @param  DataLength: The length of data to be transferred from source to destination\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_DMA_BUFFER_SIZE(DataLength));\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hdma);\r\n\r\n  if(HAL_DMA_STATE_READY == hdma->State)\r\n  {\r\n    /* Change DMA peripheral state */\r\n    hdma->State = HAL_DMA_STATE_BUSY;\r\n    \r\n    /* Initialize the error code */\r\n    hdma->ErrorCode = HAL_DMA_ERROR_NONE;    \r\n    \r\n    /* Configure the source, destination address and the data length */\r\n    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);\r\n\r\n    /* Enable the Peripheral */\r\n    __HAL_DMA_ENABLE(hdma);\r\n  }\r\n  else\r\n  {\r\n    /* Process unlocked */\r\n    __HAL_UNLOCK(hdma);\r\n    \r\n    /* Return error status */\r\n    status = HAL_BUSY;\r\n  } \r\n  return status; \r\n}\r\n\r\n/**\r\n  * @brief  Start the DMA Transfer with interrupt enabled.\r\n  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains\r\n  *                     the configuration information for the specified DMA Stream.  \r\n  * @param  SrcAddress: The source memory Buffer address\r\n  * @param  DstAddress: The destination memory Buffer address\r\n  * @param  DataLength: The length of data to be transferred from source to destination\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* calculate DMA base and stream number */\r\n  DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_DMA_BUFFER_SIZE(DataLength));\r\n \r\n  /* Process locked */\r\n  __HAL_LOCK(hdma);\r\n  \r\n  if(HAL_DMA_STATE_READY == hdma->State)\r\n  {\r\n    /* Change DMA peripheral state */\r\n    hdma->State = HAL_DMA_STATE_BUSY;\r\n    \r\n    /* Initialize the error code */\r\n    hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r\n    \r\n    /* Configure the source, destination address and the data length */\r\n    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);\r\n    \r\n    /* Clear all interrupt flags at correct offset within the register */\r\n    regs->IFCR = 0x3FU << hdma->StreamIndex;\r\n    \r\n    /* Enable Common interrupts*/\r\n    hdma->Instance->CR  |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;\r\n    hdma->Instance->FCR |= DMA_IT_FE;\r\n    \r\n    if(hdma->XferHalfCpltCallback != NULL)\r\n    {\r\n      hdma->Instance->CR  |= DMA_IT_HT;\r\n    }\r\n    \r\n    /* Enable the Peripheral */\r\n    __HAL_DMA_ENABLE(hdma);\r\n  }\r\n  else\r\n  {\r\n    /* Process unlocked */\r\n    __HAL_UNLOCK(hdma);\t  \r\n    \r\n    /* Return error status */\r\n    status = HAL_BUSY;\r\n  }\r\n  \r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Aborts the DMA Transfer.\r\n  * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains\r\n  *                 the configuration information for the specified DMA Stream.\r\n  *                   \r\n  * @note  After disabling a DMA Stream, a check for wait until the DMA Stream is \r\n  *        effectively disabled is added. If a Stream is disabled \r\n  *        while a data transfer is ongoing, the current data will be transferred\r\n  *        and the Stream will be effectively disabled only after the transfer of\r\n  *        this single data is finished.  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)\r\n{\r\n  /* calculate DMA base and stream number */\r\n  DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;\r\n  \r\n  uint32_t tickstart = HAL_GetTick();\r\n  \r\n  if(hdma->State != HAL_DMA_STATE_BUSY)\r\n  {\r\n    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hdma);\r\n    \r\n    return HAL_ERROR;\r\n  }\r\n  else\r\n  {\r\n    /* Disable all the transfer interrupts */\r\n    hdma->Instance->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);\r\n    hdma->Instance->FCR &= ~(DMA_IT_FE);\r\n    \r\n    if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))\r\n    {\r\n      hdma->Instance->CR  &= ~(DMA_IT_HT);\r\n    }\r\n    \r\n    /* Disable the stream */\r\n    __HAL_DMA_DISABLE(hdma);\r\n    \r\n    /* Check if the DMA Stream is effectively disabled */\r\n    while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)\r\n    {\r\n      /* Check for the Timeout */\r\n      if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)\r\n      {\r\n        /* Update error code */\r\n        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;\r\n        \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hdma);\r\n        \r\n        /* Change the DMA state */\r\n        hdma->State = HAL_DMA_STATE_TIMEOUT;\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n    \r\n    /* Clear all interrupt flags at correct offset within the register */\r\n    regs->IFCR = 0x3FU << hdma->StreamIndex;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hdma);\r\n    \r\n    /* Change the DMA state*/\r\n    hdma->State = HAL_DMA_STATE_READY;\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Aborts the DMA Transfer in Interrupt mode.\r\n  * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains\r\n  *                 the configuration information for the specified DMA Stream.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)\r\n{\r\n  if(hdma->State != HAL_DMA_STATE_BUSY)\r\n  {\r\n    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;\r\n    return HAL_ERROR;\r\n  }\r\n  else\r\n  {\r\n    /* Set Abort State  */\r\n    hdma->State = HAL_DMA_STATE_ABORT;\r\n    \r\n    /* Disable the stream */\r\n    __HAL_DMA_DISABLE(hdma);\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Polling for transfer complete.\r\n  * @param  hdma:          pointer to a DMA_HandleTypeDef structure that contains\r\n  *                        the configuration information for the specified DMA Stream.\r\n  * @param  CompleteLevel: Specifies the DMA level complete.\r\n  * @note   The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead.\r\n  *         This model could be used for debug purpose.\r\n  * @note   The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). \r\n  * @param  Timeout:       Timeout duration.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK; \r\n  uint32_t temp;\r\n  uint32_t tickstart = HAL_GetTick(); \r\n  uint32_t tmpisr;\r\n  \r\n  /* calculate DMA base and stream number */\r\n  DMA_Base_Registers *regs;\r\n  \r\n  /* Polling mode not supported in circular mode and double buffering mode */\r\n  if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET)\r\n  {\r\n    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Get the level transfer complete flag */\r\n  if(CompleteLevel == HAL_DMA_FULL_TRANSFER)\r\n  {\r\n    /* Transfer Complete flag */\r\n    temp = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;\r\n  }\r\n  else\r\n  {\r\n    /* Half Transfer Complete flag */\r\n    temp = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;\r\n  }\r\n  \r\n  regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;\r\n  tmpisr = regs->ISR;\r\n  \r\n  while((tmpisr & temp) == RESET )\r\n  {\r\n    /* Check for the Timeout (Not applicable in circular mode)*/\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        /* Update error code */\r\n        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;\r\n\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hdma);\r\n        \r\n        /* Change the DMA state */\r\n        hdma->State = HAL_DMA_STATE_READY;\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n    \r\n    if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)\r\n    {\r\n      /* Update error code */\r\n      hdma->ErrorCode |= HAL_DMA_ERROR_TE;\r\n      \r\n      /* Clear the transfer error flag */\r\n      regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;\r\n    }\r\n    \r\n    if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)\r\n    {\r\n      /* Update error code */\r\n      hdma->ErrorCode |= HAL_DMA_ERROR_FE;\r\n      \r\n      /* Clear the FIFO error flag */\r\n      regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;\r\n    }\r\n    \r\n    if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)\r\n    {\r\n      /* Update error code */\r\n      hdma->ErrorCode |= HAL_DMA_ERROR_DME;\r\n      \r\n      /* Clear the Direct Mode error flag */\r\n      regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;\r\n    }\r\n  }\r\n  \r\n  if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)\r\n  {\r\n    if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)\r\n    {\r\n      HAL_DMA_Abort(hdma);\r\n    \r\n      /* Clear the half transfer and transfer complete flags */\r\n      regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;\r\n    \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hdma);\r\n\r\n      /* Change the DMA state */\r\n      hdma->State= HAL_DMA_STATE_READY;\r\n\r\n      return HAL_ERROR;\r\n   }\r\n\r\n   status = HAL_ERROR;\r\n  }\r\n  \r\n  /* Get the level transfer complete flag */\r\n  if(CompleteLevel == HAL_DMA_FULL_TRANSFER)\r\n  {\r\n    /* Clear the half transfer and transfer complete flags */\r\n    regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hdma);\r\n\r\n    hdma->State = HAL_DMA_STATE_READY;\r\n  }\r\n  else\r\n  {\r\n    /* Clear the half transfer and transfer complete flags */\r\n    regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex;\r\n  }\r\n  \r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Handles DMA interrupt request.\r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified DMA Stream.  \r\n  * @retval None\r\n  */\r\nvoid HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)\r\n{\r\n  uint32_t tmpisr;\r\n  __IO uint32_t count = 0;\r\n  uint32_t timeout = SystemCoreClock / 9600;\r\n\r\n  /* calculate DMA base and stream number */\r\n  DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;\r\n\r\n  tmpisr = regs->ISR;\r\n\r\n  /* Transfer Error Interrupt management ***************************************/\r\n  if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)\r\n  {\r\n    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)\r\n    {\r\n      /* Disable the transfer error interrupt */\r\n      hdma->Instance->CR  &= ~(DMA_IT_TE);\r\n      \r\n      /* Clear the transfer error flag */\r\n      regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;\r\n      \r\n      /* Update error code */\r\n      hdma->ErrorCode |= HAL_DMA_ERROR_TE;\r\n    }\r\n  }\r\n  /* FIFO Error Interrupt management ******************************************/\r\n  if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)\r\n  {\r\n    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)\r\n    {\r\n      /* Clear the FIFO error flag */\r\n      regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;\r\n\r\n      /* Update error code */\r\n      hdma->ErrorCode |= HAL_DMA_ERROR_FE;\r\n    }\r\n  }\r\n  /* Direct Mode Error Interrupt management ***********************************/\r\n  if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)\r\n  {\r\n    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)\r\n    {\r\n      /* Clear the direct mode error flag */\r\n      regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;\r\n\r\n      /* Update error code */\r\n      hdma->ErrorCode |= HAL_DMA_ERROR_DME;\r\n    }\r\n  }\r\n  /* Half Transfer Complete Interrupt management ******************************/\r\n  if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)\r\n  {\r\n    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)\r\n    {\r\n      /* Clear the half transfer complete flag */\r\n      regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;\r\n      \r\n      /* Multi_Buffering mode enabled */\r\n      if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)\r\n      {\r\n        /* Current memory buffer used is Memory 0 */\r\n        if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)\r\n        {\r\n          if(hdma->XferHalfCpltCallback != NULL)\r\n          {\r\n            /* Half transfer callback */\r\n            hdma->XferHalfCpltCallback(hdma);\r\n          }\r\n        }\r\n        /* Current memory buffer used is Memory 1 */\r\n        else\r\n        {\r\n          if(hdma->XferM1HalfCpltCallback != NULL)\r\n          {\r\n            /* Half transfer callback */\r\n            hdma->XferM1HalfCpltCallback(hdma);\r\n          }\r\n        }\r\n      }\r\n      else\r\n      {\r\n        /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */\r\n        if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)\r\n        {\r\n          /* Disable the half transfer interrupt */\r\n          hdma->Instance->CR  &= ~(DMA_IT_HT);\r\n        }\r\n        \r\n        if(hdma->XferHalfCpltCallback != NULL)\r\n        {\r\n          /* Half transfer callback */\r\n          hdma->XferHalfCpltCallback(hdma);\r\n        }\r\n      }\r\n    }\r\n  }\r\n  /* Transfer Complete Interrupt management ***********************************/\r\n  if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)\r\n  {\r\n    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)\r\n    {\r\n      /* Clear the transfer complete flag */\r\n      regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;\r\n      \r\n      if(HAL_DMA_STATE_ABORT == hdma->State)\r\n      {\r\n        /* Disable all the transfer interrupts */\r\n        hdma->Instance->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);\r\n        hdma->Instance->FCR &= ~(DMA_IT_FE);\r\n        \r\n        if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))\r\n        {\r\n          hdma->Instance->CR  &= ~(DMA_IT_HT);\r\n        }\r\n\r\n        /* Clear all interrupt flags at correct offset within the register */\r\n        regs->IFCR = 0x3FU << hdma->StreamIndex;\r\n\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hdma);\r\n         \r\n        /* Change the DMA state */\r\n        hdma->State = HAL_DMA_STATE_READY;\r\n\t\r\n        if(hdma->XferAbortCallback != NULL)\r\n        {\r\n          hdma->XferAbortCallback(hdma);\r\n        }\r\n        return;\r\n      }\r\n      \r\n      if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)\r\n      {\r\n        /* Current memory buffer used is Memory 0 */\r\n        if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)\r\n        {\r\n          if(hdma->XferM1CpltCallback != NULL)\r\n          {\r\n            /* Transfer complete Callback for memory1 */\r\n            hdma->XferM1CpltCallback(hdma);\r\n          }\r\n        }\r\n        /* Current memory buffer used is Memory 1 */\r\n        else\r\n        {\r\n          if(hdma->XferCpltCallback != NULL)\r\n          {\r\n            /* Transfer complete Callback for memory0 */\r\n            hdma->XferCpltCallback(hdma);\r\n          }\r\n        }\r\n      }\r\n      /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */\r\n      else\r\n      {\r\n        if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)\r\n        {\r\n          /* Disable the transfer complete interrupt */\r\n          hdma->Instance->CR  &= ~(DMA_IT_TC);\r\n\r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hdma);\r\n          \r\n          /* Change the DMA state */\r\n          hdma->State = HAL_DMA_STATE_READY;\r\n        }\r\n        \r\n        if(hdma->XferCpltCallback != NULL)\r\n        {\r\n          /* Transfer complete callback */\r\n          hdma->XferCpltCallback(hdma);\r\n        }\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* manage error case */\r\n  if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)\r\n  {\r\n    if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)\r\n    {\r\n      hdma->State = HAL_DMA_STATE_ABORT;\r\n      \r\n      /* Disable the stream */\r\n      __HAL_DMA_DISABLE(hdma);\r\n      \r\n      do\r\n      {\r\n        if (++count > timeout)\r\n        {\r\n          break;\r\n        }\r\n      }\r\n      while((hdma->Instance->CR & DMA_SxCR_EN) != RESET);\r\n\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hdma);\r\n\r\n      /* Change the DMA state */\r\n      hdma->State = HAL_DMA_STATE_READY;\r\n    }\r\n    \r\n    if(hdma->XferErrorCallback != NULL)\r\n    {\r\n      /* Transfer error callback */\r\n      hdma->XferErrorCallback(hdma);\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Register callbacks\r\n  * @param  hdma:                 pointer to a DMA_HandleTypeDef structure that contains\r\n  *                               the configuration information for the specified DMA Stream.\r\n  * @param  CallbackID:           User Callback identifer\r\n  *                               a DMA_HandleTypeDef structure as parameter.\r\n  * @param  pCallback:            pointer to private callbacsk function which has pointer to \r\n  *                               a DMA_HandleTypeDef structure as parameter.\r\n  * @retval HAL status\r\n  */                      \r\nHAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))\r\n{\r\n\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hdma);\r\n\r\n  if(HAL_DMA_STATE_READY == hdma->State)\r\n  {\r\n    switch (CallbackID)\r\n    {\r\n    case  HAL_DMA_XFER_CPLT_CB_ID:\r\n      hdma->XferCpltCallback = pCallback;\r\n      break;\r\n      \r\n    case  HAL_DMA_XFER_HALFCPLT_CB_ID:\r\n      hdma->XferHalfCpltCallback = pCallback;\r\n      break;\r\n      \r\n    case  HAL_DMA_XFER_M1CPLT_CB_ID:\r\n      hdma->XferM1CpltCallback = pCallback;\r\n      break;\r\n      \r\n    case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:\r\n      hdma->XferM1HalfCpltCallback = pCallback;\r\n      break;\r\n      \r\n    case  HAL_DMA_XFER_ERROR_CB_ID:\r\n      hdma->XferErrorCallback = pCallback;\r\n      break;\r\n      \r\n    case  HAL_DMA_XFER_ABORT_CB_ID:\r\n      hdma->XferAbortCallback = pCallback;\r\n      break;\r\n      \r\n    default:\r\n      break;\r\n    }\r\n  }\r\n  else\r\n  {\r\n    /* Return error status */\r\n    status =  HAL_ERROR;\r\n  }\r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hdma);\r\n  \r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  UnRegister callbacks\r\n  * @param  hdma:                 pointer to a DMA_HandleTypeDef structure that contains\r\n  *                               the configuration information for the specified DMA Stream.\r\n  * @param  CallbackID:           User Callback identifer\r\n  *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.\r\n  * @retval HAL status\r\n  */              \r\nHAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hdma);\r\n  \r\n  if(HAL_DMA_STATE_READY == hdma->State)\r\n  {\r\n    switch (CallbackID)\r\n    {\r\n    case  HAL_DMA_XFER_CPLT_CB_ID:\r\n      hdma->XferCpltCallback = NULL;\r\n      break;\r\n      \r\n    case  HAL_DMA_XFER_HALFCPLT_CB_ID:\r\n      hdma->XferHalfCpltCallback = NULL;\r\n      break;\r\n      \r\n    case  HAL_DMA_XFER_M1CPLT_CB_ID:\r\n      hdma->XferM1CpltCallback = NULL;\r\n      break;\r\n      \r\n    case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:\r\n      hdma->XferM1HalfCpltCallback = NULL;\r\n      break;\r\n      \r\n    case  HAL_DMA_XFER_ERROR_CB_ID:\r\n      hdma->XferErrorCallback = NULL;\r\n      break;\r\n      \r\n    case  HAL_DMA_XFER_ABORT_CB_ID:\r\n      hdma->XferAbortCallback = NULL;\r\n      break; \r\n      \r\n    case   HAL_DMA_XFER_ALL_CB_ID:\r\n      hdma->XferCpltCallback = NULL;\r\n      hdma->XferHalfCpltCallback = NULL;\r\n      hdma->XferM1CpltCallback = NULL;\r\n      hdma->XferM1HalfCpltCallback = NULL;\r\n      hdma->XferErrorCallback = NULL;\r\n      hdma->XferAbortCallback = NULL;\r\n      break; \r\n      \r\n    default:\r\n      status = HAL_ERROR;\r\n      break;\r\n    }\r\n  }\r\n  else\r\n  {\r\n    status = HAL_ERROR;\r\n  }\r\n  \r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hdma);\r\n  \r\n  return status;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup DMA_Exported_Functions_Group3\r\n  *\r\n@verbatim\r\n ===============================================================================\r\n                    ##### State and Errors functions #####\r\n ===============================================================================\r\n    [..]\r\n    This subsection provides functions allowing to\r\n      (+) Check the DMA state\r\n      (+) Get error code\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Returns the DMA state.\r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified DMA Stream.\r\n  * @retval HAL state\r\n  */\r\nHAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)\r\n{\r\n  return hdma->State;\r\n}\r\n\r\n/**\r\n  * @brief  Return the DMA error code\r\n  * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains\r\n  *              the configuration information for the specified DMA Stream.\r\n  * @retval DMA Error Code\r\n  */\r\nuint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)\r\n{\r\n  return hdma->ErrorCode;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup DMA_Private_Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Sets the DMA Transfer parameter.\r\n  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains\r\n  *                     the configuration information for the specified DMA Stream.\r\n  * @param  SrcAddress: The source memory Buffer address\r\n  * @param  DstAddress: The destination memory Buffer address\r\n  * @param  DataLength: The length of data to be transferred from source to destination\r\n  * @retval HAL status\r\n  */\r\nstatic void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r\n{\r\n  /* Clear DBM bit */\r\n  hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);\r\n\r\n  /* Configure DMA Stream data length */\r\n  hdma->Instance->NDTR = DataLength;\r\n\r\n  /* Peripheral to Memory */\r\n  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)\r\n  {\r\n    /* Configure DMA Stream destination address */\r\n    hdma->Instance->PAR = DstAddress;\r\n\r\n    /* Configure DMA Stream source address */\r\n    hdma->Instance->M0AR = SrcAddress;\r\n  }\r\n  /* Memory to Peripheral */\r\n  else\r\n  {\r\n    /* Configure DMA Stream source address */\r\n    hdma->Instance->PAR = SrcAddress;\r\n    \r\n    /* Configure DMA Stream destination address */\r\n    hdma->Instance->M0AR = DstAddress;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Returns the DMA Stream base address depending on stream number\r\n  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains\r\n  *                     the configuration information for the specified DMA Stream. \r\n  * @retval Stream base address\r\n  */\r\nstatic uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)\r\n{\r\n  uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;\r\n  \r\n  /* lookup table for necessary bitshift of flags within status registers */\r\n  static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};\r\n  hdma->StreamIndex = flagBitshiftOffset[stream_number];\r\n  \r\n  if (stream_number > 3U)\r\n  {\r\n    /* return pointer to HISR and HIFCR */\r\n    hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U);\r\n  }\r\n  else\r\n  {\r\n    /* return pointer to LISR and LIFCR */\r\n    hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU));\r\n  }\r\n  \r\n  return hdma->StreamBaseAddress;\r\n}\r\n\r\n/**\r\n  * @brief  Check compatibility between FIFO threshold level and size of the memory burst\r\n  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains\r\n  *                     the configuration information for the specified DMA Stream. \r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  uint32_t tmp = hdma->Init.FIFOThreshold;\r\n  \r\n  /* Memory Data size equal to Byte */\r\n  if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)\r\n  {\r\n    switch (tmp)\r\n    {\r\n      case DMA_FIFO_THRESHOLD_1QUARTERFULL:\r\n        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)\r\n        {\r\n          status = HAL_ERROR;\r\n        }\r\n        break;\r\n      case DMA_FIFO_THRESHOLD_HALFFULL:\r\n        if (hdma->Init.MemBurst == DMA_MBURST_INC16)\r\n        {\r\n          status = HAL_ERROR;\r\n        }\r\n        break;\r\n      case DMA_FIFO_THRESHOLD_3QUARTERSFULL:\r\n        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)\r\n        {\r\n          status = HAL_ERROR;\r\n        }\r\n        break;\r\n      case DMA_FIFO_THRESHOLD_FULL:\r\n        break;\r\n      default:\r\n        break;\r\n    }\r\n  }\r\n  \r\n  /* Memory Data size equal to Half-Word */\r\n  else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)\r\n  {\r\n    switch (tmp)\r\n    {\r\n      case DMA_FIFO_THRESHOLD_1QUARTERFULL:\r\n        status = HAL_ERROR;\r\n        break;\r\n      case DMA_FIFO_THRESHOLD_HALFFULL:\r\n        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)\r\n        {\r\n          status = HAL_ERROR;\r\n        }\r\n        break;\r\n      case DMA_FIFO_THRESHOLD_3QUARTERSFULL:\r\n        status = HAL_ERROR;\r\n        break;\r\n      case DMA_FIFO_THRESHOLD_FULL:\r\n        if (hdma->Init.MemBurst == DMA_MBURST_INC16)\r\n        {\r\n          status = HAL_ERROR;\r\n        }\r\n        break;   \r\n      default:\r\n        break;\r\n    }\r\n  }\r\n  \r\n  /* Memory Data size equal to Word */\r\n  else\r\n  {\r\n    switch (tmp)\r\n    {\r\n      case DMA_FIFO_THRESHOLD_1QUARTERFULL:\r\n      case DMA_FIFO_THRESHOLD_HALFFULL:\r\n      case DMA_FIFO_THRESHOLD_3QUARTERSFULL:\r\n        status = HAL_ERROR;\r\n        break;\r\n      case DMA_FIFO_THRESHOLD_FULL:\r\n        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)\r\n        {\r\n          status = HAL_ERROR;\r\n        }\r\n\t\tbreak;\r\n      default:\r\n        break;\r\n    }\r\n  } \r\n  \r\n  return status; \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_DMA_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_dma2d.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   DMA2D HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the DMA2D peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + IO operation functions\r\n  *           + Peripheral Control functions \r\n  *           + Peripheral State and Errors functions\r\n  *\r\n  @verbatim\r\n  ==============================================================================\r\n                        ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]\r\n      (#) Program the required configuration through the following parameters:   \r\n          the transfer mode, the output color mode and the output offset using \r\n          HAL_DMA2D_Init() function.\r\n\r\n      (#) Program the required configuration through the following parameters:   \r\n          the input color mode, the input color, the input alpha value, the alpha mode,\r\n          the red/blue swap mode, the inverted alpha mode and the input offset using \r\n          HAL_DMA2D_ConfigLayer() function for foreground or/and background layer.\r\n          \r\n     *** Polling mode IO operation ***\r\n     =================================   \r\n    [..]        \r\n       (#) Configure pdata parameter (explained hereafter), destination and data length \r\n           and enable the transfer using HAL_DMA2D_Start(). \r\n       (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage\r\n           user can specify the value of timeout according to his end application.\r\n               \r\n     *** Interrupt mode IO operation ***    \r\n     ===================================\r\n     [..] \r\n       (#) Configure pdata parameter, destination and data length and enable \r\n           the transfer using HAL_DMA2D_Start_IT(). \r\n       (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine.\r\n       (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can \r\n           add his own function by customization of function pointer XferCpltCallback (member \r\n           of DMA2D handle structure). \r\n       (#) In case of error, the HAL_DMA2D_IRQHandler() function will call the callback \r\n           XferErrorCallback.            \r\n\r\n         -@-   In Register-to-Memory transfer mode, pdata parameter is the register\r\n               color, in Memory-to-memory or Memory-to-Memory with pixel format\r\n               conversion pdata is the source address.\r\n\r\n         -@-   Configure the foreground source address, the background source address, \r\n               the destination and data length then Enable the transfer using \r\n               HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()\r\n               in interrupt mode.\r\n               \r\n         -@-   HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions\r\n               are used if the memory to memory with blending transfer mode is selected.\r\n                   \r\n      (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling\r\n          mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode.\r\n\r\n      (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent()\r\n          \r\n      (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two \r\n          consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime()\r\n          and enable/disable the functionality  with the APIs HAL_DMA2D_EnableDeadTime() or\r\n          HAL_DMA2D_DisableDeadTime().          \r\n   \r\n      (#) The transfer can be suspended, resumed and aborted using the following\r\n          functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().\r\n          \r\n      (#) The CLUT loading can be suspended, resumed and aborted using the following\r\n          functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(), \r\n          HAL_DMA2D_CLUTLoading_Abort().                \r\n                     \r\n      (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState().   \r\n      \r\n      (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError().                         \r\n\r\n     *** DMA2D HAL driver macros list ***\r\n     ============================================= \r\n     [..]\r\n       Below the list of most used macros in DMA2D HAL driver :\r\n       \r\n      (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.\r\n      (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.\r\n      (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.\r\n      (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.\r\n      (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.\r\n      (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not.     \r\n     \r\n     [..] \r\n      (@) You can refer to the DMA2D HAL driver header file for more useful macros\r\n                                  \r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup DMA2D  DMA2D\r\n  * @brief DMA2D HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_DMA2D_MODULE_ENABLED\r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @defgroup DMA2D_Private_Constants DMA2D Private Constants\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup DMA2D_TimeOut DMA2D Time Out \r\n  * @{\r\n  */  \r\n#define DMA2D_TIMEOUT_ABORT           ((uint32_t)1000)  /*!<  1s  */\r\n#define DMA2D_TIMEOUT_SUSPEND         ((uint32_t)1000)  /*!<  1s  */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DMA2D_Shifts DMA2D Shifts \r\n  * @{\r\n  */                                     \r\n#define DMA2D_POSITION_FGPFCCR_CS     (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CS)    /*!< Required left shift to set foreground CLUT size */\r\n#define DMA2D_POSITION_BGPFCCR_CS     (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CS)    /*!< Required left shift to set background CLUT size */\r\n                                                                                 \r\n#define DMA2D_POSITION_FGPFCCR_CCM    (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CCM)   /*!< Required left shift to set foreground CLUT color mode */\r\n#define DMA2D_POSITION_BGPFCCR_CCM    (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CCM)   /*!< Required left shift to set background CLUT color mode */\r\n                                                                                 \r\n#define DMA2D_POSITION_OPFCCR_AI      (uint32_t)POSITION_VAL(DMA2D_OPFCCR_AI)     /*!< Required left shift to set output alpha inversion     */\r\n#define DMA2D_POSITION_FGPFCCR_AI     (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AI)    /*!< Required left shift to set foreground alpha inversion */ \r\n#define DMA2D_POSITION_BGPFCCR_AI     (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AI)    /*!< Required left shift to set background alpha inversion */ \r\n\r\n#define DMA2D_POSITION_OPFCCR_RBS     (uint32_t)POSITION_VAL(DMA2D_OPFCCR_RBS)    /*!< Required left shift to set output Red/Blue swap     */                                                                                 \r\n#define DMA2D_POSITION_FGPFCCR_RBS    (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_RBS)   /*!< Required left shift to set foreground Red/Blue swap */\r\n#define DMA2D_POSITION_BGPFCCR_RBS    (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_RBS)   /*!< Required left shift to set background Red/Blue swap */\r\n                                                                                 \r\n#define DMA2D_POSITION_AMTCR_DT       (uint32_t)POSITION_VAL(DMA2D_AMTCR_DT)      /*!< Required left shift to set deadtime value */\r\n                                                                                 \r\n#define DMA2D_POSITION_FGPFCCR_AM     (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AM)    /*!< Required left shift to set foreground alpha mode */\r\n#define DMA2D_POSITION_BGPFCCR_AM     (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AM)    /*!< Required left shift to set background alpha mode */\r\n\r\n#define DMA2D_POSITION_FGPFCCR_ALPHA  (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_ALPHA) /*!< Required left shift to set foreground alpha value */\r\n#define DMA2D_POSITION_BGPFCCR_ALPHA  (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_ALPHA) /*!< Required left shift to set background alpha value */\r\n\r\n#define DMA2D_POSITION_NLR_PL         (uint32_t)POSITION_VAL(DMA2D_NLR_PL)        /*!< Required left shift to set pixels per lines value */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/** @addtogroup DMA2D_Private_Functions_Prototypes\r\n  * @{\r\n  */\r\nstatic void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions\r\n *  @brief   Initialization and Configuration functions\r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                ##### Initialization and Configuration functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Initialize and configure the DMA2D\r\n      (+) De-initialize the DMA2D \r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n    \r\n/**\r\n  * @brief  Initialize the DMA2D according to the specified\r\n  *         parameters in the DMA2D_InitTypeDef and create the associated handle.\r\n  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                 the configuration information for the DMA2D.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)\r\n{ \r\n  /* Check the DMA2D peripheral state */\r\n  if(hdma2d == NULL)\r\n  {\r\n     return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));\r\n  assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));\r\n  assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));\r\n  assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));\r\n\r\n  if(hdma2d->State == HAL_DMA2D_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    hdma2d->Lock = HAL_UNLOCKED;\r\n    /* Init the low level hardware */\r\n    HAL_DMA2D_MspInit(hdma2d);\r\n  }\r\n  \r\n  /* Change DMA2D peripheral state */\r\n  hdma2d->State = HAL_DMA2D_STATE_BUSY;  \r\n\r\n  /* DMA2D CR register configuration -------------------------------------------*/\r\n  MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);\r\n\r\n  /* DMA2D OPFCCR register configuration ---------------------------------------*/\r\n  MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);\r\n\r\n  /* DMA2D OOR register configuration ------------------------------------------*/  \r\n  MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);  \r\n\r\n#if defined (DMA2D_OPFCCR_AI)\r\n  /* DMA2D OPFCCR AI fields setting (Output Alpha Inversion)*/\r\n  MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_AI, (hdma2d->Init.AlphaInverted << DMA2D_POSITION_OPFCCR_AI));\r\n#endif /* DMA2D_OPFCCR_AI */ \r\n  \r\n#if defined (DMA2D_OPFCCR_RBS) \r\n  MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_RBS,(hdma2d->Init.RedBlueSwap << DMA2D_POSITION_OPFCCR_RBS));\r\n#endif /* DMA2D_OPFCCR_RBS */\r\n  \r\n\r\n  /* Update error code */\r\n  hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;\r\n\r\n  /* Initialize the DMA2D state*/\r\n  hdma2d->State  = HAL_DMA2D_STATE_READY;\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Deinitializes the DMA2D peripheral registers to their default reset\r\n  *         values.\r\n  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                 the configuration information for the DMA2D.\r\n  * @retval None\r\n  */\r\n\r\nHAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)\r\n{\r\n  \r\n  /* Check the DMA2D peripheral state */\r\n  if(hdma2d == NULL)\r\n  {\r\n     return HAL_ERROR;\r\n  }\r\n  \r\n  /* Before aborting any DMA2D transfer or CLUT loading, check\r\n     first whether or not DMA2D clock is enabled */\r\n  if (__HAL_RCC_DMA2D_IS_CLK_ENABLED())\r\n  {\r\n    /* Abort DMA2D transfer if any */\r\n    if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)\r\n    {\r\n      if (HAL_DMA2D_Abort(hdma2d) != HAL_OK)\r\n      {\r\n        /* Issue when aborting DMA2D transfer */       \r\n        return HAL_ERROR;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* Abort background CLUT loading if any */\r\n      if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)\r\n      {  \r\n        if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0) != HAL_OK)        \r\n        {\r\n          /* Issue when aborting background CLUT loading */     \r\n          return HAL_ERROR;\r\n        }\r\n      }\r\n      else\r\n      {\r\n        /* Abort foreground CLUT loading if any */\r\n        if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)\r\n        {\r\n          if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1) != HAL_OK)  \r\n          {\r\n            /* Issue when aborting foreground CLUT loading */     \r\n            return HAL_ERROR;\r\n          }        \r\n        }\r\n      }\r\n    }\r\n  }\r\n\r\n            \r\n  /* Carry on with de-initialization of low level hardware */\r\n  HAL_DMA2D_MspDeInit(hdma2d);\r\n  \r\n  /* Reset DMA2D control registers*/\r\n  hdma2d->Instance->CR = 0;\r\n  hdma2d->Instance->FGOR = 0;\r\n  hdma2d->Instance->BGOR = 0;  \r\n  hdma2d->Instance->FGPFCCR = 0;\r\n  hdma2d->Instance->BGPFCCR = 0;  \r\n  hdma2d->Instance->OPFCCR = 0;\r\n\r\n  /* Update error code */\r\n  hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;\r\n  \r\n  /* Initialize the DMA2D state*/\r\n  hdma2d->State  = HAL_DMA2D_STATE_RESET;\r\n  \r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hdma2d);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the DMA2D MSP.\r\n  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                 the configuration information for the DMA2D.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdma2d);\r\n\r\n  /* NOTE : This function should not be modified; when the callback is needed,\r\n            the HAL_DMA2D_MspInit can be implemented in the user file.\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the DMA2D MSP.\r\n  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                 the configuration information for the DMA2D.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdma2d);\r\n\r\n  /* NOTE : This function should not be modified; when the callback is needed,\r\n            the HAL_DMA2D_MspDeInit can be implemented in the user file.\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions\r\n *  @brief   IO operation functions  \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                      #####  IO operation functions  #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Configure the pdata, destination address and data size then \r\n          start the DMA2D transfer.\r\n      (+) Configure the source for foreground and background, destination address \r\n          and data size then start a MultiBuffer DMA2D transfer.\r\n      (+) Configure the pdata, destination address and data size then \r\n          start the DMA2D transfer with interrupt.\r\n      (+) Configure the source for foreground and background, destination address \r\n          and data size then start a MultiBuffer DMA2D transfer with interrupt.\r\n      (+) Abort DMA2D transfer.\r\n      (+) Suspend DMA2D transfer.\r\n      (+) Resume DMA2D transfer. \r\n      (+) Enable CLUT transfer.      \r\n      (+) Configure CLUT loading then start transfer in polling mode.\r\n      (+) Configure CLUT loading then start transfer in interrupt mode.\r\n      (+) Abort DMA2D CLUT loading.\r\n      (+) Suspend DMA2D CLUT loading.\r\n      (+) Resume DMA2D CLUT loading. \r\n      (+) Poll for transfer complete.\r\n      (+) handle DMA2D interrupt request.\r\n      (+) Transfer watermark callback.\r\n      (+) CLUT Transfer Complete callback.\r\n        \r\n        \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Start the DMA2D Transfer.\r\n  * @param  hdma2d:     Pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                     the configuration information for the DMA2D.  \r\n  * @param  pdata:      Configure the source memory Buffer address if \r\n  *                     Memory-to-Memory or Memory-to-Memory with pixel format \r\n  *                     conversion mode is selected, or configure \r\n  *                     the color value if Register-to-Memory mode is selected.\r\n  * @param  DstAddress: The destination memory Buffer address.\r\n  * @param  Width:      The width of data to be transferred from source to destination (expressed in number of pixels per line).\r\n  * @param  Height:     The height of data to be transferred from source to destination (expressed in number of lines).\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,  uint32_t Height)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_DMA2D_LINE(Height));\r\n  assert_param(IS_DMA2D_PIXEL(Width));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hdma2d);\r\n\r\n  /* Change DMA2D peripheral state */\r\n  hdma2d->State = HAL_DMA2D_STATE_BUSY;\r\n  \r\n  /* Configure the source, destination address and the data size */\r\n  DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);\r\n\r\n  /* Enable the Peripheral */\r\n  __HAL_DMA2D_ENABLE(hdma2d);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Start the DMA2D Transfer with interrupt enabled.\r\n  * @param  hdma2d:     Pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                     the configuration information for the DMA2D.  \r\n  * @param  pdata:      Configure the source memory Buffer address if \r\n  *                     the Memory-to-Memory or Memory-to-Memory with pixel format \r\n  *                     conversion mode is selected, or configure \r\n  *                     the color value if Register-to-Memory mode is selected.\r\n  * @param  DstAddress: The destination memory Buffer address.\r\n  * @param  Width:      The width of data to be transferred from source to destination (expressed in number of pixels per line).\r\n  * @param  Height:     The height of data to be transferred from source to destination (expressed in number of lines).\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,  uint32_t Height)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_DMA2D_LINE(Height));\r\n  assert_param(IS_DMA2D_PIXEL(Width));\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hdma2d);\r\n\r\n  /* Change DMA2D peripheral state */\r\n  hdma2d->State = HAL_DMA2D_STATE_BUSY;\r\n\r\n  /* Configure the source, destination address and the data size */\r\n  DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);\r\n\r\n  /* Enable the transfer complete, transfer error and configuration error interrupts */\r\n  __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);\r\n\r\n  /* Enable the Peripheral */\r\n  __HAL_DMA2D_ENABLE(hdma2d);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Start the multi-source DMA2D Transfer.\r\n  * @param  hdma2d:      Pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                      the configuration information for the DMA2D.  \r\n  * @param  SrcAddress1: The source memory Buffer address for the foreground layer.\r\n  * @param  SrcAddress2: The source memory Buffer address for the background layer.\r\n  * @param  DstAddress:  The destination memory Buffer address.\r\n  * @param  Width:       The width of data to be transferred from source to destination (expressed in number of pixels per line).\r\n  * @param  Height:      The height of data to be transferred from source to destination (expressed in number of lines).\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t  SrcAddress2, uint32_t DstAddress, uint32_t Width,  uint32_t Height)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_DMA2D_LINE(Height));\r\n  assert_param(IS_DMA2D_PIXEL(Width));  \r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hdma2d);\r\n\r\n  /* Change DMA2D peripheral state */\r\n  hdma2d->State = HAL_DMA2D_STATE_BUSY; \r\n\r\n  /* Configure DMA2D Stream source2 address */\r\n  WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);\r\n\r\n  /* Configure the source, destination address and the data size */\r\n  DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);\r\n\r\n  /* Enable the Peripheral */\r\n  __HAL_DMA2D_ENABLE(hdma2d);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Start the multi-source DMA2D Transfer with interrupt enabled.\r\n  * @param  hdma2d:     Pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                     the configuration information for the DMA2D.  \r\n  * @param  SrcAddress1: The source memory Buffer address for the foreground layer.\r\n  * @param  SrcAddress2: The source memory Buffer address for the background layer.\r\n  * @param  DstAddress:  The destination memory Buffer address.\r\n  * @param  Width:       The width of data to be transferred from source to destination (expressed in number of pixels per line).\r\n  * @param  Height:      The height of data to be transferred from source to destination (expressed in number of lines).         \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t  SrcAddress2, uint32_t DstAddress, uint32_t Width,  uint32_t Height)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_DMA2D_LINE(Height));\r\n  assert_param(IS_DMA2D_PIXEL(Width));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hdma2d);\r\n\r\n  /* Change DMA2D peripheral state */\r\n  hdma2d->State = HAL_DMA2D_STATE_BUSY;\r\n \r\n  /* Configure DMA2D Stream source2 address */\r\n  WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);\r\n\r\n  /* Configure the source, destination address and the data size */\r\n  DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);\r\n  \r\n  /* Enable the transfer complete, transfer error and configuration error interrupts */\r\n  __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);\r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_DMA2D_ENABLE(hdma2d);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Abort the DMA2D Transfer.\r\n  * @param  hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                  the configuration information for the DMA2D.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)\r\n{\r\n  uint32_t tickstart = 0;\r\n\r\n  /* Abort the DMA2D transfer */\r\n  /* START bit is reset to make sure not to set it again, in the event the HW clears it\r\n     between the register read and the register write by the CPU (writing 0 has no \r\n     effect on START bitvalue). */\r\n   MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT);\r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Check if the DMA2D is effectively disabled */\r\n  while((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)\r\n  {\r\n    if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)\r\n    {\r\n      /* Update error code */\r\n      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;\r\n      \r\n      /* Change the DMA2D state */\r\n      hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;\r\n      \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hdma2d);\r\n      \r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n\r\n  /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */\r\n  __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);  \r\n\r\n  /* Change the DMA2D state*/\r\n  hdma2d->State = HAL_DMA2D_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hdma2d);  \r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Suspend the DMA2D Transfer.\r\n  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                 the configuration information for the DMA2D. \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)\r\n{\r\n  uint32_t tickstart = 0;\r\n\r\n  /* Suspend the DMA2D transfer */\r\n  /* START bit is reset to make sure not to set it again, in the event the HW clears it\r\n     between the register read and the register write by the CPU (writing 0 has no \r\n     effect on START bitvalue). */\r\n  MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP);\r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Check if the DMA2D is effectively suspended */\r\n  while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \\\r\n    && ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START))\r\n  {\r\n    if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)\r\n    {\r\n      /* Update error code */\r\n      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;\r\n      \r\n      /* Change the DMA2D state */\r\n      hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;\r\n      \r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  \r\n   /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */\r\n  if ((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)\r\n  {    \r\n    hdma2d->State = HAL_DMA2D_STATE_SUSPEND;\r\n  }\r\n  else\r\n  {\r\n    /* Make sure SUSP bit is cleared since it is meaningless \r\n       when no tranfer is on-going */\r\n    CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Resume the DMA2D Transfer.\r\n  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                 the configuration information for the DMA2D.  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)\r\n{\r\n  /* Check the SUSP and START bits */\r\n  if((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))\r\n  {\r\n    /* Ongoing transfer is suspended: change the DMA2D state before resuming */\r\n    hdma2d->State = HAL_DMA2D_STATE_BUSY;\r\n  }\r\n\r\n  /* Resume the DMA2D transfer */\r\n  /* START bit is reset to make sure not to set it again, in the event the HW clears it\r\n     between the register read and the register write by the CPU (writing 0 has no \r\n     effect on START bitvalue). */\r\n  CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START));  \r\n\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Enable the DMA2D CLUT Transfer.\r\n  * @param  hdma2d:   Pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                   the configuration information for the DMA2D.\r\n  * @param  LayerIdx: DMA2D Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0(background) / 1(foreground)\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)\r\n{  \r\n  /* Check the parameters */\r\n  assert_param(IS_DMA2D_LAYER(LayerIdx));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hdma2d);\r\n  \r\n  /* Change DMA2D peripheral state */\r\n  hdma2d->State = HAL_DMA2D_STATE_BUSY;  \r\n  \r\n  if(LayerIdx == 0)\r\n  {\r\n    /* Enable the background CLUT loading */\r\n    SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);\r\n  }\r\n  else\r\n  {\r\n    /* Enable the foreground CLUT loading */\r\n    SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);    \r\n  }\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Start DMA2D CLUT Loading.\r\n  * @param  hdma2d:   Pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                   the configuration information for the DMA2D.\r\n  * @param  CLUTCfg:  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains\r\n  *                   the configuration information for the color look up table.\r\n  * @param  LayerIdx: DMA2D Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0(background) / 1(foreground)\r\n  * @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT().                    \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_DMA2D_LAYER(LayerIdx));   \r\n  assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));\r\n  assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hdma2d);\r\n  \r\n  /* Change DMA2D peripheral state */\r\n  hdma2d->State = HAL_DMA2D_STATE_BUSY;   \r\n    \r\n  /* Configure the CLUT of the background DMA2D layer */\r\n  if(LayerIdx == 0)\r\n  {\r\n    /* Write background CLUT memory address */\r\n    WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);\r\n    \r\n    /* Write background CLUT size and CLUT color mode */\r\n    MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), \r\n            ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));\r\n\r\n    /* Enable the CLUT loading for the background */\r\n    SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);\r\n  }\r\n  /* Configure the CLUT of the foreground DMA2D layer */\r\n  else\r\n  {\r\n    /* Write foreground CLUT memory address */\r\n    WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);\r\n    \r\n    /* Write foreground CLUT size and CLUT color mode */\r\n    MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), \r\n            ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));       \r\n    \r\n /* Enable the CLUT loading for the foreground */\r\n    SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);  \r\n  }\r\n    \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Start DMA2D CLUT Loading with interrupt enabled.\r\n  * @param  hdma2d:   Pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                   the configuration information for the DMA2D.\r\n  * @param  CLUTCfg:  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains\r\n  *                   the configuration information for the color look up table.\r\n  * @param  LayerIdx: DMA2D Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0(background) / 1(foreground)\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_DMA2D_LAYER(LayerIdx));   \r\n  assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));\r\n  assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hdma2d);\r\n  \r\n  /* Change DMA2D peripheral state */\r\n  hdma2d->State = HAL_DMA2D_STATE_BUSY;   \r\n    \r\n  /* Configure the CLUT of the background DMA2D layer */\r\n  if(LayerIdx == 0)\r\n  {\r\n    /* Write background CLUT memory address */\r\n    WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);\r\n    \r\n    /* Write background CLUT size and CLUT color mode */\r\n    MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), \r\n            ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));\r\n            \r\n    /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */\r\n    __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);            \r\n\r\n    /* Enable the CLUT loading for the background */\r\n    SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);\r\n  }\r\n  /* Configure the CLUT of the foreground DMA2D layer */\r\n  else\r\n  {\r\n    /* Write foreground CLUT memory address */\r\n    WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);\r\n    \r\n    /* Write foreground CLUT size and CLUT color mode */\r\n    MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), \r\n            ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));\r\n            \r\n    /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */\r\n    __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);                   \r\n    \r\n    /* Enable the CLUT loading for the foreground */\r\n    SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);  \r\n  }\r\n    \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Abort the DMA2D CLUT loading.\r\n  * @param  hdma2d : Pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                  the configuration information for the DMA2D.\r\n  * @param  LayerIdx: DMA2D Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0(background) / 1(foreground)  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)\r\n{\r\n  uint32_t tickstart  = 0;\r\n  __IO uint32_t * reg =  &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */\r\n\r\n  /* Abort the CLUT loading */\r\n  SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);\r\n  \r\n  /* If foreground CLUT loading is considered, update local variables */ \r\n  if(LayerIdx == 1)\r\n  {\r\n    reg  = &(hdma2d->Instance->FGPFCCR);\r\n  }\r\n\r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n \r\n  /* Check if the CLUT loading is aborted */          \r\n  while((*reg & DMA2D_BGPFCCR_START) != RESET)\r\n  {\r\n    if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)\r\n    {\r\n      /* Update error code */\r\n      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;\r\n      \r\n      /* Change the DMA2D state */\r\n      hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;\r\n      \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hdma2d);\r\n      \r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n\r\n  /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */\r\n  __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);      \r\n   \r\n  /* Change the DMA2D state*/\r\n  hdma2d->State = HAL_DMA2D_STATE_READY;\r\n     \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hdma2d);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Suspend the DMA2D CLUT loading.\r\n  * @param  hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                 the configuration information for the DMA2D. \r\n  * @param  LayerIdx: DMA2D Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0(background) / 1(foreground)    \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)\r\n{\r\n  uint32_t tickstart = 0;\r\n  __IO uint32_t * reg =  &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */  \r\n\r\n  /* Suspend the CLUT loading */\r\n  SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); \r\n  \r\n  /* If foreground CLUT loading is considered, update local variables */ \r\n  if(LayerIdx == 1)\r\n  {\r\n    reg  = &(hdma2d->Instance->FGPFCCR);\r\n  }   \r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  /* Check if the CLUT loading is suspended */\r\n  while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \\\r\n    && ((*reg & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))\r\n  {\r\n    if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)\r\n    {\r\n      /* Update error code */\r\n      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;\r\n      \r\n      /* Change the DMA2D state */\r\n      hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;\r\n      \r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  \r\n   /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */\r\n  if ((*reg & DMA2D_BGPFCCR_START) != RESET)\r\n  {    \r\n    hdma2d->State = HAL_DMA2D_STATE_SUSPEND;\r\n  }\r\n  else\r\n  {\r\n    /* Make sure SUSP bit is cleared since it is meaningless \r\n       when no tranfer is on-going */\r\n    CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);\r\n  }  \r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Resume the DMA2D CLUT loading.\r\n  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                 the configuration information for the DMA2D. \r\n  * @param  LayerIdx: DMA2D Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0(background) / 1(foreground)      \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)\r\n{\r\n  /* Check the SUSP and START bits for background or foreground CLUT loading */\r\n  if(LayerIdx == 0)\r\n  {  \r\n    /* Background CLUT loading suspension check */\r\n    if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)\r\n      && ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))\r\n    {\r\n      /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */\r\n      hdma2d->State = HAL_DMA2D_STATE_BUSY;\r\n    }\r\n  }\r\n  else\r\n  {\r\n    /* Foreground CLUT loading suspension check */\r\n    if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)\r\n      && ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START))\r\n    {\r\n      /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */\r\n      hdma2d->State = HAL_DMA2D_STATE_BUSY;\r\n    }  \r\n  }\r\n\r\n  /* Resume the CLUT loading */\r\n  CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);  \r\n\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n\r\n  * @brief  Polling for transfer complete or CLUT loading.\r\n  * @param  hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                 the configuration information for the DMA2D. \r\n  * @param  Timeout: Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;\r\n  __IO uint32_t isrflags = 0x0;  \r\n\r\n  /* Polling for DMA2D transfer */\r\n  if((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)\r\n  {\r\n   /* Get tick */\r\n   tickstart = HAL_GetTick();\r\n\r\n    while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET)\r\n    {\r\n      isrflags = READ_REG(hdma2d->Instance->ISR); \r\n      if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET)\r\n      {\r\n        if ((isrflags & DMA2D_FLAG_CE) != RESET)\r\n        {\r\n          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;        \r\n        }\r\n        if ((isrflags & DMA2D_FLAG_TE) != RESET)        \r\n        {\r\n          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;        \r\n        }\r\n        /* Clear the transfer and configuration error flags */\r\n        __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);\r\n\r\n        /* Change DMA2D state */\r\n        hdma2d->State = HAL_DMA2D_STATE_ERROR;\r\n\r\n        /* Process unlocked */\r\n        __HAL_UNLOCK(hdma2d);\r\n        \r\n        return HAL_ERROR;\r\n      }\r\n      /* Check for the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n        {\r\n          /* Update error code */\r\n          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;\r\n\r\n          /* Change the DMA2D state */\r\n          hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;\r\n         \r\n          /* Process unlocked */\r\n          __HAL_UNLOCK(hdma2d);\r\n           \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }        \r\n    }\r\n  }\r\n  /* Polling for CLUT loading (foreground or background) */\r\n  if (((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != RESET)  || \r\n      ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) != RESET))\r\n  {\r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n   \r\n    while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET)\r\n    {\r\n      isrflags = READ_REG(hdma2d->Instance->ISR);   \r\n      if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET)        \r\n      {      \r\n        if ((isrflags & DMA2D_FLAG_CAE) != RESET)\r\n        {\r\n          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;        \r\n        }   \r\n        if ((isrflags & DMA2D_FLAG_CE) != RESET)             \r\n        {\r\n          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;        \r\n        }\r\n        if ((isrflags & DMA2D_FLAG_TE) != RESET)        \r\n        {\r\n          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;        \r\n        }\r\n        /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */\r\n        __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);\r\n        \r\n        /* Change DMA2D state */\r\n        hdma2d->State= HAL_DMA2D_STATE_ERROR;\r\n        \r\n        /* Process unlocked */\r\n        __HAL_UNLOCK(hdma2d);\r\n          \r\n        return HAL_ERROR;      \r\n      }      \r\n      /* Check for the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n        {\r\n          /* Update error code */\r\n          hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;\r\n    \r\n          /* Change the DMA2D state */\r\n          hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;\r\n        \r\n          /* Process unlocked */\r\n          __HAL_UNLOCK(hdma2d);\r\n                    \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }      \r\n    }\r\n  }\r\n\r\n  /* Clear the transfer complete and CLUT loading flags */\r\n  __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC);\r\n  \r\n  /* Change DMA2D state */\r\n  hdma2d->State = HAL_DMA2D_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdma2d);\r\n  \r\n  return HAL_OK;\r\n}\r\n/**\r\n  * @brief  Handle DMA2D interrupt request.\r\n  * @param  hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                 the configuration information for the DMA2D.  \r\n  * @retval HAL status\r\n  */\r\nvoid HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)\r\n{\r\n  uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);\r\n  uint32_t crflags = READ_REG(hdma2d->Instance->CR);\r\n        \r\n  /* Transfer Error Interrupt management ***************************************/\r\n  if ((isrflags & DMA2D_FLAG_TE) != RESET)\r\n  {\r\n    if ((crflags & DMA2D_IT_TE) != RESET)    \r\n    {\r\n      /* Disable the transfer Error interrupt */\r\n      __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);  \r\n\r\n      /* Update error code */\r\n      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;\r\n    \r\n      /* Clear the transfer error flag */\r\n      __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);\r\n\r\n      /* Change DMA2D state */\r\n      hdma2d->State = HAL_DMA2D_STATE_ERROR;\r\n\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hdma2d);       \r\n      \r\n      if(hdma2d->XferErrorCallback != NULL)\r\n      {\r\n        /* Transfer error Callback */\r\n        hdma2d->XferErrorCallback(hdma2d);\r\n      }\r\n    }\r\n  }\r\n  /* Configuration Error Interrupt management **********************************/\r\n  if ((isrflags & DMA2D_FLAG_CE) != RESET)\r\n  {\r\n    if ((crflags & DMA2D_IT_CE) != RESET)    \r\n    {  \r\n      /* Disable the Configuration Error interrupt */\r\n      __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);\r\n  \r\n      /* Clear the Configuration error flag */\r\n      __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);\r\n\r\n      /* Update error code */\r\n      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;    \r\n    \r\n      /* Change DMA2D state */\r\n      hdma2d->State = HAL_DMA2D_STATE_ERROR;\r\n\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hdma2d);       \r\n      \r\n      if(hdma2d->XferErrorCallback != NULL)\r\n      {\r\n        /* Transfer error Callback */\r\n        hdma2d->XferErrorCallback(hdma2d);\r\n      }\r\n    }\r\n  }\r\n  /* CLUT access Error Interrupt management ***********************************/\r\n  if ((isrflags & DMA2D_FLAG_CAE) != RESET)\r\n  {\r\n    if ((crflags & DMA2D_IT_CAE) != RESET)    \r\n    {    \r\n      /* Disable the CLUT access error interrupt */\r\n      __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);\r\n  \r\n      /* Clear the CLUT access error flag */\r\n      __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);\r\n\r\n      /* Update error code */\r\n      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;    \r\n    \r\n      /* Change DMA2D state */\r\n      hdma2d->State = HAL_DMA2D_STATE_ERROR;\r\n\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hdma2d);       \r\n      \r\n      if(hdma2d->XferErrorCallback != NULL)\r\n      {\r\n        /* Transfer error Callback */\r\n        hdma2d->XferErrorCallback(hdma2d);\r\n      }\r\n    }\r\n  }  \r\n  /* Transfer watermark Interrupt management **********************************/\r\n  if ((isrflags & DMA2D_FLAG_TW) != RESET)\r\n  {\r\n    if ((crflags & DMA2D_IT_TW) != RESET)    \r\n    {    \r\n      /* Disable the transfer watermark interrupt */\r\n      __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);\r\n  \r\n      /* Clear the transfer watermark flag */  \r\n      __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);\r\n\r\n      /* Transfer watermark Callback */\r\n      HAL_DMA2D_LineEventCallback(hdma2d);\r\n    }\r\n  }  \r\n  /* Transfer Complete Interrupt management ************************************/\r\n  if ((isrflags & DMA2D_FLAG_TC) != RESET)\r\n  {\r\n    if ((crflags & DMA2D_IT_TC) != RESET)    \r\n    {   \r\n      /* Disable the transfer complete interrupt */\r\n      __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);\r\n  \r\n      /* Clear the transfer complete flag */  \r\n      __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);\r\n\r\n      /* Update error code */\r\n      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;    \r\n    \r\n      /* Change DMA2D state */\r\n      hdma2d->State = HAL_DMA2D_STATE_READY;\r\n    \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hdma2d);       \r\n      \r\n      if(hdma2d->XferCpltCallback != NULL)\r\n      {\r\n        /* Transfer complete Callback */\r\n        hdma2d->XferCpltCallback(hdma2d);\r\n      }         \r\n    }\r\n  }\r\n  /* CLUT Transfer Complete Interrupt management ******************************/\r\n  if ((isrflags & DMA2D_FLAG_CTC) != RESET)\r\n  {\r\n    if ((crflags & DMA2D_IT_CTC) != RESET)    \r\n    {    \r\n      /* Disable the CLUT transfer complete interrupt */\r\n      __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);\r\n  \r\n      /* Clear the CLUT transfer complete flag */  \r\n      __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);\r\n\r\n      /* Update error code */\r\n      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;    \r\n    \r\n      /* Change DMA2D state */\r\n      hdma2d->State = HAL_DMA2D_STATE_READY;\r\n    \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hdma2d);       \r\n      \r\n      /* CLUT Transfer complete Callback */\r\n      HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);         \r\n    }\r\n  }  \r\n  \r\n}\r\n\r\n/**\r\n  * @brief  Transfer watermark callback.\r\n  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                 the configuration information for the DMA2D.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdma2d);\r\n  \r\n  /* NOTE : This function should not be modified; when the callback is needed,\r\n            the HAL_DMA2D_LineEventCallback can be implemented in the user file.\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  CLUT Transfer Complete callback.\r\n  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                 the configuration information for the DMA2D.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdma2d);\r\n  \r\n  /* NOTE : This function should not be modified; when the callback is needed,\r\n            the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.\r\n   */\r\n} \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions\r\n *  @brief    Peripheral Control functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                    ##### Peripheral Control functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Configure the DMA2D foreground or background layer parameters.\r\n      (+) Configure the DMA2D CLUT transfer.\r\n      (+) Configure the line watermark\r\n      (+) Configure the dead time value.\r\n      (+) Enable or disable the dead time value functionality.      \r\n          \r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Configure the DMA2D Layer according to the specified\r\n  *         parameters in the DMA2D_InitTypeDef and create the associated handle.\r\n  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                 the configuration information for the DMA2D.\r\n  * @param  LayerIdx: DMA2D Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0(background) / 1(foreground)\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)\r\n{ \r\n  DMA2D_LayerCfgTypeDef *pLayerCfg = &hdma2d->LayerCfg[LayerIdx];\r\n  \r\n  uint32_t regMask = 0, regValue = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_DMA2D_LAYER(LayerIdx));  \r\n  assert_param(IS_DMA2D_OFFSET(pLayerCfg->InputOffset));  \r\n  if(hdma2d->Init.Mode != DMA2D_R2M)\r\n  {  \r\n    assert_param(IS_DMA2D_INPUT_COLOR_MODE(pLayerCfg->InputColorMode));\r\n    if(hdma2d->Init.Mode != DMA2D_M2M)\r\n    {\r\n      assert_param(IS_DMA2D_ALPHA_MODE(pLayerCfg->AlphaMode));\r\n    }\r\n  }\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hdma2d);\r\n  \r\n  /* Change DMA2D peripheral state */\r\n  hdma2d->State = HAL_DMA2D_STATE_BUSY;  \r\n\r\n  /* DMA2D BGPFCR register configuration -----------------------------------*/\r\n  /* Prepare the value to be written to the BGPFCCR register */\r\n  \r\n  regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM);\r\n  regMask  = DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA;\r\n  \r\n#if defined (DMA2D_FGPFCCR_AI) && defined (DMA2D_BGPFCCR_AI)\r\n  regValue |= (pLayerCfg->AlphaInverted << DMA2D_POSITION_BGPFCCR_AI);\r\n  regMask  |= DMA2D_BGPFCCR_AI;  \r\n#endif /* (DMA2D_FGPFCCR_AI) && (DMA2D_BGPFCCR_AI)  */ \r\n  \r\n#if defined (DMA2D_FGPFCCR_RBS) && defined (DMA2D_BGPFCCR_RBS)\r\n  regValue |= (pLayerCfg->RedBlueSwap << DMA2D_POSITION_BGPFCCR_RBS);\r\n  regMask  |= DMA2D_BGPFCCR_RBS;  \r\n#endif  \r\n  \r\n  if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))\r\n  {\r\n    regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);\r\n  }\r\n  else\r\n  {\r\n    regValue |=  (pLayerCfg->InputAlpha << DMA2D_POSITION_BGPFCCR_ALPHA);\r\n  }\r\n  \r\n  /* Configure the background DMA2D layer */\r\n  if(LayerIdx == 0)\r\n  {\r\n    /* Write DMA2D BGPFCCR register */\r\n    MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);\r\n              \r\n    /* DMA2D BGOR register configuration -------------------------------------*/  \r\n    WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);\r\n    \r\n    /* DMA2D BGCOLR register configuration -------------------------------------*/ \r\n    if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))\r\n    {    \r\n      WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED));\r\n    }    \r\n  }\r\n  /* Configure the foreground DMA2D layer */\r\n  else\r\n  {\r\n     /* Write DMA2D FGPFCCR register */\r\n    MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);\r\n    \r\n    /* DMA2D FGOR register configuration -------------------------------------*/\r\n    WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);      \r\n   \r\n    /* DMA2D FGCOLR register configuration -------------------------------------*/   \r\n    if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))\r\n    {\r\n      WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED));      \r\n    }   \r\n  }   \r\n  /* Initialize the DMA2D state*/\r\n  hdma2d->State = HAL_DMA2D_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdma2d);  \r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Configure the DMA2D CLUT Transfer.\r\n  * @param  hdma2d:   Pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                   the configuration information for the DMA2D.\r\n  * @param  CLUTCfg:  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains\r\n  *                   the configuration information for the color look up table.\r\n  * @param  LayerIdx: DMA2D Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0(background) / 1(foreground)\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_DMA2D_LAYER(LayerIdx));   \r\n  assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));\r\n  assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hdma2d);\r\n  \r\n  /* Change DMA2D peripheral state */\r\n  hdma2d->State = HAL_DMA2D_STATE_BUSY;     \r\n  \r\n  /* Configure the CLUT of the background DMA2D layer */\r\n  if(LayerIdx == 0)\r\n  {\r\n    /* Write background CLUT memory address */\r\n    WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);\r\n     \r\n    /* Write background CLUT size and CLUT color mode */\r\n    MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), \r\n            ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));       \r\n }\r\n /* Configure the CLUT of the foreground DMA2D layer */\r\n else\r\n {\r\n   /* Write foreground CLUT memory address */\r\n    WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);\r\n     \r\n    /* Write foreground CLUT size and CLUT color mode */\r\n    MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), \r\n            ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));       \r\n  }\r\n  \r\n  /* Set the DMA2D state to Ready*/\r\n  hdma2d->State = HAL_DMA2D_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdma2d); \r\n    \r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Configure the line watermark.\r\n  * @param  hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                 the configuration information for the DMA2D.\r\n  * @param  Line:   Line Watermark configuration (maximum 16-bit long value expected).\r\n  * @note   HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt.\r\n  * @note   The transfer watermark interrupt is disabled once it has occurred.\r\n  * @retval HAL status\r\n  */\r\n\r\nHAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_DMA2D_LINEWATERMARK(Line));\r\n  \r\n  if (Line > DMA2D_LWR_LW)\r\n  {\r\n    return HAL_ERROR;  \r\n  }\r\n  else\r\n  {      \r\n    /* Process locked */\r\n    __HAL_LOCK(hdma2d);\r\n    \r\n    /* Change DMA2D peripheral state */\r\n    hdma2d->State = HAL_DMA2D_STATE_BUSY;\r\n  \r\n    /* Sets the Line watermark configuration */\r\n    WRITE_REG(hdma2d->Instance->LWR, Line);\r\n    \r\n    /* Enable the Line interrupt */\r\n    __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW);\r\n        \r\n    /* Initialize the DMA2D state*/\r\n    hdma2d->State = HAL_DMA2D_STATE_READY;\r\n    \r\n    /* Process unlocked */\r\n    __HAL_UNLOCK(hdma2d);  \r\n    \r\n    return HAL_OK;\r\n  }  \r\n}\r\n\r\n/**\r\n  * @brief Enable DMA2D dead time feature.\r\n  * @param hdma2d: DMA2D handle.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hdma2d);\r\n\r\n  hdma2d->State = HAL_DMA2D_STATE_BUSY;\r\n\r\n  /* Set DMA2D_AMTCR EN bit */\r\n  SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);\r\n\r\n  hdma2d->State = HAL_DMA2D_STATE_READY;\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hdma2d);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Disable DMA2D dead time feature.\r\n  * @param hdma2d: DMA2D handle.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hdma2d);\r\n\r\n  hdma2d->State = HAL_DMA2D_STATE_BUSY;\r\n\r\n  /* Clear DMA2D_AMTCR EN bit */\r\n  CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);\r\n\r\n  hdma2d->State = HAL_DMA2D_STATE_READY;\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hdma2d);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Configure dead time.\r\n  * @note The dead time value represents the guaranteed minimum number of cycles between \r\n  *       two consecutive transactions on the AHB bus.\r\n  * @param hdma2d: DMA2D handle.\r\n  * @param DeadTime: dead time value.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hdma2d);  \r\n  \r\n  hdma2d->State = HAL_DMA2D_STATE_BUSY;\r\n\r\n  /* Set DMA2D_AMTCR DT field */\r\n  MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_POSITION_AMTCR_DT));\r\n\r\n  hdma2d->State = HAL_DMA2D_STATE_READY;\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hdma2d);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n\r\n/** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions\r\n *  @brief    Peripheral State functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                  ##### Peripheral State and Errors functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides functions allowing to :\r\n      (+) Get the DMA2D state\r\n      (+) Get the DMA2D error code  \r\n\r\n@endverbatim\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @brief  Return the DMA2D state\r\n  * @param  hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                 the configuration information for the DMA2D.  \r\n  * @retval HAL state\r\n  */\r\nHAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)\r\n{  \r\n  return hdma2d->State;\r\n}\r\n\r\n/**\r\n  * @brief  Return the DMA2D error code\r\n  * @param  hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *               the configuration information for DMA2D.\r\n  * @retval DMA2D Error Code\r\n  */\r\nuint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)\r\n{\r\n  return hdma2d->ErrorCode;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */  \r\n\r\n\r\n/** @defgroup DMA2D_Private_Functions DMA2D Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Set the DMA2D transfer parameters.\r\n  * @param  hdma2d:     Pointer to a DMA2D_HandleTypeDef structure that contains\r\n  *                     the configuration information for the specified DMA2D.  \r\n  * @param  pdata:      The source memory Buffer address\r\n  * @param  DstAddress: The destination memory Buffer address\r\n  * @param  Width:      The width of data to be transferred from source to destination.\r\n  * @param  Height:     The height of data to be transferred from source to destination.\r\n  * @retval HAL status\r\n  */\r\nstatic void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)\r\n{  \r\n  uint32_t tmp = 0;\r\n  uint32_t tmp1 = 0;\r\n  uint32_t tmp2 = 0;\r\n  uint32_t tmp3 = 0;\r\n  uint32_t tmp4 = 0;\r\n    \r\n  /* Configure DMA2D data size */\r\n  MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_POSITION_NLR_PL))); \r\n  \r\n  /* Configure DMA2D destination address */\r\n  WRITE_REG(hdma2d->Instance->OMAR, DstAddress);\r\n \r\n  /* Register to memory DMA2D mode selected */\r\n  if (hdma2d->Init.Mode == DMA2D_R2M)\r\n  {    \r\n    tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;\r\n    tmp2 = pdata & DMA2D_OCOLR_RED_1;\r\n    tmp3 = pdata & DMA2D_OCOLR_GREEN_1;\r\n    tmp4 = pdata & DMA2D_OCOLR_BLUE_1;\r\n    \r\n    /* Prepare the value to be written to the OCOLR register according to the color mode */\r\n    if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)\r\n    {\r\n      tmp = (tmp3 | tmp2 | tmp1| tmp4);\r\n    }\r\n    else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)\r\n    {\r\n      tmp = (tmp3 | tmp2 | tmp4);  \r\n    }\r\n    else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)\r\n    {\r\n      tmp2 = (tmp2 >> 19);\r\n      tmp3 = (tmp3 >> 10);\r\n      tmp4 = (tmp4 >> 3 );\r\n      tmp  = ((tmp3 << 5) | (tmp2 << 11) | tmp4); \r\n    }\r\n    else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)\r\n    { \r\n      tmp1 = (tmp1 >> 31);\r\n      tmp2 = (tmp2 >> 19);\r\n      tmp3 = (tmp3 >> 11);\r\n      tmp4 = (tmp4 >> 3 );      \r\n      tmp  = ((tmp3 << 5) | (tmp2 << 10) | (tmp1 << 15) | tmp4);    \r\n    } \r\n    else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */\r\n    {\r\n      tmp1 = (tmp1 >> 28);\r\n      tmp2 = (tmp2 >> 20);\r\n      tmp3 = (tmp3 >> 12);\r\n      tmp4 = (tmp4 >> 4 );\r\n      tmp  = ((tmp3 << 4) | (tmp2 << 8) | (tmp1 << 12) | tmp4);\r\n    }    \r\n    /* Write to DMA2D OCOLR register */\r\n    WRITE_REG(hdma2d->Instance->OCOLR, tmp);    \r\n  } \r\n  else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */\r\n  {\r\n    /* Configure DMA2D source address */\r\n    WRITE_REG(hdma2d->Instance->FGMAR, pdata);\r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n#endif /* HAL_DMA2D_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_dma_ex.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   DMA Extension HAL module driver\r\n  *         This file provides firmware functions to manage the following \r\n  *         functionalities of the DMA Extension peripheral:\r\n  *           + Extended features functions\r\n  *\r\n  @verbatim\r\n  ==============================================================================\r\n                        ##### How to use this driver #####\r\n  ==============================================================================\r\n  [..]\r\n  The DMA Extension HAL driver can be used as follows:\r\n   (+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function\r\n       for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.\r\n\r\n     -@-  In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.\r\n     -@-  When Multi (Double) Buffer mode is enabled, the transfer is circular by default.\r\n     -@-  In Multi (Double) buffer mode, it is possible to update the base address for \r\n          the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.\r\n  \r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup DMAEx DMAEx\r\n  * @brief DMA Extended HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_DMA_MODULE_ENABLED\r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private Constants ---------------------------------------------------------*/\r\n/* Private macros ------------------------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @addtogroup DMAEx_Private_Functions\r\n  * @{\r\n  */\r\n\r\nstatic void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions ---------------------------------------------------------*/\r\n\r\n/** @addtogroup DMAEx_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n\r\n/** @addtogroup DMAEx_Exported_Functions_Group1\r\n  *\r\n@verbatim\r\n ===============================================================================\r\n                #####  Extended features functions  #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Configure the source, destination address and data length and \r\n          Start MultiBuffer DMA transfer\r\n      (+) Configure the source, destination address and data length and \r\n          Start MultiBuffer DMA transfer with interrupt\r\n      (+) Change on the fly the memory0 or memory1 address.\r\n      \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n\r\n/**\r\n  * @brief  Starts the multi_buffer DMA Transfer.\r\n  * @param  hdma      : pointer to a DMA_HandleTypeDef structure that contains\r\n  *                     the configuration information for the specified DMA Stream.  \r\n  * @param  SrcAddress: The source memory Buffer address\r\n  * @param  DstAddress: The destination memory Buffer address\r\n  * @param  SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer  \r\n  * @param  DataLength: The length of data to be transferred from source to destination\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_DMA_BUFFER_SIZE(DataLength));\r\n  \r\n  /* Memory-to-memory transfer not supported in double buffering mode */\r\n  if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)\r\n  {\r\n    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;\r\n    status = HAL_ERROR;\r\n  }\r\n  else\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hdma);\r\n    \r\n    if(HAL_DMA_STATE_READY == hdma->State)\r\n    {\r\n      /* Change DMA peripheral state */\r\n      hdma->State = HAL_DMA_STATE_BUSY; \r\n      \r\n      /* Enable the double buffer mode */\r\n      hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;\r\n      \r\n      /* Configure DMA Stream destination address */\r\n      hdma->Instance->M1AR = SecondMemAddress;\r\n      \r\n      /* Configure the source, destination address and the data length */\r\n      DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);\r\n      \r\n      /* Enable the peripheral */\r\n      __HAL_DMA_ENABLE(hdma);\r\n    }\r\n    else\r\n    {\r\n      /* Return error status */\r\n      status = HAL_BUSY;\r\n    }\r\n  }\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the multi_buffer DMA Transfer with interrupt enabled.\r\n  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains\r\n  *                     the configuration information for the specified DMA Stream.  \r\n  * @param  SrcAddress: The source memory Buffer address\r\n  * @param  DstAddress: The destination memory Buffer address\r\n  * @param  SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer  \r\n  * @param  DataLength: The length of data to be transferred from source to destination\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_DMA_BUFFER_SIZE(DataLength));\r\n  \r\n  /* Memory-to-memory transfer not supported in double buffering mode */\r\n  if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)\r\n  {\r\n    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hdma);\r\n  \r\n  if(HAL_DMA_STATE_READY == hdma->State)\r\n  {\r\n    /* Change DMA peripheral state */\r\n    hdma->State = HAL_DMA_STATE_BUSY;\r\n    \r\n    /* Initialize the error code */\r\n    hdma->ErrorCode = HAL_DMA_ERROR_NONE;\r\n    \r\n    /* Enable the Double buffer mode */\r\n    hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;\r\n    \r\n    /* Configure DMA Stream destination address */\r\n    hdma->Instance->M1AR = SecondMemAddress;\r\n    \r\n    /* Configure the source, destination address and the data length */\r\n    DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); \r\n    \r\n    /* Clear all flags */\r\n    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));\r\n    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));\r\n    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));\r\n    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));\r\n    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));\r\n    \r\n    /* Enable Common interrupts*/\r\n    hdma->Instance->CR  |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;\r\n    hdma->Instance->FCR |= DMA_IT_FE;\r\n    \r\n    if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))\r\n    {\r\n      hdma->Instance->CR  |= DMA_IT_HT;\r\n    }\r\n    \r\n    /* Enable the peripheral */\r\n    __HAL_DMA_ENABLE(hdma); \r\n  }\r\n  else\r\n  {     \r\n    /* Process unlocked */\r\n    __HAL_UNLOCK(hdma);\t  \r\n    \r\n    /* Return error status */\r\n    status = HAL_BUSY;\r\n  }  \r\n  return status; \r\n}\r\n\r\n/**\r\n  * @brief  Change the memory0 or memory1 address on the fly.\r\n  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains\r\n  *                     the configuration information for the specified DMA Stream.  \r\n  * @param  Address:    The new address\r\n  * @param  memory:     the memory to be changed, This parameter can be one of \r\n  *                     the following values:\r\n  *                      MEMORY0 /\r\n  *                      MEMORY1\r\n  * @note   The MEMORY0 address can be changed only when the current transfer use\r\n  *         MEMORY1 and the MEMORY1 address can be changed only when the current \r\n  *         transfer use MEMORY0.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)\r\n{\r\n  if(memory == MEMORY0)\r\n  {\r\n    /* change the memory0 address */\r\n    hdma->Instance->M0AR = Address;\r\n  }\r\n  else\r\n  {\r\n    /* change the memory1 address */\r\n    hdma->Instance->M1AR = Address;\r\n  }\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup DMAEx_Private_Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Set the DMA Transfer parameter.\r\n  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains\r\n  *                     the configuration information for the specified DMA Stream.  \r\n  * @param  SrcAddress: The source memory Buffer address\r\n  * @param  DstAddress: The destination memory Buffer address\r\n  * @param  DataLength: The length of data to be transferred from source to destination\r\n  * @retval HAL status\r\n  */\r\nstatic void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\r\n{\r\n  /* Configure DMA Stream data length */\r\n  hdma->Instance->NDTR = DataLength;\r\n  \r\n  /* Peripheral to Memory */\r\n  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)\r\n  {\r\n    /* Configure DMA Stream destination address */\r\n    hdma->Instance->PAR = DstAddress;\r\n    \r\n    /* Configure DMA Stream source address */\r\n    hdma->Instance->M0AR = SrcAddress;\r\n  }\r\n  /* Memory to Peripheral */\r\n  else\r\n  {\r\n    /* Configure DMA Stream source address */\r\n    hdma->Instance->PAR = SrcAddress;\r\n    \r\n    /* Configure DMA Stream destination address */\r\n    hdma->Instance->M0AR = DstAddress;\r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_DMA_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_dsi.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   DSI HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the DSI peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + IO operation functions\r\n  *           + Peripheral Control functions  \r\n  *           + Peripheral State and Errors functions\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n/** @addtogroup DSI\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_DSI_MODULE_ENABLED\r\n\r\n#if defined (STM32F769xx) || defined (STM32F779xx)\r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private defines -----------------------------------------------------------*/\r\n/** @addtogroup DSI_Private_Constants\r\n  * @{\r\n  */\r\n#define DSI_TIMEOUT_VALUE ((uint32_t)1000)  /* 1s */\r\n\r\n#define DSI_ERROR_ACK_MASK (DSI_ISR0_AE0 | DSI_ISR0_AE1 | DSI_ISR0_AE2 | DSI_ISR0_AE3 | \\\r\n                            DSI_ISR0_AE4 | DSI_ISR0_AE5 | DSI_ISR0_AE6 | DSI_ISR0_AE7 | \\\r\n                            DSI_ISR0_AE8 | DSI_ISR0_AE9 | DSI_ISR0_AE10 | DSI_ISR0_AE11 | \\\r\n                            DSI_ISR0_AE12 | DSI_ISR0_AE13 | DSI_ISR0_AE14 | DSI_ISR0_AE15)\r\n#define DSI_ERROR_PHY_MASK (DSI_ISR0_PE0 | DSI_ISR0_PE1 | DSI_ISR0_PE2 | DSI_ISR0_PE3 | DSI_ISR0_PE4)\r\n#define DSI_ERROR_TX_MASK  DSI_ISR1_TOHSTX\r\n#define DSI_ERROR_RX_MASK  DSI_ISR1_TOLPRX\r\n#define DSI_ERROR_ECC_MASK (DSI_ISR1_ECCSE | DSI_ISR1_ECCME)\r\n#define DSI_ERROR_CRC_MASK DSI_ISR1_CRCE\r\n#define DSI_ERROR_PSE_MASK DSI_ISR1_PSE\r\n#define DSI_ERROR_EOT_MASK DSI_ISR1_EOTPE\r\n#define DSI_ERROR_OVF_MASK DSI_ISR1_LPWRE\r\n#define DSI_ERROR_GEN_MASK (DSI_ISR1_GCWRE | DSI_ISR1_GPWRE | DSI_ISR1_GPTXE | DSI_ISR1_GPRDE | DSI_ISR1_GPRXE)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/* Private macros ------------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\nstatic void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0, uint32_t Data1);\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/**\r\n  * @brief  Generic DSI packet header configuration\r\n  * @param  DSIx: Pointer to DSI register base\r\n  * @param  ChannelID: Virtual channel ID of the header packet\r\n  * @param  DataType: Packet data type of the header packet\r\n  *                   This parameter can be any value of :\r\n  *                      @ref DSI_SHORT_WRITE_PKT_Data_Type\r\n  *                   or @ref DSI_LONG_WRITE_PKT_Data_Type\r\n  *                   or @ref DSI_SHORT_READ_PKT_Data_Type\r\n  *                   or DSI_MAX_RETURN_PKT_SIZE\r\n  * @param  Data0: Word count LSB\r\n  * @param  Data1: Word count MSB\r\n  * @retval None\r\n  */\r\nstatic void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx,\r\n                                   uint32_t ChannelID,\r\n                                   uint32_t DataType,\r\n                                   uint32_t Data0,\r\n                                   uint32_t Data1)\r\n{\r\n  /* Update the DSI packet header with new information */\r\n  DSIx->GHCR = (DataType | (ChannelID<<6) | (Data0<<8) | (Data1<<16));\r\n}\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup DSI_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup DSI_Group1 Initialization and Configuration functions\r\n *  @brief   Initialization and Configuration functions\r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                ##### Initialization and Configuration functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Initialize and configure the DSI\r\n      (+) De-initialize the DSI \r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @brief  Initializes the DSI according to the specified\r\n  *         parameters in the DSI_InitTypeDef and create the associated handle.\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @param  PLLInit: pointer to a DSI_PLLInitTypeDef structure that contains\r\n  *               the PLL Clock structure definition for the DSI.  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit)\r\n{\r\n  uint32_t tickstart = 0;\r\n  uint32_t unitIntervalx4 = 0;\r\n  uint32_t tempIDF = 0;\r\n  \r\n  /* Check the DSI handle allocation */\r\n  if(hdsi == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Check function parameters */\r\n  assert_param(IS_DSI_PLL_NDIV(PLLInit->PLLNDIV));\r\n  assert_param(IS_DSI_PLL_IDF(PLLInit->PLLIDF));\r\n  assert_param(IS_DSI_PLL_ODF(PLLInit->PLLODF));\r\n  assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl));\r\n  assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes));\r\n  \r\n  if(hdsi->State == HAL_DSI_STATE_RESET)\r\n  {\r\n    /* Initialize the low level hardware */\r\n    HAL_DSI_MspInit(hdsi);\r\n  }\r\n  \r\n  /* Change DSI peripheral state */\r\n  hdsi->State = HAL_DSI_STATE_BUSY;\r\n  \r\n  /**************** Turn on the regulator and enable the DSI PLL ****************/\r\n  \r\n    /* Enable the regulator */\r\n    __HAL_DSI_REG_ENABLE(hdsi);\r\n    \r\n\t/* Get tick */ \r\n    tickstart = HAL_GetTick();\r\n\t\r\n    /* Wait until the regulator is ready */\r\n\twhile(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == RESET)\r\n    {\r\n      /* Check for the Timeout */\r\n      if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n    \r\n    /* Set the PLL division factors */\r\n    hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF);\r\n    hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV)<<2) | ((PLLInit->PLLIDF)<<11) | ((PLLInit->PLLODF)<<16));\r\n    \r\n    /* Enable the DSI PLL */\r\n    __HAL_DSI_PLL_ENABLE(hdsi);\r\n    \r\n\t/* Get tick */ \r\n    tickstart = HAL_GetTick();\r\n\t\r\n    /* Wait for the lock of the PLL */\r\n    while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET)\r\n    {\r\n      /* Check for the Timeout */\r\n      if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  \r\n  /*************************** Set the PHY parameters ***************************/\r\n  \r\n    /* D-PHY clock and digital enable*/\r\n    hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN);\r\n    \r\n    /* Clock lane configuration */\r\n    hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR);\r\n    hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl);\r\n    \r\n    /* Configure the number of active data lanes */\r\n    hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL;\r\n    hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes;\r\n  \r\n  /************************ Set the DSI clock parameters ************************/\r\n  \r\n    /* Set the TX escape clock division factor */\r\n    hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;\r\n    hdsi->Instance->CCR = hdsi->Init.TXEscapeCkdiv;\r\n    \r\n    /* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */\r\n    /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 )          */\r\n    /* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF)                    */\r\n    tempIDF = (PLLInit->PLLIDF > 0) ? PLLInit->PLLIDF : 1;\r\n    unitIntervalx4 = (4000000 * tempIDF * (1 << PLLInit->PLLODF)) / ((HSE_VALUE/1000) * PLLInit->PLLNDIV);\r\n\t\r\n    /* Set the bit period in high-speed mode */\r\n    hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_UIX4;\r\n    hdsi->Instance->WPCR[0] |= unitIntervalx4;\r\n  \r\n  /****************************** Error management *****************************/\r\n  \r\n    /* Disable all error interrupts and reset the Error Mask */\r\n    hdsi->Instance->IER[0] = 0;\r\n    hdsi->Instance->IER[1] = 0;\r\n    hdsi->ErrorMsk = 0;\r\n    \r\n    /* Initialise the error code */\r\n    hdsi->ErrorCode = HAL_DSI_ERROR_NONE;\r\n  \r\n  /* Initialize the DSI state*/\r\n  hdsi->State = HAL_DSI_STATE_READY;\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  De-initializes the DSI peripheral registers to their default reset\r\n  *         values.\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi)\r\n{\r\n  /* Check the DSI handle allocation */\r\n  if(hdsi == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Change DSI peripheral state */\r\n  hdsi->State = HAL_DSI_STATE_BUSY;\r\n  \r\n  /* Disable the DSI wrapper */\r\n  __HAL_DSI_WRAPPER_DISABLE(hdsi);\r\n  \r\n  /* Disable the DSI host */\r\n  __HAL_DSI_DISABLE(hdsi);\r\n  \r\n  /* D-PHY clock and digital disable */\r\n  hdsi->Instance->PCTLR &= ~(DSI_PCTLR_CKE | DSI_PCTLR_DEN);\r\n  \r\n  /* Turn off the DSI PLL */\r\n  __HAL_DSI_PLL_DISABLE(hdsi);\r\n  \r\n  /* Disable the regulator */\r\n  __HAL_DSI_REG_DISABLE(hdsi);\r\n  \r\n  /* DeInit the low level hardware */\r\n  HAL_DSI_MspDeInit(hdsi); \r\n  \r\n  /* Initialise the error code */\r\n  hdsi->ErrorCode = HAL_DSI_ERROR_NONE;\r\n  \r\n  /* Initialize the DSI state*/\r\n  hdsi->State = HAL_DSI_STATE_RESET;\r\n  \r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hdsi);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Return the DSI error code\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @retval DSI Error Code\r\n  */\r\nuint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi)\r\n{\r\n  /* Get the error code */\r\n  return hdsi->ErrorCode;\r\n}\r\n\r\n/**\r\n  * @brief  Enable the error monitor flags \r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @param  ActiveErrors: indicates which error interrupts will be enabled.\r\n  *                      This parameter can be any combination of @ref DSI_Error_Data_Type.\r\n  * @retval HAL status \r\n  */\r\nHAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hdsi);\r\n  \r\n  hdsi->Instance->IER[0] = 0;\r\n  hdsi->Instance->IER[1] = 0;\r\n  \r\n  /* Store active errors to the handle */\r\n  hdsi->ErrorMsk = ActiveErrors;\r\n  \r\n  if((ActiveErrors & HAL_DSI_ERROR_ACK) != RESET)\r\n  {\r\n    /* Enable the interrupt generation on selected errors */\r\n    hdsi->Instance->IER[0] |= DSI_ERROR_ACK_MASK;\r\n  }\r\n  \r\n  if((ActiveErrors & HAL_DSI_ERROR_PHY ) != RESET)\r\n  {\r\n    /* Enable the interrupt generation on selected errors */\r\n    hdsi->Instance->IER[0] |= DSI_ERROR_PHY_MASK;\r\n  }\r\n  \r\n  if((ActiveErrors & HAL_DSI_ERROR_TX) != RESET)\r\n  {\r\n    /* Enable the interrupt generation on selected errors */\r\n    hdsi->Instance->IER[1] |= DSI_ERROR_TX_MASK;\r\n  }\r\n  \r\n  if((ActiveErrors & HAL_DSI_ERROR_RX) != RESET)\r\n  {\r\n    /* Enable the interrupt generation on selected errors */\r\n    hdsi->Instance->IER[1] |= DSI_ERROR_RX_MASK;\r\n  }\r\n  \r\n  if((ActiveErrors & HAL_DSI_ERROR_ECC) != RESET)\r\n  {\r\n    /* Enable the interrupt generation on selected errors */\r\n    hdsi->Instance->IER[1] |= DSI_ERROR_ECC_MASK;\r\n  }\r\n  \r\n  if((ActiveErrors & HAL_DSI_ERROR_CRC) != RESET)\r\n  {\r\n    /* Enable the interrupt generation on selected errors */\r\n    hdsi->Instance->IER[1] |= DSI_ERROR_CRC_MASK;\r\n  }\r\n  \r\n  if((ActiveErrors & HAL_DSI_ERROR_PSE) != RESET)\r\n  {\r\n    /* Enable the interrupt generation on selected errors */\r\n    hdsi->Instance->IER[1] |= DSI_ERROR_PSE_MASK;\r\n  }\r\n  \r\n  if((ActiveErrors & HAL_DSI_ERROR_EOT) != RESET)\r\n  {\r\n    /* Enable the interrupt generation on selected errors */\r\n    hdsi->Instance->IER[1] |= DSI_ERROR_EOT_MASK;\r\n  }\r\n  \r\n  if((ActiveErrors & HAL_DSI_ERROR_OVF) != RESET)\r\n  {\r\n    /* Enable the interrupt generation on selected errors */\r\n    hdsi->Instance->IER[1] |= DSI_ERROR_OVF_MASK;\r\n  }\r\n  \r\n  if((ActiveErrors & HAL_DSI_ERROR_GEN) != RESET)\r\n  {\r\n    /* Enable the interrupt generation on selected errors */\r\n    hdsi->Instance->IER[1] |= DSI_ERROR_GEN_MASK;\r\n  }\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hdsi);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the DSI MSP.\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdsi);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_DSI_MspInit could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  De-initializes the DSI MSP.\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdsi);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_DSI_MspDeInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup DSI_Group2 IO operation functions \r\n *  @brief    IO operation functions  \r\n *\r\n@verbatim\r\n ===============================================================================\r\n                      #####  IO operation functions  #####\r\n ===============================================================================  \r\n    [..]  This section provides function allowing to:\r\n      (+) Handle DSI interrupt request\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n/**\r\n  * @brief  Handles DSI interrupt request.\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.  \r\n  * @retval HAL status\r\n  */\r\nvoid HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi)\r\n{\r\n  uint32_t ErrorStatus0, ErrorStatus1;\r\n  \r\n  /* Tearing Effect Interrupt management ***************************************/\r\n  if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != RESET)\r\n  {\r\n    if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != RESET)\r\n    {\r\n      /* Clear the Tearing Effect Interrupt Flag */\r\n      __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE);\r\n      \r\n      /* Tearing Effect Callback */\r\n      HAL_DSI_TearingEffectCallback(hdsi);\r\n    }\r\n  }\r\n  \r\n  /* End of Refresh Interrupt management ***************************************/\r\n  if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != RESET)\r\n  {\r\n    if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != RESET)\r\n    {\r\n      /* Clear the End of Refresh Interrupt Flag */\r\n      __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER);\r\n      \r\n      /* End of Refresh Callback */\r\n      HAL_DSI_EndOfRefreshCallback(hdsi);\r\n    }\r\n  }\r\n  \r\n  /* Error Interrupts management ***********************************************/\r\n  if(hdsi->ErrorMsk != 0)\r\n  {\r\n    ErrorStatus0 = hdsi->Instance->ISR[0];\r\n    ErrorStatus0 &= hdsi->Instance->IER[0];\r\n    ErrorStatus1 = hdsi->Instance->ISR[1];\r\n    ErrorStatus1 &= hdsi->Instance->IER[1];\r\n    \r\n    if((ErrorStatus0 & DSI_ERROR_ACK_MASK) != RESET)\r\n    {\r\n      hdsi->ErrorCode |= HAL_DSI_ERROR_ACK;\r\n    }\r\n    \r\n    if((ErrorStatus0 & DSI_ERROR_PHY_MASK) != RESET)\r\n    {\r\n      hdsi->ErrorCode |= HAL_DSI_ERROR_PHY;\r\n    }\r\n    \r\n    if((ErrorStatus1 & DSI_ERROR_TX_MASK) != RESET)\r\n    {\r\n      hdsi->ErrorCode |= HAL_DSI_ERROR_TX;\r\n    }\r\n    \r\n    if((ErrorStatus1 & DSI_ERROR_RX_MASK) != RESET)\r\n    {\r\n      hdsi->ErrorCode |= HAL_DSI_ERROR_RX;\r\n    }\r\n    \r\n    if((ErrorStatus1 & DSI_ERROR_ECC_MASK) != RESET)\r\n    {\r\n      hdsi->ErrorCode |= HAL_DSI_ERROR_ECC;\r\n    }\r\n    \r\n    if((ErrorStatus1 & DSI_ERROR_CRC_MASK) != RESET)\r\n    {\r\n      hdsi->ErrorCode |= HAL_DSI_ERROR_CRC;\r\n    }\r\n    \r\n    if((ErrorStatus1 & DSI_ERROR_PSE_MASK) != RESET)\r\n    {\r\n      hdsi->ErrorCode |= HAL_DSI_ERROR_PSE;\r\n    }\r\n    \r\n    if((ErrorStatus1 & DSI_ERROR_EOT_MASK) != RESET)\r\n    {\r\n      hdsi->ErrorCode |= HAL_DSI_ERROR_EOT;\r\n    }\r\n    \r\n    if((ErrorStatus1 & DSI_ERROR_OVF_MASK) != RESET)\r\n    {\r\n      hdsi->ErrorCode |= HAL_DSI_ERROR_OVF;\r\n    }\r\n    \r\n    if((ErrorStatus1 & DSI_ERROR_GEN_MASK) != RESET)\r\n    {\r\n      hdsi->ErrorCode |= HAL_DSI_ERROR_GEN;\r\n    }\r\n    \r\n    /* Check only selected errors */\r\n    if(hdsi->ErrorCode != HAL_DSI_ERROR_NONE)\r\n    {\r\n      /* DSI error interrupt user callback */\r\n      HAL_DSI_ErrorCallback(hdsi);\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Tearing Effect DSI callback.\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdsi);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_DSI_TearingEffectCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  End of Refresh DSI callback.\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdsi);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_DSI_EndOfRefreshCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Operation Error DSI callback.\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @retval None\r\n  */\r\n__weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdsi);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_DSI_ErrorCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_Group3 Peripheral Control functions\r\n *  @brief    Peripheral Control functions \r\n *\r\n@verbatim\r\n ===============================================================================\r\n                    ##### Peripheral Control functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) \r\n      (+) \r\n      (+) \r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Configure the Generic interface read-back Virtual Channel ID.\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @param  VirtualChannelID: Virtual channel ID\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hdsi);\r\n  \r\n  /* Update the GVCID register */\r\n  hdsi->Instance->GVCIDR &= ~DSI_GVCIDR_VCID;\r\n  hdsi->Instance->GVCIDR |= VirtualChannelID;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdsi);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Select video mode and configure the corresponding parameters\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @param  VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains\r\n  *                 the DSI video mode configuration parameters\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hdsi);\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_DSI_COLOR_CODING(VidCfg->ColorCoding));\r\n  assert_param(IS_DSI_VIDEO_MODE_TYPE(VidCfg->Mode));\r\n  assert_param(IS_DSI_LP_COMMAND(VidCfg->LPCommandEnable));\r\n  assert_param(IS_DSI_LP_HFP(VidCfg->LPHorizontalFrontPorchEnable));\r\n  assert_param(IS_DSI_LP_HBP(VidCfg->LPHorizontalBackPorchEnable));\r\n  assert_param(IS_DSI_LP_VACTIVE(VidCfg->LPVerticalActiveEnable));\r\n  assert_param(IS_DSI_LP_VFP(VidCfg->LPVerticalFrontPorchEnable));\r\n  assert_param(IS_DSI_LP_VBP(VidCfg->LPVerticalBackPorchEnable));\r\n  assert_param(IS_DSI_LP_VSYNC(VidCfg->LPVerticalSyncActiveEnable));\r\n  assert_param(IS_DSI_FBTAA(VidCfg->FrameBTAAcknowledgeEnable));\r\n  assert_param(IS_DSI_DE_POLARITY(VidCfg->DEPolarity));\r\n  assert_param(IS_DSI_VSYNC_POLARITY(VidCfg->VSPolarity));\r\n  assert_param(IS_DSI_HSYNC_POLARITY(VidCfg->HSPolarity));\r\n  /* Check the LooselyPacked variant only in 18-bit mode */\r\n  if(VidCfg->ColorCoding == DSI_RGB666)\r\n  {\r\n    assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked));\r\n  }\r\n  \r\n  /* Select video mode by resetting CMDM and DSIM bits */\r\n  hdsi->Instance->MCR &= ~DSI_MCR_CMDM;\r\n  hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;\r\n  \r\n  /* Configure the video mode transmission type */\r\n  hdsi->Instance->VMCR &= ~DSI_VMCR_VMT;\r\n  hdsi->Instance->VMCR |= VidCfg->Mode;\r\n  \r\n  /* Configure the video packet size */\r\n  hdsi->Instance->VPCR &= ~DSI_VPCR_VPSIZE;\r\n  hdsi->Instance->VPCR |= VidCfg->PacketSize;\r\n  \r\n  /* Set the chunks number to be transmitted through the DSI link */\r\n  hdsi->Instance->VCCR &= ~DSI_VCCR_NUMC;\r\n  hdsi->Instance->VCCR |= VidCfg->NumberOfChunks;\r\n  \r\n  /* Set the size of the null packet */\r\n  hdsi->Instance->VNPCR &= ~DSI_VNPCR_NPSIZE;\r\n  hdsi->Instance->VNPCR |= VidCfg->NullPacketSize;\r\n  \r\n  /* Select the virtual channel for the LTDC interface traffic */\r\n  hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;\r\n  hdsi->Instance->LVCIDR |= VidCfg->VirtualChannelID;\r\n  \r\n  /* Configure the polarity of control signals */\r\n  hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);\r\n  hdsi->Instance->LPCR |= (VidCfg->DEPolarity | VidCfg->VSPolarity | VidCfg->HSPolarity);\r\n  \r\n  /* Select the color coding for the host */\r\n  hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;\r\n  hdsi->Instance->LCOLCR |= VidCfg->ColorCoding;\r\n    \r\n  /* Select the color coding for the wrapper */\r\n  hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;\r\n  hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding)<<1);\r\n  \r\n  /* Enable/disable the loosely packed variant to 18-bit configuration */\r\n  if(VidCfg->ColorCoding == DSI_RGB666)\r\n  {\r\n    hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE;\r\n    hdsi->Instance->LCOLCR |= VidCfg->LooselyPacked;\r\n  }\r\n  \r\n  /* Set the Horizontal Synchronization Active (HSA) in lane byte clock cycles */\r\n  hdsi->Instance->VHSACR &= ~DSI_VHSACR_HSA;\r\n  hdsi->Instance->VHSACR |= VidCfg->HorizontalSyncActive;\r\n  \r\n  /* Set the Horizontal Back Porch (HBP) in lane byte clock cycles */\r\n  hdsi->Instance->VHBPCR &= ~DSI_VHBPCR_HBP;\r\n  hdsi->Instance->VHBPCR |= VidCfg->HorizontalBackPorch;\r\n  \r\n  /* Set the total line time (HLINE=HSA+HBP+HACT+HFP) in lane byte clock cycles */\r\n  hdsi->Instance->VLCR &= ~DSI_VLCR_HLINE;\r\n  hdsi->Instance->VLCR |= VidCfg->HorizontalLine;\r\n  \r\n  /* Set the Vertical Synchronization Active (VSA) */\r\n  hdsi->Instance->VVSACR &= ~DSI_VVSACR_VSA;\r\n  hdsi->Instance->VVSACR |= VidCfg->VerticalSyncActive;\r\n  \r\n  /* Set the Vertical Back Porch (VBP)*/\r\n  hdsi->Instance->VVBPCR &= ~DSI_VVBPCR_VBP;\r\n  hdsi->Instance->VVBPCR |= VidCfg->VerticalBackPorch;\r\n  \r\n  /* Set the Vertical Front Porch (VFP)*/\r\n  hdsi->Instance->VVFPCR &= ~DSI_VVFPCR_VFP;\r\n  hdsi->Instance->VVFPCR |= VidCfg->VerticalFrontPorch;\r\n  \r\n  /* Set the Vertical Active period*/\r\n  hdsi->Instance->VVACR &= ~DSI_VVACR_VA;\r\n  hdsi->Instance->VVACR |= VidCfg->VerticalActive;\r\n  \r\n  /* Configure the command transmission mode */\r\n  hdsi->Instance->VMCR &= ~DSI_VMCR_LPCE;\r\n  hdsi->Instance->VMCR |= VidCfg->LPCommandEnable;\r\n  \r\n  /* Low power largest packet size */\r\n  hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE;\r\n  hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize)<<16);\r\n  \r\n  /* Low power VACT largest packet size */\r\n  hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE;\r\n  hdsi->Instance->LPMCR |= VidCfg->LPVACTLargestPacketSize;\r\n  \r\n  /* Enable LP transition in HFP period */\r\n  hdsi->Instance->VMCR &= ~DSI_VMCR_LPHFPE;\r\n  hdsi->Instance->VMCR |= VidCfg->LPHorizontalFrontPorchEnable;\r\n  \r\n  /* Enable LP transition in HBP period */\r\n  hdsi->Instance->VMCR &= ~DSI_VMCR_LPHBPE;\r\n  hdsi->Instance->VMCR |= VidCfg->LPHorizontalBackPorchEnable;\r\n  \r\n  /* Enable LP transition in VACT period */\r\n  hdsi->Instance->VMCR &= ~DSI_VMCR_LPVAE;\r\n  hdsi->Instance->VMCR |= VidCfg->LPVerticalActiveEnable;\r\n  \r\n  /* Enable LP transition in VFP period */\r\n  hdsi->Instance->VMCR &= ~DSI_VMCR_LPVFPE;\r\n  hdsi->Instance->VMCR |= VidCfg->LPVerticalFrontPorchEnable;\r\n  \r\n  /* Enable LP transition in VBP period */\r\n  hdsi->Instance->VMCR &= ~DSI_VMCR_LPVBPE;\r\n  hdsi->Instance->VMCR |= VidCfg->LPVerticalBackPorchEnable;\r\n  \r\n  /* Enable LP transition in vertical sync period */\r\n  hdsi->Instance->VMCR &= ~DSI_VMCR_LPVSAE;\r\n  hdsi->Instance->VMCR |= VidCfg->LPVerticalSyncActiveEnable;\r\n  \r\n  /* Enable the request for an acknowledge response at the end of a frame */\r\n  hdsi->Instance->VMCR &= ~DSI_VMCR_FBTAAE;\r\n  hdsi->Instance->VMCR |= VidCfg->FrameBTAAcknowledgeEnable;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdsi);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Select adapted command mode and configure the corresponding parameters\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @param  CmdCfg: pointer to a DSI_CmdCfgTypeDef structure that contains\r\n  *                 the DSI command mode configuration parameters\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hdsi);\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_DSI_COLOR_CODING(CmdCfg->ColorCoding));\r\n  assert_param(IS_DSI_TE_SOURCE(CmdCfg->TearingEffectSource));\r\n  assert_param(IS_DSI_TE_POLARITY(CmdCfg->TearingEffectPolarity));\r\n  assert_param(IS_DSI_AUTOMATIC_REFRESH(CmdCfg->AutomaticRefresh));\r\n  assert_param(IS_DSI_VS_POLARITY(CmdCfg->VSyncPol));\r\n  assert_param(IS_DSI_TE_ACK_REQUEST(CmdCfg->TEAcknowledgeRequest));\r\n  assert_param(IS_DSI_DE_POLARITY(CmdCfg->DEPolarity));\r\n  assert_param(IS_DSI_VSYNC_POLARITY(CmdCfg->VSPolarity));\r\n  assert_param(IS_DSI_HSYNC_POLARITY(CmdCfg->HSPolarity));\r\n  \r\n  /* Select command mode by setting CMDM and DSIM bits */\r\n  hdsi->Instance->MCR |= DSI_MCR_CMDM;\r\n  hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;\r\n  hdsi->Instance->WCFGR |= DSI_WCFGR_DSIM;\r\n  \r\n  /* Select the virtual channel for the LTDC interface traffic */\r\n  hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;\r\n  hdsi->Instance->LVCIDR |= CmdCfg->VirtualChannelID;\r\n  \r\n  /* Configure the polarity of control signals */\r\n  hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);\r\n  hdsi->Instance->LPCR |= (CmdCfg->DEPolarity | CmdCfg->VSPolarity | CmdCfg->HSPolarity);\r\n  \r\n  /* Select the color coding for the host */\r\n  hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;\r\n  hdsi->Instance->LCOLCR |= CmdCfg->ColorCoding;\r\n    \r\n  /* Select the color coding for the wrapper */\r\n  hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;\r\n  hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding)<<1);\r\n  \r\n  /* Configure the maximum allowed size for write memory command */\r\n  hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE;\r\n  hdsi->Instance->LCCR |= CmdCfg->CommandSize;\r\n  \r\n  /* Configure the tearing effect source and polarity and select the refresh mode */\r\n  hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC | DSI_WCFGR_TEPOL | DSI_WCFGR_AR | DSI_WCFGR_VSPOL);\r\n  hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh | CmdCfg->VSyncPol);\r\n  \r\n  /* Configure the tearing effect acknowledge request */\r\n  hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE;\r\n  hdsi->Instance->CMCR |= CmdCfg->TEAcknowledgeRequest;\r\n  \r\n  /* Enable the Tearing Effect interrupt */\r\n  __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_TE);\r\n  \r\n  /* Enable the End of Refresh interrupt */\r\n  __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_ER);\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdsi);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Configure command transmission mode: High-speed or Low-power\r\n  *         and enable/disable acknowledge request after packet transmission\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @param  LPCmd: pointer to a DSI_LPCmdTypeDef structure that contains\r\n  *                the DSI command transmission mode configuration parameters\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hdsi);\r\n  \r\n  assert_param(IS_DSI_LP_GSW0P(LPCmd->LPGenShortWriteNoP));\r\n  assert_param(IS_DSI_LP_GSW1P(LPCmd->LPGenShortWriteOneP));\r\n  assert_param(IS_DSI_LP_GSW2P(LPCmd->LPGenShortWriteTwoP));\r\n  assert_param(IS_DSI_LP_GSR0P(LPCmd->LPGenShortReadNoP));\r\n  assert_param(IS_DSI_LP_GSR1P(LPCmd->LPGenShortReadOneP));\r\n  assert_param(IS_DSI_LP_GSR2P(LPCmd->LPGenShortReadTwoP));\r\n  assert_param(IS_DSI_LP_GLW(LPCmd->LPGenLongWrite));\r\n  assert_param(IS_DSI_LP_DSW0P(LPCmd->LPDcsShortWriteNoP));\r\n  assert_param(IS_DSI_LP_DSW1P(LPCmd->LPDcsShortWriteOneP));\r\n  assert_param(IS_DSI_LP_DSR0P(LPCmd->LPDcsShortReadNoP));\r\n  assert_param(IS_DSI_LP_DLW(LPCmd->LPDcsLongWrite));\r\n  assert_param(IS_DSI_LP_MRDP(LPCmd->LPMaxReadPacket));\r\n  assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest));\r\n  \r\n  /* Select High-speed or Low-power for command transmission */\r\n  hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX |\\\r\n                            DSI_CMCR_GSW1TX |\\\r\n                            DSI_CMCR_GSW2TX |\\\r\n                            DSI_CMCR_GSR0TX |\\\r\n                            DSI_CMCR_GSR1TX |\\\r\n                            DSI_CMCR_GSR2TX |\\\r\n                            DSI_CMCR_GLWTX  |\\\r\n                            DSI_CMCR_DSW0TX |\\\r\n                            DSI_CMCR_DSW1TX |\\\r\n                            DSI_CMCR_DSR0TX |\\\r\n                            DSI_CMCR_DLWTX  |\\\r\n                            DSI_CMCR_MRDPS);\r\n  hdsi->Instance->CMCR |= (LPCmd->LPGenShortWriteNoP  |\\\r\n                           LPCmd->LPGenShortWriteOneP |\\\r\n                           LPCmd->LPGenShortWriteTwoP |\\\r\n                           LPCmd->LPGenShortReadNoP   |\\\r\n                           LPCmd->LPGenShortReadOneP  |\\\r\n                           LPCmd->LPGenShortReadTwoP  |\\\r\n                           LPCmd->LPGenLongWrite      |\\\r\n                           LPCmd->LPDcsShortWriteNoP  |\\\r\n                           LPCmd->LPDcsShortWriteOneP |\\\r\n                           LPCmd->LPDcsShortReadNoP   |\\\r\n                           LPCmd->LPDcsLongWrite      |\\\r\n                           LPCmd->LPMaxReadPacket);\r\n  \r\n  /* Configure the acknowledge request after each packet transmission */\r\n  hdsi->Instance->CMCR &= ~DSI_CMCR_ARE;\r\n  hdsi->Instance->CMCR |= LPCmd->AcknowledgeRequest;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdsi);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Configure the flow control parameters\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @param  FlowControl: flow control feature(s) to be enabled.\r\n  *                      This parameter can be any combination of @ref DSI_FlowControl.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hdsi);\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_DSI_FLOW_CONTROL(FlowControl));\r\n  \r\n  /* Set the DSI Host Protocol Configuration Register */\r\n  hdsi->Instance->PCR &= ~DSI_FLOW_CONTROL_ALL;\r\n  hdsi->Instance->PCR |= FlowControl;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdsi);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Configure the DSI PHY timer parameters\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @param  PhyTimers: DSI_PHY_TimerTypeDef structure that contains\r\n  *                    the DSI PHY timing parameters\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers)\r\n{\r\n  uint32_t maxTime;\r\n  /* Process locked */\r\n  __HAL_LOCK(hdsi);\r\n  \r\n  maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime)? PhyTimers->ClockLaneLP2HSTime: PhyTimers->ClockLaneHS2LPTime;\r\n\r\n  /* Clock lane timer configuration */\r\n\r\n  /* In Automatic Clock Lane control mode, the DSI Host can turn off the clock lane between two\r\n     High-Speed transmission.\r\n     To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed\r\n     to Low-Power and from Low-Power to High-Speed.\r\n     This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR).\r\n     But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME.\r\n\r\n     Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME.\r\n  */\r\n  hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME | DSI_CLTCR_HS2LP_TIME);\r\n  hdsi->Instance->CLTCR |= (maxTime | ((maxTime)<<16));\r\n  \r\n  /* Data lane timer configuration */\r\n  hdsi->Instance->DLTCR &= ~(DSI_DLTCR_MRD_TIME | DSI_DLTCR_LP2HS_TIME | DSI_DLTCR_HS2LP_TIME);\r\n  hdsi->Instance->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime)<<16) | ((PhyTimers->DataLaneHS2LPTime)<<24));\r\n  \r\n  /* Configure the wait period to request HS transmission after a stop state */\r\n  hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME;\r\n  hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime)<<8);\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdsi);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Configure the DSI HOST timeout parameters\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @param  HostTimeouts: DSI_HOST_TimeoutTypeDef structure that contains\r\n  *                       the DSI host timeout parameters\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hdsi);\r\n  \r\n  /* Set the timeout clock division factor */\r\n  hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV;\r\n  hdsi->Instance->CCR = ((HostTimeouts->TimeoutCkdiv)<<8);\r\n  \r\n  /* High-speed transmission timeout */\r\n  hdsi->Instance->TCCR[0] &= ~DSI_TCCR0_HSTX_TOCNT;\r\n  hdsi->Instance->TCCR[0] |= ((HostTimeouts->HighSpeedTransmissionTimeout)<<16);\r\n  \r\n  /* Low-power reception timeout */\r\n  hdsi->Instance->TCCR[0] &= ~DSI_TCCR0_LPRX_TOCNT;\r\n  hdsi->Instance->TCCR[0] |= HostTimeouts->LowPowerReceptionTimeout;\r\n  \r\n  /* High-speed read timeout */\r\n  hdsi->Instance->TCCR[1] &= ~DSI_TCCR1_HSRD_TOCNT;\r\n  hdsi->Instance->TCCR[1] |= HostTimeouts->HighSpeedReadTimeout;\r\n  \r\n  /* Low-power read timeout */\r\n  hdsi->Instance->TCCR[2] &= ~DSI_TCCR2_LPRD_TOCNT;\r\n  hdsi->Instance->TCCR[2] |= HostTimeouts->LowPowerReadTimeout;\r\n  \r\n  /* High-speed write timeout */\r\n  hdsi->Instance->TCCR[3] &= ~DSI_TCCR3_HSWR_TOCNT;\r\n  hdsi->Instance->TCCR[3] |= HostTimeouts->HighSpeedWriteTimeout;\r\n  \r\n  /* High-speed write presp mode */\r\n  hdsi->Instance->TCCR[3] &= ~DSI_TCCR3_PM;\r\n  hdsi->Instance->TCCR[3] |= HostTimeouts->HighSpeedWritePrespMode;\r\n  \r\n  /* Low-speed write timeout */\r\n  hdsi->Instance->TCCR[4] &= ~DSI_TCCR4_LPWR_TOCNT;\r\n  hdsi->Instance->TCCR[4] |= HostTimeouts->LowPowerWriteTimeout;\r\n  \r\n  /* BTA timeout */\r\n  hdsi->Instance->TCCR[5] &= ~DSI_TCCR5_BTA_TOCNT;\r\n  hdsi->Instance->TCCR[5] |= HostTimeouts->BTATimeout;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdsi);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Start the DSI module\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hdsi);\r\n  \r\n  /* Enable the DSI host */\r\n  __HAL_DSI_ENABLE(hdsi);\r\n  \r\n  /* Enable the DSI wrapper */\r\n  __HAL_DSI_WRAPPER_ENABLE(hdsi);\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdsi);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stop the DSI module\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hdsi);\r\n  \r\n  /* Disable the DSI host */\r\n  __HAL_DSI_DISABLE(hdsi);\r\n  \r\n  /* Disable the DSI wrapper */\r\n  __HAL_DSI_WRAPPER_DISABLE(hdsi);\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdsi);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Refresh the display in command mode\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hdsi);\r\n  \r\n  /* Update the display */\r\n  hdsi->Instance->WCR |= DSI_WCR_LTDCEN;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdsi);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Controls the display color mode in Video mode\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @param  ColorMode: Color mode (full or 8-colors).\r\n  *                    This parameter can be any value of @ref DSI_Color_Mode\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hdsi);\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_DSI_COLOR_MODE(ColorMode));\r\n  \r\n  /* Update the display color mode */\r\n  hdsi->Instance->WCR &= ~DSI_WCR_COLM;\r\n  hdsi->Instance->WCR |= ColorMode;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdsi);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Control the display shutdown in Video mode\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @param  Shutdown: Shut-down (Display-ON or Display-OFF).\r\n  *                   This parameter can be any value of @ref DSI_ShutDown\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hdsi);\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_DSI_SHUT_DOWN(Shutdown));\r\n  \r\n  /* Update the display Shutdown */\r\n  hdsi->Instance->WCR &= ~DSI_WCR_SHTDN;\r\n  hdsi->Instance->WCR |= Shutdown;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdsi);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  DCS or Generic short write command\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @param  ChannelID: Virtual channel ID.\r\n  * @param  Mode: DSI short packet data type.\r\n  *               This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type.\r\n  * @param  Param1: DSC command or first generic parameter.\r\n  *                 This parameter can be any value of @ref DSI_DCS_Command or a\r\n  *                 generic command code.\r\n  * @param  Param2: DSC parameter or second generic parameter.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,\r\n                                     uint32_t ChannelID,\r\n                                     uint32_t Mode,\r\n                                     uint32_t Param1,\r\n                                     uint32_t Param2)\r\n{\r\n  uint32_t tickstart = 0;\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hdsi);\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode));\r\n  \r\n  /* Get tick */ \r\n  tickstart = HAL_GetTick();\r\n  \r\n  /* Wait for Command FIFO Empty */\r\n  while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0)\r\n  {\r\n    /* Check for the Timeout */\r\n    if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)\r\n    {\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hdsi);\r\n      \r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  \r\n  /* Configure the packet to send a short DCS command with 0 or 1 parameter */\r\n  DSI_ConfigPacketHeader(hdsi->Instance,\r\n                         ChannelID,\r\n                         Mode,\r\n                         Param1,\r\n                         Param2);\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdsi);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  DCS or Generic long write command\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @param  ChannelID: Virtual channel ID.\r\n  * @param  Mode: DSI long packet data type.\r\n  *               This parameter can be any value of @ref DSI_LONG_WRITE_PKT_Data_Type.\r\n  * @param  NbParams: Number of parameters.\r\n  * @param  Param1: DSC command or first generic parameter.\r\n  *                 This parameter can be any value of @ref DSI_DCS_Command or a \r\n  *                 generic command code\r\n  * @param  ParametersTable: Pointer to parameter values table.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,\r\n                                    uint32_t ChannelID,\r\n                                    uint32_t Mode,\r\n                                    uint32_t NbParams,\r\n                                    uint32_t Param1,\r\n                                    uint8_t* ParametersTable)\r\n{\r\n  uint32_t uicounter = 0;\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hdsi);\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_DSI_LONG_WRITE_PACKET_TYPE(Mode));\r\n  \r\n  /* Get tick */ \r\n  tickstart = HAL_GetTick();\r\n  \r\n  /* Wait for Command FIFO Empty */\r\n  while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == RESET)\r\n  {\r\n    /* Check for the Timeout */\r\n    if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)\r\n    {\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hdsi);\r\n      \r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  \r\n  /* Set the DCS code hexadecimal on payload byte 1, and the other parameters on the write FIFO command*/\r\n  while(uicounter < NbParams)\r\n  {\r\n    if(uicounter == 0x00)\r\n    {\r\n      hdsi->Instance->GPDR=(Param1 | \\\r\n                            ((uint32_t)(*(ParametersTable + uicounter)) << 8) | \\\r\n                            ((uint32_t)(*(ParametersTable + uicounter+1))<<16) | \\\r\n                            ((uint32_t)(*(ParametersTable + uicounter+2))<<24));\r\n      uicounter += 3;\r\n    }\r\n    else\r\n    {\r\n      hdsi->Instance->GPDR=((uint32_t)(*(ParametersTable + uicounter)) | \\\r\n                            ((uint32_t)(*(ParametersTable + uicounter+1)) << 8) | \\\r\n                            ((uint32_t)(*(ParametersTable + uicounter+2)) << 16) | \\\r\n                            ((uint32_t)(*(ParametersTable + uicounter+3)) << 24));\r\n      uicounter+=4;\r\n    }\r\n  }\r\n  \r\n  /* Configure the packet to send a long DCS command */\r\n  DSI_ConfigPacketHeader(hdsi->Instance,\r\n                         ChannelID,\r\n                         Mode,\r\n                         ((NbParams+1)&0x00FF),\r\n                         (((NbParams+1)&0xFF00)>>8));\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdsi);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Read command (DCS or generic)\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @param  ChannelNbr: Virtual channel ID\r\n  * @param  Array: pointer to a buffer to store the payload of a read back operation.\r\n  * @param  Size: Data size to be read (in byte).\r\n  * @param  Mode: DSI read packet data type.\r\n  *               This parameter can be any value of @ref DSI_SHORT_READ_PKT_Data_Type.\r\n  * @param  DCSCmd: DCS get/read command.\r\n  * @param  ParametersTable: Pointer to parameter values table.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,\r\n                               uint32_t ChannelNbr,\r\n                               uint8_t* Array,\r\n                               uint32_t Size,\r\n                               uint32_t Mode,\r\n                               uint32_t DCSCmd,\r\n                               uint8_t* ParametersTable)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hdsi);\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_DSI_READ_PACKET_TYPE(Mode));\r\n  \r\n  if(Size > 2)\r\n  {\r\n    /* set max return packet size */\r\n    HAL_DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((Size)&0xFF), (((Size)>>8)&0xFF));\r\n  }\r\n  \r\n  /* Configure the packet to read command */\r\n  if (Mode == DSI_DCS_SHORT_PKT_READ)\r\n  {\r\n    DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, DCSCmd, 0);\r\n  }\r\n  else if (Mode == DSI_GEN_SHORT_PKT_READ_P0)\r\n  {\r\n    DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, 0, 0);\r\n  }\r\n  else if (Mode == DSI_GEN_SHORT_PKT_READ_P1)\r\n  {\r\n    DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0], 0);\r\n  }\r\n  else if (Mode == DSI_GEN_SHORT_PKT_READ_P2)\r\n  {\r\n    DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0], ParametersTable[1]);\r\n  }\r\n  else\r\n  {\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hdsi);\r\n      \r\n    return HAL_ERROR;    \r\n  }\r\n  \r\n  /* Get tick */ \r\n  tickstart = HAL_GetTick();\r\n  \r\n  /* Check that the payload read FIFO is not empty */\r\n  while((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == DSI_GPSR_PRDFE)\r\n  {\r\n    /* Check for the Timeout */\r\n    if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)\r\n    {\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hdsi);\r\n      \r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  \r\n  /* Get the first byte */\r\n  *((uint32_t *)Array) = (hdsi->Instance->GPDR);\r\n  if (Size > 4)\r\n  {\r\n    Size -= 4;\r\n    Array += 4;\r\n  }\r\n  else\r\n  {\r\n    /* Process unlocked */\r\n    __HAL_UNLOCK(hdsi);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  \r\n  /* Get tick */ \r\n  tickstart = HAL_GetTick();\r\n  \r\n  /* Get the remaining bytes if any */\r\n  while(((int)(Size)) > 0)\r\n  {\r\n    if((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0)\r\n    {\r\n      *((uint32_t *)Array) = (hdsi->Instance->GPDR);\r\n      Size -= 4;\r\n      Array += 4;\r\n    }\r\n    \r\n    /* Check for the Timeout */\r\n    if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)\r\n    {\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hdsi);\r\n      \r\n      return HAL_TIMEOUT;\r\n    }    \r\n  }\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdsi);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running\r\n  *         (only data lanes are in ULPM)\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hdsi);\r\n  \r\n  /* ULPS Request on Data Lanes */\r\n  hdsi->Instance->PUCR |= DSI_PUCR_URDL;\r\n  \r\n  /* Get tick */ \r\n  tickstart = HAL_GetTick();\r\n  \r\n  /* Wait until the D-PHY active lanes enter into ULPM */\r\n  if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)\r\n  {\r\n\twhile((hdsi->Instance->PSR & DSI_PSR_UAN0) != RESET)\r\n    {\r\n      /* Check for the Timeout */\r\n      if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)\r\n      {\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hdsi);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)\r\n  {\r\n\twhile((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != RESET)\r\n    {\r\n      /* Check for the Timeout */\r\n      if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)\r\n      {\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hdsi);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdsi);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running\r\n  *         (only data lanes are in ULPM)\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hdsi);\r\n  \r\n  /* Exit ULPS on Data Lanes */\r\n  hdsi->Instance->PUCR |= DSI_PUCR_UEDL;\r\n  \r\n  /* Get tick */ \r\n  tickstart = HAL_GetTick();\r\n  \r\n  /* Wait until all active lanes exit ULPM */\r\n  if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)\r\n  {\r\n\twhile((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)\r\n    {\r\n      /* Check for the Timeout */\r\n      if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)\r\n      {\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hdsi);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)\r\n  {\r\n\twhile((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1))\r\n    {\r\n      /* Check for the Timeout */\r\n      if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)\r\n      {\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hdsi);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* De-assert the ULPM requests and the ULPM exit bits */\r\n  hdsi->Instance->PUCR = 0;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdsi);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off\r\n  *         (both data and clock lanes are in ULPM)\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hdsi);\r\n  \r\n  /* Clock lane configuration: no more HS request */\r\n  hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC;\r\n  \r\n  /* Use system PLL as byte lane clock source before stopping DSIPHY clock source */\r\n  __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PLLR);\r\n  \r\n  /* ULPS Request on Clock and Data Lanes */\r\n  hdsi->Instance->PUCR |= (DSI_PUCR_URCL | DSI_PUCR_URDL);\r\n  \r\n  /* Get tick */ \r\n  tickstart = HAL_GetTick();\r\n  \r\n  /* Wait until all active lanes exit ULPM */\r\n  if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)\r\n  {\r\n\twhile((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != RESET)\r\n    {\r\n      /* Check for the Timeout */\r\n      if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)\r\n      {\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hdsi);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)\r\n  {\r\n\twhile((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != RESET)\r\n    {\r\n      /* Check for the Timeout */\r\n      if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)\r\n      {\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hdsi);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Turn off the DSI PLL */\r\n  __HAL_DSI_PLL_DISABLE(hdsi);\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdsi);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off\r\n  *         (both data and clock lanes are in ULPM)\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hdsi);\r\n  \r\n  /* Turn on the DSI PLL */\r\n  __HAL_DSI_PLL_ENABLE(hdsi);\r\n  \r\n  /* Get tick */ \r\n  tickstart = HAL_GetTick();\r\n  \r\n  /* Wait for the lock of the PLL */\r\n  while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET)\r\n  {\r\n    /* Check for the Timeout */\r\n    if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)\r\n    {\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hdsi);\r\n      \r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  \r\n  /* Exit ULPS on Clock and Data Lanes */\r\n  hdsi->Instance->PUCR |= (DSI_PUCR_UECL | DSI_PUCR_UEDL);\r\n  \r\n  /* Get tick */ \r\n  tickstart = HAL_GetTick();\r\n  \r\n  /* Wait until all active lanes exit ULPM */\r\n  if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)\r\n  {\r\n\twhile((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC))\r\n    {\r\n      /* Check for the Timeout */\r\n      if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)\r\n      {\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hdsi);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)\r\n  {\r\n\twhile((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC))\r\n    {\r\n      /* Check for the Timeout */\r\n      if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)\r\n      {\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hdsi);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* De-assert the ULPM requests and the ULPM exit bits */\r\n  hdsi->Instance->PUCR = 0;\r\n  \r\n  /* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */\r\n  __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_DSIPHY);\r\n  \r\n  /* Restore clock lane configuration to HS */\r\n  hdsi->Instance->CLCR |= DSI_CLCR_DPCC;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdsi);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Start test pattern generation\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @param  Mode: Pattern generator mode\r\n  *          This parameter can be one of the following values:\r\n  *           0 : Color bars (horizontal or vertical)\r\n  *           1 : BER pattern (vertical only)\r\n  * @param  Orientation: Pattern generator orientation\r\n  *          This parameter can be one of the following values:\r\n  *           0 : Vertical color bars\r\n  *           1 : Horizontal color bars\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hdsi);\r\n  \r\n  /* Configure pattern generator mode and orientation */\r\n  hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM | DSI_VMCR_PGO);\r\n  hdsi->Instance->VMCR |= ((Mode<<20) | (Orientation<<24));\r\n  \r\n  /* Enable pattern generator by setting PGE bit */\r\n  hdsi->Instance->VMCR |= DSI_VMCR_PGE;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdsi);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stop test pattern generation\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hdsi);\r\n  \r\n  /* Disable pattern generator by clearing PGE bit */\r\n  hdsi->Instance->VMCR &= ~DSI_VMCR_PGE;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdsi);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Set Slew-Rate And Delay Tuning\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @param  CommDelay: Communication delay to be adjusted.\r\n  *                    This parameter can be any value of @ref DSI_Communication_Delay\r\n  * @param  Lane: select between clock or data lanes.\r\n  *               This parameter can be any value of @ref DSI_Lane_Group\r\n  * @param  Value: Custom value of the slew-rate or delay\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hdsi);\r\n  \r\n  /* Check function parameters */\r\n  assert_param(IS_DSI_COMMUNICATION_DELAY(CommDelay));\r\n  assert_param(IS_DSI_LANE_GROUP(Lane));\r\n  \r\n  switch(CommDelay)\r\n  {\r\n  case DSI_SLEW_RATE_HSTX:\r\n    if(Lane == DSI_CLOCK_LANE)\r\n    {\r\n      /* High-Speed Transmission Slew Rate Control on Clock Lane */\r\n      hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXSRCCL;\r\n      hdsi->Instance->WPCR[1] |= Value<<16;\r\n    }\r\n    else if(Lane == DSI_DATA_LANES)\r\n    {\r\n      /* High-Speed Transmission Slew Rate Control on Data Lanes */\r\n      hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXSRCDL;\r\n      hdsi->Instance->WPCR[1] |= Value<<18;\r\n    }\r\n    break;\r\n  case DSI_SLEW_RATE_LPTX:\r\n    if(Lane == DSI_CLOCK_LANE)\r\n    {\r\n      /* Low-Power transmission Slew Rate Compensation on Clock Lane */\r\n      hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_LPSRCCL;\r\n      hdsi->Instance->WPCR[1] |= Value<<6;\r\n    }\r\n    else if(Lane == DSI_DATA_LANES)\r\n    {\r\n      /* Low-Power transmission Slew Rate Compensation on Data Lanes */\r\n      hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_LPSRCDL;\r\n      hdsi->Instance->WPCR[1] |= Value<<8;\r\n    }\r\n    break;\r\n  case DSI_HS_DELAY:\r\n    if(Lane == DSI_CLOCK_LANE)\r\n    {\r\n      /* High-Speed Transmission Delay on Clock Lane */\r\n      hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXDCL;\r\n      hdsi->Instance->WPCR[1] |= Value;\r\n    }\r\n    else if(Lane == DSI_DATA_LANES)\r\n    {\r\n      /* High-Speed Transmission Delay on Data Lanes */\r\n      hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXDDL;\r\n      hdsi->Instance->WPCR[1] |= Value<<2;\r\n    }\r\n    break;\r\n  default:\r\n    break;\r\n  }\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdsi);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Low-Power Reception Filter Tuning\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @param  Frequency: cutoff frequency of low-pass filter at the input of LPRX\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hdsi);\r\n  \r\n  /* Low-Power RX low-pass Filtering Tuning */\r\n  hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_LPRXFT;\r\n  hdsi->Instance->WPCR[1] |= Frequency<<25;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdsi);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Activate an additional current path on all lanes to meet the SDDTx parameter\r\n  *         defined in the MIPI D-PHY specification\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @param  State: ENABLE or DISABLE\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hdsi);\r\n  \r\n  /* Check function parameters */\r\n  assert_param(IS_FUNCTIONAL_STATE(State));\r\n  \r\n  /* Activate/Disactivate additional current path on all lanes */\r\n  hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_SDDC;\r\n  hdsi->Instance->WPCR[1] |= ((uint32_t)State << 12);\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdsi);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Custom lane pins configuration\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @param  CustomLane: Function to be applyed on selected lane.\r\n  *                     This parameter can be any value of @ref DSI_CustomLane\r\n  * @param  Lane: select between clock or data lane 0 or data lane 1.\r\n  *               This parameter can be any value of @ref DSI_Lane_Select\r\n  * @param  State: ENABLE or DISABLE\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hdsi);\r\n  \r\n  /* Check function parameters */\r\n  assert_param(IS_DSI_CUSTOM_LANE(CustomLane));\r\n  assert_param(IS_DSI_LANE(Lane));\r\n  assert_param(IS_FUNCTIONAL_STATE(State));\r\n  \r\n  switch(CustomLane)\r\n  {\r\n  case DSI_SWAP_LANE_PINS:\r\n    if(Lane == DSI_CLOCK_LANE)\r\n    {\r\n      /* Swap pins on clock lane */\r\n      hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_SWCL;\r\n      hdsi->Instance->WPCR[0] |= ((uint32_t)State << 6);\r\n    }\r\n    else if(Lane == DSI_DATA_LANE0)\r\n    {\r\n      /* Swap pins on data lane 0 */\r\n      hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_SWDL0;\r\n      hdsi->Instance->WPCR[0] |= ((uint32_t)State << 7);\r\n    }\r\n    else if(Lane == DSI_DATA_LANE1)\r\n    {\r\n      /* Swap pins on data lane 1 */\r\n      hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_SWDL1;\r\n      hdsi->Instance->WPCR[0] |= ((uint32_t)State << 8);\r\n    }\r\n    break;\r\n  case DSI_INVERT_HS_SIGNAL:\r\n    if(Lane == DSI_CLOCK_LANE)\r\n    {\r\n      /* Invert HS signal on clock lane */\r\n      hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_HSICL;\r\n      hdsi->Instance->WPCR[0] |= ((uint32_t)State << 9);\r\n    }\r\n    else if(Lane == DSI_DATA_LANE0)\r\n    {\r\n      /* Invert HS signal on data lane 0 */\r\n      hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_HSIDL0;\r\n      hdsi->Instance->WPCR[0] |= ((uint32_t)State << 10);\r\n    }\r\n    else if(Lane == DSI_DATA_LANE1)\r\n    {\r\n      /* Invert HS signal on data lane 1 */\r\n      hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_HSIDL1;\r\n      hdsi->Instance->WPCR[0] |= ((uint32_t)State << 11);\r\n    }\r\n    break;\r\n  default:\r\n    break;\r\n  }\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdsi);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Set custom timing for the PHY\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @param  Timing: PHY timing to be adjusted.\r\n  *                 This parameter can be any value of @ref DSI_PHY_Timing\r\n  * @param  State: ENABLE or DISABLE\r\n  * @param  Value: Custom value of the timing\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hdsi);\r\n  \r\n  /* Check function parameters */\r\n  assert_param(IS_DSI_PHY_TIMING(Timing));\r\n  assert_param(IS_FUNCTIONAL_STATE(State));\r\n  \r\n  switch(Timing)\r\n  {\r\n  case DSI_TCLK_POST:\r\n    /* Enable/Disable custom timing setting */\r\n    hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TCLKPOSTEN;\r\n    hdsi->Instance->WPCR[0] |= ((uint32_t)State << 27);\r\n    \r\n    if(State)\r\n    {\r\n      /* Set custom value */\r\n      hdsi->Instance->WPCR[4] &= ~DSI_WPCR4_TCLKPOST;\r\n      hdsi->Instance->WPCR[4] |= Value & DSI_WPCR4_TCLKPOST;\r\n    }\r\n    \r\n    break;\r\n  case DSI_TLPX_CLK:\r\n    /* Enable/Disable custom timing setting */\r\n    hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TLPXCEN;\r\n    hdsi->Instance->WPCR[0] |= ((uint32_t)State << 26);\r\n    \r\n    if(State)\r\n    {\r\n      /* Set custom value */\r\n      hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_TLPXC;\r\n      hdsi->Instance->WPCR[3] |= (Value << 24) & DSI_WPCR3_TLPXC;\r\n    }\r\n    \r\n    break;\r\n  case DSI_THS_EXIT:\r\n    /* Enable/Disable custom timing setting */\r\n    hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSEXITEN;\r\n    hdsi->Instance->WPCR[0] |= ((uint32_t)State << 25);\r\n    \r\n    if(State)\r\n    {\r\n      /* Set custom value */\r\n      hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_THSEXIT;\r\n      hdsi->Instance->WPCR[3] |= (Value << 16) & DSI_WPCR3_THSEXIT;\r\n    }\r\n    \r\n    break;\r\n  case DSI_TLPX_DATA:\r\n    /* Enable/Disable custom timing setting */\r\n    hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TLPXDEN;\r\n    hdsi->Instance->WPCR[0] |= ((uint32_t)State << 24);\r\n    \r\n    if(State)\r\n    {\r\n      /* Set custom value */\r\n      hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_TLPXD;\r\n      hdsi->Instance->WPCR[3] |= (Value << 8) & DSI_WPCR3_TLPXD;\r\n    }\r\n    \r\n    break;\r\n  case DSI_THS_ZERO:\r\n    /* Enable/Disable custom timing setting */\r\n    hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSZEROEN;\r\n    hdsi->Instance->WPCR[0] |= ((uint32_t)State << 23);\r\n    \r\n    if(State)\r\n    {\r\n      /* Set custom value */\r\n      hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_THSZERO;\r\n      hdsi->Instance->WPCR[3] |= Value & DSI_WPCR3_THSZERO;\r\n    }\r\n    \r\n    break;\r\n  case DSI_THS_TRAIL:\r\n    /* Enable/Disable custom timing setting */\r\n    hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSTRAILEN;\r\n    hdsi->Instance->WPCR[0] |= ((uint32_t)State << 22);\r\n    \r\n    if(State)\r\n    {\r\n      /* Set custom value */\r\n      hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_THSTRAIL;\r\n      hdsi->Instance->WPCR[2] |= (Value << 24) & DSI_WPCR2_THSTRAIL;\r\n    }\r\n    \r\n    break;\r\n  case DSI_THS_PREPARE:\r\n    /* Enable/Disable custom timing setting */\r\n    hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSPREPEN;\r\n    hdsi->Instance->WPCR[0] |= ((uint32_t)State << 21);\r\n    \r\n    if(State)\r\n    {\r\n      /* Set custom value */\r\n      hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_THSPREP;\r\n      hdsi->Instance->WPCR[2] |= (Value << 16) & DSI_WPCR2_THSPREP;\r\n    }\r\n    \r\n    break;\r\n  case DSI_TCLK_ZERO:\r\n    /* Enable/Disable custom timing setting */\r\n    hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TCLKZEROEN;\r\n    hdsi->Instance->WPCR[0] |= ((uint32_t)State << 20);\r\n    \r\n    if(State)\r\n    {\r\n      /* Set custom value */\r\n      hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_TCLKZERO;\r\n      hdsi->Instance->WPCR[2] |= (Value << 8) & DSI_WPCR2_TCLKZERO;\r\n    }\r\n    \r\n    break;\r\n  case DSI_TCLK_PREPARE:\r\n    /* Enable/Disable custom timing setting */\r\n    hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TCLKPREPEN;\r\n    hdsi->Instance->WPCR[0] |= ((uint32_t)State << 19);\r\n    \r\n    if(State)\r\n    {\r\n      /* Set custom value */\r\n      hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_TCLKPREP;\r\n      hdsi->Instance->WPCR[2] |= Value & DSI_WPCR2_TCLKPREP;\r\n    }\r\n    \r\n    break;\r\n  default:\r\n    break;\r\n  }\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdsi);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Force the Clock/Data Lane in TX Stop Mode\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @param  Lane: select between clock or data lanes.\r\n  *               This parameter can be any value of @ref DSI_Lane_Group\r\n  * @param  State: ENABLE or DISABLE\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hdsi);\r\n  \r\n  /* Check function parameters */\r\n  assert_param(IS_DSI_LANE_GROUP(Lane));\r\n  assert_param(IS_FUNCTIONAL_STATE(State));\r\n  \r\n  if(Lane == DSI_CLOCK_LANE)\r\n  {\r\n    /* Force/Unforce the Clock Lane in TX Stop Mode */\r\n    hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_FTXSMCL;\r\n    hdsi->Instance->WPCR[0] |= ((uint32_t)State << 12);\r\n  }\r\n  else if(Lane == DSI_DATA_LANES)\r\n  {\r\n    /* Force/Unforce the Data Lanes in TX Stop Mode */\r\n    hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_FTXSMDL;\r\n    hdsi->Instance->WPCR[0] |= ((uint32_t)State << 13);\r\n  }\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdsi);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Forces LP Receiver in Low-Power Mode\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @param  State: ENABLE or DISABLE\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hdsi);\r\n  \r\n  /* Check function parameters */\r\n  assert_param(IS_FUNCTIONAL_STATE(State));\r\n  \r\n  /* Force/Unforce LP Receiver in Low-Power Mode */\r\n  hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_FLPRXLPM;\r\n  hdsi->Instance->WPCR[1] |= ((uint32_t)State << 22);\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdsi);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Force Data Lanes in RX Mode after a BTA\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @param  State: ENABLE or DISABLE\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hdsi);\r\n  \r\n  /* Check function parameters */\r\n  assert_param(IS_FUNCTIONAL_STATE(State));\r\n  \r\n  /* Force Data Lanes in RX Mode */\r\n  hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TDDL;\r\n  hdsi->Instance->WPCR[0] |= ((uint32_t)State << 16);\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdsi);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Enable a pull-down on the lanes to prevent from floating states when unused\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @param  State: ENABLE or DISABLE\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hdsi);\r\n  \r\n  /* Check function parameters */\r\n  assert_param(IS_FUNCTIONAL_STATE(State));\r\n  \r\n  /* Enable/Disable pull-down on lanes */\r\n  hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_PDEN;\r\n  hdsi->Instance->WPCR[0] |= ((uint32_t)State << 18);\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdsi);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Switch off the contention detection on data lanes\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @param  State: ENABLE or DISABLE\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hdsi);\r\n  \r\n  /* Check function parameters */\r\n  assert_param(IS_FUNCTIONAL_STATE(State));\r\n  \r\n  /* Contention Detection on Data Lanes OFF */\r\n  hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_CDOFFDL;\r\n  hdsi->Instance->WPCR[0] |= ((uint32_t)State << 14);\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hdsi);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup DSI_Group4 Peripheral State and Errors functions\r\n *  @brief    Peripheral State and Errors functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                  ##### Peripheral State and Errors functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides functions allowing to\r\n      (+) Check the DSI state.\r\n      (+) Get error code.  \r\n\r\n@endverbatim\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @brief  Return the DSI state\r\n  * @param  hdsi: pointer to a DSI_HandleTypeDef structure that contains\r\n  *               the configuration information for the DSI.\r\n  * @retval HAL state\r\n  */\r\nHAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi)\r\n{\r\n  return hdsi->State;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n#endif /*STM32F769xx | STM32F779xx */  \r\n#endif /* HAL_DSI_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_eth.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   ETH HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the Ethernet (ETH) peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + IO operation functions\r\n  *           + Peripheral Control functions \r\n  *           + Peripheral State and Errors functions\r\n  *\r\n  @verbatim\r\n  ==============================================================================\r\n                    ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]\r\n      (#)Declare a ETH_HandleTypeDef handle structure, for example:\r\n         ETH_HandleTypeDef  heth;\r\n        \r\n      (#)Fill parameters of Init structure in heth handle\r\n  \r\n      (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...) \r\n\r\n      (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:\r\n          (##) Enable the Ethernet interface clock using \r\n               (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();\r\n               (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();\r\n               (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();\r\n           \r\n          (##) Initialize the related GPIO clocks\r\n          (##) Configure Ethernet pin-out\r\n          (##) Configure Ethernet NVIC interrupt (IT mode)   \r\n    \r\n      (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:\r\n          (##) HAL_ETH_DMATxDescListInit(); for Transmission process\r\n          (##) HAL_ETH_DMARxDescListInit(); for Reception process\r\n\r\n      (#)Enable MAC and DMA transmission and reception:\r\n          (##) HAL_ETH_Start();\r\n\r\n      (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer \r\n         the frame to MAC TX FIFO:\r\n         (##) HAL_ETH_TransmitFrame();\r\n\r\n      (#)Poll for a received frame in ETH RX DMA Descriptors and get received \r\n         frame parameters\r\n         (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)\r\n\r\n      (#) Get a received frame when an ETH RX interrupt occurs:\r\n         (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)\r\n\r\n      (#) Communicate with external PHY device:\r\n         (##) Read a specific register from the PHY  \r\n              HAL_ETH_ReadPHYRegister();\r\n         (##) Write data to a specific RHY register:\r\n              HAL_ETH_WritePHYRegister();\r\n\r\n      (#) Configure the Ethernet MAC after ETH peripheral initialization\r\n          HAL_ETH_ConfigMAC(); all MAC parameters should be filled.\r\n      \r\n      (#) Configure the Ethernet DMA after ETH peripheral initialization\r\n          HAL_ETH_ConfigDMA(); all DMA parameters should be filled.\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup ETH ETH \r\n  * @brief ETH HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_ETH_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @defgroup ETH_Private_Constants ETH Private Constants\r\n  * @{\r\n  */\r\n#define ETH_TIMEOUT_SWRESET                 ((uint32_t)500)  \r\n#define ETH_TIMEOUT_LINKED_STATE          ((uint32_t)5000)  \r\n#define ETH_TIMEOUT_AUTONEGO_COMPLETED    ((uint32_t)5000) \r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/** @defgroup ETH_Private_Functions ETH Private Functions\r\n  * @{\r\n  */\r\nstatic void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);\r\nstatic void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);\r\nstatic void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);\r\nstatic void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);\r\nstatic void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);\r\nstatic void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);\r\nstatic void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);\r\nstatic void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);\r\nstatic void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);\r\nstatic void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);\r\nstatic void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup ETH_Exported_Functions ETH Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions \r\n  *  @brief   Initialization and Configuration functions \r\n  *\r\n  @verbatim    \r\n  ===============================================================================\r\n            ##### Initialization and de-initialization functions #####\r\n  ===============================================================================\r\n  [..]  This section provides functions allowing to:\r\n      (+) Initialize and configure the Ethernet peripheral\r\n      (+) De-initialize the Ethernet peripheral\r\n\r\n  @endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the Ethernet MAC and DMA according to default\r\n  *         parameters.\r\n  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains\r\n  *         the configuration information for ETHERNET module\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)\r\n{\r\n  uint32_t tempreg = 0, phyreg = 0;\r\n  uint32_t hclk = 60000000;\r\n  uint32_t tickstart = 0;\r\n  uint32_t err = ETH_SUCCESS;\r\n  \r\n  /* Check the ETH peripheral state */\r\n  if(heth == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Check parameters */\r\n  assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));\r\n  assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));\r\n  assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));\r\n  assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));  \r\n  \r\n  if(heth->State == HAL_ETH_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    heth->Lock = HAL_UNLOCKED;\r\n    /* Init the low level hardware : GPIO, CLOCK, NVIC. */\r\n    HAL_ETH_MspInit(heth);\r\n  }\r\n  \r\n  /* Enable SYSCFG Clock */\r\n  __HAL_RCC_SYSCFG_CLK_ENABLE();\r\n  \r\n  /* Select MII or RMII Mode*/\r\n  SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);\r\n  SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;\r\n  \r\n  /* Ethernet Software reset */\r\n  /* Set the SWR bit: resets all MAC subsystem internal registers and logic */\r\n  /* After reset all the registers holds their respective reset values */\r\n  (heth->Instance)->DMABMR |= ETH_DMABMR_SR;\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  /* Wait for software reset */\r\n  while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)\r\n  {\r\n    /* Check for the Timeout */\r\n    if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET)\r\n    {     \r\n      heth->State= HAL_ETH_STATE_TIMEOUT;\r\n  \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(heth);\r\n    \r\n      /* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are  \r\n         not available, please check your external PHY or the IO configuration */\r\n               \r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  \r\n  /*-------------------------------- MAC Initialization ----------------------*/\r\n  /* Get the ETHERNET MACMIIAR value */\r\n  tempreg = (heth->Instance)->MACMIIAR;\r\n  /* Clear CSR Clock Range CR[2:0] bits */\r\n  tempreg &= ETH_MACMIIAR_CR_MASK;\r\n  \r\n  /* Get hclk frequency value */\r\n  hclk = HAL_RCC_GetHCLKFreq();\r\n  \r\n  /* Set CR bits depending on hclk value */\r\n  if((hclk >= 20000000)&&(hclk < 35000000))\r\n  {\r\n    /* CSR Clock Range between 20-35 MHz */\r\n    tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;\r\n  }\r\n  else if((hclk >= 35000000)&&(hclk < 60000000))\r\n  {\r\n    /* CSR Clock Range between 35-60 MHz */ \r\n    tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;\r\n  }  \r\n  else if((hclk >= 60000000)&&(hclk < 100000000))\r\n  {\r\n    /* CSR Clock Range between 60-100 MHz */ \r\n    tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;\r\n  }  \r\n  else if((hclk >= 100000000)&&(hclk < 150000000))\r\n  {\r\n    /* CSR Clock Range between 100-150 MHz */ \r\n    tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;\r\n  }\r\n  else /* ((hclk >= 150000000)&&(hclk <= 216000000)) */\r\n  {\r\n    /* CSR Clock Range between 150-216 MHz */ \r\n    tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;    \r\n  }\r\n  \r\n  /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */\r\n  (heth->Instance)->MACMIIAR = (uint32_t)tempreg;\r\n  \r\n  /*-------------------- PHY initialization and configuration ----------------*/\r\n  /* Put the PHY in reset mode */\r\n  if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)\r\n  {\r\n    /* In case of write timeout */\r\n    err = ETH_ERROR;\r\n    \r\n    /* Config MAC and DMA */\r\n    ETH_MACDMAConfig(heth, err);\r\n    \r\n    /* Set the ETH peripheral state to READY */\r\n    heth->State = HAL_ETH_STATE_READY;\r\n    \r\n    /* Return HAL_ERROR */\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Delay to assure PHY reset */\r\n  HAL_Delay(PHY_RESET_DELAY);\r\n  \r\n  if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)\r\n  {\r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n    \r\n    /* We wait for linked status */\r\n    do\r\n    {\r\n      HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);\r\n      \r\n      /* Check for the Timeout */\r\n      if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE)\r\n      {\r\n        /* In case of write timeout */\r\n        err = ETH_ERROR;\r\n      \r\n        /* Config MAC and DMA */\r\n        ETH_MACDMAConfig(heth, err);\r\n        \r\n        heth->State= HAL_ETH_STATE_READY;\r\n  \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(heth);\r\n    \r\n        return HAL_TIMEOUT;\r\n      }\r\n    } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));\r\n\r\n    \r\n    /* Enable Auto-Negotiation */\r\n    if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)\r\n    {\r\n      /* In case of write timeout */\r\n      err = ETH_ERROR;\r\n      \r\n      /* Config MAC and DMA */\r\n      ETH_MACDMAConfig(heth, err);\r\n      \r\n      /* Set the ETH peripheral state to READY */\r\n      heth->State = HAL_ETH_STATE_READY;\r\n      \r\n      /* Return HAL_ERROR */\r\n      return HAL_ERROR;   \r\n    }\r\n    \r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n    \r\n    /* Wait until the auto-negotiation will be completed */\r\n    do\r\n    {\r\n      HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);\r\n      \r\n      /* Check for the Timeout */\r\n      if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED)\r\n      {\r\n        /* In case of write timeout */\r\n        err = ETH_ERROR;\r\n      \r\n        /* Config MAC and DMA */\r\n        ETH_MACDMAConfig(heth, err);\r\n        \r\n        heth->State= HAL_ETH_STATE_READY;\r\n  \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(heth);\r\n    \r\n        return HAL_TIMEOUT;\r\n      }\r\n      \r\n    } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));\r\n    \r\n    /* Read the result of the auto-negotiation */\r\n    if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)\r\n    {\r\n      /* In case of write timeout */\r\n      err = ETH_ERROR;\r\n      \r\n      /* Config MAC and DMA */\r\n      ETH_MACDMAConfig(heth, err);\r\n      \r\n      /* Set the ETH peripheral state to READY */\r\n      heth->State = HAL_ETH_STATE_READY;\r\n      \r\n      /* Return HAL_ERROR */\r\n      return HAL_ERROR;   \r\n    }\r\n    \r\n    /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */\r\n    if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)\r\n    {\r\n      /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */\r\n      (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;  \r\n    }\r\n    else\r\n    {\r\n      /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */\r\n      (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;           \r\n    }\r\n    /* Configure the MAC with the speed fixed by the auto-negotiation process */\r\n    if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)\r\n    {  \r\n      /* Set Ethernet speed to 10M following the auto-negotiation */\r\n      (heth->Init).Speed = ETH_SPEED_10M; \r\n    }\r\n    else\r\n    {   \r\n      /* Set Ethernet speed to 100M following the auto-negotiation */ \r\n      (heth->Init).Speed = ETH_SPEED_100M;\r\n    }\r\n  }\r\n  else /* AutoNegotiation Disable */\r\n  {\r\n    /* Check parameters */\r\n    assert_param(IS_ETH_SPEED(heth->Init.Speed));\r\n    assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));\r\n    \r\n    /* Set MAC Speed and Duplex Mode */\r\n    if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) |\r\n                                                (uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)\r\n    {\r\n      /* In case of write timeout */\r\n      err = ETH_ERROR;\r\n      \r\n      /* Config MAC and DMA */\r\n      ETH_MACDMAConfig(heth, err);\r\n      \r\n      /* Set the ETH peripheral state to READY */\r\n      heth->State = HAL_ETH_STATE_READY;\r\n      \r\n      /* Return HAL_ERROR */\r\n      return HAL_ERROR;\r\n    }  \r\n    \r\n    /* Delay to assure PHY configuration */\r\n    HAL_Delay(PHY_CONFIG_DELAY);\r\n  }\r\n  \r\n  /* Config MAC and DMA */\r\n  ETH_MACDMAConfig(heth, err);\r\n  \r\n  /* Set ETH HAL State to Ready */\r\n  heth->State= HAL_ETH_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  De-Initializes the ETH peripheral. \r\n  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains\r\n  *         the configuration information for ETHERNET module\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)\r\n{\r\n  /* Set the ETH peripheral state to BUSY */\r\n  heth->State = HAL_ETH_STATE_BUSY;\r\n  \r\n  /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */\r\n  HAL_ETH_MspDeInit(heth);\r\n  \r\n  /* Set ETH HAL state to Disabled */\r\n  heth->State= HAL_ETH_STATE_RESET;\r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(heth);\r\n\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the DMA Tx descriptors in chain mode.\r\n  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains\r\n  *         the configuration information for ETHERNET module  \r\n  * @param  DMATxDescTab: Pointer to the first Tx desc list \r\n  * @param  TxBuff: Pointer to the first TxBuffer list\r\n  * @param  TxBuffCount: Number of the used Tx desc in the list\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)\r\n{\r\n  uint32_t i = 0;\r\n  ETH_DMADescTypeDef *dmatxdesc;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(heth);\r\n  \r\n  /* Set the ETH peripheral state to BUSY */\r\n  heth->State = HAL_ETH_STATE_BUSY;\r\n  \r\n  /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */\r\n  heth->TxDesc = DMATxDescTab;\r\n  \r\n  /* Fill each DMATxDesc descriptor with the right values */   \r\n  for(i=0; i < TxBuffCount; i++)\r\n  {\r\n    /* Get the pointer on the ith member of the Tx Desc list */\r\n    dmatxdesc = DMATxDescTab + i;\r\n    \r\n    /* Set Second Address Chained bit */\r\n    dmatxdesc->Status = ETH_DMATXDESC_TCH;  \r\n    \r\n    /* Set Buffer1 address pointer */\r\n    dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);\r\n    \r\n    if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)\r\n    {\r\n      /* Set the DMA Tx descriptors checksum insertion */\r\n      dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;\r\n    }\r\n    \r\n    /* Initialize the next descriptor with the Next Descriptor Polling Enable */\r\n    if(i < (TxBuffCount-1))\r\n    {\r\n      /* Set next descriptor address register with next descriptor base address */\r\n      dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);\r\n    }\r\n    else\r\n    {\r\n      /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ \r\n      dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;  \r\n    }\r\n  }\r\n  \r\n  /* Set Transmit Descriptor List Address Register */\r\n  (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;\r\n  \r\n  /* Set ETH HAL State to Ready */\r\n  heth->State= HAL_ETH_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(heth);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the DMA Rx descriptors in chain mode.\r\n  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains\r\n  *         the configuration information for ETHERNET module  \r\n  * @param  DMARxDescTab: Pointer to the first Rx desc list \r\n  * @param  RxBuff: Pointer to the first RxBuffer list\r\n  * @param  RxBuffCount: Number of the used Rx desc in the list\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)\r\n{\r\n  uint32_t i = 0;\r\n  ETH_DMADescTypeDef *DMARxDesc;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(heth);\r\n  \r\n  /* Set the ETH peripheral state to BUSY */\r\n  heth->State = HAL_ETH_STATE_BUSY;\r\n  \r\n  /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */\r\n  heth->RxDesc = DMARxDescTab; \r\n  \r\n  /* Fill each DMARxDesc descriptor with the right values */\r\n  for(i=0; i < RxBuffCount; i++)\r\n  {\r\n    /* Get the pointer on the ith member of the Rx Desc list */\r\n    DMARxDesc = DMARxDescTab+i;\r\n    \r\n    /* Set Own bit of the Rx descriptor Status */\r\n    DMARxDesc->Status = ETH_DMARXDESC_OWN;\r\n    \r\n    /* Set Buffer1 size and Second Address Chained bit */\r\n    DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;  \r\n    \r\n    /* Set Buffer1 address pointer */\r\n    DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);\r\n    \r\n    if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)\r\n    {\r\n      /* Enable Ethernet DMA Rx Descriptor interrupt */\r\n      DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;\r\n    }\r\n    \r\n    /* Initialize the next descriptor with the Next Descriptor Polling Enable */\r\n    if(i < (RxBuffCount-1))\r\n    {\r\n      /* Set next descriptor address register with next descriptor base address */\r\n      DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); \r\n    }\r\n    else\r\n    {\r\n      /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ \r\n      DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); \r\n    }\r\n  }\r\n  \r\n  /* Set Receive Descriptor List Address Register */\r\n  (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;\r\n  \r\n  /* Set ETH HAL State to Ready */\r\n  heth->State= HAL_ETH_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(heth);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the ETH MSP.\r\n  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains\r\n  *         the configuration information for ETHERNET module\r\n  * @retval None\r\n  */\r\n__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(heth);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n  the HAL_ETH_MspInit could be implemented in the user file\r\n  */\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes ETH MSP.\r\n  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains\r\n  *         the configuration information for ETHERNET module\r\n  * @retval None\r\n  */\r\n__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(heth);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n  the HAL_ETH_MspDeInit could be implemented in the user file\r\n  */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Exported_Functions_Group2 IO operation functions \r\n  *  @brief   Data transfers functions \r\n  *\r\n  @verbatim   \r\n  ==============================================================================\r\n                          ##### IO operation functions #####\r\n  ==============================================================================  \r\n  [..]  This section provides functions allowing to:\r\n        (+) Transmit a frame\r\n            HAL_ETH_TransmitFrame();\r\n        (+) Receive a frame\r\n            HAL_ETH_GetReceivedFrame();\r\n            HAL_ETH_GetReceivedFrame_IT();\r\n        (+) Read from an External PHY register\r\n            HAL_ETH_ReadPHYRegister();\r\n        (+) Write to an External PHY register\r\n            HAL_ETH_WritePHYRegister();\r\n\r\n  @endverbatim\r\n  \r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Sends an Ethernet frame. \r\n  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains\r\n  *         the configuration information for ETHERNET module\r\n  * @param  FrameLength: Amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)\r\n{\r\n  uint32_t bufcount = 0, size = 0, i = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(heth);\r\n  \r\n  /* Set the ETH peripheral state to BUSY */\r\n  heth->State = HAL_ETH_STATE_BUSY;\r\n  \r\n  if (FrameLength == 0) \r\n  {\r\n    /* Set ETH HAL state to READY */\r\n    heth->State = HAL_ETH_STATE_READY;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(heth);\r\n    \r\n    return  HAL_ERROR;                                    \r\n  }  \r\n  \r\n  /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */\r\n  if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)\r\n  {  \r\n    /* OWN bit set */\r\n    heth->State = HAL_ETH_STATE_BUSY_TX;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(heth);\r\n    \r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Get the number of needed Tx buffers for the current frame */\r\n  if (FrameLength > ETH_TX_BUF_SIZE)\r\n  {\r\n    bufcount = FrameLength/ETH_TX_BUF_SIZE;\r\n    if (FrameLength % ETH_TX_BUF_SIZE) \r\n    {\r\n      bufcount++;\r\n    }\r\n  }\r\n  else \r\n  {  \r\n    bufcount = 1;\r\n  }\r\n  if (bufcount == 1)\r\n  {\r\n    /* Set LAST and FIRST segment */\r\n    heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;\r\n    /* Set frame size */\r\n    heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);\r\n    /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */\r\n    heth->TxDesc->Status |= ETH_DMATXDESC_OWN;\r\n    /* Point to next descriptor */\r\n    heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);\r\n  }\r\n  else\r\n  {\r\n    for (i=0; i< bufcount; i++)\r\n    {\r\n      /* Clear FIRST and LAST segment bits */\r\n      heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);\r\n      \r\n      if (i == 0) \r\n      {\r\n        /* Setting the first segment bit */\r\n        heth->TxDesc->Status |= ETH_DMATXDESC_FS;  \r\n      }\r\n      \r\n      /* Program size */\r\n      heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);\r\n      \r\n      if (i == (bufcount-1))\r\n      {\r\n        /* Setting the last segment bit */\r\n        heth->TxDesc->Status |= ETH_DMATXDESC_LS;\r\n        size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;\r\n        heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);\r\n      }\r\n      \r\n      /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */\r\n      heth->TxDesc->Status |= ETH_DMATXDESC_OWN;\r\n      /* point to next descriptor */\r\n      heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);\r\n    }\r\n  }\r\n  \r\n  /* When Tx Buffer unavailable flag is set: clear it and resume transmission */\r\n  if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)\r\n  {\r\n    /* Clear TBUS ETHERNET DMA flag */\r\n    (heth->Instance)->DMASR = ETH_DMASR_TBUS;\r\n    /* Resume DMA transmission*/\r\n    (heth->Instance)->DMATPDR = 0;\r\n  }\r\n  \r\n  /* Set ETH HAL State to Ready */\r\n  heth->State = HAL_ETH_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(heth);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Checks for received frames. \r\n  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains\r\n  *         the configuration information for ETHERNET module\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)\r\n{\r\n  uint32_t framelength = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(heth);\r\n  \r\n  /* Check the ETH state to BUSY */\r\n  heth->State = HAL_ETH_STATE_BUSY;\r\n  \r\n  /* Check if segment is not owned by DMA */\r\n  /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */\r\n  if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))\r\n  {\r\n    /* Check if last segment */\r\n    if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) \r\n    {\r\n      /* increment segment count */\r\n      (heth->RxFrameInfos).SegCount++;\r\n      \r\n      /* Check if last segment is first segment: one segment contains the frame */\r\n      if ((heth->RxFrameInfos).SegCount == 1)\r\n      {\r\n        (heth->RxFrameInfos).FSRxDesc =heth->RxDesc;\r\n      }\r\n      \r\n      heth->RxFrameInfos.LSRxDesc = heth->RxDesc;\r\n      \r\n      /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */\r\n      framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;\r\n      heth->RxFrameInfos.length = framelength;\r\n      \r\n      /* Get the address of the buffer start address */\r\n      heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;\r\n      /* point to next descriptor */\r\n      heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);\r\n      \r\n      /* Set HAL State to Ready */\r\n      heth->State = HAL_ETH_STATE_READY;\r\n      \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(heth);\r\n      \r\n      /* Return function status */\r\n      return HAL_OK;\r\n    }\r\n    /* Check if first segment */\r\n    else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)\r\n    {\r\n      (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;\r\n      (heth->RxFrameInfos).LSRxDesc = NULL;\r\n      (heth->RxFrameInfos).SegCount = 1;\r\n      /* Point to next descriptor */\r\n      heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);\r\n    }\r\n    /* Check if intermediate segment */ \r\n    else\r\n    {\r\n      (heth->RxFrameInfos).SegCount++;\r\n      /* Point to next descriptor */\r\n      heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);\r\n    } \r\n  }\r\n  \r\n  /* Set ETH HAL State to Ready */\r\n  heth->State = HAL_ETH_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(heth);\r\n  \r\n  /* Return function status */\r\n  return HAL_ERROR;\r\n}\r\n\r\n/**\r\n  * @brief  Gets the Received frame in interrupt mode. \r\n  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains\r\n  *         the configuration information for ETHERNET module\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)\r\n{\r\n  uint32_t descriptorscancounter = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(heth);\r\n  \r\n  /* Set ETH HAL State to BUSY */\r\n  heth->State = HAL_ETH_STATE_BUSY;\r\n  \r\n  /* Scan descriptors owned by CPU */\r\n  while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))\r\n  {\r\n    /* Just for security */\r\n    descriptorscancounter++;\r\n    \r\n    /* Check if first segment in frame */\r\n    /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */  \r\n    if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)\r\n    { \r\n      heth->RxFrameInfos.FSRxDesc = heth->RxDesc;\r\n      heth->RxFrameInfos.SegCount = 1;   \r\n      /* Point to next descriptor */\r\n      heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);\r\n    }\r\n    /* Check if intermediate segment */\r\n    /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */\r\n    else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)\r\n    {\r\n      /* Increment segment count */\r\n      (heth->RxFrameInfos.SegCount)++;\r\n      /* Point to next descriptor */\r\n      heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);\r\n    }\r\n    /* Should be last segment */\r\n    else\r\n    { \r\n      /* Last segment */\r\n      heth->RxFrameInfos.LSRxDesc = heth->RxDesc;\r\n      \r\n      /* Increment segment count */\r\n      (heth->RxFrameInfos.SegCount)++;\r\n      \r\n      /* Check if last segment is first segment: one segment contains the frame */\r\n      if ((heth->RxFrameInfos.SegCount) == 1)\r\n      {\r\n        heth->RxFrameInfos.FSRxDesc = heth->RxDesc;\r\n      }\r\n      \r\n      /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */\r\n      heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;\r\n      \r\n      /* Get the address of the buffer start address */ \r\n      heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;\r\n      \r\n      /* Point to next descriptor */      \r\n      heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);\r\n      \r\n      /* Set HAL State to Ready */\r\n      heth->State = HAL_ETH_STATE_READY;\r\n      \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(heth);\r\n  \r\n      /* Return function status */\r\n      return HAL_OK;\r\n    }\r\n  }\r\n\r\n  /* Set HAL State to Ready */\r\n  heth->State = HAL_ETH_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(heth);\r\n  \r\n  /* Return function status */\r\n  return HAL_ERROR;\r\n}\r\n\r\n/**\r\n  * @brief  This function handles ETH interrupt request.\r\n  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains\r\n  *         the configuration information for ETHERNET module\r\n  * @retval HAL status\r\n  */\r\nvoid HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)\r\n{\r\n  /* Frame received */\r\n  if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R)) \r\n  {\r\n    /* Receive complete callback */\r\n    HAL_ETH_RxCpltCallback(heth);\r\n    \r\n     /* Clear the Eth DMA Rx IT pending bits */\r\n    __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);\r\n\r\n    /* Set HAL State to Ready */\r\n    heth->State = HAL_ETH_STATE_READY;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(heth);\r\n\r\n  }\r\n  /* Frame transmitted */\r\n  else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T)) \r\n  {\r\n    /* Transfer complete callback */\r\n    HAL_ETH_TxCpltCallback(heth);\r\n    \r\n    /* Clear the Eth DMA Tx IT pending bits */\r\n    __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);\r\n\r\n    /* Set HAL State to Ready */\r\n    heth->State = HAL_ETH_STATE_READY;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(heth);\r\n  }\r\n  \r\n  /* Clear the interrupt flags */\r\n  __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);\r\n  \r\n  /* ETH DMA Error */\r\n  if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))\r\n  {\r\n    /* Ethernet Error callback */\r\n    HAL_ETH_ErrorCallback(heth);\r\n\r\n    /* Clear the interrupt flags */\r\n    __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);\r\n  \r\n    /* Set HAL State to Ready */\r\n    heth->State = HAL_ETH_STATE_READY;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(heth);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Tx Transfer completed callbacks.\r\n  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains\r\n  *         the configuration information for ETHERNET module\r\n  * @retval None\r\n  */\r\n__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(heth);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n  the HAL_ETH_TxCpltCallback could be implemented in the user file\r\n  */ \r\n}\r\n\r\n/**\r\n  * @brief  Rx Transfer completed callbacks.\r\n  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains\r\n  *         the configuration information for ETHERNET module\r\n  * @retval None\r\n  */\r\n__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(heth);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n  the HAL_ETH_TxCpltCallback could be implemented in the user file\r\n  */ \r\n}\r\n\r\n/**\r\n  * @brief  Ethernet transfer error callbacks\r\n  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains\r\n  *         the configuration information for ETHERNET module\r\n  * @retval None\r\n  */\r\n__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(heth);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n  the HAL_ETH_TxCpltCallback could be implemented in the user file\r\n  */ \r\n}\r\n\r\n/**\r\n  * @brief  Reads a PHY register\r\n  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains\r\n  *         the configuration information for ETHERNET module                  \r\n  * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. \r\n  *                This parameter can be one of the following values: \r\n  *                   PHY_BCR: Transceiver Basic Control Register, \r\n  *                   PHY_BSR: Transceiver Basic Status Register.   \r\n  *                   More PHY register could be read depending on the used PHY\r\n  * @param RegValue: PHY register value                  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)\r\n{\r\n  uint32_t tmpreg = 0;     \r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Check parameters */\r\n  assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));\r\n  \r\n  /* Check the ETH peripheral state */\r\n  if(heth->State == HAL_ETH_STATE_BUSY_RD)\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n  /* Set ETH HAL State to BUSY_RD */\r\n  heth->State = HAL_ETH_STATE_BUSY_RD;\r\n  \r\n  /* Get the ETHERNET MACMIIAR value */\r\n  tmpreg = heth->Instance->MACMIIAR;\r\n  \r\n  /* Keep only the CSR Clock Range CR[2:0] bits value */\r\n  tmpreg &= ~ETH_MACMIIAR_CR_MASK;\r\n  \r\n  /* Prepare the MII address register value */\r\n  tmpreg |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address   */\r\n  tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR);                   /* Set the PHY register address */\r\n  tmpreg &= ~ETH_MACMIIAR_MW;                                           /* Set the read mode            */\r\n  tmpreg |= ETH_MACMIIAR_MB;                                            /* Set the MII Busy bit         */\r\n  \r\n  /* Write the result value into the MII Address register */\r\n  heth->Instance->MACMIIAR = tmpreg;\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  /* Check for the Busy flag */\r\n  while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)\r\n  {\r\n    /* Check for the Timeout */\r\n    if((HAL_GetTick() - tickstart ) > PHY_READ_TO)\r\n    {\r\n      heth->State= HAL_ETH_STATE_READY;\r\n  \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(heth);\r\n    \r\n      return HAL_TIMEOUT;\r\n    }\r\n    \r\n    tmpreg = heth->Instance->MACMIIAR;\r\n  }\r\n  \r\n  /* Get MACMIIDR value */\r\n  *RegValue = (uint16_t)(heth->Instance->MACMIIDR);\r\n  \r\n  /* Set ETH HAL State to READY */\r\n  heth->State = HAL_ETH_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Writes to a PHY register.\r\n  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains\r\n  *         the configuration information for ETHERNET module  \r\n  * @param  PHYReg: PHY register address, is the index of one of the 32 PHY register. \r\n  *          This parameter can be one of the following values: \r\n  *             PHY_BCR: Transceiver Control Register.  \r\n  *             More PHY register could be written depending on the used PHY\r\n  * @param  RegValue: the value to write\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)\r\n{\r\n  uint32_t tmpreg = 0;\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Check parameters */\r\n  assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));\r\n  \r\n  /* Check the ETH peripheral state */\r\n  if(heth->State == HAL_ETH_STATE_BUSY_WR)\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n  /* Set ETH HAL State to BUSY_WR */\r\n  heth->State = HAL_ETH_STATE_BUSY_WR;\r\n  \r\n  /* Get the ETHERNET MACMIIAR value */\r\n  tmpreg = heth->Instance->MACMIIAR;\r\n  \r\n  /* Keep only the CSR Clock Range CR[2:0] bits value */\r\n  tmpreg &= ~ETH_MACMIIAR_CR_MASK;\r\n  \r\n  /* Prepare the MII register address value */\r\n  tmpreg |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */\r\n  tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR);                 /* Set the PHY register address */\r\n  tmpreg |= ETH_MACMIIAR_MW;                                          /* Set the write mode */\r\n  tmpreg |= ETH_MACMIIAR_MB;                                          /* Set the MII Busy bit */\r\n  \r\n  /* Give the value to the MII data register */\r\n  heth->Instance->MACMIIDR = (uint16_t)RegValue;\r\n  \r\n  /* Write the result value into the MII Address register */\r\n  heth->Instance->MACMIIAR = tmpreg;\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  /* Check for the Busy flag */\r\n  while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)\r\n  {\r\n    /* Check for the Timeout */\r\n    if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)\r\n    {\r\n      heth->State= HAL_ETH_STATE_READY;\r\n  \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(heth);\r\n    \r\n      return HAL_TIMEOUT;\r\n    }\r\n    \r\n    tmpreg = heth->Instance->MACMIIAR;\r\n  }\r\n  \r\n  /* Set ETH HAL State to READY */\r\n  heth->State = HAL_ETH_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK; \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions\r\n *  @brief    Peripheral Control functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                  ##### Peripheral Control functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Enable MAC and DMA transmission and reception.\r\n          HAL_ETH_Start();\r\n      (+) Disable MAC and DMA transmission and reception. \r\n          HAL_ETH_Stop();\r\n      (+) Set the MAC configuration in runtime mode\r\n          HAL_ETH_ConfigMAC();\r\n      (+) Set the DMA configuration in runtime mode\r\n          HAL_ETH_ConfigDMA();\r\n\r\n@endverbatim\r\n  * @{\r\n  */ \r\n\r\n /**\r\n  * @brief  Enables Ethernet MAC and DMA reception/transmission \r\n  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains\r\n  *         the configuration information for ETHERNET module\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)\r\n{  \r\n  /* Process Locked */\r\n  __HAL_LOCK(heth);\r\n  \r\n  /* Set the ETH peripheral state to BUSY */\r\n  heth->State = HAL_ETH_STATE_BUSY;\r\n  \r\n  /* Enable transmit state machine of the MAC for transmission on the MII */\r\n  ETH_MACTransmissionEnable(heth);\r\n  \r\n  /* Enable receive state machine of the MAC for reception from the MII */\r\n  ETH_MACReceptionEnable(heth);\r\n  \r\n  /* Flush Transmit FIFO */\r\n  ETH_FlushTransmitFIFO(heth);\r\n  \r\n  /* Start DMA transmission */\r\n  ETH_DMATransmissionEnable(heth);\r\n  \r\n  /* Start DMA reception */\r\n  ETH_DMAReceptionEnable(heth);\r\n  \r\n  /* Set the ETH state to READY*/\r\n  heth->State= HAL_ETH_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(heth);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stop Ethernet MAC and DMA reception/transmission \r\n  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains\r\n  *         the configuration information for ETHERNET module\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)\r\n{  \r\n  /* Process Locked */\r\n  __HAL_LOCK(heth);\r\n  \r\n  /* Set the ETH peripheral state to BUSY */\r\n  heth->State = HAL_ETH_STATE_BUSY;\r\n  \r\n  /* Stop DMA transmission */\r\n  ETH_DMATransmissionDisable(heth);\r\n  \r\n  /* Stop DMA reception */\r\n  ETH_DMAReceptionDisable(heth);\r\n  \r\n  /* Disable receive state machine of the MAC for reception from the MII */\r\n  ETH_MACReceptionDisable(heth);\r\n  \r\n  /* Flush Transmit FIFO */\r\n  ETH_FlushTransmitFIFO(heth);\r\n  \r\n  /* Disable transmit state machine of the MAC for transmission on the MII */\r\n  ETH_MACTransmissionDisable(heth);\r\n  \r\n  /* Set the ETH state*/\r\n  heth->State = HAL_ETH_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(heth);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Set ETH MAC Configuration.\r\n  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains\r\n  *         the configuration information for ETHERNET module\r\n  * @param  macconf: MAC Configuration structure  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)\r\n{\r\n  uint32_t tmpreg = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(heth);\r\n  \r\n  /* Set the ETH peripheral state to BUSY */\r\n  heth->State= HAL_ETH_STATE_BUSY;\r\n  \r\n  assert_param(IS_ETH_SPEED(heth->Init.Speed));\r\n  assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode)); \r\n  \r\n  if (macconf != NULL)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));\r\n    assert_param(IS_ETH_JABBER(macconf->Jabber));\r\n    assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));\r\n    assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));\r\n    assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));\r\n    assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));\r\n    assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));\r\n    assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));\r\n    assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));\r\n    assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));\r\n    assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));\r\n    assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));\r\n    assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));\r\n    assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));\r\n    assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));\r\n    assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));\r\n    assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));\r\n    assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));\r\n    assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));\r\n    assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));\r\n    assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));\r\n    assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));\r\n    assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));\r\n    assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));\r\n    assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));\r\n    assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));\r\n    assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));\r\n    \r\n    /*------------------------ ETHERNET MACCR Configuration --------------------*/\r\n    /* Get the ETHERNET MACCR value */\r\n    tmpreg = (heth->Instance)->MACCR;\r\n    /* Clear WD, PCE, PS, TE and RE bits */\r\n    tmpreg &= ETH_MACCR_CLEAR_MASK;\r\n    \r\n    tmpreg |= (uint32_t)(macconf->Watchdog | \r\n                         macconf->Jabber | \r\n                         macconf->InterFrameGap |\r\n                         macconf->CarrierSense |\r\n                         (heth->Init).Speed | \r\n                         macconf->ReceiveOwn |\r\n                         macconf->LoopbackMode |\r\n                         (heth->Init).DuplexMode | \r\n                         macconf->ChecksumOffload |    \r\n                         macconf->RetryTransmission | \r\n                         macconf->AutomaticPadCRCStrip | \r\n                         macconf->BackOffLimit | \r\n                         macconf->DeferralCheck);\r\n    \r\n    /* Write to ETHERNET MACCR */\r\n    (heth->Instance)->MACCR = (uint32_t)tmpreg;\r\n    \r\n    /* Wait until the write operation will be taken into account :\r\n    at least four TX_CLK/RX_CLK clock cycles */\r\n    tmpreg = (heth->Instance)->MACCR;\r\n    HAL_Delay(ETH_REG_WRITE_DELAY);\r\n    (heth->Instance)->MACCR = tmpreg; \r\n    \r\n    /*----------------------- ETHERNET MACFFR Configuration --------------------*/ \r\n    /* Write to ETHERNET MACFFR */  \r\n    (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll | \r\n                                          macconf->SourceAddrFilter |\r\n                                          macconf->PassControlFrames |\r\n                                          macconf->BroadcastFramesReception | \r\n                                          macconf->DestinationAddrFilter |\r\n                                          macconf->PromiscuousMode |\r\n                                          macconf->MulticastFramesFilter |\r\n                                          macconf->UnicastFramesFilter);\r\n     \r\n     /* Wait until the write operation will be taken into account :\r\n     at least four TX_CLK/RX_CLK clock cycles */\r\n     tmpreg = (heth->Instance)->MACFFR;\r\n     HAL_Delay(ETH_REG_WRITE_DELAY);\r\n     (heth->Instance)->MACFFR = tmpreg;\r\n     \r\n     /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/\r\n     /* Write to ETHERNET MACHTHR */\r\n     (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;\r\n     \r\n     /* Write to ETHERNET MACHTLR */\r\n     (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;\r\n     /*----------------------- ETHERNET MACFCR Configuration --------------------*/\r\n     \r\n     /* Get the ETHERNET MACFCR value */  \r\n     tmpreg = (heth->Instance)->MACFCR;\r\n     /* Clear xx bits */\r\n     tmpreg &= ETH_MACFCR_CLEAR_MASK;\r\n     \r\n     tmpreg |= (uint32_t)((macconf->PauseTime << 16) | \r\n                          macconf->ZeroQuantaPause |\r\n                          macconf->PauseLowThreshold |\r\n                          macconf->UnicastPauseFrameDetect | \r\n                          macconf->ReceiveFlowControl |\r\n                          macconf->TransmitFlowControl); \r\n     \r\n     /* Write to ETHERNET MACFCR */\r\n     (heth->Instance)->MACFCR = (uint32_t)tmpreg;\r\n     \r\n     /* Wait until the write operation will be taken into account :\r\n     at least four TX_CLK/RX_CLK clock cycles */\r\n     tmpreg = (heth->Instance)->MACFCR;\r\n     HAL_Delay(ETH_REG_WRITE_DELAY);\r\n     (heth->Instance)->MACFCR = tmpreg;\r\n     \r\n     /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/\r\n     (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison | \r\n                                              macconf->VLANTagIdentifier);\r\n      \r\n      /* Wait until the write operation will be taken into account :\r\n      at least four TX_CLK/RX_CLK clock cycles */\r\n      tmpreg = (heth->Instance)->MACVLANTR;\r\n      HAL_Delay(ETH_REG_WRITE_DELAY);\r\n      (heth->Instance)->MACVLANTR = tmpreg;\r\n  }\r\n  else /* macconf == NULL : here we just configure Speed and Duplex mode */\r\n  {\r\n    /*------------------------ ETHERNET MACCR Configuration --------------------*/\r\n    /* Get the ETHERNET MACCR value */\r\n    tmpreg = (heth->Instance)->MACCR;\r\n    \r\n    /* Clear FES and DM bits */\r\n    tmpreg &= ~((uint32_t)0x00004800);\r\n    \r\n    tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);\r\n    \r\n    /* Write to ETHERNET MACCR */\r\n    (heth->Instance)->MACCR = (uint32_t)tmpreg;\r\n    \r\n    /* Wait until the write operation will be taken into account:\r\n    at least four TX_CLK/RX_CLK clock cycles */\r\n    tmpreg = (heth->Instance)->MACCR;\r\n    HAL_Delay(ETH_REG_WRITE_DELAY);\r\n    (heth->Instance)->MACCR = tmpreg;\r\n  }\r\n  \r\n  /* Set the ETH state to Ready */\r\n  heth->State= HAL_ETH_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(heth);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Sets ETH DMA Configuration.\r\n  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains\r\n  *         the configuration information for ETHERNET module\r\n  * @param  dmaconf: DMA Configuration structure  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)\r\n{\r\n  uint32_t tmpreg = 0;\r\n\r\n  /* Process Locked */\r\n  __HAL_LOCK(heth);\r\n  \r\n  /* Set the ETH peripheral state to BUSY */\r\n  heth->State= HAL_ETH_STATE_BUSY;\r\n\r\n  /* Check parameters */\r\n  assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));\r\n  assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));\r\n  assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));\r\n  assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));\r\n  assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));\r\n  assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));\r\n  assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));\r\n  assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));\r\n  assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));\r\n  assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));\r\n  assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));\r\n  assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));\r\n  assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));\r\n  assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));\r\n  assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));\r\n  assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));\r\n  \r\n  /*----------------------- ETHERNET DMAOMR Configuration --------------------*/\r\n  /* Get the ETHERNET DMAOMR value */\r\n  tmpreg = (heth->Instance)->DMAOMR;\r\n  /* Clear xx bits */\r\n  tmpreg &= ETH_DMAOMR_CLEAR_MASK;\r\n\r\n  tmpreg |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame | \r\n                       dmaconf->ReceiveStoreForward |\r\n                       dmaconf->FlushReceivedFrame |\r\n                       dmaconf->TransmitStoreForward | \r\n                       dmaconf->TransmitThresholdControl |\r\n                       dmaconf->ForwardErrorFrames |\r\n                       dmaconf->ForwardUndersizedGoodFrames |\r\n                       dmaconf->ReceiveThresholdControl |\r\n                       dmaconf->SecondFrameOperate);\r\n\r\n  /* Write to ETHERNET DMAOMR */\r\n  (heth->Instance)->DMAOMR = (uint32_t)tmpreg;\r\n\r\n  /* Wait until the write operation will be taken into account:\r\n  at least four TX_CLK/RX_CLK clock cycles */\r\n  tmpreg = (heth->Instance)->DMAOMR;\r\n  HAL_Delay(ETH_REG_WRITE_DELAY);\r\n  (heth->Instance)->DMAOMR = tmpreg;\r\n\r\n  /*----------------------- ETHERNET DMABMR Configuration --------------------*/\r\n  (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats | \r\n                                         dmaconf->FixedBurst |\r\n                                         dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */\r\n                                         dmaconf->TxDMABurstLength |\r\n                                         dmaconf->EnhancedDescriptorFormat |\r\n                                         (dmaconf->DescriptorSkipLength << 2) |\r\n                                         dmaconf->DMAArbitration | \r\n                                         ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */\r\n\r\n   /* Wait until the write operation will be taken into account:\r\n      at least four TX_CLK/RX_CLK clock cycles */\r\n   tmpreg = (heth->Instance)->DMABMR;\r\n   HAL_Delay(ETH_REG_WRITE_DELAY);\r\n   (heth->Instance)->DMABMR = tmpreg;\r\n\r\n   /* Set the ETH state to Ready */\r\n   heth->State= HAL_ETH_STATE_READY;\r\n   \r\n   /* Process Unlocked */\r\n   __HAL_UNLOCK(heth);\r\n   \r\n   /* Return function status */\r\n   return HAL_OK; \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions \r\n  *  @brief   Peripheral State functions \r\n  *\r\n  @verbatim   \r\n  ===============================================================================\r\n                         ##### Peripheral State functions #####\r\n  ===============================================================================  \r\n  [..]\r\n  This subsection permits to get in run-time the status of the peripheral \r\n  and the data flow.\r\n       (+) Get the ETH handle state:\r\n           HAL_ETH_GetState();\r\n           \r\n\r\n  @endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Return the ETH HAL state\r\n  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains\r\n  *         the configuration information for ETHERNET module\r\n  * @retval HAL state\r\n  */\r\nHAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)\r\n{  \r\n  /* Return ETH state */\r\n  return heth->State;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @addtogroup ETH_Private_Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Configures Ethernet MAC and DMA with default parameters.\r\n  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains\r\n  *         the configuration information for ETHERNET module\r\n  * @param  err: Ethernet Init error\r\n  * @retval HAL status\r\n  */\r\nstatic void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)\r\n{\r\n  ETH_MACInitTypeDef macinit;\r\n  ETH_DMAInitTypeDef dmainit;\r\n  uint32_t tmpreg = 0;\r\n  \r\n  if (err != ETH_SUCCESS) /* Auto-negotiation failed */\r\n  {\r\n    /* Set Ethernet duplex mode to Full-duplex */\r\n    (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;\r\n    \r\n    /* Set Ethernet speed to 100M */\r\n    (heth->Init).Speed = ETH_SPEED_100M;\r\n  }\r\n  \r\n  /* Ethernet MAC default initialization **************************************/\r\n  macinit.Watchdog = ETH_WATCHDOG_ENABLE;\r\n  macinit.Jabber = ETH_JABBER_ENABLE;\r\n  macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;\r\n  macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;\r\n  macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;\r\n  macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;\r\n  if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)\r\n  {\r\n    macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;\r\n  }\r\n  else\r\n  {\r\n    macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;\r\n  }\r\n  macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;\r\n  macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;\r\n  macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;\r\n  macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;\r\n  macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;\r\n  macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;\r\n  macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;\r\n  macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;\r\n  macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;\r\n  macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;\r\n  macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;\r\n  macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;\r\n  macinit.HashTableHigh = 0x0;\r\n  macinit.HashTableLow = 0x0;\r\n  macinit.PauseTime = 0x0;\r\n  macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;\r\n  macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;\r\n  macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;\r\n  macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;\r\n  macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;\r\n  macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;\r\n  macinit.VLANTagIdentifier = 0x0;\r\n  \r\n  /*------------------------ ETHERNET MACCR Configuration --------------------*/\r\n  /* Get the ETHERNET MACCR value */\r\n  tmpreg = (heth->Instance)->MACCR;\r\n  /* Clear WD, PCE, PS, TE and RE bits */\r\n  tmpreg &= ETH_MACCR_CLEAR_MASK;\r\n  /* Set the WD bit according to ETH Watchdog value */\r\n  /* Set the JD: bit according to ETH Jabber value */\r\n  /* Set the IFG bit according to ETH InterFrameGap value */\r\n  /* Set the DCRS bit according to ETH CarrierSense value */\r\n  /* Set the FES bit according to ETH Speed value */ \r\n  /* Set the DO bit according to ETH ReceiveOwn value */ \r\n  /* Set the LM bit according to ETH LoopbackMode value */\r\n  /* Set the DM bit according to ETH Mode value */ \r\n  /* Set the IPCO bit according to ETH ChecksumOffload value */\r\n  /* Set the DR bit according to ETH RetryTransmission value */\r\n  /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */\r\n  /* Set the BL bit according to ETH BackOffLimit value */\r\n  /* Set the DC bit according to ETH DeferralCheck value */\r\n  tmpreg |= (uint32_t)(macinit.Watchdog | \r\n                       macinit.Jabber | \r\n                       macinit.InterFrameGap |\r\n                       macinit.CarrierSense |\r\n                       (heth->Init).Speed | \r\n                       macinit.ReceiveOwn |\r\n                       macinit.LoopbackMode |\r\n                       (heth->Init).DuplexMode | \r\n                       macinit.ChecksumOffload |    \r\n                       macinit.RetryTransmission | \r\n                       macinit.AutomaticPadCRCStrip | \r\n                       macinit.BackOffLimit | \r\n                       macinit.DeferralCheck);\r\n  \r\n  /* Write to ETHERNET MACCR */\r\n  (heth->Instance)->MACCR = (uint32_t)tmpreg;\r\n  \r\n  /* Wait until the write operation will be taken into account:\r\n     at least four TX_CLK/RX_CLK clock cycles */\r\n  tmpreg = (heth->Instance)->MACCR;\r\n  HAL_Delay(ETH_REG_WRITE_DELAY);\r\n  (heth->Instance)->MACCR = tmpreg; \r\n  \r\n  /*----------------------- ETHERNET MACFFR Configuration --------------------*/ \r\n  /* Set the RA bit according to ETH ReceiveAll value */\r\n  /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */\r\n  /* Set the PCF bit according to ETH PassControlFrames value */\r\n  /* Set the DBF bit according to ETH BroadcastFramesReception value */\r\n  /* Set the DAIF bit according to ETH DestinationAddrFilter value */\r\n  /* Set the PR bit according to ETH PromiscuousMode value */\r\n  /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */\r\n  /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */\r\n  /* Write to ETHERNET MACFFR */  \r\n  (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll | \r\n                                        macinit.SourceAddrFilter |\r\n                                        macinit.PassControlFrames |\r\n                                        macinit.BroadcastFramesReception | \r\n                                        macinit.DestinationAddrFilter |\r\n                                        macinit.PromiscuousMode |\r\n                                        macinit.MulticastFramesFilter |\r\n                                        macinit.UnicastFramesFilter);\r\n   \r\n   /* Wait until the write operation will be taken into account:\r\n      at least four TX_CLK/RX_CLK clock cycles */\r\n   tmpreg = (heth->Instance)->MACFFR;\r\n   HAL_Delay(ETH_REG_WRITE_DELAY);\r\n   (heth->Instance)->MACFFR = tmpreg;\r\n   \r\n   /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/\r\n   /* Write to ETHERNET MACHTHR */\r\n   (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;\r\n   \r\n   /* Write to ETHERNET MACHTLR */\r\n   (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;\r\n   /*----------------------- ETHERNET MACFCR Configuration -------------------*/\r\n   \r\n   /* Get the ETHERNET MACFCR value */  \r\n   tmpreg = (heth->Instance)->MACFCR;\r\n   /* Clear xx bits */\r\n   tmpreg &= ETH_MACFCR_CLEAR_MASK;\r\n   \r\n   /* Set the PT bit according to ETH PauseTime value */\r\n   /* Set the DZPQ bit according to ETH ZeroQuantaPause value */\r\n   /* Set the PLT bit according to ETH PauseLowThreshold value */\r\n   /* Set the UP bit according to ETH UnicastPauseFrameDetect value */\r\n   /* Set the RFE bit according to ETH ReceiveFlowControl value */\r\n   /* Set the TFE bit according to ETH TransmitFlowControl value */ \r\n   tmpreg |= (uint32_t)((macinit.PauseTime << 16) | \r\n                        macinit.ZeroQuantaPause |\r\n                        macinit.PauseLowThreshold |\r\n                        macinit.UnicastPauseFrameDetect | \r\n                        macinit.ReceiveFlowControl |\r\n                        macinit.TransmitFlowControl); \r\n   \r\n   /* Write to ETHERNET MACFCR */\r\n   (heth->Instance)->MACFCR = (uint32_t)tmpreg;\r\n   \r\n   /* Wait until the write operation will be taken into account:\r\n   at least four TX_CLK/RX_CLK clock cycles */\r\n   tmpreg = (heth->Instance)->MACFCR;\r\n   HAL_Delay(ETH_REG_WRITE_DELAY);\r\n   (heth->Instance)->MACFCR = tmpreg;\r\n   \r\n   /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/\r\n   /* Set the ETV bit according to ETH VLANTagComparison value */\r\n   /* Set the VL bit according to ETH VLANTagIdentifier value */  \r\n   (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison | \r\n                                            macinit.VLANTagIdentifier);\r\n    \r\n    /* Wait until the write operation will be taken into account:\r\n       at least four TX_CLK/RX_CLK clock cycles */\r\n    tmpreg = (heth->Instance)->MACVLANTR;\r\n    HAL_Delay(ETH_REG_WRITE_DELAY);\r\n    (heth->Instance)->MACVLANTR = tmpreg;\r\n    \r\n    /* Ethernet DMA default initialization ************************************/\r\n    dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;\r\n    dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;\r\n    dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;\r\n    dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;  \r\n    dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;\r\n    dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;\r\n    dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;\r\n    dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;\r\n    dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;\r\n    dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;\r\n    dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;\r\n    dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;\r\n    dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;\r\n    dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;\r\n    dmainit.DescriptorSkipLength = 0x0;\r\n    dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;\r\n    \r\n    /* Get the ETHERNET DMAOMR value */\r\n    tmpreg = (heth->Instance)->DMAOMR;\r\n    /* Clear xx bits */\r\n    tmpreg &= ETH_DMAOMR_CLEAR_MASK;\r\n    \r\n    /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */\r\n    /* Set the RSF bit according to ETH ReceiveStoreForward value */\r\n    /* Set the DFF bit according to ETH FlushReceivedFrame value */\r\n    /* Set the TSF bit according to ETH TransmitStoreForward value */\r\n    /* Set the TTC bit according to ETH TransmitThresholdControl value */\r\n    /* Set the FEF bit according to ETH ForwardErrorFrames value */\r\n    /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */\r\n    /* Set the RTC bit according to ETH ReceiveThresholdControl value */\r\n    /* Set the OSF bit according to ETH SecondFrameOperate value */\r\n    tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame | \r\n                         dmainit.ReceiveStoreForward |\r\n                         dmainit.FlushReceivedFrame |\r\n                         dmainit.TransmitStoreForward | \r\n                         dmainit.TransmitThresholdControl |\r\n                         dmainit.ForwardErrorFrames |\r\n                         dmainit.ForwardUndersizedGoodFrames |\r\n                         dmainit.ReceiveThresholdControl |\r\n                         dmainit.SecondFrameOperate);\r\n    \r\n    /* Write to ETHERNET DMAOMR */\r\n    (heth->Instance)->DMAOMR = (uint32_t)tmpreg;\r\n    \r\n    /* Wait until the write operation will be taken into account:\r\n       at least four TX_CLK/RX_CLK clock cycles */\r\n    tmpreg = (heth->Instance)->DMAOMR;\r\n    HAL_Delay(ETH_REG_WRITE_DELAY);\r\n    (heth->Instance)->DMAOMR = tmpreg;\r\n    \r\n    /*----------------------- ETHERNET DMABMR Configuration ------------------*/\r\n    /* Set the AAL bit according to ETH AddressAlignedBeats value */\r\n    /* Set the FB bit according to ETH FixedBurst value */\r\n    /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */\r\n    /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */\r\n    /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/\r\n    /* Set the DSL bit according to ETH DesciptorSkipLength value */\r\n    /* Set the PR and DA bits according to ETH DMAArbitration value */\r\n    (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats | \r\n                                          dmainit.FixedBurst |\r\n                                          dmainit.RxDMABurstLength |    /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */\r\n                                          dmainit.TxDMABurstLength |\r\n                                          dmainit.EnhancedDescriptorFormat |\r\n                                          (dmainit.DescriptorSkipLength << 2) |\r\n                                          dmainit.DMAArbitration |\r\n                                          ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */\r\n     \r\n     /* Wait until the write operation will be taken into account:\r\n        at least four TX_CLK/RX_CLK clock cycles */\r\n     tmpreg = (heth->Instance)->DMABMR;\r\n     HAL_Delay(ETH_REG_WRITE_DELAY);\r\n     (heth->Instance)->DMABMR = tmpreg;\r\n\r\n     if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)\r\n     {\r\n       /* Enable the Ethernet Rx Interrupt */\r\n       __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);\r\n     }\r\n\r\n     /* Initialize MAC address in ethernet MAC */ \r\n     ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);\r\n}\r\n\r\n/**\r\n  * @brief  Configures the selected MAC address.\r\n  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains\r\n  *         the configuration information for ETHERNET module\r\n  * @param  MacAddr: The MAC address to configure\r\n  *          This parameter can be one of the following values:\r\n  *             @arg ETH_MAC_Address0: MAC Address0 \r\n  *             @arg ETH_MAC_Address1: MAC Address1 \r\n  *             @arg ETH_MAC_Address2: MAC Address2\r\n  *             @arg ETH_MAC_Address3: MAC Address3\r\n  * @param  Addr: Pointer to MAC address buffer data (6 bytes)\r\n  * @retval HAL status\r\n  */\r\nstatic void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)\r\n{\r\n  uint32_t tmpreg;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));\r\n  \r\n  /* Calculate the selected MAC address high register */\r\n  tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];\r\n  /* Load the selected MAC address high register */\r\n  (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg;\r\n  /* Calculate the selected MAC address low register */\r\n  tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];\r\n  \r\n  /* Load the selected MAC address low register */\r\n  (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg;\r\n}\r\n\r\n/**\r\n  * @brief  Enables the MAC transmission.\r\n  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains\r\n  *         the configuration information for ETHERNET module  \r\n  * @retval None\r\n  */\r\nstatic void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)\r\n{ \r\n  __IO uint32_t tmpreg = 0;\r\n  \r\n  /* Enable the MAC transmission */\r\n  (heth->Instance)->MACCR |= ETH_MACCR_TE;\r\n  \r\n  /* Wait until the write operation will be taken into account:\r\n     at least four TX_CLK/RX_CLK clock cycles */\r\n  tmpreg = (heth->Instance)->MACCR;\r\n  HAL_Delay(ETH_REG_WRITE_DELAY);\r\n  (heth->Instance)->MACCR = tmpreg;\r\n}\r\n\r\n/**\r\n  * @brief  Disables the MAC transmission.\r\n  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains\r\n  *         the configuration information for ETHERNET module  \r\n  * @retval None\r\n  */\r\nstatic void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)\r\n{ \r\n  __IO uint32_t tmpreg = 0;\r\n  \r\n  /* Disable the MAC transmission */\r\n  (heth->Instance)->MACCR &= ~ETH_MACCR_TE;\r\n  \r\n  /* Wait until the write operation will be taken into account:\r\n     at least four TX_CLK/RX_CLK clock cycles */\r\n  tmpreg = (heth->Instance)->MACCR;\r\n  HAL_Delay(ETH_REG_WRITE_DELAY);\r\n  (heth->Instance)->MACCR = tmpreg;\r\n}\r\n\r\n/**\r\n  * @brief  Enables the MAC reception.\r\n  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains\r\n  *         the configuration information for ETHERNET module   \r\n  * @retval None\r\n  */\r\nstatic void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)\r\n{ \r\n  __IO uint32_t tmpreg = 0;\r\n  \r\n  /* Enable the MAC reception */\r\n  (heth->Instance)->MACCR |= ETH_MACCR_RE;\r\n  \r\n  /* Wait until the write operation will be taken into account:\r\n     at least four TX_CLK/RX_CLK clock cycles */\r\n  tmpreg = (heth->Instance)->MACCR;\r\n  HAL_Delay(ETH_REG_WRITE_DELAY);\r\n  (heth->Instance)->MACCR = tmpreg;\r\n}\r\n\r\n/**\r\n  * @brief  Disables the MAC reception.\r\n  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains\r\n  *         the configuration information for ETHERNET module   \r\n  * @retval None\r\n  */\r\nstatic void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)\r\n{ \r\n  __IO uint32_t tmpreg = 0;\r\n  \r\n  /* Disable the MAC reception */\r\n  (heth->Instance)->MACCR &= ~ETH_MACCR_RE; \r\n  \r\n  /* Wait until the write operation will be taken into account:\r\n     at least four TX_CLK/RX_CLK clock cycles */\r\n  tmpreg = (heth->Instance)->MACCR;\r\n  HAL_Delay(ETH_REG_WRITE_DELAY);\r\n  (heth->Instance)->MACCR = tmpreg;\r\n}\r\n\r\n/**\r\n  * @brief  Enables the DMA transmission.\r\n  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains\r\n  *         the configuration information for ETHERNET module   \r\n  * @retval None\r\n  */\r\nstatic void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)\r\n{\r\n  /* Enable the DMA transmission */\r\n  (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;  \r\n}\r\n\r\n/**\r\n  * @brief  Disables the DMA transmission.\r\n  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains\r\n  *         the configuration information for ETHERNET module   \r\n  * @retval None\r\n  */\r\nstatic void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)\r\n{ \r\n  /* Disable the DMA transmission */\r\n  (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;\r\n}\r\n\r\n/**\r\n  * @brief  Enables the DMA reception.\r\n  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains\r\n  *         the configuration information for ETHERNET module \r\n  * @retval None\r\n  */\r\nstatic void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)\r\n{  \r\n  /* Enable the DMA reception */\r\n  (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;  \r\n}\r\n\r\n/**\r\n  * @brief  Disables the DMA reception.\r\n  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains\r\n  *         the configuration information for ETHERNET module \r\n  * @retval None\r\n  */\r\nstatic void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)\r\n{ \r\n  /* Disable the DMA reception */\r\n  (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;\r\n}\r\n\r\n/**\r\n  * @brief  Clears the ETHERNET transmit FIFO.\r\n  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains\r\n  *         the configuration information for ETHERNET module\r\n  * @retval None\r\n  */\r\nstatic void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)\r\n{\r\n  __IO uint32_t tmpreg = 0;\r\n  \r\n  /* Set the Flush Transmit FIFO bit */\r\n  (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;\r\n  \r\n  /* Wait until the write operation will be taken into account:\r\n     at least four TX_CLK/RX_CLK clock cycles */\r\n  tmpreg = (heth->Instance)->DMAOMR;\r\n  HAL_Delay(ETH_REG_WRITE_DELAY);\r\n  (heth->Instance)->DMAOMR = tmpreg;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_ETH_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_flash.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   FLASH HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the internal FLASH memory:\r\n  *           + Program operations functions\r\n  *           + Memory Control functions \r\n  *           + Peripheral Errors functions\r\n  *         \r\n  @verbatim\r\n  ==============================================================================\r\n                        ##### FLASH peripheral features #####\r\n  ==============================================================================\r\n           \r\n  [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses \r\n       to the Flash memory. It implements the erase and program Flash memory operations \r\n       and the read and write protection mechanisms.\r\n      \r\n  [..] The Flash memory interface accelerates code execution with a system of instruction\r\n       prefetch and cache lines. \r\n\r\n  [..] The FLASH main features are:\r\n      (+) Flash memory read operations\r\n      (+) Flash memory program/erase operations\r\n      (+) Read / write protections\r\n      (+) Prefetch on I-Code\r\n      (+) 64 cache lines of 128 bits on I-Code\r\n      (+) 8 cache lines of 128 bits on D-Code\r\n      \r\n                     ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]                             \r\n      This driver provides functions and macros to configure and program the FLASH \r\n      memory of all STM32F7xx devices.\r\n    \r\n      (#) FLASH Memory IO Programming functions: \r\n           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and \r\n                HAL_FLASH_Lock() functions\r\n           (++) Program functions: byte, half word, word and double word\r\n           (++) There Two modes of programming :\r\n            (+++) Polling mode using HAL_FLASH_Program() function\r\n            (+++) Interrupt mode using HAL_FLASH_Program_IT() function\r\n    \r\n      (#) Interrupts and flags management functions : \r\n           (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()\r\n           (++) Wait for last FLASH operation according to its status\r\n           (++) Get error flag status by calling HAL_SetErrorCode()          \r\n    [..] \r\n      In addition to these functions, this driver includes a set of macros allowing\r\n      to handle the following operations:\r\n       (+) Set the latency\r\n       (+) Enable/Disable the prefetch buffer\r\n       (+) Enable/Disable the Instruction cache and the Data cache\r\n       (+) Reset the Instruction cache and the Data cache\r\n       (+) Enable/Disable the FLASH interrupts\r\n       (+) Monitor the FLASH flags status\r\n    [..]\t   \r\n\t(@) For any Flash memory program operation (erase or program), the CPU clock frequency\r\n        (HCLK) must be at least 1MHz. \r\n\t(@) The contents of the Flash memory are not guaranteed if a device reset occurs during \r\n\t    a Flash memory operation.\r\n    (@) Any attempt to read the Flash memory while it is being written or erased, causes the \r\n\t    bus to stall. Read operations are processed correctly once the program operation has \r\n\t\tcompleted. This means that code or data fetches cannot be performed while a write/erase \r\n\t\toperation is ongoing.\r\n          \r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup FLASH FLASH\r\n  * @brief FLASH HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_FLASH_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @addtogroup FLASH_Private_Constants\r\n  * @{\r\n  */\r\n#define SECTOR_MASK               ((uint32_t)0xFFFFFF07U)\r\n#define FLASH_TIMEOUT_VALUE       ((uint32_t)50000U)/* 50 s */\r\n/**\r\n  * @}\r\n  */         \r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @addtogroup FLASH_Private_Variables\r\n  * @{\r\n  */\r\n/* Variable used for Erase sectors under interruption */\r\nFLASH_ProcessTypeDef pFlash;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private function prototypes -----------------------------------------------*/\r\n/** @addtogroup FLASH_Private_Functions\r\n  * @{\r\n  */\r\n/* Program operations */\r\nstatic void   FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);\r\nstatic void   FLASH_Program_Word(uint32_t Address, uint32_t Data);\r\nstatic void   FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);\r\nstatic void   FLASH_Program_Byte(uint32_t Address, uint8_t Data);\r\nstatic void   FLASH_SetErrorCode(void);\r\n\r\nHAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup FLASH_Exported_Functions FLASH Exported Functions\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions \r\n *  @brief   Programming operation functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                  ##### Programming operation functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides a set of functions allowing to manage the FLASH \r\n    program operations.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Program byte, halfword, word or double word at a specified address\r\n  * @param  TypeProgram:  Indicate the way to program at a specified address.\r\n  *                           This parameter can be a value of @ref FLASH_Type_Program\r\n  * @param  Address:  specifies the address to be programmed.\r\n  * @param  Data: specifies the data to be programmed\r\n  * \r\n  * @retval HAL_StatusTypeDef HAL Status\r\n  */\r\nHAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)\r\n{\r\n  HAL_StatusTypeDef status = HAL_ERROR;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(&pFlash);\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));\r\n\r\n  /* Wait for last operation to be completed */\r\n  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r\n  \r\n  if(status == HAL_OK)\r\n  {\r\n    switch(TypeProgram)\r\n    {\r\n      case FLASH_TYPEPROGRAM_BYTE :\r\n      {\r\n        /*Program byte (8-bit) at a specified address.*/\r\n        FLASH_Program_Byte(Address, (uint8_t) Data);\r\n        break;\r\n      }\r\n      \r\n      case FLASH_TYPEPROGRAM_HALFWORD :\r\n      {\r\n        /*Program halfword (16-bit) at a specified address.*/\r\n        FLASH_Program_HalfWord(Address, (uint16_t) Data);\r\n        break;\r\n      }\r\n      \r\n      case FLASH_TYPEPROGRAM_WORD :\r\n      {\r\n        /*Program word (32-bit) at a specified address.*/\r\n        FLASH_Program_Word(Address, (uint32_t) Data);\r\n        break;\r\n      }\r\n      \r\n      case FLASH_TYPEPROGRAM_DOUBLEWORD :\r\n      {\r\n        /*Program double word (64-bit) at a specified address.*/\r\n        FLASH_Program_DoubleWord(Address, Data);\r\n        break;\r\n      }\r\n      default :\r\n        break;\r\n    }\r\n    /* Wait for last operation to be completed */\r\n    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r\n    \r\n    /* If the program operation is completed, disable the PG Bit */\r\n    FLASH->CR &= (~FLASH_CR_PG);\r\n  }\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(&pFlash);\r\n\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief   Program byte, halfword, word or double word at a specified address  with interrupt enabled.\r\n  * @param  TypeProgram:  Indicate the way to program at a specified address.\r\n  *                           This parameter can be a value of @ref FLASH_Type_Program\r\n  * @param  Address:  specifies the address to be programmed.\r\n  * @param  Data: specifies the data to be programmed\r\n  * \r\n  * @retval HAL Status\r\n  */\r\nHAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(&pFlash);\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));\r\n\r\n  /* Enable End of FLASH Operation interrupt */\r\n  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);\r\n  \r\n  /* Enable Error source interrupt */\r\n  __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);\r\n  \r\n  /* Clear pending flags (if any) */  \r\n  __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP    | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\\\r\n                         FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR);  \r\n\r\n  pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;\r\n  pFlash.Address = Address;\r\n  \r\n  switch(TypeProgram)\r\n  {\r\n    case FLASH_TYPEPROGRAM_BYTE :\r\n    {\r\n      /*Program byte (8-bit) at a specified address.*/\r\n      FLASH_Program_Byte(Address, (uint8_t) Data);\r\n      break;\r\n    }\r\n    \r\n    case FLASH_TYPEPROGRAM_HALFWORD :\r\n    {\r\n      /*Program halfword (16-bit) at a specified address.*/\r\n      FLASH_Program_HalfWord(Address, (uint16_t) Data);\r\n      break;\r\n    }\r\n    \r\n    case FLASH_TYPEPROGRAM_WORD :\r\n    {\r\n      /*Program word (32-bit) at a specified address.*/\r\n      FLASH_Program_Word(Address, (uint32_t) Data);\r\n      break;\r\n    }\r\n    \r\n    case FLASH_TYPEPROGRAM_DOUBLEWORD :\r\n    {\r\n      /*Program double word (64-bit) at a specified address.*/\r\n      FLASH_Program_DoubleWord(Address, Data);\r\n      break;\r\n    }\r\n    default :\r\n      break;\r\n  }\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief This function handles FLASH interrupt request.\r\n  * @retval None\r\n  */\r\nvoid HAL_FLASH_IRQHandler(void)\r\n{\r\n  uint32_t temp = 0;\r\n  \r\n  /* If the program operation is completed, disable the PG Bit */\r\n  FLASH->CR &= (~FLASH_CR_PG);\r\n\r\n  /* If the erase operation is completed, disable the SER Bit */\r\n  FLASH->CR &= (~FLASH_CR_SER);\r\n  FLASH->CR &= SECTOR_MASK; \r\n\r\n  /* if the erase operation is completed, disable the MER Bit */\r\n  FLASH->CR &= (~FLASH_MER_BIT);\r\n\r\n  /* Check FLASH End of Operation flag  */\r\n  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)\r\n  {\r\n    switch (pFlash.ProcedureOnGoing)\r\n    {\r\n      case FLASH_PROC_SECTERASE :\r\n      {\r\n        /* Nb of sector to erased can be decreased */\r\n        pFlash.NbSectorsToErase--;\r\n\r\n        /* Check if there are still sectors to erase */\r\n        if(pFlash.NbSectorsToErase != 0)\r\n        {\r\n          temp = pFlash.Sector;\r\n          /* Indicate user which sector has been erased */\r\n          HAL_FLASH_EndOfOperationCallback(temp);\r\n\r\n          /* Clear pending flags (if any) */  \r\n          __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);  \r\n\r\n          /* Increment sector number */\r\n          temp = ++pFlash.Sector;\r\n          FLASH_Erase_Sector(temp, pFlash.VoltageForErase);\r\n        }\r\n        else\r\n        {\r\n          /* No more sectors to Erase, user callback can be called.*/\r\n          /* Reset Sector and stop Erase sectors procedure */\r\n          pFlash.Sector = temp = 0xFFFFFFFFU;\r\n          /* FLASH EOP interrupt user callback */\r\n          HAL_FLASH_EndOfOperationCallback(temp);\r\n          /* Sector Erase procedure is completed */\r\n          pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r\n          /* Clear FLASH End of Operation pending bit */\r\n          __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);\r\n        }\r\n        break;\r\n      }\r\n    \r\n      case FLASH_PROC_MASSERASE :\r\n      {\r\n        /* MassErase ended. Return the selected bank : in this product we don't have Banks */\r\n        /* FLASH EOP interrupt user callback */\r\n        HAL_FLASH_EndOfOperationCallback(0);\r\n        /* MAss Erase procedure is completed */\r\n        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r\n        /* Clear FLASH End of Operation pending bit */\r\n        __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);\r\n        break;\r\n      }\r\n\r\n      case FLASH_PROC_PROGRAM :\r\n      {\r\n        /*Program ended. Return the selected address*/\r\n        /* FLASH EOP interrupt user callback */\r\n        HAL_FLASH_EndOfOperationCallback(pFlash.Address);\r\n        /* Programming procedure is completed */\r\n        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r\n        /* Clear FLASH End of Operation pending bit */\r\n        __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);\r\n        break;\r\n      }\r\n      default :\r\n        break;\r\n    }\r\n  }\r\n  \r\n  /* Check FLASH operation error flags */\r\n  if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR  | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR )) != RESET)\r\n  {\r\n    switch (pFlash.ProcedureOnGoing)\r\n    {\r\n      case FLASH_PROC_SECTERASE :\r\n      {\r\n        /* return the faulty sector */\r\n        temp = pFlash.Sector;\r\n        pFlash.Sector = 0xFFFFFFFFU;\r\n        break;\r\n      }\r\n      case FLASH_PROC_MASSERASE :\r\n      {\r\n        /* No return in case of Mass Erase */\r\n        temp = 0;\r\n        break;\r\n      }\r\n      case FLASH_PROC_PROGRAM :\r\n      {\r\n        /*return the faulty address*/\r\n        temp = pFlash.Address;\r\n        break;\r\n      }\r\n    default :\r\n      break;\r\n    }\r\n    /*Save the Error code*/\r\n    FLASH_SetErrorCode();\r\n\r\n    /* FLASH error interrupt user callback */\r\n    HAL_FLASH_OperationErrorCallback(temp);\r\n    /* Clear FLASH error pending bits */\r\n    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPERR  | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR );\r\n\r\n    /*Stop the procedure ongoing */\r\n    pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\r\n  }\r\n  \r\n  if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)\r\n  {\r\n    /* Disable End of FLASH Operation interrupt */\r\n    __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP);\r\n\r\n    /* Disable Error source interrupt */\r\n    __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR);\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(&pFlash);\r\n  }\r\n  \r\n}\r\n\r\n/**\r\n  * @brief  FLASH end of operation interrupt callback\r\n  * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure\r\n  *                 - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that \r\n  *                                  all the selected sectors have been erased)\r\n  *                 - Program      : Address which was selected for data program\r\n  *                 - Mass Erase   : No return value expected\r\n  * @retval None\r\n  */\r\n__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(ReturnValue);\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n  the HAL_FLASH_EndOfOperationCallback could be implemented in the user file\r\n  */ \r\n}\r\n\r\n/**\r\n  * @brief  FLASH operation error interrupt callback\r\n  * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure\r\n  *                 - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that \r\n  *                                  all the selected sectors have been erased)\r\n  *                 - Program      : Address which was selected for data program\r\n  *                 - Mass Erase   : No return value expected\r\n  * @retval None\r\n  */\r\n__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(ReturnValue);\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n  the HAL_FLASH_OperationErrorCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions \r\n *  @brief   management functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                      ##### Peripheral Control functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides a set of functions allowing to control the FLASH \r\n    memory operations.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Unlock the FLASH control register access\r\n  * @retval HAL Status\r\n  */\r\nHAL_StatusTypeDef HAL_FLASH_Unlock(void)\r\n{\r\n  if((FLASH->CR & FLASH_CR_LOCK) != RESET)\r\n  {\r\n    /* Authorize the FLASH Registers access */\r\n    FLASH->KEYR = FLASH_KEY1;\r\n    FLASH->KEYR = FLASH_KEY2;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  return HAL_OK; \r\n}\r\n\r\n/**\r\n  * @brief  Locks the FLASH control register access\r\n  * @retval HAL Status\r\n  */\r\nHAL_StatusTypeDef HAL_FLASH_Lock(void)\r\n{\r\n  /* Set the LOCK Bit to lock the FLASH Registers access */\r\n  FLASH->CR |= FLASH_CR_LOCK;\r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Unlock the FLASH Option Control Registers access.\r\n  * @retval HAL Status\r\n  */\r\nHAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)\r\n{\r\n  if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)\r\n  {\r\n    /* Authorizes the Option Byte register programming */\r\n    FLASH->OPTKEYR = FLASH_OPT_KEY1;\r\n    FLASH->OPTKEYR = FLASH_OPT_KEY2;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;\r\n  }  \r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Lock the FLASH Option Control Registers access.\r\n  * @retval HAL Status \r\n  */\r\nHAL_StatusTypeDef HAL_FLASH_OB_Lock(void)\r\n{\r\n  /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */\r\n  FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;\r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Launch the option byte loading.\r\n  * @retval HAL Status\r\n  */\r\nHAL_StatusTypeDef HAL_FLASH_OB_Launch(void)\r\n{\r\n  /* Set the OPTSTRT bit in OPTCR register */\r\n  FLASH->OPTCR |= FLASH_OPTCR_OPTSTRT;\r\n\r\n  /* Wait for last operation to be completed */\r\n  return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions \r\n *  @brief   Peripheral Errors functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                ##### Peripheral Errors functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection permits to get in run-time Errors of the FLASH peripheral.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Get the specific FLASH error flag.\r\n  * @retval FLASH_ErrorCode: The returned value can be:\r\n  *            @arg FLASH_ERROR_ERS: FLASH Erasing Sequence error flag \r\n  *            @arg FLASH_ERROR_PGP: FLASH Programming Parallelism error flag  \r\n  *            @arg FLASH_ERROR_PGA: FLASH Programming Alignment error flag\r\n  *            @arg FLASH_ERROR_WRP: FLASH Write protected error flag\r\n  *            @arg FLASH_ERROR_OPERATION: FLASH operation Error flag \r\n  */\r\nuint32_t HAL_FLASH_GetError(void)\r\n{ \r\n   return pFlash.ErrorCode;\r\n}  \r\n  \r\n/**\r\n  * @}\r\n  */    \r\n\r\n/**\r\n  * @brief  Wait for a FLASH operation to complete.\r\n  * @param  Timeout: maximum flash operationtimeout\r\n  * @retval HAL Status\r\n  */\r\nHAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)\r\n{ \r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Clear Error Code */\r\n  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\r\n  \r\n  /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.\r\n     Even if the FLASH operation fails, the BUSY flag will be reset and an error\r\n     flag will be set */\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET) \r\n  { \r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n    } \r\n  }\r\n  \r\n  if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \\\r\n                           FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR )) != RESET)\r\n  {\r\n    /*Save the error code*/\r\n    FLASH_SetErrorCode();\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* If there is an error flag set */\r\n  return HAL_OK;\r\n  \r\n}  \r\n\r\n/**\r\n  * @brief  Program a double word (64-bit) at a specified address.\r\n  * @note   This function must be used when the device voltage range is from\r\n  *         2.7V to 3.6V and an External Vpp is present.\r\n  *\r\n  * @note   If an erase and a program operations are requested simultaneously,    \r\n  *         the erase operation is performed before the program one.\r\n  *  \r\n  * @param  Address: specifies the address to be programmed.\r\n  * @param  Data: specifies the data to be programmed.\r\n  * @retval None\r\n  */\r\nstatic void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_FLASH_ADDRESS(Address));\r\n  \r\n  /* If the previous operation is completed, proceed to program the new data */\r\n  FLASH->CR &= CR_PSIZE_MASK;\r\n  FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;\r\n  FLASH->CR |= FLASH_CR_PG;\r\n  \r\n  *(__IO uint64_t*)Address = Data;\r\n  \r\n  /* Data synchronous Barrier (DSB) Just after the write operation\r\n     This will force the CPU to respect the sequence of instruction (no optimization).*/\r\n  __DSB();\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Program word (32-bit) at a specified address.\r\n  * @note   This function must be used when the device voltage range is from\r\n  *         2.7V to 3.6V.\r\n  *\r\n  * @note   If an erase and a program operations are requested simultaneously,    \r\n  *         the erase operation is performed before the program one.\r\n  *  \r\n  * @param  Address: specifies the address to be programmed.\r\n  * @param  Data: specifies the data to be programmed.\r\n  * @retval None\r\n  */\r\nstatic void FLASH_Program_Word(uint32_t Address, uint32_t Data)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_FLASH_ADDRESS(Address));\r\n  \r\n  /* If the previous operation is completed, proceed to program the new data */\r\n  FLASH->CR &= CR_PSIZE_MASK;\r\n  FLASH->CR |= FLASH_PSIZE_WORD;\r\n  FLASH->CR |= FLASH_CR_PG;\r\n\r\n  *(__IO uint32_t*)Address = Data;\r\n  \r\n  /* Data synchronous Barrier (DSB) Just after the write operation\r\n     This will force the CPU to respect the sequence of instruction (no optimization).*/\r\n  __DSB();\r\n}\r\n\r\n/**\r\n  * @brief  Program a half-word (16-bit) at a specified address.\r\n  * @note   This function must be used when the device voltage range is from\r\n  *         2.7V to 3.6V.\r\n  *\r\n  * @note   If an erase and a program operations are requested simultaneously,    \r\n  *         the erase operation is performed before the program one.\r\n  *  \r\n  * @param  Address: specifies the address to be programmed.\r\n  * @param  Data: specifies the data to be programmed.\r\n  * @retval None\r\n  */\r\nstatic void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_FLASH_ADDRESS(Address));\r\n  \r\n  /* If the previous operation is completed, proceed to program the new data */\r\n  FLASH->CR &= CR_PSIZE_MASK;\r\n  FLASH->CR |= FLASH_PSIZE_HALF_WORD;\r\n  FLASH->CR |= FLASH_CR_PG;\r\n\r\n  *(__IO uint16_t*)Address = Data;\r\n\r\n  /* Data synchronous Barrier (DSB) Just after the write operation\r\n     This will force the CPU to respect the sequence of instruction (no optimization).*/\r\n  __DSB();\r\n  \r\n}\r\n\r\n/**\r\n  * @brief  Program byte (8-bit) at a specified address.\r\n  * @note   This function must be used when the device voltage range is from\r\n  *         2.7V to 3.6V.\r\n  *\r\n  * @note   If an erase and a program operations are requested simultaneously,    \r\n  *         the erase operation is performed before the program one.\r\n  *  \r\n  * @param  Address: specifies the address to be programmed.\r\n  * @param  Data: specifies the data to be programmed.\r\n  * @retval None\r\n  */\r\nstatic void FLASH_Program_Byte(uint32_t Address, uint8_t Data)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_FLASH_ADDRESS(Address));\r\n  \r\n  /* If the previous operation is completed, proceed to program the new data */\r\n  FLASH->CR &= CR_PSIZE_MASK;\r\n  FLASH->CR |= FLASH_PSIZE_BYTE;\r\n  FLASH->CR |= FLASH_CR_PG;\r\n\r\n  *(__IO uint8_t*)Address = Data;\r\n\r\n  /* Data synchronous Barrier (DSB) Just after the write operation\r\n     This will force the CPU to respect the sequence of instruction (no optimization).*/\r\n  __DSB();\r\n}\r\n\r\n/**\r\n  * @brief  Set the specific FLASH error flag.\r\n  * @retval None\r\n  */\r\nstatic void FLASH_SetErrorCode(void)\r\n{ \r\n  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET)\r\n  {\r\n   pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;\r\n  }\r\n  \r\n  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET)\r\n  {\r\n   pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;\r\n  }\r\n  \r\n  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET)\r\n  {\r\n    pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP;\r\n  }\r\n  \r\n  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ERSERR) != RESET)\r\n  {\r\n    pFlash.ErrorCode |= HAL_FLASH_ERROR_ERS;\r\n  }\r\n  \r\n  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET)\r\n  {\r\n    pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION;\r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_FLASH_MODULE_ENABLED */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_flash_ex.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Extended FLASH HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the FLASH extension peripheral:\r\n  *           + Extended programming operations functions\r\n  *  \r\n  @verbatim\r\n  ==============================================================================\r\n                   ##### Flash Extension features #####\r\n  ==============================================================================\r\n           \r\n  [..] Comparing to other previous devices, the FLASH interface for STM32F76xx/STM32F77xx \r\n       devices contains the following additional features \r\n       \r\n       (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write\r\n           capability (RWW)\r\n       (+) Dual bank memory organization       \r\n       (+) Dual boot mode\r\n   \r\n                      ##### How to use this driver #####\r\n  ==============================================================================\r\n  [..] This driver provides functions to configure and program the FLASH memory \r\n       of all STM32F7xx devices. It includes\r\n      (#) FLASH Memory Erase functions: \r\n           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and \r\n                HAL_FLASH_Lock() functions\r\n           (++) Erase function: Erase sector, erase all sectors\r\n           (++) There are two modes of erase :\r\n             (+++) Polling Mode using HAL_FLASHEx_Erase()\r\n             (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()\r\n             \r\n      (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to :\r\n           (++) Set/Reset the write protection\r\n           (++) Set the Read protection Level\r\n           (++) Set the BOR level\r\n           (++) Program the user Option Bytes\r\n  \r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup FLASHEx FLASHEx\r\n  * @brief FLASH HAL Extension module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_FLASH_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @addtogroup FLASHEx_Private_Constants\r\n  * @{\r\n  */    \r\n#define SECTOR_MASK               ((uint32_t)0xFFFFFF07)\r\n#define FLASH_TIMEOUT_VALUE       ((uint32_t)50000)/* 50 s */\r\n/**\r\n  * @}\r\n  */\r\n    \r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @addtogroup FLASHEx_Private_Variables\r\n  * @{\r\n  */    \r\nextern FLASH_ProcessTypeDef pFlash;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private function prototypes -----------------------------------------------*/\r\n/** @addtogroup FLASHEx_Private_Functions\r\n  * @{\r\n  */\r\n/* Option bytes control */\r\nstatic HAL_StatusTypeDef  FLASH_OB_EnableWRP(uint32_t WRPSector);\r\nstatic HAL_StatusTypeDef  FLASH_OB_DisableWRP(uint32_t WRPSector);\r\nstatic HAL_StatusTypeDef  FLASH_OB_RDP_LevelConfig(uint8_t Level);\r\nstatic HAL_StatusTypeDef  FLASH_OB_BOR_LevelConfig(uint8_t Level);\r\nstatic HAL_StatusTypeDef  FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address);\r\nstatic uint32_t           FLASH_OB_GetUser(void);\r\nstatic uint32_t           FLASH_OB_GetWRP(void);\r\nstatic uint8_t            FLASH_OB_GetRDP(void);\r\nstatic uint32_t           FLASH_OB_GetBOR(void);\r\nstatic uint32_t           FLASH_OB_GetBootAddress(uint32_t BootOption);\r\n\r\n#if defined (FLASH_OPTCR_nDBANK)\r\nstatic void               FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks);\r\nstatic HAL_StatusTypeDef  FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \\\r\n                                              uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot);\r\n#else\r\nstatic void               FLASH_MassErase(uint8_t VoltageRange);\r\nstatic HAL_StatusTypeDef  FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby);\r\n#endif /* FLASH_OPTCR_nDBANK */\r\n\r\nextern HAL_StatusTypeDef  FLASH_WaitForLastOperation(uint32_t Timeout);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions\r\n *  @brief   Extended IO operation functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                ##### Extended programming operation functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides a set of functions allowing to manage the Extension FLASH \r\n    programming operations Operations.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n/**\r\n  * @brief  Perform a mass erase or erase the specified FLASH memory sectors \r\n  * @param[in]  pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that\r\n  *         contains the configuration information for the erasing.\r\n  * \r\n  * @param[out]  SectorError: pointer to variable  that\r\n  *         contains the configuration information on faulty sector in case of error \r\n  *         (0xFFFFFFFF means that all the sectors have been correctly erased)\r\n  * \r\n  * @retval HAL Status\r\n  */\r\nHAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)\r\n{\r\n  HAL_StatusTypeDef status = HAL_ERROR;\r\n  uint32_t index = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(&pFlash);\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));\r\n\r\n  /* Wait for last operation to be completed */\r\n  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r\n\r\n  if(status == HAL_OK)\r\n  {\r\n    /*Initialization of SectorError variable*/\r\n    *SectorError = 0xFFFFFFFFU;\r\n    \r\n    if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)\r\n    {\r\n      /*Mass erase to be done*/\r\n#if defined (FLASH_OPTCR_nDBANK)      \r\n      FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);\r\n#else\r\n      FLASH_MassErase((uint8_t) pEraseInit->VoltageRange);      \r\n#endif /* FLASH_OPTCR_nDBANK */\r\n                      \r\n      /* Wait for last operation to be completed */\r\n      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r\n      \r\n      /* if the erase operation is completed, disable the MER Bit */\r\n      FLASH->CR &= (~FLASH_MER_BIT);\r\n    }\r\n    else\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));\r\n\r\n      /* Erase by sector by sector to be done*/\r\n      for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++)\r\n      {\r\n        FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange);\r\n\r\n        /* Wait for last operation to be completed */\r\n        status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r\n        \r\n        /* If the erase operation is completed, disable the SER Bit and SNB Bits */\r\n        CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB)); \r\n\r\n        if(status != HAL_OK) \r\n        {\r\n          /* In case of error, stop erase procedure and return the faulty sector*/\r\n          *SectorError = index;\r\n          break;\r\n        }\r\n      }\r\n    }\r\n  }\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(&pFlash);\r\n\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Perform a mass erase or erase the specified FLASH memory sectors  with interrupt enabled\r\n  * @param  pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that\r\n  *         contains the configuration information for the erasing.\r\n  * \r\n  * @retval HAL Status\r\n  */\r\nHAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Process Locked */\r\n  __HAL_LOCK(&pFlash);\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));\r\n\r\n  /* Enable End of FLASH Operation interrupt */\r\n  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);\r\n  \r\n  /* Enable Error source interrupt */\r\n  __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);\r\n  \r\n  /* Clear pending flags (if any) */  \r\n  __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP    | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\\\r\n                         FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR);  \r\n  \r\n  if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)\r\n  {\r\n    /*Mass erase to be done*/\r\n    pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;\r\n#if defined (FLASH_OPTCR_nDBANK)    \r\n    FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);\r\n#else\r\n    FLASH_MassErase((uint8_t) pEraseInit->VoltageRange);      \r\n#endif /* FLASH_OPTCR_nDBANK */    \r\n  }\r\n  else\r\n  {\r\n    /* Erase by sector to be done*/\r\n\r\n    /* Check the parameters */\r\n    assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));\r\n\r\n    pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE;\r\n    pFlash.NbSectorsToErase = pEraseInit->NbSectors;\r\n    pFlash.Sector = pEraseInit->Sector;\r\n    pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange;\r\n\r\n    /*Erase 1st sector and wait for IT*/\r\n    FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->VoltageRange);\r\n  }\r\n\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Program option bytes\r\n  * @param  pOBInit: pointer to an FLASH_OBInitStruct structure that\r\n  *         contains the configuration information for the programming.\r\n  * \r\n  * @retval HAL Status\r\n  */\r\nHAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)\r\n{\r\n  HAL_StatusTypeDef status = HAL_ERROR;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(&pFlash);\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_OPTIONBYTE(pOBInit->OptionType));\r\n\r\n  /* Write protection configuration */\r\n  if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)\r\n  {\r\n    assert_param(IS_WRPSTATE(pOBInit->WRPState));\r\n    if(pOBInit->WRPState == OB_WRPSTATE_ENABLE)\r\n    {\r\n      /*Enable of Write protection on the selected Sector*/\r\n      status = FLASH_OB_EnableWRP(pOBInit->WRPSector);\r\n    }\r\n    else\r\n    {\r\n      /*Disable of Write protection on the selected Sector*/\r\n      status = FLASH_OB_DisableWRP(pOBInit->WRPSector);\r\n    }\r\n  }\r\n\r\n  /* Read protection configuration */\r\n  if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)\r\n  {\r\n    status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);\r\n  }\r\n\r\n  /* USER  configuration */\r\n  if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)\r\n  {\r\n#if defined (FLASH_OPTCR_nDBANK)\r\n    status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW, \r\n                                 pOBInit->USERConfig & OB_IWDG_SW,\r\n                                 pOBInit->USERConfig & OB_STOP_NO_RST,\r\n                                 pOBInit->USERConfig & OB_STDBY_NO_RST, \r\n                                 pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE,\r\n                                 pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE,\r\n                                 pOBInit->USERConfig & OB_NDBANK_SINGLE_BANK,\r\n                                 pOBInit->USERConfig & OB_DUAL_BOOT_DISABLE);\r\n#else\r\n    status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW, \r\n                                 pOBInit->USERConfig & OB_IWDG_SW,\r\n                                 pOBInit->USERConfig & OB_STOP_NO_RST,\r\n                                 pOBInit->USERConfig & OB_STDBY_NO_RST, \r\n                                 pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE,\r\n                                 pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE);    \r\n#endif /* FLASH_OPTCR_nDBANK */\r\n  }\r\n  \r\n  /* BOR Level  configuration */\r\n  if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)\r\n  {\r\n    status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel);\r\n  }\r\n  \r\n  /* Boot 0 Address configuration */\r\n  if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_0) == OPTIONBYTE_BOOTADDR_0)\r\n  {\r\n    status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_0, pOBInit->BootAddr0);\r\n  }\r\n  \r\n  /* Boot 1 Address configuration */\r\n  if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_1) == OPTIONBYTE_BOOTADDR_1)\r\n  {\r\n    status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_1, pOBInit->BootAddr1);\r\n  }\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(&pFlash);\r\n\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Get the Option byte configuration\r\n  * @param  pOBInit: pointer to an FLASH_OBInitStruct structure that\r\n  *         contains the configuration information for the programming.\r\n  * \r\n  * @retval None\r\n  */\r\nvoid HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)\r\n{\r\n  pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\\\r\n\t                OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1;\r\n\r\n  /*Get WRP*/\r\n  pOBInit->WRPSector = FLASH_OB_GetWRP();\r\n\r\n  /*Get RDP Level*/\r\n  pOBInit->RDPLevel = FLASH_OB_GetRDP();\r\n\r\n  /*Get USER*/\r\n  pOBInit->USERConfig = FLASH_OB_GetUser();\r\n\r\n  /*Get BOR Level*/\r\n  pOBInit->BORLevel = FLASH_OB_GetBOR();\r\n  \r\n  /*Get Boot Address when Boot pin = 0 */\r\n  pOBInit->BootAddr0 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_0);\r\n  \r\n  /*Get Boot Address when Boot pin = 1 */\r\n  pOBInit->BootAddr1 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_1);\r\n}\r\n/**\r\n  * @}\r\n  */\r\n\r\n#if defined (FLASH_OPTCR_nDBANK)\r\n/**\r\n  * @brief  Full erase of FLASH memory sectors \r\n  * @param  VoltageRange: The device voltage range which defines the erase parallelism.  \r\n  *          This parameter can be one of the following values:\r\n  *            @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, \r\n  *                                  the operation will be done by byte (8-bit) \r\n  *            @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,\r\n  *                                  the operation will be done by half word (16-bit)\r\n  *            @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,\r\n  *                                  the operation will be done by word (32-bit)\r\n  *            @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, \r\n  *                                  the operation will be done by double word (64-bit)\r\n  * @param  Banks: Banks to be erased\r\n  *          This parameter can be one of the following values:\r\n  *            @arg FLASH_BANK_1: Bank1 to be erased\r\n  *            @arg FLASH_BANK_2: Bank2 to be erased\r\n  *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased\r\n  *\r\n  * @retval HAL Status\r\n  */\r\nstatic void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_VOLTAGERANGE(VoltageRange));\r\n  assert_param(IS_FLASH_BANK(Banks));\r\n\r\n  /* if the previous operation is completed, proceed to erase all sectors */\r\n  FLASH->CR &= CR_PSIZE_MASK;\r\n  if(Banks == FLASH_BANK_BOTH)\r\n  {\r\n    /* bank1 & bank2 will be erased*/\r\n    FLASH->CR |= FLASH_MER_BIT;\r\n  }\r\n  else if(Banks == FLASH_BANK_2)\r\n  {\r\n    /*Only bank2 will be erased*/\r\n    FLASH->CR |= FLASH_CR_MER2;\r\n  }\r\n  else\r\n  {\r\n    /*Only bank1 will be erased*/\r\n    FLASH->CR |= FLASH_CR_MER1;    \r\n  }\r\n  FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8);\r\n  /* Data synchronous Barrier (DSB) Just after the write operation\r\n     This will force the CPU to respect the sequence of instruction (no optimization).*/\r\n  __DSB();\r\n}\r\n\r\n/**\r\n  * @brief  Erase the specified FLASH memory sector\r\n  * @param  Sector: FLASH sector to erase\r\n  *         The value of this parameter depend on device used within the same series      \r\n  * @param  VoltageRange: The device voltage range which defines the erase parallelism.  \r\n  *          This parameter can be one of the following values:\r\n  *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, \r\n  *                                  the operation will be done by byte (8-bit) \r\n  *            @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,\r\n  *                                  the operation will be done by half word (16-bit)\r\n  *            @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,\r\n  *                                  the operation will be done by word (32-bit)\r\n  *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, \r\n  *                                  the operation will be done by double word (64-bit)\r\n  * \r\n  * @retval None\r\n  */\r\nvoid FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)\r\n{\r\n  uint32_t tmp_psize = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_FLASH_SECTOR(Sector));\r\n  assert_param(IS_VOLTAGERANGE(VoltageRange));\r\n  \r\n  if(VoltageRange == FLASH_VOLTAGE_RANGE_1)\r\n  {\r\n     tmp_psize = FLASH_PSIZE_BYTE;\r\n  }\r\n  else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)\r\n  {\r\n    tmp_psize = FLASH_PSIZE_HALF_WORD;\r\n  }\r\n  else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)\r\n  {\r\n    tmp_psize = FLASH_PSIZE_WORD;\r\n  }\r\n  else\r\n  {\r\n    tmp_psize = FLASH_PSIZE_DOUBLE_WORD;\r\n  }\r\n  \r\n  /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */\r\n  if(Sector > FLASH_SECTOR_11) \r\n  {\r\n    Sector += 4;\r\n  }  \r\n\r\n  /* If the previous operation is completed, proceed to erase the sector */\r\n  FLASH->CR &= CR_PSIZE_MASK;\r\n  FLASH->CR |= tmp_psize;\r\n  CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);\r\n  FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB));\r\n  FLASH->CR |= FLASH_CR_STRT;\r\n  \r\n  /* Data synchronous Barrier (DSB) Just after the write operation\r\n     This will force the CPU to respect the sequence of instruction (no optimization).*/\r\n  __DSB();\r\n}\r\n\r\n/**\r\n  * @brief  Return the FLASH Write Protection Option Bytes value.\r\n  * @retval uint32_t FLASH Write Protection Option Bytes value\r\n  */\r\nstatic uint32_t FLASH_OB_GetWRP(void)\r\n{\r\n  /* Return the FLASH write protection Register value */\r\n  return ((uint32_t)(FLASH->OPTCR & 0x0FFF0000));\r\n}\r\n\r\n/**\r\n  * @brief  Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.    \r\n  * @param  Wwdg: Selects the IWDG mode\r\n  *          This parameter can be one of the following values:\r\n  *            @arg OB_WWDG_SW: Software WWDG selected\r\n  *            @arg OB_WWDG_HW: Hardware WWDG selected\r\n  * @param  Iwdg: Selects the WWDG mode\r\n  *          This parameter can be one of the following values:\r\n  *            @arg OB_IWDG_SW: Software IWDG selected\r\n  *            @arg OB_IWDG_HW: Hardware IWDG selected\r\n  * @param  Stop: Reset event when entering STOP mode.\r\n  *          This parameter  can be one of the following values:\r\n  *            @arg OB_STOP_NO_RST: No reset generated when entering in STOP\r\n  *            @arg OB_STOP_RST: Reset generated when entering in STOP\r\n  * @param  Stdby: Reset event when entering Standby mode.\r\n  *          This parameter  can be one of the following values:\r\n  *            @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY\r\n  *            @arg OB_STDBY_RST: Reset generated when entering in STANDBY\r\n  * @param  Iwdgstop: Independent watchdog counter freeze in Stop mode.\r\n  *          This parameter  can be one of the following values:\r\n  *            @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP\r\n  *            @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP\r\n  * @param  Iwdgstdby: Independent watchdog counter freeze in standby mode.\r\n  *          This parameter  can be one of the following values:\r\n  *            @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY\r\n  *            @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY\r\n  * @param  NDBank: Flash Single Bank mode enabled.\r\n  *          This parameter  can be one of the following values:\r\n  *            @arg OB_NDBANK_SINGLE_BANK: enable 256 bits mode (Flash is a single bank)\r\n  *            @arg OB_NDBANK_DUAL_BANK: disable 256 bits mode (Flash is a dual bank in 128 bits mode)  \r\n  * @param  NDBoot: Flash Dual boot mode disable.\r\n  *          This parameter  can be one of the following values:\r\n  *            @arg OB_DUAL_BOOT_DISABLE: Disable Dual Boot\r\n  *            @arg OB_DUAL_BOOT_ENABLE: Enable Dual Boot\r\n\r\n  * @retval HAL Status\r\n  */\r\nstatic HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \\\r\n                                             uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot)\r\n{\r\n  uint32_t useroptionmask = 0x00;\r\n  uint32_t useroptionvalue = 0x00;\r\n\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_OB_WWDG_SOURCE(Wwdg));\r\n  assert_param(IS_OB_IWDG_SOURCE(Iwdg));\r\n  assert_param(IS_OB_STOP_SOURCE(Stop));\r\n  assert_param(IS_OB_STDBY_SOURCE(Stdby));\r\n  assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop));\r\n  assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby));\r\n  assert_param(IS_OB_NDBANK(NDBank));\r\n  assert_param(IS_OB_NDBOOT(NDBoot));\r\n  \r\n  /* Wait for last operation to be completed */\r\n  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r\n  \r\n  if(status == HAL_OK)\r\n  {\r\n    useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \\\r\n                      FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY | \\\r\n                      FLASH_OPTCR_nDBOOT | FLASH_OPTCR_nDBANK);\r\n                      \r\n    useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby | NDBoot | NDBank);\r\n        \r\n    /* Update User Option Byte */               \r\n    MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue);\r\n  }\r\n  \r\n  return status; \r\n}\r\n\r\n/**\r\n  * @brief  Return the FLASH User Option Byte value.\r\n  * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6), \r\n  *         nRST_STDBY(Bit7), nDBOOT(Bit28), nDBANK(Bit29), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31).\r\n  */\r\nstatic uint32_t FLASH_OB_GetUser(void)\r\n{\r\n  /* Return the User Option Byte */\r\n  return ((uint32_t)(FLASH->OPTCR & 0xF00000F0U));\r\n}\r\n#else\r\n\r\n/**\r\n  * @brief  Full erase of FLASH memory sectors \r\n  * @param  VoltageRange: The device voltage range which defines the erase parallelism.  \r\n  *          This parameter can be one of the following values:\r\n  *            @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, \r\n  *                                  the operation will be done by byte (8-bit) \r\n  *            @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,\r\n  *                                  the operation will be done by half word (16-bit)\r\n  *            @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,\r\n  *                                  the operation will be done by word (32-bit)\r\n  *            @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, \r\n  *                                  the operation will be done by double word (64-bit)\r\n  *\r\n  * @retval HAL Status\r\n  */\r\nstatic void FLASH_MassErase(uint8_t VoltageRange)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_VOLTAGERANGE(VoltageRange));\r\n\r\n  /* if the previous operation is completed, proceed to erase all sectors */\r\n  FLASH->CR &= CR_PSIZE_MASK;\r\n  FLASH->CR |= FLASH_CR_MER;\r\n  FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8);\r\n  /* Data synchronous Barrier (DSB) Just after the write operation\r\n     This will force the CPU to respect the sequence of instruction (no optimization).*/\r\n  __DSB();\r\n}\r\n\r\n/**\r\n  * @brief  Erase the specified FLASH memory sector\r\n  * @param  Sector: FLASH sector to erase\r\n  *         The value of this parameter depend on device used within the same series      \r\n  * @param  VoltageRange: The device voltage range which defines the erase parallelism.  \r\n  *          This parameter can be one of the following values:\r\n  *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, \r\n  *                                  the operation will be done by byte (8-bit) \r\n  *            @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,\r\n  *                                  the operation will be done by half word (16-bit)\r\n  *            @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,\r\n  *                                  the operation will be done by word (32-bit)\r\n  *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, \r\n  *                                  the operation will be done by double word (64-bit)\r\n  * \r\n  * @retval None\r\n  */\r\nvoid FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)\r\n{\r\n  uint32_t tmp_psize = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_FLASH_SECTOR(Sector));\r\n  assert_param(IS_VOLTAGERANGE(VoltageRange));\r\n  \r\n  if(VoltageRange == FLASH_VOLTAGE_RANGE_1)\r\n  {\r\n     tmp_psize = FLASH_PSIZE_BYTE;\r\n  }\r\n  else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)\r\n  {\r\n    tmp_psize = FLASH_PSIZE_HALF_WORD;\r\n  }\r\n  else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)\r\n  {\r\n    tmp_psize = FLASH_PSIZE_WORD;\r\n  }\r\n  else\r\n  {\r\n    tmp_psize = FLASH_PSIZE_DOUBLE_WORD;\r\n  }\r\n\r\n  /* If the previous operation is completed, proceed to erase the sector */\r\n  FLASH->CR &= CR_PSIZE_MASK;\r\n  FLASH->CR |= tmp_psize;\r\n  FLASH->CR &= SECTOR_MASK;\r\n  FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB));\r\n  FLASH->CR |= FLASH_CR_STRT;\r\n  \r\n  /* Data synchronous Barrier (DSB) Just after the write operation\r\n     This will force the CPU to respect the sequence of instruction (no optimization).*/\r\n  __DSB();\r\n}\r\n\r\n/**\r\n  * @brief  Return the FLASH Write Protection Option Bytes value.\r\n  * @retval uint32_t FLASH Write Protection Option Bytes value\r\n  */\r\nstatic uint32_t FLASH_OB_GetWRP(void)\r\n{\r\n  /* Return the FLASH write protection Register value */\r\n  return ((uint32_t)(FLASH->OPTCR & 0x00FF0000));\r\n}\r\n\r\n/**\r\n  * @brief  Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.    \r\n  * @param  Wwdg: Selects the IWDG mode\r\n  *          This parameter can be one of the following values:\r\n  *            @arg OB_WWDG_SW: Software WWDG selected\r\n  *            @arg OB_WWDG_HW: Hardware WWDG selected\r\n  * @param  Iwdg: Selects the WWDG mode\r\n  *          This parameter can be one of the following values:\r\n  *            @arg OB_IWDG_SW: Software IWDG selected\r\n  *            @arg OB_IWDG_HW: Hardware IWDG selected\r\n  * @param  Stop: Reset event when entering STOP mode.\r\n  *          This parameter  can be one of the following values:\r\n  *            @arg OB_STOP_NO_RST: No reset generated when entering in STOP\r\n  *            @arg OB_STOP_RST: Reset generated when entering in STOP\r\n  * @param  Stdby: Reset event when entering Standby mode.\r\n  *          This parameter  can be one of the following values:\r\n  *            @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY\r\n  *            @arg OB_STDBY_RST: Reset generated when entering in STANDBY\r\n  * @param  Iwdgstop: Independent watchdog counter freeze in Stop mode.\r\n  *          This parameter  can be one of the following values:\r\n  *            @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP\r\n  *            @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP\r\n  * @param  Iwdgstdby: Independent watchdog counter freeze in standby mode.\r\n  *          This parameter  can be one of the following values:\r\n  *            @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY\r\n  *            @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY           \r\n  * @retval HAL Status\r\n  */\r\nstatic HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby)\r\n{\r\n  uint32_t useroptionmask = 0x00;\r\n  uint32_t useroptionvalue = 0x00;\r\n\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_OB_WWDG_SOURCE(Wwdg));\r\n  assert_param(IS_OB_IWDG_SOURCE(Iwdg));\r\n  assert_param(IS_OB_STOP_SOURCE(Stop));\r\n  assert_param(IS_OB_STDBY_SOURCE(Stdby));\r\n  assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop));\r\n  assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby));\r\n\r\n  /* Wait for last operation to be completed */\r\n  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r\n  \r\n  if(status == HAL_OK)\r\n  {\r\n    useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \\\r\n                      FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY);\r\n                      \r\n    useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby);\r\n        \r\n    /* Update User Option Byte */               \r\n    MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue);\r\n  }\r\n  \r\n  return status; \r\n\r\n}\r\n\r\n/**\r\n  * @brief  Return the FLASH User Option Byte value.\r\n  * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6), \r\n  *         nRST_STDBY(Bit7), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31).\r\n  */\r\nstatic uint32_t FLASH_OB_GetUser(void)\r\n{\r\n  /* Return the User Option Byte */\r\n  return ((uint32_t)(FLASH->OPTCR & 0xC00000F0));\r\n}\r\n#endif /* FLASH_OPTCR_nDBANK */\r\n\r\n/**\r\n  * @brief  Enable the write protection of the desired bank1 or bank2 sectors\r\n  *\r\n  * @note   When the memory read protection level is selected (RDP level = 1), \r\n  *         it is not possible to program or erase the flash sector i if CortexM7  \r\n  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1    \r\n  * \r\n  * @param  WRPSector: specifies the sector(s) to be write protected.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices)\r\n  *              or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices)\r\n  *              or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices)\r\n  *            @arg OB_WRP_SECTOR_All\r\n  *\r\n  * @retval HAL FLASH State   \r\n  */\r\nstatic HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_OB_WRP_SECTOR(WRPSector));\r\n    \r\n  /* Wait for last operation to be completed */\r\n  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r\n\r\n  if(status == HAL_OK)\r\n  {\r\n    /*Write protection enabled on sectors */\r\n    FLASH->OPTCR &= (~WRPSector);  \r\n  }\r\n  \r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Disable the write protection of the desired bank1 or bank 2 sectors\r\n  *\r\n  * @note   When the memory read protection level is selected (RDP level = 1), \r\n  *         it is not possible to program or erase the flash sector i if CortexM4  \r\n  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1  \r\n  * \r\n  * @param  WRPSector: specifies the sector(s) to be write protected.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices)\r\n  *              or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices)\r\n  *              or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices)                      \r\n  *            @arg OB_WRP_Sector_All\r\n  *\r\n  *\r\n  * @retval HAL Status   \r\n  */\r\nstatic HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_OB_WRP_SECTOR(WRPSector));\r\n    \r\n  /* Wait for last operation to be completed */\r\n  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r\n\r\n  if(status == HAL_OK)\r\n  {\r\n    /* Write protection disabled on sectors */\r\n    FLASH->OPTCR |= (WRPSector); \r\n  }\r\n\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Set the read protection level.\r\n  * @param  Level: specifies the read protection level.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg OB_RDP_LEVEL_0: No protection\r\n  *            @arg OB_RDP_LEVEL_1: Read protection of the memory\r\n  *            @arg OB_RDP_LEVEL_2: Full chip protection\r\n  *   \r\n  * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0\r\n  *    \r\n  * @retval HAL Status\r\n  */\r\nstatic HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_OB_RDP_LEVEL(Level));\r\n    \r\n  /* Wait for last operation to be completed */\r\n  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r\n\r\n  if(status == HAL_OK)\r\n  { \r\n    *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = Level;\r\n  }\r\n  \r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Set the BOR Level. \r\n  * @param  Level: specifies the Option Bytes BOR Reset Level.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V\r\n  *            @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V\r\n  *            @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V\r\n  *            @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V\r\n  * @retval HAL Status\r\n  */\r\nstatic HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_OB_BOR_LEVEL(Level));\r\n\r\n  /* Set the BOR Level */\r\n  MODIFY_REG(FLASH->OPTCR, FLASH_OPTCR_BOR_LEV, Level);\r\n  \r\n  return HAL_OK;\r\n  \r\n}\r\n\r\n/**\r\n  * @brief  Configure Boot base address.\r\n  * \r\n  * @param   BootOption : specifies Boot base address depending from Boot pin = 0 or pin = 1\r\n  *          This parameter can be one of the following values:\r\n  *            @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0                 \r\n  *            @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1  \r\n  * @param   Address: specifies Boot base address\r\n  *          This parameter can be one of the following values:\r\n  *            @arg OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000)                 \r\n  *            @arg OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000) \r\n  *            @arg OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000)  \r\n  *            @arg OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000)  \r\n  *            @arg OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000)                 \r\n  *            @arg OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000)                    \r\n  *            @arg OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000)              \r\n  *    \r\n  * @retval HAL Status\r\n  */\r\nstatic HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_OB_BOOT_ADDRESS(Address));\r\n    \r\n  /* Wait for last operation to be completed */\r\n  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\r\n  \r\n  if(status == HAL_OK)\r\n  {\r\n    if(BootOption == OPTIONBYTE_BOOTADDR_0)\r\n    {\t\t\t\r\n      MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD0, Address);\r\n    }\r\n    else\r\n    {\r\n      MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD1, (Address << 16));\r\n    }\r\n  }\r\n  \r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the FLASH Read Protection level.\r\n  * @retval FlagStatus FLASH ReadOut Protection Status:\r\n  *         This parameter can be one of the following values:\r\n  *            @arg OB_RDP_LEVEL_0: No protection\r\n  *            @arg OB_RDP_LEVEL_1: Read protection of the memory\r\n  *            @arg OB_RDP_LEVEL_2: Full chip protection\r\n  */\r\nstatic uint8_t FLASH_OB_GetRDP(void)\r\n{\r\n  uint8_t readstatus = OB_RDP_LEVEL_0;\r\n  \r\n  if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_0)\r\n  {\r\n    readstatus = OB_RDP_LEVEL_0;\r\n  }\r\n  else if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_2)\r\n  {\r\n    readstatus = OB_RDP_LEVEL_2;\r\n  }\r\n  else \r\n  {\r\n    readstatus = OB_RDP_LEVEL_1;\r\n  }\r\n\r\n  return readstatus;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the FLASH BOR level.\r\n  * @retval uint32_t The FLASH BOR level:\r\n  *           - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V\r\n  *           - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V\r\n  *           - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V\r\n  *           - OB_BOR_OFF   : Supply voltage ranges from 1.62 to 2.1 V  \r\n  */\r\nstatic uint32_t FLASH_OB_GetBOR(void)\r\n{\r\n  /* Return the FLASH BOR level */\r\n  return ((uint32_t)(FLASH->OPTCR & 0x0C));\r\n}\r\n\r\n/**\r\n  * @brief  Configure Boot base address.\r\n  * \r\n  * @param   BootOption : specifies Boot base address depending from Boot pin = 0 or pin = 1\r\n  *          This parameter can be one of the following values:\r\n  *            @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0                 \r\n  *            @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1       \r\n  *    \r\n  * @retval uint32_t Boot Base Address:\r\n  *            - OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000)                 \r\n  *            - OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000) \r\n  *            - OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000)  \r\n  *            - OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000)  \r\n  *            - OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000)                 \r\n  *            - OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000)                    \r\n  *            - OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000) \r\n  */\r\nstatic uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption)\r\n{  \r\n  uint32_t Address = 0;\r\n    \r\n\t/* Return the Boot base Address */\r\n  if(BootOption == OPTIONBYTE_BOOTADDR_0)\r\n  {\t\t\t\r\n    Address = FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD0;\r\n\t}\r\n  else\r\n\t{\r\n\t\tAddress = ((FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD1) >> 16);\r\n\t}\r\n\r\n  return Address;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n#endif /* HAL_FLASH_MODULE_ENABLED */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_gpio.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   GPIO HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the General Purpose Input/Output (GPIO) peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + IO operation functions\r\n  *\r\n  @verbatim\r\n  ==============================================================================\r\n                    ##### GPIO Peripheral features #####\r\n  ==============================================================================\r\n  [..] \r\n  Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each\r\n  port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software\r\n  in several modes:\r\n  (+) Input mode \r\n  (+) Analog mode\r\n  (+) Output mode\r\n  (+) Alternate function mode\r\n  (+) External interrupt/event lines\r\n\r\n  [..]  \r\n  During and just after reset, the alternate functions and external interrupt  \r\n  lines are not active and the I/O ports are configured in input floating mode.\r\n  \r\n  [..]   \r\n  All GPIO pins have weak internal pull-up and pull-down resistors, which can be \r\n  activated or not.\r\n\r\n  [..]\r\n  In Output or Alternate mode, each IO can be configured on open-drain or push-pull\r\n  type and the IO speed can be selected depending on the VDD value.\r\n\r\n  [..]  \r\n  All ports have external interrupt/event capability. To use external interrupt \r\n  lines, the port must be configured in input mode. All available GPIO pins are \r\n  connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.\r\n  \r\n  [..]\r\n  The external interrupt/event controller consists of up to 23 edge detectors \r\n  (16 lines are connected to GPIO) for generating event/interrupt requests (each \r\n  input line can be independently configured to select the type (interrupt or event) \r\n  and the corresponding trigger event (rising or falling or both). Each line can \r\n  also be masked independently. \r\n\r\n                     ##### How to use this driver #####\r\n  ==============================================================================  \r\n  [..]\r\n    (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). \r\n\r\n    (#) Configure the GPIO pin(s) using HAL_GPIO_Init().\r\n        (++) Configure the IO mode using \"Mode\" member from GPIO_InitTypeDef structure\r\n        (++) Activate Pull-up, Pull-down resistor using \"Pull\" member from GPIO_InitTypeDef \r\n             structure.\r\n        (++) In case of Output or alternate function mode selection: the speed is \r\n             configured through \"Speed\" member from GPIO_InitTypeDef structure.\r\n        (++) In alternate mode is selection, the alternate function connected to the IO\r\n             is configured through \"Alternate\" member from GPIO_InitTypeDef structure.\r\n        (++) Analog mode is required when a pin is to be used as ADC channel \r\n             or DAC output.\r\n        (++) In case of external interrupt/event selection the \"Mode\" member from \r\n             GPIO_InitTypeDef structure select the type (interrupt or event) and \r\n             the corresponding trigger event (rising or falling or both).\r\n\r\n    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority \r\n        mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using\r\n        HAL_NVIC_EnableIRQ().\r\n         \r\n    (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().\r\n            \r\n    (#) To set/reset the level of a pin configured in output mode use \r\n        HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().\r\n    \r\n    (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().\r\n\r\n                 \r\n    (#) During and just after reset, the alternate functions are not \r\n        active and the GPIO pins are configured in input floating mode (except JTAG\r\n        pins).\r\n  \r\n    (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose \r\n        (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has \r\n        priority over the GPIO function.\r\n  \r\n    (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as \r\n        general purpose PH0 and PH1, respectively, when the HSE oscillator is off. \r\n        The HSE has priority over the GPIO function.\r\n  \r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup GPIO GPIO\r\n  * @brief GPIO HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_GPIO_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @addtogroup GPIO_Private_Constants GPIO Private Constants\r\n  * @{\r\n  */\r\n#define GPIO_MODE             ((uint32_t)0x00000003U)\r\n#define EXTI_MODE             ((uint32_t)0x10000000U)\r\n#define GPIO_MODE_IT          ((uint32_t)0x00010000U)\r\n#define GPIO_MODE_EVT         ((uint32_t)0x00020000U)\r\n#define RISING_EDGE           ((uint32_t)0x00100000U)\r\n#define FALLING_EDGE          ((uint32_t)0x00200000U)\r\n#define GPIO_OUTPUT_TYPE      ((uint32_t)0x00000010U)\r\n\r\n#define GPIO_NUMBER           ((uint32_t)16U)\r\n/**\r\n  * @}\r\n  */\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup GPIO_Exported_Functions GPIO Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions\r\n *  @brief    Initialization and Configuration functions\r\n *\r\n@verbatim\r\n ===============================================================================\r\n              ##### Initialization and de-initialization functions #####\r\n ===============================================================================\r\n  [..]\r\n    This section provides functions allowing to initialize and de-initialize the GPIOs\r\n    to be ready for use.\r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.\r\n  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.\r\n  * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains\r\n  *         the configuration information for the specified GPIO peripheral.\r\n  * @retval None\r\n  */\r\nvoid HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)\r\n{\r\n  uint32_t position = 0x00;\r\n  uint32_t ioposition = 0x00;\r\n  uint32_t iocurrent = 0x00;\r\n  uint32_t temp = 0x00;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));\r\n  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));\r\n  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));\r\n  assert_param(IS_GPIO_PULL(GPIO_Init->Pull));\r\n\r\n  /* Configure the port pins */\r\n  for(position = 0; position < GPIO_NUMBER; position++)\r\n  {\r\n    /* Get the IO position */\r\n    ioposition = ((uint32_t)0x01) << position;\r\n    /* Get the current IO position */\r\n    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;\r\n\r\n    if(iocurrent == ioposition)\r\n    {\r\n      /*--------------------- GPIO Mode Configuration ------------------------*/\r\n      /* In case of Alternate function mode selection */\r\n      if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))\r\n      {\r\n        /* Check the Alternate function parameter */\r\n        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));\r\n        \r\n        /* Configure Alternate function mapped with the current IO */\r\n        temp = GPIOx->AFR[position >> 3];\r\n        temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;\r\n        temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));\r\n        GPIOx->AFR[position >> 3] = temp;\r\n      }\r\n\r\n      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */\r\n      temp = GPIOx->MODER;\r\n      temp &= ~(GPIO_MODER_MODER0 << (position * 2));\r\n      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));\r\n      GPIOx->MODER = temp;\r\n\r\n      /* In case of Output or Alternate function mode selection */\r\n      if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||\r\n         (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))\r\n      {\r\n        /* Check the Speed parameter */\r\n        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));\r\n        /* Configure the IO Speed */\r\n        temp = GPIOx->OSPEEDR; \r\n        temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));\r\n        temp |= (GPIO_Init->Speed << (position * 2));\r\n        GPIOx->OSPEEDR = temp;\r\n\r\n        /* Configure the IO Output Type */\r\n        temp = GPIOx->OTYPER;\r\n        temp &= ~(GPIO_OTYPER_OT_0 << position) ;\r\n        temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);\r\n        GPIOx->OTYPER = temp;\r\n      }\r\n\r\n      /* Activate the Pull-up or Pull down resistor for the current IO */\r\n      temp = GPIOx->PUPDR;\r\n      temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));\r\n      temp |= ((GPIO_Init->Pull) << (position * 2));\r\n      GPIOx->PUPDR = temp;\r\n\r\n      /*--------------------- EXTI Mode Configuration ------------------------*/\r\n      /* Configure the External Interrupt or event for the current IO */\r\n      if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)\r\n      {\r\n        /* Enable SYSCFG Clock */\r\n        __HAL_RCC_SYSCFG_CLK_ENABLE();\r\n\r\n        temp = SYSCFG->EXTICR[position >> 2];\r\n        temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));\r\n        temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));\r\n        SYSCFG->EXTICR[position >> 2] = temp;\r\n\r\n        /* Clear EXTI line configuration */\r\n        temp = EXTI->IMR;\r\n        temp &= ~((uint32_t)iocurrent);\r\n        if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)\r\n        {\r\n          temp |= iocurrent;\r\n        }\r\n        EXTI->IMR = temp;\r\n\r\n        temp = EXTI->EMR;\r\n        temp &= ~((uint32_t)iocurrent);\r\n        if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)\r\n        {\r\n          temp |= iocurrent;\r\n        }\r\n        EXTI->EMR = temp;\r\n\r\n        /* Clear Rising Falling edge configuration */\r\n        temp = EXTI->RTSR;\r\n        temp &= ~((uint32_t)iocurrent);\r\n        if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)\r\n        {\r\n          temp |= iocurrent;\r\n        }\r\n        EXTI->RTSR = temp;\r\n\r\n        temp = EXTI->FTSR;\r\n        temp &= ~((uint32_t)iocurrent);\r\n        if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)\r\n        {\r\n          temp |= iocurrent;\r\n        }\r\n        EXTI->FTSR = temp;\r\n      }\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  De-initializes the GPIOx peripheral registers to their default reset values.\r\n  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.\r\n  * @param  GPIO_Pin: specifies the port bit to be written.\r\n  *          This parameter can be one of GPIO_PIN_x where x can be (0..15).\r\n  * @retval None\r\n  */\r\nvoid HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)\r\n{\r\n  uint32_t position;\r\n  uint32_t ioposition = 0x00;\r\n  uint32_t iocurrent = 0x00;\r\n  uint32_t tmp = 0x00;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));\r\n  \r\n  /* Configure the port pins */\r\n  for(position = 0; position < GPIO_NUMBER; position++)\r\n  {\r\n    /* Get the IO position */\r\n    ioposition = ((uint32_t)0x01) << position;\r\n    /* Get the current IO position */\r\n    iocurrent = (GPIO_Pin) & ioposition;\r\n\r\n    if(iocurrent == ioposition)\r\n    {\r\n      /*------------------------- GPIO Mode Configuration --------------------*/\r\n      /* Configure IO Direction in Input Floating Mode */\r\n      GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2));\r\n\r\n      /* Configure the default Alternate Function in current IO */\r\n      GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;\r\n\r\n      /* Configure the default value for IO Speed */\r\n      GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));\r\n\r\n      /* Configure the default value IO Output Type */\r\n      GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT_0 << position) ;\r\n\r\n      /* Deactivate the Pull-up and Pull-down resistor for the current IO */\r\n      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));\r\n\r\n      /*------------------------- EXTI Mode Configuration --------------------*/\r\n      tmp = SYSCFG->EXTICR[position >> 2];\r\n      tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));\r\n      if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))))\r\n      {\r\n        /* Configure the External Interrupt or event for the current IO */\r\n        tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));\r\n        SYSCFG->EXTICR[position >> 2] &= ~tmp;\r\n\r\n        /* Clear EXTI line configuration */\r\n        EXTI->IMR &= ~((uint32_t)iocurrent);\r\n        EXTI->EMR &= ~((uint32_t)iocurrent);\r\n\r\n        /* Clear Rising Falling edge configuration */\r\n        EXTI->RTSR &= ~((uint32_t)iocurrent);\r\n        EXTI->FTSR &= ~((uint32_t)iocurrent);\r\n\t  }\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions \r\n *  @brief   GPIO Read and Write\r\n *\r\n@verbatim\r\n ===============================================================================\r\n                       ##### IO operation functions #####\r\n ===============================================================================\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Reads the specified input port pin.\r\n  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.\r\n  * @param  GPIO_Pin: specifies the port bit to read.\r\n  *         This parameter can be GPIO_PIN_x where x can be (0..15).\r\n  * @retval The input port pin value.\r\n  */\r\nGPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r\n{\r\n  GPIO_PinState bitstatus;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_GPIO_PIN(GPIO_Pin));\r\n\r\n  if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)\r\n  {\r\n    bitstatus = GPIO_PIN_SET;\r\n  }\r\n  else\r\n  {\r\n    bitstatus = GPIO_PIN_RESET;\r\n  }\r\n  return bitstatus;\r\n}\r\n\r\n/**\r\n  * @brief  Sets or clears the selected data port bit.\r\n  *\r\n  * @note   This function uses GPIOx_BSRR register to allow atomic read/modify\r\n  *         accesses. In this way, there is no risk of an IRQ occurring between\r\n  *         the read and the modify access.\r\n  *\r\n  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.\r\n  * @param  GPIO_Pin: specifies the port bit to be written.\r\n  *          This parameter can be one of GPIO_PIN_x where x can be (0..15).\r\n  * @param  PinState: specifies the value to be written to the selected bit.\r\n  *          This parameter can be one of the GPIO_PinState enum values:\r\n  *            @arg GPIO_PIN_RESET: to clear the port pin\r\n  *            @arg GPIO_PIN_SET: to set the port pin\r\n  * @retval None\r\n  */\r\nvoid HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_GPIO_PIN(GPIO_Pin));\r\n  assert_param(IS_GPIO_PIN_ACTION(PinState));\r\n\r\n  if(PinState != GPIO_PIN_RESET)\r\n  {\r\n    GPIOx->BSRR = GPIO_Pin;\r\n  }\r\n  else\r\n  {\r\n    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Toggles the specified GPIO pins.\r\n  * @param  GPIOx: Where x can be (A..I) to select the GPIO peripheral.\r\n  * @param  GPIO_Pin: Specifies the pins to be toggled.\r\n  * @retval None\r\n  */\r\nvoid HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_GPIO_PIN(GPIO_Pin));\r\n\r\n  GPIOx->ODR ^= GPIO_Pin;\r\n}\r\n\r\n/**\r\n  * @brief  Locks GPIO Pins configuration registers.\r\n  * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,\r\n  *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.\r\n  * @note   The configuration of the locked GPIO pins can no longer be modified\r\n  *         until the next reset.\r\n  * @param  GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F7 family\r\n  * @param  GPIO_Pin: specifies the port bit to be locked.\r\n  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).\r\n  * @retval None\r\n  */\r\nHAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r\n{\r\n  __IO uint32_t tmp = GPIO_LCKR_LCKK;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_GPIO_PIN(GPIO_Pin));\r\n\r\n  /* Apply lock key write sequence */\r\n  tmp |= GPIO_Pin;\r\n  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */\r\n  GPIOx->LCKR = tmp;\r\n  /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */\r\n  GPIOx->LCKR = GPIO_Pin;\r\n  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */\r\n  GPIOx->LCKR = tmp;\r\n  /* Read LCKK bit*/\r\n  tmp = GPIOx->LCKR;\r\n\r\n if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)\r\n  {\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  This function handles EXTI interrupt request.\r\n  * @param  GPIO_Pin: Specifies the pins connected EXTI line\r\n  * @retval None\r\n  */\r\nvoid HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)\r\n{\r\n  /* EXTI line interrupt detected */\r\n  if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)\r\n  {\r\n    __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);\r\n    HAL_GPIO_EXTI_Callback(GPIO_Pin);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  EXTI line detection callbacks.\r\n  * @param  GPIO_Pin: Specifies the pins connected EXTI line\r\n  * @retval None\r\n  */\r\n__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(GPIO_Pin);\r\n  \r\n  /* NOTE: This function Should not be modified, when the callback is needed,\r\n           the HAL_GPIO_EXTI_Callback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_GPIO_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_hash.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   HASH HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the HASH peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + HASH/HMAC Processing functions by algorithm using polling mode\r\n  *           + HASH/HMAC functions by algorithm using interrupt mode\r\n  *           + HASH/HMAC functions by algorithm using DMA mode\r\n  *           + Peripheral State functions\r\n  *         \r\n  @verbatim\r\n  ==============================================================================\r\n                     ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]\r\n    The HASH HAL driver can be used as follows:\r\n    (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():\r\n        (##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE()\r\n        (##) In case of using processing APIs based on interrupts (e.g. HAL_HMAC_SHA1_Start_IT())\r\n            (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()\r\n            (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()\r\n            (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler()\r\n        (##) In case of using DMA to control data transfer (e.g. HAL_HMAC_SHA1_Start_DMA())\r\n            (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()\r\n            (+++) Configure and enable one DMA stream one for managing data transfer from\r\n                memory to peripheral (input stream). Managing data transfer from\r\n                peripheral to memory can be performed only using CPU\r\n            (+++) Associate the initialized DMA handle to the HASH DMA handle\r\n                using  __HAL_LINKDMA()\r\n            (+++) Configure the priority and enable the NVIC for the transfer complete\r\n                interrupt on the DMA Stream using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()\r\n    (#)Initialize the HASH HAL using HAL_HASH_Init(). This function configures mainly:\r\n        (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit.\r\n        (##) For HMAC, the encryption key.\r\n        (##) For HMAC, the key size used for encryption.\r\n    (#)Three processing functions are available:\r\n        (##) Polling mode: processing APIs are blocking functions\r\n             i.e. they process the data and wait till the digest computation is finished\r\n             e.g. HAL_HASH_SHA1_Start()\r\n        (##) Interrupt mode: encryption and decryption APIs are not blocking functions\r\n                i.e. they process the data under interrupt\r\n                e.g. HAL_HASH_SHA1_Start_IT()\r\n        (##) DMA mode: processing APIs are not blocking functions and the CPU is\r\n             not used for data transfer i.e. the data transfer is ensured by DMA\r\n                e.g. HAL_HASH_SHA1_Start_DMA()\r\n    (#)When the processing function is called at first time after HAL_HASH_Init()\r\n       the HASH peripheral is initialized and processes the buffer in input.\r\n       After that, the digest computation is started.\r\n       When processing multi-buffer use the accumulate function to write the\r\n       data in the peripheral without starting the digest computation. In last \r\n       buffer use the start function to input the last buffer ans start the digest\r\n       computation.\r\n       (##) e.g. HAL_HASH_SHA1_Accumulate() : write 1st data buffer in the peripheral without starting the digest computation\r\n       (##) write (n-1)th data buffer in the peripheral without starting the digest computation\r\n       (##) HAL_HASH_SHA1_Start() : write (n)th data buffer in the peripheral and start the digest computation\r\n    (#)In HMAC mode, there is no Accumulate API. Only Start API is available.\r\n    (#)In case of using DMA, call the DMA start processing e.g. HAL_HASH_SHA1_Start_DMA().\r\n       After that, call the finish function in order to get the digest value\r\n       e.g. HAL_HASH_SHA1_Finish()\r\n    (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n\r\n/** @defgroup HASH HASH\r\n  * @brief HASH HAL module driver.\r\n  * @{\r\n  */\r\n#ifdef HAL_HASH_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/** @defgroup HASH_Private_Functions HASH Private Functions\r\n  * @{\r\n  */\r\nstatic void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma);\r\nstatic void HASH_DMAError(DMA_HandleTypeDef *hdma);\r\nstatic void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size);\r\nstatic void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size);\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Private functions ---------------------------------------------------------*/\r\n/** @addtogroup HASH_Private_Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  DMA HASH Input Data complete callback. \r\n  * @param  hdma: DMA handle\r\n  * @retval None\r\n  */\r\nstatic void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  uint32_t inputaddr = 0;\r\n  uint32_t buffersize = 0;\r\n  \r\n  if((HASH->CR & HASH_CR_MODE) != HASH_CR_MODE)\r\n  {\r\n    /* Disable the DMA transfer */\r\n    HASH->CR &= (uint32_t)(~HASH_CR_DMAE);\r\n    \r\n    /* Change HASH peripheral state */\r\n    hhash->State = HAL_HASH_STATE_READY;\r\n    \r\n    /* Call Input data transfer complete callback */\r\n    HAL_HASH_InCpltCallback(hhash);\r\n  }\r\n  else\r\n  {\r\n    /* Increment Interrupt counter */\r\n    hhash->HashInCount++;\r\n    /* Disable the DMA transfer before starting the next transfer */\r\n    HASH->CR &= (uint32_t)(~HASH_CR_DMAE);\r\n    \r\n    if(hhash->HashInCount <= 2)\r\n    {\r\n      /* In case HashInCount = 1, set the DMA to transfer data to HASH DIN register */\r\n      if(hhash->HashInCount == 1)\r\n      {\r\n        inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r\n        buffersize = hhash->HashBuffSize;\r\n      }\r\n      /* In case HashInCount = 2, set the DMA to transfer key to HASH DIN register */\r\n      else if(hhash->HashInCount == 2)\r\n      {\r\n        inputaddr = (uint32_t)hhash->Init.pKey;\r\n        buffersize = hhash->Init.KeySize;\r\n      }\r\n      /* Configure the number of valid bits in last word of the message */\r\n      MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * (buffersize % 4));\r\n      \r\n      /* Set the HASH DMA transfer complete */\r\n      hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;\r\n      \r\n      /* Enable the DMA In DMA Stream */\r\n      HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4 ? (buffersize+3)/4:buffersize/4));\r\n      \r\n      /* Enable DMA requests */\r\n      HASH->CR |= (HASH_CR_DMAE);\r\n    }\r\n    else\r\n    {\r\n      /* Disable the DMA transfer */\r\n      HASH->CR &= (uint32_t)(~HASH_CR_DMAE);\r\n      \r\n      /* Reset the InCount */\r\n      hhash->HashInCount = 0;\r\n      \r\n      /* Change HASH peripheral state */\r\n      hhash->State = HAL_HASH_STATE_READY;\r\n      \r\n      /* Call Input data transfer complete callback */\r\n      HAL_HASH_InCpltCallback(hhash);\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  DMA HASH communication error callback. \r\n  * @param  hdma: DMA handle\r\n  * @retval None\r\n  */\r\nstatic void HASH_DMAError(DMA_HandleTypeDef *hdma)\r\n{\r\n  HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  hhash->State= HAL_HASH_STATE_READY;\r\n  HAL_HASH_ErrorCallback(hhash);\r\n}\r\n\r\n/**\r\n  * @brief  Writes the input buffer in data register.\r\n  * @param  pInBuffer: Pointer to input buffer\r\n  * @param  Size: The size of input buffer\r\n  * @retval None\r\n  */\r\nstatic void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size)\r\n{\r\n  uint32_t buffercounter;\r\n  uint32_t inputaddr = (uint32_t) pInBuffer;\r\n  \r\n  for(buffercounter = 0; buffercounter < Size; buffercounter+=4)\r\n  {\r\n    HASH->DIN = *(uint32_t*)inputaddr;\r\n    inputaddr+=4;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Provides the message digest result.\r\n  * @param  pMsgDigest: Pointer to the message digest\r\n  * @param  Size: The size of the message digest in bytes\r\n  * @retval None\r\n  */\r\nstatic void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)\r\n{\r\n  uint32_t msgdigest = (uint32_t)pMsgDigest;\r\n  \r\n  switch(Size)\r\n  {\r\n  case 16:\r\n    /* Read the message digest */\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);\r\n    break;\r\n  case 20:\r\n    /* Read the message digest */\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);\r\n    break;\r\n  case 28:\r\n    /* Read the message digest */\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);\r\n    break;\r\n  case 32:\r\n    /* Read the message digest */\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7]);\r\n    break;\r\n  default:\r\n    break;\r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup HASH_Exported_Functions\r\n  * @{\r\n  */\r\n  \r\n\r\n/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions \r\n *  @brief    Initialization and Configuration functions. \r\n *\r\n@verbatim    \r\n ===============================================================================\r\n              ##### Initialization and de-initialization functions #####\r\n ===============================================================================\r\n    [..]  This section provides functions allowing to:\r\n      (+) Initialize the HASH according to the specified parameters \r\n          in the HASH_InitTypeDef and creates the associated handle.\r\n      (+) DeInitialize the HASH peripheral.\r\n      (+) Initialize the HASH MSP.\r\n      (+) DeInitialize HASH MSP. \r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the HASH according to the specified parameters in the\r\n            HASH_HandleTypeDef and creates the associated handle.\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)\r\n{\r\n  /* Check the hash handle allocation */\r\n  if(hhash == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_HASH_DATATYPE(hhash->Init.DataType));\r\n   \r\n  if(hhash->State == HAL_HASH_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    hhash->Lock = HAL_UNLOCKED;\r\n    /* Init the low level hardware */\r\n    HAL_HASH_MspInit(hhash);\r\n  }\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Reset HashInCount, HashBuffSize and HashITCounter */\r\n  hhash->HashInCount = 0;\r\n  hhash->HashBuffSize = 0;\r\n  hhash->HashITCounter = 0;\r\n  \r\n  /* Set the data type */\r\n  HASH->CR |= (uint32_t) (hhash->Init.DataType);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_READY;\r\n  \r\n  /* Set the default HASH phase */\r\n  hhash->Phase = HAL_HASH_PHASE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the HASH peripheral.\r\n  * @note   This API must be called before starting a new processing. \r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)\r\n{ \r\n  /* Check the HASH handle allocation */\r\n  if(hhash == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Set the default HASH phase */\r\n  hhash->Phase = HAL_HASH_PHASE_READY;\r\n  \r\n  /* Reset HashInCount, HashBuffSize and HashITCounter */\r\n  hhash->HashInCount = 0;\r\n  hhash->HashBuffSize = 0;\r\n  hhash->HashITCounter = 0;\r\n  \r\n  /* DeInit the low level hardware */\r\n  HAL_HASH_MspDeInit(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_RESET;  \r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hhash);\r\n\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the HASH MSP.\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @retval None\r\n  */\r\n__weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hhash);\r\n  \r\n  /* NOTE: This function Should not be modified, when the callback is needed,\r\n           the HAL_HASH_MspInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes HASH MSP.\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @retval None\r\n  */\r\n__weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hhash);\r\n  \r\n  /* NOTE: This function Should not be modified, when the callback is needed,\r\n           the HAL_HASH_MspDeInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Input data transfer complete callback.\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @retval None\r\n  */\r\n __weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hhash);\r\n  \r\n  /* NOTE: This function Should not be modified, when the callback is needed,\r\n           the HAL_HASH_InCpltCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  Data transfer Error callback.\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @retval None\r\n  */\r\n __weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hhash);\r\n  \r\n  /* NOTE: This function Should not be modified, when the callback is needed,\r\n           the HAL_HASH_ErrorCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  Digest computation complete callback. It is used only with interrupt.\r\n  * @note   This callback is not relevant with DMA.\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @retval None\r\n  */\r\n __weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hhash);\r\n  \r\n  /* NOTE: This function Should not be modified, when the callback is needed,\r\n           the HAL_HASH_DgstCpltCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HASH_Exported_Functions_Group2 HASH processing functions using polling mode \r\n *  @brief   processing functions using polling mode \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n              ##### HASH processing using polling mode functions#####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to calculate in polling mode\r\n          the hash value using one of the following algorithms:\r\n      (+) MD5\r\n      (+) SHA1\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in MD5 mode then processes pInBuffer.\r\n            The digest is available in pOutBuffer.\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).\r\n  * @param  Size: Length of the input buffer in bytes.\r\n  *          If the Size is multiple of 64 bytes, appending the input buffer is possible.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware\r\n  *          and appending the input buffer is no more possible.\r\n  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.\r\n  * @param  Timeout: Timeout value\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute \r\n       the message digest of a new message */\r\n    HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;\r\n  }\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n  \r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(Size);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASH_WriteData(pInBuffer, Size);\r\n  \r\n  /* Start the digest calculation */\r\n  __HAL_HASH_START_DIGEST();\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Read the message digest */\r\n  HASH_GetDigest(pOutBuffer, 16);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_READY;\r\n   \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in MD5 mode then writes the pInBuffer.\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).\r\n  * @param  Size: Length of the input buffer in bytes.\r\n  *          If the Size is multiple of 64 bytes, appending the input buffer is possible.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware\r\n  *          and appending the input buffer is no more possible.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r\n{  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute \r\n       the message digest of a new message */\r\n    HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;\r\n  }\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n  \r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(Size);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASH_WriteData(pInBuffer, Size);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.\r\n            The digest is available in pOutBuffer.\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).  \r\n  * @param  Size: Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.\r\n  * @param  Timeout: Timeout value  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n\r\n  /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute \r\n       the message digest of a new message */\r\n    HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT;\r\n  }\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n  \r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(Size);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASH_WriteData(pInBuffer, Size);\r\n  \r\n  /* Start the digest calculation */\r\n  __HAL_HASH_START_DIGEST();\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))\r\n    {\r\n      /* Check for the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n        {\r\n          /* Change state */\r\n          hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hhash);\r\n          \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n  \r\n  /* Read the message digest */\r\n  HASH_GetDigest(pOutBuffer, 20);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).\r\n  * @param  Size: Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @note  Input buffer size in bytes must be a multiple of 4 otherwise the digest computation is corrupted.  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_HASH_SHA1_BUFFER_SIZE(Size));\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute \r\n       the message digest of a new message */\r\n    HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT;\r\n  }\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n  \r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(Size);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASH_WriteData(pInBuffer, Size);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HASH_Exported_Functions_Group3 HASH processing functions using interrupt mode\r\n *  @brief   processing functions using interrupt mode. \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n              ##### HASH processing using interrupt mode functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to calculate in interrupt mode\r\n          the hash value using one of the following algorithms:\r\n      (+) MD5\r\n      (+) SHA1\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in MD5 mode then processes pInBuffer.\r\n  *         The digest is available in pOutBuffer.\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).   \r\n  * @param  Size: Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  uint32_t buffercounter;\r\n  uint32_t inputcounter;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n\r\n  if(hhash->State == HAL_HASH_STATE_READY)\r\n  {\r\n    /* Change the HASH state */\r\n    hhash->State = HAL_HASH_STATE_BUSY;\r\n    \r\n    hhash->HashInCount = Size;\r\n    hhash->pHashInBuffPtr = pInBuffer;\r\n    hhash->pHashOutBuffPtr = pOutBuffer;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n    {\r\n      /* Select the SHA1 mode */\r\n      HASH->CR |= HASH_ALGOSELECTION_MD5;\r\n      /* Reset the HASH processor core, so that the HASH will be ready to compute \r\n         the message digest of a new message */\r\n      HASH->CR |= HASH_CR_INIT;\r\n    }\r\n    \r\n    /* Reset interrupt counter */\r\n    hhash->HashITCounter = 0;\r\n    \r\n    /* Set the phase */\r\n    hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hhash);\r\n    \r\n    /* Enable Interrupts */\r\n    HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))\r\n  {\r\n    outputaddr = (uint32_t)hhash->pHashOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = __REV(HASH->HR[0]);\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = __REV(HASH->HR[1]);\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = __REV(HASH->HR[2]);\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = __REV(HASH->HR[3]);\r\n    \r\n    if(hhash->HashInCount == 0)\r\n    {\r\n      /* Disable Interrupts */\r\n      HASH->IMR = 0;\r\n      /* Change the HASH state */\r\n      hhash->State = HAL_HASH_STATE_READY;\r\n      /* Call digest computation complete callback */\r\n      HAL_HASH_DgstCpltCallback(hhash);\r\n      \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hhash);\r\n      \r\n      /* Return function status */\r\n      return HAL_OK;\r\n    }\r\n  }\r\n  \r\n  if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))\r\n  {\r\n    if(hhash->HashInCount >= 68)\r\n    {\r\n      inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r\n      /* Write the Input block in the Data IN register */\r\n      for(buffercounter = 0; buffercounter < 64; buffercounter+=4)\r\n      {\r\n        HASH->DIN = *(uint32_t*)inputaddr;\r\n        inputaddr+=4;\r\n      }\r\n      if(hhash->HashITCounter == 0)\r\n      {\r\n        HASH->DIN = *(uint32_t*)inputaddr;\r\n\r\n        if(hhash->HashInCount >= 68)\r\n        {\r\n          /* Decrement buffer counter */\r\n          hhash->HashInCount -= 68;\r\n          hhash->pHashInBuffPtr+= 68;\r\n        }\r\n        else\r\n        {\r\n          hhash->HashInCount = 0;\r\n          hhash->pHashInBuffPtr+= hhash->HashInCount;\r\n        }\r\n        /* Set Interrupt counter */\r\n        hhash->HashITCounter = 1;\r\n      }\r\n      else\r\n      {\r\n        /* Decrement buffer counter */\r\n        hhash->HashInCount -= 64;\r\n        hhash->pHashInBuffPtr+= 64;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* Get the buffer address */\r\n      inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r\n      /* Get the buffer counter */\r\n      inputcounter = hhash->HashInCount;\r\n      /* Disable Interrupts */\r\n      HASH->IMR &= ~(HASH_IT_DINI);\r\n      /* Configure the number of valid bits in last word of the message */\r\n      __HAL_HASH_SET_NBVALIDBITS(inputcounter);\r\n      \r\n      if((inputcounter > 4) && (inputcounter%4))\r\n      {\r\n        inputcounter = (inputcounter+4-inputcounter%4);\r\n      }\r\n      else if ((inputcounter < 4) && (inputcounter != 0))\r\n      {\r\n        inputcounter = 4;\r\n      }\r\n      \r\n      /* Write the Input block in the Data IN register */\r\n      for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)\r\n      {\r\n        HASH->DIN = *(uint32_t*)inputaddr;\r\n        inputaddr+=4;\r\n      }\r\n      /* Start the digest calculation */\r\n      __HAL_HASH_START_DIGEST();\r\n      /* Reset buffer counter */\r\n      hhash->HashInCount = 0;\r\n      /* Call Input data transfer complete callback */\r\n      HAL_HASH_InCpltCallback(hhash);\r\n    }\r\n  }\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.\r\n  *         The digest is available in pOutBuffer.\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed). \r\n  * @param  Size: Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t outputaddr;\r\n  uint32_t buffercounter;\r\n  uint32_t inputcounter;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  if(hhash->State == HAL_HASH_STATE_READY)\r\n  {\r\n    /* Change the HASH state */\r\n    hhash->State = HAL_HASH_STATE_BUSY;\r\n    \r\n    hhash->HashInCount = Size;\r\n    hhash->pHashInBuffPtr = pInBuffer;\r\n    hhash->pHashOutBuffPtr = pOutBuffer;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n    {\r\n      /* Select the SHA1 mode */\r\n      HASH->CR |= HASH_ALGOSELECTION_SHA1;\r\n      /* Reset the HASH processor core, so that the HASH will be ready to compute \r\n         the message digest of a new message */\r\n      HASH->CR |= HASH_CR_INIT;\r\n    }\r\n    \r\n    /* Reset interrupt counter */\r\n    hhash->HashITCounter = 0;\r\n    \r\n    /* Set the phase */\r\n    hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hhash);\r\n    \r\n    /* Enable Interrupts */\r\n    HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))\r\n  {\r\n    outputaddr = (uint32_t)hhash->pHashOutBuffPtr;\r\n    /* Read the Output block from the Output FIFO */\r\n    *(uint32_t*)(outputaddr) = __REV(HASH->HR[0]);\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = __REV(HASH->HR[1]);\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = __REV(HASH->HR[2]);\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = __REV(HASH->HR[3]);\r\n    outputaddr+=4;\r\n    *(uint32_t*)(outputaddr) = __REV(HASH->HR[4]);\r\n    if(hhash->HashInCount == 0)\r\n    {\r\n      /* Disable Interrupts */\r\n      HASH->IMR = 0;\r\n      /* Change the HASH state */\r\n      hhash->State = HAL_HASH_STATE_READY;\r\n      /* Call digest computation complete callback */\r\n      HAL_HASH_DgstCpltCallback(hhash);\r\n            \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hhash);\r\n      \r\n      /* Return function status */\r\n      return HAL_OK;\r\n    }\r\n  }\r\n  if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))\r\n  {\r\n    if(hhash->HashInCount >= 68)\r\n    {\r\n      inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r\n      /* Write the Input block in the Data IN register */\r\n      for(buffercounter = 0; buffercounter < 64; buffercounter+=4)\r\n      {\r\n        HASH->DIN = *(uint32_t*)inputaddr;\r\n        inputaddr+=4;\r\n      }\r\n      if(hhash->HashITCounter == 0)\r\n      {\r\n        HASH->DIN = *(uint32_t*)inputaddr;\r\n      \r\n        if(hhash->HashInCount >= 68)\r\n        {\r\n          /* Decrement buffer counter */\r\n          hhash->HashInCount -= 68;\r\n          hhash->pHashInBuffPtr+= 68;\r\n        }\r\n        else\r\n        {\r\n          hhash->HashInCount = 0;\r\n          hhash->pHashInBuffPtr+= hhash->HashInCount;\r\n        }\r\n        /* Set Interrupt counter */\r\n        hhash->HashITCounter = 1;\r\n      }\r\n      else\r\n      {\r\n        /* Decrement buffer counter */\r\n        hhash->HashInCount -= 64;\r\n        hhash->pHashInBuffPtr+= 64;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* Get the buffer address */\r\n      inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r\n      /* Get the buffer counter */\r\n      inputcounter = hhash->HashInCount;\r\n      /* Disable Interrupts */\r\n      HASH->IMR &= ~(HASH_IT_DINI);\r\n      /* Configure the number of valid bits in last word of the message */\r\n      __HAL_HASH_SET_NBVALIDBITS(inputcounter);\r\n      \r\n      if((inputcounter > 4) && (inputcounter%4))\r\n      {\r\n        inputcounter = (inputcounter+4-inputcounter%4);\r\n      }\r\n      else if ((inputcounter < 4) && (inputcounter != 0))\r\n      {\r\n        inputcounter = 4;\r\n      }\r\n      /* Write the Input block in the Data IN register */\r\n      for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)\r\n      {\r\n        HASH->DIN = *(uint32_t*)inputaddr;\r\n        inputaddr+=4;\r\n      }\r\n      /* Start the digest calculation */\r\n      __HAL_HASH_START_DIGEST();\r\n      /* Reset buffer counter */\r\n      hhash->HashInCount = 0;\r\n      /* Call Input data transfer complete callback */\r\n      HAL_HASH_InCpltCallback(hhash);\r\n    }\r\n  }\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief This function handles HASH interrupt request.\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @retval None\r\n  */\r\nvoid HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)\r\n{\r\n  switch(HASH->CR & HASH_CR_ALGO)\r\n  {\r\n    case HASH_ALGOSELECTION_MD5:\r\n       HAL_HASH_MD5_Start_IT(hhash, NULL, 0, NULL);\r\n    break;\r\n    \r\n    case HASH_ALGOSELECTION_SHA1:\r\n      HAL_HASH_SHA1_Start_IT(hhash, NULL, 0, NULL);\r\n    break;\r\n    \r\n    default:\r\n    break;\r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HASH_Exported_Functions_Group4 HASH processing functions using DMA mode\r\n *  @brief   processing functions using DMA mode. \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n              ##### HASH processing using DMA mode functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to calculate in DMA mode\r\n          the hash value using one of the following algorithms:\r\n      (+) MD5\r\n      (+) SHA1\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in MD5 mode then enables DMA to\r\n            control data transfer. Use HAL_HASH_MD5_Finish() to get the digest.\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).\r\n  * @param  Size: Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r\n{\r\n  uint32_t inputaddr  = (uint32_t)pInBuffer;\r\n  \r\n   /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute \r\n       the message digest of a new message */\r\n    HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;\r\n  }\r\n   \r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(Size);\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n    \r\n  /* Set the HASH DMA transfer complete callback */\r\n  hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;\r\n  /* Set the DMA error callback */\r\n  hhash->hdmain->XferErrorCallback = HASH_DMAError;\r\n  \r\n  /* Enable the DMA In DMA Stream */\r\n  HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));\r\n  \r\n  /* Enable DMA requests */\r\n  HASH->CR |= (HASH_CR_DMAE);\r\n  \r\n   /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the computed digest in MD5 mode\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.\r\n  * @param  Timeout: Timeout value  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  \r\n   /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change HASH peripheral state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Read the message digest */\r\n  HASH_GetDigest(pOutBuffer, 16);\r\n      \r\n  /* Change HASH peripheral state */\r\n  hhash->State = HAL_HASH_STATE_READY;\r\n  \r\n   /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in SHA1 mode then enables DMA to\r\n            control data transfer. Use HAL_HASH_SHA1_Finish() to get the digest.\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).\r\n  * @param  Size: Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r\n{\r\n  uint32_t inputaddr  = (uint32_t)pInBuffer;\r\n  \r\n   /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute \r\n       the message digest of a new message */\r\n    HASH->CR |= HASH_ALGOSELECTION_SHA1;\r\n    HASH->CR |= HASH_CR_INIT;\r\n  }\r\n  \r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(Size);\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n  \r\n  /* Set the HASH DMA transfer complete callback */\r\n  hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;\r\n  /* Set the DMA error callback */\r\n  hhash->hdmain->XferErrorCallback = HASH_DMAError;\r\n  \r\n  /* Enable the DMA In DMA Stream */\r\n  HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));\r\n  \r\n  /* Enable DMA requests */\r\n  HASH->CR |= (HASH_CR_DMAE);\r\n  \r\n   /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the computed digest in SHA1 mode.\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.  \r\n  * @param  Timeout: Timeout value    \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  \r\n   /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change HASH peripheral state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Read the message digest */\r\n  HASH_GetDigest(pOutBuffer, 20);\r\n  \r\n  /* Change HASH peripheral state */\r\n  hhash->State = HAL_HASH_STATE_READY;\r\n  \r\n   /* Process UnLock */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HASH_Exported_Functions_Group5 HASH-MAC (HMAC) processing functions using polling mode \r\n *  @brief   HMAC processing functions using polling mode . \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n              ##### HMAC processing using polling mode functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to calculate in polling mode\r\n          the HMAC value using one of the following algorithms:\r\n      (+) MD5\r\n      (+) SHA1\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in HMAC MD5 mode\r\n  *         then processes pInBuffer. The digest is available in pOutBuffer\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).\r\n  * @param  Size: Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.\r\n  * @param  Timeout: Timeout value  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  \r\n   /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Check if key size is greater than 64 bytes */\r\n    if(hhash->Init.KeySize > 64)\r\n    {\r\n      /* Select the HMAC MD5 mode */\r\n      HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);\r\n    }\r\n    else\r\n    {\r\n      /* Select the HMAC MD5 mode */\r\n      HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);\r\n    }\r\n  }\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n  \r\n  /************************** STEP 1 ******************************************/\r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);\r\n  \r\n  /* Start the digest calculation */\r\n  __HAL_HASH_START_DIGEST();\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  /************************** STEP 2 ******************************************/\r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(Size);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASH_WriteData(pInBuffer, Size);\r\n  \r\n  /* Start the digest calculation */\r\n  __HAL_HASH_START_DIGEST();\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > Timeout)\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  /************************** STEP 3 ******************************************/\r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);\r\n  \r\n  /* Start the digest calculation */\r\n  __HAL_HASH_START_DIGEST();\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > Timeout)\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Read the message digest */\r\n  HASH_GetDigest(pOutBuffer, 16);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in HMAC SHA1 mode\r\n  *         then processes pInBuffer. The digest is available in pOutBuffer.\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).\r\n  * @param   Size: Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.\r\n  * @param  Timeout: Timeout value  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Check if key size is greater than 64 bytes */\r\n    if(hhash->Init.KeySize > 64)\r\n    {\r\n      /* Select the HMAC SHA1 mode */\r\n      HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);\r\n    }\r\n    else\r\n    {\r\n      /* Select the HMAC SHA1 mode */\r\n      HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);\r\n    }\r\n  }\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n  \r\n  /************************** STEP 1 ******************************************/\r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);\r\n  \r\n  /* Start the digest calculation */\r\n  __HAL_HASH_START_DIGEST();\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  /************************** STEP 2 ******************************************/\r\n  /* Configure the number of valid bits in last word of the message */  \r\n  __HAL_HASH_SET_NBVALIDBITS(Size);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASH_WriteData(pInBuffer, Size);\r\n  \r\n  /* Start the digest calculation */\r\n  __HAL_HASH_START_DIGEST();\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > Timeout)\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  /************************** STEP 3 ******************************************/\r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);\r\n  \r\n  /* Start the digest calculation */\r\n  __HAL_HASH_START_DIGEST();\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > Timeout)\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  /* Read the message digest */\r\n  HASH_GetDigest(pOutBuffer, 20);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HASH_Exported_Functions_Group6 HASH-MAC (HMAC) processing functions using DMA mode \r\n *  @brief   HMAC processing functions using DMA mode . \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                ##### HMAC processing using DMA mode functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to calculate in DMA mode\r\n          the HMAC value using one of the following algorithms:\r\n      (+) MD5\r\n      (+) SHA1\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in HMAC MD5 mode\r\n  *         then enables DMA to control data transfer.\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).\r\n  * @param  Size: Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r\n{\r\n  uint32_t inputaddr  = 0;\r\n  \r\n   /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Save buffer pointer and size in handle */\r\n  hhash->pHashInBuffPtr = pInBuffer;\r\n  hhash->HashBuffSize = Size;\r\n  hhash->HashInCount = 0;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Check if key size is greater than 64 bytes */\r\n    if(hhash->Init.KeySize > 64)\r\n    {\r\n      /* Select the HMAC MD5 mode */\r\n      HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);\r\n    }\r\n    else\r\n    {\r\n      /* Select the HMAC MD5 mode */\r\n      HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);\r\n    }\r\n  }\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n  \r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r\n  \r\n  /* Get the key address */\r\n  inputaddr = (uint32_t)(hhash->Init.pKey);\r\n  \r\n  /* Set the HASH DMA transfer complete callback */\r\n  hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;\r\n  /* Set the DMA error callback */\r\n  hhash->hdmain->XferErrorCallback = HASH_DMAError;\r\n  \r\n  /* Enable the DMA In DMA Stream */\r\n  HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));\r\n  /* Enable DMA requests */\r\n  HASH->CR |= (HASH_CR_DMAE);\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in HMAC SHA1 mode\r\n  *         then enables DMA to control data transfer.\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).\r\n  * @param  Size: Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r\n{\r\n  uint32_t inputaddr  = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Save buffer pointer and size in handle */\r\n  hhash->pHashInBuffPtr = pInBuffer;\r\n  hhash->HashBuffSize = Size;\r\n  hhash->HashInCount = 0;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Check if key size is greater than 64 bytes */\r\n    if(hhash->Init.KeySize > 64)\r\n    {\r\n      /* Select the HMAC SHA1 mode */\r\n      HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);\r\n    }\r\n    else\r\n    {\r\n      /* Select the HMAC SHA1 mode */\r\n      HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);\r\n    }\r\n  }\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n  \r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r\n  \r\n  /* Get the key address */\r\n  inputaddr = (uint32_t)(hhash->Init.pKey);\r\n  \r\n  /* Set the HASH DMA transfer complete callback */\r\n  hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;\r\n  /* Set the DMA error callback */\r\n  hhash->hdmain->XferErrorCallback = HASH_DMAError;\r\n  \r\n  /* Enable the DMA In DMA Stream */\r\n  HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));\r\n  /* Enable DMA requests */\r\n  HASH->CR |= (HASH_CR_DMAE);\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HASH_Exported_Functions_Group7 Peripheral State functions \r\n *  @brief   Peripheral State functions. \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                      ##### Peripheral State functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection permits to get in run-time the status of the peripheral.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief return the HASH state\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @retval HAL state\r\n  */\r\nHAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)\r\n{\r\n  return hhash->State;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_HASH_MODULE_ENABLED */\r\n\r\n/**\r\n  * @}\r\n  */\r\n#endif /* STM32F756xx || STM32F777xx || STM32F779xx */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash_ex.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_hash_ex.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   HASH HAL Extension module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of HASH peripheral:\r\n  *           + Extended HASH processing functions based on SHA224 Algorithm\r\n  *           + Extended HASH processing functions based on SHA256 Algorithm\r\n  *         \r\n  @verbatim\r\n  ==============================================================================\r\n                     ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]\r\n    The HASH HAL driver can be used as follows:\r\n    (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():\r\n        (##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE()\r\n        (##) In case of using processing APIs based on interrupts (e.g. HAL_HMACEx_SHA224_Start())\r\n            (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()\r\n            (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()\r\n            (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler()\r\n        (##) In case of using DMA to control data transfer (e.g. HAL_HMACEx_SH224_Start_DMA())\r\n            (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()\r\n            (+++) Configure and enable one DMA stream one for managing data transfer from\r\n                memory to peripheral (input stream). Managing data transfer from\r\n                peripheral to memory can be performed only using CPU\r\n            (+++) Associate the initialized DMA handle to the HASH DMA handle\r\n                using  __HAL_LINKDMA()\r\n            (+++) Configure the priority and enable the NVIC for the transfer complete\r\n                interrupt on the DMA Stream: HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()\r\n    (#)Initialize the HASH HAL using HAL_HASH_Init(). This function configures mainly:\r\n        (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit.\r\n        (##) For HMAC, the encryption key.\r\n        (##) For HMAC, the key size used for encryption.\r\n    (#)Three processing functions are available:\r\n        (##) Polling mode: processing APIs are blocking functions\r\n             i.e. they process the data and wait till the digest computation is finished\r\n             e.g. HAL_HASHEx_SHA224_Start()\r\n        (##) Interrupt mode: encryption and decryption APIs are not blocking functions\r\n                i.e. they process the data under interrupt\r\n                e.g. HAL_HASHEx_SHA224_Start_IT()\r\n        (##) DMA mode: processing APIs are not blocking functions and the CPU is\r\n             not used for data transfer i.e. the data transfer is ensured by DMA\r\n                e.g. HAL_HASHEx_SHA224_Start_DMA()\r\n    (#)When the processing function is called at first time after HAL_HASH_Init()\r\n       the HASH peripheral is initialized and processes the buffer in input.\r\n       After that, the digest computation is started.\r\n       When processing multi-buffer use the accumulate function to write the\r\n       data in the peripheral without starting the digest computation. In last \r\n       buffer use the start function to input the last buffer ans start the digest\r\n       computation.\r\n       (##) e.g. HAL_HASHEx_SHA224_Accumulate() : write 1st data buffer in the peripheral without starting the digest computation\r\n       (##)  write (n-1)th data buffer in the peripheral without starting the digest computation\r\n       (##)  HAL_HASHEx_SHA224_Start() : write (n)th data buffer in the peripheral and start the digest computation\r\n    (#)In HMAC mode, there is no Accumulate API. Only Start API is available.\r\n    (#)In case of using DMA, call the DMA start processing e.g. HAL_HASHEx_SHA224_Start_DMA().\r\n       After that, call the finish function in order to get the digest value\r\n       e.g. HAL_HASHEx_SHA224_Finish()\r\n    (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n#if defined(STM32F756xx) || defined(STM32F777xx) || defined(STM32F779xx)\r\n\r\n/** @defgroup HASHEx HASHEx\r\n  * @brief HASH Extension HAL module driver.\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_HASH_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/** @addtogroup HASHEx_Private_Functions\r\n  * @{\r\n  */\r\nstatic void HASHEx_DMAXferCplt(DMA_HandleTypeDef *hdma);\r\nstatic void HASHEx_WriteData(uint8_t *pInBuffer, uint32_t Size);\r\nstatic void HASHEx_GetDigest(uint8_t *pMsgDigest, uint8_t Size);\r\nstatic void HASHEx_DMAError(DMA_HandleTypeDef *hdma);\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @addtogroup HASHEx_Private_Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Writes the input buffer in data register.\r\n  * @param  pInBuffer: Pointer to input buffer\r\n  * @param  Size: The size of input buffer\r\n  * @retval None\r\n  */\r\nstatic void HASHEx_WriteData(uint8_t *pInBuffer, uint32_t Size)\r\n{\r\n  uint32_t buffercounter;\r\n  uint32_t inputaddr = (uint32_t) pInBuffer;\r\n  \r\n  for(buffercounter = 0; buffercounter < Size; buffercounter+=4)\r\n  {\r\n    HASH->DIN = *(uint32_t*)inputaddr;\r\n    inputaddr+=4;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Provides the message digest result.\r\n  * @param  pMsgDigest: Pointer to the message digest\r\n  * @param  Size: The size of the message digest in bytes\r\n  * @retval None\r\n  */\r\nstatic void HASHEx_GetDigest(uint8_t *pMsgDigest, uint8_t Size)\r\n{\r\n  uint32_t msgdigest = (uint32_t)pMsgDigest;\r\n  \r\n  switch(Size)\r\n  {\r\n  case 16:\r\n    /* Read the message digest */\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);\r\n    break;\r\n  case 20:\r\n    /* Read the message digest */\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);\r\n    break;\r\n  case 28:\r\n    /* Read the message digest */\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);\r\n    break;\r\n  case 32:\r\n    /* Read the message digest */\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);\r\n    msgdigest+=4;\r\n    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7]);\r\n    break;\r\n  default:\r\n    break;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  DMA HASH Input Data complete callback. \r\n  * @param  hdma: DMA handle\r\n  * @retval None\r\n  */\r\nstatic void HASHEx_DMAXferCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  uint32_t inputaddr = 0;\r\n  uint32_t buffersize = 0;\r\n  \r\n  if((HASH->CR & HASH_CR_MODE) != HASH_CR_MODE)\r\n  {\r\n    /* Disable the DMA transfer */\r\n    HASH->CR &= (uint32_t)(~HASH_CR_DMAE);\r\n    \r\n    /* Change HASH peripheral state */\r\n    hhash->State = HAL_HASH_STATE_READY;\r\n    \r\n    /* Call Input data transfer complete callback */\r\n    HAL_HASH_InCpltCallback(hhash);\r\n  }\r\n  else\r\n  {\r\n    /* Increment Interrupt counter */\r\n    hhash->HashInCount++;\r\n    /* Disable the DMA transfer before starting the next transfer */\r\n    HASH->CR &= (uint32_t)(~HASH_CR_DMAE);\r\n    \r\n    if(hhash->HashInCount <= 2)\r\n    {\r\n      /* In case HashInCount = 1, set the DMA to transfer data to HASH DIN register */\r\n      if(hhash->HashInCount == 1)\r\n      {\r\n        inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r\n        buffersize = hhash->HashBuffSize;\r\n      }\r\n      /* In case HashInCount = 2, set the DMA to transfer key to HASH DIN register */\r\n      else if(hhash->HashInCount == 2)\r\n      {\r\n        inputaddr = (uint32_t)hhash->Init.pKey;\r\n        buffersize = hhash->Init.KeySize;\r\n      }\r\n      /* Configure the number of valid bits in last word of the message */\r\n      MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * (buffersize % 4));\r\n      \r\n      /* Set the HASH DMA transfer complete */\r\n      hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;\r\n      \r\n      /* Enable the DMA In DMA Stream */\r\n      HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4 ? (buffersize+3)/4:buffersize/4));\r\n      \r\n      /* Enable DMA requests */\r\n      HASH->CR |= (HASH_CR_DMAE);\r\n    }\r\n    else\r\n    {\r\n      /* Disable the DMA transfer */\r\n      HASH->CR &= (uint32_t)(~HASH_CR_DMAE);\r\n      \r\n      /* Reset the InCount */\r\n      hhash->HashInCount = 0;\r\n      \r\n      /* Change HASH peripheral state */\r\n      hhash->State = HAL_HASH_STATE_READY;\r\n      \r\n      /* Call Input data transfer complete callback */\r\n      HAL_HASH_InCpltCallback(hhash);\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  DMA HASH communication error callback. \r\n  * @param  hdma: DMA handle\r\n  * @retval None\r\n  */\r\nstatic void HASHEx_DMAError(DMA_HandleTypeDef *hdma)\r\n{\r\n  HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  hhash->State= HAL_HASH_STATE_READY;\r\n  HAL_HASH_ErrorCallback(hhash);\r\n}\r\n\r\n /**\r\n  * @}\r\n  */\r\n  \r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup HASHEx_Exported_Functions\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup  HASHEx_Group1 HASH processing functions  \r\n *  @brief   processing functions using polling mode \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n              ##### HASH processing using polling mode functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to calculate in polling mode\r\n          the hash value using one of the following algorithms:\r\n      (+) SHA224\r\n      (+) SHA256\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in SHA224 mode\r\n  *         then processes pInBuffer. The digest is available in pOutBuffer\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).\r\n  * @param  Size: Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes.\r\n  * @param  Timeout: Specify Timeout value   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute \r\n       the message digest of a new message */\r\n    HASH->CR |= HASH_ALGOSELECTION_SHA224 | HASH_CR_INIT;\r\n  }\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n  \r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(Size);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASHEx_WriteData(pInBuffer, Size);\r\n  \r\n  /* Start the digest calculation */\r\n  __HAL_HASH_START_DIGEST();\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */          \r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Read the message digest */\r\n  HASHEx_GetDigest(pOutBuffer, 28);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.\r\n            The digest is available in pOutBuffer.\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed). \r\n  * @param  Size: Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 32 bytes.\r\n  * @param  Timeout: Specify Timeout value   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute \r\n       the message digest of a new message */\r\n    HASH->CR |= HASH_ALGOSELECTION_SHA256 | HASH_CR_INIT;\r\n  }\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n  \r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(Size);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASHEx_WriteData(pInBuffer, Size);\r\n  \r\n  /* Start the digest calculation */\r\n  __HAL_HASH_START_DIGEST();\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */          \r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Read the message digest */\r\n  HASHEx_GetDigest(pOutBuffer, 32);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_READY;\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);  \r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in SHA224 mode\r\n  *         then processes pInBuffer. The digest is available in pOutBuffer\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).\r\n  * @param  Size: Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute \r\n       the message digest of a new message */\r\n    HASH->CR |= HASH_ALGOSELECTION_SHA224 | HASH_CR_INIT;\r\n  }\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n  \r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(Size);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASHEx_WriteData(pInBuffer, Size);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.\r\n            The digest is available in pOutBuffer.\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).\r\n  * @param  Size: Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r\n{\r\n   /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute \r\n       the message digest of a new message */\r\n    HASH->CR |= HASH_ALGOSELECTION_SHA256 | HASH_CR_INIT;\r\n  }\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n  \r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(Size);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASHEx_WriteData(pInBuffer, Size);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HASHEx_Group2 HMAC processing functions using polling mode \r\n *  @brief   HMAC processing functions using polling mode . \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n            ##### HMAC processing using polling mode functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to calculate in polling mode\r\n          the HMAC value using one of the following algorithms:\r\n      (+) SHA224\r\n      (+) SHA256\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in HMAC SHA224 mode\r\n  *         then processes pInBuffer. The digest is available in pOutBuffer.\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed). \r\n  * @param  Size: Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.\r\n  * @param  Timeout: Timeout value \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n                                                  \r\n   /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Check if key size is greater than 64 bytes */\r\n    if(hhash->Init.KeySize > 64)\r\n    {\r\n      /* Select the HMAC SHA224 mode */\r\n      HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);\r\n    }\r\n    else\r\n    {\r\n      /* Select the HMAC SHA224 mode */\r\n      HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);\r\n    }\r\n  }\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n  \r\n  /************************** STEP 1 ******************************************/\r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);\r\n  \r\n  /* Start the digest calculation */\r\n  __HAL_HASH_START_DIGEST();\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */          \r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  /************************** STEP 2 ******************************************/\r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(Size);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASHEx_WriteData(pInBuffer, Size);\r\n  \r\n  /* Start the digest calculation */\r\n  __HAL_HASH_START_DIGEST();\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > Timeout)\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */          \r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  /************************** STEP 3 ******************************************/\r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);\r\n  \r\n  /* Start the digest calculation */\r\n  __HAL_HASH_START_DIGEST();\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > Timeout)\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */          \r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  /* Read the message digest */\r\n  HASHEx_GetDigest(pOutBuffer, 28);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in HMAC SHA256 mode\r\n  *         then processes pInBuffer. The digest is available in pOutBuffer\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed). \r\n  * @param  Size: Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.\r\n  * @param  Timeout: Timeout value \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Check if key size is greater than 64 bytes */\r\n    if(hhash->Init.KeySize > 64)\r\n    {\r\n      /* Select the HMAC SHA256 mode */\r\n      HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY);\r\n    }\r\n    else\r\n    {\r\n      /* Select the HMAC SHA256 mode */\r\n      HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC);\r\n    }\r\n    /* Reset the HASH processor core, so that the HASH will be ready to compute \r\n       the message digest of a new message */\r\n    HASH->CR |= HASH_CR_INIT;\r\n  }\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n  \r\n  /************************** STEP 1 ******************************************/\r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);\r\n  \r\n  /* Start the digest calculation */\r\n  __HAL_HASH_START_DIGEST();\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */          \r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  /************************** STEP 2 ******************************************/\r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(Size);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASHEx_WriteData(pInBuffer, Size);\r\n  \r\n  /* Start the digest calculation */\r\n  __HAL_HASH_START_DIGEST();\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > Timeout)\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */          \r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  /************************** STEP 3 ******************************************/\r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r\n  \r\n  /* Write input buffer in data register */\r\n  HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);\r\n  \r\n  /* Start the digest calculation */\r\n  __HAL_HASH_START_DIGEST();\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > Timeout)\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */          \r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  /* Read the message digest */\r\n  HASHEx_GetDigest(pOutBuffer, 32);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_READY;\r\n  \r\n   /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HASHEx_Group3 HASH processing functions using interrupt mode\r\n *  @brief   processing functions using interrupt mode. \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n              ##### HASH processing using interrupt functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to calculate in interrupt mode\r\n          the hash value using one of the following algorithms:\r\n      (+) SHA224\r\n      (+) SHA256\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in SHA224 mode then processes pInBuffer.\r\n  *         The digest is available in pOutBuffer.\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).\r\n  * @param  Size: Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t buffercounter;\r\n  uint32_t inputcounter;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n\r\n  if(hhash->State == HAL_HASH_STATE_READY)\r\n  {\r\n    /* Change the HASH state */\r\n    hhash->State = HAL_HASH_STATE_BUSY;\r\n    \r\n    hhash->HashInCount = Size;\r\n    hhash->pHashInBuffPtr = pInBuffer;\r\n    hhash->pHashOutBuffPtr = pOutBuffer;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n    {\r\n      /* Select the SHA224 mode */\r\n      HASH->CR |= HASH_ALGOSELECTION_SHA224;\r\n      /* Reset the HASH processor core, so that the HASH will be ready to compute \r\n         the message digest of a new message */\r\n      HASH->CR |= HASH_CR_INIT;\r\n    }\r\n    /* Reset interrupt counter */\r\n    hhash->HashITCounter = 0;\r\n    /* Set the phase */\r\n    hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hhash);\r\n    \r\n    /* Enable Interrupts */\r\n    HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))\r\n  {\r\n    /* Read the message digest */\r\n    HASHEx_GetDigest(hhash->pHashOutBuffPtr, 28);\r\n    if(hhash->HashInCount == 0)\r\n    {\r\n      /* Disable Interrupts */\r\n      HASH->IMR = 0;\r\n      /* Change the HASH state */\r\n      hhash->State = HAL_HASH_STATE_READY;\r\n      /* Call digest computation complete callback */\r\n      HAL_HASH_DgstCpltCallback(hhash);\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hhash);\r\n      \r\n      /* Return function status */\r\n      return HAL_OK;\r\n    }\r\n  }\r\n  if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))\r\n  {\r\n    if(hhash->HashInCount >= 68)\r\n    {\r\n      inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r\n      /* Write the Input block in the Data IN register */\r\n      for(buffercounter = 0; buffercounter < 64; buffercounter+=4)\r\n      {\r\n        HASH->DIN = *(uint32_t*)inputaddr;\r\n        inputaddr+=4;\r\n      }\r\n      if(hhash->HashITCounter == 0)\r\n      {\r\n        HASH->DIN = *(uint32_t*)inputaddr;\r\n        if(hhash->HashInCount >= 68)\r\n        {\r\n          /* Decrement buffer counter */\r\n          hhash->HashInCount -= 68;\r\n          hhash->pHashInBuffPtr+= 68;\r\n        }\r\n        else\r\n        {\r\n           hhash->HashInCount = 0;\r\n          hhash->pHashInBuffPtr+= hhash->HashInCount;\r\n        }\r\n        /* Set Interrupt counter */\r\n        hhash->HashITCounter = 1;\r\n      }\r\n      else\r\n      {\r\n        /* Decrement buffer counter */\r\n        hhash->HashInCount -= 64;\r\n        hhash->pHashInBuffPtr+= 64;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* Get the buffer address */\r\n      inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r\n      /* Get the buffer counter */\r\n      inputcounter = hhash->HashInCount;\r\n      /* Disable Interrupts */\r\n      HASH->IMR &= ~(HASH_IT_DINI);\r\n      /* Configure the number of valid bits in last word of the message */\r\n      __HAL_HASH_SET_NBVALIDBITS(inputcounter);\r\n      \r\n      if((inputcounter > 4) && (inputcounter%4))\r\n      {\r\n        inputcounter = (inputcounter+4-inputcounter%4);\r\n      }\r\n      else if ((inputcounter < 4) && (inputcounter != 0))\r\n      {\r\n        inputcounter = 4;\r\n      }\r\n      /* Write the Input block in the Data IN register */\r\n      for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)\r\n      {\r\n        HASH->DIN = *(uint32_t*)inputaddr;\r\n        inputaddr+=4;\r\n      }\r\n      /* Start the digest calculation */\r\n      __HAL_HASH_START_DIGEST();\r\n      /* Reset buffer counter */\r\n      hhash->HashInCount = 0;\r\n      /* Call Input data transfer complete callback */\r\n      HAL_HASH_InCpltCallback(hhash);\r\n    }\r\n  }\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.\r\n  *         The digest is available in pOutBuffer.\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).\r\n  * @param  Size: Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)\r\n{\r\n  uint32_t inputaddr;\r\n  uint32_t buffercounter;\r\n  uint32_t inputcounter;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n\r\n  if(hhash->State == HAL_HASH_STATE_READY)\r\n  {\r\n    /* Change the HASH state */\r\n    hhash->State = HAL_HASH_STATE_BUSY;\r\n    \r\n    hhash->HashInCount = Size;\r\n    hhash->pHashInBuffPtr = pInBuffer;\r\n    hhash->pHashOutBuffPtr = pOutBuffer;\r\n    \r\n    /* Check if initialization phase has already been performed */\r\n    if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n    {\r\n      /* Select the SHA256 mode */\r\n      HASH->CR |= HASH_ALGOSELECTION_SHA256;\r\n      /* Reset the HASH processor core, so that the HASH will be ready to compute \r\n         the message digest of a new message */\r\n      HASH->CR |= HASH_CR_INIT;\r\n    }\r\n    \r\n    /* Reset interrupt counter */\r\n    hhash->HashITCounter = 0;\r\n    \r\n    /* Set the phase */\r\n    hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hhash);\r\n    \r\n    /* Enable Interrupts */\r\n    HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);\r\n    \r\n    /* Return function status */\r\n    return HAL_OK;\r\n  }\r\n  if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))\r\n  {\r\n    /* Read the message digest */\r\n    HASHEx_GetDigest(hhash->pHashOutBuffPtr, 32);\r\n    if(hhash->HashInCount == 0)\r\n    {\r\n      /* Disable Interrupts */\r\n      HASH->IMR = 0;\r\n      /* Change the HASH state */\r\n      hhash->State = HAL_HASH_STATE_READY;\r\n      /* Call digest computation complete callback */\r\n      HAL_HASH_DgstCpltCallback(hhash);\r\n      \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hhash);\r\n      \r\n      /* Return function status */\r\n      return HAL_OK;\r\n    }\r\n  }\r\n  if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))\r\n  {\r\n    if(hhash->HashInCount >= 68)\r\n    {\r\n      inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r\n      /* Write the Input block in the Data IN register */\r\n      for(buffercounter = 0; buffercounter < 64; buffercounter+=4)\r\n      {\r\n        HASH->DIN = *(uint32_t*)inputaddr;\r\n        inputaddr+=4;\r\n      }\r\n      if(hhash->HashITCounter == 0)\r\n      {\r\n        HASH->DIN = *(uint32_t*)inputaddr;\r\n        \r\n        if(hhash->HashInCount >= 68)\r\n        {\r\n          /* Decrement buffer counter */\r\n          hhash->HashInCount -= 68;\r\n          hhash->pHashInBuffPtr+= 68;\r\n        }\r\n        else\r\n        {\r\n          hhash->HashInCount = 0;\r\n          hhash->pHashInBuffPtr+= hhash->HashInCount;\r\n        }\r\n        /* Set Interrupt counter */\r\n        hhash->HashITCounter = 1;\r\n      }\r\n      else\r\n      {\r\n        /* Decrement buffer counter */\r\n        hhash->HashInCount -= 64;\r\n        hhash->pHashInBuffPtr+= 64;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* Get the buffer address */\r\n      inputaddr = (uint32_t)hhash->pHashInBuffPtr;\r\n      /* Get the buffer counter */\r\n      inputcounter = hhash->HashInCount;\r\n      /* Disable Interrupts */\r\n      HASH->IMR &= ~(HASH_IT_DINI);\r\n      /* Configure the number of valid bits in last word of the message */\r\n      __HAL_HASH_SET_NBVALIDBITS(inputcounter);\r\n      \r\n      if((inputcounter > 4) && (inputcounter%4))\r\n      {\r\n        inputcounter = (inputcounter+4-inputcounter%4);\r\n      }\r\n      else if ((inputcounter < 4) && (inputcounter != 0))\r\n      {\r\n        inputcounter = 4;\r\n      }\r\n      \r\n      /* Write the Input block in the Data IN register */\r\n      for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)\r\n      {\r\n        HASH->DIN = *(uint32_t*)inputaddr;\r\n        inputaddr+=4;\r\n      }\r\n      /* Start the digest calculation */\r\n      __HAL_HASH_START_DIGEST();\r\n      /* Reset buffer counter */\r\n      hhash->HashInCount = 0;\r\n      /* Call Input data transfer complete callback */\r\n      HAL_HASH_InCpltCallback(hhash);\r\n    }\r\n  }\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief This function handles HASH interrupt request.\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @retval None\r\n  */\r\nvoid HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash)\r\n{\r\n  switch(HASH->CR & HASH_CR_ALGO)\r\n  {\r\n    \r\n    case HASH_ALGOSELECTION_SHA224:\r\n       HAL_HASHEx_SHA224_Start_IT(hhash, NULL, 0, NULL);\r\n    break;\r\n    \r\n    case HASH_ALGOSELECTION_SHA256:\r\n      HAL_HASHEx_SHA256_Start_IT(hhash, NULL, 0, NULL);\r\n    break;\r\n    \r\n    default:\r\n    break;\r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HASHEx_Group4 HASH processing functions using DMA mode\r\n *  @brief   processing functions using DMA mode. \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                ##### HASH processing using DMA functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to calculate in DMA mode\r\n          the hash value using one of the following algorithms:\r\n      (+) SHA224\r\n      (+) SHA256\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in SHA224 mode then enables DMA to\r\n            control data transfer. Use HAL_HASH_SHA224_Finish() to get the digest.\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).\r\n  * @param  Size: Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r\n{\r\n  uint32_t inputaddr  = (uint32_t)pInBuffer;\r\n  \r\n   /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute \r\n       the message digest of a new message */\r\n    HASH->CR |= HASH_ALGOSELECTION_SHA224 | HASH_CR_INIT;\r\n  }\r\n   \r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(Size);\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n    \r\n  /* Set the HASH DMA transfer complete callback */\r\n  hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;\r\n  /* Set the DMA error callback */\r\n  hhash->hdmain->XferErrorCallback = HASHEx_DMAError;\r\n  \r\n  /* Enable the DMA In DMA Stream */\r\n  HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));\r\n  \r\n  /* Enable DMA requests */\r\n  HASH->CR |= (HASH_CR_DMAE);\r\n  \r\n   /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the computed digest in SHA224\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes.\r\n  * @param  Timeout: Timeout value    \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change HASH peripheral state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */          \r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Read the message digest */\r\n  HASHEx_GetDigest(pOutBuffer, 28);\r\n      \r\n  /* Change HASH peripheral state */\r\n  hhash->State = HAL_HASH_STATE_READY;\r\n  \r\n   /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in SHA256 mode then enables DMA to\r\n            control data transfer. Use HAL_HASH_SHA256_Finish() to get the digest.\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).\r\n  * @param  Size: Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r\n{\r\n  uint32_t inputaddr  = (uint32_t)pInBuffer;\r\n  \r\n   /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute \r\n       the message digest of a new message */\r\n    HASH->CR |= HASH_ALGOSELECTION_SHA256 | HASH_CR_INIT;\r\n  }\r\n  \r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(Size);\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n    \r\n  /* Set the HASH DMA transfer complete callback */\r\n  hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;\r\n  /* Set the DMA error callback */\r\n  hhash->hdmain->XferErrorCallback = HASHEx_DMAError;\r\n  \r\n  /* Enable the DMA In DMA Stream */\r\n  HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));\r\n  \r\n  /* Enable DMA requests */\r\n  HASH->CR |= (HASH_CR_DMAE);\r\n  \r\n   /* Process UnLock */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the computed digest in SHA256.\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 32 bytes.\r\n  * @param  Timeout: Timeout value    \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;   \r\n  \r\n   /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change HASH peripheral state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        /* Change state */\r\n        hhash->State = HAL_HASH_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */          \r\n        __HAL_UNLOCK(hhash);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Read the message digest */\r\n  HASHEx_GetDigest(pOutBuffer, 32);\r\n  \r\n  /* Change HASH peripheral state */\r\n  hhash->State = HAL_HASH_STATE_READY;\r\n  \r\n   /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n/** @defgroup HASHEx_Group5 HMAC processing functions using DMA mode \r\n *  @brief   HMAC processing functions using DMA mode . \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                ##### HMAC processing using DMA functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to calculate in DMA mode\r\n          the HMAC value using one of the following algorithms:\r\n      (+) SHA224\r\n      (+) SHA256\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in HMAC SHA224 mode\r\n  *         then enables DMA to control data transfer.\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).\r\n  * @param  Size: Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r\n{\r\n  uint32_t inputaddr;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Save buffer pointer and size in handle */\r\n  hhash->pHashInBuffPtr = pInBuffer;\r\n  hhash->HashBuffSize = Size;\r\n  hhash->HashInCount = 0;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Check if key size is greater than 64 bytes */\r\n    if(hhash->Init.KeySize > 64)\r\n    {\r\n      /* Select the HMAC SHA224 mode */\r\n      HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);\r\n    }\r\n    else\r\n    {\r\n      /* Select the HMAC SHA224 mode */\r\n      HASH->CR |= (HASH_ALGOSELECTION_SHA224 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);\r\n    }\r\n  }\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n  \r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r\n  \r\n  /* Get the key address */\r\n  inputaddr = (uint32_t)(hhash->Init.pKey);\r\n  \r\n  /* Set the HASH DMA transfer complete callback */\r\n  hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;\r\n  /* Set the DMA error callback */\r\n  hhash->hdmain->XferErrorCallback = HASHEx_DMAError;\r\n  \r\n  /* Enable the DMA In DMA Stream */\r\n  HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));\r\n  /* Enable DMA requests */\r\n  HASH->CR |= (HASH_CR_DMAE);\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the HASH peripheral in HMAC SHA256 mode\r\n  *         then enables DMA to control data transfer.\r\n  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains\r\n  *         the configuration information for HASH module\r\n  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).\r\n  * @param  Size: Length of the input buffer in bytes.\r\n  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)\r\n{\r\n  uint32_t inputaddr;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hhash);\r\n  \r\n  /* Change the HASH state */\r\n  hhash->State = HAL_HASH_STATE_BUSY;\r\n  \r\n  /* Save buffer pointer and size in handle */\r\n  hhash->pHashInBuffPtr = pInBuffer;\r\n  hhash->HashBuffSize = Size;\r\n  hhash->HashInCount = 0;\r\n  \r\n  /* Check if initialization phase has already been performed */\r\n  if(hhash->Phase == HAL_HASH_PHASE_READY)\r\n  {\r\n    /* Check if key size is greater than 64 bytes */\r\n    if(hhash->Init.KeySize > 64)\r\n    {\r\n      /* Select the HMAC SHA256 mode */\r\n      HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY);\r\n    }\r\n    else\r\n    {\r\n      /* Select the HMAC SHA256 mode */\r\n      HASH->CR |= (HASH_ALGOSELECTION_SHA256 | HASH_ALGOMODE_HMAC);\r\n    }\r\n    /* Reset the HASH processor core, so that the HASH will be ready to compute \r\n       the message digest of a new message */\r\n    HASH->CR |= HASH_CR_INIT;\r\n  }\r\n  \r\n  /* Set the phase */\r\n  hhash->Phase = HAL_HASH_PHASE_PROCESS;\r\n  \r\n  /* Configure the number of valid bits in last word of the message */\r\n  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);\r\n  \r\n  /* Get the key address */\r\n  inputaddr = (uint32_t)(hhash->Init.pKey);\r\n  \r\n  /* Set the HASH DMA transfer complete callback */\r\n  hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;\r\n  /* Set the DMA error callback */\r\n  hhash->hdmain->XferErrorCallback = HASHEx_DMAError;\r\n  \r\n  /* Enable the DMA In DMA Stream */\r\n  HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));\r\n  /* Enable DMA requests */\r\n  HASH->CR |= (HASH_CR_DMAE);\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hhash);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n#endif /* HAL_HASH_MODULE_ENABLED */\r\n\r\n/**\r\n  * @}\r\n  */\r\n#endif /* STM32F756xx || STM32F777xx || STM32F779xx */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hcd.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_hcd.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   HCD HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the USB Peripheral Controller:\r\n  *           + Initialization and de-initialization functions\r\n  *           + IO operation functions\r\n  *           + Peripheral Control functions \r\n  *           + Peripheral State functions\r\n  *         \r\n  @verbatim\r\n  ==============================================================================\r\n                    ##### How to use this driver #####\r\n  ==============================================================================\r\n  [..]\r\n    (#)Declare a HCD_HandleTypeDef handle structure, for example:\r\n       HCD_HandleTypeDef  hhcd;\r\n        \r\n    (#)Fill parameters of Init structure in HCD handle\r\n  \r\n    (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...) \r\n\r\n    (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:\r\n        (##) Enable the HCD/USB Low Level interface clock using the following macros\r\n             (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();\r\n             (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)\r\n             (+++) __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE(); (For High Speed Mode)\r\n           \r\n        (##) Initialize the related GPIO clocks\r\n        (##) Configure HCD pin-out\r\n        (##) Configure HCD NVIC interrupt\r\n    \r\n    (#)Associate the Upper USB Host stack to the HAL HCD Driver:\r\n        (##) hhcd.pData = phost;\r\n\r\n    (#)Enable HCD transmission and reception:\r\n        (##) HAL_HCD_Start();\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup HCD HCD \r\n  * @brief HCD HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_HCD_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function ----------------------------------------------------------*/\r\n/** @defgroup HCD_Private_Functions HCD Private Functions\r\n  * @{\r\n  */\r\nstatic void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);\r\nstatic void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); \r\nstatic void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd);\r\nstatic void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup HCD_Exported_Functions HCD Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions \r\n *  @brief    Initialization and Configuration functions \r\n *\r\n@verbatim    \r\n ===============================================================================\r\n          ##### Initialization and de-initialization functions #####\r\n ===============================================================================\r\n    [..]  This section provides functions allowing to:\r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initialize the host driver.\r\n  * @param  hhcd: HCD handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)\r\n{ \r\n  /* Check the HCD handle allocation */\r\n  if(hhcd == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));\r\n\r\n  hhcd->State = HAL_HCD_STATE_BUSY;\r\n  \r\n  /* Init the low level hardware : GPIO, CLOCK, NVIC... */\r\n  HAL_HCD_MspInit(hhcd);\r\n\r\n  /* Disable the Interrupts */\r\n __HAL_HCD_DISABLE(hhcd);\r\n \r\n /*Init the Core (common init.) */\r\n USB_CoreInit(hhcd->Instance, hhcd->Init);\r\n \r\n /* Force Host Mode*/\r\n USB_SetCurrentMode(hhcd->Instance , USB_OTG_HOST_MODE);\r\n \r\n /* Init Host */\r\n USB_HostInit(hhcd->Instance, hhcd->Init);\r\n \r\n hhcd->State= HAL_HCD_STATE_READY;\r\n \r\n return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initialize a host channel.\r\n  * @param  hhcd: HCD handle\r\n  * @param  ch_num: Channel number.\r\n  *         This parameter can be a value from 1 to 15\r\n  * @param  epnum: Endpoint number.\r\n  *          This parameter can be a value from 1 to 15\r\n  * @param  dev_address : Current device address\r\n  *          This parameter can be a value from 0 to 255\r\n  * @param  speed: Current device speed.\r\n  *          This parameter can be one of these values:\r\n  *            HCD_SPEED_HIGH: High speed mode,\r\n  *            HCD_SPEED_FULL: Full speed mode,\r\n  *            HCD_SPEED_LOW: Low speed mode\r\n  * @param  ep_type: Endpoint Type.\r\n  *          This parameter can be one of these values:\r\n  *            EP_TYPE_CTRL: Control type,\r\n  *            EP_TYPE_ISOC: Isochronous type,\r\n  *            EP_TYPE_BULK: Bulk type,\r\n  *            EP_TYPE_INTR: Interrupt type\r\n  * @param  mps: Max Packet Size.\r\n  *          This parameter can be a value from 0 to32K\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,  \r\n                                  uint8_t ch_num,\r\n                                  uint8_t epnum,\r\n                                  uint8_t dev_address,\r\n                                  uint8_t speed,\r\n                                  uint8_t ep_type,\r\n                                  uint16_t mps)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  \r\n  __HAL_LOCK(hhcd); \r\n  \r\n  hhcd->hc[ch_num].dev_addr = dev_address;\r\n  hhcd->hc[ch_num].max_packet = mps;\r\n  hhcd->hc[ch_num].ch_num = ch_num;\r\n  hhcd->hc[ch_num].ep_type = ep_type;\r\n  hhcd->hc[ch_num].ep_num = epnum & 0x7F;\r\n  hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80) == 0x80);\r\n  hhcd->hc[ch_num].speed = speed;\r\n\r\n  status =  USB_HC_Init(hhcd->Instance, \r\n                        ch_num,\r\n                        epnum,\r\n                        dev_address,\r\n                        speed,\r\n                        ep_type,\r\n                        mps);\r\n  __HAL_UNLOCK(hhcd); \r\n  \r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Halt a host channel.\r\n  * @param  hhcd: HCD handle\r\n  * @param  ch_num: Channel number.\r\n  *         This parameter can be a value from 1 to 15\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  \r\n  __HAL_LOCK(hhcd);   \r\n  USB_HC_Halt(hhcd->Instance, ch_num);   \r\n  __HAL_UNLOCK(hhcd);\r\n  \r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  DeInitialize the host driver.\r\n  * @param  hhcd: HCD handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)\r\n{\r\n  /* Check the HCD handle allocation */\r\n  if(hhcd == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  hhcd->State = HAL_HCD_STATE_BUSY;\r\n  \r\n  /* DeInit the low level hardware */\r\n  HAL_HCD_MspDeInit(hhcd);\r\n  \r\n   __HAL_HCD_DISABLE(hhcd);\r\n  \r\n  hhcd->State = HAL_HCD_STATE_RESET; \r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initialize the HCD MSP.\r\n  * @param  hhcd: HCD handle\r\n  * @retval None\r\n  */\r\n__weak void  HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hhcd);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_HCD_MspInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DeInitialize the HCD MSP.\r\n  * @param  hhcd: HCD handle\r\n  * @retval None\r\n  */\r\n__weak void  HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hhcd);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_HCD_MspDeInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions\r\n  *  @brief   HCD IO operation functions\r\n  *\r\n@verbatim\r\n ===============================================================================\r\n                      ##### IO operation functions #####\r\n ===============================================================================\r\n [..] This subsection provides a set of functions allowing to manage the USB Host Data \r\n    Transfer\r\n       \r\n@endverbatim\r\n  * @{\r\n  */\r\n  \r\n/**                                \r\n  * @brief  Submit a new URB for processing. \r\n  * @param  hhcd: HCD handle\r\n  * @param  ch_num: Channel number.\r\n  *         This parameter can be a value from 1 to 15\r\n  * @param  direction: Channel number.\r\n  *          This parameter can be one of these values:\r\n  *           0 : Output / 1 : Input\r\n  * @param  ep_type: Endpoint Type.\r\n  *          This parameter can be one of these values:\r\n  *            EP_TYPE_CTRL: Control type/\r\n  *            EP_TYPE_ISOC: Isochronous type/\r\n  *            EP_TYPE_BULK: Bulk type/\r\n  *            EP_TYPE_INTR: Interrupt type/\r\n  * @param  token: Endpoint Type.\r\n  *          This parameter can be one of these values:\r\n  *            0: HC_PID_SETUP / 1: HC_PID_DATA1\r\n  * @param  pbuff: pointer to URB data\r\n  * @param  length: Length of URB data\r\n  * @param  do_ping: activate do ping protocol (for high speed only).\r\n  *          This parameter can be one of these values:\r\n  *           0 : do ping inactive / 1 : do ping active \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,\r\n                                            uint8_t ch_num, \r\n                                            uint8_t direction ,\r\n                                            uint8_t ep_type,  \r\n                                            uint8_t token, \r\n                                            uint8_t* pbuff, \r\n                                            uint16_t length,\r\n                                            uint8_t do_ping) \r\n{\r\n  hhcd->hc[ch_num].ep_is_in = direction;\r\n  hhcd->hc[ch_num].ep_type  = ep_type; \r\n  \r\n  if(token == 0)\r\n  {\r\n    hhcd->hc[ch_num].data_pid = HC_PID_SETUP;\r\n  }\r\n  else\r\n  {\r\n    hhcd->hc[ch_num].data_pid = HC_PID_DATA1;\r\n  }\r\n  \r\n  /* Manage Data Toggle */\r\n  switch(ep_type)\r\n  {\r\n  case EP_TYPE_CTRL:\r\n    if((token == 1) && (direction == 0)) /*send data */\r\n    {\r\n      if ( length == 0 )\r\n      { /* For Status OUT stage, Length==0, Status Out PID = 1 */\r\n        hhcd->hc[ch_num].toggle_out = 1;\r\n      }\r\n      \r\n      /* Set the Data Toggle bit as per the Flag */\r\n      if ( hhcd->hc[ch_num].toggle_out == 0)\r\n      { /* Put the PID 0 */\r\n        hhcd->hc[ch_num].data_pid = HC_PID_DATA0;    \r\n      }\r\n      else\r\n      { /* Put the PID 1 */\r\n        hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;\r\n      }\r\n      if(hhcd->hc[ch_num].urb_state  != URB_NOTREADY)\r\n      {\r\n        hhcd->hc[ch_num].do_ping = do_ping;\r\n      }\r\n    }\r\n    break;\r\n  \r\n  case EP_TYPE_BULK:\r\n    if(direction == 0)\r\n    {\r\n      /* Set the Data Toggle bit as per the Flag */\r\n      if ( hhcd->hc[ch_num].toggle_out == 0)\r\n      { /* Put the PID 0 */\r\n        hhcd->hc[ch_num].data_pid = HC_PID_DATA0;    \r\n      }\r\n      else\r\n      { /* Put the PID 1 */\r\n        hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;\r\n      }\r\n      if(hhcd->hc[ch_num].urb_state  != URB_NOTREADY)\r\n      {\r\n        hhcd->hc[ch_num].do_ping = do_ping;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      if( hhcd->hc[ch_num].toggle_in == 0)\r\n      {\r\n        hhcd->hc[ch_num].data_pid = HC_PID_DATA0;\r\n      }\r\n      else\r\n      {\r\n        hhcd->hc[ch_num].data_pid = HC_PID_DATA1;\r\n      }\r\n    }\r\n    \r\n    break;\r\n  case EP_TYPE_INTR:\r\n    if(direction == 0)\r\n    {\r\n      /* Set the Data Toggle bit as per the Flag */\r\n      if ( hhcd->hc[ch_num].toggle_out == 0)\r\n      { /* Put the PID 0 */\r\n        hhcd->hc[ch_num].data_pid = HC_PID_DATA0;    \r\n      }\r\n      else\r\n      { /* Put the PID 1 */\r\n        hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      if( hhcd->hc[ch_num].toggle_in == 0)\r\n      {\r\n        hhcd->hc[ch_num].data_pid = HC_PID_DATA0;\r\n      }\r\n      else\r\n      {\r\n        hhcd->hc[ch_num].data_pid = HC_PID_DATA1;\r\n      }\r\n    }\r\n    break;\r\n    \r\n  case EP_TYPE_ISOC: \r\n    hhcd->hc[ch_num].data_pid = HC_PID_DATA0;\r\n    break;      \r\n  }\r\n  \r\n  hhcd->hc[ch_num].xfer_buff = pbuff;\r\n  hhcd->hc[ch_num].xfer_len  = length;\r\n  hhcd->hc[ch_num].urb_state =   URB_IDLE;  \r\n  hhcd->hc[ch_num].xfer_count = 0 ;\r\n  hhcd->hc[ch_num].ch_num = ch_num;\r\n  hhcd->hc[ch_num].state = HC_IDLE;\r\n  \r\n  return USB_HC_StartXfer(hhcd->Instance, &(hhcd->hc[ch_num]), hhcd->Init.dma_enable);\r\n}\r\n\r\n/**\r\n  * @brief  Handle HCD interrupt request.\r\n  * @param  hhcd: HCD handle\r\n  * @retval None\r\n  */\r\nvoid HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)\r\n{\r\n  USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;\r\n  uint32_t i = 0 , interrupt = 0;\r\n  \r\n  /* ensure that we are in device mode */\r\n  if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST)\r\n  {\r\n    /* avoid spurious interrupt */\r\n    if(__HAL_HCD_IS_INVALID_INTERRUPT(hhcd)) \r\n    {\r\n      return;\r\n    }\r\n    \r\n    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))\r\n    {\r\n     /* incorrect mode, acknowledge the interrupt */\r\n      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);\r\n    }\r\n    \r\n    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR))\r\n    {\r\n     /* incorrect mode, acknowledge the interrupt */\r\n      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR);\r\n    }\r\n\r\n    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE))\r\n    {\r\n     /* incorrect mode, acknowledge the interrupt */\r\n      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE);\r\n    }   \r\n    \r\n    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS))\r\n    {\r\n     /* incorrect mode, acknowledge the interrupt */\r\n      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS);\r\n    }     \r\n    \r\n    /* Handle Host Disconnect Interrupts */\r\n    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT))\r\n    {\r\n      \r\n      /* Cleanup HPRT */\r\n      USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\\\r\n        USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );\r\n       \r\n      /* Handle Host Port Interrupts */\r\n      HAL_HCD_Disconnect_Callback(hhcd);\r\n       USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );\r\n      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);\r\n    }\r\n    \r\n    /* Handle Host Port Interrupts */\r\n    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT))\r\n    {\r\n      HCD_Port_IRQHandler (hhcd);\r\n    }\r\n    \r\n    /* Handle Host SOF Interrupts */\r\n    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF))\r\n    {\r\n      HAL_HCD_SOF_Callback(hhcd);\r\n      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);\r\n    }\r\n          \r\n    /* Handle Host channel Interrupts */\r\n    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))\r\n    {\r\n      interrupt = USB_HC_ReadInterrupt(hhcd->Instance);\r\n      for (i = 0; i < hhcd->Init.Host_channels ; i++)\r\n      {\r\n        if (interrupt & (1 << i))\r\n        {\r\n          if ((USBx_HC(i)->HCCHAR) &  USB_OTG_HCCHAR_EPDIR)\r\n          {\r\n            HCD_HC_IN_IRQHandler (hhcd, i);\r\n          }\r\n          else\r\n          {\r\n            HCD_HC_OUT_IRQHandler (hhcd, i);\r\n          }\r\n        }\r\n      }\r\n      __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT);\r\n    } \r\n    \r\n        /* Handle Rx Queue Level Interrupts */\r\n    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL))\r\n    {\r\n      USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);\r\n      \r\n      HCD_RXQLVL_IRQHandler (hhcd);\r\n      \r\n      USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  SOF callback.\r\n  * @param  hhcd: HCD handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hhcd);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_HCD_SOF_Callback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief Connection Event callback.\r\n  * @param  hhcd: HCD handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hhcd);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_HCD_Connect_Callback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Disconnection Event callback.\r\n  * @param  hhcd: HCD handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hhcd);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_HCD_Disconnect_Callback could be implemented in the user file\r\n   */\r\n} \r\n\r\n/**\r\n  * @brief  Notify URB state change callback.\r\n  * @param  hhcd: HCD handle\r\n  * @param  chnum: Channel number.\r\n  *         This parameter can be a value from 1 to 15\r\n  * @param  urb_state:\r\n  *          This parameter can be one of these values:\r\n  *            URB_IDLE/\r\n  *            URB_DONE/\r\n  *            URB_NOTREADY/\r\n  *            URB_NYET/ \r\n  *            URB_ERROR/  \r\n  *            URB_STALL/    \r\n  * @retval None\r\n  */\r\n__weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hhcd);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions \r\n *  @brief   Management functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                      ##### Peripheral Control functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides a set of functions allowing to control the HCD data \r\n    transfers.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Start the host driver.\r\n  * @param  hhcd: HCD handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)\r\n{ \r\n  __HAL_LOCK(hhcd); \r\n  __HAL_HCD_ENABLE(hhcd);\r\n  USB_DriveVbus(hhcd->Instance, 1);  \r\n  __HAL_UNLOCK(hhcd); \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stop the host driver.\r\n  * @param  hhcd: HCD handle\r\n  * @retval HAL status\r\n  */\r\n\r\nHAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)\r\n{ \r\n  __HAL_LOCK(hhcd); \r\n  USB_StopHost(hhcd->Instance);\r\n  __HAL_UNLOCK(hhcd); \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Reset the host port.\r\n  * @param  hhcd: HCD handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)\r\n{\r\n  return (USB_ResetPort(hhcd->Instance));\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions \r\n *  @brief   Peripheral State functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                      ##### Peripheral State functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection permits to get in run-time the status of the peripheral \r\n    and the data flow.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Return the HCD handle state.\r\n  * @param  hhcd: HCD handle\r\n  * @retval HAL state\r\n  */\r\nHCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)\r\n{\r\n  return hhcd->State;\r\n}\r\n\r\n/**\r\n  * @brief  Return  URB state for a channel.\r\n  * @param  hhcd: HCD handle\r\n  * @param  chnum: Channel number.\r\n  *         This parameter can be a value from 1 to 15\r\n  * @retval URB state.\r\n  *          This parameter can be one of these values:\r\n  *            URB_IDLE/\r\n  *            URB_DONE/\r\n  *            URB_NOTREADY/\r\n  *            URB_NYET/ \r\n  *            URB_ERROR/  \r\n  *            URB_STALL\r\n  */\r\nHCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum)\r\n{\r\n  return hhcd->hc[chnum].urb_state;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Return the last host transfer size.\r\n  * @param  hhcd: HCD handle\r\n  * @param  chnum: Channel number.\r\n  *         This parameter can be a value from 1 to 15\r\n  * @retval last transfer size in byte\r\n  */\r\nuint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum)\r\n{\r\n  return hhcd->hc[chnum].xfer_count; \r\n}\r\n  \r\n/**\r\n  * @brief  Return the Host Channel state.\r\n  * @param  hhcd: HCD handle\r\n  * @param  chnum: Channel number.\r\n  *         This parameter can be a value from 1 to 15\r\n  * @retval Host channel state\r\n  *          This parameter can be one of these values:\r\n  *            HC_IDLE/\r\n  *            HC_XFRC/\r\n  *            HC_HALTED/\r\n  *            HC_NYET/ \r\n  *            HC_NAK/  \r\n  *            HC_STALL/ \r\n  *            HC_XACTERR/  \r\n  *            HC_BBLERR/  \r\n  *            HC_DATATGLERR   \r\n  */\r\nHCD_HCStateTypeDef  HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)\r\n{\r\n  return hhcd->hc[chnum].state;\r\n}\r\n\r\n/**\r\n  * @brief  Return the current Host frame number.\r\n  * @param  hhcd: HCD handle\r\n  * @retval Current Host frame number\r\n  */\r\nuint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)\r\n{\r\n  return (USB_GetCurrentFrame(hhcd->Instance));\r\n}\r\n\r\n/**\r\n  * @brief  Return the Host enumeration speed.\r\n  * @param  hhcd: HCD handle\r\n  * @retval Enumeration speed\r\n  */\r\nuint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)\r\n{\r\n  return (USB_GetHostSpeed(hhcd->Instance));\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup HCD_Private_Functions\r\n  * @{\r\n  */\r\n/**\r\n  * @brief  Handle Host Channel IN interrupt requests.\r\n  * @param  hhcd: HCD handle\r\n  * @param  chnum: Channel number.\r\n  *         This parameter can be a value from 1 to 15\r\n  * @retval none\r\n  */\r\nstatic void HCD_HC_IN_IRQHandler   (HCD_HandleTypeDef *hhcd, uint8_t chnum)\r\n{\r\n  USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;\r\n  uint32_t tmpreg = 0;\r\n  \r\n  if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_AHBERR)\r\n  {\r\n    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);\r\n    __HAL_HCD_UNMASK_HALT_HC_INT(chnum);\r\n  }  \r\n  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_ACK)\r\n  {\r\n    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);\r\n  }\r\n  \r\n  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_STALL)  \r\n  {\r\n    __HAL_HCD_UNMASK_HALT_HC_INT(chnum);\r\n    hhcd->hc[chnum].state = HC_STALL;\r\n    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);\r\n    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);    \r\n    USB_HC_Halt(hhcd->Instance, chnum);    \r\n  }\r\n  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_DTERR)\r\n  {\r\n    __HAL_HCD_UNMASK_HALT_HC_INT(chnum);\r\n    USB_HC_Halt(hhcd->Instance, chnum);  \r\n    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);    \r\n    hhcd->hc[chnum].state = HC_DATATGLERR;\r\n    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);\r\n  }    \r\n  \r\n  if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_FRMOR)\r\n  {\r\n    __HAL_HCD_UNMASK_HALT_HC_INT(chnum); \r\n    USB_HC_Halt(hhcd->Instance, chnum);  \r\n    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);\r\n  }\r\n  \r\n  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_XFRC)\r\n  {\r\n    \r\n    if (hhcd->Init.dma_enable)\r\n    {\r\n      hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].xfer_len - \\\r\n                               (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);\r\n    }\r\n    \r\n    hhcd->hc[chnum].state = HC_XFRC;\r\n    hhcd->hc[chnum].ErrCnt = 0;\r\n    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);\r\n    \r\n    \r\n    if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||\r\n        (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))\r\n    {\r\n      __HAL_HCD_UNMASK_HALT_HC_INT(chnum); \r\n      USB_HC_Halt(hhcd->Instance, chnum); \r\n      __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);\r\n      \r\n    }\r\n    else if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)\r\n    {\r\n      USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;\r\n      hhcd->hc[chnum].urb_state = URB_DONE; \r\n      HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);\r\n    }\r\n    hhcd->hc[chnum].toggle_in ^= 1;\r\n    \r\n  }\r\n  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_CHH)\r\n  {\r\n    __HAL_HCD_MASK_HALT_HC_INT(chnum); \r\n    \r\n    if(hhcd->hc[chnum].state == HC_XFRC)\r\n    {\r\n      hhcd->hc[chnum].urb_state  = URB_DONE;      \r\n    }\r\n    \r\n    else if (hhcd->hc[chnum].state == HC_STALL) \r\n    {\r\n      hhcd->hc[chnum].urb_state  = URB_STALL;\r\n    }   \r\n    \r\n    else if((hhcd->hc[chnum].state == HC_XACTERR) ||\r\n            (hhcd->hc[chnum].state == HC_DATATGLERR))\r\n    {\r\n      if(hhcd->hc[chnum].ErrCnt++ > 3)\r\n      {      \r\n        hhcd->hc[chnum].ErrCnt = 0;\r\n        hhcd->hc[chnum].urb_state = URB_ERROR;\r\n      }\r\n      else\r\n      {\r\n        hhcd->hc[chnum].urb_state = URB_NOTREADY;\r\n      }\r\n      \r\n      /* re-activate the channel  */\r\n      tmpreg = USBx_HC(chnum)->HCCHAR;\r\n      tmpreg &= ~USB_OTG_HCCHAR_CHDIS;\r\n      tmpreg |= USB_OTG_HCCHAR_CHENA;\r\n      USBx_HC(chnum)->HCCHAR = tmpreg;    \r\n    }\r\n    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);\r\n    HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);\r\n  }  \r\n  \r\n  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_TXERR)\r\n  {\r\n    __HAL_HCD_UNMASK_HALT_HC_INT(chnum); \r\n     hhcd->hc[chnum].ErrCnt++;\r\n     hhcd->hc[chnum].state = HC_XACTERR;\r\n     USB_HC_Halt(hhcd->Instance, chnum);     \r\n     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);\r\n  }\r\n  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_NAK)\r\n  {  \r\n    if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)\r\n    {\r\n      __HAL_HCD_UNMASK_HALT_HC_INT(chnum); \r\n      USB_HC_Halt(hhcd->Instance, chnum);  \r\n    }\r\n    else if  ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||\r\n         (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))\r\n    {\r\n      /* re-activate the channel  */\r\n      tmpreg = USBx_HC(chnum)->HCCHAR;\r\n      tmpreg &= ~USB_OTG_HCCHAR_CHDIS;\r\n      tmpreg |= USB_OTG_HCCHAR_CHENA;\r\n      USBx_HC(chnum)->HCCHAR = tmpreg;\r\n    }\r\n    hhcd->hc[chnum].state = HC_NAK;\r\n    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Handle Host Channel OUT interrupt requests.\r\n  * @param  hhcd: HCD handle\r\n  * @param  chnum: Channel number.\r\n  *         This parameter can be a value from 1 to 15\r\n  * @retval none\r\n  */\r\nstatic void HCD_HC_OUT_IRQHandler  (HCD_HandleTypeDef *hhcd, uint8_t chnum)\r\n{\r\n  USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;\r\n  uint32_t tmpreg = 0;\r\n  \r\n  if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_AHBERR)\r\n  {\r\n    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);\r\n    __HAL_HCD_UNMASK_HALT_HC_INT(chnum);\r\n  }  \r\n  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_ACK)\r\n  {\r\n    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);\r\n    \r\n    if( hhcd->hc[chnum].do_ping == 1)\r\n    {\r\n      hhcd->hc[chnum].state = HC_NYET;     \r\n      __HAL_HCD_UNMASK_HALT_HC_INT(chnum); \r\n      USB_HC_Halt(hhcd->Instance, chnum); \r\n      hhcd->hc[chnum].urb_state  = URB_NOTREADY;\r\n    }\r\n  }\r\n  \r\n  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_NYET)\r\n  {\r\n    hhcd->hc[chnum].state = HC_NYET;\r\n    hhcd->hc[chnum].ErrCnt= 0;    \r\n    __HAL_HCD_UNMASK_HALT_HC_INT(chnum); \r\n    USB_HC_Halt(hhcd->Instance, chnum);      \r\n    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);\r\n    \r\n  }  \r\n  \r\n  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_FRMOR)\r\n  {\r\n    __HAL_HCD_UNMASK_HALT_HC_INT(chnum); \r\n    USB_HC_Halt(hhcd->Instance, chnum);  \r\n    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);\r\n  }\r\n  \r\n  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_XFRC)\r\n  {\r\n      hhcd->hc[chnum].ErrCnt = 0;  \r\n    __HAL_HCD_UNMASK_HALT_HC_INT(chnum);\r\n    USB_HC_Halt(hhcd->Instance, chnum);   \r\n    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);\r\n    hhcd->hc[chnum].state = HC_XFRC;\r\n\r\n  }  \r\n\r\n  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_STALL)  \r\n  {\r\n    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);  \r\n    __HAL_HCD_UNMASK_HALT_HC_INT(chnum);\r\n    USB_HC_Halt(hhcd->Instance, chnum);   \r\n    hhcd->hc[chnum].state = HC_STALL;    \r\n  }\r\n\r\n  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_NAK)\r\n  {  \r\n    hhcd->hc[chnum].ErrCnt = 0;  \r\n    __HAL_HCD_UNMASK_HALT_HC_INT(chnum); \r\n    USB_HC_Halt(hhcd->Instance, chnum);   \r\n    hhcd->hc[chnum].state = HC_NAK;\r\n    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);\r\n  }\r\n\r\n  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_TXERR)\r\n  {\r\n    __HAL_HCD_UNMASK_HALT_HC_INT(chnum); \r\n    USB_HC_Halt(hhcd->Instance, chnum);      \r\n    hhcd->hc[chnum].state = HC_XACTERR;  \r\n     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);\r\n  }\r\n  \r\n  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_DTERR)\r\n  {\r\n    __HAL_HCD_UNMASK_HALT_HC_INT(chnum); \r\n    USB_HC_Halt(hhcd->Instance, chnum);      \r\n    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);\r\n    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);    \r\n    hhcd->hc[chnum].state = HC_DATATGLERR;\r\n  }\r\n  \r\n  \r\n  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_CHH)\r\n  {\r\n    __HAL_HCD_MASK_HALT_HC_INT(chnum); \r\n    \r\n    if(hhcd->hc[chnum].state == HC_XFRC)\r\n    {\r\n      hhcd->hc[chnum].urb_state  = URB_DONE;\r\n      if (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)\r\n      {\r\n        hhcd->hc[chnum].toggle_out ^= 1; \r\n      }      \r\n    }\r\n    else if (hhcd->hc[chnum].state == HC_NAK) \r\n    {\r\n      hhcd->hc[chnum].urb_state  = URB_NOTREADY;\r\n    }  \r\n    \r\n    else if (hhcd->hc[chnum].state == HC_NYET) \r\n    {\r\n      hhcd->hc[chnum].urb_state  = URB_NOTREADY;\r\n      hhcd->hc[chnum].do_ping = 0;\r\n    }   \r\n    \r\n    else if (hhcd->hc[chnum].state == HC_STALL) \r\n    {\r\n      hhcd->hc[chnum].urb_state  = URB_STALL;\r\n    } \r\n    \r\n    else if((hhcd->hc[chnum].state == HC_XACTERR) ||\r\n            (hhcd->hc[chnum].state == HC_DATATGLERR))\r\n    {\r\n      if(hhcd->hc[chnum].ErrCnt++ > 3)\r\n      {      \r\n        hhcd->hc[chnum].ErrCnt = 0;\r\n        hhcd->hc[chnum].urb_state = URB_ERROR;\r\n      }\r\n      else\r\n      {\r\n        hhcd->hc[chnum].urb_state = URB_NOTREADY;\r\n      }\r\n      \r\n      /* re-activate the channel  */\r\n      tmpreg = USBx_HC(chnum)->HCCHAR;\r\n      tmpreg &= ~USB_OTG_HCCHAR_CHDIS;\r\n      tmpreg |= USB_OTG_HCCHAR_CHENA;\r\n      USBx_HC(chnum)->HCCHAR = tmpreg;   \r\n    }\r\n    \r\n    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);\r\n    HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);  \r\n  }\r\n} \r\n\r\n/**\r\n  * @brief  Handle Rx Queue Level interrupt requests.\r\n  * @param  hhcd: HCD handle\r\n  * @retval none\r\n  */\r\nstatic void HCD_RXQLVL_IRQHandler  (HCD_HandleTypeDef *hhcd)\r\n{\r\n  USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;  \r\n  uint8_t                       channelnum =0;  \r\n  uint32_t                      pktsts;\r\n  uint32_t                      pktcnt; \r\n  uint32_t                      temp = 0;\r\n  uint32_t tmpreg = 0;\r\n  \r\n  temp = hhcd->Instance->GRXSTSP ;\r\n  channelnum = temp &  USB_OTG_GRXSTSP_EPNUM;  \r\n  pktsts = (temp &  USB_OTG_GRXSTSP_PKTSTS) >> 17;\r\n  pktcnt = (temp &  USB_OTG_GRXSTSP_BCNT) >> 4;\r\n    \r\n  switch (pktsts)\r\n  {\r\n  case GRXSTS_PKTSTS_IN:\r\n    /* Read the data into the host buffer. */\r\n    if ((pktcnt > 0) && (hhcd->hc[channelnum].xfer_buff != (void  *)0))\r\n    {  \r\n      \r\n      USB_ReadPacket(hhcd->Instance, hhcd->hc[channelnum].xfer_buff, pktcnt);\r\n     \r\n      /*manage multiple Xfer */\r\n      hhcd->hc[channelnum].xfer_buff += pktcnt;           \r\n      hhcd->hc[channelnum].xfer_count  += pktcnt;\r\n        \r\n      if((USBx_HC(channelnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0)\r\n      {\r\n        /* re-activate the channel when more packets are expected */\r\n        tmpreg = USBx_HC(channelnum)->HCCHAR;\r\n        tmpreg &= ~USB_OTG_HCCHAR_CHDIS;\r\n        tmpreg |= USB_OTG_HCCHAR_CHENA;\r\n        USBx_HC(channelnum)->HCCHAR = tmpreg;\r\n        hhcd->hc[channelnum].toggle_in ^= 1;\r\n      }\r\n    }\r\n    break;\r\n\r\n  case GRXSTS_PKTSTS_DATA_TOGGLE_ERR:\r\n    break;\r\n  case GRXSTS_PKTSTS_IN_XFER_COMP:\r\n  case GRXSTS_PKTSTS_CH_HALTED:\r\n  default:\r\n    break;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Handle Host Port interrupt requests.\r\n  * @param  hhcd: HCD handle\r\n  * @retval None\r\n  */\r\nstatic void HCD_Port_IRQHandler  (HCD_HandleTypeDef *hhcd)\r\n{\r\n  USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;  \r\n  __IO uint32_t hprt0, hprt0_dup;\r\n  \r\n  /* Handle Host Port Interrupts */\r\n  hprt0 = USBx_HPRT0;\r\n  hprt0_dup = USBx_HPRT0;\r\n  \r\n  hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\\\r\n                 USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );\r\n  \r\n  /* Check whether Port Connect detected */\r\n  if((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET)\r\n  {  \r\n    if((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)\r\n    {\r\n      USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);\r\n      HAL_HCD_Connect_Callback(hhcd);\r\n    }\r\n    hprt0_dup  |= USB_OTG_HPRT_PCDET;\r\n    \r\n  }\r\n  \r\n  /* Check whether Port Enable Changed */\r\n  if((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG)\r\n  {\r\n    hprt0_dup |= USB_OTG_HPRT_PENCHNG;\r\n    \r\n    if((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA)\r\n    {    \r\n      if(hhcd->Init.phy_itface  == USB_OTG_EMBEDDED_PHY)\r\n      {\r\n        if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17))\r\n        {\r\n          USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_6_MHZ );\r\n        }\r\n        else\r\n        {\r\n          USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );\r\n        }\r\n      }\r\n      else\r\n      {\r\n        if(hhcd->Init.speed == HCD_SPEED_FULL)\r\n        {\r\n          USBx_HOST->HFIR = (uint32_t)60000;\r\n        }\r\n      }\r\n      HAL_HCD_Connect_Callback(hhcd);\r\n      \r\n    }\r\n    else\r\n    {\r\n      /* Cleanup HPRT */\r\n      USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\\\r\n        USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );\r\n      \r\n      USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT); \r\n    }    \r\n  }\r\n  \r\n  /* Check For an overcurrent */\r\n  if((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG)\r\n  {\r\n    hprt0_dup |= USB_OTG_HPRT_POCCHNG;\r\n  }\r\n\r\n  /* Clear Port Interrupts */\r\n  USBx_HPRT0 = hprt0_dup;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n#endif /* HAL_HCD_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_i2c.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   I2C HAL module driver.\r\n  *          This file provides firmware functions to manage the following\r\n  *          functionalities of the Inter Integrated Circuit (I2C) peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + IO operation functions\r\n  *           + Peripheral State and Errors functions\r\n  *\r\n  @verbatim\r\n  ==============================================================================\r\n                        ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]\r\n    The I2C HAL driver can be used as follows:\r\n    \r\n    (#) Declare a I2C_HandleTypeDef handle structure, for example:\r\n        I2C_HandleTypeDef  hi2c;\r\n\r\n    (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:\r\n        (##) Enable the I2Cx interface clock\r\n        (##) I2C pins configuration\r\n            (+++) Enable the clock for the I2C GPIOs\r\n            (+++) Configure I2C pins as alternate function open-drain\r\n        (##) NVIC configuration if you need to use interrupt process\r\n            (+++) Configure the I2Cx interrupt priority\r\n            (+++) Enable the NVIC I2C IRQ Channel\r\n        (##) DMA Configuration if you need to use DMA process\r\n            (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream\r\n            (+++) Enable the DMAx interface clock using\r\n            (+++) Configure the DMA handle parameters\r\n            (+++) Configure the DMA Tx or Rx stream\r\n            (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle\r\n            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on\r\n                  the DMA Tx or Rx stream\r\n\r\n    (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,\r\n        Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.\r\n\r\n    (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware\r\n        (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.\r\n\r\n    (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()\r\n\r\n    (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :\r\n\r\n    *** Polling mode IO operation ***\r\n    =================================\r\n    [..]\r\n      (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()\r\n      (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()\r\n      (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()\r\n      (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()\r\n\r\n    *** Polling mode IO MEM operation ***\r\n    =====================================\r\n    [..]\r\n      (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()\r\n      (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()\r\n\r\n\r\n    *** Interrupt mode IO operation ***\r\n    ===================================\r\n    [..]\r\n      (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()\r\n      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()\r\n      (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()\r\n      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()\r\n      (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()\r\n      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()\r\n      (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()\r\n      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()\r\n      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_ErrorCallback()\r\n      (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()\r\n      (+) End of abort process, HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback()\r\n      (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.\r\n           This action will inform Master to generate a Stop condition to discard the communication.\r\n\r\n\r\n    *** Interrupt mode IO sequential operation ***\r\n    ===================================\r\n    [..]\r\n      (@) These interfaces allow to manage a sequential transfer with a repeated start condition\r\n          when a direction change during transfer\r\n    [..]\r\n      (+) A specific option field manage the different steps of a sequential transfer\r\n      (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:\r\n      (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode\r\n      (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address\r\n                            and data to transfer without a final stop condition\r\n      (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address\r\n                            and with new data to transfer if the direction change or manage only the new data to transfer\r\n                            if no direction change and without a final stop condition in both cases\r\n      (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address\r\n                            and with new data to transfer if the direction change or manage only the new data to transfer\r\n                            if no direction change and with a final stop condition in both cases\r\n\r\n      (+) Differents sequential I2C interfaces are listed below:\r\n      (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()\r\n      (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()\r\n      (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()\r\n      (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()\r\n      (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()\r\n      (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()\r\n      (+++) mean HAL_I2C_MasterTxCpltCallback() in case of previous state was master transmit\r\n      (+++) mean HAL_I2c_MasterRxCpltCallback() in case of previous state was master receive\r\n      (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()\r\n      (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can\r\n           add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).\r\n      (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()\r\n      (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()\r\n      (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()\r\n      (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()\r\n      (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()\r\n      (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_ErrorCallback()\r\n      (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()\r\n      (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()\r\n      (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.\r\n           This action will inform Master to generate a Stop condition to discard the communication.\r\n\r\n    *** Interrupt mode IO MEM operation ***\r\n    =======================================\r\n    [..]\r\n      (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using\r\n          HAL_I2C_Mem_Write_IT()\r\n      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()\r\n      (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using\r\n          HAL_I2C_Mem_Read_IT()\r\n      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()\r\n      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_ErrorCallback()\r\n\r\n    *** DMA mode IO operation ***\r\n    ==============================\r\n    [..]\r\n      (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using\r\n          HAL_I2C_Master_Transmit_DMA()\r\n      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()\r\n      (+) Receive in master mode an amount of data in non-blocking mode (DMA) using\r\n          HAL_I2C_Master_Receive_DMA()\r\n      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()\r\n      (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using\r\n          HAL_I2C_Slave_Transmit_DMA()\r\n      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()\r\n      (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using\r\n          HAL_I2C_Slave_Receive_DMA()\r\n      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()\r\n      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_ErrorCallback()\r\n      (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()\r\n      (+) End of abort process, HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback()\r\n      (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.\r\n           This action will inform Master to generate a Stop condition to discard the communication.\r\n\r\n    *** DMA mode IO MEM operation ***\r\n    =================================\r\n    [..]\r\n      (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using\r\n          HAL_I2C_Mem_Write_DMA()\r\n      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()\r\n      (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using\r\n          HAL_I2C_Mem_Read_DMA()\r\n      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()\r\n      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can\r\n           add his own code by customization of function pointer HAL_I2C_ErrorCallback()\r\n\r\n\r\n     *** I2C HAL driver macros list ***\r\n     ==================================\r\n     [..]\r\n       Below the list of most used macros in I2C HAL driver.\r\n\r\n      (+) __HAL_I2C_ENABLE: Enable the I2C peripheral\r\n      (+) __HAL_I2C_DISABLE: Disable the I2C peripheral\r\n      (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode\r\n      (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not\r\n      (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag\r\n      (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt\r\n      (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt\r\n\r\n     [..]\r\n       (@) You can refer to the I2C HAL driver header file for more useful macros\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup I2C I2C\r\n  * @brief I2C HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_I2C_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n\r\n/** @defgroup I2C_Private_Define I2C Private Define\r\n  * @{\r\n  */\r\n#define TIMING_CLEAR_MASK   ((uint32_t)0xF0FFFFFFU)  /*!<  I2C TIMING clear register Mask */\r\n#define I2C_TIMEOUT_ADDR    ((uint32_t)10000U)       /*!< 10 s  */\r\n#define I2C_TIMEOUT_BUSY    ((uint32_t)25U)          /*!< 25 ms */\r\n#define I2C_TIMEOUT_DIR     ((uint32_t)25U)          /*!< 25 ms */\r\n#define I2C_TIMEOUT_RXNE    ((uint32_t)25U)          /*!< 25 ms */\r\n#define I2C_TIMEOUT_STOPF   ((uint32_t)25U)          /*!< 25 ms */\r\n#define I2C_TIMEOUT_TC      ((uint32_t)25U)          /*!< 25 ms */\r\n#define I2C_TIMEOUT_TCR     ((uint32_t)25U)          /*!< 25 ms */\r\n#define I2C_TIMEOUT_TXIS    ((uint32_t)25U)          /*!< 25 ms */\r\n#define I2C_TIMEOUT_FLAG    ((uint32_t)25U)          /*!< 25 ms */\r\n\r\n#define MAX_NBYTE_SIZE      255U\r\n#define SlaveAddr_SHIFT     7U\r\n#define SlaveAddr_MSK       0x06U\r\n\r\n/* Private define for @ref PreviousState usage */\r\n#define I2C_STATE_MSK             ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits            */\r\n#define I2C_STATE_NONE            ((uint32_t)(HAL_I2C_MODE_NONE))                                                        /*!< Default Value                                          */\r\n#define I2C_STATE_MASTER_BUSY_TX  ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))            /*!< Master Busy TX, combinaison of State LSB and Mode enum */\r\n#define I2C_STATE_MASTER_BUSY_RX  ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))            /*!< Master Busy RX, combinaison of State LSB and Mode enum */\r\n#define I2C_STATE_SLAVE_BUSY_TX   ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))             /*!< Slave Busy TX, combinaison of State LSB and Mode enum  */\r\n#define I2C_STATE_SLAVE_BUSY_RX   ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))             /*!< Slave Busy RX, combinaison of State LSB and Mode enum  */\r\n#define I2C_STATE_MEM_BUSY_TX     ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))               /*!< Memory Busy TX, combinaison of State LSB and Mode enum */\r\n#define I2C_STATE_MEM_BUSY_RX     ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))               /*!< Memory Busy RX, combinaison of State LSB and Mode enum */\r\n\r\n\r\n/* Private define to centralize the enable/disable of Interrupts */\r\n#define I2C_XFER_TX_IT          ((uint32_t)0x00000001)\r\n#define I2C_XFER_RX_IT          ((uint32_t)0x00000002)\r\n#define I2C_XFER_LISTEN_IT      ((uint32_t)0x00000004)\r\n\r\n#define I2C_XFER_ERROR_IT       ((uint32_t)0x00000011)\r\n#define I2C_XFER_CPLT_IT        ((uint32_t)0x00000012)\r\n#define I2C_XFER_RELOAD_IT      ((uint32_t)0x00000012)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX)   ? \\\r\n                                            ((uint32_t)((__HANDLE__)->hdmatx->Instance->NDTR)) : \\\r\n                                            ((uint32_t)((__HANDLE__)->hdmarx->Instance->NDTR)))\r\n\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n\r\n/** @defgroup I2C_Private_Functions I2C Private Functions\r\n  * @{\r\n  */\r\n/* Private functions to handle DMA transfer */\r\nstatic void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);\r\nstatic void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);\r\nstatic void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);\r\nstatic void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);\r\nstatic void I2C_DMAError(DMA_HandleTypeDef *hdma);\r\nstatic void I2C_DMAAbort(DMA_HandleTypeDef *hdma);\r\n\r\n/* Private functions to handle IT transfer */\r\nstatic void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);\r\nstatic void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c);\r\nstatic void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c);\r\nstatic void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);\r\nstatic void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);\r\nstatic void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);\r\nstatic void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);\r\n\r\n/* Private functions to handle IT transfer */\r\nstatic HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);\r\nstatic HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);\r\n\r\n/* Private functions for I2C transfer IRQ handler */\r\nstatic HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);\r\nstatic HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);\r\nstatic HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);\r\nstatic HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);\r\n\r\n/* Private functions to handle flags during polling transfer */\r\nstatic HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);\r\nstatic HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);\r\nstatic HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);\r\nstatic HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);\r\nstatic HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);\r\n\r\n/* Private functions to centralize the enable/disable of Interrupts */\r\nstatic HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);\r\nstatic HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);\r\n\r\n/* Private functions to flush TXDR register */\r\nstatic void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);\r\n\r\n/* Private functions to handle  start, restart or stop a transfer */\r\nstatic void I2C_TransferConfig(I2C_HandleTypeDef *hi2c,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @defgroup I2C_Exported_Functions I2C Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions\r\n *  @brief    Initialization and Configuration functions \r\n *\r\n@verbatim\r\n ===============================================================================\r\n              ##### Initialization and de-initialization functions #####\r\n ===============================================================================\r\n    [..]  This subsection provides a set of functions allowing to initialize and\r\n          deinitialize the I2Cx peripheral:\r\n\r\n      (+) User must Implement HAL_I2C_MspInit() function in which he configures\r\n          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).\r\n\r\n      (+) Call the function HAL_I2C_Init() to configure the selected device with\r\n          the selected configuration:\r\n        (++) Clock Timing\r\n        (++) Own Address 1\r\n        (++) Addressing mode (Master, Slave)\r\n        (++) Dual Addressing mode\r\n        (++) Own Address 2\r\n        (++) Own Address 2 Mask\r\n        (++) General call mode\r\n        (++) Nostretch mode\r\n\r\n      (+) Call the function HAL_I2C_DeInit() to restore the default configuration\r\n          of the selected I2Cx peripheral.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the I2C according to the specified parameters\r\n  *         in the I2C_InitTypeDef and initialize the associated handle.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)\r\n{ \r\n  /* Check the I2C handle allocation */\r\n  if(hi2c == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\r\n  assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));\r\n  assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));\r\n  assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));\r\n  assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));\r\n  assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));\r\n  assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));\r\n  assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));\r\n\r\n  if(hi2c->State == HAL_I2C_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    hi2c->Lock = HAL_UNLOCKED;\r\n    \r\n    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */\r\n    HAL_I2C_MspInit(hi2c);\r\n  }\r\n\r\n  hi2c->State = HAL_I2C_STATE_BUSY;\r\n  \r\n  /* Disable the selected I2C peripheral */\r\n  __HAL_I2C_DISABLE(hi2c);\r\n  \r\n  /*---------------------------- I2Cx TIMINGR Configuration ------------------*/\r\n  /* Configure I2Cx: Frequency range */\r\n  hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;\r\n  \r\n  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/\r\n  /* Configure I2Cx: Own Address1 and ack own address1 mode */\r\n  hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;\r\n  if(hi2c->Init.OwnAddress1 != 0)\r\n  {\r\n    if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)\r\n    {\r\n      hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);\r\n    }\r\n    else /* I2C_ADDRESSINGMODE_10BIT */\r\n    {\r\n      hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);\r\n    }\r\n  }\r\n  \r\n  /*---------------------------- I2Cx CR2 Configuration ----------------------*/\r\n  /* Configure I2Cx: Addressing Master mode */\r\n  if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)\r\n  {\r\n    hi2c->Instance->CR2 = (I2C_CR2_ADD10);\r\n  }\r\n  /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */\r\n  hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);\r\n  \r\n  /*---------------------------- I2Cx OAR2 Configuration ---------------------*/\r\n  /* Configure I2Cx: Dual mode and Own Address2 */\r\n  hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));\r\n\r\n  /*---------------------------- I2Cx CR1 Configuration ----------------------*/\r\n  /* Configure I2Cx: Generalcall and NoStretch mode */\r\n  hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);\r\n  \r\n  /* Enable the selected I2C peripheral */\r\n  __HAL_I2C_ENABLE(hi2c);\r\n  \r\n  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r\n  hi2c->State = HAL_I2C_STATE_READY;\r\n  hi2c->PreviousState = I2C_STATE_NONE;\r\n  hi2c->Mode = HAL_I2C_MODE_NONE;\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  DeInitialize the I2C peripheral.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* Check the I2C handle allocation */\r\n  if(hi2c == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\r\n  \r\n  hi2c->State = HAL_I2C_STATE_BUSY;\r\n  \r\n  /* Disable the I2C Peripheral Clock */\r\n  __HAL_I2C_DISABLE(hi2c);\r\n  \r\n  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r\n  HAL_I2C_MspDeInit(hi2c);\r\n  \r\n  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r\n  hi2c->State = HAL_I2C_STATE_RESET;\r\n  hi2c->PreviousState = I2C_STATE_NONE;\r\n  hi2c->Mode = HAL_I2C_MODE_NONE;\r\n  \r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hi2c);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Initialize the I2C MSP.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @retval None\r\n  */\r\n__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2c);\r\n  \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_I2C_MspInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief DeInitialize the I2C MSP.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @retval None\r\n  */\r\n__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2c);\r\n  \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_I2C_MspDeInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions\r\n *  @brief   Data transfers functions \r\n *\r\n@verbatim\r\n ===============================================================================\r\n                      ##### IO operation functions #####\r\n ===============================================================================\r\n    [..]\r\n    This subsection provides a set of functions allowing to manage the I2C data\r\n    transfers.\r\n\r\n    (#) There are two modes of transfer:\r\n       (++) Blocking mode : The communication is performed in the polling mode.\r\n            The status of all data processing is returned by the same function \r\n            after finishing transfer.\r\n       (++) No-Blocking mode : The communication is performed using Interrupts\r\n            or DMA. These functions return the status of the transfer startup.\r\n            The end of the data processing will be indicated through the\r\n            dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when\r\n            using DMA mode.\r\n\r\n    (#) Blocking mode functions are :\r\n        (++) HAL_I2C_Master_Transmit()\r\n        (++) HAL_I2C_Master_Receive()\r\n        (++) HAL_I2C_Slave_Transmit()\r\n        (++) HAL_I2C_Slave_Receive()\r\n        (++) HAL_I2C_Mem_Write()\r\n        (++) HAL_I2C_Mem_Read()\r\n        (++) HAL_I2C_IsDeviceReady()\r\n\r\n    (#) No-Blocking mode functions with Interrupt are :\r\n        (++) HAL_I2C_Master_Transmit_IT()\r\n        (++) HAL_I2C_Master_Receive_IT()\r\n        (++) HAL_I2C_Slave_Transmit_IT()\r\n        (++) HAL_I2C_Slave_Receive_IT()\r\n        (++) HAL_I2C_Mem_Write_IT()\r\n        (++) HAL_I2C_Mem_Read_IT()\r\n\r\n    (#) No-Blocking mode functions with DMA are :\r\n        (++) HAL_I2C_Master_Transmit_DMA()\r\n        (++) HAL_I2C_Master_Receive_DMA()\r\n        (++) HAL_I2C_Slave_Transmit_DMA()\r\n        (++) HAL_I2C_Slave_Receive_DMA()\r\n        (++) HAL_I2C_Mem_Write_DMA()\r\n        (++) HAL_I2C_Mem_Read_DMA()\r\n\r\n    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:\r\n        (++) HAL_I2C_MemTxCpltCallback()\r\n        (++) HAL_I2C_MemRxCpltCallback()\r\n        (++) HAL_I2C_MasterTxCpltCallback()\r\n        (++) HAL_I2C_MasterRxCpltCallback()\r\n        (++) HAL_I2C_SlaveTxCpltCallback()\r\n        (++) HAL_I2C_SlaveRxCpltCallback()\r\n        (++) HAL_I2C_ErrorCallback()\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Transmits in master mode an amount of data in blocking mode.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  DevAddress: Target device address\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be sent\r\n  * @param  Timeout: Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  if(hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n    \r\n    /* Init tickstart for timeout management*/\r\n    tickstart = HAL_GetTick();\r\n    \r\n    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n    \r\n    hi2c->State     = HAL_I2C_STATE_BUSY_TX;\r\n    hi2c->Mode      = HAL_I2C_MODE_MASTER;\r\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r\n    \r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr  = pData;\r\n    hi2c->XferCount = Size;\r\n    hi2c->XferISR   = NULL;\r\n    \r\n    /* Send Slave Address */\r\n    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r\n    if(hi2c->XferCount > MAX_NBYTE_SIZE)\r\n    {\r\n      hi2c->XferSize = MAX_NBYTE_SIZE;\r\n      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);\r\n    }\r\n    else\r\n    {\r\n      hi2c->XferSize = hi2c->XferCount;\r\n      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);\r\n    }\r\n    \r\n    while(hi2c->XferSize > 0)\r\n    {\r\n      /* Wait until TXIS flag is set */\r\n      if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r\n      {\r\n        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n        {\r\n          return HAL_ERROR;\r\n        }\r\n        else\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n      /* Write data to TXDR */\r\n      hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);\r\n      hi2c->XferCount--;\r\n      hi2c->XferSize--;\r\n      \r\n      if((hi2c->XferSize == 0) && (hi2c->XferCount!=0))\r\n      {\r\n        /* Wait until TCR flag is set */\r\n        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n        \r\n        if(hi2c->XferCount > MAX_NBYTE_SIZE)\r\n        {\r\n          hi2c->XferSize = MAX_NBYTE_SIZE;\r\n          I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r\n        }\r\n        else\r\n        {\r\n          hi2c->XferSize = hi2c->XferCount;\r\n          I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r\n        }\r\n      }\r\n    }\r\n    \r\n    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r\n    /* Wait until STOPF flag is set */\r\n    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r\n    {\r\n      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n      {\r\n        return HAL_ERROR;\r\n      }\r\n      else\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n    \r\n    /* Clear STOP Flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r\n    \r\n    /* Clear Configuration Register 2 */\r\n    I2C_RESET_CR2(hi2c);\r\n    \r\n    hi2c->State = HAL_I2C_STATE_READY;\r\n    hi2c->Mode  = HAL_I2C_MODE_NONE;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Receives in master mode an amount of data in blocking mode.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  DevAddress: Target device address\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be sent\r\n  * @param  Timeout: Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  if(hi2c->State == HAL_I2C_STATE_READY)\r\n  {    \r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n    \r\n    /* Init tickstart for timeout management*/\r\n    tickstart = HAL_GetTick();\r\n    \r\n    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n    \r\n    hi2c->State     = HAL_I2C_STATE_BUSY_RX;\r\n    hi2c->Mode      = HAL_I2C_MODE_MASTER;\r\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r\n    \r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr  = pData;\r\n    hi2c->XferCount = Size;\r\n    hi2c->XferISR   = NULL;\r\n    \r\n    /* Send Slave Address */\r\n    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r\n    if(hi2c->XferCount > MAX_NBYTE_SIZE)\r\n    {\r\n      hi2c->XferSize = MAX_NBYTE_SIZE;\r\n      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);\r\n    }\r\n    else\r\n    {\r\n      hi2c->XferSize = hi2c->XferCount;\r\n      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);\r\n    }\r\n    \r\n    while(hi2c->XferSize > 0)\r\n    {\r\n      /* Wait until RXNE flag is set */\r\n      if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r\n      {\r\n        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n        {\r\n          return HAL_ERROR;\r\n        }\r\n        else\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n      \r\n      /* Read data from RXDR */\r\n      (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;\r\n      hi2c->XferSize--;\r\n      hi2c->XferCount--;\r\n      \r\n      if((hi2c->XferSize == 0) && (hi2c->XferCount != 0))\r\n      {\r\n        /* Wait until TCR flag is set */\r\n        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n        \r\n        if(hi2c->XferCount > MAX_NBYTE_SIZE)\r\n        {\r\n          hi2c->XferSize = MAX_NBYTE_SIZE;\r\n          I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r\n        }\r\n        else\r\n        {\r\n          hi2c->XferSize = hi2c->XferCount;\r\n          I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r\n        }\r\n      }\r\n    }\r\n    \r\n    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r\n    /* Wait until STOPF flag is set */\r\n    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r\n    {\r\n      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n      {\r\n        return HAL_ERROR;\r\n      }\r\n      else\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n    \r\n    /* Clear STOP Flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r\n    \r\n    /* Clear Configuration Register 2 */\r\n    I2C_RESET_CR2(hi2c);\r\n    \r\n    hi2c->State = HAL_I2C_STATE_READY;\r\n    hi2c->Mode  = HAL_I2C_MODE_NONE;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Transmits in slave mode an amount of data in blocking mode. \r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be sent\r\n  * @param  Timeout: Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  if(hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    if((pData == NULL ) || (Size == 0))\r\n    {\r\n      return  HAL_ERROR;\r\n    }\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n    \r\n    /* Init tickstart for timeout management*/\r\n    tickstart = HAL_GetTick();\r\n    \r\n    hi2c->State     = HAL_I2C_STATE_BUSY_TX;\r\n    hi2c->Mode      = HAL_I2C_MODE_SLAVE;\r\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r\n    \r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr  = pData;\r\n    hi2c->XferCount = Size;\r\n    hi2c->XferISR   = NULL;\r\n    \r\n    /* Enable Address Acknowledge */\r\n    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r\n    \r\n    /* Wait until ADDR flag is set */\r\n    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)\r\n    {\r\n      /* Disable Address Acknowledge */\r\n      hi2c->Instance->CR2 |= I2C_CR2_NACK;\r\n      return HAL_TIMEOUT;\r\n    }\r\n    \r\n    /* Clear ADDR flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);\r\n    \r\n    /* If 10bit addressing mode is selected */\r\n    if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)\r\n    {\r\n      /* Wait until ADDR flag is set */\r\n      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)\r\n      {\r\n        /* Disable Address Acknowledge */\r\n        hi2c->Instance->CR2 |= I2C_CR2_NACK;\r\n        return HAL_TIMEOUT;\r\n      }\r\n      \r\n      /* Clear ADDR flag */\r\n      __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);\r\n    }\r\n    \r\n    /* Wait until DIR flag is set Transmitter mode */\r\n    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)\r\n    {\r\n      /* Disable Address Acknowledge */\r\n      hi2c->Instance->CR2 |= I2C_CR2_NACK;\r\n      return HAL_TIMEOUT;\r\n    }\r\n    \r\n    while(hi2c->XferCount > 0)\r\n    {\r\n      /* Wait until TXIS flag is set */\r\n      if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r\n      {\r\n        /* Disable Address Acknowledge */\r\n        hi2c->Instance->CR2 |= I2C_CR2_NACK;\r\n        \r\n        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n        {\r\n          return HAL_ERROR;\r\n        }\r\n        else\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n      \r\n      /* Write data to TXDR */\r\n      hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);\r\n      hi2c->XferCount--;\r\n    }\r\n    \r\n    /* Wait until STOP flag is set */\r\n    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r\n    {\r\n      /* Disable Address Acknowledge */\r\n      hi2c->Instance->CR2 |= I2C_CR2_NACK;\r\n      \r\n      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n      {\r\n        /* Normal use case for Transmitter mode */\r\n        /* A NACK is generated to confirm the end of transfer */\r\n        hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r\n      }\r\n      else\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n    \r\n    /* Clear STOP flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);\r\n    \r\n    /* Wait until BUSY flag is reset */ \r\n    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)\r\n    {\r\n      /* Disable Address Acknowledge */\r\n      hi2c->Instance->CR2 |= I2C_CR2_NACK;\r\n      return HAL_TIMEOUT;\r\n    }\r\n    \r\n    /* Disable Address Acknowledge */\r\n    hi2c->Instance->CR2 |= I2C_CR2_NACK;\r\n    \r\n    hi2c->State = HAL_I2C_STATE_READY;\r\n    hi2c->Mode  = HAL_I2C_MODE_NONE;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Receive in slave mode an amount of data in blocking mode\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be sent\r\n  * @param  Timeout: Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  if(hi2c->State == HAL_I2C_STATE_READY)\r\n  {  \r\n    if((pData == NULL ) || (Size == 0))\r\n    {\r\n      return  HAL_ERROR;\r\n    }\r\n        /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n    \r\n    /* Init tickstart for timeout management*/\r\n    tickstart = HAL_GetTick();\r\n    \r\n    hi2c->State     = HAL_I2C_STATE_BUSY_RX;\r\n    hi2c->Mode      = HAL_I2C_MODE_SLAVE;\r\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r\n    \r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr  = pData;\r\n    hi2c->XferCount = Size;\r\n    hi2c->XferISR   = NULL;\r\n    \r\n    /* Enable Address Acknowledge */\r\n    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r\n    \r\n    /* Wait until ADDR flag is set */\r\n    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)\r\n    {\r\n      /* Disable Address Acknowledge */\r\n      hi2c->Instance->CR2 |= I2C_CR2_NACK;\r\n      return HAL_TIMEOUT;\r\n    }\r\n    \r\n    /* Clear ADDR flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);\r\n    \r\n    /* Wait until DIR flag is reset Receiver mode */\r\n    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)\r\n    {\r\n      /* Disable Address Acknowledge */\r\n      hi2c->Instance->CR2 |= I2C_CR2_NACK;\r\n      return HAL_TIMEOUT;\r\n    }\r\n    \r\n    while(hi2c->XferCount > 0)\r\n    {\r\n      /* Wait until RXNE flag is set */\r\n      if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r\n      {\r\n        /* Disable Address Acknowledge */\r\n        hi2c->Instance->CR2 |= I2C_CR2_NACK;\r\n    \r\n        /* Store Last receive data if any */\r\n        if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)\r\n        {\r\n          /* Read data from RXDR */\r\n          (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;\r\n          hi2c->XferCount--;\r\n        }\r\n\r\n        if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n        else\r\n        {\r\n          return HAL_ERROR;\r\n        }\r\n      }\r\n      \r\n      /* Read data from RXDR */\r\n      (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;\r\n      hi2c->XferCount--;\r\n    }\r\n    \r\n    /* Wait until STOP flag is set */\r\n    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r\n    {\r\n      /* Disable Address Acknowledge */\r\n      hi2c->Instance->CR2 |= I2C_CR2_NACK;\r\n      \r\n      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n      {\r\n        return HAL_ERROR;\r\n      }\r\n      else\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n    \r\n    /* Clear STOP flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);\r\n    \r\n    /* Wait until BUSY flag is reset */\r\n    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)\r\n    {\r\n      /* Disable Address Acknowledge */\r\n      hi2c->Instance->CR2 |= I2C_CR2_NACK;\r\n      return HAL_TIMEOUT;\r\n    }\r\n    \r\n    /* Disable Address Acknowledge */\r\n    hi2c->Instance->CR2 |= I2C_CR2_NACK;\r\n    \r\n    hi2c->State = HAL_I2C_STATE_READY;\r\n    hi2c->Mode  = HAL_I2C_MODE_NONE;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Transmit in master mode an amount of data in non-blocking mode with Interrupt\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  DevAddress: Target device address\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)\r\n{\r\n  uint32_t xfermode = 0;\r\n  \r\n  if(hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r\n    {\r\n      return HAL_BUSY;\r\n    }\r\n    \r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n    \r\n    hi2c->State       = HAL_I2C_STATE_BUSY_TX;\r\n    hi2c->Mode        = HAL_I2C_MODE_MASTER;\r\n    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r\n    \r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr    = pData;\r\n    hi2c->XferCount   = Size;\r\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r\n    hi2c->XferISR     = I2C_Master_ISR_IT;\r\n    \r\n    if(hi2c->XferCount > MAX_NBYTE_SIZE)\r\n    {\r\n      hi2c->XferSize = MAX_NBYTE_SIZE;\r\n      xfermode = I2C_RELOAD_MODE;\r\n    }\r\n    else\r\n    {\r\n      hi2c->XferSize = hi2c->XferCount;\r\n      xfermode = I2C_AUTOEND_MODE;\r\n    }\r\n    \r\n    /* Send Slave Address */\r\n    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */\r\n    I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c); \r\n    \r\n    /* Note : The I2C interrupts must be enabled after unlocking current process\r\n              to avoid the risk of I2C interrupt handle execution before current\r\n              process unlock */\r\n    \r\n    /* Enable ERR, TC, STOP, NACK, TXI interrupt */\r\n    /* possible to enable all of these */\r\n    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Receive in master mode an amount of data in non-blocking mode with Interrupt\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  DevAddress: Target device address\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)\r\n{\r\n  uint32_t xfermode = 0;\r\n  \r\n  if(hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r\n    {\r\n      return HAL_BUSY;\r\n    }\r\n    \r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n    \r\n    hi2c->State       = HAL_I2C_STATE_BUSY_RX;\r\n    hi2c->Mode        = HAL_I2C_MODE_MASTER;\r\n    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r\n    \r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr    = pData;\r\n    hi2c->XferCount   = Size;\r\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r\n    hi2c->XferISR     = I2C_Master_ISR_IT;\r\n    \r\n    if(hi2c->XferCount > MAX_NBYTE_SIZE)\r\n    {\r\n      hi2c->XferSize = MAX_NBYTE_SIZE;\r\n      xfermode = I2C_RELOAD_MODE;\r\n    }\r\n    else\r\n    {\r\n      hi2c->XferSize = hi2c->XferCount;\r\n      xfermode = I2C_AUTOEND_MODE;\r\n    }\r\n    \r\n    /* Send Slave Address */\r\n    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */\r\n    I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n\r\n    /* Note : The I2C interrupts must be enabled after unlocking current process\r\n              to avoid the risk of I2C interrupt handle execution before current\r\n              process unlock */\r\n    \r\n    /* Enable ERR, TC, STOP, NACK, RXI interrupt */\r\n    /* possible to enable all of these */\r\n    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Transmit in slave mode an amount of data in non-blocking mode with Interrupt\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)\r\n{\r\n  if(hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n    \r\n    hi2c->State       = HAL_I2C_STATE_BUSY_TX;\r\n    hi2c->Mode        = HAL_I2C_MODE_SLAVE;\r\n    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r\n    \r\n    /* Enable Address Acknowledge */\r\n    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r\n    \r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr    = pData;\r\n    hi2c->XferCount   = Size;\r\n    hi2c->XferSize    = hi2c->XferCount;\r\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r\n    hi2c->XferISR     = I2C_Slave_ISR_IT;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n    \r\n    /* Note : The I2C interrupts must be enabled after unlocking current process\r\n              to avoid the risk of I2C interrupt handle execution before current\r\n              process unlock */\r\n    \r\n    /* Enable ERR, TC, STOP, NACK, TXI interrupt */\r\n    /* possible to enable all of these */\r\n    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt \r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)\r\n{\r\n  if(hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n    \r\n    hi2c->State       = HAL_I2C_STATE_BUSY_RX;\r\n    hi2c->Mode        = HAL_I2C_MODE_SLAVE;\r\n    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r\n    \r\n    /* Enable Address Acknowledge */\r\n    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r\n    \r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr    = pData;\r\n    hi2c->XferCount   = Size;\r\n    hi2c->XferSize    = hi2c->XferCount;\r\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r\n    hi2c->XferISR     = I2C_Slave_ISR_IT;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n    \r\n    /* Note : The I2C interrupts must be enabled after unlocking current process\r\n              to avoid the risk of I2C interrupt handle execution before current\r\n              process unlock */\r\n    \r\n    /* Enable ERR, TC, STOP, NACK, RXI interrupt */\r\n    /* possible to enable all of these */\r\n    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Transmit in master mode an amount of data in non-blocking mode with DMA\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  DevAddress: Target device address\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)\r\n{\r\n  uint32_t xfermode = 0;\r\n  \r\n  if(hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r\n    {\r\n      return HAL_BUSY;\r\n    }\r\n    \r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n    \r\n    hi2c->State       = HAL_I2C_STATE_BUSY_TX;\r\n    hi2c->Mode        = HAL_I2C_MODE_MASTER;\r\n    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r\n    \r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr    = pData;\r\n    hi2c->XferCount   = Size;\r\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r\n    hi2c->XferISR     = I2C_Master_ISR_DMA;\r\n    \r\n    if(hi2c->XferCount > MAX_NBYTE_SIZE)\r\n    {\r\n      hi2c->XferSize = MAX_NBYTE_SIZE;\r\n      xfermode = I2C_RELOAD_MODE;\r\n    }\r\n    else\r\n    {\r\n      hi2c->XferSize = hi2c->XferCount;\r\n      xfermode = I2C_AUTOEND_MODE;\r\n    }\r\n    \r\n    /* Set the I2C DMA transfer complete callback */\r\n    hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;\r\n    \r\n    /* Set the DMA error callback */\r\n    hi2c->hdmatx->XferErrorCallback = I2C_DMAError;\r\n    \r\n    /* Set the unused DMA callbacks to NULL */\r\n    hi2c->hdmatx->XferHalfCpltCallback = NULL;\r\n    hi2c->hdmatx->XferAbortCallback = NULL;\r\n    \r\n    /* Enable the DMA channel */\r\n    HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);\r\n    \r\n    /* Send Slave Address */\r\n    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r\n    I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);\r\n    \r\n    /* Update XferCount value */\r\n    hi2c->XferCount -= hi2c->XferSize;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n    \r\n    /* Note : The I2C interrupts must be enabled after unlocking current process\r\n              to avoid the risk of I2C interrupt handle execution before current\r\n              process unlock */\r\n    /* Enable ERR and NACK interrupts */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);\r\n    \r\n    /* Enable DMA Request */\r\n    hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Receive in master mode an amount of data in non-blocking mode with DMA\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  DevAddress: Target device address\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)\r\n{\r\n  uint32_t xfermode = 0;\r\n  \r\n  if(hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r\n    {\r\n      return HAL_BUSY;\r\n    }\r\n    \r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n    \r\n    hi2c->State       = HAL_I2C_STATE_BUSY_RX;\r\n    hi2c->Mode        = HAL_I2C_MODE_MASTER;\r\n    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r\n    \r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr    = pData;\r\n    hi2c->XferCount   = Size;\r\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r\n    hi2c->XferISR     = I2C_Master_ISR_DMA;\r\n    \r\n    if(hi2c->XferCount > MAX_NBYTE_SIZE)\r\n    {\r\n      hi2c->XferSize = MAX_NBYTE_SIZE;\r\n      xfermode = I2C_RELOAD_MODE;\r\n    }\r\n    else\r\n    {\r\n      hi2c->XferSize = hi2c->XferCount;\r\n      xfermode = I2C_AUTOEND_MODE;\r\n    }\r\n    \r\n    if(hi2c->XferSize > 0)\r\n    {\r\n      /* Set the I2C DMA transfer complete callback */\r\n      hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;\r\n      \r\n      /* Set the DMA error callback */\r\n      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;\r\n      \r\n      /* Set the unused DMA callbacks to NULL */\r\n      hi2c->hdmarx->XferHalfCpltCallback = NULL;\r\n      hi2c->hdmarx->XferAbortCallback = NULL;\r\n      \r\n      /* Enable the DMA channel */\r\n      HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);\r\n      \r\n      /* Send Slave Address */\r\n      /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r\n      I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);\r\n      \r\n      /* Update XferCount value */\r\n      hi2c->XferCount -= hi2c->XferSize;\r\n      \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hi2c);\r\n      \r\n      /* Note : The I2C interrupts must be enabled after unlocking current process\r\n                to avoid the risk of I2C interrupt handle execution before current\r\n                process unlock */\r\n      /* Enable ERR and NACK interrupts */\r\n      I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);\r\n      \r\n      /* Enable DMA Request */\r\n      hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;\r\n    }\r\n    else\r\n    {\r\n      hi2c->State = HAL_I2C_STATE_READY;\r\n      hi2c->Mode = HAL_I2C_MODE_NONE;\r\n      \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hi2c);\r\n    }\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Transmit in slave mode an amount of data in non-blocking mode with DMA\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)\r\n{\r\n  if(hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    if((pData == NULL) || (Size == 0))\r\n    {\r\n      return  HAL_ERROR;\r\n    }   \r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n    \r\n    hi2c->State       = HAL_I2C_STATE_BUSY_TX;\r\n    hi2c->Mode        = HAL_I2C_MODE_SLAVE;\r\n    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r\n    \r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr    = pData;\r\n    hi2c->XferCount   = Size;\r\n    hi2c->XferSize    = hi2c->XferCount;\r\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r\n    hi2c->XferISR     = I2C_Slave_ISR_DMA;\r\n    \r\n    /* Set the I2C DMA transfer complete callback */\r\n    hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;\r\n    \r\n    /* Set the DMA error callback */\r\n    hi2c->hdmatx->XferErrorCallback = I2C_DMAError;\r\n    \r\n    /* Set the unused DMA callbacks to NULL */\r\n    hi2c->hdmatx->XferHalfCpltCallback = NULL;\r\n    hi2c->hdmatx->XferAbortCallback = NULL;\r\n    \r\n    /* Enable the DMA channel */\r\n    HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);\r\n    \r\n    /* Enable Address Acknowledge */\r\n    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n    \r\n    /* Note : The I2C interrupts must be enabled after unlocking current process\r\n              to avoid the risk of I2C interrupt handle execution before current\r\n              process unlock */\r\n    /* Enable ERR, STOP, NACK, ADDR interrupts */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r\n    \r\n    /* Enable DMA Request */\r\n    hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; \r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Receive in slave mode an amount of data in non-blocking mode with DMA\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)\r\n{\r\n  if(hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    if((pData == NULL) || (Size == 0))\r\n    {\r\n      return  HAL_ERROR;\r\n    }   \r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n    \r\n    hi2c->State       = HAL_I2C_STATE_BUSY_RX;\r\n    hi2c->Mode        = HAL_I2C_MODE_SLAVE;\r\n    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r\n    \r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr    = pData;\r\n    hi2c->XferCount   = Size;\r\n    hi2c->XferSize    = hi2c->XferCount;\r\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r\n    hi2c->XferISR     = I2C_Slave_ISR_DMA;\r\n    \r\n    /* Set the I2C DMA transfer complete callback */\r\n    hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;\r\n    \r\n    /* Set the DMA error callback */\r\n    hi2c->hdmarx->XferErrorCallback = I2C_DMAError;\r\n    \r\n    /* Set the unused DMA callbacks to NULL */\r\n    hi2c->hdmarx->XferHalfCpltCallback = NULL;\r\n    hi2c->hdmarx->XferAbortCallback = NULL;\r\n    \r\n    /* Enable the DMA channel */\r\n    HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);\r\n    \r\n    /* Enable Address Acknowledge */\r\n    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n    \r\n    /* Note : The I2C interrupts must be enabled after unlocking current process\r\n              to avoid the risk of I2C interrupt handle execution before current\r\n              process unlock */\r\n    /* Enable ERR, STOP, NACK, ADDR interrupts */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r\n    \r\n    /* Enable DMA Request */\r\n    hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n/**\r\n  * @brief  Write an amount of data in blocking mode to a specific memory address\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  DevAddress: Target device address\r\n  * @param  MemAddress: Internal memory address\r\n  * @param  MemAddSize: Size of internal memory address\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be sent\r\n  * @param  Timeout: Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r\n  \r\n  if(hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    if((pData == NULL) || (Size == 0))\r\n    {\r\n      return  HAL_ERROR;\r\n    }\r\n    \r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n    \r\n    /* Init tickstart for timeout management*/\r\n    tickstart = HAL_GetTick();\r\n    \r\n    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n    \r\n    hi2c->State     = HAL_I2C_STATE_BUSY_TX;\r\n    hi2c->Mode      = HAL_I2C_MODE_MEM;\r\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r\n    \r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr  = pData;\r\n    hi2c->XferCount = Size;\r\n    hi2c->XferISR   = NULL;\r\n    \r\n    /* Send Slave Address and Memory Address */\r\n    if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)\r\n    {\r\n      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n      {\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2c);\r\n        return HAL_ERROR;\r\n      }\r\n      else\r\n      {\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2c);\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n    \r\n    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */\r\n    if(hi2c->XferCount > MAX_NBYTE_SIZE)\r\n    {\r\n      hi2c->XferSize = MAX_NBYTE_SIZE;\r\n      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r\n    }\r\n    else\r\n    {\r\n      hi2c->XferSize = hi2c->XferCount;\r\n      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r\n    }\r\n    \r\n    do\r\n    {\r\n      /* Wait until TXIS flag is set */\r\n      if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r\n      {\r\n        if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n        {\r\n          return HAL_ERROR;\r\n        }\r\n        else\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    \r\n      /* Write data to TXDR */\r\n      hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);\r\n      hi2c->XferCount--;\r\n      hi2c->XferSize--;\r\n      \r\n      if((hi2c->XferSize == 0) && (hi2c->XferCount!=0))\r\n      {\r\n        /* Wait until TCR flag is set */\r\n        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n        \r\n        if(hi2c->XferCount > MAX_NBYTE_SIZE)\r\n        {\r\n          hi2c->XferSize = MAX_NBYTE_SIZE;\r\n          I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r\n        }\r\n        else\r\n        {\r\n          hi2c->XferSize = hi2c->XferCount;\r\n          I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r\n        }\r\n      }\r\n      \r\n    }while(hi2c->XferCount > 0);\r\n    \r\n    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r\n    /* Wait until STOPF flag is reset */ \r\n    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r\n    {\r\n      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n      {\r\n        return HAL_ERROR;\r\n      }\r\n      else\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n    \r\n    /* Clear STOP Flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r\n    \r\n    /* Clear Configuration Register 2 */\r\n    I2C_RESET_CR2(hi2c);\r\n    \r\n    hi2c->State = HAL_I2C_STATE_READY;\r\n    hi2c->Mode  = HAL_I2C_MODE_NONE;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Read an amount of data in blocking mode from a specific memory address\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  DevAddress: Target device address\r\n  * @param  MemAddress: Internal memory address\r\n  * @param  MemAddSize: Size of internal memory address\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be sent\r\n  * @param  Timeout: Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r\n  \r\n  if(hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    if((pData == NULL) || (Size == 0))\r\n    {\r\n      return  HAL_ERROR;\r\n    }\r\n    \r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n    \r\n    /* Init tickstart for timeout management*/\r\n    tickstart = HAL_GetTick();\r\n    \r\n    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n    \r\n    hi2c->State     = HAL_I2C_STATE_BUSY_RX;\r\n    hi2c->Mode      = HAL_I2C_MODE_MEM;\r\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r\n    \r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr  = pData;\r\n    hi2c->XferCount = Size;\r\n    hi2c->XferISR   = NULL;\r\n    \r\n    /* Send Slave Address and Memory Address */\r\n    if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)\r\n    {\r\n      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n      {\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2c);\r\n        return HAL_ERROR;\r\n      }\r\n      else\r\n      {\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2c);\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n    \r\n    /* Send Slave Address */\r\n    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r\n    if(hi2c->XferCount > MAX_NBYTE_SIZE)\r\n    {\r\n      hi2c->XferSize = MAX_NBYTE_SIZE;\r\n      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);\r\n    }\r\n    else\r\n    {\r\n      hi2c->XferSize = hi2c->XferCount;\r\n      I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);\r\n    }\r\n    \r\n    do\r\n    {\r\n      /* Wait until RXNE flag is set */\r\n      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n      \r\n      /* Read data from RXDR */\r\n      (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;\r\n      hi2c->XferSize--;\r\n      hi2c->XferCount--;\r\n      \r\n      if((hi2c->XferSize == 0) && (hi2c->XferCount != 0))\r\n      {\r\n        /* Wait until TCR flag is set */\r\n        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n        \r\n        if(hi2c->XferCount > MAX_NBYTE_SIZE)\r\n        {\r\n          hi2c->XferSize = MAX_NBYTE_SIZE;\r\n          I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r\n        }\r\n        else\r\n        {\r\n          hi2c->XferSize = hi2c->XferCount;\r\n          I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r\n        }\r\n      }\r\n    }while(hi2c->XferCount > 0);\r\n    \r\n    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r\n    /* Wait until STOPF flag is reset */ \r\n    if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\r\n    {\r\n      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n      {\r\n        return HAL_ERROR;\r\n      }\r\n      else\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n    \r\n    /* Clear STOP Flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r\n    \r\n    /* Clear Configuration Register 2 */\r\n    I2C_RESET_CR2(hi2c);\r\n    \r\n    hi2c->State = HAL_I2C_STATE_READY;\r\n    hi2c->Mode  = HAL_I2C_MODE_NONE;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n/**\r\n  * @brief  Write an amount of data in non-blocking mode with Interrupt to a specific memory address\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  DevAddress: Target device address\r\n  * @param  MemAddress: Internal memory address\r\n  * @param  MemAddSize: Size of internal memory address\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)\r\n{\r\n  uint32_t tickstart = 0;\r\n  uint32_t xfermode = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r\n  \r\n  if(hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    if((pData == NULL) || (Size == 0))\r\n    {\r\n      return  HAL_ERROR;\r\n    }\r\n    \r\n    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r\n    {\r\n      return HAL_BUSY;\r\n    }\r\n    \r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n    \r\n    /* Init tickstart for timeout management*/\r\n    tickstart = HAL_GetTick();\r\n    \r\n    hi2c->State       = HAL_I2C_STATE_BUSY_TX;\r\n    hi2c->Mode        = HAL_I2C_MODE_MEM;\r\n    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r\n    \r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr    = pData;\r\n    hi2c->XferCount   = Size;\r\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r\n    hi2c->XferISR     = I2C_Master_ISR_IT;\r\n    \r\n    if(hi2c->XferCount > MAX_NBYTE_SIZE)\r\n    {\r\n      hi2c->XferSize = MAX_NBYTE_SIZE;\r\n      xfermode = I2C_RELOAD_MODE;\r\n    }\r\n    else\r\n    {\r\n      hi2c->XferSize = hi2c->XferCount;\r\n      xfermode = I2C_AUTOEND_MODE;\r\n    }\r\n    \r\n    /* Send Slave Address and Memory Address */\r\n    if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)\r\n    {\r\n      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n      {\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2c);\r\n        return HAL_ERROR;\r\n      }\r\n      else\r\n      {\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2c);\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n    \r\n    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r\n    I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c); \r\n    \r\n    /* Note : The I2C interrupts must be enabled after unlocking current process \r\n              to avoid the risk of I2C interrupt handle execution before current\r\n              process unlock */\r\n    \r\n    /* Enable ERR, TC, STOP, NACK, TXI interrupt */\r\n    /* possible to enable all of these */\r\n    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Read an amount of data in non-blocking mode with Interrupt from a specific memory address\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  DevAddress: Target device address\r\n  * @param  MemAddress: Internal memory address\r\n  * @param  MemAddSize: Size of internal memory address\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)\r\n{\r\n  uint32_t tickstart = 0;\r\n  uint32_t xfermode = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r\n  \r\n  if(hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    if((pData == NULL) || (Size == 0))\r\n    {\r\n      return  HAL_ERROR;\r\n    }\r\n    \r\n    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r\n    {\r\n      return HAL_BUSY;\r\n    }\r\n    \r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n    \r\n    /* Init tickstart for timeout management*/\r\n    tickstart = HAL_GetTick();\r\n    \r\n    hi2c->State       = HAL_I2C_STATE_BUSY_RX;\r\n    hi2c->Mode        = HAL_I2C_MODE_MEM;\r\n    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r\n    \r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr    = pData;\r\n    hi2c->XferCount   = Size;\r\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r\n    hi2c->XferISR     = I2C_Master_ISR_IT;\r\n    \r\n    if(hi2c->XferCount > MAX_NBYTE_SIZE)\r\n    {\r\n      hi2c->XferSize = MAX_NBYTE_SIZE;\r\n      xfermode = I2C_RELOAD_MODE;\r\n    }\r\n    else\r\n    {\r\n      hi2c->XferSize = hi2c->XferCount;\r\n      xfermode = I2C_AUTOEND_MODE;\r\n    }\r\n    \r\n    /* Send Slave Address and Memory Address */\r\n    if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)\r\n    {\r\n      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n      {\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2c);\r\n        return HAL_ERROR;\r\n      }\r\n      else\r\n      {\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2c);\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n    \r\n    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r\n    I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n    \r\n    /* Note : The I2C interrupts must be enabled after unlocking current process\r\n              to avoid the risk of I2C interrupt handle execution before current\r\n              process unlock */\r\n    \r\n    /* Enable ERR, TC, STOP, NACK, RXI interrupt */\r\n    /* possible to enable all of these */\r\n    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }   \r\n}\r\n/**\r\n  * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  DevAddress: Target device address\r\n  * @param  MemAddress: Internal memory address\r\n  * @param  MemAddSize: Size of internal memory address\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)\r\n{\r\n  uint32_t tickstart = 0;\r\n  uint32_t xfermode = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r\n  \r\n  if(hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    if((pData == NULL) || (Size == 0))\r\n    {\r\n      return  HAL_ERROR;\r\n    }\r\n    \r\n    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r\n    {\r\n      return HAL_BUSY;\r\n    }\r\n    \r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n    \r\n    /* Init tickstart for timeout management*/\r\n    tickstart = HAL_GetTick();\r\n    \r\n    hi2c->State       = HAL_I2C_STATE_BUSY_TX;\r\n    hi2c->Mode        = HAL_I2C_MODE_MEM;\r\n    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r\n    \r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr    = pData;\r\n    hi2c->XferCount   = Size;\r\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r\n    hi2c->XferISR     = I2C_Master_ISR_DMA;\r\n    \r\n    if(hi2c->XferCount > MAX_NBYTE_SIZE)\r\n    {\r\n      hi2c->XferSize = MAX_NBYTE_SIZE;\r\n      xfermode = I2C_RELOAD_MODE;\r\n    }\r\n    else\r\n    {\r\n      hi2c->XferSize = hi2c->XferCount;\r\n      xfermode = I2C_AUTOEND_MODE;\r\n    }\r\n    \r\n    /* Send Slave Address and Memory Address */\r\n    if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)\r\n    {\r\n      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n      {\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2c);\r\n        return HAL_ERROR;\r\n      }\r\n      else\r\n      {\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2c);\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n    \r\n    /* Set the I2C DMA transfer complete callback */\r\n    hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;\r\n    \r\n    /* Set the DMA error callback */\r\n    hi2c->hdmatx->XferErrorCallback = I2C_DMAError;\r\n    \r\n    /* Set the unused DMA callbacks to NULL */\r\n    hi2c->hdmatx->XferHalfCpltCallback = NULL;\r\n    hi2c->hdmatx->XferAbortCallback = NULL;\r\n    \r\n    /* Enable the DMA channel */\r\n    HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);\r\n    \r\n    /* Send Slave Address */\r\n    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r\n    I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);\r\n    \r\n    /* Update XferCount value */\r\n    hi2c->XferCount -= hi2c->XferSize;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n    \r\n    /* Note : The I2C interrupts must be enabled after unlocking current process\r\n              to avoid the risk of I2C interrupt handle execution before current\r\n              process unlock */\r\n    /* Enable ERR and NACK interrupts */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);\r\n    \r\n    /* Enable DMA Request */\r\n    hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Reads an amount of data in non-blocking mode with DMA from a specific memory address.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  DevAddress: Target device address\r\n  * @param  MemAddress: Internal memory address\r\n  * @param  MemAddSize: Size of internal memory address\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be read\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)\r\n{\r\n  uint32_t tickstart = 0;\r\n  uint32_t xfermode = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\r\n  \r\n  if(hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    if((pData == NULL) || (Size == 0))\r\n    {\r\n      return  HAL_ERROR;\r\n    }\r\n    \r\n    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r\n    {\r\n      return HAL_BUSY;\r\n    }\r\n    \r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n    \r\n    /* Init tickstart for timeout management*/\r\n    tickstart = HAL_GetTick();\r\n    \r\n    hi2c->State       = HAL_I2C_STATE_BUSY_RX;\r\n    hi2c->Mode        = HAL_I2C_MODE_MEM;\r\n    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\r\n    \r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr    = pData;\r\n    hi2c->XferCount   = Size;\r\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r\n    hi2c->XferISR     = I2C_Master_ISR_DMA;\r\n    \r\n    if(hi2c->XferCount > MAX_NBYTE_SIZE)\r\n    {\r\n      hi2c->XferSize = MAX_NBYTE_SIZE;\r\n      xfermode = I2C_RELOAD_MODE;\r\n    }\r\n    else\r\n    {\r\n      hi2c->XferSize = hi2c->XferCount;\r\n      xfermode = I2C_AUTOEND_MODE;\r\n    }\r\n    \r\n    /* Send Slave Address and Memory Address */\r\n    if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)\r\n    {\r\n      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n      {\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2c);\r\n        return HAL_ERROR;\r\n      }\r\n      else\r\n      {\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2c);\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n    \r\n    /* Set the I2C DMA transfer complete callback */\r\n    hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;\r\n    \r\n    /* Set the DMA error callback */\r\n    hi2c->hdmarx->XferErrorCallback = I2C_DMAError;\r\n    \r\n    /* Set the unused DMA callbacks to NULL */\r\n    hi2c->hdmarx->XferHalfCpltCallback = NULL;\r\n    hi2c->hdmarx->XferAbortCallback = NULL;\r\n    \r\n    /* Enable the DMA channel */\r\n    HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);\r\n    \r\n    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */\r\n    I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);\r\n    \r\n    /* Update XferCount value */\r\n    hi2c->XferCount -= hi2c->XferSize;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n    \r\n    /* Enable DMA Request */\r\n    hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;\r\n    \r\n    /* Note : The I2C interrupts must be enabled after unlocking current process\r\n              to avoid the risk of I2C interrupt handle execution before current\r\n              process unlock */\r\n    /* Enable ERR and NACK interrupts */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Checks if target device is ready for communication.\r\n  * @note   This function is used with Memory devices\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  DevAddress: Target device address\r\n  * @param  Trials: Number of trials\r\n  * @param  Timeout: Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)\r\n{  \r\n  uint32_t tickstart = 0;\r\n  \r\n  __IO uint32_t I2C_Trials = 0;\r\n  \r\n  if(hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)\r\n    {\r\n      return HAL_BUSY;\r\n    }\r\n    \r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n    \r\n    hi2c->State = HAL_I2C_STATE_BUSY;\r\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r\n    \r\n    do\r\n    {\r\n      /* Generate Start */\r\n      hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress);\r\n      \r\n      /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */\r\n      /* Wait until STOPF flag is set or a NACK flag is set*/\r\n      tickstart = HAL_GetTick();\r\n      while((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT))\r\n      {\r\n      \tif(Timeout != HAL_MAX_DELAY)\r\n      \t{\r\n          if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n          {\r\n            /* Device is ready */\r\n            hi2c->State = HAL_I2C_STATE_READY;\r\n            /* Process Unlocked */\r\n            __HAL_UNLOCK(hi2c);\r\n            return HAL_TIMEOUT;\r\n          }\r\n        } \r\n      }\r\n      \r\n      /* Check if the NACKF flag has not been set */\r\n      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)\r\n      {\r\n        /* Wait until STOPF flag is reset */ \r\n        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n        \r\n        /* Clear STOP Flag */\r\n        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r\n        \r\n        /* Device is ready */\r\n        hi2c->State = HAL_I2C_STATE_READY;\r\n        \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2c);\r\n        \r\n        return HAL_OK;\r\n      }\r\n      else\r\n      {\r\n        /* Wait until STOPF flag is reset */ \r\n        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n        \r\n        /* Clear NACK Flag */\r\n        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r\n        \r\n        /* Clear STOP Flag, auto generated with autoend*/\r\n        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r\n      }\r\n      \r\n      /* Check if the maximum allowed number of trials has been reached */\r\n      if (I2C_Trials++ == Trials)\r\n      {\r\n        /* Generate Stop */\r\n        hi2c->Instance->CR2 |= I2C_CR2_STOP;\r\n        \r\n        /* Wait until STOPF flag is reset */ \r\n        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n        \r\n        /* Clear STOP Flag */\r\n        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r\n      }\r\n    }while(I2C_Trials < Trials);\r\n    \r\n    hi2c->State = HAL_I2C_STATE_READY;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n    \r\n    return HAL_TIMEOUT;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.\r\n  * @note   This interface allow to manage repeated start condition when a direction change during transfer\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  DevAddress: Target device address\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be sent\r\n  * @param  XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r\n{\r\n  uint32_t xfermode = 0;\r\n  uint32_t xferrequest = I2C_GENERATE_START_WRITE;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r\n  \r\n  if(hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n    \r\n    hi2c->State     = HAL_I2C_STATE_BUSY_TX;\r\n    hi2c->Mode      = HAL_I2C_MODE_MASTER;\r\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r\n    \r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr    = pData;\r\n    hi2c->XferCount   = Size;\r\n    hi2c->XferOptions = XferOptions;\r\n    hi2c->XferISR     = I2C_Master_ISR_IT;\r\n    \r\n    /* If size > MAX_NBYTE_SIZE, use reload mode */\r\n    if(hi2c->XferCount > MAX_NBYTE_SIZE)\r\n    {\r\n      hi2c->XferSize = MAX_NBYTE_SIZE;\r\n      xfermode = I2C_RELOAD_MODE;\r\n    }\r\n    else\r\n    {\r\n      hi2c->XferSize = hi2c->XferCount;\r\n      xfermode = hi2c->XferOptions;\r\n      \r\n      /* If transfer direction not change, do not generate Restart Condition */\r\n      /* Mean Previous state is same as current state */\r\n      if(hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_TX)\r\n      {\r\n        xferrequest = I2C_NO_STARTSTOP;\r\n      }\r\n    }\r\n    \r\n    /* Send Slave Address and set NBYTES to write */\r\n    I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c); \r\n    \r\n    /* Note : The I2C interrupts must be enabled after unlocking current process\r\n              to avoid the risk of I2C interrupt handle execution before current\r\n              process unlock */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt\r\n  * @note   This interface allow to manage repeated start condition when a direction change during transfer\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  DevAddress: Target device address\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be sent\r\n  * @param  XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r\n{\r\n  uint32_t xfermode = 0;\r\n  uint32_t xferrequest = I2C_GENERATE_START_READ;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r\n  \r\n  if(hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n    \r\n    hi2c->State     = HAL_I2C_STATE_BUSY_RX;\r\n    hi2c->Mode      = HAL_I2C_MODE_MASTER;\r\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r\n    \r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr    = pData;\r\n    hi2c->XferCount   = Size;\r\n    hi2c->XferOptions = XferOptions;\r\n    hi2c->XferISR     = I2C_Master_ISR_IT;\r\n    \r\n    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */\r\n    if(hi2c->XferCount > MAX_NBYTE_SIZE)\r\n    {\r\n      hi2c->XferSize = MAX_NBYTE_SIZE;\r\n      xfermode = I2C_RELOAD_MODE;\r\n    }\r\n    else\r\n    {\r\n      hi2c->XferSize = hi2c->XferCount;\r\n      xfermode = hi2c->XferOptions;\r\n      \r\n      /* If transfer direction not change, do not generate Restart Condition */\r\n      /* Mean Previous state is same as current state */\r\n      if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)\r\n      {\r\n        xferrequest = I2C_NO_STARTSTOP;\r\n      }\r\n    }\r\n    \r\n    /* Send Slave Address and set NBYTES to read */\r\n    I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, xferrequest);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c); \r\n    \r\n    /* Note : The I2C interrupts must be enabled after unlocking current process\r\n              to avoid the risk of I2C interrupt handle execution before current\r\n              process unlock */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt\r\n  * @note   This interface allow to manage repeated start condition when a direction change during transfer\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be sent\r\n  * @param  XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r\n  \r\n  if(hi2c->State == HAL_I2C_STATE_LISTEN)\r\n  {\r\n    if((pData == NULL) || (Size == 0))\r\n    {\r\n      return  HAL_ERROR;\r\n    }\r\n    \r\n    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */\r\n    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);\r\n    \r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n    \r\n    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;\r\n    hi2c->Mode      = HAL_I2C_MODE_SLAVE;\r\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r\n    \r\n    /* Enable Address Acknowledge */\r\n    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r\n    \r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr    = pData;\r\n    hi2c->XferCount   = Size;\r\n    hi2c->XferSize    = hi2c->XferCount;\r\n    hi2c->XferOptions = XferOptions;\r\n    hi2c->XferISR     = I2C_Slave_ISR_IT;\r\n    \r\n    if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)\r\n    {\r\n      /* Clear ADDR flag after prepare the transfer parameters */\r\n      /* This action will generate an acknowledge to the Master */\r\n      __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);\r\n    }\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c); \r\n    \r\n    /* Note : The I2C interrupts must be enabled after unlocking current process\r\n    to avoid the risk of I2C interrupt handle execution before current\r\n    process unlock */\r\n    /* REnable ADDR interrupt */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt\r\n  * @note   This interface allow to manage repeated start condition when a direction change during transfer\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be sent\r\n  * @param  XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\r\n  \r\n  if(hi2c->State == HAL_I2C_STATE_LISTEN)\r\n  {\r\n    if((pData == NULL) || (Size == 0))\r\n    {\r\n      return  HAL_ERROR;\r\n    }\r\n    \r\n    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */\r\n    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);\r\n    \r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n    \r\n    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;\r\n    hi2c->Mode      = HAL_I2C_MODE_SLAVE;\r\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r\n    \r\n    /* Enable Address Acknowledge */\r\n    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;\r\n    \r\n    /* Prepare transfer parameters */\r\n    hi2c->pBuffPtr    = pData;\r\n    hi2c->XferCount   = Size;\r\n    hi2c->XferSize    = hi2c->XferCount;\r\n    hi2c->XferOptions = XferOptions;\r\n    hi2c->XferISR     = I2C_Slave_ISR_IT;\r\n    \r\n    if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)\r\n    {\r\n      /* Clear ADDR flag after prepare the transfer parameters */\r\n      /* This action will generate an acknowledge to the Master */\r\n      __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);\r\n    }\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n    \r\n    /* Note : The I2C interrupts must be enabled after unlocking current process\r\n    to avoid the risk of I2C interrupt handle execution before current\r\n    process unlock */\r\n    /* REnable ADDR interrupt */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Enable the Address listen mode with Interrupt.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)\r\n{\r\n  if(hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    hi2c->State = HAL_I2C_STATE_LISTEN;\r\n    hi2c->XferISR = I2C_Slave_ISR_IT;\r\n    \r\n    /* Enable the Address Match interrupt */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Disable the Address listen mode with Interrupt.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* Declaration of tmp to prevent undefined behavior of volatile usage */\r\n  uint32_t tmp;\r\n  \r\n  /* Disable Address listen mode only if a transfer is not ongoing */\r\n  if(hi2c->State == HAL_I2C_STATE_LISTEN)\r\n  {\r\n    tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;\r\n    hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);\r\n    hi2c->State = HAL_I2C_STATE_READY;\r\n    hi2c->Mode = HAL_I2C_MODE_NONE;\r\n    hi2c->XferISR = NULL;\r\n    \r\n    /* Disable the Address Match interrupt */\r\n    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Abort a master I2C IT or DMA process communication with Interrupt.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  DevAddress: Target device address\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)\r\n{\r\n  if(hi2c->Mode == HAL_I2C_MODE_MASTER)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n    \r\n    /* Disable Interrupts */\r\n    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);\r\n    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);\r\n    \r\n    /* Set State at HAL_I2C_STATE_ABORT */\r\n    hi2c->State = HAL_I2C_STATE_ABORT;\r\n    \r\n    /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */\r\n    /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */\r\n    I2C_TransferConfig(hi2c, 0, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n    \r\n    /* Note : The I2C interrupts must be enabled after unlocking current process \r\n              to avoid the risk of I2C interrupt handle execution before current\r\n              process unlock */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    /* Wrong usage of abort function */\r\n    /* This function should be used only in case of abort monitored by master device */\r\n    return HAL_ERROR;\r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks\r\n * @{\r\n */   \r\n\r\n/**\r\n  * @brief  This function handles I2C event interrupt request.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @retval None\r\n  */\r\nvoid HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* Get current IT Flags and IT sources value */\r\n  uint32_t itflags   = READ_REG(hi2c->Instance->ISR);\r\n  uint32_t itsources = READ_REG(hi2c->Instance->CR1);\r\n  \r\n  /* I2C events treatment -------------------------------------*/\r\n  if(hi2c->XferISR != NULL)\r\n  {\r\n    hi2c->XferISR(hi2c, itflags, itsources);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  This function handles I2C error interrupt request.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @retval None\r\n  */\r\nvoid HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)\r\n{\r\n  uint32_t itflags   = READ_REG(hi2c->Instance->ISR);\r\n  uint32_t itsources = READ_REG(hi2c->Instance->CR1);\r\n  \r\n  /* I2C Bus error interrupt occurred ------------------------------------*/\r\n  if(((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))\r\n  {\r\n    hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;\r\n    \r\n    /* Clear BERR flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);\r\n  }\r\n  \r\n  /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/\r\n  if(((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))\r\n  {\r\n    hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;\r\n    \r\n    /* Clear OVR flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);\r\n  }\r\n  \r\n  /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/\r\n  if(((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))\r\n  {\r\n    hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;\r\n    \r\n    /* Clear ARLO flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);\r\n  }\r\n  \r\n  /* Call the Error Callback in case of Error detected */\r\n  if((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) !=  HAL_I2C_ERROR_NONE)\r\n  {\r\n    I2C_ITError(hi2c, hi2c->ErrorCode);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Master Tx Transfer completed callback.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @retval None\r\n  */\r\n__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2c);\r\n  \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_I2C_MasterTxCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Master Rx Transfer completed callback.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @retval None\r\n  */\r\n__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2c);\r\n  \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_I2C_MasterRxCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/** @brief  Slave Tx Transfer completed callback.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @retval None\r\n  */\r\n__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2c);\r\n  \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Slave Rx Transfer completed callback.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @retval None\r\n  */\r\n__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2c);\r\n  \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Slave Address Match callback.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  TransferDirection: Master request Transfer Direction (Write/Read), value of @ref I2C_XFEROPTIONS\r\n  * @param  AddrMatchCode: Address Match Code\r\n  * @retval None\r\n  */\r\n__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2c);\r\n  UNUSED(TransferDirection);\r\n  UNUSED(AddrMatchCode);\r\n  \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_I2C_AddrCallback() could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Listen Complete callback.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @retval None\r\n  */\r\n__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2c);\r\n  \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_I2C_ListenCpltCallback() could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Memory Tx Transfer completed callback.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @retval None\r\n  */\r\n__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2c);\r\n  \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_I2C_MemTxCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Memory Rx Transfer completed callback.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @retval None\r\n  */\r\n__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2c);\r\n  \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_I2C_MemRxCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  I2C error callback.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @retval None\r\n  */\r\n__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2c);\r\n  \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_I2C_ErrorCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  I2C abort callback.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @retval None\r\n  */\r\n__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2c);\r\n  \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_I2C_AbortCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions\r\n *  @brief   Peripheral State, Mode and Error functions\r\n *\r\n@verbatim\r\n ===============================================================================\r\n            ##### Peripheral State, Mode and Error functions #####\r\n ===============================================================================\r\n    [..]\r\n    This subsection permit to get in run-time the status of the peripheral\r\n    and the data flow.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Return the I2C handle state.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @retval HAL state\r\n  */\r\nHAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* Return I2C handle state */\r\n  return hi2c->State;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the I2C Master, Slave, Memory or no mode.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *         the configuration information for I2C module\r\n  * @retval HAL mode\r\n  */\r\nHAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)\r\n{\r\n  return hi2c->Mode;\r\n}\r\n\r\n/**\r\n* @brief  Return the I2C error code.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *              the configuration information for the specified I2C.\r\n* @retval I2C Error Code\r\n*/\r\nuint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)\r\n{\r\n  return hi2c->ErrorCode;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup I2C_Private_Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  ITFlags: Interrupt flags to handle.\r\n  * @param  ITSources: Interrupt sources enabled.\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) \r\n{\r\n  uint16_t devaddress = 0;\r\n\r\n  /* Process Locked */\r\n  __HAL_LOCK(hi2c);\r\n  \r\n  if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))\r\n  {\r\n    /* Clear NACK Flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r\n    \r\n    /* Set corresponding Error Code */\r\n    /* No need to generate STOP, it is automatically done */\r\n    /* Error callback will be send during stop flag treatment */\r\n    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r\n    \r\n    /* Flush TX register */\r\n    I2C_Flush_TXDR(hi2c);\r\n  }\r\n  else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))\r\n  {\r\n    /* Read data from RXDR */\r\n    (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;\r\n    hi2c->XferSize--;\r\n    hi2c->XferCount--;\r\n  }\r\n  else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))\r\n  {\r\n    /* Write data to TXDR */\r\n    hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);\r\n    hi2c->XferSize--;\r\n    hi2c->XferCount--;\t\r\n  }\r\n  else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))\r\n  {\r\n    if((hi2c->XferSize == 0) && (hi2c->XferCount != 0))\r\n    {\r\n      devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);\r\n      \r\n      if(hi2c->XferCount > MAX_NBYTE_SIZE)\r\n      {\r\n        hi2c->XferSize = MAX_NBYTE_SIZE;\r\n        I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);\r\n      }\r\n      else\r\n      {\r\n        hi2c->XferSize = hi2c->XferCount;\r\n        if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)\r\n        {\r\n          I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);\r\n        }\r\n        else\r\n        {\r\n          I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);\r\n        }\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* Call TxCpltCallback() if no stop mode is set */\r\n      if((I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)&&(hi2c->Mode == HAL_I2C_MODE_MASTER))\r\n      {\r\n        /* Call I2C Master Sequential complete process */\r\n        I2C_ITMasterSequentialCplt(hi2c);\r\n      }\r\n      else\r\n      {\r\n        /* Wrong size Status regarding TCR flag event */\r\n        /* Call the corresponding callback to inform upper layer of End of Transfer */\r\n        I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);\r\n      }\r\n    }\r\n  }\r\n  else if(((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))\r\n  {\r\n    if(hi2c->XferCount == 0)\r\n    {\r\n      if((I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)&&(hi2c->Mode == HAL_I2C_MODE_MASTER))\r\n      {\r\n        /* Call I2C Master Sequential complete process */\r\n        I2C_ITMasterSequentialCplt(hi2c);\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* Wrong size Status regarding TC flag event */\r\n      /* Call the corresponding callback to inform upper layer of End of Transfer */\r\n      I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);\r\n    }\r\n  }\r\n  \r\n  if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))\r\n  {\r\n    /* Call I2C Master complete process */\r\n    I2C_ITMasterCplt(hi2c, ITFlags);\r\n  }\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hi2c);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  ITFlags: Interrupt flags to handle.\r\n  * @param  ITSources: Interrupt sources enabled.\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) \r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hi2c);\r\n  \r\n  if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))\r\n  {\r\n    /* Check that I2C transfer finished */\r\n    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */\r\n    /* Mean XferCount == 0*/\r\n    /* So clear Flag NACKF only */\r\n    if(hi2c->XferCount == 0)\r\n    {\r\n      if(((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \\\r\n        (hi2c->State == HAL_I2C_STATE_LISTEN))\r\n      {\r\n        /* Call I2C Listen complete process */\r\n        I2C_ITListenCplt(hi2c, ITFlags);\r\n      }\r\n      else if((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN))\r\n      {\r\n        /* Clear NACK Flag */\r\n        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r\n        \r\n        /* Flush TX register */\r\n        I2C_Flush_TXDR(hi2c);\r\n        \r\n        /* Last Byte is Transmitted */\r\n        /* Call I2C Slave Sequential complete process */\r\n        I2C_ITSlaveSequentialCplt(hi2c);\r\n      }\r\n      else\r\n      {\r\n        /* Clear NACK Flag */\r\n        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/\r\n      /* Clear NACK Flag */\r\n      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r\n      \r\n      /* Set ErrorCode corresponding to a Non-Acknowledge */\r\n      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r\n    }\r\n  }\r\n  else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))\r\n  {\r\n    if(hi2c->XferCount > 0)\r\n    {\r\n      /* Read data from RXDR */\r\n      (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;\r\n      hi2c->XferSize--;\r\n      hi2c->XferCount--;\r\n    }\r\n    \r\n    if((hi2c->XferCount == 0) && \\\r\n       (hi2c->XferOptions != I2C_NO_OPTION_FRAME))\r\n    {\r\n      /* Call I2C Slave Sequential complete process */\r\n      I2C_ITSlaveSequentialCplt(hi2c);\r\n   }\r\n  }\r\n  else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))\r\n  {\r\n    I2C_ITAddrCplt(hi2c, ITFlags);\r\n  }\r\n  else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))\r\n  {\r\n    /* Write data to TXDR only if XferCount not reach \"0\" */\r\n    /* A TXIS flag can be set, during STOP treatment      */\r\n    /* Check if all Datas have already been sent */\r\n    /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */\r\n    if(hi2c->XferCount > 0)\r\n    {\r\n      /* Write data to TXDR */\r\n      hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);\r\n      hi2c->XferCount--;\r\n      hi2c->XferSize--;\r\n    }\r\n    else\r\n    {\r\n      if((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME))\r\n      {\r\n        /* Last Byte is Transmitted */\r\n        /* Call I2C Slave Sequential complete process */\r\n        I2C_ITSlaveSequentialCplt(hi2c);\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Check if STOPF is set */\r\n  if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))\r\n  {\r\n    /* Call I2C Slave complete process */\r\n    I2C_ITSlaveCplt(hi2c, ITFlags);\r\n  }\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hi2c);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  ITFlags: Interrupt flags to handle.\r\n  * @param  ITSources: Interrupt sources enabled.\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) \r\n{\r\n  uint16_t devaddress = 0;\r\n  uint32_t xfermode = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hi2c);\r\n  \r\n  if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))\r\n  {\r\n    /* Clear NACK Flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r\n    \r\n    /* Set corresponding Error Code */\r\n    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r\n    \r\n    /* No need to generate STOP, it is automatically done */\r\n    /* But enable STOP interrupt, to treat it */\r\n    /* Error callback will be send during stop flag treatment */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);\r\n    \r\n    /* Flush TX register */\r\n    I2C_Flush_TXDR(hi2c);\r\n  }\r\n  else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))\r\n  {\r\n    /* Disable TC interrupt */\r\n    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);\r\n    \r\n    if(hi2c->XferCount != 0)\r\n    {\r\n      /* Recover Slave address */\r\n      devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);\r\n      \r\n      /* Prepare the new XferSize to transfer */\r\n      if(hi2c->XferCount > MAX_NBYTE_SIZE)\r\n      {\r\n        hi2c->XferSize = MAX_NBYTE_SIZE;\r\n        xfermode = I2C_RELOAD_MODE;\r\n      }\r\n      else\r\n      {\r\n        hi2c->XferSize = hi2c->XferCount;\r\n        xfermode = I2C_AUTOEND_MODE;\r\n      }\r\n      \r\n      /* Set the new XferSize in Nbytes register */\r\n      I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);\r\n      \r\n      /* Update XferCount value */\r\n      hi2c->XferCount -= hi2c->XferSize;\r\n      \r\n      /* Enable DMA Request */\r\n      if(hi2c->State == HAL_I2C_STATE_BUSY_RX)\r\n      {\r\n        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;\r\n      }\r\n      else\r\n      {\r\n        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* Wrong size Status regarding TCR flag event */\r\n      /* Call the corresponding callback to inform upper layer of End of Transfer */\r\n      I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);\r\n    }\r\n  }\r\n  else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))\r\n  {\r\n    /* Call I2C Master complete process */\r\n    I2C_ITMasterCplt(hi2c, ITFlags);\r\n  }\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hi2c);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  ITFlags: Interrupt flags to handle.\r\n  * @param  ITSources: Interrupt sources enabled.\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) \r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hi2c);\r\n  \r\n  if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))\r\n  {\r\n    /* Check that I2C transfer finished */\r\n    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */\r\n    /* Mean XferCount == 0 */\r\n    /* So clear Flag NACKF only */\r\n    if(I2C_GET_DMA_REMAIN_DATA(hi2c) == 0)\r\n    {\r\n      /* Clear NACK Flag */\r\n      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r\n    }\r\n    else\r\n    {\r\n      /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/\r\n      /* Clear NACK Flag */\r\n      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r\n      \r\n      /* Set ErrorCode corresponding to a Non-Acknowledge */\r\n      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r\n    }\r\n  }\r\n  else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))\r\n  {\r\n    /* Clear ADDR flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r\n  }\r\n  else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))\r\n  {\r\n    /* Call I2C Slave complete process */\r\n    I2C_ITSlaveCplt(hi2c, ITFlags);\r\n  }\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hi2c);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Master sends target device address followed by internal memory address for write request.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  DevAddress: Target device address\r\n  * @param  MemAddress: Internal memory address\r\n  * @param  MemAddSize: Size of internal memory address\r\n  * @param  Timeout: Timeout duration\r\n  * @param  Tickstart Tick start value\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)\r\n{\r\n  I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);\r\n  \r\n  /* Wait until TXIS flag is set */\r\n  if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)\r\n  {\r\n    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n    else\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  \r\n  /* If Memory address size is 8Bit */\r\n  if(MemAddSize == I2C_MEMADD_SIZE_8BIT)\r\n  {\r\n    /* Send Memory Address */\r\n    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);\r\n  }\r\n  /* If Memory address size is 16Bit */\r\n  else\r\n  {\r\n    /* Send MSB of Memory Address */\r\n    hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);\r\n    \r\n    /* Wait until TXIS flag is set */\r\n    if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)\r\n    {\r\n      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n      {\r\n        return HAL_ERROR;\r\n      }\r\n      else\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n    \r\n    /* Send LSB of Memory Address */\r\n    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);\r\n  }\r\n  \r\n  /* Wait until TCR flag is set */\r\n  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)\r\n  {\r\n    return HAL_TIMEOUT;\r\n  }\r\n  \r\nreturn HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Master sends target device address followed by internal memory address for read request.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  DevAddress: Target device address\r\n  * @param  MemAddress: Internal memory address\r\n  * @param  MemAddSize: Size of internal memory address\r\n  * @param  Timeout: Timeout duration\r\n  * @param  Tickstart Tick start value\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)\r\n{\r\n  I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);\r\n  \r\n  /* Wait until TXIS flag is set */\r\n  if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)\r\n  {\r\n    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n    else\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  \r\n  /* If Memory address size is 8Bit */\r\n  if(MemAddSize == I2C_MEMADD_SIZE_8BIT)\r\n  {\r\n    /* Send Memory Address */\r\n    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);\r\n  }\r\n  /* If Memory address size is 16Bit */\r\n  else\r\n  {\r\n    /* Send MSB of Memory Address */\r\n    hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);\r\n    \r\n    /* Wait until TXIS flag is set */\r\n    if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)\r\n    {\r\n      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)\r\n      {\r\n        return HAL_ERROR;\r\n      }\r\n      else\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n    \r\n    /* Send LSB of Memory Address */\r\n    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);\r\n  }\r\n  \r\n  /* Wait until TC flag is set */\r\n  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)\r\n  {\r\n    return HAL_TIMEOUT;\r\n  }\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  I2C Address complete process callback.\r\n  * @param  hi2c: I2C handle.\r\n  * @param  ITFlags: Interrupt flags to handle.\r\n  * @retval None\r\n  */\r\nstatic void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)\r\n{\r\n  uint8_t transferdirection = 0;\r\n  uint16_t slaveaddrcode = 0;\r\n  uint16_t ownadd1code = 0;\r\n  uint16_t ownadd2code = 0;\r\n  \r\n  /* In case of Listen state, need to inform upper layer of address match code event */\r\n  if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)\r\n  {\r\n    transferdirection = I2C_GET_DIR(hi2c);\r\n    slaveaddrcode     = I2C_GET_ADDR_MATCH(hi2c);\r\n    ownadd1code       = I2C_GET_OWN_ADDRESS1(hi2c);\r\n    ownadd2code       = I2C_GET_OWN_ADDRESS2(hi2c);\r\n    \r\n    /* If 10bits addressing mode is selected */\r\n    if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)\r\n    {\r\n      if((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))\r\n      {\r\n        slaveaddrcode = ownadd1code;\r\n        hi2c->AddrEventCount++;\r\n        if(hi2c->AddrEventCount == 2)\r\n        {\r\n          /* Reset Address Event counter  */\r\n          hi2c->AddrEventCount = 0;\r\n          \r\n          /* Clear ADDR flag */\r\n          __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hi2c);\r\n          \r\n          /* Call Slave Addr callback */\r\n          HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);\r\n        }\r\n      }\r\n      else\r\n      {\r\n        slaveaddrcode = ownadd2code;\r\n        \r\n        /* Disable ADDR Interrupts */\r\n        I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r\n        \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2c);\r\n        \r\n        /* Call Slave Addr callback */\r\n        HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);\r\n      }\r\n    }\r\n    /* else 7 bits addressing mode is selected */\r\n    else\r\n    {\r\n      /* Disable ADDR Interrupts */\r\n      I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);\r\n      \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hi2c);\r\n      \r\n      /* Call Slave Addr callback */\r\n      HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);\r\n    }\r\n  }\r\n  /* Else clear address flag only */\r\n  else\r\n  {\r\n    /* Clear ADDR flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  I2C Master sequential complete process.\r\n  * @param  hi2c: I2C handle.\r\n  * @retval None\r\n  */\r\nstatic void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* Reset I2C handle mode */\r\n  hi2c->Mode = HAL_I2C_MODE_NONE;\r\n  \r\n  /* No Generate Stop, to permit restart mode */\r\n  /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */\r\n  if (hi2c->State == HAL_I2C_STATE_BUSY_TX)\r\n  {\r\n    hi2c->State         = HAL_I2C_STATE_READY;\r\n    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;\r\n    hi2c->XferISR       = NULL;\r\n    \r\n    /* Disable Interrupts */\r\n    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n    \r\n    /* Call the corresponding callback to inform upper layer of End of Transfer */\r\n    HAL_I2C_MasterTxCpltCallback(hi2c);\r\n  }\r\n  /* hi2c->State == HAL_I2C_STATE_BUSY_RX */\r\n  else\r\n  {\r\n    hi2c->State         = HAL_I2C_STATE_READY;\r\n    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;\r\n    hi2c->XferISR       = NULL;\r\n    \r\n    /* Disable Interrupts */\r\n    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n    \r\n    /* Call the corresponding callback to inform upper layer of End of Transfer */\r\n    HAL_I2C_MasterRxCpltCallback(hi2c);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  I2C Slave sequential complete process.\r\n  * @param  hi2c: I2C handle.\r\n  * @retval None\r\n  */\r\nstatic void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* Reset I2C handle mode */\r\n  hi2c->Mode = HAL_I2C_MODE_NONE;\r\n  \r\n  if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)\r\n  {\r\n    /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */\r\n    hi2c->State         = HAL_I2C_STATE_LISTEN;\r\n    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;\r\n    \r\n    /* Disable Interrupts */\r\n    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n    \r\n    /* Call the Tx complete callback to inform upper layer of the end of transmit process */\r\n    HAL_I2C_SlaveTxCpltCallback(hi2c);\r\n  }\r\n  \r\n  else if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)\r\n  {\r\n    /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */\r\n    hi2c->State         = HAL_I2C_STATE_LISTEN;\r\n    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;\r\n    \r\n    /* Disable Interrupts */\r\n    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n    \r\n    /* Call the Rx complete callback to inform upper layer of the end of receive process */\r\n    HAL_I2C_SlaveRxCpltCallback(hi2c);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  I2C Master complete process.\r\n  * @param  hi2c: I2C handle.\r\n  * @param  ITFlags: Interrupt flags to handle.\r\n  * @retval None\r\n  */\r\nstatic void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)\r\n{\r\n  /* Clear STOP Flag */\r\n  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r\n  \r\n  /* Clear Configuration Register 2 */\r\n  I2C_RESET_CR2(hi2c);\r\n  \r\n  /* Reset handle parameters */\r\n  hi2c->PreviousState = I2C_STATE_NONE;\r\n  hi2c->XferISR       = NULL;\r\n  hi2c->XferOptions   = I2C_NO_OPTION_FRAME;\r\n  \r\n  if((ITFlags & I2C_FLAG_AF) != RESET)\r\n  {\r\n    /* Clear NACK Flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r\n    \r\n    /* Set acknowledge error code */\r\n    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r\n  }\r\n  \r\n  /* Flush TX register */\r\n  I2C_Flush_TXDR(hi2c);\r\n  \r\n  /* Disable Interrupts */\r\n  I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT| I2C_XFER_RX_IT);\r\n  \r\n  /* Call the corresponding callback to inform upper layer of End of Transfer */\r\n  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)\r\n  {\r\n    /* Call the corresponding callback to inform upper layer of End of Transfer */\r\n    I2C_ITError(hi2c, hi2c->ErrorCode);\r\n  }\r\n  /* hi2c->State == HAL_I2C_STATE_BUSY_TX */\r\n  else if(hi2c->State == HAL_I2C_STATE_BUSY_TX)\r\n  {\r\n    hi2c->State = HAL_I2C_STATE_READY;\r\n    \r\n    if (hi2c->Mode == HAL_I2C_MODE_MEM)\r\n    {\r\n      hi2c->Mode = HAL_I2C_MODE_NONE;\r\n      \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hi2c);\r\n      \r\n      /* Call the corresponding callback to inform upper layer of End of Transfer */\r\n      HAL_I2C_MemTxCpltCallback(hi2c);\r\n    }\r\n    else\r\n    {\r\n      hi2c->Mode = HAL_I2C_MODE_NONE;\r\n      \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hi2c);\r\n      \r\n      /* Call the corresponding callback to inform upper layer of End of Transfer */\r\n      HAL_I2C_MasterTxCpltCallback(hi2c);\r\n    }\r\n  }\r\n  /* hi2c->State == HAL_I2C_STATE_BUSY_RX */\r\n  else if(hi2c->State == HAL_I2C_STATE_BUSY_RX)\r\n  {\r\n    hi2c->State = HAL_I2C_STATE_READY;\r\n    \r\n    if (hi2c->Mode == HAL_I2C_MODE_MEM)\r\n    {\r\n      hi2c->Mode = HAL_I2C_MODE_NONE;\r\n      \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hi2c);\r\n      \r\n      HAL_I2C_MemRxCpltCallback(hi2c);\r\n    }\r\n    else\r\n    {\r\n      hi2c->Mode = HAL_I2C_MODE_NONE;\r\n      \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hi2c);\r\n      \r\n      HAL_I2C_MasterRxCpltCallback(hi2c);\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  I2C Slave complete process.\r\n  * @param  hi2c: I2C handle.\r\n  * @param  ITFlags: Interrupt flags to handle.\r\n  * @retval None\r\n  */\r\nstatic void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)\r\n{\r\n  /* Clear STOP Flag */\r\n  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r\n  \r\n  /* Clear ADDR flag */\r\n  __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);\r\n  \r\n  /* Disable all interrupts */\r\n  I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);\r\n  \r\n  /* Disable Address Acknowledge */\r\n  hi2c->Instance->CR2 |= I2C_CR2_NACK;\r\n  \r\n  /* Clear Configuration Register 2 */\r\n  I2C_RESET_CR2(hi2c);\r\n  \r\n  /* Flush TX register */\r\n  I2C_Flush_TXDR(hi2c);\r\n  \r\n  /* If a DMA is ongoing, Update handle size context */\r\n  if(((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) ||\r\n     ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN))\r\n  {\r\n    if((hi2c->XferSize - I2C_GET_DMA_REMAIN_DATA(hi2c)) != hi2c->XferSize)\r\n    {\r\n      hi2c->XferSize = I2C_GET_DMA_REMAIN_DATA(hi2c);\r\n      hi2c->XferCount += hi2c->XferSize;\r\n      \r\n      /* Set ErrorCode corresponding to a Non-Acknowledge */\r\n      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r\n    }\r\n  }\r\n  \r\n  /* Store Last receive data if any */\r\n  if(((ITFlags & I2C_FLAG_RXNE) != RESET))\r\n  {\r\n    /* Read data from RXDR */\r\n    (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;\r\n    \r\n    if((hi2c->XferSize > 0))\r\n    {\r\n      hi2c->XferSize--;\r\n      hi2c->XferCount--;\r\n      \r\n      /* Set ErrorCode corresponding to a Non-Acknowledge */\r\n      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r\n    }\r\n  }\r\n  \r\n  hi2c->PreviousState = I2C_STATE_NONE;\r\n  hi2c->Mode = HAL_I2C_MODE_NONE;\r\n  hi2c->XferISR = NULL;\r\n  \r\n  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)\r\n  {\r\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r\n    hi2c->State = HAL_I2C_STATE_READY;\r\n    \r\n    /* Call the corresponding callback to inform upper layer of End of Transfer */\r\n    I2C_ITError(hi2c, hi2c->ErrorCode);\r\n  }\r\n  else if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)\r\n  {\r\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r\n    hi2c->State = HAL_I2C_STATE_READY;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n    \r\n    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */\r\n    HAL_I2C_ListenCpltCallback(hi2c);\r\n  }\r\n  /* Call the corresponding callback to inform upper layer of End of Transfer */\r\n  else if(hi2c->State == HAL_I2C_STATE_BUSY_RX)\r\n  {\r\n    hi2c->State = HAL_I2C_STATE_READY;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n    \r\n    /* Call the Slave Rx Complete callback */\r\n    HAL_I2C_SlaveRxCpltCallback(hi2c);\r\n  }\r\n  else\r\n  {\r\n    hi2c->State = HAL_I2C_STATE_READY;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n    \r\n    /* Call the Slave Tx Complete callback */\r\n    HAL_I2C_SlaveTxCpltCallback(hi2c);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  I2C Listen complete process.\r\n  * @param  hi2c: I2C handle.\r\n  * @param  ITFlags: Interrupt flags to handle.\r\n  * @retval None\r\n  */\r\nstatic void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)\r\n{\r\n  /* Reset handle parameters */\r\n  hi2c->XferOptions = I2C_NO_OPTION_FRAME;\r\n  hi2c->PreviousState = I2C_STATE_NONE;\r\n  hi2c->State = HAL_I2C_STATE_READY;\r\n  hi2c->Mode = HAL_I2C_MODE_NONE;\r\n  hi2c->XferISR = NULL;\r\n  \r\n  /* Store Last receive data if any */\r\n  if(((ITFlags & I2C_FLAG_RXNE) != RESET))\r\n  {\r\n    /* Read data from RXDR */\r\n    (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;\r\n    \r\n    if((hi2c->XferSize > 0))\r\n    {\r\n      hi2c->XferSize--;\r\n      hi2c->XferCount--;\r\n      \r\n      /* Set ErrorCode corresponding to a Non-Acknowledge */\r\n      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\r\n    }\r\n  }\r\n  \r\n  /* Disable all Interrupts*/\r\n  I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);\r\n  \r\n  /* Clear NACK Flag */\r\n  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hi2c);\r\n  \r\n  /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */\r\n  HAL_I2C_ListenCpltCallback(hi2c);\r\n}\r\n\r\n/**\r\n  * @brief  I2C interrupts error process.\r\n  * @param  hi2c: I2C handle.\r\n  * @param  ErrorCode: Error code to handle.\r\n  * @retval None\r\n  */\r\nstatic void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)\r\n{\r\n  /* Reset handle parameters */\r\n  hi2c->Mode          = HAL_I2C_MODE_NONE;\r\n  hi2c->XferOptions   = I2C_NO_OPTION_FRAME;\r\n  hi2c->XferCount     = 0;\r\n  \r\n  /* Set new error code */\r\n  hi2c->ErrorCode |= ErrorCode;\r\n  \r\n  /* Disable Interrupts */\r\n  if((hi2c->State == HAL_I2C_STATE_LISTEN)         ||\r\n     (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) ||\r\n     (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))\r\n  {\r\n    /* Disable all interrupts, except interrupts related to LISTEN state */\r\n    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);\r\n    \r\n    /* keep HAL_I2C_STATE_LISTEN if set */\r\n    hi2c->State         = HAL_I2C_STATE_LISTEN;\r\n    hi2c->PreviousState = I2C_STATE_NONE;\r\n    hi2c->XferISR       = I2C_Slave_ISR_IT;\r\n  }\r\n  else\r\n  {\r\n    /* Disable all interrupts */\r\n    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);\r\n    \r\n    /* Set HAL_I2C_STATE_READY */\r\n    hi2c->State         = HAL_I2C_STATE_READY;\r\n    hi2c->PreviousState = I2C_STATE_NONE;\r\n    hi2c->XferISR       = NULL;\r\n  }\r\n  \r\n  /* Abort DMA TX transfer if any */\r\n  if((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)\r\n  {\r\n    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;\r\n    \r\n    /* Set the I2C DMA Abort callback : \r\n       will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\r\n    hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n    \r\n    /* Abort DMA TX */\r\n    if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)\r\n    {\r\n      /* Call Directly XferAbortCallback function in case of error */\r\n      hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);\r\n    }\r\n  }\r\n  /* Abort DMA RX transfer if any */\r\n  else if((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)\r\n  {\r\n    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;\r\n    \r\n    /* Set the I2C DMA Abort callback : \r\n       will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\r\n    hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n    \r\n    /* Abort DMA RX */\r\n    if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)\r\n    {\r\n      /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */\r\n      hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);\r\n    }\r\n  }\r\n  else if(hi2c->ErrorCode == HAL_I2C_ERROR_ABORT)\r\n  {\r\n    hi2c->ErrorCode &= ~HAL_I2C_ERROR_ABORT;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n    \r\n    /* Call the corresponding callback to inform upper layer of End of Transfer */\r\n    HAL_I2C_AbortCpltCallback(hi2c);\r\n  }\r\n  else\r\n  {\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n    \r\n    /* Call the corresponding callback to inform upper layer of End of Transfer */\r\n    HAL_I2C_ErrorCallback(hi2c);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  I2C Tx data register flush process.\r\n  * @param  hi2c: I2C handle.\r\n  * @retval None\r\n  */\r\nstatic void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)\r\n{\r\n  /* If a pending TXIS flag is set */\r\n  /* Write a dummy data in TXDR to clear it */\r\n  if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)\r\n  {\r\n     hi2c->Instance->TXDR = 0x00;\r\n  }\r\n  \r\n  /* Flush TX register if not empty */\r\n  if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)\r\n  {\r\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  DMA I2C master transmit process complete callback.\r\n  * @param  hdma: DMA handle\r\n  * @retval None\r\n  */\r\nstatic void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n  \r\n  /* Disable DMA Request */\r\n  hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;\r\n  \r\n  /* If last transfer, enable STOP interrupt */\r\n  if(hi2c->XferCount == 0)\r\n  {\r\n    /* Enable STOP interrupt */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);\r\n  }\r\n  /* else prepare a new DMA transfer and enable TCReload interrupt */\r\n  else\r\n  {\r\n    /* Update Buffer pointer */\r\n    hi2c->pBuffPtr += hi2c->XferSize;\r\n    \r\n    /* Set the XferSize to transfer */\r\n    if(hi2c->XferCount > MAX_NBYTE_SIZE)\r\n    {\r\n      hi2c->XferSize = MAX_NBYTE_SIZE;\r\n    }\r\n    else\r\n    {\r\n      hi2c->XferSize = hi2c->XferCount;\r\n    }\r\n    \r\n    /* Enable the DMA channel */\r\n    HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);\r\n    \r\n    /* Enable TC interrupts */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  DMA I2C slave transmit process complete callback.\r\n  * @param  hdma: DMA handle\r\n  * @retval None\r\n  */\r\nstatic void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  /* No specific action, Master fully manage the generation of STOP condition */\r\n  /* Mean that this generation can arrive at any time, at the end or during DMA process */\r\n  /* So STOP condition should be manage through Interrupt treatment */\r\n}\r\n\r\n/**\r\n  * @brief DMA I2C master receive process complete callback.\r\n  * @param  hdma: DMA handle\r\n  * @retval None\r\n  */\r\nstatic void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n  \r\n  /* Disable DMA Request */\r\n  hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;\r\n  \r\n  /* If last transfer, enable STOP interrupt */\r\n  if(hi2c->XferCount == 0)\r\n  {\r\n    /* Enable STOP interrupt */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);\r\n  }\r\n  /* else prepare a new DMA transfer and enable TCReload interrupt */\r\n  else\r\n  {\r\n    /* Update Buffer pointer */\r\n    hi2c->pBuffPtr += hi2c->XferSize;\r\n    \r\n    /* Set the XferSize to transfer */\r\n    if(hi2c->XferCount > MAX_NBYTE_SIZE)\r\n    {\r\n      hi2c->XferSize = MAX_NBYTE_SIZE;\r\n    }\r\n    else\r\n    {\r\n      hi2c->XferSize = hi2c->XferCount;\r\n    }\r\n    \r\n    /* Enable the DMA channel */\r\n    HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);\r\n    \r\n    /* Enable TC interrupts */\r\n    I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  DMA I2C slave receive process complete callback.\r\n  * @param hdma: DMA handle\r\n  * @retval None\r\n  */\r\nstatic void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  /* No specific action, Master fully manage the generation of STOP condition */\r\n  /* Mean that this generation can arrive at any time, at the end or during DMA process */\r\n  /* So STOP condition should be manage through Interrupt treatment */\r\n}\r\n\r\n/**\r\n  * @brief  DMA I2C communication error callback.\r\n  * @param hdma: DMA handle\r\n  * @retval None\r\n  */\r\nstatic void I2C_DMAError(DMA_HandleTypeDef *hdma)\r\n{\r\n  I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  \r\n  /* Disable Acknowledge */\r\n  hi2c->Instance->CR2 |= I2C_CR2_NACK;\r\n  \r\n  /* Call the corresponding callback to inform upper layer of End of Transfer */\r\n  I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);\r\n}\r\n\r\n/**\r\n  * @brief DMA I2C communication abort callback\r\n  *        (To be called at end of DMA Abort procedure).\r\n  * @param hdma: DMA handle.\r\n  * @retval None\r\n  */\r\nstatic void I2C_DMAAbort(DMA_HandleTypeDef *hdma)\r\n{\r\n  I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  \r\n  /* Disable Acknowledge */\r\n  hi2c->Instance->CR2 |= I2C_CR2_NACK;\r\n  \r\n  /* Reset AbortCpltCallback */\r\n  hi2c->hdmatx->XferAbortCallback = NULL;\r\n  hi2c->hdmarx->XferAbortCallback = NULL;\r\n  \r\n  /* Check if come from abort from user */\r\n  if(hi2c->ErrorCode == HAL_I2C_ERROR_ABORT)\r\n  {\r\n    hi2c->ErrorCode &= ~HAL_I2C_ERROR_ABORT;\r\n    \r\n    /* Call the corresponding callback to inform upper layer of End of Transfer */\r\n    HAL_I2C_AbortCpltCallback(hi2c);\r\n  }\r\n  else\r\n  {\r\n    /* Call the corresponding callback to inform upper layer of End of Transfer */\r\n    HAL_I2C_ErrorCallback(hi2c);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  This function handles I2C Communication Timeout.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  Flag: Specifies the I2C flag to check.\r\n  * @param  Status: The new Flag status (SET or RESET).\r\n  * @param  Timeout: Timeout duration\r\n  * @param  Tickstart: Tick start value\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)\r\n{\r\n  while((__HAL_I2C_GET_FLAG(hi2c, Flag) ? SET : RESET) == Status)\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - Tickstart ) > Timeout))\r\n      {\r\n        hi2c->State= HAL_I2C_STATE_READY;\r\n        hi2c->Mode = HAL_I2C_MODE_NONE;\r\n        \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2c);\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  This function handles I2C Communication Timeout for specific usage of TXIS flag.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  Timeout: Timeout duration\r\n  * @param  Tickstart: Tick start value\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)\r\n{\r\n  while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)\r\n  {\r\n    /* Check if a NACK is detected */\r\n    if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n    \r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout))\r\n      {\r\n        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r\n        hi2c->State= HAL_I2C_STATE_READY;\r\n        hi2c->Mode = HAL_I2C_MODE_NONE;\r\n        \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2c);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  Timeout: Timeout duration\r\n  * @param  Tickstart: Tick start value\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)\r\n{\r\n  while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)\r\n  {\r\n    /* Check if a NACK is detected */\r\n    if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n    \r\n    /* Check for the Timeout */\r\n    if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout))\r\n    {\r\n      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r\n      hi2c->State= HAL_I2C_STATE_READY;\r\n      hi2c->Mode = HAL_I2C_MODE_NONE;\r\n      \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hi2c);\r\n      \r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  Timeout: Timeout duration\r\n  * @param  Tickstart: Tick start value\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)\r\n{\r\n  while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)\r\n  {\r\n    /* Check if a NACK is detected */\r\n    if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n    \r\n    /* Check if a STOPF is detected */\r\n    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)\r\n    {\r\n      /* Clear STOP Flag */\r\n      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r\n      \r\n      /* Clear Configuration Register 2 */\r\n      I2C_RESET_CR2(hi2c);\r\n      \r\n      hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\r\n      hi2c->State= HAL_I2C_STATE_READY;\r\n      hi2c->Mode = HAL_I2C_MODE_NONE;\r\n      \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hi2c);\r\n      \r\n      return HAL_ERROR;\r\n    }\r\n    \r\n    /* Check for the Timeout */\r\n    if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout))\r\n    {\r\n      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\r\n      hi2c->State= HAL_I2C_STATE_READY;\r\n      \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hi2c);\r\n      \r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  This function handles Acknowledge failed detection during an I2C Communication.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  Timeout: Timeout duration\r\n  * @param  Tickstart: Tick start value\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)\r\n{\r\n  if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)\r\n  {\r\n    /* Wait until STOP Flag is reset */\r\n    /* AutoEnd should be initiate after AF */\r\n    while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)\r\n    {\r\n      /* Check for the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n      if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout))\r\n        {\r\n          hi2c->State= HAL_I2C_STATE_READY;\r\n          hi2c->Mode = HAL_I2C_MODE_NONE;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hi2c);\r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n    \r\n    /* Clear NACKF Flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\r\n    \r\n    /* Clear STOP Flag */\r\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\r\n    \r\n    /* Flush TX register */\r\n    I2C_Flush_TXDR(hi2c);\r\n    \r\n    /* Clear Configuration Register 2 */\r\n    I2C_RESET_CR2(hi2c);\r\n    \r\n    hi2c->ErrorCode = HAL_I2C_ERROR_AF;\r\n    hi2c->State= HAL_I2C_STATE_READY;\r\n    hi2c->Mode = HAL_I2C_MODE_NONE;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n    \r\n    return HAL_ERROR;\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).\r\n  * @param  hi2c: I2C handle.\r\n  * @param  DevAddress: Specifies the slave address to be programmed.\r\n  * @param  Size: Specifies the number of bytes to be programmed.\r\n  *   This parameter must be a value between 0 and 255.\r\n  * @param  Mode: New state of the I2C START condition generation.\r\n  *   This parameter can be a value of @ref I2C_RELOAD_END_MODE.\r\n  * @param  Request: New state of the I2C START condition generation.\r\n  *   This parameter can be a value of I2C_START_STOP_MODE.\r\n  * @retval None\r\n  */\r\nstatic void I2C_TransferConfig(I2C_HandleTypeDef *hi2c,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)\r\n{\r\n  uint32_t tmpreg = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\r\n  assert_param(IS_TRANSFER_MODE(Mode));\r\n  assert_param(IS_TRANSFER_REQUEST(Request));\r\n  \r\n  /* Get the CR2 register value */\r\n  tmpreg = hi2c->Instance->CR2;\r\n  \r\n  /* clear tmpreg specific bits */\r\n  tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));\r\n  \r\n  /* update tmpreg */\r\n  tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \\\r\n            (uint32_t)Mode | (uint32_t)Request);\r\n  \r\n  /* update CR2 register */\r\n  hi2c->Instance->CR2 = tmpreg;\r\n}\r\n\r\n/**\r\n  * @brief  Manage the enabling of Interrupts.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  InterruptRequest: Value of @ref I2C_Interrupt_configuration_definition.\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)\r\n{\r\n  uint32_t tmpisr = 0;\r\n  \r\n  if((hi2c->XferISR == I2C_Master_ISR_DMA) || \\\r\n     (hi2c->XferISR == I2C_Slave_ISR_DMA))\r\n  {\r\n    if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)\r\n    {\r\n      /* Enable ERR, STOP, NACK and ADDR interrupts */\r\n      tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;\r\n    }\r\n    \r\n    if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)\r\n    {\r\n      /* Enable ERR and NACK interrupts */\r\n      tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;\r\n    }\r\n    \r\n    if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)\r\n    {\r\n      /* Enable STOP interrupts */\r\n      tmpisr |= I2C_IT_STOPI;\r\n    }\r\n    \r\n    if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)\r\n    {\r\n      /* Enable TC interrupts */\r\n      tmpisr |= I2C_IT_TCI;\r\n    }\r\n  }\r\n  else\r\n  {\r\n    if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)\r\n    {\r\n      /* Enable ERR, STOP, NACK, and ADDR interrupts */\r\n      tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;\r\n    }\r\n    \r\n    if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)\r\n    {\r\n      /* Enable ERR, TC, STOP, NACK and RXI interrupts */\r\n      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;\r\n    }\r\n    \r\n    if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)\r\n    {\r\n      /* Enable ERR, TC, STOP, NACK and TXI interrupts */\r\n      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;\r\n    }\r\n    \r\n    if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)\r\n    {\r\n      /* Enable STOP interrupts */\r\n      tmpisr |= I2C_IT_STOPI;\r\n    }\r\n  }\r\n  \r\n  /* Enable interrupts only at the end */\r\n  /* to avoid the risk of I2C interrupt handle execution before */\r\n  /* all interrupts requested done */\r\n  __HAL_I2C_ENABLE_IT(hi2c, tmpisr);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Manage the disabling of Interrupts.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2C.\r\n  * @param  InterruptRequest: Value of @ref I2C_Interrupt_configuration_definition.\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)\r\n{\r\n  uint32_t tmpisr = 0;\r\n  \r\n  if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)\r\n  {\r\n    /* Disable TC and TXI interrupts */\r\n    tmpisr |= I2C_IT_TCI | I2C_IT_TXI;\r\n    \r\n    if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)\r\n    {\r\n      /* Disable NACK and STOP interrupts */\r\n      tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;\r\n    }\r\n  }\r\n  \r\n  if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)\r\n  {\r\n    /* Disable TC and RXI interrupts */\r\n    tmpisr |= I2C_IT_TCI | I2C_IT_RXI;\r\n    \r\n    if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)\r\n    {\r\n      /* Disable NACK and STOP interrupts */\r\n      tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;\r\n    }\r\n  }\r\n  \r\n  if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)\r\n  {\r\n    /* Disable ADDR, NACK and STOP interrupts */\r\n    tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;\r\n  }\r\n  \r\n  if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)\r\n  {\r\n    /* Enable ERR and NACK interrupts */\r\n    tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;\r\n  }\r\n  \r\n  if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)\r\n  {\r\n    /* Enable STOP interrupts */\r\n    tmpisr |= I2C_IT_STOPI;\r\n  }\r\n  \r\n  if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)\r\n  {\r\n    /* Enable TC interrupts */\r\n    tmpisr |= I2C_IT_TCI;\r\n  }\r\n  \r\n  /* Disable interrupts only at the end */\r\n  /* to avoid a breaking situation like at \"t\" time */\r\n  /* all disable interrupts request are not done */\r\n  __HAL_I2C_DISABLE_IT(hi2c, tmpisr);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_I2C_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_i2c_ex.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   I2C Extended HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of I2C Extended peripheral:\r\n  *           + Extended features functions\r\n  *\r\n  @verbatim\r\n  ==============================================================================\r\n               ##### I2C peripheral Extended features  #####\r\n  ==============================================================================\r\n\r\n  [..] Comparing to other previous devices, the I2C interface for STM32F7XX\r\n       devices contains the following additional features\r\n\r\n       (+) Possibility to disable or enable Analog Noise Filter\r\n       (+) Use of a configured Digital Noise Filter\r\n       (+) Disable or enable Fast Mode Plus (available only for STM32F76xxx/STM32F77xxx \r\n           devices)\r\n\r\n                     ##### How to use this driver #####\r\n  ==============================================================================\r\n  [..] This driver provides functions to:\r\n    (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()\r\n    (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()\r\n    (#) Configure the enable or disable of fast mode plus driving capability using the functions :\r\n          (++) HAL_I2CEx_EnableFastModePlus()\r\n          (++) HAL_I2CEx_DisbleFastModePlus()\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup I2CEx I2C Extended HAL module driver\r\n  * @brief I2C Extended HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_I2C_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions\r\n  * @brief    Extended features functions\r\n *\r\n@verbatim\r\n ===============================================================================\r\n                      ##### Extended features functions #####\r\n ===============================================================================\r\n    [..] This section provides functions allowing to:\r\n      (+) Configure Noise Filters\r\n      (+) Configure Fast Mode Plus\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Configure I2C Analog noise filter.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2Cx peripheral.\r\n  * @param  AnalogFilter: New state of the Analog filter.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\r\n  assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));\r\n  \r\n  if(hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n    \r\n    hi2c->State = HAL_I2C_STATE_BUSY;\r\n    \r\n    /* Disable the selected I2C peripheral */\r\n    __HAL_I2C_DISABLE(hi2c);\r\n    \r\n    /* Reset I2Cx ANOFF bit */\r\n    hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);\r\n    \r\n    /* Set analog filter bit*/\r\n    hi2c->Instance->CR1 |= AnalogFilter;\r\n    \r\n    __HAL_I2C_ENABLE(hi2c);\r\n    \r\n    hi2c->State = HAL_I2C_STATE_READY;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Configure I2C Digital noise filter.\r\n  * @param  hi2c: Pointer to a I2C_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified I2Cx peripheral.\r\n  * @param  DigitalFilter: Coefficient of digital noise filter between 0x00 and 0x0F.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)\r\n{\r\n  uint32_t tmpreg = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\r\n  assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));\r\n  \r\n  if(hi2c->State == HAL_I2C_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2c);\r\n    \r\n    hi2c->State = HAL_I2C_STATE_BUSY;\r\n    \r\n    /* Disable the selected I2C peripheral */\r\n    __HAL_I2C_DISABLE(hi2c);\r\n    \r\n    /* Get the old register value */\r\n    tmpreg = hi2c->Instance->CR1;\r\n    \r\n    /* Reset I2Cx DNF bits [11:8] */\r\n    tmpreg &= ~(I2C_CR1_DNF);\r\n    \r\n    /* Set I2Cx DNF coefficient */\r\n    tmpreg |= DigitalFilter << 8;\r\n    \r\n    /* Store the new register value */\r\n    hi2c->Instance->CR1 = tmpreg;\r\n    \r\n    __HAL_I2C_ENABLE(hi2c);\r\n    \r\n    hi2c->State = HAL_I2C_STATE_READY;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2c);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n/**\r\n  * @brief Enable the I2C fast mode plus driving capability.\r\n  * @param ConfigFastModePlus: Selects the pin.\r\n  *   This parameter can be one of the @ref I2CEx_FastModePlus values\r\n  * @retval None\r\n  */\r\nvoid HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)\r\n{\r\n  /* Check the parameter */\r\n  assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));\r\n  \r\n  /* Enable SYSCFG clock */\r\n  __HAL_RCC_SYSCFG_CLK_ENABLE();\r\n  \r\n  /* Enable fast mode plus driving capability for selected pin */\r\n  SET_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus);\r\n}\r\n\r\n/**\r\n  * @brief Disable the I2C fast mode plus driving capability.\r\n  * @param ConfigFastModePlus: Selects the pin.\r\n  *   This parameter can be one of the @ref I2CEx_FastModePlus values\r\n  * @retval None\r\n  */\r\nvoid HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)\r\n{\r\n  /* Check the parameter */\r\n  assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));\r\n  \r\n  /* Enable SYSCFG clock */\r\n  __HAL_RCC_SYSCFG_CLK_ENABLE();\r\n  \r\n  /* Disable fast mode plus driving capability for selected pin */\r\n  CLEAR_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus);\r\n}\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_I2C_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2s.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_i2s.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   I2S HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the Integrated Interchip Sound (I2S) peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + IO operation functions\r\n  *           + Peripheral State and Errors functions\r\n  @verbatim\r\n ===============================================================================\r\n                  ##### How to use this driver #####\r\n ===============================================================================\r\n [..]\r\n    The I2S HAL driver can be used as follows:\r\n    \r\n    (#) Declare a I2S_HandleTypeDef handle structure.\r\n    (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:\r\n        (##) Enable the SPIx interface clock.                      \r\n        (##) I2S pins configuration:\r\n            (+++) Enable the clock for the I2S GPIOs.\r\n            (+++) Configure these I2S pins as alternate function pull-up.\r\n        (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()\r\n             and HAL_I2S_Receive_IT() APIs).\r\n            (+++) Configure the I2Sx interrupt priority.\r\n            (+++) Enable the NVIC I2S IRQ handle.\r\n        (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()\r\n             and HAL_I2S_Receive_DMA() APIs:\r\n            (+++) Declare a DMA handle structure for the Tx/Rx channel.\r\n            (+++) Enable the DMAx interface clock.\r\n            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.                \r\n            (+++) Configure the DMA Tx/Rx Channel.\r\n            (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.\r\n            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the \r\n                DMA Tx/Rx Channel.\r\n  \r\n   (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity\r\n       using HAL_I2S_Init() function.\r\n\r\n   -@- The specific I2S interrupts (Transmission complete interrupt, \r\n       RXNE interrupt and Error Interrupts) will be managed using the macros\r\n       __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.\r\n   -@- Make sure that either:\r\n       (+@) I2S clock is configured based on SYSCLK or \r\n       (+@) External clock source is configured after setting correctly \r\n            the define constant EXTERNAL_CLOCK_VALUE in the stm32f3xx_hal_conf.h file. \r\n\r\n   (#) Three mode of operations are available within this driver :     \r\n  \r\n   *** Polling mode IO operation ***\r\n   =================================\r\n   [..]    \r\n     (+) Send an amount of data in blocking mode using HAL_I2S_Transmit() \r\n     (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()\r\n   \r\n   *** Interrupt mode IO operation ***    \r\n   ===================================\r\n   [..]    \r\n     (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT() \r\n     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can \r\n         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback \r\n     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can \r\n         add his own code by customization of function pointer HAL_I2S_TxCpltCallback\r\n     (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT() \r\n     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can \r\n         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback \r\n     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can \r\n         add his own code by customization of function pointer HAL_I2S_RxCpltCallback                                      \r\n     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can \r\n         add his own code by customization of function pointer HAL_I2S_ErrorCallback\r\n\r\n   *** DMA mode IO operation ***    \r\n   ==============================\r\n   [..] \r\n     (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA() \r\n     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can \r\n         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback \r\n     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can \r\n         add his own code by customization of function pointer HAL_I2S_TxCpltCallback\r\n     (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA() \r\n     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can \r\n         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback \r\n     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can \r\n         add his own code by customization of function pointer HAL_I2S_RxCpltCallback                                     \r\n     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can \r\n         add his own code by customization of function pointer HAL_I2S_ErrorCallback\r\n     (+) Pause the DMA Transfer using HAL_I2S_DMAPause()      \r\n     (+) Resume the DMA Transfer using HAL_I2S_DMAResume()  \r\n     (+) Stop the DMA Transfer using HAL_I2S_DMAStop()      \r\n   \r\n   *** I2S HAL driver macros list ***\r\n   ============================================= \r\n   [..]\r\n     Below the list of most used macros in I2S HAL driver.\r\n       \r\n      (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode) \r\n      (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)    \r\n      (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts\r\n      (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts\r\n      (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not\r\n      \r\n    [..]  \r\n      (@) You can refer to the I2S HAL driver header file for more useful macros\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup I2S I2S\r\n  * @brief I2S HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_I2S_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/** @defgroup I2S_Private_Functions I2S Private Functions\r\n  * @{\r\n  */\r\nstatic void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);\r\nstatic void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);\r\nstatic void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);\r\nstatic void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);\r\nstatic void I2S_DMAError(DMA_HandleTypeDef *hdma);\r\nstatic void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);\r\nstatic void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);\r\nstatic uint32_t I2S_GetClockFreq(I2S_HandleTypeDef *hi2s);\r\nstatic HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup I2S_Exported_Functions I2S Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup  I2S_Exported_Functions_Group1 Initialization and de-initialization functions \r\n  *  @brief    Initialization and Configuration functions \r\n  *\r\n@verbatim    \r\n ===============================================================================\r\n              ##### Initialization and de-initialization functions #####\r\n ===============================================================================\r\n    [..]  This subsection provides a set of functions allowing to initialize and \r\n          de-initialize the I2Sx peripheral in simplex mode:\r\n\r\n      (+) User must Implement HAL_I2S_MspInit() function in which he configures \r\n          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).\r\n\r\n      (+) Call the function HAL_I2S_Init() to configure the selected device with \r\n          the selected configuration:\r\n        (++) Mode\r\n        (++) Standard \r\n        (++) Data Format\r\n        (++) MCLK Output\r\n        (++) Audio frequency\r\n        (++) Polarity\r\n        (++) Full duplex mode\r\n\r\n      (+) Call the function HAL_I2S_DeInit() to restore the default configuration \r\n          of the selected I2Sx peripheral. \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief Initializes the I2S according to the specified parameters \r\n  *         in the I2S_InitTypeDef and create the associated handle.\r\n  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)\r\n{\r\n  uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;\r\n  uint32_t tmp = 0, i2sclk = 0;\r\n \r\n  /* Check the I2S handle allocation */\r\n  if(hi2s == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));\r\n  assert_param(IS_I2S_MODE(hi2s->Init.Mode));\r\n  assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));\r\n  assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));\r\n  assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));\r\n  assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));\r\n  assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));  \r\n  assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));\r\n  \r\n  if(hi2s->State == HAL_I2S_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    hi2s->Lock = HAL_UNLOCKED;\r\n    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */\r\n    HAL_I2S_MspInit(hi2s);\r\n  }\r\n  \r\n  hi2s->State = HAL_I2S_STATE_BUSY;\r\n    \r\n  /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/\r\n  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */\r\n  hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \\\r\n                               SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \\\r\n                               SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD); \r\n  hi2s->Instance->I2SPR = 0x0002;\r\n  \r\n  /* Get the I2SCFGR register value */\r\n  tmpreg = hi2s->Instance->I2SCFGR;\r\n  \r\n  /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/\r\n  if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT)\r\n  {\r\n    i2sodd = (uint16_t)0;\r\n    i2sdiv = (uint16_t)2;   \r\n  }\r\n  /* If the requested audio frequency is not the default, compute the prescaler */\r\n  else\r\n  {\r\n    /* Check the frame length (For the Prescaler computing) *******************/\r\n    if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)\r\n    {\r\n      /* Packet length is 16 bits */\r\n      packetlength = 1;\r\n    }\r\n    else\r\n    {\r\n      /* Packet length is 32 bits */\r\n      packetlength = 2;\r\n    }\r\n    \r\n    /* Get I2S source Clock frequency  ****************************************/\r\n\r\n    /* If an external I2S clock has to be used, the specific define should be set  \r\n    in the project configuration or in the stm32f3xx_conf.h file */\r\n    if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)\r\n    {    \r\n      /* Set the I2S clock to the external clock  value */\r\n      i2sclk = EXTERNAL_CLOCK_VALUE;\r\n    }\r\n    else\r\n    {\r\n      /* Get the I2S source clock value */\r\n\t\t\ti2sclk = I2S_GetClockFreq(hi2s);\r\n    }\r\n    \r\n    /* Compute the Real divider depending on the MCLK output state, with a floating point */\r\n    if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)\r\n    {\r\n      /* MCLK output is enabled */\r\n      tmp = (uint16_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5);\r\n    }\r\n    else\r\n    {\r\n      /* MCLK output is disabled */\r\n      tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5);\r\n    }\r\n    \r\n    /* Remove the flatting point */\r\n    tmp = tmp / 10;  \r\n    \r\n    /* Check the parity of the divider */\r\n    i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);\r\n    \r\n    /* Compute the i2sdiv prescaler */\r\n    i2sdiv = (uint16_t)((tmp - i2sodd) / 2);\r\n    \r\n    /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */\r\n    i2sodd = (uint16_t) (i2sodd << 8);\r\n  }\r\n  \r\n  /* Test if the divider is 1 or 0 or greater than 0xFF */\r\n  if((i2sdiv < 2) || (i2sdiv > 0xFF))\r\n  {\r\n    /* Set the default values */\r\n    i2sdiv = 2;\r\n    i2sodd = 0;\r\n  }\r\n  \r\n  /* Write to SPIx I2SPR register the computed value */\r\n  hi2s->Instance->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)hi2s->Init.MCLKOutput));\r\n  \r\n  /* Configure the I2S with the I2S_InitStruct values */\r\n  tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(hi2s->Init.Mode | \\\r\n                       (uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \\\r\n                       (uint16_t)hi2s->Init.CPOL))));\r\n\r\n  /* Write to SPIx I2SCFGR */  \r\n  hi2s->Instance->I2SCFGR = tmpreg;    \r\n\r\n  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;\r\n  hi2s->State= HAL_I2S_STATE_READY;\r\n  \r\n  return HAL_OK;\r\n}\r\n           \r\n/**\r\n  * @brief DeInitializes the I2S peripheral \r\n  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)\r\n{\r\n  /* Check the I2S handle allocation */\r\n  if(hi2s == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));\r\n\r\n  hi2s->State = HAL_I2S_STATE_BUSY;\r\n  \r\n  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */\r\n  HAL_I2S_MspDeInit(hi2s);\r\n  \r\n  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;\r\n  hi2s->State = HAL_I2S_STATE_RESET;\r\n  \r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hi2s);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief I2S MSP Init\r\n  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @retval None\r\n  */\r\n __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2s);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_I2S_MspInit could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief I2S MSP DeInit\r\n  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @retval None\r\n  */\r\n __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2s);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_I2S_MspDeInit could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2S_Exported_Functions_Group2 Input and Output operation functions \r\n  *  @brief Data transfers functions \r\n  *\r\n@verbatim   \r\n ===============================================================================\r\n                      ##### IO operation functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides a set of functions allowing to manage the I2S data \r\n    transfers.\r\n\r\n    (#) There are two modes of transfer:\r\n       (++) Blocking mode : The communication is performed in the polling mode. \r\n            The status of all data processing is returned by the same function \r\n            after finishing transfer.  \r\n       (++) No-Blocking mode : The communication is performed using Interrupts \r\n            or DMA. These functions return the status of the transfer startup.\r\n            The end of the data processing will be indicated through the \r\n            dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when \r\n            using DMA mode.\r\n\r\n    (#) Blocking mode functions are :\r\n        (++) HAL_I2S_Transmit()\r\n        (++) HAL_I2S_Receive()\r\n        \r\n    (#) No-Blocking mode functions with Interrupt are :\r\n        (++) HAL_I2S_Transmit_IT()\r\n        (++) HAL_I2S_Receive_IT()\r\n\r\n    (#) No-Blocking mode functions with DMA are :\r\n        (++) HAL_I2S_Transmit_DMA()\r\n        (++) HAL_I2S_Receive_DMA()\r\n\r\n    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:\r\n        (++) HAL_I2S_TxCpltCallback()\r\n        (++) HAL_I2S_RxCpltCallback()\r\n        (++) HAL_I2S_ErrorCallback()\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief Transmit an amount of data in blocking mode\r\n  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @param pData: a 16-bit pointer to data buffer.\r\n  * @param Size: number of data sample to be sent:\r\n  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S\r\n  *       configuration phase, the Size parameter means the number of 16-bit data length \r\n  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected \r\n  *       the Size parameter means the number of 16-bit data length. \r\n  * @param  Timeout: Timeout duration\r\n  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization \r\n  *       between Master and Slave(example: audio streaming).\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)\r\n{\r\n  if((pData == NULL ) || (Size == 0)) \r\n  {\r\n    return  HAL_ERROR;                                    \r\n  }\r\n  \r\n  if(hi2s->State == HAL_I2S_STATE_READY)\r\n  { \r\n    if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\\\r\n       ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))\r\n    {\r\n      hi2s->TxXferSize = (Size << 1);\r\n      hi2s->TxXferCount = (Size << 1);\r\n    }\r\n    else\r\n    {\r\n      hi2s->TxXferSize = Size;\r\n      hi2s->TxXferCount = Size;\r\n    }\r\n    \r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2s);\r\n    \r\n    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;\r\n    hi2s->State = HAL_I2S_STATE_BUSY_TX;\r\n   \r\n    /* Check if the I2S is already enabled */ \r\n    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)\r\n    {\r\n      /* Enable I2S peripheral */    \r\n      __HAL_I2S_ENABLE(hi2s);\r\n    }\r\n    \r\n    while(hi2s->TxXferCount > 0)\r\n    {\r\n      hi2s->Instance->DR = (*pData++);\r\n      hi2s->TxXferCount--;   \r\n      /* Wait until TXE flag is set */\r\n      if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)\r\n      {\r\n        /* Set the error code and execute error callback*/\r\n        hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;\r\n        HAL_I2S_ErrorCallback(hi2s);\r\n        return HAL_TIMEOUT;\r\n      }\r\n\r\n      /* Check if an underrun occurs */\r\n      if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) \r\n      {\r\n        /* Set the I2S State ready */\r\n        hi2s->State = HAL_I2S_STATE_READY; \r\n\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2s);\r\n\r\n        /* Set the error code and execute error callback*/\r\n        hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;\r\n        HAL_I2S_ErrorCallback(hi2s);\r\n\r\n        return HAL_ERROR;\r\n      }\r\n    }      \r\n    \r\n    /* Check if Slave mode is selected */\r\n    if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))\r\n    {\r\n      /* Wait until Busy flag is reset */\r\n      if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK) \r\n      {\r\n        /* Set the error code and execute error callback*/\r\n        hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;\r\n        HAL_I2S_ErrorCallback(hi2s);\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n    \r\n    hi2s->State = HAL_I2S_STATE_READY; \r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2s);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Receive an amount of data in blocking mode \r\n  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @param pData: a 16-bit pointer to data buffer.\r\n  * @param Size: number of data sample to be sent:\r\n  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S\r\n  *       configuration phase, the Size parameter means the number of 16-bit data length \r\n  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected \r\n  *       the Size parameter means the number of 16-bit data length. \r\n  * @param Timeout: Timeout duration\r\n  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization \r\n  *       between Master and Slave(example: audio streaming).\r\n  * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate\r\n  *       in continuous way and as the I2S is not disabled at the end of the I2S transaction.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)\r\n{\r\n  if((pData == NULL ) || (Size == 0)) \r\n  {\r\n    return  HAL_ERROR;                                    \r\n  }\r\n  \r\n  if(hi2s->State == HAL_I2S_STATE_READY)\r\n  { \r\n    if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\\\r\n       ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))\r\n    {\r\n      hi2s->RxXferSize = (Size << 1);\r\n      hi2s->RxXferCount = (Size << 1);\r\n    }\r\n    else\r\n    {\r\n      hi2s->RxXferSize = Size;\r\n      hi2s->RxXferCount = Size;\r\n    }\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2s);\r\n    \r\n    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;\r\n    hi2s->State = HAL_I2S_STATE_BUSY_RX;\r\n        \r\n    /* Check if the I2S is already enabled */ \r\n    if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)\r\n    {\r\n      /* Enable I2S peripheral */    \r\n      __HAL_I2S_ENABLE(hi2s);\r\n    }\r\n    \r\n    /* Check if Master Receiver mode is selected */\r\n    if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)\r\n    {\r\n      /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read\r\n      access to the SPI_SR register. */ \r\n      __HAL_I2S_CLEAR_OVRFLAG(hi2s);        \r\n    }\r\n    \r\n    /* Receive data */\r\n    while(hi2s->RxXferCount > 0)\r\n    {\r\n      /* Wait until RXNE flag is set */\r\n      if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK) \r\n      {\r\n        /* Set the error code and execute error callback*/\r\n        hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;\r\n        HAL_I2S_ErrorCallback(hi2s);\r\n        return HAL_TIMEOUT;\r\n      }\r\n      \r\n      /* Check if an overrun occurs */\r\n      if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET) \r\n      {\r\n        /* Set the I2S State ready */\r\n        hi2s->State = HAL_I2S_STATE_READY; \r\n\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hi2s);\r\n\r\n        /* Set the error code and execute error callback*/\r\n        hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;\r\n        HAL_I2S_ErrorCallback(hi2s);\r\n\r\n        return HAL_ERROR;\r\n      }\r\n\r\n      (*pData++) = hi2s->Instance->DR;\r\n      hi2s->RxXferCount--;\r\n    }      \r\n\r\n    hi2s->State = HAL_I2S_STATE_READY; \r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2s);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Transmit an amount of data in non-blocking mode with Interrupt\r\n  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @param pData: a 16-bit pointer to data buffer.\r\n  * @param Size: number of data sample to be sent:\r\n  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S\r\n  *       configuration phase, the Size parameter means the number of 16-bit data length \r\n  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected \r\n  *       the Size parameter means the number of 16-bit data length. \r\n  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization \r\n  *       between Master and Slave(example: audio streaming).\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)\r\n{\r\n  if(hi2s->State == HAL_I2S_STATE_READY)\r\n  {\r\n    if((pData == NULL) || (Size == 0)) \r\n    {\r\n      return  HAL_ERROR;                                    \r\n    }\r\n    \r\n    hi2s->pTxBuffPtr = pData;\r\n    if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\\\r\n      ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))\r\n    {\r\n      hi2s->TxXferSize = (Size << 1);\r\n      hi2s->TxXferCount = (Size << 1);\r\n    }  \r\n    else\r\n    {\r\n      hi2s->TxXferSize = Size;\r\n      hi2s->TxXferCount = Size;\r\n    }\r\n    \r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2s);\r\n    \r\n    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;\r\n    hi2s->State = HAL_I2S_STATE_BUSY_TX;\r\n\r\n    /* Enable TXE and ERR interrupt */\r\n    __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));\r\n    \r\n    /* Check if the I2S is already enabled */ \r\n    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)\r\n    {\r\n      /* Enable I2S peripheral */    \r\n      __HAL_I2S_ENABLE(hi2s);\r\n    }\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2s);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Receive an amount of data in non-blocking mode with Interrupt\r\n  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @param pData: a 16-bit pointer to the Receive data buffer.\r\n  * @param Size: number of data sample to be sent:\r\n  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S\r\n  *       configuration phase, the Size parameter means the number of 16-bit data length \r\n  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected \r\n  *       the Size parameter means the number of 16-bit data length. \r\n  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization \r\n  *       between Master and Slave(example: audio streaming).\r\n  * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation \r\n  * between Master and Slave otherwise the I2S interrupt should be optimized. \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)\r\n{\r\n  if(hi2s->State == HAL_I2S_STATE_READY)\r\n  {\r\n    if((pData == NULL) || (Size == 0)) \r\n    {\r\n      return  HAL_ERROR;                                    \r\n    }\r\n    \r\n    hi2s->pRxBuffPtr = pData;\r\n    if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\\\r\n      ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))\r\n    {\r\n      hi2s->RxXferSize = (Size << 1);\r\n      hi2s->RxXferCount = (Size << 1);\r\n    }  \r\n    else\r\n    {\r\n      hi2s->RxXferSize = Size;\r\n      hi2s->RxXferCount = Size;\r\n    }\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2s);\r\n    \r\n    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;\r\n    hi2s->State = HAL_I2S_STATE_BUSY_RX;\r\n\r\n    /* Enable TXE and ERR interrupt */\r\n    __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));\r\n    \r\n    /* Check if the I2S is already enabled */ \r\n    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)\r\n    {\r\n      /* Enable I2S peripheral */    \r\n      __HAL_I2S_ENABLE(hi2s);\r\n    }\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2s);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY; \r\n  } \r\n}\r\n\r\n/**\r\n  * @brief Transmit an amount of data in non-blocking mode with DMA\r\n  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @param pData: a 16-bit pointer to the Transmit data buffer.\r\n  * @param Size: number of data sample to be sent:\r\n  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S\r\n  *       configuration phase, the Size parameter means the number of 16-bit data length \r\n  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected \r\n  *       the Size parameter means the number of 16-bit data length. \r\n  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization \r\n  *       between Master and Slave(example: audio streaming).\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)\r\n{\r\n  uint32_t *tmp;\r\n  \r\n  if((pData == NULL) || (Size == 0)) \r\n  {\r\n    return  HAL_ERROR;                                    \r\n  }\r\n  \r\n  if(hi2s->State == HAL_I2S_STATE_READY)\r\n  {  \r\n    hi2s->pTxBuffPtr = pData;\r\n    if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\\\r\n      ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))\r\n    {\r\n      hi2s->TxXferSize = (Size << 1);\r\n      hi2s->TxXferCount = (Size << 1);\r\n    }  \r\n    else\r\n    {\r\n      hi2s->TxXferSize = Size;\r\n      hi2s->TxXferCount = Size;\r\n    }  \r\n    \r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2s);\r\n    \r\n    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;\r\n    hi2s->State = HAL_I2S_STATE_BUSY_TX;\r\n\r\n    /* Set the I2S Tx DMA Half transfer complete callback */\r\n    hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;\r\n\r\n    /* Set the I2S TxDMA transfer complete callback */\r\n    hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;\r\n    \r\n    /* Set the DMA error callback */\r\n    hi2s->hdmatx->XferErrorCallback = I2S_DMAError;\r\n    \r\n    /* Enable the Tx DMA Channel */\r\n    tmp = (uint32_t*)&pData;\r\n    HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);\r\n    \r\n    /* Check if the I2S is already enabled */ \r\n    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)\r\n    {\r\n      /* Enable I2S peripheral */    \r\n      __HAL_I2S_ENABLE(hi2s);\r\n    }\r\n    \r\n    /* Enable Tx DMA Request */  \r\n    hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2s);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Receive an amount of data in non-blocking mode with DMA \r\n  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @param pData: a 16-bit pointer to the Receive data buffer.\r\n  * @param Size: number of data sample to be sent:\r\n  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S\r\n  *       configuration phase, the Size parameter means the number of 16-bit data length \r\n  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected \r\n  *       the Size parameter means the number of 16-bit data length. \r\n  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization \r\n  *       between Master and Slave(example: audio streaming).\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)\r\n{\r\n  uint32_t *tmp;\r\n  \r\n  if((pData == NULL) || (Size == 0)) \r\n  {\r\n    return  HAL_ERROR;                                    \r\n  } \r\n    \r\n  if(hi2s->State == HAL_I2S_STATE_READY)\r\n  {    \r\n    hi2s->pRxBuffPtr = pData;\r\n    if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\\\r\n      ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))\r\n    {\r\n      hi2s->RxXferSize = (Size << 1);\r\n      hi2s->RxXferCount = (Size << 1);\r\n    }  \r\n    else\r\n    {\r\n      hi2s->RxXferSize = Size;\r\n      hi2s->RxXferCount = Size;\r\n    }\r\n    /* Process Locked */\r\n    __HAL_LOCK(hi2s);\r\n    \r\n    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;\r\n    hi2s->State = HAL_I2S_STATE_BUSY_RX;\r\n   \r\n    /* Set the I2S Rx DMA Half transfer complete callback */\r\n    hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;\r\n\r\n    /* Set the I2S Rx DMA transfer complete callback */\r\n    hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;\r\n    \r\n    /* Set the DMA error callback */\r\n    hi2s->hdmarx->XferErrorCallback = I2S_DMAError;\r\n    \r\n    /* Check if Master Receiver mode is selected */\r\n    if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)\r\n    {\r\n      /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read\r\n      access to the SPI_SR register. */ \r\n      __HAL_I2S_CLEAR_OVRFLAG(hi2s);        \r\n    }\r\n    \r\n    /* Enable the Rx DMA Channel */\r\n    tmp = (uint32_t*)&pData;        \r\n    HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);\r\n    \r\n    /* Check if the I2S is already enabled */ \r\n    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)\r\n    {\r\n      /* Enable I2S peripheral */    \r\n      __HAL_I2S_ENABLE(hi2s);\r\n    }\r\n    \r\n    /* Enable Rx DMA Request */  \r\n    hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hi2s);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Pauses the audio stream playing from the Media.\r\n  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hi2s);\r\n\r\n  if(hi2s->State == HAL_I2S_STATE_BUSY_TX)\r\n  {\r\n    /* Disable the I2S DMA Tx request */\r\n    hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);\r\n  }\r\n  else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)\r\n  {\r\n    /* Disable the I2S DMA Rx request */\r\n    hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);\r\n  }\r\n  else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)\r\n  {\r\n    if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))\r\n    {\r\n      /* Disable the I2S DMA Tx request */\r\n      hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);\r\n    }\r\n    else\r\n    {\r\n      /* Disable the I2S DMA Rx request */\r\n      hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);\r\n    }\r\n  }\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hi2s);\r\n  \r\n  return HAL_OK; \r\n}\r\n\r\n/**\r\n  * @brief Resumes the audio stream playing from the Media.\r\n  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hi2s);\r\n  \r\n  if(hi2s->State == HAL_I2S_STATE_BUSY_TX)\r\n  {\r\n    /* Enable the I2S DMA Tx request */\r\n    SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);\r\n  }\r\n  else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)\r\n  {\r\n    /* Enable the I2S DMA Rx request */\r\n    SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);\r\n  }\r\n  \r\n  /* If the I2S peripheral is still not enabled, enable it */\r\n  if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))\r\n  {\r\n    /* Enable I2S peripheral */    \r\n    __HAL_I2S_ENABLE(hi2s);\r\n  }\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hi2s);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Stops the audio stream playing from the Media.\r\n  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hi2s);\r\n  \r\n  /* Disable the I2S Tx/Rx DMA requests */\r\n  CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);\r\n  CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);\r\n  \r\n  /* Abort the I2S DMA Channel tx */\r\n  if(hi2s->hdmatx != NULL)\r\n  {\r\n    /* Disable the I2S DMA channel */\r\n    __HAL_DMA_DISABLE(hi2s->hdmatx);\r\n    HAL_DMA_Abort(hi2s->hdmatx);\r\n  }\r\n  /* Abort the I2S DMA Channel rx */\r\n  if(hi2s->hdmarx != NULL)\r\n  {\r\n    /* Disable the I2S DMA channel */\r\n    __HAL_DMA_DISABLE(hi2s->hdmarx);\r\n    HAL_DMA_Abort(hi2s->hdmarx);\r\n  }\r\n\r\n  /* Disable I2S peripheral */\r\n  __HAL_I2S_DISABLE(hi2s);\r\n  \r\n  hi2s->State = HAL_I2S_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hi2s);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  This function handles I2S interrupt request.\r\n  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @retval HAL status\r\n  */\r\nvoid HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)\r\n{  \r\n  __IO uint32_t i2ssr = hi2s->Instance->SR;\r\n\r\n  if(hi2s->State == HAL_I2S_STATE_BUSY_RX)\r\n  {  \r\n    /* I2S in mode Receiver ----------------------------------------------------*/\r\n    if(((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))\r\n    {\r\n      I2S_Receive_IT(hi2s);\r\n    }\r\n\r\n    /* I2S Overrun error interrupt occurred -------------------------------------*/\r\n    if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))\r\n    {\r\n      /* Disable RXNE and ERR interrupt */\r\n      __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));\r\n\r\n      /* Set the I2S State ready */\r\n      hi2s->State = HAL_I2S_STATE_READY; \r\n\r\n      /* Set the error code and execute error callback*/\r\n      hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;\r\n      HAL_I2S_ErrorCallback(hi2s);\r\n    }  \r\n  }\r\n  else if(hi2s->State == HAL_I2S_STATE_BUSY_TX)\r\n  {  \r\n    /* I2S in mode Transmitter ---------------------------------------------------*/\r\n    if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))\r\n    {     \r\n      I2S_Transmit_IT(hi2s);\r\n    } \r\n    \r\n    /* I2S Underrun error interrupt occurred ------------------------------------*/\r\n    if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))\r\n    {\r\n      /* Disable TXE and ERR interrupt */\r\n      __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));\r\n\r\n      /* Set the I2S State ready */\r\n      hi2s->State = HAL_I2S_STATE_READY; \r\n\r\n      /* Set the error code and execute error callback*/\r\n      hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;\r\n      HAL_I2S_ErrorCallback(hi2s);\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup I2S_Private_Functions I2S Private Functions\r\n  * @{\r\n  */\r\n/**\r\n  * @brief This function handles I2S Communication Timeout.\r\n  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @param Flag: Flag checked\r\n  * @param State: Value of the flag expected\r\n  * @param Timeout: Duration of the timeout\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, \r\n                                                       uint32_t State, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  /* Wait until flag is set */\r\n  if(State == RESET)\r\n  {\r\n    while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)\r\n    {\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n        {\r\n          /* Set the I2S State ready */\r\n          hi2s->State= HAL_I2S_STATE_READY;\r\n\r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hi2s);\r\n\r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n  }\r\n  else\r\n  {\r\n    while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)\r\n    {\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n        {\r\n          /* Set the I2S State ready */\r\n          hi2s->State= HAL_I2S_STATE_READY;\r\n\r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hi2s);\r\n\r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n  }\r\n  return HAL_OK;    \r\n}\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup I2S_Exported_Functions I2S Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup  I2S_Exported_Functions_Group2 Input and Output operation functions \r\n  * @{\r\n  */\r\n/**\r\n  * @brief Tx Transfer Half completed callbacks\r\n  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @retval None\r\n  */\r\n __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2s);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_I2S_TxHalfCpltCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief Tx Transfer completed callbacks\r\n  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @retval None\r\n  */\r\n __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2s);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_I2S_TxCpltCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief Rx Transfer half completed callbacks\r\n  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @retval None\r\n  */\r\n__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2s);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_I2S_RxCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief Rx Transfer completed callbacks\r\n  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @retval None\r\n  */\r\n__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2s);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_I2S_RxCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief I2S error callbacks\r\n  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @retval None\r\n  */\r\n __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hi2s);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_I2S_ErrorCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions \r\n  *  @brief   Peripheral State functions \r\n  *\r\n@verbatim   \r\n ===============================================================================\r\n                      ##### Peripheral State and Errors functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection permits to get in run-time the status of the peripheral \r\n    and the data flow.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Return the I2S state\r\n  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @retval HAL state\r\n  */\r\nHAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)\r\n{\r\n  return hi2s->State;\r\n}\r\n\r\n/**\r\n  * @brief  Return the I2S error code\r\n  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @retval I2S Error Code\r\n  */\r\nuint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)\r\n{\r\n  return hi2s->ErrorCode;\r\n}\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n  /**\r\n  * @brief  Get I2S Input Clock based on I2S source clock selection\r\n  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains\r\n  *               the configuration information for I2S module.   \r\n  * @retval I2S Clock Input \r\n  */\r\nstatic uint32_t I2S_GetClockFreq(I2S_HandleTypeDef *hi2s)   \r\n{\r\n  uint32_t tmpreg = 0;\r\n  /* This variable used to store the VCO Input (value in Hz) */\r\n  uint32_t vcoinput = 0;\r\n  /* This variable used to store the I2S_CK_x (value in Hz) */\r\n  uint32_t i2sclocksource = 0;\r\n\r\n  /* Configure I2S Clock based on I2S source clock selection */ \r\n  \r\n  /* I2S_CLK_x : I2S Block Clock configuration for different clock sources selected */\r\n  switch(hi2s->Init.ClockSource)\r\n  {\r\n    case I2S_CLOCK_PLL :\r\n    {\r\n      /* Configure the PLLI2S division factor */\r\n      /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */ \r\n      if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)\r\n      {\r\n        /* In Case the PLL Source is HSI (Internal Clock) */\r\n        vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\r\n      }\r\n      else\r\n      {\r\n        /* In Case the PLL Source is HSE (External Clock) */\r\n        vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));\r\n      }\r\n\r\n      /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */\r\n      /* I2S_CLK(first level) = PLLI2S_VCO Output/PLLI2SR */\r\n      tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28;\r\n      i2sclocksource = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);\r\n    \r\n      break;\r\n    }\r\n    case I2S_CLOCK_EXTERNAL :\r\n    {\r\n      i2sclocksource = EXTERNAL_CLOCK_VALUE;\r\n      break;\r\n    }\r\n    default :\r\n    {\r\n      break;\r\n    }\r\n  }\r\n\r\n  /* the return result is the value of I2S clock */\r\n  return i2sclocksource; \r\n}\r\n\r\n/** @addtogroup I2S_Private_Functions I2S Private Functions\r\n  * @{\r\n  */\r\n/**\r\n  * @brief DMA I2S transmit process complete callback \r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)   \r\n{\r\n  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n  \r\n  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)\r\n  {\r\n    hi2s->TxXferCount = 0;\r\n\r\n    /* Disable Tx DMA Request */\r\n    hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);\r\n    \r\n    if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)\r\n    {\r\n      if(hi2s->RxXferCount == 0)\r\n      {\r\n        hi2s->State = HAL_I2S_STATE_READY;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      hi2s->State = HAL_I2S_STATE_READY; \r\n    }\r\n  }\r\n  HAL_I2S_TxCpltCallback(hi2s);\r\n}\r\n\r\n/**\r\n  * @brief DMA I2S transmit process half complete callback \r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n\r\n  HAL_I2S_TxHalfCpltCallback(hi2s);\r\n}\r\n\r\n/**\r\n  * @brief DMA I2S receive process complete callback \r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)   \r\n{\r\n  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n\r\n  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)\r\n  {\r\n    /* Disable Rx DMA Request */\r\n    hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);\r\n\r\n    hi2s->RxXferCount = 0;\r\n    if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)\r\n    {\r\n      if(hi2s->TxXferCount == 0)\r\n      {\r\n        hi2s->State = HAL_I2S_STATE_READY;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      hi2s->State = HAL_I2S_STATE_READY; \r\n    }\r\n  }\r\n  HAL_I2S_RxCpltCallback(hi2s); \r\n}\r\n      \r\n/**\r\n  * @brief DMA I2S receive process half complete callback \r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n\r\n  HAL_I2S_RxHalfCpltCallback(hi2s); \r\n}\r\n\r\n/**\r\n  * @brief DMA I2S communication error callback \r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void I2S_DMAError(DMA_HandleTypeDef *hdma)   \r\n{\r\n  I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  \r\n  /* Disable Rx and Tx DMA Request */\r\n  hi2s->Instance->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));\r\n  hi2s->TxXferCount = 0;\r\n  hi2s->RxXferCount = 0;\r\n  \r\n  hi2s->State= HAL_I2S_STATE_READY;\r\n\r\n  /* Set the error code and execute error callback*/\r\n  hi2s->ErrorCode |= HAL_I2S_ERROR_DMA;\r\n  HAL_I2S_ErrorCallback(hi2s);\r\n}\r\n\r\n/**\r\n  * @brief Transmit an amount of data in non-blocking mode with Interrupt\r\n  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains\r\n  *         the configuration information for I2S module\r\n  * @retval None\r\n  */\r\nstatic void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)\r\n{\r\n  /* Transmit data */\r\n  hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);\r\n  hi2s->TxXferCount--;\t\r\n\r\n  if(hi2s->TxXferCount == 0)\r\n  {\r\n    /* Disable TXE and ERR interrupt */\r\n    __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));\r\n\r\n    hi2s->State = HAL_I2S_STATE_READY;\r\n    HAL_I2S_TxCpltCallback(hi2s);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Receive an amount of data in non-blocking mode with Interrupt\r\n  * @param hi2s: I2S handle\r\n  * @retval None\r\n  */\r\nstatic void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)\r\n{\r\n  /* Receive data */    \r\n  (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;\r\n  hi2s->RxXferCount--;\r\n\r\n  if(hi2s->RxXferCount == 0)\r\n  {    \r\n    /* Disable RXNE and ERR interrupt */\r\n    __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));\r\n\r\n    hi2s->State = HAL_I2S_STATE_READY;     \r\n    HAL_I2S_RxCpltCallback(hi2s); \r\n  }\r\n}\r\n/**\r\n  * @}\r\n  */\r\n  \r\n#endif /* HAL_I2S_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_irda.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_irda.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   IRDA HAL module driver.\r\n  *          This file provides firmware functions to manage the following\r\n  *          functionalities of the IrDA SIR ENDEC block (IrDA):\r\n  *           + Initialization and de-initialization methods\r\n  *           + IO operation methods\r\n  *           + Peripheral Control methods\r\n  *\r\n  @verbatim\r\n  ==============================================================================\r\n                        ##### How to use this driver #####\r\n  ==============================================================================\r\n  [..]\r\n    The IRDA HAL driver can be used as follows:\r\n\r\n    (#) Declare a IRDA_HandleTypeDef handle structure.\r\n    (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API:\r\n        (##) Enable the USARTx interface clock.\r\n        (##) IRDA pins configuration:\r\n            (+++) Enable the clock for the IRDA GPIOs.\r\n            (+++) Configure these IRDA pins as alternate function pull-up.\r\n        (##) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()\r\n             and HAL_IRDA_Receive_IT() APIs):\r\n            (+++) Configure the USARTx interrupt priority.\r\n            (+++) Enable the NVIC USART IRQ handle.\r\n        (##) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()\r\n             and HAL_IRDA_Receive_DMA() APIs):\r\n            (+++) Declare a DMA handle structure for the Tx/Rx stream.\r\n            (+++) Enable the DMAx interface clock.\r\n            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.\r\n            (+++) Configure the DMA Tx/Rx Stream.\r\n            (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.\r\n            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.\r\n\r\n    (#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler\r\n        and Mode(Receiver/Transmitter) in the hirda Init structure.\r\n\r\n    (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:\r\n        (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)\r\n            by calling the customized HAL_IRDA_MspInit() API.\r\n    -@@- The specific IRDA interrupts (Transmission complete interrupt,\r\n        RXNE interrupt and Error Interrupts) will be managed using the macros\r\n        __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.\r\n\r\n    (#) Three operation modes are available within this driver :\r\n\r\n    *** Polling mode IO operation ***\r\n    =================================\r\n    [..]\r\n      (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()\r\n      (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()\r\n\r\n    *** Interrupt mode IO operation ***\r\n    ===================================\r\n    [..]\r\n      (+) Send an amount of data in non blocking mode using HAL_IRDA_Transmit_IT()\r\n      (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can\r\n           add his own code by customization of function pointer HAL_IRDA_TxCpltCallback\r\n      (+) Receive an amount of data in non blocking mode using HAL_IRDA_Receive_IT()\r\n      (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can\r\n           add his own code by customization of function pointer HAL_IRDA_RxCpltCallback\r\n      (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can\r\n           add his own code by customization of function pointer HAL_IRDA_ErrorCallback\r\n\r\n    *** DMA mode IO operation ***\r\n    =============================\r\n    [..]\r\n      (+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA()\r\n      (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can\r\n           add his own code by customization of function pointer HAL_IRDA_TxCpltCallback\r\n      (+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA()\r\n      (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can\r\n           add his own code by customization of function pointer HAL_IRDA_RxCpltCallback\r\n      (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can\r\n           add his own code by customization of function pointer HAL_IRDA_ErrorCallback\r\n\r\n    *** IRDA HAL driver macros list ***\r\n    ===================================\r\n    [..]\r\n      Below the list of most used macros in IRDA HAL driver.\r\n\r\n     (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral\r\n     (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral\r\n     (+) __HAL_IRDA_GET_FLAG : Checks whether the specified IRDA flag is set or not\r\n     (+) __HAL_IRDA_CLEAR_FLAG : Clears the specified IRDA pending flag\r\n     (+) __HAL_IRDA_ENABLE_IT: Enables the specified IRDA interrupt\r\n     (+) __HAL_IRDA_DISABLE_IT: Disables the specified IRDA interrupt\r\n\r\n     (@) You can refer to the IRDA HAL driver header file for more useful macros\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup IRDA IRDA\r\n  * @brief HAL IRDA module driver\r\n  * @{\r\n  */\r\n#ifdef HAL_IRDA_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @addtogroup IRDA_Private_Constants\r\n  * @{\r\n  */\r\n#define TEACK_REACK_TIMEOUT            1000U\r\n#define HAL_IRDA_TXDMA_TIMEOUTVALUE    22000U\r\n#define IRDA_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE \\\r\n                                   | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE))\r\n/**\r\n  * @}\r\n  */\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/** @addtogroup IRDA_Private_Functions\r\n  * @{\r\n  */\r\nstatic void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);\r\nstatic void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);\r\nstatic void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);\r\nstatic void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);\r\nstatic void IRDA_DMAError(DMA_HandleTypeDef *hdma);\r\nstatic void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma);\r\nstatic void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);\r\nstatic void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);\r\nstatic void IRDA_SetConfig (IRDA_HandleTypeDef *hirda);\r\nstatic HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);\r\nstatic HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);\r\nstatic HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);\r\nstatic HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);\r\nstatic HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);\r\n/**\r\n  * @}\r\n  */\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup IRDA_Exported_Functions IrDA Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions\r\n  *  @brief    Initialization and Configuration functions\r\n  *\r\n@verbatim\r\n\r\n===============================================================================\r\n            ##### Initialization and Configuration functions #####\r\n ===============================================================================\r\n    [..]\r\n    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy\r\n    in IrDA mode.\r\n      (+) For the asynchronous mode only these parameters can be configured:\r\n        (++) BaudRate\r\n        (++) WordLength\r\n        (++) Parity: If the parity is enabled, then the MSB bit of the data written\r\n             in the data register is transmitted but is changed by the parity bit.\r\n             Depending on the frame length defined by the M bit (8-bits or 9-bits),\r\n             please refer to Reference manual for possible IRDA frame formats.\r\n        (++) Prescaler: A pulse of width less than two and greater than one PSC period(s) may or may\r\n             not be rejected. The receiver set up time should be managed by software. The IrDA physical layer\r\n             specification specifies a minimum of 10 ms delay between transmission and\r\n             reception (IrDA is a half duplex protocol).\r\n        (++) Mode: Receiver/transmitter modes\r\n        (++) IrDAMode: the IrDA can operate in the Normal mode or in the Low power mode.\r\n    [..]\r\n    The HAL_IRDA_Init() API follows IRDA configuration procedures (details for the procedures\r\n    are available in reference manual).\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the IRDA mode according to the specified\r\n  *         parameters in the IRDA_InitTypeDef and create the associated handle.\r\n  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified IRDA module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)\r\n{\r\n    /* Check the IRDA handle allocation */\r\n    if(hirda == NULL)\r\n    {\r\n        return HAL_ERROR;\r\n    }\r\n\r\n    /* Check the USART/UART associated to the IRDA handle */\r\n    assert_param(IS_IRDA_INSTANCE(hirda->Instance));\r\n\r\n    if(hirda->gState == HAL_IRDA_STATE_RESET)\r\n    {\r\n        /* Allocate lock resource and initialize it */\r\n        hirda->Lock = HAL_UNLOCKED;\r\n        /* Init the low level hardware : GPIO, CLOCK, CORTEX */\r\n        HAL_IRDA_MspInit(hirda);\r\n    }\r\n\r\n    hirda->gState = HAL_IRDA_STATE_BUSY;\r\n\r\n    /* Disable the Peripheral to update the configuration registers */\r\n    __HAL_IRDA_DISABLE(hirda);\r\n\r\n    /* Set the IRDA Communication parameters */\r\n    IRDA_SetConfig(hirda);\r\n\r\n    /* In IRDA mode, the following bits must be kept cleared:\r\n    - LINEN, STOP and CLKEN bits in the USART_CR2 register,\r\n    - SCEN and HDSEL bits in the USART_CR3 register.*/\r\n    CLEAR_BIT(hirda->Instance->CR3, USART_CR2_LINEN | USART_CR2_STOP | USART_CR2_CLKEN);\r\n    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_SCEN | USART_CR3_HDSEL);\r\n\r\n    /* set the UART/USART in IRDA mode */\r\n    SET_BIT(hirda->Instance->CR3, USART_CR3_IREN);\r\n\r\n    /* Enable the Peripheral */\r\n    __HAL_IRDA_ENABLE(hirda);\r\n\r\n    /* TEACK and/or REACK to check before moving hirda->State to Ready */\r\n    return (IRDA_CheckIdleState(hirda));\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the IRDA peripheral\r\n  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified IRDA module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)\r\n{\r\n    /* Check the IRDA handle allocation */\r\n    if(hirda == NULL)\r\n    {\r\n        return HAL_ERROR;\r\n    }\r\n\r\n    /* Check the parameters */\r\n    assert_param(IS_IRDA_INSTANCE(hirda->Instance));\r\n\r\n    hirda->gState = HAL_IRDA_STATE_BUSY;\r\n\r\n    /* DeInit the low level hardware */\r\n    HAL_IRDA_MspDeInit(hirda);\r\n    /* Disable the Peripheral */\r\n    __HAL_IRDA_DISABLE(hirda);\r\n\r\n    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;\r\n    hirda->gState = HAL_IRDA_STATE_RESET;\r\n    hirda->RxState = HAL_IRDA_STATE_RESET;\r\n\r\n    /* Release Lock */\r\n    __HAL_UNLOCK(hirda);\r\n\r\n    return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  IRDA MSP Init.\r\n  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified IRDA module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)\r\n{\r\n    /* Prevent unused argument(s) compilation warning */\r\n    UNUSED(hirda);\r\n\r\n    /* NOTE : This function Should not be modified, when the callback is needed,\r\n              the HAL_IRDA_MspInit could be implemented in the user file\r\n     */\r\n}\r\n\r\n/**\r\n  * @brief  IRDA MSP DeInit.\r\n  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified IRDA module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)\r\n{\r\n    /* Prevent unused argument(s) compilation warning */\r\n    UNUSED(hirda);\r\n\r\n    /* NOTE : This function Should not be modified, when the callback is needed,\r\n              the HAL_IRDA_MspDeInit could be implemented in the user file\r\n     */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions\r\n  *  @brief   IRDA Transmit/Receive functions\r\n  *\r\n@verbatim\r\n ===============================================================================\r\n                      ##### IO operation functions #####\r\n ===============================================================================\r\n    This subsection provides a set of functions allowing to manage the IRDA data transfers.\r\n    [..]\r\n    IrDA is a half duplex communication protocol. If the Transmitter is busy, any data\r\n    on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver\r\n    is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.\r\n    While receiving data, transmission should be avoided as the data to be transmitted\r\n    could be corrupted.\r\n\r\n    (#) There are two modes of transfer:\r\n       (++) Blocking mode: the communication is performed in polling mode.\r\n            The HAL status of all data processing is returned by the same function\r\n            after finishing transfer.\r\n       (++) No-Blocking mode: the communication is performed using Interrupts\r\n           or DMA, these API's return the HAL status.\r\n           The end of the data processing will be indicated through the\r\n           dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when\r\n           using DMA mode.\r\n           The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks\r\n           will be executed respectively at the end of the Transmit or Receive process\r\n           The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected\r\n\r\n    (#) Blocking mode API's are :\r\n        (++) HAL_IRDA_Transmit()\r\n        (++) HAL_IRDA_Receive()\r\n\r\n    (#) Non-Blocking mode API's with Interrupt are :\r\n        (++) HAL_IRDA_Transmit_IT()\r\n        (++) HAL_IRDA_Receive_IT()\r\n        (++) HAL_IRDA_IRQHandler()\r\n        (++) IRDA_Transmit_IT()\r\n        (++) IRDA_Receive_IT()\r\n\r\n    (#) Non-Blocking mode functions with DMA are :\r\n        (++) HAL_IRDA_Transmit_DMA()\r\n        (++) HAL_IRDA_Receive_DMA()\r\n\r\n    (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:\r\n        (++) HAL_IRDA_TxCpltCallback()\r\n        (++) HAL_IRDA_RxCpltCallback()\r\n        (++) HAL_IRDA_ErrorCallback()\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Sends an amount of data in blocking mode.\r\n  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified IRDA module.\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be sent\r\n  * @param  Timeout: Specify timeout value\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r\n{\r\n    uint16_t* tmp;\r\n    uint32_t tickstart = 0U;\r\n\r\n    /* Check that a Tx process is not already ongoing */\r\n    if(hirda->gState == HAL_IRDA_STATE_READY)\r\n    {\r\n        if((pData == NULL) || (Size == 0U))\r\n        {\r\n            return  HAL_ERROR;\r\n        }\r\n\r\n        /* Process Locked */\r\n        __HAL_LOCK(hirda);\r\n        hirda->ErrorCode = HAL_IRDA_ERROR_NONE;\r\n        hirda->gState = HAL_IRDA_STATE_BUSY_TX;\r\n\r\n        /* Init tickstart for timeout managment*/\r\n        tickstart = HAL_GetTick();\r\n\r\n        hirda->TxXferSize = Size;\r\n        hirda->TxXferCount = Size;\r\n        while(hirda->TxXferCount > 0U)\r\n        {\r\n            hirda->TxXferCount--;\r\n\r\n            if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)\r\n            {\r\n                return HAL_TIMEOUT;\r\n            }\r\n            if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))\r\n            {\r\n                tmp = (uint16_t*) pData;\r\n                hirda->Instance->TDR = (*tmp & (uint16_t)0x01FFU);\r\n                pData +=2;\r\n            }\r\n            else\r\n            {\r\n                hirda->Instance->TDR = (*pData++ & (uint8_t)0xFFU);\r\n            }\r\n        }\r\n\r\n        if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)\r\n        {\r\n            return HAL_TIMEOUT;\r\n        }\r\n\r\n        /* At end of Tx process, restore hirda->gState to Ready */\r\n        hirda->gState = HAL_IRDA_STATE_READY;\r\n\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hirda);\r\n\r\n        return HAL_OK;\r\n    }\r\n    else\r\n    {\r\n        return HAL_BUSY;\r\n    }\r\n}\r\n\r\n/**\r\n  * @brief  Receive an amount of data in blocking mode.\r\n  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified IRDA module.\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be received\r\n  * @param  Timeout: Specify timeout value\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r\n{\r\n    uint16_t* tmp;\r\n    uint16_t uhMask;\r\n    uint32_t tickstart = 0U;\r\n\r\n    /* Check that a Rx process is not already ongoing */\r\n    if(hirda->RxState == HAL_IRDA_STATE_READY)\r\n    {\r\n        if((pData == NULL) || (Size == 0U))\r\n        {\r\n            return  HAL_ERROR;\r\n        }\r\n\r\n        /* Process Locked */\r\n        __HAL_LOCK(hirda);\r\n        hirda->ErrorCode = HAL_IRDA_ERROR_NONE;\r\n        hirda->RxState = HAL_IRDA_STATE_BUSY_RX;\r\n\r\n        /* Init tickstart for timeout managment*/\r\n        tickstart = HAL_GetTick();\r\n\r\n        hirda->RxXferSize = Size;\r\n        hirda->RxXferCount = Size;\r\n\r\n        /* Computation of the mask to apply to the RDR register\r\n           of the UART associated to the IRDA */\r\n        IRDA_MASK_COMPUTATION(hirda);\r\n        uhMask = hirda->Mask;\r\n\r\n        /* Check data remaining to be received */\r\n        while(hirda->RxXferCount > 0U)\r\n        {\r\n            hirda->RxXferCount--;\r\n\r\n            if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)\r\n            {\r\n                return HAL_TIMEOUT;\r\n            }\r\n            if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))\r\n            {\r\n                tmp = (uint16_t*) pData ;\r\n                *tmp = (uint16_t)(hirda->Instance->RDR & uhMask);\r\n                pData +=2;\r\n            }\r\n            else\r\n            {\r\n                *pData++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);\r\n            }\r\n        }\r\n\r\n        /* At end of Rx process, restore hirda->RxState to Ready */\r\n        hirda->RxState = HAL_IRDA_STATE_READY;\r\n\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hirda);\r\n\r\n        return HAL_OK;\r\n    }\r\n    else\r\n    {\r\n        return HAL_BUSY;\r\n    }\r\n}\r\n\r\n/**\r\n  * @brief  Send an amount of data in non blocking mode.\r\n  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified IRDA module.\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)\r\n{\r\n    /* Check that a Tx process is not already ongoing */\r\n    if(hirda->gState == HAL_IRDA_STATE_READY)\r\n    {\r\n        if((pData == NULL) || (Size == 0U))\r\n        {\r\n            return HAL_ERROR;\r\n        }\r\n\r\n        /* Process Locked */\r\n        __HAL_LOCK(hirda);\r\n\r\n        hirda->pTxBuffPtr = pData;\r\n        hirda->TxXferSize = Size;\r\n        hirda->TxXferCount = Size;\r\n\r\n        hirda->ErrorCode = HAL_IRDA_ERROR_NONE;\r\n        hirda->gState = HAL_IRDA_STATE_BUSY_TX;\r\n\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hirda);\r\n\r\n        /* Enable the IRDA Transmit Complete Interrupt */\r\n        SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);\r\n\r\n        return HAL_OK;\r\n    }\r\n    else\r\n    {\r\n        return HAL_BUSY;\r\n    }\r\n}\r\n\r\n/**\r\n  * @brief  Receives an amount of data in non blocking mode.\r\n  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified IRDA module.\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be received\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)\r\n{\r\n    /* Check that a Rx process is not already ongoing */\r\n    if(hirda->RxState == HAL_IRDA_STATE_READY)\r\n    {\r\n        if((pData == NULL) || (Size == 0U))\r\n        {\r\n            return HAL_ERROR;\r\n        }\r\n\r\n        /* Process Locked */\r\n        __HAL_LOCK(hirda);\r\n\r\n        hirda->pRxBuffPtr = pData;\r\n        hirda->RxXferSize = Size;\r\n        hirda->RxXferCount = Size;\r\n\r\n        /* Computation of the mask to apply to the RDR register\r\n           of the UART associated to the IRDA */\r\n        IRDA_MASK_COMPUTATION(hirda);\r\n\r\n        hirda->ErrorCode = HAL_IRDA_ERROR_NONE;\r\n        hirda->RxState = HAL_IRDA_STATE_BUSY_RX;\r\n\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hirda);\r\n\r\n        /* Enable the IRDA Parity Error Interrupt */\r\n        SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);\r\n\r\n        /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */\r\n        SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);\r\n\r\n        /* Enable the IRDA Data Register not empty Interrupt */\r\n        SET_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE);\r\n\r\n        return HAL_OK;\r\n    }\r\n    else\r\n    {\r\n        return HAL_BUSY;\r\n    }\r\n}\r\n\r\n/**\r\n  * @brief  Sends an amount of data in non blocking mode.\r\n  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified IRDA module.\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)\r\n{\r\n    uint32_t *tmp;\r\n\r\n    /* Check that a Tx process is not already ongoing */\r\n    if(hirda->gState == HAL_IRDA_STATE_READY)\r\n    {\r\n        if((pData == NULL) || (Size == 0U))\r\n        {\r\n            return HAL_ERROR;\r\n        }\r\n\r\n        /* Process Locked */\r\n        __HAL_LOCK(hirda);\r\n\r\n        hirda->pTxBuffPtr = pData;\r\n        hirda->TxXferSize = Size;\r\n        hirda->TxXferCount = Size;\r\n\r\n        hirda->ErrorCode = HAL_IRDA_ERROR_NONE;\r\n        hirda->gState = HAL_IRDA_STATE_BUSY_TX;\r\n\r\n        /* Set the IRDA DMA transfer complete callback */\r\n        hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;\r\n\r\n        /* Set the IRDA DMA half transfer complete callback */\r\n        hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;\r\n\r\n        /* Set the DMA error callback */\r\n        hirda->hdmatx->XferErrorCallback = IRDA_DMAError;\r\n\r\n        /* Set the DMA abort callback */\r\n        hirda->hdmatx->XferAbortCallback = NULL;\r\n\r\n        /* Enable the IRDA transmit DMA channel */\r\n        tmp = (uint32_t*)&pData;\r\n        HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->TDR, Size);\r\n\r\n        /* Clear the TC flag in the SR register by writing 0 to it */\r\n        __HAL_IRDA_CLEAR_IT(hirda, IRDA_FLAG_TC);\r\n\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hirda);\r\n\r\n        /* Enable the DMA transfer for transmit request by setting the DMAT bit\r\n           in the IRDA CR3 register */\r\n        SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);\r\n\r\n        return HAL_OK;\r\n    }\r\n    else\r\n    {\r\n        return HAL_BUSY;\r\n    }\r\n}\r\n\r\n/**\r\n  * @brief  Receives an amount of data in non blocking mode.\r\n  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified IRDA module.\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be received\r\n  * @note   When the IRDA parity is enabled (PCE = 1) the data received contain the parity bit.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)\r\n{\r\n    uint32_t *tmp;\r\n\r\n    /* Check that a Rx process is not already ongoing */\r\n    if(hirda->RxState == HAL_IRDA_STATE_READY)\r\n    {\r\n        if((pData == NULL) || (Size == 0U))\r\n        {\r\n            return HAL_ERROR;\r\n        }\r\n\r\n        /* Process Locked */\r\n        __HAL_LOCK(hirda);\r\n\r\n        hirda->pRxBuffPtr = pData;\r\n        hirda->RxXferSize = Size;\r\n\r\n        hirda->ErrorCode = HAL_IRDA_ERROR_NONE;\r\n        hirda->RxState = HAL_IRDA_STATE_BUSY_RX;\r\n\r\n        /* Set the IRDA DMA transfer complete callback */\r\n        hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;\r\n\r\n        /* Set the IRDA DMA half transfer complete callback */\r\n        hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;\r\n\r\n        /* Set the DMA error callback */\r\n        hirda->hdmarx->XferErrorCallback = IRDA_DMAError;\r\n\r\n        /* Set the DMA abort callback */\r\n        hirda->hdmarx->XferAbortCallback = NULL;\r\n\r\n        /* Enable the DMA channel */\r\n        tmp = (uint32_t*)&pData;\r\n        HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, *(uint32_t*)tmp, Size);\r\n\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hirda);\r\n\r\n        /* Enable the IRDA Parity Error Interrupt */\r\n        SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);\r\n\r\n        /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */\r\n        SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);\r\n\r\n        /* Enable the DMA transfer for the receiver request by setting the DMAR bit\r\n        in the USART CR3 register */\r\n        SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);\r\n\r\n        return HAL_OK;\r\n    }\r\n    else\r\n    {\r\n        return HAL_BUSY;\r\n    }\r\n}\r\n\r\n/**\r\n  * @brief Pauses the DMA Transfer.\r\n  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified IRDA module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)\r\n{\r\n    /* Process Locked */\r\n    __HAL_LOCK(hirda);\r\n\r\n    if((hirda->gState == HAL_IRDA_STATE_BUSY_TX)&&\r\n            (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))\r\n    {\r\n        /* Disable the UART DMA Tx request */\r\n        CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);\r\n    }\r\n    if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX)&&\r\n            (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))\r\n    {\r\n        /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */\r\n        CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);\r\n        CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);\r\n\r\n        /* Disable the UART DMA Rx request */\r\n        CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);\r\n    }\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hirda);\r\n\r\n    return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Resumes the DMA Transfer.\r\n  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified UART module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)\r\n{\r\n    /* Process Locked */\r\n    __HAL_LOCK(hirda);\r\n\r\n    if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)\r\n    {\r\n        /* Enable the UART DMA Tx request */\r\n        SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);\r\n    }\r\n    if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)\r\n    {\r\n        /* Clear the Overrun flag before resuming the Rx transfer*/\r\n        __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);\r\n\r\n        /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */\r\n        SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);\r\n        SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);\r\n\r\n        /* Enable the UART DMA Rx request */\r\n        SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);\r\n    }\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hirda);\r\n\r\n    return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Stops the DMA Transfer.\r\n  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified UART module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)\r\n{\r\n    /* The Lock is not implemented on this API to allow the user application\r\n       to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() /\r\n       HAL_IRDA_TxHalfCpltCallback / HAL_IRDA_RxHalfCpltCallback:\r\n       indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete\r\n       interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of\r\n       the stream and the corresponding call back is executed. */\r\n\r\n    /* Stop IRDA DMA Tx request if ongoing */\r\n    if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) &&\r\n            (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))\r\n    {\r\n        CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);\r\n\r\n        /* Abort the IRDA DMA Tx channel */\r\n        if(hirda->hdmatx != NULL)\r\n        {\r\n            HAL_DMA_Abort(hirda->hdmatx);\r\n        }\r\n        IRDA_EndTxTransfer(hirda);\r\n    }\r\n\r\n    /* Stop IRDA DMA Rx request if ongoing */\r\n    if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) &&\r\n            (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))\r\n    {\r\n        CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);\r\n\r\n        /* Abort the IRDA DMA Rx channel */\r\n        if(hirda->hdmarx != NULL)\r\n        {\r\n            HAL_DMA_Abort(hirda->hdmarx);\r\n        }\r\n        IRDA_EndRxTransfer(hirda);\r\n    }\r\n    return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief DMA IRDA communication abort callback, when call by HAL services on Error\r\n  *        (To be called at end of DMA Abort procedure following error occurrence).\r\n  * @param hdma: DMA handle.\r\n  * @retval None\r\n  */\r\nstatic void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)\r\n{\r\n    IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n    hirda->RxXferCount = 0U;\r\n    hirda->TxXferCount = 0U;\r\n\r\n    HAL_IRDA_ErrorCallback(hirda);\r\n}\r\n\r\n/**\r\n  * @brief  This function handles IRDA interrupt request.\r\n  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified IRDA module.\r\n  * @retval None\r\n  */\r\nvoid HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)\r\n{\r\n    uint32_t isrflags, cr1its, cr3its, errorflags;\r\n\r\n    isrflags   = READ_REG(hirda->Instance->ISR);\r\n    cr1its     = READ_REG(hirda->Instance->CR1);\r\n    cr3its     = READ_REG(hirda->Instance->CR3);\r\n\r\n    /* If no error occurs */\r\n    errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));\r\n    if (errorflags == RESET)\r\n    {\r\n        /* IRDA in mode Receiver ---------------------------------------------------*/\r\n        if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))\r\n        {\r\n            IRDA_Receive_IT(hirda);\r\n            /* Clear RXNE interrupt flag */\r\n            __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);\r\n        }\r\n    }\r\n\r\n    /* If some errors occur */\r\n    if((errorflags != RESET) && ((cr3its & (USART_CR3_EIE | USART_CR1_PEIE)) != RESET))\r\n    {\r\n        /* IRDA parity error interrupt occurred -------------------------------------*/\r\n        if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))\r\n        {\r\n            __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF);\r\n            hirda->ErrorCode |= HAL_IRDA_ERROR_PE;\r\n        }\r\n\r\n        /* IRDA frame error interrupt occurred --------------------------------------*/\r\n        if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))\r\n        {\r\n            __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF);\r\n            hirda->ErrorCode |= HAL_IRDA_ERROR_FE;\r\n        }\r\n\r\n        /* IRDA noise error interrupt occurred --------------------------------------*/\r\n        if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))\r\n        {\r\n            __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF);\r\n            hirda->ErrorCode |= HAL_IRDA_ERROR_NE;\r\n        }\r\n\r\n        /* IRDA Over-Run interrupt occurred -----------------------------------------*/\r\n        if(((isrflags & USART_ISR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))\r\n        {\r\n            __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);\r\n            hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;\r\n        }\r\n\r\n        /* Call IRDA Error Call back function if need be --------------------------*/\r\n        if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)\r\n        {\r\n            /* IRDA in mode Receiver ---------------------------------------------------*/\r\n            if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))\r\n            {\r\n                IRDA_Receive_IT(hirda);\r\n            }\r\n\r\n            /* If Overrun error occurs, or if any error occurs in DMA mode reception,\r\n            consider error as blocking */\r\n            if (((hirda->ErrorCode & HAL_UART_ERROR_ORE) != RESET) ||\r\n                    (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))\r\n            {\r\n                /* Blocking error : transfer is aborted\r\n                Set the IRDA state ready to be able to start again the process,\r\n                Disable Rx Interrupts, and disable Rx DMA request, if ongoing */\r\n                IRDA_EndRxTransfer(hirda);\r\n\r\n                /* Disable the IRDA DMA Rx request if enabled */\r\n                if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))\r\n                {\r\n                    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);\r\n\r\n                    /* Abort the IRDA DMA Rx channel */\r\n                    if(hirda->hdmarx != NULL)\r\n                    {\r\n                        /* Set the IRDA DMA Abort callback :\r\n                        will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */\r\n                        hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;\r\n\r\n                        /* Abort DMA RX */\r\n                        if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)\r\n                        {\r\n                          /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */\r\n                          hirda->hdmarx->XferAbortCallback(hirda->hdmarx);\r\n                        }\r\n                    }\r\n                    else\r\n                    {\r\n                        /* Call user error callback */\r\n                        HAL_IRDA_ErrorCallback(hirda);\r\n                    }\r\n                }\r\n                else\r\n                {\r\n                    /* Call user error callback */\r\n                    HAL_IRDA_ErrorCallback(hirda);\r\n                }\r\n            }\r\n            else\r\n            {\r\n                /* Non Blocking error : transfer could go on.\r\n                Error is notified to user through user error callback */\r\n                HAL_IRDA_ErrorCallback(hirda);\r\n                hirda->ErrorCode = HAL_IRDA_ERROR_NONE;\r\n            }\r\n        }\r\n        return;\r\n\r\n    } /* End if some error occurs */\r\n\r\n    /* IRDA in mode Transmitter ------------------------------------------------*/\r\n    if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))\r\n    {\r\n        IRDA_Transmit_IT(hirda);\r\n        return;\r\n    }\r\n\r\n    /* IRDA in mode Transmitter (transmission end) -----------------------------*/\r\n    if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))\r\n    {\r\n        IRDA_EndTransmit_IT(hirda);\r\n        return;\r\n    }\r\n}\r\n\r\n/**\r\n  * @brief  End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).\r\n  * @param  hirda: IRDA handle.\r\n  * @retval None\r\n  */\r\nstatic void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)\r\n{\r\n    /* Disable TXEIE and TCIE interrupts */\r\n    CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));\r\n\r\n    /* At end of Tx process, restore hirda->gState to Ready */\r\n    hirda->gState = HAL_IRDA_STATE_READY;\r\n}\r\n\r\n/**\r\n  * @brief  End ongoing Rx transfer on IRDA peripheral (following error detection or Reception completion).\r\n  * @param  hirda: IRDA handle.\r\n  * @retval None\r\n  */\r\nstatic void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)\r\n{\r\n    /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\r\n    CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r\n    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);\r\n\r\n    /* At end of Rx process, restore huart->RxState to Ready */\r\n    hirda->RxState = HAL_IRDA_STATE_READY;\r\n}\r\n\r\n/**\r\n  * @brief  Tx Transfer complete callbacks.\r\n  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified IRDA module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)\r\n{\r\n    /* Prevent unused argument(s) compilation warning */\r\n    UNUSED(hirda);\r\n\r\n    /* NOTE : This function should not be modified, when the callback is needed,\r\n              the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file\r\n     */\r\n}\r\n\r\n/**\r\n  * @brief  Tx Half Transfer completed callbacks.\r\n  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified USART module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)\r\n{\r\n    /* Prevent unused argument(s) compilation warning */\r\n    UNUSED(hirda);\r\n\r\n    /* NOTE : This function should not be modified, when the callback is needed,\r\n              the HAL_IRDA_TxCpltCallback can be implemented in the user file\r\n     */\r\n}\r\n\r\n/**\r\n  * @brief  Rx Transfer complete callbacks.\r\n  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified IRDA module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)\r\n{\r\n    /* Prevent unused argument(s) compilation warning */\r\n    UNUSED(hirda);\r\n\r\n    /* NOTE : This function should not be modified, when the callback is needed,\r\n              the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file\r\n     */\r\n}\r\n\r\n/**\r\n  * @brief  Rx Half Transfer complete callbacks.\r\n  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified IRDA module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)\r\n{\r\n    /* Prevent unused argument(s) compilation warning */\r\n    UNUSED(hirda);\r\n\r\n    /* NOTE : This function should not be modified, when the callback is needed,\r\n              the HAL_IRDA_RxCpltCallback can be implemented in the user file\r\n     */\r\n}\r\n\r\n/**\r\n  * @brief IRDA error callbacks.\r\n  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified IRDA module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)\r\n{\r\n    /* Prevent unused argument(s) compilation warning */\r\n    UNUSED(hirda);\r\n\r\n    /* NOTE : This function should not be modified, when the callback is needed,\r\n              the HAL_IRDA_ErrorCallback can be implemented in the user file\r\n     */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup IRDA_Exported_Functions_Group3 Peripheral Control functions\r\n  *  @brief   IRDA control functions\r\n  *\r\n@verbatim\r\n ===============================================================================\r\n                      ##### Peripheral Control functions #####\r\n ===============================================================================\r\n    [..]\r\n    This subsection provides a set of functions allowing to control the IRDA.\r\n     (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state of the IRDA peripheral.\r\n     (+) IRDA_SetConfig() API is used to configure the IRDA communications parameters.\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Returns the IRDA state.\r\n  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified IRDA module.\r\n  * @retval HAL state\r\n  */\r\nHAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)\r\n{\r\n    uint32_t temp1 = 0x00U, temp2 = 0x00U;\r\n    temp1 = hirda->gState;\r\n    temp2 = hirda->RxState;\r\n\r\n    return (HAL_IRDA_StateTypeDef)(temp1 | temp2);\r\n}\r\n\r\n/**\r\n  * @brief  Return the IRDA error code\r\n  * @param  hirda : pointer to a IRDA_HandleTypeDef structure that contains\r\n  *              the configuration information for the specified IRDA.\r\n* @retval IRDA Error Code\r\n*/\r\nuint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)\r\n{\r\n    uint32_t temp1 = 0x00U, temp2 = 0x00U;\r\n    temp1 = hirda->gState;\r\n    temp2 = hirda->RxState;\r\n\r\n    return (HAL_IRDA_StateTypeDef)(temp1 | temp2);\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @brief Configure the IRDA peripheral\r\n  * @param hirda: irda handle\r\n  * @retval None\r\n  */\r\nstatic void IRDA_SetConfig(IRDA_HandleTypeDef *hirda)\r\n{\r\n    uint32_t tmpreg      = 0x00000000U;\r\n    uint32_t clocksource = 0x00000000U;\r\n\r\n    /* Check the communication parameters */\r\n    assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));\r\n    assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));\r\n    assert_param(IS_IRDA_PARITY(hirda->Init.Parity));\r\n    assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode));\r\n    assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler));\r\n    assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode));\r\n    /*-------------------------- USART CR1 Configuration -----------------------*/\r\n    /* Configure the IRDA Word Length, Parity and transfer Mode:\r\n    Set the M bits according to hirda->Init.WordLength value\r\n    Set PCE and PS bits according to hirda->Init.Parity value\r\n    Set TE and RE bits according to hirda->Init.Mode value */\r\n    tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ;\r\n\r\n    MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg);\r\n\r\n    /*-------------------------- USART CR3 Configuration -----------------------*/\r\n    MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode);\r\n\r\n    /*-------------------------- USART GTPR Configuration ----------------------*/\r\n    MODIFY_REG(hirda->Instance->GTPR, (uint32_t)USART_GTPR_PSC, hirda->Init.Prescaler);\r\n\r\n    /*-------------------------- USART BRR Configuration -----------------------*/\r\n    IRDA_GETCLOCKSOURCE(hirda, clocksource);\r\n    switch (clocksource)\r\n    {\r\n    case IRDA_CLOCKSOURCE_PCLK1:\r\n        hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hirda->Init.BaudRate/2))/ hirda->Init.BaudRate);\r\n        break;\r\n    case IRDA_CLOCKSOURCE_PCLK2:\r\n        hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hirda->Init.BaudRate/2))/ hirda->Init.BaudRate);\r\n        break;\r\n    case IRDA_CLOCKSOURCE_HSI:\r\n        hirda->Instance->BRR = (uint16_t)((HSI_VALUE + (hirda->Init.BaudRate/2))/ hirda->Init.BaudRate);\r\n        break;\r\n    case IRDA_CLOCKSOURCE_SYSCLK:\r\n        hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hirda->Init.BaudRate/2))/ hirda->Init.BaudRate);\r\n        break;\r\n    case IRDA_CLOCKSOURCE_LSE:\r\n        hirda->Instance->BRR = (uint16_t)((LSE_VALUE + (hirda->Init.BaudRate/2))/ hirda->Init.BaudRate);\r\n        break;\r\n    default:\r\n        break;\r\n    }\r\n}\r\n\r\n/**\r\n  * @brief Check the IRDA Idle State\r\n  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified IRDA module.\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)\r\n{\r\n    uint32_t tickstart = 0U;\r\n\r\n    /* Initialize the IRDA ErrorCode */\r\n    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;\r\n\r\n    /* Init tickstart for timeout managment*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    /* Check if the Transmitter is enabled */\r\n    if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)\r\n    {\r\n        /* Wait until TEACK flag is set */\r\n        if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK)\r\n        {\r\n            return HAL_TIMEOUT;\r\n        }\r\n    }\r\n    /* Check if the Receiver is enabled */\r\n    if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)\r\n    {\r\n        if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK)\r\n        {\r\n            return HAL_TIMEOUT;\r\n        }\r\n    }\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hirda);\r\n\r\n    /* Initialize the IRDA state*/\r\n    hirda->gState= HAL_IRDA_STATE_READY;\r\n    hirda->RxState= HAL_IRDA_STATE_READY;\r\n\r\n    return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  This function handles IRDA Communication Timeout.\r\n  * @param  hirda pointer to a IRDA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified IRDA module.\r\n  * @param  Flag specifies the IRDA flag to check.\r\n  * @param  Status The new Flag status (SET or RESET).\r\n  * @param  Tickstart Tick start value\r\n  * @param  Timeout Timeout duration\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)\r\n{\r\n    /* Wait until flag is set */\r\n    while((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)\r\n    {\r\n        /* Check for the Timeout */\r\n        if(Timeout != HAL_MAX_DELAY)\r\n        {\r\n            if((Timeout == 0)||((HAL_GetTick() - Tickstart ) > Timeout))\r\n            {\r\n                /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */\r\n                CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));\r\n                CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);\r\n\r\n                hirda->gState= HAL_IRDA_STATE_READY;\r\n                hirda->RxState= HAL_IRDA_STATE_READY;\r\n\r\n                /* Process Unlocked */\r\n                __HAL_UNLOCK(hirda);\r\n\r\n                return HAL_TIMEOUT;\r\n            }\r\n        }\r\n    }\r\n    return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Send an amount of data in non blocking mode.\r\n  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified IRDA module.\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)\r\n{\r\n    uint16_t* tmp;\r\n\r\n    /* Check that a Tx process is ongoing */\r\n    if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)\r\n    {\r\n        if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)\r\n        {\r\n            tmp = (uint16_t*) hirda->pTxBuffPtr;\r\n            hirda->Instance->RDR = (uint16_t)(*tmp & (uint16_t)0x01FFU);\r\n            if(hirda->Init.Parity == IRDA_PARITY_NONE)\r\n            {\r\n                hirda->pTxBuffPtr += 2U;\r\n            }\r\n            else\r\n            {\r\n                hirda->pTxBuffPtr += 1U;\r\n            }\r\n        }\r\n        else\r\n        {\r\n            hirda->Instance->RDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0x00FFU);\r\n        }\r\n\r\n        if(--hirda->TxXferCount == 0U)\r\n        {\r\n            /* Disable the IRDA Transmit Data Register Empty Interrupt */\r\n            CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);\r\n\r\n            /* Enable the IRDA Transmit Complete Interrupt */\r\n            SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);\r\n        }\r\n\r\n        return HAL_OK;\r\n    }\r\n    else\r\n    {\r\n        return HAL_BUSY;\r\n    }\r\n}\r\n\r\n/**\r\n  * @brief  Wraps up transmission in non blocking mode.\r\n  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified IRDA module.\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)\r\n{\r\n    /* Disable the IRDA Transmit Complete Interrupt */\r\n    CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);\r\n\r\n    /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */\r\n    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);\r\n\r\n    /* Tx process is ended, restore hirda->gState to Ready */\r\n    hirda->gState = HAL_IRDA_STATE_READY;\r\n\r\n    HAL_IRDA_TxCpltCallback(hirda);\r\n\r\n    return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Receive an amount of data in non blocking mode.\r\n  *         Function called under interruption only, once\r\n  *         interruptions have been enabled by HAL_IRDA_Receive_IT()\r\n  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified IRDA module.\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)\r\n{\r\n    uint16_t* tmp;\r\n    uint16_t  uhdata;\r\n    uint16_t  uhMask = hirda->Mask;\r\n\r\n    if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)\r\n    {\r\n        uhdata = (uint16_t) READ_REG(hirda->Instance->RDR);\r\n        if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))\r\n        {\r\n            tmp = (uint16_t*) hirda->pRxBuffPtr ;\r\n            *tmp = (uint16_t)(uhdata & uhMask);\r\n            hirda->pRxBuffPtr  +=2U;\r\n        }\r\n        else\r\n        {\r\n            *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask);\r\n        }\r\n\r\n        if(--hirda->RxXferCount == 0U)\r\n        {\r\n            CLEAR_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE);\r\n\r\n            /* Disable the IRDA Parity Error Interrupt */\r\n            CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);\r\n\r\n            /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */\r\n            CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);\r\n\r\n            /* Rx process is completed, restore hirda->RxState to Ready */\r\n            hirda->RxState = HAL_IRDA_STATE_READY;\r\n\r\n            HAL_IRDA_RxCpltCallback(hirda);\r\n\r\n            return HAL_OK;\r\n        }\r\n        return HAL_OK;\r\n    }\r\n    else\r\n    {\r\n        /* Clear RXNE interrupt flag */\r\n        __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);\r\n        return HAL_BUSY;\r\n    }\r\n}\r\n\r\n/**\r\n  * @brief DMA IRDA Tx transfer completed callback\r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n    IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n\r\n    /* DMA Normal mode*/\r\n    if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)\r\n    {\r\n        hirda->TxXferCount = 0U;\r\n\r\n        /* Disable the DMA transfer for transmit request by setting the DMAT bit\r\n           in the IRDA CR3 register */\r\n        CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);\r\n\r\n        /* Enable the IRDA Transmit Complete Interrupt */\r\n        SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);\r\n    }\r\n    /* DMA Circular mode */\r\n    else\r\n    {\r\n        HAL_IRDA_TxCpltCallback(hirda);\r\n    }\r\n}\r\n\r\n/**\r\n  * @brief DMA IRDA receive process half complete callback\r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n    IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n\r\n    HAL_IRDA_TxHalfCpltCallback(hirda);\r\n}\r\n\r\n/**\r\n  * @brief DMA IRDA Rx Transfer completed callback\r\n  * @param hdma: DMA handle\r\n  * @retval None\r\n  */\r\nstatic void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n    IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n\r\n    /* DMA Normal mode */\r\n    if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)\r\n    {\r\n        hirda->RxXferCount = 0U;\r\n\r\n        /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */\r\n        CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);\r\n        CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);\r\n\r\n        /* Disable the DMA transfer for the receiver request by setting the DMAR bit\r\n           in the IRDA CR3 register */\r\n        CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);\r\n\r\n        /* At end of Rx process, restore hirda->RxState to Ready */\r\n        hirda->RxState = HAL_IRDA_STATE_READY;\r\n    }\r\n\r\n    HAL_IRDA_RxCpltCallback(hirda);\r\n}\r\n\r\n/**\r\n  * @brief DMA IRDA receive process half complete callback\r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n    IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n\r\n    HAL_IRDA_RxHalfCpltCallback(hirda);\r\n}\r\n\r\n/**\r\n  * @brief DMA IRDA communication error callback\r\n  * @param hdma: DMA handle\r\n  * @retval None\r\n  */\r\nstatic void IRDA_DMAError(DMA_HandleTypeDef *hdma)\r\n{\r\n    IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n\r\n    hirda->RxXferCount = 0U;\r\n    hirda->TxXferCount = 0U;\r\n\r\n    /* Stop IRDA DMA Tx request if ongoing */\r\n    if (  (hirda->gState == HAL_IRDA_STATE_BUSY_TX)\r\n            &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) )\r\n    {\r\n        IRDA_EndTxTransfer(hirda);\r\n    }\r\n\r\n    /* Stop IRDA DMA Rx request if ongoing */\r\n    if (  (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)\r\n            &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) )\r\n    {\r\n        IRDA_EndRxTransfer(hirda);\r\n    }\r\n\r\n    hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;\r\n\r\n    HAL_IRDA_ErrorCallback(hirda);\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_IRDA_MODULE_ENABLED */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_iwdg.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_iwdg.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   IWDG HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the Independent Watchdog (IWDG) peripheral:\r\n  *           + Initialization and Start functions\r\n  *           + IO operation functions\r\n  *\r\n  @verbatim\r\n  ==============================================================================\r\n                    ##### IWDG Generic features #####\r\n  ==============================================================================\r\n  [..]\r\n    (+) The IWDG can be started by either software or hardware (configurable\r\n        through option byte).\r\n\r\n    (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even\r\n        if the main clock fails.\r\n\r\n    (+) Once the IWDG is started, the LSI is forced ON and both can not be \r\n        disabled. The counter starts counting down from the reset value (0xFFF).\r\n        When it reaches the end of count value (0x000) a reset signal is \r\n        generated (IWDG reset).\r\n\r\n    (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register, \r\n        the IWDG_RLR value is reloaded in the counter and the watchdog reset is\r\n        prevented.\r\n\r\n    (+) The IWDG is implemented in the VDD voltage domain that is still functional\r\n        in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).\r\n        IWDGRST flag in RCC_CSR register can be used to inform when an IWDG\r\n        reset occurs.\r\n\r\n    (+) Debug mode : When the microcontroller enters debug mode (core halted),\r\n        the IWDG counter either continues to work normally or stops, depending \r\n        on DBG_IWDG_STOP configuration bit in DBG module, accessible through\r\n        __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros\r\n\r\n    [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s\r\n         The IWDG timeout may vary due to LSI frequency dispersion. STM32F7xx\r\n         devices provide the capability to measure the LSI frequency (LSI clock\r\n         connected internally to TIM16 CH1 input capture). The measured value\r\n         can be used to have an IWDG timeout with an acceptable accuracy.\r\n\r\n                     ##### How to use this driver #####\r\n  ==============================================================================\r\n  [..]\r\n    (#) Use IWDG using HAL_IWDG_Init() function to :\r\n      (+) Enable instance by writing Start keyword in IWDG_KEY register. LSI \r\n           clock is forced ON and IWDG counter starts downcounting.\r\n      (+) Enable write access to configuration register: IWDG_PR, IWDG_RLR & \r\n           IWDG_WINR.\r\n      (+) Configure the IWDG prescaler and counter reload value. This reload \r\n           value will be loaded in the IWDG counter each time the watchdog is \r\n           reloaded, then the IWDG will start counting down from this value.\r\n      (+) wait for status flags to be reset\"\r\n      (+) Depending on window parameter:\r\n        (++) If Window Init parameter is same as Window register value, \r\n             nothing more is done but reload counter value in order to exit \r\n             function withy exact time base.\r\n        (++) Else modify Window register. This will automatically reload\r\n             watchdog counter.\r\n\r\n    (#) Then the application program must refresh the IWDG counter at regular\r\n        intervals during normal operation to prevent an MCU reset, using\r\n        HAL_IWDG_Refresh() function.\r\n\r\n     *** IWDG HAL driver macros list ***\r\n     ====================================\r\n     [..]\r\n       Below the list of most used macros in IWDG HAL driver:\r\n      (+) __HAL_IWDG_START: Enable the IWDG peripheral\r\n      (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in\r\n          the reload register\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_IWDG_MODULE_ENABLED\r\n/** @addtogroup IWDG\r\n  * @brief IWDG HAL module driver.\r\n  * @{\r\n  */\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @defgroup IWDG_Private_Defines IWDG Private Defines\r\n  * @{\r\n  */\r\n/* Status register need 5 RC LSI divided by prescaler clock to be updated. With \r\n   higher prescaler (256), and according to LSI variation, we need to wait at \r\n   least 6 cycles so 48 ms. */\r\n#define HAL_IWDG_DEFAULT_TIMEOUT            48u\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @addtogroup IWDG_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup IWDG_Exported_Functions_Group1\r\n *  @brief    Initialization and Start functions.\r\n *\r\n@verbatim\r\n ===============================================================================\r\n          ##### Initialization and Start functions #####\r\n ===============================================================================\r\n [..]  This section provides functions allowing to:\r\n      (+) Initialize the IWDG according to the specified parameters in the \r\n          IWDG_InitTypeDef of associated handle.\r\n      (+) Manage Window option.\r\n      (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog \r\n          is reloaded in order to exit function with correct time base.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initialize the IWDG according to the specified parameters in the \r\n  *         IWDG_InitTypeDef and start watchdog. Before exiting function, \r\n  *         watchdog is refreshed in order to have correct time base.\r\n  * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified IWDG module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)\r\n{\r\n  uint32_t tickstart;\r\n\r\n  /* Check the IWDG handle allocation */\r\n  if(hiwdg == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));\r\n  assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));\r\n  assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));\r\n  assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));\r\n\r\n  /* Enable IWDG. LSI is turned on automaticaly */\r\n  __HAL_IWDG_START(hiwdg);\r\n\r\n  /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing\r\n  0x5555 in KR */\r\n  IWDG_ENABLE_WRITE_ACCESS(hiwdg);\r\n\r\n  /* Write to IWDG registers the Prescaler & Reload values to work with */\r\n  hiwdg->Instance->PR = hiwdg->Init.Prescaler;\r\n  hiwdg->Instance->RLR = hiwdg->Init.Reload;\r\n\r\n  /* Check pending flag, if previous update not done, return timeout */\r\n  tickstart = HAL_GetTick();\r\n\r\n   /* Wait for register to be updated */\r\n  while(hiwdg->Instance->SR != RESET)\r\n  {\r\n    if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n\r\n  /* If window parameter is different than current value, modify window \r\n  register */\r\n  if(hiwdg->Instance->WINR != hiwdg->Init.Window)\r\n  {\r\n    /* Write to IWDG WINR the IWDG_Window value to compare with. In any case,\r\n    even if window feature is disabled, Watchdog will be reloaded by writing \r\n    windows register */\r\n    hiwdg->Instance->WINR = hiwdg->Init.Window;\r\n  }\r\n  else\r\n  {\r\n    /* Reload IWDG counter with value defined in the reload register */\r\n    __HAL_IWDG_RELOAD_COUNTER(hiwdg);\r\n  }\r\n\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @addtogroup IWDG_Exported_Functions_Group2\r\n *  @brief   IO operation functions\r\n *\r\n@verbatim\r\n ===============================================================================\r\n                      ##### IO operation functions #####\r\n ===============================================================================\r\n [..]  This section provides functions allowing to:\r\n      (+) Refresh the IWDG.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n\r\n/**\r\n  * @brief  Refresh the IWDG.\r\n  * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified IWDG module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)\r\n{\r\n  /* Reload IWDG counter with value defined in the reload register */\r\n  __HAL_IWDG_RELOAD_COUNTER(hiwdg);\r\n\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_IWDG_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_jpeg.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_jpeg.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   JPEG HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the JPEG encoder/decoder peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + JPEG processing functions encoding and decoding\r\n  *           + JPEG decoding Getting Info and encoding configuration setting\r\n  *           + JPEG enable/disable header parsing functions (for decoding)\r\n  *           + JPEG Input/Output Buffer configuration.\r\n  *           + JPEG callback functions\r\n  *           + JPEG Abort/Pause/Resume functions\r\n  *           + JPEG custom quantization tables setting functions\r\n  *           + IRQ handler management\r\n  *           + Peripheral State and Error functions\r\n  *\r\n  @verbatim\r\n  ==============================================================================\r\n                     ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]\r\n     (#) Initialize the JPEG peripheral using HAL_JPEG_Init : No initialization parameters are required.\r\n         Only the call to HAL_JPEG_Init is necessary to initialize the JPEG peripheral.\r\n\r\n     (#) If operation is JPEG encoding use function HAL_JPEG_ConfigEncoding to set\r\n         the encoding parameters (mandatory before calling the encoding function).\r\n         the application can change the encoding parameter \"ImageQuality\" from\r\n         1 to 100 to obtain a more or less quality (visual quality vs the original row image),\r\n         and inversely more or less jpg file size.\r\n\r\n     (#) Note that for decoding operation the JPEG peripheral output data are organized in\r\n         YCbCr blocks called MCU (Minimum Coded Unit) as defioned in the JPEG specification\r\n         ISO/IEC 10918-1 standard. \r\n         It is up to the application to transform these YCbCr blocks to RGB data that can be display.\r\n         \r\n         Respectively, for Encoding operation the JPEG peripheral input should be organized\r\n         in YCbCr MCU blocks. It is up to the application to perform the necessary RGB to YCbCr\r\n         MCU blocks transformation before feeding the JPEG peripheral with data.\r\n\r\n     (#) Use functions HAL_JPEG_Encode and HAL_JPEG_Decode to start respectively\r\n         a JPEG encoding/decoding operation in polling method (blocking).\r\n\r\n     (#) Use functions HAL_JPEG_Encode_IT and HAL_JPEG_Decode_IT to start respectively\r\n         a JPEG encoding/decoding operation with Interrupt method (not blocking).\r\n\r\n     (#) Use functions HAL_JPEG_Encode_DMA and HAL_JPEG_Decode_DMA to start respectively\r\n         a JPEG encoding/decoding operation with DMA method (not blocking).\r\n\r\n     (#) Callback HAL_JPEG_InfoReadyCallback is asserted if the current operation \r\n         is a JPEG decoding to provide the application with JPEG image  parameters.\r\n         This callback is asserted when the JPEG peripheral successfully parse the\r\n         JPEG header.\r\n\r\n     (#) Callback HAL_JPEG_GetDataCallback is asserted for both encoding and decoding\r\n         operations to inform the application that the input buffer has been\r\n         consumed by the peripheral and to ask for a new data chunk if the operation\r\n         (encoding/decoding) has not been complete yet.\r\n\r\n         This CallBack should be implemented in the application side. It should \r\n         call the function HAL_JPEG_ConfigInputBuffer if new input data are available, \r\n         or call HAL_JPEG_Pause with parameter XferSelection set to \"JPEG_PAUSE_RESUME_INPUT\" \r\n         to inform the JPEG HAL driver that the ongoing operation shall pause waiting for the\r\n         application to provide a new input data chunk. \r\n         Once the application succeed getting new data and if the input has been paused,\r\n         the application can call the function HAL_JPEG_ConfigInputBuffer to set the new\r\n         input buffer and size, then resume the JPEG HAL input by calling new function HAL_JPEG_Resume.\r\n         If the application has ended feeding the HAL JPEG with input data (no more input data), the application \r\n         Should call the function HAL_JPEG_ConfigInputBuffer (within the callback HAL_JPEG_GetDataCallback) \r\n         with the parameter InDataLength set to zero.\r\n       \r\n         The mechanism of HAL_JPEG_ConfigInputBuffer/HAL_JPEG_Pause/HAL_JPEG_Resume allows\r\n         to the application to provide the input data (for encoding or decoding) by chunks.\r\n         If the new input data chunk is not available (because data should be read from an input file\r\n         for example) the application can pause the JPEG input (using function HAL_JPEG_Pause)\r\n         Once the new input data chunk is available ( read from a file for example), the application\r\n         can call the function \"HAL_JPEG_ConfigInputBuffer\" to provide the HAL with the new chunk\r\n         then resume the JPEG HAL input by calling function \"HAL_JPEG_Resume\".\r\n        \r\n         The application can call  functions HAL_JPEG_ConfigInputBuffer  then \"HAL_JPEG_Resume\".\r\n         any time (outside the HAL_JPEG_GetDataCallback)  Once the new input chunk data available.\r\n         However, to keep data coherency, the function HAL_JPEG_Pause must be imperatively called\r\n        (if necessary) within the callback HAL_JPEG_GetDataCallback, i.e when the HAL JPEG has ended\r\n         Transferring the previous chunk buffer to the JPEG peripheral.\r\n        \r\n     (#) Callback HAL_JPEG_DataReadyCallback is asserted when the HAL JPEG driver\r\n         has filled the given output buffer with the given size.\r\n         \r\n         This CallBack should be implemented in the application side. It should \r\n         call the function HAL_JPEG_ConfigOutputBuffer to provide the HAL JPEG driver\r\n         with the new output buffer location and size to be used  to store next data chunk.\r\n         if the application is not ready to provide the output chunk location then it can\r\n         call the function \"HAL_JPEG_Pause\" with parameter XferSelection set to \"JPEG_PAUSE_RESUME_OUTPUT\"\r\n         to inform the JPEG HAL driver that it shall pause output data. Once the application\r\n         is ready to receive the new data chunk (output buffer location free or available) it should call\r\n         the function \"HAL_JPEG_ConfigOutputBuffer\" to provide the HAL JPEG driver\r\n         with the new output chunk buffer location and size, then call \"HAL_JPEG_Resume\" \r\n         to inform the HAL that it shall resume outputting data in the given output buffer.\r\n\r\n         The mechanism of HAL_JPEG_ConfigOutputBuffer/HAL_JPEG_Pause/HAL_JPEG_Resume allows\r\n         the application to receive data from the JPEG peripheral by chunks. when a chunk\r\n         is received, the application can pause the HAL JPEG output data to be able to process\r\n         these received data (YCbCr to RGB conversion in case of decoding or data storage in case\r\n         of encoding).\r\n\r\n        The application can call  functions HAL_JPEG_ ConfigOutputBuffer then \"HAL_JPEG_Resume\".\r\n        any time (outside the HAL_JPEG_ DataReadyCallback)  Once the output data buffer is free to use.\r\n        However, to keep data coherency, the function HAL_JPEG_Pause must be imperatively called\r\n        (if necessary) within the callback HAL_JPEG_ DataReadyCallback, i.e when the HAL JPEG has ended\r\n        Transferring the previous chunk buffer from the JPEG peripheral to the application.\r\n\r\n     (#) Callback HAL_JPEG_EncodeCpltCallback is asserted when the HAL JPEG driver has\r\n         ended the current JPEG encoding operation, and all output data has been transmitted\r\n         to the application.\r\n\r\n     (#) Callback HAL_JPEG_DecodeCpltCallback is asserted when the HAL JPEG driver has\r\n         ended the current JPEG decoding operation. and all output data has been transmitted\r\n         to the application.\r\n\r\n     (#) Callback HAL_JPEG_ErrorCallback is asserted when an error occurred during \r\n         the current operation. the application can call the function \"HAL_JPEG_GetError\"\r\n         to retrieve the error codes.\r\n\r\n     (#) By default the HAL JPEG driver uses the default quantization tables\r\n          as provide in the JPEG specification (ISO/IEC 10918-1 standard) for encoding.\r\n          User can change these default tables if necessary using the function \"HAL_JPEG_SetUserQuantTables\"\r\n          Note that for decoding the quantization tables are automatically extracted from\r\n          the JPEG header.\r\n\r\n      (#) To control JPEG state you can use the following function: HAL_JPEG_GetState()      \r\n\r\n     *** JPEG HAL driver macros list ***\r\n     ============================================= \r\n     [..]\r\n       Below the list of most used macros in JPEG HAL driver.\r\n       \r\n      (+) __HAL_JPEG_RESET_HANDLE_STATE : Reset JPEG handle state.\r\n      (+) __HAL_JPEG_ENABLE             : Enable the JPEG peripheral.\r\n      (+) __HAL_JPEG_DISABLE            : Disable the JPEG peripheral.\r\n      (+) __HAL_JPEG_GET_FLAG           : Check the specified JPEG status flag.\r\n      (+) __HAL_JPEG_CLEAR_FLAG         : Clear the specified JPEG status flag.\r\n      (+) __HAL_JPEG_ENABLE_IT          : Enable the specified JPEG Interrupt.\r\n      (+) __HAL_JPEG_DISABLE_IT         : Disable the specified JPEG Interrupt.\r\n      (+) __HAL_JPEG_GET_IT_SOURCE      : returns the state of the specified JPEG Interrupt (Enabled or disabled).\r\n\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup JPEG JPEG \r\n  * @brief JPEG HAL module driver.\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_JPEG_MODULE_ENABLED\r\n\r\n#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n\r\n/* Private define ------------------------------------------------------------*/\r\n/** @addtogroup JPEG_Private_Constants\r\n  * @{\r\n  */\r\n#define JPEG_TIMEOUT_VALUE  ((uint32_t)1000U)     /* 1s */\r\n#define JPEG_AC_HUFF_TABLE_SIZE  ((uint32_t)162U) /* Huffman AC table size : 162 codes*/\r\n#define JPEG_DC_HUFF_TABLE_SIZE  ((uint32_t)12U)  /* Huffman AC table size : 12 codes*/\r\n\r\n#define JPEG_FIFO_SIZE ((uint32_t)8U)             /* JPEG Input/Output HW FIFO size in words*/\r\n\r\n#define JPEG_INTERRUPT_MASK  ((uint32_t)0x0000007EU) /* JPEG Interrupt Mask*/\r\n\r\n#define JPEG_DMA_MASK     ((uint32_t)0x00001800U)     /* JPEG DMA request Mask*/\r\n#define JPEG_DMA_IDMA     ((uint32_t)JPEG_CR_IDMAEN)  /* DMA request for the input FIFO */\r\n#define JPEG_DMA_ODMA     ((uint32_t)JPEG_CR_ODMAEN)  /* DMA request for the output FIFO */ \r\n\r\n#define JPEG_CONTEXT_ENCODE          ((uint32_t)0x00000001U) /* JPEG context : operation is encoding*/\r\n#define JPEG_CONTEXT_DECODE          ((uint32_t)0x00000002U) /* JPEG context : operation is decoding*/\r\n#define JPEG_CONTEXT_OPERATION_MASK  ((uint32_t)0x00000003U) /* JPEG context : operation Mask */\r\n\r\n#define JPEG_CONTEXT_POLLING        ((uint32_t)0x00000004U)  /* JPEG context : Transfer use Polling */\r\n#define JPEG_CONTEXT_IT             ((uint32_t)0x00000008U)  /* JPEG context : Transfer use Interrupt */\r\n#define JPEG_CONTEXT_DMA            ((uint32_t)0x0000000CU)  /* JPEG context : Transfer use DMA */\r\n#define JPEG_CONTEXT_METHOD_MASK    ((uint32_t)0x0000000CU)  /* JPEG context : Transfer Mask */\r\n\r\n\r\n#define JPEG_CONTEXT_CONF_ENCODING  ((uint32_t)0x00000100U)  /* JPEG context : encoding config done */\r\n\r\n#define JPEG_CONTEXT_PAUSE_INPUT    ((uint32_t)0x00001000U)  /* JPEG context : Pause Input */\r\n#define JPEG_CONTEXT_PAUSE_OUTPUT   ((uint32_t)0x00002000U)  /* JPEG context : Pause Output */\r\n    \r\n#define JPEG_CONTEXT_CUSTOM_TABLES  ((uint32_t)0x00004000U)  /* JPEG context : Use custom quantization tables */\r\n\r\n#define JPEG_CONTEXT_ENDING_DMA     ((uint32_t)0x00008000U)  /* JPEG context : ending with DMA in progress */\r\n    \r\n#define JPEG_PROCESS_ONGOING        ((uint32_t)0x00000000U)  /* Process is on going */\r\n#define JPEG_PROCESS_DONE           ((uint32_t)0x00000001U)  /* Process is done (ends) */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/** @addtogroup JPEG_Private_Types\r\n  * @{\r\n  */\r\n\r\n/* \r\n JPEG Huffman Table Structure definition : \r\n This implementation of Huffman table structure is compliant with ISO/IEC 10918-1 standard , Annex C Huffman Table specification \r\n */ \r\ntypedef struct \r\n{\r\n  /* These two fields directly represent the contents of a JPEG DHT marker */\r\n  uint8_t Bits[16];        /*!< bits[k] = # of symbols with codes of length k bits, this parameter corresponds to BITS list in the Annex C */\r\n  \r\n  uint8_t HuffVal[162];    /*!< The symbols, in order of incremented code length, this parameter corresponds to HUFFVAL list in the Annex C */\r\n  \r\n  \r\n}JPEG_ACHuffTableTypeDef;\r\n\r\ntypedef struct \r\n{\r\n  /* These two fields directly represent the contents of a JPEG DHT marker */\r\n  uint8_t Bits[16];        /*!< bits[k] = # of symbols with codes of length k bits, this parameter corresponds to BITS list in the Annex C */\r\n  \r\n  uint8_t HuffVal[12];    /*!< The symbols, in order of incremented code length, this parameter corresponds to HUFFVAL list in the Annex C */\r\n  \r\n  \r\n}JPEG_DCHuffTableTypeDef;    \r\n    \r\ntypedef struct \r\n{\r\n  uint8_t CodeLength[JPEG_AC_HUFF_TABLE_SIZE];      /*!< Code length  */\r\n  \r\n  uint32_t HuffmanCode[JPEG_AC_HUFF_TABLE_SIZE];    /*!< HuffmanCode */\r\n  \r\n}JPEG_AC_HuffCodeTableTypeDef;\r\n\r\ntypedef struct \r\n{\r\n  uint8_t CodeLength[JPEG_DC_HUFF_TABLE_SIZE];        /*!< Code length  */\r\n  \r\n  uint32_t HuffmanCode[JPEG_DC_HUFF_TABLE_SIZE];    /*!< HuffmanCode */\r\n  \r\n}JPEG_DC_HuffCodeTableTypeDef;\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/** @addtogroup JPEG_Private_Macros\r\n  * @{\r\n  */\r\n#define JPEG_ENABLE_DMA(__HANDLE__,__DMA__)  ((__HANDLE__)->Instance->CR |= ((__DMA__) & JPEG_DMA_MASK))\r\n/*note  : To disable a DMA request we must use MODIFY_REG macro to avoid writing \"1\" to the FIFO flush bits \r\n         located in the same DMA request enable register (CR register). */     \r\n#define JPEG_DISABLE_DMA(__HANDLE__,__DMA__) MODIFY_REG((__HANDLE__)->Instance->CR, ((__DMA__) & JPEG_DMA_MASK), 0)\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @addtogroup JPEG_Private_Variables\r\n  * @{\r\n  */\r\n\r\nstatic const JPEG_DCHuffTableTypeDef JPEG_DCLUM_HuffTable =\r\n{\r\n  { 0, 1, 5, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 },   /*Bits*/\r\n  \r\n  { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb }           /*HUFFVAL */\r\n\r\n};\r\n\r\nstatic const JPEG_DCHuffTableTypeDef JPEG_DCCHROM_HuffTable =\r\n{\r\n  { 0, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 },  /*Bits*/\r\n  \r\n  { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb }          /*HUFFVAL */\r\n};\r\n\r\nstatic const JPEG_ACHuffTableTypeDef JPEG_ACLUM_HuffTable =\r\n{\r\n  { 0, 2, 1, 3, 3, 2, 4, 3, 5, 5, 4, 4, 0, 0, 1, 0x7d },  /*Bits*/\r\n  \r\n  {   0x01, 0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12,     /*HUFFVAL */\r\n      0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07,\r\n      0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xa1, 0x08,\r\n      0x23, 0x42, 0xb1, 0xc1, 0x15, 0x52, 0xd1, 0xf0,\r\n      0x24, 0x33, 0x62, 0x72, 0x82, 0x09, 0x0a, 0x16,\r\n      0x17, 0x18, 0x19, 0x1a, 0x25, 0x26, 0x27, 0x28,\r\n      0x29, 0x2a, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39,\r\n      0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49,\r\n      0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59,\r\n      0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69,\r\n      0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79,\r\n      0x7a, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89,\r\n      0x8a, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98,\r\n      0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,\r\n      0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6,\r\n      0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3, 0xc4, 0xc5,\r\n      0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2, 0xd3, 0xd4,\r\n      0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xe1, 0xe2,\r\n      0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea,\r\n      0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8,\r\n      0xf9, 0xfa }\r\n};\r\n\r\nstatic const JPEG_ACHuffTableTypeDef JPEG_ACCHROM_HuffTable =\r\n{\r\n  { 0, 2, 1, 2, 4, 4, 3, 4, 7, 5, 4, 4, 0, 1, 2, 0x77 },   /*Bits*/\r\n  \r\n  {   0x00, 0x01, 0x02, 0x03, 0x11, 0x04, 0x05, 0x21,      /*HUFFVAL */\r\n      0x31, 0x06, 0x12, 0x41, 0x51, 0x07, 0x61, 0x71,\r\n      0x13, 0x22, 0x32, 0x81, 0x08, 0x14, 0x42, 0x91,\r\n      0xa1, 0xb1, 0xc1, 0x09, 0x23, 0x33, 0x52, 0xf0,\r\n      0x15, 0x62, 0x72, 0xd1, 0x0a, 0x16, 0x24, 0x34,\r\n      0xe1, 0x25, 0xf1, 0x17, 0x18, 0x19, 0x1a, 0x26,\r\n      0x27, 0x28, 0x29, 0x2a, 0x35, 0x36, 0x37, 0x38,\r\n      0x39, 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48,\r\n      0x49, 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58,\r\n      0x59, 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,\r\n      0x69, 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78,\r\n      0x79, 0x7a, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,\r\n      0x88, 0x89, 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96,\r\n      0x97, 0x98, 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5,\r\n      0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4,\r\n      0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3,\r\n      0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2,\r\n      0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda,\r\n      0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9,\r\n      0xea, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8,\r\n      0xf9, 0xfa }\r\n};\r\n\r\n\r\n/* \r\n  These are the sample quantization tables given in JPEG spec ISO/IEC 10918-1 standard , section K.1.\r\n*/\r\nstatic const uint8_t JPEG_LUM_QuantTable[JPEG_QUANT_TABLE_SIZE] = \r\n{\r\n  16,  11,  10,  16,  24,  40,  51,  61,\r\n  12,  12,  14,  19,  26,  58,  60,  55,\r\n  14,  13,  16,  24,  40,  57,  69,  56,\r\n  14,  17,  22,  29,  51,  87,  80,  62,\r\n  18,  22,  37,  56,  68, 109, 103,  77,\r\n  24,  35,  55,  64,  81, 104, 113,  92,\r\n  49,  64,  78,  87, 103, 121, 120, 101,\r\n  72,  92,  95,  98, 112, 100, 103,  99\r\n};\r\nstatic const uint8_t JPEG_CHROM_QuantTable[JPEG_QUANT_TABLE_SIZE] = \r\n{\r\n  17,  18,  24,  47,  99,  99,  99,  99,\r\n  18,  21,  26,  66,  99,  99,  99,  99,\r\n  24,  26,  56,  99,  99,  99,  99,  99,\r\n  47,  66,  99,  99,  99,  99,  99,  99,\r\n  99,  99,  99,  99,  99,  99,  99,  99,\r\n  99,  99,  99,  99,  99,  99,  99,  99,\r\n  99,  99,  99,  99,  99,  99,  99,  99,\r\n  99,  99,  99,  99,  99,  99,  99,  99\r\n};\r\n\r\nstatic const uint8_t JPEG_ZIGZAG_ORDER[JPEG_QUANT_TABLE_SIZE] =\r\n{\r\n   0,   1,   8,  16,   9,   2,   3,  10,\r\n  17,  24,  32,  25,  18,  11,   4,   5,\r\n  12,  19,  26,  33,  40,  48,  41,  34,\r\n  27,  20,  13,   6,   7,  14,  21,  28,\r\n  35,  42,  49,  56,  57,  50,  43,  36,\r\n  29,  22,  15,  23,  30,  37,  44,  51,\r\n  58,  59,  52,  45,  38,  31,  39,  46,\r\n  53,  60,  61,  54,  47,  55,  62,  63\r\n};\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/* Private function prototypes -----------------------------------------------*/\r\n/** @addtogroup JPEG_Private_Functions_Prototypes\r\n  * @{\r\n  */\r\n\r\nstatic HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode, uint32_t *LastK);\r\nstatic HAL_StatusTypeDef JPEG_DCHuff_BitsVals_To_SizeCodes(JPEG_DCHuffTableTypeDef *DC_BitsValsTable, JPEG_DC_HuffCodeTableTypeDef *DC_SizeCodesTable);\r\nstatic HAL_StatusTypeDef JPEG_ACHuff_BitsVals_To_SizeCodes(JPEG_ACHuffTableTypeDef *AC_BitsValsTable, JPEG_AC_HuffCodeTableTypeDef *AC_SizeCodesTable);\r\nstatic HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC, uint32_t *DCTableAddress);\r\nstatic HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC, uint32_t *ACTableAddress);\r\nstatic HAL_StatusTypeDef JPEG_Set_HuffEnc_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0 ,  JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1);\r\nstatic void JPEG_Set_Huff_DHTMem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0 ,  JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1);\r\nstatic HAL_StatusTypeDef  JPEG_Set_Quantization_Mem(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable, uint32_t *QTableAddress);\r\nstatic void JPEG_SetColorYCBCR(JPEG_HandleTypeDef *hjpeg);\r\nstatic void JPEG_SetColorGrayScale(JPEG_HandleTypeDef *hjpeg);\r\nstatic void JPEG_SetColorCMYK(JPEG_HandleTypeDef *hjpeg);\r\n\r\nstatic void JPEG_Init_Process(JPEG_HandleTypeDef *hjpeg);\r\nstatic uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg);\r\nstatic void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWords);\r\nstatic void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWords);\r\nstatic uint32_t JPEG_GetQuality(JPEG_HandleTypeDef *hjpeg);\r\n\r\nstatic HAL_StatusTypeDef JPEG_DMA_StartProcess(JPEG_HandleTypeDef *hjpeg);\r\nstatic uint32_t JPEG_DMA_ContinueProcess(JPEG_HandleTypeDef *hjpeg);\r\nstatic uint32_t JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg);\r\nstatic void JPEG_DMAOutCpltCallback(DMA_HandleTypeDef *hdma);\r\nstatic void JPEG_DMAInCpltCallback(DMA_HandleTypeDef *hdma);\r\nstatic void JPEG_DMAErrorCallback(DMA_HandleTypeDef *hdma);\r\nstatic void JPEG_DMAOutAbortCallback(DMA_HandleTypeDef *hdma)  ;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup JPEG_Exported_Functions JPEG Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup JPEG_Exported_Functions_Group1 Initialization and de-initialization functions \r\n *  @brief    Initialization and de-initialization functions. \r\n *\r\n@verbatim    \r\n  ==============================================================================\r\n              ##### Initialization and de-initialization functions #####\r\n  ==============================================================================\r\n    [..]  This section provides functions allowing to:\r\n      (+) Initialize the JPEG peripheral and creates the associated handle\r\n      (+) DeInitialize the JPEG peripheral\r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the JPEG according to the specified\r\n  *         parameters in the JPEG_InitTypeDef and creates the associated handle.\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_JPEG_Init(JPEG_HandleTypeDef *hjpeg)\r\n{\r\n  /*Note : these intermediate variables are used to avoid MISRA warning \r\n  regarding rule 11.5 */\r\n  uint32_t acLum_huffmanTableAddr = (uint32_t)(&JPEG_ACLUM_HuffTable);\r\n  uint32_t dcLum_huffmanTableAddr = (uint32_t)(&JPEG_DCLUM_HuffTable);\r\n  uint32_t acChrom_huffmanTableAddr = (uint32_t)(&JPEG_ACCHROM_HuffTable);\r\n  uint32_t dcChrom_huffmanTableAddr = (uint32_t)(&JPEG_DCCHROM_HuffTable);\r\n  \r\n  /* Check the JPEG handle allocation */\r\n  if(hjpeg == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  if(hjpeg->State == HAL_JPEG_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    hjpeg->Lock = HAL_UNLOCKED;\r\n\r\n    /* Init the low level hardware : GPIO, CLOCK */\r\n    HAL_JPEG_MspInit(hjpeg);\r\n  }\r\n  \r\n  /* Change the JPEG state */\r\n  hjpeg->State = HAL_JPEG_STATE_BUSY;\r\n  \r\n  /* Start the JPEG Core*/\r\n  __HAL_JPEG_ENABLE(hjpeg);\r\n  \r\n  /* Stop the JPEG encoding/decoding process*/\r\n  hjpeg->Instance->CONFR0 &=  ~JPEG_CONFR0_START;\r\n  \r\n  /* Disable All Interrupts */\r\n  __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);\r\n  \r\n  /* Disable All DMA requests */\r\n  JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_MASK);\r\n  \r\n  /* Flush input and output FIFOs*/\r\n  hjpeg->Instance->CR |= JPEG_CR_IFF;\r\n  hjpeg->Instance->CR |= JPEG_CR_OFF;  \r\n  \r\n  /* Clear all flags */\r\n  __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_ALL);\r\n  \r\n  hjpeg->QuantTable0 = (uint8_t *)JPEG_LUM_QuantTable;\r\n  hjpeg->QuantTable1 = (uint8_t *)JPEG_CHROM_QuantTable;\r\n  hjpeg->QuantTable2 = NULL;\r\n  hjpeg->QuantTable3 = NULL;\r\n   \r\n  /* init the default Huffman tables*/\r\n  if(JPEG_Set_HuffEnc_Mem(hjpeg, (JPEG_ACHuffTableTypeDef *)acLum_huffmanTableAddr, (JPEG_DCHuffTableTypeDef *)dcLum_huffmanTableAddr, (JPEG_ACHuffTableTypeDef *)acChrom_huffmanTableAddr, (JPEG_DCHuffTableTypeDef *)dcChrom_huffmanTableAddr) != HAL_OK)\r\n  {\r\n    hjpeg->ErrorCode = HAL_JPEG_ERROR_HUFF_TABLE;\r\n    \r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Enable header processing*/\r\n  hjpeg->Instance->CONFR1 |= JPEG_CONFR1_HDR;\r\n  \r\n  /* Reset JpegInCount and JpegOutCount */\r\n  hjpeg->JpegInCount = 0;\r\n  hjpeg->JpegOutCount = 0;\r\n  \r\n  /* Change the JPEG state */\r\n  hjpeg->State = HAL_JPEG_STATE_READY;\r\n  \r\n  /* Reset the JPEG ErrorCode */\r\n  hjpeg->ErrorCode = HAL_JPEG_ERROR_NONE;\r\n  \r\n  /*Clear the context filelds*/\r\n  hjpeg->Context = 0;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the JPEG peripheral. \r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_JPEG_DeInit(JPEG_HandleTypeDef *hjpeg)\r\n{\r\n  /* Check the JPEG handle allocation */\r\n  if(hjpeg == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* DeInit the low level hardware: CLOCK, NVIC.*/\r\n  HAL_JPEG_MspDeInit(hjpeg);  \r\n  \r\n  /* Change the JPEG state */\r\n  hjpeg->State = HAL_JPEG_STATE_BUSY;\r\n  \r\n  /* Reset the JPEG ErrorCode */\r\n  hjpeg->ErrorCode = HAL_JPEG_ERROR_NONE;\r\n  \r\n  /* Reset JpegInCount and JpegOutCount */\r\n  hjpeg->JpegInCount = 0;\r\n  hjpeg->JpegOutCount = 0;\r\n  \r\n  /* Change the JPEG state */\r\n  hjpeg->State = HAL_JPEG_STATE_RESET;\r\n  \r\n  /*Clear the context fields*/\r\n  hjpeg->Context = 0;\r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hjpeg);\r\n\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the JPEG MSP.\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @retval None\r\n  */\r\n__weak void HAL_JPEG_MspInit(JPEG_HandleTypeDef *hjpeg)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hjpeg);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_JPEG_MspInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes JPEG MSP.\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @retval None\r\n  */\r\n__weak void HAL_JPEG_MspDeInit(JPEG_HandleTypeDef *hjpeg)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hjpeg);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_JPEG_MspDeInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup JPEG_Exported_Functions_Group2 Configuration functions \r\n *  @brief    JPEG Configuration functions. \r\n *\r\n@verbatim    \r\n  ==============================================================================\r\n              ##### Configuration functions #####\r\n  ==============================================================================\r\n    [..]  This section provides functions allowing to:\r\n      (+) HAL_JPEG_ConfigEncoding() : JPEG encoding configuration\r\n      (+) HAL_JPEG_GetInfo() :  Extract the image configuration from the JPEG header during the decoding\r\n      (+) HAL_JPEG_EnableHeaderParsing() :  Enable JPEG Header parsing for decoding\r\n      (+) HAL_JPEG_DisableHeaderParsing() : Disable JPEG Header parsing for decoding\r\n      (+) HAL_JPEG_SetUserQuantTables : Modify the default Quantization tables used for JPEG encoding.\r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Set the JPEG encoding configuration. \r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @param  pConf: pointer to a JPEG_ConfTypeDef structure that contains\r\n  *         the encoding configuration \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pConf)\r\n{\r\n  uint32_t error = HAL_OK;\r\n  uint32_t numberMCU, hfactor, vfactor,hMCU, vMCU;  \r\n  \r\n  /* Check the JPEG handle allocation */\r\n  if( (hjpeg == NULL) || (pConf == NULL) )\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  else\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_JPEG_COLORSPACE(pConf->ColorSpace));\r\n    assert_param(IS_JPEG_CHROMASUBSAMPLING(pConf->ChromaSubsampling));\r\n    assert_param(IS_JPEG_IMAGE_QUALITY(pConf->ImageQuality));\r\n  \r\n    /* Process Locked */\r\n    __HAL_LOCK(hjpeg);\r\n      \r\n    if(hjpeg->State == HAL_JPEG_STATE_READY)\r\n    {      \r\n      hjpeg->State = HAL_JPEG_STATE_BUSY;\r\n      \r\n      hjpeg->Conf.ColorSpace          =  pConf->ColorSpace;\r\n      hjpeg->Conf.ChromaSubsampling   =  pConf->ChromaSubsampling; \r\n      hjpeg->Conf.ImageHeight         =  pConf->ImageHeight;\r\n      hjpeg->Conf.ImageWidth          =  pConf->ImageWidth; \r\n      hjpeg->Conf.ImageQuality        =  pConf->ImageQuality;     \r\n      \r\n      /* Reset the Color Space : by default only one quantization table is used*/      \r\n      hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_COLORSPACE;\r\n      \r\n      /* Set Number of color components*/      \r\n      if(hjpeg->Conf.ColorSpace == JPEG_GRAYSCALE_COLORSPACE)\r\n      {        \r\n        /*Gray Scale is only one component 8x8 blocks i.e 4:4:4*/\r\n        hjpeg->Conf.ChromaSubsampling = JPEG_444_SUBSAMPLING;\r\n        \r\n        JPEG_SetColorGrayScale(hjpeg);\r\n        /* Set quantization table 0*/\r\n        error = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (uint32_t *)(hjpeg->Instance->QMEM0));       \r\n      }\r\n      else if(hjpeg->Conf.ColorSpace == JPEG_YCBCR_COLORSPACE) \r\n      {\r\n        /* \r\n           Set the Color Space for YCbCr : 2 quantization tables are used \r\n           one for Luminance(Y) and one for both Chrominances (Cb & Cr)\r\n        */\r\n        hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE_0;\r\n        \r\n        JPEG_SetColorYCBCR(hjpeg);\r\n        \r\n        /* Set quantization table 0*/\r\n        error  = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (uint32_t *)(hjpeg->Instance->QMEM0));\r\n        /*By default quantization table 0 for component 0 and quantization table 1 for both components 1 and 2*/\r\n        error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable1, (uint32_t *)(hjpeg->Instance->QMEM1));\r\n\r\n        if((hjpeg->Context & JPEG_CONTEXT_CUSTOM_TABLES) != 0) /*Use user customized quantization tables , 1 table per component*/\r\n        {\r\n          /* use 3 quantization tables , one for each component*/\r\n          hjpeg->Instance->CONFR1 &= (~JPEG_CONFR1_COLORSPACE);\r\n          hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE_1;\r\n          \r\n          error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable2, (uint32_t *)(hjpeg->Instance->QMEM2));\r\n \r\n          /*Use Quantization 1 table for component 1*/\r\n          hjpeg->Instance->CONFR5 &=  (~JPEG_CONFR6_QT);           \r\n          hjpeg->Instance->CONFR5 |=  JPEG_CONFR5_QT_0; \r\n          \r\n          /*Use Quantization 2 table for component 2*/\r\n          hjpeg->Instance->CONFR6 &=  (~JPEG_CONFR6_QT);\r\n          hjpeg->Instance->CONFR6 |=  JPEG_CONFR6_QT_1;                   \r\n        }\r\n      }\r\n      else if(hjpeg->Conf.ColorSpace == JPEG_CMYK_COLORSPACE)\r\n      {\r\n        JPEG_SetColorCMYK(hjpeg);\r\n        \r\n         /* Set quantization table 0*/\r\n        error  = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (uint32_t *)(hjpeg->Instance->QMEM0));\r\n        /*By default quantization table 0 for All components*/      \r\n        \r\n        if((hjpeg->Context & JPEG_CONTEXT_CUSTOM_TABLES) != 0) /*Use user customized quantization tables , 1 table per component*/\r\n        {\r\n          /* use 4 quantization tables , one for each component*/\r\n          hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE;\r\n          \r\n          error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable1, (uint32_t *)(hjpeg->Instance->QMEM1));\r\n          error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable2, (uint32_t *)(hjpeg->Instance->QMEM2));\r\n          error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable3, (uint32_t *)(hjpeg->Instance->QMEM3));\r\n          \r\n          /*Use Quantization 1 table for component 1*/\r\n          hjpeg->Instance->CONFR5 |=  JPEG_CONFR5_QT_0; \r\n          \r\n          /*Use Quantization 2 table for component 2*/\r\n          hjpeg->Instance->CONFR6 |=  JPEG_CONFR6_QT_1;\r\n          \r\n          /*Use Quantization 3 table for component 3*/\r\n          hjpeg->Instance->CONFR7 |=  JPEG_CONFR7_QT;                    \r\n        }\r\n      }\r\n\r\n      if(error != HAL_OK)\r\n      {\r\n        hjpeg->ErrorCode = HAL_JPEG_ERROR_QUANT_TABLE;\r\n        \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hjpeg);\r\n        \r\n        /* Set the JPEG State to ready */\r\n        hjpeg->State = HAL_JPEG_STATE_READY;\r\n        \r\n        return  HAL_ERROR;\r\n      }\r\n      /* Set the image size*/\r\n      hjpeg->Instance->CONFR1 |= ((hjpeg->Conf.ImageHeight & 0x0000FFFF) << 16); /* set the number of lines*/\r\n      hjpeg->Instance->CONFR3 |= ((hjpeg->Conf.ImageWidth & 0x0000FFFF) << 16);  /* set the number of pixels per line*/\r\n      \r\n      if(hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING)  /* 4:2:0*/\r\n      {\r\n        hfactor = 16;\r\n        vfactor = 16;\r\n      }\r\n      else if(hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING) /* 4:2:2*/\r\n      {\r\n        hfactor = 16;\r\n        vfactor = 8;        \r\n      }   \r\n      else /* Default is 8x8 MCU,  4:4:4*/\r\n      {\r\n        hfactor = 8;\r\n        vfactor = 8;          \r\n      }        \r\n      \r\n      hMCU = (hjpeg->Conf.ImageWidth / hfactor);\r\n      if((hjpeg->Conf.ImageWidth % hfactor) != 0)\r\n      {\r\n        hMCU++; /*+1 for horizontal incomplete MCU */                \r\n      }\r\n\r\n      vMCU = (hjpeg->Conf.ImageHeight / vfactor);\r\n      if((hjpeg->Conf.ImageHeight % vfactor) != 0)\r\n      {\r\n        vMCU++; /*+1 for vertical incomplete MCU */                \r\n      }\r\n      \r\n      numberMCU = (hMCU * vMCU) - 1; /* Bit Field JPEG_CONFR2_NMCU shall be set to NB_MCU - 1*/\r\n      /* Set the number of MCU*/\r\n      hjpeg->Instance->CONFR2 =  (numberMCU & JPEG_CONFR2_NMCU);\r\n      \r\n      hjpeg->Context |= JPEG_CONTEXT_CONF_ENCODING;\r\n\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hjpeg);\r\n      \r\n       /* Set the JPEG State to ready */\r\n      hjpeg->State = HAL_JPEG_STATE_READY;     \r\n      \r\n      /* Return function status */\r\n      return HAL_OK;\r\n    }\r\n    else\r\n    {\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hjpeg);\r\n      \r\n      /* Return function status */\r\n      return HAL_BUSY;\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Extract the image configuration from the JPEG header during the decoding\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @param  pInfo: pointer to a JPEG_ConfTypeDef structure that contains\r\n  *         The JPEG decoded header informations\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo)\r\n{\r\n  uint32_t yblockNb, cBblockNb, cRblockNb;\r\n  \r\n  /* Check the JPEG handle allocation */\r\n  if((hjpeg == NULL) || (pInfo == NULL))\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /*Read the conf parameters */\r\n  if((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == JPEG_CONFR1_NF_1)\r\n  {\r\n    pInfo->ColorSpace = JPEG_YCBCR_COLORSPACE;    \r\n  }    \r\n  else if((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == 0)\r\n  {\r\n    pInfo->ColorSpace = JPEG_GRAYSCALE_COLORSPACE;\r\n  }\r\n  else if((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == JPEG_CONFR1_NF)\r\n  {\r\n    pInfo->ColorSpace = JPEG_CMYK_COLORSPACE;    \r\n  }\r\n  \r\n  pInfo->ImageHeight = (hjpeg->Instance->CONFR1 & 0xFFFF0000U) >> 16;\r\n  pInfo->ImageWidth  = (hjpeg->Instance->CONFR3 & 0xFFFF0000U) >> 16;\r\n  \r\n  if((pInfo->ColorSpace == JPEG_YCBCR_COLORSPACE) || (pInfo->ColorSpace == JPEG_CMYK_COLORSPACE))\r\n  {\r\n    yblockNb  = (hjpeg->Instance->CONFR4 & JPEG_CONFR4_NB) >> 4;\r\n    cBblockNb = (hjpeg->Instance->CONFR5 & JPEG_CONFR5_NB) >> 4;\r\n    cRblockNb = (hjpeg->Instance->CONFR6 & JPEG_CONFR6_NB) >> 4;\r\n    \r\n    if((yblockNb == 1) && (cBblockNb == 0) && (cRblockNb == 0))\r\n    {\r\n      pInfo->ChromaSubsampling = JPEG_422_SUBSAMPLING; /*16x8 block*/\r\n    }\r\n    else if((yblockNb == 0) && (cBblockNb == 0) && (cRblockNb == 0))\r\n    {\r\n      pInfo->ChromaSubsampling = JPEG_444_SUBSAMPLING;\r\n    }\r\n    else if((yblockNb == 3) && (cBblockNb == 0) && (cRblockNb == 0))\r\n    {\r\n      pInfo->ChromaSubsampling = JPEG_420_SUBSAMPLING;\r\n    }\r\n    else /*Default is 4:4:4*/\r\n    {\r\n      pInfo->ChromaSubsampling = JPEG_444_SUBSAMPLING;\r\n    } \r\n  }\r\n  else \r\n  {\r\n    pInfo->ChromaSubsampling = JPEG_444_SUBSAMPLING;\r\n  }\r\n  \r\n  pInfo->ImageQuality = JPEG_GetQuality(hjpeg);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Enable JPEG Header parsing for decoding\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *               the configuration information for the JPEG.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_JPEG_EnableHeaderParsing(JPEG_HandleTypeDef *hjpeg)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hjpeg);\r\n  \r\n  if(hjpeg->State == HAL_JPEG_STATE_READY)\r\n  {\r\n    /* Change the JPEG state */\r\n    hjpeg->State = HAL_JPEG_STATE_BUSY;\r\n    \r\n    /* Enable header processing*/\r\n    hjpeg->Instance->CONFR1 |= JPEG_CONFR1_HDR;\r\n    \r\n    /* Process unlocked */\r\n    __HAL_UNLOCK(hjpeg);\r\n    \r\n    /* Change the JPEG state */\r\n    hjpeg->State = HAL_JPEG_STATE_READY;\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    /* Process unlocked */\r\n    __HAL_UNLOCK(hjpeg);\r\n\r\n    return HAL_BUSY;    \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Disable JPEG Header parsing for decoding\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *               the configuration information for the JPEG.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_JPEG_DisableHeaderParsing(JPEG_HandleTypeDef *hjpeg)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hjpeg);\r\n  \r\n  if(hjpeg->State == HAL_JPEG_STATE_READY)\r\n  {\r\n    /* Change the JPEG state */\r\n    hjpeg->State = HAL_JPEG_STATE_BUSY;\r\n    \r\n    /* Disable header processing*/\r\n    hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_HDR;\r\n    \r\n    /* Process unlocked */\r\n    __HAL_UNLOCK(hjpeg);\r\n    \r\n    /* Change the JPEG state */\r\n    hjpeg->State = HAL_JPEG_STATE_READY;\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    /* Process unlocked */\r\n    __HAL_UNLOCK(hjpeg);\r\n \r\n    return HAL_BUSY;    \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Modify the default Quantization tables used for JPEG encoding.\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @param  QTable0 : pointer to uint8_t , define the user quantification table for color component 1.\r\n  *                   If NULL assume no need to update  the table and no error return\r\n  * @param  QTable1 : pointer to uint8_t , define the user quantification table for color component 2. \r\n  *                   If NULL assume no need to update  the table and no error return.\r\n  * @param  QTable2 : pointer to uint8_t , define the user quantification table for color component 3, \r\n  *                   If NULL assume no need to update  the table and no error return. \r\n  * @param  QTable3 : pointer to uint8_t , define the user quantification table for color component 4. \r\n  *                   If NULL assume no need to update  the table and no error return.\r\n  *\r\n  * @retval HAL status\r\n  */\r\n\r\n\r\nHAL_StatusTypeDef  HAL_JPEG_SetUserQuantTables(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable0, uint8_t *QTable1, uint8_t *QTable2, uint8_t *QTable3)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hjpeg);\r\n  \r\n  if(hjpeg->State == HAL_JPEG_STATE_READY)\r\n  {\r\n    /* Change the DMA state */\r\n    hjpeg->State = HAL_JPEG_STATE_BUSY;\r\n    \r\n    hjpeg->Context |= JPEG_CONTEXT_CUSTOM_TABLES;\r\n    \r\n    hjpeg->QuantTable0 = QTable0;\r\n    hjpeg->QuantTable1 = QTable1;\r\n    hjpeg->QuantTable2 = QTable2;\r\n    hjpeg->QuantTable3 = QTable3;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hjpeg);\r\n    \r\n    /* Change the DMA state */\r\n    hjpeg->State = HAL_JPEG_STATE_READY; \r\n    \r\n    /* Return function status */\r\n    return HAL_OK;    \r\n  }\r\n  else\r\n  {\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hjpeg);\r\n    \r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup JPEG_Exported_Functions_Group3 encoding/decoding processing functions \r\n *  @brief   processing functions. \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                      ##### JPEG processing functions #####\r\n  ==============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) HAL_JPEG_Encode()     : JPEG encoding with polling process \r\n      (+) HAL_JPEG_Decode()     : JPEG decoding with polling process\r\n      (+) HAL_JPEG_Encode_IT()  : JPEG encoding with interrupt process\r\n      (+) HAL_JPEG_Decode_IT()  : JPEG decoding with interrupt process\r\n      (+) HAL_JPEG_Encode_DMA() : JPEG encoding with DMA process\r\n      (+) HAL_JPEG_Decode_DMA() : JPEG decoding with DMA process\r\n      (+) HAL_JPEG_Pause()      :   Pause the Input/Output processing \r\n      (+) HAL_JPEG_Resume()     :  Resume the JPEG Input/Output processing\r\n      (+) HAL_JPEG_ConfigInputBuffer()  : Config Encoding/Decoding Input Buffer\r\n      (+) HAL_JPEG_ConfigOutputBuffer() : Config Encoding/Decoding Output Buffer\r\n      (+) HAL_JPEG_Abort()              : Aborts the JPEG Encoding/Decoding\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Starts JPEG encoding with polling processing\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @param  pDataInMCU: Pointer to the Input buffer\r\n  * @param  InDataLength: size in bytes Input buffer\r\n  * @param  pDataOut: Pointer to the jpeg output data buffer\r\n  * @param  OutDataLength: size in bytes of the Output buffer\r\n  * @param  Timeout: Specify Timeout value \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef  HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param((InDataLength >= 4));\r\n  assert_param((OutDataLength >= 4));\r\n  \r\n  /* Check In/out buffer allocation and size */\r\n  if((hjpeg == NULL)     || (pDataInMCU == NULL) || (pDataOut == NULL) || \\\r\n    (InDataLength == 0) || (OutDataLength == 0))\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  /* Process locked */\r\n  __HAL_LOCK(hjpeg);\r\n  \r\n  if(hjpeg->State != HAL_JPEG_STATE_READY)\r\n  {\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hjpeg);\r\n    \r\n    return HAL_BUSY;    \r\n  }\r\n  \r\n  if(hjpeg->State == HAL_JPEG_STATE_READY)\r\n  {  \r\n    if((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING )\r\n    {      \r\n      /*Change JPEG state*/\r\n      hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING;\r\n      \r\n      /*Set the Context to Encode with Polling*/\r\n      hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);\r\n      hjpeg->Context |= (JPEG_CONTEXT_ENCODE | JPEG_CONTEXT_POLLING);\r\n      \r\n      /* Get tick */ \r\n      tickstart = HAL_GetTick();    \r\n      /*In/Out Data length must be multiple of 4 Bytes (1 word)*/\r\n      InDataLength = InDataLength - (InDataLength % 4);\r\n      OutDataLength = OutDataLength - (OutDataLength % 4);\r\n      \r\n      /*Store In/out buffers pointers and size*/\r\n      hjpeg->pJpegInBuffPtr = pDataInMCU;\r\n      hjpeg->pJpegOutBuffPtr = pDataOut;\r\n      hjpeg->InDataLength = InDataLength;\r\n      hjpeg->OutDataLength = OutDataLength;\r\n      \r\n      /*Reset In/out data counter */\r\n      hjpeg->JpegInCount = 0;    \r\n      hjpeg->JpegOutCount = 0;\r\n      \r\n      /*Init decoding process*/\r\n      JPEG_Init_Process(hjpeg);\r\n      \r\n      /*JPEG data processing : In/Out FIFO transfer*/\r\n      while((JPEG_Process(hjpeg) == JPEG_PROCESS_ONGOING))\r\n      {\r\n        if(Timeout != HAL_MAX_DELAY)\r\n        {\r\n          if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n          {\r\n            \r\n            /* Update error code */\r\n            hjpeg->ErrorCode |= HAL_JPEG_ERROR_TIMEOUT;          \r\n            \r\n            /* Process Unlocked */\r\n            __HAL_UNLOCK(hjpeg);\r\n            \r\n           /*Change JPEG state*/\r\n            hjpeg->State= HAL_JPEG_STATE_READY;             \r\n            \r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n      }\r\n      \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hjpeg);\r\n      \r\n      /*Change JPEG state*/\r\n      hjpeg->State= HAL_JPEG_STATE_READY;\r\n      \r\n    }else\r\n    {\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hjpeg);\r\n      \r\n      return HAL_ERROR;\r\n    }\r\n  }\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts JPEG decoding with polling processing\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @param  pDataIn: Pointer to the input data buffer \r\n  * @param  InDataLength: size in bytes Input buffer\r\n  * @param  pDataOutMCU: Pointer to the Output data buffer\r\n  * @param  OutDataLength: size in bytes of the Output buffer\r\n  * @param  Timeout: Specify Timeout value \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef  HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param((InDataLength >= 4));\r\n  assert_param((OutDataLength >= 4));\r\n  \r\n  /* Check In/out buffer allocation and size */\r\n  if((hjpeg == NULL)     || (pDataIn == NULL) || (pDataOutMCU == NULL) || \\\r\n     (InDataLength == 0) || (OutDataLength == 0))\r\n  {\r\n    return HAL_ERROR;\r\n  }  \r\n\r\n  /* Process Locked */\r\n  __HAL_LOCK(hjpeg);\r\n  \r\n  /* Get tick */ \r\n  tickstart = HAL_GetTick();\r\n  \r\n  if(hjpeg->State == HAL_JPEG_STATE_READY)\r\n  {\r\n    /*Change JPEG state*/\r\n    hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING;\r\n    \r\n    /*Set the Context to Decode with Polling*/\r\n    /*Set the Context to Encode with Polling*/\r\n    hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);\r\n    hjpeg->Context |= (JPEG_CONTEXT_DECODE | JPEG_CONTEXT_POLLING);  \r\n    \r\n    /*In/Out Data length must be multiple of 4 Bytes (1 word)*/\r\n    InDataLength = InDataLength - (InDataLength % 4);\r\n    OutDataLength = OutDataLength - (OutDataLength % 4);\r\n    \r\n    /*Store In/out buffers pointers and size*/\r\n    hjpeg->pJpegInBuffPtr = pDataIn;\r\n    hjpeg->pJpegOutBuffPtr = pDataOutMCU;\r\n    hjpeg->InDataLength = InDataLength;\r\n    hjpeg->OutDataLength = OutDataLength;\r\n    \r\n    /*Reset In/out data counter */\r\n    hjpeg->JpegInCount = 0;    \r\n    hjpeg->JpegOutCount = 0;\r\n    \r\n    /*Init decoding process*/\r\n    JPEG_Init_Process(hjpeg);\r\n\r\n    /*JPEG data processing : In/Out FIFO transfer*/\r\n    while((JPEG_Process(hjpeg) == JPEG_PROCESS_ONGOING))\r\n    {\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n        {\r\n          \r\n          /* Update error code */\r\n          hjpeg->ErrorCode |= HAL_JPEG_ERROR_TIMEOUT;  \r\n\r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hjpeg);\r\n\r\n          /*Change JPEG state*/\r\n          hjpeg->State= HAL_JPEG_STATE_READY;    \r\n\r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hjpeg);\r\n    \r\n    /*Change JPEG state*/\r\n    hjpeg->State= HAL_JPEG_STATE_READY; \r\n    \r\n  }else\r\n  {\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hjpeg);\r\n      \r\n    return HAL_BUSY;\r\n  }\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts JPEG encoding with interrupt processing\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @param  pDataInMCU: Pointer to the Input buffer\r\n  * @param  InDataLength: size in bytes Input buffer\r\n  * @param  pDataOut: Pointer to the jpeg output data buffer\r\n  * @param  OutDataLength: size in bytes of the Output buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef  HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength)\r\n{\r\n  /* Check the parameters */\r\n  assert_param((InDataLength >= 4));\r\n  assert_param((OutDataLength >= 4));\r\n  \r\n  /* Check In/out buffer allocation and size */\r\n  if((hjpeg == NULL)     || (pDataInMCU == NULL) || (pDataOut == NULL) || \\\r\n    (InDataLength == 0) || (OutDataLength == 0))\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hjpeg);\r\n  \r\n  if(hjpeg->State != HAL_JPEG_STATE_READY)\r\n  {\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hjpeg);\r\n    \r\n    return HAL_BUSY;    \r\n  }  \r\n  else \r\n  {\r\n    if((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING )\r\n    {\r\n      /*Change JPEG state*/\r\n      hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING;\r\n      \r\n      /*Set the Context to Encode with IT*/\r\n      hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);\r\n      hjpeg->Context |= (JPEG_CONTEXT_ENCODE | JPEG_CONTEXT_IT);    \r\n      \r\n      /*In/Out Data length must be multiple of 4 Bytes (1 word)*/\r\n      InDataLength = InDataLength - (InDataLength % 4);\r\n      OutDataLength = OutDataLength - (OutDataLength % 4);\r\n      \r\n      /*Store In/out buffers pointers and size*/\r\n      hjpeg->pJpegInBuffPtr = pDataInMCU;\r\n      hjpeg->pJpegOutBuffPtr = pDataOut;\r\n      hjpeg->InDataLength = InDataLength;\r\n      hjpeg->OutDataLength = OutDataLength;\r\n      \r\n      /*Reset In/out data counter */\r\n      hjpeg->JpegInCount = 0;    \r\n      hjpeg->JpegOutCount = 0;\r\n      \r\n      /*Init decoding process*/\r\n      JPEG_Init_Process(hjpeg);    \r\n      \r\n    }\r\n    else\r\n    {\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hjpeg);\r\n    \r\n      return HAL_ERROR;\r\n    }\r\n  }\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts JPEG decoding with interrupt processing\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @param  pDataIn: Pointer to the input data buffer \r\n  * @param  InDataLength: size in bytes Input buffer\r\n  * @param  pDataOutMCU: Pointer to the Output data buffer\r\n  * @param  OutDataLength: size in bytes of the Output buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef  HAL_JPEG_Decode_IT(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength)\r\n{\r\n  /* Check the parameters */\r\n  assert_param((InDataLength >= 4));\r\n  assert_param((OutDataLength >= 4));\r\n \r\n  /* Check In/out buffer allocation and size */\r\n  if((hjpeg == NULL)     || (pDataIn == NULL) || (pDataOutMCU == NULL) || \\\r\n     (InDataLength == 0) || (OutDataLength == 0))\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Process Locked */\r\n  __HAL_LOCK(hjpeg);\r\n  \r\n  if(hjpeg->State == HAL_JPEG_STATE_READY)\r\n  {\r\n    /*Change JPEG state*/\r\n    hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING;\r\n    \r\n    /*Set the Context to Decode with IT*/\r\n    hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);\r\n    hjpeg->Context |= (JPEG_CONTEXT_DECODE | JPEG_CONTEXT_IT);      \r\n    \r\n    /*In/Out Data length must be multiple of 4 Bytes (1 word)*/\r\n    InDataLength = InDataLength - (InDataLength % 4);\r\n    OutDataLength = OutDataLength - (OutDataLength % 4);\r\n    \r\n    /*Store In/out buffers pointers and size*/\r\n    hjpeg->pJpegInBuffPtr = pDataIn;\r\n    hjpeg->pJpegOutBuffPtr = pDataOutMCU;\r\n    hjpeg->InDataLength = InDataLength;\r\n    hjpeg->OutDataLength = OutDataLength;\r\n    \r\n    /*Reset In/out data counter */\r\n    hjpeg->JpegInCount = 0;    \r\n    hjpeg->JpegOutCount = 0;    \r\n    \r\n    /*Init decoding process*/\r\n    JPEG_Init_Process(hjpeg);    \r\n \r\n  }\r\n  else\r\n  {\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hjpeg);\r\n      \r\n    return HAL_BUSY;\r\n  }\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts JPEG encoding with DMA processing\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @param  pDataInMCU: Pointer to the Input buffer\r\n  * @param  InDataLength: size in bytes Input buffer\r\n  * @param  pDataOut: Pointer to the jpeg output data buffer\r\n  * @param  OutDataLength: size in bytes of the Output buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef  HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength)\r\n{\r\n  /* Check the parameters */\r\n  assert_param((InDataLength >= 4));\r\n  assert_param((OutDataLength >= 4));\r\n  \r\n  /* Check In/out buffer allocation and size */\r\n  if((hjpeg == NULL)     || (pDataInMCU == NULL) || (pDataOut == NULL) || \\\r\n    (InDataLength == 0) || (OutDataLength == 0))\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hjpeg);\r\n  \r\n  if(hjpeg->State != HAL_JPEG_STATE_READY)\r\n  {\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hjpeg);\r\n    \r\n    return HAL_BUSY;    \r\n  }  \r\n  else \r\n  {\r\n    if((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING )\r\n    {\r\n      /*Change JPEG state*/\r\n      hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING;\r\n      \r\n      /*Set the Context to Encode with DMA*/\r\n      hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);\r\n      hjpeg->Context |= (JPEG_CONTEXT_ENCODE | JPEG_CONTEXT_DMA);    \r\n      \r\n      /*Store In/out buffers pointers and size*/\r\n      hjpeg->pJpegInBuffPtr = pDataInMCU;\r\n      hjpeg->pJpegOutBuffPtr = pDataOut;\r\n      hjpeg->InDataLength = InDataLength;\r\n      hjpeg->OutDataLength = OutDataLength;\r\n      \r\n      /*Reset In/out data counter */\r\n      hjpeg->JpegInCount = 0;    \r\n      hjpeg->JpegOutCount = 0;\r\n      \r\n      /*Init decoding process*/\r\n      JPEG_Init_Process(hjpeg);\r\n      \r\n      /* JPEG encoding process using DMA */\r\n      JPEG_DMA_StartProcess(hjpeg);\r\n      \r\n    }\r\n    else\r\n    {\r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hjpeg);\r\n    \r\n      return HAL_ERROR;\r\n    }\r\n  }\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts JPEG decoding with DMA processing\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @param  pDataIn: Pointer to the input data buffer \r\n  * @param  InDataLength: size in bytes Input buffer\r\n  * @param  pDataOutMCU: Pointer to the Output data buffer\r\n  * @param  OutDataLength: size in bytes of the Output buffer\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef  HAL_JPEG_Decode_DMA(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength)\r\n{\r\n  /* Check the parameters */\r\n  assert_param((InDataLength >= 4));\r\n  assert_param((OutDataLength >= 4));\r\n  \r\n  /* Check In/out buffer allocation and size */\r\n  if((hjpeg == NULL)     || (pDataIn == NULL) || (pDataOutMCU == NULL) || \\\r\n    (InDataLength == 0) || (OutDataLength == 0))\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hjpeg);\r\n  \r\n  if(hjpeg->State == HAL_JPEG_STATE_READY)\r\n  {\r\n    /*Change JPEG state*/\r\n    hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING;\r\n    \r\n    /*Set the Context to Decode with DMA*/\r\n    hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK);\r\n    hjpeg->Context |= (JPEG_CONTEXT_DECODE | JPEG_CONTEXT_DMA);         \r\n    \r\n    /*Store In/out buffers pointers and size*/\r\n    hjpeg->pJpegInBuffPtr = pDataIn;\r\n    hjpeg->pJpegOutBuffPtr = pDataOutMCU;\r\n    hjpeg->InDataLength = InDataLength;\r\n    hjpeg->OutDataLength = OutDataLength;\r\n    \r\n    /*Reset In/out data counter */\r\n    hjpeg->JpegInCount = 0;    \r\n    hjpeg->JpegOutCount = 0;    \r\n    \r\n    /*Init decoding process*/\r\n    JPEG_Init_Process(hjpeg);\r\n    \r\n    /* JPEG decoding process using DMA */\r\n    JPEG_DMA_StartProcess(hjpeg);\r\n    \r\n  }\r\n  else\r\n  {\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hjpeg);\r\n    \r\n    return HAL_BUSY;\r\n  }\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Pause the JPEG Input/Output processing\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @param  XferSelection: This parameter can be one of the following values :\r\n  *                           JPEG_PAUSE_RESUME_INPUT : Pause Input processing\r\n  *                           JPEG_PAUSE_RESUME_OUTPUT: Pause Output processing\r\n  *                           JPEG_PAUSE_RESUME_INPUT_OUTPUT: Pause Input and Output processing\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef  HAL_JPEG_Pause(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection)\r\n{\r\n  uint32_t mask = 0;\r\n  \r\n  assert_param(IS_JPEG_PAUSE_RESUME_STATE(XferSelection));\r\n  \r\n  if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)\r\n  {  \r\n    if((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT)\r\n    {\r\n      hjpeg->Context |= JPEG_CONTEXT_PAUSE_INPUT;\r\n      mask |= JPEG_DMA_IDMA;\r\n    }\r\n    if((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT)\r\n    {\r\n      hjpeg->Context |= JPEG_CONTEXT_PAUSE_OUTPUT;\r\n      mask |= JPEG_DMA_ODMA;\r\n    }    \r\n    JPEG_DISABLE_DMA(hjpeg,mask);\r\n\r\n  }\r\n  else if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)\r\n  {  \r\n    \r\n    if((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT)\r\n    {\r\n      hjpeg->Context |= JPEG_CONTEXT_PAUSE_INPUT;\r\n      mask |= (JPEG_IT_IFT | JPEG_IT_IFNF); \r\n    }\r\n    if((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT)\r\n    {\r\n      hjpeg->Context |= JPEG_CONTEXT_PAUSE_OUTPUT;\r\n      mask |=  (JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC); \r\n    }    \r\n    __HAL_JPEG_DISABLE_IT(hjpeg,mask);\r\n\r\n  }\r\n   \r\n  /* Return function status */\r\n  return HAL_OK;    \r\n}\r\n\r\n/**\r\n  * @brief  Resume the JPEG Input/Output processing\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @param  XferSelection: This parameter can be one of the following values :\r\n  *                           JPEG_PAUSE_RESUME_INPUT : Resume Input processing\r\n  *                           JPEG_PAUSE_RESUME_OUTPUT: Resume Output processing\r\n  *                           JPEG_PAUSE_RESUME_INPUT_OUTPUT: Resume Input and Output processing\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef  HAL_JPEG_Resume(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection)\r\n{\r\n  uint32_t mask = 0;\r\n\r\n  assert_param(IS_JPEG_PAUSE_RESUME_STATE(XferSelection));  \r\n  \r\n  if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)\r\n  {\r\n    \r\n    if((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT)\r\n    {\r\n      hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_INPUT);\r\n      mask |= JPEG_DMA_IDMA;\r\n      \r\n      /*JPEG Input DMA transfer data number must be multiple of DMA buffer size \r\n        as the destination is a 32 bits register */\r\n      hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4);\r\n      \r\n      if(hjpeg->InDataLength > 0)\r\n      {  \r\n        /* Start DMA FIFO In transfer */\r\n        HAL_DMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR, hjpeg->InDataLength >> 2);\r\n      }\r\n      \r\n    }\r\n    if((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT)\r\n    {\r\n      hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_OUTPUT);\r\n      mask |= JPEG_DMA_ODMA;\r\n      \r\n      /* Start DMA FIFO Out transfer */\r\n      HAL_DMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr, hjpeg->OutDataLength >> 2);\r\n    }    \r\n    JPEG_ENABLE_DMA(hjpeg,mask);\r\n\r\n  }\r\n  else if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)\r\n  {  \r\n    if((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT)\r\n    {\r\n      hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_INPUT);\r\n      mask |= (JPEG_IT_IFT | JPEG_IT_IFNF); \r\n    }\r\n    if((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT)\r\n    {\r\n      hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_OUTPUT);\r\n      mask |=  (JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC); \r\n    }    \r\n    __HAL_JPEG_ENABLE_IT(hjpeg,mask);\r\n\r\n  }\r\n   \r\n  /* Return function status */\r\n  return HAL_OK;    \r\n}\r\n\r\n/**\r\n  * @brief  Config Encoding/Decoding Input Buffer.\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module.\r\n  * @param  pNewInputBuffer: Pointer to the new input data buffer\r\n  * @param  InDataLength: Size in bytes of the new Input data buffer \r\n  * @retval HAL status\r\n  */\r\nvoid HAL_JPEG_ConfigInputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewInputBuffer, uint32_t InDataLength)\r\n{\r\n  hjpeg->pJpegInBuffPtr =  pNewInputBuffer;\r\n  hjpeg->InDataLength = InDataLength;\r\n}\r\n\r\n/**\r\n  * @brief  Config Encoding/Decoding Output Buffer.\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module.\r\n  * @param  pNewOutputBuffer: Pointer to the new output data buffer\r\n  * @param  OutDataLength: Size in bytes of the new Output data buffer \r\n  * @retval HAL status\r\n  */\r\nvoid HAL_JPEG_ConfigOutputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputBuffer, uint32_t OutDataLength)\r\n{\r\n  hjpeg->pJpegOutBuffPtr = pNewOutputBuffer;\r\n  hjpeg->OutDataLength = OutDataLength;  \r\n}\r\n\r\n/**\r\n  * @brief  Aborts the JPEG Encoding/Decoding.\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg)\r\n{\r\n  uint32_t tickstart, tmpContext;  \r\n  \r\n  tmpContext = hjpeg->Context;\r\n  \r\n  /*Reset the Context operation and method*/\r\n  hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK | JPEG_CONTEXT_ENDING_DMA);\r\n    \r\n  if((tmpContext & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)\r\n  {\r\n    /* Stop the DMA In/out Xfer*/\r\n    HAL_DMA_Abort(hjpeg->hdmaout);\r\n    HAL_DMA_Abort(hjpeg->hdmain);\r\n  }\r\n  \r\n  /* Stop the JPEG encoding/decoding process*/\r\n  hjpeg->Instance->CONFR0 &=  ~JPEG_CONFR0_START;\r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  /* Check if the JPEG Codec is effectively disabled */\r\n  while(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_COF) != RESET)\r\n  {\r\n    /* Check for the Timeout */\r\n    if((HAL_GetTick() - tickstart ) > JPEG_TIMEOUT_VALUE)\r\n    {\r\n      /* Update error code */\r\n      hjpeg->ErrorCode |= HAL_JPEG_ERROR_TIMEOUT;\r\n      \r\n      /* Change the DMA state */\r\n      hjpeg->State = HAL_JPEG_STATE_TIMEOUT;\r\n      \r\n      /* Process Unlocked */\r\n      __HAL_UNLOCK(hjpeg);\r\n      \r\n      return HAL_TIMEOUT;\r\n    }\r\n  }  \r\n  \r\n  /* Disable All Interrupts */\r\n  __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);\r\n  \r\n  /* Disable All DMA requests */\r\n  JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_MASK);\r\n  \r\n  /* Flush input and output FIFOs*/\r\n  hjpeg->Instance->CR |= JPEG_CR_IFF;\r\n  hjpeg->Instance->CR |= JPEG_CR_OFF;  \r\n  \r\n  /* Clear all flags */\r\n  __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_ALL);\r\n\r\n  /* Reset JpegInCount and JpegOutCount */\r\n  hjpeg->JpegInCount = 0;\r\n  hjpeg->JpegOutCount = 0; \r\n  \r\n  /*Reset the Context Pause*/\r\n  hjpeg->Context &= ~(JPEG_CONTEXT_PAUSE_INPUT | JPEG_CONTEXT_PAUSE_OUTPUT);  \r\n  \r\n  /* Change the DMA state*/\r\n  hjpeg->State = HAL_JPEG_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hjpeg);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;  \r\n}\r\n  \r\n  \r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup JPEG_Exported_Functions_Group4 JPEG Decode/Encode callback functions \r\n *  @brief   JPEG process callback functions. \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n              #####  JPEG Decode/Encode callback functions  #####\r\n  ==============================================================================  \r\n    [..]  This section provides callback functions:\r\n      (+) HAL_JPEG_InfoReadyCallback()  : Decoding JPEG Info ready callback\r\n      (+) HAL_JPEG_EncodeCpltCallback() : Encoding complete callback.\r\n      (+) HAL_JPEG_DecodeCpltCallback() : Decoding complete callback.\r\n      (+) HAL_JPEG_ErrorCallback()      : JPEG error callback.\r\n      (+) HAL_JPEG_GetDataCallback()    : Get New Data chunk callback. \r\n      (+) HAL_JPEG_DataReadyCallback()  : Decoded/Encoded Data ready  callback. \r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Decoding JPEG Info ready callback.\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @param  pInfo: pointer to a JPEG_ConfTypeDef structure that contains\r\n  *         The JPEG decoded header informations\r\n  * @retval None\r\n  */\r\n__weak void HAL_JPEG_InfoReadyCallback(JPEG_HandleTypeDef *hjpeg,JPEG_ConfTypeDef *pInfo)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hjpeg);\r\n  UNUSED(pInfo);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_JPEG_HeaderParsingCpltCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  Encoding complete callback.\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @retval None\r\n  */\r\n__weak void HAL_JPEG_EncodeCpltCallback(JPEG_HandleTypeDef *hjpeg)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hjpeg);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_JPEG_EncodeCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Decoding complete callback.\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @retval None\r\n  */\r\n__weak void HAL_JPEG_DecodeCpltCallback(JPEG_HandleTypeDef *hjpeg)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hjpeg);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_JPEG_EncodeCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  JPEG error callback.\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @retval None\r\n  */\r\n __weak void HAL_JPEG_ErrorCallback(JPEG_HandleTypeDef *hjpeg)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hjpeg);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_JPEG_ErrorCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  Get New Data chunk callback.\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @param  NbDecodedData: Number of consummed data in the previous chunk in bytes\r\n  * @retval None\r\n  */\r\n __weak void HAL_JPEG_GetDataCallback(JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hjpeg);\r\n  UNUSED(NbDecodedData);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_JPEG_GetDataCallback could be implemented in the user file\r\n   */    \r\n}\r\n\r\n/**\r\n  * @brief  Decoded/Encoded Data ready  callback.\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @param  pDataOut: pointer to the output data buffer \r\n  * @param  OutDataLength: number in bytes of data available in the specified output buffer \r\n  * @retval None\r\n  */\r\n__weak void HAL_JPEG_DataReadyCallback (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hjpeg);\r\n  UNUSED(pDataOut);\r\n  UNUSED(OutDataLength);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_JPEG_DataReadyCallback could be implemented in the user file\r\n   */    \r\n}\r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n\r\n/** @defgroup JPEG_Exported_Functions_Group5 JPEG IRQ handler management  \r\n *  @brief   JPEG IRQ handler.\r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                ##### JPEG IRQ handler management #####\r\n  ==============================================================================  \r\n    [..]  This section provides JPEG IRQ handler function.\r\n      (+) HAL_JPEG_IRQHandler()  : handles JPEG interrupt request\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  This function handles JPEG interrupt request.\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @retval None\r\n  */\r\nvoid HAL_JPEG_IRQHandler(JPEG_HandleTypeDef *hjpeg)\r\n{\r\n  switch(hjpeg->State)\r\n  {\r\n    case HAL_JPEG_STATE_BUSY_ENCODING:\r\n    case HAL_JPEG_STATE_BUSY_DECODING:  \r\n      /* continue JPEG data encoding/Decoding*/\r\n      /* JPEG data processing : In/Out FIFO transfer*/\r\n      if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)\r\n      {  \r\n        JPEG_Process(hjpeg);\r\n      }\r\n      else if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)\r\n      {\r\n        JPEG_DMA_ContinueProcess(hjpeg);\r\n\r\n      }\r\n      \r\n      break;  \r\n    \r\n    default:\r\n      break;\r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup JPEG_Exported_Functions_Group6 Peripheral State functions \r\n *  @brief   Peripheral State functions. \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                    ##### Peripheral State and Error functions #####\r\n  ============================================================================== \r\n    [..]  This section provides JPEG State and Errors function.\r\n      (+) HAL_JPEG_GetState()  : permits to get in run-time the JPEG state.\r\n      (+) HAL_JPEG_GetError()  : Returns the JPEG error code if any.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Returns the JPEG state.\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @retval JPEG state\r\n  */\r\nHAL_JPEG_STATETypeDef HAL_JPEG_GetState(JPEG_HandleTypeDef *hjpeg)\r\n{\r\n  return hjpeg->State;\r\n}\r\n\r\n/**\r\n* @brief  Return the JPEG error code\r\n* @param  hjpeg : pointer to a JPEG_HandleTypeDef structure that contains\r\n  *              the configuration information for the specified JPEG.\r\n* @retval JPEG Error Code\r\n*/\r\nuint32_t HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg)\r\n{\r\n  return hjpeg->ErrorCode;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n\r\n/** @addtogroup JPEG_Private_Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Generates Huffman sizes/Codes Table from Bits/vals Table\r\n  * @param  Bits: pointer to bits table\r\n  * @param  Huffsize: pointer to sizes table\r\n  * @param  Huffcode: pointer to codes table\r\n  * @param  LastK: pointer to last Coeff (table dimmension) \r\n  * @retval HAL status\r\n  */   \r\nstatic HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode, uint32_t *LastK)\r\n{  \r\n  uint32_t i, p, l, code, si;\r\n   \r\n  /* Figure C.1  Generation of table of Huffman code sizes */\r\n  p = 0;\r\n  for (l = 0; l < 16; l++) \r\n  {\r\n    i = (uint32_t)Bits[l];\r\n    if ( (p + i) > 256)\r\n    {  /* check for table overflow */\r\n      return HAL_ERROR;\r\n    }\r\n    while (i != 0)\r\n    {\r\n      Huffsize[p++] = (uint8_t) l+1;\r\n      i--;\r\n    }\r\n  }\r\n  Huffsize[p] = 0;\r\n  *LastK = p; \r\n  \r\n  /* Figure C.2  Generation of table of Huffman codes */ \r\n  code = 0;\r\n  si = Huffsize[0];\r\n  p = 0;\r\n  while (Huffsize[p] != 0) \r\n  {\r\n    while (((uint32_t) Huffsize[p]) == si) \r\n    {\r\n      Huffcode[p++] = code;\r\n      code++;\r\n    }\r\n    /* code must fit in \"size\" bits (si), no code is allowed to be all ones*/\r\n    if (((uint32_t) code) >= (((uint32_t) 1) << si))\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n    code <<= 1;\r\n    si++;\r\n  }    \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Transform a Bits/Vals AC Huffman table to sizes/Codes huffman Table\r\n  *         that can programmed to the JPEG encoder registers\r\n  * @param  AC_BitsValsTable: pointer to AC huffman bits/vals table\r\n  * @param  AC_SizeCodesTable: pointer to AC huffman Sizes/Codes table \r\n  * @retval HAL status\r\n  */ \r\nstatic HAL_StatusTypeDef JPEG_ACHuff_BitsVals_To_SizeCodes(JPEG_ACHuffTableTypeDef *AC_BitsValsTable, JPEG_AC_HuffCodeTableTypeDef *AC_SizeCodesTable)\r\n{\r\n  HAL_StatusTypeDef error;\r\n  uint8_t huffsize[257];\r\n  uint32_t huffcode[257];\r\n  uint32_t k;\r\n  uint32_t l,lsb, msb;\r\n  uint32_t lastK;\r\n  \r\n  error = JPEG_Bits_To_SizeCodes(AC_BitsValsTable->Bits, huffsize, huffcode, &lastK);\r\n  if(error != HAL_OK)\r\n  {\r\n    return  error;\r\n  }\r\n  \r\n  /* Figure C.3  Ordering procedure for encoding procedure code tables */\r\n  k=0;\r\n   \r\n  while(k < lastK)\r\n  {\r\n    l = AC_BitsValsTable->HuffVal[k];\r\n    if(l == 0)\r\n    {\r\n      l = 160; /*l = 0x00 EOB code*/\r\n    }\r\n    else if(l == 0xF0)/* l = 0xF0 ZRL code*/\r\n    {\r\n      l = 161;\r\n    }  \r\n    else\r\n    {\r\n      msb = (l & 0xF0) >> 4;\r\n      lsb = (l & 0x0F);\r\n      l = (msb * 10) + lsb - 1; \r\n    }\r\n    if(l >= JPEG_AC_HUFF_TABLE_SIZE)\r\n    {\r\n      return HAL_ERROR; /* Huffman Table overflow error*/\r\n    }\r\n    else\r\n    {\r\n      AC_SizeCodesTable->HuffmanCode[l] = huffcode[k];\r\n      AC_SizeCodesTable->CodeLength[l] = huffsize[k] - 1;\r\n      k++;\r\n    }      \r\n  }\r\n\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Transform a Bits/Vals DC Huffman table to sizes/Codes huffman Table\r\n  *         that can programmed to the JPEG encoder registers\r\n  * @param  DC_BitsValsTable: pointer to DC huffman bits/vals table\r\n  * @param  DC_SizeCodesTable: pointer to DC huffman Sizes/Codes table \r\n  * @retval HAL status\r\n  */ \r\nstatic HAL_StatusTypeDef JPEG_DCHuff_BitsVals_To_SizeCodes(JPEG_DCHuffTableTypeDef *DC_BitsValsTable, JPEG_DC_HuffCodeTableTypeDef *DC_SizeCodesTable)\r\n{\r\n  HAL_StatusTypeDef error;\r\n\r\n  uint32_t k;\r\n  uint32_t l;\r\n  uint32_t lastK;\r\n  uint8_t huffsize[257];\r\n  uint32_t huffcode[257];  \r\n  error = JPEG_Bits_To_SizeCodes(DC_BitsValsTable->Bits, huffsize, huffcode, &lastK);\r\n  if(error != HAL_OK)\r\n  {\r\n    return  error;\r\n  }  \r\n  /* Figure C.3: ordering procedure for encoding procedure code tables */\r\n  k=0;\r\n    \r\n  while(k < lastK)\r\n  {\r\n    l = DC_BitsValsTable->HuffVal[k];\r\n    if(l >= JPEG_DC_HUFF_TABLE_SIZE)\r\n    {\r\n      return HAL_ERROR; /* Huffman Table overflow error*/\r\n    }\r\n    else\r\n    {\r\n      DC_SizeCodesTable->HuffmanCode[l] = huffcode[k];\r\n      DC_SizeCodesTable->CodeLength[l] = huffsize[k] - 1;\r\n      k++;\r\n    }      \r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Set the JPEG register with an DC huffman table at the given DC table address\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @param  HuffTableDC: pointer to DC huffman table\r\n  * @param  DCTableAddress: Encoder DC huffman table address it could be HUFFENC_DC0 or HUFFENC_DC1. \r\n  * @retval HAL status\r\n  */    \r\nstatic HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC, uint32_t *DCTableAddress)\r\n{\r\n  HAL_StatusTypeDef error = HAL_OK;\r\n  JPEG_DC_HuffCodeTableTypeDef dcSizeCodesTable;\r\n  uint32_t i, lsb, msb;\r\n  __IO uint32_t *address, *addressDef;\r\n  \r\n  if(DCTableAddress == (uint32_t *)(hjpeg->Instance->HUFFENC_DC0))\r\n  {\r\n    address = (hjpeg->Instance->HUFFENC_DC0 + (JPEG_DC_HUFF_TABLE_SIZE/2));\r\n  }\r\n  else if (DCTableAddress == (uint32_t *)(hjpeg->Instance->HUFFENC_DC1))\r\n  {\r\n    address = (hjpeg->Instance->HUFFENC_DC1 + (JPEG_DC_HUFF_TABLE_SIZE/2));\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  if(HuffTableDC != NULL)\r\n  {\r\n    error = JPEG_DCHuff_BitsVals_To_SizeCodes(HuffTableDC, &dcSizeCodesTable);\r\n    if(error != HAL_OK)\r\n    {\r\n      return  error;\r\n    }\r\n    addressDef = address;\r\n    *addressDef = 0x0FFF0FFF;\r\n    addressDef++;\r\n    *addressDef = 0x0FFF0FFF;\r\n    \r\n    i = JPEG_DC_HUFF_TABLE_SIZE;\r\n    while(i>0)\r\n    {       \r\n      i--;\r\n      address --;\r\n      msb = ((uint32_t)(((uint32_t)dcSizeCodesTable.CodeLength[i] & 0xF) << 8 )) | ((uint32_t)dcSizeCodesTable.HuffmanCode[i] & 0xFF);\r\n      i--;\r\n      lsb = ((uint32_t)(((uint32_t)dcSizeCodesTable.CodeLength[i] & 0xF) << 8 )) | ((uint32_t)dcSizeCodesTable.HuffmanCode[i] & 0xFF);\r\n\r\n      *address = lsb | (msb << 16);\r\n    }        \r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Set the JPEG register with an AC huffman table at the given AC table address\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @param  HuffTableAC: pointer to AC huffman table\r\n  * @param  ACTableAddress: Encoder AC huffman table address it could be HUFFENC_AC0 or HUFFENC_AC1. \r\n  * @retval HAL status\r\n  */  \r\nstatic HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC, uint32_t *ACTableAddress)\r\n{\r\n  HAL_StatusTypeDef error = HAL_OK;\r\n  JPEG_AC_HuffCodeTableTypeDef acSizeCodesTable;\r\n  uint32_t i, lsb, msb;\r\n  __IO uint32_t *address, *addressDef;\r\n  \r\n  if(ACTableAddress == (uint32_t *)(hjpeg->Instance->HUFFENC_AC0))\r\n  {\r\n    address = (hjpeg->Instance->HUFFENC_AC0 + (JPEG_AC_HUFF_TABLE_SIZE/2));\r\n  }\r\n  else if (ACTableAddress == (uint32_t *)(hjpeg->Instance->HUFFENC_AC1))\r\n  {\r\n    address = (hjpeg->Instance->HUFFENC_AC1 + (JPEG_AC_HUFF_TABLE_SIZE/2));\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;\r\n  } \r\n    \r\n  if(HuffTableAC != NULL)\r\n  {\r\n    error = JPEG_ACHuff_BitsVals_To_SizeCodes(HuffTableAC, &acSizeCodesTable);\r\n    if(error != HAL_OK)\r\n    {\r\n      return  error;\r\n    }\r\n    /* Default values settings : 162167 FFFh , 168175 FD0hFD7h */\r\n    /* Locations 162:175 of each AC table contain information used internally by the core */\r\n\r\n    addressDef = address;\r\n    for(i=0; i<3; i++)\r\n    {\r\n      *addressDef = 0x0FFF0FFF;\r\n      addressDef++;\r\n    }\r\n    *addressDef = 0x0FD10FD0;\r\n    addressDef++;\r\n    *addressDef = 0x0FD30FD2;\r\n    addressDef++;\r\n    *addressDef = 0x0FD50FD4;\r\n    addressDef++;\r\n    *addressDef = 0x0FD70FD6;\r\n    /* end of Locations 162:175  */\r\n\r\n    \r\n    i = JPEG_AC_HUFF_TABLE_SIZE;\r\n    while (i > 0)\r\n    {\r\n      i--;\r\n      address--;\r\n      msb = ((uint32_t)(((uint32_t)acSizeCodesTable.CodeLength[i] & 0xF) << 8 )) | ((uint32_t)acSizeCodesTable.HuffmanCode[i] & 0xFF);\r\n      i--;\r\n      lsb = ((uint32_t)(((uint32_t)acSizeCodesTable.CodeLength[i] & 0xF) << 8 )) | ((uint32_t)acSizeCodesTable.HuffmanCode[i] & 0xFF);\r\n      \r\n      *address = lsb | (msb << 16);       \r\n    }  \r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Configure the JPEG encoder register huffman tables to used during\r\n  *         the encdoing operation\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @param  HuffTableAC0: AC0 huffman table\r\n  * @param  HuffTableDC0: DC0 huffman table\r\n  * @param  HuffTableAC1: AC1 huffman table\r\n  * @param  HuffTableDC1: DC1 huffman table  \r\n  * @retval None\r\n  */ \r\nstatic HAL_StatusTypeDef JPEG_Set_HuffEnc_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0 ,  JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1)\r\n{\r\n  HAL_StatusTypeDef error = HAL_OK;\r\n  \r\n  JPEG_Set_Huff_DHTMem(hjpeg, HuffTableAC0, HuffTableDC0, HuffTableAC1, HuffTableDC1);\r\n  \r\n  if(HuffTableAC0 != NULL)\r\n  {\r\n    error = JPEG_Set_HuffAC_Mem(hjpeg, HuffTableAC0, (uint32_t *)(hjpeg->Instance->HUFFENC_AC0));\r\n    if(error != HAL_OK)\r\n    {\r\n      return  error;\r\n    }   \r\n  }\r\n  \r\n  if(HuffTableAC1 != NULL)\r\n  {\r\n    error = JPEG_Set_HuffAC_Mem(hjpeg, HuffTableAC1, (uint32_t *)(hjpeg->Instance->HUFFENC_AC1));\r\n    if(error != HAL_OK)\r\n    {\r\n      return  error;\r\n    }   \r\n  }\r\n  \r\n  if(HuffTableDC0 != NULL)\r\n  {\r\n    error = JPEG_Set_HuffDC_Mem(hjpeg, HuffTableDC0, (uint32_t *)hjpeg->Instance->HUFFENC_DC0);\r\n    if(error != HAL_OK)\r\n    {\r\n      return  error;\r\n    } \r\n  }\r\n  \r\n  if(HuffTableDC1 != NULL)\r\n  {\r\n    error = JPEG_Set_HuffDC_Mem(hjpeg, HuffTableDC1, (uint32_t *)hjpeg->Instance->HUFFENC_DC1);\r\n    if(error != HAL_OK)\r\n    {\r\n      return  error;\r\n    } \r\n  }\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Configure the JPEG register huffman tables to be included in the JPEG\r\n  *         file header (used for encoding only)\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @param  HuffTableAC0: AC0 huffman table\r\n  * @param  HuffTableDC0: DC0 huffman table\r\n  * @param  HuffTableAC1: AC1 huffman table\r\n  * @param  HuffTableDC1: DC1 huffman table  \r\n  * @retval None\r\n  */ \r\nstatic void JPEG_Set_Huff_DHTMem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0 ,  JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1)\r\n{\r\n  uint32_t value, index;\r\n  __IO uint32_t *address;\r\n  if(HuffTableDC0 != NULL)\r\n  {\r\n    /* DC0 Huffman Table : BITS*/\r\n    /* DC0 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address to DHTMEM + 3*/\r\n    address = (hjpeg->Instance->DHTMEM + 3); \r\n    index = 16;\r\n    while(index > 0)\r\n    {\r\n\r\n      *address = (((uint32_t)HuffTableDC0->Bits[index-1] & 0xFF) << 24)|\r\n                 (((uint32_t)HuffTableDC0->Bits[index-2] & 0xFF) << 16)|\r\n                 (((uint32_t)HuffTableDC0->Bits[index-3] & 0xFF) << 8) |\r\n                 ((uint32_t)HuffTableDC0->Bits[index-4] & 0xFF);\r\n      address--;\r\n      index -=4;      \r\n      \r\n    }\r\n    /* DC0 Huffman Table : Val*/\r\n    /* DC0 VALS is a 12 Bytes table i.e 3x32bits words from DHTMEM base address +4 to DHTMEM + 6 */\r\n    address = (hjpeg->Instance->DHTMEM + 6);\r\n    index = 12;\r\n    while(index > 0)\r\n    {\r\n      *address = (((uint32_t)HuffTableDC0->HuffVal[index-1] & 0xFF) << 24)|\r\n                 (((uint32_t)HuffTableDC0->HuffVal[index-2] & 0xFF) << 16)|\r\n                 (((uint32_t)HuffTableDC0->HuffVal[index-3] & 0xFF) << 8) |\r\n                 ((uint32_t)HuffTableDC0->HuffVal[index-4] & 0xFF);\r\n      address--;\r\n      index -=4;    \r\n    }    \r\n  }\r\n\r\n  if(HuffTableAC0 != NULL)\r\n  {\r\n    /* AC0 Huffman Table : BITS*/\r\n    /* AC0 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address + 7 to DHTMEM + 10*/\r\n    address = (hjpeg->Instance->DHTMEM + 10); \r\n    index = 16;\r\n    while(index > 0)\r\n    {\r\n\r\n      *address = (((uint32_t)HuffTableAC0->Bits[index-1] & 0xFF) << 24)|\r\n                 (((uint32_t)HuffTableAC0->Bits[index-2] & 0xFF) << 16)|\r\n                 (((uint32_t)HuffTableAC0->Bits[index-3] & 0xFF) << 8) |\r\n                 ((uint32_t)HuffTableAC0->Bits[index-4] & 0xFF);\r\n      address--;\r\n      index -=4;      \r\n      \r\n    }\r\n    /* AC0 Huffman Table : Val*/\r\n    /* AC0 VALS is a 162 Bytes table i.e 41x32bits words from DHTMEM base address + 11 to DHTMEM + 51 */\r\n    /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 51) belong to AC0 VALS table */\r\n    address = (hjpeg->Instance->DHTMEM + 51);    \r\n    value = *address & 0xFFFF0000U;\r\n    value = value | (((uint32_t)HuffTableAC0->HuffVal[161] & 0xFF) << 8) | ((uint32_t)HuffTableAC0->HuffVal[160] & 0xFF);\r\n    *address = value;\r\n    \r\n    /*continue setting 160 AC0 huffman values */\r\n    address--; /* address = hjpeg->Instance->DHTMEM + 50*/\r\n    index = 160;\r\n    while(index > 0)\r\n    {\r\n      *address = (((uint32_t)HuffTableAC0->HuffVal[index-1] & 0xFF) << 24)|\r\n                 (((uint32_t)HuffTableAC0->HuffVal[index-2] & 0xFF) << 16)|\r\n                 (((uint32_t)HuffTableAC0->HuffVal[index-3] & 0xFF) << 8) |\r\n                 ((uint32_t)HuffTableAC0->HuffVal[index-4] & 0xFF);\r\n      address--;\r\n      index -=4;    \r\n    }    \r\n  }\r\n\r\n  if(HuffTableDC1 != NULL)\r\n  {\r\n    /* DC1 Huffman Table : BITS*/\r\n    /* DC1 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM + 51 base address to DHTMEM + 55*/\r\n    /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 51) belong to DC1 Bits table */\r\n    address = (hjpeg->Instance->DHTMEM + 51);\r\n    value = *address & 0x0000FFFFU;\r\n    value = value | (((uint32_t)HuffTableDC1->Bits[1] & 0xFF) << 24) | (((uint32_t)HuffTableDC1->Bits[0] & 0xFF) << 16);\r\n    *address = value;\r\n    \r\n    /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 55) belong to DC1 Bits table */\r\n    address = (hjpeg->Instance->DHTMEM + 55);\r\n    value = *address & 0xFFFF0000U;\r\n    value = value | (((uint32_t)HuffTableDC1->Bits[15] & 0xFF) << 8) | ((uint32_t)HuffTableDC1->Bits[14] & 0xFF);    \r\n    *address = value;\r\n    \r\n    /*continue setting 12 DC1 huffman Bits from DHTMEM + 54 down to DHTMEM + 52*/\r\n    address--;\r\n    index = 12;\r\n    while(index > 0)\r\n    {\r\n\r\n      *address = (((uint32_t)HuffTableDC1->Bits[index+1] & 0xFF) << 24)|\r\n                 (((uint32_t)HuffTableDC1->Bits[index] & 0xFF) << 16)|\r\n                 (((uint32_t)HuffTableDC1->Bits[index-1] & 0xFF) << 8) |\r\n                 ((uint32_t)HuffTableDC1->Bits[index-2] & 0xFF);\r\n      address--;\r\n      index -=4;      \r\n      \r\n    }\r\n    /* DC1 Huffman Table : Val*/\r\n    /* DC1 VALS is a 12 Bytes table i.e 3x32bits words from DHTMEM base address +55 to DHTMEM + 58 */\r\n    /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 55) belong to DC1 Val table */\r\n    address = (hjpeg->Instance->DHTMEM + 55);\r\n    value = *address & 0x0000FFFF;\r\n    value = value | (((uint32_t)HuffTableDC1->HuffVal[1] & 0xFF) << 24) | (((uint32_t)HuffTableDC1->HuffVal[0] & 0xFF) << 16);\r\n    *address = value;\r\n    \r\n    /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 58) belong to DC1 Val table */\r\n    address = (hjpeg->Instance->DHTMEM + 58);\r\n    value = *address & 0xFFFF0000U;\r\n    value = value | (((uint32_t)HuffTableDC1->HuffVal[11] & 0xFF) << 8) | ((uint32_t)HuffTableDC1->HuffVal[10] & 0xFF);\r\n    *address = value;\r\n    \r\n    /*continue setting 8 DC1 huffman val from DHTMEM + 57 down to DHTMEM + 56*/\r\n    address--;\r\n    index = 8;\r\n    while(index > 0)\r\n    {\r\n      *address = (((uint32_t)HuffTableDC1->HuffVal[index+1] & 0xFF) << 24)|\r\n                 (((uint32_t)HuffTableDC1->HuffVal[index] & 0xFF) << 16)|\r\n                 (((uint32_t)HuffTableDC1->HuffVal[index-1] & 0xFF) << 8) |\r\n                 ((uint32_t)HuffTableDC1->HuffVal[index-2] & 0xFF);\r\n      address--;\r\n      index -=4;    \r\n    }    \r\n  }\r\n  \r\n  if(HuffTableAC1 != NULL)\r\n  {\r\n    /* AC1 Huffman Table : BITS*/\r\n    /* AC1 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address + 58 to DHTMEM + 62*/\r\n    /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 58) belong to AC1 Bits table */\r\n    address = (hjpeg->Instance->DHTMEM + 58);\r\n    value = *address & 0x0000FFFFU;\r\n    value = value | (((uint32_t)HuffTableAC1->Bits[1] & 0xFF) << 24) | (((uint32_t)HuffTableAC1->Bits[0] & 0xFF) << 16);\r\n    *address = value;\r\n    \r\n    /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 62) belong to Bits Val table */\r\n    address = (hjpeg->Instance->DHTMEM + 62);\r\n    value = *address & 0xFFFF0000U;\r\n    value = value | (((uint32_t)HuffTableAC1->Bits[15] & 0xFF) << 8) | ((uint32_t)HuffTableAC1->Bits[14] & 0xFF);\r\n    *address = value;\r\n    \r\n    /*continue setting 12 AC1 huffman Bits from DHTMEM + 61 down to DHTMEM + 59*/\r\n    address--;\r\n    index = 12;\r\n    while(index > 0)\r\n    {\r\n\r\n      *address = (((uint32_t)HuffTableAC1->Bits[index+1] & 0xFF) << 24)|\r\n                 (((uint32_t)HuffTableAC1->Bits[index] & 0xFF) << 16)|\r\n                 (((uint32_t)HuffTableAC1->Bits[index-1] & 0xFF) << 8) |\r\n                 ((uint32_t)HuffTableAC1->Bits[index-2] & 0xFF);\r\n      address--;\r\n      index -=4;      \r\n      \r\n    }\r\n    /* AC1 Huffman Table : Val*/\r\n    /* AC1 VALS is a 162 Bytes table i.e 41x32bits words from DHTMEM base address + 62 to DHTMEM + 102 */\r\n    /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 62) belong to AC1 VALS table */\r\n    address = (hjpeg->Instance->DHTMEM + 62);    \r\n    value = *address & 0x0000FFFF;\r\n    value = value | (((uint32_t)HuffTableAC1->HuffVal[1] & 0xFF) << 24) | (((uint32_t)HuffTableAC1->HuffVal[0] & 0xFF) << 16);\r\n    *address = value;\r\n    \r\n    /*continue setting 160 AC1 huffman values from DHTMEM + 63 to DHTMEM+102 */\r\n    address = (hjpeg->Instance->DHTMEM + 102);\r\n    index = 160;\r\n    while(index > 0)\r\n    {\r\n      *address = (((uint32_t)HuffTableAC1->HuffVal[index+1] & 0xFF) << 24)|\r\n                 (((uint32_t)HuffTableAC1->HuffVal[index] & 0xFF) << 16)|\r\n                 (((uint32_t)HuffTableAC1->HuffVal[index-1] & 0xFF) << 8) |\r\n                 ((uint32_t)HuffTableAC1->HuffVal[index-2] & 0xFF);\r\n      address--;\r\n      index -=4;    \r\n    }    \r\n  }  \r\n}\r\n\r\n/**\r\n  * @brief  Configure the JPEG registers with a given quantization table\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @param  QTable: pointer to an array of 64 bytes giving the quantization table\r\n  * @param  QTableAddress: destination quantization address in the JPEG peripheral\r\n  *         it could be QMEM0, QMEM1, QMEM2 or QMEM3         \r\n  * @retval None\r\n  */\r\nstatic HAL_StatusTypeDef  JPEG_Set_Quantization_Mem(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable, uint32_t *QTableAddress)\r\n{\r\n  uint32_t i, j, *tableAddress, quantRow, quantVal, ScaleFactor;\r\n  \r\n  if((QTableAddress == ((uint32_t *)(hjpeg->Instance->QMEM0))) ||\r\n     (QTableAddress == ((uint32_t *)(hjpeg->Instance->QMEM1))) ||\r\n     (QTableAddress == ((uint32_t *)(hjpeg->Instance->QMEM2))) ||\r\n     (QTableAddress == ((uint32_t *)(hjpeg->Instance->QMEM3))))  \r\n  {\r\n    tableAddress = QTableAddress;  \r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  if ((hjpeg->Conf.ImageQuality >= 50) && (hjpeg->Conf.ImageQuality <= 100)) \r\n  {\r\n    ScaleFactor = 200 - (hjpeg->Conf.ImageQuality * 2);\r\n  }\r\n  else if (hjpeg->Conf.ImageQuality > 0)\r\n  {  \r\n    ScaleFactor = ((uint32_t) 5000) / ((uint32_t) hjpeg->Conf.ImageQuality);\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;  \r\n  }\r\n\r\n  /*Quantization_table = (Standard_quanization_table * ScaleFactor + 50) / 100*/\r\n  i = 0;\r\n  while( i < JPEG_QUANT_TABLE_SIZE)\r\n  {\r\n    quantRow = 0;\r\n    for(j=0; j<4; j++)\r\n    {\r\n      /* Note that the quantization coefficients must be specified in the table in zigzag order */\r\n      quantVal = ((((uint32_t) QTable[JPEG_ZIGZAG_ORDER[i+j]]) * ScaleFactor) + 50) / 100;\r\n      \r\n      if(quantVal == 0)\r\n      {\r\n        quantVal = 1;  \r\n      }\r\n      else if (quantVal > 255)\r\n      {\r\n        quantVal = 255;\r\n      }\r\n      \r\n      quantRow |= ((quantVal & 0xFF) << (8 * j));   \r\n    }\r\n\r\n    i += 4;  \r\n    *tableAddress = quantRow;\r\n    tableAddress ++;        \r\n  }\r\n\r\n  /* Return function status */\r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Configure the JPEG registers for YCbCr color space\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @retval None\r\n  */\r\nstatic void JPEG_SetColorYCBCR(JPEG_HandleTypeDef *hjpeg) \r\n{\r\n  uint32_t ySamplingH;\r\n  uint32_t ySamplingV;\r\n  uint32_t yblockNb;\r\n  \r\n  /*Set Number of color components to 3*/\r\n  hjpeg->Instance->CONFR1 &=  ~JPEG_CONFR1_NF;\r\n  hjpeg->Instance->CONFR1 |=  JPEG_CONFR1_NF_1;\r\n        \r\n  /* compute MCU block size and Y, Cb ,Cr sampling factors*/ \r\n  if(hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING) \r\n  {          \r\n    ySamplingH  = JPEG_CONFR4_HSF_1;   /* Hs = 2*/          \r\n    ySamplingV  = JPEG_CONFR4_VSF_1;   /* Vs = 2*/\r\n          \r\n    yblockNb  = 0x30; /* 4 blocks of 8x8*/\r\n  }\r\n  else if(hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING)\r\n  {          \r\n    ySamplingH  = JPEG_CONFR4_HSF_1;   /* Hs = 2*/          \r\n    ySamplingV  = JPEG_CONFR4_VSF_0;   /* Vs = 1*/\r\n          \r\n    yblockNb  = 0x10; /* 2 blocks of 8x8*/          \r\n  } \r\n  else /*JPEG_444_SUBSAMPLING and default*/\r\n  {\r\n    ySamplingH  = JPEG_CONFR4_HSF_0;   /* Hs = 1*/          \r\n    ySamplingV  = JPEG_CONFR4_VSF_0;   /* Vs = 1*/\r\n          \r\n    yblockNb  = 0; /* 1 block of 8x8*/\r\n  }  \r\n        \r\n  hjpeg->Instance->CONFR1 &= ~(JPEG_CONFR1_NF | JPEG_CONFR1_NS);\r\n  hjpeg->Instance->CONFR1 |=  (JPEG_CONFR1_NF_1 | JPEG_CONFR1_NS_1);\r\n  \r\n  /*Reset CONFR4 register*/\r\n  hjpeg->Instance->CONFR4 =  0;\r\n  /*Set Horizental and Vertical  sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 0*/\r\n  hjpeg->Instance->CONFR4 |=  (ySamplingH | ySamplingV | (yblockNb & JPEG_CONFR4_NB) );\r\n        \r\n  /*Reset CONFR5 register*/\r\n  hjpeg->Instance->CONFR5 =  0;\r\n  /*Set Horizental and Vertical  sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 1*/\r\n  hjpeg->Instance->CONFR5 |=  (JPEG_CONFR5_HSF_0 | JPEG_CONFR5_VSF_0 | JPEG_CONFR5_QT_0 | JPEG_CONFR5_HA | JPEG_CONFR5_HD);\r\n        \r\n  /*Reset CONFR6 register*/\r\n  hjpeg->Instance->CONFR6 =  0;\r\n  /*Set Horizental and Vertical  sampling factor and number of blocks for component 2*/\r\n  /* In YCBCR , by default, both chrominance components (component 1 and component 2) use the same Quantization table (table 1) */\r\n  /* In YCBCR , both chrominance components (component 1 and component 2) use the same Huffman tables (table 1) */\r\n  hjpeg->Instance->CONFR6 |=  (JPEG_CONFR6_HSF_0 | JPEG_CONFR6_VSF_0 | JPEG_CONFR6_QT_0 | JPEG_CONFR6_HA | JPEG_CONFR6_HD);\r\n  \r\n}\r\n\r\n/**\r\n  * @brief  Configure the JPEG registers for GrayScale color space\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @retval None\r\n  */\r\nstatic void JPEG_SetColorGrayScale(JPEG_HandleTypeDef *hjpeg)\r\n{  \r\n  /*Set Number of color components to 1*/\r\n  hjpeg->Instance->CONFR1 &= ~(JPEG_CONFR1_NF | JPEG_CONFR1_NS);\r\n  \r\n  /*in GrayScale use 1 single Quantization table (Table 0)*/\r\n  /*in GrayScale use only one couple of AC/DC huffman table (table 0)*/\r\n  \r\n  /*Reset CONFR4 register*/\r\n  hjpeg->Instance->CONFR4 =  0;\r\n  /*Set Horizental and Vertical  sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 0*/\r\n  hjpeg->Instance->CONFR4 |=  JPEG_CONFR4_HSF_0 | JPEG_CONFR4_VSF_0 ;\r\n}\r\n\r\n/**\r\n  * @brief  Configure the JPEG registers for CMYK color space\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @retval None\r\n  */\r\nstatic void JPEG_SetColorCMYK(JPEG_HandleTypeDef *hjpeg)\r\n{\r\n  uint32_t ySamplingH;\r\n  uint32_t ySamplingV;\r\n  uint32_t yblockNb;\r\n  \r\n  /*Set Number of color components to 4*/\r\n  hjpeg->Instance->CONFR1 |= (JPEG_CONFR1_NF | JPEG_CONFR1_NS);\r\n        \r\n  /* compute MCU block size and Y, Cb ,Cr sampling factors*/ \r\n  if(hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING) \r\n  {          \r\n    ySamplingH  = JPEG_CONFR4_HSF_1;   /* Hs = 2*/          \r\n    ySamplingV  = JPEG_CONFR4_VSF_1;   /* Vs = 2*/\r\n          \r\n    yblockNb  = 0x30; /* 4 blocks of 8x8*/\r\n  }\r\n  else if(hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING)\r\n  {          \r\n    ySamplingH  = JPEG_CONFR4_HSF_1;   /* Hs = 2*/          \r\n    ySamplingV  = JPEG_CONFR4_VSF_0;   /* Vs = 1*/\r\n          \r\n    yblockNb  = 0x10; /* 2 blocks of 8x8*/          \r\n  }\r\n  else /*JPEG_444_SUBSAMPLING and default*/\r\n  {          \r\n    ySamplingH  = JPEG_CONFR4_HSF_0;   /* Hs = 1*/          \r\n    ySamplingV  = JPEG_CONFR4_VSF_0;   /* Vs = 1*/\r\n          \r\n    yblockNb  = 0; /* 1 block of 8x8*/\r\n  } \r\n  \r\n  /*Reset CONFR4 register*/\r\n  hjpeg->Instance->CONFR4 =  0;\r\n  /*Set Horizental and Vertical  sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 0*/\r\n  hjpeg->Instance->CONFR4 |=  (ySamplingH | ySamplingV | (yblockNb & JPEG_CONFR4_NB) );\r\n        \r\n  /*Reset CONFR5 register*/\r\n  hjpeg->Instance->CONFR5 =  0;\r\n  /*Set Horizental and Vertical  sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 1*/\r\n  hjpeg->Instance->CONFR5 |=  (JPEG_CONFR5_HSF_0 | JPEG_CONFR5_VSF_0);\r\n        \r\n  /*Reset CONFR6 register*/\r\n  hjpeg->Instance->CONFR6 =  0;\r\n  /*Set Horizental and Vertical  sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 2*/\r\n  hjpeg->Instance->CONFR6 |=  (JPEG_CONFR6_HSF_0 | JPEG_CONFR6_VSF_0);\r\n        \r\n  /*Reset CONFR7 register*/\r\n  hjpeg->Instance->CONFR7 =  0;\r\n  /*Set Horizental and Vertical  sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 3*/\r\n  hjpeg->Instance->CONFR7 |=  (JPEG_CONFR7_HSF_0 | JPEG_CONFR7_VSF_0);\r\n}\r\n\r\n/**\r\n  * @brief  Init the JPEG encoding/decoding process in case of Polling or Interrupt and DMA\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @retval None\r\n  */\r\nstatic void JPEG_Init_Process(JPEG_HandleTypeDef *hjpeg)\r\n{\r\n  /*Reset pause*/\r\n  hjpeg->Context &= (~(JPEG_CONTEXT_PAUSE_INPUT | JPEG_CONTEXT_PAUSE_OUTPUT));\r\n  \r\n  if((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)\r\n  {\r\n    /*Set JPEG Codec to Decoding mode */\r\n    hjpeg->Instance->CONFR1 |= JPEG_CONFR1_DE;\r\n  }  \r\n  else if((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_ENCODE)\r\n  {\r\n    /*Set JPEG Codec to Encoding mode */\r\n    hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_DE;\r\n  }\r\n  \r\n  /*Stop JPEG processing */\r\n  hjpeg->Instance->CONFR0 &=  ~JPEG_CONFR0_START;\r\n    \r\n  /* Disable All Interrupts */\r\n  __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);\r\n  \r\n  /* Disable All DMA requests */\r\n  JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_MASK);\r\n    \r\n  /* Flush input and output FIFOs*/\r\n  hjpeg->Instance->CR |= JPEG_CR_IFF;\r\n  hjpeg->Instance->CR |= JPEG_CR_OFF;\r\n    \r\n  /* Clear all flags */\r\n  __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_ALL);\r\n    \r\n  /*Start Encoding/Decoding*/\r\n  hjpeg->Instance->CONFR0 |=  JPEG_CONFR0_START;\r\n    \r\n  if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)\r\n  {  \r\n    /*Enable IN/OUT, end of Conversation, and end of header parsing interruptions*/\r\n    __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_IFT | JPEG_IT_IFNF | JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC |JPEG_IT_HPD);\r\n  }\r\n  else if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)\r\n  {\r\n    /*Enable End Of Conversation, and End Of Header parsing interruptions*/\r\n    __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_EOC |JPEG_IT_HPD);\r\n  \r\n  }    \r\n}\r\n\r\n/**\r\n  * @brief  JPEG encoding/decoding process in case of Polling or Interrupt\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @retval JPEG_PROCESS_DONE if the process has ends else JPEG_PROCESS_ONGOING\r\n  */\r\nstatic uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg)\r\n{\r\n  uint32_t tmpContext;\r\n  \r\n  /*End of header processing flag rised*/\r\n  if(((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) && (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_HPDF) != RESET))\r\n  {\r\n    /*Call Header parsing complet callback */\r\n    HAL_JPEG_GetInfo(hjpeg, &hjpeg->Conf);\r\n    /* Reset the ImageQuality */\r\n    hjpeg->Conf.ImageQuality = 0;\r\n    /* Note : the image quality is only available at the end of the decoding operation */\r\n    /* at the current stage the calculated image quality is not correct so reset it */    \r\n    \r\n    /*Call Info Ready callback */ \r\n    HAL_JPEG_InfoReadyCallback(hjpeg, &hjpeg->Conf);    \r\n    \r\n    __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_IT_HPD);\r\n    \r\n    /* Clear header processing done flag */\r\n    __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_HPDF);    \r\n  }\r\n\r\n  /*Input FIFO status handling*/\r\n  if((hjpeg->Context &  JPEG_CONTEXT_PAUSE_INPUT) == 0)\r\n  {  \r\n    if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_IFTF) != RESET)\r\n    {\r\n      /*Input FIFO threshold flag rised*/\r\n      /*4 words (16 bytes) can be written in */\r\n      JPEG_ReadInputData(hjpeg,4);\r\n    }\r\n    else if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_IFNFF) != RESET)\r\n    {\r\n      /*Input FIFO Not Full flag rised*/\r\n      /*32-bit value can be written in */\r\n      JPEG_ReadInputData(hjpeg,1);\r\n    }\r\n  }\r\n  \r\n \r\n  /*Output FIFO flag handling*/\r\n  if((hjpeg->Context &  JPEG_CONTEXT_PAUSE_OUTPUT) == 0)\r\n  {  \r\n    if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFTF) != RESET)\r\n    {\r\n      /*Output FIFO threshold flag rised*/\r\n      /*4 words (16 bytes) can be read out */\r\n      JPEG_StoreOutputData(hjpeg, 4);    \r\n    }\r\n    else if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) != RESET)\r\n    {\r\n      /*Output FIFO Not Empty flag rised*/\r\n      /*32-bit value can be read out */\r\n      JPEG_StoreOutputData(hjpeg, 1);  \r\n    }\r\n  }\r\n    \r\n  /*End of Conversion handling :i.e EOC flag is high and OFTF low and OFNEF low*/\r\n  if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF | JPEG_FLAG_OFTF | JPEG_FLAG_OFNEF) == JPEG_FLAG_EOCF)\r\n  {    \r\n    /*Stop Encoding/Decoding*/\r\n    hjpeg->Instance->CONFR0 &=  ~JPEG_CONFR0_START;\r\n\r\n    if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT)\r\n    {\r\n      /* Disable All Interrupts */\r\n      __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);\r\n    }\r\n  \r\n    /* Clear all flags */\r\n    __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_ALL);\r\n  \r\n    /*Call End of conversion callback */\r\n    if(hjpeg->JpegOutCount > 0)\r\n    {\r\n      /*Output Buffer is not empty, call DecodedDataReadyCallback*/\r\n      HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);\r\n      hjpeg->JpegOutCount = 0;\r\n    }\r\n    \r\n    /*Reset Context Operation*/\r\n    tmpContext = hjpeg->Context;\r\n    /*Clear all context fields execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/\r\n    hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hjpeg);\r\n    \r\n    /* Change the JPEG state */\r\n    hjpeg->State = HAL_JPEG_STATE_READY;\r\n    \r\n    /*Call End of Encoding/Decoding callback */\r\n    if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)\r\n    {\r\n      HAL_JPEG_DecodeCpltCallback(hjpeg);\r\n    }\r\n    else if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_ENCODE)\r\n    {\r\n      HAL_JPEG_EncodeCpltCallback(hjpeg);        \r\n    }\r\n  \r\n    return JPEG_PROCESS_DONE;    \r\n  }  \r\n\r\n  \r\n  return JPEG_PROCESS_ONGOING;\r\n}\r\n\r\n/**\r\n  * @brief  Store some output data from the JPEG peripheral to the output buffer.\r\n  *         This function is used when the JPEG peripheral has new data to output \r\n  *         in case of Polling or Interrupt process\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @param  nbOutputWords: Number of output words (of 32 bits) ready from the JPEG peripheral\r\n  * @retval None \r\n  */\r\nstatic void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWords)\r\n{\r\n  uint32_t index, nBwords, nbBytes , dataword, *pOutData;\r\n\r\n  pOutData = (uint32_t *)(((uint32_t *)hjpeg->pJpegOutBuffPtr) + (hjpeg->JpegOutCount/4));\r\n      \r\n  if(hjpeg->OutDataLength >= (hjpeg->JpegOutCount + (nbOutputWords*4)))\r\n  {\r\n    for(index = 0; index < nbOutputWords; index++)    \r\n    {\r\n      /*Transfer 32 bits from the JPEG output FIFO*/\r\n      *pOutData = hjpeg->Instance->DOR;\r\n      pOutData++;\r\n      hjpeg->JpegOutCount += 4;\r\n    }\r\n    if(hjpeg->OutDataLength == hjpeg->JpegOutCount)\r\n    {\r\n      /*Output Buffer is full, call DecodedDataReadyCallback*/\r\n      HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);\r\n      hjpeg->JpegOutCount = 0;            \r\n    }\r\n  }  \r\n  else if(hjpeg->OutDataLength > hjpeg->JpegOutCount)\r\n  {\r\n    nBwords = (hjpeg->OutDataLength - hjpeg->JpegOutCount)/4;\r\n    for(index = 0; index < nBwords; index++)    \r\n    {\r\n      /*Transfer 32 bits from the JPEG output FIFO*/\r\n      *pOutData = hjpeg->Instance->DOR;\r\n      pOutData++;\r\n      hjpeg->JpegOutCount += 4;\r\n    }\r\n    if(hjpeg->OutDataLength == hjpeg->JpegOutCount)\r\n    {\r\n      /*Output Buffer is full, call DecodedDataReadyCallback*/\r\n      HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);\r\n      hjpeg->JpegOutCount = 0;            \r\n    }\r\n    else\r\n    {      \r\n      nbBytes = hjpeg->OutDataLength - hjpeg->JpegOutCount;  \r\n      dataword = hjpeg->Instance->DOR;\r\n      for(index = 0; index < nbBytes; index++)\r\n      {\r\n        hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (dataword >> (8*index)) & 0xFF;\r\n        hjpeg->JpegOutCount++;\r\n      }        \r\n      /*Output Buffer is full, call DecodedDataReadyCallback*/\r\n      HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);\r\n      hjpeg->JpegOutCount = 0;\r\n      \r\n      nbBytes = 4 - nbBytes;\r\n      for(index = nbBytes; index < 4; index++)\r\n      {\r\n        hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (dataword >> (8*index)) & 0xFF;\r\n        hjpeg->JpegOutCount++;\r\n      }\r\n    }    \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Read some input Data from the input buffer.\r\n  *         This function is used when the JPEG peripheral needs new data \r\n  *         in case of Polling or Interrupt process\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @param  nbRequestWords: Number of input words (of 32 bits) that the JPE peripheral request\r\n  * @retval None \r\n  */\r\nstatic void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWords)\r\n{\r\n  uint32_t nbBytes = 0, nBwords, index, Dataword;  \r\n  \r\n  if((hjpeg->InDataLength == 0) || (nbRequestWords == 0))\r\n  {\r\n    /* No more Input data : nothing to do*/\r\n    HAL_JPEG_Pause(hjpeg, JPEG_PAUSE_RESUME_INPUT);\r\n  }\r\n  else if(hjpeg->InDataLength > hjpeg->JpegInCount)\r\n  {\r\n    nbBytes = hjpeg->InDataLength - hjpeg->JpegInCount;\r\n  }\r\n  else if(hjpeg->InDataLength == hjpeg->JpegInCount)\r\n  {\r\n    /*Call HAL_JPEG_GetDataCallback to get new data */\r\n    HAL_JPEG_GetDataCallback(hjpeg, hjpeg->JpegInCount);\r\n    if(hjpeg->InDataLength > 4)\r\n    {      \r\n      hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4);\r\n    }\r\n    hjpeg->JpegInCount = 0;\r\n    nbBytes = hjpeg->InDataLength;      \r\n  }\r\n  if((nbBytes > 0) && ((hjpeg->Context &  JPEG_CONTEXT_PAUSE_INPUT) == 0))\r\n  {  \r\n    nBwords = nbBytes / 4;\r\n    if(nBwords >= nbRequestWords)\r\n    {\r\n      for(index = 0; index < nbRequestWords; index++)\r\n      {      \r\n        hjpeg->Instance->DIR = *((uint32_t *)(((uint32_t *)hjpeg->pJpegInBuffPtr) + (hjpeg->JpegInCount/4)));\r\n      \r\n        hjpeg->JpegInCount += 4;\r\n      }\r\n    }\r\n    else /*nBwords < nbRequestWords*/\r\n    {\r\n      if(nBwords > 0)\r\n      {\r\n        for(index = 0; index < nBwords; index++)\r\n        {      \r\n          hjpeg->Instance->DIR = *((uint32_t *)(((uint32_t *)hjpeg->pJpegInBuffPtr) + (hjpeg->JpegInCount/4)));\r\n      \r\n          hjpeg->JpegInCount += 4;\r\n        }        \r\n      }      \r\n      else\r\n      {\r\n        /* end of file*/\r\n        Dataword = 0;\r\n        for(index=0; index< nbBytes; index++)\r\n        {\r\n          Dataword |= (uint32_t)hjpeg->pJpegInBuffPtr[hjpeg->JpegInCount] << (8 * index);\r\n          hjpeg->JpegInCount++;\r\n        }\r\n        hjpeg->Instance->DIR = Dataword;        \r\n      }       \r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Start the JPEG DMA process (encoding/decoding) \r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @retval JPEG_PROCESS_DONE if process ends else JPEG_PROCESS_ONGOING \r\n  */\r\nstatic HAL_StatusTypeDef JPEG_DMA_StartProcess(JPEG_HandleTypeDef *hjpeg)\r\n{  \r\n  if((hjpeg->InDataLength < 4) || (hjpeg->OutDataLength < 4))\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  /* Reset Ending DMA internal context flag*/\r\n  hjpeg->Context &= ~JPEG_CONTEXT_ENDING_DMA;\r\n  \r\n  /* Disable DMA In/Out Request*/\r\n  JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_ODMA | JPEG_DMA_IDMA);\r\n  \r\n  /* Set the JPEG DMA In transfer complete callback */\r\n  hjpeg->hdmain->XferCpltCallback = JPEG_DMAInCpltCallback; \r\n  /* Set the DMA In error callback */  \r\n  hjpeg->hdmain->XferErrorCallback = JPEG_DMAErrorCallback;\r\n  \r\n  /* Set the JPEG DMA Out transfer complete callback */\r\n  hjpeg->hdmaout->XferCpltCallback = JPEG_DMAOutCpltCallback;\r\n  /* Set the DMA Out error callback */\r\n  hjpeg->hdmaout->XferErrorCallback = JPEG_DMAErrorCallback;  \r\n  /* Set the DMA Out Abort callback */   \r\n  hjpeg->hdmaout->XferAbortCallback = JPEG_DMAOutAbortCallback;\r\n  \r\n  /*DMA transfer size must be a multiple of 4 bytes i.e mutliple of 32bits words*/\r\n  hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4);\r\n  \r\n  /*DMA transfer size must be a multiple of 4 bytes i.e mutliple of 32bits words*/\r\n  hjpeg->OutDataLength = hjpeg->OutDataLength - (hjpeg->OutDataLength % 4);\r\n    \r\n  /* Start DMA FIFO In transfer */\r\n  HAL_DMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR, hjpeg->InDataLength >> 2);  \r\n\r\n  /* Start DMA FIFO Out transfer */\r\n  HAL_DMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr, hjpeg->OutDataLength >> 2);\r\n\r\n  /* Enable JPEG In/Out DMA requests*/\r\n  JPEG_ENABLE_DMA(hjpeg,JPEG_DMA_IDMA | JPEG_DMA_ODMA); \r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Continue the current JPEG DMA process (encoding/decoding) \r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @retval JPEG_PROCESS_DONE if process ends else JPEG_PROCESS_ONGOING \r\n  */\r\nstatic uint32_t JPEG_DMA_ContinueProcess(JPEG_HandleTypeDef *hjpeg)\r\n{\r\n  /*End of header processing flag rises*/\r\n  if(((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) && (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_HPDF) != RESET))\r\n  {\r\n    /*Call Header parsing complete callback */\r\n    HAL_JPEG_GetInfo(hjpeg, &hjpeg->Conf);\r\n    \r\n    /* Reset the ImageQuality */\r\n    hjpeg->Conf.ImageQuality = 0;\r\n    /* Note : the image quality is only available at the end of the decoding operation */\r\n    /* at the current stage the calculated image quality is not correct so reset it */    \r\n    \r\n    /*Call Info Ready callback */  \r\n    HAL_JPEG_InfoReadyCallback(hjpeg, &hjpeg->Conf);    \r\n    \r\n    __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_IT_HPD);\r\n    \r\n    /* Clear header processing done flag */\r\n    __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_HPDF);    \r\n  }\r\n  \r\n  /*End of Conversion handling*/\r\n  if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF) != RESET)\r\n  {   \r\n    /*Disabkle JPEG In/Out DMA Requests*/\r\n    JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_ODMA | JPEG_DMA_IDMA); \r\n    \r\n    hjpeg->Context |= JPEG_CONTEXT_ENDING_DMA;\r\n    \r\n    /*Stop Encoding/Decoding*/\r\n    hjpeg->Instance->CONFR0 &=  ~JPEG_CONFR0_START;\r\n    \r\n    __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);\r\n    \r\n    /* Clear all flags */\r\n    __HAL_JPEG_CLEAR_FLAG(hjpeg,JPEG_FLAG_ALL);\r\n    \r\n    if(hjpeg->hdmain->State == HAL_DMA_STATE_BUSY)\r\n    {\r\n      /* Stop the DMA In Xfer*/\r\n      HAL_DMA_Abort_IT(hjpeg->hdmain);\r\n    }\r\n    \r\n    if(hjpeg->hdmaout->State == HAL_DMA_STATE_BUSY)\r\n    {\r\n      /* Stop the DMA out Xfer*/\r\n      HAL_DMA_Abort_IT(hjpeg->hdmaout);\r\n    }\r\n    else\r\n    {\r\n      return JPEG_DMA_EndProcess(hjpeg);\r\n    }    \r\n  }\r\n  \r\n  return JPEG_PROCESS_ONGOING;\r\n}\r\n\r\n/**\r\n  * @brief  Finalize the current JPEG DMA process (encoding/decoding) \r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module\r\n  * @retval JPEG_PROCESS_DONE\r\n  */\r\nstatic uint32_t JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg)\r\n{\r\n  uint32_t tmpContext, count = JPEG_FIFO_SIZE, *pDataOut;\r\n  \r\n  hjpeg->JpegOutCount = hjpeg->OutDataLength - ((hjpeg->hdmaout->Instance->NDTR & DMA_SxNDT) << 2);\r\n  \r\n  /*if Output Buffer is full, call HAL_JPEG_DataReadyCallback*/\r\n  if(hjpeg->JpegOutCount == hjpeg->OutDataLength)\r\n  {\r\n    HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);\r\n    hjpeg->JpegOutCount = 0;\r\n  }\r\n  \r\n  pDataOut = (uint32_t *)(hjpeg->pJpegOutBuffPtr + hjpeg->JpegOutCount);\r\n  \r\n  while((__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) != 0) && (count > 0))\r\n  {\r\n    count--;\r\n    \r\n    *pDataOut = hjpeg->Instance->DOR;\r\n    pDataOut++;\r\n    hjpeg->JpegOutCount += 4;\r\n    \r\n    if(hjpeg->JpegOutCount == hjpeg->OutDataLength)\r\n    {\r\n      /*Output Buffer is full, call HAL_JPEG_DataReadyCallback*/\r\n      HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);\r\n      hjpeg->JpegOutCount = 0;      \r\n    }\r\n  }\r\n  \r\n  /*Stop Encoding/Decoding*/\r\n  hjpeg->Instance->CONFR0 &=  ~JPEG_CONFR0_START;\r\n  \r\n  if(hjpeg->JpegOutCount > 0)\r\n  {\r\n    /*Output Buffer is not empty, call DecodedDataReadyCallback*/\r\n    HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);\r\n    hjpeg->JpegOutCount = 0;\r\n  }\r\n  \r\n  tmpContext = hjpeg->Context;\r\n  /*Clear all context fileds execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/\r\n  hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES);\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hjpeg);\r\n  \r\n  /* Change the JPEG state */\r\n  hjpeg->State = HAL_JPEG_STATE_READY;\r\n  \r\n  /*Call End of Encoding/Decoding callback */\r\n  if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)\r\n  {\r\n    HAL_JPEG_DecodeCpltCallback(hjpeg);\r\n  }\r\n  else if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_ENCODE)\r\n  {\r\n    HAL_JPEG_EncodeCpltCallback(hjpeg);        \r\n  }\r\n  \r\n  \r\n  return JPEG_PROCESS_DONE; \r\n}\r\n\r\n/**\r\n  * @brief  DMA input transfer complete callback\r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure. \r\n  * @retval None\r\n  */\r\nstatic void JPEG_DMAInCpltCallback(DMA_HandleTypeDef *hdma)  \r\n{  \r\n  JPEG_HandleTypeDef* hjpeg = (JPEG_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n  \r\n  /* Disable The JPEG IT so the DMA Input Callback can not be interrupted by the JPEG EOC IT or JPEG HPD IT */\r\n  __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);\r\n  \r\n  if(((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) && ((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) == 0))\r\n  {  \r\n    JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_IDMA); \r\n    \r\n    hjpeg->JpegInCount = hjpeg->InDataLength - ((hdma->Instance->NDTR & DMA_SxNDT) << 2);\r\n\r\n    /*Call HAL_JPEG_GetDataCallback to get new data */\r\n    HAL_JPEG_GetDataCallback(hjpeg, hjpeg->JpegInCount);\r\n    \r\n    if(hjpeg->InDataLength >= 4)\r\n    {\r\n      /*JPEG Input DMA transfer data number must be multiple of 32 bits word \r\n        as the destination is a 32 bits (4 bytes) register */\r\n      hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4);   \r\n    }\r\n    else if(hjpeg->InDataLength > 0)\r\n    {\r\n      /*Transfer last data word (i.e last 4 bytes)*/\r\n      hjpeg->InDataLength = 4;\r\n    }\r\n    \r\n    if(((hjpeg->Context &  JPEG_CONTEXT_PAUSE_INPUT) == 0) && (hjpeg->InDataLength > 0))\r\n    {  \r\n      /* Start DMA FIFO In transfer */\r\n      HAL_DMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR, hjpeg->InDataLength >> 2);\r\n      JPEG_ENABLE_DMA(hjpeg,JPEG_DMA_IDMA);\r\n    }       \r\n    \r\n    /* JPEG Conversion still on going : Enable the JPEG IT */\r\n    __HAL_JPEG_ENABLE_IT(hjpeg,JPEG_IT_EOC |JPEG_IT_HPD); \r\n  }  \r\n}\r\n\r\n/**\r\n  * @brief  DMA output transfer complete callback\r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure. \r\n  * @retval None\r\n  */\r\nstatic void JPEG_DMAOutCpltCallback(DMA_HandleTypeDef *hdma)  \r\n{ \r\n  JPEG_HandleTypeDef* hjpeg = (JPEG_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;  \r\n  \r\n  /* Disable The JPEG IT so the DMA Output Callback can not be interrupted by the JPEG EOC IT or JPEG HPD IT */\r\n  __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);\r\n    \r\n  if(((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) && ((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) == 0))\r\n  {    \r\n    if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF) == 0)\r\n    {    \r\n      JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_ODMA); \r\n      hjpeg->JpegOutCount = hjpeg->OutDataLength - ((hdma->Instance->NDTR & DMA_SxNDT) << 2);\r\n    \r\n      /*Output Buffer is full, call HAL_JPEG_DataReadyCallback*/\r\n      HAL_JPEG_DataReadyCallback (hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount);\r\n      \r\n      if((hjpeg->Context &  JPEG_CONTEXT_PAUSE_OUTPUT) == 0)\r\n      {   \r\n        /* Start DMA FIFO Out transfer */\r\n        HAL_DMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr, hjpeg->OutDataLength >> 2);\r\n        JPEG_ENABLE_DMA(hjpeg,JPEG_DMA_ODMA);\r\n      }\r\n    }\r\n    \r\n    /* JPEG Conversion still on going : Enable the JPEG IT */\r\n    __HAL_JPEG_ENABLE_IT(hjpeg,JPEG_IT_EOC |JPEG_IT_HPD);  \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  DMA Transfer error callback\r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure. \r\n  * @retval None\r\n  */\r\nstatic void JPEG_DMAErrorCallback(DMA_HandleTypeDef *hdma)\r\n{\r\n  JPEG_HandleTypeDef* hjpeg = (JPEG_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n  \r\n  /* if DMA error is FIFO error ignore it */\r\n  if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)\r\n  {\r\n    /*Stop Encoding/Decoding*/\r\n    hjpeg->Instance->CONFR0 &=  ~JPEG_CONFR0_START;\r\n    \r\n    /* Disable All Interrupts */\r\n    __HAL_JPEG_DISABLE_IT(hjpeg,JPEG_INTERRUPT_MASK);\r\n    \r\n    /* Disable All DMA requests */\r\n    JPEG_DISABLE_DMA(hjpeg,JPEG_DMA_MASK);  \r\n    \r\n    hjpeg->State= HAL_JPEG_STATE_READY;\r\n    hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; \r\n    HAL_JPEG_ErrorCallback(hjpeg);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  DMA output Abort callback\r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure. \r\n  * @retval None\r\n  */\r\nstatic void JPEG_DMAOutAbortCallback(DMA_HandleTypeDef *hdma)  \r\n{\r\n  JPEG_HandleTypeDef* hjpeg = (JPEG_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n  \r\n  if((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) != 0)\r\n  {\r\n    JPEG_DMA_EndProcess(hjpeg);\r\n  }  \r\n}\r\n\r\n/**\r\n  * @brief  Calculate the decoded image quality (from 1 to 100)\r\n  * @param  hjpeg: pointer to a JPEG_HandleTypeDef structure that contains\r\n  *         the configuration information for JPEG module \r\n  * @retval JPEG image quality from 1 to 100.\r\n  */\r\nstatic uint32_t JPEG_GetQuality(JPEG_HandleTypeDef *hjpeg)\r\n{\r\n  uint32_t quality = 0;\r\n  uint32_t quantRow, quantVal,scale, i, j; \r\n  uint32_t *tableAddress = (uint32_t *)hjpeg->Instance->QMEM0;\r\n  \r\n  i = 0;\r\n  while( i < JPEG_QUANT_TABLE_SIZE)\r\n  {\r\n    quantRow = *tableAddress;\r\n    for(j=0; j<4; j++)\r\n    {\r\n      quantVal = (quantRow >> (8 * j)) & 0xFF;\r\n      if(quantVal == 1)\r\n      {\r\n        /* if Quantization value = 1 then quality is 100%*/\r\n        quality += 100;\r\n      }\r\n      else\r\n      {\r\n        /* Note that the quantization coefficients must be specified in the table in zigzag order */\r\n        scale = (quantVal*100)/((uint32_t) JPEG_LUM_QuantTable[JPEG_ZIGZAG_ORDER[i+j]]);\r\n      \r\n        if(scale <= 100)\r\n        {\r\n          quality += (200 - scale)/2;         \r\n        }\r\n        else\r\n        {\r\n          quality += 5000/scale;        \r\n        }\r\n      }      \r\n    }\r\n\r\n    i += 4;\r\n    tableAddress ++;        \r\n  }\r\n\r\n  return (quality/((uint32_t)64));   \r\n}\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* STM32F767xx ||  STM32F769xx ||  STM32F777xx ||  STM32F779xx */\r\n#endif /* HAL_JPEG_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_lptim.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_lptim.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   LPTIM HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the Low Power Timer (LPTIM) peripheral:\r\n  *           + Initialization and de-initialization functions.\r\n  *           + Start/Stop operation functions in polling mode.\r\n  *           + Start/Stop operation functions in interrupt mode.\r\n  *           + Reading operation functions.\r\n  *           + Peripheral State functions.\r\n  *         \r\n  @verbatim\r\n  ==============================================================================\r\n                     ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]\r\n      The LPTIM HAL driver can be used as follows:\r\n\r\n      (#)Initialize the LPTIM low level resources by implementing the\r\n        HAL_LPTIM_MspInit():\r\n         (##) Enable the LPTIM interface clock using __LPTIMx_CLK_ENABLE().\r\n         (##) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):\r\n             (+) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().\r\n             (+) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().\r\n             (+) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().\r\n    \r\n      (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function\r\n         configures mainly:\r\n         (##) The instance: LPTIM1.\r\n         (##) Clock: the counter clock.\r\n                 - Source   : it can be either the ULPTIM input (IN1) or one of\r\n                              the internal clock; (APB, LSE, LSI or MSI).\r\n                 - Prescaler: select the clock divider.\r\n         (##)  UltraLowPowerClock : To be used only if the ULPTIM is selected\r\n               as counter clock source.\r\n                 - Polarity:   polarity of the active edge for the counter unit\r\n                               if the ULPTIM input is selected.\r\n                 - SampleTime: clock sampling time to configure the clock glitch\r\n                               filter.              \r\n         (##) Trigger: How the counter start.\r\n                 - Source: trigger can be software or one of the hardware triggers.\r\n                 - ActiveEdge : only for hardware trigger.\r\n                 - SampleTime : trigger sampling time to configure the trigger\r\n                                glitch filter.\r\n         (##) OutputPolarity : 2 opposite polarities are possibles.\r\n         (##) UpdateMode: specifies whether the update of the autoreload and\r\n              the compare values is done immediately or after the end of current\r\n              period.   \r\n    \r\n      (#)Six modes are available:\r\n      \r\n         (##) PWM Mode: To generate a PWM signal with specified period and pulse,\r\n         call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption\r\n         mode.\r\n         \r\n         (##) One Pulse Mode: To generate pulse with specified width in response\r\n         to a stimulus, call HAL_LPTIM_OnePulse_Start() or\r\n         HAL_LPTIM_OnePulse_Start_IT() for interruption mode.\r\n         \r\n         (##) Set once Mode: In this mode, the output changes the level (from\r\n         low level to high level if the output polarity is configured high, else\r\n         the opposite) when a compare match occurs. To start this mode, call \r\n         HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for\r\n         interruption mode.\r\n         \r\n         (##) Encoder Mode: To use the encoder interface call\r\n         HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for \r\n         interruption mode.\r\n         \r\n         (##) Time out Mode: an active edge on one selected trigger input rests\r\n         the counter. The first trigger event will start the timer, any\r\n         successive trigger event will reset the counter and the timer will\r\n         restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or \r\n         HAL_LPTIM_TimeOut_Start_IT() for interruption mode.\r\n         \r\n         (##) Counter Mode: counter can be used to count external events on\r\n         the LPTIM Input1 or it can be used to count internal clock cycles.\r\n         To start this mode, call HAL_LPTIM_Counter_Start() or \r\n         HAL_LPTIM_Counter_Start_IT() for interruption mode.             \r\n\r\n    \r\n      (#) User can stop any process by calling the corresponding API:\r\n          HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is\r\n          already started in interruption mode.\r\n         \r\n       (#)Call HAL_LPTIM_DeInit() to deinitialize the LPTIM peripheral.\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************  \r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup LPTIM LPTIM\r\n  * @brief LPTIM HAL module driver.\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_LPTIM_MODULE_ENABLED\r\n/* Private types -------------------------------------------------------------*/\r\n/** @defgroup LPTIM_Private_Types LPTIM Private Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Private defines -----------------------------------------------------------*/\r\n/** @defgroup LPTIM_Private_Defines LPTIM Private Defines\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @addtogroup LPTIM_Private_Variables LPTIM Private Variables\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n \r\n/* Private constants ---------------------------------------------------------*/\r\n/** @addtogroup LPTIM_Private_Constants LPTIM Private Constants\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Private macros ------------------------------------------------------------*/\r\n/** @addtogroup LPTIM_Private_Macros LPTIM Private Macros\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private function prototypes -----------------------------------------------*/\r\n/** @addtogroup LPTIM_Private_Functions_Prototypes LPTIM Private Functions Prototypes\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @addtogroup LPTIM_Private_Functions LPTIM Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Exported functions ---------------------------------------------------------*/\r\n/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup LPTIM_Group1 Initialization/de-initialization functions \r\n *  @brief    Initialization and Configuration functions. \r\n *\r\n@verbatim    \r\n  ==============================================================================\r\n              ##### Initialization and de-initialization functions #####\r\n  ==============================================================================\r\n    [..]  This section provides functions allowing to:\r\n      (+) Initialize the LPTIM according to the specified parameters in the\r\n          LPTIM_InitTypeDef and creates the associated handle.\r\n      (+) DeInitialize the LPTIM peripheral.\r\n      (+) Initialize the LPTIM MSP.\r\n      (+) DeInitialize LPTIM MSP. \r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the LPTIM according to the specified parameters in the\r\n  *         LPTIM_InitTypeDef and creates the associated handle.\r\n  * @param  hlptim: LPTIM handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  uint32_t tmpcfgr = 0;\r\n\r\n  /* Check the LPTIM handle allocation */\r\n  if(hlptim == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  \r\n  assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));\r\n  assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));  \r\n  if ((hlptim->Init.Clock.Source) ==  LPTIM_CLOCKSOURCE_ULPTIM)\r\n  {\r\n    assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));\r\n    assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));\r\n  }  \r\n  assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));\r\n  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)\r\n  {\r\n    assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));\r\n    assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));\r\n  }  \r\n  assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));  \r\n  assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));\r\n  assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource));\r\n  \r\n  if(hlptim->State == HAL_LPTIM_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    hlptim->Lock = HAL_UNLOCKED;\r\n    /* Init the low level hardware */\r\n    HAL_LPTIM_MspInit(hlptim);\r\n  }\r\n  \r\n  /* Change the LPTIM state */\r\n  hlptim->State = HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Get the LPTIMx CFGR value */\r\n  tmpcfgr = hlptim->Instance->CFGR;\r\n  \r\n  if ((hlptim->Init.Clock.Source) ==  LPTIM_CLOCKSOURCE_ULPTIM)\r\n  {\r\n    tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));\r\n  }\r\n  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)\r\n  {\r\n    tmpcfgr &= (uint32_t)(~ (LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));\r\n  }\r\n    \r\n  /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */\r\n  tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |\r\n                          LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE ));\r\n  \r\n  /* Set initialization parameters */\r\n  tmpcfgr |= (hlptim->Init.Clock.Source    |\r\n              hlptim->Init.Clock.Prescaler |\r\n              hlptim->Init.OutputPolarity  |\r\n              hlptim->Init.UpdateMode      |\r\n              hlptim->Init.CounterSource);\r\n  \r\n  if ((hlptim->Init.Clock.Source) ==  LPTIM_CLOCKSOURCE_ULPTIM)\r\n  {\r\n    tmpcfgr |=  (hlptim->Init.UltraLowPowerClock.Polarity |\r\n                hlptim->Init.UltraLowPowerClock.SampleTime);\r\n  } \r\n  \r\n  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)\r\n  {\r\n    /* Enable External trigger and set the trigger source */\r\n    tmpcfgr |= (hlptim->Init.Trigger.Source     |\r\n                hlptim->Init.Trigger.ActiveEdge |\r\n                hlptim->Init.Trigger.SampleTime);\r\n  }\r\n  \r\n  /* Write to LPTIMx CFGR */\r\n  hlptim->Instance->CFGR = tmpcfgr;\r\n\r\n  /* Change the LPTIM state */\r\n  hlptim->State = HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the LPTIM peripheral. \r\n  * @param  hlptim: LPTIM handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Check the LPTIM handle allocation */\r\n  if(hlptim == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Change the LPTIM state */\r\n  hlptim->State = HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Disable the LPTIM Peripheral Clock */\r\n  __HAL_LPTIM_DISABLE(hlptim);\r\n  \r\n  /* DeInit the low level hardware: CLOCK, NVIC.*/\r\n  HAL_LPTIM_MspDeInit(hlptim);\r\n  \r\n  /* Change the LPTIM state */\r\n  hlptim->State = HAL_LPTIM_STATE_RESET;\r\n  \r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hlptim);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the LPTIM MSP.\r\n  * @param  hlptim: LPTIM handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hlptim);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_LPTIM_MspInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes LPTIM MSP.\r\n  * @param  hlptim: LPTIM handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hlptim);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_LPTIM_MspDeInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LPTIM_Group2 LPTIM Start-Stop operation functions \r\n *  @brief   Start-Stop operation functions. \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                ##### LPTIM Start Stop operation functions #####\r\n  ==============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Start the PWM mode.\r\n      (+) Stop the PWM mode.\r\n      (+) Start the One pulse mode.\r\n      (+) Stop the One pulse mode.\r\n      (+) Start the Set once mode.\r\n      (+) Stop the Set once mode.\r\n      (+) Start the Encoder mode.\r\n      (+) Stop the Encoder mode.\r\n      (+) Start the Timeout mode.\r\n      (+) Stop the Timeout mode.      \r\n      (+) Start the Counter mode.\r\n      (+) Stop the Counter mode.\r\n      \r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n    \r\n/**\r\n  * @brief  Starts the LPTIM PWM generation.\r\n  * @param  hlptim : LPTIM handle\r\n  * @param  Period : Specifies the Autoreload value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @param  Pulse : Specifies the compare value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  assert_param(IS_LPTIM_PERIOD(Period));\r\n  assert_param(IS_LPTIM_PULSE(Pulse));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n \r\n  /* Reset WAVE bit to set PWM mode */\r\n  hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;\r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_LPTIM_ENABLE(hlptim);\r\n  \r\n  /* Load the period value in the autoreload register */\r\n  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r\n  \r\n  /* Load the pulse value in the compare register */\r\n  __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);\r\n  \r\n  /* Start timer in continuous mode */\r\n  __HAL_LPTIM_START_CONTINUOUS(hlptim);\r\n    \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the LPTIM PWM generation.\r\n  * @param  hlptim : LPTIM handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_LPTIM_DISABLE(hlptim);\r\n\r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the LPTIM PWM generation in interrupt mode.\r\n  * @param  hlptim : LPTIM handle\r\n  * @param  Period : Specifies the Autoreload value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF\r\n  * @param  Pulse : Specifies the compare value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  assert_param(IS_LPTIM_PERIOD(Period));\r\n  assert_param(IS_LPTIM_PULSE(Pulse));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n \r\n  /* Reset WAVE bit to set PWM mode */\r\n  hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;\r\n  \r\n  /* Enable Autoreload write complete interrupt */\r\n  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);\r\n  \r\n  /* Enable Compare write complete interrupt */\r\n  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);\r\n  \r\n  /* Enable Autoreload match interrupt */\r\n  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);\r\n  \r\n  /* Enable Compare match interrupt */\r\n  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);\r\n  \r\n  /* If external trigger source is used, then enable external trigger interrupt */\r\n  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)\r\n  {\r\n    /* Enable external trigger interrupt */\r\n    __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);\r\n  }  \r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_LPTIM_ENABLE(hlptim);\r\n  \r\n  /* Load the period value in the autoreload register */\r\n  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r\n  \r\n  /* Load the pulse value in the compare register */\r\n  __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);\r\n  \r\n  /* Start timer in continuous mode */\r\n  __HAL_LPTIM_START_CONTINUOUS(hlptim);\r\n    \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the LPTIM PWM generation in interrupt mode.\r\n  * @param  hlptim : LPTIM handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_LPTIM_DISABLE(hlptim);\r\n  \r\n    /* Disable Autoreload write complete interrupt */\r\n  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);\r\n  \r\n  /* Disable Compare write complete interrupt */\r\n  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);\r\n  \r\n  /* Disable Autoreload match interrupt */\r\n  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);\r\n  \r\n  /* Disable Compare match interrupt */\r\n  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);\r\n  \r\n  /* If external trigger source is used, then disable external trigger interrupt */\r\n  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)\r\n  {\r\n    /* Disable external trigger interrupt */\r\n    __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);\r\n  }  \r\n\r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the LPTIM One pulse generation.\r\n  * @param  hlptim : LPTIM handle\r\n  * @param  Period : Specifies the Autoreload value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @param  Pulse : Specifies the compare value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  assert_param(IS_LPTIM_PERIOD(Period));\r\n  assert_param(IS_LPTIM_PULSE(Pulse));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Reset WAVE bit to set one pulse mode */\r\n  hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;\r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_LPTIM_ENABLE(hlptim);\r\n  \r\n  /* Load the period value in the autoreload register */\r\n  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r\n  \r\n  /* Load the pulse value in the compare register */\r\n  __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);\r\n  \r\n  /* Start timer in continuous mode */\r\n  __HAL_LPTIM_START_SINGLE(hlptim);\r\n    \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the LPTIM One pulse generation.\r\n  * @param  hlptim : LPTIM handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_LPTIM_DISABLE(hlptim);\r\n\r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the LPTIM One pulse generation in interrupt mode.\r\n  * @param  hlptim : LPTIM handle\r\n  * @param  Period : Specifies the Autoreload value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @param  Pulse : Specifies the compare value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  assert_param(IS_LPTIM_PERIOD(Period));\r\n  assert_param(IS_LPTIM_PULSE(Pulse));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Reset WAVE bit to set one pulse mode */\r\n  hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;\r\n  \r\n  /* Enable Autoreload write complete interrupt */\r\n  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);\r\n  \r\n  /* Enable Compare write complete interrupt */\r\n  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);\r\n  \r\n  /* Enable Autoreload match interrupt */\r\n  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);\r\n  \r\n  /* Enable Compare match interrupt */\r\n  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);\r\n  \r\n  /* If external trigger source is used, then enable external trigger interrupt */\r\n  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)\r\n  {\r\n    /* Enable external trigger interrupt */\r\n    __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);\r\n  }\r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_LPTIM_ENABLE(hlptim);\r\n  \r\n  /* Load the period value in the autoreload register */\r\n  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r\n  \r\n  /* Load the pulse value in the compare register */\r\n  __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);\r\n  \r\n  /* Start timer in continuous mode */\r\n  __HAL_LPTIM_START_SINGLE(hlptim);\r\n    \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the LPTIM One pulse generation in interrupt mode.\r\n  * @param  hlptim : LPTIM handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_LPTIM_DISABLE(hlptim);\r\n  \r\n  /* Disable Autoreload write complete interrupt */\r\n  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);\r\n  \r\n  /* Disable Compare write complete interrupt */\r\n  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);\r\n  \r\n  /* Disable Autoreload match interrupt */\r\n  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);\r\n  \r\n  /* Disable Compare match interrupt */\r\n  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);\r\n  \r\n  /* If external trigger source is used, then disable external trigger interrupt */\r\n  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)\r\n  {\r\n    /* Disable external trigger interrupt */\r\n    __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);\r\n  }\r\n  \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the LPTIM in Set once mode.\r\n  * @param  hlptim : LPTIM handle\r\n  * @param  Period : Specifies the Autoreload value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @param  Pulse : Specifies the compare value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  assert_param(IS_LPTIM_PERIOD(Period));\r\n  assert_param(IS_LPTIM_PULSE(Pulse));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Set WAVE bit to enable the set once mode */\r\n  hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;\r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_LPTIM_ENABLE(hlptim);\r\n  \r\n  /* Load the period value in the autoreload register */\r\n  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r\n  \r\n  /* Load the pulse value in the compare register */\r\n  __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);\r\n  \r\n  /* Start timer in continuous mode */\r\n  __HAL_LPTIM_START_SINGLE(hlptim);\r\n    \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the LPTIM Set once mode.\r\n  * @param  hlptim : LPTIM handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_LPTIM_DISABLE(hlptim);\r\n\r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the LPTIM Set once mode in interrupt mode.\r\n  * @param  hlptim : LPTIM handle\r\n  * @param  Period : Specifies the Autoreload value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @param  Pulse : Specifies the compare value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  assert_param(IS_LPTIM_PERIOD(Period));\r\n  assert_param(IS_LPTIM_PULSE(Pulse));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Set WAVE bit to enable the set once mode */\r\n  hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;\r\n  \r\n  /* Enable Autoreload write complete interrupt */\r\n  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);\r\n  \r\n  /* Enable Compare write complete interrupt */\r\n  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);\r\n  \r\n  /* Enable Autoreload match interrupt */\r\n  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);\r\n  \r\n  /* Enable Compare match interrupt */\r\n  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);\r\n  \r\n  /* If external trigger source is used, then enable external trigger interrupt */\r\n  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)\r\n  {\r\n    /* Enable external trigger interrupt */\r\n    __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);\r\n  }  \r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_LPTIM_ENABLE(hlptim);\r\n  \r\n  /* Load the period value in the autoreload register */\r\n  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r\n  \r\n  /* Load the pulse value in the compare register */\r\n  __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);\r\n  \r\n  /* Start timer in continuous mode */\r\n  __HAL_LPTIM_START_SINGLE(hlptim);\r\n    \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the LPTIM Set once mode in interrupt mode.\r\n  * @param  hlptim : LPTIM handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_LPTIM_DISABLE(hlptim);\r\n\r\n  /* Disable Autoreload write complete interrupt */\r\n  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);\r\n  \r\n  /* Disable Compare write complete interrupt */\r\n  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);\r\n  \r\n  /* Disable Autoreload match interrupt */\r\n  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);\r\n  \r\n  /* Disable Compare match interrupt */\r\n  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);\r\n  \r\n  /* If external trigger source is used, then disable external trigger interrupt */\r\n  if ((hlptim->Init.Trigger.Source) !=  LPTIM_TRIGSOURCE_SOFTWARE)\r\n  {\r\n    /* Disable external trigger interrupt */\r\n    __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);\r\n  } \r\n  \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the Encoder interface.\r\n  * @param  hlptim : LPTIM handle\r\n  * @param  Period : Specifies the Autoreload value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)\r\n{\r\n  uint32_t tmpcfgr = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  assert_param(IS_LPTIM_PERIOD(Period));\r\n  assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);\r\n  assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);\r\n  assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));\r\n\r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n\r\n  /* Get the LPTIMx CFGR value */\r\n  tmpcfgr = hlptim->Instance->CFGR;\r\n\r\n  /* Clear CKPOL bits */\r\n  tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);\r\n\r\n  /* Set Input polarity */\r\n  tmpcfgr |=  hlptim->Init.UltraLowPowerClock.Polarity;\r\n\r\n  /* Write to LPTIMx CFGR */\r\n  hlptim->Instance->CFGR = tmpcfgr;\r\n\r\n  /* Set ENC bit to enable the encoder interface */\r\n  hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;\r\n\r\n  /* Enable the Peripheral */\r\n  __HAL_LPTIM_ENABLE(hlptim);\r\n\r\n  /* Load the period value in the autoreload register */\r\n  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r\n\r\n  /* Start timer in continuous mode */\r\n  __HAL_LPTIM_START_CONTINUOUS(hlptim);\r\n\r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the Encoder interface.\r\n  * @param  hlptim : LPTIM handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_LPTIM_DISABLE(hlptim);\r\n  \r\n  /* Reset ENC bit to disable the encoder interface */\r\n  hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;\r\n  \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the Encoder interface in interrupt mode.\r\n  * @param  hlptim : LPTIM handle\r\n  * @param  Period : Specifies the Autoreload value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)\r\n{\r\n  uint32_t tmpcfgr = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  assert_param(IS_LPTIM_PERIOD(Period));\r\n  assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);\r\n  assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);\r\n  assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));\r\n\r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Configure edge sensitivity for encoder mode */\r\n  /* Get the LPTIMx CFGR value */\r\n  tmpcfgr = hlptim->Instance->CFGR;\r\n\r\n  /* Clear CKPOL bits */\r\n  tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);\r\n\r\n  /* Set Input polarity */\r\n  tmpcfgr |=  hlptim->Init.UltraLowPowerClock.Polarity;\r\n\r\n  /* Write to LPTIMx CFGR */\r\n  hlptim->Instance->CFGR = tmpcfgr;\r\n\r\n  /* Set ENC bit to enable the encoder interface */\r\n  hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;\r\n\r\n  /* Enable \"switch to down direction\" interrupt */\r\n  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN);\r\n\r\n  /* Enable \"switch to up direction\" interrupt */\r\n  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP);  \r\n\r\n  /* Enable the Peripheral */\r\n  __HAL_LPTIM_ENABLE(hlptim);\r\n\r\n  /* Load the period value in the autoreload register */\r\n  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r\n\r\n  /* Start timer in continuous mode */\r\n  __HAL_LPTIM_START_CONTINUOUS(hlptim);\r\n\r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the Encoder interface in interrupt mode.\r\n  * @param  hlptim : LPTIM handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_LPTIM_DISABLE(hlptim);\r\n  \r\n  /* Reset ENC bit to disable the encoder interface */\r\n  hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;\r\n  \r\n  /* Disable \"switch to down direction\" interrupt */\r\n  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_DOWN);\r\n  \r\n  /* Disable \"switch to up direction\" interrupt */\r\n  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP); \r\n  \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the Timeout function. The first trigger event will start the\r\n  *         timer, any successive trigger event will reset the counter and\r\n  *         the timer restarts.\r\n  * @param  hlptim : LPTIM handle\r\n  * @param  Period : Specifies the Autoreload value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @param  Timeout : Specifies the TimeOut value to rest the counter.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  assert_param(IS_LPTIM_PERIOD(Period));\r\n  assert_param(IS_LPTIM_PULSE(Timeout));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n \r\n  /* Set TIMOUT bit to enable the timeout function */\r\n  hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;\r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_LPTIM_ENABLE(hlptim);\r\n  \r\n  /* Load the period value in the autoreload register */\r\n  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r\n  \r\n  /* Load the Timeout value in the compare register */\r\n  __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);\r\n  \r\n  /* Start timer in continuous mode */\r\n  __HAL_LPTIM_START_CONTINUOUS(hlptim);\r\n    \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the Timeout function.\r\n  * @param  hlptim : LPTIM handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_LPTIM_DISABLE(hlptim);\r\n  \r\n  /* Reset TIMOUT bit to enable the timeout function */\r\n  hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;\r\n  \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the Timeout function in interrupt mode. The first trigger \r\n  *         event will start the timer, any successive trigger event will reset\r\n  *         the counter and the timer restarts.\r\n  * @param  hlptim : LPTIM handle\r\n  * @param  Period : Specifies the Autoreload value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @param  Timeout : Specifies the TimeOut value to rest the counter.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  assert_param(IS_LPTIM_PERIOD(Period));\r\n  assert_param(IS_LPTIM_PULSE(Timeout));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n \r\n  /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */\r\n  __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(); \r\n  \r\n  /* Enable rising edge trigger on the LPTIM Wake-up Timer Exti line */\r\n  __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();\r\n \r\n  /* Set TIMOUT bit to enable the timeout function */\r\n  hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;\r\n  \r\n  /* Enable Compare match interrupt */\r\n  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);\r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_LPTIM_ENABLE(hlptim);\r\n  \r\n  /* Load the period value in the autoreload register */\r\n  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r\n  \r\n  /* Load the Timeout value in the compare register */\r\n  __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);\r\n  \r\n  /* Start timer in continuous mode */\r\n  __HAL_LPTIM_START_CONTINUOUS(hlptim);\r\n    \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the Timeout function in interrupt mode.\r\n  * @param  hlptim : LPTIM handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */ \r\n  __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\r\n  \r\n  /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */\r\n  __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(); \r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_LPTIM_DISABLE(hlptim);\r\n  \r\n  /* Reset TIMOUT bit to enable the timeout function */\r\n  hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;\r\n  \r\n  /* Disable Compare match interrupt */\r\n  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);\r\n  \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the Counter mode.\r\n  * @param  hlptim : LPTIM handle\r\n  * @param  Period : Specifies the Autoreload value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  assert_param(IS_LPTIM_PERIOD(Period));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */\r\n  if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))\r\n  {\r\n    /* Check if clock is prescaled */\r\n    assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));\r\n    /* Set clock prescaler to 0 */\r\n    hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;\r\n  }\r\n\r\n  /* Enable the Peripheral */\r\n  __HAL_LPTIM_ENABLE(hlptim);\r\n  \r\n  /* Load the period value in the autoreload register */\r\n  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r\n  \r\n  /* Start timer in continuous mode */\r\n  __HAL_LPTIM_START_CONTINUOUS(hlptim);\r\n    \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the Counter mode.\r\n  * @param  hlptim : LPTIM handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_LPTIM_DISABLE(hlptim);\r\n  \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the Counter mode in interrupt mode.\r\n  * @param  hlptim : LPTIM handle\r\n  * @param  Period : Specifies the Autoreload value.\r\n  *         This parameter must be a value between 0x0000 and 0xFFFF.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  assert_param(IS_LPTIM_PERIOD(Period));\r\n               \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n\r\n  /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */\r\n  __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(); \r\n  \r\n  /* Enable rising edge trigger on the LPTIM Wake-up Timer Exti line */\r\n  __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();  \r\n  \r\n  /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */\r\n  if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))\r\n  {\r\n    /* Check if clock is prescaled */\r\n    assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));\r\n    /* Set clock prescaler to 0 */\r\n    hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;\r\n  }\r\n  \r\n  /* Enable Autoreload write complete interrupt */\r\n  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);\r\n  \r\n  /* Enable Autoreload match interrupt */\r\n  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);\r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_LPTIM_ENABLE(hlptim);\r\n  \r\n  /* Load the period value in the autoreload register */\r\n  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);\r\n  \r\n  /* Start timer in continuous mode */\r\n  __HAL_LPTIM_START_CONTINUOUS(hlptim);\r\n    \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the Counter mode in interrupt mode.\r\n  * @param  hlptim : LPTIM handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  \r\n  /* Set the LPTIM state */\r\n  hlptim->State= HAL_LPTIM_STATE_BUSY;\r\n  \r\n  /* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */ \r\n  __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\r\n  \r\n  /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */\r\n  __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(); \r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_LPTIM_DISABLE(hlptim);\r\n  \r\n  /* Disable Autoreload write complete interrupt */\r\n  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);\r\n  \r\n  /* Disable Autoreload match interrupt */\r\n  __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);\r\n  \r\n  /* Change the TIM state*/\r\n  hlptim->State= HAL_LPTIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LPTIM_Group3 LPTIM Read operation functions \r\n *  @brief  Read operation functions.\r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                  ##### LPTIM Read operation functions #####\r\n  ==============================================================================  \r\n[..]  This section provides LPTIM Reading functions.\r\n      (+) Read the counter value.\r\n      (+) Read the period (Auto-reload) value.\r\n      (+) Read the pulse (Compare)value.\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  This function returns the current counter value.\r\n  * @param  hlptim: LPTIM handle\r\n  * @retval Counter value.\r\n  */\r\nuint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n    /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  \r\n  return (hlptim->Instance->CNT);\r\n}\r\n\r\n/**\r\n  * @brief  This function return the current Autoreload (Period) value.\r\n  * @param  hlptim: LPTIM handle\r\n  * @retval Autoreload value.\r\n  */\r\nuint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n    /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  \r\n  return (hlptim->Instance->ARR);\r\n}\r\n\r\n/**\r\n  * @brief  This function return the current Compare (Pulse) value.\r\n  * @param  hlptim: LPTIM handle\r\n  * @retval Compare value.\r\n  */\r\nuint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n    /* Check the parameters */\r\n  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));\r\n  \r\n  return (hlptim->Instance->CMP);\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n\r\n/** @defgroup LPTIM_Group4 LPTIM IRQ handler \r\n *  @brief  LPTIM  IRQ handler.\r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                      ##### LPTIM IRQ handler  #####\r\n  ==============================================================================  \r\n[..]  This section provides LPTIM IRQ handler function.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  This function handles LPTIM interrupt request.\r\n  * @param  hlptim: LPTIM handle\r\n  * @retval None\r\n  */\r\nvoid HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Compare match interrupt */\r\n  if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPM) != RESET)\r\n\t{\r\n    if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPM) !=RESET)\r\n\t\t{\r\n      /* Clear Compare match flag */\r\n      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPM);\r\n      /* Compare match Callback */\r\n      HAL_LPTIM_CompareMatchCallback(hlptim);      \r\n    }\r\n  }\r\n  \r\n  /* Autoreload match interrupt */\r\n  if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET)\r\n\t{\r\n    if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) !=RESET)\r\n\t\t{\r\n      /* Clear Autoreload match flag */\r\n      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM);\r\n      /* Autoreload match Callback */\r\n      HAL_LPTIM_AutoReloadMatchCallback(hlptim);      \r\n    }\r\n  }\r\n  \r\n  /* Trigger detected interrupt */\r\n  if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET)\r\n\t{\r\n    if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) !=RESET)\r\n\t\t{\r\n      /* Clear Trigger detected flag */\r\n      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG);\r\n      /* Trigger detected callback */\r\n      HAL_LPTIM_TriggerCallback(hlptim);      \r\n    }\r\n  }\r\n  \r\n  /* Compare write interrupt */\r\n  if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK) != RESET)\r\n\t{\r\n    if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CMPM) !=RESET)\r\n\t\t{\r\n      /* Clear Compare write flag */\r\n      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);\r\n      /* Compare write Callback */\r\n      HAL_LPTIM_CompareWriteCallback(hlptim);      \r\n    }\r\n  }\r\n  \r\n  /* Autoreload write interrupt */\r\n  if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET)\r\n\t{\r\n    if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) !=RESET)\r\n\t\t{\r\n      /* Clear Autoreload write flag */\r\n      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);\r\n      /* Autoreload write Callback */\r\n      HAL_LPTIM_AutoReloadWriteCallback(hlptim);      \r\n    }\r\n  }\r\n  \r\n  /* Direction counter changed from Down to Up interrupt */\r\n  if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET)\r\n\t{\r\n    if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) !=RESET)\r\n\t\t{\r\n      /* Clear Direction counter changed from Down to Up flag */\r\n      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP);\r\n      /* Direction counter changed from Down to Up Callback */\r\n      HAL_LPTIM_DirectionUpCallback(hlptim);      \r\n    }\r\n  }\r\n  \r\n  /* Direction counter changed from Up to Down interrupt */\r\n  if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET)\r\n\t{\r\n    if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) !=RESET)\r\n\t\t{\r\n      /* Clear Direction counter changed from Up to Down flag */\r\n      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN);\r\n      /* Direction counter changed from Up to Down Callback */\r\n      HAL_LPTIM_DirectionDownCallback(hlptim);      \r\n    }\r\n  }\r\n  \r\n  __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG();\r\n}\r\n\r\n/**\r\n  * @brief  Compare match callback in non blocking mode \r\n  * @param  hlptim : LPTIM handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hlptim);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_LPTIM_CompareMatchCallback could be implemented in the user file\r\n   */  \r\n}\r\n\r\n/**\r\n  * @brief  Autoreload match callback in non blocking mode \r\n  * @param  hlptim : LPTIM handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hlptim);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file\r\n   */  \r\n}\r\n\r\n/**\r\n  * @brief  Trigger detected callback in non blocking mode \r\n  * @param  hlptim : LPTIM handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hlptim);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_LPTIM_TriggerCallback could be implemented in the user file\r\n   */  \r\n}\r\n\r\n/**\r\n  * @brief  Compare write callback in non blocking mode \r\n  * @param  hlptim : LPTIM handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hlptim);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_LPTIM_CompareWriteCallback could be implemented in the user file\r\n   */  \r\n}\r\n\r\n/**\r\n  * @brief  Autoreload write callback in non blocking mode \r\n  * @param  hlptim : LPTIM handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hlptim);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file\r\n   */  \r\n}\r\n\r\n/**\r\n  * @brief  Direction counter changed from Down to Up callback in non blocking mode \r\n  * @param  hlptim : LPTIM handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hlptim);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_LPTIM_DirectionUpCallback could be implemented in the user file\r\n   */  \r\n}\r\n\r\n/**\r\n  * @brief  Direction counter changed from Up to Down callback in non blocking mode \r\n  * @param  hlptim : LPTIM handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hlptim);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_LPTIM_DirectionDownCallback could be implemented in the user file\r\n   */  \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LPTIM_Group5 Peripheral State functions \r\n *  @brief   Peripheral State functions. \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                      ##### Peripheral State functions #####\r\n  ==============================================================================  \r\n    [..]\r\n    This subsection permits to get in run-time the status of the peripheral.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Returns the LPTIM state.\r\n  * @param  hlptim: LPTIM handle\r\n  * @retval HAL state\r\n  */\r\nHAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim)\r\n{\r\n  return hlptim->State;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_LPTIM_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_ltdc.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   LTDC HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the LTDC peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + IO operation functions\r\n  *           + Peripheral Control functions  \r\n  *           + Peripheral State and Errors functions\r\n  *           \r\n  @verbatim      \r\n  ==============================================================================\r\n                        ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]\r\n     (#) Program the required configuration through the following parameters:   \r\n         the LTDC timing, the horizontal and vertical polarity, \r\n         the pixel clock polarity, Data Enable polarity and the LTDC background color value \r\n         using HAL_LTDC_Init() function\r\n\r\n     (#) Program the required configuration through the following parameters:   \r\n         the pixel format, the blending factors, input alpha value, the window size \r\n         and the image size using HAL_LTDC_ConfigLayer() function for foreground\r\n         or/and background layer.     \r\n  \r\n     (#) Optionally, configure and enable the CLUT using HAL_LTDC_ConfigCLUT() and \r\n         HAL_LTDC_EnableCLUT functions.\r\n       \r\n     (#) Optionally, enable the Dither using HAL_LTDC_EnableDither().       \r\n\r\n     (#) Optionally, configure and enable the Color keying using HAL_LTDC_ConfigColorKeying()\r\n         and HAL_LTDC_EnableColorKeying functions.\r\n\r\n     (#) Optionally, configure LineInterrupt using HAL_LTDC_ProgramLineEvent()\r\n         function\r\n\r\n     (#) If needed, reconfigure and change the pixel format value, the alpha value\r\n         value, the window size, the window position and the layer start address \r\n         for foreground or/and background layer using respectively the following \r\n         functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(),\r\n         HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetAddress.\r\n\r\n     (#) Variant functions with _NoReload post fix allows to set the LTDC configuration/settings without immediate reload.\r\n         This is useful in case when the program requires to modify serval LTDC settings (on one or both layers) \r\n         then applying(reload) these settings in one shot by calling the function HAL_LTDC_Reload\r\n\r\n         After calling the _NoReload functions to set different color/format/layer settings, \r\n         the program can call the function  HAL_LTDC_Reload To apply(Reload) these settings. \r\n         Function HAL_LTDC_Reload can be called with the parameter  ReloadType \r\n         set to LTDC_RELOAD_IMMEDIATE if an immediate reload is required.\r\n         Function HAL_LTDC_Reload can be called with the parameter  ReloadType \r\n         set to LTDC_RELOAD_VERTICAL_BLANKING if the reload should be done in the next vertical blanking period, \r\n         this option allows to avoid display flicker by applying the new settings during the vertical blanking period.\r\n           \r\n                     \r\n     (#) To control LTDC state you can use the following function: HAL_LTDC_GetState()               \r\n\r\n     *** LTDC HAL driver macros list ***\r\n     ============================================= \r\n     [..]\r\n       Below the list of most used macros in LTDC HAL driver.\r\n       \r\n      (+) __HAL_LTDC_ENABLE: Enable the LTDC.\r\n      (+) __HAL_LTDC_DISABLE: Disable the LTDC.\r\n      (+) __HAL_LTDC_LAYER_ENABLE: Enable the LTDC Layer.\r\n      (+) __HAL_LTDC_LAYER_DISABLE: Disable the LTDC Layer.\r\n      (+) __HAL_LTDC_RELOAD_CONFIG: Reload  Layer Configuration.\r\n      (+) __HAL_LTDC_GET_FLAG: Get the LTDC pending flags.\r\n      (+) __HAL_LTDC_CLEAR_FLAG: Clear the LTDC pending flags.\r\n      (+) __HAL_LTDC_ENABLE_IT: Enable the specified LTDC interrupts. \r\n      (+) __HAL_LTDC_DISABLE_IT: Disable the specified LTDC interrupts.\r\n      (+) __HAL_LTDC_GET_IT_SOURCE: Check whether the specified LTDC interrupt has occurred or not.\r\n      \r\n     [..] \r\n       (@) You can refer to the LTDC HAL driver header file for more useful macros\r\n  \r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n\r\n/** @defgroup LTDC LTDC\r\n  * @brief LTDC HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_LTDC_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/    \r\n/* Private function prototypes -----------------------------------------------*/\r\nstatic void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup LTDC_Exported_Functions LTDC Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup LTDC_Exported_Functions_Group1 Initialization and Configuration functions\r\n *  @brief   Initialization and Configuration functions\r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                ##### Initialization and Configuration functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Initialize and configure the LTDC\r\n      (+) De-initialize the LTDC \r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @brief  Initializes the LTDC according to the specified\r\n  *         parameters in the LTDC_InitTypeDef and create the associated handle.\r\n  * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                the configuration information for the LTDC.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)\r\n{\r\n  uint32_t tmp = 0, tmp1 = 0;\r\n\r\n  /* Check the LTDC peripheral state */\r\n  if(hltdc == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check function parameters */\r\n  assert_param(IS_LTDC_ALL_INSTANCE(hltdc->Instance));\r\n  assert_param(IS_LTDC_HSYNC(hltdc->Init.HorizontalSync));\r\n  assert_param(IS_LTDC_VSYNC(hltdc->Init.VerticalSync));\r\n  assert_param(IS_LTDC_AHBP(hltdc->Init.AccumulatedHBP));\r\n  assert_param(IS_LTDC_AVBP(hltdc->Init.AccumulatedVBP));\r\n  assert_param(IS_LTDC_AAH(hltdc->Init.AccumulatedActiveH));\r\n  assert_param(IS_LTDC_AAW(hltdc->Init.AccumulatedActiveW));\r\n  assert_param(IS_LTDC_TOTALH(hltdc->Init.TotalHeigh));\r\n  assert_param(IS_LTDC_TOTALW(hltdc->Init.TotalWidth));\r\n  assert_param(IS_LTDC_HSPOL(hltdc->Init.HSPolarity));\r\n  assert_param(IS_LTDC_VSPOL(hltdc->Init.VSPolarity));\r\n  assert_param(IS_LTDC_DEPOL(hltdc->Init.DEPolarity));\r\n  assert_param(IS_LTDC_PCPOL(hltdc->Init.PCPolarity));\r\n\r\n  if(hltdc->State == HAL_LTDC_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    hltdc->Lock = HAL_UNLOCKED;\r\n    /* Init the low level hardware */\r\n    HAL_LTDC_MspInit(hltdc);\r\n  }\r\n  \r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Configures the HS, VS, DE and PC polarity */\r\n  hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL);\r\n  hltdc->Instance->GCR |=  (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \\\r\n  hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);\r\n\r\n  /* Sets Synchronization size */\r\n  hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW);\r\n  tmp = (hltdc->Init.HorizontalSync << 16);\r\n  hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync);\r\n\r\n  /* Sets Accumulated Back porch */\r\n  hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP);\r\n  tmp = (hltdc->Init.AccumulatedHBP << 16);\r\n  hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP);\r\n\r\n  /* Sets Accumulated Active Width */\r\n  hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW);\r\n  tmp = (hltdc->Init.AccumulatedActiveW << 16);\r\n  hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH);\r\n\r\n  /* Sets Total Width */\r\n  hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW);\r\n  tmp = (hltdc->Init.TotalWidth << 16);\r\n  hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh);\r\n\r\n  /* Sets the background color value */\r\n  tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8);\r\n  tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16);\r\n  hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED);\r\n  hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue);\r\n\r\n  /* Enable the transfer Error interrupt */\r\n  __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE);\r\n\r\n  /* Enable the FIFO underrun interrupt */\r\n  __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_FU);\r\n\r\n  /* Enable LTDC by setting LTDCEN bit */\r\n  __HAL_LTDC_ENABLE(hltdc);\r\n\r\n  /* Initialize the error code */\r\n  hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;  \r\n\r\n  /* Initialize the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Deinitializes the LTDC peripheral registers to their default reset\r\n  *         values.\r\n  * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                the configuration information for the LTDC.\r\n  * @retval None\r\n  */\r\n\r\nHAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc)\r\n{\r\n  /* DeInit the low level hardware */\r\n  HAL_LTDC_MspDeInit(hltdc); \r\n\r\n  /* Initialize the error code */\r\n  hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;\r\n\r\n  /* Initialize the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_RESET;\r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the LTDC MSP.\r\n  * @param  hltdc : pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                the configuration information for the LTDC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hltdc);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_LTDC_MspInit could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the LTDC MSP.\r\n  * @param  hltdc : pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                the configuration information for the LTDC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hltdc);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_LTDC_MspDeInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup LTDC_Exported_Functions_Group2 IO operation functions \r\n *  @brief   IO operation functions  \r\n *\r\n@verbatim\r\n ===============================================================================\r\n                      #####  IO operation functions  #####\r\n ===============================================================================  \r\n    [..]  This section provides function allowing to:\r\n      (+) Handle LTDC interrupt request\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n/**\r\n  * @brief  Handles LTDC interrupt request.\r\n  * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                the configuration information for the LTDC.  \r\n  * @retval HAL status\r\n  */\r\nvoid HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc)\r\n{\r\n  /* Transfer Error Interrupt management ***************************************/\r\n  if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_TE) != RESET)\r\n  {\r\n    if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_TE) != RESET)\r\n    {\r\n      /* Disable the transfer Error interrupt */\r\n      __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE);\r\n\r\n      /* Clear the transfer error flag */\r\n      __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE);\r\n\r\n      /* Update error code */\r\n      hltdc->ErrorCode |= HAL_LTDC_ERROR_TE;\r\n\r\n      /* Change LTDC state */\r\n      hltdc->State = HAL_LTDC_STATE_ERROR;\r\n\r\n      /* Process unlocked */\r\n      __HAL_UNLOCK(hltdc);\r\n\r\n      /* Transfer error Callback */\r\n      HAL_LTDC_ErrorCallback(hltdc);\r\n    }\r\n  }\r\n  /* FIFO underrun Interrupt management ***************************************/\r\n  if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_FU) != RESET)\r\n  {\r\n    if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_FU) != RESET)\r\n    {\r\n      /* Disable the FIFO underrun interrupt */\r\n      __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU);\r\n\r\n      /* Clear the FIFO underrun flag */\r\n      __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU);\r\n\r\n      /* Update error code */\r\n      hltdc->ErrorCode |= HAL_LTDC_ERROR_FU;\r\n\r\n      /* Change LTDC state */\r\n      hltdc->State = HAL_LTDC_STATE_ERROR;\r\n\r\n      /* Process unlocked */\r\n      __HAL_UNLOCK(hltdc);\r\n      \r\n      /* Transfer error Callback */\r\n      HAL_LTDC_ErrorCallback(hltdc);\r\n    }\r\n  }\r\n  /* Line Interrupt management ************************************************/\r\n  if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_LI) != RESET)\r\n  {\r\n    if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_LI) != RESET)\r\n    {\r\n      /* Disable the Line interrupt */\r\n      __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI);\r\n\r\n      /* Clear the Line interrupt flag */  \r\n      __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI);\r\n\r\n      /* Change LTDC state */\r\n      hltdc->State = HAL_LTDC_STATE_READY;\r\n\r\n      /* Process unlocked */\r\n      __HAL_UNLOCK(hltdc);\r\n\r\n      /* Line interrupt Callback */\r\n      HAL_LTDC_LineEvenCallback(hltdc);\r\n    }\r\n  }\r\n  /* Register reload Interrupt management ***************************************/\r\n  if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_RR) != RESET)\r\n  {\r\n    if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_RR) != RESET)\r\n    {\r\n      /* Disable the register reload interrupt */\r\n      __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR);\r\n      \r\n      /* Clear the register reload flag */\r\n      __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR);\r\n      \r\n      /* Change LTDC state */\r\n      hltdc->State = HAL_LTDC_STATE_READY;\r\n      \r\n      /* Process unlocked */\r\n      __HAL_UNLOCK(hltdc);\r\n      \r\n      /* Register reload interrupt Callback */\r\n      HAL_LTDC_ReloadEventCallback(hltdc);\r\n    }\r\n  }  \r\n}\r\n\r\n/**\r\n  * @brief  Error LTDC callback.\r\n  * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                the configuration information for the LTDC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hltdc);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_LTDC_ErrorCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Line Event callback.\r\n  * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                the configuration information for the LTDC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_LTDC_LineEvenCallback(LTDC_HandleTypeDef *hltdc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hltdc);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_LTDC_LineEvenCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Reload Event callback.\r\n  * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                the configuration information for the LTDC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hltdc);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_LTDC_ReloadEvenCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LTDC_Exported_Functions_Group3 Peripheral Control functions\r\n *  @brief    Peripheral Control functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                    ##### Peripheral Control functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Configure the LTDC foreground or/and background parameters.\r\n      (+) Set the active layer.\r\n      (+) Configure the color keying.\r\n      (+) Configure the C-LUT.\r\n      (+) Enable / Disable the color keying.\r\n      (+) Enable / Disable the C-LUT.\r\n      (+) Update the layer position.\r\n      (+) Update the layer size.\r\n      (+) Update pixel format on the fly. \r\n      (+) Update transparency on the fly.\r\n      (+) Update address on the fly.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Configure the LTDC Layer according to the specified\r\n  *         parameters in the LTDC_InitTypeDef and create the associated handle.\r\n  * @param  hltdc:     pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                    the configuration information for the LTDC.\r\n  * @param  pLayerCfg: pointer to a LTDC_LayerCfgTypeDef structure that contains\r\n  *                    the configuration information for the Layer.\r\n  * @param  LayerIdx:  LTDC Layer index.\r\n  *                    This parameter can be one of the following values:\r\n  *                    0 or 1\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)\r\n{   \r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n  \r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n  assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat));\r\n  assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1));\r\n  assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));\r\n  assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));\r\n  assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));\r\n  assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));\r\n  assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));\r\n  assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0));\r\n  assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));\r\n  assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));\r\n\r\n  /* Copy new layer configuration into handle structure */\r\n  hltdc->LayerCfg[LayerIdx] = *pLayerCfg;  \r\n\r\n  /* Configure the LTDC Layer */  \r\n  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);\r\n\r\n  /* Sets the Reload type */\r\n  hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r\n\r\n  /* Initialize the LTDC state*/\r\n  hltdc->State  = HAL_LTDC_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Configure the color keying.\r\n  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  RGBValue: the color key value\r\n  * @param  LayerIdx:  LTDC Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0 or 1\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n\r\n  /* Configures the default color values */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CKCR &=  ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED);\r\n  LTDC_LAYER(hltdc, LayerIdx)->CKCR  = RGBValue;\r\n\r\n  /* Sets the Reload type */\r\n  hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Load the color lookup table.\r\n  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  pCLUT:    pointer to the color lookup table address.\r\n  * @param  CLUTSize: the color lookup table size.  \r\n  * @param  LayerIdx:  LTDC Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0 or 1\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx)\r\n{\r\n  uint32_t tmp = 0;\r\n  uint32_t counter = 0;\r\n  uint32_t pcounter = 0;\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;  \r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx)); \r\n\r\n  for(counter = 0; (counter < CLUTSize); counter++)\r\n  {\r\n    if(hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44)\r\n    {\r\n      tmp  = (((counter + 16*counter) << 24) | ((uint32_t)(*pCLUT) & 0xFF) | ((uint32_t)(*pCLUT) & 0xFF00) | ((uint32_t)(*pCLUT) & 0xFF0000));\r\n    }\r\n    else\r\n    { \r\n      tmp  = ((counter << 24) | ((uint32_t)(*pCLUT) & 0xFF) | ((uint32_t)(*pCLUT) & 0xFF00) | ((uint32_t)(*pCLUT) & 0xFF0000));\r\n    }\r\n    pcounter = (uint32_t)pCLUT + sizeof(*pCLUT);\r\n    pCLUT = (uint32_t *)pcounter;\r\n\r\n    /* Specifies the C-LUT address and RGB value */\r\n    LTDC_LAYER(hltdc, LayerIdx)->CLUTWR  = tmp;\r\n  }\r\n  \r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY; \r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);  \r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Enable the color keying.\r\n  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  LayerIdx:  LTDC Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0 or 1\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)\r\n{  \r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n\r\n  /* Enable LTDC color keying by setting COLKEN bit */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN;\r\n\r\n  /* Sets the Reload type */\r\n  hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY; \r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;  \r\n}\r\n  \r\n/**\r\n  * @brief  Disable the color keying.\r\n  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  LayerIdx:  LTDC Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0 or 1\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n\r\n  /* Disable LTDC color keying by setting COLKEN bit */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN;\r\n\r\n  /* Sets the Reload type */\r\n  hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY; \r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Enable the color lookup table.\r\n  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  LayerIdx:  LTDC Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0 or 1\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)\r\n{\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n\r\n  /* Disable LTDC color lookup table by setting CLUTEN bit */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN;\r\n\r\n  /* Sets the Reload type */\r\n  hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY; \r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Disable the color lookup table.\r\n  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  LayerIdx:  LTDC Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0 or 1   \r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)\r\n{\r\n \r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n\r\n  /* Disable LTDC color lookup table by setting CLUTEN bit */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN;\r\n\r\n  /* Sets the Reload type */\r\n  hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY; \r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Enables Dither.\r\n  * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                the configuration information for the LTDC.\r\n  * @retval  HAL status\r\n  */\r\n\r\nHAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Enable Dither by setting DTEN bit */\r\n  LTDC->GCR |= (uint32_t)LTDC_GCR_DEN;\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY; \r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Disables Dither.\r\n  * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                the configuration information for the LTDC.\r\n  * @retval  HAL status\r\n  */\r\n\r\nHAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Disable Dither by setting DTEN bit */\r\n  LTDC->GCR &= ~(uint32_t)LTDC_GCR_DEN;\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Set the LTDC window size.\r\n  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  XSize:    LTDC Pixel per line\r\n  * @param  YSize:    LTDC Line number\r\n  * @param  LayerIdx:  LTDC Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0 or 1\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) \r\n{\r\n  LTDC_LayerCfgTypeDef *pLayerCfg;\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY; \r\n\r\n  /* Get layer configuration from handle structure */\r\n  pLayerCfg = &hltdc->LayerCfg[LayerIdx];\r\n\r\n  /* Check the parameters (Layers parameters)*/\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n  assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));\r\n  assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));\r\n  assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));\r\n  assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));\r\n  assert_param(IS_LTDC_CFBLL(XSize));\r\n  assert_param(IS_LTDC_CFBLNBR(YSize));\r\n\r\n  /* update horizontal start/stop */\r\n  pLayerCfg->WindowX0 = 0;\r\n  pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0;\r\n\r\n  /* update vertical start/stop */  \r\n  pLayerCfg->WindowY0 = 0;\r\n  pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0;\r\n\r\n  /* Reconfigures the color frame buffer pitch in byte */\r\n  pLayerCfg->ImageWidth = XSize;\r\n\r\n  /* Reconfigures the frame buffer line number */\r\n  pLayerCfg->ImageHeight = YSize;\r\n\r\n  /* Set LTDC parameters */\r\n  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);\r\n\r\n  /* Sets the Reload type */\r\n  hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Set the LTDC window position.\r\n  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  X0:       LTDC window X offset\r\n  * @param  Y0:       LTDC window Y offset\r\n  * @param  LayerIdx:  LTDC Layer index.\r\n  *                         This parameter can be one of the following values:\r\n  *                         0 or 1\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)\r\n{\r\n  LTDC_LayerCfgTypeDef *pLayerCfg;\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Get layer configuration from handle structure */\r\n  pLayerCfg = &hltdc->LayerCfg[LayerIdx];\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n  assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));\r\n  assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));\r\n  assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));\r\n  assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));\r\n\r\n  /* update horizontal start/stop */\r\n  pLayerCfg->WindowX0 = X0;\r\n  pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth;\r\n\r\n  /* update vertical start/stop */\r\n  pLayerCfg->WindowY0 = Y0;\r\n  pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight;\r\n\r\n  /* Set LTDC parameters */\r\n  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);\r\n\r\n  /* Sets the Reload type */\r\n  hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Reconfigure the pixel format.\r\n  * @param  hltdc:       pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                      the configuration information for the LTDC.\r\n  * @param  Pixelformat: new pixel format value.\r\n  * @param  LayerIdx:    LTDC Layer index.\r\n  *                      This parameter can be one of the following values:\r\n  *                      0 or 1.\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)\r\n{\r\n  LTDC_LayerCfgTypeDef *pLayerCfg;\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n  assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat));\r\n\r\n  /* Get layer configuration from handle structure */\r\n  pLayerCfg = &hltdc->LayerCfg[LayerIdx];  \r\n\r\n  /* Reconfigure the pixel format */\r\n  pLayerCfg->PixelFormat = Pixelformat;\r\n\r\n  /* Set LTDC parameters */\r\n  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);   \r\n\r\n  /* Sets the Reload type */\r\n  hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Reconfigure the layer alpha value.\r\n  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  Alpha:    new alpha value.\r\n  * @param  LayerIdx:  LTDC Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0 or 1\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)\r\n{\r\n  LTDC_LayerCfgTypeDef *pLayerCfg;\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_ALPHA(Alpha));\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n\r\n  /* Get layer configuration from handle structure */\r\n  pLayerCfg = &hltdc->LayerCfg[LayerIdx];\r\n\r\n  /* Reconfigure the Alpha value */\r\n  pLayerCfg->Alpha = Alpha;\r\n\r\n  /* Set LTDC parameters */\r\n  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);\r\n\r\n  /* Sets the Reload type */\r\n  hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n/**\r\n  * @brief  Reconfigure the frame buffer Address.\r\n  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  Address:  new address value.\r\n  * @param  LayerIdx: LTDC Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0 or 1.\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)\r\n{\r\n  LTDC_LayerCfgTypeDef *pLayerCfg;\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n\r\n  /* Get layer configuration from handle structure */\r\n  pLayerCfg = &hltdc->LayerCfg[LayerIdx];\r\n\r\n  /* Reconfigure the Address */\r\n  pLayerCfg->FBStartAdress = Address;\r\n\r\n  /* Set LTDC parameters */\r\n  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);\r\n\r\n  /* Sets the Reload type */\r\n  hltdc->Instance->SRCR = LTDC_SRCR_IMR;\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is\r\n  *         larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we \r\n  *         want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels \r\n  *         will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer().\r\n  *         Note : this function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch\r\n  *                configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).\r\n  * @param  hltdc:             pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                            the configuration information for the LTDC.\r\n  * @param  LinePitchInPixels: New line pitch in pixels to configure for LTDC layer 'LayerIdx'.\r\n  * @param  LayerIdx:          LTDC layer index concerned by the modification of line pitch.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)\r\n{\r\n  uint32_t tmp = 0;\r\n  uint32_t pitchUpdate = 0;\r\n  uint32_t pixelFormat = 0;\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n  \r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n  \r\n  /* get LayerIdx used pixel format */\r\n  pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat;\r\n  \r\n  if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)\r\n  {\r\n    tmp = 4;\r\n  }\r\n  else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888)\r\n  {\r\n    tmp = 3;\r\n  }\r\n  else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \\\r\n          (pixelFormat == LTDC_PIXEL_FORMAT_RGB565)   || \\\r\n          (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \\\r\n         (pixelFormat == LTDC_PIXEL_FORMAT_AL88))\r\n  {\r\n    tmp = 2;\r\n  }\r\n  else\r\n  {\r\n    tmp = 1;\r\n  }\r\n  \r\n  pitchUpdate = ((LinePitchInPixels * tmp) << 16);\r\n  \r\n  /* Clear previously set standard pitch */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP;\r\n  \r\n  /* Sets the Reload type as immediate update of LTDC pitch configured above */\r\n  LTDC->SRCR |= LTDC_SRCR_IMR;\r\n  \r\n  /* Set new line pitch value */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate;\r\n  \r\n  /* Sets the Reload type as immediate update of LTDC pitch configured above */\r\n  LTDC->SRCR |= LTDC_SRCR_IMR;\r\n  \r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Define the position of the line interrupt.\r\n  * @param  hltdc:             pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                            the configuration information for the LTDC.\r\n  * @param  Line:   Line Interrupt Position.\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LIPOS(Line));\r\n\r\n  /* Enable the Line interrupt */\r\n  __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_LI);\r\n\r\n  /* Sets the Line Interrupt position */\r\n  LTDC->LIPCR = (uint32_t)Line;\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  LTDC configuration reload.\r\n  * @param  hltdc:            pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                           the configuration information for the LTDC.\r\n  * @param  ReloadType:       This parameter can be one of the following values :\r\n  *                           LTDC_RELOAD_IMMEDIATE : Immediate Reload\r\n  *                           LTDC_RELOAD_VERTICAL_BLANKING  : Reload in the next Vertical Blanking\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef  HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType)\r\n{\r\n  assert_param(IS_LTDC_RELAOD(ReloadType));\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;  \r\n  \r\n  /* Enable the Reload interrupt */  \r\n  __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_RR);\r\n       \r\n  /* Apply Reload type */\r\n  hltdc->Instance->SRCR = ReloadType;        \r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Configure the LTDC Layer according to the specified without reloading\r\n  *         parameters in the LTDC_InitTypeDef and create the associated handle.\r\n  *         Variant of the function HAL_LTDC_ConfigLayer without immediate reload\r\n  * @param  hltdc:     pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                    the configuration information for the LTDC.\r\n  * @param  pLayerCfg: pointer to a LTDC_LayerCfgTypeDef structure that contains\r\n  *                    the configuration information for the Layer.\r\n  * @param  LayerIdx:  LTDC Layer index.\r\n  *                    This parameter can be one of the following values:\r\n  *                    0 or 1\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)\r\n{   \r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n  \r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n  assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat));\r\n  assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1));\r\n  assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));\r\n  assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));\r\n  assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));\r\n  assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));\r\n  assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));\r\n  assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0));\r\n  assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));\r\n  assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));\r\n\r\n  /* Copy new layer configuration into handle structure */\r\n  hltdc->LayerCfg[LayerIdx] = *pLayerCfg;  \r\n\r\n  /* Configure the LTDC Layer */  \r\n  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);\r\n\r\n  /* Do not Sets the Reload  */\r\n\r\n  /* Initialize the LTDC state*/\r\n  hltdc->State  = HAL_LTDC_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Set the LTDC window size without reloading.\r\n  *         Variant of the function HAL_LTDC_SetWindowSize without immediate reload\r\n  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  XSize:    LTDC Pixel per line\r\n  * @param  YSize:    LTDC Line number\r\n  * @param  LayerIdx:  LTDC Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0 or 1\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) \r\n{\r\n  LTDC_LayerCfgTypeDef *pLayerCfg;\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY; \r\n\r\n  /* Get layer configuration from handle structure */\r\n  pLayerCfg = &hltdc->LayerCfg[LayerIdx];\r\n\r\n  /* Check the parameters (Layers parameters)*/\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n  assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));\r\n  assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));\r\n  assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));\r\n  assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));\r\n  assert_param(IS_LTDC_CFBLL(XSize));\r\n  assert_param(IS_LTDC_CFBLNBR(YSize));\r\n\r\n  /* update horizontal start/stop */\r\n  pLayerCfg->WindowX0 = 0;\r\n  pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0;\r\n\r\n  /* update vertical start/stop */  \r\n  pLayerCfg->WindowY0 = 0;\r\n  pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0;\r\n\r\n  /* Reconfigures the color frame buffer pitch in byte */\r\n  pLayerCfg->ImageWidth = XSize;\r\n\r\n  /* Reconfigures the frame buffer line number */\r\n  pLayerCfg->ImageHeight = YSize;\r\n\r\n  /* Set LTDC parameters */\r\n  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);\r\n\r\n  /* Do not Sets the Reload  */\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Set the LTDC window position without reloading.\r\n  *         Variant of the function HAL_LTDC_SetWindowPosition without immediate reload\r\n  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  X0:       LTDC window X offset\r\n  * @param  Y0:       LTDC window Y offset\r\n  * @param  LayerIdx:  LTDC Layer index.\r\n  *                         This parameter can be one of the following values:\r\n  *                         0 or 1\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)\r\n{\r\n  LTDC_LayerCfgTypeDef *pLayerCfg;\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Get layer configuration from handle structure */\r\n  pLayerCfg = &hltdc->LayerCfg[LayerIdx];\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n  assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));\r\n  assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));\r\n  assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));\r\n  assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));\r\n\r\n  /* update horizontal start/stop */\r\n  pLayerCfg->WindowX0 = X0;\r\n  pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth;\r\n\r\n  /* update vertical start/stop */\r\n  pLayerCfg->WindowY0 = Y0;\r\n  pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight;\r\n\r\n  /* Set LTDC parameters */\r\n  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);\r\n\r\n  /* Do not Sets the Reload  */\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Reconfigure the pixel format without reloading.\r\n  *         Variant of the function HAL_LTDC_SetPixelFormat without immediate reload\r\n  * @param  hltdc:       pointer to a LTDC_HandleTypeDfef structure that contains\r\n  *                      the configuration information for the LTDC.\r\n  * @param  Pixelformat: new pixel format value.\r\n  * @param  LayerIdx:    LTDC Layer index.\r\n  *                      This parameter can be one of the following values:\r\n  *                      0 or 1.\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)\r\n{\r\n  LTDC_LayerCfgTypeDef *pLayerCfg;\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n  assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat));\r\n\r\n  /* Get layer configuration from handle structure */\r\n  pLayerCfg = &hltdc->LayerCfg[LayerIdx];  \r\n\r\n  /* Reconfigure the pixel format */\r\n  pLayerCfg->PixelFormat = Pixelformat;\r\n\r\n  /* Set LTDC parameters */\r\n  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);   \r\n\r\n  /* Do not Sets the Reload  */\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Reconfigure the layer alpha value without reloading.\r\n  *         Variant of the function HAL_LTDC_SetAlpha without immediate reload\r\n  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  Alpha:    new alpha value.\r\n  * @param  LayerIdx:  LTDC Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0 or 1\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)\r\n{\r\n  LTDC_LayerCfgTypeDef *pLayerCfg;\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_ALPHA(Alpha));\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n\r\n  /* Get layer configuration from handle structure */\r\n  pLayerCfg = &hltdc->LayerCfg[LayerIdx];\r\n\r\n  /* Reconfigure the Alpha value */\r\n  pLayerCfg->Alpha = Alpha;\r\n\r\n  /* Set LTDC parameters */\r\n  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);\r\n\r\n  /* Do not Sets the Reload  */\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Reconfigure the frame buffer Address without reloading.\r\n  *         Variant of the function HAL_LTDC_SetAddress without immediate reload   \r\n  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  Address:  new address value.\r\n  * @param  LayerIdx: LTDC Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0 or 1.\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)\r\n{\r\n  LTDC_LayerCfgTypeDef *pLayerCfg;\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n\r\n  /* Get layer configuration from handle structure */\r\n  pLayerCfg = &hltdc->LayerCfg[LayerIdx];\r\n\r\n  /* Reconfigure the Address */\r\n  pLayerCfg->FBStartAdress = Address;\r\n\r\n  /* Set LTDC parameters */\r\n  LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);\r\n\r\n  /* Do not Sets the Reload  */\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is\r\n  *         larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we \r\n  *         want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels \r\n  *         will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer().\r\n  *         Note : this function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch\r\n  *                configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).\r\n  *         Variant of the function HAL_LTDC_SetPitch without immediate reload    \r\n  * @param  hltdc:             pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                            the configuration information for the LTDC.\r\n  * @param  LinePitchInPixels: New line pitch in pixels to configure for LTDC layer 'LayerIdx'.\r\n  * @param  LayerIdx:          LTDC layer index concerned by the modification of line pitch.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)\r\n{\r\n  uint32_t tmp = 0;\r\n  uint32_t pitchUpdate = 0;\r\n  uint32_t pixelFormat = 0;\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n  \r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n  \r\n  /* get LayerIdx used pixel format */\r\n  pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat;\r\n  \r\n  if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)\r\n  {\r\n    tmp = 4;\r\n  }\r\n  else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888)\r\n  {\r\n    tmp = 3;\r\n  }\r\n  else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \\\r\n          (pixelFormat == LTDC_PIXEL_FORMAT_RGB565)   || \\\r\n          (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \\\r\n         (pixelFormat == LTDC_PIXEL_FORMAT_AL88))\r\n  {\r\n    tmp = 2;\r\n  }\r\n  else\r\n  {\r\n    tmp = 1;\r\n  }\r\n  \r\n  pitchUpdate = ((LinePitchInPixels * tmp) << 16);\r\n  \r\n  /* Clear previously set standard pitch */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP;\r\n  \r\n  /* Set new line pitch value */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate;\r\n  \r\n  /* Do not Sets the Reload  */\r\n  \r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n\r\n/**\r\n  * @brief  Configure the color keying without reloading.\r\n  *         Variant of the function HAL_LTDC_ConfigColorKeying without immediate reload\r\n  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  RGBValue: the color key value\r\n  * @param  LayerIdx:  LTDC Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0 or 1\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n\r\n  /* Configures the default color values */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CKCR &=  ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED);\r\n  LTDC_LAYER(hltdc, LayerIdx)->CKCR  = RGBValue;\r\n\r\n  /* Do not Sets the Reload  */\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Enable the color keying without reloading.\r\n  *         Variant of the function HAL_LTDC_EnableColorKeying without immediate reload\r\n  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  LayerIdx:  LTDC Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0 or 1\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)\r\n{  \r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n\r\n  /* Enable LTDC color keying by setting COLKEN bit */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN;\r\n\r\n  /* Do not Sets the Reload  */\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY; \r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Disable the color keying without reloading.\r\n  *         Variant of the function HAL_LTDC_DisableColorKeying without immediate reload\r\n  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  LayerIdx:  LTDC Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0 or 1\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)\r\n{\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n\r\n  /* Disable LTDC color keying by setting COLKEN bit */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN;\r\n\r\n  /* Do not Sets the Reload  */\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY; \r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Enable the color lookup table without reloading.\r\n  *         Variant of the function HAL_LTDC_EnableCLUT without immediate reload\r\n  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  LayerIdx:  LTDC Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0 or 1\r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)\r\n{\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n\r\n  /* Disable LTDC color lookup table by setting CLUTEN bit */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN;\r\n\r\n  /* Do not Sets the Reload  */\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY; \r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Disable the color lookup table without reloading.\r\n  *         Variant of the function HAL_LTDC_DisableCLUT without immediate reload\r\n  * @param  hltdc:    pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  LayerIdx:  LTDC Layer index.\r\n  *                   This parameter can be one of the following values:\r\n  *                   0 or 1   \r\n  * @retval  HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)\r\n{\r\n \r\n  /* Process locked */\r\n  __HAL_LOCK(hltdc);\r\n\r\n  /* Change LTDC peripheral state */\r\n  hltdc->State = HAL_LTDC_STATE_BUSY;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_LTDC_LAYER(LayerIdx));\r\n\r\n  /* Disable LTDC color lookup table by setting CLUTEN bit */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN;\r\n\r\n  /* Do not Sets the Reload  */\r\n\r\n  /* Change the LTDC state*/\r\n  hltdc->State = HAL_LTDC_STATE_READY; \r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hltdc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup LTDC_Exported_Functions_Group4 Peripheral State and Errors functions\r\n *  @brief    Peripheral State and Errors functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                  ##### Peripheral State and Errors functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides functions allowing to\r\n      (+) Check the LTDC state.\r\n      (+) Get error code.  \r\n\r\n@endverbatim\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @brief  Return the LTDC state\r\n  * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                the configuration information for the LTDC.\r\n  * @retval HAL state\r\n  */\r\nHAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc)\r\n{\r\n  return hltdc->State;\r\n}\r\n\r\n/**\r\n* @brief  Return the LTDC error code\r\n* @param  hltdc : pointer to a LTDC_HandleTypeDef structure that contains\r\n  *               the configuration information for the LTDC.\r\n* @retval LTDC Error Code\r\n*/\r\nuint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc)\r\n{\r\n  return hltdc->ErrorCode;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @brief  Configures the LTDC peripheral \r\n  * @param  hltdc   :  Pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                   the configuration information for the LTDC.\r\n  * @param  pLayerCfg: Pointer LTDC Layer Configuration structure\r\n  * @param  LayerIdx:  LTDC Layer index.\r\n  *                    This parameter can be one of the following values: 0 or 1\r\n  * @retval None\r\n  */\r\nstatic void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)\r\n{\r\n  uint32_t tmp = 0;\r\n  uint32_t tmp1 = 0;\r\n  uint32_t tmp2 = 0;\r\n\r\n  /* Configures the horizontal start and stop position */\r\n  tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16)) << 16);\r\n  LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS);\r\n  LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16) + 1) | tmp);\r\n\r\n  /* Configures the vertical start and stop position */\r\n  tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16);\r\n  LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS);\r\n  LTDC_LAYER(hltdc, LayerIdx)->WVPCR  = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1) | tmp);  \r\n\r\n  /* Specifies the pixel format */\r\n  LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF);\r\n  LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat);\r\n\r\n  /* Configures the default color values */\r\n  tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8);\r\n  tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16);\r\n  tmp2 = (pLayerCfg->Alpha0 << 24);  \r\n  LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA);\r\n  LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2); \r\n\r\n  /* Specifies the constant alpha value */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA);\r\n  LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha);\r\n\r\n  /* Specifies the blending factors */\r\n  LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1);\r\n  LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2);\r\n\r\n  /* Configures the color frame buffer start address */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD);\r\n  LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress);\r\n\r\n  if(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)\r\n  {\r\n    tmp = 4;\r\n  }\r\n  else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888)\r\n  {\r\n    tmp = 3;\r\n  }\r\n  else if((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \\\r\n    (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565)   || \\\r\n      (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \\\r\n        (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88))\r\n  {\r\n    tmp = 2;\r\n  }\r\n  else\r\n  {\r\n    tmp = 1;\r\n  }\r\n\r\n  /* Configures the color frame buffer pitch in byte */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CFBLR  &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP);\r\n  LTDC_LAYER(hltdc, LayerIdx)->CFBLR  = (((pLayerCfg->ImageWidth * tmp) << 16) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp)  + 3));\r\n\r\n  /* Configures the frame buffer line number */\r\n  LTDC_LAYER(hltdc, LayerIdx)->CFBLNR  &= ~(LTDC_LxCFBLNR_CFBLNBR);\r\n  LTDC_LAYER(hltdc, LayerIdx)->CFBLNR  = (pLayerCfg->ImageHeight);\r\n\r\n  /* Enable LTDC_Layer by setting LEN bit */  \r\n  LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_LTDC_MODULE_ENABLED */\r\n\r\n/**\r\n  * @}\r\n  */\r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_ltdc_ex.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   LTDC Extension HAL module driver.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n/** @defgroup LTDCEx LTDCEx\r\n  * @brief LTDC HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_LTDC_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @defgroup LTDCEx_Exported_Functions LTDC Extended Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup LTDCEx_Exported_Functions_Group1 Initialization and Configuration functions\r\n *  @brief   Initialization and Configuration functions\r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                ##### Initialization and Configuration functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Initialize and configure the LTDC\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n#if defined (STM32F769xx) || defined (STM32F779xx)\r\n/**\r\n  * @brief  Retrieve common parameters from DSI Video mode configuration structure\r\n  * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                the configuration information for the LTDC.\r\n  * @param  VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains\r\n  *                 the DSI video mode configuration parameters\r\n  * @note   The implementation of this function is taking into account the LTDC\r\n  *         polarities inversion as described in the current LTDC specification\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_StructInitFromVideoConfig(LTDC_HandleTypeDef* hltdc, DSI_VidCfgTypeDef *VidCfg)\r\n{\r\n  /* Retrieve signal polarities from DSI */\r\n  \r\n  /* The following polarities are inverted:\r\n                     LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH\r\n\t                   LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH\r\n\t                   LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/\r\n  \r\n  /* Note 1 : Code in line w/ Current LTDC specification */\r\n  hltdc->Init.DEPolarity = (VidCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;\r\n  hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH;\r\n  hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH;\r\n\r\n  /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */\r\n  /* hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29;\r\n     hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29;\r\n     hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29; */\r\n    \r\n  /* Retrieve vertical timing parameters from DSI */\r\n  hltdc->Init.VerticalSync       = VidCfg->VerticalSyncActive - 1;\r\n  hltdc->Init.AccumulatedVBP     = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1;\r\n  hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive - 1;\r\n  hltdc->Init.TotalHeigh         = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1;\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Retrieve common parameters from DSI Adapted command mode configuration structure\r\n  * @param  hltdc: pointer to a LTDC_HandleTypeDef structure that contains\r\n  *                the configuration information for the LTDC.\r\n  * @param  CmdCfg: pointer to a DSI_CmdCfgTypeDef structure that contains\r\n  *                 the DSI command mode configuration parameters\r\n  * @note   The implementation of this function is taking into account the LTDC\r\n  *         polarities inversion as described in the current LTDC specification\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LTDC_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef* hltdc, DSI_CmdCfgTypeDef *CmdCfg)\r\n{\r\n  /* Retrieve signal polarities from DSI */\r\n  \r\n  /* The following polarities are inverted:\r\n                     LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH\r\n\t                   LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH\r\n\t                   LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/\r\n  \r\n  /* Note 1 : Code in line w/ Current LTDC specification */\r\n  hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;\r\n  hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH;\r\n  hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH;\r\n  \r\n  /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */\r\n  /* hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29;\r\n     hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29;\r\n     hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29; */\r\n  \r\n  return HAL_OK;\r\n}\r\n#endif /*STM32F769xx | STM32F779xx */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_LTCD_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_mdios.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_mdios.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   MDIOS HAL module driver.\r\n  * \r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the MDIOS Peripheral.\r\n  *           + Initialization and de-initialization functions\r\n  *           + IO operation functions\r\n  *           + Peripheral Control functions\r\n  *\r\n  *           \r\n  @verbatim       \r\n ===============================================================================\r\n                        ##### How to use this driver #####\r\n ===============================================================================\r\n    [..]\r\n    The MDIOS HAL driver can be used as follow:\r\n\r\n    (#) Declare a MDIOS_HandleTypeDef handle structure.\r\n\r\n    (#) Initialize the MDIOS low level resources by implementing the HAL_MDIOS_MspInit() API:\r\n        (##) Enable the MDIOS interface clock.\r\n        (##) MDIOS pins configuration:\r\n            (+++) Enable clocks for the MDIOS GPIOs.\r\n            (+++) Configure the MDIOS pins as alternate function.\r\n        (##) NVIC configuration if you need to use interrupt process:\r\n            (+++) Configure the MDIOS interrupt priority.\r\n            (+++) Enable the NVIC MDIOS IRQ handle.\r\n\r\n    (#) Program the Port Address and the Preamble Check in the Init structure.\r\n\r\n    (#) Initialize the MDIOS registers by calling the HAL_MDIOS_Init() API.\r\n\r\n    (#) Perform direct slave read/write operations using the following APIs:\r\n        (##) Read the value of a DINn register: HAL_MDIOS_ReadReg()\r\n        (##) Write a value to a DOUTn register: HAL_MDIOS_WriteReg()\r\n\r\n    (#) Get the Master read/write operations flags using the following APIs:\r\n        (##) Bit map of DOUTn registers read by Master: HAL_MDIOS_GetReadRegAddress()\r\n        (##) Bit map of DINn registers written by Master : HAL_MDIOS_GetWrittenRegAddress()\r\n\r\n    (#) Clear the read/write flags using the following APIs:\r\n        (##) Clear read flags of a set of registers: HAL_MDIOS_ClearReadRegAddress()\r\n        (##) Clear write flags of a set of registers: HAL_MDIOS_ClearWriteRegAddress()\r\n\r\n    (#) Enable interrupts on events using HAL_MDIOS_EnableEvents(), when called\r\n        the MDIOS will generate an interrupt in the following cases: \r\n        (##) a DINn register written by the Master\r\n        (##) a DOUTn register read by the Master\r\n        (##) an error occur\r\n\r\n        (@) A callback is executed for each genereted interrupt, so the driver provide the following \r\n            HAL_MDIOS_WriteCpltCallback(), HAL_MDIOS_ReadCpltCallback() and HAL_MDIOS_ErrorCallback()\r\n        (@) HAL_MDIOS_IRQHandler() must be called from the MDIOS IRQ Handler, to handle the interrupt\r\n            and execute the previous callbacks\r\n   \r\n    (#) Reset the MDIOS peripheral and all related ressources by calling the HAL_MDIOS_DeInit() API.\r\n        (##) HAL_MDIOS_MspDeInit() must be implemented to reset low level ressources \r\n            (GPIO, Clocks, NVIC configuration ...)\r\n\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************  \r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup MDIOS MDIOS\r\n  * @brief HAL MDIOS module driver\r\n  * @{\r\n  */\r\n#ifdef HAL_MDIOS_MODULE_ENABLED\r\n    \r\n#if defined (MDIOS)\r\n    \r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n#define MDIOS_PORT_ADDRESS_SHIFT        ((uint32_t)8)\r\n#define\tMDIOS_ALL_REG_FLAG\t        ((uint32_t)0xFFFFFFFFU)\r\n#define\tMDIOS_ALL_ERRORS_FLAG           ((uint32_t)(MDIOS_SR_PERF | MDIOS_SR_SERF | MDIOS_SR_TERF))\r\n\r\n#define MDIOS_DIN_BASE_ADDR             (MDIOS_BASE + 0x100)\r\n#define MDIOS_DOUT_BASE_ADDR            (MDIOS_BASE + 0x180)\r\n\r\n/* Private macro -------------------------------------------------------------*/ \r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup MDIOS_Exported_Functions MDIOS Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup MDIOS_Exported_Functions_Group1 Initialization/de-initialization functions \r\n  *  @brief    Initialization and Configuration functions \r\n  *\r\n@verbatim                                               \r\n===============================================================================\r\n            ##### Initialization and Configuration functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides a set of functions allowing to initialize the MDIOS\r\n      (+) The following parameters can be configured: \r\n        (++) Port Address\r\n        (++) Preamble Check\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the MDIOS according to the specified parameters in \r\n  *         the MDIOS_InitTypeDef and creates the associated handle .\r\n  * @param  hmdios: pointer to a MDIOS_HandleTypeDef structure that contains\r\n  *         the configuration information for MDIOS module\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_MDIOS_Init(MDIOS_HandleTypeDef *hmdios)\r\n{\r\n  uint32_t tmpcr = 0;\r\n\r\n  /* Check the MDIOS handle allocation */\r\n  if(hmdios == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_MDIOS_ALL_INSTANCE(hmdios->Instance));\r\n  assert_param(IS_MDIOS_PORTADDRESS(hmdios->Init.PortAddress));\r\n  assert_param(IS_MDIOS_PREAMBLECHECK(hmdios->Init.PreambleCheck));\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hmdios);\r\n  \r\n  if(hmdios->State == HAL_MDIOS_STATE_RESET)\r\n  {\r\n    /* Init the low level hardware */\r\n    HAL_MDIOS_MspInit(hmdios);\r\n  }\r\n  \r\n  /* Change the MDIOS state */\r\n  hmdios->State = HAL_MDIOS_STATE_BUSY;\r\n  \r\n  /* Get the MDIOS CR value */\r\n  tmpcr = hmdios->Instance->CR;\r\n  \r\n  /* Clear PORT_ADDRESS, DPC and EN bits */\r\n  tmpcr &= ((uint32_t)~(MDIOS_CR_EN | MDIOS_CR_DPC | MDIOS_CR_PORT_ADDRESS));\r\n  \r\n  /* Set MDIOS control parametrs and enable the peripheral */\r\n  tmpcr |=  (uint32_t)(((hmdios->Init.PortAddress) << MDIOS_PORT_ADDRESS_SHIFT)    |\\\r\n                        (hmdios->Init.PreambleCheck) | \\\r\n                        (MDIOS_CR_EN));\r\n  \r\n  /* Write the MDIOS CR */\r\n  hmdios->Instance->CR = tmpcr;\r\n  \r\n  /* Change the MDIOS state */\r\n  hmdios->State = HAL_MDIOS_STATE_READY;\r\n  \r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hmdios);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the MDIOS peripheral.\r\n  * @param  hmdios: MDIOS handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_MDIOS_DeInit(MDIOS_HandleTypeDef *hmdios)\r\n{\r\n  /* Check the MDIOS handle allocation */\r\n  if(hmdios == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_MDIOS_ALL_INSTANCE(hmdios->Instance));\r\n  \r\n  /* Change the MDIOS state */\r\n  hmdios->State = HAL_MDIOS_STATE_BUSY;\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_MDIOS_DISABLE(hmdios);\r\n  \r\n  /* DeInit the low level hardware */\r\n  HAL_MDIOS_MspDeInit(hmdios);\r\n  \r\n  /* Change the MDIOS state */\r\n  hmdios->State = HAL_MDIOS_STATE_RESET;\r\n  \r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hmdios);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  MDIOS MSP Init\r\n  * @param  hmdios: mdios handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_MDIOS_MspInit(MDIOS_HandleTypeDef *hmdios)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hmdios);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_MDIOS_MspInit can be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  MDIOS MSP DeInit\r\n  * @param  hmdios: mdios handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_MDIOS_MspDeInit(MDIOS_HandleTypeDef *hmdios)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hmdios);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_MDIOS_MspDeInit can be implemented in the user file\r\n   */ \r\n}\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup MDIOS_Exported_Functions_Group2 IO operation functions \r\n  *  @brief MDIOS Read/Write functions \r\n  *\r\n@verbatim   \r\n ===============================================================================\r\n                      ##### IO operation functions #####\r\n ===============================================================================\r\n    This subsection provides a set of functions allowing to manage the MDIOS \r\n    read and write operations.\r\n\r\n    (#) APIs that allow to the MDIOS to read/write from/to the \r\n        values of one of the DINn/DOUTn registers:\r\n        (+) Read the value of a DINn register: HAL_MDIOS_ReadReg()\r\n        (+) Write a value to a DOUTn register: HAL_MDIOS_WriteReg()\r\n\r\n    (#) APIs that provide if there are some Slave registres have been \r\n        read or written by the Master:\r\n        (+) DOUTn registers read by Master: HAL_MDIOS_GetReadRegAddress()\r\n        (+) DINn registers written by Master : HAL_MDIOS_GetWrittenRegAddress()\r\n\r\n    (#) APIs that Clear the read/write flags:\r\n        (+) Clear read registers flags: HAL_MDIOS_ClearReadRegAddress()\r\n        (+) Clear write registers flags: HAL_MDIOS_ClearWriteRegAddress()\r\n\r\n    (#) A set of Callbacks are provided:\r\n        (+) HAL_MDIOS_WriteCpltCallback()\r\n        (+) HAL_MDIOS_ReadCpltCallback()\r\n        (+) HAL_MDIOS_ErrorCallback() \r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Writes to an MDIOS output register\r\n  * @param  hmdios: mdios handle\r\n  * @param  RegNum: MDIOS input register number    \r\n  * @param  Data: Data to write\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_MDIOS_WriteReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t Data)\r\n{\r\n  uint32_t tmpreg;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_MDIOS_REGISTER(RegNum));\r\n      \r\n  /* Process Locked */\r\n  __HAL_LOCK(hmdios);\r\n  \r\n  /* Get the addr of output register to be written by the MDIOS */\r\n  tmpreg = MDIOS_DOUT_BASE_ADDR + (4 * RegNum);\r\n    \r\n  /* Write to DOUTn register */\r\n  *((uint32_t *)tmpreg) = Data;  \r\n        \r\n    /* Process Unlocked */\r\n  __HAL_UNLOCK(hmdios);\r\n        \r\n  return HAL_OK;   \r\n}\r\n      \r\n/**\r\n  * @brief  Reads an MDIOS input register\r\n  * @param  hmdios: mdios handle\r\n  * @param  RegNum: MDIOS input register number\r\n  * @param  pData: pointer to Data\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t *pData)\r\n{\r\n  uint32_t tmpreg;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_MDIOS_REGISTER(RegNum));\r\n\r\n  /* Process Locked */\r\n  __HAL_LOCK(hmdios);\r\n  \r\n  /* Get the addr of input register to be read by the MDIOS */\r\n  tmpreg = MDIOS_DIN_BASE_ADDR + (4 * RegNum);\r\n\r\n  /* Read DINn register */\r\n  *pData = (uint16_t)(*((uint32_t *)tmpreg));\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hmdios);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Gets Written registers by MDIO master\r\n  * @param  hmdios: mdios handle\r\n  * @retval bit map of written registers addresses\r\n  */\r\nuint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios)\r\n{        \r\n  return hmdios->Instance->WRFR;   \r\n}\r\n\r\n/**\r\n  * @brief  Gets Read registers by MDIO master\r\n  * @param  hmdios: mdios handle\r\n  * @retval bit map of read registers addresses\r\n  */\r\nuint32_t HAL_MDIOS_GetReadRegAddress(MDIOS_HandleTypeDef *hmdios)\r\n{        \r\n  return hmdios->Instance->RDFR;   \r\n}\r\n\r\n/**\r\n  * @brief  Clears Write registers flag\r\n  * @param  hmdios: mdios handle\r\n  * @param  RegNum: registers addresses to be cleared\r\n  * @retval HAL status \r\n  */\r\nHAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_MDIOS_REGISTER(RegNum));\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hmdios);\r\n         \r\n  /* Clear write registers flags */\r\n  hmdios->Instance->CWRFR |= (RegNum);\r\n \r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hmdios);\r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Clears Read register flag\r\n  * @param  hmdios: mdios handle\r\n  * @param  RegNum: registers addresses to be cleared\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_MDIOS_ClearReadRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_MDIOS_REGISTER(RegNum));\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hmdios);\r\n          \r\n  /* Clear read registers flags */\r\n  hmdios->Instance->CRDFR |= (RegNum); \r\n  \r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hmdios);\r\n  \r\n  return HAL_OK;    \r\n}\r\n\r\n/**\r\n  * @brief  Enables Events for MDIOS peripheral \r\n  * @param  hmdios: mdios handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_MDIOS_EnableEvents(MDIOS_HandleTypeDef *hmdios)\r\n{        \r\n  /* Process Locked */\r\n  __HAL_LOCK(hmdios);\r\n  \r\n  /* Enable MDIOS interrupts: Register Write, Register Read and Error ITs */\r\n  __HAL_MDIOS_ENABLE_IT(hmdios, (MDIOS_IT_WRITE | MDIOS_IT_READ | MDIOS_IT_ERROR));\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hmdios);\r\n    \r\n  return HAL_OK;   \r\n}\r\n\r\n/**\r\n  * @brief This function handles MDIOS interrupt request.\r\n  * @param hmdios: MDIOS handle\r\n  * @retval None\r\n  */\r\nvoid HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios)\r\n{\r\n  /* Write Register Interrupt enabled ? */\r\n  if(__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_WRITE) != RESET)\r\n  {\r\n    /* Write register flag */\r\n    if(HAL_MDIOS_GetWrittenRegAddress(hmdios) != RESET)\r\n    {\r\n      /* Write callback function */\r\n      HAL_MDIOS_WriteCpltCallback(hmdios);\r\n      \r\n      /* Clear write register flag */\r\n      HAL_MDIOS_ClearWriteRegAddress(hmdios, MDIOS_ALL_REG_FLAG);\r\n    }\r\n  }\r\n  \r\n  /* Read Register Interrupt enabled ? */\r\n  if(__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_READ) != RESET)\r\n  {\r\n    /* Read register flag */\r\n    if(HAL_MDIOS_GetReadRegAddress(hmdios) != RESET)\r\n    {\r\n      /* Read callback function  */\r\n      HAL_MDIOS_ReadCpltCallback(hmdios);\r\n      \r\n      /* Clear read register flag */\r\n      HAL_MDIOS_ClearReadRegAddress(hmdios, MDIOS_ALL_REG_FLAG);\r\n    }\r\n  }\r\n  \r\n  /* Error Interrupt enabled ? */\r\n  if(__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_ERROR) != RESET)\r\n  {\r\n    /* All Errors Flag */\r\n    if(__HAL_MDIOS_GET_ERROR_FLAG(hmdios, MDIOS_ALL_ERRORS_FLAG) !=RESET)\r\n    {\r\n      /* Error Callback */\r\n      HAL_MDIOS_ErrorCallback(hmdios);\r\n      \r\n      /* Clear errors flag */\r\n      __HAL_MDIOS_CLEAR_ERROR_FLAG(hmdios, MDIOS_ALL_ERRORS_FLAG);\r\n    }\r\n  }\r\n   \r\n  /* check MDIOS WAKEUP exti flag */\r\n  if(__HAL_MDIOS_WAKEUP_EXTI_GET_FLAG() != RESET)\r\n  {\r\n    /* MDIOS WAKEUP interrupt user callback */\r\n    HAL_MDIOS_WakeUpCallback(hmdios);\r\n    \r\n    /* Clear MDIOS WAKEUP Exti pending bit */\r\n    __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG();\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Write Complete Callback\r\n  * @param  hmdios: mdios handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_MDIOS_WriteCpltCallback(MDIOS_HandleTypeDef *hmdios)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hmdios);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_MDIOS_WriteCpltCallback can be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  Read Complete Callback\r\n  * @param  hmdios: mdios handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_MDIOS_ReadCpltCallback(MDIOS_HandleTypeDef *hmdios)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hmdios);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_MDIOS_ReadCpltCallback can be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief Error Callback\r\n  * @param hmdios: mdios handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_MDIOS_ErrorCallback(MDIOS_HandleTypeDef *hmdios)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hmdios);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_MDIOS_ErrorCallback can be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  MDIOS WAKEUP interrupt callback\r\n  * @param hmdios: mdios handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hmdios);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_MDIOS_WakeUpCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup MDIOS_Exported_Functions_Group3 Peripheral Control functions \r\n  *  @brief   MDIOS control functions \r\n  *\r\n@verbatim   \r\n ===============================================================================\r\n                      ##### Peripheral Control functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides a set of functions allowing to control the MDIOS.\r\n     (+) HAL_MDIOS_GetState() API, helpful to check in run-time the state. \r\n     (+) HAL_MDIOS_GetError() API, returns the errors occured during data transfer. \r\n        \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Gets MDIOS error flags \r\n  * @param  hmdios: mdios handle\r\n  * @retval bit map of occured errors \r\n  */\r\nuint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios)\r\n{\r\n  /* return errors flags on status register */\r\n  return hmdios->Instance->SR;\r\n}\r\n\r\n/**\r\n  * @brief  Return the MDIOS HAL state\r\n  * @param  hmdios: mdios handle\r\n  * @retval MDIOS state\r\n  */\r\nHAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios)\r\n{\r\n  /* Return MDIOS state */\r\n  return hmdios->State;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n#endif /* MDIOS */\r\n#endif /* HAL_MDIOS_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_msp_template.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_msp_template.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   HAL MSP module.\r\n  *          This file template is located in the HAL folder and should be copied \r\n  *          to the user folder.\r\n  *         \r\n  @verbatim\r\n ===============================================================================\r\n                     ##### How to use this driver #####\r\n ===============================================================================\r\n    [..]\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup HAL_MSP HAL MSP\r\n  * @brief HAL MSP module.\r\n  * @{\r\n  */\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup HAL_MSP_Private_Functions HAL MSP Private Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the Global MSP.\r\n  * @retval None\r\n  */\r\nvoid HAL_MspInit(void)\r\n{\r\n \r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the Global MSP.  \r\n  * @retval None\r\n  */\r\nvoid HAL_MspDeInit(void)\r\n{\r\n\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the PPP MSP.\r\n  * @retval None\r\n  */\r\nvoid HAL_PPP_MspInit(void)\r\n{\r\n \r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the PPP MSP.  \r\n  * @retval None\r\n  */\r\nvoid HAL_PPP_MspDeInit(void)\r\n{\r\n\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_nand.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_nand.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   NAND HAL module driver.\r\n  *          This file provides a generic firmware to drive NAND memories mounted \r\n  *          as external device.\r\n  *         \r\n  @verbatim\r\n  ==============================================================================\r\n                         ##### How to use this driver #####\r\n  ==============================================================================    \r\n    [..]\r\n      This driver is a generic layered driver which contains a set of APIs used to \r\n      control NAND flash memories. It uses the FMC/FSMC layer functions to interface \r\n      with NAND devices. This driver is used as follows:\r\n    \r\n      (+) NAND flash memory configuration sequence using the function HAL_NAND_Init() \r\n          with control and timing parameters for both common and attribute spaces.\r\n            \r\n      (+) Read NAND flash memory maker and device IDs using the function\r\n          HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef \r\n          structure declared by the function caller. \r\n        \r\n      (+) Access NAND flash memory by read/write operations using the functions\r\n          HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea()\r\n          to read/write page(s)/spare area(s). These functions use specific device \r\n          information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef \r\n          structure. The read/write address information is contained by the Nand_Address_Typedef\r\n          structure passed as parameter.\r\n        \r\n      (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().\r\n        \r\n      (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().\r\n          The erase block address information is contained in the Nand_Address_Typedef \r\n          structure passed as parameter.\r\n    \r\n      (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().\r\n        \r\n      (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/\r\n          HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction\r\n          feature or the function HAL_NAND_GetECC() to get the ECC correction code. \r\n       \r\n      (+) You can monitor the NAND device HAL state by calling the function\r\n          HAL_NAND_GetState()  \r\n\r\n    [..]\r\n      (@) This driver is a set of generic APIs which handle standard NAND flash operations.\r\n          If a NAND flash device contains different operations and/or implementations, \r\n          it should be implemented separately.\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n\r\n#ifdef HAL_NAND_MODULE_ENABLED\r\n\r\n/** @defgroup NAND NAND \r\n  * @brief NAND HAL module driver\r\n  * @{\r\n  */\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private Constants ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/    \r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Exported functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup NAND_Exported_Functions NAND Exported Functions\r\n  * @{\r\n  */\r\n    \r\n/** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions \r\n  * @brief    Initialization and Configuration functions \r\n  *\r\n  @verbatim    \r\n  ==============================================================================\r\n            ##### NAND Initialization and de-initialization functions #####\r\n  ==============================================================================\r\n  [..]  \r\n    This section provides functions allowing to initialize/de-initialize\r\n    the NAND memory\r\n  \r\n@endverbatim\r\n  * @{\r\n  */\r\n    \r\n/**\r\n  * @brief  Perform NAND memory Initialization sequence\r\n  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains\r\n  *                the configuration information for NAND module.\r\n  * @param  ComSpace_Timing: pointer to Common space timing structure\r\n  * @param  AttSpace_Timing: pointer to Attribute space timing structure\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)\r\n{\r\n  /* Check the NAND handle state */\r\n  if(hnand == NULL)\r\n  {\r\n     return HAL_ERROR;\r\n  }\r\n\r\n  if(hnand->State == HAL_NAND_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    hnand->Lock = HAL_UNLOCKED;\r\n    /* Initialize the low level hardware (MSP) */\r\n    HAL_NAND_MspInit(hnand);\r\n  } \r\n\r\n  /* Initialize NAND control Interface */\r\n  FMC_NAND_Init(hnand->Instance, &(hnand->Init));\r\n  \r\n  /* Initialize NAND common space timing Interface */  \r\n  FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);\r\n  \r\n  /* Initialize NAND attribute space timing Interface */  \r\n  FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);\r\n  \r\n  /* Enable the NAND device */\r\n  __FMC_NAND_ENABLE(hnand->Instance);\r\n  \r\n  /* Update the NAND controller state */\r\n  hnand->State = HAL_NAND_STATE_READY;\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Perform NAND memory De-Initialization sequence\r\n  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains\r\n  *                the configuration information for NAND module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)  \r\n{\r\n  /* Initialize the low level hardware (MSP) */\r\n  HAL_NAND_MspDeInit(hnand);\r\n\r\n  /* Configure the NAND registers with their reset values */\r\n  FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);\r\n\r\n  /* Reset the NAND controller state */\r\n  hnand->State = HAL_NAND_STATE_RESET;\r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hnand);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  NAND MSP Init\r\n  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains\r\n  *                the configuration information for NAND module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hnand);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_NAND_MspInit could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  NAND MSP DeInit\r\n  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains\r\n  *                the configuration information for NAND module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hnand);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_NAND_MspDeInit could be implemented in the user file\r\n   */ \r\n}\r\n\r\n\r\n/**\r\n  * @brief  This function handles NAND device interrupt request.\r\n  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains\r\n  *                the configuration information for NAND module.\r\n  * @retval HAL status\r\n*/\r\nvoid HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)\r\n{\r\n  /* Check NAND interrupt Rising edge flag */\r\n  if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))\r\n  {\r\n    /* NAND interrupt callback*/\r\n    HAL_NAND_ITCallback(hnand);\r\n  \r\n    /* Clear NAND interrupt Rising edge pending bit */\r\n    __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_RISING_EDGE);\r\n  }\r\n  \r\n  /* Check NAND interrupt Level flag */\r\n  if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))\r\n  {\r\n    /* NAND interrupt callback*/\r\n    HAL_NAND_ITCallback(hnand);\r\n  \r\n    /* Clear NAND interrupt Level pending bit */\r\n    __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_LEVEL);\r\n  }\r\n\r\n  /* Check NAND interrupt Falling edge flag */\r\n  if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))\r\n  {\r\n    /* NAND interrupt callback*/\r\n    HAL_NAND_ITCallback(hnand);\r\n  \r\n    /* Clear NAND interrupt Falling edge pending bit */\r\n    __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FALLING_EDGE);\r\n  }\r\n  \r\n  /* Check NAND interrupt FIFO empty flag */\r\n  if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))\r\n  {\r\n    /* NAND interrupt callback*/\r\n    HAL_NAND_ITCallback(hnand);\r\n  \r\n    /* Clear NAND interrupt FIFO empty pending bit */\r\n    __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FEMPT);\r\n  }  \r\n\r\n}\r\n\r\n/**\r\n  * @brief  NAND interrupt feature callback\r\n  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains\r\n  *                the configuration information for NAND module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hnand);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_NAND_ITCallback could be implemented in the user file\r\n   */\r\n}\r\n \r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup NAND_Exported_Functions_Group2 Input and Output functions \r\n  * @brief    Input Output and memory control functions \r\n  *\r\n  @verbatim    \r\n  ==============================================================================\r\n                    ##### NAND Input and Output functions #####\r\n  ==============================================================================\r\n  [..]  \r\n    This section provides functions allowing to use and control the NAND \r\n    memory\r\n  \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Read the NAND memory electronic signature\r\n  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains\r\n  *                the configuration information for NAND module.\r\n  * @param  pNAND_ID: NAND ID structure\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)\r\n{\r\n  __IO uint32_t data = 0;\r\n  __IO uint32_t data1 = 0;\r\n  uint32_t deviceAddress = 0;\r\n\r\n  /* Process Locked */\r\n  __HAL_LOCK(hnand);  \r\n  \r\n  /* Check the NAND controller state */\r\n  if(hnand->State == HAL_NAND_STATE_BUSY)\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n  \r\n  /* Identify the device address */\r\n  deviceAddress = NAND_DEVICE;\r\n  \r\n  /* Update the NAND controller state */ \r\n  hnand->State = HAL_NAND_STATE_BUSY;\r\n  \r\n  /* Send Read ID command sequence */ \t\r\n  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA))  = NAND_CMD_READID;\r\n  __DSB();\r\n  *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;\r\n  __DSB();\r\n\r\n  /* Read the electronic signature from NAND flash */\r\n  if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8)\r\n  {\r\n    data = *(__IO uint32_t *)deviceAddress;\r\n\r\n    /* Return the data read */\r\n    pNAND_ID->Maker_Id   = ADDR_1ST_CYCLE(data);\r\n    pNAND_ID->Device_Id  = ADDR_2ND_CYCLE(data);\r\n    pNAND_ID->Third_Id   = ADDR_3RD_CYCLE(data);\r\n    pNAND_ID->Fourth_Id  = ADDR_4TH_CYCLE(data);\r\n  }\r\n  else\r\n  {\r\n    data = *(__IO uint32_t *)deviceAddress;\r\n    data1 = *((__IO uint32_t *)deviceAddress + 4);\r\n    \r\n    /* Return the data read */\r\n    pNAND_ID->Maker_Id   = ADDR_1ST_CYCLE(data);\r\n    pNAND_ID->Device_Id  = ADDR_3RD_CYCLE(data);\r\n    pNAND_ID->Third_Id   = ADDR_1ST_CYCLE(data1);\r\n    pNAND_ID->Fourth_Id  = ADDR_3RD_CYCLE(data1);\r\n  }\r\n\r\n  \r\n  /* Update the NAND controller state */ \r\n  hnand->State = HAL_NAND_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hnand);   \r\n   \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  NAND memory reset\r\n  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains\r\n  *                the configuration information for NAND module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)\r\n{\r\n  uint32_t deviceAddress = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hnand);\r\n    \r\n  /* Check the NAND controller state */\r\n  if(hnand->State == HAL_NAND_STATE_BUSY)\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n\r\n  /* Identify the device address */  \r\n  deviceAddress = NAND_DEVICE;\r\n  \r\n  /* Update the NAND controller state */   \r\n  hnand->State = HAL_NAND_STATE_BUSY; \r\n  \r\n  /* Send NAND reset command */  \r\n  *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0xFF;\r\n    \r\n  \r\n  /* Update the NAND controller state */   \r\n  hnand->State = HAL_NAND_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hnand);    \r\n  \r\n  return HAL_OK;\r\n  \r\n}\r\n  \r\n/**\r\n  * @brief  Read Page(s) from NAND memory block (8-bits addressing)\r\n  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains\r\n  *                the configuration information for NAND module.\r\n  * @param  pAddress : pointer to NAND address structure\r\n  * @param  pBuffer : pointer to destination read buffer\r\n  * @param  NumPageToRead : number of pages to read from block \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)\r\n{\r\n  __IO uint32_t index  = 0;\r\n  uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hnand); \r\n  \r\n  /* Check the NAND controller state */\r\n  if(hnand->State == HAL_NAND_STATE_BUSY)\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  \r\n  /* Identify the device address */\r\n  deviceAddress = NAND_DEVICE;\r\n\r\n  /* Update the NAND controller state */ \r\n  hnand->State = HAL_NAND_STATE_BUSY;\r\n  \r\n  /* NAND raw address calculation */\r\n  nandAddress = ARRAY_ADDRESS(pAddress, hnand);\r\n  \r\n  /* Page(s) read loop */  \r\n  while((NumPageToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize))))\r\n  {\t   \r\n    /* update the buffer size */\r\n    size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesRead);\r\n    \r\n    /* Send read page command sequence */\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;  \r\n    __DSB();\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;\r\n    __DSB();\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);\r\n    __DSB();\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);\r\n    __DSB();\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);\r\n    __DSB();\r\n  \r\n    /* for 512 and 1 GB devices, 4th cycle is required */    \r\n    if(hnand->Info.BlockNbr >= 1024)\r\n    {\r\n      *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);\r\n      __DSB();\r\n    }\r\n  \r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA))  = NAND_CMD_AREA_TRUE1;\r\n    __DSB();\r\n    \r\n    if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8)\r\n    {\r\n      /* Get Data into Buffer */    \r\n      for(; index < size; index++)\r\n      {\r\n        *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* Get Data into Buffer */    \r\n      for(; index < size; index++)\r\n      {\r\n        *(uint16_t *)pBuffer++ = *(uint16_t *)deviceAddress;\r\n      }\r\n    }\r\n    \r\n    /* Increment read pages number */\r\n    numPagesRead++;\r\n    \r\n    /* Decrement pages to read */\r\n    NumPageToRead--;\r\n    \r\n    /* Increment the NAND address */\r\n    nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8));\r\n  }\r\n  \r\n  /* Update the NAND controller state */ \r\n  hnand->State = HAL_NAND_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hnand);  \r\n    \r\n  return HAL_OK;\r\n\r\n}\r\n\r\n/**\r\n  * @brief  Read Page(s) from NAND memory block (16-bits addressing)\r\n  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains\r\n  *                the configuration information for NAND module.\r\n  * @param  pAddress : pointer to NAND address structure\r\n  * @param  pBuffer : pointer to destination read buffer\r\n  * @param  NumPageToRead : number of pages to read from block \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)\r\n{   \r\n  __IO uint32_t index  = 0;\r\n  uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hnand); \r\n  \r\n  /* Check the NAND controller state */\r\n  if(hnand->State == HAL_NAND_STATE_BUSY)\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  \r\n  /* Identify the device address */\r\n  deviceAddress = NAND_DEVICE;\r\n\r\n  /* Update the NAND controller state */ \r\n  hnand->State = HAL_NAND_STATE_BUSY;\r\n  \r\n  /* NAND raw address calculation */\r\n  nandAddress = ARRAY_ADDRESS(pAddress, hnand);\r\n  \r\n  /* Page(s) read loop */  \r\n  while((NumPageToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize))))\r\n  {\t   \r\n    /* update the buffer size */\r\n    size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesRead);\r\n    \r\n    /* Send read page command sequence */\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;  \r\n    __DSB();\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;\r\n    __DSB();\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);\r\n    __DSB();\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);\r\n    __DSB();\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);\r\n    __DSB();\r\n  \r\n    /* for 512 and 1 GB devices, 4th cycle is required */    \r\n    if(hnand->Info.BlockNbr >= 1024)\r\n    {\r\n      *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);\r\n      __DSB();\r\n    }\r\n  \r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA))  = NAND_CMD_AREA_TRUE1;\r\n    __DSB();\r\n      \r\n    /* Get Data into Buffer */    \r\n    for(; index < size; index++)\r\n    {\r\n      *(uint16_t *)pBuffer++ = *(uint16_t *)deviceAddress;\r\n    }\r\n    \r\n    /* Increment read pages number */\r\n    numPagesRead++;\r\n    \r\n    /* Decrement pages to read */\r\n    NumPageToRead--;\r\n    \r\n    /* Increment the NAND address */\r\n    nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8));\r\n  }\r\n  \r\n  /* Update the NAND controller state */ \r\n  hnand->State = HAL_NAND_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hnand);  \r\n    \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Write Page(s) to NAND memory block (8-bits addressing)\r\n  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains\r\n  *                the configuration information for NAND module.\r\n  * @param  pAddress : pointer to NAND address structure\r\n  * @param  pBuffer : pointer to source buffer to write  \r\n  * @param  NumPageToWrite  : number of pages to write to block \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)\r\n{\r\n  __IO uint32_t index = 0;\r\n  uint32_t tickstart = 0;\r\n  uint32_t deviceAddress = 0, size = 0, numPagesWritten = 0, nandAddress = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hnand);  \r\n\r\n  /* Check the NAND controller state */\r\n  if(hnand->State == HAL_NAND_STATE_BUSY)\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  \r\n  /* Identify the device address */\r\n  deviceAddress = NAND_DEVICE;\r\n  \r\n  /* Update the NAND controller state */ \r\n  hnand->State = HAL_NAND_STATE_BUSY;\r\n  \r\n  /* NAND raw address calculation */\r\n  nandAddress = ARRAY_ADDRESS(pAddress, hnand);\r\n  \r\n  /* Page(s) write loop */\r\n  while((NumPageToWrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize))))\r\n  {  \r\n    /* update the buffer size */\r\n    size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesWritten);\r\n \r\n    /* Send write page command sequence */\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;\r\n    __DSB();\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;\r\n    __DSB();\r\n\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;\r\n    __DSB();\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);\r\n    __DSB();\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);\r\n    __DSB();\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);\r\n    __DSB();\r\n    \r\n    /* for 512 and 1 GB devices, 4th cycle is required */     \r\n    if(hnand->Info.BlockNbr >= 1024)\r\n    {\r\n      *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);\r\n      __DSB();\r\n    }\r\n \r\n    if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8)\r\n    {\r\n      /* Write data to memory */\r\n      for(; index < size; index++)\r\n      {\r\n        *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;\r\n        __DSB();\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* Write data to memory */\r\n      for(; index < size; index++)\r\n      {\r\n        *(__IO uint16_t *)deviceAddress = *(uint16_t *)pBuffer++;\r\n        __DSB();\r\n      }\r\n    }\r\n   \r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;\r\n    __DSB();\r\n    \r\n    /* Read status until NAND is ready */\r\n    while(HAL_NAND_Read_Status(hnand) != NAND_READY)\r\n    {\r\n      /* Get tick */\r\n      tickstart = HAL_GetTick();\r\n    \r\n      if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)\r\n      {\r\n        return HAL_TIMEOUT; \r\n      } \r\n    }    \r\n \r\n    /* Increment written pages number */\r\n    numPagesWritten++;\r\n    \r\n    /* Decrement pages to write */\r\n    NumPageToWrite--;\r\n    \r\n    /* Increment the NAND address */\r\n    nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8));\r\n  }\r\n  \r\n  /* Update the NAND controller state */ \r\n  hnand->State = HAL_NAND_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hnand);      \r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Write Page(s) to NAND memory block (16-bits addressing)\r\n  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains\r\n  *                the configuration information for NAND module.\r\n  * @param  pAddress : pointer to NAND address structure\r\n  * @param  pBuffer : pointer to source buffer to write  \r\n  * @param  NumPageToWrite  : number of pages to write to block \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)\r\n{\r\n  __IO uint32_t index = 0;\r\n  uint32_t tickstart = 0;\r\n  uint32_t deviceAddress = 0, size = 0, numPagesWritten = 0, nandAddress = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hnand);  \r\n\r\n  /* Check the NAND controller state */\r\n  if(hnand->State == HAL_NAND_STATE_BUSY)\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  \r\n  /* Identify the device address */\r\n  deviceAddress = NAND_DEVICE;\r\n  \r\n  /* Update the NAND controller state */ \r\n  hnand->State = HAL_NAND_STATE_BUSY;\r\n  \r\n  /* NAND raw address calculation */\r\n  nandAddress = ARRAY_ADDRESS(pAddress, hnand);\r\n  \r\n  /* Page(s) write loop */\r\n  while((NumPageToWrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize))))\r\n  {\r\n    /* update the buffer size */\r\n    size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesWritten);\r\n \r\n    /* Send write page command sequence */\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;\r\n    __DSB();\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;\r\n    __DSB();\r\n\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;\r\n    __DSB();\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);\r\n    __DSB();\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);\r\n    __DSB();\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);\r\n    __DSB();\r\n    \r\n    /* for 512 and 1 GB devices, 4th cycle is required */     \r\n    if(hnand->Info.BlockNbr >= 1024)\r\n    {\r\n      *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);\r\n      __DSB();\r\n    }\r\n  \r\n    /* Write data to memory */\r\n    for(; index < size; index++)\r\n    {\r\n      *(__IO uint16_t *)deviceAddress = *(uint16_t *)pBuffer++;\r\n      __DSB();\r\n    }\r\n   \r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;\r\n    __DSB();\r\n    \r\n    /* Read status until NAND is ready */\r\n    while(HAL_NAND_Read_Status(hnand) != NAND_READY)\r\n    {\r\n      /* Get tick */\r\n      tickstart = HAL_GetTick();\r\n    \r\n      if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)\r\n      {\r\n        return HAL_TIMEOUT; \r\n      } \r\n    }   \r\n \r\n    /* Increment written pages number */\r\n    numPagesWritten++;\r\n    \r\n    /* Decrement pages to write */\r\n    NumPageToWrite--;\r\n    \r\n    /* Increment the NAND address */\r\n    nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8));\r\n  }\r\n  \r\n  /* Update the NAND controller state */ \r\n  hnand->State = HAL_NAND_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hnand);      \r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Read Spare area(s) from NAND memory (8-bits addressing)\r\n  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains\r\n  *                the configuration information for NAND module.\r\n  * @param  pAddress : pointer to NAND address structure\r\n  * @param  pBuffer: pointer to source buffer to write  \r\n  * @param  NumSpareAreaToRead: Number of spare area to read  \r\n  * @retval HAL status\r\n*/\r\nHAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)\r\n{\r\n  __IO uint32_t index = 0; \r\n  uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hnand);  \r\n  \r\n  /* Check the NAND controller state */\r\n  if(hnand->State == HAL_NAND_STATE_BUSY)\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  \r\n  /* Identify the device address */\r\n  deviceAddress = NAND_DEVICE;\r\n  \r\n  /* Update the NAND controller state */\r\n  hnand->State = HAL_NAND_STATE_BUSY;\r\n  \r\n  /* NAND raw address calculation */\r\n  nandAddress = ARRAY_ADDRESS(pAddress, hnand);    \r\n  \r\n  /* Spare area(s) read loop */ \r\n  while((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize))))\r\n  {\r\n    /* update the buffer size */\r\n    size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaRead);   \r\n\r\n    /* Send read spare area command sequence */     \r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;\r\n    __DSB();\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;\r\n    __DSB();\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);\r\n    __DSB();\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);\r\n    __DSB();\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);\r\n    __DSB();\r\n  \r\n    /* for 512 and 1 GB devices, 4th cycle is required */    \r\n    if(hnand->Info.BlockNbr >= 1024)\r\n    {\r\n      *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);\r\n      __DSB();\r\n    } \r\n\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;\r\n    __DSB();\r\n    \r\n    /* Get Data into Buffer */\r\n    for(; index < size; index++)\r\n    {\r\n      *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;\r\n    }\r\n    \r\n    /* Increment read spare areas number */\r\n    numSpareAreaRead++;\r\n    \r\n    /* Decrement spare areas to read */\r\n    NumSpareAreaToRead--;\r\n    \r\n    /* Increment the NAND address */\r\n    nandAddress = (uint32_t)(nandAddress + (hnand->Info.SpareAreaSize));\r\n  }\r\n  \r\n  /* Update the NAND controller state */\r\n  hnand->State = HAL_NAND_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hnand);     \r\n\r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Read Spare area(s) from NAND memory (16-bits addressing)\r\n  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains\r\n  *                the configuration information for NAND module.\r\n  * @param  pAddress : pointer to NAND address structure\r\n  * @param  pBuffer: pointer to source buffer to write  \r\n  * @param  NumSpareAreaToRead: Number of spare area to read  \r\n  * @retval HAL status\r\n*/\r\nHAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)\r\n{\r\n  __IO uint32_t index = 0; \r\n  uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hnand);  \r\n  \r\n  /* Check the NAND controller state */\r\n  if(hnand->State == HAL_NAND_STATE_BUSY)\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  \r\n  /* Identify the device address */\r\n  deviceAddress = NAND_DEVICE;\r\n  \r\n  /* Update the NAND controller state */\r\n  hnand->State = HAL_NAND_STATE_BUSY;\r\n  \r\n  /* NAND raw address calculation */\r\n  nandAddress = ARRAY_ADDRESS(pAddress, hnand);    \r\n  \r\n  /* Spare area(s) read loop */ \r\n  while((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize))))\r\n  {\r\n    /* update the buffer size */\r\n    size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaRead);   \r\n\r\n    /* Send read spare area command sequence */     \r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;\r\n    __DSB();\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;\r\n    __DSB();\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);\r\n    __DSB();\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);\r\n    __DSB();\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);\r\n    __DSB();\r\n  \r\n    /* for 512 and 1 GB devices, 4th cycle is required */    \r\n    if(hnand->Info.BlockNbr >= 1024)\r\n    {\r\n      *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);\r\n      __DSB();\r\n    } \r\n\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;\r\n    __DSB();\r\n    \r\n    /* Get Data into Buffer */\r\n    for(; index < size; index++)\r\n    {\r\n      *(uint16_t *)pBuffer++ = *(uint16_t *)deviceAddress;\r\n    }\r\n    \r\n    /* Increment read spare areas number */\r\n    numSpareAreaRead++;\r\n    \r\n    /* Decrement spare areas to read */\r\n    NumSpareAreaToRead--;\r\n    \r\n    /* Increment the NAND address */\r\n    nandAddress = (uint32_t)(nandAddress + (hnand->Info.SpareAreaSize));\r\n  }\r\n  \r\n  /* Update the NAND controller state */\r\n  hnand->State = HAL_NAND_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hnand);     \r\n\r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Write Spare area(s) to NAND memory (8-bits addressing)\r\n  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains\r\n  *                the configuration information for NAND module.\r\n  * @param  pAddress : pointer to NAND address structure\r\n  * @param  pBuffer : pointer to source buffer to write  \r\n  * @param  NumSpareAreaTowrite  : number of spare areas to write to block\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)\r\n{\r\n  __IO uint32_t index = 0;\r\n  uint32_t tickstart = 0;\r\n  uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0;\r\n\r\n  /* Process Locked */\r\n  __HAL_LOCK(hnand); \r\n  \r\n  /* Check the NAND controller state */\r\n  if(hnand->State == HAL_NAND_STATE_BUSY)\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  \r\n  /* Identify the device address */\r\n  deviceAddress = NAND_DEVICE;\r\n  \r\n  /* Update the FMC_NAND controller state */\r\n  hnand->State = HAL_NAND_STATE_BUSY;  \r\n  \r\n  /* NAND raw address calculation */\r\n  nandAddress = ARRAY_ADDRESS(pAddress, hnand);  \r\n  \r\n  /* Spare area(s) write loop */\r\n  while((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize))))\r\n  {\r\n    /* update the buffer size */\r\n    size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaWritten);\r\n\r\n    /* Send write Spare area command sequence */\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;\r\n    __DSB();\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;\r\n    __DSB();\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;\r\n    __DSB();\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);\r\n    __DSB();\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);\r\n    __DSB();\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); \r\n    __DSB();\r\n    /* for 512 and 1 GB devices, 4th cycle is required */     \r\n    if(hnand->Info.BlockNbr >= 1024)\r\n    {\r\n      *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);\r\n      __DSB();\r\n    }\r\n  \r\n    /* Write data to memory */\r\n    for(; index < size; index++)\r\n    {\r\n      *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;\r\n      __DSB();\r\n    }\r\n   \r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;\r\n    __DSB();\r\n   \r\n    /* Read status until NAND is ready */\r\n    while(HAL_NAND_Read_Status(hnand) != NAND_READY)\r\n    {\r\n      /* Get tick */\r\n      tickstart = HAL_GetTick();\r\n    \r\n      if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)\r\n      {\r\n        return HAL_TIMEOUT; \r\n      }\r\n    }\r\n\r\n    /* Increment written spare areas number */\r\n    numSpareAreaWritten++;\r\n    \r\n    /* Decrement spare areas to write */\r\n    NumSpareAreaTowrite--;\r\n    \r\n    /* Increment the NAND address */\r\n    nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize));\r\n  }\r\n\r\n  /* Update the NAND controller state */\r\n  hnand->State = HAL_NAND_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hnand);\r\n\r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Write Spare area(s) to NAND memory (16-bits addressing)\r\n  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains\r\n  *                the configuration information for NAND module.\r\n  * @param  pAddress : pointer to NAND address structure\r\n  * @param  pBuffer : pointer to source buffer to write  \r\n  * @param  NumSpareAreaTowrite  : number of spare areas to write to block\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)\r\n{\r\n  __IO uint32_t index = 0;\r\n  uint32_t tickstart = 0;\r\n  uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0;\r\n\r\n  /* Process Locked */\r\n  __HAL_LOCK(hnand); \r\n  \r\n  /* Check the NAND controller state */\r\n  if(hnand->State == HAL_NAND_STATE_BUSY)\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  \r\n  /* Identify the device address */\r\n  deviceAddress = NAND_DEVICE;\r\n  \r\n  /* Update the FMC_NAND controller state */\r\n  hnand->State = HAL_NAND_STATE_BUSY;  \r\n  \r\n  /* NAND raw address calculation */\r\n  nandAddress = ARRAY_ADDRESS(pAddress, hnand);  \r\n  \r\n  /* Spare area(s) write loop */\r\n  while((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize))))\r\n  {\r\n    /* update the buffer size */\r\n    size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaWritten);\r\n\r\n    /* Send write Spare area command sequence */\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;\r\n    __DSB();\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;\r\n    __DSB();\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;\r\n    __DSB();\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);\r\n    __DSB();\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);\r\n    __DSB();\r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); \r\n    __DSB();\r\n    /* for 512 and 1 GB devices, 4th cycle is required */     \r\n    if(hnand->Info.BlockNbr >= 1024)\r\n    {\r\n      *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);\r\n      __DSB();\r\n    }\r\n  \r\n    /* Write data to memory */\r\n    for(; index < size; index++)\r\n    {\r\n      *(__IO uint16_t *)deviceAddress = *(uint16_t *)pBuffer++;\r\n      __DSB();\r\n    }\r\n   \r\n    *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;\r\n    __DSB();\r\n   \r\n    /* Read status until NAND is ready */\r\n    while(HAL_NAND_Read_Status(hnand) != NAND_READY)\r\n    {\r\n      /* Get tick */\r\n      tickstart = HAL_GetTick();\r\n    \r\n      if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)\r\n      {\r\n        return HAL_TIMEOUT; \r\n      }\r\n    }\r\n\r\n    /* Increment written spare areas number */\r\n    numSpareAreaWritten++;\r\n    \r\n    /* Decrement spare areas to write */\r\n    NumSpareAreaTowrite--;\r\n    \r\n    /* Increment the NAND address */\r\n    nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize));\r\n  }\r\n\r\n  /* Update the NAND controller state */\r\n  hnand->State = HAL_NAND_STATE_READY;\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hnand);\r\n\r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  NAND memory Block erase \r\n  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains\r\n  *                the configuration information for NAND module.\r\n  * @param  pAddress : pointer to NAND address structure\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)\r\n{\r\n  uint32_t DeviceAddress = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hnand);\r\n  \r\n  /* Check the NAND controller state */\r\n  if(hnand->State == HAL_NAND_STATE_BUSY)\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  \r\n  /* Identify the device address */\r\n  DeviceAddress = NAND_DEVICE;\r\n  \r\n  /* Update the NAND controller state */\r\n  hnand->State = HAL_NAND_STATE_BUSY;  \r\n  \r\n  /* Send Erase block command sequence */\r\n  *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE0;\r\n  __DSB();\r\n  *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));\r\n    __DSB();\r\n  *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));\r\n    __DSB();\r\n  *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));\r\n  __DSB();\r\n  \r\n  /* for 512 and 1 GB devices, 4th cycle is required */     \r\n  if(hnand->Info.BlockNbr >= 1024)\r\n  {\r\n    *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(ARRAY_ADDRESS(pAddress, hnand));\r\n    __DSB();\r\n  }  \r\n\t\t\r\n  *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE1; \r\n  __DSB();\r\n  \r\n  /* Update the NAND controller state */\r\n  hnand->State = HAL_NAND_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hnand);    \r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  NAND memory read status \r\n  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains\r\n  *                the configuration information for NAND module.\r\n  * @retval NAND status\r\n  */\r\nuint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)\r\n{\r\n  uint32_t data = 0;\r\n  uint32_t DeviceAddress = 0;\r\n  \r\n  /* Identify the device address */\r\n   DeviceAddress = NAND_DEVICE;\r\n\r\n  /* Send Read status operation command */\r\n  *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_STATUS;\r\n  \r\n  /* Read status register data */\r\n  data = *(__IO uint8_t *)DeviceAddress;\r\n\r\n  /* Return the status */\r\n  if((data & NAND_ERROR) == NAND_ERROR)\r\n  {\r\n    return NAND_ERROR;\r\n  } \r\n  else if((data & NAND_READY) == NAND_READY)\r\n  {\r\n    return NAND_READY;\r\n  }\r\n\r\n  return NAND_BUSY; \r\n}\r\n\r\n/**\r\n  * @brief  Increment the NAND memory address\r\n  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains\r\n  *                the configuration information for NAND module.\r\n  * @param pAddress: pointer to NAND address structure\r\n  * @retval The new status of the increment address operation. It can be:\r\n  *           - NAND_VALID_ADDRESS: When the new address is valid address\r\n  *           - NAND_INVALID_ADDRESS: When the new address is invalid address\r\n  */\r\nuint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)\r\n{\r\n  uint32_t status = NAND_VALID_ADDRESS;\r\n \r\n  /* Increment page address */\r\n  pAddress->Page++;\r\n\r\n  /* Check NAND address is valid */\r\n  if(pAddress->Page == hnand->Info.BlockSize)\r\n  {\r\n    pAddress->Page = 0;\r\n    pAddress->Block++;\r\n    \r\n    if(pAddress->Block == hnand->Info.ZoneSize)\r\n    {\r\n      pAddress->Block = 0;\r\n      pAddress->Zone++;\r\n\r\n      if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr))\r\n      {\r\n        status = NAND_INVALID_ADDRESS;\r\n      }\r\n    }\r\n  } \r\n  \r\n  return (status);\r\n}\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions \r\n *  @brief   management functions \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                         ##### NAND Control functions #####\r\n  ==============================================================================  \r\n  [..]\r\n    This subsection provides a set of functions allowing to control dynamically\r\n    the NAND interface.\r\n\r\n@endverbatim\r\n  * @{\r\n  */ \r\n\r\n    \r\n/**\r\n  * @brief  Enables dynamically NAND ECC feature.\r\n  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains\r\n  *                the configuration information for NAND module.\r\n  * @retval HAL status\r\n  */    \r\nHAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)\r\n{\r\n  /* Check the NAND controller state */\r\n  if(hnand->State == HAL_NAND_STATE_BUSY)\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n\r\n  /* Update the NAND state */\r\n  hnand->State = HAL_NAND_STATE_BUSY;\r\n   \r\n  /* Enable ECC feature */\r\n  FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);\r\n  \r\n  /* Update the NAND state */\r\n  hnand->State = HAL_NAND_STATE_READY;\r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Disables dynamically FMC_NAND ECC feature.\r\n  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains\r\n  *                the configuration information for NAND module.\r\n  * @retval HAL status\r\n  */  \r\nHAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)  \r\n{\r\n  /* Check the NAND controller state */\r\n  if(hnand->State == HAL_NAND_STATE_BUSY)\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n\r\n  /* Update the NAND state */\r\n  hnand->State = HAL_NAND_STATE_BUSY;\r\n    \r\n  /* Disable ECC feature */\r\n  FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);\r\n  \r\n  /* Update the NAND state */\r\n  hnand->State = HAL_NAND_STATE_READY;\r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Disables dynamically NAND ECC feature.\r\n  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains\r\n  *                the configuration information for NAND module.\r\n  * @param  ECCval: pointer to ECC value \r\n  * @param  Timeout: maximum timeout to wait    \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  \r\n  /* Check the NAND controller state */\r\n  if(hnand->State == HAL_NAND_STATE_BUSY)\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  \r\n  /* Update the NAND state */\r\n  hnand->State = HAL_NAND_STATE_BUSY;  \r\n   \r\n  /* Get NAND ECC value */\r\n  status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);\r\n  \r\n  /* Update the NAND state */\r\n  hnand->State = HAL_NAND_STATE_READY;\r\n\r\n  return status;  \r\n}\r\n                      \r\n/**\r\n  * @}\r\n  */\r\n  \r\n    \r\n/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions  \r\n *  @brief   Peripheral State functions \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                         ##### NAND State functions #####\r\n  ==============================================================================  \r\n  [..]\r\n    This subsection permits to get in run-time the status of the NAND controller \r\n    and the data flow.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @brief  return the NAND state\r\n  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains\r\n  *                the configuration information for NAND module.\r\n  * @retval HAL state\r\n  */\r\nHAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)\r\n{\r\n  return hnand->State;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_NAND_MODULE_ENABLED  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_nor.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_nor.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   NOR HAL module driver.\r\n  *          This file provides a generic firmware to drive NOR memories mounted \r\n  *          as external device.\r\n  *         \r\n  @verbatim\r\n  ==============================================================================\r\n                     ##### How to use this driver #####\r\n  ==============================================================================       \r\n    [..]\r\n      This driver is a generic layered driver which contains a set of APIs used to \r\n      control NOR flash memories. It uses the FMC layer functions to interface \r\n      with NOR devices. This driver is used as follows:\r\n    \r\n      (+) NOR flash memory configuration sequence using the function HAL_NOR_Init() \r\n          with control and timing parameters for both normal and extended mode.\r\n            \r\n      (+) Read NOR flash memory manufacturer code and device IDs using the function\r\n          HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef \r\n          structure declared by the function caller. \r\n        \r\n      (+) Access NOR flash memory by read/write data unit operations using the functions\r\n          HAL_NOR_Read(), HAL_NOR_Program().\r\n        \r\n      (+) Perform NOR flash erase block/chip operations using the functions \r\n          HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().\r\n        \r\n      (+) Read the NOR flash CFI (common flash interface) IDs using the function\r\n          HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef\r\n          structure declared by the function caller.\r\n        \r\n      (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/\r\n          HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation  \r\n       \r\n      (+) You can monitor the NOR device HAL state by calling the function\r\n          HAL_NOR_GetState() \r\n    [..]\r\n     (@) This driver is a set of generic APIs which handle standard NOR flash operations.\r\n         If a NOR flash device contains different operations and/or implementations, \r\n         it should be implemented separately.\r\n\r\n     *** NOR HAL driver macros list ***\r\n     ============================================= \r\n     [..]\r\n       Below the list of most used macros in NOR HAL driver.\r\n       \r\n      (+) NOR_WRITE : NOR memory write data to specified address\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup NOR NOR\r\n  * @brief NOR driver modules\r\n  * @{\r\n  */\r\n#ifdef HAL_NOR_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n      \r\n/** @defgroup NOR_Private_Defines NOR Private Defines\r\n  * @{\r\n  */\r\n\r\n/* Constants to define address to set to write a command */\r\n#define NOR_CMD_ADDRESS_FIRST                 (uint16_t)0x0555\r\n#define NOR_CMD_ADDRESS_FIRST_CFI             (uint16_t)0x0055\r\n#define NOR_CMD_ADDRESS_SECOND                (uint16_t)0x02AA\r\n#define NOR_CMD_ADDRESS_THIRD                 (uint16_t)0x0555\r\n#define NOR_CMD_ADDRESS_FOURTH                (uint16_t)0x0555\r\n#define NOR_CMD_ADDRESS_FIFTH                 (uint16_t)0x02AA\r\n#define NOR_CMD_ADDRESS_SIXTH                 (uint16_t)0x0555\r\n\r\n/* Constants to define data to program a command */\r\n#define NOR_CMD_DATA_READ_RESET               (uint16_t)0x00F0\r\n#define NOR_CMD_DATA_FIRST                    (uint16_t)0x00AA\r\n#define NOR_CMD_DATA_SECOND                   (uint16_t)0x0055\r\n#define NOR_CMD_DATA_AUTO_SELECT              (uint16_t)0x0090\r\n#define NOR_CMD_DATA_PROGRAM                  (uint16_t)0x00A0\r\n#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD   (uint16_t)0x0080\r\n#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH  (uint16_t)0x00AA\r\n#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH   (uint16_t)0x0055\r\n#define NOR_CMD_DATA_CHIP_ERASE               (uint16_t)0x0010\r\n#define NOR_CMD_DATA_CFI                      (uint16_t)0x0098\r\n\r\n#define NOR_CMD_DATA_BUFFER_AND_PROG          (uint8_t)0x25\r\n#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM  (uint8_t)0x29\r\n#define NOR_CMD_DATA_BLOCK_ERASE              (uint8_t)0x30\r\n\r\n/* Mask on NOR STATUS REGISTER */\r\n#define NOR_MASK_STATUS_DQ5                   (uint16_t)0x0020\r\n#define NOR_MASK_STATUS_DQ6                   (uint16_t)0x0040\r\n\r\n/**\r\n  * @}\r\n  */\r\n      \r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @defgroup NOR_Private_Variables NOR Private Variables\r\n  * @{\r\n  */\r\n\r\nstatic uint32_t uwNORMemoryDataWidth  = NOR_MEMORY_8B;\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup NOR_Exported_Functions NOR Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions \r\n  * @brief    Initialization and Configuration functions \r\n  *\r\n  @verbatim    \r\n  ==============================================================================\r\n           ##### NOR Initialization and de_initialization functions #####\r\n  ==============================================================================\r\n  [..]  \r\n    This section provides functions allowing to initialize/de-initialize\r\n    the NOR memory\r\n  \r\n@endverbatim\r\n  * @{\r\n  */\r\n    \r\n/**\r\n  * @brief  Perform the NOR memory Initialization sequence\r\n  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains\r\n  *                the configuration information for NOR module.\r\n  * @param  Timing: pointer to NOR control timing structure \r\n  * @param  ExtTiming: pointer to NOR extended mode timing structure    \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)\r\n{\r\n  /* Check the NOR handle parameter */\r\n  if(hnor == NULL)\r\n  {\r\n     return HAL_ERROR;\r\n  }\r\n  \r\n  if(hnor->State == HAL_NOR_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    hnor->Lock = HAL_UNLOCKED;\r\n    /* Initialize the low level hardware (MSP) */\r\n    HAL_NOR_MspInit(hnor);\r\n  }\r\n  \r\n  /* Initialize NOR control Interface */\r\n  FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));\r\n\r\n  /* Initialize NOR timing Interface */\r\n  FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); \r\n\r\n  /* Initialize NOR extended mode timing Interface */\r\n  FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);\r\n\r\n  /* Enable the NORSRAM device */\r\n  __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);\r\n\r\n  /* Initialize NOR Memory Data Width*/\r\n  if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8)\r\n  {\r\n    uwNORMemoryDataWidth = NOR_MEMORY_8B;\r\n  }\r\n  else\r\n  {\r\n    uwNORMemoryDataWidth = NOR_MEMORY_16B;\r\n  }\r\n\r\n  /* Check the NOR controller state */\r\n  hnor->State = HAL_NOR_STATE_READY; \r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Perform NOR memory De-Initialization sequence\r\n  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains\r\n  *                the configuration information for NOR module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)  \r\n{\r\n  /* De-Initialize the low level hardware (MSP) */\r\n  HAL_NOR_MspDeInit(hnor);\r\n \r\n  /* Configure the NOR registers with their reset values */\r\n  FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);\r\n  \r\n  /* Update the NOR controller state */\r\n  hnor->State = HAL_NOR_STATE_RESET;\r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hnor);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  NOR MSP Init\r\n  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains\r\n  *                the configuration information for NOR module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hnor);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_NOR_MspInit could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  NOR MSP DeInit\r\n  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains\r\n  *                the configuration information for NOR module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hnor);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_NOR_MspDeInit could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  NOR MSP Wait for Ready/Busy signal\r\n  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains\r\n  *                the configuration information for NOR module.\r\n  * @param  Timeout: Maximum timeout value\r\n  * @retval None\r\n  */\r\n__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hnor);\r\n  UNUSED(Timeout);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_NOR_MspWait could be implemented in the user file\r\n   */ \r\n}\r\n  \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions \r\n  * @brief    Input Output and memory control functions \r\n  *\r\n  @verbatim    \r\n  ==============================================================================\r\n                ##### NOR Input and Output functions #####\r\n  ==============================================================================\r\n  [..]  \r\n    This section provides functions allowing to use and control the NOR memory\r\n  \r\n@endverbatim\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @brief  Read NOR flash IDs\r\n  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains\r\n  *                the configuration information for NOR module.\r\n  * @param  pNOR_ID : pointer to NOR ID structure\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)\r\n{\r\n  uint32_t deviceaddress = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hnor);\r\n  \r\n  /* Check the NOR controller state */\r\n  if(hnor->State == HAL_NOR_STATE_BUSY)\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  \r\n  /* Select the NOR device address */\r\n  if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS1;\r\n  }\r\n  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS2;\r\n  }\r\n  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS3;\r\n  }\r\n  else /* FMC_NORSRAM_BANK4 */\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS4;\r\n  }  \r\n    \r\n  /* Update the NOR controller state */\r\n  hnor->State = HAL_NOR_STATE_BUSY;\r\n  \r\n  /* Send read ID command */\r\n  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);\r\n  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);\r\n  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);\r\n\r\n  /* Read the NOR IDs */\r\n  pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);\r\n  pNOR_ID->Device_Code1      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);\r\n  pNOR_ID->Device_Code2      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);\r\n  pNOR_ID->Device_Code3      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);\r\n  \r\n  /* Check the NOR controller state */\r\n  hnor->State = HAL_NOR_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hnor);   \r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the NOR memory to Read mode.\r\n  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains\r\n  *                the configuration information for NOR module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)\r\n{\r\n  uint32_t deviceaddress = 0;  \r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hnor);\r\n  \r\n  /* Check the NOR controller state */\r\n  if(hnor->State == HAL_NOR_STATE_BUSY)\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  \r\n  /* Select the NOR device address */\r\n  if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS1;\r\n  }\r\n  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS2;\r\n  }\r\n  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS3;\r\n  }\r\n  else /* FMC_NORSRAM_BANK4 */\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS4;\r\n  }  \r\n  \r\n  NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);\r\n\r\n  /* Check the NOR controller state */\r\n  hnor->State = HAL_NOR_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hnor);   \r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Read data from NOR memory \r\n  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains\r\n  *                the configuration information for NOR module.\r\n  * @param  pAddress: pointer to Device address\r\n  * @param  pData : pointer to read data  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)\r\n{\r\n  uint32_t deviceaddress = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hnor);\r\n  \r\n  /* Check the NOR controller state */\r\n  if(hnor->State == HAL_NOR_STATE_BUSY)\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  \r\n  /* Select the NOR device address */\r\n  if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS1;\r\n  }\r\n  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS2;\r\n  }\r\n  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS3;\r\n  }\r\n  else /* FMC_NORSRAM_BANK4 */\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS4;\r\n  } \r\n    \r\n  /* Update the NOR controller state */\r\n  hnor->State = HAL_NOR_STATE_BUSY;\r\n  \r\n  /* Send read data command */\r\n  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); \r\n  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);  \r\n  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);\r\n\r\n  /* Read the data */\r\n  *pData = *(__IO uint32_t *)(uint32_t)pAddress;\r\n  \r\n  /* Check the NOR controller state */\r\n  hnor->State = HAL_NOR_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hnor);\r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Program data to NOR memory \r\n  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains\r\n  *                the configuration information for NOR module.\r\n  * @param  pAddress: Device address\r\n  * @param  pData : pointer to the data to write   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)\r\n{\r\n  uint32_t deviceaddress = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hnor);\r\n  \r\n  /* Check the NOR controller state */\r\n  if(hnor->State == HAL_NOR_STATE_BUSY)\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  \r\n  /* Select the NOR device address */\r\n  if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS1;\r\n  }\r\n  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS2;\r\n  }\r\n  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS3;\r\n  }\r\n  else /* FMC_NORSRAM_BANK4 */\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS4;\r\n  } \r\n    \r\n  /* Update the NOR controller state */\r\n  hnor->State = HAL_NOR_STATE_BUSY;\r\n  \r\n  /* Send program data command */\r\n  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);\r\n  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);\r\n  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);\r\n\r\n  /* Write the data */\r\n  NOR_WRITE(pAddress, *pData);\r\n  \r\n  /* Check the NOR controller state */\r\n  hnor->State = HAL_NOR_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hnor);\r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Reads a half-word buffer from the NOR memory.\r\n  * @param  hnor: pointer to the NOR handle\r\n  * @param  uwAddress: NOR memory internal address to read from.\r\n  * @param  pData: pointer to the buffer that receives the data read from the \r\n  *         NOR memory.\r\n  * @param  uwBufferSize : number of Half word to read.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)\r\n{\r\n  uint32_t deviceaddress = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hnor);\r\n  \r\n  /* Check the NOR controller state */\r\n  if(hnor->State == HAL_NOR_STATE_BUSY)\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  \r\n  /* Select the NOR device address */\r\n  if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS1;\r\n  }\r\n  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS2;\r\n  }\r\n  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS3;\r\n  }\r\n  else /* FMC_NORSRAM_BANK4 */\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS4;\r\n  }  \r\n    \r\n  /* Update the NOR controller state */\r\n  hnor->State = HAL_NOR_STATE_BUSY;\r\n  \r\n  /* Send read data command */\r\n  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); \r\n  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);  \r\n  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);\r\n  \r\n  /* Read buffer */\r\n  while( uwBufferSize > 0) \r\n  {\r\n    *pData++ = *(__IO uint16_t *)uwAddress;\r\n    uwAddress += 2;\r\n    uwBufferSize--;\r\n  } \r\n  \r\n  /* Check the NOR controller state */\r\n  hnor->State = HAL_NOR_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hnor);\r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Writes a half-word buffer to the NOR memory. This function must be used \r\n            only with S29GL128P NOR memory. \r\n  * @param  hnor: pointer to the NOR handle\r\n  * @param  uwAddress: NOR memory internal start write address \r\n  * @param  pData: pointer to source data buffer. \r\n  * @param  uwBufferSize: Size of the buffer to write\r\n  * @retval HAL status\r\n  */ \r\nHAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)\r\n{\r\n  uint16_t * p_currentaddress = (uint16_t *)NULL;\r\n  uint16_t * p_endaddress = (uint16_t *)NULL;\r\n  uint32_t lastloadedaddress = 0, deviceaddress = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hnor);\r\n  \r\n  /* Check the NOR controller state */\r\n  if(hnor->State == HAL_NOR_STATE_BUSY)\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  \r\n  /* Select the NOR device address */\r\n  if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS1;\r\n  }\r\n  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS2;\r\n  }\r\n  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS3;\r\n  }\r\n  else /* FMC_NORSRAM_BANK4 */\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS4;\r\n  }  \r\n    \r\n  /* Update the NOR controller state */\r\n  hnor->State = HAL_NOR_STATE_BUSY;\r\n  \r\n  /* Initialize variables */\r\n  p_currentaddress  = (uint16_t*)((uint32_t)(uwAddress));\r\n  p_endaddress      = p_currentaddress + (uwBufferSize-1);\r\n  lastloadedaddress = (uint32_t)(uwAddress);\r\n\r\n  /* Issue unlock command sequence */\r\n  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);\r\n  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); \r\n\r\n  /* Write Buffer Load Command */\r\n  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG); \r\n  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), (uwBufferSize - 1)); \r\n\r\n  /* Load Data into NOR Buffer */\r\n  while(p_currentaddress <= p_endaddress)\r\n  {\r\n    /* Store last loaded address & data value (for polling) */\r\n     lastloadedaddress = (uint32_t)p_currentaddress;\r\n \r\n    NOR_WRITE(p_currentaddress, *pData++);\r\n    \r\n    p_currentaddress ++; \r\n  }\r\n\r\n  NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);\r\n  \r\n  /* Check the NOR controller state */\r\n  hnor->State = HAL_NOR_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hnor);\r\n  \r\n  return HAL_OK; \r\n  \r\n}\r\n\r\n/**\r\n  * @brief  Erase the specified block of the NOR memory \r\n  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains\r\n  *                the configuration information for NOR module.\r\n  * @param  BlockAddress : Block to erase address \r\n  * @param  Address: Device address\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)\r\n{\r\n  uint32_t deviceaddress = 0;\r\n\r\n  /* Process Locked */\r\n  __HAL_LOCK(hnor);\r\n  \r\n  /* Check the NOR controller state */\r\n  if(hnor->State == HAL_NOR_STATE_BUSY)\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  \r\n  /* Select the NOR device address */\r\n  if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS1;\r\n  }\r\n  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS2;\r\n  }\r\n  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS3;\r\n  }\r\n  else /* FMC_NORSRAM_BANK4 */\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS4;\r\n  }\r\n    \r\n  /* Update the NOR controller state */\r\n  hnor->State = HAL_NOR_STATE_BUSY;\r\n  \r\n  /* Send block erase command sequence */\r\n  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);\r\n  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);\r\n  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);\r\n  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);\r\n  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);\r\n  NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);\r\n\r\n  /* Check the NOR memory status and update the controller state */\r\n  hnor->State = HAL_NOR_STATE_READY;\r\n    \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hnor);\r\n  \r\n  return HAL_OK;\r\n \r\n}\r\n\r\n/**\r\n  * @brief  Erase the entire NOR chip.\r\n  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains\r\n  *                the configuration information for NOR module.\r\n  * @param  Address : Device address  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)\r\n{\r\n  uint32_t deviceaddress = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hnor);\r\n  \r\n  /* Check the NOR controller state */\r\n  if(hnor->State == HAL_NOR_STATE_BUSY)\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  \r\n  /* Select the NOR device address */\r\n  if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS1;\r\n  }\r\n  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS2;\r\n  }\r\n  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS3;\r\n  }\r\n  else /* FMC_NORSRAM_BANK4 */\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS4;\r\n  }\r\n    \r\n  /* Update the NOR controller state */\r\n  hnor->State = HAL_NOR_STATE_BUSY;  \r\n    \r\n  /* Send NOR chip erase command sequence */\r\n  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);\r\n  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);\r\n  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);\r\n  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);\r\n  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);  \r\n  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);\r\n  \r\n  /* Check the NOR memory status and update the controller state */\r\n  hnor->State = HAL_NOR_STATE_READY;\r\n    \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hnor);\r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Read NOR flash CFI IDs\r\n  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains\r\n  *                the configuration information for NOR module.\r\n  * @param  pNOR_CFI : pointer to NOR CFI IDs structure  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)\r\n{\r\n  uint32_t deviceaddress = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hnor);\r\n  \r\n  /* Check the NOR controller state */\r\n  if(hnor->State == HAL_NOR_STATE_BUSY)\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  \r\n  /* Select the NOR device address */\r\n  if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS1;\r\n  }\r\n  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS2;\r\n  }\r\n  else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS3;\r\n  }\r\n  else /* FMC_NORSRAM_BANK4 */\r\n  {\r\n    deviceaddress = NOR_MEMORY_ADRESS4;\r\n  }  \r\n    \r\n  /* Update the NOR controller state */\r\n  hnor->State = HAL_NOR_STATE_BUSY;\r\n  \r\n  /* Send read CFI query command */\r\n  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);\r\n\r\n  /* read the NOR CFI information */\r\n  pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);\r\n  pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);\r\n  pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);\r\n  pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);\r\n\r\n  /* Check the NOR controller state */\r\n  hnor->State = HAL_NOR_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hnor);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup NOR_Exported_Functions_Group3 NOR Control functions\r\n *  @brief   management functions \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                        ##### NOR Control functions #####\r\n  ==============================================================================\r\n  [..]\r\n    This subsection provides a set of functions allowing to control dynamically\r\n    the NOR interface.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n    \r\n/**\r\n  * @brief  Enables dynamically NOR write operation.\r\n  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains\r\n  *                the configuration information for NOR module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hnor);\r\n\r\n  /* Enable write operation */\r\n  FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank); \r\n  \r\n  /* Update the NOR controller state */\r\n  hnor->State = HAL_NOR_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hnor); \r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Disables dynamically NOR write operation.\r\n  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains\r\n  *                the configuration information for NOR module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hnor);\r\n\r\n  /* Update the SRAM controller state */\r\n  hnor->State = HAL_NOR_STATE_BUSY;\r\n    \r\n  /* Disable write operation */\r\n  FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); \r\n  \r\n  /* Update the NOR controller state */\r\n  hnor->State = HAL_NOR_STATE_PROTECTED;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hnor); \r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @}\r\n  */  \r\n  \r\n/** @defgroup NOR_Exported_Functions_Group4 NOR State functions \r\n *  @brief   Peripheral State functions \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                      ##### NOR State functions #####\r\n  ==============================================================================  \r\n  [..]\r\n    This subsection permits to get in run-time the status of the NOR controller \r\n    and the data flow.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @brief  return the NOR controller state\r\n  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains\r\n  *                the configuration information for NOR module.\r\n  * @retval NOR controller state\r\n  */\r\nHAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)\r\n{\r\n  return hnor->State;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the NOR operation status.\r\n  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains\r\n  *                the configuration information for NOR module.   \r\n  * @param  Address: Device address\r\n  * @param  Timeout: NOR programming Timeout\r\n  * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR\r\n  *         or HAL_NOR_STATUS_TIMEOUT\r\n  */\r\nHAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)\r\n{ \r\n  HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;\r\n  uint16_t tmpSR1 = 0, tmpSR2 = 0;\r\n  uint32_t tickstart = 0;\r\n\r\n  /* Poll on NOR memory Ready/Busy signal ------------------------------------*/\r\n  HAL_NOR_MspWait(hnor, Timeout);\r\n  \r\n  /* Get the NOR memory operation status -------------------------------------*/\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  while((status != HAL_NOR_STATUS_SUCCESS ) && (status != HAL_NOR_STATUS_TIMEOUT))\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        status = HAL_NOR_STATUS_TIMEOUT; \r\n      } \r\n    } \r\n\r\n    /* Read NOR status register (DQ6 and DQ5) */\r\n    tmpSR1 = *(__IO uint16_t *)Address;\r\n    tmpSR2 = *(__IO uint16_t *)Address;\r\n\r\n    /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS  */\r\n    if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6)) \r\n    {\r\n      return HAL_NOR_STATUS_SUCCESS ;\r\n    }\r\n    \r\n    if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)\r\n    {\r\n      status = HAL_NOR_STATUS_ONGOING;\r\n    }\r\n    \r\n    tmpSR1 = *(__IO uint16_t *)Address;\r\n    tmpSR2 = *(__IO uint16_t *)Address;\r\n\r\n    /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS  */\r\n    if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6)) \r\n    {\r\n      return HAL_NOR_STATUS_SUCCESS;\r\n    }\r\n    if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)\r\n    {\r\n      return HAL_NOR_STATUS_ERROR;\r\n    } \r\n  }\r\n\r\n  /* Return the operation status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n#endif /* HAL_NOR_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_pcd.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   PCD HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the USB Peripheral Controller:\r\n  *           + Initialization and de-initialization functions\r\n  *           + IO operation functions\r\n  *           + Peripheral Control functions \r\n  *           + Peripheral State functions\r\n  *         \r\n  @verbatim\r\n  ==============================================================================\r\n                    ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]\r\n      The PCD HAL driver can be used as follows:\r\n\r\n     (#) Declare a PCD_HandleTypeDef handle structure, for example:\r\n         PCD_HandleTypeDef  hpcd;\r\n        \r\n     (#) Fill parameters of Init structure in HCD handle\r\n  \r\n     (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...) \r\n\r\n     (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:\r\n         (##) Enable the PCD/USB Low Level interface clock using \r\n              (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();\r\n              (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)\r\n           \r\n         (##) Initialize the related GPIO clocks\r\n         (##) Configure PCD pin-out\r\n         (##) Configure PCD NVIC interrupt\r\n    \r\n     (#)Associate the Upper USB device stack to the HAL PCD Driver:\r\n         (##) hpcd.pData = pdev;\r\n\r\n     (#)Enable PCD transmission and reception:\r\n         (##) HAL_PCD_Start();\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup PCD PCD\r\n  * @brief PCD HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_PCD_MODULE_ENABLED\r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/* Private macros ------------------------------------------------------------*/\r\n/** @defgroup PCD_Private_Macros PCD Private Macros\r\n  * @{\r\n  */ \r\n#define PCD_MIN(a, b)  (((a) < (b)) ? (a) : (b))\r\n#define PCD_MAX(a, b)  (((a) > (b)) ? (a) : (b))\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions prototypes ----------------------------------------------*/\r\n/** @defgroup PCD_Private_Functions PCD Private Functions\r\n  * @{\r\n  */\r\nstatic HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup PCD_Exported_Functions PCD Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions \r\n *  @brief    Initialization and Configuration functions \r\n *\r\n@verbatim    \r\n ===============================================================================\r\n            ##### Initialization and de-initialization functions #####\r\n ===============================================================================\r\n    [..]  This section provides functions allowing to:\r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the PCD according to the specified\r\n  *         parameters in the PCD_InitTypeDef and create the associated handle.\r\n  * @param  hpcd: PCD handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)\r\n{ \r\n  uint32_t i = 0;\r\n  \r\n  /* Check the PCD handle allocation */\r\n  if(hpcd == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));\r\n\r\n  hpcd->State = HAL_PCD_STATE_BUSY;\r\n  \r\n  /* Init the low level hardware : GPIO, CLOCK, NVIC... */\r\n  HAL_PCD_MspInit(hpcd);\r\n\r\n  /* Disable the Interrupts */\r\n __HAL_PCD_DISABLE(hpcd);\r\n \r\n /*Init the Core (common init.) */\r\n USB_CoreInit(hpcd->Instance, hpcd->Init);\r\n \r\n /* Force Device Mode*/\r\n USB_SetCurrentMode(hpcd->Instance , USB_OTG_DEVICE_MODE);\r\n \r\n /* Init endpoints structures */\r\n for (i = 0; i < 15 ; i++)\r\n {\r\n   /* Init ep structure */\r\n   hpcd->IN_ep[i].is_in = 1;\r\n   hpcd->IN_ep[i].num = i;\r\n   hpcd->IN_ep[i].tx_fifo_num = i;\r\n   /* Control until ep is activated */\r\n   hpcd->IN_ep[i].type = EP_TYPE_CTRL;\r\n   hpcd->IN_ep[i].maxpacket =  0;\r\n   hpcd->IN_ep[i].xfer_buff = 0;\r\n   hpcd->IN_ep[i].xfer_len = 0;\r\n }\r\n \r\n for (i = 0; i < 15 ; i++)\r\n {\r\n   hpcd->OUT_ep[i].is_in = 0;\r\n   hpcd->OUT_ep[i].num = i;\r\n   hpcd->IN_ep[i].tx_fifo_num = i;\r\n   /* Control until ep is activated */\r\n   hpcd->OUT_ep[i].type = EP_TYPE_CTRL;\r\n   hpcd->OUT_ep[i].maxpacket = 0;\r\n   hpcd->OUT_ep[i].xfer_buff = 0;\r\n   hpcd->OUT_ep[i].xfer_len = 0;\r\n   \r\n   hpcd->Instance->DIEPTXF[i] = 0;\r\n }\r\n \r\n /* Init Device */\r\n USB_DevInit(hpcd->Instance, hpcd->Init);\r\n \r\n hpcd->State= HAL_PCD_STATE_READY;\r\n \r\n /* Activate LPM */\r\n if (hpcd->Init.lpm_enable == 1)\r\n {\r\n   HAL_PCDEx_ActivateLPM(hpcd);\r\n }\r\n \r\n USB_DevDisconnect (hpcd->Instance);  \r\n return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the PCD peripheral. \r\n  * @param  hpcd: PCD handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)\r\n{\r\n  /* Check the PCD handle allocation */\r\n  if(hpcd == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  hpcd->State = HAL_PCD_STATE_BUSY;\r\n  \r\n  /* Stop Device */\r\n  HAL_PCD_Stop(hpcd);\r\n    \r\n  /* DeInit the low level hardware */\r\n  HAL_PCD_MspDeInit(hpcd);\r\n  \r\n  hpcd->State = HAL_PCD_STATE_RESET; \r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the PCD MSP.\r\n  * @param  hpcd: PCD handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hpcd);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_PCD_MspInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes PCD MSP.\r\n  * @param  hpcd: PCD handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hpcd);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_PCD_MspDeInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions\r\n *  @brief   Data transfers functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                      ##### IO operation functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides a set of functions allowing to manage the PCD data \r\n    transfers.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @brief  Start The USB OTG Device.\r\n  * @param  hpcd: PCD handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)\r\n{ \r\n  __HAL_LOCK(hpcd); \r\n  USB_DevConnect (hpcd->Instance);  \r\n  __HAL_PCD_ENABLE(hpcd);\r\n  __HAL_UNLOCK(hpcd); \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stop The USB OTG Device.\r\n  * @param  hpcd: PCD handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)\r\n{ \r\n  __HAL_LOCK(hpcd); \r\n  __HAL_PCD_DISABLE(hpcd);\r\n  USB_StopDevice(hpcd->Instance);\r\n  USB_DevDisconnect (hpcd->Instance);\r\n  __HAL_UNLOCK(hpcd); \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Handle PCD interrupt request.\r\n  * @param  hpcd: PCD handle\r\n  * @retval HAL status\r\n  */\r\nvoid HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)\r\n{\r\n  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\r\n  uint32_t i = 0, ep_intr = 0, epint = 0, epnum = 0;\r\n  uint32_t fifoemptymsk = 0, temp = 0;\r\n  USB_OTG_EPTypeDef *ep = NULL;\r\n  uint32_t hclk = 200000000;\r\n  \r\n  /* ensure that we are in device mode */\r\n  if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)\r\n  {\r\n    /* avoid spurious interrupt */\r\n    if(__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) \r\n    {\r\n      return;\r\n    }\r\n    \r\n    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))\r\n    {\r\n     /* incorrect mode, acknowledge the interrupt */\r\n      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);\r\n    }\r\n    \r\n    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))\r\n    {\r\n      epnum = 0;\r\n      \r\n      /* Read in the device interrupt bits */\r\n      ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);\r\n      \r\n      while ( ep_intr )\r\n      {\r\n        if (ep_intr & 0x1)\r\n        {\r\n          epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, epnum);\r\n          \r\n          if(( epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)\r\n          {\r\n            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);\r\n            \r\n            if(hpcd->Init.dma_enable == 1)\r\n            {\r\n              hpcd->OUT_ep[epnum].xfer_count = hpcd->OUT_ep[epnum].maxpacket- (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); \r\n              hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;            \r\n            }\r\n            \r\n            HAL_PCD_DataOutStageCallback(hpcd, epnum);\r\n            if(hpcd->Init.dma_enable == 1)\r\n            {\r\n              if((epnum == 0) && (hpcd->OUT_ep[epnum].xfer_len == 0))\r\n              {\r\n                 /* this is ZLP, so prepare EP0 for next setup */\r\n                USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup);\r\n              }              \r\n            }\r\n          }\r\n          \r\n          if(( epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)\r\n          {\r\n            /* Inform the upper layer that a setup packet is available */\r\n            HAL_PCD_SetupStageCallback(hpcd);\r\n            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);\r\n          }\r\n          \r\n          if(( epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)\r\n          {\r\n            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);\r\n          }\r\n          /* Clear Status Phase Received interrupt */\r\n          if(( epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)\r\n          {\r\n            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);\r\n          }\r\n        }\r\n        epnum++;\r\n        ep_intr >>= 1;\r\n      }\r\n    }\r\n    \r\n    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))\r\n    {\r\n      /* Read in the device interrupt bits */\r\n      ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);\r\n      \r\n      epnum = 0;\r\n      \r\n      while ( ep_intr )\r\n      {\r\n        if (ep_intr & 0x1) /* In ITR */\r\n        {\r\n          epint = USB_ReadDevInEPInterrupt(hpcd->Instance, epnum);\r\n\r\n           if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)\r\n          {\r\n            fifoemptymsk = 0x1 << epnum;\r\n            USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;\r\n            \r\n            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);\r\n            \r\n            if (hpcd->Init.dma_enable == 1)\r\n            {\r\n              hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; \r\n            }\r\n                                      \r\n            HAL_PCD_DataInStageCallback(hpcd, epnum);\r\n\r\n            if (hpcd->Init.dma_enable == 1)\r\n            {\r\n              /* this is ZLP, so prepare EP0 for next setup */\r\n              if((epnum == 0) && (hpcd->IN_ep[epnum].xfer_len == 0))\r\n              {\r\n                /* prepare to rx more setup packets */\r\n                USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup);\r\n              }\r\n            }           \r\n          }\r\n           if(( epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)\r\n          {\r\n            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);\r\n          }\r\n          if(( epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)\r\n          {\r\n            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);\r\n          }\r\n          if(( epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)\r\n          {\r\n            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);\r\n          }\r\n          if(( epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)\r\n          {\r\n            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);\r\n          }       \r\n          if(( epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)\r\n          {\r\n            PCD_WriteEmptyTxFifo(hpcd , epnum);\r\n          }\r\n        }\r\n        epnum++;\r\n        ep_intr >>= 1;\r\n      }\r\n    }\r\n    \r\n    /* Handle Resume Interrupt */\r\n    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))\r\n    {\r\n      /* Clear the Remote Wake-up Signaling */\r\n      USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;\r\n      \r\n      if(hpcd->LPM_State == LPM_L1)\r\n      {\r\n        hpcd->LPM_State = LPM_L0;\r\n        HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);\r\n      }\r\n      else\r\n      {\r\n        HAL_PCD_ResumeCallback(hpcd);\r\n      }\r\n      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);\r\n    }\r\n    \r\n    /* Handle Suspend Interrupt */\r\n    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))\r\n    {\r\n      if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)\r\n      {\r\n        \r\n        HAL_PCD_SuspendCallback(hpcd);\r\n      }\r\n      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);\r\n    }\r\n    \r\n    /* Handle LPM Interrupt */ \r\n    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))\r\n    {\r\n      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);      \r\n      if( hpcd->LPM_State == LPM_L0)\r\n      {\r\n        hpcd->LPM_State = LPM_L1;\r\n        hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >>2 ;\r\n        HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);\r\n      }\r\n      else\r\n      {\r\n        HAL_PCD_SuspendCallback(hpcd);\r\n      }\r\n    }\r\n    \r\n    /* Handle Reset Interrupt */\r\n    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))\r\n    {\r\n      USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; \r\n      USB_FlushTxFifo(hpcd->Instance ,  0 );\r\n      \r\n      for (i = 0; i < hpcd->Init.dev_endpoints ; i++)\r\n      {\r\n        USBx_INEP(i)->DIEPINT = 0xFF;\r\n        USBx_OUTEP(i)->DOEPINT = 0xFF;\r\n      }\r\n      USBx_DEVICE->DAINT = 0xFFFFFFFF;\r\n      USBx_DEVICE->DAINTMSK |= 0x10001;\r\n      \r\n      if(hpcd->Init.use_dedicated_ep1)\r\n      {\r\n        USBx_DEVICE->DOUTEP1MSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM); \r\n        USBx_DEVICE->DINEP1MSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);  \r\n      }\r\n      else\r\n      {\r\n        USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM);\r\n        USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);\r\n      }\r\n      \r\n      /* Set Default Address to 0 */\r\n      USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;\r\n      \r\n      /* setup EP0 to receive SETUP packets */\r\n      USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);\r\n      \r\n      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);\r\n    }\r\n    \r\n    /* Handle Enumeration done Interrupt */\r\n    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))\r\n    {\r\n      USB_ActivateSetup(hpcd->Instance);\r\n      hpcd->Instance->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;\r\n      \r\n      if ( USB_GetDevSpeed(hpcd->Instance) == USB_OTG_SPEED_HIGH)\r\n      {\r\n        hpcd->Init.speed            = USB_OTG_SPEED_HIGH;\r\n        hpcd->Init.ep0_mps          = USB_OTG_HS_MAX_PACKET_SIZE ;\r\n        hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_HS_TRDT_VALUE << 10) & USB_OTG_GUSBCFG_TRDT);\r\n      }\r\n      else\r\n      {\r\n        hpcd->Init.speed            = USB_OTG_SPEED_FULL;\r\n        hpcd->Init.ep0_mps          = USB_OTG_FS_MAX_PACKET_SIZE ;  \r\n        \r\n        /* The USBTRD is configured according to the tables below, depending on AHB frequency \r\n        used by application. In the low AHB frequency range it is used to stretch enough the USB response \r\n        time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access \r\n        latency to the Data FIFO */\r\n        \r\n        /* Get hclk frequency value */\r\n        hclk = HAL_RCC_GetHCLKFreq();\r\n\t\t\r\n\t\tif((hclk >= 14200000)&&(hclk < 15000000))\r\n        {\r\n          /* hclk Clock Range between 14.2-15 MHz */\r\n          hpcd->Instance->GUSBCFG |= (uint32_t)((0xF << 10) & USB_OTG_GUSBCFG_TRDT);\r\n        }\r\n        \r\n        else if((hclk >= 15000000)&&(hclk < 16000000))\r\n        {\r\n          /* hclk Clock Range between 15-16 MHz */\r\n          hpcd->Instance->GUSBCFG |= (uint32_t)((0xE << 10) & USB_OTG_GUSBCFG_TRDT);\r\n        }\r\n        \r\n        else if((hclk >= 16000000)&&(hclk < 17200000))\r\n        {\r\n          /* hclk Clock Range between 16-17.2 MHz */\r\n          hpcd->Instance->GUSBCFG |= (uint32_t)((0xD << 10) & USB_OTG_GUSBCFG_TRDT);\r\n        }\r\n        \r\n        else if((hclk >= 17200000)&&(hclk < 18500000))\r\n        {\r\n          /* hclk Clock Range between 17.2-18.5 MHz */\r\n          hpcd->Instance->GUSBCFG |= (uint32_t)((0xC << 10) & USB_OTG_GUSBCFG_TRDT);\r\n        }\r\n        \r\n        else if((hclk >= 18500000)&&(hclk < 20000000))\r\n        {\r\n          /* hclk Clock Range between 18.5-20 MHz */\r\n          hpcd->Instance->GUSBCFG |= (uint32_t)((0xB << 10) & USB_OTG_GUSBCFG_TRDT);\r\n        }\r\n        \r\n        else if((hclk >= 20000000)&&(hclk < 21800000))\r\n        {\r\n          /* hclk Clock Range between 20-21.8 MHz */\r\n          hpcd->Instance->GUSBCFG |= (uint32_t)((0xA << 10) & USB_OTG_GUSBCFG_TRDT);\r\n        }\r\n        \r\n        else if((hclk >= 21800000)&&(hclk < 24000000))\r\n        {\r\n          /* hclk Clock Range between 21.8-24 MHz */\r\n          hpcd->Instance->GUSBCFG |= (uint32_t)((0x9 << 10) & USB_OTG_GUSBCFG_TRDT);\r\n        }\r\n        \r\n        else if((hclk >= 24000000)&&(hclk < 27700000))\r\n        {\r\n          /* hclk Clock Range between 24-27.7 MHz */\r\n          hpcd->Instance->GUSBCFG |= (uint32_t)((0x8 << 10) & USB_OTG_GUSBCFG_TRDT);\r\n        }\r\n        \r\n        else if((hclk >= 27700000)&&(hclk < 32000000))\r\n        {\r\n          /* hclk Clock Range between 27.7-32 MHz */\r\n          hpcd->Instance->GUSBCFG |= (uint32_t)((0x7 << 10) & USB_OTG_GUSBCFG_TRDT);\r\n        }\r\n        \r\n        else /* if(hclk >= 32000000) */\r\n        {\r\n          /* hclk Clock Range between 32-200 MHz */\r\n          hpcd->Instance->GUSBCFG |= (uint32_t)((0x6 << 10) & USB_OTG_GUSBCFG_TRDT);\r\n        }  \r\n      }\r\n      \r\n      HAL_PCD_ResetCallback(hpcd);\r\n      \r\n      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);\r\n    }\r\n    \r\n    /* Handle RxQLevel Interrupt */\r\n    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))\r\n    {\r\n      USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);\r\n      temp = USBx->GRXSTSP;\r\n      ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];\r\n      \r\n      if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_DATA_UPDT)\r\n      {\r\n        if((temp & USB_OTG_GRXSTSP_BCNT) != 0)\r\n        {\r\n          USB_ReadPacket(USBx, ep->xfer_buff, (temp & USB_OTG_GRXSTSP_BCNT) >> 4);\r\n          ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;\r\n          ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;\r\n        }\r\n      }\r\n      else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_SETUP_UPDT)\r\n      {\r\n        USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8);\r\n        ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;\r\n      }\r\n      USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);\r\n    }\r\n    \r\n    /* Handle SOF Interrupt */\r\n    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))\r\n    {\r\n      HAL_PCD_SOFCallback(hpcd);\r\n      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);\r\n    }\r\n    \r\n    /* Handle Incomplete ISO IN Interrupt */\r\n    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))\r\n    {\r\n      HAL_PCD_ISOINIncompleteCallback(hpcd, epnum);\r\n      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);\r\n    } \r\n    \r\n    /* Handle Incomplete ISO OUT Interrupt */\r\n    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))\r\n    {\r\n      HAL_PCD_ISOOUTIncompleteCallback(hpcd, epnum);\r\n      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);\r\n    } \r\n    \r\n    /* Handle Connection event Interrupt */\r\n    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))\r\n    {\r\n      HAL_PCD_ConnectCallback(hpcd);\r\n      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);\r\n    } \r\n    \r\n    /* Handle Disconnection event Interrupt */\r\n    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))\r\n    {\r\n      temp = hpcd->Instance->GOTGINT;\r\n      \r\n      if((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)\r\n      {\r\n        HAL_PCD_DisconnectCallback(hpcd);\r\n      }\r\n      hpcd->Instance->GOTGINT |= temp;\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Data OUT stage callback.\r\n  * @param  hpcd: PCD handle\r\n  * @param  epnum: endpoint number  \r\n  * @retval None\r\n  */\r\n __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hpcd);\r\n  UNUSED(epnum);  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_PCD_DataOutStageCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  Data IN stage callback.\r\n  * @param  hpcd: PCD handle\r\n  * @param  epnum: endpoint number  \r\n  * @retval None\r\n  */\r\n __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hpcd);\r\n  UNUSED(epnum); \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_PCD_DataInStageCallback could be implemented in the user file\r\n   */ \r\n}\r\n/**\r\n  * @brief  Setup stage callback.\r\n  * @param  hpcd: PCD handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hpcd);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_PCD_SetupStageCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  USB Start Of Frame callback.\r\n  * @param  hpcd: PCD handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hpcd);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_PCD_SOFCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  USB Reset callback.\r\n  * @param  hpcd: PCD handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hpcd);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_PCD_ResetCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  Suspend event callback.\r\n  * @param  hpcd: PCD handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hpcd);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_PCD_SuspendCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  Resume event callback.\r\n  * @param  hpcd: PCD handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hpcd);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_PCD_ResumeCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  Incomplete ISO OUT callback.\r\n  * @param  hpcd: PCD handle\r\n  * @param  epnum: endpoint number\r\n  * @retval None\r\n  */\r\n __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hpcd);\r\n  UNUSED(epnum);  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  Incomplete ISO IN  callback.\r\n  * @param  hpcd: PCD handle\r\n  * @param  epnum: endpoint number  \r\n  * @retval None\r\n  */\r\n __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hpcd);\r\n  UNUSED(epnum);  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  Connection event callback.\r\n  * @param  hpcd: PCD handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hpcd);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_PCD_ConnectCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  Disconnection event callback.\r\n  * @param  hpcd: PCD handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hpcd);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_PCD_DisconnectCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions\r\n *  @brief   management functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                      ##### Peripheral Control functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides a set of functions allowing to control the PCD data \r\n    transfers.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Connect the USB device.\r\n  * @param  hpcd: PCD handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)\r\n{\r\n  __HAL_LOCK(hpcd); \r\n  USB_DevConnect(hpcd->Instance);\r\n  __HAL_UNLOCK(hpcd); \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Disconnect the USB device.\r\n  * @param  hpcd: PCD handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)\r\n{\r\n  __HAL_LOCK(hpcd); \r\n  USB_DevDisconnect(hpcd->Instance);\r\n  __HAL_UNLOCK(hpcd); \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Set the USB Device address. \r\n  * @param  hpcd: PCD handle\r\n  * @param  address: new device address\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)\r\n{\r\n  __HAL_LOCK(hpcd); \r\n  USB_SetDevAddress(hpcd->Instance, address);\r\n  __HAL_UNLOCK(hpcd);   \r\n  return HAL_OK;\r\n}\r\n/**\r\n  * @brief  Open and configure an endpoint.\r\n  * @param  hpcd: PCD handle\r\n  * @param  ep_addr: endpoint address\r\n  * @param  ep_mps: endpoint max packet size\r\n  * @param  ep_type: endpoint type   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)\r\n{\r\n  HAL_StatusTypeDef  ret = HAL_OK;\r\n  USB_OTG_EPTypeDef *ep;\r\n  \r\n  if ((ep_addr & 0x80) == 0x80)\r\n  {\r\n    ep = &hpcd->IN_ep[ep_addr & 0x7F];\r\n  }\r\n  else\r\n  {\r\n    ep = &hpcd->OUT_ep[ep_addr & 0x7F];\r\n  }\r\n  ep->num   = ep_addr & 0x7F;\r\n  \r\n  ep->is_in = (0x80 & ep_addr) != 0;\r\n  ep->maxpacket = ep_mps;\r\n  ep->type = ep_type;\r\n  if (ep->is_in)\r\n  {\r\n    /* Assign a Tx FIFO */\r\n    ep->tx_fifo_num = ep->num;\r\n  }\r\n  /* Set initial data PID. */\r\n  if (ep_type == EP_TYPE_BULK )\r\n  {\r\n    ep->data_pid_start = 0;\r\n  }\r\n  \r\n  __HAL_LOCK(hpcd); \r\n  USB_ActivateEndpoint(hpcd->Instance , ep);\r\n  __HAL_UNLOCK(hpcd);   \r\n  return ret;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Deactivate an endpoint.\r\n  * @param  hpcd: PCD handle\r\n  * @param  ep_addr: endpoint address\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)\r\n{  \r\n  USB_OTG_EPTypeDef *ep;\r\n  \r\n  if ((ep_addr & 0x80) == 0x80)\r\n  {\r\n    ep = &hpcd->IN_ep[ep_addr & 0x7F];\r\n  }\r\n  else\r\n  {\r\n    ep = &hpcd->OUT_ep[ep_addr & 0x7F];\r\n  }\r\n  ep->num   = ep_addr & 0x7F;\r\n  \r\n  ep->is_in = (0x80 & ep_addr) != 0;\r\n  \r\n  __HAL_LOCK(hpcd); \r\n  USB_DeactivateEndpoint(hpcd->Instance , ep);\r\n  __HAL_UNLOCK(hpcd);   \r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Receive an amount of data.  \r\n  * @param  hpcd: PCD handle\r\n  * @param  ep_addr: endpoint address\r\n  * @param  pBuf: pointer to the reception buffer   \r\n  * @param  len: amount of data to be received\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)\r\n{\r\n  USB_OTG_EPTypeDef *ep;\r\n  \r\n  ep = &hpcd->OUT_ep[ep_addr & 0x7F];\r\n  \r\n  /*setup and start the Xfer */\r\n  ep->xfer_buff = pBuf;  \r\n  ep->xfer_len = len;\r\n  ep->xfer_count = 0;\r\n  ep->is_in = 0;\r\n  ep->num = ep_addr & 0x7F;\r\n  \r\n  if (hpcd->Init.dma_enable == 1)\r\n  {\r\n    ep->dma_addr = (uint32_t)pBuf;  \r\n  }\r\n  \r\n  __HAL_LOCK(hpcd); \r\n  \r\n  if ((ep_addr & 0x7F) == 0 )\r\n  {\r\n    USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);\r\n  }\r\n  else\r\n  {\r\n    USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);\r\n  }\r\n  __HAL_UNLOCK(hpcd); \r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Get Received Data Size.\r\n  * @param  hpcd: PCD handle\r\n  * @param  ep_addr: endpoint address\r\n  * @retval Data Size\r\n  */\r\nuint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)\r\n{\r\n  return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count;\r\n}\r\n/**\r\n  * @brief  Send an amount of data.  \r\n  * @param  hpcd: PCD handle\r\n  * @param  ep_addr: endpoint address\r\n  * @param  pBuf: pointer to the transmission buffer   \r\n  * @param  len: amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)\r\n{\r\n  USB_OTG_EPTypeDef *ep;\r\n  \r\n  ep = &hpcd->IN_ep[ep_addr & 0x7F];\r\n  \r\n  /*setup and start the Xfer */\r\n  ep->xfer_buff = pBuf;  \r\n  ep->xfer_len = len;\r\n  ep->xfer_count = 0;\r\n  ep->is_in = 1;\r\n  ep->num = ep_addr & 0x7F;\r\n  \r\n  if (hpcd->Init.dma_enable == 1)\r\n  {\r\n    ep->dma_addr = (uint32_t)pBuf;  \r\n  }\r\n  \r\n  __HAL_LOCK(hpcd); \r\n  \r\n  if ((ep_addr & 0x7F) == 0 )\r\n  {\r\n    USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);\r\n  }\r\n  else\r\n  {\r\n    USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);\r\n  }\r\n  \r\n  __HAL_UNLOCK(hpcd);\r\n     \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Set a STALL condition over an endpoint.\r\n  * @param  hpcd: PCD handle\r\n  * @param  ep_addr: endpoint address\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)\r\n{\r\n  USB_OTG_EPTypeDef *ep;\r\n  \r\n  if ((0x80 & ep_addr) == 0x80)\r\n  {\r\n    ep = &hpcd->IN_ep[ep_addr & 0x7F];\r\n  }\r\n  else\r\n  {\r\n    ep = &hpcd->OUT_ep[ep_addr];\r\n  }\r\n  \r\n  ep->is_stall = 1;\r\n  ep->num   = ep_addr & 0x7F;\r\n  ep->is_in = ((ep_addr & 0x80) == 0x80);\r\n  \r\n  \r\n  __HAL_LOCK(hpcd); \r\n  USB_EPSetStall(hpcd->Instance , ep);\r\n  if((ep_addr & 0x7F) == 0)\r\n  {\r\n    USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);\r\n  }\r\n  __HAL_UNLOCK(hpcd); \r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Clear a STALL condition over in an endpoint.\r\n  * @param  hpcd: PCD handle\r\n  * @param  ep_addr: endpoint address\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)\r\n{\r\n  USB_OTG_EPTypeDef *ep;\r\n  \r\n  if ((0x80 & ep_addr) == 0x80)\r\n  {\r\n    ep = &hpcd->IN_ep[ep_addr & 0x7F];\r\n  }\r\n  else\r\n  {\r\n    ep = &hpcd->OUT_ep[ep_addr];\r\n  }\r\n  \r\n  ep->is_stall = 0;\r\n  ep->num   = ep_addr & 0x7F;\r\n  ep->is_in = ((ep_addr & 0x80) == 0x80);\r\n  \r\n  __HAL_LOCK(hpcd); \r\n  USB_EPClearStall(hpcd->Instance , ep);\r\n  __HAL_UNLOCK(hpcd); \r\n    \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Flush an endpoint.\r\n  * @param  hpcd: PCD handle\r\n  * @param  ep_addr: endpoint address\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)\r\n{\r\n  __HAL_LOCK(hpcd); \r\n  \r\n  if ((ep_addr & 0x80) == 0x80)\r\n  {\r\n    USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F);\r\n  }\r\n  else\r\n  {\r\n    USB_FlushRxFifo(hpcd->Instance);\r\n  }\r\n  \r\n  __HAL_UNLOCK(hpcd); \r\n    \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Activate remote wakeup signalling.\r\n  * @param  hpcd: PCD handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)\r\n{\r\n  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  \r\n    \r\n  if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)\r\n  {\r\n    /* Activate Remote wakeup signaling */\r\n    USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;\r\n  }\r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  De-activate remote wakeup signalling.\r\n  * @param  hpcd: PCD handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)\r\n{\r\n  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  \r\n  \r\n  /* De-activate Remote wakeup signaling */\r\n   USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);\r\n  return HAL_OK;  \r\n}\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions \r\n *  @brief   Peripheral State functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                      ##### Peripheral State functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection permits to get in run-time the status of the peripheral \r\n    and the data flow.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Return the PCD handle state.\r\n  * @param  hpcd: PCD handle\r\n  * @retval HAL state\r\n  */\r\nPCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)\r\n{\r\n  return hpcd->State;\r\n}\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @addtogroup PCD_Private_Functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Check FIFO for the next packet to be loaded.\r\n  * @param  hpcd: PCD handle\r\n  * @param  epnum : endpoint number   \r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)\r\n{\r\n  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  \r\n  USB_OTG_EPTypeDef *ep;\r\n  int32_t len = 0;\r\n  uint32_t len32b;\r\n  uint32_t fifoemptymsk = 0;\r\n\r\n  ep = &hpcd->IN_ep[epnum];\r\n  len = ep->xfer_len - ep->xfer_count;\r\n  \r\n  if (len > ep->maxpacket)\r\n  {\r\n    len = ep->maxpacket;\r\n  }\r\n  \r\n  \r\n  len32b = (len + 3) / 4;\r\n \r\n  while  ( (USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b &&\r\n          ep->xfer_count < ep->xfer_len &&\r\n            ep->xfer_len != 0)\r\n  {\r\n    /* Write the FIFO */\r\n    len = ep->xfer_len - ep->xfer_count;\r\n    \r\n    if (len > ep->maxpacket)\r\n    {\r\n      len = ep->maxpacket;\r\n    }\r\n    len32b = (len + 3) / 4;\r\n    \r\n    USB_WritePacket(USBx, ep->xfer_buff, epnum, len, hpcd->Init.dma_enable); \r\n    \r\n    ep->xfer_buff  += len;\r\n    ep->xfer_count += len;\r\n  }\r\n  \r\n  if(len <= 0)\r\n  {\r\n    fifoemptymsk = 0x1 << epnum;\r\n    USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;\r\n    \r\n  }\r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_PCD_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd_ex.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_pcd_ex.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   PCD HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the USB Peripheral Controller:\r\n  *           + Extended features functions\r\n  *\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup PCDEx PCDEx\r\n  * @brief PCD Extended HAL module driver\r\n  * @{\r\n  */\r\n#ifdef HAL_PCD_MODULE_ENABLED\r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/* Private macros ------------------------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions\r\n  * @brief    PCDEx control functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                 ##### Extended features functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Update FIFO configuration\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Set Tx FIFO\r\n  * @param  hpcd: PCD handle\r\n  * @param  fifo: The number of Tx fifo\r\n  * @param  size: Fifo size\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)\r\n{\r\n  uint8_t i = 0;\r\n  uint32_t Tx_Offset = 0;\r\n\r\n  /*  TXn min size = 16 words. (n  : Transmit FIFO index)\r\n      When a TxFIFO is not used, the Configuration should be as follows: \r\n          case 1 :  n > m    and Txn is not used    (n,m  : Transmit FIFO indexes)\r\n         --> Txm can use the space allocated for Txn.\r\n         case2  :  n < m    and Txn is not used    (n,m  : Transmit FIFO indexes)\r\n         --> Txn should be configured with the minimum space of 16 words\r\n     The FIFO is used optimally when used TxFIFOs are allocated in the top \r\n         of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.\r\n     When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */\r\n  \r\n  Tx_Offset = hpcd->Instance->GRXFSIZ;\r\n  \r\n  if(fifo == 0)\r\n  {\r\n    hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((uint32_t)size << 16) | Tx_Offset);\r\n  }\r\n  else\r\n  {\r\n    Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;\r\n    for (i = 0; i < (fifo - 1); i++)\r\n    {\r\n      Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);\r\n    }\r\n    \r\n    /* Multiply Tx_Size by 2 to get higher performance */\r\n    hpcd->Instance->DIEPTXF[fifo - 1] = (uint32_t)(((uint32_t)size << 16) | Tx_Offset);\r\n  }\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Set Rx FIFO\r\n  * @param  hpcd: PCD handle\r\n  * @param  size: Size of Rx fifo\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)\r\n{\r\n  hpcd->Instance->GRXFSIZ = size;\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Activate LPM Feature\r\n  * @param  hpcd: PCD handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)\r\n{\r\n  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  \r\n  \r\n  hpcd->lpm_active = ENABLE;\r\n  hpcd->LPM_State = LPM_L0;\r\n  USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;\r\n  USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);\r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  DeActivate LPM feature.\r\n  * @param  hpcd: PCD handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)\r\n{\r\n  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  \r\n  \r\n  hpcd->lpm_active = DISABLE;\r\n  USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;\r\n  USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);\r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Send LPM message to user layer callback.\r\n  * @param  hpcd: PCD handle\r\n  * @param  msg: LPM message\r\n  * @retval HAL status\r\n  */\r\n__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hpcd);\r\n  UNUSED(msg);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_PCDEx_LPM_Callback could be implemented in the user file\r\n   */\t\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_PCD_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_pwr.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   PWR HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the Power Controller (PWR) peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + Peripheral Control functions \r\n  *         \r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup PWR PWR\r\n  * @brief PWR HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_PWR_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @addtogroup PWR_Private_Constants\r\n  * @{\r\n  */\r\n\t\r\n/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask\r\n  * @{\r\n  */     \r\n#define PVD_MODE_IT               ((uint32_t)0x00010000U)\r\n#define PVD_MODE_EVT              ((uint32_t)0x00020000U)\r\n#define PVD_RISING_EDGE           ((uint32_t)0x00000001U)\r\n#define PVD_FALLING_EDGE          ((uint32_t)0x00000002U)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask\r\n  * @{\r\n  */  \r\n#define  PWR_EWUP_MASK                          ((uint32_t)0x00003F00)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup PWR_Exported_Functions PWR Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions \r\n  *  @brief    Initialization and de-initialization functions\r\n  *\r\n@verbatim\r\n ===============================================================================\r\n              ##### Initialization and de-initialization functions #####\r\n ===============================================================================\r\n    [..]\r\n      After reset, the backup domain (RTC registers, RTC backup data \r\n      registers and backup SRAM) is protected against possible unwanted \r\n      write accesses. \r\n      To enable access to the RTC Domain and RTC registers, proceed as follows:\r\n        (+) Enable the Power Controller (PWR) APB1 interface clock using the\r\n            __HAL_RCC_PWR_CLK_ENABLE() macro.\r\n        (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.\r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief Deinitializes the HAL PWR peripheral registers to their default reset values.\r\n  * @retval None\r\n  */\r\nvoid HAL_PWR_DeInit(void)\r\n{\r\n  __HAL_RCC_PWR_FORCE_RESET();\r\n  __HAL_RCC_PWR_RELEASE_RESET();\r\n}\r\n\r\n/**\r\n  * @brief Enables access to the backup domain (RTC registers, RTC \r\n  *         backup data registers and backup SRAM).\r\n  * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the \r\n  *         Backup Domain Access should be kept enabled.\r\n  * @retval None\r\n  */\r\nvoid HAL_PWR_EnableBkUpAccess(void)\r\n{\r\n  /* Enable access to RTC and backup registers */\r\n  SET_BIT(PWR->CR1, PWR_CR1_DBP);\r\n}\r\n\r\n/**\r\n  * @brief Disables access to the backup domain (RTC registers, RTC \r\n  *         backup data registers and backup SRAM).\r\n  * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the \r\n  *         Backup Domain Access should be kept enabled.\r\n  * @retval None\r\n  */\r\nvoid HAL_PWR_DisableBkUpAccess(void)\r\n{\r\n  /* Disable access to RTC and backup registers */\r\n\tCLEAR_BIT(PWR->CR1, PWR_CR1_DBP);\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions \r\n  *  @brief Low Power modes configuration functions \r\n  *\r\n@verbatim\r\n\r\n ===============================================================================\r\n                 ##### Peripheral Control functions #####\r\n ===============================================================================\r\n     \r\n    *** PVD configuration ***\r\n    =========================\r\n    [..]\r\n      (+) The PVD is used to monitor the VDD power supply by comparing it to a \r\n          threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).\r\n      (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower \r\n          than the PVD threshold. This event is internally connected to the EXTI \r\n          line16 and can generate an interrupt if enabled. This is done through\r\n          __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.\r\n      (+) The PVD is stopped in Standby mode.\r\n\r\n    *** Wake-up pin configuration ***\r\n    ================================\r\n    [..]\r\n      (+) Wake-up pin is used to wake up the system from Standby mode. This pin is \r\n          forced in input pull-down configuration and is active on rising edges.\r\n      (+) There are to 6 Wake-up pin in the STM32F7 devices family\r\n\r\n    *** Low Power modes configuration ***\r\n    =====================================\r\n    [..]\r\n      The devices feature 3 low-power modes:\r\n      (+) Sleep mode: Cortex-M7 core stopped, peripherals kept running.\r\n      (+) Stop mode: all clocks are stopped, regulator running, regulator \r\n          in low power mode\r\n      (+) Standby mode: 1.2V domain powered off.\r\n   \r\n   *** Sleep mode ***\r\n   ==================\r\n    [..]\r\n      (+) Entry:\r\n        The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI)\r\n              functions with\r\n          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction\r\n          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction\r\n      \r\n      -@@- The Regulator parameter is not used for the STM32F7 family \r\n              and is kept as parameter just to maintain compatibility with the \r\n              lower power families (STM32L).\r\n      (+) Exit:\r\n        Any peripheral interrupt acknowledged by the nested vectored interrupt \r\n              controller (NVIC) can wake up the device from Sleep mode.\r\n\r\n   *** Stop mode ***\r\n   =================\r\n    [..]\r\n      In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,\r\n      and the HSE RC oscillators are disabled. Internal SRAM and register contents \r\n      are preserved.\r\n      The voltage regulator can be configured either in normal or low-power mode.\r\n      To minimize the consumption In Stop mode, FLASH can be powered off before \r\n      entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.\r\n      It can be switched on again by software after exiting the Stop mode using\r\n      the HAL_PWREx_DisableFlashPowerDown() function. \r\n\r\n      (+) Entry:\r\n         The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON) \r\n             function with:\r\n          (++) Main regulator ON.\r\n          (++) Low Power regulator ON.\r\n      (+) Exit:\r\n        Any EXTI Line (Internal or External) configured in Interrupt/Event mode.\r\n\r\n   *** Standby mode ***\r\n   ====================\r\n    [..]\r\n    (+)\r\n      The Standby mode allows to achieve the lowest power consumption. It is based \r\n      on the Cortex-M7 deep sleep mode, with the voltage regulator disabled. \r\n      The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and \r\n      the HSE oscillator are also switched off. SRAM and register contents are lost \r\n      except for the RTC registers, RTC backup registers, backup SRAM and Standby \r\n      circuitry.\r\n   \r\n      The voltage regulator is OFF.\r\n      \r\n      (++) Entry:\r\n        (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.\r\n      (++) Exit:\r\n        (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC\r\n             wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset.\r\n\r\n   *** Auto-wakeup (AWU) from low-power mode ***\r\n   =============================================\r\n    [..]\r\n    \r\n     (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC \r\n      Wakeup event, a tamper event or a time-stamp event, without depending on \r\n      an external interrupt (Auto-wakeup mode).\r\n\r\n      (+) RTC auto-wakeup (AWU) from the Stop and Standby modes\r\n       \r\n        (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to \r\n              configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.\r\n\r\n        (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it \r\n             is necessary to configure the RTC to detect the tamper or time stamp event using the\r\n                HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.\r\n                  \r\n        (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to\r\n              configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).\r\n  * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration\r\n  *        information for the PVD.\r\n  * @note Refer to the electrical characteristics of your device datasheet for\r\n  *         more details about the voltage threshold corresponding to each \r\n  *         detection level.\r\n  * @retval None\r\n  */\r\nvoid HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));\r\n  assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));\r\n  \r\n  /* Set PLS[7:5] bits according to PVDLevel value */\r\n  MODIFY_REG(PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);\r\n  \r\n  /* Clear any previous config. Keep it clear if no event or IT mode is selected */\r\n  __HAL_PWR_PVD_EXTI_DISABLE_EVENT();\r\n  __HAL_PWR_PVD_EXTI_DISABLE_IT();\r\n  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\r\n  __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \r\n\r\n  /* Configure interrupt mode */\r\n  if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)\r\n  {\r\n    __HAL_PWR_PVD_EXTI_ENABLE_IT();\r\n  }\r\n  \r\n  /* Configure event mode */\r\n  if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)\r\n  {\r\n    __HAL_PWR_PVD_EXTI_ENABLE_EVENT();\r\n  }\r\n  \r\n  /* Configure the edge */\r\n  if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)\r\n  {\r\n    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\r\n  }\r\n  \r\n  if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)\r\n  {\r\n    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Enables the Power Voltage Detector(PVD).\r\n  * @retval None\r\n  */\r\nvoid HAL_PWR_EnablePVD(void)\r\n{\r\n  /* Enable the power voltage detector */\r\n\tSET_BIT(PWR->CR1, PWR_CR1_PVDE);\r\n}\r\n\r\n/**\r\n  * @brief Disables the Power Voltage Detector(PVD).\r\n  * @retval None\r\n  */\r\nvoid HAL_PWR_DisablePVD(void)\r\n{\r\n  /* Disable the power voltage detector */\r\n\tCLEAR_BIT(PWR->CR1, PWR_CR1_PVDE);\r\n}\r\n\r\n/**\r\n  * @brief Enable the WakeUp PINx functionality.\r\n  * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.\r\n  *         This parameter can be one of the following legacy values, which sets the default polarity: \r\n  *         detection on high level (rising edge):\r\n  *           @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6 \r\n  *         or one of the following value where the user can explicitly states the enabled pin and\r\n  *         the chosen polarity  \r\n  *           @arg PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW \r\n  *           @arg PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW \r\n  *           @arg PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW \r\n  *           @arg PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW\r\n  *           @arg PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW \r\n  *           @arg PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW \r\n  * @note  PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.               \r\n  * @retval None\r\n  */\r\nvoid HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)\r\n{\r\n  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));\r\n  \r\n  /* Enable wake-up pin */\r\n  SET_BIT(PWR->CSR2, (PWR_EWUP_MASK & WakeUpPinPolarity));\r\n\t\r\n  /* Specifies the Wake-Up pin polarity for the event detection\r\n    (rising or falling edge) */\r\n  MODIFY_REG(PWR->CR2, (PWR_EWUP_MASK & WakeUpPinPolarity), (WakeUpPinPolarity >> 0x06));\r\n}\r\n\r\n/**\r\n  * @brief Disables the WakeUp PINx functionality.\r\n  * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.\r\n  *         This parameter can be one of the following values:\r\n  *           @arg PWR_WAKEUP_PIN1\r\n  *           @arg PWR_WAKEUP_PIN2\r\n  *           @arg PWR_WAKEUP_PIN3\r\n  *           @arg PWR_WAKEUP_PIN4\r\n  *           @arg PWR_WAKEUP_PIN5\r\n  *           @arg PWR_WAKEUP_PIN6 \r\n  * @retval None\r\n  */\r\nvoid HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)\r\n{\r\n  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));\r\n\r\n  CLEAR_BIT(PWR->CSR2, WakeUpPinx);\r\n}\r\n  \r\n/**\r\n  * @brief Enters Sleep mode.\r\n  *   \r\n  * @note In Sleep mode, all I/O pins keep the same state as in Run mode.\r\n  * \r\n  * @note In Sleep mode, the systick is stopped to avoid exit from this mode with\r\n  *       systick interrupt when used as time base for Timeout \r\n  *                \r\n  * @param Regulator: Specifies the regulator state in SLEEP mode.\r\n  *            This parameter can be one of the following values:\r\n  *            @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON\r\n  *            @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON\r\n  * @note This parameter is not used for the STM32F7 family and is kept as parameter\r\n  *       just to maintain compatibility with the lower power families.\r\n  * @param SLEEPEntry: Specifies if SLEEP mode in entered with WFI or WFE instruction.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction\r\n  *            @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction\r\n  * @retval None\r\n  */\r\nvoid HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_PWR_REGULATOR(Regulator));\r\n  assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));\r\n\r\n  /* Clear SLEEPDEEP bit of Cortex System Control Register */\r\n  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\r\n\r\n  /* Select SLEEP mode entry -------------------------------------------------*/\r\n  if(SLEEPEntry == PWR_SLEEPENTRY_WFI)\r\n  {   \r\n    /* Request Wait For Interrupt */\r\n    __WFI();\r\n  }\r\n  else\r\n  {\r\n    /* Request Wait For Event */\r\n    __SEV();\r\n    __WFE();\r\n    __WFE();\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Enters Stop mode. \r\n  * @note In Stop mode, all I/O pins keep the same state as in Run mode.\r\n  * @note When exiting Stop mode by issuing an interrupt or a wakeup event, \r\n  *         the HSI RC oscillator is selected as system clock.\r\n  * @note When the voltage regulator operates in low power mode, an additional \r\n  *         startup delay is incurred when waking up from Stop mode. \r\n  *         By keeping the internal regulator ON during Stop mode, the consumption \r\n  *         is higher although the startup time is reduced.    \r\n  * @param Regulator: Specifies the regulator state in Stop mode.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON\r\n  *            @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON\r\n  * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction\r\n  *            @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction\r\n  * @retval None\r\n  */\r\nvoid HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)\r\n{\r\n  uint32_t tmpreg = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_PWR_REGULATOR(Regulator));\r\n  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));\r\n  \r\n  /* Select the regulator state in Stop mode ---------------------------------*/\r\n  tmpreg = PWR->CR1;\r\n  /* Clear PDDS and LPDS bits */\r\n  tmpreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS);\r\n  \r\n  /* Set LPDS, MRLVDS and LPLVDS bits according to Regulator value */\r\n  tmpreg |= Regulator;\r\n  \r\n  /* Store the new value */\r\n  PWR->CR1 = tmpreg;\r\n  \r\n  /* Set SLEEPDEEP bit of Cortex System Control Register */\r\n  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r\n  \r\n  /* Select Stop mode entry --------------------------------------------------*/\r\n  if(STOPEntry == PWR_STOPENTRY_WFI)\r\n  {   \r\n    /* Request Wait For Interrupt */\r\n    __WFI();\r\n  }\r\n  else\r\n  {\r\n    /* Request Wait For Event */\r\n    __SEV();\r\n    __WFE();\r\n    __WFE();\r\n  }\r\n  /* Reset SLEEPDEEP bit of Cortex System Control Register */\r\n  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);  \r\n}\r\n\r\n/**\r\n  * @brief Enters Standby mode.\r\n  * @note In Standby mode, all I/O pins are high impedance except for:\r\n  *          - Reset pad (still available) \r\n  *          - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC \r\n  *            Alarm out, or RTC clock calibration out.\r\n  *          - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.  \r\n  *          - WKUP pins if enabled.       \r\n  * @retval None\r\n  */\r\nvoid HAL_PWR_EnterSTANDBYMode(void)\r\n{\r\n  /* Select Standby mode */\r\n  PWR->CR1 |= PWR_CR1_PDDS;\r\n  \r\n  /* Set SLEEPDEEP bit of Cortex System Control Register */\r\n  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r\n  \r\n  /* This option is used to ensure that store operations are completed */\r\n#if defined ( __CC_ARM)\r\n  __force_stores();\r\n#endif\r\n  /* Request Wait For Interrupt */\r\n  __WFI();\r\n}\r\n\r\n/**\r\n  * @brief This function handles the PWR PVD interrupt request.\r\n  * @note This API should be called under the PVD_IRQHandler().\r\n  * @retval None\r\n  */\r\nvoid HAL_PWR_PVD_IRQHandler(void)\r\n{\r\n  /* Check PWR Exti flag */\r\n  if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)\r\n  {\r\n    /* PWR PVD interrupt user callback */\r\n    HAL_PWR_PVDCallback();\r\n    \r\n    /* Clear PWR Exti pending bit */\r\n    __HAL_PWR_PVD_EXTI_CLEAR_FLAG();\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  PWR PVD interrupt callback\r\n  * @retval None\r\n  */\r\n__weak void HAL_PWR_PVDCallback(void)\r\n{\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_PWR_PVDCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. \r\n  * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor \r\n  *       re-enters SLEEP mode when an interruption handling is over.\r\n  *       Setting this bit is useful when the processor is expected to run only on\r\n  *       interruptions handling.         \r\n  * @retval None\r\n  */\r\nvoid HAL_PWR_EnableSleepOnExit(void)\r\n{\r\n  /* Set SLEEPONEXIT bit of Cortex System Control Register */\r\n  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));\r\n}\r\n\r\n/**\r\n  * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. \r\n  * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor \r\n  *       re-enters SLEEP mode when an interruption handling is over.          \r\n  * @retval None\r\n  */\r\nvoid HAL_PWR_DisableSleepOnExit(void)\r\n{\r\n  /* Clear SLEEPONEXIT bit of Cortex System Control Register */\r\n  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));\r\n}\r\n\r\n/**\r\n  * @brief Enables CORTEX M4 SEVONPEND bit. \r\n  * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes \r\n  *       WFE to wake up when an interrupt moves from inactive to pended.\r\n  * @retval None\r\n  */\r\nvoid HAL_PWR_EnableSEVOnPend(void)\r\n{\r\n  /* Set SEVONPEND bit of Cortex System Control Register */\r\n  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));\r\n}\r\n\r\n/**\r\n  * @brief Disables CORTEX M4 SEVONPEND bit. \r\n  * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes \r\n  *       WFE to wake up when an interrupt moves from inactive to pended.         \r\n  * @retval None\r\n  */\r\nvoid HAL_PWR_DisableSEVOnPend(void)\r\n{\r\n  /* Clear SEVONPEND bit of Cortex System Control Register */\r\n  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_PWR_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_pwr_ex.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Extended PWR HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of PWR extension peripheral:           \r\n  *           + Peripheral Extended features functions\r\n  *         \r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup PWREx PWREx\r\n  * @brief PWR HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_PWR_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @addtogroup PWREx_Private_Constants\r\n  * @{\r\n  */    \r\n#define PWR_OVERDRIVE_TIMEOUT_VALUE  1000\r\n#define PWR_UDERDRIVE_TIMEOUT_VALUE  1000\r\n#define PWR_BKPREG_TIMEOUT_VALUE     1000\r\n#define PWR_VOSRDY_TIMEOUT_VALUE     1000\r\n/**\r\n  * @}\r\n  */\r\n    \r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup PWREx_Exported_Functions PWREx Exported Functions\r\n  *  @{\r\n  */\r\n\r\n/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions \r\n  *  @brief Peripheral Extended features functions \r\n  *\r\n@verbatim   \r\n\r\n ===============================================================================\r\n                 ##### Peripheral extended features functions #####\r\n ===============================================================================\r\n\r\n    *** Main and Backup Regulators configuration ***\r\n    ================================================\r\n    [..] \r\n      (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from \r\n          the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is \r\n          retained even in Standby or VBAT mode when the low power backup regulator\r\n          is enabled. It can be considered as an internal EEPROM when VBAT is \r\n          always present. You can use the HAL_PWREx_EnableBkUpReg() function to \r\n          enable the low power backup regulator. \r\n\r\n      (+) When the backup domain is supplied by VDD (analog switch connected to VDD) \r\n          the backup SRAM is powered from VDD which replaces the VBAT power supply to \r\n          save battery life.\r\n\r\n      (+) The backup SRAM is not mass erased by a tamper event. It is read \r\n          protected to prevent confidential data, such as cryptographic private \r\n          key, from being accessed. The backup SRAM can be erased only through \r\n          the Flash interface when a protection level change from level 1 to \r\n          level 0 is requested. \r\n      -@- Refer to the description of Read protection (RDP) in the Flash \r\n          programming manual.\r\n\r\n      (+) The main internal regulator can be configured to have a tradeoff between \r\n          performance and power consumption when the device does not operate at \r\n          the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG() \r\n          macro which configure VOS bit in PWR_CR register\r\n          \r\n        Refer to the product datasheets for more details.\r\n\r\n    *** FLASH Power Down configuration ****\r\n    =======================================\r\n    [..] \r\n      (+) By setting the FPDS bit in the PWR_CR register by using the \r\n          HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power \r\n          down mode when the device enters Stop mode. When the Flash memory \r\n          is in power down mode, an additional startup delay is incurred when \r\n          waking up from Stop mode.\r\n\r\n    *** Over-Drive and Under-Drive configuration ****\r\n    =================================================\r\n    [..]         \r\n       (+) In Run mode: the main regulator has 2 operating modes available:\r\n        (++) Normal mode: The CPU and core logic operate at maximum frequency at a given \r\n             voltage scaling (scale 1, scale 2 or scale 3)\r\n        (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a \r\n            higher frequency than the normal mode for a given voltage scaling (scale 1,  \r\n            scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and\r\n            disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow \r\n            the sequence described in Reference manual.\r\n             \r\n       (+) In Stop mode: the main regulator or low power regulator supplies a low power \r\n           voltage to the 1.2V domain, thus preserving the content of registers \r\n           and internal SRAM. 2 operating modes are available:\r\n         (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only \r\n              available when the main regulator or the low power regulator is used in Scale 3 or \r\n              low voltage mode.\r\n         (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only\r\n              available when the main regulator or the low power regulator is in low voltage mode.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief Enables the Backup Regulator.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)\r\n{\r\n  uint32_t tickstart = 0;\r\n\r\n  /* Enable Backup regulator */\r\n  PWR->CSR1 |= PWR_CSR1_BRE;\r\n    \r\n  /* Workaround for the following hardware bug: */\r\n  /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */\r\n  PWR->CSR1 |= PWR_CSR1_EIWUP;\r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Wait till Backup regulator ready flag is set */  \r\n  while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET)\r\n  {\r\n    if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    } \r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Disables the Backup Regulator.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Disable Backup regulator */\r\n  PWR->CSR1 &= (uint32_t)~((uint32_t)PWR_CSR1_BRE);\r\n  \r\n  /* Workaround for the following hardware bug: */\r\n  /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */\r\n  PWR->CSR1 |= PWR_CSR1_EIWUP;\r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Wait till Backup regulator ready flag is set */  \r\n  while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)\r\n  {\r\n    if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    } \r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Enables the Flash Power Down in Stop mode.\r\n  * @retval None\r\n  */\r\nvoid HAL_PWREx_EnableFlashPowerDown(void)\r\n{\r\n  /* Enable the Flash Power Down */\r\n  PWR->CR1 |= PWR_CR1_FPDS;\r\n}\r\n\r\n/**\r\n  * @brief Disables the Flash Power Down in Stop mode.\r\n  * @retval None\r\n  */\r\nvoid HAL_PWREx_DisableFlashPowerDown(void)\r\n{\r\n  /* Disable the Flash Power Down */\r\n  PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_FPDS);\r\n}\r\n\r\n/**\r\n  * @brief Enables Main Regulator low voltage mode.\r\n  * @retval None\r\n  */\r\nvoid HAL_PWREx_EnableMainRegulatorLowVoltage(void)\r\n{\r\n  /* Enable Main regulator low voltage */\r\n  PWR->CR1 |= PWR_CR1_MRUDS;\r\n}\r\n\r\n/**\r\n  * @brief Disables Main Regulator low voltage mode.\r\n  * @retval None\r\n  */\r\nvoid HAL_PWREx_DisableMainRegulatorLowVoltage(void)\r\n{  \r\n  /* Disable Main regulator low voltage */\r\n  PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_MRUDS);\r\n}\r\n\r\n/**\r\n  * @brief Enables Low Power Regulator low voltage mode.\r\n  * @retval None\r\n  */\r\nvoid HAL_PWREx_EnableLowRegulatorLowVoltage(void)\r\n{\r\n  /* Enable low power regulator */\r\n  PWR->CR1 |= PWR_CR1_LPUDS;\r\n}\r\n\r\n/**\r\n  * @brief Disables Low Power Regulator low voltage mode.\r\n  * @retval None\r\n  */\r\nvoid HAL_PWREx_DisableLowRegulatorLowVoltage(void)\r\n{\r\n  /* Disable low power regulator */\r\n  PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_LPUDS);\r\n}\r\n\r\n/**\r\n  * @brief  Activates the Over-Drive mode.\r\n  * @note   This mode allows the CPU and the core logic to operate at a higher frequency\r\n  *         than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).   \r\n  * @note   It is recommended to enter or exit Over-drive mode when the application is not running \r\n  *         critical tasks and when the system clock source is either HSI or HSE. \r\n  *         During the Over-drive switch activation, no peripheral clocks should be enabled.   \r\n  *         The peripheral clocks must be enabled once the Over-drive mode is activated.   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)\r\n{\r\n  uint32_t tickstart = 0;\r\n\r\n  __HAL_RCC_PWR_CLK_ENABLE();\r\n  \r\n  /* Enable the Over-drive to extend the clock frequency to 216 MHz */\r\n  __HAL_PWR_OVERDRIVE_ENABLE();\r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))\r\n  {\r\n    if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  \r\n  /* Enable the Over-drive switch */\r\n  __HAL_PWR_OVERDRIVESWITCHING_ENABLE();\r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))\r\n  {\r\n    if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  } \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Deactivates the Over-Drive mode.\r\n  * @note   This mode allows the CPU and the core logic to operate at a higher frequency\r\n  *         than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).    \r\n  * @note   It is recommended to enter or exit Over-drive mode when the application is not running \r\n  *         critical tasks and when the system clock source is either HSI or HSE. \r\n  *         During the Over-drive switch activation, no peripheral clocks should be enabled.   \r\n  *         The peripheral clocks must be enabled once the Over-drive mode is activated.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  __HAL_RCC_PWR_CLK_ENABLE();\r\n    \r\n  /* Disable the Over-drive switch */\r\n  __HAL_PWR_OVERDRIVESWITCHING_DISABLE();\r\n  \r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n \r\n  while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))\r\n  {\r\n    if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  } \r\n  \r\n  /* Disable the Over-drive */\r\n  __HAL_PWR_OVERDRIVE_DISABLE();\r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))\r\n  {\r\n    if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Enters in Under-Drive STOP mode.\r\n  * \r\n  * @note    This mode can be selected only when the Under-Drive is already active \r\n  *   \r\n  * @note    This mode is enabled only with STOP low power mode.\r\n  *          In this mode, the 1.2V domain is preserved in reduced leakage mode. This \r\n  *          mode is only available when the main regulator or the low power regulator \r\n  *          is in low voltage mode\r\n  *        \r\n  * @note   If the Under-drive mode was enabled, it is automatically disabled after \r\n  *         exiting Stop mode. \r\n  *         When the voltage regulator operates in Under-drive mode, an additional  \r\n  *         startup delay is induced when waking up from Stop mode.\r\n  *                    \r\n  * @note   In Stop mode, all I/O pins keep the same state as in Run mode.\r\n  *   \r\n  * @note   When exiting Stop mode by issuing an interrupt or a wakeup event, \r\n  *         the HSI RC oscillator is selected as system clock.\r\n  *           \r\n  * @note   When the voltage regulator operates in low power mode, an additional \r\n  *         startup delay is incurred when waking up from Stop mode. \r\n  *         By keeping the internal regulator ON during Stop mode, the consumption \r\n  *         is higher although the startup time is reduced.\r\n  *     \r\n  * @param  Regulator: specifies the regulator state in STOP mode.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg PWR_MAINREGULATOR_UNDERDRIVE_ON:  Main Regulator in under-drive mode \r\n  *                 and Flash memory in power-down when the device is in Stop under-drive mode\r\n  *            @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON:  Low Power Regulator in under-drive mode \r\n  *                and Flash memory in power-down when the device is in Stop under-drive mode\r\n  * @param  STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction\r\n  *            @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction\r\n  * @retval None\r\n  */\r\nHAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry)\r\n{\r\n  uint32_t tempreg = 0;\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator));\r\n  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));\r\n  \r\n  /* Enable Power ctrl clock */\r\n  __HAL_RCC_PWR_CLK_ENABLE();\r\n  /* Enable the Under-drive Mode ---------------------------------------------*/\r\n  /* Clear Under-drive flag */\r\n  __HAL_PWR_CLEAR_ODRUDR_FLAG();\r\n  \r\n  /* Enable the Under-drive */ \r\n  __HAL_PWR_UNDERDRIVE_ENABLE();\r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Wait for UnderDrive mode is ready */\r\n  while(__HAL_PWR_GET_FLAG(PWR_FLAG_UDRDY))\r\n  {\r\n    if((HAL_GetTick() - tickstart ) > PWR_UDERDRIVE_TIMEOUT_VALUE)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  \r\n  /* Select the regulator state in STOP mode ---------------------------------*/\r\n  tempreg = PWR->CR1;\r\n  /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */\r\n  tempreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS);\r\n  \r\n  /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */\r\n  tempreg |= Regulator;\r\n  \r\n  /* Store the new value */\r\n  PWR->CR1 = tempreg;\r\n  \r\n  /* Set SLEEPDEEP bit of Cortex System Control Register */\r\n  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r\n  \r\n  /* Select STOP mode entry --------------------------------------------------*/\r\n  if(STOPEntry == PWR_SLEEPENTRY_WFI)\r\n  {   \r\n    /* Request Wait For Interrupt */\r\n    __WFI();\r\n  }\r\n  else\r\n  {\r\n    /* Request Wait For Event */\r\n    __WFE();\r\n  }\r\n  /* Reset SLEEPDEEP bit of Cortex System Control Register */\r\n  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);\r\n\r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief Returns Voltage Scaling Range.\r\n  * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or \r\n  *            PWR_REGULATOR_VOLTAGE_SCALE3)PWR_REGULATOR_VOLTAGE_SCALE1\r\n  */  \r\nuint32_t HAL_PWREx_GetVoltageRange(void)\r\n{\r\n  return  (PWR->CR1 & PWR_CR1_VOS);\r\n}\r\n\r\n/**\r\n  * @brief Configures the main internal regulator output voltage.\r\n  * @param  VoltageScaling: specifies the regulator output voltage to achieve\r\n  *         a tradeoff between performance and power consumption.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,\r\n  *                                                typical output voltage at 1.4 V,  \r\n  *                                                system frequency up to 216 MHz.\r\n  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,\r\n  *                                                typical output voltage at 1.2 V,                \r\n  *                                                system frequency up to 180 MHz.\r\n  *            @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 2 mode,\r\n  *                                                typical output voltage at 1.00 V,                \r\n  *                                                system frequency up to 151 MHz.\r\n  * @note To update the system clock frequency(SYSCLK):\r\n  *        - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig().\r\n  *        - Call the HAL_RCC_OscConfig() to configure the PLL.\r\n  *        - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale.\r\n  *        - Set the new system clock frequency using the HAL_RCC_ClockConfig().\r\n  * @note The scale can be modified only when the HSI or HSE clock source is selected \r\n  *        as system clock source, otherwise the API returns HAL_ERROR.  \r\n  * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits\r\n  *       value in the PWR_CR1 register are not taken in account.\r\n  * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2.\r\n  * @note The new voltage scale is active only when the PLL is ON.  \r\n  * @retval HAL Status\r\n  */\r\nHAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)\r\n{\r\n  uint32_t tickstart = 0;\r\n\r\n  assert_param(IS_PWR_REGULATOR_VOLTAGE(VoltageScaling));\r\n\r\n  /* Enable Power ctrl clock */\r\n  __HAL_RCC_PWR_CLK_ENABLE();\r\n\r\n  /* Check if the PLL is used as system clock or not */\r\n  if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)\r\n  {\r\n    /* Disable the main PLL */\r\n    __HAL_RCC_PLL_DISABLE();\r\n    \r\n    /* Get Start Tick */\r\n    tickstart = HAL_GetTick();    \r\n    /* Wait till PLL is disabled */  \r\n    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n    \r\n    /* Set Range */\r\n    __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);\r\n    \r\n    /* Enable the main PLL */\r\n    __HAL_RCC_PLL_ENABLE();\r\n    \r\n    /* Get Start Tick */\r\n    tickstart = HAL_GetTick();\r\n    /* Wait till PLL is ready */  \r\n    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      } \r\n    }\r\n    \r\n    /* Get Start Tick */\r\n    tickstart = HAL_GetTick();\r\n    while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      } \r\n    }\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_PWR_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_qspi.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   QSPI HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the QuadSPI interface (QSPI).\r\n  *           + Initialization and de-initialization functions\r\n  *           + Indirect functional mode management\r\n  *           + Memory-mapped functional mode management\r\n  *           + Auto-polling functional mode management\r\n  *           + Interrupts and flags management\r\n  *           + DMA channel configuration for indirect functional mode\r\n  *           + Errors management and abort functionality\r\n  *\r\n  *\r\n  @verbatim\r\n ===============================================================================\r\n                        ##### How to use this driver #####\r\n ===============================================================================\r\n  [..]\r\n    *** Initialization ***\r\n    ======================\r\n    [..]\r\n      (#) As prerequisite, fill in the HAL_QSPI_MspInit() :\r\n        (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().\r\n        (++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().\r\n        (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().\r\n        (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().\r\n        (++) If interrupt mode is used, enable and configure QuadSPI global\r\n            interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().\r\n        (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel \r\n            with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(), \r\n            link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure \r\n            DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().\r\n      (#) Configure the flash size, the clock prescaler, the fifo threshold, the\r\n          clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.\r\n\r\n    *** Indirect functional mode ***\r\n    ================================\r\n    [..]\r\n      (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT() \r\n          functions :\r\n         (++) Instruction phase : the mode used and if present the instruction opcode.\r\n         (++) Address phase : the mode used and if present the size and the address value.\r\n         (++) Alternate-bytes phase : the mode used and if present the size and the alternate \r\n             bytes values.\r\n         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).\r\n         (++) Data phase : the mode used and if present the number of bytes.\r\n         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay \r\n             if activated.\r\n         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.\r\n      (#) If no data is required for the command, it is sent directly to the memory :\r\n         (++) In polling mode, the output of the function is done when the transfer is complete.\r\n         (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.\r\n      (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or \r\n          HAL_QSPI_Transmit_IT() after the command configuration :\r\n         (++) In polling mode, the output of the function is done when the transfer is complete.\r\n         (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold \r\n             is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.\r\n         (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and \r\n             HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.\r\n      (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or \r\n          HAL_QSPI_Receive_IT() after the command configuration :\r\n         (++) In polling mode, the output of the function is done when the transfer is complete.\r\n         (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold \r\n             is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.\r\n         (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and \r\n             HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.\r\n\r\n    *** Auto-polling functional mode ***\r\n    ====================================\r\n    [..]\r\n      (#) Configure the command sequence and the auto-polling functional mode using the \r\n          HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :\r\n         (++) Instruction phase : the mode used and if present the instruction opcode.\r\n         (++) Address phase : the mode used and if present the size and the address value.\r\n         (++) Alternate-bytes phase : the mode used and if present the size and the alternate \r\n             bytes values.\r\n         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).\r\n         (++) Data phase : the mode used.\r\n         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay \r\n             if activated.\r\n         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.\r\n         (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),\r\n             the polling interval and the automatic stop activation.\r\n      (#) After the configuration :\r\n         (++) In polling mode, the output of the function is done when the status match is reached. The\r\n             automatic stop is activated to avoid an infinite loop.\r\n         (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.\r\n\r\n    *** Memory-mapped functional mode ***\r\n    =====================================\r\n    [..]\r\n      (#) Configure the command sequence and the memory-mapped functional mode using the \r\n          HAL_QSPI_MemoryMapped() functions :\r\n         (++) Instruction phase : the mode used and if present the instruction opcode.\r\n         (++) Address phase : the mode used and the size.\r\n         (++) Alternate-bytes phase : the mode used and if present the size and the alternate \r\n             bytes values.\r\n         (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).\r\n         (++) Data phase : the mode used.\r\n         (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay \r\n             if activated.\r\n         (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.\r\n         (++) The timeout activation and the timeout period.\r\n      (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on \r\n          the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.\r\n\r\n    *** Errors management and abort functionality ***\r\n    ==================================================\r\n    [..]\r\n      (#) HAL_QSPI_GetError() function gives the error raised during the last operation.\r\n      (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and \r\n          flushes the fifo :\r\n         (++) In polling mode, the output of the function is done when the transfer \r\n              complete bit is set and the busy bit cleared.\r\n         (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when \r\n              the transfer complete bi is set.\r\n\r\n    *** Control functions ***\r\n    =========================\r\n    [..]\r\n      (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.\r\n      (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.\r\n      (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.\r\n      (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold \r\n\r\n    *** Workarounds linked to Silicon Limitation ***\r\n    ====================================================\r\n    [..]\r\n      (#) Workarounds Implemented inside HAL Driver\r\n         (++) Extra data written in the FIFO at the end of a read transfer\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************  \r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup QSPI QSPI\r\n  * @brief HAL QSPI module driver\r\n  * @{\r\n  */\r\n#ifdef HAL_QSPI_MODULE_ENABLED\r\n    \r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @addtogroup QSPI_Private_Constants \r\n  * @{\r\n  */\r\n#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000U)          /*!<Indirect write mode*/\r\n#define QSPI_FUNCTIONAL_MODE_INDIRECT_READ  ((uint32_t)QUADSPI_CCR_FMODE_0) /*!<Indirect read mode*/\r\n#define QSPI_FUNCTIONAL_MODE_AUTO_POLLING   ((uint32_t)QUADSPI_CCR_FMODE_1) /*!<Automatic polling mode*/\r\n#define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED  ((uint32_t)QUADSPI_CCR_FMODE)   /*!<Memory-mapped mode*/\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Private macro -------------------------------------------------------------*/\r\n/** @addtogroup QSPI_Private_Macros QSPI Private Macros\r\n  * @{\r\n  */\r\n#define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \\\r\n                                       ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ)  || \\\r\n                                       ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING)   || \\\r\n                                       ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))\r\n/**\r\n  * @}\r\n  */\r\n                                         \r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/** @addtogroup QSPI_Private_Functions QSPI Private Functions\r\n  * @{\r\n  */\r\nstatic void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);\r\nstatic void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);\r\nstatic void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);\r\nstatic void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);\r\nstatic void QSPI_DMAError(DMA_HandleTypeDef *hdma); \r\nstatic void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma);\r\nstatic HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t tickstart, uint32_t Timeout);\r\nstatic void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode);\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Exported functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup QSPI_Exported_Functions QSPI Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions \r\n  *  @brief    Initialization and Configuration functions \r\n  *\r\n@verbatim    \r\n===============================================================================\r\n            ##### Initialization and Configuration functions #####\r\n ===============================================================================\r\n    [..]\r\n    This subsection provides a set of functions allowing to :\r\n      (+) Initialize the QuadSPI.\r\n      (+) De-initialize the QuadSPI.\r\n      \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief Initializes the QSPI mode according to the specified parameters\r\n  *        in the QSPI_InitTypeDef and creates the associated handle.\r\n  * @param hqspi: qspi handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)\r\n{\r\n  HAL_StatusTypeDef status = HAL_ERROR;\r\n  uint32_t tickstart = HAL_GetTick();\r\n  \r\n  /* Check the QSPI handle allocation */\r\n  if(hqspi == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));\r\n  assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));\r\n  assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));\r\n  assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));\r\n  assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));\r\n  assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));\r\n  assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));\r\n  assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));\r\n\r\n  if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )\r\n  {\r\n    assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));\r\n  }\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hqspi);\r\n    \r\n  if(hqspi->State == HAL_QSPI_STATE_RESET)\r\n  { \r\n    /* Allocate lock resource and initialize it */\r\n    hqspi->Lock = HAL_UNLOCKED;\r\n     \r\n    /* Init the low level hardware : GPIO, CLOCK */\r\n    HAL_QSPI_MspInit(hqspi);\r\n             \r\n    /* Configure the default timeout for the QSPI memory access */\r\n    HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);\r\n  }\r\n  \r\n  /* Configure QSPI FIFO Threshold */\r\n  MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, ((hqspi->Init.FifoThreshold - 1) << 8));\r\n\r\n  /* Wait till BUSY flag reset */\r\n  status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);\r\n\r\n  if(status == HAL_OK)\r\n  {\r\n                \r\n    /* Configure QSPI Clock Prescaler and Sample Shift */\r\n    MODIFY_REG(hqspi->Instance->CR,(QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM), ((hqspi->Init.ClockPrescaler << 24)| hqspi->Init.SampleShifting | hqspi->Init.FlashID| hqspi->Init.DualFlash ));\r\n        \r\n    /* Configure QSPI Flash Size, CS High Time and Clock Mode */\r\n    MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE), \r\n               ((hqspi->Init.FlashSize << 16) | hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));\r\n    \r\n    /* Enable the QSPI peripheral */\r\n    __HAL_QSPI_ENABLE(hqspi);\r\n  \r\n    /* Set QSPI error code to none */\r\n    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;  \r\n\r\n    /* Initialize the QSPI state */\r\n    hqspi->State = HAL_QSPI_STATE_READY;\r\n  }\r\n  \r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hqspi);\r\n\r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief DeInitializes the QSPI peripheral \r\n  * @param hqspi: qspi handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)\r\n{\r\n  /* Check the QSPI handle allocation */\r\n  if(hqspi == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hqspi);\r\n\r\n  /* Disable the QSPI Peripheral Clock */\r\n  __HAL_QSPI_DISABLE(hqspi);\r\n\r\n  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */\r\n  HAL_QSPI_MspDeInit(hqspi);\r\n\r\n  /* Set QSPI error code to none */\r\n  hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r\n\r\n  /* Initialize the QSPI state */\r\n  hqspi->State = HAL_QSPI_STATE_RESET;\r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hqspi);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief QSPI MSP Init\r\n  * @param hqspi: QSPI handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hqspi);\r\n  \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_QSPI_MspInit can be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief QSPI MSP DeInit\r\n  * @param hqspi: QSPI handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hqspi);\r\n  \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_QSPI_MspDeInit can be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup QSPI_Exported_Functions_Group2 IO operation functions \r\n  *  @brief QSPI Transmit/Receive functions \r\n  *\r\n@verbatim   \r\n ===============================================================================\r\n                      ##### IO operation functions #####\r\n ===============================================================================\r\n       [..]\r\n    This subsection provides a set of functions allowing to :\r\n      (+) Handle the interrupts.\r\n      (+) Handle the command sequence.\r\n      (+) Transmit data in blocking, interrupt or DMA mode.\r\n      (+) Receive data in blocking, interrupt or DMA mode.\r\n      (+) Manage the auto-polling functional mode.\r\n      (+) Manage the memory-mapped functional mode.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief This function handles QSPI interrupt request.\r\n  * @param hqspi: QSPI handle\r\n  * @retval None.\r\n  */\r\nvoid HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)\r\n{\r\n  __IO uint32_t *data_reg;\r\n  uint32_t flag = READ_REG(hqspi->Instance->SR);\r\n  uint32_t itsource = READ_REG(hqspi->Instance->CR);\r\n\r\n  /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/\r\n  if(((flag & QSPI_FLAG_FT)!= RESET) && ((itsource & QSPI_IT_FT)!= RESET))\r\n  {\r\n    data_reg = &hqspi->Instance->DR;\r\n\r\n    if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)\r\n    {\r\n      /* Transmission process */\r\n      while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)\r\n      {\r\n        if (hqspi->TxXferCount > 0)\r\n        {\r\n          /* Fill the FIFO until it is full */\r\n          *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;\r\n          hqspi->TxXferCount--;\r\n        }\r\n        else\r\n        {\r\n          /* No more data available for the transfer */\r\n          /* Disable the QSPI FIFO Threshold Interrupt */\r\n          __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);\r\n          break;\r\n        }\r\n      }\r\n    }\r\n    else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)\r\n    {\r\n      /* Receiving Process */\r\n      while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)\r\n      {\r\n        if (hqspi->RxXferCount > 0)\r\n        {\r\n          /* Read the FIFO until it is empty */\r\n          *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;\r\n          hqspi->RxXferCount--;\r\n        }\r\n        else\r\n        {\r\n          /* All data have been received for the transfer */\r\n          /* Disable the QSPI FIFO Threshold Interrupt */\r\n          __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);\r\n          break;\r\n        }\r\n      }\r\n    }\r\n    \r\n    /* FIFO Threshold callback */\r\n    HAL_QSPI_FifoThresholdCallback(hqspi);\r\n  }\r\n\r\n  /* QSPI Transfer Complete interrupt occurred -------------------------------*/\r\n  else if(((flag & QSPI_FLAG_TC)!= RESET) && ((itsource & QSPI_IT_TC)!= RESET))\r\n  {\r\n    /* Clear interrupt */\r\n    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);\r\n\r\n    /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */\r\n    __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);\r\n    \r\n    /* Transfer complete callback */\r\n    if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)\r\n    {\r\n      if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)\r\n      {\r\n        /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */\r\n        CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r\n        \r\n        /* Disable the DMA channel */\r\n        __HAL_DMA_DISABLE(hqspi->hdma);\r\n      }\r\n\r\n#if defined(QSPI1_V1_0)\r\n/* Clear Busy bit */\r\n      HAL_QSPI_Abort_IT(hqspi);\r\n#endif\r\n      \r\n      /* Change state of QSPI */\r\n      hqspi->State = HAL_QSPI_STATE_READY;\r\n\r\n      /* TX Complete callback */\r\n      HAL_QSPI_TxCpltCallback(hqspi);\r\n    }\r\n    else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)\r\n    {\r\n      if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)\r\n      {\r\n        /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */\r\n        CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r\n        \r\n        /* Disable the DMA channel */\r\n        __HAL_DMA_DISABLE(hqspi->hdma);\r\n      }\r\n      else\r\n      {\r\n        data_reg = &hqspi->Instance->DR;\r\n        while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0)\r\n        {\r\n          if (hqspi->RxXferCount > 0)\r\n          {\r\n            /* Read the last data received in the FIFO until it is empty */\r\n            *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;\r\n            hqspi->RxXferCount--;\r\n          }\r\n          else\r\n          {\r\n            /* All data have been received for the transfer */\r\n            break;\r\n          }\r\n        }\r\n      }\r\n#if defined(QSPI1_V1_0)\r\n      /* Workaround - Extra data written in the FIFO at the end of a read transfer */\r\n      HAL_QSPI_Abort_IT(hqspi);\r\n#endif /* QSPI_V1_0*/      \r\n      \r\n      /* Change state of QSPI */\r\n      hqspi->State = HAL_QSPI_STATE_READY;\r\n\r\n      /* RX Complete callback */\r\n      HAL_QSPI_RxCpltCallback(hqspi);\r\n    }\r\n    else if(hqspi->State == HAL_QSPI_STATE_BUSY)\r\n    {\r\n      /* Change state of QSPI */\r\n      hqspi->State = HAL_QSPI_STATE_READY;\r\n\r\n      /* Command Complete callback */\r\n      HAL_QSPI_CmdCpltCallback(hqspi);\r\n    }\r\n    else if(hqspi->State == HAL_QSPI_STATE_ABORT)\r\n    {\r\n      /* Change state of QSPI */\r\n      hqspi->State = HAL_QSPI_STATE_READY;\r\n\r\n      if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE)\r\n      {\r\n        /* Abort called by the user */\r\n\r\n        /* Abort Complete callback */\r\n        HAL_QSPI_AbortCpltCallback(hqspi);\r\n      }\r\n      else \r\n      {\r\n        /* Abort due to an error (eg :  DMA error) */\r\n\r\n        /* Error callback */\r\n        HAL_QSPI_ErrorCallback(hqspi);\r\n      }\r\n    }\r\n  }\r\n\r\n  /* QSPI Status Match interrupt occurred ------------------------------------*/\r\n  else if(((flag & QSPI_FLAG_SM)!= RESET) && ((itsource & QSPI_IT_SM)!= RESET))\r\n  {\r\n    /* Clear interrupt */\r\n    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);\r\n   \r\n    /* Check if the automatic poll mode stop is activated */\r\n    if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0)\r\n    {\r\n      /* Disable the QSPI Transfer Error and Status Match Interrupts */\r\n      __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));\r\n\r\n      /* Change state of QSPI */\r\n      hqspi->State = HAL_QSPI_STATE_READY;\r\n    }\r\n\r\n    /* Status match callback */\r\n    HAL_QSPI_StatusMatchCallback(hqspi);\r\n  }\r\n\r\n  /* QSPI Transfer Error interrupt occurred ----------------------------------*/\r\n  else if(((flag & QSPI_FLAG_TE)!= RESET) && ((itsource & QSPI_IT_TE)!= RESET))\r\n  {\r\n    /* Clear interrupt */\r\n    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);\r\n    \r\n    /* Disable all the QSPI Interrupts */\r\n    __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);\r\n\r\n    /* Set error code */\r\n    hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;\r\n    \r\n    if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)\r\n    {\r\n      /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */\r\n      CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r\n      \r\n      /* Disable the DMA channel */\r\n      hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;\r\n      HAL_DMA_Abort_IT(hqspi->hdma);\r\n    }\r\n    else\r\n    {\r\n      /* Change state of QSPI */\r\n      hqspi->State = HAL_QSPI_STATE_READY;\r\n      \r\n      /* Error callback */\r\n      HAL_QSPI_ErrorCallback(hqspi);\r\n    }\r\n  }\r\n\r\n  /* QSPI Timeout interrupt occurred -----------------------------------------*/\r\n  else if(((flag & QSPI_FLAG_TO)!= RESET) && ((itsource & QSPI_IT_TO)!= RESET))\r\n  {\r\n    /* Clear interrupt */\r\n    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);\r\n    \r\n    /* Time out callback */\r\n    HAL_QSPI_TimeOutCallback(hqspi);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Sets the command configuration. \r\n  * @param hqspi: QSPI handle\r\n  * @param cmd : structure that contains the command configuration information\r\n  * @param Timeout : Time out duration\r\n  * @note   This function is used only in Indirect Read or Write Modes\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)\r\n{\r\n  HAL_StatusTypeDef status = HAL_ERROR;\r\n  uint32_t tickstart = HAL_GetTick();\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));\r\n  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r\n  {\r\n    assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));\r\n  }\r\n\r\n  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));\r\n  if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r\n  {\r\n    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));\r\n  }\r\n\r\n  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));\r\n  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r\n  {\r\n    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));\r\n  }\r\n\r\n  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));\r\n  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));\r\n\r\n  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));\r\n  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));\r\n  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hqspi);\r\n\r\n  if(hqspi->State == HAL_QSPI_STATE_READY)\r\n  {\r\n    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r\n    \r\n    /* Update QSPI state */\r\n    hqspi->State = HAL_QSPI_STATE_BUSY;   \r\n    \r\n    /* Wait till BUSY flag reset */\r\n    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);\r\n    \r\n    if (status == HAL_OK)\r\n    {\r\n      /* Call the configuration function */\r\n      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);\r\n      \r\n      if (cmd->DataMode == QSPI_DATA_NONE)\r\n      {\r\n        /* When there is no data phase, the transfer start as soon as the configuration is done \r\n        so wait until TC flag is set to go back in idle state */\r\n        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);\r\n\r\n        if (status == HAL_OK)\r\n        {\r\n          __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r\n          \r\n          /* Update QSPI state */\r\n          hqspi->State = HAL_QSPI_STATE_READY;   \r\n        }\r\n        \r\n      }\r\n      else\r\n      {\r\n        /* Update QSPI state */\r\n        hqspi->State = HAL_QSPI_STATE_READY;   \r\n      }\r\n    }\r\n  }\r\n  else\r\n  {\r\n    status = HAL_BUSY;   \r\n  }\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hqspi);\r\n\r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief Sets the command configuration in interrupt mode. \r\n  * @param hqspi: QSPI handle\r\n  * @param cmd : structure that contains the command configuration information\r\n  * @note   This function is used only in Indirect Read or Write Modes\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)\r\n{\r\n  HAL_StatusTypeDef status = HAL_ERROR;\r\n  uint32_t tickstart = HAL_GetTick();\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));\r\n  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r\n  {\r\n    assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));\r\n  }\r\n\r\n  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));\r\n  if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r\n  {\r\n    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));\r\n  }\r\n\r\n  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));\r\n  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r\n  {\r\n    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));\r\n  }\r\n\r\n  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));\r\n  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));\r\n\r\n  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));\r\n  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));\r\n  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hqspi);\r\n\r\n  if(hqspi->State == HAL_QSPI_STATE_READY)\r\n  {\r\n    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r\n    \r\n    /* Update QSPI state */\r\n    hqspi->State = HAL_QSPI_STATE_BUSY;   \r\n    \r\n    /* Wait till BUSY flag reset */\r\n    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);\r\n    \r\n    if (status == HAL_OK)\r\n    {\r\n      if (cmd->DataMode == QSPI_DATA_NONE)\r\n      {\r\n        /* Clear interrupt */\r\n        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);\r\n      }\r\n      \r\n      /* Call the configuration function */\r\n      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);\r\n      \r\n      if (cmd->DataMode == QSPI_DATA_NONE)\r\n      {\r\n        /* When there is no data phase, the transfer start as soon as the configuration is done \r\n        so activate TC and TE interrupts */\r\n        /* Process unlocked */\r\n        __HAL_UNLOCK(hqspi);\r\n\r\n        /* Enable the QSPI Transfer Error Interrupt */\r\n        __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);\r\n      }\r\n      else\r\n      {\r\n        /* Update QSPI state */\r\n        hqspi->State = HAL_QSPI_STATE_READY;   \r\n\r\n        /* Process unlocked */\r\n        __HAL_UNLOCK(hqspi);\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* Process unlocked */\r\n      __HAL_UNLOCK(hqspi);\r\n    }\r\n  }\r\n  else\r\n  {\r\n    status = HAL_BUSY;   \r\n\r\n    /* Process unlocked */\r\n    __HAL_UNLOCK(hqspi);\r\n  }\r\n  \r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief Transmit an amount of data in blocking mode. \r\n  * @param hqspi: QSPI handle\r\n  * @param pData: pointer to data buffer\r\n  * @param Timeout : Time out duration\r\n  * @note   This function is used only in Indirect Write Mode\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)\r\n{\r\n   HAL_StatusTypeDef status = HAL_OK;\r\n  uint32_t tickstart = HAL_GetTick();\r\n  __IO uint32_t *data_reg = &hqspi->Instance->DR;\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hqspi);\r\n\r\n  if(hqspi->State == HAL_QSPI_STATE_READY)\r\n  {\r\n    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r\n\r\n    if(pData != NULL )\r\n    {\r\n      /* Update state */\r\n      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;\r\n      \r\n      /* Configure counters and size of the handle */\r\n      hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;\r\n      hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;\r\n      hqspi->pTxBuffPtr = pData;\r\n    \r\n      /* Configure QSPI: CCR register with functional as indirect write */\r\n      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);\r\n\r\n      while(hqspi->TxXferCount > 0)\r\n      {\r\n        /* Wait until FT flag is set to send data */\r\n        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout);\r\n\r\n        if (status != HAL_OK)\r\n        { \r\n          break;\r\n        }\r\n\r\n        *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;\r\n        hqspi->TxXferCount--;\r\n      }\r\n    \r\n      if (status == HAL_OK)\r\n      {\r\n        /* Wait until TC flag is set to go back in idle state */\r\n        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);\r\n\r\n        if (status == HAL_OK)\r\n        {\r\n          /* Clear Transfer Complete bit */\r\n          __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r\n          \r\n#if defined(QSPI1_V1_0)\r\n          /* Clear Busy bit */\r\n          status = HAL_QSPI_Abort(hqspi);\r\n#endif /* QSPI_V1_0 */ \r\n        }\r\n      }\r\n    \r\n      /* Update QSPI state */\r\n      hqspi->State = HAL_QSPI_STATE_READY;    \r\n    }\r\n    else\r\n    {\r\n      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r\n      status = HAL_ERROR;\r\n    }\r\n  }\r\n  else\r\n  {\r\n    status = HAL_BUSY;\r\n  }\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hqspi);\r\n\r\n  return status;\r\n}\r\n\r\n\r\n/**\r\n  * @brief Receive an amount of data in blocking mode \r\n  * @param hqspi: QSPI handle\r\n  * @param pData: pointer to data buffer\r\n  * @param Timeout : Time out duration\r\n  * @note   This function is used only in Indirect Read Mode\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  uint32_t tickstart = HAL_GetTick();\r\n  uint32_t addr_reg = READ_REG(hqspi->Instance->AR);\r\n  __IO uint32_t *data_reg = &hqspi->Instance->DR;\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hqspi);\r\n  \r\n  if(hqspi->State == HAL_QSPI_STATE_READY)\r\n  {\r\n    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r\n    if(pData != NULL )\r\n    {\r\n      /* Update state */\r\n      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;\r\n    \r\n      /* Configure counters and size of the handle */\r\n      hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;\r\n      hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;\r\n      hqspi->pRxBuffPtr = pData;\r\n\r\n      /* Configure QSPI: CCR register with functional as indirect read */\r\n      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);\r\n\r\n      /* Start the transfer by re-writing the address in AR register */\r\n      WRITE_REG(hqspi->Instance->AR, addr_reg);\r\n      \r\n      while(hqspi->RxXferCount > 0)\r\n      {\r\n        /* Wait until FT or TC flag is set to read received data */\r\n        status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Timeout);\r\n\r\n        if  (status != HAL_OK)\r\n        { \r\n          break;\r\n        }\r\n\r\n        *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;\r\n        hqspi->RxXferCount--;\r\n      }\r\n    \r\n      if (status == HAL_OK)\r\n      {\r\n        /* Wait until TC flag is set to go back in idle state */\r\n        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);\r\n\r\n        if  (status == HAL_OK)\r\n        {\r\n          /* Clear Transfer Complete bit */\r\n          __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r\n          \r\n#if defined(QSPI1_V1_0)\r\n         /* Workaround - Extra data written in the FIFO at the end of a read transfer */\r\n         status = HAL_QSPI_Abort(hqspi);\r\n#endif /* QSPI_V1_0 */  \r\n        }\r\n      }\r\n\r\n      /* Update QSPI state */\r\n      hqspi->State = HAL_QSPI_STATE_READY;    \r\n    }\r\n    else\r\n    {\r\n      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r\n      status = HAL_ERROR;\r\n    }\r\n  }\r\n  else\r\n  {\r\n    status = HAL_BUSY;\r\n  }\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hqspi);\r\n\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Send an amount of data in interrupt mode \r\n  * @param  hqspi: QSPI handle\r\n  * @param  pData: pointer to data buffer\r\n  * @note   This function is used only in Indirect Write Mode\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)\r\n{  \r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hqspi);\r\n\r\n  if(hqspi->State == HAL_QSPI_STATE_READY)\r\n  {\r\n    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r\n    if(pData != NULL )\r\n    {\r\n      /* Update state */\r\n      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;\r\n\r\n      /* Configure counters and size of the handle */\r\n      hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;\r\n      hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;\r\n      hqspi->pTxBuffPtr = pData;\r\n    \r\n      /* Configure QSPI: CCR register with functional as indirect write */\r\n      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);\r\n    \r\n      /* Clear interrupt */\r\n      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);\r\n\r\n      /* Process unlocked */\r\n      __HAL_UNLOCK(hqspi);\r\n      \r\n      /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */\r\n      __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);\r\n      \r\n    }\r\n    else\r\n    {\r\n      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r\n      status = HAL_ERROR;\r\n\r\n      /* Process unlocked */\r\n      __HAL_UNLOCK(hqspi);\r\n    }\r\n  }\r\n  else\r\n  {\r\n    status = HAL_BUSY;\r\n\r\n    /* Process unlocked */\r\n    __HAL_UNLOCK(hqspi);\r\n  }\r\n\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Receive an amount of data in no-blocking mode with Interrupt\r\n  * @param  hqspi: QSPI handle\r\n  * @param  pData: pointer to data buffer\r\n  * @note   This function is used only in Indirect Read Mode\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  uint32_t addr_reg = READ_REG(hqspi->Instance->AR);\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hqspi);\r\n\r\n  if(hqspi->State == HAL_QSPI_STATE_READY)\r\n  {\r\n    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r\n    \r\n    if(pData != NULL )\r\n    {\r\n      /* Update state */\r\n      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;\r\n    \r\n      /* Configure counters and size of the handle */\r\n      hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;\r\n      hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;\r\n      hqspi->pRxBuffPtr = pData;\r\n\r\n      /* Configure QSPI: CCR register with functional as indirect read */\r\n      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);\r\n\r\n      /* Start the transfer by re-writing the address in AR register */\r\n      WRITE_REG(hqspi->Instance->AR, addr_reg);\r\n\r\n      /* Clear interrupt */\r\n      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);\r\n\r\n      /* Process unlocked */\r\n      __HAL_UNLOCK(hqspi);\r\n\r\n      /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */\r\n      __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);\r\n    }\r\n    else\r\n    {\r\n      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r\n      status = HAL_ERROR;\r\n\r\n      /* Process unlocked */\r\n      __HAL_UNLOCK(hqspi);\r\n    }\r\n  }\r\n  else\r\n  {\r\n    status = HAL_BUSY;   \r\n\r\n    /* Process unlocked */\r\n    __HAL_UNLOCK(hqspi);\r\n  }\r\n\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Sends an amount of data in non blocking mode with DMA. \r\n  * @param  hqspi: QSPI handle\r\n  * @param  pData: pointer to data buffer\r\n  * @note   This function is used only in Indirect Write Mode\r\n  * @note   If DMA peripheral access is configured as halfword, the number \r\n  *         of data and the fifo threshold should be aligned on halfword\r\n  * @note   If DMA peripheral access is configured as word, the number \r\n  *         of data and the fifo threshold should be aligned on word\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  uint32_t *tmp;\r\n  uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1);\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hqspi);\r\n  \r\n  if(hqspi->State == HAL_QSPI_STATE_READY)\r\n  {\r\n    /* Clear the error code */                \r\n    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r\n    \r\n    if(pData != NULL ) \r\n    {\r\n      /* Configure counters of the handle */\r\n      if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)\r\n      {\r\n        hqspi->TxXferCount = data_size;\r\n      }\r\n      else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)\r\n      {\r\n        if (((data_size % 2) != 0) || ((hqspi->Init.FifoThreshold % 2) != 0))\r\n        {\r\n          /* The number of data or the fifo threshold is not aligned on halfword \r\n          => no transfer possible with DMA peripheral access configured as halfword */\r\n          hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r\n          status = HAL_ERROR;\r\n          \r\n          /* Process unlocked */\r\n          __HAL_UNLOCK(hqspi);\r\n        }\r\n        else\r\n        {\r\n          hqspi->TxXferCount = (data_size >> 1);\r\n        }\r\n      }\r\n      else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)\r\n      {\r\n        if (((data_size % 4) != 0) || ((hqspi->Init.FifoThreshold % 4) != 0))\r\n        {\r\n          /* The number of data or the fifo threshold is not aligned on word \r\n          => no transfer possible with DMA peripheral access configured as word */\r\n          hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r\n          status = HAL_ERROR;\r\n          \r\n          /* Process unlocked */\r\n          __HAL_UNLOCK(hqspi);\r\n        }\r\n        else\r\n        {\r\n          hqspi->TxXferCount = (data_size >> 2);\r\n        }\r\n      }\r\n      \r\n      if (status == HAL_OK)\r\n      {\r\n\r\n      /* Update state */\r\n      hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;\r\n\r\n      /* Clear interrupt */\r\n      __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));\r\n\r\n      /* Configure size and pointer of the handle */\r\n      hqspi->TxXferSize = hqspi->TxXferCount;\r\n      hqspi->pTxBuffPtr = pData;\r\n    \r\n      /* Configure QSPI: CCR register with functional mode as indirect write */\r\n      MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);\r\n    \r\n      /* Set the QSPI DMA transfer complete callback */\r\n      hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;\r\n    \r\n      /* Set the QSPI DMA Half transfer complete callback */\r\n      hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;\r\n    \r\n      /* Set the DMA error callback */\r\n      hqspi->hdma->XferErrorCallback = QSPI_DMAError;\r\n      \r\n      /* Clear the DMA abort callback */      \r\n      hqspi->hdma->XferAbortCallback = NULL;\r\n\r\n      /* Configure the direction of the DMA */\r\n      hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;\r\n      MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);\r\n\r\n      /* Enable the QSPI transmit DMA Channel */\r\n      tmp = (uint32_t*)&pData;\r\n      HAL_DMA_Start_IT(hqspi->hdma, *(uint32_t*)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize);\r\n\r\n      /* Process unlocked */\r\n      __HAL_UNLOCK(hqspi);\r\n\r\n      /* Enable the QSPI transfer error Interrupt */\r\n      __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);\r\n\r\n      /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */\r\n      SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r\n    }\r\n    }\r\n    else\r\n    {\r\n      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r\n      \r\n      status = HAL_ERROR;\r\n\r\n      /* Process unlocked */\r\n      __HAL_UNLOCK(hqspi);\r\n    }\r\n  }\r\n  else\r\n  {\r\n    status = HAL_BUSY;   \r\n\r\n    /* Process unlocked */\r\n    __HAL_UNLOCK(hqspi);\r\n  }\r\n\r\n  return status;\r\n}\r\n                          \r\n/**\r\n  * @brief  Receives an amount of data in non blocking mode with DMA. \r\n  * @param  hqspi: QSPI handle\r\n  * @param  pData: pointer to data buffer.\r\n  * @note   This function is used only in Indirect Read Mode\r\n  * @note   If DMA peripheral access is configured as halfword, the number \r\n  *         of data and the fifo threshold should be aligned on halfword\r\n  * @note   If DMA peripheral access is configured as word, the number \r\n  *         of data and the fifo threshold should be aligned on word\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  uint32_t *tmp;\r\n  uint32_t addr_reg = READ_REG(hqspi->Instance->AR);\r\n  uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1);\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hqspi);\r\n  \r\n  if(hqspi->State == HAL_QSPI_STATE_READY)\r\n  {\r\n    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r\n    \r\n    if(pData != NULL ) \r\n    {\r\n      /* Configure counters of the handle */\r\n      if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)\r\n      {\r\n        hqspi->RxXferCount = data_size;\r\n      }\r\n      else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)\r\n      {\r\n        if (((data_size % 2) != 0) || ((hqspi->Init.FifoThreshold % 2) != 0))\r\n        {\r\n          /* The number of data or the fifo threshold is not aligned on halfword \r\n          => no transfer possible with DMA peripheral access configured as halfword */\r\n          hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r\n          status = HAL_ERROR;\r\n          \r\n          /* Process unlocked */\r\n          __HAL_UNLOCK(hqspi);\r\n        }\r\n        else\r\n        {\r\n          hqspi->RxXferCount = (data_size >> 1);\r\n        }\r\n      }\r\n      else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)\r\n      {\r\n        if (((data_size % 4) != 0) || ((hqspi->Init.FifoThreshold % 4) != 0))\r\n        {\r\n          /* The number of data or the fifo threshold is not aligned on word \r\n          => no transfer possible with DMA peripheral access configured as word */\r\n          hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r\n          status = HAL_ERROR;\r\n          \r\n          /* Process unlocked */\r\n          __HAL_UNLOCK(hqspi);\r\n        }\r\n        else\r\n        {\r\n          hqspi->RxXferCount = (data_size >> 2);\r\n        }\r\n      }\r\n      \r\n      if (status == HAL_OK)\r\n      {\r\n        \r\n        /* Update state */\r\n        hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;\r\n        \r\n        /* Clear interrupt */\r\n        __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));\r\n        \r\n        /* Configure size and pointer of the handle */\r\n        hqspi->RxXferSize = hqspi->RxXferCount;\r\n        hqspi->pRxBuffPtr = pData;\r\n        \r\n        /* Set the QSPI DMA transfer complete callback */\r\n        hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;\r\n        \r\n        /* Set the QSPI DMA Half transfer complete callback */\r\n        hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;\r\n        \r\n        /* Set the DMA error callback */\r\n        hqspi->hdma->XferErrorCallback = QSPI_DMAError;\r\n        \r\n        /* Clear the DMA abort callback */      \r\n        hqspi->hdma->XferAbortCallback = NULL;\r\n        \r\n        /* Configure the direction of the DMA */\r\n        hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;\r\n        MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);\r\n        \r\n        /* Enable the DMA Channel */\r\n        tmp = (uint32_t*)&pData;\r\n        HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize);\r\n        \r\n        /* Configure QSPI: CCR register with functional as indirect read */\r\n        MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);\r\n        \r\n        /* Start the transfer by re-writing the address in AR register */\r\n        WRITE_REG(hqspi->Instance->AR, addr_reg);\r\n        \r\n        /* Process unlocked */\r\n        __HAL_UNLOCK(hqspi);\r\n        \r\n        /* Enable the QSPI transfer error Interrupt */\r\n        __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);\r\n        \r\n        /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */\r\n        SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r\n      }\r\n    }\r\n    else\r\n    {\r\n      hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;\r\n      status = HAL_ERROR;\r\n      \r\n      /* Process unlocked */\r\n      __HAL_UNLOCK(hqspi);\r\n    }\r\n  }\r\n  else\r\n  {\r\n    status = HAL_BUSY; \r\n    \r\n    /* Process unlocked */\r\n    __HAL_UNLOCK(hqspi);\r\n  }\r\n  \r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Configure the QSPI Automatic Polling Mode in blocking mode. \r\n  * @param  hqspi: QSPI handle\r\n  * @param  cmd: structure that contains the command configuration information.\r\n  * @param  cfg: structure that contains the polling configuration information.\r\n  * @param  Timeout : Time out duration\r\n  * @note   This function is used only in Automatic Polling Mode\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)\r\n{\r\n  HAL_StatusTypeDef status = HAL_ERROR;\r\n  uint32_t tickstart = HAL_GetTick();\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));\r\n  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r\n  {\r\n    assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));\r\n  }\r\n  \r\n  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));\r\n  if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r\n  {\r\n    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));\r\n  }\r\n  \r\n  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));\r\n  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r\n  {\r\n    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));\r\n  }\r\n  \r\n  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));\r\n  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));\r\n  \r\n  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));\r\n  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));\r\n  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));\r\n  \r\n  assert_param(IS_QSPI_INTERVAL(cfg->Interval));\r\n  assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));\r\n  assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hqspi);\r\n  \r\n  if(hqspi->State == HAL_QSPI_STATE_READY)\r\n  {\r\n    \r\n    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r\n    \r\n    /* Update state */\r\n    hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;\r\n    \r\n    /* Wait till BUSY flag reset */\r\n    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);\r\n    \r\n    if (status == HAL_OK)\r\n    {\r\n      /* Configure QSPI: PSMAR register with the status match value */\r\n      WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);\r\n      \r\n      /* Configure QSPI: PSMKR register with the status mask value */\r\n      WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);\r\n      \r\n      /* Configure QSPI: PIR register with the interval value */\r\n      WRITE_REG(hqspi->Instance->PIR, cfg->Interval);\r\n      \r\n      /* Configure QSPI: CR register with Match mode and Automatic stop enabled \r\n      (otherwise there will be an infinite loop in blocking mode) */\r\n      MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), \r\n               (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));\r\n      \r\n      /* Call the configuration function */\r\n      cmd->NbData = cfg->StatusBytesSize;\r\n      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);\r\n      \r\n      /* Wait until SM flag is set to go back in idle state */\r\n      status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout);\r\n\r\n      if (status == HAL_OK)\r\n      {\r\n        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);\r\n        \r\n        /* Update state */\r\n        hqspi->State = HAL_QSPI_STATE_READY;\r\n      }\r\n    }\r\n  }\r\n  else\r\n  {\r\n    status = HAL_BUSY;   \r\n  }\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hqspi);\r\n  \r\n  /* Return function status */\r\n  return status;  \r\n}\r\n\r\n/**\r\n  * @brief  Configure the QSPI Automatic Polling Mode in non-blocking mode. \r\n  * @param  hqspi: QSPI handle\r\n  * @param  cmd: structure that contains the command configuration information.\r\n  * @param  cfg: structure that contains the polling configuration information.\r\n  * @note   This function is used only in Automatic Polling Mode\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)\r\n{\r\n  HAL_StatusTypeDef status = HAL_ERROR;\r\n  uint32_t tickstart = HAL_GetTick();\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));\r\n  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r\n  {\r\n    assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));\r\n  }\r\n  \r\n  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));\r\n  if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r\n  {\r\n    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));\r\n  }\r\n  \r\n  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));\r\n  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r\n  {\r\n    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));\r\n  }\r\n  \r\n  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));\r\n  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));\r\n  \r\n  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));\r\n  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));\r\n  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));\r\n  \r\n  assert_param(IS_QSPI_INTERVAL(cfg->Interval));\r\n  assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));\r\n  assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));\r\n  assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hqspi);\r\n  \r\n  if(hqspi->State == HAL_QSPI_STATE_READY)\r\n  {\r\n    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r\n    \r\n    /* Update state */\r\n    hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;\r\n    \r\n    /* Wait till BUSY flag reset */\r\n    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);\r\n    \r\n    if (status == HAL_OK)\r\n    {\r\n      /* Configure QSPI: PSMAR register with the status match value */\r\n      WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);\r\n      \r\n      /* Configure QSPI: PSMKR register with the status mask value */\r\n      WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);\r\n      \r\n      /* Configure QSPI: PIR register with the interval value */\r\n      WRITE_REG(hqspi->Instance->PIR, cfg->Interval);\r\n      \r\n      /* Configure QSPI: CR register with Match mode and Automatic stop mode */\r\n      MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), \r\n               (cfg->MatchMode | cfg->AutomaticStop));\r\n      \r\n      /* Clear interrupt */\r\n      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM);\r\n      \r\n      /* Call the configuration function */\r\n      cmd->NbData = cfg->StatusBytesSize;\r\n      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);\r\n\r\n      /* Process unlocked */\r\n      __HAL_UNLOCK(hqspi);\r\n  \r\n      /* Enable the QSPI Transfer Error and status match Interrupt */\r\n      __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));\r\n\r\n    }\r\n    else\r\n    {\r\n      /* Process unlocked */\r\n      __HAL_UNLOCK(hqspi);\r\n    }\r\n  }\r\n  else\r\n  {\r\n    status = HAL_BUSY;   \r\n\r\n    /* Process unlocked */\r\n    __HAL_UNLOCK(hqspi);\r\n  }\r\n  \r\n  /* Return function status */\r\n  return status;  \r\n}\r\n\r\n/**\r\n  * @brief  Configure the Memory Mapped mode. \r\n  * @param  hqspi: QSPI handle\r\n  * @param  cmd: structure that contains the command configuration information.\r\n  * @param  cfg: structure that contains the memory mapped configuration information.\r\n  * @note   This function is used only in Memory mapped Mode\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)\r\n{\r\n  HAL_StatusTypeDef status = HAL_ERROR;\r\n  uint32_t tickstart = HAL_GetTick();\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));\r\n  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r\n  {\r\n  assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));\r\n  }\r\n\r\n  assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));\r\n  if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r\n  {\r\n    assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));\r\n  }\r\n\r\n  assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));\r\n  if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r\n  {\r\n    assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));\r\n  }\r\n\r\n  assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));\r\n  assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));\r\n\r\n  assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));\r\n  assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));\r\n  assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));\r\n\r\n  assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hqspi);\r\n  \r\n  if(hqspi->State == HAL_QSPI_STATE_READY)\r\n  {\r\n    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;\r\n    \r\n    /* Update state */\r\n    hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;\r\n    \r\n    /* Wait till BUSY flag reset */\r\n    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);\r\n    \r\n    if (status == HAL_OK)\r\n    {\r\n      /* Configure QSPI: CR register with timeout counter enable */\r\n    MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);\r\n\r\n    if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)\r\n      {\r\n        assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));\r\n        \r\n        /* Configure QSPI: LPTR register with the low-power timeout value */\r\n        WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);\r\n        \r\n        /* Clear interrupt */\r\n        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);\r\n\r\n        /* Enable the QSPI TimeOut Interrupt */\r\n        __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);\r\n      }\r\n      \r\n      /* Call the configuration function */\r\n      QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);\r\n    }\r\n  }\r\n  else\r\n  {\r\n    status = HAL_BUSY;   \r\n  }\r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hqspi);\r\n  \r\n  /* Return function status */\r\n  return status;  \r\n}\r\n\r\n/**\r\n  * @brief  Transfer Error callbacks\r\n  * @param  hqspi: QSPI handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hqspi);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_QSPI_ErrorCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Abort completed callback.\r\n  * @param  hqspi: QSPI handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hqspi);\r\n\r\n  /* NOTE: This function should not be modified, when the callback is needed,\r\n           the HAL_QSPI_AbortCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Command completed callback.\r\n  * @param  hqspi: QSPI handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hqspi);\r\n  \r\n  /* NOTE: This function Should not be modified, when the callback is needed,\r\n           the HAL_QSPI_CmdCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Rx Transfer completed callbacks.\r\n  * @param  hqspi: QSPI handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hqspi);\r\n  \r\n  /* NOTE: This function Should not be modified, when the callback is needed,\r\n           the HAL_QSPI_RxCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Tx Transfer completed callbacks.\r\n  * @param  hqspi: QSPI handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hqspi);\r\n  \r\n  /* NOTE: This function Should not be modified, when the callback is needed,\r\n           the HAL_QSPI_TxCpltCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  Rx Half Transfer completed callbacks.\r\n  * @param  hqspi: QSPI handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hqspi);\r\n  \r\n  /* NOTE: This function Should not be modified, when the callback is needed,\r\n           the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Tx Half Transfer completed callbacks.\r\n  * @param  hqspi: QSPI handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hqspi);\r\n  \r\n  /* NOTE: This function Should not be modified, when the callback is needed,\r\n           the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  FIFO Threshold callbacks\r\n  * @param  hqspi: QSPI handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hqspi);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Status Match callbacks\r\n  * @param  hqspi: QSPI handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hqspi);\r\n    \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_QSPI_StatusMatchCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Timeout callbacks\r\n  * @param  hqspi: QSPI handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hqspi);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_QSPI_TimeOutCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions \r\n  *  @brief   QSPI control and State functions \r\n  *\r\n@verbatim   \r\n ===============================================================================\r\n                  ##### Peripheral Control and State functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides a set of functions allowing to :\r\n      (+) Check in run-time the state of the driver. \r\n      (+) Check the error code set during last operation.\r\n      (+) Abort any operation.\r\n.....   \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Return the QSPI handle state.\r\n  * @param  hqspi: QSPI handle\r\n  * @retval HAL state\r\n  */\r\nHAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)\r\n{\r\n  /* Return QSPI handle state */\r\n  return hqspi->State;\r\n}\r\n\r\n/**\r\n* @brief  Return the QSPI error code\r\n* @param  hqspi: QSPI handle\r\n* @retval QSPI Error Code\r\n*/\r\nuint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)\r\n{\r\n  return hqspi->ErrorCode;\r\n}\r\n\r\n/**\r\n* @brief  Abort the current transmission\r\n* @param  hqspi: QSPI handle\r\n* @retval HAL status\r\n*/\r\nHAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  uint32_t tickstart = HAL_GetTick();\r\n  \r\n  /* Check if the state is in one of the busy states */\r\n  if ((hqspi->State & 0x2) != 0)\r\n  {\r\n    /* Process unlocked */\r\n    __HAL_UNLOCK(hqspi);\r\n\r\n    if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)\r\n    {\r\n      /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */\r\n      CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r\n      \r\n      /* Abort DMA channel */\r\n      status = HAL_DMA_Abort(hqspi->hdma);\r\n      if(status != HAL_OK)\r\n      {\r\n        hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;\r\n      }\r\n    }  \r\n    \r\n    /* Configure QSPI: CR register with Abort request */\r\n    SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);\r\n    \r\n    /* Wait until TC flag is set to go back in idle state */\r\n    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);\r\n\r\n    if(status == HAL_OK)\r\n    {\r\n      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r\n      \r\n      /* Wait until BUSY flag is reset */\r\n      status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);\r\n    }\r\n    \r\n    if (status == HAL_OK)\r\n    {\r\n      /* Update state */\r\n      hqspi->State = HAL_QSPI_STATE_READY;\r\n    }\r\n  }\r\n\r\n  return status;\r\n}\r\n\r\n/**\r\n* @brief  Abort the current transmission (non-blocking function)\r\n* @param  hqspi: QSPI handle\r\n* @retval HAL status\r\n*/\r\nHAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  \r\n  /* Check if the state is in one of the busy states */\r\n  if ((hqspi->State & 0x2) != 0)\r\n  {\r\n    /* Process unlocked */\r\n    __HAL_UNLOCK(hqspi);\r\n    \r\n    /* Update QSPI state */\r\n    hqspi->State = HAL_QSPI_STATE_ABORT;   \r\n    \r\n    /* Disable all interrupts */\r\n    __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE));\r\n    \r\n    if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)\r\n    {\r\n      /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */\r\n      CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r\n      \r\n      /* Abort DMA channel */\r\n      hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;\r\n      HAL_DMA_Abort_IT(hqspi->hdma);\r\n    }  \r\n    else\r\n    {\r\n      /* Clear interrupt */\r\n      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r\n      \r\n      /* Enable the QSPI Transfer Complete Interrupt */\r\n      __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);\r\n      \r\n      /* Configure QSPI: CR register with Abort request */\r\n      SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);\r\n    }\r\n  }\r\n\r\n  return status;\r\n}\r\n\r\n/** @brief Set QSPI timeout\r\n  * @param  hqspi: QSPI handle.\r\n  * @param  Timeout: Timeout for the QSPI memory access.\r\n  * @retval None\r\n  */\r\nvoid HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)\r\n{\r\n  hqspi->Timeout = Timeout;\r\n}\r\n\r\n/** @brief Set QSPI Fifo threshold.\r\n  * @param  hqspi: QSPI handle.\r\n  * @param  Threshold: Threshold of the Fifo (value between 1 and 16).\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hqspi);\r\n\r\n  if(hqspi->State == HAL_QSPI_STATE_READY)\r\n  {\r\n    /* Synchronize init structure with new FIFO threshold value */\r\n    hqspi->Init.FifoThreshold = Threshold;\r\n    \r\n    /* Configure QSPI FIFO Threshold */\r\n    MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, \r\n               ((hqspi->Init.FifoThreshold - 1) << POSITION_VAL(QUADSPI_CR_FTHRES)));\r\n  }\r\n  else\r\n  {\r\n    status = HAL_BUSY;   \r\n  }\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hqspi);\r\n\r\n  /* Return function status */\r\n  return status;\r\n}\r\n\r\n/** @brief Get QSPI Fifo threshold.\r\n  * @param  hqspi: QSPI handle.\r\n  * @retval Fifo threshold (value between 1 and 16)\r\n  */\r\nuint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)\r\n{\r\n  return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> POSITION_VAL(QUADSPI_CR_FTHRES)) + 1);\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n \r\n/**\r\n  * @brief  DMA QSPI receive process complete callback. \r\n  * @param  hdma: DMA handle\r\n  * @retval None\r\n  */\r\nstatic void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)  \r\n{\r\n  QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  hqspi->RxXferCount = 0;\r\n  \r\n  /* Enable the QSPI transfer complete Interrupt */\r\n  __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);\r\n}\r\n\r\n/**\r\n  * @brief  DMA QSPI transmit process complete callback. \r\n  * @param  hdma: DMA handle\r\n  * @retval None\r\n  */\r\nstatic void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)     \r\n{\r\n  QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  hqspi->TxXferCount = 0;\r\n  \r\n  /* Enable the QSPI transfer complete Interrupt */\r\n  __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);\r\n}\r\n\r\n/**\r\n  * @brief  DMA QSPI receive process half complete callback \r\n  * @param  hdma : DMA handle\r\n  * @retval None\r\n  */\r\nstatic void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n\r\n  HAL_QSPI_RxHalfCpltCallback(hqspi); \r\n}\r\n\r\n/**\r\n  * @brief  DMA QSPI transmit process half complete callback \r\n  * @param  hdma : DMA handle\r\n  * @retval None\r\n  */\r\nstatic void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n\r\n  HAL_QSPI_TxHalfCpltCallback(hqspi);\r\n}\r\n\r\n/**\r\n  * @brief  DMA QSPI communication error callback.\r\n  * @param  hdma: DMA handle\r\n  * @retval None\r\n  */\r\nstatic void QSPI_DMAError(DMA_HandleTypeDef *hdma)   \r\n{\r\n  QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  \r\n  /* if DMA error is FIFO error ignore it */\r\n  if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)\r\n  {\r\n    hqspi->RxXferCount = 0;\r\n    hqspi->TxXferCount = 0;\r\n    hqspi->ErrorCode   |= HAL_QSPI_ERROR_DMA;\r\n    \r\n    /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */\r\n    CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);\r\n    \r\n    /* Abort the QSPI */\r\n    HAL_QSPI_Abort_IT(hqspi);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  DMA QSPI abort complete callback.\r\n  * @param  hdma: DMA handle\r\n  * @retval None\r\n  */\r\nstatic void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)   \r\n{\r\n  QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n\r\n  hqspi->RxXferCount = 0;\r\n  hqspi->TxXferCount = 0;\r\n\r\n  if(hqspi->State == HAL_QSPI_STATE_ABORT)\r\n  {\r\n    /* DMA Abort called by QSPI abort */\r\n    /* Clear interrupt */\r\n    __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);\r\n    \r\n    /* Enable the QSPI Transfer Complete Interrupt */\r\n    __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);\r\n    \r\n    /* Configure QSPI: CR register with Abort request */\r\n    SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);\r\n  }\r\n  else\r\n  {\r\n    /* DMA Abort called due to a transfer error interrupt */\r\n    /* Change state of QSPI */\r\n    hqspi->State = HAL_QSPI_STATE_READY;\r\n    \r\n    /* Error callback */\r\n    HAL_QSPI_ErrorCallback(hqspi);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Wait for a flag state until timeout.\r\n  * @param  hqspi: QSPI handle\r\n  * @param  Flag: Flag checked\r\n  * @param  State: Value of the flag expected\r\n  * @param  tickstart: Start tick value\r\n  * @param  Timeout: Duration of the time out\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, \r\n                                                        FlagStatus State, uint32_t tickstart, uint32_t Timeout)\r\n{\r\n  /* Wait until flag is in expected state */    \r\n  while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)\r\n  {\r\n    /* Check for the Timeout */\r\n    if (Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))\r\n      {\r\n        hqspi->State     = HAL_QSPI_STATE_ERROR;\r\n        hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;\r\n        \r\n        return HAL_ERROR;\r\n      }\r\n    }\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Configure the communication registers.\r\n  * @param  hqspi: QSPI handle\r\n  * @param  cmd: structure that contains the command configuration information\r\n  * @param  FunctionalMode: functional mode to configured\r\n  *           This parameter can be one of the following values:\r\n  *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode\r\n  *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode\r\n  *            @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode\r\n  *            @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode\r\n  * @retval None\r\n  */\r\nstatic void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)\r\n{\r\n  assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));\r\n\r\n  if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))\r\n  {\r\n    /* Configure QSPI: DLR register with the number of data to read or write */\r\n    WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1));\r\n  }\r\n      \r\n  if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)\r\n  {\r\n    if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r\n    {\r\n      /* Configure QSPI: ABR register with alternate bytes value */\r\n      WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);\r\n\r\n      if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r\n      {\r\n        /*---- Command with instruction, address and alternate bytes ----*/\r\n        /* Configure QSPI: CCR register with all communications parameters */\r\n        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r\n                                         cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |\r\n                                         cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |\r\n                                         cmd->InstructionMode | cmd->Instruction | FunctionalMode));\r\n\r\n        if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)\r\n        {\r\n          /* Configure QSPI: AR register with address value */\r\n          WRITE_REG(hqspi->Instance->AR, cmd->Address);\r\n        }\r\n      }\r\n      else\r\n      {\r\n        /*---- Command with instruction and alternate bytes ----*/\r\n        /* Configure QSPI: CCR register with all communications parameters */\r\n        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r\n                                         cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |\r\n                                         cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | \r\n                                         cmd->Instruction | FunctionalMode));\r\n      }\r\n    }\r\n    else\r\n    {\r\n      if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r\n      {\r\n        /*---- Command with instruction and address ----*/\r\n        /* Configure QSPI: CCR register with all communications parameters */\r\n        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r\n                                         cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode | \r\n                                         cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | \r\n                                         cmd->Instruction | FunctionalMode));\r\n\r\n        if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)\r\n        {\r\n          /* Configure QSPI: AR register with address value */\r\n          WRITE_REG(hqspi->Instance->AR, cmd->Address);\r\n        }\r\n      }\r\n      else\r\n      {\r\n        /*---- Command with only instruction ----*/\r\n        /* Configure QSPI: CCR register with all communications parameters */\r\n        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r\n                                         cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode | \r\n                                         cmd->AddressMode | cmd->InstructionMode | cmd->Instruction  | \r\n                                         FunctionalMode));\r\n      }\r\n    }\r\n  }\r\n  else\r\n  {\r\n    if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)\r\n    {\r\n      /* Configure QSPI: ABR register with alternate bytes value */\r\n      WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);\r\n\r\n      if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r\n      {\r\n        /*---- Command with address and alternate bytes ----*/\r\n        /* Configure QSPI: CCR register with all communications parameters */\r\n        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r\n                                         cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |\r\n                                         cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |\r\n                                         cmd->InstructionMode | FunctionalMode));\r\n\r\n        if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)\r\n        {\r\n          /* Configure QSPI: AR register with address value */\r\n          WRITE_REG(hqspi->Instance->AR, cmd->Address);\r\n        }\r\n      }\r\n      else\r\n      {\r\n        /*---- Command with only alternate bytes ----*/\r\n        /* Configure QSPI: CCR register with all communications parameters */\r\n        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r\n                                         cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |\r\n                                         cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | \r\n                                         FunctionalMode));\r\n      }\r\n    }\r\n    else\r\n    {\r\n      if (cmd->AddressMode != QSPI_ADDRESS_NONE)\r\n      {\r\n        /*---- Command with only address ----*/\r\n        /* Configure QSPI: CCR register with all communications parameters */\r\n        WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r\n                                         cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode | \r\n                                         cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | \r\n                                         FunctionalMode));\r\n\r\n        if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)\r\n        {\r\n          /* Configure QSPI: AR register with address value */\r\n          WRITE_REG(hqspi->Instance->AR, cmd->Address);\r\n        }\r\n      }\r\n      else\r\n      {\r\n        /*---- Command with only data phase ----*/\r\n        if (cmd->DataMode != QSPI_DATA_NONE)\r\n        {\r\n          /* Configure QSPI: CCR register with all communications parameters */\r\n          WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |\r\n                                           cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode | \r\n                                           cmd->AddressMode | cmd->InstructionMode | FunctionalMode));\r\n        }\r\n      }\r\n    }\r\n  }\r\n}\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_QSPI_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_rcc.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   RCC HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the Reset and Clock Control (RCC) peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + Peripheral Control functions\r\n  *       \r\n  @verbatim                \r\n  ==============================================================================\r\n                      ##### RCC specific features #####\r\n  ==============================================================================\r\n    [..]  \r\n      After reset the device is running from Internal High Speed oscillator \r\n      (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache \r\n      and I-Cache are disabled, and all peripherals are off except internal\r\n      SRAM, Flash and JTAG.\r\n      (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;\r\n          all peripherals mapped on these busses are running at HSI speed.\r\n      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.\r\n      (+) All GPIOs are in input floating state, except the JTAG pins which\r\n          are assigned to be used for debug purpose.\r\n    \r\n    [..]          \r\n      Once the device started from reset, the user application has to:        \r\n      (+) Configure the clock source to be used to drive the System clock\r\n          (if the application needs higher frequency/performance)\r\n      (+) Configure the System clock frequency and Flash settings  \r\n      (+) Configure the AHB and APB busses prescalers\r\n      (+) Enable the clock for the peripheral(s) to be used\r\n      (+) Configure the clock source(s) for peripherals which clocks are not\r\n          derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)\r\n\r\n                      ##### RCC Limitations #####\r\n  ==============================================================================\r\n    [..]  \r\n      A delay between an RCC peripheral clock enable and the effective peripheral \r\n      enabling should be taken into account in order to manage the peripheral read/write \r\n      from/to registers.\r\n      (+) This delay depends on the peripheral mapping.\r\n      (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle \r\n          after the clock enable bit is set on the hardware register\r\n      (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle \r\n          after the clock enable bit is set on the hardware register\r\n\r\n    [..]  \r\n      Implemented Workaround:\r\n      (+) For AHB & APB peripherals, a dummy read to the peripheral register has been\r\n          inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup RCC RCC\r\n  * @brief RCC HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_RCC_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/** @defgroup RCC_Private_Macros RCC Private Macros\r\n  * @{\r\n  */\r\n\r\n#define MCO1_CLK_ENABLE()   __HAL_RCC_GPIOA_CLK_ENABLE()\r\n#define MCO1_GPIO_PORT        GPIOA\r\n#define MCO1_PIN              GPIO_PIN_8\r\n\r\n#define MCO2_CLK_ENABLE()   __HAL_RCC_GPIOC_CLK_ENABLE()\r\n#define MCO2_GPIO_PORT         GPIOC\r\n#define MCO2_PIN               GPIO_PIN_9\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @defgroup RCC_Private_Variables RCC Private Variables\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Exported functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup RCC_Exported_Functions RCC Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions \r\n  *  @brief    Initialization and Configuration functions \r\n  *\r\n  @verbatim    \r\n  ===============================================================================\r\n##### Initialization and de-initialization functions #####\r\n  ===============================================================================\r\n    [..]\r\n      This section provides functions allowing to configure the internal/external oscillators\r\n      (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1 \r\n      and APB2).\r\n\r\n    [..] Internal/external clock and PLL configuration\r\n      (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through\r\n          the PLL as System clock source.\r\n\r\n      (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC\r\n          clock source.\r\n\r\n      (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or\r\n          through the PLL as System clock source. Can be used also as RTC clock source.\r\n\r\n      (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.   \r\n\r\n      (#) PLL (clocked by HSI or HSE), featuring two different output clocks:\r\n        (++) The first output is used to generate the high speed system clock (up to 216 MHz)\r\n        (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),\r\n             the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).\r\n\r\n      (#) CSS (Clock security system), once enable using the function HAL_RCC_EnableCSS()\r\n          and if a HSE clock failure occurs(HSE used directly or through PLL as System \r\n          clock source), the System clock is automatically switched to HSI and an interrupt\r\n          is generated if enabled. The interrupt is linked to the Cortex-M7 NMI \r\n          (Non-Maskable Interrupt) exception vector.   \r\n\r\n      (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL\r\n          clock (through a configurable prescaler) on PA8 pin.\r\n\r\n      (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S\r\n          clock (through a configurable prescaler) on PC9 pin.\r\n\r\n    [..] System, AHB and APB busses clocks configuration  \r\n      (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,\r\n          HSE and PLL.\r\n          The AHB clock (HCLK) is derived from System clock through configurable \r\n          prescaler and used to clock the CPU, memory and peripherals mapped \r\n          on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived \r\n          from AHB clock through configurable prescalers and used to clock \r\n          the peripherals mapped on these busses. You can use \r\n          \"HAL_RCC_GetSysClockFreq()\" function to retrieve the frequencies of these clocks.  \r\n\r\n      -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:\r\n          (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or\r\n              from an external clock mapped on the I2S_CKIN pin. \r\n              You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.\r\n          (+@)  SAI: the SAI clock can be derived either from a specific PLL (PLLI2S) or (PLLSAI) or\r\n              from an external clock mapped on the I2S_CKIN pin. \r\n               You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock. \r\n          (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock\r\n              divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()\r\n              macros to configure this clock. \r\n          (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz\r\n              to work correctly, while the SDIO require a frequency equal or lower than\r\n              to 48. This clock is derived of the main PLL through PLLQ divider.\r\n          (+@) IWDG clock which is always the LSI clock.\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Resets the RCC clock configuration to the default reset state.\r\n  * @note   The default reset state of the clock configuration is given below:\r\n  *            - HSI ON and used as system clock source\r\n  *            - HSE, PLL and PLLI2S OFF\r\n  *            - AHB, APB1 and APB2 prescaler set to 1.\r\n  *            - CSS, MCO1 and MCO2 OFF\r\n  *            - All interrupts disabled\r\n  * @note   This function doesn't modify the configuration of the\r\n  *            - Peripheral clocks  \r\n  *            - LSI, LSE and RTC clocks \r\n  * @retval None\r\n  */\r\nvoid HAL_RCC_DeInit(void)\r\n{\r\n  /* Set HSION bit */\r\n  SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4); \r\n  \r\n  /* Reset CFGR register */\r\n  CLEAR_REG(RCC->CFGR);\r\n  \r\n  /* Reset HSEON, CSSON, PLLON, PLLI2S */\r\n  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON| RCC_CR_PLLI2SON); \r\n  \r\n  /* Reset PLLCFGR register */\r\n  CLEAR_REG(RCC->PLLCFGR);\r\n  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | ((uint32_t)0x20000000U)); \r\n  \r\n  /* Reset PLLI2SCFGR register */\r\n  CLEAR_REG(RCC->PLLI2SCFGR);\r\n  SET_BIT(RCC->PLLI2SCFGR,  RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1);\r\n  \r\n  /* Reset HSEBYP bit */\r\n  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);\r\n  \r\n  /* Disable all interrupts */\r\n  CLEAR_REG(RCC->CIR);\r\n  \r\n  /* Update the SystemCoreClock global variable */\r\n  SystemCoreClock = HSI_VALUE;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the RCC Oscillators according to the specified parameters in the\r\n  *         RCC_OscInitTypeDef.\r\n  * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that\r\n  *         contains the configuration information for the RCC Oscillators.\r\n  * @note   The PLL is not disabled when used as system clock.\r\n  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not\r\n  *         supported by this function. User should request a transition to LSE Off\r\n  *         first and then LSE On or LSE Bypass.\r\n  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not\r\n  *         supported by this function. User should request a transition to HSE Off\r\n  *         first and then HSE On or HSE Bypass.\r\n  * @retval HAL status\r\n  */\r\n__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)\r\n{\r\n  uint32_t tickstart = 0;  \r\n \r\n  /* Check the parameters */\r\n  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));\r\n  \r\n  /*------------------------------- HSE Configuration ------------------------*/ \r\n  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));\r\n    /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */\r\n    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) \r\n       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))\r\n    {\r\n\t  if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))\r\n      {\r\n        return HAL_ERROR;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* Set the new HSE configuration ---------------------------------------*/\r\n      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);\r\n      \r\n      /* Check the HSE State */\r\n      if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)\r\n      {\r\n        /* Get Start Tick*/\r\n        tickstart = HAL_GetTick();\r\n        \r\n        /* Wait till HSE is ready */  \r\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)\r\n        {\r\n          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)\r\n          {\r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n      }\r\n      else\r\n      {\r\n        /* Get Start Tick*/\r\n        tickstart = HAL_GetTick();\r\n        \r\n        /* Wait till HSE is bypassed or disabled */\r\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)\r\n        {\r\n           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)\r\n          {\r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n      }\r\n    }\r\n  }\r\n  /*----------------------------- HSI Configuration --------------------------*/ \r\n  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));\r\n    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));\r\n    \r\n    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ \r\n    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) \r\n       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))\r\n    {\r\n      /* When HSI is used as system clock it will not disabled */\r\n      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))\r\n      {\r\n        return HAL_ERROR;\r\n      }\r\n      /* Otherwise, just the calibration is allowed */\r\n      else\r\n      {\r\n        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/\r\n        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* Check the HSI State */\r\n      if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)\r\n      {\r\n        /* Enable the Internal High Speed oscillator (HSI). */\r\n        __HAL_RCC_HSI_ENABLE();\r\n\r\n        /* Get Start Tick*/\r\n        tickstart = HAL_GetTick();\r\n\r\n        /* Wait till HSI is ready */  \r\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)\r\n        {\r\n          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)\r\n          {\r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n                \r\n        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/\r\n        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);\r\n      }\r\n      else\r\n      {\r\n        /* Disable the Internal High Speed oscillator (HSI). */\r\n        __HAL_RCC_HSI_DISABLE();\r\n\r\n        /* Get Start Tick*/\r\n        tickstart = HAL_GetTick();\r\n      \r\n        /* Wait till HSI is ready */  \r\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)\r\n        {\r\n          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)\r\n          {\r\n            return HAL_TIMEOUT;\r\n          } \r\n        } \r\n      }\r\n    }\r\n  }\r\n  /*------------------------------ LSI Configuration -------------------------*/\r\n  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));\r\n\r\n    /* Check the LSI State */\r\n    if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)\r\n    {\r\n      /* Enable the Internal Low Speed oscillator (LSI). */\r\n      __HAL_RCC_LSI_ENABLE();\r\n      \r\n      /* Get Start Tick*/\r\n      tickstart = HAL_GetTick();\r\n      \r\n      /* Wait till LSI is ready */\r\n      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)\r\n      {\r\n        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* Disable the Internal Low Speed oscillator (LSI). */\r\n      __HAL_RCC_LSI_DISABLE();\r\n      \r\n      /* Get Start Tick*/\r\n      tickstart = HAL_GetTick();\r\n      \r\n      /* Wait till LSI is ready */  \r\n      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)\r\n      {\r\n        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n  }\r\n  /*------------------------------ LSE Configuration -------------------------*/ \r\n  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));\r\n    \r\n    /* Enable Power Clock*/\r\n    __HAL_RCC_PWR_CLK_ENABLE();\r\n    \r\n    /* Enable write access to Backup domain */\r\n    PWR->CR1 |= PWR_CR1_DBP;\r\n    \r\n    /* Wait for Backup domain Write protection disable */\r\n    tickstart = HAL_GetTick();\r\n    \r\n    while((PWR->CR1 & PWR_CR1_DBP) == RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }      \r\n    }\r\n    \r\n    /* Set the new LSE configuration -----------------------------------------*/\r\n    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);\r\n    /* Check the LSE State */\r\n    if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)\r\n    {\r\n      /* Get Start Tick*/\r\n      tickstart = HAL_GetTick();\r\n      \r\n      /* Wait till LSE is ready */  \r\n      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)\r\n      {\r\n        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }       \r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* Get Start Tick*/\r\n      tickstart = HAL_GetTick();\r\n      \r\n      /* Wait till LSE is ready */  \r\n      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)\r\n      {\r\n        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }       \r\n      }\r\n    }\r\n  }\r\n  /*-------------------------------- PLL Configuration -----------------------*/\r\n  /* Check the parameters */\r\n  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));\r\n  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)\r\n  {\r\n    /* Check if the PLL is used as system clock or not */\r\n    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)\r\n    { \r\n      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)\r\n      {\r\n        /* Check the parameters */\r\n        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));\r\n        assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));\r\n        assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));\r\n        assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));\r\n        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));\r\n        \r\n        /* Disable the main PLL. */\r\n        __HAL_RCC_PLL_DISABLE();\r\n        \r\n        /* Get Start Tick*/\r\n        tickstart = HAL_GetTick();\r\n        \r\n        /* Wait till PLL is ready */  \r\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)\r\n        {\r\n          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r\n          {\r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n        \r\n        /* Configure the main PLL clock source, multiplication and division factors. */\r\n        WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource                                            | \\\r\n                                 RCC_OscInitStruct->PLL.PLLM                                                 | \\\r\n                                 (RCC_OscInitStruct->PLL.PLLN << POSITION_VAL(RCC_PLLCFGR_PLLN))             | \\\r\n                                 (((RCC_OscInitStruct->PLL.PLLP >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \\\r\n                                 (RCC_OscInitStruct->PLL.PLLQ << POSITION_VAL(RCC_PLLCFGR_PLLQ))));\r\n        /* Enable the main PLL. */\r\n        __HAL_RCC_PLL_ENABLE();\r\n\r\n        /* Get Start Tick*/\r\n        tickstart = HAL_GetTick();\r\n        \r\n        /* Wait till PLL is ready */  \r\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)\r\n        {\r\n          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r\n          {\r\n            return HAL_TIMEOUT;\r\n          } \r\n        }\r\n      }\r\n      else\r\n      {\r\n        /* Disable the main PLL. */\r\n        __HAL_RCC_PLL_DISABLE();\r\n \r\n        /* Get Start Tick*/\r\n        tickstart = HAL_GetTick();\r\n        \r\n        /* Wait till PLL is ready */  \r\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)\r\n        {\r\n          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r\n          {\r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n      }\r\n    }\r\n    else\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n  }\r\n  return HAL_OK;\r\n}\r\n \r\n/**\r\n  * @brief  Initializes the CPU, AHB and APB busses clocks according to the specified \r\n  *         parameters in the RCC_ClkInitStruct.\r\n  * @param  RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that\r\n  *         contains the configuration information for the RCC peripheral.\r\n  * @param  FLatency: FLASH Latency, this parameter depend on device selected\r\n  * \r\n  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency \r\n  *         and updated by HAL_RCC_GetHCLKFreq() function called within this function\r\n  *\r\n  * @note   The HSI is used (enabled by hardware) as system clock source after\r\n  *         startup from Reset, wake-up from STOP and STANDBY mode, or in case\r\n  *         of failure of the HSE used directly or indirectly as system clock\r\n  *         (if the Clock Security System CSS is enabled).\r\n  *           \r\n  * @note   A switch from one clock source to another occurs only if the target\r\n  *         clock source is ready (clock stable after startup delay or PLL locked). \r\n  *         If a clock source which is not yet ready is selected, the switch will\r\n  *         occur when the clock source will be ready. \r\n  *         You can use HAL_RCC_GetClockConfig() function to know which clock is\r\n  *         currently used as system clock source.\r\n  * @note   Depending on the device voltage range, the software has to set correctly\r\n  *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency\r\n  *         (for more details refer to section above \"Initialization/de-initialization functions\")\r\n  * @retval None\r\n  */\r\nHAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)\r\n{\r\n  uint32_t tickstart = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));\r\n  assert_param(IS_FLASH_LATENCY(FLatency));\r\n\r\n  /* To correctly read data from FLASH memory, the number of wait states (LATENCY) \r\n  must be correctly programmed according to the frequency of the CPU clock \r\n  (HCLK) and the supply voltage of the device. */\r\n  \r\n  /* Increasing the CPU frequency */\r\n  if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))\r\n  {    \r\n    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */\r\n    __HAL_FLASH_SET_LATENCY(FLatency);\r\n    \r\n    /* Check that the new number of wait states is taken into account to access the Flash\r\n    memory by reading the FLASH_ACR register */\r\n    if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n  }\r\n  \r\n  /*-------------------------- HCLK Configuration --------------------------*/\r\n  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)\r\n  {\r\n    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));\r\n    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);\r\n  }\r\n  \r\n  /*------------------------- SYSCLK Configuration ---------------------------*/ \r\n  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)\r\n  {    \r\n    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));\r\n    \r\n    /* HSE is selected as System Clock Source */\r\n    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)\r\n    {\r\n      /* Check the HSE ready flag */  \r\n      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)\r\n      {\r\n        return HAL_ERROR;\r\n      }\r\n    }\r\n    /* PLL is selected as System Clock Source */\r\n    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)\r\n    {\r\n      /* Check the PLL ready flag */  \r\n      if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)\r\n      {\r\n        return HAL_ERROR;\r\n      }\r\n    }\r\n    /* HSI is selected as System Clock Source */\r\n    else\r\n    {\r\n      /* Check the HSI ready flag */  \r\n      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)\r\n      {\r\n        return HAL_ERROR;\r\n      }\r\n    }\r\n    \r\n    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);\r\n    /* Get Start Tick*/\r\n    tickstart = HAL_GetTick();\r\n    \r\n    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)\r\n    {\r\n      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)\r\n      {\r\n        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)\r\n    {\r\n      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)\r\n      {\r\n        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n    else\r\n    {\r\n      while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)\r\n      {\r\n        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Decreasing the number of wait states because of lower CPU frequency */\r\n  if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))\r\n  {\r\n    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */\r\n    __HAL_FLASH_SET_LATENCY(FLatency);\r\n    \r\n    /* Check that the new number of wait states is taken into account to access the Flash\r\n    memory by reading the FLASH_ACR register */\r\n    if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n  }\r\n\r\n  /*-------------------------- PCLK1 Configuration ---------------------------*/ \r\n  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)\r\n  {\r\n    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));\r\n    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);\r\n  }\r\n  \r\n  /*-------------------------- PCLK2 Configuration ---------------------------*/ \r\n  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)\r\n  {\r\n    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));\r\n    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));\r\n  }\r\n\r\n  /* Update the SystemCoreClock global variable */\r\n  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];\r\n  \r\n  /* Configure the source of time base considering new system clocks settings*/\r\n  HAL_InitTick (TICK_INT_PRIORITY);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions \r\n  *  @brief   RCC clocks control functions \r\n  *\r\n  @verbatim   \r\n  ===============================================================================\r\n                  ##### Peripheral Control functions #####\r\n  ===============================================================================  \r\n    [..]\r\n    This subsection provides a set of functions allowing to control the RCC Clocks \r\n    frequencies.\r\n      \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).\r\n  * @note   PA8/PC9 should be configured in alternate function mode.\r\n  * @param  RCC_MCOx: specifies the output direction for the clock source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).\r\n  *            @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).\r\n  * @param  RCC_MCOSource: specifies the clock source to output.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source\r\n  *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source\r\n  *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source\r\n  *            @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source\r\n  *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source\r\n  *            @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source\r\n  *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source\r\n  *            @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source\r\n  * @param  RCC_MCODiv: specifies the MCOx prescaler.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RCC_MCODIV_1: no division applied to MCOx clock\r\n  *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock\r\n  *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock\r\n  *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock\r\n  *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock\r\n  * @retval None\r\n  */\r\nvoid HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)\r\n{\r\n  GPIO_InitTypeDef GPIO_InitStruct;\r\n  /* Check the parameters */\r\n  assert_param(IS_RCC_MCO(RCC_MCOx));\r\n  assert_param(IS_RCC_MCODIV(RCC_MCODiv));\r\n  /* RCC_MCO1 */\r\n  if(RCC_MCOx == RCC_MCO1)\r\n  {\r\n    assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));\r\n    \r\n    /* MCO1 Clock Enable */\r\n    MCO1_CLK_ENABLE();\r\n    \r\n    /* Configure the MCO1 pin in alternate function mode */    \r\n    GPIO_InitStruct.Pin = MCO1_PIN;\r\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r\n    GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;\r\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\r\n    GPIO_InitStruct.Alternate = GPIO_AF0_MCO;\r\n    HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);\r\n    \r\n    /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */\r\n    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));\r\n  }\r\n  else\r\n  {\r\n    assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));\r\n    \r\n    /* MCO2 Clock Enable */\r\n    MCO2_CLK_ENABLE();\r\n    \r\n    /* Configure the MCO2 pin in alternate function mode */\r\n    GPIO_InitStruct.Pin = MCO2_PIN;\r\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\r\n    GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;\r\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\r\n    GPIO_InitStruct.Alternate = GPIO_AF0_MCO;\r\n    HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);\r\n    \r\n    /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */\r\n    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3)));\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Enables the Clock Security System.\r\n  * @note   If a failure is detected on the HSE oscillator clock, this oscillator\r\n  *         is automatically disabled and an interrupt is generated to inform the\r\n  *         software about the failure (Clock Security System Interrupt, CSSI),\r\n  *         allowing the MCU to perform rescue operations. The CSSI is linked to \r\n  *         the Cortex-M7 NMI (Non-Maskable Interrupt) exception vector.  \r\n  * @retval None\r\n  */\r\nvoid HAL_RCC_EnableCSS(void)\r\n{\r\n  SET_BIT(RCC->CR, RCC_CR_CSSON);\r\n}\r\n\r\n/**\r\n  * @brief  Disables the Clock Security System.\r\n  * @retval None\r\n  */\r\nvoid HAL_RCC_DisableCSS(void)\r\n{\r\n  CLEAR_BIT(RCC->CR, RCC_CR_CSSON);\r\n}\r\n\r\n/**\r\n  * @brief  Returns the SYSCLK frequency\r\n  *        \r\n  * @note   The system frequency computed by this function is not the real \r\n  *         frequency in the chip. It is calculated based on the predefined \r\n  *         constant and the selected clock source:\r\n  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)\r\n  * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)\r\n  * @note     If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) \r\n  *           or HSI_VALUE(*) multiplied/divided by the PLL factors.         \r\n  * @note     (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value\r\n  *               16 MHz) but the real value may vary depending on the variations\r\n  *               in voltage and temperature.\r\n  * @note     (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value\r\n  *                25 MHz), user has to ensure that HSE_VALUE is same as the real\r\n  *                frequency of the crystal used. Otherwise, this function may\r\n  *                have wrong result.\r\n  *                  \r\n  * @note   The result of this function could be not correct when using fractional\r\n  *         value for HSE crystal.\r\n  *           \r\n  * @note   This function can be used by the user application to compute the \r\n  *         baudrate for the communication peripherals or configure other parameters.\r\n  *           \r\n  * @note   Each time SYSCLK changes, this function must be called to update the\r\n  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.\r\n  *         \r\n  *               \r\n  * @retval SYSCLK frequency\r\n  */\r\nuint32_t HAL_RCC_GetSysClockFreq(void)\r\n{\r\n  uint32_t pllm = 0, pllvco = 0, pllp = 0;\r\n  uint32_t sysclockfreq = 0;\r\n\r\n  /* Get SYSCLK source -------------------------------------------------------*/\r\n  switch (RCC->CFGR & RCC_CFGR_SWS)\r\n  {\r\n    case RCC_SYSCLKSOURCE_STATUS_HSI:  /* HSI used as system clock source */\r\n    {\r\n      sysclockfreq = HSI_VALUE;\r\n       break;\r\n    }\r\n    case RCC_SYSCLKSOURCE_STATUS_HSE:  /* HSE used as system clock  source */\r\n    {\r\n      sysclockfreq = HSE_VALUE;\r\n      break;\r\n    }\r\n    case RCC_SYSCLKSOURCE_STATUS_PLLCLK:  /* PLL used as system clock  source */\r\n    {\r\n      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN\r\n      SYSCLK = PLL_VCO / PLLP */\r\n      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;\r\n      if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)\r\n      {\r\n        /* HSE used as PLL clock source */\r\n        pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));\r\n      }\r\n      else\r\n      {\r\n        /* HSI used as PLL clock source */\r\n        pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));    \r\n      }\r\n      pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1 ) *2);\r\n      \r\n      sysclockfreq = pllvco/pllp;\r\n      break;\r\n    }\r\n    default:\r\n    {\r\n      sysclockfreq = HSI_VALUE;\r\n      break;\r\n    }\r\n  }\r\n  return sysclockfreq;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the HCLK frequency     \r\n  * @note   Each time HCLK changes, this function must be called to update the\r\n  *         right HCLK value. Otherwise, any configuration based on this function will be incorrect. \r\n  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency.\r\n  * @retval HCLK frequency\r\n  */\r\nuint32_t HAL_RCC_GetHCLKFreq(void)\r\n{\r\n  return SystemCoreClock;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the PCLK1 frequency     \r\n  * @note   Each time PCLK1 changes, this function must be called to update the\r\n  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.\r\n  * @retval PCLK1 frequency\r\n  */\r\nuint32_t HAL_RCC_GetPCLK1Freq(void)\r\n{  \r\n  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/\r\n  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);\r\n}\r\n\r\n/**\r\n  * @brief  Returns the PCLK2 frequency     \r\n  * @note   Each time PCLK2 changes, this function must be called to update the\r\n  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.\r\n  * @retval PCLK2 frequency\r\n  */\r\nuint32_t HAL_RCC_GetPCLK2Freq(void)\r\n{\r\n  /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/\r\n  return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);\r\n} \r\n\r\n/**\r\n  * @brief  Configures the RCC_OscInitStruct according to the internal \r\n  * RCC configuration registers.\r\n  * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that \r\n  * will be configured.\r\n  * @retval None\r\n  */\r\nvoid HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)\r\n{\r\n  /* Set all possible values for the Oscillator type parameter ---------------*/\r\n  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;\r\n  \r\n  /* Get the HSE configuration -----------------------------------------------*/\r\n  if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)\r\n  {\r\n    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;\r\n  }\r\n  else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)\r\n  {\r\n    RCC_OscInitStruct->HSEState = RCC_HSE_ON;\r\n  }\r\n  else\r\n  {\r\n    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;\r\n  }\r\n  \r\n  /* Get the HSI configuration -----------------------------------------------*/\r\n  if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)\r\n  {\r\n    RCC_OscInitStruct->HSIState = RCC_HSI_ON;\r\n  }\r\n  else\r\n  {\r\n    RCC_OscInitStruct->HSIState = RCC_HSI_OFF;\r\n  }\r\n  \r\n  RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));\r\n  \r\n  /* Get the LSE configuration -----------------------------------------------*/\r\n  if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)\r\n  {\r\n    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;\r\n  }\r\n  else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)\r\n  {\r\n    RCC_OscInitStruct->LSEState = RCC_LSE_ON;\r\n  }\r\n  else\r\n  {\r\n    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;\r\n  }\r\n  \r\n  /* Get the LSI configuration -----------------------------------------------*/\r\n  if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)\r\n  {\r\n    RCC_OscInitStruct->LSIState = RCC_LSI_ON;\r\n  }\r\n  else\r\n  {\r\n    RCC_OscInitStruct->LSIState = RCC_LSI_OFF;\r\n  }\r\n  \r\n  /* Get the PLL configuration -----------------------------------------------*/\r\n  if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)\r\n  {\r\n    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;\r\n  }\r\n  else\r\n  {\r\n    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;\r\n  }\r\n  RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);\r\n  RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);\r\n  RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));\r\n  RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> POSITION_VAL(RCC_PLLCFGR_PLLP));\r\n  RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));\r\n}\r\n\r\n/**\r\n  * @brief  Configures the RCC_ClkInitStruct according to the internal \r\n  * RCC configuration registers.\r\n  * @param  RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that \r\n  * will be configured.\r\n  * @param  pFLatency: Pointer on the Flash Latency.\r\n  * @retval None\r\n  */\r\nvoid HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)\r\n{\r\n  /* Set all possible values for the Clock type parameter --------------------*/\r\n  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;\r\n   \r\n  /* Get the SYSCLK configuration --------------------------------------------*/ \r\n  RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);\r\n  \r\n  /* Get the HCLK configuration ----------------------------------------------*/ \r\n  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); \r\n  \r\n  /* Get the APB1 configuration ----------------------------------------------*/ \r\n  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);   \r\n  \r\n  /* Get the APB2 configuration ----------------------------------------------*/ \r\n  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);\r\n  \r\n  /* Get the Flash Wait State (Latency) configuration ------------------------*/   \r\n  *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); \r\n}\r\n\r\n/**\r\n  * @brief This function handles the RCC CSS interrupt request.\r\n  * @note This API should be called under the NMI_Handler().\r\n  * @retval None\r\n  */\r\nvoid HAL_RCC_NMI_IRQHandler(void)\r\n{\r\n  /* Check RCC CSSF flag  */\r\n  if(__HAL_RCC_GET_IT(RCC_IT_CSS))\r\n  {\r\n    /* RCC Clock Security System interrupt user callback */\r\n    HAL_RCC_CSSCallback();\r\n\r\n    /* Clear RCC CSS pending bit */\r\n    __HAL_RCC_CLEAR_IT(RCC_IT_CSS);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  RCC Clock Security System interrupt callback\r\n  * @retval None\r\n  */\r\n__weak void HAL_RCC_CSSCallback(void)\r\n{\r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_RCC_CSSCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_RCC_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_rcc_ex.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Extension RCC HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities RCC extension peripheral:\r\n  *           + Extended Peripheral Control functions\r\n  *  \r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup RCCEx RCCEx\r\n  * @brief RCCEx HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_RCC_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @defgroup RCCEx_Private_Defines RCCEx Private Defines\r\n  * @{\r\n  */\r\n  \r\n#define PLLI2S_TIMEOUT_VALUE    100 /* Timeout value fixed to 100 ms  */\r\n#define PLLSAI_TIMEOUT_VALUE    100 /* Timeout value fixed to 100 ms  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n/* Private macro -------------------------------------------------------------*/\r\n/** @defgroup RCCEx_Private_Macros RCCEx Private Macros\r\n * @{\r\n */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RCCEx_Private_Macros RCCEx Private Macros\r\n * @{\r\n */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions \r\n *  @brief  Extended Peripheral Control functions  \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                ##### Extended Peripheral Control functions  #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides a set of functions allowing to control the RCC Clocks \r\n    frequencies.\r\n    [..] \r\n    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to\r\n        select the RTC clock source; in this case the Backup domain will be reset in  \r\n        order to modify the RTC Clock source, as consequence RTC registers (including \r\n        the backup registers) and RCC_BDCR register will be set to their reset values.\r\n      \r\n@endverbatim\r\n  * @{\r\n  */\r\n/**\r\n  * @brief  Initializes the RCC extended peripherals clocks according to the specified\r\n  *         parameters in the RCC_PeriphCLKInitTypeDef.\r\n  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that\r\n  *         contains the configuration information for the Extended Peripherals\r\n  *         clocks(I2S, SAI, LTDC, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...).\r\n  *         \r\n  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select \r\n  *         the RTC clock source; in this case the Backup domain will be reset in  \r\n  *         order to modify the RTC Clock source, as consequence RTC registers (including \r\n  *         the backup registers) are set to their reset values.\r\n  *\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)\r\n{\r\n  uint32_t tickstart = 0;\r\n  uint32_t tmpreg0 = 0;\r\n  uint32_t tmpreg1 = 0;\r\n  uint32_t plli2sused = 0;\r\n  uint32_t pllsaiused = 0;\r\n    \r\n  /* Check the parameters */\r\n  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));\r\n  \r\n  /*----------------------------------- I2S configuration ----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));\r\n    \r\n    /* Configure I2S Clock source */\r\n    __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);\r\n    \r\n    /* Enable the PLLI2S when it's used as clock source for I2S */\r\n    if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)\r\n    {\r\n      plli2sused = 1; \r\n    }\r\n  }\r\n  \r\n  /*------------------------------------ SAI1 configuration --------------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));\r\n    \r\n    /* Configure SAI1 Clock source */\r\n    __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);\r\n    /* Enable the PLLI2S when it's used as clock source for SAI */\r\n    if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)\r\n    {\r\n      plli2sused = 1; \r\n    }\r\n    /* Enable the PLLSAI when it's used as clock source for SAI */\r\n    if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)\r\n    {\r\n      pllsaiused = 1; \r\n    }\r\n  }\r\n  \r\n  /*------------------------------------ SAI2 configuration --------------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));\r\n    \r\n    /* Configure SAI2 Clock source */\r\n    __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);\r\n    \r\n    /* Enable the PLLI2S when it's used as clock source for SAI */\r\n    if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)\r\n    {\r\n      plli2sused = 1; \r\n    }\r\n    /* Enable the PLLSAI when it's used as clock source for SAI */\r\n    if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)\r\n    {\r\n      pllsaiused = 1; \r\n    }\r\n  }\r\n  \r\n  /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)\r\n  {    \r\n      plli2sused = 1; \r\n  }  \r\n  \r\n  /*------------------------------------ RTC configuration --------------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))\r\n  {\r\n    /* Check for RTC Parameters used to output RTCCLK */\r\n    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));\r\n    \r\n    /* Enable Power Clock*/\r\n    __HAL_RCC_PWR_CLK_ENABLE();\r\n    \r\n    /* Enable write access to Backup domain */\r\n    PWR->CR1 |= PWR_CR1_DBP;\r\n    \r\n    /* Get Start Tick*/\r\n    tickstart = HAL_GetTick();\r\n    \r\n    /* Wait for Backup domain Write protection disable */\r\n    while((PWR->CR1 & PWR_CR1_DBP) == RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n\r\n    /* Reset the Backup domain only if the RTC Clock source selection is modified */\r\n    tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);\r\n\r\n    if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))\r\n    {\r\n      /* Store the content of BDCR register before the reset of Backup Domain */\r\n      tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));\r\n\r\n      /* RTC Clock selection can be changed only if the Backup Domain is reset */\r\n      __HAL_RCC_BACKUPRESET_FORCE();\r\n      __HAL_RCC_BACKUPRESET_RELEASE();\r\n\r\n      /* Restore the Content of BDCR register */\r\n      RCC->BDCR = tmpreg0;\r\n\r\n      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */\r\n      if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))\r\n      {\r\n        /* Get Start Tick*/\r\n        tickstart = HAL_GetTick();\r\n        \r\n        /* Wait till LSE is ready */  \r\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)\r\n        {\r\n          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\r\n          {\r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n      }\r\n    }\r\n    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);\r\n  }\r\n\r\n  /*------------------------------------ TIM configuration --------------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));\r\n    \r\n    /* Configure Timer Prescaler */\r\n    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);\r\n  }\r\n  \r\n  /*-------------------------------------- I2C1 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));\r\n    \r\n    /* Configure the I2C1 clock source */\r\n    __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);\r\n  }\r\n  \r\n  /*-------------------------------------- I2C2 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));\r\n    \r\n    /* Configure the I2C2 clock source */\r\n    __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);\r\n  }\r\n  \r\n  /*-------------------------------------- I2C3 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));\r\n    \r\n    /* Configure the I2C3 clock source */\r\n    __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);\r\n  }\r\n    \r\n  /*-------------------------------------- I2C4 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));\r\n    \r\n    /* Configure the I2C4 clock source */\r\n    __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);\r\n  }\r\n\r\n  /*-------------------------------------- USART1 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));\r\n    \r\n    /* Configure the USART1 clock source */\r\n    __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);\r\n  }\r\n\r\n  /*-------------------------------------- USART2 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));\r\n    \r\n    /* Configure the USART2 clock source */\r\n    __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);\r\n  }\r\n\r\n  /*-------------------------------------- USART3 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));\r\n    \r\n    /* Configure the USART3 clock source */\r\n    __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);\r\n  }\r\n\r\n  /*-------------------------------------- UART4 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));\r\n    \r\n    /* Configure the UART4 clock source */\r\n    __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);\r\n  }\r\n\r\n  /*-------------------------------------- UART5 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));\r\n    \r\n    /* Configure the UART5 clock source */\r\n    __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);\r\n  }\r\n\r\n  /*-------------------------------------- USART6 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));\r\n    \r\n    /* Configure the USART6 clock source */\r\n    __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);\r\n  }\r\n\r\n  /*-------------------------------------- UART7 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));\r\n    \r\n    /* Configure the UART7 clock source */\r\n    __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);\r\n  }\r\n\r\n  /*-------------------------------------- UART8 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));\r\n    \r\n    /* Configure the UART8 clock source */\r\n    __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);\r\n  }\r\n  \r\n  /*--------------------------------------- CEC Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));\r\n    \r\n    /* Configure the CEC clock source */\r\n    __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);\r\n  }\r\n  \r\n  /*-------------------------------------- CK48 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));\r\n    \r\n    /* Configure the CLK48 source */\r\n    __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);\r\n\r\n    /* Enable the PLLSAI when it's used as clock source for CK48 */\r\n    if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)\r\n    {\r\n      pllsaiused = 1; \r\n    }\r\n  }\r\n\r\n  /*-------------------------------------- LTDC Configuration -----------------------------------*/\r\n#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)\r\n  {\r\n    pllsaiused = 1; \r\n  }\r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n  \r\n  /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));\r\n    \r\n    /* Configure the LTPIM1 clock source */\r\n    __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);\r\n   }\r\n  \r\n  /*------------------------------------- SDMMC1 Configuration ------------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));\r\n    \r\n    /* Configure the SDMMC1 clock source */\r\n    __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);\r\n  }\r\n  \r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)  \r\n  /*------------------------------------- SDMMC2 Configuration ------------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection));\r\n    \r\n    /* Configure the SDMMC2 clock source */\r\n    __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection);\r\n  }\r\n\t\r\n  /*------------------------------------- DFSDM1 Configuration -------------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));\r\n\r\n    /* Configure the DFSDM1 interface clock source */\r\n    __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);\r\n  }\r\n  \r\n  /*------------------------------------- DFSDM AUDIO Configuration -------------------------------------*/\r\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));\r\n\r\n    /* Configure the DFSDM interface clock source */\r\n    __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);\r\n  }  \r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n  \r\n  /*-------------------------------------- PLLI2S Configuration ---------------------------------*/\r\n  /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */\r\n  if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))\r\n  {\r\n    /* Disable the PLLI2S */\r\n    __HAL_RCC_PLLI2S_DISABLE();  \r\n    \r\n    /* Get Start Tick*/\r\n    tickstart = HAL_GetTick();\r\n    \r\n    /* Wait till PLLI2S is disabled */\r\n    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)\r\n      {\r\n        /* return in case of Timeout detected */         \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n    \r\n    /* check for common PLLI2S Parameters */\r\n    assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));\r\n      \r\n    /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/ \r\n    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))\r\n    {\r\n      /* check for Parameters */\r\n      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));\r\n    \r\n      /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */\r\n      tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP));\r\n      tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));\r\n      /* Configure the PLLI2S division factors */\r\n      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */\r\n      /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */\r\n      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR);\r\n    }\r\n        \r\n    /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/  \r\n    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||\r\n       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) \r\n    {\r\n      /* Check for PLLI2S Parameters */\r\n      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));\r\n      /* Check for PLLI2S/DIVQ parameters */\r\n      assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));\r\n            \r\n      /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */\r\n      tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP));\r\n      tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));\r\n      /* Configure the PLLI2S division factors */      \r\n      /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */\r\n      /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */\r\n      /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */\r\n      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1);\r\n   \r\n      /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ \r\n      __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);   \r\n    }          \r\n\r\n    /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/  \r\n    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)\r\n    {\r\n      /* check for Parameters */\r\n      assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));\r\n     \r\n     /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */\r\n      tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));\r\n      tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));\r\n      /* Configure the PLLI2S division factors */\r\n      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */\r\n      /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */\r\n      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1);\r\n    }  \r\n         \r\n    /*----------------- In Case of PLLI2S is just selected  -----------------*/  \r\n    if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)\r\n    {\r\n      /* Check for Parameters */\r\n      assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));\r\n      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));\r\n      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));\r\n\r\n      /* Configure the PLLI2S division factors */\r\n      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */\r\n      /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */\r\n      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);\r\n    } \r\n    \r\n    /* Enable the PLLI2S */\r\n    __HAL_RCC_PLLI2S_ENABLE();\r\n    \r\n    /* Get Start Tick*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    /* Wait till PLLI2S is ready */\r\n    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)\r\n      {\r\n        /* return in case of Timeout detected */                \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  } \r\n  \r\n  /*-------------------------------------- PLLSAI Configuration ---------------------------------*/\r\n  /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */\r\n  if(pllsaiused == 1)\r\n  {\r\n    /* Disable PLLSAI Clock */\r\n    __HAL_RCC_PLLSAI_DISABLE(); \r\n    \r\n    /* Get Start Tick*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    /* Wait till PLLSAI is disabled */\r\n    while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)\r\n      { \r\n        /* return in case of Timeout detected */        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    } \r\n    \r\n    /* Check the PLLSAI division factors */\r\n    assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));\r\n    \r\n    /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/  \r\n    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\\\r\n       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))\r\n    {\r\n      /* check for PLLSAIQ Parameter */\r\n      assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));\r\n      /* check for PLLSAI/DIVQ Parameter */\r\n      assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));\r\n    \r\n      /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */\r\n      tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));\r\n      tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));\r\n      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */\r\n      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */\r\n      /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */\r\n      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);\r\n      \r\n      /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ \r\n      __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);\r\n    }           \r\n\r\n    /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/   \r\n    /* In Case of PLLI2S is selected as source clock for CK48 */ \r\n    if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))\r\n    {\r\n      /* check for Parameters */\r\n      assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));\r\n      /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */\r\n      tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));\r\n      tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));\r\n      \r\n      /* Configure the PLLSAI division factors */\r\n      /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */\r\n      /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */\r\n      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1);\r\n    }        \r\n\r\n#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) \r\n    /*---------------------------- LTDC configuration -------------------------------*/\r\n    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))\r\n    {\r\n      assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));\r\n      assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));\r\n      \r\n      /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */\r\n      tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));\r\n      tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));\r\n      \r\n      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */\r\n      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */\r\n      /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */\r\n      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR);\r\n      \r\n      /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ \r\n      __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);\r\n    }    \r\n#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */  \r\n\r\n    /* Enable PLLSAI Clock */\r\n    __HAL_RCC_PLLSAI_ENABLE();\r\n    \r\n    /* Get Start Tick*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    /* Wait till PLLSAI is ready */\r\n    while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)\r\n      { \r\n        /* return in case of Timeout detected */        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Get the RCC_PeriphCLKInitTypeDef according to the internal\r\n  *         RCC configuration registers.\r\n  * @param  PeriphClkInit: pointer to the configured RCC_PeriphCLKInitTypeDef structure\r\n  * @retval None\r\n  */\r\nvoid HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)\r\n{\r\n  uint32_t tempreg = 0;\r\n  \r\n  /* Set all possible values for the extended clock type parameter------------*/\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)  \r\n  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S      | RCC_PERIPHCLK_LPTIM1   |\\\r\n                                        RCC_PERIPHCLK_SAI1     | RCC_PERIPHCLK_SAI2     |\\\r\n                                        RCC_PERIPHCLK_TIM      | RCC_PERIPHCLK_RTC      |\\\r\n                                        RCC_PERIPHCLK_CEC      | RCC_PERIPHCLK_I2C4     |\\\r\n                                        RCC_PERIPHCLK_I2C1     | RCC_PERIPHCLK_I2C2     |\\\r\n                                        RCC_PERIPHCLK_I2C3     | RCC_PERIPHCLK_USART1   |\\\r\n                                        RCC_PERIPHCLK_USART2   | RCC_PERIPHCLK_USART3   |\\\r\n                                        RCC_PERIPHCLK_UART4    | RCC_PERIPHCLK_UART5    |\\\r\n                                        RCC_PERIPHCLK_USART6   | RCC_PERIPHCLK_UART7    |\\\r\n                                        RCC_PERIPHCLK_UART8    | RCC_PERIPHCLK_SDMMC1   |\\\r\n                                        RCC_PERIPHCLK_CLK48    | RCC_PERIPHCLK_SDMMC2   |\\\r\n                                        RCC_PERIPHCLK_DFSDM1   | RCC_PERIPHCLK_DFSDM1_AUDIO;\r\n#else  \r\n  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S      | RCC_PERIPHCLK_LPTIM1   |\\\r\n                                        RCC_PERIPHCLK_SAI1     | RCC_PERIPHCLK_SAI2     |\\\r\n                                        RCC_PERIPHCLK_TIM      | RCC_PERIPHCLK_RTC      |\\\r\n                                        RCC_PERIPHCLK_CEC      | RCC_PERIPHCLK_I2C4     |\\\r\n                                        RCC_PERIPHCLK_I2C1     | RCC_PERIPHCLK_I2C2     |\\\r\n                                        RCC_PERIPHCLK_I2C3     | RCC_PERIPHCLK_USART1   |\\\r\n                                        RCC_PERIPHCLK_USART2   | RCC_PERIPHCLK_USART3   |\\\r\n                                        RCC_PERIPHCLK_UART4    | RCC_PERIPHCLK_UART5    |\\\r\n                                        RCC_PERIPHCLK_USART6   | RCC_PERIPHCLK_UART7    |\\\r\n                                        RCC_PERIPHCLK_UART8    | RCC_PERIPHCLK_SDMMC1   |\\\r\n                                        RCC_PERIPHCLK_CLK48;\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ \r\n  \r\n  /* Get the PLLI2S Clock configuration -----------------------------------------------*/\r\n  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));\r\n  PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP));\r\n  PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));\r\n  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));\r\n  \r\n  /* Get the PLLSAI Clock configuration -----------------------------------------------*/\r\n  PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));\r\n  PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));\r\n  PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); \r\n  PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)); \r\n  \r\n  /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/\r\n  PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR1_PLLI2SDIVQ));\r\n  PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR1_PLLSAIDIVQ));\r\n  PeriphClkInit->PLLSAIDivR = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVR) >> POSITION_VAL(RCC_DCKCFGR1_PLLSAIDIVR));\r\n\r\n  /* Get the SAI1 clock configuration ----------------------------------------------*/\r\n  PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();\r\n  \r\n  /* Get the SAI2 clock configuration ----------------------------------------------*/\r\n  PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();\r\n  \r\n  /* Get the I2S clock configuration ------------------------------------------*/\r\n  PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE();\r\n  \r\n  /* Get the I2C1 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();\r\n  \r\n  /* Get the I2C2 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();\r\n  \r\n  /* Get the I2C3 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();\r\n  \r\n  /* Get the I2C4 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE();\r\n  \r\n  /* Get the USART1 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();\r\n  \r\n  /* Get the USART2 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();\r\n  \r\n  /* Get the USART3 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();\r\n  \r\n  /* Get the UART4 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();\r\n  \r\n  /* Get the UART5 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();\r\n  \r\n  /* Get the USART6 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE();\r\n  \r\n  /* Get the UART7 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE();\r\n  \r\n  /* Get the UART8 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE();\r\n  \r\n  /* Get the LPTIM1 clock configuration ------------------------------------------*/\r\n  PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();\r\n  \r\n  /* Get the CEC clock configuration -----------------------------------------------*/\r\n  PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();\r\n  \r\n  /* Get the CK48 clock configuration -----------------------------------------------*/\r\n  PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();\r\n\r\n  /* Get the SDMMC1 clock configuration -----------------------------------------------*/\r\n  PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE();\r\n  \r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)  \r\n  /* Get the SDMMC2 clock configuration -----------------------------------------------*/\r\n  PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE();\r\n\t\r\n  /* Get the DFSDM clock configuration -----------------------------------------------*/\r\n  PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE();\r\n  \r\n  /* Get the DFSDM AUDIO clock configuration -----------------------------------------------*/\r\n  PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE();  \r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n  \r\n  /* Get the RTC Clock configuration -----------------------------------------------*/\r\n  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);\r\n  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));\r\n  \r\n  /* Get the TIM Prescaler configuration --------------------------------------------*/\r\n  if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET)\r\n  {\r\n    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;\r\n  }\r\n  else\r\n  {\r\n    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Return the peripheral clock frequency for a given peripheral(SAI..) \r\n  * @note   Return 0 if peripheral clock identifier not managed by this API\r\n  * @param  PeriphClk: Peripheral clock identifier\r\n  *         This parameter can be one of the following values:\r\n  *            @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock\r\n  *            @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock\r\n  * @retval Frequency in KHz\r\n  */\r\nuint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)\r\n{\r\n  uint32_t tmpreg = 0;\r\n  /* This variable is used to store the SAI clock frequency (value in Hz) */\r\n  uint32_t frequency = 0;\r\n  /* This variable is used to store the VCO Input (value in Hz) */\r\n  uint32_t vcoinput = 0;\r\n  /* This variable is used to store the SAI clock source */\r\n  uint32_t saiclocksource = 0;\r\n  \r\n  if (PeriphClk == RCC_PERIPHCLK_SAI1)\r\n  {\r\n    saiclocksource = RCC->DCKCFGR1;   \r\n    saiclocksource &= RCC_DCKCFGR1_SAI1SEL;\r\n    switch (saiclocksource)\r\n    {\r\n    case 0: /* PLLSAI is the clock source for SAI1 */ \r\n      {\r\n        /* Configure the PLLSAI division factor */\r\n        /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */ \r\n        if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)\r\n        {\r\n          /* In Case the PLL Source is HSI (Internal Clock) */\r\n          vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\r\n        }\r\n        else\r\n        {\r\n          /* In Case the PLL Source is HSE (External Clock) */\r\n          vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));\r\n        }   \r\n        /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */\r\n        /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */\r\n        tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;\r\n        frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);\r\n        \r\n        /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */\r\n        tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1);\r\n        frequency = frequency/(tmpreg); \r\n        break;       \r\n      }\r\n    case RCC_DCKCFGR1_SAI1SEL_0: /* PLLI2S is the clock source for SAI1 */\r\n      {  \r\n        /* Configure the PLLI2S division factor */\r\n        /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */ \r\n        if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)\r\n        {\r\n          /* In Case the PLL Source is HSI (Internal Clock) */\r\n          vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\r\n        }\r\n        else\r\n        {\r\n          /* In Case the PLL Source is HSE (External Clock) */\r\n          vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));\r\n        }\r\n        \r\n        /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */\r\n        /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */\r\n        tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;\r\n        frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);\r\n        \r\n        /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */\r\n        tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1); \r\n        frequency = frequency/(tmpreg);\r\n        break;\r\n      }\r\n    case RCC_DCKCFGR1_SAI1SEL_1: /* External clock is the clock source for SAI1 */\r\n      {\r\n        frequency = EXTERNAL_CLOCK_VALUE;\r\n        break;       \r\n      }\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)      \r\n    case RCC_DCKCFGR1_SAI1SEL: /* HSI or HSE is the clock source for SAI*/\r\n      {\r\n        if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)\r\n        {\r\n          /* In Case the main PLL Source is HSI */\r\n          frequency = HSI_VALUE;\r\n        }\r\n        else\r\n        {\r\n          /* In Case the main PLL Source is HSE */\r\n          frequency = HSE_VALUE;\r\n        }\r\n        break;       \r\n      }\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */      \r\n    default :\r\n      {\r\n        break;\r\n      }\r\n    }\r\n  }\r\n  \r\n  if (PeriphClk == RCC_PERIPHCLK_SAI2)\r\n  {\r\n    saiclocksource = RCC->DCKCFGR1;   \r\n    saiclocksource &= RCC_DCKCFGR1_SAI2SEL;\r\n    switch (saiclocksource)\r\n    {\r\n    case 0: /* PLLSAI is the clock source for SAI*/ \r\n      {\r\n        /* Configure the PLLSAI division factor */\r\n        /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */ \r\n        if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)\r\n        {\r\n          /* In Case the PLL Source is HSI (Internal Clock) */\r\n          vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\r\n        }\r\n        else\r\n        {\r\n          /* In Case the PLL Source is HSE (External Clock) */\r\n          vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));\r\n        }   \r\n        /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */\r\n        /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */\r\n        tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;\r\n        frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);\r\n        \r\n        /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */\r\n        tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1);\r\n        frequency = frequency/(tmpreg); \r\n        break;       \r\n      }\r\n    case RCC_DCKCFGR1_SAI2SEL_0: /* PLLI2S is the clock source for SAI2 */\r\n      {  \r\n        /* Configure the PLLI2S division factor */\r\n        /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */ \r\n        if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)\r\n        {\r\n          /* In Case the PLL Source is HSI (Internal Clock) */\r\n          vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\r\n        }\r\n        else\r\n        {\r\n          /* In Case the PLL Source is HSE (External Clock) */\r\n          vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));\r\n        }\r\n        \r\n        /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */\r\n        /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */\r\n        tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;\r\n        frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);\r\n        \r\n        /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */\r\n        tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1); \r\n        frequency = frequency/(tmpreg);\r\n        break;\r\n      }\r\n    case RCC_DCKCFGR1_SAI2SEL_1: /* External clock is the clock source for SAI2 */\r\n      {\r\n        frequency = EXTERNAL_CLOCK_VALUE;\r\n        break;       \r\n      }\r\n#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)\r\n    case RCC_DCKCFGR1_SAI2SEL: /* HSI or HSE is the clock source for SAI2 */\r\n      {\r\n        if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)\r\n        {\r\n          /* In Case the main PLL Source is HSI */\r\n          frequency = HSI_VALUE;\r\n        }\r\n        else\r\n        {\r\n          /* In Case the main PLL Source is HSE */\r\n          frequency = HSE_VALUE;\r\n        }\r\n        break;       \r\n      }\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */      \r\n    default :\r\n      {\r\n        break;\r\n      }\r\n    }\r\n  }\r\n  \r\n  return frequency;\r\n}\r\n\r\n#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r\n/**\r\n  * @brief  Initializes the RCC Oscillators according to the specified parameters in the\r\n  *         RCC_OscInitTypeDef.\r\n  * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that\r\n  *         contains the configuration information for the RCC Oscillators.\r\n  * @note   The PLL is not disabled when used as system clock.\r\n  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not\r\n  *         supported by this function. User should request a transition to LSE Off\r\n  *         first and then LSE On or LSE Bypass.\r\n  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not\r\n  *         supported by this function. User should request a transition to HSE Off\r\n  *         first and then HSE On or HSE Bypass.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)\r\n{\r\n  uint32_t tickstart = 0;  \r\n \r\n  /* Check the parameters */\r\n  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));\r\n  \r\n  /*------------------------------- HSE Configuration ------------------------*/ \r\n  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));\r\n    /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */\r\n    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) \r\n       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))\r\n    {\r\n\t  if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))\r\n      {\r\n        return HAL_ERROR;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* Set the new HSE configuration ---------------------------------------*/\r\n      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);\r\n      \r\n      /* Check the HSE State */\r\n      if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)\r\n      {\r\n        /* Get Start Tick*/\r\n        tickstart = HAL_GetTick();\r\n        \r\n        /* Wait till HSE is ready */  \r\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)\r\n        {\r\n          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)\r\n          {\r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n      }\r\n      else\r\n      {\r\n        /* Get Start Tick*/\r\n        tickstart = HAL_GetTick();\r\n        \r\n        /* Wait till HSE is bypassed or disabled */\r\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)\r\n        {\r\n           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)\r\n          {\r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n      }\r\n    }\r\n  }\r\n  /*----------------------------- HSI Configuration --------------------------*/ \r\n  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));\r\n    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));\r\n    \r\n    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ \r\n    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) \r\n       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))\r\n    {\r\n      /* When HSI is used as system clock it will not disabled */\r\n      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))\r\n      {\r\n        return HAL_ERROR;\r\n      }\r\n      /* Otherwise, just the calibration is allowed */\r\n      else\r\n      {\r\n        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/\r\n        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* Check the HSI State */\r\n      if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)\r\n      {\r\n        /* Enable the Internal High Speed oscillator (HSI). */\r\n        __HAL_RCC_HSI_ENABLE();\r\n\r\n        /* Get Start Tick*/\r\n        tickstart = HAL_GetTick();\r\n\r\n        /* Wait till HSI is ready */  \r\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)\r\n        {\r\n          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)\r\n          {\r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n                \r\n        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/\r\n        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);\r\n      }\r\n      else\r\n      {\r\n        /* Disable the Internal High Speed oscillator (HSI). */\r\n        __HAL_RCC_HSI_DISABLE();\r\n\r\n        /* Get Start Tick*/\r\n        tickstart = HAL_GetTick();\r\n      \r\n        /* Wait till HSI is ready */  \r\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)\r\n        {\r\n          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)\r\n          {\r\n            return HAL_TIMEOUT;\r\n          } \r\n        } \r\n      }\r\n    }\r\n  }\r\n  /*------------------------------ LSI Configuration -------------------------*/\r\n  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));\r\n\r\n    /* Check the LSI State */\r\n    if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)\r\n    {\r\n      /* Enable the Internal Low Speed oscillator (LSI). */\r\n      __HAL_RCC_LSI_ENABLE();\r\n      \r\n      /* Get Start Tick*/\r\n      tickstart = HAL_GetTick();\r\n      \r\n      /* Wait till LSI is ready */\r\n      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)\r\n      {\r\n        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* Disable the Internal Low Speed oscillator (LSI). */\r\n      __HAL_RCC_LSI_DISABLE();\r\n      \r\n      /* Get Start Tick*/\r\n      tickstart = HAL_GetTick();\r\n      \r\n      /* Wait till LSI is ready */  \r\n      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)\r\n      {\r\n        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n  }\r\n  /*------------------------------ LSE Configuration -------------------------*/ \r\n  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));\r\n    \r\n    /* Enable Power Clock*/\r\n    __HAL_RCC_PWR_CLK_ENABLE();\r\n    \r\n    /* Enable write access to Backup domain */\r\n    PWR->CR1 |= PWR_CR1_DBP;\r\n    \r\n    /* Wait for Backup domain Write protection disable */\r\n    tickstart = HAL_GetTick();\r\n    \r\n    while((PWR->CR1 & PWR_CR1_DBP) == RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }      \r\n    }\r\n\r\n    /* Set the new LSE configuration -----------------------------------------*/\r\n    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);\r\n    /* Check the LSE State */\r\n    if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)\r\n    {\r\n      /* Get Start Tick*/\r\n      tickstart = HAL_GetTick();\r\n      \r\n      /* Wait till LSE is ready */  \r\n      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)\r\n      {\r\n        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }       \r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* Get Start Tick*/\r\n      tickstart = HAL_GetTick();\r\n      \r\n      /* Wait till LSE is ready */  \r\n      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)\r\n      {\r\n        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }       \r\n      }\r\n    }\r\n  }\r\n  /*-------------------------------- PLL Configuration -----------------------*/\r\n  /* Check the parameters */\r\n  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));\r\n  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)\r\n  {\r\n    /* Check if the PLL is used as system clock or not */\r\n    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)\r\n    { \r\n      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)\r\n      {\r\n        /* Check the parameters */\r\n        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));\r\n        assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));\r\n        assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));\r\n        assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));\r\n        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));\r\n        assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));\r\n        \r\n        /* Disable the main PLL. */\r\n        __HAL_RCC_PLL_DISABLE();\r\n        \r\n        /* Get Start Tick*/\r\n        tickstart = HAL_GetTick();\r\n        \r\n        /* Wait till PLL is ready */  \r\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)\r\n        {\r\n          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r\n          {\r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n        \r\n        /* Configure the main PLL clock source, multiplication and division factors. */\r\n        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,\r\n                             RCC_OscInitStruct->PLL.PLLM,\r\n                             RCC_OscInitStruct->PLL.PLLN,\r\n                             RCC_OscInitStruct->PLL.PLLP,\r\n                             RCC_OscInitStruct->PLL.PLLQ,\r\n                             RCC_OscInitStruct->PLL.PLLR);\r\n        \r\n        /* Enable the main PLL. */\r\n        __HAL_RCC_PLL_ENABLE();\r\n\r\n        /* Get Start Tick*/\r\n        tickstart = HAL_GetTick();\r\n        \r\n        /* Wait till PLL is ready */  \r\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)\r\n        {\r\n          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r\n          {\r\n            return HAL_TIMEOUT;\r\n          } \r\n        }\r\n      }\r\n      else\r\n      {\r\n        /* Disable the main PLL. */\r\n        __HAL_RCC_PLL_DISABLE();\r\n \r\n        /* Get Start Tick*/\r\n        tickstart = HAL_GetTick();\r\n        \r\n        /* Wait till PLL is ready */  \r\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)\r\n        {\r\n          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\r\n          {\r\n            return HAL_TIMEOUT;\r\n          }\r\n        }\r\n      }\r\n    }\r\n    else\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n  }\r\n  return HAL_OK;\r\n}\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_RCC_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rng.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_rng.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   RNG HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the Random Number Generator (RNG) peripheral:\r\n  *           + Initialization/de-initialization functions\r\n  *           + Peripheral Control functions \r\n  *           + Peripheral State functions\r\n  *         \r\n  @verbatim\r\n  ==============================================================================\r\n                     ##### How to use this driver #####\r\n  ==============================================================================\r\n  [..]\r\n      The RNG HAL driver can be used as follows:\r\n\r\n      (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro \r\n          in HAL_RNG_MspInit().\r\n      (#) Activate the RNG peripheral using HAL_RNG_Init() function.\r\n      (#) Wait until the 32 bit Random Number Generator contains a valid \r\n          random data using (polling/interrupt) mode.   \r\n      (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.\r\n  \r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup RNG \r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_RNG_MODULE_ENABLED\r\n\r\n/* Private types -------------------------------------------------------------*/\r\n/* Private defines -----------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private constants ---------------------------------------------------------*/\r\n/** @addtogroup RNG_Private_Constants\r\n  * @{\r\n  */\r\n#define RNG_TIMEOUT_VALUE     2\r\n/**\r\n  * @}\r\n  */ \r\n/* Private macros ------------------------------------------------------------*/\r\n/* Private functions prototypes ----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @addtogroup RNG_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup RNG_Exported_Functions_Group1\r\n *  @brief   Initialization and de-initialization functions\r\n *\r\n@verbatim\r\n ===============================================================================\r\n          ##### Initialization and de-initialization functions #####\r\n ===============================================================================\r\n    [..]  This section provides functions allowing to:\r\n      (+) Initialize the RNG according to the specified parameters \r\n          in the RNG_InitTypeDef and create the associated handle\r\n      (+) DeInitialize the RNG peripheral\r\n      (+) Initialize the RNG MSP\r\n      (+) DeInitialize RNG MSP \r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @brief  Initializes the RNG peripheral and creates the associated handle.\r\n  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains\r\n  *                the configuration information for RNG.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)\r\n{ \r\n  /* Check the RNG handle allocation */\r\n  if(hrng == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  __HAL_LOCK(hrng);\r\n  \r\n  if(hrng->State == HAL_RNG_STATE_RESET)\r\n  {  \r\n    /* Allocate lock resource and initialize it */\r\n    hrng->Lock = HAL_UNLOCKED;\r\n\r\n    /* Init the low level hardware */\r\n    HAL_RNG_MspInit(hrng);\r\n  }\r\n  \r\n  /* Change RNG peripheral state */\r\n  hrng->State = HAL_RNG_STATE_BUSY;\r\n\r\n  /* Enable the RNG Peripheral */\r\n  __HAL_RNG_ENABLE(hrng);\r\n\r\n  /* Initialize the RNG state */\r\n  hrng->State = HAL_RNG_STATE_READY;\r\n  \r\n  __HAL_UNLOCK(hrng);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the RNG peripheral. \r\n  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains\r\n  *                the configuration information for RNG.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)\r\n{ \r\n  /* Check the RNG handle allocation */\r\n  if(hrng == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  /* Disable the RNG Peripheral */\r\n  CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN);\r\n  \r\n  /* Clear RNG interrupt status flags */\r\n  CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS);\r\n  \r\n  /* DeInit the low level hardware */\r\n  HAL_RNG_MspDeInit(hrng);\r\n  \r\n  /* Update the RNG state */\r\n  hrng->State = HAL_RNG_STATE_RESET; \r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hrng);\r\n  \r\n  /* Return the function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the RNG MSP.\r\n  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains\r\n  *                the configuration information for RNG.\r\n  * @retval None\r\n  */\r\n__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hrng);\r\n  \r\n  /* NOTE : This function should not be modified. When the callback is needed,\r\n            function HAL_RNG_MspInit must be implemented in the user file.\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the RNG MSP.\r\n  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains\r\n  *                the configuration information for RNG.\r\n  * @retval None\r\n  */\r\n__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hrng);\r\n  \r\n  /* NOTE : This function should not be modified. When the callback is needed,\r\n            function HAL_RNG_MspDeInit must be implemented in the user file.\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup RNG_Exported_Functions_Group2\r\n *  @brief   Peripheral Control functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                      ##### Peripheral Control functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) Get the 32 bit Random number\r\n      (+) Get the 32 bit Random number with interrupt enabled\r\n      (+) Handle RNG interrupt request \r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n   \r\n/**\r\n  * @brief  Generates a 32-bit random number.\r\n  * @note   Each time the random number data is read the RNG_FLAG_DRDY flag \r\n  *         is automatically cleared.\r\n  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains\r\n  *                the configuration information for RNG.\r\n  * @param  random32bit: pointer to generated random number variable if successful.\r\n  * @retval HAL status\r\n  */\r\n\r\nHAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)\r\n{\r\n  uint32_t tickstart = 0;    \r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Process Locked */\r\n  __HAL_LOCK(hrng); \r\n  \r\n  /* Check RNG peripheral state */\r\n  if(hrng->State == HAL_RNG_STATE_READY)\r\n  {\r\n    /* Change RNG peripheral state */  \r\n    hrng->State = HAL_RNG_STATE_BUSY;  \r\n\r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n  \r\n    /* Check if data register contains valid random data */\r\n    while(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE)\r\n      {    \r\n        hrng->State = HAL_RNG_STATE_ERROR;\r\n\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hrng);\r\n      \r\n        return HAL_TIMEOUT;\r\n      } \r\n    }\r\n  \r\n    /* Get a 32bit Random number */\r\n    hrng->RandomNumber = hrng->Instance->DR;\r\n    *random32bit = hrng->RandomNumber;\r\n  \r\n    hrng->State = HAL_RNG_STATE_READY;\r\n  }\r\n  else\r\n  {\r\n    status = HAL_ERROR;\r\n  }\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hrng);\r\n  \r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Generates a 32-bit random number in interrupt mode.\r\n  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains\r\n  *                the configuration information for RNG.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hrng);\r\n  \r\n  /* Check RNG peripheral state */\r\n  if(hrng->State == HAL_RNG_STATE_READY)\r\n  {\r\n    /* Change RNG peripheral state */  \r\n    hrng->State = HAL_RNG_STATE_BUSY;  \r\n  \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hrng);\r\n    \r\n    /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ \r\n    __HAL_RNG_ENABLE_IT(hrng);\r\n  }\r\n  else\r\n  {\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hrng);\r\n    \r\n    status = HAL_ERROR;\r\n  }\r\n  \r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Handles RNG interrupt request.\r\n  * @note   In the case of a clock error, the RNG is no more able to generate \r\n  *         random numbers because the PLL48CLK clock is not correct. User has \r\n  *         to check that the clock controller is correctly configured to provide\r\n  *         the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT(). \r\n  *         The clock error has no impact on the previously generated \r\n  *         random numbers, and the RNG_DR register contents can be used.\r\n  * @note   In the case of a seed error, the generation of random numbers is \r\n  *         interrupted as long as the SECS bit is '1'. If a number is \r\n  *         available in the RNG_DR register, it must not be used because it may \r\n  *         not have enough entropy. In this case, it is recommended to clear the \r\n  *         SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable \r\n  *         the RNG peripheral to reinitialize and restart the RNG.\r\n  * @note   User-written HAL_RNG_ErrorCallback() API is called once whether SEIS\r\n  *         or CEIS are set.  \r\n  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains\r\n  *                the configuration information for RNG.\r\n  * @retval None\r\n\r\n  */\r\nvoid HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)\r\n{\r\n  /* RNG clock error interrupt occurred */\r\n  if((__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) ||  (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET))\r\n  { \r\n    /* Change RNG peripheral state */\r\n    hrng->State = HAL_RNG_STATE_ERROR;\r\n  \r\n    HAL_RNG_ErrorCallback(hrng);\r\n    \r\n    /* Clear the clock error flag */\r\n    __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI|RNG_IT_SEI);\r\n    \r\n  }\r\n  \r\n  /* Check RNG data ready interrupt occurred */    \r\n  if(__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)\r\n  {\r\n    /* Generate random number once, so disable the IT */\r\n    __HAL_RNG_DISABLE_IT(hrng);\r\n    \r\n    /* Get the 32bit Random number (DRDY flag automatically cleared) */ \r\n    hrng->RandomNumber = hrng->Instance->DR;\r\n    \r\n    if(hrng->State != HAL_RNG_STATE_ERROR)\r\n    {\r\n      /* Change RNG peripheral state */\r\n      hrng->State = HAL_RNG_STATE_READY; \r\n      \r\n      /* Data Ready callback */ \r\n      HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);\r\n    } \r\n  }\r\n} \r\n\r\n/**\r\n  * @brief  Returns generated random number in polling mode (Obsolete)\r\n  *         Use HAL_RNG_GenerateRandomNumber() API instead.\r\n  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains\r\n  *                the configuration information for RNG.\r\n  * @retval Random value\r\n  */\r\nuint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng)\r\n{\r\n  if(HAL_RNG_GenerateRandomNumber(hrng, &(hrng->RandomNumber)) == HAL_OK)\r\n  {\r\n    return hrng->RandomNumber; \r\n  }\r\n  else\r\n  {\r\n    return 0;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Returns a 32-bit random number with interrupt enabled (Obsolete),\r\n  *         Use HAL_RNG_GenerateRandomNumber_IT() API instead.\r\n  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains\r\n  *                the configuration information for RNG.\r\n  * @retval 32-bit random number\r\n  */\r\nuint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)\r\n{\r\n  uint32_t random32bit = 0;\r\n  \r\n  /* Process locked */\r\n  __HAL_LOCK(hrng);\r\n  \r\n  /* Change RNG peripheral state */  \r\n  hrng->State = HAL_RNG_STATE_BUSY;  \r\n  \r\n  /* Get a 32bit Random number */ \r\n  random32bit = hrng->Instance->DR;\r\n  \r\n  /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ \r\n  __HAL_RNG_ENABLE_IT(hrng); \r\n  \r\n  /* Return the 32 bit random number */   \r\n  return random32bit;\r\n}\r\n\r\n/**\r\n  * @brief  Read latest generated random number. \r\n  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains\r\n  *                the configuration information for RNG.\r\n  * @retval random value\r\n  */\r\nuint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)\r\n{\r\n  return(hrng->RandomNumber);\r\n}\r\n\r\n/**\r\n  * @brief  Data Ready callback in non-blocking mode. \r\n  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains\r\n  *                the configuration information for RNG.\r\n  * @param  random32bit: generated random number.\r\n  * @retval None\r\n  */\r\n__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hrng);\r\n  \r\n  /* NOTE : This function should not be modified. When the callback is needed,\r\n            function HAL_RNG_ReadyDataCallback must be implemented in the user file.\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  RNG error callbacks.\r\n  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains\r\n  *                the configuration information for RNG.\r\n  * @retval None\r\n  */\r\n__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hrng);\r\n  \r\n  /* NOTE : This function should not be modified. When the callback is needed,\r\n            function HAL_RNG_ErrorCallback must be implemented in the user file.\r\n   */\r\n}\r\n/**\r\n  * @}\r\n  */ \r\n\r\n  \r\n/** @addtogroup RNG_Exported_Functions_Group3\r\n *  @brief   Peripheral State functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                      ##### Peripheral State functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection permits to get in run-time the status of the peripheral \r\n    and the data flow.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @brief  Returns the RNG state.\r\n  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains\r\n  *                the configuration information for RNG.\r\n  * @retval HAL state\r\n  */\r\nHAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)\r\n{\r\n  return hrng->State;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_RNG_MODULE_ENABLED */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_rtc.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   RTC HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the Real Time Clock (RTC) peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + RTC Time and Date functions\r\n  *           + RTC Alarm functions\r\n  *           + Peripheral Control functions   \r\n  *           + Peripheral State functions\r\n  *         \r\n  @verbatim\r\n  ==============================================================================\r\n              ##### Backup Domain Operating Condition #####\r\n  ==============================================================================\r\n  [..] The real-time clock (RTC), the RTC backup registers, and the backup \r\n       SRAM (BKP SRAM) can be powered from the VBAT voltage when the main \r\n       VDD supply is powered off.\r\n       To retain the content of the RTC backup registers, backup SRAM, and supply \r\n       the RTC when VDD is turned off, VBAT pin can be connected to an optional \r\n       standby voltage supplied by a battery or by another source.\r\n\r\n  [..] To allow the RTC operating even when the main digital supply (VDD) is turned\r\n       off, the VBAT pin powers the following blocks:\r\n    (#) The RTC\r\n    (#) The LSE oscillator\r\n    (#) The backup SRAM when the low power backup regulator is enabled\r\n    (#) PC13 to PC15 I/Os, plus PI8 I/O (when available)\r\n  \r\n  [..] When the backup domain is supplied by VDD (analog switch connected to VDD),\r\n       the following pins are available:\r\n    (#) PC14 and PC15 can be used as either GPIO or LSE pins\r\n    (#) PC13 can be used as a GPIO or as the RTC_AF1 pin\r\n    (#) PI8 can be used as a GPIO or as the RTC_AF2 pin\r\n  \r\n  [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT \r\n       because VDD is not present), the following pins are available:\r\n    (#) PC14 and PC15 can be used as LSE pins only\r\n    (#) PC13 can be used as the RTC_AF1 pin \r\n    (#) PI8 can be used as the RTC_AF2 pin\r\n    (#) PC1 can be used as the RTC_AF3 pin\r\n             \r\n                   ##### Backup Domain Reset #####\r\n  ==================================================================\r\n  [..] The backup domain reset sets all RTC registers and the RCC_BDCR register \r\n       to their reset values. The BKPSRAM is not affected by this reset. The only\r\n       way to reset the BKPSRAM is through the Flash interface by requesting \r\n       a protection level change from 1 to 0.\r\n  [..] A backup domain reset is generated when one of the following events occurs:\r\n    (#) Software reset, triggered by setting the BDRST bit in the \r\n        RCC Backup domain control register (RCC_BDCR). \r\n    (#) VDD or VBAT power on, if both supplies have previously been powered off.  \r\n\r\n                   ##### Backup Domain Access #####\r\n  ==================================================================\r\n  [..] After reset, the backup domain (RTC registers, RTC backup data \r\n       registers and backup SRAM) is protected against possible unwanted write \r\n       accesses. \r\n  [..] To enable access to the RTC Domain and RTC registers, proceed as follows:\r\n    (+) Enable the Power Controller (PWR) APB1 interface clock using the\r\n        __HAL_RCC_PWR_CLK_ENABLE() function.\r\n    (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.\r\n    (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.\r\n    (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.\r\n  \r\n  \r\n                  ##### How to use this driver #####\r\n  ==================================================================\r\n  [..] \r\n    (+) Enable the RTC domain access (see description in the section above).\r\n    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour \r\n        format using the HAL_RTC_Init() function.\r\n  \r\n  *** Time and Date configuration ***\r\n  ===================================\r\n  [..] \r\n    (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime() \r\n        and HAL_RTC_SetDate() functions.\r\n    (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions. \r\n  \r\n  *** Alarm configuration ***\r\n  ===========================\r\n  [..]\r\n    (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function. \r\n        You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function.\r\n    (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.\r\n  \r\n                  ##### RTC and low power modes #####\r\n  ==================================================================\r\n  [..] The MCU can be woken up from a low power mode by an RTC alternate \r\n       function.\r\n  [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), \r\n       RTC wakeup, RTC tamper event detection and RTC time stamp event detection.\r\n       These RTC alternate functions can wake up the system from the Stop and \r\n       Standby low power modes.\r\n  [..] The system can also wake up from low power modes without depending \r\n       on an external interrupt (Auto-wakeup mode), by using the RTC alarm \r\n       or the RTC wakeup events.\r\n  [..] The RTC provides a programmable time base for waking up from the \r\n       Stop or Standby mode at regular intervals.\r\n       Wakeup from STOP and STANDBY modes is possible only when the RTC clock source\r\n       is LSE or LSI.\r\n     \r\n   @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup RTC RTC\r\n  * @brief RTC HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_RTC_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup RTC_Exported_Functions RTC Exported Functions\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup RTC_Group1 Initialization and de-initialization functions \r\n *  @brief    Initialization and Configuration functions \r\n *\r\n@verbatim    \r\n ===============================================================================\r\n              ##### Initialization and de-initialization functions #####\r\n ===============================================================================\r\n   [..] This section provides functions allowing to initialize and configure the \r\n         RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable \r\n         RTC registers Write protection, enter and exit the RTC initialization mode, \r\n         RTC registers synchronization check and reference clock detection enable.\r\n         (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. \r\n             It is split into 2 programmable prescalers to minimize power consumption.\r\n             (++) A 7-bit asynchronous prescaler and a 13-bit synchronous prescaler.\r\n             (++) When both prescalers are used, it is recommended to configure the \r\n                 asynchronous prescaler to a high value to minimize power consumption.\r\n         (#) All RTC registers are Write protected. Writing to the RTC registers\r\n             is enabled by writing a key into the Write Protection register, RTC_WPR.\r\n         (#) To configure the RTC Calendar, user application should enter \r\n             initialization mode. In this mode, the calendar counter is stopped \r\n             and its value can be updated. When the initialization sequence is \r\n             complete, the calendar restarts counting after 4 RTCCLK cycles.\r\n         (#) To read the calendar through the shadow registers after Calendar \r\n             initialization, calendar update or after wakeup from low power modes \r\n             the software must first clear the RSF flag. The software must then \r\n             wait until it is set again before reading the calendar, which means \r\n             that the calendar registers have been correctly copied into the \r\n             RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function \r\n             implements the above software sequence (RSF clear and RSF check).\r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the RTC peripheral \r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)\r\n{\r\n  /* Check the RTC peripheral state */\r\n  if(hrtc == NULL)\r\n  {\r\n     return HAL_ERROR;\r\n  }\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));\r\n  assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));\r\n  assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));\r\n  assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv));\r\n  assert_param (IS_RTC_OUTPUT(hrtc->Init.OutPut));\r\n  assert_param (IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));\r\n  assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));\r\n    \r\n  if(hrtc->State == HAL_RTC_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    hrtc->Lock = HAL_UNLOCKED;\r\n    /* Initialize RTC MSP */\r\n    HAL_RTC_MspInit(hrtc);\r\n  }\r\n  \r\n  /* Set RTC state */  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;  \r\n       \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n\r\n  /* Set Initialization mode */\r\n  if(RTC_EnterInitMode(hrtc) != HAL_OK)\r\n  {\r\n    /* Enable the write protection for RTC registers */\r\n    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r\n    \r\n    /* Set RTC state */\r\n    hrtc->State = HAL_RTC_STATE_ERROR;\r\n    \r\n    return HAL_ERROR;\r\n  } \r\n  else\r\n  { \r\n    /* Clear RTC_CR FMT, OSEL and POL Bits */\r\n    hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));\r\n    /* Set RTC_CR register */\r\n    hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);\r\n    \r\n    /* Configure the RTC PRER */\r\n    hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);\r\n    hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16);\r\n    \r\n    /* Exit Initialization mode */\r\n    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; \r\n    \r\n    hrtc->Instance->OR &= (uint32_t)~RTC_OR_ALARMTYPE;\r\n    hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType); \r\n    \r\n    /* Enable the write protection for RTC registers */\r\n    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r\n    \r\n    /* Set RTC state */\r\n    hrtc->State = HAL_RTC_STATE_READY;\r\n    \r\n    return HAL_OK;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the RTC peripheral \r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @note   This function doesn't reset the RTC Backup Data registers.   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));\r\n\r\n  /* Set RTC state */\r\n  hrtc->State = HAL_RTC_STATE_BUSY; \r\n  \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  /* Set Initialization mode */\r\n  if(RTC_EnterInitMode(hrtc) != HAL_OK)\r\n  {\r\n    /* Enable the write protection for RTC registers */\r\n    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r\n    \r\n    /* Set RTC state */\r\n    hrtc->State = HAL_RTC_STATE_ERROR;\r\n    \r\n    return HAL_ERROR;\r\n  }  \r\n  else\r\n  {\r\n    /* Reset TR, DR and CR registers */\r\n    hrtc->Instance->TR = (uint32_t)0x00000000;\r\n    hrtc->Instance->DR = (uint32_t)0x00002101;\r\n    /* Reset All CR bits except CR[2:0] */\r\n    hrtc->Instance->CR &= (uint32_t)0x00000007;\r\n\r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n    /* Wait till WUTWF flag is set and if Time out is reached exit */\r\n    while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r\n      { \r\n        /* Enable the write protection for RTC registers */\r\n        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r\n        \r\n        /* Set RTC state */\r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT;\r\n        \r\n        return HAL_TIMEOUT;\r\n      }      \r\n    }\r\n    \r\n    /* Reset all RTC CR register bits */\r\n    hrtc->Instance->CR &= (uint32_t)0x00000000;\r\n    hrtc->Instance->WUTR = (uint32_t)0x0000FFFF;\r\n    hrtc->Instance->PRER = (uint32_t)0x007F00FF;\r\n    hrtc->Instance->ALRMAR = (uint32_t)0x00000000;\r\n    hrtc->Instance->ALRMBR = (uint32_t)0x00000000;\r\n    hrtc->Instance->SHIFTR = (uint32_t)0x00000000;\r\n    hrtc->Instance->CALR = (uint32_t)0x00000000;\r\n    hrtc->Instance->ALRMASSR = (uint32_t)0x00000000;\r\n    hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000;\r\n    \r\n    /* Reset ISR register and exit initialization mode */\r\n    hrtc->Instance->ISR = (uint32_t)0x00000000;\r\n    \r\n    /* Reset Tamper and alternate functions configuration register */\r\n    hrtc->Instance->TAMPCR = 0x00000000;\r\n    \r\n    /* Reset Option register */\r\n    hrtc->Instance->OR = 0x00000000;\r\n    \r\n    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */\r\n    if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)\r\n    {\r\n      if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)\r\n      {\r\n        /* Enable the write protection for RTC registers */\r\n        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  \r\n        \r\n        hrtc->State = HAL_RTC_STATE_ERROR;\r\n        \r\n        return HAL_ERROR;\r\n      }\r\n    }    \r\n  }\r\n  \r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n  \r\n  /* De-Initialize RTC MSP */\r\n  HAL_RTC_MspDeInit(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_RESET; \r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hrtc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the RTC MSP.\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.  \r\n  * @retval None\r\n  */\r\n__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hrtc);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_RTC_MspInit could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the RTC MSP.\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC. \r\n  * @retval None\r\n  */\r\n__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hrtc);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_RTC_MspDeInit could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RTC_Group2 RTC Time and Date functions\r\n *  @brief   RTC Time and Date functions\r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                 ##### RTC Time and Date functions #####\r\n ===============================================================================  \r\n \r\n [..] This section provides functions allowing to configure Time and Date features\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Sets RTC current time.\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  sTime: Pointer to Time structure\r\n  * @param  Format: Specifies the format of the entered parameters.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg FORMAT_BIN: Binary data format \r\n  *            @arg FORMAT_BCD: BCD data format\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)\r\n{\r\n  uint32_t tmpreg = 0;\r\n  \r\n /* Check the parameters */\r\n  assert_param(IS_RTC_FORMAT(Format));\r\n  assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));\r\n  assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));\r\n  \r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n  if(Format == RTC_FORMAT_BIN)\r\n  {\r\n    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)\r\n    {\r\n      assert_param(IS_RTC_HOUR12(sTime->Hours));\r\n      assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));\r\n    } \r\n    else\r\n    {\r\n      sTime->TimeFormat = 0x00;\r\n      assert_param(IS_RTC_HOUR24(sTime->Hours));\r\n    }\r\n    assert_param(IS_RTC_MINUTES(sTime->Minutes));\r\n    assert_param(IS_RTC_SECONDS(sTime->Seconds));\r\n    \r\n    tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \\\r\n                        ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \\\r\n                        ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \\\r\n                        (((uint32_t)sTime->TimeFormat) << 16));  \r\n  }\r\n  else\r\n  {\r\n    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)\r\n    {\r\n      tmpreg = RTC_Bcd2ToByte(sTime->Hours);\r\n      assert_param(IS_RTC_HOUR12(tmpreg));\r\n      assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); \r\n    } \r\n    else\r\n    {\r\n      sTime->TimeFormat = 0x00;\r\n      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));\r\n    }\r\n    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));\r\n    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));\r\n    tmpreg = (((uint32_t)(sTime->Hours) << 16) | \\\r\n              ((uint32_t)(sTime->Minutes) << 8) | \\\r\n              ((uint32_t)sTime->Seconds) | \\\r\n              ((uint32_t)(sTime->TimeFormat) << 16));   \r\n  }\r\n  \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  /* Set Initialization mode */\r\n  if(RTC_EnterInitMode(hrtc) != HAL_OK)\r\n  {\r\n    /* Enable the write protection for RTC registers */\r\n    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r\n    \r\n    /* Set RTC state */\r\n    hrtc->State = HAL_RTC_STATE_ERROR;\r\n    \r\n    /* Process Unlocked */ \r\n    __HAL_UNLOCK(hrtc);\r\n    \r\n    return HAL_ERROR;\r\n  } \r\n  else\r\n  {\r\n    /* Set the RTC_TR register */\r\n    hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);\r\n     \r\n    /* Clear the bits to be configured */\r\n    hrtc->Instance->CR &= (uint32_t)~RTC_CR_BCK;\r\n    \r\n    /* Configure the RTC_CR register */\r\n    hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);\r\n    \r\n    /* Exit Initialization mode */\r\n    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;  \r\n    \r\n    /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */\r\n    if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)\r\n    {\r\n      if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)\r\n      {        \r\n        /* Enable the write protection for RTC registers */\r\n        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  \r\n        \r\n        hrtc->State = HAL_RTC_STATE_ERROR;\r\n        \r\n        /* Process Unlocked */ \r\n        __HAL_UNLOCK(hrtc);\r\n        \r\n        return HAL_ERROR;\r\n      }\r\n    }\r\n    \r\n    /* Enable the write protection for RTC registers */\r\n    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n    \r\n   hrtc->State = HAL_RTC_STATE_READY;\r\n  \r\n   __HAL_UNLOCK(hrtc); \r\n     \r\n   return HAL_OK;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Gets RTC current time.\r\n  * @param  hrtc: RTC handle\r\n  * @param  sTime: Pointer to Time structure with Hours, Minutes and Seconds fields returned \r\n  *                with input format (BIN or BCD), also SubSeconds field returning the\r\n  *                RTC_SSR register content and SecondFraction field the Synchronous pre-scaler\r\n  *                factor to be used for second fraction ratio computation.\r\n  * @param  Format: Specifies the format of the entered parameters.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RTC_FORMAT_BIN: Binary data format \r\n  *            @arg RTC_FORMAT_BCD: BCD data format\r\n  * @note  You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds\r\n  *        value in second fraction ratio with time unit following generic formula:\r\n  *        Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit\r\n  *        This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS\r\n  * @note  You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values \r\n  *        in the higher-order calendar shadow registers to ensure consistency between the time and date values.\r\n  *        Reading RTC current time locks the values in calendar shadow registers until Current date is read\r\n  *        to ensure consistency between the time and date values.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)\r\n{\r\n  uint32_t tmpreg = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_FORMAT(Format));\r\n  \r\n  /* Get subseconds values from the correspondent registers*/\r\n  sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR);\r\n  \r\n  /* Get SecondFraction structure field from the corresponding register field*/\r\n  sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S);\r\n\r\n  /* Get the TR register */\r\n  tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK); \r\n  \r\n  /* Fill the structure fields with the read parameters */\r\n  sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);\r\n  sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);\r\n  sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));\r\n  sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); \r\n  \r\n  /* Check the input parameters format */\r\n  if(Format == RTC_FORMAT_BIN)\r\n  {\r\n    /* Convert the time structure parameters to Binary format */\r\n    sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);\r\n    sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes);\r\n    sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);  \r\n  }\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Sets RTC current date.\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  sDate: Pointer to date structure\r\n  * @param  Format: specifies the format of the entered parameters.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RTC_FORMAT_BIN: Binary data format \r\n  *            @arg RTC_FORMAT_BCD: BCD data format\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)\r\n{\r\n  uint32_t datetmpreg = 0;\r\n  \r\n /* Check the parameters */\r\n  assert_param(IS_RTC_FORMAT(Format));\r\n  \r\n /* Process Locked */ \r\n __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY; \r\n  \r\n  if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U))\r\n  {\r\n    sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU);\r\n  }\r\n  \r\n  assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));\r\n  \r\n  if(Format == RTC_FORMAT_BIN)\r\n  {   \r\n    assert_param(IS_RTC_YEAR(sDate->Year));\r\n    assert_param(IS_RTC_MONTH(sDate->Month));\r\n    assert_param(IS_RTC_DATE(sDate->Date)); \r\n    \r\n   datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \\\r\n                 ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \\\r\n                 ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \\\r\n                 ((uint32_t)sDate->WeekDay << 13));   \r\n  }\r\n  else\r\n  {   \r\n    assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));\r\n    datetmpreg = RTC_Bcd2ToByte(sDate->Month);\r\n    assert_param(IS_RTC_MONTH(datetmpreg));\r\n    datetmpreg = RTC_Bcd2ToByte(sDate->Date);\r\n    assert_param(IS_RTC_DATE(datetmpreg));\r\n    \r\n    datetmpreg = ((((uint32_t)sDate->Year) << 16) | \\\r\n                  (((uint32_t)sDate->Month) << 8) | \\\r\n                  ((uint32_t)sDate->Date) | \\\r\n                  (((uint32_t)sDate->WeekDay) << 13));  \r\n  }\r\n\r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  /* Set Initialization mode */\r\n  if(RTC_EnterInitMode(hrtc) != HAL_OK)\r\n  {\r\n    /* Enable the write protection for RTC registers */\r\n    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r\n    \r\n    /* Set RTC state*/\r\n    hrtc->State = HAL_RTC_STATE_ERROR;\r\n    \r\n    /* Process Unlocked */ \r\n    __HAL_UNLOCK(hrtc);\r\n    \r\n    return HAL_ERROR;\r\n  } \r\n  else\r\n  {\r\n    /* Set the RTC_DR register */\r\n    hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);\r\n    \r\n    /* Exit Initialization mode */\r\n    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;  \r\n    \r\n    /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */\r\n    if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)\r\n    {\r\n      if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)\r\n      { \r\n        /* Enable the write protection for RTC registers */\r\n        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  \r\n        \r\n        hrtc->State = HAL_RTC_STATE_ERROR;\r\n        \r\n        /* Process Unlocked */ \r\n        __HAL_UNLOCK(hrtc);\r\n        \r\n        return HAL_ERROR;\r\n      }\r\n    }\r\n    \r\n    /* Enable the write protection for RTC registers */\r\n    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  \r\n    \r\n    hrtc->State = HAL_RTC_STATE_READY ;\r\n    \r\n    /* Process Unlocked */ \r\n    __HAL_UNLOCK(hrtc);\r\n    \r\n    return HAL_OK;    \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Gets RTC current date.\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  sDate: Pointer to Date structure\r\n  * @param  Format: Specifies the format of the entered parameters.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RTC_FORMAT_BIN:  Binary data format \r\n  *            @arg RTC_FORMAT_BCD:  BCD data format\r\n  * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values \r\n  * in the higher-order calendar shadow registers to ensure consistency between the time and date values.\r\n  * Reading RTC current time locks the values in calendar shadow registers until Current date is read.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)\r\n{\r\n  uint32_t datetmpreg = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_FORMAT(Format));\r\n          \r\n  /* Get the DR register */\r\n  datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK); \r\n\r\n  /* Fill the structure fields with the read parameters */\r\n  sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);\r\n  sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);\r\n  sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU));\r\n  sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13); \r\n\r\n  /* Check the input parameters format */\r\n  if(Format == RTC_FORMAT_BIN)\r\n  {    \r\n    /* Convert the date structure parameters to Binary format */\r\n    sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);\r\n    sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);\r\n    sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);  \r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RTC_Group3 RTC Alarm functions\r\n *  @brief   RTC Alarm functions\r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                 ##### RTC Alarm functions #####\r\n ===============================================================================  \r\n \r\n [..] This section provides functions allowing to configure Alarm feature\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n/**\r\n  * @brief  Sets the specified RTC Alarm.\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  sAlarm: Pointer to Alarm structure\r\n  * @param  Format: Specifies the format of the entered parameters.\r\n  *          This parameter can be one of the following values:\r\n  *             @arg FORMAT_BIN: Binary data format \r\n  *             @arg FORMAT_BCD: BCD data format\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)\r\n{\r\n  uint32_t tickstart = 0;\r\n  uint32_t tmpreg = 0, subsecondtmpreg = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_FORMAT(Format));\r\n  assert_param(IS_RTC_ALARM(sAlarm->Alarm));\r\n  assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));\r\n  assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));\r\n  assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));\r\n  assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));\r\n  \r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n  if(Format == RTC_FORMAT_BIN)\r\n  {\r\n    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)\r\n    {\r\n      assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));\r\n      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));\r\n    } \r\n    else\r\n    {\r\n      sAlarm->AlarmTime.TimeFormat = 0x00;\r\n      assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));\r\n    }\r\n    assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));\r\n    assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));\r\n    \r\n    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)\r\n    {\r\n      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));\r\n    }\r\n    else\r\n    {\r\n      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));\r\n    }\r\n    \r\n    tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \\\r\n              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \\\r\n              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \\\r\n              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \\\r\n              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \\\r\n              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \\\r\n              ((uint32_t)sAlarm->AlarmMask)); \r\n  }\r\n  else\r\n  {\r\n    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)\r\n    {\r\n      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);\r\n      assert_param(IS_RTC_HOUR12(tmpreg));\r\n      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));\r\n    } \r\n    else\r\n    {\r\n      sAlarm->AlarmTime.TimeFormat = 0x00;\r\n      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));\r\n    }\r\n    \r\n    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));\r\n    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));\r\n    \r\n    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)\r\n    {\r\n      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);\r\n      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));    \r\n    }\r\n    else\r\n    {\r\n      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);\r\n      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));      \r\n    }  \r\n    \r\n    tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \\\r\n              ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \\\r\n              ((uint32_t) sAlarm->AlarmTime.Seconds) | \\\r\n              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \\\r\n              ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \\\r\n              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \\\r\n              ((uint32_t)sAlarm->AlarmMask));   \r\n  }\r\n  \r\n  /* Configure the Alarm A or Alarm B Sub Second registers */\r\n  subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));\r\n  \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n\r\n  /* Configure the Alarm register */\r\n  if(sAlarm->Alarm == RTC_ALARM_A)\r\n  {\r\n    /* Disable the Alarm A interrupt */\r\n    __HAL_RTC_ALARMA_DISABLE(hrtc);\r\n    \r\n    /* In case of interrupt mode is used, the interrupt source must disabled */ \r\n    __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);\r\n\r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n    /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */\r\n    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r\n      {\r\n        /* Enable the write protection for RTC registers */\r\n        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n        \r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT; \r\n        \r\n        /* Process Unlocked */ \r\n        __HAL_UNLOCK(hrtc);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }   \r\n    }\r\n    \r\n    hrtc->Instance->ALRMAR = (uint32_t)tmpreg;\r\n    /* Configure the Alarm A Sub Second register */\r\n    hrtc->Instance->ALRMASSR = subsecondtmpreg;\r\n    /* Configure the Alarm state: Enable Alarm */\r\n    __HAL_RTC_ALARMA_ENABLE(hrtc);\r\n  }\r\n  else\r\n  {\r\n    /* Disable the Alarm B interrupt */\r\n    __HAL_RTC_ALARMB_DISABLE(hrtc);\r\n    \r\n    /* In case of interrupt mode is used, the interrupt source must disabled */ \r\n    __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);\r\n\r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n    /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */\r\n    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r\n      {\r\n        /* Enable the write protection for RTC registers */\r\n        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n        \r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT; \r\n        \r\n        /* Process Unlocked */ \r\n        __HAL_UNLOCK(hrtc);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }  \r\n    }    \r\n    \r\n    hrtc->Instance->ALRMBR = (uint32_t)tmpreg;\r\n    /* Configure the Alarm B Sub Second register */\r\n    hrtc->Instance->ALRMBSSR = subsecondtmpreg;\r\n    /* Configure the Alarm state: Enable Alarm */\r\n    __HAL_RTC_ALARMB_ENABLE(hrtc); \r\n  }\r\n  \r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);   \r\n  \r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY; \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Sets the specified RTC Alarm with Interrupt \r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  sAlarm: Pointer to Alarm structure\r\n  * @param  Format: Specifies the format of the entered parameters.\r\n  *          This parameter can be one of the following values:\r\n  *             @arg FORMAT_BIN: Binary data format \r\n  *             @arg FORMAT_BCD: BCD data format\r\n  * @note   The Alarm register can only be written when the corresponding Alarm\r\n  *         is disabled (Use the HAL_RTC_DeactivateAlarm()).   \r\n  * @note   The HAL_RTC_SetTime() must be called before enabling the Alarm feature.   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)\r\n{\r\n  uint32_t tickstart = 0;\r\n  uint32_t tmpreg = 0, subsecondtmpreg = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_FORMAT(Format));\r\n  assert_param(IS_RTC_ALARM(sAlarm->Alarm));\r\n  assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));\r\n  assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));\r\n  assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));\r\n  assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));\r\n      \r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n  if(Format == RTC_FORMAT_BIN)\r\n  {\r\n    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)\r\n    {\r\n      assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));\r\n      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));\r\n    } \r\n    else\r\n    {\r\n      sAlarm->AlarmTime.TimeFormat = 0x00;\r\n      assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));\r\n    }\r\n    assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));\r\n    assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));\r\n    \r\n    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)\r\n    {\r\n      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));\r\n    }\r\n    else\r\n    {\r\n      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));\r\n    }\r\n    tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \\\r\n              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \\\r\n              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \\\r\n              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \\\r\n              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \\\r\n              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \\\r\n              ((uint32_t)sAlarm->AlarmMask)); \r\n  }\r\n  else\r\n  {\r\n    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)\r\n    {\r\n      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);\r\n      assert_param(IS_RTC_HOUR12(tmpreg));\r\n      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));\r\n    } \r\n    else\r\n    {\r\n      sAlarm->AlarmTime.TimeFormat = 0x00;\r\n      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));\r\n    }\r\n    \r\n    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));\r\n    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));\r\n    \r\n    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)\r\n    {\r\n      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);\r\n      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));    \r\n    }\r\n    else\r\n    {\r\n      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);\r\n      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));      \r\n    }\r\n    tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \\\r\n              ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \\\r\n              ((uint32_t) sAlarm->AlarmTime.Seconds) | \\\r\n              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \\\r\n              ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \\\r\n              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \\\r\n              ((uint32_t)sAlarm->AlarmMask));     \r\n  }\r\n  /* Configure the Alarm A or Alarm B Sub Second registers */\r\n  subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));\r\n  \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  /* Configure the Alarm register */\r\n  if(sAlarm->Alarm == RTC_ALARM_A)\r\n  {\r\n    /* Disable the Alarm A interrupt */\r\n    __HAL_RTC_ALARMA_DISABLE(hrtc);\r\n\r\n    /* Clear flag alarm A */\r\n    __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);\r\n\r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n    /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */\r\n    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r\n      {\r\n        /* Enable the write protection for RTC registers */\r\n        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n        \r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT; \r\n        \r\n        /* Process Unlocked */ \r\n        __HAL_UNLOCK(hrtc);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }  \r\n    }\r\n    \r\n    hrtc->Instance->ALRMAR = (uint32_t)tmpreg;\r\n    /* Configure the Alarm A Sub Second register */\r\n    hrtc->Instance->ALRMASSR = subsecondtmpreg;\r\n    /* Configure the Alarm state: Enable Alarm */\r\n    __HAL_RTC_ALARMA_ENABLE(hrtc);\r\n    /* Configure the Alarm interrupt */\r\n    __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA);\r\n  }\r\n  else\r\n  {\r\n    /* Disable the Alarm B interrupt */\r\n    __HAL_RTC_ALARMB_DISABLE(hrtc);\r\n\r\n    /* Clear flag alarm B */\r\n    __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);\r\n\r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n    /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */\r\n    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r\n      {\r\n        /* Enable the write protection for RTC registers */\r\n        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n        \r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT; \r\n        \r\n        /* Process Unlocked */ \r\n        __HAL_UNLOCK(hrtc);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }  \r\n    }\r\n\r\n    hrtc->Instance->ALRMBR = (uint32_t)tmpreg;\r\n    /* Configure the Alarm B Sub Second register */\r\n    hrtc->Instance->ALRMBSSR = subsecondtmpreg;\r\n    /* Configure the Alarm state: Enable Alarm */\r\n    __HAL_RTC_ALARMB_ENABLE(hrtc);\r\n    /* Configure the Alarm interrupt */\r\n    __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB);\r\n  }\r\n\r\n  /* RTC Alarm Interrupt Configuration: EXTI configuration */\r\n  __HAL_RTC_ALARM_EXTI_ENABLE_IT();\r\n  \r\n  EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT;\r\n  \r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  \r\n  \r\n  hrtc->State = HAL_RTC_STATE_READY; \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);  \r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Deactive the specified RTC Alarm \r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  Alarm: Specifies the Alarm.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg RTC_ALARM_A:  AlarmA\r\n  *            @arg RTC_ALARM_B:  AlarmB\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_ALARM(Alarm));\r\n  \r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  if(Alarm == RTC_ALARM_A)\r\n  {\r\n    /* AlarmA */\r\n    __HAL_RTC_ALARMA_DISABLE(hrtc);\r\n    \r\n    /* In case of interrupt mode is used, the interrupt source must disabled */ \r\n    __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);\r\n\r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n    /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */\r\n    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r\n      { \r\n        /* Enable the write protection for RTC registers */\r\n        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n        \r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT; \r\n        \r\n        /* Process Unlocked */ \r\n        __HAL_UNLOCK(hrtc);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }      \r\n    }\r\n  }\r\n  else\r\n  {\r\n    /* AlarmB */\r\n    __HAL_RTC_ALARMB_DISABLE(hrtc);\r\n    \r\n    /* In case of interrupt mode is used, the interrupt source must disabled */ \r\n    __HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB);\r\n\r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n    /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */\r\n    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r\n      {\r\n        /* Enable the write protection for RTC registers */\r\n        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n        \r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT; \r\n        \r\n        /* Process Unlocked */ \r\n        __HAL_UNLOCK(hrtc);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }    \r\n    }\r\n  }\r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_READY; \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);  \r\n  \r\n  return HAL_OK; \r\n}\r\n           \r\n/**\r\n  * @brief  Gets the RTC Alarm value and masks.\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  sAlarm: Pointer to Date structure\r\n  * @param  Alarm: Specifies the Alarm.\r\n  *          This parameter can be one of the following values:\r\n  *             @arg RTC_ALARM_A: AlarmA\r\n  *             @arg RTC_ALARM_B: AlarmB  \r\n  * @param  Format: Specifies the format of the entered parameters.\r\n  *          This parameter can be one of the following values:\r\n  *             @arg RTC_FORMAT_BIN: Binary data format \r\n  *             @arg RTC_FORMAT_BCD: BCD data format\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)\r\n{\r\n  uint32_t tmpreg = 0, subsecondtmpreg = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_FORMAT(Format));\r\n  assert_param(IS_RTC_ALARM(Alarm));\r\n  \r\n  if(Alarm == RTC_ALARM_A)\r\n  {\r\n    /* AlarmA */\r\n    sAlarm->Alarm = RTC_ALARM_A;\r\n    \r\n    tmpreg = (uint32_t)(hrtc->Instance->ALRMAR);\r\n    subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS);\r\n  }\r\n  else\r\n  {\r\n    sAlarm->Alarm = RTC_ALARM_B;\r\n    \r\n    tmpreg = (uint32_t)(hrtc->Instance->ALRMBR);\r\n    subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS);\r\n  }\r\n    \r\n  /* Fill the structure with the read parameters */\r\n  sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16);\r\n  sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8);\r\n  sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU));\r\n  sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);\r\n  sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;\r\n  sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);\r\n  sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);\r\n  sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);\r\n    \r\n  if(Format == RTC_FORMAT_BIN)\r\n  {\r\n    sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);\r\n    sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);\r\n    sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);\r\n    sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);\r\n  }  \r\n    \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  This function handles Alarm interrupt request.\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @retval None\r\n  */\r\nvoid HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)\r\n{  \r\n  if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRA))\r\n  {\r\n    /* Get the status of the Interrupt */\r\n    if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRA) != (uint32_t)RESET)\r\n    {\r\n      /* AlarmA callback */ \r\n      HAL_RTC_AlarmAEventCallback(hrtc);\r\n      \r\n      /* Clear the Alarm interrupt pending bit */\r\n      __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF);\r\n    }\r\n  }\r\n  \r\n  if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRB))\r\n  {\r\n    /* Get the status of the Interrupt */\r\n    if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRB) != (uint32_t)RESET)\r\n    {\r\n      /* AlarmB callback */ \r\n      HAL_RTCEx_AlarmBEventCallback(hrtc);\r\n      \r\n      /* Clear the Alarm interrupt pending bit */\r\n      __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRBF);\r\n    }\r\n  }\r\n  \r\n  /* Clear the EXTI's line Flag for RTC Alarm */\r\n  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();\r\n  \r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY;\r\n}\r\n\r\n/**\r\n  * @brief  Alarm A callback.\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hrtc);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_RTC_AlarmAEventCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  This function handles AlarmA Polling request.\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  Timeout: Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0; \r\n\r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n  while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET)\r\n  {\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT;\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Clear the Alarm interrupt pending bit */\r\n  __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);\r\n  \r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY; \r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup RTC_Group4 Peripheral Control functions \r\n *  @brief   Peripheral Control functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                     ##### Peripheral Control functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides functions allowing to\r\n      (+) Wait for RTC Time and Date Synchronization\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are \r\n  *         synchronized with RTC APB clock.\r\n  * @note   The RTC Resynchronization mode is write protected, use the \r\n  *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. \r\n  * @note   To read the calendar through the shadow registers after Calendar \r\n  *         initialization, calendar update or after wakeup from low power modes \r\n  *         the software must first clear the RSF flag. \r\n  *         The software must then wait until it is set again before reading \r\n  *         the calendar, which means that the calendar registers have been \r\n  *         correctly copied into the RTC_TR and RTC_DR shadow registers.   \r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)\r\n{\r\n  uint32_t tickstart = 0;\r\n\r\n  /* Clear RSF flag */\r\n  hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;\r\n\r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n  /* Wait the registers to be synchronised */\r\n  while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET)\r\n  {\r\n    if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r\n    {       \r\n      return HAL_TIMEOUT;\r\n    } \r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup RTC_Group5 Peripheral State functions \r\n *  @brief   Peripheral State functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                     ##### Peripheral State functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides functions allowing to\r\n      (+) Get RTC state\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n/**\r\n  * @brief  Returns the RTC state.\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @retval HAL state\r\n  */\r\nHAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)\r\n{\r\n  return hrtc->State;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @brief  Enters the RTC Initialization mode.\r\n  * @note   The RTC Initialization mode is write protected, use the\r\n  *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)\r\n{\r\n  uint32_t tickstart = 0; \r\n  \r\n  /* Check if the Initialization mode is set */\r\n  if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)\r\n  {\r\n    /* Set the Initialization mode */\r\n    hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;\r\n\r\n    /* Get tick */\r\n    tickstart = HAL_GetTick();\r\n\r\n    /* Wait till RTC is in INIT state and if Time out is reached exit */\r\n    while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r\n      {       \r\n        return HAL_TIMEOUT;\r\n      } \r\n    }\r\n  }\r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n\r\n/**\r\n  * @brief  Converts a 2 digit decimal to BCD format.\r\n  * @param  Value: Byte to be converted\r\n  * @retval Converted byte\r\n  */\r\nuint8_t RTC_ByteToBcd2(uint8_t Value)\r\n{\r\n  uint32_t bcdhigh = 0;\r\n  \r\n  while(Value >= 10)\r\n  {\r\n    bcdhigh++;\r\n    Value -= 10;\r\n  }\r\n  \r\n  return  ((uint8_t)(bcdhigh << 4) | Value);\r\n}\r\n\r\n/**\r\n  * @brief  Converts from 2 digit BCD to Binary.\r\n  * @param  Value: BCD value to be converted\r\n  * @retval Converted word\r\n  */\r\nuint8_t RTC_Bcd2ToByte(uint8_t Value)\r\n{\r\n  uint32_t tmp = 0;\r\n  tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;\r\n  return (tmp + (Value & (uint8_t)0x0F));\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_RTC_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_rtc_ex.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   RTC HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the Real Time Clock (RTC) Extension peripheral:\r\n  *           + RTC Time Stamp functions\r\n  *           + RTC Tamper functions \r\n  *           + RTC Wake-up functions\r\n  *           + Extension Control functions\r\n  *           + Extension RTC features functions    \r\n  *         \r\n  @verbatim\r\n  ==============================================================================\r\n                  ##### How to use this driver #####\r\n  ==============================================================================\r\n  [..] \r\n    (+) Enable the RTC domain access.\r\n    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour \r\n        format using the HAL_RTC_Init() function.\r\n  \r\n  *** RTC Wakeup configuration ***\r\n  ================================\r\n  [..] \r\n    (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTC_SetWakeUpTimer()\r\n        function. You can also configure the RTC Wakeup timer in interrupt mode \r\n        using the HAL_RTC_SetWakeUpTimer_IT() function.\r\n    (+) To read the RTC WakeUp Counter register, use the HAL_RTC_GetWakeUpTimer() \r\n        function.\r\n  \r\n  *** TimeStamp configuration ***\r\n  ===============================\r\n  [..]\r\n    (+) Enables the RTC TimeStamp using the HAL_RTC_SetTimeStamp() function.\r\n        You can also configure the RTC TimeStamp with interrupt mode using the\r\n        HAL_RTC_SetTimeStamp_IT() function.\r\n    (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp()\r\n        function.\r\n\r\n  *** Internal TimeStamp configuration ***\r\n  ===============================\r\n  [..]\r\n    (+) Enables the RTC internal TimeStamp using the HAL_RTC_SetInternalTimeStamp() function.\r\n    (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp()\r\n        function.\r\n  \r\n  *** Tamper configuration ***\r\n  ============================\r\n  [..]\r\n    (+) Enable the RTC Tamper and Configure the Tamper filter count, trigger Edge \r\n        or Level according to the Tamper filter (if equal to 0 Edge else Level) \r\n        value, sampling frequency, NoErase, MaskFlag,  precharge or discharge and\r\n        Pull-UP using the HAL_RTC_SetTamper() function. You can configure RTC Tamper\r\n        with interrupt mode using HAL_RTC_SetTamper_IT() function.\r\n    (+) The default configuration of the Tamper erases the backup registers. To avoid\r\n        erase, enable the NoErase field on the RTC_TAMPCR register.\r\n  \r\n  *** Backup Data Registers configuration ***\r\n  ===========================================\r\n  [..]\r\n    (+) To write to the RTC Backup Data registers, use the HAL_RTC_BKUPWrite()\r\n        function.  \r\n    (+) To read the RTC Backup Data registers, use the HAL_RTC_BKUPRead()\r\n        function.\r\n     \r\n   @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup RTCEx RTCEx \r\n  * @brief RTC Extended HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_RTC_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions\r\n  * @{\r\n  */\r\n  \r\n\r\n/** @defgroup RTCEx_Group1 RTC TimeStamp and Tamper functions\r\n *  @brief   RTC TimeStamp and Tamper functions\r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                 ##### RTC TimeStamp and Tamper functions #####\r\n ===============================================================================  \r\n \r\n [..] This section provides functions allowing to configure TimeStamp feature\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Sets TimeStamp.\r\n  * @note   This API must be called before enabling the TimeStamp feature. \r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  TimeStampEdge: Specifies the pin edge on which the TimeStamp is \r\n  *         activated.\r\n  *          This parameter can be one of the following values:\r\n  *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the  \r\n  *                                        rising edge of the related pin.\r\n  *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the \r\n  *                                         falling edge of the related pin.\r\n  * @param  RTC_TimeStampPin: specifies the RTC TimeStamp Pin.\r\n  *          This parameter can be one of the following values:\r\n  *             @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.\r\n  *             @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin.  \r\n  *             @arg RTC_TIMESTAMPPIN_PC1: PC1 is selected as RTC TimeStamp Pin.   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)\r\n{\r\n  uint32_t tmpreg = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));\r\n  assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));\r\n  \r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n  /* Get the RTC_CR register and clear the bits to be configured */\r\n  tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));\r\n    \r\n  tmpreg|= TimeStampEdge;\r\n  \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  hrtc->Instance->OR &= (uint32_t)~RTC_OR_TSINSEL;\r\n  hrtc->Instance->OR |= (uint32_t)(RTC_TimeStampPin); \r\n  \r\n  /* Configure the Time Stamp TSEDGE and Enable bits */\r\n  hrtc->Instance->CR = (uint32_t)tmpreg;\r\n  \r\n  __HAL_RTC_TIMESTAMP_ENABLE(hrtc);\r\n  \r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);    \r\n  \r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY; \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Sets TimeStamp with Interrupt. \r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @note   This API must be called before enabling the TimeStamp feature.\r\n  * @param  TimeStampEdge: Specifies the pin edge on which the TimeStamp is \r\n  *         activated.\r\n  *          This parameter can be one of the following values:\r\n  *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the  \r\n  *                                        rising edge of the related pin.\r\n  *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the \r\n  *                                         falling edge of the related pin.\r\n  * @param  RTC_TimeStampPin: Specifies the RTC TimeStamp Pin.\r\n  *          This parameter can be one of the following values:\r\n  *             @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.\r\n  *             @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin.  \r\n  *             @arg RTC_TIMESTAMPPIN_PC1: PC1 is selected as RTC TimeStamp Pin.   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)\r\n{\r\n  uint32_t tmpreg = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));\r\n  assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));\r\n  \r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n  /* Get the RTC_CR register and clear the bits to be configured */\r\n  tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));\r\n  \r\n  tmpreg |= TimeStampEdge;\r\n  \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  /* Configure the Time Stamp TSEDGE and Enable bits */\r\n  hrtc->Instance->CR = (uint32_t)tmpreg;\r\n  \r\n  hrtc->Instance->OR &= (uint32_t)~RTC_OR_TSINSEL;\r\n  hrtc->Instance->OR |= (uint32_t)(RTC_TimeStampPin); \r\n  \r\n  __HAL_RTC_TIMESTAMP_ENABLE(hrtc);\r\n  \r\n  /* Enable IT timestamp */ \r\n  __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS);\r\n  \r\n  /* RTC timestamp Interrupt Configuration: EXTI configuration */\r\n  __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();\r\n  \r\n  EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;\r\n  \r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  \r\n  \r\n  hrtc->State = HAL_RTC_STATE_READY;  \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Deactivates TimeStamp. \r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)\r\n{\r\n  uint32_t tmpreg = 0;\r\n  \r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  /* In case of interrupt mode is used, the interrupt source must disabled */ \r\n  __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS);\r\n  \r\n  /* Get the RTC_CR register and clear the bits to be configured */\r\n  tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));\r\n  \r\n  /* Configure the Time Stamp TSEDGE and Enable bits */\r\n  hrtc->Instance->CR = (uint32_t)tmpreg;\r\n  \r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n \r\n  hrtc->State = HAL_RTC_STATE_READY;  \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Sets Internal TimeStamp.\r\n  * @note   This API must be called before enabling the internal TimeStamp feature.\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hrtc);\r\n\r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n\r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n\r\n  /* Configure the internal Time Stamp Enable bits */\r\n  __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(hrtc);\r\n\r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n\r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY;\r\n\r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Deactivates internal TimeStamp.\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hrtc);\r\n\r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n\r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n\r\n  /* Configure the internal Time Stamp Enable bits */\r\n  __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(hrtc);\r\n\r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n\r\n  hrtc->State = HAL_RTC_STATE_READY;\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hrtc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Gets the RTC TimeStamp value.\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  sTimeStamp: Pointer to Time structure\r\n  * @param  sTimeStampDate: Pointer to Date structure  \r\n  * @param  Format: specifies the format of the entered parameters.\r\n  *          This parameter can be one of the following values:\r\n  *             FORMAT_BIN: Binary data format \r\n  *             FORMAT_BCD: BCD data format\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)\r\n{\r\n  uint32_t tmptime = 0, tmpdate = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_FORMAT(Format));\r\n\r\n  /* Get the TimeStamp time and date registers values */\r\n  tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK);\r\n  tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK);\r\n\r\n  /* Fill the Time structure fields with the read parameters */\r\n  sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);\r\n  sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);\r\n  sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));\r\n  sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16);  \r\n  sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR;\r\n  \r\n  /* Fill the Date structure fields with the read parameters */\r\n  sTimeStampDate->Year = 0;\r\n  sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);\r\n  sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));\r\n  sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);\r\n\r\n  /* Check the input parameters format */\r\n  if(Format == RTC_FORMAT_BIN)\r\n  {\r\n    /* Convert the TimeStamp structure parameters to Binary format */\r\n    sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);\r\n    sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes);\r\n    sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds);\r\n    \r\n    /* Convert the DateTimeStamp structure parameters to Binary format */\r\n    sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);\r\n    sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);\r\n    sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay);\r\n  }\r\n  \r\n  /* Clear the TIMESTAMP Flag */\r\n  __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);\r\n    \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Sets Tamper\r\n  * @note   By calling this API we disable the tamper interrupt for all tampers. \r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  sTamper: Pointer to Tamper Structure.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)\r\n{\r\n  uint32_t tmpreg = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_TAMPER(sTamper->Tamper)); \r\n  assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));\r\n  assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));\r\n  assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));\r\n  assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));\r\n  assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));         \r\n  assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));\r\n  assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));\r\n  assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));\r\n \r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n    \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n\r\n  if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)\r\n  { \r\n    sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); \r\n  } \r\n  \r\n  if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)\r\n  { \r\n    sTamper->NoErase = 0;\r\n    if((sTamper->Tamper & RTC_TAMPER_1) != 0)\r\n    {\r\n      sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE;\r\n    }\r\n    if((sTamper->Tamper & RTC_TAMPER_2) != 0)\r\n    {\r\n      sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE;\r\n    }\r\n    if((sTamper->Tamper & RTC_TAMPER_3) != 0)\r\n    {\r\n      sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE;\r\n    }\r\n  }\r\n\r\n  if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)\r\n  {\r\n    sTamper->MaskFlag = 0;\r\n    if((sTamper->Tamper & RTC_TAMPER_1) != 0)\r\n    {\r\n      sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF;\r\n    }\r\n    if((sTamper->Tamper & RTC_TAMPER_2) != 0)\r\n    {\r\n      sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF;\r\n    }\r\n    if((sTamper->Tamper & RTC_TAMPER_3) != 0)\r\n    {\r\n      sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF;\r\n    }\r\n  }\r\n  \r\n  tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger  | (uint32_t)sTamper->NoErase |\\\r\n            (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\\\r\n            (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);\r\n\r\n  hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAMPCR_TAMPTS |\\\r\n                                       (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\\\r\n                                       (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE | (uint32_t)RTC_TAMPCR_TAMP1IE |\\\r\n                                       (uint32_t)RTC_TAMPCR_TAMP2IE | (uint32_t)RTC_TAMPCR_TAMP3IE | (uint32_t)RTC_TAMPCR_TAMP1NOERASE |\\\r\n                                       (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF |\\\r\n                                       (uint32_t)RTC_TAMPCR_TAMP2MF | (uint32_t)RTC_TAMPCR_TAMP3MF);\r\n\r\n  hrtc->Instance->TAMPCR |= tmpreg;      \r\n      \r\n  hrtc->State = HAL_RTC_STATE_READY; \r\n\r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n    \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Sets Tamper with interrupt.\r\n  * @note   By calling this API we force the tamper interrupt for all tampers.\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  sTamper: Pointer to RTC Tamper.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)\r\n{\r\n  uint32_t tmpreg = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_TAMPER(sTamper->Tamper)); \r\n  assert_param(IS_RTC_TAMPER_INTERRUPT(sTamper->Interrupt));\r\n  assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));\r\n  assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));\r\n  assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));\r\n  assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));\r\n  assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));         \r\n  assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));\r\n  assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));\r\n  assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));\r\n \r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n      \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n  /* Configure the tamper trigger */\r\n  if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)\r\n  { \r\n    sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); \r\n  } \r\n  \r\n  if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)\r\n  { \r\n    sTamper->NoErase = 0;\r\n    if((sTamper->Tamper & RTC_TAMPER_1) != 0)\r\n    {\r\n      sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE;\r\n    }\r\n    if((sTamper->Tamper & RTC_TAMPER_2) != 0)\r\n    {\r\n      sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE;\r\n    }\r\n    if((sTamper->Tamper & RTC_TAMPER_3) != 0)\r\n    {\r\n      sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE;\r\n    }\r\n  }\r\n\r\n  if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)\r\n  {\r\n    sTamper->MaskFlag = 0;\r\n    if((sTamper->Tamper & RTC_TAMPER_1) != 0)\r\n    {\r\n      sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF;\r\n    }\r\n    if((sTamper->Tamper & RTC_TAMPER_2) != 0)\r\n    {\r\n      sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF;\r\n    }\r\n    if((sTamper->Tamper & RTC_TAMPER_3) != 0)\r\n    {\r\n      sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF;\r\n    }\r\n  }\r\n  \r\n  tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Interrupt | (uint32_t)sTamper->Trigger  | (uint32_t)sTamper->NoErase |\\\r\n            (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\\\r\n            (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);\r\n  \r\n  hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAMPCR_TAMPTS |\\\r\n                                       (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\\\r\n                                       (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE | (uint32_t)RTC_TAMPCR_TAMP1IE |\\\r\n                                       (uint32_t)RTC_TAMPCR_TAMP2IE | (uint32_t)RTC_TAMPCR_TAMP3IE | (uint32_t)RTC_TAMPCR_TAMP1NOERASE |\\\r\n                                       (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF |\\\r\n                                       (uint32_t)RTC_TAMPCR_TAMP2MF | (uint32_t)RTC_TAMPCR_TAMP3MF);\r\n\r\n  hrtc->Instance->TAMPCR |= tmpreg;\r\n\r\n  /* RTC Tamper Interrupt Configuration: EXTI configuration */\r\n  __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();\r\n\r\n  EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;\r\n  \r\n  hrtc->State = HAL_RTC_STATE_READY;   \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Deactivates Tamper.\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  Tamper: Selected tamper pin.\r\n  *          This parameter can be RTC_Tamper_1 and/or RTC_TAMPER_2.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)\r\n{\r\n  assert_param(IS_RTC_TAMPER(Tamper)); \r\n  \r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n      \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n/* Disable the selected Tamper pin */\r\n  hrtc->Instance->TAMPCR &= (uint32_t)~Tamper;\r\n\r\n  if ((Tamper & RTC_TAMPER_1) != 0)\r\n  {\r\n    /* Disable the Tamper1 interrupt */\r\n    hrtc->Instance->TAMPCR &= (uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP1);\r\n  }\r\n  if ((Tamper & RTC_TAMPER_2) != 0)\r\n  {\r\n    /* Disable the Tamper2 interrupt */\r\n    hrtc->Instance->TAMPCR &= (uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP2);\r\n  }\r\n  if ((Tamper & RTC_TAMPER_3) != 0)\r\n  {\r\n    /* Disable the Tamper2 interrupt */\r\n    hrtc->Instance->TAMPCR &= (uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP3);\r\n  } \r\n  \r\n  hrtc->State = HAL_RTC_STATE_READY;   \r\n  \r\n  /* Process Unlocked */  \r\n  __HAL_UNLOCK(hrtc);\r\n  \r\n  return HAL_OK; \r\n}\r\n\r\n/**\r\n  * @brief  This function handles TimeStamp interrupt request.\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @retval None\r\n  */\r\nvoid HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)\r\n{  \r\n  if(__HAL_RTC_TIMESTAMP_GET_IT(hrtc, RTC_IT_TS))\r\n  {\r\n    /* Get the status of the Interrupt */\r\n    if((uint32_t)(hrtc->Instance->CR & RTC_IT_TS) != (uint32_t)RESET)\r\n    {\r\n       /* TIMESTAMP callback */ \r\n        HAL_RTCEx_TimeStampEventCallback(hrtc);\r\n\r\n      /* Clear the TIMESTAMP interrupt pending bit */\r\n      __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc,RTC_FLAG_TSF);\r\n    }\r\n  }\r\n\r\n  /* Get the status of the Interrupt */\r\n  if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== SET)\r\n  {\r\n    /* Get the TAMPER Interrupt enable bit and pending bit */\r\n    if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \\\r\n       (((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP1IE)) != (uint32_t)RESET))\r\n    {\r\n      /* Tamper callback */\r\n      HAL_RTCEx_Tamper1EventCallback(hrtc);\r\n\r\n      /* Clear the Tamper interrupt pending bit */\r\n      __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);\r\n    }\r\n  }\r\n\r\n  /* Get the status of the Interrupt */\r\n  if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F)== SET)\r\n  {\r\n    /* Get the TAMPER Interrupt enable bit and pending bit */\r\n    if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \\\r\n       (((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP2IE)) != (uint32_t)RESET))\r\n    {\r\n      /* Tamper callback */\r\n      HAL_RTCEx_Tamper2EventCallback(hrtc);\r\n\r\n      /* Clear the Tamper interrupt pending bit */\r\n      __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);\r\n    }\r\n  }\r\n\r\n  /* Get the status of the Interrupt */\r\n  if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F)== SET)\r\n  {\r\n    /* Get the TAMPER Interrupt enable bit and pending bit */\r\n    if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \\\r\n       (((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP3IE)) != (uint32_t)RESET))\r\n    {\r\n      /* Tamper callback */\r\n      HAL_RTCEx_Tamper3EventCallback(hrtc);\r\n\r\n      /* Clear the Tamper interrupt pending bit */\r\n      __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);\r\n    }\r\n  }\r\n  \r\n  /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */\r\n  __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();\r\n\r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY;\r\n}\r\n\r\n/**\r\n  * @brief  TimeStamp callback. \r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hrtc);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_RTC_TimeStampEventCallback could be implemented in the user file\r\n  */\r\n}\r\n\r\n/**\r\n  * @brief  Tamper 1 callback. \r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hrtc);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_RTC_Tamper1EventCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Tamper 2 callback. \r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hrtc);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_RTC_Tamper2EventCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Tamper 3 callback. \r\n  * @param  hrtc: RTC handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hrtc);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  This function handles TimeStamp polling request.\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  Timeout: Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)\r\n{ \r\n  uint32_t tickstart = 0; \r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET)\r\n  {\t        \r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT;\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n\t\r\n  if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET)\r\n  {\r\n    /* Clear the TIMESTAMP OverRun Flag */\r\n    __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);\r\n      \r\n    /* Change TIMESTAMP state */\r\n    hrtc->State = HAL_RTC_STATE_ERROR; \r\n      \r\n    return HAL_ERROR; \r\n   }\r\n\t\r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY; \r\n  \r\n  return HAL_OK; \r\n}\r\n  \r\n/**\r\n  * @brief  This function handles Tamper1 Polling.\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  Timeout: Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)\r\n{  \r\n  uint32_t tickstart = 0; \r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  /* Get the status of the Interrupt */\r\n  while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== RESET)\r\n  {\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT;\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Clear the Tamper Flag */\r\n  __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);\r\n  \r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY;\r\n  \r\n  return HAL_OK; \r\n}\r\n\r\n/**\r\n  * @brief  This function handles Tamper2 Polling.\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  Timeout: Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)\r\n{  \r\n  uint32_t tickstart = 0; \r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n  \r\n  /* Get the status of the Interrupt */\r\n  while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == RESET)\r\n  {\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT;\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Clear the Tamper Flag */\r\n  __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP2F);\r\n  \r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY;\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  This function handles Tamper3 Polling.\r\n  * @param  hrtc: RTC handle\r\n  * @param  Timeout: Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = HAL_GetTick();\r\n\r\n  /* Get the status of the Interrupt */\r\n  while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) == RESET)\r\n  {\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT;\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n\r\n  /* Clear the Tamper Flag */\r\n  __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP3F);\r\n\r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY;\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup RTCEx_Group2 RTC Wake-up functions\r\n *  @brief   RTC Wake-up functions\r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                        ##### RTC Wake-up functions #####\r\n ===============================================================================  \r\n \r\n [..] This section provides functions allowing to configure Wake-up feature\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Sets wake up timer. \r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  WakeUpCounter: Wake up counter\r\n  * @param  WakeUpClock: Wake up clock  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)\r\n{\r\n  uint32_t tickstart = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));\r\n  assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));\r\n \r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n    \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);\r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  /*Check RTC WUTWF flag is reset only when wake up timer enabled*/\r\n  if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)\r\n  {\r\n    /* Wait till RTC WUTWF flag is set and if Time out is reached exit */\r\n    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r\n      {\r\n        /* Enable the write protection for RTC registers */\r\n        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n      \r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT; \r\n      \r\n        /* Process Unlocked */ \r\n        __HAL_UNLOCK(hrtc);\r\n      \r\n        return HAL_TIMEOUT;\r\n      }  \r\n    }\r\n  }\r\n  \r\n  /* Clear the Wakeup Timer clock source bits in CR register */\r\n  hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;\r\n  \r\n  /* Configure the clock source */\r\n  hrtc->Instance->CR |= (uint32_t)WakeUpClock;\r\n  \r\n  /* Configure the Wakeup Timer counter */\r\n  hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;\r\n  \r\n   /* Enable the Wakeup Timer */\r\n  __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);   \r\n  \r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r\n  \r\n  hrtc->State = HAL_RTC_STATE_READY;   \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Sets wake up timer with interrupt\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  WakeUpCounter: Wake up counter\r\n  * @param  WakeUpClock: Wake up clock  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));\r\n  assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));\r\n  \r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);\r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n    /*Check RTC WUTWF flag is reset only when wake up timer enabled*/\r\n  if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)\r\n  {\r\n    /* Wait till RTC WUTWF flag is set and if Time out is reached exit */\r\n    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r\n      {\r\n        /* Enable the write protection for RTC registers */\r\n        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n       \r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT; \r\n      \r\n        /* Process Unlocked */ \r\n        __HAL_UNLOCK(hrtc);\r\n      \r\n        return HAL_TIMEOUT;\r\n      }  \r\n    }\r\n  }\r\n  \r\n  /* Configure the Wakeup Timer counter */\r\n  hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;\r\n\r\n  /* Clear the Wakeup Timer clock source bits in CR register */\r\n  hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;\r\n\r\n  /* Configure the clock source */\r\n  hrtc->Instance->CR |= (uint32_t)WakeUpClock;\r\n  \r\n  /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */\r\n  __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();\r\n  \r\n  EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT;\r\n  \r\n  /* Configure the Interrupt in the RTC_CR register */\r\n  __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);\r\n  \r\n  /* Enable the Wakeup Timer */\r\n  __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);\r\n    \r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r\n  \r\n  hrtc->State = HAL_RTC_STATE_READY;   \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Deactivates wake up timer counter.\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC. \r\n  * @retval HAL status\r\n  */\r\nuint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  /* Disable the Wakeup Timer */\r\n  __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);\r\n  \r\n  /* In case of interrupt mode is used, the interrupt source must disabled */ \r\n  __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT);\r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Wait till RTC WUTWF flag is set and if Time out is reached exit */\r\n  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)\r\n  {\r\n    if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r\n    {\r\n      /* Enable the write protection for RTC registers */\r\n      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n      \r\n      hrtc->State = HAL_RTC_STATE_TIMEOUT; \r\n      \r\n      /* Process Unlocked */ \r\n      __HAL_UNLOCK(hrtc);\r\n      \r\n      return HAL_TIMEOUT;\r\n    }   \r\n  }\r\n  \r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_READY;   \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Gets wake up timer counter.\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC. \r\n  * @retval Counter value\r\n  */\r\nuint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)\r\n{\r\n  /* Get the counter value */\r\n  return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT)); \r\n}\r\n\r\n/**\r\n  * @brief  This function handles Wake Up Timer interrupt request.\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @retval None\r\n  */\r\nvoid HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)\r\n{  \r\n  if(__HAL_RTC_WAKEUPTIMER_GET_IT(hrtc, RTC_IT_WUT))\r\n  {\r\n    /* Get the status of the Interrupt */\r\n    if((uint32_t)(hrtc->Instance->CR & RTC_IT_WUT) != (uint32_t)RESET)\r\n    {\r\n      /* WAKEUPTIMER callback */ \r\n      HAL_RTCEx_WakeUpTimerEventCallback(hrtc);\r\n      \r\n      /* Clear the WAKEUPTIMER interrupt pending bit */\r\n      __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);\r\n    }\r\n  }\r\n  \r\n  /* Clear the EXTI's line Flag for RTC WakeUpTimer */\r\n  __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();\r\n  \r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY;\r\n}\r\n\r\n/**\r\n  * @brief  Wake Up Timer callback.\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hrtc);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_RTC_WakeUpTimerEventCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  This function handles Wake Up Timer Polling.\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  Timeout: Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)\r\n{  \r\n  uint32_t tickstart = 0; \r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET)\r\n  {\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT;\r\n      \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Clear the WAKEUPTIMER Flag */\r\n  __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);\r\n  \r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY;\r\n  \r\n  return HAL_OK; \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup RTCEx_Group3 Extension Peripheral Control functions \r\n *  @brief   Extension Peripheral Control functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n              ##### Extension Peripheral Control functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides functions allowing to\r\n      (+) Write a data in a specified RTC Backup data register\r\n      (+) Read a data in a specified RTC Backup data register\r\n      (+) Set the Coarse calibration parameters.\r\n      (+) Deactivate the Coarse calibration parameters\r\n      (+) Set the Smooth calibration parameters.\r\n      (+) Configure the Synchronization Shift Control Settings.\r\n      (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).\r\n      (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).\r\n      (+) Enable the RTC reference clock detection.\r\n      (+) Disable the RTC reference clock detection.\r\n      (+) Enable the Bypass Shadow feature.\r\n      (+) Disable the Bypass Shadow feature.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Writes a data in a specified RTC Backup data register.\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC. \r\n  * @param  BackupRegister: RTC Backup data Register number.\r\n  *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to \r\n  *                                 specify the register.\r\n  * @param  Data: Data to be written in the specified RTC Backup data register.                     \r\n  * @retval None\r\n  */\r\nvoid HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)\r\n{\r\n  uint32_t tmp = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_BKP(BackupRegister));\r\n  \r\n  tmp = (uint32_t)&(hrtc->Instance->BKP0R);\r\n  tmp += (BackupRegister * 4);\r\n  \r\n  /* Write the specified register */\r\n  *(__IO uint32_t *)tmp = (uint32_t)Data;\r\n}\r\n\r\n/**\r\n  * @brief  Reads data from the specified RTC Backup data Register.\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC. \r\n  * @param  BackupRegister: RTC Backup data Register number.\r\n  *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to \r\n  *                                 specify the register.                   \r\n  * @retval Read value\r\n  */\r\nuint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)\r\n{\r\n  uint32_t tmp = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_BKP(BackupRegister));\r\n\r\n  tmp = (uint32_t)&(hrtc->Instance->BKP0R);\r\n  tmp += (BackupRegister * 4);\r\n  \r\n  /* Read the specified register */\r\n  return (*(__IO uint32_t *)tmp);\r\n}\r\n\r\n/**\r\n  * @brief  Sets the Smooth calibration parameters.\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.  \r\n  * @param  SmoothCalibPeriod: Select the Smooth Calibration Period.\r\n  *          This parameter can be can be one of the following values :\r\n  *             @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.\r\n  *             @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.\r\n  *             @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.\r\n  * @param  SmoothCalibPlusPulses: Select to Set or reset the CALP bit.\r\n  *          This parameter can be one of the following values:\r\n  *             @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulses every 2*11 pulses.\r\n  *             @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.\r\n  * @param  SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.\r\n  *          This parameter can be one any value from 0 to 0x000001FF.\r\n  * @note   To deactivate the smooth calibration, the field SmoothCalibPlusPulses \r\n  *         must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field \r\n  *         SmouthCalibMinusPulsesValue must be equal to 0.  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue)\r\n{\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod));\r\n  assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses));\r\n  assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmouthCalibMinusPulsesValue));\r\n  \r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  /* check if a calibration is pending*/\r\n  if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)\r\n  {\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n    /* check if a calibration is pending*/\r\n    while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r\n      {\r\n        /* Enable the write protection for RTC registers */\r\n        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n        \r\n        /* Change RTC state */\r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT; \r\n        \r\n        /* Process Unlocked */ \r\n        __HAL_UNLOCK(hrtc);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Configure the Smooth calibration settings */\r\n  hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmouthCalibMinusPulsesValue);\r\n  \r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n  \r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY; \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Configures the Synchronization Shift Control Settings.\r\n  * @note   When REFCKON is set, firmware must not write to Shift control register. \r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.    \r\n  * @param  ShiftAdd1S: Select to add or not 1 second to the time calendar.\r\n  *          This parameter can be one of the following values :\r\n  *             @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. \r\n  *             @arg RTC_SHIFTADD1S_RESET: No effect.\r\n  * @param  ShiftSubFS: Select the number of Second Fractions to substitute.\r\n  *          This parameter can be one any value from 0 to 0x7FFF.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)\r\n{\r\n  uint32_t tickstart = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S));\r\n  assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS));\r\n\r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n\r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n    /* Wait until the shift is completed*/\r\n    while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET)\r\n    {\r\n      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)\r\n      {  \r\n        /* Enable the write protection for RTC registers */\r\n        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  \r\n        \r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT;\r\n        \r\n        /* Process Unlocked */ \r\n        __HAL_UNLOCK(hrtc);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  \r\n    /* Check if the reference clock detection is disabled */\r\n    if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET)\r\n    {\r\n      /* Configure the Shift settings */\r\n      hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S);\r\n      \r\n      /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */\r\n      if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)\r\n      {\r\n        if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)\r\n        {\r\n          /* Enable the write protection for RTC registers */\r\n          __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  \r\n          \r\n          hrtc->State = HAL_RTC_STATE_ERROR;\r\n          \r\n          /* Process Unlocked */ \r\n          __HAL_UNLOCK(hrtc);\r\n          \r\n          return HAL_ERROR;\r\n        }\r\n      }\r\n    }\r\n    else\r\n    {\r\n      /* Enable the write protection for RTC registers */\r\n      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n      \r\n      /* Change RTC state */\r\n      hrtc->State = HAL_RTC_STATE_ERROR; \r\n      \r\n      /* Process Unlocked */ \r\n      __HAL_UNLOCK(hrtc);\r\n      \r\n      return HAL_ERROR;\r\n    }\r\n  \r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n  \r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY; \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.    \r\n  * @param  CalibOutput: Select the Calibration output Selection .\r\n  *          This parameter can be one of the following values:\r\n  *             @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz. \r\n  *             @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput));\r\n  \r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n\r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  /* Clear flags before config */\r\n  hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL;\r\n  \r\n  /* Configure the RTC_CR register */\r\n  hrtc->Instance->CR |= (uint32_t)CalibOutput;\r\n  \r\n  __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc);\r\n  \r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n  \r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY; \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.    \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc)\r\n{\r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc);\r\n    \r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n  \r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY; \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Enables the RTC reference clock detection.\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.    \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)\r\n{\r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  /* Set Initialization mode */\r\n  if(RTC_EnterInitMode(hrtc) != HAL_OK)\r\n  {\r\n    /* Enable the write protection for RTC registers */\r\n    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r\n    \r\n    /* Set RTC state*/\r\n    hrtc->State = HAL_RTC_STATE_ERROR;\r\n    \r\n    /* Process Unlocked */ \r\n    __HAL_UNLOCK(hrtc);\r\n    \r\n    return HAL_ERROR;\r\n  } \r\n  else\r\n  {\r\n    __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc);\r\n\r\n    /* Exit Initialization mode */\r\n    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; \r\n  }\r\n  \r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n  \r\n   /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY; \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Disable the RTC reference clock detection.\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.    \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)\r\n{ \r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  /* Set Initialization mode */\r\n  if(RTC_EnterInitMode(hrtc) != HAL_OK)\r\n  {\r\n    /* Enable the write protection for RTC registers */\r\n    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); \r\n    \r\n    /* Set RTC state*/\r\n    hrtc->State = HAL_RTC_STATE_ERROR;\r\n    \r\n    /* Process Unlocked */ \r\n    __HAL_UNLOCK(hrtc);\r\n    \r\n    return HAL_ERROR;\r\n  } \r\n  else\r\n  {\r\n    __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc);\r\n    \r\n    /* Exit Initialization mode */\r\n    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; \r\n  }\r\n  \r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n  \r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY; \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Enables the Bypass Shadow feature.\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.  \r\n  * @note   When the Bypass Shadow is enabled the calendar value are taken \r\n  *         directly from the Calendar counter.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc)\r\n{\r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  /* Set the BYPSHAD bit */\r\n  hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD;\r\n  \r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n  \r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY; \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Disables the Bypass Shadow feature.\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.  \r\n  * @note   When the Bypass Shadow is enabled the calendar value are taken \r\n  *         directly from the Calendar counter.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc)\r\n{\r\n  /* Process Locked */ \r\n  __HAL_LOCK(hrtc);\r\n  \r\n  hrtc->State = HAL_RTC_STATE_BUSY;\r\n  \r\n  /* Disable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);\r\n  \r\n  /* Reset the BYPSHAD bit */\r\n  hrtc->Instance->CR &= (uint8_t)~RTC_CR_BYPSHAD;\r\n  \r\n  /* Enable the write protection for RTC registers */\r\n  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);\r\n  \r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY; \r\n  \r\n  /* Process Unlocked */ \r\n  __HAL_UNLOCK(hrtc);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n  /** @defgroup RTCEx_Group4 Extended features functions \r\n *  @brief    Extended features functions  \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                 ##### Extended features functions #####\r\n ===============================================================================  \r\n    [..]  This section provides functions allowing to:\r\n      (+) RTC Alram B callback\r\n      (+) RTC Poll for Alarm B request\r\n               \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Alarm B callback.\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @retval None\r\n  */\r\n__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hrtc);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_RTC_AlarmBEventCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  This function handles AlarmB Polling request.\r\n  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains\r\n  *                the configuration information for RTC.\r\n  * @param  Timeout: Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)\r\n{  \r\n  uint32_t tickstart = 0; \r\n\r\n  /* Get tick */\r\n  tickstart = HAL_GetTick();\r\n\r\n  while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET)\r\n  {\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        hrtc->State = HAL_RTC_STATE_TIMEOUT;\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* Clear the Alarm Flag */\r\n  __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);\r\n  \r\n  /* Change RTC state */\r\n  hrtc->State = HAL_RTC_STATE_READY; \r\n  \r\n  return HAL_OK; \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_RTC_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sai.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_sai.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   SAI HAL module driver.\r\n  *          This file provides firmware functions to manage the following\r\n  *          functionalities of the Serial Audio Interface (SAI) peripheral:\r\n  *           + Initialization/de-initialization functions\r\n  *           + I/O operation functions\r\n  *           + Peripheral Control functions\r\n  *           + Peripheral State functions\r\n  *\r\n  @verbatim\r\n ==============================================================================\r\n                  ##### How to use this driver #####\r\n  ==============================================================================\r\n\r\n  [..]\r\n    The SAI HAL driver can be used as follows:\r\n\r\n    (#) Declare a SAI_HandleTypeDef handle structure (eg. SAI_HandleTypeDef hsai).\r\n    (#) Initialize the SAI low level resources by implementing the HAL_SAI_MspInit() API:\r\n        (##) Enable the SAI interface clock.\r\n        (##) SAI pins configuration:\r\n            (+++) Enable the clock for the SAI GPIOs.\r\n            (+++) Configure these SAI pins as alternate function pull-up.\r\n        (##) NVIC configuration if you need to use interrupt process (HAL_SAI_Transmit_IT()\r\n             and HAL_SAI_Receive_IT() APIs):\r\n            (+++) Configure the SAI interrupt priority.\r\n            (+++) Enable the NVIC SAI IRQ handle.\r\n\r\n        (##) DMA Configuration if you need to use DMA process (HAL_SAI_Transmit_DMA()\r\n             and HAL_SAI_Receive_DMA() APIs):\r\n            (+++) Declare a DMA handle structure for the Tx/Rx stream.\r\n            (+++) Enable the DMAx interface clock.\r\n            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.\r\n            (+++) Configure the DMA Tx/Rx Stream.\r\n            (+++) Associate the initialized DMA handle to the SAI DMA Tx/Rx handle.\r\n            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the\r\n                DMA Tx/Rx Stream.\r\n\r\n    (#) The initialization can be done by two ways\r\n        (##) Expert mode : Initialize the structures Init, FrameInit and SlotInit and call HAL_SAI_Init().\r\n        (##) Simplified mode : Initialize the high part of Init Structure and call HAL_SAI_InitProtocol().\r\n\r\n  [..]\r\n    (@) The specific SAI interrupts (FIFO request and Overrun underrun interrupt)\r\n        will be managed using the macros __HAL_SAI_ENABLE_IT() and __HAL_SAI_DISABLE_IT()\r\n        inside the transmit and receive process.\r\n  [..]\r\n   (@) Make sure that either:\r\n       (+@) I2S PLL is configured or\r\n       (+@) SAI PLL is configured or\r\n       (+@) External clock source is configured after setting correctly\r\n            the define constant EXTERNAL_CLOCK_VALUE in the stm32f7xx_hal_conf.h file.\r\n  [..]\r\n    (@) In master Tx mode: enabling the audio block immediately generates the bit clock\r\n        for the external slaves even if there is no data in the FIFO, However FS signal\r\n        generation is conditioned by the presence of data in the FIFO.\r\n\r\n  [..]\r\n    (@) In master Rx mode: enabling the audio block immediately generates the bit clock\r\n        and FS signal for the external slaves.\r\n\r\n  [..]\r\n    (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior:\r\n        (+@) First bit Offset <= (SLOT size - Data size)\r\n        (+@) Data size <= SLOT size\r\n        (+@) Number of SLOT x SLOT size = Frame length\r\n        (+@) The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected.\r\n\r\n  [..]\r\n    Three operation modes are available within this driver :\r\n\r\n    *** Polling mode IO operation ***\r\n    =================================\r\n    [..]\r\n      (+) Send an amount of data in blocking mode using HAL_SAI_Transmit()\r\n      (+) Receive an amount of data in blocking mode using HAL_SAI_Receive()\r\n\r\n    *** Interrupt mode IO operation ***\r\n    ===================================\r\n    [..]\r\n      (+) Send an amount of data in non-blocking mode using HAL_SAI_Transmit_IT()\r\n      (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can\r\n          add his own code by customization of function pointer HAL_SAI_TxCpltCallback()\r\n      (+) Receive an amount of data in non-blocking mode using HAL_SAI_Receive_IT()\r\n      (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can\r\n          add his own code by customization of function pointer HAL_SAI_RxCpltCallback()\r\n      (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can \r\n          add his own code by customization of function pointer HAL_SAI_ErrorCallback()\r\n\r\n    *** DMA mode IO operation ***\r\n    =============================\r\n    [..]\r\n      (+) Send an amount of data in non-blocking mode (DMA) using HAL_SAI_Transmit_DMA()\r\n      (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can\r\n          add his own code by customization of function pointer HAL_SAI_TxCpltCallback()\r\n      (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SAI_Receive_DMA()\r\n      (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can\r\n          add his own code by customization of function pointer HAL_SAI_RxCpltCallback()\r\n      (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can\r\n          add his own code by customization of function pointer HAL_SAI_ErrorCallback()\r\n      (+) Pause the DMA Transfer using HAL_SAI_DMAPause()\r\n      (+) Resume the DMA Transfer using HAL_SAI_DMAResume()\r\n      (+) Stop the DMA Transfer using HAL_SAI_DMAStop()\r\n\r\n    *** SAI HAL driver additional function list ***\r\n    ===============================================\r\n    [..]\r\n      Below the list the others API available SAI HAL driver :\r\n\r\n      (+) HAL_SAI_EnableTxMuteMode(): Enable the mute in tx mode\r\n      (+) HAL_SAI_DisableTxMuteMode(): Disable the mute in tx mode\r\n      (+) HAL_SAI_EnableRxMuteMode(): Enable the mute in Rx mode\r\n      (+) HAL_SAI_DisableRxMuteMode(): Disable the mute in Rx mode\r\n      (+) HAL_SAI_FlushRxFifo(): Flush the rx fifo.\r\n      (+) HAL_SAI_Abort(): Abort the current transfer\r\n\r\n    *** SAI HAL driver macros list ***\r\n    ==================================\r\n    [..]\r\n      Below the list of most used macros in SAI HAL driver :\r\n\r\n      (+) __HAL_SAI_ENABLE(): Enable the SAI peripheral\r\n      (+) __HAL_SAI_DISABLE(): Disable the SAI peripheral\r\n      (+) __HAL_SAI_ENABLE_IT(): Enable the specified SAI interrupts\r\n      (+) __HAL_SAI_DISABLE_IT(): Disable the specified SAI interrupts\r\n      (+) __HAL_SAI_GET_IT_SOURCE(): Check if the specified SAI interrupt source is\r\n          enabled or disabled\r\n      (+) __HAL_SAI_GET_FLAG(): Check whether the specified SAI flag is set or not\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup SAI SAI\r\n  * @brief SAI HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_SAI_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n\r\n/** @defgroup SAI_Private_Typedefs  SAI Private Typedefs\r\n  * @{\r\n  */\r\ntypedef enum {\r\n  SAI_MODE_DMA,\r\n  SAI_MODE_IT\r\n}SAI_ModeTypedef;\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private define ------------------------------------------------------------*/\r\n\r\n/** @defgroup SAI_Private_Constants  SAI Private Constants\r\n  * @{\r\n  */\r\n#define SAI_FIFO_SIZE         8\r\n#define SAI_DEFAULT_TIMEOUT   4 /* 4ms */\r\n#define SAI_xCR2_MUTECNT_OFFSET POSITION_VAL(SAI_xCR2_MUTECNT)\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n\r\n/** @defgroup SAI_Private_Functions  SAI Private Functions\r\n  * @{\r\n  */\r\nstatic void SAI_FillFifo(SAI_HandleTypeDef *hsai);\r\nstatic uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode);\r\nstatic HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);\r\nstatic HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);\r\n\r\nstatic HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai);\r\nstatic void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai);\r\nstatic void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai);\r\nstatic void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai);\r\nstatic void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai);\r\nstatic void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai);\r\nstatic void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai);\r\n\r\nstatic void SAI_DMATxCplt(DMA_HandleTypeDef *hdma);\r\nstatic void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);\r\nstatic void SAI_DMARxCplt(DMA_HandleTypeDef *hdma);\r\nstatic void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);\r\nstatic void SAI_DMAError(DMA_HandleTypeDef *hdma);\r\nstatic void SAI_DMAAbort(DMA_HandleTypeDef *hdma);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup SAI_Exported_Functions SAI Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup SAI_Exported_Functions_Group1 Initialization and de-initialization functions\r\n *  @brief    Initialization and Configuration functions\r\n *\r\n@verbatim\r\n ===============================================================================\r\n            ##### Initialization and de-initialization functions #####\r\n ===============================================================================\r\n  [..]  This subsection provides a set of functions allowing to initialize and\r\n        de-initialize the SAIx peripheral:\r\n\r\n      (+) User must implement HAL_SAI_MspInit() function in which he configures\r\n          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).\r\n\r\n      (+) Call the function HAL_SAI_Init() to configure the selected device with\r\n          the selected configuration:\r\n        (++) Mode (Master/slave TX/RX)\r\n        (++) Protocol\r\n        (++) Data Size\r\n        (++) MCLK Output\r\n        (++) Audio frequency\r\n        (++) FIFO Threshold\r\n        (++) Frame Config\r\n        (++) Slot Config\r\n\r\n      (+) Call the function HAL_SAI_DeInit() to restore the default configuration\r\n          of the selected SAI peripheral.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initialize the structure FrameInit, SlotInit and the low part of\r\n  *         Init according to the specified parameters and call the function\r\n  *         HAL_SAI_Init to initialize the SAI block.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *               the configuration information for SAI module.\r\n  * @param  protocol: one of the supported protocol @ref SAI_Protocol\r\n  * @param  datasize: one of the supported datasize @ref SAI_Protocol_DataSize\r\n  *                   the configuration information for SAI module.\r\n  * @param  nbslot: Number of slot.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)\r\n{\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol));\r\n  assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize));\r\n\r\n  switch(protocol)\r\n  {\r\n  case SAI_I2S_STANDARD :\r\n  case SAI_I2S_MSBJUSTIFIED :\r\n  case SAI_I2S_LSBJUSTIFIED :\r\n    status = SAI_InitI2S(hsai, protocol, datasize, nbslot);\r\n    break;\r\n  case SAI_PCM_LONG :\r\n  case SAI_PCM_SHORT :\r\n    status = SAI_InitPCM(hsai, protocol, datasize, nbslot);\r\n    break;\r\n  default :\r\n    status = HAL_ERROR;\r\n    break;\r\n  }\r\n  \r\n  if(status == HAL_OK)\r\n  {\r\n    status = HAL_SAI_Init(hsai);\r\n  }\r\n\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Initialize the SAI according to the specified parameters.\r\n  *         in the SAI_InitTypeDef structure and initialize the associated handle.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)\r\n{\r\n  uint32_t tmpregisterGCR = 0;\r\n  uint32_t ckstr_bits = 0;\r\n  uint32_t syncen_bits = 0;\r\n\r\n  /* Check the SAI handle allocation */\r\n  if(hsai == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* check the instance */\r\n  assert_param(IS_SAI_ALL_INSTANCE(hsai->Instance));\r\n  \r\n  /* Check the SAI Block parameters */\r\n  assert_param(IS_SAI_AUDIO_FREQUENCY(hsai->Init.AudioFrequency));\r\n  assert_param(IS_SAI_BLOCK_PROTOCOL(hsai->Init.Protocol));\r\n  assert_param(IS_SAI_BLOCK_MODE(hsai->Init.AudioMode));\r\n  assert_param(IS_SAI_BLOCK_DATASIZE(hsai->Init.DataSize));\r\n  assert_param(IS_SAI_BLOCK_FIRST_BIT(hsai->Init.FirstBit));\r\n  assert_param(IS_SAI_BLOCK_CLOCK_STROBING(hsai->Init.ClockStrobing));\r\n  assert_param(IS_SAI_BLOCK_SYNCHRO(hsai->Init.Synchro));\r\n  assert_param(IS_SAI_BLOCK_OUTPUT_DRIVE(hsai->Init.OutputDrive));\r\n  assert_param(IS_SAI_BLOCK_NODIVIDER(hsai->Init.NoDivider));\r\n  assert_param(IS_SAI_BLOCK_FIFO_THRESHOLD(hsai->Init.FIFOThreshold));\r\n  assert_param(IS_SAI_MONO_STEREO_MODE(hsai->Init.MonoStereoMode));\r\n  assert_param(IS_SAI_BLOCK_COMPANDING_MODE(hsai->Init.CompandingMode));\r\n  assert_param(IS_SAI_BLOCK_TRISTATE_MANAGEMENT(hsai->Init.TriState));\r\n  assert_param(IS_SAI_BLOCK_SYNCEXT(hsai->Init.SynchroExt));\r\n  \r\n  /* Check the SAI Block Frame parameters */\r\n  assert_param(IS_SAI_BLOCK_FRAME_LENGTH(hsai->FrameInit.FrameLength));\r\n  assert_param(IS_SAI_BLOCK_ACTIVE_FRAME(hsai->FrameInit.ActiveFrameLength));\r\n  assert_param(IS_SAI_BLOCK_FS_DEFINITION(hsai->FrameInit.FSDefinition));\r\n  assert_param(IS_SAI_BLOCK_FS_POLARITY(hsai->FrameInit.FSPolarity));\r\n  assert_param(IS_SAI_BLOCK_FS_OFFSET(hsai->FrameInit.FSOffset));\r\n  \r\n  /* Check the SAI Block Slot parameters */\r\n  assert_param(IS_SAI_BLOCK_FIRSTBIT_OFFSET(hsai->SlotInit.FirstBitOffset));\r\n  assert_param(IS_SAI_BLOCK_SLOT_SIZE(hsai->SlotInit.SlotSize));\r\n  assert_param(IS_SAI_BLOCK_SLOT_NUMBER(hsai->SlotInit.SlotNumber));\r\n  assert_param(IS_SAI_SLOT_ACTIVE(hsai->SlotInit.SlotActive));\r\n  \r\n  if(hsai->State == HAL_SAI_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    hsai->Lock = HAL_UNLOCKED;\r\n    \r\n    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r\n    HAL_SAI_MspInit(hsai);\r\n  }\r\n  \r\n  hsai->State = HAL_SAI_STATE_BUSY;\r\n  \r\n  /* Disable the selected SAI peripheral */\r\n  SAI_Disable(hsai);\r\n  \r\n  /* SAI Block Synchro Configuration -----------------------------------------*/\r\n  /* This setting must be done with both audio block (A & B) disabled         */\r\n  switch(hsai->Init.SynchroExt)\r\n  {\r\n    case SAI_SYNCEXT_DISABLE :\r\n      tmpregisterGCR = 0;\r\n      break;\r\n    case SAI_SYNCEXT_OUTBLOCKA_ENABLE :\r\n      tmpregisterGCR = SAI_GCR_SYNCOUT_0;\r\n      break;\r\n    case SAI_SYNCEXT_OUTBLOCKB_ENABLE :\r\n      tmpregisterGCR = SAI_GCR_SYNCOUT_1;\r\n      break;\r\n  default:\r\n    break;\r\n  }\r\n  \r\n  switch(hsai->Init.Synchro)\r\n  {\r\n    case SAI_ASYNCHRONOUS :\r\n      {\r\n        syncen_bits = 0;\r\n      }\r\n      break;\r\n    case SAI_SYNCHRONOUS :\r\n      {\r\n        syncen_bits = SAI_xCR1_SYNCEN_0;\r\n      }\r\n      break;\r\n    case SAI_SYNCHRONOUS_EXT_SAI1 :\r\n      {\r\n        syncen_bits = SAI_xCR1_SYNCEN_1;\r\n      }\r\n      break;\r\n    case SAI_SYNCHRONOUS_EXT_SAI2 :\r\n      {\r\n        syncen_bits = SAI_xCR1_SYNCEN_1;\r\n        tmpregisterGCR |= SAI_GCR_SYNCIN_0;\r\n      }\r\n      break;\r\n  default:\r\n    break;      \r\n  }\r\n\r\n  if((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B))\r\n  {\r\n    SAI1->GCR = tmpregisterGCR;\r\n  }\r\n  else \r\n  {\r\n    SAI2->GCR = tmpregisterGCR;\r\n  }\r\n\r\n  if(hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV)\r\n  {\r\n    uint32_t freq = 0;\r\n    uint32_t tmpval;\r\n\r\n    if((hsai->Instance == SAI1_Block_A ) || (hsai->Instance == SAI1_Block_B ))\r\n    {\r\n      freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1);\r\n    }\r\n    if((hsai->Instance == SAI2_Block_A ) || (hsai->Instance == SAI2_Block_B ))\r\n    {\r\n      freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI2);\r\n    }\r\n    \r\n    /* Configure Master Clock using the following formula :\r\n       MCLK_x = SAI_CK_x / (MCKDIV[3:0] * 2) with MCLK_x = 256 * FS\r\n       FS = SAI_CK_x / (MCKDIV[3:0] * 2) * 256\r\n       MCKDIV[3:0] = SAI_CK_x / FS * 512 */\r\n    /* (freq x 10) to keep Significant digits */\r\n    tmpval = (freq * 10) / (hsai->Init.AudioFrequency * 2 * 256);\r\n    hsai->Init.Mckdiv = tmpval / 10;\r\n    \r\n    /* Round result to the nearest integer */\r\n    if((tmpval % 10) > 8)\r\n    {\r\n      hsai->Init.Mckdiv+= 1;\r\n    }\r\n  }\r\n  \r\n  /* Compute CKSTR bits of SAI CR1 according ClockStrobing and AudioMode */\r\n  if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))\r\n  { /* Transmit */\r\n    ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? 0 : SAI_xCR1_CKSTR;\r\n  }\r\n  else\r\n  { /* Receive */\r\n    ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? SAI_xCR1_CKSTR : 0;\r\n  }\r\n  \r\n  /* SAI Block Configuration -------------------------------------------------*/\r\n  /* SAI CR1 Configuration */\r\n  hsai->Instance->CR1&=~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG |  SAI_xCR1_DS |      \\\r\n                         SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN |\\\r\n                         SAI_xCR1_MONO | SAI_xCR1_OUTDRIV  | SAI_xCR1_DMAEN |  \\\r\n                         SAI_xCR1_NODIV | SAI_xCR1_MCKDIV);\r\n  \r\n  hsai->Instance->CR1|=(hsai->Init.AudioMode | hsai->Init.Protocol |           \\\r\n                        hsai->Init.DataSize | hsai->Init.FirstBit  |           \\\r\n                        ckstr_bits | syncen_bits |                               \\\r\n                        hsai->Init.MonoStereoMode | hsai->Init.OutputDrive |   \\\r\n                        hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20));\r\n  \r\n  /* SAI CR2 Configuration */\r\n  hsai->Instance->CR2&= ~(SAI_xCR2_FTH | SAI_xCR2_FFLUSH | SAI_xCR2_COMP | SAI_xCR2_CPL);\r\n  hsai->Instance->CR2|=  (hsai->Init.FIFOThreshold | hsai->Init.CompandingMode | hsai->Init.TriState);\r\n  \r\n  /* SAI Frame Configuration -----------------------------------------*/\r\n  hsai->Instance->FRCR&=(~(SAI_xFRCR_FRL | SAI_xFRCR_FSALL | SAI_xFRCR_FSDEF | \\\r\n                           SAI_xFRCR_FSPOL | SAI_xFRCR_FSOFF));\r\n  hsai->Instance->FRCR|=((hsai->FrameInit.FrameLength - 1) |\r\n                          hsai->FrameInit.FSOffset |\r\n                          hsai->FrameInit.FSDefinition |\r\n                          hsai->FrameInit.FSPolarity   |\r\n                          ((hsai->FrameInit.ActiveFrameLength - 1) << 8));\r\n  \r\n  /* SAI Block_x SLOT Configuration ------------------------------------------*/\r\n  /* This register has no meaning in AC 97 and SPDIF audio protocol */\r\n  hsai->Instance->SLOTR&= (~(SAI_xSLOTR_FBOFF | SAI_xSLOTR_SLOTSZ |            \\\r\n                             SAI_xSLOTR_NBSLOT | SAI_xSLOTR_SLOTEN ));\r\n  \r\n  hsai->Instance->SLOTR|=  hsai->SlotInit.FirstBitOffset |  hsai->SlotInit.SlotSize\r\n                          | (hsai->SlotInit.SlotActive << 16) | ((hsai->SlotInit.SlotNumber - 1) <<  8);\r\n  \r\n  /* Initialize the error code */\r\n  hsai->ErrorCode = HAL_SAI_ERROR_NONE;\r\n  \r\n  /* Initialize the SAI state */\r\n  hsai->State= HAL_SAI_STATE_READY;\r\n  \r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hsai);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  DeInitialize the SAI peripheral.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai)\r\n{\r\n  /* Check the SAI handle allocation */\r\n  if(hsai == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  hsai->State = HAL_SAI_STATE_BUSY;\r\n\r\n  /* Disabled All interrupt and clear all the flag */\r\n  hsai->Instance->IMR = 0;\r\n  hsai->Instance->CLRFR = 0xFFFFFFFFU;\r\n  \r\n  /* Disable the SAI */\r\n  SAI_Disable(hsai);\r\n\r\n  /* Flush the fifo */\r\n  SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);\r\n  \r\n  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\r\n  HAL_SAI_MspDeInit(hsai);\r\n\r\n  /* Initialize the error code */\r\n  hsai->ErrorCode = HAL_SAI_ERROR_NONE;\r\n\r\n  /* Initialize the SAI state */\r\n  hsai->State = HAL_SAI_STATE_RESET;\r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hsai);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Initialize the SAI MSP.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hsai);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_SAI_MspInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief DeInitialize the SAI MSP.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hsai);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_SAI_MspDeInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SAI_Exported_Functions_Group2 IO operation functions\r\n *  @brief    Data transfers functions\r\n *\r\n@verbatim\r\n  ==============================================================================\r\n                      ##### IO operation functions #####\r\n  ==============================================================================\r\n  [..]\r\n    This subsection provides a set of functions allowing to manage the SAI data\r\n    transfers.\r\n\r\n    (+) There are two modes of transfer:\r\n      (++) Blocking mode : The communication is performed in the polling mode.\r\n           The status of all data processing is returned by the same function\r\n           after finishing transfer.\r\n      (++) No-Blocking mode : The communication is performed using Interrupts\r\n           or DMA. These functions return the status of the transfer startup.\r\n           The end of the data processing will be indicated through the\r\n           dedicated SAI IRQ when using Interrupt mode or the DMA IRQ when\r\n           using DMA mode.\r\n\r\n    (+) Blocking mode functions are :\r\n      (++) HAL_SAI_Transmit()\r\n      (++) HAL_SAI_Receive()\r\n      (++) HAL_SAI_TransmitReceive()\r\n\r\n    (+) Non Blocking mode functions with Interrupt are :\r\n      (++) HAL_SAI_Transmit_IT()\r\n      (++) HAL_SAI_Receive_IT()\r\n      (++) HAL_SAI_TransmitReceive_IT()\r\n\r\n    (+) Non Blocking mode functions with DMA are :\r\n      (++) HAL_SAI_Transmit_DMA()\r\n      (++) HAL_SAI_Receive_DMA()\r\n      (++) HAL_SAI_TransmitReceive_DMA()\r\n\r\n    (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:\r\n      (++) HAL_SAI_TxCpltCallback()\r\n      (++) HAL_SAI_RxCpltCallback()\r\n      (++) HAL_SAI_ErrorCallback()\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Transmit an amount of data in blocking mode.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be sent\r\n  * @param  Timeout: Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint16_t Size, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = HAL_GetTick();\r\n\r\n  if((pData == NULL ) || (Size == 0))\r\n  {\r\n    return  HAL_ERROR;\r\n  }\r\n\r\n  if(hsai->State == HAL_SAI_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hsai);\r\n\r\n    hsai->XferSize = Size;\r\n    hsai->XferCount = Size;\r\n    hsai->pBuffPtr = pData;\r\n    hsai->State = HAL_SAI_STATE_BUSY_TX;\r\n    hsai->ErrorCode = HAL_SAI_ERROR_NONE;\r\n\r\n    /* Check if the SAI is already enabled */\r\n    if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)\r\n    {\r\n      /* fill the fifo with data before to enabled the SAI */\r\n      SAI_FillFifo(hsai);\r\n      /* Enable SAI peripheral */\r\n      __HAL_SAI_ENABLE(hsai);\r\n    }\r\n\r\n    while(hsai->XferCount > 0)\r\n    {\r\n      /* Write data if the FIFO is not full */\r\n      if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL)\r\n      {\r\n        if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))\r\n        {\r\n          hsai->Instance->DR = (*hsai->pBuffPtr++);\r\n        }\r\n        else if(hsai->Init.DataSize <= SAI_DATASIZE_16)\r\n        {\r\n          hsai->Instance->DR = *((uint16_t *)hsai->pBuffPtr);\r\n          hsai->pBuffPtr+= 2;\r\n        }\r\n        else\r\n        {\r\n          hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);\r\n          hsai->pBuffPtr+= 4;\r\n        }\r\n        hsai->XferCount--;\r\n      }\r\n      else\r\n      {\r\n        /* Check for the Timeout */\r\n        if((Timeout != HAL_MAX_DELAY) && ((Timeout == 0)||((HAL_GetTick() - tickstart) > Timeout)))\r\n        {\r\n          /* Update error code */\r\n          hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;\r\n\r\n          /* Clear all the flags */\r\n          hsai->Instance->CLRFR = 0xFFFFFFFFU;\r\n\r\n          /* Disable SAI peripheral */\r\n          SAI_Disable(hsai);\r\n\r\n          /* Flush the fifo */\r\n          SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);\r\n\r\n          /* Change the SAI state */\r\n          hsai->State = HAL_SAI_STATE_READY;\r\n\r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hsai);\r\n\r\n          return HAL_ERROR;\r\n        }\r\n      }\r\n    }\r\n\r\n    hsai->State = HAL_SAI_STATE_READY;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hsai);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Receive an amount of data in blocking mode.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be received\r\n  * @param  Timeout: Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = HAL_GetTick();\r\n\r\n  if((pData == NULL ) || (Size == 0))\r\n  {\r\n    return  HAL_ERROR;\r\n  }\r\n\r\n  if(hsai->State == HAL_SAI_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hsai);\r\n\r\n    hsai->pBuffPtr = pData;\r\n    hsai->XferSize = Size;\r\n    hsai->XferCount = Size;\r\n    hsai->State = HAL_SAI_STATE_BUSY_RX;\r\n    hsai->ErrorCode = HAL_SAI_ERROR_NONE;\r\n\r\n    /* Check if the SAI is already enabled */\r\n    if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)\r\n    {\r\n      /* Enable SAI peripheral */\r\n      __HAL_SAI_ENABLE(hsai);\r\n    }\r\n\r\n    /* Receive data */\r\n    while(hsai->XferCount > 0)\r\n    {\r\n      if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_EMPTY)\r\n      {\r\n        if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))\r\n        {\r\n          (*hsai->pBuffPtr++) = hsai->Instance->DR;\r\n        }\r\n        else if(hsai->Init.DataSize <= SAI_DATASIZE_16)\r\n        {\r\n          *((uint16_t*)hsai->pBuffPtr) = hsai->Instance->DR;\r\n          hsai->pBuffPtr+= 2;\r\n        }\r\n        else\r\n        {\r\n          *((uint32_t*)hsai->pBuffPtr) = hsai->Instance->DR;\r\n          hsai->pBuffPtr+= 4;\r\n        }\r\n        hsai->XferCount--;\r\n      }\r\n      else\r\n      {\r\n        /* Check for the Timeout */\r\n        if((Timeout != HAL_MAX_DELAY) && ((Timeout == 0)||((HAL_GetTick() - tickstart) > Timeout)))\r\n        {\r\n          /* Update error code */\r\n          hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;\r\n\r\n          /* Clear all the flags */\r\n          hsai->Instance->CLRFR = 0xFFFFFFFFU;\r\n\r\n          /* Disable SAI peripheral */\r\n          SAI_Disable(hsai);\r\n\r\n          /* Flush the fifo */\r\n          SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);\r\n\r\n          /* Change the SAI state */\r\n          hsai->State = HAL_SAI_STATE_READY;\r\n\r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hsai);\r\n\r\n          return HAL_ERROR;\r\n        }\r\n      }\r\n    }\r\n\r\n    hsai->State = HAL_SAI_STATE_READY;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hsai);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Transmit an amount of data in non-blocking mode with Interrupt.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)\r\n{\r\n  if((pData == NULL) || (Size == 0))\r\n  {\r\n    return  HAL_ERROR;\r\n  }\r\n\r\n  if(hsai->State == HAL_SAI_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hsai);\r\n\r\n    hsai->pBuffPtr = pData;\r\n    hsai->XferSize = Size;\r\n    hsai->XferCount = Size;\r\n    hsai->ErrorCode = HAL_SAI_ERROR_NONE;\r\n    hsai->State = HAL_SAI_STATE_BUSY_TX;\r\n\r\n    if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))\r\n    {\r\n      hsai->InterruptServiceRoutine = SAI_Transmit_IT8Bit;\r\n    }\r\n    else if(hsai->Init.DataSize <= SAI_DATASIZE_16)\r\n    {\r\n      hsai->InterruptServiceRoutine = SAI_Transmit_IT16Bit;\r\n    }\r\n    else\r\n    {\r\n      hsai->InterruptServiceRoutine = SAI_Transmit_IT32Bit;\r\n    }\r\n\r\n    /* Fill the fifo before starting the communication */\r\n    SAI_FillFifo(hsai);\r\n\r\n    /* Enable FRQ and OVRUDR interrupts */\r\n    __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));\r\n\r\n    /* Check if the SAI is already enabled */\r\n    if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)\r\n    {\r\n      /* Enable SAI peripheral */\r\n      __HAL_SAI_ENABLE(hsai);\r\n    }\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hsai);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Receive an amount of data in non-blocking mode with Interrupt.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be received\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)\r\n{\r\n  if((pData == NULL) || (Size == 0))\r\n  {\r\n    return  HAL_ERROR;\r\n  }\r\n\r\n  if(hsai->State == HAL_SAI_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hsai);\r\n\r\n    hsai->pBuffPtr = pData;\r\n    hsai->XferSize = Size;\r\n    hsai->XferCount = Size;\r\n    hsai->ErrorCode = HAL_SAI_ERROR_NONE;\r\n    hsai->State = HAL_SAI_STATE_BUSY_RX;\r\n\r\n    if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))\r\n    {\r\n      hsai->InterruptServiceRoutine = SAI_Receive_IT8Bit;\r\n    }\r\n    else if(hsai->Init.DataSize <= SAI_DATASIZE_16)\r\n    {\r\n      hsai->InterruptServiceRoutine = SAI_Receive_IT16Bit;\r\n    }\r\n    else\r\n    {\r\n      hsai->InterruptServiceRoutine = SAI_Receive_IT32Bit;\r\n    }\r\n\r\n    /* Enable TXE and OVRUDR interrupts */\r\n    __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));\r\n\r\n    /* Check if the SAI is already enabled */\r\n    if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)\r\n    {\r\n      /* Enable SAI peripheral */\r\n      __HAL_SAI_ENABLE(hsai);\r\n    }\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hsai);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Pause the audio stream playing from the Media.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hsai);\r\n\r\n  /* Pause the audio file playing by disabling the SAI DMA requests */\r\n  hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hsai);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Resume the audio stream playing from the Media.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hsai);\r\n\r\n  /* Enable the SAI DMA requests */\r\n  hsai->Instance->CR1 |= SAI_xCR1_DMAEN;\r\n\r\n  /* If the SAI peripheral is still not enabled, enable it */\r\n  if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)\r\n  {\r\n    /* Enable SAI peripheral */\r\n    __HAL_SAI_ENABLE(hsai);\r\n  }\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hsai);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Stop the audio stream playing from the Media.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hsai);\r\n\r\n  /* Disable the SAI DMA request */\r\n  hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;\r\n\r\n  /* Abort the SAI DMA Streams */\r\n  if(hsai->hdmatx != NULL)\r\n  {\r\n    if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK)\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n  }\r\n\r\n  if(hsai->hdmarx != NULL)\r\n  {\r\n    if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK)\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n  }\r\n  \r\n  /* Disable SAI peripheral */\r\n  SAI_Disable(hsai);\r\n\r\n  hsai->State = HAL_SAI_STATE_READY;\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hsai);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Abort the current transfer and disable the SAI.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hsai);\r\n\r\n  /* Check SAI DMA is enabled or not */\r\n  if((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)\r\n  {\r\n    /* Disable the SAI DMA request */\r\n    hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;\r\n    \r\n    /* Abort the SAI DMA Streams */\r\n    if(hsai->hdmatx != NULL)\r\n    {\r\n      if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK)\r\n      {\r\n        return HAL_ERROR;\r\n      }\r\n    }\r\n\r\n    if(hsai->hdmarx != NULL)\r\n    {\r\n      if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK)\r\n      {\r\n        return HAL_ERROR;\r\n      }\r\n    }\r\n  }\r\n  /* Disabled All interrupt and clear all the flag */\r\n  hsai->Instance->IMR = 0;\r\n  hsai->Instance->CLRFR = 0xFFFFFFFFU;\r\n\r\n  /* Disable SAI peripheral */\r\n  SAI_Disable(hsai);\r\n\r\n  /* Flush the fifo */\r\n  SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);\r\n\r\n  hsai->State = HAL_SAI_STATE_READY;\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hsai);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Transmit an amount of data in non-blocking mode with DMA.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)\r\n{\r\n  if((pData == NULL) || (Size == 0))\r\n  {\r\n    return  HAL_ERROR;\r\n  }\r\n\r\n  if(hsai->State == HAL_SAI_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hsai);\r\n\r\n    hsai->pBuffPtr = pData;\r\n    hsai->XferSize = Size;\r\n    hsai->XferCount = Size;\r\n    hsai->ErrorCode = HAL_SAI_ERROR_NONE;\r\n    hsai->State = HAL_SAI_STATE_BUSY_TX;\r\n\r\n    /* Set the SAI Tx DMA Half transfer complete callback */\r\n    hsai->hdmatx->XferHalfCpltCallback = SAI_DMATxHalfCplt;\r\n\r\n    /* Set the SAI TxDMA transfer complete callback */\r\n    hsai->hdmatx->XferCpltCallback = SAI_DMATxCplt;\r\n\r\n    /* Set the DMA error callback */\r\n    hsai->hdmatx->XferErrorCallback = SAI_DMAError;\r\n\r\n    /* Set the DMA Tx abort callback */\r\n    hsai->hdmatx->XferAbortCallback = NULL;\r\n\r\n    /* Enable the Tx DMA Stream */\r\n    if(HAL_DMA_Start_IT(hsai->hdmatx, (uint32_t)hsai->pBuffPtr, (uint32_t)&hsai->Instance->DR, hsai->XferSize) != HAL_OK)\r\n    {\r\n      __HAL_UNLOCK(hsai);\r\n      return  HAL_ERROR;\r\n    }\r\n\r\n    /* Check if the SAI is already enabled */\r\n    if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)\r\n    {\r\n      /* Enable SAI peripheral */\r\n      __HAL_SAI_ENABLE(hsai);\r\n    }\r\n\r\n    /* Enable the interrupts for error handling */\r\n    __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));\r\n\r\n    /* Enable SAI Tx DMA Request */\r\n    hsai->Instance->CR1 |= SAI_xCR1_DMAEN;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hsai);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Receive an amount of data in non-blocking mode with DMA.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be received\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)\r\n{\r\n\r\n  if((pData == NULL) || (Size == 0))\r\n  {\r\n    return  HAL_ERROR;\r\n  }\r\n\r\n  if(hsai->State == HAL_SAI_STATE_READY)\r\n  {\r\n    /* Process Locked */\r\n    __HAL_LOCK(hsai);\r\n\r\n    hsai->pBuffPtr = pData;\r\n    hsai->XferSize = Size;\r\n    hsai->XferCount = Size;\r\n    hsai->ErrorCode = HAL_SAI_ERROR_NONE;\r\n    hsai->State = HAL_SAI_STATE_BUSY_RX;\r\n\r\n    /* Set the SAI Rx DMA Half transfer complete callback */\r\n    hsai->hdmarx->XferHalfCpltCallback = SAI_DMARxHalfCplt;\r\n\r\n    /* Set the SAI Rx DMA transfer complete callback */\r\n    hsai->hdmarx->XferCpltCallback = SAI_DMARxCplt;\r\n\r\n    /* Set the DMA error callback */\r\n    hsai->hdmarx->XferErrorCallback = SAI_DMAError;\r\n\r\n    /* Set the DMA Rx abort callback */\r\n    hsai->hdmarx->XferAbortCallback = NULL;\r\n\r\n    /* Enable the Rx DMA Stream */\r\n    if(HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, (uint32_t)hsai->pBuffPtr, hsai->XferSize) != HAL_OK)\r\n    {\r\n      __HAL_UNLOCK(hsai);\r\n      return  HAL_ERROR;\r\n    }\r\n\r\n    /* Check if the SAI is already enabled */\r\n    if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET)\r\n    {\r\n      /* Enable SAI peripheral */\r\n      __HAL_SAI_ENABLE(hsai);\r\n    }\r\n\r\n    /* Enable the interrupts for error handling */\r\n    __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));\r\n\r\n    /* Enable SAI Rx DMA Request */\r\n    hsai->Instance->CR1 |= SAI_xCR1_DMAEN;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hsai);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Enable the Tx mute mode.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @param  val:  value sent during the mute @ref SAI_Block_Mute_Value\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val)\r\n{\r\n  assert_param(IS_SAI_BLOCK_MUTE_VALUE(val));\r\n\r\n  if(hsai->State != HAL_SAI_STATE_RESET)\r\n  {\r\n    CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);\r\n    SET_BIT(hsai->Instance->CR2, SAI_xCR2_MUTE | val);\r\n    return HAL_OK;\r\n  }\r\n  return HAL_ERROR;\r\n}\r\n\r\n/**\r\n  * @brief  Disable the Tx mute mode.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai)\r\n{\r\n  if(hsai->State != HAL_SAI_STATE_RESET)\r\n  {\r\n    CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE);\r\n    return HAL_OK;\r\n  }\r\n  return HAL_ERROR;\r\n}\r\n\r\n/**\r\n  * @brief  Enable the Rx mute detection.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @param  callback: function called when the mute is detected.\r\n  * @param  counter: number a data before mute detection max 63.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)\r\n{\r\n  assert_param(IS_SAI_BLOCK_MUTE_COUNTER(counter));\r\n\r\n  if(hsai->State != HAL_SAI_STATE_RESET)\r\n  {\r\n    /* set the mute counter */\r\n    CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTECNT);\r\n    SET_BIT(hsai->Instance->CR2, (uint32_t)((uint32_t)counter << SAI_xCR2_MUTECNT_OFFSET));\r\n    hsai->mutecallback = callback;\r\n    /* enable the IT interrupt */\r\n    __HAL_SAI_ENABLE_IT(hsai, SAI_IT_MUTEDET);\r\n    return HAL_OK;\r\n  }\r\n  return HAL_ERROR;\r\n}\r\n\r\n/**\r\n  * @brief  Disable the Rx mute detection.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai)\r\n{\r\n  if(hsai->State != HAL_SAI_STATE_RESET)\r\n  {\r\n    /* set the mutecallback to NULL */\r\n    hsai->mutecallback = (SAIcallback)NULL;\r\n    /* enable the IT interrupt */\r\n    __HAL_SAI_DISABLE_IT(hsai, SAI_IT_MUTEDET);\r\n    return HAL_OK;\r\n  }\r\n  return HAL_ERROR;\r\n}\r\n\r\n/**\r\n  * @brief  Handle SAI interrupt request.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @retval None\r\n  */\r\nvoid HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)\r\n{\r\n  if(hsai->State != HAL_SAI_STATE_RESET)\r\n  {\r\n    uint32_t itflags = hsai->Instance->SR;\r\n    uint32_t itsources = hsai->Instance->IMR;\r\n    uint32_t cr1config = hsai->Instance->CR1;    \r\n    uint32_t tmperror;\r\n\r\n    /* SAI Fifo request interrupt occured ------------------------------------*/\r\n    if(((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ))\r\n    {\r\n      hsai->InterruptServiceRoutine(hsai);\r\n    }\r\n    /* SAI Overrun error interrupt occurred ----------------------------------*/\r\n    else if(((itflags & SAI_FLAG_OVRUDR) == SAI_FLAG_OVRUDR) && ((itsources & SAI_IT_OVRUDR) == SAI_IT_OVRUDR))\r\n    {\r\n      /* Clear the SAI Overrun flag */\r\n      __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);\r\n      /* Get the SAI error code */\r\n      tmperror = ((hsai->State == HAL_SAI_STATE_BUSY_RX) ? HAL_SAI_ERROR_OVR : HAL_SAI_ERROR_UDR);      \r\n      /* Change the SAI error code */\r\n      hsai->ErrorCode |= tmperror;\r\n      /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */\r\n      HAL_SAI_ErrorCallback(hsai);\r\n    }\r\n    /* SAI mutedet interrupt occurred ----------------------------------*/\r\n    else if(((itflags & SAI_FLAG_MUTEDET) == SAI_FLAG_MUTEDET) && ((itsources & SAI_IT_MUTEDET) == SAI_IT_MUTEDET))\r\n    {\r\n      /* Clear the SAI mutedet flag */\r\n      __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_MUTEDET);\r\n      /* call the call back function */\r\n      if(hsai->mutecallback != (SAIcallback)NULL)\r\n      {\r\n        /* inform the user that an RX mute event has been detected */\r\n        hsai->mutecallback();\r\n      }\r\n    }\r\n    /* SAI AFSDET interrupt occurred ----------------------------------*/\r\n    else if(((itflags & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((itsources & SAI_IT_AFSDET) == SAI_IT_AFSDET))\r\n    {\r\n      /* Change the SAI error code */\r\n      hsai->ErrorCode |= HAL_SAI_ERROR_AFSDET;\r\n      /* Check SAI DMA is enabled or not */\r\n      if((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)\r\n      {\r\n        /* Abort the SAI DMA Streams */\r\n        if(hsai->hdmatx != NULL)\r\n        {\r\n          /* Set the DMA Tx abort callback */\r\n          hsai->hdmatx->XferAbortCallback = SAI_DMAAbort;\r\n\r\n          /* Abort DMA in IT mode */\r\n          HAL_DMA_Abort_IT(hsai->hdmatx);\r\n        }\r\n        else if(hsai->hdmarx != NULL)\r\n        {\r\n          /* Set the DMA Rx abort callback */\r\n          hsai->hdmarx->XferAbortCallback = SAI_DMAAbort;\r\n          /* Abort DMA in IT mode */\r\n          HAL_DMA_Abort_IT(hsai->hdmarx);\r\n        }\r\n      }\r\n      else\r\n      {\r\n        /* Abort SAI */ \r\n        HAL_SAI_Abort(hsai);\r\n        \r\n        /* Set error callback */\r\n        HAL_SAI_ErrorCallback(hsai);          \r\n      }\r\n    }\r\n    /* SAI LFSDET interrupt occurred ----------------------------------*/\r\n    else if(((itflags & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((itsources & SAI_IT_LFSDET) == SAI_IT_LFSDET))\r\n    {\r\n      /* Change the SAI error code */\r\n      hsai->ErrorCode |= HAL_SAI_ERROR_LFSDET;\r\n\r\n      /* Check SAI DMA is enabled or not */\r\n      if((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)\r\n      {\r\n        /* Abort the SAI DMA Streams */\r\n        if(hsai->hdmatx != NULL)\r\n        {\r\n          /* Set the DMA Tx abort callback */\r\n          hsai->hdmatx->XferAbortCallback = SAI_DMAAbort; \r\n          /* Abort DMA in IT mode */\r\n          HAL_DMA_Abort_IT(hsai->hdmatx);\r\n        }\r\n        else if(hsai->hdmarx != NULL)\r\n        {\r\n          /* Set the DMA Rx abort callback */\r\n          hsai->hdmarx->XferAbortCallback = SAI_DMAAbort; \r\n          /* Abort DMA in IT mode */          \r\n          HAL_DMA_Abort_IT(hsai->hdmarx);\r\n        }\r\n      }\r\n      else\r\n      {\r\n        /* Abort SAI */ \r\n        HAL_SAI_Abort(hsai);\r\n        \r\n        /* Set error callback */\r\n        HAL_SAI_ErrorCallback(hsai);\r\n      }\r\n    }\r\n    /* SAI WCKCFG interrupt occurred ----------------------------------*/\r\n    else if(((itflags & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((itsources & SAI_IT_WCKCFG) == SAI_IT_WCKCFG))\r\n    {\r\n      /* Change the SAI error code */\r\n      hsai->ErrorCode |= HAL_SAI_ERROR_WCKCFG;\r\n\r\n      /* Abort the SAI DMA Streams */\r\n      if(hsai->hdmatx != NULL)\r\n      {\r\n        /* Set the DMA Tx abort callback */\r\n        hsai->hdmatx->XferAbortCallback = SAI_DMAAbort; \r\n        /* Abort DMA in IT mode */\r\n        HAL_DMA_Abort_IT(hsai->hdmatx);\r\n      }\r\n      else if(hsai->hdmarx != NULL)\r\n      {\r\n        /* Set the DMA Rx abort callback */\r\n        hsai->hdmarx->XferAbortCallback = SAI_DMAAbort; \r\n        /* Abort DMA in IT mode */          \r\n        HAL_DMA_Abort_IT(hsai->hdmarx);\r\n      }\r\n      else\r\n      {\r\n        /* If WCKCFG occurs, SAI audio block is automatically disabled */\r\n        /* Disable all interrupts and clear all flags */\r\n        hsai->Instance->IMR = 0U;\r\n        hsai->Instance->CLRFR = 0xFFFFFFFFU;\r\n        /* Set the SAI state to ready to be able to start again the process */\r\n        hsai->State = HAL_SAI_STATE_READY;\r\n\r\n        /* Initialize XferCount */\r\n        hsai->XferCount = 0U;\r\n\r\n        /* SAI error Callback */\r\n        HAL_SAI_ErrorCallback(hsai);        \r\n      }\r\n    }\r\n    /* SAI CNRDY interrupt occurred ----------------------------------*/\r\n    else if(((itflags & SAI_FLAG_CNRDY) == SAI_FLAG_CNRDY) && ((itsources & SAI_IT_CNRDY) == SAI_IT_CNRDY))\r\n    {\r\n      /* Clear the SAI CNRDY flag */\r\n      __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_CNRDY);\r\n      /* Change the SAI error code */\r\n      hsai->ErrorCode |= HAL_SAI_ERROR_CNREADY;\r\n      /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */\r\n      HAL_SAI_ErrorCallback(hsai);\r\n    }\r\n    else\r\n    {\r\n      /* Nothing to do */\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Tx Transfer completed callback.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hsai);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_SAI_TxCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief Tx Transfer Half completed callback.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @retval None\r\n  */\r\n __weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hsai);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_SAI_TxHalfCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief Rx Transfer completed callback.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hsai);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_SAI_RxCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief Rx Transfer half completed callback.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hsai);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_SAI_RxHalfCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief SAI error callback.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hsai);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_SAI_ErrorCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/** @defgroup SAI_Exported_Functions_Group3 Peripheral State functions\r\n *  @brief   Peripheral State functions\r\n *\r\n@verbatim\r\n ===============================================================================\r\n                ##### Peripheral State and Errors functions #####\r\n ===============================================================================\r\n  [..]\r\n    This subsection permits to get in run-time the status of the peripheral\r\n    and the data flow.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Return the SAI handle state.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @retval HAL state\r\n  */\r\nHAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai)\r\n{\r\n  return hsai->State;\r\n}\r\n\r\n/**\r\n* @brief  Return the SAI error code.\r\n* @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *              the configuration information for the specified SAI Block.\r\n* @retval SAI Error Code\r\n*/\r\nuint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai)\r\n{\r\n  return hsai->ErrorCode;\r\n}\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup SAI_Private_Functions\r\n *  @brief      Private functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initialize the SAI I2S protocol according to the specified parameters\r\n  *         in the SAI_InitTypeDef and create the associated handle.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @param  protocol: one of the supported protocol.\r\n  * @param  datasize: one of the supported datasize @ref SAI_Protocol_DataSize\r\n  *                the configuration information for SAI module.\r\n  * @param  nbslot: number of slot minimum value is 2 and max is 16. \r\n  *                    the value must be a multiple of 2.\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)\r\n{\r\n  hsai->Init.Protocol            = SAI_FREE_PROTOCOL;\r\n  hsai->Init.FirstBit            = SAI_FIRSTBIT_MSB;\r\n  /* Compute ClockStrobing according AudioMode */\r\n  if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))\r\n  { /* Transmit */\r\n    hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_FALLINGEDGE;\r\n  }\r\n  else\r\n  { /* Receive */\r\n    hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_RISINGEDGE;\r\n  }\r\n  hsai->FrameInit.FSDefinition   = SAI_FS_CHANNEL_IDENTIFICATION;\r\n  hsai->SlotInit.SlotActive      = SAI_SLOTACTIVE_ALL;\r\n  hsai->SlotInit.FirstBitOffset  = 0;\r\n  hsai->SlotInit.SlotNumber      = nbslot;\r\n\r\n  /* in IS2 the number of slot must be even */\r\n  if((nbslot & 0x1) != 0 )\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  switch(protocol)\r\n  {\r\n  case SAI_I2S_STANDARD :\r\n    hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW;\r\n    hsai->FrameInit.FSOffset   = SAI_FS_BEFOREFIRSTBIT;\r\n    break;\r\n  case SAI_I2S_MSBJUSTIFIED :\r\n  case SAI_I2S_LSBJUSTIFIED :\r\n    hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH;\r\n    hsai->FrameInit.FSOffset   = SAI_FS_FIRSTBIT;\r\n    break;\r\n  default :\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Frame definition */\r\n  switch(datasize)\r\n  {\r\n  case SAI_PROTOCOL_DATASIZE_16BIT:\r\n    hsai->Init.DataSize = SAI_DATASIZE_16;\r\n    hsai->FrameInit.FrameLength = 32*(nbslot/2);\r\n    hsai->FrameInit.ActiveFrameLength = 16*(nbslot/2);\r\n    hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;\r\n    break;\r\n  case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :\r\n    hsai->Init.DataSize = SAI_DATASIZE_16;\r\n    hsai->FrameInit.FrameLength = 64*(nbslot/2);\r\n    hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2);\r\n    hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;\r\n    break;\r\n  case SAI_PROTOCOL_DATASIZE_24BIT:\r\n    hsai->Init.DataSize = SAI_DATASIZE_24;\r\n    hsai->FrameInit.FrameLength = 64*(nbslot/2);\r\n    hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2);\r\n    hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;\r\n    break;\r\n  case SAI_PROTOCOL_DATASIZE_32BIT:\r\n    hsai->Init.DataSize = SAI_DATASIZE_32;\r\n    hsai->FrameInit.FrameLength = 64*(nbslot/2);\r\n    hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2);\r\n    hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;\r\n    break;\r\n  default :\r\n    return HAL_ERROR;\r\n  }\r\n  if(protocol == SAI_I2S_LSBJUSTIFIED)\r\n  {\r\n    if (datasize == SAI_PROTOCOL_DATASIZE_16BITEXTENDED)\r\n    {\r\n      hsai->SlotInit.FirstBitOffset = 16;\r\n    }\r\n    if (datasize == SAI_PROTOCOL_DATASIZE_24BIT)\r\n    {\r\n      hsai->SlotInit.FirstBitOffset = 8;\r\n    }\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initialize the SAI PCM protocol according to the specified parameters\r\n  *         in the SAI_InitTypeDef and create the associated handle.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @param  protocol: one of the supported protocol\r\n  * @param  datasize: one of the supported datasize @ref SAI_Protocol_DataSize\r\n  * @param  nbslot: number of slot minimum value is 1 and the max is 16.\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)\r\n{\r\n  hsai->Init.Protocol            = SAI_FREE_PROTOCOL;\r\n  hsai->Init.FirstBit            = SAI_FIRSTBIT_MSB;\r\n  /* Compute ClockStrobing according AudioMode */\r\n  if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))\r\n  { /* Transmit */\r\n    hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_RISINGEDGE;\r\n  }\r\n  else\r\n  { /* Receive */\r\n    hsai->Init.ClockStrobing     = SAI_CLOCKSTROBING_FALLINGEDGE;\r\n  }\r\n  hsai->FrameInit.FSDefinition   = SAI_FS_STARTFRAME;\r\n  hsai->FrameInit.FSPolarity     = SAI_FS_ACTIVE_HIGH;\r\n  hsai->FrameInit.FSOffset       = SAI_FS_BEFOREFIRSTBIT;\r\n  hsai->SlotInit.FirstBitOffset  = 0;\r\n  hsai->SlotInit.SlotNumber      = nbslot;\r\n  hsai->SlotInit.SlotActive      = SAI_SLOTACTIVE_ALL;\r\n\r\n  switch(protocol)\r\n  {\r\n  case SAI_PCM_SHORT :\r\n    hsai->FrameInit.ActiveFrameLength = 1;\r\n    break;\r\n  case SAI_PCM_LONG :\r\n    hsai->FrameInit.ActiveFrameLength = 13;\r\n    break;\r\n  default :\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  switch(datasize)\r\n  {\r\n  case SAI_PROTOCOL_DATASIZE_16BIT:\r\n    hsai->Init.DataSize = SAI_DATASIZE_16;\r\n    hsai->FrameInit.FrameLength = 16 * nbslot;\r\n    hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B;\r\n    break;\r\n  case SAI_PROTOCOL_DATASIZE_16BITEXTENDED :\r\n    hsai->Init.DataSize = SAI_DATASIZE_16;\r\n    hsai->FrameInit.FrameLength = 32 * nbslot;\r\n    hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;\r\n    break;\r\n  case SAI_PROTOCOL_DATASIZE_24BIT :\r\n    hsai->Init.DataSize = SAI_DATASIZE_24;\r\n    hsai->FrameInit.FrameLength = 32 * nbslot;\r\n    hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;\r\n    break;\r\n  case SAI_PROTOCOL_DATASIZE_32BIT:\r\n    hsai->Init.DataSize = SAI_DATASIZE_32;\r\n    hsai->FrameInit.FrameLength = 32 * nbslot;\r\n    hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B;\r\n    break;\r\n  default :\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Fill the fifo.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @retval None\r\n  */\r\nstatic void SAI_FillFifo(SAI_HandleTypeDef *hsai)\r\n{\r\n  /* fill the fifo with data before to enabled the SAI */\r\n  while(((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) && (hsai->XferCount > 0))\r\n  {\r\n    if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING))\r\n    {\r\n      hsai->Instance->DR = (*hsai->pBuffPtr++);\r\n    }\r\n    else if(hsai->Init.DataSize <= SAI_DATASIZE_16)\r\n    {\r\n      hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);\r\n      hsai->pBuffPtr+= 2;\r\n    }\r\n    else\r\n    {\r\n      hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr);\r\n      hsai->pBuffPtr+= 4;\r\n    }\r\n    hsai->XferCount--;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Return the interrupt flag to set according the SAI setup.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @param  mode: SAI_MODE_DMA or SAI_MODE_IT\r\n  * @retval the list of the IT flag to enable\r\n */\r\nstatic uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode)\r\n{\r\n  uint32_t tmpIT = SAI_IT_OVRUDR;\r\n  \r\n  if(mode == SAI_MODE_IT)\r\n  {\r\n    tmpIT|= SAI_IT_FREQ;\r\n  }\r\n\r\n  if((hsai->Init.Protocol == SAI_AC97_PROTOCOL) &&\r\n    ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODEMASTER_RX)))\r\n  {\r\n    tmpIT|= SAI_IT_CNRDY;\r\n  }\r\n\r\n  if((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX))\r\n  {\r\n    tmpIT|= SAI_IT_AFSDET | SAI_IT_LFSDET;\r\n  }\r\n  else\r\n  {\r\n    /* hsai has been configured in master mode */\r\n    tmpIT|= SAI_IT_WCKCFG;\r\n  }\r\n  return tmpIT;\r\n}\r\n\r\n/**\r\n  * @brief  Disable the SAI and wait for the disabling.\r\n  * @param  hsai : pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @retval None\r\n  */\r\nstatic HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai)\r\n{\r\n  register uint32_t count = SAI_DEFAULT_TIMEOUT * (SystemCoreClock /7/1000);\r\n  HAL_StatusTypeDef status = HAL_OK;\r\n\r\n  /* Disable the SAI instance */\r\n  __HAL_SAI_DISABLE(hsai);\r\n\r\n  do \r\n  {\r\n    /* Check for the Timeout */\r\n    if (count-- == 0)\r\n    {         \r\n      /* Update error code */\r\n      hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT;\r\n      status = HAL_TIMEOUT;\r\n      break;\r\n    }\r\n  } while((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != RESET);\r\n\r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  Tx Handler for Transmit in Interrupt mode 8-Bit transfer.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @retval None\r\n  */\r\nstatic void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai)\r\n{\r\n  if(hsai->XferCount == 0)\r\n  {\r\n    /* Handle the end of the transmission */\r\n    /* Disable FREQ and OVRUDR interrupts */\r\n    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));\r\n    hsai->State = HAL_SAI_STATE_READY;\r\n    HAL_SAI_TxCpltCallback(hsai);\r\n  }\r\n  else\r\n  {\r\n    /* Write data on DR register */\r\n    hsai->Instance->DR = (*hsai->pBuffPtr++);\r\n    hsai->XferCount--;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Tx Handler for Transmit in Interrupt mode for 16-Bit transfer.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @retval None\r\n  */\r\nstatic void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai)\r\n{\r\n  if(hsai->XferCount == 0)\r\n  {\r\n    /* Handle the end of the transmission */\r\n    /* Disable FREQ and OVRUDR interrupts */\r\n    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));\r\n    hsai->State = HAL_SAI_STATE_READY;\r\n    HAL_SAI_TxCpltCallback(hsai);\r\n  }\r\n  else\r\n  {\r\n    /* Write data on DR register */\r\n    hsai->Instance->DR = *(uint16_t *)hsai->pBuffPtr;\r\n    hsai->pBuffPtr+=2;\r\n    hsai->XferCount--;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Tx Handler for Transmit in Interrupt mode for 32-Bit transfer.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @retval None\r\n  */\r\nstatic void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai)\r\n{\r\n  if(hsai->XferCount == 0)\r\n  {\r\n    /* Handle the end of the transmission */\r\n    /* Disable FREQ and OVRUDR interrupts */\r\n    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));\r\n    hsai->State = HAL_SAI_STATE_READY;\r\n    HAL_SAI_TxCpltCallback(hsai);\r\n  }\r\n  else\r\n  {\r\n    /* Write data on DR register */\r\n    hsai->Instance->DR = *(uint32_t *)hsai->pBuffPtr;\r\n    hsai->pBuffPtr+=4;\r\n    hsai->XferCount--;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Rx Handler for Receive in Interrupt mode 8-Bit transfer.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @retval None\r\n  */\r\nstatic void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai)\r\n{\r\n  /* Receive data */\r\n  (*hsai->pBuffPtr++) = hsai->Instance->DR;\r\n  hsai->XferCount--;\r\n\r\n  /* Check end of the transfer */\r\n  if(hsai->XferCount == 0)\r\n  {\r\n    /* Disable TXE and OVRUDR interrupts */\r\n    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));\r\n\r\n    /* Clear the SAI Overrun flag */\r\n    __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);\r\n    \r\n    hsai->State = HAL_SAI_STATE_READY;\r\n    HAL_SAI_RxCpltCallback(hsai);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Rx Handler for Receive in Interrupt mode for 16-Bit transfer.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @retval None\r\n  */\r\nstatic void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai)\r\n{\r\n  /* Receive data */\r\n  *(uint16_t*)hsai->pBuffPtr = hsai->Instance->DR;\r\n  hsai->pBuffPtr+=2;\r\n  hsai->XferCount--;\r\n\r\n  /* Check end of the transfer */\r\n  if(hsai->XferCount == 0)\r\n  {\r\n    /* Disable TXE and OVRUDR interrupts */\r\n    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));\r\n\r\n    /* Clear the SAI Overrun flag */\r\n    __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);\r\n\r\n    hsai->State = HAL_SAI_STATE_READY;\r\n    HAL_SAI_RxCpltCallback(hsai);\r\n  }\r\n}\r\n/**\r\n  * @brief  Rx Handler for Receive in Interrupt mode for 32-Bit transfer.\r\n  * @param  hsai: pointer to a SAI_HandleTypeDef structure that contains\r\n  *                the configuration information for SAI module.\r\n  * @retval None\r\n  */\r\nstatic void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai)\r\n{\r\n  /* Receive data */\r\n  *(uint32_t*)hsai->pBuffPtr = hsai->Instance->DR;\r\n  hsai->pBuffPtr+=4;\r\n  hsai->XferCount--;\r\n\r\n  /* Check end of the transfer */\r\n  if(hsai->XferCount == 0)\r\n  {\r\n    /* Disable TXE and OVRUDR interrupts */\r\n    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT));\r\n    \r\n    /* Clear the SAI Overrun flag */\r\n    __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR);\r\n\r\n    hsai->State = HAL_SAI_STATE_READY;\r\n    HAL_SAI_RxCpltCallback(hsai);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief DMA SAI transmit process complete callback.\r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void SAI_DMATxCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef* )hdma)->Parent;\r\n\r\n  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)\r\n  {\r\n    hsai->XferCount = 0;\r\n    \r\n    /* Disable SAI Tx DMA Request */\r\n    hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);\r\n\r\n    /* Stop the interrupts error handling */\r\n    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));\r\n    \r\n    hsai->State= HAL_SAI_STATE_READY;\r\n  }\r\n  HAL_SAI_TxCpltCallback(hsai);\r\n}\r\n\r\n/**\r\n  * @brief DMA SAI transmit process half complete callback.\r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n\r\n  HAL_SAI_TxHalfCpltCallback(hsai);\r\n}\r\n\r\n/**\r\n  * @brief DMA SAI receive process complete callback.\r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void SAI_DMARxCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)\r\n  {\r\n    /* Disable Rx DMA Request */\r\n    hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN);\r\n    hsai->XferCount = 0;\r\n\r\n    /* Stop the interrupts error handling */\r\n    __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));\r\n    \r\n    hsai->State = HAL_SAI_STATE_READY;\r\n  }\r\n  HAL_SAI_RxCpltCallback(hsai);\r\n}\r\n\r\n/**\r\n  * @brief DMA SAI receive process half complete callback \r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n\r\n  HAL_SAI_RxHalfCpltCallback(hsai);\r\n}\r\n/**\r\n  * @brief DMA SAI communication error callback.\r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void SAI_DMAError(DMA_HandleTypeDef *hdma)\r\n{\r\n  SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n\r\n  /* Set SAI error code */\r\n  hsai->ErrorCode |= HAL_SAI_ERROR_DMA;\r\n\r\n  if((hsai->hdmatx->ErrorCode == HAL_DMA_ERROR_TE) || (hsai->hdmarx->ErrorCode == HAL_DMA_ERROR_TE))\r\n  {\r\n    /* Disable the SAI DMA request */\r\n    hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;\r\n\r\n    /* Disable SAI peripheral */\r\n    SAI_Disable(hsai);\r\n    \r\n    /* Set the SAI state ready to be able to start again the process */\r\n    hsai->State = HAL_SAI_STATE_READY;\r\n\r\n    /* Initialize XferCount */\r\n    hsai->XferCount = 0U;\r\n  }\r\n  /* SAI error Callback */ \r\n  HAL_SAI_ErrorCallback(hsai);\r\n}\r\n\r\n/**\r\n  * @brief DMA SAI Abort callback. \r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void SAI_DMAAbort(DMA_HandleTypeDef *hdma)   \r\n{\r\n  SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  \r\n  /* Disable DMA request */\r\n  hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;\r\n\r\n  /* Disable all interrupts and clear all flags */\r\n  hsai->Instance->IMR = 0U;\r\n  hsai->Instance->CLRFR = 0xFFFFFFFFU;\r\n  \r\n  if(hsai->ErrorCode != HAL_SAI_ERROR_WCKCFG)\r\n  {\r\n    /* Disable SAI peripheral */\r\n    SAI_Disable(hsai);\r\n\r\n    /* Flush the fifo */\r\n    SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);\r\n  }\r\n  /* Set the SAI state to ready to be able to start again the process */\r\n  hsai->State = HAL_SAI_STATE_READY;\r\n  \r\n  /* Initialize XferCount */\r\n  hsai->XferCount = 0U;  \r\n\r\n  /* SAI error Callback */ \r\n  HAL_SAI_ErrorCallback(hsai);\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_SAI_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sai_ex.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_sai_ex.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   Empty file; This file is no longer used to set synchronization and\r\n  *          to get SAI block frequency. Its content is now moved to common files\r\n  *          (stm32f7xx_hal_sai.c/.h) as there's no device's dependency within F7\r\n  *          family. It's just kept for compatibility reasons.\r\n  *\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_sd.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   SD card HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the Secure Digital (SD) peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + IO operation functions\r\n  *           + Peripheral Control functions \r\n  *           + Peripheral State functions\r\n  *         \r\n  @verbatim\r\n  ==============================================================================\r\n                        ##### How to use this driver #####\r\n  ==============================================================================\r\n  [..]\r\n    This driver implements a high level communication layer for read and write from/to \r\n    this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by \r\n    the user in HAL_SD_MspInit() function (MSP layer).                             \r\n    Basically, the MSP layer configuration should be the same as we provide in the \r\n    examples.\r\n    You can easily tailor this configuration according to hardware resources.\r\n\r\n  [..]\r\n    This driver is a generic layered driver for SDMMC memories which uses the HAL \r\n    SDMMC driver functions to interface with SD and uSD cards devices. \r\n    It is used as follows:\r\n \r\n    (#)Initialize the SDMMC low level resources by implement the HAL_SD_MspInit() API:\r\n        (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE(); \r\n        (##) SDMMC pins configuration for SD card\r\n            (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();   \r\n            (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()\r\n                  and according to your pin assignment;\r\n        (##) DMA Configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()\r\n             and HAL_SD_WriteBlocks_DMA() APIs).\r\n            (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE(); \r\n            (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled. \r\n        (##) NVIC configuration if you need to use interrupt process when using DMA transfer.\r\n            (+++) Configure the SDMMC and DMA interrupt priorities using functions\r\n                  HAL_NVIC_SetPriority(); DMA priority is superior to SDMMC's priority\r\n            (+++) Enable the NVIC DMA and SDMMC IRQs using function HAL_NVIC_EnableIRQ()\r\n            (+++) SDMMC interrupts are managed using the macros __HAL_SD_SDMMC_ENABLE_IT() \r\n                  and __HAL_SD_SDMMC_DISABLE_IT() inside the communication process.\r\n            (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_SDMMC_GET_IT()\r\n                  and __HAL_SD_SDMMC_CLEAR_IT()\r\n    (#) At this stage, you can perform SD read/write/erase operations after SD card initialization  \r\n\r\n         \r\n  *** SD Card Initialization and configuration ***\r\n  ================================================    \r\n  [..]\r\n    To initialize the SD Card, use the HAL_SD_Init() function.  It Initializes \r\n    the SD Card and put it into StandBy State (Ready for data transfer). \r\n    This function provide the following operations:\r\n  \r\n    (#) Apply the SD Card initialization process at 400KHz and check the SD Card \r\n        type (Standard Capacity or High Capacity). You can change or adapt this \r\n        frequency by adjusting the \"ClockDiv\" field. \r\n        The SD Card frequency (SDMMC_CK) is computed as follows:\r\n  \r\n           SDMMC_CK = SDMMCCLK / (ClockDiv + 2)\r\n  \r\n        In initialization mode and according to the SD Card standard, \r\n        make sure that the SDMMC_CK frequency doesn't exceed 400KHz.\r\n  \r\n    (#) Get the SD CID and CSD data. All these information are managed by the SDCardInfo \r\n        structure. This structure provide also ready computed SD Card capacity \r\n        and Block size.\r\n        \r\n        -@- These information are stored in SD handle structure in case of future use.  \r\n  \r\n    (#) Configure the SD Card Data transfer frequency. By Default, the card transfer \r\n        frequency is set to 24MHz. You can change or adapt this frequency by adjusting \r\n        the \"ClockDiv\" field.\r\n        In transfer mode and according to the SD Card standard, make sure that the \r\n        SDMMC_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.\r\n        To be able to use a frequency higher than 24MHz, you should use the SDMMC \r\n        peripheral in bypass mode. Refer to the corresponding reference manual \r\n        for more details.\r\n  \r\n    (#) Select the corresponding SD Card according to the address read with the step 2.\r\n    \r\n    (#) Configure the SD Card in wide bus mode: 4-bits data.\r\n  \r\n  *** SD Card Read operation ***\r\n  ==============================\r\n  [..] \r\n    (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks(). \r\n        This function support only 512-bytes block length (the block size should be \r\n        chosen as 512 bytes).\r\n        You can choose either one block read operation or multiple block read operation \r\n        by adjusting the \"NumberOfBlocks\" parameter.\r\n\r\n    (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().\r\n        This function support only 512-bytes block length (the block size should be \r\n        chosen as 512 bytes).\r\n        You can choose either one block read operation or multiple block read operation \r\n        by adjusting the \"NumberOfBlocks\" parameter.\r\n        After this, you have to call the function HAL_SD_CheckReadOperation(), to insure\r\n        that the read transfer is done correctly in both DMA and SD sides.\r\n  \r\n  *** SD Card Write operation ***\r\n  =============================== \r\n  [..] \r\n    (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks(). \r\n        This function support only 512-bytes block length (the block size should be \r\n        chosen as 512 bytes).\r\n        You can choose either one block read operation or multiple block read operation \r\n        by adjusting the \"NumberOfBlocks\" parameter.\r\n\r\n    (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().\r\n        This function support only 512-bytes block length (the block size should be \r\n        chosen as 512 byte).\r\n        You can choose either one block read operation or multiple block read operation \r\n        by adjusting the \"NumberOfBlocks\" parameter.\r\n        After this, you have to call the function HAL_SD_CheckWriteOperation(), to insure\r\n        that the write transfer is done correctly in both DMA and SD sides.  \r\n  \r\n  *** SD card status ***\r\n  ====================== \r\n  [..]\r\n    (+) At any time, you can check the SD Card status and get the SD card state \r\n        by using the HAL_SD_GetStatus() function. This function checks first if the \r\n        SD card is still connected and then get the internal SD Card transfer state.     \r\n    (+) You can also get the SD card SD Status register by using the HAL_SD_SendSDStatus() \r\n        function.    \r\n\r\n  *** SD HAL driver macros list ***\r\n  ==================================\r\n  [..]\r\n    Below the list of most used macros in SD HAL driver.\r\n       \r\n    (+) __HAL_SD_SDMMC_ENABLE : Enable the SD device\r\n    (+) __HAL_SD_SDMMC_DISABLE : Disable the SD device\r\n    (+) __HAL_SD_SDMMC_DMA_ENABLE: Enable the SDMMC DMA transfer\r\n    (+) __HAL_SD_SDMMC_DMA_DISABLE: Disable the SDMMC DMA transfer\r\n    (+) __HAL_SD_SDMMC_ENABLE_IT: Enable the SD device interrupt\r\n    (+) __HAL_SD_SDMMC_DISABLE_IT: Disable the SD device interrupt\r\n    (+) __HAL_SD_SDMMC_GET_FLAG:Check whether the specified SD flag is set or not\r\n    (+) __HAL_SD_SDMMC_CLEAR_FLAG: Clear the SD's pending flags\r\n      \r\n    (@) You can refer to the SD HAL driver header file for more useful macros \r\n      \r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup SD \r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_SD_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @addtogroup SD_Private_Defines\r\n  * @{\r\n  */\r\n/** \r\n  * @brief  SDMMC Data block size \r\n  */ \r\n#define DATA_BLOCK_SIZE                  ((uint32_t)(9 << 4))\r\n/** \r\n  * @brief  SDMMC Static flags, Timeout, FIFO Address  \r\n  */\r\n#define SDMMC_STATIC_FLAGS               ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\\\r\n                                                    SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR  |\\\r\n                                                    SDMMC_FLAG_CMDREND  | SDMMC_FLAG_CMDSENT  | SDMMC_FLAG_DATAEND  |\\\r\n                                                    SDMMC_FLAG_DBCKEND))  \r\n\r\n#define SDMMC_CMD0TIMEOUT                ((uint32_t)0x00010000U)\r\n\r\n/** \r\n  * @brief  Mask for errors Card Status R1 (OCR Register) \r\n  */\r\n#define SD_OCR_ADDR_OUT_OF_RANGE        ((uint32_t)0x80000000U)\r\n#define SD_OCR_ADDR_MISALIGNED          ((uint32_t)0x40000000U)\r\n#define SD_OCR_BLOCK_LEN_ERR            ((uint32_t)0x20000000U)\r\n#define SD_OCR_ERASE_SEQ_ERR            ((uint32_t)0x10000000U)\r\n#define SD_OCR_BAD_ERASE_PARAM          ((uint32_t)0x08000000U)\r\n#define SD_OCR_WRITE_PROT_VIOLATION     ((uint32_t)0x04000000U)\r\n#define SD_OCR_LOCK_UNLOCK_FAILED       ((uint32_t)0x01000000U)\r\n#define SD_OCR_COM_CRC_FAILED           ((uint32_t)0x00800000U)\r\n#define SD_OCR_ILLEGAL_CMD              ((uint32_t)0x00400000U)\r\n#define SD_OCR_CARD_ECC_FAILED          ((uint32_t)0x00200000U)\r\n#define SD_OCR_CC_ERROR                 ((uint32_t)0x00100000U)\r\n#define SD_OCR_GENERAL_UNKNOWN_ERROR    ((uint32_t)0x00080000U)\r\n#define SD_OCR_STREAM_READ_UNDERRUN     ((uint32_t)0x00040000U)\r\n#define SD_OCR_STREAM_WRITE_OVERRUN     ((uint32_t)0x00020000U)\r\n#define SD_OCR_CID_CSD_OVERWRITE        ((uint32_t)0x00010000U)\r\n#define SD_OCR_WP_ERASE_SKIP            ((uint32_t)0x00008000U)\r\n#define SD_OCR_CARD_ECC_DISABLED        ((uint32_t)0x00004000U)\r\n#define SD_OCR_ERASE_RESET              ((uint32_t)0x00002000U)\r\n#define SD_OCR_AKE_SEQ_ERROR            ((uint32_t)0x00000008U)\r\n#define SD_OCR_ERRORBITS                ((uint32_t)0xFDFFE008U)\r\n\r\n/** \r\n  * @brief  Masks for R6 Response \r\n  */\r\n#define SD_R6_GENERAL_UNKNOWN_ERROR     ((uint32_t)0x00002000U)\r\n#define SD_R6_ILLEGAL_CMD               ((uint32_t)0x00004000U)\r\n#define SD_R6_COM_CRC_FAILED            ((uint32_t)0x00008000U)\r\n\r\n#define SD_VOLTAGE_WINDOW_SD            ((uint32_t)0x80100000U)\r\n#define SD_HIGH_CAPACITY                ((uint32_t)0x40000000U)\r\n#define SD_STD_CAPACITY                 ((uint32_t)0x00000000U)\r\n#define SD_CHECK_PATTERN                ((uint32_t)0x000001AAU)\r\n\r\n#define SD_MAX_VOLT_TRIAL               ((uint32_t)0x0000FFFFU)\r\n#define SD_ALLZERO                      ((uint32_t)0x00000000U)\r\n\r\n#define SD_WIDE_BUS_SUPPORT             ((uint32_t)0x00040000U)\r\n#define SD_SINGLE_BUS_SUPPORT           ((uint32_t)0x00010000U)\r\n#define SD_CARD_LOCKED                  ((uint32_t)0x02000000U)\r\n\r\n#define SD_DATATIMEOUT                  ((uint32_t)0xFFFFFFFFU)\r\n#define SD_0TO7BITS                     ((uint32_t)0x000000FFU)\r\n#define SD_8TO15BITS                    ((uint32_t)0x0000FF00U)\r\n#define SD_16TO23BITS                   ((uint32_t)0x00FF0000U)\r\n#define SD_24TO31BITS                   ((uint32_t)0xFF000000U)\r\n#define SD_MAX_DATA_LENGTH              ((uint32_t)0x01FFFFFFU)\r\n\r\n#define SD_HALFFIFO                     ((uint32_t)0x00000008U)\r\n#define SD_HALFFIFOBYTES                ((uint32_t)0x00000020U)\r\n\r\n/** \r\n  * @brief  Command Class Supported \r\n  */\r\n#define SD_CCCC_LOCK_UNLOCK             ((uint32_t)0x00000080U)\r\n#define SD_CCCC_WRITE_PROT              ((uint32_t)0x00000040U)\r\n#define SD_CCCC_ERASE                   ((uint32_t)0x00000020U)\r\n\r\n/** \r\n  * @brief  Following commands are SD Card Specific commands.\r\n  *         SDMMC_APP_CMD should be sent before sending these commands. \r\n  */\r\n#define SD_SDMMC_SEND_IF_COND            ((uint32_t)SD_CMD_HS_SEND_EXT_CSD)\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @defgroup SD_Private_Functions SD Private Functions\r\n  * @{\r\n  */\r\nstatic HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd);\r\nstatic HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr);\r\nstatic HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd); \r\nstatic HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd);\r\nstatic HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus);\r\nstatic HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd);\r\nstatic HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus);\r\nstatic HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd);\r\nstatic HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD);\r\nstatic HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd);\r\nstatic HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd);\r\nstatic HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd);\r\nstatic HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA);\r\nstatic HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd);\r\nstatic HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd);\r\nstatic HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR);  \r\nstatic void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma);\r\nstatic void SD_DMA_RxError(DMA_HandleTypeDef *hdma);\r\nstatic void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma);\r\nstatic void SD_DMA_TxError(DMA_HandleTypeDef *hdma);\r\n/**\r\n  * @}\r\n  */\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @addtogroup SD_Exported_Functions\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup SD_Exported_Functions_Group1\r\n *  @brief   Initialization and de-initialization functions \r\n *\r\n@verbatim    \r\n  ==============================================================================\r\n          ##### Initialization and de-initialization functions #####\r\n  ==============================================================================\r\n  [..]  \r\n    This section provides functions allowing to initialize/de-initialize the SD\r\n    card device to be ready for use.\r\n      \r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the SD card according to the specified parameters in the \r\n            SD_HandleTypeDef and create the associated handle.\r\n  * @param  hsd: SD handle\r\n  * @param  SDCardInfo: HAL_SD_CardInfoTypedef structure for SD card information   \r\n  * @retval HAL SD error state\r\n  */\r\nHAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo)\r\n{ \r\n  __IO HAL_SD_ErrorTypedef errorstate = SD_OK;\r\n  SD_InitTypeDef tmpinit;\r\n  \r\n  /* Allocate lock resource and initialize it */\r\n  hsd->Lock = HAL_UNLOCKED;\r\n  \r\n  /* Initialize the low level hardware (MSP) */\r\n  HAL_SD_MspInit(hsd);\r\n  \r\n  /* Default SDMMC peripheral configuration for SD card initialization */\r\n  tmpinit.ClockEdge           = SDMMC_CLOCK_EDGE_RISING;\r\n  tmpinit.ClockBypass         = SDMMC_CLOCK_BYPASS_DISABLE;\r\n  tmpinit.ClockPowerSave      = SDMMC_CLOCK_POWER_SAVE_DISABLE;\r\n  tmpinit.BusWide             = SDMMC_BUS_WIDE_1B;\r\n  tmpinit.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;\r\n  tmpinit.ClockDiv            = SDMMC_INIT_CLK_DIV;\r\n  \r\n  /* Initialize SDMMC peripheral interface with default configuration */\r\n  SDMMC_Init(hsd->Instance, tmpinit);\r\n  \r\n  /* Identify card operating voltage */\r\n  errorstate = SD_PowerON(hsd); \r\n  \r\n  if(errorstate != SD_OK)     \r\n  {\r\n    return errorstate;\r\n  }\r\n  \r\n  /* Initialize the present SDMMC card(s) and put them in idle state */\r\n  errorstate = SD_Initialize_Cards(hsd);\r\n  \r\n  if (errorstate != SD_OK)\r\n  {\r\n    return errorstate;\r\n  }\r\n  \r\n  /* Read CSD/CID MSD registers */\r\n  errorstate = HAL_SD_Get_CardInfo(hsd, SDCardInfo);\r\n  \r\n  if (errorstate == SD_OK)\r\n  {\r\n    /* Select the Card */\r\n    errorstate = SD_Select_Deselect(hsd, (uint32_t)(((uint32_t)SDCardInfo->RCA) << 16));\r\n  }\r\n  \r\n  /* Configure SDMMC peripheral interface */\r\n  SDMMC_Init(hsd->Instance, hsd->Init);   \r\n  \r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  De-Initializes the SD card.\r\n  * @param  hsd: SD handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)\r\n{\r\n  \r\n  /* Set SD power state to off */ \r\n  SD_PowerOFF(hsd);\r\n  \r\n  /* De-Initialize the MSP layer */\r\n  HAL_SD_MspDeInit(hsd);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Initializes the SD MSP.\r\n  * @param  hsd: SD handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hsd);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_SD_MspInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  De-Initialize SD MSP.\r\n  * @param  hsd: SD handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hsd);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_SD_MspDeInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup SD_Exported_Functions_Group2\r\n *  @brief   Data transfer functions \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                        ##### IO operation functions #####\r\n  ==============================================================================  \r\n  [..]\r\n    This subsection provides a set of functions allowing to manage the data \r\n    transfer from/to SD card.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Reads block(s) from a specified address in a card. The Data transfer \r\n  *         is managed by polling mode.  \r\n  * @param  hsd: SD handle\r\n  * @param  pReadBuffer: pointer to the buffer that will contain the received data\r\n  * @param  ReadAddr: Address from where data is to be read  \r\n  * @param  BlockSize: SD card Data block size \r\n  *   @note BlockSize must be 512 bytes.\r\n  * @param  NumberOfBlocks: Number of SD blocks to read   \r\n  * @retval SD Card error state\r\n  */\r\nHAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)\r\n{\r\n  SDMMC_CmdInitTypeDef  sdmmc_cmdinitstructure;\r\n  SDMMC_DataInitTypeDef sdmmc_datainitstructure;\r\n  HAL_SD_ErrorTypedef errorstate = SD_OK;\r\n  uint32_t count = 0, *tempbuff = (uint32_t *)pReadBuffer;\r\n  \r\n  /* Initialize data control register */\r\n  hsd->Instance->DCTRL = 0;\r\n  \r\n  if (hsd->CardType == HIGH_CAPACITY_SD_CARD)\r\n  {\r\n    BlockSize = 512;\r\n    ReadAddr /= 512;\r\n  }\r\n  \r\n  /* Set Block Size for Card */ \r\n  sdmmc_cmdinitstructure.Argument         = (uint32_t) BlockSize;\r\n  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;\r\n  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;\r\n  sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);\r\n  \r\n  if (errorstate != SD_OK)\r\n  {\r\n    return errorstate;\r\n  }\r\n  \r\n  /* Configure the SD DPSM (Data Path State Machine) */\r\n  sdmmc_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;\r\n  sdmmc_datainitstructure.DataLength    = NumberOfBlocks * BlockSize;\r\n  sdmmc_datainitstructure.DataBlockSize = DATA_BLOCK_SIZE;\r\n  sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;\r\n  sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;\r\n  sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;\r\n  SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);\r\n  \r\n  if(NumberOfBlocks > 1)\r\n  {\r\n    /* Send CMD18 READ_MULT_BLOCK with argument data address */\r\n    sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK;\r\n  }\r\n  else\r\n  {\r\n    /* Send CMD17 READ_SINGLE_BLOCK */\r\n    sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK;    \r\n  }\r\n  \r\n  sdmmc_cmdinitstructure.Argument         = (uint32_t)ReadAddr;\r\n  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r\n  \r\n  /* Read block(s) in polling mode */\r\n  if(NumberOfBlocks > 1)\r\n  {\r\n    /* Check for error conditions */\r\n    errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK);\r\n    \r\n    if (errorstate != SD_OK)\r\n    {\r\n      return errorstate;\r\n    }\r\n    \r\n    /* Poll on SDMMC flags */\r\n    while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))\r\n    {\r\n      if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))\r\n      {\r\n        /* Read data from SDMMC Rx FIFO */\r\n        for (count = 0; count < 8; count++)\r\n        {\r\n          *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance);\r\n        }\r\n        \r\n        tempbuff += 8;\r\n      }\r\n    }      \r\n  }\r\n  else\r\n  {\r\n    /* Check for error conditions */\r\n    errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK); \r\n    \r\n    if (errorstate != SD_OK)\r\n    {\r\n      return errorstate;\r\n    }    \r\n    \r\n    /* In case of single block transfer, no need of stop transfer at all */\r\n    while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))\r\n    {\r\n      if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))\r\n      {\r\n        /* Read data from SDMMC Rx FIFO */\r\n        for (count = 0; count < 8; count++)\r\n        {\r\n          *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance);\r\n        }\r\n        \r\n        tempbuff += 8;\r\n      }\r\n    }   \r\n  }\r\n  \r\n  /* Send stop transmission command in case of multiblock read */\r\n  if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1))\r\n  {    \r\n    if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) ||\\\r\n      (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\\\r\n        (hsd->CardType == HIGH_CAPACITY_SD_CARD))\r\n    {\r\n      /* Send stop transmission command */\r\n      errorstate = HAL_SD_StopTransfer(hsd);\r\n    }\r\n  }\r\n  \r\n  /* Get error state */\r\n  if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))\r\n  {\r\n    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);\r\n    \r\n    errorstate = SD_DATA_TIMEOUT;\r\n    \r\n    return errorstate;\r\n  }\r\n  else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))\r\n  {\r\n    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);\r\n    \r\n    errorstate = SD_DATA_CRC_FAIL;\r\n    \r\n    return errorstate;\r\n  }\r\n  else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))\r\n  {\r\n    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);\r\n    \r\n    errorstate = SD_RX_OVERRUN;\r\n    \r\n    return errorstate;\r\n  }\r\n  else\r\n  {\r\n    /* No error flag set */\r\n  }\r\n  \r\n  count = SD_DATATIMEOUT;\r\n  \r\n  /* Empty FIFO if there is still any data */\r\n  while ((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) && (count > 0))\r\n  {\r\n    *tempbuff = SDMMC_ReadFIFO(hsd->Instance);\r\n    tempbuff++;\r\n    count--;\r\n  }\r\n  \r\n  /* Clear all the static flags */\r\n  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r\n  \r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Allows to write block(s) to a specified address in a card. The Data\r\n  *         transfer is managed by polling mode.  \r\n  * @param  hsd: SD handle\r\n  * @param  pWriteBuffer: pointer to the buffer that will contain the data to transmit\r\n  * @param  WriteAddr: Address from where data is to be written \r\n  * @param  BlockSize: SD card Data block size \r\n  * @note   BlockSize must be 512 bytes.\r\n  * @param  NumberOfBlocks: Number of SD blocks to write \r\n  * @retval SD Card error state\r\n  */\r\nHAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)\r\n{\r\n  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r\n  SDMMC_DataInitTypeDef sdmmc_datainitstructure;\r\n  HAL_SD_ErrorTypedef errorstate = SD_OK;\r\n  uint32_t totalnumberofbytes = 0, bytestransferred = 0, count = 0, restwords = 0;\r\n  uint32_t *tempbuff = (uint32_t *)pWriteBuffer;\r\n  uint8_t cardstate  = 0;\r\n  \r\n  /* Initialize data control register */\r\n  hsd->Instance->DCTRL = 0;\r\n  \r\n  if (hsd->CardType == HIGH_CAPACITY_SD_CARD)\r\n  {\r\n    BlockSize = 512;\r\n    WriteAddr /= 512;\r\n  }\r\n  \r\n  /* Set Block Size for Card */ \r\n  sdmmc_cmdinitstructure.Argument         = (uint32_t)BlockSize;\r\n  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;\r\n  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;\r\n  sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);\r\n  \r\n  if (errorstate != SD_OK)\r\n  {\r\n    return errorstate;\r\n  }\r\n  \r\n  if(NumberOfBlocks > 1)\r\n  {\r\n    /* Send CMD25 WRITE_MULT_BLOCK with argument data address */\r\n    sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK;\r\n  }\r\n  else\r\n  {\r\n    /* Send CMD24 WRITE_SINGLE_BLOCK */\r\n    sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;\r\n  }\r\n  \r\n  sdmmc_cmdinitstructure.Argument         = (uint32_t)WriteAddr;\r\n  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r\n  \r\n  /* Check for error conditions */\r\n  if(NumberOfBlocks > 1)\r\n  {\r\n    errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK);\r\n  }\r\n  else\r\n  {\r\n    errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK);\r\n  }  \r\n  \r\n  if (errorstate != SD_OK)\r\n  {\r\n    return errorstate;\r\n  }\r\n  \r\n  /* Set total number of bytes to write */\r\n  totalnumberofbytes = NumberOfBlocks * BlockSize;\r\n  \r\n  /* Configure the SD DPSM (Data Path State Machine) */ \r\n  sdmmc_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;\r\n  sdmmc_datainitstructure.DataLength    = NumberOfBlocks * BlockSize;\r\n  sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;\r\n  sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;\r\n  sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;\r\n  sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;\r\n  SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);\r\n  \r\n  /* Write block(s) in polling mode */\r\n  if(NumberOfBlocks > 1)\r\n  {\r\n    while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))\r\n    {\r\n      if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE))\r\n      {\r\n        if ((totalnumberofbytes - bytestransferred) < 32)\r\n        {\r\n          restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes -  bytestransferred) / 4 + 1);\r\n          \r\n          /* Write data to SDMMC Tx FIFO */\r\n          for (count = 0; count < restwords; count++)\r\n          {\r\n            SDMMC_WriteFIFO(hsd->Instance, tempbuff);\r\n            tempbuff++;\r\n            bytestransferred += 4;\r\n          }\r\n        }\r\n        else\r\n        {\r\n          /* Write data to SDMMC Tx FIFO */\r\n          for (count = 0; count < 8; count++)\r\n          {\r\n            SDMMC_WriteFIFO(hsd->Instance, (tempbuff + count));\r\n          }\r\n          \r\n          tempbuff += 8;\r\n          bytestransferred += 32;\r\n        }\r\n      }\r\n    }   \r\n  }\r\n  else\r\n  {\r\n    /* In case of single data block transfer no need of stop command at all */ \r\n    while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))\r\n    {\r\n      if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE))\r\n      {\r\n        if ((totalnumberofbytes - bytestransferred) < 32)\r\n        {\r\n          restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes -  bytestransferred) / 4 + 1);\r\n          \r\n          /* Write data to SDMMC Tx FIFO */\r\n          for (count = 0; count < restwords; count++)\r\n          {\r\n            SDMMC_WriteFIFO(hsd->Instance, tempbuff);\r\n            tempbuff++; \r\n            bytestransferred += 4;\r\n          }\r\n        }\r\n        else\r\n        {\r\n          /* Write data to SDMMC Tx FIFO */\r\n          for (count = 0; count < 8; count++)\r\n          {\r\n            SDMMC_WriteFIFO(hsd->Instance, (tempbuff + count));\r\n          }\r\n          \r\n          tempbuff += 8;\r\n          bytestransferred += 32;\r\n        }\r\n      }\r\n    }  \r\n  }\r\n  \r\n  /* Send stop transmission command in case of multiblock write */\r\n  if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1))\r\n  {    \r\n    if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\\\r\n      (hsd->CardType == HIGH_CAPACITY_SD_CARD))\r\n    {\r\n      /* Send stop transmission command */\r\n      errorstate = HAL_SD_StopTransfer(hsd);\r\n    }\r\n  }\r\n  \r\n  /* Get error state */\r\n  if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))\r\n  {\r\n    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);\r\n    \r\n    errorstate = SD_DATA_TIMEOUT;\r\n    \r\n    return errorstate;\r\n  }\r\n  else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))\r\n  {\r\n    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);\r\n    \r\n    errorstate = SD_DATA_CRC_FAIL;\r\n    \r\n    return errorstate;\r\n  }\r\n  else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR))\r\n  {\r\n    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_TXUNDERR);\r\n    \r\n    errorstate = SD_TX_UNDERRUN;\r\n    \r\n    return errorstate;\r\n  }\r\n  else\r\n  {\r\n    /* No error flag set */\r\n  }\r\n  \r\n  /* Clear all the static flags */\r\n  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r\n  \r\n  /* Wait till the card is in programming state */\r\n  errorstate = SD_IsCardProgramming(hsd, &cardstate);\r\n  \r\n  while ((errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING)))\r\n  {\r\n    errorstate = SD_IsCardProgramming(hsd, &cardstate);\r\n  }\r\n  \r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Reads block(s) from a specified address in a card. The Data transfer \r\n  *         is managed by DMA mode. \r\n  * @note   This API should be followed by the function HAL_SD_CheckReadOperation()\r\n  *         to check the completion of the read process   \r\n  * @param  hsd: SD handle                 \r\n  * @param  pReadBuffer: Pointer to the buffer that will contain the received data\r\n  * @param  ReadAddr: Address from where data is to be read  \r\n  * @param  BlockSize: SD card Data block size \r\n  * @note   BlockSize must be 512 bytes.\r\n  * @param  NumberOfBlocks: Number of blocks to read.\r\n  * @retval SD Card error state\r\n  */\r\nHAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)\r\n{\r\n  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r\n  SDMMC_DataInitTypeDef sdmmc_datainitstructure;\r\n  HAL_SD_ErrorTypedef errorstate = SD_OK;\r\n  \r\n  /* Initialize data control register */\r\n  hsd->Instance->DCTRL = 0;\r\n  \r\n  /* Initialize handle flags */\r\n  hsd->SdTransferCplt  = 0;\r\n  hsd->DmaTransferCplt = 0;\r\n  hsd->SdTransferErr   = SD_OK; \r\n  \r\n  /* Initialize SD Read operation */\r\n  if(NumberOfBlocks > 1)\r\n  {\r\n    hsd->SdOperation = SD_READ_MULTIPLE_BLOCK;\r\n  }\r\n  else\r\n  {\r\n    hsd->SdOperation = SD_READ_SINGLE_BLOCK;\r\n  }\r\n  \r\n  /* Enable transfer interrupts */\r\n  __HAL_SD_SDMMC_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL |\\\r\n                                 SDMMC_IT_DTIMEOUT |\\\r\n                                 SDMMC_IT_DATAEND  |\\\r\n                                 SDMMC_IT_RXOVERR));\r\n  \r\n  /* Enable SDMMC DMA transfer */\r\n  __HAL_SD_SDMMC_DMA_ENABLE(hsd);\r\n  \r\n  /* Configure DMA user callbacks */\r\n  hsd->hdmarx->XferCpltCallback  = SD_DMA_RxCplt;\r\n  hsd->hdmarx->XferErrorCallback = SD_DMA_RxError;\r\n  \r\n  /* Enable the DMA Channel */\r\n  HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pReadBuffer, (uint32_t)(BlockSize * NumberOfBlocks)/4);\r\n  \r\n  if (hsd->CardType == HIGH_CAPACITY_SD_CARD)\r\n  {\r\n    BlockSize = 512;\r\n    ReadAddr /= 512;\r\n  }\r\n  \r\n  /* Set Block Size for Card */ \r\n  sdmmc_cmdinitstructure.Argument         = (uint32_t)BlockSize;\r\n  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;\r\n  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;\r\n  sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);\r\n  \r\n  if (errorstate != SD_OK)\r\n  {\r\n    return errorstate;\r\n  }\r\n  \r\n  /* Configure the SD DPSM (Data Path State Machine) */ \r\n  sdmmc_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;\r\n  sdmmc_datainitstructure.DataLength    = BlockSize * NumberOfBlocks;\r\n  sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;\r\n  sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;\r\n  sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;\r\n  sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;\r\n  SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);\r\n  \r\n  /* Check number of blocks command */\r\n  if(NumberOfBlocks > 1)\r\n  {\r\n    /* Send CMD18 READ_MULT_BLOCK with argument data address */\r\n    sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK;\r\n  }\r\n  else\r\n  {\r\n    /* Send CMD17 READ_SINGLE_BLOCK */\r\n    sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK;\r\n  }\r\n  \r\n  sdmmc_cmdinitstructure.Argument         = (uint32_t)ReadAddr;\r\n  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r\n  \r\n  /* Check for error conditions */\r\n  if(NumberOfBlocks > 1)\r\n  {\r\n    errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK);\r\n  }\r\n  else\r\n  {\r\n    errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK);\r\n  }\r\n  \r\n  /* Update the SD transfer error in SD handle */\r\n  hsd->SdTransferErr = errorstate;\r\n  \r\n  return errorstate;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Writes block(s) to a specified address in a card. The Data transfer \r\n  *         is managed by DMA mode. \r\n  * @note   This API should be followed by the function HAL_SD_CheckWriteOperation()\r\n  *         to check the completion of the write process (by SD current status polling).  \r\n  * @param  hsd: SD handle\r\n  * @param  pWriteBuffer: pointer to the buffer that will contain the data to transmit\r\n  * @param  WriteAddr: Address from where data is to be read   \r\n  * @param  BlockSize: the SD card Data block size \r\n  * @note   BlockSize must be 512 bytes.\r\n  * @param  NumberOfBlocks: Number of blocks to write\r\n  * @retval SD Card error state\r\n  */\r\nHAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)\r\n{\r\n  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r\n  SDMMC_DataInitTypeDef sdmmc_datainitstructure;\r\n  HAL_SD_ErrorTypedef errorstate = SD_OK;\r\n  \r\n  /* Initialize data control register */\r\n  hsd->Instance->DCTRL = 0;\r\n  \r\n  /* Initialize handle flags */\r\n  hsd->SdTransferCplt  = 0;\r\n  hsd->DmaTransferCplt = 0;\r\n  hsd->SdTransferErr   = SD_OK;\r\n  \r\n  /* Initialize SD Write operation */\r\n  if(NumberOfBlocks > 1)\r\n  {\r\n    hsd->SdOperation = SD_WRITE_MULTIPLE_BLOCK;\r\n  }\r\n  else\r\n  {\r\n    hsd->SdOperation = SD_WRITE_SINGLE_BLOCK;\r\n  }  \r\n  \r\n  /* Enable transfer interrupts */\r\n  __HAL_SD_SDMMC_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL |\\\r\n                                 SDMMC_IT_DTIMEOUT |\\\r\n                                 SDMMC_IT_DATAEND  |\\\r\n                                 SDMMC_IT_TXUNDERR)); \r\n  \r\n  /* Configure DMA user callbacks */\r\n  hsd->hdmatx->XferCpltCallback  = SD_DMA_TxCplt;\r\n  hsd->hdmatx->XferErrorCallback = SD_DMA_TxError;\r\n  \r\n  /* Enable the DMA Channel */\r\n  HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pWriteBuffer, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BlockSize * NumberOfBlocks)/4);\r\n\r\n  /* Enable SDMMC DMA transfer */\r\n  __HAL_SD_SDMMC_DMA_ENABLE(hsd);\r\n  \r\n  if (hsd->CardType == HIGH_CAPACITY_SD_CARD)\r\n  {\r\n    BlockSize = 512;\r\n    WriteAddr /= 512;\r\n  }\r\n\r\n  /* Set Block Size for Card */ \r\n  sdmmc_cmdinitstructure.Argument         = (uint32_t)BlockSize;\r\n  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;\r\n  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;\r\n  sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r\n\r\n  /* Check for error conditions */\r\n  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);\r\n\r\n  if (errorstate != SD_OK)\r\n  {\r\n    return errorstate;\r\n  }\r\n  \r\n  /* Check number of blocks command */\r\n  if(NumberOfBlocks <= 1)\r\n  {\r\n    /* Send CMD24 WRITE_SINGLE_BLOCK */\r\n    sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;\r\n  }\r\n  else\r\n  {\r\n    /* Send CMD25 WRITE_MULT_BLOCK with argument data address */\r\n    sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK;\r\n  }\r\n  \r\n  sdmmc_cmdinitstructure.Argument         = (uint32_t)WriteAddr;\r\n  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r\n\r\n  /* Check for error conditions */\r\n  if(NumberOfBlocks > 1)\r\n  {\r\n    errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK);\r\n  }\r\n  else\r\n  {\r\n    errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK);\r\n  }\r\n  \r\n  if (errorstate != SD_OK)\r\n  {\r\n    return errorstate;\r\n  }\r\n  \r\n  /* Configure the SD DPSM (Data Path State Machine) */ \r\n  sdmmc_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;\r\n  sdmmc_datainitstructure.DataLength    = BlockSize * NumberOfBlocks;\r\n  sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;\r\n  sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_CARD;\r\n  sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;\r\n  sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;\r\n  SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);\r\n  \r\n  hsd->SdTransferErr = errorstate;\r\n  \r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  This function waits until the SD DMA data read transfer is finished. \r\n  *         This API should be called after HAL_SD_ReadBlocks_DMA() function\r\n  *         to insure that all data sent by the card is already transferred by the \r\n  *         DMA controller.\r\n  * @param  hsd: SD handle\r\n  * @param  Timeout: Timeout duration  \r\n  * @retval SD Card error state\r\n  */\r\nHAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout)\r\n{\r\n  HAL_SD_ErrorTypedef errorstate = SD_OK;\r\n  uint32_t timeout = Timeout;\r\n  uint32_t tmp1, tmp2;\r\n  HAL_SD_ErrorTypedef tmp3;\r\n  \r\n  /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */\r\n  tmp1 = hsd->DmaTransferCplt; \r\n  tmp2 = hsd->SdTransferCplt;\r\n  tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;\r\n    \r\n  while (((tmp1 & tmp2) == 0) && (tmp3 == SD_OK) && (timeout > 0))\r\n  {\r\n    tmp1 = hsd->DmaTransferCplt; \r\n    tmp2 = hsd->SdTransferCplt;\r\n    tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;    \r\n    timeout--;\r\n  }\r\n\r\n  timeout = Timeout;\r\n  \r\n  /* Wait until the Rx transfer is no longer active */\r\n  while((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXACT)) && (timeout > 0))\r\n  {\r\n    timeout--;  \r\n  }\r\n  \r\n  /* Send stop command in multiblock read */\r\n  if (hsd->SdOperation == SD_READ_MULTIPLE_BLOCK)\r\n  {\r\n    errorstate = HAL_SD_StopTransfer(hsd);\r\n  }\r\n  \r\n  if ((timeout == 0) && (errorstate == SD_OK))\r\n  {\r\n    errorstate = SD_DATA_TIMEOUT;\r\n  }\r\n  \r\n  /* Clear all the static flags */\r\n  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r\n  \r\n  /* Return error state */\r\n  if (hsd->SdTransferErr != SD_OK)\r\n  {\r\n    return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr);\r\n  }\r\n  \r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  This function waits until the SD DMA data write transfer is finished. \r\n  *         This API should be called after HAL_SD_WriteBlocks_DMA() function\r\n  *         to insure that all data sent by the card is already transferred by the \r\n  *         DMA controller.\r\n  * @param  hsd: SD handle\r\n  * @param  Timeout: Timeout duration  \r\n  * @retval SD Card error state\r\n  */\r\nHAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout)\r\n{\r\n  HAL_SD_ErrorTypedef errorstate = SD_OK;\r\n  uint32_t timeout = Timeout;\r\n  uint32_t tmp1, tmp2;\r\n  HAL_SD_ErrorTypedef tmp3;\r\n\r\n  /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */\r\n  tmp1 = hsd->DmaTransferCplt; \r\n  tmp2 = hsd->SdTransferCplt;\r\n  tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;\r\n    \r\n  while (((tmp1 & tmp2) == 0) && (tmp3 == SD_OK) && (timeout > 0))\r\n  {\r\n    tmp1 = hsd->DmaTransferCplt; \r\n    tmp2 = hsd->SdTransferCplt;\r\n    tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;\r\n    timeout--;\r\n  }\r\n  \r\n  timeout = Timeout;\r\n  \r\n  /* Wait until the Tx transfer is no longer active */\r\n  while((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_TXACT))  && (timeout > 0))\r\n  {\r\n    timeout--;  \r\n  }\r\n\r\n  /* Send stop command in multiblock write */\r\n  if (hsd->SdOperation == SD_WRITE_MULTIPLE_BLOCK)\r\n  {\r\n    errorstate = HAL_SD_StopTransfer(hsd);\r\n  }\r\n  \r\n  if ((timeout == 0) && (errorstate == SD_OK))\r\n  {\r\n    errorstate = SD_DATA_TIMEOUT;\r\n  }\r\n  \r\n  /* Clear all the static flags */\r\n  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r\n  \r\n  /* Return error state */\r\n  if (hsd->SdTransferErr != SD_OK)\r\n  {\r\n    return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr);\r\n  }\r\n  \r\n  /* Wait until write is complete */\r\n  while(HAL_SD_GetStatus(hsd) != SD_TRANSFER_OK)\r\n  {    \r\n  }\r\n\r\n  return errorstate; \r\n}\r\n\r\n/**\r\n  * @brief  Erases the specified memory area of the given SD card.\r\n  * @param  hsd: SD handle \r\n  * @param  startaddr: Start byte address\r\n  * @param  endaddr: End byte address\r\n  * @retval SD Card error state\r\n  */\r\nHAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr)\r\n{\r\n  HAL_SD_ErrorTypedef errorstate = SD_OK;\r\n  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r\n  \r\n  uint32_t delay         = 0;\r\n  __IO uint32_t maxdelay = 0;\r\n  uint8_t cardstate      = 0;\r\n  \r\n  /* Check if the card command class supports erase command */\r\n  if (((hsd->CSD[1] >> 20) & SD_CCCC_ERASE) == 0)\r\n  {\r\n    errorstate = SD_REQUEST_NOT_APPLICABLE;\r\n    \r\n    return errorstate;\r\n  }\r\n  \r\n  /* Get max delay value */\r\n  maxdelay = 120000 / (((hsd->Instance->CLKCR) & 0xFF) + 2);\r\n  \r\n  if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)\r\n  {\r\n    errorstate = SD_LOCK_UNLOCK_FAILED;\r\n    \r\n    return errorstate;\r\n  }\r\n  \r\n  /* Get start and end block for high capacity cards */\r\n  if (hsd->CardType == HIGH_CAPACITY_SD_CARD)\r\n  {\r\n    startaddr /= 512;\r\n    endaddr   /= 512;\r\n  }\r\n  \r\n  /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */\r\n  if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\\\r\n    (hsd->CardType == HIGH_CAPACITY_SD_CARD))\r\n  {\r\n    /* Send CMD32 SD_ERASE_GRP_START with argument as addr  */\r\n    sdmmc_cmdinitstructure.Argument         =(uint32_t)startaddr;\r\n    sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SD_ERASE_GRP_START;\r\n    sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;\r\n    sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r\n    sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;\r\n    SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r\n    \r\n    /* Check for error conditions */\r\n    errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_START);\r\n    \r\n    if (errorstate != SD_OK)\r\n    {\r\n      return errorstate;\r\n    }\r\n    \r\n    /* Send CMD33 SD_ERASE_GRP_END with argument as addr  */\r\n    sdmmc_cmdinitstructure.Argument         = (uint32_t)endaddr;\r\n    sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SD_ERASE_GRP_END;\r\n    SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r\n    \r\n    /* Check for error conditions */\r\n    errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_END);\r\n    \r\n    if (errorstate != SD_OK)\r\n    {\r\n      return errorstate;\r\n    }\r\n  }\r\n  \r\n  /* Send CMD38 ERASE */\r\n  sdmmc_cmdinitstructure.Argument         = 0;\r\n  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_ERASE;\r\n  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SD_CmdResp1Error(hsd, SD_CMD_ERASE);\r\n  \r\n  if (errorstate != SD_OK)\r\n  {\r\n    return errorstate;\r\n  }\r\n  \r\n  for (; delay < maxdelay; delay++)\r\n  {\r\n  }\r\n  \r\n  /* Wait until the card is in programming state */\r\n  errorstate = SD_IsCardProgramming(hsd, &cardstate);\r\n  \r\n  delay = SD_DATATIMEOUT;\r\n  \r\n  while ((delay > 0) && (errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING)))\r\n  {\r\n    errorstate = SD_IsCardProgramming(hsd, &cardstate);\r\n    delay--;\r\n  }\r\n  \r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  This function handles SD card interrupt request.\r\n  * @param  hsd: SD handle\r\n  * @retval None\r\n  */\r\nvoid HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)\r\n{  \r\n  /* Check for SDMMC interrupt flags */\r\n  if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_DATAEND))\r\n  {\r\n    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_IT_DATAEND);  \r\n      \r\n    /* SD transfer is complete */\r\n    hsd->SdTransferCplt = 1;\r\n\r\n    /* No transfer error */ \r\n    hsd->SdTransferErr  = SD_OK;\r\n\r\n    HAL_SD_XferCpltCallback(hsd);  \r\n  }  \r\n  else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL))\r\n  {\r\n    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);\r\n    \r\n    hsd->SdTransferErr = SD_DATA_CRC_FAIL;\r\n    \r\n    HAL_SD_XferErrorCallback(hsd);\r\n    \r\n  }\r\n  else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_DTIMEOUT))\r\n  {\r\n    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);\r\n    \r\n    hsd->SdTransferErr = SD_DATA_TIMEOUT;\r\n    \r\n    HAL_SD_XferErrorCallback(hsd);\r\n  }\r\n  else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_RXOVERR))\r\n  {\r\n    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);\r\n    \r\n    hsd->SdTransferErr = SD_RX_OVERRUN;\r\n    \r\n    HAL_SD_XferErrorCallback(hsd);\r\n  }\r\n  else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_IT_TXUNDERR))\r\n  {\r\n    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_TXUNDERR);\r\n    \r\n    hsd->SdTransferErr = SD_TX_UNDERRUN;\r\n    \r\n    HAL_SD_XferErrorCallback(hsd);\r\n  }\r\n  else\r\n  {\r\n    /* No error flag set */\r\n  }  \r\n\r\n  /* Disable all SDMMC peripheral interrupt sources */\r\n  __HAL_SD_SDMMC_DISABLE_IT(hsd, SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_DATAEND  |\\\r\n                                 SDMMC_IT_TXFIFOHE | SDMMC_IT_RXFIFOHF | SDMMC_IT_TXUNDERR |\\\r\n                                 SDMMC_IT_RXOVERR);                               \r\n}\r\n\r\n\r\n/**\r\n  * @brief  SD end of transfer callback.\r\n  * @param  hsd: SD handle \r\n  * @retval None\r\n  */\r\n__weak void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hsd);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_SD_XferCpltCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  SD Transfer Error callback.\r\n  * @param  hsd: SD handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hsd);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_SD_XferErrorCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  SD Transfer complete Rx callback in non blocking mode.\r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdma);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_SD_DMA_RxCpltCallback could be implemented in the user file\r\n   */ \r\n}  \r\n\r\n/**\r\n  * @brief  SD DMA transfer complete Rx error callback.\r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdma);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_SD_DMA_RxErrorCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  SD Transfer complete Tx callback in non blocking mode.\r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdma);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_SD_DMA_TxCpltCallback could be implemented in the user file\r\n   */ \r\n}  \r\n\r\n/**\r\n  * @brief  SD DMA transfer complete error Tx callback.\r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdma);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_SD_DMA_TxErrorCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup SD_Exported_Functions_Group3\r\n *  @brief   management functions \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                      ##### Peripheral Control functions #####\r\n  ==============================================================================  \r\n  [..]\r\n    This subsection provides a set of functions allowing to control the SD card \r\n    operations.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Returns information about specific card.\r\n  * @param  hsd: SD handle\r\n  * @param  pCardInfo: Pointer to a HAL_SD_CardInfoTypedef structure that  \r\n  *         contains all SD cardinformation  \r\n  * @retval SD Card error state\r\n  */\r\nHAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo)\r\n{\r\n  HAL_SD_ErrorTypedef errorstate = SD_OK;\r\n  uint32_t tmp = 0;\r\n  \r\n  pCardInfo->CardType = (uint8_t)(hsd->CardType);\r\n  pCardInfo->RCA      = (uint16_t)(hsd->RCA);\r\n  \r\n  /* Byte 0 */\r\n  tmp = (hsd->CSD[0] & 0xFF000000U) >> 24;\r\n  pCardInfo->SD_csd.CSDStruct      = (uint8_t)((tmp & 0xC0) >> 6);\r\n  pCardInfo->SD_csd.SysSpecVersion = (uint8_t)((tmp & 0x3C) >> 2);\r\n  pCardInfo->SD_csd.Reserved1      = tmp & 0x03;\r\n  \r\n  /* Byte 1 */\r\n  tmp = (hsd->CSD[0] & 0x00FF0000) >> 16;\r\n  pCardInfo->SD_csd.TAAC = (uint8_t)tmp;\r\n  \r\n  /* Byte 2 */\r\n  tmp = (hsd->CSD[0] & 0x0000FF00) >> 8;\r\n  pCardInfo->SD_csd.NSAC = (uint8_t)tmp;\r\n  \r\n  /* Byte 3 */\r\n  tmp = hsd->CSD[0] & 0x000000FF;\r\n  pCardInfo->SD_csd.MaxBusClkFrec = (uint8_t)tmp;\r\n  \r\n  /* Byte 4 */\r\n  tmp = (hsd->CSD[1] & 0xFF000000U) >> 24;\r\n  pCardInfo->SD_csd.CardComdClasses = (uint16_t)(tmp << 4);\r\n  \r\n  /* Byte 5 */\r\n  tmp = (hsd->CSD[1] & 0x00FF0000U) >> 16;\r\n  pCardInfo->SD_csd.CardComdClasses |= (uint16_t)((tmp & 0xF0) >> 4);\r\n  pCardInfo->SD_csd.RdBlockLen       = (uint8_t)(tmp & 0x0F);\r\n  \r\n  /* Byte 6 */\r\n  tmp = (hsd->CSD[1] & 0x0000FF00U) >> 8;\r\n  pCardInfo->SD_csd.PartBlockRead   = (uint8_t)((tmp & 0x80) >> 7);\r\n  pCardInfo->SD_csd.WrBlockMisalign = (uint8_t)((tmp & 0x40) >> 6);\r\n  pCardInfo->SD_csd.RdBlockMisalign = (uint8_t)((tmp & 0x20) >> 5);\r\n  pCardInfo->SD_csd.DSRImpl         = (uint8_t)((tmp & 0x10) >> 4);\r\n  pCardInfo->SD_csd.Reserved2       = 0; /*!< Reserved */\r\n  \r\n  if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0))\r\n  {\r\n    pCardInfo->SD_csd.DeviceSize = (tmp & 0x03) << 10;\r\n    \r\n    /* Byte 7 */\r\n    tmp = (uint8_t)(hsd->CSD[1] & 0x000000FFU);\r\n    pCardInfo->SD_csd.DeviceSize |= (tmp) << 2;\r\n    \r\n    /* Byte 8 */\r\n    tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000U) >> 24);\r\n    pCardInfo->SD_csd.DeviceSize |= (tmp & 0xC0) >> 6;\r\n    \r\n    pCardInfo->SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38) >> 3;\r\n    pCardInfo->SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07);\r\n    \r\n    /* Byte 9 */\r\n    tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000U) >> 16);\r\n    pCardInfo->SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5;\r\n    pCardInfo->SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2;\r\n    pCardInfo->SD_csd.DeviceSizeMul      = (tmp & 0x03) << 1;\r\n    /* Byte 10 */\r\n    tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00U) >> 8);\r\n    pCardInfo->SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7;\r\n    \r\n    pCardInfo->CardCapacity  = (pCardInfo->SD_csd.DeviceSize + 1) ;\r\n    pCardInfo->CardCapacity *= (1 << (pCardInfo->SD_csd.DeviceSizeMul + 2));\r\n    pCardInfo->CardBlockSize = 1 << (pCardInfo->SD_csd.RdBlockLen);\r\n    pCardInfo->CardCapacity *= pCardInfo->CardBlockSize;\r\n  }\r\n  else if (hsd->CardType == HIGH_CAPACITY_SD_CARD)\r\n  {\r\n    /* Byte 7 */\r\n    tmp = (uint8_t)(hsd->CSD[1] & 0x000000FFU);\r\n    pCardInfo->SD_csd.DeviceSize = (tmp & 0x3F) << 16;\r\n    \r\n    /* Byte 8 */\r\n    tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000U) >> 24);\r\n    \r\n    pCardInfo->SD_csd.DeviceSize |= (tmp << 8);\r\n    \r\n    /* Byte 9 */\r\n    tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000U) >> 16);\r\n    \r\n    pCardInfo->SD_csd.DeviceSize |= (tmp);\r\n    \r\n    /* Byte 10 */\r\n    tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00U) >> 8);\r\n    \r\n    pCardInfo->CardCapacity = (uint64_t)(((uint64_t)pCardInfo->SD_csd.DeviceSize + 1) * 512 * 1024);\r\n    pCardInfo->CardBlockSize = 512;\r\n  }\r\n  else\r\n  {\r\n    /* Not supported card type */\r\n    errorstate = SD_ERROR;\r\n  }\r\n      \r\n  pCardInfo->SD_csd.EraseGrSize = (tmp & 0x40) >> 6;\r\n  pCardInfo->SD_csd.EraseGrMul  = (tmp & 0x3F) << 1;\r\n  \r\n  /* Byte 11 */\r\n  tmp = (uint8_t)(hsd->CSD[2] & 0x000000FF);\r\n  pCardInfo->SD_csd.EraseGrMul     |= (tmp & 0x80) >> 7;\r\n  pCardInfo->SD_csd.WrProtectGrSize = (tmp & 0x7F);\r\n  \r\n  /* Byte 12 */\r\n  tmp = (uint8_t)((hsd->CSD[3] & 0xFF000000U) >> 24);\r\n  pCardInfo->SD_csd.WrProtectGrEnable = (tmp & 0x80) >> 7;\r\n  pCardInfo->SD_csd.ManDeflECC        = (tmp & 0x60) >> 5;\r\n  pCardInfo->SD_csd.WrSpeedFact       = (tmp & 0x1C) >> 2;\r\n  pCardInfo->SD_csd.MaxWrBlockLen     = (tmp & 0x03) << 2;\r\n  \r\n  /* Byte 13 */\r\n  tmp = (uint8_t)((hsd->CSD[3] & 0x00FF0000) >> 16);\r\n  pCardInfo->SD_csd.MaxWrBlockLen      |= (tmp & 0xC0) >> 6;\r\n  pCardInfo->SD_csd.WriteBlockPaPartial = (tmp & 0x20) >> 5;\r\n  pCardInfo->SD_csd.Reserved3           = 0;\r\n  pCardInfo->SD_csd.ContentProtectAppli = (tmp & 0x01);\r\n  \r\n  /* Byte 14 */\r\n  tmp = (uint8_t)((hsd->CSD[3] & 0x0000FF00) >> 8);\r\n  pCardInfo->SD_csd.FileFormatGrouop = (tmp & 0x80) >> 7;\r\n  pCardInfo->SD_csd.CopyFlag         = (tmp & 0x40) >> 6;\r\n  pCardInfo->SD_csd.PermWrProtect    = (tmp & 0x20) >> 5;\r\n  pCardInfo->SD_csd.TempWrProtect    = (tmp & 0x10) >> 4;\r\n  pCardInfo->SD_csd.FileFormat       = (tmp & 0x0C) >> 2;\r\n  pCardInfo->SD_csd.ECC              = (tmp & 0x03);\r\n  \r\n  /* Byte 15 */\r\n  tmp = (uint8_t)(hsd->CSD[3] & 0x000000FF);\r\n  pCardInfo->SD_csd.CSD_CRC   = (tmp & 0xFE) >> 1;\r\n  pCardInfo->SD_csd.Reserved4 = 1;\r\n  \r\n  /* Byte 0 */\r\n  tmp = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24);\r\n  pCardInfo->SD_cid.ManufacturerID = tmp;\r\n  \r\n  /* Byte 1 */\r\n  tmp = (uint8_t)((hsd->CID[0] & 0x00FF0000) >> 16);\r\n  pCardInfo->SD_cid.OEM_AppliID = tmp << 8;\r\n  \r\n  /* Byte 2 */\r\n  tmp = (uint8_t)((hsd->CID[0] & 0x000000FF00) >> 8);\r\n  pCardInfo->SD_cid.OEM_AppliID |= tmp;\r\n  \r\n  /* Byte 3 */\r\n  tmp = (uint8_t)(hsd->CID[0] & 0x000000FF);\r\n  pCardInfo->SD_cid.ProdName1 = tmp << 24;\r\n  \r\n  /* Byte 4 */\r\n  tmp = (uint8_t)((hsd->CID[1] & 0xFF000000U) >> 24);\r\n  pCardInfo->SD_cid.ProdName1 |= tmp << 16;\r\n  \r\n  /* Byte 5 */\r\n  tmp = (uint8_t)((hsd->CID[1] & 0x00FF0000) >> 16);\r\n  pCardInfo->SD_cid.ProdName1 |= tmp << 8;\r\n  \r\n  /* Byte 6 */\r\n  tmp = (uint8_t)((hsd->CID[1] & 0x0000FF00) >> 8);\r\n  pCardInfo->SD_cid.ProdName1 |= tmp;\r\n  \r\n  /* Byte 7 */\r\n  tmp = (uint8_t)(hsd->CID[1] & 0x000000FF);\r\n  pCardInfo->SD_cid.ProdName2 = tmp;\r\n  \r\n  /* Byte 8 */\r\n  tmp = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24);\r\n  pCardInfo->SD_cid.ProdRev = tmp;\r\n  \r\n  /* Byte 9 */\r\n  tmp = (uint8_t)((hsd->CID[2] & 0x00FF0000) >> 16);\r\n  pCardInfo->SD_cid.ProdSN = tmp << 24;\r\n  \r\n  /* Byte 10 */\r\n  tmp = (uint8_t)((hsd->CID[2] & 0x0000FF00) >> 8);\r\n  pCardInfo->SD_cid.ProdSN |= tmp << 16;\r\n  \r\n  /* Byte 11 */\r\n  tmp = (uint8_t)(hsd->CID[2] & 0x000000FF);\r\n  pCardInfo->SD_cid.ProdSN |= tmp << 8;\r\n  \r\n  /* Byte 12 */\r\n  tmp = (uint8_t)((hsd->CID[3] & 0xFF000000U) >> 24);\r\n  pCardInfo->SD_cid.ProdSN |= tmp;\r\n  \r\n  /* Byte 13 */\r\n  tmp = (uint8_t)((hsd->CID[3] & 0x00FF0000) >> 16);\r\n  pCardInfo->SD_cid.Reserved1   |= (tmp & 0xF0) >> 4;\r\n  pCardInfo->SD_cid.ManufactDate = (tmp & 0x0F) << 8;\r\n  \r\n  /* Byte 14 */\r\n  tmp = (uint8_t)((hsd->CID[3] & 0x0000FF00) >> 8);\r\n  pCardInfo->SD_cid.ManufactDate |= tmp;\r\n  \r\n  /* Byte 15 */\r\n  tmp = (uint8_t)(hsd->CID[3] & 0x000000FF);\r\n  pCardInfo->SD_cid.CID_CRC   = (tmp & 0xFE) >> 1;\r\n  pCardInfo->SD_cid.Reserved2 = 1;\r\n  \r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Enables wide bus operation for the requested card if supported by \r\n  *         card.\r\n  * @param  hsd: SD handle       \r\n  * @param  WideMode: Specifies the SD card wide bus mode \r\n  *          This parameter can be one of the following values:\r\n  *            @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer (Only for MMC)\r\n  *            @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer\r\n  *            @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer\r\n  * @retval SD Card error state\r\n  */\r\nHAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode)\r\n{\r\n  HAL_SD_ErrorTypedef errorstate = SD_OK;\r\n  SDMMC_InitTypeDef tmpinit;\r\n  \r\n  /* MMC Card does not support this feature */\r\n  if (hsd->CardType == MULTIMEDIA_CARD)\r\n  {\r\n    errorstate = SD_UNSUPPORTED_FEATURE;\r\n    \r\n    return errorstate;\r\n  }\r\n  else if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\\\r\n    (hsd->CardType == HIGH_CAPACITY_SD_CARD))\r\n  {\r\n    if (WideMode == SDMMC_BUS_WIDE_8B)\r\n    {\r\n      errorstate = SD_UNSUPPORTED_FEATURE;\r\n    }\r\n    else if (WideMode == SDMMC_BUS_WIDE_4B)\r\n    {\r\n      errorstate = SD_WideBus_Enable(hsd);\r\n    }\r\n    else if (WideMode == SDMMC_BUS_WIDE_1B)\r\n    {\r\n      errorstate = SD_WideBus_Disable(hsd);\r\n    }\r\n    else\r\n    {\r\n      /* WideMode is not a valid argument*/\r\n      errorstate = SD_INVALID_PARAMETER;\r\n    }\r\n      \r\n    if (errorstate == SD_OK)\r\n    {\r\n      /* Configure the SDMMC peripheral */\r\n      tmpinit.ClockEdge           = hsd->Init.ClockEdge;\r\n      tmpinit.ClockBypass         = hsd->Init.ClockBypass;\r\n      tmpinit.ClockPowerSave      = hsd->Init.ClockPowerSave;\r\n      tmpinit.BusWide             = WideMode;\r\n      tmpinit.HardwareFlowControl = hsd->Init.HardwareFlowControl;\r\n      tmpinit.ClockDiv            = hsd->Init.ClockDiv;\r\n      SDMMC_Init(hsd->Instance, tmpinit);\r\n    }\r\n  }\r\n  \r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Aborts an ongoing data transfer.\r\n  * @param  hsd: SD handle\r\n  * @retval SD Card error state\r\n  */\r\nHAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd)\r\n{\r\n  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r\n  HAL_SD_ErrorTypedef errorstate = SD_OK;\r\n  \r\n  /* Send CMD12 STOP_TRANSMISSION  */\r\n  sdmmc_cmdinitstructure.Argument         = 0;\r\n  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_STOP_TRANSMISSION;\r\n  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;\r\n  sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SD_CmdResp1Error(hsd, SD_CMD_STOP_TRANSMISSION);\r\n  \r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Switches the SD card to High Speed mode.\r\n  *         This API must be used after \"Transfer State\"\r\n  * @note   This operation should be followed by the configuration \r\n  *         of PLL to have SDMMCCK clock between 67 and 75 MHz\r\n  * @param  hsd: SD handle\r\n  * @retval SD Card error state\r\n  */\r\nHAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd)\r\n{\r\n  HAL_SD_ErrorTypedef errorstate = SD_OK;\r\n  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r\n  SDMMC_DataInitTypeDef sdmmc_datainitstructure;\r\n  \r\n  uint8_t SD_hs[64]  = {0};\r\n  uint32_t SD_scr[2] = {0, 0};\r\n  uint32_t SD_SPEC   = 0 ;\r\n  uint32_t count = 0, *tempbuff = (uint32_t *)SD_hs;\r\n  \r\n  /* Initialize the Data control register */\r\n  hsd->Instance->DCTRL = 0;\r\n  \r\n  /* Get SCR Register */\r\n  errorstate = SD_FindSCR(hsd, SD_scr);\r\n  \r\n  if (errorstate != SD_OK)\r\n  {\r\n    return errorstate;\r\n  }\r\n  \r\n  /* Test the Version supported by the card*/ \r\n  SD_SPEC = (SD_scr[1]  & 0x01000000) | (SD_scr[1]  & 0x02000000);\r\n  \r\n  if (SD_SPEC != SD_ALLZERO)\r\n  {\r\n    /* Set Block Size for Card */\r\n    sdmmc_cmdinitstructure.Argument         = (uint32_t)64;\r\n    sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;\r\n    sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;\r\n    sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r\n    sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;\r\n    SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r\n    \r\n    /* Check for error conditions */\r\n    errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);\r\n    \r\n    if (errorstate != SD_OK)\r\n    {\r\n      return errorstate;\r\n    }\r\n    \r\n    /* Configure the SD DPSM (Data Path State Machine) */\r\n    sdmmc_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;\r\n    sdmmc_datainitstructure.DataLength    = 64;\r\n    sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ;\r\n    sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;\r\n    sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;\r\n    sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;\r\n    SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);\r\n    \r\n    /* Send CMD6 switch mode */\r\n    sdmmc_cmdinitstructure.Argument         = 0x80FFFF01U;\r\n    sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_HS_SWITCH;\r\n    SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure); \r\n    \r\n    /* Check for error conditions */\r\n    errorstate = SD_CmdResp1Error(hsd, SD_CMD_HS_SWITCH);\r\n    \r\n    if (errorstate != SD_OK)\r\n    {\r\n      return errorstate;\r\n    }\r\n        \r\n    while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))\r\n    {\r\n      if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))\r\n      {\r\n        for (count = 0; count < 8; count++)\r\n        {\r\n          *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance);\r\n        }\r\n        \r\n        tempbuff += 8;\r\n      }\r\n    }\r\n    \r\n    if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))\r\n    {\r\n      __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);\r\n      \r\n      errorstate = SD_DATA_TIMEOUT;\r\n      \r\n      return errorstate;\r\n    }\r\n    else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))\r\n    {\r\n      __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);\r\n      \r\n      errorstate = SD_DATA_CRC_FAIL;\r\n      \r\n      return errorstate;\r\n    }\r\n    else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))\r\n    {\r\n      __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);\r\n      \r\n      errorstate = SD_RX_OVERRUN;\r\n      \r\n      return errorstate;\r\n    }\r\n    else\r\n    {\r\n      /* No error flag set */\r\n    }\r\n        \r\n    count = SD_DATATIMEOUT;\r\n    \r\n    while ((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) && (count > 0))\r\n    {\r\n      *tempbuff = SDMMC_ReadFIFO(hsd->Instance);\r\n      tempbuff++;\r\n      count--;\r\n    }\r\n    \r\n    /* Clear all the static flags */\r\n    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r\n    \r\n    /* Test if the switch mode HS is ok */\r\n    if ((SD_hs[13]& 2) != 2)\r\n    {\r\n      errorstate = SD_UNSUPPORTED_FEATURE;\r\n    } \r\n  }\r\n  \r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup SD_Exported_Functions_Group4\r\n *  @brief   Peripheral State functions \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                      ##### Peripheral State functions #####\r\n  ==============================================================================  \r\n  [..]\r\n    This subsection permits to get in runtime the status of the peripheral \r\n    and the data flow.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Returns the current SD card's status.\r\n  * @param  hsd: SD handle\r\n  * @param  pSDstatus: Pointer to the buffer that will contain the SD card status \r\n  *         SD Status register)\r\n  * @retval SD Card error state\r\n  */\r\nHAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)\r\n{\r\n  SDMMC_CmdInitTypeDef  sdmmc_cmdinitstructure;\r\n  SDMMC_DataInitTypeDef sdmmc_datainitstructure;\r\n  HAL_SD_ErrorTypedef errorstate = SD_OK;\r\n  uint32_t count = 0;\r\n  \r\n  /* Check SD response */\r\n  if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)\r\n  {\r\n    errorstate = SD_LOCK_UNLOCK_FAILED;\r\n    \r\n    return errorstate;\r\n  }\r\n  \r\n  /* Set block size for card if it is not equal to current block size for card */\r\n  sdmmc_cmdinitstructure.Argument         = 64;\r\n  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;\r\n  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;\r\n  sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);\r\n  \r\n  if (errorstate != SD_OK)\r\n  {\r\n    return errorstate;\r\n  }\r\n  \r\n  /* Send CMD55 */\r\n  sdmmc_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);\r\n  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;\r\n  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);\r\n  \r\n  if (errorstate != SD_OK)\r\n  {\r\n    return errorstate;\r\n  }\r\n  \r\n  /* Configure the SD DPSM (Data Path State Machine) */ \r\n  sdmmc_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;\r\n  sdmmc_datainitstructure.DataLength    = 64;\r\n  sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B;\r\n  sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;\r\n  sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;\r\n  sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;\r\n  SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);\r\n  \r\n  /* Send ACMD13 (SD_APP_STAUS)  with argument as card's RCA */\r\n  sdmmc_cmdinitstructure.Argument         = 0;\r\n  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SD_APP_STATUS;\r\n  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_STATUS);\r\n  \r\n  if (errorstate != SD_OK)\r\n  {\r\n    return errorstate;\r\n  }\r\n  \r\n  /* Get status data */\r\n  while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))\r\n  {\r\n    if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))\r\n    {\r\n      for (count = 0; count < 8; count++)\r\n      {\r\n        *(pSDstatus + count) = SDMMC_ReadFIFO(hsd->Instance);\r\n      }\r\n      \r\n      pSDstatus += 8;\r\n    }\r\n  }\r\n  \r\n  if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))\r\n  {\r\n    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);\r\n    \r\n    errorstate = SD_DATA_TIMEOUT;\r\n    \r\n    return errorstate;\r\n  }\r\n  else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))\r\n  {\r\n    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);\r\n    \r\n    errorstate = SD_DATA_CRC_FAIL;\r\n    \r\n    return errorstate;\r\n  }\r\n  else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))\r\n  {\r\n    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);\r\n    \r\n    errorstate = SD_RX_OVERRUN;\r\n    \r\n    return errorstate;\r\n  }\r\n  else\r\n  {\r\n    /* No error flag set */\r\n  }  \r\n  \r\n  count = SD_DATATIMEOUT;\r\n  while ((__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) && (count > 0))\r\n  {\r\n    *pSDstatus = SDMMC_ReadFIFO(hsd->Instance);\r\n    pSDstatus++;\r\n    count--;\r\n  }\r\n  \r\n  /* Clear all the static status flags*/\r\n  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r\n  \r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Gets the current sd card data status.\r\n  * @param  hsd: SD handle\r\n  * @retval Data Transfer state\r\n  */\r\nHAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd)\r\n{\r\n  HAL_SD_CardStateTypedef cardstate =  SD_CARD_TRANSFER;\r\n\r\n  /* Get SD card state */\r\n  cardstate = SD_GetState(hsd);\r\n  \r\n  /* Find SD status according to card state*/\r\n  if (cardstate == SD_CARD_TRANSFER)\r\n  {\r\n    return SD_TRANSFER_OK;\r\n  }\r\n  else if(cardstate == SD_CARD_ERROR)\r\n  {\r\n    return SD_TRANSFER_ERROR;\r\n  }\r\n  else\r\n  {\r\n    return SD_TRANSFER_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Gets the SD card status.\r\n  * @param  hsd: SD handle      \r\n  * @param  pCardStatus: Pointer to the HAL_SD_CardStatusTypedef structure that \r\n  *         will contain the SD card status information \r\n  * @retval SD Card error state\r\n  */\r\nHAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus)\r\n{\r\n  HAL_SD_ErrorTypedef errorstate = SD_OK;\r\n  uint32_t tmp = 0;\r\n  uint32_t sd_status[16];\r\n  \r\n  errorstate = HAL_SD_SendSDStatus(hsd, sd_status);\r\n  \r\n  if (errorstate  != SD_OK)\r\n  {\r\n    return errorstate;\r\n  }\r\n  \r\n  /* Byte 0 */\r\n  tmp = (sd_status[0] & 0xC0) >> 6;\r\n  pCardStatus->DAT_BUS_WIDTH = (uint8_t)tmp;\r\n  \r\n  /* Byte 0 */\r\n  tmp = (sd_status[0] & 0x20) >> 5;\r\n  pCardStatus->SECURED_MODE = (uint8_t)tmp;\r\n  \r\n  /* Byte 2 */\r\n  tmp = (sd_status[0] & 0x00FF0000) >> 16;\r\n  pCardStatus->SD_CARD_TYPE = (uint16_t)(tmp << 8);\r\n  \r\n  /* Byte 3 */\r\n  tmp = (sd_status[0] & 0xFF000000) >> 24;\r\n  pCardStatus->SD_CARD_TYPE |= (uint16_t)tmp;\r\n  \r\n  /* Byte 4 */\r\n  tmp = (sd_status[1] & 0xFF);\r\n  pCardStatus->SIZE_OF_PROTECTED_AREA = (uint32_t)(tmp << 24);\r\n  \r\n  /* Byte 5 */\r\n  tmp = (sd_status[1] & 0xFF00) >> 8;\r\n  pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint32_t)(tmp << 16);\r\n  \r\n  /* Byte 6 */\r\n  tmp = (sd_status[1] & 0xFF0000) >> 16;\r\n  pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint32_t)(tmp << 8);\r\n  \r\n  /* Byte 7 */\r\n  tmp = (sd_status[1] & 0xFF000000) >> 24;\r\n  pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint32_t)tmp;\r\n  \r\n  /* Byte 8 */\r\n  tmp = (sd_status[2] & 0xFF);\r\n  pCardStatus->SPEED_CLASS = (uint8_t)tmp;\r\n  \r\n  /* Byte 9 */\r\n  tmp = (sd_status[2] & 0xFF00) >> 8;\r\n  pCardStatus->PERFORMANCE_MOVE = (uint8_t)tmp;\r\n  \r\n  /* Byte 10 */\r\n  tmp = (sd_status[2] & 0xF00000) >> 20;\r\n  pCardStatus->AU_SIZE = (uint8_t)tmp;\r\n  \r\n  /* Byte 11 */\r\n  tmp = (sd_status[2] & 0xFF000000) >> 24;\r\n  pCardStatus->ERASE_SIZE = (uint16_t)(tmp << 8);\r\n  \r\n  /* Byte 12 */\r\n  tmp = (sd_status[3] & 0xFF);\r\n  pCardStatus->ERASE_SIZE |= (uint16_t)tmp;\r\n  \r\n  /* Byte 13 */\r\n  tmp = (sd_status[3] & 0xFC00) >> 10;\r\n  pCardStatus->ERASE_TIMEOUT = (uint8_t)tmp;\r\n  \r\n  /* Byte 13 */\r\n  tmp = (sd_status[3] & 0x0300) >> 8;\r\n  pCardStatus->ERASE_OFFSET = (uint8_t)tmp;\r\n  \r\n  return errorstate;\r\n}\r\n         \r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Private function ----------------------------------------------------------*/  \r\n/** @addtogroup SD_Private_Functions\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @brief  SD DMA transfer complete Rx callback.\r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n  \r\n  /* DMA transfer is complete */\r\n  hsd->DmaTransferCplt = 1;\r\n  \r\n  /* Wait until SD transfer is complete */\r\n  while(hsd->SdTransferCplt == 0)\r\n  {\r\n  }\r\n  \r\n  /* Disable the DMA channel */\r\n  HAL_DMA_Abort(hdma);\r\n\r\n  /* Transfer complete user callback */\r\n  HAL_SD_DMA_RxCpltCallback(hsd->hdmarx);   \r\n}\r\n\r\n/**\r\n  * @brief  SD DMA transfer Error Rx callback.\r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void SD_DMA_RxError(DMA_HandleTypeDef *hdma)\r\n{\r\n  SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n  \r\n  /* Transfer complete user callback */\r\n  HAL_SD_DMA_RxErrorCallback(hsd->hdmarx);\r\n}\r\n\r\n/**\r\n  * @brief  SD DMA transfer complete Tx callback.\r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n  \r\n  /* DMA transfer is complete */\r\n  hsd->DmaTransferCplt = 1;\r\n  \r\n  /* Wait until SD transfer is complete */\r\n  while(hsd->SdTransferCplt == 0)\r\n  {\r\n  }\r\n \r\n  /* Disable the DMA channel */\r\n  HAL_DMA_Abort(hdma);\r\n\r\n  /* Transfer complete user callback */\r\n  HAL_SD_DMA_TxCpltCallback(hsd->hdmatx);  \r\n}\r\n\r\n/**\r\n  * @brief  SD DMA transfer Error Tx callback.\r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void SD_DMA_TxError(DMA_HandleTypeDef *hdma)\r\n{\r\n  SD_HandleTypeDef *hsd = ( SD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  \r\n  /* Transfer complete user callback */\r\n  HAL_SD_DMA_TxErrorCallback(hsd->hdmatx);\r\n}\r\n\r\n/**\r\n  * @brief  Returns the SD current state.\r\n  * @param  hsd: SD handle\r\n  * @retval SD card current state\r\n  */\r\nstatic HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd)\r\n{\r\n  uint32_t resp1 = 0;\r\n  \r\n  if (SD_SendStatus(hsd, &resp1) != SD_OK)\r\n  {\r\n    return SD_CARD_ERROR;\r\n  }\r\n  else\r\n  {\r\n    return (HAL_SD_CardStateTypedef)((resp1 >> 9) & 0x0F);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Initializes all cards or single card as the case may be Card(s) come \r\n  *         into standby state.\r\n  * @param  hsd: SD handle\r\n  * @retval SD Card error state\r\n  */\r\nstatic HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd)\r\n{\r\n  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; \r\n  HAL_SD_ErrorTypedef errorstate = SD_OK;\r\n  uint16_t sd_rca = 1;\r\n  \r\n  if(SDMMC_GetPowerState(hsd->Instance) == 0) /* Power off */\r\n  {\r\n    errorstate = SD_REQUEST_NOT_APPLICABLE;\r\n    \r\n    return errorstate;\r\n  }\r\n  \r\n  if(hsd->CardType != SECURE_DIGITAL_IO_CARD)\r\n  {\r\n    /* Send CMD2 ALL_SEND_CID */\r\n    sdmmc_cmdinitstructure.Argument         = 0;\r\n    sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_ALL_SEND_CID;\r\n    sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_LONG;\r\n    sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r\n    sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;\r\n    SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r\n    \r\n    /* Check for error conditions */\r\n    errorstate = SD_CmdResp2Error(hsd);\r\n    \r\n    if(errorstate != SD_OK)\r\n    {\r\n      return errorstate;\r\n    }\r\n    \r\n    /* Get Card identification number data */\r\n    hsd->CID[0] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);\r\n    hsd->CID[1] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);\r\n    hsd->CID[2] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);\r\n    hsd->CID[3] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);\r\n  }\r\n  \r\n  if((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1)    || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\\\r\n     (hsd->CardType == SECURE_DIGITAL_IO_COMBO_CARD) || (hsd->CardType == HIGH_CAPACITY_SD_CARD))\r\n  {\r\n    /* Send CMD3 SET_REL_ADDR with argument 0 */\r\n    /* SD Card publishes its RCA. */\r\n    sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_REL_ADDR;\r\n    sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;\r\n    SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r\n    \r\n    /* Check for error conditions */\r\n    errorstate = SD_CmdResp6Error(hsd, SD_CMD_SET_REL_ADDR, &sd_rca);\r\n    \r\n    if(errorstate != SD_OK)\r\n    {\r\n      return errorstate;\r\n    }\r\n  }\r\n  \r\n  if (hsd->CardType != SECURE_DIGITAL_IO_CARD)\r\n  {\r\n    /* Get the SD card RCA */\r\n    hsd->RCA = sd_rca;\r\n    \r\n    /* Send CMD9 SEND_CSD with argument as card's RCA */\r\n    sdmmc_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);\r\n    sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SEND_CSD;\r\n    sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_LONG;\r\n    SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r\n    \r\n    /* Check for error conditions */\r\n    errorstate = SD_CmdResp2Error(hsd);\r\n    \r\n    if(errorstate != SD_OK)\r\n    {\r\n      return errorstate;\r\n    }\r\n    \r\n    /* Get Card Specific Data */\r\n    hsd->CSD[0] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);\r\n    hsd->CSD[1] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2);\r\n    hsd->CSD[2] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3);\r\n    hsd->CSD[3] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4);\r\n  }\r\n  \r\n  /* All cards are initialized */\r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Selects od Deselects the corresponding card.\r\n  * @param  hsd: SD handle\r\n  * @param  addr: Address of the card to be selected  \r\n  * @retval SD Card error state\r\n  */\r\nstatic HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr)\r\n{\r\n  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r\n  HAL_SD_ErrorTypedef errorstate = SD_OK;\r\n  \r\n  /* Send CMD7 SDMMC_SEL_DESEL_CARD */\r\n  sdmmc_cmdinitstructure.Argument         = (uint32_t)addr;\r\n  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SEL_DESEL_CARD;\r\n  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;\r\n  sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEL_DESEL_CARD);\r\n  \r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Enquires cards about their operating voltage and configures clock\r\n  *         controls and stores SD information that will be needed in future\r\n  *         in the SD handle.\r\n  * @param  hsd: SD handle\r\n  * @retval SD Card error state\r\n  */\r\nstatic HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd)\r\n{\r\n  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure; \r\n  __IO HAL_SD_ErrorTypedef errorstate = SD_OK; \r\n  uint32_t response = 0, count = 0, validvoltage = 0;\r\n  uint32_t sdtype = SD_STD_CAPACITY;\r\n  \r\n  /* Power ON Sequence -------------------------------------------------------*/\r\n  /* Disable SDMMC Clock */\r\n  __HAL_SD_SDMMC_DISABLE(hsd); \r\n  \r\n  /* Set Power State to ON */\r\n  SDMMC_PowerState_ON(hsd->Instance);\r\n\r\n  /* 1ms: required power up waiting time before starting the SD initialization \r\n     sequence */\r\n  HAL_Delay(1);\r\n  \r\n  /* Enable SDMMC Clock */\r\n  __HAL_SD_SDMMC_ENABLE(hsd);\r\n  \r\n  /* CMD0: GO_IDLE_STATE -----------------------------------------------------*/\r\n  /* No CMD response required */\r\n  sdmmc_cmdinitstructure.Argument         = 0;\r\n  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_GO_IDLE_STATE;\r\n  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_NO;\r\n  sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SD_CmdError(hsd);\r\n  \r\n  if(errorstate != SD_OK)\r\n  {\r\n    /* CMD Response Timeout (wait for CMDSENT flag) */\r\n    return errorstate;\r\n  }\r\n  \r\n  /* CMD8: SEND_IF_COND ------------------------------------------------------*/\r\n  /* Send CMD8 to verify SD card interface operating condition */\r\n  /* Argument: - [31:12]: Reserved (shall be set to '0')\r\n  - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)\r\n  - [7:0]: Check Pattern (recommended 0xAA) */\r\n  /* CMD Response: R7 */\r\n  sdmmc_cmdinitstructure.Argument         = SD_CHECK_PATTERN;\r\n  sdmmc_cmdinitstructure.CmdIndex         = SD_SDMMC_SEND_IF_COND;\r\n  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;\r\n  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r\n  \r\n  /* Check for error conditions */ \r\n  errorstate = SD_CmdResp7Error(hsd);\r\n  \r\n  if (errorstate == SD_OK)\r\n  {\r\n    /* SD Card 2.0 */\r\n    hsd->CardType = STD_CAPACITY_SD_CARD_V2_0; \r\n    sdtype        = SD_HIGH_CAPACITY;\r\n  }\r\n  \r\n  /* Send CMD55 */\r\n  sdmmc_cmdinitstructure.Argument         = 0;\r\n  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;\r\n  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);\r\n  \r\n  /* If errorstate is Command Timeout, it is a MMC card */\r\n  /* If errorstate is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch)\r\n     or SD card 1.x */\r\n  if(errorstate == SD_OK)\r\n  {\r\n    /* SD CARD */\r\n    /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */\r\n    while((!validvoltage) && (count < SD_MAX_VOLT_TRIAL))\r\n    {\r\n      \r\n      /* SEND CMD55 APP_CMD with RCA as 0 */\r\n      sdmmc_cmdinitstructure.Argument         = 0;\r\n      sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;\r\n      sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;\r\n      sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r\n      sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;\r\n      SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r\n      \r\n      /* Check for error conditions */\r\n      errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);\r\n      \r\n      if(errorstate != SD_OK)\r\n      {\r\n        return errorstate;\r\n      }\r\n      \r\n      /* Send CMD41 */\r\n      sdmmc_cmdinitstructure.Argument         = SD_VOLTAGE_WINDOW_SD | sdtype;\r\n      sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SD_APP_OP_COND;\r\n      sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;\r\n      sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r\n      sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;\r\n      SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r\n      \r\n      /* Check for error conditions */\r\n      errorstate = SD_CmdResp3Error(hsd);\r\n      \r\n      if(errorstate != SD_OK)\r\n      {\r\n        return errorstate;\r\n      }\r\n      \r\n      /* Get command response */\r\n      response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);\r\n      \r\n      /* Get operating voltage*/\r\n      validvoltage = (((response >> 31) == 1) ? 1 : 0);\r\n      \r\n      count++;\r\n    }\r\n    \r\n    if(count >= SD_MAX_VOLT_TRIAL)\r\n    {\r\n      errorstate = SD_INVALID_VOLTRANGE;\r\n      \r\n      return errorstate;\r\n    }\r\n    \r\n    if((response & SD_HIGH_CAPACITY) == SD_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */\r\n    {\r\n      hsd->CardType = HIGH_CAPACITY_SD_CARD;\r\n    }\r\n    \r\n  } /* else MMC Card */\r\n  \r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Turns the SDMMC output signals off.\r\n  * @param  hsd: SD handle\r\n  * @retval SD Card error state\r\n  */\r\nstatic HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd)\r\n{\r\n  HAL_SD_ErrorTypedef errorstate = SD_OK;\r\n  \r\n  /* Set Power State to OFF */\r\n  SDMMC_PowerState_OFF(hsd->Instance);\r\n  \r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the current card's status.\r\n  * @param  hsd: SD handle\r\n  * @param  pCardStatus: pointer to the buffer that will contain the SD card \r\n  *         status (Card Status register)  \r\n  * @retval SD Card error state\r\n  */\r\nstatic HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)\r\n{\r\n  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r\n  HAL_SD_ErrorTypedef errorstate = SD_OK;\r\n  \r\n  if(pCardStatus == NULL)\r\n  {\r\n    errorstate = SD_INVALID_PARAMETER;\r\n    \r\n    return errorstate;\r\n  }\r\n  \r\n  /* Send Status command */\r\n  sdmmc_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);\r\n  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SEND_STATUS;\r\n  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;\r\n  sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEND_STATUS);\r\n  \r\n  if(errorstate != SD_OK)\r\n  {\r\n    return errorstate;\r\n  }\r\n  \r\n  /* Get SD card status */\r\n  *pCardStatus = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);\r\n  \r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Checks for error conditions for CMD0.\r\n  * @param  hsd: SD handle\r\n  * @retval SD Card error state\r\n  */\r\nstatic HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd)\r\n{\r\n  HAL_SD_ErrorTypedef errorstate = SD_OK;\r\n  uint32_t timeout, tmp;\r\n  \r\n  timeout = SDMMC_CMD0TIMEOUT;\r\n  \r\n  tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CMDSENT);\r\n    \r\n  while((timeout > 0) && (!tmp))\r\n  {\r\n    tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CMDSENT);\r\n    timeout--;\r\n  }\r\n  \r\n  if(timeout == 0)\r\n  {\r\n    errorstate = SD_CMD_RSP_TIMEOUT;\r\n    return errorstate;\r\n  }\r\n  \r\n  /* Clear all the static flags */\r\n  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r\n  \r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Checks for error conditions for R7 response.\r\n  * @param  hsd: SD handle\r\n  * @retval SD Card error state\r\n  */\r\nstatic HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd)\r\n{\r\n  HAL_SD_ErrorTypedef errorstate = SD_ERROR;\r\n  uint32_t timeout = SDMMC_CMD0TIMEOUT, tmp;\r\n  \r\n  tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT); \r\n  \r\n  while((!tmp) && (timeout > 0))\r\n  {\r\n    tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT);\r\n    timeout--;\r\n  }\r\n  \r\n  tmp = __HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT); \r\n  \r\n  if((timeout == 0) || tmp)\r\n  {\r\n    /* Card is not V2.0 compliant or card does not support the set voltage range */\r\n    errorstate = SD_CMD_RSP_TIMEOUT;\r\n    \r\n    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);\r\n    \r\n    return errorstate;\r\n  }\r\n  \r\n  if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CMDREND))\r\n  {\r\n    /* Card is SD V2.0 compliant */\r\n    errorstate = SD_OK;\r\n    \r\n    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CMDREND);\r\n    \r\n    return errorstate;\r\n  }\r\n  \r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Checks for error conditions for R1 response.\r\n  * @param  hsd: SD handle\r\n  * @param  SD_CMD: The sent command index  \r\n  * @retval SD Card error state\r\n  */\r\nstatic HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD)\r\n{\r\n  HAL_SD_ErrorTypedef errorstate = SD_OK;\r\n  uint32_t response_r1;\r\n  \r\n  while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT))\r\n  {\r\n  }\r\n  \r\n  if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT))\r\n  {\r\n    errorstate = SD_CMD_RSP_TIMEOUT;\r\n    \r\n    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);\r\n    \r\n    return errorstate;\r\n  }\r\n  else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL))\r\n  {\r\n    errorstate = SD_CMD_CRC_FAIL;\r\n    \r\n    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL);\r\n    \r\n    return errorstate;\r\n  }\r\n  \r\n  /* Check response received is of desired command */\r\n  if(SDMMC_GetCommandResponse(hsd->Instance) != SD_CMD)\r\n  {\r\n    errorstate = SD_ILLEGAL_CMD;\r\n    \r\n    return errorstate;\r\n  }\r\n  \r\n  /* Clear all the static flags */\r\n  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r\n  \r\n  /* We have received response, retrieve it for analysis  */\r\n  response_r1 = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);\r\n  \r\n  if((response_r1 & SD_OCR_ERRORBITS) == SD_ALLZERO)\r\n  {\r\n    return errorstate;\r\n  }\r\n  \r\n  if((response_r1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE)\r\n  {\r\n    return(SD_ADDR_OUT_OF_RANGE);\r\n  }\r\n  \r\n  if((response_r1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED)\r\n  {\r\n    return(SD_ADDR_MISALIGNED);\r\n  }\r\n  \r\n  if((response_r1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR)\r\n  {\r\n    return(SD_BLOCK_LEN_ERR);\r\n  }\r\n  \r\n  if((response_r1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR)\r\n  {\r\n    return(SD_ERASE_SEQ_ERR);\r\n  }\r\n  \r\n  if((response_r1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM)\r\n  {\r\n    return(SD_BAD_ERASE_PARAM);\r\n  }\r\n  \r\n  if((response_r1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION)\r\n  {\r\n    return(SD_WRITE_PROT_VIOLATION);\r\n  }\r\n  \r\n  if((response_r1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED)\r\n  {\r\n    return(SD_LOCK_UNLOCK_FAILED);\r\n  }\r\n  \r\n  if((response_r1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED)\r\n  {\r\n    return(SD_COM_CRC_FAILED);\r\n  }\r\n  \r\n  if((response_r1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD)\r\n  {\r\n    return(SD_ILLEGAL_CMD);\r\n  }\r\n  \r\n  if((response_r1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED)\r\n  {\r\n    return(SD_CARD_ECC_FAILED);\r\n  }\r\n  \r\n  if((response_r1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR)\r\n  {\r\n    return(SD_CC_ERROR);\r\n  }\r\n  \r\n  if((response_r1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR)\r\n  {\r\n    return(SD_GENERAL_UNKNOWN_ERROR);\r\n  }\r\n  \r\n  if((response_r1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN)\r\n  {\r\n    return(SD_STREAM_READ_UNDERRUN);\r\n  }\r\n  \r\n  if((response_r1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN)\r\n  {\r\n    return(SD_STREAM_WRITE_OVERRUN);\r\n  }\r\n  \r\n  if((response_r1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE)\r\n  {\r\n    return(SD_CID_CSD_OVERWRITE);\r\n  }\r\n  \r\n  if((response_r1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP)\r\n  {\r\n    return(SD_WP_ERASE_SKIP);\r\n  }\r\n  \r\n  if((response_r1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED)\r\n  {\r\n    return(SD_CARD_ECC_DISABLED);\r\n  }\r\n  \r\n  if((response_r1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET)\r\n  {\r\n    return(SD_ERASE_RESET);\r\n  }\r\n  \r\n  if((response_r1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR)\r\n  {\r\n    return(SD_AKE_SEQ_ERROR);\r\n  }\r\n  \r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Checks for error conditions for R3 (OCR) response.\r\n  * @param  hsd: SD handle\r\n  * @retval SD Card error state\r\n  */\r\nstatic HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd)\r\n{\r\n  HAL_SD_ErrorTypedef errorstate = SD_OK;\r\n  \r\n  while (!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT))\r\n  {\r\n  }\r\n  \r\n  if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT))\r\n  {\r\n    errorstate = SD_CMD_RSP_TIMEOUT;\r\n    \r\n    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);\r\n    \r\n    return errorstate;\r\n  }\r\n  \r\n  /* Clear all the static flags */\r\n  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r\n  \r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Checks for error conditions for R2 (CID or CSD) response.\r\n  * @param  hsd: SD handle\r\n  * @retval SD Card error state\r\n  */\r\nstatic HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd)\r\n{\r\n  HAL_SD_ErrorTypedef errorstate = SD_OK;\r\n  \r\n  while (!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT))\r\n  {\r\n  }\r\n    \r\n  if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT))\r\n  {\r\n    errorstate = SD_CMD_RSP_TIMEOUT;\r\n    \r\n    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);\r\n    \r\n    return errorstate;\r\n  }\r\n  else if (__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL))\r\n  {\r\n    errorstate = SD_CMD_CRC_FAIL;\r\n    \r\n    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL);\r\n    \r\n    return errorstate;\r\n  }\r\n  else\r\n  {\r\n    /* No error flag set */\r\n  }  \r\n  \r\n  /* Clear all the static flags */\r\n  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r\n  \r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Checks for error conditions for R6 (RCA) response.\r\n  * @param  hsd: SD handle\r\n  * @param  SD_CMD: The sent command index\r\n  * @param  pRCA: Pointer to the variable that will contain the SD card relative \r\n  *         address RCA   \r\n  * @retval SD Card error state\r\n  */\r\nstatic HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA)\r\n{\r\n  HAL_SD_ErrorTypedef errorstate = SD_OK;\r\n  uint32_t response_r1;\r\n  \r\n  while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT))\r\n  {\r\n  }\r\n  \r\n  if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT))\r\n  {\r\n    errorstate = SD_CMD_RSP_TIMEOUT;\r\n    \r\n    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);\r\n    \r\n    return errorstate;\r\n  }\r\n  else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL))\r\n  {\r\n    errorstate = SD_CMD_CRC_FAIL;\r\n    \r\n    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL);\r\n    \r\n    return errorstate;\r\n  }\r\n  else\r\n  {\r\n    /* No error flag set */\r\n  }  \r\n  \r\n  /* Check response received is of desired command */\r\n  if(SDMMC_GetCommandResponse(hsd->Instance) != SD_CMD)\r\n  {\r\n    errorstate = SD_ILLEGAL_CMD;\r\n    \r\n    return errorstate;\r\n  }\r\n  \r\n  /* Clear all the static flags */\r\n  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r\n  \r\n  /* We have received response, retrieve it.  */\r\n  response_r1 = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);\r\n  \r\n  if((response_r1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED)) == SD_ALLZERO)\r\n  {\r\n    *pRCA = (uint16_t) (response_r1 >> 16);\r\n    \r\n    return errorstate;\r\n  }\r\n  \r\n  if((response_r1 & SD_R6_GENERAL_UNKNOWN_ERROR) == SD_R6_GENERAL_UNKNOWN_ERROR)\r\n  {\r\n    return(SD_GENERAL_UNKNOWN_ERROR);\r\n  }\r\n  \r\n  if((response_r1 & SD_R6_ILLEGAL_CMD) == SD_R6_ILLEGAL_CMD)\r\n  {\r\n    return(SD_ILLEGAL_CMD);\r\n  }\r\n  \r\n  if((response_r1 & SD_R6_COM_CRC_FAILED) == SD_R6_COM_CRC_FAILED)\r\n  {\r\n    return(SD_COM_CRC_FAILED);\r\n  }\r\n  \r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Enables the SDMMC wide bus mode.\r\n  * @param  hsd: SD handle\r\n  * @retval SD Card error state\r\n  */\r\nstatic HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd)\r\n{\r\n  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r\n  HAL_SD_ErrorTypedef errorstate = SD_OK;\r\n  \r\n  uint32_t scr[2] = {0, 0};\r\n  \r\n  if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)\r\n  {\r\n    errorstate = SD_LOCK_UNLOCK_FAILED;\r\n    \r\n    return errorstate;\r\n  }\r\n  \r\n  /* Get SCR Register */\r\n  errorstate = SD_FindSCR(hsd, scr);\r\n  \r\n  if(errorstate != SD_OK)\r\n  {\r\n    return errorstate;\r\n  }\r\n  \r\n  /* If requested card supports wide bus operation */\r\n  if((scr[1] & SD_WIDE_BUS_SUPPORT) != SD_ALLZERO)\r\n  {\r\n    /* Send CMD55 APP_CMD with argument as card's RCA.*/\r\n    sdmmc_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);\r\n    sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;\r\n    sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;\r\n    sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r\n    sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;\r\n    SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r\n    \r\n    /* Check for error conditions */\r\n    errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);\r\n    \r\n    if(errorstate != SD_OK)\r\n    {\r\n      return errorstate;\r\n    }\r\n    \r\n    /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */\r\n    sdmmc_cmdinitstructure.Argument         = 2;\r\n    sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_SD_SET_BUSWIDTH;\r\n    SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r\n    \r\n    /* Check for error conditions */\r\n    errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH);\r\n    \r\n    if(errorstate != SD_OK)\r\n    {\r\n      return errorstate;\r\n    }\r\n    \r\n    return errorstate;\r\n  }\r\n  else\r\n  {\r\n    errorstate = SD_REQUEST_NOT_APPLICABLE;\r\n    \r\n    return errorstate;\r\n  }\r\n}   \r\n\r\n/**\r\n  * @brief  Disables the SDMMC wide bus mode.\r\n  * @param  hsd: SD handle\r\n  * @retval SD Card error state\r\n  */\r\nstatic HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd)\r\n{\r\n  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r\n  HAL_SD_ErrorTypedef errorstate = SD_OK;\r\n  \r\n  uint32_t scr[2] = {0, 0};\r\n  \r\n  if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)\r\n  {\r\n    errorstate = SD_LOCK_UNLOCK_FAILED;\r\n    \r\n    return errorstate;\r\n  }\r\n  \r\n  /* Get SCR Register */\r\n  errorstate = SD_FindSCR(hsd, scr);\r\n  \r\n  if(errorstate != SD_OK)\r\n  {\r\n    return errorstate;\r\n  }\r\n  \r\n  /* If requested card supports 1 bit mode operation */\r\n  if((scr[1] & SD_SINGLE_BUS_SUPPORT) != SD_ALLZERO)\r\n  {\r\n    /* Send CMD55 APP_CMD with argument as card's RCA */\r\n    sdmmc_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);\r\n    sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;\r\n    sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;\r\n    sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r\n    sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;\r\n    SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r\n    \r\n    /* Check for error conditions */\r\n    errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);\r\n    \r\n    if(errorstate != SD_OK)\r\n    {\r\n      return errorstate;\r\n    }\r\n    \r\n    /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */\r\n    sdmmc_cmdinitstructure.Argument         = 0;\r\n    sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_SD_SET_BUSWIDTH;\r\n    SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r\n    \r\n    /* Check for error conditions */\r\n    errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH);\r\n    \r\n    if(errorstate != SD_OK)\r\n    {\r\n      return errorstate;\r\n    }\r\n    \r\n    return errorstate;\r\n  }\r\n  else\r\n  {\r\n    errorstate = SD_REQUEST_NOT_APPLICABLE;\r\n    \r\n    return errorstate;\r\n  }\r\n}\r\n  \r\n  \r\n/**\r\n  * @brief  Finds the SD card SCR register value.\r\n  * @param  hsd: SD handle\r\n  * @param  pSCR: pointer to the buffer that will contain the SCR value  \r\n  * @retval SD Card error state\r\n  */\r\nstatic HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)\r\n{\r\n  SDMMC_CmdInitTypeDef  sdmmc_cmdinitstructure;\r\n  SDMMC_DataInitTypeDef sdmmc_datainitstructure;\r\n  HAL_SD_ErrorTypedef errorstate = SD_OK;\r\n  uint32_t index = 0;\r\n  uint32_t tempscr[2] = {0, 0};\r\n  \r\n  /* Set Block Size To 8 Bytes */\r\n  /* Send CMD55 APP_CMD with argument as card's RCA */\r\n  sdmmc_cmdinitstructure.Argument         = (uint32_t)8;\r\n  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;\r\n  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;\r\n  sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);\r\n  \r\n  if(errorstate != SD_OK)\r\n  {\r\n    return errorstate;\r\n  }\r\n  \r\n  /* Send CMD55 APP_CMD with argument as card's RCA */\r\n  sdmmc_cmdinitstructure.Argument         = (uint32_t)((hsd->RCA) << 16);\r\n  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;\r\n  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);\r\n  \r\n  if(errorstate != SD_OK)\r\n  {\r\n    return errorstate;\r\n  }\r\n  sdmmc_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;\r\n  sdmmc_datainitstructure.DataLength    = 8;\r\n  sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B;\r\n  sdmmc_datainitstructure.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;\r\n  sdmmc_datainitstructure.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;\r\n  sdmmc_datainitstructure.DPSM          = SDMMC_DPSM_ENABLE;\r\n  SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);\r\n  \r\n  /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */\r\n  sdmmc_cmdinitstructure.Argument         = 0;\r\n  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SD_APP_SEND_SCR;\r\n  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r\n  \r\n  /* Check for error conditions */\r\n  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_SEND_SCR);\r\n  \r\n  if(errorstate != SD_OK)\r\n  {\r\n    return errorstate;\r\n  }\r\n  \r\n  while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND))\r\n  {\r\n    if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL))\r\n    {\r\n      *(tempscr + index) = SDMMC_ReadFIFO(hsd->Instance);\r\n      index++;\r\n    }\r\n  }\r\n  \r\n  if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))\r\n  {\r\n    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);\r\n    \r\n    errorstate = SD_DATA_TIMEOUT;\r\n    \r\n    return errorstate;\r\n  }\r\n  else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))\r\n  {\r\n    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);\r\n    \r\n    errorstate = SD_DATA_CRC_FAIL;\r\n    \r\n    return errorstate;\r\n  }\r\n  else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))\r\n  {\r\n    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);\r\n    \r\n    errorstate = SD_RX_OVERRUN;\r\n    \r\n    return errorstate;\r\n  }\r\n  else\r\n  {\r\n    /* No error flag set */\r\n  }\r\n  \r\n  /* Clear all the static flags */\r\n  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r\n  \r\n  *(pSCR + 1) = ((tempscr[0] & SD_0TO7BITS) << 24)  | ((tempscr[0] & SD_8TO15BITS) << 8) |\\\r\n    ((tempscr[0] & SD_16TO23BITS) >> 8) | ((tempscr[0] & SD_24TO31BITS) >> 24);\r\n  \r\n  *(pSCR) = ((tempscr[1] & SD_0TO7BITS) << 24)  | ((tempscr[1] & SD_8TO15BITS) << 8) |\\\r\n    ((tempscr[1] & SD_16TO23BITS) >> 8) | ((tempscr[1] & SD_24TO31BITS) >> 24);\r\n  \r\n  return errorstate;\r\n}\r\n\r\n/**\r\n  * @brief  Checks if the SD card is in programming state.\r\n  * @param  hsd: SD handle\r\n  * @param  pStatus: pointer to the variable that will contain the SD card state  \r\n  * @retval SD Card error state\r\n  */\r\nstatic HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus)\r\n{\r\n  SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;\r\n  HAL_SD_ErrorTypedef errorstate = SD_OK;\r\n  __IO uint32_t responseR1 = 0;\r\n  \r\n  sdmmc_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);\r\n  sdmmc_cmdinitstructure.CmdIndex         = SD_CMD_SEND_STATUS;\r\n  sdmmc_cmdinitstructure.Response         = SDMMC_RESPONSE_SHORT;\r\n  sdmmc_cmdinitstructure.WaitForInterrupt = SDMMC_WAIT_NO;\r\n  sdmmc_cmdinitstructure.CPSM             = SDMMC_CPSM_ENABLE;\r\n  SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);\r\n  \r\n  while(!__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT))\r\n  {\r\n  }\r\n  \r\n  if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CTIMEOUT))\r\n  {\r\n    errorstate = SD_CMD_RSP_TIMEOUT;\r\n    \r\n    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CTIMEOUT);\r\n    \r\n    return errorstate;\r\n  }\r\n  else if(__HAL_SD_SDMMC_GET_FLAG(hsd, SDMMC_FLAG_CCRCFAIL))\r\n  {\r\n    errorstate = SD_CMD_CRC_FAIL;\r\n    \r\n    __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_FLAG_CCRCFAIL);\r\n    \r\n    return errorstate;\r\n  }\r\n  else\r\n  {\r\n    /* No error flag set */\r\n  }\r\n  \r\n  /* Check response received is of desired command */\r\n  if((uint32_t)SDMMC_GetCommandResponse(hsd->Instance) != SD_CMD_SEND_STATUS)\r\n  {\r\n    errorstate = SD_ILLEGAL_CMD;\r\n    \r\n    return errorstate;\r\n  }\r\n  \r\n  /* Clear all the static flags */\r\n  __HAL_SD_SDMMC_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);\r\n  \r\n  \r\n  /* We have received response, retrieve it for analysis */\r\n  responseR1 = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);\r\n  \r\n  /* Find out card status */\r\n  *pStatus = (uint8_t)((responseR1 >> 9) & 0x0000000F);\r\n  \r\n  if((responseR1 & SD_OCR_ERRORBITS) == SD_ALLZERO)\r\n  {\r\n    return errorstate;\r\n  }\r\n  \r\n  if((responseR1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE)\r\n  {\r\n    return(SD_ADDR_OUT_OF_RANGE);\r\n  }\r\n  \r\n  if((responseR1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED)\r\n  {\r\n    return(SD_ADDR_MISALIGNED);\r\n  }\r\n  \r\n  if((responseR1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR)\r\n  {\r\n    return(SD_BLOCK_LEN_ERR);\r\n  }\r\n  \r\n  if((responseR1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR)\r\n  {\r\n    return(SD_ERASE_SEQ_ERR);\r\n  }\r\n  \r\n  if((responseR1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM)\r\n  {\r\n    return(SD_BAD_ERASE_PARAM);\r\n  }\r\n  \r\n  if((responseR1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION)\r\n  {\r\n    return(SD_WRITE_PROT_VIOLATION);\r\n  }\r\n  \r\n  if((responseR1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED)\r\n  {\r\n    return(SD_LOCK_UNLOCK_FAILED);\r\n  }\r\n  \r\n  if((responseR1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED)\r\n  {\r\n    return(SD_COM_CRC_FAILED);\r\n  }\r\n  \r\n  if((responseR1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD)\r\n  {\r\n    return(SD_ILLEGAL_CMD);\r\n  }\r\n  \r\n  if((responseR1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED)\r\n  {\r\n    return(SD_CARD_ECC_FAILED);\r\n  }\r\n  \r\n  if((responseR1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR)\r\n  {\r\n    return(SD_CC_ERROR);\r\n  }\r\n  \r\n  if((responseR1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR)\r\n  {\r\n    return(SD_GENERAL_UNKNOWN_ERROR);\r\n  }\r\n  \r\n  if((responseR1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN)\r\n  {\r\n    return(SD_STREAM_READ_UNDERRUN);\r\n  }\r\n  \r\n  if((responseR1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN)\r\n  {\r\n    return(SD_STREAM_WRITE_OVERRUN);\r\n  }\r\n  \r\n  if((responseR1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE)\r\n  {\r\n    return(SD_CID_CSD_OVERWRITE);\r\n  }\r\n  \r\n  if((responseR1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP)\r\n  {\r\n    return(SD_WP_ERASE_SKIP);\r\n  }\r\n  \r\n  if((responseR1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED)\r\n  {\r\n    return(SD_CARD_ECC_DISABLED);\r\n  }\r\n  \r\n  if((responseR1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET)\r\n  {\r\n    return(SD_ERASE_RESET);\r\n  }\r\n  \r\n  if((responseR1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR)\r\n  {\r\n    return(SD_AKE_SEQ_ERROR);\r\n  }\r\n  \r\n  return errorstate;\r\n}   \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_SD_MODULE_ENABLED */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_sdram.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   SDRAM HAL module driver.\r\n  *          This file provides a generic firmware to drive SDRAM memories mounted \r\n  *          as external device.\r\n  *         \r\n  @verbatim\r\n  ==============================================================================\r\n                       ##### How to use this driver #####\r\n  ============================================================================== \r\n  [..]\r\n    This driver is a generic layered driver which contains a set of APIs used to \r\n    control SDRAM memories. It uses the FMC layer functions to interface \r\n    with SDRAM devices.  \r\n    The following sequence should be followed to configure the FMC to interface\r\n    with SDRAM memories: \r\n      \r\n   (#) Declare a SDRAM_HandleTypeDef handle structure, for example:\r\n          SDRAM_HandleTypeDef  hdsram \r\n          \r\n       (++) Fill the SDRAM_HandleTypeDef handle \"Init\" field with the allowed \r\n            values of the structure member.\r\n            \r\n       (++) Fill the SDRAM_HandleTypeDef handle \"Instance\" field with a predefined \r\n            base register instance for NOR or SDRAM device \r\n             \r\n   (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:\r\n          FMC_SDRAM_TimingTypeDef  Timing;\r\n      and fill its fields with the allowed values of the structure member.\r\n      \r\n   (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function\r\n       performs the following sequence:\r\n          \r\n       (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()\r\n       (##) Control register configuration using the FMC SDRAM interface function \r\n            FMC_SDRAM_Init()\r\n       (##) Timing register configuration using the FMC SDRAM interface function \r\n            FMC_SDRAM_Timing_Init()\r\n       (##) Program the SDRAM external device by applying its initialization sequence\r\n            according to the device plugged in your hardware. This step is mandatory\r\n            for accessing the SDRAM device.   \r\n\r\n   (#) At this stage you can perform read/write accesses from/to the memory connected \r\n       to the SDRAM Bank. You can perform either polling or DMA transfer using the\r\n       following APIs:\r\n       (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access\r\n       (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer\r\n       \r\n   (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/\r\n       HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or \r\n       the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM\r\n       device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef \r\n       structure.   \r\n       \r\n   (#) You can continuously monitor the SDRAM device HAL state by calling the function\r\n       HAL_SDRAM_GetState()         \r\n      \r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup SDRAM SDRAM\r\n  * @brief SDRAM driver modules\r\n  * @{\r\n  */\r\n#ifdef HAL_SDRAM_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/    \r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions \r\n  * @brief    Initialization and Configuration functions \r\n  *\r\n  @verbatim    \r\n  ==============================================================================\r\n           ##### SDRAM Initialization and de_initialization functions #####\r\n  ==============================================================================\r\n  [..]  \r\n    This section provides functions allowing to initialize/de-initialize\r\n    the SDRAM memory\r\n  \r\n@endverbatim\r\n  * @{\r\n  */\r\n    \r\n/**\r\n  * @brief  Performs the SDRAM device initialization sequence.\r\n  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SDRAM module.\r\n  * @param  Timing: Pointer to SDRAM control timing structure \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)\r\n{   \r\n  /* Check the SDRAM handle parameter */\r\n  if(hsdram == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  if(hsdram->State == HAL_SDRAM_STATE_RESET)\r\n  {  \r\n    /* Allocate lock resource and initialize it */\r\n    hsdram->Lock = HAL_UNLOCKED;\r\n    /* Initialize the low level hardware (MSP) */\r\n    HAL_SDRAM_MspInit(hsdram);\r\n  }\r\n  \r\n  /* Initialize the SDRAM controller state */\r\n  hsdram->State = HAL_SDRAM_STATE_BUSY;\r\n  \r\n  /* Initialize SDRAM control Interface */\r\n  FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));\r\n  \r\n  /* Initialize SDRAM timing Interface */\r\n  FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank); \r\n  \r\n  /* Update the SDRAM controller state */\r\n  hsdram->State = HAL_SDRAM_STATE_READY;\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Perform the SDRAM device initialization sequence.\r\n  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SDRAM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)\r\n{\r\n  /* Initialize the low level hardware (MSP) */\r\n  HAL_SDRAM_MspDeInit(hsdram);\r\n\r\n  /* Configure the SDRAM registers with their reset values */\r\n  FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);\r\n\r\n  /* Reset the SDRAM controller state */\r\n  hsdram->State = HAL_SDRAM_STATE_RESET;\r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hsdram);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  SDRAM MSP Init.\r\n  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SDRAM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hsdram);\r\n \r\n  /* NOTE: This function Should not be modified, when the callback is needed,\r\n            the HAL_SDRAM_MspInit could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  SDRAM MSP DeInit.\r\n  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SDRAM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hsdram);\r\n \r\n  /* NOTE: This function Should not be modified, when the callback is needed,\r\n            the HAL_SDRAM_MspDeInit could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  This function handles SDRAM refresh error interrupt request.\r\n  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SDRAM module.\r\n  * @retval HAL status\r\n*/\r\nvoid HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)\r\n{\r\n  /* Check SDRAM interrupt Rising edge flag */\r\n  if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))\r\n  {\r\n    /* SDRAM refresh error interrupt callback */\r\n    HAL_SDRAM_RefreshErrorCallback(hsdram);\r\n    \r\n    /* Clear SDRAM refresh error interrupt pending bit */\r\n    __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  SDRAM Refresh error callback.\r\n  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SDRAM module. \r\n  * @retval None\r\n  */\r\n__weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hsdram);\r\n \r\n  /* NOTE: This function Should not be modified, when the callback is needed,\r\n            the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  DMA transfer complete callback.\r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdma);\r\n \r\n  /* NOTE: This function Should not be modified, when the callback is needed,\r\n            the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  DMA transfer complete error callback.\r\n  * @param  hdma: DMA handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdma);\r\n \r\n  /* NOTE: This function Should not be modified, when the callback is needed,\r\n            the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions \r\n  * @brief    Input Output and memory control functions \r\n  *\r\n  @verbatim    \r\n  ==============================================================================\r\n                    ##### SDRAM Input and Output functions #####\r\n  ==============================================================================\r\n  [..]  \r\n    This section provides functions allowing to use and control the SDRAM memory\r\n  \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Reads 8-bit data buffer from the SDRAM memory.\r\n  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SDRAM module.\r\n  * @param  pAddress: Pointer to read start address\r\n  * @param  pDstBuffer: Pointer to destination buffer  \r\n  * @param  BufferSize: Size of the buffer to read from memory\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)\r\n{\r\n  __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hsdram);\r\n  \r\n  /* Check the SDRAM controller state */\r\n  if(hsdram->State == HAL_SDRAM_STATE_BUSY)\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n  else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)\r\n  {\r\n    return  HAL_ERROR; \r\n  }  \r\n  \r\n  /* Read data from source */\r\n  for(; BufferSize != 0; BufferSize--)\r\n  {\r\n    *pDstBuffer = *(__IO uint8_t *)pSdramAddress;  \r\n    pDstBuffer++;\r\n    pSdramAddress++;\r\n  }\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hsdram);\r\n  \r\n  return HAL_OK; \r\n}\r\n\r\n\r\n/**\r\n  * @brief  Writes 8-bit data buffer to SDRAM memory.\r\n  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SDRAM module.\r\n  * @param  pAddress: Pointer to write start address\r\n  * @param  pSrcBuffer: Pointer to source buffer to write  \r\n  * @param  BufferSize: Size of the buffer to write to memory\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)\r\n{\r\n  __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;\r\n  uint32_t tmp = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hsdram);\r\n  \r\n  /* Check the SDRAM controller state */\r\n  tmp = hsdram->State;\r\n  \r\n  if(tmp == HAL_SDRAM_STATE_BUSY)\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n  else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))\r\n  {\r\n    return  HAL_ERROR; \r\n  }\r\n  \r\n  /* Write data to memory */\r\n  for(; BufferSize != 0; BufferSize--)\r\n  {\r\n    *(__IO uint8_t *)pSdramAddress = *pSrcBuffer;\r\n    pSrcBuffer++;\r\n    pSdramAddress++;\r\n  }\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hsdram);    \r\n  \r\n  return HAL_OK;   \r\n}\r\n\r\n\r\n/**\r\n  * @brief  Reads 16-bit data buffer from the SDRAM memory. \r\n  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SDRAM module.\r\n  * @param  pAddress: Pointer to read start address\r\n  * @param  pDstBuffer: Pointer to destination buffer  \r\n  * @param  BufferSize: Size of the buffer to read from memory\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)\r\n{\r\n  __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hsdram);\r\n  \r\n  /* Check the SDRAM controller state */\r\n  if(hsdram->State == HAL_SDRAM_STATE_BUSY)\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n  else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)\r\n  {\r\n    return  HAL_ERROR; \r\n  }  \r\n  \r\n  /* Read data from source */\r\n  for(; BufferSize != 0; BufferSize--)\r\n  {\r\n    *pDstBuffer = *(__IO uint16_t *)pSdramAddress;  \r\n    pDstBuffer++;\r\n    pSdramAddress++;               \r\n  }\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hsdram);       \r\n  \r\n  return HAL_OK; \r\n}\r\n\r\n/**\r\n  * @brief  Writes 16-bit data buffer to SDRAM memory. \r\n  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SDRAM module.\r\n  * @param  pAddress: Pointer to write start address\r\n  * @param  pSrcBuffer: Pointer to source buffer to write  \r\n  * @param  BufferSize: Size of the buffer to write to memory\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)\r\n{\r\n  __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;\r\n  uint32_t tmp = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hsdram);\r\n  \r\n  /* Check the SDRAM controller state */\r\n  tmp = hsdram->State;\r\n  \r\n  if(tmp == HAL_SDRAM_STATE_BUSY)\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n  else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))\r\n  {\r\n    return  HAL_ERROR; \r\n  }\r\n  \r\n  /* Write data to memory */\r\n  for(; BufferSize != 0; BufferSize--)\r\n  {\r\n    *(__IO uint16_t *)pSdramAddress = *pSrcBuffer;\r\n    pSrcBuffer++;\r\n    pSdramAddress++;            \r\n  }\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hsdram);    \r\n  \r\n  return HAL_OK;   \r\n}\r\n\r\n/**\r\n  * @brief  Reads 32-bit data buffer from the SDRAM memory. \r\n  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SDRAM module.\r\n  * @param  pAddress: Pointer to read start address\r\n  * @param  pDstBuffer: Pointer to destination buffer  \r\n  * @param  BufferSize: Size of the buffer to read from memory\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)\r\n{\r\n  __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hsdram);\r\n  \r\n  /* Check the SDRAM controller state */\r\n  if(hsdram->State == HAL_SDRAM_STATE_BUSY)\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n  else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)\r\n  {\r\n    return  HAL_ERROR; \r\n  }  \r\n  \r\n  /* Read data from source */\r\n  for(; BufferSize != 0; BufferSize--)\r\n  {\r\n    *pDstBuffer = *(__IO uint32_t *)pSdramAddress;  \r\n    pDstBuffer++;\r\n    pSdramAddress++;               \r\n  }\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hsdram);       \r\n  \r\n  return HAL_OK; \r\n}\r\n\r\n/**\r\n  * @brief  Writes 32-bit data buffer to SDRAM memory. \r\n  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SDRAM module.\r\n  * @param  pAddress: Pointer to write start address\r\n  * @param  pSrcBuffer: Pointer to source buffer to write  \r\n  * @param  BufferSize: Size of the buffer to write to memory\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)\r\n{\r\n  __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;\r\n  uint32_t tmp = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hsdram);\r\n  \r\n  /* Check the SDRAM controller state */\r\n  tmp = hsdram->State;\r\n  \r\n  if(tmp == HAL_SDRAM_STATE_BUSY)\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n  else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))\r\n  {\r\n    return  HAL_ERROR; \r\n  }\r\n  \r\n  /* Write data to memory */\r\n  for(; BufferSize != 0; BufferSize--)\r\n  {\r\n    *(__IO uint32_t *)pSdramAddress = *pSrcBuffer;\r\n    pSrcBuffer++;\r\n    pSdramAddress++;          \r\n  }\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hsdram);    \r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Reads a Words data from the SDRAM memory using DMA transfer. \r\n  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SDRAM module.\r\n  * @param  pAddress: Pointer to read start address\r\n  * @param  pDstBuffer: Pointer to destination buffer  \r\n  * @param  BufferSize: Size of the buffer to read from memory\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)\r\n{\r\n  uint32_t tmp = 0;\r\n    \r\n  /* Process Locked */\r\n  __HAL_LOCK(hsdram);\r\n  \r\n  /* Check the SDRAM controller state */  \r\n  tmp = hsdram->State;\r\n  \r\n  if(tmp == HAL_SDRAM_STATE_BUSY)\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n  else if(tmp == HAL_SDRAM_STATE_PRECHARGED)\r\n  {\r\n    return  HAL_ERROR; \r\n  }  \r\n  \r\n  /* Configure DMA user callbacks */\r\n  hsdram->hdma->XferCpltCallback  = HAL_SDRAM_DMA_XferCpltCallback;\r\n  hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;\r\n  \r\n  /* Enable the DMA Stream */\r\n  HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hsdram);  \r\n  \r\n  return HAL_OK; \r\n}\r\n\r\n/**\r\n  * @brief  Writes a Words data buffer to SDRAM memory using DMA transfer.\r\n  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SDRAM module.\r\n  * @param  pAddress: Pointer to write start address\r\n  * @param  pSrcBuffer: Pointer to source buffer to write  \r\n  * @param  BufferSize: Size of the buffer to write to memory\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)\r\n{\r\n  uint32_t tmp = 0;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hsdram);\r\n  \r\n  /* Check the SDRAM controller state */  \r\n  tmp = hsdram->State;\r\n  \r\n  if(tmp == HAL_SDRAM_STATE_BUSY)\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n  else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))\r\n  {\r\n    return  HAL_ERROR; \r\n  }  \r\n  \r\n  /* Configure DMA user callbacks */\r\n  hsdram->hdma->XferCpltCallback  = HAL_SDRAM_DMA_XferCpltCallback;\r\n  hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;\r\n  \r\n  /* Enable the DMA Stream */\r\n  HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hsdram);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup SDRAM_Exported_Functions_Group3 Control functions \r\n *  @brief   management functions \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                         ##### SDRAM Control functions #####\r\n  ==============================================================================  \r\n  [..]\r\n    This subsection provides a set of functions allowing to control dynamically\r\n    the SDRAM interface.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Enables dynamically SDRAM write protection.\r\n  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SDRAM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)\r\n{ \r\n  /* Check the SDRAM controller state */ \r\n  if(hsdram->State == HAL_SDRAM_STATE_BUSY)\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n  \r\n  /* Update the SDRAM state */\r\n  hsdram->State = HAL_SDRAM_STATE_BUSY;\r\n  \r\n  /* Enable write protection */\r\n  FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);\r\n  \r\n  /* Update the SDRAM state */\r\n  hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;\r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Disables dynamically SDRAM write protection.\r\n  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SDRAM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)\r\n{\r\n  /* Check the SDRAM controller state */\r\n  if(hsdram->State == HAL_SDRAM_STATE_BUSY)\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n  \r\n  /* Update the SDRAM state */\r\n  hsdram->State = HAL_SDRAM_STATE_BUSY;\r\n  \r\n  /* Disable write protection */\r\n  FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);\r\n  \r\n  /* Update the SDRAM state */\r\n  hsdram->State = HAL_SDRAM_STATE_READY;\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Sends Command to the SDRAM bank.\r\n  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SDRAM module.\r\n  * @param  Command: SDRAM command structure\r\n  * @param  Timeout: Timeout duration\r\n  * @retval HAL status\r\n  */  \r\nHAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)\r\n{\r\n  /* Check the SDRAM controller state */\r\n  if(hsdram->State == HAL_SDRAM_STATE_BUSY)\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n  \r\n  /* Update the SDRAM state */\r\n  hsdram->State = HAL_SDRAM_STATE_BUSY;\r\n  \r\n  /* Send SDRAM command */\r\n  FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);\r\n  \r\n  /* Update the SDRAM controller state state */\r\n  if(Command->CommandMode == FMC_SDRAM_CMD_PALL)\r\n  {\r\n    hsdram->State = HAL_SDRAM_STATE_PRECHARGED;\r\n  }\r\n  else\r\n  {\r\n    hsdram->State = HAL_SDRAM_STATE_READY;\r\n  }\r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Programs the SDRAM Memory Refresh rate.\r\n  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SDRAM module.  \r\n  * @param  RefreshRate: The SDRAM refresh rate value       \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)\r\n{\r\n  /* Check the SDRAM controller state */\r\n  if(hsdram->State == HAL_SDRAM_STATE_BUSY)\r\n  {\r\n    return HAL_BUSY;\r\n  } \r\n  \r\n  /* Update the SDRAM state */\r\n  hsdram->State = HAL_SDRAM_STATE_BUSY;\r\n  \r\n  /* Program the refresh rate */\r\n  FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate);\r\n  \r\n  /* Update the SDRAM state */\r\n  hsdram->State = HAL_SDRAM_STATE_READY;\r\n  \r\n  return HAL_OK;   \r\n}\r\n\r\n/**\r\n  * @brief  Sets the Number of consecutive SDRAM Memory auto Refresh commands.\r\n  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SDRAM module.  \r\n  * @param  AutoRefreshNumber: The SDRAM auto Refresh number       \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)\r\n{\r\n  /* Check the SDRAM controller state */\r\n  if(hsdram->State == HAL_SDRAM_STATE_BUSY)\r\n  {\r\n    return HAL_BUSY;\r\n  } \r\n  \r\n  /* Update the SDRAM state */\r\n  hsdram->State = HAL_SDRAM_STATE_BUSY;\r\n  \r\n  /* Set the Auto-Refresh number */\r\n  FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance ,AutoRefreshNumber);\r\n  \r\n  /* Update the SDRAM state */\r\n  hsdram->State = HAL_SDRAM_STATE_READY;\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Returns the SDRAM memory current mode.\r\n  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SDRAM module.\r\n  * @retval The SDRAM memory mode.        \r\n  */\r\nuint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)\r\n{\r\n  /* Return the SDRAM memory current mode */\r\n  return(FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup SDRAM_Exported_Functions_Group4 State functions \r\n *  @brief   Peripheral State functions \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                      ##### SDRAM State functions #####\r\n  ==============================================================================  \r\n  [..]\r\n    This subsection permits to get in run-time the status of the SDRAM controller \r\n    and the data flow.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Returns the SDRAM state.\r\n  * @param  hsdram: pointer to a SDRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SDRAM module.\r\n  * @retval HAL state\r\n  */\r\nHAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)\r\n{\r\n  return hsdram->State;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */    \r\n\r\n/**\r\n  * @}\r\n  */\r\n#endif /* HAL_SDRAM_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smartcard.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_smartcard.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   SMARTCARD HAL module driver.\r\n  *          This file provides firmware functions to manage the following\r\n  *          functionalities of the SMARTCARD peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + IO operation functions\r\n  *           + Peripheral State and Errors functions \r\n  *           \r\n  @verbatim       \r\n  ==============================================================================\r\n                     ##### How to use this driver #####\r\n  ==============================================================================\r\n  [..]\r\n    The SMARTCARD HAL driver can be used as follow:\r\n    \r\n    (#) Declare a SMARTCARD_HandleTypeDef handle structure.\r\n    (#) Associate a USART to the SMARTCARD handle hsc.\r\n    (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:\r\n        (##) Enable the USARTx interface clock.\r\n        (##) SMARTCARD pins configuration:\r\n            (+++) Enable the clock for the SMARTCARD GPIOs.\r\n            (+++) Configure these SMARTCARD pins as alternate function pull-up.\r\n        (##) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()\r\n             and HAL_SMARTCARD_Receive_IT() APIs):\r\n            (+++) Configure the USARTx interrupt priority.\r\n            (+++) Enable the NVIC USART IRQ handle.\r\n            (+++) The specific USART interrupts (Transmission complete interrupt, \r\n                  RXNE interrupt and Error Interrupts) will be managed using the macros\r\n                  __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.\r\n        (##) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()\r\n             and HAL_SMARTCARD_Receive_DMA() APIs):\r\n            (+++) Declare a DMA handle structure for the Tx/Rx stream.\r\n            (+++) Enable the DMAx interface clock.\r\n            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.                \r\n            (+++) Configure the DMA Tx/Rx Stream.\r\n            (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.\r\n            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.\r\n\r\n    (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,\r\n        the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission\r\n        error enabling or disabling in the hsc Init structure.\r\n        \r\n    (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...)\r\n        in the hsc AdvancedInit structure.\r\n\r\n    (#) Initialize the SMARTCARD associated USART registers by calling\r\n        the HAL_SMARTCARD_Init() API. \r\n    \r\n  [..]\r\n    (@) HAL_SMARTCARD_Init() API also configure also the low level Hardware GPIO, CLOCK, CORTEX...etc) by \r\n        calling the customized HAL_SMARTCARD_MspInit() API.\r\n          \r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup SMARTCARD SMARTCARD\r\n  * @brief HAL USART SMARTCARD module driver\r\n  * @{\r\n  */\r\n#ifdef HAL_SMARTCARD_MODULE_ENABLED\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants\r\n * @{\r\n */\r\n#define TEACK_REACK_TIMEOUT               1000U\r\n#define HAL_SMARTCARD_TXDMA_TIMEOUTVALUE  22000U\r\n#define USART_CR1_FIELDS      ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \\\r\n                                          USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8))\r\n#define USART_CR2_CLK_FIELDS  ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL))   \r\n#define USART_CR2_FIELDS      ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP))\r\n#define USART_CR3_FIELDS      ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT))  \r\n/**\r\n  * @}\r\n  */\r\n/* Private macros -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/** @addtogroup SMARTCARD_Private_Functions\r\n  * @{\r\n  */\r\nstatic void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);\r\nstatic void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);\r\nstatic void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);\r\nstatic void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma);\r\nstatic void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc);\r\nstatic HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);\r\nstatic HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsc);\r\nstatic HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc);\r\nstatic HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc);\r\nstatic void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsc);\r\nstatic void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc);\r\nstatic void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsc);\r\n/**\r\n  * @}\r\n  */\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup SMARTCARD_Exported_Functions_Group1 SmartCard Initialization and de-initialization functions\r\n  *  @brief    Initialization and Configuration functions\r\n  *\r\n@verbatim\r\n===============================================================================\r\n            ##### Initialization and Configuration functions #####\r\n ===============================================================================\r\n  [..]\r\n  This subsection provides a set of functions allowing to initialize the USART\r\n  associated to the SmartCard.\r\n      (+) These parameters can be configured: \r\n        (++) Baud Rate\r\n        (++) Parity: parity should be enabled,\r\n             Frame Length is fixed to 8 bits plus parity.\r\n        (++) Receiver/transmitter modes\r\n        (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)\r\n        (++) Prescaler value\r\n        (++) Guard bit time \r\n        (++) NACK enabling or disabling on transmission error               \r\n\r\n      (+) The following advanced features can be configured as well:\r\n        (++) TX and/or RX pin level inversion\r\n        (++) data logical level inversion\r\n        (++) RX and TX pins swap\r\n        (++) RX overrun detection disabling\r\n        (++) DMA disabling on RX error\r\n        (++) MSB first on communication line\r\n        (++) Time out enabling (and if activated, timeout value)\r\n        (++) Block length\r\n        (++) Auto-retry counter       \r\n        \r\n    [..]                                                  \r\n    The HAL_SMARTCARD_Init() API follow respectively the USART (a)synchronous configuration procedures \r\n    (details for the procedures are available in reference manual).\r\n\r\n@endverbatim\r\n\r\n  The USART frame format is given in the following table:\r\n\r\n     +---------------------------------------------------------------+\r\n     | M1M0 bits |  PCE bit  |            USART frame                |\r\n     |-----------------------|---------------------------------------|\r\n     |     01    |    1      |    | SB | 8 bit data | PB | STB |     |\r\n     +---------------------------------------------------------------+\r\n\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief Initializes the SMARTCARD mode according to the specified\r\n  *         parameters in the SMARTCARD_InitTypeDef and create the associated handle .\r\n  * @param hsc: SMARTCARD handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)\r\n{\r\n  /* Check the SMARTCARD handle allocation */\r\n  if(hsc == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));\r\n  \r\n  if(hsc->gState == HAL_SMARTCARD_STATE_RESET)\r\n  { \r\n    /* Allocate lock resource and initialize it */\r\n    hsc->Lock = HAL_UNLOCKED; \r\n    /* Init the low level hardware : GPIO, CLOCK, CORTEX */\r\n    HAL_SMARTCARD_MspInit(hsc);\r\n  }\r\n  \r\n  hsc->gState = HAL_SMARTCARD_STATE_BUSY;\r\n\r\n  /* Disable the Peripheral */\r\n  __HAL_SMARTCARD_DISABLE(hsc);\r\n\r\n  /* Set the SMARTCARD Communication parameters */\r\n  SMARTCARD_SetConfig(hsc);\r\n\r\n  if(hsc->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT)\r\n  {\r\n    SMARTCARD_AdvFeatureConfig(hsc);\r\n  }\r\n\r\n  /* In SmartCard mode, the following bits must be kept cleared: \r\n  - LINEN in the USART_CR2 register,\r\n  - HDSEL and IREN  bits in the USART_CR3 register.*/\r\n  CLEAR_BIT(hsc->Instance->CR2, USART_CR2_LINEN);\r\n  CLEAR_BIT(hsc->Instance->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));\r\n\r\n  /* set the USART in SMARTCARD mode */\r\n  SET_BIT(hsc->Instance->CR3, USART_CR3_SCEN);\r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_SMARTCARD_ENABLE(hsc);\r\n  \r\n  /* TEACK and/or REACK to check before moving hsc->State to Ready */\r\n  return (SMARTCARD_CheckIdleState(hsc));\r\n}\r\n\r\n/**\r\n  * @brief DeInitializes the SMARTCARD peripheral \r\n  * @param hsc: SMARTCARD handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)\r\n{\r\n  /* Check the SMARTCARD handle allocation */\r\n  if(hsc == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));\r\n\r\n  hsc->gState = HAL_SMARTCARD_STATE_BUSY;\r\n\r\n  /* DeInit the low level hardware */\r\n  HAL_SMARTCARD_MspDeInit(hsc);\r\n\r\n  hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;\r\n  hsc->gState = HAL_SMARTCARD_STATE_RESET;\r\n  hsc->RxState = HAL_SMARTCARD_STATE_RESET;\r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hsc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief SMARTCARD MSP Init\r\n  * @param hsc: SMARTCARD handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hsc);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_SMARTCARD_MspInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief SMARTCARD MSP DeInit\r\n  * @param hsc: SMARTCARD handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hsc);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_SMARTCARD_MspDeInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions \r\n  *  @brief   SMARTCARD Transmit and Receive functions \r\n  *\r\n@verbatim   \r\n ===============================================================================\r\n                      ##### IO operation functions #####\r\n ===============================================================================  \r\n    This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.\r\n\r\n    (#) There are two modes of transfer:\r\n       (+) Blocking mode: The communication is performed in polling mode. \r\n            The HAL status of all data processing is returned by the same function \r\n            after finishing transfer.  \r\n       (+) No-Blocking mode: The communication is performed using Interrupts \r\n           or DMA, These API's return the HAL status.\r\n           The end of the data processing will be indicated through the \r\n           dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when \r\n           using DMA mode.\r\n           The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks \r\n           will be executed respectively at the end of the Transmit or Receive process\r\n           The HAL_SMARTCARD_ErrorCallback()user callback will be executed when a communication error is detected\r\n\r\n    (#) Blocking mode API's are :\r\n        (+) HAL_SMARTCARD_Transmit()\r\n        (+) HAL_SMARTCARD_Receive() \r\n        \r\n    (#) Non-Blocking mode API's with Interrupt are :\r\n        (+) HAL_SMARTCARD_Transmit_IT()\r\n        (+) HAL_SMARTCARD_Receive_IT()\r\n        (+) HAL_SMARTCARD_IRQHandler()\r\n        (+) SMARTCARD_Transmit_IT()\r\n        (+) SMARTCARD_Receive_IT()    \r\n\r\n    (#) No-Blocking mode functions with DMA are :\r\n        (+) HAL_SMARTCARD_Transmit_DMA()\r\n        (+) HAL_SMARTCARD_Receive_DMA()\r\n\r\n    (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:\r\n        (+) HAL_SMARTCARD_TxCpltCallback()\r\n        (+) HAL_SMARTCARD_RxCpltCallback()\r\n        (+) HAL_SMARTCARD_ErrorCallback()\r\n      \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief Send an amount of data in blocking mode \r\n  * @param hsc: SMARTCARD handle\r\n  * @param pData: pointer to data buffer\r\n  * @param Size: amount of data to be sent\r\n  * @param Timeout: Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0U;\r\n  \r\n  if(hsc->gState == HAL_SMARTCARD_STATE_READY)\r\n  {\r\n    if((pData == NULL) || (Size == 0U)) \r\n    {\r\n      return  HAL_ERROR;\r\n    }\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(hsc);\r\n    hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;    \r\n    hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;\r\n    \r\n    /* Init tickstart for timeout managment*/\r\n    tickstart = HAL_GetTick();\r\n    \r\n    hsc->TxXferSize = Size;\r\n    hsc->TxXferCount = Size;\r\n    while(hsc->TxXferCount > 0U)\r\n    {\r\n      hsc->TxXferCount--;\r\n      if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)  \r\n      { \r\n        return HAL_TIMEOUT;\r\n      }\r\n      hsc->Instance->TDR = (*pData++ & (uint8_t)0xFFU);\r\n    }\r\n    if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)  \r\n    { \r\n      return HAL_TIMEOUT;\r\n    }\r\n    \r\n    /* At end of Tx process, restore hsc->gState to Ready */\r\n    hsc->gState = HAL_SMARTCARD_STATE_READY;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hsc);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Receive an amount of data in blocking mode \r\n  * @param hsc: SMARTCARD handle\r\n  * @param pData: pointer to data buffer\r\n  * @param Size: amount of data to be received\r\n  * @param Timeout: Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0U;\r\n  \r\n  if(hsc->RxState == HAL_SMARTCARD_STATE_READY)\r\n  {\r\n    if((pData == NULL) || (Size == 0U)) \r\n    {\r\n      return  HAL_ERROR;\r\n    }\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(hsc);\r\n    \r\n    hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;\r\n    hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;\r\n    \r\n    /* Init tickstart for timeout managment*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    hsc->RxXferSize = Size;\r\n    hsc->RxXferCount = Size;\r\n    /* Check the remain data to be received */\r\n    while(hsc->RxXferCount > 0U)\r\n    {\r\n      hsc->RxXferCount--;\r\n      if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)  \r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n      *pData++ = (uint8_t)(hsc->Instance->RDR & (uint8_t)0x00FFU);\r\n    }\r\n\r\n    /* At end of Rx process, restore hsc->RxState to Ready */\r\n    hsc->RxState = HAL_SMARTCARD_STATE_READY;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hsc);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Send an amount of data in interrupt mode \r\n  * @param hsc: SMARTCARD handle\r\n  * @param pData: pointer to data buffer\r\n  * @param Size: amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)\r\n{\r\n  /* Check that a Tx process is not already ongoing */\r\n  if(hsc->gState == HAL_SMARTCARD_STATE_READY)\r\n  {\r\n    if((pData == NULL) || (Size == 0U)) \r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(hsc);\r\n\r\n    hsc->pTxBuffPtr = pData;\r\n    hsc->TxXferSize = Size;\r\n    hsc->TxXferCount = Size;\r\n\r\n    hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;\r\n    hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hsc);\r\n\r\n    /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */\r\n    CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);\r\n\r\n    /* Enable the SMARTCARD Transmit Complete Interrupt */\r\n    CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TCIE);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Receive an amount of data in interrupt mode \r\n  * @param hsc: SMARTCARD handle\r\n  * @param pData: pointer to data buffer\r\n  * @param Size: amount of data to be received\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)\r\n{\r\n  /* Check that a Rx process is not already ongoing */ \r\n  if(hsc->RxState == HAL_SMARTCARD_STATE_READY) \r\n  {\r\n    if((pData == NULL) || (Size == 0U)) \r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(hsc);\r\n\r\n    hsc->pRxBuffPtr = pData;\r\n    hsc->RxXferSize = Size;\r\n    hsc->RxXferCount = Size;\r\n\r\n    hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;\r\n    hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hsc);\r\n    \r\n    /* Enable the SMARTCARD Parity Error Interrupt */\r\n    SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE);\r\n\r\n    /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */\r\n    SET_BIT(hsc->Instance->CR3, USART_CR3_EIE);\r\n\r\n    /* Enable the SMARTCARD Data Register not empty Interrupt */\r\n    SET_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Send an amount of data in DMA mode \r\n  * @param hsc: SMARTCARD handle\r\n  * @param pData: pointer to data buffer\r\n  * @param Size: amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)\r\n{\r\n  uint32_t *tmp;\r\n  \r\n  /* Check that a Tx process is not already ongoing */\r\n  if(hsc->gState == HAL_SMARTCARD_STATE_READY)\r\n  {\r\n    if((pData == NULL) || (Size == 0U)) \r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(hsc);\r\n\r\n    hsc->pTxBuffPtr = pData;\r\n    hsc->TxXferSize = Size;\r\n    hsc->TxXferCount = Size;\r\n\r\n    hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;\r\n    hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;\r\n\r\n    /* Set the SMARTCARD DMA transfer complete callback */\r\n    hsc->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;\r\n\r\n    /* Set the SMARTCARD error callback */\r\n    hsc->hdmatx->XferErrorCallback = SMARTCARD_DMAError;\r\n    \r\n    /* Set the DMA abort callback */\r\n    hsc->hdmatx->XferAbortCallback = NULL;\r\n\r\n    /* Enable the SMARTCARD transmit DMA Stream */\r\n    tmp = (uint32_t*)&pData;\r\n    HAL_DMA_Start_IT(hsc->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsc->Instance->TDR, Size);\r\n    \r\n\t/* Clear the TC flag in the SR register by writing 0 to it */\r\n    __HAL_SMARTCARD_CLEAR_IT(hsc, SMARTCARD_FLAG_TC);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hsc);\r\n\r\n    /* Enable the DMA transfer for transmit request by setting the DMAT bit\r\n       in the SMARTCARD associated USART CR3 register */\r\n    SET_BIT(hsc->Instance->CR3, USART_CR3_DMAT);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Receive an amount of data in DMA mode \r\n  * @param hsc: SMARTCARD handle\r\n  * @param pData: pointer to data buffer\r\n  * @param Size: amount of data to be received\r\n  * @note   The SMARTCARD-associated USART parity is enabled (PCE = 1), \r\n  *         the received data contain the parity bit (MSB position)   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)\r\n{\r\n  uint32_t *tmp;\r\n  \r\n  /* Check that a Rx process is not already ongoing */\r\n  if(hsc->RxState == HAL_SMARTCARD_STATE_READY)\r\n  {\r\n    if((pData == NULL) || (Size == 0U)) \r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(hsc);\r\n\r\n    hsc->pRxBuffPtr = pData;\r\n    hsc->RxXferSize = Size;\r\n\r\n    hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;\r\n    hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;\r\n\r\n    /* Set the SMARTCARD DMA transfer complete callback */\r\n    hsc->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;\r\n\r\n    /* Set the SMARTCARD DMA error callback */\r\n    hsc->hdmarx->XferErrorCallback = SMARTCARD_DMAError;\r\n    \r\n    /* Set the DMA abort callback */\r\n    hsc->hdmatx->XferAbortCallback = NULL;\r\n\r\n    /* Enable the DMA Stream */\r\n    tmp = (uint32_t*)&pData;\r\n    HAL_DMA_Start_IT(hsc->hdmarx, (uint32_t)&hsc->Instance->RDR, *(uint32_t*)tmp, Size);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hsc);\r\n    \r\n    /* Enable the SMARTCARD Parity Error Interrupt */\r\n    SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE);\r\n\r\n    /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */\r\n    SET_BIT(hsc->Instance->CR3, USART_CR3_EIE);\r\n\r\n    /* Enable the DMA transfer for the receiver request by setting the DMAR bit \r\n    in the SMARTCARD associated USART CR3 register */\r\n    SET_BIT(hsc->Instance->CR3, USART_CR3_DMAR);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n    \r\n/**\r\n  * @brief SMARTCARD interrupt requests handling.\r\n  * @param hsc: SMARTCARD handle\r\n  * @retval None\r\n  */\r\nvoid HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)\r\n{\r\n  uint32_t isrflags   = READ_REG(hsc->Instance->ISR);\r\n  uint32_t cr1its     = READ_REG(hsc->Instance->CR1);\r\n  uint32_t cr3its     = READ_REG(hsc->Instance->CR3);\r\n  uint32_t dmarequest = 0x00U;\r\n  uint32_t errorflags = 0x00U;\r\n\r\n  /* If no error occurs */\r\n  errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));\r\n  if(errorflags == RESET)\r\n  {\r\n    /* SMARTCARD in mode Receiver -------------------------------------------------*/\r\n    if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))\r\n    {\r\n      SMARTCARD_Receive_IT(hsc);\r\n      return;\r\n    }\r\n  }\r\n\r\n  /* If some errors occur */\r\n  if((errorflags != RESET) && ((cr3its & (USART_CR3_EIE | USART_CR1_PEIE)) != RESET))\r\n  {\r\n    /* SMARTCARD parity error interrupt occurred ---------------------------*/\r\n    if(((isrflags & SMARTCARD_FLAG_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))\r\n    { \r\n      hsc->ErrorCode |= HAL_SMARTCARD_ERROR_PE;\r\n    }\r\n\r\n    /* SMARTCARD frame error interrupt occurred ----------------------------*/\r\n    if(((isrflags & SMARTCARD_FLAG_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))\r\n    { \r\n      hsc->ErrorCode |= HAL_SMARTCARD_ERROR_FE;\r\n    }\r\n\r\n    /* SMARTCARD noise error interrupt occurred ----------------------------*/\r\n    if(((isrflags & SMARTCARD_FLAG_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))\r\n    { \r\n      hsc->ErrorCode |= HAL_SMARTCARD_ERROR_NE;\r\n    }\r\n\r\n    /* SMARTCARD Over-Run interrupt occurred -------------------------------*/\r\n    if(((isrflags & SMARTCARD_FLAG_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))\r\n    { \r\n      hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;\r\n    }\r\n    /* Call the Error call Back in case of Errors */\r\n    if(hsc->ErrorCode != HAL_SMARTCARD_ERROR_NONE)\r\n    {\r\n      /* SMARTCARD in mode Receiver -----------------------------------------------*/\r\n      if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))\r\n      {\r\n        SMARTCARD_Receive_IT(hsc);\r\n      }\r\n\r\n      /* If Overrun error occurs, or if any error occurs in DMA mode reception,\r\n         consider error as blocking */\r\n      dmarequest = HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR);\r\n      if(((hsc->ErrorCode & HAL_SMARTCARD_ERROR_ORE) != RESET) || dmarequest)\r\n      {\r\n        /* Blocking error : transfer is aborted\r\n          Set the SMARTCARD state ready to be able to start again the process,\r\n          Disable Rx Interrupts, and disable Rx DMA request, if ongoing */\r\n        SMARTCARD_EndRxTransfer(hsc);\r\n        /* Disable the SMARTCARD DMA Rx request if enabled */\r\n        if (HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))\r\n        {\r\n          CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);\r\n\r\n          /* Abort the SMARTCARD DMA Rx channel */\r\n          if(hsc->hdmarx != NULL)\r\n          {\r\n            /* Set the SMARTCARD DMA Abort callback : \r\n              will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */\r\n            hsc->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError;\r\n\r\n           if(HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK)\r\n            {\r\n              /* Call Directly XferAbortCallback function in case of error */\r\n              hsc->hdmarx->XferAbortCallback(hsc->hdmarx);\r\n            }\r\n          }\r\n          else\r\n          {\r\n            /* Call user error callback */\r\n            HAL_SMARTCARD_ErrorCallback(hsc);\r\n          }\r\n        }\r\n        else\r\n        {\r\n          /* Call user error callback */\r\n          HAL_SMARTCARD_ErrorCallback(hsc);\r\n        }\r\n      }\r\n      else\r\n      {\r\n        /* Call user error callback */\r\n        HAL_SMARTCARD_ErrorCallback(hsc);\r\n        hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;\r\n      }\r\n    }\r\n    return;\r\n  } /* End if some error occurs */\r\n  \r\n  /* SMARTCARD in mode Transmitter -------------------------------------------*/\r\n  if(((isrflags & SMARTCARD_FLAG_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))\r\n  {\r\n    SMARTCARD_Transmit_IT(hsc);\r\n    return;\r\n  }\r\n  \r\n  /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/\r\n  if(((isrflags & SMARTCARD_FLAG_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))\r\n  {\r\n    /* Disable the SMARTCARD Transmit Complete Interrupt */   \r\n    CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TCIE);\r\n\r\n    /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */\r\n    CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);\r\n\r\n    /* Tx process is ended, restore hsmartcard->gState to Ready */\r\n    hsc->gState = HAL_SMARTCARD_STATE_READY;\r\n\r\n    HAL_SMARTCARD_TxCpltCallback(hsc);\r\n    \r\n    return;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Tx Transfer completed callbacks\r\n  * @param hsc: SMARTCARD handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hsc);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_SMARTCARD_TxCpltCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief Rx Transfer completed callbacks\r\n  * @param hsc: SMARTCARD handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hsc);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_SMARTCARD_TxCpltCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief SMARTCARD error callbacks\r\n  * @param hsc: SMARTCARD handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hsc);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_SMARTCARD_ErrorCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State functions \r\n  *  @brief   SMARTCARD State functions \r\n  *\r\n@verbatim   \r\n ===============================================================================\r\n                ##### Peripheral State and Errors functions #####\r\n ===============================================================================\r\n    [..]\r\n    This subsection provides a set of functions allowing to initialize the SMARTCARD.\r\n     (+) HAL_SMARTCARD_GetState() API is helpful to check in run-time the state of the SMARTCARD peripheral \r\n     (+) SMARTCARD_SetConfig() API configures the SMARTCARD peripheral  \r\n     (+) SMARTCARD_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization \r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n\r\n/**\r\n  * @brief return the SMARTCARD state\r\n  * @param hsc: SMARTCARD handle\r\n  * @retval HAL state\r\n  */\r\nHAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc)\r\n{\r\n  uint32_t temp1= 0x00U, temp2 = 0x00U;\r\n  temp1 = hsc->gState;\r\n  temp2 = hsc->RxState;\r\n  \r\n  return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2);\r\n}\r\n\r\n/**\r\n  * @brief  Return the SMARTCARD error code\r\n  * @param  hsc : pointer to a SMARTCARD_HandleTypeDef structure that contains\r\n  *              the configuration information for the specified SMARTCARD.\r\n  * @retval SMARTCARD Error Code\r\n  */\r\nuint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc)\r\n{\r\n  return hsc->ErrorCode;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @brief Send an amount of data in non blocking mode \r\n  * @param hsc: SMARTCARD handle.\r\n  *         Function called under interruption only, once\r\n  *         interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()      \r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc)\r\n{\r\n  if(hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX)\r\n  {\r\n    if(hsc->TxXferCount == 0)\r\n    {\r\n      /* Disable the SMARTCARD Transmit Complete Interrupt */\r\n      CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TXEIE);\r\n      \r\n      /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */\r\n      CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);\r\n      \r\n      /* Tx process is ended, restore hsmartcard->gState to Ready */\r\n      hsc->gState = HAL_SMARTCARD_STATE_READY;\r\n    }\r\n    \r\n    HAL_SMARTCARD_TxCpltCallback(hsc);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {    \r\n    hsc->Instance->TDR = (*hsc->pTxBuffPtr++ & (uint8_t)0xFFU);\r\n    hsc->TxXferCount--;\r\n    \r\n    return HAL_OK;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Receive an amount of data in non blocking mode \r\n  * @param hsc: SMARTCARD handle.\r\n  *         Function called under interruption only, once\r\n  *         interruptions have been enabled by HAL_SMARTCARD_Receive_IT()      \r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc)\r\n{\r\n  /* Check that a Rx process is ongoing */\r\n  if(hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX) \r\n  {\r\n    *hsc->pRxBuffPtr++ = (uint8_t)(hsc->Instance->RDR & (uint8_t)0xFFU);\r\n    \r\n    if(--hsc->RxXferCount == 0)\r\n    {\r\n      CLEAR_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE);\r\n      \r\n      /* Disable the SMARTCARD Parity Error Interrupt */\r\n      CLEAR_BIT(hsc->Instance->CR1, USART_CR1_PEIE);\r\n      \r\n      /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */\r\n      CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);\r\n      \r\n      hsc->RxState = HAL_SMARTCARD_STATE_READY;\r\n      \r\n      HAL_SMARTCARD_RxCpltCallback(hsc);\r\n      \r\n      return HAL_OK;\r\n    }\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Configure the SMARTCARD associated USART peripheral \r\n  * @param hsc: SMARTCARD handle\r\n  * @retval None\r\n  */\r\nstatic void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc)\r\n{\r\n  uint32_t tmpreg      = 0x00000000U;\r\n  uint32_t clocksource = 0x00000000U;\r\n  \r\n  /* Check the parameters */ \r\n  assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));\r\n  assert_param(IS_SMARTCARD_BAUDRATE(hsc->Init.BaudRate)); \r\n  assert_param(IS_SMARTCARD_WORD_LENGTH(hsc->Init.WordLength));  \r\n  assert_param(IS_SMARTCARD_STOPBITS(hsc->Init.StopBits));   \r\n  assert_param(IS_SMARTCARD_PARITY(hsc->Init.Parity));\r\n  assert_param(IS_SMARTCARD_MODE(hsc->Init.Mode));\r\n  assert_param(IS_SMARTCARD_POLARITY(hsc->Init.CLKPolarity));\r\n  assert_param(IS_SMARTCARD_PHASE(hsc->Init.CLKPhase));\r\n  assert_param(IS_SMARTCARD_LASTBIT(hsc->Init.CLKLastBit));    \r\n  assert_param(IS_SMARTCARD_ONE_BIT_SAMPLE(hsc->Init.OneBitSampling));\r\n  assert_param(IS_SMARTCARD_NACK(hsc->Init.NACKState));\r\n  assert_param(IS_SMARTCARD_TIMEOUT(hsc->Init.TimeOutEnable));\r\n  assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsc->Init.AutoRetryCount)); \r\n\r\n  /*-------------------------- USART CR1 Configuration -----------------------*/\r\n  /* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity).\r\n   * Oversampling is forced to 16 (OVER8 = 0).\r\n   * Configure the Parity and Mode: \r\n   *  set PS bit according to hsc->Init.Parity value\r\n   *  set TE and RE bits according to hsc->Init.Mode value */\r\n  tmpreg = (uint32_t) hsc->Init.Parity | hsc->Init.Mode;\r\n  /* in case of TX-only mode, if NACK is enabled, the USART must be able to monitor \r\n     the bidirectional line to detect a NACK signal in case of parity error. \r\n     Therefore, the receiver block must be enabled as well (RE bit must be set). */\r\n  if((hsc->Init.Mode == SMARTCARD_MODE_TX) && (hsc->Init.NACKState == SMARTCARD_NACK_ENABLE))\r\n  {\r\n    tmpreg |= USART_CR1_RE;   \r\n  }\r\n  tmpreg |= (uint32_t) hsc->Init.WordLength;\r\n  MODIFY_REG(hsc->Instance->CR1, USART_CR1_FIELDS, tmpreg);\r\n\r\n  /*-------------------------- USART CR2 Configuration -----------------------*/\r\n  /* Stop bits are forced to 1.5 (STOP = 11) */\r\n  tmpreg = hsc->Init.StopBits;\r\n  /* Synchronous mode is activated by default */\r\n  tmpreg |= (uint32_t) USART_CR2_CLKEN | hsc->Init.CLKPolarity; \r\n  tmpreg |= (uint32_t) hsc->Init.CLKPhase | hsc->Init.CLKLastBit;\r\n  tmpreg |= (uint32_t) hsc->Init.TimeOutEnable;\r\n  MODIFY_REG(hsc->Instance->CR2, USART_CR2_FIELDS, tmpreg); \r\n    \r\n  /*-------------------------- USART CR3 Configuration -----------------------*/\r\n  /* Configure \r\n   * - one-bit sampling method versus three samples' majority rule \r\n   *   according to hsc->Init.OneBitSampling \r\n   * - NACK transmission in case of parity error according \r\n   *   to hsc->Init.NACKEnable   \r\n   * - autoretry counter according to hsc->Init.AutoRetryCount     */\r\n  tmpreg =  (uint32_t) hsc->Init.OneBitSampling | hsc->Init.NACKState;\r\n  tmpreg |= (uint32_t) (hsc->Init.AutoRetryCount << SMARTCARD_CR3_SCARCNT_LSB_POS);\r\n  MODIFY_REG(hsc->Instance-> CR3,USART_CR3_FIELDS, tmpreg);\r\n  \r\n  /*-------------------------- USART GTPR Configuration ----------------------*/\r\n  tmpreg = (uint32_t) (hsc->Init.Prescaler | (hsc->Init.GuardTime << SMARTCARD_GTPR_GT_LSB_POS));\r\n  MODIFY_REG(hsc->Instance->GTPR, (uint32_t)(USART_GTPR_GT|USART_GTPR_PSC), tmpreg); \r\n  \r\n  /*-------------------------- USART RTOR Configuration ----------------------*/ \r\n  tmpreg =   (uint32_t) (hsc->Init.BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS);\r\n  if(hsc->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE)\r\n  {\r\n    assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsc->Init.TimeOutValue));\r\n    tmpreg |=  (uint32_t) hsc->Init.TimeOutValue;\r\n  }\r\n  MODIFY_REG(hsc->Instance->RTOR, (USART_RTOR_RTO|USART_RTOR_BLEN), tmpreg);\r\n  \r\n  /*-------------------------- USART BRR Configuration -----------------------*/\r\n  SMARTCARD_GETCLOCKSOURCE(hsc, clocksource);\r\n  switch (clocksource)\r\n  {\r\n  case SMARTCARD_CLOCKSOURCE_PCLK1: \r\n    hsc->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsc->Init.BaudRate/2))/ hsc->Init.BaudRate);\r\n    break;\r\n  case SMARTCARD_CLOCKSOURCE_PCLK2: \r\n    hsc->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hsc->Init.BaudRate/2))/ hsc->Init.BaudRate);\r\n    break;\r\n  case SMARTCARD_CLOCKSOURCE_HSI: \r\n    hsc->Instance->BRR = (uint16_t)((HSI_VALUE + (hsc->Init.BaudRate/2))/ hsc->Init.BaudRate); \r\n    break; \r\n  case SMARTCARD_CLOCKSOURCE_SYSCLK:  \r\n    hsc->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hsc->Init.BaudRate/2))/ hsc->Init.BaudRate);\r\n    break;  \r\n  case SMARTCARD_CLOCKSOURCE_LSE:                \r\n    hsc->Instance->BRR = (uint16_t)((LSE_VALUE + (hsc->Init.BaudRate/2))/ hsc->Init.BaudRate); \r\n    break;\r\n  default:\r\n    break;\r\n  } \r\n}\r\n\r\n/**\r\n  * @brief Check the SMARTCARD Idle State\r\n  * @param hsc: SMARTCARD handle\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsc)\r\n{\r\n  uint32_t tickstart = 0U;\r\n  \r\n  /* Initialize the SMARTCARD ErrorCode */\r\n  hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;\r\n  \r\n  /* Init tickstart for timeout managment*/\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Check if the Transmitter is enabled */\r\n  if((hsc->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)\r\n  {\r\n    /* Wait until TEACK flag is set */\r\n    if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, USART_ISR_TEACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK)  \r\n    { \r\n      return HAL_TIMEOUT;\r\n    } \r\n  }\r\n  /* Check if the Receiver is enabled */\r\n  if((hsc->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)\r\n  {\r\n    /* Wait until REACK flag is set */\r\n    if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, USART_ISR_REACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK)  \r\n    { \r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hsc);\r\n        \r\n  /* Initialize the SMARTCARD state*/\r\n  hsc->gState= HAL_SMARTCARD_STATE_READY;\r\n  hsc->RxState= HAL_SMARTCARD_STATE_READY;\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Configure the SMARTCARD associated USART peripheral advanced features \r\n  * @param hsc: SMARTCARD handle  \r\n  * @retval None\r\n  */\r\nstatic void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsc)\r\n{  \r\n  /* Check whether the set of advanced features to configure is properly set */ \r\n  assert_param(IS_SMARTCARD_ADVFEATURE_INIT(hsc->AdvancedInit.AdvFeatureInit));\r\n  \r\n  /* if required, configure TX pin active level inversion */\r\n  if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXINVERT_INIT))\r\n  {\r\n    assert_param(IS_SMARTCARD_ADVFEATURE_TXINV(hsc->AdvancedInit.TxPinLevelInvert));\r\n    MODIFY_REG(hsc->Instance->CR2, USART_CR2_TXINV, hsc->AdvancedInit.TxPinLevelInvert);\r\n  }\r\n  \r\n  /* if required, configure RX pin active level inversion */\r\n  if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXINVERT_INIT))\r\n  {\r\n    assert_param(IS_SMARTCARD_ADVFEATURE_RXINV(hsc->AdvancedInit.RxPinLevelInvert));\r\n    MODIFY_REG(hsc->Instance->CR2, USART_CR2_RXINV, hsc->AdvancedInit.RxPinLevelInvert);\r\n  }\r\n  \r\n  /* if required, configure data inversion */\r\n  if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DATAINVERT_INIT))\r\n  {\r\n    assert_param(IS_SMARTCARD_ADVFEATURE_DATAINV(hsc->AdvancedInit.DataInvert));\r\n    MODIFY_REG(hsc->Instance->CR2, USART_CR2_DATAINV, hsc->AdvancedInit.DataInvert);\r\n  }\r\n  \r\n  /* if required, configure RX/TX pins swap */\r\n  if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_SWAP_INIT))\r\n  {\r\n    assert_param(IS_SMARTCARD_ADVFEATURE_SWAP(hsc->AdvancedInit.Swap));\r\n    MODIFY_REG(hsc->Instance->CR2, USART_CR2_SWAP, hsc->AdvancedInit.Swap);\r\n  }\r\n  \r\n  /* if required, configure RX overrun detection disabling */\r\n  if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT))\r\n  {\r\n    assert_param(IS_SMARTCARD_OVERRUN(hsc->AdvancedInit.OverrunDisable));  \r\n    MODIFY_REG(hsc->Instance->CR3, USART_CR3_OVRDIS, hsc->AdvancedInit.OverrunDisable);\r\n  }\r\n  \r\n  /* if required, configure DMA disabling on reception error */\r\n  if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT))\r\n  {\r\n    assert_param(IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(hsc->AdvancedInit.DMADisableonRxError));   \r\n    MODIFY_REG(hsc->Instance->CR3, USART_CR3_DDRE, hsc->AdvancedInit.DMADisableonRxError);\r\n  }\r\n  \r\n  /* if required, configure MSB first on communication line */  \r\n  if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_MSBFIRST_INIT))\r\n  {\r\n    assert_param(IS_SMARTCARD_ADVFEATURE_MSBFIRST(hsc->AdvancedInit.MSBFirst));   \r\n    MODIFY_REG(hsc->Instance->CR2, USART_CR2_MSBFIRST, hsc->AdvancedInit.MSBFirst);\r\n  }\r\n}\r\n  \r\n/**\r\n  * @brief  This function handles SMARTCARD Communication Timeout.\r\n  * @param  hsc SMARTCARD handle\r\n  * @param  Flag specifies the SMARTCARD flag to check.\r\n  * @param  Status The new Flag status (SET or RESET).\r\n  * @param  Tickstart Tick start value\r\n  * @param  Timeout Timeout duration\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)\r\n{\r\n  /* Wait until flag is set */\r\n  while((__HAL_SMARTCARD_GET_FLAG(hsc, Flag) ? SET : RESET) == Status)\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))\r\n      {\r\n        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */\r\n        CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TXEIE);\r\n        CLEAR_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE);\r\n        __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_PE);\r\n        __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);\r\n        CLEAR_BIT(hsc->Instance->CR1, USART_CR1_PEIE);\r\n        CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);\r\n        \r\n        hsc->gState= HAL_SMARTCARD_STATE_READY;\r\n        hsc->RxState= HAL_SMARTCARD_STATE_READY;\r\n        \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hsc);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/*\r\n  * @brief  End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).\r\n  * @param  hsc: SMARTCARD handle.\r\n  * @retval None\r\n  */\r\nstatic void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsc)\r\n{\r\n  /* Disable TXEIE and TCIE interrupts */\r\n  CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));\r\n  \r\n  /* At end of Tx process, restore hsc->gState to Ready */\r\n  hsc->gState = HAL_SMARTCARD_STATE_READY;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  End ongoing Rx transfer on SMARTCARD peripheral (following error detection or Reception completion).\r\n  * @param  hsc: SMARTCARD handle.\r\n  * @retval None\r\n  */\r\nstatic void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc)\r\n{\r\n  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\r\n  CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r\n  CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);\r\n  \r\n  /* At end of Rx process, restore hsc->RxState to Ready */\r\n  hsc->RxState = HAL_SMARTCARD_STATE_READY;\r\n}\r\n\r\n/**\r\n  * @brief DMA SMARTCARD transmit process complete callback \r\n  * @param hdma: DMA handle\r\n  * @retval None\r\n  */\r\nstatic void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)     \r\n{ \r\n  SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  hsc->TxXferCount = 0;\r\n  \r\n  /* Disable the DMA transfer for transmit request by setting the DMAT bit\r\n  in the USART CR3 register */\r\n  CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);\r\n  \r\n  /* Enable the SMARTCARD Transmit Complete Interrupt */   \r\n  SET_BIT(hsc->Instance->CR1, USART_CR1_TCIE);\r\n}\r\n\r\n/**\r\n  * @brief DMA SMARTCARD receive process complete callback \r\n  * @param hdma: DMA handle\r\n  * @retval None\r\n  */\r\nstatic void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)  \r\n{\r\n  SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  hsc->RxXferCount = 0;\r\n  \r\n  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\r\n  CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r\n  CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);\r\n  \r\n  /* Disable the DMA transfer for the receiver request by setting the DMAR bit \r\n     in the SMARTCARD associated USART CR3 register */\r\n  CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);\r\n  \r\n  /* At end of Rx process, restore hsc->RxState to Ready */\r\n  hsc->RxState = HAL_SMARTCARD_STATE_READY;\r\n  \r\n  HAL_SMARTCARD_RxCpltCallback(hsc);\r\n}\r\n\r\n/**\r\n  * @brief DMA SMARTCARD communication error callback \r\n  * @param hdma: DMA handle\r\n  * @retval None\r\n  */\r\nstatic void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)\r\n{\r\n  SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  hsc->RxXferCount = 0U;\r\n  hsc->TxXferCount = 0U;\r\n  hsc->ErrorCode = HAL_SMARTCARD_ERROR_DMA;\r\n  \r\n  /* Stop SMARTCARD DMA Tx request if ongoing */\r\n  if (  (hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX)\r\n      &&(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT)) )\r\n  {\r\n    SMARTCARD_EndTxTransfer(hsc);\r\n  }\r\n  \r\n  /* Stop SMARTCARD DMA Rx request if ongoing */\r\n  if (  (hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX)\r\n      &&(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR)) )\r\n  {\r\n    SMARTCARD_EndRxTransfer(hsc);\r\n  }\r\n  \r\n  HAL_SMARTCARD_ErrorCallback(hsc);\r\n}\r\n\r\n/**\r\n  * @brief DMA SMARTCARD communication abort callback, when call by HAL services on Error\r\n  *        (To be called at end of DMA Abort procedure following error occurrence).\r\n  * @param hdma: DMA handle.\r\n  * @retval None\r\n  */\r\nstatic void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)\r\n{\r\n  SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  hsc->RxXferCount = 0U;\r\n  hsc->TxXferCount = 0U;\r\n\r\n  HAL_SMARTCARD_ErrorCallback(hsc);\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_SMARTCARD_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smartcard_ex.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_smartcard_ex.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   SMARTCARD HAL module driver.\r\n  *\r\n  *          This file provides extended firmware functions to manage the following \r\n  *          functionalities of the SmartCard.\r\n  *           + Initialization and de-initialization functions\r\n  *           + Peripheral Control functions\r\n  @verbatim\r\n ===============================================================================\r\n                        ##### How to use this driver #####\r\n ===============================================================================\r\n    [..]\r\n    The Extended SMARTCARD HAL driver can be used as follow:\r\n\r\n    (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(), \r\n        then if required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, \r\n        auto-retry counter,...) in the hsc AdvancedInit structure.\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup SMARTCARDEx SMARTCARDEx\r\n  * @brief SMARTCARD Extended HAL module driver\r\n  * @{\r\n  */\r\n#ifdef HAL_SMARTCARD_MODULE_ENABLED\r\n    \r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup SMARTCARDEx_Exported_Functions SMARTCARDEx Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup SMARTCARDEx_Group1 Extended Peripheral Control functions\r\n  * @brief    Extended control functions\r\n  *\r\n@verbatim   \r\n ===============================================================================\r\n                      ##### Peripheral Control functions #####\r\n ===============================================================================\r\n    [..]\r\n    This subsection provides a set of functions allowing to initialize the SMARTCARD.\r\n     (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly \r\n     (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly  \r\n     (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature\r\n     (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief Update on the fly the SMARTCARD block length in RTOR register\r\n  * @param hsc: SMARTCARD handle\r\n  * @param BlockLength: SMARTCARD block length (8-bit long at most)  \r\n  * @retval None\r\n  */\r\nvoid HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsc, uint8_t BlockLength)\r\n{\r\n  MODIFY_REG(hsc->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS));\r\n}\r\n\r\n/**\r\n  * @brief Update on the fly the receiver timeout value in RTOR register\r\n  * @param hsc: SMARTCARD handle\r\n  * @param TimeOutValue: receiver timeout value in number of baud blocks. The timeout\r\n  *                     value must be less or equal to 0x0FFFFFFFF. \r\n  * @retval None\r\n  */\r\nvoid HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsc, uint32_t TimeOutValue)\r\n{\r\n  assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsc->Init.TimeOutValue));\r\n  MODIFY_REG(hsc->Instance->RTOR, USART_RTOR_RTO, TimeOutValue); \r\n}\r\n\r\n/**\r\n  * @brief Enable the SMARTCARD receiver timeout feature\r\n  * @param hsc: SMARTCARD handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsc)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hsc);\r\n\r\n  hsc->gState = HAL_SMARTCARD_STATE_BUSY;\r\n\r\n  /* Set the USART RTOEN bit */\r\n  hsc->Instance->CR2 |= USART_CR2_RTOEN;\r\n\r\n  hsc->gState = HAL_SMARTCARD_STATE_READY;\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hsc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Disable the SMARTCARD receiver timeout feature\r\n  * @param hsc: SMARTCARD handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsc)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hsc);\r\n\r\n  hsc->gState = HAL_SMARTCARD_STATE_BUSY;\r\n\r\n  /* Clear the USART RTOEN bit */\r\n  hsc->Instance->CR2 &= ~(USART_CR2_RTOEN);\r\n\r\n  hsc->gState = HAL_SMARTCARD_STATE_READY;\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hsc);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_SMARTCARD_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spdifrx.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_spdifrx.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   This file provides firmware functions to manage the following \r\n  *          functionalities of the SPDIFRX audio interface:\r\n  *           + Initialization and Configuration\r\n  *           + Data transfers functions\r\n  *           + DMA transfers management\r\n  *           + Interrupts and flags management \r\n  @verbatim\r\n ===============================================================================\r\n                  ##### How to use this driver #####\r\n ===============================================================================\r\n [..]\r\n    The SPDIFRX HAL driver can be used as follow:\r\n    \r\n    (#) Declare SPDIFRX_HandleTypeDef handle structure.\r\n    (#) Initialize the SPDIFRX low level resources by implement the HAL_SPDIFRX_MspInit() API:\r\n        (##) Enable the SPDIFRX interface clock.                      \r\n        (##) SPDIFRX pins configuration:\r\n            (+++) Enable the clock for the SPDIFRX GPIOs.\r\n            (+++) Configure these SPDIFRX pins as alternate function pull-up.\r\n        (##) NVIC configuration if you need to use interrupt process (HAL_SPDIFRX_ReceiveControlFlow_IT() and HAL_SPDIFRX_ReceiveDataFlow_IT() API's).\r\n            (+++) Configure the SPDIFRX interrupt priority.\r\n            (+++) Enable the NVIC SPDIFRX IRQ handle.\r\n        (##) DMA Configuration if you need to use DMA process (HAL_SPDIFRX_ReceiveDataFlow_DMA() and HAL_SPDIFRX_ReceiveControlFlow_DMA() API's).\r\n            (+++) Declare a DMA handle structure for the reception of the Data Flow channel.\r\n            (+++) Declare a DMA handle structure for the reception of the Control Flow channel.\r\n            (+++) Enable the DMAx interface clock.\r\n            (+++) Configure the declared DMA handle structure CtrlRx/DataRx with the required parameters.\r\n            (+++) Configure the DMA Channel.\r\n            (+++) Associate the initialized DMA handle to the SPDIFRX DMA CtrlRx/DataRx handle.\r\n            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the \r\n                DMA CtrlRx/DataRx channel.\r\n  \r\n   (#) Program the input selection, re-tries number, wait for activity, channel status selection, data format, stereo mode and masking of user bits\r\n       using HAL_SPDIFRX_Init() function.\r\n\r\n   -@- The specific SPDIFRX interrupts (RXNE/CSRNE and Error Interrupts) will be managed using the macros\r\n       __SPDIFRX_ENABLE_IT() and __SPDIFRX_DISABLE_IT() inside the receive process.\r\n   -@- Make sure that ck_spdif clock is configured. \r\n   \r\n   (#) Three operation modes are available within this driver :\r\n  \r\n   *** Polling mode for reception operation (for debug purpose) ***\r\n   ================================================================\r\n   [..]    \r\n     (+) Receive data flow in blocking mode using HAL_SPDIFRX_ReceiveDataFlow()\r\n         (+) Receive control flow of data in blocking mode using HAL_SPDIFRX_ReceiveControlFlow()\r\n   \r\n   *** Interrupt mode for reception operation ***\r\n   =========================================\r\n   [..]    \r\n     (+) Receive an amount of data (Data Flow) in non blocking mode using HAL_SPDIFRX_ReceiveDataFlow_IT() \r\n         (+) Receive an amount of data (Control Flow) in non blocking mode using HAL_SPDIFRX_ReceiveControlFlow_IT() \r\n     (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can \r\n         add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback \r\n     (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can \r\n         add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback\r\n     (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can \r\n         add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback\r\n\r\n   *** DMA mode for reception operation ***\r\n   ========================================\r\n   [..] \r\n     (+) Receive an amount of data (Data Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveDataFlow_DMA() \r\n         (+) Receive an amount of data (Control Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveControlFlow_DMA() \r\n     (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can \r\n         add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback \r\n     (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can \r\n         add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback\r\n     (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can \r\n         add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback\r\n     (+) Stop the DMA Transfer using HAL_SPDIFRX_DMAStop()\r\n\r\n   *** SPDIFRX HAL driver macros list ***\r\n   =============================================\r\n   [..]\r\n     Below the list of most used macros in USART HAL driver.\r\n      (+) __HAL_SPDIFRX_IDLE: Disable the specified SPDIFRX peripheral (IDEL State)\r\n      (+) __HAL_SPDIFRX_SYNC: Enable the synchronization state of the specified SPDIFRX peripheral (SYNC State) \r\n      (+) __HAL_SPDIFRX_RCV: Enable the receive state of the specified SPDIFRX peripheral (RCV State)\r\n      (+) __HAL_SPDIFRX_ENABLE_IT : Enable the specified SPDIFRX interrupts\r\n      (+) __HAL_SPDIFRX_DISABLE_IT : Disable the specified SPDIFRX interrupts\r\n      (+) __HAL_SPDIFRX_GET_FLAG: Check whether the specified SPDIFRX flag is set or not.\r\n\r\n    [..]\r\n      (@) You can refer to the SPDIFRX HAL driver header file for more useful macros\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n/** @defgroup SPDIFRX SPDIFRX\r\n* @brief SPDIFRX HAL module driver\r\n* @{\r\n*/\r\n\r\n#ifdef HAL_SPDIFRX_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n#define SPDIFRX_TIMEOUT_VALUE  0xFFFF\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/** @addtogroup SPDIFRX_Private_Functions\r\n  * @{\r\n  */\r\nstatic void  SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma);\r\nstatic void  SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma);\r\nstatic void  SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma);\r\nstatic void  SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma);\r\nstatic void  SPDIFRX_DMAError(DMA_HandleTypeDef *hdma);\r\nstatic void  SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif);\r\nstatic void  SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif);\r\nstatic HAL_StatusTypeDef  SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart);\r\n/**\r\n  * @}\r\n  */\r\n/* Exported functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup SPDIFRX_Exported_Functions SPDIFRX Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup  SPDIFRX_Exported_Functions_Group1 Initialization and de-initialization functions \r\n  *  @brief    Initialization and Configuration functions \r\n  *\r\n  @verbatim    \r\n  ===============================================================================\r\n  ##### Initialization and de-initialization functions #####\r\n  ===============================================================================\r\n  [..]  This subsection provides a set of functions allowing to initialize and \r\n  de-initialize the SPDIFRX peripheral:\r\n  \r\n  (+) User must Implement HAL_SPDIFRX_MspInit() function in which he configures \r\n  all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).\r\n  \r\n  (+) Call the function HAL_SPDIFRX_Init() to configure the SPDIFRX peripheral with \r\n  the selected configuration:\r\n  (++) Input Selection (IN0, IN1,...)\r\n  (++) Maximum allowed re-tries during synchronization phase\r\n  (++) Wait for activity on SPDIF selected input\r\n  (++) Channel status selection (from channel A or B)\r\n  (++) Data format (LSB, MSB, ...)\r\n  (++) Stereo mode\r\n  (++) User bits masking (PT,C,U,V,...)\r\n  \r\n  (+) Call the function HAL_SPDIFRX_DeInit() to restore the default configuration \r\n  of the selected SPDIFRXx peripheral. \r\n  @endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief Initializes the SPDIFRX according to the specified parameters \r\n  *        in the SPDIFRX_InitTypeDef and create the associated handle.\r\n  * @param hspdif: SPDIFRX handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)\r\n{\r\n  uint32_t tmpreg = 0;\r\n  \r\n  /* Check the SPDIFRX handle allocation */\r\n  if(hspdif == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Check the SPDIFRX parameters */\r\n  assert_param(IS_STEREO_MODE(hspdif->Init.StereoMode));\r\n  assert_param(IS_SPDIFRX_INPUT_SELECT(hspdif->Init.InputSelection));\r\n  assert_param(IS_SPDIFRX_MAX_RETRIES(hspdif->Init.Retries));\r\n  assert_param(IS_SPDIFRX_WAIT_FOR_ACTIVITY(hspdif->Init.WaitForActivity));\r\n  assert_param(IS_SPDIFRX_CHANNEL(hspdif->Init.ChannelSelection));\r\n  assert_param(IS_SPDIFRX_DATA_FORMAT(hspdif->Init.DataFormat));\r\n  assert_param(IS_PREAMBLE_TYPE_MASK(hspdif->Init.PreambleTypeMask));\r\n  assert_param(IS_CHANNEL_STATUS_MASK(hspdif->Init.ChannelStatusMask));\r\n  assert_param(IS_VALIDITY_MASK(hspdif->Init.ValidityBitMask));\r\n  assert_param(IS_PARITY_ERROR_MASK(hspdif->Init.ParityErrorMask));\r\n  \r\n  if(hspdif->State == HAL_SPDIFRX_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    hspdif->Lock = HAL_UNLOCKED;\r\n    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */\r\n    HAL_SPDIFRX_MspInit(hspdif);\r\n  }\r\n  \r\n  /* SPDIFRX peripheral state is BUSY*/\r\n  hspdif->State = HAL_SPDIFRX_STATE_BUSY;  \r\n  \r\n  /* Disable SPDIFRX interface (IDLE State) */\r\n  __HAL_SPDIFRX_IDLE(hspdif);\r\n  \r\n  /* Reset the old SPDIFRX CR configuration */\r\n  tmpreg = hspdif->Instance->CR;\r\n  \r\n  tmpreg &= ~((uint16_t) SPDIFRX_CR_RXSTEO  | SPDIFRX_CR_DRFMT  | SPDIFRX_CR_PMSK |\r\n              SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK  |\r\n              SPDIFRX_CR_CHSEL | SPDIFRX_CR_NBTR | SPDIFRX_CR_WFA | SPDIFRX_CR_INSEL); \r\n  \r\n  /* Sets the new configuration of the SPDIFRX peripheral */\r\n  tmpreg |= ((uint16_t) hspdif->Init.StereoMode |\r\n             hspdif->Init.InputSelection |\r\n             hspdif->Init.Retries |\r\n             hspdif->Init.WaitForActivity |\r\n             hspdif->Init.ChannelSelection |\r\n             hspdif->Init.DataFormat |\r\n             hspdif->Init.PreambleTypeMask |\r\n             hspdif->Init.ChannelStatusMask |\r\n             hspdif->Init.ValidityBitMask |\r\n             hspdif->Init.ParityErrorMask);\r\n  \r\n  hspdif->Instance->CR = tmpreg;  \r\n  \r\n  hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;\r\n  \r\n  /* SPDIFRX peripheral state is READY*/\r\n  hspdif->State = HAL_SPDIFRX_STATE_READY;\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief DeInitializes the SPDIFRX peripheral \r\n  * @param hspdif: SPDIFRX handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif)\r\n{\r\n  /* Check the SPDIFRX handle allocation */\r\n  if(hspdif == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_SPDIFRX_ALL_INSTANCE(hspdif->Instance));\r\n  \r\n  hspdif->State = HAL_SPDIFRX_STATE_BUSY;\r\n  \r\n  /* Disable SPDIFRX interface (IDLE state) */\r\n  __HAL_SPDIFRX_IDLE(hspdif);\r\n  \r\n  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */\r\n  HAL_SPDIFRX_MspDeInit(hspdif);\r\n  \r\n  hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;\r\n  \r\n  /* SPDIFRX peripheral state is RESET*/\r\n  hspdif->State = HAL_SPDIFRX_STATE_RESET;\r\n  \r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hspdif);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief SPDIFRX MSP Init\r\n  * @param hspdif: SPDIFRX handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hspdif);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n  the HAL_SPDIFRX_MspInit could be implemented in the user file\r\n  */ \r\n}\r\n\r\n/**\r\n  * @brief SPDIFRX MSP DeInit\r\n  * @param hspdif: SPDIFRX handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hspdif);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n  the HAL_SPDIFRX_MspDeInit could be implemented in the user file\r\n  */ \r\n}\r\n\r\n/**\r\n  * @brief Sets the SPDIFRX  dtat format according to the specified parameters \r\n  *        in the SPDIFRX_InitTypeDef.\r\n  * @param hspdif: SPDIFRX handle\r\n  * @param sDataFormat: SPDIFRX data format\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef  sDataFormat)\r\n{\r\n  uint32_t tmpreg = 0;\r\n  \r\n  /* Check the SPDIFRX handle allocation */\r\n  if(hspdif == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Check the SPDIFRX parameters */\r\n  assert_param(IS_STEREO_MODE(sDataFormat.StereoMode));\r\n  assert_param(IS_SPDIFRX_DATA_FORMAT(sDataFormat.DataFormat));\r\n  assert_param(IS_PREAMBLE_TYPE_MASK(sDataFormat.PreambleTypeMask));\r\n  assert_param(IS_CHANNEL_STATUS_MASK(sDataFormat.ChannelStatusMask));\r\n  assert_param(IS_VALIDITY_MASK(sDataFormat.ValidityBitMask));\r\n  assert_param(IS_PARITY_ERROR_MASK(sDataFormat.ParityErrorMask));\r\n  \r\n  /* Reset the old SPDIFRX CR configuration */\r\n  tmpreg = hspdif->Instance->CR;\r\n  \r\n  if(((tmpreg & SPDIFRX_STATE_RCV) == SPDIFRX_STATE_RCV) &&\r\n     (((tmpreg & SPDIFRX_CR_DRFMT) != sDataFormat.DataFormat) ||\r\n      ((tmpreg & SPDIFRX_CR_RXSTEO) != sDataFormat.StereoMode)))  \r\n  {\r\n    return HAL_ERROR;    \r\n  }  \r\n  \r\n  tmpreg &= ~((uint16_t) SPDIFRX_CR_RXSTEO  | SPDIFRX_CR_DRFMT  | SPDIFRX_CR_PMSK |\r\n              SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK);   \r\n  \r\n  /* Sets the new configuration of the SPDIFRX peripheral */\r\n  tmpreg |= ((uint16_t) sDataFormat.StereoMode |\r\n             sDataFormat.DataFormat |\r\n             sDataFormat.PreambleTypeMask |\r\n             sDataFormat.ChannelStatusMask |\r\n             sDataFormat.ValidityBitMask |\r\n             sDataFormat.ParityErrorMask);\r\n  \r\n  hspdif->Instance->CR = tmpreg;  \r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPDIFRX_Exported_Functions_Group2 IO operation functions \r\n  *  @brief Data transfers functions \r\n  *\r\n@verbatim   \r\n===============================================================================\r\n                     ##### IO operation functions #####\r\n===============================================================================  \r\n    [..]\r\n    This subsection provides a set of functions allowing to manage the SPDIFRX data \r\n    transfers.\r\n\r\n    (#) There is two mode of transfer:\r\n        (++) Blocking mode : The communication is performed in the polling mode. \r\n             The status of all data processing is returned by the same function \r\n             after finishing transfer.  \r\n        (++) No-Blocking mode : The communication is performed using Interrupts \r\n             or DMA. These functions return the status of the transfer start-up.\r\n             The end of the data processing will be indicated through the \r\n             dedicated SPDIFRX IRQ when using Interrupt mode or the DMA IRQ when \r\n             using DMA mode.\r\n\r\n    (#) Blocking mode functions are :\r\n        (++) HAL_SPDIFRX_ReceiveDataFlow()\r\n        (++) HAL_SPDIFRX_ReceiveControlFlow()\r\n                (+@) Do not use blocking mode to receive both control and data flow at the same time.\r\n\r\n    (#) No-Blocking mode functions with Interrupt are :\r\n        (++) HAL_SPDIFRX_ReceiveControlFlow_IT()\r\n        (++) HAL_SPDIFRX_ReceiveDataFlow_IT()\r\n\r\n    (#) No-Blocking mode functions with DMA are :\r\n        (++) HAL_SPDIFRX_ReceiveControlFlow_DMA()\r\n        (++) HAL_SPDIFRX_ReceiveDataFlow_DMA()\r\n\r\n    (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:\r\n        (++) HAL_SPDIFRX_RxCpltCallback()\r\n        (++) HAL_SPDIFRX_ErrorCallback()\r\n\r\n@endverbatim\r\n* @{\r\n*/\r\n\r\n\r\n/**\r\n  * @brief  Receives an amount of data (Data Flow) in blocking mode. \r\n  * @param  hspdif: pointer to SPDIFRX_HandleTypeDef structure that contains\r\n  *                 the configuration information for SPDIFRX module.\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be received\r\n  * @param  Timeout: Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0U;\r\n  \r\n  if((pData == NULL ) || (Size == 0U)) \r\n  {\r\n    return  HAL_ERROR;\r\n  }\r\n  \r\n  if(hspdif->State == HAL_SPDIFRX_STATE_READY)\r\n  { \r\n    /* Process Locked */\r\n    __HAL_LOCK(hspdif);\r\n    \r\n    hspdif->State = HAL_SPDIFRX_STATE_BUSY;\r\n    \r\n    /* Start synchronisation */\r\n    __HAL_SPDIFRX_SYNC(hspdif);\r\n    \r\n    /* Get tick */ \r\n    tickstart = HAL_GetTick();\r\n    \r\n    /* Wait until SYNCD flag is set */\r\n    if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK)\r\n    { \r\n      return HAL_TIMEOUT;\r\n    }  \r\n    \r\n    /* Start reception */    \r\n    __HAL_SPDIFRX_RCV(hspdif);\r\n    \r\n    /* Receive data flow */\r\n    while(Size > 0U)\r\n    {     \r\n      /* Get tick */ \r\n      tickstart = HAL_GetTick();\r\n      \r\n      /* Wait until RXNE flag is set */\r\n      if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)\r\n      { \r\n        return HAL_TIMEOUT;\r\n      }  \r\n      \r\n      (*pData++) = hspdif->Instance->DR;\r\n      Size--; \r\n    }      \r\n    \r\n    /* SPDIFRX ready */\r\n    hspdif->State = HAL_SPDIFRX_STATE_READY;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hspdif);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Receives an amount of data (Control Flow) in blocking mode. \r\n  * @param  hspdif: pointer to a SPDIFRX_HandleTypeDef structure that contains\r\n  *                 the configuration information for SPDIFRX module.\r\n  * @param  pData: Pointer to data buffer\r\n  * @param  Size: Amount of data to be received\r\n  * @param  Timeout: Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0U;\r\n  \r\n  if((pData == NULL ) || (Size == 0U)) \r\n  {\r\n    return  HAL_ERROR;\r\n  }\r\n  \r\n  if(hspdif->State == HAL_SPDIFRX_STATE_READY)\r\n  { \r\n    /* Process Locked */\r\n    __HAL_LOCK(hspdif);\r\n    \r\n    hspdif->State = HAL_SPDIFRX_STATE_BUSY;\r\n    \r\n    /* Start synchronization */\r\n    __HAL_SPDIFRX_SYNC(hspdif);\r\n    \r\n    /* Get tick */ \r\n    tickstart = HAL_GetTick();\r\n    \r\n    /* Wait until SYNCD flag is set */\r\n    if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK)\r\n    { \r\n      return HAL_TIMEOUT;\r\n    }  \r\n    \r\n    /* Start reception */    \r\n    __HAL_SPDIFRX_RCV(hspdif);\r\n    \r\n    /* Receive control flow */\r\n    while(Size > 0U)\r\n    {      \r\n      /* Get tick */ \r\n      tickstart = HAL_GetTick();\r\n      \r\n      /* Wait until CSRNE flag is set */\r\n      if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_CSRNE, RESET, Timeout, tickstart) != HAL_OK)\r\n      { \r\n        return HAL_TIMEOUT;\r\n      }  \r\n      \r\n      (*pData++) = hspdif->Instance->CSR;\r\n      Size--; \r\n    }      \r\n    \r\n    /* SPDIFRX ready */\r\n    hspdif->State = HAL_SPDIFRX_STATE_READY;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hspdif);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Receive an amount of data (Data Flow) in non-blocking mode with Interrupt\r\n  * @param hspdif: SPDIFRX handle\r\n  * @param pData: a 32-bit pointer to the Receive data buffer.\r\n  * @param Size: number of data sample to be received .\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)\r\n{\r\n  uint32_t tickstart = 0U;\r\n  \r\n  if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_CX))\r\n  {\r\n    if((pData == NULL) || (Size == 0U)) \r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n    \r\n    /* Process Locked */\r\n    __HAL_LOCK(hspdif);\r\n    \r\n    hspdif->pRxBuffPtr = pData;\r\n    hspdif->RxXferSize = Size;\r\n    hspdif->RxXferCount = Size;\r\n    \r\n    hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;\r\n    \r\n    /* Check if a receive process is ongoing or not */\r\n    hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX;\r\n    \r\n    \r\n    /* Enable the SPDIFRX  PE Error Interrupt */\r\n    __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE);\r\n    \r\n    /* Enable the SPDIFRX  OVR Error Interrupt */\r\n    __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hspdif);\r\n    \r\n    /* Enable the SPDIFRX RXNE interrupt */\r\n    __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_RXNE);\r\n    \r\n    if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)) \r\n    {\r\n      /* Start synchronization */\r\n      __HAL_SPDIFRX_SYNC(hspdif);\r\n      \r\n      /* Get tick */ \r\n      tickstart = HAL_GetTick();\r\n      \r\n      /* Wait until SYNCD flag is set */\r\n      if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK)\r\n      { \r\n        return HAL_TIMEOUT;\r\n      }  \r\n      \r\n      /* Start reception */    \r\n      __HAL_SPDIFRX_RCV(hspdif);\r\n    }\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY; \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Receive an amount of data (Control Flow) with Interrupt\r\n  * @param hspdif: SPDIFRX handle\r\n  * @param pData: a 32-bit pointer to the Receive data buffer.\r\n  * @param Size: number of data sample (Control Flow) to be received :\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)\r\n{\r\n  uint32_t tickstart = 0U;\r\n  \r\n  if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX))\r\n  {\r\n    if((pData == NULL ) || (Size == 0U)) \r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n    \r\n    /* Process Locked */\r\n    __HAL_LOCK(hspdif);\r\n    \r\n    hspdif->pCsBuffPtr = pData;\r\n    hspdif->CsXferSize = Size;\r\n    hspdif->CsXferCount = Size;\r\n    \r\n    hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;\r\n    \r\n    /* Check if a receive process is ongoing or not */\r\n    hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX;\r\n    \r\n    \r\n    /* Enable the SPDIFRX PE Error Interrupt */\r\n    __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE);\r\n    \r\n    /* Enable the SPDIFRX OVR Error Interrupt */\r\n    __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hspdif);\r\n    \r\n    /* Enable the SPDIFRX CSRNE interrupt */\r\n    __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_CSRNE);\r\n    \r\n    if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)) \r\n    {\r\n      /* Start synchronization */\r\n      __HAL_SPDIFRX_SYNC(hspdif);\r\n      \r\n      /* Get tick */ \r\n      tickstart = HAL_GetTick();\r\n      \r\n      /* Wait until SYNCD flag is set */\r\n      if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK)\r\n      { \r\n        return HAL_TIMEOUT;\r\n      }  \r\n      \r\n      /* Start reception */    \r\n      __HAL_SPDIFRX_RCV(hspdif);\r\n    }\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY; \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Receive an amount of data (Data Flow) mode with DMA \r\n  * @param hspdif: SPDIFRX handle\r\n  * @param pData: a 32-bit pointer to the Receive data buffer.\r\n  * @param Size: number of data sample to be received :\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)\r\n{\r\n  uint32_t tickstart = 0U;\r\n  \r\n  if((pData == NULL) || (Size == 0U)) \r\n  {\r\n    return  HAL_ERROR;                                    \r\n  } \r\n  \r\n  if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_CX))\r\n  {   \r\n    hspdif->pRxBuffPtr = pData;\r\n    hspdif->RxXferSize = Size;\r\n    hspdif->RxXferCount = Size;\r\n    \r\n    /* Process Locked */\r\n    __HAL_LOCK(hspdif);\r\n    \r\n    hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;\r\n    hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX;\r\n    \r\n    /* Set the SPDIFRX Rx DMA Half transfer complete callback */\r\n    hspdif->hdmaDrRx->XferHalfCpltCallback = SPDIFRX_DMARxHalfCplt;\r\n    \r\n    /* Set the SPDIFRX Rx DMA transfer complete callback */\r\n    hspdif->hdmaDrRx->XferCpltCallback = SPDIFRX_DMARxCplt;\r\n    \r\n    /* Set the DMA error callback */\r\n    hspdif->hdmaDrRx->XferErrorCallback = SPDIFRX_DMAError;\r\n    \r\n    /* Enable the DMA request */\r\n    HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size);\r\n    \r\n    /* Enable RXDMAEN bit in SPDIFRX CR register for data flow reception*/\r\n    hspdif->Instance->CR |= SPDIFRX_CR_RXDMAEN;\r\n    \r\n    if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)) \r\n    {\r\n      /* Start synchronization */\r\n      __HAL_SPDIFRX_SYNC(hspdif);\r\n      \r\n      /* Get tick */ \r\n      tickstart = HAL_GetTick();\r\n      \r\n      /* Wait until SYNCD flag is set */\r\n      if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK)\r\n      { \r\n        return HAL_TIMEOUT;\r\n      }  \r\n      \r\n      /* Start reception */    \r\n      __HAL_SPDIFRX_RCV(hspdif);\r\n    }\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hspdif);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY; \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Receive an amount of data (Control Flow) with DMA \r\n  * @param hspdif: SPDIFRX handle\r\n  * @param pData: a 32-bit pointer to the Receive data buffer.\r\n  * @param Size: number of data (Control Flow) sample to be received :\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)\r\n{\r\n  uint32_t tickstart = 0U;\r\n  \r\n  if((pData == NULL) || (Size == 0U)) \r\n  {\r\n    return  HAL_ERROR;                                    \r\n  } \r\n  \r\n  if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX))\r\n  {    \r\n    hspdif->pCsBuffPtr = pData;\r\n    hspdif->CsXferSize = Size;\r\n    hspdif->CsXferCount = Size;\r\n    \r\n    /* Process Locked */\r\n    __HAL_LOCK(hspdif);\r\n    \r\n    hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;\r\n    hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX;\r\n    \r\n    /* Set the SPDIFRX Rx DMA Half transfer complete callback */\r\n    hspdif->hdmaCsRx->XferHalfCpltCallback = SPDIFRX_DMACxHalfCplt;\r\n    \r\n    /* Set the SPDIFRX Rx DMA transfer complete callback */\r\n    hspdif->hdmaCsRx->XferCpltCallback = SPDIFRX_DMACxCplt;\r\n    \r\n    /* Set the DMA error callback */\r\n    hspdif->hdmaCsRx->XferErrorCallback = SPDIFRX_DMAError;\r\n    \r\n    /* Enable the DMA request */\r\n    HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size);\r\n    \r\n    /* Enable CBDMAEN bit in SPDIFRX CR register for control flow reception*/\r\n    hspdif->Instance->CR |= SPDIFRX_CR_CBDMAEN;\r\n    \r\n    if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)) \r\n    {\r\n      /* Start synchronization */\r\n      __HAL_SPDIFRX_SYNC(hspdif);\r\n      \r\n      /* Get tick */ \r\n      tickstart = HAL_GetTick();\r\n      \r\n      /* Wait until SYNCD flag is set */\r\n      if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK)\r\n      { \r\n        return HAL_TIMEOUT;\r\n      }  \r\n      \r\n      /* Start reception */    \r\n      __HAL_SPDIFRX_RCV(hspdif);\r\n    }\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hspdif);\r\n    \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY; \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief stop the audio stream receive from the Media.\r\n  * @param hspdif: SPDIFRX handle\r\n  * @retval None\r\n  */\r\nHAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hspdif);\r\n  \r\n  /* Disable the SPDIFRX DMA requests */\r\n  hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN);\r\n  hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN);\r\n  \r\n  /* Disable the SPDIFRX DMA channel */\r\n  __HAL_DMA_DISABLE(hspdif->hdmaDrRx);\r\n  __HAL_DMA_DISABLE(hspdif->hdmaCsRx);\r\n  \r\n  /* Disable SPDIFRX peripheral */\r\n  __HAL_SPDIFRX_IDLE(hspdif);\r\n  \r\n  hspdif->State = HAL_SPDIFRX_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hspdif);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  This function handles SPDIFRX interrupt request.\r\n  * @param  hspdif: SPDIFRX handle\r\n  * @retval HAL status\r\n  */\r\nvoid HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif)\r\n{  \r\n  /* SPDIFRX in mode Data Flow Reception ------------------------------------------------*/\r\n  if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_RXNE) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_RXNE) != RESET))\r\n  {\r\n    __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_RXNE);\r\n    SPDIFRX_ReceiveDataFlow_IT(hspdif);\r\n  }\r\n  \r\n  /* SPDIFRX in mode Control Flow Reception ------------------------------------------------*/\r\n  if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_CSRNE) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_CSRNE) != RESET))\r\n  {\r\n    __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_CSRNE);\r\n    SPDIFRX_ReceiveControlFlow_IT(hspdif);\r\n  }\r\n  \r\n  /* SPDIFRX Overrun error interrupt occurred ---------------------------------*/\r\n  if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_OVR) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_OVRIE) != RESET))\r\n  {\r\n    __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_FLAG_OVR);\r\n    \r\n    /* Change the SPDIFRX error code */\r\n    hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_OVR;\r\n    \r\n    /* the transfer is not stopped */\r\n    HAL_SPDIFRX_ErrorCallback(hspdif);\r\n  } \r\n  \r\n  /* SPDIFRX Parity error interrupt occurred ---------------------------------*/\r\n  if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_PERR) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_PERRIE) != RESET))\r\n  {\r\n    __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_FLAG_PERR);\r\n    \r\n    /* Change the SPDIFRX error code */\r\n    hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_PE;\r\n    \r\n    /* the transfer is not stopped */\r\n    HAL_SPDIFRX_ErrorCallback(hspdif);\r\n  } \r\n}\r\n\r\n/**\r\n  * @brief Rx Transfer (Data flow) half completed callbacks\r\n  * @param hspdif: SPDIFRX handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hspdif);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n  the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file\r\n  */\r\n}\r\n\r\n/**\r\n  * @brief Rx Transfer (Data flow) completed callbacks\r\n  * @param hspdif: SPDIFRX handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hspdif);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n  the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file\r\n  */\r\n}\r\n\r\n/**\r\n  * @brief Rx (Control flow) Transfer half completed callbacks\r\n  * @param hspdif: SPDIFRX handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hspdif);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n  the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file\r\n  */\r\n}\r\n\r\n/**\r\n  * @brief Rx Transfer (Control flow) completed callbacks\r\n  * @param hspdif: SPDIFRX handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hspdif);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n  the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file\r\n  */\r\n}\r\n\r\n/**\r\n  * @brief SPDIFRX error callbacks\r\n  * @param hspdif: SPDIFRX handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hspdif);\r\n  \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n  the HAL_SPDIFRX_ErrorCallback could be implemented in the user file\r\n  */ \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPDIFRX_Exported_Functions_Group3 Peripheral State and Errors functions \r\n  *  @brief   Peripheral State functions \r\n  *\r\n@verbatim   \r\n===============================================================================\r\n##### Peripheral State and Errors functions #####\r\n===============================================================================  \r\n[..]\r\nThis subsection permit to get in run-time the status of the peripheral \r\nand the data flow.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Return the SPDIFRX state\r\n  * @param  hspdif : SPDIFRX handle\r\n  * @retval HAL state\r\n  */\r\nHAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif)\r\n{\r\n  return hspdif->State;\r\n}\r\n\r\n/**\r\n  * @brief  Return the SPDIFRX error code\r\n  * @param  hspdif : SPDIFRX handle\r\n  * @retval SPDIFRX Error Code\r\n  */\r\nuint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif)\r\n{\r\n  return hspdif->ErrorCode;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */  \r\n\r\n/**\r\n  * @brief DMA SPDIFRX receive process (Data flow) complete callback \r\n  * @param hdma : DMA handle\r\n  * @retval None\r\n  */\r\nstatic void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  \r\n  /* Disable Rx DMA Request */\r\n  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)\r\n  {\r\n    hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN);\r\n    hspdif->RxXferCount = 0;\r\n    hspdif->State = HAL_SPDIFRX_STATE_READY; \r\n  }\r\n  HAL_SPDIFRX_RxCpltCallback(hspdif); \r\n}\r\n\r\n/**\r\n  * @brief DMA SPDIFRX receive process (Data flow) half complete callback \r\n  * @param hdma : DMA handle\r\n  * @retval None\r\n  */\r\nstatic void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n  \r\n  HAL_SPDIFRX_RxHalfCpltCallback(hspdif); \r\n}\r\n\r\n\r\n/**\r\n  * @brief DMA SPDIFRX receive process (Control flow) complete callback \r\n  * @param hdma : DMA handle\r\n  * @retval None\r\n  */\r\nstatic void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  \r\n  /* Disable Cb DMA Request */\r\n  hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN);\r\n  hspdif->CsXferCount = 0;\r\n  \r\n  hspdif->State = HAL_SPDIFRX_STATE_READY; \r\n  HAL_SPDIFRX_CxCpltCallback(hspdif); \r\n}\r\n\r\n/**\r\n  * @brief DMA SPDIFRX receive process (Control flow) half complete callback \r\n  * @param hdma : DMA handle\r\n  * @retval None\r\n  */\r\nstatic void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n  \r\n  HAL_SPDIFRX_CxHalfCpltCallback(hspdif); \r\n}\r\n\r\n/**\r\n  * @brief DMA SPDIFRX communication error callback \r\n  * @param hdma : DMA handle\r\n  * @retval None\r\n  */\r\nstatic void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma)\r\n{\r\n  SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  \r\n  /* Disable Rx and Cb DMA Request */\r\n  hspdif->Instance->CR &= (uint16_t)(~(SPDIFRX_CR_RXDMAEN | SPDIFRX_CR_CBDMAEN));\r\n  hspdif->RxXferCount = 0;\r\n  \r\n  hspdif->State= HAL_SPDIFRX_STATE_READY;\r\n  \r\n  /* Set the error code and execute error callback*/\r\n  hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_DMA;\r\n  HAL_SPDIFRX_ErrorCallback(hspdif);\r\n}\r\n\r\n/**\r\n  * @brief Receive an amount of data (Data Flow) with Interrupt\r\n  * @param hspdif: SPDIFRX handle\r\n  * @retval None\r\n  */\r\nstatic void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif)\r\n{\r\n  /* Receive data */\r\n  (*hspdif->pRxBuffPtr++) = hspdif->Instance->DR;\r\n  hspdif->RxXferCount--;\r\n  \r\n  if(hspdif->RxXferCount == 0)\r\n  {            \r\n    /* Disable RXNE/PE and OVR interrupts */\r\n    __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE | SPDIFRX_IT_PERRIE | SPDIFRX_IT_RXNE);\r\n    \r\n    hspdif->State = HAL_SPDIFRX_STATE_READY;\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hspdif);\r\n    \r\n    HAL_SPDIFRX_RxCpltCallback(hspdif);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Receive an amount of data (Control Flow) with Interrupt\r\n  * @param hspdif: SPDIFRX handle\r\n  * @retval None\r\n  */\r\nstatic void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif)\r\n{\r\n  /* Receive data */\r\n  (*hspdif->pCsBuffPtr++) = hspdif->Instance->CSR;\r\n  hspdif->CsXferCount--;\r\n  \r\n  if(hspdif->CsXferCount == 0)\r\n  {        \r\n    /* Disable CSRNE interrupt */\r\n    __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);\r\n    \r\n    hspdif->State = HAL_SPDIFRX_STATE_READY; \r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hspdif);\r\n    \r\n    HAL_SPDIFRX_CxCpltCallback(hspdif);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief This function handles SPDIFRX Communication Timeout.\r\n  * @param hspdif: SPDIFRX handle\r\n  * @param Flag: Flag checked\r\n  * @param Status: Value of the flag expected\r\n  * @param Timeout: Duration of the timeout\r\n  * @param tickstart: Tick start value\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart)\r\n{\r\n  /* Wait until flag is set */\r\n  if(Status == RESET)\r\n  {\r\n    while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) == RESET)\r\n    {\r\n      /* Check for the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))\r\n        {\r\n          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */\r\n          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);\r\n          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);\r\n          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);\r\n          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);\r\n          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);\r\n          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);\r\n          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);\r\n          \r\n          hspdif->State= HAL_SPDIFRX_STATE_READY;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hspdif);\r\n          \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n  }\r\n  else\r\n  {\r\n    while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) != RESET)\r\n    {\r\n      /* Check for the Timeout */\r\n      if(Timeout != HAL_MAX_DELAY)\r\n      {\r\n        if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))\r\n        {\r\n          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */\r\n          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);\r\n          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);\r\n          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);\r\n          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE);\r\n          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE);\r\n          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);\r\n          __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);\r\n          \r\n          hspdif->State= HAL_SPDIFRX_STATE_READY;\r\n          \r\n          /* Process Unlocked */\r\n          __HAL_UNLOCK(hspdif);\r\n          \r\n          return HAL_TIMEOUT;\r\n        }\r\n      }\r\n    }\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n* @}\r\n*/\r\n\r\n#endif /* HAL_SPDIFRX_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_spi.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   SPI HAL module driver.\r\n  *          This file provides firmware functions to manage the following\r\n  *          functionalities of the Serial Peripheral Interface (SPI) peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + IO operation functions\r\n  *           + Peripheral Control functions\r\n  *           + Peripheral State functions\r\n  *\r\n  @verbatim\r\n  ==============================================================================\r\n                        ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]\r\n      The SPI HAL driver can be used as follows:\r\n\r\n      (#) Declare a SPI_HandleTypeDef handle structure, for example:\r\n          SPI_HandleTypeDef  hspi;\r\n\r\n      (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:\r\n          (##) Enable the SPIx interface clock\r\n          (##) SPI pins configuration\r\n              (+++) Enable the clock for the SPI GPIOs\r\n              (+++) Configure these SPI pins as alternate function push-pull\r\n          (##) NVIC configuration if you need to use interrupt process\r\n              (+++) Configure the SPIx interrupt priority\r\n              (+++) Enable the NVIC SPI IRQ handle\r\n          (##) DMA Configuration if you need to use DMA process\r\n              (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel\r\n              (+++) Enable the DMAx clock\r\n              (+++) Configure the DMA handle parameters\r\n              (+++) Configure the DMA Tx or Rx channel\r\n              (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle\r\n              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel\r\n\r\n      (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS\r\n          management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.\r\n\r\n      (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:\r\n          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)\r\n              by calling the customized HAL_SPI_MspInit() API.\r\n     [..]\r\n       Circular mode restriction:\r\n      (#) The DMA circular mode cannot be used when the SPI is configured in these modes:\r\n          (##) Master 2Lines RxOnly\r\n          (##) Master 1Line Rx\r\n      (#) The CRC feature is not managed when the DMA circular mode is enabled\r\n      (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs\r\n          the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup SPI SPI\r\n  * @brief SPI HAL module driver\r\n  * @{\r\n  */\r\n#ifdef HAL_SPI_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private defines -----------------------------------------------------------*/\r\n/** @defgroup SPI_Private_Constants SPI Private Constants\r\n  * @{\r\n  */\r\n#define SPI_DEFAULT_TIMEOUT 50\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Private macros ------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/** @defgroup SPI_Private_Functions SPI Private Functions\r\n  * @{\r\n  */\r\nstatic void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);\r\nstatic void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);\r\nstatic void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);\r\nstatic void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);\r\nstatic void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);\r\nstatic void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);\r\nstatic void SPI_DMAError(DMA_HandleTypeDef *hdma);\r\nstatic void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);\r\nstatic HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout);\r\nstatic HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout);\r\nstatic void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\r\nstatic void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\r\nstatic void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\r\n#if (USE_SPI_CRC != 0U)\r\nstatic void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);\r\nstatic void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);\r\nstatic void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);\r\nstatic void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);\r\n#endif\r\nstatic void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\r\nstatic void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\r\nstatic void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\r\nstatic void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\r\nstatic void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\r\nstatic void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);\r\nstatic void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);\r\nstatic void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);\r\nstatic HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);\r\nstatic HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup SPI_Exported_Functions SPI Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions\r\n *  @brief    Initialization and Configuration functions\r\n *\r\n@verbatim\r\n ===============================================================================\r\n              ##### Initialization and de-initialization functions #####\r\n ===============================================================================\r\n    [..]  This subsection provides a set of functions allowing to initialize and\r\n          de-initialize the SPIx peripheral:\r\n\r\n      (+) User must implement HAL_SPI_MspInit() function in which he configures\r\n          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).\r\n\r\n      (+) Call the function HAL_SPI_Init() to configure the selected device with\r\n          the selected configuration:\r\n        (++) Mode\r\n        (++) Direction\r\n        (++) Data Size\r\n        (++) Clock Polarity and Phase\r\n        (++) NSS Management\r\n        (++) BaudRate Prescaler\r\n        (++) FirstBit\r\n        (++) TIMode\r\n        (++) CRC Calculation\r\n        (++) CRC Polynomial if CRC enabled\r\n        (++) CRC Length, used only with Data8 and Data16\r\n        (++) FIFO reception threshold\r\n\r\n      (+) Call the function HAL_SPI_DeInit() to restore the default configuration\r\n          of the selected SPIx peripheral.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initialize the SPI according to the specified parameters\r\n  *         in the SPI_InitTypeDef and initialize the associated handle.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)\r\n{\r\n  uint32_t frxth;\r\n\r\n  /* Check the SPI handle allocation */\r\n  if(hspi == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));\r\n  assert_param(IS_SPI_MODE(hspi->Init.Mode));\r\n  assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));\r\n  assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));\r\n  assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));\r\n  assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));\r\n  assert_param(IS_SPI_NSS(hspi->Init.NSS));\r\n  assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));\r\n  assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));\r\n  assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));\r\n  assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));\r\n#if (USE_SPI_CRC != 0U)\r\n  assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));\r\n  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n  {\r\n    assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));\r\n    assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));\r\n  }\r\n  /* Align the CRC Length on the data size */\r\n  if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)\r\n  {\r\n    /* CRC Length aligned on the data size : value set by default */\r\n    if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r\n    {\r\n      hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;\r\n    }\r\n    else\r\n    {\r\n      hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;\r\n    }\r\n  }\r\n#endif\r\n\r\n  if(hspi->State == HAL_SPI_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    hspi->Lock = HAL_UNLOCKED;\r\n\r\n    /* Init the low level hardware : GPIO, CLOCK, NVIC... */\r\n    HAL_SPI_MspInit(hspi);\r\n  }\r\n\r\n  hspi->State = HAL_SPI_STATE_BUSY;\r\n\r\n  /* Disable the selected SPI peripheral */\r\n  __HAL_SPI_DISABLE(hspi);\r\n\r\n  /* Align by default the rs fifo threshold on the data size */\r\n  if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r\n  {\r\n    frxth = SPI_RXFIFO_THRESHOLD_HF;\r\n  }\r\n  else\r\n  {\r\n    frxth = SPI_RXFIFO_THRESHOLD_QF;\r\n  }\r\n\r\n  /* CRC calculation is valid only for 16Bit and 8 Bit */\r\n  if(( hspi->Init.DataSize != SPI_DATASIZE_16BIT ) && ( hspi->Init.DataSize != SPI_DATASIZE_8BIT ))\r\n  {\r\n    /* CRC must be disabled */\r\n    hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;\r\n  }\r\n\r\n  /*---------------------------- SPIx CR1 & CR2 Configuration ------------------------*/\r\n  /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,\r\n  Communication speed, First bit, CRC calculation state, CRC Length */\r\n  hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction |\r\n                         hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |\r\n                         hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit  | hspi->Init.CRCCalculation);\r\n\r\n  if( hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)\r\n  {\r\n    hspi->Instance->CR1|= SPI_CR1_CRCL;\r\n  }\r\n\r\n  /* Configure : NSS management */\r\n  /* Configure : Rx Fifo Threshold */\r\n  hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode | hspi->Init.NSSPMode |\r\n                         hspi->Init.DataSize ) | frxth;\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n  /*---------------------------- SPIx CRCPOLY Configuration --------------------*/\r\n  /* Configure : CRC Polynomial */\r\n  WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);\r\n#endif\r\n\r\n  hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r\n  hspi->State= HAL_SPI_STATE_READY;\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  DeInitialize the SPI peripheral.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Check the SPI handle allocation */\r\n  if(hspi == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));\r\n\r\n  hspi->State = HAL_SPI_STATE_BUSY;\r\n\r\n  /* Disable the SPI Peripheral Clock */\r\n  __HAL_SPI_DISABLE(hspi);\r\n\r\n  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */\r\n  HAL_SPI_MspDeInit(hspi);\r\n\r\n  hspi->ErrorCode = HAL_SPI_ERROR_NONE;\r\n  hspi->State = HAL_SPI_STATE_RESET;\r\n\r\n  __HAL_UNLOCK(hspi);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief SPI MSP Init\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hspi);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n  the HAL_SPI_MspInit should be implemented in the user file\r\n  */\r\n}\r\n\r\n/**\r\n  * @brief SPI MSP DeInit\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hspi);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_SPI_MspDeInit should be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_Exported_Functions_Group2 IO operation functions\r\n *  @brief   Data transfers functions\r\n *\r\n@verbatim\r\n  ==============================================================================\r\n                      ##### IO operation functions #####\r\n ===============================================================================\r\n [..]\r\n    This subsection provides a set of functions allowing to manage the SPI\r\n    data transfers.\r\n\r\n    [..] The SPI supports master and slave mode :\r\n\r\n    (#) There are two modes of transfer:\r\n       (++) Blocking mode: The communication is performed in polling mode.\r\n            The HAL status of all data processing is returned by the same function\r\n            after finishing transfer.\r\n       (++) No-Blocking mode: The communication is performed using Interrupts\r\n           or DMA, These APIs return the HAL status.\r\n           The end of the data processing will be indicated through the\r\n           dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when\r\n           using DMA mode.\r\n           The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks\r\n           will be executed respectively at the end of the transmit or Receive process\r\n           The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected\r\n\r\n    (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)\r\n        exist for 1Line (simplex) and 2Lines (full duplex) modes.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Transmit an amount of data in blocking mode.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @param  pData: pointer to data buffer\r\n  * @param  Size: amount of data to be sent\r\n  * @param  Timeout: Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = HAL_GetTick();\r\n  HAL_StatusTypeDef errorcode = HAL_OK;\r\n\r\n  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));\r\n\r\n  /* Process Locked */\r\n  __HAL_LOCK(hspi);\r\n\r\n  if(hspi->State != HAL_SPI_STATE_READY)\r\n  {\r\n    errorcode = HAL_BUSY;\r\n    goto error;\r\n  }\r\n\r\n  if((pData == NULL ) || (Size == 0))\r\n  {\r\n    errorcode = HAL_ERROR;\r\n    goto error;\r\n  }\r\n\r\n  /* Set the transaction information */\r\n  hspi->State       = HAL_SPI_STATE_BUSY_TX;\r\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r\n  hspi->pTxBuffPtr  = pData;\r\n  hspi->TxXferSize  = Size;\r\n  hspi->TxXferCount = Size;\r\n  hspi->pRxBuffPtr  = (uint8_t *)NULL;\r\n  hspi->RxXferSize  = 0;\r\n  hspi->RxXferCount = 0;\r\n\r\n  /* Configure communication direction : 1Line */\r\n  if(hspi->Init.Direction == SPI_DIRECTION_1LINE)\r\n  {\r\n    SPI_1LINE_TX(hspi);\r\n  }\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Reset CRC Calculation */\r\n  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n  {\r\n    SPI_RESET_CRC(hspi);\r\n  }\r\n#endif\r\n\r\n  /* Check if the SPI is already enabled */\r\n  if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r\n  {\r\n    /* Enable SPI peripheral */\r\n    __HAL_SPI_ENABLE(hspi);\r\n  }\r\n\r\n  /* Transmit data in 16 Bit mode */\r\n  if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r\n  {\r\n    /* Transmit data in 16 Bit mode */\r\n    while (hspi->TxXferCount > 0)\r\n    {\r\n      /* Wait until TXE flag is set to send data */\r\n      if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)\r\n      {\r\n        hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r\n        hspi->pTxBuffPtr += sizeof(uint16_t);\r\n        hspi->TxXferCount--;\r\n      }\r\n      else\r\n      {\r\n        /* Timeout management */\r\n        if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout)))\r\n        {\r\n          errorcode = HAL_TIMEOUT;\r\n          goto error;\r\n        }\r\n      }\r\n    }\r\n  }\r\n  /* Transmit data in 8 Bit mode */\r\n  else\r\n  {\r\n    while (hspi->TxXferCount > 0)\r\n    {\r\n      /* Wait until TXE flag is set to send data */\r\n      if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)\r\n      {\r\n        if(hspi->TxXferCount > 1)\r\n        {\r\n          /* write on the data register in packing mode */\r\n          hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);\r\n          hspi->pTxBuffPtr += sizeof(uint16_t);\r\n          hspi->TxXferCount -= 2;\r\n        }\r\n        else\r\n        {\r\n          *((__IO uint8_t*)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++);\r\n          hspi->TxXferCount--;\r\n        }\r\n      }\r\n      else\r\n      {\r\n        /* Timeout management */\r\n        if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout)))\r\n        {\r\n          errorcode = HAL_TIMEOUT;\r\n          goto error;\r\n        }\r\n      }\r\n    }\r\n  }\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Enable CRC Transmission */\r\n  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n  {\r\n     hspi->Instance->CR1|= SPI_CR1_CRCNEXT;\r\n  }\r\n#endif\r\n\r\n  /* Check the end of the transaction */\r\n  if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)\r\n  {\r\n    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;\r\n  }\r\n\r\n  /* Clear overrun flag in 2 Lines communication mode because received is not read */\r\n  if(hspi->Init.Direction == SPI_DIRECTION_2LINES)\r\n  {\r\n    __HAL_SPI_CLEAR_OVRFLAG(hspi);\r\n  }\r\n\r\n  if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r\n  {\r\n    errorcode = HAL_ERROR;\r\n  }\r\n\r\nerror:\r\n  hspi->State = HAL_SPI_STATE_READY;\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hspi);\r\n  return errorcode;\r\n}\r\n\r\n/**\r\n  * @brief  Receive an amount of data in blocking mode.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @param  pData: pointer to data buffer\r\n  * @param  Size: amount of data to be received\r\n  * @param  Timeout: Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r\n{\r\n#if (USE_SPI_CRC != 0U)\r\n  __IO uint16_t tmpreg;\r\n#endif\r\n  uint32_t tickstart = HAL_GetTick();\r\n  HAL_StatusTypeDef errorcode = HAL_OK;\r\n\r\n  if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))\r\n  {\r\n    /* the receive process is not supported in 2Lines direction master mode */\r\n    /* in this case we call the TransmitReceive process                     */\r\n    /* Process Locked */\r\n    return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);\r\n  }\r\n\r\n  /* Process Locked */\r\n  __HAL_LOCK(hspi);\r\n\r\n  if(hspi->State != HAL_SPI_STATE_READY)\r\n  {\r\n    errorcode = HAL_BUSY;\r\n    goto error;\r\n  }\r\n\r\n  if((pData == NULL ) || (Size == 0))\r\n  {\r\n    errorcode = HAL_ERROR;\r\n    goto error;\r\n  }\r\n\r\n  hspi->State       = HAL_SPI_STATE_BUSY_RX;\r\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r\n  hspi->pRxBuffPtr  = pData;\r\n  hspi->RxXferSize  = Size;\r\n  hspi->RxXferCount = Size;\r\n  hspi->pTxBuffPtr  = (uint8_t *)NULL;\r\n  hspi->TxXferSize  = 0;\r\n  hspi->TxXferCount = 0;\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Reset CRC Calculation */\r\n  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n  {\r\n    SPI_RESET_CRC(hspi);\r\n    /* this is done to handle the CRCNEXT before the latest data */\r\n    hspi->RxXferCount--;\r\n  }\r\n#endif\r\n\r\n  /* Set the Rx Fido threshold */\r\n  if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r\n  {\r\n    /* set fiforxthreshold according the reception data length: 16bit */\r\n    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r\n  }\r\n  else\r\n  {\r\n    /* set fiforxthreshold according the reception data length: 8bit */\r\n    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r\n  }\r\n\r\n  /* Configure communication direction 1Line and enabled SPI if needed */\r\n  if(hspi->Init.Direction == SPI_DIRECTION_1LINE)\r\n  {\r\n    SPI_1LINE_RX(hspi);\r\n  }\r\n\r\n  /* Check if the SPI is already enabled */\r\n  if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r\n  {\r\n    /* Enable SPI peripheral */\r\n    __HAL_SPI_ENABLE(hspi);\r\n  }\r\n\r\n  /* Receive data in 8 Bit mode */\r\n  if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT)\r\n  {\r\n    /* Transfer loop */\r\n    while(hspi->RxXferCount > 0)\r\n    {\r\n      /* Check the RXNE flag */\r\n      if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)\r\n      {\r\n        /* read the received data */\r\n        (*hspi->pRxBuffPtr++)= *(__IO uint8_t *)&hspi->Instance->DR;\r\n        hspi->RxXferCount--;\r\n      }\r\n      else\r\n      {\r\n        /* Timeout management */\r\n        if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout)))\r\n        {\r\n          errorcode = HAL_TIMEOUT;\r\n          goto error;\r\n        }\r\n      }\r\n    }\r\n  }\r\n  else\r\n  {\r\n    /* Transfer loop */\r\n    while(hspi->RxXferCount > 0)\r\n    {\r\n      /* Check the RXNE flag */\r\n      if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)\r\n      {\r\n        *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;\r\n        hspi->pRxBuffPtr += sizeof(uint16_t);\r\n        hspi->RxXferCount--;\r\n      }\r\n      else\r\n      {\r\n        /* Timeout management */\r\n        if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout)))\r\n        {\r\n          errorcode = HAL_TIMEOUT;\r\n          goto error;\r\n        }\r\n      }\r\n    }\r\n  }\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Handle the CRC Transmission */\r\n  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n  {\r\n    /* freeze the CRC before the latest data */\r\n    hspi->Instance->CR1|= SPI_CR1_CRCNEXT;\r\n\r\n    /* Read the latest data */\r\n    if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)\r\n    {\r\n      /* the latest data has not been received */\r\n      errorcode = HAL_TIMEOUT;\r\n      goto error;\r\n    }\r\n\r\n    /* Receive last data in 16 Bit mode */\r\n    if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r\n    {\r\n      *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;\r\n    }\r\n    /* Receive last data in 8 Bit mode */\r\n    else\r\n    {\r\n      *hspi->pRxBuffPtr = *(__IO uint8_t *)&hspi->Instance->DR;\r\n    }\r\n\r\n    /* Wait until TXE flag */\r\n    if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)\r\n    {\r\n      /* Flag Error*/\r\n      hspi->ErrorCode = HAL_SPI_ERROR_CRC;\r\n      errorcode = HAL_TIMEOUT;\r\n      goto error;\r\n    }\r\n\r\n    if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)\r\n    {\r\n      tmpreg = hspi->Instance->DR;\r\n      UNUSED(tmpreg); /* To avoid GCC warning */\r\n    }\r\n    else\r\n    {\r\n      tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;\r\n      UNUSED(tmpreg); /* To avoid GCC warning */\r\n\r\n      if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))\r\n      {\r\n        if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)\r\n        {\r\n          /* Error on the CRC reception */\r\n          hspi->ErrorCode = HAL_SPI_ERROR_CRC;\r\n          errorcode = HAL_TIMEOUT;\r\n          goto error;\r\n        }\r\n        tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;\r\n        UNUSED(tmpreg); /* To avoid GCC warning */\r\n      }\r\n    }\r\n  }\r\n#endif\r\n\r\n  /* Check the end of the transaction */\r\n  if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK)\r\n  {\r\n    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;\r\n  }\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Check if CRC error occurred */\r\n  if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)\r\n  {\r\n    hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r\n    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r\n  }\r\n#endif\r\n\r\n  if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r\n  {\r\n    errorcode = HAL_ERROR;\r\n  }\r\n\r\nerror :\r\n  hspi->State = HAL_SPI_STATE_READY;\r\n  __HAL_UNLOCK(hspi);\r\n  return errorcode;\r\n}\r\n\r\n/**\r\n  * @brief  Transmit and Receive an amount of data in blocking mode.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @param  pTxData: pointer to transmission data buffer\r\n  * @param  pRxData: pointer to reception data buffer\r\n  * @param  Size: amount of data to be sent and received\r\n  * @param  Timeout: Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)\r\n{\r\n#if (USE_SPI_CRC != 0U)\r\n  __IO uint16_t tmpreg;\r\n#endif\r\n  uint32_t tickstart = HAL_GetTick();\r\n  /* Variable used to alternate Rx and Tx during transfer */\r\n  uint32_t txallowed = 1U;\r\n\r\n  HAL_StatusTypeDef errorcode = HAL_OK;\r\n\r\n  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));\r\n\r\n  /* Process Locked */\r\n  __HAL_LOCK(hspi);\r\n\r\n  if(hspi->State != HAL_SPI_STATE_READY)\r\n  {\r\n    errorcode = HAL_BUSY;\r\n    goto error;\r\n  }\r\n\r\n  if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))\r\n  {\r\n    errorcode = HAL_ERROR;\r\n    goto error;\r\n  }\r\n\r\n  hspi->State       = HAL_SPI_STATE_BUSY_TX_RX;\r\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r\n  hspi->pRxBuffPtr  = pRxData;\r\n  hspi->RxXferCount = Size;\r\n  hspi->RxXferSize  = Size;\r\n  hspi->pTxBuffPtr  = pTxData;\r\n  hspi->TxXferCount = Size;\r\n  hspi->TxXferSize  = Size;\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Reset CRC Calculation */\r\n  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n  {\r\n    SPI_RESET_CRC(hspi);\r\n  }\r\n#endif\r\n\r\n  /* Set the Rx Fifo threshold */\r\n  if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1))\r\n  {\r\n    /* set fiforxthreshold according the reception data length: 16bit */\r\n    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r\n  }\r\n  else\r\n  {\r\n    /* set fiforxthreshold according the reception data length: 8bit */\r\n    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r\n  }\r\n\r\n  /* Check if the SPI is already enabled */\r\n  if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)\r\n  {\r\n    /* Enable SPI peripheral */\r\n    __HAL_SPI_ENABLE(hspi);\r\n  }\r\n\r\n  /* Transmit and Receive data in 16 Bit mode */\r\n  if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r\n  {\r\n    while ((hspi->TxXferCount > 0 ) || (hspi->RxXferCount > 0))\r\n    {\r\n      /* Check TXE flag */\r\n      if(txallowed && ((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)))\r\n      {\r\n        hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r\n        hspi->pTxBuffPtr += sizeof(uint16_t);\r\n        hspi->TxXferCount--;\r\n        /* Next Data is a reception (Rx). Tx not allowed */\r\n        txallowed = 0U;\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n        /* Enable CRC Transmission */\r\n        if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\r\n        {\r\n          /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */\r\n          if(((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))\r\n          {\r\n            SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);\r\n          }\r\n          SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r\n        }\r\n#endif\r\n      }\r\n      /* Check RXNE flag */\r\n      if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))\r\n      {\r\n        *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;\r\n        hspi->pRxBuffPtr += sizeof(uint16_t);\r\n        hspi->RxXferCount--;\r\n        /* Next Data is a reception (Rx). Tx not allowed */\r\n        txallowed = 1U;\r\n      }\r\n      if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout))\r\n      {\r\n        errorcode = HAL_TIMEOUT;\r\n        goto error;\r\n      }\r\n    }\r\n  }\r\n  /* Transmit and Receive data in 8 Bit mode */\r\n  else\r\n  {\r\n    while((hspi->TxXferCount > 0) || (hspi->RxXferCount > 0))\r\n    {\r\n      /* check TXE flag */\r\n      if(txallowed && ((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)))\r\n      {\r\n        if(hspi->TxXferCount > 1)\r\n        {\r\n          hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);\r\n          hspi->pTxBuffPtr += sizeof(uint16_t);\r\n          hspi->TxXferCount -= 2;\r\n        }\r\n        else\r\n        {\r\n          *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);\r\n          hspi->TxXferCount--;\r\n          /* Next Data is a reception (Rx). Tx not allowed */\r\n        txallowed = 0U;\r\n        }\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n        /* Enable CRC Transmission */\r\n        if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\r\n        {\r\n          /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */\r\n          if(((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))\r\n          {\r\n            SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);\r\n          }\r\n          SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\r\n        }\r\n#endif\r\n      }\r\n\r\n      /* Wait until RXNE flag is reset */\r\n      if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))\r\n      {\r\n        if(hspi->RxXferCount > 1)\r\n        {\r\n          *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;\r\n          hspi->pRxBuffPtr += sizeof(uint16_t);\r\n          hspi->RxXferCount -= 2;\r\n          if(hspi->RxXferCount <= 1)\r\n          {\r\n            /* set fiforxthreshold before to switch on 8 bit data size */\r\n            SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r\n          }\r\n        }\r\n        else\r\n        {\r\n          (*hspi->pRxBuffPtr++) =  *(__IO uint8_t *)&hspi->Instance->DR;\r\n          hspi->RxXferCount--;\r\n          /* Next Data is a Transmission (Tx). Tx is allowed */\r\n          txallowed = 1U;\r\n        }\r\n      }\r\n      if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout))\r\n      {\r\n        errorcode = HAL_TIMEOUT;\r\n        goto error;\r\n      }\r\n    }\r\n  }\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Read CRC from DR to close CRC calculation process */\r\n  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n  {\r\n    /* Wait until TXE flag */\r\n    if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)\r\n    {\r\n      /* Error on the CRC reception */\r\n      hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r\n      errorcode = HAL_TIMEOUT;\r\n      goto error;\r\n    }\r\n\r\n    if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)\r\n    {\r\n      tmpreg = hspi->Instance->DR;\r\n      UNUSED(tmpreg); /* To avoid GCC warning */\r\n    }\r\n    else\r\n    {\r\n      tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;\r\n      UNUSED(tmpreg); /* To avoid GCC warning */\r\n\r\n      if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)\r\n      {\r\n        if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)\r\n        {\r\n          /* Error on the CRC reception */\r\n          hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r\n          errorcode = HAL_TIMEOUT;\r\n          goto error;\r\n        }\r\n        tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;\r\n        UNUSED(tmpreg); /* To avoid GCC warning */\r\n      }\r\n    }\r\n  }\r\n\r\n  /* Check if CRC error occurred */\r\n  if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)\r\n  {\r\n    hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r\n    /* Clear CRC Flag */\r\n    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r\n\r\n    errorcode = HAL_ERROR;\r\n  }\r\n#endif\r\n\r\n  /* Check the end of the transaction */\r\n  if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)\r\n  {\r\n    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;\r\n  }\r\n\r\n  if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r\n  {\r\n    errorcode = HAL_ERROR;\r\n  }\r\n\r\nerror :\r\n  hspi->State = HAL_SPI_STATE_READY;\r\n  __HAL_UNLOCK(hspi);\r\n  return errorcode;\r\n}\r\n\r\n/**\r\n  * @brief  Transmit an amount of data in non-blocking mode with Interrupt.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @param  pData: pointer to data buffer\r\n  * @param  Size: amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\r\n{\r\n  HAL_StatusTypeDef errorcode = HAL_OK;\r\n  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));\r\n\r\n  /* Process Locked */\r\n  __HAL_LOCK(hspi);\r\n\r\n  if((pData == NULL) || (Size == 0))\r\n  {\r\n    errorcode = HAL_ERROR;\r\n    goto error;\r\n  }\r\n\r\n  if(hspi->State != HAL_SPI_STATE_READY)\r\n  {\r\n    errorcode = HAL_BUSY;\r\n    goto error;\r\n  }\r\n\r\n  /* prepare the transfer */\r\n  hspi->State       = HAL_SPI_STATE_BUSY_TX;\r\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r\n  hspi->pTxBuffPtr  = pData;\r\n  hspi->TxXferSize  = Size;\r\n  hspi->TxXferCount = Size;\r\n  hspi->pRxBuffPtr  = (uint8_t *)NULL;\r\n  hspi->RxXferSize  = 0;\r\n  hspi->RxXferCount = 0;\r\n  hspi->RxISR = NULL;\r\n\r\n  /* Set the function for IT treatment */\r\n  if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )\r\n  {\r\n    hspi->TxISR = SPI_TxISR_16BIT;\r\n  }\r\n  else\r\n  {\r\n    hspi->TxISR = SPI_TxISR_8BIT;\r\n  }\r\n\r\n  /* Configure communication direction : 1Line */\r\n  if(hspi->Init.Direction == SPI_DIRECTION_1LINE)\r\n  {\r\n    SPI_1LINE_TX(hspi);\r\n  }\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Reset CRC Calculation */\r\n  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n  {\r\n    SPI_RESET_CRC(hspi);\r\n  }\r\n#endif\r\n\r\n  /* Enable TXE and ERR interrupt */\r\n  __HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE));\r\n\r\n  /* Check if the SPI is already enabled */\r\n  if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)\r\n  {\r\n    /* Enable SPI peripheral */\r\n    __HAL_SPI_ENABLE(hspi);\r\n  }\r\n\r\nerror :\r\n  __HAL_UNLOCK(hspi);\r\n  return errorcode;\r\n}\r\n\r\n/**\r\n  * @brief  Receive an amount of data in non-blocking mode with Interrupt.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @param  pData: pointer to data buffer\r\n  * @param  Size: amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\r\n{\r\n  HAL_StatusTypeDef errorcode = HAL_OK;\r\n\r\n  /* Process Locked */\r\n  __HAL_LOCK(hspi);\r\n\r\n  if(hspi->State != HAL_SPI_STATE_READY)\r\n  {\r\n    errorcode = HAL_BUSY;\r\n    goto error;\r\n  }\r\n  if((pData == NULL) || (Size == 0))\r\n  {\r\n    errorcode = HAL_ERROR;\r\n    goto error;\r\n  }\r\n\r\n  /* Configure communication */\r\n  hspi->State       = HAL_SPI_STATE_BUSY_RX;\r\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r\n  hspi->pRxBuffPtr  = pData;\r\n  hspi->RxXferSize  = Size;\r\n  hspi->RxXferCount = Size;\r\n  hspi->pTxBuffPtr  = (uint8_t *)NULL;\r\n  hspi->TxXferSize  = 0;\r\n  hspi->TxXferCount = 0;\r\n\r\n  if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))\r\n  {\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hspi);\r\n    /* the receive process is not supported in 2Lines direction master mode */\r\n    /* in this we call the TransmitReceive process          */\r\n    return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size);\r\n  }\r\n\r\n  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n  {\r\n    hspi->CRCSize = 1;\r\n    if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))\r\n    {\r\n      hspi->CRCSize = 2;\r\n    }\r\n  }\r\n  else\r\n  {\r\n    hspi->CRCSize = 0;\r\n  }\r\n\r\n  hspi->TxISR = NULL;\r\n  /* check the data size to adapt Rx threshold and the set the function for IT treatment */\r\n  if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )\r\n  {\r\n    /* set fiforxthresold according the reception data length: 16 bit */\r\n    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r\n    hspi->RxISR = SPI_RxISR_16BIT;\r\n  }\r\n  else\r\n  {\r\n    /* set fiforxthresold according the reception data length: 8 bit */\r\n    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r\n    hspi->RxISR = SPI_RxISR_8BIT;\r\n  }\r\n\r\n  /* Configure communication direction : 1Line */\r\n  if(hspi->Init.Direction == SPI_DIRECTION_1LINE)\r\n  {\r\n    SPI_1LINE_RX(hspi);\r\n  }\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Reset CRC Calculation */\r\n  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n  {\r\n    SPI_RESET_CRC(hspi);\r\n  }\r\n#endif\r\n\r\n  /* Enable TXE and ERR interrupt */\r\n  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\r\n\r\n  /* Check if the SPI is already enabled */\r\n  if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r\n  {\r\n    /* Enable SPI peripheral */\r\n    __HAL_SPI_ENABLE(hspi);\r\n  }\r\n\r\nerror :\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hspi);\r\n  return errorcode;\r\n}\r\n\r\n/**\r\n  * @brief  Transmit and Receive an amount of data in non-blocking mode with Interrupt.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @param  pTxData: pointer to transmission data buffer\r\n  * @param  pRxData: pointer to reception data buffer\r\n  * @param  Size: amount of data to be sent and received\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)\r\n{\r\n  HAL_StatusTypeDef errorcode = HAL_OK;\r\n  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hspi);\r\n\r\n  if(!((hspi->State == HAL_SPI_STATE_READY) || \\\r\n    ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))\r\n  {\r\n    errorcode = HAL_BUSY;\r\n    goto error;\r\n  }\r\n\r\n  if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))\r\n  {\r\n    errorcode = HAL_ERROR;\r\n    goto error;\r\n  }\r\n\r\n  hspi->CRCSize = 0;\r\n  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n  {\r\n    hspi->CRCSize = 1;\r\n    if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))\r\n    {\r\n      hspi->CRCSize = 2;\r\n    }\r\n  }\r\n\r\n  if(hspi->State != HAL_SPI_STATE_BUSY_RX)\r\n  {\r\n    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;\r\n  }\r\n\r\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r\n  hspi->pTxBuffPtr  = pTxData;\r\n  hspi->TxXferSize  = Size;\r\n  hspi->TxXferCount = Size;\r\n  hspi->pRxBuffPtr  = pRxData;\r\n  hspi->RxXferSize  = Size;\r\n  hspi->RxXferCount = Size;\r\n\r\n  /* Set the function for IT treatment */\r\n  if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )\r\n  {\r\n    hspi->RxISR = SPI_2linesRxISR_16BIT;\r\n    hspi->TxISR = SPI_2linesTxISR_16BIT;\r\n  }\r\n  else\r\n  {\r\n    hspi->RxISR = SPI_2linesRxISR_8BIT;\r\n    hspi->TxISR = SPI_2linesTxISR_8BIT;\r\n  }\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Reset CRC Calculation */\r\n  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n  {\r\n    SPI_RESET_CRC(hspi);\r\n  }\r\n#endif\r\n\r\n  /* check if packing mode is enabled and if there is more than 2 data to receive */\r\n  if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2))\r\n  {\r\n    /* set fiforxthresold according the reception data length: 16 bit */\r\n    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r\n  }\r\n  else\r\n  {\r\n    /* set fiforxthresold according the reception data length: 8 bit */\r\n    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r\n  }\r\n\r\n  /* Enable TXE, RXNE and ERR interrupt */\r\n  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));\r\n\r\n  /* Check if the SPI is already enabled */\r\n  if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r\n  {\r\n    /* Enable SPI peripheral */\r\n    __HAL_SPI_ENABLE(hspi);\r\n  }\r\n\r\nerror :\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hspi);\r\n  return errorcode;\r\n}\r\n\r\n/**\r\n  * @brief  Transmit an amount of data in non-blocking mode with DMA.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @param  pData: pointer to data buffer\r\n  * @param  Size: amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\r\n{\r\n  HAL_StatusTypeDef errorcode = HAL_OK;\r\n  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));\r\n\r\n  /* Process Locked */\r\n  __HAL_LOCK(hspi);\r\n\r\n  if(hspi->State != HAL_SPI_STATE_READY)\r\n  {\r\n    errorcode = HAL_BUSY;\r\n    goto error;\r\n  }\r\n\r\n  if((pData == NULL) || (Size == 0))\r\n  {\r\n    errorcode = HAL_ERROR;\r\n    goto error;\r\n  }\r\n\r\n  hspi->State       = HAL_SPI_STATE_BUSY_TX;\r\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r\n  hspi->pTxBuffPtr  = pData;\r\n  hspi->TxXferSize  = Size;\r\n  hspi->TxXferCount = Size;\r\n  hspi->pRxBuffPtr  = (uint8_t *)NULL;\r\n  hspi->RxXferSize  = 0;\r\n  hspi->RxXferCount = 0;\r\n\r\n  /* Configure communication direction : 1Line */\r\n  if(hspi->Init.Direction == SPI_DIRECTION_1LINE)\r\n  {\r\n    SPI_1LINE_TX(hspi);\r\n  }\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Reset CRC Calculation */\r\n  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n  {\r\n    SPI_RESET_CRC(hspi);\r\n  }\r\n#endif\r\n\r\n  /* Set the SPI TxDMA Half transfer complete callback */\r\n  hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;\r\n\r\n  /* Set the SPI TxDMA transfer complete callback */\r\n  hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;\r\n\r\n  /* Set the DMA error callback */\r\n  hspi->hdmatx->XferErrorCallback = SPI_DMAError;\r\n\r\n  /* Set the DMA abort callback */\r\n  hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;\r\n\r\n  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r\n  /* packing mode is enabled only if the DMA setting is HALWORD */\r\n  if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))\r\n  {\r\n    /* Check the even/odd of the data size + crc if enabled */\r\n    if((hspi->TxXferCount & 0x1) == 0)\r\n    {\r\n      CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r\n      hspi->TxXferCount = (hspi->TxXferCount >> 1);\r\n    }\r\n    else\r\n    {\r\n      SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r\n      hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;\r\n    }\r\n  }\r\n\r\n  /* Enable SPI Error interrupts, EIE: MODF, OVR, FE, FRE, CEC(depends on family) */\r\n  SET_BIT(hspi->Instance->CR2, (SPI_CR2_ERRIE));\r\n  SET_BIT(hspi->Instance->SR, (SPI_SR_FRE | SPI_SR_OVR | SPI_SR_MODF | SPI_SR_CRCERR));\r\n\r\n  /* Enable the Tx DMA channel */\r\n  HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);\r\n\r\n  /* Check if the SPI is already enabled */\r\n  if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)\r\n  {\r\n    /* Enable SPI peripheral */\r\n    __HAL_SPI_ENABLE(hspi);\r\n  }\r\n\r\n  /* Enable Tx DMA Request */\r\n  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);\r\n\r\nerror :\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hspi);\r\n  return errorcode;\r\n}\r\n\r\n/**\r\n  * @brief  Receive an amount of data in non-blocking mode with DMA.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @param  pData: pointer to data buffer\r\n  * @note  When the CRC feature is enabled the pData Length must be Size + 1.\r\n  * @param  Size: amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\r\n{\r\n  HAL_StatusTypeDef errorcode = HAL_OK;\r\n\r\n  /* Process Locked */\r\n  __HAL_LOCK(hspi);\r\n\r\n  if(hspi->State != HAL_SPI_STATE_READY)\r\n  {\r\n    errorcode = HAL_BUSY;\r\n    goto error;\r\n  }\r\n\r\n  if((pData == NULL) || (Size == 0))\r\n  {\r\n    errorcode = HAL_ERROR;\r\n    goto error;\r\n  }\r\n\r\n  hspi->State       = HAL_SPI_STATE_BUSY_RX;\r\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r\n  hspi->pRxBuffPtr  = pData;\r\n  hspi->RxXferSize  = Size;\r\n  hspi->RxXferCount = Size;\r\n  hspi->pTxBuffPtr  = (uint8_t *)NULL;\r\n  hspi->TxXferSize  = 0;\r\n  hspi->TxXferCount = 0;\r\n\r\n  if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))\r\n  {\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(hspi);\r\n    /* the receive process is not supported in 2Lines direction master mode */\r\n    /* in this case we call the TransmitReceive process                     */\r\n    return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size);\r\n  }\r\n\r\n  /* Configure communication direction : 1Line */\r\n  if(hspi->Init.Direction == SPI_DIRECTION_1LINE)\r\n  {\r\n    SPI_1LINE_RX(hspi);\r\n  }\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Reset CRC Calculation */\r\n  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n  {\r\n    SPI_RESET_CRC(hspi);\r\n  }\r\n#endif\r\n\r\n  /* packing mode management is enabled by the DMA settings */\r\n  if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))\r\n  {\r\n    /* Restriction the DMA data received is not allowed in this mode */\r\n    errorcode = HAL_ERROR;\r\n    goto error;\r\n  }\r\n\r\n  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);\r\n  if( hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r\n  {\r\n    /* set fiforxthreshold according the reception data length: 16bit */\r\n    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r\n  }\r\n  else\r\n  {\r\n    /* set fiforxthreshold according the reception data length: 8bit */\r\n    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r\n  }\r\n\r\n  /* Set the SPI RxDMA Half transfer complete callback */\r\n  hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;\r\n\r\n  /* Set the SPI Rx DMA transfer complete callback */\r\n  hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;\r\n\r\n  /* Set the DMA error callback */\r\n  hspi->hdmarx->XferErrorCallback = SPI_DMAError;\r\n\r\n  /* Set the DMA abort callback */\r\n  hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;\r\n\r\n  /* Enable SPI Error interrupts, EIE: MODF, OVR, FE, FRE, CEC(depends on family) */\r\n  SET_BIT(hspi->Instance->CR2, (SPI_CR2_ERRIE));\r\n  SET_BIT(hspi->Instance->SR, (SPI_SR_FRE | SPI_SR_OVR | SPI_SR_MODF | SPI_SR_CRCERR));\r\n\r\n  /* Enable Rx DMA Request */\r\n  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);\r\n\r\n  /* Enable the Rx DMA channel */\r\n  HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);\r\n\r\n  /* Check if the SPI is already enabled */\r\n  if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\r\n  {\r\n    /* Enable SPI peripheral */\r\n    __HAL_SPI_ENABLE(hspi);\r\n  }\r\n\r\nerror:\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hspi);\r\n  return errorcode;\r\n}\r\n\r\n/**\r\n  * @brief  Transmit and Receive an amount of data in non-blocking mode with DMA.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @param  pTxData: pointer to transmission data buffer\r\n  * @param  pRxData: pointer to reception data buffer\r\n  * @note  When the CRC feature is enabled the pRxData Length must be Size + 1\r\n  * @param  Size: amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)\r\n{\r\n  HAL_StatusTypeDef errorcode = HAL_OK;\r\n  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));\r\n\r\n  /* Process locked */\r\n  __HAL_LOCK(hspi);\r\n\r\n  if(!((hspi->State == HAL_SPI_STATE_READY) ||\r\n      ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))\r\n  {\r\n    errorcode = HAL_BUSY;\r\n    goto error;\r\n  }\r\n\r\n  if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))\r\n  {\r\n    errorcode = HAL_ERROR;\r\n    goto error;\r\n  }\r\n\r\n  /* check if the transmit Receive function is not called by a receive master */\r\n  if(hspi->State != HAL_SPI_STATE_BUSY_RX)\r\n  {\r\n    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;\r\n  }\r\n\r\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\r\n  hspi->pTxBuffPtr  = (uint8_t *)pTxData;\r\n  hspi->TxXferSize  = Size;\r\n  hspi->TxXferCount = Size;\r\n  hspi->pRxBuffPtr  = (uint8_t *)pRxData;\r\n  hspi->RxXferSize  = Size;\r\n  hspi->RxXferCount = Size;\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Reset CRC Calculation + increase the rxsize */\r\n  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n  {\r\n    SPI_RESET_CRC(hspi);\r\n  }\r\n#endif\r\n\r\n  /* Reset the threshold bit */\r\n  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);\r\n\r\n  /* the packing mode management is enabled by the DMA settings according the spi data size */\r\n  if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r\n  {\r\n    /* set fiforxthreshold according the reception data length: 16bit */\r\n    CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r\n  }\r\n  else\r\n  {\r\n    /* set fiforxthresold according the reception data length: 8bit */\r\n    SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r\n\r\n    if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)\r\n    {\r\n      if((hspi->TxXferSize & 0x1) == 0x0)\r\n      {\r\n        CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r\n        hspi->TxXferCount = hspi->TxXferCount >> 1;\r\n      }\r\n      else\r\n      {\r\n        SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);\r\n        hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;\r\n      }\r\n    }\r\n\r\n    if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)\r\n    {\r\n      /* set fiforxthresold according the reception data length: 16bit */\r\n      CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r\n\r\n      if((hspi->RxXferCount & 0x1) == 0x0 )\r\n      {\r\n        CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);\r\n        hspi->RxXferCount = hspi->RxXferCount >> 1;\r\n      }\r\n      else\r\n      {\r\n        SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);\r\n        hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1;\r\n      }\r\n    }\r\n  }\r\n\r\n  /* Set the SPI Rx DMA transfer complete callback if the transfer request is a\r\n     reception request (RXNE) */\r\n  if(hspi->State == HAL_SPI_STATE_BUSY_RX)\r\n  {\r\n    /* Set the SPI Rx DMA Half transfer complete callback */\r\n    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;\r\n    hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;\r\n  }\r\n  else\r\n  {\r\n    /* Set the SPI Rx DMA Half transfer complete callback */\r\n    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;\r\n    hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;\r\n  }\r\n\r\n  /* Set the DMA error callback */\r\n  hspi->hdmarx->XferErrorCallback = SPI_DMAError;\r\n\r\n  /* Set the DMA abort callback */\r\n  hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;\r\n\r\n  /* Enable SPI Error interrupts, EIE: MODF, OVR, FE, FRE, CEC(depends on family) */\r\n  SET_BIT(hspi->Instance->CR2, (SPI_CR2_ERRIE));\r\n  SET_BIT(hspi->Instance->SR, (SPI_SR_FRE | SPI_SR_OVR | SPI_SR_MODF | SPI_SR_CRCERR));\r\n\r\n  /* Enable Rx DMA Request */\r\n  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);\r\n\r\n  /* Enable the Rx DMA channel */\r\n  HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount);\r\n\r\n  /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing\r\n  is performed in DMA reception complete callback  */\r\n  hspi->hdmatx->XferHalfCpltCallback = NULL;\r\n  hspi->hdmatx->XferCpltCallback = NULL;\r\n\r\n  /* Set the DMA error callback */\r\n  hspi->hdmatx->XferErrorCallback = SPI_DMAError;\r\n\r\n  /* Set the DMA abort callback */\r\n  hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;\r\n\r\n  /* Enable the Tx DMA channel */\r\n  HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);\r\n\r\n  /* Check if the SPI is already enabled */\r\n  if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)\r\n  {\r\n    /* Enable SPI peripheral */\r\n    __HAL_SPI_ENABLE(hspi);\r\n  }\r\n\r\n  /* Enable Tx DMA Request */\r\n  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);\r\n\r\nerror :\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hspi);\r\n  return errorcode;\r\n}\r\n\r\n/**\r\n  * @brief Pause the DMA Transfer.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified SPI module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hspi);\r\n\r\n  /* Disable the SPI DMA Tx & Rx requests */\r\n  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hspi);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Resumes the DMA Transfer.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified SPI module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hspi);\r\n\r\n  /* Enable the SPI DMA Tx & Rx requests */\r\n  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(hspi);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Stops the DMA Transfer.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified SPI module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)\r\n{\r\n  /* The Lock is not implemented on this API to allow the user application\r\n  to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():\r\n  when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated\r\n  and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()\r\n  */\r\n\r\n  /* Abort the SPI DMA tx Stream */\r\n  if(hspi->hdmatx != NULL)\r\n  {\r\n    HAL_DMA_Abort(hspi->hdmatx);\r\n  }\r\n  /* Abort the SPI DMA rx Stream */\r\n  if(hspi->hdmarx != NULL)\r\n  {\r\n    HAL_DMA_Abort(hspi->hdmarx);\r\n  }\r\n\r\n  /* Disable the SPI DMA Tx & Rx requests */\r\n  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r\n  hspi->State = HAL_SPI_STATE_READY;\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  This function handles SPI interrupt request.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified SPI module.\r\n  * @retval None\r\n  */\r\nvoid HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)\r\n{\r\n  uint32_t itsource = hspi->Instance->CR2;\r\n  uint32_t itflag   = hspi->Instance->SR;\r\n\r\n  /* SPI in mode Receiver ----------------------------------------------------*/\r\n  if(((itflag & SPI_FLAG_OVR) == RESET) &&\r\n     ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))\r\n  {\r\n    hspi->RxISR(hspi);\r\n    return;\r\n  }\r\n\r\n  /* SPI in mode Transmitter ---------------------------------------------------*/\r\n  if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))\r\n  {\r\n    hspi->TxISR(hspi);\r\n    return;\r\n  }\r\n\r\n  /* SPI in Error Treatment ---------------------------------------------------*/\r\n  if((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET)\r\n  {\r\n    /* SPI Overrun error interrupt occurred -------------------------------------*/\r\n    if((itflag & SPI_FLAG_OVR) != RESET)\r\n    {\r\n      if(hspi->State != HAL_SPI_STATE_BUSY_TX)\r\n      {\r\n        hspi->ErrorCode |= HAL_SPI_ERROR_OVR;\r\n        __HAL_SPI_CLEAR_OVRFLAG(hspi);\r\n      }\r\n      else\r\n      {\r\n        return;\r\n      }\r\n    }\r\n\r\n    /* SPI Mode Fault error interrupt occurred -------------------------------------*/\r\n    if((itflag & SPI_FLAG_MODF) != RESET)\r\n    {\r\n      hspi->ErrorCode |= HAL_SPI_ERROR_MODF;\r\n      __HAL_SPI_CLEAR_MODFFLAG(hspi);\r\n    }\r\n\r\n    /* SPI Frame error interrupt occurred ----------------------------------------*/\r\n    if((itflag & SPI_FLAG_FRE) != RESET)\r\n    {\r\n      hspi->ErrorCode |= HAL_SPI_ERROR_FRE;\r\n      __HAL_SPI_CLEAR_FREFLAG(hspi);\r\n    }\r\n\r\n    if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r\n    {\r\n      /* All SPI errors are treated as Blocking errors : transfer is aborted.\r\n      Set the SPI state to ready so as to be able to restart the process,\r\n      Disable Rx/Tx Interrupts, and disable DMA Rx/Tx requests, if ongoing */\r\n\r\n      /* Disable TXE, RXNE, MODF, OVR, FRE, and CRCERR (Master mode fault, Overrun error, TI frame format error, CRC protocol error) interrupts */\r\n      CLEAR_BIT(hspi->Instance->CR1, (SPI_CR2_RXNEIE | SPI_CR2_TXEIE | SPI_CR2_ERRIE));\r\n      CLEAR_BIT(hspi->Instance->SR, (SPI_SR_FRE | SPI_SR_OVR | SPI_SR_MODF | SPI_SR_CRCERR));\r\n\r\n      /* Restore SPI State to Ready */\r\n      hspi->State = HAL_SPI_STATE_READY;\r\n\r\n      /* Disable the SPI DMA requests if enabled */\r\n      if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))||(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))\r\n      {\r\n        CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));\r\n\r\n        /* Abort the SPI DMA Rx channel */\r\n        if(hspi->hdmarx != NULL)\r\n        {\r\n          /* Set the SPI DMA Abort callback :\r\n          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */\r\n          hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;\r\n\r\n          /* Abort DMA RX */\r\n          if(HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)\r\n          {\r\n            /* Call Directly hspi->hdmarx->XferAbortCallback function in case of error */\r\n            hspi->hdmarx->XferAbortCallback(hspi->hdmarx);\r\n          }\r\n        }\r\n        /* Abort the SPI DMA Tx channel */\r\n        if(hspi->hdmatx != NULL)\r\n        {\r\n          /* Set the SPI DMA Abort callback :\r\n          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */\r\n          hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;\r\n\r\n          /* Abort DMA TX */\r\n          if(HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)\r\n          {\r\n            /* Call Directly hspi->hdmatx->XferAbortCallback function in case of error */\r\n            hspi->hdmatx->XferAbortCallback(hspi->hdmatx);\r\n          }\r\n        }\r\n      }\r\n      else\r\n      {\r\n        /* Call user error callback */\r\n        HAL_SPI_ErrorCallback(hspi);\r\n      }\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Tx Transfer completed callback.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hspi);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n  the HAL_SPI_TxCpltCallback should be implemented in the user file\r\n  */\r\n}\r\n\r\n/**\r\n  * @brief Rx Transfer completed callback.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hspi);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n  the HAL_SPI_RxCpltCallback should be implemented in the user file\r\n  */\r\n}\r\n\r\n/**\r\n  * @brief Tx and Rx Transfer completed callback.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hspi);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n  the HAL_SPI_TxRxCpltCallback should be implemented in the user file\r\n  */\r\n}\r\n\r\n/**\r\n  * @brief Tx Half Transfer completed callback.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hspi);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n  the HAL_SPI_TxHalfCpltCallback should be implemented in the user file\r\n  */\r\n}\r\n\r\n/**\r\n  * @brief Rx Half Transfer completed callback.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hspi);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n  the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file\r\n  */\r\n}\r\n\r\n/**\r\n  * @brief Tx and Rx Half Transfer callback.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hspi);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n  the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file\r\n  */\r\n}\r\n\r\n/**\r\n  * @brief SPI error callback.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hspi);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n  the HAL_SPI_ErrorCallback should be implemented in the user file\r\n  */\r\n  /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes\r\n  and user can use HAL_SPI_GetError() API to check the latest error occurred\r\n  */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions\r\n  *  @brief   SPI control functions\r\n  *\r\n@verbatim\r\n ===============================================================================\r\n                      ##### Peripheral State and Errors functions #####\r\n ===============================================================================\r\n    [..]\r\n    This subsection provides a set of functions allowing to control the SPI.\r\n     (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral\r\n     (+) HAL_SPI_GetError() check in run-time Errors occurring during communication\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Return the SPI handle state.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval SPI state\r\n  */\r\nHAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Return SPI handle state */\r\n  return hspi->State;\r\n}\r\n\r\n/**\r\n  * @brief  Return the SPI error code.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval SPI error code in bitmap format\r\n  */\r\nuint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)\r\n{\r\n  return hspi->ErrorCode;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup SPI_Private_Functions\r\n *  @brief   Private functions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief DMA SPI transmit process complete callback.\r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n\r\n  /* DMA Normal Mode */\r\n  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)\r\n  {\r\n    /* Disable Tx DMA Request */\r\n    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);\r\n\r\n    /* Check the end of the transaction */\r\n    if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK)\r\n    {\r\n      hspi->ErrorCode = HAL_SPI_ERROR_FLAG;\r\n    }\r\n\r\n    /* Clear overrun flag in 2 Lines communication mode because received data is not read */\r\n    if(hspi->Init.Direction == SPI_DIRECTION_2LINES)\r\n    {\r\n      __HAL_SPI_CLEAR_OVRFLAG(hspi);\r\n    }\r\n\r\n    hspi->TxXferCount = 0;\r\n    hspi->State = HAL_SPI_STATE_READY;\r\n\r\n    if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r\n    {\r\n      HAL_SPI_ErrorCallback(hspi);\r\n      return;\r\n    }\r\n  }\r\n  HAL_SPI_TxCpltCallback(hspi);\r\n}\r\n\r\n/**\r\n  * @brief DMA SPI receive process complete callback.\r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n\r\n  /* DMA Normal mode */\r\n  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)\r\n  {\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n    __IO uint16_t tmpreg;\r\n    /* CRC handling */\r\n    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n    {\r\n      /* Wait until TXE flag */\r\n      if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)\r\n      {\r\n        /* Error on the CRC reception */\r\n        hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r\n      }\r\n      if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)\r\n      {\r\n        tmpreg = hspi->Instance->DR;\r\n        UNUSED(tmpreg); /* To avoid GCC warning */\r\n      }\r\n      else\r\n      {\r\n        tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;\r\n        UNUSED(tmpreg); /* To avoid GCC warning */\r\n\r\n        if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)\r\n        {\r\n          if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)\r\n          {\r\n            /* Error on the CRC reception */\r\n            hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r\n          }\r\n          tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;\r\n          UNUSED(tmpreg); /* To avoid GCC warning */\r\n        }\r\n      }\r\n    }\r\n#endif\r\n\r\n    /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */\r\n    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r\n\r\n    /* Check the end of the transaction */\r\n    if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)\r\n    {\r\n      hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;\r\n    }\r\n\r\n    hspi->RxXferCount = 0;\r\n    hspi->State = HAL_SPI_STATE_READY;\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n    /* Check if CRC error occurred */\r\n    if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)\r\n    {\r\n      hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r\n      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r\n    }\r\n#endif\r\n\r\n    if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r\n    {\r\n      HAL_SPI_ErrorCallback(hspi);\r\n      return;\r\n    }\r\n  }\r\n  HAL_SPI_RxCpltCallback(hspi);\r\n}\r\n\r\n/**\r\n  * @brief DMA SPI transmit receive process complete callback.\r\n  * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n#if (USE_SPI_CRC != 0U)\r\n  __IO uint16_t tmpreg;\r\n  /* CRC handling */\r\n  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n  {\r\n    if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))\r\n    {\r\n      if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)\r\n      {\r\n        /* Error on the CRC reception */\r\n        hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r\n      }\r\n      tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;\r\n      UNUSED(tmpreg); /* To avoid GCC warning */\r\n    }\r\n    else\r\n    {\r\n      if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)\r\n      {\r\n        /* Error on the CRC reception */\r\n        hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r\n      }\r\n      tmpreg = hspi->Instance->DR;\r\n      UNUSED(tmpreg); /* To avoid GCC warning */\r\n    }\r\n  }\r\n#endif\r\n\r\n  /* Check the end of the transaction */\r\n  if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK)\r\n  {\r\n    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;\r\n  }\r\n\r\n  /* Disable Rx/Tx DMA Request */\r\n  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r\n\r\n  hspi->TxXferCount = 0;\r\n  hspi->RxXferCount = 0;\r\n  hspi->State = HAL_SPI_STATE_READY;\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Check if CRC error occurred */\r\n  if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)\r\n  {\r\n    hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r\n    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r\n  }\r\n#endif\r\n\r\n  if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r\n  {\r\n    HAL_SPI_ErrorCallback(hspi);\r\n    return;\r\n  }\r\n  HAL_SPI_TxRxCpltCallback(hspi);\r\n}\r\n\r\n/**\r\n  * @brief DMA SPI half transmit process complete callback.\r\n  * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  HAL_SPI_TxHalfCpltCallback(hspi);\r\n}\r\n\r\n/**\r\n  * @brief DMA SPI half receive process complete callback.\r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  HAL_SPI_RxHalfCpltCallback(hspi);\r\n}\r\n\r\n/**\r\n  * @brief DMA SPI half transmit receive process complete callback.\r\n  * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  HAL_SPI_TxRxHalfCpltCallback(hspi);\r\n}\r\n\r\n/**\r\n  * @brief DMA SPI communication error callback.\r\n  * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains\r\n  *               the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_DMAError(DMA_HandleTypeDef *hdma)\r\n{\r\n  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n\r\n  /* Stop the disable DMA transfer on SPI side */\r\n  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\r\n\r\n  hspi->ErrorCode|= HAL_SPI_ERROR_DMA;\r\n  hspi->State = HAL_SPI_STATE_READY;\r\n  HAL_SPI_ErrorCallback(hspi);\r\n}\r\n\r\n/**\r\n  * @brief DMA SPI communication abort callback\r\n  *        (To be called at end of DMA Abort procedure).\r\n  * @param hdma: DMA handle.\r\n  * @retval None\r\n  */\r\nstatic void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)\r\n{\r\n  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  hspi->RxXferCount = 0U;\r\n  hspi->TxXferCount = 0U;\r\n\r\n  HAL_SPI_ErrorCallback(hspi);\r\n}\r\n\r\n/**\r\n  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Receive data in packing mode */\r\n  if(hspi->RxXferCount > 1)\r\n  {\r\n    *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;\r\n    hspi->pRxBuffPtr += sizeof(uint16_t);\r\n    hspi->RxXferCount -= 2;\r\n    if(hspi->RxXferCount == 1)\r\n    {\r\n      /* set fiforxthreshold according the reception data length: 8bit */\r\n      SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r\n    }\r\n  }\r\n  /* Receive data in 8 Bit mode */\r\n  else\r\n  {\r\n    *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);\r\n    hspi->RxXferCount--;\r\n  }\r\n\r\n  /* check end of the reception */\r\n  if(hspi->RxXferCount == 0)\r\n  {\r\n#if (USE_SPI_CRC != 0U)\r\n    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n    {\r\n      SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);\r\n      hspi->RxISR =  SPI_2linesRxISR_8BITCRC;\r\n      return;\r\n    }\r\n#endif\r\n\r\n    /* Disable RXNE interrupt */\r\n    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);\r\n\r\n    if(hspi->TxXferCount == 0)\r\n    {\r\n      SPI_CloseRxTx_ISR(hspi);\r\n    }\r\n  }\r\n}\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n/**\r\n  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)\r\n{\r\n  __IO uint8_t tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);\r\n  UNUSED(tmpreg); /* To avoid GCC warning */\r\n\r\n  hspi->CRCSize--;\r\n\r\n  /* check end of the reception */\r\n  if(hspi->CRCSize == 0)\r\n  {\r\n    /* Disable RXNE interrupt */\r\n    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);\r\n\r\n    if(hspi->TxXferCount == 0)\r\n    {\r\n      SPI_CloseRxTx_ISR(hspi);\r\n    }\r\n  }\r\n}\r\n#endif\r\n\r\n/**\r\n  * @brief  Tx 8-bit handler for Transmit and Receive in Interrupt mode.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Transmit data in packing Bit mode */\r\n  if(hspi->TxXferCount >= 2)\r\n  {\r\n    hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r\n    hspi->pTxBuffPtr += sizeof(uint16_t);\r\n    hspi->TxXferCount -= 2;\r\n  }\r\n  /* Transmit data in 8 Bit mode */\r\n  else\r\n  {\r\n    *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);\r\n    hspi->TxXferCount--;\r\n  }\r\n\r\n  /* check the end of the transmission */\r\n  if(hspi->TxXferCount == 0)\r\n  {\r\n#if (USE_SPI_CRC != 0U)\r\n    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n    {\r\n      hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;\r\n    }\r\n#endif\r\n\r\n    /* Disable TXE interrupt */\r\n    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);\r\n\r\n    if(hspi->RxXferCount == 0)\r\n    {\r\n      SPI_CloseRxTx_ISR(hspi);\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Rx 16-bit handler for Transmit and Receive in Interrupt mode.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Receive data in 16 Bit mode */\r\n  *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;\r\n  hspi->pRxBuffPtr += sizeof(uint16_t);\r\n  hspi->RxXferCount--;\r\n\r\n  if(hspi->RxXferCount == 0)\r\n  {\r\n#if (USE_SPI_CRC != 0U)\r\n    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n    {\r\n      hspi->RxISR =  SPI_2linesRxISR_16BITCRC;\r\n      return;\r\n    }\r\n#endif\r\n\r\n    /* Disable RXNE interrupt */\r\n    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);\r\n\r\n    if(hspi->TxXferCount == 0)\r\n    {\r\n      SPI_CloseRxTx_ISR(hspi);\r\n    }\r\n  }\r\n}\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n/**\r\n  * @brief  Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Receive data in 16 Bit mode */\r\n  __IO uint16_t tmpreg = hspi->Instance->DR;\r\n  UNUSED(tmpreg); /* To avoid GCC warning */\r\n\r\n  /* Disable RXNE interrupt */\r\n  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);\r\n\r\n  SPI_CloseRxTx_ISR(hspi);\r\n}\r\n#endif\r\n\r\n/**\r\n  * @brief  Tx 16-bit handler for Transmit and Receive in Interrupt mode.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Transmit data in 16 Bit mode */\r\n  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r\n  hspi->pTxBuffPtr += sizeof(uint16_t);\r\n  hspi->TxXferCount--;\r\n\r\n  /* Enable CRC Transmission */\r\n  if(hspi->TxXferCount == 0)\r\n  {\r\n#if (USE_SPI_CRC != 0U)\r\n    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n    {\r\n      hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;\r\n    }\r\n#endif\r\n\r\n    /* Disable TXE interrupt */\r\n    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);\r\n\r\n    if(hspi->RxXferCount == 0)\r\n    {\r\n      SPI_CloseRxTx_ISR(hspi);\r\n    }\r\n  }\r\n}\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n/**\r\n  * @brief  Manage the CRC 8-bit receive in Interrupt context.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)\r\n{\r\n  __IO uint8_t tmpreg;\r\n  tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);\r\n\r\n  UNUSED(tmpreg); /* To avoid GCC warning */\r\n\r\n  hspi->CRCSize--;\r\n\r\n  if(hspi->CRCSize == 0)\r\n  {\r\n    SPI_CloseRx_ISR(hspi);\r\n  }\r\n}\r\n#endif\r\n\r\n/**\r\n  * @brief  Manage the receive 8-bit in Interrupt context.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\r\n{\r\n  *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);\r\n  hspi->RxXferCount--;\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Enable CRC Transmission */\r\n  if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\r\n  {\r\n    hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;\r\n  }\r\n#endif\r\n\r\n  if(hspi->RxXferCount == 0)\r\n  {\r\n#if (USE_SPI_CRC != 0U)\r\n    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n    {\r\n      hspi->RxISR =  SPI_RxISR_8BITCRC;\r\n      return;\r\n    }\r\n#endif\r\n    SPI_CloseRx_ISR(hspi);\r\n  }\r\n}\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n/**\r\n  * @brief  Manage the CRC 16-bit receive in Interrupt context.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)\r\n{\r\n  __IO uint16_t tmpreg;\r\n\r\n  tmpreg = hspi->Instance->DR;\r\n  UNUSED(tmpreg); /* To avoid GCC warning */\r\n\r\n  /* Disable RXNE and ERR interrupt */\r\n  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\r\n\r\n  SPI_CloseRx_ISR(hspi);\r\n}\r\n#endif\r\n\r\n/**\r\n  * @brief  Manage the 16-bit receive in Interrupt context.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\r\n{\r\n  *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;\r\n  hspi->pRxBuffPtr += sizeof(uint16_t);\r\n  hspi->RxXferCount--;\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Enable CRC Transmission */\r\n  if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\r\n  {\r\n    hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;\r\n  }\r\n#endif\r\n  if(hspi->RxXferCount == 0)\r\n  {\r\n#if (USE_SPI_CRC != 0U)\r\n    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n    {\r\n      hspi->RxISR = SPI_RxISR_16BITCRC;\r\n      return;\r\n    }\r\n#endif\r\n    SPI_CloseRx_ISR(hspi);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Handle the data 8-bit transmit in Interrupt mode.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\r\n{\r\n  *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);\r\n  hspi->TxXferCount--;\r\n\r\n  if(hspi->TxXferCount == 0)\r\n  {\r\n#if (USE_SPI_CRC != 0U)\r\n    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n    {\r\n      /* Enable CRC Transmission */\r\n      hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;\r\n    }\r\n#endif\r\n    SPI_CloseTx_ISR(hspi);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Handle the data 16-bit transmit in Interrupt mode.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Transmit data in 16 Bit mode */\r\n  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\r\n  hspi->pTxBuffPtr += sizeof(uint16_t);\r\n  hspi->TxXferCount--;\r\n\r\n  if(hspi->TxXferCount == 0)\r\n  {\r\n#if (USE_SPI_CRC != 0U)\r\n    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n    {\r\n      /* Enable CRC Transmission */\r\n      hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;\r\n    }\r\n#endif\r\n    SPI_CloseTx_ISR(hspi);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Handle SPI Communication Timeout.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @param Flag : SPI flag to check\r\n  * @param State : flag state to check\r\n  * @param Timeout : Timeout duration\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = HAL_GetTick();\r\n\r\n  while((hspi->Instance->SR & Flag) != State)\r\n  {\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))\r\n      {\r\n        /* Disable the SPI and reset the CRC: the CRC value should be cleared\r\n        on both master and slave sides in order to resynchronize the master\r\n        and slave for their respective CRC calculation */\r\n\r\n        /* Disable TXE, RXNE and ERR interrupts for the interrupt process */\r\n        __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));\r\n\r\n        if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))\r\n        {\r\n          /* Disable SPI peripheral */\r\n          __HAL_SPI_DISABLE(hspi);\r\n        }\r\n\r\n        /* Reset CRC Calculation */\r\n        if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n        {\r\n          SPI_RESET_CRC(hspi);\r\n        }\r\n\r\n        hspi->State= HAL_SPI_STATE_READY;\r\n\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hspi);\r\n\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Handle SPI FIFO Communication Timeout.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @param Fifo : Fifo to check\r\n  * @param State : Fifo state to check\r\n  * @param Timeout : Timeout duration\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout)\r\n{\r\n  __IO uint8_t tmpreg;\r\n  uint32_t tickstart = HAL_GetTick();\r\n\r\n  while((hspi->Instance->SR & Fifo) != State)\r\n  {\r\n    if((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))\r\n    {\r\n      tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);\r\n      UNUSED(tmpreg); /* To avoid GCC warning */\r\n    }\r\n\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))\r\n      {\r\n        /* Disable the SPI and reset the CRC: the CRC value should be cleared\r\n        on both master and slave sides in order to resynchronize the master\r\n        and slave for their respective CRC calculation */\r\n\r\n        /* Disable TXE, RXNE and ERR interrupts for the interrupt process */\r\n        __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));\r\n\r\n        if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))\r\n        {\r\n          /* Disable SPI peripheral */\r\n          __HAL_SPI_DISABLE(hspi);\r\n        }\r\n\r\n        /* Reset CRC Calculation */\r\n        if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\r\n        {\r\n          SPI_RESET_CRC(hspi);\r\n        }\r\n\r\n        hspi->State = HAL_SPI_STATE_READY;\r\n\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(hspi);\r\n\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Handle the check of the RX transaction complete.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @param Timeout : Timeout duration\r\n  * @retval None\r\n  */\r\nstatic HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi,  uint32_t Timeout)\r\n{\r\n  if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))\r\n  {\r\n    /* Disable SPI peripheral */\r\n    __HAL_SPI_DISABLE(hspi);\r\n  }\r\n\r\n  /* Control the BSY flag */\r\n  if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)\r\n  {\r\n    hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;\r\n    return HAL_TIMEOUT;\r\n  }\r\n\r\n  if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))\r\n  {\r\n    /* Empty the FRLVL fifo */\r\n    if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)\r\n    {\r\n      hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Handle the check of the RXTX or TX transaction complete.\r\n  * @param hspi: SPI handle\r\n  * @param Timeout : Timeout duration\r\n  */\r\nstatic HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)\r\n{\r\n  /* Procedure to check the transaction complete */\r\n  if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout) != HAL_OK)\r\n  {\r\n    hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;\r\n    return HAL_TIMEOUT;\r\n  }\r\n  if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)\r\n  {\r\n    hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;\r\n    return HAL_TIMEOUT;\r\n  }\r\n  /* Control the BSY flag */\r\n  if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)\r\n  {\r\n    hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;\r\n    return HAL_TIMEOUT;\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Handle the end of the RXTX transaction.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Disable ERR interrupt */\r\n  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);\r\n\r\n  /* Check the end of the transaction */\r\n  if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)\r\n  {\r\n    hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;\r\n  }\r\n\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Check if CRC error occurred */\r\n  if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)\r\n  {\r\n    hspi->State = HAL_SPI_STATE_READY;\r\n    hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r\n    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r\n    HAL_SPI_ErrorCallback(hspi);\r\n  }\r\n  else\r\n  {\r\n#endif\r\n    if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)\r\n    {\r\n      if(hspi->State == HAL_SPI_STATE_BUSY_RX)\r\n      {\r\n        hspi->State = HAL_SPI_STATE_READY;\r\n        HAL_SPI_RxCpltCallback(hspi);\r\n      }\r\n      else\r\n      {\r\n        hspi->State = HAL_SPI_STATE_READY;\r\n        HAL_SPI_TxRxCpltCallback(hspi);\r\n      }\r\n    }\r\n    else\r\n    {\r\n      hspi->State = HAL_SPI_STATE_READY;\r\n      HAL_SPI_ErrorCallback(hspi);\r\n    }\r\n#if (USE_SPI_CRC != 0U)\r\n  }\r\n#endif\r\n}\r\n\r\n/**\r\n  * @brief Handle the end of the RX transaction.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Disable RXNE and ERR interrupt */\r\n  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\r\n\r\n  /* Check the end of the transaction */\r\n  if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)\r\n  {\r\n    hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;\r\n  }\r\n  hspi->State = HAL_SPI_STATE_READY;\r\n#if (USE_SPI_CRC != 0U)\r\n  /* Check if CRC error occurred */\r\n  if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)\r\n  {\r\n    hspi->ErrorCode|= HAL_SPI_ERROR_CRC;\r\n    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\r\n    HAL_SPI_ErrorCallback(hspi);\r\n  }\r\n  else\r\n  {\r\n#endif\r\n    if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)\r\n    {\r\n      HAL_SPI_RxCpltCallback(hspi);\r\n    }\r\n    else\r\n    {\r\n      HAL_SPI_ErrorCallback(hspi);\r\n    }\r\n#if (USE_SPI_CRC != 0U)\r\n  }\r\n#endif\r\n}\r\n\r\n/**\r\n  * @brief Handle the end of the TX transaction.\r\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\r\n  *               the configuration information for SPI module.\r\n  * @retval None\r\n  */\r\nstatic void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)\r\n{\r\n  /* Disable TXE and ERR interrupt */\r\n  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));\r\n\r\n  /* Check the end of the transaction */\r\n  if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)\r\n  {\r\n    hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;\r\n  }\r\n\r\n  /* Clear overrun flag in 2 Lines communication mode because received is not read */\r\n  if(hspi->Init.Direction == SPI_DIRECTION_2LINES)\r\n  {\r\n    __HAL_SPI_CLEAR_OVRFLAG(hspi);\r\n  }\r\n\r\n  hspi->State = HAL_SPI_STATE_READY;\r\n  if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)\r\n  {\r\n    HAL_SPI_ErrorCallback(hspi);\r\n  }\r\n  else\r\n  {\r\n    HAL_SPI_TxCpltCallback(hspi);\r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_SPI_MODULE_ENABLED */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sram.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_sram.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   SRAM HAL module driver.\r\n  *          This file provides a generic firmware to drive SRAM memories  \r\n  *          mounted as external device.\r\n  *         \r\n  @verbatim\r\n  ==============================================================================\r\n                          ##### How to use this driver #####\r\n  ==============================================================================  \r\n  [..]\r\n    This driver is a generic layered driver which contains a set of APIs used to \r\n    control SRAM memories. It uses the FMC layer functions to interface \r\n    with SRAM devices.  \r\n    The following sequence should be followed to configure the FMC to interface\r\n    with SRAM/PSRAM memories: \r\n      \r\n   (#) Declare a SRAM_HandleTypeDef handle structure, for example:\r\n          SRAM_HandleTypeDef  hsram; and: \r\n          \r\n       (++) Fill the SRAM_HandleTypeDef handle \"Init\" field with the allowed \r\n            values of the structure member.\r\n            \r\n       (++) Fill the SRAM_HandleTypeDef handle \"Instance\" field with a predefined \r\n            base register instance for NOR or SRAM device \r\n                         \r\n       (++) Fill the SRAM_HandleTypeDef handle \"Extended\" field with a predefined\r\n            base register instance for NOR or SRAM extended mode \r\n             \r\n   (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended \r\n       mode timings; for example:\r\n          FMC_NORSRAM_TimingTypeDef  Timing and FMC_NORSRAM_TimingTypeDef  ExTiming;\r\n      and fill its fields with the allowed values of the structure member.\r\n      \r\n   (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function\r\n       performs the following sequence:\r\n          \r\n       (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()\r\n       (##) Control register configuration using the FMC NORSRAM interface function \r\n            FMC_NORSRAM_Init()\r\n       (##) Timing register configuration using the FMC NORSRAM interface function \r\n            FMC_NORSRAM_Timing_Init()\r\n       (##) Extended mode Timing register configuration using the FMC NORSRAM interface function \r\n            FMC_NORSRAM_Extended_Timing_Init()\r\n       (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()    \r\n\r\n   (#) At this stage you can perform read/write accesses from/to the memory connected \r\n       to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the\r\n       following APIs:\r\n       (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access\r\n       (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer\r\n       \r\n   (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/\r\n       HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation  \r\n       \r\n   (#) You can continuously monitor the SRAM device HAL state by calling the function\r\n       HAL_SRAM_GetState()              \r\n                             \r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup SRAM SRAM \r\n  * @brief SRAM driver modules\r\n  * @{\r\n  */\r\n#ifdef HAL_SRAM_MODULE_ENABLED\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/    \r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @defgroup SRAM_Exported_Functions SRAM Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions\r\n  * @brief    Initialization and Configuration functions.\r\n  *\r\n  @verbatim    \r\n  ==============================================================================\r\n           ##### SRAM Initialization and de_initialization functions #####\r\n  ==============================================================================\r\n    [..]  This section provides functions allowing to initialize/de-initialize\r\n          the SRAM memory\r\n  \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Performs the SRAM device initialization sequence\r\n  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SRAM module.\r\n  * @param  Timing: Pointer to SRAM control timing structure \r\n  * @param  ExtTiming: Pointer to SRAM extended mode timing structure  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)\r\n{ \r\n  /* Check the SRAM handle parameter */\r\n  if(hsram == NULL)\r\n  {\r\n     return HAL_ERROR;\r\n  }\r\n  \r\n  if(hsram->State == HAL_SRAM_STATE_RESET)\r\n  {  \r\n    /* Allocate lock resource and initialize it */\r\n    hsram->Lock = HAL_UNLOCKED;\r\n    /* Initialize the low level hardware (MSP) */\r\n    HAL_SRAM_MspInit(hsram);\r\n  }\r\n  \r\n  /* Initialize SRAM control Interface */\r\n  FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));\r\n\r\n  /* Initialize SRAM timing Interface */\r\n  FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); \r\n\r\n  /* Initialize SRAM extended mode timing Interface */\r\n  FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,  hsram->Init.ExtendedMode);  \r\n  \r\n  /* Enable the NORSRAM device */\r\n  __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); \r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Performs the SRAM device De-initialization sequence.\r\n  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SRAM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef  HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)\r\n{ \r\n  /* De-Initialize the low level hardware (MSP) */\r\n  HAL_SRAM_MspDeInit(hsram);\r\n   \r\n  /* Configure the SRAM registers with their reset values */\r\n  FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);\r\n\r\n  hsram->State = HAL_SRAM_STATE_RESET;\r\n  \r\n  /* Release Lock */\r\n  __HAL_UNLOCK(hsram);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  SRAM MSP Init.\r\n  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SRAM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hsram);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_SRAM_MspInit could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  SRAM MSP DeInit.\r\n  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SRAM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hsram);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_SRAM_MspDeInit could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  DMA transfer complete callback.\r\n  * @param  hdma: pointer to a SRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SRAM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdma);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  DMA transfer complete error callback.\r\n  * @param  hdma: pointer to a SRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SRAM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hdma);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions \r\n  * @brief    Input Output and memory control functions \r\n  *\r\n  @verbatim    \r\n  ==============================================================================\r\n                  ##### SRAM Input and Output functions #####\r\n  ==============================================================================\r\n  [..]  \r\n    This section provides functions allowing to use and control the SRAM memory\r\n  \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Reads 8-bit buffer from SRAM memory. \r\n  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SRAM module.\r\n  * @param  pAddress: Pointer to read start address\r\n  * @param  pDstBuffer: Pointer to destination buffer  \r\n  * @param  BufferSize: Size of the buffer to read from memory\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)\r\n{\r\n  __IO uint8_t * psramaddress = (uint8_t *)pAddress;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hsram);\r\n  \r\n  /* Update the SRAM controller state */\r\n  hsram->State = HAL_SRAM_STATE_BUSY;  \r\n  \r\n  /* Read data from memory */\r\n  for(; BufferSize != 0; BufferSize--)\r\n  {\r\n    *pDstBuffer = *(__IO uint8_t *)psramaddress;\r\n    pDstBuffer++;\r\n    psramaddress++;\r\n  }\r\n  \r\n  /* Update the SRAM controller state */\r\n  hsram->State = HAL_SRAM_STATE_READY;    \r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hsram); \r\n    \r\n  return HAL_OK;   \r\n}\r\n\r\n/**\r\n  * @brief  Writes 8-bit buffer to SRAM memory. \r\n  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SRAM module.\r\n  * @param  pAddress: Pointer to write start address\r\n  * @param  pSrcBuffer: Pointer to source buffer to write  \r\n  * @param  BufferSize: Size of the buffer to write to memory\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)\r\n{\r\n  __IO uint8_t * psramaddress = (uint8_t *)pAddress;\r\n  \r\n  /* Check the SRAM controller state */\r\n  if(hsram->State == HAL_SRAM_STATE_PROTECTED)\r\n  {\r\n    return  HAL_ERROR; \r\n  }\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hsram);\r\n  \r\n  /* Update the SRAM controller state */\r\n  hsram->State = HAL_SRAM_STATE_BUSY; \r\n\r\n  /* Write data to memory */\r\n  for(; BufferSize != 0; BufferSize--)\r\n  {\r\n    *(__IO uint8_t *)psramaddress = *pSrcBuffer; \r\n    pSrcBuffer++;\r\n    psramaddress++;    \r\n  }    \r\n\r\n  /* Update the SRAM controller state */\r\n  hsram->State = HAL_SRAM_STATE_READY; \r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hsram);\r\n    \r\n  return HAL_OK;   \r\n}\r\n\r\n/**\r\n  * @brief  Reads 16-bit buffer from SRAM memory. \r\n  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SRAM module.\r\n  * @param  pAddress: Pointer to read start address\r\n  * @param  pDstBuffer: Pointer to destination buffer  \r\n  * @param  BufferSize: Size of the buffer to read from memory\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)\r\n{\r\n  __IO uint16_t * psramaddress = (uint16_t *)pAddress;\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hsram);\r\n  \r\n  /* Update the SRAM controller state */\r\n  hsram->State = HAL_SRAM_STATE_BUSY;  \r\n  \r\n  /* Read data from memory */\r\n  for(; BufferSize != 0; BufferSize--)\r\n  {\r\n    *pDstBuffer = *(__IO uint16_t *)psramaddress;\r\n    pDstBuffer++;\r\n    psramaddress++;\r\n  }\r\n  \r\n  /* Update the SRAM controller state */\r\n  hsram->State = HAL_SRAM_STATE_READY;    \r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hsram); \r\n    \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Writes 16-bit buffer to SRAM memory. \r\n  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SRAM module.\r\n  * @param  pAddress: Pointer to write start address\r\n  * @param  pSrcBuffer: Pointer to source buffer to write  \r\n  * @param  BufferSize: Size of the buffer to write to memory\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)\r\n{\r\n  __IO uint16_t * psramaddress = (uint16_t *)pAddress; \r\n  \r\n  /* Check the SRAM controller state */\r\n  if(hsram->State == HAL_SRAM_STATE_PROTECTED)\r\n  {\r\n    return  HAL_ERROR; \r\n  }\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hsram);\r\n  \r\n  /* Update the SRAM controller state */\r\n  hsram->State = HAL_SRAM_STATE_BUSY; \r\n\r\n  /* Write data to memory */\r\n  for(; BufferSize != 0; BufferSize--)\r\n  {\r\n    *(__IO uint16_t *)psramaddress = *pSrcBuffer; \r\n    pSrcBuffer++;\r\n    psramaddress++;    \r\n  }    \r\n\r\n  /* Update the SRAM controller state */\r\n  hsram->State = HAL_SRAM_STATE_READY; \r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hsram);\r\n    \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Reads 32-bit buffer from SRAM memory. \r\n  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SRAM module.\r\n  * @param  pAddress: Pointer to read start address\r\n  * @param  pDstBuffer: Pointer to destination buffer  \r\n  * @param  BufferSize: Size of the buffer to read from memory\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hsram);\r\n  \r\n  /* Update the SRAM controller state */\r\n  hsram->State = HAL_SRAM_STATE_BUSY;  \r\n  \r\n  /* Read data from memory */\r\n  for(; BufferSize != 0; BufferSize--)\r\n  {\r\n    *pDstBuffer = *(__IO uint32_t *)pAddress;\r\n    pDstBuffer++;\r\n    pAddress++;\r\n  }\r\n  \r\n  /* Update the SRAM controller state */\r\n  hsram->State = HAL_SRAM_STATE_READY;    \r\n\r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hsram); \r\n    \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Writes 32-bit buffer to SRAM memory. \r\n  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SRAM module.\r\n  * @param  pAddress: Pointer to write start address\r\n  * @param  pSrcBuffer: Pointer to source buffer to write  \r\n  * @param  BufferSize: Size of the buffer to write to memory\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)\r\n{\r\n  /* Check the SRAM controller state */\r\n  if(hsram->State == HAL_SRAM_STATE_PROTECTED)\r\n  {\r\n    return  HAL_ERROR; \r\n  }\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hsram);\r\n  \r\n  /* Update the SRAM controller state */\r\n  hsram->State = HAL_SRAM_STATE_BUSY; \r\n\r\n  /* Write data to memory */\r\n  for(; BufferSize != 0; BufferSize--)\r\n  {\r\n    *(__IO uint32_t *)pAddress = *pSrcBuffer; \r\n    pSrcBuffer++;\r\n    pAddress++;    \r\n  }    \r\n\r\n  /* Update the SRAM controller state */\r\n  hsram->State = HAL_SRAM_STATE_READY; \r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hsram);\r\n    \r\n  return HAL_OK;   \r\n}\r\n\r\n/**\r\n  * @brief  Reads a Words data from the SRAM memory using DMA transfer.\r\n  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SRAM module.\r\n  * @param  pAddress: Pointer to read start address\r\n  * @param  pDstBuffer: Pointer to destination buffer  \r\n  * @param  BufferSize: Size of the buffer to read from memory\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hsram);  \r\n  \r\n  /* Update the SRAM controller state */\r\n  hsram->State = HAL_SRAM_STATE_BUSY;   \r\n  \r\n  /* Configure DMA user callbacks */\r\n  hsram->hdma->XferCpltCallback  = HAL_SRAM_DMA_XferCpltCallback;\r\n  hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;\r\n\r\n  /* Enable the DMA Stream */\r\n  HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);\r\n  \r\n  /* Update the SRAM controller state */\r\n  hsram->State = HAL_SRAM_STATE_READY; \r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hsram);  \r\n  \r\n  return HAL_OK; \r\n}\r\n\r\n/**\r\n  * @brief  Writes a Words data buffer to SRAM memory using DMA transfer.\r\n  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SRAM module.\r\n  * @param  pAddress: Pointer to write start address\r\n  * @param  pSrcBuffer: Pointer to source buffer to write  \r\n  * @param  BufferSize: Size of the buffer to write to memory\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)\r\n{\r\n  /* Check the SRAM controller state */\r\n  if(hsram->State == HAL_SRAM_STATE_PROTECTED)\r\n  {\r\n    return  HAL_ERROR; \r\n  }\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(hsram);\r\n  \r\n  /* Update the SRAM controller state */\r\n  hsram->State = HAL_SRAM_STATE_BUSY; \r\n  \r\n  /* Configure DMA user callbacks */\r\n  hsram->hdma->XferCpltCallback  = HAL_SRAM_DMA_XferCpltCallback;\r\n  hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;\r\n\r\n  /* Enable the DMA Stream */\r\n  HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);\r\n  \r\n  /* Update the SRAM controller state */\r\n  hsram->State = HAL_SRAM_STATE_READY;  \r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hsram);  \r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup SRAM_Exported_Functions_Group3 Control functions \r\n *  @brief   Control functions \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                        ##### SRAM Control functions #####\r\n  ==============================================================================  \r\n  [..]\r\n    This subsection provides a set of functions allowing to control dynamically\r\n    the SRAM interface.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n    \r\n/**\r\n  * @brief  Enables dynamically SRAM write operation.\r\n  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SRAM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hsram);\r\n\r\n  /* Enable write operation */\r\n  FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank); \r\n  \r\n  /* Update the SRAM controller state */\r\n  hsram->State = HAL_SRAM_STATE_READY;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hsram); \r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Disables dynamically SRAM write operation.\r\n  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SRAM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(hsram);\r\n\r\n  /* Update the SRAM controller state */\r\n  hsram->State = HAL_SRAM_STATE_BUSY;\r\n    \r\n  /* Disable write operation */\r\n  FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank); \r\n  \r\n  /* Update the SRAM controller state */\r\n  hsram->State = HAL_SRAM_STATE_PROTECTED;\r\n  \r\n  /* Process unlocked */\r\n  __HAL_UNLOCK(hsram); \r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions \r\n *  @brief   Peripheral State functions \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                      ##### SRAM State functions #####\r\n  ==============================================================================  \r\n  [..]\r\n    This subsection permits to get in run-time the status of the SRAM controller \r\n    and the data flow.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @brief  Returns the SRAM controller state\r\n  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains\r\n  *                the configuration information for SRAM module.\r\n  * @retval HAL state\r\n  */\r\nHAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)\r\n{\r\n  return hsram->State;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n#endif /* HAL_SRAM_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_tim.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   TIM HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the Timer (TIM) peripheral:\r\n  *           + Time Base Initialization\r\n  *           + Time Base Start\r\n  *           + Time Base Start Interruption\r\n  *           + Time Base Start DMA\r\n  *           + Time Output Compare/PWM Initialization\r\n  *           + Time Output Compare/PWM Channel Configuration\r\n  *           + Time Output Compare/PWM  Start\r\n  *           + Time Output Compare/PWM  Start Interruption\r\n  *           + Time Output Compare/PWM Start DMA\r\n  *           + Time Input Capture Initialization\r\n  *           + Time Input Capture Channel Configuration\r\n  *           + Time Input Capture Start\r\n  *           + Time Input Capture Start Interruption \r\n  *           + Time Input Capture Start DMA\r\n  *           + Time One Pulse Initialization\r\n  *           + Time One Pulse Channel Configuration\r\n  *           + Time One Pulse Start \r\n  *           + Time Encoder Interface Initialization\r\n  *           + Time Encoder Interface Start\r\n  *           + Time Encoder Interface Start Interruption\r\n  *           + Time Encoder Interface Start DMA\r\n  *           + Commutation Event configuration with Interruption and DMA\r\n  *           + Time OCRef clear configuration\r\n  *           + Time External Clock configuration\r\n  @verbatim \r\n  ==============================================================================\r\n                      ##### TIMER Generic features #####\r\n  ==============================================================================\r\n  [..] The Timer features include: \r\n       (#) 16-bit up, down, up/down auto-reload counter.\r\n       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the \r\n           counter clock frequency either by any factor between 1 and 65536.\r\n       (#) Up to 4 independent channels for:\r\n           (++) Input Capture\r\n           (++) Output Compare\r\n           (++) PWM generation (Edge and Center-aligned Mode)\r\n           (++) One-pulse mode output               \r\n   \r\n                        ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]\r\n     (#) Initialize the TIM low level resources by implementing the following functions \r\n         depending from feature used :\r\n           (++) Time Base : HAL_TIM_Base_MspInit() \r\n           (++) Input Capture : HAL_TIM_IC_MspInit()\r\n           (++) Output Compare : HAL_TIM_OC_MspInit()\r\n           (++) PWM generation : HAL_TIM_PWM_MspInit()\r\n           (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()\r\n           (++) Encoder mode output : HAL_TIM_Encoder_MspInit()\r\n           \r\n     (#) Initialize the TIM low level resources :\r\n        (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE(); \r\n        (##) TIM pins configuration\r\n            (+++) Enable the clock for the TIM GPIOs using the following function:\r\n                 __GPIOx_CLK_ENABLE();   \r\n            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();  \r\n\r\n     (#) The external Clock can be configured, if needed (the default clock is the \r\n         internal clock from the APBx), using the following function:\r\n         HAL_TIM_ConfigClockSource, the clock configuration should be done before \r\n         any start function.\r\n  \r\n     (#) Configure the TIM in the desired functioning mode using one of the \r\n         initialization function of this driver:\r\n         (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base\r\n         (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an \r\n              Output Compare signal.\r\n         (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a \r\n              PWM signal.\r\n         (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an \r\n              external signal.\r\n         (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer \r\n              in One Pulse Mode.\r\n         (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.\r\n         \r\n     (#) Activate the TIM peripheral using one of the start functions depending from the feature used: \r\n           (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()\r\n           (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()\r\n           (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()\r\n           (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()\r\n           (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()\r\n           (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().\r\n\r\n     (#) The DMA Burst is managed with the two following functions:\r\n         HAL_TIM_DMABurst_WriteStart()\r\n         HAL_TIM_DMABurst_ReadStart()\r\n  \r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup TIM TIM\r\n  * @brief TIM HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_TIM_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/** @addtogroup TIM_Private_Functions\r\n  * @{\r\n  */\r\n/* Private function prototypes -----------------------------------------------*/\r\nstatic void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);\r\nstatic void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r\n                       uint32_t TIM_ICFilter);\r\nstatic void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);\r\nstatic void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r\n                       uint32_t TIM_ICFilter);\r\nstatic void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r\n                       uint32_t TIM_ICFilter);\r\n\r\nstatic void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx);\r\nstatic void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);\r\nstatic void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);\r\nstatic void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,\r\n                                     TIM_SlaveConfigTypeDef * sSlaveConfig);\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup TIM_Exported_Functions TIM Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup TIM_Exported_Functions_Group1 Time Base functions \r\n *  @brief    Time Base functions \r\n *\r\n@verbatim    \r\n  ==============================================================================\r\n              ##### Time Base functions #####\r\n  ==============================================================================\r\n  [..]  \r\n    This section provides functions allowing to:\r\n    (+) Initialize and configure the TIM base. \r\n    (+) De-initialize the TIM base.\r\n    (+) Start the Time Base.\r\n    (+) Stop the Time Base.\r\n    (+) Start the Time Base and enable interrupt.\r\n    (+) Stop the Time Base and disable interrupt.\r\n    (+) Start the Time Base and enable DMA transfer.\r\n    (+) Stop the Time Base and disable DMA transfer.\r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n/**\r\n  * @brief  Initializes the TIM Time base Unit according to the specified\r\n  *         parameters in the TIM_HandleTypeDef and create the associated handle.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)\r\n{ \r\n  /* Check the TIM handle allocation */\r\n  if(htim == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_INSTANCE(htim->Instance)); \r\n  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r\n  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r\n  \r\n  if(htim->State == HAL_TIM_STATE_RESET)\r\n  {  \r\n    /* Init the low level hardware : GPIO, CLOCK, NVIC */\r\n    HAL_TIM_Base_MspInit(htim);\r\n  }\r\n  \r\n  /* Set the TIM state */\r\n  htim->State= HAL_TIM_STATE_BUSY;\r\n  \r\n  /* Set the Time Base configuration */\r\n  TIM_Base_SetConfig(htim->Instance, &htim->Init); \r\n  \r\n  /* Initialize the TIM state*/\r\n  htim->State= HAL_TIM_STATE_READY;\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the TIM Base peripheral \r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)\r\n{  \r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\r\n\r\n  htim->State = HAL_TIM_STATE_BUSY;\r\n   \r\n  /* Disable the TIM Peripheral Clock */\r\n  __HAL_TIM_DISABLE(htim);\r\n    \r\n  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r\n  HAL_TIM_Base_MspDeInit(htim);\r\n  \r\n  /* Change TIM state */  \r\n  htim->State = HAL_TIM_STATE_RESET; \r\n  \r\n  /* Release Lock */\r\n  __HAL_UNLOCK(htim);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the TIM Base MSP.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_TIM_Base_MspInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes TIM Base MSP.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_TIM_Base_MspDeInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Starts the TIM Base generation.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\r\n  \r\n  /* Set the TIM state */\r\n  htim->State= HAL_TIM_STATE_BUSY;\r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim);\r\n  \r\n  /* Change the TIM state*/\r\n  htim->State= HAL_TIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the TIM Base generation.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\r\n  \r\n  /* Set the TIM state */\r\n  htim->State= HAL_TIM_STATE_BUSY;\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim);\r\n  \r\n  /* Change the TIM state*/\r\n  htim->State= HAL_TIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the TIM Base generation in interrupt mode.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\r\n  \r\n  /* Enable the TIM Update interrupt */\r\n  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);\r\n      \r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim);\r\n      \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the TIM Base generation in interrupt mode.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\r\n  /* Disable the TIM Update interrupt */\r\n  __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);\r\n      \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim);\r\n    \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the TIM Base generation in DMA mode.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  pData: The source Buffer address.\r\n  * @param  Length: The length of data to be transferred from memory to peripheral.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); \r\n  \r\n  if((htim->State == HAL_TIM_STATE_BUSY))\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  else if((htim->State == HAL_TIM_STATE_READY))\r\n  {\r\n    if((pData == 0 ) && (Length > 0)) \r\n    {\r\n      return HAL_ERROR;                                    \r\n    }\r\n    else\r\n    {\r\n      htim->State = HAL_TIM_STATE_BUSY;\r\n    }\r\n  }  \r\n  /* Set the DMA Period elapsed callback */\r\n  htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;\r\n     \r\n  /* Set the DMA error callback */\r\n  htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;\r\n  \r\n  /* Enable the DMA Stream */\r\n  HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);\r\n  \r\n  /* Enable the TIM Update DMA request */\r\n  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);\r\n\r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim);  \r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the TIM Base generation in DMA mode.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));\r\n  \r\n  /* Disable the TIM Update DMA request */\r\n  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);\r\n      \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim);\r\n    \r\n  /* Change the htim state */\r\n  htim->State = HAL_TIM_STATE_READY;\r\n      \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions \r\n *  @brief    Time Output Compare functions \r\n *\r\n@verbatim    \r\n  ==============================================================================\r\n                  ##### Time Output Compare functions #####\r\n  ==============================================================================\r\n  [..]\r\n    This section provides functions allowing to:\r\n    (+) Initialize and configure the TIM Output Compare. \r\n    (+) De-initialize the TIM Output Compare.\r\n    (+) Start the Time Output Compare.\r\n    (+) Stop the Time Output Compare.\r\n    (+) Start the Time Output Compare and enable interrupt.\r\n    (+) Stop the Time Output Compare and disable interrupt.\r\n    (+) Start the Time Output Compare and enable DMA transfer.\r\n    (+) Stop the Time Output Compare and disable DMA transfer.\r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n/**\r\n  * @brief  Initializes the TIM Output Compare according to the specified\r\n  *         parameters in the TIM_HandleTypeDef and create the associated handle.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)\r\n{\r\n  /* Check the TIM handle allocation */\r\n  if(htim == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\r\n  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r\n  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r\n \r\n  if(htim->State == HAL_TIM_STATE_RESET)\r\n  { \r\n    /* Allocate lock resource and initialize it */\r\n    htim->Lock = HAL_UNLOCKED;  \r\n    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r\n    HAL_TIM_OC_MspInit(htim);\r\n  }\r\n  \r\n  /* Set the TIM state */\r\n  htim->State= HAL_TIM_STATE_BUSY;\r\n  \r\n  /* Init the base time for the Output Compare */  \r\n  TIM_Base_SetConfig(htim->Instance,  &htim->Init); \r\n  \r\n  /* Initialize the TIM state*/\r\n  htim->State= HAL_TIM_STATE_READY;\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the TIM peripheral \r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\r\n  \r\n   htim->State = HAL_TIM_STATE_BUSY;\r\n   \r\n  /* Disable the TIM Peripheral Clock */\r\n  __HAL_TIM_DISABLE(htim);\r\n  \r\n  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\r\n  HAL_TIM_OC_MspDeInit(htim);\r\n    \r\n  /* Change TIM state */  \r\n  htim->State = HAL_TIM_STATE_RESET; \r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(htim);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the TIM Output Compare MSP.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_TIM_OC_MspInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes TIM Output Compare MSP.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_TIM_OC_MspDeInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Starts the TIM Output Compare signal generation.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.  \r\n  * @param  Channel: TIM Channel to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n  \r\n  /* Enable the Output compare channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r\n  \r\n  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  \r\n  {\r\n    /* Enable the main output */\r\n    __HAL_TIM_MOE_ENABLE(htim);\r\n  }\r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim); \r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the TIM Output Compare signal generation.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel: TIM Channel to be disabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n  \r\n  /* Disable the Output compare channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r\n  \r\n  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  \r\n  {\r\n    /* Disable the Main Output */\r\n    __HAL_TIM_MOE_DISABLE(htim);\r\n  }  \r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim);  \r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}  \r\n\r\n/**\r\n  * @brief  Starts the TIM Output Compare signal generation in interrupt mode.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel: TIM Channel to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n  \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {       \r\n      /* Enable the TIM Capture/Compare 1 interrupt */\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Enable the TIM Capture/Compare 2 interrupt */\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      /* Enable the TIM Capture/Compare 3 interrupt */\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n      /* Enable the TIM Capture/Compare 4 interrupt */\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break;\r\n  } \r\n\r\n  /* Enable the Output compare channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r\n  \r\n  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  \r\n  {\r\n    /* Enable the main output */\r\n    __HAL_TIM_MOE_ENABLE(htim);\r\n  }\r\n\r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the TIM Output Compare signal generation in interrupt mode.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel: TIM Channel to be disabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n  \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {       \r\n      /* Disable the TIM Capture/Compare 1 interrupt */\r\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Disable the TIM Capture/Compare 2 interrupt */\r\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      /* Disable the TIM Capture/Compare 3 interrupt */\r\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n      /* Disable the TIM Capture/Compare 4 interrupt */\r\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break; \r\n  } \r\n  \r\n  /* Disable the Output compare channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); \r\n  \r\n  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  \r\n  {\r\n    /* Disable the Main Output */\r\n    __HAL_TIM_MOE_DISABLE(htim);\r\n  }\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim);  \r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the TIM Output Compare signal generation in DMA mode.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel: TIM Channel to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @param  pData: The source Buffer address.\r\n  * @param  Length: The length of data to be transferred from memory to TIM peripheral\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n  \r\n  if((htim->State == HAL_TIM_STATE_BUSY))\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  else if((htim->State == HAL_TIM_STATE_READY))\r\n  {\r\n    if(((uint32_t)pData == 0 ) && (Length > 0)) \r\n    {\r\n      return HAL_ERROR;                                    \r\n    }\r\n    else\r\n    {\r\n      htim->State = HAL_TIM_STATE_BUSY;\r\n    }\r\n  }    \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {      \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);\r\n      \r\n      /* Enable the TIM Capture/Compare 1 DMA request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);\r\n      \r\n      /* Enable the TIM Capture/Compare 2 DMA request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);\r\n      \r\n      /* Enable the TIM Capture/Compare 3 DMA request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n     /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);\r\n      \r\n      /* Enable the TIM Capture/Compare 4 DMA request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break;\r\n  }\r\n\r\n  /* Enable the Output compare channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r\n  \r\n  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  \r\n  {\r\n    /* Enable the main output */\r\n    __HAL_TIM_MOE_ENABLE(htim);\r\n  }  \r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim); \r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the TIM Output Compare signal generation in DMA mode.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel: TIM Channel to be disabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n  \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {       \r\n      /* Disable the TIM Capture/Compare 1 DMA request */\r\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Disable the TIM Capture/Compare 2 DMA request */\r\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      /* Disable the TIM Capture/Compare 3 DMA request */\r\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n      /* Disable the TIM Capture/Compare 4 interrupt */\r\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break;\r\n  } \r\n  \r\n  /* Disable the Output compare channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r\n  \r\n  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  \r\n  {\r\n    /* Disable the Main Output */\r\n    __HAL_TIM_MOE_DISABLE(htim);\r\n  }\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim);\r\n  \r\n  /* Change the htim state */\r\n  htim->State = HAL_TIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions \r\n *  @brief    Time PWM functions \r\n *\r\n@verbatim    \r\n  ==============================================================================\r\n                          ##### Time PWM functions #####\r\n  ==============================================================================\r\n  [..]  \r\n    This section provides functions allowing to:\r\n    (+) Initialize and configure the TIM OPWM. \r\n    (+) De-initialize the TIM PWM.\r\n    (+) Start the Time PWM.\r\n    (+) Stop the Time PWM.\r\n    (+) Start the Time PWM and enable interrupt.\r\n    (+) Stop the Time PWM and disable interrupt.\r\n    (+) Start the Time PWM and enable DMA transfer.\r\n    (+) Stop the Time PWM and disable DMA transfer.\r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n/**\r\n  * @brief  Initializes the TIM PWM Time Base according to the specified\r\n  *         parameters in the TIM_HandleTypeDef and create the associated handle.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Check the TIM handle allocation */\r\n  if(htim == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\r\n  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r\n  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r\n\r\n  if(htim->State == HAL_TIM_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    htim->Lock = HAL_UNLOCKED;  \r\n    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r\n    HAL_TIM_PWM_MspInit(htim);\r\n  }\r\n\r\n  /* Set the TIM state */\r\n  htim->State= HAL_TIM_STATE_BUSY;  \r\n  \r\n  /* Init the base time for the PWM */  \r\n  TIM_Base_SetConfig(htim->Instance, &htim->Init); \r\n   \r\n  /* Initialize the TIM state*/\r\n  htim->State= HAL_TIM_STATE_READY;\r\n  \r\n  return HAL_OK;\r\n}  \r\n\r\n/**\r\n  * @brief  DeInitializes the TIM peripheral \r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\r\n  \r\n  htim->State = HAL_TIM_STATE_BUSY;\r\n  \r\n  /* Disable the TIM Peripheral Clock */\r\n  __HAL_TIM_DISABLE(htim);\r\n    \r\n  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\r\n  HAL_TIM_PWM_MspDeInit(htim);\r\n    \r\n  /* Change TIM state */  \r\n  htim->State = HAL_TIM_STATE_RESET; \r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(htim);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the TIM PWM MSP.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_TIM_PWM_MspInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes TIM PWM MSP.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_TIM_PWM_MspDeInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Starts the PWM signal generation.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel: TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n\r\n  /* Enable the Capture compare channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r\n  \r\n  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  \r\n  {\r\n    /* Enable the main output */\r\n    __HAL_TIM_MOE_ENABLE(htim);\r\n  }\r\n    \r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n} \r\n\r\n/**\r\n  * @brief  Stops the PWM signal generation.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel: TIM Channels to be disabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{ \r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n    \r\n  /* Disable the Capture compare channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r\n  \r\n  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  \r\n  {\r\n    /* Disable the Main Output */\r\n    __HAL_TIM_MOE_DISABLE(htim);\r\n  }\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim);\r\n  \r\n  /* Change the htim state */\r\n  htim->State = HAL_TIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n} \r\n\r\n/**\r\n  * @brief  Starts the PWM signal generation in interrupt mode.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel: TIM Channel to be disabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n  \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {       \r\n      /* Enable the TIM Capture/Compare 1 interrupt */\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Enable the TIM Capture/Compare 2 interrupt */\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      /* Enable the TIM Capture/Compare 3 interrupt */\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n      /* Enable the TIM Capture/Compare 4 interrupt */\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break;\r\n  } \r\n  \r\n  /* Enable the Capture compare channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r\n  \r\n  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  \r\n  {\r\n    /* Enable the main output */\r\n    __HAL_TIM_MOE_ENABLE(htim);\r\n  }\r\n\r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n} \r\n\r\n/**\r\n  * @brief  Stops the PWM signal generation in interrupt mode.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel: TIM Channels to be disabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n  \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {       \r\n      /* Disable the TIM Capture/Compare 1 interrupt */\r\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Disable the TIM Capture/Compare 2 interrupt */\r\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      /* Disable the TIM Capture/Compare 3 interrupt */\r\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n      /* Disable the TIM Capture/Compare 4 interrupt */\r\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break; \r\n  }\r\n  \r\n  /* Disable the Capture compare channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r\n  \r\n  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  \r\n  {\r\n    /* Disable the Main Output */\r\n    __HAL_TIM_MOE_DISABLE(htim);\r\n  }\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n} \r\n\r\n/**\r\n  * @brief  Starts the TIM PWM signal generation in DMA mode.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel: TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @param  pData: The source Buffer address.\r\n  * @param  Length: The length of data to be transferred from memory to TIM peripheral\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n  \r\n  if((htim->State == HAL_TIM_STATE_BUSY))\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  else if((htim->State == HAL_TIM_STATE_READY))\r\n  {\r\n    if(((uint32_t)pData == 0 ) && (Length > 0)) \r\n    {\r\n      return HAL_ERROR;                                    \r\n    }\r\n    else\r\n    {\r\n      htim->State = HAL_TIM_STATE_BUSY;\r\n    }\r\n  }    \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {      \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);\r\n      \r\n      /* Enable the TIM Capture/Compare 1 DMA request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);\r\n      \r\n      /* Enable the TIM Capture/Compare 2 DMA request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);\r\n      \r\n      /* Enable the TIM Output Capture/Compare 3 request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n     /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);\r\n      \r\n      /* Enable the TIM Capture/Compare 4 DMA request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break;\r\n  }\r\n\r\n  /* Enable the Capture compare channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r\n    \r\n  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  \r\n  {\r\n    /* Enable the main output */\r\n    __HAL_TIM_MOE_ENABLE(htim);\r\n  }\r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim); \r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the TIM PWM signal generation in DMA mode.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel: TIM Channels to be disabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n  \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {       \r\n      /* Disable the TIM Capture/Compare 1 DMA request */\r\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Disable the TIM Capture/Compare 2 DMA request */\r\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      /* Disable the TIM Capture/Compare 3 DMA request */\r\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n      /* Disable the TIM Capture/Compare 4 interrupt */\r\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break;\r\n  } \r\n  \r\n  /* Disable the Capture compare channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r\n  \r\n  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  \r\n  {\r\n    /* Disable the Main Output */\r\n    __HAL_TIM_MOE_DISABLE(htim);\r\n  }\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim);\r\n  \r\n  /* Change the htim state */\r\n  htim->State = HAL_TIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions \r\n *  @brief    Time Input Capture functions \r\n *\r\n@verbatim    \r\n  ==============================================================================\r\n              ##### Time Input Capture functions #####\r\n  ==============================================================================\r\n [..]  \r\n   This section provides functions allowing to:\r\n   (+) Initialize and configure the TIM Input Capture. \r\n   (+) De-initialize the TIM Input Capture.\r\n   (+) Start the Time Input Capture.\r\n   (+) Stop the Time Input Capture.\r\n   (+) Start the Time Input Capture and enable interrupt.\r\n   (+) Stop the Time Input Capture and disable interrupt.\r\n   (+) Start the Time Input Capture and enable DMA transfer.\r\n   (+) Stop the Time Input Capture and disable DMA transfer.\r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n/**\r\n  * @brief  Initializes the TIM Input Capture Time base according to the specified\r\n  *         parameters in the TIM_HandleTypeDef and create the associated handle.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Check the TIM handle allocation */\r\n  if(htim == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\r\n  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r\n  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); \r\n\r\n  if(htim->State == HAL_TIM_STATE_RESET)\r\n  { \r\n    /* Allocate lock resource and initialize it */\r\n    htim->Lock = HAL_UNLOCKED;   \r\n    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r\n    HAL_TIM_IC_MspInit(htim);\r\n  }\r\n  \r\n  /* Set the TIM state */\r\n  htim->State= HAL_TIM_STATE_BUSY;   \r\n  \r\n  /* Init the base time for the input capture */  \r\n  TIM_Base_SetConfig(htim->Instance, &htim->Init); \r\n   \r\n  /* Initialize the TIM state*/\r\n  htim->State= HAL_TIM_STATE_READY;\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the TIM peripheral \r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\r\n\r\n  htim->State = HAL_TIM_STATE_BUSY;\r\n  \r\n  /* Disable the TIM Peripheral Clock */\r\n  __HAL_TIM_DISABLE(htim);\r\n    \r\n  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\r\n  HAL_TIM_IC_MspDeInit(htim);\r\n    \r\n  /* Change TIM state */  \r\n  htim->State = HAL_TIM_STATE_RESET;\r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(htim);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the TIM INput Capture MSP.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_TIM_IC_MspInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes TIM Input Capture MSP.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n   \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_TIM_IC_MspDeInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Starts the TIM Input Capture measurement.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel: TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n  \r\n  /* Enable the Input Capture channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r\n    \r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim);  \r\n\r\n  /* Return function status */\r\n  return HAL_OK;  \r\n} \r\n\r\n/**\r\n  * @brief  Stops the TIM Input Capture measurement.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel: TIM Channels to be disabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{ \r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n  \r\n  /* Disable the Input Capture channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim); \r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the TIM Input Capture measurement in interrupt mode.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel: TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n  \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {       \r\n      /* Enable the TIM Capture/Compare 1 interrupt */\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Enable the TIM Capture/Compare 2 interrupt */\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      /* Enable the TIM Capture/Compare 3 interrupt */\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n      /* Enable the TIM Capture/Compare 4 interrupt */\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break;\r\n  }  \r\n  /* Enable the Input Capture channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r\n    \r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim);  \r\n\r\n  /* Return function status */\r\n  return HAL_OK;  \r\n} \r\n\r\n/**\r\n  * @brief  Stops the TIM Input Capture measurement in interrupt mode.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel: TIM Channels to be disabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n  \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {       \r\n      /* Disable the TIM Capture/Compare 1 interrupt */\r\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Disable the TIM Capture/Compare 2 interrupt */\r\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      /* Disable the TIM Capture/Compare 3 interrupt */\r\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n      /* Disable the TIM Capture/Compare 4 interrupt */\r\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break; \r\n  } \r\n  \r\n  /* Disable the Input Capture channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); \r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim); \r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the TIM Input Capture measurement on in DMA mode.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel: TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @param  pData: The destination Buffer address.\r\n  * @param  Length: The length of data to be transferred from TIM peripheral to memory.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r\n  \r\n  if((htim->State == HAL_TIM_STATE_BUSY))\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  else if((htim->State == HAL_TIM_STATE_READY))\r\n  {\r\n    if((pData == 0 ) && (Length > 0)) \r\n    {\r\n      return HAL_ERROR;                                    \r\n    }\r\n    else\r\n    {\r\n      htim->State = HAL_TIM_STATE_BUSY;\r\n    }\r\n  }  \r\n   \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {\r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); \r\n      \r\n      /* Enable the TIM Capture/Compare 1 DMA request */      \r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);\r\n      \r\n      /* Enable the TIM Capture/Compare 2  DMA request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);\r\n      \r\n      /* Enable the TIM Capture/Compare 3  DMA request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);\r\n      \r\n      /* Enable the TIM Capture/Compare 4  DMA request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break;\r\n  }\r\n\r\n  /* Enable the Input Capture channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\r\n   \r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim); \r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the TIM Input Capture measurement on in DMA mode.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel: TIM Channels to be disabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\r\n  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r\n  \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {       \r\n      /* Disable the TIM Capture/Compare 1 DMA request */\r\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Disable the TIM Capture/Compare 2 DMA request */\r\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      /* Disable the TIM Capture/Compare 3  DMA request */\r\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n      /* Disable the TIM Capture/Compare 4  DMA request */\r\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break;\r\n  }\r\n\r\n  /* Disable the Input Capture channel */\r\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim); \r\n  \r\n  /* Change the htim state */\r\n  htim->State = HAL_TIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}  \r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions \r\n *  @brief    Time One Pulse functions \r\n *\r\n@verbatim    \r\n  ==============================================================================\r\n                        ##### Time One Pulse functions #####\r\n  ==============================================================================\r\n  [..]  \r\n    This section provides functions allowing to:\r\n    (+) Initialize and configure the TIM One Pulse. \r\n    (+) De-initialize the TIM One Pulse.\r\n    (+) Start the Time One Pulse.\r\n    (+) Stop the Time One Pulse.\r\n    (+) Start the Time One Pulse and enable interrupt.\r\n    (+) Stop the Time One Pulse and disable interrupt.\r\n    (+) Start the Time One Pulse and enable DMA transfer.\r\n    (+) Stop the Time One Pulse and disable DMA transfer.\r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n/**\r\n  * @brief  Initializes the TIM One Pulse Time Base according to the specified\r\n  *         parameters in the TIM_HandleTypeDef and create the associated handle.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  OnePulseMode: Select the One pulse mode.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.\r\n  *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)\r\n{\r\n  /* Check the TIM handle allocation */\r\n  if(htim == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\r\n  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r\n  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r\n  assert_param(IS_TIM_OPM_MODE(OnePulseMode));\r\n  \r\n  if(htim->State == HAL_TIM_STATE_RESET)\r\n  { \r\n    /* Allocate lock resource and initialize it */\r\n    htim->Lock = HAL_UNLOCKED;    \r\n    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r\n    HAL_TIM_OnePulse_MspInit(htim);\r\n  }\r\n  \r\n  /* Set the TIM state */\r\n  htim->State= HAL_TIM_STATE_BUSY;  \r\n  \r\n  /* Configure the Time base in the One Pulse Mode */\r\n  TIM_Base_SetConfig(htim->Instance, &htim->Init);\r\n  \r\n  /* Reset the OPM Bit */\r\n  htim->Instance->CR1 &= ~TIM_CR1_OPM;\r\n\r\n  /* Configure the OPM Mode */\r\n  htim->Instance->CR1 |= OnePulseMode;\r\n   \r\n  /* Initialize the TIM state*/\r\n  htim->State= HAL_TIM_STATE_READY;\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the TIM One Pulse  \r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\r\n  \r\n  htim->State = HAL_TIM_STATE_BUSY;\r\n  \r\n  /* Disable the TIM Peripheral Clock */\r\n  __HAL_TIM_DISABLE(htim);\r\n  \r\n  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r\n  HAL_TIM_OnePulse_MspDeInit(htim);\r\n    \r\n  /* Change TIM state */  \r\n  htim->State = HAL_TIM_STATE_RESET;\r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(htim);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the TIM One Pulse MSP.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_TIM_OnePulse_MspInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes TIM One Pulse MSP.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Starts the TIM One Pulse signal generation.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  OutputChannel : TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r\n{\r\n  /* Enable the Capture compare and the Input Capture channels \r\n    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r\n    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r\n    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output \r\n    in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together \r\n    \r\n    No need to enable the counter, it's enabled automatically by hardware \r\n    (the counter starts in response to a stimulus and generate a pulse */\r\n  \r\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); \r\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); \r\n  \r\n  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  \r\n  {\r\n    /* Enable the main output */\r\n    __HAL_TIM_MOE_ENABLE(htim);\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the TIM One Pulse signal generation.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  OutputChannel : TIM Channels to be disable.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r\n{\r\n  /* Disable the Capture compare and the Input Capture channels \r\n  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r\n  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r\n  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output \r\n  in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */\r\n  \r\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); \r\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); \r\n    \r\n  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  \r\n  {\r\n    /* Disable the Main Output */\r\n    __HAL_TIM_MOE_DISABLE(htim);\r\n  }\r\n    \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim); \r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the TIM One Pulse signal generation in interrupt mode.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  OutputChannel : TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r\n{\r\n  /* Enable the Capture compare and the Input Capture channels \r\n    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r\n    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r\n    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output \r\n    in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together \r\n    \r\n    No need to enable the counter, it's enabled automatically by hardware \r\n    (the counter starts in response to a stimulus and generate a pulse */\r\n \r\n  /* Enable the TIM Capture/Compare 1 interrupt */\r\n  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r\n  \r\n  /* Enable the TIM Capture/Compare 2 interrupt */\r\n  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r\n  \r\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); \r\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); \r\n  \r\n  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  \r\n  {\r\n    /* Enable the main output */\r\n    __HAL_TIM_MOE_ENABLE(htim);\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the TIM One Pulse signal generation in interrupt mode.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  OutputChannel : TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r\n{\r\n  /* Disable the TIM Capture/Compare 1 interrupt */\r\n  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);  \r\n  \r\n  /* Disable the TIM Capture/Compare 2 interrupt */\r\n  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r\n  \r\n  /* Disable the Capture compare and the Input Capture channels \r\n  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\r\n  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\r\n  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output \r\n  in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */  \r\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); \r\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); \r\n    \r\n  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  \r\n  {\r\n    /* Disable the Main Output */\r\n    __HAL_TIM_MOE_DISABLE(htim);\r\n  }\r\n    \r\n  /* Disable the Peripheral */\r\n   __HAL_TIM_DISABLE(htim);  \r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions \r\n *  @brief    Time Encoder functions \r\n *\r\n@verbatim    \r\n  ==============================================================================\r\n                          ##### Time Encoder functions #####\r\n  ==============================================================================\r\n  [..]\r\n    This section provides functions allowing to:\r\n    (+) Initialize and configure the TIM Encoder. \r\n    (+) De-initialize the TIM Encoder.\r\n    (+) Start the Time Encoder.\r\n    (+) Stop the Time Encoder.\r\n    (+) Start the Time Encoder and enable interrupt.\r\n    (+) Stop the Time Encoder and disable interrupt.\r\n    (+) Start the Time Encoder and enable DMA transfer.\r\n    (+) Stop the Time Encoder and disable DMA transfer.\r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n/**\r\n  * @brief  Initializes the TIM Encoder Interface and create the associated handle.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  sConfig: TIM Encoder Interface configuration structure\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig)\r\n{\r\n  uint32_t tmpsmcr = 0;\r\n  uint32_t tmpccmr1 = 0;\r\n  uint32_t tmpccer = 0;\r\n  \r\n  /* Check the TIM handle allocation */\r\n  if(htim == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n   \r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n  assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));\r\n  assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));\r\n  assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));\r\n  assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));\r\n  assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));\r\n  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));\r\n  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));\r\n  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));\r\n  assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));\r\n\r\n  if(htim->State == HAL_TIM_STATE_RESET)\r\n  { \r\n    /* Allocate lock resource and initialize it */\r\n    htim->Lock = HAL_UNLOCKED;  \r\n    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r\n    HAL_TIM_Encoder_MspInit(htim);\r\n  }\r\n  \r\n  /* Set the TIM state */\r\n  htim->State= HAL_TIM_STATE_BUSY;   \r\n    \r\n  /* Reset the SMS bits */\r\n  htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r\n  \r\n  /* Configure the Time base in the Encoder Mode */\r\n  TIM_Base_SetConfig(htim->Instance, &htim->Init);  \r\n  \r\n  /* Get the TIMx SMCR register value */\r\n  tmpsmcr = htim->Instance->SMCR;\r\n\r\n  /* Get the TIMx CCMR1 register value */\r\n  tmpccmr1 = htim->Instance->CCMR1;\r\n\r\n  /* Get the TIMx CCER register value */\r\n  tmpccer = htim->Instance->CCER;\r\n\r\n  /* Set the encoder Mode */\r\n  tmpsmcr |= sConfig->EncoderMode;\r\n\r\n  /* Select the Capture Compare 1 and the Capture Compare 2 as input */\r\n  tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);\r\n  tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));\r\n  \r\n  /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */\r\n  tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);\r\n  tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);\r\n  tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);\r\n  tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);\r\n\r\n  /* Set the TI1 and the TI2 Polarities */\r\n  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);\r\n  tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);\r\n  tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);\r\n  \r\n  /* Write to TIMx SMCR */\r\n  htim->Instance->SMCR = tmpsmcr;\r\n\r\n  /* Write to TIMx CCMR1 */\r\n  htim->Instance->CCMR1 = tmpccmr1;\r\n\r\n  /* Write to TIMx CCER */\r\n  htim->Instance->CCER = tmpccer;\r\n  \r\n  /* Initialize the TIM state*/\r\n  htim->State= HAL_TIM_STATE_READY;\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the TIM Encoder interface  \r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\r\n  \r\n  htim->State = HAL_TIM_STATE_BUSY;\r\n  \r\n  /* Disable the TIM Peripheral Clock */\r\n  __HAL_TIM_DISABLE(htim);\r\n  \r\n  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r\n  HAL_TIM_Encoder_MspDeInit(htim);\r\n    \r\n  /* Change TIM state */  \r\n  htim->State = HAL_TIM_STATE_RESET;\r\n \r\n  /* Release Lock */\r\n  __HAL_UNLOCK(htim);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the TIM Encoder Interface MSP.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_TIM_Encoder_MspInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes TIM Encoder Interface MSP.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_TIM_Encoder_MspDeInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Starts the TIM Encoder Interface.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel: TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n  \r\n  /* Enable the encoder interface channels */\r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {\r\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r\n      break; \r\n    }\r\n    case TIM_CHANNEL_2:\r\n    { \r\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); \r\n      break;\r\n    }  \r\n    default :\r\n    {\r\n     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r\n     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r\n     break; \r\n    }\r\n  }  \r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the TIM Encoder Interface.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel: TIM Channels to be disabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n    \r\n   /* Disable the Input Capture channels 1 and 2\r\n    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {\r\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r\n      break; \r\n    }\r\n    case TIM_CHANNEL_2:\r\n    { \r\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); \r\n      break;\r\n    }  \r\n    default :\r\n    {\r\n     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\r\n     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\r\n     break; \r\n    }\r\n  }  \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the TIM Encoder Interface in interrupt mode.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel: TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n  \r\n  /* Enable the encoder interface channels */\r\n  /* Enable the capture compare Interrupts 1 and/or 2 */\r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {\r\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r\n      break; \r\n    }\r\n    case TIM_CHANNEL_2:\r\n    { \r\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); \r\n      break;\r\n    }  \r\n    default :\r\n    {\r\n     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r\n     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r\n     __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r\n     __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r\n     break; \r\n    }\r\n  }\r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the TIM Encoder Interface in interrupt mode.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel: TIM Channels to be disabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n    \r\n  /* Disable the Input Capture channels 1 and 2\r\n    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ \r\n  if(Channel == TIM_CHANNEL_1)\r\n  {\r\n    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); \r\n    \r\n    /* Disable the capture compare Interrupts 1 */\r\n  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r\n  }  \r\n  else if(Channel == TIM_CHANNEL_2)\r\n  {  \r\n    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); \r\n    \r\n    /* Disable the capture compare Interrupts 2 */\r\n  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r\n  }  \r\n  else\r\n  {\r\n    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); \r\n    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); \r\n    \r\n    /* Disable the capture compare Interrupts 1 and 2 */\r\n    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r\n    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r\n  }\r\n    \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim);\r\n  \r\n  /* Change the htim state */\r\n  htim->State = HAL_TIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the TIM Encoder Interface in DMA mode.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel: TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r\n  * @param  pData1: The destination Buffer address for IC1.\r\n  * @param  pData2: The destination Buffer address for IC2.\r\n  * @param  Length: The length of data to be transferred from TIM peripheral to memory.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r\n  \r\n  if((htim->State == HAL_TIM_STATE_BUSY))\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  else if((htim->State == HAL_TIM_STATE_READY))\r\n  {\r\n    if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0)) \r\n    {\r\n      return HAL_ERROR;                                    \r\n    }\r\n    else\r\n    {\r\n      htim->State = HAL_TIM_STATE_BUSY;\r\n    }\r\n  }  \r\n   \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {\r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length); \r\n      \r\n      /* Enable the TIM Input Capture DMA request */      \r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r\n            \r\n      /* Enable the Peripheral */\r\n      __HAL_TIM_ENABLE(htim);\r\n      \r\n      /* Enable the Capture compare channel */\r\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError;\r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);\r\n      \r\n      /* Enable the TIM Input Capture  DMA request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r\n     \r\n      /* Enable the Peripheral */\r\n      __HAL_TIM_ENABLE(htim);\r\n      \r\n      /* Enable the Capture compare channel */\r\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_ALL:\r\n    {\r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);\r\n      \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);\r\n          \r\n     /* Enable the Peripheral */\r\n      __HAL_TIM_ENABLE(htim);\r\n      \r\n      /* Enable the Capture compare channel */\r\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\r\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\r\n      \r\n      /* Enable the TIM Input Capture  DMA request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r\n      /* Enable the TIM Input Capture  DMA request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break;\r\n  }  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the TIM Encoder Interface in DMA mode.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel: TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\r\n  \r\n  /* Disable the Input Capture channels 1 and 2\r\n    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ \r\n  if(Channel == TIM_CHANNEL_1)\r\n  {\r\n    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); \r\n    \r\n    /* Disable the capture compare DMA Request 1 */\r\n    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r\n  }  \r\n  else if(Channel == TIM_CHANNEL_2)\r\n  {  \r\n    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); \r\n    \r\n    /* Disable the capture compare DMA Request 2 */\r\n    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r\n  }  \r\n  else\r\n  {\r\n    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); \r\n    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); \r\n    \r\n    /* Disable the capture compare DMA Request 1 and 2 */\r\n    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r\n    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r\n  }\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim);\r\n  \r\n  /* Change the htim state */\r\n  htim->State = HAL_TIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management \r\n *  @brief    IRQ handler management \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                        ##### IRQ handler management #####\r\n  ==============================================================================  \r\n  [..]  \r\n    This section provides Timer IRQ handler function.\r\n               \r\n@endverbatim\r\n  * @{\r\n  */\r\n/**\r\n  * @brief  This function handles TIM interrupts requests.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\nvoid HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Capture compare 1 event */\r\n  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)\r\n  {\r\n    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)\r\n    {\r\n      {\r\n        __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);\r\n        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r\n        \r\n        /* Input capture event */\r\n        if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)\r\n        {\r\n          HAL_TIM_IC_CaptureCallback(htim);\r\n        }\r\n        /* Output compare event */\r\n        else\r\n        {\r\n          HAL_TIM_OC_DelayElapsedCallback(htim);\r\n          HAL_TIM_PWM_PulseFinishedCallback(htim);\r\n        }\r\n        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r\n      }\r\n    }\r\n  }\r\n  /* Capture compare 2 event */\r\n  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)\r\n  {\r\n    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)\r\n    {\r\n      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);\r\n      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r\n      /* Input capture event */\r\n      if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)\r\n      {          \r\n        HAL_TIM_IC_CaptureCallback(htim);\r\n      }\r\n      /* Output compare event */\r\n      else\r\n      {\r\n        HAL_TIM_OC_DelayElapsedCallback(htim);\r\n        HAL_TIM_PWM_PulseFinishedCallback(htim);\r\n      }\r\n      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r\n    }\r\n  }\r\n  /* Capture compare 3 event */\r\n  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)\r\n  {\r\n    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)\r\n    {\r\n      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);\r\n      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r\n      /* Input capture event */\r\n      if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)\r\n      {          \r\n        HAL_TIM_IC_CaptureCallback(htim);\r\n      }\r\n      /* Output compare event */\r\n      else\r\n      {\r\n        HAL_TIM_OC_DelayElapsedCallback(htim);\r\n        HAL_TIM_PWM_PulseFinishedCallback(htim); \r\n      }\r\n      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r\n    }\r\n  }\r\n  /* Capture compare 4 event */\r\n  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)\r\n  {\r\n    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)\r\n    {\r\n      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);\r\n      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r\n      /* Input capture event */\r\n      if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)\r\n      {          \r\n        HAL_TIM_IC_CaptureCallback(htim);\r\n      }\r\n      /* Output compare event */\r\n      else\r\n      {\r\n        HAL_TIM_OC_DelayElapsedCallback(htim);\r\n        HAL_TIM_PWM_PulseFinishedCallback(htim);\r\n      }\r\n      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r\n    }\r\n  }\r\n  /* TIM Update event */\r\n  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)\r\n  {\r\n    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)\r\n    {\r\n      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);\r\n      HAL_TIM_PeriodElapsedCallback(htim);\r\n    }\r\n  }\r\n  /* TIM Break input event */\r\n  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)\r\n  {\r\n    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)\r\n    {\r\n      __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);\r\n      HAL_TIMEx_BreakCallback(htim);\r\n    }\r\n  }\r\n  \r\n    /* TIM Break input event */\r\n  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)\r\n  {\r\n    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)\r\n    {\r\n      __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);\r\n      HAL_TIMEx_BreakCallback(htim);\r\n    }\r\n  }\r\n\r\n  /* TIM Trigger detection event */\r\n  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)\r\n  {\r\n    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)\r\n    {\r\n      __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);\r\n      HAL_TIM_TriggerCallback(htim);\r\n    }\r\n  }\r\n  /* TIM commutation event */\r\n  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)\r\n  {\r\n    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)\r\n    {\r\n      __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);\r\n      HAL_TIMEx_CommutationCallback(htim);\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions\r\n *  @brief   \tPeripheral Control functions \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                   ##### Peripheral Control functions #####\r\n  ==============================================================================  \r\n [..] \r\n   This section provides functions allowing to:\r\n   (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. \r\n   (+) Configure External Clock source.\r\n   (+) Configure Complementary channels, break features and dead time.\r\n   (+) Configure Master and the Slave synchronization.\r\n   (+) Configure the DMA Burst Mode.\r\n      \r\n@endverbatim\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @brief  Initializes the TIM Output Compare Channels according to the specified\r\n  *         parameters in the TIM_OC_InitTypeDef.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  sConfig: TIM Output Compare configuration structure\r\n  * @param  Channel: TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected \r\n  * @retval HAL status\r\n  */\r\n__weak HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)\r\n{\r\n  /* Check the parameters */ \r\n  assert_param(IS_TIM_CHANNELS(Channel)); \r\n  assert_param(IS_TIM_OC_MODE(sConfig->OCMode));\r\n  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));\r\n  \r\n  /* Check input state */\r\n  __HAL_LOCK(htim); \r\n  \r\n  htim->State = HAL_TIM_STATE_BUSY;\r\n  \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {\r\n      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r\n      /* Configure the TIM Channel 1 in Output Compare */\r\n      TIM_OC1_SetConfig(htim->Instance, sConfig);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n      /* Configure the TIM Channel 2 in Output Compare */\r\n      TIM_OC2_SetConfig(htim->Instance, sConfig);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r\n      /* Configure the TIM Channel 3 in Output Compare */\r\n      TIM_OC3_SetConfig(htim->Instance, sConfig);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r\n      /* Configure the TIM Channel 4 in Output Compare */\r\n      TIM_OC4_SetConfig(htim->Instance, sConfig);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break;    \r\n  }\r\n  htim->State = HAL_TIM_STATE_READY;\r\n  \r\n  __HAL_UNLOCK(htim); \r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the TIM Input Capture Channels according to the specified\r\n  *         parameters in the TIM_IC_InitTypeDef.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  sConfig: TIM Input Capture configuration structure\r\n  * @param  Channel: TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r\n  assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));\r\n  assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));\r\n  assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));\r\n  assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));\r\n  \r\n  __HAL_LOCK(htim);\r\n  \r\n  htim->State = HAL_TIM_STATE_BUSY;\r\n  \r\n  if (Channel == TIM_CHANNEL_1)\r\n  {\r\n    /* TI1 Configuration */\r\n    TIM_TI1_SetConfig(htim->Instance,\r\n               sConfig->ICPolarity,\r\n               sConfig->ICSelection,\r\n               sConfig->ICFilter);\r\n               \r\n    /* Reset the IC1PSC Bits */\r\n    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;\r\n\r\n    /* Set the IC1PSC value */\r\n    htim->Instance->CCMR1 |= sConfig->ICPrescaler;\r\n  }\r\n  else if (Channel == TIM_CHANNEL_2)\r\n  {\r\n    /* TI2 Configuration */\r\n    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n    \r\n    TIM_TI2_SetConfig(htim->Instance, \r\n                      sConfig->ICPolarity,\r\n                      sConfig->ICSelection,\r\n                      sConfig->ICFilter);\r\n               \r\n    /* Reset the IC2PSC Bits */\r\n    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;\r\n\r\n    /* Set the IC2PSC value */\r\n    htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);\r\n  }\r\n  else if (Channel == TIM_CHANNEL_3)\r\n  {\r\n    /* TI3 Configuration */\r\n    assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r\n    \r\n    TIM_TI3_SetConfig(htim->Instance,  \r\n               sConfig->ICPolarity,\r\n               sConfig->ICSelection,\r\n               sConfig->ICFilter);\r\n               \r\n    /* Reset the IC3PSC Bits */\r\n    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;\r\n\r\n    /* Set the IC3PSC value */\r\n    htim->Instance->CCMR2 |= sConfig->ICPrescaler;\r\n  }\r\n  else\r\n  {\r\n    /* TI4 Configuration */\r\n    assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r\n    \r\n    TIM_TI4_SetConfig(htim->Instance, \r\n               sConfig->ICPolarity,\r\n               sConfig->ICSelection,\r\n               sConfig->ICFilter);\r\n               \r\n    /* Reset the IC4PSC Bits */\r\n    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;\r\n\r\n    /* Set the IC4PSC value */\r\n    htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);\r\n  }\r\n  \r\n  htim->State = HAL_TIM_STATE_READY;\r\n    \r\n  __HAL_UNLOCK(htim);\r\n  \r\n  return HAL_OK; \r\n}\r\n\r\n/**\r\n  * @brief  Initializes the TIM PWM  channels according to the specified\r\n  *         parameters in the TIM_OC_InitTypeDef.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  sConfig: TIM PWM configuration structure\r\n  * @param  Channel: TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\n__weak HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)\r\n{\r\n  __HAL_LOCK(htim);\r\n  \r\n  /* Check the parameters */ \r\n  assert_param(IS_TIM_CHANNELS(Channel)); \r\n  assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));\r\n  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));\r\n  assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); \r\n  \r\n  htim->State = HAL_TIM_STATE_BUSY;\r\n    \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {\r\n      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r\n      /* Configure the Channel 1 in PWM mode */\r\n      TIM_OC1_SetConfig(htim->Instance, sConfig);\r\n      \r\n      /* Set the Preload enable bit for channel1 */\r\n      htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;\r\n      \r\n      /* Configure the Output Fast mode */\r\n      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;\r\n      htim->Instance->CCMR1 |= sConfig->OCFastMode;\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n      /* Configure the Channel 2 in PWM mode */\r\n      TIM_OC2_SetConfig(htim->Instance, sConfig);\r\n      \r\n      /* Set the Preload enable bit for channel2 */\r\n      htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;\r\n      \r\n      /* Configure the Output Fast mode */\r\n      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;\r\n      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r\n      /* Configure the Channel 3 in PWM mode */\r\n      TIM_OC3_SetConfig(htim->Instance, sConfig);\r\n      \r\n      /* Set the Preload enable bit for channel3 */\r\n      htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;\r\n      \r\n     /* Configure the Output Fast mode */\r\n      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;\r\n      htim->Instance->CCMR2 |= sConfig->OCFastMode;  \r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r\n      /* Configure the Channel 4 in PWM mode */\r\n      TIM_OC4_SetConfig(htim->Instance, sConfig);\r\n      \r\n      /* Set the Preload enable bit for channel4 */\r\n      htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;\r\n      \r\n     /* Configure the Output Fast mode */\r\n      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;\r\n      htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;  \r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break;    \r\n  }\r\n  \r\n  htim->State = HAL_TIM_STATE_READY;\r\n    \r\n  __HAL_UNLOCK(htim);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the TIM One Pulse Channels according to the specified\r\n  *         parameters in the TIM_OnePulse_InitTypeDef.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  sConfig: TIM One Pulse configuration structure\r\n  * @param  OutputChannel: TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  * @param  InputChannel: TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel,  uint32_t InputChannel)\r\n{\r\n  TIM_OC_InitTypeDef temp1;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));\r\n  assert_param(IS_TIM_OPM_CHANNELS(InputChannel));\r\n\r\n  if(OutputChannel != InputChannel)  \r\n  {\r\n    __HAL_LOCK(htim);\r\n  \r\n    htim->State = HAL_TIM_STATE_BUSY;\r\n\r\n    /* Extract the Output compare configuration from sConfig structure */  \r\n    temp1.OCMode = sConfig->OCMode;\r\n    temp1.Pulse = sConfig->Pulse;\r\n    temp1.OCPolarity = sConfig->OCPolarity;\r\n    temp1.OCNPolarity = sConfig->OCNPolarity;\r\n    temp1.OCIdleState = sConfig->OCIdleState;\r\n    temp1.OCNIdleState = sConfig->OCNIdleState; \r\n    \r\n    switch (OutputChannel)\r\n    {\r\n      case TIM_CHANNEL_1:\r\n      {\r\n        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r\n      \r\n        TIM_OC1_SetConfig(htim->Instance, &temp1); \r\n      }\r\n      break;\r\n      case TIM_CHANNEL_2:\r\n      {\r\n        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n      \r\n        TIM_OC2_SetConfig(htim->Instance, &temp1);\r\n      }\r\n      break;\r\n      default:\r\n      break;  \r\n    } \r\n    switch (InputChannel)\r\n    {\r\n      case TIM_CHANNEL_1:\r\n      {\r\n        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r\n      \r\n        TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,\r\n                        sConfig->ICSelection, sConfig->ICFilter);\r\n               \r\n        /* Reset the IC1PSC Bits */\r\n        htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;\r\n\r\n        /* Select the Trigger source */\r\n        htim->Instance->SMCR &= ~TIM_SMCR_TS;\r\n        htim->Instance->SMCR |= TIM_TS_TI1FP1;\r\n      \r\n        /* Select the Slave Mode */      \r\n        htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r\n        htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;\r\n      }\r\n      break;\r\n      case TIM_CHANNEL_2:\r\n      {\r\n        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n      \r\n        TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,\r\n                 sConfig->ICSelection, sConfig->ICFilter);\r\n               \r\n        /* Reset the IC2PSC Bits */\r\n        htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;\r\n\r\n        /* Select the Trigger source */\r\n        htim->Instance->SMCR &= ~TIM_SMCR_TS;\r\n        htim->Instance->SMCR |= TIM_TS_TI2FP2;\r\n      \r\n        /* Select the Slave Mode */      \r\n        htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r\n        htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;\r\n      }\r\n      break;\r\n    \r\n      default:\r\n      break;  \r\n    }\r\n  \r\n    htim->State = HAL_TIM_STATE_READY;\r\n    \r\n    __HAL_UNLOCK(htim);\r\n  \r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n} \r\n\r\n/**\r\n  * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral  \r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.\r\n  *         This parameters can be on of the following values:\r\n  *            @arg TIM_DMABASE_CR1  \r\n  *            @arg TIM_DMABASE_CR2\r\n  *            @arg TIM_DMABASE_SMCR\r\n  *            @arg TIM_DMABASE_DIER\r\n  *            @arg TIM_DMABASE_SR\r\n  *            @arg TIM_DMABASE_EGR\r\n  *            @arg TIM_DMABASE_CCMR1\r\n  *            @arg TIM_DMABASE_CCMR2\r\n  *            @arg TIM_DMABASE_CCER\r\n  *            @arg TIM_DMABASE_CNT   \r\n  *            @arg TIM_DMABASE_PSC   \r\n  *            @arg TIM_DMABASE_ARR\r\n  *            @arg TIM_DMABASE_RCR\r\n  *            @arg TIM_DMABASE_CCR1\r\n  *            @arg TIM_DMABASE_CCR2\r\n  *            @arg TIM_DMABASE_CCR3  \r\n  *            @arg TIM_DMABASE_CCR4\r\n  *            @arg TIM_DMABASE_BDTR\r\n  *            @arg TIM_DMABASE_DCR\r\n  * @param  BurstRequestSrc: TIM DMA Request sources.\r\n  *         This parameters can be on of the following values:\r\n  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source\r\n  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\r\n  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\r\n  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\r\n  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\r\n  *            @arg TIM_DMA_COM: TIM Commutation DMA source\r\n  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source\r\n  * @param  BurstBuffer: The Buffer address.\r\n  * @param  BurstLength: DMA Burst length. This parameter can be one value\r\n  *         between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,\r\n                                              uint32_t* BurstBuffer, uint32_t  BurstLength)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));\r\n  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));\r\n  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r\n  assert_param(IS_TIM_DMA_LENGTH(BurstLength));\r\n  \r\n  if((htim->State == HAL_TIM_STATE_BUSY))\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  else if((htim->State == HAL_TIM_STATE_READY))\r\n  {\r\n    if((BurstBuffer == 0 ) && (BurstLength > 0)) \r\n    {\r\n      return HAL_ERROR;                                    \r\n    }\r\n    else\r\n    {\r\n      htim->State = HAL_TIM_STATE_BUSY;\r\n    }\r\n  }\r\n  switch(BurstRequestSrc)\r\n  {\r\n    case TIM_DMA_UPDATE:\r\n    {  \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;\r\n  \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); \r\n    }\r\n    break;\r\n    case TIM_DMA_CC1:\r\n    {  \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r\n  \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);     \r\n    }\r\n    break;\r\n    case TIM_DMA_CC2:\r\n    {  \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;\r\n  \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);     \r\n    }\r\n    break;\r\n    case TIM_DMA_CC3:\r\n    {  \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;\r\n  \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);     \r\n    }\r\n    break;\r\n    case TIM_DMA_CC4:\r\n    {  \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;\r\n  \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);     \r\n    }\r\n    break;\r\n    case TIM_DMA_COM:\r\n    {  \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;\r\n  \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);     \r\n    }\r\n    break;\r\n    case TIM_DMA_TRIGGER:\r\n    {  \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;\r\n  \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);     \r\n    }\r\n    break;\r\n    default:\r\n    break;  \r\n  }\r\n   /* configure the DMA Burst Mode */\r\n   htim->Instance->DCR = BurstBaseAddress | BurstLength;  \r\n   \r\n   /* Enable the TIM DMA Request */\r\n   __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);  \r\n   \r\n   htim->State = HAL_TIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the TIM DMA Burst mode \r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  BurstRequestSrc: TIM DMA Request sources to disable\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r\n  \r\n  /* Abort the DMA transfer (at least disable the DMA channel) */\r\n  switch(BurstRequestSrc)\r\n  {\r\n    case TIM_DMA_UPDATE:\r\n    {  \r\n      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);\r\n    }\r\n    break;\r\n    case TIM_DMA_CC1:\r\n    {  \r\n      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);\r\n    }\r\n    break;\r\n    case TIM_DMA_CC2:\r\n    {  \r\n      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);\r\n    }\r\n    break;\r\n    case TIM_DMA_CC3:\r\n    {  \r\n      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);\r\n    }\r\n    break;\r\n    case TIM_DMA_CC4:\r\n    {  \r\n      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);\r\n    }\r\n    break;\r\n    case TIM_DMA_COM:\r\n    {  \r\n      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);\r\n    }\r\n    break;\r\n    case TIM_DMA_TRIGGER:\r\n    {  \r\n      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);\r\n    }\r\n    break;\r\n    default:\r\n    break;\r\n  }\r\n\r\n  /* Disable the TIM Update DMA request */\r\n  __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);\r\n      \r\n  /* Return function status */\r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory \r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.\r\n  *         This parameters can be on of the following values:\r\n  *            @arg TIM_DMABASE_CR1  \r\n  *            @arg TIM_DMABASE_CR2\r\n  *            @arg TIM_DMABASE_SMCR\r\n  *            @arg TIM_DMABASE_DIER\r\n  *            @arg TIM_DMABASE_SR\r\n  *            @arg TIM_DMABASE_EGR\r\n  *            @arg TIM_DMABASE_CCMR1\r\n  *            @arg TIM_DMABASE_CCMR2\r\n  *            @arg TIM_DMABASE_CCER\r\n  *            @arg TIM_DMABASE_CNT   \r\n  *            @arg TIM_DMABASE_PSC   \r\n  *            @arg TIM_DMABASE_ARR\r\n  *            @arg TIM_DMABASE_RCR\r\n  *            @arg TIM_DMABASE_CCR1\r\n  *            @arg TIM_DMABASE_CCR2\r\n  *            @arg TIM_DMABASE_CCR3  \r\n  *            @arg TIM_DMABASE_CCR4\r\n  *            @arg TIM_DMABASE_BDTR\r\n  *            @arg TIM_DMABASE_DCR\r\n  * @param  BurstRequestSrc: TIM DMA Request sources.\r\n  *         This parameters can be on of the following values:\r\n  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source\r\n  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\r\n  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\r\n  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\r\n  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\r\n  *            @arg TIM_DMA_COM: TIM Commutation DMA source\r\n  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source\r\n  * @param  BurstBuffer: The Buffer address.\r\n  * @param  BurstLength: DMA Burst length. This parameter can be one value\r\n  *         between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,\r\n                                             uint32_t  *BurstBuffer, uint32_t  BurstLength)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));\r\n  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));\r\n  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r\n  assert_param(IS_TIM_DMA_LENGTH(BurstLength));\r\n  \r\n  if((htim->State == HAL_TIM_STATE_BUSY))\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  else if((htim->State == HAL_TIM_STATE_READY))\r\n  {\r\n    if((BurstBuffer == 0 ) && (BurstLength > 0)) \r\n    {\r\n      return HAL_ERROR;                                    \r\n    }\r\n    else\r\n    {\r\n      htim->State = HAL_TIM_STATE_BUSY;\r\n    }\r\n  }  \r\n  switch(BurstRequestSrc)\r\n  {\r\n    case TIM_DMA_UPDATE:\r\n    {  \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;\r\n  \r\n      /* Enable the DMA Stream */\r\n       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);     \r\n    }\r\n    break;\r\n    case TIM_DMA_CC1:\r\n    {  \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r\n  \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);      \r\n    }\r\n    break;\r\n    case TIM_DMA_CC2:\r\n    {  \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;\r\n  \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);     \r\n    }\r\n    break;\r\n    case TIM_DMA_CC3:\r\n    {  \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;\r\n  \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);      \r\n    }\r\n    break;\r\n    case TIM_DMA_CC4:\r\n    {  \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;\r\n  \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);      \r\n    }\r\n    break;\r\n    case TIM_DMA_COM:\r\n    {  \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;\r\n  \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);      \r\n    }\r\n    break;\r\n    case TIM_DMA_TRIGGER:\r\n    {  \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;\r\n  \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);      \r\n    }\r\n    break;\r\n    default:\r\n    break;  \r\n  }\r\n\r\n  /* configure the DMA Burst Mode */\r\n  htim->Instance->DCR = BurstBaseAddress | BurstLength;  \r\n  \r\n  /* Enable the TIM DMA Request */\r\n  __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);\r\n  \r\n  htim->State = HAL_TIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stop the DMA burst reading \r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  BurstRequestSrc: TIM DMA Request sources to disable.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\r\n  \r\n  /* Abort the DMA transfer (at least disable the DMA channel) */\r\n  switch(BurstRequestSrc)\r\n  {\r\n    case TIM_DMA_UPDATE:\r\n    {  \r\n      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);\r\n    }\r\n    break;\r\n    case TIM_DMA_CC1:\r\n    {  \r\n      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);\r\n    }\r\n    break;\r\n    case TIM_DMA_CC2:\r\n    {  \r\n      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);\r\n    }\r\n    break;\r\n    case TIM_DMA_CC3:\r\n    {  \r\n      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);\r\n    }\r\n    break;\r\n    case TIM_DMA_CC4:\r\n    {  \r\n      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);\r\n    }\r\n    break;\r\n    case TIM_DMA_COM:\r\n    {  \r\n      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);\r\n    }\r\n    break;\r\n    case TIM_DMA_TRIGGER:\r\n    {  \r\n      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);\r\n    }\r\n    break;\r\n    default:\r\n    break;  \r\n  }\r\n  \r\n  /* Disable the TIM Update DMA request */\r\n  __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);\r\n      \r\n  /* Return function status */\r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Generate a software event\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  EventSource: specifies the event source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source\r\n  *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source\r\n  *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source\r\n  *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source\r\n  *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source\r\n  *            @arg TIM_EVENTSOURCE_COM: Timer COM event source  \r\n  *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source\r\n  *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source\r\n  *            @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source  \r\n  * @note   TIM6 and TIM7 can only generate an update event. \r\n  * @note   TIM_EVENTSOURCE_COM, TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are used only with TIM1 and TIM8.\r\n  * @retval HAL status\r\n  */ \r\n\r\nHAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\r\n  assert_param(IS_TIM_EVENT_SOURCE(EventSource));\r\n  \r\n  /* Process Locked */\r\n  __HAL_LOCK(htim);\r\n  \r\n  /* Change the TIM state */\r\n  htim->State = HAL_TIM_STATE_BUSY;\r\n  \r\n  /* Set the event sources */\r\n  htim->Instance->EGR = EventSource;\r\n  \r\n  /* Change the TIM state */\r\n  htim->State = HAL_TIM_STATE_READY;\r\n  \r\n  __HAL_UNLOCK(htim);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Configures the OCRef clear feature\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that\r\n  *         contains the OCREF clear feature and parameters for the TIM peripheral. \r\n  * @param  Channel: specifies the TIM Channel.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */ \r\n__weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)\r\n{ \r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r\n  assert_param(IS_TIM_CHANNELS(Channel));\r\n  assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));\r\n   \r\n  /* Process Locked */\r\n  __HAL_LOCK(htim);\r\n  \r\n  htim->State = HAL_TIM_STATE_BUSY;\r\n  \r\n  if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)\r\n  {\r\n    assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));\r\n    assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));\r\n    assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));\r\n  \r\n    TIM_ETR_SetConfig(htim->Instance, \r\n                      sClearInputConfig->ClearInputPrescaler,\r\n                      sClearInputConfig->ClearInputPolarity,\r\n                      sClearInputConfig->ClearInputFilter);\r\n  }\r\n  \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {        \r\n      if(sClearInputConfig->ClearInputState != RESET)  \r\n      {\r\n        /* Enable the Ocref clear feature for Channel 1 */\r\n        htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;\r\n      }\r\n      else\r\n      {\r\n        /* Disable the Ocref clear feature for Channel 1 */\r\n        htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;      \r\n      }\r\n    }    \r\n    break;\r\n    case TIM_CHANNEL_2:    \r\n    { \r\n      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); \r\n      if(sClearInputConfig->ClearInputState != RESET)  \r\n      {\r\n        /* Enable the Ocref clear feature for Channel 2 */\r\n        htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;\r\n      }\r\n      else\r\n      {\r\n        /* Disable the Ocref clear feature for Channel 2 */\r\n        htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;      \r\n      }\r\n    } \r\n    break;\r\n    case TIM_CHANNEL_3:   \r\n    {  \r\n      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r\n      if(sClearInputConfig->ClearInputState != RESET)  \r\n      {\r\n        /* Enable the Ocref clear feature for Channel 3 */\r\n        htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;\r\n      }\r\n      else\r\n      {\r\n        /* Disable the Ocref clear feature for Channel 3 */\r\n        htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;      \r\n      }\r\n    } \r\n    break;\r\n    case TIM_CHANNEL_4:    \r\n    {  \r\n      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r\n      if(sClearInputConfig->ClearInputState != RESET)  \r\n      {\r\n        /* Enable the Ocref clear feature for Channel 4 */\r\n        htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;\r\n      }\r\n      else\r\n      {\r\n        /* Disable the Ocref clear feature for Channel 4 */\r\n        htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;      \r\n      }\r\n    } \r\n    break;\r\n    default:  \r\n    break;\r\n  } \r\n\r\n  htim->State = HAL_TIM_STATE_READY;\r\n  \r\n  __HAL_UNLOCK(htim);\r\n  \r\n  return HAL_OK;  \r\n}  \r\n\r\n/**\r\n  * @brief   Configures the clock source to be used\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that\r\n  *         contains the clock source information for the TIM peripheral. \r\n  * @retval HAL status\r\n  */ \r\nHAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)    \r\n{\r\n  uint32_t tmpsmcr = 0;\r\n    \r\n  /* Process Locked */\r\n  __HAL_LOCK(htim);\r\n  \r\n  htim->State = HAL_TIM_STATE_BUSY;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));\r\n  \r\n  /* Reset the SMS, TS, ECE, ETPS and ETRF bits */\r\n  tmpsmcr = htim->Instance->SMCR;\r\n  tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);\r\n  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);\r\n  htim->Instance->SMCR = tmpsmcr;\r\n  \r\n  switch (sClockSourceConfig->ClockSource)\r\n  {\r\n    case TIM_CLOCKSOURCE_INTERNAL:\r\n    { \r\n      assert_param(IS_TIM_INSTANCE(htim->Instance));      \r\n      /* Disable slave mode to clock the prescaler directly with the internal clock */\r\n      htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r\n    }\r\n    break;\r\n    \r\n    case TIM_CLOCKSOURCE_ETRMODE1:\r\n    {\r\n      assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));\r\n      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r\n      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));\r\n      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r\n      /* Configure the ETR Clock source */\r\n      TIM_ETR_SetConfig(htim->Instance, \r\n                        sClockSourceConfig->ClockPrescaler, \r\n                        sClockSourceConfig->ClockPolarity, \r\n                        sClockSourceConfig->ClockFilter);\r\n      /* Get the TIMx SMCR register value */\r\n      tmpsmcr = htim->Instance->SMCR;\r\n      /* Reset the SMS and TS Bits */\r\n      tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);\r\n      /* Select the External clock mode1 and the ETRF trigger */\r\n      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);\r\n      /* Write to TIMx SMCR */\r\n      htim->Instance->SMCR = tmpsmcr;\r\n    }\r\n    break;\r\n    \r\n    case TIM_CLOCKSOURCE_ETRMODE2:\r\n    {\r\n      assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));\r\n      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r\n      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));\r\n      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r\n      \r\n      /* Configure the ETR Clock source */\r\n      TIM_ETR_SetConfig(htim->Instance, \r\n                        sClockSourceConfig->ClockPrescaler, \r\n                        sClockSourceConfig->ClockPolarity,\r\n                        sClockSourceConfig->ClockFilter);\r\n      /* Enable the External clock mode2 */\r\n      htim->Instance->SMCR |= TIM_SMCR_ECE;\r\n    }\r\n    break;\r\n    \r\n    case TIM_CLOCKSOURCE_TI1:\r\n    {\r\n      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));\r\n  \r\n      /* Check TI1 input conditioning related parameters */\r\n      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r\n      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r\n\r\n      TIM_TI1_ConfigInputStage(htim->Instance, \r\n                        sClockSourceConfig->ClockPolarity, \r\n                        sClockSourceConfig->ClockFilter);\r\n      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);\r\n    }\r\n    break;\r\n    case TIM_CLOCKSOURCE_TI2:\r\n    {\r\n      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));\r\n      \r\n      /* Check TI1 input conditioning related parameters */\r\n      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r\n      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r\n\r\n      TIM_TI2_ConfigInputStage(htim->Instance, \r\n                        sClockSourceConfig->ClockPolarity, \r\n                        sClockSourceConfig->ClockFilter);\r\n      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);\r\n    }\r\n    break;\r\n    case TIM_CLOCKSOURCE_TI1ED:\r\n    {\r\n      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));\r\n      /* Check TI1 input conditioning related parameters */\r\n      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\r\n      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\r\n  \r\n      TIM_TI1_ConfigInputStage(htim->Instance, \r\n                        sClockSourceConfig->ClockPolarity,\r\n                        sClockSourceConfig->ClockFilter);\r\n      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);\r\n    }\r\n    break;\r\n    case TIM_CLOCKSOURCE_ITR0:\r\n    {\r\n      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));\r\n      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);\r\n    }\r\n    break;\r\n    case TIM_CLOCKSOURCE_ITR1:\r\n    {\r\n      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));\r\n      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);\r\n    }\r\n    break;\r\n    case TIM_CLOCKSOURCE_ITR2:\r\n    {\r\n      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));\r\n      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);\r\n    }\r\n    break;\r\n    case TIM_CLOCKSOURCE_ITR3:\r\n    {\r\n      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));\r\n      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break;    \r\n  }\r\n  htim->State = HAL_TIM_STATE_READY;\r\n  \r\n  __HAL_UNLOCK(htim);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Selects the signal connected to the TI1 input: direct from CH1_input\r\n  *         or a XOR combination between CH1_input, CH2_input & CH3_input\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  TI1_Selection: Indicate whether or not channel 1 is connected to the\r\n  *         output of a XOR gate.\r\n  *         This parameter can be one of the following values:\r\n  *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input\r\n  *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3\r\n  *            pins are connected to the TI1 input (XOR combination)\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)\r\n{\r\n  uint32_t tmpcr2 = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); \r\n  assert_param(IS_TIM_TI1SELECTION(TI1_Selection));\r\n\r\n  /* Get the TIMx CR2 register value */\r\n  tmpcr2 = htim->Instance->CR2;\r\n\r\n  /* Reset the TI1 selection */\r\n  tmpcr2 &= ~TIM_CR2_TI1S;\r\n\r\n  /* Set the TI1 selection */\r\n  tmpcr2 |= TI1_Selection;\r\n  \r\n  /* Write to TIMxCR2 */\r\n  htim->Instance->CR2 = tmpcr2;\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Configures the TIM in Slave mode\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that\r\n  *         contains the selected trigger (internal trigger input, filtered\r\n  *         timer input or external trigger input) and the ) and the Slave \r\n  *         mode (Disable, Reset, Gated, Trigger, External clock mode 1). \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)\r\n{\r\n  uint32_t tmpsmcr  = 0;\r\n  uint32_t tmpccmr1 = 0;\r\n  uint32_t tmpccer = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));\r\n  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));\r\n  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));\r\n   \r\n  __HAL_LOCK(htim);\r\n  \r\n  htim->State = HAL_TIM_STATE_BUSY;\r\n\r\n  /* Get the TIMx SMCR register value */\r\n  tmpsmcr = htim->Instance->SMCR;\r\n\r\n  /* Reset the Trigger Selection Bits */\r\n  tmpsmcr &= ~TIM_SMCR_TS;\r\n  /* Set the Input Trigger source */\r\n  tmpsmcr |= sSlaveConfig->InputTrigger;\r\n\r\n  /* Reset the slave mode Bits */\r\n  tmpsmcr &= ~TIM_SMCR_SMS;\r\n  /* Set the slave mode */\r\n  tmpsmcr |= sSlaveConfig->SlaveMode;\r\n\r\n  /* Write to TIMx SMCR */\r\n  htim->Instance->SMCR = tmpsmcr;\r\n  \r\n  /* Configure the trigger prescaler, filter, and polarity */\r\n  switch (sSlaveConfig->InputTrigger)\r\n  {\r\n  case TIM_TS_ETRF:\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));\r\n      assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));\r\n      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r\n      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r\n      /* Configure the ETR Trigger source */\r\n      TIM_ETR_SetConfig(htim->Instance, \r\n                        sSlaveConfig->TriggerPrescaler, \r\n                        sSlaveConfig->TriggerPolarity, \r\n                        sSlaveConfig->TriggerFilter);\r\n    }\r\n    break;\r\n    \r\n  case TIM_TS_TI1F_ED:\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r\n      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r\n      \r\n      /* Disable the Channel 1: Reset the CC1E Bit */\r\n      tmpccer = htim->Instance->CCER;\r\n      htim->Instance->CCER &= ~TIM_CCER_CC1E;\r\n      tmpccmr1 = htim->Instance->CCMR1;    \r\n      \r\n      /* Set the filter */\r\n      tmpccmr1 &= ~TIM_CCMR1_IC1F;\r\n      tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);\r\n      \r\n      /* Write to TIMx CCMR1 and CCER registers */\r\n      htim->Instance->CCMR1 = tmpccmr1;\r\n      htim->Instance->CCER = tmpccer;                               \r\n                               \r\n    }\r\n    break;\r\n    \r\n  case TIM_TS_TI1FP1:\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r\n      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r\n      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r\n\r\n      /* Configure TI1 Filter and Polarity */\r\n      TIM_TI1_ConfigInputStage(htim->Instance,\r\n                               sSlaveConfig->TriggerPolarity,\r\n                               sSlaveConfig->TriggerFilter);\r\n    }\r\n    break;\r\n    \r\n  case TIM_TS_TI2FP2:\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r\n      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r\n      \r\n      /* Configure TI2 Filter and Polarity */\r\n      TIM_TI2_ConfigInputStage(htim->Instance,\r\n                                sSlaveConfig->TriggerPolarity,\r\n                                sSlaveConfig->TriggerFilter);\r\n    }\r\n    break;\r\n    \r\n  case TIM_TS_ITR0:\r\n    {\r\n      /* Check the parameter */\r\n      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n    }\r\n    break;\r\n    \r\n  case TIM_TS_ITR1:\r\n    {\r\n      /* Check the parameter */\r\n      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n    }\r\n    break;\r\n    \r\n  case TIM_TS_ITR2:\r\n    {\r\n      /* Check the parameter */\r\n      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n    }\r\n    break;\r\n    \r\n  case TIM_TS_ITR3:\r\n    {\r\n      /* Check the parameter */\r\n      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n    }\r\n    break;\r\n       \r\n  default:\r\n    break;\r\n  }\r\n  \r\n  htim->State = HAL_TIM_STATE_READY;\r\n     \r\n  __HAL_UNLOCK(htim);  \r\n  \r\n  return HAL_OK;\r\n} \r\n\r\n/**\r\n  * @brief  Configures the TIM in Slave mode in interrupt mode\r\n  * @param  htim: TIM handle.\r\n  * @param  sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that\r\n  *         contains the selected trigger (internal trigger input, filtered\r\n  *         timer input or external trigger input) and the ) and the Slave \r\n  *         mode (Disable, Reset, Gated, Trigger, External clock mode 1). \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, \r\n                                                        TIM_SlaveConfigTypeDef * sSlaveConfig)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));\r\n  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));\r\n  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));\r\n  \r\n  __HAL_LOCK(htim);\r\n\r\n  htim->State = HAL_TIM_STATE_BUSY;\r\n  \r\n  TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);\r\n  \r\n  /* Enable Trigger Interrupt */\r\n  __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);\r\n  \r\n  /* Disable Trigger DMA request */\r\n  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);\r\n  \r\n  htim->State = HAL_TIM_STATE_READY;\r\n     \r\n  __HAL_UNLOCK(htim);  \r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Read the captured value from Capture Compare unit\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel: TIM Channels to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval Captured value\r\n  */\r\nuint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  uint32_t tmpreg = 0;\r\n  \r\n  __HAL_LOCK(htim);\r\n  \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r\n      \r\n      /* Return the capture 1 value */\r\n      tmpreg = htim->Instance->CCR1;\r\n      \r\n      break;\r\n    }\r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n      \r\n      /* Return the capture 2 value */\r\n      tmpreg = htim->Instance->CCR2;\r\n      \r\n      break;\r\n    }\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\r\n      \r\n      /* Return the capture 3 value */\r\n      tmpreg = htim->Instance->CCR3;\r\n      \r\n      break;\r\n    }\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\r\n      \r\n      /* Return the capture 4 value */\r\n      tmpreg = htim->Instance->CCR4;\r\n      \r\n      break;\r\n    }\r\n    \r\n    default:\r\n    break;  \r\n  }\r\n     \r\n  __HAL_UNLOCK(htim);  \r\n  return tmpreg;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions\r\n *  @brief    TIM Callbacks functions \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                        ##### TIM Callbacks functions #####\r\n  ==============================================================================  \r\n [..]  \r\n   This section provides TIM callback functions:\r\n   (+) Timer Period elapsed callback\r\n   (+) Timer Output Compare callback\r\n   (+) Timer Input capture callback\r\n   (+) Timer Trigger callback\r\n   (+) Timer Error callback\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Period elapsed callback in non blocking mode \r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file\r\n   */\r\n  \r\n}\r\n/**\r\n  * @brief  Output Compare callback in non blocking mode \r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file\r\n   */\r\n}\r\n/**\r\n  * @brief  Input Capture callback in non blocking mode \r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the __HAL_TIM_IC_CaptureCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  PWM Pulse finished callback in non blocking mode \r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Hall Trigger detection callback in non blocking mode \r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_TIM_TriggerCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Timer error callback in non blocking mode \r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_TIM_ErrorCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions \r\n *  @brief   Peripheral State functions \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                        ##### Peripheral State functions #####\r\n  ==============================================================================  \r\n  [..]\r\n    This subsection permits to get in run-time the status of the peripheral \r\n    and the data flow.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Return the TIM Base state\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL state\r\n  */\r\nHAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)\r\n{\r\n  return htim->State;\r\n}\r\n\r\n/**\r\n  * @brief  Return the TIM OC state\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL state\r\n  */\r\nHAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)\r\n{\r\n  return htim->State;\r\n}\r\n\r\n/**\r\n  * @brief  Return the TIM PWM state\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL state\r\n  */\r\nHAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)\r\n{\r\n  return htim->State;\r\n}\r\n\r\n/**\r\n  * @brief  Return the TIM Input Capture state\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL state\r\n  */\r\nHAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)\r\n{\r\n  return htim->State;\r\n}\r\n\r\n/**\r\n  * @brief  Return the TIM One Pulse Mode state\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL state\r\n  */\r\nHAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)\r\n{\r\n  return htim->State;\r\n}\r\n\r\n/**\r\n  * @brief  Return the TIM Encoder Mode state\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL state\r\n  */\r\nHAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)\r\n{\r\n  return htim->State;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @brief  TIM DMA error callback \r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nvoid HAL_TIM_DMAError(DMA_HandleTypeDef *hdma)\r\n{\r\n  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  \r\n  htim->State= HAL_TIM_STATE_READY;\r\n   \r\n  HAL_TIM_ErrorCallback(htim);\r\n}\r\n\r\n/**\r\n  * @brief  TIM DMA Delay Pulse complete callback. \r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nvoid HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  \r\n  htim->State= HAL_TIM_STATE_READY; \r\n  \r\n  if (hdma == htim->hdma[TIM_DMA_ID_CC1])\r\n  {\r\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r\n  }\r\n  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\r\n  {\r\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r\n  }\r\n  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\r\n  {\r\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r\n  }\r\n  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\r\n  {\r\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r\n  }\r\n\r\n  HAL_TIM_PWM_PulseFinishedCallback(htim);\r\n\r\n  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r\n}\r\n/**\r\n  * @brief  TIM DMA Capture complete callback. \r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nvoid HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n    \r\n   htim->State= HAL_TIM_STATE_READY; \r\n    \r\n  if (hdma == htim->hdma[TIM_DMA_ID_CC1])\r\n  {\r\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\r\n  }\r\n  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\r\n  {\r\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\r\n  }\r\n  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\r\n  {\r\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\r\n  }\r\n  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\r\n  {\r\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\r\n  }\r\n  \r\n  HAL_TIM_IC_CaptureCallback(htim); \r\n  \r\n  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\r\n\r\n}\r\n\r\n/**\r\n  * @brief  TIM DMA Period Elapse complete callback. \r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  \r\n  htim->State= HAL_TIM_STATE_READY;\r\n  \r\n  HAL_TIM_PeriodElapsedCallback(htim);\r\n}\r\n\r\n/**\r\n  * @brief  TIM DMA Trigger callback. \r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nstatic void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;  \r\n  \r\n  htim->State= HAL_TIM_STATE_READY; \r\n  \r\n  HAL_TIM_TriggerCallback(htim);\r\n}\r\n\r\n/**\r\n  * @brief  Time Base configuration\r\n  * @param  TIMx: TIM peripheral\r\n  * @param  Structure: pointer on TIM Time Base required parameters  \r\n  * @retval None\r\n  */\r\nvoid TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)\r\n{\r\n  uint32_t tmpcr1 = 0;\r\n  tmpcr1 = TIMx->CR1;\r\n  \r\n  /* Set TIM Time Base Unit parameters ---------------------------------------*/\r\n  if(IS_TIM_CC3_INSTANCE(TIMx) != RESET)   \r\n  {\r\n    /* Select the Counter Mode */\r\n    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);\r\n    tmpcr1 |= Structure->CounterMode;\r\n  }\r\n \r\n  if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)  \r\n  {\r\n    /* Set the clock division */\r\n    tmpcr1 &= ~TIM_CR1_CKD;\r\n    tmpcr1 |= (uint32_t)Structure->ClockDivision;\r\n  }\r\n\r\n  TIMx->CR1 = tmpcr1;\r\n\r\n  /* Set the Auto-reload value */\r\n  TIMx->ARR = (uint32_t)Structure->Period ;\r\n \r\n  /* Set the Prescaler value */\r\n  TIMx->PSC = (uint32_t)Structure->Prescaler;\r\n    \r\n  if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)  \r\n  {\r\n    /* Set the Repetition Counter value */\r\n    TIMx->RCR = Structure->RepetitionCounter;\r\n  }\r\n\r\n  /* Generate an update event to reload the Prescaler \r\n     and the repetition counter(only for TIM1 and TIM8) value immediately */\r\n  TIMx->EGR = TIM_EGR_UG;\r\n}\r\n\r\n/**\r\n  * @brief  Time Output Compare 1 configuration\r\n  * @param  TIMx to select the TIM peripheral\r\n  * @param  OC_Config: The output configuration structure\r\n  * @retval None\r\n  */\r\nvoid TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r\n{\r\n  uint32_t tmpccmrx = 0;\r\n  uint32_t tmpccer = 0;\r\n  uint32_t tmpcr2 = 0;  \r\n\r\n  /* Disable the Channel 1: Reset the CC1E Bit */\r\n  TIMx->CCER &= ~TIM_CCER_CC1E;\r\n  \r\n  /* Get the TIMx CCER register value */\r\n  tmpccer = TIMx->CCER;\r\n  /* Get the TIMx CR2 register value */\r\n  tmpcr2 = TIMx->CR2;\r\n  \r\n  /* Get the TIMx CCMR1 register value */\r\n  tmpccmrx = TIMx->CCMR1;\r\n    \r\n  /* Reset the Output Compare Mode Bits */\r\n  tmpccmrx &= ~TIM_CCMR1_OC1M;\r\n  tmpccmrx &= ~TIM_CCMR1_CC1S;\r\n  /* Select the Output Compare Mode */\r\n  tmpccmrx |= OC_Config->OCMode;\r\n  \r\n  /* Reset the Output Polarity level */\r\n  tmpccer &= ~TIM_CCER_CC1P;\r\n  /* Set the Output Compare Polarity */\r\n  tmpccer |= OC_Config->OCPolarity;\r\n\r\n    \r\n  if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)\r\n  {   \r\n    /* Reset the Output N Polarity level */\r\n    tmpccer &= ~TIM_CCER_CC1NP;\r\n    /* Set the Output N Polarity */\r\n    tmpccer |= OC_Config->OCNPolarity;\r\n    /* Reset the Output N State */\r\n    tmpccer &= ~TIM_CCER_CC1NE;\r\n    \r\n    /* Reset the Output Compare and Output Compare N IDLE State */\r\n    tmpcr2 &= ~TIM_CR2_OIS1;\r\n    tmpcr2 &= ~TIM_CR2_OIS1N;\r\n    /* Set the Output Idle state */\r\n    tmpcr2 |= OC_Config->OCIdleState;\r\n    /* Set the Output N Idle state */\r\n    tmpcr2 |= OC_Config->OCNIdleState;\r\n  }\r\n  /* Write to TIMx CR2 */\r\n  TIMx->CR2 = tmpcr2;\r\n  \r\n  /* Write to TIMx CCMR1 */\r\n  TIMx->CCMR1 = tmpccmrx;\r\n  \r\n  /* Set the Capture Compare Register value */\r\n  TIMx->CCR1 = OC_Config->Pulse;\r\n  \r\n  /* Write to TIMx CCER */\r\n  TIMx->CCER = tmpccer;  \r\n} \r\n\r\n/**\r\n  * @brief  Time Output Compare 2 configuration\r\n  * @param  TIMx to select the TIM peripheral\r\n  * @param  OC_Config: The output configuration structure\r\n  * @retval None\r\n  */\r\nvoid TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r\n{\r\n  uint32_t tmpccmrx = 0;\r\n  uint32_t tmpccer = 0;\r\n  uint32_t tmpcr2 = 0;\r\n   \r\n  /* Disable the Channel 2: Reset the CC2E Bit */\r\n  TIMx->CCER &= ~TIM_CCER_CC2E;\r\n  \r\n  /* Get the TIMx CCER register value */  \r\n  tmpccer = TIMx->CCER;\r\n  /* Get the TIMx CR2 register value */\r\n  tmpcr2 = TIMx->CR2;\r\n  \r\n  /* Get the TIMx CCMR1 register value */\r\n  tmpccmrx = TIMx->CCMR1;\r\n    \r\n  /* Reset the Output Compare mode and Capture/Compare selection Bits */\r\n  tmpccmrx &= ~TIM_CCMR1_OC2M;\r\n  tmpccmrx &= ~TIM_CCMR1_CC2S;\r\n  \r\n  /* Select the Output Compare Mode */\r\n  tmpccmrx |= (OC_Config->OCMode << 8);\r\n  \r\n  /* Reset the Output Polarity level */\r\n  tmpccer &= ~TIM_CCER_CC2P;\r\n  /* Set the Output Compare Polarity */\r\n  tmpccer |= (OC_Config->OCPolarity << 4);\r\n    \r\n  if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)\r\n  {\r\n    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));\r\n    \r\n    /* Reset the Output N Polarity level */\r\n    tmpccer &= ~TIM_CCER_CC2NP;\r\n    /* Set the Output N Polarity */\r\n    tmpccer |= (OC_Config->OCNPolarity << 4);\r\n    /* Reset the Output N State */\r\n    tmpccer &= ~TIM_CCER_CC2NE;\r\n    \r\n    /* Reset the Output Compare and Output Compare N IDLE State */\r\n    tmpcr2 &= ~TIM_CR2_OIS2;\r\n    tmpcr2 &= ~TIM_CR2_OIS2N;\r\n    /* Set the Output Idle state */\r\n    tmpcr2 |= (OC_Config->OCIdleState << 2);\r\n    /* Set the Output N Idle state */\r\n    tmpcr2 |= (OC_Config->OCNIdleState << 2);\r\n  }\r\n  /* Write to TIMx CR2 */\r\n  TIMx->CR2 = tmpcr2;\r\n  \r\n  /* Write to TIMx CCMR1 */\r\n  TIMx->CCMR1 = tmpccmrx;\r\n  \r\n  /* Set the Capture Compare Register value */\r\n  TIMx->CCR2 = OC_Config->Pulse;\r\n  \r\n  /* Write to TIMx CCER */\r\n  TIMx->CCER = tmpccer;\r\n}\r\n\r\n/**\r\n  * @brief  Time Output Compare 3 configuration\r\n  * @param  TIMx to select the TIM peripheral\r\n  * @param  OC_Config: The output configuration structure\r\n  * @retval None\r\n  */\r\nvoid TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r\n{\r\n  uint32_t tmpccmrx = 0;\r\n  uint32_t tmpccer = 0;\r\n  uint32_t tmpcr2 = 0;   \r\n\r\n  /* Disable the Channel 3: Reset the CC2E Bit */\r\n  TIMx->CCER &= ~TIM_CCER_CC3E;\r\n  \r\n  /* Get the TIMx CCER register value */\r\n  tmpccer = TIMx->CCER;\r\n  /* Get the TIMx CR2 register value */\r\n  tmpcr2 = TIMx->CR2;\r\n  \r\n  /* Get the TIMx CCMR2 register value */\r\n  tmpccmrx = TIMx->CCMR2;\r\n    \r\n  /* Reset the Output Compare mode and Capture/Compare selection Bits */\r\n  tmpccmrx &= ~TIM_CCMR2_OC3M;\r\n  tmpccmrx &= ~TIM_CCMR2_CC3S;  \r\n  /* Select the Output Compare Mode */\r\n  tmpccmrx |= OC_Config->OCMode;\r\n  \r\n  /* Reset the Output Polarity level */\r\n  tmpccer &= ~TIM_CCER_CC3P;\r\n  /* Set the Output Compare Polarity */\r\n  tmpccer |= (OC_Config->OCPolarity << 8);\r\n    \r\n  if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)\r\n  {\r\n    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));\r\n    \r\n    /* Reset the Output N Polarity level */\r\n    tmpccer &= ~TIM_CCER_CC3NP;\r\n    /* Set the Output N Polarity */\r\n    tmpccer |= (OC_Config->OCNPolarity << 8);\r\n    /* Reset the Output N State */\r\n    tmpccer &= ~TIM_CCER_CC3NE;\r\n    \r\n    /* Reset the Output Compare and Output Compare N IDLE State */\r\n    tmpcr2 &= ~TIM_CR2_OIS3;\r\n    tmpcr2 &= ~TIM_CR2_OIS3N;\r\n    /* Set the Output Idle state */\r\n    tmpcr2 |= (OC_Config->OCIdleState << 4);\r\n    /* Set the Output N Idle state */\r\n    tmpcr2 |= (OC_Config->OCNIdleState << 4);\r\n  }\r\n  /* Write to TIMx CR2 */\r\n  TIMx->CR2 = tmpcr2;\r\n  \r\n  /* Write to TIMx CCMR2 */\r\n  TIMx->CCMR2 = tmpccmrx;\r\n  \r\n  /* Set the Capture Compare Register value */\r\n  TIMx->CCR3 = OC_Config->Pulse;\r\n  \r\n  /* Write to TIMx CCER */\r\n  TIMx->CCER = tmpccer;\r\n}\r\n\r\n/**\r\n  * @brief  Time Output Compare 4 configuration\r\n  * @param  TIMx to select the TIM peripheral\r\n  * @param  OC_Config: The output configuration structure\r\n  * @retval None\r\n  */\r\nvoid TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r\n{\r\n  uint32_t tmpccmrx = 0;\r\n  uint32_t tmpccer = 0;\r\n  uint32_t tmpcr2 = 0;\r\n\r\n  /* Disable the Channel 4: Reset the CC4E Bit */\r\n  TIMx->CCER &= ~TIM_CCER_CC4E;\r\n  \r\n  /* Get the TIMx CCER register value */\r\n  tmpccer = TIMx->CCER;\r\n  /* Get the TIMx CR2 register value */\r\n  tmpcr2 = TIMx->CR2;\r\n  \r\n  /* Get the TIMx CCMR2 register value */\r\n  tmpccmrx = TIMx->CCMR2;\r\n    \r\n  /* Reset the Output Compare mode and Capture/Compare selection Bits */\r\n  tmpccmrx &= ~TIM_CCMR2_OC4M;\r\n  tmpccmrx &= ~TIM_CCMR2_CC4S;\r\n  \r\n  /* Select the Output Compare Mode */\r\n  tmpccmrx |= (OC_Config->OCMode << 8);\r\n  \r\n  /* Reset the Output Polarity level */\r\n  tmpccer &= ~TIM_CCER_CC4P;\r\n  /* Set the Output Compare Polarity */\r\n  tmpccer |= (OC_Config->OCPolarity << 12);\r\n   \r\n  /*if((TIMx == TIM1) || (TIMx == TIM8))*/\r\n  if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)\r\n  {\r\n    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));\r\n    /* Reset the Output Compare IDLE State */\r\n    tmpcr2 &= ~TIM_CR2_OIS4;\r\n    /* Set the Output Idle state */\r\n    tmpcr2 |= (OC_Config->OCIdleState << 6);\r\n  }\r\n  /* Write to TIMx CR2 */\r\n  TIMx->CR2 = tmpcr2;\r\n  \r\n  /* Write to TIMx CCMR2 */  \r\n  TIMx->CCMR2 = tmpccmrx;\r\n    \r\n  /* Set the Capture Compare Register value */\r\n  TIMx->CCR4 = OC_Config->Pulse;\r\n  \r\n  /* Write to TIMx CCER */\r\n  TIMx->CCER = tmpccer;\r\n}\r\n\r\n/**\r\n  * @brief  Time Output Compare 4 configuration\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  sSlaveConfig: The slave configuration structure\r\n  * @retval None\r\n  */\r\nstatic void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,\r\n                              TIM_SlaveConfigTypeDef * sSlaveConfig)\r\n{\r\n  uint32_t tmpsmcr = 0;\r\n  uint32_t tmpccmr1 = 0;\r\n  uint32_t tmpccer = 0;\r\n\r\n /* Get the TIMx SMCR register value */\r\n  tmpsmcr = htim->Instance->SMCR;\r\n\r\n  /* Reset the Trigger Selection Bits */\r\n  tmpsmcr &= ~TIM_SMCR_TS;\r\n  /* Set the Input Trigger source */\r\n  tmpsmcr |= sSlaveConfig->InputTrigger;\r\n\r\n  /* Reset the slave mode Bits */\r\n  tmpsmcr &= ~TIM_SMCR_SMS;\r\n  /* Set the slave mode */\r\n  tmpsmcr |= sSlaveConfig->SlaveMode;\r\n\r\n  /* Write to TIMx SMCR */\r\n  htim->Instance->SMCR = tmpsmcr;\r\n \r\n  /* Configure the trigger prescaler, filter, and polarity */\r\n  switch (sSlaveConfig->InputTrigger)\r\n  {\r\n  case TIM_TS_ETRF:\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));\r\n      assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));\r\n      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r\n      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r\n      /* Configure the ETR Trigger source */\r\n      TIM_ETR_SetConfig(htim->Instance, \r\n                        sSlaveConfig->TriggerPrescaler, \r\n                        sSlaveConfig->TriggerPolarity, \r\n                        sSlaveConfig->TriggerFilter);\r\n    }\r\n    break;\r\n    \r\n  case TIM_TS_TI1F_ED:\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r\n      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r\n      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r\n  \r\n      /* Disable the Channel 1: Reset the CC1E Bit */\r\n      tmpccer = htim->Instance->CCER;\r\n      htim->Instance->CCER &= ~TIM_CCER_CC1E;\r\n      tmpccmr1 = htim->Instance->CCMR1;    \r\n      \r\n      /* Set the filter */\r\n      tmpccmr1 &= ~TIM_CCMR1_IC1F;\r\n      tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);\r\n      \r\n      /* Write to TIMx CCMR1 and CCER registers */\r\n      htim->Instance->CCMR1 = tmpccmr1;\r\n      htim->Instance->CCER = tmpccer;                               \r\n                               \r\n    }\r\n    break;\r\n    \r\n  case TIM_TS_TI1FP1:\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\r\n      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r\n      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r\n\r\n      /* Configure TI1 Filter and Polarity */\r\n      TIM_TI1_ConfigInputStage(htim->Instance,\r\n                               sSlaveConfig->TriggerPolarity,\r\n                               sSlaveConfig->TriggerFilter);\r\n    }\r\n    break;\r\n    \r\n  case TIM_TS_TI2FP2:\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\r\n      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\r\n  \r\n      /* Configure TI2 Filter and Polarity */\r\n      TIM_TI2_ConfigInputStage(htim->Instance,\r\n                                sSlaveConfig->TriggerPolarity,\r\n                                sSlaveConfig->TriggerFilter);\r\n    }\r\n    break;\r\n    \r\n  case TIM_TS_ITR0:\r\n    {\r\n      /* Check the parameter */\r\n      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n    }\r\n    break;\r\n    \r\n  case TIM_TS_ITR1:\r\n    {\r\n      /* Check the parameter */\r\n      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n    }\r\n    break;\r\n    \r\n  case TIM_TS_ITR2:\r\n    {\r\n      /* Check the parameter */\r\n      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n    }\r\n    break;\r\n    \r\n  case TIM_TS_ITR3:\r\n    {\r\n      /* Check the parameter */\r\n      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\r\n    }\r\n    break;\r\n       \r\n  default:\r\n    break;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Configure the TI1 as Input.\r\n  * @param  TIMx to select the TIM peripheral.\r\n  * @param  TIM_ICPolarity : The Input Polarity.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_ICPolarity_Rising\r\n  *            @arg TIM_ICPolarity_Falling\r\n  *            @arg TIM_ICPolarity_BothEdge  \r\n  * @param  TIM_ICSelection: specifies the input to be used.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.\r\n  *            @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.\r\n  *            @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.\r\n  * @param  TIM_ICFilter: Specifies the Input Capture Filter.\r\n  *          This parameter must be a value between 0x00 and 0x0F.\r\n  * @retval None  \r\n  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 \r\n  *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be \r\n  *        protected against un-initialized filter and polarity values.  \r\n  */\r\nvoid TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r\n                       uint32_t TIM_ICFilter)\r\n{\r\n  uint32_t tmpccmr1 = 0;\r\n  uint32_t tmpccer = 0;\r\n\r\n  /* Disable the Channel 1: Reset the CC1E Bit */\r\n  TIMx->CCER &= ~TIM_CCER_CC1E;\r\n  tmpccmr1 = TIMx->CCMR1;\r\n  tmpccer = TIMx->CCER;\r\n\r\n  /* Select the Input */\r\n  if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)\r\n  {\r\n    tmpccmr1 &= ~TIM_CCMR1_CC1S;\r\n    tmpccmr1 |= TIM_ICSelection;\r\n  } \r\n  else\r\n  {\r\n    tmpccmr1 |= TIM_CCMR1_CC1S_0;\r\n  }\r\n  \r\n  /* Set the filter */\r\n  tmpccmr1 &= ~TIM_CCMR1_IC1F;\r\n  tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);\r\n\r\n  /* Select the Polarity and set the CC1E Bit */\r\n  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);\r\n  tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));\r\n\r\n  /* Write to TIMx CCMR1 and CCER registers */\r\n  TIMx->CCMR1 = tmpccmr1;\r\n  TIMx->CCER = tmpccer;\r\n}\r\n\r\n/**\r\n  * @brief  Configure the Polarity and Filter for TI1.\r\n  * @param  TIMx to select the TIM peripheral.\r\n  * @param  TIM_ICPolarity : The Input Polarity.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_ICPolarity_Rising\r\n  *            @arg TIM_ICPolarity_Falling\r\n  *            @arg TIM_ICPolarity_BothEdge\r\n  * @param  TIM_ICFilter: Specifies the Input Capture Filter.\r\n  *          This parameter must be a value between 0x00 and 0x0F.\r\n  * @retval None\r\n  */\r\nstatic void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)\r\n{\r\n  uint32_t tmpccmr1 = 0;\r\n  uint32_t tmpccer = 0;\r\n  \r\n  /* Disable the Channel 1: Reset the CC1E Bit */\r\n  tmpccer = TIMx->CCER;\r\n  TIMx->CCER &= ~TIM_CCER_CC1E;\r\n  tmpccmr1 = TIMx->CCMR1;    \r\n  \r\n  /* Set the filter */\r\n  tmpccmr1 &= ~TIM_CCMR1_IC1F;\r\n  tmpccmr1 |= (TIM_ICFilter << 4);\r\n  \r\n  /* Select the Polarity and set the CC1E Bit */\r\n  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);\r\n  tmpccer |= TIM_ICPolarity;\r\n  \r\n  /* Write to TIMx CCMR1 and CCER registers */\r\n  TIMx->CCMR1 = tmpccmr1;\r\n  TIMx->CCER = tmpccer;\r\n}\r\n\r\n/**\r\n  * @brief  Configure the TI2 as Input.\r\n  * @param  TIMx to select the TIM peripheral\r\n  * @param  TIM_ICPolarity : The Input Polarity.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_ICPolarity_Rising\r\n  *            @arg TIM_ICPolarity_Falling\r\n  *            @arg TIM_ICPolarity_BothEdge   \r\n  * @param  TIM_ICSelection: specifies the input to be used.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.\r\n  *            @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.\r\n  *            @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.\r\n  * @param  TIM_ICFilter: Specifies the Input Capture Filter.\r\n  *          This parameter must be a value between 0x00 and 0x0F.\r\n  * @retval None\r\n  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 \r\n  *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be \r\n  *        protected against un-initialized filter and polarity values.  \r\n  */\r\nstatic void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r\n                       uint32_t TIM_ICFilter)\r\n{\r\n  uint32_t tmpccmr1 = 0;\r\n  uint32_t tmpccer = 0;\r\n\r\n  /* Disable the Channel 2: Reset the CC2E Bit */\r\n  TIMx->CCER &= ~TIM_CCER_CC2E;\r\n  tmpccmr1 = TIMx->CCMR1;\r\n  tmpccer = TIMx->CCER;\r\n\r\n  /* Select the Input */\r\n  tmpccmr1 &= ~TIM_CCMR1_CC2S;\r\n  tmpccmr1 |= (TIM_ICSelection << 8);\r\n\r\n  /* Set the filter */\r\n  tmpccmr1 &= ~TIM_CCMR1_IC2F;\r\n  tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);\r\n\r\n  /* Select the Polarity and set the CC2E Bit */\r\n  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);\r\n  tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));\r\n\r\n  /* Write to TIMx CCMR1 and CCER registers */\r\n  TIMx->CCMR1 = tmpccmr1 ;\r\n  TIMx->CCER = tmpccer;\r\n}\r\n\r\n/**\r\n  * @brief  Configure the Polarity and Filter for TI2.\r\n  * @param  TIMx to select the TIM peripheral.\r\n  * @param  TIM_ICPolarity : The Input Polarity.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_ICPolarity_Rising\r\n  *            @arg TIM_ICPolarity_Falling\r\n  *            @arg TIM_ICPolarity_BothEdge\r\n  * @param  TIM_ICFilter: Specifies the Input Capture Filter.\r\n  *          This parameter must be a value between 0x00 and 0x0F.\r\n  * @retval None\r\n  */\r\nstatic void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)\r\n{\r\nuint32_t tmpccmr1 = 0;\r\n  uint32_t tmpccer = 0;\r\n  \r\n  /* Disable the Channel 2: Reset the CC2E Bit */\r\n  TIMx->CCER &= ~TIM_CCER_CC2E;\r\n  tmpccmr1 = TIMx->CCMR1;\r\n  tmpccer = TIMx->CCER;\r\n  \r\n  /* Set the filter */\r\n  tmpccmr1 &= ~TIM_CCMR1_IC2F;\r\n  tmpccmr1 |= (TIM_ICFilter << 12);\r\n\r\n  /* Select the Polarity and set the CC2E Bit */\r\n  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);\r\n  tmpccer |= (TIM_ICPolarity << 4);\r\n\r\n  /* Write to TIMx CCMR1 and CCER registers */\r\n  TIMx->CCMR1 = tmpccmr1 ;\r\n  TIMx->CCER = tmpccer;\r\n}\r\n\r\n/**\r\n  * @brief  Configure the TI3 as Input.\r\n  * @param  TIMx to select the TIM peripheral\r\n  * @param  TIM_ICPolarity : The Input Polarity.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_ICPolarity_Rising\r\n  *            @arg TIM_ICPolarity_Falling\r\n  *            @arg TIM_ICPolarity_BothEdge         \r\n  * @param  TIM_ICSelection: specifies the input to be used.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.\r\n  *            @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.\r\n  *            @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.\r\n  * @param  TIM_ICFilter: Specifies the Input Capture Filter.\r\n  *          This parameter must be a value between 0x00 and 0x0F.\r\n  * @retval None\r\n  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 \r\n  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be \r\n  *        protected against un-initialized filter and polarity values.  \r\n  */\r\nstatic void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r\n                       uint32_t TIM_ICFilter)\r\n{\r\n  uint32_t tmpccmr2 = 0;\r\n  uint32_t tmpccer = 0;\r\n\r\n  /* Disable the Channel 3: Reset the CC3E Bit */\r\n  TIMx->CCER &= ~TIM_CCER_CC3E;\r\n  tmpccmr2 = TIMx->CCMR2;\r\n  tmpccer = TIMx->CCER;\r\n\r\n  /* Select the Input */\r\n  tmpccmr2 &= ~TIM_CCMR2_CC3S;\r\n  tmpccmr2 |= TIM_ICSelection;\r\n\r\n  /* Set the filter */\r\n  tmpccmr2 &= ~TIM_CCMR2_IC3F;\r\n  tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);\r\n\r\n  /* Select the Polarity and set the CC3E Bit */\r\n  tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);\r\n  tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));\r\n\r\n  /* Write to TIMx CCMR2 and CCER registers */\r\n  TIMx->CCMR2 = tmpccmr2;\r\n  TIMx->CCER = tmpccer;\r\n}\r\n\r\n/**\r\n  * @brief  Configure the TI4 as Input.\r\n  * @param  TIMx to select the TIM peripheral\r\n  * @param  TIM_ICPolarity : The Input Polarity.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_ICPolarity_Rising\r\n  *            @arg TIM_ICPolarity_Falling\r\n  *            @arg TIM_ICPolarity_BothEdge     \r\n  * @param  TIM_ICSelection: specifies the input to be used.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.\r\n  *            @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.\r\n  *            @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.\r\n  * @param  TIM_ICFilter: Specifies the Input Capture Filter.\r\n  *          This parameter must be a value between 0x00 and 0x0F.\r\n  * @retval None\r\n  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 \r\n  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be \r\n  *        protected against un-initialized filter and polarity values.  \r\n  */\r\nstatic void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\r\n                       uint32_t TIM_ICFilter)\r\n{\r\n  uint32_t tmpccmr2 = 0;\r\n  uint32_t tmpccer = 0;\r\n\r\n  /* Disable the Channel 4: Reset the CC4E Bit */\r\n  TIMx->CCER &= ~TIM_CCER_CC4E;\r\n  tmpccmr2 = TIMx->CCMR2;\r\n  tmpccer = TIMx->CCER;\r\n\r\n  /* Select the Input */\r\n  tmpccmr2 &= ~TIM_CCMR2_CC4S;\r\n  tmpccmr2 |= (TIM_ICSelection << 8);\r\n\r\n  /* Set the filter */\r\n  tmpccmr2 &= ~TIM_CCMR2_IC4F;\r\n  tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);\r\n\r\n  /* Select the Polarity and set the CC4E Bit */\r\n  tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);\r\n  tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));\r\n\r\n  /* Write to TIMx CCMR2 and CCER registers */\r\n  TIMx->CCMR2 = tmpccmr2;\r\n  TIMx->CCER = tmpccer ;\r\n}\r\n\r\n/**\r\n  * @brief  Selects the Input Trigger source\r\n  * @param  TIMx to select the TIM peripheral\r\n  * @param  TIM_ITRx: The Input Trigger source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_TS_ITR0: Internal Trigger 0\r\n  *            @arg TIM_TS_ITR1: Internal Trigger 1\r\n  *            @arg TIM_TS_ITR2: Internal Trigger 2\r\n  *            @arg TIM_TS_ITR3: Internal Trigger 3\r\n  *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector\r\n  *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1\r\n  *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2\r\n  *            @arg TIM_TS_ETRF: External Trigger input\r\n  * @retval None\r\n  */\r\nstatic void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx)\r\n{\r\n  uint32_t tmpsmcr = 0;\r\n  \r\n   /* Get the TIMx SMCR register value */\r\n   tmpsmcr = TIMx->SMCR;\r\n   /* Reset the TS Bits */\r\n   tmpsmcr &= ~TIM_SMCR_TS;\r\n   /* Set the Input Trigger source and the slave mode*/\r\n   tmpsmcr |= TIM_ITRx | TIM_SLAVEMODE_EXTERNAL1;\r\n   /* Write to TIMx SMCR */\r\n   TIMx->SMCR = tmpsmcr;\r\n}\r\n\r\n/**\r\n  * @brief  Configures the TIMx External Trigger (ETR).\r\n  * @param  TIMx to select the TIM peripheral\r\n  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.\r\n  *            @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r\n  *            @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r\n  *            @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r\n  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r\n  *            @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r\n  * @param  ExtTRGFilter: External Trigger Filter.\r\n  *          This parameter must be a value between 0x00 and 0x0F\r\n  * @retval None\r\n  */\r\nvoid TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,\r\n                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)\r\n{\r\n  uint32_t tmpsmcr = 0;\r\n\r\n  tmpsmcr = TIMx->SMCR;\r\n\r\n  /* Reset the ETR Bits */\r\n  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);\r\n\r\n  /* Set the Prescaler, the Filter value and the Polarity */\r\n  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));\r\n\r\n  /* Write to TIMx SMCR */\r\n  TIMx->SMCR = tmpsmcr;\r\n} \r\n\r\n/**\r\n  * @brief  Enables or disables the TIM Capture Compare Channel x.\r\n  * @param  TIMx to select the TIM peripheral\r\n  * @param  Channel: specifies the TIM Channel\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_Channel_1: TIM Channel 1\r\n  *            @arg TIM_Channel_2: TIM Channel 2\r\n  *            @arg TIM_Channel_3: TIM Channel 3\r\n  *            @arg TIM_Channel_4: TIM Channel 4\r\n  * @param  ChannelState: specifies the TIM Channel CCxE bit new state.\r\n  *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable. \r\n  * @retval None\r\n  */\r\nvoid TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)\r\n{\r\n  uint32_t tmp = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CC1_INSTANCE(TIMx)); \r\n  assert_param(IS_TIM_CHANNELS(Channel));\r\n\r\n  tmp = TIM_CCER_CC1E << Channel;\r\n\r\n  /* Reset the CCxE Bit */\r\n  TIMx->CCER &= ~tmp;\r\n\r\n  /* Set or reset the CCxE Bit */ \r\n  TIMx->CCER |= (uint32_t)(ChannelState << Channel);\r\n}\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_TIM_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_tim_ex.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   TIM HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the Timer extension peripheral:\r\n  *           + Time Hall Sensor Interface Initialization\r\n  *           + Time Hall Sensor Interface Start\r\n  *           + Time Complementary signal bread and dead time configuration  \r\n  *           + Time Master and Slave synchronization configuration\r\n  *           + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)\r\n  *           + Time OCRef clear configuration\r\n  *           + Timer remapping capabilities configuration  \r\n  @verbatim \r\n  ==============================================================================\r\n                      ##### TIMER Extended features #####\r\n  ==============================================================================\r\n  [..] \r\n    The Timer Extension features include: \r\n    (#) Complementary outputs with programmable dead-time for :\r\n        (++) Input Capture\r\n        (++) Output Compare\r\n        (++) PWM generation (Edge and Center-aligned Mode)\r\n        (++) One-pulse mode output\r\n    (#) Synchronization circuit to control the timer with external signals and to \r\n        interconnect several timers together.\r\n    (#) Break input to put the timer output signals in reset state or in a known state.\r\n    (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for \r\n        positioning purposes                \r\n   \r\n                        ##### How to use this driver #####\r\n  ==============================================================================\r\n  [..]\r\n     (#) Initialize the TIM low level resources by implementing the following functions \r\n         depending from feature used :\r\n           (++) Complementary Output Compare : HAL_TIM_OC_MspInit()\r\n           (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()\r\n           (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()\r\n           (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()\r\n           \r\n     (#) Initialize the TIM low level resources :\r\n        (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE(); \r\n        (##) TIM pins configuration\r\n            (+++) Enable the clock for the TIM GPIOs using the following function:\r\n                 __GPIOx_CLK_ENABLE();   \r\n            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();  \r\n\r\n     (#) The external Clock can be configured, if needed (the default clock is the \r\n         internal clock from the APBx), using the following function:\r\n         HAL_TIM_ConfigClockSource, the clock configuration should be done before \r\n         any start function.\r\n  \r\n    (#) Configure the TIM in the desired functioning mode using one of the \r\n        initialization function of this driver:\r\n        (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the \r\n             Timer Hall Sensor Interface and the commutation event with the corresponding \r\n             Interrupt and DMA request if needed (Note that One Timer is used to interface \r\n             with the Hall sensor Interface and another Timer should be used to use \r\n             the commutation event).\r\n\r\n    (#) Activate the TIM peripheral using one of the start functions: \r\n           (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()\r\n           (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()\r\n           (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()\r\n           (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().\r\n\r\n  \r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup TIMEx TIMEx\r\n  * @brief TIM Extended HAL module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_TIM_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n#define BDTR_BKF_SHIFT  (16)\r\n#define BDTR_BK2F_SHIFT (20)\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/** @addtogroup TIMEx_Private_Functions\r\n  * @{\r\n  */\r\nstatic void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);  \r\nstatic void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r\nstatic void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\r\n/**\r\n  * @}\r\n  */\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions\r\n *  @brief    Timer Hall Sensor functions \r\n *\r\n@verbatim    \r\n  ==============================================================================\r\n                      ##### Timer Hall Sensor functions #####\r\n  ==============================================================================\r\n  [..]  \r\n    This section provides functions allowing to:\r\n    (+) Initialize and configure TIM HAL Sensor. \r\n    (+) De-initialize TIM HAL Sensor.\r\n    (+) Start the Hall Sensor Interface.\r\n    (+) Stop the Hall Sensor Interface.\r\n    (+) Start the Hall Sensor Interface and enable interrupts.\r\n    (+) Stop the Hall Sensor Interface and disable interrupts.\r\n    (+) Start the Hall Sensor Interface and enable DMA transfers.\r\n    (+) Stop the Hall Sensor Interface and disable DMA transfers.\r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n/**\r\n  * @brief  Initializes the TIM Hall Sensor Interface and create the associated handle.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  sConfig: TIM Hall Sensor configuration structure\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)\r\n{\r\n  TIM_OC_InitTypeDef OC_Config;\r\n    \r\n  /* Check the TIM handle allocation */\r\n  if(htim == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  \r\n  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));\r\n  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\r\n  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\r\n  assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));\r\n  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));\r\n  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));\r\n\r\n  /* Set the TIM state */\r\n  htim->State= HAL_TIM_STATE_BUSY;\r\n  \r\n  /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\r\n  HAL_TIMEx_HallSensor_MspInit(htim);\r\n  \r\n  /* Configure the Time base in the Encoder Mode */\r\n  TIM_Base_SetConfig(htim->Instance, &htim->Init);\r\n  \r\n  /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the  Hall sensor */\r\n  TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);\r\n  \r\n  /* Reset the IC1PSC Bits */\r\n  htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;\r\n  /* Set the IC1PSC value */\r\n  htim->Instance->CCMR1 |= sConfig->IC1Prescaler;\r\n  \r\n  /* Enable the Hall sensor interface (XOR function of the three inputs) */\r\n  htim->Instance->CR2 |= TIM_CR2_TI1S;\r\n  \r\n  /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */\r\n  htim->Instance->SMCR &= ~TIM_SMCR_TS;\r\n  htim->Instance->SMCR |= TIM_TS_TI1F_ED;\r\n  \r\n  /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */  \r\n  htim->Instance->SMCR &= ~TIM_SMCR_SMS;\r\n  htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;\r\n  \r\n  /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/\r\n  OC_Config.OCFastMode = TIM_OCFAST_DISABLE;\r\n  OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;\r\n  OC_Config.OCMode = TIM_OCMODE_PWM2;\r\n  OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;\r\n  OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;\r\n  OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;\r\n  OC_Config.Pulse = sConfig->Commutation_Delay; \r\n    \r\n  TIM_OC2_SetConfig(htim->Instance, &OC_Config);\r\n  \r\n  /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2\r\n    register to 101 */\r\n  htim->Instance->CR2 &= ~TIM_CR2_MMS;\r\n  htim->Instance->CR2 |= TIM_TRGO_OC2REF; \r\n  \r\n  /* Initialize the TIM state*/\r\n  htim->State= HAL_TIM_STATE_READY;\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the TIM Hall Sensor interface  \r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\r\n\r\n  htim->State = HAL_TIM_STATE_BUSY;\r\n  \r\n  /* Disable the TIM Peripheral Clock */\r\n  __HAL_TIM_DISABLE(htim);\r\n    \r\n  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\r\n  HAL_TIMEx_HallSensor_MspDeInit(htim);\r\n    \r\n  /* Change TIM state */  \r\n  htim->State = HAL_TIM_STATE_RESET; \r\n\r\n  /* Release Lock */\r\n  __HAL_UNLOCK(htim);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the TIM Hall Sensor MSP.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes TIM Hall Sensor MSP.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Starts the TIM Hall Sensor Interface.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));\r\n  \r\n  /* Enable the Input Capture channels 1\r\n    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */  \r\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); \r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the TIM Hall sensor Interface.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));\r\n  \r\n  /* Disable the Input Capture channels 1, 2 and 3\r\n    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */  \r\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); \r\n\r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the TIM Hall Sensor Interface in interrupt mode.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)\r\n{ \r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));\r\n  \r\n  /* Enable the capture compare Interrupts 1 event */\r\n  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r\n  \r\n  /* Enable the Input Capture channels 1\r\n    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */  \r\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);  \r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the TIM Hall Sensor Interface in interrupt mode.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));\r\n  \r\n  /* Disable the Input Capture channels 1\r\n    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */  \r\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); \r\n  \r\n  /* Disable the capture compare Interrupts event */\r\n  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the TIM Hall Sensor Interface in DMA mode.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  pData: The destination Buffer address.\r\n  * @param  Length: The length of data to be transferred from TIM peripheral to memory.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));\r\n  \r\n   if((htim->State == HAL_TIM_STATE_BUSY))\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  else if((htim->State == HAL_TIM_STATE_READY))\r\n  {\r\n    if(((uint32_t)pData == 0 ) && (Length > 0)) \r\n    {\r\n      return HAL_ERROR;                                    \r\n    }\r\n    else\r\n    {\r\n      htim->State = HAL_TIM_STATE_BUSY;\r\n    }\r\n  }\r\n  /* Enable the Input Capture channels 1\r\n    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */  \r\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); \r\n  \r\n  /* Set the DMA Input Capture 1 Callback */\r\n  htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;     \r\n  /* Set the DMA error callback */\r\n  htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r\n  \r\n  /* Enable the DMA Stream for Capture 1*/\r\n  HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);    \r\n  \r\n  /* Enable the capture compare 1 Interrupt */\r\n  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r\n \r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the TIM Hall Sensor Interface in DMA mode.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));\r\n  \r\n  /* Disable the Input Capture channels 1\r\n    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */  \r\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); \r\n \r\n  \r\n  /* Disable the capture compare Interrupts 1 event */\r\n  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r\n \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions\r\n *  @brief    Timer Complementary Output Compare functions \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n              ##### Timer Complementary Output Compare functions #####\r\n  ==============================================================================  \r\n  [..]  \r\n    This section provides functions allowing to:\r\n    (+) Start the Complementary Output Compare/PWM.\r\n    (+) Stop the Complementary Output Compare/PWM.\r\n    (+) Start the Complementary Output Compare/PWM and enable interrupts.\r\n    (+) Stop the Complementary Output Compare/PWM and disable interrupts.\r\n    (+) Start the Complementary Output Compare/PWM and enable DMA transfers.\r\n    (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.\r\n               \r\n@endverbatim\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @brief  Starts the TIM Output Compare signal generation on the complementary\r\n  *         output.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.  \r\n  * @param  Channel: TIM Channel to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r\n  \r\n     /* Enable the Capture compare channel N */\r\n     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r\n    \r\n  /* Enable the Main Output */\r\n    __HAL_TIM_MOE_ENABLE(htim);\r\n\r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n} \r\n\r\n/**\r\n  * @brief  Stops the TIM Output Compare signal generation on the complementary\r\n  *         output.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel: TIM Channel to be disabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{ \r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r\n  \r\n    /* Disable the Capture compare channel N */\r\n  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r\n    \r\n  /* Disable the Main Output */\r\n    __HAL_TIM_MOE_DISABLE(htim);\r\n\r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n} \r\n\r\n/**\r\n  * @brief  Starts the TIM Output Compare signal generation in interrupt mode \r\n  *         on the complementary output.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel: TIM Channel to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r\n  \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {       \r\n      /* Enable the TIM Output Compare interrupt */\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Enable the TIM Output Compare interrupt */\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      /* Enable the TIM Output Compare interrupt */\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n      /* Enable the TIM Output Compare interrupt */\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break;\r\n  } \r\n  \r\n  /* Enable the TIM Break interrupt */\r\n  __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);\r\n  \r\n  /* Enable the Capture compare channel N */\r\n  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r\n\r\n  /* Enable the Main Output */\r\n __HAL_TIM_MOE_ENABLE(htim);\r\n\r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n} \r\n\r\n/**\r\n  * @brief  Stops the TIM Output Compare signal generation in interrupt mode \r\n  *         on the complementary output.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel: TIM Channel to be disabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  uint32_t tmpccer = 0; \r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r\n  \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {       \r\n      /* Disable the TIM Output Compare interrupt */\r\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Disable the TIM Output Compare interrupt */\r\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      /* Disable the TIM Output Compare interrupt */\r\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n      /* Disable the TIM Output Compare interrupt */\r\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break; \r\n  }\r\n\r\n  /* Disable the Capture compare channel N */\r\n  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r\n\r\n  /* Disable the TIM Break interrupt (only if no more channel is active) */\r\n  tmpccer = htim->Instance->CCER;\r\n  if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)\r\n  {\r\n    __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);\r\n  }\r\n\r\n  /* Disable the Main Output */\r\n  __HAL_TIM_MOE_DISABLE(htim);\r\n\r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n} \r\n\r\n/**\r\n  * @brief  Starts the TIM Output Compare signal generation in DMA mode \r\n  *         on the complementary output.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel: TIM Channel to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @param  pData: The source Buffer address.\r\n  * @param  Length: The length of data to be transferred from memory to TIM peripheral\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r\n  \r\n  if((htim->State == HAL_TIM_STATE_BUSY))\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  else if((htim->State == HAL_TIM_STATE_READY))\r\n  {\r\n    if(((uint32_t)pData == 0 ) && (Length > 0)) \r\n    {\r\n      return HAL_ERROR;                                    \r\n    }\r\n    else\r\n    {\r\n      htim->State = HAL_TIM_STATE_BUSY;\r\n    }\r\n  }    \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {      \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);\r\n      \r\n      /* Enable the TIM Output Compare DMA request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);\r\n      \r\n      /* Enable the TIM Output Compare DMA request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n{\r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);\r\n      \r\n      /* Enable the TIM Output Compare DMA request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n     /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);\r\n      \r\n      /* Enable the TIM Output Compare DMA request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break;\r\n  }\r\n\r\n  /* Enable the Capture compare channel N */\r\n  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r\n  \r\n  /* Enable the Main Output */\r\n  __HAL_TIM_MOE_ENABLE(htim);\r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim); \r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the TIM Output Compare signal generation in DMA mode \r\n  *         on the complementary output.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel: TIM Channel to be disabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r\n  \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {       \r\n      /* Disable the TIM Output Compare DMA request */\r\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Disable the TIM Output Compare DMA request */\r\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      /* Disable the TIM Output Compare DMA request */\r\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n      /* Disable the TIM Output Compare interrupt */\r\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break;\r\n  } \r\n  \r\n  /* Disable the Capture compare channel N */\r\n  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r\n  \r\n  /* Disable the Main Output */\r\n  __HAL_TIM_MOE_DISABLE(htim);\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim);\r\n  \r\n  /* Change the htim state */\r\n  htim->State = HAL_TIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions\r\n *  @brief    Timer Complementary PWM functions \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                 ##### Timer Complementary PWM functions #####\r\n  ==============================================================================  \r\n  [..]  \r\n    This section provides functions allowing to:\r\n    (+) Start the Complementary PWM.\r\n    (+) Stop the Complementary PWM.\r\n    (+) Start the Complementary PWM and enable interrupts.\r\n    (+) Stop the Complementary PWM and disable interrupts.\r\n    (+) Start the Complementary PWM and enable DMA transfers.\r\n    (+) Stop the Complementary PWM and disable DMA transfers.\r\n    (+) Start the Complementary Input Capture measurement.\r\n    (+) Stop the Complementary Input Capture.\r\n    (+) Start the Complementary Input Capture and enable interrupts.\r\n    (+) Stop the Complementary Input Capture and disable interrupts.\r\n    (+) Start the Complementary Input Capture and enable DMA transfers.\r\n    (+) Stop the Complementary Input Capture and disable DMA transfers.\r\n    (+) Start the Complementary One Pulse generation.\r\n    (+) Stop the Complementary One Pulse.\r\n    (+) Start the Complementary One Pulse and enable interrupts.\r\n    (+) Stop the Complementary One Pulse and disable interrupts.\r\n               \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Starts the PWM signal generation on the complementary output.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel: TIM Channel to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r\n  \r\n  /* Enable the complementary PWM output  */\r\n  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r\n  \r\n  /* Enable the Main Output */\r\n  __HAL_TIM_MOE_ENABLE(htim);\r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n} \r\n\r\n/**\r\n  * @brief  Stops the PWM signal generation on the complementary output.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel: TIM Channel to be disabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{ \r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r\n  \r\n  /* Disable the complementary PWM output  */\r\n  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);  \r\n  \r\n  /* Disable the Main Output */\r\n  __HAL_TIM_MOE_DISABLE(htim);\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n} \r\n\r\n/**\r\n  * @brief  Starts the PWM signal generation in interrupt mode on the \r\n  *         complementary output.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel: TIM Channel to be disabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r\n  \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {       \r\n      /* Enable the TIM Capture/Compare 1 interrupt */\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Enable the TIM Capture/Compare 2 interrupt */\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      /* Enable the TIM Capture/Compare 3 interrupt */\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n      /* Enable the TIM Capture/Compare 4 interrupt */\r\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break;\r\n  } \r\n  \r\n  /* Enable the TIM Break interrupt */\r\n  __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);\r\n  \r\n  /* Enable the complementary PWM output  */\r\n  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r\n  \r\n  /* Enable the Main Output */\r\n  __HAL_TIM_MOE_ENABLE(htim);\r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n} \r\n\r\n/**\r\n  * @brief  Stops the PWM signal generation in interrupt mode on the \r\n  *         complementary output.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel: TIM Channel to be disabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  uint32_t tmpccer = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r\n\r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {       \r\n      /* Disable the TIM Capture/Compare 1 interrupt */\r\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Disable the TIM Capture/Compare 2 interrupt */\r\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      /* Disable the TIM Capture/Compare 3 interrupt */\r\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n      /* Disable the TIM Capture/Compare 3 interrupt */\r\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break; \r\n  }\r\n  \r\n  /* Disable the complementary PWM output  */\r\n  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r\n  \r\n  /* Disable the TIM Break interrupt (only if no more channel is active) */\r\n  tmpccer = htim->Instance->CCER;\r\n  if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)\r\n  {\r\n    __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);\r\n  }\r\n  \r\n  /* Disable the Main Output */\r\n  __HAL_TIM_MOE_DISABLE(htim);\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n} \r\n\r\n/**\r\n  * @brief  Starts the TIM PWM signal generation in DMA mode on the \r\n  *         complementary output\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel: TIM Channel to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @param  pData: The source Buffer address.\r\n  * @param  Length: The length of data to be transferred from memory to TIM peripheral\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r\n  \r\n  if((htim->State == HAL_TIM_STATE_BUSY))\r\n  {\r\n     return HAL_BUSY;\r\n  }\r\n  else if((htim->State == HAL_TIM_STATE_READY))\r\n  {\r\n    if(((uint32_t)pData == 0 ) && (Length > 0)) \r\n    {\r\n      return HAL_ERROR;                                    \r\n    }\r\n    else\r\n    {\r\n      htim->State = HAL_TIM_STATE_BUSY;\r\n    }\r\n  }    \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {      \r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);\r\n      \r\n      /* Enable the TIM Capture/Compare 1 DMA request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);\r\n      \r\n      /* Enable the TIM Capture/Compare 2 DMA request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);\r\n      \r\n      /* Enable the TIM Capture/Compare 3 DMA request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n     /* Set the DMA Period elapsed callback */\r\n      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;\r\n     \r\n      /* Set the DMA error callback */\r\n      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;\r\n      \r\n      /* Enable the DMA Stream */\r\n      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);\r\n      \r\n      /* Enable the TIM Capture/Compare 4 DMA request */\r\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break;\r\n  }\r\n\r\n  /* Enable the complementary PWM output  */\r\n     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\r\n    \r\n  /* Enable the Main Output */\r\n    __HAL_TIM_MOE_ENABLE(htim);\r\n  \r\n  /* Enable the Peripheral */\r\n  __HAL_TIM_ENABLE(htim); \r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary\r\n  *         output\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Channel: TIM Channel to be disabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); \r\n  \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {       \r\n      /* Disable the TIM Capture/Compare 1 DMA request */\r\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Disable the TIM Capture/Compare 2 DMA request */\r\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      /* Disable the TIM Capture/Compare 3 DMA request */\r\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n      /* Disable the TIM Capture/Compare 4 DMA request */\r\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break;\r\n  } \r\n  \r\n  /* Disable the complementary PWM output */\r\n    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\r\n     \r\n  /* Disable the Main Output */\r\n    __HAL_TIM_MOE_DISABLE(htim);\r\n\r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim);\r\n  \r\n  /* Change the htim state */\r\n  htim->State = HAL_TIM_STATE_READY;\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions\r\n *  @brief    Timer Complementary One Pulse functions \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                ##### Timer Complementary One Pulse functions #####\r\n  ==============================================================================  \r\n  [..]  \r\n    This section provides functions allowing to:\r\n    (+) Start the Complementary One Pulse generation.\r\n    (+) Stop the Complementary One Pulse.\r\n    (+) Start the Complementary One Pulse and enable interrupts.\r\n    (+) Stop the Complementary One Pulse and disable interrupts.\r\n               \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Starts the TIM One Pulse signal generation on the complemetary \r\n  *         output.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  OutputChannel: TIM Channel to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r\n  {\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); \r\n  \r\n  /* Enable the complementary One Pulse output */\r\n  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); \r\n  \r\n  /* Enable the Main Output */\r\n  __HAL_TIM_MOE_ENABLE(htim);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Stops the TIM One Pulse signal generation on the complementary \r\n  *         output.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  OutputChannel: TIM Channel to be disabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r\n{\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); \r\n\r\n  /* Disable the complementary One Pulse output */\r\n    TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);\r\n  \r\n  /* Disable the Main Output */\r\n    __HAL_TIM_MOE_DISABLE(htim);\r\n  \r\n  /* Disable the Peripheral */\r\n  __HAL_TIM_DISABLE(htim); \r\n   \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the\r\n  *         complementary channel.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  OutputChannel: TIM Channel to be enabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); \r\n\r\n  /* Enable the TIM Capture/Compare 1 interrupt */\r\n  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\r\n  \r\n  /* Enable the TIM Capture/Compare 2 interrupt */\r\n  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\r\n  \r\n  /* Enable the complementary One Pulse output */\r\n  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); \r\n  \r\n  /* Enable the Main Output */\r\n  __HAL_TIM_MOE_ENABLE(htim);\r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n  } \r\n  \r\n/**\r\n  * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the\r\n  *         complementary channel.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  OutputChannel: TIM Channel to be disabled.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); \r\n\r\n  /* Disable the TIM Capture/Compare 1 interrupt */\r\n  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\r\n  \r\n  /* Disable the TIM Capture/Compare 2 interrupt */\r\n  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\r\n  \r\n  /* Disable the complementary One Pulse output */\r\n  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);\r\n  \r\n  /* Disable the Main Output */\r\n  __HAL_TIM_MOE_DISABLE(htim);\r\n  \r\n  /* Disable the Peripheral */\r\n   __HAL_TIM_DISABLE(htim);  \r\n  \r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions\r\n *  @brief   \tPeripheral Control functions \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                    ##### Peripheral Control functions #####\r\n  ==============================================================================  \r\n  [..]  \r\n    This section provides functions allowing to:\r\n    (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. \r\n    (+) Configure External Clock source.\r\n    (+) Configure Complementary channels, break features and dead time.\r\n    (+) Configure Master and the Slave synchronization.\r\n    (+) Configure the commutation event in case of use of the Hall sensor interface.\r\n    (+) Configure the DMA Burst Mode.\r\n      \r\n@endverbatim\r\n  * @{\r\n  */\r\n/**\r\n  * @brief  Configure the TIM commutation event sequence.\r\n  * @note  This function is mandatory to use the commutation event in order to \r\n  *        update the configuration at each commutation detection on the TRGI input of the Timer,\r\n  *        the typical use of this feature is with the use of another Timer(interface Timer) \r\n  *        configured in Hall sensor interface, this interface Timer will generate the \r\n  *        commutation at its TRGO output (connected to Timer used in this function) each time \r\n  *        the TI1 of the Interface Timer detect a commutation at its input TI1.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_TS_ITR0: Internal trigger 0 selected\r\n  *            @arg TIM_TS_ITR1: Internal trigger 1 selected\r\n  *            @arg TIM_TS_ITR2: Internal trigger 2 selected\r\n  *            @arg TIM_TS_ITR3: Internal trigger 3 selected\r\n  *            @arg TIM_TS_NONE: No trigger is needed \r\n  * @param  CommutationSource: the Commutation Event source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer\r\n  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));\r\n  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));\r\n  \r\n  __HAL_LOCK(htim);\r\n  \r\n  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||\r\n      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))\r\n  {    \r\n    /* Select the Input trigger */\r\n    htim->Instance->SMCR &= ~TIM_SMCR_TS;\r\n    htim->Instance->SMCR |= InputTrigger;\r\n  }\r\n    \r\n  /* Select the Capture Compare preload feature */\r\n  htim->Instance->CR2 |= TIM_CR2_CCPC;\r\n  /* Select the Commutation event source */\r\n  htim->Instance->CR2 &= ~TIM_CR2_CCUS;\r\n  htim->Instance->CR2 |= CommutationSource;\r\n    \r\n  __HAL_UNLOCK(htim);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Configure the TIM commutation event sequence with interrupt.\r\n  * @note  This function is mandatory to use the commutation event in order to \r\n  *        update the configuration at each commutation detection on the TRGI input of the Timer,\r\n  *        the typical use of this feature is with the use of another Timer(interface Timer) \r\n  *        configured in Hall sensor interface, this interface Timer will generate the \r\n  *        commutation at its TRGO output (connected to Timer used in this function) each time \r\n  *        the TI1 of the Interface Timer detect a commutation at its input TI1.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_TS_ITR0: Internal trigger 0 selected\r\n  *            @arg TIM_TS_ITR1: Internal trigger 1 selected\r\n  *            @arg TIM_TS_ITR2: Internal trigger 2 selected\r\n  *            @arg TIM_TS_ITR3: Internal trigger 3 selected\r\n  *            @arg TIM_TS_NONE: No trigger is needed\r\n  * @param  CommutationSource: the Commutation Event source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer\r\n  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));\r\n  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));\r\n  \r\n  __HAL_LOCK(htim);\r\n  \r\n  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||\r\n      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))\r\n  {    \r\n    /* Select the Input trigger */\r\n    htim->Instance->SMCR &= ~TIM_SMCR_TS;\r\n    htim->Instance->SMCR |= InputTrigger;\r\n  }\r\n  \r\n  /* Select the Capture Compare preload feature */\r\n  htim->Instance->CR2 |= TIM_CR2_CCPC;\r\n  /* Select the Commutation event source */\r\n  htim->Instance->CR2 &= ~TIM_CR2_CCUS;\r\n  htim->Instance->CR2 |= CommutationSource;\r\n    \r\n  /* Enable the Commutation Interrupt Request */\r\n  __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);\r\n\r\n  __HAL_UNLOCK(htim);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Configure the TIM commutation event sequence with DMA.\r\n  * @note  This function is mandatory to use the commutation event in order to \r\n  *        update the configuration at each commutation detection on the TRGI input of the Timer,\r\n  *        the typical use of this feature is with the use of another Timer(interface Timer) \r\n  *        configured in Hall sensor interface, this interface Timer will generate the \r\n  *        commutation at its TRGO output (connected to Timer used in this function) each time \r\n  *        the TI1 of the Interface Timer detect a commutation at its input TI1.\r\n  * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_TS_ITR0: Internal trigger 0 selected\r\n  *            @arg TIM_TS_ITR1: Internal trigger 1 selected\r\n  *            @arg TIM_TS_ITR2: Internal trigger 2 selected\r\n  *            @arg TIM_TS_ITR3: Internal trigger 3 selected\r\n  *            @arg TIM_TS_NONE: No trigger is needed\r\n  * @param  CommutationSource: the Commutation Event source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer\r\n  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));\r\n  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));\r\n  \r\n  __HAL_LOCK(htim);\r\n  \r\n  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||\r\n      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))\r\n  {    \r\n    /* Select the Input trigger */\r\n    htim->Instance->SMCR &= ~TIM_SMCR_TS;\r\n    htim->Instance->SMCR |= InputTrigger;\r\n  }\r\n  \r\n  /* Select the Capture Compare preload feature */\r\n  htim->Instance->CR2 |= TIM_CR2_CCPC;\r\n  /* Select the Commutation event source */\r\n  htim->Instance->CR2 &= ~TIM_CR2_CCUS;\r\n  htim->Instance->CR2 |= CommutationSource;\r\n  \r\n  /* Enable the Commutation DMA Request */\r\n  /* Set the DMA Commutation Callback */\r\n  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;     \r\n  /* Set the DMA error callback */\r\n  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError;\r\n  \r\n  /* Enable the Commutation DMA Request */\r\n  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);\r\n\r\n  __HAL_UNLOCK(htim);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the TIM Output Compare Channels according to the specified\r\n  *         parameters in the TIM_OC_InitTypeDef.\r\n  * @param  htim: TIM Output Compare handle\r\n  * @param  sConfig: TIM Output Compare configuration structure\r\n  * @param  Channel : TIM Channels to configure\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected \r\n  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected \r\n  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)\r\n{  \r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CHANNELS(Channel)); \r\n  assert_param(IS_TIM_OC_MODE(sConfig->OCMode));\r\n  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));\r\n  \r\n  /* Check input state */\r\n  __HAL_LOCK(htim); \r\n  \r\n  htim->State = HAL_TIM_STATE_BUSY;\r\n  \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); \r\n      \r\n     /* Configure the TIM Channel 1 in Output Compare */\r\n      TIM_OC1_SetConfig(htim->Instance, sConfig);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); \r\n      \r\n      /* Configure the TIM Channel 2 in Output Compare */\r\n      TIM_OC2_SetConfig(htim->Instance, sConfig);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); \r\n      \r\n      /* Configure the TIM Channel 3 in Output Compare */\r\n      TIM_OC3_SetConfig(htim->Instance, sConfig);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); \r\n      \r\n       /* Configure the TIM Channel 4 in Output Compare */\r\n       TIM_OC4_SetConfig(htim->Instance, sConfig);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_5:\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); \r\n      \r\n       /* Configure the TIM Channel 5 in Output Compare */\r\n       TIM_OC5_SetConfig(htim->Instance, sConfig);\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_6:\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); \r\n      \r\n       /* Configure the TIM Channel 6 in Output Compare */\r\n       TIM_OC6_SetConfig(htim->Instance, sConfig);\r\n    }\r\n    break;\r\n        \r\n    default:\r\n    break;    \r\n  }\r\n  \r\n  htim->State = HAL_TIM_STATE_READY;\r\n  \r\n  __HAL_UNLOCK(htim); \r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the TIM PWM  channels according to the specified\r\n  *         parameters in the TIM_OC_InitTypeDef.\r\n  * @param  htim: TIM PWM handle\r\n  * @param  sConfig: TIM PWM configuration structure\r\n  * @param  Channel : TIM Channels to be configured\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\r\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\r\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\r\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\r\n  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected \r\n  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, \r\n                                            TIM_OC_InitTypeDef* sConfig, \r\n                                            uint32_t Channel)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_CHANNELS(Channel)); \r\n  assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));\r\n  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));\r\n  assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));\r\n  \r\n  /* Check input state */\r\n  __HAL_LOCK(htim);\r\n  \r\n  htim->State = HAL_TIM_STATE_BUSY;\r\n    \r\n  switch (Channel)\r\n  {\r\n    case TIM_CHANNEL_1:\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); \r\n      \r\n      /* Configure the Channel 1 in PWM mode */\r\n      TIM_OC1_SetConfig(htim->Instance, sConfig);\r\n      \r\n      /* Set the Preload enable bit for channel1 */\r\n      htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;\r\n      \r\n      /* Configure the Output Fast mode */\r\n      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;\r\n      htim->Instance->CCMR1 |= sConfig->OCFastMode;\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_2:\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); \r\n      \r\n      /* Configure the Channel 2 in PWM mode */\r\n      TIM_OC2_SetConfig(htim->Instance, sConfig);\r\n      \r\n      /* Set the Preload enable bit for channel2 */\r\n      htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;\r\n      \r\n      /* Configure the Output Fast mode */\r\n      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;\r\n      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;\r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_3:\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); \r\n      \r\n      /* Configure the Channel 3 in PWM mode */\r\n      TIM_OC3_SetConfig(htim->Instance, sConfig);\r\n      \r\n      /* Set the Preload enable bit for channel3 */\r\n      htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;\r\n      \r\n     /* Configure the Output Fast mode */\r\n      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;\r\n      htim->Instance->CCMR2 |= sConfig->OCFastMode;  \r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_4:\r\n    {\r\n      /* Check the parameters */\r\n      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); \r\n      \r\n      /* Configure the Channel 4 in PWM mode */\r\n      TIM_OC4_SetConfig(htim->Instance, sConfig);\r\n      \r\n      /* Set the Preload enable bit for channel4 */\r\n      htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;\r\n      \r\n     /* Configure the Output Fast mode */\r\n      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;\r\n      htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;  \r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_5:\r\n    {\r\n       /* Check the parameters */\r\n      assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); \r\n      \r\n     /* Configure the Channel 5 in PWM mode */\r\n      TIM_OC5_SetConfig(htim->Instance, sConfig);\r\n      \r\n      /* Set the Preload enable bit for channel5*/\r\n      htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;\r\n      \r\n     /* Configure the Output Fast mode */\r\n      htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;\r\n      htim->Instance->CCMR3 |= sConfig->OCFastMode;  \r\n    }\r\n    break;\r\n    \r\n    case TIM_CHANNEL_6:\r\n    {\r\n       /* Check the parameters */\r\n      assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); \r\n      \r\n     /* Configure the Channel 5 in PWM mode */\r\n      TIM_OC6_SetConfig(htim->Instance, sConfig);\r\n      \r\n      /* Set the Preload enable bit for channel6 */\r\n      htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;\r\n      \r\n     /* Configure the Output Fast mode */\r\n      htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;\r\n      htim->Instance->CCMR3 |= sConfig->OCFastMode << 8;  \r\n    }\r\n    break;\r\n    \r\n    default:\r\n    break;    \r\n  }\r\n  \r\n  htim->State = HAL_TIM_STATE_READY;\r\n    \r\n  __HAL_UNLOCK(htim);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Configures the OCRef clear feature\r\n  * @param  htim: TIM handle\r\n  * @param  sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that\r\n  *         contains the OCREF clear feature and parameters for the TIM peripheral. \r\n  * @param  Channel: specifies the TIM Channel\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_Channel_1: TIM Channel 1\r\n  *            @arg TIM_Channel_2: TIM Channel 2\r\n  *            @arg TIM_Channel_3: TIM Channel 3\r\n  *            @arg TIM_Channel_4: TIM Channel 4\r\n  *            @arg TIM_Channel_5: TIM Channel 5\r\n  *            @arg TIM_Channel_6: TIM Channel 6\r\n  * @retval None\r\n  */ \r\nHAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,\r\n                                           TIM_ClearInputConfigTypeDef *sClearInputConfig,\r\n                                           uint32_t Channel)\r\n{ \r\n  uint32_t tmpsmcr = 0;\r\n\r\n  /* Check the parameters */ \r\n  assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));\r\n  assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));\r\n                                        \r\n  /* Check input state */\r\n  __HAL_LOCK(htim);\r\n  \r\n  switch (sClearInputConfig->ClearInputSource)\r\n  {\r\n    case TIM_CLEARINPUTSOURCE_NONE:\r\n    {\r\n      /* Get the TIMx SMCR register value */\r\n      tmpsmcr = htim->Instance->SMCR;\r\n      \r\n      /* Clear the OCREF clear selection bit */\r\n      tmpsmcr &= ~TIM_SMCR_OCCS;\r\n      \r\n      /* Clear the ETR Bits */\r\n      tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);\r\n      \r\n      /* Set TIMx_SMCR */\r\n      htim->Instance->SMCR = tmpsmcr;\r\n   }\r\n    break;\r\n    \r\n    case TIM_CLEARINPUTSOURCE_OCREFCLR:\r\n    {\r\n      /* Clear the OCREF clear selection bit */\r\n      htim->Instance->SMCR &= ~TIM_SMCR_OCCS;\r\n    }\r\n    break;\r\n    \r\n    case TIM_CLEARINPUTSOURCE_ETR:\r\n    {\r\n      /* Check the parameters */ \r\n      assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));\r\n      assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));\r\n      assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));\r\n      \r\n      TIM_ETR_SetConfig(htim->Instance,\r\n                        sClearInputConfig->ClearInputPrescaler,\r\n                        sClearInputConfig->ClearInputPolarity,\r\n                        sClearInputConfig->ClearInputFilter);\r\n      \r\n      /* Set the OCREF clear selection bit */\r\n      htim->Instance->SMCR |= TIM_SMCR_OCCS;\r\n    }\r\n    break;\r\n    default:  \r\n    break;\r\n  }\r\n  \r\n  switch (Channel)\r\n  { \r\n    case TIM_CHANNEL_1:\r\n      {\r\n        if(sClearInputConfig->ClearInputState != RESET)\r\n        {\r\n          /* Enable the Ocref clear feature for Channel 1 */\r\n          htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;\r\n        }\r\n        else\r\n        {\r\n          /* Disable the Ocref clear feature for Channel 1 */\r\n          htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;      \r\n        }\r\n      }    \r\n      break;\r\n    case TIM_CHANNEL_2:    \r\n      {\r\n        if(sClearInputConfig->ClearInputState != RESET)\r\n        {\r\n          /* Enable the Ocref clear feature for Channel 2 */\r\n          htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;\r\n        }\r\n        else\r\n        {\r\n          /* Disable the Ocref clear feature for Channel 2 */\r\n          htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;      \r\n        }\r\n      }    \r\n    break;\r\n    case TIM_CHANNEL_3:    \r\n      {\r\n        if(sClearInputConfig->ClearInputState != RESET)\r\n        {\r\n          /* Enable the Ocref clear feature for Channel 3 */\r\n          htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;\r\n        }\r\n        else\r\n        {\r\n          /* Disable the Ocref clear feature for Channel 3 */\r\n          htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;      \r\n        }\r\n      }    \r\n    break;\r\n    case TIM_CHANNEL_4:    \r\n      {\r\n        if(sClearInputConfig->ClearInputState != RESET)\r\n        {\r\n          /* Enable the Ocref clear feature for Channel 4 */\r\n          htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;\r\n        }\r\n        else\r\n        {\r\n          /* Disable the Ocref clear feature for Channel 4 */\r\n          htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;      \r\n        }\r\n      }    \r\n    break;\r\n    case TIM_CHANNEL_5:    \r\n      {\r\n        if(sClearInputConfig->ClearInputState != RESET)\r\n        {\r\n          /* Enable the Ocref clear feature for Channel 1 */\r\n          htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE;\r\n        }\r\n        else\r\n        {\r\n          /* Disable the Ocref clear feature for Channel 1 */\r\n          htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE;      \r\n        }\r\n      }    \r\n    break;\r\n    case TIM_CHANNEL_6:    \r\n      {\r\n        if(sClearInputConfig->ClearInputState != RESET)\r\n        {\r\n          /* Enable the Ocref clear feature for Channel 1 */\r\n          htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE;\r\n        }\r\n        else\r\n        {\r\n          /* Disable the Ocref clear feature for Channel 1 */\r\n          htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE;      \r\n        }\r\n      }    \r\n    break;\r\n    default:  \r\n    break;\r\n  } \r\n  \r\n  __HAL_UNLOCK(htim);\r\n\r\n  return HAL_OK;  \r\n}  \r\n\r\n/**\r\n  * @brief  Configures the TIM in master mode.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.   \r\n  * @param  sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that\r\n  *         contains the selected trigger output (TRGO) and the Master/Slave \r\n  *         mode. \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)\r\n{\r\n  uint32_t tmpcr2;  \r\n  uint32_t tmpsmcr;  \r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));\r\n  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));\r\n  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));\r\n  \r\n  /* Check input state */\r\n  __HAL_LOCK(htim);\r\n\r\n /* Get the TIMx CR2 register value */\r\n  tmpcr2 = htim->Instance->CR2;\r\n\r\n  /* Get the TIMx SMCR register value */\r\n  tmpsmcr = htim->Instance->SMCR;\r\n\r\n  /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */\r\n  if (IS_TIM_TRGO2_INSTANCE(htim->Instance))\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));\r\n    \r\n    /* Clear the MMS2 bits */\r\n    tmpcr2 &= ~TIM_CR2_MMS2;\r\n    /* Select the TRGO2 source*/\r\n    tmpcr2 |= sMasterConfig->MasterOutputTrigger2;\r\n  }\r\n  \r\n  /* Reset the MMS Bits */\r\n  tmpcr2 &= ~TIM_CR2_MMS;\r\n  /* Select the TRGO source */\r\n  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;\r\n\r\n  /* Reset the MSM Bit */\r\n  tmpsmcr &= ~TIM_SMCR_MSM;\r\n  /* Set master mode */\r\n  tmpsmcr |= sMasterConfig->MasterSlaveMode;\r\n  \r\n  /* Update TIMx CR2 */\r\n  htim->Instance->CR2 = tmpcr2;\r\n  \r\n  /* Update TIMx SMCR */\r\n  htim->Instance->SMCR = tmpsmcr;\r\n\r\n  __HAL_UNLOCK(htim);\r\n  \r\n  return HAL_OK;\r\n} \r\n                                                     \r\n/**\r\n  * @brief   Configures the Break feature, dead time, Lock level, OSSI/OSSR State\r\n  *         and the AOE(automatic output enable).\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that\r\n  *         contains the BDTR Register configuration  information for the TIM peripheral. \r\n  * @retval HAL status\r\n  */    \r\nHAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, \r\n                                              TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)\r\n{\r\n  uint32_t tmpbdtr = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));\r\n  assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));\r\n  assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));\r\n  assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));\r\n  assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));\r\n  assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));\r\n  assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));\r\n  assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));\r\n  assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));\r\n  assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));\r\n  assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));\r\n  assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));\r\n  \r\n  /* Check input state */\r\n  __HAL_LOCK(htim);\r\n  \r\n  htim->State = HAL_TIM_STATE_BUSY;\r\n\r\n  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,\r\n     the OSSI State, the dead time value and the Automatic Output Enable Bit */\r\n    \r\n  /* Clear the BDTR bits */\r\n  tmpbdtr &= ~(TIM_BDTR_DTG | TIM_BDTR_LOCK |  TIM_BDTR_OSSI | \r\n               TIM_BDTR_OSSR | TIM_BDTR_BKE | TIM_BDTR_BKP | \r\n               TIM_BDTR_AOE | TIM_BDTR_MOE | TIM_BDTR_BKF |\r\n               TIM_BDTR_BK2F | TIM_BDTR_BK2E | TIM_BDTR_BK2P);\r\n\r\n  /* Set the BDTR bits */\r\n  tmpbdtr |= sBreakDeadTimeConfig->DeadTime;\r\n  tmpbdtr |= sBreakDeadTimeConfig->LockLevel;\r\n  tmpbdtr |= sBreakDeadTimeConfig->OffStateIDLEMode;\r\n  tmpbdtr |= sBreakDeadTimeConfig->OffStateRunMode;\r\n  tmpbdtr |= sBreakDeadTimeConfig->BreakState;\r\n  tmpbdtr |= sBreakDeadTimeConfig->BreakPolarity;\r\n  tmpbdtr |= sBreakDeadTimeConfig->AutomaticOutput;\r\n  tmpbdtr |= (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT);\r\n  tmpbdtr |= (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT);\r\n  tmpbdtr |= sBreakDeadTimeConfig->Break2State;\r\n  tmpbdtr |= sBreakDeadTimeConfig->Break2Polarity;\r\n  \r\n  /* Set TIMx_BDTR */\r\n  htim->Instance->BDTR = tmpbdtr;\r\n  \r\n  __HAL_UNLOCK(htim);\r\n  \r\n  return HAL_OK;\r\n}\r\n#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)\r\n/**\r\n  * @brief  Configures the break input source.\r\n  * @param  htim: TIM handle.\r\n  * @param  BreakInput: Break input to configure\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_BREAKINPUT_BRK: Timer break input\r\n  *            @arg TIM_BREAKINPUT_BRK2: Timer break 2 input\r\n  * @param  sBreakInputConfig: Break input source configuration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,\r\n                                             uint32_t BreakInput,\r\n                                             TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)\r\n\r\n{\r\n  uint32_t tmporx = 0;\r\n  uint32_t bkin_enable_mask = 0;\r\n  uint32_t bkin_enable_bitpos = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));\r\n  assert_param(IS_TIM_BREAKINPUT(BreakInput));\r\n  assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));\r\n  assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));\r\n\r\n  /* Check input state */\r\n  __HAL_LOCK(htim);\r\n  \r\n  switch(sBreakInputConfig->Source)\r\n  {\r\n  case TIM_BREAKINPUTSOURCE_BKIN:\r\n    {\r\n      bkin_enable_mask = TIM1_AF1_BKINE;\r\n      bkin_enable_bitpos = 0;\r\n    }\r\n    break;\r\n  \r\n  case TIM_BREAKINPUTSOURCE_DFSDM1:\r\n    {\r\n      bkin_enable_mask = TIM1_AF1_BKDF1BKE;\r\n      bkin_enable_bitpos = 8;\r\n    }\r\n    break;    \r\n\r\n  default:\r\n    break;\r\n  }\r\n  \r\n  switch(BreakInput)\r\n  {\r\n    case TIM_BREAKINPUT_BRK:\r\n      {\r\n        /* Get the TIMx_AF1 register value */\r\n        tmporx = htim->Instance->AF1;\r\n        \r\n        /* Enable the break input */\r\n        tmporx &= ~bkin_enable_mask;\r\n        tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;\r\n        \r\n        /* Set TIMx_AF1 */\r\n        htim->Instance->AF1 = tmporx;        \r\n      }\r\n        break;\r\n    case TIM_BREAKINPUT_BRK2:\r\n      {\r\n        /* Get the TIMx_AF2 register value */\r\n        tmporx = htim->Instance->AF2;\r\n        \r\n        /* Enable the break input */\r\n        tmporx &= ~bkin_enable_mask;\r\n        tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;\r\n        \r\n        /* Set TIMx_AF2 */\r\n        htim->Instance->AF2 = tmporx;        \r\n      }\r\n      break;    \r\n  default:\r\n    break;\r\n  }\r\n  \r\n  __HAL_UNLOCK(htim);\r\n\r\n  return HAL_OK;\r\n}\r\n#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */\r\n\r\n/**\r\n  * @brief  Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @param  Remap: specifies the TIM input remapping source.\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)\r\n  *            @arg TIM_TIM2_ETH_PTP:   TIM2 ITR1 input is connected to ETH PTP trigger output.\r\n  *            @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF. \r\n  *            @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF. \r\n  *            @arg TIM_TIM5_GPIO:      TIM5 CH4 input is connected to dedicated Timer pin(default)\r\n  *            @arg TIM_TIM5_LSI:       TIM5 CH4 input is connected to LSI clock.\r\n  *            @arg TIM_TIM5_LSE:       TIM5 CH4 input is connected to LSE clock.\r\n  *            @arg TIM_TIM5_RTC:       TIM5 CH4 input is connected to RTC Output event.\r\n  *            @arg TIM_TIM11_GPIO:     TIM11 CH4 input is connected to dedicated Timer pin(default) \r\n  *            @arg TIM_TIM11_SPDIF:    SPDIF Frame synchronous   \r\n  *            @arg TIM_TIM11_HSE:      TIM11 CH4 input is connected to HSE_RTC clock\r\n  *                                     (HSE divided by a programmable prescaler) \r\n  *            @arg TIM_TIM11_MCO1:     TIM11 CH1 input is connected to MCO1    \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)\r\n{\r\n  __HAL_LOCK(htim);\r\n    \r\n  /* Check parameters */\r\n  assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));\r\n  assert_param(IS_TIM_REMAP(Remap));\r\n  \r\n  /* Set the Timer remapping configuration */\r\n  htim->Instance->OR = Remap;\r\n  \r\n  htim->State = HAL_TIM_STATE_READY;\r\n  \r\n  __HAL_UNLOCK(htim);  \r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Group channel 5 and channel 1, 2 or 3\r\n  * @param  htim: TIM handle.\r\n  * @param  OCRef: specifies the reference signal(s) the OC5REF is combined with.\r\n  *         This parameter can be any combination of the following values:\r\n  *         TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC\r\n  *         TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF\r\n  *         TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF\r\n  *         TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRef)\r\n{\r\n  /* Check parameters */\r\n  assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));\r\n  assert_param(IS_TIM_GROUPCH5(OCRef));\r\n\r\n  /* Process Locked */\r\n  __HAL_LOCK(htim);\r\n  \r\n  htim->State = HAL_TIM_STATE_BUSY;\r\n  \r\n  /* Clear GC5Cx bit fields */\r\n  htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1);\r\n  \r\n  /* Set GC5Cx bit fields */\r\n  htim->Instance->CCR5 |= OCRef;\r\n                                   \r\n  htim->State = HAL_TIM_STATE_READY;                                 \r\n  \r\n  __HAL_UNLOCK(htim);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions \r\n  * @brief    Extended Callbacks functions\r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                    ##### Extension Callbacks functions #####\r\n  ==============================================================================  \r\n  [..]  \r\n    This section provides Extension TIM callback functions:\r\n    (+) Timer Commutation callback\r\n    (+) Timer Break callback\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Hall commutation changed callback in non blocking mode \r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_TIMEx_CommutationCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Hall Break detection callback in non blocking mode \r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(htim);\r\n \r\n  /* NOTE : This function Should not be modified, when the callback is needed,\r\n            the HAL_TIMEx_BreakCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions \r\n *  @brief    Extended Peripheral State functions\r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                ##### Extension Peripheral State functions #####\r\n  ==============================================================================  \r\n  [..]\r\n    This subsection permits to get in run-time the status of the peripheral \r\n    and the data flow.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Return the TIM Hall Sensor interface state\r\n  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains\r\n  *                the configuration information for TIM module.\r\n  * @retval HAL state\r\n  */\r\nHAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)\r\n{\r\n  return htim->State;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @brief  TIM DMA Commutation callback. \r\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified DMA module.\r\n  * @retval None\r\n  */\r\nvoid HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  \r\n  htim->State= HAL_TIM_STATE_READY;\r\n    \r\n  HAL_TIMEx_CommutationCallback(htim); \r\n}\r\n\r\n/**\r\n  * @brief  Enables or disables the TIM Capture Compare Channel xN.\r\n  * @param  TIMx to select the TIM peripheral\r\n  * @param  Channel: specifies the TIM Channel\r\n  *          This parameter can be one of the following values:\r\n  *            @arg TIM_Channel_1: TIM Channel 1\r\n  *            @arg TIM_Channel_2: TIM Channel 2\r\n  *            @arg TIM_Channel_3: TIM Channel 3\r\n  * @param  ChannelNState: specifies the TIM Channel CCxNE bit new state.\r\n  *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. \r\n  * @retval None\r\n  */\r\nstatic void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)\r\n{\r\n  uint32_t tmp = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_TIM_ADVANCED_INSTANCE(TIMx));\r\n  assert_param(IS_TIM_COMPLEMENTARY_CHANNELS(Channel));\r\n\r\n  tmp = TIM_CCER_CC1NE << Channel;\r\n\r\n  /* Reset the CCxNE Bit */\r\n  TIMx->CCER &= ~tmp;\r\n\r\n  /* Set or reset the CCxNE Bit */ \r\n  TIMx->CCER |= (uint32_t)(ChannelNState << Channel);\r\n}\r\n\r\n/**\r\n  * @brief  Timer Output Compare 5 configuration\r\n  * @param  TIMx to select the TIM peripheral\r\n  * @param  OC_Config: The output configuration structure\r\n  * @retval None\r\n  */\r\nstatic void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r\n{\r\n  uint32_t tmpccmrx = 0;\r\n  uint32_t tmpccer = 0;\r\n  uint32_t tmpcr2 = 0; \r\n\r\n  /* Disable the output: Reset the CCxE Bit */\r\n  TIMx->CCER &= ~TIM_CCER_CC5E;\r\n  \r\n  /* Get the TIMx CCER register value */\r\n  tmpccer = TIMx->CCER;\r\n  /* Get the TIMx CR2 register value */\r\n  tmpcr2 =  TIMx->CR2; \r\n  /* Get the TIMx CCMR1 register value */\r\n  tmpccmrx = TIMx->CCMR3;\r\n\r\n  /* Reset the Output Compare Mode Bits */\r\n  tmpccmrx &= ~(TIM_CCMR3_OC5M);\r\n  /* Select the Output Compare Mode */\r\n  tmpccmrx |= OC_Config->OCMode;\r\n  \r\n  /* Reset the Output Polarity level */\r\n  tmpccer &= ~TIM_CCER_CC5P;\r\n  /* Set the Output Compare Polarity */\r\n  tmpccer |= (OC_Config->OCPolarity << 16);\r\n\r\n  if(IS_TIM_BREAK_INSTANCE(TIMx))\r\n  {   \r\n    /* Reset the Output Compare IDLE State */\r\n    tmpcr2 &= ~TIM_CR2_OIS5;\r\n    /* Set the Output Idle state */\r\n    tmpcr2 |= (OC_Config->OCIdleState << 8);\r\n  }\r\n  /* Write to TIMx CR2 */\r\n  TIMx->CR2 = tmpcr2;\r\n  \r\n  /* Write to TIMx CCMR3 */\r\n  TIMx->CCMR3 = tmpccmrx;\r\n  \r\n  /* Set the Capture Compare Register value */\r\n  TIMx->CCR5 = OC_Config->Pulse;\r\n  \r\n  /* Write to TIMx CCER */\r\n  TIMx->CCER = tmpccer;  \r\n}\r\n\r\n/**\r\n  * @brief  Timer Output Compare 6 configuration\r\n  * @param  TIMx to select the TIM peripheral\r\n  * @param  OC_Config: The output configuration structure\r\n  * @retval None\r\n  */\r\nstatic void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\r\n{\r\n  uint32_t tmpccmrx = 0;\r\n  uint32_t tmpccer = 0;\r\n  uint32_t tmpcr2 = 0; \r\n\r\n  /* Disable the output: Reset the CCxE Bit */\r\n  TIMx->CCER &= ~TIM_CCER_CC6E;\r\n  \r\n  /* Get the TIMx CCER register value */\r\n  tmpccer = TIMx->CCER;\r\n  /* Get the TIMx CR2 register value */\r\n  tmpcr2 =  TIMx->CR2; \r\n  /* Get the TIMx CCMR1 register value */\r\n  tmpccmrx = TIMx->CCMR3;\r\n    \r\n  /* Reset the Output Compare Mode Bits */\r\n  tmpccmrx &= ~(TIM_CCMR3_OC6M);\r\n  /* Select the Output Compare Mode */\r\n  tmpccmrx |= (OC_Config->OCMode << 8);\r\n  \r\n  /* Reset the Output Polarity level */\r\n  tmpccer &= (uint32_t)~TIM_CCER_CC6P;\r\n  /* Set the Output Compare Polarity */\r\n  tmpccer |= (OC_Config->OCPolarity << 20);\r\n\r\n  if(IS_TIM_BREAK_INSTANCE(TIMx))\r\n  {   \r\n    /* Reset the Output Compare IDLE State */\r\n    tmpcr2 &= ~TIM_CR2_OIS6;\r\n    /* Set the Output Idle state */\r\n    tmpcr2 |= (OC_Config->OCIdleState << 10);\r\n  }\r\n  \r\n  /* Write to TIMx CR2 */\r\n  TIMx->CR2 = tmpcr2;\r\n  \r\n  /* Write to TIMx CCMR3 */\r\n  TIMx->CCMR3 = tmpccmrx;\r\n  \r\n  /* Set the Capture Compare Register value */\r\n  TIMx->CCR6 = OC_Config->Pulse;\r\n  \r\n  /* Write to TIMx CCER */\r\n  TIMx->CCER = tmpccer;  \r\n} \r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_TIM_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_timebase_tim_template.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_timebase_tim_template.c \r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   HAL time base based on the hardware TIM Template.\r\n  *    \r\n  *          This file overrides the native HAL time base functions (defined as weak)\r\n  *          the TIM time base:\r\n  *           + Intializes the TIM peripheral generate a Period elapsed Event each 1ms\r\n  *           + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms\r\n  * \r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @addtogroup HAL_TimeBase\r\n  * @{\r\n  */ \r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\nTIM_HandleTypeDef        TimHandle;\r\n/* Private function prototypes -----------------------------------------------*/\r\nvoid TIM6_DAC_IRQHandler(void);\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/**\r\n  * @brief  This function configures the TIM6 as a time base source. \r\n  *         The time source is configured to have 1ms time base with a dedicated \r\n  *         Tick interrupt priority. \r\n  * @note   This function is called  automatically at the beginning of program after\r\n  *         reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). \r\n  * @param  TickPriority: Tick interrupt priority.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)\r\n{\r\n  RCC_ClkInitTypeDef    clkconfig;\r\n  uint32_t              uwTimclock, uwAPB1Prescaler = 0U;\r\n  uint32_t              uwPrescalerValue = 0U;\r\n  uint32_t              pFLatency;\r\n  \r\n    /*Configure the TIM6 IRQ priority */\r\n  HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0U);\r\n  \r\n  /* Enable the TIM6 global Interrupt */\r\n  HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);\r\n  \r\n  /* Enable TIM6 clock */\r\n  __HAL_RCC_TIM6_CLK_ENABLE();\r\n  \r\n  /* Get clock configuration */\r\n  HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);\r\n  \r\n  /* Get APB1 prescaler */\r\n  uwAPB1Prescaler = clkconfig.APB1CLKDivider;\r\n  \r\n  /* Compute TIM6 clock */\r\n  if (uwAPB1Prescaler == RCC_HCLK_DIV1) \r\n  {\r\n    uwTimclock = HAL_RCC_GetPCLK1Freq();\r\n  }\r\n  else\r\n  {\r\n    uwTimclock = 2*HAL_RCC_GetPCLK1Freq();\r\n  }\r\n  \r\n  /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */\r\n  uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);\r\n  \r\n  /* Initialize TIM6 */\r\n  TimHandle.Instance = TIM6;\r\n  \r\n  /* Initialize TIMx peripheral as follow:\r\n  + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base.\r\n  + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.\r\n  + ClockDivision = 0\r\n  + Counter direction = Up\r\n  */\r\n  TimHandle.Init.Period = (1000000U / 1000U) - 1U;\r\n  TimHandle.Init.Prescaler = uwPrescalerValue;\r\n  TimHandle.Init.ClockDivision = 0;\r\n  TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP;\r\n  if(HAL_TIM_Base_Init(&TimHandle) == HAL_OK)\r\n  {\r\n    /* Start the TIM time Base generation in interrupt mode */\r\n    return HAL_TIM_Base_Start_IT(&TimHandle);\r\n  }\r\n  \r\n  /* Return function status */\r\n  return HAL_ERROR;\r\n}\r\n\r\n/**\r\n  * @brief  Suspend Tick increment.\r\n  * @note   Disable the tick increment by disabling TIM6 update interrupt.\r\n  * @param  None\r\n  * @retval None\r\n  */\r\nvoid HAL_SuspendTick(void)\r\n{\r\n  /* Disable TIM6 update Interrupt */\r\n  __HAL_TIM_DISABLE_IT(&TimHandle, TIM_IT_UPDATE);\r\n}\r\n\r\n/**\r\n  * @brief  Resume Tick increment.\r\n  * @note   Enable the tick increment by Enabling TIM6 update interrupt.\r\n  * @param  None\r\n  * @retval None\r\n  */\r\nvoid HAL_ResumeTick(void)\r\n{\r\n  /* Enable TIM6 Update interrupt */\r\n  __HAL_TIM_ENABLE_IT(&TimHandle, TIM_IT_UPDATE);\r\n}\r\n\r\n/**\r\n  * @brief  Period elapsed callback in non blocking mode\r\n  * @note   This function is called  when TIM6 interrupt took place, inside\r\n  * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment\r\n  * a global variable \"uwTick\" used as application time base.\r\n  * @param  htim : TIM handle\r\n  * @retval None\r\n  */\r\nvoid HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)\r\n{\r\n  HAL_IncTick();\r\n}\r\n\r\n/**\r\n  * @brief  This function handles TIM interrupt request.\r\n  * @param  None\r\n  * @retval None\r\n  */\r\nvoid TIM6_DAC_IRQHandler(void)\r\n{\r\n  HAL_TIM_IRQHandler(&TimHandle);\r\n}\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_uart.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   UART HAL module driver.\r\n  *          This file provides firmware functions to manage the following\r\n  *          functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:\r\n  *           + Initialization and de-initialization functions\r\n  *           + IO operation functions\r\n  *           + Peripheral Control functions\r\n  *           + Peripheral State and Errors functions\r\n  *\r\n  @verbatim\r\n  ==============================================================================\r\n                        ##### How to use this driver #####\r\n  ==============================================================================\r\n  [..]\r\n    The UART HAL driver can be used as follows:\r\n\r\n    (#) Declare a UART_HandleTypeDef handle structure.\r\n\r\n    (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:\r\n        (##) Enable the USARTx interface clock.\r\n        (##) UART pins configuration:\r\n            (+++) Enable the clock for the UART GPIOs.\r\n            (+++) Configure these UART pins as alternate function pull-up.\r\n        (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()\r\n             and HAL_UART_Receive_IT() APIs):\r\n            (+++) Configure the USARTx interrupt priority.\r\n            (+++) Enable the NVIC USART IRQ handle.\r\n        (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()\r\n             and HAL_UART_Receive_DMA() APIs):\r\n            (+++) Declare a DMA handle structure for the Tx/Rx stream.\r\n            (+++) Enable the DMAx interface clock.\r\n            (+++) Configure the declared DMA handle structure with the required\r\n                  Tx/Rx parameters.\r\n            (+++) Configure the DMA Tx/Rx Stream.\r\n            (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.\r\n            (+++) Configure the priority and enable the NVIC for the transfer complete\r\n                  interrupt on the DMA Tx/Rx Stream.\r\n\r\n    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware\r\n        flow control and Mode(Receiver/Transmitter) in the Init structure.\r\n\r\n    (#) For the UART asynchronous mode, initialize the UART registers by calling\r\n        the HAL_UART_Init() API.\r\n\r\n    (#) For the UART Half duplex mode, initialize the UART registers by calling\r\n        the HAL_HalfDuplex_Init() API.\r\n\r\n    (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API.\r\n\r\n    (#) For the Multi-Processor mode, initialize the UART registers by calling\r\n        the HAL_MultiProcessor_Init() API.\r\n\r\n     [..]\r\n       (@) The specific UART interrupts (Transmission complete interrupt,\r\n            RXNE interrupt and Error Interrupts) will be managed using the macros\r\n            __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit\r\n            and receive process.\r\n\r\n     [..]\r\n       (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the\r\n            low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized\r\n            HAL_UART_MspInit() API.\r\n\r\n     [..]\r\n        Three operation modes are available within this driver :\r\n\r\n     *** Polling mode IO operation ***\r\n     =================================\r\n     [..]\r\n       (+) Send an amount of data in blocking mode using HAL_UART_Transmit()\r\n       (+) Receive an amount of data in blocking mode using HAL_UART_Receive()\r\n\r\n     *** Interrupt mode IO operation ***\r\n     ===================================\r\n     [..]\r\n       (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT()\r\n       (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can\r\n            add his own code by customization of function pointer HAL_UART_TxCpltCallback\r\n       (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT()\r\n       (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can\r\n            add his own code by customization of function pointer HAL_UART_RxCpltCallback\r\n       (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can\r\n            add his own code by customization of function pointer HAL_UART_ErrorCallback\r\n\r\n     *** DMA mode IO operation ***\r\n     ==============================\r\n     [..]\r\n       (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA()\r\n       (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can\r\n            add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback\r\n       (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can\r\n            add his own code by customization of function pointer HAL_UART_TxCpltCallback\r\n       (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA()\r\n       (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can\r\n            add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback\r\n       (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can\r\n            add his own code by customization of function pointer HAL_UART_RxCpltCallback\r\n       (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can\r\n            add his own code by customization of function pointer HAL_UART_ErrorCallback\r\n       (+) Pause the DMA Transfer using HAL_UART_DMAPause()\r\n       (+) Resume the DMA Transfer using HAL_UART_DMAResume()\r\n       (+) Stop the DMA Transfer using HAL_UART_DMAStop()\r\n\r\n     *** UART HAL driver macros list ***\r\n     =============================================\r\n     [..]\r\n       Below the list of most used macros in UART HAL driver.\r\n\r\n      (+) __HAL_UART_ENABLE: Enable the UART peripheral\r\n      (+) __HAL_UART_DISABLE: Disable the UART peripheral\r\n      (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not\r\n      (+) __HAL_UART_CLEAR_IT : Clears the specified UART ISR flag\r\n      (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt\r\n      (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt\r\n      (+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not\r\n\r\n     [..]\r\n       (@) You can refer to the UART HAL driver header file for more useful macros\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup UART UART\r\n  * @brief HAL UART module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_UART_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @defgroup UART_Private_Constants UART Private Constants\r\n  * @{\r\n  */\r\n#define UART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \\\r\n                                     USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8))\r\n/**\r\n  * @}\r\n  */\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/** @addtogroup UART_Private_Functions\r\n  * @{\r\n  */\r\nstatic void UART_EndTxTransfer(UART_HandleTypeDef *huart);\r\nstatic void UART_EndRxTransfer(UART_HandleTypeDef *huart);\r\nstatic void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);\r\nstatic void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);\r\nstatic void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);\r\nstatic void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);\r\nstatic void UART_DMAError(DMA_HandleTypeDef *hdma);\r\nstatic void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);\r\nstatic HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);\r\nstatic HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);\r\nstatic HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @defgroup UART_Exported_Functions UART Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions\r\n  *  @brief    Initialization and Configuration functions\r\n  *\r\n@verbatim\r\n===============================================================================\r\n            ##### Initialization and Configuration functions #####\r\n ===============================================================================\r\n    [..]\r\n    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy\r\n    in asynchronous mode.\r\n      (+) For the asynchronous mode only these parameters can be configured:\r\n        (++) Baud Rate\r\n        (++) Word Length\r\n        (++) Stop Bit\r\n        (++) Parity: If the parity is enabled, then the MSB bit of the data written\r\n             in the data register is transmitted but is changed by the parity bit.\r\n             Depending on the frame length defined by the M bit (8-bits or 9-bits),\r\n             please refer to Reference manual for possible UART frame formats.\r\n        (++) Hardware flow control\r\n        (++) Receiver/transmitter modes\r\n        (++) Over Sampling Method\r\n    [..]\r\n    The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs\r\n    follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor\r\n    configuration procedures (details for the procedures are available in reference manual (RM0329)).\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief Initializes the UART mode according to the specified\r\n  *         parameters in the UART_InitTypeDef and creates the associated handle .\r\n  * @param huart: uart handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)\r\n{\r\n  /* Check the UART handle allocation */\r\n  if(huart == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));\r\n  }\r\n  else\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_UART_INSTANCE(huart->Instance));\r\n  }\r\n\r\n  if(huart->gState == HAL_UART_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    huart->Lock = HAL_UNLOCKED;\r\n\r\n    /* Init the low level hardware : GPIO, CLOCK */\r\n    HAL_UART_MspInit(huart);\r\n  }\r\n\r\n  huart->gState = HAL_UART_STATE_BUSY;\r\n\r\n  /* Disable the Peripheral */\r\n  __HAL_UART_DISABLE(huart);\r\n\r\n  /* Set the UART Communication parameters */\r\n  if (UART_SetConfig(huart) == HAL_ERROR)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)\r\n  {\r\n    UART_AdvFeatureConfig(huart);\r\n  }\r\n\r\n  /* In asynchronous mode, the following bits must be kept cleared:\r\n  - LINEN and CLKEN bits in the USART_CR2 register,\r\n  - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/\r\n  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\r\n  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));\r\n\r\n  /* Enable the Peripheral */\r\n  __HAL_UART_ENABLE(huart);\r\n\r\n  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */\r\n  return (UART_CheckIdleState(huart));\r\n}\r\n\r\n/**\r\n  * @brief Initializes the half-duplex mode according to the specified\r\n  *         parameters in the UART_InitTypeDef and creates the associated handle .\r\n  * @param huart: UART handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)\r\n{\r\n  /* Check the UART handle allocation */\r\n  if(huart == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  if(huart->gState == HAL_UART_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    huart->Lock = HAL_UNLOCKED;\r\n\r\n    /* Init the low level hardware : GPIO, CLOCK */\r\n    HAL_UART_MspInit(huart);\r\n  }\r\n\r\n  huart->gState = HAL_UART_STATE_BUSY;\r\n\r\n  /* Disable the Peripheral */\r\n  __HAL_UART_DISABLE(huart);\r\n\r\n  /* Set the UART Communication parameters */\r\n  if (UART_SetConfig(huart) == HAL_ERROR)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)\r\n  {\r\n    UART_AdvFeatureConfig(huart);\r\n  }\r\n\r\n  /* In half-duplex mode, the following bits must be kept cleared:\r\n  - LINEN and CLKEN bits in the USART_CR2 register,\r\n  - SCEN and IREN bits in the USART_CR3 register.*/\r\n  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\r\n  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));\r\n\r\n  /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */\r\n  SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);\r\n\r\n  /* Enable the Peripheral */\r\n  __HAL_UART_ENABLE(huart);\r\n\r\n  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */\r\n  return (UART_CheckIdleState(huart));\r\n}\r\n\r\n\r\n/**\r\n  * @brief Initialize the LIN mode according to the specified\r\n  *        parameters in the UART_InitTypeDef and creates the associated handle .\r\n  * @param huart: UART handle.\r\n  * @param BreakDetectLength: specifies the LIN break detection length.\r\n  *        This parameter can be one of the following values:\r\n  *          @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection\r\n  *          @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)\r\n{\r\n  /* Check the UART handle allocation */\r\n  if(huart == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_UART_INSTANCE(huart->Instance));\r\n  assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));\r\n  assert_param(IS_LIN_WORD_LENGTH(huart->Init.WordLength));\r\n\r\n  if(huart->gState == HAL_UART_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    huart->Lock = HAL_UNLOCKED;\r\n\r\n    /* Init the low level hardware : GPIO, CLOCK */\r\n    HAL_UART_MspInit(huart);\r\n  }\r\n\r\n  huart->gState = HAL_UART_STATE_BUSY;\r\n\r\n  /* Disable the Peripheral */\r\n  __HAL_UART_DISABLE(huart);\r\n\r\n  /* Set the UART Communication parameters */\r\n  if (UART_SetConfig(huart) == HAL_ERROR)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)\r\n  {\r\n    UART_AdvFeatureConfig(huart);\r\n  }\r\n\r\n  /* In LIN mode, the following bits must be kept cleared:\r\n  - LINEN and CLKEN bits in the USART_CR2 register,\r\n  - SCEN and IREN bits in the USART_CR3 register.*/\r\n  CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);\r\n  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));\r\n\r\n  /* Enable the LIN mode by setting the LINEN bit in the CR2 register */\r\n  SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);\r\n\r\n  /* Set the USART LIN Break detection length. */\r\n  MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);\r\n\r\n  /* Enable the Peripheral */\r\n  __HAL_UART_ENABLE(huart);\r\n\r\n  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */\r\n  return (UART_CheckIdleState(huart));\r\n}\r\n\r\n\r\n/**\r\n  * @brief Initialize the multiprocessor mode according to the specified\r\n  *        parameters in the UART_InitTypeDef and initialize the associated handle.\r\n  * @param huart: UART handle.\r\n  * @param Address: UART node address (4-, 6-, 7- or 8-bit long).\r\n  * @param WakeUpMethod: specifies the UART wakeup method.\r\n  *        This parameter can be one of the following values:\r\n  *          @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection\r\n  *          @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark\r\n  * @note  If the user resorts to idle line detection wake up, the Address parameter\r\n  *        is useless and ignored by the initialization function.\r\n  * @note  If the user resorts to address mark wake up, the address length detection\r\n  *        is configured by default to 4 bits only. For the UART to be able to\r\n  *        manage 6-, 7- or 8-bit long addresses detection\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)\r\n{\r\n  /* Check the UART handle allocation */\r\n  if(huart == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the wake up method parameter */\r\n  assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));\r\n\r\n  if(huart->gState == HAL_UART_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    huart->Lock = HAL_UNLOCKED;\r\n\r\n    /* Init the low level hardware : GPIO, CLOCK */\r\n    HAL_UART_MspInit(huart);\r\n  }\r\n\r\n  huart->gState = HAL_UART_STATE_BUSY;\r\n\r\n  /* Disable the Peripheral */\r\n  __HAL_UART_DISABLE(huart);\r\n\r\n  /* Set the UART Communication parameters */\r\n  if (UART_SetConfig(huart) == HAL_ERROR)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)\r\n  {\r\n    UART_AdvFeatureConfig(huart);\r\n  }\r\n\r\n  /* In multiprocessor mode, the following bits must be kept cleared:\r\n  - LINEN and CLKEN bits in the USART_CR2 register,\r\n  - SCEN, HDSEL and IREN  bits in the USART_CR3 register. */\r\n  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\r\n  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));\r\n\r\n  if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)\r\n  {\r\n    /* If address mark wake up method is chosen, set the USART address node */\r\n    MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));\r\n  }\r\n\r\n  /* Set the wake up method by setting the WAKE bit in the CR1 register */\r\n  MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);\r\n\r\n  /* Enable the Peripheral */\r\n  __HAL_UART_ENABLE(huart);\r\n\r\n  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */\r\n  return (UART_CheckIdleState(huart));\r\n}\r\n\r\n\r\n/**\r\n  * @brief Initialize the RS485 Driver enable feature according to the specified\r\n  *         parameters in the UART_InitTypeDef and creates the associated handle.\r\n  * @param huart: UART handle.\r\n  * @param Polarity: select the driver enable polarity.\r\n  *        This parameter can be one of the following values:\r\n  *          @arg @ref UART_DE_POLARITY_HIGH DE signal is active high\r\n  *          @arg @ref UART_DE_POLARITY_LOW  DE signal is active low\r\n  * @param AssertionTime: Driver Enable assertion time:\r\n  *                         5-bit value defining the time between the activation of the DE (Driver Enable)\r\n  *                         signal and the beginning of the start bit. It is expressed in sample time\r\n  *                         units (1/8 or 1/16 bit time, depending on the oversampling rate)\r\n  * @param DeassertionTime: Driver Enable deassertion time:\r\n  *                         5-bit value defining the time between the end of the last stop bit, in a\r\n  *                         transmitted message, and the de-activation of the DE (Driver Enable) signal.\r\n  *                         It is expressed in sample time units (1/8 or 1/16 bit time, depending on the\r\n  *                         oversampling rate).\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)\r\n{\r\n  uint32_t temp = 0x0;\r\n\r\n  /* Check the UART handle allocation */\r\n  if(huart == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n  /* Check the Driver Enable UART instance */\r\n  assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));\r\n\r\n  /* Check the Driver Enable polarity */\r\n  assert_param(IS_UART_DE_POLARITY(Polarity));\r\n\r\n  /* Check the Driver Enable assertion time */\r\n  assert_param(IS_UART_ASSERTIONTIME(AssertionTime));\r\n\r\n  /* Check the Driver Enable deassertion time */\r\n  assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));\r\n\r\n  if(huart->gState == HAL_UART_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    huart->Lock = HAL_UNLOCKED;\r\n\r\n    /* Init the low level hardware : GPIO, CLOCK, CORTEX */\r\n    HAL_UART_MspInit(huart);\r\n  }\r\n\r\n  huart->gState = HAL_UART_STATE_BUSY;\r\n\r\n  /* Disable the Peripheral */\r\n  __HAL_UART_DISABLE(huart);\r\n\r\n  /* Set the UART Communication parameters */\r\n  if (UART_SetConfig(huart) == HAL_ERROR)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  if(huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)\r\n  {\r\n    UART_AdvFeatureConfig(huart);\r\n  }\r\n\r\n  /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */\r\n  SET_BIT(huart->Instance->CR3, USART_CR3_DEM);\r\n\r\n  /* Set the Driver Enable polarity */\r\n  MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);\r\n\r\n  /* Set the Driver Enable assertion and deassertion times */\r\n  temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);\r\n  temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);\r\n  MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT|USART_CR1_DEAT), temp);\r\n\r\n  /* Enable the Peripheral */\r\n  __HAL_UART_ENABLE(huart);\r\n\r\n  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */\r\n  return (UART_CheckIdleState(huart));\r\n}\r\n\r\n/**\r\n  * @brief DeInitializes the UART peripheral\r\n  * @param huart: uart handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)\r\n{\r\n  /* Check the UART handle allocation */\r\n  if(huart == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_UART_INSTANCE(huart->Instance));\r\n\r\n  huart->gState = HAL_UART_STATE_BUSY;\r\n\r\n  /* Disable the Peripheral */\r\n  __HAL_UART_DISABLE(huart);\r\n\r\n  huart->Instance->CR1 = 0x0U;\r\n  huart->Instance->CR2 = 0x0U;\r\n  huart->Instance->CR3 = 0x0U;\r\n\r\n  /* DeInit the low level hardware */\r\n  HAL_UART_MspDeInit(huart);\r\n\r\n  huart->ErrorCode = HAL_UART_ERROR_NONE;\r\n  huart->gState    = HAL_UART_STATE_RESET;\r\n  huart->RxState   = HAL_UART_STATE_RESET;\r\n\r\n  /* Process Unlock */\r\n  __HAL_UNLOCK(huart);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief UART MSP Init\r\n  * @param huart: uart handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(huart);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_UART_MspInit can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief UART MSP DeInit\r\n  * @param huart: uart handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(huart);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_UART_MspDeInit can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Exported_Functions_Group2 IO operation functions\r\n  * @brief UART Transmit/Receive functions\r\n  *\r\n@verbatim\r\n ===============================================================================\r\n                      ##### IO operation functions #####\r\n ===============================================================================\r\n    This subsection provides a set of functions allowing to manage the UART asynchronous\r\n    and Half duplex data transfers.\r\n\r\n    (#) There are two mode of transfer:\r\n       (+) Blocking mode: The communication is performed in polling mode.\r\n           The HAL status of all data processing is returned by the same function\r\n           after finishing transfer.\r\n       (+) Non-Blocking mode: The communication is performed using Interrupts\r\n           or DMA, These API's return the HAL status.\r\n           The end of the data processing will be indicated through the\r\n           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when\r\n           using DMA mode.\r\n           The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks\r\n           will be executed respectively at the end of the transmit or Receive process\r\n           The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected\r\n\r\n    (#) Blocking mode API's are :\r\n        (+) HAL_UART_Transmit()\r\n        (+) HAL_UART_Receive()\r\n\r\n    (#) Non-Blocking mode API's with Interrupt are :\r\n        (+) HAL_UART_Transmit_IT()\r\n        (+) HAL_UART_Receive_IT()\r\n        (+) HAL_UART_IRQHandler()\r\n        (+) UART_Transmit_IT()\r\n        (+) UART_Receive_IT()\r\n\r\n    (#) Non-Blocking mode API's with DMA are :\r\n        (+) HAL_UART_Transmit_DMA()\r\n        (+) HAL_UART_Receive_DMA()\r\n        (+) HAL_UART_DMAPause()\r\n        (+) HAL_UART_DMAResume()\r\n        (+) HAL_UART_DMAStop()\r\n\r\n    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:\r\n        (+) HAL_UART_TxHalfCpltCallback()\r\n        (+) HAL_UART_TxCpltCallback()\r\n        (+) HAL_UART_RxHalfCpltCallback()\r\n        (+) HAL_UART_RxCpltCallback()\r\n        (+) HAL_UART_ErrorCallback()\r\n\r\n\r\n    -@- In the Half duplex communication, it is forbidden to run the transmit\r\n        and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief Send an amount of data in blocking mode.\r\n  * @param huart: UART handle.\r\n  * @param pData: Pointer to data buffer.\r\n  * @param Size: Amount of data to be sent.\r\n  * @param Timeout: Timeout duration.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r\n{\r\n  uint16_t* tmp;\r\n  uint32_t tickstart = 0U;\r\n\r\n  /* Check that a Tx process is not already ongoing */\r\n  if(huart->gState == HAL_UART_STATE_READY)\r\n  {\r\n    if((pData == NULL ) || (Size == 0U))\r\n    {\r\n      return  HAL_ERROR;\r\n    }\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(huart);\r\n\r\n    huart->ErrorCode = HAL_UART_ERROR_NONE;\r\n    huart->gState = HAL_UART_STATE_BUSY_TX;\r\n\r\n    /* Init tickstart for timeout managment*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    huart->TxXferSize = Size;\r\n    huart->TxXferCount = Size;\r\n    while(huart->TxXferCount > 0U)\r\n    {\r\n      huart->TxXferCount--;\r\n      if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r\n      {\r\n        tmp = (uint16_t*) pData;\r\n        huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);\r\n        pData += 2;\r\n      }\r\n      else\r\n      {\r\n        huart->Instance->TDR = (*pData++ & (uint8_t)0xFFU);\r\n      }\r\n    }\r\n    if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n\r\n    /* At end of Tx process, restore huart->gState to Ready */\r\n    huart->gState = HAL_UART_STATE_READY;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(huart);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Receive an amount of data in blocking mode.\r\n  * @param huart: UART handle.\r\n  * @param pData: pointer to data buffer.\r\n  * @param Size: amount of data to be received.\r\n  * @param Timeout: Timeout duration.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)\r\n{\r\n  uint16_t* tmp;\r\n  uint16_t uhMask;\r\n  uint32_t tickstart = 0U;\r\n\r\n  /* Check that a Rx process is not already ongoing */\r\n  if(huart->RxState == HAL_UART_STATE_READY)\r\n  {\r\n    if((pData == NULL ) || (Size == 0U))\r\n    {\r\n      return  HAL_ERROR;\r\n    }\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(huart);\r\n\r\n    huart->ErrorCode = HAL_UART_ERROR_NONE;\r\n    huart->RxState = HAL_UART_STATE_BUSY_RX;\r\n\r\n    /* Init tickstart for timeout managment*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    huart->RxXferSize = Size;\r\n    huart->RxXferCount = Size;\r\n\r\n    /* Computation of UART mask to apply to RDR register */\r\n    UART_MASK_COMPUTATION(huart);\r\n    uhMask = huart->Mask;\r\n\r\n    /* as long as data have to be received */\r\n    while(huart->RxXferCount > 0U)\r\n    {\r\n      huart->RxXferCount--;\r\n      if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r\n      {\r\n        tmp = (uint16_t*) pData ;\r\n        *tmp = (uint16_t)(huart->Instance->RDR & uhMask);\r\n        pData +=2U;\r\n      }\r\n      else\r\n      {\r\n        *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);\r\n      }\r\n    }\r\n\r\n    /* At end of Rx process, restore huart->RxState to Ready */\r\n    huart->RxState = HAL_UART_STATE_READY;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(huart);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Send an amount of data in interrupt mode.\r\n  * @param huart: UART handle.\r\n  * @param pData: pointer to data buffer.\r\n  * @param Size: amount of data to be sent.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\r\n{\r\n  /* Check that a Tx process is not already ongoing */\r\n  if(huart->gState == HAL_UART_STATE_READY)\r\n  {\r\n    if((pData == NULL ) || (Size == 0U))\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(huart);\r\n\r\n    huart->pTxBuffPtr = pData;\r\n    huart->TxXferSize = Size;\r\n    huart->TxXferCount = Size;\r\n\r\n    huart->ErrorCode = HAL_UART_ERROR_NONE;\r\n    huart->gState = HAL_UART_STATE_BUSY_TX;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(huart);\r\n\r\n    /* Enable the UART Transmit Data Register Empty Interrupt */\r\n    SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Receive an amount of data in interrupt mode.\r\n  * @param huart: UART handle.\r\n  * @param pData: pointer to data buffer.\r\n  * @param Size: amount of data to be received.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\r\n{\r\n  /* Check that a Rx process is not already ongoing */\r\n  if(huart->RxState == HAL_UART_STATE_READY)\r\n  {\r\n    if((pData == NULL ) || (Size == 0U))\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(huart);\r\n\r\n    huart->pRxBuffPtr = pData;\r\n    huart->RxXferSize = Size;\r\n    huart->RxXferCount = Size;\r\n\r\n    /* Computation of UART mask to apply to RDR register */\r\n    UART_MASK_COMPUTATION(huart);\r\n\r\n    huart->ErrorCode = HAL_UART_ERROR_NONE;\r\n    huart->RxState = HAL_UART_STATE_BUSY_RX;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(huart);\r\n\r\n    /* Enable the UART Parity Error Interrupt */\r\n    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r\n\r\n    /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */\r\n    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);\r\n\r\n    /* Enable the UART Data Register not empty Interrupt */\r\n    SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Send an amount of data in DMA mode.\r\n  * @param huart: UART handle.\r\n  * @param pData: pointer to data buffer.\r\n  * @param Size: amount of data to be sent.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\r\n{\r\n  uint32_t *tmp;\r\n\r\n  /* Check that a Tx process is not already ongoing */\r\n  if(huart->gState == HAL_UART_STATE_READY)\r\n  {\r\n    if((pData == NULL ) || (Size == 0U))\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(huart);\r\n\r\n    huart->pTxBuffPtr = pData;\r\n    huart->TxXferSize = Size;\r\n    huart->TxXferCount = Size;\r\n\r\n    huart->ErrorCode = HAL_UART_ERROR_NONE;\r\n    huart->gState = HAL_UART_STATE_BUSY_TX;\r\n\r\n    /* Set the UART DMA transfer complete callback */\r\n    huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;\r\n\r\n    /* Set the UART DMA Half transfer complete callback */\r\n    huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;\r\n\r\n    /* Set the DMA error callback */\r\n    huart->hdmatx->XferErrorCallback = UART_DMAError;\r\n\r\n    /* Set the DMA abort callback */\r\n    huart->hdmatx->XferAbortCallback = NULL;\r\n\r\n    /* Enable the UART transmit DMA channel */\r\n    tmp = (uint32_t*)&pData;\r\n    HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->TDR, Size);\r\n\r\n    /* Clear the TC flag in the SR register by writing 0 to it */\r\n    __HAL_UART_CLEAR_IT(huart, UART_FLAG_TC);\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(huart);\r\n\r\n    /* Enable the DMA transfer for transmit request by setting the DMAT bit\r\n       in the UART CR3 register */\r\n    SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Receive an amount of data in DMA mode.\r\n  * @param huart: UART handle.\r\n  * @param pData: pointer to data buffer.\r\n  * @param Size: amount of data to be received.\r\n  * @note   When the UART parity is enabled (PCE = 1), the received data contain\r\n  *         the parity bit (MSB position).\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\r\n{\r\n  uint32_t *tmp;\r\n\r\n  /* Check that a Rx process is not already ongoing */\r\n  if(huart->RxState == HAL_UART_STATE_READY)\r\n  {\r\n    if((pData == NULL ) || (Size == 0U))\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(huart);\r\n\r\n    huart->pRxBuffPtr = pData;\r\n    huart->RxXferSize = Size;\r\n\r\n    huart->ErrorCode = HAL_UART_ERROR_NONE;\r\n    huart->RxState = HAL_UART_STATE_BUSY_RX;\r\n\r\n    /* Set the UART DMA transfer complete callback */\r\n    huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;\r\n\r\n    /* Set the UART DMA Half transfer complete callback */\r\n    huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;\r\n\r\n    /* Set the DMA error callback */\r\n    huart->hdmarx->XferErrorCallback = UART_DMAError;\r\n\r\n    /* Set the DMA abort callback */\r\n    huart->hdmarx->XferAbortCallback = NULL;\r\n\r\n    /* Enable the DMA channel */\r\n    tmp = (uint32_t*)&pData;\r\n    HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, *(uint32_t*)tmp, Size);\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(huart);\r\n\r\n    /* Enable the UART Parity Error Interrupt */\r\n    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r\n\r\n    /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */\r\n    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);\r\n\r\n    /* Enable the DMA transfer for the receiver request by setting the DMAR bit\r\n    in the UART CR3 register */\r\n    SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Pause the DMA Transfer.\r\n  * @param huart: UART handle.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(huart);\r\n\r\n  if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&\r\n      (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))\r\n  {\r\n    /* Disable the UART DMA Tx request */\r\n    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r\n  }\r\n  if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&\r\n      (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))\r\n  {\r\n    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */\r\n    CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r\n    CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r\n\r\n    /* Disable the UART DMA Rx request */\r\n    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r\n  }\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(huart);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Resume the DMA Transfer.\r\n  * @param huart: UART handle.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(huart);\r\n\r\n  if(huart->gState == HAL_UART_STATE_BUSY_TX)\r\n  {\r\n    /* Enable the UART DMA Tx request */\r\n    SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r\n  }\r\n  if(huart->RxState == HAL_UART_STATE_BUSY_RX)\r\n  {\r\n    /* Clear the Overrun flag before resuming the Rx transfer*/\r\n    __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);\r\n\r\n    /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */\r\n    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r\n    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);\r\n\r\n    /* Enable the UART DMA Rx request */\r\n    SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r\n  }\r\n\r\n  /* If the UART peripheral is still not enabled, enable it */\r\n  if ((huart->Instance->CR1 & USART_CR1_UE) == 0U)\r\n  {\r\n    /* Enable UART peripheral */\r\n    __HAL_UART_ENABLE(huart);\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Stop the DMA Transfer.\r\n  * @param huart: UART handle.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)\r\n{\r\n  /* The Lock is not implemented on this API to allow the user application\r\n     to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /\r\n     HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:\r\n     indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete\r\n     interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of\r\n     the stream and the corresponding call back is executed. */\r\n\r\n  /* Stop UART DMA Tx request if ongoing */\r\n  if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&\r\n      (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))\r\n  {\r\n    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r\n\r\n    /* Abort the UART DMA Tx channel */\r\n    if(huart->hdmatx != NULL)\r\n    {\r\n      HAL_DMA_Abort(huart->hdmatx);\r\n    }\r\n\r\n    UART_EndTxTransfer(huart);\r\n  }\r\n\r\n  /* Stop UART DMA Rx request if ongoing */\r\n  if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&\r\n      (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))\r\n  {\r\n    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r\n\r\n    /* Abort the UART DMA Rx channel */\r\n    if(huart->hdmarx != NULL)\r\n    {\r\n      HAL_DMA_Abort(huart->hdmarx);\r\n    }\r\n\r\n    UART_EndRxTransfer(huart);\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief This function handles UART interrupt request.\r\n  * @param huart: uart handle\r\n  * @retval None\r\n  */\r\nvoid HAL_UART_IRQHandler(UART_HandleTypeDef *huart)\r\n{\r\n  uint32_t isrflags   = READ_REG(huart->Instance->ISR);\r\n  uint32_t cr1its     = READ_REG(huart->Instance->CR1);\r\n  uint32_t cr3its     = READ_REG(huart->Instance->CR3);\r\n  uint32_t errorflags;\r\n\r\n  /* If no error occurs */\r\n  errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));\r\n  if (errorflags == RESET)\r\n  {\r\n    /* UART in mode Receiver ---------------------------------------------------*/\r\n    if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))\r\n    {\r\n      UART_Receive_IT(huart);\r\n      return;\r\n    }\r\n  }\r\n\r\n  /* If some errors occur */\r\n  if((errorflags != RESET) && ((cr3its & (USART_CR3_EIE | USART_CR1_PEIE)) != RESET))\r\n  {\r\n\r\n    /* UART parity error interrupt occurred -------------------------------------*/\r\n    if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))\r\n    {\r\n      __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF);\r\n\r\n      huart->ErrorCode |= HAL_UART_ERROR_PE;\r\n    }\r\n\r\n    /* UART frame error interrupt occurred --------------------------------------*/\r\n    if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))\r\n    {\r\n      __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF);\r\n\r\n      huart->ErrorCode |= HAL_UART_ERROR_FE;\r\n    }\r\n\r\n    /* UART noise error interrupt occurred --------------------------------------*/\r\n    if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))\r\n    {\r\n      __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF);\r\n\r\n      huart->ErrorCode |= HAL_UART_ERROR_NE;\r\n    }\r\n    \r\n    /* UART Over-Run interrupt occurred -----------------------------------------*/\r\n    if(((isrflags & USART_ISR_ORE) != RESET) &&\r\n       (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))\r\n    {\r\n      __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);\r\n\r\n      huart->ErrorCode |= HAL_UART_ERROR_ORE;\r\n    }\r\n\r\n    /* Call UART Error Call back function if need be --------------------------*/\r\n    if(huart->ErrorCode != HAL_UART_ERROR_NONE)\r\n    {\r\n      /* UART in mode Receiver ---------------------------------------------------*/\r\n      if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))\r\n      {\r\n        UART_Receive_IT(huart);\r\n      }\r\n\r\n      /* If Overrun error occurs, or if any error occurs in DMA mode reception,\r\n         consider error as blocking */\r\n      if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) ||\r\n          (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))\r\n      {\r\n        /* Blocking error : transfer is aborted\r\n           Set the UART state ready to be able to start again the process,\r\n           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */\r\n        UART_EndRxTransfer(huart);\r\n\r\n        /* Disable the UART DMA Rx request if enabled */\r\n        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))\r\n        {\r\n          CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r\n\r\n          /* Abort the UART DMA Rx channel */\r\n          if(huart->hdmarx != NULL)\r\n          {\r\n            /* Set the UART DMA Abort callback :\r\n            will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */\r\n            huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;\r\n\r\n            /* Abort DMA RX */\r\n            if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)\r\n            {\r\n              /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */\r\n              huart->hdmarx->XferAbortCallback(huart->hdmarx);\r\n            }\r\n          }\r\n          else\r\n          {\r\n            /* Call user error callback */\r\n            HAL_UART_ErrorCallback(huart);\r\n          }\r\n        }\r\n        else\r\n        {\r\n          /* Call user error callback */\r\n          HAL_UART_ErrorCallback(huart);\r\n        }\r\n      }\r\n      else\r\n      {\r\n        /* Non Blocking error : transfer could go on.\r\n           Error is notified to user through user error callback */\r\n        HAL_UART_ErrorCallback(huart);\r\n        huart->ErrorCode = HAL_UART_ERROR_NONE;\r\n      }\r\n    }\r\n    return;\r\n\r\n  } /* End if some error occurs */\r\n\r\n  /* UART in mode Transmitter ------------------------------------------------*/\r\n  if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))\r\n  {\r\n    UART_Transmit_IT(huart);\r\n    return;\r\n  }\r\n\r\n  /* UART in mode Transmitter (transmission end) -----------------------------*/\r\n  if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))\r\n  {\r\n    UART_EndTransmit_IT(huart);\r\n    return;\r\n  }\r\n\r\n}\r\n\r\n/**\r\n  * @brief  This function handles UART Communication Timeout.\r\n  * @param  huart UART handle\r\n  * @param  Flag specifies the UART flag to check.\r\n  * @param  Status The new Flag status (SET or RESET).\r\n  * @param  Tickstart Tick start value\r\n  * @param  Timeout Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)\r\n{\r\n  /* Wait until flag is set */\r\n  while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0U)||((HAL_GetTick()-Tickstart) >=  Timeout))\r\n      {\r\n        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */\r\n        CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));\r\n        CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r\n\r\n        huart->gState = HAL_UART_STATE_READY;\r\n        huart->RxState = HAL_UART_STATE_READY;\r\n\r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(huart);\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief DMA UART transmit process complete callback\r\n  * @param hdma: DMA handle\r\n  * @retval None\r\n  */\r\nstatic void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n\r\n  /* DMA Normal mode*/\r\n  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)\r\n  {\r\n    huart->TxXferCount = 0U;\r\n\r\n    /* Disable the DMA transfer for transmit request by setting the DMAT bit\r\n       in the UART CR3 register */\r\n    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\r\n\r\n    /* Enable the UART Transmit Complete Interrupt */\r\n    SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);\r\n  }\r\n  /* DMA Circular mode */\r\n  else\r\n  {\r\n    HAL_UART_TxCpltCallback(huart);\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief DMA UART transmit process half complete callback\r\n  * @param hdma : DMA handle\r\n  * @retval None\r\n  */\r\nstatic void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n\r\n  HAL_UART_TxHalfCpltCallback(huart);\r\n}\r\n\r\n/**\r\n  * @brief DMA UART receive process complete callback\r\n  * @param hdma: DMA handle\r\n  * @retval None\r\n  */\r\nstatic void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n\r\n  /* DMA Normal mode */\r\n  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)\r\n  {\r\n    huart->RxXferCount = 0U;\r\n\r\n    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */\r\n    CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);\r\n    CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r\n\r\n    /* Disable the DMA transfer for the receiver request by setting the DMAR bit\r\n    in the UART CR3 register */\r\n    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\r\n\r\n\t/* At end of Rx process, restore huart->RxState to Ready */\r\n    huart->RxState = HAL_UART_STATE_READY;\r\n  }\r\n  HAL_UART_RxCpltCallback(huart);\r\n}\r\n\r\n/**\r\n  * @brief DMA UART receive process half complete callback\r\n  * @param hdma : DMA handle\r\n  * @retval None\r\n  */\r\nstatic void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n\r\n  HAL_UART_RxHalfCpltCallback(huart);\r\n}\r\n\r\n/**\r\n  * @brief DMA UART communication error callback\r\n  * @param hdma: DMA handle\r\n  * @retval None\r\n  */\r\nstatic void UART_DMAError(DMA_HandleTypeDef *hdma)\r\n{\r\n  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  huart->RxXferCount = 0U;\r\n  huart->TxXferCount = 0U;\r\n  /* Stop UART DMA Tx request if ongoing */\r\n  if (  (huart->gState == HAL_UART_STATE_BUSY_TX)\r\n      &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) )\r\n  {\r\n    UART_EndTxTransfer(huart);\r\n  }\r\n\r\n  /* Stop UART DMA Rx request if ongoing */\r\n  if (  (huart->RxState == HAL_UART_STATE_BUSY_RX)\r\n      &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) )\r\n  {\r\n    UART_EndRxTransfer(huart);\r\n  }\r\n  SET_BIT(huart->ErrorCode, HAL_UART_ERROR_DMA);\r\n  HAL_UART_ErrorCallback(huart);\r\n}\r\n\r\n/**\r\n  * @brief DMA UART communication abort callback, when call by HAL services on Error\r\n  *        (To be called at end of DMA Abort procedure following error occurrence).\r\n  * @param hdma: DMA handle.\r\n  * @retval None\r\n  */\r\nstatic void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)\r\n{\r\n  UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);\r\n  huart->RxXferCount = 0U;\r\n  huart->TxXferCount = 0U;\r\n\r\n  HAL_UART_ErrorCallback(huart);\r\n}\r\n\r\n/**\r\n  * @brief Tx Transfer completed callbacks\r\n  * @param huart: uart handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(huart);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_UART_TxCpltCallback can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Tx Half Transfer completed callbacks.\r\n  * @param  huart: UART handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(huart);\r\n\r\n  /* NOTE: This function should not be modified, when the callback is needed,\r\n           the HAL_UART_TxHalfCpltCallback can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief Rx Transfer completed callbacks\r\n  * @param huart: uart handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(huart);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_UART_RxCpltCallback can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Rx Half Transfer completed callbacks.\r\n  * @param  huart: UART handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(huart);\r\n\r\n  /* NOTE: This function should not be modified, when the callback is needed,\r\n           the HAL_UART_RxHalfCpltCallback can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief UART error callbacks\r\n  * @param huart: uart handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(huart);\r\n\r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_UART_ErrorCallback can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief Send an amount of data in interrupt mode\r\n  *         Function called under interruption only, once\r\n  *         interruptions have been enabled by HAL_UART_Transmit_IT()\r\n  * @param  huart: UART handle\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)\r\n{\r\n  uint16_t* tmp;\r\n\r\n  /* Check that a Tx process is ongoing */\r\n  if (huart->gState == HAL_UART_STATE_BUSY_TX)\r\n  {\r\n\r\n    if(huart->TxXferCount == 0U)\r\n    {\r\n      /* Disable the UART Transmit Data Register Empty Interrupt */\r\n      CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);\r\n\r\n      /* Enable the UART Transmit Complete Interrupt */\r\n      SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);\r\n\r\n      return HAL_OK;\r\n    }\r\n    else\r\n    {\r\n      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r\n      {\r\n        tmp = (uint16_t*) huart->pTxBuffPtr;\r\n        huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);\r\n        huart->pTxBuffPtr += 2U;\r\n      }\r\n      else\r\n      {\r\n        huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFFU);\r\n      }\r\n\r\n      huart->TxXferCount--;\r\n\r\n      return HAL_OK;\r\n    }\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Wrap up transmission in non-blocking mode.\r\n  * @param  huart: pointer to a UART_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified UART module.\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)\r\n{\r\n  /* Disable the UART Transmit Complete Interrupt */\r\n  CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);\r\n\r\n  /* Tx process is ended, restore huart->gState to Ready */\r\n  huart->gState = HAL_UART_STATE_READY;\r\n\r\n  HAL_UART_TxCpltCallback(huart);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Receive an amount of data in interrupt mode\r\n  *         Function called under interruption only, once\r\n  *         interruptions have been enabled by HAL_UART_Receive_IT()\r\n  * @param  huart: UART handle\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)\r\n{\r\n  uint16_t* tmp;\r\n  uint16_t uhMask = huart->Mask;\r\n\r\n  /* Check that a Rx process is ongoing */\r\n  if(huart->RxState == HAL_UART_STATE_BUSY_RX)\r\n  {\r\n\r\n    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\r\n    {\r\n      tmp = (uint16_t*) huart->pRxBuffPtr ;\r\n      *tmp = (uint16_t)(huart->Instance->RDR & uhMask);\r\n      huart->pRxBuffPtr +=2;\r\n    }\r\n    else\r\n    {\r\n      *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);\r\n    }\r\n\r\n    if(--huart->RxXferCount == 0)\r\n    {\r\n      /* Disable the UART Parity Error Interrupt and RXNE interrupt*/\r\n      CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r\n\r\n      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */\r\n      CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r\n\r\n      /* Rx process is completed, restore huart->RxState to Ready */\r\n      huart->RxState = HAL_UART_STATE_READY;\r\n\r\n      HAL_UART_RxCpltCallback(huart);\r\n\r\n      return HAL_OK;\r\n    }\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    /* Clear RXNE interrupt flag */\r\n    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);\r\n\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).\r\n  * @param  huart: UART handle.\r\n  * @retval None\r\n  */\r\nstatic void UART_EndTxTransfer(UART_HandleTypeDef *huart)\r\n{\r\n  /* Disable TXEIE and TCIE interrupts */\r\n  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));\r\n\r\n  /* At end of Tx process, restore huart->gState to Ready */\r\n  huart->gState = HAL_UART_STATE_READY;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).\r\n  * @param  huart: UART handle.\r\n  * @retval None\r\n  */\r\nstatic void UART_EndRxTransfer(UART_HandleTypeDef *huart)\r\n{\r\n  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\r\n  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r\n  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\r\n\r\n  /* At end of Rx process, restore huart->RxState to Ready */\r\n  huart->RxState = HAL_UART_STATE_READY;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions\r\n  *  @brief   UART control functions\r\n  *\r\n@verbatim\r\n ===============================================================================\r\n                      ##### Peripheral Control functions #####\r\n ===============================================================================\r\n    [..]\r\n    This subsection provides a set of functions allowing to control the UART.\r\n     (+) HAL_UART_GetState() API is helpful to check in run-time the state of the UART peripheral.\r\n     (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode\r\n     (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode\r\n     (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode\r\n     (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode\r\n     (+) UART_SetConfig() API configures the UART peripheral\r\n     (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features\r\n     (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization\r\n     (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter\r\n     (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver\r\n     (+) HAL_LIN_SendBreak() API transmits the break characters\r\n\t (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address\r\n         detection length to more than 4 bits for multiprocessor address mark wake up.\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief Enable UART in mute mode (doesn't mean UART enters mute mode;\r\n  * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called)\r\n  * @param huart: UART handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(huart);\r\n\r\n  huart->gState = HAL_UART_STATE_BUSY;\r\n\r\n  /* Enable USART mute mode by setting the MME bit in the CR1 register */\r\n  SET_BIT(huart->Instance->CR1, USART_CR1_MME);\r\n\r\n  huart->gState = HAL_UART_STATE_READY;\r\n\r\n  return (UART_CheckIdleState(huart));\r\n}\r\n\r\n/**\r\n  * @brief Disable UART mute mode (doesn't mean it actually wakes up the software,\r\n  * as it may not have been in mute mode at this very moment).\r\n  * @param huart: uart handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(huart);\r\n\r\n  huart->gState = HAL_UART_STATE_BUSY;\r\n\r\n   /* Disable USART mute mode by clearing the MME bit in the CR1 register */\r\n  CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);\r\n\r\n  huart->gState = HAL_UART_STATE_READY;\r\n\r\n  return (UART_CheckIdleState(huart));\r\n}\r\n\r\n/**\r\n  * @brief Enter UART mute mode (means UART actually enters mute mode).\r\n  * To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.\r\n  * @param huart: uart handle\r\n  * @retval HAL status\r\n  */\r\nvoid HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)\r\n{\r\n  __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);\r\n}\r\n\r\n\r\n\r\n/**\r\n  * @brief return the UART state\r\n  * @param huart: uart handle\r\n  * @retval HAL state\r\n  */\r\nHAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)\r\n{\r\n  uint32_t temp1= 0x00U, temp2 = 0x00U;\r\n  temp1 = huart->gState;\r\n  temp2 = huart->RxState;\r\n\r\n  return (HAL_UART_StateTypeDef)(temp1 | temp2);\r\n}\r\n\r\n/**\r\n* @brief  Return the UART error code\r\n* @param  huart : pointer to a UART_HandleTypeDef structure that contains\r\n  *              the configuration information for the specified UART.\r\n* @retval UART Error Code\r\n*/\r\nuint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)\r\n{\r\n  return huart->ErrorCode;\r\n}\r\n\r\n/**\r\n  * @brief Configure the UART peripheral\r\n  * @param huart: uart handle\r\n  * @retval None\r\n  */\r\nHAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)\r\n{\r\n  uint32_t tmpreg                     = 0x00000000U;\r\n  UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED;\r\n  uint16_t brrtemp                    = 0x0000U;\r\n  uint16_t usartdiv                   = 0x0000U;\r\n  HAL_StatusTypeDef ret               = HAL_OK;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));\r\n  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));\r\n  assert_param(IS_UART_STOPBITS(huart->Init.StopBits));\r\n  assert_param(IS_UART_PARITY(huart->Init.Parity));\r\n  assert_param(IS_UART_MODE(huart->Init.Mode));\r\n  assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));\r\n  assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));\r\n\r\n\r\n  /*-------------------------- USART CR1 Configuration -----------------------*/\r\n  /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure\r\n   *  the UART Word Length, Parity, Mode and oversampling:\r\n   *  set the M bits according to huart->Init.WordLength value\r\n   *  set PCE and PS bits according to huart->Init.Parity value\r\n   *  set TE and RE bits according to huart->Init.Mode value\r\n   *  set OVER8 bit according to huart->Init.OverSampling value */\r\n  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;\r\n  MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);\r\n\r\n  /*-------------------------- USART CR2 Configuration -----------------------*/\r\n  /* Configure the UART Stop Bits: Set STOP[13:12] bits according\r\n   * to huart->Init.StopBits value */\r\n  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);\r\n\r\n  /*-------------------------- USART CR3 Configuration -----------------------*/\r\n  /* Configure\r\n   * - UART HardWare Flow Control: set CTSE and RTSE bits according\r\n   *   to huart->Init.HwFlowCtl value\r\n   * - one-bit sampling method versus three samples' majority rule according\r\n   *   to huart->Init.OneBitSampling */\r\n  tmpreg = (uint32_t)huart->Init.HwFlowCtl | huart->Init.OneBitSampling ;\r\n  MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg);\r\n\r\n  /*-------------------------- USART BRR Configuration -----------------------*/\r\n  UART_GETCLOCKSOURCE(huart, clocksource);\r\n\r\n  /* Check UART Over Sampling to set Baud Rate Register */\r\n  if (huart->Init.OverSampling == UART_OVERSAMPLING_8)\r\n  {\r\n    switch (clocksource)\r\n    {\r\n    case UART_CLOCKSOURCE_PCLK1:\r\n        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));\r\n      break;\r\n    case UART_CLOCKSOURCE_PCLK2:\r\n        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));\r\n      break;\r\n    case UART_CLOCKSOURCE_HSI:\r\n        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));\r\n      break;\r\n    case UART_CLOCKSOURCE_SYSCLK:\r\n        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));\r\n      break;\r\n    case UART_CLOCKSOURCE_LSE:\r\n        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));\r\n      break;\r\n      case UART_CLOCKSOURCE_UNDEFINED:\r\n    default:\r\n        ret = HAL_ERROR;\r\n      break;\r\n    }\r\n\r\n    brrtemp = usartdiv & 0xFFF0U;\r\n    brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);\r\n    huart->Instance->BRR = brrtemp;\r\n  }\r\n  else\r\n  {\r\n    switch (clocksource)\r\n    {\r\n    case UART_CLOCKSOURCE_PCLK1:\r\n        huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));\r\n      break;\r\n    case UART_CLOCKSOURCE_PCLK2:\r\n        huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));\r\n      break;\r\n    case UART_CLOCKSOURCE_HSI:\r\n        huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));\r\n      break;\r\n    case UART_CLOCKSOURCE_SYSCLK:\r\n        huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));\r\n      break;\r\n    case UART_CLOCKSOURCE_LSE:\r\n        huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));\r\n      break;\r\n      case UART_CLOCKSOURCE_UNDEFINED:\r\n    default:\r\n        ret = HAL_ERROR;\r\n      break;\r\n    }\r\n  }\r\n\r\n  return ret;\r\n\r\n}\r\n\r\n\r\n/**\r\n  * @brief Configure the UART peripheral advanced features\r\n  * @param huart: uart handle\r\n  * @retval None\r\n  */\r\nvoid UART_AdvFeatureConfig(UART_HandleTypeDef *huart)\r\n{\r\n  /* Check whether the set of advanced features to configure is properly set */\r\n  assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));\r\n\r\n  /* if required, configure TX pin active level inversion */\r\n  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))\r\n  {\r\n    assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));\r\n    MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);\r\n  }\r\n\r\n  /* if required, configure RX pin active level inversion */\r\n  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))\r\n  {\r\n    assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));\r\n    MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);\r\n  }\r\n\r\n  /* if required, configure data inversion */\r\n  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))\r\n  {\r\n    assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));\r\n    MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);\r\n  }\r\n\r\n  /* if required, configure RX/TX pins swap */\r\n  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))\r\n  {\r\n    assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));\r\n    MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);\r\n  }\r\n\r\n  /* if required, configure RX overrun detection disabling */\r\n  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))\r\n  {\r\n    assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));\r\n    MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);\r\n  }\r\n\r\n  /* if required, configure DMA disabling on reception error */\r\n  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))\r\n  {\r\n    assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));\r\n    MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);\r\n  }\r\n\r\n  /* if required, configure auto Baud rate detection scheme */\r\n  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))\r\n  {\r\n    assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));\r\n    MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);\r\n    /* set auto Baudrate detection parameters if detection is enabled */\r\n    if(huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)\r\n    {\r\n      assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));\r\n      MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);\r\n    }\r\n  }\r\n\r\n  /* if required, configure MSB first on communication line */\r\n  if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))\r\n  {\r\n    assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));\r\n    MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);\r\n  }\r\n}\r\n\r\n\r\n\r\n/**\r\n  * @brief Check the UART Idle State\r\n  * @param huart: uart handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)\r\n{\r\n  uint32_t tickstart = 0U;\r\n\r\n  /* Initialize the UART ErrorCode */\r\n  huart->ErrorCode = HAL_UART_ERROR_NONE;\r\n\r\n  /* Init tickstart for timeout managment*/\r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Check if the Transmitter is enabled */\r\n  if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)\r\n  {\r\n    /* Wait until TEACK flag is set */\r\n    if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)\r\n    {\r\n      /* Timeout Occurred */\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  /* Check if the Receiver is enabled */\r\n  if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)\r\n  {\r\n    /* Wait until REACK flag is set */\r\n    if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)\r\n    {\r\n      /* Timeout Occurred */\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n\r\n  /* Initialize the UART State */\r\n  huart->gState= HAL_UART_STATE_READY;\r\n  huart->RxState= HAL_UART_STATE_READY;\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(huart);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Enables the UART transmitter and disables the UART receiver.\r\n  * @param  huart: UART handle\r\n  * @retval HAL status\r\n  * @retval None\r\n  */\r\nHAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(huart);\r\n  huart->gState = HAL_UART_STATE_BUSY;\r\n\r\n  /* Clear TE and RE bits */\r\n  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));\r\n  /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */\r\n  SET_BIT(huart->Instance->CR1, USART_CR1_TE);\r\n\r\n  huart->gState= HAL_UART_STATE_READY;\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(huart);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Enables the UART receiver and disables the UART transmitter.\r\n  * @param  huart: UART handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(huart);\r\n  huart->gState = HAL_UART_STATE_BUSY;\r\n\r\n  /* Clear TE and RE bits */\r\n  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));\r\n  /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */\r\n  SET_BIT(huart->Instance->CR1, USART_CR1_RE);\r\n\r\n  huart->gState = HAL_UART_STATE_READY;\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(huart);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Transmits break characters.\r\n  * @param  huart: UART handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_UART_INSTANCE(huart->Instance));\r\n\r\n  /* Process Locked */\r\n  __HAL_LOCK(huart);\r\n\r\n  huart->gState = HAL_UART_STATE_BUSY;\r\n\r\n  /* Send break characters */\r\n  SET_BIT(huart->Instance->RQR, UART_SENDBREAK_REQUEST);\r\n\r\n  huart->gState = HAL_UART_STATE_READY;\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(huart);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief By default in multiprocessor mode, when the wake up method is set\r\n  *        to address mark, the UART handles only 4-bit long addresses detection;\r\n  *        this API allows to enable longer addresses detection (6-, 7- or 8-bit\r\n  *        long).\r\n  * @note  Addresses detection lengths are: 6-bit address detection in 7-bit data mode,\r\n  *        7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.\r\n  * @param huart: UART handle.\r\n  * @param AddressLength: this parameter can be one of the following values:\r\n  *          @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address\r\n  *          @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)\r\n{\r\n  /* Check the UART handle allocation */\r\n  if(huart == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the address length parameter */\r\n  assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));\r\n\r\n  huart->gState = HAL_UART_STATE_BUSY;\r\n\r\n  /* Disable the Peripheral */\r\n  __HAL_UART_DISABLE(huart);\r\n\r\n  /* Set the address length */\r\n  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);\r\n\r\n  /* Enable the Peripheral */\r\n  __HAL_UART_ENABLE(huart);\r\n\r\n  /* TEACK and/or REACK to check before moving huart->gState to Ready */\r\n  return (UART_CheckIdleState(huart));\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_UART_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_usart.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_usart.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   USART HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter\r\n  *          Peripheral (USART).\r\n  *           + Initialization and de-initialization functions\r\n  *           + IO operation functions\r\n  *           + Peripheral Control functions\r\n  *\r\n  @verbatim\r\n  ===============================================================================\r\n                        ##### How to use this driver #####\r\n ===============================================================================\r\n    [..]\r\n      The USART HAL driver can be used as follows:\r\n\r\n      (#) Declare a USART_HandleTypeDef handle structure.\r\n      (#) Initialize the USART low level resources by implement the HAL_USART_MspInit ()API:\r\n          (##) Enable the USARTx interface clock.\r\n          (##) USART pins configuration:\r\n            (+++) Enable the clock for the USART GPIOs.\r\n            (+++) Configure these USART pins as alternate function pull-up.\r\n          (##) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),\r\n                HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):\r\n            (+++) Configure the USARTx interrupt priority.\r\n            (+++) Enable the NVIC USART IRQ handle.\r\n            (+++) The specific USART interrupts (Transmission complete interrupt, \r\n                  RXNE interrupt and Error Interrupts) will be managed using the macros\r\n                  __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.\r\n          (##) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()\r\n               HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):\r\n            (+++) Declare a DMA handle structure for the Tx/Rx stream.\r\n            (+++) Enable the DMAx interface clock.\r\n            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.                \r\n            (+++) Configure the DMA Tx/Rx Stream.\r\n            (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.\r\n            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.\r\n\r\n      (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware \r\n          flow control and Mode(Receiver/Transmitter) in the husart Init structure.\r\n\r\n      (#) Initialize the USART registers by calling the HAL_USART_Init() API:\r\n          (++) These API's configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)\r\n               by calling the customed HAL_USART_MspInit(&husart) API.\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup USART USART\r\n  * @brief HAL USART Synchronous module driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_USART_MODULE_ENABLED\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/** @addtogroup USART_Private_Constants\r\n  * @{\r\n  */\r\n#define DUMMY_DATA                             ((uint16_t) 0xFFFFU)\r\n#define TEACK_REACK_TIMEOUT                    ((uint32_t) 1000U)\r\n#define USART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \\\r\n                                     USART_CR1_TE | USART_CR1_RE  | USART_CR1_OVER8))\r\n#define USART_CR2_FIELDS       ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \\\r\n                            USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP))\r\n/**\r\n  * @}\r\n  */\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n/** @addtogroup USART_Private_Functions\r\n  * @{\r\n  */\r\nstatic void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);\r\nstatic void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);\r\nstatic void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);\r\nstatic void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);\r\nstatic void USART_DMAError(DMA_HandleTypeDef *hdma);\r\nstatic void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);\r\nstatic void USART_EndTxTransfer(USART_HandleTypeDef *husart);\r\nstatic void USART_EndRxTransfer(USART_HandleTypeDef *husart);\r\nstatic HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);\r\nstatic HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);\r\nstatic HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);\r\nstatic HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);\r\nstatic HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);\r\nstatic HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);\r\nstatic HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @defgroup USART_Exported_Functions USART Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup USART_Exported_Functions_Group1 USART Initialization and de-initialization functions\r\n  *  @brief    Initialization and Configuration functions\r\n  *\r\n@verbatim\r\n ===============================================================================\r\n            ##### Initialization and Configuration functions #####\r\n ===============================================================================\r\n    [..]\r\n    This subsection provides a set of functions allowing to initialize the USART\r\n    in asynchronous and in synchronous modes.\r\n      (+) For the asynchronous mode only these parameters can be configured:\r\n        (++) Baud Rate\r\n        (++) Word Length\r\n        (++) Stop Bit\r\n        (++) Parity: If the parity is enabled, then the MSB bit of the data written\r\n             in the data register is transmitted but is changed by the parity bit.\r\n        (++) USART polarity\r\n        (++) USART phase\r\n        (++) USART LastBit\r\n        (++) Receiver/transmitter modes\r\n\r\n    [..]\r\n    The HAL_USART_Init() function follows the USART  synchronous configuration\r\n    procedure (details for the procedure are available in reference manual).\r\n\r\n@endverbatim\r\n\r\n   Depending on the frame length defined by the M1 and M0 bits (7-bit,\r\n   8-bit or 9-bit), the possible USART frame formats are as listed in the\r\n   following table:\r\n\r\n     +---------------------------------------------------------------+\r\n     | M1M0 bits |  PCE bit  |            USART frame                |\r\n     |-----------------------|---------------------------------------|\r\n     |     10    |     0     |    | SB | 7-bit data | STB |          |\r\n     |-----------|-----------|---------------------------------------|\r\n     |     10    |     1     |    | SB | 6-bit data | PB | STB |     |\r\n     +---------------------------------------------------------------+\r\n\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the USART mode according to the specified\r\n  *         parameters in the USART_InitTypeDef and create the associated handle.\r\n  * @param husart: USART handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)\r\n{\r\n  /* Check the USART handle allocation */\r\n  if(husart == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_USART_INSTANCE(husart->Instance));\r\n\r\n  if(husart->State == HAL_USART_STATE_RESET)\r\n  {\r\n    /* Allocate lock resource and initialize it */\r\n    husart->Lock = HAL_UNLOCKED;\r\n    /* Init the low level hardware : GPIO, CLOCK */\r\n    HAL_USART_MspInit(husart);\r\n  }\r\n\r\n  husart->State = HAL_USART_STATE_BUSY;\r\n\r\n  /* Disable the Peripheral */\r\n  __HAL_USART_DISABLE(husart);\r\n\r\n  /* Set the Usart Communication parameters */\r\n  if (USART_SetConfig(husart) == HAL_ERROR)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* In Synchronous mode, the following bits must be kept cleared:\r\n  - LINEN bit in the USART_CR2 register\r\n  - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/\r\n  CLEAR_BIT(husart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\r\n  CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));\r\n\r\n  /* Enable the Peripheral */\r\n  __HAL_USART_ENABLE(husart);\r\n\r\n  /* TEACK and/or REACK to check before moving husart->State to Ready */\r\n  return (USART_CheckIdleState(husart));\r\n}\r\n\r\n/**\r\n  * @brief DeInitializes the USART peripheral\r\n  * @param husart: USART handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)\r\n{\r\n   /* Check the USART handle allocation */\r\n  if(husart == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_USART_INSTANCE(husart->Instance));\r\n\r\n  husart->State = HAL_USART_STATE_BUSY;\r\n\r\n  husart->Instance->CR1 = 0x0U;\r\n  husart->Instance->CR2 = 0x0U;\r\n  husart->Instance->CR3 = 0x0U;\r\n\r\n  /* DeInit the low level hardware */\r\n  HAL_USART_MspDeInit(husart);\r\n\r\n  husart->ErrorCode = HAL_USART_ERROR_NONE;\r\n  husart->State = HAL_USART_STATE_RESET;\r\n\r\n  /* Process Unlock */\r\n  __HAL_UNLOCK(husart);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief USART MSP Init\r\n  * @param husart: USART handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(husart);\r\n \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_USART_MspInit can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief USART MSP DeInit\r\n  * @param husart: USART handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(husart);\r\n \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_USART_MspDeInit can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USART_Exported_Functions_Group2 IO operation functions \r\n  *  @brief   USART Transmit and Receive functions \r\n  *\r\n@verbatim\r\n ===============================================================================\r\n                      ##### IO operation functions #####\r\n ===============================================================================\r\n    This subsection provides a set of functions allowing to manage the USART synchronous\r\n    data transfers.\r\n\r\n    [..] The USART supports master mode only: it cannot receive or send data related to an input\r\n         clock (SCLK is always an output).\r\n\r\n    (#) There are two mode of transfer:\r\n       (++) Blocking mode: The communication is performed in polling mode.\r\n            The HAL status of all data processing is returned by the same function\r\n            after finishing transfer.\r\n       (++) No-Blocking mode: The communication is performed using Interrupts\r\n           or DMA, These API's return the HAL status.\r\n           The end of the data processing will be indicated through the\r\n           dedicated USART IRQ when using Interrupt mode or the DMA IRQ when\r\n           using DMA mode.\r\n           The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks\r\n           will be executed respectively at the end of the transmit or Receive process\r\n           The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected\r\n\r\n    (#) Blocking mode API's are :\r\n        (++) HAL_USART_Transmit()in simplex mode\r\n        (++) HAL_USART_Receive() in full duplex receive only\r\n        (++) HAL_USART_TransmitReceive() in full duplex mode\r\n\r\n    (#) Non-Blocking mode API's with Interrupt are :\r\n        (++) HAL_USART_Transmit_IT()in simplex mode\r\n        (++) HAL_USART_Receive_IT() in full duplex receive only\r\n        (++) HAL_USART_TransmitReceive_IT()in full duplex mode\r\n        (++) HAL_USART_IRQHandler()\r\n\r\n    (#) No-Blocking mode functions with DMA are :\r\n        (++) HAL_USART_Transmit_DMA()in simplex mode\r\n        (++) HAL_USART_Receive_DMA() in full duplex receive only\r\n        (++) HAL_USART_TransmitReceive_DMA() in full duplex mode\r\n        (++) HAL_USART_DMAPause()\r\n        (++) HAL_USART_DMAResume()\r\n        (++) HAL_USART_DMAStop()\r\n\r\n    (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:\r\n        (++) HAL_USART_TxCpltCallback()\r\n        (++) HAL_USART_RxCpltCallback()\r\n        (++) HAL_USART_TxHalfCpltCallback()\r\n        (++) HAL_USART_RxHalfCpltCallback()\r\n        (++) HAL_USART_ErrorCallback()\r\n        (++) HAL_USART_TxRxCpltCallback()\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Simplex Send an amount of data in blocking mode\r\n  * @param  husart: USART handle\r\n  * @param pTxData: pointer to data buffer\r\n  * @param Size: amount of data to be sent\r\n  * @param Timeout : Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)\r\n{\r\n  uint16_t* tmp;\r\n  uint32_t tickstart = 0U;\r\n\r\n  if(husart->State == HAL_USART_STATE_READY)\r\n  {\r\n    if((pTxData == NULL) || (Size == 0U))\r\n    {\r\n      return  HAL_ERROR;\r\n    }\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(husart);\r\n\r\n    husart->ErrorCode = HAL_USART_ERROR_NONE;\r\n    husart->State = HAL_USART_STATE_BUSY_TX;\r\n    \r\n    /* Init tickstart for timeout managment*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    husart->TxXferSize = Size;\r\n    husart->TxXferCount = Size;\r\n\r\n    /* Check the remaining data to be sent */\r\n    while(husart->TxXferCount > 0U)\r\n    {\r\n      husart->TxXferCount--;\r\n      if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)\r\n        {\r\n          return HAL_TIMEOUT;\r\n        }\r\n      if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r\n      {\r\n        tmp = (uint16_t*) pTxData;\r\n        husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);\r\n        pTxData += 2;\r\n      }\r\n      else\r\n      {\r\n        husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFFU);\r\n      }\r\n    }\r\n\r\n    if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n\r\n    husart->State = HAL_USART_STATE_READY;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(husart);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Receive an amount of data in blocking mode\r\n  * @note To receive synchronous data, dummy data are simultaneously transmitted\r\n  * @param husart: USART handle\r\n  * @param pRxData: pointer to data buffer\r\n  * @param Size: amount of data to be received\r\n  * @param Timeout : Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)\r\n{\r\n  uint16_t* tmp;\r\n  uint16_t uhMask;\r\n  uint32_t tickstart = 0U;\r\n\r\n  if(husart->State == HAL_USART_STATE_READY)\r\n  {\r\n    if((pRxData == NULL) || (Size == 0U))\r\n    {\r\n      return  HAL_ERROR;\r\n    }\r\n    /* Process Locked */\r\n    __HAL_LOCK(husart);\r\n\r\n    husart->ErrorCode = HAL_USART_ERROR_NONE;\r\n    husart->State = HAL_USART_STATE_BUSY_RX;\r\n\t\r\n\t/* Init tickstart for timeout managment*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    husart->RxXferSize = Size;\r\n    husart->RxXferCount = Size;\r\n\r\n    /* Computation of USART mask to apply to RDR register */\r\n    __HAL_USART_MASK_COMPUTATION(husart);\r\n    uhMask = husart->Mask;\r\n\r\n    /* as long as data have to be received */\r\n    while(husart->RxXferCount > 0U)\r\n    {\r\n      husart->RxXferCount--;\r\n\r\n      /* Wait until TC flag is set to send dummy byte in order to generate the\r\n      * clock for the slave to send data.\r\n       * Whatever the frame length (7, 8 or 9-bit long), the same dummy value\r\n       * can be written for all the cases. */\r\n      if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n      husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x0FFU);\r\n\r\n      /* Wait for RXNE Flag */\r\n      if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n\r\n      if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r\n      {\r\n        tmp = (uint16_t*) pRxData ;\r\n        *tmp = (uint16_t)(husart->Instance->RDR & uhMask);\r\n        pRxData +=2;\r\n      }\r\n      else\r\n      {\r\n        *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);\r\n      }\r\n    }\r\n\r\n    husart->State = HAL_USART_STATE_READY;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(husart);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Full-Duplex Send and Receive an amount of data in blocking mode\r\n  * @param husart: USART handle\r\n  * @param pTxData: pointer to TX data buffer\r\n  * @param pRxData: pointer to RX data buffer\r\n  * @param Size: amount of data to be sent (same amount to be received)\r\n  * @param Timeout : Timeout duration\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)\r\n{\r\n  uint16_t* tmp;\r\n  uint16_t uhMask;\r\n  uint32_t tickstart = 0U;\r\n\r\n  if(husart->State == HAL_USART_STATE_READY)\r\n  {\r\n    if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))\r\n    {\r\n      return  HAL_ERROR;\r\n    }\r\n    /* Process Locked */\r\n    __HAL_LOCK(husart);\r\n\r\n    husart->ErrorCode = HAL_USART_ERROR_NONE;\r\n    husart->State = HAL_USART_STATE_BUSY_RX;\r\n\t\r\n\t/* Init tickstart for timeout managment*/\r\n    tickstart = HAL_GetTick();\r\n\r\n    husart->RxXferSize = Size;\r\n    husart->TxXferSize = Size;\r\n    husart->TxXferCount = Size;\r\n    husart->RxXferCount = Size;\r\n\r\n    /* Computation of USART mask to apply to RDR register */\r\n    __HAL_USART_MASK_COMPUTATION(husart);\r\n    uhMask = husart->Mask;\r\n\r\n    /* Check the remain data to be sent */\r\n    while(husart->TxXferCount > 0)\r\n    {\r\n      husart->TxXferCount--;\r\n      husart->RxXferCount--;\r\n\r\n      /* Wait until TC flag is set to send data */\r\n      if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n      if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r\n      {\r\n        tmp = (uint16_t*) pTxData;\r\n        husart->Instance->TDR = (*tmp & uhMask);\r\n        pTxData += 2;\r\n      }\r\n      else\r\n      {\r\n        husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask);\r\n      }\r\n\r\n      /* Wait for RXNE Flag */\r\n      if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n\r\n      if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r\n      {\r\n        tmp = (uint16_t*) pRxData ;\r\n        *tmp = (uint16_t)(husart->Instance->RDR & uhMask);\r\n        pRxData +=2U;\r\n      }\r\n      else\r\n      {\r\n        *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);\r\n      }\r\n    }\r\n\r\n    husart->State = HAL_USART_STATE_READY;\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(husart);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Send an amount of data in interrupt mode\r\n  * @param  husart: USART handle\r\n  * @param pTxData: pointer to data buffer\r\n  * @param Size: amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)\r\n{\r\n  if(husart->State == HAL_USART_STATE_READY)\r\n  {\r\n    if((pTxData == NULL ) || (Size == 0U))\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(husart);\r\n\r\n    husart->pTxBuffPtr = pTxData;\r\n    husart->TxXferSize = Size;\r\n    husart->TxXferCount = Size;\r\n\r\n    husart->ErrorCode = HAL_USART_ERROR_NONE;\r\n    husart->State = HAL_USART_STATE_BUSY_TX;\r\n\r\n    /* The USART Error Interrupts: (Frame error, noise error, overrun error)\r\n    are not managed by the USART Transmit Process to avoid the overrun interrupt\r\n    when the usart mode is configured for transmit and receive \"USART_MODE_TX_RX\"\r\n    to benefit for the frame error and noise interrupts the usart mode should be\r\n    configured only for transmit \"USART_MODE_TX\" */\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(husart);\r\n\r\n    /* Enable the USART Transmit Data Register Empty Interrupt */\r\n    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Receive an amount of data in blocking mode\r\n  *        To receive synchronous data, dummy data are simultaneously transmitted\r\n  * @param husart: USART handle\r\n  * @param pRxData: pointer to data buffer\r\n  * @param Size: amount of data to be received\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)\r\n{\r\n  if(husart->State == HAL_USART_STATE_READY)\r\n  {\r\n    if((pRxData == NULL ) || (Size == 0U))\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n    /* Process Locked */\r\n    __HAL_LOCK(husart);\r\n\r\n    husart->pRxBuffPtr = pRxData;\r\n    husart->RxXferSize = Size;\r\n    husart->RxXferCount = Size;\r\n\r\n    __HAL_USART_MASK_COMPUTATION(husart);\r\n\r\n    husart->ErrorCode = HAL_USART_ERROR_NONE;\r\n    husart->State = HAL_USART_STATE_BUSY_RX;\r\n\r\n    /* Enable the USART Parity Error Interrupt */\r\n    SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);\r\n\r\n    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r\n    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);\r\n\r\n    /* Enable the USART Data Register not empty Interrupt */\r\n    SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(husart);\r\n\r\n\r\n    /* Send dummy byte in order to generate the clock for the Slave to send the next data */\r\n    if(husart->Init.WordLength == USART_WORDLENGTH_9B)\r\n    {\r\n      husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x01FFU);\r\n    }\r\n    else\r\n    {\r\n      husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x00FFU);\r\n    }\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Full-Duplex Send and Receive an amount of data in interrupt mode\r\n  * @param husart: USART handle\r\n  * @param pTxData: pointer to TX data buffer\r\n  * @param pRxData: pointer to RX data buffer\r\n  * @param Size: amount of data to be sent (same amount to be received)\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,  uint16_t Size)\r\n{\r\n\r\n  if(husart->State == HAL_USART_STATE_READY)\r\n  {\r\n    if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n    /* Process Locked */\r\n    __HAL_LOCK(husart);\r\n\r\n    husart->pRxBuffPtr = pRxData;\r\n    husart->RxXferSize = Size;\r\n    husart->RxXferCount = Size;\r\n    husart->pTxBuffPtr = pTxData;\r\n    husart->TxXferSize = Size;\r\n    husart->TxXferCount = Size;\r\n\r\n    /* Computation of USART mask to apply to RDR register */\r\n    __HAL_USART_MASK_COMPUTATION(husart);\r\n\r\n    husart->ErrorCode = HAL_USART_ERROR_NONE;\r\n    husart->State = HAL_USART_STATE_BUSY_TX_RX;\r\n\r\n    /* Enable the USART Data Register not empty Interrupt */\r\n    SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);\r\n\r\n    /* Enable the USART Parity Error Interrupt */\r\n    SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);\r\n\r\n    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r\n    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);\r\n\r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(husart);\r\n\r\n    /* Enable the USART Transmit Data Register Empty Interrupt */\r\n    __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Send an amount of data in DMA mode\r\n  * @param husart: USART handle\r\n  * @param pTxData: pointer to data buffer\r\n  * @param Size: amount of data to be sent\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)\r\n{\r\n  uint32_t *tmp;\r\n\r\n  if(husart->State == HAL_USART_STATE_READY)\r\n  {\r\n    if((pTxData == NULL ) || (Size == 0U))\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n    /* Process Locked */\r\n    __HAL_LOCK(husart);\r\n\r\n    husart->pTxBuffPtr = pTxData;\r\n    husart->TxXferSize = Size;\r\n    husart->TxXferCount = Size;\r\n\r\n    husart->ErrorCode = HAL_USART_ERROR_NONE;\r\n    husart->State = HAL_USART_STATE_BUSY_TX;\r\n\r\n    /* Set the USART DMA transfer complete callback */\r\n    husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;\r\n\r\n    /* Set the USART DMA Half transfer complete callback */\r\n    husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;\r\n\r\n    /* Set the DMA error callback */\r\n    husart->hdmatx->XferErrorCallback = USART_DMAError;\r\n\r\n    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r\n    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);\r\n    SET_BIT(husart->Instance->ISR, (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE | USART_ISR_ORE));\r\n  \r\n    /* Enable the USART transmit DMA channel */\r\n    tmp = (uint32_t*)&pTxData;\r\n    HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);\r\n\r\n    /* Clear the TC flag in the SR register by writing 0 to it */\r\n    __HAL_USART_CLEAR_IT(husart, USART_FLAG_TC);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(husart);\r\n\r\n    /* Enable the DMA transfer for transmit request by setting the DMAT bit\r\n       in the USART CR3 register */\r\n    SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Receive an amount of data in DMA mode\r\n  * @param husart: USART handle\r\n  * @param pRxData: pointer to data buffer\r\n  * @param Size: amount of data to be received\r\n  * @note   When the USART parity is enabled (PCE = 1), the received data contain\r\n  *         the parity bit (MSB position)\r\n  * @retval HAL status\r\n  * @note The USART DMA transmit stream must be configured in order to generate the clock for the slave.\r\n  */\r\nHAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)\r\n{\r\n  uint32_t *tmp;\r\n\r\n  if(husart->State == HAL_USART_STATE_READY)\r\n  {\r\n    if((pRxData == NULL ) || (Size == 0U))\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n\r\n    /* Process Locked */\r\n    __HAL_LOCK(husart);\r\n\r\n    husart->pRxBuffPtr = pRxData;\r\n    husart->RxXferSize = Size;\r\n    husart->pTxBuffPtr = pRxData;\r\n    husart->TxXferSize = Size;\r\n\r\n    husart->ErrorCode = HAL_USART_ERROR_NONE;\r\n    husart->State = HAL_USART_STATE_BUSY_RX;\r\n\r\n    /* Set the USART DMA Rx transfer complete callback */\r\n    husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;\r\n\r\n    /* Set the USART DMA Half transfer complete callback */\r\n    husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;\r\n\r\n    /* Set the USART DMA Rx transfer error callback */\r\n    husart->hdmarx->XferErrorCallback = USART_DMAError;\r\n    \r\n    /* Set the DMA abort callback */\r\n    husart->hdmatx->XferAbortCallback = NULL;\r\n\t\r\n\t/* Set the USART Tx DMA transfer complete callback as NULL because the communication closing\r\n    is performed in DMA reception complete callback  */\r\n    husart->hdmatx->XferHalfCpltCallback = NULL;\r\n    husart->hdmatx->XferCpltCallback = NULL;\r\n    \r\n    /* Set the DMA error callback */\r\n    husart->hdmatx->XferErrorCallback = USART_DMAError;\r\n\r\n    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r\n    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);\r\n    SET_BIT(husart->Instance->ISR, (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE | USART_ISR_ORE));\r\n\r\n    /* Enable the USART receive DMA channel */\r\n    tmp = (uint32_t*)&pRxData;\r\n    HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);\r\n\r\n    /* Enable the USART transmit DMA channel: the transmit stream is used in order\r\n       to generate in the non-blocking mode the clock to the slave device,\r\n       this mode isn't a simplex receive mode but a full-duplex receive mode */\r\n    HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(husart);\r\n    \r\n    /* Enable the USART Parity Error Interrupt */\r\n    SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);\r\n    \r\n    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r\n    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);\r\n\r\n    /* Enable the DMA transfer for the receiver request by setting the DMAR bit\r\n       in the USART CR3 register */\r\n    SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);\r\n\r\n    /* Enable the DMA transfer for transmit request by setting the DMAT bit\r\n       in the USART CR3 register */\r\n    SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r\n\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Full-Duplex Transmit Receive an amount of data in non blocking mode \r\n  * @param husart: USART handle\r\n  * @param pTxData: pointer to TX data buffer\r\n  * @param pRxData: pointer to RX data buffer\r\n  * @param Size: amount of data to be received/sent\r\n  * @note   When the USART parity is enabled (PCE = 1) the data received contain the parity bit.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)\r\n{\r\n  uint32_t *tmp;\r\n\r\n  if(husart->State == HAL_USART_STATE_READY)\r\n  {\r\n    if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))\r\n    {\r\n      return HAL_ERROR;\r\n    }\r\n    /* Process Locked */\r\n    __HAL_LOCK(husart);\r\n\r\n    husart->pRxBuffPtr = pRxData;\r\n    husart->RxXferSize = Size;\r\n    husart->pTxBuffPtr = pTxData;\r\n    husart->TxXferSize = Size;\r\n\r\n    husart->ErrorCode = HAL_USART_ERROR_NONE;\r\n    husart->State = HAL_USART_STATE_BUSY_TX_RX;\r\n\r\n    /* Set the USART DMA Rx transfer complete callback */\r\n    husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;\r\n\r\n    /* Set the USART DMA Half transfer complete callback */\r\n    husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;\r\n\r\n    /* Set the USART DMA Tx transfer complete callback */\r\n    husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;\r\n\r\n    /* Set the USART DMA Half transfer complete callback */\r\n    husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;\r\n\r\n    /* Set the USART DMA Tx transfer error callback */\r\n    husart->hdmatx->XferErrorCallback = USART_DMAError;\r\n\r\n    /* Set the USART DMA Rx transfer error callback */\r\n    husart->hdmarx->XferErrorCallback = USART_DMAError;\r\n\r\n    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r\n    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);\r\n    SET_BIT(husart->Instance->ISR, (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE | USART_ISR_ORE));\r\n\r\n    /* Enable the USART receive DMA channel */\r\n    tmp = (uint32_t*)&pRxData;\r\n    HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);\r\n\r\n    /* Enable the USART transmit DMA channel */\r\n    tmp = (uint32_t*)&pTxData;\r\n    HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);\r\n\r\n    /* Clear the TC flag in the SR register by writing 0 to it */\r\n    __HAL_USART_CLEAR_IT(husart, USART_FLAG_TC);\r\n    \r\n    /* Process Unlocked */\r\n    __HAL_UNLOCK(husart);\r\n    \r\n    /* Enable the USART Parity Error Interrupt */\r\n    SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);\r\n    \r\n    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r\n    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);\r\n\r\n    /* Enable the DMA transfer for the receiver request by setting the DMAR bit\r\n       in the USART CR3 register */\r\n    SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);\r\n\r\n    /* Enable the DMA transfer for transmit request by setting the DMAT bit\r\n       in the USART CR3 register */\r\n    SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Pauses the DMA Transfer.\r\n  * @param husart: USART handle\r\n  * @retval None\r\n  */\r\nHAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(husart);\r\n\r\n  if(husart->State == HAL_USART_STATE_BUSY_TX)\r\n  {\r\n    /* Disable the USART DMA Tx request */\r\n    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r\n  }\r\n  else if(husart->State == HAL_USART_STATE_BUSY_RX)\r\n  {\r\n    /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\r\n    CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r\n    CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);\r\n    /* Disable the USART DMA Rx request */\r\n    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);\r\n  }\r\n  else if(husart->State == HAL_USART_STATE_BUSY_TX_RX)\r\n  {\r\n    /* Disable the USART DMA Tx request */\r\n    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);\r\n    /* Disable the USART DMA Rx request */\r\n    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r\n  }\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(husart);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Resumes the DMA Transfer.\r\n  * @param husart: USART handle\r\n  * @retval None\r\n  */\r\nHAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)\r\n{\r\n  /* Process Locked */\r\n  __HAL_LOCK(husart);\r\n\r\n  if(husart->State == HAL_USART_STATE_BUSY_TX)\r\n  {\r\n    /* Enable the USART DMA Tx request */\r\n    SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r\n  }\r\n  else if(husart->State == HAL_USART_STATE_BUSY_RX)\r\n  {\r\n    /* Clear the Overrun flag before resuming the Rx transfer*/\r\n    __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);\r\n    \r\n    /* Reenable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\r\n    SET_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r\n    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);\r\n\r\n    /* Enable the USART DMA Rx request */\r\n    SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);\r\n  }\r\n  else if(husart->State == HAL_USART_STATE_BUSY_TX_RX)\r\n  {\r\n    /* Clear the Overrun flag before resuming the Rx transfer*/\r\n    __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);\r\n\r\n    /* Enable the USART DMA Rx request  before the DMA Tx request */\r\n    SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);\r\n\r\n    /* Enable the USART DMA Tx request */\r\n    SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r\n  }\r\n\r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(husart);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Stops the DMA Transfer.\r\n  * @param husart: USART handle\r\n  * @retval None\r\n  */\r\nHAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)\r\n{\r\n  /* The Lock is not implemented on this API to allow the user application\r\n     to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() /\r\n     HAL_USART_TxHalfCpltCallback / HAL_USART_RxHalfCpltCallback: \r\n     indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete  \r\n     interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of \r\n     the stream and the corresponding call back is executed. */\r\n\r\n  /* Stop USART DMA Tx request if ongoing */\r\n  if ((husart->State == HAL_USART_STATE_BUSY_TX) &&\r\n      (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)))\r\n  {\r\n    USART_EndTxTransfer(husart);\r\n    \r\n    /* Abort the USART DMA Tx channel */\r\n    if(husart->hdmatx != NULL)\r\n    {\r\n      HAL_DMA_Abort(husart->hdmatx);\r\n    }\r\n    \r\n    /* Disable the USART Tx DMA request */\r\n    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r\n  }\r\n  \r\n  /* Stop USART DMA Rx request if ongoing */\r\n  if ((husart->State == HAL_USART_STATE_BUSY_RX) &&\r\n      (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)))\r\n  {\r\n    USART_EndRxTransfer(husart);\r\n    \r\n    /* Abort the USART DMA Rx channel */\r\n    if(husart->hdmarx != NULL)\r\n    {\r\n      HAL_DMA_Abort(husart->hdmarx);\r\n    }\r\n    \r\n    /* Disable the USART Rx DMA request */\r\n    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);\r\n  }\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  This function handles USART interrupt request.\r\n  * @param  husart: USART handle\r\n  * @retval None\r\n  */\r\nvoid HAL_USART_IRQHandler(USART_HandleTypeDef *husart)\r\n{\r\n  uint32_t isrflags = READ_REG(husart->Instance->ISR);\r\n  uint32_t cr1its   = READ_REG(husart->Instance->CR1);\r\n  uint32_t cr3its   = READ_REG(husart->Instance->CR3);\r\n  uint32_t errorflags;\r\n  \r\n  /* If no error occurs */\r\n  errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));\r\n  if (errorflags == RESET)\r\n  {\r\n    /* USART in mode Receiver --------------------------------------------------*/\r\n    if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))\r\n    {\r\n      if(husart->State == HAL_USART_STATE_BUSY_RX)\r\n      {\r\n        USART_Receive_IT(husart);\r\n      }\r\n      else\r\n      {\r\n        USART_TransmitReceive_IT(husart);\r\n      }\r\n    }\r\n  }\r\n  \r\n  /* If some errors occur */\r\n  if((errorflags != RESET) && ((cr3its & (USART_CR3_EIE | USART_CR1_PEIE)) != RESET))\r\n  {\r\n    \r\n    /* USART parity error interrupt occurred ------------------------------------*/\r\n    if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))\r\n    {\r\n      __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF);\r\n      husart->ErrorCode |= HAL_USART_ERROR_PE;\r\n    }\r\n    \r\n    /* USART frame error interrupt occurred -------------------------------------*/\r\n    if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))\r\n    {\r\n      __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF);\r\n      husart->ErrorCode |= HAL_USART_ERROR_FE;\r\n    }\r\n    \r\n    /* USART noise error interrupt occurred -------------------------------------*/\r\n    if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))\r\n    {\r\n      __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF);\r\n      husart->ErrorCode |= HAL_USART_ERROR_NE;\r\n    }\r\n    \r\n    /* USART Over-Run interrupt occurred ----------------------------------------*/\r\n    if(((isrflags & USART_ISR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))\r\n    {\r\n      __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);\r\n      husart->ErrorCode |= HAL_USART_ERROR_ORE;\r\n    }\r\n    \r\n    /* Call USART Error Call back function if need be --------------------------*/\r\n    if(husart->ErrorCode != HAL_USART_ERROR_NONE)\r\n    {\r\n      /* USART in mode Receiver ---------------------------------------------------*/\r\n      if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))\r\n      {\r\n        USART_Receive_IT(husart);\r\n      }\r\n      \r\n      /* If Overrun error occurs, or if any error occurs in DMA mode reception,\r\n      consider error as blocking */\r\n      if (((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) ||\r\n          (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)))\r\n      {  \r\n        /* Blocking error : transfer is aborted\r\n        Set the USART state ready to be able to start again the process,\r\n        Disable Rx Interrupts, and disable Rx DMA request, if ongoing */\r\n        USART_EndRxTransfer(husart);\r\n        \r\n        /* Disable the USART DMA Rx request if enabled */\r\n        if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))\r\n        {\r\n          CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);\r\n          \r\n          /* Abort the USART DMA Rx channel */\r\n          if(husart->hdmarx != NULL)\r\n          {            \r\n            /* Set the USART DMA Abort callback : \r\n            will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */\r\n            husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;\r\n            \r\n            /* Abort DMA RX */\r\n            if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)\r\n            {\r\n              /* Call Directly husart->hdmarx->XferAbortCallback function in case of error */\r\n              husart->hdmarx->XferAbortCallback(husart->hdmarx);\r\n            }\r\n          }\r\n          else\r\n          {\r\n            /* Call user error callback */\r\n            HAL_USART_ErrorCallback(husart);\r\n          }\r\n        }\r\n        else\r\n        {\r\n          /* Call user error callback */\r\n          HAL_USART_ErrorCallback(husart);\r\n        }\r\n      }\r\n      else\r\n      {\r\n        /* Non Blocking error : transfer could go on. \r\n        Error is notified to user through user error callback */\r\n        HAL_USART_ErrorCallback(husart);\r\n        husart->ErrorCode = HAL_USART_ERROR_NONE;\r\n      }\r\n    }\r\n    return;\r\n    \r\n  } /* End if some error occurs */\r\n  \r\n  /* USART in mode Transmitter -----------------------------------------------*/\r\n  if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))\r\n  {\r\n    if(husart->State == HAL_USART_STATE_BUSY_TX)\r\n    {\r\n      USART_Transmit_IT(husart);\r\n    }\r\n    else\r\n    {\r\n      USART_TransmitReceive_IT(husart);\r\n    }\r\n    return;\r\n  }\r\n  \r\n  /* USART in mode Transmitter (transmission end) -----------------------------*/\r\n  if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))\r\n  {\r\n    USART_EndTransmit_IT(husart);\r\n    return;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief Tx Transfer completed callbacks\r\n  * @param husart: USART handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(husart);\r\n \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_USART_TxCpltCallback can be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @brief  Tx Half Transfer completed callbacks.\r\n  * @param  husart: USART handle\r\n  * @retval None\r\n  */\r\n __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(husart);\r\n \r\n  /* NOTE: This function should not be modified, when the callback is needed,\r\n           the HAL_USART_TxHalfCpltCallback can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief  Rx Transfer completed callbacks.\r\n  * @param  husart: USART handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(husart);\r\n \r\n  /* NOTE: This function should not be modified, when the callback is needed,\r\n           the HAL_USART_RxCpltCallback can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief Rx Half Transfer completed callbacks\r\n  * @param husart: usart handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(husart);\r\n \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_USART_RxHalfCpltCallback can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief Tx/Rx Transfers completed callback for the non-blocking process\r\n  * @param husart: USART handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(husart);\r\n \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_USART_TxRxCpltCallback can be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @brief USART error callbacks\r\n  * @param husart: USART handle\r\n  * @retval None\r\n  */\r\n__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(husart);\r\n \r\n  /* NOTE : This function should not be modified, when the callback is needed,\r\n            the HAL_USART_ErrorCallback can be implemented in the user file\r\n   */ \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Errors functions \r\n  *  @brief   USART State and Errors functions \r\n  *\r\n@verbatim   \r\n  ==============================================================================\r\n                  ##### Peripheral State and Errors functions #####\r\n  ==============================================================================  \r\n  [..]\r\n    This subsection provides a set of functions allowing to return the State of \r\n    USART communication\r\n    process, return Peripheral Errors occurred during communication process\r\n     (+) HAL_USART_GetState() API can be helpful to check in run-time the state \r\n         of the USART peripheral.\r\n     (+) HAL_USART_GetError() check in run-time errors that could be occurred during \r\n         communication. \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief return the USART state\r\n  * @param husart: USART handle\r\n  * @retval HAL state\r\n  */\r\nHAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)\r\n{\r\n  return husart->State;\r\n}\r\n\r\n/**\r\n  * @brief  Return the USART error code\r\n  * @param  husart : pointer to a USART_HandleTypeDef structure that contains\r\n  *              the configuration information for the specified USART.\r\n  * @retval USART Error Code\r\n  */\r\nuint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)\r\n{\r\n  return husart->ErrorCode;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n\r\n/**\r\n  * @brief  Simplex Send an amount of data in non-blocking mode.\r\n  * @note   Function called under interruption only, once\r\n  *         interruptions have been enabled by HAL_USART_Transmit_IT().\r\n  * @param  husart: USART handle\r\n  * @retval HAL status\r\n  * @note   The USART errors are not managed to avoid the overrun error.\r\n  */\r\nstatic HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)\r\n{\r\n  uint16_t* tmp;\r\n\r\n  if(husart->State == HAL_USART_STATE_BUSY_TX)\r\n  {\r\n\r\n    if(husart->TxXferCount == 0U)\r\n    {\r\n      /* Disable the USART Transmit data register empty interrupt */\r\n      __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);\r\n\r\n      /* Enable the USART Transmit Complete Interrupt */\r\n      __HAL_USART_ENABLE_IT(husart, USART_IT_TC);\r\n\r\n      return HAL_OK;\r\n    }\r\n    else\r\n    {\r\n      if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r\n      {\r\n        tmp = (uint16_t*) husart->pTxBuffPtr;\r\n        husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);\r\n        husart->pTxBuffPtr += 2U;\r\n      }\r\n      else\r\n      {\r\n        husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFF);       \r\n      }\r\n\r\n      husart->TxXferCount--;\r\n\r\n      return HAL_OK;\r\n    }\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Wraps up transmission in non-blocking mode.\r\n  * @param  husart: pointer to a USART_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified USART module.\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)\r\n{\r\n  /* Disable the USART Transmit Complete Interrupt */\r\n  CLEAR_BIT(husart->Instance->CR1, USART_CR1_TCIE);\r\n\r\n  /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r\n  CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);\r\n\r\n  husart->State = HAL_USART_STATE_READY;\r\n\r\n  HAL_USART_TxCpltCallback(husart);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Simplex Receive an amount of data in non-blocking mode.\r\n  *         Function called under interruption only, once\r\n  *         interruptions have been enabled by HAL_USART_Receive_IT()\r\n  * @param  husart: USART handle\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)\r\n{\r\n  uint16_t* tmp;\r\n  uint16_t uhMask = husart->Mask;\r\n\r\n  if(husart->State == HAL_USART_STATE_BUSY_RX)\r\n  {\r\n\r\n    if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r\n    {\r\n      tmp = (uint16_t*) husart->pRxBuffPtr;\r\n      *tmp = (uint16_t)(husart->Instance->RDR & uhMask);\r\n      husart->pRxBuffPtr += 2U;\r\n    }\r\n    else\r\n    {\r\n      *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);\r\n    }\r\n      /* Send dummy byte in order to generate the clock for the Slave to Send the next data */\r\n      husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x00FFU);\r\n\r\n    if(--husart->RxXferCount == 0U)\r\n    {\r\n      CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);\r\n\r\n      /* Disable the USART Parity Error Interrupt */\r\n      CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);\r\n\r\n      /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r\n      CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);\r\n\r\n      husart->State = HAL_USART_STATE_READY;\r\n\r\n      HAL_USART_RxCpltCallback(husart);\r\n\r\n      return HAL_OK;\r\n    }\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).\r\n  *         Function called under interruption only, once\r\n  *         interruptions have been enabled by HAL_USART_TransmitReceive_IT()     \r\n  * @param  husart: USART handle\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)\r\n{\r\n  uint16_t* tmp;\r\n  uint16_t uhMask = husart->Mask;\r\n\r\n  if(husart->State == HAL_USART_STATE_BUSY_TX_RX)\r\n  {\r\n    if(husart->TxXferCount != 0x00U)\r\n    {\r\n      if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)\r\n      {\r\n        if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r\n        {\r\n          tmp = (uint16_t*) husart->pTxBuffPtr;\r\n          husart->Instance->TDR = (uint16_t)(*tmp & uhMask);\r\n          husart->pTxBuffPtr += 2U;\r\n        }\r\n        else\r\n        {\r\n          husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)uhMask);\r\n        }\r\n        husart->TxXferCount--;\r\n\r\n        /* Check the latest data transmitted */\r\n        if(husart->TxXferCount == 0U)\r\n        {\r\n           CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);\r\n        }\r\n      }\r\n    }\r\n\r\n    if(husart->RxXferCount != 0x00U)\r\n    {\r\n      if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)\r\n      {\r\n        if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))\r\n        {\r\n          tmp = (uint16_t*) husart->pRxBuffPtr;\r\n          *tmp = (uint16_t)(husart->Instance->RDR & uhMask);\r\n          husart->pRxBuffPtr += 2U;\r\n        }\r\n        else\r\n        {\r\n          *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);\r\n        }\r\n        husart->RxXferCount--;\r\n      }\r\n    }\r\n\r\n    /* Check the latest data received */\r\n    if(husart->RxXferCount == 0U)\r\n    {\r\n      CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);\r\n\r\n      /* Disable the USART Parity Error Interrupt */\r\n      CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);\r\n\r\n      /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r\n      CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);\r\n\r\n      husart->State = HAL_USART_STATE_READY;\r\n\r\n      HAL_USART_TxRxCpltCallback(husart);\r\n\r\n      return HAL_OK;\r\n    }\r\n\r\n    return HAL_OK;\r\n  }\r\n  else\r\n  {\r\n    return HAL_BUSY;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  This function handles USART Communication Timeout.\r\n  * @param  husart USART handle\r\n  * @param  Flag specifies the USART flag to check.\r\n  * @param  Status The new Flag status (SET or RESET).\r\n  * @param  Tickstart Tick start value\r\n  * @param  Timeout Timeout duration\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)  \r\n{\r\n  /* Wait until flag is set */\r\n  while((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0U)||((HAL_GetTick()-Tickstart) >=  Timeout))\r\n      {\r\n        /* Disable the USART Transmit Complete Interrupt */\r\n        CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);\r\n        \r\n        /* Disable the USART RXNE Interrupt */\r\n        CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);\r\n        \r\n        /* Disable the USART Parity Error Interrupt */\r\n        CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);\r\n        \r\n        /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */\r\n        CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);\r\n        \r\n        husart->State= HAL_USART_STATE_READY;\r\n        \r\n        /* Process Unlocked */\r\n        __HAL_UNLOCK(husart);\r\n        \r\n        return HAL_TIMEOUT;\r\n      }\r\n    }\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief DMA USART transmit process complete callback\r\n  * @param  hdma: DMA handle\r\n  * @retval None\r\n  */\r\nstatic void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n\r\n  /* DMA Normal mode */\r\n  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)\r\n  { \r\n    husart->TxXferCount = 0U;\r\n\r\n    if(husart->State == HAL_USART_STATE_BUSY_TX)\r\n    {\r\n      /* Disable the DMA transfer for transmit request by resetting the DMAT bit\r\n         in the USART CR3 register */\r\n      CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r\n\r\n      /* Enable the USART Transmit Complete Interrupt */\r\n      SET_BIT(husart->Instance->CR1, USART_CR1_TCIE);\r\n    }\r\n  }\r\n  /* DMA Circular mode */\r\n  else\r\n  {\r\n    if(husart->State == HAL_USART_STATE_BUSY_TX)\r\n    {\r\n    HAL_USART_TxCpltCallback(husart);\r\n   }\r\n }\r\n}\r\n\r\n\r\n/**\r\n  * @brief DMA USART transmit process half complete callback\r\n  * @param hdma : DMA handle\r\n  * @retval None\r\n  */\r\nstatic void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n\r\n  HAL_USART_TxHalfCpltCallback(husart);\r\n}\r\n\r\n/**\r\n  * @brief DMA USART receive process complete callback\r\n  * @param  hdma: DMA handle\r\n  * @retval None\r\n  */\r\nstatic void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n\r\n  /* DMA Normal mode */\r\n  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)\r\n  { \r\n    husart->RxXferCount = 0U;\r\n    \r\n    /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\r\n    CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r\n    CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);\r\n\r\n    /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit\r\n    in USART CR3 register */\r\n    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);\r\n    /* similarly, disable the DMA TX transfer that was started to provide the\r\n       clock to the slave device */\r\n    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);\r\n\r\n      if(husart->State == HAL_USART_STATE_BUSY_RX)\r\n      {\r\n        HAL_USART_RxCpltCallback(husart);\r\n      }\r\n      /* The USART state is HAL_USART_STATE_BUSY_TX_RX */\r\n      else\r\n      {\r\n        HAL_USART_TxRxCpltCallback(husart);\r\n      }\r\n    husart->State= HAL_USART_STATE_READY;\r\n  }\r\n  /* DMA circular mode */\r\n  else\r\n  {\r\n    if(husart->State == HAL_USART_STATE_BUSY_RX)\r\n    {\r\n      HAL_USART_RxCpltCallback(husart);\r\n    }\r\n    /* The USART state is HAL_USART_STATE_BUSY_TX_RX */\r\n    else\r\n    {\r\n      HAL_USART_TxRxCpltCallback(husart);\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief DMA USART receive process half complete callback\r\n  * @param hdma : DMA handle\r\n  * @retval None\r\n  */\r\nstatic void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)\r\n{\r\n  USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;\r\n\r\n  HAL_USART_RxHalfCpltCallback(husart);\r\n}\r\n\r\n/**\r\n  * @brief DMA USART communication error callback\r\n  * @param  hdma: DMA handle\r\n  * @retval None\r\n  */\r\nstatic void USART_DMAError(DMA_HandleTypeDef *hdma)\r\n{\r\n  USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n\r\n  husart->RxXferCount = 0U;\r\n  husart->TxXferCount = 0U;\r\n  \r\n  /* Stop USART DMA Tx request if ongoing */\r\n  if((husart->State == HAL_USART_STATE_BUSY_TX)\r\n     &&(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)))\r\n  {\r\n    USART_EndTxTransfer(husart);\r\n  }\r\n  \r\n  /* Stop USART DMA Rx request if ongoing */\r\n  if((husart->State == HAL_USART_STATE_BUSY_RX)\r\n     &&(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)))\r\n  {\r\n    USART_EndRxTransfer(husart);\r\n  }\r\n  \r\n  husart->ErrorCode |= HAL_USART_ERROR_DMA;\r\n  husart->State= HAL_USART_STATE_READY;\r\n\r\n  HAL_USART_ErrorCallback(husart);\r\n}\r\n\r\n/**\r\n  * @brief DMA USART communication abort callback\r\n  *        (To be called at end of DMA Abort procedure).\r\n  * @param hdma: DMA handle.\r\n  * @retval None\r\n  */\r\nstatic void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)\r\n{\r\n  USART_HandleTypeDef* husart = (USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\r\n  husart->RxXferCount = 0U;\r\n  husart->TxXferCount = 0U;\r\n  \r\n  HAL_USART_ErrorCallback(husart);\r\n}\r\n\r\n/**\r\n  * @brief  End ongoing Tx transfer on USART peripheral (following error detection or Transmit completion).\r\n  * @param  husart: USART handle.\r\n  * @retval None\r\n  */\r\nstatic void USART_EndTxTransfer(USART_HandleTypeDef *husart)\r\n{\r\n  /* At end of Tx process, restore husart->State to Ready */\r\n  husart->State = HAL_USART_STATE_READY;\r\n  \r\n  /* Disable TXEIE and TCIE interrupts */\r\n  CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));\r\n}\r\n\r\n/**\r\n  * @brief  End ongoing Rx transfer on USART peripheral (following error detection or Reception completion).\r\n  * @param  husart: USART handle.\r\n  * @retval None\r\n  */\r\nstatic void USART_EndRxTransfer(USART_HandleTypeDef *husart)\r\n{\r\n  /* At end of Rx process, restore husart->RxState to Ready */\r\n  husart->State = HAL_USART_STATE_READY;\r\n  \r\n  /* Disable RXNE, PE and ERR interrupts */\r\n  CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\r\n  CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);\r\n}\r\n\r\n/**\r\n  * @brief Configure the USART peripheral \r\n  * @param husart: USART handle\r\n  * @retval None\r\n  */\r\nstatic HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)\r\n{\r\n  uint32_t tmpreg      = 0x0U;\r\n  USART_ClockSourceTypeDef clocksource = USART_CLOCKSOURCE_UNDEFINED;\r\n  HAL_StatusTypeDef ret                = HAL_OK;\r\n  uint16_t brrtemp                     = 0x0000U;\r\n  uint16_t usartdiv                    = 0x0000U;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));\r\n  assert_param(IS_USART_PHASE(husart->Init.CLKPhase));\r\n  assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));\r\n  assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));  \r\n  assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));\r\n  assert_param(IS_USART_STOPBITS(husart->Init.StopBits));\r\n  assert_param(IS_USART_PARITY(husart->Init.Parity));\r\n  assert_param(IS_USART_MODE(husart->Init.Mode));\r\n  assert_param(IS_USART_OVERSAMPLING(husart->Init.OverSampling));   \r\n\r\n\r\n  /*-------------------------- USART CR1 Configuration -----------------------*/\r\n   /* Clear M, PCE, PS, TE and RE bits and configure       \r\n   *  the USART Word Length, Parity, Mode and OverSampling: \r\n   *  set the M bits according to husart->Init.WordLength value \r\n   *  set PCE and PS bits according to husart->Init.Parity value\r\n   *  set TE and RE bits according to husart->Init.Mode value\r\n   *  force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */\r\n  tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;\r\n  MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg);\r\n  \r\n  /*---------------------------- USART CR2 Configuration ---------------------*/\r\n  /* Clear and configure the USART Clock, CPOL, CPHA, LBCL and STOP bits:\r\n   * set CPOL bit according to husart->Init.CLKPolarity value\r\n   * set CPHA bit according to husart->Init.CLKPhase value\r\n   * set LBCL bit according to husart->Init.CLKLastBit value\r\n   * set STOP[13:12] bits according to husart->Init.StopBits value */\r\n  tmpreg = (uint32_t)(USART_CLOCK_ENABLE); \r\n  tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase);\r\n  tmpreg |= ((uint32_t)husart->Init.CLKLastBit | (uint32_t)husart->Init.StopBits);\r\n  MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg);\r\n\r\n  /*-------------------------- USART CR3 Configuration -----------------------*/\r\n  /* no CR3 register configuration                                            */\r\n\r\n  /*-------------------------- USART BRR Configuration -----------------------*/\r\n  /* BRR is filled-up according to OVER8 bit setting which is forced to 1     */\r\n  USART_GETCLOCKSOURCE(husart, clocksource);\r\n  switch (clocksource)\r\n  {\r\n    case USART_CLOCKSOURCE_PCLK1:\r\n      usartdiv = (uint16_t)(((2*HAL_RCC_GetPCLK1Freq()) + (husart->Init.BaudRate/2))/ husart->Init.BaudRate);\r\n      break;\r\n    case USART_CLOCKSOURCE_PCLK2:\r\n      usartdiv = (uint16_t)(((2*HAL_RCC_GetPCLK2Freq()) + (husart->Init.BaudRate/2))/ husart->Init.BaudRate);\r\n      break;\r\n    case USART_CLOCKSOURCE_HSI:\r\n      usartdiv = (uint16_t)(((2*HSI_VALUE) + (husart->Init.BaudRate/2))/ husart->Init.BaudRate);\r\n      break;\r\n    case USART_CLOCKSOURCE_SYSCLK:\r\n      usartdiv = (uint16_t)(((2*HAL_RCC_GetSysClockFreq()) + (husart->Init.BaudRate/2))/ husart->Init.BaudRate);\r\n      break;\r\n    case USART_CLOCKSOURCE_LSE:\r\n      usartdiv = (uint16_t)(((2*LSE_VALUE) + (husart->Init.BaudRate/2))/ husart->Init.BaudRate);\r\n      break;\r\n    case USART_CLOCKSOURCE_UNDEFINED:\r\n    default:\r\n      ret = HAL_ERROR;\r\n      break;\r\n  } \r\n  \r\n  brrtemp = usartdiv & 0xFFF0U;\r\n  brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);\r\n  husart->Instance->BRR = brrtemp;\r\n  \r\n  return ret; \r\n}\r\n\r\n/**\r\n  * @brief Check the USART Idle State\r\n  * @param husart: USART handle\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)\r\n{\r\n  uint32_t tickstart = 0U;\r\n\t\r\n   /* Initialize the USART ErrorCode */\r\n  husart->ErrorCode = HAL_USART_ERROR_NONE;\r\n  \r\n  /* Init tickstart for timeout managment*/\r\n  tickstart = HAL_GetTick();\r\n  \r\n  /* Check if the Transmitter is enabled */\r\n  if((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)\r\n  {\r\n    /* Wait until TEACK flag is set */\r\n    if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK)  \r\n    { \r\n      husart->State= HAL_USART_STATE_TIMEOUT;      \r\n      return HAL_TIMEOUT;\r\n    } \r\n  }\r\n  /* Check if the Receiver is enabled */\r\n  if((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)\r\n  {\r\n    /* Wait until REACK flag is set */\r\n    if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK)  \r\n    { \r\n      husart->State= HAL_USART_STATE_TIMEOUT;       \r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  \r\n  /* Initialize the USART state*/\r\n  husart->State= HAL_USART_STATE_READY;\r\n  \r\n  /* Process Unlocked */\r\n  __HAL_UNLOCK(husart);\r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_USART_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_wwdg.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_hal_wwdg.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   WWDG HAL module driver.\r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the Window Watchdog (WWDG) peripheral:\r\n  *           + Initialization and Configuration function\r\n  *           + IO operation functions\r\n  @verbatim\r\n  ==============================================================================\r\n                      ##### WWDG specific features #####\r\n  ==============================================================================\r\n  [..]\r\n    Once enabled the WWDG generates a system reset on expiry of a programmed\r\n    time period, unless the program refreshes the counter (T[6;0] downcounter)\r\n    before reaching 0x3F value (i.e. a reset is generated when the counter\r\n    value rolls over from 0x40 to 0x3F).\r\n\r\n    (+) An MCU reset is also generated if the counter value is refreshed\r\n        before the counter has reached the refresh window value. This\r\n        implies that the counter must be refreshed in a limited window.\r\n\r\n    (+) Once enabled the WWDG cannot be disabled except by a system reset.\r\n\r\n    (+) WWDGRST flag in RCC_CSR register informs when a WWDG reset has \r\n        occurred (check available with __HAL_RCC_GET_FLAG(RCC_FLAG_WWDGRST)).\r\n\r\n    (+) The WWDG downcounter input clock is derived from the APB clock divided\r\n        by a programmable prescaler.\r\n\r\n    (+) WWDG downcounter clock (Hz) = PCLK1 / (4096 * Prescaler)\r\n\r\n    (+) WWDG timeout (ms) = (1000 * (T[5;0] + 1)) / (WWDG downcounter clock)\r\n        where T[5;0] are the lowest 6 bits of downcounter.\r\n\r\n    (+) WWDG Counter refresh is allowed between the following limits :\r\n        (++) min time (ms) = (1000 * (T[5;0] - Window)) / (WWDG downcounter clock)\r\n        (++) max time (ms) = (1000 * (T[5;0] - 0x40)) / (WWDG downcounter clock)\r\n\r\n    (+) Min-max timeout value @80 MHz(PCLK1): ~51.2 us / ~26.22 ms\r\n\r\n    (+) The Early Wakeup Interrupt (EWI) can be used if specific safety \r\n        operations or data logging must be performed before the actual reset is\r\n        generated. When the downcounter reaches the value 0x40, an EWI interrupt\r\n        is generated and the corresponding interrupt service routine (ISR) can \r\n        be used to trigger specific actions (such as communications or data \r\n        logging), before resetting the device.\r\n        In some applications, the EWI interrupt can be used to manage a software\r\n        system check and/or system recovery/graceful degradation, without \r\n        generating a WWDG reset. In this case, the corresponding interrupt \r\n        service routine (ISR) should reload the WWDG counter to avoid the WWDG \r\n        reset, then trigger the required actions.\r\n        Note:When the EWI interrupt cannot be served, e.g. due to a system lock \r\n        in a higher priority task, the WWDG reset will eventually be generated.\r\n\r\n    (+) Debug mode : When the microcontroller enters debug mode (core halted),\r\n        the WWDG counter either continues to work normally or stops, depending \r\n        on DBG_WWDG_STOP configuration bit in DBG module, accessible through\r\n        __HAL_DBGMCU_FREEZE_WWDG() and __HAL_DBGMCU_UNFREEZE_WWDG() macros\r\n\r\n                     ##### How to use this driver #####\r\n  ==============================================================================\r\n  [..]\r\n    (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().\r\n\r\n    (+) Set the WWDG prescaler, refresh window, counter value and Early Wakeup \r\n        Interrupt mode using using HAL_WWDG_Init() function.\r\n        This enables WWDG peripheral and the downcounter starts downcounting \r\n        from given counter value.\r\n        Init function can be called again to modify all watchdog parameters, \r\n        however if EWI mode has been set once, it can't be clear until next \r\n        reset.\r\n\r\n    (+) The application program must refresh the WWDG counter at regular\r\n        intervals during normal operation to prevent an MCU reset using\r\n        HAL_WWDG_Refresh() function. This operation must occur only when\r\n        the counter is lower than the window value already programmed.\r\n\r\n    (+) if Early Wakeup Interrupt mode is enable an interrupt is generated when \r\n        the counter reaches 0x40. User can add his own code in weak function \r\n        HAL_WWDG_EarlyWakeupCallback().\r\n\r\n     *** WWDG HAL driver macros list ***\r\n     ==================================\r\n     [..]\r\n       Below the list of most used macros in WWDG HAL driver.\r\n\r\n      (+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source.\r\n      (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status.\r\n      (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags.\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n#ifdef HAL_WWDG_MODULE_ENABLED\r\n/** @defgroup WWDG WWDG\r\n  * @brief WWDG HAL module driver.\r\n  * @{\r\n  */\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @defgroup WWDG_Exported_Functions WWDG Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions\r\n *  @brief    Initialization and Configuration functions.\r\n *\r\n@verbatim\r\n  ==============================================================================\r\n          ##### Initialization and Configuration functions #####\r\n  ==============================================================================\r\n  [..]  \r\n    This section provides functions allowing to:\r\n      (+) Initialize and start the WWDG according to the specified parameters\r\n          in the WWDG_InitTypeDef of associated handle.\r\n      (+) Initialize the WWDG MSP.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initialize the WWDG according to the specified.\r\n  *         parameters in the WWDG_InitTypeDef of  associated handle.\r\n  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified WWDG module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)\r\n{\r\n  /* Check the WWDG handle allocation */\r\n  if(hwwdg == NULL)\r\n  {\r\n    return HAL_ERROR;\r\n  }\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));\r\n  assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));\r\n  assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));\r\n  assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));\r\n  assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));\r\n\r\n  /* Init the low level hardware */\r\n  HAL_WWDG_MspInit(hwwdg);\r\n\r\n  /* Set WWDG Counter */\r\n  WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));\r\n\r\n  /* Set WWDG Prescaler and Window */\r\n  WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window));\r\n\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Initialize the WWDG MSP.\r\n  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified WWDG module.\r\n  * @note   When rewriting this function in user file, mechanism may be added\r\n  *         to avoid multiple initialize when HAL_WWDG_Init function is called\r\n  *         again to change parameters.\r\n  * @retval None\r\n  */\r\n__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hwwdg);\r\n\r\n  /* NOTE: This function should not be modified, when the callback is needed,\r\n           the HAL_WWDG_MspInit could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions\r\n *  @brief    IO operation functions \r\n *\r\n@verbatim\r\n  ==============================================================================\r\n                      ##### IO operation functions #####\r\n  ==============================================================================  \r\n  [..]\r\n    This section provides functions allowing to:\r\n    (+) Refresh the WWDG.\r\n    (+) Handle WWDG interrupt request and associated function callback.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Refresh the WWDG.\r\n  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified WWDG module.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg)\r\n{\r\n  /* Write to WWDG CR the WWDG Counter value to refresh with */\r\n  WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter));\r\n\r\n  /* Return function status */\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Handle WWDG interrupt request.\r\n  * @note   The Early Wakeup Interrupt (EWI) can be used if specific safety operations\r\n  *         or data logging must be performed before the actual reset is generated.\r\n  *         The EWI interrupt is enabled by calling HAL_WWDG_Init function with \r\n  *         EWIMode set to WWDG_EWI_ENABLE.\r\n  *         When the downcounter reaches the value 0x40, and EWI interrupt is\r\n  *         generated and the corresponding Interrupt Service Routine (ISR) can\r\n  *         be used to trigger specific actions (such as communications or data\r\n  *         logging), before resetting the device.\r\n  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified WWDG module.\r\n  * @retval None\r\n  */\r\nvoid HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)\r\n{\r\n  /* Check if Early Wakeup Interrupt is enable */\r\n  if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)\r\n  {\r\n    /* Check if WWDG Early Wakeup Interrupt occurred */\r\n    if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)\r\n    {\r\n      /* Clear the WWDG Early Wakeup flag */\r\n      __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);\r\n\r\n      /* Early Wakeup callback */ \r\n      HAL_WWDG_EarlyWakeupCallback(hwwdg);\r\n    }\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  * @brief  WWDG Early Wakeup callback.\r\n  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains\r\n  *                the configuration information for the specified WWDG module.\r\n  * @retval None\r\n  */\r\n__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg)\r\n{\r\n  /* Prevent unused argument(s) compilation warning */\r\n  UNUSED(hwwdg);\r\n\r\n  /* NOTE: This function should not be modified, when the callback is needed,\r\n           the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file\r\n   */\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* HAL_WWDG_MODULE_ENABLED */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_ll_fmc.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   FMC Low Layer HAL module driver.\r\n  *    \r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the Flexible Memory Controller (FMC) peripheral memories:\r\n  *           + Initialization/de-initialization functions\r\n  *           + Peripheral Control functions \r\n  *           + Peripheral State functions\r\n  *         \r\n  @verbatim\r\n  ==============================================================================\r\n                        ##### FMC peripheral features #####\r\n  ==============================================================================\r\n  [..] The Flexible memory controller (FMC) includes three memory controllers:\r\n       (+) The NOR/PSRAM memory controller\r\n       (+) The NAND memory controller\r\n       (+) The Synchronous DRAM (SDRAM) controller \r\n       \r\n  [..] The FMC functional block makes the interface with synchronous and asynchronous static\r\n       memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:\r\n       (+) to translate AHB transactions into the appropriate external device protocol\r\n       (+) to meet the access time requirements of the external memory devices\r\n   \r\n  [..] All external memories share the addresses, data and control signals with the controller.\r\n       Each external device is accessed by means of a unique Chip Select. The FMC performs\r\n       only one access at a time to an external device.\r\n       The main features of the FMC controller are the following:\r\n        (+) Interface with static-memory mapped devices including:\r\n           (++) Static random access memory (SRAM)\r\n           (++) Read-only memory (ROM)\r\n           (++) NOR Flash memory/OneNAND Flash memory\r\n           (++) PSRAM (4 memory banks)\r\n           (++) 16-bit PC Card compatible devices\r\n           (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of\r\n                data\r\n        (+) Interface with synchronous DRAM (SDRAM) memories\r\n        (+) Independent Chip Select control for each memory bank\r\n        (+) Independent configuration for each memory bank\r\n                    \r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup FMC_LL  FMC Low Layer\r\n  * @brief FMC driver modules\r\n  * @{\r\n  */\r\n\r\n#if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions\r\n  * @brief  NORSRAM Controller functions \r\n  *\r\n  @verbatim \r\n  ==============================================================================   \r\n                   ##### How to use NORSRAM device driver #####\r\n  ==============================================================================\r\n \r\n  [..] \r\n    This driver contains a set of APIs to interface with the FMC NORSRAM banks in order\r\n    to run the NORSRAM external devices.\r\n      \r\n    (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit() \r\n    (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()\r\n    (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()\r\n    (+) FMC NORSRAM bank extended timing configuration using the function \r\n        FMC_NORSRAM_Extended_Timing_Init()\r\n    (+) FMC NORSRAM bank enable/disable write operation using the functions\r\n        FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()\r\n        \r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n       \r\n/** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions\r\n  * @brief    Initialization and Configuration functions \r\n  *\r\n  @verbatim    \r\n  ==============================================================================\r\n              ##### Initialization and de_initialization functions #####\r\n  ==============================================================================\r\n  [..]  \r\n    This section provides functions allowing to:\r\n    (+) Initialize and configure the FMC NORSRAM interface\r\n    (+) De-initialize the FMC NORSRAM interface \r\n    (+) Configure the FMC clock and associated GPIOs    \r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n  \r\n/**\r\n  * @brief  Initialize the FMC_NORSRAM device according to the specified\r\n  *         control parameters in the FMC_NORSRAM_InitTypeDef\r\n  * @param  Device: Pointer to NORSRAM device instance\r\n  * @param  Init: Pointer to NORSRAM Initialization structure   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef  FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init)\r\n{ \r\n  uint32_t tmpr = 0;\r\n    \r\n  /* Check the parameters */\r\n  assert_param(IS_FMC_NORSRAM_DEVICE(Device));\r\n  assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));\r\n  assert_param(IS_FMC_MUX(Init->DataAddressMux));\r\n  assert_param(IS_FMC_MEMORY(Init->MemoryType));\r\n  assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));\r\n  assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));\r\n  assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));\r\n  assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));\r\n  assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));\r\n  assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));\r\n  assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));\r\n  assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));\r\n  assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));\r\n  assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock)); \r\n  assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));\r\n  assert_param(IS_FMC_PAGESIZE(Init->PageSize));\r\n\r\n  /* Get the BTCR register value */\r\n  tmpr = Device->BTCR[Init->NSBank];\r\n  \r\n  /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WAITCFG, WREN,\r\n           WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */\r\n  tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN     | FMC_BCR1_MUXEN    | FMC_BCR1_MTYP     | \\\r\n                       FMC_BCR1_MWID      | FMC_BCR1_FACCEN   | FMC_BCR1_BURSTEN  | \\\r\n                       FMC_BCR1_WAITPOL   | FMC_BCR1_CPSIZE    | FMC_BCR1_WAITCFG  | \\\r\n                       FMC_BCR1_WREN      | FMC_BCR1_WAITEN   | FMC_BCR1_EXTMOD   | \\\r\n                       FMC_BCR1_ASYNCWAIT | FMC_BCR1_CBURSTRW | FMC_BCR1_CCLKEN | FMC_BCR1_WFDIS));\r\n  \r\n  /* Set NORSRAM device control parameters */\r\n  tmpr |= (uint32_t)(Init->DataAddressMux       |\\\r\n                    Init->MemoryType           |\\\r\n                    Init->MemoryDataWidth      |\\\r\n                    Init->BurstAccessMode      |\\\r\n                    Init->WaitSignalPolarity   |\\\r\n                    Init->WaitSignalActive     |\\\r\n                    Init->WriteOperation       |\\\r\n                    Init->WaitSignal           |\\\r\n                    Init->ExtendedMode         |\\\r\n                    Init->AsynchronousWait     |\\\r\n                    Init->WriteBurst           |\\\r\n                    Init->ContinuousClock      |\\\r\n                    Init->PageSize             |\\\r\n                    Init->WriteFifo);\r\n                    \r\n  if(Init->MemoryType == FMC_MEMORY_TYPE_NOR)\r\n  {\r\n    tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE;\r\n  }\r\n  \r\n  Device->BTCR[Init->NSBank] = tmpr;\r\n\r\n  /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */\r\n  if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))\r\n  { \r\n    Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->ContinuousClock);\r\n  }\r\n  if(Init->NSBank != FMC_NORSRAM_BANK1)\r\n  {\r\n    Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo);              \r\n  }\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  DeInitialize the FMC_NORSRAM peripheral \r\n  * @param  Device: Pointer to NORSRAM device instance\r\n  * @param  ExDevice: Pointer to NORSRAM extended mode device instance  \r\n  * @param  Bank: NORSRAM bank number  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_FMC_NORSRAM_DEVICE(Device));\r\n  assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));\r\n  assert_param(IS_FMC_NORSRAM_BANK(Bank));\r\n  \r\n  /* Disable the FMC_NORSRAM device */\r\n  __FMC_NORSRAM_DISABLE(Device, Bank);\r\n  \r\n  /* De-initialize the FMC_NORSRAM device */\r\n  /* FMC_NORSRAM_BANK1 */\r\n  if(Bank == FMC_NORSRAM_BANK1)\r\n  {\r\n    Device->BTCR[Bank] = 0x000030DB;    \r\n  }\r\n  /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */\r\n  else\r\n  {   \r\n    Device->BTCR[Bank] = 0x000030D2; \r\n  }\r\n  \r\n  Device->BTCR[Bank + 1] = 0x0FFFFFFF;\r\n  ExDevice->BWTR[Bank]   = 0x0FFFFFFF;\r\n   \r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Initialize the FMC_NORSRAM Timing according to the specified\r\n  *         parameters in the FMC_NORSRAM_TimingTypeDef\r\n  * @param  Device: Pointer to NORSRAM device instance\r\n  * @param  Timing: Pointer to NORSRAM Timing structure\r\n  * @param  Bank: NORSRAM bank number  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)\r\n{\r\n  uint32_t tmpr = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_FMC_NORSRAM_DEVICE(Device));\r\n  assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));\r\n  assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));\r\n  assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));\r\n  assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));\r\n  assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));\r\n  assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));\r\n  assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));\r\n  assert_param(IS_FMC_NORSRAM_BANK(Bank));\r\n  \r\n  /* Get the BTCR register value */\r\n  tmpr = Device->BTCR[Bank + 1];\r\n\r\n  /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */\r\n  tmpr &= ((uint32_t)~(FMC_BTR1_ADDSET  | FMC_BTR1_ADDHLD | FMC_BTR1_DATAST | \\\r\n                       FMC_BTR1_BUSTURN | FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT | \\\r\n                       FMC_BTR1_ACCMOD));\r\n  \r\n  /* Set FMC_NORSRAM device timing parameters */  \r\n  tmpr |= (uint32_t)(Timing->AddressSetupTime                  |\\\r\n                   ((Timing->AddressHoldTime) << 4)          |\\\r\n                   ((Timing->DataSetupTime) << 8)            |\\\r\n                   ((Timing->BusTurnAroundDuration) << 16)   |\\\r\n                   (((Timing->CLKDivision)-1) << 20)         |\\\r\n                   (((Timing->DataLatency)-2) << 24)         |\\\r\n                    (Timing->AccessMode)\r\n                    );\r\n  \r\n  Device->BTCR[Bank + 1] = tmpr;\r\n  \r\n  /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */\r\n  if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))\r\n  {\r\n    tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << 20)); \r\n    tmpr |= (uint32_t)(((Timing->CLKDivision)-1) << 20);\r\n    Device->BTCR[FMC_NORSRAM_BANK1 + 1] = tmpr;\r\n  }  \r\n  \r\n  return HAL_OK;   \r\n}\r\n\r\n/**\r\n  * @brief  Initialize the FMC_NORSRAM Extended mode Timing according to the specified\r\n  *         parameters in the FMC_NORSRAM_TimingTypeDef\r\n  * @param  Device: Pointer to NORSRAM device instance\r\n  * @param  Timing: Pointer to NORSRAM Timing structure\r\n  * @param  Bank: NORSRAM bank number  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef  FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)\r\n{  \r\n  uint32_t tmpr = 0;\r\n \r\n  /* Check the parameters */\r\n  assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));\r\n  \r\n  /* Set NORSRAM device timing register for write configuration, if extended mode is used */\r\n  if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE)\r\n  {\r\n    /* Check the parameters */\r\n    assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));  \r\n    assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));\r\n    assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));\r\n    assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));\r\n    assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));\r\n    assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));\r\n    assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));\r\n    assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));\r\n    assert_param(IS_FMC_NORSRAM_BANK(Bank));  \r\n    \r\n    /* Get the BWTR register value */\r\n    tmpr = Device->BWTR[Bank];\r\n\r\n    /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */\r\n    tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET  | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \\\r\n                         FMC_BWTR1_BUSTURN | FMC_BWTR1_ACCMOD));\r\n    \r\n    tmpr |= (uint32_t)(Timing->AddressSetupTime                 |\\\r\n                      ((Timing->AddressHoldTime) << 4)          |\\\r\n                      ((Timing->DataSetupTime) << 8)            |\\\r\n                      ((Timing->BusTurnAroundDuration) << 16)   |\\\r\n                      (Timing->AccessMode));\r\n\r\n    Device->BWTR[Bank] = tmpr;\r\n  }\r\n  else\r\n  {\r\n    Device->BWTR[Bank] = 0x0FFFFFFF;\r\n  }   \r\n  \r\n  return HAL_OK;  \r\n}\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2\r\n *  @brief   management functions \r\n *\r\n@verbatim   \r\n  ==============================================================================\r\n                      ##### FMC_NORSRAM Control functions #####\r\n  ==============================================================================  \r\n  [..]\r\n    This subsection provides a set of functions allowing to control dynamically\r\n    the FMC NORSRAM interface.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Enables dynamically FMC_NORSRAM write operation.\r\n  * @param  Device: Pointer to NORSRAM device instance\r\n  * @param  Bank: NORSRAM bank number   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_FMC_NORSRAM_DEVICE(Device));\r\n  assert_param(IS_FMC_NORSRAM_BANK(Bank));\r\n  \r\n  /* Enable write operation */\r\n  Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE; \r\n\r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Disables dynamically FMC_NORSRAM write operation.\r\n  * @param  Device: Pointer to NORSRAM device instance\r\n  * @param  Bank: NORSRAM bank number   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)\r\n{ \r\n  /* Check the parameters */\r\n  assert_param(IS_FMC_NORSRAM_DEVICE(Device));\r\n  assert_param(IS_FMC_NORSRAM_BANK(Bank));\r\n    \r\n  /* Disable write operation */\r\n  Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE; \r\n\r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions\r\n  * @brief    NAND Controller functions \r\n  *\r\n  @verbatim \r\n  ==============================================================================\r\n                    ##### How to use NAND device driver #####\r\n  ==============================================================================\r\n  [..]\r\n    This driver contains a set of APIs to interface with the FMC NAND banks in order\r\n    to run the NAND external devices.\r\n  \r\n    (+) FMC NAND bank reset using the function FMC_NAND_DeInit() \r\n    (+) FMC NAND bank control configuration using the function FMC_NAND_Init()\r\n    (+) FMC NAND bank common space timing configuration using the function \r\n        FMC_NAND_CommonSpace_Timing_Init()\r\n    (+) FMC NAND bank attribute space timing configuration using the function \r\n        FMC_NAND_AttributeSpace_Timing_Init()\r\n    (+) FMC NAND bank enable/disable ECC correction feature using the functions\r\n        FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()\r\n    (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()    \r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions\r\n *  @brief    Initialization and Configuration functions \r\n *\r\n@verbatim    \r\n  ==============================================================================\r\n              ##### Initialization and de_initialization functions #####\r\n  ==============================================================================\r\n  [..]  \r\n    This section provides functions allowing to:\r\n    (+) Initialize and configure the FMC NAND interface\r\n    (+) De-initialize the FMC NAND interface \r\n    (+) Configure the FMC clock and associated GPIOs\r\n        \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the FMC_NAND device according to the specified\r\n  *         control parameters in the FMC_NAND_HandleTypeDef\r\n  * @param  Device: Pointer to NAND device instance\r\n  * @param  Init: Pointer to NAND Initialization structure\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)\r\n{\r\n  uint32_t tmpr  = 0; \r\n    \r\n  /* Check the parameters */\r\n  assert_param(IS_FMC_NAND_DEVICE(Device));\r\n  assert_param(IS_FMC_NAND_BANK(Init->NandBank));\r\n  assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));\r\n  assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));\r\n  assert_param(IS_FMC_ECC_STATE(Init->EccComputation));\r\n  assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));\r\n  assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));\r\n  assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));   \r\n\r\n  /* Get the NAND bank 3 register value */\r\n  tmpr = Device->PCR;\r\n\r\n  /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */\r\n  tmpr &= ((uint32_t)~(FMC_PCR_PWAITEN  | FMC_PCR_PBKEN | FMC_PCR_PTYP | \\\r\n                       FMC_PCR_PWID | FMC_PCR_ECCEN | FMC_PCR_TCLR | \\\r\n                       FMC_PCR_TAR | FMC_PCR_ECCPS));  \r\n  /* Set NAND device control parameters */\r\n  tmpr |= (uint32_t)(Init->Waitfeature                |\\\r\n                      FMC_PCR_MEMORY_TYPE_NAND         |\\\r\n                      Init->MemoryDataWidth            |\\\r\n                      Init->EccComputation             |\\\r\n                      Init->ECCPageSize                |\\\r\n                      ((Init->TCLRSetupTime) << 9)     |\\\r\n                      ((Init->TARSetupTime) << 13));   \r\n  \r\n    /* NAND bank 3 registers configuration */\r\n    Device->PCR  = tmpr;\r\n  \r\n  return HAL_OK;\r\n\r\n}\r\n\r\n/**\r\n  * @brief  Initializes the FMC_NAND Common space Timing according to the specified\r\n  *         parameters in the FMC_NAND_PCC_TimingTypeDef\r\n  * @param  Device: Pointer to NAND device instance\r\n  * @param  Timing: Pointer to NAND timing structure\r\n  * @param  Bank: NAND bank number   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)\r\n{\r\n  uint32_t tmpr = 0;  \r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_FMC_NAND_DEVICE(Device));\r\n  assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));\r\n  assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));\r\n  assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));\r\n  assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));\r\n  assert_param(IS_FMC_NAND_BANK(Bank));\r\n  \r\n  /* Get the NAND bank 3 register value */\r\n  tmpr = Device->PMEM;\r\n\r\n  /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */\r\n  tmpr &= ((uint32_t)~(FMC_PMEM_MEMSET3  | FMC_PMEM_MEMWAIT3 | FMC_PMEM_MEMHOLD3 | \\\r\n                       FMC_PMEM_MEMHIZ3)); \r\n  /* Set FMC_NAND device timing parameters */\r\n  tmpr |= (uint32_t)(Timing->SetupTime                  |\\\r\n                       ((Timing->WaitSetupTime) << 8)     |\\\r\n                       ((Timing->HoldSetupTime) << 16)    |\\\r\n                       ((Timing->HiZSetupTime) << 24)\r\n                       );\r\n                            \r\n    /* NAND bank 3 registers configuration */\r\n    Device->PMEM = tmpr;\r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Initializes the FMC_NAND Attribute space Timing according to the specified\r\n  *         parameters in the FMC_NAND_PCC_TimingTypeDef\r\n  * @param  Device: Pointer to NAND device instance\r\n  * @param  Timing: Pointer to NAND timing structure\r\n  * @param  Bank: NAND bank number \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)\r\n{\r\n  uint32_t tmpr = 0;  \r\n  \r\n  /* Check the parameters */ \r\n  assert_param(IS_FMC_NAND_DEVICE(Device)); \r\n  assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));\r\n  assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));\r\n  assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));\r\n  assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));\r\n  assert_param(IS_FMC_NAND_BANK(Bank));\r\n  \r\n  /* Get the NAND bank 3 register value */\r\n  tmpr = Device->PATT;\r\n\r\n  /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */\r\n  tmpr &= ((uint32_t)~(FMC_PATT_ATTSET3  | FMC_PATT_ATTWAIT3 | FMC_PATT_ATTHOLD3 | \\\r\n                       FMC_PATT_ATTHIZ3));\r\n  /* Set FMC_NAND device timing parameters */\r\n  tmpr |= (uint32_t)(Timing->SetupTime                  |\\\r\n                   ((Timing->WaitSetupTime) << 8)     |\\\r\n                   ((Timing->HoldSetupTime) << 16)    |\\\r\n                   ((Timing->HiZSetupTime) << 24));\r\n                       \r\n    /* NAND bank 3 registers configuration */\r\n    Device->PATT = tmpr;\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the FMC_NAND device \r\n  * @param  Device: Pointer to NAND device instance\r\n  * @param  Bank: NAND bank number\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)\r\n{\r\n  /* Check the parameters */ \r\n  assert_param(IS_FMC_NAND_DEVICE(Device)); \r\n  assert_param(IS_FMC_NAND_BANK(Bank));\r\n      \r\n  /* Disable the NAND Bank */\r\n  __FMC_NAND_DISABLE(Device);\r\n \r\n    /* Set the FMC_NAND_BANK3 registers to their reset values */\r\n    Device->PCR  = 0x00000018U;\r\n    Device->SR   = 0x00000040U;\r\n    Device->PMEM = 0xFCFCFCFCU;\r\n    Device->PATT = 0xFCFCFCFCU; \r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_FMC_NAND_Group3 Control functions \r\n  *  @brief   management functions \r\n  *\r\n@verbatim   \r\n  ==============================================================================\r\n                       ##### FMC_NAND Control functions #####\r\n  ==============================================================================  \r\n  [..]\r\n    This subsection provides a set of functions allowing to control dynamically\r\n    the FMC NAND interface.\r\n\r\n@endverbatim\r\n  * @{\r\n  */ \r\n\r\n    \r\n/**\r\n  * @brief  Enables dynamically FMC_NAND ECC feature.\r\n  * @param  Device: Pointer to NAND device instance\r\n  * @param  Bank: NAND bank number\r\n  * @retval HAL status\r\n  */    \r\nHAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)\r\n{\r\n  /* Check the parameters */ \r\n  assert_param(IS_FMC_NAND_DEVICE(Device)); \r\n  assert_param(IS_FMC_NAND_BANK(Bank));\r\n    \r\n  /* Enable ECC feature */\r\n    Device->PCR |= FMC_PCR_ECCEN;\r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n\r\n/**\r\n  * @brief  Disables dynamically FMC_NAND ECC feature.\r\n  * @param  Device: Pointer to NAND device instance\r\n  * @param  Bank: NAND bank number\r\n  * @retval HAL status\r\n  */  \r\nHAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)  \r\n{  \r\n  /* Check the parameters */ \r\n  assert_param(IS_FMC_NAND_DEVICE(Device)); \r\n  assert_param(IS_FMC_NAND_BANK(Bank));\r\n    \r\n  /* Disable ECC feature */\r\n    Device->PCR &= ~FMC_PCR_ECCEN;\r\n\r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Disables dynamically FMC_NAND ECC feature.\r\n  * @param  Device: Pointer to NAND device instance\r\n  * @param  ECCval: Pointer to ECC value\r\n  * @param  Bank: NAND bank number\r\n  * @param  Timeout: Timeout wait value  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)\r\n{\r\n  uint32_t tickstart = 0;\r\n\r\n  /* Check the parameters */ \r\n  assert_param(IS_FMC_NAND_DEVICE(Device)); \r\n  assert_param(IS_FMC_NAND_BANK(Bank));\r\n\r\n  /* Get tick */ \r\n  tickstart = HAL_GetTick();\r\n\r\n  /* Wait until FIFO is empty */\r\n  while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }  \r\n  }\r\n \r\n  /* Get the ECCR register value */\r\n  *ECCval = (uint32_t)Device->ECCR;\r\n\r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n  \r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup FMC_LL_SDRAM\r\n  * @brief    SDRAM Controller functions \r\n  *\r\n  @verbatim \r\n  ==============================================================================\r\n                     ##### How to use SDRAM device driver #####\r\n  ==============================================================================\r\n  [..] \r\n    This driver contains a set of APIs to interface with the FMC SDRAM banks in order\r\n    to run the SDRAM external devices.\r\n    \r\n    (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit() \r\n    (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()\r\n    (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()\r\n    (+) FMC SDRAM bank enable/disable write operation using the functions\r\n        FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()   \r\n    (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()      \r\n       \r\n@endverbatim\r\n  * @{\r\n  */\r\n         \r\n/** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1\r\n  *  @brief    Initialization and Configuration functions \r\n  *\r\n@verbatim    \r\n  ==============================================================================\r\n              ##### Initialization and de_initialization functions #####\r\n  ==============================================================================\r\n  [..]  \r\n    This section provides functions allowing to:\r\n    (+) Initialize and configure the FMC SDRAM interface\r\n    (+) De-initialize the FMC SDRAM interface \r\n    (+) Configure the FMC clock and associated GPIOs\r\n        \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the FMC_SDRAM device according to the specified\r\n  *         control parameters in the FMC_SDRAM_InitTypeDef\r\n  * @param  Device: Pointer to SDRAM device instance\r\n  * @param  Init: Pointer to SDRAM Initialization structure   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)\r\n{\r\n  uint32_t tmpr1 = 0;\r\n  uint32_t tmpr2 = 0;\r\n    \r\n  /* Check the parameters */\r\n  assert_param(IS_FMC_SDRAM_DEVICE(Device));\r\n  assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));\r\n  assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));\r\n  assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));\r\n  assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));\r\n  assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));\r\n  assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));\r\n  assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));\r\n  assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));\r\n  assert_param(IS_FMC_READ_BURST(Init->ReadBurst));\r\n  assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));   \r\n\r\n  /* Set SDRAM bank configuration parameters */\r\n  if (Init->SDBank != FMC_SDRAM_BANK2) \r\n  {\r\n    tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];\r\n    \r\n    /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */\r\n    tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC  | FMC_SDCR1_NR | FMC_SDCR1_MWID | \\\r\n                          FMC_SDCR1_NB  | FMC_SDCR1_CAS | FMC_SDCR1_WP   | \\\r\n                          FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));\r\n\r\n    tmpr1 |= (uint32_t)(Init->ColumnBitsNumber   |\\\r\n                        Init->RowBitsNumber      |\\\r\n                        Init->MemoryDataWidth    |\\\r\n                        Init->InternalBankNumber |\\\r\n                        Init->CASLatency         |\\\r\n                        Init->WriteProtection    |\\\r\n                        Init->SDClockPeriod      |\\\r\n                        Init->ReadBurst          |\\\r\n                        Init->ReadPipeDelay\r\n                        );                                      \r\n    Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;\r\n  }\r\n  else /* FMC_Bank2_SDRAM */                      \r\n  {\r\n    tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];\r\n    \r\n    /* Clear SDCLK, RBURST, and RPIPE bits */\r\n    tmpr1 &= ((uint32_t)~(FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));\r\n    \r\n    tmpr1 |= (uint32_t)(Init->SDClockPeriod      |\\\r\n                        Init->ReadBurst          |\\\r\n                        Init->ReadPipeDelay);\r\n    \r\n    tmpr2 = Device->SDCR[FMC_SDRAM_BANK2];\r\n    \r\n    /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */\r\n    tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC  | FMC_SDCR1_NR | FMC_SDCR1_MWID | \\\r\n                          FMC_SDCR1_NB  | FMC_SDCR1_CAS | FMC_SDCR1_WP   | \\\r\n                          FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));\r\n\r\n    tmpr2 |= (uint32_t)(Init->ColumnBitsNumber   |\\\r\n                       Init->RowBitsNumber       |\\\r\n                       Init->MemoryDataWidth     |\\\r\n                       Init->InternalBankNumber  |\\\r\n                       Init->CASLatency          |\\\r\n                       Init->WriteProtection);\r\n\r\n    Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;\r\n    Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;\r\n  }\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Initializes the FMC_SDRAM device timing according to the specified\r\n  *         parameters in the FMC_SDRAM_TimingTypeDef\r\n  * @param  Device: Pointer to SDRAM device instance\r\n  * @param  Timing: Pointer to SDRAM Timing structure\r\n  * @param  Bank: SDRAM bank number   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)\r\n{\r\n  uint32_t tmpr1 = 0;\r\n  uint32_t tmpr2 = 0;\r\n    \r\n  /* Check the parameters */\r\n  assert_param(IS_FMC_SDRAM_DEVICE(Device));\r\n  assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));\r\n  assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));\r\n  assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));\r\n  assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));\r\n  assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));\r\n  assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));\r\n  assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));\r\n  assert_param(IS_FMC_SDRAM_BANK(Bank));\r\n  \r\n  /* Set SDRAM device timing parameters */ \r\n  if (Bank != FMC_SDRAM_BANK2) \r\n  {\r\n    tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];\r\n    \r\n    /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */\r\n    tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD  | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \\\r\n                          FMC_SDTR1_TRC  | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \\\r\n                          FMC_SDTR1_TRCD));\r\n    \r\n    tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1)           |\\\r\n                       (((Timing->ExitSelfRefreshDelay)-1) << 4) |\\\r\n                       (((Timing->SelfRefreshTime)-1) << 8)      |\\\r\n                       (((Timing->RowCycleDelay)-1) << 12)       |\\\r\n                       (((Timing->WriteRecoveryTime)-1) <<16)    |\\\r\n                       (((Timing->RPDelay)-1) << 20)             |\\\r\n                       (((Timing->RCDDelay)-1) << 24));\r\n    Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;\r\n  }\r\n  else /* FMC_Bank2_SDRAM */\r\n  {\r\n    tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];\r\n    \r\n    /* Clear TRC and TRP bits */\r\n    tmpr1 &= ((uint32_t)~(FMC_SDTR1_TRC | FMC_SDTR1_TRP));\r\n    \r\n    tmpr1 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12)       |\\\r\n                        (((Timing->RPDelay)-1) << 20)); \r\n    \r\n    tmpr2 = Device->SDTR[FMC_SDRAM_BANK2];\r\n    \r\n    /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */\r\n    tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD  | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \\\r\n                          FMC_SDTR1_TRC  | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \\\r\n                          FMC_SDTR1_TRCD));\r\n    \r\n    tmpr2 |= (uint32_t)(((Timing->LoadToActiveDelay)-1)           |\\\r\n                       (((Timing->ExitSelfRefreshDelay)-1) << 4)  |\\\r\n                       (((Timing->SelfRefreshTime)-1) << 8)       |\\\r\n                       (((Timing->WriteRecoveryTime)-1) <<16)     |\\\r\n                       (((Timing->RCDDelay)-1) << 24));   \r\n\r\n    Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;\r\n    Device->SDTR[FMC_SDRAM_BANK2] = tmpr2;\r\n  }\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  DeInitializes the FMC_SDRAM peripheral \r\n  * @param  Device: Pointer to SDRAM device instance\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_FMC_SDRAM_DEVICE(Device));\r\n  assert_param(IS_FMC_SDRAM_BANK(Bank));\r\n  \r\n  /* De-initialize the SDRAM device */\r\n  Device->SDCR[Bank] = 0x000002D0;\r\n  Device->SDTR[Bank] = 0x0FFFFFFF;    \r\n  Device->SDCMR      = 0x00000000;\r\n  Device->SDRTR      = 0x00000000;\r\n  Device->SDSR       = 0x00000000;\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2\r\n  *  @brief   management functions \r\n  *\r\n@verbatim   \r\n  ==============================================================================\r\n                      ##### FMC_SDRAM Control functions #####\r\n  ==============================================================================  \r\n  [..]\r\n    This subsection provides a set of functions allowing to control dynamically\r\n    the FMC SDRAM interface.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Enables dynamically FMC_SDRAM write protection.\r\n  * @param  Device: Pointer to SDRAM device instance\r\n  * @param  Bank: SDRAM bank number \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)\r\n{ \r\n  /* Check the parameters */\r\n  assert_param(IS_FMC_SDRAM_DEVICE(Device));\r\n  assert_param(IS_FMC_SDRAM_BANK(Bank));\r\n  \r\n  /* Enable write protection */\r\n  Device->SDCR[Bank] |= FMC_SDRAM_WRITE_PROTECTION_ENABLE;\r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Disables dynamically FMC_SDRAM write protection.\r\n  * @param  hsdram: FMC_SDRAM handle\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_FMC_SDRAM_DEVICE(Device));\r\n  assert_param(IS_FMC_SDRAM_BANK(Bank));\r\n  \r\n  /* Disable write protection */\r\n  Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE;\r\n  \r\n  return HAL_OK;\r\n}\r\n  \r\n/**\r\n  * @brief  Send Command to the FMC SDRAM bank\r\n  * @param  Device: Pointer to SDRAM device instance\r\n  * @param  Command: Pointer to SDRAM command structure   \r\n  * @param  Timing: Pointer to SDRAM Timing structure\r\n  * @param  Timeout: Timeout wait value\r\n  * @retval HAL state\r\n  */  \r\nHAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)\r\n{\r\n  __IO uint32_t tmpr = 0;\r\n  uint32_t tickstart = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_FMC_SDRAM_DEVICE(Device));\r\n  assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));\r\n  assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));\r\n  assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));\r\n  assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));  \r\n\r\n  /* Set command register */\r\n  tmpr = (uint32_t)((Command->CommandMode)                  |\\\r\n                    (Command->CommandTarget)                |\\\r\n                    (((Command->AutoRefreshNumber)-1) << 5) |\\\r\n                    ((Command->ModeRegisterDefinition) << 9)\r\n                    );\r\n    \r\n  Device->SDCMR = tmpr;\r\n\r\n  /* Get tick */ \r\n  tickstart = HAL_GetTick();\r\n\r\n  /* wait until command is send */\r\n  while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY))\r\n  {\r\n    /* Check for the Timeout */\r\n    if(Timeout != HAL_MAX_DELAY)\r\n    {\r\n      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))\r\n      {\r\n        return HAL_TIMEOUT;\r\n      }\r\n    }     \r\n  }\r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Program the SDRAM Memory Refresh rate.\r\n  * @param  Device: Pointer to SDRAM device instance  \r\n  * @param  RefreshRate: The SDRAM refresh rate value.       \r\n  * @retval HAL state\r\n  */\r\nHAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_FMC_SDRAM_DEVICE(Device));\r\n  assert_param(IS_FMC_REFRESH_RATE(RefreshRate));\r\n  \r\n  /* Set the refresh rate in command register */\r\n  Device->SDRTR |= (RefreshRate<<1);\r\n  \r\n  return HAL_OK;   \r\n}\r\n\r\n/**\r\n  * @brief  Set the Number of consecutive SDRAM Memory auto Refresh commands.\r\n  * @param  Device: Pointer to SDRAM device instance  \r\n  * @param  AutoRefreshNumber: Specifies the auto Refresh number.       \r\n  * @retval None\r\n  */\r\nHAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_FMC_SDRAM_DEVICE(Device));\r\n  assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));\r\n  \r\n  /* Set the Auto-refresh number in command register */\r\n  Device->SDCMR |= (AutoRefreshNumber << 5); \r\n\r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Returns the indicated FMC SDRAM bank mode status.\r\n  * @param  Device: Pointer to SDRAM device instance  \r\n  * @param  Bank: Defines the FMC SDRAM bank. This parameter can be \r\n  *                     FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. \r\n  * @retval The FMC SDRAM bank mode status, could be on of the following values:\r\n  *         FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or \r\n  *         FMC_SDRAM_POWER_DOWN_MODE.           \r\n  */\r\nuint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)\r\n{\r\n  uint32_t tmpreg = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_FMC_SDRAM_DEVICE(Device));\r\n  assert_param(IS_FMC_SDRAM_BANK(Bank));\r\n\r\n  /* Get the corresponding bank mode */\r\n  if(Bank == FMC_SDRAM_BANK1)\r\n  {\r\n    tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1); \r\n  }\r\n  else\r\n  {\r\n    tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2);\r\n  }\r\n  \r\n  /* Return the mode status */\r\n  return tmpreg;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n#endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_SDRAM_MODULE_ENABLED */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_ll_sdmmc.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   SDMMC Low Layer HAL module driver.\r\n  *    \r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the SDMMC peripheral:\r\n  *           + Initialization/de-initialization functions\r\n  *           + I/O operation functions\r\n  *           + Peripheral Control functions \r\n  *           + Peripheral State functions\r\n  *         \r\n  @verbatim\r\n  ==============================================================================\r\n                       ##### SDMMC peripheral features #####\r\n  ==============================================================================        \r\n    [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the APB2\r\n         peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA\r\n         devices.\r\n    \r\n    [..] The SDMMC features include the following:\r\n         (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support\r\n             for three different databus modes: 1-bit (default), 4-bit and 8-bit\r\n         (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility)\r\n         (+) Full compliance with SD Memory Card Specifications Version 2.0\r\n         (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two\r\n             different data bus modes: 1-bit (default) and 4-bit\r\n         (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol\r\n             Rev1.1)\r\n         (+) Data transfer up to 48 MHz for the 8 bit mode\r\n         (+) Data and command output enable signals to control external bidirectional drivers.\r\n                 \r\n   \r\n                           ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]\r\n      This driver is a considered as a driver of service for external devices drivers \r\n      that interfaces with the SDMMC peripheral.\r\n      According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs \r\n      is used in the device's driver to perform SDMMC operations and functionalities.\r\n   \r\n      This driver is almost transparent for the final user, it is only used to implement other\r\n      functionalities of the external device.\r\n   \r\n    [..]\r\n      (+) The SDMMC clock (SDMMCCLK = 48 MHz) is coming from a specific output of PLL \r\n          (PLL48CLK). Before start working with SDMMC peripheral make sure that the\r\n          PLL is well configured.\r\n          The SDMMC peripheral uses two clock signals:\r\n          (++) SDMMC adapter clock (SDMMCCLK = 48 MHz)\r\n          (++) APB2 bus clock (PCLK2)\r\n       \r\n          -@@- PCLK2 and SDMMC_CK clock frequencies must respect the following condition:\r\n               Frequency(PCLK2) >= (3 / 8 x Frequency(SDMMC_CK))\r\n  \r\n      (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC\r\n          peripheral.\r\n\r\n      (+) Enable the Power ON State using the SDMMC_PowerState_ON(SDMMCx) \r\n          function and disable it using the function SDMMC_PowerState_OFF(SDMMCx).\r\n                \r\n      (+) Enable/Disable the clock using the __SDMMC_ENABLE()/__SDMMC_DISABLE() macros.\r\n  \r\n      (+) Enable/Disable the peripheral interrupts using the macros __SDMMC_ENABLE_IT(hSDMMC, IT) \r\n          and __SDMMC_DISABLE_IT(hSDMMC, IT) if you need to use interrupt mode. \r\n  \r\n      (+) When using the DMA mode \r\n          (++) Configure the DMA in the MSP layer of the external device\r\n          (++) Active the needed channel Request \r\n          (++) Enable the DMA using __SDMMC_DMA_ENABLE() macro or Disable it using the macro\r\n               __SDMMC_DMA_DISABLE().\r\n  \r\n      (+) To control the CPSM (Command Path State Machine) and send \r\n          commands to the card use the SDMMC_SendCommand(SDMMCx), \r\n          SDMMC_GetCommandResponse() and SDMMC_GetResponse() functions. First, user has\r\n          to fill the command structure (pointer to SDMMC_CmdInitTypeDef) according \r\n          to the selected command to be sent.\r\n          The parameters that should be filled are:\r\n           (++) Command Argument\r\n           (++) Command Index\r\n           (++) Command Response type\r\n           (++) Command Wait\r\n           (++) CPSM Status (Enable or Disable).\r\n  \r\n          -@@- To check if the command is well received, read the SDMMC_CMDRESP\r\n              register using the SDMMC_GetCommandResponse().\r\n              The SDMMC responses registers (SDMMC_RESP1 to SDMMC_RESP2), use the\r\n              SDMMC_GetResponse() function.\r\n  \r\n      (+) To control the DPSM (Data Path State Machine) and send/receive \r\n           data to/from the card use the SDMMC_DataConfig(), SDMMC_GetDataCounter(), \r\n          SDMMC_ReadFIFO(), DIO_WriteFIFO() and SDMMC_GetFIFOCount() functions.\r\n  \r\n    *** Read Operations ***\r\n    =======================\r\n    [..]\r\n      (#) First, user has to fill the data structure (pointer to\r\n          SDMMC_DataInitTypeDef) according to the selected data type to be received.\r\n          The parameters that should be filled are:\r\n           (++) Data TimeOut\r\n           (++) Data Length\r\n           (++) Data Block size\r\n           (++) Data Transfer direction: should be from card (To SDMMC)\r\n           (++) Data Transfer mode\r\n           (++) DPSM Status (Enable or Disable)\r\n                                     \r\n      (#) Configure the SDMMC resources to receive the data from the card\r\n          according to selected transfer mode (Refer to Step 8, 9 and 10).\r\n  \r\n      (#) Send the selected Read command (refer to step 11).\r\n                    \r\n      (#) Use the SDMMC flags/interrupts to check the transfer status.\r\n  \r\n    *** Write Operations ***\r\n    ========================\r\n    [..]\r\n     (#) First, user has to fill the data structure (pointer to\r\n         SDMMC_DataInitTypeDef) according to the selected data type to be received.\r\n         The parameters that should be filled are:\r\n          (++) Data TimeOut\r\n          (++) Data Length\r\n          (++) Data Block size\r\n          (++) Data Transfer direction:  should be to card (To CARD)\r\n          (++) Data Transfer mode\r\n          (++) DPSM Status (Enable or Disable)\r\n  \r\n     (#) Configure the SDMMC resources to send the data to the card according to \r\n         selected transfer mode.\r\n                     \r\n     (#) Send the selected Write command.\r\n                    \r\n     (#) Use the SDMMC flags/interrupts to check the transfer status.\r\n  \r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_HAL_Driver\r\n  * @{\r\n  */\r\n\r\n/** @defgroup SDMMC_LL SDMMC Low Layer\r\n  * @brief Low layer module for SD\r\n  * @{\r\n  */\r\n\r\n#if defined (HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED)\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Exported functions --------------------------------------------------------*/\r\n\r\n/** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions \r\n *  @brief    Initialization and Configuration functions \r\n *\r\n@verbatim    \r\n ===============================================================================\r\n              ##### Initialization/de-initialization functions #####\r\n ===============================================================================\r\n    [..]  This section provides functions allowing to:\r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the SDMMC according to the specified\r\n  *         parameters in the SDMMC_InitTypeDef and create the associated handle.\r\n  * @param  SDMMCx: Pointer to SDMMC register base\r\n  * @param  Init: SDMMC initialization structure   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init)\r\n{\r\n  uint32_t tmpreg = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_SDMMC_ALL_INSTANCE(SDMMCx));\r\n  assert_param(IS_SDMMC_CLOCK_EDGE(Init.ClockEdge)); \r\n  assert_param(IS_SDMMC_CLOCK_BYPASS(Init.ClockBypass));\r\n  assert_param(IS_SDMMC_CLOCK_POWER_SAVE(Init.ClockPowerSave));\r\n  assert_param(IS_SDMMC_BUS_WIDE(Init.BusWide));\r\n  assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));\r\n  assert_param(IS_SDMMC_CLKDIV(Init.ClockDiv));\r\n  \r\n  /* Set SDMMC configuration parameters */\r\n  tmpreg |= (Init.ClockEdge           |\\\r\n             Init.ClockBypass         |\\\r\n             Init.ClockPowerSave      |\\\r\n             Init.BusWide             |\\\r\n             Init.HardwareFlowControl |\\\r\n             Init.ClockDiv\r\n             ); \r\n  \r\n  /* Write to SDMMC CLKCR */\r\n  MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, tmpreg);  \r\n\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_SDMMC_LL_Group2 IO operation functions \r\n *  @brief   Data transfers functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                      ##### I/O operation functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides a set of functions allowing to manage the SDMMC data \r\n    transfers.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Read data (word) from Rx FIFO in blocking mode (polling) \r\n  * @param  SDMMCx: Pointer to SDMMC register base\r\n  * @retval HAL status\r\n  */\r\nuint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx)\r\n{\r\n  /* Read data from Rx FIFO */ \r\n  return (SDMMCx->FIFO);\r\n}\r\n\r\n/**\r\n  * @brief  Write data (word) to Tx FIFO in blocking mode (polling) \r\n  * @param  SDMMCx: Pointer to SDMMC register base\r\n  * @param  pWriteData: pointer to data to write\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData)\r\n{ \r\n  /* Write data to FIFO */ \r\n  SDMMCx->FIFO = *pWriteData;\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions \r\n *  @brief   management functions \r\n *\r\n@verbatim   \r\n ===============================================================================\r\n                      ##### Peripheral Control functions #####\r\n ===============================================================================  \r\n    [..]\r\n    This subsection provides a set of functions allowing to control the SDMMC data \r\n    transfers.\r\n\r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Set SDMMC Power state to ON. \r\n  * @param  SDMMCx: Pointer to SDMMC register base\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx)\r\n{  \r\n  /* Set power state to ON */ \r\n  SDMMCx->POWER = SDMMC_POWER_PWRCTRL;\r\n  \r\n  return HAL_OK; \r\n}\r\n\r\n/**\r\n  * @brief  Set SDMMC Power state to OFF. \r\n  * @param  SDMMCx: Pointer to SDMMC register base\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx)\r\n{\r\n  /* Set power state to OFF */\r\n  SDMMCx->POWER = (uint32_t)0x00000000;\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Get SDMMC Power state. \r\n  * @param  SDMMCx: Pointer to SDMMC register base\r\n  * @retval Power status of the controller. The returned value can be one of the \r\n  *         following values:\r\n  *            - 0x00: Power OFF\r\n  *            - 0x02: Power UP\r\n  *            - 0x03: Power ON \r\n  */\r\nuint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx)  \r\n{\r\n  return (SDMMCx->POWER & SDMMC_POWER_PWRCTRL);\r\n}\r\n\r\n/**\r\n  * @brief  Configure the SDMMC command path according to the specified parameters in\r\n  *         SDMMC_CmdInitTypeDef structure and send the command \r\n  * @param  SDMMCx: Pointer to SDMMC register base\r\n  * @param  Command: pointer to a SDMMC_CmdInitTypeDef structure that contains \r\n  *         the configuration information for the SDMMC command\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command)\r\n{\r\n  uint32_t tmpreg = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_SDMMC_CMD_INDEX(Command->CmdIndex));\r\n  assert_param(IS_SDMMC_RESPONSE(Command->Response));\r\n  assert_param(IS_SDMMC_WAIT(Command->WaitForInterrupt));\r\n  assert_param(IS_SDMMC_CPSM(Command->CPSM));\r\n\r\n  /* Set the SDMMC Argument value */\r\n  SDMMCx->ARG = Command->Argument;\r\n\r\n  /* Set SDMMC command parameters */\r\n  tmpreg |= (uint32_t)(Command->CmdIndex         |\\\r\n                       Command->Response         |\\\r\n                       Command->WaitForInterrupt |\\\r\n                       Command->CPSM);\r\n  \r\n  /* Write to SDMMC CMD register */\r\n  MODIFY_REG(SDMMCx->CMD, CMD_CLEAR_MASK, tmpreg); \r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Return the command index of last command for which response received\r\n  * @param  SDMMCx: Pointer to SDMMC register base\r\n  * @retval Command index of the last command response received\r\n  */\r\nuint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx)\r\n{\r\n  return (uint8_t)(SDMMCx->RESPCMD);\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Return the response received from the card for the last command\r\n  * @param  SDMMCx: Pointer to SDMMC register base    \r\n  * @param  Response: Specifies the SDMMC response register. \r\n  *          This parameter can be one of the following values:\r\n  *            @arg SDMMC_RESP1: Response Register 1\r\n  *            @arg SDMMC_RESP2: Response Register 2\r\n  *            @arg SDMMC_RESP3: Response Register 3\r\n  *            @arg SDMMC_RESP4: Response Register 4  \r\n  * @retval The Corresponding response register value\r\n  */\r\nuint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response)\r\n{\r\n  __IO uint32_t tmp = 0;\r\n\r\n  /* Check the parameters */\r\n  assert_param(IS_SDMMC_RESP(Response));\r\n  \r\n  /* Get the response */\r\n  tmp = (uint32_t)&(SDMMCx->RESP1) + Response;\r\n  \r\n  return (*(__IO uint32_t *) tmp);\r\n}  \r\n\r\n/**\r\n  * @brief  Configure the SDMMC data path according to the specified \r\n  *         parameters in the SDMMC_DataInitTypeDef.\r\n  * @param  SDMMCx: Pointer to SDMMC register base  \r\n  * @param  Data : pointer to a SDMMC_DataInitTypeDef structure \r\n  *         that contains the configuration information for the SDMMC data.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef SDMMC_DataConfig(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data)\r\n{\r\n  uint32_t tmpreg = 0;\r\n  \r\n  /* Check the parameters */\r\n  assert_param(IS_SDMMC_DATA_LENGTH(Data->DataLength));\r\n  assert_param(IS_SDMMC_BLOCK_SIZE(Data->DataBlockSize));\r\n  assert_param(IS_SDMMC_TRANSFER_DIR(Data->TransferDir));\r\n  assert_param(IS_SDMMC_TRANSFER_MODE(Data->TransferMode));\r\n  assert_param(IS_SDMMC_DPSM(Data->DPSM));\r\n\r\n  /* Set the SDMMC Data TimeOut value */\r\n  SDMMCx->DTIMER = Data->DataTimeOut;\r\n\r\n  /* Set the SDMMC DataLength value */\r\n  SDMMCx->DLEN = Data->DataLength;\r\n\r\n  /* Set the SDMMC data configuration parameters */\r\n  tmpreg |= (uint32_t)(Data->DataBlockSize |\\\r\n                       Data->TransferDir   |\\\r\n                       Data->TransferMode  |\\\r\n                       Data->DPSM);\r\n  \r\n  /* Write to SDMMC DCTRL */\r\n  MODIFY_REG(SDMMCx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);\r\n\r\n  return HAL_OK;\r\n\r\n}\r\n\r\n/**\r\n  * @brief  Returns number of remaining data bytes to be transferred.\r\n  * @param  SDMMCx: Pointer to SDMMC register base\r\n  * @retval Number of remaining data bytes to be transferred\r\n  */\r\nuint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx)\r\n{\r\n  return (SDMMCx->DCOUNT);\r\n}\r\n\r\n/**\r\n  * @brief  Get the FIFO data\r\n  * @param  SDMMCx: Pointer to SDMMC register base \r\n  * @retval Data received\r\n  */\r\nuint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx)\r\n{\r\n  return (SDMMCx->FIFO);\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Sets one of the two options of inserting read wait interval.\r\n  * @param  SDMMCx: Pointer to SDMMC register base   \r\n  * @param  SDMMC_ReadWaitMode: SDMMC Read Wait operation mode.\r\n  *          This parameter can be:\r\n  *            @arg SDMMC_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK\r\n  *            @arg SDMMC_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2\r\n  * @retval None\r\n  */\r\nHAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode)\r\n{\r\n  /* Check the parameters */\r\n  assert_param(IS_SDMMC_READWAIT_MODE(SDMMC_ReadWaitMode));\r\n\r\n  /* Set SDMMC read wait mode */\r\n  MODIFY_REG(SDMMCx->DCTRL, SDMMC_DCTRL_RWMOD, SDMMC_ReadWaitMode);\r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* (HAL_SD_MODULE_ENABLED) || (HAL_MMC_MODULE_ENABLED) */\r\n/**\r\n  * @}\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usb.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    stm32f7xx_ll_usb.c\r\n  * @author  MCD Application Team\r\n  * @version V1.1.0\r\n  * @date    22-April-2016\r\n  * @brief   USB Low Layer HAL module driver.\r\n  *    \r\n  *          This file provides firmware functions to manage the following \r\n  *          functionalities of the USB Peripheral Controller:\r\n  *           + Initialization/de-initialization functions\r\n  *           + I/O operation functions\r\n  *           + Peripheral Control functions \r\n  *           + Peripheral State functions\r\n  *         \r\n  @verbatim\r\n  ==============================================================================\r\n                    ##### How to use this driver #####\r\n  ==============================================================================\r\n    [..]\r\n      (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.\r\n  \r\n      (#) Call USB_CoreInit() API to initialize the USB Core peripheral.\r\n\r\n      (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.\r\n\r\n  @endverbatim\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r\n  *\r\n  * Redistribution and use in source and binary forms, with or without modification,\r\n  * are permitted provided that the following conditions are met:\r\n  *   1. Redistributions of source code must retain the above copyright notice,\r\n  *      this list of conditions and the following disclaimer.\r\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\r\n  *      this list of conditions and the following disclaimer in the documentation\r\n  *      and/or other materials provided with the distribution.\r\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r\n  *      may be used to endorse or promote products derived from this software\r\n  *      without specific prior written permission.\r\n  *\r\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32f7xx_hal.h\"\r\n\r\n/** @addtogroup STM32F7xx_LL_USB_DRIVER\r\n  * @{\r\n  */\r\n\r\n#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\nstatic HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);\r\n\r\n/* Exported functions --------------------------------------------------------*/\r\n/** @defgroup LL_USB_Exported_Functions USB Low Layer Exported Functions\r\n  * @{\r\n  */\r\n\r\n/** @defgroup LL_USB_Group1 Initialization/de-initialization functions \r\n *  @brief    Initialization and Configuration functions \r\n *\r\n@verbatim    \r\n ===============================================================================\r\n              ##### Initialization/de-initialization functions #####\r\n ===============================================================================\r\n    [..]  This section provides functions allowing to:\r\n \r\n@endverbatim\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @brief  Initializes the USB Core\r\n  * @param  USBx: USB Instance\r\n  * @param  cfg : pointer to a USB_OTG_CfgTypeDef structure that contains\r\n  *         the configuration information for the specified USBx peripheral.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)\r\n{\r\n  if (cfg.phy_itface == USB_OTG_ULPI_PHY)\r\n  {\r\n    \r\n    USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);\r\n\r\n    /* Init The ULPI Interface */\r\n    USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);\r\n   \r\n    /* Select vbus source */\r\n    USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);\r\n    if(cfg.use_external_vbus == 1)\r\n    {\r\n      USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;\r\n    }\r\n    /* Reset after a PHY select  */\r\n    USB_CoreReset(USBx); \r\n  }\r\n  else /* FS interface (embedded Phy) */\r\n  {\r\n    /* Select FS Embedded PHY */\r\n    USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;\r\n    \r\n    /* Reset after a PHY select and set Host mode */\r\n    USB_CoreReset(USBx);\r\n    \r\n    /* Deactivate the power down*/\r\n    USBx->GCCFG = USB_OTG_GCCFG_PWRDWN;\r\n  }\r\n \r\n  if(cfg.dma_enable == ENABLE)\r\n  {\r\n    USBx->GAHBCFG |= (USB_OTG_GAHBCFG_HBSTLEN_1 | USB_OTG_GAHBCFG_HBSTLEN_2);\r\n    USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;\r\n  }  \r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USB_EnableGlobalInt\r\n  *         Enables the controller's Global Int in the AHB Config reg\r\n  * @param  USBx : Selected device\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  USB_DisableGlobalInt\r\n  *         Disable the controller's Global Int in the AHB Config reg\r\n  * @param  USBx : Selected device\r\n  * @retval HAL status\r\n*/\r\nHAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;\r\n  return HAL_OK;\r\n}\r\n   \r\n/**\r\n  * @brief  USB_SetCurrentMode : Set functional mode\r\n  * @param  USBx : Selected device\r\n  * @param  mode :  current core mode\r\n  *          This parameter can be one of these values:\r\n  *            @arg USB_OTG_DEVICE_MODE: Peripheral mode\r\n  *            @arg USB_OTG_HOST_MODE: Host mode\r\n  *            @arg USB_OTG_DRD_MODE: Dual Role Device mode  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode)\r\n{\r\n  USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); \r\n  \r\n  if ( mode == USB_OTG_HOST_MODE)\r\n  {\r\n    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; \r\n  }\r\n  else if ( mode == USB_OTG_DEVICE_MODE)\r\n  {\r\n    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; \r\n  }\r\n  HAL_Delay(50);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USB_DevInit : Initializes the USB_OTG controller registers \r\n  *         for device mode\r\n  * @param  USBx : Selected device\r\n  * @param  cfg  : pointer to a USB_OTG_CfgTypeDef structure that contains\r\n  *         the configuration information for the specified USBx peripheral.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)\r\n{\r\n  uint32_t i = 0;\r\n\r\n  /*Activate VBUS Sensing B */\r\n  USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;\r\n  \r\n  if (cfg.vbus_sensing_enable == 0)\r\n  {\r\n    /* Deactivate VBUS Sensing B */\r\n    USBx->GCCFG &= ~ USB_OTG_GCCFG_VBDEN;\r\n    \r\n    /* B-peripheral session valid override enable*/ \r\n    USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;\r\n    USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;\r\n  }\r\n   \r\n  /* Restart the Phy Clock */\r\n  USBx_PCGCCTL = 0;\r\n\r\n  /* Device mode configuration */\r\n  USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;\r\n  \r\n  if(cfg.phy_itface  == USB_OTG_ULPI_PHY)\r\n  {\r\n    if(cfg.speed == USB_OTG_SPEED_HIGH)\r\n    {      \r\n      /* Set High speed phy */\r\n      USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH);\r\n    }\r\n    else \r\n    {\r\n      /* set High speed phy in Full speed mode */\r\n      USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH_IN_FULL);\r\n    }\r\n  }\r\n  else\r\n  {\r\n    /* Set Full speed phy */\r\n    USB_SetDevSpeed (USBx , USB_OTG_SPEED_FULL);\r\n  }\r\n\r\n  /* Flush the FIFOs */\r\n  USB_FlushTxFifo(USBx , 0x10); /* all Tx FIFOs */\r\n  USB_FlushRxFifo(USBx);\r\n  \r\n  /* Clear all pending Device Interrupts */\r\n  USBx_DEVICE->DIEPMSK = 0;\r\n  USBx_DEVICE->DOEPMSK = 0;\r\n  USBx_DEVICE->DAINT = 0xFFFFFFFF;\r\n  USBx_DEVICE->DAINTMSK = 0;\r\n  \r\n  for (i = 0; i < cfg.dev_endpoints; i++)\r\n  {\r\n    if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)\r\n    {\r\n      USBx_INEP(i)->DIEPCTL = (USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK);\r\n    }\r\n    else\r\n    {\r\n      USBx_INEP(i)->DIEPCTL = 0;\r\n    }\r\n    \r\n    USBx_INEP(i)->DIEPTSIZ = 0;\r\n    USBx_INEP(i)->DIEPINT  = 0xFF;\r\n  }\r\n  \r\n  for (i = 0; i < cfg.dev_endpoints; i++)\r\n  {\r\n    if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)\r\n    {\r\n      USBx_OUTEP(i)->DOEPCTL = (USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK);\r\n    }\r\n    else\r\n    {\r\n      USBx_OUTEP(i)->DOEPCTL = 0;\r\n    }\r\n    \r\n    USBx_OUTEP(i)->DOEPTSIZ = 0;\r\n    USBx_OUTEP(i)->DOEPINT  = 0xFF;\r\n  }\r\n  \r\n  USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);\r\n  \r\n  if (cfg.dma_enable == 1)\r\n  {\r\n    /*Set threshold parameters */\r\n    USBx_DEVICE->DTHRCTL = (USB_OTG_DTHRCTL_TXTHRLEN_6 | USB_OTG_DTHRCTL_RXTHRLEN_6);\r\n    USBx_DEVICE->DTHRCTL |= (USB_OTG_DTHRCTL_RXTHREN | USB_OTG_DTHRCTL_ISOTHREN | USB_OTG_DTHRCTL_NONISOTHREN);\r\n    \r\n    i= USBx_DEVICE->DTHRCTL;\r\n  }\r\n  \r\n  /* Disable all interrupts. */\r\n  USBx->GINTMSK = 0;\r\n  \r\n  /* Clear any pending interrupts */\r\n  USBx->GINTSTS = 0xBFFFFFFF;\r\n\r\n  /* Enable the common interrupts */\r\n  if (cfg.dma_enable == DISABLE)\r\n  {\r\n    USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; \r\n  }\r\n  \r\n  /* Enable interrupts matching to the Device mode ONLY */\r\n  USBx->GINTMSK |= (USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |\\\r\n                    USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |\\\r\n                    USB_OTG_GINTMSK_OEPINT   | USB_OTG_GINTMSK_IISOIXFRM|\\\r\n                    USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);\r\n  \r\n  if(cfg.Sof_enable)\r\n  {\r\n    USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;\r\n  }\r\n\r\n  if (cfg.vbus_sensing_enable == ENABLE)\r\n  {\r\n    USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); \r\n  }\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  USB_OTG_FlushTxFifo : Flush a Tx FIFO\r\n  * @param  USBx : Selected device\r\n  * @param  num : FIFO number\r\n  *         This parameter can be a value from 1 to 15\r\n            15 means Flush all Tx FIFOs\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num )\r\n{\r\n  uint32_t count = 0;\r\n \r\n  USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 6)); \r\n \r\n  do\r\n  {\r\n    if (++count > 200000)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  USB_FlushRxFifo : Flush Rx FIFO\r\n  * @param  USBx : Selected device\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  uint32_t count = 0;\r\n  \r\n  USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;\r\n  \r\n  do\r\n  {\r\n    if (++count > 200000)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USB_SetDevSpeed :Initializes the DevSpd field of DCFG register \r\n  *         depending the PHY type and the enumeration speed of the device.\r\n  * @param  USBx : Selected device\r\n  * @param  speed : device speed\r\n  *          This parameter can be one of these values:\r\n  *            @arg USB_OTG_SPEED_HIGH: High speed mode\r\n  *            @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode\r\n  *            @arg USB_OTG_SPEED_FULL: Full speed mode\r\n  *            @arg USB_OTG_SPEED_LOW: Low speed mode\r\n  * @retval  Hal status\r\n  */\r\nHAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed)\r\n{\r\n  USBx_DEVICE->DCFG |= speed;\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USB_GetDevSpeed :Return the  Dev Speed \r\n  * @param  USBx : Selected device\r\n  * @retval speed : device speed\r\n  *          This parameter can be one of these values:\r\n  *            @arg USB_OTG_SPEED_HIGH: High speed mode\r\n  *            @arg USB_OTG_SPEED_FULL: Full speed mode\r\n  *            @arg USB_OTG_SPEED_LOW: Low speed mode\r\n  */\r\nuint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  uint8_t speed = 0;\r\n  \r\n  if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)\r\n  {\r\n    speed = USB_OTG_SPEED_HIGH;\r\n  }\r\n  else if (((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ)||\r\n           ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_48MHZ))\r\n  {\r\n    speed = USB_OTG_SPEED_FULL;\r\n  }\r\n  else if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)\r\n  {\r\n    speed = USB_OTG_SPEED_LOW;\r\n  }\r\n  \r\n  return speed;\r\n}\r\n\r\n/**\r\n  * @brief  Activate and configure an endpoint\r\n  * @param  USBx : Selected device\r\n  * @param  ep: pointer to endpoint structure\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r\n{\r\n  if (ep->is_in == 1)\r\n  {\r\n   USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)));\r\n   \r\n    if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0)\r\n    {\r\n      USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\\\r\n        ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); \r\n    } \r\n\r\n  }\r\n  else\r\n  {\r\n     USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16);\r\n     \r\n    if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0)\r\n    {\r\n      USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\\\r\n       (USB_OTG_DIEPCTL_SD0PID_SEVNFRM)| (USB_OTG_DOEPCTL_USBAEP));\r\n    } \r\n  }\r\n  return HAL_OK;\r\n}\r\n/**\r\n  * @brief  Activate and configure a dedicated endpoint\r\n  * @param  USBx : Selected device\r\n  * @param  ep: pointer to endpoint structure\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r\n{\r\n  static __IO uint32_t debug = 0;\r\n  \r\n  /* Read DEPCTLn register */\r\n  if (ep->is_in == 1)\r\n  {\r\n    if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0)\r\n    {\r\n      USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\\\r\n        ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); \r\n    } \r\n    \r\n    \r\n    debug  |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\\\r\n        ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); \r\n    \r\n   USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)));\r\n  }\r\n  else\r\n  {\r\n    if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0)\r\n    {\r\n      USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\\\r\n        ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP));\r\n      \r\n      debug = (uint32_t)(((uint32_t )USBx) + USB_OTG_OUT_ENDPOINT_BASE + (0)*USB_OTG_EP_REG_SIZE);\r\n      debug = (uint32_t )&USBx_OUTEP(ep->num)->DOEPCTL;\r\n      debug |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\\\r\n        ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP)); \r\n    } \r\n    \r\n     USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16);\r\n  }\r\n\r\n  return HAL_OK;\r\n}\r\n/**\r\n  * @brief  De-activate and de-initialize an endpoint\r\n  * @param  USBx : Selected device\r\n  * @param  ep: pointer to endpoint structure\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r\n{\r\n  /* Read DEPCTLn register */\r\n  if (ep->is_in == 1)\r\n  {\r\n   USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));\r\n   USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));   \r\n   USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;   \r\n  }\r\n  else\r\n  {\r\n     USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));\r\n     USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));     \r\n     USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;      \r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  De-activate and de-initialize a dedicated endpoint\r\n  * @param  USBx : Selected device\r\n  * @param  ep: pointer to endpoint structure\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r\n{\r\n  /* Read DEPCTLn register */\r\n  if (ep->is_in == 1)\r\n  {\r\n   USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;\r\n   USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));\r\n  }\r\n  else\r\n  {\r\n     USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; \r\n     USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USB_EPStartXfer : setup and starts a transfer over an EP\r\n  * @param  USBx : Selected device\r\n  * @param  ep: pointer to endpoint structure\r\n  * @param  dma: USB dma enabled or disabled \r\n  *          This parameter can be one of these values:\r\n  *           0 : DMA feature not used \r\n  *           1 : DMA feature used  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)\r\n{\r\n  uint16_t pktcnt = 0;\r\n  \r\n  /* IN endpoint */\r\n  if (ep->is_in == 1)\r\n  {\r\n    /* Zero Length Packet? */\r\n    if (ep->xfer_len == 0)\r\n    {\r\n      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); \r\n      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;\r\n      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); \r\n    }\r\n    else\r\n    {\r\n      /* Program the transfer size and packet count\r\n      * as follows: xfersize = N * maxpacket +\r\n      * short_packet pktcnt = N + (short_packet\r\n      * exist ? 1 : 0)\r\n      */\r\n      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);\r\n      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); \r\n      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket) << 19)) ;\r\n      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); \r\n      \r\n      if (ep->type == EP_TYPE_ISOC)\r\n      {\r\n        USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); \r\n        USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1 << 29)); \r\n      }       \r\n    }\r\n\r\n    if (dma == 1)\r\n    {\r\n      USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);\r\n    }\r\n    else\r\n    {\r\n      if (ep->type != EP_TYPE_ISOC)\r\n      {\r\n        /* Enable the Tx FIFO Empty Interrupt for this EP */\r\n        if (ep->xfer_len > 0)\r\n        {\r\n          USBx_DEVICE->DIEPEMPMSK |= 1 << ep->num;\r\n        }\r\n      }\r\n    }\r\n\r\n    if (ep->type == EP_TYPE_ISOC)\r\n    {\r\n      if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0)\r\n      {\r\n        USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;\r\n      }\r\n      else\r\n      {\r\n        USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;\r\n      }\r\n    } \r\n    \r\n    /* EP enable, IN data in FIFO */\r\n    USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);\r\n    \r\n    if (ep->type == EP_TYPE_ISOC)\r\n    {\r\n      USB_WritePacket(USBx, ep->xfer_buff, ep->num, ep->xfer_len, dma);   \r\n    }    \r\n  }\r\n  else /* OUT endpoint */\r\n  {\r\n    /* Program the transfer size and packet count as follows:\r\n    * pktcnt = N\r\n    * xfersize = N * maxpacket\r\n    */  \r\n    USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); \r\n    USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); \r\n      \r\n    if (ep->xfer_len == 0)\r\n    {\r\n      USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);\r\n      USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ;      \r\n    }\r\n    else\r\n    {\r\n      pktcnt = (ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket; \r\n      USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19));\r\n      USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt)); \r\n    }\r\n\r\n    if (dma == 1)\r\n    {\r\n      USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)ep->xfer_buff;\r\n    }\r\n    \r\n    if (ep->type == EP_TYPE_ISOC)\r\n    {\r\n      if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0)\r\n      {\r\n        USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;\r\n      }\r\n      else\r\n      {\r\n        USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;\r\n      }\r\n    }\r\n    /* EP enable */\r\n    USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USB_EP0StartXfer : setup and starts a transfer over the EP  0\r\n  * @param  USBx : Selected device\r\n  * @param  ep: pointer to endpoint structure\r\n  * @param  dma: USB dma enabled or disabled \r\n  *          This parameter can be one of these values:\r\n  *           0 : DMA feature not used \r\n  *           1 : DMA feature used  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)\r\n{\r\n  /* IN endpoint */\r\n  if (ep->is_in == 1)\r\n  {\r\n    /* Zero Length Packet? */\r\n    if (ep->xfer_len == 0)\r\n    {\r\n      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); \r\n      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;\r\n      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); \r\n    }\r\n    else\r\n    {\r\n      /* Program the transfer size and packet count\r\n      * as follows: xfersize = N * maxpacket +\r\n      * short_packet pktcnt = N + (short_packet\r\n      * exist ? 1 : 0)\r\n      */\r\n      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);\r\n      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); \r\n      \r\n      if(ep->xfer_len > ep->maxpacket)\r\n      {\r\n        ep->xfer_len = ep->maxpacket;\r\n      }\r\n      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;\r\n      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); \r\n    \r\n    }\r\n    \r\n    if (dma == 1)\r\n    {\r\n      USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);\r\n    }\r\n    else\r\n    {\r\n      /* Enable the Tx FIFO Empty Interrupt for this EP */\r\n      if (ep->xfer_len > 0)\r\n      {\r\n        USBx_DEVICE->DIEPEMPMSK |= 1 << (ep->num);\r\n      }\r\n    }\r\n    \r\n    /* EP enable, IN data in FIFO */\r\n    USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);   \r\n  }\r\n  else /* OUT endpoint */\r\n  {\r\n    /* Program the transfer size and packet count as follows:\r\n    * pktcnt = N\r\n    * xfersize = N * maxpacket\r\n    */\r\n    USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); \r\n    USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); \r\n      \r\n    if (ep->xfer_len > 0)\r\n    {\r\n      ep->xfer_len = ep->maxpacket;\r\n    }\r\n    \r\n    USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19));\r\n    USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); \r\n    \r\n\r\n    if (dma == 1)\r\n    {\r\n      USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)(ep->xfer_buff);\r\n    }\r\n    \r\n    /* EP enable */\r\n    USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);    \r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USB_WritePacket : Writes a packet into the Tx FIFO associated \r\n  *         with the EP/channel\r\n  * @param  USBx : Selected device           \r\n  * @param  src :  pointer to source buffer\r\n  * @param  ch_ep_num : endpoint or host channel number\r\n  * @param  len : Number of bytes to write\r\n  * @param  dma: USB dma enabled or disabled \r\n  *          This parameter can be one of these values:\r\n  *           0 : DMA feature not used \r\n  *           1 : DMA feature used  \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma)\r\n{\r\n  uint32_t count32b= 0 , i= 0;\r\n  \r\n  if (dma == 0)\r\n  {\r\n    count32b =  (len + 3) / 4;\r\n    for (i = 0; i < count32b; i++, src += 4)\r\n    {\r\n      USBx_DFIFO(ch_ep_num) = *((__packed uint32_t *)src);\r\n    }\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USB_ReadPacket : read a packet from the Tx FIFO associated \r\n  *         with the EP/channel\r\n  * @param  USBx : Selected device  \r\n  * @param  src : source pointer\r\n  * @param  ch_ep_num : endpoint or host channel number\r\n  * @param  len : Number of bytes to read\r\n  * @param  dma: USB dma enabled or disabled \r\n  *          This parameter can be one of these values:\r\n  *           0 : DMA feature not used \r\n  *           1 : DMA feature used  \r\n  * @retval pointer to destination buffer\r\n  */\r\nvoid *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)\r\n{\r\n  uint32_t i=0;\r\n  uint32_t count32b = (len + 3) / 4;\r\n  \r\n  for ( i = 0; i < count32b; i++, dest += 4 )\r\n  {\r\n    *(__packed uint32_t *)dest = USBx_DFIFO(0);\r\n    \r\n  }\r\n  return ((void *)dest);\r\n}\r\n\r\n/**\r\n  * @brief  USB_EPSetStall : set a stall condition over an EP\r\n  * @param  USBx : Selected device\r\n  * @param  ep: pointer to endpoint structure   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep)\r\n{\r\n  if (ep->is_in == 1)\r\n  {\r\n    if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == 0)\r\n    {\r\n      USBx_INEP(ep->num)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); \r\n    } \r\n    USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;\r\n  }\r\n  else\r\n  {\r\n    if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == 0)\r\n    {\r\n      USBx_OUTEP(ep->num)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); \r\n    } \r\n    USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;\r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  USB_EPClearStall : Clear a stall condition over an EP\r\n  * @param  USBx : Selected device\r\n  * @param  ep: pointer to endpoint structure   \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\r\n{\r\n  if (ep->is_in == 1)\r\n  {\r\n    USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;\r\n    if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)\r\n    {\r\n       USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */\r\n    }    \r\n  }\r\n  else\r\n  {\r\n    USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;\r\n    if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)\r\n    {\r\n      USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */\r\n    }    \r\n  }\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USB_StopDevice : Stop the usb device mode\r\n  * @param  USBx : Selected device\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  uint32_t i;\r\n  \r\n  /* Clear Pending interrupt */\r\n  for (i = 0; i < 15 ; i++)\r\n  {\r\n    USBx_INEP(i)->DIEPINT  = 0xFF;\r\n    USBx_OUTEP(i)->DOEPINT  = 0xFF;\r\n  }\r\n  USBx_DEVICE->DAINT = 0xFFFFFFFF;\r\n  \r\n  /* Clear interrupt masks */\r\n  USBx_DEVICE->DIEPMSK  = 0;\r\n  USBx_DEVICE->DOEPMSK  = 0;\r\n  USBx_DEVICE->DAINTMSK = 0;\r\n  \r\n  /* Flush the FIFO */\r\n  USB_FlushRxFifo(USBx);\r\n  USB_FlushTxFifo(USBx ,  0x10 );  \r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USB_SetDevAddress : Stop the usb device mode\r\n  * @param  USBx : Selected device\r\n  * @param  address : new device address to be assigned\r\n  *          This parameter can be a value from 0 to 255\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef  USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address)\r\n{\r\n  USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD);\r\n  USBx_DEVICE->DCFG |= (address << 4) & USB_OTG_DCFG_DAD ;\r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down\r\n  * @param  USBx : Selected device\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef  USB_DevConnect (USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS ;\r\n  HAL_Delay(3);\r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down\r\n  * @param  USBx : Selected device\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef  USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS ;\r\n  HAL_Delay(3);\r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  USB_ReadInterrupts: return the global USB interrupt status\r\n  * @param  USBx : Selected device\r\n  * @retval HAL status\r\n  */\r\nuint32_t  USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  uint32_t v = 0;\r\n  \r\n  v = USBx->GINTSTS;\r\n  v &= USBx->GINTMSK;\r\n  return v;  \r\n}\r\n\r\n/**\r\n  * @brief  USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status\r\n  * @param  USBx : Selected device\r\n  * @retval HAL status\r\n  */\r\nuint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  uint32_t v;\r\n  v  = USBx_DEVICE->DAINT;\r\n  v &= USBx_DEVICE->DAINTMSK;\r\n  return ((v & 0xffff0000) >> 16);\r\n}\r\n\r\n/**\r\n  * @brief  USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status\r\n  * @param  USBx : Selected device\r\n  * @retval HAL status\r\n  */\r\nuint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  uint32_t v;\r\n  v  = USBx_DEVICE->DAINT;\r\n  v &= USBx_DEVICE->DAINTMSK;\r\n  return ((v & 0xFFFF));\r\n}\r\n\r\n/**\r\n  * @brief  Returns Device OUT EP Interrupt register\r\n  * @param  USBx : Selected device\r\n  * @param  epnum : endpoint number\r\n  *          This parameter can be a value from 0 to 15\r\n  * @retval Device OUT EP Interrupt register\r\n  */\r\nuint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)\r\n{\r\n  uint32_t v;\r\n  v  = USBx_OUTEP(epnum)->DOEPINT;\r\n  v &= USBx_DEVICE->DOEPMSK;\r\n  return v;\r\n}\r\n\r\n/**\r\n  * @brief  Returns Device IN EP Interrupt register\r\n  * @param  USBx : Selected device\r\n  * @param  epnum : endpoint number\r\n  *          This parameter can be a value from 0 to 15\r\n  * @retval Device IN EP Interrupt register\r\n  */\r\nuint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)\r\n{\r\n  uint32_t v, msk, emp;\r\n  \r\n  msk = USBx_DEVICE->DIEPMSK;\r\n  emp = USBx_DEVICE->DIEPEMPMSK;\r\n  msk |= ((emp >> epnum) & 0x1) << 7;\r\n  v = USBx_INEP(epnum)->DIEPINT & msk;\r\n  return v;\r\n}\r\n\r\n/**\r\n  * @brief  USB_ClearInterrupts: clear a USB interrupt\r\n  * @param  USBx : Selected device\r\n  * @param  interrupt : interrupt flag\r\n  * @retval None\r\n  */\r\nvoid  USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)\r\n{\r\n  USBx->GINTSTS |= interrupt; \r\n}\r\n\r\n/**\r\n  * @brief  Returns USB core mode\r\n  * @param  USBx : Selected device\r\n  * @retval return core mode : Host or Device\r\n  *          This parameter can be one of these values:\r\n  *           0 : Host \r\n  *           1 : Device\r\n  */\r\nuint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  return ((USBx->GINTSTS ) & 0x1);\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Activate EP0 for Setup transactions\r\n  * @param  USBx : Selected device\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef  USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  /* Set the MPS of the IN EP based on the enumeration speed */\r\n  USBx_INEP(0)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;\r\n  \r\n  if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)\r\n  {\r\n    USBx_INEP(0)->DIEPCTL |= 3;\r\n  }\r\n  USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  Prepare the EP0 to start the first control setup\r\n  * @param  USBx : Selected device\r\n  * @param  dma: USB dma enabled or disabled \r\n  *          This parameter can be one of these values:\r\n  *           0 : DMA feature not used \r\n  *           1 : DMA feature used  \r\n  * @param  psetup : pointer to setup packet\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup)\r\n{\r\n  USBx_OUTEP(0)->DOEPTSIZ = 0;\r\n  USBx_OUTEP(0)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ;\r\n  USBx_OUTEP(0)->DOEPTSIZ |= (3 * 8);\r\n  USBx_OUTEP(0)->DOEPTSIZ |=  USB_OTG_DOEPTSIZ_STUPCNT;  \r\n  \r\n  if (dma == 1)\r\n  {\r\n    USBx_OUTEP(0)->DOEPDMA = (uint32_t)psetup;\r\n    /* EP enable */\r\n    USBx_OUTEP(0)->DOEPCTL = 0x80008000;\r\n  }\r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n\r\n/**\r\n  * @brief  Reset the USB Core (needed after USB clock settings change)\r\n  * @param  USBx : Selected device\r\n  * @retval HAL status\r\n  */\r\nstatic HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  uint32_t count = 0;\r\n\r\n  /* Wait for AHB master IDLE state. */\r\n  do\r\n  {\r\n    if (++count > 200000)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0);\r\n  \r\n  /* Core Soft Reset */\r\n  count = 0;\r\n  USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;\r\n\r\n  do\r\n  {\r\n    if (++count > 200000)\r\n    {\r\n      return HAL_TIMEOUT;\r\n    }\r\n  }\r\n  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  USB_HostInit : Initializes the USB OTG controller registers \r\n  *         for Host mode \r\n  * @param  USBx : Selected device\r\n  * @param  cfg  : pointer to a USB_OTG_CfgTypeDef structure that contains\r\n  *         the configuration information for the specified USBx peripheral.\r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)\r\n{\r\n  uint32_t i;\r\n  \r\n  /* Restart the Phy Clock */\r\n  USBx_PCGCCTL = 0;\r\n  \r\n  /*Activate VBUS Sensing B */\r\n  USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;\r\n  \r\n  /* Disable the FS/LS support mode only */\r\n  if((cfg.speed == USB_OTG_SPEED_FULL)&&\r\n     (USBx != USB_OTG_FS))\r\n  {\r\n    USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; \r\n  }\r\n  else\r\n  {\r\n    USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);  \r\n  }\r\n\r\n  /* Make sure the FIFOs are flushed. */\r\n  USB_FlushTxFifo(USBx, 0x10 ); /* all Tx FIFOs */\r\n  USB_FlushRxFifo(USBx);\r\n\r\n  /* Clear all pending HC Interrupts */\r\n  for (i = 0; i < cfg.Host_channels; i++)\r\n  {\r\n    USBx_HC(i)->HCINT = 0xFFFFFFFF;\r\n    USBx_HC(i)->HCINTMSK = 0;\r\n  }\r\n  \r\n  /* Enable VBUS driving */\r\n  USB_DriveVbus(USBx, 1);\r\n  \r\n  HAL_Delay(200);\r\n  \r\n  /* Disable all interrupts. */\r\n  USBx->GINTMSK = 0;\r\n  \r\n  /* Clear any pending interrupts */\r\n  USBx->GINTSTS = 0xFFFFFFFF;\r\n  \r\n  if(USBx == USB_OTG_FS)\r\n  {\r\n    /* set Rx FIFO size */\r\n    USBx->GRXFSIZ  = (uint32_t )0x80; \r\n    USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60 << 16)& USB_OTG_NPTXFD) | 0x80);\r\n    USBx->HPTXFSIZ = (uint32_t )(((0x40 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0);\r\n  }\r\n  else\r\n  {\r\n    /* set Rx FIFO size */\r\n    USBx->GRXFSIZ  = (uint32_t )0x200; \r\n    USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x100 << 16)& USB_OTG_NPTXFD) | 0x200);\r\n    USBx->HPTXFSIZ = (uint32_t )(((0xE0 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0x300);\r\n  }\r\n  \r\n  /* Enable the common interrupts */\r\n  if (cfg.dma_enable == DISABLE)\r\n  {\r\n    USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; \r\n  }\r\n  \r\n  /* Enable interrupts matching to the Host mode ONLY */\r\n  USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM            | USB_OTG_GINTMSK_HCIM |\\\r\n                    USB_OTG_GINTMSK_SOFM             |USB_OTG_GINTSTS_DISCINT|\\\r\n                    USB_OTG_GINTMSK_PXFRM_IISOOXFRM  | USB_OTG_GINTMSK_WUIM);\r\n\r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the \r\n  *         HCFG register on the PHY type and set the right frame interval\r\n  * @param  USBx : Selected device\r\n  * @param  freq : clock frequency\r\n  *          This parameter can be one of these values:\r\n  *           HCFG_48_MHZ : Full Speed 48 MHz Clock \r\n  *           HCFG_6_MHZ : Low Speed 6 MHz Clock \r\n  * @retval HAL status\r\n  */\r\nHAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq)\r\n{\r\n  USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);\r\n  USBx_HOST->HCFG |= (freq & USB_OTG_HCFG_FSLSPCS);\r\n  \r\n  if (freq ==  HCFG_48_MHZ)\r\n  {\r\n    USBx_HOST->HFIR = (uint32_t)48000;\r\n  }\r\n  else if (freq ==  HCFG_6_MHZ)\r\n  {\r\n    USBx_HOST->HFIR = (uint32_t)6000;\r\n  } \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n* @brief  USB_OTG_ResetPort : Reset Host Port\r\n  * @param  USBx : Selected device\r\n  * @retval HAL status\r\n  * @note : (1)The application must wait at least 10 ms\r\n  *   before clearing the reset bit.\r\n  */\r\nHAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  __IO uint32_t hprt0;\r\n  \r\n  hprt0 = USBx_HPRT0;\r\n  \r\n  hprt0 &= ~(USB_OTG_HPRT_PENA    | USB_OTG_HPRT_PCDET |\\\r\n    USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );\r\n  \r\n  USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);  \r\n  HAL_Delay (10);                                /* See Note #1 */\r\n  USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USB_DriveVbus : activate or de-activate vbus\r\n  * @param  state : VBUS state\r\n  *          This parameter can be one of these values:\r\n  *           0 : VBUS Active \r\n  *           1 : VBUS Inactive\r\n  * @retval HAL status\r\n*/\r\nHAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state)\r\n{\r\n  __IO uint32_t hprt0;\r\n\r\n  hprt0 = USBx_HPRT0;\r\n  hprt0 &= ~(USB_OTG_HPRT_PENA    | USB_OTG_HPRT_PCDET |\\\r\n                         USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );\r\n  \r\n  if (((hprt0 & USB_OTG_HPRT_PPWR) == 0 ) && (state == 1 ))\r\n  {\r\n    USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); \r\n  }\r\n  if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0 ))\r\n  {\r\n    USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0); \r\n  }\r\n  return HAL_OK; \r\n}\r\n\r\n/**\r\n  * @brief  Return Host Core speed\r\n  * @param  USBx : Selected device\r\n  * @retval speed : Host speed\r\n  *          This parameter can be one of these values:\r\n  *            @arg USB_OTG_SPEED_HIGH: High speed mode\r\n  *            @arg USB_OTG_SPEED_FULL: Full speed mode\r\n  *            @arg USB_OTG_SPEED_LOW: Low speed mode\r\n  */\r\nuint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  __IO uint32_t hprt0;\r\n  \r\n  hprt0 = USBx_HPRT0;\r\n  return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17);\r\n}\r\n\r\n/**\r\n  * @brief  Return Host Current Frame number\r\n  * @param  USBx : Selected device\r\n  * @retval current frame number\r\n*/\r\nuint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);\r\n}\r\n\r\n/**\r\n  * @brief  Initialize a host channel\r\n  * @param  USBx : Selected device\r\n  * @param  ch_num : Channel number\r\n  *         This parameter can be a value from 1 to 15\r\n  * @param  epnum : Endpoint number\r\n  *          This parameter can be a value from 1 to 15\r\n  * @param  dev_address : Current device address\r\n  *          This parameter can be a value from 0 to 255\r\n  * @param  speed : Current device speed\r\n  *          This parameter can be one of these values:\r\n  *            @arg USB_OTG_SPEED_HIGH: High speed mode\r\n  *            @arg USB_OTG_SPEED_FULL: Full speed mode\r\n  *            @arg USB_OTG_SPEED_LOW: Low speed mode\r\n  * @param  ep_type : Endpoint Type\r\n  *          This parameter can be one of these values:\r\n  *            @arg EP_TYPE_CTRL: Control type\r\n  *            @arg EP_TYPE_ISOC: Isochronous type\r\n  *            @arg EP_TYPE_BULK: Bulk type\r\n  *            @arg EP_TYPE_INTR: Interrupt type\r\n  * @param  mps : Max Packet Size\r\n  *          This parameter can be a value from 0 to32K\r\n  * @retval HAL state\r\n  */\r\nHAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,  \r\n                              uint8_t ch_num,\r\n                              uint8_t epnum,\r\n                              uint8_t dev_address,\r\n                              uint8_t speed,\r\n                              uint8_t ep_type,\r\n                              uint16_t mps)\r\n{\r\n    \r\n  /* Clear old interrupt conditions for this host channel. */\r\n  USBx_HC(ch_num)->HCINT = 0xFFFFFFFF;\r\n  \r\n  /* Enable channel interrupts required for this transfer. */\r\n  switch (ep_type) \r\n  {\r\n  case EP_TYPE_CTRL:\r\n  case EP_TYPE_BULK:\r\n    \r\n    USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |\\\r\n                                USB_OTG_HCINTMSK_STALLM |\\\r\n                                USB_OTG_HCINTMSK_TXERRM |\\\r\n                                USB_OTG_HCINTMSK_DTERRM |\\\r\n                                USB_OTG_HCINTMSK_AHBERR |\\\r\n                                USB_OTG_HCINTMSK_NAKM ;\r\n \r\n    if (epnum & 0x80) \r\n    {\r\n      USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;\r\n    } \r\n    else \r\n    {\r\n      if(USBx != USB_OTG_FS)\r\n      {\r\n        USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);\r\n      }\r\n    }\r\n    break;\r\n    \r\n  case EP_TYPE_INTR:\r\n    \r\n    USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |\\\r\n                                USB_OTG_HCINTMSK_STALLM |\\\r\n                                USB_OTG_HCINTMSK_TXERRM |\\\r\n                                USB_OTG_HCINTMSK_DTERRM |\\\r\n                                USB_OTG_HCINTMSK_NAKM   |\\\r\n                                USB_OTG_HCINTMSK_AHBERR |\\\r\n                                USB_OTG_HCINTMSK_FRMORM ;    \r\n    \r\n    if (epnum & 0x80) \r\n    {\r\n      USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;\r\n    }\r\n    \r\n    break;\r\n  case EP_TYPE_ISOC:\r\n    \r\n    USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |\\\r\n                                USB_OTG_HCINTMSK_ACKM   |\\\r\n                                USB_OTG_HCINTMSK_AHBERR |\\\r\n                                USB_OTG_HCINTMSK_FRMORM ;   \r\n    \r\n    if (epnum & 0x80) \r\n    {\r\n      USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);      \r\n    }\r\n    break;\r\n  }\r\n  \r\n  /* Enable the top level host channel interrupt. */\r\n  USBx_HOST->HAINTMSK |= (1 << ch_num);\r\n  \r\n  /* Make sure host channel interrupts are enabled. */\r\n  USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;\r\n  \r\n  /* Program the HCCHAR register */\r\n  USBx_HC(ch_num)->HCCHAR = (((dev_address << 22) & USB_OTG_HCCHAR_DAD)  |\\\r\n                             (((epnum & 0x7F)<< 11) & USB_OTG_HCCHAR_EPNUM)|\\\r\n                             ((((epnum & 0x80) == 0x80)<< 15) & USB_OTG_HCCHAR_EPDIR)|\\\r\n                             (((speed == HPRT0_PRTSPD_LOW_SPEED)<< 17) & USB_OTG_HCCHAR_LSDEV)|\\\r\n                             ((ep_type << 18) & USB_OTG_HCCHAR_EPTYP)|\\\r\n                             (mps & USB_OTG_HCCHAR_MPSIZ));\r\n    \r\n  if (ep_type == EP_TYPE_INTR)\r\n  {\r\n    USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ;\r\n  }\r\n\r\n  return HAL_OK; \r\n}\r\n\r\n/**\r\n  * @brief  Start a transfer over a host channel\r\n  * @param  USBx : Selected device\r\n  * @param  hc : pointer to host channel structure\r\n  * @param  dma: USB dma enabled or disabled \r\n  *          This parameter can be one of these values:\r\n  *           0 : DMA feature not used \r\n  *           1 : DMA feature used  \r\n  * @retval HAL state\r\n  */\r\n#if defined   (__CC_ARM) /*!< ARM Compiler */\r\n#pragma O0\r\n#elif defined (__GNUC__) /*!< GNU Compiler */\r\n#pragma GCC optimize (\"O0\")\r\n#endif /* __CC_ARM */\r\nHAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma)\r\n{\r\n  uint8_t  is_oddframe = 0; \r\n  uint16_t len_words = 0;   \r\n  uint16_t num_packets = 0;\r\n  uint16_t max_hc_pkt_count = 256;\r\n  uint32_t tmpreg = 0;\r\n    \r\n  if((USBx != USB_OTG_FS) && (hc->speed == USB_OTG_SPEED_HIGH))\r\n  {\r\n    if((dma == 0) && (hc->do_ping == 1))\r\n    {\r\n      USB_DoPing(USBx, hc->ch_num);\r\n      return HAL_OK;\r\n    }\r\n    else if(dma == 1)\r\n    {\r\n      USBx_HC(hc->ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);\r\n      hc->do_ping = 0;\r\n    }\r\n  }\r\n  \r\n  /* Compute the expected number of packets associated to the transfer */\r\n  if (hc->xfer_len > 0)\r\n  {\r\n    num_packets = (hc->xfer_len + hc->max_packet - 1) / hc->max_packet;\r\n    \r\n    if (num_packets > max_hc_pkt_count)\r\n    {\r\n      num_packets = max_hc_pkt_count;\r\n      hc->xfer_len = num_packets * hc->max_packet;\r\n    }\r\n  }\r\n  else\r\n  {\r\n    num_packets = 1;\r\n  }\r\n  if (hc->ep_is_in)\r\n  {\r\n    hc->xfer_len = num_packets * hc->max_packet;\r\n  }\r\n  \r\n  /* Initialize the HCTSIZn register */\r\n  USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) |\\\r\n    ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\\\r\n      (((hc->data_pid) << 29) & USB_OTG_HCTSIZ_DPID);\r\n  \r\n  if (dma)\r\n  {\r\n    /* xfer_buff MUST be 32-bits aligned */\r\n    USBx_HC(hc->ch_num)->HCDMA = (uint32_t)hc->xfer_buff;\r\n  }\r\n  \r\n  is_oddframe = (USBx_HOST->HFNUM & 0x01) ? 0 : 1;\r\n  USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;\r\n  USBx_HC(hc->ch_num)->HCCHAR |= (is_oddframe << 29);\r\n  \r\n  /* Set host channel enable */\r\n  tmpreg = USBx_HC(hc->ch_num)->HCCHAR;\r\n  tmpreg &= ~USB_OTG_HCCHAR_CHDIS;\r\n  tmpreg |= USB_OTG_HCCHAR_CHENA;\r\n  USBx_HC(hc->ch_num)->HCCHAR = tmpreg;\r\n  \r\n  if (dma == 0) /* Slave mode */\r\n  {  \r\n    if((hc->ep_is_in == 0) && (hc->xfer_len > 0))\r\n    {\r\n      switch(hc->ep_type) \r\n      {\r\n        /* Non periodic transfer */\r\n      case EP_TYPE_CTRL:\r\n      case EP_TYPE_BULK:\r\n        \r\n        len_words = (hc->xfer_len + 3) / 4;\r\n        \r\n        /* check if there is enough space in FIFO space */\r\n        if(len_words > (USBx->HNPTXSTS & 0xFFFF))\r\n        {\r\n          /* need to process data in nptxfempty interrupt */\r\n          USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;\r\n        }\r\n        break;\r\n        /* Periodic transfer */\r\n      case EP_TYPE_INTR:\r\n      case EP_TYPE_ISOC:\r\n        len_words = (hc->xfer_len + 3) / 4;\r\n        /* check if there is enough space in FIFO space */\r\n        if(len_words > (USBx_HOST->HPTXSTS & 0xFFFF)) /* split the transfer */\r\n        {\r\n          /* need to process data in ptxfempty interrupt */\r\n          USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;          \r\n        }\r\n        break;\r\n        \r\n      default:\r\n        break;\r\n      }\r\n      \r\n      /* Write packet into the Tx FIFO. */\r\n      USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, hc->xfer_len, 0);\r\n    }\r\n  }\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief Read all host channel interrupts status\r\n  * @param  USBx : Selected device\r\n  * @retval HAL state\r\n  */\r\nuint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  return ((USBx_HOST->HAINT) & 0xFFFF);\r\n}\r\n\r\n/**\r\n  * @brief  Halt a host channel\r\n  * @param  USBx : Selected device\r\n  * @param  hc_num : Host Channel number\r\n  *         This parameter can be a value from 1 to 15\r\n  * @retval HAL state\r\n  */\r\nHAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num)\r\n{\r\n  uint32_t count = 0;\r\n  \r\n  /* Check for space in the request queue to issue the halt. */\r\n  if (((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_CTRL << 18)) || ((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_BULK << 18)))\r\n  {\r\n    USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;\r\n    \r\n    if ((USBx->HNPTXSTS & 0xFFFF) == 0)\r\n    {\r\n      USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;\r\n      USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;  \r\n      USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;\r\n      do \r\n      {\r\n        if (++count > 1000) \r\n        {\r\n          break;\r\n        }\r\n      } \r\n      while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);     \r\n    }\r\n    else\r\n    {\r\n      USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; \r\n    }\r\n  }\r\n  else\r\n  {\r\n    USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;\r\n    \r\n    if ((USBx_HOST->HPTXSTS & 0xFFFF) == 0)\r\n    {\r\n      USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;\r\n      USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;  \r\n      USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;\r\n      do \r\n      {\r\n        if (++count > 1000) \r\n        {\r\n          break;\r\n        }\r\n      } \r\n      while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);     \r\n    }\r\n    else\r\n    {\r\n       USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; \r\n    }\r\n  }\r\n  \r\n  return HAL_OK;\r\n}\r\n\r\n/**\r\n  * @brief  Initiate Do Ping protocol\r\n  * @param  USBx : Selected device\r\n  * @param  hc_num : Host Channel number\r\n  *         This parameter can be a value from 1 to 15\r\n  * @retval HAL state\r\n  */\r\nHAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num)\r\n{\r\n  uint8_t  num_packets = 1;\r\n  uint32_t tmpreg = 0;\r\n\r\n  USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\\\r\n                                USB_OTG_HCTSIZ_DOPING;\r\n  \r\n  /* Set host channel enable */\r\n  tmpreg = USBx_HC(ch_num)->HCCHAR;\r\n  tmpreg &= ~USB_OTG_HCCHAR_CHDIS;\r\n  tmpreg |= USB_OTG_HCCHAR_CHENA;\r\n  USBx_HC(ch_num)->HCCHAR = tmpreg;\r\n  \r\n  return HAL_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  Stop Host Core\r\n  * @param  USBx : Selected device\r\n  * @retval HAL state\r\n  */\r\nHAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)\r\n{\r\n  uint8_t i;\r\n  uint32_t count = 0;\r\n  uint32_t value;\r\n  \r\n  USB_DisableGlobalInt(USBx);\r\n  \r\n    /* Flush FIFO */\r\n  USB_FlushTxFifo(USBx, 0x10);\r\n  USB_FlushRxFifo(USBx);\r\n  \r\n  /* Flush out any leftover queued requests. */\r\n  for (i = 0; i <= 15; i++)\r\n  {   \r\n\r\n    value = USBx_HC(i)->HCCHAR ;\r\n    value |=  USB_OTG_HCCHAR_CHDIS;\r\n    value &= ~USB_OTG_HCCHAR_CHENA;  \r\n    value &= ~USB_OTG_HCCHAR_EPDIR;\r\n    USBx_HC(i)->HCCHAR = value;\r\n  }\r\n  \r\n  /* Halt all channels to put them into a known state. */  \r\n  for (i = 0; i <= 15; i++)\r\n  {\r\n    value = USBx_HC(i)->HCCHAR ;\r\n    \r\n    value |= USB_OTG_HCCHAR_CHDIS;\r\n    value |= USB_OTG_HCCHAR_CHENA;  \r\n    value &= ~USB_OTG_HCCHAR_EPDIR;\r\n    \r\n    USBx_HC(i)->HCCHAR = value;\r\n    do \r\n    {\r\n      if (++count > 1000) \r\n      {\r\n        break;\r\n      }\r\n    } \r\n    while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);\r\n  }\r\n\r\n  /* Clear any pending Host interrupts */\r\n  USBx_HOST->HAINT = 0xFFFFFFFF;\r\n  USBx->GINTSTS = 0xFFFFFFFF;\r\n  USB_EnableGlobalInt(USBx);\r\n  return HAL_OK;  \r\n}\r\n/**\r\n  * @}\r\n  */\r\n\r\n#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */\r\n\r\n/**\r\n  * @}\r\n  */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Class/AUDIO/Inc/usbd_audio.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_audio.h\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   header file for the usbd_audio.c file.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n \r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __USB_AUDIO_H\r\n#define __USB_AUDIO_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include  \"usbd_ioreq.h\"\r\n\r\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup USBD_AUDIO\r\n  * @brief This file is the Header file for usbd_audio.c\r\n  * @{\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_AUDIO_Exported_Defines\r\n  * @{\r\n  */ \r\n#define AUDIO_OUT_EP                                  0x01\r\n#define USB_AUDIO_CONFIG_DESC_SIZ                     109\r\n#define AUDIO_INTERFACE_DESC_SIZE                     9\r\n#define USB_AUDIO_DESC_SIZ                            0x09\r\n#define AUDIO_STANDARD_ENDPOINT_DESC_SIZE             0x09\r\n#define AUDIO_STREAMING_ENDPOINT_DESC_SIZE            0x07\r\n\r\n#define AUDIO_DESCRIPTOR_TYPE                         0x21\r\n#define USB_DEVICE_CLASS_AUDIO                        0x01\r\n#define AUDIO_SUBCLASS_AUDIOCONTROL                   0x01\r\n#define AUDIO_SUBCLASS_AUDIOSTREAMING                 0x02\r\n#define AUDIO_PROTOCOL_UNDEFINED                      0x00\r\n#define AUDIO_STREAMING_GENERAL                       0x01\r\n#define AUDIO_STREAMING_FORMAT_TYPE                   0x02\r\n\r\n/* Audio Descriptor Types */\r\n#define AUDIO_INTERFACE_DESCRIPTOR_TYPE               0x24\r\n#define AUDIO_ENDPOINT_DESCRIPTOR_TYPE                0x25\r\n\r\n/* Audio Control Interface Descriptor Subtypes */\r\n#define AUDIO_CONTROL_HEADER                          0x01\r\n#define AUDIO_CONTROL_INPUT_TERMINAL                  0x02\r\n#define AUDIO_CONTROL_OUTPUT_TERMINAL                 0x03\r\n#define AUDIO_CONTROL_FEATURE_UNIT                    0x06\r\n\r\n#define AUDIO_INPUT_TERMINAL_DESC_SIZE                0x0C\r\n#define AUDIO_OUTPUT_TERMINAL_DESC_SIZE               0x09\r\n#define AUDIO_STREAMING_INTERFACE_DESC_SIZE           0x07\r\n\r\n#define AUDIO_CONTROL_MUTE                            0x0001\r\n\r\n#define AUDIO_FORMAT_TYPE_I                           0x01\r\n#define AUDIO_FORMAT_TYPE_III                         0x03\r\n\r\n#define AUDIO_ENDPOINT_GENERAL                        0x01\r\n\r\n#define AUDIO_REQ_GET_CUR                             0x81\r\n#define AUDIO_REQ_SET_CUR                             0x01\r\n\r\n#define AUDIO_OUT_STREAMING_CTRL                      0x02\r\n\r\n\r\n#define AUDIO_OUT_PACKET                              (uint32_t)(((USBD_AUDIO_FREQ * 2 * 2) /1000)) \r\n#define AUDIO_DEFAULT_VOLUME                          70\r\n    \r\n/* Number of sub-packets in the audio transfer buffer. You can modify this value but always make sure\r\n  that it is an even number and higher than 3 */\r\n#define AUDIO_OUT_PACKET_NUM                          80\r\n/* Total size of the audio transfer buffer */\r\n#define AUDIO_TOTAL_BUF_SIZE                          ((uint32_t)(AUDIO_OUT_PACKET * AUDIO_OUT_PACKET_NUM))\r\n    \r\n    /* Audio Commands enumeration */\r\ntypedef enum\r\n{\r\n  AUDIO_CMD_START = 1,\r\n  AUDIO_CMD_PLAY,\r\n  AUDIO_CMD_STOP,\r\n}AUDIO_CMD_TypeDef;\r\n\r\n\r\ntypedef enum\r\n{\r\n  AUDIO_OFFSET_NONE = 0,\r\n  AUDIO_OFFSET_HALF,\r\n  AUDIO_OFFSET_FULL,  \r\n  AUDIO_OFFSET_UNKNOWN,    \r\n}\r\nAUDIO_OffsetTypeDef;\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_CORE_Exported_TypesDefinitions\r\n  * @{\r\n  */\r\n typedef struct\r\n{\r\n   uint8_t cmd;   \r\n   uint8_t data[USB_MAX_EP0_SIZE];  \r\n   uint8_t len;  \r\n   uint8_t unit;    \r\n}\r\nUSBD_AUDIO_ControlTypeDef; \r\n\r\n\r\n\r\ntypedef struct\r\n{\r\n  __IO uint32_t             alt_setting; \r\n  uint8_t                   buffer[AUDIO_TOTAL_BUF_SIZE];\r\n  AUDIO_OffsetTypeDef       offset;\r\n  uint8_t                    rd_enable;  \r\n  uint16_t                   rd_ptr;  \r\n  uint16_t                   wr_ptr;  \r\n  USBD_AUDIO_ControlTypeDef control;   \r\n}\r\nUSBD_AUDIO_HandleTypeDef; \r\n\r\n\r\ntypedef struct\r\n{\r\n    int8_t  (*Init)         (uint32_t  AudioFreq, uint32_t Volume, uint32_t options);\r\n    int8_t  (*DeInit)       (uint32_t options);\r\n    int8_t  (*AudioCmd)     (uint8_t* pbuf, uint32_t size, uint8_t cmd);\r\n    int8_t  (*VolumeCtl)    (uint8_t vol);\r\n    int8_t  (*MuteCtl)      (uint8_t cmd);\r\n    int8_t  (*PeriodicTC)   (uint8_t cmd);\r\n    int8_t  (*GetState)     (void);\r\n}USBD_AUDIO_ItfTypeDef;\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n\r\n/** @defgroup USBD_CORE_Exported_Macros\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_CORE_Exported_Variables\r\n  * @{\r\n  */ \r\n\r\nextern USBD_ClassTypeDef  USBD_AUDIO;\r\n#define USBD_AUDIO_CLASS    &USBD_AUDIO\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USB_CORE_Exported_Functions\r\n  * @{\r\n  */ \r\nuint8_t  USBD_AUDIO_RegisterInterface  (USBD_HandleTypeDef   *pdev, \r\n                                        USBD_AUDIO_ItfTypeDef *fops);\r\n\r\nvoid  USBD_AUDIO_Sync (USBD_HandleTypeDef *pdev, AUDIO_OffsetTypeDef offset);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif  /* __USB_AUDIO_H */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Class/AUDIO/Inc/usbd_audio_if_template.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_audio_if_template.h\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   Header for usbd_audio_if_template.c file.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __USBD_AUDIO_IF_TEMPLATE_H\r\n#define __USBD_AUDIO_IF_TEMPLATE_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_audio.h\"\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\nextern USBD_AUDIO_ItfTypeDef  USBD_AUDIO_Template_fops;\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions ------------------------------------------------------- */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __USBD_AUDIO_IF_TEMPLATE_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_audio.c\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   This file provides the Audio core functions.\r\n  *\r\n  * @verbatim\r\n  *      \r\n  *          ===================================================================      \r\n  *                                AUDIO Class  Description\r\n  *          ===================================================================\r\n *           This driver manages the Audio Class 1.0 following the \"USB Device Class Definition for\r\n  *           Audio Devices V1.0 Mar 18, 98\".\r\n  *           This driver implements the following aspects of the specification:\r\n  *             - Device descriptor management\r\n  *             - Configuration descriptor management\r\n  *             - Standard AC Interface Descriptor management\r\n  *             - 1 Audio Streaming Interface (with single channel, PCM, Stereo mode)\r\n  *             - 1 Audio Streaming Endpoint\r\n  *             - 1 Audio Terminal Input (1 channel)\r\n  *             - Audio Class-Specific AC Interfaces\r\n  *             - Audio Class-Specific AS Interfaces\r\n  *             - AudioControl Requests: only SET_CUR and GET_CUR requests are supported (for Mute)\r\n  *             - Audio Feature Unit (limited to Mute control)\r\n  *             - Audio Synchronization type: Asynchronous\r\n  *             - Single fixed audio sampling rate (configurable in usbd_conf.h file)\r\n  *          The current audio class version supports the following audio features:\r\n  *             - Pulse Coded Modulation (PCM) format\r\n  *             - sampling rate: 48KHz. \r\n  *             - Bit resolution: 16\r\n  *             - Number of channels: 2\r\n  *             - No volume control\r\n  *             - Mute/Unmute capability\r\n  *             - Asynchronous Endpoints \r\n  *          \r\n  * @note     In HS mode and when the DMA is used, all variables and data structures\r\n  *           dealing with the DMA during the transaction process should be 32-bit aligned.\r\n  *           \r\n  *      \r\n  *  @endverbatim\r\n  *\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_audio.h\"\r\n#include \"usbd_desc.h\"\r\n#include \"usbd_ctlreq.h\"\r\n\r\n\r\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n\r\n\r\n/** @defgroup USBD_AUDIO \r\n  * @brief usbd core module\r\n  * @{\r\n  */ \r\n\r\n/** @defgroup USBD_AUDIO_Private_TypesDefinitions\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_AUDIO_Private_Defines\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_AUDIO_Private_Macros\r\n  * @{\r\n  */ \r\n#define AUDIO_SAMPLE_FREQ(frq)      (uint8_t)(frq), (uint8_t)((frq >> 8)), (uint8_t)((frq >> 16))\r\n\r\n#define AUDIO_PACKET_SZE(frq)          (uint8_t)(((frq * 2 * 2)/1000) & 0xFF), \\\r\n                                       (uint8_t)((((frq * 2 * 2)/1000) >> 8) & 0xFF)\r\n                                         \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n\r\n\r\n/** @defgroup USBD_AUDIO_Private_FunctionPrototypes\r\n  * @{\r\n  */\r\n\r\n\r\nstatic uint8_t  USBD_AUDIO_Init (USBD_HandleTypeDef *pdev, \r\n                               uint8_t cfgidx);\r\n\r\nstatic uint8_t  USBD_AUDIO_DeInit (USBD_HandleTypeDef *pdev, \r\n                                 uint8_t cfgidx);\r\n\r\nstatic uint8_t  USBD_AUDIO_Setup (USBD_HandleTypeDef *pdev, \r\n                                USBD_SetupReqTypedef *req);\r\n\r\nstatic uint8_t  *USBD_AUDIO_GetCfgDesc (uint16_t *length);\r\n\r\nstatic uint8_t  *USBD_AUDIO_GetDeviceQualifierDesc (uint16_t *length);\r\n\r\nstatic uint8_t  USBD_AUDIO_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum);\r\n\r\nstatic uint8_t  USBD_AUDIO_DataOut (USBD_HandleTypeDef *pdev, uint8_t epnum);\r\n\r\nstatic uint8_t  USBD_AUDIO_EP0_RxReady (USBD_HandleTypeDef *pdev);\r\n\r\nstatic uint8_t  USBD_AUDIO_EP0_TxReady (USBD_HandleTypeDef *pdev);\r\n\r\nstatic uint8_t  USBD_AUDIO_SOF (USBD_HandleTypeDef *pdev);\r\n\r\nstatic uint8_t  USBD_AUDIO_IsoINIncomplete (USBD_HandleTypeDef *pdev, uint8_t epnum);\r\n\r\nstatic uint8_t  USBD_AUDIO_IsoOutIncomplete (USBD_HandleTypeDef *pdev, uint8_t epnum);\r\n\r\nstatic void AUDIO_REQ_GetCurrent(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);\r\n\r\nstatic void AUDIO_REQ_SetCurrent(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_AUDIO_Private_Variables\r\n  * @{\r\n  */ \r\n\r\nUSBD_ClassTypeDef  USBD_AUDIO = \r\n{\r\n  USBD_AUDIO_Init,\r\n  USBD_AUDIO_DeInit,\r\n  USBD_AUDIO_Setup,\r\n  USBD_AUDIO_EP0_TxReady,  \r\n  USBD_AUDIO_EP0_RxReady,\r\n  USBD_AUDIO_DataIn,\r\n  USBD_AUDIO_DataOut,\r\n  USBD_AUDIO_SOF,\r\n  USBD_AUDIO_IsoINIncomplete,\r\n  USBD_AUDIO_IsoOutIncomplete,      \r\n  USBD_AUDIO_GetCfgDesc,\r\n  USBD_AUDIO_GetCfgDesc, \r\n  USBD_AUDIO_GetCfgDesc,\r\n  USBD_AUDIO_GetDeviceQualifierDesc,\r\n};\r\n\r\n/* USB AUDIO device Configuration Descriptor */\r\n__ALIGN_BEGIN static uint8_t USBD_AUDIO_CfgDesc[USB_AUDIO_CONFIG_DESC_SIZ] __ALIGN_END =\r\n{\r\n  /* Configuration 1 */\r\n  0x09,                                 /* bLength */\r\n  USB_DESC_TYPE_CONFIGURATION,          /* bDescriptorType */\r\n  LOBYTE(USB_AUDIO_CONFIG_DESC_SIZ),    /* wTotalLength  109 bytes*/\r\n  HIBYTE(USB_AUDIO_CONFIG_DESC_SIZ),      \r\n  0x02,                                 /* bNumInterfaces */\r\n  0x01,                                 /* bConfigurationValue */\r\n  0x00,                                 /* iConfiguration */\r\n  0xC0,                                 /* bmAttributes  BUS Powred*/\r\n  0x32,                                 /* bMaxPower = 100 mA*/\r\n  /* 09 byte*/\r\n  \r\n  /* USB Speaker Standard interface descriptor */\r\n  AUDIO_INTERFACE_DESC_SIZE,            /* bLength */\r\n  USB_DESC_TYPE_INTERFACE,              /* bDescriptorType */\r\n  0x00,                                 /* bInterfaceNumber */\r\n  0x00,                                 /* bAlternateSetting */\r\n  0x00,                                 /* bNumEndpoints */\r\n  USB_DEVICE_CLASS_AUDIO,               /* bInterfaceClass */\r\n  AUDIO_SUBCLASS_AUDIOCONTROL,          /* bInterfaceSubClass */\r\n  AUDIO_PROTOCOL_UNDEFINED,             /* bInterfaceProtocol */\r\n  0x00,                                 /* iInterface */\r\n  /* 09 byte*/\r\n  \r\n  /* USB Speaker Class-specific AC Interface Descriptor */\r\n  AUDIO_INTERFACE_DESC_SIZE,            /* bLength */\r\n  AUDIO_INTERFACE_DESCRIPTOR_TYPE,      /* bDescriptorType */\r\n  AUDIO_CONTROL_HEADER,                 /* bDescriptorSubtype */\r\n  0x00,          /* 1.00 */             /* bcdADC */\r\n  0x01,\r\n  0x27,                                 /* wTotalLength = 39*/\r\n  0x00,\r\n  0x01,                                 /* bInCollection */\r\n  0x01,                                 /* baInterfaceNr */\r\n  /* 09 byte*/\r\n  \r\n  /* USB Speaker Input Terminal Descriptor */\r\n  AUDIO_INPUT_TERMINAL_DESC_SIZE,       /* bLength */\r\n  AUDIO_INTERFACE_DESCRIPTOR_TYPE,      /* bDescriptorType */\r\n  AUDIO_CONTROL_INPUT_TERMINAL,         /* bDescriptorSubtype */\r\n  0x01,                                 /* bTerminalID */\r\n  0x01,                                 /* wTerminalType AUDIO_TERMINAL_USB_STREAMING   0x0101 */\r\n  0x01,\r\n  0x00,                                 /* bAssocTerminal */\r\n  0x01,                                 /* bNrChannels */\r\n  0x00,                                 /* wChannelConfig 0x0000  Mono */\r\n  0x00,\r\n  0x00,                                 /* iChannelNames */\r\n  0x00,                                 /* iTerminal */\r\n  /* 12 byte*/\r\n  \r\n  /* USB Speaker Audio Feature Unit Descriptor */\r\n  0x09,                                 /* bLength */\r\n  AUDIO_INTERFACE_DESCRIPTOR_TYPE,      /* bDescriptorType */\r\n  AUDIO_CONTROL_FEATURE_UNIT,           /* bDescriptorSubtype */\r\n  AUDIO_OUT_STREAMING_CTRL,             /* bUnitID */\r\n  0x01,                                 /* bSourceID */\r\n  0x01,                                 /* bControlSize */\r\n  AUDIO_CONTROL_MUTE,// |AUDIO_CONTROL_VOLUME, /* bmaControls(0) */\r\n  0,                                    /* bmaControls(1) */\r\n  0x00,                                 /* iTerminal */\r\n  /* 09 byte*/\r\n  \r\n  /*USB Speaker Output Terminal Descriptor */\r\n  0x09,      /* bLength */\r\n  AUDIO_INTERFACE_DESCRIPTOR_TYPE,      /* bDescriptorType */\r\n  AUDIO_CONTROL_OUTPUT_TERMINAL,        /* bDescriptorSubtype */\r\n  0x03,                                 /* bTerminalID */\r\n  0x01,                                 /* wTerminalType  0x0301*/\r\n  0x03,\r\n  0x00,                                 /* bAssocTerminal */\r\n  0x02,                                 /* bSourceID */\r\n  0x00,                                 /* iTerminal */\r\n  /* 09 byte*/\r\n  \r\n  /* USB Speaker Standard AS Interface Descriptor - Audio Streaming Zero Bandwith */\r\n  /* Interface 1, Alternate Setting 0                                             */\r\n  AUDIO_INTERFACE_DESC_SIZE,  /* bLength */\r\n  USB_DESC_TYPE_INTERFACE,        /* bDescriptorType */\r\n  0x01,                                 /* bInterfaceNumber */\r\n  0x00,                                 /* bAlternateSetting */\r\n  0x00,                                 /* bNumEndpoints */\r\n  USB_DEVICE_CLASS_AUDIO,               /* bInterfaceClass */\r\n  AUDIO_SUBCLASS_AUDIOSTREAMING,        /* bInterfaceSubClass */\r\n  AUDIO_PROTOCOL_UNDEFINED,             /* bInterfaceProtocol */\r\n  0x00,                                 /* iInterface */\r\n  /* 09 byte*/\r\n  \r\n  /* USB Speaker Standard AS Interface Descriptor - Audio Streaming Operational */\r\n  /* Interface 1, Alternate Setting 1                                           */\r\n  AUDIO_INTERFACE_DESC_SIZE,  /* bLength */\r\n  USB_DESC_TYPE_INTERFACE,        /* bDescriptorType */\r\n  0x01,                                 /* bInterfaceNumber */\r\n  0x01,                                 /* bAlternateSetting */\r\n  0x01,                                 /* bNumEndpoints */\r\n  USB_DEVICE_CLASS_AUDIO,               /* bInterfaceClass */\r\n  AUDIO_SUBCLASS_AUDIOSTREAMING,        /* bInterfaceSubClass */\r\n  AUDIO_PROTOCOL_UNDEFINED,             /* bInterfaceProtocol */\r\n  0x00,                                 /* iInterface */\r\n  /* 09 byte*/\r\n  \r\n  /* USB Speaker Audio Streaming Interface Descriptor */\r\n  AUDIO_STREAMING_INTERFACE_DESC_SIZE,  /* bLength */\r\n  AUDIO_INTERFACE_DESCRIPTOR_TYPE,      /* bDescriptorType */\r\n  AUDIO_STREAMING_GENERAL,              /* bDescriptorSubtype */\r\n  0x01,                                 /* bTerminalLink */\r\n  0x01,                                 /* bDelay */\r\n  0x01,                                 /* wFormatTag AUDIO_FORMAT_PCM  0x0001*/\r\n  0x00,\r\n  /* 07 byte*/\r\n  \r\n  /* USB Speaker Audio Type III Format Interface Descriptor */\r\n  0x0B,                                 /* bLength */\r\n  AUDIO_INTERFACE_DESCRIPTOR_TYPE,      /* bDescriptorType */\r\n  AUDIO_STREAMING_FORMAT_TYPE,          /* bDescriptorSubtype */\r\n  AUDIO_FORMAT_TYPE_III,                /* bFormatType */ \r\n  0x02,                                 /* bNrChannels */\r\n  0x02,                                 /* bSubFrameSize :  2 Bytes per frame (16bits) */\r\n  16,                                   /* bBitResolution (16-bits per sample) */ \r\n  0x01,                                 /* bSamFreqType only one frequency supported */ \r\n  AUDIO_SAMPLE_FREQ(USBD_AUDIO_FREQ),         /* Audio sampling frequency coded on 3 bytes */\r\n  /* 11 byte*/\r\n  \r\n  /* Endpoint 1 - Standard Descriptor */\r\n  AUDIO_STANDARD_ENDPOINT_DESC_SIZE,    /* bLength */\r\n  USB_DESC_TYPE_ENDPOINT,               /* bDescriptorType */\r\n  AUDIO_OUT_EP,                         /* bEndpointAddress 1 out endpoint*/\r\n  USBD_EP_TYPE_ISOC,                    /* bmAttributes */\r\n  AUDIO_PACKET_SZE(USBD_AUDIO_FREQ),    /* wMaxPacketSize in Bytes (Freq(Samples)*2(Stereo)*2(HalfWord)) */\r\n  0x01,                                 /* bInterval */\r\n  0x00,                                 /* bRefresh */\r\n  0x00,                                 /* bSynchAddress */\r\n  /* 09 byte*/\r\n  \r\n  /* Endpoint - Audio Streaming Descriptor*/\r\n  AUDIO_STREAMING_ENDPOINT_DESC_SIZE,   /* bLength */\r\n  AUDIO_ENDPOINT_DESCRIPTOR_TYPE,       /* bDescriptorType */\r\n  AUDIO_ENDPOINT_GENERAL,               /* bDescriptor */\r\n  0x00,                                 /* bmAttributes */\r\n  0x00,                                 /* bLockDelayUnits */\r\n  0x00,                                 /* wLockDelay */\r\n  0x00,\r\n  /* 07 byte*/\r\n} ;\r\n\r\n/* USB Standard Device Descriptor */\r\n__ALIGN_BEGIN static uint8_t USBD_AUDIO_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END=\r\n{\r\n  USB_LEN_DEV_QUALIFIER_DESC,\r\n  USB_DESC_TYPE_DEVICE_QUALIFIER,\r\n  0x00,\r\n  0x02,\r\n  0x00,\r\n  0x00,\r\n  0x00,\r\n  0x40,\r\n  0x01,\r\n  0x00,\r\n};\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_AUDIO_Private_Functions\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @brief  USBD_AUDIO_Init\r\n  *         Initialize the AUDIO interface\r\n  * @param  pdev: device instance\r\n  * @param  cfgidx: Configuration index\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_AUDIO_Init (USBD_HandleTypeDef *pdev, \r\n                               uint8_t cfgidx)\r\n{\r\n  USBD_AUDIO_HandleTypeDef   *haudio;\r\n  \r\n  /* Open EP OUT */\r\n  USBD_LL_OpenEP(pdev,\r\n                 AUDIO_OUT_EP,\r\n                 USBD_EP_TYPE_ISOC,\r\n                 AUDIO_OUT_PACKET);\r\n  \r\n  /* Allocate Audio structure */\r\n  pdev->pClassData = USBD_malloc(sizeof (USBD_AUDIO_HandleTypeDef));\r\n  \r\n  if(pdev->pClassData == NULL)\r\n  {\r\n    return USBD_FAIL; \r\n  }\r\n  else\r\n  {\r\n    haudio = (USBD_AUDIO_HandleTypeDef*) pdev->pClassData;\r\n    haudio->alt_setting = 0;\r\n    haudio->offset = AUDIO_OFFSET_UNKNOWN;\r\n    haudio->wr_ptr = 0; \r\n    haudio->rd_ptr = 0;  \r\n    haudio->rd_enable = 0;\r\n    \r\n    /* Initialize the Audio output Hardware layer */\r\n    if (((USBD_AUDIO_ItfTypeDef *)pdev->pUserData)->Init(USBD_AUDIO_FREQ, AUDIO_DEFAULT_VOLUME, 0) != USBD_OK)\r\n    {\r\n      return USBD_FAIL;\r\n    }\r\n    \r\n    /* Prepare Out endpoint to receive 1st packet */ \r\n    USBD_LL_PrepareReceive(pdev,\r\n                           AUDIO_OUT_EP,\r\n                           haudio->buffer,                        \r\n                           AUDIO_OUT_PACKET);      \r\n  }\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_AUDIO_Init\r\n  *         DeInitialize the AUDIO layer\r\n  * @param  pdev: device instance\r\n  * @param  cfgidx: Configuration index\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_AUDIO_DeInit (USBD_HandleTypeDef *pdev, \r\n                                 uint8_t cfgidx)\r\n{\r\n  \r\n  /* Open EP OUT */\r\n  USBD_LL_CloseEP(pdev,\r\n              AUDIO_OUT_EP);\r\n\r\n  /* DeInit  physical Interface components */\r\n  if(pdev->pClassData != NULL)\r\n  {\r\n   ((USBD_AUDIO_ItfTypeDef *)pdev->pUserData)->DeInit(0);\r\n    USBD_free(pdev->pClassData);\r\n    pdev->pClassData = NULL;\r\n  }\r\n  \r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_AUDIO_Setup\r\n  *         Handle the AUDIO specific requests\r\n  * @param  pdev: instance\r\n  * @param  req: usb requests\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_AUDIO_Setup (USBD_HandleTypeDef *pdev, \r\n                                USBD_SetupReqTypedef *req)\r\n{\r\n  USBD_AUDIO_HandleTypeDef   *haudio;\r\n  uint16_t len;\r\n  uint8_t *pbuf;\r\n  uint8_t ret = USBD_OK;\r\n  haudio = (USBD_AUDIO_HandleTypeDef*) pdev->pClassData;\r\n  \r\n  switch (req->bmRequest & USB_REQ_TYPE_MASK)\r\n  {\r\n  case USB_REQ_TYPE_CLASS :  \r\n    switch (req->bRequest)\r\n    {\r\n    case AUDIO_REQ_GET_CUR:\r\n      AUDIO_REQ_GetCurrent(pdev, req);\r\n      break;\r\n      \r\n    case AUDIO_REQ_SET_CUR:\r\n      AUDIO_REQ_SetCurrent(pdev, req);   \r\n      break;\r\n      \r\n    default:\r\n      USBD_CtlError (pdev, req);\r\n      ret = USBD_FAIL; \r\n    }\r\n    break;\r\n    \r\n  case USB_REQ_TYPE_STANDARD:\r\n    switch (req->bRequest)\r\n    {\r\n    case USB_REQ_GET_DESCRIPTOR:      \r\n      if( (req->wValue >> 8) == AUDIO_DESCRIPTOR_TYPE)\r\n      {\r\n        pbuf = USBD_AUDIO_CfgDesc + 18;\r\n        len = MIN(USB_AUDIO_DESC_SIZ , req->wLength);\r\n        \r\n        \r\n        USBD_CtlSendData (pdev, \r\n                          pbuf,\r\n                          len);\r\n      }\r\n      break;\r\n      \r\n    case USB_REQ_GET_INTERFACE :\r\n      USBD_CtlSendData (pdev,\r\n                        (uint8_t *)&(haudio->alt_setting),\r\n                        1);\r\n      break;\r\n      \r\n    case USB_REQ_SET_INTERFACE :\r\n      if ((uint8_t)(req->wValue) <= USBD_MAX_NUM_INTERFACES)\r\n      {\r\n        haudio->alt_setting = (uint8_t)(req->wValue);\r\n      }\r\n      else\r\n      {\r\n        /* Call the error management function (command will be nacked */\r\n        USBD_CtlError (pdev, req);\r\n      }\r\n      break;      \r\n      \r\n    default:\r\n      USBD_CtlError (pdev, req);\r\n      ret = USBD_FAIL;     \r\n    }\r\n  }\r\n  return ret;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  USBD_AUDIO_GetCfgDesc \r\n  *         return configuration descriptor\r\n  * @param  speed : current device speed\r\n  * @param  length : pointer data length\r\n  * @retval pointer to descriptor buffer\r\n  */\r\nstatic uint8_t  *USBD_AUDIO_GetCfgDesc (uint16_t *length)\r\n{\r\n  *length = sizeof (USBD_AUDIO_CfgDesc);\r\n  return USBD_AUDIO_CfgDesc;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_AUDIO_DataIn\r\n  *         handle data IN Stage\r\n  * @param  pdev: device instance\r\n  * @param  epnum: endpoint index\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_AUDIO_DataIn (USBD_HandleTypeDef *pdev, \r\n                              uint8_t epnum)\r\n{\r\n\r\n  /* Only OUT data are processed */\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_AUDIO_EP0_RxReady\r\n  *         handle EP0 Rx Ready event\r\n  * @param  pdev: device instance\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_AUDIO_EP0_RxReady (USBD_HandleTypeDef *pdev)\r\n{\r\n  USBD_AUDIO_HandleTypeDef   *haudio;\r\n  haudio = (USBD_AUDIO_HandleTypeDef*) pdev->pClassData;\r\n  \r\n  if (haudio->control.cmd == AUDIO_REQ_SET_CUR)\r\n  {/* In this driver, to simplify code, only SET_CUR request is managed */\r\n\r\n    if (haudio->control.unit == AUDIO_OUT_STREAMING_CTRL)\r\n    {\r\n     ((USBD_AUDIO_ItfTypeDef *)pdev->pUserData)->MuteCtl(haudio->control.data[0]);     \r\n      haudio->control.cmd = 0;\r\n      haudio->control.len = 0;\r\n    }\r\n  } \r\n\r\n  return USBD_OK;\r\n}\r\n/**\r\n  * @brief  USBD_AUDIO_EP0_TxReady\r\n  *         handle EP0 TRx Ready event\r\n  * @param  pdev: device instance\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_AUDIO_EP0_TxReady (USBD_HandleTypeDef *pdev)\r\n{\r\n  /* Only OUT control data are processed */\r\n  return USBD_OK;\r\n}\r\n/**\r\n  * @brief  USBD_AUDIO_SOF\r\n  *         handle SOF event\r\n  * @param  pdev: device instance\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_AUDIO_SOF (USBD_HandleTypeDef *pdev)\r\n{\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_AUDIO_SOF\r\n  *         handle SOF event\r\n  * @param  pdev: device instance\r\n  * @retval status\r\n  */\r\nvoid  USBD_AUDIO_Sync (USBD_HandleTypeDef *pdev, AUDIO_OffsetTypeDef offset)\r\n{\r\n  int8_t shift = 0;\r\n  USBD_AUDIO_HandleTypeDef   *haudio;\r\n  haudio = (USBD_AUDIO_HandleTypeDef*) pdev->pClassData;\r\n  \r\n  haudio->offset =  offset; \r\n  \r\n  \r\n  if(haudio->rd_enable == 1)\r\n  {\r\n    haudio->rd_ptr += AUDIO_TOTAL_BUF_SIZE/2;\r\n    \r\n    if (haudio->rd_ptr == AUDIO_TOTAL_BUF_SIZE)\r\n    {\r\n      /* roll back */\r\n      haudio->rd_ptr = 0;\r\n    }\r\n  }\r\n  \r\n  if(haudio->rd_ptr > haudio->wr_ptr)\r\n  {\r\n    if((haudio->rd_ptr - haudio->wr_ptr) < AUDIO_OUT_PACKET)\r\n    {\r\n      shift = -4;\r\n    }\r\n    else if((haudio->rd_ptr - haudio->wr_ptr) > (AUDIO_TOTAL_BUF_SIZE - AUDIO_OUT_PACKET))\r\n    {\r\n      shift = 4;\r\n    }    \r\n\r\n  }\r\n  else\r\n  {\r\n    if((haudio->wr_ptr - haudio->rd_ptr) < AUDIO_OUT_PACKET)\r\n    {\r\n      shift = 4;\r\n    }\r\n    else if((haudio->wr_ptr - haudio->rd_ptr) > (AUDIO_TOTAL_BUF_SIZE - AUDIO_OUT_PACKET))\r\n    {\r\n      shift = -4;\r\n    }  \r\n  }\r\n\r\n  if(haudio->offset == AUDIO_OFFSET_FULL)\r\n  {\r\n    ((USBD_AUDIO_ItfTypeDef *)pdev->pUserData)->AudioCmd(&haudio->buffer[0],\r\n                                                         AUDIO_TOTAL_BUF_SIZE/2 - shift,\r\n                                                         AUDIO_CMD_PLAY); \r\n      haudio->offset = AUDIO_OFFSET_NONE;           \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  USBD_AUDIO_IsoINIncomplete\r\n  *         handle data ISO IN Incomplete event\r\n  * @param  pdev: device instance\r\n  * @param  epnum: endpoint index\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_AUDIO_IsoINIncomplete (USBD_HandleTypeDef *pdev, uint8_t epnum)\r\n{\r\n\r\n  return USBD_OK;\r\n}\r\n/**\r\n  * @brief  USBD_AUDIO_IsoOutIncomplete\r\n  *         handle data ISO OUT Incomplete event\r\n  * @param  pdev: device instance\r\n  * @param  epnum: endpoint index\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_AUDIO_IsoOutIncomplete (USBD_HandleTypeDef *pdev, uint8_t epnum)\r\n{\r\n\r\n  return USBD_OK;\r\n}\r\n/**\r\n  * @brief  USBD_AUDIO_DataOut\r\n  *         handle data OUT Stage\r\n  * @param  pdev: device instance\r\n  * @param  epnum: endpoint index\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_AUDIO_DataOut (USBD_HandleTypeDef *pdev, \r\n                              uint8_t epnum)\r\n{\r\n  USBD_AUDIO_HandleTypeDef   *haudio;\r\n  haudio = (USBD_AUDIO_HandleTypeDef*) pdev->pClassData;\r\n  \r\n  if (epnum == AUDIO_OUT_EP)\r\n  {\r\n    /* Increment the Buffer pointer or roll it back when all buffers are full */\r\n    \r\n    haudio->wr_ptr += AUDIO_OUT_PACKET;\r\n    \r\n    if (haudio->wr_ptr == AUDIO_TOTAL_BUF_SIZE)\r\n    {/* All buffers are full: roll back */\r\n      haudio->wr_ptr = 0;\r\n      \r\n      if(haudio->offset == AUDIO_OFFSET_UNKNOWN)\r\n      {\r\n        ((USBD_AUDIO_ItfTypeDef *)pdev->pUserData)->AudioCmd(&haudio->buffer[0],\r\n                                                             AUDIO_TOTAL_BUF_SIZE/2,\r\n                                                             AUDIO_CMD_START);\r\n          haudio->offset = AUDIO_OFFSET_NONE;\r\n      }\r\n    }\r\n    \r\n    if(haudio->rd_enable == 0)\r\n    {\r\n      if (haudio->wr_ptr == (AUDIO_TOTAL_BUF_SIZE / 2))\r\n      {\r\n        haudio->rd_enable = 1; \r\n      }\r\n    }\r\n    \r\n    /* Prepare Out endpoint to receive next audio packet */\r\n    USBD_LL_PrepareReceive(pdev,\r\n                           AUDIO_OUT_EP,\r\n                           &haudio->buffer[haudio->wr_ptr], \r\n                           AUDIO_OUT_PACKET);  \r\n      \r\n  }\r\n  \r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  AUDIO_Req_GetCurrent\r\n  *         Handles the GET_CUR Audio control request.\r\n  * @param  pdev: instance\r\n  * @param  req: setup class request\r\n  * @retval status\r\n  */\r\nstatic void AUDIO_REQ_GetCurrent(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)\r\n{  \r\n  USBD_AUDIO_HandleTypeDef   *haudio;\r\n  haudio = (USBD_AUDIO_HandleTypeDef*) pdev->pClassData;\r\n  \r\n  memset(haudio->control.data, 0, 64);\r\n  /* Send the current mute state */\r\n  USBD_CtlSendData (pdev, \r\n                    haudio->control.data,\r\n                    req->wLength);\r\n}\r\n\r\n/**\r\n  * @brief  AUDIO_Req_SetCurrent\r\n  *         Handles the SET_CUR Audio control request.\r\n  * @param  pdev: instance\r\n  * @param  req: setup class request\r\n  * @retval status\r\n  */\r\nstatic void AUDIO_REQ_SetCurrent(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)\r\n{ \r\n  USBD_AUDIO_HandleTypeDef   *haudio;\r\n  haudio = (USBD_AUDIO_HandleTypeDef*) pdev->pClassData;\r\n  \r\n  if (req->wLength)\r\n  {\r\n    /* Prepare the reception of the buffer over EP0 */\r\n    USBD_CtlPrepareRx (pdev,\r\n                       haudio->control.data,                                  \r\n                       req->wLength);    \r\n    \r\n    haudio->control.cmd = AUDIO_REQ_SET_CUR;     /* Set the request value */\r\n    haudio->control.len = req->wLength;          /* Set the request data length */\r\n    haudio->control.unit = HIBYTE(req->wIndex);  /* Set the request target unit */\r\n  }\r\n}\r\n\r\n\r\n/**\r\n* @brief  DeviceQualifierDescriptor \r\n*         return Device Qualifier descriptor\r\n* @param  length : pointer data length\r\n* @retval pointer to descriptor buffer\r\n*/\r\nstatic uint8_t  *USBD_AUDIO_GetDeviceQualifierDesc (uint16_t *length)\r\n{\r\n  *length = sizeof (USBD_AUDIO_DeviceQualifierDesc);\r\n  return USBD_AUDIO_DeviceQualifierDesc;\r\n}\r\n\r\n/**\r\n* @brief  USBD_AUDIO_RegisterInterface\r\n* @param  fops: Audio interface callback\r\n* @retval status\r\n*/\r\nuint8_t  USBD_AUDIO_RegisterInterface  (USBD_HandleTypeDef   *pdev, \r\n                                        USBD_AUDIO_ItfTypeDef *fops)\r\n{\r\n  if(fops != NULL)\r\n  {\r\n    pdev->pUserData= fops;\r\n  }\r\n  return 0;\r\n}\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio_if_template.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_cdc_if_template.c\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   Generic media access Layer.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_audio_if_template.h\"\r\n\r\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n\r\n\r\n/** @defgroup USBD_AUDIO \r\n  * @brief usbd core module\r\n  * @{\r\n  */ \r\n\r\n/** @defgroup USBD_AUDIO_Private_TypesDefinitions\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_AUDIO_Private_Defines\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_AUDIO_Private_Macros\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_AUDIO_Private_FunctionPrototypes\r\n  * @{\r\n  */\r\n\r\nstatic int8_t  TEMPLATE_Init         (uint32_t  AudioFreq, uint32_t Volume, uint32_t options);\r\nstatic int8_t  TEMPLATE_DeInit       (uint32_t options);\r\nstatic int8_t  TEMPLATE_AudioCmd     (uint8_t* pbuf, uint32_t size, uint8_t cmd);\r\nstatic int8_t  TEMPLATE_VolumeCtl    (uint8_t vol);\r\nstatic int8_t  TEMPLATE_MuteCtl      (uint8_t cmd);\r\nstatic int8_t  TEMPLATE_PeriodicTC   (uint8_t cmd);\r\nstatic int8_t  TEMPLATE_GetState     (void);\r\n\r\nUSBD_AUDIO_ItfTypeDef USBD_AUDIO_Template_fops = \r\n{\r\n  TEMPLATE_Init,\r\n  TEMPLATE_DeInit,\r\n  TEMPLATE_AudioCmd,\r\n  TEMPLATE_VolumeCtl,\r\n  TEMPLATE_MuteCtl,\r\n  TEMPLATE_PeriodicTC,\r\n  TEMPLATE_GetState,\r\n};\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/**\r\n  * @brief  TEMPLATE_Init\r\n  *         Initializes the AUDIO media low layer\r\n  * @param  None\r\n  * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL\r\n  */\r\nstatic int8_t TEMPLATE_Init(uint32_t  AudioFreq, uint32_t Volume, uint32_t options)\r\n{\r\n  /*\r\n     Add your initialization code here \r\n  */  \r\n  return (0);\r\n}\r\n\r\n/**\r\n  * @brief  TEMPLATE_DeInit\r\n  *         DeInitializes the AUDIO media low layer\r\n  * @param  None\r\n  * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL\r\n  */\r\nstatic int8_t TEMPLATE_DeInit(uint32_t options)\r\n{\r\n  /*\r\n     Add your deinitialization code here \r\n  */  \r\n  return (0);\r\n}\r\n\r\n\r\n/**\r\n  * @brief  TEMPLATE_AudioCmd\r\n  *         AUDIO command handler \r\n  * @param  Buf: Buffer of data to be sent\r\n  * @param  size: Number of data to be sent (in bytes)\r\n  * @param  cmd: command opcode\r\n  * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL\r\n  */\r\nstatic int8_t TEMPLATE_AudioCmd (uint8_t* pbuf, uint32_t size, uint8_t cmd)\r\n{\r\n\r\n  return (0);\r\n}\r\n\r\n/**\r\n  * @brief  TEMPLATE_VolumeCtl              \r\n  * @param  vol: volume level (0..100)\r\n  * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL\r\n  */\r\nstatic int8_t TEMPLATE_VolumeCtl (uint8_t vol)\r\n{\r\n \r\n  return (0);\r\n}\r\n\r\n/**\r\n  * @brief  TEMPLATE_MuteCtl              \r\n  * @param  cmd: vmute command\r\n  * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL\r\n  */\r\nstatic int8_t TEMPLATE_MuteCtl (uint8_t cmd)\r\n{\r\n \r\n  return (0);\r\n}\r\n\r\n/**\r\n  * @brief  TEMPLATE_PeriodicTC              \r\n  * @param  cmd\r\n  * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL\r\n  */\r\nstatic int8_t TEMPLATE_PeriodicTC (uint8_t cmd)\r\n{\r\n \r\n  return (0);\r\n}\r\n\r\n/**\r\n  * @brief  TEMPLATE_GetState              \r\n  * @param  None\r\n  * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL\r\n  */\r\nstatic int8_t TEMPLATE_GetState (void)\r\n{\r\n \r\n  return (0);\r\n}\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_cdc.h\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   header file for the usbd_cdc.c file.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n \r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __USB_CDC_H\r\n#define __USB_CDC_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include  \"usbd_ioreq.h\"\r\n\r\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup usbd_cdc\r\n  * @brief This file is the Header file for usbd_cdc.c\r\n  * @{\r\n  */ \r\n\r\n\r\n/** @defgroup usbd_cdc_Exported_Defines\r\n  * @{\r\n  */ \r\n#define CDC_IN_EP                                   0x81  /* EP1 for data IN */\r\n#define CDC_OUT_EP                                  0x01  /* EP1 for data OUT */\r\n#define CDC_CMD_EP                                  0x82  /* EP2 for CDC commands */\r\n\r\n/* CDC Endpoints parameters: you can fine tune these values depending on the needed baudrates and performance. */\r\n#define CDC_DATA_HS_MAX_PACKET_SIZE                 512  /* Endpoint IN & OUT Packet size */\r\n#define CDC_DATA_FS_MAX_PACKET_SIZE                 64  /* Endpoint IN & OUT Packet size */\r\n#define CDC_CMD_PACKET_SIZE                         8  /* Control Endpoint Packet size */ \r\n\r\n#define USB_CDC_CONFIG_DESC_SIZ                     67\r\n#define CDC_DATA_HS_IN_PACKET_SIZE                  CDC_DATA_HS_MAX_PACKET_SIZE\r\n#define CDC_DATA_HS_OUT_PACKET_SIZE                 CDC_DATA_HS_MAX_PACKET_SIZE\r\n\r\n#define CDC_DATA_FS_IN_PACKET_SIZE                  CDC_DATA_FS_MAX_PACKET_SIZE\r\n#define CDC_DATA_FS_OUT_PACKET_SIZE                 CDC_DATA_FS_MAX_PACKET_SIZE\r\n\r\n/*---------------------------------------------------------------------*/\r\n/*  CDC definitions                                                    */\r\n/*---------------------------------------------------------------------*/\r\n#define CDC_SEND_ENCAPSULATED_COMMAND               0x00\r\n#define CDC_GET_ENCAPSULATED_RESPONSE               0x01\r\n#define CDC_SET_COMM_FEATURE                        0x02\r\n#define CDC_GET_COMM_FEATURE                        0x03\r\n#define CDC_CLEAR_COMM_FEATURE                      0x04\r\n#define CDC_SET_LINE_CODING                         0x20\r\n#define CDC_GET_LINE_CODING                         0x21\r\n#define CDC_SET_CONTROL_LINE_STATE                  0x22\r\n#define CDC_SEND_BREAK                              0x23\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_CORE_Exported_TypesDefinitions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\ntypedef struct\r\n{\r\n  uint32_t bitrate;\r\n  uint8_t  format;\r\n  uint8_t  paritytype;\r\n  uint8_t  datatype;\r\n}USBD_CDC_LineCodingTypeDef;\r\n\r\ntypedef struct _USBD_CDC_Itf\r\n{\r\n  int8_t (* Init)          (void);\r\n  int8_t (* DeInit)        (void);\r\n  int8_t (* Control)       (uint8_t, uint8_t * , uint16_t);   \r\n  int8_t (* Receive)       (uint8_t *, uint32_t *);  \r\n\r\n}USBD_CDC_ItfTypeDef;\r\n\r\n\r\ntypedef struct\r\n{\r\n  uint32_t data[CDC_DATA_HS_MAX_PACKET_SIZE/4];      /* Force 32bits alignment */\r\n  uint8_t  CmdOpCode;\r\n  uint8_t  CmdLength;    \r\n  uint8_t  *RxBuffer;  \r\n  uint8_t  *TxBuffer;   \r\n  uint32_t RxLength;\r\n  uint32_t TxLength;    \r\n  \r\n  __IO uint32_t TxState;     \r\n  __IO uint32_t RxState;    \r\n}\r\nUSBD_CDC_HandleTypeDef; \r\n\r\n\r\n\r\n/** @defgroup USBD_CORE_Exported_Macros\r\n  * @{\r\n  */ \r\n  \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_CORE_Exported_Variables\r\n  * @{\r\n  */ \r\n\r\nextern USBD_ClassTypeDef  USBD_CDC;\r\n#define USBD_CDC_CLASS    &USBD_CDC\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USB_CORE_Exported_Functions\r\n  * @{\r\n  */\r\nuint8_t  USBD_CDC_RegisterInterface  (USBD_HandleTypeDef   *pdev, \r\n                                      USBD_CDC_ItfTypeDef *fops);\r\n\r\nuint8_t  USBD_CDC_SetTxBuffer        (USBD_HandleTypeDef   *pdev,\r\n                                      uint8_t  *pbuff,\r\n                                      uint16_t length);\r\n\r\nuint8_t  USBD_CDC_SetRxBuffer        (USBD_HandleTypeDef   *pdev,\r\n                                      uint8_t  *pbuff);\r\n  \r\nuint8_t  USBD_CDC_ReceivePacket      (USBD_HandleTypeDef *pdev);\r\n\r\nuint8_t  USBD_CDC_TransmitPacket     (USBD_HandleTypeDef *pdev);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif  /* __USB_CDC_H */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc_if_template.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_cdc_if_template.h\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   Header for usbd_cdc_if_template.c file.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __USBD_CDC_IF_TEMPLATE_H\r\n#define __USBD_CDC_IF_TEMPLATE_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_cdc.h\"\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n\r\nextern USBD_CDC_ItfTypeDef  USBD_CDC_Template_fops;\r\n\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions ------------------------------------------------------- */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __USBD_CDC_IF_TEMPLATE_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_cdc.c\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   This file provides the high layer firmware functions to manage the \r\n  *          following functionalities of the USB CDC Class:\r\n  *           - Initialization and Configuration of high and low layer\r\n  *           - Enumeration as CDC Device (and enumeration for each implemented memory interface)\r\n  *           - OUT/IN data transfer\r\n  *           - Command IN transfer (class requests management)\r\n  *           - Error management\r\n  *           \r\n  *  @verbatim\r\n  *      \r\n  *          ===================================================================      \r\n  *                                CDC Class Driver Description\r\n  *          =================================================================== \r\n  *           This driver manages the \"Universal Serial Bus Class Definitions for Communications Devices\r\n  *           Revision 1.2 November 16, 2007\" and the sub-protocol specification of \"Universal Serial Bus \r\n  *           Communications Class Subclass Specification for PSTN Devices Revision 1.2 February 9, 2007\"\r\n  *           This driver implements the following aspects of the specification:\r\n  *             - Device descriptor management\r\n  *             - Configuration descriptor management\r\n  *             - Enumeration as CDC device with 2 data endpoints (IN and OUT) and 1 command endpoint (IN)\r\n  *             - Requests management (as described in section 6.2 in specification)\r\n  *             - Abstract Control Model compliant\r\n  *             - Union Functional collection (using 1 IN endpoint for control)\r\n  *             - Data interface class\r\n  * \r\n  *           These aspects may be enriched or modified for a specific user application.\r\n  *          \r\n  *            This driver doesn't implement the following aspects of the specification \r\n  *            (but it is possible to manage these features with some modifications on this driver):\r\n  *             - Any class-specific aspect relative to communication classes should be managed by user application.\r\n  *             - All communication classes other than PSTN are not managed\r\n  *      \r\n  *  @endverbatim\r\n  *                                  \r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"USBD_CDC.h\"\r\n#include \"usbd_desc.h\"\r\n#include \"usbd_ctlreq.h\"\r\n\r\n\r\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n\r\n\r\n/** @defgroup USBD_CDC \r\n  * @brief usbd core module\r\n  * @{\r\n  */ \r\n\r\n/** @defgroup USBD_CDC_Private_TypesDefinitions\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_CDC_Private_Defines\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_CDC_Private_Macros\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_CDC_Private_FunctionPrototypes\r\n  * @{\r\n  */\r\n\r\n\r\nstatic uint8_t  USBD_CDC_Init (USBD_HandleTypeDef *pdev, \r\n                               uint8_t cfgidx);\r\n\r\nstatic uint8_t  USBD_CDC_DeInit (USBD_HandleTypeDef *pdev, \r\n                                 uint8_t cfgidx);\r\n\r\nstatic uint8_t  USBD_CDC_Setup (USBD_HandleTypeDef *pdev, \r\n                                USBD_SetupReqTypedef *req);\r\n\r\nstatic uint8_t  USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, \r\n                                 uint8_t epnum);\r\n\r\nstatic uint8_t  USBD_CDC_DataOut (USBD_HandleTypeDef *pdev, \r\n                                 uint8_t epnum);\r\n\r\nstatic uint8_t  USBD_CDC_EP0_RxReady (USBD_HandleTypeDef *pdev);\r\n\r\nstatic uint8_t  *USBD_CDC_GetFSCfgDesc (uint16_t *length);\r\n\r\nstatic uint8_t  *USBD_CDC_GetHSCfgDesc (uint16_t *length);\r\n\r\nstatic uint8_t  *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length);\r\n\r\nstatic uint8_t  *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length);\r\n\r\nuint8_t  *USBD_CDC_GetDeviceQualifierDescriptor (uint16_t *length);\r\n\r\n/* USB Standard Device Descriptor */\r\n__ALIGN_BEGIN static uint8_t USBD_CDC_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END =\r\n{\r\n  USB_LEN_DEV_QUALIFIER_DESC,\r\n  USB_DESC_TYPE_DEVICE_QUALIFIER,\r\n  0x00,\r\n  0x02,\r\n  0x00,\r\n  0x00,\r\n  0x00,\r\n  0x40,\r\n  0x01,\r\n  0x00,\r\n};\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_CDC_Private_Variables\r\n  * @{\r\n  */ \r\n\r\n\r\n/* CDC interface class callbacks structure */\r\nUSBD_ClassTypeDef  USBD_CDC = \r\n{\r\n  USBD_CDC_Init,\r\n  USBD_CDC_DeInit,\r\n  USBD_CDC_Setup,\r\n  NULL,                 /* EP0_TxSent, */\r\n  USBD_CDC_EP0_RxReady,\r\n  USBD_CDC_DataIn,\r\n  USBD_CDC_DataOut,\r\n  NULL,\r\n  NULL,\r\n  NULL,     \r\n  USBD_CDC_GetHSCfgDesc,  \r\n  USBD_CDC_GetFSCfgDesc,    \r\n  USBD_CDC_GetOtherSpeedCfgDesc, \r\n  USBD_CDC_GetDeviceQualifierDescriptor,\r\n};\r\n\r\n/* USB CDC device Configuration Descriptor */\r\n__ALIGN_BEGIN uint8_t USBD_CDC_CfgHSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END =\r\n{\r\n  /*Configuration Descriptor*/\r\n  0x09,   /* bLength: Configuration Descriptor size */\r\n  USB_DESC_TYPE_CONFIGURATION,      /* bDescriptorType: Configuration */\r\n  USB_CDC_CONFIG_DESC_SIZ,                /* wTotalLength:no of returned bytes */\r\n  0x00,\r\n  0x02,   /* bNumInterfaces: 2 interface */\r\n  0x01,   /* bConfigurationValue: Configuration value */\r\n  0x00,   /* iConfiguration: Index of string descriptor describing the configuration */\r\n  0xC0,   /* bmAttributes: self powered */\r\n  0x32,   /* MaxPower 0 mA */\r\n  \r\n  /*---------------------------------------------------------------------------*/\r\n  \r\n  /*Interface Descriptor */\r\n  0x09,   /* bLength: Interface Descriptor size */\r\n  USB_DESC_TYPE_INTERFACE,  /* bDescriptorType: Interface */\r\n  /* Interface descriptor type */\r\n  0x00,   /* bInterfaceNumber: Number of Interface */\r\n  0x00,   /* bAlternateSetting: Alternate setting */\r\n  0x01,   /* bNumEndpoints: One endpoints used */\r\n  0x02,   /* bInterfaceClass: Communication Interface Class */\r\n  0x02,   /* bInterfaceSubClass: Abstract Control Model */\r\n  0x01,   /* bInterfaceProtocol: Common AT commands */\r\n  0x00,   /* iInterface: */\r\n  \r\n  /*Header Functional Descriptor*/\r\n  0x05,   /* bLength: Endpoint Descriptor size */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x00,   /* bDescriptorSubtype: Header Func Desc */\r\n  0x10,   /* bcdCDC: spec release number */\r\n  0x01,\r\n  \r\n  /*Call Management Functional Descriptor*/\r\n  0x05,   /* bFunctionLength */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x01,   /* bDescriptorSubtype: Call Management Func Desc */\r\n  0x00,   /* bmCapabilities: D0+D1 */\r\n  0x01,   /* bDataInterface: 1 */\r\n  \r\n  /*ACM Functional Descriptor*/\r\n  0x04,   /* bFunctionLength */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x02,   /* bDescriptorSubtype: Abstract Control Management desc */\r\n  0x02,   /* bmCapabilities */\r\n  \r\n  /*Union Functional Descriptor*/\r\n  0x05,   /* bFunctionLength */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x06,   /* bDescriptorSubtype: Union func desc */\r\n  0x00,   /* bMasterInterface: Communication class interface */\r\n  0x01,   /* bSlaveInterface0: Data Class Interface */\r\n  \r\n  /*Endpoint 2 Descriptor*/\r\n  0x07,                           /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_ENDPOINT,   /* bDescriptorType: Endpoint */\r\n  CDC_CMD_EP,                     /* bEndpointAddress */\r\n  0x03,                           /* bmAttributes: Interrupt */\r\n  LOBYTE(CDC_CMD_PACKET_SIZE),     /* wMaxPacketSize: */\r\n  HIBYTE(CDC_CMD_PACKET_SIZE),\r\n  0x10,                           /* bInterval: */ \r\n  /*---------------------------------------------------------------------------*/\r\n  \r\n  /*Data class interface descriptor*/\r\n  0x09,   /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_INTERFACE,  /* bDescriptorType: */\r\n  0x01,   /* bInterfaceNumber: Number of Interface */\r\n  0x00,   /* bAlternateSetting: Alternate setting */\r\n  0x02,   /* bNumEndpoints: Two endpoints used */\r\n  0x0A,   /* bInterfaceClass: CDC */\r\n  0x00,   /* bInterfaceSubClass: */\r\n  0x00,   /* bInterfaceProtocol: */\r\n  0x00,   /* iInterface: */\r\n  \r\n  /*Endpoint OUT Descriptor*/\r\n  0x07,   /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_ENDPOINT,      /* bDescriptorType: Endpoint */\r\n  CDC_OUT_EP,                        /* bEndpointAddress */\r\n  0x02,                              /* bmAttributes: Bulk */\r\n  LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE),  /* wMaxPacketSize: */\r\n  HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE),\r\n  0x00,                              /* bInterval: ignore for Bulk transfer */\r\n  \r\n  /*Endpoint IN Descriptor*/\r\n  0x07,   /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_ENDPOINT,      /* bDescriptorType: Endpoint */\r\n  CDC_IN_EP,                         /* bEndpointAddress */\r\n  0x02,                              /* bmAttributes: Bulk */\r\n  LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE),  /* wMaxPacketSize: */\r\n  HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE),\r\n  0x00                               /* bInterval: ignore for Bulk transfer */\r\n} ;\r\n\r\n\r\n/* USB CDC device Configuration Descriptor */\r\n__ALIGN_BEGIN uint8_t USBD_CDC_CfgFSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END =\r\n{\r\n  /*Configuration Descriptor*/\r\n  0x09,   /* bLength: Configuration Descriptor size */\r\n  USB_DESC_TYPE_CONFIGURATION,      /* bDescriptorType: Configuration */\r\n  USB_CDC_CONFIG_DESC_SIZ,                /* wTotalLength:no of returned bytes */\r\n  0x00,\r\n  0x02,   /* bNumInterfaces: 2 interface */\r\n  0x01,   /* bConfigurationValue: Configuration value */\r\n  0x00,   /* iConfiguration: Index of string descriptor describing the configuration */\r\n  0xC0,   /* bmAttributes: self powered */\r\n  0x32,   /* MaxPower 0 mA */\r\n  \r\n  /*---------------------------------------------------------------------------*/\r\n  \r\n  /*Interface Descriptor */\r\n  0x09,   /* bLength: Interface Descriptor size */\r\n  USB_DESC_TYPE_INTERFACE,  /* bDescriptorType: Interface */\r\n  /* Interface descriptor type */\r\n  0x00,   /* bInterfaceNumber: Number of Interface */\r\n  0x00,   /* bAlternateSetting: Alternate setting */\r\n  0x01,   /* bNumEndpoints: One endpoints used */\r\n  0x02,   /* bInterfaceClass: Communication Interface Class */\r\n  0x02,   /* bInterfaceSubClass: Abstract Control Model */\r\n  0x01,   /* bInterfaceProtocol: Common AT commands */\r\n  0x00,   /* iInterface: */\r\n  \r\n  /*Header Functional Descriptor*/\r\n  0x05,   /* bLength: Endpoint Descriptor size */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x00,   /* bDescriptorSubtype: Header Func Desc */\r\n  0x10,   /* bcdCDC: spec release number */\r\n  0x01,\r\n  \r\n  /*Call Management Functional Descriptor*/\r\n  0x05,   /* bFunctionLength */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x01,   /* bDescriptorSubtype: Call Management Func Desc */\r\n  0x00,   /* bmCapabilities: D0+D1 */\r\n  0x01,   /* bDataInterface: 1 */\r\n  \r\n  /*ACM Functional Descriptor*/\r\n  0x04,   /* bFunctionLength */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x02,   /* bDescriptorSubtype: Abstract Control Management desc */\r\n  0x02,   /* bmCapabilities */\r\n  \r\n  /*Union Functional Descriptor*/\r\n  0x05,   /* bFunctionLength */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x06,   /* bDescriptorSubtype: Union func desc */\r\n  0x00,   /* bMasterInterface: Communication class interface */\r\n  0x01,   /* bSlaveInterface0: Data Class Interface */\r\n  \r\n  /*Endpoint 2 Descriptor*/\r\n  0x07,                           /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_ENDPOINT,   /* bDescriptorType: Endpoint */\r\n  CDC_CMD_EP,                     /* bEndpointAddress */\r\n  0x03,                           /* bmAttributes: Interrupt */\r\n  LOBYTE(CDC_CMD_PACKET_SIZE),     /* wMaxPacketSize: */\r\n  HIBYTE(CDC_CMD_PACKET_SIZE),\r\n  0x10,                           /* bInterval: */ \r\n  /*---------------------------------------------------------------------------*/\r\n  \r\n  /*Data class interface descriptor*/\r\n  0x09,   /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_INTERFACE,  /* bDescriptorType: */\r\n  0x01,   /* bInterfaceNumber: Number of Interface */\r\n  0x00,   /* bAlternateSetting: Alternate setting */\r\n  0x02,   /* bNumEndpoints: Two endpoints used */\r\n  0x0A,   /* bInterfaceClass: CDC */\r\n  0x00,   /* bInterfaceSubClass: */\r\n  0x00,   /* bInterfaceProtocol: */\r\n  0x00,   /* iInterface: */\r\n  \r\n  /*Endpoint OUT Descriptor*/\r\n  0x07,   /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_ENDPOINT,      /* bDescriptorType: Endpoint */\r\n  CDC_OUT_EP,                        /* bEndpointAddress */\r\n  0x02,                              /* bmAttributes: Bulk */\r\n  LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE),  /* wMaxPacketSize: */\r\n  HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE),\r\n  0x00,                              /* bInterval: ignore for Bulk transfer */\r\n  \r\n  /*Endpoint IN Descriptor*/\r\n  0x07,   /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_ENDPOINT,      /* bDescriptorType: Endpoint */\r\n  CDC_IN_EP,                         /* bEndpointAddress */\r\n  0x02,                              /* bmAttributes: Bulk */\r\n  LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE),  /* wMaxPacketSize: */\r\n  HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE),\r\n  0x00                               /* bInterval: ignore for Bulk transfer */\r\n} ;\r\n\r\n__ALIGN_BEGIN uint8_t USBD_CDC_OtherSpeedCfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END =\r\n{ \r\n  0x09,   /* bLength: Configuation Descriptor size */\r\n  USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION,   \r\n  USB_CDC_CONFIG_DESC_SIZ,\r\n  0x00,\r\n  0x02,   /* bNumInterfaces: 2 interfaces */\r\n  0x01,   /* bConfigurationValue: */\r\n  0x04,   /* iConfiguration: */\r\n  0xC0,   /* bmAttributes: */\r\n  0x32,   /* MaxPower 100 mA */  \r\n  \r\n  /*Interface Descriptor */\r\n  0x09,   /* bLength: Interface Descriptor size */\r\n  USB_DESC_TYPE_INTERFACE,  /* bDescriptorType: Interface */\r\n  /* Interface descriptor type */\r\n  0x00,   /* bInterfaceNumber: Number of Interface */\r\n  0x00,   /* bAlternateSetting: Alternate setting */\r\n  0x01,   /* bNumEndpoints: One endpoints used */\r\n  0x02,   /* bInterfaceClass: Communication Interface Class */\r\n  0x02,   /* bInterfaceSubClass: Abstract Control Model */\r\n  0x01,   /* bInterfaceProtocol: Common AT commands */\r\n  0x00,   /* iInterface: */\r\n  \r\n  /*Header Functional Descriptor*/\r\n  0x05,   /* bLength: Endpoint Descriptor size */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x00,   /* bDescriptorSubtype: Header Func Desc */\r\n  0x10,   /* bcdCDC: spec release number */\r\n  0x01,\r\n  \r\n  /*Call Management Functional Descriptor*/\r\n  0x05,   /* bFunctionLength */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x01,   /* bDescriptorSubtype: Call Management Func Desc */\r\n  0x00,   /* bmCapabilities: D0+D1 */\r\n  0x01,   /* bDataInterface: 1 */\r\n  \r\n  /*ACM Functional Descriptor*/\r\n  0x04,   /* bFunctionLength */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x02,   /* bDescriptorSubtype: Abstract Control Management desc */\r\n  0x02,   /* bmCapabilities */\r\n  \r\n  /*Union Functional Descriptor*/\r\n  0x05,   /* bFunctionLength */\r\n  0x24,   /* bDescriptorType: CS_INTERFACE */\r\n  0x06,   /* bDescriptorSubtype: Union func desc */\r\n  0x00,   /* bMasterInterface: Communication class interface */\r\n  0x01,   /* bSlaveInterface0: Data Class Interface */\r\n  \r\n  /*Endpoint 2 Descriptor*/\r\n  0x07,                           /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_ENDPOINT      ,   /* bDescriptorType: Endpoint */\r\n  CDC_CMD_EP,                     /* bEndpointAddress */\r\n  0x03,                           /* bmAttributes: Interrupt */\r\n  LOBYTE(CDC_CMD_PACKET_SIZE),     /* wMaxPacketSize: */\r\n  HIBYTE(CDC_CMD_PACKET_SIZE),\r\n  0xFF,                           /* bInterval: */\r\n  \r\n  /*---------------------------------------------------------------------------*/\r\n  \r\n  /*Data class interface descriptor*/\r\n  0x09,   /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_INTERFACE,  /* bDescriptorType: */\r\n  0x01,   /* bInterfaceNumber: Number of Interface */\r\n  0x00,   /* bAlternateSetting: Alternate setting */\r\n  0x02,   /* bNumEndpoints: Two endpoints used */\r\n  0x0A,   /* bInterfaceClass: CDC */\r\n  0x00,   /* bInterfaceSubClass: */\r\n  0x00,   /* bInterfaceProtocol: */\r\n  0x00,   /* iInterface: */\r\n  \r\n  /*Endpoint OUT Descriptor*/\r\n  0x07,   /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_ENDPOINT,      /* bDescriptorType: Endpoint */\r\n  CDC_OUT_EP,                        /* bEndpointAddress */\r\n  0x02,                              /* bmAttributes: Bulk */\r\n  0x40,                              /* wMaxPacketSize: */\r\n  0x00,\r\n  0x00,                              /* bInterval: ignore for Bulk transfer */\r\n  \r\n  /*Endpoint IN Descriptor*/\r\n  0x07,   /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_ENDPOINT,     /* bDescriptorType: Endpoint */\r\n  CDC_IN_EP,                        /* bEndpointAddress */\r\n  0x02,                             /* bmAttributes: Bulk */\r\n  0x40,                             /* wMaxPacketSize: */\r\n  0x00,\r\n  0x00                              /* bInterval */\r\n};\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_CDC_Private_Functions\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @brief  USBD_CDC_Init\r\n  *         Initialize the CDC interface\r\n  * @param  pdev: device instance\r\n  * @param  cfgidx: Configuration index\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_CDC_Init (USBD_HandleTypeDef *pdev, \r\n                               uint8_t cfgidx)\r\n{\r\n  uint8_t ret = 0;\r\n  USBD_CDC_HandleTypeDef   *hcdc;\r\n  \r\n  if(pdev->dev_speed == USBD_SPEED_HIGH  ) \r\n  {  \r\n    /* Open EP IN */\r\n    USBD_LL_OpenEP(pdev,\r\n                   CDC_IN_EP,\r\n                   USBD_EP_TYPE_BULK,\r\n                   CDC_DATA_HS_IN_PACKET_SIZE);\r\n    \r\n    /* Open EP OUT */\r\n    USBD_LL_OpenEP(pdev,\r\n                   CDC_OUT_EP,\r\n                   USBD_EP_TYPE_BULK,\r\n                   CDC_DATA_HS_OUT_PACKET_SIZE);\r\n    \r\n  }\r\n  else\r\n  {\r\n    /* Open EP IN */\r\n    USBD_LL_OpenEP(pdev,\r\n                   CDC_IN_EP,\r\n                   USBD_EP_TYPE_BULK,\r\n                   CDC_DATA_FS_IN_PACKET_SIZE);\r\n    \r\n    /* Open EP OUT */\r\n    USBD_LL_OpenEP(pdev,\r\n                   CDC_OUT_EP,\r\n                   USBD_EP_TYPE_BULK,\r\n                   CDC_DATA_FS_OUT_PACKET_SIZE);\r\n  }\r\n  /* Open Command IN EP */\r\n  USBD_LL_OpenEP(pdev,\r\n                 CDC_CMD_EP,\r\n                 USBD_EP_TYPE_INTR,\r\n                 CDC_CMD_PACKET_SIZE);\r\n  \r\n    \r\n  pdev->pClassData = USBD_malloc(sizeof (USBD_CDC_HandleTypeDef));\r\n  \r\n  if(pdev->pClassData == NULL)\r\n  {\r\n    ret = 1; \r\n  }\r\n  else\r\n  {\r\n    hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\r\n    \r\n    /* Init  physical Interface components */\r\n    ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Init();\r\n    \r\n    /* Init Xfer states */\r\n    hcdc->TxState =0;\r\n    hcdc->RxState =0;\r\n       \r\n    if(pdev->dev_speed == USBD_SPEED_HIGH  ) \r\n    {      \r\n      /* Prepare Out endpoint to receive next packet */\r\n      USBD_LL_PrepareReceive(pdev,\r\n                             CDC_OUT_EP,\r\n                             hcdc->RxBuffer,\r\n                             CDC_DATA_HS_OUT_PACKET_SIZE);\r\n    }\r\n    else\r\n    {\r\n      /* Prepare Out endpoint to receive next packet */\r\n      USBD_LL_PrepareReceive(pdev,\r\n                             CDC_OUT_EP,\r\n                             hcdc->RxBuffer,\r\n                             CDC_DATA_FS_OUT_PACKET_SIZE);\r\n    }\r\n    \r\n    \r\n  }\r\n  return ret;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_CDC_Init\r\n  *         DeInitialize the CDC layer\r\n  * @param  pdev: device instance\r\n  * @param  cfgidx: Configuration index\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_CDC_DeInit (USBD_HandleTypeDef *pdev, \r\n                                 uint8_t cfgidx)\r\n{\r\n  uint8_t ret = 0;\r\n  \r\n  /* Open EP IN */\r\n  USBD_LL_CloseEP(pdev,\r\n              CDC_IN_EP);\r\n  \r\n  /* Open EP OUT */\r\n  USBD_LL_CloseEP(pdev,\r\n              CDC_OUT_EP);\r\n  \r\n  /* Open Command IN EP */\r\n  USBD_LL_CloseEP(pdev,\r\n              CDC_CMD_EP);\r\n  \r\n  \r\n  /* DeInit  physical Interface components */\r\n  if(pdev->pClassData != NULL)\r\n  {\r\n    ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->DeInit();\r\n    USBD_free(pdev->pClassData);\r\n    pdev->pClassData = NULL;\r\n  }\r\n  \r\n  return ret;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_CDC_Setup\r\n  *         Handle the CDC specific requests\r\n  * @param  pdev: instance\r\n  * @param  req: usb requests\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_CDC_Setup (USBD_HandleTypeDef *pdev, \r\n                                USBD_SetupReqTypedef *req)\r\n{\r\n  USBD_CDC_HandleTypeDef   *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\r\n  static uint8_t ifalt = 0;\r\n    \r\n  switch (req->bmRequest & USB_REQ_TYPE_MASK)\r\n  {\r\n  case USB_REQ_TYPE_CLASS :\r\n    if (req->wLength)\r\n    {\r\n      if (req->bmRequest & 0x80)\r\n      {\r\n        ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,\r\n                                                          (uint8_t *)hcdc->data,\r\n                                                          req->wLength);\r\n          USBD_CtlSendData (pdev, \r\n                            (uint8_t *)hcdc->data,\r\n                            req->wLength);\r\n      }\r\n      else\r\n      {\r\n        hcdc->CmdOpCode = req->bRequest;\r\n        hcdc->CmdLength = req->wLength;\r\n        \r\n        USBD_CtlPrepareRx (pdev, \r\n                           (uint8_t *)hcdc->data,\r\n                           req->wLength);\r\n      }\r\n      \r\n    }\r\n    else\r\n    {\r\n      ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,\r\n                                                        (uint8_t*)req,\r\n                                                        0);\r\n    }\r\n    break;\r\n\r\n  case USB_REQ_TYPE_STANDARD:\r\n    switch (req->bRequest)\r\n    {      \r\n    case USB_REQ_GET_INTERFACE :\r\n      USBD_CtlSendData (pdev,\r\n                        &ifalt,\r\n                        1);\r\n      break;\r\n      \r\n    case USB_REQ_SET_INTERFACE :\r\n      break;\r\n    }\r\n \r\n  default: \r\n    break;\r\n  }\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_CDC_DataIn\r\n  *         Data sent on non-control IN endpoint\r\n  * @param  pdev: device instance\r\n  * @param  epnum: endpoint number\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum)\r\n{\r\n  USBD_CDC_HandleTypeDef   *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\r\n  \r\n  if(pdev->pClassData != NULL)\r\n  {\r\n    \r\n    hcdc->TxState = 0;\r\n\r\n    return USBD_OK;\r\n  }\r\n  else\r\n  {\r\n    return USBD_FAIL;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  USBD_CDC_DataOut\r\n  *         Data received on non-control Out endpoint\r\n  * @param  pdev: device instance\r\n  * @param  epnum: endpoint number\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_CDC_DataOut (USBD_HandleTypeDef *pdev, uint8_t epnum)\r\n{      \r\n  USBD_CDC_HandleTypeDef   *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\r\n  \r\n  /* Get the received data length */\r\n  hcdc->RxLength = USBD_LL_GetRxDataSize (pdev, epnum);\r\n  \r\n  /* USB data will be immediately processed, this allow next USB traffic being \r\n  NAKed till the end of the application Xfer */\r\n  if(pdev->pClassData != NULL)\r\n  {\r\n    ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hcdc->RxBuffer, &hcdc->RxLength);\r\n\r\n    return USBD_OK;\r\n  }\r\n  else\r\n  {\r\n    return USBD_FAIL;\r\n  }\r\n}\r\n\r\n\r\n\r\n/**\r\n  * @brief  USBD_CDC_DataOut\r\n  *         Data received on non-control Out endpoint\r\n  * @param  pdev: device instance\r\n  * @param  epnum: endpoint number\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_CDC_EP0_RxReady (USBD_HandleTypeDef *pdev)\r\n{ \r\n  USBD_CDC_HandleTypeDef   *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\r\n  \r\n  if((pdev->pUserData != NULL) && (hcdc->CmdOpCode != 0xFF))\r\n  {\r\n    ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode,\r\n                                                      (uint8_t *)hcdc->data,\r\n                                                      hcdc->CmdLength);\r\n      hcdc->CmdOpCode = 0xFF; \r\n      \r\n  }\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_CDC_GetFSCfgDesc \r\n  *         Return configuration descriptor\r\n  * @param  speed : current device speed\r\n  * @param  length : pointer data length\r\n  * @retval pointer to descriptor buffer\r\n  */\r\nstatic uint8_t  *USBD_CDC_GetFSCfgDesc (uint16_t *length)\r\n{\r\n  *length = sizeof (USBD_CDC_CfgFSDesc);\r\n  return USBD_CDC_CfgFSDesc;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_CDC_GetHSCfgDesc \r\n  *         Return configuration descriptor\r\n  * @param  speed : current device speed\r\n  * @param  length : pointer data length\r\n  * @retval pointer to descriptor buffer\r\n  */\r\nstatic uint8_t  *USBD_CDC_GetHSCfgDesc (uint16_t *length)\r\n{\r\n  *length = sizeof (USBD_CDC_CfgHSDesc);\r\n  return USBD_CDC_CfgHSDesc;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_CDC_GetCfgDesc \r\n  *         Return configuration descriptor\r\n  * @param  speed : current device speed\r\n  * @param  length : pointer data length\r\n  * @retval pointer to descriptor buffer\r\n  */\r\nstatic uint8_t  *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length)\r\n{\r\n  *length = sizeof (USBD_CDC_OtherSpeedCfgDesc);\r\n  return USBD_CDC_OtherSpeedCfgDesc;\r\n}\r\n\r\n/**\r\n* @brief  DeviceQualifierDescriptor \r\n*         return Device Qualifier descriptor\r\n* @param  length : pointer data length\r\n* @retval pointer to descriptor buffer\r\n*/\r\nuint8_t  *USBD_CDC_GetDeviceQualifierDescriptor (uint16_t *length)\r\n{\r\n  *length = sizeof (USBD_CDC_DeviceQualifierDesc);\r\n  return USBD_CDC_DeviceQualifierDesc;\r\n}\r\n\r\n/**\r\n* @brief  USBD_CDC_RegisterInterface\r\n  * @param  pdev: device instance\r\n  * @param  fops: CD  Interface callback\r\n  * @retval status\r\n  */\r\nuint8_t  USBD_CDC_RegisterInterface  (USBD_HandleTypeDef   *pdev, \r\n                                      USBD_CDC_ItfTypeDef *fops)\r\n{\r\n  uint8_t  ret = USBD_FAIL;\r\n  \r\n  if(fops != NULL)\r\n  {\r\n    pdev->pUserData= fops;\r\n    ret = USBD_OK;    \r\n  }\r\n  \r\n  return ret;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_CDC_SetTxBuffer\r\n  * @param  pdev: device instance\r\n  * @param  pbuff: Tx Buffer\r\n  * @retval status\r\n  */\r\nuint8_t  USBD_CDC_SetTxBuffer  (USBD_HandleTypeDef   *pdev,\r\n                                uint8_t  *pbuff,\r\n                                uint16_t length)\r\n{\r\n  USBD_CDC_HandleTypeDef   *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\r\n  \r\n  hcdc->TxBuffer = pbuff;\r\n  hcdc->TxLength = length;  \r\n  \r\n  return USBD_OK;  \r\n}\r\n\r\n\r\n/**\r\n  * @brief  USBD_CDC_SetRxBuffer\r\n  * @param  pdev: device instance\r\n  * @param  pbuff: Rx Buffer\r\n  * @retval status\r\n  */\r\nuint8_t  USBD_CDC_SetRxBuffer  (USBD_HandleTypeDef   *pdev,\r\n                                   uint8_t  *pbuff)\r\n{\r\n  USBD_CDC_HandleTypeDef   *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\r\n  \r\n  hcdc->RxBuffer = pbuff;\r\n  \r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_CDC_DataOut\r\n  *         Data received on non-control Out endpoint\r\n  * @param  pdev: device instance\r\n  * @param  epnum: endpoint number\r\n  * @retval status\r\n  */\r\nuint8_t  USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev)\r\n{      \r\n  USBD_CDC_HandleTypeDef   *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\r\n  \r\n  if(pdev->pClassData != NULL)\r\n  {\r\n    if(hcdc->TxState == 0)\r\n    {\r\n      /* Tx Transfer in progress */\r\n      hcdc->TxState = 1;\r\n      \r\n      /* Transmit next packet */\r\n      USBD_LL_Transmit(pdev,\r\n                       CDC_IN_EP,\r\n                       hcdc->TxBuffer,\r\n                       hcdc->TxLength);\r\n      \r\n      return USBD_OK;\r\n    }\r\n    else\r\n    {\r\n      return USBD_BUSY;\r\n    }\r\n  }\r\n  else\r\n  {\r\n    return USBD_FAIL;\r\n  }\r\n}\r\n\r\n\r\n/**\r\n  * @brief  USBD_CDC_ReceivePacket\r\n  *         prepare OUT Endpoint for reception\r\n  * @param  pdev: device instance\r\n  * @retval status\r\n  */\r\nuint8_t  USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev)\r\n{      \r\n  USBD_CDC_HandleTypeDef   *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\r\n  \r\n  /* Suspend or Resume USB Out process */\r\n  if(pdev->pClassData != NULL)\r\n  {\r\n    if(pdev->dev_speed == USBD_SPEED_HIGH  ) \r\n    {      \r\n      /* Prepare Out endpoint to receive next packet */\r\n      USBD_LL_PrepareReceive(pdev,\r\n                             CDC_OUT_EP,\r\n                             hcdc->RxBuffer,\r\n                             CDC_DATA_HS_OUT_PACKET_SIZE);\r\n    }\r\n    else\r\n    {\r\n      /* Prepare Out endpoint to receive next packet */\r\n      USBD_LL_PrepareReceive(pdev,\r\n                             CDC_OUT_EP,\r\n                             hcdc->RxBuffer,\r\n                             CDC_DATA_FS_OUT_PACKET_SIZE);\r\n    }\r\n    return USBD_OK;\r\n  }\r\n  else\r\n  {\r\n    return USBD_FAIL;\r\n  }\r\n}\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Class/CustomHID/Inc/usbd_customhid.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_customhid.h\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   header file for the usbd_customhid.c file.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n \r\n/* Define to prevent recursive inclusion -------------------------------------*/ \r\n#ifndef __USB_CUSTOMHID_H\r\n#define __USB_CUSTOMHID_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include  \"usbd_ioreq.h\"\r\n\r\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup USBD_CUSTOM_HID\r\n  * @brief This file is the Header file for USBD_customhid.c\r\n  * @{\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_CUSTOM_HID_Exported_Defines\r\n  * @{\r\n  */ \r\n#define CUSTOM_HID_EPIN_ADDR                 0x81\r\n#define CUSTOM_HID_EPIN_SIZE                 0x02\r\n\r\n#define CUSTOM_HID_EPOUT_ADDR                0x01\r\n#define CUSTOM_HID_EPOUT_SIZE                0x02\r\n\r\n#define USB_CUSTOM_HID_CONFIG_DESC_SIZ       41\r\n#define USB_CUSTOM_HID_DESC_SIZ              9\r\n\r\n#define CUSTOM_HID_DESCRIPTOR_TYPE           0x21\r\n#define CUSTOM_HID_REPORT_DESC               0x22\r\n\r\n\r\n#define CUSTOM_HID_REQ_SET_PROTOCOL          0x0B\r\n#define CUSTOM_HID_REQ_GET_PROTOCOL          0x03\r\n\r\n#define CUSTOM_HID_REQ_SET_IDLE              0x0A\r\n#define CUSTOM_HID_REQ_GET_IDLE              0x02\r\n\r\n#define CUSTOM_HID_REQ_SET_REPORT            0x09\r\n#define CUSTOM_HID_REQ_GET_REPORT            0x01\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_CORE_Exported_TypesDefinitions\r\n  * @{\r\n  */\r\ntypedef enum\r\n{\r\n  CUSTOM_HID_IDLE = 0,\r\n  CUSTOM_HID_BUSY,\r\n}\r\nCUSTOM_HID_StateTypeDef; \r\n\r\ntypedef struct _USBD_CUSTOM_HID_Itf\r\n{\r\n  uint8_t                  *pReport;\r\n  int8_t (* Init)          (void);\r\n  int8_t (* DeInit)        (void);\r\n  int8_t (* OutEvent)      (uint8_t, uint8_t );   \r\n\r\n}USBD_CUSTOM_HID_ItfTypeDef;\r\n\r\ntypedef struct\r\n{\r\n  uint8_t              Report_buf[USBD_CUSTOMHID_OUTREPORT_BUF_SIZE];\r\n  uint32_t             Protocol;   \r\n  uint32_t             IdleState;  \r\n  uint32_t             AltSetting;\r\n  uint32_t             IsReportAvailable;  \r\n  CUSTOM_HID_StateTypeDef     state;  \r\n}\r\nUSBD_CUSTOM_HID_HandleTypeDef; \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n\r\n/** @defgroup USBD_CORE_Exported_Macros\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_CORE_Exported_Variables\r\n  * @{\r\n  */ \r\n\r\nextern USBD_ClassTypeDef  USBD_CUSTOM_HID;\r\n#define USBD_CUSTOM_HID_CLASS    &USBD_CUSTOM_HID\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USB_CORE_Exported_Functions\r\n  * @{\r\n  */ \r\nuint8_t USBD_CUSTOM_HID_SendReport (USBD_HandleTypeDef *pdev, \r\n                                 uint8_t *report,\r\n                                 uint16_t len);\r\n\r\n\r\n\r\nuint8_t  USBD_CUSTOM_HID_RegisterInterface  (USBD_HandleTypeDef   *pdev, \r\n                                             USBD_CUSTOM_HID_ItfTypeDef *fops);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif  /* __USB_CUSTOMHID_H */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Class/CustomHID/Inc/usbd_customhid_if_template.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_customhid_if_template.h\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   Header for usbd_customhid_if_template.c file.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for th?\r\n  e specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __USBD_CUSTOMHID_IF_TEMPLATE_H\r\n#define __USBD_CUSTOMHID_IF_TEMPLATE_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_customhid.h\"\r\n\r\n/* Exported types ------------------------------------------------------------*/\r\n/* Exported constants --------------------------------------------------------*/\r\n/* Exported macro ------------------------------------------------------------*/\r\n/* Exported functions ------------------------------------------------------- */\r\nextern USBD_CUSTOM_HID_ItfTypeDef USBD_CustomHID_template_fops;\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __USBD_CUSTOMHID_IF_TEMPLATE_H */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Class/CustomHID/Src/usbd_customhid.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_customhid.c\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   This file provides the CUSTOM_HID core functions.\r\n  *\r\n  * @verbatim\r\n  *      \r\n  *          ===================================================================      \r\n  *                                CUSTOM_HID Class  Description\r\n  *          =================================================================== \r\n  *           This module manages the CUSTOM_HID class V1.11 following the \"Device Class Definition\r\n  *           for Human Interface Devices (CUSTOM_HID) Version 1.11 Jun 27, 2001\".\r\n  *           This driver implements the following aspects of the specification:\r\n  *             - The Boot Interface Subclass\r\n  *             - Usage Page : Generic Desktop\r\n  *             - Usage : Vendor\r\n  *             - Collection : Application \r\n  *      \r\n  * @note     In HS mode and when the DMA is used, all variables and data structures\r\n  *           dealing with the DMA during the transaction process should be 32-bit aligned.\r\n  *           \r\n  *      \r\n  *  @endverbatim\r\n  *\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_customhid.h\"\r\n#include \"usbd_desc.h\"\r\n#include \"usbd_ctlreq.h\"\r\n\r\n\r\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n\r\n\r\n/** @defgroup USBD_CUSTOM_HID \r\n  * @brief usbd core module\r\n  * @{\r\n  */ \r\n\r\n/** @defgroup USBD_CUSTOM_HID_Private_TypesDefinitions\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_CUSTOM_HID_Private_Defines\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_CUSTOM_HID_Private_Macros\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n/** @defgroup USBD_CUSTOM_HID_Private_FunctionPrototypes\r\n  * @{\r\n  */\r\n\r\n\r\nstatic uint8_t  USBD_CUSTOM_HID_Init (USBD_HandleTypeDef *pdev, \r\n                               uint8_t cfgidx);\r\n\r\nstatic uint8_t  USBD_CUSTOM_HID_DeInit (USBD_HandleTypeDef *pdev, \r\n                                 uint8_t cfgidx);\r\n\r\nstatic uint8_t  USBD_CUSTOM_HID_Setup (USBD_HandleTypeDef *pdev, \r\n                                USBD_SetupReqTypedef *req);\r\n\r\nstatic uint8_t  *USBD_CUSTOM_HID_GetCfgDesc (uint16_t *length);\r\n\r\nstatic uint8_t  *USBD_CUSTOM_HID_GetDeviceQualifierDesc (uint16_t *length);\r\n\r\nstatic uint8_t  USBD_CUSTOM_HID_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum);\r\n\r\nstatic uint8_t  USBD_CUSTOM_HID_DataOut (USBD_HandleTypeDef *pdev, uint8_t epnum);\r\nstatic uint8_t  USBD_CUSTOM_HID_EP0_RxReady (USBD_HandleTypeDef  *pdev);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_CUSTOM_HID_Private_Variables\r\n  * @{\r\n  */ \r\n\r\nUSBD_ClassTypeDef  USBD_CUSTOM_HID = \r\n{\r\n  USBD_CUSTOM_HID_Init,\r\n  USBD_CUSTOM_HID_DeInit,\r\n  USBD_CUSTOM_HID_Setup,\r\n  NULL, /*EP0_TxSent*/  \r\n  USBD_CUSTOM_HID_EP0_RxReady, /*EP0_RxReady*/ /* STATUS STAGE IN */\r\n  USBD_CUSTOM_HID_DataIn, /*DataIn*/\r\n  USBD_CUSTOM_HID_DataOut,\r\n  NULL, /*SOF */\r\n  NULL,\r\n  NULL,      \r\n  USBD_CUSTOM_HID_GetCfgDesc,\r\n  USBD_CUSTOM_HID_GetCfgDesc, \r\n  USBD_CUSTOM_HID_GetCfgDesc,\r\n  USBD_CUSTOM_HID_GetDeviceQualifierDesc,\r\n};\r\n\r\n/* USB CUSTOM_HID device Configuration Descriptor */\r\n__ALIGN_BEGIN static uint8_t USBD_CUSTOM_HID_CfgDesc[USB_CUSTOM_HID_CONFIG_DESC_SIZ] __ALIGN_END =\r\n{\r\n  0x09, /* bLength: Configuration Descriptor size */\r\n  USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */\r\n  USB_CUSTOM_HID_CONFIG_DESC_SIZ,\r\n  /* wTotalLength: Bytes returned */\r\n  0x00,\r\n  0x01,         /*bNumInterfaces: 1 interface*/\r\n  0x01,         /*bConfigurationValue: Configuration value*/\r\n  0x00,         /*iConfiguration: Index of string descriptor describing\r\n  the configuration*/\r\n  0xC0,         /*bmAttributes: bus powered */\r\n  0x32,         /*MaxPower 100 mA: this current is used for detecting Vbus*/\r\n  \r\n  /************** Descriptor of CUSTOM HID interface ****************/\r\n  /* 09 */\r\n  0x09,         /*bLength: Interface Descriptor size*/\r\n  USB_DESC_TYPE_INTERFACE,/*bDescriptorType: Interface descriptor type*/\r\n  0x00,         /*bInterfaceNumber: Number of Interface*/\r\n  0x00,         /*bAlternateSetting: Alternate setting*/\r\n  0x02,         /*bNumEndpoints*/\r\n  0x03,         /*bInterfaceClass: CUSTOM_HID*/\r\n  0x00,         /*bInterfaceSubClass : 1=BOOT, 0=no boot*/\r\n  0x00,         /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/\r\n  0,            /*iInterface: Index of string descriptor*/\r\n  /******************** Descriptor of CUSTOM_HID *************************/\r\n  /* 18 */\r\n  0x09,         /*bLength: CUSTOM_HID Descriptor size*/\r\n  CUSTOM_HID_DESCRIPTOR_TYPE, /*bDescriptorType: CUSTOM_HID*/\r\n  0x11,         /*bCUSTOM_HIDUSTOM_HID: CUSTOM_HID Class Spec release number*/\r\n  0x01,\r\n  0x00,         /*bCountryCode: Hardware target country*/\r\n  0x01,         /*bNumDescriptors: Number of CUSTOM_HID class descriptors to follow*/\r\n  0x22,         /*bDescriptorType*/\r\n  USBD_CUSTOM_HID_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/\r\n  0x00,\r\n  /******************** Descriptor of Custom HID endpoints ********************/\r\n  /* 27 */\r\n  0x07,          /*bLength: Endpoint Descriptor size*/\r\n  USB_DESC_TYPE_ENDPOINT, /*bDescriptorType:*/\r\n  \r\n  CUSTOM_HID_EPIN_ADDR,     /*bEndpointAddress: Endpoint Address (IN)*/\r\n  0x03,          /*bmAttributes: Interrupt endpoint*/\r\n  CUSTOM_HID_EPIN_SIZE, /*wMaxPacketSize: 2 Byte max */\r\n  0x00,\r\n  0x20,          /*bInterval: Polling Interval (20 ms)*/\r\n  /* 34 */\r\n  \r\n  0x07,\t         /* bLength: Endpoint Descriptor size */\r\n  USB_DESC_TYPE_ENDPOINT,\t/* bDescriptorType: */\r\n  CUSTOM_HID_EPOUT_ADDR,  /*bEndpointAddress: Endpoint Address (OUT)*/\r\n  0x03,\t/* bmAttributes: Interrupt endpoint */\r\n  CUSTOM_HID_EPOUT_SIZE,\t/* wMaxPacketSize: 2 Bytes max  */\r\n  0x00,\r\n  0x20,\t/* bInterval: Polling Interval (20 ms) */\r\n  /* 41 */\r\n} ;\r\n\r\n/* USB CUSTOM_HID device Configuration Descriptor */\r\n__ALIGN_BEGIN static uint8_t USBD_CUSTOM_HID_Desc[USB_CUSTOM_HID_DESC_SIZ] __ALIGN_END =\r\n{\r\n  /* 18 */\r\n  0x09,         /*bLength: CUSTOM_HID Descriptor size*/\r\n  CUSTOM_HID_DESCRIPTOR_TYPE, /*bDescriptorType: CUSTOM_HID*/\r\n  0x11,         /*bCUSTOM_HIDUSTOM_HID: CUSTOM_HID Class Spec release number*/\r\n  0x01,\r\n  0x00,         /*bCountryCode: Hardware target country*/\r\n  0x01,         /*bNumDescriptors: Number of CUSTOM_HID class descriptors to follow*/\r\n  0x22,         /*bDescriptorType*/\r\n  USBD_CUSTOM_HID_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/\r\n  0x00,\r\n};\r\n\r\n/* USB Standard Device Descriptor */\r\n__ALIGN_BEGIN static uint8_t USBD_CUSTOM_HID_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END =\r\n{\r\n  USB_LEN_DEV_QUALIFIER_DESC,\r\n  USB_DESC_TYPE_DEVICE_QUALIFIER,\r\n  0x00,\r\n  0x02,\r\n  0x00,\r\n  0x00,\r\n  0x00,\r\n  0x40,\r\n  0x01,\r\n  0x00,\r\n};\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_CUSTOM_HID_Private_Functions\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @brief  USBD_CUSTOM_HID_Init\r\n  *         Initialize the CUSTOM_HID interface\r\n  * @param  pdev: device instance\r\n  * @param  cfgidx: Configuration index\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_CUSTOM_HID_Init (USBD_HandleTypeDef *pdev, \r\n                               uint8_t cfgidx)\r\n{\r\n  uint8_t ret = 0;\r\n  USBD_CUSTOM_HID_HandleTypeDef     *hhid;\r\n  /* Open EP IN */\r\n  USBD_LL_OpenEP(pdev,\r\n                 CUSTOM_HID_EPIN_ADDR,\r\n                 USBD_EP_TYPE_INTR,\r\n                 CUSTOM_HID_EPIN_SIZE);  \r\n  \r\n  /* Open EP OUT */\r\n  USBD_LL_OpenEP(pdev,\r\n                 CUSTOM_HID_EPOUT_ADDR,\r\n                 USBD_EP_TYPE_INTR,\r\n                 CUSTOM_HID_EPOUT_SIZE);\r\n  \r\n  pdev->pClassData = USBD_malloc(sizeof (USBD_CUSTOM_HID_HandleTypeDef));\r\n  \r\n  if(pdev->pClassData == NULL)\r\n  {\r\n    ret = 1; \r\n  }\r\n  else\r\n  {\r\n    hhid = (USBD_CUSTOM_HID_HandleTypeDef*) pdev->pClassData;\r\n      \r\n    hhid->state = CUSTOM_HID_IDLE;\r\n    ((USBD_CUSTOM_HID_ItfTypeDef *)pdev->pUserData)->Init();\r\n          /* Prepare Out endpoint to receive 1st packet */ \r\n    USBD_LL_PrepareReceive(pdev, CUSTOM_HID_EPOUT_ADDR, hhid->Report_buf, \r\n                           USBD_CUSTOMHID_OUTREPORT_BUF_SIZE);\r\n  }\r\n    \r\n  return ret;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_CUSTOM_HID_Init\r\n  *         DeInitialize the CUSTOM_HID layer\r\n  * @param  pdev: device instance\r\n  * @param  cfgidx: Configuration index\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_CUSTOM_HID_DeInit (USBD_HandleTypeDef *pdev, \r\n                                 uint8_t cfgidx)\r\n{\r\n  /* Close CUSTOM_HID EP IN */\r\n  USBD_LL_CloseEP(pdev,\r\n                  CUSTOM_HID_EPIN_ADDR);\r\n  \r\n  /* Close CUSTOM_HID EP OUT */\r\n  USBD_LL_CloseEP(pdev,\r\n                  CUSTOM_HID_EPOUT_ADDR);\r\n  \r\n  /* FRee allocated memory */\r\n  if(pdev->pClassData != NULL)\r\n  {\r\n    ((USBD_CUSTOM_HID_ItfTypeDef *)pdev->pUserData)->DeInit();\r\n    USBD_free(pdev->pClassData);\r\n    pdev->pClassData = NULL;\r\n  }\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_CUSTOM_HID_Setup\r\n  *         Handle the CUSTOM_HID specific requests\r\n  * @param  pdev: instance\r\n  * @param  req: usb requests\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_CUSTOM_HID_Setup (USBD_HandleTypeDef *pdev, \r\n                                USBD_SetupReqTypedef *req)\r\n{\r\n  uint16_t len = 0;\r\n  uint8_t  *pbuf = NULL;\r\n  USBD_CUSTOM_HID_HandleTypeDef     *hhid = (USBD_CUSTOM_HID_HandleTypeDef*)pdev->pClassData;\r\n\r\n  switch (req->bmRequest & USB_REQ_TYPE_MASK)\r\n  {\r\n  case USB_REQ_TYPE_CLASS :  \r\n    switch (req->bRequest)\r\n    {\r\n      \r\n      \r\n    case CUSTOM_HID_REQ_SET_PROTOCOL:\r\n      hhid->Protocol = (uint8_t)(req->wValue);\r\n      break;\r\n      \r\n    case CUSTOM_HID_REQ_GET_PROTOCOL:\r\n      USBD_CtlSendData (pdev, \r\n                        (uint8_t *)&hhid->Protocol,\r\n                        1);    \r\n      break;\r\n      \r\n    case CUSTOM_HID_REQ_SET_IDLE:\r\n      hhid->IdleState = (uint8_t)(req->wValue >> 8);\r\n      break;\r\n      \r\n    case CUSTOM_HID_REQ_GET_IDLE:\r\n      USBD_CtlSendData (pdev, \r\n                        (uint8_t *)&hhid->IdleState,\r\n                        1);        \r\n      break;      \r\n    \r\n    case CUSTOM_HID_REQ_SET_REPORT:\r\n      hhid->IsReportAvailable = 1;\r\n      USBD_CtlPrepareRx (pdev, hhid->Report_buf, (uint8_t)(req->wLength));\r\n      \r\n      break;\r\n    default:\r\n      USBD_CtlError (pdev, req);\r\n      return USBD_FAIL; \r\n    }\r\n    break;\r\n    \r\n  case USB_REQ_TYPE_STANDARD:\r\n    switch (req->bRequest)\r\n    {\r\n    case USB_REQ_GET_DESCRIPTOR: \r\n      if( req->wValue >> 8 == CUSTOM_HID_REPORT_DESC)\r\n      {\r\n        len = MIN(USBD_CUSTOM_HID_REPORT_DESC_SIZE , req->wLength);\r\n        pbuf =  ((USBD_CUSTOM_HID_ItfTypeDef *)pdev->pUserData)->pReport;\r\n      }\r\n      else if( req->wValue >> 8 == CUSTOM_HID_DESCRIPTOR_TYPE)\r\n      {\r\n        pbuf = USBD_CUSTOM_HID_Desc;   \r\n        len = MIN(USB_CUSTOM_HID_DESC_SIZ , req->wLength);\r\n      }\r\n      \r\n      USBD_CtlSendData (pdev, \r\n                        pbuf,\r\n                        len);\r\n      \r\n      break;\r\n      \r\n    case USB_REQ_GET_INTERFACE :\r\n      USBD_CtlSendData (pdev,\r\n                        (uint8_t *)&hhid->AltSetting,\r\n                        1);\r\n      break;\r\n      \r\n    case USB_REQ_SET_INTERFACE :\r\n      hhid->AltSetting = (uint8_t)(req->wValue);\r\n      break;\r\n    }\r\n  }\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_CUSTOM_HID_SendReport \r\n  *         Send CUSTOM_HID Report\r\n  * @param  pdev: device instance\r\n  * @param  buff: pointer to report\r\n  * @retval status\r\n  */\r\nuint8_t USBD_CUSTOM_HID_SendReport     (USBD_HandleTypeDef  *pdev, \r\n                                 uint8_t *report,\r\n                                 uint16_t len)\r\n{\r\n  USBD_CUSTOM_HID_HandleTypeDef     *hhid = (USBD_CUSTOM_HID_HandleTypeDef*)pdev->pClassData;\r\n  \r\n  if (pdev->dev_state == USBD_STATE_CONFIGURED )\r\n  {\r\n    if(hhid->state == CUSTOM_HID_IDLE)\r\n    {\r\n      hhid->state = CUSTOM_HID_BUSY;\r\n      USBD_LL_Transmit (pdev, \r\n                        CUSTOM_HID_EPIN_ADDR,                                      \r\n                        report,\r\n                        len);\r\n    }\r\n  }\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_CUSTOM_HID_GetCfgDesc \r\n  *         return configuration descriptor\r\n  * @param  speed : current device speed\r\n  * @param  length : pointer data length\r\n  * @retval pointer to descriptor buffer\r\n  */\r\nstatic uint8_t  *USBD_CUSTOM_HID_GetCfgDesc (uint16_t *length)\r\n{\r\n  *length = sizeof (USBD_CUSTOM_HID_CfgDesc);\r\n  return USBD_CUSTOM_HID_CfgDesc;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_CUSTOM_HID_DataIn\r\n  *         handle data IN Stage\r\n  * @param  pdev: device instance\r\n  * @param  epnum: endpoint index\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_CUSTOM_HID_DataIn (USBD_HandleTypeDef *pdev, \r\n                              uint8_t epnum)\r\n{\r\n  \r\n  /* Ensure that the FIFO is empty before a new transfer, this condition could \r\n  be caused by  a new transfer before the end of the previous transfer */\r\n  ((USBD_CUSTOM_HID_HandleTypeDef *)pdev->pClassData)->state = CUSTOM_HID_IDLE;\r\n\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_CUSTOM_HID_DataOut\r\n  *         handle data OUT Stage\r\n  * @param  pdev: device instance\r\n  * @param  epnum: endpoint index\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_CUSTOM_HID_DataOut (USBD_HandleTypeDef *pdev, \r\n                              uint8_t epnum)\r\n{\r\n  \r\n  USBD_CUSTOM_HID_HandleTypeDef     *hhid = (USBD_CUSTOM_HID_HandleTypeDef*)pdev->pClassData;  \r\n  \r\n  ((USBD_CUSTOM_HID_ItfTypeDef *)pdev->pUserData)->OutEvent(hhid->Report_buf[0], \r\n                                                            hhid->Report_buf[1]);\r\n    \r\n  USBD_LL_PrepareReceive(pdev, CUSTOM_HID_EPOUT_ADDR , hhid->Report_buf, \r\n                         USBD_CUSTOMHID_OUTREPORT_BUF_SIZE);\r\n\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_CUSTOM_HID_EP0_RxReady\r\n  *         Handles control request data.\r\n  * @param  pdev: device instance\r\n  * @retval status\r\n  */\r\nuint8_t USBD_CUSTOM_HID_EP0_RxReady(USBD_HandleTypeDef *pdev)\r\n{\r\n  USBD_CUSTOM_HID_HandleTypeDef     *hhid = (USBD_CUSTOM_HID_HandleTypeDef*)pdev->pClassData;  \r\n\r\n  if (hhid->IsReportAvailable == 1)\r\n  {\r\n    ((USBD_CUSTOM_HID_ItfTypeDef *)pdev->pUserData)->OutEvent(hhid->Report_buf[0], \r\n                                                              hhid->Report_buf[1]);\r\n    hhid->IsReportAvailable = 0;      \r\n  }\r\n\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n* @brief  DeviceQualifierDescriptor \r\n*         return Device Qualifier descriptor\r\n* @param  length : pointer data length\r\n* @retval pointer to descriptor buffer\r\n*/\r\nstatic uint8_t  *USBD_CUSTOM_HID_GetDeviceQualifierDesc (uint16_t *length)\r\n{\r\n  *length = sizeof (USBD_CUSTOM_HID_DeviceQualifierDesc);\r\n  return USBD_CUSTOM_HID_DeviceQualifierDesc;\r\n}\r\n\r\n/**\r\n* @brief  USBD_CUSTOM_HID_RegisterInterface\r\n  * @param  pdev: device instance\r\n  * @param  fops: CUSTOMHID Interface callback\r\n  * @retval status\r\n  */\r\nuint8_t  USBD_CUSTOM_HID_RegisterInterface  (USBD_HandleTypeDef   *pdev, \r\n                                             USBD_CUSTOM_HID_ItfTypeDef *fops)\r\n{\r\n  uint8_t  ret = USBD_FAIL;\r\n  \r\n  if(fops != NULL)\r\n  {\r\n    pdev->pUserData= fops;\r\n    ret = USBD_OK;    \r\n  }\r\n  \r\n  return ret;\r\n}\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Class/CustomHID/Src/usbd_customhid_if_template.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_customhid_if_template.c\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   USB Device Custom HID interface file.\r\n  *\t\t     This template should be copied to the user folder, renamed and customized\r\n  *          following user needs.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_customhid_if_template.h\"\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n\r\nstatic int8_t TEMPLATE_CUSTOM_HID_Init     (void);\r\nstatic int8_t TEMPLATE_CUSTOM_HID_DeInit   (void);\r\nstatic int8_t TEMPLATE_CUSTOM_HID_OutEvent (uint8_t event_idx, uint8_t state);\r\n/* Private variables ---------------------------------------------------------*/\r\nUSBD_CUSTOM_HID_ItfTypeDef USBD_CustomHID_template_fops = \r\n{\r\n  TEMPLATE_CUSTOM_HID_ReportDesc,\r\n  TEMPLATE_CUSTOM_HID_Init,\r\n  TEMPLATE_CUSTOM_HID_DeInit,\r\n  TEMPLATE_CUSTOM_HID_OutEvent,\r\n};\r\n\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n/**\r\n  * @brief  TEMPLATE_CUSTOM_HID_Init\r\n  *         Initializes the CUSTOM HID media low layer\r\n  * @param  None\r\n  * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL\r\n  */\r\nstatic int8_t TEMPLATE_CUSTOM_HID_Init(void)\r\n{\r\n\r\n  return (0);\r\n}\r\n\r\n/**\r\n  * @brief  TEMPLATE_CUSTOM_HID_DeInit\r\n  *         DeInitializes the CUSTOM HID media low layer\r\n  * @param  None\r\n  * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL\r\n  */\r\nstatic int8_t TEMPLATE_CUSTOM_HID_DeInit(void)\r\n{\r\n  /*\r\n     Add your deinitialization code here \r\n  */  \r\n  return (0);\r\n}\r\n\r\n\r\n/**\r\n  * @brief  TEMPLATE_CUSTOM_HID_Control\r\n  *         Manage the CUSTOM HID class events       \r\n  * @param  event_idx: event index\r\n  * @param  state: event state\r\n  * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL\r\n  */\r\nstatic int8_t TEMPLATE_CUSTOM_HID_OutEvent  (uint8_t event_idx, uint8_t state)\r\n{ \r\n\r\n  return (0);\r\n}\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Class/DFU/Inc/usbd_dfu.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_dfu.h\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   Header file for the usbd_dfu.c file.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/ \r\n#ifndef __USB_DFU_H\r\n#define __USB_DFU_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include  \"usbd_ioreq.h\"\r\n\r\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup USBD_DFU\r\n  * @brief This file is the Header file for usbd_dfu.c\r\n  * @{\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_DFU_Exported_Defines\r\n  * @{\r\n  */ \r\n    \r\n#define USB_DFU_CONFIG_DESC_SIZ        (18 + (9 * USBD_DFU_MAX_ITF_NUM))\r\n#define USB_DFU_DESC_SIZ               9\r\n    \r\n#define DFU_DESCRIPTOR_TYPE            0x21\r\n    \r\n\r\n/**************************************************/\r\n/* DFU Requests  DFU states                       */\r\n/**************************************************/\r\n#define APP_STATE_IDLE                 0\r\n#define APP_STATE_DETACH               1\r\n#define DFU_STATE_IDLE                 2\r\n#define DFU_STATE_DNLOAD_SYNC          3\r\n#define DFU_STATE_DNLOAD_BUSY          4\r\n#define DFU_STATE_DNLOAD_IDLE          5\r\n#define DFU_STATE_MANIFEST_SYNC        6\r\n#define DFU_STATE_MANIFEST             7\r\n#define DFU_STATE_MANIFEST_WAIT_RESET  8\r\n#define DFU_STATE_UPLOAD_IDLE          9\r\n#define DFU_STATE_ERROR                10\r\n\r\n/**************************************************/\r\n/* DFU errors                                     */\r\n/**************************************************/\r\n#define DFU_ERROR_NONE                 0x00\r\n#define DFU_ERROR_TARGET               0x01\r\n#define DFU_ERROR_FILE                 0x02\r\n#define DFU_ERROR_WRITE                0x03\r\n#define DFU_ERROR_ERASE                0x04\r\n#define DFU_ERROR_CHECK_ERASED         0x05\r\n#define DFU_ERROR_PROG                 0x06\r\n#define DFU_ERROR_VERIFY               0x07\r\n#define DFU_ERROR_ADDRESS              0x08\r\n#define DFU_ERROR_NOTDONE              0x09\r\n#define DFU_ERROR_FIRMWARE             0x0A\r\n#define DFU_ERROR_VENDOR               0x0B\r\n#define DFU_ERROR_USB                  0x0C\r\n#define DFU_ERROR_POR                  0x0D\r\n#define DFU_ERROR_UNKNOWN              0x0E\r\n#define DFU_ERROR_STALLEDPKT           0x0F\r\n\r\n/**************************************************/\r\n/* DFU Manifestation State                        */\r\n/**************************************************/\r\n#define DFU_MANIFEST_COMPLETE          0x00\r\n#define DFU_MANIFEST_IN_PROGRESS       0x01\r\n\r\n\r\n/**************************************************/\r\n/* Special Commands  with Download Request        */\r\n/**************************************************/\r\n#define DFU_CMD_GETCOMMANDS            0x00\r\n#define DFU_CMD_SETADDRESSPOINTER      0x21\r\n#define DFU_CMD_ERASE                  0x41\r\n    \r\n#define DFU_MEDIA_ERASE                0x00\r\n#define DFU_MEDIA_PROGRAM              0x01\r\n\r\n/**************************************************/\r\n/* Other defines                                  */\r\n/**************************************************/\r\n/* Bit Detach capable = bit 3 in bmAttributes field */\r\n#define DFU_DETACH_MASK                (uint8_t)(1 << 4) \r\n#define DFU_STATUS_DEPTH               (6) \r\n    \r\ntypedef enum \r\n{\r\n  DFU_DETACH = 0,\r\n  DFU_DNLOAD ,\r\n  DFU_UPLOAD,\r\n  DFU_GETSTATUS,\r\n  DFU_CLRSTATUS,\r\n  DFU_GETSTATE,\r\n  DFU_ABORT\r\n} DFU_RequestTypeDef;\r\n\r\ntypedef  void (*pFunction)(void);\r\n\r\n\r\n/**********  Descriptor of DFU interface 0 Alternate setting n ****************/  \r\n#define USBD_DFU_IF_DESC(n)            0x09,   /* bLength: Interface Descriptor size */ \\\r\n                                      USB_DESC_TYPE_INTERFACE,   /* bDescriptorType */ \\\r\n                                      0x00,   /* bInterfaceNumber: Number of Interface */ \\\r\n                                      (n),      /* bAlternateSetting: Alternate setting */ \\\r\n                                      0x00,   /* bNumEndpoints*/ \\\r\n                                      0xFE,   /* bInterfaceClass: Application Specific Class Code */ \\\r\n                                      0x01,   /* bInterfaceSubClass : Device Firmware Upgrade Code */ \\\r\n                                      0x02,   /* nInterfaceProtocol: DFU mode protocol */ \\\r\n                                      USBD_IDX_INTERFACE_STR + (n) + 1 /* iInterface: Index of string descriptor */ \\\r\n                                \r\n#define TRANSFER_SIZE_BYTES(size)      ((uint8_t)(size)), /* XFERSIZEB0 */\\\r\n                                       ((uint8_t)(size >> 8)) /* XFERSIZEB1 */\r\n                                             \r\n#define IS_PROTECTED_AREA(add)         (uint8_t)(((add >= 0x08000000) && (add < (APP_DEFAULT_ADD)))? 1:0)                                             \r\n                                            \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_CORE_Exported_TypesDefinitions\r\n  * @{\r\n  */\r\n\r\ntypedef struct\r\n{\r\n  union\r\n  {\r\n    uint32_t d32[USBD_DFU_XFER_SIZE/4];\r\n    uint8_t  d8[USBD_DFU_XFER_SIZE];\r\n  }buffer;\r\n  \r\n  uint8_t              dev_state; \r\n  uint8_t              dev_status[DFU_STATUS_DEPTH];\r\n  uint8_t              manif_state;    \r\n  \r\n  uint32_t             wblock_num;\r\n  uint32_t             wlength;\r\n  uint32_t             data_ptr; \r\n  __IO uint32_t        alt_setting;\r\n  \r\n}\r\nUSBD_DFU_HandleTypeDef; \r\n\r\n\r\ntypedef struct\r\n{\r\n  const uint8_t* pStrDesc;\r\n  uint16_t (* Init)     (void);   \r\n  uint16_t (* DeInit)   (void);   \r\n  uint16_t (* Erase)    (uint32_t Add);\r\n  uint16_t (* Write)    (uint8_t *src, uint8_t *dest, uint32_t Len);\r\n  uint8_t* (* Read)     (uint8_t *src, uint8_t *dest, uint32_t Len);\r\n  uint16_t (* GetStatus)(uint32_t Add, uint8_t cmd, uint8_t *buff);  \r\n}\r\nUSBD_DFU_MediaTypeDef;\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n\r\n/** @defgroup USBD_CORE_Exported_Macros\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_CORE_Exported_Variables\r\n  * @{\r\n  */ \r\n\r\nextern USBD_ClassTypeDef  USBD_DFU;\r\n#define USBD_DFU_CLASS    &USBD_DFU\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USB_CORE_Exported_Functions\r\n  * @{\r\n  */ \r\nuint8_t  USBD_DFU_RegisterMedia    (USBD_HandleTypeDef   *pdev, \r\n                                    USBD_DFU_MediaTypeDef *fops);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif  /* __USB_DFU_H */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Class/DFU/Inc/usbd_dfu_media_template.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_dfu_media_template.h\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   header file for the usbd_dfu_media_template.c file\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __USBD_DFU_MEDIA_TEMPLATE_H\r\n#define __USBD_DFU_MEDIA_TEMPLATE_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_dfu.h\"\r\n\r\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup USBD_MEDIA\r\n  * @brief header file for the usbd_dfu_media_template.c file\r\n  * @{\r\n  */ \r\n\r\n/** @defgroup USBD_MEDIA_Exported_Defines\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_MEDIA_Exported_Types\r\n  * @{\r\n  */\r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n\r\n/** @defgroup USBD_MEDIA_Exported_Macros\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_MEDIA_Exported_Variables\r\n  * @{\r\n  */ \r\nextern USBD_DFU_MediaTypeDef  USBD_DFU_MEDIA_Template_fops;\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_MEDIA_Exported_FunctionsPrototype\r\n  * @{\r\n  */ \r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __USBD_DFU_MEDIA_TEMPLATE_H */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n* @}\r\n*/ \r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_dfu.c\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   This file provides the DFU core functions.\r\n  *\r\n  * @verbatim\r\n  *      \r\n  *          ===================================================================      \r\n  *                                DFU Class Driver Description\r\n  *          =================================================================== \r\n  *           This driver manages the DFU class V1.1 following the \"Device Class Specification for \r\n  *           Device Firmware Upgrade Version 1.1 Aug 5, 2004\".\r\n  *           This driver implements the following aspects of the specification:\r\n  *             - Device descriptor management\r\n  *             - Configuration descriptor management\r\n  *             - Enumeration as DFU device (in DFU mode only)\r\n  *             - Requests management (supporting ST DFU sub-protocol)\r\n  *             - Memory operations management (Download/Upload/Erase/Detach/GetState/GetStatus)\r\n  *             - DFU state machine implementation.\r\n  *          \r\n  *           @note\r\n  *            ST DFU sub-protocol is compliant with DFU protocol and use sub-requests to manage\r\n  *            memory addressing, commands processing, specific memories operations (ie. Erase) ...\r\n  *            As required by the DFU specification, only endpoint 0 is used in this application.\r\n  *            Other endpoints and functions may be added to the application (ie. DFU ...)\r\n  * \r\n  *           These aspects may be enriched or modified for a specific user application.\r\n  *          \r\n  *           This driver doesn't implement the following aspects of the specification \r\n  *           (but it is possible to manage these features with some modifications on this driver):\r\n  *             - Manifestation Tolerant mode\r\n  *      \r\n  *  @endverbatim\r\n  *\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_dfu.h\"\r\n#include \"usbd_desc.h\"\r\n#include \"usbd_ctlreq.h\"\r\n\r\n\r\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n\r\n\r\n/** @defgroup USBD_DFU \r\n  * @brief usbd core module\r\n  * @{\r\n  */ \r\n\r\n/** @defgroup USBD_DFU_Private_TypesDefinitions\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_DFU_Private_Defines\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_DFU_Private_Macros\r\n  * @{\r\n  */ \r\n#define DFU_SAMPLE_FREQ(frq)      (uint8_t)(frq), (uint8_t)((frq >> 8)), (uint8_t)((frq >> 16))\r\n\r\n#define DFU_PACKET_SZE(frq)          (uint8_t)(((frq * 2 * 2)/1000) & 0xFF), \\\r\n                                       (uint8_t)((((frq * 2 * 2)/1000) >> 8) & 0xFF)\r\n                                         \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n\r\n\r\n/** @defgroup USBD_DFU_Private_FunctionPrototypes\r\n  * @{\r\n  */\r\n\r\n\r\nstatic uint8_t  USBD_DFU_Init (USBD_HandleTypeDef *pdev, \r\n                               uint8_t cfgidx);\r\n\r\nstatic uint8_t  USBD_DFU_DeInit (USBD_HandleTypeDef *pdev, \r\n                                 uint8_t cfgidx);\r\n\r\nstatic uint8_t  USBD_DFU_Setup (USBD_HandleTypeDef *pdev, \r\n                                USBD_SetupReqTypedef *req);\r\n\r\nstatic uint8_t  *USBD_DFU_GetCfgDesc (uint16_t *length);\r\n\r\nstatic uint8_t  *USBD_DFU_GetDeviceQualifierDesc (uint16_t *length);\r\n\r\nstatic uint8_t  USBD_DFU_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum);\r\n\r\nstatic uint8_t  USBD_DFU_DataOut (USBD_HandleTypeDef *pdev, uint8_t epnum);\r\n\r\nstatic uint8_t  USBD_DFU_EP0_RxReady (USBD_HandleTypeDef *pdev);\r\n\r\nstatic uint8_t  USBD_DFU_EP0_TxReady (USBD_HandleTypeDef *pdev);\r\n\r\nstatic uint8_t  USBD_DFU_SOF (USBD_HandleTypeDef *pdev);\r\n\r\nstatic uint8_t  USBD_DFU_IsoINIncomplete (USBD_HandleTypeDef *pdev, uint8_t epnum);\r\n\r\nstatic uint8_t  USBD_DFU_IsoOutIncomplete (USBD_HandleTypeDef *pdev, uint8_t epnum);\r\n\r\n#if (USBD_SUPPORT_USER_STRING == 1)  \r\nstatic uint8_t* USBD_DFU_GetUsrStringDesc ( USBD_HandleTypeDef *pdev, uint8_t index , uint16_t *length);\r\n#endif\r\n\r\nstatic void DFU_Detach    (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);\r\n\r\nstatic void DFU_Download  (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);\r\n\r\nstatic void DFU_Upload    (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);\r\n\r\nstatic void DFU_GetStatus (USBD_HandleTypeDef *pdev);\r\n\r\nstatic void DFU_ClearStatus (USBD_HandleTypeDef *pdev);\r\n\r\nstatic void DFU_GetState  (USBD_HandleTypeDef *pdev);\r\n\r\nstatic void DFU_Abort     (USBD_HandleTypeDef *pdev);\r\n\r\nstatic void DFU_Leave  (USBD_HandleTypeDef *pdev); \r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_DFU_Private_Variables\r\n  * @{\r\n  */ \r\n\r\nUSBD_ClassTypeDef  USBD_DFU = \r\n{\r\n  USBD_DFU_Init,\r\n  USBD_DFU_DeInit,\r\n  USBD_DFU_Setup,\r\n  USBD_DFU_EP0_TxReady,  \r\n  USBD_DFU_EP0_RxReady,\r\n  USBD_DFU_DataIn,\r\n  USBD_DFU_DataOut,\r\n  USBD_DFU_SOF,\r\n  USBD_DFU_IsoINIncomplete,\r\n  USBD_DFU_IsoOutIncomplete,      \r\n  USBD_DFU_GetCfgDesc,\r\n  USBD_DFU_GetCfgDesc, \r\n  USBD_DFU_GetCfgDesc,\r\n  USBD_DFU_GetDeviceQualifierDesc,\r\n#if (USBD_SUPPORT_USER_STRING == 1)  \r\n  USBD_DFU_GetUsrStringDesc\r\n#endif\r\n};\r\n\r\n/* USB DFU device Configuration Descriptor */\r\n__ALIGN_BEGIN static uint8_t USBD_DFU_CfgDesc[USB_DFU_CONFIG_DESC_SIZ] __ALIGN_END =\r\n{\r\n  0x09, /* bLength: Configuation Descriptor size */\r\n  USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */\r\n  USB_DFU_CONFIG_DESC_SIZ,\r\n  /* wTotalLength: Bytes returned */\r\n  0x00,\r\n  0x01,         /*bNumInterfaces: 1 interface*/\r\n  0x01,         /*bConfigurationValue: Configuration value*/\r\n  0x02,         /*iConfiguration: Index of string descriptor describing the configuration*/\r\n  0xC0,         /*bmAttributes: bus powered and Supprts Remote Wakeup */\r\n  0x32,         /*MaxPower 100 mA: this current is used for detecting Vbus*/\r\n  /* 09 */\r\n  \r\n  /**********  Descriptor of DFU interface 0 Alternate setting 0 **************/  \r\n  USBD_DFU_IF_DESC(0), /* This interface is mandatory for all devices */\r\n  \r\n#if (USBD_DFU_MAX_ITF_NUM > 1)\r\n  /**********  Descriptor of DFU interface 0 Alternate setting 1 **************/ \r\n  USBD_DFU_IF_DESC(1),\r\n#endif /* (USBD_DFU_MAX_ITF_NUM > 1) */\r\n\r\n#if (USBD_DFU_MAX_ITF_NUM > 2)\r\n  /**********  Descriptor of DFU interface 0 Alternate setting 2 **************/ \r\n  USBD_DFU_IF_DESC(2),\r\n#endif /* (USBD_DFU_MAX_ITF_NUM > 2) */\r\n\r\n#if (USBD_DFU_MAX_ITF_NUM > 3)\r\n  /**********  Descriptor of DFU interface 0 Alternate setting 3 **************/ \r\n  USBD_DFU_IF_DESC(3),\r\n#endif /* (USBD_DFU_MAX_ITF_NUM > 3) */\r\n\r\n#if (USBD_DFU_MAX_ITF_NUM > 4)\r\n  /**********  Descriptor of DFU interface 0 Alternate setting 4 **************/ \r\n  USBD_DFU_IF_DESC(4),\r\n#endif /* (USBD_DFU_MAX_ITF_NUM > 4) */\r\n\r\n#if (USBD_DFU_MAX_ITF_NUM > 5)\r\n  /**********  Descriptor of DFU interface 0 Alternate setting 5 **************/ \r\n  USBD_DFU_IF_DESC(5),\r\n#endif /* (USBD_DFU_MAX_ITF_NUM > 5) */\r\n\r\n#if (USBD_DFU_MAX_ITF_NUM > 6)\r\n#error \"ERROR: usbd_dfu_core.c: Modify the file to support more descriptors!\"\r\n#endif /* (USBD_DFU_MAX_ITF_NUM > 6) */\r\n\r\n  /******************** DFU Functional Descriptor********************/\r\n  0x09,   /*blength = 9 Bytes*/\r\n  DFU_DESCRIPTOR_TYPE,   /* DFU Functional Descriptor*/\r\n  0x0B,   /*bmAttribute\r\n                bitCanDnload             = 1      (bit 0)\r\n                bitCanUpload             = 1      (bit 1)\r\n                bitManifestationTolerant = 0      (bit 2)\r\n                bitWillDetach            = 1      (bit 3)\r\n                Reserved                          (bit4-6)\r\n                bitAcceleratedST         = 0      (bit 7)*/\r\n  0xFF,   /*DetachTimeOut= 255 ms*/\r\n  0x00,\r\n  /*WARNING: In DMA mode the multiple MPS packets feature is still not supported\r\n   ==> In this case, when using DMA USBD_DFU_XFER_SIZE should be set to 64 in usbd_conf.h */\r\n  TRANSFER_SIZE_BYTES(USBD_DFU_XFER_SIZE),       /* TransferSize = 1024 Byte*/         \r\n  0x1A,                                /* bcdDFUVersion*/\r\n  0x01\r\n  /***********************************************************/\r\n  /* 9*/\r\n};\r\n  \r\n/* USB Standard Device Descriptor */\r\n__ALIGN_BEGIN static uint8_t USBD_DFU_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END =\r\n{\r\n  USB_LEN_DEV_QUALIFIER_DESC,\r\n  USB_DESC_TYPE_DEVICE_QUALIFIER,\r\n  0x00,\r\n  0x02,\r\n  0x00,\r\n  0x00,\r\n  0x00,\r\n  0x40,\r\n  0x01,\r\n  0x00,\r\n};\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_DFU_Private_Functions\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @brief  USBD_DFU_Init\r\n  *         Initialize the DFU interface\r\n  * @param  pdev: device instance\r\n  * @param  cfgidx: Configuration index\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_DFU_Init (USBD_HandleTypeDef *pdev, \r\n                               uint8_t cfgidx)\r\n{\r\n  USBD_DFU_HandleTypeDef   *hdfu;\r\n  \r\n /* Allocate Audio structure */\r\n  pdev->pClassData = USBD_malloc(sizeof (USBD_DFU_HandleTypeDef));\r\n  \r\n  if(pdev->pClassData == NULL)\r\n  {\r\n    return USBD_FAIL; \r\n  }\r\n  else\r\n  {\r\n    hdfu = (USBD_DFU_HandleTypeDef*) pdev->pClassData;\r\n    \r\n    hdfu->alt_setting = 0;\r\n    hdfu->data_ptr = USBD_DFU_APP_DEFAULT_ADD;\r\n    hdfu->wblock_num = 0;\r\n    hdfu->wlength = 0;\r\n    \r\n    hdfu->manif_state = DFU_MANIFEST_COMPLETE;\r\n    hdfu->dev_state = DFU_STATE_IDLE;\r\n    \r\n    hdfu->dev_status[0] = DFU_ERROR_NONE;\r\n    hdfu->dev_status[1] = 0;\r\n    hdfu->dev_status[2] = 0;   \r\n    hdfu->dev_status[3] = 0;\r\n    hdfu->dev_status[4] = DFU_STATE_IDLE;    \r\n    hdfu->dev_status[5] = 0;    \r\n    \r\n    /* Initialize Hardware layer */\r\n    if (((USBD_DFU_MediaTypeDef *)pdev->pUserData)->Init() != USBD_OK)\r\n    {\r\n      return USBD_FAIL;\r\n    }   \r\n  }\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_DFU_Init\r\n  *         De-Initialize the DFU layer\r\n  * @param  pdev: device instance\r\n  * @param  cfgidx: Configuration index\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_DFU_DeInit (USBD_HandleTypeDef *pdev, \r\n                                 uint8_t cfgidx)\r\n{\r\n  USBD_DFU_HandleTypeDef   *hdfu;\r\n  hdfu = (USBD_DFU_HandleTypeDef*) pdev->pClassData;\r\n  \r\n  hdfu->wblock_num = 0;\r\n  hdfu->wlength = 0;\r\n\r\n  hdfu->dev_state = DFU_STATE_IDLE;\r\n  hdfu->dev_status[0] = DFU_ERROR_NONE;\r\n  hdfu->dev_status[4] = DFU_STATE_IDLE;\r\n \r\n  /* DeInit  physical Interface components */\r\n  if(pdev->pClassData != NULL)\r\n  {\r\n    /* De-Initialize Hardware layer */\r\n    ((USBD_DFU_MediaTypeDef *)pdev->pUserData)->DeInit(); \r\n    USBD_free(pdev->pClassData);\r\n    pdev->pClassData = NULL;\r\n  } \r\n\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_DFU_Setup\r\n  *         Handle the DFU specific requests\r\n  * @param  pdev: instance\r\n  * @param  req: usb requests\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_DFU_Setup (USBD_HandleTypeDef *pdev, \r\n                                USBD_SetupReqTypedef *req)\r\n{\r\n  uint8_t *pbuf = 0;\r\n  uint16_t len = 0;\r\n  uint8_t ret = USBD_OK;\r\n  USBD_DFU_HandleTypeDef   *hdfu;\r\n  \r\n  hdfu = (USBD_DFU_HandleTypeDef*) pdev->pClassData;\r\n  \r\n  switch (req->bmRequest & USB_REQ_TYPE_MASK)\r\n  {\r\n  case USB_REQ_TYPE_CLASS :  \r\n    switch (req->bRequest)\r\n    {\r\n    case DFU_DNLOAD:\r\n      DFU_Download(pdev, req);\r\n      break;\r\n      \r\n    case DFU_UPLOAD:\r\n      DFU_Upload(pdev, req);   \r\n      break;\r\n      \r\n    case DFU_GETSTATUS:\r\n      DFU_GetStatus(pdev);\r\n      break;\r\n      \r\n    case DFU_CLRSTATUS:\r\n      DFU_ClearStatus(pdev);\r\n      break;      \r\n      \r\n    case DFU_GETSTATE:\r\n      DFU_GetState(pdev);\r\n      break;  \r\n      \r\n    case DFU_ABORT:\r\n      DFU_Abort(pdev);\r\n      break;\r\n      \r\n    case DFU_DETACH:\r\n      DFU_Detach(pdev, req);\r\n      break;\r\n      \r\n      \r\n    default:\r\n      USBD_CtlError (pdev, req);\r\n      ret = USBD_FAIL; \r\n    }\r\n    break;\r\n    \r\n  case USB_REQ_TYPE_STANDARD:\r\n    switch (req->bRequest)\r\n    {\r\n    case USB_REQ_GET_DESCRIPTOR: \r\n      if( (req->wValue >> 8) == DFU_DESCRIPTOR_TYPE)\r\n      {\r\n        pbuf = USBD_DFU_CfgDesc + (9 * (USBD_DFU_MAX_ITF_NUM + 1));\r\n        len = MIN(USB_DFU_DESC_SIZ , req->wLength);\r\n      }\r\n      \r\n      USBD_CtlSendData (pdev, \r\n                        pbuf,\r\n                        len);\r\n      break;\r\n      \r\n    case USB_REQ_GET_INTERFACE :\r\n      USBD_CtlSendData (pdev,\r\n                        (uint8_t *)&hdfu->alt_setting,\r\n                        1);\r\n      break;\r\n      \r\n    case USB_REQ_SET_INTERFACE :\r\n      if ((uint8_t)(req->wValue) < USBD_DFU_MAX_ITF_NUM)\r\n      {\r\n        hdfu->alt_setting = (uint8_t)(req->wValue);\r\n      }\r\n      else\r\n      {\r\n        /* Call the error management function (command will be nacked */\r\n        USBD_CtlError (pdev, req);\r\n        ret = USBD_FAIL;  \r\n      }\r\n      break;\r\n      \r\n    default:\r\n      USBD_CtlError (pdev, req);\r\n      ret = USBD_FAIL;     \r\n    }\r\n  }\r\n  return ret;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  USBD_DFU_GetCfgDesc \r\n  *         return configuration descriptor\r\n  * @param  speed : current device speed\r\n  * @param  length : pointer data length\r\n  * @retval pointer to descriptor buffer\r\n  */\r\nstatic uint8_t  *USBD_DFU_GetCfgDesc (uint16_t *length)\r\n{\r\n  *length = sizeof (USBD_DFU_CfgDesc);\r\n  return USBD_DFU_CfgDesc;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_DFU_DataIn\r\n  *         handle data IN Stage\r\n  * @param  pdev: device instance\r\n  * @param  epnum: endpoint index\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_DFU_DataIn (USBD_HandleTypeDef *pdev, \r\n                              uint8_t epnum)\r\n{\r\n\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_DFU_EP0_RxReady\r\n  *         handle EP0 Rx Ready event\r\n  * @param  pdev: device instance\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_DFU_EP0_RxReady (USBD_HandleTypeDef *pdev)\r\n{\r\n\r\n  return USBD_OK;\r\n}\r\n/**\r\n  * @brief  USBD_DFU_EP0_TxReady\r\n  *         handle EP0 TRx Ready event\r\n  * @param  pdev: device instance\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_DFU_EP0_TxReady (USBD_HandleTypeDef *pdev)\r\n{\r\n uint32_t addr;\r\n USBD_SetupReqTypedef     req; \r\n USBD_DFU_HandleTypeDef   *hdfu;\r\n \r\n hdfu = (USBD_DFU_HandleTypeDef*) pdev->pClassData;\r\n  \r\n  if (hdfu->dev_state == DFU_STATE_DNLOAD_BUSY)\r\n  {\r\n    /* Decode the Special Command*/\r\n    if (hdfu->wblock_num == 0)   \r\n    {\r\n      if ((hdfu->buffer.d8[0] ==  DFU_CMD_GETCOMMANDS) && (hdfu->wlength == 1))\r\n      {\r\n       \r\n      }\r\n      else if  (( hdfu->buffer.d8[0] ==  DFU_CMD_SETADDRESSPOINTER ) && (hdfu->wlength == 5))\r\n      {\r\n        hdfu->data_ptr  = hdfu->buffer.d8[1];\r\n        hdfu->data_ptr += hdfu->buffer.d8[2] << 8;\r\n        hdfu->data_ptr += hdfu->buffer.d8[3] << 16;\r\n        hdfu->data_ptr += hdfu->buffer.d8[4] << 24;\r\n      }\r\n      else if (( hdfu->buffer.d8[0] ==  DFU_CMD_ERASE ) && (hdfu->wlength == 5))\r\n      {\r\n        hdfu->data_ptr  = hdfu->buffer.d8[1];\r\n        hdfu->data_ptr += hdfu->buffer.d8[2] << 8;\r\n        hdfu->data_ptr += hdfu->buffer.d8[3] << 16;\r\n        hdfu->data_ptr += hdfu->buffer.d8[4] << 24;\r\n       \r\n        if (((USBD_DFU_MediaTypeDef *)pdev->pUserData)->Erase(hdfu->data_ptr) != USBD_OK)\r\n        {\r\n          return USBD_FAIL;\r\n        }\r\n      }\r\n      else\r\n      {\r\n        /* Reset the global length and block number */\r\n        hdfu->wlength = 0;\r\n        hdfu->wblock_num = 0;     \r\n        /* Call the error management function (command will be nacked) */\r\n        req.bmRequest = 0;\r\n        req.wLength = 1;\r\n        USBD_CtlError (pdev, &req);\r\n      }\r\n    }\r\n    /* Regular Download Command */\r\n    else if (hdfu->wblock_num > 1)  \r\n    {\r\n      /* Decode the required address */\r\n      addr = ((hdfu->wblock_num - 2) * USBD_DFU_XFER_SIZE) + hdfu->data_ptr;\r\n      \r\n      /* Preform the write operation */\r\n      if (((USBD_DFU_MediaTypeDef *)pdev->pUserData)->Write(hdfu->buffer.d8, (uint8_t *)addr, hdfu->wlength) != USBD_OK)\r\n      {\r\n        return USBD_FAIL;\r\n      }      \r\n    }\r\n    /* Reset the global length and block number */\r\n    hdfu->wlength = 0;\r\n    hdfu->wblock_num = 0;\r\n    \r\n    /* Update the state machine */\r\n    hdfu->dev_state =  DFU_STATE_DNLOAD_SYNC;\r\n\r\n    hdfu->dev_status[1] = 0;\r\n    hdfu->dev_status[2] = 0;\r\n    hdfu->dev_status[3] = 0;\r\n    hdfu->dev_status[4] = hdfu->dev_state;    \r\n    return USBD_OK;\r\n  }\r\n  else if (hdfu->dev_state == DFU_STATE_MANIFEST)/* Manifestation in progress*/\r\n  {\r\n    /* Start leaving DFU mode */\r\n    DFU_Leave(pdev);\r\n  }\r\n  \r\n  return USBD_OK;\r\n}\r\n/**\r\n  * @brief  USBD_DFU_SOF\r\n  *         handle SOF event\r\n  * @param  pdev: device instance\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_DFU_SOF (USBD_HandleTypeDef *pdev)\r\n{\r\n\r\n  return USBD_OK;\r\n}\r\n/**\r\n  * @brief  USBD_DFU_IsoINIncomplete\r\n  *         handle data ISO IN Incomplete event\r\n  * @param  pdev: device instance\r\n  * @param  epnum: endpoint index\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_DFU_IsoINIncomplete (USBD_HandleTypeDef *pdev, uint8_t epnum)\r\n{\r\n\r\n  return USBD_OK;\r\n}\r\n/**\r\n  * @brief  USBD_DFU_IsoOutIncomplete\r\n  *         handle data ISO OUT Incomplete event\r\n  * @param  pdev: device instance\r\n  * @param  epnum: endpoint index\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_DFU_IsoOutIncomplete (USBD_HandleTypeDef *pdev, uint8_t epnum)\r\n{\r\n\r\n  return USBD_OK;\r\n}\r\n/**\r\n  * @brief  USBD_DFU_DataOut\r\n  *         handle data OUT Stage\r\n  * @param  pdev: device instance\r\n  * @param  epnum: endpoint index\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_DFU_DataOut (USBD_HandleTypeDef *pdev, \r\n                              uint8_t epnum)\r\n{\r\n\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n* @brief  DeviceQualifierDescriptor \r\n*         return Device Qualifier descriptor\r\n* @param  length : pointer data length\r\n* @retval pointer to descriptor buffer\r\n*/\r\nstatic uint8_t  *USBD_DFU_GetDeviceQualifierDesc (uint16_t *length)\r\n{\r\n  *length = sizeof (USBD_DFU_DeviceQualifierDesc);\r\n  return USBD_DFU_DeviceQualifierDesc;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_DFU_GetUsrStringDesc\r\n  *         Manages the transfer of memory interfaces string descriptors.\r\n  * @param  speed : current device speed\r\n  * @param  index: desciptor index\r\n  * @param  length : pointer data length\r\n  * @retval pointer to the descriptor table or NULL if the descriptor is not supported.\r\n  */\r\n#if (USBD_SUPPORT_USER_STRING == 1)  \r\nstatic uint8_t* USBD_DFU_GetUsrStringDesc (USBD_HandleTypeDef *pdev, uint8_t index , uint16_t *length)\r\n{\r\n  static uint8_t USBD_StrDesc[255];\r\n  /* Check if the requested string interface is supported */\r\n  if (index <= (USBD_IDX_INTERFACE_STR + USBD_DFU_MAX_ITF_NUM))\r\n  {\r\n    USBD_GetString ((uint8_t *)((USBD_DFU_MediaTypeDef *)pdev->pUserData)->pStrDesc, USBD_StrDesc, length);\r\n    return USBD_StrDesc;  \r\n  }\r\n  /* Not supported Interface Descriptor index */\r\n  else\r\n  {\r\n    return NULL;\r\n  }\r\n}\r\n#endif\r\n\r\n/**\r\n* @brief  USBD_MSC_RegisterStorage\r\n* @param  fops: storage callback\r\n* @retval status\r\n*/\r\nuint8_t  USBD_DFU_RegisterMedia    (USBD_HandleTypeDef   *pdev, \r\n                                    USBD_DFU_MediaTypeDef *fops)\r\n{\r\n  if(fops != NULL)\r\n  {\r\n    pdev->pUserData= fops;\r\n  }\r\n  return 0;\r\n}\r\n\r\n/******************************************************************************\r\n     DFU Class requests management\r\n******************************************************************************/\r\n/**\r\n  * @brief  DFU_Detach\r\n  *         Handles the DFU DETACH request.\r\n  * @param  pdev: device instance\r\n  * @param  req: pointer to the request structure.\r\n  * @retval None.\r\n  */\r\nstatic void DFU_Detach(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)\r\n{\r\n USBD_DFU_HandleTypeDef   *hdfu;\r\n \r\n hdfu = (USBD_DFU_HandleTypeDef*) pdev->pClassData;\r\n \r\n  if (hdfu->dev_state == DFU_STATE_IDLE || hdfu->dev_state == DFU_STATE_DNLOAD_SYNC\r\n      || hdfu->dev_state == DFU_STATE_DNLOAD_IDLE || hdfu->dev_state == DFU_STATE_MANIFEST_SYNC\r\n        || hdfu->dev_state == DFU_STATE_UPLOAD_IDLE )\r\n  {\r\n    /* Update the state machine */\r\n    hdfu->dev_state = DFU_STATE_IDLE;\r\n    hdfu->dev_status[0] = DFU_ERROR_NONE;\r\n    hdfu->dev_status[1] = 0;\r\n    hdfu->dev_status[2] = 0;\r\n    hdfu->dev_status[3] = 0; /*bwPollTimeout=0ms*/\r\n    hdfu->dev_status[4] = hdfu->dev_state;\r\n    hdfu->dev_status[5] = 0; /*iString*/\r\n    hdfu->wblock_num = 0;\r\n    hdfu->wlength = 0;\r\n  } \r\n  \r\n  /* Check the detach capability in the DFU functional descriptor */\r\n  if ((USBD_DFU_CfgDesc[12 + (9 * USBD_DFU_MAX_ITF_NUM)]) & DFU_DETACH_MASK)\r\n  {\r\n    /* Perform an Attach-Detach operation on USB bus */\r\n    USBD_Stop (pdev);\r\n    USBD_Start (pdev);  \r\n  }\r\n  else\r\n  {\r\n    /* Wait for the period of time specified in Detach request */\r\n    USBD_Delay (req->wValue);  \r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  DFU_Download\r\n  *         Handles the DFU DNLOAD request.\r\n  * @param  pdev: device instance\r\n  * @param  req: pointer to the request structure\r\n  * @retval None\r\n  */\r\nstatic void DFU_Download(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)\r\n{\r\n USBD_DFU_HandleTypeDef   *hdfu;\r\n \r\n hdfu = (USBD_DFU_HandleTypeDef*) pdev->pClassData;\r\n \r\n  /* Data setup request */\r\n  if (req->wLength > 0)\r\n  {\r\n    if ((hdfu->dev_state == DFU_STATE_IDLE) || (hdfu->dev_state == DFU_STATE_DNLOAD_IDLE))\r\n    {\r\n      /* Update the global length and block number */\r\n      hdfu->wblock_num = req->wValue;\r\n      hdfu->wlength = req->wLength;\r\n      \r\n      /* Update the state machine */\r\n      hdfu->dev_state = DFU_STATE_DNLOAD_SYNC;\r\n      hdfu->dev_status[4] = hdfu->dev_state;\r\n      \r\n      /* Prepare the reception of the buffer over EP0 */\r\n      USBD_CtlPrepareRx (pdev,\r\n                         (uint8_t*)hdfu->buffer.d8,                                  \r\n                         hdfu->wlength);\r\n    }\r\n    /* Unsupported state */\r\n    else\r\n    {\r\n      /* Call the error management function (command will be nacked */\r\n      USBD_CtlError (pdev, req);\r\n    }\r\n  }\r\n  /* 0 Data DNLOAD request */\r\n  else\r\n  {\r\n    /* End of DNLOAD operation*/\r\n    if (hdfu->dev_state == DFU_STATE_DNLOAD_IDLE || hdfu->dev_state == DFU_STATE_IDLE )\r\n    {\r\n      hdfu->manif_state = DFU_MANIFEST_IN_PROGRESS;\r\n      hdfu->dev_state = DFU_STATE_MANIFEST_SYNC;\r\n      hdfu->dev_status[1] = 0;\r\n      hdfu->dev_status[2] = 0;\r\n      hdfu->dev_status[3] = 0;\r\n      hdfu->dev_status[4] = hdfu->dev_state;        \r\n    }\r\n    else\r\n    {\r\n      /* Call the error management function (command will be nacked */\r\n      USBD_CtlError (pdev, req);\r\n    }\r\n  }  \r\n}\r\n\r\n/**\r\n  * @brief  DFU_Upload\r\n  *         Handles the DFU UPLOAD request.\r\n  * @param  pdev: instance\r\n  * @param  req: pointer to the request structure\r\n  * @retval status\r\n  */\r\nstatic void DFU_Upload(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)\r\n{\r\n USBD_DFU_HandleTypeDef   *hdfu;\r\n \r\n hdfu = (USBD_DFU_HandleTypeDef*) pdev->pClassData;\r\n \r\n  uint8_t *phaddr = NULL;\r\n  uint32_t addr = 0;\r\n  \r\n  /* Data setup request */\r\n  if (req->wLength > 0)\r\n  {\r\n    if ((hdfu->dev_state == DFU_STATE_IDLE) || (hdfu->dev_state == DFU_STATE_UPLOAD_IDLE))\r\n    {\r\n      /* Update the global length and block number */\r\n      hdfu->wblock_num = req->wValue;\r\n      hdfu->wlength = req->wLength;\r\n      \r\n      /* DFU Get Command */\r\n      if (hdfu->wblock_num == 0)  \r\n      {\r\n        /* Update the state machine */\r\n        hdfu->dev_state = (hdfu->wlength > 3)? DFU_STATE_IDLE:DFU_STATE_UPLOAD_IDLE;        \r\n    \r\n        hdfu->dev_status[1] = 0;\r\n        hdfu->dev_status[2] = 0;\r\n        hdfu->dev_status[3] = 0;\r\n        hdfu->dev_status[4] = hdfu->dev_state;       \r\n        \r\n        /* Store the values of all supported commands */\r\n        hdfu->buffer.d8[0] = DFU_CMD_GETCOMMANDS;\r\n        hdfu->buffer.d8[1] = DFU_CMD_SETADDRESSPOINTER;\r\n        hdfu->buffer.d8[2] = DFU_CMD_ERASE;\r\n        \r\n        /* Send the status data over EP0 */\r\n        USBD_CtlSendData (pdev,\r\n                          (uint8_t *)(&(hdfu->buffer.d8[0])),\r\n                          3);\r\n      }\r\n      else if (hdfu->wblock_num > 1)\r\n      {\r\n        hdfu->dev_state = DFU_STATE_UPLOAD_IDLE ;\r\n        \r\n        hdfu->dev_status[1] = 0;\r\n        hdfu->dev_status[2] = 0;\r\n        hdfu->dev_status[3] = 0;\r\n        hdfu->dev_status[4] = hdfu->dev_state;\r\n        \r\n        addr = ((hdfu->wblock_num - 2) * USBD_DFU_XFER_SIZE) + hdfu->data_ptr;  /* Change is Accelerated*/\r\n        \r\n        /* Return the physical address where data are stored */\r\n        phaddr =  ((USBD_DFU_MediaTypeDef *)pdev->pUserData)->Read((uint8_t *)addr, hdfu->buffer.d8, hdfu->wlength);  \r\n        \r\n        /* Send the status data over EP0 */\r\n        USBD_CtlSendData (pdev,\r\n                          phaddr,\r\n                          hdfu->wlength);\r\n      }\r\n      else  /* unsupported hdfu->wblock_num */\r\n      {\r\n        hdfu->dev_state = DFU_ERROR_STALLEDPKT;\r\n        \r\n        hdfu->dev_status[1] = 0;\r\n        hdfu->dev_status[2] = 0;\r\n        hdfu->dev_status[3] = 0;\r\n        hdfu->dev_status[4] = hdfu->dev_state;        \r\n        \r\n        /* Call the error management function (command will be nacked */\r\n        USBD_CtlError (pdev, req); \r\n      }\r\n    }\r\n    /* Unsupported state */\r\n    else\r\n    {\r\n      hdfu->wlength = 0;\r\n      hdfu->wblock_num = 0;   \r\n      /* Call the error management function (command will be nacked */\r\n      USBD_CtlError (pdev, req);\r\n    }\r\n  }\r\n  /* No Data setup request */\r\n  else\r\n  {\r\n    hdfu->dev_state = DFU_STATE_IDLE;\r\n     \r\n    hdfu->dev_status[1] = 0;\r\n    hdfu->dev_status[2] = 0;\r\n    hdfu->dev_status[3] = 0;\r\n    hdfu->dev_status[4] = hdfu->dev_state;\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  DFU_GetStatus\r\n  *         Handles the DFU GETSTATUS request.\r\n  * @param  pdev: instance\r\n  * @retval status\r\n  */\r\nstatic void DFU_GetStatus(USBD_HandleTypeDef *pdev)\r\n{\r\n USBD_DFU_HandleTypeDef   *hdfu;\r\n \r\n hdfu = (USBD_DFU_HandleTypeDef*) pdev->pClassData;\r\n \r\n  switch (hdfu->dev_state)\r\n  {\r\n  case   DFU_STATE_DNLOAD_SYNC:\r\n    if (hdfu->wlength != 0)\r\n    {\r\n      hdfu->dev_state = DFU_STATE_DNLOAD_BUSY;\r\n       \r\n      hdfu->dev_status[1] = 0;\r\n      hdfu->dev_status[2] = 0;\r\n      hdfu->dev_status[3] = 0;\r\n      hdfu->dev_status[4] = hdfu->dev_state;\r\n      \r\n      if ((hdfu->wblock_num == 0) && (hdfu->buffer.d8[0] == DFU_CMD_ERASE))\r\n      {\r\n        ((USBD_DFU_MediaTypeDef *)pdev->pUserData)->GetStatus(hdfu->data_ptr, DFU_MEDIA_ERASE, hdfu->dev_status);\r\n      }\r\n      else\r\n      {\r\n        ((USBD_DFU_MediaTypeDef *)pdev->pUserData)->GetStatus(hdfu->data_ptr, DFU_MEDIA_PROGRAM, hdfu->dev_status);\r\n      }\r\n    }\r\n    else  /* (hdfu->wlength==0)*/\r\n    {\r\n      hdfu->dev_state = DFU_STATE_DNLOAD_IDLE;\r\n\r\n      hdfu->dev_status[1] = 0;\r\n      hdfu->dev_status[2] = 0;\r\n      hdfu->dev_status[3] = 0;\r\n      hdfu->dev_status[4] = hdfu->dev_state;     \r\n    }\r\n    break;\r\n    \r\n  case   DFU_STATE_MANIFEST_SYNC :\r\n    if (hdfu->manif_state == DFU_MANIFEST_IN_PROGRESS)\r\n    {\r\n      hdfu->dev_state = DFU_STATE_MANIFEST;\r\n      \r\n      hdfu->dev_status[1] = 1;             /*bwPollTimeout = 1ms*/\r\n      hdfu->dev_status[2] = 0;\r\n      hdfu->dev_status[3] = 0;\r\n      hdfu->dev_status[4] = hdfu->dev_state;   \r\n    }\r\n    else if ((hdfu->manif_state == DFU_MANIFEST_COMPLETE) && \\\r\n      ((USBD_DFU_CfgDesc[(11 + (9 * USBD_DFU_MAX_ITF_NUM))]) & 0x04))\r\n    {\r\n      hdfu->dev_state = DFU_STATE_IDLE;\r\n      \r\n      hdfu->dev_status[1] = 0;\r\n      hdfu->dev_status[2] = 0;\r\n      hdfu->dev_status[3] = 0;\r\n      hdfu->dev_status[4] = hdfu->dev_state;      \r\n    }\r\n    break;\r\n    \r\n  default :\r\n    break;\r\n  }\r\n  \r\n  /* Send the status data over EP0 */\r\n  USBD_CtlSendData (pdev,\r\n                    (uint8_t *)(&(hdfu->dev_status[0])),\r\n                    6);\r\n}\r\n\r\n/**\r\n  * @brief  DFU_ClearStatus \r\n  *         Handles the DFU CLRSTATUS request.\r\n  * @param  pdev: device instance\r\n  * @retval status\r\n  */\r\nstatic void DFU_ClearStatus(USBD_HandleTypeDef *pdev)\r\n{\r\n USBD_DFU_HandleTypeDef   *hdfu;\r\n \r\n hdfu = (USBD_DFU_HandleTypeDef*) pdev->pClassData;\r\n \r\n  if (hdfu->dev_state == DFU_STATE_ERROR)\r\n  {\r\n    hdfu->dev_state = DFU_STATE_IDLE;\r\n    hdfu->dev_status[0] = DFU_ERROR_NONE;/*bStatus*/\r\n    hdfu->dev_status[1] = 0;\r\n    hdfu->dev_status[2] = 0;\r\n    hdfu->dev_status[3] = 0; /*bwPollTimeout=0ms*/\r\n    hdfu->dev_status[4] = hdfu->dev_state;/*bState*/\r\n    hdfu->dev_status[5] = 0;/*iString*/\r\n  }\r\n  else\r\n  {   /*State Error*/\r\n    hdfu->dev_state = DFU_STATE_ERROR;\r\n    hdfu->dev_status[0] = DFU_ERROR_UNKNOWN;/*bStatus*/\r\n    hdfu->dev_status[1] = 0;\r\n    hdfu->dev_status[2] = 0;\r\n    hdfu->dev_status[3] = 0; /*bwPollTimeout=0ms*/\r\n    hdfu->dev_status[4] = hdfu->dev_state;/*bState*/\r\n    hdfu->dev_status[5] = 0;/*iString*/\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief  DFU_GetState\r\n  *         Handles the DFU GETSTATE request.\r\n  * @param  pdev: device instance\r\n  * @retval None\r\n  */\r\nstatic void DFU_GetState(USBD_HandleTypeDef *pdev)\r\n{\r\n USBD_DFU_HandleTypeDef   *hdfu;\r\n \r\n hdfu = (USBD_DFU_HandleTypeDef*) pdev->pClassData;\r\n \r\n  /* Return the current state of the DFU interface */\r\n  USBD_CtlSendData (pdev, \r\n                    &hdfu->dev_state,\r\n                    1);  \r\n}\r\n\r\n/**\r\n  * @brief  DFU_Abort\r\n  *         Handles the DFU ABORT request.\r\n  * @param  pdev: device instance\r\n  * @retval None\r\n  */\r\nstatic void DFU_Abort(USBD_HandleTypeDef *pdev)\r\n{\r\n USBD_DFU_HandleTypeDef   *hdfu;\r\n \r\n hdfu = (USBD_DFU_HandleTypeDef*) pdev->pClassData;\r\n \r\n  if (hdfu->dev_state == DFU_STATE_IDLE || hdfu->dev_state == DFU_STATE_DNLOAD_SYNC\r\n      || hdfu->dev_state == DFU_STATE_DNLOAD_IDLE || hdfu->dev_state == DFU_STATE_MANIFEST_SYNC\r\n        || hdfu->dev_state == DFU_STATE_UPLOAD_IDLE )\r\n  {\r\n    hdfu->dev_state = DFU_STATE_IDLE;\r\n    hdfu->dev_status[0] = DFU_ERROR_NONE;\r\n    hdfu->dev_status[1] = 0;\r\n    hdfu->dev_status[2] = 0;\r\n    hdfu->dev_status[3] = 0; /*bwPollTimeout=0ms*/\r\n    hdfu->dev_status[4] = hdfu->dev_state;\r\n    hdfu->dev_status[5] = 0; /*iString*/\r\n    hdfu->wblock_num = 0;\r\n    hdfu->wlength = 0;\r\n  }  \r\n}\r\n\r\n/**\r\n  * @brief  DFU_Leave\r\n  *         Handles the sub-protocol DFU leave DFU mode request (leaves DFU mode\r\n  *         and resets device to jump to user loaded code).\r\n  * @param  pdev: device instance\r\n  * @retval None\r\n  */\r\nvoid DFU_Leave(USBD_HandleTypeDef *pdev)\r\n{\r\n USBD_DFU_HandleTypeDef   *hdfu;\r\n \r\n hdfu = (USBD_DFU_HandleTypeDef*) pdev->pClassData;\r\n \r\n hdfu->manif_state = DFU_MANIFEST_COMPLETE;\r\n\r\n  if ((USBD_DFU_CfgDesc[(11 + (9 * USBD_DFU_MAX_ITF_NUM))]) & 0x04)\r\n  {\r\n    hdfu->dev_state = DFU_STATE_MANIFEST_SYNC;\r\n\r\n    hdfu->dev_status[1] = 0;\r\n    hdfu->dev_status[2] = 0;\r\n    hdfu->dev_status[3] = 0;\r\n    hdfu->dev_status[4] = hdfu->dev_state;       \r\n    return;\r\n  }\r\n  else\r\n  {\r\n    \r\n    hdfu->dev_state = DFU_STATE_MANIFEST_WAIT_RESET;\r\n    \r\n    hdfu->dev_status[1] = 0;\r\n    hdfu->dev_status[2] = 0;\r\n    hdfu->dev_status[3] = 0;\r\n    hdfu->dev_status[4] = hdfu->dev_state;     \r\n    \r\n    /* Disconnect the USB device */\r\n    USBD_Stop (pdev);\r\n\r\n    /* DeInitilialize the MAL(Media Access Layer) */\r\n    ((USBD_DFU_MediaTypeDef *)pdev->pUserData)->DeInit();\r\n    \r\n    /* Generate system reset to allow jumping to the user code */\r\n    NVIC_SystemReset();\r\n   \r\n    /* This instruction will not be reached (system reset) */\r\n    for(;;);\r\n  }  \r\n}\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu_media_template.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_dfu_media_template.c\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   Memory management layer\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_dfu_media_template.h\"\r\n\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Extern function prototypes ------------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\nuint16_t MEM_If_Init(void);\r\nuint16_t MEM_If_Erase (uint32_t Add);\r\nuint16_t MEM_If_Write (uint8_t *src, uint8_t *dest, uint32_t Len);\r\nuint8_t *MEM_If_Read  (uint8_t *src, uint8_t *dest, uint32_t Len);\r\nuint16_t MEM_If_DeInit(void);\r\nuint16_t MEM_If_GetStatus (uint32_t Add, uint8_t Cmd, uint8_t *buffer);\r\n\r\nUSBD_DFU_MediaTypeDef USBD_DFU_MEDIA_Template_fops =\r\n{\r\n    (uint8_t *)\"DFU MEDIA\",\r\n    MEM_If_Init,\r\n    MEM_If_DeInit,\r\n    MEM_If_Erase,\r\n    MEM_If_Write,\r\n    MEM_If_Read,\r\n    MEM_If_GetStatus,\r\n  \r\n};\r\n/**\r\n  * @brief  MEM_If_Init\r\n  *         Memory initialization routine.\r\n  * @param  None\r\n  * @retval 0 if operation is successful, MAL_FAIL else.\r\n  */\r\nuint16_t MEM_If_Init(void)\r\n{ \r\n  return 0;\r\n}\r\n\r\n/**\r\n  * @brief  MEM_If_DeInit\r\n  *         Memory deinitialization routine.\r\n  * @param  None\r\n  * @retval 0 if operation is successful, MAL_FAIL else.\r\n  */\r\nuint16_t MEM_If_DeInit(void)\r\n{ \r\n  return 0;\r\n}\r\n\r\n/**\r\n  * @brief  MEM_If_Erase\r\n  *         Erase sector.\r\n  * @param  Add: Address of sector to be erased.\r\n  * @retval 0 if operation is successful, MAL_FAIL else.\r\n  */\r\nuint16_t MEM_If_Erase(uint32_t Add)\r\n{\r\n  return 0;\r\n}\r\n\r\n/**\r\n  * @brief  MEM_If_Write\r\n  *         Memory write routine.\r\n  * @param  Add: Address to be written to.\r\n  * @param  Len: Number of data to be written (in bytes).\r\n  * @retval 0 if operation is successful, MAL_FAIL else.\r\n  */\r\nuint16_t MEM_If_Write(uint8_t *src, uint8_t *dest, uint32_t Len)\r\n{\r\n  return 0;\r\n}\r\n\r\n/**\r\n  * @brief  MEM_If_Read\r\n  *         Memory read routine.\r\n  * @param  Add: Address to be read from.\r\n  * @param  Len: Number of data to be read (in bytes).\r\n  * @retval Pointer to the physical address where data should be read.\r\n  */\r\nuint8_t *MEM_If_Read (uint8_t *src, uint8_t *dest, uint32_t Len)\r\n{\r\n  /* Return a valid address to avoid HardFault */\r\n  return  (uint8_t*)(0); \r\n}\r\n\r\n/**\r\n  * @brief  Flash_If_GetStatus\r\n  *         Memory read routine.\r\n  * @param  Add: Address to be read from.\r\n  * @param  cmd: Number of data to be read (in bytes).\r\n  * @retval Pointer to the physical address where data should be read.\r\n  */\r\nuint16_t MEM_If_GetStatus (uint32_t Add, uint8_t Cmd, uint8_t *buffer)\r\n{\r\n  switch (Cmd)\r\n  {\r\n  case DFU_MEDIA_PROGRAM:\r\n\r\n    break;\r\n    \r\n  case DFU_MEDIA_ERASE:\r\n  default:\r\n\r\n    break;\r\n  }                             \r\n  return  (0); \r\n}\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_hid.h\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   Header file for the usbd_hid_core.c file.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __USB_HID_H\r\n#define __USB_HID_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include  \"usbd_ioreq.h\"\r\n\r\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup USBD_HID\r\n  * @brief This file is the Header file for usbd_hid.c\r\n  * @{\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_HID_Exported_Defines\r\n  * @{\r\n  */ \r\n#define HID_EPIN_ADDR                 0x81\r\n#define HID_EPIN_SIZE                 0x04\r\n\r\n#define USB_HID_CONFIG_DESC_SIZ       34\r\n#define USB_HID_DESC_SIZ              9\r\n#define HID_MOUSE_REPORT_DESC_SIZE    74\r\n\r\n#define HID_DESCRIPTOR_TYPE           0x21\r\n#define HID_REPORT_DESC               0x22\r\n\r\n#define HID_HS_BINTERVAL               0x07\r\n#define HID_FS_BINTERVAL               0x0A\r\n#define HID_POLLING_INTERVAL           0x0A\r\n\r\n#define HID_REQ_SET_PROTOCOL          0x0B\r\n#define HID_REQ_GET_PROTOCOL          0x03\r\n\r\n#define HID_REQ_SET_IDLE              0x0A\r\n#define HID_REQ_GET_IDLE              0x02\r\n\r\n#define HID_REQ_SET_REPORT            0x09\r\n#define HID_REQ_GET_REPORT            0x01\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_CORE_Exported_TypesDefinitions\r\n  * @{\r\n  */\r\ntypedef enum\r\n{\r\n  HID_IDLE = 0,\r\n  HID_BUSY,\r\n}\r\nHID_StateTypeDef; \r\n\r\n\r\ntypedef struct\r\n{\r\n  uint32_t             Protocol;   \r\n  uint32_t             IdleState;  \r\n  uint32_t             AltSetting;\r\n  HID_StateTypeDef     state;  \r\n}\r\nUSBD_HID_HandleTypeDef; \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n\r\n/** @defgroup USBD_CORE_Exported_Macros\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_CORE_Exported_Variables\r\n  * @{\r\n  */ \r\n\r\nextern USBD_ClassTypeDef  USBD_HID;\r\n#define USBD_HID_CLASS    &USBD_HID\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USB_CORE_Exported_Functions\r\n  * @{\r\n  */ \r\nuint8_t USBD_HID_SendReport (USBD_HandleTypeDef *pdev, \r\n                                 uint8_t *report,\r\n                                 uint16_t len);\r\n\r\nuint32_t USBD_HID_GetPollingInterval (USBD_HandleTypeDef *pdev);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif  /* __USB_HID_H */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_hid.c\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   This file provides the HID core functions.\r\n  *\r\n  * @verbatim\r\n  *      \r\n  *          ===================================================================      \r\n  *                                HID Class  Description\r\n  *          =================================================================== \r\n  *           This module manages the HID class V1.11 following the \"Device Class Definition\r\n  *           for Human Interface Devices (HID) Version 1.11 Jun 27, 2001\".\r\n  *           This driver implements the following aspects of the specification:\r\n  *             - The Boot Interface Subclass\r\n  *             - The Mouse protocol\r\n  *             - Usage Page : Generic Desktop\r\n  *             - Usage : Joystick\r\n  *             - Collection : Application \r\n  *      \r\n  * @note     In HS mode and when the DMA is used, all variables and data structures\r\n  *           dealing with the DMA during the transaction process should be 32-bit aligned.\r\n  *           \r\n  *      \r\n  *  @endverbatim\r\n  *\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_hid.h\"\r\n#include \"usbd_desc.h\"\r\n#include \"usbd_ctlreq.h\"\r\n\r\n\r\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n\r\n\r\n/** @defgroup USBD_HID \r\n  * @brief usbd core module\r\n  * @{\r\n  */ \r\n\r\n/** @defgroup USBD_HID_Private_TypesDefinitions\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_HID_Private_Defines\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_HID_Private_Macros\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n\r\n\r\n/** @defgroup USBD_HID_Private_FunctionPrototypes\r\n  * @{\r\n  */\r\n\r\n\r\nstatic uint8_t  USBD_HID_Init (USBD_HandleTypeDef *pdev, \r\n                               uint8_t cfgidx);\r\n\r\nstatic uint8_t  USBD_HID_DeInit (USBD_HandleTypeDef *pdev, \r\n                                 uint8_t cfgidx);\r\n\r\nstatic uint8_t  USBD_HID_Setup (USBD_HandleTypeDef *pdev, \r\n                                USBD_SetupReqTypedef *req);\r\n\r\nstatic uint8_t  *USBD_HID_GetCfgDesc (uint16_t *length);\r\n\r\nstatic uint8_t  *USBD_HID_GetDeviceQualifierDesc (uint16_t *length);\r\n\r\nstatic uint8_t  USBD_HID_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_HID_Private_Variables\r\n  * @{\r\n  */ \r\n\r\nUSBD_ClassTypeDef  USBD_HID = \r\n{\r\n  USBD_HID_Init,\r\n  USBD_HID_DeInit,\r\n  USBD_HID_Setup,\r\n  NULL, /*EP0_TxSent*/  \r\n  NULL, /*EP0_RxReady*/\r\n  USBD_HID_DataIn, /*DataIn*/\r\n  NULL, /*DataOut*/\r\n  NULL, /*SOF */\r\n  NULL,\r\n  NULL,      \r\n  USBD_HID_GetCfgDesc,\r\n  USBD_HID_GetCfgDesc, \r\n  USBD_HID_GetCfgDesc,\r\n  USBD_HID_GetDeviceQualifierDesc,\r\n};\r\n\r\n/* USB HID device Configuration Descriptor */\r\n__ALIGN_BEGIN static uint8_t USBD_HID_CfgDesc[USB_HID_CONFIG_DESC_SIZ]  __ALIGN_END =\r\n{\r\n  0x09, /* bLength: Configuration Descriptor size */\r\n  USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */\r\n  USB_HID_CONFIG_DESC_SIZ,\r\n  /* wTotalLength: Bytes returned */\r\n  0x00,\r\n  0x01,         /*bNumInterfaces: 1 interface*/\r\n  0x01,         /*bConfigurationValue: Configuration value*/\r\n  0x00,         /*iConfiguration: Index of string descriptor describing\r\n  the configuration*/\r\n  0xE0,         /*bmAttributes: bus powered and Support Remote Wake-up */\r\n  0x32,         /*MaxPower 100 mA: this current is used for detecting Vbus*/\r\n  \r\n  /************** Descriptor of Joystick Mouse interface ****************/\r\n  /* 09 */\r\n  0x09,         /*bLength: Interface Descriptor size*/\r\n  USB_DESC_TYPE_INTERFACE,/*bDescriptorType: Interface descriptor type*/\r\n  0x00,         /*bInterfaceNumber: Number of Interface*/\r\n  0x00,         /*bAlternateSetting: Alternate setting*/\r\n  0x01,         /*bNumEndpoints*/\r\n  0x03,         /*bInterfaceClass: HID*/\r\n  0x01,         /*bInterfaceSubClass : 1=BOOT, 0=no boot*/\r\n  0x02,         /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/\r\n  0,            /*iInterface: Index of string descriptor*/\r\n  /******************** Descriptor of Joystick Mouse HID ********************/\r\n  /* 18 */\r\n  0x09,         /*bLength: HID Descriptor size*/\r\n  HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/\r\n  0x11,         /*bcdHID: HID Class Spec release number*/\r\n  0x01,\r\n  0x00,         /*bCountryCode: Hardware target country*/\r\n  0x01,         /*bNumDescriptors: Number of HID class descriptors to follow*/\r\n  0x22,         /*bDescriptorType*/\r\n  HID_MOUSE_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/\r\n  0x00,\r\n  /******************** Descriptor of Mouse endpoint ********************/\r\n  /* 27 */\r\n  0x07,          /*bLength: Endpoint Descriptor size*/\r\n  USB_DESC_TYPE_ENDPOINT, /*bDescriptorType:*/\r\n  \r\n  HID_EPIN_ADDR,     /*bEndpointAddress: Endpoint Address (IN)*/\r\n  0x03,          /*bmAttributes: Interrupt endpoint*/\r\n  HID_EPIN_SIZE, /*wMaxPacketSize: 4 Byte max */\r\n  0x00,\r\n  HID_FS_BINTERVAL,          /*bInterval: Polling Interval (10 ms)*/\r\n  /* 34 */\r\n} ;\r\n\r\n/* USB HID device Configuration Descriptor */\r\n__ALIGN_BEGIN static uint8_t USBD_HID_Desc[USB_HID_DESC_SIZ]  __ALIGN_END  =\r\n{\r\n  /* 18 */\r\n  0x09,         /*bLength: HID Descriptor size*/\r\n  HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/\r\n  0x11,         /*bcdHID: HID Class Spec release number*/\r\n  0x01,\r\n  0x00,         /*bCountryCode: Hardware target country*/\r\n  0x01,         /*bNumDescriptors: Number of HID class descriptors to follow*/\r\n  0x22,         /*bDescriptorType*/\r\n  HID_MOUSE_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/\r\n  0x00,\r\n};\r\n\r\n/* USB Standard Device Descriptor */\r\n__ALIGN_BEGIN static uint8_t USBD_HID_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC]  __ALIGN_END =\r\n{\r\n  USB_LEN_DEV_QUALIFIER_DESC,\r\n  USB_DESC_TYPE_DEVICE_QUALIFIER,\r\n  0x00,\r\n  0x02,\r\n  0x00,\r\n  0x00,\r\n  0x00,\r\n  0x40,\r\n  0x01,\r\n  0x00,\r\n};\r\n\r\n__ALIGN_BEGIN static uint8_t HID_MOUSE_ReportDesc[HID_MOUSE_REPORT_DESC_SIZE]  __ALIGN_END =\r\n{\r\n  0x05,   0x01,\r\n  0x09,   0x02,\r\n  0xA1,   0x01,\r\n  0x09,   0x01,\r\n  \r\n  0xA1,   0x00,\r\n  0x05,   0x09,\r\n  0x19,   0x01,\r\n  0x29,   0x03,\r\n  \r\n  0x15,   0x00,\r\n  0x25,   0x01,\r\n  0x95,   0x03,\r\n  0x75,   0x01,\r\n  \r\n  0x81,   0x02,\r\n  0x95,   0x01,\r\n  0x75,   0x05,\r\n  0x81,   0x01,\r\n  \r\n  0x05,   0x01,\r\n  0x09,   0x30,\r\n  0x09,   0x31,\r\n  0x09,   0x38,\r\n  \r\n  0x15,   0x81,\r\n  0x25,   0x7F,\r\n  0x75,   0x08,\r\n  0x95,   0x03,\r\n  \r\n  0x81,   0x06,\r\n  0xC0,   0x09,\r\n  0x3c,   0x05,\r\n  0xff,   0x09,\r\n  \r\n  0x01,   0x15,\r\n  0x00,   0x25,\r\n  0x01,   0x75,\r\n  0x01,   0x95,\r\n  \r\n  0x02,   0xb1,\r\n  0x22,   0x75,\r\n  0x06,   0x95,\r\n  0x01,   0xb1,\r\n  \r\n  0x01,   0xc0\r\n}; \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_HID_Private_Functions\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @brief  USBD_HID_Init\r\n  *         Initialize the HID interface\r\n  * @param  pdev: device instance\r\n  * @param  cfgidx: Configuration index\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_HID_Init (USBD_HandleTypeDef *pdev, \r\n                               uint8_t cfgidx)\r\n{\r\n  uint8_t ret = 0;\r\n  \r\n  /* Open EP IN */\r\n  USBD_LL_OpenEP(pdev,\r\n                 HID_EPIN_ADDR,\r\n                 USBD_EP_TYPE_INTR,\r\n                 HID_EPIN_SIZE);  \r\n  \r\n  pdev->pClassData = USBD_malloc(sizeof (USBD_HID_HandleTypeDef));\r\n  \r\n  if(pdev->pClassData == NULL)\r\n  {\r\n    ret = 1; \r\n  }\r\n  else\r\n  {\r\n    ((USBD_HID_HandleTypeDef *)pdev->pClassData)->state = HID_IDLE;\r\n  }\r\n  return ret;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_HID_Init\r\n  *         DeInitialize the HID layer\r\n  * @param  pdev: device instance\r\n  * @param  cfgidx: Configuration index\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_HID_DeInit (USBD_HandleTypeDef *pdev, \r\n                                 uint8_t cfgidx)\r\n{\r\n  /* Close HID EPs */\r\n  USBD_LL_CloseEP(pdev,\r\n                  HID_EPIN_ADDR);\r\n  \r\n  /* FRee allocated memory */\r\n  if(pdev->pClassData != NULL)\r\n  {\r\n    USBD_free(pdev->pClassData);\r\n    pdev->pClassData = NULL;\r\n  } \r\n  \r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_HID_Setup\r\n  *         Handle the HID specific requests\r\n  * @param  pdev: instance\r\n  * @param  req: usb requests\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_HID_Setup (USBD_HandleTypeDef *pdev, \r\n                                USBD_SetupReqTypedef *req)\r\n{\r\n  uint16_t len = 0;\r\n  uint8_t  *pbuf = NULL;\r\n  USBD_HID_HandleTypeDef     *hhid = (USBD_HID_HandleTypeDef*) pdev->pClassData;\r\n  \r\n  switch (req->bmRequest & USB_REQ_TYPE_MASK)\r\n  {\r\n  case USB_REQ_TYPE_CLASS :  \r\n    switch (req->bRequest)\r\n    {\r\n      \r\n      \r\n    case HID_REQ_SET_PROTOCOL:\r\n      hhid->Protocol = (uint8_t)(req->wValue);\r\n      break;\r\n      \r\n    case HID_REQ_GET_PROTOCOL:\r\n      USBD_CtlSendData (pdev, \r\n                        (uint8_t *)&hhid->Protocol,\r\n                        1);    \r\n      break;\r\n      \r\n    case HID_REQ_SET_IDLE:\r\n      hhid->IdleState = (uint8_t)(req->wValue >> 8);\r\n      break;\r\n      \r\n    case HID_REQ_GET_IDLE:\r\n      USBD_CtlSendData (pdev, \r\n                        (uint8_t *)&hhid->IdleState,\r\n                        1);        \r\n      break;      \r\n      \r\n    default:\r\n      USBD_CtlError (pdev, req);\r\n      return USBD_FAIL; \r\n    }\r\n    break;\r\n    \r\n  case USB_REQ_TYPE_STANDARD:\r\n    switch (req->bRequest)\r\n    {\r\n    case USB_REQ_GET_DESCRIPTOR: \r\n      if( req->wValue >> 8 == HID_REPORT_DESC)\r\n      {\r\n        len = MIN(HID_MOUSE_REPORT_DESC_SIZE , req->wLength);\r\n        pbuf = HID_MOUSE_ReportDesc;\r\n      }\r\n      else if( req->wValue >> 8 == HID_DESCRIPTOR_TYPE)\r\n      {\r\n        pbuf = USBD_HID_Desc;   \r\n        len = MIN(USB_HID_DESC_SIZ , req->wLength);\r\n      }\r\n      \r\n      USBD_CtlSendData (pdev, \r\n                        pbuf,\r\n                        len);\r\n      \r\n      break;\r\n      \r\n    case USB_REQ_GET_INTERFACE :\r\n      USBD_CtlSendData (pdev,\r\n                        (uint8_t *)&hhid->AltSetting,\r\n                        1);\r\n      break;\r\n      \r\n    case USB_REQ_SET_INTERFACE :\r\n      hhid->AltSetting = (uint8_t)(req->wValue);\r\n      break;\r\n    }\r\n  }\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_HID_SendReport \r\n  *         Send HID Report\r\n  * @param  pdev: device instance\r\n  * @param  buff: pointer to report\r\n  * @retval status\r\n  */\r\nuint8_t USBD_HID_SendReport     (USBD_HandleTypeDef  *pdev, \r\n                                 uint8_t *report,\r\n                                 uint16_t len)\r\n{\r\n  USBD_HID_HandleTypeDef     *hhid = (USBD_HID_HandleTypeDef*)pdev->pClassData;\r\n  \r\n  if (pdev->dev_state == USBD_STATE_CONFIGURED )\r\n  {\r\n    if(hhid->state == HID_IDLE)\r\n    {\r\n      hhid->state = HID_BUSY;\r\n      USBD_LL_Transmit (pdev, \r\n                        HID_EPIN_ADDR,                                      \r\n                        report,\r\n                        len);\r\n    }\r\n  }\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_HID_GetPollingInterval \r\n  *         return polling interval from endpoint descriptor\r\n  * @param  pdev: device instance\r\n  * @retval polling interval\r\n  */\r\nuint32_t USBD_HID_GetPollingInterval (USBD_HandleTypeDef *pdev)\r\n{\r\n  uint32_t polling_interval = 0;\r\n\r\n  /* HIGH-speed endpoints */\r\n  if(pdev->dev_speed == USBD_SPEED_HIGH)\r\n  {\r\n   /* Sets the data transfer polling interval for high speed transfers. \r\n    Values between 1..16 are allowed. Values correspond to interval \r\n    of 2 ^ (bInterval-1). This option (8 ms, corresponds to HID_HS_BINTERVAL */\r\n    polling_interval = (((1 <<(HID_HS_BINTERVAL - 1)))/8);\r\n  }\r\n  else   /* LOW and FULL-speed endpoints */\r\n  {\r\n    /* Sets the data transfer polling interval for low and full \r\n    speed transfers */\r\n    polling_interval =  HID_FS_BINTERVAL;\r\n  }\r\n  \r\n  return ((uint32_t)(polling_interval));\r\n}\r\n\r\n/**\r\n  * @brief  USBD_HID_GetCfgDesc \r\n  *         return configuration descriptor\r\n  * @param  speed : current device speed\r\n  * @param  length : pointer data length\r\n  * @retval pointer to descriptor buffer\r\n  */\r\nstatic uint8_t  *USBD_HID_GetCfgDesc (uint16_t *length)\r\n{\r\n  *length = sizeof (USBD_HID_CfgDesc);\r\n  return USBD_HID_CfgDesc;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  USBD_HID_DataIn\r\n  *         handle data IN Stage\r\n  * @param  pdev: device instance\r\n  * @param  epnum: endpoint index\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_HID_DataIn (USBD_HandleTypeDef *pdev, \r\n                              uint8_t epnum)\r\n{\r\n  \r\n  /* Ensure that the FIFO is empty before a new transfer, this condition could \r\n  be caused by  a new transfer before the end of the previous transfer */\r\n  ((USBD_HID_HandleTypeDef *)pdev->pClassData)->state = HID_IDLE;\r\n  return USBD_OK;\r\n}\r\n\r\n\r\n/**\r\n* @brief  DeviceQualifierDescriptor \r\n*         return Device Qualifier descriptor\r\n* @param  length : pointer data length\r\n* @retval pointer to descriptor buffer\r\n*/\r\nstatic uint8_t  *USBD_HID_GetDeviceQualifierDesc (uint16_t *length)\r\n{\r\n  *length = sizeof (USBD_HID_DeviceQualifierDesc);\r\n  return USBD_HID_DeviceQualifierDesc;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_msc.h\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   Header for the usbd_msc.c file\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __USBD_MSC_H\r\n#define __USBD_MSC_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include  \"usbd_msc_bot.h\"\r\n#include  \"usbd_msc_scsi.h\"\r\n#include  \"usbd_ioreq.h\"\r\n\r\n/** @addtogroup USBD_MSC_BOT\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup USBD_MSC\r\n  * @brief This file is the Header file for usbd_msc.c\r\n  * @{\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_BOT_Exported_Defines\r\n  * @{\r\n  */ \r\n#define MSC_MAX_FS_PACKET            0x40\r\n#define MSC_MAX_HS_PACKET            0x200\r\n\r\n#define BOT_GET_MAX_LUN              0xFE\r\n#define BOT_RESET                    0xFF\r\n#define USB_MSC_CONFIG_DESC_SIZ      32\r\n \r\n\r\n#define MSC_EPIN_ADDR                0x81 \r\n#define MSC_EPOUT_ADDR               0x01 \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USB_CORE_Exported_Types\r\n  * @{\r\n  */ \r\ntypedef struct _USBD_STORAGE\r\n{\r\n  int8_t (* Init) (uint8_t lun);\r\n  int8_t (* GetCapacity) (uint8_t lun, uint32_t *block_num, uint16_t *block_size);\r\n  int8_t (* IsReady) (uint8_t lun);\r\n  int8_t (* IsWriteProtected) (uint8_t lun);\r\n  int8_t (* Read) (uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len);\r\n  int8_t (* Write)(uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len);\r\n  int8_t (* GetMaxLun)(void);\r\n  int8_t *pInquiry;\r\n  \r\n}USBD_StorageTypeDef;\r\n\r\n\r\ntypedef struct\r\n{\r\n  uint32_t                 max_lun;   \r\n  uint32_t                 interface; \r\n  uint8_t                  bot_state;\r\n  uint8_t                  bot_status;  \r\n  uint16_t                 bot_data_length;\r\n  uint8_t                  bot_data[MSC_MEDIA_PACKET];  \r\n  USBD_MSC_BOT_CBWTypeDef  cbw;\r\n  USBD_MSC_BOT_CSWTypeDef  csw;\r\n  \r\n  USBD_SCSI_SenseTypeDef   scsi_sense [SENSE_LIST_DEEPTH];\r\n  uint8_t                  scsi_sense_head;\r\n  uint8_t                  scsi_sense_tail;\r\n  \r\n  uint16_t                 scsi_blk_size;\r\n  uint32_t                 scsi_blk_nbr;\r\n  \r\n  uint32_t                 scsi_blk_addr;\r\n  uint32_t                 scsi_blk_len;\r\n}\r\nUSBD_MSC_BOT_HandleTypeDef; \r\n\r\n/* Structure for MSC process */\r\nextern USBD_ClassTypeDef  USBD_MSC;\r\n#define USBD_MSC_CLASS    &USBD_MSC\r\n\r\nuint8_t  USBD_MSC_RegisterStorage  (USBD_HandleTypeDef   *pdev, \r\n                                    USBD_StorageTypeDef *fops);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif  /* __USBD_MSC_H */\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_bot.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_msc_bot.h\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   Header for the usbd_msc_bot.c file\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __USBD_MSC_BOT_H\r\n#define __USBD_MSC_BOT_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_core.h\"\r\n\r\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup MSC_BOT\r\n  * @brief This file is the Header file for usbd_msc_bot.c\r\n  * @{\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_CORE_Exported_Defines\r\n  * @{\r\n  */ \r\n#define USBD_BOT_IDLE                      0       /* Idle state */\r\n#define USBD_BOT_DATA_OUT                  1       /* Data Out state */\r\n#define USBD_BOT_DATA_IN                   2       /* Data In state */\r\n#define USBD_BOT_LAST_DATA_IN              3       /* Last Data In Last */\r\n#define USBD_BOT_SEND_DATA                 4       /* Send Immediate data */\r\n#define USBD_BOT_NO_DATA                   5       /* No data Stage */\r\n\r\n#define USBD_BOT_CBW_SIGNATURE             0x43425355\r\n#define USBD_BOT_CSW_SIGNATURE             0x53425355\r\n#define USBD_BOT_CBW_LENGTH                31\r\n#define USBD_BOT_CSW_LENGTH                13\r\n#define USBD_BOT_MAX_DATA                  256\r\n\r\n/* CSW Status Definitions */\r\n#define USBD_CSW_CMD_PASSED                0x00\r\n#define USBD_CSW_CMD_FAILED                0x01\r\n#define USBD_CSW_PHASE_ERROR               0x02\r\n\r\n/* BOT Status */\r\n#define USBD_BOT_STATUS_NORMAL             0\r\n#define USBD_BOT_STATUS_RECOVERY           1\r\n#define USBD_BOT_STATUS_ERROR              2\r\n\r\n\r\n#define USBD_DIR_IN                        0\r\n#define USBD_DIR_OUT                       1\r\n#define USBD_BOTH_DIR                      2\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup MSC_CORE_Private_TypesDefinitions\r\n  * @{\r\n  */ \r\n\r\ntypedef struct\r\n{\r\n  uint32_t dSignature;\r\n  uint32_t dTag;\r\n  uint32_t dDataLength;\r\n  uint8_t  bmFlags;\r\n  uint8_t  bLUN;\r\n  uint8_t  bCBLength;\r\n  uint8_t  CB[16];\r\n  uint8_t  ReservedForAlign;\r\n}\r\nUSBD_MSC_BOT_CBWTypeDef;\r\n\r\n\r\ntypedef struct\r\n{\r\n  uint32_t dSignature;\r\n  uint32_t dTag;\r\n  uint32_t dDataResidue;\r\n  uint8_t  bStatus;\r\n  uint8_t  ReservedForAlign[3];  \r\n}\r\nUSBD_MSC_BOT_CSWTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_CORE_Exported_Types\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n/** @defgroup USBD_CORE_Exported_FunctionsPrototypes\r\n  * @{\r\n  */ \r\nvoid MSC_BOT_Init (USBD_HandleTypeDef  *pdev);\r\nvoid MSC_BOT_Reset (USBD_HandleTypeDef  *pdev);\r\nvoid MSC_BOT_DeInit (USBD_HandleTypeDef  *pdev);\r\nvoid MSC_BOT_DataIn (USBD_HandleTypeDef  *pdev, \r\n                     uint8_t epnum);\r\n\r\nvoid MSC_BOT_DataOut (USBD_HandleTypeDef  *pdev, \r\n                      uint8_t epnum);\r\n\r\nvoid MSC_BOT_SendCSW (USBD_HandleTypeDef  *pdev,\r\n                             uint8_t CSW_Status);\r\n\r\nvoid  MSC_BOT_CplClrFeature (USBD_HandleTypeDef  *pdev, \r\n                             uint8_t epnum);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __USBD_MSC_BOT_H */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n* @}\r\n*/ \r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_data.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_msc_data.h\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   Header for the usbd_msc_data.c file\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __USBD_MSC_DATA_H\r\n#define __USBD_MSC_DATA_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_conf.h\"\r\n\r\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup USB_INFO\r\n  * @brief general defines for the usb device library file\r\n  * @{\r\n  */ \r\n\r\n/** @defgroup USB_INFO_Exported_Defines\r\n  * @{\r\n  */ \r\n#define MODE_SENSE6_LEN\t\t\t 8\r\n#define MODE_SENSE10_LEN\t\t 8\r\n#define LENGTH_INQUIRY_PAGE00\t\t 7\r\n#define LENGTH_FORMAT_CAPACITIES    \t20\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_INFO_Exported_TypesDefinitions\r\n  * @{\r\n  */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n\r\n/** @defgroup USBD_INFO_Exported_Macros\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_INFO_Exported_Variables\r\n  * @{\r\n  */ \r\nextern const uint8_t MSC_Page00_Inquiry_Data[];  \r\nextern const uint8_t MSC_Mode_Sense6_data[];\r\nextern const uint8_t MSC_Mode_Sense10_data[] ;\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_INFO_Exported_FunctionsPrototype\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __USBD_MSC_DATA_H */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n* @}\r\n*/ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_scsi.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_msc_scsi.h\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   Header for the usbd_msc_scsi.c file\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __USBD_MSC_SCSI_H\r\n#define __USBD_MSC_SCSI_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_def.h\"\r\n\r\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup USBD_SCSI\r\n  * @brief header file for the storage disk file\r\n  * @{\r\n  */ \r\n\r\n/** @defgroup USBD_SCSI_Exported_Defines\r\n  * @{\r\n  */ \r\n\r\n#define SENSE_LIST_DEEPTH                           4\r\n\r\n/* SCSI Commands */\r\n#define SCSI_FORMAT_UNIT                            0x04\r\n#define SCSI_INQUIRY                                0x12\r\n#define SCSI_MODE_SELECT6                           0x15\r\n#define SCSI_MODE_SELECT10                          0x55\r\n#define SCSI_MODE_SENSE6                            0x1A\r\n#define SCSI_MODE_SENSE10                           0x5A\r\n#define SCSI_ALLOW_MEDIUM_REMOVAL                   0x1E\r\n#define SCSI_READ6                                  0x08\r\n#define SCSI_READ10                                 0x28\r\n#define SCSI_READ12                                 0xA8\r\n#define SCSI_READ16                                 0x88\r\n\r\n#define SCSI_READ_CAPACITY10                        0x25\r\n#define SCSI_READ_CAPACITY16                        0x9E\r\n\r\n#define SCSI_REQUEST_SENSE                          0x03\r\n#define SCSI_START_STOP_UNIT                        0x1B\r\n#define SCSI_TEST_UNIT_READY                        0x00\r\n#define SCSI_WRITE6                                 0x0A\r\n#define SCSI_WRITE10                                0x2A\r\n#define SCSI_WRITE12                                0xAA\r\n#define SCSI_WRITE16                                0x8A\r\n\r\n#define SCSI_VERIFY10                               0x2F\r\n#define SCSI_VERIFY12                               0xAF\r\n#define SCSI_VERIFY16                               0x8F\r\n\r\n#define SCSI_SEND_DIAGNOSTIC                        0x1D\r\n#define SCSI_READ_FORMAT_CAPACITIES                 0x23\r\n\r\n#define NO_SENSE                                    0\r\n#define RECOVERED_ERROR                             1\r\n#define NOT_READY                                   2\r\n#define MEDIUM_ERROR                                3\r\n#define HARDWARE_ERROR                              4\r\n#define ILLEGAL_REQUEST                             5\r\n#define UNIT_ATTENTION                              6\r\n#define DATA_PROTECT                                7\r\n#define BLANK_CHECK                                 8\r\n#define VENDOR_SPECIFIC                             9\r\n#define COPY_ABORTED                                10\r\n#define ABORTED_COMMAND                             11\r\n#define VOLUME_OVERFLOW                             13\r\n#define MISCOMPARE                                  14\r\n\r\n\r\n#define INVALID_CDB                                 0x20\r\n#define INVALID_FIELED_IN_COMMAND                   0x24\r\n#define PARAMETER_LIST_LENGTH_ERROR                 0x1A\r\n#define INVALID_FIELD_IN_PARAMETER_LIST             0x26\r\n#define ADDRESS_OUT_OF_RANGE                        0x21\r\n#define MEDIUM_NOT_PRESENT                          0x3A\r\n#define MEDIUM_HAVE_CHANGED                         0x28\r\n#define WRITE_PROTECTED                             0x27 \r\n#define UNRECOVERED_READ_ERROR\t\t\t    0x11\r\n#define WRITE_FAULT\t\t\t\t    0x03 \r\n\r\n#define READ_FORMAT_CAPACITY_DATA_LEN               0x0C\r\n#define READ_CAPACITY10_DATA_LEN                    0x08\r\n#define MODE_SENSE10_DATA_LEN                       0x08\r\n#define MODE_SENSE6_DATA_LEN                        0x04\r\n#define REQUEST_SENSE_DATA_LEN                      0x12\r\n#define STANDARD_INQUIRY_DATA_LEN                   0x24\r\n#define BLKVFY                                      0x04\r\n\r\nextern  uint8_t Page00_Inquiry_Data[];\r\nextern  uint8_t Standard_Inquiry_Data[];\r\nextern  uint8_t Standard_Inquiry_Data2[];\r\nextern  uint8_t Mode_Sense6_data[];\r\nextern  uint8_t Mode_Sense10_data[];\r\nextern  uint8_t Scsi_Sense_Data[];\r\nextern  uint8_t ReadCapacity10_Data[];\r\nextern  uint8_t ReadFormatCapacity_Data [];\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_SCSI_Exported_TypesDefinitions\r\n  * @{\r\n  */\r\n\r\ntypedef struct _SENSE_ITEM {                \r\n  char Skey;\r\n  union {\r\n    struct _ASCs {\r\n      char ASC;\r\n      char ASCQ;\r\n    }b;\r\n    unsigned int\tASC;\r\n    char *pData;\r\n  } w;\r\n} USBD_SCSI_SenseTypeDef; \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_SCSI_Exported_Macros\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_SCSI_Exported_Variables\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n/** @defgroup USBD_SCSI_Exported_FunctionsPrototype\r\n  * @{\r\n  */ \r\nint8_t SCSI_ProcessCmd(USBD_HandleTypeDef  *pdev,\r\n                           uint8_t lun, \r\n                           uint8_t *cmd);\r\n\r\nvoid   SCSI_SenseCode(USBD_HandleTypeDef  *pdev,\r\n                      uint8_t lun, \r\n                      uint8_t sKey, \r\n                      uint8_t ASC);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __USBD_MSC_SCSI_H */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n* @}\r\n*/ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_storage_template.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_msc_storage.h\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   Header file for the usbd_msc_storage.c file\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __USBD_MSC_STORAGE_H\r\n#define __USBD_MSC_STORAGE_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_msc.h\"\r\n\r\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup USBD_STORAGE\r\n  * @brief header file for the usbd_msc_storage.c file\r\n  * @{\r\n  */ \r\n\r\n/** @defgroup USBD_STORAGE_Exported_Defines\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_STORAGE_Exported_Types\r\n  * @{\r\n  */\r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n\r\n/** @defgroup USBD_STORAGE_Exported_Macros\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_STORAGE_Exported_Variables\r\n  * @{\r\n  */ \r\nextern USBD_StorageTypeDef  USBD_MSC_Template_fops;\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_STORAGE_Exported_FunctionsPrototype\r\n  * @{\r\n  */ \r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __USBD_MSC_STORAGE_H */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n* @}\r\n*/ \r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_msc.c\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   This file provides all the MSC core functions.\r\n  *\r\n  * @verbatim\r\n  *      \r\n  *          ===================================================================      \r\n  *                                MSC Class  Description\r\n  *          =================================================================== \r\n  *           This module manages the MSC class V1.0 following the \"Universal \r\n  *           Serial Bus Mass Storage Class (MSC) Bulk-Only Transport (BOT) Version 1.0\r\n  *           Sep. 31, 1999\".\r\n  *           This driver implements the following aspects of the specification:\r\n  *             - Bulk-Only Transport protocol\r\n  *             - Subclass : SCSI transparent command set (ref. SCSI Primary Commands - 3 (SPC-3))\r\n  *      \r\n  *  @endverbatim\r\n  *\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_msc.h\"\r\n\r\n\r\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n\r\n\r\n/** @defgroup MSC_CORE \r\n  * @brief Mass storage core module\r\n  * @{\r\n  */ \r\n\r\n/** @defgroup MSC_CORE_Private_TypesDefinitions\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup MSC_CORE_Private_Defines\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup MSC_CORE_Private_Macros\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup MSC_CORE_Private_FunctionPrototypes\r\n  * @{\r\n  */ \r\nuint8_t  USBD_MSC_Init (USBD_HandleTypeDef *pdev, \r\n                            uint8_t cfgidx);\r\n\r\nuint8_t  USBD_MSC_DeInit (USBD_HandleTypeDef *pdev, \r\n                              uint8_t cfgidx);\r\n\r\nuint8_t  USBD_MSC_Setup (USBD_HandleTypeDef *pdev, \r\n                             USBD_SetupReqTypedef *req);\r\n\r\nuint8_t  USBD_MSC_DataIn (USBD_HandleTypeDef *pdev, \r\n                              uint8_t epnum);\r\n\r\n\r\nuint8_t  USBD_MSC_DataOut (USBD_HandleTypeDef *pdev, \r\n                               uint8_t epnum);\r\n\r\nuint8_t  *USBD_MSC_GetHSCfgDesc (uint16_t *length);\r\n\r\nuint8_t  *USBD_MSC_GetFSCfgDesc (uint16_t *length);\r\n\r\nuint8_t  *USBD_MSC_GetOtherSpeedCfgDesc (uint16_t *length);\r\n\r\nuint8_t  *USBD_MSC_GetDeviceQualifierDescriptor (uint16_t *length);\r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup MSC_CORE_Private_Variables\r\n  * @{\r\n  */ \r\n\r\n\r\nUSBD_ClassTypeDef  USBD_MSC = \r\n{\r\n  USBD_MSC_Init,\r\n  USBD_MSC_DeInit,\r\n  USBD_MSC_Setup,\r\n  NULL, /*EP0_TxSent*/  \r\n  NULL, /*EP0_RxReady*/\r\n  USBD_MSC_DataIn,\r\n  USBD_MSC_DataOut,\r\n  NULL, /*SOF */ \r\n  NULL,  \r\n  NULL,     \r\n  USBD_MSC_GetHSCfgDesc,\r\n  USBD_MSC_GetFSCfgDesc,  \r\n  USBD_MSC_GetOtherSpeedCfgDesc,\r\n  USBD_MSC_GetDeviceQualifierDescriptor,\r\n};\r\n\r\n/* USB Mass storage device Configuration Descriptor */\r\n/*   All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */\r\n__ALIGN_BEGIN uint8_t USBD_MSC_CfgHSDesc[USB_MSC_CONFIG_DESC_SIZ]  __ALIGN_END =\r\n{\r\n  \r\n  0x09,   /* bLength: Configuation Descriptor size */\r\n  USB_DESC_TYPE_CONFIGURATION,   /* bDescriptorType: Configuration */\r\n  USB_MSC_CONFIG_DESC_SIZ,\r\n  \r\n  0x00,\r\n  0x01,   /* bNumInterfaces: 1 interface */\r\n  0x01,   /* bConfigurationValue: */\r\n  0x04,   /* iConfiguration: */\r\n  0xC0,   /* bmAttributes: */\r\n  0x32,   /* MaxPower 100 mA */\r\n  \r\n  /********************  Mass Storage interface ********************/\r\n  0x09,   /* bLength: Interface Descriptor size */\r\n  0x04,   /* bDescriptorType: */\r\n  0x00,   /* bInterfaceNumber: Number of Interface */\r\n  0x00,   /* bAlternateSetting: Alternate setting */\r\n  0x02,   /* bNumEndpoints*/\r\n  0x08,   /* bInterfaceClass: MSC Class */\r\n  0x06,   /* bInterfaceSubClass : SCSI transparent*/\r\n  0x50,   /* nInterfaceProtocol */\r\n  0x05,          /* iInterface: */\r\n  /********************  Mass Storage Endpoints ********************/\r\n  0x07,   /*Endpoint descriptor length = 7*/\r\n  0x05,   /*Endpoint descriptor type */\r\n  MSC_EPIN_ADDR,   /*Endpoint address (IN, address 1) */\r\n  0x02,   /*Bulk endpoint type */\r\n  LOBYTE(MSC_MAX_HS_PACKET),\r\n  HIBYTE(MSC_MAX_HS_PACKET),\r\n  0x00,   /*Polling interval in milliseconds */\r\n  \r\n  0x07,   /*Endpoint descriptor length = 7 */\r\n  0x05,   /*Endpoint descriptor type */\r\n  MSC_EPOUT_ADDR,   /*Endpoint address (OUT, address 1) */\r\n  0x02,   /*Bulk endpoint type */\r\n  LOBYTE(MSC_MAX_HS_PACKET),\r\n  HIBYTE(MSC_MAX_HS_PACKET),\r\n  0x00     /*Polling interval in milliseconds*/\r\n};\r\n\r\n/* USB Mass storage device Configuration Descriptor */\r\n/*   All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */\r\nuint8_t USBD_MSC_CfgFSDesc[USB_MSC_CONFIG_DESC_SIZ]  __ALIGN_END =\r\n{\r\n  \r\n  0x09,   /* bLength: Configuation Descriptor size */\r\n  USB_DESC_TYPE_CONFIGURATION,   /* bDescriptorType: Configuration */\r\n  USB_MSC_CONFIG_DESC_SIZ,\r\n  \r\n  0x00,\r\n  0x01,   /* bNumInterfaces: 1 interface */\r\n  0x01,   /* bConfigurationValue: */\r\n  0x04,   /* iConfiguration: */\r\n  0xC0,   /* bmAttributes: */\r\n  0x32,   /* MaxPower 100 mA */\r\n  \r\n  /********************  Mass Storage interface ********************/\r\n  0x09,   /* bLength: Interface Descriptor size */\r\n  0x04,   /* bDescriptorType: */\r\n  0x00,   /* bInterfaceNumber: Number of Interface */\r\n  0x00,   /* bAlternateSetting: Alternate setting */\r\n  0x02,   /* bNumEndpoints*/\r\n  0x08,   /* bInterfaceClass: MSC Class */\r\n  0x06,   /* bInterfaceSubClass : SCSI transparent*/\r\n  0x50,   /* nInterfaceProtocol */\r\n  0x05,          /* iInterface: */\r\n  /********************  Mass Storage Endpoints ********************/\r\n  0x07,   /*Endpoint descriptor length = 7*/\r\n  0x05,   /*Endpoint descriptor type */\r\n  MSC_EPIN_ADDR,   /*Endpoint address (IN, address 1) */\r\n  0x02,   /*Bulk endpoint type */\r\n  LOBYTE(MSC_MAX_FS_PACKET),\r\n  HIBYTE(MSC_MAX_FS_PACKET),\r\n  0x00,   /*Polling interval in milliseconds */\r\n  \r\n  0x07,   /*Endpoint descriptor length = 7 */\r\n  0x05,   /*Endpoint descriptor type */\r\n  MSC_EPOUT_ADDR,   /*Endpoint address (OUT, address 1) */\r\n  0x02,   /*Bulk endpoint type */\r\n  LOBYTE(MSC_MAX_FS_PACKET),\r\n  HIBYTE(MSC_MAX_FS_PACKET),\r\n  0x00     /*Polling interval in milliseconds*/\r\n};\r\n\r\n__ALIGN_BEGIN uint8_t USBD_MSC_OtherSpeedCfgDesc[USB_MSC_CONFIG_DESC_SIZ]   __ALIGN_END  =\r\n{\r\n  \r\n  0x09,   /* bLength: Configuation Descriptor size */\r\n  USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION,   \r\n  USB_MSC_CONFIG_DESC_SIZ,\r\n  \r\n  0x00,\r\n  0x01,   /* bNumInterfaces: 1 interface */\r\n  0x01,   /* bConfigurationValue: */\r\n  0x04,   /* iConfiguration: */\r\n  0xC0,   /* bmAttributes: */\r\n  0x32,   /* MaxPower 100 mA */\r\n  \r\n  /********************  Mass Storage interface ********************/\r\n  0x09,   /* bLength: Interface Descriptor size */\r\n  0x04,   /* bDescriptorType: */\r\n  0x00,   /* bInterfaceNumber: Number of Interface */\r\n  0x00,   /* bAlternateSetting: Alternate setting */\r\n  0x02,   /* bNumEndpoints*/\r\n  0x08,   /* bInterfaceClass: MSC Class */\r\n  0x06,   /* bInterfaceSubClass : SCSI transparent command set*/\r\n  0x50,   /* nInterfaceProtocol */\r\n  0x05,          /* iInterface: */\r\n  /********************  Mass Storage Endpoints ********************/\r\n  0x07,   /*Endpoint descriptor length = 7*/\r\n  0x05,   /*Endpoint descriptor type */\r\n  MSC_EPIN_ADDR,   /*Endpoint address (IN, address 1) */\r\n  0x02,   /*Bulk endpoint type */\r\n  0x40,\r\n  0x00,\r\n  0x00,   /*Polling interval in milliseconds */\r\n  \r\n  0x07,   /*Endpoint descriptor length = 7 */\r\n  0x05,   /*Endpoint descriptor type */\r\n  MSC_EPOUT_ADDR,   /*Endpoint address (OUT, address 1) */\r\n  0x02,   /*Bulk endpoint type */\r\n  0x40,\r\n  0x00,\r\n  0x00     /*Polling interval in milliseconds*/\r\n};\r\n\r\n/* USB Standard Device Descriptor */\r\n__ALIGN_BEGIN  uint8_t USBD_MSC_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC]  __ALIGN_END =\r\n{\r\n  USB_LEN_DEV_QUALIFIER_DESC,\r\n  USB_DESC_TYPE_DEVICE_QUALIFIER,\r\n  0x00,\r\n  0x02,\r\n  0x00,\r\n  0x00,\r\n  0x00,\r\n  MSC_MAX_FS_PACKET,\r\n  0x01,\r\n  0x00,\r\n};\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup MSC_CORE_Private_Functions\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @brief  USBD_MSC_Init\r\n  *         Initialize  the mass storage configuration\r\n  * @param  pdev: device instance\r\n  * @param  cfgidx: configuration index\r\n  * @retval status\r\n  */\r\nuint8_t  USBD_MSC_Init (USBD_HandleTypeDef *pdev, \r\n                            uint8_t cfgidx)\r\n{\r\n  int16_t ret = 0;\r\n   \r\n  if(pdev->dev_speed == USBD_SPEED_HIGH  ) \r\n  {\r\n    /* Open EP OUT */\r\n    USBD_LL_OpenEP(pdev,\r\n                   MSC_EPOUT_ADDR,\r\n                   USBD_EP_TYPE_BULK,\r\n                   MSC_MAX_HS_PACKET);\r\n    \r\n    /* Open EP IN */\r\n    USBD_LL_OpenEP(pdev,\r\n                   MSC_EPIN_ADDR,\r\n                   USBD_EP_TYPE_BULK,\r\n                   MSC_MAX_HS_PACKET);  \r\n  }\r\n  else\r\n  {\r\n    /* Open EP OUT */\r\n    USBD_LL_OpenEP(pdev,\r\n                   MSC_EPOUT_ADDR,\r\n                   USBD_EP_TYPE_BULK,\r\n                   MSC_MAX_FS_PACKET);\r\n    \r\n    /* Open EP IN */\r\n    USBD_LL_OpenEP(pdev,\r\n                   MSC_EPIN_ADDR,\r\n                   USBD_EP_TYPE_BULK,\r\n                   MSC_MAX_FS_PACKET);  \r\n  }\r\n  pdev->pClassData = USBD_malloc(sizeof (USBD_MSC_BOT_HandleTypeDef));\r\n  \r\n  if(pdev->pClassData == NULL)\r\n  {\r\n    ret = 1; \r\n  }\r\n  else\r\n  {\r\n    /* Init the BOT  layer */\r\n    MSC_BOT_Init(pdev); \r\n    ret = 0;\r\n  }\r\n  \r\n  return ret;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_MSC_DeInit\r\n  *         DeInitilaize  the mass storage configuration\r\n  * @param  pdev: device instance\r\n  * @param  cfgidx: configuration index\r\n  * @retval status\r\n  */\r\nuint8_t  USBD_MSC_DeInit (USBD_HandleTypeDef *pdev, \r\n                              uint8_t cfgidx)\r\n{\r\n  /* Close MSC EPs */\r\n  USBD_LL_CloseEP(pdev,\r\n                  MSC_EPOUT_ADDR);\r\n  \r\n  /* Open EP IN */\r\n  USBD_LL_CloseEP(pdev,\r\n                  MSC_EPIN_ADDR);\r\n  \r\n  \r\n    /* De-Init the BOT layer */\r\n  MSC_BOT_DeInit(pdev);\r\n  \r\n  /* Free MSC Class Resources */\r\n  if(pdev->pClassData != NULL)\r\n  {\r\n    USBD_free(pdev->pClassData);\r\n    pdev->pClassData  = NULL; \r\n  }\r\n  return 0;\r\n}\r\n/**\r\n* @brief  USBD_MSC_Setup\r\n*         Handle the MSC specific requests\r\n* @param  pdev: device instance\r\n* @param  req: USB request\r\n* @retval status\r\n*/\r\nuint8_t  USBD_MSC_Setup (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)\r\n{\r\n  USBD_MSC_BOT_HandleTypeDef     *hmsc = (USBD_MSC_BOT_HandleTypeDef*) pdev->pClassData;\r\n  \r\n  switch (req->bmRequest & USB_REQ_TYPE_MASK)\r\n  {\r\n\r\n  /* Class request */\r\n  case USB_REQ_TYPE_CLASS :\r\n    switch (req->bRequest)\r\n    {\r\n    case BOT_GET_MAX_LUN :\r\n\r\n      if((req->wValue  == 0) && \r\n         (req->wLength == 1) &&\r\n         ((req->bmRequest & 0x80) == 0x80))\r\n      {\r\n        hmsc->max_lun = ((USBD_StorageTypeDef *)pdev->pUserData)->GetMaxLun();\r\n        USBD_CtlSendData (pdev,\r\n                          (uint8_t *)&hmsc->max_lun,\r\n                          1);\r\n      }\r\n      else\r\n      {\r\n         USBD_CtlError(pdev , req);\r\n         return USBD_FAIL; \r\n      }\r\n      break;\r\n      \r\n    case BOT_RESET :\r\n      if((req->wValue  == 0) && \r\n         (req->wLength == 0) &&\r\n        ((req->bmRequest & 0x80) != 0x80))\r\n      {      \r\n         MSC_BOT_Reset(pdev);\r\n      }\r\n      else\r\n      {\r\n         USBD_CtlError(pdev , req);\r\n         return USBD_FAIL; \r\n      }\r\n      break;\r\n\r\n    default:\r\n       USBD_CtlError(pdev , req);\r\n       return USBD_FAIL; \r\n    }\r\n    break;\r\n  /* Interface & Endpoint request */\r\n  case USB_REQ_TYPE_STANDARD:\r\n    switch (req->bRequest)\r\n    {\r\n    case USB_REQ_GET_INTERFACE :\r\n      USBD_CtlSendData (pdev,\r\n                        (uint8_t *)&hmsc->interface,\r\n                        1);\r\n      break;\r\n      \r\n    case USB_REQ_SET_INTERFACE :\r\n      hmsc->interface = (uint8_t)(req->wValue);\r\n      break;\r\n    \r\n    case USB_REQ_CLEAR_FEATURE:  \r\n      \r\n      /* Flush the FIFO and Clear the stall status */    \r\n      USBD_LL_FlushEP(pdev, (uint8_t)req->wIndex);\r\n      \r\n      /* Reactivate the EP */      \r\n      USBD_LL_CloseEP (pdev , (uint8_t)req->wIndex);\r\n      if((((uint8_t)req->wIndex) & 0x80) == 0x80)\r\n      {\r\n        if(pdev->dev_speed == USBD_SPEED_HIGH  ) \r\n        {\r\n          /* Open EP IN */\r\n          USBD_LL_OpenEP(pdev,\r\n                         MSC_EPIN_ADDR,\r\n                         USBD_EP_TYPE_BULK,\r\n                         MSC_MAX_HS_PACKET);  \r\n        }\r\n        else\r\n        {   \r\n          /* Open EP IN */\r\n          USBD_LL_OpenEP(pdev,\r\n                         MSC_EPIN_ADDR,\r\n                         USBD_EP_TYPE_BULK,\r\n                         MSC_MAX_FS_PACKET);  \r\n        }\r\n      }\r\n      else\r\n      {\r\n        if(pdev->dev_speed == USBD_SPEED_HIGH  ) \r\n        {\r\n          /* Open EP IN */\r\n          USBD_LL_OpenEP(pdev,\r\n                         MSC_EPOUT_ADDR,\r\n                         USBD_EP_TYPE_BULK,\r\n                         MSC_MAX_HS_PACKET);  \r\n        }\r\n        else\r\n        {   \r\n          /* Open EP IN */\r\n          USBD_LL_OpenEP(pdev,\r\n                         MSC_EPOUT_ADDR,\r\n                         USBD_EP_TYPE_BULK,\r\n                         MSC_MAX_FS_PACKET);  \r\n        }\r\n      }\r\n      \r\n      /* Handle BOT error */\r\n      MSC_BOT_CplClrFeature(pdev, (uint8_t)req->wIndex);\r\n      break;\r\n      \r\n    }  \r\n    break;\r\n   \r\n  default:\r\n    break;\r\n  }\r\n  return 0;\r\n}\r\n\r\n/**\r\n* @brief  USBD_MSC_DataIn\r\n*         handle data IN Stage\r\n* @param  pdev: device instance\r\n* @param  epnum: endpoint index\r\n* @retval status\r\n*/\r\nuint8_t  USBD_MSC_DataIn (USBD_HandleTypeDef *pdev, \r\n                              uint8_t epnum)\r\n{\r\n  MSC_BOT_DataIn(pdev , epnum);\r\n  return 0;\r\n}\r\n\r\n/**\r\n* @brief  USBD_MSC_DataOut\r\n*         handle data OUT Stage\r\n* @param  pdev: device instance\r\n* @param  epnum: endpoint index\r\n* @retval status\r\n*/\r\nuint8_t  USBD_MSC_DataOut (USBD_HandleTypeDef *pdev, \r\n                               uint8_t epnum)\r\n{\r\n  MSC_BOT_DataOut(pdev , epnum);\r\n  return 0;\r\n}\r\n\r\n/**\r\n* @brief  USBD_MSC_GetHSCfgDesc \r\n*         return configuration descriptor\r\n* @param  length : pointer data length\r\n* @retval pointer to descriptor buffer\r\n*/\r\nuint8_t  *USBD_MSC_GetHSCfgDesc (uint16_t *length)\r\n{\r\n  *length = sizeof (USBD_MSC_CfgHSDesc);\r\n  return USBD_MSC_CfgHSDesc;\r\n}\r\n\r\n/**\r\n* @brief  USBD_MSC_GetFSCfgDesc \r\n*         return configuration descriptor\r\n* @param  length : pointer data length\r\n* @retval pointer to descriptor buffer\r\n*/\r\nuint8_t  *USBD_MSC_GetFSCfgDesc (uint16_t *length)\r\n{\r\n  *length = sizeof (USBD_MSC_CfgFSDesc);\r\n  return USBD_MSC_CfgFSDesc;\r\n}\r\n\r\n/**\r\n* @brief  USBD_MSC_GetOtherSpeedCfgDesc \r\n*         return other speed configuration descriptor\r\n* @param  length : pointer data length\r\n* @retval pointer to descriptor buffer\r\n*/\r\nuint8_t  *USBD_MSC_GetOtherSpeedCfgDesc (uint16_t *length)\r\n{\r\n  *length = sizeof (USBD_MSC_OtherSpeedCfgDesc);\r\n  return USBD_MSC_OtherSpeedCfgDesc;\r\n}\r\n/**\r\n* @brief  DeviceQualifierDescriptor \r\n*         return Device Qualifier descriptor\r\n* @param  length : pointer data length\r\n* @retval pointer to descriptor buffer\r\n*/\r\nuint8_t  *USBD_MSC_GetDeviceQualifierDescriptor (uint16_t *length)\r\n{\r\n  *length = sizeof (USBD_MSC_DeviceQualifierDesc);\r\n  return USBD_MSC_DeviceQualifierDesc;\r\n}\r\n\r\n/**\r\n* @brief  USBD_MSC_RegisterStorage\r\n* @param  fops: storage callback\r\n* @retval status\r\n*/\r\nuint8_t  USBD_MSC_RegisterStorage  (USBD_HandleTypeDef   *pdev, \r\n                                    USBD_StorageTypeDef *fops)\r\n{\r\n  if(fops != NULL)\r\n  {\r\n    pdev->pUserData= fops;\r\n  }\r\n  return 0;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_bot.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_msc_bot.c\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   This file provides all the BOT protocol core functions.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_msc_bot.h\"\r\n#include \"usbd_msc.h\"\r\n#include \"usbd_msc_scsi.h\"\r\n#include \"usbd_ioreq.h\"\r\n\r\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n\r\n\r\n/** @defgroup MSC_BOT \r\n  * @brief BOT protocol module\r\n  * @{\r\n  */ \r\n\r\n/** @defgroup MSC_BOT_Private_TypesDefinitions\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup MSC_BOT_Private_Defines\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup MSC_BOT_Private_Macros\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup MSC_BOT_Private_Variables\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup MSC_BOT_Private_FunctionPrototypes\r\n  * @{\r\n  */ \r\nstatic void MSC_BOT_CBW_Decode (USBD_HandleTypeDef  *pdev);\r\n\r\nstatic void MSC_BOT_SendData (USBD_HandleTypeDef  *pdev, \r\n                              uint8_t* pbuf, \r\n                              uint16_t len);\r\n\r\nstatic void MSC_BOT_Abort(USBD_HandleTypeDef  *pdev);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup MSC_BOT_Private_Functions\r\n  * @{\r\n  */ \r\n\r\n\r\n\r\n/**\r\n* @brief  MSC_BOT_Init\r\n*         Initialize the BOT Process\r\n* @param  pdev: device instance\r\n* @retval None\r\n*/\r\nvoid MSC_BOT_Init (USBD_HandleTypeDef  *pdev)\r\n{\r\n  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData;\r\n    \r\n  hmsc->bot_state  = USBD_BOT_IDLE;\r\n  hmsc->bot_status = USBD_BOT_STATUS_NORMAL;\r\n  \r\n  hmsc->scsi_sense_tail = 0;\r\n  hmsc->scsi_sense_head = 0;\r\n  \r\n  ((USBD_StorageTypeDef *)pdev->pUserData)->Init(0);\r\n  \r\n  USBD_LL_FlushEP(pdev, MSC_EPOUT_ADDR);\r\n  USBD_LL_FlushEP(pdev, MSC_EPIN_ADDR);\r\n  \r\n  /* Prapare EP to Receive First BOT Cmd */\r\n  USBD_LL_PrepareReceive (pdev,\r\n                          MSC_EPOUT_ADDR,\r\n                          (uint8_t *)&hmsc->cbw,\r\n                          USBD_BOT_CBW_LENGTH);    \r\n}\r\n\r\n/**\r\n* @brief  MSC_BOT_Reset\r\n*         Reset the BOT Machine\r\n* @param  pdev: device instance\r\n* @retval  None\r\n*/\r\nvoid MSC_BOT_Reset (USBD_HandleTypeDef  *pdev)\r\n{\r\n  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData;\r\n    \r\n  hmsc->bot_state  = USBD_BOT_IDLE;\r\n  hmsc->bot_status = USBD_BOT_STATUS_RECOVERY;  \r\n  \r\n  /* Prapare EP to Receive First BOT Cmd */\r\n  USBD_LL_PrepareReceive (pdev,\r\n                          MSC_EPOUT_ADDR,\r\n                          (uint8_t *)&hmsc->cbw,\r\n                          USBD_BOT_CBW_LENGTH);   \r\n}\r\n\r\n/**\r\n* @brief  MSC_BOT_DeInit\r\n*         Deinitialize the BOT Machine\r\n* @param  pdev: device instance\r\n* @retval None\r\n*/\r\nvoid MSC_BOT_DeInit (USBD_HandleTypeDef  *pdev)\r\n{\r\n  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData;  \r\n  hmsc->bot_state  = USBD_BOT_IDLE;\r\n}\r\n\r\n/**\r\n* @brief  MSC_BOT_DataIn\r\n*         Handle BOT IN data stage\r\n* @param  pdev: device instance\r\n* @param  epnum: endpoint index\r\n* @retval None\r\n*/\r\nvoid MSC_BOT_DataIn (USBD_HandleTypeDef  *pdev, \r\n                     uint8_t epnum)\r\n{\r\n  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData;  \r\n  \r\n  switch (hmsc->bot_state)\r\n  {\r\n  case USBD_BOT_DATA_IN:\r\n    if(SCSI_ProcessCmd(pdev,\r\n                        hmsc->cbw.bLUN,\r\n                        &hmsc->cbw.CB[0]) < 0)\r\n    {\r\n      MSC_BOT_SendCSW (pdev, USBD_CSW_CMD_FAILED);\r\n    }\r\n    break;\r\n    \r\n  case USBD_BOT_SEND_DATA:\r\n  case USBD_BOT_LAST_DATA_IN:\r\n    MSC_BOT_SendCSW (pdev, USBD_CSW_CMD_PASSED);\r\n    \r\n    break;\r\n    \r\n  default:\r\n    break;\r\n  }\r\n}\r\n/**\r\n* @brief  MSC_BOT_DataOut\r\n*         Process MSC OUT data\r\n* @param  pdev: device instance\r\n* @param  epnum: endpoint index\r\n* @retval None\r\n*/\r\nvoid MSC_BOT_DataOut (USBD_HandleTypeDef  *pdev, \r\n                      uint8_t epnum)\r\n{\r\n  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData;\r\n  \r\n  switch (hmsc->bot_state)\r\n  {\r\n  case USBD_BOT_IDLE:\r\n    MSC_BOT_CBW_Decode(pdev);\r\n    break;\r\n    \r\n  case USBD_BOT_DATA_OUT:\r\n    \r\n    if(SCSI_ProcessCmd(pdev,\r\n                        hmsc->cbw.bLUN,\r\n                        &hmsc->cbw.CB[0]) < 0)\r\n    {\r\n      MSC_BOT_SendCSW (pdev, USBD_CSW_CMD_FAILED);\r\n    }\r\n\r\n    break;\r\n    \r\n  default:\r\n    break;\r\n  }\r\n}\r\n\r\n/**\r\n* @brief  MSC_BOT_CBW_Decode\r\n*         Decode the CBW command and set the BOT state machine accordingly  \r\n* @param  pdev: device instance\r\n* @retval None\r\n*/\r\nstatic void  MSC_BOT_CBW_Decode (USBD_HandleTypeDef  *pdev)\r\n{\r\n  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData;  \r\n  \r\n  hmsc->csw.dTag = hmsc->cbw.dTag;\r\n  hmsc->csw.dDataResidue = hmsc->cbw.dDataLength;\r\n  \r\n  if ((USBD_LL_GetRxDataSize (pdev ,MSC_EPOUT_ADDR) != USBD_BOT_CBW_LENGTH) ||\r\n      (hmsc->cbw.dSignature != USBD_BOT_CBW_SIGNATURE)||\r\n        (hmsc->cbw.bLUN > 1) || \r\n          (hmsc->cbw.bCBLength < 1) || \r\n            (hmsc->cbw.bCBLength > 16))\r\n  {\r\n    \r\n    SCSI_SenseCode(pdev,\r\n                   hmsc->cbw.bLUN, \r\n                   ILLEGAL_REQUEST, \r\n                   INVALID_CDB);\r\n    \r\n    hmsc->bot_status = USBD_BOT_STATUS_ERROR;   \r\n    MSC_BOT_Abort(pdev);\r\n \r\n  }\r\n  else\r\n  {\r\n    if(SCSI_ProcessCmd(pdev,\r\n                       hmsc->cbw.bLUN,\r\n                       &hmsc->cbw.CB[0]) < 0)\r\n    {\r\n      if(hmsc->bot_state == USBD_BOT_NO_DATA)\r\n      {\r\n       MSC_BOT_SendCSW (pdev,\r\n                         USBD_CSW_CMD_FAILED); \r\n      }\r\n      else\r\n      {\r\n        MSC_BOT_Abort(pdev);\r\n      }\r\n    }\r\n    /*Burst xfer handled internally*/\r\n    else if ((hmsc->bot_state != USBD_BOT_DATA_IN) && \r\n             (hmsc->bot_state != USBD_BOT_DATA_OUT) &&\r\n             (hmsc->bot_state != USBD_BOT_LAST_DATA_IN)) \r\n    {\r\n      if (hmsc->bot_data_length > 0)\r\n      {\r\n        MSC_BOT_SendData(pdev,\r\n                         hmsc->bot_data, \r\n                         hmsc->bot_data_length);\r\n      }\r\n      else if (hmsc->bot_data_length == 0) \r\n      {\r\n        MSC_BOT_SendCSW (pdev,\r\n                         USBD_CSW_CMD_PASSED);\r\n      }\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n* @brief  MSC_BOT_SendData\r\n*         Send the requested data\r\n* @param  pdev: device instance\r\n* @param  buf: pointer to data buffer\r\n* @param  len: Data Length\r\n* @retval None\r\n*/\r\nstatic void  MSC_BOT_SendData(USBD_HandleTypeDef  *pdev,\r\n                              uint8_t* buf, \r\n                              uint16_t len)\r\n{\r\n  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData; \r\n  \r\n  len = MIN (hmsc->cbw.dDataLength, len);\r\n  hmsc->csw.dDataResidue -= len;\r\n  hmsc->csw.bStatus = USBD_CSW_CMD_PASSED;\r\n  hmsc->bot_state = USBD_BOT_SEND_DATA;\r\n  \r\n  USBD_LL_Transmit (pdev, MSC_EPIN_ADDR, buf, len);  \r\n}\r\n\r\n/**\r\n* @brief  MSC_BOT_SendCSW\r\n*         Send the Command Status Wrapper\r\n* @param  pdev: device instance\r\n* @param  status : CSW status\r\n* @retval None\r\n*/\r\nvoid  MSC_BOT_SendCSW (USBD_HandleTypeDef  *pdev,\r\n                              uint8_t CSW_Status)\r\n{\r\n  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData; \r\n  \r\n  hmsc->csw.dSignature = USBD_BOT_CSW_SIGNATURE;\r\n  hmsc->csw.bStatus = CSW_Status;\r\n  hmsc->bot_state = USBD_BOT_IDLE;\r\n  \r\n  USBD_LL_Transmit (pdev, \r\n             MSC_EPIN_ADDR, \r\n             (uint8_t *)&hmsc->csw, \r\n             USBD_BOT_CSW_LENGTH);\r\n  \r\n  /* Prepare EP to Receive next Cmd */\r\n  USBD_LL_PrepareReceive (pdev,\r\n                    MSC_EPOUT_ADDR,\r\n                    (uint8_t *)&hmsc->cbw, \r\n                    USBD_BOT_CBW_LENGTH);  \r\n  \r\n}\r\n\r\n/**\r\n* @brief  MSC_BOT_Abort\r\n*         Abort the current transfer\r\n* @param  pdev: device instance\r\n* @retval status\r\n*/\r\n\r\nstatic void  MSC_BOT_Abort (USBD_HandleTypeDef  *pdev)\r\n{\r\n  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData; \r\n  \r\n  if ((hmsc->cbw.bmFlags == 0) && \r\n      (hmsc->cbw.dDataLength != 0) &&\r\n      (hmsc->bot_status == USBD_BOT_STATUS_NORMAL) )\r\n  {\r\n    USBD_LL_StallEP(pdev, MSC_EPOUT_ADDR );\r\n  }\r\n  USBD_LL_StallEP(pdev, MSC_EPIN_ADDR);\r\n  \r\n  if(hmsc->bot_status == USBD_BOT_STATUS_ERROR)\r\n  {\r\n    USBD_LL_PrepareReceive (pdev,\r\n                      MSC_EPOUT_ADDR,\r\n                      (uint8_t *)&hmsc->cbw, \r\n                      USBD_BOT_CBW_LENGTH);    \r\n  }\r\n}\r\n\r\n/**\r\n* @brief  MSC_BOT_CplClrFeature\r\n*         Complete the clear feature request\r\n* @param  pdev: device instance\r\n* @param  epnum: endpoint index\r\n* @retval None\r\n*/\r\n\r\nvoid  MSC_BOT_CplClrFeature (USBD_HandleTypeDef  *pdev, uint8_t epnum)\r\n{\r\n  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData; \r\n  \r\n  if(hmsc->bot_status == USBD_BOT_STATUS_ERROR )/* Bad CBW Signature */\r\n  {\r\n    USBD_LL_StallEP(pdev, MSC_EPIN_ADDR);\r\n    hmsc->bot_status = USBD_BOT_STATUS_NORMAL;    \r\n  }\r\n  else if(((epnum & 0x80) == 0x80) && ( hmsc->bot_status != USBD_BOT_STATUS_RECOVERY))\r\n  {\r\n    MSC_BOT_SendCSW (pdev, USBD_CSW_CMD_FAILED);\r\n  }\r\n  \r\n}\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_data.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_msc_data.c\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   This file provides all the vital inquiry pages and sense data.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_msc_data.h\"\r\n\r\n\r\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n\r\n\r\n/** @defgroup MSC_DATA \r\n  * @brief Mass storage info/data module\r\n  * @{\r\n  */ \r\n\r\n/** @defgroup MSC_DATA_Private_TypesDefinitions\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup MSC_DATA_Private_Defines\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup MSC_DATA_Private_Macros\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup MSC_DATA_Private_Variables\r\n  * @{\r\n  */ \r\n\r\n\r\n/* USB Mass storage Page 0 Inquiry Data */\r\nconst uint8_t  MSC_Page00_Inquiry_Data[] = {//7\t\t\t\t\t\t\r\n\t0x00,\t\t\r\n\t0x00, \r\n\t0x00, \r\n\t(LENGTH_INQUIRY_PAGE00 - 4),\r\n\t0x00, \r\n\t0x80, \r\n\t0x83 \r\n};  \r\n/* USB Mass storage sense 6  Data */\r\nconst uint8_t  MSC_Mode_Sense6_data[] = {\r\n\t0x00,\r\n\t0x00,\r\n\t0x00,\r\n\t0x00,\r\n\t0x00,\r\n\t0x00, \r\n\t0x00,\r\n\t0x00\r\n};\t\r\n/* USB Mass storage sense 10  Data */\r\nconst uint8_t  MSC_Mode_Sense10_data[] = {\r\n\t0x00,\r\n\t0x06, \r\n\t0x00, \r\n\t0x00, \r\n\t0x00, \r\n\t0x00, \r\n\t0x00, \r\n\t0x00\r\n};\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup MSC_DATA_Private_FunctionPrototypes\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup MSC_DATA_Private_Functions\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_scsi.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_msc_scsi.c\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   This file provides all the USBD SCSI layer functions.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_msc_bot.h\"\r\n#include \"usbd_msc_scsi.h\"\r\n#include \"usbd_msc.h\"\r\n#include \"usbd_msc_data.h\"\r\n\r\n\r\n\r\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n\r\n\r\n/** @defgroup MSC_SCSI \r\n  * @brief Mass storage SCSI layer module\r\n  * @{\r\n  */ \r\n\r\n/** @defgroup MSC_SCSI_Private_TypesDefinitions\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup MSC_SCSI_Private_Defines\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup MSC_SCSI_Private_Macros\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup MSC_SCSI_Private_Variables\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup MSC_SCSI_Private_FunctionPrototypes\r\n  * @{\r\n  */ \r\nstatic int8_t SCSI_TestUnitReady(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params);\r\nstatic int8_t SCSI_Inquiry(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params);\r\nstatic int8_t SCSI_ReadFormatCapacity(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params);\r\nstatic int8_t SCSI_ReadCapacity10(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params);\r\nstatic int8_t SCSI_RequestSense (USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params);\r\nstatic int8_t SCSI_StartStopUnit(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params);\r\nstatic int8_t SCSI_ModeSense6 (USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params);\r\nstatic int8_t SCSI_ModeSense10 (USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params);\r\nstatic int8_t SCSI_Write10(USBD_HandleTypeDef  *pdev, uint8_t lun , uint8_t *params);\r\nstatic int8_t SCSI_Read10(USBD_HandleTypeDef  *pdev, uint8_t lun , uint8_t *params);\r\nstatic int8_t SCSI_Verify10(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params);\r\nstatic int8_t SCSI_CheckAddressRange (USBD_HandleTypeDef  *pdev, \r\n                                      uint8_t lun , \r\n                                      uint32_t blk_offset , \r\n                                      uint16_t blk_nbr);\r\nstatic int8_t SCSI_ProcessRead (USBD_HandleTypeDef  *pdev,\r\n                                uint8_t lun);\r\n\r\nstatic int8_t SCSI_ProcessWrite (USBD_HandleTypeDef  *pdev,\r\n                                 uint8_t lun);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup MSC_SCSI_Private_Functions\r\n  * @{\r\n  */ \r\n\r\n\r\n/**\r\n* @brief  SCSI_ProcessCmd\r\n*         Process SCSI commands\r\n* @param  pdev: device instance\r\n* @param  lun: Logical unit number\r\n* @param  params: Command parameters\r\n* @retval status\r\n*/\r\nint8_t SCSI_ProcessCmd(USBD_HandleTypeDef  *pdev,\r\n                           uint8_t lun, \r\n                           uint8_t *params)\r\n{\r\n  \r\n  switch (params[0])\r\n  {\r\n  case SCSI_TEST_UNIT_READY:\r\n    return SCSI_TestUnitReady(pdev, lun, params);\r\n    \r\n  case SCSI_REQUEST_SENSE:\r\n    return SCSI_RequestSense (pdev, lun, params);\r\n  case SCSI_INQUIRY:\r\n    return SCSI_Inquiry(pdev, lun, params);\r\n    \r\n  case SCSI_START_STOP_UNIT:\r\n    return SCSI_StartStopUnit(pdev, lun, params);\r\n    \r\n  case SCSI_ALLOW_MEDIUM_REMOVAL:\r\n    return SCSI_StartStopUnit(pdev, lun, params);\r\n    \r\n  case SCSI_MODE_SENSE6:\r\n    return SCSI_ModeSense6 (pdev, lun, params);\r\n    \r\n  case SCSI_MODE_SENSE10:\r\n    return SCSI_ModeSense10 (pdev, lun, params);\r\n    \r\n  case SCSI_READ_FORMAT_CAPACITIES:\r\n    return SCSI_ReadFormatCapacity(pdev, lun, params);\r\n    \r\n  case SCSI_READ_CAPACITY10:\r\n    return SCSI_ReadCapacity10(pdev, lun, params);\r\n    \r\n  case SCSI_READ10:\r\n    return SCSI_Read10(pdev, lun, params); \r\n    \r\n  case SCSI_WRITE10:\r\n    return SCSI_Write10(pdev, lun, params);\r\n    \r\n  case SCSI_VERIFY10:\r\n    return SCSI_Verify10(pdev, lun, params);\r\n    \r\n  default:\r\n    SCSI_SenseCode(pdev, \r\n                   lun,\r\n                   ILLEGAL_REQUEST, \r\n                   INVALID_CDB);    \r\n    return -1;\r\n  }\r\n}\r\n\r\n\r\n/**\r\n* @brief  SCSI_TestUnitReady\r\n*         Process SCSI Test Unit Ready Command\r\n* @param  lun: Logical unit number\r\n* @param  params: Command parameters\r\n* @retval status\r\n*/\r\nstatic int8_t SCSI_TestUnitReady(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params)\r\n{\r\n  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData;  \r\n    \r\n  /* case 9 : Hi > D0 */\r\n  if (hmsc->cbw.dDataLength != 0)\r\n  {\r\n    SCSI_SenseCode(pdev,\r\n                   hmsc->cbw.bLUN, \r\n                   ILLEGAL_REQUEST, \r\n                   INVALID_CDB);\r\n    return -1;\r\n  }  \r\n  \r\n  if(((USBD_StorageTypeDef *)pdev->pUserData)->IsReady(lun) !=0 )\r\n  {\r\n    SCSI_SenseCode(pdev,\r\n                   lun,\r\n                   NOT_READY, \r\n                   MEDIUM_NOT_PRESENT);\r\n    \r\n    hmsc->bot_state = USBD_BOT_NO_DATA;\r\n    return -1;\r\n  } \r\n  hmsc->bot_data_length = 0;\r\n  return 0;\r\n}\r\n\r\n/**\r\n* @brief  SCSI_Inquiry\r\n*         Process Inquiry command\r\n* @param  lun: Logical unit number\r\n* @param  params: Command parameters\r\n* @retval status\r\n*/\r\nstatic int8_t  SCSI_Inquiry(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params)\r\n{\r\n  uint8_t* pPage;\r\n  uint16_t len;\r\n  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData; \r\n  \r\n  if (params[1] & 0x01)/*Evpd is set*/\r\n  {\r\n    pPage = (uint8_t *)MSC_Page00_Inquiry_Data;\r\n    len = LENGTH_INQUIRY_PAGE00;\r\n  }\r\n  else\r\n  {\r\n    \r\n    pPage = (uint8_t *)&((USBD_StorageTypeDef *)pdev->pUserData)->pInquiry[lun * STANDARD_INQUIRY_DATA_LEN];\r\n    len = pPage[4] + 5;\r\n    \r\n    if (params[4] <= len)\r\n    {\r\n      len = params[4];\r\n    }\r\n  }\r\n  hmsc->bot_data_length = len;\r\n  \r\n  while (len) \r\n  {\r\n    len--;\r\n    hmsc->bot_data[len] = pPage[len];\r\n  }\r\n  return 0;\r\n}\r\n\r\n/**\r\n* @brief  SCSI_ReadCapacity10\r\n*         Process Read Capacity 10 command\r\n* @param  lun: Logical unit number\r\n* @param  params: Command parameters\r\n* @retval status\r\n*/\r\nstatic int8_t SCSI_ReadCapacity10(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params)\r\n{\r\n  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData; \r\n  \r\n  if(((USBD_StorageTypeDef *)pdev->pUserData)->GetCapacity(lun, &hmsc->scsi_blk_nbr, &hmsc->scsi_blk_size) != 0)\r\n  {\r\n    SCSI_SenseCode(pdev,\r\n                   lun,\r\n                   NOT_READY, \r\n                   MEDIUM_NOT_PRESENT);\r\n    return -1;\r\n  } \r\n  else\r\n  {\r\n    \r\n    hmsc->bot_data[0] = (uint8_t)((hmsc->scsi_blk_nbr - 1) >> 24);\r\n    hmsc->bot_data[1] = (uint8_t)((hmsc->scsi_blk_nbr - 1) >> 16);\r\n    hmsc->bot_data[2] = (uint8_t)((hmsc->scsi_blk_nbr - 1) >>  8);\r\n    hmsc->bot_data[3] = (uint8_t)(hmsc->scsi_blk_nbr - 1);\r\n    \r\n    hmsc->bot_data[4] = (uint8_t)(hmsc->scsi_blk_size >>  24);\r\n    hmsc->bot_data[5] = (uint8_t)(hmsc->scsi_blk_size >>  16);\r\n    hmsc->bot_data[6] = (uint8_t)(hmsc->scsi_blk_size >>  8);\r\n    hmsc->bot_data[7] = (uint8_t)(hmsc->scsi_blk_size);\r\n    \r\n    hmsc->bot_data_length = 8;\r\n    return 0;\r\n  }\r\n}\r\n/**\r\n* @brief  SCSI_ReadFormatCapacity\r\n*         Process Read Format Capacity command\r\n* @param  lun: Logical unit number\r\n* @param  params: Command parameters\r\n* @retval status\r\n*/\r\nstatic int8_t SCSI_ReadFormatCapacity(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params)\r\n{\r\n  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData; \r\n  \r\n  uint16_t blk_size;\r\n  uint32_t blk_nbr;\r\n  uint16_t i;\r\n  \r\n  for(i=0 ; i < 12 ; i++) \r\n  {\r\n    hmsc->bot_data[i] = 0;\r\n  }\r\n  \r\n  if(((USBD_StorageTypeDef *)pdev->pUserData)->GetCapacity(lun, &blk_nbr, &blk_size) != 0)\r\n  {\r\n    SCSI_SenseCode(pdev,\r\n                   lun,\r\n                   NOT_READY, \r\n                   MEDIUM_NOT_PRESENT);\r\n    return -1;\r\n  } \r\n  else\r\n  {\r\n    hmsc->bot_data[3] = 0x08;\r\n    hmsc->bot_data[4] = (uint8_t)((blk_nbr - 1) >> 24);\r\n    hmsc->bot_data[5] = (uint8_t)((blk_nbr - 1) >> 16);\r\n    hmsc->bot_data[6] = (uint8_t)((blk_nbr - 1) >>  8);\r\n    hmsc->bot_data[7] = (uint8_t)(blk_nbr - 1);\r\n    \r\n    hmsc->bot_data[8] = 0x02;\r\n    hmsc->bot_data[9] = (uint8_t)(blk_size >>  16);\r\n    hmsc->bot_data[10] = (uint8_t)(blk_size >>  8);\r\n    hmsc->bot_data[11] = (uint8_t)(blk_size);\r\n    \r\n    hmsc->bot_data_length = 12;\r\n    return 0;\r\n  }\r\n}\r\n/**\r\n* @brief  SCSI_ModeSense6\r\n*         Process Mode Sense6 command\r\n* @param  lun: Logical unit number\r\n* @param  params: Command parameters\r\n* @retval status\r\n*/\r\nstatic int8_t SCSI_ModeSense6 (USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params)\r\n{\r\n  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData; \r\n  uint16_t len = 8 ;\r\n  hmsc->bot_data_length = len;\r\n  \r\n  while (len) \r\n  {\r\n    len--;\r\n    hmsc->bot_data[len] = MSC_Mode_Sense6_data[len];\r\n  }\r\n  return 0;\r\n}\r\n\r\n/**\r\n* @brief  SCSI_ModeSense10\r\n*         Process Mode Sense10 command\r\n* @param  lun: Logical unit number\r\n* @param  params: Command parameters\r\n* @retval status\r\n*/\r\nstatic int8_t SCSI_ModeSense10 (USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params)\r\n{\r\n  uint16_t len = 8;\r\n  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData; \r\n  \r\n  hmsc->bot_data_length = len;\r\n\r\n  while (len) \r\n  {\r\n    len--;\r\n    hmsc->bot_data[len] = MSC_Mode_Sense10_data[len];\r\n  }\r\n  return 0;\r\n}\r\n\r\n/**\r\n* @brief  SCSI_RequestSense\r\n*         Process Request Sense command\r\n* @param  lun: Logical unit number\r\n* @param  params: Command parameters\r\n* @retval status\r\n*/\r\n\r\nstatic int8_t SCSI_RequestSense (USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params)\r\n{\r\n  uint8_t i;\r\n  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData; \r\n  \r\n  for(i=0 ; i < REQUEST_SENSE_DATA_LEN ; i++) \r\n  {\r\n    hmsc->bot_data[i] = 0;\r\n  }\r\n  \r\n  hmsc->bot_data[0]\t= 0x70;\t\t\r\n  hmsc->bot_data[7]\t= REQUEST_SENSE_DATA_LEN - 6;\t\r\n  \r\n  if((hmsc->scsi_sense_head != hmsc->scsi_sense_tail)) {\r\n    \r\n    hmsc->bot_data[2]     = hmsc->scsi_sense[hmsc->scsi_sense_head].Skey;\t\t\r\n    hmsc->bot_data[12]    = hmsc->scsi_sense[hmsc->scsi_sense_head].w.b.ASCQ;\t\r\n    hmsc->bot_data[13]    = hmsc->scsi_sense[hmsc->scsi_sense_head].w.b.ASC;\t\r\n    hmsc->scsi_sense_head++;\r\n    \r\n    if (hmsc->scsi_sense_head == SENSE_LIST_DEEPTH)\r\n    {\r\n      hmsc->scsi_sense_head = 0;\r\n    }\r\n  }\r\n  hmsc->bot_data_length = REQUEST_SENSE_DATA_LEN;  \r\n  \r\n  if (params[4] <= REQUEST_SENSE_DATA_LEN)\r\n  {\r\n    hmsc->bot_data_length = params[4];\r\n  }\r\n  return 0;\r\n}\r\n\r\n/**\r\n* @brief  SCSI_SenseCode\r\n*         Load the last error code in the error list\r\n* @param  lun: Logical unit number\r\n* @param  sKey: Sense Key\r\n* @param  ASC: Additional Sense Key\r\n* @retval none\r\n\r\n*/\r\nvoid SCSI_SenseCode(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t sKey, uint8_t ASC)\r\n{\r\n  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData; \r\n  \r\n  hmsc->scsi_sense[hmsc->scsi_sense_tail].Skey  = sKey;\r\n  hmsc->scsi_sense[hmsc->scsi_sense_tail].w.ASC = ASC << 8;\r\n  hmsc->scsi_sense_tail++;\r\n  if (hmsc->scsi_sense_tail == SENSE_LIST_DEEPTH)\r\n  {\r\n    hmsc->scsi_sense_tail = 0;\r\n  }\r\n}\r\n/**\r\n* @brief  SCSI_StartStopUnit\r\n*         Process Start Stop Unit command\r\n* @param  lun: Logical unit number\r\n* @param  params: Command parameters\r\n* @retval status\r\n*/\r\nstatic int8_t SCSI_StartStopUnit(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params)\r\n{\r\n  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*) pdev->pClassData;   \r\n  hmsc->bot_data_length = 0;\r\n  return 0;\r\n}\r\n\r\n/**\r\n* @brief  SCSI_Read10\r\n*         Process Read10 command\r\n* @param  lun: Logical unit number\r\n* @param  params: Command parameters\r\n* @retval status\r\n*/\r\nstatic int8_t SCSI_Read10(USBD_HandleTypeDef  *pdev, uint8_t lun , uint8_t *params)\r\n{\r\n  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*) pdev->pClassData; \r\n  \r\n  if(hmsc->bot_state == USBD_BOT_IDLE)  /* Idle */\r\n  {\r\n    \r\n    /* case 10 : Ho <> Di */\r\n    \r\n    if ((hmsc->cbw.bmFlags & 0x80) != 0x80)\r\n    {\r\n      SCSI_SenseCode(pdev,\r\n                     hmsc->cbw.bLUN, \r\n                     ILLEGAL_REQUEST, \r\n                     INVALID_CDB);\r\n      return -1;\r\n    }    \r\n    \r\n    if(((USBD_StorageTypeDef *)pdev->pUserData)->IsReady(lun) !=0 )\r\n    {\r\n      SCSI_SenseCode(pdev,\r\n                     lun,\r\n                     NOT_READY, \r\n                     MEDIUM_NOT_PRESENT);\r\n      return -1;\r\n    } \r\n    \r\n    hmsc->scsi_blk_addr = (params[2] << 24) | \\\r\n      (params[3] << 16) | \\\r\n        (params[4] <<  8) | \\\r\n          params[5];\r\n    \r\n    hmsc->scsi_blk_len =  (params[7] <<  8) | \\\r\n      params[8];  \r\n    \r\n    \r\n    \r\n    if( SCSI_CheckAddressRange(pdev, lun, hmsc->scsi_blk_addr, hmsc->scsi_blk_len) < 0)\r\n    {\r\n      return -1; /* error */\r\n    }\r\n    \r\n    hmsc->bot_state = USBD_BOT_DATA_IN;\r\n    hmsc->scsi_blk_addr *= hmsc->scsi_blk_size;\r\n    hmsc->scsi_blk_len  *= hmsc->scsi_blk_size;\r\n    \r\n    /* cases 4,5 : Hi <> Dn */\r\n    if (hmsc->cbw.dDataLength != hmsc->scsi_blk_len)\r\n    {\r\n      SCSI_SenseCode(pdev,\r\n                     hmsc->cbw.bLUN, \r\n                     ILLEGAL_REQUEST, \r\n                     INVALID_CDB);\r\n      return -1;\r\n    }\r\n  }\r\n  hmsc->bot_data_length = MSC_MEDIA_PACKET;  \r\n  \r\n  return SCSI_ProcessRead(pdev, lun);\r\n}\r\n\r\n/**\r\n* @brief  SCSI_Write10\r\n*         Process Write10 command\r\n* @param  lun: Logical unit number\r\n* @param  params: Command parameters\r\n* @retval status\r\n*/\r\n\r\nstatic int8_t SCSI_Write10 (USBD_HandleTypeDef  *pdev, uint8_t lun , uint8_t *params)\r\n{\r\n  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*) pdev->pClassData; \r\n  \r\n  if (hmsc->bot_state == USBD_BOT_IDLE) /* Idle */\r\n  {\r\n    \r\n    /* case 8 : Hi <> Do */\r\n    \r\n    if ((hmsc->cbw.bmFlags & 0x80) == 0x80)\r\n    {\r\n      SCSI_SenseCode(pdev,\r\n                     hmsc->cbw.bLUN, \r\n                     ILLEGAL_REQUEST, \r\n                     INVALID_CDB);\r\n      return -1;\r\n    }\r\n    \r\n    /* Check whether Media is ready */\r\n    if(((USBD_StorageTypeDef *)pdev->pUserData)->IsReady(lun) !=0 )\r\n    {\r\n      SCSI_SenseCode(pdev,\r\n                     lun,\r\n                     NOT_READY, \r\n                     MEDIUM_NOT_PRESENT);\r\n      return -1;\r\n    } \r\n    \r\n    /* Check If media is write-protected */\r\n    if(((USBD_StorageTypeDef *)pdev->pUserData)->IsWriteProtected(lun) !=0 )\r\n    {\r\n      SCSI_SenseCode(pdev,\r\n                     lun,\r\n                     NOT_READY, \r\n                     WRITE_PROTECTED);\r\n      return -1;\r\n    } \r\n    \r\n    \r\n    hmsc->scsi_blk_addr = (params[2] << 24) | \\\r\n      (params[3] << 16) | \\\r\n        (params[4] <<  8) | \\\r\n          params[5];\r\n    hmsc->scsi_blk_len = (params[7] <<  8) | \\\r\n      params[8];  \r\n    \r\n    /* check if LBA address is in the right range */\r\n    if(SCSI_CheckAddressRange(pdev,\r\n                              lun,\r\n                              hmsc->scsi_blk_addr,\r\n                              hmsc->scsi_blk_len) < 0)\r\n    {\r\n      return -1; /* error */      \r\n    }\r\n    \r\n    hmsc->scsi_blk_addr *= hmsc->scsi_blk_size;\r\n    hmsc->scsi_blk_len  *= hmsc->scsi_blk_size;\r\n    \r\n    /* cases 3,11,13 : Hn,Ho <> D0 */\r\n    if (hmsc->cbw.dDataLength != hmsc->scsi_blk_len)\r\n    {\r\n      SCSI_SenseCode(pdev,\r\n                     hmsc->cbw.bLUN, \r\n                     ILLEGAL_REQUEST, \r\n                     INVALID_CDB);\r\n      return -1;\r\n    }\r\n    \r\n    /* Prepare EP to receive first data packet */\r\n    hmsc->bot_state = USBD_BOT_DATA_OUT;  \r\n    USBD_LL_PrepareReceive (pdev,\r\n                      MSC_EPOUT_ADDR,\r\n                      hmsc->bot_data, \r\n                      MIN (hmsc->scsi_blk_len, MSC_MEDIA_PACKET));  \r\n  }\r\n  else /* Write Process ongoing */\r\n  {\r\n    return SCSI_ProcessWrite(pdev, lun);\r\n  }\r\n  return 0;\r\n}\r\n\r\n\r\n/**\r\n* @brief  SCSI_Verify10\r\n*         Process Verify10 command\r\n* @param  lun: Logical unit number\r\n* @param  params: Command parameters\r\n* @retval status\r\n*/\r\n\r\nstatic int8_t SCSI_Verify10(USBD_HandleTypeDef  *pdev, uint8_t lun , uint8_t *params)\r\n{\r\n  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*) pdev->pClassData; \r\n  \r\n  if ((params[1]& 0x02) == 0x02) \r\n  {\r\n    SCSI_SenseCode (pdev,\r\n                    lun, \r\n                    ILLEGAL_REQUEST, \r\n                    INVALID_FIELED_IN_COMMAND);\r\n    return -1; /* Error, Verify Mode Not supported*/\r\n  }\r\n  \r\n  if(SCSI_CheckAddressRange(pdev,\r\n                            lun, \r\n                            hmsc->scsi_blk_addr, \r\n                            hmsc->scsi_blk_len) < 0)\r\n  {\r\n    return -1; /* error */      \r\n  }\r\n  hmsc->bot_data_length = 0;\r\n  return 0;\r\n}\r\n\r\n/**\r\n* @brief  SCSI_CheckAddressRange\r\n*         Check address range\r\n* @param  lun: Logical unit number\r\n* @param  blk_offset: first block address\r\n* @param  blk_nbr: number of block to be processed\r\n* @retval status\r\n*/\r\nstatic int8_t SCSI_CheckAddressRange (USBD_HandleTypeDef  *pdev, uint8_t lun , uint32_t blk_offset , uint16_t blk_nbr)\r\n{\r\n  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*) pdev->pClassData; \r\n  \r\n  if ((blk_offset + blk_nbr) > hmsc->scsi_blk_nbr )\r\n  {\r\n    SCSI_SenseCode(pdev,\r\n                   lun, \r\n                   ILLEGAL_REQUEST, \r\n                   ADDRESS_OUT_OF_RANGE);\r\n    return -1;\r\n  }\r\n  return 0;\r\n}\r\n\r\n/**\r\n* @brief  SCSI_ProcessRead\r\n*         Handle Read Process\r\n* @param  lun: Logical unit number\r\n* @retval status\r\n*/\r\nstatic int8_t SCSI_ProcessRead (USBD_HandleTypeDef  *pdev, uint8_t lun)\r\n{\r\n  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData;   \r\n  uint32_t len;\r\n  \r\n  len = MIN(hmsc->scsi_blk_len , MSC_MEDIA_PACKET); \r\n  \r\n  if( ((USBD_StorageTypeDef *)pdev->pUserData)->Read(lun ,\r\n                              hmsc->bot_data, \r\n                              hmsc->scsi_blk_addr / hmsc->scsi_blk_size, \r\n                              len / hmsc->scsi_blk_size) < 0)\r\n  {\r\n    \r\n    SCSI_SenseCode(pdev,\r\n                   lun, \r\n                   HARDWARE_ERROR, \r\n                   UNRECOVERED_READ_ERROR);\r\n    return -1; \r\n  }\r\n  \r\n  \r\n  USBD_LL_Transmit (pdev, \r\n             MSC_EPIN_ADDR,\r\n             hmsc->bot_data,\r\n             len);\r\n  \r\n  \r\n  hmsc->scsi_blk_addr   += len; \r\n  hmsc->scsi_blk_len    -= len;  \r\n  \r\n  /* case 6 : Hi = Di */\r\n  hmsc->csw.dDataResidue -= len;\r\n  \r\n  if (hmsc->scsi_blk_len == 0)\r\n  {\r\n    hmsc->bot_state = USBD_BOT_LAST_DATA_IN;\r\n  }\r\n  return 0;\r\n}\r\n\r\n/**\r\n* @brief  SCSI_ProcessWrite\r\n*         Handle Write Process\r\n* @param  lun: Logical unit number\r\n* @retval status\r\n*/\r\n\r\nstatic int8_t SCSI_ProcessWrite (USBD_HandleTypeDef  *pdev, uint8_t lun)\r\n{\r\n  uint32_t len;\r\n  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*) pdev->pClassData; \r\n  \r\n  len = MIN(hmsc->scsi_blk_len , MSC_MEDIA_PACKET); \r\n  \r\n  if(((USBD_StorageTypeDef *)pdev->pUserData)->Write(lun ,\r\n                              hmsc->bot_data, \r\n                              hmsc->scsi_blk_addr / hmsc->scsi_blk_size, \r\n                              len / hmsc->scsi_blk_size) < 0)\r\n  {\r\n    SCSI_SenseCode(pdev,\r\n                   lun, \r\n                   HARDWARE_ERROR, \r\n                   WRITE_FAULT);     \r\n    return -1; \r\n  }\r\n  \r\n  \r\n  hmsc->scsi_blk_addr  += len; \r\n  hmsc->scsi_blk_len   -= len; \r\n  \r\n  /* case 12 : Ho = Do */\r\n  hmsc->csw.dDataResidue -= len;\r\n  \r\n  if (hmsc->scsi_blk_len == 0)\r\n  {\r\n    MSC_BOT_SendCSW (pdev, USBD_CSW_CMD_PASSED);\r\n  }\r\n  else\r\n  {\r\n    /* Prepare EP to Receive next packet */\r\n    USBD_LL_PrepareReceive (pdev,\r\n                            MSC_EPOUT_ADDR,\r\n                            hmsc->bot_data, \r\n                            MIN (hmsc->scsi_blk_len, MSC_MEDIA_PACKET)); \r\n  }\r\n  \r\n  return 0;\r\n}\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_storage_template.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_msc_storage_template.c\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   Memory management layer\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_msc_storage_template.h\"\r\n\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Private define ------------------------------------------------------------*/\r\n/* Private macro -------------------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Extern function prototypes ------------------------------------------------*/\r\n/* Private functions ---------------------------------------------------------*/\r\n\r\n#define STORAGE_LUN_NBR                  1  \r\n#define STORAGE_BLK_NBR                  0x10000  \r\n#define STORAGE_BLK_SIZ                  0x200\r\n\r\nint8_t STORAGE_Init (uint8_t lun);\r\n\r\nint8_t STORAGE_GetCapacity (uint8_t lun, \r\n                           uint32_t *block_num, \r\n                           uint16_t *block_size);\r\n\r\nint8_t  STORAGE_IsReady (uint8_t lun);\r\n\r\nint8_t  STORAGE_IsWriteProtected (uint8_t lun);\r\n\r\nint8_t STORAGE_Read (uint8_t lun, \r\n                        uint8_t *buf, \r\n                        uint32_t blk_addr,\r\n                        uint16_t blk_len);\r\n\r\nint8_t STORAGE_Write (uint8_t lun, \r\n                        uint8_t *buf, \r\n                        uint32_t blk_addr,\r\n                        uint16_t blk_len);\r\n\r\nint8_t STORAGE_GetMaxLun (void);\r\n\r\n/* USB Mass storage Standard Inquiry Data */\r\nint8_t  STORAGE_Inquirydata[] = {//36\r\n  \r\n  /* LUN 0 */\r\n  0x00,\t\t\r\n  0x80,\t\t\r\n  0x02,\t\t\r\n  0x02,\r\n  (STANDARD_INQUIRY_DATA_LEN - 5),\r\n  0x00,\r\n  0x00,\t\r\n  0x00,\r\n  'S', 'T', 'M', ' ', ' ', ' ', ' ', ' ', /* Manufacturer : 8 bytes */\r\n  'P', 'r', 'o', 'd', 'u', 'c', 't', ' ', /* Product      : 16 Bytes */\r\n  ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ',\r\n  '0', '.', '0' ,'1',                     /* Version      : 4 Bytes */\r\n}; \r\n\r\nUSBD_StorageTypeDef USBD_MSC_Template_fops =\r\n{\r\n  STORAGE_Init,\r\n  STORAGE_GetCapacity,\r\n  STORAGE_IsReady,\r\n  STORAGE_IsWriteProtected,\r\n  STORAGE_Read,\r\n  STORAGE_Write,\r\n  STORAGE_GetMaxLun,\r\n  STORAGE_Inquirydata,\r\n  \r\n};\r\n/*******************************************************************************\r\n* Function Name  : Read_Memory\r\n* Description    : Handle the Read operation from the microSD card.\r\n* Input          : None.\r\n* Output         : None.\r\n* Return         : None.\r\n*******************************************************************************/\r\nint8_t STORAGE_Init (uint8_t lun)\r\n{\r\n  return (0);\r\n}\r\n\r\n/*******************************************************************************\r\n* Function Name  : Read_Memory\r\n* Description    : Handle the Read operation from the STORAGE card.\r\n* Input          : None.\r\n* Output         : None.\r\n* Return         : None.\r\n*******************************************************************************/\r\nint8_t STORAGE_GetCapacity (uint8_t lun, uint32_t *block_num, uint16_t *block_size)\r\n{\r\n  *block_num  = STORAGE_BLK_NBR;\r\n  *block_size = STORAGE_BLK_SIZ;\r\n  return (0);\r\n}\r\n\r\n/*******************************************************************************\r\n* Function Name  : Read_Memory\r\n* Description    : Handle the Read operation from the STORAGE card.\r\n* Input          : None.\r\n* Output         : None.\r\n* Return         : None.\r\n*******************************************************************************/\r\nint8_t  STORAGE_IsReady (uint8_t lun)\r\n{\r\n  return (0);\r\n}\r\n\r\n/*******************************************************************************\r\n* Function Name  : Read_Memory\r\n* Description    : Handle the Read operation from the STORAGE card.\r\n* Input          : None.\r\n* Output         : None.\r\n* Return         : None.\r\n*******************************************************************************/\r\nint8_t  STORAGE_IsWriteProtected (uint8_t lun)\r\n{\r\n  return  0;\r\n}\r\n\r\n/*******************************************************************************\r\n* Function Name  : Read_Memory\r\n* Description    : Handle the Read operation from the STORAGE card.\r\n* Input          : None.\r\n* Output         : None.\r\n* Return         : None.\r\n*******************************************************************************/\r\nint8_t STORAGE_Read (uint8_t lun, \r\n                 uint8_t *buf, \r\n                 uint32_t blk_addr,                       \r\n                 uint16_t blk_len)\r\n{\r\n  return 0;\r\n}\r\n/*******************************************************************************\r\n* Function Name  : Write_Memory\r\n* Description    : Handle the Write operation to the STORAGE card.\r\n* Input          : None.\r\n* Output         : None.\r\n* Return         : None.\r\n*******************************************************************************/\r\nint8_t STORAGE_Write (uint8_t lun, \r\n                  uint8_t *buf, \r\n                  uint32_t blk_addr,\r\n                  uint16_t blk_len)\r\n{\r\n  return (0);\r\n}\r\n/*******************************************************************************\r\n* Function Name  : Write_Memory\r\n* Description    : Handle the Write operation to the STORAGE card.\r\n* Input          : None.\r\n* Output         : None.\r\n* Return         : None.\r\n*******************************************************************************/\r\nint8_t STORAGE_GetMaxLun (void)\r\n{\r\n  return (STORAGE_LUN_NBR - 1);\r\n}\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Class/Template/Inc/usbd_template.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_template_core.h\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   Header file for the usbd_template_core.c file.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/ \r\n#ifndef __USB_TEMPLATE_CORE_H\r\n#define __USB_TEMPLATE_CORE_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include  \"usbd_ioreq.h\"\r\n\r\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup USBD_TEMPLATE\r\n  * @brief This file is the header file for usbd_template_core.c\r\n  * @{\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_TEMPLATE_Exported_Defines\r\n  * @{\r\n  */ \r\n#define TEMPLATE_EPIN_ADDR                 0x81\r\n#define TEMPLATE_EPIN_SIZE                 0x10\r\n\r\n#define USB_TEMPLATE_CONFIG_DESC_SIZ       64\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_CORE_Exported_TypesDefinitions\r\n  * @{\r\n  */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n\r\n/** @defgroup USBD_CORE_Exported_Macros\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_CORE_Exported_Variables\r\n  * @{\r\n  */ \r\n\r\nextern USBD_ClassTypeDef  USBD_TEMPLATE_ClassDriver;\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USB_CORE_Exported_Functions\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif  /* __USB_TEMPLATE_CORE_H */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n  \r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Class/Template/Src/usbd_template.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_template.c\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   This file provides the HID core functions.\r\n  *\r\n  * @verbatim\r\n  *      \r\n  *          ===================================================================      \r\n  *                                TEMPLATE Class  Description\r\n  *          ===================================================================\r\n  *          \r\n  *\r\n  *\r\n  *\r\n  *           \r\n  *      \r\n  * @note     In HS mode and when the DMA is used, all variables and data structures\r\n  *           dealing with the DMA during the transaction process should be 32-bit aligned.\r\n  *           \r\n  *      \r\n  *  @endverbatim\r\n  *\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_template.h\"\r\n#include \"usbd_desc.h\"\r\n#include \"usbd_ctlreq.h\"\r\n\r\n\r\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n\r\n\r\n/** @defgroup USBD_TEMPLATE \r\n  * @brief usbd core module\r\n  * @{\r\n  */ \r\n\r\n/** @defgroup USBD_TEMPLATE_Private_TypesDefinitions\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_TEMPLATE_Private_Defines\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_TEMPLATE_Private_Macros\r\n  * @{\r\n  */ \r\n                                         \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n\r\n\r\n/** @defgroup USBD_TEMPLATE_Private_FunctionPrototypes\r\n  * @{\r\n  */\r\n\r\n\r\nstatic uint8_t  USBD_TEMPLATE_Init (USBD_HandleTypeDef *pdev, \r\n                               uint8_t cfgidx);\r\n\r\nstatic uint8_t  USBD_TEMPLATE_DeInit (USBD_HandleTypeDef *pdev, \r\n                                 uint8_t cfgidx);\r\n\r\nstatic uint8_t  USBD_TEMPLATE_Setup (USBD_HandleTypeDef *pdev, \r\n                                USBD_SetupReqTypedef *req);\r\n\r\nstatic uint8_t  *USBD_TEMPLATE_GetCfgDesc (uint16_t *length);\r\n\r\nstatic uint8_t  *USBD_TEMPLATE_GetDeviceQualifierDesc (uint16_t *length);\r\n\r\nstatic uint8_t  USBD_TEMPLATE_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum);\r\n\r\nstatic uint8_t  USBD_TEMPLATE_DataOut (USBD_HandleTypeDef *pdev, uint8_t epnum);\r\n\r\nstatic uint8_t  USBD_TEMPLATE_EP0_RxReady (USBD_HandleTypeDef *pdev);\r\n\r\nstatic uint8_t  USBD_TEMPLATE_EP0_TxReady (USBD_HandleTypeDef *pdev);\r\n\r\nstatic uint8_t  USBD_TEMPLATE_SOF (USBD_HandleTypeDef *pdev);\r\n\r\nstatic uint8_t  USBD_TEMPLATE_IsoINIncomplete (USBD_HandleTypeDef *pdev, uint8_t epnum);\r\n\r\nstatic uint8_t  USBD_TEMPLATE_IsoOutIncomplete (USBD_HandleTypeDef *pdev, uint8_t epnum);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_TEMPLATE_Private_Variables\r\n  * @{\r\n  */ \r\n\r\nUSBD_ClassTypeDef  USBD_TEMPLATE_ClassDriver = \r\n{\r\n  USBD_TEMPLATE_Init,\r\n  USBD_TEMPLATE_DeInit,\r\n  USBD_TEMPLATE_Setup,\r\n  USBD_TEMPLATE_EP0_TxReady,  \r\n  USBD_TEMPLATE_EP0_RxReady,\r\n  USBD_TEMPLATE_DataIn,\r\n  USBD_TEMPLATE_DataOut,\r\n  USBD_TEMPLATE_SOF,\r\n  USBD_TEMPLATE_IsoINIncomplete,\r\n  USBD_TEMPLATE_IsoOutIncomplete,      \r\n  USBD_TEMPLATE_GetCfgDesc,\r\n  USBD_TEMPLATE_GetCfgDesc, \r\n  USBD_TEMPLATE_GetCfgDesc,\r\n  USBD_TEMPLATE_GetDeviceQualifierDesc,\r\n};\r\n\r\n#if defined ( __ICCARM__ ) /*!< IAR Compiler */\r\n  #pragma data_alignment=4   \r\n#endif\r\n/* USB TEMPLATE device Configuration Descriptor */\r\nstatic uint8_t USBD_TEMPLATE_CfgDesc[USB_TEMPLATE_CONFIG_DESC_SIZ] =\r\n{\r\n  0x09, /* bLength: Configuation Descriptor size */\r\n  USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION, /* bDescriptorType: Configuration */\r\n  USB_TEMPLATE_CONFIG_DESC_SIZ,\r\n  /* wTotalLength: Bytes returned */\r\n  0x00,\r\n  0x01,         /*bNumInterfaces: 1 interface*/\r\n  0x01,         /*bConfigurationValue: Configuration value*/\r\n  0x02,         /*iConfiguration: Index of string descriptor describing the configuration*/\r\n  0xC0,         /*bmAttributes: bus powered and Supports Remote Wakeup */\r\n  0x32,         /*MaxPower 100 mA: this current is used for detecting Vbus*/\r\n  /* 09 */\r\n  \r\n  /**********  Descriptor of TEMPLATE interface 0 Alternate setting 0 **************/  \r\n \r\n};\r\n  \r\n#if defined ( __ICCARM__ ) /*!< IAR Compiler */\r\n  #pragma data_alignment=4   \r\n#endif\r\n/* USB Standard Device Descriptor */\r\nstatic uint8_t USBD_TEMPLATE_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] =\r\n{\r\n  USB_LEN_DEV_QUALIFIER_DESC,\r\n  USB_DESC_TYPE_DEVICE_QUALIFIER,\r\n  0x00,\r\n  0x02,\r\n  0x00,\r\n  0x00,\r\n  0x00,\r\n  0x40,\r\n  0x01,\r\n  0x00,\r\n};\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_TEMPLATE_Private_Functions\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @brief  USBD_TEMPLATE_Init\r\n  *         Initialize the TEMPLATE interface\r\n  * @param  pdev: device instance\r\n  * @param  cfgidx: Configuration index\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_TEMPLATE_Init (USBD_HandleTypeDef *pdev, \r\n                               uint8_t cfgidx)\r\n{\r\n  uint8_t ret = 0;\r\n  \r\n\r\n  return ret;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_TEMPLATE_Init\r\n  *         DeInitialize the TEMPLATE layer\r\n  * @param  pdev: device instance\r\n  * @param  cfgidx: Configuration index\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_TEMPLATE_DeInit (USBD_HandleTypeDef *pdev, \r\n                                 uint8_t cfgidx)\r\n{\r\n\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_TEMPLATE_Setup\r\n  *         Handle the TEMPLATE specific requests\r\n  * @param  pdev: instance\r\n  * @param  req: usb requests\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_TEMPLATE_Setup (USBD_HandleTypeDef *pdev, \r\n                                USBD_SetupReqTypedef *req)\r\n{\r\n \r\n  switch (req->bmRequest & USB_REQ_TYPE_MASK)\r\n  {\r\n  case USB_REQ_TYPE_CLASS :  \r\n    switch (req->bRequest)\r\n    {\r\n      \r\n    default:\r\n      USBD_CtlError (pdev, req);\r\n      return USBD_FAIL; \r\n    }\r\n    break;\r\n    \r\n  case USB_REQ_TYPE_STANDARD:\r\n    switch (req->bRequest)\r\n    {\r\n    \r\n    default:\r\n      USBD_CtlError (pdev, req);\r\n      return USBD_FAIL;     \r\n    }\r\n  }\r\n  return USBD_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  USBD_TEMPLATE_GetCfgDesc \r\n  *         return configuration descriptor\r\n  * @param  length : pointer data length\r\n  * @retval pointer to descriptor buffer\r\n  */\r\nstatic uint8_t  *USBD_TEMPLATE_GetCfgDesc (uint16_t *length)\r\n{\r\n  *length = sizeof (USBD_TEMPLATE_CfgDesc);\r\n  return USBD_TEMPLATE_CfgDesc;\r\n}\r\n\r\n/**\r\n* @brief  DeviceQualifierDescriptor \r\n*         return Device Qualifier descriptor\r\n* @param  length : pointer data length\r\n* @retval pointer to descriptor buffer\r\n*/\r\nuint8_t  *USBD_TEMPLATE_DeviceQualifierDescriptor (uint16_t *length)\r\n{\r\n  *length = sizeof (USBD_TEMPLATE_DeviceQualifierDesc);\r\n  return USBD_TEMPLATE_DeviceQualifierDesc;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  USBD_TEMPLATE_DataIn\r\n  *         handle data IN Stage\r\n  * @param  pdev: device instance\r\n  * @param  epnum: endpoint index\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_TEMPLATE_DataIn (USBD_HandleTypeDef *pdev, \r\n                              uint8_t epnum)\r\n{\r\n\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_TEMPLATE_EP0_RxReady\r\n  *         handle EP0 Rx Ready event\r\n  * @param  pdev: device instance\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_TEMPLATE_EP0_RxReady (USBD_HandleTypeDef *pdev)\r\n{\r\n\r\n  return USBD_OK;\r\n}\r\n/**\r\n  * @brief  USBD_TEMPLATE_EP0_TxReady\r\n  *         handle EP0 TRx Ready event\r\n  * @param  pdev: device instance\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_TEMPLATE_EP0_TxReady (USBD_HandleTypeDef *pdev)\r\n{\r\n\r\n  return USBD_OK;\r\n}\r\n/**\r\n  * @brief  USBD_TEMPLATE_SOF\r\n  *         handle SOF event\r\n  * @param  pdev: device instance\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_TEMPLATE_SOF (USBD_HandleTypeDef *pdev)\r\n{\r\n\r\n  return USBD_OK;\r\n}\r\n/**\r\n  * @brief  USBD_TEMPLATE_IsoINIncomplete\r\n  *         handle data ISO IN Incomplete event\r\n  * @param  pdev: device instance\r\n  * @param  epnum: endpoint index\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_TEMPLATE_IsoINIncomplete (USBD_HandleTypeDef *pdev, uint8_t epnum)\r\n{\r\n\r\n  return USBD_OK;\r\n}\r\n/**\r\n  * @brief  USBD_TEMPLATE_IsoOutIncomplete\r\n  *         handle data ISO OUT Incomplete event\r\n  * @param  pdev: device instance\r\n  * @param  epnum: endpoint index\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_TEMPLATE_IsoOutIncomplete (USBD_HandleTypeDef *pdev, uint8_t epnum)\r\n{\r\n\r\n  return USBD_OK;\r\n}\r\n/**\r\n  * @brief  USBD_TEMPLATE_DataOut\r\n  *         handle data OUT Stage\r\n  * @param  pdev: device instance\r\n  * @param  epnum: endpoint index\r\n  * @retval status\r\n  */\r\nstatic uint8_t  USBD_TEMPLATE_DataOut (USBD_HandleTypeDef *pdev, \r\n                              uint8_t epnum)\r\n{\r\n\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n* @brief  DeviceQualifierDescriptor \r\n*         return Device Qualifier descriptor\r\n* @param  length : pointer data length\r\n* @retval pointer to descriptor buffer\r\n*/\r\nuint8_t  *USBD_TEMPLATE_GetDeviceQualifierDesc (uint16_t *length)\r\n{\r\n  *length = sizeof (USBD_TEMPLATE_DeviceQualifierDesc);\r\n  return USBD_TEMPLATE_DeviceQualifierDesc;\r\n}\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Core/Inc/usbd_conf_template.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_conf_template.h\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   Header file for the usbd_conf_template.c file\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */\r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __USBD_CONF_TEMPLATE_H\r\n#define __USBD_CONF_TEMPLATE_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"stm32fxxx.h\"  /* replace 'stm32xxx' with your HAL driver header filename, ex: stm32f4xx.h */\r\n#include <stdio.h>\r\n#include <stdlib.h>\r\n#include <string.h>\r\n\r\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup USBD_CONF\r\n  * @brief USB device low level driver configuration file\r\n  * @{\r\n  */ \r\n\r\n/** @defgroup USBD_CONF_Exported_Defines\r\n  * @{\r\n  */ \r\n\r\n#define USBD_MAX_NUM_INTERFACES               1\r\n#define USBD_MAX_NUM_CONFIGURATION            1\r\n#define USBD_MAX_STR_DESC_SIZ                 0x100\r\n#define USBD_SUPPORT_USER_STRING              0 \r\n#define USBD_SELF_POWERED                     1\r\n#define USBD_DEBUG_LEVEL                      2\r\n\r\n/* MSC Class Config */\r\n#define MSC_MEDIA_PACKET                       8192   \r\n\r\n/* CDC Class Config */\r\n#define USBD_CDC_INTERVAL                      2000  \r\n\r\n /* DFU Class Config */\r\n#define USBD_DFU_MAX_ITF_NUM                   1\r\n#define USBD_DFU_XFERS_IZE                     1024\r\n\r\n /* AUDIO Class Config */\r\n#define USBD_AUDIO_FREQ                       22100 \r\n\r\n/** @defgroup USBD_Exported_Macros\r\n  * @{\r\n  */ \r\n\r\n /* Memory management macros */   \r\n#define USBD_malloc               malloc\r\n#define USBD_free                 free\r\n#define USBD_memset               memset\r\n#define USBD_memcpy               memcpy\r\n    \r\n /* DEBUG macros */  \r\n\r\n  \r\n#if (USBD_DEBUG_LEVEL > 0)\r\n#define  USBD_UsrLog(...)   printf(__VA_ARGS__);\\\r\n                            printf(\"\\n\");\r\n#else\r\n#define USBD_UsrLog(...)   \r\n#endif \r\n                            \r\n                            \r\n#if (USBD_DEBUG_LEVEL > 1)\r\n\r\n#define  USBD_ErrLog(...)   printf(\"ERROR: \") ;\\\r\n                            printf(__VA_ARGS__);\\\r\n                            printf(\"\\n\");\r\n#else\r\n#define USBD_ErrLog(...)   \r\n#endif \r\n                            \r\n                            \r\n#if (USBD_DEBUG_LEVEL > 2)                         \r\n#define  USBD_DbgLog(...)   printf(\"DEBUG : \") ;\\\r\n                            printf(__VA_ARGS__);\\\r\n                            printf(\"\\n\");\r\n#else\r\n#define USBD_DbgLog(...)                         \r\n#endif\r\n                            \r\n/**\r\n  * @}\r\n  */ \r\n \r\n    \r\n    \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_CONF_Exported_Types\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_CONF_Exported_Macros\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_CONF_Exported_Variables\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_CONF_Exported_FunctionsPrototype\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __USBD_CONF_TEMPLATE_H */\r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Core/Inc/usbd_core.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_core.h\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   Header file for usbd_core.c file\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __USBD_CORE_H\r\n#define __USBD_CORE_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_conf.h\"\r\n#include \"usbd_def.h\"\r\n#include \"usbd_ioreq.h\"\r\n#include \"usbd_ctlreq.h\"\r\n\r\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup USBD_CORE\r\n  * @brief This file is the Header file for usbd_core.c file\r\n  * @{\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_CORE_Exported_Defines\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_CORE_Exported_TypesDefinitions\r\n  * @{\r\n  */\r\n \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n\r\n/** @defgroup USBD_CORE_Exported_Macros\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_CORE_Exported_Variables\r\n  * @{\r\n  */ \r\n#define USBD_SOF          USBD_LL_SOF\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_CORE_Exported_FunctionsPrototype\r\n  * @{\r\n  */ \r\nUSBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id);\r\nUSBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev);\r\nUSBD_StatusTypeDef USBD_Start  (USBD_HandleTypeDef *pdev);\r\nUSBD_StatusTypeDef USBD_Stop   (USBD_HandleTypeDef *pdev);\r\nUSBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass);\r\n\r\nUSBD_StatusTypeDef USBD_RunTestMode (USBD_HandleTypeDef  *pdev); \r\nUSBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef  *pdev, uint8_t cfgidx);\r\nUSBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef  *pdev, uint8_t cfgidx);\r\n\r\nUSBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup);\r\nUSBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata);\r\nUSBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata);\r\n\r\nUSBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef  *pdev);\r\nUSBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef  *pdev, USBD_SpeedTypeDef speed);\r\nUSBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef  *pdev);\r\nUSBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef  *pdev);\r\n\r\nUSBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef  *pdev);\r\nUSBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef  *pdev, uint8_t epnum);\r\nUSBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef  *pdev, uint8_t epnum);\r\n\r\nUSBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef  *pdev);\r\nUSBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef  *pdev);\r\n\r\n/* USBD Low Level Driver */\r\nUSBD_StatusTypeDef  USBD_LL_Init (USBD_HandleTypeDef *pdev);\r\nUSBD_StatusTypeDef  USBD_LL_DeInit (USBD_HandleTypeDef *pdev);\r\nUSBD_StatusTypeDef  USBD_LL_Start(USBD_HandleTypeDef *pdev);\r\nUSBD_StatusTypeDef  USBD_LL_Stop (USBD_HandleTypeDef *pdev);\r\nUSBD_StatusTypeDef  USBD_LL_OpenEP  (USBD_HandleTypeDef *pdev, \r\n                                      uint8_t  ep_addr,                                      \r\n                                      uint8_t  ep_type,\r\n                                      uint16_t ep_mps);\r\n\r\nUSBD_StatusTypeDef  USBD_LL_CloseEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr);   \r\nUSBD_StatusTypeDef  USBD_LL_FlushEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr);   \r\nUSBD_StatusTypeDef  USBD_LL_StallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr);   \r\nUSBD_StatusTypeDef  USBD_LL_ClearStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr);   \r\nuint8_t             USBD_LL_IsStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr);   \r\nUSBD_StatusTypeDef  USBD_LL_SetUSBAddress (USBD_HandleTypeDef *pdev, uint8_t dev_addr);   \r\nUSBD_StatusTypeDef  USBD_LL_Transmit (USBD_HandleTypeDef *pdev, \r\n                                      uint8_t  ep_addr,                                      \r\n                                      uint8_t  *pbuf,\r\n                                      uint16_t  size);\r\n\r\nUSBD_StatusTypeDef  USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, \r\n                                           uint8_t  ep_addr,                                      \r\n                                           uint8_t  *pbuf,\r\n                                           uint16_t  size);\r\n\r\nuint32_t USBD_LL_GetRxDataSize  (USBD_HandleTypeDef *pdev, uint8_t  ep_addr);  \r\nvoid  USBD_LL_Delay (uint32_t Delay);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __USBD_CORE_H */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n* @}\r\n*/ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n\r\n\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_req.h\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   Header file for the usbd_req.c file\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __USB_REQUEST_H\r\n#define __USB_REQUEST_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include  \"usbd_def.h\"\r\n\r\n\r\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup USBD_REQ\r\n  * @brief header file for the usbd_req.c file\r\n  * @{\r\n  */ \r\n\r\n/** @defgroup USBD_REQ_Exported_Defines\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_REQ_Exported_Types\r\n  * @{\r\n  */\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n\r\n/** @defgroup USBD_REQ_Exported_Macros\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_REQ_Exported_Variables\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_REQ_Exported_FunctionsPrototype\r\n  * @{\r\n  */ \r\n\r\nUSBD_StatusTypeDef  USBD_StdDevReq (USBD_HandleTypeDef  *pdev, USBD_SetupReqTypedef  *req);\r\nUSBD_StatusTypeDef  USBD_StdItfReq (USBD_HandleTypeDef  *pdev, USBD_SetupReqTypedef  *req);\r\nUSBD_StatusTypeDef  USBD_StdEPReq  (USBD_HandleTypeDef  *pdev, USBD_SetupReqTypedef  *req);\r\n\r\n\r\nvoid USBD_CtlError  (USBD_HandleTypeDef  *pdev, USBD_SetupReqTypedef *req);\r\n\r\nvoid USBD_ParseSetupRequest (USBD_SetupReqTypedef *req, uint8_t *pdata);\r\n\r\nvoid USBD_GetString         (uint8_t *desc, uint8_t *unicode, uint16_t *len);\r\n/**\r\n  * @}\r\n  */ \r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __USB_REQUEST_H */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n* @}\r\n*/ \r\n\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Core/Inc/usbd_def.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_def.h\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   General defines for the usb device library \r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __USBD_DEF_H\r\n#define __USBD_DEF_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_conf.h\"\r\n\r\n/** @addtogroup STM32_USBD_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup USB_DEF\r\n  * @brief general defines for the usb device library file\r\n  * @{\r\n  */ \r\n\r\n/** @defgroup USB_DEF_Exported_Defines\r\n  * @{\r\n  */ \r\n\r\n#ifndef NULL\r\n#define NULL  0\r\n#endif\r\n\r\n\r\n#define  USB_LEN_DEV_QUALIFIER_DESC                     0x0A\r\n#define  USB_LEN_DEV_DESC                               0x12\r\n#define  USB_LEN_CFG_DESC                               0x09\r\n#define  USB_LEN_IF_DESC                                0x09\r\n#define  USB_LEN_EP_DESC                                0x07\r\n#define  USB_LEN_OTG_DESC                               0x03\r\n#define  USB_LEN_LANGID_STR_DESC                        0x04\r\n#define  USB_LEN_OTHER_SPEED_DESC_SIZ                   0x09\r\n\r\n#define  USBD_IDX_LANGID_STR                            0x00 \r\n#define  USBD_IDX_MFC_STR                               0x01 \r\n#define  USBD_IDX_PRODUCT_STR                           0x02\r\n#define  USBD_IDX_SERIAL_STR                            0x03 \r\n#define  USBD_IDX_CONFIG_STR                            0x04 \r\n#define  USBD_IDX_INTERFACE_STR                         0x05 \r\n\r\n#define  USB_REQ_TYPE_STANDARD                          0x00\r\n#define  USB_REQ_TYPE_CLASS                             0x20\r\n#define  USB_REQ_TYPE_VENDOR                            0x40\r\n#define  USB_REQ_TYPE_MASK                              0x60\r\n\r\n#define  USB_REQ_RECIPIENT_DEVICE                       0x00\r\n#define  USB_REQ_RECIPIENT_INTERFACE                    0x01\r\n#define  USB_REQ_RECIPIENT_ENDPOINT                     0x02\r\n#define  USB_REQ_RECIPIENT_MASK                         0x03\r\n\r\n#define  USB_REQ_GET_STATUS                             0x00\r\n#define  USB_REQ_CLEAR_FEATURE                          0x01\r\n#define  USB_REQ_SET_FEATURE                            0x03\r\n#define  USB_REQ_SET_ADDRESS                            0x05\r\n#define  USB_REQ_GET_DESCRIPTOR                         0x06\r\n#define  USB_REQ_SET_DESCRIPTOR                         0x07\r\n#define  USB_REQ_GET_CONFIGURATION                      0x08\r\n#define  USB_REQ_SET_CONFIGURATION                      0x09\r\n#define  USB_REQ_GET_INTERFACE                          0x0A\r\n#define  USB_REQ_SET_INTERFACE                          0x0B\r\n#define  USB_REQ_SYNCH_FRAME                            0x0C\r\n\r\n#define  USB_DESC_TYPE_DEVICE                              1\r\n#define  USB_DESC_TYPE_CONFIGURATION                       2\r\n#define  USB_DESC_TYPE_STRING                              3\r\n#define  USB_DESC_TYPE_INTERFACE                           4\r\n#define  USB_DESC_TYPE_ENDPOINT                            5\r\n#define  USB_DESC_TYPE_DEVICE_QUALIFIER                    6\r\n#define  USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION           7\r\n#define  USB_DESC_TYPE_BOS                                 0x0F\r\n\r\n#define USB_CONFIG_REMOTE_WAKEUP                           2\r\n#define USB_CONFIG_SELF_POWERED                            1\r\n\r\n#define USB_FEATURE_EP_HALT                                0\r\n#define USB_FEATURE_REMOTE_WAKEUP                          1\r\n#define USB_FEATURE_TEST_MODE                              2\r\n\r\n#define USB_DEVICE_CAPABITY_TYPE                           0x10\r\n\r\n#define USB_HS_MAX_PACKET_SIZE                            512\r\n#define USB_FS_MAX_PACKET_SIZE                            64\r\n#define USB_MAX_EP0_SIZE                                  64\r\n\r\n/*  Device Status */\r\n#define USBD_STATE_DEFAULT                                1\r\n#define USBD_STATE_ADDRESSED                              2\r\n#define USBD_STATE_CONFIGURED                             3\r\n#define USBD_STATE_SUSPENDED                              4\r\n\r\n\r\n/*  EP0 State */    \r\n#define USBD_EP0_IDLE                                     0\r\n#define USBD_EP0_SETUP                                    1\r\n#define USBD_EP0_DATA_IN                                  2\r\n#define USBD_EP0_DATA_OUT                                 3\r\n#define USBD_EP0_STATUS_IN                                4\r\n#define USBD_EP0_STATUS_OUT                               5\r\n#define USBD_EP0_STALL                                    6    \r\n\r\n#define USBD_EP_TYPE_CTRL                                 0\r\n#define USBD_EP_TYPE_ISOC                                 1\r\n#define USBD_EP_TYPE_BULK                                 2\r\n#define USBD_EP_TYPE_INTR                                 3\r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_DEF_Exported_TypesDefinitions\r\n  * @{\r\n  */\r\n\r\ntypedef  struct  usb_setup_req \r\n{\r\n    \r\n    uint8_t   bmRequest;                      \r\n    uint8_t   bRequest;                           \r\n    uint16_t  wValue;                             \r\n    uint16_t  wIndex;                             \r\n    uint16_t  wLength;                            \r\n}USBD_SetupReqTypedef;\r\n\r\nstruct _USBD_HandleTypeDef;\r\n    \r\ntypedef struct _Device_cb\r\n{\r\n  uint8_t  (*Init)             (struct _USBD_HandleTypeDef *pdev , uint8_t cfgidx);\r\n  uint8_t  (*DeInit)           (struct _USBD_HandleTypeDef *pdev , uint8_t cfgidx);\r\n /* Control Endpoints*/\r\n  uint8_t  (*Setup)            (struct _USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef  *req);  \r\n  uint8_t  (*EP0_TxSent)       (struct _USBD_HandleTypeDef *pdev );    \r\n  uint8_t  (*EP0_RxReady)      (struct _USBD_HandleTypeDef *pdev );  \r\n  /* Class Specific Endpoints*/\r\n  uint8_t  (*DataIn)           (struct _USBD_HandleTypeDef *pdev , uint8_t epnum);   \r\n  uint8_t  (*DataOut)          (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); \r\n  uint8_t  (*SOF)              (struct _USBD_HandleTypeDef *pdev); \r\n  uint8_t  (*IsoINIncomplete)  (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); \r\n  uint8_t  (*IsoOUTIncomplete) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum);   \r\n\r\n  uint8_t  *(*GetHSConfigDescriptor)(uint16_t *length); \r\n  uint8_t  *(*GetFSConfigDescriptor)(uint16_t *length);   \r\n  uint8_t  *(*GetOtherSpeedConfigDescriptor)(uint16_t *length);\r\n  uint8_t  *(*GetDeviceQualifierDescriptor)(uint16_t *length);\r\n#if (USBD_SUPPORT_USER_STRING == 1)\r\n  uint8_t  *(*GetUsrStrDescriptor)(struct _USBD_HandleTypeDef *pdev ,uint8_t index,  uint16_t *length);   \r\n#endif  \r\n  \r\n} USBD_ClassTypeDef;\r\n\r\n/* Following USB Device Speed */\r\ntypedef enum \r\n{\r\n  USBD_SPEED_HIGH  = 0,\r\n  USBD_SPEED_FULL  = 1,\r\n  USBD_SPEED_LOW   = 2,  \r\n}USBD_SpeedTypeDef;\r\n\r\n/* Following USB Device status */\r\ntypedef enum {\r\n  USBD_OK   = 0,\r\n  USBD_BUSY,\r\n  USBD_FAIL,\r\n}USBD_StatusTypeDef;\r\n\r\n/* USB Device descriptors structure */\r\ntypedef struct\r\n{\r\n  uint8_t  *(*GetDeviceDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length);  \r\n  uint8_t  *(*GetLangIDStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); \r\n  uint8_t  *(*GetManufacturerStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length);  \r\n  uint8_t  *(*GetProductStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length);  \r\n  uint8_t  *(*GetSerialStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length);  \r\n  uint8_t  *(*GetConfigurationStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length);  \r\n  uint8_t  *(*GetInterfaceStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); \r\n#if (USBD_LPM_ENABLED == 1)\r\n  uint8_t  *(*GetBOSDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); \r\n#endif  \r\n} USBD_DescriptorsTypeDef;\r\n\r\n/* USB Device handle structure */\r\ntypedef struct\r\n{ \r\n  uint32_t                status;\r\n  uint32_t                total_length;    \r\n  uint32_t                rem_length; \r\n  uint32_t                maxpacket;   \r\n} USBD_EndpointTypeDef;\r\n\r\n/* USB Device handle structure */\r\ntypedef struct _USBD_HandleTypeDef\r\n{\r\n  uint8_t                 id;\r\n  uint32_t                dev_config;\r\n  uint32_t                dev_default_config;\r\n  uint32_t                dev_config_status; \r\n  USBD_SpeedTypeDef       dev_speed; \r\n  USBD_EndpointTypeDef    ep_in[15];\r\n  USBD_EndpointTypeDef    ep_out[15];  \r\n  uint32_t                ep0_state;  \r\n  uint32_t                ep0_data_len;     \r\n  uint8_t                 dev_state;\r\n  uint8_t                 dev_old_state;\r\n  uint8_t                 dev_address;\r\n  uint8_t                 dev_connection_status;  \r\n  uint8_t                 dev_test_mode;\r\n  uint32_t                dev_remote_wakeup;\r\n\r\n  USBD_SetupReqTypedef    request;\r\n  USBD_DescriptorsTypeDef *pDesc;\r\n  USBD_ClassTypeDef       *pClass;\r\n  void                    *pClassData;  \r\n  void                    *pUserData;    \r\n  void                    *pData;    \r\n} USBD_HandleTypeDef;\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n\r\n/** @defgroup USBD_DEF_Exported_Macros\r\n  * @{\r\n  */ \r\n#define  SWAPBYTE(addr)        (((uint16_t)(*((uint8_t *)(addr)))) + \\\r\n                               (((uint16_t)(*(((uint8_t *)(addr)) + 1))) << 8))\r\n\r\n#define LOBYTE(x)  ((uint8_t)(x & 0x00FF))\r\n#define HIBYTE(x)  ((uint8_t)((x & 0xFF00) >>8))\r\n#define MIN(a, b)  (((a) < (b)) ? (a) : (b))\r\n#define MAX(a, b)  (((a) > (b)) ? (a) : (b))\r\n\r\n\r\n#if  defined ( __GNUC__ )\r\n  #ifndef __weak\r\n    #define __weak   __attribute__((weak))\r\n  #endif /* __weak */\r\n  #ifndef __packed\r\n    #define __packed __attribute__((__packed__))\r\n  #endif /* __packed */\r\n#endif /* __GNUC__ */\r\n\r\n\r\n/* In HS mode and when the DMA is used, all variables and data structures dealing\r\n   with the DMA during the transaction process should be 4-bytes aligned */    \r\n\r\n#if defined   (__GNUC__)        /* GNU Compiler */\r\n  #define __ALIGN_END    __attribute__ ((aligned (4)))\r\n  #define __ALIGN_BEGIN         \r\n#else                           \r\n  #define __ALIGN_END\r\n  #if defined   (__CC_ARM)      /* ARM Compiler */\r\n    #define __ALIGN_BEGIN    __align(4)  \r\n  #elif defined (__ICCARM__)    /* IAR Compiler */\r\n    #define __ALIGN_BEGIN \r\n  #elif defined  (__TASKING__)  /* TASKING Compiler */\r\n    #define __ALIGN_BEGIN    __align(4) \r\n  #endif /* __CC_ARM */  \r\n#endif /* __GNUC__ */ \r\n  \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_DEF_Exported_Variables\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_DEF_Exported_FunctionsPrototype\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __USBD_DEF_H */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n* @}\r\n*/ \r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_ioreq.h\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   Header file for the usbd_ioreq.c file\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Define to prevent recursive inclusion -------------------------------------*/\r\n#ifndef __USBD_IOREQ_H\r\n#define __USBD_IOREQ_H\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include  \"usbd_def.h\"\r\n#include  \"usbd_core.h\"\r\n\r\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n  \r\n/** @defgroup USBD_IOREQ\r\n  * @brief header file for the usbd_ioreq.c file\r\n  * @{\r\n  */ \r\n\r\n/** @defgroup USBD_IOREQ_Exported_Defines\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_IOREQ_Exported_Types\r\n  * @{\r\n  */\r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n\r\n/** @defgroup USBD_IOREQ_Exported_Macros\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_IOREQ_Exported_Variables\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/** @defgroup USBD_IOREQ_Exported_FunctionsPrototype\r\n  * @{\r\n  */ \r\n\r\nUSBD_StatusTypeDef  USBD_CtlSendData (USBD_HandleTypeDef  *pdev, \r\n                               uint8_t *buf,\r\n                               uint16_t len);\r\n\r\nUSBD_StatusTypeDef  USBD_CtlContinueSendData (USBD_HandleTypeDef  *pdev, \r\n                               uint8_t *pbuf,\r\n                               uint16_t len);\r\n\r\nUSBD_StatusTypeDef USBD_CtlPrepareRx (USBD_HandleTypeDef  *pdev, \r\n                               uint8_t *pbuf,                                 \r\n                               uint16_t len);\r\n\r\nUSBD_StatusTypeDef  USBD_CtlContinueRx (USBD_HandleTypeDef  *pdev, \r\n                              uint8_t *pbuf,                                          \r\n                              uint16_t len);\r\n\r\nUSBD_StatusTypeDef  USBD_CtlSendStatus (USBD_HandleTypeDef  *pdev);\r\n\r\nUSBD_StatusTypeDef  USBD_CtlReceiveStatus (USBD_HandleTypeDef  *pdev);\r\n\r\nuint16_t  USBD_GetRxCount (USBD_HandleTypeDef  *pdev , \r\n                           uint8_t epnum);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif /* __USBD_IOREQ_H */\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/**\r\n* @}\r\n*/ \r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Core/Src/usbd_core.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_core.c\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   This file provides all the USBD core functions.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_core.h\"\r\n\r\n/** @addtogroup STM32_USBD_DEVICE_LIBRARY\r\n* @{\r\n*/\r\n\r\n\r\n/** @defgroup USBD_CORE \r\n* @brief usbd core module\r\n* @{\r\n*/ \r\n\r\n/** @defgroup USBD_CORE_Private_TypesDefinitions\r\n* @{\r\n*/ \r\n/**\r\n* @}\r\n*/ \r\n\r\n\r\n/** @defgroup USBD_CORE_Private_Defines\r\n* @{\r\n*/ \r\n\r\n/**\r\n* @}\r\n*/ \r\n\r\n\r\n/** @defgroup USBD_CORE_Private_Macros\r\n* @{\r\n*/ \r\n/**\r\n* @}\r\n*/ \r\n\r\n\r\n\r\n\r\n/** @defgroup USBD_CORE_Private_FunctionPrototypes\r\n* @{\r\n*/ \r\n\r\n/**\r\n* @}\r\n*/ \r\n\r\n/** @defgroup USBD_CORE_Private_Variables\r\n* @{\r\n*/ \r\n\r\n/**\r\n* @}\r\n*/ \r\n\r\n/** @defgroup USBD_CORE_Private_Functions\r\n* @{\r\n*/ \r\n\r\n/**\r\n* @brief  USBD_Init\r\n*         Initializes the device stack and load the class driver\r\n* @param  pdev: device instance\r\n* @param  pdesc: Descriptor structure address\r\n* @param  id: Low level core index\r\n* @retval None\r\n*/\r\nUSBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id)\r\n{\r\n  /* Check whether the USB Host handle is valid */\r\n  if(pdev == NULL)\r\n  {\r\n    USBD_ErrLog(\"Invalid Device handle\");\r\n    return USBD_FAIL; \r\n  }\r\n  \r\n  /* Unlink previous class*/\r\n  if(pdev->pClass != NULL)\r\n  {\r\n    pdev->pClass = NULL;\r\n  }\r\n  \r\n  /* Assign USBD Descriptors */\r\n  if(pdesc != NULL)\r\n  {\r\n    pdev->pDesc = pdesc;\r\n  }\r\n  \r\n  /* Set Device initial State */\r\n  pdev->dev_state  = USBD_STATE_DEFAULT;\r\n  pdev->id = id;\r\n  /* Initialize low level driver */\r\n  USBD_LL_Init(pdev);\r\n  \r\n  return USBD_OK; \r\n}\r\n\r\n/**\r\n* @brief  USBD_DeInit \r\n*         Re-Initialize th device library\r\n* @param  pdev: device instance\r\n* @retval status: status\r\n*/\r\nUSBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev)\r\n{\r\n  /* Set Default State */\r\n  pdev->dev_state  = USBD_STATE_DEFAULT;\r\n  \r\n  /* Free Class Resources */\r\n  pdev->pClass->DeInit(pdev, pdev->dev_config);  \r\n  \r\n    /* Stop the low level driver  */\r\n  USBD_LL_Stop(pdev); \r\n  \r\n  /* Initialize low level driver */\r\n  USBD_LL_DeInit(pdev);\r\n  \r\n  return USBD_OK;\r\n}\r\n\r\n\r\n/**\r\n  * @brief  USBD_RegisterClass \r\n  *         Link class driver to Device Core.\r\n  * @param  pDevice : Device Handle\r\n  * @param  pclass: Class handle\r\n  * @retval USBD Status\r\n  */\r\nUSBD_StatusTypeDef  USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass)\r\n{\r\n  USBD_StatusTypeDef   status = USBD_OK;\r\n  if(pclass != 0)\r\n  {\r\n    /* link the class to the USB Device handle */\r\n    pdev->pClass = pclass;\r\n    status = USBD_OK;\r\n  }\r\n  else\r\n  {\r\n    USBD_ErrLog(\"Invalid Class handle\");\r\n    status = USBD_FAIL; \r\n  }\r\n  \r\n  return status;\r\n}\r\n\r\n/**\r\n  * @brief  USBD_Start \r\n  *         Start the USB Device Core.\r\n  * @param  pdev: Device Handle\r\n  * @retval USBD Status\r\n  */\r\nUSBD_StatusTypeDef  USBD_Start  (USBD_HandleTypeDef *pdev)\r\n{\r\n  \r\n  /* Start the low level driver  */\r\n  USBD_LL_Start(pdev); \r\n  \r\n  return USBD_OK;  \r\n}\r\n\r\n/**\r\n  * @brief  USBD_Stop \r\n  *         Stop the USB Device Core.\r\n  * @param  pdev: Device Handle\r\n  * @retval USBD Status\r\n  */\r\nUSBD_StatusTypeDef  USBD_Stop   (USBD_HandleTypeDef *pdev)\r\n{\r\n  /* Free Class Resources */\r\n  pdev->pClass->DeInit(pdev, pdev->dev_config);  \r\n\r\n  /* Stop the low level driver  */\r\n  USBD_LL_Stop(pdev); \r\n  \r\n  return USBD_OK;  \r\n}\r\n\r\n/**\r\n* @brief  USBD_RunTestMode \r\n*         Launch test mode process\r\n* @param  pdev: device instance\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef  USBD_RunTestMode (USBD_HandleTypeDef  *pdev) \r\n{\r\n  return USBD_OK;\r\n}\r\n\r\n\r\n/**\r\n* @brief  USBD_SetClassConfig \r\n*        Configure device and start the interface\r\n* @param  pdev: device instance\r\n* @param  cfgidx: configuration index\r\n* @retval status\r\n*/\r\n\r\nUSBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef  *pdev, uint8_t cfgidx)\r\n{\r\n  USBD_StatusTypeDef   ret = USBD_FAIL;\r\n  \r\n  if(pdev->pClass != NULL)\r\n  {\r\n    /* Set configuration  and Start the Class*/\r\n    if(pdev->pClass->Init(pdev, cfgidx) == 0)\r\n    {\r\n      ret = USBD_OK;\r\n    }\r\n  }\r\n  return ret; \r\n}\r\n\r\n/**\r\n* @brief  USBD_ClrClassConfig \r\n*         Clear current configuration\r\n* @param  pdev: device instance\r\n* @param  cfgidx: configuration index\r\n* @retval status: USBD_StatusTypeDef\r\n*/\r\nUSBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef  *pdev, uint8_t cfgidx)\r\n{\r\n  /* Clear configuration  and De-initialize the Class process*/\r\n  pdev->pClass->DeInit(pdev, cfgidx);  \r\n  return USBD_OK;\r\n}\r\n\r\n\r\n/**\r\n* @brief  USBD_SetupStage \r\n*         Handle the setup stage\r\n* @param  pdev: device instance\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup)\r\n{\r\n\r\n  USBD_ParseSetupRequest(&pdev->request, psetup);\r\n  \r\n  pdev->ep0_state = USBD_EP0_SETUP;\r\n  pdev->ep0_data_len = pdev->request.wLength;\r\n  \r\n  switch (pdev->request.bmRequest & 0x1F) \r\n  {\r\n  case USB_REQ_RECIPIENT_DEVICE:   \r\n    USBD_StdDevReq (pdev, &pdev->request);\r\n    break;\r\n    \r\n  case USB_REQ_RECIPIENT_INTERFACE:     \r\n    USBD_StdItfReq(pdev, &pdev->request);\r\n    break;\r\n    \r\n  case USB_REQ_RECIPIENT_ENDPOINT:        \r\n    USBD_StdEPReq(pdev, &pdev->request);   \r\n    break;\r\n    \r\n  default:           \r\n    USBD_LL_StallEP(pdev , pdev->request.bmRequest & 0x80);\r\n    break;\r\n  }  \r\n  return USBD_OK;  \r\n}\r\n\r\n/**\r\n* @brief  USBD_DataOutStage \r\n*         Handle data OUT stage\r\n* @param  pdev: device instance\r\n* @param  epnum: endpoint index\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata)\r\n{\r\n  USBD_EndpointTypeDef    *pep;\r\n  \r\n  if(epnum == 0) \r\n  {\r\n    pep = &pdev->ep_out[0];\r\n    \r\n    if ( pdev->ep0_state == USBD_EP0_DATA_OUT)\r\n    {\r\n      if(pep->rem_length > pep->maxpacket)\r\n      {\r\n        pep->rem_length -=  pep->maxpacket;\r\n       \r\n        USBD_CtlContinueRx (pdev, \r\n                            pdata,\r\n                            MIN(pep->rem_length ,pep->maxpacket));\r\n      }\r\n      else\r\n      {\r\n        if((pdev->pClass->EP0_RxReady != NULL)&&\r\n           (pdev->dev_state == USBD_STATE_CONFIGURED))\r\n        {\r\n          pdev->pClass->EP0_RxReady(pdev); \r\n        }\r\n        USBD_CtlSendStatus(pdev);\r\n      }\r\n    }\r\n  }\r\n  else if((pdev->pClass->DataOut != NULL)&&\r\n          (pdev->dev_state == USBD_STATE_CONFIGURED))\r\n  {\r\n    pdev->pClass->DataOut(pdev, epnum); \r\n  }  \r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n* @brief  USBD_DataInStage \r\n*         Handle data in stage\r\n* @param  pdev: device instance\r\n* @param  epnum: endpoint index\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev ,uint8_t epnum, uint8_t *pdata)\r\n{\r\n  USBD_EndpointTypeDef    *pep;\r\n    \r\n  if(epnum == 0) \r\n  {\r\n    pep = &pdev->ep_in[0];\r\n    \r\n    if ( pdev->ep0_state == USBD_EP0_DATA_IN)\r\n    {\r\n      if(pep->rem_length > pep->maxpacket)\r\n      {\r\n        pep->rem_length -=  pep->maxpacket;\r\n        \r\n        USBD_CtlContinueSendData (pdev, \r\n                                  pdata, \r\n                                  pep->rem_length);\r\n        \r\n        /* Prepare endpoint for premature end of transfer */\r\n        USBD_LL_PrepareReceive (pdev,\r\n                                0,\r\n                                NULL,\r\n                                0);  \r\n      }\r\n      else\r\n      { /* last packet is MPS multiple, so send ZLP packet */\r\n        if((pep->total_length % pep->maxpacket == 0) &&\r\n           (pep->total_length >= pep->maxpacket) &&\r\n             (pep->total_length < pdev->ep0_data_len ))\r\n        {\r\n          \r\n          USBD_CtlContinueSendData(pdev , NULL, 0);\r\n          pdev->ep0_data_len = 0;\r\n          \r\n        /* Prepare endpoint for premature end of transfer */\r\n        USBD_LL_PrepareReceive (pdev,\r\n                                0,\r\n                                NULL,\r\n                                0);\r\n        }\r\n        else\r\n        {\r\n          if((pdev->pClass->EP0_TxSent != NULL)&&\r\n             (pdev->dev_state == USBD_STATE_CONFIGURED))\r\n          {\r\n            pdev->pClass->EP0_TxSent(pdev); \r\n          }          \r\n          USBD_CtlReceiveStatus(pdev);\r\n        }\r\n      }\r\n    }\r\n    if (pdev->dev_test_mode == 1)\r\n    {\r\n      USBD_RunTestMode(pdev); \r\n      pdev->dev_test_mode = 0;\r\n    }\r\n  }\r\n  else if((pdev->pClass->DataIn != NULL)&& \r\n          (pdev->dev_state == USBD_STATE_CONFIGURED))\r\n  {\r\n    pdev->pClass->DataIn(pdev, epnum); \r\n  }  \r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n* @brief  USBD_LL_Reset \r\n*         Handle Reset event\r\n* @param  pdev: device instance\r\n* @retval status\r\n*/\r\n\r\nUSBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef  *pdev)\r\n{\r\n  /* Open EP0 OUT */\r\n  USBD_LL_OpenEP(pdev,\r\n              0x00,\r\n              USBD_EP_TYPE_CTRL,\r\n              USB_MAX_EP0_SIZE);\r\n  \r\n  pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE;\r\n  \r\n  /* Open EP0 IN */\r\n  USBD_LL_OpenEP(pdev,\r\n              0x80,\r\n              USBD_EP_TYPE_CTRL,\r\n              USB_MAX_EP0_SIZE);\r\n  \r\n  pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE;\r\n  /* Upon Reset call user call back */\r\n  pdev->dev_state = USBD_STATE_DEFAULT;\r\n  \r\n  if (pdev->pClassData) \r\n    pdev->pClass->DeInit(pdev, pdev->dev_config);  \r\n \r\n  \r\n  return USBD_OK;\r\n}\r\n\r\n\r\n\r\n\r\n/**\r\n* @brief  USBD_LL_Reset \r\n*         Handle Reset event\r\n* @param  pdev: device instance\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef  *pdev, USBD_SpeedTypeDef speed)\r\n{\r\n  pdev->dev_speed = speed;\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n* @brief  USBD_Suspend \r\n*         Handle Suspend event\r\n* @param  pdev: device instance\r\n* @retval status\r\n*/\r\n\r\nUSBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef  *pdev)\r\n{\r\n  pdev->dev_old_state =  pdev->dev_state;\r\n  pdev->dev_state  = USBD_STATE_SUSPENDED;\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n* @brief  USBD_Resume \r\n*         Handle Resume event\r\n* @param  pdev: device instance\r\n* @retval status\r\n*/\r\n\r\nUSBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef  *pdev)\r\n{\r\n  pdev->dev_state = pdev->dev_old_state;  \r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n* @brief  USBD_SOF \r\n*         Handle SOF event\r\n* @param  pdev: device instance\r\n* @retval status\r\n*/\r\n\r\nUSBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef  *pdev)\r\n{\r\n  if(pdev->dev_state == USBD_STATE_CONFIGURED)\r\n  {\r\n    if(pdev->pClass->SOF != NULL)\r\n    {\r\n      pdev->pClass->SOF(pdev);\r\n    }\r\n  }\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n* @brief  USBD_IsoINIncomplete \r\n*         Handle iso in incomplete event\r\n* @param  pdev: device instance\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef  *pdev, uint8_t epnum)\r\n{\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n* @brief  USBD_IsoOUTIncomplete \r\n*         Handle iso out incomplete event\r\n* @param  pdev: device instance\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef  *pdev, uint8_t epnum)\r\n{\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n* @brief  USBD_DevConnected \r\n*         Handle device connection event\r\n* @param  pdev: device instance\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef  *pdev)\r\n{\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n* @brief  USBD_DevDisconnected \r\n*         Handle device disconnection event\r\n* @param  pdev: device instance\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef  *pdev)\r\n{\r\n  /* Free Class Resources */\r\n  pdev->dev_state = USBD_STATE_DEFAULT;\r\n  pdev->pClass->DeInit(pdev, pdev->dev_config);  \r\n   \r\n  return USBD_OK;\r\n}\r\n/**\r\n* @}\r\n*/ \r\n\r\n\r\n/**\r\n* @}\r\n*/ \r\n\r\n\r\n/**\r\n* @}\r\n*/ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_req.c\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015 \r\n  * @brief   This file provides the standard USB requests following chapter 9.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_ctlreq.h\"\r\n#include \"usbd_ioreq.h\"\r\n\r\n\r\n/** @addtogroup STM32_USBD_STATE_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n\r\n\r\n/** @defgroup USBD_REQ \r\n  * @brief USB standard requests module\r\n  * @{\r\n  */ \r\n\r\n/** @defgroup USBD_REQ_Private_TypesDefinitions\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_REQ_Private_Defines\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_REQ_Private_Macros\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_REQ_Private_Variables\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_REQ_Private_FunctionPrototypes\r\n  * @{\r\n  */ \r\nstatic void USBD_GetDescriptor(USBD_HandleTypeDef *pdev , \r\n                               USBD_SetupReqTypedef *req);\r\n\r\nstatic void USBD_SetAddress(USBD_HandleTypeDef *pdev , \r\n                            USBD_SetupReqTypedef *req);\r\n\r\nstatic void USBD_SetConfig(USBD_HandleTypeDef *pdev , \r\n                           USBD_SetupReqTypedef *req);\r\n\r\nstatic void USBD_GetConfig(USBD_HandleTypeDef *pdev , \r\n                           USBD_SetupReqTypedef *req);\r\n\r\nstatic void USBD_GetStatus(USBD_HandleTypeDef *pdev , \r\n                           USBD_SetupReqTypedef *req);\r\n\r\nstatic void USBD_SetFeature(USBD_HandleTypeDef *pdev , \r\n                            USBD_SetupReqTypedef *req);\r\n\r\nstatic void USBD_ClrFeature(USBD_HandleTypeDef *pdev , \r\n                            USBD_SetupReqTypedef *req);\r\n\r\nstatic uint8_t USBD_GetLen(uint8_t *buf);\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_REQ_Private_Functions\r\n  * @{\r\n  */ \r\n\r\n\r\n/**\r\n* @brief  USBD_StdDevReq\r\n*         Handle standard usb device requests\r\n* @param  pdev: device instance\r\n* @param  req: usb request\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef  USBD_StdDevReq (USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef  *req)\r\n{\r\n  USBD_StatusTypeDef ret = USBD_OK;  \r\n  \r\n  switch (req->bRequest) \r\n  {\r\n  case USB_REQ_GET_DESCRIPTOR: \r\n    \r\n    USBD_GetDescriptor (pdev, req) ;\r\n    break;\r\n    \r\n  case USB_REQ_SET_ADDRESS:                      \r\n    USBD_SetAddress(pdev, req);\r\n    break;\r\n    \r\n  case USB_REQ_SET_CONFIGURATION:                    \r\n    USBD_SetConfig (pdev , req);\r\n    break;\r\n    \r\n  case USB_REQ_GET_CONFIGURATION:                 \r\n    USBD_GetConfig (pdev , req);\r\n    break;\r\n    \r\n  case USB_REQ_GET_STATUS:                                  \r\n    USBD_GetStatus (pdev , req);\r\n    break;\r\n    \r\n    \r\n  case USB_REQ_SET_FEATURE:   \r\n    USBD_SetFeature (pdev , req);    \r\n    break;\r\n    \r\n  case USB_REQ_CLEAR_FEATURE:                                   \r\n    USBD_ClrFeature (pdev , req);\r\n    break;\r\n    \r\n  default:  \r\n    USBD_CtlError(pdev , req);\r\n    break;\r\n  }\r\n  \r\n  return ret;\r\n}\r\n\r\n/**\r\n* @brief  USBD_StdItfReq\r\n*         Handle standard usb interface requests\r\n* @param  pdev: device instance\r\n* @param  req: usb request\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef  USBD_StdItfReq (USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef  *req)\r\n{\r\n  USBD_StatusTypeDef ret = USBD_OK; \r\n  \r\n  switch (pdev->dev_state) \r\n  {\r\n  case USBD_STATE_CONFIGURED:\r\n    \r\n    if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES) \r\n    {\r\n      pdev->pClass->Setup (pdev, req); \r\n      \r\n      if((req->wLength == 0)&& (ret == USBD_OK))\r\n      {\r\n         USBD_CtlSendStatus(pdev);\r\n      }\r\n    } \r\n    else \r\n    {                                               \r\n       USBD_CtlError(pdev , req);\r\n    }\r\n    break;\r\n    \r\n  default:\r\n     USBD_CtlError(pdev , req);\r\n    break;\r\n  }\r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n* @brief  USBD_StdEPReq\r\n*         Handle standard usb endpoint requests\r\n* @param  pdev: device instance\r\n* @param  req: usb request\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef  USBD_StdEPReq (USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef  *req)\r\n{\r\n  \r\n  uint8_t   ep_addr;\r\n  USBD_StatusTypeDef ret = USBD_OK; \r\n  USBD_EndpointTypeDef   *pep;\r\n  ep_addr  = LOBYTE(req->wIndex);   \r\n  \r\n  /* Check if it is a class request */\r\n  if ((req->bmRequest & 0x60) == 0x20)\r\n  {\r\n    pdev->pClass->Setup (pdev, req);\r\n    \r\n    return USBD_OK;\r\n  }\r\n  \r\n  switch (req->bRequest) \r\n  {\r\n    \r\n  case USB_REQ_SET_FEATURE :\r\n    \r\n    switch (pdev->dev_state) \r\n    {\r\n    case USBD_STATE_ADDRESSED:          \r\n      if ((ep_addr != 0x00) && (ep_addr != 0x80)) \r\n      {\r\n        USBD_LL_StallEP(pdev , ep_addr);\r\n      }\r\n      break;\t\r\n      \r\n    case USBD_STATE_CONFIGURED:   \r\n      if (req->wValue == USB_FEATURE_EP_HALT)\r\n      {\r\n        if ((ep_addr != 0x00) && (ep_addr != 0x80)) \r\n        { \r\n          USBD_LL_StallEP(pdev , ep_addr);\r\n          \r\n        }\r\n      }\r\n      pdev->pClass->Setup (pdev, req);   \r\n      USBD_CtlSendStatus(pdev);\r\n      \r\n      break;\r\n      \r\n    default:                         \r\n      USBD_CtlError(pdev , req);\r\n      break;    \r\n    }\r\n    break;\r\n    \r\n  case USB_REQ_CLEAR_FEATURE :\r\n    \r\n    switch (pdev->dev_state) \r\n    {\r\n    case USBD_STATE_ADDRESSED:          \r\n      if ((ep_addr != 0x00) && (ep_addr != 0x80)) \r\n      {\r\n        USBD_LL_StallEP(pdev , ep_addr);\r\n      }\r\n      break;\t\r\n      \r\n    case USBD_STATE_CONFIGURED:   \r\n      if (req->wValue == USB_FEATURE_EP_HALT)\r\n      {\r\n        if ((ep_addr & 0x7F) != 0x00) \r\n        {        \r\n          USBD_LL_ClearStallEP(pdev , ep_addr);\r\n          pdev->pClass->Setup (pdev, req);\r\n        }\r\n        USBD_CtlSendStatus(pdev);\r\n      }\r\n      break;\r\n      \r\n    default:                         \r\n      USBD_CtlError(pdev , req);\r\n      break;    \r\n    }\r\n    break;\r\n    \r\n  case USB_REQ_GET_STATUS:                  \r\n    switch (pdev->dev_state) \r\n    {\r\n    case USBD_STATE_ADDRESSED:          \r\n      if ((ep_addr & 0x7F) != 0x00) \r\n      {\r\n        USBD_LL_StallEP(pdev , ep_addr);\r\n      }\r\n      break;\t\r\n      \r\n    case USBD_STATE_CONFIGURED:\r\n      pep = ((ep_addr & 0x80) == 0x80) ? &pdev->ep_in[ep_addr & 0x7F]:\\\r\n                                         &pdev->ep_out[ep_addr & 0x7F];\r\n      if(USBD_LL_IsStallEP(pdev, ep_addr))\r\n      {\r\n        pep->status = 0x0001;     \r\n      }\r\n      else\r\n      {\r\n        pep->status = 0x0000;  \r\n      }\r\n      \r\n      USBD_CtlSendData (pdev,\r\n                        (uint8_t *)&pep->status,\r\n                        2);\r\n      break;\r\n      \r\n    default:                         \r\n      USBD_CtlError(pdev , req);\r\n      break;\r\n    }\r\n    break;\r\n    \r\n  default:\r\n    break;\r\n  }\r\n  return ret;\r\n}\r\n/**\r\n* @brief  USBD_GetDescriptor\r\n*         Handle Get Descriptor requests\r\n* @param  pdev: device instance\r\n* @param  req: usb request\r\n* @retval status\r\n*/\r\nstatic void USBD_GetDescriptor(USBD_HandleTypeDef *pdev , \r\n                               USBD_SetupReqTypedef *req)\r\n{\r\n  uint16_t len;\r\n  uint8_t *pbuf;\r\n  \r\n    \r\n  switch (req->wValue >> 8)\r\n  { \r\n#if (USBD_LPM_ENABLED == 1)\r\n  case USB_DESC_TYPE_BOS:\r\n    pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len);\r\n    break;\r\n#endif    \r\n  case USB_DESC_TYPE_DEVICE:\r\n    pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len);\r\n    break;\r\n    \r\n  case USB_DESC_TYPE_CONFIGURATION:     \r\n    if(pdev->dev_speed == USBD_SPEED_HIGH )   \r\n    {\r\n      pbuf   = (uint8_t *)pdev->pClass->GetHSConfigDescriptor(&len);\r\n      pbuf[1] = USB_DESC_TYPE_CONFIGURATION;\r\n    }\r\n    else\r\n    {\r\n      pbuf   = (uint8_t *)pdev->pClass->GetFSConfigDescriptor(&len);\r\n      pbuf[1] = USB_DESC_TYPE_CONFIGURATION;\r\n    }\r\n    break;\r\n    \r\n  case USB_DESC_TYPE_STRING:\r\n    switch ((uint8_t)(req->wValue))\r\n    {\r\n    case USBD_IDX_LANGID_STR:\r\n     pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len);        \r\n      break;\r\n      \r\n    case USBD_IDX_MFC_STR:\r\n      pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len);\r\n      break;\r\n      \r\n    case USBD_IDX_PRODUCT_STR:\r\n      pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len);\r\n      break;\r\n      \r\n    case USBD_IDX_SERIAL_STR:\r\n      pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len);\r\n      break;\r\n      \r\n    case USBD_IDX_CONFIG_STR:\r\n      pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len);\r\n      break;\r\n      \r\n    case USBD_IDX_INTERFACE_STR:\r\n      pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len);\r\n      break;\r\n      \r\n    default:\r\n#if (USBD_SUPPORT_USER_STRING == 1)\r\n      pbuf = pdev->pClass->GetUsrStrDescriptor(pdev, (req->wValue) , &len);\r\n      break;\r\n#else      \r\n       USBD_CtlError(pdev , req);\r\n      return;\r\n#endif   \r\n    }\r\n    break;\r\n  case USB_DESC_TYPE_DEVICE_QUALIFIER:                   \r\n\r\n    if(pdev->dev_speed == USBD_SPEED_HIGH  )   \r\n    {\r\n      pbuf   = (uint8_t *)pdev->pClass->GetDeviceQualifierDescriptor(&len);\r\n      break;\r\n    }\r\n    else\r\n    {\r\n      USBD_CtlError(pdev , req);\r\n      return;\r\n    } \r\n\r\n  case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION:\r\n    if(pdev->dev_speed == USBD_SPEED_HIGH  )   \r\n    {\r\n      pbuf   = (uint8_t *)pdev->pClass->GetOtherSpeedConfigDescriptor(&len);\r\n      pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION;\r\n      break; \r\n    }\r\n    else\r\n    {\r\n      USBD_CtlError(pdev , req);\r\n      return;\r\n    }\r\n\r\n  default: \r\n     USBD_CtlError(pdev , req);\r\n    return;\r\n  }\r\n  \r\n  if((len != 0)&& (req->wLength != 0))\r\n  {\r\n    \r\n    len = MIN(len , req->wLength);\r\n    \r\n    USBD_CtlSendData (pdev, \r\n                      pbuf,\r\n                      len);\r\n  }\r\n  \r\n}\r\n\r\n/**\r\n* @brief  USBD_SetAddress\r\n*         Set device address\r\n* @param  pdev: device instance\r\n* @param  req: usb request\r\n* @retval status\r\n*/\r\nstatic void USBD_SetAddress(USBD_HandleTypeDef *pdev , \r\n                            USBD_SetupReqTypedef *req)\r\n{\r\n  uint8_t  dev_addr; \r\n  \r\n  if ((req->wIndex == 0) && (req->wLength == 0)) \r\n  {\r\n    dev_addr = (uint8_t)(req->wValue) & 0x7F;     \r\n    \r\n    if (pdev->dev_state == USBD_STATE_CONFIGURED) \r\n    {\r\n      USBD_CtlError(pdev , req);\r\n    } \r\n    else \r\n    {\r\n      pdev->dev_address = dev_addr;\r\n      USBD_LL_SetUSBAddress(pdev, dev_addr);               \r\n      USBD_CtlSendStatus(pdev);                         \r\n      \r\n      if (dev_addr != 0) \r\n      {\r\n        pdev->dev_state  = USBD_STATE_ADDRESSED;\r\n      } \r\n      else \r\n      {\r\n        pdev->dev_state  = USBD_STATE_DEFAULT; \r\n      }\r\n    }\r\n  } \r\n  else \r\n  {\r\n     USBD_CtlError(pdev , req);                        \r\n  } \r\n}\r\n\r\n/**\r\n* @brief  USBD_SetConfig\r\n*         Handle Set device configuration request\r\n* @param  pdev: device instance\r\n* @param  req: usb request\r\n* @retval status\r\n*/\r\nstatic void USBD_SetConfig(USBD_HandleTypeDef *pdev , \r\n                           USBD_SetupReqTypedef *req)\r\n{\r\n  \r\n  static uint8_t  cfgidx;\r\n  \r\n  cfgidx = (uint8_t)(req->wValue);                 \r\n  \r\n  if (cfgidx > USBD_MAX_NUM_CONFIGURATION ) \r\n  {            \r\n     USBD_CtlError(pdev , req);                              \r\n  } \r\n  else \r\n  {\r\n    switch (pdev->dev_state) \r\n    {\r\n    case USBD_STATE_ADDRESSED:\r\n      if (cfgidx) \r\n      {                                \t\t\t   \t\t\t\t\t\t\t   \t\t\t\t\t\t\t   \t\t\t\t\r\n        pdev->dev_config = cfgidx;\r\n        pdev->dev_state = USBD_STATE_CONFIGURED;\r\n        if(USBD_SetClassConfig(pdev , cfgidx) == USBD_FAIL)\r\n        {\r\n          USBD_CtlError(pdev , req);  \r\n          return;\r\n        }\r\n        USBD_CtlSendStatus(pdev);\r\n      }\r\n      else \r\n      {\r\n         USBD_CtlSendStatus(pdev);\r\n      }\r\n      break;\r\n      \r\n    case USBD_STATE_CONFIGURED:\r\n      if (cfgidx == 0) \r\n      {                           \r\n        pdev->dev_state = USBD_STATE_ADDRESSED;\r\n        pdev->dev_config = cfgidx;          \r\n        USBD_ClrClassConfig(pdev , cfgidx);\r\n        USBD_CtlSendStatus(pdev);\r\n        \r\n      } \r\n      else  if (cfgidx != pdev->dev_config) \r\n      {\r\n        /* Clear old configuration */\r\n        USBD_ClrClassConfig(pdev , pdev->dev_config);\r\n        \r\n        /* set new configuration */\r\n        pdev->dev_config = cfgidx;\r\n        if(USBD_SetClassConfig(pdev , cfgidx) == USBD_FAIL)\r\n        {\r\n          USBD_CtlError(pdev , req);  \r\n          return;\r\n        }\r\n        USBD_CtlSendStatus(pdev);\r\n      }\r\n      else\r\n      {\r\n        USBD_CtlSendStatus(pdev);\r\n      }\r\n      break;\r\n      \r\n    default:\t\t\t\t\t\r\n       USBD_CtlError(pdev , req);                     \r\n      break;\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n* @brief  USBD_GetConfig\r\n*         Handle Get device configuration request\r\n* @param  pdev: device instance\r\n* @param  req: usb request\r\n* @retval status\r\n*/\r\nstatic void USBD_GetConfig(USBD_HandleTypeDef *pdev , \r\n                           USBD_SetupReqTypedef *req)\r\n{\r\n\r\n  if (req->wLength != 1) \r\n  {                   \r\n     USBD_CtlError(pdev , req);\r\n  }\r\n  else \r\n  {\r\n    switch (pdev->dev_state )  \r\n    {\r\n    case USBD_STATE_ADDRESSED:                     \r\n      pdev->dev_default_config = 0;\r\n      USBD_CtlSendData (pdev, \r\n                        (uint8_t *)&pdev->dev_default_config,\r\n                        1);\r\n      break;\r\n      \r\n    case USBD_STATE_CONFIGURED:   \r\n      \r\n      USBD_CtlSendData (pdev, \r\n                        (uint8_t *)&pdev->dev_config,\r\n                        1);\r\n      break;\r\n      \r\n    default:\r\n       USBD_CtlError(pdev , req);\r\n      break;\r\n    }\r\n  }\r\n}\r\n\r\n/**\r\n* @brief  USBD_GetStatus\r\n*         Handle Get Status request\r\n* @param  pdev: device instance\r\n* @param  req: usb request\r\n* @retval status\r\n*/\r\nstatic void USBD_GetStatus(USBD_HandleTypeDef *pdev , \r\n                           USBD_SetupReqTypedef *req)\r\n{\r\n  \r\n    \r\n  switch (pdev->dev_state) \r\n  {\r\n  case USBD_STATE_ADDRESSED:\r\n  case USBD_STATE_CONFIGURED:\r\n    \r\n#if ( USBD_SELF_POWERED == 1)\r\n    pdev->dev_config_status = USB_CONFIG_SELF_POWERED;                                  \r\n#else\r\n    pdev->dev_config_status = 0;                                   \r\n#endif\r\n                      \r\n    if (pdev->dev_remote_wakeup) \r\n    {\r\n       pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP;                                \r\n    }\r\n    \r\n    USBD_CtlSendData (pdev, \r\n                      (uint8_t *)& pdev->dev_config_status,\r\n                      2);\r\n    break;\r\n    \r\n  default :\r\n    USBD_CtlError(pdev , req);                        \r\n    break;\r\n  }\r\n}\r\n\r\n\r\n/**\r\n* @brief  USBD_SetFeature\r\n*         Handle Set device feature request\r\n* @param  pdev: device instance\r\n* @param  req: usb request\r\n* @retval status\r\n*/\r\nstatic void USBD_SetFeature(USBD_HandleTypeDef *pdev , \r\n                            USBD_SetupReqTypedef *req)\r\n{\r\n\r\n  if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)\r\n  {\r\n    pdev->dev_remote_wakeup = 1;  \r\n    pdev->pClass->Setup (pdev, req);   \r\n    USBD_CtlSendStatus(pdev);\r\n  }\r\n\r\n}\r\n\r\n\r\n/**\r\n* @brief  USBD_ClrFeature\r\n*         Handle clear device feature request\r\n* @param  pdev: device instance\r\n* @param  req: usb request\r\n* @retval status\r\n*/\r\nstatic void USBD_ClrFeature(USBD_HandleTypeDef *pdev , \r\n                            USBD_SetupReqTypedef *req)\r\n{\r\n  switch (pdev->dev_state)\r\n  {\r\n  case USBD_STATE_ADDRESSED:\r\n  case USBD_STATE_CONFIGURED:\r\n    if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) \r\n    {\r\n      pdev->dev_remote_wakeup = 0; \r\n      pdev->pClass->Setup (pdev, req);   \r\n      USBD_CtlSendStatus(pdev);\r\n    }\r\n    break;\r\n    \r\n  default :\r\n     USBD_CtlError(pdev , req);\r\n    break;\r\n  }\r\n}\r\n\r\n/**\r\n* @brief  USBD_ParseSetupRequest \r\n*         Copy buffer into setup structure\r\n* @param  pdev: device instance\r\n* @param  req: usb request\r\n* @retval None\r\n*/\r\n\r\nvoid USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata)\r\n{\r\n  req->bmRequest     = *(uint8_t *)  (pdata);\r\n  req->bRequest      = *(uint8_t *)  (pdata +  1);\r\n  req->wValue        = SWAPBYTE      (pdata +  2);\r\n  req->wIndex        = SWAPBYTE      (pdata +  4);\r\n  req->wLength       = SWAPBYTE      (pdata +  6);\r\n\r\n}\r\n\r\n/**\r\n* @brief  USBD_CtlError \r\n*         Handle USB low level Error\r\n* @param  pdev: device instance\r\n* @param  req: usb request\r\n* @retval None\r\n*/\r\n\r\nvoid USBD_CtlError( USBD_HandleTypeDef *pdev ,\r\n                            USBD_SetupReqTypedef *req)\r\n{\r\n  USBD_LL_StallEP(pdev , 0x80);\r\n  USBD_LL_StallEP(pdev , 0);\r\n}\r\n\r\n\r\n/**\r\n  * @brief  USBD_GetString\r\n  *         Convert Ascii string into unicode one\r\n  * @param  desc : descriptor buffer\r\n  * @param  unicode : Formatted string buffer (unicode)\r\n  * @param  len : descriptor length\r\n  * @retval None\r\n  */\r\nvoid USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len)\r\n{\r\n  uint8_t idx = 0;\r\n  \r\n  if (desc != NULL) \r\n  {\r\n    *len =  USBD_GetLen(desc) * 2 + 2;    \r\n    unicode[idx++] = *len;\r\n    unicode[idx++] =  USB_DESC_TYPE_STRING;\r\n    \r\n    while (*desc != '\\0') \r\n    {\r\n      unicode[idx++] = *desc++;\r\n      unicode[idx++] =  0x00;\r\n    }\r\n  } \r\n}\r\n\r\n/**\r\n  * @brief  USBD_GetLen\r\n  *         return the string length\r\n   * @param  buf : pointer to the ascii string buffer\r\n  * @retval string length\r\n  */\r\nstatic uint8_t USBD_GetLen(uint8_t *buf)\r\n{\r\n    uint8_t  len = 0;\r\n\r\n    while (*buf != '\\0') \r\n    {\r\n        len++;\r\n        buf++;\r\n    }\r\n\r\n    return len;\r\n}\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/lib/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c",
    "content": "/**\r\n  ******************************************************************************\r\n  * @file    usbd_ioreq.c\r\n  * @author  MCD Application Team\r\n  * @version V2.4.1\r\n  * @date    19-June-2015\r\n  * @brief   This file provides the IO requests APIs for control endpoints.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\r\n  *\r\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\r\n  * You may not use this file except in compliance with the License.\r\n  * You may obtain a copy of the License at:\r\n  *\r\n  *        http://www.st.com/software_license_agreement_liberty_v2\r\n  *\r\n  * Unless required by applicable law or agreed to in writing, software \r\n  * distributed under the License is distributed on an \"AS IS\" BASIS, \r\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n  * See the License for the specific language governing permissions and\r\n  * limitations under the License.\r\n  *\r\n  ******************************************************************************\r\n  */ \r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"usbd_ioreq.h\"\r\n\r\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\r\n  * @{\r\n  */\r\n\r\n\r\n/** @defgroup USBD_IOREQ \r\n  * @brief control I/O requests module\r\n  * @{\r\n  */ \r\n\r\n/** @defgroup USBD_IOREQ_Private_TypesDefinitions\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_IOREQ_Private_Defines\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_IOREQ_Private_Macros\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_IOREQ_Private_Variables\r\n  * @{\r\n  */ \r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_IOREQ_Private_FunctionPrototypes\r\n  * @{\r\n  */ \r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/** @defgroup USBD_IOREQ_Private_Functions\r\n  * @{\r\n  */ \r\n\r\n/**\r\n* @brief  USBD_CtlSendData\r\n*         send data on the ctl pipe\r\n* @param  pdev: device instance\r\n* @param  buff: pointer to data buffer\r\n* @param  len: length of data to be sent\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef  USBD_CtlSendData (USBD_HandleTypeDef  *pdev, \r\n                               uint8_t *pbuf,\r\n                               uint16_t len)\r\n{\r\n  /* Set EP0 State */\r\n  pdev->ep0_state          = USBD_EP0_DATA_IN;                                      \r\n  pdev->ep_in[0].total_length = len;\r\n  pdev->ep_in[0].rem_length   = len;\r\n /* Start the transfer */\r\n  USBD_LL_Transmit (pdev, 0x00, pbuf, len);  \r\n  \r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n* @brief  USBD_CtlContinueSendData\r\n*         continue sending data on the ctl pipe\r\n* @param  pdev: device instance\r\n* @param  buff: pointer to data buffer\r\n* @param  len: length of data to be sent\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef  USBD_CtlContinueSendData (USBD_HandleTypeDef  *pdev, \r\n                                       uint8_t *pbuf,\r\n                                       uint16_t len)\r\n{\r\n /* Start the next transfer */\r\n  USBD_LL_Transmit (pdev, 0x00, pbuf, len);   \r\n  \r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n* @brief  USBD_CtlPrepareRx\r\n*         receive data on the ctl pipe\r\n* @param  pdev: device instance\r\n* @param  buff: pointer to data buffer\r\n* @param  len: length of data to be received\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef  USBD_CtlPrepareRx (USBD_HandleTypeDef  *pdev,\r\n                                  uint8_t *pbuf,                                  \r\n                                  uint16_t len)\r\n{\r\n  /* Set EP0 State */\r\n  pdev->ep0_state = USBD_EP0_DATA_OUT; \r\n  pdev->ep_out[0].total_length = len;\r\n  pdev->ep_out[0].rem_length   = len;\r\n  /* Start the transfer */\r\n  USBD_LL_PrepareReceive (pdev,\r\n                          0,\r\n                          pbuf,\r\n                         len);\r\n  \r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n* @brief  USBD_CtlContinueRx\r\n*         continue receive data on the ctl pipe\r\n* @param  pdev: device instance\r\n* @param  buff: pointer to data buffer\r\n* @param  len: length of data to be received\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef  USBD_CtlContinueRx (USBD_HandleTypeDef  *pdev, \r\n                                          uint8_t *pbuf,                                          \r\n                                          uint16_t len)\r\n{\r\n\r\n  USBD_LL_PrepareReceive (pdev,\r\n                          0,                     \r\n                          pbuf,                         \r\n                          len);\r\n  return USBD_OK;\r\n}\r\n/**\r\n* @brief  USBD_CtlSendStatus\r\n*         send zero lzngth packet on the ctl pipe\r\n* @param  pdev: device instance\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef  USBD_CtlSendStatus (USBD_HandleTypeDef  *pdev)\r\n{\r\n\r\n  /* Set EP0 State */\r\n  pdev->ep0_state = USBD_EP0_STATUS_IN;\r\n  \r\n /* Start the transfer */\r\n  USBD_LL_Transmit (pdev, 0x00, NULL, 0);   \r\n  \r\n  return USBD_OK;\r\n}\r\n\r\n/**\r\n* @brief  USBD_CtlReceiveStatus\r\n*         receive zero lzngth packet on the ctl pipe\r\n* @param  pdev: device instance\r\n* @retval status\r\n*/\r\nUSBD_StatusTypeDef  USBD_CtlReceiveStatus (USBD_HandleTypeDef  *pdev)\r\n{\r\n  /* Set EP0 State */\r\n  pdev->ep0_state = USBD_EP0_STATUS_OUT; \r\n  \r\n /* Start the transfer */  \r\n  USBD_LL_PrepareReceive ( pdev,\r\n                    0,\r\n                    NULL,\r\n                    0);  \r\n\r\n  return USBD_OK;\r\n}\r\n\r\n\r\n/**\r\n* @brief  USBD_GetRxCount\r\n*         returns the received data length\r\n* @param  pdev: device instance\r\n* @param  ep_addr: endpoint address\r\n* @retval Rx Data blength\r\n*/\r\nuint16_t  USBD_GetRxCount (USBD_HandleTypeDef  *pdev , uint8_t ep_addr)\r\n{\r\n  return USBD_LL_GetRxDataSize(pdev, ep_addr);\r\n}\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n\r\n/**\r\n  * @}\r\n  */ \r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
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SemiHidden=\"true\"\r\n   UnhideWhenUsed=\"true\" QFormat=\"true\" Name=\"TOC Heading\"/>\r\n </w:LatentStyles>\r\n</xml><![endif]-->\r\n\r\n<style>\r\n<!--\r\n /* Font Definitions */\r\n @font-face\r\n\t{font-family:\"Cambria Math\";\r\n\tpanose-1:2 4 5 3 5 4 6 3 2 4;\r\n\tmso-font-charset:1;\r\n\tmso-generic-font-family:roman;\r\n\tmso-font-format:other;\r\n\tmso-font-pitch:variable;\r\n\tmso-font-signature:0 0 0 0 0 0;}\r\n@font-face\r\n\t{font-family:Calibri;\r\n\tpanose-1:2 15 5 2 2 2 4 3 2 4;\r\n\tmso-font-charset:0;\r\n\tmso-generic-font-family:swiss;\r\n\tmso-font-pitch:variable;\r\n\tmso-font-signature:-1610611985 1073750139 0 0 159 0;}\r\n@font-face\r\n\t{font-family:Tahoma;\r\n\tpanose-1:2 11 6 4 3 5 4 4 2 4;\r\n\tmso-font-charset:0;\r\n\tmso-generic-font-family:swiss;\r\n\tmso-font-pitch:variable;\r\n\tmso-font-signature:1627400839 -2147483648 8 0 66047 0;}\r\n@font-face\r\n\t{font-family:Verdana;\r\n\tpanose-1:2 11 6 4 3 5 4 4 2 4;\r\n\tmso-font-charset:0;\r\n\tmso-generic-font-family:swiss;\r\n\tmso-font-pitch:variable;\r\n\tmso-font-signature:536871559 0 0 0 415 0;}\r\n /* Style Definitions */\r\n p.MsoNormal, li.MsoNormal, div.MsoNormal\r\n\t{mso-style-unhide:no;\r\n\tmso-style-qformat:yes;\r\n\tmso-style-parent:\"\";\r\n\tmargin:0in;\r\n\tmargin-bottom:.0001pt;\r\n\tmso-pagination:widow-orphan;\r\n\tfont-size:12.0pt;\r\n\tfont-family:\"Times New Roman\",\"serif\";\r\n\tmso-fareast-font-family:\"Times New Roman\";}\r\nh1\r\n\t{mso-style-unhide:no;\r\n\tmso-style-qformat:yes;\r\n\tmso-style-link:\"Heading 1 Char\";\r\n\tmso-margin-top-alt:auto;\r\n\tmargin-right:0in;\r\n\tmso-margin-bottom-alt:auto;\r\n\tmargin-left:0in;\r\n\tmso-pagination:widow-orphan;\r\n\tmso-outline-level:1;\r\n\tfont-size:24.0pt;\r\n\tfont-family:\"Times New Roman\",\"serif\";\r\n\tmso-fareast-font-family:\"Times New Roman\";\r\n\tmso-fareast-theme-font:minor-fareast;\r\n\tfont-weight:bold;}\r\nh2\r\n\t{mso-style-unhide:no;\r\n\tmso-style-qformat:yes;\r\n\tmso-style-link:\"Heading 2 Char\";\r\n\tmso-style-next:Normal;\r\n\tmargin-top:12.0pt;\r\n\tmargin-right:0in;\r\n\tmargin-bottom:3.0pt;\r\n\tmargin-left:0in;\r\n\tmso-pagination:widow-orphan;\r\n\tpage-break-after:avoid;\r\n\tmso-outline-level:2;\r\n\tfont-size:14.0pt;\r\n\tfont-family:\"Arial\",\"sans-serif\";\r\n\tmso-fareast-font-family:\"Times New Roman\";\r\n\tmso-fareast-theme-font:minor-fareast;\r\n\tfont-weight:bold;\r\n\tfont-style:italic;}\r\nh3\r\n\t{mso-style-unhide:no;\r\n\tmso-style-qformat:yes;\r\n\tmso-style-link:\"Heading 3 Char\";\r\n\tmso-margin-top-alt:auto;\r\n\tmargin-right:0in;\r\n\tmso-margin-bottom-alt:auto;\r\n\tmargin-left:0in;\r\n\tmso-pagination:widow-orphan;\r\n\tmso-outline-level:3;\r\n\tfont-size:13.5pt;\r\n\tfont-family:\"Times New Roman\",\"serif\";\r\n\tmso-fareast-font-family:\"Times New Roman\";\r\n\tmso-fareast-theme-font:minor-fareast;\r\n\tfont-weight:bold;}\r\na:link, span.MsoHyperlink\r\n\t{mso-style-unhide:no;\r\n\tcolor:blue;\r\n\ttext-decoration:underline;\r\n\ttext-underline:single;}\r\na:visited, span.MsoHyperlinkFollowed\r\n\t{mso-style-unhide:no;\r\n\tcolor:blue;\r\n\ttext-decoration:underline;\r\n\ttext-underline:single;}\r\np\r\n\t{mso-style-unhide:no;\r\n\tmso-margin-top-alt:auto;\r\n\tmargin-right:0in;\r\n\tmso-margin-bottom-alt:auto;\r\n\tmargin-left:0in;\r\n\tmso-pagination:widow-orphan;\r\n\tfont-size:12.0pt;\r\n\tfont-family:\"Times New Roman\",\"serif\";\r\n\tmso-fareast-font-family:\"Times New Roman\";}\r\np.MsoAcetate, li.MsoAcetate, div.MsoAcetate\r\n\t{mso-style-unhide:no;\r\n\tmso-style-link:\"Balloon Text Char\";\r\n\tmargin:0in;\r\n\tmargin-bottom:.0001pt;\r\n\tmso-pagination:widow-orphan;\r\n\tfont-size:8.0pt;\r\n\tfont-family:\"Tahoma\",\"sans-serif\";\r\n\tmso-fareast-font-family:\"Times New Roman\";}\r\nspan.Heading1Char\r\n\t{mso-style-name:\"Heading 1 Char\";\r\n\tmso-style-unhide:no;\r\n\tmso-style-locked:yes;\r\n\tmso-style-link:\"Heading 1\";\r\n\tmso-ansi-font-size:14.0pt;\r\n\tmso-bidi-font-size:14.0pt;\r\n\tfont-family:\"Cambria\",\"serif\";\r\n\tmso-ascii-font-family:Cambria;\r\n\tmso-ascii-theme-font:major-latin;\r\n\tmso-fareast-font-family:\"Times New Roman\";\r\n\tmso-fareast-theme-font:major-fareast;\r\n\tmso-hansi-font-family:Cambria;\r\n\tmso-hansi-theme-font:major-latin;\r\n\tmso-bidi-font-family:\"Times New Roman\";\r\n\tmso-bidi-theme-font:major-bidi;\r\n\tcolor:#365F91;\r\n\tmso-themecolor:accent1;\r\n\tmso-themeshade:191;\r\n\tfont-weight:bold;}\r\nspan.Heading2Char\r\n\t{mso-style-name:\"Heading 2 Char\";\r\n\tmso-style-unhide:no;\r\n\tmso-style-locked:yes;\r\n\tmso-style-link:\"Heading 2\";\r\n\tmso-ansi-font-size:13.0pt;\r\n\tmso-bidi-font-size:13.0pt;\r\n\tfont-family:\"Cambria\",\"serif\";\r\n\tmso-ascii-font-family:Cambria;\r\n\tmso-ascii-theme-font:major-latin;\r\n\tmso-fareast-font-family:\"Times New Roman\";\r\n\tmso-fareast-theme-font:major-fareast;\r\n\tmso-hansi-font-family:Cambria;\r\n\tmso-hansi-theme-font:major-latin;\r\n\tmso-bidi-font-family:\"Times New Roman\";\r\n\tmso-bidi-theme-font:major-bidi;\r\n\tcolor:#4F81BD;\r\n\tmso-themecolor:accent1;\r\n\tfont-weight:bold;}\r\nspan.Heading3Char\r\n\t{mso-style-name:\"Heading 3 Char\";\r\n\tmso-style-unhide:no;\r\n\tmso-style-locked:yes;\r\n\tmso-style-link:\"Heading 3\";\r\n\tmso-ansi-font-size:12.0pt;\r\n\tmso-bidi-font-size:12.0pt;\r\n\tfont-family:\"Cambria\",\"serif\";\r\n\tmso-ascii-font-family:Cambria;\r\n\tmso-ascii-theme-font:major-latin;\r\n\tmso-fareast-font-family:\"Times New Roman\";\r\n\tmso-fareast-theme-font:major-fareast;\r\n\tmso-hansi-font-family:Cambria;\r\n\tmso-hansi-theme-font:major-latin;\r\n\tmso-bidi-font-family:\"Times New Roman\";\r\n\tmso-bidi-theme-font:major-bidi;\r\n\tcolor:#4F81BD;\r\n\tmso-themecolor:accent1;\r\n\tfont-weight:bold;}\r\nspan.BalloonTextChar\r\n\t{mso-style-name:\"Balloon Text Char\";\r\n\tmso-style-unhide:no;\r\n\tmso-style-locked:yes;\r\n\tmso-style-link:\"Balloon Text\";\r\n\tmso-ansi-font-size:8.0pt;\r\n\tmso-bidi-font-size:8.0pt;\r\n\tfont-family:\"Tahoma\",\"sans-serif\";\r\n\tmso-ascii-font-family:Tahoma;\r\n\tmso-hansi-font-family:Tahoma;\r\n\tmso-bidi-font-family:Tahoma;}\r\n.MsoChpDefault\r\n\t{mso-style-type:export-only;\r\n\tmso-default-props:yes;\r\n\tfont-size:10.0pt;\r\n\tmso-ansi-font-size:10.0pt;\r\n\tmso-bidi-font-size:10.0pt;}\r\n@page WordSection1\r\n\t{size:8.5in 11.0in;\r\n\tmargin:1.0in 1.25in 1.0in 1.25in;\r\n\tmso-header-margin:.5in;\r\n\tmso-footer-margin:.5in;\r\n\tmso-paper-source:0;}\r\ndiv.WordSection1\r\n\t{page:WordSection1;}\r\n /* List Definitions */\r\n @list l0\r\n\t{mso-list-id:62067358;\r\n\tmso-list-template-ids:-174943062;}\r\n@list l0:level1\r\n\t{mso-level-number-format:bullet;\r\n\tmso-level-text:\\F0B7;\r\n\tmso-level-tab-stop:.5in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;\r\n\tmso-ansi-font-size:10.0pt;\r\n\tfont-family:Symbol;}\r\n@list l0:level2\r\n\t{mso-level-tab-stop:1.0in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l0:level3\r\n\t{mso-level-tab-stop:1.5in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l0:level4\r\n\t{mso-level-tab-stop:2.0in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l0:level5\r\n\t{mso-level-tab-stop:2.5in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l0:level6\r\n\t{mso-level-tab-stop:3.0in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l0:level7\r\n\t{mso-level-tab-stop:3.5in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l0:level8\r\n\t{mso-level-tab-stop:4.0in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l0:level9\r\n\t{mso-level-tab-stop:4.5in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l1\r\n\t{mso-list-id:128015942;\r\n\tmso-list-template-ids:-90681214;}\r\n@list l1:level1\r\n\t{mso-level-tab-stop:.5in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l1:level2\r\n\t{mso-level-tab-stop:1.0in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l1:level3\r\n\t{mso-level-tab-stop:1.5in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l1:level4\r\n\t{mso-level-tab-stop:2.0in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l1:level5\r\n\t{mso-level-tab-stop:2.5in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l1:level6\r\n\t{mso-level-tab-stop:3.0in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l1:level7\r\n\t{mso-level-tab-stop:3.5in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l1:level8\r\n\t{mso-level-tab-stop:4.0in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l1:level9\r\n\t{mso-level-tab-stop:4.5in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l2\r\n\t{mso-list-id:216556000;\r\n\tmso-list-template-ids:925924412;}\r\n@list l2:level1\r\n\t{mso-level-number-format:bullet;\r\n\tmso-level-text:\\F0B7;\r\n\tmso-level-tab-stop:.5in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;\r\n\tmso-ansi-font-size:10.0pt;\r\n\tfont-family:Symbol;}\r\n@list l2:level2\r\n\t{mso-level-number-format:bullet;\r\n\tmso-level-text:\\F0B7;\r\n\tmso-level-tab-stop:1.0in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;\r\n\tmso-ansi-font-size:10.0pt;\r\n\tfont-family:Symbol;}\r\n@list l2:level3\r\n\t{mso-level-tab-stop:1.5in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l2:level4\r\n\t{mso-level-tab-stop:2.0in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l2:level5\r\n\t{mso-level-tab-stop:2.5in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l2:level6\r\n\t{mso-level-tab-stop:3.0in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l2:level7\r\n\t{mso-level-tab-stop:3.5in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l2:level8\r\n\t{mso-level-tab-stop:4.0in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l2:level9\r\n\t{mso-level-tab-stop:4.5in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l3\r\n\t{mso-list-id:562446694;\r\n\tmso-list-template-ids:913898366;}\r\n@list l3:level1\r\n\t{mso-level-number-format:bullet;\r\n\tmso-level-text:\\F0B7;\r\n\tmso-level-tab-stop:.5in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;\r\n\tmso-ansi-font-size:10.0pt;\r\n\tfont-family:Symbol;}\r\n@list l3:level2\r\n\t{mso-level-tab-stop:1.0in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l3:level3\r\n\t{mso-level-tab-stop:1.5in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l3:level4\r\n\t{mso-level-tab-stop:2.0in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l3:level5\r\n\t{mso-level-tab-stop:2.5in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l3:level6\r\n\t{mso-level-tab-stop:3.0in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l3:level7\r\n\t{mso-level-tab-stop:3.5in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l3:level8\r\n\t{mso-level-tab-stop:4.0in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l3:level9\r\n\t{mso-level-tab-stop:4.5in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l4\r\n\t{mso-list-id:797802132;\r\n\tmso-list-template-ids:-1971191336;}\r\n@list l4:level1\r\n\t{mso-level-tab-stop:.5in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l4:level2\r\n\t{mso-level-tab-stop:1.0in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l4:level3\r\n\t{mso-level-tab-stop:1.5in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l4:level4\r\n\t{mso-level-tab-stop:2.0in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l4:level5\r\n\t{mso-level-tab-stop:2.5in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l4:level6\r\n\t{mso-level-tab-stop:3.0in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l4:level7\r\n\t{mso-level-tab-stop:3.5in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l4:level8\r\n\t{mso-level-tab-stop:4.0in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l4:level9\r\n\t{mso-level-tab-stop:4.5in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l5\r\n\t{mso-list-id:907304066;\r\n\tmso-list-template-ids:1969781532;}\r\n@list l5:level1\r\n\t{mso-level-tab-stop:.5in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l5:level2\r\n\t{mso-level-tab-stop:1.0in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l5:level3\r\n\t{mso-level-tab-stop:1.5in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list l5:level4\r\n\t{mso-level-tab-stop:2.0in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\n@list 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l9:level9\r\n\t{mso-level-tab-stop:4.5in;\r\n\tmso-level-number-position:left;\r\n\ttext-indent:-.25in;}\r\nol\r\n\t{margin-bottom:0in;}\r\nul\r\n\t{margin-bottom:0in;}\r\n-->\r\n</style><!--[if gte mso 10]>\r\n<style>\r\n /* Style Definitions */\r\n table.MsoNormalTable\r\n\t{mso-style-name:\"Table Normal\";\r\n\tmso-tstyle-rowband-size:0;\r\n\tmso-tstyle-colband-size:0;\r\n\tmso-style-noshow:yes;\r\n\tmso-style-priority:99;\r\n\tmso-style-qformat:yes;\r\n\tmso-style-parent:\"\";\r\n\tmso-padding-alt:0in 5.4pt 0in 5.4pt;\r\n\tmso-para-margin:0in;\r\n\tmso-para-margin-bottom:.0001pt;\r\n\tmso-pagination:widow-orphan;\r\n\tfont-size:10.0pt;\r\n\tfont-family:\"Times New Roman\",\"serif\";}\r\n</style>\r\n<![endif]--><!--[if gte mso 9]><xml>\r\n <o:shapedefaults v:ext=\"edit\" spidmax=\"7170\"/>\r\n</xml><![endif]--><!--[if gte mso 9]><xml>\r\n <o:shapelayout v:ext=\"edit\">\r\n  <o:idmap v:ext=\"edit\" data=\"1\"/>\r\n </o:shapelayout></xml><![endif]--><meta content=\"MCD Application Team\" name=\"author\"></head><body style=\"\" link=\"blue\" vlink=\"blue\">\r\n\r\n<div class=\"WordSection1\">\r\n\r\n<p class=\"MsoNormal\"><span style=\"font-family: &quot;Arial&quot;,&quot;sans-serif&quot;;\"><o:p>&nbsp;</o:p></span></p>\r\n\r\n<div align=\"center\">\r\n\r\n<table class=\"MsoNormalTable\" style=\"width: 675pt;\" border=\"0\" cellpadding=\"0\" cellspacing=\"0\" width=\"900\">\r\n <tbody><tr style=\"\">\r\n  <td style=\"padding: 0in;\" valign=\"top\">\r\n  <table class=\"MsoNormalTable\" style=\"width: 675pt;\" border=\"0\" cellpadding=\"0\" cellspacing=\"0\" width=\"900\">\r\n   <tbody><tr style=\"\">\r\n    <td style=\"padding: 0in 5.4pt;\" valign=\"top\">\r\n    <p class=\"MsoNormal\"><span style=\"font-size: 8pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: blue;\"><a href=\"../../../Release_Notes.html\">Back to Release page</a></span><span style=\"font-size: 10pt;\"><o:p></o:p></span></p>\r\n    </td>\r\n   </tr>\r\n   <tr style=\"\">\r\n    <td style=\"padding: 1.5pt;\">\r\n    <h1 style=\"margin-bottom: 0.25in; text-align: center;\" align=\"center\"><span style=\"font-size: 20pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: rgb(51, 102, 255);\">Release Notes for STM32 USB Device Library</span><span style=\"font-size: 20pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\"><o:p></o:p></span></h1>\r\n    <p class=\"MsoNormal\" style=\"text-align: center;\" align=\"center\"><span style=\"font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;\">Copyright\r\n    2015 STMicroelectronics</span><span style=\"color: black;\"><u1:p></u1:p><o:p></o:p></span></p>\r\n    <p class=\"MsoNormal\" style=\"text-align: center;\" align=\"center\"><span style=\"font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;\"><img style=\"border: 0px solid ; width: 86px; height: 65px;\" alt=\"\" id=\"_x0000_i1026\" src=\"../../../_htmresc/st_logo.png\"></span><span style=\"font-size: 10pt;\"><o:p></o:p></span></p>\r\n    </td>\r\n   </tr>\r\n  </tbody></table>\r\n  <p class=\"MsoNormal\"><span style=\"font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; display: none;\"><o:p>&nbsp;</o:p></span></p>\r\n  <table class=\"MsoNormalTable\" style=\"width: 675pt;\" border=\"0\" cellpadding=\"0\" width=\"900\">\r\n   <tbody><tr style=\"\">\r\n    <td style=\"padding: 0in;\" valign=\"top\">\r\n    <h2 style=\"background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;\"><a name=\"History\"></a><span style=\"font-size: 12pt; color: white;\">Update History</span></h2>\r\n            <h3 style=\"background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 180px;\"><span style=\"font-size: 10pt; font-family: Arial; color: white;\">V2.4.1 / 19-June-2015<br>\r\n</span></h3>\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n            \r\n            \r\n            \r\n            \r\n            \r\n            \r\n            \r\n            <p class=\"MsoNormal\" style=\"margin: 4.5pt 0cm 4.5pt 18pt;\"><b style=\"\"><u><span style=\"font-size: 10pt; font-family: Verdana; color: black;\">Main\r\nChanges</span></u></b><u><span style=\"font-size: 10pt; font-family: Verdana; color: black;\"><o:p></o:p></span></u></p>\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n            \r\n            \r\n            \r\n            \r\n            \r\n            \r\n            \r\n            \r\n            \r\n            <ul style=\"margin-top: 0cm;\" type=\"square\">\r\n              <li><span style=\"font-size: 10pt; font-family: Verdana;\">CDC Class</span></li>\r\n              <ul>\r\n                <li><span style=\"font-size: 10pt; font-family: Verdana;\">usbd_cdc.c: comments update</span></li>\r\n              </ul>\r\n              <li><span style=\"font-size: 10pt; font-family: Verdana;\">MSC Class</span></li>\r\n              <ul>\r\n                <li><span style=\"font-size: 10pt; font-family: Verdana;\">usbd_msc_bot.h: update to be</span><span style=\"font-size: 10pt; font-family: Verdana;\"> C++ compliant</span></li>\r\n              </ul>\r\n              <li><span style=\"font-size: 10pt; font-family: Verdana;\">AUDIO Class</span></li>\r\n              <ul>\r\n                <li><span style=\"font-size: 10pt; font-family: Verdana;\">usbd_audio.c: fix issue when Host sends GetInterface command it gets a wrong value</span></li>\r\n              </ul>\r\n              <ul>\r\n                <li><span style=\"font-size: 10pt; font-family: Verdana;\">usbd_audio.c: remove useless management of DMA half transfer<br>\r\n                  </span></li>\r\n              </ul>\r\n            </ul>\r\n\r\n\r\n            \r\n            <h3 style=\"background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 180px;\"><span style=\"font-size: 10pt; font-family: Arial; color: white;\">V2.4.0 / 28-February-2015<br>\r\n</span></h3>\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n            \r\n            \r\n            \r\n            \r\n            \r\n            \r\n            <p class=\"MsoNormal\" style=\"margin: 4.5pt 0cm 4.5pt 18pt;\"><b style=\"\"><u><span style=\"font-size: 10pt; font-family: Verdana; color: black;\">Main\r\nChanges</span></u></b><u><span style=\"font-size: 10pt; font-family: Verdana; color: black;\"><o:p></o:p></span></u></p>\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n            \r\n            \r\n            \r\n            \r\n            \r\n            \r\n            \r\n            \r\n            <ul style=\"margin-top: 0cm;\" type=\"square\">\r\n              <li><span style=\"font-size: 10pt; font-family: Verdana;\">Core Driver</span></li>\r\n              <ul style=\"list-style-type: circle;\">\r\n                <li><span style=\"font-size: 10pt; font-family: Verdana;\">Add support of </span><span style=\"font-size: 10pt; font-family: Verdana;\"><span style=\"font-weight: bold; font-style: italic;\">Link Power Management (LPM)</span>: </span><span style=\"font-size: 10pt; font-family: Verdana;\">add new API <span style=\"font-style: italic;\">GetBOSDescriptor()</span>, that is used only if <span style=\"font-style: italic;\">USBD_LPM_ENABLED</span>  switch is enabled in usbd_conf.h file</span></li><li><span style=\"font-size: 10pt; font-family: Verdana;\">usbd_core.c:\r\nFix bug of unsupported premature Host Out stage during data In stage\r\n(ie. when endpoint 0 maximum data size is 8 and Host requests\r\nGetDeviceDescriptor for the first time)</span></li><li><span style=\"font-size: 10pt; font-family: Verdana;\">usbd_ctlreq.c: Fix bug of unsupported Endpoint Class requests (ie. Audio SetCurrent request for endpoint sampling rate setting)</span></li>\r\n              </ul>\r\n              <li><span style=\"font-size: 10pt; font-family: Verdana;\">HID Class</span></li>\r\n              <ul>\r\n                <li><span style=\"font-size: 10pt; font-family: Verdana;\">Updating Polling time API <span style=\"font-style: italic;\">USBD_HID_GetPollingInterval()</span> to query this period for HS and FS</span></li><li><span style=\"font-size: 10pt; font-family: Verdana;\">usbd_hid.c: Fix USBD_LL_CloseEP() function call in USBD_HID_DeInit() replacing endpoint size by endpoint address.</span></li>\r\n              </ul><li><span style=\"font-size: 10pt; font-family: Verdana;\">CDC Class</span></li><ul><li><span style=\"font-size: 10pt; font-family: Verdana;\">usbd_cdc.c:&nbsp;</span></li><ul><li><span style=\"font-size: 10pt; font-family: Verdana;\">Add missing GetInterface request management in USBD_CDC_Setup() function</span></li></ul><ul><li><span style=\"font-size: 10pt; font-family: Verdana;\">Update\r\nUSBD_CDC_Setup() function to allow correct user implementation of\r\nCDC_SET_CONTROL_LINE_STATE and similar no-data setup requests.<br></span></li></ul></ul>\r\n            </ul>\r\n\r\n            <h3 style=\"background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 180px;\"><span style=\"font-size: 10pt; font-family: Arial; color: white;\">V2.3.0 / 04-November-2014<br>\r\n</span></h3>\r\n\r\n\r\n\r\n\r\n\r\n\r\n            \r\n            \r\n            \r\n            \r\n            \r\n            <p class=\"MsoNormal\" style=\"margin: 4.5pt 0cm 4.5pt 18pt;\"><b style=\"\"><u><span style=\"font-size: 10pt; font-family: Verdana; color: black;\">Main\r\nChanges</span></u></b><u><span style=\"font-size: 10pt; font-family: Verdana; color: black;\"><o:p></o:p></span></u></p>\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n            \r\n            \r\n            \r\n            \r\n            \r\n            \r\n            \r\n            <ul style=\"margin-top: 0cm;\" type=\"square\">\r\n<li><span style=\"font-size: 10pt; font-family: Verdana;\">Update all drivers to be C++ compliant<br>\r\n</span></li>\r\n              <li><span style=\"font-size: 10pt; font-family: Verdana;\">CDC Class</span></li>\r\n              <ul>\r\n                <li><span style=\"font-size: 10pt; font-family: Verdana;\">usbd_cdc.c: fix clear flag issue in <span style=\"font-style: italic;\">USBD_CDC_TransmitPacket()</span> function</span></li>\r\n              </ul>\r\n              <ul>\r\n                <li><span style=\"font-size: 10pt; font-family: Verdana;\">usbd_cdc_if_template.c: </span><span style=\"font-size: 10pt; font-family: Verdana;\">update <span style=\"font-style: italic;\">TEMPLATE_Receive()</span> function header comment<br>\r\n                  </span></li>\r\n              </ul>\r\n<li><span style=\"font-size: 10pt; font-family: Verdana;\">Miscellaneous source code comments update</span></li>\r\n            </ul>\r\n<h3 style=\"background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 180px;\"><span style=\"font-size: 10pt; font-family: Arial; color: white;\">V2.2.0 / 13-June-2014</span></h3>\r\n\r\n\r\n\r\n\r\n\r\n            \r\n            \r\n            \r\n            \r\n            <p class=\"MsoNormal\" style=\"margin: 4.5pt 0cm 4.5pt 18pt;\"><b style=\"\"><u><span style=\"font-size: 10pt; font-family: Verdana; color: black;\">Main\r\nChanges</span></u></b><u><span style=\"font-size: 10pt; font-family: Verdana; color: black;\"><o:p></o:p></span></u></p>\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n            \r\n            \r\n            \r\n            \r\n            \r\n            \r\n            <ul style=\"margin-top: 0cm;\" type=\"square\">\r\n<li><span style=\"font-size: 10pt; font-family: Verdana;\">Source code comments review and update</span></li>\r\n              <li><span style=\"font-size: 10pt; font-family: Verdana;\">HID class</span></li>\r\n              <ul>\r\n                <li><span style=\"font-size: 10pt; font-family: Verdana;\">Remove unused API <span style=\"font-style: italic;\">USBD_HID_DeviceQualifierDescriptor()</span></span></li>\r\n                <li><span style=\"font-size: 10pt; font-family: Verdana;\">Add a new API in the HID class to query the poll time <span style=\"font-style: italic;\">USBD_HID_GetPollingInterval()</span></span><br>\r\n                  <span style=\"font-size: 10pt; font-family: Verdana;\"></span></li>\r\n              </ul>\r\n              \r\n              <li><span style=\"font-size: 10pt; font-family: Verdana;\">CDC class</span></li>\r\n              <ul>\r\n<li><span style=\"font-size: 10pt; font-family: Verdana;\">Bug fix: missing handling ZeroLength Setup request</span></li>\r\n              </ul>\r\n              <li><span style=\"font-size: 10pt; font-family: Verdana;\">All classes</span><br>\r\n                <span style=\"font-size: 10pt; font-family: Verdana;\"></span></li>\r\n\r\n              <ul>\r\n                <li><span style=\"font-size: 10pt; font-family: Verdana;\">Add alias for the class definition, it's defined as macro with capital letter</span></li>\r\n              </ul>\r\n            </ul>\r\n            <div style=\"margin-left: 80px;\"><span style=\"font-size: 10pt; font-family: Verdana;\">ex. for the HID, the <span style=\"font-style: italic;\">USBD_HID_CLASS</span> macro is defined this way </span><span style=\"font-size: 10pt; font-family: Verdana;\"><span style=\"font-style: italic;\">#define USBD_HID_CLASS&nbsp; &amp;USBD_HID</span></span><br>&nbsp;  <span style=\"font-size: 10pt; font-family: Verdana;\"></span><span style=\"font-size: 10pt; font-family: Verdana;\"></span><span style=\"font-size: 10pt; font-family: Verdana;\">and the application code can use the previous definition: <span style=\"font-style: italic;\">&amp;USBD_HID</span> ex. <span style=\"font-style: italic;\">USBD_RegisterClass(&amp;USBD_Device, &amp;USBD_HID)</span> or the new <span style=\"font-style: italic;\">USBD_HID_CLASS</span> ex. <span style=\"font-style: italic;\">USBD_RegisterClass(&amp;USBD_Device, USBD_HID_CLASS)</span></span></div>\r\n            <h3 style=\"background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 180px;\"><span style=\"font-size: 10pt; font-family: Arial; color: white;\">V2.1.0 / 22-April-2014</span></h3>\r\n\r\n\r\n\r\n\r\n\r\n            \r\n            \r\n            \r\n            <p class=\"MsoNormal\" style=\"margin: 4.5pt 0cm 4.5pt 18pt;\"><b style=\"\"><u><span style=\"font-size: 10pt; font-family: Verdana; color: black;\">Main\r\nChanges</span></u></b><u><span style=\"font-size: 10pt; font-family: Verdana; color: black;\"><o:p></o:p></span></u></p>\r\n\r\n\r\n\r\n\r\n\r\n\r\n            \r\n            \r\n            \r\n            \r\n            \r\n            <ul style=\"margin-top: 0cm;\" type=\"square\">\r\n<li><span style=\"font-size: 10pt; font-family: Verdana;\">usbd_conf_template.c: update file with the right content (it was using MSC memory management layer)<br>\r\n </span></li>\r\n              <li><span style=\"font-size: 10pt; font-family: Verdana;\">usbd_conf_template.h: change include of <span style=\"font-style: italic;\">stm32f4xx.h </span>by <span style=\"font-style: italic;\">stm32xxx.h</span> and add comment to inform user to adapt it to the device used</span></li>\r\n              <li><span style=\"font-size: 10pt; font-family: Verdana;\">Several enhancements in CustomHID class</span></li>\r\n              <ul>\r\n                <li><span style=\"font-size: 10pt; font-family: Verdana;\">Update the Custom HID class driver to simplify the link with user processes</span></li>\r\n                <li><span style=\"font-size: 10pt; font-family: Verdana;\">Optimize the Custom HID class driver and reduce footprint</span></li>\r\n                <li><span style=\"font-size: 10pt; font-family: Verdana;\">Add <span style=\"font-style: italic;\">USBD_CUSTOM_HID_RegisterInterface() </span>API to link user process to custom HID class</span></li>\r\n                <li><span style=\"font-size: 10pt; font-family: Verdana;\">Add Custom HID interface template file <span style=\"font-style: italic;\">usbd_customhid_if_template.c/h</span></span></li>\r\n              </ul>\r\n              <li><span style=\"font-size: 10pt; font-family: Verdana;\">Miscellaneous comments update<span style=\"font-style: italic;\"><br>\r\n                </span></span></li>\r\n\r\n            </ul>\r\n\r\n            <h3 style=\"background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 180px;\"><span style=\"font-size: 10pt; font-family: Arial; color: white;\">V2.0.0 / 18-February-2014</span></h3>\r\n\r\n\r\n\r\n            \r\n            \r\n            <p class=\"MsoNormal\" style=\"margin: 4.5pt 0cm 4.5pt 18pt;\"><b style=\"\"><u><span style=\"font-size: 10pt; font-family: Verdana; color: black;\">Main\r\nChanges</span></u></b><u><span style=\"font-size: 10pt; font-family: Verdana; color: black;\"><o:p></o:p></span></u></p>\r\n\r\n\r\n\r\n\r\n\r\n            \r\n            \r\n            \r\n            \r\n            <ul style=\"margin-top: 0cm;\" type=\"square\">\r\n<li><span style=\"font-size: 10pt; font-family: Verdana;\">Major update\r\nbased on STM32Cube specification: Library Core, Classes architecture and APIs\r\nmodified vs. V1.1.0, and thus the 2 versions are not compatible.<br>\r\n</span></li><li style=\"font-weight: bold;\"><span style=\"font-size: 10pt; font-family: Verdana;\">This version has to be used only with </span><span style=\"font-size: 10pt; font-family: Verdana;\">STM32Cube</span><span style=\"font-size: 10pt; font-family: Verdana;\"> based development</span></li>\r\n            </ul>\r\n\r\n            \r\n<h3 style=\"background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 200px;\"><span style=\"font-size: 10pt; font-family: Arial; color: white;\">V1.1.0 / 19-March-2012<o:p></o:p></span></h3>\r\n            <p class=\"MsoNormal\" style=\"margin: 4.5pt 0cm 4.5pt 18pt;\"><b style=\"\"><u><span style=\"font-size: 10pt; font-family: Verdana; color: black;\">Main\r\nChanges<o:p></o:p></span></u></b></p>\r\n\r\n            <ul style=\"margin-top: 0cm;\" type=\"square\"><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: Verdana;\">Official support of </span><span style=\"font-size: 10pt; font-family: Verdana;\"><span style=\"font-weight: bold; font-style: italic;\">STM32F4xx</span> devices</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: Verdana;\">All source files: license disclaimer text update and add link to the License file on ST Internet.<br></span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: Verdana;\">Handle test mode in the set feature request</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: Verdana;\">Handle dynamically the USB SELF POWERED feature</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: Verdana;\">Handle correctly the USBD_CtlError process to take into account error during Control OUT stage</span></li><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: Verdana;\">Miscellaneous bug fix</span></li></ul><h3 style=\"background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 171px;\"><span style=\"font-size: 10pt; font-family: Arial; color: white;\">V1.0.0 / 22-July-2011<o:p></o:p></span></h3><p class=\"MsoNormal\" style=\"margin: 4.5pt 0cm 4.5pt 18pt;\"><b style=\"\"><u><span style=\"font-size: 10pt; font-family: Verdana; color: black;\">Main\r\nChanges<o:p></o:p></span></u></b></p>\r\n<ul style=\"margin-top: 0cm;\" type=\"square\"><li class=\"MsoNormal\" style=\"color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;\"><span style=\"font-size: 10pt; font-family: Verdana;\">First official version for <span style=\"font-weight: bold; font-style: italic;\">STM32F105/7xx</span> and <span style=\"font-weight: bold; font-style: italic;\">STM32F2xx</span> devices</span></li></ul><span style=\"font-size: 10pt; font-family: Verdana;\"></span><br><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\"></span>\r\n    <h2 style=\"background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;\"><a name=\"License\"></a><span style=\"font-size: 12pt; color: white;\">License<o:p></o:p></span></h2>\r\n    <p class=\"MsoNormal\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;\">Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\"); You may not use this&nbsp;</span><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;\">package</span><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;\"> except in compliance with the License. You may obtain a copy of the License at:<br><br></span></p><div style=\"text-align: center;\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;\">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a target=\"_blank\" href=\"http://www.st.com/software_license_agreement_liberty_v2\">http://www.st.com/software_license_agreement_liberty_v2</a></span><br><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;\"></span></div><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;\"><br>Unless\r\nrequired by applicable law or agreed to in writing, software\r\ndistributed under the License is distributed on an \"AS IS\" BASIS, <br>WITHOUT\r\nWARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See\r\nthe License for the specific language governing permissions and\r\nlimitations under the License.</span>\r\n    <div class=\"MsoNormal\" style=\"text-align: center;\" align=\"center\"><span style=\"color: black;\">\r\n    <hr align=\"center\" size=\"2\" width=\"100%\">\r\n    </span></div>\r\n    <p class=\"MsoNormal\" style=\"margin: 4.5pt 0in 4.5pt 0.25in; text-align: center;\" align=\"center\"><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;\">For\r\n    complete documentation on </span><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\">STM32<span style=\"color: black;\">\r\n    Microcontrollers visit </span><u><span style=\"color: blue;\"><a href=\"http://www.st.com/internet/mcu/family/141.jsp\" target=\"_blank\">www.st.com/STM32</a></span></u></span><span style=\"font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;\"><u><span style=\"color: blue;\"><a href=\"http://www.st.com/stm32\" target=\"_blank\"></a></span></u></span><span style=\"color: black;\"><o:p></o:p></span></p>\r\n    </td>\r\n   </tr>\r\n  </tbody></table>\r\n  <p class=\"MsoNormal\"><span style=\"font-size: 10pt;\"><o:p></o:p></span></p>\r\n  </td>\r\n </tr>\r\n</tbody></table>\r\n\r\n</div>\r\n\r\n<p class=\"MsoNormal\"><o:p>&nbsp;</o:p></p>\r\n\r\n</div>\r\n\r\n</body></html>"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/msg/mavlink/checksum.h",
    "content": "#ifdef __cplusplus\r\nextern \"C\" {\r\n#endif\r\n\r\n#ifndef _CHECKSUM_H_\r\n#define _CHECKSUM_H_\r\n\r\n// Visual Studio versions before 2010 don't have stdint.h, so we just error out.\r\n#if (defined _MSC_VER) && (_MSC_VER < 1600)\r\n#error \"The C-MAVLink implementation requires Visual Studio 2010 or greater\"\r\n#endif\r\n\r\n#include <stdint.h>\r\n\r\n/**\r\n *\r\n *  CALCULATE THE CHECKSUM\r\n *\r\n */\r\n\r\n#define X25_INIT_CRC 0xffff\r\n#define X25_VALIDATE_CRC 0xf0b8\r\n\r\n#ifndef HAVE_CRC_ACCUMULATE\r\n/**\r\n * @brief Accumulate the X.25 CRC by adding one char at a time.\r\n *\r\n * The checksum function adds the hash of one char at a time to the\r\n * 16 bit checksum (uint16_t).\r\n *\r\n * @param data new char to hash\r\n * @param crcAccum the already accumulated checksum\r\n **/\r\nstatic inline void crc_accumulate(uint8_t data, uint16_t *crcAccum)\r\n{\r\n        /*Accumulate one byte of data into the CRC*/\r\n        uint8_t tmp;\r\n\r\n        tmp = data ^ (uint8_t)(*crcAccum &0xff);\r\n        tmp ^= (tmp<<4);\r\n        *crcAccum = (*crcAccum>>8) ^ (tmp<<8) ^ (tmp <<3) ^ (tmp>>4);\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n * @brief Initiliaze the buffer for the X.25 CRC\r\n *\r\n * @param crcAccum the 16 bit X.25 CRC\r\n */\r\nstatic inline void crc_init(uint16_t* crcAccum)\r\n{\r\n        *crcAccum = X25_INIT_CRC;\r\n}\r\n\r\n\r\n/**\r\n * @brief Calculates the X.25 checksum on a byte buffer\r\n *\r\n * @param  pBuffer buffer containing the byte array to hash\r\n * @param  length  length of the byte array\r\n * @return the checksum over the buffer bytes\r\n **/\r\nstatic inline uint16_t crc_calculate(const uint8_t* pBuffer, uint16_t length)\r\n{\r\n        uint16_t crcTmp;\r\n        crc_init(&crcTmp);\r\n\twhile (length--) {\r\n                crc_accumulate(*pBuffer++, &crcTmp);\r\n        }\r\n        return crcTmp;\r\n}\r\n\r\n\r\n/**\r\n * @brief Accumulate the X.25 CRC by adding an array of bytes\r\n *\r\n * The checksum function adds the hash of one char at a time to the\r\n * 16 bit checksum (uint16_t).\r\n *\r\n * @param data new bytes to hash\r\n * @param crcAccum the already accumulated checksum\r\n **/\r\nstatic inline void crc_accumulate_buffer(uint16_t *crcAccum, const char *pBuffer, uint16_t length)\r\n{\r\n\tconst uint8_t *p = (const uint8_t *)pBuffer;\r\n\twhile (length--) {\r\n                crc_accumulate(*p++, crcAccum);\r\n        }\r\n}\r\n\r\n#endif /* _CHECKSUM_H_ */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/msg/mavlink/mavlink_conversions.h",
    "content": "#ifndef  _MAVLINK_CONVERSIONS_H_\r\n#define  _MAVLINK_CONVERSIONS_H_\r\n\r\n/* enable math defines on Windows */\r\n#ifdef _MSC_VER\r\n#ifndef _USE_MATH_DEFINES\r\n#define _USE_MATH_DEFINES\r\n#endif\r\n#endif\r\n#include <math.h>\r\n\r\n#ifndef M_PI_2\r\n    #define M_PI_2 ((float)asin(1))\r\n#endif\r\n\r\n/**\r\n * @file mavlink_conversions.h\r\n *\r\n * These conversion functions follow the NASA rotation standards definition file\r\n * available online.\r\n *\r\n * Their intent is to lower the barrier for MAVLink adopters to use gimbal-lock free\r\n * (both rotation matrices, sometimes called DCM, and quaternions are gimbal-lock free)\r\n * rotation representations. Euler angles (roll, pitch, yaw) will be phased out of the\r\n * protocol as widely as possible.\r\n *\r\n * @author James Goppert\r\n * @author Thomas Gubler <thomasgubler@gmail.com>\r\n */\r\n\r\n\r\n/**\r\n * Converts a quaternion to a rotation matrix\r\n *\r\n * @param quaternion a [w, x, y, z] ordered quaternion (null-rotation being 1 0 0 0)\r\n * @param dcm a 3x3 rotation matrix\r\n */\r\nMAVLINK_HELPER void mavlink_quaternion_to_dcm(const float quaternion[4], float dcm[3][3])\r\n{\r\n    double a = quaternion[0];\r\n    double b = quaternion[1];\r\n    double c = quaternion[2];\r\n    double d = quaternion[3];\r\n    double aSq = a * a;\r\n    double bSq = b * b;\r\n    double cSq = c * c;\r\n    double dSq = d * d;\r\n    dcm[0][0] = aSq + bSq - cSq - dSq;\r\n    dcm[0][1] = 2 * (b * c - a * d);\r\n    dcm[0][2] = 2 * (a * c + b * d);\r\n    dcm[1][0] = 2 * (b * c + a * d);\r\n    dcm[1][1] = aSq - bSq + cSq - dSq;\r\n    dcm[1][2] = 2 * (c * d - a * b);\r\n    dcm[2][0] = 2 * (b * d - a * c);\r\n    dcm[2][1] = 2 * (a * b + c * d);\r\n    dcm[2][2] = aSq - bSq - cSq + dSq;\r\n}\r\n\r\n\r\n/**\r\n * Converts a rotation matrix to euler angles\r\n *\r\n * @param dcm a 3x3 rotation matrix\r\n * @param roll the roll angle in radians\r\n * @param pitch the pitch angle in radians\r\n * @param yaw the yaw angle in radians\r\n */\r\nMAVLINK_HELPER void mavlink_dcm_to_euler(const float dcm[3][3], float* roll, float* pitch, float* yaw)\r\n{\r\n    float phi, theta, psi;\r\n    theta = asin(-dcm[2][0]);\r\n\r\n    if (fabsf(theta - (float)M_PI_2) < 1.0e-3f) {\r\n        phi = 0.0f;\r\n        psi = (atan2f(dcm[1][2] - dcm[0][1],\r\n                dcm[0][2] + dcm[1][1]) + phi);\r\n\r\n    } else if (fabsf(theta + (float)M_PI_2) < 1.0e-3f) {\r\n        phi = 0.0f;\r\n        psi = atan2f(dcm[1][2] - dcm[0][1],\r\n                  dcm[0][2] + dcm[1][1] - phi);\r\n\r\n    } else {\r\n        phi = atan2f(dcm[2][1], dcm[2][2]);\r\n        psi = atan2f(dcm[1][0], dcm[0][0]);\r\n    }\r\n\r\n    *roll = phi;\r\n    *pitch = theta;\r\n    *yaw = psi;\r\n}\r\n\r\n\r\n/**\r\n * Converts a quaternion to euler angles\r\n *\r\n * @param quaternion a [w, x, y, z] ordered quaternion (null-rotation being 1 0 0 0)\r\n * @param roll the roll angle in radians\r\n * @param pitch the pitch angle in radians\r\n * @param yaw the yaw angle in radians\r\n */\r\nMAVLINK_HELPER void mavlink_quaternion_to_euler(const float quaternion[4], float* roll, float* pitch, float* yaw)\r\n{\r\n    float dcm[3][3];\r\n    mavlink_quaternion_to_dcm(quaternion, dcm);\r\n    mavlink_dcm_to_euler((const float(*)[3])dcm, roll, pitch, yaw);\r\n}\r\n\r\n\r\n/**\r\n * Converts euler angles to a quaternion\r\n *\r\n * @param roll the roll angle in radians\r\n * @param pitch the pitch angle in radians\r\n * @param yaw the yaw angle in radians\r\n * @param quaternion a [w, x, y, z] ordered quaternion (null-rotation being 1 0 0 0)\r\n */\r\nMAVLINK_HELPER void mavlink_euler_to_quaternion(float roll, float pitch, float yaw, float quaternion[4])\r\n{\r\n    float cosPhi_2 = cosf(roll / 2);\r\n    float sinPhi_2 = sinf(roll / 2);\r\n    float cosTheta_2 = cosf(pitch / 2);\r\n    float sinTheta_2 = sinf(pitch / 2);\r\n    float cosPsi_2 = cosf(yaw / 2);\r\n    float sinPsi_2 = sinf(yaw / 2);\r\n    quaternion[0] = (cosPhi_2 * cosTheta_2 * cosPsi_2 +\r\n            sinPhi_2 * sinTheta_2 * sinPsi_2);\r\n    quaternion[1] = (sinPhi_2 * cosTheta_2 * cosPsi_2 -\r\n            cosPhi_2 * sinTheta_2 * sinPsi_2);\r\n    quaternion[2] = (cosPhi_2 * sinTheta_2 * cosPsi_2 +\r\n            sinPhi_2 * cosTheta_2 * sinPsi_2);\r\n    quaternion[3] = (cosPhi_2 * cosTheta_2 * sinPsi_2 -\r\n            sinPhi_2 * sinTheta_2 * cosPsi_2);\r\n}\r\n\r\n\r\n/**\r\n * Converts a rotation matrix to a quaternion\r\n * Reference:\r\n *  - Shoemake, Quaternions,\r\n *  http://www.cs.ucr.edu/~vbz/resources/quatut.pdf\r\n *\r\n * @param dcm a 3x3 rotation matrix\r\n * @param quaternion a [w, x, y, z] ordered quaternion (null-rotation being 1 0 0 0)\r\n */\r\nMAVLINK_HELPER void mavlink_dcm_to_quaternion(const float dcm[3][3], float quaternion[4])\r\n{\r\n    float tr = dcm[0][0] + dcm[1][1] + dcm[2][2];\r\n    if (tr > 0.0f) {\r\n        float s = sqrtf(tr + 1.0f);\r\n        quaternion[0] = s * 0.5f;\r\n        s = 0.5f / s;\r\n        quaternion[1] = (dcm[2][1] - dcm[1][2]) * s;\r\n        quaternion[2] = (dcm[0][2] - dcm[2][0]) * s;\r\n        quaternion[3] = (dcm[1][0] - dcm[0][1]) * s;\r\n    } else {\r\n        /* Find maximum diagonal element in dcm\r\n         * store index in dcm_i */\r\n        int dcm_i = 0;\r\n        int i;\r\n        for (i = 1; i < 3; i++) {\r\n            if (dcm[i][i] > dcm[dcm_i][dcm_i]) {\r\n                dcm_i = i;\r\n            }\r\n        }\r\n\r\n        int dcm_j = (dcm_i + 1) % 3;\r\n        int dcm_k = (dcm_i + 2) % 3;\r\n\r\n        float s = sqrtf((dcm[dcm_i][dcm_i] - dcm[dcm_j][dcm_j] -\r\n                    dcm[dcm_k][dcm_k]) + 1.0f);\r\n        quaternion[dcm_i + 1] = s * 0.5f;\r\n        s = 0.5f / s;\r\n        quaternion[dcm_j + 1] = (dcm[dcm_i][dcm_j] + dcm[dcm_j][dcm_i]) * s;\r\n        quaternion[dcm_k + 1] = (dcm[dcm_k][dcm_i] + dcm[dcm_i][dcm_k]) * s;\r\n        quaternion[0] = (dcm[dcm_k][dcm_j] - dcm[dcm_j][dcm_k]) * s;\r\n    }\r\n}\r\n\r\n\r\n/**\r\n * Converts euler angles to a rotation matrix\r\n *\r\n * @param roll the roll angle in radians\r\n * @param pitch the pitch angle in radians\r\n * @param yaw the yaw angle in radians\r\n * @param dcm a 3x3 rotation matrix\r\n */\r\nMAVLINK_HELPER void mavlink_euler_to_dcm(float roll, float pitch, float yaw, float dcm[3][3])\r\n{\r\n    float cosPhi = cosf(roll);\r\n    float sinPhi = sinf(roll);\r\n    float cosThe = cosf(pitch);\r\n    float sinThe = sinf(pitch);\r\n    float cosPsi = cosf(yaw);\r\n    float sinPsi = sinf(yaw);\r\n\r\n    dcm[0][0] = cosThe * cosPsi;\r\n    dcm[0][1] = -cosPhi * sinPsi + sinPhi * sinThe * cosPsi;\r\n    dcm[0][2] = sinPhi * sinPsi + cosPhi * sinThe * cosPsi;\r\n\r\n    dcm[1][0] = cosThe * sinPsi;\r\n    dcm[1][1] = cosPhi * cosPsi + sinPhi * sinThe * sinPsi;\r\n    dcm[1][2] = -sinPhi * cosPsi + cosPhi * sinThe * sinPsi;\r\n\r\n    dcm[2][0] = -sinThe;\r\n    dcm[2][1] = sinPhi * cosThe;\r\n    dcm[2][2] = cosPhi * cosThe;\r\n}\r\n\r\n#endif\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/msg/mavlink/mavlink_helpers.h",
    "content": "#ifndef  _MAVLINK_HELPERS_H_\r\n#define  _MAVLINK_HELPERS_H_\r\n\r\n#include \"string.h\"\r\n#include \"checksum.h\"\r\n#include \"mavlink_types.h\"\r\n#include \"mavlink_conversions.h\"\r\n\r\n#ifndef MAVLINK_HELPER\r\n#define MAVLINK_HELPER\r\n#endif\r\n\r\n/*\r\n * Internal function to give access to the channel status for each channel\r\n */\r\n#ifndef MAVLINK_GET_CHANNEL_STATUS\r\nMAVLINK_HELPER mavlink_status_t* mavlink_get_channel_status(uint8_t chan)\r\n{\r\n#ifdef MAVLINK_EXTERNAL_RX_STATUS\r\n\t// No m_mavlink_status array defined in function,\r\n\t// has to be defined externally\r\n#else\r\n\tstatic mavlink_status_t m_mavlink_status[MAVLINK_COMM_NUM_BUFFERS];\r\n#endif\r\n\treturn &m_mavlink_status[chan];\r\n}\r\n#endif\r\n\r\n/*\r\n * Internal function to give access to the channel buffer for each channel\r\n */\r\n#ifndef MAVLINK_GET_CHANNEL_BUFFER\r\nMAVLINK_HELPER mavlink_message_t* mavlink_get_channel_buffer(uint8_t chan)\r\n{\r\n\t\r\n#ifdef MAVLINK_EXTERNAL_RX_BUFFER\r\n\t// No m_mavlink_buffer array defined in function,\r\n\t// has to be defined externally\r\n#else\r\n\tstatic mavlink_message_t m_mavlink_buffer[MAVLINK_COMM_NUM_BUFFERS];\r\n#endif\r\n\treturn &m_mavlink_buffer[chan];\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Reset the status of a channel.\r\n */\r\nMAVLINK_HELPER void mavlink_reset_channel_status(uint8_t chan)\r\n{\r\n\tmavlink_status_t *status = mavlink_get_channel_status(chan);\r\n\tstatus->parse_state = MAVLINK_PARSE_STATE_IDLE;\r\n}\r\n\r\n/**\r\n * @brief Finalize a MAVLink message with channel assignment\r\n *\r\n * This function calculates the checksum and sets length and aircraft id correctly.\r\n * It assumes that the message id and the payload are already correctly set. This function\r\n * can also be used if the message header has already been written before (as in mavlink_msg_xxx_pack\r\n * instead of mavlink_msg_xxx_pack_headerless), it just introduces little extra overhead.\r\n *\r\n * @param msg Message to finalize\r\n * @param system_id Id of the sending (this) system, 1-127\r\n * @param length Message length\r\n */\r\n#if MAVLINK_CRC_EXTRA\r\nMAVLINK_HELPER uint16_t mavlink_finalize_message_chan(mavlink_message_t* msg, uint8_t system_id, uint8_t component_id, \r\n\t\t\t\t\t\t      uint8_t chan, uint8_t min_length, uint8_t length, uint8_t crc_extra)\r\n#else\r\nMAVLINK_HELPER uint16_t mavlink_finalize_message_chan(mavlink_message_t* msg, uint8_t system_id, uint8_t component_id, \r\n\t\t\t\t\t\t      uint8_t chan, uint8_t length)\r\n#endif\r\n{\r\n\t// This code part is the same for all messages;\r\n\tmsg->magic = MAVLINK_STX;\r\n\tmsg->len = length;\r\n\tmsg->sysid = system_id;\r\n\tmsg->compid = component_id;\r\n\t// One sequence number per channel\r\n\tmsg->seq = mavlink_get_channel_status(chan)->current_tx_seq;\r\n\tmavlink_get_channel_status(chan)->current_tx_seq = mavlink_get_channel_status(chan)->current_tx_seq+1;\r\n\tmsg->checksum = crc_calculate(((const uint8_t*)(msg)) + 3, MAVLINK_CORE_HEADER_LEN);\r\n\tcrc_accumulate_buffer(&msg->checksum, _MAV_PAYLOAD(msg), msg->len);\r\n#if MAVLINK_CRC_EXTRA\r\n\tcrc_accumulate(crc_extra, &msg->checksum);\r\n#endif\r\n\tmavlink_ck_a(msg) = (uint8_t)(msg->checksum & 0xFF);\r\n\tmavlink_ck_b(msg) = (uint8_t)(msg->checksum >> 8);\r\n\r\n\treturn length + MAVLINK_NUM_NON_PAYLOAD_BYTES;\r\n}\r\n\r\n\r\n/**\r\n * @brief Finalize a MAVLink message with MAVLINK_COMM_0 as default channel\r\n */\r\n#if MAVLINK_CRC_EXTRA\r\nMAVLINK_HELPER uint16_t mavlink_finalize_message(mavlink_message_t* msg, uint8_t system_id, uint8_t component_id, \r\n\t\t\t\t\t\t uint8_t min_length, uint8_t length, uint8_t crc_extra)\r\n{\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, MAVLINK_COMM_0, min_length, length, crc_extra);\r\n}\r\n#else\r\nMAVLINK_HELPER uint16_t mavlink_finalize_message(mavlink_message_t* msg, uint8_t system_id, uint8_t component_id, \r\n\t\t\t\t\t\t uint8_t length)\r\n{\r\n\treturn mavlink_finalize_message_chan(msg, system_id, component_id, MAVLINK_COMM_0, length);\r\n}\r\n#endif\r\n\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\nMAVLINK_HELPER void _mavlink_send_uart(mavlink_channel_t chan, const char *buf, uint16_t len);\r\n\r\n/**\r\n * @brief Finalize a MAVLink message with channel assignment and send\r\n */\r\n#if MAVLINK_CRC_EXTRA\r\nMAVLINK_HELPER void _mav_finalize_message_chan_send(mavlink_channel_t chan, uint8_t msgid, const char *packet, \r\n\t\t\t\t\t\t    uint8_t min_length, uint8_t length, uint8_t crc_extra)\r\n#else\r\nMAVLINK_HELPER void _mav_finalize_message_chan_send(mavlink_channel_t chan, uint8_t msgid, const char *packet, uint8_t length)\r\n#endif\r\n{\r\n\tuint16_t checksum;\r\n\tuint8_t buf[MAVLINK_NUM_HEADER_BYTES];\r\n\tuint8_t ck[2];\r\n\tmavlink_status_t *status = mavlink_get_channel_status(chan);\r\n\tbuf[0] = MAVLINK_STX;\r\n\tbuf[1] = length;\r\n\tbuf[2] = status->current_tx_seq;\r\n\tbuf[3] = mavlink_system.sysid;\r\n\tbuf[4] = mavlink_system.compid;\r\n\tbuf[5] = msgid;\r\n\tstatus->current_tx_seq++;\r\n\tchecksum = crc_calculate((const uint8_t*)&buf[1], MAVLINK_CORE_HEADER_LEN);\r\n\tcrc_accumulate_buffer(&checksum, packet, length);\r\n#if MAVLINK_CRC_EXTRA\r\n\tcrc_accumulate(crc_extra, &checksum);\r\n#endif\r\n\tck[0] = (uint8_t)(checksum & 0xFF);\r\n\tck[1] = (uint8_t)(checksum >> 8);\r\n\r\n\tMAVLINK_START_UART_SEND(chan, MAVLINK_NUM_NON_PAYLOAD_BYTES + (uint16_t)length);\r\n\t_mavlink_send_uart(chan, (const char *)buf, MAVLINK_NUM_HEADER_BYTES);\r\n\t_mavlink_send_uart(chan, packet, length);\r\n\t_mavlink_send_uart(chan, (const char *)ck, 2);\r\n\tMAVLINK_END_UART_SEND(chan, MAVLINK_NUM_NON_PAYLOAD_BYTES + (uint16_t)length);\r\n}\r\n\r\n/**\r\n * @brief re-send a message over a uart channel\r\n * this is more stack efficient than re-marshalling the message\r\n */\r\nMAVLINK_HELPER void _mavlink_resend_uart(mavlink_channel_t chan, const mavlink_message_t *msg)\r\n{\r\n\tuint8_t ck[2];\r\n\r\n\tck[0] = (uint8_t)(msg->checksum & 0xFF);\r\n\tck[1] = (uint8_t)(msg->checksum >> 8);\r\n\t// XXX use the right sequence here\r\n\r\n\tMAVLINK_START_UART_SEND(chan, MAVLINK_NUM_NON_PAYLOAD_BYTES + msg->len);\r\n\t_mavlink_send_uart(chan, (const char *)&msg->magic, MAVLINK_NUM_HEADER_BYTES);\r\n\t_mavlink_send_uart(chan, _MAV_PAYLOAD(msg), msg->len);\r\n\t_mavlink_send_uart(chan, (const char *)ck, 2);\r\n\tMAVLINK_END_UART_SEND(chan, MAVLINK_NUM_NON_PAYLOAD_BYTES + msg->len);\r\n}\r\n#endif // MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\n/**\r\n * @brief Pack a message to send it over a serial byte stream\r\n */\r\nMAVLINK_HELPER uint16_t mavlink_msg_to_send_buffer(uint8_t *buffer, const mavlink_message_t *msg)\r\n{\r\n\tmemcpy(buffer, (const uint8_t *)&msg->magic, MAVLINK_NUM_HEADER_BYTES + (uint16_t)msg->len);\r\n\r\n\tuint8_t *ck = buffer + (MAVLINK_NUM_HEADER_BYTES + (uint16_t)msg->len);\r\n\r\n\tck[0] = (uint8_t)(msg->checksum & 0xFF);\r\n\tck[1] = (uint8_t)(msg->checksum >> 8);\r\n\r\n\treturn MAVLINK_NUM_NON_PAYLOAD_BYTES + (uint16_t)msg->len;\r\n}\r\n\r\nunion __mavlink_bitfield {\r\n\tuint8_t uint8;\r\n\tint8_t int8;\r\n\tuint16_t uint16;\r\n\tint16_t int16;\r\n\tuint32_t uint32;\r\n\tint32_t int32;\r\n};\r\n\r\n\r\nMAVLINK_HELPER void mavlink_start_checksum(mavlink_message_t* msg)\r\n{\r\n\tcrc_init(&msg->checksum);\r\n}\r\n\r\nMAVLINK_HELPER void mavlink_update_checksum(mavlink_message_t* msg, uint8_t c)\r\n{\r\n\tcrc_accumulate(c, &msg->checksum);\r\n}\r\n\r\n/**\r\n * This is a varient of mavlink_frame_char() but with caller supplied\r\n * parsing buffers. It is useful when you want to create a MAVLink\r\n * parser in a library that doesn't use any global variables\r\n *\r\n * @param rxmsg    parsing message buffer\r\n * @param status   parsing starus buffer \r\n * @param c        The char to parse\r\n *\r\n * @param returnMsg NULL if no message could be decoded, the message data else\r\n * @param returnStats if a message was decoded, this is filled with the channel's stats\r\n * @return 0 if no message could be decoded, 1 on good message and CRC, 2 on bad CRC\r\n *\r\n * A typical use scenario of this function call is:\r\n *\r\n * @code\r\n * #include <mavlink.h>\r\n *\r\n * mavlink_message_t msg;\r\n * int chan = 0;\r\n *\r\n *\r\n * while(serial.bytesAvailable > 0)\r\n * {\r\n *   uint8_t byte = serial.getNextByte();\r\n *   if (mavlink_frame_char(chan, byte, &msg) != MAVLINK_FRAMING_INCOMPLETE)\r\n *     {\r\n *     printf(\"Received message with ID %d, sequence: %d from component %d of system %d\", msg.msgid, msg.seq, msg.compid, msg.sysid);\r\n *     }\r\n * }\r\n *\r\n *\r\n * @endcode\r\n */\r\nMAVLINK_HELPER uint8_t mavlink_frame_char_buffer(mavlink_message_t* rxmsg, \r\n                                                 mavlink_status_t* status,\r\n                                                 uint8_t c, \r\n                                                 mavlink_message_t* r_message, \r\n                                                 mavlink_status_t* r_mavlink_status)\r\n{\r\n        /*\r\n\t  default message crc function. You can override this per-system to\r\n\t  put this data in a different memory segment\r\n\t*/\r\n#if MAVLINK_CRC_EXTRA\r\n#ifndef MAVLINK_MESSAGE_CRC\r\n\tstatic const uint8_t mavlink_message_crcs[256] = MAVLINK_MESSAGE_CRCS;\r\n#define MAVLINK_MESSAGE_CRC(msgid) mavlink_message_crcs[msgid]\r\n#endif\r\n#endif\r\n\r\n\t/* Enable this option to check the length of each message.\r\n\t   This allows invalid messages to be caught much sooner. Use if the transmission\r\n\t   medium is prone to missing (or extra) characters (e.g. a radio that fades in\r\n\t   and out). Only use if the channel will only contain messages types listed in\r\n\t   the headers.\r\n\t*/\r\n#ifdef MAVLINK_CHECK_MESSAGE_LENGTH\r\n#ifndef MAVLINK_MESSAGE_LENGTH\r\n\tstatic const uint8_t mavlink_message_lengths[256] = MAVLINK_MESSAGE_LENGTHS;\r\n#define MAVLINK_MESSAGE_LENGTH(msgid) mavlink_message_lengths[msgid]\r\n#endif\r\n#endif\r\n\r\n\tint bufferIndex = 0;\r\n\r\n\tstatus->msg_received = MAVLINK_FRAMING_INCOMPLETE;\r\n\r\n\tswitch (status->parse_state)\r\n\t{\r\n\tcase MAVLINK_PARSE_STATE_UNINIT:\r\n\tcase MAVLINK_PARSE_STATE_IDLE:\r\n\t\tif (c == MAVLINK_STX)\r\n\t\t{\r\n\t\t\tstatus->parse_state = MAVLINK_PARSE_STATE_GOT_STX;\r\n\t\t\trxmsg->len = 0;\r\n\t\t\trxmsg->magic = c;\r\n\t\t\tmavlink_start_checksum(rxmsg);\r\n\t\t}\r\n\t\tbreak;\r\n\r\n\tcase MAVLINK_PARSE_STATE_GOT_STX:\r\n\t\t\tif (status->msg_received \r\n/* Support shorter buffers than the\r\n   default maximum packet size */\r\n#if (MAVLINK_MAX_PAYLOAD_LEN < 255)\r\n\t\t\t\t|| c > MAVLINK_MAX_PAYLOAD_LEN\r\n#endif\r\n\t\t\t\t)\r\n\t\t{\r\n\t\t\tstatus->buffer_overrun++;\r\n\t\t\tstatus->parse_error++;\r\n\t\t\tstatus->msg_received = 0;\r\n\t\t\tstatus->parse_state = MAVLINK_PARSE_STATE_IDLE;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\t// NOT counting STX, LENGTH, SEQ, SYSID, COMPID, MSGID, CRC1 and CRC2\r\n\t\t\trxmsg->len = c;\r\n\t\t\tstatus->packet_idx = 0;\r\n\t\t\tmavlink_update_checksum(rxmsg, c);\r\n\t\t\tstatus->parse_state = MAVLINK_PARSE_STATE_GOT_LENGTH;\r\n\t\t}\r\n\t\tbreak;\r\n\r\n\tcase MAVLINK_PARSE_STATE_GOT_LENGTH:\r\n\t\trxmsg->seq = c;\r\n\t\tmavlink_update_checksum(rxmsg, c);\r\n\t\tstatus->parse_state = MAVLINK_PARSE_STATE_GOT_SEQ;\r\n\t\tbreak;\r\n\r\n\tcase MAVLINK_PARSE_STATE_GOT_SEQ:\r\n\t\trxmsg->sysid = c;\r\n\t\tmavlink_update_checksum(rxmsg, c);\r\n\t\tstatus->parse_state = MAVLINK_PARSE_STATE_GOT_SYSID;\r\n\t\tbreak;\r\n\r\n\tcase MAVLINK_PARSE_STATE_GOT_SYSID:\r\n\t\trxmsg->compid = c;\r\n\t\tmavlink_update_checksum(rxmsg, c);\r\n\t\tstatus->parse_state = MAVLINK_PARSE_STATE_GOT_COMPID;\r\n\t\tbreak;\r\n\r\n\tcase MAVLINK_PARSE_STATE_GOT_COMPID:\r\n#ifdef MAVLINK_CHECK_MESSAGE_LENGTH\r\n\t        if (rxmsg->len != MAVLINK_MESSAGE_LENGTH(c))\r\n\t\t{\r\n\t\t\tstatus->parse_error++;\r\n\t\t\tstatus->parse_state = MAVLINK_PARSE_STATE_IDLE;\r\n\t\t\tbreak;\r\n\t    }\r\n#endif\r\n\t\trxmsg->msgid = c;\r\n\t\tmavlink_update_checksum(rxmsg, c);\r\n\t\tif (rxmsg->len == 0)\r\n\t\t{\r\n\t\t\tstatus->parse_state = MAVLINK_PARSE_STATE_GOT_PAYLOAD;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tstatus->parse_state = MAVLINK_PARSE_STATE_GOT_MSGID;\r\n\t\t}\r\n\t\tbreak;\r\n\r\n\tcase MAVLINK_PARSE_STATE_GOT_MSGID:\r\n\t\t_MAV_PAYLOAD_NON_CONST(rxmsg)[status->packet_idx++] = (char)c;\r\n\t\tmavlink_update_checksum(rxmsg, c);\r\n\t\tif (status->packet_idx == rxmsg->len)\r\n\t\t{\r\n\t\t\tstatus->parse_state = MAVLINK_PARSE_STATE_GOT_PAYLOAD;\r\n\t\t}\r\n\t\tbreak;\r\n\r\n\tcase MAVLINK_PARSE_STATE_GOT_PAYLOAD:\r\n#if MAVLINK_CRC_EXTRA\r\n\t\tmavlink_update_checksum(rxmsg, MAVLINK_MESSAGE_CRC(rxmsg->msgid));\r\n#endif\r\n\t\tif (c != (rxmsg->checksum & 0xFF)) {\r\n\t\t\tstatus->parse_state = MAVLINK_PARSE_STATE_GOT_BAD_CRC1;\r\n\t\t} else {\r\n\t\t\tstatus->parse_state = MAVLINK_PARSE_STATE_GOT_CRC1;\r\n\t\t}\r\n                _MAV_PAYLOAD_NON_CONST(rxmsg)[status->packet_idx] = (char)c;\r\n\t\tbreak;\r\n\r\n\tcase MAVLINK_PARSE_STATE_GOT_CRC1:\r\n\tcase MAVLINK_PARSE_STATE_GOT_BAD_CRC1:\r\n\t\tif (status->parse_state == MAVLINK_PARSE_STATE_GOT_BAD_CRC1 || c != (rxmsg->checksum >> 8)) {\r\n\t\t\t// got a bad CRC message\r\n\t\t\tstatus->msg_received = MAVLINK_FRAMING_BAD_CRC;\r\n\t\t} else {\r\n\t\t\t// Successfully got message\r\n\t\t\tstatus->msg_received = MAVLINK_FRAMING_OK;\r\n                }\r\n                status->parse_state = MAVLINK_PARSE_STATE_IDLE;\r\n                _MAV_PAYLOAD_NON_CONST(rxmsg)[status->packet_idx+1] = (char)c;\r\n                memcpy(r_message, rxmsg, sizeof(mavlink_message_t));\r\n\t\tbreak;\r\n\t}\r\n\r\n\tbufferIndex++;\r\n\t// If a message has been sucessfully decoded, check index\r\n\tif (status->msg_received == MAVLINK_FRAMING_OK)\r\n\t{\r\n\t\t//while(status->current_seq != rxmsg->seq)\r\n\t\t//{\r\n\t\t//\tstatus->packet_rx_drop_count++;\r\n\t\t//               status->current_seq++;\r\n\t\t//}\r\n\t\tstatus->current_rx_seq = rxmsg->seq;\r\n\t\t// Initial condition: If no packet has been received so far, drop count is undefined\r\n\t\tif (status->packet_rx_success_count == 0) status->packet_rx_drop_count = 0;\r\n\t\t// Count this packet as received\r\n\t\tstatus->packet_rx_success_count++;\r\n\t}\r\n\r\n\tr_message->len = rxmsg->len; // Provide visibility on how far we are into current msg\r\n\tr_mavlink_status->parse_state = status->parse_state;\r\n\tr_mavlink_status->packet_idx = status->packet_idx;\r\n\tr_mavlink_status->current_rx_seq = status->current_rx_seq+1;\r\n\tr_mavlink_status->packet_rx_success_count = status->packet_rx_success_count;\r\n\tr_mavlink_status->packet_rx_drop_count = status->parse_error;\r\n\tstatus->parse_error = 0;\r\n\r\n\tif (status->msg_received == MAVLINK_FRAMING_BAD_CRC) {\r\n\t\t/*\r\n\t\t  the CRC came out wrong. We now need to overwrite the\r\n\t\t  msg CRC with the one on the wire so that if the\r\n\t\t  caller decides to forward the message anyway that\r\n\t\t  mavlink_msg_to_send_buffer() won't overwrite the\r\n\t\t  checksum\r\n\t\t */\r\n\t\tr_message->checksum = _MAV_PAYLOAD(rxmsg)[status->packet_idx] | (_MAV_PAYLOAD(rxmsg)[status->packet_idx+1]<<8);\r\n\t}\r\n\r\n\treturn status->msg_received;\r\n}\r\n\r\n/**\r\n * This is a convenience function which handles the complete MAVLink parsing.\r\n * the function will parse one byte at a time and return the complete packet once\r\n * it could be successfully decoded. This function will return 0, 1 or\r\n * 2 (MAVLINK_FRAMING_INCOMPLETE, MAVLINK_FRAMING_OK or MAVLINK_FRAMING_BAD_CRC)\r\n *\r\n * Messages are parsed into an internal buffer (one for each channel). When a complete\r\n * message is received it is copies into *returnMsg and the channel's status is\r\n * copied into *returnStats.\r\n *\r\n * @param chan     ID of the current channel. This allows to parse different channels with this function.\r\n *                 a channel is not a physical message channel like a serial port, but a logic partition of\r\n *                 the communication streams in this case. COMM_NB is the limit for the number of channels\r\n *                 on MCU (e.g. ARM7), while COMM_NB_HIGH is the limit for the number of channels in Linux/Windows\r\n * @param c        The char to parse\r\n *\r\n * @param returnMsg NULL if no message could be decoded, the message data else\r\n * @param returnStats if a message was decoded, this is filled with the channel's stats\r\n * @return 0 if no message could be decoded, 1 on good message and CRC, 2 on bad CRC\r\n *\r\n * A typical use scenario of this function call is:\r\n *\r\n * @code\r\n * #include <mavlink.h>\r\n *\r\n * mavlink_message_t msg;\r\n * int chan = 0;\r\n *\r\n *\r\n * while(serial.bytesAvailable > 0)\r\n * {\r\n *   uint8_t byte = serial.getNextByte();\r\n *   if (mavlink_frame_char(chan, byte, &msg) != MAVLINK_FRAMING_INCOMPLETE)\r\n *     {\r\n *     printf(\"Received message with ID %d, sequence: %d from component %d of system %d\", msg.msgid, msg.seq, msg.compid, msg.sysid);\r\n *     }\r\n * }\r\n *\r\n *\r\n * @endcode\r\n */\r\nMAVLINK_HELPER uint8_t mavlink_frame_char(uint8_t chan, uint8_t c, mavlink_message_t* r_message, mavlink_status_t* r_mavlink_status)\r\n{\r\n\treturn mavlink_frame_char_buffer(mavlink_get_channel_buffer(chan),\r\n\t\t\t\t\t mavlink_get_channel_status(chan),\r\n\t\t\t\t\t c,\r\n\t\t\t\t\t r_message,\r\n\t\t\t\t\t r_mavlink_status);\r\n}\r\n\r\n\r\n/**\r\n * This is a convenience function which handles the complete MAVLink parsing.\r\n * the function will parse one byte at a time and return the complete packet once\r\n * it could be successfully decoded. This function will return 0 or 1.\r\n *\r\n * Messages are parsed into an internal buffer (one for each channel). When a complete\r\n * message is received it is copies into *returnMsg and the channel's status is\r\n * copied into *returnStats.\r\n *\r\n * @param chan     ID of the current channel. This allows to parse different channels with this function.\r\n *                 a channel is not a physical message channel like a serial port, but a logic partition of\r\n *                 the communication streams in this case. COMM_NB is the limit for the number of channels\r\n *                 on MCU (e.g. ARM7), while COMM_NB_HIGH is the limit for the number of channels in Linux/Windows\r\n * @param c        The char to parse\r\n *\r\n * @param returnMsg NULL if no message could be decoded, the message data else\r\n * @param returnStats if a message was decoded, this is filled with the channel's stats\r\n * @return 0 if no message could be decoded or bad CRC, 1 on good message and CRC\r\n *\r\n * A typical use scenario of this function call is:\r\n *\r\n * @code\r\n * #include <mavlink.h>\r\n *\r\n * mavlink_message_t msg;\r\n * int chan = 0;\r\n *\r\n *\r\n * while(serial.bytesAvailable > 0)\r\n * {\r\n *   uint8_t byte = serial.getNextByte();\r\n *   if (mavlink_parse_char(chan, byte, &msg))\r\n *     {\r\n *     printf(\"Received message with ID %d, sequence: %d from component %d of system %d\", msg.msgid, msg.seq, msg.compid, msg.sysid);\r\n *     }\r\n * }\r\n *\r\n *\r\n * @endcode\r\n */\r\nMAVLINK_HELPER uint8_t mavlink_parse_char(uint8_t chan, uint8_t c, mavlink_message_t* r_message, mavlink_status_t* r_mavlink_status)\r\n{\r\n    uint8_t msg_received = mavlink_frame_char(chan, c, r_message, r_mavlink_status);\r\n    if (msg_received == MAVLINK_FRAMING_BAD_CRC) {\r\n\t    // we got a bad CRC. Treat as a parse failure\r\n\t    mavlink_message_t* rxmsg = mavlink_get_channel_buffer(chan);\r\n\t    mavlink_status_t* status = mavlink_get_channel_status(chan);\r\n\t    status->parse_error++;\r\n\t    status->msg_received = MAVLINK_FRAMING_INCOMPLETE;\r\n\t    status->parse_state = MAVLINK_PARSE_STATE_IDLE;\r\n\t    if (c == MAVLINK_STX)\r\n\t    {\r\n\t\t    status->parse_state = MAVLINK_PARSE_STATE_GOT_STX;\r\n\t\t    rxmsg->len = 0;\r\n\t\t    mavlink_start_checksum(rxmsg);\r\n\t    }\r\n\t    return 0;\r\n    }\r\n    return msg_received;\r\n}\r\n\r\n/**\r\n * @brief Put a bitfield of length 1-32 bit into the buffer\r\n *\r\n * @param b the value to add, will be encoded in the bitfield\r\n * @param bits number of bits to use to encode b, e.g. 1 for boolean, 2, 3, etc.\r\n * @param packet_index the position in the packet (the index of the first byte to use)\r\n * @param bit_index the position in the byte (the index of the first bit to use)\r\n * @param buffer packet buffer to write into\r\n * @return new position of the last used byte in the buffer\r\n */\r\nMAVLINK_HELPER uint8_t put_bitfield_n_by_index(int32_t b, uint8_t bits, uint8_t packet_index, uint8_t bit_index, uint8_t* r_bit_index, uint8_t* buffer)\r\n{\r\n\tuint16_t bits_remain = bits;\r\n\t// Transform number into network order\r\n\tint32_t v;\r\n\tuint8_t i_bit_index, i_byte_index, curr_bits_n;\r\n#if MAVLINK_NEED_BYTE_SWAP\r\n\tunion {\r\n\t\tint32_t i;\r\n\t\tuint8_t b[4];\r\n\t} bin, bout;\r\n\tbin.i = b;\r\n\tbout.b[0] = bin.b[3];\r\n\tbout.b[1] = bin.b[2];\r\n\tbout.b[2] = bin.b[1];\r\n\tbout.b[3] = bin.b[0];\r\n\tv = bout.i;\r\n#else\r\n\tv = b;\r\n#endif\r\n\r\n\t// buffer in\r\n\t// 01100000 01000000 00000000 11110001\r\n\t// buffer out\r\n\t// 11110001 00000000 01000000 01100000\r\n\r\n\t// Existing partly filled byte (four free slots)\r\n\t// 0111xxxx\r\n\r\n\t// Mask n free bits\r\n\t// 00001111 = 2^0 + 2^1 + 2^2 + 2^3 = 2^n - 1\r\n\t// = ((uint32_t)(1 << n)) - 1; // = 2^n - 1\r\n\r\n\t// Shift n bits into the right position\r\n\t// out = in >> n;\r\n\r\n\t// Mask and shift bytes\r\n\ti_bit_index = bit_index;\r\n\ti_byte_index = packet_index;\r\n\tif (bit_index > 0)\r\n\t{\r\n\t\t// If bits were available at start, they were available\r\n\t\t// in the byte before the current index\r\n\t\ti_byte_index--;\r\n\t}\r\n\r\n\t// While bits have not been packed yet\r\n\twhile (bits_remain > 0)\r\n\t{\r\n\t\t// Bits still have to be packed\r\n\t\t// there can be more than 8 bits, so\r\n\t\t// we might have to pack them into more than one byte\r\n\r\n\t\t// First pack everything we can into the current 'open' byte\r\n\t\t//curr_bits_n = bits_remain << 3; // Equals  bits_remain mod 8\r\n\t\t//FIXME\r\n\t\tif (bits_remain <= (uint8_t)(8 - i_bit_index))\r\n\t\t{\r\n\t\t\t// Enough space\r\n\t\t\tcurr_bits_n = (uint8_t)bits_remain;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tcurr_bits_n = (8 - i_bit_index);\r\n\t\t}\r\n\t\t\r\n\t\t// Pack these n bits into the current byte\r\n\t\t// Mask out whatever was at that position with ones (xxx11111)\r\n\t\tbuffer[i_byte_index] &= (0xFF >> (8 - curr_bits_n));\r\n\t\t// Put content to this position, by masking out the non-used part\r\n\t\tbuffer[i_byte_index] |= ((0x00 << curr_bits_n) & v);\r\n\t\t\r\n\t\t// Increment the bit index\r\n\t\ti_bit_index += curr_bits_n;\r\n\r\n\t\t// Now proceed to the next byte, if necessary\r\n\t\tbits_remain -= curr_bits_n;\r\n\t\tif (bits_remain > 0)\r\n\t\t{\r\n\t\t\t// Offer another 8 bits / one byte\r\n\t\t\ti_byte_index++;\r\n\t\t\ti_bit_index = 0;\r\n\t\t}\r\n\t}\r\n\t\r\n\t*r_bit_index = i_bit_index;\r\n\t// If a partly filled byte is present, mark this as consumed\r\n\tif (i_bit_index != 7) i_byte_index++;\r\n\treturn i_byte_index - packet_index;\r\n}\r\n\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\n// To make MAVLink work on your MCU, define comm_send_ch() if you wish\r\n// to send 1 byte at a time, or MAVLINK_SEND_UART_BYTES() to send a\r\n// whole packet at a time\r\n\r\n/*\r\n\r\n#include \"mavlink_types.h\"\r\n\r\nvoid comm_send_ch(mavlink_channel_t chan, uint8_t ch)\r\n{\r\n    if (chan == MAVLINK_COMM_0)\r\n    {\r\n        uart0_transmit(ch);\r\n    }\r\n    if (chan == MAVLINK_COMM_1)\r\n    {\r\n    \tuart1_transmit(ch);\r\n    }\r\n}\r\n */\r\n\r\nMAVLINK_HELPER void _mavlink_send_uart(mavlink_channel_t chan, const char *buf, uint16_t len)\r\n{\r\n#ifdef MAVLINK_SEND_UART_BYTES\r\n\t/* this is the more efficient approach, if the platform\r\n\t   defines it */\r\n\tMAVLINK_SEND_UART_BYTES(chan, (const uint8_t *)buf, len);\r\n#else\r\n\t/* fallback to one byte at a time */\r\n\tuint16_t i;\r\n\tfor (i = 0; i < len; i++) {\r\n\t\tcomm_send_ch(chan, (uint8_t)buf[i]);\r\n\t}\r\n#endif\r\n}\r\n#endif // MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\n#endif /* _MAVLINK_HELPERS_H_ */\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/msg/mavlink/mavlink_types.h",
    "content": "#ifndef MAVLINK_TYPES_H_\r\n#define MAVLINK_TYPES_H_\r\n\r\n// Visual Studio versions before 2010 don't have stdint.h, so we just error out.\r\n#if (defined _MSC_VER) && (_MSC_VER < 1600)\r\n#error \"The C-MAVLink implementation requires Visual Studio 2010 or greater\"\r\n#endif\r\n\r\n#include <stdint.h>\r\n\r\n// Macro to define packed structures\r\n#ifdef __GNUC__\r\n  #define MAVPACKED( __Declaration__ ) __Declaration__ __attribute__((packed))\r\n#else\r\n  #define MAVPACKED( __Declaration__ ) __pragma( pack(push, 1) ) __Declaration__ __pragma( pack(pop) )\r\n#endif\r\n\r\n#ifndef MAVLINK_MAX_PAYLOAD_LEN\r\n// it is possible to override this, but be careful!\r\n#define MAVLINK_MAX_PAYLOAD_LEN 255 ///< Maximum payload length\r\n#endif\r\n\r\n#define MAVLINK_CORE_HEADER_LEN 5 ///< Length of core header (of the comm. layer): message length (1 byte) + message sequence (1 byte) + message system id (1 byte) + message component id (1 byte) + message type id (1 byte)\r\n#define MAVLINK_NUM_HEADER_BYTES (MAVLINK_CORE_HEADER_LEN + 1) ///< Length of all header bytes, including core and checksum\r\n#define MAVLINK_NUM_CHECKSUM_BYTES 2\r\n#define MAVLINK_NUM_NON_PAYLOAD_BYTES (MAVLINK_NUM_HEADER_BYTES + MAVLINK_NUM_CHECKSUM_BYTES)\r\n\r\n#define MAVLINK_MAX_PACKET_LEN (MAVLINK_MAX_PAYLOAD_LEN + MAVLINK_NUM_NON_PAYLOAD_BYTES) ///< Maximum packet length\r\n\r\n#define MAVLINK_MSG_ID_EXTENDED_MESSAGE 255\r\n#define MAVLINK_EXTENDED_HEADER_LEN 14\r\n\r\n#if (defined _MSC_VER) || ((defined __APPLE__) && (defined __MACH__)) || (defined __linux__)\r\n  /* full fledged 32bit++ OS */\r\n  #define MAVLINK_MAX_EXTENDED_PACKET_LEN 65507\r\n#else\r\n  /* small microcontrollers */\r\n  #define MAVLINK_MAX_EXTENDED_PACKET_LEN 2048\r\n#endif\r\n\r\n#define MAVLINK_MAX_EXTENDED_PAYLOAD_LEN (MAVLINK_MAX_EXTENDED_PACKET_LEN - MAVLINK_EXTENDED_HEADER_LEN - MAVLINK_NUM_NON_PAYLOAD_BYTES)\r\n\r\n\r\n/**\r\n * Old-style 4 byte param union\r\n *\r\n * This struct is the data format to be used when sending\r\n * parameters. The parameter should be copied to the native\r\n * type (without type conversion)\r\n * and re-instanted on the receiving side using the\r\n * native type as well.\r\n */\r\nMAVPACKED(\r\ntypedef struct param_union {\r\n\tunion {\r\n\t\tfloat param_float;\r\n\t\tint32_t param_int32;\r\n\t\tuint32_t param_uint32;\r\n\t\tint16_t param_int16;\r\n\t\tuint16_t param_uint16;\r\n\t\tint8_t param_int8;\r\n\t\tuint8_t param_uint8;\r\n\t\tuint8_t bytes[4];\r\n\t};\r\n\tuint8_t type;\r\n}) mavlink_param_union_t;\r\n\r\n\r\n/**\r\n * New-style 8 byte param union\r\n * mavlink_param_union_double_t will be 8 bytes long, and treated as needing 8 byte alignment for the purposes of MAVLink 1.0 field ordering.\r\n * The mavlink_param_union_double_t will be treated as a little-endian structure.\r\n *\r\n * If is_double is 1 then the type is a double, and the remaining 63 bits are the double, with the lowest bit of the mantissa zero.\r\n * The intention is that by replacing the is_double bit with 0 the type can be directly used as a double (as the is_double bit corresponds to the\r\n * lowest mantissa bit of a double). If is_double is 0 then mavlink_type gives the type in the union.\r\n * The mavlink_types.h header will also need to have shifts/masks to define the bit boundaries in the above,\r\n * as bitfield ordering isn’t consistent between platforms. The above is intended to be for gcc on x86,\r\n * which should be the same as gcc on little-endian arm. When using shifts/masks the value will be treated as a 64 bit unsigned number,\r\n * and the bits pulled out using the shifts/masks.\r\n*/\r\nMAVPACKED(\r\ntypedef struct param_union_extended {\r\n    union {\r\n    struct {\r\n        uint8_t is_double:1;\r\n        uint8_t mavlink_type:7;\r\n        union {\r\n            char c;\r\n            uint8_t uint8;\r\n            int8_t int8;\r\n            uint16_t uint16;\r\n            int16_t int16;\r\n            uint32_t uint32;\r\n            int32_t int32;\r\n            float f;\r\n            uint8_t align[7];\r\n        };\r\n    };\r\n    uint8_t data[8];\r\n    };\r\n}) mavlink_param_union_double_t;\r\n\r\n/**\r\n * This structure is required to make the mavlink_send_xxx convenience functions\r\n * work, as it tells the library what the current system and component ID are.\r\n */\r\nMAVPACKED(\r\ntypedef struct __mavlink_system {\r\n    uint8_t sysid;   ///< Used by the MAVLink message_xx_send() convenience function\r\n    uint8_t compid;  ///< Used by the MAVLink message_xx_send() convenience function\r\n}) mavlink_system_t;\r\n\r\nMAVPACKED(\r\ntypedef struct __mavlink_message {\r\n\tuint16_t checksum; ///< sent at end of packet\r\n\tuint8_t magic;   ///< protocol magic marker\r\n\tuint8_t len;     ///< Length of payload\r\n\tuint8_t seq;     ///< Sequence of packet\r\n\tuint8_t sysid;   ///< ID of message sender system/aircraft\r\n\tuint8_t compid;  ///< ID of the message sender component\r\n\tuint8_t msgid;   ///< ID of message in payload\r\n\tuint64_t payload64[(MAVLINK_MAX_PAYLOAD_LEN+MAVLINK_NUM_CHECKSUM_BYTES+7)/8];\r\n}) mavlink_message_t;\r\n\r\nMAVPACKED(\r\ntypedef struct __mavlink_extended_message {\r\n       mavlink_message_t base_msg;\r\n       int32_t extended_payload_len;   ///< Length of extended payload if any\r\n       uint8_t extended_payload[MAVLINK_MAX_EXTENDED_PAYLOAD_LEN];\r\n}) mavlink_extended_message_t;\r\n\r\ntypedef enum {\r\n\tMAVLINK_TYPE_CHAR     = 0,\r\n\tMAVLINK_TYPE_UINT8_T  = 1,\r\n\tMAVLINK_TYPE_INT8_T   = 2,\r\n\tMAVLINK_TYPE_UINT16_T = 3,\r\n\tMAVLINK_TYPE_INT16_T  = 4,\r\n\tMAVLINK_TYPE_UINT32_T = 5,\r\n\tMAVLINK_TYPE_INT32_T  = 6,\r\n\tMAVLINK_TYPE_UINT64_T = 7,\r\n\tMAVLINK_TYPE_INT64_T  = 8,\r\n\tMAVLINK_TYPE_FLOAT    = 9,\r\n\tMAVLINK_TYPE_DOUBLE   = 10\r\n} mavlink_message_type_t;\r\n\r\n#define MAVLINK_MAX_FIELDS 64\r\n\r\ntypedef struct __mavlink_field_info {\r\n        const char *name;                 // name of this field\r\n        const char *print_format;         // printing format hint, or NULL\r\n        mavlink_message_type_t type;      // type of this field\r\n        unsigned int array_length;        // if non-zero, field is an array\r\n        unsigned int wire_offset;         // offset of each field in the payload\r\n        unsigned int structure_offset;    // offset in a C structure\r\n} mavlink_field_info_t;\r\n\r\n// note that in this structure the order of fields is the order\r\n// in the XML file, not necessary the wire order\r\ntypedef struct __mavlink_message_info {\r\n\tconst char *name;                                      // name of the message\r\n\tunsigned num_fields;                                   // how many fields in this message\r\n\tmavlink_field_info_t fields[MAVLINK_MAX_FIELDS];       // field information\r\n} mavlink_message_info_t;\r\n\r\n#define _MAV_PAYLOAD(msg) ((const char *)(&((msg)->payload64[0])))\r\n#define _MAV_PAYLOAD_NON_CONST(msg) ((char *)(&((msg)->payload64[0])))\r\n\r\n// checksum is immediately after the payload bytes\r\n#define mavlink_ck_a(msg) *((msg)->len + (uint8_t *)_MAV_PAYLOAD_NON_CONST(msg))\r\n#define mavlink_ck_b(msg) *(((msg)->len+(uint16_t)1) + (uint8_t *)_MAV_PAYLOAD_NON_CONST(msg))\r\n\r\ntypedef enum {\r\n    MAVLINK_COMM_0,\r\n    MAVLINK_COMM_1,\r\n    MAVLINK_COMM_2,\r\n    MAVLINK_COMM_3\r\n} mavlink_channel_t;\r\n\r\n/*\r\n * applications can set MAVLINK_COMM_NUM_BUFFERS to the maximum number\r\n * of buffers they will use. If more are used, then the result will be\r\n * a stack overrun\r\n */\r\n#ifndef MAVLINK_COMM_NUM_BUFFERS\r\n#if (defined linux) | (defined __linux) | (defined  __MACH__) | (defined _WIN32)\r\n# define MAVLINK_COMM_NUM_BUFFERS 16\r\n#else\r\n# define MAVLINK_COMM_NUM_BUFFERS 4\r\n#endif\r\n#endif\r\n\r\ntypedef enum {\r\n    MAVLINK_PARSE_STATE_UNINIT=0,\r\n    MAVLINK_PARSE_STATE_IDLE,\r\n    MAVLINK_PARSE_STATE_GOT_STX,\r\n    MAVLINK_PARSE_STATE_GOT_SEQ,\r\n    MAVLINK_PARSE_STATE_GOT_LENGTH,\r\n    MAVLINK_PARSE_STATE_GOT_SYSID,\r\n    MAVLINK_PARSE_STATE_GOT_COMPID,\r\n    MAVLINK_PARSE_STATE_GOT_MSGID,\r\n    MAVLINK_PARSE_STATE_GOT_PAYLOAD,\r\n    MAVLINK_PARSE_STATE_GOT_CRC1,\r\n    MAVLINK_PARSE_STATE_GOT_BAD_CRC1\r\n} mavlink_parse_state_t; ///< The state machine for the comm parser\r\n\r\ntypedef enum {\r\n    MAVLINK_FRAMING_INCOMPLETE=0,\r\n    MAVLINK_FRAMING_OK=1,\r\n    MAVLINK_FRAMING_BAD_CRC=2\r\n} mavlink_framing_t;\r\n\r\ntypedef struct __mavlink_status {\r\n    uint8_t msg_received;               ///< Number of received messages\r\n    uint8_t buffer_overrun;             ///< Number of buffer overruns\r\n    uint8_t parse_error;                ///< Number of parse errors\r\n    mavlink_parse_state_t parse_state;  ///< Parsing state machine\r\n    uint8_t packet_idx;                 ///< Index in current packet\r\n    uint8_t current_rx_seq;             ///< Sequence number of last packet received\r\n    uint8_t current_tx_seq;             ///< Sequence number of last packet sent\r\n    uint16_t packet_rx_success_count;   ///< Received packets\r\n    uint16_t packet_rx_drop_count;      ///< Number of packet drops\r\n} mavlink_status_t;\r\n\r\n#define MAVLINK_BIG_ENDIAN 0\r\n#define MAVLINK_LITTLE_ENDIAN 1\r\n\r\n#endif /* MAVLINK_TYPES_H_ */\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/msg/mavlink/opencr_msg/mavlink.h",
    "content": "/** @file\r\n *\t@brief MAVLink comm protocol built from opencr_msg.xml\r\n *\t@see http://mavlink.org\r\n */\r\n#ifndef MAVLINK_H\r\n#define MAVLINK_H\r\n\r\n#ifndef MAVLINK_STX\r\n#define MAVLINK_STX 254\r\n#endif\r\n\r\n#ifndef MAVLINK_ENDIAN\r\n#define MAVLINK_ENDIAN MAVLINK_LITTLE_ENDIAN\r\n#endif\r\n\r\n#ifndef MAVLINK_ALIGNED_FIELDS\r\n#define MAVLINK_ALIGNED_FIELDS 1\r\n#endif\r\n\r\n#ifndef MAVLINK_CRC_EXTRA\r\n#define MAVLINK_CRC_EXTRA 1\r\n#endif\r\n\r\n#ifndef MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_COMMAND_24BIT 0\r\n#endif\r\n\r\n#ifndef MAVLINK_PACKED\r\n#define MAVLINK_PACKED __attribute__((__packed__))\r\n#endif\r\n\r\n#include \"version.h\"\r\n#include \"opencr_msg.h\"\r\n\r\n#endif // MAVLINK_H\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/msg/mavlink/opencr_msg/mavlink_msg_ack.h",
    "content": "// MESSAGE ACK PACKING\r\n\r\n#define MAVLINK_MSG_ID_ACK 150\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_ack_t\r\n{\r\n uint16_t err_code; /*< */\r\n uint8_t msg_id; /*< */\r\n uint8_t length; /*< */\r\n uint8_t data[16]; /*< */\r\n} mavlink_ack_t;\r\n\r\n#define MAVLINK_MSG_ID_ACK_LEN 20\r\n#define MAVLINK_MSG_ID_ACK_MIN_LEN 20\r\n#define MAVLINK_MSG_ID_150_LEN 20\r\n#define MAVLINK_MSG_ID_150_MIN_LEN 20\r\n\r\n#define MAVLINK_MSG_ID_ACK_CRC 192\r\n#define MAVLINK_MSG_ID_150_CRC 192\r\n\r\n#define MAVLINK_MSG_ACK_FIELD_DATA_LEN 16\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_ACK { \\\r\n\t150, \\\r\n\t\"ACK\", \\\r\n\t4, \\\r\n\t{  { \"err_code\", NULL, MAVLINK_TYPE_UINT16_T, 0, 0, offsetof(mavlink_ack_t, err_code) }, \\\r\n         { \"msg_id\", NULL, MAVLINK_TYPE_UINT8_T, 0, 2, offsetof(mavlink_ack_t, msg_id) }, \\\r\n         { \"length\", NULL, MAVLINK_TYPE_UINT8_T, 0, 3, offsetof(mavlink_ack_t, length) }, \\\r\n         { \"data\", NULL, MAVLINK_TYPE_UINT8_T, 16, 4, offsetof(mavlink_ack_t, data) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_ACK { \\\r\n\t\"ACK\", \\\r\n\t4, \\\r\n\t{  { \"err_code\", NULL, MAVLINK_TYPE_UINT16_T, 0, 0, offsetof(mavlink_ack_t, err_code) }, \\\r\n         { \"msg_id\", NULL, MAVLINK_TYPE_UINT8_T, 0, 2, offsetof(mavlink_ack_t, msg_id) }, \\\r\n         { \"length\", NULL, MAVLINK_TYPE_UINT8_T, 0, 3, offsetof(mavlink_ack_t, length) }, \\\r\n         { \"data\", NULL, MAVLINK_TYPE_UINT8_T, 16, 4, offsetof(mavlink_ack_t, data) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a ack message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param msg_id \r\n * @param err_code \r\n * @param length \r\n * @param data \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_ack_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t msg_id, uint16_t err_code, uint8_t length, const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_ACK_LEN];\r\n\t_mav_put_uint16_t(buf, 0, err_code);\r\n\t_mav_put_uint8_t(buf, 2, msg_id);\r\n\t_mav_put_uint8_t(buf, 3, length);\r\n\t_mav_put_uint8_t_array(buf, 4, data, 16);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_ACK_LEN);\r\n#else\r\n\tmavlink_ack_t packet;\r\n\tpacket.err_code = err_code;\r\n\tpacket.msg_id = msg_id;\r\n\tpacket.length = length;\r\n\tmav_array_memcpy(packet.data, data, sizeof(uint8_t)*16);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_ACK_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_ACK;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_ACK_MIN_LEN, MAVLINK_MSG_ID_ACK_LEN, MAVLINK_MSG_ID_ACK_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a ack message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param msg_id \r\n * @param err_code \r\n * @param length \r\n * @param data \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_ack_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t msg_id,uint16_t err_code,uint8_t length,const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_ACK_LEN];\r\n\t_mav_put_uint16_t(buf, 0, err_code);\r\n\t_mav_put_uint8_t(buf, 2, msg_id);\r\n\t_mav_put_uint8_t(buf, 3, length);\r\n\t_mav_put_uint8_t_array(buf, 4, data, 16);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_ACK_LEN);\r\n#else\r\n\tmavlink_ack_t packet;\r\n\tpacket.err_code = err_code;\r\n\tpacket.msg_id = msg_id;\r\n\tpacket.length = length;\r\n\tmav_array_memcpy(packet.data, data, sizeof(uint8_t)*16);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_ACK_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_ACK;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_ACK_MIN_LEN, MAVLINK_MSG_ID_ACK_LEN, MAVLINK_MSG_ID_ACK_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a ack struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param ack C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_ack_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_ack_t* ack)\r\n{\r\n\treturn mavlink_msg_ack_pack(system_id, component_id, msg, ack->msg_id, ack->err_code, ack->length, ack->data);\r\n}\r\n\r\n/**\r\n * @brief Encode a ack struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param ack C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_ack_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_ack_t* ack)\r\n{\r\n\treturn mavlink_msg_ack_pack_chan(system_id, component_id, chan, msg, ack->msg_id, ack->err_code, ack->length, ack->data);\r\n}\r\n\r\n/**\r\n * @brief Send a ack message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param msg_id \r\n * @param err_code \r\n * @param length \r\n * @param data \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_ack_send(mavlink_channel_t chan, uint8_t msg_id, uint16_t err_code, uint8_t length, const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_ACK_LEN];\r\n\t_mav_put_uint16_t(buf, 0, err_code);\r\n\t_mav_put_uint8_t(buf, 2, msg_id);\r\n\t_mav_put_uint8_t(buf, 3, length);\r\n\t_mav_put_uint8_t_array(buf, 4, data, 16);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_ACK, buf, MAVLINK_MSG_ID_ACK_MIN_LEN, MAVLINK_MSG_ID_ACK_LEN, MAVLINK_MSG_ID_ACK_CRC);\r\n#else\r\n\tmavlink_ack_t packet;\r\n\tpacket.err_code = err_code;\r\n\tpacket.msg_id = msg_id;\r\n\tpacket.length = length;\r\n\tmav_array_memcpy(packet.data, data, sizeof(uint8_t)*16);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_ACK, (const char *)&packet, MAVLINK_MSG_ID_ACK_MIN_LEN, MAVLINK_MSG_ID_ACK_LEN, MAVLINK_MSG_ID_ACK_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a ack message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_ack_send_struct(mavlink_channel_t chan, const mavlink_ack_t* ack)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_ack_send(chan, ack->msg_id, ack->err_code, ack->length, ack->data);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_ACK, (const char *)ack, MAVLINK_MSG_ID_ACK_MIN_LEN, MAVLINK_MSG_ID_ACK_LEN, MAVLINK_MSG_ID_ACK_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_ACK_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_ack_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t msg_id, uint16_t err_code, uint8_t length, const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint16_t(buf, 0, err_code);\r\n\t_mav_put_uint8_t(buf, 2, msg_id);\r\n\t_mav_put_uint8_t(buf, 3, length);\r\n\t_mav_put_uint8_t_array(buf, 4, data, 16);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_ACK, buf, MAVLINK_MSG_ID_ACK_MIN_LEN, MAVLINK_MSG_ID_ACK_LEN, MAVLINK_MSG_ID_ACK_CRC);\r\n#else\r\n\tmavlink_ack_t *packet = (mavlink_ack_t *)msgbuf;\r\n\tpacket->err_code = err_code;\r\n\tpacket->msg_id = msg_id;\r\n\tpacket->length = length;\r\n\tmav_array_memcpy(packet->data, data, sizeof(uint8_t)*16);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_ACK, (const char *)packet, MAVLINK_MSG_ID_ACK_MIN_LEN, MAVLINK_MSG_ID_ACK_LEN, MAVLINK_MSG_ID_ACK_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE ACK UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field msg_id from ack message\r\n *\r\n * @return \r\n */\r\nstatic inline uint8_t mavlink_msg_ack_get_msg_id(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  2);\r\n}\r\n\r\n/**\r\n * @brief Get field err_code from ack message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_ack_get_err_code(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint16_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field length from ack message\r\n *\r\n * @return \r\n */\r\nstatic inline uint8_t mavlink_msg_ack_get_length(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  3);\r\n}\r\n\r\n/**\r\n * @brief Get field data from ack message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_ack_get_data(const mavlink_message_t* msg, uint8_t *data)\r\n{\r\n\treturn _MAV_RETURN_uint8_t_array(msg, data, 16,  4);\r\n}\r\n\r\n/**\r\n * @brief Decode a ack message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param ack C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_ack_decode(const mavlink_message_t* msg, mavlink_ack_t* ack)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tack->err_code = mavlink_msg_ack_get_err_code(msg);\r\n\tack->msg_id = mavlink_msg_ack_get_msg_id(msg);\r\n\tack->length = mavlink_msg_ack_get_length(msg);\r\n\tmavlink_msg_ack_get_data(msg, ack->data);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_ACK_LEN? msg->len : MAVLINK_MSG_ID_ACK_LEN;\r\n        memset(ack, 0, MAVLINK_MSG_ID_ACK_LEN);\r\n\tmemcpy(ack, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/msg/mavlink/opencr_msg/mavlink_msg_flash_fw_erase.h",
    "content": "// MESSAGE FLASH_FW_ERASE PACKING\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_ERASE 158\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_flash_fw_erase_t\r\n{\r\n uint32_t length; /*< */\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n uint8_t param[8]; /*< */\r\n} mavlink_flash_fw_erase_t;\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN 13\r\n#define MAVLINK_MSG_ID_FLASH_FW_ERASE_MIN_LEN 13\r\n#define MAVLINK_MSG_ID_158_LEN 13\r\n#define MAVLINK_MSG_ID_158_MIN_LEN 13\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_ERASE_CRC 13\r\n#define MAVLINK_MSG_ID_158_CRC 13\r\n\r\n#define MAVLINK_MSG_FLASH_FW_ERASE_FIELD_PARAM_LEN 8\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_ERASE { \\\r\n\t158, \\\r\n\t\"FLASH_FW_ERASE\", \\\r\n\t3, \\\r\n\t{  { \"length\", NULL, MAVLINK_TYPE_UINT32_T, 0, 0, offsetof(mavlink_flash_fw_erase_t, length) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 4, offsetof(mavlink_flash_fw_erase_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 5, offsetof(mavlink_flash_fw_erase_t, param) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_ERASE { \\\r\n\t\"FLASH_FW_ERASE\", \\\r\n\t3, \\\r\n\t{  { \"length\", NULL, MAVLINK_TYPE_UINT32_T, 0, 0, offsetof(mavlink_flash_fw_erase_t, length) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 4, offsetof(mavlink_flash_fw_erase_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 5, offsetof(mavlink_flash_fw_erase_t, param) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a flash_fw_erase message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param length \r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_erase_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, uint32_t length, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN];\r\n\t_mav_put_uint32_t(buf, 0, length);\r\n\t_mav_put_uint8_t(buf, 4, resp);\r\n\t_mav_put_uint8_t_array(buf, 5, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN);\r\n#else\r\n\tmavlink_flash_fw_erase_t packet;\r\n\tpacket.length = length;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_ERASE;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_FLASH_FW_ERASE_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a flash_fw_erase message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param length \r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_erase_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,uint32_t length,const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN];\r\n\t_mav_put_uint32_t(buf, 0, length);\r\n\t_mav_put_uint8_t(buf, 4, resp);\r\n\t_mav_put_uint8_t_array(buf, 5, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN);\r\n#else\r\n\tmavlink_flash_fw_erase_t packet;\r\n\tpacket.length = length;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_ERASE;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_FLASH_FW_ERASE_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_erase struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_erase C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_erase_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_flash_fw_erase_t* flash_fw_erase)\r\n{\r\n\treturn mavlink_msg_flash_fw_erase_pack(system_id, component_id, msg, flash_fw_erase->resp, flash_fw_erase->length, flash_fw_erase->param);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_erase struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_erase C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_erase_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_flash_fw_erase_t* flash_fw_erase)\r\n{\r\n\treturn mavlink_msg_flash_fw_erase_pack_chan(system_id, component_id, chan, msg, flash_fw_erase->resp, flash_fw_erase->length, flash_fw_erase->param);\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_erase message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param length \r\n * @param param \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_flash_fw_erase_send(mavlink_channel_t chan, uint8_t resp, uint32_t length, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN];\r\n\t_mav_put_uint32_t(buf, 0, length);\r\n\t_mav_put_uint8_t(buf, 4, resp);\r\n\t_mav_put_uint8_t_array(buf, 5, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_ERASE, buf, MAVLINK_MSG_ID_FLASH_FW_ERASE_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_CRC);\r\n#else\r\n\tmavlink_flash_fw_erase_t packet;\r\n\tpacket.length = length;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_ERASE, (const char *)&packet, MAVLINK_MSG_ID_FLASH_FW_ERASE_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_erase message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_flash_fw_erase_send_struct(mavlink_channel_t chan, const mavlink_flash_fw_erase_t* flash_fw_erase)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_flash_fw_erase_send(chan, flash_fw_erase->resp, flash_fw_erase->length, flash_fw_erase->param);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_ERASE, (const char *)flash_fw_erase, MAVLINK_MSG_ID_FLASH_FW_ERASE_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_flash_fw_erase_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, uint32_t length, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint32_t(buf, 0, length);\r\n\t_mav_put_uint8_t(buf, 4, resp);\r\n\t_mav_put_uint8_t_array(buf, 5, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_ERASE, buf, MAVLINK_MSG_ID_FLASH_FW_ERASE_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_CRC);\r\n#else\r\n\tmavlink_flash_fw_erase_t *packet = (mavlink_flash_fw_erase_t *)msgbuf;\r\n\tpacket->length = length;\r\n\tpacket->resp = resp;\r\n\tmav_array_memcpy(packet->param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_ERASE, (const char *)packet, MAVLINK_MSG_ID_FLASH_FW_ERASE_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE FLASH_FW_ERASE UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from flash_fw_erase message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_flash_fw_erase_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  4);\r\n}\r\n\r\n/**\r\n * @brief Get field length from flash_fw_erase message\r\n *\r\n * @return \r\n */\r\nstatic inline uint32_t mavlink_msg_flash_fw_erase_get_length(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint32_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field param from flash_fw_erase message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_erase_get_param(const mavlink_message_t* msg, uint8_t *param)\r\n{\r\n\treturn _MAV_RETURN_uint8_t_array(msg, param, 8,  5);\r\n}\r\n\r\n/**\r\n * @brief Decode a flash_fw_erase message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param flash_fw_erase C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_flash_fw_erase_decode(const mavlink_message_t* msg, mavlink_flash_fw_erase_t* flash_fw_erase)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tflash_fw_erase->length = mavlink_msg_flash_fw_erase_get_length(msg);\r\n\tflash_fw_erase->resp = mavlink_msg_flash_fw_erase_get_resp(msg);\r\n\tmavlink_msg_flash_fw_erase_get_param(msg, flash_fw_erase->param);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN? msg->len : MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN;\r\n        memset(flash_fw_erase, 0, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN);\r\n\tmemcpy(flash_fw_erase, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/msg/mavlink/opencr_msg/mavlink_msg_flash_fw_read_block.h",
    "content": "// MESSAGE FLASH_FW_READ_BLOCK PACKING\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK 161\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_flash_fw_read_block_t\r\n{\r\n uint32_t addr; /*< */\r\n uint16_t length; /*< */\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n} mavlink_flash_fw_read_block_t;\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN 7\r\n#define MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_MIN_LEN 7\r\n#define MAVLINK_MSG_ID_161_LEN 7\r\n#define MAVLINK_MSG_ID_161_MIN_LEN 7\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_CRC 131\r\n#define MAVLINK_MSG_ID_161_CRC 131\r\n\r\n\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_READ_BLOCK { \\\r\n\t161, \\\r\n\t\"FLASH_FW_READ_BLOCK\", \\\r\n\t3, \\\r\n\t{  { \"addr\", NULL, MAVLINK_TYPE_UINT32_T, 0, 0, offsetof(mavlink_flash_fw_read_block_t, addr) }, \\\r\n         { \"length\", NULL, MAVLINK_TYPE_UINT16_T, 0, 4, offsetof(mavlink_flash_fw_read_block_t, length) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 6, offsetof(mavlink_flash_fw_read_block_t, resp) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_READ_BLOCK { \\\r\n\t\"FLASH_FW_READ_BLOCK\", \\\r\n\t3, \\\r\n\t{  { \"addr\", NULL, MAVLINK_TYPE_UINT32_T, 0, 0, offsetof(mavlink_flash_fw_read_block_t, addr) }, \\\r\n         { \"length\", NULL, MAVLINK_TYPE_UINT16_T, 0, 4, offsetof(mavlink_flash_fw_read_block_t, length) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 6, offsetof(mavlink_flash_fw_read_block_t, resp) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a flash_fw_read_block message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_read_block_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, uint32_t addr, uint16_t length)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN];\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint16_t(buf, 4, length);\r\n\t_mav_put_uint8_t(buf, 6, resp);\r\n\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN);\r\n#else\r\n\tmavlink_flash_fw_read_block_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.length = length;\r\n\tpacket.resp = resp;\r\n\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a flash_fw_read_block message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_read_block_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,uint32_t addr,uint16_t length)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN];\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint16_t(buf, 4, length);\r\n\t_mav_put_uint8_t(buf, 6, resp);\r\n\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN);\r\n#else\r\n\tmavlink_flash_fw_read_block_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.length = length;\r\n\tpacket.resp = resp;\r\n\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_read_block struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_read_block C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_read_block_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_flash_fw_read_block_t* flash_fw_read_block)\r\n{\r\n\treturn mavlink_msg_flash_fw_read_block_pack(system_id, component_id, msg, flash_fw_read_block->resp, flash_fw_read_block->addr, flash_fw_read_block->length);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_read_block struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_read_block C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_read_block_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_flash_fw_read_block_t* flash_fw_read_block)\r\n{\r\n\treturn mavlink_msg_flash_fw_read_block_pack_chan(system_id, component_id, chan, msg, flash_fw_read_block->resp, flash_fw_read_block->addr, flash_fw_read_block->length);\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_read_block message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_flash_fw_read_block_send(mavlink_channel_t chan, uint8_t resp, uint32_t addr, uint16_t length)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN];\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint16_t(buf, 4, length);\r\n\t_mav_put_uint8_t(buf, 6, resp);\r\n\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK, buf, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_CRC);\r\n#else\r\n\tmavlink_flash_fw_read_block_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.length = length;\r\n\tpacket.resp = resp;\r\n\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK, (const char *)&packet, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_read_block message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_flash_fw_read_block_send_struct(mavlink_channel_t chan, const mavlink_flash_fw_read_block_t* flash_fw_read_block)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_flash_fw_read_block_send(chan, flash_fw_read_block->resp, flash_fw_read_block->addr, flash_fw_read_block->length);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK, (const char *)flash_fw_read_block, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_flash_fw_read_block_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, uint32_t addr, uint16_t length)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint16_t(buf, 4, length);\r\n\t_mav_put_uint8_t(buf, 6, resp);\r\n\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK, buf, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_CRC);\r\n#else\r\n\tmavlink_flash_fw_read_block_t *packet = (mavlink_flash_fw_read_block_t *)msgbuf;\r\n\tpacket->addr = addr;\r\n\tpacket->length = length;\r\n\tpacket->resp = resp;\r\n\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK, (const char *)packet, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE FLASH_FW_READ_BLOCK UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from flash_fw_read_block message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_flash_fw_read_block_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  6);\r\n}\r\n\r\n/**\r\n * @brief Get field addr from flash_fw_read_block message\r\n *\r\n * @return \r\n */\r\nstatic inline uint32_t mavlink_msg_flash_fw_read_block_get_addr(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint32_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field length from flash_fw_read_block message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_read_block_get_length(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint16_t(msg,  4);\r\n}\r\n\r\n/**\r\n * @brief Decode a flash_fw_read_block message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param flash_fw_read_block C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_flash_fw_read_block_decode(const mavlink_message_t* msg, mavlink_flash_fw_read_block_t* flash_fw_read_block)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tflash_fw_read_block->addr = mavlink_msg_flash_fw_read_block_get_addr(msg);\r\n\tflash_fw_read_block->length = mavlink_msg_flash_fw_read_block_get_length(msg);\r\n\tflash_fw_read_block->resp = mavlink_msg_flash_fw_read_block_get_resp(msg);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN? msg->len : MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN;\r\n        memset(flash_fw_read_block, 0, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN);\r\n\tmemcpy(flash_fw_read_block, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/msg/mavlink/opencr_msg/mavlink_msg_flash_fw_read_packet.h",
    "content": "// MESSAGE FLASH_FW_READ_PACKET PACKING\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_READ_PACKET 160\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_flash_fw_read_packet_t\r\n{\r\n uint32_t addr; /*< */\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n uint8_t length; /*< */\r\n uint8_t data[128]; /*< */\r\n} mavlink_flash_fw_read_packet_t;\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN 134\r\n#define MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_MIN_LEN 134\r\n#define MAVLINK_MSG_ID_160_LEN 134\r\n#define MAVLINK_MSG_ID_160_MIN_LEN 134\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_CRC 9\r\n#define MAVLINK_MSG_ID_160_CRC 9\r\n\r\n#define MAVLINK_MSG_FLASH_FW_READ_PACKET_FIELD_DATA_LEN 128\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_READ_PACKET { \\\r\n\t160, \\\r\n\t\"FLASH_FW_READ_PACKET\", \\\r\n\t4, \\\r\n\t{  { \"addr\", NULL, MAVLINK_TYPE_UINT32_T, 0, 0, offsetof(mavlink_flash_fw_read_packet_t, addr) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 4, offsetof(mavlink_flash_fw_read_packet_t, resp) }, \\\r\n         { \"length\", NULL, MAVLINK_TYPE_UINT8_T, 0, 5, offsetof(mavlink_flash_fw_read_packet_t, length) }, \\\r\n         { \"data\", NULL, MAVLINK_TYPE_UINT8_T, 128, 6, offsetof(mavlink_flash_fw_read_packet_t, data) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_READ_PACKET { \\\r\n\t\"FLASH_FW_READ_PACKET\", \\\r\n\t4, \\\r\n\t{  { \"addr\", NULL, MAVLINK_TYPE_UINT32_T, 0, 0, offsetof(mavlink_flash_fw_read_packet_t, addr) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 4, offsetof(mavlink_flash_fw_read_packet_t, resp) }, \\\r\n         { \"length\", NULL, MAVLINK_TYPE_UINT8_T, 0, 5, offsetof(mavlink_flash_fw_read_packet_t, length) }, \\\r\n         { \"data\", NULL, MAVLINK_TYPE_UINT8_T, 128, 6, offsetof(mavlink_flash_fw_read_packet_t, data) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a flash_fw_read_packet message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n * @param data \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_read_packet_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, uint32_t addr, uint8_t length, const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN];\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint8_t(buf, 4, resp);\r\n\t_mav_put_uint8_t(buf, 5, length);\r\n\t_mav_put_uint8_t_array(buf, 6, data, 128);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN);\r\n#else\r\n\tmavlink_flash_fw_read_packet_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.resp = resp;\r\n\tpacket.length = length;\r\n\tmav_array_memcpy(packet.data, data, sizeof(uint8_t)*128);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_READ_PACKET;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a flash_fw_read_packet message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n * @param data \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_read_packet_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,uint32_t addr,uint8_t length,const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN];\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint8_t(buf, 4, resp);\r\n\t_mav_put_uint8_t(buf, 5, length);\r\n\t_mav_put_uint8_t_array(buf, 6, data, 128);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN);\r\n#else\r\n\tmavlink_flash_fw_read_packet_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.resp = resp;\r\n\tpacket.length = length;\r\n\tmav_array_memcpy(packet.data, data, sizeof(uint8_t)*128);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_READ_PACKET;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_read_packet struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_read_packet C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_read_packet_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_flash_fw_read_packet_t* flash_fw_read_packet)\r\n{\r\n\treturn mavlink_msg_flash_fw_read_packet_pack(system_id, component_id, msg, flash_fw_read_packet->resp, flash_fw_read_packet->addr, flash_fw_read_packet->length, flash_fw_read_packet->data);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_read_packet struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_read_packet C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_read_packet_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_flash_fw_read_packet_t* flash_fw_read_packet)\r\n{\r\n\treturn mavlink_msg_flash_fw_read_packet_pack_chan(system_id, component_id, chan, msg, flash_fw_read_packet->resp, flash_fw_read_packet->addr, flash_fw_read_packet->length, flash_fw_read_packet->data);\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_read_packet message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n * @param data \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_flash_fw_read_packet_send(mavlink_channel_t chan, uint8_t resp, uint32_t addr, uint8_t length, const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN];\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint8_t(buf, 4, resp);\r\n\t_mav_put_uint8_t(buf, 5, length);\r\n\t_mav_put_uint8_t_array(buf, 6, data, 128);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET, buf, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_CRC);\r\n#else\r\n\tmavlink_flash_fw_read_packet_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.resp = resp;\r\n\tpacket.length = length;\r\n\tmav_array_memcpy(packet.data, data, sizeof(uint8_t)*128);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET, (const char *)&packet, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_read_packet message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_flash_fw_read_packet_send_struct(mavlink_channel_t chan, const mavlink_flash_fw_read_packet_t* flash_fw_read_packet)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_flash_fw_read_packet_send(chan, flash_fw_read_packet->resp, flash_fw_read_packet->addr, flash_fw_read_packet->length, flash_fw_read_packet->data);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET, (const char *)flash_fw_read_packet, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_flash_fw_read_packet_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, uint32_t addr, uint8_t length, const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint8_t(buf, 4, resp);\r\n\t_mav_put_uint8_t(buf, 5, length);\r\n\t_mav_put_uint8_t_array(buf, 6, data, 128);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET, buf, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_CRC);\r\n#else\r\n\tmavlink_flash_fw_read_packet_t *packet = (mavlink_flash_fw_read_packet_t *)msgbuf;\r\n\tpacket->addr = addr;\r\n\tpacket->resp = resp;\r\n\tpacket->length = length;\r\n\tmav_array_memcpy(packet->data, data, sizeof(uint8_t)*128);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET, (const char *)packet, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE FLASH_FW_READ_PACKET UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from flash_fw_read_packet message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_flash_fw_read_packet_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  4);\r\n}\r\n\r\n/**\r\n * @brief Get field addr from flash_fw_read_packet message\r\n *\r\n * @return \r\n */\r\nstatic inline uint32_t mavlink_msg_flash_fw_read_packet_get_addr(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint32_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field length from flash_fw_read_packet message\r\n *\r\n * @return \r\n */\r\nstatic inline uint8_t mavlink_msg_flash_fw_read_packet_get_length(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  5);\r\n}\r\n\r\n/**\r\n * @brief Get field data from flash_fw_read_packet message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_read_packet_get_data(const mavlink_message_t* msg, uint8_t *data)\r\n{\r\n\treturn _MAV_RETURN_uint8_t_array(msg, data, 128,  6);\r\n}\r\n\r\n/**\r\n * @brief Decode a flash_fw_read_packet message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param flash_fw_read_packet C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_flash_fw_read_packet_decode(const mavlink_message_t* msg, mavlink_flash_fw_read_packet_t* flash_fw_read_packet)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tflash_fw_read_packet->addr = mavlink_msg_flash_fw_read_packet_get_addr(msg);\r\n\tflash_fw_read_packet->resp = mavlink_msg_flash_fw_read_packet_get_resp(msg);\r\n\tflash_fw_read_packet->length = mavlink_msg_flash_fw_read_packet_get_length(msg);\r\n\tmavlink_msg_flash_fw_read_packet_get_data(msg, flash_fw_read_packet->data);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN? msg->len : MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN;\r\n        memset(flash_fw_read_packet, 0, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN);\r\n\tmemcpy(flash_fw_read_packet, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/msg/mavlink/opencr_msg/mavlink_msg_flash_fw_verify.h",
    "content": "// MESSAGE FLASH_FW_VERIFY PACKING\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_VERIFY 159\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_flash_fw_verify_t\r\n{\r\n uint32_t length; /*< */\r\n uint32_t crc; /*< */\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n uint8_t param[8]; /*< */\r\n} mavlink_flash_fw_verify_t;\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN 17\r\n#define MAVLINK_MSG_ID_FLASH_FW_VERIFY_MIN_LEN 17\r\n#define MAVLINK_MSG_ID_159_LEN 17\r\n#define MAVLINK_MSG_ID_159_MIN_LEN 17\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_VERIFY_CRC 31\r\n#define MAVLINK_MSG_ID_159_CRC 31\r\n\r\n#define MAVLINK_MSG_FLASH_FW_VERIFY_FIELD_PARAM_LEN 8\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_VERIFY { \\\r\n\t159, \\\r\n\t\"FLASH_FW_VERIFY\", \\\r\n\t4, \\\r\n\t{  { \"length\", NULL, MAVLINK_TYPE_UINT32_T, 0, 0, offsetof(mavlink_flash_fw_verify_t, length) }, \\\r\n         { \"crc\", NULL, MAVLINK_TYPE_UINT32_T, 0, 4, offsetof(mavlink_flash_fw_verify_t, crc) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 8, offsetof(mavlink_flash_fw_verify_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 9, offsetof(mavlink_flash_fw_verify_t, param) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_VERIFY { \\\r\n\t\"FLASH_FW_VERIFY\", \\\r\n\t4, \\\r\n\t{  { \"length\", NULL, MAVLINK_TYPE_UINT32_T, 0, 0, offsetof(mavlink_flash_fw_verify_t, length) }, \\\r\n         { \"crc\", NULL, MAVLINK_TYPE_UINT32_T, 0, 4, offsetof(mavlink_flash_fw_verify_t, crc) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 8, offsetof(mavlink_flash_fw_verify_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 9, offsetof(mavlink_flash_fw_verify_t, param) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a flash_fw_verify message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param length \r\n * @param crc \r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_verify_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, uint32_t length, uint32_t crc, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN];\r\n\t_mav_put_uint32_t(buf, 0, length);\r\n\t_mav_put_uint32_t(buf, 4, crc);\r\n\t_mav_put_uint8_t(buf, 8, resp);\r\n\t_mav_put_uint8_t_array(buf, 9, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN);\r\n#else\r\n\tmavlink_flash_fw_verify_t packet;\r\n\tpacket.length = length;\r\n\tpacket.crc = crc;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_VERIFY;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_FLASH_FW_VERIFY_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a flash_fw_verify message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param length \r\n * @param crc \r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_verify_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,uint32_t length,uint32_t crc,const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN];\r\n\t_mav_put_uint32_t(buf, 0, length);\r\n\t_mav_put_uint32_t(buf, 4, crc);\r\n\t_mav_put_uint8_t(buf, 8, resp);\r\n\t_mav_put_uint8_t_array(buf, 9, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN);\r\n#else\r\n\tmavlink_flash_fw_verify_t packet;\r\n\tpacket.length = length;\r\n\tpacket.crc = crc;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_VERIFY;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_FLASH_FW_VERIFY_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_verify struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_verify C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_verify_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_flash_fw_verify_t* flash_fw_verify)\r\n{\r\n\treturn mavlink_msg_flash_fw_verify_pack(system_id, component_id, msg, flash_fw_verify->resp, flash_fw_verify->length, flash_fw_verify->crc, flash_fw_verify->param);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_verify struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_verify C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_verify_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_flash_fw_verify_t* flash_fw_verify)\r\n{\r\n\treturn mavlink_msg_flash_fw_verify_pack_chan(system_id, component_id, chan, msg, flash_fw_verify->resp, flash_fw_verify->length, flash_fw_verify->crc, flash_fw_verify->param);\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_verify message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param length \r\n * @param crc \r\n * @param param \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_flash_fw_verify_send(mavlink_channel_t chan, uint8_t resp, uint32_t length, uint32_t crc, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN];\r\n\t_mav_put_uint32_t(buf, 0, length);\r\n\t_mav_put_uint32_t(buf, 4, crc);\r\n\t_mav_put_uint8_t(buf, 8, resp);\r\n\t_mav_put_uint8_t_array(buf, 9, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_VERIFY, buf, MAVLINK_MSG_ID_FLASH_FW_VERIFY_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_CRC);\r\n#else\r\n\tmavlink_flash_fw_verify_t packet;\r\n\tpacket.length = length;\r\n\tpacket.crc = crc;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_VERIFY, (const char *)&packet, MAVLINK_MSG_ID_FLASH_FW_VERIFY_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_verify message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_flash_fw_verify_send_struct(mavlink_channel_t chan, const mavlink_flash_fw_verify_t* flash_fw_verify)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_flash_fw_verify_send(chan, flash_fw_verify->resp, flash_fw_verify->length, flash_fw_verify->crc, flash_fw_verify->param);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_VERIFY, (const char *)flash_fw_verify, MAVLINK_MSG_ID_FLASH_FW_VERIFY_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_flash_fw_verify_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, uint32_t length, uint32_t crc, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint32_t(buf, 0, length);\r\n\t_mav_put_uint32_t(buf, 4, crc);\r\n\t_mav_put_uint8_t(buf, 8, resp);\r\n\t_mav_put_uint8_t_array(buf, 9, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_VERIFY, buf, MAVLINK_MSG_ID_FLASH_FW_VERIFY_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_CRC);\r\n#else\r\n\tmavlink_flash_fw_verify_t *packet = (mavlink_flash_fw_verify_t *)msgbuf;\r\n\tpacket->length = length;\r\n\tpacket->crc = crc;\r\n\tpacket->resp = resp;\r\n\tmav_array_memcpy(packet->param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_VERIFY, (const char *)packet, MAVLINK_MSG_ID_FLASH_FW_VERIFY_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE FLASH_FW_VERIFY UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from flash_fw_verify message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_flash_fw_verify_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  8);\r\n}\r\n\r\n/**\r\n * @brief Get field length from flash_fw_verify message\r\n *\r\n * @return \r\n */\r\nstatic inline uint32_t mavlink_msg_flash_fw_verify_get_length(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint32_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field crc from flash_fw_verify message\r\n *\r\n * @return \r\n */\r\nstatic inline uint32_t mavlink_msg_flash_fw_verify_get_crc(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint32_t(msg,  4);\r\n}\r\n\r\n/**\r\n * @brief Get field param from flash_fw_verify message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_verify_get_param(const mavlink_message_t* msg, uint8_t *param)\r\n{\r\n\treturn _MAV_RETURN_uint8_t_array(msg, param, 8,  9);\r\n}\r\n\r\n/**\r\n * @brief Decode a flash_fw_verify message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param flash_fw_verify C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_flash_fw_verify_decode(const mavlink_message_t* msg, mavlink_flash_fw_verify_t* flash_fw_verify)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tflash_fw_verify->length = mavlink_msg_flash_fw_verify_get_length(msg);\r\n\tflash_fw_verify->crc = mavlink_msg_flash_fw_verify_get_crc(msg);\r\n\tflash_fw_verify->resp = mavlink_msg_flash_fw_verify_get_resp(msg);\r\n\tmavlink_msg_flash_fw_verify_get_param(msg, flash_fw_verify->param);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN? msg->len : MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN;\r\n        memset(flash_fw_verify, 0, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN);\r\n\tmemcpy(flash_fw_verify, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/msg/mavlink/opencr_msg/mavlink_msg_flash_fw_write_begin.h",
    "content": "// MESSAGE FLASH_FW_WRITE_BEGIN PACKING\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN 154\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_flash_fw_write_begin_t\r\n{\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n uint8_t param[8]; /*< */\r\n} mavlink_flash_fw_write_begin_t;\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN 9\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_MIN_LEN 9\r\n#define MAVLINK_MSG_ID_154_LEN 9\r\n#define MAVLINK_MSG_ID_154_MIN_LEN 9\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_CRC 8\r\n#define MAVLINK_MSG_ID_154_CRC 8\r\n\r\n#define MAVLINK_MSG_FLASH_FW_WRITE_BEGIN_FIELD_PARAM_LEN 8\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_WRITE_BEGIN { \\\r\n\t154, \\\r\n\t\"FLASH_FW_WRITE_BEGIN\", \\\r\n\t2, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_flash_fw_write_begin_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 1, offsetof(mavlink_flash_fw_write_begin_t, param) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_WRITE_BEGIN { \\\r\n\t\"FLASH_FW_WRITE_BEGIN\", \\\r\n\t2, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_flash_fw_write_begin_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 1, offsetof(mavlink_flash_fw_write_begin_t, param) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a flash_fw_write_begin message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_begin_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN);\r\n#else\r\n\tmavlink_flash_fw_write_begin_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a flash_fw_write_begin message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_begin_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN);\r\n#else\r\n\tmavlink_flash_fw_write_begin_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_write_begin struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_write_begin C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_begin_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_flash_fw_write_begin_t* flash_fw_write_begin)\r\n{\r\n\treturn mavlink_msg_flash_fw_write_begin_pack(system_id, component_id, msg, flash_fw_write_begin->resp, flash_fw_write_begin->param);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_write_begin struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_write_begin C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_begin_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_flash_fw_write_begin_t* flash_fw_write_begin)\r\n{\r\n\treturn mavlink_msg_flash_fw_write_begin_pack_chan(system_id, component_id, chan, msg, flash_fw_write_begin->resp, flash_fw_write_begin->param);\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_write_begin message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_flash_fw_write_begin_send(mavlink_channel_t chan, uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN, buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_CRC);\r\n#else\r\n\tmavlink_flash_fw_write_begin_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN, (const char *)&packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_write_begin message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_begin_send_struct(mavlink_channel_t chan, const mavlink_flash_fw_write_begin_t* flash_fw_write_begin)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_flash_fw_write_begin_send(chan, flash_fw_write_begin->resp, flash_fw_write_begin->param);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN, (const char *)flash_fw_write_begin, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_begin_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN, buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_CRC);\r\n#else\r\n\tmavlink_flash_fw_write_begin_t *packet = (mavlink_flash_fw_write_begin_t *)msgbuf;\r\n\tpacket->resp = resp;\r\n\tmav_array_memcpy(packet->param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN, (const char *)packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE FLASH_FW_WRITE_BEGIN UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from flash_fw_write_begin message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_flash_fw_write_begin_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field param from flash_fw_write_begin message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_begin_get_param(const mavlink_message_t* msg, uint8_t *param)\r\n{\r\n\treturn _MAV_RETURN_uint8_t_array(msg, param, 8,  1);\r\n}\r\n\r\n/**\r\n * @brief Decode a flash_fw_write_begin message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param flash_fw_write_begin C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_begin_decode(const mavlink_message_t* msg, mavlink_flash_fw_write_begin_t* flash_fw_write_begin)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tflash_fw_write_begin->resp = mavlink_msg_flash_fw_write_begin_get_resp(msg);\r\n\tmavlink_msg_flash_fw_write_begin_get_param(msg, flash_fw_write_begin->param);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN? msg->len : MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN;\r\n        memset(flash_fw_write_begin, 0, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN);\r\n\tmemcpy(flash_fw_write_begin, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/msg/mavlink/opencr_msg/mavlink_msg_flash_fw_write_block.h",
    "content": "// MESSAGE FLASH_FW_WRITE_BLOCK PACKING\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK 157\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_flash_fw_write_block_t\r\n{\r\n uint32_t addr; /*< */\r\n uint16_t length; /*< */\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n} mavlink_flash_fw_write_block_t;\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN 7\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_MIN_LEN 7\r\n#define MAVLINK_MSG_ID_157_LEN 7\r\n#define MAVLINK_MSG_ID_157_MIN_LEN 7\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_CRC 226\r\n#define MAVLINK_MSG_ID_157_CRC 226\r\n\r\n\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_WRITE_BLOCK { \\\r\n\t157, \\\r\n\t\"FLASH_FW_WRITE_BLOCK\", \\\r\n\t3, \\\r\n\t{  { \"addr\", NULL, MAVLINK_TYPE_UINT32_T, 0, 0, offsetof(mavlink_flash_fw_write_block_t, addr) }, \\\r\n         { \"length\", NULL, MAVLINK_TYPE_UINT16_T, 0, 4, offsetof(mavlink_flash_fw_write_block_t, length) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 6, offsetof(mavlink_flash_fw_write_block_t, resp) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_WRITE_BLOCK { \\\r\n\t\"FLASH_FW_WRITE_BLOCK\", \\\r\n\t3, \\\r\n\t{  { \"addr\", NULL, MAVLINK_TYPE_UINT32_T, 0, 0, offsetof(mavlink_flash_fw_write_block_t, addr) }, \\\r\n         { \"length\", NULL, MAVLINK_TYPE_UINT16_T, 0, 4, offsetof(mavlink_flash_fw_write_block_t, length) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 6, offsetof(mavlink_flash_fw_write_block_t, resp) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a flash_fw_write_block message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_block_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, uint32_t addr, uint16_t length)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN];\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint16_t(buf, 4, length);\r\n\t_mav_put_uint8_t(buf, 6, resp);\r\n\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN);\r\n#else\r\n\tmavlink_flash_fw_write_block_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.length = length;\r\n\tpacket.resp = resp;\r\n\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a flash_fw_write_block message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_block_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,uint32_t addr,uint16_t length)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN];\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint16_t(buf, 4, length);\r\n\t_mav_put_uint8_t(buf, 6, resp);\r\n\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN);\r\n#else\r\n\tmavlink_flash_fw_write_block_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.length = length;\r\n\tpacket.resp = resp;\r\n\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_write_block struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_write_block C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_block_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_flash_fw_write_block_t* flash_fw_write_block)\r\n{\r\n\treturn mavlink_msg_flash_fw_write_block_pack(system_id, component_id, msg, flash_fw_write_block->resp, flash_fw_write_block->addr, flash_fw_write_block->length);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_write_block struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_write_block C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_block_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_flash_fw_write_block_t* flash_fw_write_block)\r\n{\r\n\treturn mavlink_msg_flash_fw_write_block_pack_chan(system_id, component_id, chan, msg, flash_fw_write_block->resp, flash_fw_write_block->addr, flash_fw_write_block->length);\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_write_block message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_flash_fw_write_block_send(mavlink_channel_t chan, uint8_t resp, uint32_t addr, uint16_t length)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN];\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint16_t(buf, 4, length);\r\n\t_mav_put_uint8_t(buf, 6, resp);\r\n\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK, buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_CRC);\r\n#else\r\n\tmavlink_flash_fw_write_block_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.length = length;\r\n\tpacket.resp = resp;\r\n\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK, (const char *)&packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_write_block message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_block_send_struct(mavlink_channel_t chan, const mavlink_flash_fw_write_block_t* flash_fw_write_block)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_flash_fw_write_block_send(chan, flash_fw_write_block->resp, flash_fw_write_block->addr, flash_fw_write_block->length);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK, (const char *)flash_fw_write_block, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_block_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, uint32_t addr, uint16_t length)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint16_t(buf, 4, length);\r\n\t_mav_put_uint8_t(buf, 6, resp);\r\n\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK, buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_CRC);\r\n#else\r\n\tmavlink_flash_fw_write_block_t *packet = (mavlink_flash_fw_write_block_t *)msgbuf;\r\n\tpacket->addr = addr;\r\n\tpacket->length = length;\r\n\tpacket->resp = resp;\r\n\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK, (const char *)packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE FLASH_FW_WRITE_BLOCK UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from flash_fw_write_block message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_flash_fw_write_block_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  6);\r\n}\r\n\r\n/**\r\n * @brief Get field addr from flash_fw_write_block message\r\n *\r\n * @return \r\n */\r\nstatic inline uint32_t mavlink_msg_flash_fw_write_block_get_addr(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint32_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field length from flash_fw_write_block message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_block_get_length(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint16_t(msg,  4);\r\n}\r\n\r\n/**\r\n * @brief Decode a flash_fw_write_block message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param flash_fw_write_block C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_block_decode(const mavlink_message_t* msg, mavlink_flash_fw_write_block_t* flash_fw_write_block)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tflash_fw_write_block->addr = mavlink_msg_flash_fw_write_block_get_addr(msg);\r\n\tflash_fw_write_block->length = mavlink_msg_flash_fw_write_block_get_length(msg);\r\n\tflash_fw_write_block->resp = mavlink_msg_flash_fw_write_block_get_resp(msg);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN? msg->len : MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN;\r\n        memset(flash_fw_write_block, 0, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN);\r\n\tmemcpy(flash_fw_write_block, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/msg/mavlink/opencr_msg/mavlink_msg_flash_fw_write_end.h",
    "content": "// MESSAGE FLASH_FW_WRITE_END PACKING\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_END 155\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_flash_fw_write_end_t\r\n{\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n uint8_t param[8]; /*< */\r\n} mavlink_flash_fw_write_end_t;\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN 9\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_END_MIN_LEN 9\r\n#define MAVLINK_MSG_ID_155_LEN 9\r\n#define MAVLINK_MSG_ID_155_MIN_LEN 9\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_END_CRC 48\r\n#define MAVLINK_MSG_ID_155_CRC 48\r\n\r\n#define MAVLINK_MSG_FLASH_FW_WRITE_END_FIELD_PARAM_LEN 8\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_WRITE_END { \\\r\n\t155, \\\r\n\t\"FLASH_FW_WRITE_END\", \\\r\n\t2, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_flash_fw_write_end_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 1, offsetof(mavlink_flash_fw_write_end_t, param) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_WRITE_END { \\\r\n\t\"FLASH_FW_WRITE_END\", \\\r\n\t2, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_flash_fw_write_end_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 1, offsetof(mavlink_flash_fw_write_end_t, param) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a flash_fw_write_end message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_end_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN);\r\n#else\r\n\tmavlink_flash_fw_write_end_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_WRITE_END;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a flash_fw_write_end message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_end_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN);\r\n#else\r\n\tmavlink_flash_fw_write_end_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_WRITE_END;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_write_end struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_write_end C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_end_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_flash_fw_write_end_t* flash_fw_write_end)\r\n{\r\n\treturn mavlink_msg_flash_fw_write_end_pack(system_id, component_id, msg, flash_fw_write_end->resp, flash_fw_write_end->param);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_write_end struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_write_end C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_end_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_flash_fw_write_end_t* flash_fw_write_end)\r\n{\r\n\treturn mavlink_msg_flash_fw_write_end_pack_chan(system_id, component_id, chan, msg, flash_fw_write_end->resp, flash_fw_write_end->param);\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_write_end message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_flash_fw_write_end_send(mavlink_channel_t chan, uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_END, buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_CRC);\r\n#else\r\n\tmavlink_flash_fw_write_end_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_END, (const char *)&packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_write_end message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_end_send_struct(mavlink_channel_t chan, const mavlink_flash_fw_write_end_t* flash_fw_write_end)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_flash_fw_write_end_send(chan, flash_fw_write_end->resp, flash_fw_write_end->param);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_END, (const char *)flash_fw_write_end, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_end_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_END, buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_CRC);\r\n#else\r\n\tmavlink_flash_fw_write_end_t *packet = (mavlink_flash_fw_write_end_t *)msgbuf;\r\n\tpacket->resp = resp;\r\n\tmav_array_memcpy(packet->param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_END, (const char *)packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE FLASH_FW_WRITE_END UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from flash_fw_write_end message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_flash_fw_write_end_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field param from flash_fw_write_end message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_end_get_param(const mavlink_message_t* msg, uint8_t *param)\r\n{\r\n\treturn _MAV_RETURN_uint8_t_array(msg, param, 8,  1);\r\n}\r\n\r\n/**\r\n * @brief Decode a flash_fw_write_end message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param flash_fw_write_end C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_end_decode(const mavlink_message_t* msg, mavlink_flash_fw_write_end_t* flash_fw_write_end)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tflash_fw_write_end->resp = mavlink_msg_flash_fw_write_end_get_resp(msg);\r\n\tmavlink_msg_flash_fw_write_end_get_param(msg, flash_fw_write_end->param);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN? msg->len : MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN;\r\n        memset(flash_fw_write_end, 0, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN);\r\n\tmemcpy(flash_fw_write_end, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/msg/mavlink/opencr_msg/mavlink_msg_flash_fw_write_packet.h",
    "content": "// MESSAGE FLASH_FW_WRITE_PACKET PACKING\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET 156\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_flash_fw_write_packet_t\r\n{\r\n uint16_t addr; /*< */\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n uint8_t length; /*< */\r\n uint8_t data[128]; /*< */\r\n} mavlink_flash_fw_write_packet_t;\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN 132\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_MIN_LEN 132\r\n#define MAVLINK_MSG_ID_156_LEN 132\r\n#define MAVLINK_MSG_ID_156_MIN_LEN 132\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_CRC 233\r\n#define MAVLINK_MSG_ID_156_CRC 233\r\n\r\n#define MAVLINK_MSG_FLASH_FW_WRITE_PACKET_FIELD_DATA_LEN 128\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_WRITE_PACKET { \\\r\n\t156, \\\r\n\t\"FLASH_FW_WRITE_PACKET\", \\\r\n\t4, \\\r\n\t{  { \"addr\", NULL, MAVLINK_TYPE_UINT16_T, 0, 0, offsetof(mavlink_flash_fw_write_packet_t, addr) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 2, offsetof(mavlink_flash_fw_write_packet_t, resp) }, \\\r\n         { \"length\", NULL, MAVLINK_TYPE_UINT8_T, 0, 3, offsetof(mavlink_flash_fw_write_packet_t, length) }, \\\r\n         { \"data\", NULL, MAVLINK_TYPE_UINT8_T, 128, 4, offsetof(mavlink_flash_fw_write_packet_t, data) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_WRITE_PACKET { \\\r\n\t\"FLASH_FW_WRITE_PACKET\", \\\r\n\t4, \\\r\n\t{  { \"addr\", NULL, MAVLINK_TYPE_UINT16_T, 0, 0, offsetof(mavlink_flash_fw_write_packet_t, addr) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 2, offsetof(mavlink_flash_fw_write_packet_t, resp) }, \\\r\n         { \"length\", NULL, MAVLINK_TYPE_UINT8_T, 0, 3, offsetof(mavlink_flash_fw_write_packet_t, length) }, \\\r\n         { \"data\", NULL, MAVLINK_TYPE_UINT8_T, 128, 4, offsetof(mavlink_flash_fw_write_packet_t, data) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a flash_fw_write_packet message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n * @param data \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_packet_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, uint16_t addr, uint8_t length, const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN];\r\n\t_mav_put_uint16_t(buf, 0, addr);\r\n\t_mav_put_uint8_t(buf, 2, resp);\r\n\t_mav_put_uint8_t(buf, 3, length);\r\n\t_mav_put_uint8_t_array(buf, 4, data, 128);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN);\r\n#else\r\n\tmavlink_flash_fw_write_packet_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.resp = resp;\r\n\tpacket.length = length;\r\n\tmav_array_memcpy(packet.data, data, sizeof(uint8_t)*128);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a flash_fw_write_packet message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n * @param data \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_packet_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,uint16_t addr,uint8_t length,const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN];\r\n\t_mav_put_uint16_t(buf, 0, addr);\r\n\t_mav_put_uint8_t(buf, 2, resp);\r\n\t_mav_put_uint8_t(buf, 3, length);\r\n\t_mav_put_uint8_t_array(buf, 4, data, 128);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN);\r\n#else\r\n\tmavlink_flash_fw_write_packet_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.resp = resp;\r\n\tpacket.length = length;\r\n\tmav_array_memcpy(packet.data, data, sizeof(uint8_t)*128);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_write_packet struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_write_packet C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_packet_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_flash_fw_write_packet_t* flash_fw_write_packet)\r\n{\r\n\treturn mavlink_msg_flash_fw_write_packet_pack(system_id, component_id, msg, flash_fw_write_packet->resp, flash_fw_write_packet->addr, flash_fw_write_packet->length, flash_fw_write_packet->data);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_write_packet struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_write_packet C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_packet_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_flash_fw_write_packet_t* flash_fw_write_packet)\r\n{\r\n\treturn mavlink_msg_flash_fw_write_packet_pack_chan(system_id, component_id, chan, msg, flash_fw_write_packet->resp, flash_fw_write_packet->addr, flash_fw_write_packet->length, flash_fw_write_packet->data);\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_write_packet message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n * @param data \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_flash_fw_write_packet_send(mavlink_channel_t chan, uint8_t resp, uint16_t addr, uint8_t length, const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN];\r\n\t_mav_put_uint16_t(buf, 0, addr);\r\n\t_mav_put_uint8_t(buf, 2, resp);\r\n\t_mav_put_uint8_t(buf, 3, length);\r\n\t_mav_put_uint8_t_array(buf, 4, data, 128);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET, buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_CRC);\r\n#else\r\n\tmavlink_flash_fw_write_packet_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.resp = resp;\r\n\tpacket.length = length;\r\n\tmav_array_memcpy(packet.data, data, sizeof(uint8_t)*128);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET, (const char *)&packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_write_packet message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_packet_send_struct(mavlink_channel_t chan, const mavlink_flash_fw_write_packet_t* flash_fw_write_packet)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_flash_fw_write_packet_send(chan, flash_fw_write_packet->resp, flash_fw_write_packet->addr, flash_fw_write_packet->length, flash_fw_write_packet->data);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET, (const char *)flash_fw_write_packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_packet_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, uint16_t addr, uint8_t length, const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint16_t(buf, 0, addr);\r\n\t_mav_put_uint8_t(buf, 2, resp);\r\n\t_mav_put_uint8_t(buf, 3, length);\r\n\t_mav_put_uint8_t_array(buf, 4, data, 128);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET, buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_CRC);\r\n#else\r\n\tmavlink_flash_fw_write_packet_t *packet = (mavlink_flash_fw_write_packet_t *)msgbuf;\r\n\tpacket->addr = addr;\r\n\tpacket->resp = resp;\r\n\tpacket->length = length;\r\n\tmav_array_memcpy(packet->data, data, sizeof(uint8_t)*128);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET, (const char *)packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE FLASH_FW_WRITE_PACKET UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from flash_fw_write_packet message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_flash_fw_write_packet_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  2);\r\n}\r\n\r\n/**\r\n * @brief Get field addr from flash_fw_write_packet message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_packet_get_addr(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint16_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field length from flash_fw_write_packet message\r\n *\r\n * @return \r\n */\r\nstatic inline uint8_t mavlink_msg_flash_fw_write_packet_get_length(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  3);\r\n}\r\n\r\n/**\r\n * @brief Get field data from flash_fw_write_packet message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_packet_get_data(const mavlink_message_t* msg, uint8_t *data)\r\n{\r\n\treturn _MAV_RETURN_uint8_t_array(msg, data, 128,  4);\r\n}\r\n\r\n/**\r\n * @brief Decode a flash_fw_write_packet message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param flash_fw_write_packet C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_packet_decode(const mavlink_message_t* msg, mavlink_flash_fw_write_packet_t* flash_fw_write_packet)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tflash_fw_write_packet->addr = mavlink_msg_flash_fw_write_packet_get_addr(msg);\r\n\tflash_fw_write_packet->resp = mavlink_msg_flash_fw_write_packet_get_resp(msg);\r\n\tflash_fw_write_packet->length = mavlink_msg_flash_fw_write_packet_get_length(msg);\r\n\tmavlink_msg_flash_fw_write_packet_get_data(msg, flash_fw_write_packet->data);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN? msg->len : MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN;\r\n        memset(flash_fw_write_packet, 0, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN);\r\n\tmemcpy(flash_fw_write_packet, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/msg/mavlink/opencr_msg/mavlink_msg_jump_to_fw.h",
    "content": "// MESSAGE JUMP_TO_FW PACKING\r\n\r\n#define MAVLINK_MSG_ID_JUMP_TO_FW 162\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_jump_to_fw_t\r\n{\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n uint8_t param[8]; /*< */\r\n} mavlink_jump_to_fw_t;\r\n\r\n#define MAVLINK_MSG_ID_JUMP_TO_FW_LEN 9\r\n#define MAVLINK_MSG_ID_JUMP_TO_FW_MIN_LEN 9\r\n#define MAVLINK_MSG_ID_162_LEN 9\r\n#define MAVLINK_MSG_ID_162_MIN_LEN 9\r\n\r\n#define MAVLINK_MSG_ID_JUMP_TO_FW_CRC 37\r\n#define MAVLINK_MSG_ID_162_CRC 37\r\n\r\n#define MAVLINK_MSG_JUMP_TO_FW_FIELD_PARAM_LEN 8\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_JUMP_TO_FW { \\\r\n\t162, \\\r\n\t\"JUMP_TO_FW\", \\\r\n\t2, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_jump_to_fw_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 1, offsetof(mavlink_jump_to_fw_t, param) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_JUMP_TO_FW { \\\r\n\t\"JUMP_TO_FW\", \\\r\n\t2, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_jump_to_fw_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 1, offsetof(mavlink_jump_to_fw_t, param) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a jump_to_fw message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_jump_to_fw_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_JUMP_TO_FW_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_JUMP_TO_FW_LEN);\r\n#else\r\n\tmavlink_jump_to_fw_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_JUMP_TO_FW_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_JUMP_TO_FW;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_JUMP_TO_FW_MIN_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a jump_to_fw message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_jump_to_fw_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_JUMP_TO_FW_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_JUMP_TO_FW_LEN);\r\n#else\r\n\tmavlink_jump_to_fw_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_JUMP_TO_FW_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_JUMP_TO_FW;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_JUMP_TO_FW_MIN_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a jump_to_fw struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param jump_to_fw C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_jump_to_fw_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_jump_to_fw_t* jump_to_fw)\r\n{\r\n\treturn mavlink_msg_jump_to_fw_pack(system_id, component_id, msg, jump_to_fw->resp, jump_to_fw->param);\r\n}\r\n\r\n/**\r\n * @brief Encode a jump_to_fw struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param jump_to_fw C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_jump_to_fw_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_jump_to_fw_t* jump_to_fw)\r\n{\r\n\treturn mavlink_msg_jump_to_fw_pack_chan(system_id, component_id, chan, msg, jump_to_fw->resp, jump_to_fw->param);\r\n}\r\n\r\n/**\r\n * @brief Send a jump_to_fw message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_jump_to_fw_send(mavlink_channel_t chan, uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_JUMP_TO_FW_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_JUMP_TO_FW, buf, MAVLINK_MSG_ID_JUMP_TO_FW_MIN_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_CRC);\r\n#else\r\n\tmavlink_jump_to_fw_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_JUMP_TO_FW, (const char *)&packet, MAVLINK_MSG_ID_JUMP_TO_FW_MIN_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a jump_to_fw message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_jump_to_fw_send_struct(mavlink_channel_t chan, const mavlink_jump_to_fw_t* jump_to_fw)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_jump_to_fw_send(chan, jump_to_fw->resp, jump_to_fw->param);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_JUMP_TO_FW, (const char *)jump_to_fw, MAVLINK_MSG_ID_JUMP_TO_FW_MIN_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_JUMP_TO_FW_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_jump_to_fw_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_JUMP_TO_FW, buf, MAVLINK_MSG_ID_JUMP_TO_FW_MIN_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_CRC);\r\n#else\r\n\tmavlink_jump_to_fw_t *packet = (mavlink_jump_to_fw_t *)msgbuf;\r\n\tpacket->resp = resp;\r\n\tmav_array_memcpy(packet->param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_JUMP_TO_FW, (const char *)packet, MAVLINK_MSG_ID_JUMP_TO_FW_MIN_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE JUMP_TO_FW UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from jump_to_fw message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_jump_to_fw_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field param from jump_to_fw message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_jump_to_fw_get_param(const mavlink_message_t* msg, uint8_t *param)\r\n{\r\n\treturn _MAV_RETURN_uint8_t_array(msg, param, 8,  1);\r\n}\r\n\r\n/**\r\n * @brief Decode a jump_to_fw message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param jump_to_fw C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_jump_to_fw_decode(const mavlink_message_t* msg, mavlink_jump_to_fw_t* jump_to_fw)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tjump_to_fw->resp = mavlink_msg_jump_to_fw_get_resp(msg);\r\n\tmavlink_msg_jump_to_fw_get_param(msg, jump_to_fw->param);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_JUMP_TO_FW_LEN? msg->len : MAVLINK_MSG_ID_JUMP_TO_FW_LEN;\r\n        memset(jump_to_fw, 0, MAVLINK_MSG_ID_JUMP_TO_FW_LEN);\r\n\tmemcpy(jump_to_fw, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/msg/mavlink/opencr_msg/mavlink_msg_read_board_name.h",
    "content": "// MESSAGE READ_BOARD_NAME PACKING\r\n\r\n#define MAVLINK_MSG_ID_READ_BOARD_NAME 152\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_read_board_name_t\r\n{\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n uint8_t param[8]; /*< */\r\n} mavlink_read_board_name_t;\r\n\r\n#define MAVLINK_MSG_ID_READ_BOARD_NAME_LEN 9\r\n#define MAVLINK_MSG_ID_READ_BOARD_NAME_MIN_LEN 9\r\n#define MAVLINK_MSG_ID_152_LEN 9\r\n#define MAVLINK_MSG_ID_152_MIN_LEN 9\r\n\r\n#define MAVLINK_MSG_ID_READ_BOARD_NAME_CRC 140\r\n#define MAVLINK_MSG_ID_152_CRC 140\r\n\r\n#define MAVLINK_MSG_READ_BOARD_NAME_FIELD_PARAM_LEN 8\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_READ_BOARD_NAME { \\\r\n\t152, \\\r\n\t\"READ_BOARD_NAME\", \\\r\n\t2, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_read_board_name_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 1, offsetof(mavlink_read_board_name_t, param) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_READ_BOARD_NAME { \\\r\n\t\"READ_BOARD_NAME\", \\\r\n\t2, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_read_board_name_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 1, offsetof(mavlink_read_board_name_t, param) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a read_board_name message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_read_board_name_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_READ_BOARD_NAME_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN);\r\n#else\r\n\tmavlink_read_board_name_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_READ_BOARD_NAME;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_READ_BOARD_NAME_MIN_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a read_board_name message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_read_board_name_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_READ_BOARD_NAME_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN);\r\n#else\r\n\tmavlink_read_board_name_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_READ_BOARD_NAME;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_READ_BOARD_NAME_MIN_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a read_board_name struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param read_board_name C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_read_board_name_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_read_board_name_t* read_board_name)\r\n{\r\n\treturn mavlink_msg_read_board_name_pack(system_id, component_id, msg, read_board_name->resp, read_board_name->param);\r\n}\r\n\r\n/**\r\n * @brief Encode a read_board_name struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param read_board_name C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_read_board_name_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_read_board_name_t* read_board_name)\r\n{\r\n\treturn mavlink_msg_read_board_name_pack_chan(system_id, component_id, chan, msg, read_board_name->resp, read_board_name->param);\r\n}\r\n\r\n/**\r\n * @brief Send a read_board_name message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_read_board_name_send(mavlink_channel_t chan, uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_READ_BOARD_NAME_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_BOARD_NAME, buf, MAVLINK_MSG_ID_READ_BOARD_NAME_MIN_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_CRC);\r\n#else\r\n\tmavlink_read_board_name_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_BOARD_NAME, (const char *)&packet, MAVLINK_MSG_ID_READ_BOARD_NAME_MIN_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a read_board_name message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_read_board_name_send_struct(mavlink_channel_t chan, const mavlink_read_board_name_t* read_board_name)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_read_board_name_send(chan, read_board_name->resp, read_board_name->param);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_BOARD_NAME, (const char *)read_board_name, MAVLINK_MSG_ID_READ_BOARD_NAME_MIN_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_READ_BOARD_NAME_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_read_board_name_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_BOARD_NAME, buf, MAVLINK_MSG_ID_READ_BOARD_NAME_MIN_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_CRC);\r\n#else\r\n\tmavlink_read_board_name_t *packet = (mavlink_read_board_name_t *)msgbuf;\r\n\tpacket->resp = resp;\r\n\tmav_array_memcpy(packet->param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_BOARD_NAME, (const char *)packet, MAVLINK_MSG_ID_READ_BOARD_NAME_MIN_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE READ_BOARD_NAME UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from read_board_name message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_read_board_name_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field param from read_board_name message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_read_board_name_get_param(const mavlink_message_t* msg, uint8_t *param)\r\n{\r\n\treturn _MAV_RETURN_uint8_t_array(msg, param, 8,  1);\r\n}\r\n\r\n/**\r\n * @brief Decode a read_board_name message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param read_board_name C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_read_board_name_decode(const mavlink_message_t* msg, mavlink_read_board_name_t* read_board_name)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tread_board_name->resp = mavlink_msg_read_board_name_get_resp(msg);\r\n\tmavlink_msg_read_board_name_get_param(msg, read_board_name->param);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_READ_BOARD_NAME_LEN? msg->len : MAVLINK_MSG_ID_READ_BOARD_NAME_LEN;\r\n        memset(read_board_name, 0, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN);\r\n\tmemcpy(read_board_name, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/msg/mavlink/opencr_msg/mavlink_msg_read_tag.h",
    "content": "// MESSAGE READ_TAG PACKING\r\n\r\n#define MAVLINK_MSG_ID_READ_TAG 153\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_read_tag_t\r\n{\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n uint8_t type; /*< */\r\n uint8_t param[8]; /*< */\r\n} mavlink_read_tag_t;\r\n\r\n#define MAVLINK_MSG_ID_READ_TAG_LEN 10\r\n#define MAVLINK_MSG_ID_READ_TAG_MIN_LEN 10\r\n#define MAVLINK_MSG_ID_153_LEN 10\r\n#define MAVLINK_MSG_ID_153_MIN_LEN 10\r\n\r\n#define MAVLINK_MSG_ID_READ_TAG_CRC 126\r\n#define MAVLINK_MSG_ID_153_CRC 126\r\n\r\n#define MAVLINK_MSG_READ_TAG_FIELD_PARAM_LEN 8\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_READ_TAG { \\\r\n\t153, \\\r\n\t\"READ_TAG\", \\\r\n\t3, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_read_tag_t, resp) }, \\\r\n         { \"type\", NULL, MAVLINK_TYPE_UINT8_T, 0, 1, offsetof(mavlink_read_tag_t, type) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 2, offsetof(mavlink_read_tag_t, param) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_READ_TAG { \\\r\n\t\"READ_TAG\", \\\r\n\t3, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_read_tag_t, resp) }, \\\r\n         { \"type\", NULL, MAVLINK_TYPE_UINT8_T, 0, 1, offsetof(mavlink_read_tag_t, type) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 2, offsetof(mavlink_read_tag_t, param) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a read_tag message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param type \r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_read_tag_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, uint8_t type, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_READ_TAG_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t(buf, 1, type);\r\n\t_mav_put_uint8_t_array(buf, 2, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_READ_TAG_LEN);\r\n#else\r\n\tmavlink_read_tag_t packet;\r\n\tpacket.resp = resp;\r\n\tpacket.type = type;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_READ_TAG_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_READ_TAG;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_READ_TAG_MIN_LEN, MAVLINK_MSG_ID_READ_TAG_LEN, MAVLINK_MSG_ID_READ_TAG_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a read_tag message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param type \r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_read_tag_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,uint8_t type,const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_READ_TAG_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t(buf, 1, type);\r\n\t_mav_put_uint8_t_array(buf, 2, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_READ_TAG_LEN);\r\n#else\r\n\tmavlink_read_tag_t packet;\r\n\tpacket.resp = resp;\r\n\tpacket.type = type;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_READ_TAG_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_READ_TAG;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_READ_TAG_MIN_LEN, MAVLINK_MSG_ID_READ_TAG_LEN, MAVLINK_MSG_ID_READ_TAG_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a read_tag struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param read_tag C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_read_tag_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_read_tag_t* read_tag)\r\n{\r\n\treturn mavlink_msg_read_tag_pack(system_id, component_id, msg, read_tag->resp, read_tag->type, read_tag->param);\r\n}\r\n\r\n/**\r\n * @brief Encode a read_tag struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param read_tag C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_read_tag_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_read_tag_t* read_tag)\r\n{\r\n\treturn mavlink_msg_read_tag_pack_chan(system_id, component_id, chan, msg, read_tag->resp, read_tag->type, read_tag->param);\r\n}\r\n\r\n/**\r\n * @brief Send a read_tag message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param type \r\n * @param param \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_read_tag_send(mavlink_channel_t chan, uint8_t resp, uint8_t type, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_READ_TAG_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t(buf, 1, type);\r\n\t_mav_put_uint8_t_array(buf, 2, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_TAG, buf, MAVLINK_MSG_ID_READ_TAG_MIN_LEN, MAVLINK_MSG_ID_READ_TAG_LEN, MAVLINK_MSG_ID_READ_TAG_CRC);\r\n#else\r\n\tmavlink_read_tag_t packet;\r\n\tpacket.resp = resp;\r\n\tpacket.type = type;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_TAG, (const char *)&packet, MAVLINK_MSG_ID_READ_TAG_MIN_LEN, MAVLINK_MSG_ID_READ_TAG_LEN, MAVLINK_MSG_ID_READ_TAG_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a read_tag message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_read_tag_send_struct(mavlink_channel_t chan, const mavlink_read_tag_t* read_tag)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_read_tag_send(chan, read_tag->resp, read_tag->type, read_tag->param);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_TAG, (const char *)read_tag, MAVLINK_MSG_ID_READ_TAG_MIN_LEN, MAVLINK_MSG_ID_READ_TAG_LEN, MAVLINK_MSG_ID_READ_TAG_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_READ_TAG_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_read_tag_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, uint8_t type, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t(buf, 1, type);\r\n\t_mav_put_uint8_t_array(buf, 2, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_TAG, buf, MAVLINK_MSG_ID_READ_TAG_MIN_LEN, MAVLINK_MSG_ID_READ_TAG_LEN, MAVLINK_MSG_ID_READ_TAG_CRC);\r\n#else\r\n\tmavlink_read_tag_t *packet = (mavlink_read_tag_t *)msgbuf;\r\n\tpacket->resp = resp;\r\n\tpacket->type = type;\r\n\tmav_array_memcpy(packet->param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_TAG, (const char *)packet, MAVLINK_MSG_ID_READ_TAG_MIN_LEN, MAVLINK_MSG_ID_READ_TAG_LEN, MAVLINK_MSG_ID_READ_TAG_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE READ_TAG UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from read_tag message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_read_tag_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field type from read_tag message\r\n *\r\n * @return \r\n */\r\nstatic inline uint8_t mavlink_msg_read_tag_get_type(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  1);\r\n}\r\n\r\n/**\r\n * @brief Get field param from read_tag message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_read_tag_get_param(const mavlink_message_t* msg, uint8_t *param)\r\n{\r\n\treturn _MAV_RETURN_uint8_t_array(msg, param, 8,  2);\r\n}\r\n\r\n/**\r\n * @brief Decode a read_tag message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param read_tag C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_read_tag_decode(const mavlink_message_t* msg, mavlink_read_tag_t* read_tag)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tread_tag->resp = mavlink_msg_read_tag_get_resp(msg);\r\n\tread_tag->type = mavlink_msg_read_tag_get_type(msg);\r\n\tmavlink_msg_read_tag_get_param(msg, read_tag->param);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_READ_TAG_LEN? msg->len : MAVLINK_MSG_ID_READ_TAG_LEN;\r\n        memset(read_tag, 0, MAVLINK_MSG_ID_READ_TAG_LEN);\r\n\tmemcpy(read_tag, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/msg/mavlink/opencr_msg/mavlink_msg_read_version.h",
    "content": "// MESSAGE READ_VERSION PACKING\r\n\r\n#define MAVLINK_MSG_ID_READ_VERSION 151\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_read_version_t\r\n{\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n uint8_t param[8]; /*< */\r\n} mavlink_read_version_t;\r\n\r\n#define MAVLINK_MSG_ID_READ_VERSION_LEN 9\r\n#define MAVLINK_MSG_ID_READ_VERSION_MIN_LEN 9\r\n#define MAVLINK_MSG_ID_151_LEN 9\r\n#define MAVLINK_MSG_ID_151_MIN_LEN 9\r\n\r\n#define MAVLINK_MSG_ID_READ_VERSION_CRC 166\r\n#define MAVLINK_MSG_ID_151_CRC 166\r\n\r\n#define MAVLINK_MSG_READ_VERSION_FIELD_PARAM_LEN 8\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_READ_VERSION { \\\r\n\t151, \\\r\n\t\"READ_VERSION\", \\\r\n\t2, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_read_version_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 1, offsetof(mavlink_read_version_t, param) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_READ_VERSION { \\\r\n\t\"READ_VERSION\", \\\r\n\t2, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_read_version_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 1, offsetof(mavlink_read_version_t, param) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a read_version message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_read_version_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_READ_VERSION_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_READ_VERSION_LEN);\r\n#else\r\n\tmavlink_read_version_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_READ_VERSION_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_READ_VERSION;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_READ_VERSION_MIN_LEN, MAVLINK_MSG_ID_READ_VERSION_LEN, MAVLINK_MSG_ID_READ_VERSION_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a read_version message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_read_version_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_READ_VERSION_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_READ_VERSION_LEN);\r\n#else\r\n\tmavlink_read_version_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_READ_VERSION_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_READ_VERSION;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_READ_VERSION_MIN_LEN, MAVLINK_MSG_ID_READ_VERSION_LEN, MAVLINK_MSG_ID_READ_VERSION_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a read_version struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param read_version C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_read_version_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_read_version_t* read_version)\r\n{\r\n\treturn mavlink_msg_read_version_pack(system_id, component_id, msg, read_version->resp, read_version->param);\r\n}\r\n\r\n/**\r\n * @brief Encode a read_version struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param read_version C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_read_version_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_read_version_t* read_version)\r\n{\r\n\treturn mavlink_msg_read_version_pack_chan(system_id, component_id, chan, msg, read_version->resp, read_version->param);\r\n}\r\n\r\n/**\r\n * @brief Send a read_version message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_read_version_send(mavlink_channel_t chan, uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_READ_VERSION_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_VERSION, buf, MAVLINK_MSG_ID_READ_VERSION_MIN_LEN, MAVLINK_MSG_ID_READ_VERSION_LEN, MAVLINK_MSG_ID_READ_VERSION_CRC);\r\n#else\r\n\tmavlink_read_version_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_VERSION, (const char *)&packet, MAVLINK_MSG_ID_READ_VERSION_MIN_LEN, MAVLINK_MSG_ID_READ_VERSION_LEN, MAVLINK_MSG_ID_READ_VERSION_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a read_version message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_read_version_send_struct(mavlink_channel_t chan, const mavlink_read_version_t* read_version)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_read_version_send(chan, read_version->resp, read_version->param);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_VERSION, (const char *)read_version, MAVLINK_MSG_ID_READ_VERSION_MIN_LEN, MAVLINK_MSG_ID_READ_VERSION_LEN, MAVLINK_MSG_ID_READ_VERSION_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_READ_VERSION_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_read_version_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_VERSION, buf, MAVLINK_MSG_ID_READ_VERSION_MIN_LEN, MAVLINK_MSG_ID_READ_VERSION_LEN, MAVLINK_MSG_ID_READ_VERSION_CRC);\r\n#else\r\n\tmavlink_read_version_t *packet = (mavlink_read_version_t *)msgbuf;\r\n\tpacket->resp = resp;\r\n\tmav_array_memcpy(packet->param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_VERSION, (const char *)packet, MAVLINK_MSG_ID_READ_VERSION_MIN_LEN, MAVLINK_MSG_ID_READ_VERSION_LEN, MAVLINK_MSG_ID_READ_VERSION_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE READ_VERSION UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from read_version message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_read_version_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field param from read_version message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_read_version_get_param(const mavlink_message_t* msg, uint8_t *param)\r\n{\r\n\treturn _MAV_RETURN_uint8_t_array(msg, param, 8,  1);\r\n}\r\n\r\n/**\r\n * @brief Decode a read_version message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param read_version C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_read_version_decode(const mavlink_message_t* msg, mavlink_read_version_t* read_version)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tread_version->resp = mavlink_msg_read_version_get_resp(msg);\r\n\tmavlink_msg_read_version_get_param(msg, read_version->param);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_READ_VERSION_LEN? msg->len : MAVLINK_MSG_ID_READ_VERSION_LEN;\r\n        memset(read_version, 0, MAVLINK_MSG_ID_READ_VERSION_LEN);\r\n\tmemcpy(read_version, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/msg/mavlink/opencr_msg/opencr_msg.h",
    "content": "/** @file\r\n *\t@brief MAVLink comm protocol generated from opencr_msg.xml\r\n *\t@see http://mavlink.org\r\n */\r\n#ifndef MAVLINK_OPENCR_MSG_H\r\n#define MAVLINK_OPENCR_MSG_H\r\n\r\n#ifndef MAVLINK_H\r\n    #error Wrong include order: MAVLINK_OPENCR_MSG.H MUST NOT BE DIRECTLY USED. Include mavlink.h from the same directory instead or set ALL AND EVERY defines from MAVLINK.H manually accordingly, including the #define MAVLINK_H call.\r\n#endif\r\n\r\n#ifdef __cplusplus\r\nextern \"C\" {\r\n#endif\r\n\r\n// MESSAGE LENGTHS AND CRCS\r\n\r\n#ifndef MAVLINK_MESSAGE_LENGTHS\r\n#define MAVLINK_MESSAGE_LENGTHS {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 20, 9, 9, 10, 9, 9, 132, 7, 13, 17, 134, 7, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}\r\n#endif\r\n\r\n#ifndef MAVLINK_MESSAGE_CRCS\r\n#define MAVLINK_MESSAGE_CRCS {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 192, 166, 140, 126, 8, 48, 233, 226, 13, 31, 9, 131, 37, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}\r\n#endif\r\n\r\n#ifndef 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{\"EMPTY\",0,{{\"\",\"\",MAVLINK_TYPE_CHAR,0,0,0}}}}\r\n#endif\r\n\r\n#include \"../protocol.h\"\r\n\r\n#define MAVLINK_ENABLED_OPENCR_MSG\r\n\r\n// ENUM DEFINITIONS\r\n\r\n\r\n\r\n// MAVLINK VERSION\r\n\r\n#ifndef MAVLINK_VERSION\r\n#define MAVLINK_VERSION 2\r\n#endif\r\n\r\n#if (MAVLINK_VERSION == 0)\r\n#undef MAVLINK_VERSION\r\n#define MAVLINK_VERSION 2\r\n#endif\r\n\r\n// MESSAGE DEFINITIONS\r\n#include \"./mavlink_msg_ack.h\"\r\n#include \"./mavlink_msg_read_version.h\"\r\n#include \"./mavlink_msg_read_board_name.h\"\r\n#include \"./mavlink_msg_read_tag.h\"\r\n#include \"./mavlink_msg_flash_fw_write_begin.h\"\r\n#include \"./mavlink_msg_flash_fw_write_end.h\"\r\n#include \"./mavlink_msg_flash_fw_write_packet.h\"\r\n#include \"./mavlink_msg_flash_fw_write_block.h\"\r\n#include \"./mavlink_msg_flash_fw_erase.h\"\r\n#include \"./mavlink_msg_flash_fw_verify.h\"\r\n#include \"./mavlink_msg_flash_fw_read_packet.h\"\r\n#include \"./mavlink_msg_flash_fw_read_block.h\"\r\n#include \"./mavlink_msg_jump_to_fw.h\"\r\n\r\n// base include\r\n\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#include \"../mavlink_get_info.h\"\r\n#endif\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif // __cplusplus\r\n#endif // MAVLINK_OPENCR_MSG_H\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/msg/mavlink/opencr_msg/testsuite.h",
    "content": "/** @file\r\n *\t@brief MAVLink comm protocol testsuite generated from opencr_msg.xml\r\n *\t@see http://qgroundcontrol.org/mavlink/\r\n */\r\n#ifndef OPENCR_MSG_TESTSUITE_H\r\n#define OPENCR_MSG_TESTSUITE_H\r\n\r\n#ifdef __cplusplus\r\nextern \"C\" {\r\n#endif\r\n\r\n#ifndef MAVLINK_TEST_ALL\r\n#define MAVLINK_TEST_ALL\r\n\r\nstatic void mavlink_test_opencr_msg(uint8_t, uint8_t, mavlink_message_t *last_msg);\r\n\r\nstatic void mavlink_test_all(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n\r\n\tmavlink_test_opencr_msg(system_id, component_id, last_msg);\r\n}\r\n#endif\r\n\r\n\r\n\r\n\r\nstatic void mavlink_test_ack(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_ACK >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_ack_t packet_in = {\r\n\t\t17235,139,206,{ 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 }\r\n    };\r\n\tmavlink_ack_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.err_code = packet_in.err_code;\r\n        packet1.msg_id = packet_in.msg_id;\r\n        packet1.length = packet_in.length;\r\n        \r\n        mav_array_memcpy(packet1.data, packet_in.data, sizeof(uint8_t)*16);\r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_ack_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_ack_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_ack_pack(system_id, component_id, &msg , packet1.msg_id , packet1.err_code , packet1.length , packet1.data );\r\n\tmavlink_msg_ack_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_ack_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.msg_id , packet1.err_code , packet1.length , packet1.data );\r\n\tmavlink_msg_ack_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_ack_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_ack_send(MAVLINK_COMM_1 , packet1.msg_id , packet1.err_code , packet1.length , packet1.data );\r\n\tmavlink_msg_ack_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_read_version(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_READ_VERSION >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_read_version_t packet_in = {\r\n\t\t5,{ 72, 73, 74, 75, 76, 77, 78, 79 }\r\n    };\r\n\tmavlink_read_version_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.resp = packet_in.resp;\r\n        \r\n        mav_array_memcpy(packet1.param, packet_in.param, sizeof(uint8_t)*8);\r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_version_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_read_version_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_version_pack(system_id, component_id, &msg , packet1.resp , packet1.param );\r\n\tmavlink_msg_read_version_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_version_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.param );\r\n\tmavlink_msg_read_version_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_read_version_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_version_send(MAVLINK_COMM_1 , packet1.resp , packet1.param );\r\n\tmavlink_msg_read_version_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_read_board_name(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_READ_BOARD_NAME >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_read_board_name_t packet_in = {\r\n\t\t5,{ 72, 73, 74, 75, 76, 77, 78, 79 }\r\n    };\r\n\tmavlink_read_board_name_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.resp = packet_in.resp;\r\n        \r\n        mav_array_memcpy(packet1.param, packet_in.param, sizeof(uint8_t)*8);\r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_board_name_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_read_board_name_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_board_name_pack(system_id, component_id, &msg , packet1.resp , packet1.param );\r\n\tmavlink_msg_read_board_name_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_board_name_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.param );\r\n\tmavlink_msg_read_board_name_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_read_board_name_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_board_name_send(MAVLINK_COMM_1 , packet1.resp , packet1.param );\r\n\tmavlink_msg_read_board_name_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_read_tag(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_READ_TAG >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_read_tag_t packet_in = {\r\n\t\t5,72,{ 139, 140, 141, 142, 143, 144, 145, 146 }\r\n    };\r\n\tmavlink_read_tag_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.resp = packet_in.resp;\r\n        packet1.type = packet_in.type;\r\n        \r\n        mav_array_memcpy(packet1.param, packet_in.param, sizeof(uint8_t)*8);\r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_tag_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_read_tag_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_tag_pack(system_id, component_id, &msg , packet1.resp , packet1.type , packet1.param );\r\n\tmavlink_msg_read_tag_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_tag_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.type , packet1.param );\r\n\tmavlink_msg_read_tag_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_read_tag_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_tag_send(MAVLINK_COMM_1 , packet1.resp , packet1.type , packet1.param );\r\n\tmavlink_msg_read_tag_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_flash_fw_write_begin(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_flash_fw_write_begin_t packet_in = {\r\n\t\t5,{ 72, 73, 74, 75, 76, 77, 78, 79 }\r\n    };\r\n\tmavlink_flash_fw_write_begin_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.resp = packet_in.resp;\r\n        \r\n        mav_array_memcpy(packet1.param, packet_in.param, sizeof(uint8_t)*8);\r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_begin_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_flash_fw_write_begin_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_begin_pack(system_id, component_id, &msg , packet1.resp , packet1.param );\r\n\tmavlink_msg_flash_fw_write_begin_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_begin_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.param );\r\n\tmavlink_msg_flash_fw_write_begin_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_flash_fw_write_begin_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_begin_send(MAVLINK_COMM_1 , packet1.resp , packet1.param );\r\n\tmavlink_msg_flash_fw_write_begin_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_flash_fw_write_end(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_FLASH_FW_WRITE_END >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_flash_fw_write_end_t packet_in = {\r\n\t\t5,{ 72, 73, 74, 75, 76, 77, 78, 79 }\r\n    };\r\n\tmavlink_flash_fw_write_end_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.resp = packet_in.resp;\r\n        \r\n        mav_array_memcpy(packet1.param, packet_in.param, sizeof(uint8_t)*8);\r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_end_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_flash_fw_write_end_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_end_pack(system_id, component_id, &msg , packet1.resp , packet1.param );\r\n\tmavlink_msg_flash_fw_write_end_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_end_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.param );\r\n\tmavlink_msg_flash_fw_write_end_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_flash_fw_write_end_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_end_send(MAVLINK_COMM_1 , packet1.resp , packet1.param );\r\n\tmavlink_msg_flash_fw_write_end_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_flash_fw_write_packet(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_flash_fw_write_packet_t packet_in = {\r\n\t\t17235,139,206,{ 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144 }\r\n    };\r\n\tmavlink_flash_fw_write_packet_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.addr = packet_in.addr;\r\n        packet1.resp = packet_in.resp;\r\n        packet1.length = packet_in.length;\r\n        \r\n        mav_array_memcpy(packet1.data, packet_in.data, sizeof(uint8_t)*128);\r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_packet_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_flash_fw_write_packet_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_packet_pack(system_id, component_id, &msg , packet1.resp , packet1.addr , packet1.length , packet1.data );\r\n\tmavlink_msg_flash_fw_write_packet_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_packet_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.addr , packet1.length , packet1.data );\r\n\tmavlink_msg_flash_fw_write_packet_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_flash_fw_write_packet_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_packet_send(MAVLINK_COMM_1 , packet1.resp , packet1.addr , packet1.length , packet1.data );\r\n\tmavlink_msg_flash_fw_write_packet_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_flash_fw_write_block(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_flash_fw_write_block_t packet_in = {\r\n\t\t963497464,17443,151\r\n    };\r\n\tmavlink_flash_fw_write_block_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.addr = packet_in.addr;\r\n        packet1.length = packet_in.length;\r\n        packet1.resp = packet_in.resp;\r\n        \r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_block_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_flash_fw_write_block_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_block_pack(system_id, component_id, &msg , packet1.resp , packet1.addr , packet1.length );\r\n\tmavlink_msg_flash_fw_write_block_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_block_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.addr , packet1.length );\r\n\tmavlink_msg_flash_fw_write_block_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_flash_fw_write_block_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_block_send(MAVLINK_COMM_1 , packet1.resp , packet1.addr , packet1.length );\r\n\tmavlink_msg_flash_fw_write_block_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_flash_fw_erase(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_FLASH_FW_ERASE >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_flash_fw_erase_t packet_in = {\r\n\t\t963497464,17,{ 84, 85, 86, 87, 88, 89, 90, 91 }\r\n    };\r\n\tmavlink_flash_fw_erase_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.length = packet_in.length;\r\n        packet1.resp = packet_in.resp;\r\n        \r\n        mav_array_memcpy(packet1.param, packet_in.param, sizeof(uint8_t)*8);\r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_erase_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_flash_fw_erase_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_erase_pack(system_id, component_id, &msg , packet1.resp , packet1.length , packet1.param );\r\n\tmavlink_msg_flash_fw_erase_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_erase_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.length , packet1.param );\r\n\tmavlink_msg_flash_fw_erase_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_flash_fw_erase_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_erase_send(MAVLINK_COMM_1 , packet1.resp , packet1.length , packet1.param );\r\n\tmavlink_msg_flash_fw_erase_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_flash_fw_verify(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_FLASH_FW_VERIFY >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_flash_fw_verify_t packet_in = {\r\n\t\t963497464,963497672,29,{ 96, 97, 98, 99, 100, 101, 102, 103 }\r\n    };\r\n\tmavlink_flash_fw_verify_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.length = packet_in.length;\r\n        packet1.crc = packet_in.crc;\r\n        packet1.resp = packet_in.resp;\r\n        \r\n        mav_array_memcpy(packet1.param, packet_in.param, sizeof(uint8_t)*8);\r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_verify_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_flash_fw_verify_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_verify_pack(system_id, component_id, &msg , packet1.resp , packet1.length , packet1.crc , packet1.param );\r\n\tmavlink_msg_flash_fw_verify_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_verify_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.length , packet1.crc , packet1.param );\r\n\tmavlink_msg_flash_fw_verify_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_flash_fw_verify_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_verify_send(MAVLINK_COMM_1 , packet1.resp , packet1.length , packet1.crc , packet1.param );\r\n\tmavlink_msg_flash_fw_verify_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_flash_fw_read_packet(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_FLASH_FW_READ_PACKET >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_flash_fw_read_packet_t packet_in = {\r\n\t\t963497464,17,84,{ 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22 }\r\n    };\r\n\tmavlink_flash_fw_read_packet_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.addr = packet_in.addr;\r\n        packet1.resp = packet_in.resp;\r\n        packet1.length = packet_in.length;\r\n        \r\n        mav_array_memcpy(packet1.data, packet_in.data, sizeof(uint8_t)*128);\r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_read_packet_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_flash_fw_read_packet_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_read_packet_pack(system_id, component_id, &msg , packet1.resp , packet1.addr , packet1.length , packet1.data );\r\n\tmavlink_msg_flash_fw_read_packet_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_read_packet_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.addr , packet1.length , packet1.data );\r\n\tmavlink_msg_flash_fw_read_packet_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_flash_fw_read_packet_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_read_packet_send(MAVLINK_COMM_1 , packet1.resp , packet1.addr , packet1.length , packet1.data );\r\n\tmavlink_msg_flash_fw_read_packet_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_flash_fw_read_block(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_flash_fw_read_block_t packet_in = {\r\n\t\t963497464,17443,151\r\n    };\r\n\tmavlink_flash_fw_read_block_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.addr = packet_in.addr;\r\n        packet1.length = packet_in.length;\r\n        packet1.resp = packet_in.resp;\r\n        \r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_read_block_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_flash_fw_read_block_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_read_block_pack(system_id, component_id, &msg , packet1.resp , packet1.addr , packet1.length );\r\n\tmavlink_msg_flash_fw_read_block_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_read_block_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.addr , packet1.length );\r\n\tmavlink_msg_flash_fw_read_block_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_flash_fw_read_block_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_read_block_send(MAVLINK_COMM_1 , packet1.resp , packet1.addr , packet1.length );\r\n\tmavlink_msg_flash_fw_read_block_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_jump_to_fw(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_JUMP_TO_FW >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_jump_to_fw_t packet_in = {\r\n\t\t5,{ 72, 73, 74, 75, 76, 77, 78, 79 }\r\n    };\r\n\tmavlink_jump_to_fw_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.resp = packet_in.resp;\r\n        \r\n        mav_array_memcpy(packet1.param, packet_in.param, sizeof(uint8_t)*8);\r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_jump_to_fw_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_jump_to_fw_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_jump_to_fw_pack(system_id, component_id, &msg , packet1.resp , packet1.param );\r\n\tmavlink_msg_jump_to_fw_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_jump_to_fw_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.param );\r\n\tmavlink_msg_jump_to_fw_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_jump_to_fw_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_jump_to_fw_send(MAVLINK_COMM_1 , packet1.resp , packet1.param );\r\n\tmavlink_msg_jump_to_fw_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_opencr_msg(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n\tmavlink_test_ack(system_id, component_id, last_msg);\r\n\tmavlink_test_read_version(system_id, component_id, last_msg);\r\n\tmavlink_test_read_board_name(system_id, component_id, last_msg);\r\n\tmavlink_test_read_tag(system_id, component_id, last_msg);\r\n\tmavlink_test_flash_fw_write_begin(system_id, component_id, last_msg);\r\n\tmavlink_test_flash_fw_write_end(system_id, component_id, last_msg);\r\n\tmavlink_test_flash_fw_write_packet(system_id, component_id, last_msg);\r\n\tmavlink_test_flash_fw_write_block(system_id, component_id, last_msg);\r\n\tmavlink_test_flash_fw_erase(system_id, component_id, last_msg);\r\n\tmavlink_test_flash_fw_verify(system_id, component_id, last_msg);\r\n\tmavlink_test_flash_fw_read_packet(system_id, component_id, last_msg);\r\n\tmavlink_test_flash_fw_read_block(system_id, component_id, last_msg);\r\n\tmavlink_test_jump_to_fw(system_id, component_id, last_msg);\r\n}\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif // __cplusplus\r\n#endif // OPENCR_MSG_TESTSUITE_H\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/msg/mavlink/opencr_msg/version.h",
    "content": "/** @file\r\n *\t@brief MAVLink comm protocol built from opencr_msg.xml\r\n *\t@see http://mavlink.org\r\n */\r\n#ifndef MAVLINK_VERSION_H\r\n#define MAVLINK_VERSION_H\r\n\r\n#define MAVLINK_BUILD_DATE \"Mon May 30 2016\"\r\n#define MAVLINK_WIRE_PROTOCOL_VERSION \"1.0\"\r\n#define MAVLINK_MAX_DIALECT_PAYLOAD_SIZE 134\r\n \r\n#endif // MAVLINK_VERSION_H\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/msg/mavlink/protocol.h",
    "content": "#ifndef  _MAVLINK_PROTOCOL_H_\r\n#define  _MAVLINK_PROTOCOL_H_\r\n\r\n#include \"string.h\"\r\n#include \"mavlink_types.h\"\r\n\r\n/* \r\n   If you want MAVLink on a system that is native big-endian,\r\n   you need to define NATIVE_BIG_ENDIAN\r\n*/\r\n#ifdef NATIVE_BIG_ENDIAN\r\n# define MAVLINK_NEED_BYTE_SWAP (MAVLINK_ENDIAN == MAVLINK_LITTLE_ENDIAN)\r\n#else\r\n# define MAVLINK_NEED_BYTE_SWAP (MAVLINK_ENDIAN != MAVLINK_LITTLE_ENDIAN)\r\n#endif\r\n\r\n#ifndef MAVLINK_STACK_BUFFER\r\n#define MAVLINK_STACK_BUFFER 0\r\n#endif\r\n\r\n#ifndef MAVLINK_AVOID_GCC_STACK_BUG\r\n# define MAVLINK_AVOID_GCC_STACK_BUG defined(__GNUC__)\r\n#endif\r\n\r\n#ifndef MAVLINK_ASSERT\r\n#define MAVLINK_ASSERT(x)\r\n#endif\r\n\r\n#ifndef MAVLINK_START_UART_SEND\r\n#define MAVLINK_START_UART_SEND(chan, length)\r\n#endif\r\n\r\n#ifndef MAVLINK_END_UART_SEND\r\n#define MAVLINK_END_UART_SEND(chan, length)\r\n#endif\r\n\r\n/* option to provide alternative implementation of mavlink_helpers.h */\r\n#ifdef MAVLINK_SEPARATE_HELPERS\r\n\r\n    #define MAVLINK_HELPER\r\n\r\n    /* decls in sync with those in mavlink_helpers.h */\r\n    #ifndef MAVLINK_GET_CHANNEL_STATUS\r\n    MAVLINK_HELPER mavlink_status_t* mavlink_get_channel_status(uint8_t chan);\r\n    #endif\r\n    MAVLINK_HELPER void mavlink_reset_channel_status(uint8_t chan);\r\n    #if MAVLINK_CRC_EXTRA\r\n    MAVLINK_HELPER uint16_t mavlink_finalize_message_chan(mavlink_message_t* msg, uint8_t system_id, uint8_t component_id,\r\n                                                          uint8_t chan, uint8_t min_length, uint8_t length, uint8_t crc_extra);\r\n    MAVLINK_HELPER uint16_t mavlink_finalize_message(mavlink_message_t* msg, uint8_t system_id, uint8_t component_id,\r\n                                                     uint8_t min_length, uint8_t length, uint8_t crc_extra);\r\n    #ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n    MAVLINK_HELPER void _mav_finalize_message_chan_send(mavlink_channel_t chan, uint8_t msgid, const char *packet,\r\n                                                        uint8_t min_length, uint8_t length, uint8_t crc_extra);\r\n    #endif\r\n    #else\r\n    MAVLINK_HELPER uint16_t mavlink_finalize_message_chan(mavlink_message_t* msg, uint8_t system_id, uint8_t component_id,\r\n                                                          uint8_t chan, uint8_t length);\r\n    MAVLINK_HELPER uint16_t mavlink_finalize_message(mavlink_message_t* msg, uint8_t system_id, uint8_t component_id,\r\n                                                     uint8_t length);\r\n    #ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n    MAVLINK_HELPER void _mav_finalize_message_chan_send(mavlink_channel_t chan, uint8_t msgid, const char *packet, uint8_t length);\r\n    #endif\r\n    #endif // MAVLINK_CRC_EXTRA\r\n    MAVLINK_HELPER uint16_t mavlink_msg_to_send_buffer(uint8_t *buffer, const mavlink_message_t *msg);\r\n    MAVLINK_HELPER void mavlink_start_checksum(mavlink_message_t* msg);\r\n    MAVLINK_HELPER void mavlink_update_checksum(mavlink_message_t* msg, uint8_t c);\r\n    MAVLINK_HELPER uint8_t mavlink_frame_char_buffer(mavlink_message_t* rxmsg, \r\n\t\t\t\t\t\t     mavlink_status_t* status,\r\n\t\t\t\t\t\t     uint8_t c, \r\n\t\t\t\t\t\t     mavlink_message_t* r_message, \r\n\t\t\t\t\t\t     mavlink_status_t* r_mavlink_status);\r\n    MAVLINK_HELPER uint8_t mavlink_frame_char(uint8_t chan, uint8_t c, mavlink_message_t* r_message, mavlink_status_t* r_mavlink_status);\r\n    MAVLINK_HELPER uint8_t mavlink_parse_char(uint8_t chan, uint8_t c, mavlink_message_t* r_message, mavlink_status_t* r_mavlink_status);\r\n    MAVLINK_HELPER uint8_t put_bitfield_n_by_index(int32_t b, uint8_t bits, uint8_t packet_index, uint8_t bit_index,\r\n                               uint8_t* r_bit_index, uint8_t* buffer);\r\n    #ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n    MAVLINK_HELPER void _mavlink_send_uart(mavlink_channel_t chan, const char *buf, uint16_t len);\r\n    MAVLINK_HELPER void _mavlink_resend_uart(mavlink_channel_t chan, const mavlink_message_t *msg);\r\n    #endif\r\n\r\n#else\r\n\r\n    #define MAVLINK_HELPER static inline\r\n    #include \"mavlink_helpers.h\"\r\n\r\n#endif // MAVLINK_SEPARATE_HELPERS\r\n\r\n/**\r\n * @brief Get the required buffer size for this message\r\n */\r\nstatic inline uint16_t mavlink_msg_get_send_buffer_length(const mavlink_message_t* msg)\r\n{\r\n\treturn msg->len + MAVLINK_NUM_NON_PAYLOAD_BYTES;\r\n}\r\n\r\n#if MAVLINK_NEED_BYTE_SWAP\r\nstatic inline void byte_swap_2(char *dst, const char *src)\r\n{\r\n\tdst[0] = src[1];\r\n\tdst[1] = src[0];\r\n}\r\nstatic inline void byte_swap_4(char *dst, const char *src)\r\n{\r\n\tdst[0] = src[3];\r\n\tdst[1] = src[2];\r\n\tdst[2] = src[1];\r\n\tdst[3] = src[0];\r\n}\r\nstatic inline void byte_swap_8(char *dst, const char *src)\r\n{\r\n\tdst[0] = src[7];\r\n\tdst[1] = src[6];\r\n\tdst[2] = src[5];\r\n\tdst[3] = src[4];\r\n\tdst[4] = src[3];\r\n\tdst[5] = src[2];\r\n\tdst[6] = src[1];\r\n\tdst[7] = src[0];\r\n}\r\n#elif !MAVLINK_ALIGNED_FIELDS\r\nstatic inline void byte_copy_2(char *dst, const char *src)\r\n{\r\n\tdst[0] = src[0];\r\n\tdst[1] = src[1];\r\n}\r\nstatic inline void byte_copy_4(char *dst, const char *src)\r\n{\r\n\tdst[0] = src[0];\r\n\tdst[1] = src[1];\r\n\tdst[2] = src[2];\r\n\tdst[3] = src[3];\r\n}\r\nstatic inline void byte_copy_8(char *dst, const char *src)\r\n{\r\n\tmemcpy(dst, src, 8);\r\n}\r\n#endif\r\n\r\n#define _mav_put_uint8_t(buf, wire_offset, b) buf[wire_offset] = (uint8_t)b\r\n#define _mav_put_int8_t(buf, wire_offset, b)  buf[wire_offset] = (int8_t)b\r\n#define _mav_put_char(buf, wire_offset, b)    buf[wire_offset] = b\r\n\r\n#if MAVLINK_NEED_BYTE_SWAP\r\n#define _mav_put_uint16_t(buf, wire_offset, b) byte_swap_2(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_int16_t(buf, wire_offset, b)  byte_swap_2(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_uint32_t(buf, wire_offset, b) byte_swap_4(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_int32_t(buf, wire_offset, b)  byte_swap_4(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_uint64_t(buf, wire_offset, b) byte_swap_8(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_int64_t(buf, wire_offset, b)  byte_swap_8(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_float(buf, wire_offset, b)    byte_swap_4(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_double(buf, wire_offset, b)   byte_swap_8(&buf[wire_offset], (const char *)&b)\r\n#elif !MAVLINK_ALIGNED_FIELDS\r\n#define _mav_put_uint16_t(buf, wire_offset, b) byte_copy_2(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_int16_t(buf, wire_offset, b)  byte_copy_2(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_uint32_t(buf, wire_offset, b) byte_copy_4(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_int32_t(buf, wire_offset, b)  byte_copy_4(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_uint64_t(buf, wire_offset, b) byte_copy_8(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_int64_t(buf, wire_offset, b)  byte_copy_8(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_float(buf, wire_offset, b)    byte_copy_4(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_double(buf, wire_offset, b)   byte_copy_8(&buf[wire_offset], (const char *)&b)\r\n#else\r\n#define _mav_put_uint16_t(buf, wire_offset, b) *(uint16_t *)&buf[wire_offset] = b\r\n#define _mav_put_int16_t(buf, wire_offset, b)  *(int16_t *)&buf[wire_offset] = b\r\n#define _mav_put_uint32_t(buf, wire_offset, b) *(uint32_t *)&buf[wire_offset] = b\r\n#define _mav_put_int32_t(buf, wire_offset, b)  *(int32_t *)&buf[wire_offset] = b\r\n#define _mav_put_uint64_t(buf, wire_offset, b) *(uint64_t *)&buf[wire_offset] = b\r\n#define _mav_put_int64_t(buf, wire_offset, b)  *(int64_t *)&buf[wire_offset] = b\r\n#define _mav_put_float(buf, wire_offset, b)    *(float *)&buf[wire_offset] = b\r\n#define _mav_put_double(buf, wire_offset, b)   *(double *)&buf[wire_offset] = b\r\n#endif\r\n\r\n/*\r\n  like memcpy(), but if src is NULL, do a memset to zero\r\n*/\r\nstatic inline void mav_array_memcpy(void *dest, const void *src, size_t n)\r\n{\r\n\tif (src == NULL) {\r\n\t\tmemset(dest, 0, n);\r\n\t} else {\r\n\t\tmemcpy(dest, src, n);\r\n\t}\r\n}\r\n\r\n/*\r\n * Place a char array into a buffer\r\n */\r\nstatic inline void _mav_put_char_array(char *buf, uint8_t wire_offset, const char *b, uint8_t array_length)\r\n{\r\n\tmav_array_memcpy(&buf[wire_offset], b, array_length);\r\n\r\n}\r\n\r\n/*\r\n * Place a uint8_t array into a buffer\r\n */\r\nstatic inline void _mav_put_uint8_t_array(char *buf, uint8_t wire_offset, const uint8_t *b, uint8_t array_length)\r\n{\r\n\tmav_array_memcpy(&buf[wire_offset], b, array_length);\r\n\r\n}\r\n\r\n/*\r\n * Place a int8_t array into a buffer\r\n */\r\nstatic inline void _mav_put_int8_t_array(char *buf, uint8_t wire_offset, const int8_t *b, uint8_t array_length)\r\n{\r\n\tmav_array_memcpy(&buf[wire_offset], b, array_length);\r\n\r\n}\r\n\r\n#if MAVLINK_NEED_BYTE_SWAP\r\n#define _MAV_PUT_ARRAY(TYPE, V) \\\r\nstatic inline void _mav_put_ ## TYPE ##_array(char *buf, uint8_t wire_offset, const TYPE *b, uint8_t array_length) \\\r\n{ \\\r\n\tif (b == NULL) { \\\r\n\t\tmemset(&buf[wire_offset], 0, array_length*sizeof(TYPE)); \\\r\n\t} else { \\\r\n\t\tuint16_t i; \\\r\n\t\tfor (i=0; i<array_length; i++) { \\\r\n\t\t\t_mav_put_## TYPE (buf, wire_offset+(i*sizeof(TYPE)), b[i]); \\\r\n\t\t} \\\r\n\t} \\\r\n}\r\n#else\r\n#define _MAV_PUT_ARRAY(TYPE, V)\t\t\t\t\t\\\r\nstatic inline void _mav_put_ ## TYPE ##_array(char *buf, uint8_t wire_offset, const TYPE *b, uint8_t array_length) \\\r\n{ \\\r\n\tmav_array_memcpy(&buf[wire_offset], b, array_length*sizeof(TYPE)); \\\r\n}\r\n#endif\r\n\r\n_MAV_PUT_ARRAY(uint16_t, u16)\r\n_MAV_PUT_ARRAY(uint32_t, u32)\r\n_MAV_PUT_ARRAY(uint64_t, u64)\r\n_MAV_PUT_ARRAY(int16_t,  i16)\r\n_MAV_PUT_ARRAY(int32_t,  i32)\r\n_MAV_PUT_ARRAY(int64_t,  i64)\r\n_MAV_PUT_ARRAY(float,    f)\r\n_MAV_PUT_ARRAY(double,   d)\r\n\r\n#define _MAV_RETURN_char(msg, wire_offset)             (const char)_MAV_PAYLOAD(msg)[wire_offset]\r\n#define _MAV_RETURN_int8_t(msg, wire_offset)   (const int8_t)_MAV_PAYLOAD(msg)[wire_offset]\r\n#define _MAV_RETURN_uint8_t(msg, wire_offset) (const uint8_t)_MAV_PAYLOAD(msg)[wire_offset]\r\n\r\n#if MAVLINK_NEED_BYTE_SWAP\r\n#define _MAV_MSG_RETURN_TYPE(TYPE, SIZE) \\\r\nstatic inline TYPE _MAV_RETURN_## TYPE(const mavlink_message_t *msg, uint8_t ofs) \\\r\n{ TYPE r; byte_swap_## SIZE((char*)&r, &_MAV_PAYLOAD(msg)[ofs]); return r; }\r\n\r\n_MAV_MSG_RETURN_TYPE(uint16_t, 2)\r\n_MAV_MSG_RETURN_TYPE(int16_t,  2)\r\n_MAV_MSG_RETURN_TYPE(uint32_t, 4)\r\n_MAV_MSG_RETURN_TYPE(int32_t,  4)\r\n_MAV_MSG_RETURN_TYPE(uint64_t, 8)\r\n_MAV_MSG_RETURN_TYPE(int64_t,  8)\r\n_MAV_MSG_RETURN_TYPE(float,    4)\r\n_MAV_MSG_RETURN_TYPE(double,   8)\r\n\r\n#elif !MAVLINK_ALIGNED_FIELDS\r\n#define _MAV_MSG_RETURN_TYPE(TYPE, SIZE) \\\r\nstatic inline TYPE _MAV_RETURN_## TYPE(const mavlink_message_t *msg, uint8_t ofs) \\\r\n{ TYPE r; byte_copy_## SIZE((char*)&r, &_MAV_PAYLOAD(msg)[ofs]); return r; }\r\n\r\n_MAV_MSG_RETURN_TYPE(uint16_t, 2)\r\n_MAV_MSG_RETURN_TYPE(int16_t,  2)\r\n_MAV_MSG_RETURN_TYPE(uint32_t, 4)\r\n_MAV_MSG_RETURN_TYPE(int32_t,  4)\r\n_MAV_MSG_RETURN_TYPE(uint64_t, 8)\r\n_MAV_MSG_RETURN_TYPE(int64_t,  8)\r\n_MAV_MSG_RETURN_TYPE(float,    4)\r\n_MAV_MSG_RETURN_TYPE(double,   8)\r\n#else // nicely aligned, no swap\r\n#define _MAV_MSG_RETURN_TYPE(TYPE) \\\r\nstatic inline TYPE _MAV_RETURN_## TYPE(const mavlink_message_t *msg, uint8_t ofs) \\\r\n{ return *(const TYPE *)(&_MAV_PAYLOAD(msg)[ofs]);}\r\n\r\n_MAV_MSG_RETURN_TYPE(uint16_t)\r\n_MAV_MSG_RETURN_TYPE(int16_t)\r\n_MAV_MSG_RETURN_TYPE(uint32_t)\r\n_MAV_MSG_RETURN_TYPE(int32_t)\r\n_MAV_MSG_RETURN_TYPE(uint64_t)\r\n_MAV_MSG_RETURN_TYPE(int64_t)\r\n_MAV_MSG_RETURN_TYPE(float)\r\n_MAV_MSG_RETURN_TYPE(double)\r\n#endif // MAVLINK_NEED_BYTE_SWAP\r\n\r\nstatic inline uint16_t _MAV_RETURN_char_array(const mavlink_message_t *msg, char *value, \r\n\t\t\t\t\t\t     uint8_t array_length, uint8_t wire_offset)\r\n{\r\n\tmemcpy(value, &_MAV_PAYLOAD(msg)[wire_offset], array_length);\r\n\treturn array_length;\r\n}\r\n\r\nstatic inline uint16_t _MAV_RETURN_uint8_t_array(const mavlink_message_t *msg, uint8_t *value, \r\n\t\t\t\t\t\t\tuint8_t array_length, uint8_t wire_offset)\r\n{\r\n\tmemcpy(value, &_MAV_PAYLOAD(msg)[wire_offset], array_length);\r\n\treturn array_length;\r\n}\r\n\r\nstatic inline uint16_t _MAV_RETURN_int8_t_array(const mavlink_message_t *msg, int8_t *value, \r\n\t\t\t\t\t\t       uint8_t array_length, uint8_t wire_offset)\r\n{\r\n\tmemcpy(value, &_MAV_PAYLOAD(msg)[wire_offset], array_length);\r\n\treturn array_length;\r\n}\r\n\r\n#if MAVLINK_NEED_BYTE_SWAP\r\n#define _MAV_RETURN_ARRAY(TYPE, V) \\\r\nstatic inline uint16_t _MAV_RETURN_## TYPE ##_array(const mavlink_message_t *msg, TYPE *value, \\\r\n\t\t\t\t\t\t\t uint8_t array_length, uint8_t wire_offset) \\\r\n{ \\\r\n\tuint16_t i; \\\r\n\tfor (i=0; i<array_length; i++) { \\\r\n\t\tvalue[i] = _MAV_RETURN_## TYPE (msg, wire_offset+(i*sizeof(value[0]))); \\\r\n\t} \\\r\n\treturn array_length*sizeof(value[0]); \\\r\n}\r\n#else\r\n#define _MAV_RETURN_ARRAY(TYPE, V)\t\t\t\t\t\\\r\nstatic inline uint16_t _MAV_RETURN_## TYPE ##_array(const mavlink_message_t *msg, TYPE *value, \\\r\n\t\t\t\t\t\t\t uint8_t array_length, uint8_t wire_offset) \\\r\n{ \\\r\n\tmemcpy(value, &_MAV_PAYLOAD(msg)[wire_offset], array_length*sizeof(TYPE)); \\\r\n\treturn array_length*sizeof(TYPE); \\\r\n}\r\n#endif\r\n\r\n_MAV_RETURN_ARRAY(uint16_t, u16)\r\n_MAV_RETURN_ARRAY(uint32_t, u32)\r\n_MAV_RETURN_ARRAY(uint64_t, u64)\r\n_MAV_RETURN_ARRAY(int16_t,  i16)\r\n_MAV_RETURN_ARRAY(int32_t,  i32)\r\n_MAV_RETURN_ARRAY(int64_t,  i64)\r\n_MAV_RETURN_ARRAY(float,    f)\r\n_MAV_RETURN_ARRAY(double,   d)\r\n\r\n#endif // _MAVLINK_PROTOCOL_H_\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/common/msg/xml/opencr_msg",
    "content": "<?xml version=\"1.0\"?>\r\n<mavlink>\r\n        <!--<include>common.xml</include>-->\r\n        <!-- NOTE: If the included file already contains a version tag, remove the version tag here, else uncomment to enable. -->\r\n\t<!--<version>3</version>-->\r\n\t<enums>\r\n\t</enums>\r\n\t\r\n\t<messages>\r\n\t\t<message id=\"150\" name=\"ACK\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"    name=\"msg_id\"></field>\r\n\t\t\t<field type=\"uint16_t\"   name=\"err_code\"></field>\r\n\t\t\t<field type=\"uint8_t\"    name=\"length\"></field>\r\n\t\t\t<field type=\"uint8_t[16]\" name=\"data\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\t\r\n\t<messages>\r\n\t\t<message id=\"151\" name=\"READ_VERSION\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"    name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint8_t[8]\" name=\"param\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\r\n\t<messages>\r\n\t\t<message id=\"152\" name=\"READ_BOARD_NAME\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"    name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint8_t[8]\" name=\"param\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\r\n\t<messages>\r\n\t\t<message id=\"153\" name=\"READ_TAG\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"    name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint8_t\"    name=\"type\"></field>\r\n\t\t\t<field type=\"uint8_t[8]\" name=\"param\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\r\n\t<messages>\r\n\t\t<message id=\"154\" name=\"FLASH_FW_WRITE_BEGIN\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"    name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint8_t[8]\" name=\"param\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\t\r\n\t<messages>\r\n\t\t<message id=\"155\" name=\"FLASH_FW_WRITE_END\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"    name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint8_t[8]\" name=\"param\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\r\n\t<messages>\r\n\t\t<message id=\"156\" name=\"FLASH_FW_WRITE_PACKET\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"  name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint16_t\" name=\"addr\"></field>\r\n\t\t\t<field type=\"uint8_t\"  name=\"length\"></field>\r\n\t\t\t<field type=\"uint8_t[128]\" name=\"data\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\r\n\t<messages>\r\n\t\t<message id=\"157\" name=\"FLASH_FW_WRITE_BLOCK\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"  name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint32_t\" name=\"addr\"></field>\r\n\t\t\t<field type=\"uint16_t\" name=\"length\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\t\r\n\t<messages>\r\n\t\t<message id=\"158\" name=\"FLASH_FW_ERASE\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"    name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint32_t\"   name=\"length\"></field>\r\n\t\t\t<field type=\"uint8_t[8]\" name=\"param\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\t\r\n\t<messages>\r\n\t\t<message id=\"159\" name=\"FLASH_FW_VERIFY\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"    name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint32_t\"   name=\"length\"></field>\r\n\t\t\t<field type=\"uint32_t\"   name=\"crc\"></field>\r\n\t\t\t<field type=\"uint8_t[8]\" name=\"param\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\r\n\t<messages>\r\n\t\t<message id=\"160\" name=\"FLASH_FW_READ_PACKET\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"  name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint32_t\" name=\"addr\"></field>\r\n\t\t\t<field type=\"uint8_t\"  name=\"length\"></field>\r\n\t\t\t<field type=\"uint8_t[128]\" name=\"data\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\r\n\t<messages>\r\n\t\t<message id=\"161\" name=\"FLASH_FW_READ_BLOCK\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"  name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint32_t\" name=\"addr\"></field>\r\n\t\t\t<field type=\"uint16_t\" name=\"length\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\t\r\n\t<messages>\r\n\t\t<message id=\"162\" name=\"JUMP_TO_FW\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"    name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint8_t[8]\" name=\"param\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\t\t\r\n</mavlink>"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/main.c",
    "content": "/*\r\n * OpenCR BootLoader Firmware.\r\n *\r\n * by Baram\r\n * by PBHP\r\n * by http://oroca.org\r\n */\r\n\r\n#include \"main.h\"\r\n\r\n\r\n\r\nvoid main_init();\r\nvoid msg_process_vcp(void);\r\n\r\n\r\n\r\n\r\nint main(void)\r\n{\r\n  uint32_t tTime;\r\n\r\n\r\n  main_init();\r\n\r\n  tTime = millis();\r\n  while(1)\r\n  {\r\n    if( millis()-tTime > 100 )\r\n    {\r\n      tTime = millis();\r\n      led_toggle(0);\r\n    }\r\n\r\n\r\n#if 0\r\n    uint8_t ch;\r\n    static uint32_t cnt = 0;\r\n\r\n    vcp_printf(\"cnd : %d \\r\\n\", cnt++);\r\n\r\n\r\n    if( vcp_is_available() )\r\n    {\r\n      ch = vcp_getch();\r\n      vcp_printf(\"pressed : 0x%02X \\r\\n\", ch);\r\n      //vcp_printf(\"float test %f\\r\\n\",fvalue);\r\n    }\r\n#else\r\n    msg_process_vcp();\r\n#endif\r\n  }\r\n}\r\n\r\n\r\nvoid main_init()\r\n{\r\n\r\n\r\n  bsp_init();\r\n  hal_init();\r\n\r\n  if( wdg_get_reset() == FALSE )\r\n  {\r\n    if( button_read(0) == FALSE )\r\n    {\r\n      delay_ms(10);\r\n      if( button_read(0) == FALSE )\r\n      {\r\n        led_on(0);\r\n        jump_to_fw();\r\n      }\r\n    }\r\n  }\r\n}\r\n\r\n\r\nvoid msg_process_vcp(void)\r\n{\r\n  BOOL ret;\r\n  uint8_t ch;\r\n  msg_t\tmsg;\r\n\r\n\r\n  while(vcp_is_available())\r\n  {\r\n    ch = vcp_getch();\r\n    ret = msg_recv( 0, ch, &msg );\r\n\r\n    if( ret == TRUE )\r\n    {\r\n      switch( msg.p_msg->msgid )\r\n      {\r\n\tcase MAVLINK_MSG_ID_READ_VERSION:\r\n\t  cmd_read_version(&msg);\r\n\t  break;\r\n\r\n\tcase MAVLINK_MSG_ID_READ_BOARD_NAME:\r\n\t  cmd_read_board_name(&msg);\r\n\t  break;\r\n\r\n\tcase MAVLINK_MSG_ID_READ_TAG:\r\n\t  cmd_read_tag(&msg);\r\n\t  break;\r\n\r\n\tcase MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET:\r\n\t  cmd_flash_fw_write_packet(&msg);\r\n\t  break;\r\n\r\n\tcase MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN:\r\n\t  cmd_flash_fw_write_begin(&msg);\r\n\t  break;\r\n\r\n\tcase MAVLINK_MSG_ID_FLASH_FW_WRITE_END:\r\n\t  cmd_flash_fw_write_end(&msg);\r\n\t  break;\r\n\r\n\tcase MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK:\r\n\t  cmd_flash_fw_write_block(&msg);\r\n\t  break;\r\n\r\n\tcase MAVLINK_MSG_ID_FLASH_FW_ERASE:\r\n\t  cmd_flash_fw_erase(&msg);\r\n\t  break;\r\n\r\n\tcase MAVLINK_MSG_ID_FLASH_FW_VERIFY:\r\n\t  cmd_flash_fw_verify(&msg);\r\n\t  break;\r\n\r\n\tcase MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK:\r\n\t  cmd_flash_fw_read_block(&msg);\r\n\t  break;\r\n\r\n\tcase MAVLINK_MSG_ID_JUMP_TO_FW:\r\n\t  cmd_jump_to_fw(&msg);\r\n\t  break;\r\n\r\n\tdefault:\r\n\t  cmd_send_error(&msg, ERR_INVALID_CMD);\r\n\t  break;\r\n      }\r\n    }\r\n  }\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/main.h",
    "content": "/*\r\n *  main.h\r\n *\r\n *  Created on: 2016. 5. 14.\r\n *      Author: Baram, PBHP\r\n */\r\n\r\n#ifndef __MAIN_H\r\n#define __MAIN_H\r\n\r\n\r\n#include \"stdio.h\"\r\n#include \"hal.h\"\r\n#include \"cmd.h\"\r\n\r\n\r\n\r\n#endif \r\n\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/opencr_flash.cfg",
    "content": "# This is an OpenCR board with a single STM32F756NGH6 chip.\r\n\r\n# This is for using the onboard STLINK/V2\r\nsource [find interface/stlink-v2.cfg]\r\n\r\ntransport select hla_swd\r\n\r\n# increase working area to 256KB\r\nset WORKAREASIZE 0x40000\r\n\r\nsource [find target/stm32f7x.cfg]\r\n\r\nreset_config none \r\n\r\nprogram ./bin/opencr_boot.elf verify reset exit\r\n\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/opencr_openocd.cfg",
    "content": "# This is an OpenCR board with a single STM32F756NGH6 chip.\r\n\r\ninterface hla\r\nhla_layout stlink\r\nhla_device_desc \"ST-LINK/V2\"\r\nhla_vid_pid 0x0483 0x3748\r\n\r\ntransport select hla_swd\r\n\r\n# increase working area to 256KB\r\nset WORKAREASIZE 0x40000\r\n\r\nadapter_nsrst_delay 100\r\n\r\nsource [find target/stm32f7x.cfg]\r\n\r\nreset_config none"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/src/cmd.c",
    "content": "/*\r\n *  cmd.c\r\n *\r\n *  message process\r\n *\r\n *  Created on: 2016. 5. 14.\r\n *      Author: Baram, PBHP\r\n */\r\n\r\n#include \"cmd.h\"\r\n#include <math.h>\r\n#include <string.h>\r\n#include <stdarg.h>\r\n#include <stdio.h>\r\n\r\n#include \"crc.h\"\r\n\r\n\r\n#define FLASH_FW_SIZE             (768*1024)\t// 768KB\r\n#define FLASH_FW_ADDR_START       0x08040000\r\n#define FLASH_FW_ADDR_END         (FLASH_FW_ADDR_START + FLASH_FW_SIZE)\r\n\r\n#define FLASH_CONFIG_SIZE         (32*1024)\t// 32KB\r\n#define FLASH_CONFIG_ADDR_START   0x08010000\r\n#define FLASH_CONFIG_ADDR_END     (FLASH_CONFIG_ADDR_START + FLASH_CONFIG_SIZE)\r\n\r\n#define FLASH_BLOCK_PACKET_LENGTH\t128\r\n#define FLASH_BLOCK_MAX_LENGTH\t\t(16*1024)\r\n\r\n\r\n\r\nconst uint8_t  *board_name   = \"OpenCR R1.0\";\r\nuint32_t boot_version        = 0x17020800;\r\nuint32_t boot_revision       = 0x00000000;\r\n\r\n\r\n\r\ntypedef struct\r\n{\r\n  uint32_t length;\r\n  uint32_t length_received;\r\n  uint32_t length_total;\r\n\r\n  uint16_t count;\r\n  uint16_t count_total;\r\n\r\n  uint8_t  data[FLASH_BLOCK_MAX_LENGTH];\r\n} flash_block_t;\r\n\r\n\r\n\r\nflash_block_t flash_block;\r\n\r\n\r\n\r\nvoid jump_to_fw(void);\r\n\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : cmd_init\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nvoid cmd_init(void)\r\n{\r\n\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : resp_ack\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nvoid resp_ack( uint8_t ch, mavlink_ack_t *p_ack )\r\n{\r\n  mavlink_message_t mav_msg;\r\n\r\n\r\n  mavlink_msg_ack_pack_chan(0, 0, ch, &mav_msg, p_ack->msg_id, p_ack->err_code, p_ack->length, p_ack->data);\r\n\r\n  msg_send( ch, &mav_msg);\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : cmd_read_version\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nvoid cmd_read_version( msg_t *p_msg )\r\n{\r\n  err_code_t err_code = OK;\r\n  mavlink_ack_t     mav_ack;\r\n  mavlink_read_version_t mav_data;\r\n\r\n\r\n  mavlink_msg_read_version_decode(p_msg->p_msg, &mav_data);\r\n\r\n\r\n\r\n  if( mav_data.resp == 1 )\r\n  {\r\n    mav_ack.msg_id   = p_msg->p_msg->msgid;\r\n    mav_ack.err_code = err_code;\r\n    mav_ack.data[0] = boot_version;\r\n    mav_ack.data[1] = boot_version>>8;\r\n    mav_ack.data[2] = boot_version>>16;\r\n    mav_ack.data[3] = boot_version>>24;\r\n    mav_ack.data[4] = boot_revision;\r\n    mav_ack.data[5] = boot_revision>>8;\r\n    mav_ack.data[6] = boot_revision>>16;\r\n    mav_ack.data[7] = boot_revision>>24;\r\n    mav_ack.length  = 8;\r\n    resp_ack(p_msg->ch, &mav_ack);\r\n  }\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : cmd_read_board_name\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nvoid cmd_read_board_name( msg_t *p_msg )\r\n{\r\n  err_code_t err_code = OK;\r\n  mavlink_ack_t     mav_ack;\r\n  mavlink_read_board_name_t mav_data;\r\n  uint8_t i;\r\n\r\n  mavlink_msg_read_board_name_decode(p_msg->p_msg, &mav_data);\r\n\r\n\r\n\r\n  if( mav_data.resp == 1 )\r\n  {\r\n    mav_ack.msg_id   = p_msg->p_msg->msgid;\r\n    mav_ack.err_code = err_code;\r\n\r\n\r\n    for( i=0; i<strlen(board_name); i++ )\r\n    {\r\n      mav_ack.data[i] = board_name[i];\r\n    }\r\n    mav_ack.data[i] = 0;\r\n    mav_ack.length  = i;\r\n    resp_ack(p_msg->ch, &mav_ack);\r\n  }\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : cmd_read_tag\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nvoid cmd_read_tag( msg_t *p_msg )\r\n{\r\n  err_code_t err_code = OK;\r\n  mavlink_ack_t     mav_ack;\r\n  mavlink_read_tag_t mav_data;\r\n\r\n  mavlink_msg_read_tag_decode(p_msg->p_msg, &mav_data);\r\n\r\n\r\n\r\n  if( mav_data.resp == 1 )\r\n  {\r\n    mav_ack.msg_id   = p_msg->p_msg->msgid;\r\n    mav_ack.err_code = err_code;\r\n\r\n    mav_ack.length  = 0;\r\n    resp_ack(p_msg->ch, &mav_ack);\r\n  }\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : cmd_flash_fw_write_packet\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nvoid cmd_flash_fw_write_packet( msg_t *p_msg )\r\n{\r\n  err_code_t err_code = OK;\r\n  mavlink_ack_t     mav_ack;\r\n  mavlink_flash_fw_write_packet_t mav_data;\r\n\r\n  mavlink_msg_flash_fw_write_packet_decode(p_msg->p_msg, &mav_data);\r\n\r\n  if((flash_block.length_received + mav_data.length) <= FLASH_BLOCK_MAX_LENGTH)\r\n  {\r\n    memcpy(&flash_block.data[flash_block.length_received], &mav_data.data[0], mav_data.length);\r\n  }\r\n\r\n  flash_block.count += 1;\r\n  flash_block.length_received  += mav_data.length;\r\n\r\n  flash_block.count_total += 1;\r\n  flash_block.length_total  += mav_data.length;\r\n\r\n\r\n\r\n  if( mav_data.resp == 1 )\r\n  {\r\n    mav_ack.msg_id   = p_msg->p_msg->msgid;\r\n    mav_ack.err_code = err_code;\r\n    resp_ack(p_msg->ch, &mav_ack);\r\n  }\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : cmd_flash_fw_write_begin\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nvoid cmd_flash_fw_write_begin( msg_t *p_msg )\r\n{\r\n  err_code_t err_code = OK;\r\n  mavlink_ack_t     mav_ack;\r\n  mavlink_flash_fw_write_begin_t mav_data;\r\n\r\n\r\n  mavlink_msg_flash_fw_write_begin_decode(p_msg->p_msg, &mav_data);\r\n\r\n  flash_block.count = 0;\r\n  flash_block.count_total = 0;\r\n\r\n  flash_block.length = 0;\r\n  flash_block.length_total = 0;\r\n  flash_block.length_received = 0;\r\n\r\n  if( mav_data.resp == 1 )\r\n  {\r\n    mav_ack.msg_id   = p_msg->p_msg->msgid;\r\n    mav_ack.err_code = err_code;\r\n    resp_ack(p_msg->ch, &mav_ack);\r\n  }\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : cmd_flash_fw_write_end\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nvoid cmd_flash_fw_write_end( msg_t *p_msg )\r\n{\r\n  err_code_t err_code = OK;\r\n  mavlink_ack_t     mav_ack;\r\n  mavlink_flash_fw_write_end_t mav_data;\r\n\r\n\r\n  mavlink_msg_flash_fw_write_end_decode(p_msg->p_msg, &mav_data);\r\n\r\n\r\n\r\n  if( mav_data.resp == 1 )\r\n  {\r\n    mav_ack.msg_id   = p_msg->p_msg->msgid;\r\n    mav_ack.err_code = err_code;\r\n    mav_ack.data[0] = flash_block.count_total;\r\n    mav_ack.data[1] = flash_block.count_total>>8;\r\n    mav_ack.data[2] = flash_block.length_total;\r\n    mav_ack.data[3] = flash_block.length_total>>8;\r\n    mav_ack.data[4] = flash_block.length_total>>16;\r\n    mav_ack.data[5] = flash_block.length_total>>24;\r\n    mav_ack.length  = 6;\r\n\r\n    resp_ack(p_msg->ch, &mav_ack);\r\n  }\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : cmd_flash_fw_write_block\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nvoid cmd_flash_fw_write_block( msg_t *p_msg )\r\n{\r\n  err_code_t err_code = OK;\r\n  mavlink_ack_t     mav_ack;\r\n  mavlink_flash_fw_write_block_t mav_data;\r\n\r\n\r\n  mavlink_msg_flash_fw_write_block_decode(p_msg->p_msg, &mav_data);\r\n\r\n\r\n  // TODO ------------------------------------------------\r\n  // 플래시에 블럭 데이터를 Write한다.\r\n  // mav_data.addr : 플래시 메모리 시작 주소\r\n  // mav_data.length : 저장할 데이터 사이즈\r\n  // flash_block.data[] : 저장할 데이터 버퍼\r\n  //\r\n\r\n  err_code = flash_write( FLASH_FW_ADDR_START + mav_data.addr,flash_block.data, mav_data.length);\r\n\r\n  //------------------------------------------------------\r\n\r\n  flash_block.count = 0;\r\n  flash_block.length_received = 0;\r\n\r\n  if( mav_data.resp == 1 )\r\n  {\r\n    mav_ack.msg_id   = p_msg->p_msg->msgid;\r\n    mav_ack.err_code = err_code;\r\n    resp_ack(p_msg->ch, &mav_ack);\r\n  }\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : cmd_flash_fw_erase\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nvoid cmd_flash_fw_erase( msg_t *p_msg )\r\n{\r\n  err_code_t err_code = OK;\r\n  mavlink_ack_t     mav_ack;\r\n  mavlink_flash_fw_erase_t mav_data;\r\n\r\n\r\n  mavlink_msg_flash_fw_erase_decode(p_msg->p_msg, &mav_data);\r\n\r\n\r\n  // TODO ------------------------------------------------\r\n  // 플래시에 펌웨어 영역 768KB의 영역을 지운다.\r\n\r\n  if( mav_data.length > FLASH_FW_SIZE )\r\n  {\r\n    err_code = ERR_FLASH_SIZE;\r\n  }\r\n  else\r\n  {\r\n    err_code = flash_erase_fw_block( mav_data.length );\r\n  }\r\n\r\n\r\n  //------------------------------------------------------\r\n\r\n  flash_block.count = 0;\r\n  flash_block.length_received = 0;\r\n\r\n  if( mav_data.resp == 1 )\r\n  {\r\n    mav_ack.msg_id   = p_msg->p_msg->msgid;\r\n    mav_ack.err_code = err_code;\r\n    resp_ack(p_msg->ch, &mav_ack);\r\n  }\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : cmd_flash_fw_verify\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nvoid cmd_flash_fw_verify( msg_t *p_msg )\r\n{\r\n  err_code_t err_code = OK;\r\n  mavlink_ack_t     mav_ack;\r\n  mavlink_flash_fw_verify_t mav_data;\r\n  uint32_t crc = 0;\r\n  uint32_t i;\r\n  uint8_t *p_fw = (uint8_t *)FLASH_FW_ADDR_START;\r\n\r\n\r\n  mavlink_msg_flash_fw_verify_decode(p_msg->p_msg, &mav_data);\r\n\r\n  crc = 0;\r\n  for( i=0; i<mav_data.length; i++ )\r\n  {\r\n    crc = crc_calc( crc, p_fw[i] );\r\n  }\r\n\r\n\r\n  if( mav_data.resp == 1 )\r\n  {\r\n    mav_ack.msg_id   = p_msg->p_msg->msgid;\r\n\r\n    if( crc != mav_data.crc )\r\n    {\r\n      err_code = ERR_FLASH_CRC;\r\n    }\r\n\r\n    mav_ack.data[0] = crc >> 0;\r\n    mav_ack.data[1] = crc >> 8;\r\n    mav_ack.data[2] = crc >> 16;\r\n    mav_ack.data[3] = crc >> 24;\r\n    mav_ack.length = 4;\r\n\r\n    mav_ack.err_code = err_code;\r\n    resp_ack(p_msg->ch, &mav_ack);\r\n  }\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : cmd_flash_fw_read_packet\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nvoid cmd_flash_fw_read_packet( uint8_t ch, mavlink_flash_fw_read_packet_t *p_msg )\r\n{\r\n  mavlink_message_t mav_msg;\r\n\r\n\r\n  mavlink_msg_flash_fw_read_packet_pack_chan(0, 0, ch, &mav_msg, p_msg->resp, p_msg->addr, p_msg->length, p_msg->data);\r\n  msg_send( ch, &mav_msg);\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : cmd_flash_fw_read_block\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\n#if 0\r\nvoid cmd_flash_fw_read_block( msg_t *p_msg )\r\n{\r\n  err_code_t err_code = OK;\r\n  mavlink_flash_fw_read_t       mav_resp;\r\n  mavlink_flash_fw_read_block_t mav_data;\r\n  uint16_t block_cnt = 0;\r\n  uint16_t i;\r\n  uint8_t *p_fw = (uint8_t *)FLASH_FW_ADDR_START;\r\n\r\n\r\n  mavlink_msg_flash_fw_read_block_decode(p_msg->p_msg, &mav_data);\r\n\r\n\r\n  flash_block.length_received = 0;\r\n  flash_block.length_total    = mav_data.length;\r\n\r\n  if( mav_data.resp == 1 )\r\n  {\r\n    if( mav_data.length > FLASH_BLOCK_MAX_LENGTH )\r\n    {\r\n      mav_data.length = FLASH_BLOCK_MAX_LENGTH;\r\n    }\r\n\r\n    memcpy(flash_block.data, &p_fw[mav_data.addr], mav_data.length );\r\n\r\n\r\n    block_cnt = mav_data.length/FLASH_BLOCK_PACKET_LENGTH;\r\n\r\n    if( (block_cnt%FLASH_BLOCK_PACKET_LENGTH) > 0 )\r\n    {\r\n      block_cnt += 1;\r\n    }\r\n\r\n    for(i=0; i<block_cnt; i++)\r\n    {\r\n      flash_block.length = flash_block.length_total - flash_block.length_received;\r\n      if( flash_block.length > FLASH_BLOCK_PACKET_LENGTH )\r\n      {\r\n\tflash_block.length = FLASH_BLOCK_PACKET_LENGTH;\r\n      }\r\n\r\n      mav_resp.addr   = flash_block.length_received;\r\n      mav_resp.length = flash_block.length;\r\n\r\n      memcpy(&mav_resp.data[0], &flash_block.data[0], flash_block.length);\r\n\r\n      cmd_flash_fw_read(p_msg->ch, &mav_resp);\r\n    }\r\n  }\r\n}\r\n#else\r\nvoid cmd_flash_fw_read_block( msg_t *p_msg )\r\n{\r\n  err_code_t err_code = OK;\r\n  mavlink_flash_fw_read_packet_t  mav_resp;\r\n  mavlink_flash_fw_read_block_t   mav_data;\r\n  uint16_t block_cnt = 0;\r\n  uint16_t i;\r\n  uint8_t *p_fw = (uint8_t *)FLASH_FW_ADDR_START;\r\n\r\n\r\n  mavlink_msg_flash_fw_read_block_decode(p_msg->p_msg, &mav_data);\r\n\r\n\r\n  flash_block.length_received = 0;\r\n  flash_block.length_total    = mav_data.length;\r\n\r\n  if( mav_data.resp == 1 )\r\n  {\r\n    mav_resp.addr   = mav_data.addr;\r\n    mav_resp.length = mav_data.length;\r\n\r\n    memcpy(mav_resp.data, &p_fw[mav_data.addr], mav_data.length );\r\n\r\n    cmd_flash_fw_read_packet(p_msg->ch, &mav_resp);\r\n  }\r\n}\r\n#endif\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : cmd_jump_to_fw\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nvoid cmd_jump_to_fw( msg_t *p_msg )\r\n{\r\n  err_code_t err_code = OK;\r\n  mavlink_ack_t     mav_ack;\r\n  mavlink_jump_to_fw_t mav_data;\r\n\r\n\r\n  mavlink_msg_jump_to_fw_decode(p_msg->p_msg, &mav_data);\r\n\r\n\r\n\r\n  jump_to_fw();\r\n\r\n\r\n  if( mav_data.resp == 1 )\r\n  {\r\n    mav_ack.msg_id   = p_msg->p_msg->msgid;\r\n    mav_ack.err_code = err_code;\r\n    resp_ack(p_msg->ch, &mav_ack);\r\n  }\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : cmd_send_error\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nvoid cmd_send_error( msg_t *p_msg, err_code_t err_code )\r\n{\r\n\r\n  mavlink_ack_t     mav_ack;\r\n  mavlink_read_version_t mav_data;\r\n\r\n\r\n  mavlink_msg_read_version_decode(p_msg->p_msg, &mav_data);\r\n\r\n  mav_ack.msg_id   = p_msg->p_msg->msgid;\r\n  mav_ack.err_code = err_code;\r\n  resp_ack(p_msg->ch, &mav_ack);\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : check_fw\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nBOOL check_fw(void)\r\n{\r\n  BOOL ret = TRUE;\r\n  uint32_t *p_addr = (uint32_t *)FLASH_FW_ADDR_START;\r\n\r\n\r\n  if( p_addr[0] == 0xFFFFFFFF ) ret = FALSE;\r\n\r\n\r\n  return ret;\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : jump_to_fw\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nvoid jump_to_fw(void)\r\n{\r\n\r\n  if( check_fw() == FALSE ) return;\r\n\r\n  bsp_deinit();\r\n\r\n  SCB->VTOR = FLASH_FW_ADDR_START;\r\n\r\n  __asm volatile(\"ldr r0, =0x08040000 \\n\"\r\n                 \"ldr sp, [r0]        \\n\"\r\n                 \"ldr pc, [r0, #4]    \\n\");\r\n}\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/src/cmd.h",
    "content": "/*\r\n *  cmd.h\r\n *\r\n *  command process\r\n *\r\n *  Created on: 2016. 5. 14.\r\n *      Author: Baram, PBHP\r\n */\r\n\r\n#ifndef CMD_H\r\n#define CMD_H\r\n\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n\r\n#include \"def.h\"\r\n#include \"bsp.h\"\r\n#include \"hal.h\"\r\n\r\n\r\n\r\n\r\n\r\nvoid cmd_init(void);\r\n\r\nvoid cmd_send_error( msg_t *p_msg, err_code_t err_code );\r\nvoid cmd_read_version( msg_t *p_msg );\r\nvoid cmd_read_board_name( msg_t *p_msg );\r\nvoid cmd_read_tag( msg_t *p_msg );\r\nvoid cmd_jump_to_fw( msg_t *p_msg );\r\nvoid cmd_flash_fw_write_packet( msg_t *p_msg );\r\nvoid cmd_flash_fw_write_begin( msg_t *p_msg );\r\nvoid cmd_flash_fw_write_end( msg_t *p_msg );\r\nvoid cmd_flash_fw_write_block( msg_t *p_msg );\r\nvoid cmd_flash_fw_erase( msg_t *p_msg );\r\nvoid cmd_flash_fw_verify( msg_t *p_msg );\r\nvoid cmd_flash_fw_read_block( msg_t *p_msg );\r\n\r\nvoid jump_to_fw(void);\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/src/crc.c",
    "content": "/*\r\n *  crc.c\r\n *\r\n *  crc\r\n *\r\n *  Created on: 2016. 5. 30.\r\n *      Author: Baram, PBHP\r\n */\r\n\r\n#include \"crc.h\"\r\n#include <math.h>\r\n#include <string.h>\r\n#include <stdarg.h>\r\n#include <stdio.h>\r\n\r\n\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : crc_calc\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nuint32_t crc_calc( uint32_t crc_in, uint8_t data_in )\r\n{\r\n\r\n  crc_in  ^= data_in;\r\n  crc_in  += data_in;\r\n\r\n  return crc_in;\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_bootloader/src/crc.h",
    "content": "/*\r\n *  crc.h\r\n *\r\n *  command process\r\n *\r\n *  Created on: 2016. 5. 30.\r\n *      Author: Baram, PBHP\r\n */\r\n\r\n#ifndef CRC_H\r\n#define CRC_H\r\n\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n\r\n#include \"def.h\"\r\n#include \"bsp.h\"\r\n#include \"hal.h\"\r\n\r\n\r\n\r\n\r\n\r\nuint32_t crc_calc( uint32_t crc_in, uint8_t data_in );\r\n\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld/.cproject",
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    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\r\n<projectDescription>\r\n\t<name>opencr_ld</name>\r\n\t<comment></comment>\r\n\t<projects>\r\n\t</projects>\r\n\t<buildSpec>\r\n\t\t<buildCommand>\r\n\t\t\t<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>\r\n\t\t\t<triggers>clean,full,incremental,</triggers>\r\n\t\t\t<arguments>\r\n\t\t\t</arguments>\r\n\t\t</buildCommand>\r\n\t\t<buildCommand>\r\n\t\t\t<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>\r\n\t\t\t<triggers>full,incremental,</triggers>\r\n\t\t\t<arguments>\r\n\t\t\t</arguments>\r\n\t\t</buildCommand>\r\n\t</buildSpec>\r\n\t<natures>\r\n\t\t<nature>org.eclipse.cdt.core.cnature</nature>\r\n\t\t<nature>org.eclipse.cdt.core.ccnature</nature>\r\n\t\t<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>\r\n\t\t<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>\r\n\t</natures>\r\n</projectDescription>\r\n"
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    "content": "\r\n\r\n\r\nall: clean  opencr_ld\r\n\r\n\r\nSRCS  = main.c \r\nSRCS += opencr_ld.c \r\nSRCS += serial_posix.c\r\nSRCS += ./msg/msg.c\r\n\r\n\r\nopencr_ld:\r\n\tgcc -o opencr_ld $(SRCS)\r\n\r\nclean:\r\n\trm -f opencr_ld"
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    "path": "arduino/opencr_develop/opencr_ld/README.md",
    "content": "opencr_ld\r\n=======\r\n\r\nOpenCR DownLoader for arduino and normal firmware\r\n\r\n\r\n=======\r\nCompile - Mac/Linux\r\n\r\nmake\r\n\r\n=======\r\nCompile - Windows\r\n\r\ncomming soon.\r\n\r\n\r\n=======\r\nExecute \r\n\r\nopencr_ld /dev/tty 115200 main.bin 1 \r\n\r\n\r\n\r\n\r\n"
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    "path": "arduino/opencr_develop/opencr_ld/main.c",
    "content": "/*\r\n * OpenCR Loader\r\n *\r\n * by Baram\r\n * by PBPH\r\n * by http://oroca.org\r\n */\r\n\r\n\r\n#include <stdio.h>\r\n#include <stdlib.h>\r\n#include <string.h>\r\n#include <errno.h>\r\n#include <limits.h>\r\n#include \"opencr_ld.h\"\r\n\r\n\r\n\r\n\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : main\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nint main( int argc, const char **argv )\r\n{\r\n  u8 not_flashing=0;\r\n  u8 send_go_command=0;\r\n  u8 boot_mode = 0;\r\n  u8 minor, major;\r\n  u16 version;\r\n  long baud;\r\n \r\n\r\n  printf(\"opencr_ld ver 1.0.4\\n\");\r\n\r\n  if( argc < 4 )\r\n  {\r\n    fprintf( stderr, \"Usage: opencl_ld <port> <baud> <binary image name> [<0|1 to send Go command to new flashed app>]\\n\" );\r\n    exit( 1 );\r\n  }\r\n\r\n  errno = 0;\r\n  baud = strtol( argv[ 2 ], NULL, 10 );\r\n  if( ( errno == ERANGE && ( baud == LONG_MAX || baud == LONG_MIN ) ) || ( errno != 0 && baud == 0 ) || ( baud < 0 ) ) \r\n  {\r\n    fprintf( stderr, \"Invalid baud '%s'\\n\", argv[ 2 ] );\r\n    exit( 1 );\r\n  }\r\n  \r\n\r\n  opencr_ld_main( argc, argv );\r\n  \r\n  return 0;\r\n}\r\n           \r\n"
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    "path": "arduino/opencr_develop/opencr_ld/msg/def.h",
    "content": "/*\r\n *  def.h\r\n *\r\n *  Created on: 2016. 5. 14.\r\n *      Author: Baram, PBPH\r\n */\r\n\r\n#ifndef DEF_H\r\n#define DEF_H\r\n\r\n#include <stdint.h>\r\n#include \"def_err.h\"\r\n\r\n#ifndef BOOL\r\n#define BOOL uint8_t\r\n#endif\r\n\r\n#ifndef TRUE\r\n#define TRUE  1\r\n#endif\r\n\r\n#ifndef FALSE\r\n#define FALSE 0\r\n#endif\r\n\r\n#ifndef bool\r\n#define bool uint8_t\r\n#endif\r\n\r\n#ifndef true\r\n#define true  1\r\n#endif\r\n\r\n#ifndef false\r\n#define false 0\r\n#endif\r\n\r\n\r\n#include \"./mavlink/opencr_msg/mavlink.h\"\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n#endif\r\n\r\n"
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    "path": "arduino/opencr_develop/opencr_ld/msg/def_err.h",
    "content": "/*\r\n *  def_err.h\r\n *\r\n *  Created on: 2016. 5. 14.\r\n *      Author: Baram, PBPH\r\n */\r\n\r\n#ifndef DEF_ERR_H\r\n#define DEF_ERR_H\r\n\r\n#include <stdint.h>\r\n\r\n\r\n\r\ntypedef uint16_t err_code_t;\r\n\r\n\r\n\r\n\r\n#define OK                                  0x0000\r\n#define ERR_FLASH_ERROR                     0xF010\r\n#define ERR_FLASH_BUSY                      0xF011\r\n#define ERR_FLASH_ERR_TIMEOUT               0xF012\r\n#define ERR_FLASH_NOT_EMPTY                 0xF013\r\n#define ERR_FLASH_WRITE                     0xF014\r\n#define ERR_FLASH_READ                      0xF015\r\n#define ERR_FLASH_ERASE                     0xF016\r\n\r\n#define ERR_TIMEOUT                         0xF020\r\n#define ERR_MISMATCH_ID                     0xF021\r\n#define ERR_SIZE_OVER                       0xF022\r\n\r\n\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld/msg/mavlink/checksum.h",
    "content": "#ifdef __cplusplus\r\nextern \"C\" {\r\n#endif\r\n\r\n#ifndef _CHECKSUM_H_\r\n#define _CHECKSUM_H_\r\n\r\n// Visual Studio versions before 2010 don't have stdint.h, so we just error out.\r\n#if (defined _MSC_VER) && (_MSC_VER < 1600)\r\n#error \"The C-MAVLink implementation requires Visual Studio 2010 or greater\"\r\n#endif\r\n\r\n#include <stdint.h>\r\n\r\n/**\r\n *\r\n *  CALCULATE THE CHECKSUM\r\n *\r\n */\r\n\r\n#define X25_INIT_CRC 0xffff\r\n#define X25_VALIDATE_CRC 0xf0b8\r\n\r\n#ifndef HAVE_CRC_ACCUMULATE\r\n/**\r\n * @brief Accumulate the X.25 CRC by adding one char at a time.\r\n *\r\n * The checksum function adds the hash of one char at a time to the\r\n * 16 bit checksum (uint16_t).\r\n *\r\n * @param data new char to hash\r\n * @param crcAccum the already accumulated checksum\r\n **/\r\nstatic inline void crc_accumulate(uint8_t data, uint16_t *crcAccum)\r\n{\r\n        /*Accumulate one byte of data into the CRC*/\r\n        uint8_t tmp;\r\n\r\n        tmp = data ^ (uint8_t)(*crcAccum &0xff);\r\n        tmp ^= (tmp<<4);\r\n        *crcAccum = (*crcAccum>>8) ^ (tmp<<8) ^ (tmp <<3) ^ (tmp>>4);\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n * @brief Initiliaze the buffer for the X.25 CRC\r\n *\r\n * @param crcAccum the 16 bit X.25 CRC\r\n */\r\nstatic inline void crc_init(uint16_t* crcAccum)\r\n{\r\n        *crcAccum = X25_INIT_CRC;\r\n}\r\n\r\n\r\n/**\r\n * @brief Calculates the X.25 checksum on a byte buffer\r\n *\r\n * @param  pBuffer buffer containing the byte array to hash\r\n * @param  length  length of the byte array\r\n * @return the checksum over the buffer bytes\r\n **/\r\nstatic inline uint16_t crc_calculate(const uint8_t* pBuffer, uint16_t length)\r\n{\r\n        uint16_t crcTmp;\r\n        crc_init(&crcTmp);\r\n\twhile (length--) {\r\n                crc_accumulate(*pBuffer++, &crcTmp);\r\n        }\r\n        return crcTmp;\r\n}\r\n\r\n\r\n/**\r\n * @brief Accumulate the X.25 CRC by adding an array of bytes\r\n *\r\n * The checksum function adds the hash of one char at a time to the\r\n * 16 bit checksum (uint16_t).\r\n *\r\n * @param data new bytes to hash\r\n * @param crcAccum the already accumulated checksum\r\n **/\r\nstatic inline void crc_accumulate_buffer(uint16_t *crcAccum, const char *pBuffer, uint16_t length)\r\n{\r\n\tconst uint8_t *p = (const uint8_t *)pBuffer;\r\n\twhile (length--) {\r\n                crc_accumulate(*p++, crcAccum);\r\n        }\r\n}\r\n\r\n#endif /* _CHECKSUM_H_ */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld/msg/mavlink/mavlink_conversions.h",
    "content": "#ifndef  _MAVLINK_CONVERSIONS_H_\r\n#define  _MAVLINK_CONVERSIONS_H_\r\n\r\n/* enable math defines on Windows */\r\n#ifdef _MSC_VER\r\n#ifndef _USE_MATH_DEFINES\r\n#define _USE_MATH_DEFINES\r\n#endif\r\n#endif\r\n#include <math.h>\r\n\r\n#ifndef M_PI_2\r\n    #define M_PI_2 ((float)asin(1))\r\n#endif\r\n\r\n/**\r\n * @file mavlink_conversions.h\r\n *\r\n * These conversion functions follow the NASA rotation standards definition file\r\n * available online.\r\n *\r\n * Their intent is to lower the barrier for MAVLink adopters to use gimbal-lock free\r\n * (both rotation matrices, sometimes called DCM, and quaternions are gimbal-lock free)\r\n * rotation representations. Euler angles (roll, pitch, yaw) will be phased out of the\r\n * protocol as widely as possible.\r\n *\r\n * @author James Goppert\r\n * @author Thomas Gubler <thomasgubler@gmail.com>\r\n */\r\n\r\n\r\n/**\r\n * Converts a quaternion to a rotation matrix\r\n *\r\n * @param quaternion a [w, x, y, z] ordered quaternion (null-rotation being 1 0 0 0)\r\n * @param dcm a 3x3 rotation matrix\r\n */\r\nMAVLINK_HELPER void mavlink_quaternion_to_dcm(const float quaternion[4], float dcm[3][3])\r\n{\r\n    double a = quaternion[0];\r\n    double b = quaternion[1];\r\n    double c = quaternion[2];\r\n    double d = quaternion[3];\r\n    double aSq = a * a;\r\n    double bSq = b * b;\r\n    double cSq = c * c;\r\n    double dSq = d * d;\r\n    dcm[0][0] = aSq + bSq - cSq - dSq;\r\n    dcm[0][1] = 2 * (b * c - a * d);\r\n    dcm[0][2] = 2 * (a * c + b * d);\r\n    dcm[1][0] = 2 * (b * c + a * d);\r\n    dcm[1][1] = aSq - bSq + cSq - dSq;\r\n    dcm[1][2] = 2 * (c * d - a * b);\r\n    dcm[2][0] = 2 * (b * d - a * c);\r\n    dcm[2][1] = 2 * (a * b + c * d);\r\n    dcm[2][2] = aSq - bSq - cSq + dSq;\r\n}\r\n\r\n\r\n/**\r\n * Converts a rotation matrix to euler angles\r\n *\r\n * @param dcm a 3x3 rotation matrix\r\n * @param roll the roll angle in radians\r\n * @param pitch the pitch angle in radians\r\n * @param yaw the yaw angle in radians\r\n */\r\nMAVLINK_HELPER void mavlink_dcm_to_euler(const float dcm[3][3], float* roll, float* pitch, float* yaw)\r\n{\r\n    float phi, theta, psi;\r\n    theta = asin(-dcm[2][0]);\r\n\r\n    if (fabsf(theta - (float)M_PI_2) < 1.0e-3f) {\r\n        phi = 0.0f;\r\n        psi = (atan2f(dcm[1][2] - dcm[0][1],\r\n                dcm[0][2] + dcm[1][1]) + phi);\r\n\r\n    } else if (fabsf(theta + (float)M_PI_2) < 1.0e-3f) {\r\n        phi = 0.0f;\r\n        psi = atan2f(dcm[1][2] - dcm[0][1],\r\n                  dcm[0][2] + dcm[1][1] - phi);\r\n\r\n    } else {\r\n        phi = atan2f(dcm[2][1], dcm[2][2]);\r\n        psi = atan2f(dcm[1][0], dcm[0][0]);\r\n    }\r\n\r\n    *roll = phi;\r\n    *pitch = theta;\r\n    *yaw = psi;\r\n}\r\n\r\n\r\n/**\r\n * Converts a quaternion to euler angles\r\n *\r\n * @param quaternion a [w, x, y, z] ordered quaternion (null-rotation being 1 0 0 0)\r\n * @param roll the roll angle in radians\r\n * @param pitch the pitch angle in radians\r\n * @param yaw the yaw angle in radians\r\n */\r\nMAVLINK_HELPER void mavlink_quaternion_to_euler(const float quaternion[4], float* roll, float* pitch, float* yaw)\r\n{\r\n    float dcm[3][3];\r\n    mavlink_quaternion_to_dcm(quaternion, dcm);\r\n    mavlink_dcm_to_euler((const float(*)[3])dcm, roll, pitch, yaw);\r\n}\r\n\r\n\r\n/**\r\n * Converts euler angles to a quaternion\r\n *\r\n * @param roll the roll angle in radians\r\n * @param pitch the pitch angle in radians\r\n * @param yaw the yaw angle in radians\r\n * @param quaternion a [w, x, y, z] ordered quaternion (null-rotation being 1 0 0 0)\r\n */\r\nMAVLINK_HELPER void mavlink_euler_to_quaternion(float roll, float pitch, float yaw, float quaternion[4])\r\n{\r\n    float cosPhi_2 = cosf(roll / 2);\r\n    float sinPhi_2 = sinf(roll / 2);\r\n    float cosTheta_2 = cosf(pitch / 2);\r\n    float sinTheta_2 = sinf(pitch / 2);\r\n    float cosPsi_2 = cosf(yaw / 2);\r\n    float sinPsi_2 = sinf(yaw / 2);\r\n    quaternion[0] = (cosPhi_2 * cosTheta_2 * cosPsi_2 +\r\n            sinPhi_2 * sinTheta_2 * sinPsi_2);\r\n    quaternion[1] = (sinPhi_2 * cosTheta_2 * cosPsi_2 -\r\n            cosPhi_2 * sinTheta_2 * sinPsi_2);\r\n    quaternion[2] = (cosPhi_2 * sinTheta_2 * cosPsi_2 +\r\n            sinPhi_2 * cosTheta_2 * sinPsi_2);\r\n    quaternion[3] = (cosPhi_2 * cosTheta_2 * sinPsi_2 -\r\n            sinPhi_2 * sinTheta_2 * cosPsi_2);\r\n}\r\n\r\n\r\n/**\r\n * Converts a rotation matrix to a quaternion\r\n * Reference:\r\n *  - Shoemake, Quaternions,\r\n *  http://www.cs.ucr.edu/~vbz/resources/quatut.pdf\r\n *\r\n * @param dcm a 3x3 rotation matrix\r\n * @param quaternion a [w, x, y, z] ordered quaternion (null-rotation being 1 0 0 0)\r\n */\r\nMAVLINK_HELPER void mavlink_dcm_to_quaternion(const float dcm[3][3], float quaternion[4])\r\n{\r\n    float tr = dcm[0][0] + dcm[1][1] + dcm[2][2];\r\n    if (tr > 0.0f) {\r\n        float s = sqrtf(tr + 1.0f);\r\n        quaternion[0] = s * 0.5f;\r\n        s = 0.5f / s;\r\n        quaternion[1] = (dcm[2][1] - dcm[1][2]) * s;\r\n        quaternion[2] = (dcm[0][2] - dcm[2][0]) * s;\r\n        quaternion[3] = (dcm[1][0] - dcm[0][1]) * s;\r\n    } else {\r\n        /* Find maximum diagonal element in dcm\r\n         * store index in dcm_i */\r\n        int dcm_i = 0;\r\n        int i;\r\n        for (i = 1; i < 3; i++) {\r\n            if (dcm[i][i] > dcm[dcm_i][dcm_i]) {\r\n                dcm_i = i;\r\n            }\r\n        }\r\n\r\n        int dcm_j = (dcm_i + 1) % 3;\r\n        int dcm_k = (dcm_i + 2) % 3;\r\n\r\n        float s = sqrtf((dcm[dcm_i][dcm_i] - dcm[dcm_j][dcm_j] -\r\n                    dcm[dcm_k][dcm_k]) + 1.0f);\r\n        quaternion[dcm_i + 1] = s * 0.5f;\r\n        s = 0.5f / s;\r\n        quaternion[dcm_j + 1] = (dcm[dcm_i][dcm_j] + dcm[dcm_j][dcm_i]) * s;\r\n        quaternion[dcm_k + 1] = (dcm[dcm_k][dcm_i] + dcm[dcm_i][dcm_k]) * s;\r\n        quaternion[0] = (dcm[dcm_k][dcm_j] - dcm[dcm_j][dcm_k]) * s;\r\n    }\r\n}\r\n\r\n\r\n/**\r\n * Converts euler angles to a rotation matrix\r\n *\r\n * @param roll the roll angle in radians\r\n * @param pitch the pitch angle in radians\r\n * @param yaw the yaw angle in radians\r\n * @param dcm a 3x3 rotation matrix\r\n */\r\nMAVLINK_HELPER void mavlink_euler_to_dcm(float roll, float pitch, float yaw, float dcm[3][3])\r\n{\r\n    float cosPhi = cosf(roll);\r\n    float sinPhi = sinf(roll);\r\n    float cosThe = cosf(pitch);\r\n    float sinThe = sinf(pitch);\r\n    float cosPsi = cosf(yaw);\r\n    float sinPsi = sinf(yaw);\r\n\r\n    dcm[0][0] = cosThe * cosPsi;\r\n    dcm[0][1] = -cosPhi * sinPsi + sinPhi * sinThe * cosPsi;\r\n    dcm[0][2] = sinPhi * sinPsi + cosPhi * sinThe * cosPsi;\r\n\r\n    dcm[1][0] = cosThe * sinPsi;\r\n    dcm[1][1] = cosPhi * cosPsi + sinPhi * sinThe * sinPsi;\r\n    dcm[1][2] = -sinPhi * cosPsi + cosPhi * sinThe * sinPsi;\r\n\r\n    dcm[2][0] = -sinThe;\r\n    dcm[2][1] = sinPhi * cosThe;\r\n    dcm[2][2] = cosPhi * cosThe;\r\n}\r\n\r\n#endif\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld/msg/mavlink/mavlink_helpers.h",
    "content": "#ifndef  _MAVLINK_HELPERS_H_\r\n#define  _MAVLINK_HELPERS_H_\r\n\r\n#include \"string.h\"\r\n#include \"checksum.h\"\r\n#include \"mavlink_types.h\"\r\n#include \"mavlink_conversions.h\"\r\n\r\n#ifndef MAVLINK_HELPER\r\n#define MAVLINK_HELPER\r\n#endif\r\n\r\n/*\r\n * Internal function to give access to the channel status for each channel\r\n */\r\n#ifndef MAVLINK_GET_CHANNEL_STATUS\r\nMAVLINK_HELPER mavlink_status_t* mavlink_get_channel_status(uint8_t chan)\r\n{\r\n#ifdef MAVLINK_EXTERNAL_RX_STATUS\r\n\t// No m_mavlink_status array defined in function,\r\n\t// has to be defined externally\r\n#else\r\n\tstatic mavlink_status_t m_mavlink_status[MAVLINK_COMM_NUM_BUFFERS];\r\n#endif\r\n\treturn &m_mavlink_status[chan];\r\n}\r\n#endif\r\n\r\n/*\r\n * Internal function to give access to the channel buffer for each channel\r\n */\r\n#ifndef MAVLINK_GET_CHANNEL_BUFFER\r\nMAVLINK_HELPER mavlink_message_t* mavlink_get_channel_buffer(uint8_t chan)\r\n{\r\n\t\r\n#ifdef MAVLINK_EXTERNAL_RX_BUFFER\r\n\t// No m_mavlink_buffer array defined in function,\r\n\t// has to be defined externally\r\n#else\r\n\tstatic mavlink_message_t m_mavlink_buffer[MAVLINK_COMM_NUM_BUFFERS];\r\n#endif\r\n\treturn &m_mavlink_buffer[chan];\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Reset the status of a channel.\r\n */\r\nMAVLINK_HELPER void mavlink_reset_channel_status(uint8_t chan)\r\n{\r\n\tmavlink_status_t *status = mavlink_get_channel_status(chan);\r\n\tstatus->parse_state = MAVLINK_PARSE_STATE_IDLE;\r\n}\r\n\r\n/**\r\n * @brief Finalize a MAVLink message with channel assignment\r\n *\r\n * This function calculates the checksum and sets length and aircraft id correctly.\r\n * It assumes that the message id and the payload are already correctly set. This function\r\n * can also be used if the message header has already been written before (as in mavlink_msg_xxx_pack\r\n * instead of mavlink_msg_xxx_pack_headerless), it just introduces little extra overhead.\r\n *\r\n * @param msg Message to finalize\r\n * @param system_id Id of the sending (this) system, 1-127\r\n * @param length Message length\r\n */\r\n#if MAVLINK_CRC_EXTRA\r\nMAVLINK_HELPER uint16_t mavlink_finalize_message_chan(mavlink_message_t* msg, uint8_t system_id, uint8_t component_id, \r\n\t\t\t\t\t\t      uint8_t chan, uint8_t min_length, uint8_t length, uint8_t crc_extra)\r\n#else\r\nMAVLINK_HELPER uint16_t mavlink_finalize_message_chan(mavlink_message_t* msg, uint8_t system_id, uint8_t component_id, \r\n\t\t\t\t\t\t      uint8_t chan, uint8_t length)\r\n#endif\r\n{\r\n\t// This code part is the same for all messages;\r\n\tmsg->magic = MAVLINK_STX;\r\n\tmsg->len = length;\r\n\tmsg->sysid = system_id;\r\n\tmsg->compid = component_id;\r\n\t// One sequence number per channel\r\n\tmsg->seq = mavlink_get_channel_status(chan)->current_tx_seq;\r\n\tmavlink_get_channel_status(chan)->current_tx_seq = mavlink_get_channel_status(chan)->current_tx_seq+1;\r\n\tmsg->checksum = crc_calculate(((const uint8_t*)(msg)) + 3, MAVLINK_CORE_HEADER_LEN);\r\n\tcrc_accumulate_buffer(&msg->checksum, _MAV_PAYLOAD(msg), msg->len);\r\n#if MAVLINK_CRC_EXTRA\r\n\tcrc_accumulate(crc_extra, &msg->checksum);\r\n#endif\r\n\tmavlink_ck_a(msg) = (uint8_t)(msg->checksum & 0xFF);\r\n\tmavlink_ck_b(msg) = (uint8_t)(msg->checksum >> 8);\r\n\r\n\treturn length + MAVLINK_NUM_NON_PAYLOAD_BYTES;\r\n}\r\n\r\n\r\n/**\r\n * @brief Finalize a MAVLink message with MAVLINK_COMM_0 as default channel\r\n */\r\n#if MAVLINK_CRC_EXTRA\r\nMAVLINK_HELPER uint16_t mavlink_finalize_message(mavlink_message_t* msg, uint8_t system_id, uint8_t component_id, \r\n\t\t\t\t\t\t uint8_t min_length, uint8_t length, uint8_t crc_extra)\r\n{\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, MAVLINK_COMM_0, min_length, length, crc_extra);\r\n}\r\n#else\r\nMAVLINK_HELPER uint16_t mavlink_finalize_message(mavlink_message_t* msg, uint8_t system_id, uint8_t component_id, \r\n\t\t\t\t\t\t uint8_t length)\r\n{\r\n\treturn mavlink_finalize_message_chan(msg, system_id, component_id, MAVLINK_COMM_0, length);\r\n}\r\n#endif\r\n\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\nMAVLINK_HELPER void _mavlink_send_uart(mavlink_channel_t chan, const char *buf, uint16_t len);\r\n\r\n/**\r\n * @brief Finalize a MAVLink message with channel assignment and send\r\n */\r\n#if MAVLINK_CRC_EXTRA\r\nMAVLINK_HELPER void _mav_finalize_message_chan_send(mavlink_channel_t chan, uint8_t msgid, const char *packet, \r\n\t\t\t\t\t\t    uint8_t min_length, uint8_t length, uint8_t crc_extra)\r\n#else\r\nMAVLINK_HELPER void _mav_finalize_message_chan_send(mavlink_channel_t chan, uint8_t msgid, const char *packet, uint8_t length)\r\n#endif\r\n{\r\n\tuint16_t checksum;\r\n\tuint8_t buf[MAVLINK_NUM_HEADER_BYTES];\r\n\tuint8_t ck[2];\r\n\tmavlink_status_t *status = mavlink_get_channel_status(chan);\r\n\tbuf[0] = MAVLINK_STX;\r\n\tbuf[1] = length;\r\n\tbuf[2] = status->current_tx_seq;\r\n\tbuf[3] = mavlink_system.sysid;\r\n\tbuf[4] = mavlink_system.compid;\r\n\tbuf[5] = msgid;\r\n\tstatus->current_tx_seq++;\r\n\tchecksum = crc_calculate((const uint8_t*)&buf[1], MAVLINK_CORE_HEADER_LEN);\r\n\tcrc_accumulate_buffer(&checksum, packet, length);\r\n#if MAVLINK_CRC_EXTRA\r\n\tcrc_accumulate(crc_extra, &checksum);\r\n#endif\r\n\tck[0] = (uint8_t)(checksum & 0xFF);\r\n\tck[1] = (uint8_t)(checksum >> 8);\r\n\r\n\tMAVLINK_START_UART_SEND(chan, MAVLINK_NUM_NON_PAYLOAD_BYTES + (uint16_t)length);\r\n\t_mavlink_send_uart(chan, (const char *)buf, MAVLINK_NUM_HEADER_BYTES);\r\n\t_mavlink_send_uart(chan, packet, length);\r\n\t_mavlink_send_uart(chan, (const char *)ck, 2);\r\n\tMAVLINK_END_UART_SEND(chan, MAVLINK_NUM_NON_PAYLOAD_BYTES + (uint16_t)length);\r\n}\r\n\r\n/**\r\n * @brief re-send a message over a uart channel\r\n * this is more stack efficient than re-marshalling the message\r\n */\r\nMAVLINK_HELPER void _mavlink_resend_uart(mavlink_channel_t chan, const mavlink_message_t *msg)\r\n{\r\n\tuint8_t ck[2];\r\n\r\n\tck[0] = (uint8_t)(msg->checksum & 0xFF);\r\n\tck[1] = (uint8_t)(msg->checksum >> 8);\r\n\t// XXX use the right sequence here\r\n\r\n\tMAVLINK_START_UART_SEND(chan, MAVLINK_NUM_NON_PAYLOAD_BYTES + msg->len);\r\n\t_mavlink_send_uart(chan, (const char *)&msg->magic, MAVLINK_NUM_HEADER_BYTES);\r\n\t_mavlink_send_uart(chan, _MAV_PAYLOAD(msg), msg->len);\r\n\t_mavlink_send_uart(chan, (const char *)ck, 2);\r\n\tMAVLINK_END_UART_SEND(chan, MAVLINK_NUM_NON_PAYLOAD_BYTES + msg->len);\r\n}\r\n#endif // MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\n/**\r\n * @brief Pack a message to send it over a serial byte stream\r\n */\r\nMAVLINK_HELPER uint16_t mavlink_msg_to_send_buffer(uint8_t *buffer, const mavlink_message_t *msg)\r\n{\r\n\tmemcpy(buffer, (const uint8_t *)&msg->magic, MAVLINK_NUM_HEADER_BYTES + (uint16_t)msg->len);\r\n\r\n\tuint8_t *ck = buffer + (MAVLINK_NUM_HEADER_BYTES + (uint16_t)msg->len);\r\n\r\n\tck[0] = (uint8_t)(msg->checksum & 0xFF);\r\n\tck[1] = (uint8_t)(msg->checksum >> 8);\r\n\r\n\treturn MAVLINK_NUM_NON_PAYLOAD_BYTES + (uint16_t)msg->len;\r\n}\r\n\r\nunion __mavlink_bitfield {\r\n\tuint8_t uint8;\r\n\tint8_t int8;\r\n\tuint16_t uint16;\r\n\tint16_t int16;\r\n\tuint32_t uint32;\r\n\tint32_t int32;\r\n};\r\n\r\n\r\nMAVLINK_HELPER void mavlink_start_checksum(mavlink_message_t* msg)\r\n{\r\n\tcrc_init(&msg->checksum);\r\n}\r\n\r\nMAVLINK_HELPER void mavlink_update_checksum(mavlink_message_t* msg, uint8_t c)\r\n{\r\n\tcrc_accumulate(c, &msg->checksum);\r\n}\r\n\r\n/**\r\n * This is a varient of mavlink_frame_char() but with caller supplied\r\n * parsing buffers. It is useful when you want to create a MAVLink\r\n * parser in a library that doesn't use any global variables\r\n *\r\n * @param rxmsg    parsing message buffer\r\n * @param status   parsing starus buffer \r\n * @param c        The char to parse\r\n *\r\n * @param returnMsg NULL if no message could be decoded, the message data else\r\n * @param returnStats if a message was decoded, this is filled with the channel's stats\r\n * @return 0 if no message could be decoded, 1 on good message and CRC, 2 on bad CRC\r\n *\r\n * A typical use scenario of this function call is:\r\n *\r\n * @code\r\n * #include <mavlink.h>\r\n *\r\n * mavlink_message_t msg;\r\n * int chan = 0;\r\n *\r\n *\r\n * while(serial.bytesAvailable > 0)\r\n * {\r\n *   uint8_t byte = serial.getNextByte();\r\n *   if (mavlink_frame_char(chan, byte, &msg) != MAVLINK_FRAMING_INCOMPLETE)\r\n *     {\r\n *     printf(\"Received message with ID %d, sequence: %d from component %d of system %d\", msg.msgid, msg.seq, msg.compid, msg.sysid);\r\n *     }\r\n * }\r\n *\r\n *\r\n * @endcode\r\n */\r\nMAVLINK_HELPER uint8_t mavlink_frame_char_buffer(mavlink_message_t* rxmsg, \r\n                                                 mavlink_status_t* status,\r\n                                                 uint8_t c, \r\n                                                 mavlink_message_t* r_message, \r\n                                                 mavlink_status_t* r_mavlink_status)\r\n{\r\n        /*\r\n\t  default message crc function. You can override this per-system to\r\n\t  put this data in a different memory segment\r\n\t*/\r\n#if MAVLINK_CRC_EXTRA\r\n#ifndef MAVLINK_MESSAGE_CRC\r\n\tstatic const uint8_t mavlink_message_crcs[256] = MAVLINK_MESSAGE_CRCS;\r\n#define MAVLINK_MESSAGE_CRC(msgid) mavlink_message_crcs[msgid]\r\n#endif\r\n#endif\r\n\r\n\t/* Enable this option to check the length of each message.\r\n\t   This allows invalid messages to be caught much sooner. Use if the transmission\r\n\t   medium is prone to missing (or extra) characters (e.g. a radio that fades in\r\n\t   and out). Only use if the channel will only contain messages types listed in\r\n\t   the headers.\r\n\t*/\r\n#ifdef MAVLINK_CHECK_MESSAGE_LENGTH\r\n#ifndef MAVLINK_MESSAGE_LENGTH\r\n\tstatic const uint8_t mavlink_message_lengths[256] = MAVLINK_MESSAGE_LENGTHS;\r\n#define MAVLINK_MESSAGE_LENGTH(msgid) mavlink_message_lengths[msgid]\r\n#endif\r\n#endif\r\n\r\n\tint bufferIndex = 0;\r\n\r\n\tstatus->msg_received = MAVLINK_FRAMING_INCOMPLETE;\r\n\r\n\tswitch (status->parse_state)\r\n\t{\r\n\tcase MAVLINK_PARSE_STATE_UNINIT:\r\n\tcase MAVLINK_PARSE_STATE_IDLE:\r\n\t\tif (c == MAVLINK_STX)\r\n\t\t{\r\n\t\t\tstatus->parse_state = MAVLINK_PARSE_STATE_GOT_STX;\r\n\t\t\trxmsg->len = 0;\r\n\t\t\trxmsg->magic = c;\r\n\t\t\tmavlink_start_checksum(rxmsg);\r\n\t\t}\r\n\t\tbreak;\r\n\r\n\tcase MAVLINK_PARSE_STATE_GOT_STX:\r\n\t\t\tif (status->msg_received \r\n/* Support shorter buffers than the\r\n   default maximum packet size */\r\n#if (MAVLINK_MAX_PAYLOAD_LEN < 255)\r\n\t\t\t\t|| c > MAVLINK_MAX_PAYLOAD_LEN\r\n#endif\r\n\t\t\t\t)\r\n\t\t{\r\n\t\t\tstatus->buffer_overrun++;\r\n\t\t\tstatus->parse_error++;\r\n\t\t\tstatus->msg_received = 0;\r\n\t\t\tstatus->parse_state = MAVLINK_PARSE_STATE_IDLE;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\t// NOT counting STX, LENGTH, SEQ, SYSID, COMPID, MSGID, CRC1 and CRC2\r\n\t\t\trxmsg->len = c;\r\n\t\t\tstatus->packet_idx = 0;\r\n\t\t\tmavlink_update_checksum(rxmsg, c);\r\n\t\t\tstatus->parse_state = MAVLINK_PARSE_STATE_GOT_LENGTH;\r\n\t\t}\r\n\t\tbreak;\r\n\r\n\tcase MAVLINK_PARSE_STATE_GOT_LENGTH:\r\n\t\trxmsg->seq = c;\r\n\t\tmavlink_update_checksum(rxmsg, c);\r\n\t\tstatus->parse_state = MAVLINK_PARSE_STATE_GOT_SEQ;\r\n\t\tbreak;\r\n\r\n\tcase MAVLINK_PARSE_STATE_GOT_SEQ:\r\n\t\trxmsg->sysid = c;\r\n\t\tmavlink_update_checksum(rxmsg, c);\r\n\t\tstatus->parse_state = MAVLINK_PARSE_STATE_GOT_SYSID;\r\n\t\tbreak;\r\n\r\n\tcase MAVLINK_PARSE_STATE_GOT_SYSID:\r\n\t\trxmsg->compid = c;\r\n\t\tmavlink_update_checksum(rxmsg, c);\r\n\t\tstatus->parse_state = MAVLINK_PARSE_STATE_GOT_COMPID;\r\n\t\tbreak;\r\n\r\n\tcase MAVLINK_PARSE_STATE_GOT_COMPID:\r\n#ifdef MAVLINK_CHECK_MESSAGE_LENGTH\r\n\t        if (rxmsg->len != MAVLINK_MESSAGE_LENGTH(c))\r\n\t\t{\r\n\t\t\tstatus->parse_error++;\r\n\t\t\tstatus->parse_state = MAVLINK_PARSE_STATE_IDLE;\r\n\t\t\tbreak;\r\n\t    }\r\n#endif\r\n\t\trxmsg->msgid = c;\r\n\t\tmavlink_update_checksum(rxmsg, c);\r\n\t\tif (rxmsg->len == 0)\r\n\t\t{\r\n\t\t\tstatus->parse_state = MAVLINK_PARSE_STATE_GOT_PAYLOAD;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tstatus->parse_state = MAVLINK_PARSE_STATE_GOT_MSGID;\r\n\t\t}\r\n\t\tbreak;\r\n\r\n\tcase MAVLINK_PARSE_STATE_GOT_MSGID:\r\n\t\t_MAV_PAYLOAD_NON_CONST(rxmsg)[status->packet_idx++] = (char)c;\r\n\t\tmavlink_update_checksum(rxmsg, c);\r\n\t\tif (status->packet_idx == rxmsg->len)\r\n\t\t{\r\n\t\t\tstatus->parse_state = MAVLINK_PARSE_STATE_GOT_PAYLOAD;\r\n\t\t}\r\n\t\tbreak;\r\n\r\n\tcase MAVLINK_PARSE_STATE_GOT_PAYLOAD:\r\n#if MAVLINK_CRC_EXTRA\r\n\t\tmavlink_update_checksum(rxmsg, MAVLINK_MESSAGE_CRC(rxmsg->msgid));\r\n#endif\r\n\t\tif (c != (rxmsg->checksum & 0xFF)) {\r\n\t\t\tstatus->parse_state = MAVLINK_PARSE_STATE_GOT_BAD_CRC1;\r\n\t\t} else {\r\n\t\t\tstatus->parse_state = MAVLINK_PARSE_STATE_GOT_CRC1;\r\n\t\t}\r\n                _MAV_PAYLOAD_NON_CONST(rxmsg)[status->packet_idx] = (char)c;\r\n\t\tbreak;\r\n\r\n\tcase MAVLINK_PARSE_STATE_GOT_CRC1:\r\n\tcase MAVLINK_PARSE_STATE_GOT_BAD_CRC1:\r\n\t\tif (status->parse_state == MAVLINK_PARSE_STATE_GOT_BAD_CRC1 || c != (rxmsg->checksum >> 8)) {\r\n\t\t\t// got a bad CRC message\r\n\t\t\tstatus->msg_received = MAVLINK_FRAMING_BAD_CRC;\r\n\t\t} else {\r\n\t\t\t// Successfully got message\r\n\t\t\tstatus->msg_received = MAVLINK_FRAMING_OK;\r\n                }\r\n                status->parse_state = MAVLINK_PARSE_STATE_IDLE;\r\n                _MAV_PAYLOAD_NON_CONST(rxmsg)[status->packet_idx+1] = (char)c;\r\n                memcpy(r_message, rxmsg, sizeof(mavlink_message_t));\r\n\t\tbreak;\r\n\t}\r\n\r\n\tbufferIndex++;\r\n\t// If a message has been sucessfully decoded, check index\r\n\tif (status->msg_received == MAVLINK_FRAMING_OK)\r\n\t{\r\n\t\t//while(status->current_seq != rxmsg->seq)\r\n\t\t//{\r\n\t\t//\tstatus->packet_rx_drop_count++;\r\n\t\t//               status->current_seq++;\r\n\t\t//}\r\n\t\tstatus->current_rx_seq = rxmsg->seq;\r\n\t\t// Initial condition: If no packet has been received so far, drop count is undefined\r\n\t\tif (status->packet_rx_success_count == 0) status->packet_rx_drop_count = 0;\r\n\t\t// Count this packet as received\r\n\t\tstatus->packet_rx_success_count++;\r\n\t}\r\n\r\n\tr_message->len = rxmsg->len; // Provide visibility on how far we are into current msg\r\n\tr_mavlink_status->parse_state = status->parse_state;\r\n\tr_mavlink_status->packet_idx = status->packet_idx;\r\n\tr_mavlink_status->current_rx_seq = status->current_rx_seq+1;\r\n\tr_mavlink_status->packet_rx_success_count = status->packet_rx_success_count;\r\n\tr_mavlink_status->packet_rx_drop_count = status->parse_error;\r\n\tstatus->parse_error = 0;\r\n\r\n\tif (status->msg_received == MAVLINK_FRAMING_BAD_CRC) {\r\n\t\t/*\r\n\t\t  the CRC came out wrong. We now need to overwrite the\r\n\t\t  msg CRC with the one on the wire so that if the\r\n\t\t  caller decides to forward the message anyway that\r\n\t\t  mavlink_msg_to_send_buffer() won't overwrite the\r\n\t\t  checksum\r\n\t\t */\r\n\t\tr_message->checksum = _MAV_PAYLOAD(rxmsg)[status->packet_idx] | (_MAV_PAYLOAD(rxmsg)[status->packet_idx+1]<<8);\r\n\t}\r\n\r\n\treturn status->msg_received;\r\n}\r\n\r\n/**\r\n * This is a convenience function which handles the complete MAVLink parsing.\r\n * the function will parse one byte at a time and return the complete packet once\r\n * it could be successfully decoded. This function will return 0, 1 or\r\n * 2 (MAVLINK_FRAMING_INCOMPLETE, MAVLINK_FRAMING_OK or MAVLINK_FRAMING_BAD_CRC)\r\n *\r\n * Messages are parsed into an internal buffer (one for each channel). When a complete\r\n * message is received it is copies into *returnMsg and the channel's status is\r\n * copied into *returnStats.\r\n *\r\n * @param chan     ID of the current channel. This allows to parse different channels with this function.\r\n *                 a channel is not a physical message channel like a serial port, but a logic partition of\r\n *                 the communication streams in this case. COMM_NB is the limit for the number of channels\r\n *                 on MCU (e.g. ARM7), while COMM_NB_HIGH is the limit for the number of channels in Linux/Windows\r\n * @param c        The char to parse\r\n *\r\n * @param returnMsg NULL if no message could be decoded, the message data else\r\n * @param returnStats if a message was decoded, this is filled with the channel's stats\r\n * @return 0 if no message could be decoded, 1 on good message and CRC, 2 on bad CRC\r\n *\r\n * A typical use scenario of this function call is:\r\n *\r\n * @code\r\n * #include <mavlink.h>\r\n *\r\n * mavlink_message_t msg;\r\n * int chan = 0;\r\n *\r\n *\r\n * while(serial.bytesAvailable > 0)\r\n * {\r\n *   uint8_t byte = serial.getNextByte();\r\n *   if (mavlink_frame_char(chan, byte, &msg) != MAVLINK_FRAMING_INCOMPLETE)\r\n *     {\r\n *     printf(\"Received message with ID %d, sequence: %d from component %d of system %d\", msg.msgid, msg.seq, msg.compid, msg.sysid);\r\n *     }\r\n * }\r\n *\r\n *\r\n * @endcode\r\n */\r\nMAVLINK_HELPER uint8_t mavlink_frame_char(uint8_t chan, uint8_t c, mavlink_message_t* r_message, mavlink_status_t* r_mavlink_status)\r\n{\r\n\treturn mavlink_frame_char_buffer(mavlink_get_channel_buffer(chan),\r\n\t\t\t\t\t mavlink_get_channel_status(chan),\r\n\t\t\t\t\t c,\r\n\t\t\t\t\t r_message,\r\n\t\t\t\t\t r_mavlink_status);\r\n}\r\n\r\n\r\n/**\r\n * This is a convenience function which handles the complete MAVLink parsing.\r\n * the function will parse one byte at a time and return the complete packet once\r\n * it could be successfully decoded. This function will return 0 or 1.\r\n *\r\n * Messages are parsed into an internal buffer (one for each channel). When a complete\r\n * message is received it is copies into *returnMsg and the channel's status is\r\n * copied into *returnStats.\r\n *\r\n * @param chan     ID of the current channel. This allows to parse different channels with this function.\r\n *                 a channel is not a physical message channel like a serial port, but a logic partition of\r\n *                 the communication streams in this case. COMM_NB is the limit for the number of channels\r\n *                 on MCU (e.g. ARM7), while COMM_NB_HIGH is the limit for the number of channels in Linux/Windows\r\n * @param c        The char to parse\r\n *\r\n * @param returnMsg NULL if no message could be decoded, the message data else\r\n * @param returnStats if a message was decoded, this is filled with the channel's stats\r\n * @return 0 if no message could be decoded or bad CRC, 1 on good message and CRC\r\n *\r\n * A typical use scenario of this function call is:\r\n *\r\n * @code\r\n * #include <mavlink.h>\r\n *\r\n * mavlink_message_t msg;\r\n * int chan = 0;\r\n *\r\n *\r\n * while(serial.bytesAvailable > 0)\r\n * {\r\n *   uint8_t byte = serial.getNextByte();\r\n *   if (mavlink_parse_char(chan, byte, &msg))\r\n *     {\r\n *     printf(\"Received message with ID %d, sequence: %d from component %d of system %d\", msg.msgid, msg.seq, msg.compid, msg.sysid);\r\n *     }\r\n * }\r\n *\r\n *\r\n * @endcode\r\n */\r\nMAVLINK_HELPER uint8_t mavlink_parse_char(uint8_t chan, uint8_t c, mavlink_message_t* r_message, mavlink_status_t* r_mavlink_status)\r\n{\r\n    uint8_t msg_received = mavlink_frame_char(chan, c, r_message, r_mavlink_status);\r\n    if (msg_received == MAVLINK_FRAMING_BAD_CRC) {\r\n\t    // we got a bad CRC. Treat as a parse failure\r\n\t    mavlink_message_t* rxmsg = mavlink_get_channel_buffer(chan);\r\n\t    mavlink_status_t* status = mavlink_get_channel_status(chan);\r\n\t    status->parse_error++;\r\n\t    status->msg_received = MAVLINK_FRAMING_INCOMPLETE;\r\n\t    status->parse_state = MAVLINK_PARSE_STATE_IDLE;\r\n\t    if (c == MAVLINK_STX)\r\n\t    {\r\n\t\t    status->parse_state = MAVLINK_PARSE_STATE_GOT_STX;\r\n\t\t    rxmsg->len = 0;\r\n\t\t    mavlink_start_checksum(rxmsg);\r\n\t    }\r\n\t    return 0;\r\n    }\r\n    return msg_received;\r\n}\r\n\r\n/**\r\n * @brief Put a bitfield of length 1-32 bit into the buffer\r\n *\r\n * @param b the value to add, will be encoded in the bitfield\r\n * @param bits number of bits to use to encode b, e.g. 1 for boolean, 2, 3, etc.\r\n * @param packet_index the position in the packet (the index of the first byte to use)\r\n * @param bit_index the position in the byte (the index of the first bit to use)\r\n * @param buffer packet buffer to write into\r\n * @return new position of the last used byte in the buffer\r\n */\r\nMAVLINK_HELPER uint8_t put_bitfield_n_by_index(int32_t b, uint8_t bits, uint8_t packet_index, uint8_t bit_index, uint8_t* r_bit_index, uint8_t* buffer)\r\n{\r\n\tuint16_t bits_remain = bits;\r\n\t// Transform number into network order\r\n\tint32_t v;\r\n\tuint8_t i_bit_index, i_byte_index, curr_bits_n;\r\n#if MAVLINK_NEED_BYTE_SWAP\r\n\tunion {\r\n\t\tint32_t i;\r\n\t\tuint8_t b[4];\r\n\t} bin, bout;\r\n\tbin.i = b;\r\n\tbout.b[0] = bin.b[3];\r\n\tbout.b[1] = bin.b[2];\r\n\tbout.b[2] = bin.b[1];\r\n\tbout.b[3] = bin.b[0];\r\n\tv = bout.i;\r\n#else\r\n\tv = b;\r\n#endif\r\n\r\n\t// buffer in\r\n\t// 01100000 01000000 00000000 11110001\r\n\t// buffer out\r\n\t// 11110001 00000000 01000000 01100000\r\n\r\n\t// Existing partly filled byte (four free slots)\r\n\t// 0111xxxx\r\n\r\n\t// Mask n free bits\r\n\t// 00001111 = 2^0 + 2^1 + 2^2 + 2^3 = 2^n - 1\r\n\t// = ((uint32_t)(1 << n)) - 1; // = 2^n - 1\r\n\r\n\t// Shift n bits into the right position\r\n\t// out = in >> n;\r\n\r\n\t// Mask and shift bytes\r\n\ti_bit_index = bit_index;\r\n\ti_byte_index = packet_index;\r\n\tif (bit_index > 0)\r\n\t{\r\n\t\t// If bits were available at start, they were available\r\n\t\t// in the byte before the current index\r\n\t\ti_byte_index--;\r\n\t}\r\n\r\n\t// While bits have not been packed yet\r\n\twhile (bits_remain > 0)\r\n\t{\r\n\t\t// Bits still have to be packed\r\n\t\t// there can be more than 8 bits, so\r\n\t\t// we might have to pack them into more than one byte\r\n\r\n\t\t// First pack everything we can into the current 'open' byte\r\n\t\t//curr_bits_n = bits_remain << 3; // Equals  bits_remain mod 8\r\n\t\t//FIXME\r\n\t\tif (bits_remain <= (uint8_t)(8 - i_bit_index))\r\n\t\t{\r\n\t\t\t// Enough space\r\n\t\t\tcurr_bits_n = (uint8_t)bits_remain;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tcurr_bits_n = (8 - i_bit_index);\r\n\t\t}\r\n\t\t\r\n\t\t// Pack these n bits into the current byte\r\n\t\t// Mask out whatever was at that position with ones (xxx11111)\r\n\t\tbuffer[i_byte_index] &= (0xFF >> (8 - curr_bits_n));\r\n\t\t// Put content to this position, by masking out the non-used part\r\n\t\tbuffer[i_byte_index] |= ((0x00 << curr_bits_n) & v);\r\n\t\t\r\n\t\t// Increment the bit index\r\n\t\ti_bit_index += curr_bits_n;\r\n\r\n\t\t// Now proceed to the next byte, if necessary\r\n\t\tbits_remain -= curr_bits_n;\r\n\t\tif (bits_remain > 0)\r\n\t\t{\r\n\t\t\t// Offer another 8 bits / one byte\r\n\t\t\ti_byte_index++;\r\n\t\t\ti_bit_index = 0;\r\n\t\t}\r\n\t}\r\n\t\r\n\t*r_bit_index = i_bit_index;\r\n\t// If a partly filled byte is present, mark this as consumed\r\n\tif (i_bit_index != 7) i_byte_index++;\r\n\treturn i_byte_index - packet_index;\r\n}\r\n\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\n// To make MAVLink work on your MCU, define comm_send_ch() if you wish\r\n// to send 1 byte at a time, or MAVLINK_SEND_UART_BYTES() to send a\r\n// whole packet at a time\r\n\r\n/*\r\n\r\n#include \"mavlink_types.h\"\r\n\r\nvoid comm_send_ch(mavlink_channel_t chan, uint8_t ch)\r\n{\r\n    if (chan == MAVLINK_COMM_0)\r\n    {\r\n        uart0_transmit(ch);\r\n    }\r\n    if (chan == MAVLINK_COMM_1)\r\n    {\r\n    \tuart1_transmit(ch);\r\n    }\r\n}\r\n */\r\n\r\nMAVLINK_HELPER void _mavlink_send_uart(mavlink_channel_t chan, const char *buf, uint16_t len)\r\n{\r\n#ifdef MAVLINK_SEND_UART_BYTES\r\n\t/* this is the more efficient approach, if the platform\r\n\t   defines it */\r\n\tMAVLINK_SEND_UART_BYTES(chan, (const uint8_t *)buf, len);\r\n#else\r\n\t/* fallback to one byte at a time */\r\n\tuint16_t i;\r\n\tfor (i = 0; i < len; i++) {\r\n\t\tcomm_send_ch(chan, (uint8_t)buf[i]);\r\n\t}\r\n#endif\r\n}\r\n#endif // MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\n#endif /* _MAVLINK_HELPERS_H_ */\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld/msg/mavlink/mavlink_types.h",
    "content": "#ifndef MAVLINK_TYPES_H_\r\n#define MAVLINK_TYPES_H_\r\n\r\n// Visual Studio versions before 2010 don't have stdint.h, so we just error out.\r\n#if (defined _MSC_VER) && (_MSC_VER < 1600)\r\n#error \"The C-MAVLink implementation requires Visual Studio 2010 or greater\"\r\n#endif\r\n\r\n#include <stdint.h>\r\n\r\n// Macro to define packed structures\r\n#ifdef __GNUC__\r\n  #define MAVPACKED( __Declaration__ ) __Declaration__ __attribute__((packed))\r\n#else\r\n  #define MAVPACKED( __Declaration__ ) __pragma( pack(push, 1) ) __Declaration__ __pragma( pack(pop) )\r\n#endif\r\n\r\n#ifndef MAVLINK_MAX_PAYLOAD_LEN\r\n// it is possible to override this, but be careful!\r\n#define MAVLINK_MAX_PAYLOAD_LEN 255 ///< Maximum payload length\r\n#endif\r\n\r\n#define MAVLINK_CORE_HEADER_LEN 5 ///< Length of core header (of the comm. layer): message length (1 byte) + message sequence (1 byte) + message system id (1 byte) + message component id (1 byte) + message type id (1 byte)\r\n#define MAVLINK_NUM_HEADER_BYTES (MAVLINK_CORE_HEADER_LEN + 1) ///< Length of all header bytes, including core and checksum\r\n#define MAVLINK_NUM_CHECKSUM_BYTES 2\r\n#define MAVLINK_NUM_NON_PAYLOAD_BYTES (MAVLINK_NUM_HEADER_BYTES + MAVLINK_NUM_CHECKSUM_BYTES)\r\n\r\n#define MAVLINK_MAX_PACKET_LEN (MAVLINK_MAX_PAYLOAD_LEN + MAVLINK_NUM_NON_PAYLOAD_BYTES) ///< Maximum packet length\r\n\r\n#define MAVLINK_MSG_ID_EXTENDED_MESSAGE 255\r\n#define MAVLINK_EXTENDED_HEADER_LEN 14\r\n\r\n#if (defined _MSC_VER) || ((defined __APPLE__) && (defined __MACH__)) || (defined __linux__)\r\n  /* full fledged 32bit++ OS */\r\n  #define MAVLINK_MAX_EXTENDED_PACKET_LEN 65507\r\n#else\r\n  /* small microcontrollers */\r\n  #define MAVLINK_MAX_EXTENDED_PACKET_LEN 2048\r\n#endif\r\n\r\n#define MAVLINK_MAX_EXTENDED_PAYLOAD_LEN (MAVLINK_MAX_EXTENDED_PACKET_LEN - MAVLINK_EXTENDED_HEADER_LEN - MAVLINK_NUM_NON_PAYLOAD_BYTES)\r\n\r\n\r\n/**\r\n * Old-style 4 byte param union\r\n *\r\n * This struct is the data format to be used when sending\r\n * parameters. The parameter should be copied to the native\r\n * type (without type conversion)\r\n * and re-instanted on the receiving side using the\r\n * native type as well.\r\n */\r\nMAVPACKED(\r\ntypedef struct param_union {\r\n\tunion {\r\n\t\tfloat param_float;\r\n\t\tint32_t param_int32;\r\n\t\tuint32_t param_uint32;\r\n\t\tint16_t param_int16;\r\n\t\tuint16_t param_uint16;\r\n\t\tint8_t param_int8;\r\n\t\tuint8_t param_uint8;\r\n\t\tuint8_t bytes[4];\r\n\t};\r\n\tuint8_t type;\r\n}) mavlink_param_union_t;\r\n\r\n\r\n/**\r\n * New-style 8 byte param union\r\n * mavlink_param_union_double_t will be 8 bytes long, and treated as needing 8 byte alignment for the purposes of MAVLink 1.0 field ordering.\r\n * The mavlink_param_union_double_t will be treated as a little-endian structure.\r\n *\r\n * If is_double is 1 then the type is a double, and the remaining 63 bits are the double, with the lowest bit of the mantissa zero.\r\n * The intention is that by replacing the is_double bit with 0 the type can be directly used as a double (as the is_double bit corresponds to the\r\n * lowest mantissa bit of a double). If is_double is 0 then mavlink_type gives the type in the union.\r\n * The mavlink_types.h header will also need to have shifts/masks to define the bit boundaries in the above,\r\n * as bitfield ordering isn’t consistent between platforms. The above is intended to be for gcc on x86,\r\n * which should be the same as gcc on little-endian arm. When using shifts/masks the value will be treated as a 64 bit unsigned number,\r\n * and the bits pulled out using the shifts/masks.\r\n*/\r\nMAVPACKED(\r\ntypedef struct param_union_extended {\r\n    union {\r\n    struct {\r\n        uint8_t is_double:1;\r\n        uint8_t mavlink_type:7;\r\n        union {\r\n            char c;\r\n            uint8_t uint8;\r\n            int8_t int8;\r\n            uint16_t uint16;\r\n            int16_t int16;\r\n            uint32_t uint32;\r\n            int32_t int32;\r\n            float f;\r\n            uint8_t align[7];\r\n        };\r\n    };\r\n    uint8_t data[8];\r\n    };\r\n}) mavlink_param_union_double_t;\r\n\r\n/**\r\n * This structure is required to make the mavlink_send_xxx convenience functions\r\n * work, as it tells the library what the current system and component ID are.\r\n */\r\nMAVPACKED(\r\ntypedef struct __mavlink_system {\r\n    uint8_t sysid;   ///< Used by the MAVLink message_xx_send() convenience function\r\n    uint8_t compid;  ///< Used by the MAVLink message_xx_send() convenience function\r\n}) mavlink_system_t;\r\n\r\nMAVPACKED(\r\ntypedef struct __mavlink_message {\r\n\tuint16_t checksum; ///< sent at end of packet\r\n\tuint8_t magic;   ///< protocol magic marker\r\n\tuint8_t len;     ///< Length of payload\r\n\tuint8_t seq;     ///< Sequence of packet\r\n\tuint8_t sysid;   ///< ID of message sender system/aircraft\r\n\tuint8_t compid;  ///< ID of the message sender component\r\n\tuint8_t msgid;   ///< ID of message in payload\r\n\tuint64_t payload64[(MAVLINK_MAX_PAYLOAD_LEN+MAVLINK_NUM_CHECKSUM_BYTES+7)/8];\r\n}) mavlink_message_t;\r\n\r\nMAVPACKED(\r\ntypedef struct __mavlink_extended_message {\r\n       mavlink_message_t base_msg;\r\n       int32_t extended_payload_len;   ///< Length of extended payload if any\r\n       uint8_t extended_payload[MAVLINK_MAX_EXTENDED_PAYLOAD_LEN];\r\n}) mavlink_extended_message_t;\r\n\r\ntypedef enum {\r\n\tMAVLINK_TYPE_CHAR     = 0,\r\n\tMAVLINK_TYPE_UINT8_T  = 1,\r\n\tMAVLINK_TYPE_INT8_T   = 2,\r\n\tMAVLINK_TYPE_UINT16_T = 3,\r\n\tMAVLINK_TYPE_INT16_T  = 4,\r\n\tMAVLINK_TYPE_UINT32_T = 5,\r\n\tMAVLINK_TYPE_INT32_T  = 6,\r\n\tMAVLINK_TYPE_UINT64_T = 7,\r\n\tMAVLINK_TYPE_INT64_T  = 8,\r\n\tMAVLINK_TYPE_FLOAT    = 9,\r\n\tMAVLINK_TYPE_DOUBLE   = 10\r\n} mavlink_message_type_t;\r\n\r\n#define MAVLINK_MAX_FIELDS 64\r\n\r\ntypedef struct __mavlink_field_info {\r\n        const char *name;                 // name of this field\r\n        const char *print_format;         // printing format hint, or NULL\r\n        mavlink_message_type_t type;      // type of this field\r\n        unsigned int array_length;        // if non-zero, field is an array\r\n        unsigned int wire_offset;         // offset of each field in the payload\r\n        unsigned int structure_offset;    // offset in a C structure\r\n} mavlink_field_info_t;\r\n\r\n// note that in this structure the order of fields is the order\r\n// in the XML file, not necessary the wire order\r\ntypedef struct __mavlink_message_info {\r\n\tconst char *name;                                      // name of the message\r\n\tunsigned num_fields;                                   // how many fields in this message\r\n\tmavlink_field_info_t fields[MAVLINK_MAX_FIELDS];       // field information\r\n} mavlink_message_info_t;\r\n\r\n#define _MAV_PAYLOAD(msg) ((const char *)(&((msg)->payload64[0])))\r\n#define _MAV_PAYLOAD_NON_CONST(msg) ((char *)(&((msg)->payload64[0])))\r\n\r\n// checksum is immediately after the payload bytes\r\n#define mavlink_ck_a(msg) *((msg)->len + (uint8_t *)_MAV_PAYLOAD_NON_CONST(msg))\r\n#define mavlink_ck_b(msg) *(((msg)->len+(uint16_t)1) + (uint8_t *)_MAV_PAYLOAD_NON_CONST(msg))\r\n\r\ntypedef enum {\r\n    MAVLINK_COMM_0,\r\n    MAVLINK_COMM_1,\r\n    MAVLINK_COMM_2,\r\n    MAVLINK_COMM_3\r\n} mavlink_channel_t;\r\n\r\n/*\r\n * applications can set MAVLINK_COMM_NUM_BUFFERS to the maximum number\r\n * of buffers they will use. If more are used, then the result will be\r\n * a stack overrun\r\n */\r\n#ifndef MAVLINK_COMM_NUM_BUFFERS\r\n#if (defined linux) | (defined __linux) | (defined  __MACH__) | (defined _WIN32)\r\n# define MAVLINK_COMM_NUM_BUFFERS 16\r\n#else\r\n# define MAVLINK_COMM_NUM_BUFFERS 4\r\n#endif\r\n#endif\r\n\r\ntypedef enum {\r\n    MAVLINK_PARSE_STATE_UNINIT=0,\r\n    MAVLINK_PARSE_STATE_IDLE,\r\n    MAVLINK_PARSE_STATE_GOT_STX,\r\n    MAVLINK_PARSE_STATE_GOT_SEQ,\r\n    MAVLINK_PARSE_STATE_GOT_LENGTH,\r\n    MAVLINK_PARSE_STATE_GOT_SYSID,\r\n    MAVLINK_PARSE_STATE_GOT_COMPID,\r\n    MAVLINK_PARSE_STATE_GOT_MSGID,\r\n    MAVLINK_PARSE_STATE_GOT_PAYLOAD,\r\n    MAVLINK_PARSE_STATE_GOT_CRC1,\r\n    MAVLINK_PARSE_STATE_GOT_BAD_CRC1\r\n} mavlink_parse_state_t; ///< The state machine for the comm parser\r\n\r\ntypedef enum {\r\n    MAVLINK_FRAMING_INCOMPLETE=0,\r\n    MAVLINK_FRAMING_OK=1,\r\n    MAVLINK_FRAMING_BAD_CRC=2\r\n} mavlink_framing_t;\r\n\r\ntypedef struct __mavlink_status {\r\n    uint8_t msg_received;               ///< Number of received messages\r\n    uint8_t buffer_overrun;             ///< Number of buffer overruns\r\n    uint8_t parse_error;                ///< Number of parse errors\r\n    mavlink_parse_state_t parse_state;  ///< Parsing state machine\r\n    uint8_t packet_idx;                 ///< Index in current packet\r\n    uint8_t current_rx_seq;             ///< Sequence number of last packet received\r\n    uint8_t current_tx_seq;             ///< Sequence number of last packet sent\r\n    uint16_t packet_rx_success_count;   ///< Received packets\r\n    uint16_t packet_rx_drop_count;      ///< Number of packet drops\r\n} mavlink_status_t;\r\n\r\n#define MAVLINK_BIG_ENDIAN 0\r\n#define MAVLINK_LITTLE_ENDIAN 1\r\n\r\n#endif /* MAVLINK_TYPES_H_ */\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld/msg/mavlink/opencr_msg/mavlink.h",
    "content": "/** @file\r\n *\t@brief MAVLink comm protocol built from opencr_msg.xml\r\n *\t@see http://mavlink.org\r\n */\r\n#ifndef MAVLINK_H\r\n#define MAVLINK_H\r\n\r\n#ifndef MAVLINK_STX\r\n#define MAVLINK_STX 254\r\n#endif\r\n\r\n#ifndef MAVLINK_ENDIAN\r\n#define MAVLINK_ENDIAN MAVLINK_LITTLE_ENDIAN\r\n#endif\r\n\r\n#ifndef MAVLINK_ALIGNED_FIELDS\r\n#define MAVLINK_ALIGNED_FIELDS 1\r\n#endif\r\n\r\n#ifndef MAVLINK_CRC_EXTRA\r\n#define MAVLINK_CRC_EXTRA 1\r\n#endif\r\n\r\n#ifndef MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_COMMAND_24BIT 0\r\n#endif\r\n\r\n#ifndef MAVLINK_PACKED\r\n#define MAVLINK_PACKED __attribute__((__packed__))\r\n#endif\r\n\r\n#include \"version.h\"\r\n#include \"opencr_msg.h\"\r\n\r\n#endif // MAVLINK_H\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld/msg/mavlink/opencr_msg/mavlink_msg_ack.h",
    "content": "// MESSAGE ACK PACKING\r\n\r\n#define MAVLINK_MSG_ID_ACK 150\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_ack_t\r\n{\r\n uint16_t err_code; /*< */\r\n uint8_t msg_id; /*< */\r\n uint8_t length; /*< */\r\n uint8_t data[16]; /*< */\r\n} mavlink_ack_t;\r\n\r\n#define MAVLINK_MSG_ID_ACK_LEN 20\r\n#define MAVLINK_MSG_ID_ACK_MIN_LEN 20\r\n#define MAVLINK_MSG_ID_150_LEN 20\r\n#define MAVLINK_MSG_ID_150_MIN_LEN 20\r\n\r\n#define MAVLINK_MSG_ID_ACK_CRC 192\r\n#define MAVLINK_MSG_ID_150_CRC 192\r\n\r\n#define MAVLINK_MSG_ACK_FIELD_DATA_LEN 16\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_ACK { \\\r\n\t150, \\\r\n\t\"ACK\", \\\r\n\t4, \\\r\n\t{  { \"err_code\", NULL, MAVLINK_TYPE_UINT16_T, 0, 0, offsetof(mavlink_ack_t, err_code) }, \\\r\n         { \"msg_id\", NULL, MAVLINK_TYPE_UINT8_T, 0, 2, offsetof(mavlink_ack_t, msg_id) }, \\\r\n         { \"length\", NULL, MAVLINK_TYPE_UINT8_T, 0, 3, offsetof(mavlink_ack_t, length) }, \\\r\n         { \"data\", NULL, MAVLINK_TYPE_UINT8_T, 16, 4, offsetof(mavlink_ack_t, data) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_ACK { \\\r\n\t\"ACK\", \\\r\n\t4, \\\r\n\t{  { \"err_code\", NULL, MAVLINK_TYPE_UINT16_T, 0, 0, offsetof(mavlink_ack_t, err_code) }, \\\r\n         { \"msg_id\", NULL, MAVLINK_TYPE_UINT8_T, 0, 2, offsetof(mavlink_ack_t, msg_id) }, \\\r\n         { \"length\", NULL, MAVLINK_TYPE_UINT8_T, 0, 3, offsetof(mavlink_ack_t, length) }, \\\r\n         { \"data\", NULL, MAVLINK_TYPE_UINT8_T, 16, 4, offsetof(mavlink_ack_t, data) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a ack message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param msg_id \r\n * @param err_code \r\n * @param length \r\n * @param data \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_ack_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t msg_id, uint16_t err_code, uint8_t length, const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_ACK_LEN];\r\n\t_mav_put_uint16_t(buf, 0, err_code);\r\n\t_mav_put_uint8_t(buf, 2, msg_id);\r\n\t_mav_put_uint8_t(buf, 3, length);\r\n\t_mav_put_uint8_t_array(buf, 4, data, 16);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_ACK_LEN);\r\n#else\r\n\tmavlink_ack_t packet;\r\n\tpacket.err_code = err_code;\r\n\tpacket.msg_id = msg_id;\r\n\tpacket.length = length;\r\n\tmav_array_memcpy(packet.data, data, sizeof(uint8_t)*16);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_ACK_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_ACK;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_ACK_MIN_LEN, MAVLINK_MSG_ID_ACK_LEN, MAVLINK_MSG_ID_ACK_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a ack message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param msg_id \r\n * @param err_code \r\n * @param length \r\n * @param data \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_ack_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t msg_id,uint16_t err_code,uint8_t length,const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_ACK_LEN];\r\n\t_mav_put_uint16_t(buf, 0, err_code);\r\n\t_mav_put_uint8_t(buf, 2, msg_id);\r\n\t_mav_put_uint8_t(buf, 3, length);\r\n\t_mav_put_uint8_t_array(buf, 4, data, 16);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_ACK_LEN);\r\n#else\r\n\tmavlink_ack_t packet;\r\n\tpacket.err_code = err_code;\r\n\tpacket.msg_id = msg_id;\r\n\tpacket.length = length;\r\n\tmav_array_memcpy(packet.data, data, sizeof(uint8_t)*16);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_ACK_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_ACK;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_ACK_MIN_LEN, MAVLINK_MSG_ID_ACK_LEN, MAVLINK_MSG_ID_ACK_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a ack struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param ack C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_ack_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_ack_t* ack)\r\n{\r\n\treturn mavlink_msg_ack_pack(system_id, component_id, msg, ack->msg_id, ack->err_code, ack->length, ack->data);\r\n}\r\n\r\n/**\r\n * @brief Encode a ack struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param ack C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_ack_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_ack_t* ack)\r\n{\r\n\treturn mavlink_msg_ack_pack_chan(system_id, component_id, chan, msg, ack->msg_id, ack->err_code, ack->length, ack->data);\r\n}\r\n\r\n/**\r\n * @brief Send a ack message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param msg_id \r\n * @param err_code \r\n * @param length \r\n * @param data \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_ack_send(mavlink_channel_t chan, uint8_t msg_id, uint16_t err_code, uint8_t length, const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_ACK_LEN];\r\n\t_mav_put_uint16_t(buf, 0, err_code);\r\n\t_mav_put_uint8_t(buf, 2, msg_id);\r\n\t_mav_put_uint8_t(buf, 3, length);\r\n\t_mav_put_uint8_t_array(buf, 4, data, 16);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_ACK, buf, MAVLINK_MSG_ID_ACK_MIN_LEN, MAVLINK_MSG_ID_ACK_LEN, MAVLINK_MSG_ID_ACK_CRC);\r\n#else\r\n\tmavlink_ack_t packet;\r\n\tpacket.err_code = err_code;\r\n\tpacket.msg_id = msg_id;\r\n\tpacket.length = length;\r\n\tmav_array_memcpy(packet.data, data, sizeof(uint8_t)*16);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_ACK, (const char *)&packet, MAVLINK_MSG_ID_ACK_MIN_LEN, MAVLINK_MSG_ID_ACK_LEN, MAVLINK_MSG_ID_ACK_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a ack message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_ack_send_struct(mavlink_channel_t chan, const mavlink_ack_t* ack)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_ack_send(chan, ack->msg_id, ack->err_code, ack->length, ack->data);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_ACK, (const char *)ack, MAVLINK_MSG_ID_ACK_MIN_LEN, MAVLINK_MSG_ID_ACK_LEN, MAVLINK_MSG_ID_ACK_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_ACK_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_ack_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t msg_id, uint16_t err_code, uint8_t length, const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint16_t(buf, 0, err_code);\r\n\t_mav_put_uint8_t(buf, 2, msg_id);\r\n\t_mav_put_uint8_t(buf, 3, length);\r\n\t_mav_put_uint8_t_array(buf, 4, data, 16);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_ACK, buf, MAVLINK_MSG_ID_ACK_MIN_LEN, MAVLINK_MSG_ID_ACK_LEN, MAVLINK_MSG_ID_ACK_CRC);\r\n#else\r\n\tmavlink_ack_t *packet = (mavlink_ack_t *)msgbuf;\r\n\tpacket->err_code = err_code;\r\n\tpacket->msg_id = msg_id;\r\n\tpacket->length = length;\r\n\tmav_array_memcpy(packet->data, data, sizeof(uint8_t)*16);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_ACK, (const char *)packet, MAVLINK_MSG_ID_ACK_MIN_LEN, MAVLINK_MSG_ID_ACK_LEN, MAVLINK_MSG_ID_ACK_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE ACK UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field msg_id from ack message\r\n *\r\n * @return \r\n */\r\nstatic inline uint8_t mavlink_msg_ack_get_msg_id(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  2);\r\n}\r\n\r\n/**\r\n * @brief Get field err_code from ack message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_ack_get_err_code(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint16_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field length from ack message\r\n *\r\n * @return \r\n */\r\nstatic inline uint8_t mavlink_msg_ack_get_length(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  3);\r\n}\r\n\r\n/**\r\n * @brief Get field data from ack message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_ack_get_data(const mavlink_message_t* msg, uint8_t *data)\r\n{\r\n\treturn _MAV_RETURN_uint8_t_array(msg, data, 16,  4);\r\n}\r\n\r\n/**\r\n * @brief Decode a ack message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param ack C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_ack_decode(const mavlink_message_t* msg, mavlink_ack_t* ack)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tack->err_code = mavlink_msg_ack_get_err_code(msg);\r\n\tack->msg_id = mavlink_msg_ack_get_msg_id(msg);\r\n\tack->length = mavlink_msg_ack_get_length(msg);\r\n\tmavlink_msg_ack_get_data(msg, ack->data);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_ACK_LEN? msg->len : MAVLINK_MSG_ID_ACK_LEN;\r\n        memset(ack, 0, MAVLINK_MSG_ID_ACK_LEN);\r\n\tmemcpy(ack, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld/msg/mavlink/opencr_msg/mavlink_msg_flash_fw_erase.h",
    "content": "// MESSAGE FLASH_FW_ERASE PACKING\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_ERASE 158\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_flash_fw_erase_t\r\n{\r\n uint32_t length; /*< */\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n uint8_t param[8]; /*< */\r\n} mavlink_flash_fw_erase_t;\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN 13\r\n#define MAVLINK_MSG_ID_FLASH_FW_ERASE_MIN_LEN 13\r\n#define MAVLINK_MSG_ID_158_LEN 13\r\n#define MAVLINK_MSG_ID_158_MIN_LEN 13\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_ERASE_CRC 13\r\n#define MAVLINK_MSG_ID_158_CRC 13\r\n\r\n#define MAVLINK_MSG_FLASH_FW_ERASE_FIELD_PARAM_LEN 8\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_ERASE { \\\r\n\t158, \\\r\n\t\"FLASH_FW_ERASE\", \\\r\n\t3, \\\r\n\t{  { \"length\", NULL, MAVLINK_TYPE_UINT32_T, 0, 0, offsetof(mavlink_flash_fw_erase_t, length) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 4, offsetof(mavlink_flash_fw_erase_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 5, offsetof(mavlink_flash_fw_erase_t, param) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_ERASE { \\\r\n\t\"FLASH_FW_ERASE\", \\\r\n\t3, \\\r\n\t{  { \"length\", NULL, MAVLINK_TYPE_UINT32_T, 0, 0, offsetof(mavlink_flash_fw_erase_t, length) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 4, offsetof(mavlink_flash_fw_erase_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 5, offsetof(mavlink_flash_fw_erase_t, param) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a flash_fw_erase message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param length \r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_erase_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, uint32_t length, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN];\r\n\t_mav_put_uint32_t(buf, 0, length);\r\n\t_mav_put_uint8_t(buf, 4, resp);\r\n\t_mav_put_uint8_t_array(buf, 5, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN);\r\n#else\r\n\tmavlink_flash_fw_erase_t packet;\r\n\tpacket.length = length;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_ERASE;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_FLASH_FW_ERASE_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a flash_fw_erase message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param length \r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_erase_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,uint32_t length,const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN];\r\n\t_mav_put_uint32_t(buf, 0, length);\r\n\t_mav_put_uint8_t(buf, 4, resp);\r\n\t_mav_put_uint8_t_array(buf, 5, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN);\r\n#else\r\n\tmavlink_flash_fw_erase_t packet;\r\n\tpacket.length = length;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_ERASE;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_FLASH_FW_ERASE_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_erase struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_erase C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_erase_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_flash_fw_erase_t* flash_fw_erase)\r\n{\r\n\treturn mavlink_msg_flash_fw_erase_pack(system_id, component_id, msg, flash_fw_erase->resp, flash_fw_erase->length, flash_fw_erase->param);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_erase struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_erase C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_erase_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_flash_fw_erase_t* flash_fw_erase)\r\n{\r\n\treturn mavlink_msg_flash_fw_erase_pack_chan(system_id, component_id, chan, msg, flash_fw_erase->resp, flash_fw_erase->length, flash_fw_erase->param);\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_erase message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param length \r\n * @param param \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_flash_fw_erase_send(mavlink_channel_t chan, uint8_t resp, uint32_t length, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN];\r\n\t_mav_put_uint32_t(buf, 0, length);\r\n\t_mav_put_uint8_t(buf, 4, resp);\r\n\t_mav_put_uint8_t_array(buf, 5, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_ERASE, buf, MAVLINK_MSG_ID_FLASH_FW_ERASE_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_CRC);\r\n#else\r\n\tmavlink_flash_fw_erase_t packet;\r\n\tpacket.length = length;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_ERASE, (const char *)&packet, MAVLINK_MSG_ID_FLASH_FW_ERASE_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_erase message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_flash_fw_erase_send_struct(mavlink_channel_t chan, const mavlink_flash_fw_erase_t* flash_fw_erase)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_flash_fw_erase_send(chan, flash_fw_erase->resp, flash_fw_erase->length, flash_fw_erase->param);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_ERASE, (const char *)flash_fw_erase, MAVLINK_MSG_ID_FLASH_FW_ERASE_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_flash_fw_erase_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, uint32_t length, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint32_t(buf, 0, length);\r\n\t_mav_put_uint8_t(buf, 4, resp);\r\n\t_mav_put_uint8_t_array(buf, 5, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_ERASE, buf, MAVLINK_MSG_ID_FLASH_FW_ERASE_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_CRC);\r\n#else\r\n\tmavlink_flash_fw_erase_t *packet = (mavlink_flash_fw_erase_t *)msgbuf;\r\n\tpacket->length = length;\r\n\tpacket->resp = resp;\r\n\tmav_array_memcpy(packet->param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_ERASE, (const char *)packet, MAVLINK_MSG_ID_FLASH_FW_ERASE_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE FLASH_FW_ERASE UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from flash_fw_erase message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_flash_fw_erase_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  4);\r\n}\r\n\r\n/**\r\n * @brief Get field length from flash_fw_erase message\r\n *\r\n * @return \r\n */\r\nstatic inline uint32_t mavlink_msg_flash_fw_erase_get_length(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint32_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field param from flash_fw_erase message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_erase_get_param(const mavlink_message_t* msg, uint8_t *param)\r\n{\r\n\treturn _MAV_RETURN_uint8_t_array(msg, param, 8,  5);\r\n}\r\n\r\n/**\r\n * @brief Decode a flash_fw_erase message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param flash_fw_erase C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_flash_fw_erase_decode(const mavlink_message_t* msg, mavlink_flash_fw_erase_t* flash_fw_erase)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tflash_fw_erase->length = mavlink_msg_flash_fw_erase_get_length(msg);\r\n\tflash_fw_erase->resp = mavlink_msg_flash_fw_erase_get_resp(msg);\r\n\tmavlink_msg_flash_fw_erase_get_param(msg, flash_fw_erase->param);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN? msg->len : MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN;\r\n        memset(flash_fw_erase, 0, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN);\r\n\tmemcpy(flash_fw_erase, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld/msg/mavlink/opencr_msg/mavlink_msg_flash_fw_read_block.h",
    "content": "// MESSAGE FLASH_FW_READ_BLOCK PACKING\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK 161\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_flash_fw_read_block_t\r\n{\r\n uint32_t addr; /*< */\r\n uint16_t length; /*< */\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n} mavlink_flash_fw_read_block_t;\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN 7\r\n#define MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_MIN_LEN 7\r\n#define MAVLINK_MSG_ID_161_LEN 7\r\n#define MAVLINK_MSG_ID_161_MIN_LEN 7\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_CRC 131\r\n#define MAVLINK_MSG_ID_161_CRC 131\r\n\r\n\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_READ_BLOCK { \\\r\n\t161, \\\r\n\t\"FLASH_FW_READ_BLOCK\", \\\r\n\t3, \\\r\n\t{  { \"addr\", NULL, MAVLINK_TYPE_UINT32_T, 0, 0, offsetof(mavlink_flash_fw_read_block_t, addr) }, \\\r\n         { \"length\", NULL, MAVLINK_TYPE_UINT16_T, 0, 4, offsetof(mavlink_flash_fw_read_block_t, length) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 6, offsetof(mavlink_flash_fw_read_block_t, resp) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_READ_BLOCK { \\\r\n\t\"FLASH_FW_READ_BLOCK\", \\\r\n\t3, \\\r\n\t{  { \"addr\", NULL, MAVLINK_TYPE_UINT32_T, 0, 0, offsetof(mavlink_flash_fw_read_block_t, addr) }, \\\r\n         { \"length\", NULL, MAVLINK_TYPE_UINT16_T, 0, 4, offsetof(mavlink_flash_fw_read_block_t, length) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 6, offsetof(mavlink_flash_fw_read_block_t, resp) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a flash_fw_read_block message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_read_block_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, uint32_t addr, uint16_t length)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN];\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint16_t(buf, 4, length);\r\n\t_mav_put_uint8_t(buf, 6, resp);\r\n\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN);\r\n#else\r\n\tmavlink_flash_fw_read_block_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.length = length;\r\n\tpacket.resp = resp;\r\n\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a flash_fw_read_block message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_read_block_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,uint32_t addr,uint16_t length)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN];\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint16_t(buf, 4, length);\r\n\t_mav_put_uint8_t(buf, 6, resp);\r\n\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN);\r\n#else\r\n\tmavlink_flash_fw_read_block_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.length = length;\r\n\tpacket.resp = resp;\r\n\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_read_block struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_read_block C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_read_block_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_flash_fw_read_block_t* flash_fw_read_block)\r\n{\r\n\treturn mavlink_msg_flash_fw_read_block_pack(system_id, component_id, msg, flash_fw_read_block->resp, flash_fw_read_block->addr, flash_fw_read_block->length);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_read_block struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_read_block C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_read_block_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_flash_fw_read_block_t* flash_fw_read_block)\r\n{\r\n\treturn mavlink_msg_flash_fw_read_block_pack_chan(system_id, component_id, chan, msg, flash_fw_read_block->resp, flash_fw_read_block->addr, flash_fw_read_block->length);\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_read_block message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_flash_fw_read_block_send(mavlink_channel_t chan, uint8_t resp, uint32_t addr, uint16_t length)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN];\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint16_t(buf, 4, length);\r\n\t_mav_put_uint8_t(buf, 6, resp);\r\n\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK, buf, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_CRC);\r\n#else\r\n\tmavlink_flash_fw_read_block_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.length = length;\r\n\tpacket.resp = resp;\r\n\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK, (const char *)&packet, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_read_block message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_flash_fw_read_block_send_struct(mavlink_channel_t chan, const mavlink_flash_fw_read_block_t* flash_fw_read_block)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_flash_fw_read_block_send(chan, flash_fw_read_block->resp, flash_fw_read_block->addr, flash_fw_read_block->length);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK, (const char *)flash_fw_read_block, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_flash_fw_read_block_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, uint32_t addr, uint16_t length)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint16_t(buf, 4, length);\r\n\t_mav_put_uint8_t(buf, 6, resp);\r\n\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK, buf, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_CRC);\r\n#else\r\n\tmavlink_flash_fw_read_block_t *packet = (mavlink_flash_fw_read_block_t *)msgbuf;\r\n\tpacket->addr = addr;\r\n\tpacket->length = length;\r\n\tpacket->resp = resp;\r\n\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK, (const char *)packet, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE FLASH_FW_READ_BLOCK UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from flash_fw_read_block message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_flash_fw_read_block_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  6);\r\n}\r\n\r\n/**\r\n * @brief Get field addr from flash_fw_read_block message\r\n *\r\n * @return \r\n */\r\nstatic inline uint32_t mavlink_msg_flash_fw_read_block_get_addr(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint32_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field length from flash_fw_read_block message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_read_block_get_length(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint16_t(msg,  4);\r\n}\r\n\r\n/**\r\n * @brief Decode a flash_fw_read_block message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param flash_fw_read_block C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_flash_fw_read_block_decode(const mavlink_message_t* msg, mavlink_flash_fw_read_block_t* flash_fw_read_block)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tflash_fw_read_block->addr = mavlink_msg_flash_fw_read_block_get_addr(msg);\r\n\tflash_fw_read_block->length = mavlink_msg_flash_fw_read_block_get_length(msg);\r\n\tflash_fw_read_block->resp = mavlink_msg_flash_fw_read_block_get_resp(msg);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN? msg->len : MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN;\r\n        memset(flash_fw_read_block, 0, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN);\r\n\tmemcpy(flash_fw_read_block, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld/msg/mavlink/opencr_msg/mavlink_msg_flash_fw_read_packet.h",
    "content": "// MESSAGE FLASH_FW_READ_PACKET PACKING\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_READ_PACKET 160\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_flash_fw_read_packet_t\r\n{\r\n uint32_t addr; /*< */\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n uint8_t length; /*< */\r\n uint8_t data[128]; /*< */\r\n} mavlink_flash_fw_read_packet_t;\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN 134\r\n#define MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_MIN_LEN 134\r\n#define MAVLINK_MSG_ID_160_LEN 134\r\n#define MAVLINK_MSG_ID_160_MIN_LEN 134\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_CRC 9\r\n#define MAVLINK_MSG_ID_160_CRC 9\r\n\r\n#define MAVLINK_MSG_FLASH_FW_READ_PACKET_FIELD_DATA_LEN 128\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_READ_PACKET { \\\r\n\t160, \\\r\n\t\"FLASH_FW_READ_PACKET\", \\\r\n\t4, \\\r\n\t{  { \"addr\", NULL, MAVLINK_TYPE_UINT32_T, 0, 0, offsetof(mavlink_flash_fw_read_packet_t, addr) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 4, offsetof(mavlink_flash_fw_read_packet_t, resp) }, \\\r\n         { \"length\", NULL, MAVLINK_TYPE_UINT8_T, 0, 5, offsetof(mavlink_flash_fw_read_packet_t, length) }, \\\r\n         { \"data\", NULL, MAVLINK_TYPE_UINT8_T, 128, 6, offsetof(mavlink_flash_fw_read_packet_t, data) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_READ_PACKET { \\\r\n\t\"FLASH_FW_READ_PACKET\", \\\r\n\t4, \\\r\n\t{  { \"addr\", NULL, MAVLINK_TYPE_UINT32_T, 0, 0, offsetof(mavlink_flash_fw_read_packet_t, addr) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 4, offsetof(mavlink_flash_fw_read_packet_t, resp) }, \\\r\n         { \"length\", NULL, MAVLINK_TYPE_UINT8_T, 0, 5, offsetof(mavlink_flash_fw_read_packet_t, length) }, \\\r\n         { \"data\", NULL, MAVLINK_TYPE_UINT8_T, 128, 6, offsetof(mavlink_flash_fw_read_packet_t, data) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a flash_fw_read_packet message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n * @param data \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_read_packet_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, uint32_t addr, uint8_t length, const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN];\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint8_t(buf, 4, resp);\r\n\t_mav_put_uint8_t(buf, 5, length);\r\n\t_mav_put_uint8_t_array(buf, 6, data, 128);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN);\r\n#else\r\n\tmavlink_flash_fw_read_packet_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.resp = resp;\r\n\tpacket.length = length;\r\n\tmav_array_memcpy(packet.data, data, sizeof(uint8_t)*128);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_READ_PACKET;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a flash_fw_read_packet message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n * @param data \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_read_packet_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,uint32_t addr,uint8_t length,const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN];\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint8_t(buf, 4, resp);\r\n\t_mav_put_uint8_t(buf, 5, length);\r\n\t_mav_put_uint8_t_array(buf, 6, data, 128);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN);\r\n#else\r\n\tmavlink_flash_fw_read_packet_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.resp = resp;\r\n\tpacket.length = length;\r\n\tmav_array_memcpy(packet.data, data, sizeof(uint8_t)*128);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_READ_PACKET;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_read_packet struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_read_packet C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_read_packet_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_flash_fw_read_packet_t* flash_fw_read_packet)\r\n{\r\n\treturn mavlink_msg_flash_fw_read_packet_pack(system_id, component_id, msg, flash_fw_read_packet->resp, flash_fw_read_packet->addr, flash_fw_read_packet->length, flash_fw_read_packet->data);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_read_packet struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_read_packet C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_read_packet_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_flash_fw_read_packet_t* flash_fw_read_packet)\r\n{\r\n\treturn mavlink_msg_flash_fw_read_packet_pack_chan(system_id, component_id, chan, msg, flash_fw_read_packet->resp, flash_fw_read_packet->addr, flash_fw_read_packet->length, flash_fw_read_packet->data);\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_read_packet message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n * @param data \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_flash_fw_read_packet_send(mavlink_channel_t chan, uint8_t resp, uint32_t addr, uint8_t length, const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN];\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint8_t(buf, 4, resp);\r\n\t_mav_put_uint8_t(buf, 5, length);\r\n\t_mav_put_uint8_t_array(buf, 6, data, 128);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET, buf, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_CRC);\r\n#else\r\n\tmavlink_flash_fw_read_packet_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.resp = resp;\r\n\tpacket.length = length;\r\n\tmav_array_memcpy(packet.data, data, sizeof(uint8_t)*128);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET, (const char *)&packet, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_read_packet message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_flash_fw_read_packet_send_struct(mavlink_channel_t chan, const mavlink_flash_fw_read_packet_t* flash_fw_read_packet)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_flash_fw_read_packet_send(chan, flash_fw_read_packet->resp, flash_fw_read_packet->addr, flash_fw_read_packet->length, flash_fw_read_packet->data);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET, (const char *)flash_fw_read_packet, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_flash_fw_read_packet_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, uint32_t addr, uint8_t length, const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint8_t(buf, 4, resp);\r\n\t_mav_put_uint8_t(buf, 5, length);\r\n\t_mav_put_uint8_t_array(buf, 6, data, 128);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET, buf, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_CRC);\r\n#else\r\n\tmavlink_flash_fw_read_packet_t *packet = (mavlink_flash_fw_read_packet_t *)msgbuf;\r\n\tpacket->addr = addr;\r\n\tpacket->resp = resp;\r\n\tpacket->length = length;\r\n\tmav_array_memcpy(packet->data, data, sizeof(uint8_t)*128);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET, (const char *)packet, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE FLASH_FW_READ_PACKET UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from flash_fw_read_packet message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_flash_fw_read_packet_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  4);\r\n}\r\n\r\n/**\r\n * @brief Get field addr from flash_fw_read_packet message\r\n *\r\n * @return \r\n */\r\nstatic inline uint32_t mavlink_msg_flash_fw_read_packet_get_addr(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint32_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field length from flash_fw_read_packet message\r\n *\r\n * @return \r\n */\r\nstatic inline uint8_t mavlink_msg_flash_fw_read_packet_get_length(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  5);\r\n}\r\n\r\n/**\r\n * @brief Get field data from flash_fw_read_packet message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_read_packet_get_data(const mavlink_message_t* msg, uint8_t *data)\r\n{\r\n\treturn _MAV_RETURN_uint8_t_array(msg, data, 128,  6);\r\n}\r\n\r\n/**\r\n * @brief Decode a flash_fw_read_packet message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param flash_fw_read_packet C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_flash_fw_read_packet_decode(const mavlink_message_t* msg, mavlink_flash_fw_read_packet_t* flash_fw_read_packet)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tflash_fw_read_packet->addr = mavlink_msg_flash_fw_read_packet_get_addr(msg);\r\n\tflash_fw_read_packet->resp = mavlink_msg_flash_fw_read_packet_get_resp(msg);\r\n\tflash_fw_read_packet->length = mavlink_msg_flash_fw_read_packet_get_length(msg);\r\n\tmavlink_msg_flash_fw_read_packet_get_data(msg, flash_fw_read_packet->data);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN? msg->len : MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN;\r\n        memset(flash_fw_read_packet, 0, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN);\r\n\tmemcpy(flash_fw_read_packet, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld/msg/mavlink/opencr_msg/mavlink_msg_flash_fw_verify.h",
    "content": "// MESSAGE FLASH_FW_VERIFY PACKING\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_VERIFY 159\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_flash_fw_verify_t\r\n{\r\n uint32_t length; /*< */\r\n uint32_t crc; /*< */\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n uint8_t param[8]; /*< */\r\n} mavlink_flash_fw_verify_t;\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN 17\r\n#define MAVLINK_MSG_ID_FLASH_FW_VERIFY_MIN_LEN 17\r\n#define MAVLINK_MSG_ID_159_LEN 17\r\n#define MAVLINK_MSG_ID_159_MIN_LEN 17\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_VERIFY_CRC 31\r\n#define MAVLINK_MSG_ID_159_CRC 31\r\n\r\n#define MAVLINK_MSG_FLASH_FW_VERIFY_FIELD_PARAM_LEN 8\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_VERIFY { \\\r\n\t159, \\\r\n\t\"FLASH_FW_VERIFY\", \\\r\n\t4, \\\r\n\t{  { \"length\", NULL, MAVLINK_TYPE_UINT32_T, 0, 0, offsetof(mavlink_flash_fw_verify_t, length) }, \\\r\n         { \"crc\", NULL, MAVLINK_TYPE_UINT32_T, 0, 4, offsetof(mavlink_flash_fw_verify_t, crc) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 8, offsetof(mavlink_flash_fw_verify_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 9, offsetof(mavlink_flash_fw_verify_t, param) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_VERIFY { \\\r\n\t\"FLASH_FW_VERIFY\", \\\r\n\t4, \\\r\n\t{  { \"length\", NULL, MAVLINK_TYPE_UINT32_T, 0, 0, offsetof(mavlink_flash_fw_verify_t, length) }, \\\r\n         { \"crc\", NULL, MAVLINK_TYPE_UINT32_T, 0, 4, offsetof(mavlink_flash_fw_verify_t, crc) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 8, offsetof(mavlink_flash_fw_verify_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 9, offsetof(mavlink_flash_fw_verify_t, param) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a flash_fw_verify message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param length \r\n * @param crc \r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_verify_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, uint32_t length, uint32_t crc, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN];\r\n\t_mav_put_uint32_t(buf, 0, length);\r\n\t_mav_put_uint32_t(buf, 4, crc);\r\n\t_mav_put_uint8_t(buf, 8, resp);\r\n\t_mav_put_uint8_t_array(buf, 9, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN);\r\n#else\r\n\tmavlink_flash_fw_verify_t packet;\r\n\tpacket.length = length;\r\n\tpacket.crc = crc;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_VERIFY;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_FLASH_FW_VERIFY_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a flash_fw_verify message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param length \r\n * @param crc \r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_verify_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,uint32_t length,uint32_t crc,const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN];\r\n\t_mav_put_uint32_t(buf, 0, length);\r\n\t_mav_put_uint32_t(buf, 4, crc);\r\n\t_mav_put_uint8_t(buf, 8, resp);\r\n\t_mav_put_uint8_t_array(buf, 9, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN);\r\n#else\r\n\tmavlink_flash_fw_verify_t packet;\r\n\tpacket.length = length;\r\n\tpacket.crc = crc;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_VERIFY;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_FLASH_FW_VERIFY_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_verify struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_verify C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_verify_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_flash_fw_verify_t* flash_fw_verify)\r\n{\r\n\treturn mavlink_msg_flash_fw_verify_pack(system_id, component_id, msg, flash_fw_verify->resp, flash_fw_verify->length, flash_fw_verify->crc, flash_fw_verify->param);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_verify struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_verify C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_verify_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_flash_fw_verify_t* flash_fw_verify)\r\n{\r\n\treturn mavlink_msg_flash_fw_verify_pack_chan(system_id, component_id, chan, msg, flash_fw_verify->resp, flash_fw_verify->length, flash_fw_verify->crc, flash_fw_verify->param);\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_verify message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param length \r\n * @param crc \r\n * @param param \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_flash_fw_verify_send(mavlink_channel_t chan, uint8_t resp, uint32_t length, uint32_t crc, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN];\r\n\t_mav_put_uint32_t(buf, 0, length);\r\n\t_mav_put_uint32_t(buf, 4, crc);\r\n\t_mav_put_uint8_t(buf, 8, resp);\r\n\t_mav_put_uint8_t_array(buf, 9, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_VERIFY, buf, MAVLINK_MSG_ID_FLASH_FW_VERIFY_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_CRC);\r\n#else\r\n\tmavlink_flash_fw_verify_t packet;\r\n\tpacket.length = length;\r\n\tpacket.crc = crc;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_VERIFY, (const char *)&packet, MAVLINK_MSG_ID_FLASH_FW_VERIFY_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_verify message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_flash_fw_verify_send_struct(mavlink_channel_t chan, const mavlink_flash_fw_verify_t* flash_fw_verify)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_flash_fw_verify_send(chan, flash_fw_verify->resp, flash_fw_verify->length, flash_fw_verify->crc, flash_fw_verify->param);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_VERIFY, (const char *)flash_fw_verify, MAVLINK_MSG_ID_FLASH_FW_VERIFY_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_flash_fw_verify_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, uint32_t length, uint32_t crc, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint32_t(buf, 0, length);\r\n\t_mav_put_uint32_t(buf, 4, crc);\r\n\t_mav_put_uint8_t(buf, 8, resp);\r\n\t_mav_put_uint8_t_array(buf, 9, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_VERIFY, buf, MAVLINK_MSG_ID_FLASH_FW_VERIFY_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_CRC);\r\n#else\r\n\tmavlink_flash_fw_verify_t *packet = (mavlink_flash_fw_verify_t *)msgbuf;\r\n\tpacket->length = length;\r\n\tpacket->crc = crc;\r\n\tpacket->resp = resp;\r\n\tmav_array_memcpy(packet->param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_VERIFY, (const char *)packet, MAVLINK_MSG_ID_FLASH_FW_VERIFY_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE FLASH_FW_VERIFY UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from flash_fw_verify message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_flash_fw_verify_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  8);\r\n}\r\n\r\n/**\r\n * @brief Get field length from flash_fw_verify message\r\n *\r\n * @return \r\n */\r\nstatic inline uint32_t mavlink_msg_flash_fw_verify_get_length(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint32_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field crc from flash_fw_verify message\r\n *\r\n * @return \r\n */\r\nstatic inline uint32_t mavlink_msg_flash_fw_verify_get_crc(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint32_t(msg,  4);\r\n}\r\n\r\n/**\r\n * @brief Get field param from flash_fw_verify message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_verify_get_param(const mavlink_message_t* msg, uint8_t *param)\r\n{\r\n\treturn _MAV_RETURN_uint8_t_array(msg, param, 8,  9);\r\n}\r\n\r\n/**\r\n * @brief Decode a flash_fw_verify message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param flash_fw_verify C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_flash_fw_verify_decode(const mavlink_message_t* msg, mavlink_flash_fw_verify_t* flash_fw_verify)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tflash_fw_verify->length = mavlink_msg_flash_fw_verify_get_length(msg);\r\n\tflash_fw_verify->crc = mavlink_msg_flash_fw_verify_get_crc(msg);\r\n\tflash_fw_verify->resp = mavlink_msg_flash_fw_verify_get_resp(msg);\r\n\tmavlink_msg_flash_fw_verify_get_param(msg, flash_fw_verify->param);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN? msg->len : MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN;\r\n        memset(flash_fw_verify, 0, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN);\r\n\tmemcpy(flash_fw_verify, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld/msg/mavlink/opencr_msg/mavlink_msg_flash_fw_write_begin.h",
    "content": "// MESSAGE FLASH_FW_WRITE_BEGIN PACKING\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN 154\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_flash_fw_write_begin_t\r\n{\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n uint8_t param[8]; /*< */\r\n} mavlink_flash_fw_write_begin_t;\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN 9\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_MIN_LEN 9\r\n#define MAVLINK_MSG_ID_154_LEN 9\r\n#define MAVLINK_MSG_ID_154_MIN_LEN 9\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_CRC 8\r\n#define MAVLINK_MSG_ID_154_CRC 8\r\n\r\n#define MAVLINK_MSG_FLASH_FW_WRITE_BEGIN_FIELD_PARAM_LEN 8\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_WRITE_BEGIN { \\\r\n\t154, \\\r\n\t\"FLASH_FW_WRITE_BEGIN\", \\\r\n\t2, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_flash_fw_write_begin_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 1, offsetof(mavlink_flash_fw_write_begin_t, param) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_WRITE_BEGIN { \\\r\n\t\"FLASH_FW_WRITE_BEGIN\", \\\r\n\t2, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_flash_fw_write_begin_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 1, offsetof(mavlink_flash_fw_write_begin_t, param) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a flash_fw_write_begin message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_begin_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN);\r\n#else\r\n\tmavlink_flash_fw_write_begin_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a flash_fw_write_begin message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_begin_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN);\r\n#else\r\n\tmavlink_flash_fw_write_begin_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_write_begin struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_write_begin C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_begin_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_flash_fw_write_begin_t* flash_fw_write_begin)\r\n{\r\n\treturn mavlink_msg_flash_fw_write_begin_pack(system_id, component_id, msg, flash_fw_write_begin->resp, flash_fw_write_begin->param);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_write_begin struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_write_begin C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_begin_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_flash_fw_write_begin_t* flash_fw_write_begin)\r\n{\r\n\treturn mavlink_msg_flash_fw_write_begin_pack_chan(system_id, component_id, chan, msg, flash_fw_write_begin->resp, flash_fw_write_begin->param);\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_write_begin message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_flash_fw_write_begin_send(mavlink_channel_t chan, uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN, buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_CRC);\r\n#else\r\n\tmavlink_flash_fw_write_begin_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN, (const char *)&packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_write_begin message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_begin_send_struct(mavlink_channel_t chan, const mavlink_flash_fw_write_begin_t* flash_fw_write_begin)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_flash_fw_write_begin_send(chan, flash_fw_write_begin->resp, flash_fw_write_begin->param);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN, (const char *)flash_fw_write_begin, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_begin_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN, buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_CRC);\r\n#else\r\n\tmavlink_flash_fw_write_begin_t *packet = (mavlink_flash_fw_write_begin_t *)msgbuf;\r\n\tpacket->resp = resp;\r\n\tmav_array_memcpy(packet->param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN, (const char *)packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE FLASH_FW_WRITE_BEGIN UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from flash_fw_write_begin message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_flash_fw_write_begin_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field param from flash_fw_write_begin message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_begin_get_param(const mavlink_message_t* msg, uint8_t *param)\r\n{\r\n\treturn _MAV_RETURN_uint8_t_array(msg, param, 8,  1);\r\n}\r\n\r\n/**\r\n * @brief Decode a flash_fw_write_begin message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param flash_fw_write_begin C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_begin_decode(const mavlink_message_t* msg, mavlink_flash_fw_write_begin_t* flash_fw_write_begin)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tflash_fw_write_begin->resp = mavlink_msg_flash_fw_write_begin_get_resp(msg);\r\n\tmavlink_msg_flash_fw_write_begin_get_param(msg, flash_fw_write_begin->param);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN? msg->len : MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN;\r\n        memset(flash_fw_write_begin, 0, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN);\r\n\tmemcpy(flash_fw_write_begin, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld/msg/mavlink/opencr_msg/mavlink_msg_flash_fw_write_block.h",
    "content": "// MESSAGE FLASH_FW_WRITE_BLOCK PACKING\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK 157\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_flash_fw_write_block_t\r\n{\r\n uint32_t addr; /*< */\r\n uint16_t length; /*< */\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n} mavlink_flash_fw_write_block_t;\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN 7\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_MIN_LEN 7\r\n#define MAVLINK_MSG_ID_157_LEN 7\r\n#define MAVLINK_MSG_ID_157_MIN_LEN 7\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_CRC 226\r\n#define MAVLINK_MSG_ID_157_CRC 226\r\n\r\n\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_WRITE_BLOCK { \\\r\n\t157, \\\r\n\t\"FLASH_FW_WRITE_BLOCK\", \\\r\n\t3, \\\r\n\t{  { \"addr\", NULL, MAVLINK_TYPE_UINT32_T, 0, 0, offsetof(mavlink_flash_fw_write_block_t, addr) }, \\\r\n         { \"length\", NULL, MAVLINK_TYPE_UINT16_T, 0, 4, offsetof(mavlink_flash_fw_write_block_t, length) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 6, offsetof(mavlink_flash_fw_write_block_t, resp) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_WRITE_BLOCK { \\\r\n\t\"FLASH_FW_WRITE_BLOCK\", \\\r\n\t3, \\\r\n\t{  { \"addr\", NULL, MAVLINK_TYPE_UINT32_T, 0, 0, offsetof(mavlink_flash_fw_write_block_t, addr) }, \\\r\n         { \"length\", NULL, MAVLINK_TYPE_UINT16_T, 0, 4, offsetof(mavlink_flash_fw_write_block_t, length) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 6, offsetof(mavlink_flash_fw_write_block_t, resp) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a flash_fw_write_block message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_block_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, uint32_t addr, uint16_t length)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN];\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint16_t(buf, 4, length);\r\n\t_mav_put_uint8_t(buf, 6, resp);\r\n\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN);\r\n#else\r\n\tmavlink_flash_fw_write_block_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.length = length;\r\n\tpacket.resp = resp;\r\n\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a flash_fw_write_block message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_block_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,uint32_t addr,uint16_t length)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN];\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint16_t(buf, 4, length);\r\n\t_mav_put_uint8_t(buf, 6, resp);\r\n\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN);\r\n#else\r\n\tmavlink_flash_fw_write_block_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.length = length;\r\n\tpacket.resp = resp;\r\n\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_write_block struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_write_block C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_block_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_flash_fw_write_block_t* flash_fw_write_block)\r\n{\r\n\treturn mavlink_msg_flash_fw_write_block_pack(system_id, component_id, msg, flash_fw_write_block->resp, flash_fw_write_block->addr, flash_fw_write_block->length);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_write_block struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_write_block C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_block_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_flash_fw_write_block_t* flash_fw_write_block)\r\n{\r\n\treturn mavlink_msg_flash_fw_write_block_pack_chan(system_id, component_id, chan, msg, flash_fw_write_block->resp, flash_fw_write_block->addr, flash_fw_write_block->length);\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_write_block message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_flash_fw_write_block_send(mavlink_channel_t chan, uint8_t resp, uint32_t addr, uint16_t length)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN];\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint16_t(buf, 4, length);\r\n\t_mav_put_uint8_t(buf, 6, resp);\r\n\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK, buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_CRC);\r\n#else\r\n\tmavlink_flash_fw_write_block_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.length = length;\r\n\tpacket.resp = resp;\r\n\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK, (const char *)&packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_write_block message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_block_send_struct(mavlink_channel_t chan, const mavlink_flash_fw_write_block_t* flash_fw_write_block)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_flash_fw_write_block_send(chan, flash_fw_write_block->resp, flash_fw_write_block->addr, flash_fw_write_block->length);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK, (const char *)flash_fw_write_block, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_block_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, uint32_t addr, uint16_t length)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint16_t(buf, 4, length);\r\n\t_mav_put_uint8_t(buf, 6, resp);\r\n\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK, buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_CRC);\r\n#else\r\n\tmavlink_flash_fw_write_block_t *packet = (mavlink_flash_fw_write_block_t *)msgbuf;\r\n\tpacket->addr = addr;\r\n\tpacket->length = length;\r\n\tpacket->resp = resp;\r\n\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK, (const char *)packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE FLASH_FW_WRITE_BLOCK UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from flash_fw_write_block message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_flash_fw_write_block_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  6);\r\n}\r\n\r\n/**\r\n * @brief Get field addr from flash_fw_write_block message\r\n *\r\n * @return \r\n */\r\nstatic inline uint32_t mavlink_msg_flash_fw_write_block_get_addr(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint32_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field length from flash_fw_write_block message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_block_get_length(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint16_t(msg,  4);\r\n}\r\n\r\n/**\r\n * @brief Decode a flash_fw_write_block message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param flash_fw_write_block C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_block_decode(const mavlink_message_t* msg, mavlink_flash_fw_write_block_t* flash_fw_write_block)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tflash_fw_write_block->addr = mavlink_msg_flash_fw_write_block_get_addr(msg);\r\n\tflash_fw_write_block->length = mavlink_msg_flash_fw_write_block_get_length(msg);\r\n\tflash_fw_write_block->resp = mavlink_msg_flash_fw_write_block_get_resp(msg);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN? msg->len : MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN;\r\n        memset(flash_fw_write_block, 0, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN);\r\n\tmemcpy(flash_fw_write_block, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld/msg/mavlink/opencr_msg/mavlink_msg_flash_fw_write_end.h",
    "content": "// MESSAGE FLASH_FW_WRITE_END PACKING\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_END 155\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_flash_fw_write_end_t\r\n{\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n uint8_t param[8]; /*< */\r\n} mavlink_flash_fw_write_end_t;\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN 9\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_END_MIN_LEN 9\r\n#define MAVLINK_MSG_ID_155_LEN 9\r\n#define MAVLINK_MSG_ID_155_MIN_LEN 9\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_END_CRC 48\r\n#define MAVLINK_MSG_ID_155_CRC 48\r\n\r\n#define MAVLINK_MSG_FLASH_FW_WRITE_END_FIELD_PARAM_LEN 8\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_WRITE_END { \\\r\n\t155, \\\r\n\t\"FLASH_FW_WRITE_END\", \\\r\n\t2, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_flash_fw_write_end_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 1, offsetof(mavlink_flash_fw_write_end_t, param) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_WRITE_END { \\\r\n\t\"FLASH_FW_WRITE_END\", \\\r\n\t2, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_flash_fw_write_end_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 1, offsetof(mavlink_flash_fw_write_end_t, param) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a flash_fw_write_end message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_end_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN);\r\n#else\r\n\tmavlink_flash_fw_write_end_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_WRITE_END;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a flash_fw_write_end message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_end_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN);\r\n#else\r\n\tmavlink_flash_fw_write_end_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_WRITE_END;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_write_end struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_write_end C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_end_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_flash_fw_write_end_t* flash_fw_write_end)\r\n{\r\n\treturn mavlink_msg_flash_fw_write_end_pack(system_id, component_id, msg, flash_fw_write_end->resp, flash_fw_write_end->param);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_write_end struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_write_end C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_end_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_flash_fw_write_end_t* flash_fw_write_end)\r\n{\r\n\treturn mavlink_msg_flash_fw_write_end_pack_chan(system_id, component_id, chan, msg, flash_fw_write_end->resp, flash_fw_write_end->param);\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_write_end message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_flash_fw_write_end_send(mavlink_channel_t chan, uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_END, buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_CRC);\r\n#else\r\n\tmavlink_flash_fw_write_end_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_END, (const char *)&packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_write_end message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_end_send_struct(mavlink_channel_t chan, const mavlink_flash_fw_write_end_t* flash_fw_write_end)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_flash_fw_write_end_send(chan, flash_fw_write_end->resp, flash_fw_write_end->param);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_END, (const char *)flash_fw_write_end, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_end_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_END, buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_CRC);\r\n#else\r\n\tmavlink_flash_fw_write_end_t *packet = (mavlink_flash_fw_write_end_t *)msgbuf;\r\n\tpacket->resp = resp;\r\n\tmav_array_memcpy(packet->param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_END, (const char *)packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE FLASH_FW_WRITE_END UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from flash_fw_write_end message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_flash_fw_write_end_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field param from flash_fw_write_end message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_end_get_param(const mavlink_message_t* msg, uint8_t *param)\r\n{\r\n\treturn _MAV_RETURN_uint8_t_array(msg, param, 8,  1);\r\n}\r\n\r\n/**\r\n * @brief Decode a flash_fw_write_end message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param flash_fw_write_end C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_end_decode(const mavlink_message_t* msg, mavlink_flash_fw_write_end_t* flash_fw_write_end)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tflash_fw_write_end->resp = mavlink_msg_flash_fw_write_end_get_resp(msg);\r\n\tmavlink_msg_flash_fw_write_end_get_param(msg, flash_fw_write_end->param);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN? msg->len : MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN;\r\n        memset(flash_fw_write_end, 0, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN);\r\n\tmemcpy(flash_fw_write_end, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld/msg/mavlink/opencr_msg/mavlink_msg_flash_fw_write_packet.h",
    "content": "// MESSAGE FLASH_FW_WRITE_PACKET PACKING\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET 156\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_flash_fw_write_packet_t\r\n{\r\n uint16_t addr; /*< */\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n uint8_t length; /*< */\r\n uint8_t data[128]; /*< */\r\n} mavlink_flash_fw_write_packet_t;\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN 132\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_MIN_LEN 132\r\n#define MAVLINK_MSG_ID_156_LEN 132\r\n#define MAVLINK_MSG_ID_156_MIN_LEN 132\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_CRC 233\r\n#define MAVLINK_MSG_ID_156_CRC 233\r\n\r\n#define MAVLINK_MSG_FLASH_FW_WRITE_PACKET_FIELD_DATA_LEN 128\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_WRITE_PACKET { \\\r\n\t156, \\\r\n\t\"FLASH_FW_WRITE_PACKET\", \\\r\n\t4, \\\r\n\t{  { \"addr\", NULL, MAVLINK_TYPE_UINT16_T, 0, 0, offsetof(mavlink_flash_fw_write_packet_t, addr) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 2, offsetof(mavlink_flash_fw_write_packet_t, resp) }, \\\r\n         { \"length\", NULL, MAVLINK_TYPE_UINT8_T, 0, 3, offsetof(mavlink_flash_fw_write_packet_t, length) }, \\\r\n         { \"data\", NULL, MAVLINK_TYPE_UINT8_T, 128, 4, offsetof(mavlink_flash_fw_write_packet_t, data) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_WRITE_PACKET { \\\r\n\t\"FLASH_FW_WRITE_PACKET\", \\\r\n\t4, \\\r\n\t{  { \"addr\", NULL, MAVLINK_TYPE_UINT16_T, 0, 0, offsetof(mavlink_flash_fw_write_packet_t, addr) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 2, offsetof(mavlink_flash_fw_write_packet_t, resp) }, \\\r\n         { \"length\", NULL, MAVLINK_TYPE_UINT8_T, 0, 3, offsetof(mavlink_flash_fw_write_packet_t, length) }, \\\r\n         { \"data\", NULL, MAVLINK_TYPE_UINT8_T, 128, 4, offsetof(mavlink_flash_fw_write_packet_t, data) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a flash_fw_write_packet message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n * @param data \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_packet_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, uint16_t addr, uint8_t length, const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN];\r\n\t_mav_put_uint16_t(buf, 0, addr);\r\n\t_mav_put_uint8_t(buf, 2, resp);\r\n\t_mav_put_uint8_t(buf, 3, length);\r\n\t_mav_put_uint8_t_array(buf, 4, data, 128);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN);\r\n#else\r\n\tmavlink_flash_fw_write_packet_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.resp = resp;\r\n\tpacket.length = length;\r\n\tmav_array_memcpy(packet.data, data, sizeof(uint8_t)*128);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a flash_fw_write_packet message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n * @param data \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_packet_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,uint16_t addr,uint8_t length,const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN];\r\n\t_mav_put_uint16_t(buf, 0, addr);\r\n\t_mav_put_uint8_t(buf, 2, resp);\r\n\t_mav_put_uint8_t(buf, 3, length);\r\n\t_mav_put_uint8_t_array(buf, 4, data, 128);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN);\r\n#else\r\n\tmavlink_flash_fw_write_packet_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.resp = resp;\r\n\tpacket.length = length;\r\n\tmav_array_memcpy(packet.data, data, sizeof(uint8_t)*128);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_write_packet struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_write_packet C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_packet_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_flash_fw_write_packet_t* flash_fw_write_packet)\r\n{\r\n\treturn mavlink_msg_flash_fw_write_packet_pack(system_id, component_id, msg, flash_fw_write_packet->resp, flash_fw_write_packet->addr, flash_fw_write_packet->length, flash_fw_write_packet->data);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_write_packet struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_write_packet C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_packet_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_flash_fw_write_packet_t* flash_fw_write_packet)\r\n{\r\n\treturn mavlink_msg_flash_fw_write_packet_pack_chan(system_id, component_id, chan, msg, flash_fw_write_packet->resp, flash_fw_write_packet->addr, flash_fw_write_packet->length, flash_fw_write_packet->data);\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_write_packet message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n * @param data \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_flash_fw_write_packet_send(mavlink_channel_t chan, uint8_t resp, uint16_t addr, uint8_t length, const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN];\r\n\t_mav_put_uint16_t(buf, 0, addr);\r\n\t_mav_put_uint8_t(buf, 2, resp);\r\n\t_mav_put_uint8_t(buf, 3, length);\r\n\t_mav_put_uint8_t_array(buf, 4, data, 128);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET, buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_CRC);\r\n#else\r\n\tmavlink_flash_fw_write_packet_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.resp = resp;\r\n\tpacket.length = length;\r\n\tmav_array_memcpy(packet.data, data, sizeof(uint8_t)*128);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET, (const char *)&packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_write_packet message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_packet_send_struct(mavlink_channel_t chan, const mavlink_flash_fw_write_packet_t* flash_fw_write_packet)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_flash_fw_write_packet_send(chan, flash_fw_write_packet->resp, flash_fw_write_packet->addr, flash_fw_write_packet->length, flash_fw_write_packet->data);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET, (const char *)flash_fw_write_packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_packet_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, uint16_t addr, uint8_t length, const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint16_t(buf, 0, addr);\r\n\t_mav_put_uint8_t(buf, 2, resp);\r\n\t_mav_put_uint8_t(buf, 3, length);\r\n\t_mav_put_uint8_t_array(buf, 4, data, 128);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET, buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_CRC);\r\n#else\r\n\tmavlink_flash_fw_write_packet_t *packet = (mavlink_flash_fw_write_packet_t *)msgbuf;\r\n\tpacket->addr = addr;\r\n\tpacket->resp = resp;\r\n\tpacket->length = length;\r\n\tmav_array_memcpy(packet->data, data, sizeof(uint8_t)*128);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET, (const char *)packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE FLASH_FW_WRITE_PACKET UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from flash_fw_write_packet message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_flash_fw_write_packet_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  2);\r\n}\r\n\r\n/**\r\n * @brief Get field addr from flash_fw_write_packet message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_packet_get_addr(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint16_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field length from flash_fw_write_packet message\r\n *\r\n * @return \r\n */\r\nstatic inline uint8_t mavlink_msg_flash_fw_write_packet_get_length(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  3);\r\n}\r\n\r\n/**\r\n * @brief Get field data from flash_fw_write_packet message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_packet_get_data(const mavlink_message_t* msg, uint8_t *data)\r\n{\r\n\treturn _MAV_RETURN_uint8_t_array(msg, data, 128,  4);\r\n}\r\n\r\n/**\r\n * @brief Decode a flash_fw_write_packet message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param flash_fw_write_packet C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_packet_decode(const mavlink_message_t* msg, mavlink_flash_fw_write_packet_t* flash_fw_write_packet)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tflash_fw_write_packet->addr = mavlink_msg_flash_fw_write_packet_get_addr(msg);\r\n\tflash_fw_write_packet->resp = mavlink_msg_flash_fw_write_packet_get_resp(msg);\r\n\tflash_fw_write_packet->length = mavlink_msg_flash_fw_write_packet_get_length(msg);\r\n\tmavlink_msg_flash_fw_write_packet_get_data(msg, flash_fw_write_packet->data);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN? msg->len : MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN;\r\n        memset(flash_fw_write_packet, 0, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN);\r\n\tmemcpy(flash_fw_write_packet, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld/msg/mavlink/opencr_msg/mavlink_msg_jump_to_fw.h",
    "content": "// MESSAGE JUMP_TO_FW PACKING\r\n\r\n#define MAVLINK_MSG_ID_JUMP_TO_FW 162\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_jump_to_fw_t\r\n{\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n uint8_t param[8]; /*< */\r\n} mavlink_jump_to_fw_t;\r\n\r\n#define MAVLINK_MSG_ID_JUMP_TO_FW_LEN 9\r\n#define MAVLINK_MSG_ID_JUMP_TO_FW_MIN_LEN 9\r\n#define MAVLINK_MSG_ID_162_LEN 9\r\n#define MAVLINK_MSG_ID_162_MIN_LEN 9\r\n\r\n#define MAVLINK_MSG_ID_JUMP_TO_FW_CRC 37\r\n#define MAVLINK_MSG_ID_162_CRC 37\r\n\r\n#define MAVLINK_MSG_JUMP_TO_FW_FIELD_PARAM_LEN 8\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_JUMP_TO_FW { \\\r\n\t162, \\\r\n\t\"JUMP_TO_FW\", \\\r\n\t2, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_jump_to_fw_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 1, offsetof(mavlink_jump_to_fw_t, param) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_JUMP_TO_FW { \\\r\n\t\"JUMP_TO_FW\", \\\r\n\t2, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_jump_to_fw_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 1, offsetof(mavlink_jump_to_fw_t, param) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a jump_to_fw message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_jump_to_fw_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_JUMP_TO_FW_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_JUMP_TO_FW_LEN);\r\n#else\r\n\tmavlink_jump_to_fw_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_JUMP_TO_FW_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_JUMP_TO_FW;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_JUMP_TO_FW_MIN_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a jump_to_fw message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_jump_to_fw_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_JUMP_TO_FW_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_JUMP_TO_FW_LEN);\r\n#else\r\n\tmavlink_jump_to_fw_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_JUMP_TO_FW_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_JUMP_TO_FW;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_JUMP_TO_FW_MIN_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a jump_to_fw struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param jump_to_fw C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_jump_to_fw_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_jump_to_fw_t* jump_to_fw)\r\n{\r\n\treturn mavlink_msg_jump_to_fw_pack(system_id, component_id, msg, jump_to_fw->resp, jump_to_fw->param);\r\n}\r\n\r\n/**\r\n * @brief Encode a jump_to_fw struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param jump_to_fw C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_jump_to_fw_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_jump_to_fw_t* jump_to_fw)\r\n{\r\n\treturn mavlink_msg_jump_to_fw_pack_chan(system_id, component_id, chan, msg, jump_to_fw->resp, jump_to_fw->param);\r\n}\r\n\r\n/**\r\n * @brief Send a jump_to_fw message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_jump_to_fw_send(mavlink_channel_t chan, uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_JUMP_TO_FW_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_JUMP_TO_FW, buf, MAVLINK_MSG_ID_JUMP_TO_FW_MIN_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_CRC);\r\n#else\r\n\tmavlink_jump_to_fw_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_JUMP_TO_FW, (const char *)&packet, MAVLINK_MSG_ID_JUMP_TO_FW_MIN_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a jump_to_fw message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_jump_to_fw_send_struct(mavlink_channel_t chan, const mavlink_jump_to_fw_t* jump_to_fw)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_jump_to_fw_send(chan, jump_to_fw->resp, jump_to_fw->param);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_JUMP_TO_FW, (const char *)jump_to_fw, MAVLINK_MSG_ID_JUMP_TO_FW_MIN_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_JUMP_TO_FW_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_jump_to_fw_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_JUMP_TO_FW, buf, MAVLINK_MSG_ID_JUMP_TO_FW_MIN_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_CRC);\r\n#else\r\n\tmavlink_jump_to_fw_t *packet = (mavlink_jump_to_fw_t *)msgbuf;\r\n\tpacket->resp = resp;\r\n\tmav_array_memcpy(packet->param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_JUMP_TO_FW, (const char *)packet, MAVLINK_MSG_ID_JUMP_TO_FW_MIN_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE JUMP_TO_FW UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from jump_to_fw message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_jump_to_fw_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field param from jump_to_fw message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_jump_to_fw_get_param(const mavlink_message_t* msg, uint8_t *param)\r\n{\r\n\treturn _MAV_RETURN_uint8_t_array(msg, param, 8,  1);\r\n}\r\n\r\n/**\r\n * @brief Decode a jump_to_fw message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param jump_to_fw C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_jump_to_fw_decode(const mavlink_message_t* msg, mavlink_jump_to_fw_t* jump_to_fw)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tjump_to_fw->resp = mavlink_msg_jump_to_fw_get_resp(msg);\r\n\tmavlink_msg_jump_to_fw_get_param(msg, jump_to_fw->param);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_JUMP_TO_FW_LEN? msg->len : MAVLINK_MSG_ID_JUMP_TO_FW_LEN;\r\n        memset(jump_to_fw, 0, MAVLINK_MSG_ID_JUMP_TO_FW_LEN);\r\n\tmemcpy(jump_to_fw, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld/msg/mavlink/opencr_msg/mavlink_msg_read_board_name.h",
    "content": "// MESSAGE READ_BOARD_NAME PACKING\r\n\r\n#define MAVLINK_MSG_ID_READ_BOARD_NAME 152\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_read_board_name_t\r\n{\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n uint8_t param[8]; /*< */\r\n} mavlink_read_board_name_t;\r\n\r\n#define MAVLINK_MSG_ID_READ_BOARD_NAME_LEN 9\r\n#define MAVLINK_MSG_ID_READ_BOARD_NAME_MIN_LEN 9\r\n#define MAVLINK_MSG_ID_152_LEN 9\r\n#define MAVLINK_MSG_ID_152_MIN_LEN 9\r\n\r\n#define MAVLINK_MSG_ID_READ_BOARD_NAME_CRC 140\r\n#define MAVLINK_MSG_ID_152_CRC 140\r\n\r\n#define MAVLINK_MSG_READ_BOARD_NAME_FIELD_PARAM_LEN 8\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_READ_BOARD_NAME { \\\r\n\t152, \\\r\n\t\"READ_BOARD_NAME\", \\\r\n\t2, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_read_board_name_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 1, offsetof(mavlink_read_board_name_t, param) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_READ_BOARD_NAME { \\\r\n\t\"READ_BOARD_NAME\", \\\r\n\t2, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_read_board_name_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 1, offsetof(mavlink_read_board_name_t, param) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a read_board_name message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_read_board_name_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_READ_BOARD_NAME_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN);\r\n#else\r\n\tmavlink_read_board_name_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_READ_BOARD_NAME;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_READ_BOARD_NAME_MIN_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a read_board_name message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_read_board_name_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_READ_BOARD_NAME_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN);\r\n#else\r\n\tmavlink_read_board_name_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_READ_BOARD_NAME;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_READ_BOARD_NAME_MIN_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a read_board_name struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param read_board_name C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_read_board_name_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_read_board_name_t* read_board_name)\r\n{\r\n\treturn mavlink_msg_read_board_name_pack(system_id, component_id, msg, read_board_name->resp, read_board_name->param);\r\n}\r\n\r\n/**\r\n * @brief Encode a read_board_name struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param read_board_name C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_read_board_name_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_read_board_name_t* read_board_name)\r\n{\r\n\treturn mavlink_msg_read_board_name_pack_chan(system_id, component_id, chan, msg, read_board_name->resp, read_board_name->param);\r\n}\r\n\r\n/**\r\n * @brief Send a read_board_name message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_read_board_name_send(mavlink_channel_t chan, uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_READ_BOARD_NAME_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_BOARD_NAME, buf, MAVLINK_MSG_ID_READ_BOARD_NAME_MIN_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_CRC);\r\n#else\r\n\tmavlink_read_board_name_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_BOARD_NAME, (const char *)&packet, MAVLINK_MSG_ID_READ_BOARD_NAME_MIN_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a read_board_name message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_read_board_name_send_struct(mavlink_channel_t chan, const mavlink_read_board_name_t* read_board_name)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_read_board_name_send(chan, read_board_name->resp, read_board_name->param);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_BOARD_NAME, (const char *)read_board_name, MAVLINK_MSG_ID_READ_BOARD_NAME_MIN_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_READ_BOARD_NAME_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_read_board_name_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_BOARD_NAME, buf, MAVLINK_MSG_ID_READ_BOARD_NAME_MIN_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_CRC);\r\n#else\r\n\tmavlink_read_board_name_t *packet = (mavlink_read_board_name_t *)msgbuf;\r\n\tpacket->resp = resp;\r\n\tmav_array_memcpy(packet->param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_BOARD_NAME, (const char *)packet, MAVLINK_MSG_ID_READ_BOARD_NAME_MIN_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE READ_BOARD_NAME UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from read_board_name message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_read_board_name_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field param from read_board_name message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_read_board_name_get_param(const mavlink_message_t* msg, uint8_t *param)\r\n{\r\n\treturn _MAV_RETURN_uint8_t_array(msg, param, 8,  1);\r\n}\r\n\r\n/**\r\n * @brief Decode a read_board_name message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param read_board_name C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_read_board_name_decode(const mavlink_message_t* msg, mavlink_read_board_name_t* read_board_name)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tread_board_name->resp = mavlink_msg_read_board_name_get_resp(msg);\r\n\tmavlink_msg_read_board_name_get_param(msg, read_board_name->param);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_READ_BOARD_NAME_LEN? msg->len : MAVLINK_MSG_ID_READ_BOARD_NAME_LEN;\r\n        memset(read_board_name, 0, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN);\r\n\tmemcpy(read_board_name, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld/msg/mavlink/opencr_msg/mavlink_msg_read_tag.h",
    "content": "// MESSAGE READ_TAG PACKING\r\n\r\n#define MAVLINK_MSG_ID_READ_TAG 153\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_read_tag_t\r\n{\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n uint8_t type; /*< */\r\n uint8_t param[8]; /*< */\r\n} mavlink_read_tag_t;\r\n\r\n#define MAVLINK_MSG_ID_READ_TAG_LEN 10\r\n#define MAVLINK_MSG_ID_READ_TAG_MIN_LEN 10\r\n#define MAVLINK_MSG_ID_153_LEN 10\r\n#define MAVLINK_MSG_ID_153_MIN_LEN 10\r\n\r\n#define MAVLINK_MSG_ID_READ_TAG_CRC 126\r\n#define MAVLINK_MSG_ID_153_CRC 126\r\n\r\n#define MAVLINK_MSG_READ_TAG_FIELD_PARAM_LEN 8\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_READ_TAG { \\\r\n\t153, \\\r\n\t\"READ_TAG\", \\\r\n\t3, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_read_tag_t, resp) }, \\\r\n         { \"type\", NULL, MAVLINK_TYPE_UINT8_T, 0, 1, offsetof(mavlink_read_tag_t, type) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 2, offsetof(mavlink_read_tag_t, param) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_READ_TAG { \\\r\n\t\"READ_TAG\", \\\r\n\t3, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_read_tag_t, resp) }, \\\r\n         { \"type\", NULL, MAVLINK_TYPE_UINT8_T, 0, 1, offsetof(mavlink_read_tag_t, type) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 2, offsetof(mavlink_read_tag_t, param) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a read_tag message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param type \r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_read_tag_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, uint8_t type, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_READ_TAG_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t(buf, 1, type);\r\n\t_mav_put_uint8_t_array(buf, 2, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_READ_TAG_LEN);\r\n#else\r\n\tmavlink_read_tag_t packet;\r\n\tpacket.resp = resp;\r\n\tpacket.type = type;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_READ_TAG_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_READ_TAG;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_READ_TAG_MIN_LEN, MAVLINK_MSG_ID_READ_TAG_LEN, MAVLINK_MSG_ID_READ_TAG_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a read_tag message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param type \r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_read_tag_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,uint8_t type,const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_READ_TAG_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t(buf, 1, type);\r\n\t_mav_put_uint8_t_array(buf, 2, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_READ_TAG_LEN);\r\n#else\r\n\tmavlink_read_tag_t packet;\r\n\tpacket.resp = resp;\r\n\tpacket.type = type;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_READ_TAG_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_READ_TAG;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_READ_TAG_MIN_LEN, MAVLINK_MSG_ID_READ_TAG_LEN, MAVLINK_MSG_ID_READ_TAG_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a read_tag struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param read_tag C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_read_tag_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_read_tag_t* read_tag)\r\n{\r\n\treturn mavlink_msg_read_tag_pack(system_id, component_id, msg, read_tag->resp, read_tag->type, read_tag->param);\r\n}\r\n\r\n/**\r\n * @brief Encode a read_tag struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param read_tag C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_read_tag_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_read_tag_t* read_tag)\r\n{\r\n\treturn mavlink_msg_read_tag_pack_chan(system_id, component_id, chan, msg, read_tag->resp, read_tag->type, read_tag->param);\r\n}\r\n\r\n/**\r\n * @brief Send a read_tag message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param type \r\n * @param param \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_read_tag_send(mavlink_channel_t chan, uint8_t resp, uint8_t type, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_READ_TAG_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t(buf, 1, type);\r\n\t_mav_put_uint8_t_array(buf, 2, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_TAG, buf, MAVLINK_MSG_ID_READ_TAG_MIN_LEN, MAVLINK_MSG_ID_READ_TAG_LEN, MAVLINK_MSG_ID_READ_TAG_CRC);\r\n#else\r\n\tmavlink_read_tag_t packet;\r\n\tpacket.resp = resp;\r\n\tpacket.type = type;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_TAG, (const char *)&packet, MAVLINK_MSG_ID_READ_TAG_MIN_LEN, MAVLINK_MSG_ID_READ_TAG_LEN, MAVLINK_MSG_ID_READ_TAG_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a read_tag message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_read_tag_send_struct(mavlink_channel_t chan, const mavlink_read_tag_t* read_tag)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_read_tag_send(chan, read_tag->resp, read_tag->type, read_tag->param);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_TAG, (const char *)read_tag, MAVLINK_MSG_ID_READ_TAG_MIN_LEN, MAVLINK_MSG_ID_READ_TAG_LEN, MAVLINK_MSG_ID_READ_TAG_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_READ_TAG_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_read_tag_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, uint8_t type, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t(buf, 1, type);\r\n\t_mav_put_uint8_t_array(buf, 2, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_TAG, buf, MAVLINK_MSG_ID_READ_TAG_MIN_LEN, MAVLINK_MSG_ID_READ_TAG_LEN, MAVLINK_MSG_ID_READ_TAG_CRC);\r\n#else\r\n\tmavlink_read_tag_t *packet = (mavlink_read_tag_t *)msgbuf;\r\n\tpacket->resp = resp;\r\n\tpacket->type = type;\r\n\tmav_array_memcpy(packet->param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_TAG, (const char *)packet, MAVLINK_MSG_ID_READ_TAG_MIN_LEN, MAVLINK_MSG_ID_READ_TAG_LEN, MAVLINK_MSG_ID_READ_TAG_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE READ_TAG UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from read_tag message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_read_tag_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field type from read_tag message\r\n *\r\n * @return \r\n */\r\nstatic inline uint8_t mavlink_msg_read_tag_get_type(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  1);\r\n}\r\n\r\n/**\r\n * @brief Get field param from read_tag message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_read_tag_get_param(const mavlink_message_t* msg, uint8_t *param)\r\n{\r\n\treturn _MAV_RETURN_uint8_t_array(msg, param, 8,  2);\r\n}\r\n\r\n/**\r\n * @brief Decode a read_tag message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param read_tag C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_read_tag_decode(const mavlink_message_t* msg, mavlink_read_tag_t* read_tag)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tread_tag->resp = mavlink_msg_read_tag_get_resp(msg);\r\n\tread_tag->type = mavlink_msg_read_tag_get_type(msg);\r\n\tmavlink_msg_read_tag_get_param(msg, read_tag->param);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_READ_TAG_LEN? msg->len : MAVLINK_MSG_ID_READ_TAG_LEN;\r\n        memset(read_tag, 0, MAVLINK_MSG_ID_READ_TAG_LEN);\r\n\tmemcpy(read_tag, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld/msg/mavlink/opencr_msg/mavlink_msg_read_version.h",
    "content": "// MESSAGE READ_VERSION PACKING\r\n\r\n#define MAVLINK_MSG_ID_READ_VERSION 151\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_read_version_t\r\n{\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n uint8_t param[8]; /*< */\r\n} mavlink_read_version_t;\r\n\r\n#define MAVLINK_MSG_ID_READ_VERSION_LEN 9\r\n#define MAVLINK_MSG_ID_READ_VERSION_MIN_LEN 9\r\n#define MAVLINK_MSG_ID_151_LEN 9\r\n#define MAVLINK_MSG_ID_151_MIN_LEN 9\r\n\r\n#define MAVLINK_MSG_ID_READ_VERSION_CRC 166\r\n#define MAVLINK_MSG_ID_151_CRC 166\r\n\r\n#define MAVLINK_MSG_READ_VERSION_FIELD_PARAM_LEN 8\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_READ_VERSION { \\\r\n\t151, \\\r\n\t\"READ_VERSION\", \\\r\n\t2, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_read_version_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 1, offsetof(mavlink_read_version_t, param) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_READ_VERSION { \\\r\n\t\"READ_VERSION\", \\\r\n\t2, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_read_version_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 1, offsetof(mavlink_read_version_t, param) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a read_version message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_read_version_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_READ_VERSION_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_READ_VERSION_LEN);\r\n#else\r\n\tmavlink_read_version_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_READ_VERSION_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_READ_VERSION;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_READ_VERSION_MIN_LEN, MAVLINK_MSG_ID_READ_VERSION_LEN, MAVLINK_MSG_ID_READ_VERSION_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a read_version message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_read_version_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_READ_VERSION_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_READ_VERSION_LEN);\r\n#else\r\n\tmavlink_read_version_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_READ_VERSION_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_READ_VERSION;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_READ_VERSION_MIN_LEN, MAVLINK_MSG_ID_READ_VERSION_LEN, MAVLINK_MSG_ID_READ_VERSION_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a read_version struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param read_version C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_read_version_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_read_version_t* read_version)\r\n{\r\n\treturn mavlink_msg_read_version_pack(system_id, component_id, msg, read_version->resp, read_version->param);\r\n}\r\n\r\n/**\r\n * @brief Encode a read_version struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param read_version C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_read_version_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_read_version_t* read_version)\r\n{\r\n\treturn mavlink_msg_read_version_pack_chan(system_id, component_id, chan, msg, read_version->resp, read_version->param);\r\n}\r\n\r\n/**\r\n * @brief Send a read_version message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_read_version_send(mavlink_channel_t chan, uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_READ_VERSION_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_VERSION, buf, MAVLINK_MSG_ID_READ_VERSION_MIN_LEN, MAVLINK_MSG_ID_READ_VERSION_LEN, MAVLINK_MSG_ID_READ_VERSION_CRC);\r\n#else\r\n\tmavlink_read_version_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_VERSION, (const char *)&packet, MAVLINK_MSG_ID_READ_VERSION_MIN_LEN, MAVLINK_MSG_ID_READ_VERSION_LEN, MAVLINK_MSG_ID_READ_VERSION_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a read_version message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_read_version_send_struct(mavlink_channel_t chan, const mavlink_read_version_t* read_version)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_read_version_send(chan, read_version->resp, read_version->param);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_VERSION, (const char *)read_version, MAVLINK_MSG_ID_READ_VERSION_MIN_LEN, MAVLINK_MSG_ID_READ_VERSION_LEN, MAVLINK_MSG_ID_READ_VERSION_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_READ_VERSION_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_read_version_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_VERSION, buf, MAVLINK_MSG_ID_READ_VERSION_MIN_LEN, MAVLINK_MSG_ID_READ_VERSION_LEN, MAVLINK_MSG_ID_READ_VERSION_CRC);\r\n#else\r\n\tmavlink_read_version_t *packet = (mavlink_read_version_t *)msgbuf;\r\n\tpacket->resp = resp;\r\n\tmav_array_memcpy(packet->param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_VERSION, (const char *)packet, MAVLINK_MSG_ID_READ_VERSION_MIN_LEN, MAVLINK_MSG_ID_READ_VERSION_LEN, MAVLINK_MSG_ID_READ_VERSION_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE READ_VERSION UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from read_version message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_read_version_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field param from read_version message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_read_version_get_param(const mavlink_message_t* msg, uint8_t *param)\r\n{\r\n\treturn _MAV_RETURN_uint8_t_array(msg, param, 8,  1);\r\n}\r\n\r\n/**\r\n * @brief Decode a read_version message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param read_version C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_read_version_decode(const mavlink_message_t* msg, mavlink_read_version_t* read_version)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tread_version->resp = mavlink_msg_read_version_get_resp(msg);\r\n\tmavlink_msg_read_version_get_param(msg, read_version->param);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_READ_VERSION_LEN? msg->len : MAVLINK_MSG_ID_READ_VERSION_LEN;\r\n        memset(read_version, 0, MAVLINK_MSG_ID_READ_VERSION_LEN);\r\n\tmemcpy(read_version, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld/msg/mavlink/opencr_msg/opencr_msg.h",
    "content": "/** @file\r\n *\t@brief MAVLink comm protocol generated from opencr_msg.xml\r\n *\t@see http://mavlink.org\r\n */\r\n#ifndef MAVLINK_OPENCR_MSG_H\r\n#define MAVLINK_OPENCR_MSG_H\r\n\r\n#ifndef MAVLINK_H\r\n    #error Wrong include order: MAVLINK_OPENCR_MSG.H MUST NOT BE DIRECTLY USED. Include mavlink.h from the same directory instead or set ALL AND EVERY defines from MAVLINK.H manually accordingly, including the #define MAVLINK_H call.\r\n#endif\r\n\r\n#ifdef __cplusplus\r\nextern \"C\" {\r\n#endif\r\n\r\n// MESSAGE LENGTHS AND CRCS\r\n\r\n#ifndef MAVLINK_MESSAGE_LENGTHS\r\n#define MAVLINK_MESSAGE_LENGTHS {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 20, 9, 9, 10, 9, 9, 132, 7, 13, 17, 134, 7, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}\r\n#endif\r\n\r\n#ifndef MAVLINK_MESSAGE_CRCS\r\n#define MAVLINK_MESSAGE_CRCS {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 192, 166, 140, 126, 8, 48, 233, 226, 13, 31, 9, 131, 37, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}\r\n#endif\r\n\r\n#ifndef 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{\"EMPTY\",0,{{\"\",\"\",MAVLINK_TYPE_CHAR,0,0,0}}}}\r\n#endif\r\n\r\n#include \"../protocol.h\"\r\n\r\n#define MAVLINK_ENABLED_OPENCR_MSG\r\n\r\n// ENUM DEFINITIONS\r\n\r\n\r\n\r\n// MAVLINK VERSION\r\n\r\n#ifndef MAVLINK_VERSION\r\n#define MAVLINK_VERSION 2\r\n#endif\r\n\r\n#if (MAVLINK_VERSION == 0)\r\n#undef MAVLINK_VERSION\r\n#define MAVLINK_VERSION 2\r\n#endif\r\n\r\n// MESSAGE DEFINITIONS\r\n#include \"./mavlink_msg_ack.h\"\r\n#include \"./mavlink_msg_read_version.h\"\r\n#include \"./mavlink_msg_read_board_name.h\"\r\n#include \"./mavlink_msg_read_tag.h\"\r\n#include \"./mavlink_msg_flash_fw_write_begin.h\"\r\n#include \"./mavlink_msg_flash_fw_write_end.h\"\r\n#include \"./mavlink_msg_flash_fw_write_packet.h\"\r\n#include \"./mavlink_msg_flash_fw_write_block.h\"\r\n#include \"./mavlink_msg_flash_fw_erase.h\"\r\n#include \"./mavlink_msg_flash_fw_verify.h\"\r\n#include \"./mavlink_msg_flash_fw_read_packet.h\"\r\n#include \"./mavlink_msg_flash_fw_read_block.h\"\r\n#include \"./mavlink_msg_jump_to_fw.h\"\r\n\r\n// base include\r\n\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#include \"../mavlink_get_info.h\"\r\n#endif\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif // __cplusplus\r\n#endif // MAVLINK_OPENCR_MSG_H\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld/msg/mavlink/opencr_msg/testsuite.h",
    "content": "/** @file\r\n *\t@brief MAVLink comm protocol testsuite generated from opencr_msg.xml\r\n *\t@see http://qgroundcontrol.org/mavlink/\r\n */\r\n#ifndef OPENCR_MSG_TESTSUITE_H\r\n#define OPENCR_MSG_TESTSUITE_H\r\n\r\n#ifdef __cplusplus\r\nextern \"C\" {\r\n#endif\r\n\r\n#ifndef MAVLINK_TEST_ALL\r\n#define MAVLINK_TEST_ALL\r\n\r\nstatic void mavlink_test_opencr_msg(uint8_t, uint8_t, mavlink_message_t *last_msg);\r\n\r\nstatic void mavlink_test_all(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n\r\n\tmavlink_test_opencr_msg(system_id, component_id, last_msg);\r\n}\r\n#endif\r\n\r\n\r\n\r\n\r\nstatic void mavlink_test_ack(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_ACK >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_ack_t packet_in = {\r\n\t\t17235,139,206,{ 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 }\r\n    };\r\n\tmavlink_ack_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.err_code = packet_in.err_code;\r\n        packet1.msg_id = packet_in.msg_id;\r\n        packet1.length = packet_in.length;\r\n        \r\n        mav_array_memcpy(packet1.data, packet_in.data, sizeof(uint8_t)*16);\r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_ack_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_ack_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_ack_pack(system_id, component_id, &msg , packet1.msg_id , packet1.err_code , packet1.length , packet1.data );\r\n\tmavlink_msg_ack_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_ack_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.msg_id , packet1.err_code , packet1.length , packet1.data );\r\n\tmavlink_msg_ack_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_ack_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_ack_send(MAVLINK_COMM_1 , packet1.msg_id , packet1.err_code , packet1.length , packet1.data );\r\n\tmavlink_msg_ack_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_read_version(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_READ_VERSION >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_read_version_t packet_in = {\r\n\t\t5,{ 72, 73, 74, 75, 76, 77, 78, 79 }\r\n    };\r\n\tmavlink_read_version_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.resp = packet_in.resp;\r\n        \r\n        mav_array_memcpy(packet1.param, packet_in.param, sizeof(uint8_t)*8);\r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_version_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_read_version_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_version_pack(system_id, component_id, &msg , packet1.resp , packet1.param );\r\n\tmavlink_msg_read_version_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_version_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.param );\r\n\tmavlink_msg_read_version_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_read_version_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_version_send(MAVLINK_COMM_1 , packet1.resp , packet1.param );\r\n\tmavlink_msg_read_version_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_read_board_name(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_READ_BOARD_NAME >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_read_board_name_t packet_in = {\r\n\t\t5,{ 72, 73, 74, 75, 76, 77, 78, 79 }\r\n    };\r\n\tmavlink_read_board_name_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.resp = packet_in.resp;\r\n        \r\n        mav_array_memcpy(packet1.param, packet_in.param, sizeof(uint8_t)*8);\r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_board_name_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_read_board_name_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_board_name_pack(system_id, component_id, &msg , packet1.resp , packet1.param );\r\n\tmavlink_msg_read_board_name_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_board_name_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.param );\r\n\tmavlink_msg_read_board_name_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_read_board_name_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_board_name_send(MAVLINK_COMM_1 , packet1.resp , packet1.param );\r\n\tmavlink_msg_read_board_name_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_read_tag(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_READ_TAG >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_read_tag_t packet_in = {\r\n\t\t5,72,{ 139, 140, 141, 142, 143, 144, 145, 146 }\r\n    };\r\n\tmavlink_read_tag_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.resp = packet_in.resp;\r\n        packet1.type = packet_in.type;\r\n        \r\n        mav_array_memcpy(packet1.param, packet_in.param, sizeof(uint8_t)*8);\r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_tag_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_read_tag_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_tag_pack(system_id, component_id, &msg , packet1.resp , packet1.type , packet1.param );\r\n\tmavlink_msg_read_tag_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_tag_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.type , packet1.param );\r\n\tmavlink_msg_read_tag_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_read_tag_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_tag_send(MAVLINK_COMM_1 , packet1.resp , packet1.type , packet1.param );\r\n\tmavlink_msg_read_tag_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_flash_fw_write_begin(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_flash_fw_write_begin_t packet_in = {\r\n\t\t5,{ 72, 73, 74, 75, 76, 77, 78, 79 }\r\n    };\r\n\tmavlink_flash_fw_write_begin_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.resp = packet_in.resp;\r\n        \r\n        mav_array_memcpy(packet1.param, packet_in.param, sizeof(uint8_t)*8);\r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_begin_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_flash_fw_write_begin_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_begin_pack(system_id, component_id, &msg , packet1.resp , packet1.param );\r\n\tmavlink_msg_flash_fw_write_begin_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_begin_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.param );\r\n\tmavlink_msg_flash_fw_write_begin_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_flash_fw_write_begin_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_begin_send(MAVLINK_COMM_1 , packet1.resp , packet1.param );\r\n\tmavlink_msg_flash_fw_write_begin_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_flash_fw_write_end(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_FLASH_FW_WRITE_END >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_flash_fw_write_end_t packet_in = {\r\n\t\t5,{ 72, 73, 74, 75, 76, 77, 78, 79 }\r\n    };\r\n\tmavlink_flash_fw_write_end_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.resp = packet_in.resp;\r\n        \r\n        mav_array_memcpy(packet1.param, packet_in.param, sizeof(uint8_t)*8);\r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_end_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_flash_fw_write_end_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_end_pack(system_id, component_id, &msg , packet1.resp , packet1.param );\r\n\tmavlink_msg_flash_fw_write_end_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_end_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.param );\r\n\tmavlink_msg_flash_fw_write_end_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_flash_fw_write_end_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_end_send(MAVLINK_COMM_1 , packet1.resp , packet1.param );\r\n\tmavlink_msg_flash_fw_write_end_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_flash_fw_write_packet(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_flash_fw_write_packet_t packet_in = {\r\n\t\t17235,139,206,{ 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144 }\r\n    };\r\n\tmavlink_flash_fw_write_packet_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.addr = packet_in.addr;\r\n        packet1.resp = packet_in.resp;\r\n        packet1.length = packet_in.length;\r\n        \r\n        mav_array_memcpy(packet1.data, packet_in.data, sizeof(uint8_t)*128);\r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_packet_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_flash_fw_write_packet_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_packet_pack(system_id, component_id, &msg , packet1.resp , packet1.addr , packet1.length , packet1.data );\r\n\tmavlink_msg_flash_fw_write_packet_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_packet_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.addr , packet1.length , packet1.data );\r\n\tmavlink_msg_flash_fw_write_packet_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_flash_fw_write_packet_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_packet_send(MAVLINK_COMM_1 , packet1.resp , packet1.addr , packet1.length , packet1.data );\r\n\tmavlink_msg_flash_fw_write_packet_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_flash_fw_write_block(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_flash_fw_write_block_t packet_in = {\r\n\t\t963497464,17443,151\r\n    };\r\n\tmavlink_flash_fw_write_block_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.addr = packet_in.addr;\r\n        packet1.length = packet_in.length;\r\n        packet1.resp = packet_in.resp;\r\n        \r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_block_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_flash_fw_write_block_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_block_pack(system_id, component_id, &msg , packet1.resp , packet1.addr , packet1.length );\r\n\tmavlink_msg_flash_fw_write_block_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_block_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.addr , packet1.length );\r\n\tmavlink_msg_flash_fw_write_block_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_flash_fw_write_block_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_block_send(MAVLINK_COMM_1 , packet1.resp , packet1.addr , packet1.length );\r\n\tmavlink_msg_flash_fw_write_block_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_flash_fw_erase(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_FLASH_FW_ERASE >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_flash_fw_erase_t packet_in = {\r\n\t\t963497464,17,{ 84, 85, 86, 87, 88, 89, 90, 91 }\r\n    };\r\n\tmavlink_flash_fw_erase_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.length = packet_in.length;\r\n        packet1.resp = packet_in.resp;\r\n        \r\n        mav_array_memcpy(packet1.param, packet_in.param, sizeof(uint8_t)*8);\r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_erase_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_flash_fw_erase_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_erase_pack(system_id, component_id, &msg , packet1.resp , packet1.length , packet1.param );\r\n\tmavlink_msg_flash_fw_erase_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_erase_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.length , packet1.param );\r\n\tmavlink_msg_flash_fw_erase_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_flash_fw_erase_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_erase_send(MAVLINK_COMM_1 , packet1.resp , packet1.length , packet1.param );\r\n\tmavlink_msg_flash_fw_erase_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_flash_fw_verify(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_FLASH_FW_VERIFY >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_flash_fw_verify_t packet_in = {\r\n\t\t963497464,963497672,29,{ 96, 97, 98, 99, 100, 101, 102, 103 }\r\n    };\r\n\tmavlink_flash_fw_verify_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.length = packet_in.length;\r\n        packet1.crc = packet_in.crc;\r\n        packet1.resp = packet_in.resp;\r\n        \r\n        mav_array_memcpy(packet1.param, packet_in.param, sizeof(uint8_t)*8);\r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_verify_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_flash_fw_verify_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_verify_pack(system_id, component_id, &msg , packet1.resp , packet1.length , packet1.crc , packet1.param );\r\n\tmavlink_msg_flash_fw_verify_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_verify_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.length , packet1.crc , packet1.param );\r\n\tmavlink_msg_flash_fw_verify_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_flash_fw_verify_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_verify_send(MAVLINK_COMM_1 , packet1.resp , packet1.length , packet1.crc , packet1.param );\r\n\tmavlink_msg_flash_fw_verify_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_flash_fw_read_packet(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_FLASH_FW_READ_PACKET >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_flash_fw_read_packet_t packet_in = {\r\n\t\t963497464,17,84,{ 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22 }\r\n    };\r\n\tmavlink_flash_fw_read_packet_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.addr = packet_in.addr;\r\n        packet1.resp = packet_in.resp;\r\n        packet1.length = packet_in.length;\r\n        \r\n        mav_array_memcpy(packet1.data, packet_in.data, sizeof(uint8_t)*128);\r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_read_packet_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_flash_fw_read_packet_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_read_packet_pack(system_id, component_id, &msg , packet1.resp , packet1.addr , packet1.length , packet1.data );\r\n\tmavlink_msg_flash_fw_read_packet_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_read_packet_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.addr , packet1.length , packet1.data );\r\n\tmavlink_msg_flash_fw_read_packet_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_flash_fw_read_packet_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_read_packet_send(MAVLINK_COMM_1 , packet1.resp , packet1.addr , packet1.length , packet1.data );\r\n\tmavlink_msg_flash_fw_read_packet_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_flash_fw_read_block(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_flash_fw_read_block_t packet_in = {\r\n\t\t963497464,17443,151\r\n    };\r\n\tmavlink_flash_fw_read_block_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.addr = packet_in.addr;\r\n        packet1.length = packet_in.length;\r\n        packet1.resp = packet_in.resp;\r\n        \r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_read_block_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_flash_fw_read_block_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_read_block_pack(system_id, component_id, &msg , packet1.resp , packet1.addr , packet1.length );\r\n\tmavlink_msg_flash_fw_read_block_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_read_block_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.addr , packet1.length );\r\n\tmavlink_msg_flash_fw_read_block_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_flash_fw_read_block_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_read_block_send(MAVLINK_COMM_1 , packet1.resp , packet1.addr , packet1.length );\r\n\tmavlink_msg_flash_fw_read_block_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_jump_to_fw(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_JUMP_TO_FW >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_jump_to_fw_t packet_in = {\r\n\t\t5,{ 72, 73, 74, 75, 76, 77, 78, 79 }\r\n    };\r\n\tmavlink_jump_to_fw_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.resp = packet_in.resp;\r\n        \r\n        mav_array_memcpy(packet1.param, packet_in.param, sizeof(uint8_t)*8);\r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_jump_to_fw_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_jump_to_fw_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_jump_to_fw_pack(system_id, component_id, &msg , packet1.resp , packet1.param );\r\n\tmavlink_msg_jump_to_fw_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_jump_to_fw_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.param );\r\n\tmavlink_msg_jump_to_fw_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_jump_to_fw_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_jump_to_fw_send(MAVLINK_COMM_1 , packet1.resp , packet1.param );\r\n\tmavlink_msg_jump_to_fw_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_opencr_msg(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n\tmavlink_test_ack(system_id, component_id, last_msg);\r\n\tmavlink_test_read_version(system_id, component_id, last_msg);\r\n\tmavlink_test_read_board_name(system_id, component_id, last_msg);\r\n\tmavlink_test_read_tag(system_id, component_id, last_msg);\r\n\tmavlink_test_flash_fw_write_begin(system_id, component_id, last_msg);\r\n\tmavlink_test_flash_fw_write_end(system_id, component_id, last_msg);\r\n\tmavlink_test_flash_fw_write_packet(system_id, component_id, last_msg);\r\n\tmavlink_test_flash_fw_write_block(system_id, component_id, last_msg);\r\n\tmavlink_test_flash_fw_erase(system_id, component_id, last_msg);\r\n\tmavlink_test_flash_fw_verify(system_id, component_id, last_msg);\r\n\tmavlink_test_flash_fw_read_packet(system_id, component_id, last_msg);\r\n\tmavlink_test_flash_fw_read_block(system_id, component_id, last_msg);\r\n\tmavlink_test_jump_to_fw(system_id, component_id, last_msg);\r\n}\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif // __cplusplus\r\n#endif // OPENCR_MSG_TESTSUITE_H\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld/msg/mavlink/opencr_msg/version.h",
    "content": "/** @file\r\n *\t@brief MAVLink comm protocol built from opencr_msg.xml\r\n *\t@see http://mavlink.org\r\n */\r\n#ifndef MAVLINK_VERSION_H\r\n#define MAVLINK_VERSION_H\r\n\r\n#define MAVLINK_BUILD_DATE \"Mon May 30 2016\"\r\n#define MAVLINK_WIRE_PROTOCOL_VERSION \"1.0\"\r\n#define MAVLINK_MAX_DIALECT_PAYLOAD_SIZE 134\r\n \r\n#endif // MAVLINK_VERSION_H\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld/msg/mavlink/protocol.h",
    "content": "#ifndef  _MAVLINK_PROTOCOL_H_\r\n#define  _MAVLINK_PROTOCOL_H_\r\n\r\n#include \"string.h\"\r\n#include \"mavlink_types.h\"\r\n\r\n/* \r\n   If you want MAVLink on a system that is native big-endian,\r\n   you need to define NATIVE_BIG_ENDIAN\r\n*/\r\n#ifdef NATIVE_BIG_ENDIAN\r\n# define MAVLINK_NEED_BYTE_SWAP (MAVLINK_ENDIAN == MAVLINK_LITTLE_ENDIAN)\r\n#else\r\n# define MAVLINK_NEED_BYTE_SWAP (MAVLINK_ENDIAN != MAVLINK_LITTLE_ENDIAN)\r\n#endif\r\n\r\n#ifndef MAVLINK_STACK_BUFFER\r\n#define MAVLINK_STACK_BUFFER 0\r\n#endif\r\n\r\n#ifndef MAVLINK_AVOID_GCC_STACK_BUG\r\n# define MAVLINK_AVOID_GCC_STACK_BUG defined(__GNUC__)\r\n#endif\r\n\r\n#ifndef MAVLINK_ASSERT\r\n#define MAVLINK_ASSERT(x)\r\n#endif\r\n\r\n#ifndef MAVLINK_START_UART_SEND\r\n#define MAVLINK_START_UART_SEND(chan, length)\r\n#endif\r\n\r\n#ifndef MAVLINK_END_UART_SEND\r\n#define MAVLINK_END_UART_SEND(chan, length)\r\n#endif\r\n\r\n/* option to provide alternative implementation of mavlink_helpers.h */\r\n#ifdef MAVLINK_SEPARATE_HELPERS\r\n\r\n    #define MAVLINK_HELPER\r\n\r\n    /* decls in sync with those in mavlink_helpers.h */\r\n    #ifndef MAVLINK_GET_CHANNEL_STATUS\r\n    MAVLINK_HELPER mavlink_status_t* mavlink_get_channel_status(uint8_t chan);\r\n    #endif\r\n    MAVLINK_HELPER void mavlink_reset_channel_status(uint8_t chan);\r\n    #if MAVLINK_CRC_EXTRA\r\n    MAVLINK_HELPER uint16_t mavlink_finalize_message_chan(mavlink_message_t* msg, uint8_t system_id, uint8_t component_id,\r\n                                                          uint8_t chan, uint8_t min_length, uint8_t length, uint8_t crc_extra);\r\n    MAVLINK_HELPER uint16_t mavlink_finalize_message(mavlink_message_t* msg, uint8_t system_id, uint8_t component_id,\r\n                                                     uint8_t min_length, uint8_t length, uint8_t crc_extra);\r\n    #ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n    MAVLINK_HELPER void _mav_finalize_message_chan_send(mavlink_channel_t chan, uint8_t msgid, const char *packet,\r\n                                                        uint8_t min_length, uint8_t length, uint8_t crc_extra);\r\n    #endif\r\n    #else\r\n    MAVLINK_HELPER uint16_t mavlink_finalize_message_chan(mavlink_message_t* msg, uint8_t system_id, uint8_t component_id,\r\n                                                          uint8_t chan, uint8_t length);\r\n    MAVLINK_HELPER uint16_t mavlink_finalize_message(mavlink_message_t* msg, uint8_t system_id, uint8_t component_id,\r\n                                                     uint8_t length);\r\n    #ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n    MAVLINK_HELPER void _mav_finalize_message_chan_send(mavlink_channel_t chan, uint8_t msgid, const char *packet, uint8_t length);\r\n    #endif\r\n    #endif // MAVLINK_CRC_EXTRA\r\n    MAVLINK_HELPER uint16_t mavlink_msg_to_send_buffer(uint8_t *buffer, const mavlink_message_t *msg);\r\n    MAVLINK_HELPER void mavlink_start_checksum(mavlink_message_t* msg);\r\n    MAVLINK_HELPER void mavlink_update_checksum(mavlink_message_t* msg, uint8_t c);\r\n    MAVLINK_HELPER uint8_t mavlink_frame_char_buffer(mavlink_message_t* rxmsg, \r\n\t\t\t\t\t\t     mavlink_status_t* status,\r\n\t\t\t\t\t\t     uint8_t c, \r\n\t\t\t\t\t\t     mavlink_message_t* r_message, \r\n\t\t\t\t\t\t     mavlink_status_t* r_mavlink_status);\r\n    MAVLINK_HELPER uint8_t mavlink_frame_char(uint8_t chan, uint8_t c, mavlink_message_t* r_message, mavlink_status_t* r_mavlink_status);\r\n    MAVLINK_HELPER uint8_t mavlink_parse_char(uint8_t chan, uint8_t c, mavlink_message_t* r_message, mavlink_status_t* r_mavlink_status);\r\n    MAVLINK_HELPER uint8_t put_bitfield_n_by_index(int32_t b, uint8_t bits, uint8_t packet_index, uint8_t bit_index,\r\n                               uint8_t* r_bit_index, uint8_t* buffer);\r\n    #ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n    MAVLINK_HELPER void _mavlink_send_uart(mavlink_channel_t chan, const char *buf, uint16_t len);\r\n    MAVLINK_HELPER void _mavlink_resend_uart(mavlink_channel_t chan, const mavlink_message_t *msg);\r\n    #endif\r\n\r\n#else\r\n\r\n    #define MAVLINK_HELPER static inline\r\n    #include \"mavlink_helpers.h\"\r\n\r\n#endif // MAVLINK_SEPARATE_HELPERS\r\n\r\n/**\r\n * @brief Get the required buffer size for this message\r\n */\r\nstatic inline uint16_t mavlink_msg_get_send_buffer_length(const mavlink_message_t* msg)\r\n{\r\n\treturn msg->len + MAVLINK_NUM_NON_PAYLOAD_BYTES;\r\n}\r\n\r\n#if MAVLINK_NEED_BYTE_SWAP\r\nstatic inline void byte_swap_2(char *dst, const char *src)\r\n{\r\n\tdst[0] = src[1];\r\n\tdst[1] = src[0];\r\n}\r\nstatic inline void byte_swap_4(char *dst, const char *src)\r\n{\r\n\tdst[0] = src[3];\r\n\tdst[1] = src[2];\r\n\tdst[2] = src[1];\r\n\tdst[3] = src[0];\r\n}\r\nstatic inline void byte_swap_8(char *dst, const char *src)\r\n{\r\n\tdst[0] = src[7];\r\n\tdst[1] = src[6];\r\n\tdst[2] = src[5];\r\n\tdst[3] = src[4];\r\n\tdst[4] = src[3];\r\n\tdst[5] = src[2];\r\n\tdst[6] = src[1];\r\n\tdst[7] = src[0];\r\n}\r\n#elif !MAVLINK_ALIGNED_FIELDS\r\nstatic inline void byte_copy_2(char *dst, const char *src)\r\n{\r\n\tdst[0] = src[0];\r\n\tdst[1] = src[1];\r\n}\r\nstatic inline void byte_copy_4(char *dst, const char *src)\r\n{\r\n\tdst[0] = src[0];\r\n\tdst[1] = src[1];\r\n\tdst[2] = src[2];\r\n\tdst[3] = src[3];\r\n}\r\nstatic inline void byte_copy_8(char *dst, const char *src)\r\n{\r\n\tmemcpy(dst, src, 8);\r\n}\r\n#endif\r\n\r\n#define _mav_put_uint8_t(buf, wire_offset, b) buf[wire_offset] = (uint8_t)b\r\n#define _mav_put_int8_t(buf, wire_offset, b)  buf[wire_offset] = (int8_t)b\r\n#define _mav_put_char(buf, wire_offset, b)    buf[wire_offset] = b\r\n\r\n#if MAVLINK_NEED_BYTE_SWAP\r\n#define _mav_put_uint16_t(buf, wire_offset, b) byte_swap_2(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_int16_t(buf, wire_offset, b)  byte_swap_2(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_uint32_t(buf, wire_offset, b) byte_swap_4(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_int32_t(buf, wire_offset, b)  byte_swap_4(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_uint64_t(buf, wire_offset, b) byte_swap_8(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_int64_t(buf, wire_offset, b)  byte_swap_8(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_float(buf, wire_offset, b)    byte_swap_4(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_double(buf, wire_offset, b)   byte_swap_8(&buf[wire_offset], (const char *)&b)\r\n#elif !MAVLINK_ALIGNED_FIELDS\r\n#define _mav_put_uint16_t(buf, wire_offset, b) byte_copy_2(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_int16_t(buf, wire_offset, b)  byte_copy_2(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_uint32_t(buf, wire_offset, b) byte_copy_4(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_int32_t(buf, wire_offset, b)  byte_copy_4(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_uint64_t(buf, wire_offset, b) byte_copy_8(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_int64_t(buf, wire_offset, b)  byte_copy_8(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_float(buf, wire_offset, b)    byte_copy_4(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_double(buf, wire_offset, b)   byte_copy_8(&buf[wire_offset], (const char *)&b)\r\n#else\r\n#define _mav_put_uint16_t(buf, wire_offset, b) *(uint16_t *)&buf[wire_offset] = b\r\n#define _mav_put_int16_t(buf, wire_offset, b)  *(int16_t *)&buf[wire_offset] = b\r\n#define _mav_put_uint32_t(buf, wire_offset, b) *(uint32_t *)&buf[wire_offset] = b\r\n#define _mav_put_int32_t(buf, wire_offset, b)  *(int32_t *)&buf[wire_offset] = b\r\n#define _mav_put_uint64_t(buf, wire_offset, b) *(uint64_t *)&buf[wire_offset] = b\r\n#define _mav_put_int64_t(buf, wire_offset, b)  *(int64_t *)&buf[wire_offset] = b\r\n#define _mav_put_float(buf, wire_offset, b)    *(float *)&buf[wire_offset] = b\r\n#define _mav_put_double(buf, wire_offset, b)   *(double *)&buf[wire_offset] = b\r\n#endif\r\n\r\n/*\r\n  like memcpy(), but if src is NULL, do a memset to zero\r\n*/\r\nstatic inline void mav_array_memcpy(void *dest, const void *src, size_t n)\r\n{\r\n\tif (src == NULL) {\r\n\t\tmemset(dest, 0, n);\r\n\t} else {\r\n\t\tmemcpy(dest, src, n);\r\n\t}\r\n}\r\n\r\n/*\r\n * Place a char array into a buffer\r\n */\r\nstatic inline void _mav_put_char_array(char *buf, uint8_t wire_offset, const char *b, uint8_t array_length)\r\n{\r\n\tmav_array_memcpy(&buf[wire_offset], b, array_length);\r\n\r\n}\r\n\r\n/*\r\n * Place a uint8_t array into a buffer\r\n */\r\nstatic inline void _mav_put_uint8_t_array(char *buf, uint8_t wire_offset, const uint8_t *b, uint8_t array_length)\r\n{\r\n\tmav_array_memcpy(&buf[wire_offset], b, array_length);\r\n\r\n}\r\n\r\n/*\r\n * Place a int8_t array into a buffer\r\n */\r\nstatic inline void _mav_put_int8_t_array(char *buf, uint8_t wire_offset, const int8_t *b, uint8_t array_length)\r\n{\r\n\tmav_array_memcpy(&buf[wire_offset], b, array_length);\r\n\r\n}\r\n\r\n#if MAVLINK_NEED_BYTE_SWAP\r\n#define _MAV_PUT_ARRAY(TYPE, V) \\\r\nstatic inline void _mav_put_ ## TYPE ##_array(char *buf, uint8_t wire_offset, const TYPE *b, uint8_t array_length) \\\r\n{ \\\r\n\tif (b == NULL) { \\\r\n\t\tmemset(&buf[wire_offset], 0, array_length*sizeof(TYPE)); \\\r\n\t} else { \\\r\n\t\tuint16_t i; \\\r\n\t\tfor (i=0; i<array_length; i++) { \\\r\n\t\t\t_mav_put_## TYPE (buf, wire_offset+(i*sizeof(TYPE)), b[i]); \\\r\n\t\t} \\\r\n\t} \\\r\n}\r\n#else\r\n#define _MAV_PUT_ARRAY(TYPE, V)\t\t\t\t\t\\\r\nstatic inline void _mav_put_ ## TYPE ##_array(char *buf, uint8_t wire_offset, const TYPE *b, uint8_t array_length) \\\r\n{ \\\r\n\tmav_array_memcpy(&buf[wire_offset], b, array_length*sizeof(TYPE)); \\\r\n}\r\n#endif\r\n\r\n_MAV_PUT_ARRAY(uint16_t, u16)\r\n_MAV_PUT_ARRAY(uint32_t, u32)\r\n_MAV_PUT_ARRAY(uint64_t, u64)\r\n_MAV_PUT_ARRAY(int16_t,  i16)\r\n_MAV_PUT_ARRAY(int32_t,  i32)\r\n_MAV_PUT_ARRAY(int64_t,  i64)\r\n_MAV_PUT_ARRAY(float,    f)\r\n_MAV_PUT_ARRAY(double,   d)\r\n\r\n#define _MAV_RETURN_char(msg, wire_offset)             (const char)_MAV_PAYLOAD(msg)[wire_offset]\r\n#define _MAV_RETURN_int8_t(msg, wire_offset)   (const int8_t)_MAV_PAYLOAD(msg)[wire_offset]\r\n#define _MAV_RETURN_uint8_t(msg, wire_offset) (const uint8_t)_MAV_PAYLOAD(msg)[wire_offset]\r\n\r\n#if MAVLINK_NEED_BYTE_SWAP\r\n#define _MAV_MSG_RETURN_TYPE(TYPE, SIZE) \\\r\nstatic inline TYPE _MAV_RETURN_## TYPE(const mavlink_message_t *msg, uint8_t ofs) \\\r\n{ TYPE r; byte_swap_## SIZE((char*)&r, &_MAV_PAYLOAD(msg)[ofs]); return r; }\r\n\r\n_MAV_MSG_RETURN_TYPE(uint16_t, 2)\r\n_MAV_MSG_RETURN_TYPE(int16_t,  2)\r\n_MAV_MSG_RETURN_TYPE(uint32_t, 4)\r\n_MAV_MSG_RETURN_TYPE(int32_t,  4)\r\n_MAV_MSG_RETURN_TYPE(uint64_t, 8)\r\n_MAV_MSG_RETURN_TYPE(int64_t,  8)\r\n_MAV_MSG_RETURN_TYPE(float,    4)\r\n_MAV_MSG_RETURN_TYPE(double,   8)\r\n\r\n#elif !MAVLINK_ALIGNED_FIELDS\r\n#define _MAV_MSG_RETURN_TYPE(TYPE, SIZE) \\\r\nstatic inline TYPE _MAV_RETURN_## TYPE(const mavlink_message_t *msg, uint8_t ofs) \\\r\n{ TYPE r; byte_copy_## SIZE((char*)&r, &_MAV_PAYLOAD(msg)[ofs]); return r; }\r\n\r\n_MAV_MSG_RETURN_TYPE(uint16_t, 2)\r\n_MAV_MSG_RETURN_TYPE(int16_t,  2)\r\n_MAV_MSG_RETURN_TYPE(uint32_t, 4)\r\n_MAV_MSG_RETURN_TYPE(int32_t,  4)\r\n_MAV_MSG_RETURN_TYPE(uint64_t, 8)\r\n_MAV_MSG_RETURN_TYPE(int64_t,  8)\r\n_MAV_MSG_RETURN_TYPE(float,    4)\r\n_MAV_MSG_RETURN_TYPE(double,   8)\r\n#else // nicely aligned, no swap\r\n#define _MAV_MSG_RETURN_TYPE(TYPE) \\\r\nstatic inline TYPE _MAV_RETURN_## TYPE(const mavlink_message_t *msg, uint8_t ofs) \\\r\n{ return *(const TYPE *)(&_MAV_PAYLOAD(msg)[ofs]);}\r\n\r\n_MAV_MSG_RETURN_TYPE(uint16_t)\r\n_MAV_MSG_RETURN_TYPE(int16_t)\r\n_MAV_MSG_RETURN_TYPE(uint32_t)\r\n_MAV_MSG_RETURN_TYPE(int32_t)\r\n_MAV_MSG_RETURN_TYPE(uint64_t)\r\n_MAV_MSG_RETURN_TYPE(int64_t)\r\n_MAV_MSG_RETURN_TYPE(float)\r\n_MAV_MSG_RETURN_TYPE(double)\r\n#endif // MAVLINK_NEED_BYTE_SWAP\r\n\r\nstatic inline uint16_t _MAV_RETURN_char_array(const mavlink_message_t *msg, char *value, \r\n\t\t\t\t\t\t     uint8_t array_length, uint8_t wire_offset)\r\n{\r\n\tmemcpy(value, &_MAV_PAYLOAD(msg)[wire_offset], array_length);\r\n\treturn array_length;\r\n}\r\n\r\nstatic inline uint16_t _MAV_RETURN_uint8_t_array(const mavlink_message_t *msg, uint8_t *value, \r\n\t\t\t\t\t\t\tuint8_t array_length, uint8_t wire_offset)\r\n{\r\n\tmemcpy(value, &_MAV_PAYLOAD(msg)[wire_offset], array_length);\r\n\treturn array_length;\r\n}\r\n\r\nstatic inline uint16_t _MAV_RETURN_int8_t_array(const mavlink_message_t *msg, int8_t *value, \r\n\t\t\t\t\t\t       uint8_t array_length, uint8_t wire_offset)\r\n{\r\n\tmemcpy(value, &_MAV_PAYLOAD(msg)[wire_offset], array_length);\r\n\treturn array_length;\r\n}\r\n\r\n#if MAVLINK_NEED_BYTE_SWAP\r\n#define _MAV_RETURN_ARRAY(TYPE, V) \\\r\nstatic inline uint16_t _MAV_RETURN_## TYPE ##_array(const mavlink_message_t *msg, TYPE *value, \\\r\n\t\t\t\t\t\t\t uint8_t array_length, uint8_t wire_offset) \\\r\n{ \\\r\n\tuint16_t i; \\\r\n\tfor (i=0; i<array_length; i++) { \\\r\n\t\tvalue[i] = _MAV_RETURN_## TYPE (msg, wire_offset+(i*sizeof(value[0]))); \\\r\n\t} \\\r\n\treturn array_length*sizeof(value[0]); \\\r\n}\r\n#else\r\n#define _MAV_RETURN_ARRAY(TYPE, V)\t\t\t\t\t\\\r\nstatic inline uint16_t _MAV_RETURN_## TYPE ##_array(const mavlink_message_t *msg, TYPE *value, \\\r\n\t\t\t\t\t\t\t uint8_t array_length, uint8_t wire_offset) \\\r\n{ \\\r\n\tmemcpy(value, &_MAV_PAYLOAD(msg)[wire_offset], array_length*sizeof(TYPE)); \\\r\n\treturn array_length*sizeof(TYPE); \\\r\n}\r\n#endif\r\n\r\n_MAV_RETURN_ARRAY(uint16_t, u16)\r\n_MAV_RETURN_ARRAY(uint32_t, u32)\r\n_MAV_RETURN_ARRAY(uint64_t, u64)\r\n_MAV_RETURN_ARRAY(int16_t,  i16)\r\n_MAV_RETURN_ARRAY(int32_t,  i32)\r\n_MAV_RETURN_ARRAY(int64_t,  i64)\r\n_MAV_RETURN_ARRAY(float,    f)\r\n_MAV_RETURN_ARRAY(double,   d)\r\n\r\n#endif // _MAVLINK_PROTOCOL_H_\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld/msg/msg.c",
    "content": "/*\r\n *  msg.c\r\n *\r\n *  message process\r\n *\r\n *  Created on: 2016. 5. 14.\r\n *      Author: Baram, PBPH\r\n */\r\n\r\n#include \"msg.h\"\r\n#include <math.h>\r\n#include <string.h>\r\n#include <stdarg.h>\r\n#include <stdio.h>\r\n#include \"../serial.h\"\r\n\r\n\r\nextern ser_handler stm32_ser_id;\r\nextern int read_byte( void );\r\nextern int write_bytes( char *p_data, int len );\r\n\r\n\r\n\r\nvoid msg_init(void)\r\n{\r\n\r\n}\r\n\r\n\r\nvoid msg_send(uint8_t chan, mavlink_message_t *p_msg)\r\n{\r\n  uint8_t  buf[1024];\r\n  uint16_t len;\r\n  uint16_t write_len;\r\n\r\n  len = mavlink_msg_to_send_buffer(buf, p_msg);\r\n\r\n  switch(chan)\r\n  {\r\n    case 0:\r\n      write_len = write_bytes((char *)buf, (uint32_t)len);\r\n#ifndef WIN32_BUILD\r\n      if( write_len != len ) printf(\"wlen %d : len %d\\r\\n\", write_len, len);\r\n#endif\r\n      break;\r\n\r\n    case 1:\r\n      break;\r\n  }\r\n}\r\n\r\n\r\nBOOL msg_recv( uint8_t chan, uint8_t data , mavlink_message_t *p_msg, mavlink_status_t *p_status )\r\n{\r\n  BOOL ret = FALSE;\r\n\r\n\r\n  if(chan == 0)\r\n  {\r\n    if (mavlink_parse_char(MAVLINK_COMM_0, data, p_msg, p_status) == MAVLINK_FRAMING_OK)\r\n    {\r\n      ret = TRUE;\r\n    }\r\n  }\r\n  else\r\n  {\r\n    if (mavlink_parse_char(MAVLINK_COMM_1, data, p_msg, p_status) == MAVLINK_FRAMING_OK)\r\n    {\r\n      ret = TRUE;\r\n    }\r\n  }\r\n\r\n  return ret;\r\n}\r\n\r\n\r\nBOOL msg_get_resp( uint8_t chan, mavlink_message_t *p_msg, uint32_t timeout)\r\n{\r\n  BOOL ret = FALSE;\r\n  //int  ch_ret;\r\n  int  length;\r\n  int  i;\r\n  uint8_t ch_buff[128];\r\n  uint8_t ch;\r\n  static mavlink_message_t msg[MSG_CH_MAX];\r\n  static mavlink_status_t status[MSG_CH_MAX];\r\n  int retry = timeout;\r\n\r\n\r\n#ifndef WIN32_BUILD\r\n  retry = timeout/100;\r\n  ser_set_timeout_ms( stm32_ser_id, 100 );\r\n  while(1)\r\n  {\r\n    length = read_bytes( ch_buff, 128 );\r\n\r\n    if( length <= 0 )\r\n    {\r\n      if( retry-- <= 0 )\r\n      {\r\n        ret = FALSE;\r\n        break;\r\n      }\r\n      else\r\n      {\r\n        continue;\r\n      }\r\n    }\r\n\r\n    for( i=0; i<length; i++ )\r\n    {\r\n      ch = ch_buff[i];\r\n      ret = msg_recv( chan, ch, &msg[chan], &status[chan] );\r\n\r\n      if( ret == TRUE )\r\n      {\r\n        *p_msg = msg[chan];\r\n        return ret;\r\n      }\r\n    }\r\n  }\r\n#else\r\n  int  ch_ret;\r\n  ser_set_timeout_ms( stm32_ser_id, 1 );\r\n\r\n  while(1)\r\n  {\r\n    ch_ret = read_byte();\r\n    if( ch_ret < 0 )\r\n    {\r\n      if( retry-- <= 0 )\r\n      {\r\n        ret = FALSE;\r\n        break;\r\n      }\r\n      else\r\n      {\r\n        continue;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      ch = (uint8_t)(ch_ret);\r\n      retry = timeout;\r\n    }\r\n\r\n    ret = msg_recv( chan, ch, &msg[chan], &status[chan] );\r\n\r\n    if( ret == TRUE )\r\n    {\r\n      *p_msg = msg[chan];\r\n      break;\r\n    }\r\n  }\r\n#endif\r\n\r\n  return ret;\r\n}\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld/msg/msg.h",
    "content": "/*\r\n *  msg.h\r\n *\r\n *  message process\r\n *\r\n *  Created on: 2016. 5. 14.\r\n *      Author: Baram, PBPH\r\n */\r\n\r\n#ifndef MSG_H\r\n#define MSG_H\r\n\r\n\r\n#ifdef __cplusplus\r\n extern \"C\" {\r\n#endif\r\n\r\n\r\n#include \"def.h\"\r\n\r\n\r\n\r\n#define MSG_CH_MAX\t1\r\n\r\n\r\ntypedef struct\r\n{\r\n  uint8_t ch;\r\n  mavlink_message_t *p_msg;\r\n} msg_t;\r\n\r\n\r\n\r\nvoid msg_init(void);\r\nvoid msg_send(uint8_t chan, mavlink_message_t *p_msg);\r\nBOOL msg_recv( uint8_t chan, uint8_t data , mavlink_message_t *p_msg, mavlink_status_t *p_status );\r\nBOOL msg_get_resp( uint8_t chan, mavlink_message_t *p_msg, uint32_t timeout);\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld/msg/xml/opencr_msg",
    "content": "<?xml version=\"1.0\"?>\r\n<mavlink>\r\n        <!--<include>common.xml</include>-->\r\n        <!-- NOTE: If the included file already contains a version tag, remove the version tag here, else uncomment to enable. -->\r\n\t<!--<version>3</version>-->\r\n\t<enums>\r\n\t</enums>\r\n\t\r\n\t<messages>\r\n\t\t<message id=\"150\" name=\"ACK\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"    name=\"msg_id\"></field>\r\n\t\t\t<field type=\"uint16_t\"   name=\"err_code\"></field>\r\n\t\t\t<field type=\"uint8_t\"    name=\"length\"></field>\r\n\t\t\t<field type=\"uint8_t[16]\" name=\"data\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\t\r\n\t<messages>\r\n\t\t<message id=\"151\" name=\"READ_VERSION\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"    name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint8_t[8]\" name=\"param\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\r\n\t<messages>\r\n\t\t<message id=\"152\" name=\"READ_BOARD_NAME\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"    name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint8_t[8]\" name=\"param\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\r\n\t<messages>\r\n\t\t<message id=\"153\" name=\"READ_TAG\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"    name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint8_t\"    name=\"type\"></field>\r\n\t\t\t<field type=\"uint8_t[8]\" name=\"param\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\r\n\t<messages>\r\n\t\t<message id=\"154\" name=\"FLASH_FW_WRITE_BEGIN\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"    name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint8_t[8]\" name=\"param\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\t\r\n\t<messages>\r\n\t\t<message id=\"155\" name=\"FLASH_FW_WRITE_END\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"    name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint8_t[8]\" name=\"param\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\r\n\t<messages>\r\n\t\t<message id=\"156\" name=\"FLASH_FW_WRITE_PACKET\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"  name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint16_t\" name=\"addr\"></field>\r\n\t\t\t<field type=\"uint8_t\"  name=\"length\"></field>\r\n\t\t\t<field type=\"uint8_t[128]\" name=\"data\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\r\n\t<messages>\r\n\t\t<message id=\"157\" name=\"FLASH_FW_WRITE_BLOCK\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"  name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint32_t\" name=\"addr\"></field>\r\n\t\t\t<field type=\"uint16_t\" name=\"length\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\t\r\n\t<messages>\r\n\t\t<message id=\"158\" name=\"FLASH_FW_ERASE\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"    name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint32_t\"   name=\"length\"></field>\r\n\t\t\t<field type=\"uint8_t[8]\" name=\"param\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\t\r\n\t<messages>\r\n\t\t<message id=\"159\" name=\"FLASH_FW_VERIFY\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"    name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint32_t\"   name=\"length\"></field>\r\n\t\t\t<field type=\"uint32_t\"   name=\"crc\"></field>\r\n\t\t\t<field type=\"uint8_t[8]\" name=\"param\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\r\n\t<messages>\r\n\t\t<message id=\"160\" name=\"FLASH_FW_READ_PACKET\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"  name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint32_t\" name=\"addr\"></field>\r\n\t\t\t<field type=\"uint8_t\"  name=\"length\"></field>\r\n\t\t\t<field type=\"uint8_t[128]\" name=\"data\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\r\n\t<messages>\r\n\t\t<message id=\"161\" name=\"FLASH_FW_READ_BLOCK\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"  name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint32_t\" name=\"addr\"></field>\r\n\t\t\t<field type=\"uint16_t\" name=\"length\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\t\r\n\t<messages>\r\n\t\t<message id=\"162\" name=\"JUMP_TO_FW\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"    name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint8_t[8]\" name=\"param\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\t\t\r\n</mavlink>"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld/opencr_ld.c",
    "content": "#include \"opencr_ld.h\"\r\n#include <stdio.h>\r\n#include <stdlib.h>\r\n#include <string.h>\r\n#include <errno.h>\r\n#include <limits.h>\r\n#include <stdio.h>\r\n#include <stdarg.h>\r\n\r\n#include \"serial.h\"\r\n#include \"type.h\"\r\n#include \"./msg/msg.h\"\r\n#include <sys/time.h>\r\n#include <stdio.h>\r\n\r\n\r\n\r\nstatic FILE      *opencr_fp;\r\nstatic uint32_t   opencr_fpsize;\r\n\r\n\r\nser_handler stm32_ser_id = ( ser_handler )-1;\r\n\r\n\r\n#define GET_CALC_TIME(x)\t( (int)(x / 1000) + ((float)(x % 1000))/1000 )\r\n\r\n#define FLASH_TX_BLOCK_LENGTH\t(8*1024)\r\n#define FLASH_RX_BLOCK_LENGTH\t(128)\r\n#define FLASH_PACKET_LENGTH   \t128\r\n\r\n\r\nuint32_t tx_buf[768*1024/4];\r\nuint32_t rx_buf[768*1024/4];\r\n\r\nchar err_msg_str[512];\r\n\r\n\r\nint opencr_ld_down( int argc, const char **argv );\r\nint opencr_ld_jump_to_boot( char *portname );\r\nint opencr_ld_flash_write( uint32_t addr, uint8_t *p_data, uint32_t length  );\r\nint opencr_ld_flash_read( uint32_t addr, uint8_t *p_data, uint32_t length  );\r\nint opencr_ld_flash_erase( uint32_t length  );\r\n\r\nuint32_t opencr_ld_file_read_data( uint8_t *dst, uint32_t len );\r\n\r\nvoid opencr_ld_write_err_msg( const char *fmt, ...);\r\nvoid opencr_ld_print_err_msg(void);\r\n\r\nstatic long iclock();\r\nint read_byte( void );\r\nint write_bytes( char *p_data, int len );\r\nvoid delay_ms( int WaitTime );\r\nuint32_t crc_calc( uint32_t crc_in, uint8_t data_in );\r\n\r\n\r\nerr_code_t cmd_read_version( uint32_t *p_version, uint32_t *p_revision );\r\nerr_code_t cmd_read_board_name( uint8_t *p_str, uint8_t *p_len );\r\nerr_code_t cmd_flash_fw_erase( uint32_t length );\r\nerr_code_t cmd_flash_fw_write_begin( void );\r\nerr_code_t cmd_flash_fw_write_end( void );\r\nerr_code_t cmd_flash_fw_write_packet( uint16_t addr, uint8_t *p_data, uint8_t length );\r\nerr_code_t cmd_flash_fw_write_block( uint32_t addr, uint32_t length  );\r\nerr_code_t cmd_flash_fw_send_block_multi( uint8_t block_count );\r\nerr_code_t cmd_flash_fw_read_block( uint32_t addr, uint8_t *p_data, uint16_t length );\r\nerr_code_t cmd_flash_fw_verify( uint32_t length, uint32_t crc, uint32_t *p_crc_ret );\r\nerr_code_t cmd_jump_to_fw(void);\r\n\r\n\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : opencr_ld_main\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nint opencr_ld_main( int argc, const char **argv )\r\n{\r\n  long baud;\r\n  baud = strtol( argv[ 2 ], NULL, 10 );\r\n\r\n  printf(\"opencr_ld_main \\r\\n\");\r\n\r\n  opencr_ld_down( argc, argv );\r\n\r\n  return 0;\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : opencr_ld_down\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nint opencr_ld_down( int argc, const char **argv )\r\n{\r\n  int i;\r\n  int j;\r\n  int ret = 0;\r\n  err_code_t err_code = OK;\r\n  long t, dt;\r\n  float calc_time;\r\n  uint32_t fw_size = 256*1024*3;\r\n  uint8_t  board_str[16];\r\n  uint8_t  board_str_len;\r\n  uint32_t board_version;\r\n  uint32_t board_revision;\r\n  uint32_t crc;\r\n  uint32_t crc_ret = 0;\r\n  uint8_t  *p_buf_crc;\r\n  char *portname;\r\n  uint32_t baud;\r\n  uint8_t  block_buf[FLASH_TX_BLOCK_LENGTH];\r\n  uint32_t addr;\r\n  uint32_t len;\r\n  uint8_t jump_to_fw = 0;\r\n  uint8_t retry;\r\n\r\n\r\n  baud     = strtol( argv[ 2 ], NULL, 10 );\r\n  portname = (char *)argv[ 1 ];\r\n\r\n  if( argc >= 5 && strlen(argv[ 4 ])==1 && strncmp(argv[ 4 ], \"1\", 1)==0 )\r\n  {\r\n    jump_to_fw = 1;\r\n  }\r\n\r\n  if( ( opencr_fp = fopen( argv[ 3 ], \"rb\" ) ) == NULL )\r\n  {\r\n    fprintf( stderr, \"Unable to open %s\\n\", argv[ 3 ] );\r\n    exit( 1 );\r\n  }\r\n  else\r\n  {\r\n    fseek( opencr_fp, 0, SEEK_END );\r\n    opencr_fpsize = ftell( opencr_fp );\r\n    fseek( opencr_fp, 0, SEEK_SET );\r\n    printf(\">>\\r\\n\");\r\n    printf(\"file name : %s \\r\\n\", argv[3]);\r\n    printf(\"file size : %d KB\\r\\n\", opencr_fpsize/1024);\r\n  }\r\n\r\n  fw_size = opencr_fpsize;\r\n\r\n\r\n  // Jump To Boot\r\n  if( opencr_ld_jump_to_boot(portname ) < 0 )\r\n  {\r\n    printf(\"Fail to jump to boot\\n\");\r\n    return -1;\r\n  }\r\n\r\n\r\n  // Open port\r\n  if( ( stm32_ser_id = ser_open( portname ) ) == ( ser_handler )-1 )\r\n  {\r\n    printf(\"Fail to open port 1\\n\");\r\n    return -1;\r\n  }\r\n  else\r\n  {\r\n    printf(\"Open port OK\\n\");\r\n  }\r\n\r\n  // Setup port\r\n  ser_setupEx( stm32_ser_id, 115200, SER_DATABITS_8, SER_PARITY_NONE, SER_STOPBITS_1, 1 );\r\n\r\n  printf(\"Clear Buffer Start\\n\");\r\n  ser_set_timeout_ms( stm32_ser_id, SER_NO_TIMEOUT );\r\n  while( read_byte() != -1 );\r\n  ser_set_timeout_ms( stm32_ser_id, 1000 );\r\n  printf(\"Clear Buffer End\\n\");\r\n\r\n\r\n  err_code = cmd_read_board_name( board_str, &board_str_len );\r\n  if( err_code == OK )\r\n  {\r\n    printf(\"Board Name : %s\\r\\n\", board_str);\r\n  }\r\n  else\r\n  {\r\n    printf(\"cmd_read_board_name fail : 0x%X\\n\", err_code);\r\n    ser_close( stm32_ser_id );\r\n    fclose( opencr_fp );\r\n    exit(1);\r\n  }\r\n  err_code = cmd_read_version( &board_version, &board_revision );\r\n  if( err_code == OK )\r\n  {\r\n    printf(\"Board Ver  : 0x%08X\\r\\n\", board_version);\r\n    printf(\"Board Rev  : 0x%08X\\r\\n\", board_revision);\r\n  }\r\n  printf(\">>\\r\\n\");\r\n\r\n  t = iclock();\r\n  ret = opencr_ld_flash_erase(fw_size);\r\n  dt = iclock() - t;\r\n  printf(\"flash_erase : %d : %f sec\\r\\n\", ret, GET_CALC_TIME(dt));\r\n  if( ret < 0 )\r\n  {\r\n    ser_close( stm32_ser_id );\r\n    fclose( opencr_fp );\r\n    exit(1);\r\n  }\r\n\r\n#if 1\r\n  t = iclock();\r\n  crc  = 0;\r\n  addr = 0;\r\n  while(1)\r\n  {\r\n    len = opencr_ld_file_read_data( block_buf, FLASH_TX_BLOCK_LENGTH);\r\n    if( len == 0 ) break;\r\n\r\n    for( i=0; i<len; i++ )\r\n    {\r\n      crc = crc_calc( crc,  block_buf[i] );\r\n    }\r\n\r\n    for( retry=0; retry<3; retry++ )\r\n    {\r\n      ret = opencr_ld_flash_write( addr, block_buf, len );\r\n      if( ret >= 0 ) break;\r\n    }\r\n    if( ret < 0 ) break;\r\n\r\n    addr += len;\r\n  }\r\n  dt = iclock() - t;\r\n\r\n  printf(\"flash_write : %d : %f sec \\r\\n\", ret,  GET_CALC_TIME(dt));\r\n  if( ret < 0 )\r\n  {\r\n    ser_close( stm32_ser_id );\r\n    fclose( opencr_fp );\r\n    opencr_ld_print_err_msg();\r\n    printf(\"[FAIL] Download \\r\\n\");\r\n    return -2;\r\n  }\r\n\r\n\r\n#else\r\n  for( i=0; i<fw_size/4; i++ )\r\n  {\r\n    tx_buf[i] = i;\r\n  }\r\n\r\n  t = iclock();\r\n  crc = 0;\r\n  p_buf_crc = (uint8_t *)tx_buf;\r\n  for( i=0; i<fw_size; i++ )\r\n  {\r\n    crc = crc_calc( crc,  p_buf_crc[i] );\r\n  }\r\n  dt = iclock() - t;\r\n  printf(\"calc crc : %f sec \\r\\n\", GET_CALC_TIME(dt));\r\n\r\n\r\n  t = iclock();\r\n  ret = opencr_ld_flash_write( 0, (uint8_t *)tx_buf, fw_size );\r\n  dt = iclock() - t;\r\n\r\n\r\n  calc_time = GET_CALC_TIME(dt);\r\n  printf(\"opencr_ld_flash_write : %d : %f sec, %f KB/s\\n\", ret, calc_time, (fw_size/1024/calc_time) );\r\n\r\n  memset(rx_buf, 0, 768*1024);\r\n  t = iclock();\r\n  ret = opencr_ld_flash_read( 0, (uint8_t *)rx_buf, fw_size );\r\n  dt = iclock() - t;\r\n  printf(\"opencr_ld_flash_read : %d : %f sec \\r\\n\", ret,  GET_CALC_TIME(dt));\r\n\r\n  ret = 0;\r\n  for( i=0; i<fw_size/4; i++ )\r\n  {\r\n    if( tx_buf[i] != rx_buf[i] )\r\n    {\r\n      printf(\"Compare Error : 0x%X \\r\\n\", i*4);\r\n      ret = -1;\r\n      break;\r\n    }\r\n  }\r\n  if( ret == 0 )\r\n  {\r\n    printf(\"Compare OK \\r\\n\");\r\n  }\r\n#endif\r\n\r\n\r\n  for(i = 0; i < 3; i++)\r\n  {\r\n    if( i > 0)\r\n    {\r\n      printf(\"CRC Retry : %d\\r\\n\", i);\r\n    }\r\n\r\n    t = iclock();\r\n    err_code = cmd_flash_fw_verify( fw_size, crc, &crc_ret );\r\n    dt = iclock() - t;\r\n    \r\n    if(err_code == OK)\r\n    {\r\n      break;\r\n    }\r\n  }\r\n\r\n  if( err_code == OK )\r\n  {\r\n    printf(\"CRC OK %X %X %f sec\\r\\n\", crc, crc_ret, GET_CALC_TIME(dt));\r\n  }\r\n  else\r\n  {\r\n    printf(\"CRC Fail : 0x%X : %X, %X %f sec\\r\\n\", err_code, crc, crc_ret, GET_CALC_TIME(dt));\r\n    printf(\"[FAIL] Download \\r\\n\");\r\n    ser_close( stm32_ser_id );\r\n    fclose( opencr_fp );\r\n    return -3;\r\n  }\r\n\r\n  printf(\"[OK] Download \\r\\n\");\r\n\r\n  if( jump_to_fw == 1 )\r\n  {\r\n    printf(\"jump_to_fw \\r\\n\");\r\n    cmd_jump_to_fw();\r\n  }\r\n\r\n  ser_close( stm32_ser_id );\r\n  fclose( opencr_fp );\r\n\r\n\r\n  for (int i=0; i<6; i++)\r\n  {\r\n    delay_ms(500);\r\n    if (ser_port_is_ready(portname) > 0)\r\n    {\r\n      printf(\"jump finished\\r\\n\");\r\n      delay_ms(100);\r\n      break;\r\n    }\r\n  }\r\n\r\n  return ret;\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : opencr_ld_file_read_data\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nint opencr_ld_jump_to_boot( char *portname )\r\n{\r\n  bool ret;\r\n\r\n\r\n  // Open port\r\n  if( ( stm32_ser_id = ser_open( portname ) ) == ( ser_handler )-1 )\r\n  {\r\n    printf(\"Fail to open port 1 : %s\\n\", portname);\r\n    return -1;\r\n  }\r\n\r\n  // Setup port\r\n  ser_setupEx( stm32_ser_id, 1200, SER_DATABITS_8, SER_PARITY_NONE, SER_STOPBITS_1, 1 );\r\n\r\n  write_bytes(\"OpenCR 5555AAAA\", 15);\r\n  ser_close( stm32_ser_id );\r\n\r\n  delay_ms(1500);\r\n\r\n  return 0;\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : opencr_ld_file_read_data\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nuint32_t opencr_ld_file_read_data( uint8_t *dst, uint32_t len )\r\n{\r\n  size_t readbytes = 0;\r\n\r\n  if( !feof( opencr_fp ) )\r\n  {\r\n    readbytes = fread( dst, 1, len, opencr_fp );\r\n  }\r\n  return ( uint32_t )readbytes;\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : opencr_ld_flash_write\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nint opencr_ld_flash_write( uint32_t addr, uint8_t *p_data, uint32_t length  )\r\n{\r\n  int ret = 0;\r\n  err_code_t err_code = OK;\r\n  uint32_t block_length;\r\n  uint16_t block_cnt;\r\n  uint32_t written_packet_length;\r\n  uint32_t written_total_length;\r\n  uint32_t packet_length = 128;\r\n  uint32_t i;\r\n\r\n\r\n  err_code = cmd_flash_fw_write_begin();\r\n  if( err_code != OK )\r\n  {\r\n    opencr_ld_write_err_msg(\"cmd_flash_fw_write_begin ERR : 0x%04X\\r\\n\", err_code);\r\n\r\n    return -1;\r\n  }\r\n\r\n  written_total_length = 0;\r\n\r\n  while(1)\r\n  {\r\n    block_length = length - written_total_length;\r\n\r\n    if( block_length > FLASH_TX_BLOCK_LENGTH )\r\n    {\r\n      block_length = FLASH_TX_BLOCK_LENGTH;\r\n    }\r\n\r\n    block_cnt = block_length/FLASH_PACKET_LENGTH;\r\n    if( block_length%FLASH_PACKET_LENGTH > 0 )\r\n    {\r\n      block_cnt += 1;\r\n    }\r\n\r\n\r\n    written_packet_length = 0;\r\n    for( i=0; i<block_cnt; i++ )\r\n    {\r\n      packet_length = block_length - written_packet_length;\r\n      if( packet_length > FLASH_PACKET_LENGTH )\r\n      {\r\n        packet_length = FLASH_PACKET_LENGTH;\r\n      }\r\n\r\n      err_code = cmd_flash_fw_write_packet(written_packet_length, &p_data[written_total_length+written_packet_length], packet_length);\r\n      if( err_code != OK )\r\n      {\r\n        opencr_ld_write_err_msg(\"cmd_flash_fw_send_block ERR : 0x%04X\\r\\n\", err_code);\r\n        return -2;\r\n      }\r\n\r\n      written_packet_length += packet_length;\r\n    }\r\n\r\n    //printf(\"%d : %d, %d, %d \\r\\n\", written_packet_length, block_length, block_cnt, packet_length);\r\n\r\n    if( written_packet_length == block_length )\r\n    {\r\n      err_code = cmd_flash_fw_write_block(addr+written_total_length, block_length);\r\n      if( err_code != OK )\r\n      {\r\n        opencr_ld_write_err_msg(\"cmd_flash_fw_write_block ERR : 0x%04X\\r\\n\", err_code);\r\n        return -3;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      opencr_ld_write_err_msg(\"written_packet_length : %d, %d 0x%04X\\r\\n\", written_packet_length, block_length, err_code);\r\n      return -4;\r\n    }\r\n\r\n    written_total_length += block_length;\r\n\r\n    if( written_total_length == length )\r\n    {\r\n      break;\r\n    }\r\n    else if( written_total_length > length )\r\n    {\r\n      opencr_ld_write_err_msg(\"written_total_length over \\r\\n\");\r\n      return -5;\r\n    }\r\n  }\r\n\r\n\r\n  cmd_flash_fw_write_end();\r\n\r\n  return ret;\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : opencr_ld_flash_read\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nint opencr_ld_flash_read( uint32_t addr, uint8_t *p_data, uint32_t length  )\r\n{\r\n  int ret = 0;\r\n  err_code_t err_code = OK;\r\n  uint32_t block_length;\r\n  uint32_t read_packet_length;\r\n  uint32_t read_total_length;\r\n  int i;\r\n  int err_count = 0;\r\n\r\n  read_total_length = 0;\r\n\r\n  while(1)\r\n  {\r\n    block_length = length - read_total_length;\r\n\r\n    if( block_length > FLASH_PACKET_LENGTH )\r\n    {\r\n      block_length = FLASH_PACKET_LENGTH;\r\n    }\r\n\r\n\r\n    for( i=0; i<3; i++ )\r\n    {\r\n      err_code = cmd_flash_fw_read_block( addr+read_total_length, &p_data[read_total_length], block_length );\r\n      if( err_code == OK ) break;\r\n      err_count++;\r\n    }\r\n\r\n\r\n    if( err_code != OK )\r\n    {\r\n      printf(\"cmd_flash_fw_read_block : addr:%X, 0x%04X \\r\\n\", addr+read_total_length, err_code);\r\n      return -1;\r\n    }\r\n\r\n    read_total_length += block_length;\r\n\r\n    if( read_total_length == length )\r\n    {\r\n      break;\r\n    }\r\n    else if( read_total_length > length )\r\n    {\r\n      printf(\"read_total_length over \\r\\n\");\r\n      return -2;\r\n    }\r\n  }\r\n\r\n  return ret;\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : opencr_ld_flash_erase\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nint opencr_ld_flash_erase( uint32_t length  )\r\n{\r\n  int ret = 0;\r\n  err_code_t err_code = OK;\r\n\r\n  err_code = cmd_flash_fw_erase( length );\r\n\r\n  if( err_code != OK )\r\n  {\r\n    printf(\"cmd_flash_fw_erase_block : 0x%04X %d\\r\\n\", err_code, length );\r\n    return -1;\r\n  }\r\n\r\n  return ret;\r\n}\r\n\r\n\r\n\r\nstatic long iclock()\r\n{\r\n\tstruct timeval tv;\r\n\tgettimeofday (&tv, NULL);\r\n\treturn (tv.tv_sec * 1000 + tv.tv_usec / 1000);\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : delay_ms\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nvoid delay_ms( int WaitTime )\r\n{\r\n  int i;\r\n\r\n  #ifdef WIN32_BUILD\r\n  Sleep(WaitTime);\r\n  #else\r\n  for( i=0; i<WaitTime; i++ )\r\n  {\r\n    usleep(1000);\r\n  }\r\n  #endif\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : read_byte\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nint read_byte( void )\r\n{\r\n  return ser_read_byte( stm32_ser_id );\r\n}\r\n\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : read_bytes\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nint read_bytes( uint8_t *pData, uint32_t size )\r\n{\r\n  return read( stm32_ser_id, pData, size ); //ser_read( stm32_ser_id, pData, size );\r\n  //return ser_read( stm32_ser_id, pData, size );\r\n}\r\n\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : write_bytes\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nint write_bytes( char *p_data, int len )\r\n{\r\n  int written_len;\r\n\r\n  written_len = ser_write( stm32_ser_id, (const u8 *)p_data, len );\r\n\r\n  return written_len;\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : cmd_read_version\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nerr_code_t cmd_read_version( uint32_t *p_version, uint32_t *p_revision )\r\n{\r\n  err_code_t err_code = OK;\r\n  mavlink_message_t tx_msg;\r\n  mavlink_message_t rx_msg;\r\n  mavlink_ack_t     ack_msg;\r\n  uint8_t param[8];\r\n  uint8_t resp = 1;\r\n\r\n\r\n  mavlink_msg_read_version_pack(0, 0, &tx_msg, resp, param);\r\n  msg_send(0, &tx_msg);\r\n\r\n  if( resp == 1 )\r\n  {\r\n    if( msg_get_resp(0, &rx_msg, 500) == TRUE )\r\n    {\r\n      mavlink_msg_ack_decode( &rx_msg, &ack_msg);\r\n\r\n      //printf(\"BootVersion : 0x%08X\\r\\n\", ack_msg.data[3]<<24|ack_msg.data[2]<<16|ack_msg.data[1]<<8|ack_msg.data[0]);\r\n      *p_version  = ack_msg.data[3]<<24|ack_msg.data[2]<<16|ack_msg.data[1]<<8|ack_msg.data[0];\r\n      *p_revision = ack_msg.data[7]<<24|ack_msg.data[6]<<16|ack_msg.data[5]<<8|ack_msg.data[4];\r\n      if( tx_msg.msgid == ack_msg.msg_id ) err_code = ack_msg.err_code;\r\n      else                                 err_code = ERR_MISMATCH_ID;\r\n    }\r\n    else\r\n    {\r\n      err_code = ERR_TIMEOUT;\r\n    }\r\n  }\r\n\r\n  return OK;\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : cmd_read_board_name\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nerr_code_t cmd_read_board_name( uint8_t *p_str, uint8_t *p_len )\r\n{\r\n  err_code_t err_code = OK;\r\n  mavlink_message_t tx_msg;\r\n  mavlink_message_t rx_msg;\r\n  mavlink_ack_t     ack_msg;\r\n  uint8_t param[8];\r\n  uint8_t resp = 1;\r\n\r\n  mavlink_msg_read_board_name_pack(0, 0, &tx_msg, resp, param);\r\n  msg_send(0, &tx_msg);\r\n  if( resp == 1 )\r\n  {\r\n    if( msg_get_resp(0, &rx_msg, 500) == TRUE )\r\n    {\r\n      mavlink_msg_ack_decode( &rx_msg, &ack_msg);\r\n\r\n      *p_len = ack_msg.length;\r\n      memcpy(p_str, ack_msg.data, ack_msg.length);\r\n      p_str[ack_msg.length] = 0;\r\n\r\n      if( tx_msg.msgid == ack_msg.msg_id ) err_code = ack_msg.err_code;\r\n      else                                 err_code = ERR_MISMATCH_ID;\r\n    }\r\n    else\r\n    {\r\n      err_code = ERR_TIMEOUT;\r\n    }\r\n  }\r\n\r\n  return err_code;\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : cmd_flash_fw_erase\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nerr_code_t cmd_flash_fw_erase( uint32_t length )\r\n{\r\n  err_code_t err_code = OK;\r\n  mavlink_message_t tx_msg;\r\n  mavlink_message_t rx_msg;\r\n  mavlink_ack_t     ack_msg;\r\n  uint8_t param[8];\r\n  uint8_t resp = 1;\r\n\r\n\r\n  mavlink_msg_flash_fw_erase_pack(0, 0, &tx_msg, resp, length, param);\r\n  msg_send(0, &tx_msg);\r\n\r\n  if( resp == 1 )\r\n  {\r\n    if( msg_get_resp(0, &rx_msg, 5000) == TRUE )\r\n    {\r\n      mavlink_msg_ack_decode( &rx_msg, &ack_msg);\r\n\r\n      if( tx_msg.msgid == ack_msg.msg_id ) err_code = ack_msg.err_code;\r\n      else                                 err_code = ERR_MISMATCH_ID;\r\n    }\r\n    else\r\n    {\r\n      err_code = ERR_TIMEOUT;\r\n    }\r\n  }\r\n\r\n  return err_code;\r\n}\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : cmd_flash_fw_write_begin\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nerr_code_t cmd_flash_fw_write_begin( void )\r\n{\r\n  err_code_t err_code = OK;\r\n  mavlink_message_t tx_msg;\r\n  mavlink_message_t rx_msg;\r\n  mavlink_ack_t     ack_msg;\r\n  uint8_t param[8];\r\n  uint8_t resp = 1;\r\n\r\n\r\n  mavlink_msg_flash_fw_write_begin_pack(0, 0, &tx_msg, resp, param);\r\n  msg_send(0, &tx_msg);\r\n\r\n  if( resp == 1 )\r\n  {\r\n    if( msg_get_resp(0, &rx_msg, 500) == TRUE )\r\n    {\r\n      mavlink_msg_ack_decode( &rx_msg, &ack_msg);\r\n\r\n      if( tx_msg.msgid == ack_msg.msg_id ) err_code = ack_msg.err_code;\r\n      else                                 err_code = ERR_MISMATCH_ID;\r\n    }\r\n    else\r\n    {\r\n      err_code = ERR_TIMEOUT;\r\n    }\r\n  }\r\n\r\n  return err_code;\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : cmd_flash_fw_write_end\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nerr_code_t cmd_flash_fw_write_end( void )\r\n{\r\n  err_code_t err_code = OK;\r\n  mavlink_message_t tx_msg;\r\n  mavlink_message_t rx_msg;\r\n  mavlink_ack_t     ack_msg;\r\n  uint8_t param[8];\r\n  uint8_t resp = 1;\r\n\r\n\r\n  mavlink_msg_flash_fw_write_end_pack(0, 0, &tx_msg, resp, param);\r\n  msg_send(0, &tx_msg);\r\n\r\n  if( resp == 1 )\r\n  {\r\n    if( msg_get_resp(0, &rx_msg, 500) == TRUE )\r\n    {\r\n      mavlink_msg_ack_decode( &rx_msg, &ack_msg);\r\n\r\n      //printf(\"block_count  : %d\\r\\n\", ack_msg.data[1]<<8|ack_msg.data[0]);\r\n      //printf(\"block_length : %d\\r\\n\", ack_msg.data[5]<<24|ack_msg.data[4]<<16|ack_msg.data[3]<<8|ack_msg.data[2]);\r\n\r\n\r\n      if( tx_msg.msgid == ack_msg.msg_id ) err_code = ack_msg.err_code;\r\n      else                                 err_code = ERR_MISMATCH_ID;\r\n    }\r\n    else\r\n    {\r\n      err_code = ERR_TIMEOUT;\r\n    }\r\n  }\r\n\r\n  return err_code;\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : cmd_flash_fw_write_packet\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nerr_code_t cmd_flash_fw_write_packet( uint16_t addr, uint8_t *p_data, uint8_t length )\r\n{\r\n  err_code_t err_code = OK;\r\n  mavlink_message_t tx_msg;\r\n  mavlink_message_t rx_msg;\r\n  mavlink_ack_t     ack_msg;\r\n  uint8_t resp = 0;\r\n\r\n\r\n\r\n  mavlink_msg_flash_fw_write_packet_pack(0, 0, &tx_msg, resp, addr, length, p_data);\r\n  msg_send(0, &tx_msg);\r\n\r\n\r\n  if( resp == 1 )\r\n  {\r\n    if( msg_get_resp(0, &rx_msg, 500) == TRUE )\r\n    {\r\n      mavlink_msg_ack_decode( &rx_msg, &ack_msg);\r\n\r\n      if( tx_msg.msgid == ack_msg.msg_id ) err_code = ack_msg.err_code;\r\n      else                                 err_code = ERR_MISMATCH_ID;\r\n    }\r\n    else\r\n    {\r\n      err_code = ERR_TIMEOUT;\r\n    }\r\n  }\r\n\r\n  return err_code;\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : cmd_flash_fw_send_block_multi\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nerr_code_t cmd_flash_fw_send_block_multi( uint8_t block_count )\r\n{\r\n  err_code_t err_code = OK;\r\n  mavlink_message_t tx_msg;\r\n  mavlink_message_t rx_msg;\r\n  mavlink_ack_t     ack_msg;\r\n  uint8_t buf[256];\r\n  uint8_t tx_buf[16*1024];\r\n  uint8_t resp = 0;\r\n  uint8_t i;\r\n  uint32_t len;\r\n\r\n\r\n   len = 0;\r\n  for( i=0; i<block_count; i++ )\r\n  {\r\n    mavlink_msg_flash_fw_write_packet_pack(0, 0, &tx_msg, resp, 0, 128, buf);\r\n    len += mavlink_msg_to_send_buffer(&tx_buf[len], &tx_msg);\r\n  }\r\n  write_bytes((char *)tx_buf, len);\r\n\r\n  return err_code;\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : cmd_flash_fw_write_block\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nerr_code_t cmd_flash_fw_write_block( uint32_t addr, uint32_t length  )\r\n{\r\n  err_code_t err_code = OK;\r\n  mavlink_message_t tx_msg;\r\n  mavlink_message_t rx_msg;\r\n  mavlink_ack_t     ack_msg;\r\n  uint8_t buf[256];\r\n  uint8_t resp = 1;\r\n\r\n\r\n  mavlink_msg_flash_fw_write_block_pack(0, 0, &tx_msg, resp, addr, length);\r\n  msg_send(0, &tx_msg);\r\n\r\n\r\n  if( resp == 1 )\r\n  {\r\n    if( msg_get_resp(0, &rx_msg, 500) == TRUE )\r\n    {\r\n      mavlink_msg_ack_decode( &rx_msg, &ack_msg);\r\n\r\n      if( tx_msg.msgid == ack_msg.msg_id ) err_code = ack_msg.err_code;\r\n      else                                 err_code = ERR_MISMATCH_ID;\r\n    }\r\n    else\r\n    {\r\n      err_code = ERR_TIMEOUT;\r\n    }\r\n  }\r\n\r\n  return err_code;\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : cmd_flash_fw_read_block\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\n#if 0\r\nerr_code_t cmd_flash_fw_read_block( uint32_t addr, uint8_t *p_data, uint16_t length )\r\n{\r\n  err_code_t err_code = OK;\r\n  mavlink_message_t tx_msg;\r\n  mavlink_message_t rx_msg;\r\n  mavlink_flash_fw_read_t  resp_msg;\r\n  uint8_t resp = 1;\r\n  uint16_t received_length;\r\n\r\n\r\n  mavlink_msg_flash_fw_read_block_pack(0, 0, &tx_msg, resp, addr, length);\r\n  msg_send(0, &tx_msg);\r\n\r\n\r\n\r\n  if( resp == 1 )\r\n  {\r\n    received_length = 0;\r\n\r\n    while(1)\r\n    {\r\n      if( msg_get_resp(0, &rx_msg, 3000) == TRUE )\r\n      {\r\n\tmavlink_msg_flash_fw_read_decode( &rx_msg, &resp_msg);\r\n\r\n\tmemcpy(&p_data[received_length], resp_msg.data, resp_msg.length);\r\n\treceived_length += resp_msg.length;\r\n\r\n\t//printf(\"recv %d \\r\\n\", received_length);\r\n\r\n\tif( received_length == length )\r\n\t{\r\n\t  break;\r\n\t}\r\n\telse if( received_length > length )\r\n\t{\r\n\t  err_code = ERR_SIZE_OVER;\r\n\t  break;\r\n\t}\r\n      }\r\n      else\r\n      {\r\n\terr_code = ERR_TIMEOUT;\r\n\tbreak;\r\n      }\r\n    }\r\n  }\r\n\r\n  return err_code;\r\n}\r\n#else\r\nerr_code_t cmd_flash_fw_read_block( uint32_t addr, uint8_t *p_data, uint16_t length )\r\n{\r\n  err_code_t err_code = OK;\r\n  mavlink_message_t tx_msg;\r\n  mavlink_message_t rx_msg;\r\n  mavlink_flash_fw_read_packet_t  resp_msg;\r\n  uint8_t resp = 1;\r\n\r\n\r\n  mavlink_msg_flash_fw_read_block_pack(0, 0, &tx_msg, resp, addr, length);\r\n  msg_send(0, &tx_msg);\r\n\r\n\r\n\r\n  if( resp == 1 )\r\n  {\r\n    if( msg_get_resp(0, &rx_msg, 100) == TRUE )\r\n    {\r\n      mavlink_msg_flash_fw_read_packet_decode( &rx_msg, &resp_msg);\r\n\r\n      memcpy(p_data, resp_msg.data, resp_msg.length);\r\n\r\n      if( resp_msg.length > length )\r\n      {\r\n\terr_code = ERR_SIZE_OVER;\r\n      }\r\n    }\r\n    else\r\n    {\r\n      err_code = ERR_TIMEOUT;\r\n    }\r\n  }\r\n\r\n  return err_code;\r\n}\r\n#endif\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : cmd_flash_fw_verify\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nerr_code_t cmd_flash_fw_verify( uint32_t length, uint32_t crc, uint32_t *p_crc_ret )\r\n{\r\n  err_code_t err_code = OK;\r\n  mavlink_message_t tx_msg;\r\n  mavlink_message_t rx_msg;\r\n  mavlink_ack_t     ack_msg;\r\n  uint8_t param[8];\r\n  uint8_t resp = 1;\r\n\r\n\r\n  mavlink_msg_flash_fw_verify_pack(0, 0, &tx_msg, resp, length, crc, param);\r\n  msg_send(0, &tx_msg);\r\n\r\n\r\n  if( resp == 1 )\r\n  {\r\n    if( msg_get_resp(0, &rx_msg, 500) == TRUE )\r\n    {\r\n      mavlink_msg_ack_decode( &rx_msg, &ack_msg);\r\n\r\n      *p_crc_ret = ack_msg.data[3]<<24|ack_msg.data[2]<<16|ack_msg.data[1]<<8|ack_msg.data[0];\r\n\r\n      if( tx_msg.msgid == ack_msg.msg_id ) err_code = ack_msg.err_code;\r\n      else                                 err_code = ERR_MISMATCH_ID;\r\n    }\r\n    else\r\n    {\r\n      err_code = ERR_TIMEOUT;\r\n    }\r\n  }\r\n  return err_code;\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : cmd_jump_to_fw\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nerr_code_t cmd_jump_to_fw(void)\r\n{\r\n  err_code_t err_code = OK;\r\n  mavlink_message_t tx_msg;\r\n  mavlink_message_t rx_msg;\r\n  mavlink_ack_t     ack_msg;\r\n  uint8_t param[8];\r\n  uint8_t resp = 0;\r\n\r\n\r\n  mavlink_msg_jump_to_fw_pack(0, 0, &tx_msg, resp, param);\r\n  msg_send(0, &tx_msg);\r\n\r\n\r\n  if( resp == 1 )\r\n  {\r\n    if( msg_get_resp(0, &rx_msg, 500) == TRUE )\r\n    {\r\n      mavlink_msg_ack_decode( &rx_msg, &ack_msg);\r\n\r\n      if( tx_msg.msgid == ack_msg.msg_id ) err_code = ack_msg.err_code;\r\n      else                                 err_code = ERR_MISMATCH_ID;\r\n    }\r\n    else\r\n    {\r\n      err_code = ERR_TIMEOUT;\r\n    }\r\n  }\r\n  return err_code;\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : crc_calc\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nuint32_t crc_calc( uint32_t crc_in, uint8_t data_in )\r\n{\r\n\r\n  crc_in  ^= data_in;\r\n  crc_in  += data_in;\r\n\r\n  return crc_in;\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : opencr_ld_write_err_msg\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nvoid opencr_ld_write_err_msg( const char *fmt, ...)\r\n{\r\n  int32_t ret = 0;\r\n  va_list arg;\r\n  va_start (arg, fmt);\r\n  int32_t len;\r\n\r\n  len = vsnprintf(err_msg_str, 255, fmt, arg);\r\n  va_end (arg);\r\n}\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : opencr_ld_write_err_msg\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nvoid opencr_ld_print_err_msg(void)\r\n{\r\n  uint32_t len;\r\n\r\n  len = strlen(err_msg_str);\r\n\r\n  if( len > 0 && len < 500 )\r\n  {\r\n    printf(\"%s\", err_msg_str);\r\n  }\r\n}\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld/opencr_ld.h",
    "content": "/*\r\n *  main.h\r\n *\r\n *  Created on: 2016. 5. 14.\r\n *      Author: Baram, PBPH\r\n */\r\n\r\n#ifndef __OPENCR_LD_MAIN_H_\r\n#define __OPENCR_LD_MAIN_H_\r\n\r\n#include <unistd.h>\r\n#include \"type.h\"\r\n#include \"serial.h\"\r\n\r\n\r\nint opencr_ld_main( int argc, const char **argv );\r\n\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld/qt_win/opencr_ld_win/opencr_ld/main.c",
    "content": "#include <stdio.h>\r\n\r\nint main(int argc, char *argv[])\r\n{\r\n    printf(\"Hello World!\\n\");\r\n    return 0;\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld/qt_win/opencr_ld_win/opencr_ld/opencr_ld.pro",
    "content": "TEMPLATE = app\r\nCONFIG += console\r\nCONFIG -= app_bundle\r\nCONFIG -= qt\r\n\r\nDEFINES += WIN32_BUILD\r\n\r\nSOURCES += \\\r\n    ../../../msg/msg.c \\\r\n    ../../../main.c \\\r\n    ../../../opencr_ld.c \\\r\n    ../../../serial_win32.c\r\n\r\nHEADERS += \\\r\n    ../../../opencr_ld.h \\\r\n    ../../../serial.h \\\r\n    ../../../type.h \\\r\n    ../../../msg/mavlink/opencr_msg/mavlink.h \\\r\n    ../../../msg/mavlink/opencr_msg/mavlink_msg_ack.h \\\r\n    ../../../msg/mavlink/opencr_msg/mavlink_msg_flash_fw_erase.h \\\r\n    ../../../msg/mavlink/opencr_msg/mavlink_msg_flash_fw_read_block.h \\\r\n    ../../../msg/mavlink/opencr_msg/mavlink_msg_flash_fw_read_packet.h \\\r\n    ../../../msg/mavlink/opencr_msg/mavlink_msg_flash_fw_verify.h \\\r\n    ../../../msg/mavlink/opencr_msg/mavlink_msg_flash_fw_write_begin.h \\\r\n    ../../../msg/mavlink/opencr_msg/mavlink_msg_flash_fw_write_block.h \\\r\n    ../../../msg/mavlink/opencr_msg/mavlink_msg_flash_fw_write_end.h \\\r\n    ../../../msg/mavlink/opencr_msg/mavlink_msg_flash_fw_write_packet.h \\\r\n    ../../../msg/mavlink/opencr_msg/mavlink_msg_jump_to_fw.h \\\r\n    ../../../msg/mavlink/opencr_msg/mavlink_msg_read_board_name.h \\\r\n    ../../../msg/mavlink/opencr_msg/mavlink_msg_read_tag.h \\\r\n    ../../../msg/mavlink/opencr_msg/mavlink_msg_read_version.h \\\r\n    ../../../msg/mavlink/opencr_msg/opencr_msg.h \\\r\n    ../../../msg/mavlink/opencr_msg/testsuite.h \\\r\n    ../../../msg/mavlink/opencr_msg/version.h \\\r\n    ../../../msg/mavlink/checksum.h \\\r\n    ../../../msg/mavlink/mavlink_conversions.h \\\r\n    ../../../msg/mavlink/mavlink_helpers.h \\\r\n    ../../../msg/mavlink/mavlink_types.h \\\r\n    ../../../msg/mavlink/protocol.h \\\r\n    ../../../msg/def.h \\\r\n    ../../../msg/def_err.h \\\r\n    ../../../msg/msg.h\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld/serial.h",
    "content": "#ifndef __SERIAL_H__\r\n#define __SERIAL_H__\r\n\r\n#include \"type.h\"\r\n\r\n#define SER_INF_TIMEOUT         0xFFFFFFFF\r\n#define SER_NO_TIMEOUT          0\r\n#define SER_OK                  0\r\n#define SER_ERR                 1\r\n\r\n// Serial interface modes (blocking or non blocking)\r\n#define SER_MODE_BLOCKING       0\r\n#define SER_MODE_NONBLOCKING    1\r\n\r\n// Setup constants\r\n#define SER_PARITY_NONE         0\r\n#define SER_PARITY_EVEN         1\r\n#define SER_PARITY_ODD          2\r\n\r\n#define SER_STOPBITS_1          0\r\n#define SER_STOPBITS_1_5        1\r\n#define SER_STOPBITS_2          2\r\n\r\n#define SER_DATABITS_5          5\r\n#define SER_DATABITS_6          6\r\n#define SER_DATABITS_7          7\r\n#define SER_DATABITS_8          8\r\n\r\n// Serial access functions (to be implemented by each platform)\r\nser_handler ser_open( const char *sername );\r\nvoid ser_close( ser_handler id );\r\nint ser_setup( ser_handler id, u32 baud, int databits, int parity, int stopbits );\r\nu32 ser_read( ser_handler id, u8* dest, u32 maxsize );\r\nint ser_read_byte( ser_handler id );\r\nu32 ser_write( ser_handler id, const u8 *src, u32 size );\r\nu32 ser_write_byte( ser_handler id, u8 data );\r\nvoid ser_set_timeout_ms( ser_handler id, u32 timeout );\r\n\r\nint ser_setupEx( ser_handler id, u32 baud, int databits, int parity, int stopbits, int Mode );\r\n\r\nextern int read_bytes( uint8_t *pData, uint32_t size );\r\nint ser_port_is_ready( const char* sername );\r\n\r\n\r\n#endif\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld/serial_posix.c",
    "content": "// Serial inteface implementation for POSIX-compliant systems\r\n\r\n#include \"serial.h\"\r\n#include <stdio.h>\r\n#include <string.h>\r\n#include <unistd.h>\r\n#include <fcntl.h>\r\n#include <errno.h>\r\n#include <termios.h>\r\n#include <sys/select.h>\r\n#include <sys/time.h>\r\n#include <sys/types.h>\r\n\r\nstatic u32 ser_timeout = SER_INF_TIMEOUT;\r\n\r\n// Open the serial port\r\nser_handler ser_open( const char* sername )\r\n{\r\n  int fd;\r\n\r\n  if( ( fd = open( sername, O_RDWR | O_NOCTTY | O_NDELAY | O_NONBLOCK) ) == -1 )\r\n    perror( \"ser_open: unable to open port\" );\r\n  else\r\n    fcntl( fd, F_SETFL, 0 );\r\n  return ( ser_handler )fd;\r\n}\r\n\r\n// Close the serial port\r\nvoid ser_close( ser_handler id )\r\n{\r\n  close( ( int )id );\r\n}\r\n\r\n// Helper function: get baud ID from actual baud rate\r\n#define BAUDCASE(x)  case x: return B##x\r\nstatic u32 ser_baud_to_id( u32 baud )\r\n{\r\n  switch( baud )\r\n  {\r\n    BAUDCASE( 1200 );\r\n    BAUDCASE( 1800 );\r\n    BAUDCASE( 2400 );\r\n    BAUDCASE( 4800 );\r\n    BAUDCASE( 9600 );\r\n    BAUDCASE( 19200 );\r\n    BAUDCASE( 38400 );\r\n    BAUDCASE( 57600 );\r\n    BAUDCASE( 115200 );\r\n    BAUDCASE( 230400 );\r\n  }\r\n  return 0;\r\n}\r\n\r\n// Helper function: get number of bits ID from actual number of bits\r\n#define NBCASE(x) case x: return CS##x\r\nstatic int ser_number_of_bits_to_id( int nb )\r\n{\r\n  switch( nb )\r\n  {\r\n    NBCASE( 5 );\r\n    NBCASE( 6 );\r\n    NBCASE( 7 );\r\n    NBCASE( 8 );\r\n  }\r\n  return 0;\r\n}\r\n\r\nint ser_setup( ser_handler id, u32 baud, int databits, int parity, int stopbits )\r\n{\r\n  struct termios termdata;\r\n  int hnd = ( int )id;\r\n\r\n  usleep( 200000 );\r\n  tcgetattr( hnd, &termdata );\r\n\r\n  // Baud rate\r\n  cfsetispeed( &termdata, ser_baud_to_id( baud ) );\r\n  cfsetospeed( &termdata, ser_baud_to_id( baud ) );\r\n\r\n  // Parity / stop bits\r\n  termdata.c_cflag &= ~CSTOPB;\r\n  if( parity == SER_PARITY_NONE ) // no parity\r\n  {\r\n    termdata.c_cflag &= ~PARENB;\r\n  }\r\n  else if( parity == SER_PARITY_EVEN ) // even parity\r\n  {\r\n    termdata.c_cflag |= PARENB;\r\n    termdata.c_cflag &= ~PARODD;\r\n  }\r\n  else if( parity == SER_PARITY_ODD ) // odd parity\r\n  {\r\n    termdata.c_cflag |= PARENB;\r\n    termdata.c_cflag |= PARODD;\r\n  }\r\n\r\n   // Data bits\r\n  termdata.c_cflag |= ( CLOCAL | CREAD );\r\n  termdata.c_cflag &= ~CSIZE;\r\n  termdata.c_cflag |= ser_number_of_bits_to_id( databits );\r\n\r\n  // Disable HW and SW flow control\r\n  termdata.c_cflag &= ~CRTSCTS;\r\n  termdata.c_iflag &= ~( IXON | IXOFF | IXANY );\r\n\r\n  // Raw input\r\n  termdata.c_lflag &= ~( ICANON | ECHO | ECHOE | ISIG );\r\n\r\n  // Raw output\r\n  termdata.c_oflag &= ~OPOST;\r\n\r\n  // Check and strip parity bit\r\n  if( parity == SER_PARITY_NONE )\r\n    termdata.c_iflag &= ~( INPCK | ISTRIP );\r\n  else\r\n    termdata.c_iflag |= ( INPCK | ISTRIP );\r\n\r\n  // Setup timeouts\r\n  termdata.c_cc[ VMIN ]  = 1;\r\n  termdata.c_cc[ VTIME ] = 0;\r\n\r\n  // Set the attibutes now\r\n  tcsetattr( hnd, TCSANOW, &termdata );\r\n\r\n  // Flush everything\r\n  tcflush( hnd, TCIOFLUSH );\r\n\r\n  // And set blocking mode by default\r\n  fcntl( id, F_SETFL, 0 );\r\n\r\n  return 0;\r\n}\r\n\r\n\r\nint ser_setupEx( ser_handler id, u32 baud, int databits, int parity, int stopbits, int Mode )\r\n{\r\n  struct termios termdata;\r\n  int hnd = ( int )id;\r\n\r\n  usleep( 200000 );\r\n  tcgetattr( hnd, &termdata );\r\n\r\n  // Baud rate\r\n  cfsetispeed( &termdata, ser_baud_to_id( baud ) );\r\n  cfsetospeed( &termdata, ser_baud_to_id( baud ) );\r\n\r\n  // Parity / stop bits\r\n  termdata.c_cflag &= ~CSTOPB;\r\n  if( parity == SER_PARITY_NONE ) // no parity\r\n  {\r\n    termdata.c_cflag &= ~PARENB;\r\n  }\r\n  else if( parity == SER_PARITY_EVEN ) // even parity\r\n  {\r\n    termdata.c_cflag |= PARENB;\r\n    termdata.c_cflag &= ~PARODD;\r\n  }\r\n  else if( parity == SER_PARITY_ODD ) // odd parity\r\n  {\r\n    termdata.c_cflag |= PARENB;\r\n    termdata.c_cflag |= PARODD;\r\n  }\r\n\r\n   // Data bits\r\n  termdata.c_cflag |= ( CLOCAL | CREAD );\r\n  termdata.c_cflag &= ~CSIZE;\r\n  termdata.c_cflag |= ser_number_of_bits_to_id( databits );\r\n\r\n\r\n\r\n  // Disable HW and SW flow control\r\n  termdata.c_cflag &= ~CRTSCTS;\r\n  termdata.c_iflag &= ~( IXON | IXOFF | IXANY );\r\n\r\n\r\n  if( Mode == 0 )\r\n    termdata.c_cflag &= ~CRTSCTS;\r\n  else\r\n    termdata.c_cflag |= CRTSCTS;    /* Also called CRTSCTS */\r\n\r\n    \r\n\r\n  // Raw input\r\n  termdata.c_lflag &= ~( ICANON | ECHO | ECHOE | ISIG );\r\n\r\n  // Raw output\r\n  termdata.c_oflag &= ~OPOST;\r\n\r\n\r\n  // Check and strip parity bit\r\n  if( parity == SER_PARITY_NONE )\r\n    termdata.c_iflag &= ~( INPCK | ISTRIP );\r\n  else\r\n    termdata.c_iflag |= ( INPCK | ISTRIP );\r\n\r\n  // Setup timeouts\r\n  termdata.c_cc[ VMIN ]  = 0;\r\n  termdata.c_cc[ VTIME ] = 1;\r\n\r\n  // Set the attibutes now\r\n  tcsetattr( hnd, TCSANOW, &termdata );\r\n\r\n  // Flush everything\r\n  tcflush( hnd, TCIOFLUSH );\r\n\r\n  // And set blocking mode by default\r\n  //fcntl( id, F_SETFL, 0 );\r\n\r\n  return 0;\r\n}\r\n\r\n\r\n\r\n// Read up to the specified number of bytes, return bytes actually read\r\nu32 ser_read( ser_handler id, u8* dest, u32 maxsize )\r\n{\r\n  if( ser_timeout == SER_INF_TIMEOUT )\r\n    return ( u32 )read( ( int )id, dest, maxsize );\r\n  else\r\n  {\r\n    fd_set readfs;\r\n    struct timeval tv;\r\n    int retval;\r\n\r\n    FD_ZERO( &readfs );\r\n    FD_SET( ( int )id, &readfs );\r\n    tv.tv_sec = ser_timeout / 1000000;\r\n    tv.tv_usec = ( ser_timeout % 1000000 ) * 1000;\r\n    retval = select( ( int )id + 1, &readfs, NULL, NULL, &tv );\r\n    if( retval == -1 || retval == 0 )\r\n      return 0;\r\n    else \r\n      return ( u32 )read( ( int )id, dest, maxsize );\r\n  }\r\n}\r\n\r\n// Read a single byte and return it (or -1 for error)\r\nint ser_read_byte( ser_handler id )\r\n{\r\n  u8 data;\r\n  int res = ser_read( id, &data, 1 );\r\n\r\n  return res == 1 ? data : -1;\r\n}\r\n\r\n// Write up to the specified number of bytes, return bytes actually written\r\nu32 ser_write( ser_handler id, const u8 *src, u32 size )\r\n{\r\n  u32 res;\r\n  \r\n  res = ( u32 )write( ( int )id, src, size );\r\n  return res;\r\n}\r\n\r\n// Write a byte to the serial port\r\nu32 ser_write_byte( ser_handler id, u8 data )\r\n{\r\n  return ( u32 )write( id, &data, 1 );\r\n}\r\n\r\n// Set communication timeout\r\nvoid ser_set_timeout_ms( ser_handler id, u32 timeout )\r\n{\r\n  ser_timeout = timeout;\r\n}\r\n\r\n\r\nint ser_port_is_ready( const char* sername )\r\n{\r\n\r\n  int fd;\r\n\r\n  if( ( fd = open( sername, O_RDWR | O_NOCTTY | O_NDELAY | O_NONBLOCK) ) == -1 )\r\n  {\r\n    return 0;\r\n  }\r\n  else\r\n  {\r\n    close(fd);\r\n    return 1;\r\n  }\r\n}"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld/serial_win32.c",
    "content": "// Serial inteface implementation for POSIX-compliant systems\r\n\r\n#include <windows.h>\r\n#include <string.h>\r\n#include <stdio.h>\r\n#include \"type.h\"\r\n#include \"serial.h\"\r\n\r\n#define WIN_ERROR     ( HANDLE )-1\r\n#define WIN_MAX_PORT_NAME   1024\r\n\r\n// Helper: set timeout\r\nstatic int ser_win32_set_timeouts( HANDLE hComm, DWORD ri, DWORD rtm, DWORD rtc, DWORD wtm, DWORD wtc )\r\n{   \r\n  COMMTIMEOUTS timeouts;\r\n  \r\n  if( GetCommTimeouts( hComm, &timeouts ) == FALSE )\r\n  {\r\n    CloseHandle( hComm );\r\n    return SER_ERR;\r\n  }\r\n  timeouts.ReadIntervalTimeout = ri;\r\n  timeouts.ReadTotalTimeoutConstant = rtm;\r\n  timeouts.ReadTotalTimeoutMultiplier = rtc;\r\n  timeouts.WriteTotalTimeoutConstant = wtm;\r\n  timeouts.WriteTotalTimeoutMultiplier = wtc;\r\n\tif( SetCommTimeouts( hComm, &timeouts ) == FALSE )\r\n\t{\r\n\t  CloseHandle( hComm );\r\n\t  return SER_ERR;\r\n  }               \r\n  \r\n  return SER_OK;\r\n}\r\n\r\n// Open the serial port\r\nser_handler ser_open( const char* sername )\r\n{\r\n  char portname[ WIN_MAX_PORT_NAME + 1 ];\r\n  wchar_t pname[ WIN_MAX_PORT_NAME + 1 ];\r\n  HANDLE hComm;\r\n  \r\n  portname[ 0 ] = portname[ WIN_MAX_PORT_NAME ] = '\\0';\r\n  _snprintf( portname, WIN_MAX_PORT_NAME, \"\\\\\\\\.\\\\%s\", sername );\r\n  //swprintf( portname, WIN_MAX_PORT_NAME, \"\\\\\\\\.\\\\%s\", sername );\r\n\r\n  mbstowcs(pname, portname, WIN_MAX_PORT_NAME);\r\n\r\n#ifdef _MINGW_GCC_\r\n  hComm = CreateFile( portname, GENERIC_READ | GENERIC_WRITE, 0, 0, OPEN_EXISTING, 0, 0 );\r\n#else\r\n  hComm = CreateFile( pname, GENERIC_READ | GENERIC_WRITE, 0, 0, OPEN_EXISTING, 0, 0 );\r\n#endif\r\n  if( hComm == INVALID_HANDLE_VALUE )\r\n  {\r\n#ifdef _MINGW_GCC_\r\n    printf(\"hComm err : %s\\n\", portname);\r\n#else\r\n    printf(\"hComm err : %s\\n\", pname);\r\n#endif\r\n    return WIN_ERROR;\r\n  }\r\n  if( !SetupComm( hComm, 2048, 2048 ) )\r\n    return WIN_ERROR;\r\n  return hComm;\r\n}\r\n\r\n// Close the serial port\r\nvoid ser_close( ser_handler id )\r\n{\r\n  CloseHandle( id );\r\n}\r\n\r\nint ser_setup( ser_handler id, u32 baud, int databits, int parity, int stopbits )\r\n{\r\n  HANDLE hComm = ( HANDLE )id;\r\n  DCB dcb;\r\n  \r\n\tif( GetCommState( hComm, &dcb ) == FALSE )\r\n\t{\r\n\t\tCloseHandle( hComm );\r\n\t\treturn SER_ERR;\r\n\t}\r\n  dcb.BaudRate = baud;\r\n  dcb.ByteSize = databits;\r\n  dcb.Parity = parity == SER_PARITY_NONE ? NOPARITY : ( parity == SER_PARITY_EVEN ? EVENPARITY : ODDPARITY );\r\n  dcb.StopBits = stopbits == SER_STOPBITS_1 ? ONESTOPBIT : ( stopbits == SER_STOPBITS_1_5 ? ONE5STOPBITS : TWOSTOPBITS );\r\n  dcb.fBinary = TRUE;\r\n  dcb.fDsrSensitivity = FALSE;\r\n  dcb.fParity = parity != SER_PARITY_NONE ? TRUE : FALSE;\r\n  dcb.fOutX = FALSE;\r\n  dcb.fInX = FALSE;\r\n  dcb.fNull = FALSE;\r\n  /**/ dcb.fAbortOnError = FALSE;\r\n  dcb.fOutxCtsFlow = FALSE;\r\n  dcb.fOutxDsrFlow = FALSE;\r\n  dcb.fDtrControl = DTR_CONTROL_DISABLE;\r\n  dcb.fDsrSensitivity = FALSE;\r\n  dcb.fRtsControl = RTS_CONTROL_DISABLE;\r\n  dcb.fOutxCtsFlow = FALSE;\r\n  if( SetCommState( hComm, &dcb ) == 0 )\r\n  {\r\n    CloseHandle( hComm );\r\n    return SER_ERR;\r\n  }\r\n  \r\n  if( ser_win32_set_timeouts( hComm, 0, 0, 0, 0, 0 ) == SER_ERR )\r\n  {\r\n    CloseHandle( hComm );\r\n    return SER_ERR;\r\n  }\r\n  \r\n  FlushFileBuffers( hComm );\r\n\r\n  return SER_OK;\r\n}\r\n\r\n\r\nint ser_setupEx( ser_handler id, u32 baud, int databits, int parity, int stopbits, int Mode )\r\n{\r\n  HANDLE hComm = ( HANDLE )id;\r\n  DCB dcb;\r\n  \r\n  if( GetCommState( hComm, &dcb ) == FALSE )\r\n  {\r\n    CloseHandle( hComm );\r\n    return SER_ERR;\r\n  }\r\n  dcb.BaudRate = baud;\r\n  dcb.ByteSize = databits;\r\n  dcb.Parity = parity == SER_PARITY_NONE ? NOPARITY : ( parity == SER_PARITY_EVEN ? EVENPARITY : ODDPARITY );\r\n  dcb.StopBits = stopbits == SER_STOPBITS_1 ? ONESTOPBIT : ( stopbits == SER_STOPBITS_1_5 ? ONE5STOPBITS : TWOSTOPBITS );\r\n  dcb.fBinary = TRUE;\r\n  dcb.fDsrSensitivity = FALSE;\r\n  dcb.fParity = parity != SER_PARITY_NONE ? TRUE : FALSE;\r\n  dcb.fOutX = FALSE;\r\n  dcb.fInX = FALSE;\r\n  dcb.fNull = FALSE;\r\n  /**/ dcb.fAbortOnError = FALSE;\r\n  dcb.fOutxCtsFlow = FALSE;\r\n  dcb.fOutxDsrFlow = FALSE;\r\n  dcb.fDtrControl = DTR_CONTROL_DISABLE;\r\n  dcb.fDsrSensitivity = FALSE;\r\n  \r\n  if( Mode == 0 )\r\n    dcb.fRtsControl = RTS_CONTROL_DISABLE;\r\n  else\r\n    dcb.fRtsControl = RTS_CONTROL_ENABLE;\r\n    \r\n  dcb.fOutxCtsFlow = FALSE;\r\n  if( SetCommState( hComm, &dcb ) == 0 )\r\n  {\r\n    CloseHandle( hComm );\r\n    return SER_ERR;\r\n  }\r\n  \r\n  if( ser_win32_set_timeouts( hComm, 0, 0, 0, 0, 0 ) == SER_ERR )\r\n  {\r\n    CloseHandle( hComm );\r\n    return SER_ERR;\r\n  }\r\n  \r\n  FlushFileBuffers( hComm );\r\n\r\n  return SER_OK;\r\n}\r\n\r\n\r\n// Read up to the specified number of bytes, return bytes actually read\r\nu32 ser_read( ser_handler id, u8* dest, u32 maxsize )\r\n{\r\n  HANDLE hComm = ( HANDLE )id;\r\n  DWORD readbytes;\r\n  \r\n  if( ReadFile( hComm, dest, maxsize, &readbytes, NULL ) == FALSE )\r\n    return 0;\r\n  return readbytes;\r\n}\r\n\r\n// Read a single byte and return it (or -1 for error)\r\nint ser_read_byte( ser_handler id )\r\n{\r\n  u8 data;\r\n  int res = ser_read( id, &data, 1 );\r\n\r\n  //printf( \"READ %02X, res is %d\\n\", data, res );\r\n  return res == 1 ? data : -1;\r\n}\r\n\r\n// Write up to the specified number of bytes, return bytes actually written\r\nu32 ser_write( ser_handler id, const u8 *src, u32 size )\r\n{\r\n  HANDLE hComm = ( HANDLE )id;\r\n\tDWORD written;\r\n\t\r\n  if( WriteFile( hComm, src, size, &written, NULL ) == FALSE )\r\n    return 0;\r\n  return written;\r\n}\r\n\r\n// Write a byte to the serial port\r\nu32 ser_write_byte( ser_handler id, u8 data )\r\n{\r\n  return ser_write( id, &data, 1 );\r\n}\r\n\r\n// Set communication timeout\r\nvoid ser_set_timeout_ms( ser_handler id, u32 timeout )\r\n{\r\n  if( timeout == SER_NO_TIMEOUT )\r\n    ser_win32_set_timeouts( id, MAXDWORD, 0, 0, 0, 0 );\r\n  else if( timeout == SER_INF_TIMEOUT )\r\n    ser_win32_set_timeouts( id, 0, 0, 0, 0, 0 );\r\n  else\r\n    ser_win32_set_timeouts( id, 0, 0, timeout, 0, 0 );\r\n}\r\n\r\nint ser_port_is_ready( const char* sername )\r\n{\r\n  char portname[ WIN_MAX_PORT_NAME + 1 ];\r\n  wchar_t pname[ WIN_MAX_PORT_NAME + 1 ];\r\n  HANDLE hComm;\r\n\r\n  portname[ 0 ] = portname[ WIN_MAX_PORT_NAME ] = '\\0';\r\n  _snprintf( portname, WIN_MAX_PORT_NAME, \"\\\\\\\\.\\\\%s\", sername );\r\n  //swprintf( portname, WIN_MAX_PORT_NAME, \"\\\\\\\\.\\\\%s\", sername );\r\n\r\n  mbstowcs(pname, portname, WIN_MAX_PORT_NAME);\r\n\r\n#ifdef _MINGW_GCC_\r\n  hComm = CreateFile(portname, GENERIC_READ | GENERIC_WRITE, 0, 0, OPEN_EXISTING, 0, 0 );\r\n#else\r\n  hComm = CreateFile(pname, GENERIC_READ | GENERIC_WRITE, 0, 0, OPEN_EXISTING, 0, 0 );\r\n#endif\r\n  if( hComm == INVALID_HANDLE_VALUE )\r\n  {\r\n    return 0;\r\n  }\r\n  else\r\n  {\r\n    CloseHandle( hComm );\r\n\r\n    return 1;\r\n  }\r\n}\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld/type.h",
    "content": "// Portable types\r\n\r\n#ifndef __TYPE_H_\r\n#define __TYPE_H_\r\n\r\n#include <stdint.h>\r\n\r\n#ifdef WIN32_BUILD\r\ntypedef char s8;\r\ntypedef unsigned char u8;\r\n\r\ntypedef short s16;\r\ntypedef unsigned short u16;\r\n\r\ntypedef int s32;\r\ntypedef unsigned int u32;\r\n\r\ntypedef long s64;\r\ntypedef unsigned long u64;\r\n#else\r\ntypedef char s8;\r\ntypedef unsigned char u8;\r\n\r\ntypedef short s16;\r\ntypedef unsigned short u16;\r\n\r\ntypedef long s32;\r\ntypedef unsigned long u32;\r\n\r\ntypedef long long s64;\r\ntypedef unsigned long long u64;\r\n#endif\r\n\r\n// Define serial port \"handle\" type for each platform\r\n// [TODO] for now, only UNIX is supported\r\n#ifdef WIN32_BUILD\r\n#include <windows.h>\r\ntypedef HANDLE ser_handler;\r\n#else // assume POSIX here\r\ntypedef int ser_handler;\r\n#endif\r\n\r\n\r\n#ifndef TRUE\r\n#define TRUE  1\r\n#endif\r\n\r\n#ifndef FALSE \r\n#define FALSE 0\r\n#endif\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/.cproject",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"no\"?>\r\n<?fileVersion 4.0.0?><cproject storage_type_id=\"org.eclipse.cdt.core.XmlProjectDescriptionStorage\">\r\n\t<storageModule moduleId=\"org.eclipse.cdt.core.settings\">\r\n\t\t<cconfiguration id=\"cdt.managedbuild.toolchain.gnu.base.670151943\">\r\n\t\t\t<storageModule buildSystemId=\"org.eclipse.cdt.managedbuilder.core.configurationDataProvider\" id=\"cdt.managedbuild.toolchain.gnu.base.670151943\" moduleId=\"org.eclipse.cdt.core.settings\" name=\"Default\">\r\n\t\t\t\t<externalSettings/>\r\n\t\t\t\t<extensions>\r\n\t\t\t\t\t<extension id=\"org.eclipse.cdt.core.ELF\" point=\"org.eclipse.cdt.core.BinaryParser\"/>\r\n\t\t\t\t\t<extension id=\"org.eclipse.cdt.core.GASErrorParser\" point=\"org.eclipse.cdt.core.ErrorParser\"/>\r\n\t\t\t\t\t<extension id=\"org.eclipse.cdt.core.GmakeErrorParser\" point=\"org.eclipse.cdt.core.ErrorParser\"/>\r\n\t\t\t\t\t<extension id=\"org.eclipse.cdt.core.GLDErrorParser\" point=\"org.eclipse.cdt.core.ErrorParser\"/>\r\n\t\t\t\t\t<extension id=\"org.eclipse.cdt.core.CWDLocator\" point=\"org.eclipse.cdt.core.ErrorParser\"/>\r\n\t\t\t\t\t<extension id=\"org.eclipse.cdt.core.GCCErrorParser\" point=\"org.eclipse.cdt.core.ErrorParser\"/>\r\n\t\t\t\t</extensions>\r\n\t\t\t</storageModule>\r\n\t\t\t<storageModule moduleId=\"cdtBuildSystem\" version=\"4.0.0\">\r\n\t\t\t\t<configuration artifactName=\"${ProjName}\" buildProperties=\"\" description=\"\" id=\"cdt.managedbuild.toolchain.gnu.base.670151943\" name=\"Default\" parent=\"org.eclipse.cdt.build.core.emptycfg\">\r\n\t\t\t\t\t<folderInfo id=\"cdt.managedbuild.toolchain.gnu.base.670151943.1975977434\" name=\"/\" resourcePath=\"\">\r\n\t\t\t\t\t\t<toolChain id=\"cdt.managedbuild.toolchain.gnu.base.1623739321\" name=\"Linux GCC\" superClass=\"cdt.managedbuild.toolchain.gnu.base\">\r\n\t\t\t\t\t\t\t<targetPlatform archList=\"all\" binaryParser=\"org.eclipse.cdt.core.ELF\" id=\"cdt.managedbuild.target.gnu.platform.base.100128838\" name=\"Debug Platform\" osList=\"linux,hpux,aix,qnx\" superClass=\"cdt.managedbuild.target.gnu.platform.base\"/>\r\n\t\t\t\t\t\t\t<builder id=\"cdt.managedbuild.target.gnu.builder.base.1495015087\" keepEnvironmentInBuildfile=\"false\" managedBuildOn=\"false\" name=\"Gnu Make Builder\" superClass=\"cdt.managedbuild.target.gnu.builder.base\"/>\r\n\t\t\t\t\t\t\t<tool id=\"cdt.managedbuild.tool.gnu.archiver.base.2110478634\" name=\"GCC Archiver\" superClass=\"cdt.managedbuild.tool.gnu.archiver.base\"/>\r\n\t\t\t\t\t\t\t<tool id=\"cdt.managedbuild.tool.gnu.cpp.compiler.base.1023283233\" name=\"GCC C++ Compiler\" superClass=\"cdt.managedbuild.tool.gnu.cpp.compiler.base\">\r\n\t\t\t\t\t\t\t\t<inputType id=\"cdt.managedbuild.tool.gnu.cpp.compiler.input.1420409330\" superClass=\"cdt.managedbuild.tool.gnu.cpp.compiler.input\"/>\r\n\t\t\t\t\t\t\t</tool>\r\n\t\t\t\t\t\t\t<tool id=\"cdt.managedbuild.tool.gnu.c.compiler.base.1069134073\" name=\"GCC C Compiler\" superClass=\"cdt.managedbuild.tool.gnu.c.compiler.base\">\r\n\t\t\t\t\t\t\t\t<inputType id=\"cdt.managedbuild.tool.gnu.c.compiler.input.1054310859\" superClass=\"cdt.managedbuild.tool.gnu.c.compiler.input\"/>\r\n\t\t\t\t\t\t\t</tool>\r\n\t\t\t\t\t\t\t<tool id=\"cdt.managedbuild.tool.gnu.c.linker.base.532014838\" name=\"GCC C Linker\" superClass=\"cdt.managedbuild.tool.gnu.c.linker.base\"/>\r\n\t\t\t\t\t\t\t<tool id=\"cdt.managedbuild.tool.gnu.cpp.linker.base.244388505\" name=\"GCC C++ Linker\" superClass=\"cdt.managedbuild.tool.gnu.cpp.linker.base\">\r\n\t\t\t\t\t\t\t\t<inputType id=\"cdt.managedbuild.tool.gnu.cpp.linker.input.637409581\" superClass=\"cdt.managedbuild.tool.gnu.cpp.linker.input\">\r\n\t\t\t\t\t\t\t\t\t<additionalInput kind=\"additionalinputdependency\" paths=\"$(USER_OBJS)\"/>\r\n\t\t\t\t\t\t\t\t\t<additionalInput kind=\"additionalinput\" paths=\"$(LIBS)\"/>\r\n\t\t\t\t\t\t\t\t</inputType>\r\n\t\t\t\t\t\t\t</tool>\r\n\t\t\t\t\t\t\t<tool id=\"cdt.managedbuild.tool.gnu.assembler.base.770703164\" name=\"GCC Assembler\" superClass=\"cdt.managedbuild.tool.gnu.assembler.base\">\r\n\t\t\t\t\t\t\t\t<inputType id=\"cdt.managedbuild.tool.gnu.assembler.input.1799729650\" superClass=\"cdt.managedbuild.tool.gnu.assembler.input\"/>\r\n\t\t\t\t\t\t\t</tool>\r\n\t\t\t\t\t\t</toolChain>\r\n\t\t\t\t\t</folderInfo>\r\n\t\t\t\t</configuration>\r\n\t\t\t</storageModule>\r\n\t\t\t<storageModule moduleId=\"org.eclipse.cdt.core.externalSettings\"/>\r\n\t\t</cconfiguration>\r\n\t</storageModule>\r\n\t<storageModule moduleId=\"scannerConfiguration\">\r\n\t\t<autodiscovery enabled=\"true\" problemReportingEnabled=\"true\" selectedProfileId=\"\"/>\r\n\t</storageModule>\r\n\t<storageModule moduleId=\"cdtBuildSystem\" version=\"4.0.0\">\r\n\t\t<project id=\"opencr_ld.null.270043\" name=\"opencr_ld\"/>\r\n\t</storageModule>\r\n\t<storageModule moduleId=\"org.eclipse.cdt.core.LanguageSettingsProviders\"/>\r\n</cproject>\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/.gitignore",
    "content": "/opencr_ld_shell\n.vscode\n.settings"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/.project",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\r\n<projectDescription>\r\n\t<name>opencr_ld</name>\r\n\t<comment></comment>\r\n\t<projects>\r\n\t</projects>\r\n\t<buildSpec>\r\n\t\t<buildCommand>\r\n\t\t\t<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>\r\n\t\t\t<triggers>clean,full,incremental,</triggers>\r\n\t\t\t<arguments>\r\n\t\t\t</arguments>\r\n\t\t</buildCommand>\r\n\t\t<buildCommand>\r\n\t\t\t<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>\r\n\t\t\t<triggers>full,incremental,</triggers>\r\n\t\t\t<arguments>\r\n\t\t\t</arguments>\r\n\t\t</buildCommand>\r\n\t</buildSpec>\r\n\t<natures>\r\n\t\t<nature>org.eclipse.cdt.core.cnature</nature>\r\n\t\t<nature>org.eclipse.cdt.core.ccnature</nature>\r\n\t\t<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>\r\n\t\t<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>\r\n\t</natures>\r\n</projectDescription>\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/Makefile",
    "content": "\n\n\nall: clean  opencr_ld\n\n\nSRCS  = main.c\nSRCS += opencr_ld.c\nSRCS += serial_posix.c\nSRCS += ./msg/msg.c\n\n\nopencr_ld:\n\tgcc -o opencr_ld_shell $(SRCS)\n\nclean:\n\trm -f opencr_ld_shell\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/README.md",
    "content": "Please refer to the TurtleBot3 eManual Quick Start Guide > OpenCR Setup section below.\n\nSelect the correct ROS distribution first.\n\nhttps://emanual.robotis.com/docs/en/platform/turtlebot3/opencr_setup/#opencr-setup"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/install_opencr.sh",
    "content": "#! /bin/bash\n\necho \"Install OpenCR Update V171016\"\n\nif (($#==2))\nthen\n  mkdir opencr_update\n  tar -xvf opencr_update.tar.bz2 -C opencr_update\n  cd ./opencr_update\nelse\n  echo \"wrong parameter \"\n  echo \"install_opencr.sh <port> burger\"\n  echo \"install_opencr.sh <port> waffle\"\nfi\n\nexit\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/main.c",
    "content": "/*\r\n * OpenCR Loader\r\n *\r\n * by Baram\r\n * by PBPH\r\n * by http://oroca.org\r\n */\r\n\r\n\r\n#include <stdio.h>\r\n#include <stdlib.h>\r\n#include <string.h>\r\n#include <errno.h>\r\n#include <limits.h>\r\n#include \"opencr_ld.h\"\r\n\r\n\r\n/*\r\n  opencr_ld_shell make fw.bin fw_name fw_ver\r\n  opencr_ld_shell view fw_name\r\n*/\r\n\r\n\r\n\r\n\r\n\r\nvoid make_firmware( int argc, const char **argv );\r\nvoid view_firmware( int argc, const char **argv );\r\n\r\n\r\n\r\n/*---------------------------------------------------------------------------\r\n     TITLE   : main\r\n     WORK    :\r\n---------------------------------------------------------------------------*/\r\nint main( int argc, const char **argv )\r\n{\r\n  u8 not_flashing=0;\r\n  u8 send_go_command=0;\r\n  u8 boot_mode = 0;\r\n  u8 minor, major;\r\n  u16 version;\r\n  long baud;\r\n\r\n\r\n  printf(\"opencr_ld_shell ver 1.0.1\\n\");\r\n\r\n  if (argc == 5 && strcmp(argv[ 1 ], \"make\") == 0)\r\n  {\r\n    make_firmware(argc, argv);\r\n    return 0;\r\n  }\r\n\r\n  if (argc == 3 && strcmp(argv[ 1 ], \"view\") == 0)\r\n  {\r\n    view_firmware(argc, argv);\r\n    return 0;\r\n  }\r\n\r\n  if( argc < 4 )\r\n  {\r\n    fprintf( stderr, \"Usage: opencl_ld <port> <baud> <binary image name> [<0|1 to send Go command to new flashed app>]\\n\" );\r\n    fprintf( stderr, \"       opencr_ld_shell make fw.bin burger V171017R1\\n\" );\r\n    fprintf( stderr, \"       opencr_ld_shell view fw_name\\n\" );\r\n\r\n    exit( 1 );\r\n  }\r\n\r\n  errno = 0;\r\n  baud = strtol( argv[ 2 ], NULL, 10 );\r\n  if( ( errno == ERANGE && ( baud == LONG_MAX || baud == LONG_MIN ) ) || ( errno != 0 && baud == 0 ) || ( baud < 0 ) )\r\n  {\r\n    fprintf( stderr, \"Invalid baud '%s'\\n\", argv[ 2 ] );\r\n    exit( 1 );\r\n  }\r\n\r\n\r\n  opencr_ld_main( argc, argv );\r\n\r\n  return 0;\r\n}\r\n\r\nvoid make_firmware( int argc, const char **argv )\r\n{\r\n  FILE    *fp;\r\n  uint32_t fpsize;\r\n  int      fw_size;\r\n\r\n  char     *fw_ver_str;\r\n  char     *fw_input_str;\r\n  int      i;\r\n\r\n  opencr_fw_header_t fw_header;\r\n\r\n  printf(\"make firmware...\\n\");\r\n\r\n\r\n  if( ( fp = fopen( argv[2], \"rb\" ) ) == NULL )\r\n  {\r\n    fprintf( stderr, \"[NG] Unable to open \\t: %s\\n\", argv[ 2 ] );\r\n    exit( 1 );\r\n  }\r\n  else\r\n  {\r\n    fseek( fp, 0, SEEK_END );\r\n    fpsize = ftell( fp );\r\n    fseek(fp, 0, SEEK_SET);\r\n\r\n    printf(\"[  ] file name   \\t: %s \\r\\n\", argv[2]);\r\n    printf(\"[  ] file size   \\t: %d bytes\\r\\n\", fpsize);\r\n  }\r\n\r\n  fw_input_str = (char *)argv[2];\r\n  fw_ver_str = (char *)argv[4];\r\n  fw_size = fpsize;\r\n\r\n\r\n  memset(&fw_header, 0, sizeof(opencr_fw_header_t));\r\n\r\n  fw_header.magic_number = MAGIC_NUMBER;\r\n  fw_header.fw_size = fw_size;\r\n\r\n  strcpy(fw_header.fw_name_str, argv[3]);\r\n  strcpy(fw_header.fw_ver_str, argv[4]);\r\n\r\n  printf(\"[  ] fw_name     \\t: %s \\n\", fw_header.fw_name_str);\r\n  printf(\"[  ] fw_ver      \\t: %s \\n\", fw_header.fw_ver_str);\r\n\r\n\r\n  FILE    *fp_write;\r\n\r\n  char fw_write_name[128];\r\n\r\n  sprintf(fw_write_name, \"%s.opencr\", fw_header.fw_name_str);\r\n\r\n  if( ( fp_write = fopen( fw_write_name, \"wb\" ) ) == NULL )\r\n  {\r\n    fclose(fp);\r\n    fprintf( stderr, \"[NG] Unable to open \\t: %s\\n\", argv[ 2 ] );\r\n    exit( 1 );\r\n  }\r\n\r\n  fwrite(&fw_header, 1, sizeof(opencr_fw_header_t), fp_write);\r\n\r\n  for (i=0; i<fw_size; i++)\r\n  {\r\n    uint8_t data;\r\n\r\n    fread(&data, 1, 1, fp);\r\n    fwrite(&data, 1, 1, fp_write);\r\n  }\r\n\r\n  printf(\"[OK] finished    \\t: %d bytes\\n\", (int)(fw_size + sizeof(opencr_fw_header_t)));\r\n\r\n  fclose(fp_write);\r\n  fclose(fp);\r\n}\r\n\r\nvoid view_firmware( int argc, const char **argv )\r\n{\r\n  FILE    *fp;\r\n  uint32_t fpsize;\r\n  int      fw_size;\r\n\r\n  char     *fw_ver_str;\r\n  char     *fw_input_str;\r\n\r\n  opencr_fw_header_t fw_header;\r\n\r\n  printf(\"view firmware...\\n\");\r\n\r\n\r\n  if( ( fp = fopen( argv[2], \"rb\" ) ) == NULL )\r\n  {\r\n    fprintf( stderr, \"[NG] Unable to open \\t: %s\\n\", argv[ 2 ] );\r\n    exit( 1 );\r\n  }\r\n  else\r\n  {\r\n    fseek( fp, 0, SEEK_END );\r\n    fpsize = ftell( fp );\r\n    fseek(fp, 0, SEEK_SET);\r\n\r\n    printf(\"[  ] file name   \\t: %s \\r\\n\", argv[2]);\r\n    printf(\"[  ] file size   \\t: %d KB\\r\\n\", fpsize/1024);\r\n  }\r\n\r\n  fw_size = fpsize;\r\n\r\n\r\n  fread(&fw_header, 1, sizeof(opencr_fw_header_t), fp);\r\n\r\n  if (fw_header.magic_number == MAGIC_NUMBER)\r\n  {\r\n    printf(\"[  ] fw_name     \\t: %s \\n\", fw_header.fw_name_str);\r\n    printf(\"[  ] fw_ver      \\t: %s \\n\", fw_header.fw_ver_str);\r\n  }\r\n  else\r\n  {\r\n    printf(\"[NG] not opencr fw \\n\");\r\n  }\r\n\r\n\r\n  fclose(fp);\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/msg/def.h",
    "content": "/*\n *  def.h\n *\n *  Created on: 2016. 5. 14.\n *      Author: Baram, PBPH\n */\n\n#ifndef DEF_H\n#define DEF_H\n\n#include <stdint.h>\n#include \"def_err.h\"\n\n#ifndef BOOL\n#define BOOL uint8_t\n#endif\n\n#ifndef TRUE\n#define TRUE  1\n#endif\n\n#ifndef FALSE\n#define FALSE 0\n#endif\n\n#ifndef bool\n#define bool uint8_t\n#endif\n\n#ifndef true\n#define true  1\n#endif\n\n#ifndef false\n#define false 0\n#endif\n\n\n#include \"./mavlink/opencr_msg/mavlink.h\"\n\n\n\n\n\n\n\n#endif\n\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/msg/def_err.h",
    "content": "/*\n *  def_err.h\n *\n *  Created on: 2016. 5. 14.\n *      Author: Baram, PBPH\n */\n\n#ifndef DEF_ERR_H\n#define DEF_ERR_H\n\n#include <stdint.h>\n\n\n\ntypedef uint16_t err_code_t;\n\n\n\n\n#define OK                                  0x0000\n#define ERR_FLASH_ERROR                     0xF010\n#define ERR_FLASH_BUSY                      0xF011\n#define ERR_FLASH_ERR_TIMEOUT               0xF012\n#define ERR_FLASH_NOT_EMPTY                 0xF013\n#define ERR_FLASH_WRITE                     0xF014\n#define ERR_FLASH_READ                      0xF015\n#define ERR_FLASH_ERASE                     0xF016\n\n#define ERR_TIMEOUT                         0xF020\n#define ERR_MISMATCH_ID                     0xF021\n#define ERR_SIZE_OVER                       0xF022\n\n\n\n#endif\n\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/msg/mavlink/checksum.h",
    "content": "#ifdef __cplusplus\r\nextern \"C\" {\r\n#endif\r\n\r\n#ifndef _CHECKSUM_H_\r\n#define _CHECKSUM_H_\r\n\r\n// Visual Studio versions before 2010 don't have stdint.h, so we just error out.\r\n#if (defined _MSC_VER) && (_MSC_VER < 1600)\r\n#error \"The C-MAVLink implementation requires Visual Studio 2010 or greater\"\r\n#endif\r\n\r\n#include <stdint.h>\r\n\r\n/**\r\n *\r\n *  CALCULATE THE CHECKSUM\r\n *\r\n */\r\n\r\n#define X25_INIT_CRC 0xffff\r\n#define X25_VALIDATE_CRC 0xf0b8\r\n\r\n#ifndef HAVE_CRC_ACCUMULATE\r\n/**\r\n * @brief Accumulate the X.25 CRC by adding one char at a time.\r\n *\r\n * The checksum function adds the hash of one char at a time to the\r\n * 16 bit checksum (uint16_t).\r\n *\r\n * @param data new char to hash\r\n * @param crcAccum the already accumulated checksum\r\n **/\r\nstatic inline void crc_accumulate(uint8_t data, uint16_t *crcAccum)\r\n{\r\n        /*Accumulate one byte of data into the CRC*/\r\n        uint8_t tmp;\r\n\r\n        tmp = data ^ (uint8_t)(*crcAccum &0xff);\r\n        tmp ^= (tmp<<4);\r\n        *crcAccum = (*crcAccum>>8) ^ (tmp<<8) ^ (tmp <<3) ^ (tmp>>4);\r\n}\r\n#endif\r\n\r\n\r\n/**\r\n * @brief Initiliaze the buffer for the X.25 CRC\r\n *\r\n * @param crcAccum the 16 bit X.25 CRC\r\n */\r\nstatic inline void crc_init(uint16_t* crcAccum)\r\n{\r\n        *crcAccum = X25_INIT_CRC;\r\n}\r\n\r\n\r\n/**\r\n * @brief Calculates the X.25 checksum on a byte buffer\r\n *\r\n * @param  pBuffer buffer containing the byte array to hash\r\n * @param  length  length of the byte array\r\n * @return the checksum over the buffer bytes\r\n **/\r\nstatic inline uint16_t crc_calculate(const uint8_t* pBuffer, uint16_t length)\r\n{\r\n        uint16_t crcTmp;\r\n        crc_init(&crcTmp);\r\n\twhile (length--) {\r\n                crc_accumulate(*pBuffer++, &crcTmp);\r\n        }\r\n        return crcTmp;\r\n}\r\n\r\n\r\n/**\r\n * @brief Accumulate the X.25 CRC by adding an array of bytes\r\n *\r\n * The checksum function adds the hash of one char at a time to the\r\n * 16 bit checksum (uint16_t).\r\n *\r\n * @param data new bytes to hash\r\n * @param crcAccum the already accumulated checksum\r\n **/\r\nstatic inline void crc_accumulate_buffer(uint16_t *crcAccum, const char *pBuffer, uint16_t length)\r\n{\r\n\tconst uint8_t *p = (const uint8_t *)pBuffer;\r\n\twhile (length--) {\r\n                crc_accumulate(*p++, crcAccum);\r\n        }\r\n}\r\n\r\n#endif /* _CHECKSUM_H_ */\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/msg/mavlink/mavlink_conversions.h",
    "content": "#ifndef  _MAVLINK_CONVERSIONS_H_\r\n#define  _MAVLINK_CONVERSIONS_H_\r\n\r\n/* enable math defines on Windows */\r\n#ifdef _MSC_VER\r\n#ifndef _USE_MATH_DEFINES\r\n#define _USE_MATH_DEFINES\r\n#endif\r\n#endif\r\n#include <math.h>\r\n\r\n#ifndef M_PI_2\r\n    #define M_PI_2 ((float)asin(1))\r\n#endif\r\n\r\n/**\r\n * @file mavlink_conversions.h\r\n *\r\n * These conversion functions follow the NASA rotation standards definition file\r\n * available online.\r\n *\r\n * Their intent is to lower the barrier for MAVLink adopters to use gimbal-lock free\r\n * (both rotation matrices, sometimes called DCM, and quaternions are gimbal-lock free)\r\n * rotation representations. Euler angles (roll, pitch, yaw) will be phased out of the\r\n * protocol as widely as possible.\r\n *\r\n * @author James Goppert\r\n * @author Thomas Gubler <thomasgubler@gmail.com>\r\n */\r\n\r\n\r\n/**\r\n * Converts a quaternion to a rotation matrix\r\n *\r\n * @param quaternion a [w, x, y, z] ordered quaternion (null-rotation being 1 0 0 0)\r\n * @param dcm a 3x3 rotation matrix\r\n */\r\nMAVLINK_HELPER void mavlink_quaternion_to_dcm(const float quaternion[4], float dcm[3][3])\r\n{\r\n    double a = quaternion[0];\r\n    double b = quaternion[1];\r\n    double c = quaternion[2];\r\n    double d = quaternion[3];\r\n    double aSq = a * a;\r\n    double bSq = b * b;\r\n    double cSq = c * c;\r\n    double dSq = d * d;\r\n    dcm[0][0] = aSq + bSq - cSq - dSq;\r\n    dcm[0][1] = 2 * (b * c - a * d);\r\n    dcm[0][2] = 2 * (a * c + b * d);\r\n    dcm[1][0] = 2 * (b * c + a * d);\r\n    dcm[1][1] = aSq - bSq + cSq - dSq;\r\n    dcm[1][2] = 2 * (c * d - a * b);\r\n    dcm[2][0] = 2 * (b * d - a * c);\r\n    dcm[2][1] = 2 * (a * b + c * d);\r\n    dcm[2][2] = aSq - bSq - cSq + dSq;\r\n}\r\n\r\n\r\n/**\r\n * Converts a rotation matrix to euler angles\r\n *\r\n * @param dcm a 3x3 rotation matrix\r\n * @param roll the roll angle in radians\r\n * @param pitch the pitch angle in radians\r\n * @param yaw the yaw angle in radians\r\n */\r\nMAVLINK_HELPER void mavlink_dcm_to_euler(const float dcm[3][3], float* roll, float* pitch, float* yaw)\r\n{\r\n    float phi, theta, psi;\r\n    theta = asin(-dcm[2][0]);\r\n\r\n    if (fabsf(theta - (float)M_PI_2) < 1.0e-3f) {\r\n        phi = 0.0f;\r\n        psi = (atan2f(dcm[1][2] - dcm[0][1],\r\n                dcm[0][2] + dcm[1][1]) + phi);\r\n\r\n    } else if (fabsf(theta + (float)M_PI_2) < 1.0e-3f) {\r\n        phi = 0.0f;\r\n        psi = atan2f(dcm[1][2] - dcm[0][1],\r\n                  dcm[0][2] + dcm[1][1] - phi);\r\n\r\n    } else {\r\n        phi = atan2f(dcm[2][1], dcm[2][2]);\r\n        psi = atan2f(dcm[1][0], dcm[0][0]);\r\n    }\r\n\r\n    *roll = phi;\r\n    *pitch = theta;\r\n    *yaw = psi;\r\n}\r\n\r\n\r\n/**\r\n * Converts a quaternion to euler angles\r\n *\r\n * @param quaternion a [w, x, y, z] ordered quaternion (null-rotation being 1 0 0 0)\r\n * @param roll the roll angle in radians\r\n * @param pitch the pitch angle in radians\r\n * @param yaw the yaw angle in radians\r\n */\r\nMAVLINK_HELPER void mavlink_quaternion_to_euler(const float quaternion[4], float* roll, float* pitch, float* yaw)\r\n{\r\n    float dcm[3][3];\r\n    mavlink_quaternion_to_dcm(quaternion, dcm);\r\n    mavlink_dcm_to_euler((const float(*)[3])dcm, roll, pitch, yaw);\r\n}\r\n\r\n\r\n/**\r\n * Converts euler angles to a quaternion\r\n *\r\n * @param roll the roll angle in radians\r\n * @param pitch the pitch angle in radians\r\n * @param yaw the yaw angle in radians\r\n * @param quaternion a [w, x, y, z] ordered quaternion (null-rotation being 1 0 0 0)\r\n */\r\nMAVLINK_HELPER void mavlink_euler_to_quaternion(float roll, float pitch, float yaw, float quaternion[4])\r\n{\r\n    float cosPhi_2 = cosf(roll / 2);\r\n    float sinPhi_2 = sinf(roll / 2);\r\n    float cosTheta_2 = cosf(pitch / 2);\r\n    float sinTheta_2 = sinf(pitch / 2);\r\n    float cosPsi_2 = cosf(yaw / 2);\r\n    float sinPsi_2 = sinf(yaw / 2);\r\n    quaternion[0] = (cosPhi_2 * cosTheta_2 * cosPsi_2 +\r\n            sinPhi_2 * sinTheta_2 * sinPsi_2);\r\n    quaternion[1] = (sinPhi_2 * cosTheta_2 * cosPsi_2 -\r\n            cosPhi_2 * sinTheta_2 * sinPsi_2);\r\n    quaternion[2] = (cosPhi_2 * sinTheta_2 * cosPsi_2 +\r\n            sinPhi_2 * cosTheta_2 * sinPsi_2);\r\n    quaternion[3] = (cosPhi_2 * cosTheta_2 * sinPsi_2 -\r\n            sinPhi_2 * sinTheta_2 * cosPsi_2);\r\n}\r\n\r\n\r\n/**\r\n * Converts a rotation matrix to a quaternion\r\n * Reference:\r\n *  - Shoemake, Quaternions,\r\n *  http://www.cs.ucr.edu/~vbz/resources/quatut.pdf\r\n *\r\n * @param dcm a 3x3 rotation matrix\r\n * @param quaternion a [w, x, y, z] ordered quaternion (null-rotation being 1 0 0 0)\r\n */\r\nMAVLINK_HELPER void mavlink_dcm_to_quaternion(const float dcm[3][3], float quaternion[4])\r\n{\r\n    float tr = dcm[0][0] + dcm[1][1] + dcm[2][2];\r\n    if (tr > 0.0f) {\r\n        float s = sqrtf(tr + 1.0f);\r\n        quaternion[0] = s * 0.5f;\r\n        s = 0.5f / s;\r\n        quaternion[1] = (dcm[2][1] - dcm[1][2]) * s;\r\n        quaternion[2] = (dcm[0][2] - dcm[2][0]) * s;\r\n        quaternion[3] = (dcm[1][0] - dcm[0][1]) * s;\r\n    } else {\r\n        /* Find maximum diagonal element in dcm\r\n         * store index in dcm_i */\r\n        int dcm_i = 0;\r\n        int i;\r\n        for (i = 1; i < 3; i++) {\r\n            if (dcm[i][i] > dcm[dcm_i][dcm_i]) {\r\n                dcm_i = i;\r\n            }\r\n        }\r\n\r\n        int dcm_j = (dcm_i + 1) % 3;\r\n        int dcm_k = (dcm_i + 2) % 3;\r\n\r\n        float s = sqrtf((dcm[dcm_i][dcm_i] - dcm[dcm_j][dcm_j] -\r\n                    dcm[dcm_k][dcm_k]) + 1.0f);\r\n        quaternion[dcm_i + 1] = s * 0.5f;\r\n        s = 0.5f / s;\r\n        quaternion[dcm_j + 1] = (dcm[dcm_i][dcm_j] + dcm[dcm_j][dcm_i]) * s;\r\n        quaternion[dcm_k + 1] = (dcm[dcm_k][dcm_i] + dcm[dcm_i][dcm_k]) * s;\r\n        quaternion[0] = (dcm[dcm_k][dcm_j] - dcm[dcm_j][dcm_k]) * s;\r\n    }\r\n}\r\n\r\n\r\n/**\r\n * Converts euler angles to a rotation matrix\r\n *\r\n * @param roll the roll angle in radians\r\n * @param pitch the pitch angle in radians\r\n * @param yaw the yaw angle in radians\r\n * @param dcm a 3x3 rotation matrix\r\n */\r\nMAVLINK_HELPER void mavlink_euler_to_dcm(float roll, float pitch, float yaw, float dcm[3][3])\r\n{\r\n    float cosPhi = cosf(roll);\r\n    float sinPhi = sinf(roll);\r\n    float cosThe = cosf(pitch);\r\n    float sinThe = sinf(pitch);\r\n    float cosPsi = cosf(yaw);\r\n    float sinPsi = sinf(yaw);\r\n\r\n    dcm[0][0] = cosThe * cosPsi;\r\n    dcm[0][1] = -cosPhi * sinPsi + sinPhi * sinThe * cosPsi;\r\n    dcm[0][2] = sinPhi * sinPsi + cosPhi * sinThe * cosPsi;\r\n\r\n    dcm[1][0] = cosThe * sinPsi;\r\n    dcm[1][1] = cosPhi * cosPsi + sinPhi * sinThe * sinPsi;\r\n    dcm[1][2] = -sinPhi * cosPsi + cosPhi * sinThe * sinPsi;\r\n\r\n    dcm[2][0] = -sinThe;\r\n    dcm[2][1] = sinPhi * cosThe;\r\n    dcm[2][2] = cosPhi * cosThe;\r\n}\r\n\r\n#endif\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/msg/mavlink/mavlink_helpers.h",
    "content": "#ifndef  _MAVLINK_HELPERS_H_\r\n#define  _MAVLINK_HELPERS_H_\r\n\r\n#include \"string.h\"\r\n#include \"checksum.h\"\r\n#include \"mavlink_types.h\"\r\n#include \"mavlink_conversions.h\"\r\n\r\n#ifndef MAVLINK_HELPER\r\n#define MAVLINK_HELPER\r\n#endif\r\n\r\n/*\r\n * Internal function to give access to the channel status for each channel\r\n */\r\n#ifndef MAVLINK_GET_CHANNEL_STATUS\r\nMAVLINK_HELPER mavlink_status_t* mavlink_get_channel_status(uint8_t chan)\r\n{\r\n#ifdef MAVLINK_EXTERNAL_RX_STATUS\r\n\t// No m_mavlink_status array defined in function,\r\n\t// has to be defined externally\r\n#else\r\n\tstatic mavlink_status_t m_mavlink_status[MAVLINK_COMM_NUM_BUFFERS];\r\n#endif\r\n\treturn &m_mavlink_status[chan];\r\n}\r\n#endif\r\n\r\n/*\r\n * Internal function to give access to the channel buffer for each channel\r\n */\r\n#ifndef MAVLINK_GET_CHANNEL_BUFFER\r\nMAVLINK_HELPER mavlink_message_t* mavlink_get_channel_buffer(uint8_t chan)\r\n{\r\n\t\r\n#ifdef MAVLINK_EXTERNAL_RX_BUFFER\r\n\t// No m_mavlink_buffer array defined in function,\r\n\t// has to be defined externally\r\n#else\r\n\tstatic mavlink_message_t m_mavlink_buffer[MAVLINK_COMM_NUM_BUFFERS];\r\n#endif\r\n\treturn &m_mavlink_buffer[chan];\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Reset the status of a channel.\r\n */\r\nMAVLINK_HELPER void mavlink_reset_channel_status(uint8_t chan)\r\n{\r\n\tmavlink_status_t *status = mavlink_get_channel_status(chan);\r\n\tstatus->parse_state = MAVLINK_PARSE_STATE_IDLE;\r\n}\r\n\r\n/**\r\n * @brief Finalize a MAVLink message with channel assignment\r\n *\r\n * This function calculates the checksum and sets length and aircraft id correctly.\r\n * It assumes that the message id and the payload are already correctly set. This function\r\n * can also be used if the message header has already been written before (as in mavlink_msg_xxx_pack\r\n * instead of mavlink_msg_xxx_pack_headerless), it just introduces little extra overhead.\r\n *\r\n * @param msg Message to finalize\r\n * @param system_id Id of the sending (this) system, 1-127\r\n * @param length Message length\r\n */\r\n#if MAVLINK_CRC_EXTRA\r\nMAVLINK_HELPER uint16_t mavlink_finalize_message_chan(mavlink_message_t* msg, uint8_t system_id, uint8_t component_id, \r\n\t\t\t\t\t\t      uint8_t chan, uint8_t min_length, uint8_t length, uint8_t crc_extra)\r\n#else\r\nMAVLINK_HELPER uint16_t mavlink_finalize_message_chan(mavlink_message_t* msg, uint8_t system_id, uint8_t component_id, \r\n\t\t\t\t\t\t      uint8_t chan, uint8_t length)\r\n#endif\r\n{\r\n\t// This code part is the same for all messages;\r\n\tmsg->magic = MAVLINK_STX;\r\n\tmsg->len = length;\r\n\tmsg->sysid = system_id;\r\n\tmsg->compid = component_id;\r\n\t// One sequence number per channel\r\n\tmsg->seq = mavlink_get_channel_status(chan)->current_tx_seq;\r\n\tmavlink_get_channel_status(chan)->current_tx_seq = mavlink_get_channel_status(chan)->current_tx_seq+1;\r\n\tmsg->checksum = crc_calculate(((const uint8_t*)(msg)) + 3, MAVLINK_CORE_HEADER_LEN);\r\n\tcrc_accumulate_buffer(&msg->checksum, _MAV_PAYLOAD(msg), msg->len);\r\n#if MAVLINK_CRC_EXTRA\r\n\tcrc_accumulate(crc_extra, &msg->checksum);\r\n#endif\r\n\tmavlink_ck_a(msg) = (uint8_t)(msg->checksum & 0xFF);\r\n\tmavlink_ck_b(msg) = (uint8_t)(msg->checksum >> 8);\r\n\r\n\treturn length + MAVLINK_NUM_NON_PAYLOAD_BYTES;\r\n}\r\n\r\n\r\n/**\r\n * @brief Finalize a MAVLink message with MAVLINK_COMM_0 as default channel\r\n */\r\n#if MAVLINK_CRC_EXTRA\r\nMAVLINK_HELPER uint16_t mavlink_finalize_message(mavlink_message_t* msg, uint8_t system_id, uint8_t component_id, \r\n\t\t\t\t\t\t uint8_t min_length, uint8_t length, uint8_t crc_extra)\r\n{\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, MAVLINK_COMM_0, min_length, length, crc_extra);\r\n}\r\n#else\r\nMAVLINK_HELPER uint16_t mavlink_finalize_message(mavlink_message_t* msg, uint8_t system_id, uint8_t component_id, \r\n\t\t\t\t\t\t uint8_t length)\r\n{\r\n\treturn mavlink_finalize_message_chan(msg, system_id, component_id, MAVLINK_COMM_0, length);\r\n}\r\n#endif\r\n\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\nMAVLINK_HELPER void _mavlink_send_uart(mavlink_channel_t chan, const char *buf, uint16_t len);\r\n\r\n/**\r\n * @brief Finalize a MAVLink message with channel assignment and send\r\n */\r\n#if MAVLINK_CRC_EXTRA\r\nMAVLINK_HELPER void _mav_finalize_message_chan_send(mavlink_channel_t chan, uint8_t msgid, const char *packet, \r\n\t\t\t\t\t\t    uint8_t min_length, uint8_t length, uint8_t crc_extra)\r\n#else\r\nMAVLINK_HELPER void _mav_finalize_message_chan_send(mavlink_channel_t chan, uint8_t msgid, const char *packet, uint8_t length)\r\n#endif\r\n{\r\n\tuint16_t checksum;\r\n\tuint8_t buf[MAVLINK_NUM_HEADER_BYTES];\r\n\tuint8_t ck[2];\r\n\tmavlink_status_t *status = mavlink_get_channel_status(chan);\r\n\tbuf[0] = MAVLINK_STX;\r\n\tbuf[1] = length;\r\n\tbuf[2] = status->current_tx_seq;\r\n\tbuf[3] = mavlink_system.sysid;\r\n\tbuf[4] = mavlink_system.compid;\r\n\tbuf[5] = msgid;\r\n\tstatus->current_tx_seq++;\r\n\tchecksum = crc_calculate((const uint8_t*)&buf[1], MAVLINK_CORE_HEADER_LEN);\r\n\tcrc_accumulate_buffer(&checksum, packet, length);\r\n#if MAVLINK_CRC_EXTRA\r\n\tcrc_accumulate(crc_extra, &checksum);\r\n#endif\r\n\tck[0] = (uint8_t)(checksum & 0xFF);\r\n\tck[1] = (uint8_t)(checksum >> 8);\r\n\r\n\tMAVLINK_START_UART_SEND(chan, MAVLINK_NUM_NON_PAYLOAD_BYTES + (uint16_t)length);\r\n\t_mavlink_send_uart(chan, (const char *)buf, MAVLINK_NUM_HEADER_BYTES);\r\n\t_mavlink_send_uart(chan, packet, length);\r\n\t_mavlink_send_uart(chan, (const char *)ck, 2);\r\n\tMAVLINK_END_UART_SEND(chan, MAVLINK_NUM_NON_PAYLOAD_BYTES + (uint16_t)length);\r\n}\r\n\r\n/**\r\n * @brief re-send a message over a uart channel\r\n * this is more stack efficient than re-marshalling the message\r\n */\r\nMAVLINK_HELPER void _mavlink_resend_uart(mavlink_channel_t chan, const mavlink_message_t *msg)\r\n{\r\n\tuint8_t ck[2];\r\n\r\n\tck[0] = (uint8_t)(msg->checksum & 0xFF);\r\n\tck[1] = (uint8_t)(msg->checksum >> 8);\r\n\t// XXX use the right sequence here\r\n\r\n\tMAVLINK_START_UART_SEND(chan, MAVLINK_NUM_NON_PAYLOAD_BYTES + msg->len);\r\n\t_mavlink_send_uart(chan, (const char *)&msg->magic, MAVLINK_NUM_HEADER_BYTES);\r\n\t_mavlink_send_uart(chan, _MAV_PAYLOAD(msg), msg->len);\r\n\t_mavlink_send_uart(chan, (const char *)ck, 2);\r\n\tMAVLINK_END_UART_SEND(chan, MAVLINK_NUM_NON_PAYLOAD_BYTES + msg->len);\r\n}\r\n#endif // MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\n/**\r\n * @brief Pack a message to send it over a serial byte stream\r\n */\r\nMAVLINK_HELPER uint16_t mavlink_msg_to_send_buffer(uint8_t *buffer, const mavlink_message_t *msg)\r\n{\r\n\tmemcpy(buffer, (const uint8_t *)&msg->magic, MAVLINK_NUM_HEADER_BYTES + (uint16_t)msg->len);\r\n\r\n\tuint8_t *ck = buffer + (MAVLINK_NUM_HEADER_BYTES + (uint16_t)msg->len);\r\n\r\n\tck[0] = (uint8_t)(msg->checksum & 0xFF);\r\n\tck[1] = (uint8_t)(msg->checksum >> 8);\r\n\r\n\treturn MAVLINK_NUM_NON_PAYLOAD_BYTES + (uint16_t)msg->len;\r\n}\r\n\r\nunion __mavlink_bitfield {\r\n\tuint8_t uint8;\r\n\tint8_t int8;\r\n\tuint16_t uint16;\r\n\tint16_t int16;\r\n\tuint32_t uint32;\r\n\tint32_t int32;\r\n};\r\n\r\n\r\nMAVLINK_HELPER void mavlink_start_checksum(mavlink_message_t* msg)\r\n{\r\n\tcrc_init(&msg->checksum);\r\n}\r\n\r\nMAVLINK_HELPER void mavlink_update_checksum(mavlink_message_t* msg, uint8_t c)\r\n{\r\n\tcrc_accumulate(c, &msg->checksum);\r\n}\r\n\r\n/**\r\n * This is a varient of mavlink_frame_char() but with caller supplied\r\n * parsing buffers. It is useful when you want to create a MAVLink\r\n * parser in a library that doesn't use any global variables\r\n *\r\n * @param rxmsg    parsing message buffer\r\n * @param status   parsing starus buffer \r\n * @param c        The char to parse\r\n *\r\n * @param returnMsg NULL if no message could be decoded, the message data else\r\n * @param returnStats if a message was decoded, this is filled with the channel's stats\r\n * @return 0 if no message could be decoded, 1 on good message and CRC, 2 on bad CRC\r\n *\r\n * A typical use scenario of this function call is:\r\n *\r\n * @code\r\n * #include <mavlink.h>\r\n *\r\n * mavlink_message_t msg;\r\n * int chan = 0;\r\n *\r\n *\r\n * while(serial.bytesAvailable > 0)\r\n * {\r\n *   uint8_t byte = serial.getNextByte();\r\n *   if (mavlink_frame_char(chan, byte, &msg) != MAVLINK_FRAMING_INCOMPLETE)\r\n *     {\r\n *     printf(\"Received message with ID %d, sequence: %d from component %d of system %d\", msg.msgid, msg.seq, msg.compid, msg.sysid);\r\n *     }\r\n * }\r\n *\r\n *\r\n * @endcode\r\n */\r\nMAVLINK_HELPER uint8_t mavlink_frame_char_buffer(mavlink_message_t* rxmsg, \r\n                                                 mavlink_status_t* status,\r\n                                                 uint8_t c, \r\n                                                 mavlink_message_t* r_message, \r\n                                                 mavlink_status_t* r_mavlink_status)\r\n{\r\n        /*\r\n\t  default message crc function. You can override this per-system to\r\n\t  put this data in a different memory segment\r\n\t*/\r\n#if MAVLINK_CRC_EXTRA\r\n#ifndef MAVLINK_MESSAGE_CRC\r\n\tstatic const uint8_t mavlink_message_crcs[256] = MAVLINK_MESSAGE_CRCS;\r\n#define MAVLINK_MESSAGE_CRC(msgid) mavlink_message_crcs[msgid]\r\n#endif\r\n#endif\r\n\r\n\t/* Enable this option to check the length of each message.\r\n\t   This allows invalid messages to be caught much sooner. Use if the transmission\r\n\t   medium is prone to missing (or extra) characters (e.g. a radio that fades in\r\n\t   and out). Only use if the channel will only contain messages types listed in\r\n\t   the headers.\r\n\t*/\r\n#ifdef MAVLINK_CHECK_MESSAGE_LENGTH\r\n#ifndef MAVLINK_MESSAGE_LENGTH\r\n\tstatic const uint8_t mavlink_message_lengths[256] = MAVLINK_MESSAGE_LENGTHS;\r\n#define MAVLINK_MESSAGE_LENGTH(msgid) mavlink_message_lengths[msgid]\r\n#endif\r\n#endif\r\n\r\n\tint bufferIndex = 0;\r\n\r\n\tstatus->msg_received = MAVLINK_FRAMING_INCOMPLETE;\r\n\r\n\tswitch (status->parse_state)\r\n\t{\r\n\tcase MAVLINK_PARSE_STATE_UNINIT:\r\n\tcase MAVLINK_PARSE_STATE_IDLE:\r\n\t\tif (c == MAVLINK_STX)\r\n\t\t{\r\n\t\t\tstatus->parse_state = MAVLINK_PARSE_STATE_GOT_STX;\r\n\t\t\trxmsg->len = 0;\r\n\t\t\trxmsg->magic = c;\r\n\t\t\tmavlink_start_checksum(rxmsg);\r\n\t\t}\r\n\t\tbreak;\r\n\r\n\tcase MAVLINK_PARSE_STATE_GOT_STX:\r\n\t\t\tif (status->msg_received \r\n/* Support shorter buffers than the\r\n   default maximum packet size */\r\n#if (MAVLINK_MAX_PAYLOAD_LEN < 255)\r\n\t\t\t\t|| c > MAVLINK_MAX_PAYLOAD_LEN\r\n#endif\r\n\t\t\t\t)\r\n\t\t{\r\n\t\t\tstatus->buffer_overrun++;\r\n\t\t\tstatus->parse_error++;\r\n\t\t\tstatus->msg_received = 0;\r\n\t\t\tstatus->parse_state = MAVLINK_PARSE_STATE_IDLE;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\t// NOT counting STX, LENGTH, SEQ, SYSID, COMPID, MSGID, CRC1 and CRC2\r\n\t\t\trxmsg->len = c;\r\n\t\t\tstatus->packet_idx = 0;\r\n\t\t\tmavlink_update_checksum(rxmsg, c);\r\n\t\t\tstatus->parse_state = MAVLINK_PARSE_STATE_GOT_LENGTH;\r\n\t\t}\r\n\t\tbreak;\r\n\r\n\tcase MAVLINK_PARSE_STATE_GOT_LENGTH:\r\n\t\trxmsg->seq = c;\r\n\t\tmavlink_update_checksum(rxmsg, c);\r\n\t\tstatus->parse_state = MAVLINK_PARSE_STATE_GOT_SEQ;\r\n\t\tbreak;\r\n\r\n\tcase MAVLINK_PARSE_STATE_GOT_SEQ:\r\n\t\trxmsg->sysid = c;\r\n\t\tmavlink_update_checksum(rxmsg, c);\r\n\t\tstatus->parse_state = MAVLINK_PARSE_STATE_GOT_SYSID;\r\n\t\tbreak;\r\n\r\n\tcase MAVLINK_PARSE_STATE_GOT_SYSID:\r\n\t\trxmsg->compid = c;\r\n\t\tmavlink_update_checksum(rxmsg, c);\r\n\t\tstatus->parse_state = MAVLINK_PARSE_STATE_GOT_COMPID;\r\n\t\tbreak;\r\n\r\n\tcase MAVLINK_PARSE_STATE_GOT_COMPID:\r\n#ifdef MAVLINK_CHECK_MESSAGE_LENGTH\r\n\t        if (rxmsg->len != MAVLINK_MESSAGE_LENGTH(c))\r\n\t\t{\r\n\t\t\tstatus->parse_error++;\r\n\t\t\tstatus->parse_state = MAVLINK_PARSE_STATE_IDLE;\r\n\t\t\tbreak;\r\n\t    }\r\n#endif\r\n\t\trxmsg->msgid = c;\r\n\t\tmavlink_update_checksum(rxmsg, c);\r\n\t\tif (rxmsg->len == 0)\r\n\t\t{\r\n\t\t\tstatus->parse_state = MAVLINK_PARSE_STATE_GOT_PAYLOAD;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tstatus->parse_state = MAVLINK_PARSE_STATE_GOT_MSGID;\r\n\t\t}\r\n\t\tbreak;\r\n\r\n\tcase MAVLINK_PARSE_STATE_GOT_MSGID:\r\n\t\t_MAV_PAYLOAD_NON_CONST(rxmsg)[status->packet_idx++] = (char)c;\r\n\t\tmavlink_update_checksum(rxmsg, c);\r\n\t\tif (status->packet_idx == rxmsg->len)\r\n\t\t{\r\n\t\t\tstatus->parse_state = MAVLINK_PARSE_STATE_GOT_PAYLOAD;\r\n\t\t}\r\n\t\tbreak;\r\n\r\n\tcase MAVLINK_PARSE_STATE_GOT_PAYLOAD:\r\n#if MAVLINK_CRC_EXTRA\r\n\t\tmavlink_update_checksum(rxmsg, MAVLINK_MESSAGE_CRC(rxmsg->msgid));\r\n#endif\r\n\t\tif (c != (rxmsg->checksum & 0xFF)) {\r\n\t\t\tstatus->parse_state = MAVLINK_PARSE_STATE_GOT_BAD_CRC1;\r\n\t\t} else {\r\n\t\t\tstatus->parse_state = MAVLINK_PARSE_STATE_GOT_CRC1;\r\n\t\t}\r\n                _MAV_PAYLOAD_NON_CONST(rxmsg)[status->packet_idx] = (char)c;\r\n\t\tbreak;\r\n\r\n\tcase MAVLINK_PARSE_STATE_GOT_CRC1:\r\n\tcase MAVLINK_PARSE_STATE_GOT_BAD_CRC1:\r\n\t\tif (status->parse_state == MAVLINK_PARSE_STATE_GOT_BAD_CRC1 || c != (rxmsg->checksum >> 8)) {\r\n\t\t\t// got a bad CRC message\r\n\t\t\tstatus->msg_received = MAVLINK_FRAMING_BAD_CRC;\r\n\t\t} else {\r\n\t\t\t// Successfully got message\r\n\t\t\tstatus->msg_received = MAVLINK_FRAMING_OK;\r\n                }\r\n                status->parse_state = MAVLINK_PARSE_STATE_IDLE;\r\n                _MAV_PAYLOAD_NON_CONST(rxmsg)[status->packet_idx+1] = (char)c;\r\n                memcpy(r_message, rxmsg, sizeof(mavlink_message_t));\r\n\t\tbreak;\r\n\t}\r\n\r\n\tbufferIndex++;\r\n\t// If a message has been sucessfully decoded, check index\r\n\tif (status->msg_received == MAVLINK_FRAMING_OK)\r\n\t{\r\n\t\t//while(status->current_seq != rxmsg->seq)\r\n\t\t//{\r\n\t\t//\tstatus->packet_rx_drop_count++;\r\n\t\t//               status->current_seq++;\r\n\t\t//}\r\n\t\tstatus->current_rx_seq = rxmsg->seq;\r\n\t\t// Initial condition: If no packet has been received so far, drop count is undefined\r\n\t\tif (status->packet_rx_success_count == 0) status->packet_rx_drop_count = 0;\r\n\t\t// Count this packet as received\r\n\t\tstatus->packet_rx_success_count++;\r\n\t}\r\n\r\n\tr_message->len = rxmsg->len; // Provide visibility on how far we are into current msg\r\n\tr_mavlink_status->parse_state = status->parse_state;\r\n\tr_mavlink_status->packet_idx = status->packet_idx;\r\n\tr_mavlink_status->current_rx_seq = status->current_rx_seq+1;\r\n\tr_mavlink_status->packet_rx_success_count = status->packet_rx_success_count;\r\n\tr_mavlink_status->packet_rx_drop_count = status->parse_error;\r\n\tstatus->parse_error = 0;\r\n\r\n\tif (status->msg_received == MAVLINK_FRAMING_BAD_CRC) {\r\n\t\t/*\r\n\t\t  the CRC came out wrong. We now need to overwrite the\r\n\t\t  msg CRC with the one on the wire so that if the\r\n\t\t  caller decides to forward the message anyway that\r\n\t\t  mavlink_msg_to_send_buffer() won't overwrite the\r\n\t\t  checksum\r\n\t\t */\r\n\t\tr_message->checksum = _MAV_PAYLOAD(rxmsg)[status->packet_idx] | (_MAV_PAYLOAD(rxmsg)[status->packet_idx+1]<<8);\r\n\t}\r\n\r\n\treturn status->msg_received;\r\n}\r\n\r\n/**\r\n * This is a convenience function which handles the complete MAVLink parsing.\r\n * the function will parse one byte at a time and return the complete packet once\r\n * it could be successfully decoded. This function will return 0, 1 or\r\n * 2 (MAVLINK_FRAMING_INCOMPLETE, MAVLINK_FRAMING_OK or MAVLINK_FRAMING_BAD_CRC)\r\n *\r\n * Messages are parsed into an internal buffer (one for each channel). When a complete\r\n * message is received it is copies into *returnMsg and the channel's status is\r\n * copied into *returnStats.\r\n *\r\n * @param chan     ID of the current channel. This allows to parse different channels with this function.\r\n *                 a channel is not a physical message channel like a serial port, but a logic partition of\r\n *                 the communication streams in this case. COMM_NB is the limit for the number of channels\r\n *                 on MCU (e.g. ARM7), while COMM_NB_HIGH is the limit for the number of channels in Linux/Windows\r\n * @param c        The char to parse\r\n *\r\n * @param returnMsg NULL if no message could be decoded, the message data else\r\n * @param returnStats if a message was decoded, this is filled with the channel's stats\r\n * @return 0 if no message could be decoded, 1 on good message and CRC, 2 on bad CRC\r\n *\r\n * A typical use scenario of this function call is:\r\n *\r\n * @code\r\n * #include <mavlink.h>\r\n *\r\n * mavlink_message_t msg;\r\n * int chan = 0;\r\n *\r\n *\r\n * while(serial.bytesAvailable > 0)\r\n * {\r\n *   uint8_t byte = serial.getNextByte();\r\n *   if (mavlink_frame_char(chan, byte, &msg) != MAVLINK_FRAMING_INCOMPLETE)\r\n *     {\r\n *     printf(\"Received message with ID %d, sequence: %d from component %d of system %d\", msg.msgid, msg.seq, msg.compid, msg.sysid);\r\n *     }\r\n * }\r\n *\r\n *\r\n * @endcode\r\n */\r\nMAVLINK_HELPER uint8_t mavlink_frame_char(uint8_t chan, uint8_t c, mavlink_message_t* r_message, mavlink_status_t* r_mavlink_status)\r\n{\r\n\treturn mavlink_frame_char_buffer(mavlink_get_channel_buffer(chan),\r\n\t\t\t\t\t mavlink_get_channel_status(chan),\r\n\t\t\t\t\t c,\r\n\t\t\t\t\t r_message,\r\n\t\t\t\t\t r_mavlink_status);\r\n}\r\n\r\n\r\n/**\r\n * This is a convenience function which handles the complete MAVLink parsing.\r\n * the function will parse one byte at a time and return the complete packet once\r\n * it could be successfully decoded. This function will return 0 or 1.\r\n *\r\n * Messages are parsed into an internal buffer (one for each channel). When a complete\r\n * message is received it is copies into *returnMsg and the channel's status is\r\n * copied into *returnStats.\r\n *\r\n * @param chan     ID of the current channel. This allows to parse different channels with this function.\r\n *                 a channel is not a physical message channel like a serial port, but a logic partition of\r\n *                 the communication streams in this case. COMM_NB is the limit for the number of channels\r\n *                 on MCU (e.g. ARM7), while COMM_NB_HIGH is the limit for the number of channels in Linux/Windows\r\n * @param c        The char to parse\r\n *\r\n * @param returnMsg NULL if no message could be decoded, the message data else\r\n * @param returnStats if a message was decoded, this is filled with the channel's stats\r\n * @return 0 if no message could be decoded or bad CRC, 1 on good message and CRC\r\n *\r\n * A typical use scenario of this function call is:\r\n *\r\n * @code\r\n * #include <mavlink.h>\r\n *\r\n * mavlink_message_t msg;\r\n * int chan = 0;\r\n *\r\n *\r\n * while(serial.bytesAvailable > 0)\r\n * {\r\n *   uint8_t byte = serial.getNextByte();\r\n *   if (mavlink_parse_char(chan, byte, &msg))\r\n *     {\r\n *     printf(\"Received message with ID %d, sequence: %d from component %d of system %d\", msg.msgid, msg.seq, msg.compid, msg.sysid);\r\n *     }\r\n * }\r\n *\r\n *\r\n * @endcode\r\n */\r\nMAVLINK_HELPER uint8_t mavlink_parse_char(uint8_t chan, uint8_t c, mavlink_message_t* r_message, mavlink_status_t* r_mavlink_status)\r\n{\r\n    uint8_t msg_received = mavlink_frame_char(chan, c, r_message, r_mavlink_status);\r\n    if (msg_received == MAVLINK_FRAMING_BAD_CRC) {\r\n\t    // we got a bad CRC. Treat as a parse failure\r\n\t    mavlink_message_t* rxmsg = mavlink_get_channel_buffer(chan);\r\n\t    mavlink_status_t* status = mavlink_get_channel_status(chan);\r\n\t    status->parse_error++;\r\n\t    status->msg_received = MAVLINK_FRAMING_INCOMPLETE;\r\n\t    status->parse_state = MAVLINK_PARSE_STATE_IDLE;\r\n\t    if (c == MAVLINK_STX)\r\n\t    {\r\n\t\t    status->parse_state = MAVLINK_PARSE_STATE_GOT_STX;\r\n\t\t    rxmsg->len = 0;\r\n\t\t    mavlink_start_checksum(rxmsg);\r\n\t    }\r\n\t    return 0;\r\n    }\r\n    return msg_received;\r\n}\r\n\r\n/**\r\n * @brief Put a bitfield of length 1-32 bit into the buffer\r\n *\r\n * @param b the value to add, will be encoded in the bitfield\r\n * @param bits number of bits to use to encode b, e.g. 1 for boolean, 2, 3, etc.\r\n * @param packet_index the position in the packet (the index of the first byte to use)\r\n * @param bit_index the position in the byte (the index of the first bit to use)\r\n * @param buffer packet buffer to write into\r\n * @return new position of the last used byte in the buffer\r\n */\r\nMAVLINK_HELPER uint8_t put_bitfield_n_by_index(int32_t b, uint8_t bits, uint8_t packet_index, uint8_t bit_index, uint8_t* r_bit_index, uint8_t* buffer)\r\n{\r\n\tuint16_t bits_remain = bits;\r\n\t// Transform number into network order\r\n\tint32_t v;\r\n\tuint8_t i_bit_index, i_byte_index, curr_bits_n;\r\n#if MAVLINK_NEED_BYTE_SWAP\r\n\tunion {\r\n\t\tint32_t i;\r\n\t\tuint8_t b[4];\r\n\t} bin, bout;\r\n\tbin.i = b;\r\n\tbout.b[0] = bin.b[3];\r\n\tbout.b[1] = bin.b[2];\r\n\tbout.b[2] = bin.b[1];\r\n\tbout.b[3] = bin.b[0];\r\n\tv = bout.i;\r\n#else\r\n\tv = b;\r\n#endif\r\n\r\n\t// buffer in\r\n\t// 01100000 01000000 00000000 11110001\r\n\t// buffer out\r\n\t// 11110001 00000000 01000000 01100000\r\n\r\n\t// Existing partly filled byte (four free slots)\r\n\t// 0111xxxx\r\n\r\n\t// Mask n free bits\r\n\t// 00001111 = 2^0 + 2^1 + 2^2 + 2^3 = 2^n - 1\r\n\t// = ((uint32_t)(1 << n)) - 1; // = 2^n - 1\r\n\r\n\t// Shift n bits into the right position\r\n\t// out = in >> n;\r\n\r\n\t// Mask and shift bytes\r\n\ti_bit_index = bit_index;\r\n\ti_byte_index = packet_index;\r\n\tif (bit_index > 0)\r\n\t{\r\n\t\t// If bits were available at start, they were available\r\n\t\t// in the byte before the current index\r\n\t\ti_byte_index--;\r\n\t}\r\n\r\n\t// While bits have not been packed yet\r\n\twhile (bits_remain > 0)\r\n\t{\r\n\t\t// Bits still have to be packed\r\n\t\t// there can be more than 8 bits, so\r\n\t\t// we might have to pack them into more than one byte\r\n\r\n\t\t// First pack everything we can into the current 'open' byte\r\n\t\t//curr_bits_n = bits_remain << 3; // Equals  bits_remain mod 8\r\n\t\t//FIXME\r\n\t\tif (bits_remain <= (uint8_t)(8 - i_bit_index))\r\n\t\t{\r\n\t\t\t// Enough space\r\n\t\t\tcurr_bits_n = (uint8_t)bits_remain;\r\n\t\t}\r\n\t\telse\r\n\t\t{\r\n\t\t\tcurr_bits_n = (8 - i_bit_index);\r\n\t\t}\r\n\t\t\r\n\t\t// Pack these n bits into the current byte\r\n\t\t// Mask out whatever was at that position with ones (xxx11111)\r\n\t\tbuffer[i_byte_index] &= (0xFF >> (8 - curr_bits_n));\r\n\t\t// Put content to this position, by masking out the non-used part\r\n\t\tbuffer[i_byte_index] |= ((0x00 << curr_bits_n) & v);\r\n\t\t\r\n\t\t// Increment the bit index\r\n\t\ti_bit_index += curr_bits_n;\r\n\r\n\t\t// Now proceed to the next byte, if necessary\r\n\t\tbits_remain -= curr_bits_n;\r\n\t\tif (bits_remain > 0)\r\n\t\t{\r\n\t\t\t// Offer another 8 bits / one byte\r\n\t\t\ti_byte_index++;\r\n\t\t\ti_bit_index = 0;\r\n\t\t}\r\n\t}\r\n\t\r\n\t*r_bit_index = i_bit_index;\r\n\t// If a partly filled byte is present, mark this as consumed\r\n\tif (i_bit_index != 7) i_byte_index++;\r\n\treturn i_byte_index - packet_index;\r\n}\r\n\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\n// To make MAVLink work on your MCU, define comm_send_ch() if you wish\r\n// to send 1 byte at a time, or MAVLINK_SEND_UART_BYTES() to send a\r\n// whole packet at a time\r\n\r\n/*\r\n\r\n#include \"mavlink_types.h\"\r\n\r\nvoid comm_send_ch(mavlink_channel_t chan, uint8_t ch)\r\n{\r\n    if (chan == MAVLINK_COMM_0)\r\n    {\r\n        uart0_transmit(ch);\r\n    }\r\n    if (chan == MAVLINK_COMM_1)\r\n    {\r\n    \tuart1_transmit(ch);\r\n    }\r\n}\r\n */\r\n\r\nMAVLINK_HELPER void _mavlink_send_uart(mavlink_channel_t chan, const char *buf, uint16_t len)\r\n{\r\n#ifdef MAVLINK_SEND_UART_BYTES\r\n\t/* this is the more efficient approach, if the platform\r\n\t   defines it */\r\n\tMAVLINK_SEND_UART_BYTES(chan, (const uint8_t *)buf, len);\r\n#else\r\n\t/* fallback to one byte at a time */\r\n\tuint16_t i;\r\n\tfor (i = 0; i < len; i++) {\r\n\t\tcomm_send_ch(chan, (uint8_t)buf[i]);\r\n\t}\r\n#endif\r\n}\r\n#endif // MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\n#endif /* _MAVLINK_HELPERS_H_ */\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/msg/mavlink/mavlink_types.h",
    "content": "#ifndef MAVLINK_TYPES_H_\r\n#define MAVLINK_TYPES_H_\r\n\r\n// Visual Studio versions before 2010 don't have stdint.h, so we just error out.\r\n#if (defined _MSC_VER) && (_MSC_VER < 1600)\r\n#error \"The C-MAVLink implementation requires Visual Studio 2010 or greater\"\r\n#endif\r\n\r\n#include <stdint.h>\r\n\r\n// Macro to define packed structures\r\n#ifdef __GNUC__\r\n  #define MAVPACKED( __Declaration__ ) __Declaration__ __attribute__((packed))\r\n#else\r\n  #define MAVPACKED( __Declaration__ ) __pragma( pack(push, 1) ) __Declaration__ __pragma( pack(pop) )\r\n#endif\r\n\r\n#ifndef MAVLINK_MAX_PAYLOAD_LEN\r\n// it is possible to override this, but be careful!\r\n#define MAVLINK_MAX_PAYLOAD_LEN 255 ///< Maximum payload length\r\n#endif\r\n\r\n#define MAVLINK_CORE_HEADER_LEN 5 ///< Length of core header (of the comm. layer): message length (1 byte) + message sequence (1 byte) + message system id (1 byte) + message component id (1 byte) + message type id (1 byte)\r\n#define MAVLINK_NUM_HEADER_BYTES (MAVLINK_CORE_HEADER_LEN + 1) ///< Length of all header bytes, including core and checksum\r\n#define MAVLINK_NUM_CHECKSUM_BYTES 2\r\n#define MAVLINK_NUM_NON_PAYLOAD_BYTES (MAVLINK_NUM_HEADER_BYTES + MAVLINK_NUM_CHECKSUM_BYTES)\r\n\r\n#define MAVLINK_MAX_PACKET_LEN (MAVLINK_MAX_PAYLOAD_LEN + MAVLINK_NUM_NON_PAYLOAD_BYTES) ///< Maximum packet length\r\n\r\n#define MAVLINK_MSG_ID_EXTENDED_MESSAGE 255\r\n#define MAVLINK_EXTENDED_HEADER_LEN 14\r\n\r\n#if (defined _MSC_VER) || ((defined __APPLE__) && (defined __MACH__)) || (defined __linux__)\r\n  /* full fledged 32bit++ OS */\r\n  #define MAVLINK_MAX_EXTENDED_PACKET_LEN 65507\r\n#else\r\n  /* small microcontrollers */\r\n  #define MAVLINK_MAX_EXTENDED_PACKET_LEN 2048\r\n#endif\r\n\r\n#define MAVLINK_MAX_EXTENDED_PAYLOAD_LEN (MAVLINK_MAX_EXTENDED_PACKET_LEN - MAVLINK_EXTENDED_HEADER_LEN - MAVLINK_NUM_NON_PAYLOAD_BYTES)\r\n\r\n\r\n/**\r\n * Old-style 4 byte param union\r\n *\r\n * This struct is the data format to be used when sending\r\n * parameters. The parameter should be copied to the native\r\n * type (without type conversion)\r\n * and re-instanted on the receiving side using the\r\n * native type as well.\r\n */\r\nMAVPACKED(\r\ntypedef struct param_union {\r\n\tunion {\r\n\t\tfloat param_float;\r\n\t\tint32_t param_int32;\r\n\t\tuint32_t param_uint32;\r\n\t\tint16_t param_int16;\r\n\t\tuint16_t param_uint16;\r\n\t\tint8_t param_int8;\r\n\t\tuint8_t param_uint8;\r\n\t\tuint8_t bytes[4];\r\n\t};\r\n\tuint8_t type;\r\n}) mavlink_param_union_t;\r\n\r\n\r\n/**\r\n * New-style 8 byte param union\r\n * mavlink_param_union_double_t will be 8 bytes long, and treated as needing 8 byte alignment for the purposes of MAVLink 1.0 field ordering.\r\n * The mavlink_param_union_double_t will be treated as a little-endian structure.\r\n *\r\n * If is_double is 1 then the type is a double, and the remaining 63 bits are the double, with the lowest bit of the mantissa zero.\r\n * The intention is that by replacing the is_double bit with 0 the type can be directly used as a double (as the is_double bit corresponds to the\r\n * lowest mantissa bit of a double). If is_double is 0 then mavlink_type gives the type in the union.\r\n * The mavlink_types.h header will also need to have shifts/masks to define the bit boundaries in the above,\r\n * as bitfield ordering isn’t consistent between platforms. The above is intended to be for gcc on x86,\r\n * which should be the same as gcc on little-endian arm. When using shifts/masks the value will be treated as a 64 bit unsigned number,\r\n * and the bits pulled out using the shifts/masks.\r\n*/\r\nMAVPACKED(\r\ntypedef struct param_union_extended {\r\n    union {\r\n    struct {\r\n        uint8_t is_double:1;\r\n        uint8_t mavlink_type:7;\r\n        union {\r\n            char c;\r\n            uint8_t uint8;\r\n            int8_t int8;\r\n            uint16_t uint16;\r\n            int16_t int16;\r\n            uint32_t uint32;\r\n            int32_t int32;\r\n            float f;\r\n            uint8_t align[7];\r\n        };\r\n    };\r\n    uint8_t data[8];\r\n    };\r\n}) mavlink_param_union_double_t;\r\n\r\n/**\r\n * This structure is required to make the mavlink_send_xxx convenience functions\r\n * work, as it tells the library what the current system and component ID are.\r\n */\r\nMAVPACKED(\r\ntypedef struct __mavlink_system {\r\n    uint8_t sysid;   ///< Used by the MAVLink message_xx_send() convenience function\r\n    uint8_t compid;  ///< Used by the MAVLink message_xx_send() convenience function\r\n}) mavlink_system_t;\r\n\r\nMAVPACKED(\r\ntypedef struct __mavlink_message {\r\n\tuint16_t checksum; ///< sent at end of packet\r\n\tuint8_t magic;   ///< protocol magic marker\r\n\tuint8_t len;     ///< Length of payload\r\n\tuint8_t seq;     ///< Sequence of packet\r\n\tuint8_t sysid;   ///< ID of message sender system/aircraft\r\n\tuint8_t compid;  ///< ID of the message sender component\r\n\tuint8_t msgid;   ///< ID of message in payload\r\n\tuint64_t payload64[(MAVLINK_MAX_PAYLOAD_LEN+MAVLINK_NUM_CHECKSUM_BYTES+7)/8];\r\n}) mavlink_message_t;\r\n\r\nMAVPACKED(\r\ntypedef struct __mavlink_extended_message {\r\n       mavlink_message_t base_msg;\r\n       int32_t extended_payload_len;   ///< Length of extended payload if any\r\n       uint8_t extended_payload[MAVLINK_MAX_EXTENDED_PAYLOAD_LEN];\r\n}) mavlink_extended_message_t;\r\n\r\ntypedef enum {\r\n\tMAVLINK_TYPE_CHAR     = 0,\r\n\tMAVLINK_TYPE_UINT8_T  = 1,\r\n\tMAVLINK_TYPE_INT8_T   = 2,\r\n\tMAVLINK_TYPE_UINT16_T = 3,\r\n\tMAVLINK_TYPE_INT16_T  = 4,\r\n\tMAVLINK_TYPE_UINT32_T = 5,\r\n\tMAVLINK_TYPE_INT32_T  = 6,\r\n\tMAVLINK_TYPE_UINT64_T = 7,\r\n\tMAVLINK_TYPE_INT64_T  = 8,\r\n\tMAVLINK_TYPE_FLOAT    = 9,\r\n\tMAVLINK_TYPE_DOUBLE   = 10\r\n} mavlink_message_type_t;\r\n\r\n#define MAVLINK_MAX_FIELDS 64\r\n\r\ntypedef struct __mavlink_field_info {\r\n        const char *name;                 // name of this field\r\n        const char *print_format;         // printing format hint, or NULL\r\n        mavlink_message_type_t type;      // type of this field\r\n        unsigned int array_length;        // if non-zero, field is an array\r\n        unsigned int wire_offset;         // offset of each field in the payload\r\n        unsigned int structure_offset;    // offset in a C structure\r\n} mavlink_field_info_t;\r\n\r\n// note that in this structure the order of fields is the order\r\n// in the XML file, not necessary the wire order\r\ntypedef struct __mavlink_message_info {\r\n\tconst char *name;                                      // name of the message\r\n\tunsigned num_fields;                                   // how many fields in this message\r\n\tmavlink_field_info_t fields[MAVLINK_MAX_FIELDS];       // field information\r\n} mavlink_message_info_t;\r\n\r\n#define _MAV_PAYLOAD(msg) ((const char *)(&((msg)->payload64[0])))\r\n#define _MAV_PAYLOAD_NON_CONST(msg) ((char *)(&((msg)->payload64[0])))\r\n\r\n// checksum is immediately after the payload bytes\r\n#define mavlink_ck_a(msg) *((msg)->len + (uint8_t *)_MAV_PAYLOAD_NON_CONST(msg))\r\n#define mavlink_ck_b(msg) *(((msg)->len+(uint16_t)1) + (uint8_t *)_MAV_PAYLOAD_NON_CONST(msg))\r\n\r\ntypedef enum {\r\n    MAVLINK_COMM_0,\r\n    MAVLINK_COMM_1,\r\n    MAVLINK_COMM_2,\r\n    MAVLINK_COMM_3\r\n} mavlink_channel_t;\r\n\r\n/*\r\n * applications can set MAVLINK_COMM_NUM_BUFFERS to the maximum number\r\n * of buffers they will use. If more are used, then the result will be\r\n * a stack overrun\r\n */\r\n#ifndef MAVLINK_COMM_NUM_BUFFERS\r\n#if (defined linux) | (defined __linux) | (defined  __MACH__) | (defined _WIN32)\r\n# define MAVLINK_COMM_NUM_BUFFERS 16\r\n#else\r\n# define MAVLINK_COMM_NUM_BUFFERS 4\r\n#endif\r\n#endif\r\n\r\ntypedef enum {\r\n    MAVLINK_PARSE_STATE_UNINIT=0,\r\n    MAVLINK_PARSE_STATE_IDLE,\r\n    MAVLINK_PARSE_STATE_GOT_STX,\r\n    MAVLINK_PARSE_STATE_GOT_SEQ,\r\n    MAVLINK_PARSE_STATE_GOT_LENGTH,\r\n    MAVLINK_PARSE_STATE_GOT_SYSID,\r\n    MAVLINK_PARSE_STATE_GOT_COMPID,\r\n    MAVLINK_PARSE_STATE_GOT_MSGID,\r\n    MAVLINK_PARSE_STATE_GOT_PAYLOAD,\r\n    MAVLINK_PARSE_STATE_GOT_CRC1,\r\n    MAVLINK_PARSE_STATE_GOT_BAD_CRC1\r\n} mavlink_parse_state_t; ///< The state machine for the comm parser\r\n\r\ntypedef enum {\r\n    MAVLINK_FRAMING_INCOMPLETE=0,\r\n    MAVLINK_FRAMING_OK=1,\r\n    MAVLINK_FRAMING_BAD_CRC=2\r\n} mavlink_framing_t;\r\n\r\ntypedef struct __mavlink_status {\r\n    uint8_t msg_received;               ///< Number of received messages\r\n    uint8_t buffer_overrun;             ///< Number of buffer overruns\r\n    uint8_t parse_error;                ///< Number of parse errors\r\n    mavlink_parse_state_t parse_state;  ///< Parsing state machine\r\n    uint8_t packet_idx;                 ///< Index in current packet\r\n    uint8_t current_rx_seq;             ///< Sequence number of last packet received\r\n    uint8_t current_tx_seq;             ///< Sequence number of last packet sent\r\n    uint16_t packet_rx_success_count;   ///< Received packets\r\n    uint16_t packet_rx_drop_count;      ///< Number of packet drops\r\n} mavlink_status_t;\r\n\r\n#define MAVLINK_BIG_ENDIAN 0\r\n#define MAVLINK_LITTLE_ENDIAN 1\r\n\r\n#endif /* MAVLINK_TYPES_H_ */\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/msg/mavlink/opencr_msg/mavlink.h",
    "content": "/** @file\r\n *\t@brief MAVLink comm protocol built from opencr_msg.xml\r\n *\t@see http://mavlink.org\r\n */\r\n#ifndef MAVLINK_H\r\n#define MAVLINK_H\r\n\r\n#ifndef MAVLINK_STX\r\n#define MAVLINK_STX 254\r\n#endif\r\n\r\n#ifndef MAVLINK_ENDIAN\r\n#define MAVLINK_ENDIAN MAVLINK_LITTLE_ENDIAN\r\n#endif\r\n\r\n#ifndef MAVLINK_ALIGNED_FIELDS\r\n#define MAVLINK_ALIGNED_FIELDS 1\r\n#endif\r\n\r\n#ifndef MAVLINK_CRC_EXTRA\r\n#define MAVLINK_CRC_EXTRA 1\r\n#endif\r\n\r\n#ifndef MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_COMMAND_24BIT 0\r\n#endif\r\n\r\n#ifndef MAVLINK_PACKED\r\n#define MAVLINK_PACKED __attribute__((__packed__))\r\n#endif\r\n\r\n#include \"version.h\"\r\n#include \"opencr_msg.h\"\r\n\r\n#endif // MAVLINK_H\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/msg/mavlink/opencr_msg/mavlink_msg_ack.h",
    "content": "// MESSAGE ACK PACKING\r\n\r\n#define MAVLINK_MSG_ID_ACK 150\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_ack_t\r\n{\r\n uint16_t err_code; /*< */\r\n uint8_t msg_id; /*< */\r\n uint8_t length; /*< */\r\n uint8_t data[16]; /*< */\r\n} mavlink_ack_t;\r\n\r\n#define MAVLINK_MSG_ID_ACK_LEN 20\r\n#define MAVLINK_MSG_ID_ACK_MIN_LEN 20\r\n#define MAVLINK_MSG_ID_150_LEN 20\r\n#define MAVLINK_MSG_ID_150_MIN_LEN 20\r\n\r\n#define MAVLINK_MSG_ID_ACK_CRC 192\r\n#define MAVLINK_MSG_ID_150_CRC 192\r\n\r\n#define MAVLINK_MSG_ACK_FIELD_DATA_LEN 16\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_ACK { \\\r\n\t150, \\\r\n\t\"ACK\", \\\r\n\t4, \\\r\n\t{  { \"err_code\", NULL, MAVLINK_TYPE_UINT16_T, 0, 0, offsetof(mavlink_ack_t, err_code) }, \\\r\n         { \"msg_id\", NULL, MAVLINK_TYPE_UINT8_T, 0, 2, offsetof(mavlink_ack_t, msg_id) }, \\\r\n         { \"length\", NULL, MAVLINK_TYPE_UINT8_T, 0, 3, offsetof(mavlink_ack_t, length) }, \\\r\n         { \"data\", NULL, MAVLINK_TYPE_UINT8_T, 16, 4, offsetof(mavlink_ack_t, data) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_ACK { \\\r\n\t\"ACK\", \\\r\n\t4, \\\r\n\t{  { \"err_code\", NULL, MAVLINK_TYPE_UINT16_T, 0, 0, offsetof(mavlink_ack_t, err_code) }, \\\r\n         { \"msg_id\", NULL, MAVLINK_TYPE_UINT8_T, 0, 2, offsetof(mavlink_ack_t, msg_id) }, \\\r\n         { \"length\", NULL, MAVLINK_TYPE_UINT8_T, 0, 3, offsetof(mavlink_ack_t, length) }, \\\r\n         { \"data\", NULL, MAVLINK_TYPE_UINT8_T, 16, 4, offsetof(mavlink_ack_t, data) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a ack message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param msg_id \r\n * @param err_code \r\n * @param length \r\n * @param data \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_ack_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t msg_id, uint16_t err_code, uint8_t length, const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_ACK_LEN];\r\n\t_mav_put_uint16_t(buf, 0, err_code);\r\n\t_mav_put_uint8_t(buf, 2, msg_id);\r\n\t_mav_put_uint8_t(buf, 3, length);\r\n\t_mav_put_uint8_t_array(buf, 4, data, 16);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_ACK_LEN);\r\n#else\r\n\tmavlink_ack_t packet;\r\n\tpacket.err_code = err_code;\r\n\tpacket.msg_id = msg_id;\r\n\tpacket.length = length;\r\n\tmav_array_memcpy(packet.data, data, sizeof(uint8_t)*16);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_ACK_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_ACK;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_ACK_MIN_LEN, MAVLINK_MSG_ID_ACK_LEN, MAVLINK_MSG_ID_ACK_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a ack message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param msg_id \r\n * @param err_code \r\n * @param length \r\n * @param data \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_ack_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t msg_id,uint16_t err_code,uint8_t length,const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_ACK_LEN];\r\n\t_mav_put_uint16_t(buf, 0, err_code);\r\n\t_mav_put_uint8_t(buf, 2, msg_id);\r\n\t_mav_put_uint8_t(buf, 3, length);\r\n\t_mav_put_uint8_t_array(buf, 4, data, 16);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_ACK_LEN);\r\n#else\r\n\tmavlink_ack_t packet;\r\n\tpacket.err_code = err_code;\r\n\tpacket.msg_id = msg_id;\r\n\tpacket.length = length;\r\n\tmav_array_memcpy(packet.data, data, sizeof(uint8_t)*16);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_ACK_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_ACK;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_ACK_MIN_LEN, MAVLINK_MSG_ID_ACK_LEN, MAVLINK_MSG_ID_ACK_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a ack struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param ack C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_ack_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_ack_t* ack)\r\n{\r\n\treturn mavlink_msg_ack_pack(system_id, component_id, msg, ack->msg_id, ack->err_code, ack->length, ack->data);\r\n}\r\n\r\n/**\r\n * @brief Encode a ack struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param ack C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_ack_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_ack_t* ack)\r\n{\r\n\treturn mavlink_msg_ack_pack_chan(system_id, component_id, chan, msg, ack->msg_id, ack->err_code, ack->length, ack->data);\r\n}\r\n\r\n/**\r\n * @brief Send a ack message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param msg_id \r\n * @param err_code \r\n * @param length \r\n * @param data \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_ack_send(mavlink_channel_t chan, uint8_t msg_id, uint16_t err_code, uint8_t length, const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_ACK_LEN];\r\n\t_mav_put_uint16_t(buf, 0, err_code);\r\n\t_mav_put_uint8_t(buf, 2, msg_id);\r\n\t_mav_put_uint8_t(buf, 3, length);\r\n\t_mav_put_uint8_t_array(buf, 4, data, 16);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_ACK, buf, MAVLINK_MSG_ID_ACK_MIN_LEN, MAVLINK_MSG_ID_ACK_LEN, MAVLINK_MSG_ID_ACK_CRC);\r\n#else\r\n\tmavlink_ack_t packet;\r\n\tpacket.err_code = err_code;\r\n\tpacket.msg_id = msg_id;\r\n\tpacket.length = length;\r\n\tmav_array_memcpy(packet.data, data, sizeof(uint8_t)*16);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_ACK, (const char *)&packet, MAVLINK_MSG_ID_ACK_MIN_LEN, MAVLINK_MSG_ID_ACK_LEN, MAVLINK_MSG_ID_ACK_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a ack message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_ack_send_struct(mavlink_channel_t chan, const mavlink_ack_t* ack)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_ack_send(chan, ack->msg_id, ack->err_code, ack->length, ack->data);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_ACK, (const char *)ack, MAVLINK_MSG_ID_ACK_MIN_LEN, MAVLINK_MSG_ID_ACK_LEN, MAVLINK_MSG_ID_ACK_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_ACK_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_ack_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t msg_id, uint16_t err_code, uint8_t length, const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint16_t(buf, 0, err_code);\r\n\t_mav_put_uint8_t(buf, 2, msg_id);\r\n\t_mav_put_uint8_t(buf, 3, length);\r\n\t_mav_put_uint8_t_array(buf, 4, data, 16);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_ACK, buf, MAVLINK_MSG_ID_ACK_MIN_LEN, MAVLINK_MSG_ID_ACK_LEN, MAVLINK_MSG_ID_ACK_CRC);\r\n#else\r\n\tmavlink_ack_t *packet = (mavlink_ack_t *)msgbuf;\r\n\tpacket->err_code = err_code;\r\n\tpacket->msg_id = msg_id;\r\n\tpacket->length = length;\r\n\tmav_array_memcpy(packet->data, data, sizeof(uint8_t)*16);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_ACK, (const char *)packet, MAVLINK_MSG_ID_ACK_MIN_LEN, MAVLINK_MSG_ID_ACK_LEN, MAVLINK_MSG_ID_ACK_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE ACK UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field msg_id from ack message\r\n *\r\n * @return \r\n */\r\nstatic inline uint8_t mavlink_msg_ack_get_msg_id(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  2);\r\n}\r\n\r\n/**\r\n * @brief Get field err_code from ack message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_ack_get_err_code(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint16_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field length from ack message\r\n *\r\n * @return \r\n */\r\nstatic inline uint8_t mavlink_msg_ack_get_length(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  3);\r\n}\r\n\r\n/**\r\n * @brief Get field data from ack message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_ack_get_data(const mavlink_message_t* msg, uint8_t *data)\r\n{\r\n\treturn _MAV_RETURN_uint8_t_array(msg, data, 16,  4);\r\n}\r\n\r\n/**\r\n * @brief Decode a ack message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param ack C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_ack_decode(const mavlink_message_t* msg, mavlink_ack_t* ack)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tack->err_code = mavlink_msg_ack_get_err_code(msg);\r\n\tack->msg_id = mavlink_msg_ack_get_msg_id(msg);\r\n\tack->length = mavlink_msg_ack_get_length(msg);\r\n\tmavlink_msg_ack_get_data(msg, ack->data);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_ACK_LEN? msg->len : MAVLINK_MSG_ID_ACK_LEN;\r\n        memset(ack, 0, MAVLINK_MSG_ID_ACK_LEN);\r\n\tmemcpy(ack, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/msg/mavlink/opencr_msg/mavlink_msg_flash_fw_erase.h",
    "content": "// MESSAGE FLASH_FW_ERASE PACKING\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_ERASE 158\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_flash_fw_erase_t\r\n{\r\n uint32_t length; /*< */\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n uint8_t param[8]; /*< */\r\n} mavlink_flash_fw_erase_t;\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN 13\r\n#define MAVLINK_MSG_ID_FLASH_FW_ERASE_MIN_LEN 13\r\n#define MAVLINK_MSG_ID_158_LEN 13\r\n#define MAVLINK_MSG_ID_158_MIN_LEN 13\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_ERASE_CRC 13\r\n#define MAVLINK_MSG_ID_158_CRC 13\r\n\r\n#define MAVLINK_MSG_FLASH_FW_ERASE_FIELD_PARAM_LEN 8\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_ERASE { \\\r\n\t158, \\\r\n\t\"FLASH_FW_ERASE\", \\\r\n\t3, \\\r\n\t{  { \"length\", NULL, MAVLINK_TYPE_UINT32_T, 0, 0, offsetof(mavlink_flash_fw_erase_t, length) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 4, offsetof(mavlink_flash_fw_erase_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 5, offsetof(mavlink_flash_fw_erase_t, param) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_ERASE { \\\r\n\t\"FLASH_FW_ERASE\", \\\r\n\t3, \\\r\n\t{  { \"length\", NULL, MAVLINK_TYPE_UINT32_T, 0, 0, offsetof(mavlink_flash_fw_erase_t, length) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 4, offsetof(mavlink_flash_fw_erase_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 5, offsetof(mavlink_flash_fw_erase_t, param) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a flash_fw_erase message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param length \r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_erase_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, uint32_t length, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN];\r\n\t_mav_put_uint32_t(buf, 0, length);\r\n\t_mav_put_uint8_t(buf, 4, resp);\r\n\t_mav_put_uint8_t_array(buf, 5, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN);\r\n#else\r\n\tmavlink_flash_fw_erase_t packet;\r\n\tpacket.length = length;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_ERASE;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_FLASH_FW_ERASE_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a flash_fw_erase message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param length \r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_erase_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,uint32_t length,const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN];\r\n\t_mav_put_uint32_t(buf, 0, length);\r\n\t_mav_put_uint8_t(buf, 4, resp);\r\n\t_mav_put_uint8_t_array(buf, 5, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN);\r\n#else\r\n\tmavlink_flash_fw_erase_t packet;\r\n\tpacket.length = length;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_ERASE;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_FLASH_FW_ERASE_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_erase struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_erase C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_erase_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_flash_fw_erase_t* flash_fw_erase)\r\n{\r\n\treturn mavlink_msg_flash_fw_erase_pack(system_id, component_id, msg, flash_fw_erase->resp, flash_fw_erase->length, flash_fw_erase->param);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_erase struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_erase C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_erase_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_flash_fw_erase_t* flash_fw_erase)\r\n{\r\n\treturn mavlink_msg_flash_fw_erase_pack_chan(system_id, component_id, chan, msg, flash_fw_erase->resp, flash_fw_erase->length, flash_fw_erase->param);\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_erase message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param length \r\n * @param param \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_flash_fw_erase_send(mavlink_channel_t chan, uint8_t resp, uint32_t length, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN];\r\n\t_mav_put_uint32_t(buf, 0, length);\r\n\t_mav_put_uint8_t(buf, 4, resp);\r\n\t_mav_put_uint8_t_array(buf, 5, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_ERASE, buf, MAVLINK_MSG_ID_FLASH_FW_ERASE_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_CRC);\r\n#else\r\n\tmavlink_flash_fw_erase_t packet;\r\n\tpacket.length = length;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_ERASE, (const char *)&packet, MAVLINK_MSG_ID_FLASH_FW_ERASE_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_erase message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_flash_fw_erase_send_struct(mavlink_channel_t chan, const mavlink_flash_fw_erase_t* flash_fw_erase)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_flash_fw_erase_send(chan, flash_fw_erase->resp, flash_fw_erase->length, flash_fw_erase->param);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_ERASE, (const char *)flash_fw_erase, MAVLINK_MSG_ID_FLASH_FW_ERASE_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_flash_fw_erase_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, uint32_t length, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint32_t(buf, 0, length);\r\n\t_mav_put_uint8_t(buf, 4, resp);\r\n\t_mav_put_uint8_t_array(buf, 5, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_ERASE, buf, MAVLINK_MSG_ID_FLASH_FW_ERASE_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_CRC);\r\n#else\r\n\tmavlink_flash_fw_erase_t *packet = (mavlink_flash_fw_erase_t *)msgbuf;\r\n\tpacket->length = length;\r\n\tpacket->resp = resp;\r\n\tmav_array_memcpy(packet->param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_ERASE, (const char *)packet, MAVLINK_MSG_ID_FLASH_FW_ERASE_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN, MAVLINK_MSG_ID_FLASH_FW_ERASE_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE FLASH_FW_ERASE UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from flash_fw_erase message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_flash_fw_erase_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  4);\r\n}\r\n\r\n/**\r\n * @brief Get field length from flash_fw_erase message\r\n *\r\n * @return \r\n */\r\nstatic inline uint32_t mavlink_msg_flash_fw_erase_get_length(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint32_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field param from flash_fw_erase message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_erase_get_param(const mavlink_message_t* msg, uint8_t *param)\r\n{\r\n\treturn _MAV_RETURN_uint8_t_array(msg, param, 8,  5);\r\n}\r\n\r\n/**\r\n * @brief Decode a flash_fw_erase message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param flash_fw_erase C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_flash_fw_erase_decode(const mavlink_message_t* msg, mavlink_flash_fw_erase_t* flash_fw_erase)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tflash_fw_erase->length = mavlink_msg_flash_fw_erase_get_length(msg);\r\n\tflash_fw_erase->resp = mavlink_msg_flash_fw_erase_get_resp(msg);\r\n\tmavlink_msg_flash_fw_erase_get_param(msg, flash_fw_erase->param);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN? msg->len : MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN;\r\n        memset(flash_fw_erase, 0, MAVLINK_MSG_ID_FLASH_FW_ERASE_LEN);\r\n\tmemcpy(flash_fw_erase, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/msg/mavlink/opencr_msg/mavlink_msg_flash_fw_read_block.h",
    "content": "// MESSAGE FLASH_FW_READ_BLOCK PACKING\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK 161\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_flash_fw_read_block_t\r\n{\r\n uint32_t addr; /*< */\r\n uint16_t length; /*< */\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n} mavlink_flash_fw_read_block_t;\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN 7\r\n#define MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_MIN_LEN 7\r\n#define MAVLINK_MSG_ID_161_LEN 7\r\n#define MAVLINK_MSG_ID_161_MIN_LEN 7\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_CRC 131\r\n#define MAVLINK_MSG_ID_161_CRC 131\r\n\r\n\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_READ_BLOCK { \\\r\n\t161, \\\r\n\t\"FLASH_FW_READ_BLOCK\", \\\r\n\t3, \\\r\n\t{  { \"addr\", NULL, MAVLINK_TYPE_UINT32_T, 0, 0, offsetof(mavlink_flash_fw_read_block_t, addr) }, \\\r\n         { \"length\", NULL, MAVLINK_TYPE_UINT16_T, 0, 4, offsetof(mavlink_flash_fw_read_block_t, length) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 6, offsetof(mavlink_flash_fw_read_block_t, resp) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_READ_BLOCK { \\\r\n\t\"FLASH_FW_READ_BLOCK\", \\\r\n\t3, \\\r\n\t{  { \"addr\", NULL, MAVLINK_TYPE_UINT32_T, 0, 0, offsetof(mavlink_flash_fw_read_block_t, addr) }, \\\r\n         { \"length\", NULL, MAVLINK_TYPE_UINT16_T, 0, 4, offsetof(mavlink_flash_fw_read_block_t, length) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 6, offsetof(mavlink_flash_fw_read_block_t, resp) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a flash_fw_read_block message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_read_block_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, uint32_t addr, uint16_t length)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN];\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint16_t(buf, 4, length);\r\n\t_mav_put_uint8_t(buf, 6, resp);\r\n\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN);\r\n#else\r\n\tmavlink_flash_fw_read_block_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.length = length;\r\n\tpacket.resp = resp;\r\n\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a flash_fw_read_block message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_read_block_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,uint32_t addr,uint16_t length)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN];\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint16_t(buf, 4, length);\r\n\t_mav_put_uint8_t(buf, 6, resp);\r\n\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN);\r\n#else\r\n\tmavlink_flash_fw_read_block_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.length = length;\r\n\tpacket.resp = resp;\r\n\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_read_block struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_read_block C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_read_block_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_flash_fw_read_block_t* flash_fw_read_block)\r\n{\r\n\treturn mavlink_msg_flash_fw_read_block_pack(system_id, component_id, msg, flash_fw_read_block->resp, flash_fw_read_block->addr, flash_fw_read_block->length);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_read_block struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_read_block C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_read_block_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_flash_fw_read_block_t* flash_fw_read_block)\r\n{\r\n\treturn mavlink_msg_flash_fw_read_block_pack_chan(system_id, component_id, chan, msg, flash_fw_read_block->resp, flash_fw_read_block->addr, flash_fw_read_block->length);\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_read_block message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_flash_fw_read_block_send(mavlink_channel_t chan, uint8_t resp, uint32_t addr, uint16_t length)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN];\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint16_t(buf, 4, length);\r\n\t_mav_put_uint8_t(buf, 6, resp);\r\n\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK, buf, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_CRC);\r\n#else\r\n\tmavlink_flash_fw_read_block_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.length = length;\r\n\tpacket.resp = resp;\r\n\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK, (const char *)&packet, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_read_block message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_flash_fw_read_block_send_struct(mavlink_channel_t chan, const mavlink_flash_fw_read_block_t* flash_fw_read_block)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_flash_fw_read_block_send(chan, flash_fw_read_block->resp, flash_fw_read_block->addr, flash_fw_read_block->length);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK, (const char *)flash_fw_read_block, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_flash_fw_read_block_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, uint32_t addr, uint16_t length)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint16_t(buf, 4, length);\r\n\t_mav_put_uint8_t(buf, 6, resp);\r\n\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK, buf, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_CRC);\r\n#else\r\n\tmavlink_flash_fw_read_block_t *packet = (mavlink_flash_fw_read_block_t *)msgbuf;\r\n\tpacket->addr = addr;\r\n\tpacket->length = length;\r\n\tpacket->resp = resp;\r\n\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK, (const char *)packet, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE FLASH_FW_READ_BLOCK UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from flash_fw_read_block message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_flash_fw_read_block_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  6);\r\n}\r\n\r\n/**\r\n * @brief Get field addr from flash_fw_read_block message\r\n *\r\n * @return \r\n */\r\nstatic inline uint32_t mavlink_msg_flash_fw_read_block_get_addr(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint32_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field length from flash_fw_read_block message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_read_block_get_length(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint16_t(msg,  4);\r\n}\r\n\r\n/**\r\n * @brief Decode a flash_fw_read_block message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param flash_fw_read_block C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_flash_fw_read_block_decode(const mavlink_message_t* msg, mavlink_flash_fw_read_block_t* flash_fw_read_block)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tflash_fw_read_block->addr = mavlink_msg_flash_fw_read_block_get_addr(msg);\r\n\tflash_fw_read_block->length = mavlink_msg_flash_fw_read_block_get_length(msg);\r\n\tflash_fw_read_block->resp = mavlink_msg_flash_fw_read_block_get_resp(msg);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN? msg->len : MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN;\r\n        memset(flash_fw_read_block, 0, MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK_LEN);\r\n\tmemcpy(flash_fw_read_block, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/msg/mavlink/opencr_msg/mavlink_msg_flash_fw_read_packet.h",
    "content": "// MESSAGE FLASH_FW_READ_PACKET PACKING\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_READ_PACKET 160\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_flash_fw_read_packet_t\r\n{\r\n uint32_t addr; /*< */\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n uint8_t length; /*< */\r\n uint8_t data[128]; /*< */\r\n} mavlink_flash_fw_read_packet_t;\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN 134\r\n#define MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_MIN_LEN 134\r\n#define MAVLINK_MSG_ID_160_LEN 134\r\n#define MAVLINK_MSG_ID_160_MIN_LEN 134\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_CRC 9\r\n#define MAVLINK_MSG_ID_160_CRC 9\r\n\r\n#define MAVLINK_MSG_FLASH_FW_READ_PACKET_FIELD_DATA_LEN 128\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_READ_PACKET { \\\r\n\t160, \\\r\n\t\"FLASH_FW_READ_PACKET\", \\\r\n\t4, \\\r\n\t{  { \"addr\", NULL, MAVLINK_TYPE_UINT32_T, 0, 0, offsetof(mavlink_flash_fw_read_packet_t, addr) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 4, offsetof(mavlink_flash_fw_read_packet_t, resp) }, \\\r\n         { \"length\", NULL, MAVLINK_TYPE_UINT8_T, 0, 5, offsetof(mavlink_flash_fw_read_packet_t, length) }, \\\r\n         { \"data\", NULL, MAVLINK_TYPE_UINT8_T, 128, 6, offsetof(mavlink_flash_fw_read_packet_t, data) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_READ_PACKET { \\\r\n\t\"FLASH_FW_READ_PACKET\", \\\r\n\t4, \\\r\n\t{  { \"addr\", NULL, MAVLINK_TYPE_UINT32_T, 0, 0, offsetof(mavlink_flash_fw_read_packet_t, addr) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 4, offsetof(mavlink_flash_fw_read_packet_t, resp) }, \\\r\n         { \"length\", NULL, MAVLINK_TYPE_UINT8_T, 0, 5, offsetof(mavlink_flash_fw_read_packet_t, length) }, \\\r\n         { \"data\", NULL, MAVLINK_TYPE_UINT8_T, 128, 6, offsetof(mavlink_flash_fw_read_packet_t, data) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a flash_fw_read_packet message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n * @param data \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_read_packet_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, uint32_t addr, uint8_t length, const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN];\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint8_t(buf, 4, resp);\r\n\t_mav_put_uint8_t(buf, 5, length);\r\n\t_mav_put_uint8_t_array(buf, 6, data, 128);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN);\r\n#else\r\n\tmavlink_flash_fw_read_packet_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.resp = resp;\r\n\tpacket.length = length;\r\n\tmav_array_memcpy(packet.data, data, sizeof(uint8_t)*128);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_READ_PACKET;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a flash_fw_read_packet message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n * @param data \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_read_packet_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,uint32_t addr,uint8_t length,const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN];\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint8_t(buf, 4, resp);\r\n\t_mav_put_uint8_t(buf, 5, length);\r\n\t_mav_put_uint8_t_array(buf, 6, data, 128);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN);\r\n#else\r\n\tmavlink_flash_fw_read_packet_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.resp = resp;\r\n\tpacket.length = length;\r\n\tmav_array_memcpy(packet.data, data, sizeof(uint8_t)*128);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_READ_PACKET;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_read_packet struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_read_packet C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_read_packet_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_flash_fw_read_packet_t* flash_fw_read_packet)\r\n{\r\n\treturn mavlink_msg_flash_fw_read_packet_pack(system_id, component_id, msg, flash_fw_read_packet->resp, flash_fw_read_packet->addr, flash_fw_read_packet->length, flash_fw_read_packet->data);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_read_packet struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_read_packet C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_read_packet_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_flash_fw_read_packet_t* flash_fw_read_packet)\r\n{\r\n\treturn mavlink_msg_flash_fw_read_packet_pack_chan(system_id, component_id, chan, msg, flash_fw_read_packet->resp, flash_fw_read_packet->addr, flash_fw_read_packet->length, flash_fw_read_packet->data);\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_read_packet message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n * @param data \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_flash_fw_read_packet_send(mavlink_channel_t chan, uint8_t resp, uint32_t addr, uint8_t length, const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN];\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint8_t(buf, 4, resp);\r\n\t_mav_put_uint8_t(buf, 5, length);\r\n\t_mav_put_uint8_t_array(buf, 6, data, 128);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET, buf, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_CRC);\r\n#else\r\n\tmavlink_flash_fw_read_packet_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.resp = resp;\r\n\tpacket.length = length;\r\n\tmav_array_memcpy(packet.data, data, sizeof(uint8_t)*128);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET, (const char *)&packet, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_read_packet message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_flash_fw_read_packet_send_struct(mavlink_channel_t chan, const mavlink_flash_fw_read_packet_t* flash_fw_read_packet)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_flash_fw_read_packet_send(chan, flash_fw_read_packet->resp, flash_fw_read_packet->addr, flash_fw_read_packet->length, flash_fw_read_packet->data);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET, (const char *)flash_fw_read_packet, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_flash_fw_read_packet_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, uint32_t addr, uint8_t length, const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint8_t(buf, 4, resp);\r\n\t_mav_put_uint8_t(buf, 5, length);\r\n\t_mav_put_uint8_t_array(buf, 6, data, 128);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET, buf, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_CRC);\r\n#else\r\n\tmavlink_flash_fw_read_packet_t *packet = (mavlink_flash_fw_read_packet_t *)msgbuf;\r\n\tpacket->addr = addr;\r\n\tpacket->resp = resp;\r\n\tpacket->length = length;\r\n\tmav_array_memcpy(packet->data, data, sizeof(uint8_t)*128);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET, (const char *)packet, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE FLASH_FW_READ_PACKET UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from flash_fw_read_packet message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_flash_fw_read_packet_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  4);\r\n}\r\n\r\n/**\r\n * @brief Get field addr from flash_fw_read_packet message\r\n *\r\n * @return \r\n */\r\nstatic inline uint32_t mavlink_msg_flash_fw_read_packet_get_addr(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint32_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field length from flash_fw_read_packet message\r\n *\r\n * @return \r\n */\r\nstatic inline uint8_t mavlink_msg_flash_fw_read_packet_get_length(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  5);\r\n}\r\n\r\n/**\r\n * @brief Get field data from flash_fw_read_packet message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_read_packet_get_data(const mavlink_message_t* msg, uint8_t *data)\r\n{\r\n\treturn _MAV_RETURN_uint8_t_array(msg, data, 128,  6);\r\n}\r\n\r\n/**\r\n * @brief Decode a flash_fw_read_packet message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param flash_fw_read_packet C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_flash_fw_read_packet_decode(const mavlink_message_t* msg, mavlink_flash_fw_read_packet_t* flash_fw_read_packet)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tflash_fw_read_packet->addr = mavlink_msg_flash_fw_read_packet_get_addr(msg);\r\n\tflash_fw_read_packet->resp = mavlink_msg_flash_fw_read_packet_get_resp(msg);\r\n\tflash_fw_read_packet->length = mavlink_msg_flash_fw_read_packet_get_length(msg);\r\n\tmavlink_msg_flash_fw_read_packet_get_data(msg, flash_fw_read_packet->data);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN? msg->len : MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN;\r\n        memset(flash_fw_read_packet, 0, MAVLINK_MSG_ID_FLASH_FW_READ_PACKET_LEN);\r\n\tmemcpy(flash_fw_read_packet, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/msg/mavlink/opencr_msg/mavlink_msg_flash_fw_verify.h",
    "content": "// MESSAGE FLASH_FW_VERIFY PACKING\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_VERIFY 159\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_flash_fw_verify_t\r\n{\r\n uint32_t length; /*< */\r\n uint32_t crc; /*< */\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n uint8_t param[8]; /*< */\r\n} mavlink_flash_fw_verify_t;\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN 17\r\n#define MAVLINK_MSG_ID_FLASH_FW_VERIFY_MIN_LEN 17\r\n#define MAVLINK_MSG_ID_159_LEN 17\r\n#define MAVLINK_MSG_ID_159_MIN_LEN 17\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_VERIFY_CRC 31\r\n#define MAVLINK_MSG_ID_159_CRC 31\r\n\r\n#define MAVLINK_MSG_FLASH_FW_VERIFY_FIELD_PARAM_LEN 8\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_VERIFY { \\\r\n\t159, \\\r\n\t\"FLASH_FW_VERIFY\", \\\r\n\t4, \\\r\n\t{  { \"length\", NULL, MAVLINK_TYPE_UINT32_T, 0, 0, offsetof(mavlink_flash_fw_verify_t, length) }, \\\r\n         { \"crc\", NULL, MAVLINK_TYPE_UINT32_T, 0, 4, offsetof(mavlink_flash_fw_verify_t, crc) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 8, offsetof(mavlink_flash_fw_verify_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 9, offsetof(mavlink_flash_fw_verify_t, param) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_VERIFY { \\\r\n\t\"FLASH_FW_VERIFY\", \\\r\n\t4, \\\r\n\t{  { \"length\", NULL, MAVLINK_TYPE_UINT32_T, 0, 0, offsetof(mavlink_flash_fw_verify_t, length) }, \\\r\n         { \"crc\", NULL, MAVLINK_TYPE_UINT32_T, 0, 4, offsetof(mavlink_flash_fw_verify_t, crc) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 8, offsetof(mavlink_flash_fw_verify_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 9, offsetof(mavlink_flash_fw_verify_t, param) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a flash_fw_verify message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param length \r\n * @param crc \r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_verify_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, uint32_t length, uint32_t crc, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN];\r\n\t_mav_put_uint32_t(buf, 0, length);\r\n\t_mav_put_uint32_t(buf, 4, crc);\r\n\t_mav_put_uint8_t(buf, 8, resp);\r\n\t_mav_put_uint8_t_array(buf, 9, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN);\r\n#else\r\n\tmavlink_flash_fw_verify_t packet;\r\n\tpacket.length = length;\r\n\tpacket.crc = crc;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_VERIFY;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_FLASH_FW_VERIFY_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a flash_fw_verify message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param length \r\n * @param crc \r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_verify_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,uint32_t length,uint32_t crc,const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN];\r\n\t_mav_put_uint32_t(buf, 0, length);\r\n\t_mav_put_uint32_t(buf, 4, crc);\r\n\t_mav_put_uint8_t(buf, 8, resp);\r\n\t_mav_put_uint8_t_array(buf, 9, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN);\r\n#else\r\n\tmavlink_flash_fw_verify_t packet;\r\n\tpacket.length = length;\r\n\tpacket.crc = crc;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_VERIFY;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_FLASH_FW_VERIFY_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_verify struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_verify C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_verify_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_flash_fw_verify_t* flash_fw_verify)\r\n{\r\n\treturn mavlink_msg_flash_fw_verify_pack(system_id, component_id, msg, flash_fw_verify->resp, flash_fw_verify->length, flash_fw_verify->crc, flash_fw_verify->param);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_verify struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_verify C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_verify_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_flash_fw_verify_t* flash_fw_verify)\r\n{\r\n\treturn mavlink_msg_flash_fw_verify_pack_chan(system_id, component_id, chan, msg, flash_fw_verify->resp, flash_fw_verify->length, flash_fw_verify->crc, flash_fw_verify->param);\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_verify message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param length \r\n * @param crc \r\n * @param param \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_flash_fw_verify_send(mavlink_channel_t chan, uint8_t resp, uint32_t length, uint32_t crc, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN];\r\n\t_mav_put_uint32_t(buf, 0, length);\r\n\t_mav_put_uint32_t(buf, 4, crc);\r\n\t_mav_put_uint8_t(buf, 8, resp);\r\n\t_mav_put_uint8_t_array(buf, 9, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_VERIFY, buf, MAVLINK_MSG_ID_FLASH_FW_VERIFY_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_CRC);\r\n#else\r\n\tmavlink_flash_fw_verify_t packet;\r\n\tpacket.length = length;\r\n\tpacket.crc = crc;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_VERIFY, (const char *)&packet, MAVLINK_MSG_ID_FLASH_FW_VERIFY_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_verify message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_flash_fw_verify_send_struct(mavlink_channel_t chan, const mavlink_flash_fw_verify_t* flash_fw_verify)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_flash_fw_verify_send(chan, flash_fw_verify->resp, flash_fw_verify->length, flash_fw_verify->crc, flash_fw_verify->param);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_VERIFY, (const char *)flash_fw_verify, MAVLINK_MSG_ID_FLASH_FW_VERIFY_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_flash_fw_verify_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, uint32_t length, uint32_t crc, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint32_t(buf, 0, length);\r\n\t_mav_put_uint32_t(buf, 4, crc);\r\n\t_mav_put_uint8_t(buf, 8, resp);\r\n\t_mav_put_uint8_t_array(buf, 9, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_VERIFY, buf, MAVLINK_MSG_ID_FLASH_FW_VERIFY_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_CRC);\r\n#else\r\n\tmavlink_flash_fw_verify_t *packet = (mavlink_flash_fw_verify_t *)msgbuf;\r\n\tpacket->length = length;\r\n\tpacket->crc = crc;\r\n\tpacket->resp = resp;\r\n\tmav_array_memcpy(packet->param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_VERIFY, (const char *)packet, MAVLINK_MSG_ID_FLASH_FW_VERIFY_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN, MAVLINK_MSG_ID_FLASH_FW_VERIFY_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE FLASH_FW_VERIFY UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from flash_fw_verify message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_flash_fw_verify_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  8);\r\n}\r\n\r\n/**\r\n * @brief Get field length from flash_fw_verify message\r\n *\r\n * @return \r\n */\r\nstatic inline uint32_t mavlink_msg_flash_fw_verify_get_length(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint32_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field crc from flash_fw_verify message\r\n *\r\n * @return \r\n */\r\nstatic inline uint32_t mavlink_msg_flash_fw_verify_get_crc(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint32_t(msg,  4);\r\n}\r\n\r\n/**\r\n * @brief Get field param from flash_fw_verify message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_verify_get_param(const mavlink_message_t* msg, uint8_t *param)\r\n{\r\n\treturn _MAV_RETURN_uint8_t_array(msg, param, 8,  9);\r\n}\r\n\r\n/**\r\n * @brief Decode a flash_fw_verify message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param flash_fw_verify C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_flash_fw_verify_decode(const mavlink_message_t* msg, mavlink_flash_fw_verify_t* flash_fw_verify)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tflash_fw_verify->length = mavlink_msg_flash_fw_verify_get_length(msg);\r\n\tflash_fw_verify->crc = mavlink_msg_flash_fw_verify_get_crc(msg);\r\n\tflash_fw_verify->resp = mavlink_msg_flash_fw_verify_get_resp(msg);\r\n\tmavlink_msg_flash_fw_verify_get_param(msg, flash_fw_verify->param);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN? msg->len : MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN;\r\n        memset(flash_fw_verify, 0, MAVLINK_MSG_ID_FLASH_FW_VERIFY_LEN);\r\n\tmemcpy(flash_fw_verify, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/msg/mavlink/opencr_msg/mavlink_msg_flash_fw_write_begin.h",
    "content": "// MESSAGE FLASH_FW_WRITE_BEGIN PACKING\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN 154\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_flash_fw_write_begin_t\r\n{\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n uint8_t param[8]; /*< */\r\n} mavlink_flash_fw_write_begin_t;\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN 9\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_MIN_LEN 9\r\n#define MAVLINK_MSG_ID_154_LEN 9\r\n#define MAVLINK_MSG_ID_154_MIN_LEN 9\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_CRC 8\r\n#define MAVLINK_MSG_ID_154_CRC 8\r\n\r\n#define MAVLINK_MSG_FLASH_FW_WRITE_BEGIN_FIELD_PARAM_LEN 8\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_WRITE_BEGIN { \\\r\n\t154, \\\r\n\t\"FLASH_FW_WRITE_BEGIN\", \\\r\n\t2, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_flash_fw_write_begin_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 1, offsetof(mavlink_flash_fw_write_begin_t, param) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_WRITE_BEGIN { \\\r\n\t\"FLASH_FW_WRITE_BEGIN\", \\\r\n\t2, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_flash_fw_write_begin_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 1, offsetof(mavlink_flash_fw_write_begin_t, param) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a flash_fw_write_begin message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_begin_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN);\r\n#else\r\n\tmavlink_flash_fw_write_begin_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a flash_fw_write_begin message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_begin_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN);\r\n#else\r\n\tmavlink_flash_fw_write_begin_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_write_begin struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_write_begin C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_begin_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_flash_fw_write_begin_t* flash_fw_write_begin)\r\n{\r\n\treturn mavlink_msg_flash_fw_write_begin_pack(system_id, component_id, msg, flash_fw_write_begin->resp, flash_fw_write_begin->param);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_write_begin struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_write_begin C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_begin_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_flash_fw_write_begin_t* flash_fw_write_begin)\r\n{\r\n\treturn mavlink_msg_flash_fw_write_begin_pack_chan(system_id, component_id, chan, msg, flash_fw_write_begin->resp, flash_fw_write_begin->param);\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_write_begin message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_flash_fw_write_begin_send(mavlink_channel_t chan, uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN, buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_CRC);\r\n#else\r\n\tmavlink_flash_fw_write_begin_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN, (const char *)&packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_write_begin message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_begin_send_struct(mavlink_channel_t chan, const mavlink_flash_fw_write_begin_t* flash_fw_write_begin)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_flash_fw_write_begin_send(chan, flash_fw_write_begin->resp, flash_fw_write_begin->param);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN, (const char *)flash_fw_write_begin, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_begin_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN, buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_CRC);\r\n#else\r\n\tmavlink_flash_fw_write_begin_t *packet = (mavlink_flash_fw_write_begin_t *)msgbuf;\r\n\tpacket->resp = resp;\r\n\tmav_array_memcpy(packet->param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN, (const char *)packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE FLASH_FW_WRITE_BEGIN UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from flash_fw_write_begin message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_flash_fw_write_begin_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field param from flash_fw_write_begin message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_begin_get_param(const mavlink_message_t* msg, uint8_t *param)\r\n{\r\n\treturn _MAV_RETURN_uint8_t_array(msg, param, 8,  1);\r\n}\r\n\r\n/**\r\n * @brief Decode a flash_fw_write_begin message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param flash_fw_write_begin C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_begin_decode(const mavlink_message_t* msg, mavlink_flash_fw_write_begin_t* flash_fw_write_begin)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tflash_fw_write_begin->resp = mavlink_msg_flash_fw_write_begin_get_resp(msg);\r\n\tmavlink_msg_flash_fw_write_begin_get_param(msg, flash_fw_write_begin->param);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN? msg->len : MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN;\r\n        memset(flash_fw_write_begin, 0, MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN_LEN);\r\n\tmemcpy(flash_fw_write_begin, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/msg/mavlink/opencr_msg/mavlink_msg_flash_fw_write_block.h",
    "content": "// MESSAGE FLASH_FW_WRITE_BLOCK PACKING\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK 157\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_flash_fw_write_block_t\r\n{\r\n uint32_t addr; /*< */\r\n uint16_t length; /*< */\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n} mavlink_flash_fw_write_block_t;\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN 7\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_MIN_LEN 7\r\n#define MAVLINK_MSG_ID_157_LEN 7\r\n#define MAVLINK_MSG_ID_157_MIN_LEN 7\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_CRC 226\r\n#define MAVLINK_MSG_ID_157_CRC 226\r\n\r\n\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_WRITE_BLOCK { \\\r\n\t157, \\\r\n\t\"FLASH_FW_WRITE_BLOCK\", \\\r\n\t3, \\\r\n\t{  { \"addr\", NULL, MAVLINK_TYPE_UINT32_T, 0, 0, offsetof(mavlink_flash_fw_write_block_t, addr) }, \\\r\n         { \"length\", NULL, MAVLINK_TYPE_UINT16_T, 0, 4, offsetof(mavlink_flash_fw_write_block_t, length) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 6, offsetof(mavlink_flash_fw_write_block_t, resp) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_WRITE_BLOCK { \\\r\n\t\"FLASH_FW_WRITE_BLOCK\", \\\r\n\t3, \\\r\n\t{  { \"addr\", NULL, MAVLINK_TYPE_UINT32_T, 0, 0, offsetof(mavlink_flash_fw_write_block_t, addr) }, \\\r\n         { \"length\", NULL, MAVLINK_TYPE_UINT16_T, 0, 4, offsetof(mavlink_flash_fw_write_block_t, length) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 6, offsetof(mavlink_flash_fw_write_block_t, resp) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a flash_fw_write_block message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_block_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, uint32_t addr, uint16_t length)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN];\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint16_t(buf, 4, length);\r\n\t_mav_put_uint8_t(buf, 6, resp);\r\n\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN);\r\n#else\r\n\tmavlink_flash_fw_write_block_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.length = length;\r\n\tpacket.resp = resp;\r\n\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a flash_fw_write_block message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_block_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,uint32_t addr,uint16_t length)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN];\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint16_t(buf, 4, length);\r\n\t_mav_put_uint8_t(buf, 6, resp);\r\n\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN);\r\n#else\r\n\tmavlink_flash_fw_write_block_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.length = length;\r\n\tpacket.resp = resp;\r\n\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_write_block struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_write_block C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_block_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_flash_fw_write_block_t* flash_fw_write_block)\r\n{\r\n\treturn mavlink_msg_flash_fw_write_block_pack(system_id, component_id, msg, flash_fw_write_block->resp, flash_fw_write_block->addr, flash_fw_write_block->length);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_write_block struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_write_block C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_block_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_flash_fw_write_block_t* flash_fw_write_block)\r\n{\r\n\treturn mavlink_msg_flash_fw_write_block_pack_chan(system_id, component_id, chan, msg, flash_fw_write_block->resp, flash_fw_write_block->addr, flash_fw_write_block->length);\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_write_block message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_flash_fw_write_block_send(mavlink_channel_t chan, uint8_t resp, uint32_t addr, uint16_t length)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN];\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint16_t(buf, 4, length);\r\n\t_mav_put_uint8_t(buf, 6, resp);\r\n\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK, buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_CRC);\r\n#else\r\n\tmavlink_flash_fw_write_block_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.length = length;\r\n\tpacket.resp = resp;\r\n\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK, (const char *)&packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_write_block message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_block_send_struct(mavlink_channel_t chan, const mavlink_flash_fw_write_block_t* flash_fw_write_block)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_flash_fw_write_block_send(chan, flash_fw_write_block->resp, flash_fw_write_block->addr, flash_fw_write_block->length);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK, (const char *)flash_fw_write_block, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_block_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, uint32_t addr, uint16_t length)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint32_t(buf, 0, addr);\r\n\t_mav_put_uint16_t(buf, 4, length);\r\n\t_mav_put_uint8_t(buf, 6, resp);\r\n\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK, buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_CRC);\r\n#else\r\n\tmavlink_flash_fw_write_block_t *packet = (mavlink_flash_fw_write_block_t *)msgbuf;\r\n\tpacket->addr = addr;\r\n\tpacket->length = length;\r\n\tpacket->resp = resp;\r\n\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK, (const char *)packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE FLASH_FW_WRITE_BLOCK UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from flash_fw_write_block message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_flash_fw_write_block_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  6);\r\n}\r\n\r\n/**\r\n * @brief Get field addr from flash_fw_write_block message\r\n *\r\n * @return \r\n */\r\nstatic inline uint32_t mavlink_msg_flash_fw_write_block_get_addr(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint32_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field length from flash_fw_write_block message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_block_get_length(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint16_t(msg,  4);\r\n}\r\n\r\n/**\r\n * @brief Decode a flash_fw_write_block message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param flash_fw_write_block C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_block_decode(const mavlink_message_t* msg, mavlink_flash_fw_write_block_t* flash_fw_write_block)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tflash_fw_write_block->addr = mavlink_msg_flash_fw_write_block_get_addr(msg);\r\n\tflash_fw_write_block->length = mavlink_msg_flash_fw_write_block_get_length(msg);\r\n\tflash_fw_write_block->resp = mavlink_msg_flash_fw_write_block_get_resp(msg);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN? msg->len : MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN;\r\n        memset(flash_fw_write_block, 0, MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK_LEN);\r\n\tmemcpy(flash_fw_write_block, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/msg/mavlink/opencr_msg/mavlink_msg_flash_fw_write_end.h",
    "content": "// MESSAGE FLASH_FW_WRITE_END PACKING\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_END 155\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_flash_fw_write_end_t\r\n{\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n uint8_t param[8]; /*< */\r\n} mavlink_flash_fw_write_end_t;\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN 9\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_END_MIN_LEN 9\r\n#define MAVLINK_MSG_ID_155_LEN 9\r\n#define MAVLINK_MSG_ID_155_MIN_LEN 9\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_END_CRC 48\r\n#define MAVLINK_MSG_ID_155_CRC 48\r\n\r\n#define MAVLINK_MSG_FLASH_FW_WRITE_END_FIELD_PARAM_LEN 8\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_WRITE_END { \\\r\n\t155, \\\r\n\t\"FLASH_FW_WRITE_END\", \\\r\n\t2, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_flash_fw_write_end_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 1, offsetof(mavlink_flash_fw_write_end_t, param) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_WRITE_END { \\\r\n\t\"FLASH_FW_WRITE_END\", \\\r\n\t2, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_flash_fw_write_end_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 1, offsetof(mavlink_flash_fw_write_end_t, param) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a flash_fw_write_end message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_end_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN);\r\n#else\r\n\tmavlink_flash_fw_write_end_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_WRITE_END;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a flash_fw_write_end message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_end_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN);\r\n#else\r\n\tmavlink_flash_fw_write_end_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_WRITE_END;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_write_end struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_write_end C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_end_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_flash_fw_write_end_t* flash_fw_write_end)\r\n{\r\n\treturn mavlink_msg_flash_fw_write_end_pack(system_id, component_id, msg, flash_fw_write_end->resp, flash_fw_write_end->param);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_write_end struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_write_end C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_end_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_flash_fw_write_end_t* flash_fw_write_end)\r\n{\r\n\treturn mavlink_msg_flash_fw_write_end_pack_chan(system_id, component_id, chan, msg, flash_fw_write_end->resp, flash_fw_write_end->param);\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_write_end message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_flash_fw_write_end_send(mavlink_channel_t chan, uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_END, buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_CRC);\r\n#else\r\n\tmavlink_flash_fw_write_end_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_END, (const char *)&packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_write_end message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_end_send_struct(mavlink_channel_t chan, const mavlink_flash_fw_write_end_t* flash_fw_write_end)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_flash_fw_write_end_send(chan, flash_fw_write_end->resp, flash_fw_write_end->param);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_END, (const char *)flash_fw_write_end, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_end_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_END, buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_CRC);\r\n#else\r\n\tmavlink_flash_fw_write_end_t *packet = (mavlink_flash_fw_write_end_t *)msgbuf;\r\n\tpacket->resp = resp;\r\n\tmav_array_memcpy(packet->param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_END, (const char *)packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE FLASH_FW_WRITE_END UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from flash_fw_write_end message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_flash_fw_write_end_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field param from flash_fw_write_end message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_end_get_param(const mavlink_message_t* msg, uint8_t *param)\r\n{\r\n\treturn _MAV_RETURN_uint8_t_array(msg, param, 8,  1);\r\n}\r\n\r\n/**\r\n * @brief Decode a flash_fw_write_end message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param flash_fw_write_end C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_end_decode(const mavlink_message_t* msg, mavlink_flash_fw_write_end_t* flash_fw_write_end)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tflash_fw_write_end->resp = mavlink_msg_flash_fw_write_end_get_resp(msg);\r\n\tmavlink_msg_flash_fw_write_end_get_param(msg, flash_fw_write_end->param);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN? msg->len : MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN;\r\n        memset(flash_fw_write_end, 0, MAVLINK_MSG_ID_FLASH_FW_WRITE_END_LEN);\r\n\tmemcpy(flash_fw_write_end, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/msg/mavlink/opencr_msg/mavlink_msg_flash_fw_write_packet.h",
    "content": "// MESSAGE FLASH_FW_WRITE_PACKET PACKING\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET 156\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_flash_fw_write_packet_t\r\n{\r\n uint16_t addr; /*< */\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n uint8_t length; /*< */\r\n uint8_t data[128]; /*< */\r\n} mavlink_flash_fw_write_packet_t;\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN 132\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_MIN_LEN 132\r\n#define MAVLINK_MSG_ID_156_LEN 132\r\n#define MAVLINK_MSG_ID_156_MIN_LEN 132\r\n\r\n#define MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_CRC 233\r\n#define MAVLINK_MSG_ID_156_CRC 233\r\n\r\n#define MAVLINK_MSG_FLASH_FW_WRITE_PACKET_FIELD_DATA_LEN 128\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_WRITE_PACKET { \\\r\n\t156, \\\r\n\t\"FLASH_FW_WRITE_PACKET\", \\\r\n\t4, \\\r\n\t{  { \"addr\", NULL, MAVLINK_TYPE_UINT16_T, 0, 0, offsetof(mavlink_flash_fw_write_packet_t, addr) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 2, offsetof(mavlink_flash_fw_write_packet_t, resp) }, \\\r\n         { \"length\", NULL, MAVLINK_TYPE_UINT8_T, 0, 3, offsetof(mavlink_flash_fw_write_packet_t, length) }, \\\r\n         { \"data\", NULL, MAVLINK_TYPE_UINT8_T, 128, 4, offsetof(mavlink_flash_fw_write_packet_t, data) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_FLASH_FW_WRITE_PACKET { \\\r\n\t\"FLASH_FW_WRITE_PACKET\", \\\r\n\t4, \\\r\n\t{  { \"addr\", NULL, MAVLINK_TYPE_UINT16_T, 0, 0, offsetof(mavlink_flash_fw_write_packet_t, addr) }, \\\r\n         { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 2, offsetof(mavlink_flash_fw_write_packet_t, resp) }, \\\r\n         { \"length\", NULL, MAVLINK_TYPE_UINT8_T, 0, 3, offsetof(mavlink_flash_fw_write_packet_t, length) }, \\\r\n         { \"data\", NULL, MAVLINK_TYPE_UINT8_T, 128, 4, offsetof(mavlink_flash_fw_write_packet_t, data) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a flash_fw_write_packet message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n * @param data \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_packet_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, uint16_t addr, uint8_t length, const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN];\r\n\t_mav_put_uint16_t(buf, 0, addr);\r\n\t_mav_put_uint8_t(buf, 2, resp);\r\n\t_mav_put_uint8_t(buf, 3, length);\r\n\t_mav_put_uint8_t_array(buf, 4, data, 128);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN);\r\n#else\r\n\tmavlink_flash_fw_write_packet_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.resp = resp;\r\n\tpacket.length = length;\r\n\tmav_array_memcpy(packet.data, data, sizeof(uint8_t)*128);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a flash_fw_write_packet message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n * @param data \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_packet_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,uint16_t addr,uint8_t length,const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN];\r\n\t_mav_put_uint16_t(buf, 0, addr);\r\n\t_mav_put_uint8_t(buf, 2, resp);\r\n\t_mav_put_uint8_t(buf, 3, length);\r\n\t_mav_put_uint8_t_array(buf, 4, data, 128);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN);\r\n#else\r\n\tmavlink_flash_fw_write_packet_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.resp = resp;\r\n\tpacket.length = length;\r\n\tmav_array_memcpy(packet.data, data, sizeof(uint8_t)*128);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_write_packet struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_write_packet C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_packet_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_flash_fw_write_packet_t* flash_fw_write_packet)\r\n{\r\n\treturn mavlink_msg_flash_fw_write_packet_pack(system_id, component_id, msg, flash_fw_write_packet->resp, flash_fw_write_packet->addr, flash_fw_write_packet->length, flash_fw_write_packet->data);\r\n}\r\n\r\n/**\r\n * @brief Encode a flash_fw_write_packet struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param flash_fw_write_packet C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_packet_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_flash_fw_write_packet_t* flash_fw_write_packet)\r\n{\r\n\treturn mavlink_msg_flash_fw_write_packet_pack_chan(system_id, component_id, chan, msg, flash_fw_write_packet->resp, flash_fw_write_packet->addr, flash_fw_write_packet->length, flash_fw_write_packet->data);\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_write_packet message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param addr \r\n * @param length \r\n * @param data \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_flash_fw_write_packet_send(mavlink_channel_t chan, uint8_t resp, uint16_t addr, uint8_t length, const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN];\r\n\t_mav_put_uint16_t(buf, 0, addr);\r\n\t_mav_put_uint8_t(buf, 2, resp);\r\n\t_mav_put_uint8_t(buf, 3, length);\r\n\t_mav_put_uint8_t_array(buf, 4, data, 128);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET, buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_CRC);\r\n#else\r\n\tmavlink_flash_fw_write_packet_t packet;\r\n\tpacket.addr = addr;\r\n\tpacket.resp = resp;\r\n\tpacket.length = length;\r\n\tmav_array_memcpy(packet.data, data, sizeof(uint8_t)*128);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET, (const char *)&packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a flash_fw_write_packet message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_packet_send_struct(mavlink_channel_t chan, const mavlink_flash_fw_write_packet_t* flash_fw_write_packet)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_flash_fw_write_packet_send(chan, flash_fw_write_packet->resp, flash_fw_write_packet->addr, flash_fw_write_packet->length, flash_fw_write_packet->data);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET, (const char *)flash_fw_write_packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_packet_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, uint16_t addr, uint8_t length, const uint8_t *data)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint16_t(buf, 0, addr);\r\n\t_mav_put_uint8_t(buf, 2, resp);\r\n\t_mav_put_uint8_t(buf, 3, length);\r\n\t_mav_put_uint8_t_array(buf, 4, data, 128);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET, buf, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_CRC);\r\n#else\r\n\tmavlink_flash_fw_write_packet_t *packet = (mavlink_flash_fw_write_packet_t *)msgbuf;\r\n\tpacket->addr = addr;\r\n\tpacket->resp = resp;\r\n\tpacket->length = length;\r\n\tmav_array_memcpy(packet->data, data, sizeof(uint8_t)*128);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET, (const char *)packet, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_MIN_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE FLASH_FW_WRITE_PACKET UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from flash_fw_write_packet message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_flash_fw_write_packet_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  2);\r\n}\r\n\r\n/**\r\n * @brief Get field addr from flash_fw_write_packet message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_packet_get_addr(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint16_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field length from flash_fw_write_packet message\r\n *\r\n * @return \r\n */\r\nstatic inline uint8_t mavlink_msg_flash_fw_write_packet_get_length(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  3);\r\n}\r\n\r\n/**\r\n * @brief Get field data from flash_fw_write_packet message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_flash_fw_write_packet_get_data(const mavlink_message_t* msg, uint8_t *data)\r\n{\r\n\treturn _MAV_RETURN_uint8_t_array(msg, data, 128,  4);\r\n}\r\n\r\n/**\r\n * @brief Decode a flash_fw_write_packet message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param flash_fw_write_packet C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_flash_fw_write_packet_decode(const mavlink_message_t* msg, mavlink_flash_fw_write_packet_t* flash_fw_write_packet)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tflash_fw_write_packet->addr = mavlink_msg_flash_fw_write_packet_get_addr(msg);\r\n\tflash_fw_write_packet->resp = mavlink_msg_flash_fw_write_packet_get_resp(msg);\r\n\tflash_fw_write_packet->length = mavlink_msg_flash_fw_write_packet_get_length(msg);\r\n\tmavlink_msg_flash_fw_write_packet_get_data(msg, flash_fw_write_packet->data);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN? msg->len : MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN;\r\n        memset(flash_fw_write_packet, 0, MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET_LEN);\r\n\tmemcpy(flash_fw_write_packet, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/msg/mavlink/opencr_msg/mavlink_msg_jump_to_fw.h",
    "content": "// MESSAGE JUMP_TO_FW PACKING\r\n\r\n#define MAVLINK_MSG_ID_JUMP_TO_FW 162\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_jump_to_fw_t\r\n{\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n uint8_t param[8]; /*< */\r\n} mavlink_jump_to_fw_t;\r\n\r\n#define MAVLINK_MSG_ID_JUMP_TO_FW_LEN 9\r\n#define MAVLINK_MSG_ID_JUMP_TO_FW_MIN_LEN 9\r\n#define MAVLINK_MSG_ID_162_LEN 9\r\n#define MAVLINK_MSG_ID_162_MIN_LEN 9\r\n\r\n#define MAVLINK_MSG_ID_JUMP_TO_FW_CRC 37\r\n#define MAVLINK_MSG_ID_162_CRC 37\r\n\r\n#define MAVLINK_MSG_JUMP_TO_FW_FIELD_PARAM_LEN 8\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_JUMP_TO_FW { \\\r\n\t162, \\\r\n\t\"JUMP_TO_FW\", \\\r\n\t2, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_jump_to_fw_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 1, offsetof(mavlink_jump_to_fw_t, param) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_JUMP_TO_FW { \\\r\n\t\"JUMP_TO_FW\", \\\r\n\t2, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_jump_to_fw_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 1, offsetof(mavlink_jump_to_fw_t, param) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a jump_to_fw message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_jump_to_fw_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_JUMP_TO_FW_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_JUMP_TO_FW_LEN);\r\n#else\r\n\tmavlink_jump_to_fw_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_JUMP_TO_FW_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_JUMP_TO_FW;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_JUMP_TO_FW_MIN_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a jump_to_fw message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_jump_to_fw_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_JUMP_TO_FW_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_JUMP_TO_FW_LEN);\r\n#else\r\n\tmavlink_jump_to_fw_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_JUMP_TO_FW_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_JUMP_TO_FW;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_JUMP_TO_FW_MIN_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a jump_to_fw struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param jump_to_fw C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_jump_to_fw_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_jump_to_fw_t* jump_to_fw)\r\n{\r\n\treturn mavlink_msg_jump_to_fw_pack(system_id, component_id, msg, jump_to_fw->resp, jump_to_fw->param);\r\n}\r\n\r\n/**\r\n * @brief Encode a jump_to_fw struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param jump_to_fw C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_jump_to_fw_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_jump_to_fw_t* jump_to_fw)\r\n{\r\n\treturn mavlink_msg_jump_to_fw_pack_chan(system_id, component_id, chan, msg, jump_to_fw->resp, jump_to_fw->param);\r\n}\r\n\r\n/**\r\n * @brief Send a jump_to_fw message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_jump_to_fw_send(mavlink_channel_t chan, uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_JUMP_TO_FW_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_JUMP_TO_FW, buf, MAVLINK_MSG_ID_JUMP_TO_FW_MIN_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_CRC);\r\n#else\r\n\tmavlink_jump_to_fw_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_JUMP_TO_FW, (const char *)&packet, MAVLINK_MSG_ID_JUMP_TO_FW_MIN_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a jump_to_fw message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_jump_to_fw_send_struct(mavlink_channel_t chan, const mavlink_jump_to_fw_t* jump_to_fw)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_jump_to_fw_send(chan, jump_to_fw->resp, jump_to_fw->param);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_JUMP_TO_FW, (const char *)jump_to_fw, MAVLINK_MSG_ID_JUMP_TO_FW_MIN_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_JUMP_TO_FW_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_jump_to_fw_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_JUMP_TO_FW, buf, MAVLINK_MSG_ID_JUMP_TO_FW_MIN_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_CRC);\r\n#else\r\n\tmavlink_jump_to_fw_t *packet = (mavlink_jump_to_fw_t *)msgbuf;\r\n\tpacket->resp = resp;\r\n\tmav_array_memcpy(packet->param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_JUMP_TO_FW, (const char *)packet, MAVLINK_MSG_ID_JUMP_TO_FW_MIN_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_LEN, MAVLINK_MSG_ID_JUMP_TO_FW_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE JUMP_TO_FW UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from jump_to_fw message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_jump_to_fw_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field param from jump_to_fw message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_jump_to_fw_get_param(const mavlink_message_t* msg, uint8_t *param)\r\n{\r\n\treturn _MAV_RETURN_uint8_t_array(msg, param, 8,  1);\r\n}\r\n\r\n/**\r\n * @brief Decode a jump_to_fw message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param jump_to_fw C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_jump_to_fw_decode(const mavlink_message_t* msg, mavlink_jump_to_fw_t* jump_to_fw)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tjump_to_fw->resp = mavlink_msg_jump_to_fw_get_resp(msg);\r\n\tmavlink_msg_jump_to_fw_get_param(msg, jump_to_fw->param);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_JUMP_TO_FW_LEN? msg->len : MAVLINK_MSG_ID_JUMP_TO_FW_LEN;\r\n        memset(jump_to_fw, 0, MAVLINK_MSG_ID_JUMP_TO_FW_LEN);\r\n\tmemcpy(jump_to_fw, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/msg/mavlink/opencr_msg/mavlink_msg_read_board_name.h",
    "content": "// MESSAGE READ_BOARD_NAME PACKING\r\n\r\n#define MAVLINK_MSG_ID_READ_BOARD_NAME 152\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_read_board_name_t\r\n{\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n uint8_t param[8]; /*< */\r\n} mavlink_read_board_name_t;\r\n\r\n#define MAVLINK_MSG_ID_READ_BOARD_NAME_LEN 9\r\n#define MAVLINK_MSG_ID_READ_BOARD_NAME_MIN_LEN 9\r\n#define MAVLINK_MSG_ID_152_LEN 9\r\n#define MAVLINK_MSG_ID_152_MIN_LEN 9\r\n\r\n#define MAVLINK_MSG_ID_READ_BOARD_NAME_CRC 140\r\n#define MAVLINK_MSG_ID_152_CRC 140\r\n\r\n#define MAVLINK_MSG_READ_BOARD_NAME_FIELD_PARAM_LEN 8\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_READ_BOARD_NAME { \\\r\n\t152, \\\r\n\t\"READ_BOARD_NAME\", \\\r\n\t2, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_read_board_name_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 1, offsetof(mavlink_read_board_name_t, param) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_READ_BOARD_NAME { \\\r\n\t\"READ_BOARD_NAME\", \\\r\n\t2, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_read_board_name_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 1, offsetof(mavlink_read_board_name_t, param) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a read_board_name message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_read_board_name_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_READ_BOARD_NAME_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN);\r\n#else\r\n\tmavlink_read_board_name_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_READ_BOARD_NAME;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_READ_BOARD_NAME_MIN_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a read_board_name message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_read_board_name_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_READ_BOARD_NAME_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN);\r\n#else\r\n\tmavlink_read_board_name_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_READ_BOARD_NAME;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_READ_BOARD_NAME_MIN_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a read_board_name struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param read_board_name C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_read_board_name_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_read_board_name_t* read_board_name)\r\n{\r\n\treturn mavlink_msg_read_board_name_pack(system_id, component_id, msg, read_board_name->resp, read_board_name->param);\r\n}\r\n\r\n/**\r\n * @brief Encode a read_board_name struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param read_board_name C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_read_board_name_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_read_board_name_t* read_board_name)\r\n{\r\n\treturn mavlink_msg_read_board_name_pack_chan(system_id, component_id, chan, msg, read_board_name->resp, read_board_name->param);\r\n}\r\n\r\n/**\r\n * @brief Send a read_board_name message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_read_board_name_send(mavlink_channel_t chan, uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_READ_BOARD_NAME_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_BOARD_NAME, buf, MAVLINK_MSG_ID_READ_BOARD_NAME_MIN_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_CRC);\r\n#else\r\n\tmavlink_read_board_name_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_BOARD_NAME, (const char *)&packet, MAVLINK_MSG_ID_READ_BOARD_NAME_MIN_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a read_board_name message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_read_board_name_send_struct(mavlink_channel_t chan, const mavlink_read_board_name_t* read_board_name)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_read_board_name_send(chan, read_board_name->resp, read_board_name->param);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_BOARD_NAME, (const char *)read_board_name, MAVLINK_MSG_ID_READ_BOARD_NAME_MIN_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_READ_BOARD_NAME_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_read_board_name_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_BOARD_NAME, buf, MAVLINK_MSG_ID_READ_BOARD_NAME_MIN_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_CRC);\r\n#else\r\n\tmavlink_read_board_name_t *packet = (mavlink_read_board_name_t *)msgbuf;\r\n\tpacket->resp = resp;\r\n\tmav_array_memcpy(packet->param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_BOARD_NAME, (const char *)packet, MAVLINK_MSG_ID_READ_BOARD_NAME_MIN_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN, MAVLINK_MSG_ID_READ_BOARD_NAME_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE READ_BOARD_NAME UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from read_board_name message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_read_board_name_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field param from read_board_name message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_read_board_name_get_param(const mavlink_message_t* msg, uint8_t *param)\r\n{\r\n\treturn _MAV_RETURN_uint8_t_array(msg, param, 8,  1);\r\n}\r\n\r\n/**\r\n * @brief Decode a read_board_name message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param read_board_name C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_read_board_name_decode(const mavlink_message_t* msg, mavlink_read_board_name_t* read_board_name)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tread_board_name->resp = mavlink_msg_read_board_name_get_resp(msg);\r\n\tmavlink_msg_read_board_name_get_param(msg, read_board_name->param);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_READ_BOARD_NAME_LEN? msg->len : MAVLINK_MSG_ID_READ_BOARD_NAME_LEN;\r\n        memset(read_board_name, 0, MAVLINK_MSG_ID_READ_BOARD_NAME_LEN);\r\n\tmemcpy(read_board_name, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/msg/mavlink/opencr_msg/mavlink_msg_read_tag.h",
    "content": "// MESSAGE READ_TAG PACKING\r\n\r\n#define MAVLINK_MSG_ID_READ_TAG 153\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_read_tag_t\r\n{\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n uint8_t type; /*< */\r\n uint8_t param[8]; /*< */\r\n} mavlink_read_tag_t;\r\n\r\n#define MAVLINK_MSG_ID_READ_TAG_LEN 10\r\n#define MAVLINK_MSG_ID_READ_TAG_MIN_LEN 10\r\n#define MAVLINK_MSG_ID_153_LEN 10\r\n#define MAVLINK_MSG_ID_153_MIN_LEN 10\r\n\r\n#define MAVLINK_MSG_ID_READ_TAG_CRC 126\r\n#define MAVLINK_MSG_ID_153_CRC 126\r\n\r\n#define MAVLINK_MSG_READ_TAG_FIELD_PARAM_LEN 8\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_READ_TAG { \\\r\n\t153, \\\r\n\t\"READ_TAG\", \\\r\n\t3, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_read_tag_t, resp) }, \\\r\n         { \"type\", NULL, MAVLINK_TYPE_UINT8_T, 0, 1, offsetof(mavlink_read_tag_t, type) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 2, offsetof(mavlink_read_tag_t, param) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_READ_TAG { \\\r\n\t\"READ_TAG\", \\\r\n\t3, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_read_tag_t, resp) }, \\\r\n         { \"type\", NULL, MAVLINK_TYPE_UINT8_T, 0, 1, offsetof(mavlink_read_tag_t, type) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 2, offsetof(mavlink_read_tag_t, param) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a read_tag message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param type \r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_read_tag_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, uint8_t type, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_READ_TAG_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t(buf, 1, type);\r\n\t_mav_put_uint8_t_array(buf, 2, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_READ_TAG_LEN);\r\n#else\r\n\tmavlink_read_tag_t packet;\r\n\tpacket.resp = resp;\r\n\tpacket.type = type;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_READ_TAG_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_READ_TAG;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_READ_TAG_MIN_LEN, MAVLINK_MSG_ID_READ_TAG_LEN, MAVLINK_MSG_ID_READ_TAG_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a read_tag message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param type \r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_read_tag_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,uint8_t type,const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_READ_TAG_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t(buf, 1, type);\r\n\t_mav_put_uint8_t_array(buf, 2, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_READ_TAG_LEN);\r\n#else\r\n\tmavlink_read_tag_t packet;\r\n\tpacket.resp = resp;\r\n\tpacket.type = type;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_READ_TAG_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_READ_TAG;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_READ_TAG_MIN_LEN, MAVLINK_MSG_ID_READ_TAG_LEN, MAVLINK_MSG_ID_READ_TAG_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a read_tag struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param read_tag C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_read_tag_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_read_tag_t* read_tag)\r\n{\r\n\treturn mavlink_msg_read_tag_pack(system_id, component_id, msg, read_tag->resp, read_tag->type, read_tag->param);\r\n}\r\n\r\n/**\r\n * @brief Encode a read_tag struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param read_tag C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_read_tag_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_read_tag_t* read_tag)\r\n{\r\n\treturn mavlink_msg_read_tag_pack_chan(system_id, component_id, chan, msg, read_tag->resp, read_tag->type, read_tag->param);\r\n}\r\n\r\n/**\r\n * @brief Send a read_tag message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param type \r\n * @param param \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_read_tag_send(mavlink_channel_t chan, uint8_t resp, uint8_t type, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_READ_TAG_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t(buf, 1, type);\r\n\t_mav_put_uint8_t_array(buf, 2, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_TAG, buf, MAVLINK_MSG_ID_READ_TAG_MIN_LEN, MAVLINK_MSG_ID_READ_TAG_LEN, MAVLINK_MSG_ID_READ_TAG_CRC);\r\n#else\r\n\tmavlink_read_tag_t packet;\r\n\tpacket.resp = resp;\r\n\tpacket.type = type;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_TAG, (const char *)&packet, MAVLINK_MSG_ID_READ_TAG_MIN_LEN, MAVLINK_MSG_ID_READ_TAG_LEN, MAVLINK_MSG_ID_READ_TAG_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a read_tag message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_read_tag_send_struct(mavlink_channel_t chan, const mavlink_read_tag_t* read_tag)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_read_tag_send(chan, read_tag->resp, read_tag->type, read_tag->param);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_TAG, (const char *)read_tag, MAVLINK_MSG_ID_READ_TAG_MIN_LEN, MAVLINK_MSG_ID_READ_TAG_LEN, MAVLINK_MSG_ID_READ_TAG_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_READ_TAG_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_read_tag_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, uint8_t type, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t(buf, 1, type);\r\n\t_mav_put_uint8_t_array(buf, 2, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_TAG, buf, MAVLINK_MSG_ID_READ_TAG_MIN_LEN, MAVLINK_MSG_ID_READ_TAG_LEN, MAVLINK_MSG_ID_READ_TAG_CRC);\r\n#else\r\n\tmavlink_read_tag_t *packet = (mavlink_read_tag_t *)msgbuf;\r\n\tpacket->resp = resp;\r\n\tpacket->type = type;\r\n\tmav_array_memcpy(packet->param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_TAG, (const char *)packet, MAVLINK_MSG_ID_READ_TAG_MIN_LEN, MAVLINK_MSG_ID_READ_TAG_LEN, MAVLINK_MSG_ID_READ_TAG_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE READ_TAG UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from read_tag message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_read_tag_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field type from read_tag message\r\n *\r\n * @return \r\n */\r\nstatic inline uint8_t mavlink_msg_read_tag_get_type(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  1);\r\n}\r\n\r\n/**\r\n * @brief Get field param from read_tag message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_read_tag_get_param(const mavlink_message_t* msg, uint8_t *param)\r\n{\r\n\treturn _MAV_RETURN_uint8_t_array(msg, param, 8,  2);\r\n}\r\n\r\n/**\r\n * @brief Decode a read_tag message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param read_tag C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_read_tag_decode(const mavlink_message_t* msg, mavlink_read_tag_t* read_tag)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tread_tag->resp = mavlink_msg_read_tag_get_resp(msg);\r\n\tread_tag->type = mavlink_msg_read_tag_get_type(msg);\r\n\tmavlink_msg_read_tag_get_param(msg, read_tag->param);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_READ_TAG_LEN? msg->len : MAVLINK_MSG_ID_READ_TAG_LEN;\r\n        memset(read_tag, 0, MAVLINK_MSG_ID_READ_TAG_LEN);\r\n\tmemcpy(read_tag, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/msg/mavlink/opencr_msg/mavlink_msg_read_version.h",
    "content": "// MESSAGE READ_VERSION PACKING\r\n\r\n#define MAVLINK_MSG_ID_READ_VERSION 151\r\n\r\ntypedef struct MAVLINK_PACKED __mavlink_read_version_t\r\n{\r\n uint8_t resp; /*< 0:No Resp, 1:Resp*/\r\n uint8_t param[8]; /*< */\r\n} mavlink_read_version_t;\r\n\r\n#define MAVLINK_MSG_ID_READ_VERSION_LEN 9\r\n#define MAVLINK_MSG_ID_READ_VERSION_MIN_LEN 9\r\n#define MAVLINK_MSG_ID_151_LEN 9\r\n#define MAVLINK_MSG_ID_151_MIN_LEN 9\r\n\r\n#define MAVLINK_MSG_ID_READ_VERSION_CRC 166\r\n#define MAVLINK_MSG_ID_151_CRC 166\r\n\r\n#define MAVLINK_MSG_READ_VERSION_FIELD_PARAM_LEN 8\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#define MAVLINK_MESSAGE_INFO_READ_VERSION { \\\r\n\t151, \\\r\n\t\"READ_VERSION\", \\\r\n\t2, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_read_version_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 1, offsetof(mavlink_read_version_t, param) }, \\\r\n         } \\\r\n}\r\n#else\r\n#define MAVLINK_MESSAGE_INFO_READ_VERSION { \\\r\n\t\"READ_VERSION\", \\\r\n\t2, \\\r\n\t{  { \"resp\", NULL, MAVLINK_TYPE_UINT8_T, 0, 0, offsetof(mavlink_read_version_t, resp) }, \\\r\n         { \"param\", NULL, MAVLINK_TYPE_UINT8_T, 8, 1, offsetof(mavlink_read_version_t, param) }, \\\r\n         } \\\r\n}\r\n#endif\r\n\r\n/**\r\n * @brief Pack a read_version message\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_read_version_pack(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg,\r\n\t\t\t\t\t\t       uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_READ_VERSION_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_READ_VERSION_LEN);\r\n#else\r\n\tmavlink_read_version_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_READ_VERSION_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_READ_VERSION;\r\n    return mavlink_finalize_message(msg, system_id, component_id, MAVLINK_MSG_ID_READ_VERSION_MIN_LEN, MAVLINK_MSG_ID_READ_VERSION_LEN, MAVLINK_MSG_ID_READ_VERSION_CRC);\r\n}\r\n\r\n/**\r\n * @brief Pack a read_version message on a channel\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n * @return length of the message in bytes (excluding serial stream start sign)\r\n */\r\nstatic inline uint16_t mavlink_msg_read_version_pack_chan(uint8_t system_id, uint8_t component_id, uint8_t chan,\r\n\t\t\t\t\t\t\t   mavlink_message_t* msg,\r\n\t\t\t\t\t\t           uint8_t resp,const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_READ_VERSION_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), buf, MAVLINK_MSG_ID_READ_VERSION_LEN);\r\n#else\r\n\tmavlink_read_version_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n        memcpy(_MAV_PAYLOAD_NON_CONST(msg), &packet, MAVLINK_MSG_ID_READ_VERSION_LEN);\r\n#endif\r\n\r\n\tmsg->msgid = MAVLINK_MSG_ID_READ_VERSION;\r\n    return mavlink_finalize_message_chan(msg, system_id, component_id, chan, MAVLINK_MSG_ID_READ_VERSION_MIN_LEN, MAVLINK_MSG_ID_READ_VERSION_LEN, MAVLINK_MSG_ID_READ_VERSION_CRC);\r\n}\r\n\r\n/**\r\n * @brief Encode a read_version struct\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param msg The MAVLink message to compress the data into\r\n * @param read_version C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_read_version_encode(uint8_t system_id, uint8_t component_id, mavlink_message_t* msg, const mavlink_read_version_t* read_version)\r\n{\r\n\treturn mavlink_msg_read_version_pack(system_id, component_id, msg, read_version->resp, read_version->param);\r\n}\r\n\r\n/**\r\n * @brief Encode a read_version struct on a channel\r\n *\r\n * @param system_id ID of this system\r\n * @param component_id ID of this component (e.g. 200 for IMU)\r\n * @param chan The MAVLink channel this message will be sent over\r\n * @param msg The MAVLink message to compress the data into\r\n * @param read_version C-struct to read the message contents from\r\n */\r\nstatic inline uint16_t mavlink_msg_read_version_encode_chan(uint8_t system_id, uint8_t component_id, uint8_t chan, mavlink_message_t* msg, const mavlink_read_version_t* read_version)\r\n{\r\n\treturn mavlink_msg_read_version_pack_chan(system_id, component_id, chan, msg, read_version->resp, read_version->param);\r\n}\r\n\r\n/**\r\n * @brief Send a read_version message\r\n * @param chan MAVLink channel to send the message\r\n *\r\n * @param resp 0:No Resp, 1:Resp\r\n * @param param \r\n */\r\n#ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n\r\nstatic inline void mavlink_msg_read_version_send(mavlink_channel_t chan, uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar buf[MAVLINK_MSG_ID_READ_VERSION_LEN];\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_VERSION, buf, MAVLINK_MSG_ID_READ_VERSION_MIN_LEN, MAVLINK_MSG_ID_READ_VERSION_LEN, MAVLINK_MSG_ID_READ_VERSION_CRC);\r\n#else\r\n\tmavlink_read_version_t packet;\r\n\tpacket.resp = resp;\r\n\tmav_array_memcpy(packet.param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_VERSION, (const char *)&packet, MAVLINK_MSG_ID_READ_VERSION_MIN_LEN, MAVLINK_MSG_ID_READ_VERSION_LEN, MAVLINK_MSG_ID_READ_VERSION_CRC);\r\n#endif\r\n}\r\n\r\n/**\r\n * @brief Send a read_version message\r\n * @param chan MAVLink channel to send the message\r\n * @param struct The MAVLink struct to serialize\r\n */\r\nstatic inline void mavlink_msg_read_version_send_struct(mavlink_channel_t chan, const mavlink_read_version_t* read_version)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n    mavlink_msg_read_version_send(chan, read_version->resp, read_version->param);\r\n#else\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_VERSION, (const char *)read_version, MAVLINK_MSG_ID_READ_VERSION_MIN_LEN, MAVLINK_MSG_ID_READ_VERSION_LEN, MAVLINK_MSG_ID_READ_VERSION_CRC);\r\n#endif\r\n}\r\n\r\n#if MAVLINK_MSG_ID_READ_VERSION_LEN <= MAVLINK_MAX_PAYLOAD_LEN\r\n/*\r\n  This varient of _send() can be used to save stack space by re-using\r\n  memory from the receive buffer.  The caller provides a\r\n  mavlink_message_t which is the size of a full mavlink message. This\r\n  is usually the receive buffer for the channel, and allows a reply to an\r\n  incoming message with minimum stack space usage.\r\n */\r\nstatic inline void mavlink_msg_read_version_send_buf(mavlink_message_t *msgbuf, mavlink_channel_t chan,  uint8_t resp, const uint8_t *param)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tchar *buf = (char *)msgbuf;\r\n\t_mav_put_uint8_t(buf, 0, resp);\r\n\t_mav_put_uint8_t_array(buf, 1, param, 8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_VERSION, buf, MAVLINK_MSG_ID_READ_VERSION_MIN_LEN, MAVLINK_MSG_ID_READ_VERSION_LEN, MAVLINK_MSG_ID_READ_VERSION_CRC);\r\n#else\r\n\tmavlink_read_version_t *packet = (mavlink_read_version_t *)msgbuf;\r\n\tpacket->resp = resp;\r\n\tmav_array_memcpy(packet->param, param, sizeof(uint8_t)*8);\r\n    _mav_finalize_message_chan_send(chan, MAVLINK_MSG_ID_READ_VERSION, (const char *)packet, MAVLINK_MSG_ID_READ_VERSION_MIN_LEN, MAVLINK_MSG_ID_READ_VERSION_LEN, MAVLINK_MSG_ID_READ_VERSION_CRC);\r\n#endif\r\n}\r\n#endif\r\n\r\n#endif\r\n\r\n// MESSAGE READ_VERSION UNPACKING\r\n\r\n\r\n/**\r\n * @brief Get field resp from read_version message\r\n *\r\n * @return 0:No Resp, 1:Resp\r\n */\r\nstatic inline uint8_t mavlink_msg_read_version_get_resp(const mavlink_message_t* msg)\r\n{\r\n\treturn _MAV_RETURN_uint8_t(msg,  0);\r\n}\r\n\r\n/**\r\n * @brief Get field param from read_version message\r\n *\r\n * @return \r\n */\r\nstatic inline uint16_t mavlink_msg_read_version_get_param(const mavlink_message_t* msg, uint8_t *param)\r\n{\r\n\treturn _MAV_RETURN_uint8_t_array(msg, param, 8,  1);\r\n}\r\n\r\n/**\r\n * @brief Decode a read_version message into a struct\r\n *\r\n * @param msg The message to decode\r\n * @param read_version C-struct to decode the message contents into\r\n */\r\nstatic inline void mavlink_msg_read_version_decode(const mavlink_message_t* msg, mavlink_read_version_t* read_version)\r\n{\r\n#if MAVLINK_NEED_BYTE_SWAP || !MAVLINK_ALIGNED_FIELDS\r\n\tread_version->resp = mavlink_msg_read_version_get_resp(msg);\r\n\tmavlink_msg_read_version_get_param(msg, read_version->param);\r\n#else\r\n        uint8_t len = msg->len < MAVLINK_MSG_ID_READ_VERSION_LEN? msg->len : MAVLINK_MSG_ID_READ_VERSION_LEN;\r\n        memset(read_version, 0, MAVLINK_MSG_ID_READ_VERSION_LEN);\r\n\tmemcpy(read_version, _MAV_PAYLOAD(msg), len);\r\n#endif\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/msg/mavlink/opencr_msg/opencr_msg.h",
    "content": "/** @file\r\n *\t@brief MAVLink comm protocol generated from opencr_msg.xml\r\n *\t@see http://mavlink.org\r\n */\r\n#ifndef MAVLINK_OPENCR_MSG_H\r\n#define MAVLINK_OPENCR_MSG_H\r\n\r\n#ifndef MAVLINK_H\r\n    #error Wrong include order: MAVLINK_OPENCR_MSG.H MUST NOT BE DIRECTLY USED. Include mavlink.h from the same directory instead or set ALL AND EVERY defines from MAVLINK.H manually accordingly, including the #define MAVLINK_H call.\r\n#endif\r\n\r\n#ifdef __cplusplus\r\nextern \"C\" {\r\n#endif\r\n\r\n// MESSAGE LENGTHS AND CRCS\r\n\r\n#ifndef MAVLINK_MESSAGE_LENGTHS\r\n#define MAVLINK_MESSAGE_LENGTHS {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 20, 9, 9, 10, 9, 9, 132, 7, 13, 17, 134, 7, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}\r\n#endif\r\n\r\n#ifndef MAVLINK_MESSAGE_CRCS\r\n#define MAVLINK_MESSAGE_CRCS {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 192, 166, 140, 126, 8, 48, 233, 226, 13, 31, 9, 131, 37, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}\r\n#endif\r\n\r\n#ifndef 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{\"EMPTY\",0,{{\"\",\"\",MAVLINK_TYPE_CHAR,0,0,0}}}}\r\n#endif\r\n\r\n#include \"../protocol.h\"\r\n\r\n#define MAVLINK_ENABLED_OPENCR_MSG\r\n\r\n// ENUM DEFINITIONS\r\n\r\n\r\n\r\n// MAVLINK VERSION\r\n\r\n#ifndef MAVLINK_VERSION\r\n#define MAVLINK_VERSION 2\r\n#endif\r\n\r\n#if (MAVLINK_VERSION == 0)\r\n#undef MAVLINK_VERSION\r\n#define MAVLINK_VERSION 2\r\n#endif\r\n\r\n// MESSAGE DEFINITIONS\r\n#include \"./mavlink_msg_ack.h\"\r\n#include \"./mavlink_msg_read_version.h\"\r\n#include \"./mavlink_msg_read_board_name.h\"\r\n#include \"./mavlink_msg_read_tag.h\"\r\n#include \"./mavlink_msg_flash_fw_write_begin.h\"\r\n#include \"./mavlink_msg_flash_fw_write_end.h\"\r\n#include \"./mavlink_msg_flash_fw_write_packet.h\"\r\n#include \"./mavlink_msg_flash_fw_write_block.h\"\r\n#include \"./mavlink_msg_flash_fw_erase.h\"\r\n#include \"./mavlink_msg_flash_fw_verify.h\"\r\n#include \"./mavlink_msg_flash_fw_read_packet.h\"\r\n#include \"./mavlink_msg_flash_fw_read_block.h\"\r\n#include \"./mavlink_msg_jump_to_fw.h\"\r\n\r\n// base include\r\n\r\n\r\n#if MAVLINK_COMMAND_24BIT\r\n#include \"../mavlink_get_info.h\"\r\n#endif\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif // __cplusplus\r\n#endif // MAVLINK_OPENCR_MSG_H\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/msg/mavlink/opencr_msg/testsuite.h",
    "content": "/** @file\r\n *\t@brief MAVLink comm protocol testsuite generated from opencr_msg.xml\r\n *\t@see http://qgroundcontrol.org/mavlink/\r\n */\r\n#ifndef OPENCR_MSG_TESTSUITE_H\r\n#define OPENCR_MSG_TESTSUITE_H\r\n\r\n#ifdef __cplusplus\r\nextern \"C\" {\r\n#endif\r\n\r\n#ifndef MAVLINK_TEST_ALL\r\n#define MAVLINK_TEST_ALL\r\n\r\nstatic void mavlink_test_opencr_msg(uint8_t, uint8_t, mavlink_message_t *last_msg);\r\n\r\nstatic void mavlink_test_all(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n\r\n\tmavlink_test_opencr_msg(system_id, component_id, last_msg);\r\n}\r\n#endif\r\n\r\n\r\n\r\n\r\nstatic void mavlink_test_ack(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_ACK >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_ack_t packet_in = {\r\n\t\t17235,139,206,{ 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 }\r\n    };\r\n\tmavlink_ack_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.err_code = packet_in.err_code;\r\n        packet1.msg_id = packet_in.msg_id;\r\n        packet1.length = packet_in.length;\r\n        \r\n        mav_array_memcpy(packet1.data, packet_in.data, sizeof(uint8_t)*16);\r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_ack_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_ack_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_ack_pack(system_id, component_id, &msg , packet1.msg_id , packet1.err_code , packet1.length , packet1.data );\r\n\tmavlink_msg_ack_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_ack_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.msg_id , packet1.err_code , packet1.length , packet1.data );\r\n\tmavlink_msg_ack_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_ack_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_ack_send(MAVLINK_COMM_1 , packet1.msg_id , packet1.err_code , packet1.length , packet1.data );\r\n\tmavlink_msg_ack_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_read_version(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_READ_VERSION >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_read_version_t packet_in = {\r\n\t\t5,{ 72, 73, 74, 75, 76, 77, 78, 79 }\r\n    };\r\n\tmavlink_read_version_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.resp = packet_in.resp;\r\n        \r\n        mav_array_memcpy(packet1.param, packet_in.param, sizeof(uint8_t)*8);\r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_version_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_read_version_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_version_pack(system_id, component_id, &msg , packet1.resp , packet1.param );\r\n\tmavlink_msg_read_version_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_version_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.param );\r\n\tmavlink_msg_read_version_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_read_version_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_version_send(MAVLINK_COMM_1 , packet1.resp , packet1.param );\r\n\tmavlink_msg_read_version_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_read_board_name(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_READ_BOARD_NAME >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_read_board_name_t packet_in = {\r\n\t\t5,{ 72, 73, 74, 75, 76, 77, 78, 79 }\r\n    };\r\n\tmavlink_read_board_name_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.resp = packet_in.resp;\r\n        \r\n        mav_array_memcpy(packet1.param, packet_in.param, sizeof(uint8_t)*8);\r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_board_name_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_read_board_name_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_board_name_pack(system_id, component_id, &msg , packet1.resp , packet1.param );\r\n\tmavlink_msg_read_board_name_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_board_name_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.param );\r\n\tmavlink_msg_read_board_name_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_read_board_name_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_board_name_send(MAVLINK_COMM_1 , packet1.resp , packet1.param );\r\n\tmavlink_msg_read_board_name_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_read_tag(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_READ_TAG >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_read_tag_t packet_in = {\r\n\t\t5,72,{ 139, 140, 141, 142, 143, 144, 145, 146 }\r\n    };\r\n\tmavlink_read_tag_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.resp = packet_in.resp;\r\n        packet1.type = packet_in.type;\r\n        \r\n        mav_array_memcpy(packet1.param, packet_in.param, sizeof(uint8_t)*8);\r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_tag_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_read_tag_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_tag_pack(system_id, component_id, &msg , packet1.resp , packet1.type , packet1.param );\r\n\tmavlink_msg_read_tag_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_tag_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.type , packet1.param );\r\n\tmavlink_msg_read_tag_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_read_tag_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_read_tag_send(MAVLINK_COMM_1 , packet1.resp , packet1.type , packet1.param );\r\n\tmavlink_msg_read_tag_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_flash_fw_write_begin(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_FLASH_FW_WRITE_BEGIN >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_flash_fw_write_begin_t packet_in = {\r\n\t\t5,{ 72, 73, 74, 75, 76, 77, 78, 79 }\r\n    };\r\n\tmavlink_flash_fw_write_begin_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.resp = packet_in.resp;\r\n        \r\n        mav_array_memcpy(packet1.param, packet_in.param, sizeof(uint8_t)*8);\r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_begin_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_flash_fw_write_begin_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_begin_pack(system_id, component_id, &msg , packet1.resp , packet1.param );\r\n\tmavlink_msg_flash_fw_write_begin_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_begin_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.param );\r\n\tmavlink_msg_flash_fw_write_begin_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_flash_fw_write_begin_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_begin_send(MAVLINK_COMM_1 , packet1.resp , packet1.param );\r\n\tmavlink_msg_flash_fw_write_begin_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_flash_fw_write_end(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_FLASH_FW_WRITE_END >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_flash_fw_write_end_t packet_in = {\r\n\t\t5,{ 72, 73, 74, 75, 76, 77, 78, 79 }\r\n    };\r\n\tmavlink_flash_fw_write_end_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.resp = packet_in.resp;\r\n        \r\n        mav_array_memcpy(packet1.param, packet_in.param, sizeof(uint8_t)*8);\r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_end_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_flash_fw_write_end_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_end_pack(system_id, component_id, &msg , packet1.resp , packet1.param );\r\n\tmavlink_msg_flash_fw_write_end_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_end_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.param );\r\n\tmavlink_msg_flash_fw_write_end_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_flash_fw_write_end_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_end_send(MAVLINK_COMM_1 , packet1.resp , packet1.param );\r\n\tmavlink_msg_flash_fw_write_end_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_flash_fw_write_packet(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_FLASH_FW_WRITE_PACKET >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_flash_fw_write_packet_t packet_in = {\r\n\t\t17235,139,206,{ 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144 }\r\n    };\r\n\tmavlink_flash_fw_write_packet_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.addr = packet_in.addr;\r\n        packet1.resp = packet_in.resp;\r\n        packet1.length = packet_in.length;\r\n        \r\n        mav_array_memcpy(packet1.data, packet_in.data, sizeof(uint8_t)*128);\r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_packet_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_flash_fw_write_packet_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_packet_pack(system_id, component_id, &msg , packet1.resp , packet1.addr , packet1.length , packet1.data );\r\n\tmavlink_msg_flash_fw_write_packet_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_packet_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.addr , packet1.length , packet1.data );\r\n\tmavlink_msg_flash_fw_write_packet_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_flash_fw_write_packet_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_packet_send(MAVLINK_COMM_1 , packet1.resp , packet1.addr , packet1.length , packet1.data );\r\n\tmavlink_msg_flash_fw_write_packet_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_flash_fw_write_block(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_FLASH_FW_WRITE_BLOCK >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_flash_fw_write_block_t packet_in = {\r\n\t\t963497464,17443,151\r\n    };\r\n\tmavlink_flash_fw_write_block_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.addr = packet_in.addr;\r\n        packet1.length = packet_in.length;\r\n        packet1.resp = packet_in.resp;\r\n        \r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_block_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_flash_fw_write_block_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_block_pack(system_id, component_id, &msg , packet1.resp , packet1.addr , packet1.length );\r\n\tmavlink_msg_flash_fw_write_block_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_block_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.addr , packet1.length );\r\n\tmavlink_msg_flash_fw_write_block_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_flash_fw_write_block_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_write_block_send(MAVLINK_COMM_1 , packet1.resp , packet1.addr , packet1.length );\r\n\tmavlink_msg_flash_fw_write_block_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_flash_fw_erase(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_FLASH_FW_ERASE >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_flash_fw_erase_t packet_in = {\r\n\t\t963497464,17,{ 84, 85, 86, 87, 88, 89, 90, 91 }\r\n    };\r\n\tmavlink_flash_fw_erase_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.length = packet_in.length;\r\n        packet1.resp = packet_in.resp;\r\n        \r\n        mav_array_memcpy(packet1.param, packet_in.param, sizeof(uint8_t)*8);\r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_erase_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_flash_fw_erase_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_erase_pack(system_id, component_id, &msg , packet1.resp , packet1.length , packet1.param );\r\n\tmavlink_msg_flash_fw_erase_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_erase_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.length , packet1.param );\r\n\tmavlink_msg_flash_fw_erase_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_flash_fw_erase_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_erase_send(MAVLINK_COMM_1 , packet1.resp , packet1.length , packet1.param );\r\n\tmavlink_msg_flash_fw_erase_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_flash_fw_verify(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_FLASH_FW_VERIFY >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_flash_fw_verify_t packet_in = {\r\n\t\t963497464,963497672,29,{ 96, 97, 98, 99, 100, 101, 102, 103 }\r\n    };\r\n\tmavlink_flash_fw_verify_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.length = packet_in.length;\r\n        packet1.crc = packet_in.crc;\r\n        packet1.resp = packet_in.resp;\r\n        \r\n        mav_array_memcpy(packet1.param, packet_in.param, sizeof(uint8_t)*8);\r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_verify_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_flash_fw_verify_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_verify_pack(system_id, component_id, &msg , packet1.resp , packet1.length , packet1.crc , packet1.param );\r\n\tmavlink_msg_flash_fw_verify_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_verify_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.length , packet1.crc , packet1.param );\r\n\tmavlink_msg_flash_fw_verify_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_flash_fw_verify_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_verify_send(MAVLINK_COMM_1 , packet1.resp , packet1.length , packet1.crc , packet1.param );\r\n\tmavlink_msg_flash_fw_verify_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_flash_fw_read_packet(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_FLASH_FW_READ_PACKET >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_flash_fw_read_packet_t packet_in = {\r\n\t\t963497464,17,84,{ 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22 }\r\n    };\r\n\tmavlink_flash_fw_read_packet_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.addr = packet_in.addr;\r\n        packet1.resp = packet_in.resp;\r\n        packet1.length = packet_in.length;\r\n        \r\n        mav_array_memcpy(packet1.data, packet_in.data, sizeof(uint8_t)*128);\r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_read_packet_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_flash_fw_read_packet_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_read_packet_pack(system_id, component_id, &msg , packet1.resp , packet1.addr , packet1.length , packet1.data );\r\n\tmavlink_msg_flash_fw_read_packet_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_read_packet_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.addr , packet1.length , packet1.data );\r\n\tmavlink_msg_flash_fw_read_packet_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_flash_fw_read_packet_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_read_packet_send(MAVLINK_COMM_1 , packet1.resp , packet1.addr , packet1.length , packet1.data );\r\n\tmavlink_msg_flash_fw_read_packet_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_flash_fw_read_block(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_FLASH_FW_READ_BLOCK >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_flash_fw_read_block_t packet_in = {\r\n\t\t963497464,17443,151\r\n    };\r\n\tmavlink_flash_fw_read_block_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.addr = packet_in.addr;\r\n        packet1.length = packet_in.length;\r\n        packet1.resp = packet_in.resp;\r\n        \r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_read_block_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_flash_fw_read_block_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_read_block_pack(system_id, component_id, &msg , packet1.resp , packet1.addr , packet1.length );\r\n\tmavlink_msg_flash_fw_read_block_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_read_block_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.addr , packet1.length );\r\n\tmavlink_msg_flash_fw_read_block_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_flash_fw_read_block_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_flash_fw_read_block_send(MAVLINK_COMM_1 , packet1.resp , packet1.addr , packet1.length );\r\n\tmavlink_msg_flash_fw_read_block_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_jump_to_fw(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n#ifdef MAVLINK_STATUS_FLAG_OUT_MAVLINK1\r\n\tmavlink_status_t *status = mavlink_get_channel_status(MAVLINK_COMM_0);\r\n        if ((status->flags & MAVLINK_STATUS_FLAG_OUT_MAVLINK1) && MAVLINK_MSG_ID_JUMP_TO_FW >= 256) {\r\n        \treturn;\r\n        }\r\n#endif\r\n\tmavlink_message_t msg;\r\n        uint8_t buffer[MAVLINK_MAX_PACKET_LEN];\r\n        uint16_t i;\r\n\tmavlink_jump_to_fw_t packet_in = {\r\n\t\t5,{ 72, 73, 74, 75, 76, 77, 78, 79 }\r\n    };\r\n\tmavlink_jump_to_fw_t packet1, packet2;\r\n        memset(&packet1, 0, sizeof(packet1));\r\n        packet1.resp = packet_in.resp;\r\n        \r\n        mav_array_memcpy(packet1.param, packet_in.param, sizeof(uint8_t)*8);\r\n        \r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_jump_to_fw_encode(system_id, component_id, &msg, &packet1);\r\n\tmavlink_msg_jump_to_fw_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_jump_to_fw_pack(system_id, component_id, &msg , packet1.resp , packet1.param );\r\n\tmavlink_msg_jump_to_fw_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_jump_to_fw_pack_chan(system_id, component_id, MAVLINK_COMM_0, &msg , packet1.resp , packet1.param );\r\n\tmavlink_msg_jump_to_fw_decode(&msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n\r\n        memset(&packet2, 0, sizeof(packet2));\r\n        mavlink_msg_to_send_buffer(buffer, &msg);\r\n        for (i=0; i<mavlink_msg_get_send_buffer_length(&msg); i++) {\r\n        \tcomm_send_ch(MAVLINK_COMM_0, buffer[i]);\r\n        }\r\n\tmavlink_msg_jump_to_fw_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n        \r\n        memset(&packet2, 0, sizeof(packet2));\r\n\tmavlink_msg_jump_to_fw_send(MAVLINK_COMM_1 , packet1.resp , packet1.param );\r\n\tmavlink_msg_jump_to_fw_decode(last_msg, &packet2);\r\n        MAVLINK_ASSERT(memcmp(&packet1, &packet2, sizeof(packet1)) == 0);\r\n}\r\n\r\nstatic void mavlink_test_opencr_msg(uint8_t system_id, uint8_t component_id, mavlink_message_t *last_msg)\r\n{\r\n\tmavlink_test_ack(system_id, component_id, last_msg);\r\n\tmavlink_test_read_version(system_id, component_id, last_msg);\r\n\tmavlink_test_read_board_name(system_id, component_id, last_msg);\r\n\tmavlink_test_read_tag(system_id, component_id, last_msg);\r\n\tmavlink_test_flash_fw_write_begin(system_id, component_id, last_msg);\r\n\tmavlink_test_flash_fw_write_end(system_id, component_id, last_msg);\r\n\tmavlink_test_flash_fw_write_packet(system_id, component_id, last_msg);\r\n\tmavlink_test_flash_fw_write_block(system_id, component_id, last_msg);\r\n\tmavlink_test_flash_fw_erase(system_id, component_id, last_msg);\r\n\tmavlink_test_flash_fw_verify(system_id, component_id, last_msg);\r\n\tmavlink_test_flash_fw_read_packet(system_id, component_id, last_msg);\r\n\tmavlink_test_flash_fw_read_block(system_id, component_id, last_msg);\r\n\tmavlink_test_jump_to_fw(system_id, component_id, last_msg);\r\n}\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif // __cplusplus\r\n#endif // OPENCR_MSG_TESTSUITE_H\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/msg/mavlink/opencr_msg/version.h",
    "content": "/** @file\r\n *\t@brief MAVLink comm protocol built from opencr_msg.xml\r\n *\t@see http://mavlink.org\r\n */\r\n#ifndef MAVLINK_VERSION_H\r\n#define MAVLINK_VERSION_H\r\n\r\n#define MAVLINK_BUILD_DATE \"Mon May 30 2016\"\r\n#define MAVLINK_WIRE_PROTOCOL_VERSION \"1.0\"\r\n#define MAVLINK_MAX_DIALECT_PAYLOAD_SIZE 134\r\n \r\n#endif // MAVLINK_VERSION_H\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/msg/mavlink/protocol.h",
    "content": "#ifndef  _MAVLINK_PROTOCOL_H_\r\n#define  _MAVLINK_PROTOCOL_H_\r\n\r\n#include \"string.h\"\r\n#include \"mavlink_types.h\"\r\n\r\n/* \r\n   If you want MAVLink on a system that is native big-endian,\r\n   you need to define NATIVE_BIG_ENDIAN\r\n*/\r\n#ifdef NATIVE_BIG_ENDIAN\r\n# define MAVLINK_NEED_BYTE_SWAP (MAVLINK_ENDIAN == MAVLINK_LITTLE_ENDIAN)\r\n#else\r\n# define MAVLINK_NEED_BYTE_SWAP (MAVLINK_ENDIAN != MAVLINK_LITTLE_ENDIAN)\r\n#endif\r\n\r\n#ifndef MAVLINK_STACK_BUFFER\r\n#define MAVLINK_STACK_BUFFER 0\r\n#endif\r\n\r\n#ifndef MAVLINK_AVOID_GCC_STACK_BUG\r\n# define MAVLINK_AVOID_GCC_STACK_BUG defined(__GNUC__)\r\n#endif\r\n\r\n#ifndef MAVLINK_ASSERT\r\n#define MAVLINK_ASSERT(x)\r\n#endif\r\n\r\n#ifndef MAVLINK_START_UART_SEND\r\n#define MAVLINK_START_UART_SEND(chan, length)\r\n#endif\r\n\r\n#ifndef MAVLINK_END_UART_SEND\r\n#define MAVLINK_END_UART_SEND(chan, length)\r\n#endif\r\n\r\n/* option to provide alternative implementation of mavlink_helpers.h */\r\n#ifdef MAVLINK_SEPARATE_HELPERS\r\n\r\n    #define MAVLINK_HELPER\r\n\r\n    /* decls in sync with those in mavlink_helpers.h */\r\n    #ifndef MAVLINK_GET_CHANNEL_STATUS\r\n    MAVLINK_HELPER mavlink_status_t* mavlink_get_channel_status(uint8_t chan);\r\n    #endif\r\n    MAVLINK_HELPER void mavlink_reset_channel_status(uint8_t chan);\r\n    #if MAVLINK_CRC_EXTRA\r\n    MAVLINK_HELPER uint16_t mavlink_finalize_message_chan(mavlink_message_t* msg, uint8_t system_id, uint8_t component_id,\r\n                                                          uint8_t chan, uint8_t min_length, uint8_t length, uint8_t crc_extra);\r\n    MAVLINK_HELPER uint16_t mavlink_finalize_message(mavlink_message_t* msg, uint8_t system_id, uint8_t component_id,\r\n                                                     uint8_t min_length, uint8_t length, uint8_t crc_extra);\r\n    #ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n    MAVLINK_HELPER void _mav_finalize_message_chan_send(mavlink_channel_t chan, uint8_t msgid, const char *packet,\r\n                                                        uint8_t min_length, uint8_t length, uint8_t crc_extra);\r\n    #endif\r\n    #else\r\n    MAVLINK_HELPER uint16_t mavlink_finalize_message_chan(mavlink_message_t* msg, uint8_t system_id, uint8_t component_id,\r\n                                                          uint8_t chan, uint8_t length);\r\n    MAVLINK_HELPER uint16_t mavlink_finalize_message(mavlink_message_t* msg, uint8_t system_id, uint8_t component_id,\r\n                                                     uint8_t length);\r\n    #ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n    MAVLINK_HELPER void _mav_finalize_message_chan_send(mavlink_channel_t chan, uint8_t msgid, const char *packet, uint8_t length);\r\n    #endif\r\n    #endif // MAVLINK_CRC_EXTRA\r\n    MAVLINK_HELPER uint16_t mavlink_msg_to_send_buffer(uint8_t *buffer, const mavlink_message_t *msg);\r\n    MAVLINK_HELPER void mavlink_start_checksum(mavlink_message_t* msg);\r\n    MAVLINK_HELPER void mavlink_update_checksum(mavlink_message_t* msg, uint8_t c);\r\n    MAVLINK_HELPER uint8_t mavlink_frame_char_buffer(mavlink_message_t* rxmsg, \r\n\t\t\t\t\t\t     mavlink_status_t* status,\r\n\t\t\t\t\t\t     uint8_t c, \r\n\t\t\t\t\t\t     mavlink_message_t* r_message, \r\n\t\t\t\t\t\t     mavlink_status_t* r_mavlink_status);\r\n    MAVLINK_HELPER uint8_t mavlink_frame_char(uint8_t chan, uint8_t c, mavlink_message_t* r_message, mavlink_status_t* r_mavlink_status);\r\n    MAVLINK_HELPER uint8_t mavlink_parse_char(uint8_t chan, uint8_t c, mavlink_message_t* r_message, mavlink_status_t* r_mavlink_status);\r\n    MAVLINK_HELPER uint8_t put_bitfield_n_by_index(int32_t b, uint8_t bits, uint8_t packet_index, uint8_t bit_index,\r\n                               uint8_t* r_bit_index, uint8_t* buffer);\r\n    #ifdef MAVLINK_USE_CONVENIENCE_FUNCTIONS\r\n    MAVLINK_HELPER void _mavlink_send_uart(mavlink_channel_t chan, const char *buf, uint16_t len);\r\n    MAVLINK_HELPER void _mavlink_resend_uart(mavlink_channel_t chan, const mavlink_message_t *msg);\r\n    #endif\r\n\r\n#else\r\n\r\n    #define MAVLINK_HELPER static inline\r\n    #include \"mavlink_helpers.h\"\r\n\r\n#endif // MAVLINK_SEPARATE_HELPERS\r\n\r\n/**\r\n * @brief Get the required buffer size for this message\r\n */\r\nstatic inline uint16_t mavlink_msg_get_send_buffer_length(const mavlink_message_t* msg)\r\n{\r\n\treturn msg->len + MAVLINK_NUM_NON_PAYLOAD_BYTES;\r\n}\r\n\r\n#if MAVLINK_NEED_BYTE_SWAP\r\nstatic inline void byte_swap_2(char *dst, const char *src)\r\n{\r\n\tdst[0] = src[1];\r\n\tdst[1] = src[0];\r\n}\r\nstatic inline void byte_swap_4(char *dst, const char *src)\r\n{\r\n\tdst[0] = src[3];\r\n\tdst[1] = src[2];\r\n\tdst[2] = src[1];\r\n\tdst[3] = src[0];\r\n}\r\nstatic inline void byte_swap_8(char *dst, const char *src)\r\n{\r\n\tdst[0] = src[7];\r\n\tdst[1] = src[6];\r\n\tdst[2] = src[5];\r\n\tdst[3] = src[4];\r\n\tdst[4] = src[3];\r\n\tdst[5] = src[2];\r\n\tdst[6] = src[1];\r\n\tdst[7] = src[0];\r\n}\r\n#elif !MAVLINK_ALIGNED_FIELDS\r\nstatic inline void byte_copy_2(char *dst, const char *src)\r\n{\r\n\tdst[0] = src[0];\r\n\tdst[1] = src[1];\r\n}\r\nstatic inline void byte_copy_4(char *dst, const char *src)\r\n{\r\n\tdst[0] = src[0];\r\n\tdst[1] = src[1];\r\n\tdst[2] = src[2];\r\n\tdst[3] = src[3];\r\n}\r\nstatic inline void byte_copy_8(char *dst, const char *src)\r\n{\r\n\tmemcpy(dst, src, 8);\r\n}\r\n#endif\r\n\r\n#define _mav_put_uint8_t(buf, wire_offset, b) buf[wire_offset] = (uint8_t)b\r\n#define _mav_put_int8_t(buf, wire_offset, b)  buf[wire_offset] = (int8_t)b\r\n#define _mav_put_char(buf, wire_offset, b)    buf[wire_offset] = b\r\n\r\n#if MAVLINK_NEED_BYTE_SWAP\r\n#define _mav_put_uint16_t(buf, wire_offset, b) byte_swap_2(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_int16_t(buf, wire_offset, b)  byte_swap_2(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_uint32_t(buf, wire_offset, b) byte_swap_4(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_int32_t(buf, wire_offset, b)  byte_swap_4(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_uint64_t(buf, wire_offset, b) byte_swap_8(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_int64_t(buf, wire_offset, b)  byte_swap_8(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_float(buf, wire_offset, b)    byte_swap_4(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_double(buf, wire_offset, b)   byte_swap_8(&buf[wire_offset], (const char *)&b)\r\n#elif !MAVLINK_ALIGNED_FIELDS\r\n#define _mav_put_uint16_t(buf, wire_offset, b) byte_copy_2(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_int16_t(buf, wire_offset, b)  byte_copy_2(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_uint32_t(buf, wire_offset, b) byte_copy_4(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_int32_t(buf, wire_offset, b)  byte_copy_4(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_uint64_t(buf, wire_offset, b) byte_copy_8(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_int64_t(buf, wire_offset, b)  byte_copy_8(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_float(buf, wire_offset, b)    byte_copy_4(&buf[wire_offset], (const char *)&b)\r\n#define _mav_put_double(buf, wire_offset, b)   byte_copy_8(&buf[wire_offset], (const char *)&b)\r\n#else\r\n#define _mav_put_uint16_t(buf, wire_offset, b) *(uint16_t *)&buf[wire_offset] = b\r\n#define _mav_put_int16_t(buf, wire_offset, b)  *(int16_t *)&buf[wire_offset] = b\r\n#define _mav_put_uint32_t(buf, wire_offset, b) *(uint32_t *)&buf[wire_offset] = b\r\n#define _mav_put_int32_t(buf, wire_offset, b)  *(int32_t *)&buf[wire_offset] = b\r\n#define _mav_put_uint64_t(buf, wire_offset, b) *(uint64_t *)&buf[wire_offset] = b\r\n#define _mav_put_int64_t(buf, wire_offset, b)  *(int64_t *)&buf[wire_offset] = b\r\n#define _mav_put_float(buf, wire_offset, b)    *(float *)&buf[wire_offset] = b\r\n#define _mav_put_double(buf, wire_offset, b)   *(double *)&buf[wire_offset] = b\r\n#endif\r\n\r\n/*\r\n  like memcpy(), but if src is NULL, do a memset to zero\r\n*/\r\nstatic inline void mav_array_memcpy(void *dest, const void *src, size_t n)\r\n{\r\n\tif (src == NULL) {\r\n\t\tmemset(dest, 0, n);\r\n\t} else {\r\n\t\tmemcpy(dest, src, n);\r\n\t}\r\n}\r\n\r\n/*\r\n * Place a char array into a buffer\r\n */\r\nstatic inline void _mav_put_char_array(char *buf, uint8_t wire_offset, const char *b, uint8_t array_length)\r\n{\r\n\tmav_array_memcpy(&buf[wire_offset], b, array_length);\r\n\r\n}\r\n\r\n/*\r\n * Place a uint8_t array into a buffer\r\n */\r\nstatic inline void _mav_put_uint8_t_array(char *buf, uint8_t wire_offset, const uint8_t *b, uint8_t array_length)\r\n{\r\n\tmav_array_memcpy(&buf[wire_offset], b, array_length);\r\n\r\n}\r\n\r\n/*\r\n * Place a int8_t array into a buffer\r\n */\r\nstatic inline void _mav_put_int8_t_array(char *buf, uint8_t wire_offset, const int8_t *b, uint8_t array_length)\r\n{\r\n\tmav_array_memcpy(&buf[wire_offset], b, array_length);\r\n\r\n}\r\n\r\n#if MAVLINK_NEED_BYTE_SWAP\r\n#define _MAV_PUT_ARRAY(TYPE, V) \\\r\nstatic inline void _mav_put_ ## TYPE ##_array(char *buf, uint8_t wire_offset, const TYPE *b, uint8_t array_length) \\\r\n{ \\\r\n\tif (b == NULL) { \\\r\n\t\tmemset(&buf[wire_offset], 0, array_length*sizeof(TYPE)); \\\r\n\t} else { \\\r\n\t\tuint16_t i; \\\r\n\t\tfor (i=0; i<array_length; i++) { \\\r\n\t\t\t_mav_put_## TYPE (buf, wire_offset+(i*sizeof(TYPE)), b[i]); \\\r\n\t\t} \\\r\n\t} \\\r\n}\r\n#else\r\n#define _MAV_PUT_ARRAY(TYPE, V)\t\t\t\t\t\\\r\nstatic inline void _mav_put_ ## TYPE ##_array(char *buf, uint8_t wire_offset, const TYPE *b, uint8_t array_length) \\\r\n{ \\\r\n\tmav_array_memcpy(&buf[wire_offset], b, array_length*sizeof(TYPE)); \\\r\n}\r\n#endif\r\n\r\n_MAV_PUT_ARRAY(uint16_t, u16)\r\n_MAV_PUT_ARRAY(uint32_t, u32)\r\n_MAV_PUT_ARRAY(uint64_t, u64)\r\n_MAV_PUT_ARRAY(int16_t,  i16)\r\n_MAV_PUT_ARRAY(int32_t,  i32)\r\n_MAV_PUT_ARRAY(int64_t,  i64)\r\n_MAV_PUT_ARRAY(float,    f)\r\n_MAV_PUT_ARRAY(double,   d)\r\n\r\n#define _MAV_RETURN_char(msg, wire_offset)             (const char)_MAV_PAYLOAD(msg)[wire_offset]\r\n#define _MAV_RETURN_int8_t(msg, wire_offset)   (const int8_t)_MAV_PAYLOAD(msg)[wire_offset]\r\n#define _MAV_RETURN_uint8_t(msg, wire_offset) (const uint8_t)_MAV_PAYLOAD(msg)[wire_offset]\r\n\r\n#if MAVLINK_NEED_BYTE_SWAP\r\n#define _MAV_MSG_RETURN_TYPE(TYPE, SIZE) \\\r\nstatic inline TYPE _MAV_RETURN_## TYPE(const mavlink_message_t *msg, uint8_t ofs) \\\r\n{ TYPE r; byte_swap_## SIZE((char*)&r, &_MAV_PAYLOAD(msg)[ofs]); return r; }\r\n\r\n_MAV_MSG_RETURN_TYPE(uint16_t, 2)\r\n_MAV_MSG_RETURN_TYPE(int16_t,  2)\r\n_MAV_MSG_RETURN_TYPE(uint32_t, 4)\r\n_MAV_MSG_RETURN_TYPE(int32_t,  4)\r\n_MAV_MSG_RETURN_TYPE(uint64_t, 8)\r\n_MAV_MSG_RETURN_TYPE(int64_t,  8)\r\n_MAV_MSG_RETURN_TYPE(float,    4)\r\n_MAV_MSG_RETURN_TYPE(double,   8)\r\n\r\n#elif !MAVLINK_ALIGNED_FIELDS\r\n#define _MAV_MSG_RETURN_TYPE(TYPE, SIZE) \\\r\nstatic inline TYPE _MAV_RETURN_## TYPE(const mavlink_message_t *msg, uint8_t ofs) \\\r\n{ TYPE r; byte_copy_## SIZE((char*)&r, &_MAV_PAYLOAD(msg)[ofs]); return r; }\r\n\r\n_MAV_MSG_RETURN_TYPE(uint16_t, 2)\r\n_MAV_MSG_RETURN_TYPE(int16_t,  2)\r\n_MAV_MSG_RETURN_TYPE(uint32_t, 4)\r\n_MAV_MSG_RETURN_TYPE(int32_t,  4)\r\n_MAV_MSG_RETURN_TYPE(uint64_t, 8)\r\n_MAV_MSG_RETURN_TYPE(int64_t,  8)\r\n_MAV_MSG_RETURN_TYPE(float,    4)\r\n_MAV_MSG_RETURN_TYPE(double,   8)\r\n#else // nicely aligned, no swap\r\n#define _MAV_MSG_RETURN_TYPE(TYPE) \\\r\nstatic inline TYPE _MAV_RETURN_## TYPE(const mavlink_message_t *msg, uint8_t ofs) \\\r\n{ return *(const TYPE *)(&_MAV_PAYLOAD(msg)[ofs]);}\r\n\r\n_MAV_MSG_RETURN_TYPE(uint16_t)\r\n_MAV_MSG_RETURN_TYPE(int16_t)\r\n_MAV_MSG_RETURN_TYPE(uint32_t)\r\n_MAV_MSG_RETURN_TYPE(int32_t)\r\n_MAV_MSG_RETURN_TYPE(uint64_t)\r\n_MAV_MSG_RETURN_TYPE(int64_t)\r\n_MAV_MSG_RETURN_TYPE(float)\r\n_MAV_MSG_RETURN_TYPE(double)\r\n#endif // MAVLINK_NEED_BYTE_SWAP\r\n\r\nstatic inline uint16_t _MAV_RETURN_char_array(const mavlink_message_t *msg, char *value, \r\n\t\t\t\t\t\t     uint8_t array_length, uint8_t wire_offset)\r\n{\r\n\tmemcpy(value, &_MAV_PAYLOAD(msg)[wire_offset], array_length);\r\n\treturn array_length;\r\n}\r\n\r\nstatic inline uint16_t _MAV_RETURN_uint8_t_array(const mavlink_message_t *msg, uint8_t *value, \r\n\t\t\t\t\t\t\tuint8_t array_length, uint8_t wire_offset)\r\n{\r\n\tmemcpy(value, &_MAV_PAYLOAD(msg)[wire_offset], array_length);\r\n\treturn array_length;\r\n}\r\n\r\nstatic inline uint16_t _MAV_RETURN_int8_t_array(const mavlink_message_t *msg, int8_t *value, \r\n\t\t\t\t\t\t       uint8_t array_length, uint8_t wire_offset)\r\n{\r\n\tmemcpy(value, &_MAV_PAYLOAD(msg)[wire_offset], array_length);\r\n\treturn array_length;\r\n}\r\n\r\n#if MAVLINK_NEED_BYTE_SWAP\r\n#define _MAV_RETURN_ARRAY(TYPE, V) \\\r\nstatic inline uint16_t _MAV_RETURN_## TYPE ##_array(const mavlink_message_t *msg, TYPE *value, \\\r\n\t\t\t\t\t\t\t uint8_t array_length, uint8_t wire_offset) \\\r\n{ \\\r\n\tuint16_t i; \\\r\n\tfor (i=0; i<array_length; i++) { \\\r\n\t\tvalue[i] = _MAV_RETURN_## TYPE (msg, wire_offset+(i*sizeof(value[0]))); \\\r\n\t} \\\r\n\treturn array_length*sizeof(value[0]); \\\r\n}\r\n#else\r\n#define _MAV_RETURN_ARRAY(TYPE, V)\t\t\t\t\t\\\r\nstatic inline uint16_t _MAV_RETURN_## TYPE ##_array(const mavlink_message_t *msg, TYPE *value, \\\r\n\t\t\t\t\t\t\t uint8_t array_length, uint8_t wire_offset) \\\r\n{ \\\r\n\tmemcpy(value, &_MAV_PAYLOAD(msg)[wire_offset], array_length*sizeof(TYPE)); \\\r\n\treturn array_length*sizeof(TYPE); \\\r\n}\r\n#endif\r\n\r\n_MAV_RETURN_ARRAY(uint16_t, u16)\r\n_MAV_RETURN_ARRAY(uint32_t, u32)\r\n_MAV_RETURN_ARRAY(uint64_t, u64)\r\n_MAV_RETURN_ARRAY(int16_t,  i16)\r\n_MAV_RETURN_ARRAY(int32_t,  i32)\r\n_MAV_RETURN_ARRAY(int64_t,  i64)\r\n_MAV_RETURN_ARRAY(float,    f)\r\n_MAV_RETURN_ARRAY(double,   d)\r\n\r\n#endif // _MAVLINK_PROTOCOL_H_\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/msg/msg.c",
    "content": "/*\n *  msg.c\n *\n *  message process\n *\n *  Created on: 2016. 5. 14.\n *      Author: Baram, PBPH\n */\n\n#include \"msg.h\"\n#include <math.h>\n#include <string.h>\n#include <stdarg.h>\n#include <stdio.h>\n#include \"../serial.h\"\n\n\nextern ser_handler stm32_ser_id;\nextern int read_byte( void );\nextern int write_bytes( char *p_data, int len );\n\n\n\nvoid msg_init(void)\n{\n\n}\n\n\nvoid msg_send(uint8_t chan, mavlink_message_t *p_msg)\n{\n  uint8_t  buf[1024];\n  uint16_t len;\n  uint16_t write_len;\n\n  len = mavlink_msg_to_send_buffer(buf, p_msg);\n\n  switch(chan)\n  {\n    case 0:\n      write_len = write_bytes((char *)buf, (uint32_t)len);\n#ifndef WIN32_BUILD\n      if( write_len != len ) printf(\"wlen %d : len %d\\r\\n\", write_len, len);\n#endif\n      break;\n\n    case 1:\n      break;\n  }\n}\n\n\nBOOL msg_recv( uint8_t chan, uint8_t data , mavlink_message_t *p_msg, mavlink_status_t *p_status )\n{\n  BOOL ret = FALSE;\n\n\n  if(chan == 0)\n  {\n    if (mavlink_parse_char(MAVLINK_COMM_0, data, p_msg, p_status) == MAVLINK_FRAMING_OK)\n    {\n      ret = TRUE;\n    }\n  }\n  else\n  {\n    if (mavlink_parse_char(MAVLINK_COMM_1, data, p_msg, p_status) == MAVLINK_FRAMING_OK)\n    {\n      ret = TRUE;\n    }\n  }\n\n  return ret;\n}\n\n\nBOOL msg_get_resp( uint8_t chan, mavlink_message_t *p_msg, uint32_t timeout)\n{\n  BOOL ret = FALSE;\n  //int  ch_ret;\n  int  length;\n  int  i;\n  uint8_t ch_buff[128];\n  uint8_t ch;\n  static mavlink_message_t msg[MSG_CH_MAX];\n  static mavlink_status_t status[MSG_CH_MAX];\n  int retry = timeout;\n\n\n#ifndef WIN32_BUILD\n  retry = timeout/100;\n  ser_set_timeout_ms( stm32_ser_id, 100 );\n  while(1)\n  {\n    length = read_bytes( ch_buff, 128 );\n\n    if( length <= 0 )\n    {\n      if( retry-- <= 0 )\n      {\n        ret = FALSE;\n        break;\n      }\n      else\n      {\n        continue;\n      }\n    }\n\n    for( i=0; i<length; i++ )\n    {\n      ch = ch_buff[i];\n      ret = msg_recv( chan, ch, &msg[chan], &status[chan] );\n\n      if( ret == TRUE )\n      {\n        *p_msg = msg[chan];\n        return ret;\n      }\n    }\n  }\n#else\n  int  ch_ret;\n  ser_set_timeout_ms( stm32_ser_id, 1 );\n\n  while(1)\n  {\n    ch_ret = read_byte();\n    if( ch_ret < 0 )\n    {\n      if( retry-- <= 0 )\n      {\n        ret = FALSE;\n        break;\n      }\n      else\n      {\n        continue;\n      }\n    }\n    else\n    {\n      ch = (uint8_t)(ch_ret);\n      retry = timeout;\n    }\n\n    ret = msg_recv( chan, ch, &msg[chan], &status[chan] );\n\n    if( ret == TRUE )\n    {\n      *p_msg = msg[chan];\n      break;\n    }\n  }\n#endif\n\n  return ret;\n}\n\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/msg/msg.h",
    "content": "/*\n *  msg.h\n *\n *  message process\n *\n *  Created on: 2016. 5. 14.\n *      Author: Baram, PBPH\n */\n\n#ifndef MSG_H\n#define MSG_H\n\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n\n#include \"def.h\"\n\n\n\n#define MSG_CH_MAX\t1\n\n\ntypedef struct\n{\n  uint8_t ch;\n  mavlink_message_t *p_msg;\n} msg_t;\n\n\n\nvoid msg_init(void);\nvoid msg_send(uint8_t chan, mavlink_message_t *p_msg);\nBOOL msg_recv( uint8_t chan, uint8_t data , mavlink_message_t *p_msg, mavlink_status_t *p_status );\nBOOL msg_get_resp( uint8_t chan, mavlink_message_t *p_msg, uint32_t timeout);\n\n\n#ifdef __cplusplus\n}\n#endif\n\n\n#endif\n\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/msg/xml/opencr_msg",
    "content": "<?xml version=\"1.0\"?>\r\n<mavlink>\r\n        <!--<include>common.xml</include>-->\r\n        <!-- NOTE: If the included file already contains a version tag, remove the version tag here, else uncomment to enable. -->\r\n\t<!--<version>3</version>-->\r\n\t<enums>\r\n\t</enums>\r\n\t\r\n\t<messages>\r\n\t\t<message id=\"150\" name=\"ACK\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"    name=\"msg_id\"></field>\r\n\t\t\t<field type=\"uint16_t\"   name=\"err_code\"></field>\r\n\t\t\t<field type=\"uint8_t\"    name=\"length\"></field>\r\n\t\t\t<field type=\"uint8_t[16]\" name=\"data\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\t\r\n\t<messages>\r\n\t\t<message id=\"151\" name=\"READ_VERSION\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"    name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint8_t[8]\" name=\"param\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\r\n\t<messages>\r\n\t\t<message id=\"152\" name=\"READ_BOARD_NAME\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"    name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint8_t[8]\" name=\"param\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\r\n\t<messages>\r\n\t\t<message id=\"153\" name=\"READ_TAG\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"    name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint8_t\"    name=\"type\"></field>\r\n\t\t\t<field type=\"uint8_t[8]\" name=\"param\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\r\n\t<messages>\r\n\t\t<message id=\"154\" name=\"FLASH_FW_WRITE_BEGIN\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"    name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint8_t[8]\" name=\"param\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\t\r\n\t<messages>\r\n\t\t<message id=\"155\" name=\"FLASH_FW_WRITE_END\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"    name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint8_t[8]\" name=\"param\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\r\n\t<messages>\r\n\t\t<message id=\"156\" name=\"FLASH_FW_WRITE_PACKET\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"  name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint16_t\" name=\"addr\"></field>\r\n\t\t\t<field type=\"uint8_t\"  name=\"length\"></field>\r\n\t\t\t<field type=\"uint8_t[128]\" name=\"data\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\r\n\t<messages>\r\n\t\t<message id=\"157\" name=\"FLASH_FW_WRITE_BLOCK\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"  name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint32_t\" name=\"addr\"></field>\r\n\t\t\t<field type=\"uint16_t\" name=\"length\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\t\r\n\t<messages>\r\n\t\t<message id=\"158\" name=\"FLASH_FW_ERASE\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"    name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint32_t\"   name=\"length\"></field>\r\n\t\t\t<field type=\"uint8_t[8]\" name=\"param\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\t\r\n\t<messages>\r\n\t\t<message id=\"159\" name=\"FLASH_FW_VERIFY\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"    name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint32_t\"   name=\"length\"></field>\r\n\t\t\t<field type=\"uint32_t\"   name=\"crc\"></field>\r\n\t\t\t<field type=\"uint8_t[8]\" name=\"param\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\r\n\t<messages>\r\n\t\t<message id=\"160\" name=\"FLASH_FW_READ_PACKET\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"  name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint32_t\" name=\"addr\"></field>\r\n\t\t\t<field type=\"uint8_t\"  name=\"length\"></field>\r\n\t\t\t<field type=\"uint8_t[128]\" name=\"data\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\r\n\t<messages>\r\n\t\t<message id=\"161\" name=\"FLASH_FW_READ_BLOCK\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"  name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint32_t\" name=\"addr\"></field>\r\n\t\t\t<field type=\"uint16_t\" name=\"length\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\t\r\n\t<messages>\r\n\t\t<message id=\"162\" name=\"JUMP_TO_FW\">\r\n\t\t\t<description></description>\r\n\t\t\t<field type=\"uint8_t\"    name=\"resp\">0:No Resp, 1:Resp</field>\r\n\t\t\t<field type=\"uint8_t[8]\" name=\"param\"></field>\r\n\t\t</message>\r\n\t</messages>\r\n\t\t\r\n</mavlink>"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/opencr_ld.c",
    "content": "#include \"opencr_ld.h\"\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <errno.h>\n#include <limits.h>\n#include <stdio.h>\n#include <stdarg.h>\n\n#include \"serial.h\"\n#include \"type.h\"\n#include \"./msg/msg.h\"\n#include <sys/time.h>\n#include <stdio.h>\n\n\n\nstatic FILE      *opencr_fp;\nstatic uint32_t   opencr_fpsize;\n\n\nser_handler stm32_ser_id = ( ser_handler )-1;\n\n\n#define GET_CALC_TIME(x)\t( (int)(x / 1000) + ((float)(x % 1000))/1000 )\n\n#define FLASH_TX_BLOCK_LENGTH\t(8*1024)\n#define FLASH_RX_BLOCK_LENGTH\t(128)\n#define FLASH_PACKET_LENGTH   \t128\n\n\nuint32_t tx_buf[768*1024/4];\nuint32_t rx_buf[768*1024/4];\n\nchar err_msg_str[512];\n\n\nint opencr_ld_down( int argc, const char **argv );\nint opencr_ld_jump_to_boot( char *portname );\nint opencr_ld_flash_write( uint32_t addr, uint8_t *p_data, uint32_t length  );\nint opencr_ld_flash_read( uint32_t addr, uint8_t *p_data, uint32_t length  );\nint opencr_ld_flash_erase( uint32_t length  );\n\nuint32_t opencr_ld_file_read_data( uint8_t *dst, uint32_t len );\n\nvoid opencr_ld_write_err_msg( const char *fmt, ...);\nvoid opencr_ld_print_err_msg(void);\n\nstatic long iclock();\nint read_byte( void );\nint write_bytes( char *p_data, int len );\nvoid delay_ms( int WaitTime );\nuint32_t crc_calc( uint32_t crc_in, uint8_t data_in );\n\n\nerr_code_t cmd_read_version( uint32_t *p_version, uint32_t *p_revision );\nerr_code_t cmd_read_board_name( uint8_t *p_str, uint8_t *p_len );\nerr_code_t cmd_flash_fw_erase( uint32_t length );\nerr_code_t cmd_flash_fw_write_begin( void );\nerr_code_t cmd_flash_fw_write_end( void );\nerr_code_t cmd_flash_fw_write_packet( uint16_t addr, uint8_t *p_data, uint8_t length );\nerr_code_t cmd_flash_fw_write_block( uint32_t addr, uint32_t length  );\nerr_code_t cmd_flash_fw_send_block_multi( uint8_t block_count );\nerr_code_t cmd_flash_fw_read_block( uint32_t addr, uint8_t *p_data, uint16_t length );\nerr_code_t cmd_flash_fw_verify( uint32_t length, uint32_t crc, uint32_t *p_crc_ret );\nerr_code_t cmd_jump_to_fw(void);\n\n\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : opencr_ld_main\n     WORK    :\n---------------------------------------------------------------------------*/\nint opencr_ld_main( int argc, const char **argv )\n{\n  long baud;\n  int ret;\n  baud = strtol( argv[ 2 ], NULL, 10 );\n\n  printf(\"opencr_ld_main \\r\\n\");\n\n  int retry = 3;\n  while(retry--)\n  {\n  \tret = opencr_ld_down( argc, argv );\n    if (ret == 0)\n\t{\n      break;\n\t}\n  }\n\n  return 0;\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : opencr_ld_down\n     WORK    :\n---------------------------------------------------------------------------*/\nint opencr_ld_down( int argc, const char **argv )\n{\n  int i;\n  int j;\n  int ret = 0;\n  err_code_t err_code = OK;\n  long t, dt;\n  float calc_time;\n  uint32_t fw_size = 256*1024*3;\n  uint8_t  board_str[16];\n  uint8_t  board_str_len;\n  uint32_t board_version;\n  uint32_t board_revision;\n  uint32_t crc;\n  uint32_t crc_ret = 0;\n  uint8_t  *p_buf_crc;\n  char *portname;\n  uint32_t baud;\n  uint8_t  block_buf[FLASH_TX_BLOCK_LENGTH];\n  uint32_t addr;\n  uint32_t len;\n  uint8_t jump_to_fw = 0;\n  uint8_t retry;\n  opencr_fw_header_t fw_header;\n\n\n  baud     = strtol( argv[ 2 ], NULL, 10 );\n  portname = (char *)argv[ 1 ];\n\n  if( argc >= 5 && strlen(argv[ 4 ])==1 && strncmp(argv[ 4 ], \"1\", 1)==0 )\n  {\n    jump_to_fw = 1;\n  }\n\n  if( ( opencr_fp = fopen( argv[ 3 ], \"rb\" ) ) == NULL )\n  {\n    fprintf( stderr, \"[NG] Unable to open %s\\n\", argv[ 3 ] );\n    exit( 1 );\n  }\n  else\n  {\n    fseek( opencr_fp, 0, SEEK_END );\n    opencr_fpsize = ftell( opencr_fp );\n    fseek( opencr_fp, 0, SEEK_SET );\n\n    printf(\"[  ] file name   \\t: %s \\r\\n\", argv[3]);\n    printf(\"[  ] file size   \\t: %d KB\\r\\n\", opencr_fpsize/1024);\n  }\n\n  fread(&fw_header, 1, sizeof(opencr_fw_header_t), opencr_fp);\n\n  if (fw_header.magic_number == MAGIC_NUMBER)\n  {\n    printf(\"[  ] fw_name     \\t: %s \\n\", fw_header.fw_name_str);\n    printf(\"[  ] fw_ver      \\t: %s \\n\", fw_header.fw_ver_str);\n  }\n  else\n  {\n    printf(\"[NG] not opencr fw \\n\");\n    fclose(opencr_fp);\n    return -1;\n  }\n\n  fw_size = opencr_fpsize - sizeof(opencr_fw_header_t);\n\n\n  // Jump To Boot\n  if( opencr_ld_jump_to_boot(portname ) < 0 )\n  {\n    printf(\"[NG] Fail to jump to boot\\n\");\n    return -1;\n  }\n\n\n  // Open port\n  if( ( stm32_ser_id = ser_open( portname ) ) == ( ser_handler )-1 )\n  {\n    printf(\"[NG] Fail to open port 1\\n\");\n    return -1;\n  }\n  else\n  {\n    printf(\"[OK] Open port   \\t: %s\\n\", portname);\n    printf(\"[  ]\\n\");\n  }\n\n  // Setup port\n  ser_setupEx( stm32_ser_id, 115200, SER_DATABITS_8, SER_PARITY_NONE, SER_STOPBITS_1, 1 );\n\n  ser_set_timeout_ms( stm32_ser_id, SER_NO_TIMEOUT );\n  while( read_byte() != -1 );\n  ser_set_timeout_ms( stm32_ser_id, 1000 );\n\n\n  err_code = cmd_read_board_name( board_str, &board_str_len );\n  if( err_code == OK )\n  {\n    printf(\"[  ] Board Name  \\t: %s\\r\\n\", board_str);\n  }\n  else\n  {\n    printf(\"[NG] cmd_read_board_name fail : 0x%X\\n\", err_code);\n    ser_close( stm32_ser_id );\n    fclose( opencr_fp );\n    return -1;\n  }\n  err_code = cmd_read_version( &board_version, &board_revision );\n  if( err_code == OK )\n  {\n    printf(\"[  ] Board Ver   \\t: 0x%08X\\r\\n\", board_version);\n    printf(\"[  ] Board Rev   \\t: 0x%08X\\r\\n\", board_revision);\n  }\n\n  t = iclock();\n  ret = opencr_ld_flash_erase(fw_size);\n  dt = iclock() - t;\n  if( ret < 0 )\n  {\n    printf(\"[NG] flash_erase \\t: %d(%1.2f sec)\\r\\n\", ret, GET_CALC_TIME(dt));\n    ser_close( stm32_ser_id );\n    fclose( opencr_fp );\n    return -1;\n  }\n  printf(\"[OK] flash_erase \\t: %1.2fs\\r\\n\", GET_CALC_TIME(dt));\n\n\n  t = iclock();\n  crc  = 0;\n  addr = 0;\n  while(1)\n  {\n    len = opencr_ld_file_read_data( block_buf, FLASH_TX_BLOCK_LENGTH);\n    if( len == 0 ) break;\n\n    for( i=0; i<len; i++ )\n    {\n      crc = crc_calc( crc,  block_buf[i] );\n    }\n\n    for( retry=0; retry<3; retry++ )\n    {\n      ret = opencr_ld_flash_write( addr, block_buf, len );\n      if( ret >= 0 ) break;\n    }\n    if( ret < 0 ) break;\n\n    addr += len;\n  }\n  dt = iclock() - t;\n\n\n  if( ret < 0 )\n  {\n    ser_close( stm32_ser_id );\n    fclose( opencr_fp );\n    opencr_ld_print_err_msg();\n    printf(\"[NG] flag_write  \\t: %d\\n\", ret);\n    return -2;\n  }\n  printf(\"[OK] flash_write \\t: %1.2fs \\r\\n\", GET_CALC_TIME(dt));\n\n\n\n  for (int i=0; i<3; i++)\n  {\n    t = iclock();\n    err_code = cmd_flash_fw_verify( fw_size, crc, &crc_ret );\n    dt = iclock() - t;\n    if( err_code == OK )\n    {\n      break;\n    }\n  }\n\n  if( err_code == OK )\n  {\n    printf(\"[OK] CRC Check   \\t: %X %X , %f sec\\r\\n\", crc, crc_ret, GET_CALC_TIME(dt));\n  }\n  else\n  {\n    printf(\"[NG] CRC Check   \\t: 0x%X : %X, %X %f sec\\r\\n\", err_code, crc, crc_ret, GET_CALC_TIME(dt));\n    printf(\"[NG] Download \\r\\n\");\n    ser_close( stm32_ser_id );\n    fclose( opencr_fp );\n    return -3;\n  }\n  \n  printf(\"[OK] Download \\r\\n\");\n\n  if( jump_to_fw == 1 )\n  {\n    printf(\"[OK] jump_to_fw \\r\\n\");\n    cmd_jump_to_fw();\n  }\n\n  ser_close( stm32_ser_id );\n  fclose( opencr_fp );\n\n  return 0;\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : opencr_ld_file_read_data\n     WORK    :\n---------------------------------------------------------------------------*/\nint opencr_ld_jump_to_boot( char *portname )\n{\n  bool ret;\n\n\n  // Open port\n  if( ( stm32_ser_id = ser_open( portname ) ) == ( ser_handler )-1 )\n  {\n    printf(\"Fail to open port 1 : %s\\n\", portname);\n    return -1;\n  }\n\n  // Setup port\n  ser_setupEx( stm32_ser_id, 1200, SER_DATABITS_8, SER_PARITY_NONE, SER_STOPBITS_1, 1 );\n\n  write_bytes(\"OpenCR 5555AAAA\", 15);\n  ser_close( stm32_ser_id );\n\n  delay_ms(3000);\n\n  return 0;\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : opencr_ld_file_read_data\n     WORK    :\n---------------------------------------------------------------------------*/\nuint32_t opencr_ld_file_read_data( uint8_t *dst, uint32_t len )\n{\n  size_t readbytes = 0;\n\n  if( !feof( opencr_fp ) )\n  {\n    readbytes = fread( dst, 1, len, opencr_fp );\n  }\n  return ( uint32_t )readbytes;\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : opencr_ld_flash_write\n     WORK    :\n---------------------------------------------------------------------------*/\nint opencr_ld_flash_write( uint32_t addr, uint8_t *p_data, uint32_t length  )\n{\n  int ret = 0;\n  err_code_t err_code = OK;\n  uint32_t block_length;\n  uint16_t block_cnt;\n  uint32_t written_packet_length;\n  uint32_t written_total_length;\n  uint32_t packet_length = 128;\n  uint32_t i;\n\n\n  err_code = cmd_flash_fw_write_begin();\n  if( err_code != OK )\n  {\n    opencr_ld_write_err_msg(\"cmd_flash_fw_write_begin ERR : 0x%04X\\r\\n\", err_code);\n\n    return -1;\n  }\n\n  written_total_length = 0;\n\n  while(1)\n  {\n    block_length = length - written_total_length;\n\n    if( block_length > FLASH_TX_BLOCK_LENGTH )\n    {\n      block_length = FLASH_TX_BLOCK_LENGTH;\n    }\n\n    block_cnt = block_length/FLASH_PACKET_LENGTH;\n    if( block_length%FLASH_PACKET_LENGTH > 0 )\n    {\n      block_cnt += 1;\n    }\n\n\n    written_packet_length = 0;\n    for( i=0; i<block_cnt; i++ )\n    {\n      packet_length = block_length - written_packet_length;\n      if( packet_length > FLASH_PACKET_LENGTH )\n      {\n        packet_length = FLASH_PACKET_LENGTH;\n      }\n\n      err_code = cmd_flash_fw_write_packet(written_packet_length, &p_data[written_total_length+written_packet_length], packet_length);\n      if( err_code != OK )\n      {\n        opencr_ld_write_err_msg(\"cmd_flash_fw_send_block ERR : 0x%04X\\r\\n\", err_code);\n        return -2;\n      }\n\n      written_packet_length += packet_length;\n    }\n\n    //printf(\"%d : %d, %d, %d \\r\\n\", written_packet_length, block_length, block_cnt, packet_length);\n\n    if( written_packet_length == block_length )\n    {\n      err_code = cmd_flash_fw_write_block(addr+written_total_length, block_length);\n      if( err_code != OK )\n      {\n        opencr_ld_write_err_msg(\"cmd_flash_fw_write_block ERR : 0x%04X\\r\\n\", err_code);\n        return -3;\n      }\n    }\n    else\n    {\n      opencr_ld_write_err_msg(\"written_packet_length : %d, %d 0x%04X\\r\\n\", written_packet_length, block_length, err_code);\n      return -4;\n    }\n\n    written_total_length += block_length;\n\n    if( written_total_length == length )\n    {\n      break;\n    }\n    else if( written_total_length > length )\n    {\n      opencr_ld_write_err_msg(\"written_total_length over \\r\\n\");\n      return -5;\n    }\n  }\n\n\n  cmd_flash_fw_write_end();\n\n  return ret;\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : opencr_ld_flash_read\n     WORK    :\n---------------------------------------------------------------------------*/\nint opencr_ld_flash_read( uint32_t addr, uint8_t *p_data, uint32_t length  )\n{\n  int ret = 0;\n  err_code_t err_code = OK;\n  uint32_t block_length;\n  uint32_t read_packet_length;\n  uint32_t read_total_length;\n  int i;\n  int err_count = 0;\n\n  read_total_length = 0;\n\n  while(1)\n  {\n    block_length = length - read_total_length;\n\n    if( block_length > FLASH_PACKET_LENGTH )\n    {\n      block_length = FLASH_PACKET_LENGTH;\n    }\n\n\n    for( i=0; i<3; i++ )\n    {\n      err_code = cmd_flash_fw_read_block( addr+read_total_length, &p_data[read_total_length], block_length );\n      if( err_code == OK ) break;\n      err_count++;\n    }\n\n\n    if( err_code != OK )\n    {\n      printf(\"cmd_flash_fw_read_block : addr:%X, 0x%04X \\r\\n\", addr+read_total_length, err_code);\n      return -1;\n    }\n\n    read_total_length += block_length;\n\n    if( read_total_length == length )\n    {\n      break;\n    }\n    else if( read_total_length > length )\n    {\n      printf(\"read_total_length over \\r\\n\");\n      return -2;\n    }\n  }\n\n  return ret;\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : opencr_ld_flash_erase\n     WORK    :\n---------------------------------------------------------------------------*/\nint opencr_ld_flash_erase( uint32_t length  )\n{\n  int ret = 0;\n  err_code_t err_code = OK;\n\n  err_code = cmd_flash_fw_erase( length );\n\n  if( err_code != OK )\n  {\n    printf(\"cmd_flash_fw_erase_block : 0x%04X %d\\r\\n\", err_code, length );\n    return -1;\n  }\n\n  return ret;\n}\n\n\n\nstatic long iclock()\n{\n\tstruct timeval tv;\n\tgettimeofday (&tv, NULL);\n\treturn (tv.tv_sec * 1000 + tv.tv_usec / 1000);\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : delay_ms\n     WORK    :\n---------------------------------------------------------------------------*/\nvoid delay_ms( int WaitTime )\n{\n  int i;\n\n  #ifdef WIN32_BUILD\n  Sleep(WaitTime);\n  #else\n  for( i=0; i<WaitTime; i++ )\n  {\n    usleep(1000);\n  }\n  #endif\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : read_byte\n     WORK    :\n---------------------------------------------------------------------------*/\nint read_byte( void )\n{\n  return ser_read_byte( stm32_ser_id );\n}\n\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : read_bytes\n     WORK    :\n---------------------------------------------------------------------------*/\nint read_bytes( uint8_t *pData, uint32_t size )\n{\n  return read( stm32_ser_id, pData, size ); //ser_read( stm32_ser_id, pData, size );\n  //return ser_read( stm32_ser_id, pData, size );\n}\n\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : write_bytes\n     WORK    :\n---------------------------------------------------------------------------*/\nint write_bytes( char *p_data, int len )\n{\n  int written_len;\n\n  written_len = ser_write( stm32_ser_id, (const u8 *)p_data, len );\n\n  return written_len;\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : cmd_read_version\n     WORK    :\n---------------------------------------------------------------------------*/\nerr_code_t cmd_read_version( uint32_t *p_version, uint32_t *p_revision )\n{\n  err_code_t err_code = OK;\n  mavlink_message_t tx_msg;\n  mavlink_message_t rx_msg;\n  mavlink_ack_t     ack_msg;\n  uint8_t param[8];\n  uint8_t resp = 1;\n\n\n  mavlink_msg_read_version_pack(0, 0, &tx_msg, resp, param);\n  msg_send(0, &tx_msg);\n\n  if( resp == 1 )\n  {\n    if( msg_get_resp(0, &rx_msg, 500) == TRUE )\n    {\n      mavlink_msg_ack_decode( &rx_msg, &ack_msg);\n\n      //printf(\"BootVersion : 0x%08X\\r\\n\", ack_msg.data[3]<<24|ack_msg.data[2]<<16|ack_msg.data[1]<<8|ack_msg.data[0]);\n      *p_version  = ack_msg.data[3]<<24|ack_msg.data[2]<<16|ack_msg.data[1]<<8|ack_msg.data[0];\n      *p_revision = ack_msg.data[7]<<24|ack_msg.data[6]<<16|ack_msg.data[5]<<8|ack_msg.data[4];\n      if( tx_msg.msgid == ack_msg.msg_id ) err_code = ack_msg.err_code;\n      else                                 err_code = ERR_MISMATCH_ID;\n    }\n    else\n    {\n      err_code = ERR_TIMEOUT;\n    }\n  }\n\n  return OK;\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : cmd_read_board_name\n     WORK    :\n---------------------------------------------------------------------------*/\nerr_code_t cmd_read_board_name( uint8_t *p_str, uint8_t *p_len )\n{\n  err_code_t err_code = OK;\n  mavlink_message_t tx_msg;\n  mavlink_message_t rx_msg;\n  mavlink_ack_t     ack_msg;\n  uint8_t param[8];\n  uint8_t resp = 1;\n\n  mavlink_msg_read_board_name_pack(0, 0, &tx_msg, resp, param);\n  msg_send(0, &tx_msg);\n  if( resp == 1 )\n  {\n    if( msg_get_resp(0, &rx_msg, 500) == TRUE )\n    {\n      mavlink_msg_ack_decode( &rx_msg, &ack_msg);\n\n      *p_len = ack_msg.length;\n      memcpy(p_str, ack_msg.data, ack_msg.length);\n      p_str[ack_msg.length] = 0;\n\n      if( tx_msg.msgid == ack_msg.msg_id ) err_code = ack_msg.err_code;\n      else                                 err_code = ERR_MISMATCH_ID;\n    }\n    else\n    {\n      err_code = ERR_TIMEOUT;\n    }\n  }\n\n  return err_code;\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : cmd_flash_fw_erase\n     WORK    :\n---------------------------------------------------------------------------*/\nerr_code_t cmd_flash_fw_erase( uint32_t length )\n{\n  err_code_t err_code = OK;\n  mavlink_message_t tx_msg;\n  mavlink_message_t rx_msg;\n  mavlink_ack_t     ack_msg;\n  uint8_t param[8];\n  uint8_t resp = 1;\n\n\n  mavlink_msg_flash_fw_erase_pack(0, 0, &tx_msg, resp, length, param);\n  msg_send(0, &tx_msg);\n\n  if( resp == 1 )\n  {\n    if( msg_get_resp(0, &rx_msg, 3000) == TRUE )\n    {\n      mavlink_msg_ack_decode( &rx_msg, &ack_msg);\n\n      if( tx_msg.msgid == ack_msg.msg_id ) err_code = ack_msg.err_code;\n      else                                 err_code = ERR_MISMATCH_ID;\n    }\n    else\n    {\n      err_code = ERR_TIMEOUT;\n    }\n  }\n\n  return err_code;\n}\n\n/*---------------------------------------------------------------------------\n     TITLE   : cmd_flash_fw_write_begin\n     WORK    :\n---------------------------------------------------------------------------*/\nerr_code_t cmd_flash_fw_write_begin( void )\n{\n  err_code_t err_code = OK;\n  mavlink_message_t tx_msg;\n  mavlink_message_t rx_msg;\n  mavlink_ack_t     ack_msg;\n  uint8_t param[8];\n  uint8_t resp = 1;\n\n\n  mavlink_msg_flash_fw_write_begin_pack(0, 0, &tx_msg, resp, param);\n  msg_send(0, &tx_msg);\n\n  if( resp == 1 )\n  {\n    if( msg_get_resp(0, &rx_msg, 5000) == TRUE )\n    {\n      mavlink_msg_ack_decode( &rx_msg, &ack_msg);\n\n      if( tx_msg.msgid == ack_msg.msg_id ) err_code = ack_msg.err_code;\n      else                                 err_code = ERR_MISMATCH_ID;\n    }\n    else\n    {\n      err_code = ERR_TIMEOUT;\n    }\n  }\n\n  return err_code;\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : cmd_flash_fw_write_end\n     WORK    :\n---------------------------------------------------------------------------*/\nerr_code_t cmd_flash_fw_write_end( void )\n{\n  err_code_t err_code = OK;\n  mavlink_message_t tx_msg;\n  mavlink_message_t rx_msg;\n  mavlink_ack_t     ack_msg;\n  uint8_t param[8];\n  uint8_t resp = 1;\n\n\n  mavlink_msg_flash_fw_write_end_pack(0, 0, &tx_msg, resp, param);\n  msg_send(0, &tx_msg);\n\n  if( resp == 1 )\n  {\n    if( msg_get_resp(0, &rx_msg, 500) == TRUE )\n    {\n      mavlink_msg_ack_decode( &rx_msg, &ack_msg);\n\n      //printf(\"block_count  : %d\\r\\n\", ack_msg.data[1]<<8|ack_msg.data[0]);\n      //printf(\"block_length : %d\\r\\n\", ack_msg.data[5]<<24|ack_msg.data[4]<<16|ack_msg.data[3]<<8|ack_msg.data[2]);\n\n\n      if( tx_msg.msgid == ack_msg.msg_id ) err_code = ack_msg.err_code;\n      else                                 err_code = ERR_MISMATCH_ID;\n    }\n    else\n    {\n      err_code = ERR_TIMEOUT;\n    }\n  }\n\n  return err_code;\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : cmd_flash_fw_write_packet\n     WORK    :\n---------------------------------------------------------------------------*/\nerr_code_t cmd_flash_fw_write_packet( uint16_t addr, uint8_t *p_data, uint8_t length )\n{\n  err_code_t err_code = OK;\n  mavlink_message_t tx_msg;\n  mavlink_message_t rx_msg;\n  mavlink_ack_t     ack_msg;\n  uint8_t resp = 0;\n\n\n\n  mavlink_msg_flash_fw_write_packet_pack(0, 0, &tx_msg, resp, addr, length, p_data);\n  msg_send(0, &tx_msg);\n\n\n  if( resp == 1 )\n  {\n    if( msg_get_resp(0, &rx_msg, 500) == TRUE )\n    {\n      mavlink_msg_ack_decode( &rx_msg, &ack_msg);\n\n      if( tx_msg.msgid == ack_msg.msg_id ) err_code = ack_msg.err_code;\n      else                                 err_code = ERR_MISMATCH_ID;\n    }\n    else\n    {\n      err_code = ERR_TIMEOUT;\n    }\n  }\n\n  return err_code;\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : cmd_flash_fw_send_block_multi\n     WORK    :\n---------------------------------------------------------------------------*/\nerr_code_t cmd_flash_fw_send_block_multi( uint8_t block_count )\n{\n  err_code_t err_code = OK;\n  mavlink_message_t tx_msg;\n  mavlink_message_t rx_msg;\n  mavlink_ack_t     ack_msg;\n  uint8_t buf[256];\n  uint8_t tx_buf[16*1024];\n  uint8_t resp = 0;\n  uint8_t i;\n  uint32_t len;\n\n\n   len = 0;\n  for( i=0; i<block_count; i++ )\n  {\n    mavlink_msg_flash_fw_write_packet_pack(0, 0, &tx_msg, resp, 0, 128, buf);\n    len += mavlink_msg_to_send_buffer(&tx_buf[len], &tx_msg);\n  }\n  write_bytes((char *)tx_buf, len);\n\n  return err_code;\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : cmd_flash_fw_write_block\n     WORK    :\n---------------------------------------------------------------------------*/\nerr_code_t cmd_flash_fw_write_block( uint32_t addr, uint32_t length  )\n{\n  err_code_t err_code = OK;\n  mavlink_message_t tx_msg;\n  mavlink_message_t rx_msg;\n  mavlink_ack_t     ack_msg;\n  uint8_t buf[256];\n  uint8_t resp = 1;\n\n\n  mavlink_msg_flash_fw_write_block_pack(0, 0, &tx_msg, resp, addr, length);\n  msg_send(0, &tx_msg);\n\n\n  if( resp == 1 )\n  {\n    if( msg_get_resp(0, &rx_msg, 500) == TRUE )\n    {\n      mavlink_msg_ack_decode( &rx_msg, &ack_msg);\n\n      if( tx_msg.msgid == ack_msg.msg_id ) err_code = ack_msg.err_code;\n      else                                 err_code = ERR_MISMATCH_ID;\n    }\n    else\n    {\n      err_code = ERR_TIMEOUT;\n    }\n  }\n\n  return err_code;\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : cmd_flash_fw_read_block\n     WORK    :\n---------------------------------------------------------------------------*/\n#if 0\nerr_code_t cmd_flash_fw_read_block( uint32_t addr, uint8_t *p_data, uint16_t length )\n{\n  err_code_t err_code = OK;\n  mavlink_message_t tx_msg;\n  mavlink_message_t rx_msg;\n  mavlink_flash_fw_read_t  resp_msg;\n  uint8_t resp = 1;\n  uint16_t received_length;\n\n\n  mavlink_msg_flash_fw_read_block_pack(0, 0, &tx_msg, resp, addr, length);\n  msg_send(0, &tx_msg);\n\n\n\n  if( resp == 1 )\n  {\n    received_length = 0;\n\n    while(1)\n    {\n      if( msg_get_resp(0, &rx_msg, 3000) == TRUE )\n      {\n\tmavlink_msg_flash_fw_read_decode( &rx_msg, &resp_msg);\n\n\tmemcpy(&p_data[received_length], resp_msg.data, resp_msg.length);\n\treceived_length += resp_msg.length;\n\n\t//printf(\"recv %d \\r\\n\", received_length);\n\n\tif( received_length == length )\n\t{\n\t  break;\n\t}\n\telse if( received_length > length )\n\t{\n\t  err_code = ERR_SIZE_OVER;\n\t  break;\n\t}\n      }\n      else\n      {\n\terr_code = ERR_TIMEOUT;\n\tbreak;\n      }\n    }\n  }\n\n  return err_code;\n}\n#else\nerr_code_t cmd_flash_fw_read_block( uint32_t addr, uint8_t *p_data, uint16_t length )\n{\n  err_code_t err_code = OK;\n  mavlink_message_t tx_msg;\n  mavlink_message_t rx_msg;\n  mavlink_flash_fw_read_packet_t  resp_msg;\n  uint8_t resp = 1;\n\n\n  mavlink_msg_flash_fw_read_block_pack(0, 0, &tx_msg, resp, addr, length);\n  msg_send(0, &tx_msg);\n\n\n\n  if( resp == 1 )\n  {\n    if( msg_get_resp(0, &rx_msg, 100) == TRUE )\n    {\n      mavlink_msg_flash_fw_read_packet_decode( &rx_msg, &resp_msg);\n\n      memcpy(p_data, resp_msg.data, resp_msg.length);\n\n      if( resp_msg.length > length )\n      {\n\terr_code = ERR_SIZE_OVER;\n      }\n    }\n    else\n    {\n      err_code = ERR_TIMEOUT;\n    }\n  }\n\n  return err_code;\n}\n#endif\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : cmd_flash_fw_verify\n     WORK    :\n---------------------------------------------------------------------------*/\nerr_code_t cmd_flash_fw_verify( uint32_t length, uint32_t crc, uint32_t *p_crc_ret )\n{\n  err_code_t err_code = OK;\n  mavlink_message_t tx_msg;\n  mavlink_message_t rx_msg;\n  mavlink_ack_t     ack_msg;\n  uint8_t param[8];\n  uint8_t resp = 1;\n\n\n  mavlink_msg_flash_fw_verify_pack(0, 0, &tx_msg, resp, length, crc, param);\n  msg_send(0, &tx_msg);\n\n\n  if( resp == 1 )\n  {\n    if( msg_get_resp(0, &rx_msg, 500) == TRUE )\n    {\n      mavlink_msg_ack_decode( &rx_msg, &ack_msg);\n\n      *p_crc_ret = ack_msg.data[3]<<24|ack_msg.data[2]<<16|ack_msg.data[1]<<8|ack_msg.data[0];\n\n      if( tx_msg.msgid == ack_msg.msg_id ) err_code = ack_msg.err_code;\n      else                                 err_code = ERR_MISMATCH_ID;\n    }\n    else\n    {\n      err_code = ERR_TIMEOUT;\n    }\n  }\n  return err_code;\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : cmd_jump_to_fw\n     WORK    :\n---------------------------------------------------------------------------*/\nerr_code_t cmd_jump_to_fw(void)\n{\n  err_code_t err_code = OK;\n  mavlink_message_t tx_msg;\n  mavlink_message_t rx_msg;\n  mavlink_ack_t     ack_msg;\n  uint8_t param[8];\n  uint8_t resp = 0;\n\n\n  mavlink_msg_jump_to_fw_pack(0, 0, &tx_msg, resp, param);\n  msg_send(0, &tx_msg);\n\n\n  if( resp == 1 )\n  {\n    if( msg_get_resp(0, &rx_msg, 500) == TRUE )\n    {\n      mavlink_msg_ack_decode( &rx_msg, &ack_msg);\n\n      if( tx_msg.msgid == ack_msg.msg_id ) err_code = ack_msg.err_code;\n      else                                 err_code = ERR_MISMATCH_ID;\n    }\n    else\n    {\n      err_code = ERR_TIMEOUT;\n    }\n  }\n  return err_code;\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : crc_calc\n     WORK    :\n---------------------------------------------------------------------------*/\nuint32_t crc_calc( uint32_t crc_in, uint8_t data_in )\n{\n\n  crc_in  ^= data_in;\n  crc_in  += data_in;\n\n  return crc_in;\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : opencr_ld_write_err_msg\n     WORK    :\n---------------------------------------------------------------------------*/\nvoid opencr_ld_write_err_msg( const char *fmt, ...)\n{\n  int32_t ret = 0;\n  va_list arg;\n  va_start (arg, fmt);\n  int32_t len;\n\n  len = vsnprintf(err_msg_str, 255, fmt, arg);\n  va_end (arg);\n}\n\n\n/*---------------------------------------------------------------------------\n     TITLE   : opencr_ld_write_err_msg\n     WORK    :\n---------------------------------------------------------------------------*/\nvoid opencr_ld_print_err_msg(void)\n{\n  uint32_t len;\n\n  len = strlen(err_msg_str);\n\n  if( len > 0 && len < 500 )\n  {\n    printf(\"%s\", err_msg_str);\n  }\n}\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/opencr_ld.h",
    "content": "/*\r\n *  main.h\r\n *\r\n *  Created on: 2016. 5. 14.\r\n *      Author: Baram, PBPH\r\n */\r\n\r\n#ifndef __OPENCR_LD_MAIN_H_\r\n#define __OPENCR_LD_MAIN_H_\r\n\r\n#include <unistd.h>\r\n#include \"type.h\"\r\n#include \"serial.h\"\r\n\r\n\r\n\r\n#define MAGIC_NUMBER   0x5555AAAA\r\n\r\n\r\n\r\ntypedef struct\r\n{\r\n  uint32_t magic_number;\r\n  char     fw_name_str[128];\r\n  char     fw_ver_str[128];\r\n  uint32_t fw_size;\r\n  uint8_t  reserved[1024];\r\n} opencr_fw_header_t;\r\n\r\n\r\n\r\nint opencr_ld_main( int argc, const char **argv );\r\n\r\n\r\n#endif\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/qt_win/opencr_ld_win/opencr_ld/.gitignore",
    "content": ".opencr_ld.pro.user*"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/qt_win/opencr_ld_win/opencr_ld/main.c",
    "content": "#include <stdio.h>\r\n\r\nint main(int argc, char *argv[])\r\n{\r\n    printf(\"Hello World!\\n\");\r\n    return 0;\r\n}\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/qt_win/opencr_ld_win/opencr_ld/opencr_ld.pro",
    "content": "TEMPLATE = app\r\nCONFIG += console\r\nCONFIG -= app_bundle\r\nCONFIG -= qt\r\n\r\nDEFINES += WIN32_BUILD\r\n\r\nSOURCES += \\\r\n    ../../../msg/msg.c \\\r\n    ../../../main.c \\\r\n    ../../../opencr_ld.c \\\r\n    ../../../serial_win32.c\r\n\r\nHEADERS += \\\r\n    ../../../opencr_ld.h \\\r\n    ../../../serial.h \\\r\n    ../../../type.h \\\r\n    ../../../msg/mavlink/opencr_msg/mavlink.h \\\r\n    ../../../msg/mavlink/opencr_msg/mavlink_msg_ack.h \\\r\n    ../../../msg/mavlink/opencr_msg/mavlink_msg_flash_fw_erase.h \\\r\n    ../../../msg/mavlink/opencr_msg/mavlink_msg_flash_fw_read_block.h \\\r\n    ../../../msg/mavlink/opencr_msg/mavlink_msg_flash_fw_read_packet.h \\\r\n    ../../../msg/mavlink/opencr_msg/mavlink_msg_flash_fw_verify.h \\\r\n    ../../../msg/mavlink/opencr_msg/mavlink_msg_flash_fw_write_begin.h \\\r\n    ../../../msg/mavlink/opencr_msg/mavlink_msg_flash_fw_write_block.h \\\r\n    ../../../msg/mavlink/opencr_msg/mavlink_msg_flash_fw_write_end.h \\\r\n    ../../../msg/mavlink/opencr_msg/mavlink_msg_flash_fw_write_packet.h \\\r\n    ../../../msg/mavlink/opencr_msg/mavlink_msg_jump_to_fw.h \\\r\n    ../../../msg/mavlink/opencr_msg/mavlink_msg_read_board_name.h \\\r\n    ../../../msg/mavlink/opencr_msg/mavlink_msg_read_tag.h \\\r\n    ../../../msg/mavlink/opencr_msg/mavlink_msg_read_version.h \\\r\n    ../../../msg/mavlink/opencr_msg/opencr_msg.h \\\r\n    ../../../msg/mavlink/opencr_msg/testsuite.h \\\r\n    ../../../msg/mavlink/opencr_msg/version.h \\\r\n    ../../../msg/mavlink/checksum.h \\\r\n    ../../../msg/mavlink/mavlink_conversions.h \\\r\n    ../../../msg/mavlink/mavlink_helpers.h \\\r\n    ../../../msg/mavlink/mavlink_types.h \\\r\n    ../../../msg/mavlink/protocol.h \\\r\n    ../../../msg/def.h \\\r\n    ../../../msg/def_err.h \\\r\n    ../../../msg/msg.h\r\n"
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    "path": "arduino/opencr_develop/opencr_ld_shell/qt_win/opencr_ld_win/opencr_ld/opencr_ld.pro.user",
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    "path": "arduino/opencr_develop/opencr_ld_shell/serial.h",
    "content": "#ifndef __SERIAL_H__\r\n#define __SERIAL_H__\r\n\r\n#include \"type.h\"\r\n\r\n#define SER_INF_TIMEOUT         0xFFFFFFFF\r\n#define SER_NO_TIMEOUT          0\r\n#define SER_OK                  0\r\n#define SER_ERR                 1\r\n\r\n// Serial interface modes (blocking or non blocking)\r\n#define SER_MODE_BLOCKING       0\r\n#define SER_MODE_NONBLOCKING    1\r\n\r\n// Setup constants\r\n#define SER_PARITY_NONE         0\r\n#define SER_PARITY_EVEN         1\r\n#define SER_PARITY_ODD          2\r\n\r\n#define SER_STOPBITS_1          0\r\n#define SER_STOPBITS_1_5        1\r\n#define SER_STOPBITS_2          2\r\n\r\n#define SER_DATABITS_5          5\r\n#define SER_DATABITS_6          6\r\n#define SER_DATABITS_7          7\r\n#define SER_DATABITS_8          8\r\n\r\n// Serial access functions (to be implemented by each platform)\r\nser_handler ser_open( const char *sername );\r\nvoid ser_close( ser_handler id );\r\nint ser_setup( ser_handler id, u32 baud, int databits, int parity, int stopbits );\r\nu32 ser_read( ser_handler id, u8* dest, u32 maxsize );\r\nint ser_read_byte( ser_handler id );\r\nu32 ser_write( ser_handler id, const u8 *src, u32 size );\r\nu32 ser_write_byte( ser_handler id, u8 data );\r\nvoid ser_set_timeout_ms( ser_handler id, u32 timeout );\r\n\r\nint ser_setupEx( ser_handler id, u32 baud, int databits, int parity, int stopbits, int Mode );\r\n\r\nextern int read_bytes( uint8_t *pData, uint32_t size );\r\n\r\n#endif\r\n"
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  {
    "path": "arduino/opencr_develop/opencr_ld_shell/serial_posix.c",
    "content": "// Serial inteface implementation for POSIX-compliant systems\r\n\r\n#include \"serial.h\"\r\n#include <stdio.h>\r\n#include <string.h>\r\n#include <unistd.h>\r\n#include <fcntl.h>\r\n#include <errno.h>\r\n#include <termios.h>\r\n#include <sys/select.h>\r\n#include <sys/time.h>\r\n#include <sys/types.h>\r\n\r\nstatic u32 ser_timeout = SER_INF_TIMEOUT;\r\n\r\n// Open the serial port\r\nser_handler ser_open( const char* sername )\r\n{\r\n  int fd;\r\n\r\n  if( ( fd = open( sername, O_RDWR | O_NOCTTY | O_NDELAY | O_NONBLOCK) ) == -1 )\r\n    perror( \"ser_open: unable to open port\" );\r\n  else\r\n    fcntl( fd, F_SETFL, 0 );\r\n  return ( ser_handler )fd;\r\n}\r\n\r\n// Close the serial port\r\nvoid ser_close( ser_handler id )\r\n{\r\n  close( ( int )id );\r\n}\r\n\r\n// Helper function: get baud ID from actual baud rate\r\n#define BAUDCASE(x)  case x: return B##x\r\nstatic u32 ser_baud_to_id( u32 baud )\r\n{\r\n  switch( baud )\r\n  {\r\n    BAUDCASE( 1200 );\r\n    BAUDCASE( 1800 );\r\n    BAUDCASE( 2400 );\r\n    BAUDCASE( 4800 );\r\n    BAUDCASE( 9600 );\r\n    BAUDCASE( 19200 );\r\n    BAUDCASE( 38400 );\r\n    BAUDCASE( 57600 );\r\n    BAUDCASE( 115200 );\r\n    BAUDCASE( 230400 );\r\n  }\r\n  return 0;\r\n}\r\n\r\n// Helper function: get number of bits ID from actual number of bits\r\n#define NBCASE(x) case x: return CS##x\r\nstatic int ser_number_of_bits_to_id( int nb )\r\n{\r\n  switch( nb )\r\n  {\r\n    NBCASE( 5 );\r\n    NBCASE( 6 );\r\n    NBCASE( 7 );\r\n    NBCASE( 8 );\r\n  }\r\n  return 0;\r\n}\r\n\r\nint ser_setup( ser_handler id, u32 baud, int databits, int parity, int stopbits )\r\n{\r\n  struct termios termdata;\r\n  int hnd = ( int )id;\r\n\r\n  usleep( 200000 );\r\n  tcgetattr( hnd, &termdata );\r\n\r\n  // Baud rate\r\n  cfsetispeed( &termdata, ser_baud_to_id( baud ) );\r\n  cfsetospeed( &termdata, ser_baud_to_id( baud ) );\r\n\r\n  // Parity / stop bits\r\n  termdata.c_cflag &= ~CSTOPB;\r\n  if( parity == SER_PARITY_NONE ) // no parity\r\n  {\r\n    termdata.c_cflag &= ~PARENB;\r\n  }\r\n  else if( parity == SER_PARITY_EVEN ) // even parity\r\n  {\r\n    termdata.c_cflag |= PARENB;\r\n    termdata.c_cflag &= ~PARODD;\r\n  }\r\n  else if( parity == SER_PARITY_ODD ) // odd parity\r\n  {\r\n    termdata.c_cflag |= PARENB;\r\n    termdata.c_cflag |= PARODD;\r\n  }\r\n\r\n   // Data bits\r\n  termdata.c_cflag |= ( CLOCAL | CREAD );\r\n  termdata.c_cflag &= ~CSIZE;\r\n  termdata.c_cflag |= ser_number_of_bits_to_id( databits );\r\n\r\n  // Disable HW and SW flow control\r\n  termdata.c_cflag &= ~CRTSCTS;\r\n  termdata.c_iflag &= ~( IXON | IXOFF | IXANY );\r\n\r\n  // Raw input\r\n  termdata.c_lflag &= ~( ICANON | ECHO | ECHOE | ISIG );\r\n\r\n  // Raw output\r\n  termdata.c_oflag &= ~OPOST;\r\n\r\n  // Check and strip parity bit\r\n  if( parity == SER_PARITY_NONE )\r\n    termdata.c_iflag &= ~( INPCK | ISTRIP );\r\n  else\r\n    termdata.c_iflag |= ( INPCK | ISTRIP );\r\n\r\n  // Setup timeouts\r\n  termdata.c_cc[ VMIN ]  = 1;\r\n  termdata.c_cc[ VTIME ] = 0;\r\n\r\n  // Set the attibutes now\r\n  tcsetattr( hnd, TCSANOW, &termdata );\r\n\r\n  // Flush everything\r\n  tcflush( hnd, TCIOFLUSH );\r\n\r\n  // And set blocking mode by default\r\n  fcntl( id, F_SETFL, 0 );\r\n\r\n  return 0;\r\n}\r\n\r\n\r\nint ser_setupEx( ser_handler id, u32 baud, int databits, int parity, int stopbits, int Mode )\r\n{\r\n  struct termios termdata;\r\n  int hnd = ( int )id;\r\n\r\n  usleep( 200000 );\r\n  tcgetattr( hnd, &termdata );\r\n\r\n  // Baud rate\r\n  cfsetispeed( &termdata, ser_baud_to_id( baud ) );\r\n  cfsetospeed( &termdata, ser_baud_to_id( baud ) );\r\n\r\n  // Parity / stop bits\r\n  termdata.c_cflag &= ~CSTOPB;\r\n  if( parity == SER_PARITY_NONE ) // no parity\r\n  {\r\n    termdata.c_cflag &= ~PARENB;\r\n  }\r\n  else if( parity == SER_PARITY_EVEN ) // even parity\r\n  {\r\n    termdata.c_cflag |= PARENB;\r\n    termdata.c_cflag &= ~PARODD;\r\n  }\r\n  else if( parity == SER_PARITY_ODD ) // odd parity\r\n  {\r\n    termdata.c_cflag |= PARENB;\r\n    termdata.c_cflag |= PARODD;\r\n  }\r\n\r\n   // Data bits\r\n  termdata.c_cflag |= ( CLOCAL | CREAD );\r\n  termdata.c_cflag &= ~CSIZE;\r\n  termdata.c_cflag |= ser_number_of_bits_to_id( databits );\r\n\r\n\r\n\r\n  // Disable HW and SW flow control\r\n  termdata.c_cflag &= ~CRTSCTS;\r\n  termdata.c_iflag &= ~( IXON | IXOFF | IXANY );\r\n\r\n\r\n  if( Mode == 0 )\r\n    termdata.c_cflag &= ~CRTSCTS;\r\n  else\r\n    termdata.c_cflag |= CRTSCTS;    /* Also called CRTSCTS */\r\n\r\n    \r\n\r\n  // Raw input\r\n  termdata.c_lflag &= ~( ICANON | ECHO | ECHOE | ISIG );\r\n\r\n  // Raw output\r\n  termdata.c_oflag &= ~OPOST;\r\n\r\n\r\n  // Check and strip parity bit\r\n  if( parity == SER_PARITY_NONE )\r\n    termdata.c_iflag &= ~( INPCK | ISTRIP );\r\n  else\r\n    termdata.c_iflag |= ( INPCK | ISTRIP );\r\n\r\n  // Setup timeouts\r\n  termdata.c_cc[ VMIN ]  = 0;\r\n  termdata.c_cc[ VTIME ] = 1;\r\n\r\n  // Set the attibutes now\r\n  tcsetattr( hnd, TCSANOW, &termdata );\r\n\r\n  // Flush everything\r\n  tcflush( hnd, TCIOFLUSH );\r\n\r\n  // And set blocking mode by default\r\n  //fcntl( id, F_SETFL, 0 );\r\n\r\n  return 0;\r\n}\r\n\r\n\r\n\r\n// Read up to the specified number of bytes, return bytes actually read\r\nu32 ser_read( ser_handler id, u8* dest, u32 maxsize )\r\n{\r\n  if( ser_timeout == SER_INF_TIMEOUT )\r\n    return ( u32 )read( ( int )id, dest, maxsize );\r\n  else\r\n  {\r\n    fd_set readfs;\r\n    struct timeval tv;\r\n    int retval;\r\n\r\n    FD_ZERO( &readfs );\r\n    FD_SET( ( int )id, &readfs );\r\n    tv.tv_sec = ser_timeout / 1000000;\r\n    tv.tv_usec = ( ser_timeout % 1000000 ) * 1000;\r\n    retval = select( ( int )id + 1, &readfs, NULL, NULL, &tv );\r\n    if( retval == -1 || retval == 0 )\r\n      return 0;\r\n    else \r\n      return ( u32 )read( ( int )id, dest, maxsize );\r\n  }\r\n}\r\n\r\n// Read a single byte and return it (or -1 for error)\r\nint ser_read_byte( ser_handler id )\r\n{\r\n  u8 data;\r\n  int res = ser_read( id, &data, 1 );\r\n\r\n  return res == 1 ? data : -1;\r\n}\r\n\r\n// Write up to the specified number of bytes, return bytes actually written\r\nu32 ser_write( ser_handler id, const u8 *src, u32 size )\r\n{\r\n  u32 res;\r\n  \r\n  res = ( u32 )write( ( int )id, src, size );\r\n  return res;\r\n}\r\n\r\n// Write a byte to the serial port\r\nu32 ser_write_byte( ser_handler id, u8 data )\r\n{\r\n  return ( u32 )write( id, &data, 1 );\r\n}\r\n\r\n// Set communication timeout\r\nvoid ser_set_timeout_ms( ser_handler id, u32 timeout )\r\n{\r\n  ser_timeout = timeout;\r\n}\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/serial_win32.c",
    "content": "// Serial inteface implementation for POSIX-compliant systems\r\n\r\n#include <windows.h>\r\n#include <string.h>\r\n#include <stdio.h>\r\n#include \"type.h\"\r\n#include \"serial.h\"\r\n\r\n#define WIN_ERROR     ( HANDLE )-1\r\n#define WIN_MAX_PORT_NAME   1024\r\n\r\n// Helper: set timeout\r\nstatic int ser_win32_set_timeouts( HANDLE hComm, DWORD ri, DWORD rtm, DWORD rtc, DWORD wtm, DWORD wtc )\r\n{   \r\n  COMMTIMEOUTS timeouts;\r\n  \r\n  if( GetCommTimeouts( hComm, &timeouts ) == FALSE )\r\n  {\r\n    CloseHandle( hComm );\r\n    return SER_ERR;\r\n  }\r\n  timeouts.ReadIntervalTimeout = ri;\r\n  timeouts.ReadTotalTimeoutConstant = rtm;\r\n  timeouts.ReadTotalTimeoutMultiplier = rtc;\r\n  timeouts.WriteTotalTimeoutConstant = wtm;\r\n  timeouts.WriteTotalTimeoutMultiplier = wtc;\r\n\tif( SetCommTimeouts( hComm, &timeouts ) == FALSE )\r\n\t{\r\n\t  CloseHandle( hComm );\r\n\t  return SER_ERR;\r\n  }               \r\n  \r\n  return SER_OK;\r\n}\r\n\r\n// Open the serial port\r\nser_handler ser_open( const char* sername )\r\n{\r\n  char portname[ WIN_MAX_PORT_NAME + 1 ];\r\n  wchar_t pname[ WIN_MAX_PORT_NAME + 1 ];\r\n  HANDLE hComm;\r\n  \r\n  portname[ 0 ] = portname[ WIN_MAX_PORT_NAME ] = '\\0';\r\n  _snprintf( portname, WIN_MAX_PORT_NAME, \"\\\\\\\\.\\\\%s\", sername );\r\n  //swprintf( portname, WIN_MAX_PORT_NAME, \"\\\\\\\\.\\\\%s\", sername );\r\n\r\n  mbstowcs(pname, portname, WIN_MAX_PORT_NAME);\r\n\r\n  hComm = CreateFile( pname, GENERIC_READ | GENERIC_WRITE, 0, 0, OPEN_EXISTING, 0, 0 );\r\n  if( hComm == INVALID_HANDLE_VALUE )\r\n  {\r\n    printf(\"hComm err : %s\\n\", pname);\r\n    return WIN_ERROR;\r\n  }\r\n  if( !SetupComm( hComm, 2048, 2048 ) )\r\n    return WIN_ERROR;\r\n  return hComm;\r\n}\r\n\r\n// Close the serial port\r\nvoid ser_close( ser_handler id )\r\n{\r\n  CloseHandle( id );\r\n}\r\n\r\nint ser_setup( ser_handler id, u32 baud, int databits, int parity, int stopbits )\r\n{\r\n  HANDLE hComm = ( HANDLE )id;\r\n  DCB dcb;\r\n  \r\n\tif( GetCommState( hComm, &dcb ) == FALSE )\r\n\t{\r\n\t\tCloseHandle( hComm );\r\n\t\treturn SER_ERR;\r\n\t}\r\n  dcb.BaudRate = baud;\r\n  dcb.ByteSize = databits;\r\n  dcb.Parity = parity == SER_PARITY_NONE ? NOPARITY : ( parity == SER_PARITY_EVEN ? EVENPARITY : ODDPARITY );\r\n  dcb.StopBits = stopbits == SER_STOPBITS_1 ? ONESTOPBIT : ( stopbits == SER_STOPBITS_1_5 ? ONE5STOPBITS : TWOSTOPBITS );\r\n  dcb.fBinary = TRUE;\r\n  dcb.fDsrSensitivity = FALSE;\r\n  dcb.fParity = parity != SER_PARITY_NONE ? TRUE : FALSE;\r\n  dcb.fOutX = FALSE;\r\n  dcb.fInX = FALSE;\r\n  dcb.fNull = FALSE;\r\n  /**/ dcb.fAbortOnError = FALSE;\r\n  dcb.fOutxCtsFlow = FALSE;\r\n  dcb.fOutxDsrFlow = FALSE;\r\n  dcb.fDtrControl = DTR_CONTROL_DISABLE;\r\n  dcb.fDsrSensitivity = FALSE;\r\n  dcb.fRtsControl = RTS_CONTROL_DISABLE;\r\n  dcb.fOutxCtsFlow = FALSE;\r\n  if( SetCommState( hComm, &dcb ) == 0 )\r\n  {\r\n    CloseHandle( hComm );\r\n    return SER_ERR;\r\n  }\r\n  \r\n  if( ser_win32_set_timeouts( hComm, 0, 0, 0, 0, 0 ) == SER_ERR )\r\n  {\r\n    CloseHandle( hComm );\r\n    return SER_ERR;\r\n  }\r\n  \r\n  FlushFileBuffers( hComm );\r\n\r\n  return SER_OK;\r\n}\r\n\r\n\r\nint ser_setupEx( ser_handler id, u32 baud, int databits, int parity, int stopbits, int Mode )\r\n{\r\n  HANDLE hComm = ( HANDLE )id;\r\n  DCB dcb;\r\n  \r\n  if( GetCommState( hComm, &dcb ) == FALSE )\r\n  {\r\n    CloseHandle( hComm );\r\n    return SER_ERR;\r\n  }\r\n  dcb.BaudRate = baud;\r\n  dcb.ByteSize = databits;\r\n  dcb.Parity = parity == SER_PARITY_NONE ? NOPARITY : ( parity == SER_PARITY_EVEN ? EVENPARITY : ODDPARITY );\r\n  dcb.StopBits = stopbits == SER_STOPBITS_1 ? ONESTOPBIT : ( stopbits == SER_STOPBITS_1_5 ? ONE5STOPBITS : TWOSTOPBITS );\r\n  dcb.fBinary = TRUE;\r\n  dcb.fDsrSensitivity = FALSE;\r\n  dcb.fParity = parity != SER_PARITY_NONE ? TRUE : FALSE;\r\n  dcb.fOutX = FALSE;\r\n  dcb.fInX = FALSE;\r\n  dcb.fNull = FALSE;\r\n  /**/ dcb.fAbortOnError = FALSE;\r\n  dcb.fOutxCtsFlow = FALSE;\r\n  dcb.fOutxDsrFlow = FALSE;\r\n  dcb.fDtrControl = DTR_CONTROL_DISABLE;\r\n  dcb.fDsrSensitivity = FALSE;\r\n  \r\n  if( Mode == 0 )\r\n    dcb.fRtsControl = RTS_CONTROL_DISABLE;\r\n  else\r\n    dcb.fRtsControl = RTS_CONTROL_ENABLE;\r\n    \r\n  dcb.fOutxCtsFlow = FALSE;\r\n  if( SetCommState( hComm, &dcb ) == 0 )\r\n  {\r\n    CloseHandle( hComm );\r\n    return SER_ERR;\r\n  }\r\n  \r\n  if( ser_win32_set_timeouts( hComm, 0, 0, 0, 0, 0 ) == SER_ERR )\r\n  {\r\n    CloseHandle( hComm );\r\n    return SER_ERR;\r\n  }\r\n  \r\n  FlushFileBuffers( hComm );\r\n\r\n  return SER_OK;\r\n}\r\n\r\n\r\n// Read up to the specified number of bytes, return bytes actually read\r\nu32 ser_read( ser_handler id, u8* dest, u32 maxsize )\r\n{\r\n  HANDLE hComm = ( HANDLE )id;\r\n  DWORD readbytes;\r\n  \r\n  if( ReadFile( hComm, dest, maxsize, &readbytes, NULL ) == FALSE )\r\n    return 0;\r\n  return readbytes;\r\n}\r\n\r\n// Read a single byte and return it (or -1 for error)\r\nint ser_read_byte( ser_handler id )\r\n{\r\n  u8 data;\r\n  int res = ser_read( id, &data, 1 );\r\n\r\n  //printf( \"READ %02X, res is %d\\n\", data, res );\r\n  return res == 1 ? data : -1;\r\n}\r\n\r\n// Write up to the specified number of bytes, return bytes actually written\r\nu32 ser_write( ser_handler id, const u8 *src, u32 size )\r\n{\r\n  HANDLE hComm = ( HANDLE )id;\r\n\tDWORD written;\r\n\t\r\n  if( WriteFile( hComm, src, size, &written, NULL ) == FALSE )\r\n    return 0;\r\n  return written;\r\n}\r\n\r\n// Write a byte to the serial port\r\nu32 ser_write_byte( ser_handler id, u8 data )\r\n{\r\n  return ser_write( id, &data, 1 );\r\n}\r\n\r\n// Set communication timeout\r\nvoid ser_set_timeout_ms( ser_handler id, u32 timeout )\r\n{\r\n  if( timeout == SER_NO_TIMEOUT )\r\n    ser_win32_set_timeouts( id, MAXDWORD, 0, 0, 0, 0 );\r\n  else if( timeout == SER_INF_TIMEOUT )\r\n    ser_win32_set_timeouts( id, 0, 0, 0, 0, 0 );\r\n  else\r\n    ser_win32_set_timeouts( id, 0, 0, timeout, 0, 0 );\r\n}\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/type.h",
    "content": "// Portable types\r\n\r\n#ifndef __TYPE_H_\r\n#define __TYPE_H_\r\n\r\n#include <stdint.h>\r\n\r\n#ifdef WIN32_BUILD\r\ntypedef char s8;\r\ntypedef unsigned char u8;\r\n\r\ntypedef short s16;\r\ntypedef unsigned short u16;\r\n\r\ntypedef int s32;\r\ntypedef unsigned int u32;\r\n\r\ntypedef long s64;\r\ntypedef unsigned long u64;\r\n#else\r\ntypedef char s8;\r\ntypedef unsigned char u8;\r\n\r\ntypedef short s16;\r\ntypedef unsigned short u16;\r\n\r\ntypedef long s32;\r\ntypedef unsigned long u32;\r\n\r\ntypedef long long s64;\r\ntypedef unsigned long long u64;\r\n#endif\r\n\r\n// Define serial port \"handle\" type for each platform\r\n// [TODO] for now, only UNIX is supported\r\n#ifdef WIN32_BUILD\r\n#include <windows.h>\r\ntypedef HANDLE ser_handler;\r\n#else // assume POSIX here\r\ntypedef int ser_handler;\r\n#endif\r\n\r\n\r\n#ifndef TRUE\r\n#define TRUE  1\r\n#endif\r\n\r\n#ifndef FALSE \r\n#define FALSE 0\r\n#endif\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "arduino/opencr_develop/opencr_ld_shell/update.sh",
    "content": "#! /bin/bash\n\n\necho \"OpenCR Update Start..\"\nif (($#==2))\nthen\n  ./opencr_ld_shell $1 115200 $2 1\nelse\n  echo \"wrong parameter \"\n  echo \"update.sh <port> fw_name\"\nfi\n\nexit\n"
  },
  {
    "path": "arduino/opencr_release/package_opencr_index.json",
    "content": "{\n  \"packages\": [\n    {\n      \"name\": \"OpenCR\",\n      \"maintainer\": \"ROBOTIS\",\n      \"websiteURL\": \"https://github.com/ROBOTIS-GIT/OpenCR\",\n      \"email\": \"chc@robotis.com\",\n      \"help\": {\n        \"online\": \"https://github.com/ROBOTIS-GIT/OpenCR\"\n      },\n      \"platforms\": [\n        {\n          \"name\": \"OpenCR\",\n          \"architecture\": \"OpenCR\",\n          \"version\": \"1.0.0\",\n          \"category\": \"Arduino\",\n          \"help\": {\n            \"online\": \"https://github.com/ROBOTIS-GIT/OpenCR\"\n          },\n          \"url\": \"https://github.com/ROBOTIS-GIT/OpenCR/releases/download/1.0.0/opencr_core_1.0.0.tar.bz2\",\n          \"archiveFileName\": \"opencr_core_1.0.0.tar.bz2\",\n          \"checksum\": \"SHA-256:e5a7b6b9d5b5213c4aa9b9b7600dff5d5c979656859c049706edc1c33b12ee20\",\n          \"size\": \"829978\",\n          \"help\": {\n                    \"online\": \"https://github.com/ROBOTIS-GIT/OpenCR\"\n          },\n          \"boards\": [\n            {\"name\": \"OpenCR\"}\n          ],\n          \"toolsDependencies\": [\n            {\n              \"packager\": \"OpenCR\",\n              \"name\": \"opencr_gcc\",\n              \"version\": \"5.4.0-2016q2\"\n            },\n            {\n              \"packager\": \"OpenCR\",\n              \"name\": \"opencr_tools\",\n              \"version\": \"1.0.0\"\n            }\n          ]\n        },\n        {\n          \"name\": \"OpenCR\",\n          \"architecture\": \"OpenCR\",\n          \"version\": \"1.0.1\",\n          \"category\": \"Arduino\",\n          \"help\": {\n            \"online\": \"https://github.com/ROBOTIS-GIT/OpenCR\"\n          },\n          \"url\": \"https://github.com/ROBOTIS-GIT/OpenCR/releases/download/1.0.1/opencr_core_1.0.1.tar.bz2\",\n          \"archiveFileName\": \"opencr_core_1.0.1.tar.bz2\",\n          \"checksum\": \"SHA-256:142e5ca3879ed27dd786089e1ae22074a20af0046f0f7bf193e591db69b2a8a0\",\n          \"size\": \"829978\",\n          \"help\": {\n                    \"online\": \"https://github.com/ROBOTIS-GIT/OpenCR\"\n          },\n          \"boards\": [\n            {\"name\": \"OpenCR\"}\n          ],\n          \"toolsDependencies\": [\n            {\n              \"packager\": \"OpenCR\",\n              \"name\": \"opencr_gcc\",\n              \"version\": \"5.4.0-2016q2\"\n            },\n            {\n              \"packager\": \"OpenCR\",\n              \"name\": \"opencr_tools\",\n              \"version\": \"1.0.0\"\n            }\n          ]\n        },\n        {\n          \"name\": \"OpenCR\",\n          \"architecture\": \"OpenCR\",\n          \"version\": \"1.0.2\",\n          \"category\": \"Arduino\",\n          \"help\": {\n            \"online\": \"https://github.com/ROBOTIS-GIT/OpenCR\"\n          },\n          \"url\": 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\"OpenCR\",\n              \"name\": \"opencr_tools\",\n              \"version\": \"1.0.0\"\n            }\n          ]\n        },\n        {\n          \"name\": \"OpenCR\",\n          \"architecture\": \"OpenCR\",\n          \"version\": \"1.4.17\",\n          \"category\": \"Arduino\",\n          \"help\": {\n            \"online\": \"https://github.com/ROBOTIS-GIT/OpenCR\"\n          },\n          \"url\": \"https://github.com/ROBOTIS-GIT/OpenCR/releases/download/1.4.17/opencr.tar.bz2\",\n          \"archiveFileName\": \"opencr.tar.bz2\",\n          \"checksum\": \"SHA-256:2A0E5BC5ADE6EDFE1BAB44ED865DC315D9A9B24994956C5863CD3142BE387D30\",\n          \"size\": \"1991420\",\n          \"help\": {\n                    \"online\": \"http://emanual.robotis.com/docs/en/parts/controller/opencr10/\"\n          },\n          \"boards\": [\n            {\"name\": \"OpenCR\"}\n          ],\n          \"toolsDependencies\": [\n            {\n              \"packager\": \"OpenCR\",\n              \"name\": \"opencr_gcc\",\n              \"version\": \"5.4.0-2016q2\"\n            },\n            {\n              \"packager\": \"OpenCR\",\n              \"name\": \"opencr_tools\",\n              \"version\": \"1.0.0\"\n            }\n          ]\n        },\n        {\n          \"name\": \"OpenCR\",\n          \"architecture\": \"OpenCR\",\n          \"version\": \"1.4.18\",\n          \"category\": \"Arduino\",\n          \"help\": {\n            \"online\": \"https://github.com/ROBOTIS-GIT/OpenCR\"\n          },\n          \"url\": \"https://github.com/ROBOTIS-GIT/OpenCR/releases/download/1.4.18/opencr.tar.bz2\",\n          \"archiveFileName\": \"opencr.tar.bz2\",\n          \"checksum\": \"SHA-256:DF1BA85D3EE4D54098334855956284913DBD74D8138409A8117BCE8E802C9F23\",\n          \"size\": \"1993015\",\n          \"help\": {\n                    \"online\": \"http://emanual.robotis.com/docs/en/parts/controller/opencr10/\"\n          },\n          \"boards\": [\n            {\"name\": \"OpenCR\"}\n          ],\n          \"toolsDependencies\": [\n            {\n              \"packager\": \"OpenCR\",\n              \"name\": \"opencr_gcc\",\n              \"version\": \"5.4.0-2016q2\"\n            },\n            {\n              \"packager\": \"OpenCR\",\n              \"name\": \"opencr_tools\",\n              \"version\": \"1.0.0\"\n            }\n          ]\n        },\n        {\n          \"name\": \"OpenCR\",\n          \"architecture\": \"OpenCR\",\n          \"version\": \"1.4.19\",\n          \"category\": \"Arduino\",\n          \"help\": {\n            \"online\": \"https://github.com/ROBOTIS-GIT/OpenCR\"\n          },\n          \"url\": \"https://github.com/ROBOTIS-GIT/OpenCR/releases/download/1.4.19/opencr.tar.bz2\",\n          \"archiveFileName\": \"opencr.tar.bz2\",\n          \"checksum\": \"SHA-256:ADF8130D897303F8B9EA3058663E28E4E30575F1D904B84C8BEBF6C85998FE7C\",\n          \"size\": \"2000797\",\n          \"help\": {\n                    \"online\": \"http://emanual.robotis.com/docs/en/parts/controller/opencr10/\"\n          },\n          \"boards\": [\n            {\"name\": \"OpenCR\"}\n          ],\n          \"toolsDependencies\": [\n            {\n              \"packager\": \"OpenCR\",\n              \"name\": \"opencr_gcc\",\n              \"version\": \"5.4.0-2016q2\"\n            },\n            {\n              \"packager\": \"OpenCR\",\n              \"name\": \"opencr_tools\",\n              \"version\": \"1.0.0\"\n            }\n          ]\n        },\n        {\n          \"name\": \"OpenCR\",\n          \"architecture\": \"OpenCR\",\n          \"version\": \"1.5.0\",\n          \"category\": \"Arduino\",\n          \"help\": {\n            \"online\": \"https://github.com/ROBOTIS-GIT/OpenCR\"\n          },\n          \"url\": \"https://github.com/ROBOTIS-GIT/OpenCR/releases/download/1.5.0/opencr.tar.bz2\",\n          \"archiveFileName\": \"opencr.tar.bz2\",\n          \"checksum\": \"SHA-256:3fbc2db004545fb59c9dd6769ac3fbfec5f156cc21ebc0d428a81cff9bb80e1b\",\n          \"size\": \"1997803\",\n          \"help\": {\n                    \"online\": \"http://emanual.robotis.com/docs/en/parts/controller/opencr10/\"\n          },\n          \"boards\": [\n            {\"name\": \"OpenCR\"}\n          ],\n          \"toolsDependencies\": [\n            {\n              \"packager\": \"OpenCR\",\n              \"name\": \"opencr_gcc\",\n              \"version\": \"5.4.0-2016q2\"\n            },\n            {\n              \"packager\": \"OpenCR\",\n              \"name\": \"opencr_tools\",\n              \"version\": \"1.0.0\"\n            }\n          ]\n        },\n        {\n          \"name\": \"OpenCR\",\n          \"architecture\": \"OpenCR\",\n          \"version\": \"1.5.1\",\n          \"category\": \"Arduino\",\n          \"help\": {\n            \"online\": \"https://github.com/ROBOTIS-GIT/OpenCR\"\n          },\n          \"url\": \"https://github.com/ROBOTIS-GIT/OpenCR/releases/download/1.5.1/opencr.tar.bz2\",\n          \"archiveFileName\": \"opencr.tar.bz2\",\n          \"checksum\": \"SHA-256:3809de9513c3f936c51f04c47c37be43b60084d43fe07fa787e42ea3564abacc\",\n          \"size\": \"2000179\",\n          \"help\": {\n                    \"online\": \"http://emanual.robotis.com/docs/en/parts/controller/opencr10/\"\n          },\n          \"boards\": [\n            {\"name\": \"OpenCR\"}\n          ],\n          \"toolsDependencies\": [\n            {\n              \"packager\": \"OpenCR\",\n              \"name\": \"opencr_gcc\",\n              \"version\": \"5.4.0-2016q2\"\n            },\n            {\n              \"packager\": \"OpenCR\",\n              \"name\": \"opencr_tools\",\n              \"version\": \"1.0.0\"\n            }\n          ]\n        },\n        {\n          \"name\": \"OpenCR\",\n          \"architecture\": \"OpenCR\",\n          \"version\": \"1.5.2\",\n          \"category\": \"Arduino\",\n          \"help\": {\n            \"online\": \"https://github.com/ROBOTIS-GIT/OpenCR\"\n          },\n          \"url\": \"https://github.com/ROBOTIS-GIT/OpenCR/releases/download/1.5.2/opencr.tar.bz2\",\n          \"archiveFileName\": \"opencr.tar.bz2\",\n          \"checksum\": \"SHA-256:578b4cfd399a1df2db1f3995b9d73efcd79bee10d1e4cfab91a3c01a519c369c\",\n          \"size\": \"2020884\",\n          \"help\": {\n                    \"online\": \"http://emanual.robotis.com/docs/en/parts/controller/opencr10/\"\n          },\n          \"boards\": [\n            {\"name\": \"OpenCR\"}\n          ],\n          \"toolsDependencies\": [\n            {\n              \"packager\": \"OpenCR\",\n              \"name\": \"opencr_gcc\",\n              \"version\": \"5.4.0-2016q2\"\n            },\n            {\n              \"packager\": \"OpenCR\",\n              \"name\": \"opencr_tools\",\n              \"version\": \"1.0.0\"\n            }\n          ]\n        },\n        {\n          \"name\": \"OpenCR\",\n          \"architecture\": \"OpenCR\",\n          \"version\": \"1.5.3\",\n          \"category\": \"Arduino\",\n          \"help\": {\n            \"online\": \"https://github.com/ROBOTIS-GIT/OpenCR\"\n          },\n          \"url\": \"https://github.com/ROBOTIS-GIT/OpenCR/releases/download/1.5.3/opencr.tar.bz2\",\n          \"archiveFileName\": \"opencr.tar.bz2\",\n          \"checksum\": \"SHA-256:418656e5e6d99d45d187ffdb28dece0f450c6707da3f6db56769f3ecafdc413c\",\n          \"size\": \"2690860\",\n          \"help\": {\n                    \"online\": \"http://emanual.robotis.com/docs/en/parts/controller/opencr10/\"\n          },\n          \"boards\": [\n            {\"name\": \"OpenCR\"}\n          ],\n          \"toolsDependencies\": [\n            {\n              \"packager\": \"OpenCR\",\n              \"name\": \"opencr_gcc\",\n              \"version\": \"5.4.0-2016q2\"\n            },\n            {\n              \"packager\": \"OpenCR\",\n              \"name\": \"opencr_tools\",\n              \"version\": \"1.0.0\"\n            }\n          ]\n        }\n      ],\n      \"tools\":[\n        {\n          \"name\": \"opencr_gcc\",\n          \"version\": \"5.4.0-2016q2\",\n          \"systems\": [\n            {\n              \"host\": \"i686-linux-gnu\",\n              \"url\": \"https://launchpad.net/gcc-arm-embedded/5.0/5-2016-q2-update/+download/gcc-arm-none-eabi-5_4-2016q2-20160622-linux.tar.bz2\",\n              \"archiveFileName\": \"gcc-arm-none-eabi-5_4-2016q2-20160622-linux.tar.bz2\",\n              \"checksum\": \"SHA-256:9910b6b5df12efe564dbb3856bf1599d4c16178a6f28bd8a23c9e5c3edc219e4\",\n              \"size\": \"92600244\"\n            },\n            {\n              \"host\": \"x86_64-pc-linux-gnu\",\n              \"url\": \"https://launchpad.net/gcc-arm-embedded/5.0/5-2016-q2-update/+download/gcc-arm-none-eabi-5_4-2016q2-20160622-linux.tar.bz2\",\n              \"archiveFileName\": \"gcc-arm-none-eabi-5_4-2016q2-20160622-linux.tar.bz2\",\n              \"checksum\": \"SHA-256:9910b6b5df12efe564dbb3856bf1599d4c16178a6f28bd8a23c9e5c3edc219e4\",\n              \"size\": \"92600244\"\n            },\n            {\n              \"host\": \"i686-mingw32\",\n              \"url\": \"https://github.com/ROBOTIS-GIT/OpenCR/releases/download/arduino/gcc-arm-none-eabi-5_4-2016q2-20160622-win32.tar.bz2\",\n              \"archiveFileName\": \"gcc-arm-none-eabi-5_4-2016q2-20160622-win32.tar.bz2\",\n              \"checksum\": \"SHA-256:19d6b216aba935b713274966230505d7aedc5d8e38970cbe02c1266209645161\",\n              \"size\": \"103246869\"\n            },\n            {\n              \"host\": \"i386-apple-darwin11\",\n              \"url\": \"https://launchpad.net/gcc-arm-embedded/5.0/5-2016-q2-update/+download/gcc-arm-none-eabi-5_4-2016q2-20160622-mac.tar.bz2\",\n              \"archiveFileName\": \"gcc-arm-none-eabi-5_4-2016q2-20160622-mac.tar.bz2\",\n              \"checksum\": \"SHA-256:e175a0eb7ee312013d9078a5031a14bf14dff82c7e697549f04b22e6084264c8\",\n              \"size\": \"96963810\"\n            }\n          ]\n        },\n        {\n          \"name\": \"opencr_tools\",\n          \"version\": \"1.0.0\",\n          \"systems\": [\n            {\n              \"host\": \"i686-linux-gnu\",\n              \"url\": \"https://github.com/ROBOTIS-GIT/OpenCR/releases/download/1.0.0/opencr_tools_1.0.0.tar.bz2\",\n              \"archiveFileName\": \"opencr_tools_1.0.0.tar.bz2\",\n              \"checksum\": \"SHA-256:86b547dc98e07c90f17e0a6c45b207153ee8b4344da841f26956f495295a3a6a\",\n              \"size\": \"513792\"\n            },\n            {\n              \"host\": \"x86_64-pc-linux-gnu\",\n              \"url\": \"https://github.com/ROBOTIS-GIT/OpenCR/releases/download/1.0.0/opencr_tools_1.0.0.tar.bz2\",\n              \"archiveFileName\": \"opencr_tools_1.0.0.tar.bz2\",\n              \"checksum\": \"SHA-256:86b547dc98e07c90f17e0a6c45b207153ee8b4344da841f26956f495295a3a6a\",\n              \"size\": \"513792\"\n            },\n            {\n              \"host\": \"i686-mingw32\",\n              \"url\": \"https://github.com/ROBOTIS-GIT/OpenCR/releases/download/1.0.0/opencr_tools_1.0.0.tar.bz2\",\n              \"archiveFileName\": \"opencr_tools_1.0.0.tar.bz2\",\n              \"checksum\": \"SHA-256:86b547dc98e07c90f17e0a6c45b207153ee8b4344da841f26956f495295a3a6a\",\n              \"size\": \"513792\"\n            },\n            {\n              \"host\": \"i386-apple-darwin11\",\n              \"url\": \"https://github.com/ROBOTIS-GIT/OpenCR/releases/download/1.0.0/opencr_tools_1.0.0.tar.bz2\",\n              \"archiveFileName\": \"opencr_tools_1.0.0.tar.bz2\",\n              \"checksum\": \"SHA-256:86b547dc98e07c90f17e0a6c45b207153ee8b4344da841f26956f495295a3a6a\",\n              \"size\": \"513792\"\n            }\n          ]\n        }\n      ]\n    }\n  ]\n}\n"
  },
  {
    "path": "install.sh",
    "content": "#!/usr/bin/env bash\n\n# we need bash 4 for associative arrays\nif [ \"${BASH_VERSION%%[^0-9]*}\" -lt \"4\" ]; then\n  echo \"BASH VERSION < 4: ${BASH_VERSION}\" >&2\n  exit 1\nfi\n\n# associative array for the platforms that will be verified in build_main_platforms()\n# this will be eval'd in the functions below because arrays can't be exported\nexport MAIN_PLATFORMS='declare -A main_platforms=([opencr]=\"OpenCR:OpenCR:OpenCR\")'\n\n# make display available for arduino CLI\n/sbin/start-stop-daemon --start --quiet --pidfile /tmp/custom_xvfb_1.pid --make-pidfile --background --exec /usr/bin/Xvfb -- :1 -ac -screen 0 1280x1024x16\nsleep 3\nexport DISPLAY=:1.0\n\n# download and install arduino 1.8.5\nwget https://downloads.arduino.cc/arduino-1.8.5-linux64.tar.xz\ntar xf arduino-1.8.5-linux64.tar.xz\nmv arduino-1.8.5 $HOME/arduino_ide\n\n# add the arduino CLI to our PATH\nexport PATH=\"$HOME/arduino_ide:$PATH\"\n\necho -e \"\\n########################################################################\";\necho \"INSTALLING DEPENDENCIES\"\necho \"########################################################################\";\n\n# install i386 archtecture library\nsudo dpkg --add-architecture i386\nsudo apt-get update\nsudo apt-get install libc6:i386\n\n# install other board packages\necho -n \"ADD OpenCR PACKAGE INDEX: \"\nDEPENDENCY_OUTPUT=$(arduino --pref \"boardsmanager.additional.urls=https://raw.githubusercontent.com/ROBOTIS-GIT/OpenCR/master/arduino/opencr_release/package_opencr_index.json\" --save-prefs 2>&1)\nif [ $? -ne 0 ]; then echo -e \"\\xe2\\x9c\\x96\"; else echo -e \"\\xe2\\x9c\\x93\"; fi\n\necho -n \"INSTALL OpenCR: \"\nDEPENDENCY_OUTPUT=$(arduino --install-boards OpenCR:OpenCR 2>&1)\nif [ $? -ne 0 ]; then echo -e \"\\xe2\\x9c\\x96\"; else echo -e \"\\xe2\\x9c\\x93\"; fi\n\n# Update OpenCR package manually\nif [ $1 == \"refs/heads/master\" ]; then\n  git clone --recursive https://github.com/ROBOTIS-GIT/OpenCR.git --branch master --single-branch\nelif [ $1 == \"refs/heads/develop\" ]; then\n  git clone --recursive https://github.com/ROBOTIS-GIT/OpenCR.git --branch develop --single-branch\nelse\n  echo -e \"\\xe2\\x9c\\x93\";\nfi\n\nrm -rf $HOME/.arduino15/packages/OpenCR/hardware\nmkdir $HOME/Arduino/hardware\nmkdir $HOME/Arduino/hardware/OpenCR\necho -n \"UPDATE OpenCR: \"\nDEPENDENCY_OUTPUT=$(mv $PWD/OpenCR/arduino/opencr_arduino/opencr $HOME/Arduino/hardware/OpenCR/OpenCR 2>&1)\nif [ $? -ne 0 ]; then echo -e \"\\xe2\\x9c\\x96\"; else echo -e \"\\xe2\\x9c\\x93\"; fi\n\n# install 3rd party libraries\ngit clone https://github.com/JonHub/Filters.git\necho -n \"INSTALL Filters Library: \"\nDEPENDENCY_OUTPUT=$(mv Filters $HOME/Arduino/libraries/Filters 2>&1)\nif [ $? -ne 0 ]; then echo -e \"\\xe2\\x9c\\x96\"; else echo -e \"\\xe2\\x9c\\x93\"; fi\n\n# install random lib so the arduino IDE grabs a new library index\n# see: https://github.com/arduino/Arduino/issues/3535\necho -n \"UPDATE LIBRARY INDEX: \"\nDEPENDENCY_OUTPUT=$(arduino --install-library USBHost > /dev/null 2>&1)\nif [ $? -ne 0 ]; then echo -e \"\\xe2\\x9c\\x96\"; else echo -e \"\\xe2\\x9c\\x93\"; fi\n\n# set the maximal compiler warning level\necho -n \"SET BUILD PREFERENCES: \"\nDEPENDENCY_OUTPUT=$(arduino --pref \"compiler.warning_level=all\" --save-prefs 2>&1)\nif [ $? -ne 0 ]; then echo -e \"\\xe2\\x9c\\x96\"; else echo -e \"\\xe2\\x9c\\x93\"; fi\n\n# init the json temp var for the current platform\nexport PLATFORM_JSON=\"\"\n\n# init test stats counters\nexport PASS_COUNT=0\nexport SKIP_COUNT=0\nexport FAIL_COUNT=0\nexport PDE_COUNT=0\n\n# build all of the examples for the passed platform\nfunction build_platform()\n{\n\n  # arrays can't be exported, so we have to eval\n  eval $MAIN_PLATFORMS\n  eval $AUX_PLATFORMS\n  eval $CPLAY_PLATFORMS\n\n  # reset platform json var\n  PLATFORM_JSON=\"\"\n\n  # expects argument 1 to be the platform key\n  local platform_key=$1\n\n  # placeholder for platform\n  local platform=\"\"\n\n  # track the exit code for this platform\n  local exit_code=0\n\n  # grab all pde and ino example sketches\n  declare -a examples\n\n  # loop through results and add them to the array\n  examples=($(find $HOME/Arduino/hardware/OpenCR/OpenCR/libraries/turtlebot3/examples -name \"*.pde\" -o -name \"*.ino\"))\n\n  # get the last example in the array\n  local last=\"${examples[@]:(-1)}\"\n\n  # grab the platform info from array or bail if invalid\n  if [[ ${main_platforms[$platform_key]} ]]; then\n    platform=${main_platforms[$platform_key]}\n  elif [[ ${aux_platforms[$platform_key]} ]]; then\n    platform=${aux_platforms[$platform_key]}\n  elif [[ ${cplay_platforms[$platform_key]} ]]; then\n    platform=${cplay_platforms[$platform_key]}\n  else\n    echo \"NON-STANDARD PLATFORM KEY: $platform_key\"\n    platform=$platform_key\n  fi\n\n  echo -e \"\\n########################################################################\";\n\n  echo -n \"SWITCHING TO ${platform_key}: \"\n\n  # switch to the requested board.\n  # we have to avoid reading the exit code of local:\n  # \"when declaring a local variable in a function, the local acts as a command in its own right\"\n  local platform_stdout\n  platform_stdout=$(arduino --board $platform --save-prefs 2>&1)\n\n  # grab the exit status of the arduino board change\n  local platform_switch=$?\n\n  # notify if the platform switch failed\n  if [ $platform_switch -ne 0 ]; then\n    # heavy X\n    echo -e \"\\xe2\\x9c\\x96\"\n    echo $platform_stdout\n    exit_code=1\n  else\n    # heavy checkmark\n    echo -e \"\\xe2\\x9c\\x93\"\n  fi\n\n  echo \"########################################################################\";\n\n  # loop through example sketches\n  for example in \"${examples[@]}\"; do\n\n    # store the full path to the example's sketch directory\n    local example_dir=$(dirname $example)\n\n    # store the filename for the example without the path\n    local example_file=$(basename $example)\n\n    # is this the last example in the loop\n    local last_example=0\n    if [ \"$last\" == \"$example\" ]; then\n      last_example=1\n    fi\n\n    echo -n \"$example_file: \"\n\n    # continue to next example if platform switch failed\n    if [ $platform_switch -ne 0 ]; then\n      # heavy X\n      echo -e \"\\xe2\\x9c\\x96\"\n\n      # add json\n      PLATFORM_JSON=\"${PLATFORM_JSON}$(json_sketch 0 $example_file $last_example)\"\n\n      # increment fails\n      FAIL_COUNT=$((FAIL_COUNT + 1))\n\n      # mark fail\n      exit_code=1\n\n      continue\n\n    fi\n\n    # ignore this example if there is an all platform skip\n    if [[ -f \"${example_dir}/.test.skip\" ]]; then\n\n      # right arrow\n      echo -e \"\\xe2\\x9e\\x9e\"\n\n      # add json\n      PLATFORM_JSON=\"${PLATFORM_JSON}$(json_sketch -1 $example_file $last_example)\"\n\n      # increment skips\n      SKIP_COUNT=$((SKIP_COUNT + 1))\n\n      continue\n\n    fi\n\n    # ignore this example if there is a skip file preset for this specific platform\n    if [[ -f \"${example_dir}/.${platform_key}.test.skip\" ]]; then\n\n      # right arrow\n      echo -e \"\\xe2\\x9e\\x9e\"\n\n      # add json\n      PLATFORM_JSON=\"${PLATFORM_JSON}$(json_sketch -1 $example_file $last_example)\"\n\n      # increment skips\n      SKIP_COUNT=$((SKIP_COUNT + 1))\n\n      continue\n    fi\n\n    # make sure that all examples are .ino files\n    if [[ $example =~ \\.pde$ ]]; then\n\n      # heavy X\n      echo -e \"\\xe2\\x9c\\x96\"\n\n      echo -e \"-------------------------- DEBUG OUTPUT --------------------------\\n\"\n      echo \"PDE EXTENSION. PLEASE UPDATE TO INO\"\n      echo -e \"\\n------------------------------------------------------------------\\n\"\n\n      # add json\n      PLATFORM_JSON=\"${PLATFORM_JSON}$(json_sketch 0 $example_file $last_example)\"\n\n      # increment fails\n      FAIL_COUNT=$((FAIL_COUNT + 1))\n\n      # mark as fail\n      exit_code=1\n\n      continue\n\n    fi\n\n    # verify the example, and save stdout & stderr to a variable\n    # we have to avoid reading the exit code of local:\n    # \"when declaring a local variable in a function, the local acts as a command in its own right\"\n    local build_stdout\n    build_stdout=$(arduino --verify $example 2>&1)\n\n    # echo output if the build failed\n    if [ $? -ne 0 ]; then\n\n      # heavy X\n      echo -e \"\\xe2\\x9c\\x96\"\n\n      echo -e \"----------------------------- DEBUG OUTPUT -----------------------------\\n\"\n      echo \"$build_stdout\"\n      echo -e \"\\n------------------------------------------------------------------------\\n\"\n\n      # add json\n      PLATFORM_JSON=\"${PLATFORM_JSON}$(json_sketch 0 $example_file $last_example)\"\n\n      # increment fails\n      FAIL_COUNT=$((FAIL_COUNT + 1))\n\n      # mark as fail\n      exit_code=1\n\n    else\n\n      # heavy checkmark\n      echo -e \"\\xe2\\x9c\\x93\"\n\n      # add json\n      PLATFORM_JSON=\"${PLATFORM_JSON}$(json_sketch 1 \"$example_file\" $last_example)\"\n\n      # increment passes\n      PASS_COUNT=$((PASS_COUNT + 1))\n\n    fi\n\n  done\n\n  return $exit_code\n\n}\n\n# build all examples for every platform in $main_platforms\nfunction build_main_platforms()\n{\n\n  # arrays can't be exported, so we have to eval\n  eval $MAIN_PLATFORMS\n\n  # track the build status all platforms\n  local exit_code=0\n\n  # var to hold platforms\n  local platforms_json=\"\"\n\n  # get the last element in the array\n  local last=\"${main_platforms[@]:(-1)}\"\n\n  # loop through platforms in main platforms assoc array\n  for p_key in \"${!main_platforms[@]}\"; do\n\n    # is this the last platform in the loop\n    local last_platform=0\n    if [ \"$last\" == \"${main_platforms[$p_key]}\" ]; then\n      last_platform=1\n    fi\n\n    # build all examples for this platform\n    build_platform $p_key\n\n    # check if build failed\n    if [ $? -ne 0 ]; then\n      platforms_json=\"${platforms_json}$(json_platform $p_key 0 \"$PLATFORM_JSON\" $last_platform)\"\n      exit_code=1\n    else\n      platforms_json=\"${platforms_json}$(json_platform $p_key 1 \"$PLATFORM_JSON\" $last_platform)\"\n    fi\n\n  done\n\n  # exit code is opposite of json build status\n  if [ $exit_code -eq 0 ]; then\n    json_main_platforms 1 \"$platforms_json\"\n  else\n    json_main_platforms 0 \"$platforms_json\"\n  fi\n\n  return $exit_code\n\n}\n\n\n# generate json string for a sketch\nfunction json_sketch()\n{\n\n  # -1: skipped, 0: failed, 1: passed\n  local status_number=$1\n\n  # the filename of the sketch\n  local sketch=$2\n\n  # is this the last sketch for this platform? 0: no, 1: yes\n  local last_sketch=$3\n\n  # echo out the json\n  echo -n \"\\\"$sketch\\\": $status_number\"\n\n  # echo a comma unless this is the last sketch for the platform\n  if [ $last_sketch -ne 1 ]; then\n    echo -n \", \"\n  fi\n\n}\n\n# generate json string for a platform\nfunction json_platform()\n{\n\n  # the platform key from main platforms or aux platforms\n  local platform_key=$1\n\n  # 0: failed, 1: passed\n  local status_number=$2\n\n  # the json string for the verified sketches\n  local sketch_json=$3\n\n  # is this the last platform we are building? 0: no, 1: yes\n  local last_platform=$4\n\n  echo -n \"\\\"$platform_key\\\": { \\\"status\\\": $status_number, \\\"builds\\\": { $sketch_json } }\"\n\n  # echo a comma unless this is the last sketch for the platform\n  if [ $last_platform -ne 1 ]; then\n    echo -n \", \"\n  fi\n\n}\n\n# generate final json string\nfunction json_main_platforms()\n{\n\n  # 0: failed, 1: passed\n  local status_number=$1\n\n  # the json string for the main platforms\n  local platforms_json=$2\n\n  local repo=$(git config --get remote.origin.url)\n\n  echo -e \"\\n||||||||||||||||||||||||||||| JSON STATUS ||||||||||||||||||||||||||||||\"\n\n  echo -n \"{ \\\"repo\\\": \\\"$repo\\\", \"\n  echo -n \"\\\"status\\\": $status_number, \"\n  echo -n \"\\\"passed\\\": $PASS_COUNT, \"\n  echo -n \"\\\"skipped\\\": $SKIP_COUNT, \"\n  echo -n \"\\\"failed\\\": $FAIL_COUNT, \"\n  echo \"\\\"platforms\\\": { $platforms_json } }\"\n\n  echo -e \"||||||||||||||||||||||||||||| JSON STATUS ||||||||||||||||||||||||||||||\\n\"\n\n}\n"
  }
]